data/full_repos/permissive/494905093/PUF/ROPUF/Register.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/494905093/PUF/ROPUF/Register.v:4: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input [0:15] In,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/494905093/PUF/ROPUF/Register.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n    input [0:7] count,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/494905093/PUF/ROPUF/Register.v:8: Little bit endian vector: MSB < LSB of bit range: 0:15\n    output reg [0:15] Out \n               ^\n%Error: Exiting due to 3 warning(s)\n'
module Register(
    input [0:15] In,
    input clk,
    input [0:7] count,
    input Reset,
    output reg [0:15] Out 
);

    always@( posedge clk )begin
        
        if( Reset )begin
            Out = 16'd0;
        end

        else begin
            if( count < 8'd240 )begin
                Out <= 16'd0;
            end
            else if( count == 8'd240)begin
                Out <= In;
            end
            else begin
                Out <= Out;
            end
        end

    end

endmodule
module Register(
    input [0:15] In,
    input clk,
    input [0:7] count,
    input Reset,
    output reg [0:15] Out 
);


    always@( posedge clk )begin
        
        if( Reset )begin
            Out = 16'd0;
        end

        else begin
            if( count < 8'd240 )begin
                Out <= 16'd0;
            end
            else if( count == 8'd240)begin
                Out <= In;
            end
            else begin
                Out <= Out;
            end
        end

    end

endmodule