data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:24: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.sv\n             ./const/parameters_cla.v\n             ./const/parameters_cla.v.v\n             ./const/parameters_cla.v.sv\n             obj_dir/./const/parameters_cla.v\n             obj_dir/./const/parameters_cla.v.v\n             obj_dir/./const/parameters_cla.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:55: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:76: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:106: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:125: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:146: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:172: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:200: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module DBLCTREE_16 ( PIN, GIN, PHI, GOUT, POUT );
`include "./const/parameters_cla.v"

input  [N_16-1:0] PIN;
input  [N_16:0] GIN;
input  PHI;
output [N_16:0] GOUT;
output [0:0] POUT;


   wire [N_16-2:0] INTPROP_0;
   wire [N_16:0] INTGEN_0;
   wire [N_16-4:0] INTPROP_1;
   wire [N_16:0] INTGEN_1;
   wire [N_16-8:0] INTPROP_2;
   wire [N_16:0] INTGEN_2;






  
   DBLC_0_16 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );   
   DBLC_1_16 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
   DBLC_2_16 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
   DBLC_3_16 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );

endmodule
module DBLCTREE_16 ( PIN, GIN, PHI, GOUT, POUT );

`include "./const/parameters_cla.v"

input  [N_16-1:0] PIN;
input  [N_16:0] GIN;
input  PHI;
output [N_16:0] GOUT;
output [0:0] POUT;


   wire [N_16-2:0] INTPROP_0;
   wire [N_16:0] INTGEN_0;
   wire [N_16-4:0] INTPROP_1;
   wire [N_16:0] INTGEN_1;
   wire [N_16-8:0] INTPROP_2;
   wire [N_16:0] INTGEN_2;






  
   DBLC_0_16 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );   
   DBLC_1_16 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
   DBLC_2_16 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
   DBLC_3_16 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );

endmodule