data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:1: Cannot find include file: Register.v\n`include"Register.v" \n        ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Register.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Register.v.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Register.v.sv\n             Register.v\n             Register.v.v\n             Register.v.sv\n             obj_dir/Register.v\n             obj_dir/Register.v.v\n             obj_dir/Register.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("Register.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,clk,icode,cnd,rA,rB,valE,valM,valA,valB);\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:29: Too many digits for 32 bit number: \'h3424867AEC\n valE=j+\'h3424867AEC;  \n        ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/Register_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module testbench;
reg [3:0] icode;
reg cnd;
reg [3:0] rA;
reg [3:0] rB;
reg [63:0] valE;
reg [63:0] valM;
reg clk;
wire [63:0] valA;
wire [63:0] valB;


	integer i,k,j;
	Register DUT(icode,cnd,rA,rB,valA,valB,valE,valM,clk);
	initial begin

	$dumpfile("Register.vcd");
    	$dumpvars(0,clk,icode,cnd,rA,rB,valE,valM,valA,valB);
	clk=0;
	icode=4'hB;
	rA=4'h2;
	rB=4'h7;
	cnd=0;


	for(j=0;j<4;j++) begin 
	valE=j+'h3424867AEC;
	valM='h6567;
	clk=1;
	#10;
	clk=0;
	#10;
	end
end
endmodule
module testbench;

reg [3:0] icode;
reg cnd;
reg [3:0] rA;
reg [3:0] rB;
reg [63:0] valE;
reg [63:0] valM;
reg clk;
wire [63:0] valA;
wire [63:0] valB;


	integer i,k,j;
	Register DUT(icode,cnd,rA,rB,valA,valB,valE,valM,clk);
	initial begin

	$dumpfile("Register.vcd");
    	$dumpvars(0,clk,icode,cnd,rA,rB,valE,valM,valA,valB);
	clk=0;
	icode=4'hB;
	rA=4'h2;
	rB=4'h7;
	cnd=0;


	for(j=0;j<4;j++) begin 
	valE=j+'h3424867AEC;
	valM='h6567;
	clk=1;
	#10;
	clk=0;
	#10;
	end
end
endmodule