data/full_repos/permissive/50700015/spl2_write_through/fifo/spl_fifo.v
1: b'%Error: data/full_repos/permissive/50700015/spl2_write_through/fifo/spl_fifo.v:61: Cannot find file containing module: \'spl_sdp_mem\'\n    spl_sdp_mem #(.DATA_WIDTH(FIFO_WIDTH),\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50700015/spl2_write_through/fifo,data/full_repos/permissive/50700015/spl_sdp_mem\n             data/full_repos/permissive/50700015/spl2_write_through/fifo,data/full_repos/permissive/50700015/spl_sdp_mem.v\n             data/full_repos/permissive/50700015/spl2_write_through/fifo,data/full_repos/permissive/50700015/spl_sdp_mem.sv\n             spl_sdp_mem\n             spl_sdp_mem.v\n             spl_sdp_mem.sv\n             obj_dir/spl_sdp_mem\n             obj_dir/spl_sdp_mem.v\n             obj_dir/spl_sdp_mem.sv\n%Warning-WIDTH: data/full_repos/permissive/50700015/spl2_write_through/fifo/spl_fifo.v:132: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                          : ... In instance spl_fifo\n                if (count == 1\'b1)\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module spl_fifo #(
    parameter FIFO_WIDTH = 32,
    parameter FIFO_DEPTH_BITS = 8,
    parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
) (
    input  wire                         clk,
    input  wire                         reset_n,
    
    input  wire                         we,
    input  wire [FIFO_WIDTH - 1:0]      din,

    input  wire                         re,
    output reg                          valid,
    output reg  [FIFO_WIDTH - 1:0]      dout,

    output reg  [FIFO_DEPTH_BITS - 1:0] count,
    output reg                          empty,
    output reg                          full,
    output reg                          almostfull
);


    reg     overflow;
        
    reg  [FIFO_DEPTH_BITS - 1:0]        rp;
    reg  [FIFO_DEPTH_BITS - 1:0]        wp;
    reg                                 empty_d1;
    
    wire                                mem_we;
    reg                                 mem_re;
    wire [FIFO_WIDTH - 1:0]             mem_dout;
    
        
    spl_sdp_mem #(.DATA_WIDTH(FIFO_WIDTH),
                  .ADDR_WIDTH(FIFO_DEPTH_BITS)) spl_fifo_mem( 
        .clk        (clk),
        .we         (mem_we),
		.re 		(re),
        .raddr      (rp),
        .waddr      (wp),
        .din        (din),
        .dout       (mem_dout)
    );
             
        
    assign mem_we = we & ((~re) | (~empty) | mem_re);
            
    always @(posedge clk) begin
        if (~reset_n) begin
            empty <= 1'b1;
            empty_d1 <= 1'b1;
            full <= 1'b0;
            almostfull <= 1'b0;
            count <= 'b0;
            rp <= 'b0;
            wp <= 'b0;
            valid <= 1'b0;
            mem_re <= 1'b0;
            
            overflow <= 1'b0;
        end
        
        else begin
            empty_d1 <= empty;
            valid <= 1'b0;
            mem_re <= 1'b0;
            

            if (we & re & empty & (~mem_re)) begin
                valid <= 1'b1;
                dout <= din;
            end
            

            if (we & re & (~empty)) begin
                wp <= wp + 1'b1;                    
                rp <= rp + 1'b1;
                mem_re <= 1'b1;
            end
                                        

            if (we & ((~re) | (re & empty & mem_re))) begin
                wp <= wp + 1'b1;
                count <= count + 1'b1;

                empty <= 1'b0;

                if (count == (2**FIFO_DEPTH_BITS-1))
                    full <= 1'b1;

                if (count == (FIFO_ALMOSTFULL_THRESHOLD-1))
                    almostfull <= 1'b1;
            end
            

            if ((~we) & re & (~empty)) begin
                rp <= rp + 1'b1;
                count <= count - 1'b1;                    
                full <= 1'b0;
                mem_re <= 1'b1;
                
                if (count == FIFO_ALMOSTFULL_THRESHOLD)
                    almostfull <= 1'b0;

                if (count == 1'b1)
                    empty <= 1'b1; 
            end
                       
            if (mem_re) begin
                valid <= 1'b1;  
                dout <= mem_dout;                                                          
            end   


            if (reset_n === 1'b1) begin                  
                assert (~(we & (~re) & full)) else $fatal("overflow");   
				assert ((we & re &(wp == rp) & (~empty)) == 1'b0) else 
				    $fatal("read-during-write at same time to location %x", wp);
			end

        end
    end

endmodule
module spl_fifo #(
    parameter FIFO_WIDTH = 32,
    parameter FIFO_DEPTH_BITS = 8,
    parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
) (
    input  wire                         clk,
    input  wire                         reset_n,
    
    input  wire                         we,
    input  wire [FIFO_WIDTH - 1:0]      din,

    input  wire                         re,
    output reg                          valid,
    output reg  [FIFO_WIDTH - 1:0]      dout,

    output reg  [FIFO_DEPTH_BITS - 1:0] count,
    output reg                          empty,
    output reg                          full,
    output reg                          almostfull
);



    reg     overflow;
        
    reg  [FIFO_DEPTH_BITS - 1:0]        rp;
    reg  [FIFO_DEPTH_BITS - 1:0]        wp;
    reg                                 empty_d1;
    
    wire                                mem_we;
    reg                                 mem_re;
    wire [FIFO_WIDTH - 1:0]             mem_dout;
    
        
    spl_sdp_mem #(.DATA_WIDTH(FIFO_WIDTH),
                  .ADDR_WIDTH(FIFO_DEPTH_BITS)) spl_fifo_mem( 
        .clk        (clk),
        .we         (mem_we),
		.re 		(re),
        .raddr      (rp),
        .waddr      (wp),
        .din        (din),
        .dout       (mem_dout)
    );
             
        
    assign mem_we = we & ((~re) | (~empty) | mem_re);
            
    always @(posedge clk) begin
        if (~reset_n) begin
            empty <= 1'b1;
            empty_d1 <= 1'b1;
            full <= 1'b0;
            almostfull <= 1'b0;
            count <= 'b0;
            rp <= 'b0;
            wp <= 'b0;
            valid <= 1'b0;
            mem_re <= 1'b0;
            
            overflow <= 1'b0;
        end
        
        else begin
            empty_d1 <= empty;
            valid <= 1'b0;
            mem_re <= 1'b0;
            

            if (we & re & empty & (~mem_re)) begin
                valid <= 1'b1;
                dout <= din;
            end
            

            if (we & re & (~empty)) begin
                wp <= wp + 1'b1;                    
                rp <= rp + 1'b1;
                mem_re <= 1'b1;
            end
                                        

            if (we & ((~re) | (re & empty & mem_re))) begin
                wp <= wp + 1'b1;
                count <= count + 1'b1;

                empty <= 1'b0;

                if (count == (2**FIFO_DEPTH_BITS-1))
                    full <= 1'b1;

                if (count == (FIFO_ALMOSTFULL_THRESHOLD-1))
                    almostfull <= 1'b1;
            end
            

            if ((~we) & re & (~empty)) begin
                rp <= rp + 1'b1;
                count <= count - 1'b1;                    
                full <= 1'b0;
                mem_re <= 1'b1;
                
                if (count == FIFO_ALMOSTFULL_THRESHOLD)
                    almostfull <= 1'b0;

                if (count == 1'b1)
                    empty <= 1'b1; 
            end
                       
            if (mem_re) begin
                valid <= 1'b1;  
                dout <= mem_dout;                                                          
            end   


            if (reset_n === 1'b1) begin                  
                assert (~(we & (~re) & full)) else $fatal("overflow");   
				assert ((we & re &(wp == rp) & (~empty)) == 1'b0) else 
				    $fatal("read-during-write at same time to location %x", wp);
			end

        end
    end

endmodule