data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/counter1_TB.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/counter1_TB.v\n%Error: Exiting due to 7 error(s)\n'
module counter1_TB;

reg CLOCK;
reg RESET;

wire control_signal;


counter1 CTR(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.control_signal(control_signal)
	);


always
  #20 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("counter1_TB.vcd") ;
  $dumpvars(0, counter1_TB) ;
end


initial
begin
		CLOCK  = 0 ;
		RESET  = 1 ;
  #40 	RESET  = 0 ;


  #10000 $finish ; 
end
 
endmodule
module counter1_TB;


reg CLOCK;
reg RESET;

wire control_signal;


counter1 CTR(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.control_signal(control_signal)
	);


always
  #20 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("counter1_TB.vcd") ;
  $dumpvars(0, counter1_TB) ;
end


initial
begin
		CLOCK  = 0 ;
		RESET  = 1 ;
  #40 	RESET  = 0 ;


  #10000 $finish ; 
end
 
endmodule