data/full_repos/permissive/514217463/core/rtl/mc6850.v
1: b"%Error: data/full_repos/permissive/514217463/core/rtl/mc6850.v:22: Cannot find file containing module: 'simpleuart'\n  simpleuart uart(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514217463/core/rtl,data/full_repos/permissive/514217463/simpleuart\n             data/full_repos/permissive/514217463/core/rtl,data/full_repos/permissive/514217463/simpleuart.v\n             data/full_repos/permissive/514217463/core/rtl,data/full_repos/permissive/514217463/simpleuart.sv\n             simpleuart\n             simpleuart.v\n             simpleuart.sv\n             obj_dir/simpleuart\n             obj_dir/simpleuart.v\n             obj_dir/simpleuart.sv\n%Error: Exiting due to 1 error(s)\n"
module mc6850(
  input clk,
  input reset,
  input addr,
  input [7:0] data_in,
  input rd,
  input we,
  output reg [7:0] data_out,
  input ce,
  input rx,
  output tx
);

  parameter CLOCK = 2000000;
  parameter BAUD  = 19200;
  
  wire valid;
  wire tdre;
  wire [7:0] uart_out;
  wire dat_wait;
  
  simpleuart uart(
	.clk(clk),
	.resetn(~reset),

	.ser_tx(tx),
	.ser_rx(rx),

	.cfg_divider(CLOCK/BAUD),

	.reg_dat_we(we && (addr==1'b1)),
	.reg_dat_re(rd && (addr==1'b1)),
	.reg_dat_di(data_in & 8'h7f),
	.reg_dat_do(uart_out),
	.reg_dat_wait(dat_wait),
	.recv_buf_valid(valid),
	.tdre(tdre)
);

  always @(posedge clk)
  begin
	  `ifdef DEBUG
		if (we)
		begin
			if (addr==1'b1 && ce)
				$write("%c",data_in);
		end
		`endif

		if (rd)
		begin
			if (addr==1'b0)
				data_out <= { 2'b00,valid, 1'b0,   2'b00, tdre, valid };
			else 
				data_out <= uart_out;
		end
  end
endmodule
module mc6850(
  input clk,
  input reset,
  input addr,
  input [7:0] data_in,
  input rd,
  input we,
  output reg [7:0] data_out,
  input ce,
  input rx,
  output tx
);


  parameter CLOCK = 2000000;
  parameter BAUD  = 19200;
  
  wire valid;
  wire tdre;
  wire [7:0] uart_out;
  wire dat_wait;
  
  simpleuart uart(
	.clk(clk),
	.resetn(~reset),

	.ser_tx(tx),
	.ser_rx(rx),

	.cfg_divider(CLOCK/BAUD),

	.reg_dat_we(we && (addr==1'b1)),
	.reg_dat_re(rd && (addr==1'b1)),
	.reg_dat_di(data_in & 8'h7f),
	.reg_dat_do(uart_out),
	.reg_dat_wait(dat_wait),
	.recv_buf_valid(valid),
	.tdre(tdre)
);

  always @(posedge clk)
  begin
	  `ifdef DEBUG
		if (we)
		begin
			if (addr==1'b1 && ce)
				$write("%c",data_in);
		end
		`endif

		if (rd)
		begin
			if (addr==1'b0)
				data_out <= { 2'b00,valid, 1'b0,   2'b00, tdre, valid };
			else 
				data_out <= uart_out;
		end
  end
endmodule