data/full_repos/permissive/42434302/ivltests/pr1855504.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1855504.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1855504.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #5 $finish;\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mul_test();

   reg [15:0] prod;
   reg [7:0]  op2;
   reg [15:0] op1;


   initial begin
      op1 = 16'h0DA0;
      op2 = 8'h0A;
      prod = 16'h0000;
   end

   always begin
      prod <= op1[7:0] * op2;
      #5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod);
      #5 $finish;
   end

endmodule
module mul_test();


   reg [15:0] prod;
   reg [7:0]  op2;
   reg [15:0] op1;


   initial begin
      op1 = 16'h0DA0;
      op2 = 8'h0A;
      prod = 16'h0000;
   end

   always begin
      prod <= op1[7:0] * op2;
      #5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod);
      #5 $finish;
   end

endmodule