data/full_repos/permissive/419677538/Exercise_1/verilog_code/EightBitRippleCarryAdder.v
1: b"%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/EightBitRippleCarryAdder.v:6: Cannot find file containing module: 'FourBitRippleCarryAdder'\n   FourBitRippleCarryAdder fbrca1(a[3:0],b[3:0],cstart,c[4:0]);\n   ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder.v\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder.sv\n             FourBitRippleCarryAdder\n             FourBitRippleCarryAdder.v\n             FourBitRippleCarryAdder.sv\n             obj_dir/FourBitRippleCarryAdder\n             obj_dir/FourBitRippleCarryAdder.v\n             obj_dir/FourBitRippleCarryAdder.sv\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/EightBitRippleCarryAdder.v:7: Cannot find file containing module: 'FourBitRippleCarryAdder'\n   FourBitRippleCarryAdder fbrca2(a[7:4],b[7:4],c[4],c[9:5]);  \n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module EightBitRippleCarryAdder(a,b,cstart,s);
   output [8:0] s;
   input [7:0] a,b;
   input cstart;
   wire [9:0] c;
   FourBitRippleCarryAdder fbrca1(a[3:0],b[3:0],cstart,c[4:0]);
   FourBitRippleCarryAdder fbrca2(a[7:4],b[7:4],c[4],c[9:5]);  
   assign s[3:0]=c[3:0];
   assign s[8:4]=c[9:5];
endmodule
module EightBitRippleCarryAdder(a,b,cstart,s);

   output [8:0] s;
   input [7:0] a,b;
   input cstart;
   wire [9:0] c;
   FourBitRippleCarryAdder fbrca1(a[3:0],b[3:0],cstart,c[4:0]);
   FourBitRippleCarryAdder fbrca2(a[7:4],b[7:4],c[4],c[9:5]);  
   assign s[3:0]=c[3:0];
   assign s[8:4]=c[9:5];
endmodule