data/full_repos/permissive/428158935/sources_1/new/TruncateModule.v
1: b"%Error: data/full_repos/permissive/428158935/sources_1/new/TruncateModule.v:15: Duplicate declaration of signal: 'judge'\n                                                                              : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire [31:0] judge;\n            ^~~~~\n        data/full_repos/permissive/428158935/sources_1/new/TruncateModule.v:4: ... Location of original declaration\n    output [31:0] judge\n                  ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module CutR (
    input dir,
    input [31:0] a,
    input [31:0] judge,
    output  [31:0] s
);

wire [31:0] tmp;
wire in_put;
not (in_put,dir);
or (tmp[31],in_put,judge[31]);
or (tmp[30],tmp[31],judge[30]);
or (tmp[29],tmp[30],judge[29]);
or (tmp[28],tmp[29],judge[28]);
or (tmp[27],tmp[28],judge[27]);
or (tmp[26],tmp[27],judge[26]);
or (tmp[25],tmp[26],judge[25]);
or (tmp[24],tmp[25],judge[24]);
or (tmp[23],tmp[24],judge[23]);
or (tmp[22],tmp[23],judge[22]);
or (tmp[21],tmp[22],judge[21]);
or (tmp[20],tmp[21],judge[20]);
or (tmp[19],tmp[20],judge[19]);
or (tmp[18],tmp[19],judge[18]);
or (tmp[17],tmp[18],judge[17]);
or (tmp[16],tmp[17],judge[16]);
or (tmp[15],tmp[16],judge[15]);
or (tmp[14],tmp[15],judge[14]);
or (tmp[13],tmp[14],judge[13]);
or (tmp[12],tmp[13],judge[12]);
or (tmp[11],tmp[12],judge[11]);
or (tmp[10],tmp[11],judge[10]);
or (tmp[9],tmp[10],judge[9]);
or (tmp[8],tmp[9],judge[8]);
or (tmp[7],tmp[8],judge[7]);
or (tmp[6],tmp[7],judge[6]);
or (tmp[5],tmp[6],judge[5]);
or (tmp[4],tmp[5],judge[4]);
or (tmp[3],tmp[4],judge[3]);
or (tmp[2],tmp[3],judge[2]);
or (tmp[1],tmp[2],judge[1]);
or (tmp[0],tmp[1],judge[0]);


and (s[31],tmp[31],a[31],dir);
and (s[30],tmp[30],a[30],dir);
and (s[29],tmp[29],a[29],dir);
and (s[28],tmp[28],a[28],dir);
and (s[27],tmp[27],a[27],dir);
and (s[26],tmp[26],a[26],dir);
and (s[25],tmp[25],a[25],dir);
and (s[24],tmp[24],a[24],dir);
and (s[23],tmp[23],a[23],dir);
and (s[22],tmp[22],a[22],dir);
and (s[21],tmp[21],a[21],dir);
and (s[20],tmp[20],a[20],dir);
and (s[19],tmp[19],a[19],dir);
and (s[18],tmp[18],a[18],dir);
and (s[17],tmp[17],a[17],dir);
and (s[16],tmp[16],a[16],dir);
and (s[15],tmp[15],a[15],dir);
and (s[14],tmp[14],a[14],dir);
and (s[13],tmp[13],a[13],dir);
and (s[12],tmp[12],a[12],dir);
and (s[11],tmp[11],a[11],dir);
and (s[10],tmp[10],a[10],dir);
and (s[9],tmp[9],a[9],dir);
and (s[8],tmp[8],a[8],dir);
and (s[7],tmp[7],a[7],dir);
and (s[6],tmp[6],a[6],dir);
and (s[5],tmp[5],a[5],dir);
and (s[4],tmp[4],a[4],dir);
and (s[3],tmp[3],a[3],dir);
and (s[2],tmp[2],a[2],dir);
and (s[1],tmp[1],a[1],dir);
and (s[0],tmp[0],a[0],dir);
endmodule
module CutR (
    input dir,
    input [31:0] a,
    input [31:0] judge,
    output  [31:0] s
);


wire [31:0] tmp;
wire in_put;
not (in_put,dir);
or (tmp[31],in_put,judge[31]);
or (tmp[30],tmp[31],judge[30]);
or (tmp[29],tmp[30],judge[29]);
or (tmp[28],tmp[29],judge[28]);
or (tmp[27],tmp[28],judge[27]);
or (tmp[26],tmp[27],judge[26]);
or (tmp[25],tmp[26],judge[25]);
or (tmp[24],tmp[25],judge[24]);
or (tmp[23],tmp[24],judge[23]);
or (tmp[22],tmp[23],judge[22]);
or (tmp[21],tmp[22],judge[21]);
or (tmp[20],tmp[21],judge[20]);
or (tmp[19],tmp[20],judge[19]);
or (tmp[18],tmp[19],judge[18]);
or (tmp[17],tmp[18],judge[17]);
or (tmp[16],tmp[17],judge[16]);
or (tmp[15],tmp[16],judge[15]);
or (tmp[14],tmp[15],judge[14]);
or (tmp[13],tmp[14],judge[13]);
or (tmp[12],tmp[13],judge[12]);
or (tmp[11],tmp[12],judge[11]);
or (tmp[10],tmp[11],judge[10]);
or (tmp[9],tmp[10],judge[9]);
or (tmp[8],tmp[9],judge[8]);
or (tmp[7],tmp[8],judge[7]);
or (tmp[6],tmp[7],judge[6]);
or (tmp[5],tmp[6],judge[5]);
or (tmp[4],tmp[5],judge[4]);
or (tmp[3],tmp[4],judge[3]);
or (tmp[2],tmp[3],judge[2]);
or (tmp[1],tmp[2],judge[1]);
or (tmp[0],tmp[1],judge[0]);


and (s[31],tmp[31],a[31],dir);
and (s[30],tmp[30],a[30],dir);
and (s[29],tmp[29],a[29],dir);
and (s[28],tmp[28],a[28],dir);
and (s[27],tmp[27],a[27],dir);
and (s[26],tmp[26],a[26],dir);
and (s[25],tmp[25],a[25],dir);
and (s[24],tmp[24],a[24],dir);
and (s[23],tmp[23],a[23],dir);
and (s[22],tmp[22],a[22],dir);
and (s[21],tmp[21],a[21],dir);
and (s[20],tmp[20],a[20],dir);
and (s[19],tmp[19],a[19],dir);
and (s[18],tmp[18],a[18],dir);
and (s[17],tmp[17],a[17],dir);
and (s[16],tmp[16],a[16],dir);
and (s[15],tmp[15],a[15],dir);
and (s[14],tmp[14],a[14],dir);
and (s[13],tmp[13],a[13],dir);
and (s[12],tmp[12],a[12],dir);
and (s[11],tmp[11],a[11],dir);
and (s[10],tmp[10],a[10],dir);
and (s[9],tmp[9],a[9],dir);
and (s[8],tmp[8],a[8],dir);
and (s[7],tmp[7],a[7],dir);
and (s[6],tmp[6],a[6],dir);
and (s[5],tmp[5],a[5],dir);
and (s[4],tmp[4],a[4],dir);
and (s[3],tmp[3],a[3],dir);
and (s[2],tmp[2],a[2],dir);
and (s[1],tmp[1],a[1],dir);
and (s[0],tmp[0],a[0],dir);
endmodule