data/full_repos/permissive/468612001/Week02/multiplexer2/multiplexer2.v
data/verilator_xmls/23c97b12-89cf-4226-883d-9cffe28ae833.xml
module multiplexer2(a, b, sel, out);
	input a, b, sel;
	output out;
	reg out;
	
	always @ (a, b, sel) begin
		if (sel) out = b;
		else out = a;
	end
	
endmodule
module multiplexer2(a, b, sel, out);

	input a, b, sel;
	output out;
	reg out;
	
	always @ (a, b, sel) begin
		if (sel) out = b;
		else out = a;
	end
	
endmodule