data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module subreg(
	input clk,
	input rst,
	
	input save,
	
	input setBank,
	input bank,
	
	input[15:0] f_reg,
	
	output reg[15:0] s_reg1
);

reg[15:0] f_reg1;


always@(posedge clk or posedge rst)begin
	if(rst) s_reg1 <= 0;
	else s_reg1 <= f_reg1;
end


always@(*)begin
	f_reg1 = s_reg1;
	if(bank == setBank && save) f_reg1 = f_reg;
end


endmodule
module subreg(
	input clk,
	input rst,
	
	input save,
	
	input setBank,
	input bank,
	
	input[15:0] f_reg,
	
	output reg[15:0] s_reg1
);


reg[15:0] f_reg1;


always@(posedge clk or posedge rst)begin
	if(rst) s_reg1 <= 0;
	else s_reg1 <= f_reg1;
end


always@(*)begin
	f_reg1 = s_reg1;
	if(bank == setBank && save) f_reg1 = f_reg;
end


endmodule