data/full_repos/permissive/43339463/memory.v
1: b'%Error: data/full_repos/permissive/43339463/memory.v:34: Unsupported or unknown PLI call: $monitor\n  $monitor("%t: rw = %b, addr = %x, wline = %x, rline = %x", $time, rw, addr, wline, rline);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:64: Unsupported: Ignoring delay on this delayed statement.\n always #10 begin\n        ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory(input clk, input [31:0] idata, output [47:0] odata, input [15:0] addr, input [1:0] rw);
	reg [7:0] data [0:2**16-1];
	
	initial $readmemb("mem_init.txt", data);
	
	always @(clk) begin
		case (rw)
			2'b01 : begin
				data[addr] <= idata;
			end
			2'b10 : begin
				{data[addr], data[addr + 1] } <= idata;
			end
			2'b11 : begin
				{data[addr], data[addr + 1], data[addr + 2], data[addr + 3] } <= idata;
			end
		endcase
	end
	
	assign odata = {data[addr], data[addr + 1], data[addr + 2], data[addr + 3], data[addr + 4], data[addr + 5] };
endmodule
module memory(input clk, input [31:0] idata, output [47:0] odata, input [15:0] addr, input [1:0] rw);

	reg [7:0] data [0:2**16-1];
	
	initial $readmemb("mem_init.txt", data);
	
	always @(clk) begin
		case (rw)
			2'b01 : begin
				data[addr] <= idata;
			end
			2'b10 : begin
				{data[addr], data[addr + 1] } <= idata;
			end
			2'b11 : begin
				{data[addr], data[addr + 1], data[addr + 2], data[addr + 3] } <= idata;
			end
		endcase
	end
	
	assign odata = {data[addr], data[addr + 1], data[addr + 2], data[addr + 3], data[addr + 4], data[addr + 5] };
endmodule