data/full_repos/permissive/507312280/tb/tb_core.sv
1: b'%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:2: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/tb,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/tb,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/tb,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:41: Unsupported: Ignoring delay on this delayed statement.\n    forever #(5) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:47: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:86: Unsupported: Ignoring delay on this delayed statement.\n    #300000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:99: Unsupported: Ignoring delay on this delayed statement.\n    #30;\n    ^\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:100: Unsupported: wait statements\n    wait(mends === 1\'b1) \n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:102: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:114: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:112: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:118: Unsupported: Ignoring delay on this delayed statement.\n    #15000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:120: Unsupported: Ignoring delay on this delayed statement.\n    #30;\n    ^\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:121: Unsupported: wait statements\n    wait(core_ex_trap_ready);\n    ^~~~\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:129: Unsupported: Verilog 1995 strength specifiers\n        assign (weak1,weak0) fpioa[i] = 1\'b0;\n                ^~~~~\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:129: Unsupported: Verilog 1995 strength specifiers\n        assign (weak1,weak0) fpioa[i] = 1\'b0;\n                      ^~~~~\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:135: Unsupported: wait statements\n    wait(rst_n===1\'b1);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/507312280/tb/tb_core.sv:138: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:172: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.vcd");   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/tb/tb_core.sv:173: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,tb_core);    \n    ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 10 warning(s)\n'
module tb_core(); 
`define CorePath inst_sparrow_soc.inst_core

logic clk;
logic rst_n;
logic core_ex_trap_valid, core_ex_trap_ready;
logic JTAG_TCK,JTAG_TMS,JTAG_TDI,JTAG_TDO;
wire spi0_miso;
wire [31:0]fpioa;
wire uart0_rx=1'b1;
assign fpioa[0]=uart0_rx;
wire uart0_tx=fpioa[1];
wire spi0_cs=fpioa[2];
assign fpioa[3]=spi0_miso;
wire spi0_mosi=fpioa[4];
wire spi0_clk=fpioa[5];

assign fpioa[20] = 1'b0;
assign fpioa[21] = 1'b1;
assign fpioa[31] = 1'b1;

integer r;

wire [31:0] x3  = `CorePath.inst_regs.regs[3];
wire [31:0] x26 = `CorePath.inst_regs.regs[26];
wire [31:0] x27 = `CorePath.inst_regs.regs[27];
wire mends = `CorePath.inst_csr.mends;


initial begin
    $readmemh ("inst.txt", `CorePath.inst_iram.inst_appram.BRAM);
    $readmemh ("btrm.txt", `CorePath.inst_iram.inst_bootrom.BRAM);
end


initial begin
    clk = '0;
    forever #(5) clk = ~clk;
end


initial begin
    sysrst();
    #10;


`ifdef ISA_TEST
    wait(x26 == 32'b1);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    if (x27 == 32'b1) begin
    $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~ #####     ##     ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~ #    #   #  #   #       #     ~~~~~~~~~");
    $display("~~~~~~~~~ #    #  #    #   ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~ #####   ######       #       #~~~~~~~~~");
    $display("~~~~~~~~~ #       #    #  #    #  #    #~~~~~~~~~");
    $display("~~~~~~~~~ #       #    #   ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    end else begin
    $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~######    ##       #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#        #  #      #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#####   #    #     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       ######     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       #    #     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       #    #     #    ######~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("fail testnum = %2d", x3);
    for (r = 1; r < 32; r = r + 1)
        $display("x%2d = 0x%x", r, `CorePath.inst_regs.regs[r]);
    end
    $stop;
`endif

end

initial begin
`ifndef MODELSIM
    #300000;
`else 
    #3000000;
`endif
`ifdef ISA_TEST
    $display("*Sim tool:ISA_TEST Timeout, Err");
`else 
    $display("*Sim tool:Normal Sim Timeout");
`endif
    $stop;
end

initial begin
    #30;
    wait(mends === 1'b1)
    $display("*Sim tool:CSR MENDS END, stop sim");
    #10;
    $stop;
end

task sysrst;
    core_ex_trap_valid=0;
    JTAG_TCK=0;
    JTAG_TMS=0;
    JTAG_TDI=0;

    #15

    #10;
endtask : sysrst

task ex_trap;
    #15000;
    core_ex_trap_valid=1;
    #30;
    wait(core_ex_trap_ready);
    core_ex_trap_valid=0;
endtask : ex_trap


genvar i;
generate
    for ( i=0; i <32 ; i++) begin
        assign (weak1,weak0) fpioa[i] = 1'b0;
    end
endgenerate


initial begin
    wait(rst_n===1'b1);
    if(`CorePath.inst_iram.inst_appram.BRAM[0][0]===1'bx) begin
        $display("*Sim tool:Inst load error");
        #10;
        $stop;
    end
end
sparrow_soc inst_sparrow_soc (
    .clk               (clk), 
    .hard_rst_n        (rst_n), 

    .JTAG_TCK          (JTAG_TCK),
    .JTAG_TMS          (JTAG_TMS),
    .JTAG_TDI          (JTAG_TDI),
    .JTAG_TDO          (JTAG_TDO),

    .fpioa             (fpioa),

    .core_ex_trap_valid(core_ex_trap_valid),
    .core_ex_trap_ready(core_ex_trap_ready)
);

`ifdef Flash25
pullup(WPn);
pullup(HOLDn);
W25Q128JVxIM inst_W25Q128JVxIM (
    .CSn   (spi0_cs),
    .CLK   (spi0_clk),
    .DIO   (spi0_mosi),
    .DO    (spi0_miso),
    .WPn   (WPn),
    .HOLDn (HOLDn)
);
`endif


initial begin
    $dumpfile("tb.vcd");
    $dumpvars(0,tb_core);
end


endmodule
module tb_core();
 
`define CorePath inst_sparrow_soc.inst_core

logic clk;
logic rst_n;
logic core_ex_trap_valid, core_ex_trap_ready;
logic JTAG_TCK,JTAG_TMS,JTAG_TDI,JTAG_TDO;
wire spi0_miso;
wire [31:0]fpioa;
wire uart0_rx=1'b1;
assign fpioa[0]=uart0_rx;
wire uart0_tx=fpioa[1];
wire spi0_cs=fpioa[2];
assign fpioa[3]=spi0_miso;
wire spi0_mosi=fpioa[4];
wire spi0_clk=fpioa[5];

assign fpioa[20] = 1'b0;
assign fpioa[21] = 1'b1;
assign fpioa[31] = 1'b1;

integer r;

wire [31:0] x3  = `CorePath.inst_regs.regs[3];
wire [31:0] x26 = `CorePath.inst_regs.regs[26];
wire [31:0] x27 = `CorePath.inst_regs.regs[27];
wire mends = `CorePath.inst_csr.mends;


initial begin
    $readmemh ("inst.txt", `CorePath.inst_iram.inst_appram.BRAM);
    $readmemh ("btrm.txt", `CorePath.inst_iram.inst_bootrom.BRAM);
end


initial begin
    clk = '0;
    forever #(5) clk = ~clk;
end


initial begin
    sysrst();
    #10;


`ifdef ISA_TEST
    wait(x26 == 32'b1);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    if (x27 == 32'b1) begin
    $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~ #####     ##     ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~ #    #   #  #   #       #     ~~~~~~~~~");
    $display("~~~~~~~~~ #    #  #    #   ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~ #####   ######       #       #~~~~~~~~~");
    $display("~~~~~~~~~ #       #    #  #    #  #    #~~~~~~~~~");
    $display("~~~~~~~~~ #       #    #   ####    #### ~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    end else begin
    $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("~~~~~~~~~~######    ##       #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#        #  #      #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#####   #    #     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       ######     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       #    #     #    #     ~~~~~~~~~~");
    $display("~~~~~~~~~~#       #    #     #    ######~~~~~~~~~~");
    $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    $display("fail testnum = %2d", x3);
    for (r = 1; r < 32; r = r + 1)
        $display("x%2d = 0x%x", r, `CorePath.inst_regs.regs[r]);
    end
    $stop;
`endif

end

initial begin
`ifndef MODELSIM
    #300000;
`else 
    #3000000;
`endif
`ifdef ISA_TEST
    $display("*Sim tool:ISA_TEST Timeout, Err");
`else 
    $display("*Sim tool:Normal Sim Timeout");
`endif
    $stop;
end

initial begin
    #30;
    wait(mends === 1'b1)
    $display("*Sim tool:CSR MENDS END, stop sim");
    #10;
    $stop;
end

task sysrst;
    core_ex_trap_valid=0;
    JTAG_TCK=0;
    JTAG_TMS=0;
    JTAG_TDI=0;

    #15

    #10;
endtask : sysrst

task ex_trap;
    #15000;
    core_ex_trap_valid=1;
    #30;
    wait(core_ex_trap_ready);
    core_ex_trap_valid=0;
endtask : ex_trap


genvar i;
generate
    for ( i=0; i <32 ; i++) begin
        assign (weak1,weak0) fpioa[i] = 1'b0;
    end
endgenerate


initial begin
    wait(rst_n===1'b1);
    if(`CorePath.inst_iram.inst_appram.BRAM[0][0]===1'bx) begin
        $display("*Sim tool:Inst load error");
        #10;
        $stop;
    end
end
sparrow_soc inst_sparrow_soc (
    .clk               (clk), 
    .hard_rst_n        (rst_n), 

    .JTAG_TCK          (JTAG_TCK),
    .JTAG_TMS          (JTAG_TMS),
    .JTAG_TDI          (JTAG_TDI),
    .JTAG_TDO          (JTAG_TDO),

    .fpioa             (fpioa),

    .core_ex_trap_valid(core_ex_trap_valid),
    .core_ex_trap_ready(core_ex_trap_ready)
);

`ifdef Flash25
pullup(WPn);
pullup(HOLDn);
W25Q128JVxIM inst_W25Q128JVxIM (
    .CSn   (spi0_cs),
    .CLK   (spi0_clk),
    .DIO   (spi0_mosi),
    .DO    (spi0_miso),
    .WPn   (WPn),
    .HOLDn (HOLDn)
);
`endif


initial begin
    $dumpfile("tb.vcd");
    $dumpvars(0,tb_core);
end


endmodule