data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/iu/rtl/pa_iu_addr_gen.v
data/verilator_xmls/3ceb63e8-0aea-4ffc-8467-19536710ea69.xml
module pa_iu_addr_gen(
  ag_bju_pc,
  ag_dp_ex1_dst_preg,
  ag_dp_ex1_fwd_data,
  ag_dp_ex1_fwd_vld,
  idu_iu_ex1_ag_imm,
  idu_iu_ex1_bju_sel,
  idu_iu_ex1_bju_use_pc,
  idu_iu_ex1_src0,
  iu_ex1_cur_pc,
  iu_idu_ex1_src1_update_value,
  iu_lsu_ex1_lsi_rst,
  lsu_iu_ex1_base_wb,
  lsu_iu_ex1_src1_sel
);


input   [31:0]  idu_iu_ex1_ag_imm;           
input           idu_iu_ex1_bju_sel;          
input           idu_iu_ex1_bju_use_pc;       
input   [31:0]  idu_iu_ex1_src0;             
input   [31:0]  iu_ex1_cur_pc;               
input           lsu_iu_ex1_base_wb;          
input           lsu_iu_ex1_src1_sel;         
output  [31:0]  ag_bju_pc;                   
output  [5 :0]  ag_dp_ex1_dst_preg;          
output  [31:0]  ag_dp_ex1_fwd_data;          
output          ag_dp_ex1_fwd_vld;           
output  [31:0]  iu_idu_ex1_src1_update_value; 
output  [31:0]  iu_lsu_ex1_lsi_rst;          




wire    [31:0]  ag_adder_res;                
wire    [31:0]  ag_adder_rs1;                
wire    [31:0]  ag_adder_rs1_raw;            
wire    [31:0]  ag_adder_rs2;                
wire    [31:0]  ag_bju_pc;                   
wire    [5 :0]  ag_dp_ex1_dst_preg;          
wire    [31:0]  ag_dp_ex1_fwd_data;          
wire            ag_dp_ex1_fwd_vld;           
wire            ag_rs1_use_pc;               
wire    [31:0]  idu_iu_ex1_ag_imm;           
wire            idu_iu_ex1_bju_sel;          
wire            idu_iu_ex1_bju_use_pc;       
wire    [31:0]  idu_iu_ex1_src0;             
wire    [31:0]  iu_ex1_cur_pc;               
wire    [31:0]  iu_idu_ex1_src1_update_value; 
wire    [31:0]  iu_lsu_ex1_lsi_rst;          
wire            lsu_iu_ex1_base_wb;          















assign ag_adder_rs1_raw[31:0]  = {32{idu_iu_ex1_bju_sel || lsu_iu_ex1_base_wb}} & idu_iu_ex1_src0[31:0];

assign ag_rs1_use_pc           = idu_iu_ex1_bju_use_pc;
assign ag_adder_rs1[31:0]      = ag_rs1_use_pc ? {iu_ex1_cur_pc[31:1], 1'b0}
                                               : ag_adder_rs1_raw[31:0];





assign ag_adder_rs2[31:0]      = {32{idu_iu_ex1_bju_sel || lsu_iu_ex1_base_wb}} & idu_iu_ex1_ag_imm[31:0];


assign ag_adder_res[31:0] = ag_adder_rs1[31:0] + ag_adder_rs2[31:0];


assign ag_bju_pc[31:0]       = {ag_adder_res[31:1], 1'b0};

assign iu_idu_ex1_src1_update_value[31:0] = ag_adder_res[31:0];

assign iu_lsu_ex1_lsi_rst[31:0] = ag_dp_ex1_fwd_data[31:0];







assign ag_dp_ex1_fwd_vld = 1'b0;
assign ag_dp_ex1_dst_preg[5:0] = {6{1'bx}};
assign ag_dp_ex1_fwd_data[31:0] = {32{1'bx}};



endmodule
module pa_iu_addr_gen(
  ag_bju_pc,
  ag_dp_ex1_dst_preg,
  ag_dp_ex1_fwd_data,
  ag_dp_ex1_fwd_vld,
  idu_iu_ex1_ag_imm,
  idu_iu_ex1_bju_sel,
  idu_iu_ex1_bju_use_pc,
  idu_iu_ex1_src0,
  iu_ex1_cur_pc,
  iu_idu_ex1_src1_update_value,
  iu_lsu_ex1_lsi_rst,
  lsu_iu_ex1_base_wb,
  lsu_iu_ex1_src1_sel
);



input   [31:0]  idu_iu_ex1_ag_imm;           
input           idu_iu_ex1_bju_sel;          
input           idu_iu_ex1_bju_use_pc;       
input   [31:0]  idu_iu_ex1_src0;             
input   [31:0]  iu_ex1_cur_pc;               
input           lsu_iu_ex1_base_wb;          
input           lsu_iu_ex1_src1_sel;         
output  [31:0]  ag_bju_pc;                   
output  [5 :0]  ag_dp_ex1_dst_preg;          
output  [31:0]  ag_dp_ex1_fwd_data;          
output          ag_dp_ex1_fwd_vld;           
output  [31:0]  iu_idu_ex1_src1_update_value; 
output  [31:0]  iu_lsu_ex1_lsi_rst;          




wire    [31:0]  ag_adder_res;                
wire    [31:0]  ag_adder_rs1;                
wire    [31:0]  ag_adder_rs1_raw;            
wire    [31:0]  ag_adder_rs2;                
wire    [31:0]  ag_bju_pc;                   
wire    [5 :0]  ag_dp_ex1_dst_preg;          
wire    [31:0]  ag_dp_ex1_fwd_data;          
wire            ag_dp_ex1_fwd_vld;           
wire            ag_rs1_use_pc;               
wire    [31:0]  idu_iu_ex1_ag_imm;           
wire            idu_iu_ex1_bju_sel;          
wire            idu_iu_ex1_bju_use_pc;       
wire    [31:0]  idu_iu_ex1_src0;             
wire    [31:0]  iu_ex1_cur_pc;               
wire    [31:0]  iu_idu_ex1_src1_update_value; 
wire    [31:0]  iu_lsu_ex1_lsi_rst;          
wire            lsu_iu_ex1_base_wb;          















assign ag_adder_rs1_raw[31:0]  = {32{idu_iu_ex1_bju_sel || lsu_iu_ex1_base_wb}} & idu_iu_ex1_src0[31:0];

assign ag_rs1_use_pc           = idu_iu_ex1_bju_use_pc;
assign ag_adder_rs1[31:0]      = ag_rs1_use_pc ? {iu_ex1_cur_pc[31:1], 1'b0}
                                               : ag_adder_rs1_raw[31:0];





assign ag_adder_rs2[31:0]      = {32{idu_iu_ex1_bju_sel || lsu_iu_ex1_base_wb}} & idu_iu_ex1_ag_imm[31:0];


assign ag_adder_res[31:0] = ag_adder_rs1[31:0] + ag_adder_rs2[31:0];


assign ag_bju_pc[31:0]       = {ag_adder_res[31:1], 1'b0};

assign iu_idu_ex1_src1_update_value[31:0] = ag_adder_res[31:0];

assign iu_lsu_ex1_lsi_rst[31:0] = ag_dp_ex1_fwd_data[31:0];







assign ag_dp_ex1_fwd_vld = 1'b0;
assign ag_dp_ex1_dst_preg[5:0] = {6{1'bx}};
assign ag_dp_ex1_fwd_data[31:0] = {32{1'bx}};



endmodule