data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v:47: Signal definition not found, creating implicitly: \'c\'\n assign c = (ein[N-N/CC])?cout2[N/CC-1]:cout1[N/CC-1];\n        ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v:47: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                                     : ... In instance modexp_1_N\n assign c = (ein[N-N/CC])?cout2[N/CC-1]:cout1[N/CC-1];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v:103: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                                      : ... In instance modexp_1_N\n    ereg <= {ein[N-N/CC:0], {N/CC{1\'b0}}};\n         ^~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v:130: Cannot find file containing module: \'modmult\'\n  modmult\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/modmult\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/modmult.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/modmult.sv\n             modmult\n             modmult.v\n             modmult.sv\n             obj_dir/modmult\n             obj_dir/modmult.v\n             obj_dir/modmult.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modexp_1_N.v:151: Cannot find file containing module: \'modmult\'\n  modmult\n  ^~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module modexp_1_N
#(
	parameter N 	= 8,
	parameter CC	= N
)
(
  clk,
  rst,
  g_input,
  e_input,
  o
);

  input     clk;
  input     rst;
  input   [N-1:0]   g_input;
  input   [2*N-1:0] e_input;
  output [N-1:0]    o;

  wire  [N-1:0] e;
  wire  [N-1:0] n;

  assign e = e_input[N-1:0];
  assign n = e_input[2*N-1:N];


	reg 	init;
	reg 	first_one;
	reg 	[N-1:0]	ereg; 
	reg	 	[N-1:0]	creg; 

	wire 	[N-1:0] ein;
	
	wire 	[N-1:0] cin		[N/CC-1:0];
	wire 	[N-1:0] cout1	[N/CC-1:0];
	wire 	[N-1:0] cout2	[N/CC-1:0];


	wire keep_1	[N/CC-1:0];
	wire keep_2	[N/CC-1:0];
	
	genvar i;
	
	assign cin[0] = creg;
	assign ein = (init)?ereg:e;
	
	assign c = (ein[N-N/CC])?cout2[N/CC-1]:cout1[N/CC-1];
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:ASSKEEP1
		if(i > 0)
			assign keep_1[i] = (first_one | (|ein[N-1:N-i]));
		else
			assign keep_1[i] = first_one;
	end
	endgenerate
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:ASSKEEP2
		if(i > 0)
			assign keep_2[i] = (first_one | (|ein[N-1:N-i])) & ein[N-1-i];
		else
			assign keep_2[i] = first_one & ein[N-1-i];
	end
	endgenerate


	generate 
	if(CC>1)
	begin
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				init <= 0;
				creg <= 0;
				ereg  <= 0;
				first_one <= 0;
			end
			else
			begin
				init <= 1;
				
				
				if(|ein[N-1:N-N/CC])
					first_one <= 1;
		
				if(keep_2[N/CC-1])
				begin
					creg <= cout2[N/CC-1];		
				end
				else if(keep_1[N/CC-1])
				begin
					creg <= cout1[N/CC-1];
				end
				else
				begin
					creg <= g_input;
				end
			
				ereg <= {ein[N-N/CC:0], {N/CC{1'b0}}};
			end
		end
	end
	else
	begin
		always@(*)
		begin
			init <= 1;
			creg <= g_input;
			ereg  <= e;	
			first_one <= 0;
		end
	end
	endgenerate

	
	generate 
	for(i=1;i<N/CC;i=i+1)
	begin:ASSCIN
		assign cin[i] = (keep_2[i-1])?cout2[i-1]:(keep_1[i-1])?cout1[i-1]:g_input;
	end
	endgenerate
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:MODMULT1
		modmult
		#(
			.N(N),
			.CC(1)
		)
		modmult_1
		(
			.clk(clk),
			.rst(rst),
			.start(1'b1),
			.x(cin[i]),
			.y(cin[i]),
			.n(n),
			.o(cout1[i])
		);
	end
	endgenerate

	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:MODMULT2
		modmult
		#(
			.N(N),
			.CC(1)
		)
		modmult_2
		(
			.clk(clk),
			.rst(rst),
			.x(cout1[i]),
			.start(1'b1),
			.y(g_input),
			.n(n),
			.o(cout2[i])
		);
	end
	endgenerate
endmodule
module modexp_1_N
#(
	parameter N 	= 8,
	parameter CC	= N
)
(
  clk,
  rst,
  g_input,
  e_input,
  o
);


  input     clk;
  input     rst;
  input   [N-1:0]   g_input;
  input   [2*N-1:0] e_input;
  output [N-1:0]    o;

  wire  [N-1:0] e;
  wire  [N-1:0] n;

  assign e = e_input[N-1:0];
  assign n = e_input[2*N-1:N];


	reg 	init;
	reg 	first_one;
	reg 	[N-1:0]	ereg; 
	reg	 	[N-1:0]	creg; 

	wire 	[N-1:0] ein;
	
	wire 	[N-1:0] cin		[N/CC-1:0];
	wire 	[N-1:0] cout1	[N/CC-1:0];
	wire 	[N-1:0] cout2	[N/CC-1:0];


	wire keep_1	[N/CC-1:0];
	wire keep_2	[N/CC-1:0];
	
	genvar i;
	
	assign cin[0] = creg;
	assign ein = (init)?ereg:e;
	
	assign c = (ein[N-N/CC])?cout2[N/CC-1]:cout1[N/CC-1];
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:ASSKEEP1
		if(i > 0)
			assign keep_1[i] = (first_one | (|ein[N-1:N-i]));
		else
			assign keep_1[i] = first_one;
	end
	endgenerate
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:ASSKEEP2
		if(i > 0)
			assign keep_2[i] = (first_one | (|ein[N-1:N-i])) & ein[N-1-i];
		else
			assign keep_2[i] = first_one & ein[N-1-i];
	end
	endgenerate


	generate 
	if(CC>1)
	begin
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				init <= 0;
				creg <= 0;
				ereg  <= 0;
				first_one <= 0;
			end
			else
			begin
				init <= 1;
				
				
				if(|ein[N-1:N-N/CC])
					first_one <= 1;
		
				if(keep_2[N/CC-1])
				begin
					creg <= cout2[N/CC-1];		
				end
				else if(keep_1[N/CC-1])
				begin
					creg <= cout1[N/CC-1];
				end
				else
				begin
					creg <= g_input;
				end
			
				ereg <= {ein[N-N/CC:0], {N/CC{1'b0}}};
			end
		end
	end
	else
	begin
		always@(*)
		begin
			init <= 1;
			creg <= g_input;
			ereg  <= e;	
			first_one <= 0;
		end
	end
	endgenerate

	
	generate 
	for(i=1;i<N/CC;i=i+1)
	begin:ASSCIN
		assign cin[i] = (keep_2[i-1])?cout2[i-1]:(keep_1[i-1])?cout1[i-1]:g_input;
	end
	endgenerate
	
	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:MODMULT1
		modmult
		#(
			.N(N),
			.CC(1)
		)
		modmult_1
		(
			.clk(clk),
			.rst(rst),
			.start(1'b1),
			.x(cin[i]),
			.y(cin[i]),
			.n(n),
			.o(cout1[i])
		);
	end
	endgenerate

	generate 
	for(i=0;i<N/CC;i=i+1)
	begin:MODMULT2
		modmult
		#(
			.N(N),
			.CC(1)
		)
		modmult_2
		(
			.clk(clk),
			.rst(rst),
			.x(cout1[i]),
			.start(1'b1),
			.y(g_input),
			.n(n),
			.o(cout2[i])
		);
	end
	endgenerate
endmodule