data/full_repos/permissive/499944578/rtl/src/memory/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:178: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                                   : ... Top module \'single_port_ram\'\nmodule single_port_ram\n       ^~~~~~~~~~~~~~~\n                                                                                   : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                                   : ... Top module \'simple_ram_dual_clock\'\nmodule simple_ram_dual_clock #(\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:247: Little bit endian vector: MSB < LSB of bit range: -1:0\n    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module simple_ram_dual_clock #(
  parameter DATA_WIDTH=32,
  parameter ADDR_WIDTH=32
)(
  input      [DATA_WIDTH-1:0] data,
  input      [ADDR_WIDTH-1:0] read_addr,
  input      [ADDR_WIDTH-1:0] write_addr,
  input                       we,
  input                       read_clk,
  input                       write_clk,
  input                       re,
  output wire[DATA_WIDTH-1:0] q
);
    
    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;



    always @(posedge write_clk) begin
        if (we) begin 
            ram[write_addr] <= data;
        end
    end
    assign q = ram[read_addr];





    
endmodule
module simple_ram_dual_clock #(
  parameter DATA_WIDTH=32,
  parameter ADDR_WIDTH=32
)(
  input      [DATA_WIDTH-1:0] data,
  input      [ADDR_WIDTH-1:0] read_addr,
  input      [ADDR_WIDTH-1:0] write_addr,
  input                       we,
  input                       read_clk,
  input                       write_clk,
  input                       re,
  output wire[DATA_WIDTH-1:0] q
);

    
    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;



    always @(posedge write_clk) begin
        if (we) begin 
            ram[write_addr] <= data;
        end
    end
    assign q = ram[read_addr];





    
endmodule