data/full_repos/permissive/488093047/Verilog Codes/NOT.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/NOT.v\n%Error: Exiting due to 3 error(s)\n'
module NOT #(parameter N=32)(A,NOT);
input [N-1:0]A;
output [N-1:0]NOT;
genvar i;
generate
for(i=0;i<N;i=i+1)begin
not DUT1(NOT[i],A[i]);
end
endgenerate
endmodule
module NOT #(parameter N=32)(A,NOT);

input [N-1:0]A;
output [N-1:0]NOT;
genvar i;
generate
for(i=0;i<N;i=i+1)begin
not DUT1(NOT[i],A[i]);
end
endgenerate
endmodule