data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv
1: b"%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:36: Cannot find file containing module: 'ttl_74163a_sync'\n    ttl_74163a_sync a11\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74163a_sync\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74163a_sync.v\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74163a_sync.sv\n             ttl_74163a_sync\n             ttl_74163a_sync.v\n             ttl_74163a_sync.sv\n             obj_dir/ttl_74163a_sync\n             obj_dir/ttl_74163a_sync.v\n             obj_dir/ttl_74163a_sync.sv\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:51: Cannot find file containing module: 'ttl_74163a_sync'\n    ttl_74163a_sync a12\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:66: Cannot find file containing module: 'ttl_74163a_sync'\n    ttl_74163a_sync a13\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:89: Cannot find file containing module: 'n9bit_counter'\n    n9bit_counter ra_counter\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:106: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) a8_A (\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:118: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) d9_A (\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:132: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b9 (.Enable_bar(1'b0), .Select(D9_A_Q),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:134: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b11 (.Enable_bar(1'b0), .Select(D9_A_Q),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:136: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b13 (.Enable_bar(1'b0), .Select(D9_A_Q),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:142: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b10 (.Enable_bar(1'b0), .Select(D9_A_Qn),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:144: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b12 (.Enable_bar(1'b0), .Select(D9_A_Qn),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:146: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b14 (.Enable_bar(1'b0), .Select(D9_A_Qn),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:154: Cannot find file containing module: 'ttl_74374_sync'\n    ttl_74374_sync d14 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Qn), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL1_in));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:155: Cannot find file containing module: 'ttl_74374_sync'\n    ttl_74374_sync d13 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Q), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL0_in));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:158: Cannot find file containing module: 'SRAM_sync_noinit'\n    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c13(.ADDR({L0A}), .clk(clk), .cen(~L0CE), .we(~L0WE), .DATA(DL0_in), .Q(DL0_out) );\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:159: Cannot find file containing module: 'SRAM_sync_noinit'\n    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c14(.ADDR({L1A}), .clk(clk), .cen(~L1CE), .we(~L1WE), .DATA(DL1_in), .Q(DL1_out) );\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:165: Cannot find file containing module: 'ttl_74298_sync'\n ttl_74298_sync J2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[7:4]), .B(DL1[7:4]), .Q(LD_BUF[7:4]));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_LineBuffer.sv:166: Cannot find file containing module: 'ttl_74298_sync'\n ttl_74298_sync H2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[3:0]), .B(DL1[3:0]), .Q(LD_BUF[3:0]));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n"
module IkariWarriorsCore_LineBuffer(

    input  wire VIDEO_RSTn,
    input wire clk,
    input wire RESETn,
    input wire [7:0] FD,
    input wire LT,
    input wire VCKn,
    input wire CK1,
    input wire CK1n,
    input wire CK0,
    input wire CK0n,
    input wire FCK_LDn,
    input wire [8:0] FLY,
    input wire HLD,
    input wire FY8,
    input wire [7:0] FY,
    input wire INVn,

    output logic [7:0] LD_BUF
);
    logic LTn;
    logic VCK;

    assign LTn = ~LT;
    assign VCK = ~VCKn;

    logic [8:0] W1A;
    logic A11_RCO;
    ttl_74163a_sync a11
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(1'b1),
        .ENP(1'b1),
        .D(FLY[3:0]),
        .Cen(CK0),
        .RCO(A11_RCO),
        .Q(W1A[3:0])
    );

    logic A12_RCO;
    ttl_74163a_sync a12
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(A11_RCO),
        .ENP(1'b1),
        .D(FLY[7:4]),
        .Cen(CK0),
        .RCO(A12_RCO),
        .Q(W1A[7:4])
    );

    logic [2:0] a13_dum;
    ttl_74163a_sync a13
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(A12_RCO),
        .ENP(1'b1),
        .D({3'b111,FLY[8]}),
        .Cen(CK0),
        .RCO(),
        .Q({a13_dum,W1A[8]})
    );


    logic HLDr;

    always @(posedge clk) begin
        HLDr <= HLD;

    end

    logic [8:0] R1A;
    n9bit_counter ra_counter
    (
        .Reset_n(VIDEO_RSTn),
        .clk(clk), 
        .cen(CK1),
        .direction(INVn),
        .load_n(HLDr),
        .ent_n(1'b0),
        .enp_n(1'b0),
        .P({FY8,FY}),
        .Q(R1A)
    );

    logic a14_A;
    assign a14_A = ~(&FD[2:0]);

    logic A8_B_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) a8_A (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(a14_A),
        .q(),
        .qn(A8_B_Qn),
        .set(1'b0),
        .clr(1'b0),
        .cen(CK0n)
    );

    logic D9_A_Q, D9_A_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) d9_A (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(D9_A_Qn),
        .q(D9_A_Q),
        .qn(D9_A_Qn),
        .set(1'b0),
        .clr(~LTn),
        .cen(VCK)
    );

    logic [8:0] L0A;
    logic L0OE, L0WE, L0CE;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b9 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({R1A[3],W1A[3],R1A[2],W1A[2],R1A[1],W1A[1],R1A[0],W1A[0]}), .Y(L0A[3:0]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b11 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({R1A[7],W1A[7],R1A[6],W1A[6],R1A[5],W1A[5],R1A[4],W1A[4]}), .Y(L0A[7:4]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b13 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({D9_A_Qn,1'b1, CK1,CK0, 1'b0,A8_B_Qn, R1A[8],W1A[8]}), .Y({L0OE,L0WE,L0CE,L0A[8]}));

    logic [8:0] L1A;
    logic L1OE, L1WE, L1CE;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b10 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({R1A[3],W1A[3],R1A[2],W1A[2],R1A[1],W1A[1],R1A[0],W1A[0]}), .Y(L1A[3:0]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b12 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({R1A[7],W1A[7],R1A[6],W1A[6],R1A[5],W1A[5],R1A[4],W1A[4]}), .Y(L1A[7:4]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b14 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({D9_A_Q,1'b1, CK1,CK0, 1'b0,A8_B_Qn, R1A[8],W1A[8]}), .Y({L1OE,L1WE,L1CE,L1A[8]}));



    logic [7:0] DL1_in, DL0_in;
    logic [7:0] DL1_out, DL0_out;

    ttl_74374_sync d14 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Qn), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL1_in));
    ttl_74374_sync d13 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Q), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL0_in));


    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c13(.ADDR({L0A}), .clk(clk), .cen(~L0CE), .we(~L0WE), .DATA(DL0_in), .Q(DL0_out) );
    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c14(.ADDR({L1A}), .clk(clk), .cen(~L1CE), .we(~L1WE), .DATA(DL1_in), .Q(DL1_out) );
    
    logic [7:0] DL0, DL1;
    assign DL0 = ((!L0OE && !L0CE) ? DL0_out : 8'hff);
    assign DL1 = ((!L1OE && !L1CE) ? DL1_out : 8'hff);

	ttl_74298_sync J2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[7:4]), .B(DL1[7:4]), .Q(LD_BUF[7:4]));
	ttl_74298_sync H2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[3:0]), .B(DL1[3:0]), .Q(LD_BUF[3:0]));
endmodule
module IkariWarriorsCore_LineBuffer(

    input  wire VIDEO_RSTn,
    input wire clk,
    input wire RESETn,
    input wire [7:0] FD,
    input wire LT,
    input wire VCKn,
    input wire CK1,
    input wire CK1n,
    input wire CK0,
    input wire CK0n,
    input wire FCK_LDn,
    input wire [8:0] FLY,
    input wire HLD,
    input wire FY8,
    input wire [7:0] FY,
    input wire INVn,

    output logic [7:0] LD_BUF
);

    logic LTn;
    logic VCK;

    assign LTn = ~LT;
    assign VCK = ~VCKn;

    logic [8:0] W1A;
    logic A11_RCO;
    ttl_74163a_sync a11
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(1'b1),
        .ENP(1'b1),
        .D(FLY[3:0]),
        .Cen(CK0),
        .RCO(A11_RCO),
        .Q(W1A[3:0])
    );

    logic A12_RCO;
    ttl_74163a_sync a12
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(A11_RCO),
        .ENP(1'b1),
        .D(FLY[7:4]),
        .Cen(CK0),
        .RCO(A12_RCO),
        .Q(W1A[7:4])
    );

    logic [2:0] a13_dum;
    ttl_74163a_sync a13
    (
        .Clk(clk),
        .Rst_n(VIDEO_RSTn),
        .Clear_bar(1'b1),
        .Load_bar(FCK_LDn),
        .ENT(A12_RCO),
        .ENP(1'b1),
        .D({3'b111,FLY[8]}),
        .Cen(CK0),
        .RCO(),
        .Q({a13_dum,W1A[8]})
    );


    logic HLDr;

    always @(posedge clk) begin
        HLDr <= HLD;

    end

    logic [8:0] R1A;
    n9bit_counter ra_counter
    (
        .Reset_n(VIDEO_RSTn),
        .clk(clk), 
        .cen(CK1),
        .direction(INVn),
        .load_n(HLDr),
        .ent_n(1'b0),
        .enp_n(1'b0),
        .P({FY8,FY}),
        .Q(R1A)
    );

    logic a14_A;
    assign a14_A = ~(&FD[2:0]);

    logic A8_B_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) a8_A (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(a14_A),
        .q(),
        .qn(A8_B_Qn),
        .set(1'b0),
        .clr(1'b0),
        .cen(CK0n)
    );

    logic D9_A_Q, D9_A_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) d9_A (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(D9_A_Qn),
        .q(D9_A_Q),
        .qn(D9_A_Qn),
        .set(1'b0),
        .clr(~LTn),
        .cen(VCK)
    );

    logic [8:0] L0A;
    logic L0OE, L0WE, L0CE;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b9 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({R1A[3],W1A[3],R1A[2],W1A[2],R1A[1],W1A[1],R1A[0],W1A[0]}), .Y(L0A[3:0]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b11 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({R1A[7],W1A[7],R1A[6],W1A[6],R1A[5],W1A[5],R1A[4],W1A[4]}), .Y(L0A[7:4]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b13 (.Enable_bar(1'b0), .Select(D9_A_Q),
                .A_2D({D9_A_Qn,1'b1, CK1,CK0, 1'b0,A8_B_Qn, R1A[8],W1A[8]}), .Y({L0OE,L0WE,L0CE,L0A[8]}));

    logic [8:0] L1A;
    logic L1OE, L1WE, L1CE;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b10 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({R1A[3],W1A[3],R1A[2],W1A[2],R1A[1],W1A[1],R1A[0],W1A[0]}), .Y(L1A[3:0]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b12 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({R1A[7],W1A[7],R1A[6],W1A[6],R1A[5],W1A[5],R1A[4],W1A[4]}), .Y(L1A[7:4]));
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) b14 (.Enable_bar(1'b0), .Select(D9_A_Qn),
                .A_2D({D9_A_Q,1'b1, CK1,CK0, 1'b0,A8_B_Qn, R1A[8],W1A[8]}), .Y({L1OE,L1WE,L1CE,L1A[8]}));



    logic [7:0] DL1_in, DL0_in;
    logic [7:0] DL1_out, DL0_out;

    ttl_74374_sync d14 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Qn), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL1_in));
    ttl_74374_sync d13 (.RESETn(VIDEO_RSTn), .OCn(D9_A_Q), .Clk(clk), .Cen(CK0n), .D(FD[7:0]), .Q(DL0_in));


    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c13(.ADDR({L0A}), .clk(clk), .cen(~L0CE), .we(~L0WE), .DATA(DL0_in), .Q(DL0_out) );
    SRAM_sync_noinit #(.ADDR_WIDTH(9)) c14(.ADDR({L1A}), .clk(clk), .cen(~L1CE), .we(~L1WE), .DATA(DL1_in), .Q(DL1_out) );
    
    logic [7:0] DL0, DL1;
    assign DL0 = ((!L0OE && !L0CE) ? DL0_out : 8'hff);
    assign DL1 = ((!L1OE && !L1CE) ? DL1_out : 8'hff);

	ttl_74298_sync J2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[7:4]), .B(DL1[7:4]), .Q(LD_BUF[7:4]));
	ttl_74298_sync H2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1), .WS(D9_A_Qn), .A(DL0[3:0]), .B(DL1[3:0]), .Q(LD_BUF[3:0]));
endmodule