data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v
1: b'%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:3: syntax error, unexpected int, expecting IDENTIFIER or \'[\' or do or final\n    input wire [31:0] int,\n                      ^~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:5: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:10: syntax error, unexpected IDENTIFIER\n    first_set_bit32 first_set_bit32_inst(int, first_set_bit, intEq0);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:15: syntax error, unexpected assign\n    assign fsb6bit = {1\'b0,first_set_bit};\n    ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:70: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n    reg [31:0] int;\n               ^~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:72: syntax error, unexpected \',\', expecting "\'{"\n    int2fp32 int2fp32_inst(int,float);  \n                              ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:74: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n        int = 32\'d4;\n              ^~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:75: syntax error, unexpected \'=\', expecting "\'{"\n        #10 int = 32\'d546;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10 int = 32\'d546;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:76: syntax error, unexpected \'=\', expecting "\'{"\n        #10 int = 32\'d1231506;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 int = 32\'d1231506;\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:77: syntax error, unexpected \'=\', expecting "\'{"\n        #10 int = 32\'d52540036;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #10 int = 32\'d52540036;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:83: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("int2fp32_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:84: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,int2fp32_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:85: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b0000_0000_0000_1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b0000_0000_1000_0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b0001_0000_0000_0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:120: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("first_set_bit16_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:121: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,first_set_bit16_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:122: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 8\'b0000_1000;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 8\'b0010_0000;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:166: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 8\'b1000_0000;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:172: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("first_set_bit8_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:173: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,first_set_bit8_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:174: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:187: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:188: Unsupported: Ignoring delay on this delayed statement.\n        #10 x = 16\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:194: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("first_set_bit4_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:195: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,first_set_bit4_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/utils/int2FP.v:196: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 18 error(s), 20 warning(s)\n'
module shift32(
    input wire [31:0] in, 
    input wire [5:0] shamt,
    output reg [31:0] out
);
    always @(*) begin
        case(shamt)
            6'd0: out = in<<0;
            6'd1: out = in<<1;
            6'd2: out = in<<2;
            6'd3: out = in<<3;
            6'd4: out = in<<4;
            6'd5: out = in<<5;
            6'd6: out = in<<6;
            6'd7: out = in<<7;
            6'd8: out = in<<8;
            6'd9: out = in<<9;
            6'd10: out = in<<10;
            6'd11: out = in<<11;
            6'd12: out = in<<12;
            6'd13: out = in<<13;
            6'd14: out = in<<14;
            6'd15: out = in<<15;
            6'd16: out = in<<16;
            6'd17: out = in<<17;
            6'd18: out = in<<18;
            6'd19: out = in<<19;
            6'd20: out = in<<20;
            6'd21: out = in<<21;
            6'd22: out = in<<22;
            6'd23: out = in<<23;
            6'd24: out = in<<24;
            6'd25: out = in<<25;
            6'd26: out = in<<26;
            6'd27: out = in<<27;
            6'd28: out = in<<28;
            6'd29: out = in<<29; 
            6'd30: out = in<<30;
            6'd31: out = in<<31;
            6'd32: out = in<<32;
            default: out = in<<0;
        endcase
    end

endmodule
module shift32(
    input wire [31:0] in, 
    input wire [5:0] shamt,
    output reg [31:0] out
);

    always @(*) begin
        case(shamt)
            6'd0: out = in<<0;
            6'd1: out = in<<1;
            6'd2: out = in<<2;
            6'd3: out = in<<3;
            6'd4: out = in<<4;
            6'd5: out = in<<5;
            6'd6: out = in<<6;
            6'd7: out = in<<7;
            6'd8: out = in<<8;
            6'd9: out = in<<9;
            6'd10: out = in<<10;
            6'd11: out = in<<11;
            6'd12: out = in<<12;
            6'd13: out = in<<13;
            6'd14: out = in<<14;
            6'd15: out = in<<15;
            6'd16: out = in<<16;
            6'd17: out = in<<17;
            6'd18: out = in<<18;
            6'd19: out = in<<19;
            6'd20: out = in<<20;
            6'd21: out = in<<21;
            6'd22: out = in<<22;
            6'd23: out = in<<23;
            6'd24: out = in<<24;
            6'd25: out = in<<25;
            6'd26: out = in<<26;
            6'd27: out = in<<27;
            6'd28: out = in<<28;
            6'd29: out = in<<29; 
            6'd30: out = in<<30;
            6'd31: out = in<<31;
            6'd32: out = in<<32;
            default: out = in<<0;
        endcase
    end

endmodule