data/full_repos/permissive/433624543/generic_n_x_n_mult.v
data/verilator_xmls/77bc6db2-608d-4a2f-a0fe-edfaf76a4baf.xml
module Full_Adder_four_in(input a_old, a_new, b_old, b_new, carry_in, output reg sum, carry_out);
    always @(a_old or a_new or b_old or b_new or carry_in)
    begin
        sum = (a_old & b_new) ^ (a_new & b_old) ^ carry_in;
        carry_out = (a_old & b_new) & (a_new & b_old) | ((a_old & b_new)^(a_new & b_old)) & carry_in;
    end
endmodule
module Full_Adder_four_in(input a_old, a_new, b_old, b_new, carry_in, output reg sum, carry_out);

    always @(a_old or a_new or b_old or b_new or carry_in)
    begin
        sum = (a_old & b_new) ^ (a_new & b_old) ^ carry_in;
        carry_out = (a_old & b_new) & (a_new & b_old) | ((a_old & b_new)^(a_new & b_old)) & carry_in;
    end
endmodule