data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v:92: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 12 bits.\n                                                                                       : ... In instance instdec_stage\n assign I_imm3 = sv2v_cast_32_signed($signed(instrReg3[31:20]));\n                 ^~~~~~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v:93: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 13 bits.\n                                                                                       : ... In instance instdec_stage\n assign B_imm3 = sv2v_cast_32_signed($signed({instrReg3[31], instrReg3[7], instrReg3[30:25], instrReg3[11:8], 1\'b0}));\n                 ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v:94: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 21 bits.\n                                                                                       : ... In instance instdec_stage\n assign J_imm3 = sv2v_cast_32_signed($signed({instrReg3[31], instrReg3[19:12], instrReg3[20], instrReg3[30:21], 1\'b0}));\n                 ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v:96: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 12 bits.\n                                                                                       : ... In instance instdec_stage\n assign S_imm3 = sv2v_cast_32_signed($signed({instrReg3[31:25], instrReg3[11:7]}));\n                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/core/decode_stage.v:108: Cannot find file containing module: \'instr_decoder\'\n instr_decoder c1(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522312766/verilog/rtl/core,data/full_repos/permissive/522312766/instr_decoder\n             data/full_repos/permissive/522312766/verilog/rtl/core,data/full_repos/permissive/522312766/instr_decoder.v\n             data/full_repos/permissive/522312766/verilog/rtl/core,data/full_repos/permissive/522312766/instr_decoder.sv\n             instr_decoder\n             instr_decoder.v\n             instr_decoder.sv\n             obj_dir/instr_decoder\n             obj_dir/instr_decoder.v\n             obj_dir/instr_decoder.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
function automatic signed [31:0] sv2v_cast_32_signed;
		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction
function automatic signed [31:0] sv2v_cast_32_signed;

		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction