data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v:1: Cannot find include file: rom.v\n`include "rom.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/rom.v\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/rom.v.v\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/rom.v.sv\n             rom.v\n             rom.v.v\n             rom.v.sv\n             obj_dir/rom.v\n             obj_dir/rom.v.v\n             obj_dir/rom.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v:21: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/rom.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v:22: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/memories/rom-tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module rom_tb;

reg clk, en;
reg [3:0] addr;
wire [31:0] data;
integer i;

rom dut 
(
    clk, en, addr, data
);
defparam dut.ADDR_WIDTH = 4;
defparam dut.DATA_WIDTH = 32;
defparam dut.ROM_FILE = "build/raw-mnist-weights-int8/conv2d/cell-weight-0.mem";


initial
begin
    $dumpfile("./build/rtl-sim/vcd/rom.vcd");
    $dumpvars;
end

initial
begin
    for (i = 0; i < 64; i = i + 1)
    begin
        en = 1;
        addr = i % 32;

        clk = 0;
        #100;
        clk = 1;
        #100;
    end
end

endmodule
module rom_tb;


reg clk, en;
reg [3:0] addr;
wire [31:0] data;
integer i;

rom dut 
(
    clk, en, addr, data
);
defparam dut.ADDR_WIDTH = 4;
defparam dut.DATA_WIDTH = 32;
defparam dut.ROM_FILE = "build/raw-mnist-weights-int8/conv2d/cell-weight-0.mem";


initial
begin
    $dumpfile("./build/rtl-sim/vcd/rom.vcd");
    $dumpvars;
end

initial
begin
    for (i = 0; i < 64; i = i + 1)
    begin
        en = 1;
        addr = i % 32;

        clk = 0;
        #100;
        clk = 1;
        #100;
    end
end

endmodule