data/full_repos/permissive/506636840/rtl/uart/rtl/uart_top.v
1: b'%Error: data/full_repos/permissive/506636840/rtl/uart/rtl/uart_top.v:147: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v.v\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/506636840/rtl/uart/rtl/uart_top.v:150: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module uart_top (

  input PCLK, 
  

  input PRESETn, 
  input [31:0] PADDR,
  input [31:0] PWDATA,
  output[31:0] PRDATA,
  input PWRITE,
  input PENABLE,
  input PSEL,
  output PREADY,
  output int_o,



  output stx_pad_o, 
  input srx_pad_i,


  output rts_pad_o, 
  input cts_pad_i, 
  output dtr_pad_o, 
  input dsr_pad_i, 
  input ri_pad_i, 
  input dcd_pad_i,
  output baud_o
  );





wire wb_rst_i;

assign wb_rst_i = ~PRESETn;

wire [7:0]               wb_dat8_o;

assign PRDATA = {24'b0, wb_dat8_o};

wire                   we_o;
wire                     re_o;





uart_apb apb_interface(
   .PCLK(PCLK),
   .PRESETn(PRESETn),
   .PSEL(PSEL),
   .PWRITE(PWRITE),
   .PENABLE(PENABLE),
   .PREADY(PREADY),
   .we_o(we_o),
   .re_o(re_o));


uart_regs regs(
  .clk(   PCLK    ),
  .wb_rst_i(  wb_rst_i  ),
  .wb_addr_i( PADDR[6:2]  ),
  .wb_dat_i(  PWDATA[7:0] ),
  .wb_dat_o(  wb_dat8_o ),
  .wb_we_i( we_o    ),
   .wb_re_i(re_o),
  .modem_inputs(  {cts_pad_i, dsr_pad_i,
  ri_pad_i,  dcd_pad_i} ),
  .stx_pad_o(   stx_pad_o   ),
  .srx_pad_i(   srx_pad_i   ),            
  .rts_pad_o(   rts_pad_o   ),
  .dtr_pad_o(   dtr_pad_o   ),
  .int_o(   int_o   ),
  .baud_o(baud_o)


); 

endmodule
module uart_top (

  input PCLK, 
  

  input PRESETn, 
  input [31:0] PADDR,
  input [31:0] PWDATA,
  output[31:0] PRDATA,
  input PWRITE,
  input PENABLE,
  input PSEL,
  output PREADY,
  output int_o,



  output stx_pad_o, 
  input srx_pad_i,


  output rts_pad_o, 
  input cts_pad_i, 
  output dtr_pad_o, 
  input dsr_pad_i, 
  input ri_pad_i, 
  input dcd_pad_i,
  output baud_o
  );






wire wb_rst_i;

assign wb_rst_i = ~PRESETn;

wire [7:0]               wb_dat8_o;

assign PRDATA = {24'b0, wb_dat8_o};

wire                   we_o;
wire                     re_o;





uart_apb apb_interface(
   .PCLK(PCLK),
   .PRESETn(PRESETn),
   .PSEL(PSEL),
   .PWRITE(PWRITE),
   .PENABLE(PENABLE),
   .PREADY(PREADY),
   .we_o(we_o),
   .re_o(re_o));


uart_regs regs(
  .clk(   PCLK    ),
  .wb_rst_i(  wb_rst_i  ),
  .wb_addr_i( PADDR[6:2]  ),
  .wb_dat_i(  PWDATA[7:0] ),
  .wb_dat_o(  wb_dat8_o ),
  .wb_we_i( we_o    ),
   .wb_re_i(re_o),
  .modem_inputs(  {cts_pad_i, dsr_pad_i,
  ri_pad_i,  dcd_pad_i} ),
  .stx_pad_o(   stx_pad_o   ),
  .srx_pad_i(   srx_pad_i   ),            
  .rts_pad_o(   rts_pad_o   ),
  .dtr_pad_o(   dtr_pad_o   ),
  .int_o(   int_o   ),
  .baud_o(baud_o)


); 

endmodule