data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/SEGDRIVE_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/SEGDRIVE_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/SEGDRIVE_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1000\n        ^\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/SEGDRIVE_TB.v:12: Cannot find file containing module: \'SEGDRIVE\'\n    SEGDRIVE COMP (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/SEGDRIVE\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/SEGDRIVE.v\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/SEGDRIVE.sv\n             SEGDRIVE\n             SEGDRIVE.v\n             SEGDRIVE.sv\n             obj_dir/SEGDRIVE\n             obj_dir/SEGDRIVE.v\n             obj_dir/SEGDRIVE.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SEGDRIVE_TB(

    );
    reg [31:0] tmp_SW_tb;
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;
    
    
    SEGDRIVE COMP (
    .inDigit(tmp_SW_tb),
    .Cnode(Cnode_tb),
    .dp(dp_tb),
    .AN(AN_tb)
           
    );
    
    initial 
        begin

        tmp_SW_tb=1;
        #10
        tmp_SW_tb=4;
        #1000
        $finish;
        end
        
   
   
    
    
    
    
endmodule
module SEGDRIVE_TB(

    );

    reg [31:0] tmp_SW_tb;
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;
    
    
    SEGDRIVE COMP (
    .inDigit(tmp_SW_tb),
    .Cnode(Cnode_tb),
    .dp(dp_tb),
    .AN(AN_tb)
           
    );
    
    initial 
        begin

        tmp_SW_tb=1;
        #10
        tmp_SW_tb=4;
        #1000
        $finish;
        end
        
   
   
    
    
    
    
endmodule