data/full_repos/permissive/43856783/I2C/bit_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/I2C/bit_ctrl.v:201: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'rst\' generates 1 bits.\n                                                                      : ... In instance bit_ctrl\n     state <=rst;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bit_ctrl(
    input clk,
    input clk_frame,
    input rst,
    input en,
    input rw,
	 input w_bit,
    input start_cond,
    input stop_cond,
    output reg r_bit,
    output reg busy,
	 output reg SCL,
	 inout SDA
    );
	 

	

	wire SDA_in;
	reg SDA_out, SDA_oen;
	initial begin
		SDA_out 	= 1'bz;
		SDA_oen = 1'b0;
	end
	assign SDA = SDA_oen ? SDA_out : 1'bz;
	assign SDA_in = SDA;

	

	reg write_bit,write_bit_d;
	reg in_bit,in_bit_d;
	reg[4:0] state;
	reg[2:0] del_frame;
	reg en_st;
	reg SCL_d,SDA_out_d,SDA_oen_d;

	

	localparam 	start 	= 0,
					idle 		= 1,
					write_A	= 2,
					write_B	= 3,
					write_C	= 4,
					write_D	= 5,
					read_A	= 6,
					read_B	= 7,
					read_C	= 8,
					read_D	= 9,
					start_A	= 10,
					start_B	= 11,
					start_C	= 12,
					start_D	= 13,
					stop_A	= 14,
					stop_B	= 15,
					stop_C	= 16,
					stop_D	= 17;

	
	always @(negedge clk) begin
		write_bit_d <= write_bit;
		in_bit_d <= in_bit;
		SCL_d <= SCL;
		SDA_out_d <= SDA_out;
		SDA_oen_d <= SDA_oen;
		
		del_frame[0] <= ~clk_frame;
		del_frame[2] <= ~del_frame[1];
	end
	
	always @(posedge clk) begin
		del_frame[1] <= ~del_frame[0];
		
		if(rst) state <= start;
		else begin
			case(state)
				start: begin
					state <= idle;
				end
				
				idle: begin
					if(en) begin
						if(start_cond) state <= start_A;
						else if(stop_cond) state <= stop_A;
						else if(rw) state <= write_A;
						else state <= read_A;
					end
					else state <= idle;
				end
				
				write_A: begin
					if(en_st) state <= write_B;
				end
				
				write_B: begin
					if(en_st) state <= write_C;
				end
				
				write_C: begin
					if(en_st) state <= write_D;
				end
				
				write_D: begin
					if(en_st) state <= idle;
				end
				
				read_A: begin
					if(en_st) state <= read_B;
				end
				
				read_B: begin
					if(en_st) state <= read_C;
				end
				
				read_C: begin
					if(en_st) state <= read_D;
				end
				
				read_D: begin
					if(en_st) state <= idle;
				end
				
				start_A: begin
					if(en_st) state <= start_B;
				end
				
				start_B: begin
					if(en_st) state <= start_C;
				end
				
				start_C: begin
					if(en_st) state <= start_D;
				end
				
				start_D: begin
					if(en_st) state <= idle;
				end
				
				stop_A: begin
					if(en_st) state <= stop_B;
				end
				
				stop_B: begin
					if(en_st) state <= stop_C;
				end
				
				stop_C: begin
					if(en_st) state <= stop_D;
				end
				
				stop_D: begin
					if(en_st) state <= idle;
				end
				
				default: begin
					state <=rst;
				end
			endcase
		end
	end
	
	always@(*) begin
		en_st <= clk_frame & del_frame[2];
		case(state)
			start: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			idle: begin
				r_bit			<= in_bit;
				busy			<= 1'b0;
				SCL			<= SCL_d;
				SDA_out		<= SDA_out_d;
				SDA_oen		<= SDA_oen_d;
				write_bit	<= w_bit;
				in_bit		<= in_bit_d;
			end
			
			write_A: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_A: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= SDA_in;
			end
			
			read_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_A: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= SCL_d;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			start_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_A: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			stop_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			default: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
		endcase
	end
	
endmodule
module bit_ctrl(
    input clk,
    input clk_frame,
    input rst,
    input en,
    input rw,
	 input w_bit,
    input start_cond,
    input stop_cond,
    output reg r_bit,
    output reg busy,
	 output reg SCL,
	 inout SDA
    );

	 

	

	wire SDA_in;
	reg SDA_out, SDA_oen;
	initial begin
		SDA_out 	= 1'bz;
		SDA_oen = 1'b0;
	end
	assign SDA = SDA_oen ? SDA_out : 1'bz;
	assign SDA_in = SDA;

	

	reg write_bit,write_bit_d;
	reg in_bit,in_bit_d;
	reg[4:0] state;
	reg[2:0] del_frame;
	reg en_st;
	reg SCL_d,SDA_out_d,SDA_oen_d;

	

	localparam 	start 	= 0,
					idle 		= 1,
					write_A	= 2,
					write_B	= 3,
					write_C	= 4,
					write_D	= 5,
					read_A	= 6,
					read_B	= 7,
					read_C	= 8,
					read_D	= 9,
					start_A	= 10,
					start_B	= 11,
					start_C	= 12,
					start_D	= 13,
					stop_A	= 14,
					stop_B	= 15,
					stop_C	= 16,
					stop_D	= 17;

	
	always @(negedge clk) begin
		write_bit_d <= write_bit;
		in_bit_d <= in_bit;
		SCL_d <= SCL;
		SDA_out_d <= SDA_out;
		SDA_oen_d <= SDA_oen;
		
		del_frame[0] <= ~clk_frame;
		del_frame[2] <= ~del_frame[1];
	end
	
	always @(posedge clk) begin
		del_frame[1] <= ~del_frame[0];
		
		if(rst) state <= start;
		else begin
			case(state)
				start: begin
					state <= idle;
				end
				
				idle: begin
					if(en) begin
						if(start_cond) state <= start_A;
						else if(stop_cond) state <= stop_A;
						else if(rw) state <= write_A;
						else state <= read_A;
					end
					else state <= idle;
				end
				
				write_A: begin
					if(en_st) state <= write_B;
				end
				
				write_B: begin
					if(en_st) state <= write_C;
				end
				
				write_C: begin
					if(en_st) state <= write_D;
				end
				
				write_D: begin
					if(en_st) state <= idle;
				end
				
				read_A: begin
					if(en_st) state <= read_B;
				end
				
				read_B: begin
					if(en_st) state <= read_C;
				end
				
				read_C: begin
					if(en_st) state <= read_D;
				end
				
				read_D: begin
					if(en_st) state <= idle;
				end
				
				start_A: begin
					if(en_st) state <= start_B;
				end
				
				start_B: begin
					if(en_st) state <= start_C;
				end
				
				start_C: begin
					if(en_st) state <= start_D;
				end
				
				start_D: begin
					if(en_st) state <= idle;
				end
				
				stop_A: begin
					if(en_st) state <= stop_B;
				end
				
				stop_B: begin
					if(en_st) state <= stop_C;
				end
				
				stop_C: begin
					if(en_st) state <= stop_D;
				end
				
				stop_D: begin
					if(en_st) state <= idle;
				end
				
				default: begin
					state <=rst;
				end
			endcase
		end
	end
	
	always@(*) begin
		en_st <= clk_frame & del_frame[2];
		case(state)
			start: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			idle: begin
				r_bit			<= in_bit;
				busy			<= 1'b0;
				SCL			<= SCL_d;
				SDA_out		<= SDA_out_d;
				SDA_oen		<= SDA_oen_d;
				write_bit	<= w_bit;
				in_bit		<= in_bit_d;
			end
			
			write_A: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			write_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= write_bit ? 1'bz : 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_A: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= SDA_in;
			end
			
			read_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			read_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_A: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= SCL_d;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			start_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			start_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_A: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'b0;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
			
			stop_B: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'b0;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_C: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			stop_D: begin
				r_bit			<= in_bit;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b1;
				write_bit	<= write_bit_d;
				in_bit		<= in_bit_d;
			end
			
			default: begin
				r_bit			<= 1'b0;
				busy			<= 1'b1;
				SCL			<= 1'bz;
				SDA_out		<= 1'bz;
				SDA_oen		<= 1'b0;
				write_bit	<= 1'b0;
				in_bit		<= 1'b0;
			end
		endcase
	end
	
endmodule