data/full_repos/permissive/45677639/rtl/mips_mult.v
1: b'%Warning-WIDTH: data/full_repos/permissive/45677639/rtl/mips_mult.v:30: Operator ADD expects 48 bits on the RHS, but RHS\'s SEL generates 32 bits.\n                                                                      : ... In instance mips_mult\n  assign partprod_hl= partprod_h+partprod_l[47:16];\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mips_mult  (
                  input         acompl,
                  input         bcompl,

                  input[15:0]   a,
                  input[31:0]   b,
                  input[47:0]   partprod_h,
                  input[47:0]   partprod_l,

                  output[47:0]  partproduct,
                  output[63:0]  product
                  );




  wire[47:0] partprod_hl;




  assign partproduct= a*b;
  assign partprod_hl= partprod_h+partprod_l[47:16];
  assign product= (acompl^bcompl) ? ~{partprod_hl,partprod_l[15:0]}+64'd1 :
                  {partprod_hl,partprod_l[15:0]};




endmodule
module mips_mult  (
                  input         acompl,
                  input         bcompl,

                  input[15:0]   a,
                  input[31:0]   b,
                  input[47:0]   partprod_h,
                  input[47:0]   partprod_l,

                  output[47:0]  partproduct,
                  output[63:0]  product
                  );





  wire[47:0] partprod_hl;




  assign partproduct= a*b;
  assign partprod_hl= partprod_h+partprod_l[47:16];
  assign product= (acompl^bcompl) ? ~{partprod_hl,partprod_l[15:0]}+64'd1 :
                  {partprod_hl,partprod_l[15:0]};




endmodule