data/full_repos/permissive/471941633/Delay/adld_hw.v
data/verilator_xmls/5fc03796-bf5b-4102-8614-9997939e639a.xml
module adld_hw(
    input [2:0] a_late,
    input [2:0] b,
    output reg[2:0] out
    );

wire [2:0]max,c;
assign c = a_late+b;

assign max = 3'b100;

always @(c or max)
begin
if(c>=max)
 out = 3'b101;
else
 out = 3'b010;
end


endmodule
module adld_hw(
    input [2:0] a_late,
    input [2:0] b,
    output reg[2:0] out
    );


wire [2:0]max,c;
assign c = a_late+b;

assign max = 3'b100;

always @(c or max)
begin
if(c>=max)
 out = 3'b101;
else
 out = 3'b010;
end


endmodule