data/full_repos/permissive/501791642/ISE_devel/midi/midi.v
1: b"%Error: data/full_repos/permissive/501791642/ISE_devel/midi/midi.v:191: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/501791642/ISE_devel/midi/midi.v:207: syntax error, unexpected IDENTIFIER\nregister_clr #(\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module polyphony (
	input CLK,
	input CE,
	input RST,
	input [6:0] NOTE_NUM,
	input [6:0] NOTE_VEL,
	input HANDLE_NOTE,
	input NOTE_ON,
	input NOTE_OFF,
	output [6:0] NOTE_NUM_0,
	output [6:0] NOTE_NUM_1,
	output [6:0] NOTE_NUM_2,
	output [6:0] NOTE_NUM_3,
	output [6:0] NOTE_VEL_0,
	output [6:0] NOTE_VEL_1,
	output [6:0] NOTE_VEL_2,
	output [6:0] NOTE_VEL_3,
);

wire write_note_0;
wire write_note_1;
wire write_note_2;
wire write_note_3;

wire clr_note_0;
wire clr_note_1;
wire clr_note_2;
wire clr_note_3;





register_clr #(
	.W(7)
)
NOTE_NUM_0
(
	.CLK(CLK),
	.CE(write_note_0)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_0)
);

register_clr #(
	.W(7)
)
NOTE_NUM_1
(
	.CLK(CLK),
	.CE(write_note_1)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_1)
);

register_clr #(
	.W(7)
)
NOTE_NUM_2
(
	.CLK(CLK),
	.CE(write_note_2)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_2)
);

register_clr #(
	.W(7)
)
NOTE_NUM_3
(
	.CLK(CLK),
	.CE(write_note_3)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_3)
);


register_clr #(
	.W(7)
)
NOTE_VEL_0
(
	.CLK(CLK),
	.CE(write_note_0)
	.CLR(RST | clr_note_0),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_0)
);

register_clr #(
	.W(7)
)
NOTE_VEL_1
(
	.CLK(CLK),
	.CE(write_note_1)
	.CLR(RST | clr_note_1),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_1)
);

register_clr #(
	.W(7)
)
NOTE_VEL_2
(
	.CLK(CLK),
	.CE(write_note_2)
	.CLR(RST | clr_note_2),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_2)
);

register_clr #(
	.W(7)
)
NOTE_VEL_3
(
	.CLK(CLK),
	.CE(write_note_3)
	.CLR(RST | clr_note_3),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_3)
);


always @(posedge CLK) 
	if(CE)
		if (HANDLE_NOTE && NOTE_ON)
			if (~|NOTE_VEL_0)
				write_note_0 = 1'b1;

			else if(~|NOTE_VEL_1)
				write_note_1 = 1'b1;

			else if(~|NOTE_VEL_2)
				write_note_2 = 1'b1;

			else if(~|NOTE_VEL_3)
				write_note_3 = 1'b1;
			
			else begin
				write_note_0 = 1'b0;
				write_note_1 = 1'b0;
				write_note_2 = 1'b0;
				write_note_3 = 1'b0;
			end
		else begin
			write_note_0 = 1'b0;
			write_note_1 = 1'b0;
			write_note_2 = 1'b0;
			write_note_3 = 1'b0;
		end		


always @(posedge CLK)
	if(CE)
		if(HANDLE_NOTE && NOTE_OFF)
			if (NOTE_NUM == NOTE_NUM_0)
				clr_note_0 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_1)
				clr_note_1 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_2)
				clr_note_2 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_3)
				clr_note_3 = 1'b1;	

			else begin
				clr_note_0 = 1'b0;
				clr_note_1 = 1'b0;
				clr_note_2 = 1'b0;
				clr_note_3 = 1'b0;
			end
		else begin
				clr_note_0 = 1'b0;
				clr_note_1 = 1'b0;
				clr_note_2 = 1'b0;
				clr_note_3 = 1'b0;
		end

endmodule
module polyphony (
	input CLK,
	input CE,
	input RST,
	input [6:0] NOTE_NUM,
	input [6:0] NOTE_VEL,
	input HANDLE_NOTE,
	input NOTE_ON,
	input NOTE_OFF,
	output [6:0] NOTE_NUM_0,
	output [6:0] NOTE_NUM_1,
	output [6:0] NOTE_NUM_2,
	output [6:0] NOTE_NUM_3,
	output [6:0] NOTE_VEL_0,
	output [6:0] NOTE_VEL_1,
	output [6:0] NOTE_VEL_2,
	output [6:0] NOTE_VEL_3,
);


wire write_note_0;
wire write_note_1;
wire write_note_2;
wire write_note_3;

wire clr_note_0;
wire clr_note_1;
wire clr_note_2;
wire clr_note_3;





register_clr #(
	.W(7)
)
NOTE_NUM_0
(
	.CLK(CLK),
	.CE(write_note_0)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_0)
);

register_clr #(
	.W(7)
)
NOTE_NUM_1
(
	.CLK(CLK),
	.CE(write_note_1)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_1)
);

register_clr #(
	.W(7)
)
NOTE_NUM_2
(
	.CLK(CLK),
	.CE(write_note_2)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_2)
);

register_clr #(
	.W(7)
)
NOTE_NUM_3
(
	.CLK(CLK),
	.CE(write_note_3)
	.CLR(RST),
	.D(NOTE_NUM),
	.Q(NOTE_NUM_3)
);


register_clr #(
	.W(7)
)
NOTE_VEL_0
(
	.CLK(CLK),
	.CE(write_note_0)
	.CLR(RST | clr_note_0),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_0)
);

register_clr #(
	.W(7)
)
NOTE_VEL_1
(
	.CLK(CLK),
	.CE(write_note_1)
	.CLR(RST | clr_note_1),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_1)
);

register_clr #(
	.W(7)
)
NOTE_VEL_2
(
	.CLK(CLK),
	.CE(write_note_2)
	.CLR(RST | clr_note_2),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_2)
);

register_clr #(
	.W(7)
)
NOTE_VEL_3
(
	.CLK(CLK),
	.CE(write_note_3)
	.CLR(RST | clr_note_3),
	.D(NOTE_VEL),
	.Q(NOTE_VEL_3)
);


always @(posedge CLK) 
	if(CE)
		if (HANDLE_NOTE && NOTE_ON)
			if (~|NOTE_VEL_0)
				write_note_0 = 1'b1;

			else if(~|NOTE_VEL_1)
				write_note_1 = 1'b1;

			else if(~|NOTE_VEL_2)
				write_note_2 = 1'b1;

			else if(~|NOTE_VEL_3)
				write_note_3 = 1'b1;
			
			else begin
				write_note_0 = 1'b0;
				write_note_1 = 1'b0;
				write_note_2 = 1'b0;
				write_note_3 = 1'b0;
			end
		else begin
			write_note_0 = 1'b0;
			write_note_1 = 1'b0;
			write_note_2 = 1'b0;
			write_note_3 = 1'b0;
		end		


always @(posedge CLK)
	if(CE)
		if(HANDLE_NOTE && NOTE_OFF)
			if (NOTE_NUM == NOTE_NUM_0)
				clr_note_0 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_1)
				clr_note_1 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_2)
				clr_note_2 = 1'b1;

			else if (NOTE_NUM == NOTE_NUM_3)
				clr_note_3 = 1'b1;	

			else begin
				clr_note_0 = 1'b0;
				clr_note_1 = 1'b0;
				clr_note_2 = 1'b0;
				clr_note_3 = 1'b0;
			end
		else begin
				clr_note_0 = 1'b0;
				clr_note_1 = 1'b0;
				clr_note_2 = 1'b0;
				clr_note_3 = 1'b0;
		end

endmodule