data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/function_syntax.v
data/verilator_xmls/09ea2d4a-6eb3-4e49-b57a-fc74cc4db726.xml
module function_syntax (clock, a, b, c );

input clock;
input a;
input b;
output c;



function [1:1] xor_them;
input x;
input y;
reg regz;

	begin
		xor_them = x ^ y;
	end
endfunction

assign c = xor_them(a,b);

endmodule
module function_syntax (clock, a, b, c );


input clock;
input a;
input b;
output c;



function [1:1] xor_them;
input x;
input y;
reg regz;

	begin
		xor_them = x ^ y;
	end
endfunction

assign c = xor_them(a,b);

endmodule