data/full_repos/permissive/484765019/BIST/LFSR_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/LFSR_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/LFSR_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Error: data/full_repos/permissive/484765019/BIST/LFSR_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("LFSR_tb.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/484765019/BIST/LFSR_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/LFSR_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk; \n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LFSR_tb (
	
);

parameter bits = 4;

reg clk = 0;
reg [bits-1:0] seed = 1;
reg n_rst = 0;

wire [bits:1] out;
wire done;

initial begin 
	# 10;
	seed = 4'b0011;
	n_rst = 0;
	# 10;
	n_rst = 1;
	seed = 4'b0011;
end

initial begin 
	$dumpfile("LFSR_tb.vcd"); 
	$dumpvars;
end

LFSR #(.NUM_BITS(bits)) LFSR1(.clk(clk), .n_rst(n_rst), 
	.seed(seed), .out(out), .LFSR_Done(done));

always @(*) begin
	#10 clk <= ~clk; 
end

endmodule
module LFSR_tb (
	
);


parameter bits = 4;

reg clk = 0;
reg [bits-1:0] seed = 1;
reg n_rst = 0;

wire [bits:1] out;
wire done;

initial begin 
	# 10;
	seed = 4'b0011;
	n_rst = 0;
	# 10;
	n_rst = 1;
	seed = 4'b0011;
end

initial begin 
	$dumpfile("LFSR_tb.vcd"); 
	$dumpvars;
end

LFSR #(.NUM_BITS(bits)) LFSR1(.clk(clk), .n_rst(n_rst), 
	.seed(seed), .out(out), .LFSR_Done(done));

always @(*) begin
	#10 clk <= ~clk; 
end

endmodule