data/full_repos/permissive/517239653/one_shot.v
data/verilator_xmls/283bc667-8725-4963-9faa-a7ab6a1ffb17.xml
module one_shot(pulse, clk, trigger, edges);

parameter PULSE_DURATION = 4;

output reg pulse;
input clk;
input trigger;
input [1:0] edges;

reg pulse_reg = 'b0;
reg last_trigger_reg = 'b0;
reg [31:0] pulse_width_counter = 'b0;

always @(posedge clk) begin
    if(pulse) begin

        if(pulse_width_counter == PULSE_DURATION) begin
            pulse <= 'b0;
        end
        pulse_width_counter <= pulse_width_counter + 1;
    end else begin
        case(edges)
            'b00: begin

                pulse <= 'b0;
            end
            'b01: begin

                if(!trigger && last_trigger_reg) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
            'b10: begin

                if(trigger && !last_trigger_reg) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
            'b11: begin

                if ((trigger && !last_trigger_reg) || (!trigger && last_trigger_reg)) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
        endcase
        
        last_trigger_reg <= trigger;
    end
    
    
end

endmodule
module one_shot(pulse, clk, trigger, edges);


parameter PULSE_DURATION = 4;

output reg pulse;
input clk;
input trigger;
input [1:0] edges;

reg pulse_reg = 'b0;
reg last_trigger_reg = 'b0;
reg [31:0] pulse_width_counter = 'b0;

always @(posedge clk) begin
    if(pulse) begin

        if(pulse_width_counter == PULSE_DURATION) begin
            pulse <= 'b0;
        end
        pulse_width_counter <= pulse_width_counter + 1;
    end else begin
        case(edges)
            'b00: begin

                pulse <= 'b0;
            end
            'b01: begin

                if(!trigger && last_trigger_reg) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
            'b10: begin

                if(trigger && !last_trigger_reg) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
            'b11: begin

                if ((trigger && !last_trigger_reg) || (!trigger && last_trigger_reg)) begin
                    pulse_width_counter <= 32'b1;
                    pulse <= 'b1;
                end
            end
        endcase
        
        last_trigger_reg <= trigger;
    end
    
    
end

endmodule