data/full_repos/permissive/492462267/ex.v
1: b'%Error: data/full_repos/permissive/492462267/ex.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/ex.v:11: Define or directive not defined: \'`AluOpBus\'\n    input   wire[`AluOpBus]     aluop_i,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`AluOpBus]     aluop_i,\n                          ^\n%Error: data/full_repos/permissive/492462267/ex.v:12: Define or directive not defined: \'`AluSelBus\'\n    input   wire[`AluSelBus]    alusel_i,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:13: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   data1_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:14: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   data2_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:15: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   waddr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegDataBus]   hi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:19: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   hi_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:20: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   lo_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegDataBus]   mem_hi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:22: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_hi_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:23: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_lo_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegDataBus]   wb_hi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:25: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   wb_hi_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:26: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   wb_lo_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegDataBus]    hi_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:28: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    hi_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:29: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    lo_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]    waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:33: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:34: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    result_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:40: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     logic_out;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     logic_out;\n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:41: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     shift_out;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     shift_out;\n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:42: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     move_out;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     move_out;\n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:43: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     arith_out;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     arith_out;\n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:44: Define or directive not defined: \'`DoubleWordBus\'\nreg[`DoubleWordBus]  mul_out;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`DoubleWordBus]  mul_out;\n                  ^\n%Error: data/full_repos/permissive/492462267/ex.v:46: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     HI;      \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     HI;      \n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:47: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]     LO;      \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]     LO;      \n               ^\n%Error: data/full_repos/permissive/492462267/ex.v:53: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]       data2_mux;   \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]       data2_mux;   \n                ^\n%Error: data/full_repos/permissive/492462267/ex.v:54: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]       data1_not;   \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]       data1_not;   \n                ^\n%Error: data/full_repos/permissive/492462267/ex.v:55: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]       result_sum;  \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]       result_sum;  \n                ^\n%Error: data/full_repos/permissive/492462267/ex.v:56: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]       op1_mult;    \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]       op1_mult;    \n                ^\n%Error: data/full_repos/permissive/492462267/ex.v:57: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]       op2_mult;    \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]       op2_mult;    \n                ^\n%Error: data/full_repos/permissive/492462267/ex.v:58: Define or directive not defined: \'`DoubleWordBus\'\nwire[`DoubleWordBus]    hilo_temp;   \n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`DoubleWordBus]    hilo_temp;   \n                   ^\n%Error: data/full_repos/permissive/492462267/ex.v:66: Define or directive not defined: \'`EXE_SUB_OP\'\nassign data2_mux = ( (aluop_i == `EXE_SUB_OP) \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex.v:67: Define or directive not defined: \'`EXE_SUBU_OP\'\n                        || (aluop_i == `EXE_SUBU_OP)\n                                       ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex (
    input   wire    rst,


    input   wire[`AluOpBus]     aluop_i,
    input   wire[`AluSelBus]    alusel_i,
    input   wire[`RegDataBus]   data1_i,
    input   wire[`RegDataBus]   data2_i,
    input   wire[`RegAddrBus]   waddr_i,
    input   wire                we_i,


    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,
    input   wire                mem_whilo_i,
    input   wire[`RegDataBus]   mem_hi_i,
    input   wire[`RegDataBus]   mem_lo_i,
    input   wire                wb_whilo_i,
    input   wire[`RegDataBus]   wb_hi_i,
    input   wire[`RegDataBus]   wb_lo_i,
    output  reg                 whilo_o,
    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o,


    output  reg                 we_o,
    output  reg[`RegAddrBus]    waddr_o,
    output  reg[`RegDataBus]    result_o,

    output  reg                 stallreq
);


reg[`RegDataBus]     logic_out;
reg[`RegDataBus]     shift_out;
reg[`RegDataBus]     move_out;
reg[`RegDataBus]     arith_out;
reg[`DoubleWordBus]  mul_out;

reg[`RegDataBus]     HI;
reg[`RegDataBus]     LO;


wire data1_eq_data2;
wire data1_lt_data2;
wire over_sum;
wire[`RegDataBus]       data2_mux;
wire[`RegDataBus]       data1_not;
wire[`RegDataBus]       result_sum;
wire[`RegDataBus]       op1_mult;
wire[`RegDataBus]       op2_mult;
wire[`DoubleWordBus]    hilo_temp;



assign data2_mux = ( (aluop_i == `EXE_SUB_OP) 
                        || (aluop_i == `EXE_SUBU_OP)
                        || (aluop_i == `EXE_SLT_OP) 
                        ? (~data2_i + 1) : data2_i );

assign result_sum = data1_i + data2_mux;


assign over_sum = ( data1_i[31] && data2_mux[31] && !result_sum[31] )
                    ||  ( !data1_i[31] && !data2_mux[31] && result_sum[31] );


assign data1_lt_data2 = ( aluop_i == `EXE_SLT_OP) ?
                            ( (  data1_i[31] && !data2_i[31])
                            || ( data1_i[31] &&  data2_i[31] && result_sum[31])
                            || (!data1_i[31] && !data2_i[31] && result_sum[31]) )
                            : (data1_i < data2_i);


assign data1_not = ~data1_i;




always@(*) begin
    if(rst) begin
        {HI,LO} = { `ZeroWord,`ZeroWord };
    end else if (mem_whilo_i) begin
        {HI,LO} = { mem_hi_i, mem_lo_i };
    end else if(wb_whilo_i) begin
        {HI,LO} = { wb_hi_i, wb_lo_i };
    end else begin
        {HI,LO} = { hi_i, lo_i};
    end
end


always @(*) begin
    if(rst) begin
        arith_out = `ZeroWord;
    end else begin
        case(aluop_i)
            `EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
                arith_out = result_sum;
            end
            `EXE_SUB_OP, `EXE_SUBU_OP: begin
                arith_out = result_sum;
            end
            `EXE_SLT_OP, `EXE_SLTU_OP: begin
                arith_out = data1_lt_data2;
            end
            `EXE_CLO_OP: begin
                arith_out = data1_not[31] ? 0 : data1_not[30] ? 1 : data1_not[29] ? 2 :
													 data1_not[28] ? 3 : data1_not[27] ? 4 : data1_not[26] ? 5 :
													 data1_not[25] ? 6 : data1_not[24] ? 7 : data1_not[23] ? 8 : 
													 data1_not[22] ? 9 : data1_not[21] ? 10 : data1_not[20] ? 11 :
													 data1_not[19] ? 12 : data1_not[18] ? 13 : data1_not[17] ? 14 : 
													 data1_not[16] ? 15 : data1_not[15] ? 16 : data1_not[14] ? 17 : 
													 data1_not[13] ? 18 : data1_not[12] ? 19 : data1_not[11] ? 20 :
													 data1_not[10] ? 21 : data1_not[9] ? 22 : data1_not[8] ? 23 : 
													 data1_not[7] ? 24 : data1_not[6] ? 25 : data1_not[5] ? 26 : 
													 data1_not[4] ? 27 : data1_not[3] ? 28 : data1_not[2] ? 29 : 
													 data1_not[1] ? 30 : data1_not[0] ? 31 : 32 ;
            end
            `EXE_CLZ_OP: begin
                arith_out = data1_i[31] ? 0 : data1_i[30] ? 1 : data1_i[29] ? 2 :
													 data1_i[28] ? 3 : data1_i[27] ? 4 : data1_i[26] ? 5 :
													 data1_i[25] ? 6 : data1_i[24] ? 7 : data1_i[23] ? 8 : 
													 data1_i[22] ? 9 : data1_i[21] ? 10 : data1_i[20] ? 11 :
													 data1_i[19] ? 12 : data1_i[18] ? 13 : data1_i[17] ? 14 : 
													 data1_i[16] ? 15 : data1_i[15] ? 16 : data1_i[14] ? 17 : 
													 data1_i[13] ? 18 : data1_i[12] ? 19 : data1_i[11] ? 20 :
													 data1_i[10] ? 21 : data1_i[9] ? 22 : data1_i[8] ? 23 : 
													 data1_i[7] ? 24 : data1_i[6] ? 25 : data1_i[5] ? 26 : 
													 data1_i[4] ? 27 : data1_i[3] ? 28 : data1_i[2] ? 29 : 
													 data1_i[1] ? 30 : data1_i[0] ? 31 : 32 ;
            end
            default begin
                arith_out = `ZeroWord;
            end
        endcase
    end
end


assign op1_mult = ( (aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) )
                                                && data1_i[31]  
                    ? (~data1_i + 1) : data1_i ;

assign op2_mult = ( (aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) )
                                                && data2_i[31]  
                    ? (~data2_i + 1) : data2_i ;

assign hilo_temp = op1_mult * op2_mult;


always @(*) begin
    if(rst) begin
        mul_out = `DoubleZero;
    end else if( ( aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ) begin     

        if(data1_i[31] ^ data2_i[31]) begin
            mul_out = ~hilo_temp + 1;
        end else begin
            mul_out = hilo_temp;
        end

    end else begin
        mul_out = hilo_temp;
    end
end




 always @(*) begin
     if (rst) begin
         move_out = `ZeroWord;
     end else begin
         move_out = `ZeroWord;
         case(aluop_i)
            `EXE_MOVN_OP:begin
                move_out = data1_i;
            end
            `EXE_MOVZ_OP:begin
                move_out = data1_i;
            end
            `EXE_MFHI_OP:begin
                move_out = HI;
            end
            `EXE_MFLO_OP:begin
                move_out = LO;
            end
            default begin
                move_out = `ZeroWord;
            end
        endcase
     end
 end


always @(*) begin
    if(rst) begin
        logic_out = `ZeroWord;
    end else begin
        case (aluop_i)
            `EXE_AND_OP: begin
                logic_out = data1_i & data2_i;
            end
            `EXE_OR_OP : begin
                logic_out = data1_i | data2_i;
            end
            `EXE_NOR_OP: begin
                logic_out = ~(data1_i | data2_i);
            end
            `EXE_XOR   : begin
                logic_out = data1_i ^ data2_i;
            end
            default:begin
                logic_out = `ZeroWord;
            end
        endcase
    end
end


always @(*) begin
    if(rst) begin
        shift_out = `ZeroWord;
    end else begin
        case (aluop_i)
            `EXE_SLL_OP: begin
                shift_out = data2_i << data1_i[4:0];
            end
            `EXE_SRL_OP : begin
                shift_out = data2_i >> data1_i[4:0];
            end
            `EXE_SRA_OP : begin
                shift_out = ( { 32{data2_i[31]} } << ~data1_i[4:0] ) | (data2_i >> data1_i[4:0]);
            end
            default:begin
                shift_out = `ZeroWord;
            end
        endcase
    end
end



always @(*) begin
    
    waddr_o = waddr_i;


    if ( (aluop_i == `EXE_ADD_OP || aluop_i == `EXE_SUB_OP)
            && over_sum ) begin
        we_o = `Disable;
    end else begin
        we_o = we_i;
    end
    
    case (alusel_i)
        `EXE_RES_LOGIC: begin
            result_o = logic_out;
        end
        `EXE_RES_SHIFT: begin
            result_o = shift_out;
        end
        `EXE_RES_MOVE: begin
            result_o = move_out;
        end
        `EXE_RES_ARITHMETIC: begin
            result_o = arith_out;
        end
        `EXE_RES_MUL: begin
            result_o = mul_out[31:0];
        end
        default:begin
            result_o = `ZeroWord;
        end
    endcase
    
end



always @(*) begin
    if(rst) begin
        whilo_o = `Disable;
        hi_o    = `ZeroWord;
        lo_o    = `ZeroWord;
    end else begin
        case(aluop_i)
            `EXE_MTHI_OP:begin
                whilo_o = `Enable;
                hi_o    = data1_i;
                lo_o    = LO;
            end       
            `EXE_MTLO_OP:begin
                whilo_o = `Enable;
                hi_o    = HI;
                lo_o    = data1_i;
            end
            `EXE_MULT_OP, `EXE_MULTU_OP: begin
                whilo_o = `Enable;                  
                hi_o    = mul_out[63:32];
                lo_o    = mul_out[31:0];
            end
            default begin
                whilo_o = `Disable;
                hi_o    = `ZeroWord;
                lo_o    = `ZeroWord;
            end
        endcase
    end
end


endmodule
module ex (
    input   wire    rst,


    input   wire[`AluOpBus]     aluop_i,
    input   wire[`AluSelBus]    alusel_i,
    input   wire[`RegDataBus]   data1_i,
    input   wire[`RegDataBus]   data2_i,
    input   wire[`RegAddrBus]   waddr_i,
    input   wire                we_i,


    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,
    input   wire                mem_whilo_i,
    input   wire[`RegDataBus]   mem_hi_i,
    input   wire[`RegDataBus]   mem_lo_i,
    input   wire                wb_whilo_i,
    input   wire[`RegDataBus]   wb_hi_i,
    input   wire[`RegDataBus]   wb_lo_i,
    output  reg                 whilo_o,
    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o,


    output  reg                 we_o,
    output  reg[`RegAddrBus]    waddr_o,
    output  reg[`RegDataBus]    result_o,

    output  reg                 stallreq
);



reg[`RegDataBus]     logic_out;
reg[`RegDataBus]     shift_out;
reg[`RegDataBus]     move_out;
reg[`RegDataBus]     arith_out;
reg[`DoubleWordBus]  mul_out;

reg[`RegDataBus]     HI;
reg[`RegDataBus]     LO;


wire data1_eq_data2;
wire data1_lt_data2;
wire over_sum;
wire[`RegDataBus]       data2_mux;
wire[`RegDataBus]       data1_not;
wire[`RegDataBus]       result_sum;
wire[`RegDataBus]       op1_mult;
wire[`RegDataBus]       op2_mult;
wire[`DoubleWordBus]    hilo_temp;



assign data2_mux = ( (aluop_i == `EXE_SUB_OP) 
                        || (aluop_i == `EXE_SUBU_OP)
                        || (aluop_i == `EXE_SLT_OP) 
                        ? (~data2_i + 1) : data2_i );

assign result_sum = data1_i + data2_mux;


assign over_sum = ( data1_i[31] && data2_mux[31] && !result_sum[31] )
                    ||  ( !data1_i[31] && !data2_mux[31] && result_sum[31] );


assign data1_lt_data2 = ( aluop_i == `EXE_SLT_OP) ?
                            ( (  data1_i[31] && !data2_i[31])
                            || ( data1_i[31] &&  data2_i[31] && result_sum[31])
                            || (!data1_i[31] && !data2_i[31] && result_sum[31]) )
                            : (data1_i < data2_i);


assign data1_not = ~data1_i;




always@(*) begin
    if(rst) begin
        {HI,LO} = { `ZeroWord,`ZeroWord };
    end else if (mem_whilo_i) begin
        {HI,LO} = { mem_hi_i, mem_lo_i };
    end else if(wb_whilo_i) begin
        {HI,LO} = { wb_hi_i, wb_lo_i };
    end else begin
        {HI,LO} = { hi_i, lo_i};
    end
end


always @(*) begin
    if(rst) begin
        arith_out = `ZeroWord;
    end else begin
        case(aluop_i)
            `EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
                arith_out = result_sum;
            end
            `EXE_SUB_OP, `EXE_SUBU_OP: begin
                arith_out = result_sum;
            end
            `EXE_SLT_OP, `EXE_SLTU_OP: begin
                arith_out = data1_lt_data2;
            end
            `EXE_CLO_OP: begin
                arith_out = data1_not[31] ? 0 : data1_not[30] ? 1 : data1_not[29] ? 2 :
													 data1_not[28] ? 3 : data1_not[27] ? 4 : data1_not[26] ? 5 :
													 data1_not[25] ? 6 : data1_not[24] ? 7 : data1_not[23] ? 8 : 
													 data1_not[22] ? 9 : data1_not[21] ? 10 : data1_not[20] ? 11 :
													 data1_not[19] ? 12 : data1_not[18] ? 13 : data1_not[17] ? 14 : 
													 data1_not[16] ? 15 : data1_not[15] ? 16 : data1_not[14] ? 17 : 
													 data1_not[13] ? 18 : data1_not[12] ? 19 : data1_not[11] ? 20 :
													 data1_not[10] ? 21 : data1_not[9] ? 22 : data1_not[8] ? 23 : 
													 data1_not[7] ? 24 : data1_not[6] ? 25 : data1_not[5] ? 26 : 
													 data1_not[4] ? 27 : data1_not[3] ? 28 : data1_not[2] ? 29 : 
													 data1_not[1] ? 30 : data1_not[0] ? 31 : 32 ;
            end
            `EXE_CLZ_OP: begin
                arith_out = data1_i[31] ? 0 : data1_i[30] ? 1 : data1_i[29] ? 2 :
													 data1_i[28] ? 3 : data1_i[27] ? 4 : data1_i[26] ? 5 :
													 data1_i[25] ? 6 : data1_i[24] ? 7 : data1_i[23] ? 8 : 
													 data1_i[22] ? 9 : data1_i[21] ? 10 : data1_i[20] ? 11 :
													 data1_i[19] ? 12 : data1_i[18] ? 13 : data1_i[17] ? 14 : 
													 data1_i[16] ? 15 : data1_i[15] ? 16 : data1_i[14] ? 17 : 
													 data1_i[13] ? 18 : data1_i[12] ? 19 : data1_i[11] ? 20 :
													 data1_i[10] ? 21 : data1_i[9] ? 22 : data1_i[8] ? 23 : 
													 data1_i[7] ? 24 : data1_i[6] ? 25 : data1_i[5] ? 26 : 
													 data1_i[4] ? 27 : data1_i[3] ? 28 : data1_i[2] ? 29 : 
													 data1_i[1] ? 30 : data1_i[0] ? 31 : 32 ;
            end
            default begin
                arith_out = `ZeroWord;
            end
        endcase
    end
end


assign op1_mult = ( (aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) )
                                                && data1_i[31]  
                    ? (~data1_i + 1) : data1_i ;

assign op2_mult = ( (aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) )
                                                && data2_i[31]  
                    ? (~data2_i + 1) : data2_i ;

assign hilo_temp = op1_mult * op2_mult;


always @(*) begin
    if(rst) begin
        mul_out = `DoubleZero;
    end else if( ( aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ) begin     

        if(data1_i[31] ^ data2_i[31]) begin
            mul_out = ~hilo_temp + 1;
        end else begin
            mul_out = hilo_temp;
        end

    end else begin
        mul_out = hilo_temp;
    end
end




 always @(*) begin
     if (rst) begin
         move_out = `ZeroWord;
     end else begin
         move_out = `ZeroWord;
         case(aluop_i)
            `EXE_MOVN_OP:begin
                move_out = data1_i;
            end
            `EXE_MOVZ_OP:begin
                move_out = data1_i;
            end
            `EXE_MFHI_OP:begin
                move_out = HI;
            end
            `EXE_MFLO_OP:begin
                move_out = LO;
            end
            default begin
                move_out = `ZeroWord;
            end
        endcase
     end
 end


always @(*) begin
    if(rst) begin
        logic_out = `ZeroWord;
    end else begin
        case (aluop_i)
            `EXE_AND_OP: begin
                logic_out = data1_i & data2_i;
            end
            `EXE_OR_OP : begin
                logic_out = data1_i | data2_i;
            end
            `EXE_NOR_OP: begin
                logic_out = ~(data1_i | data2_i);
            end
            `EXE_XOR   : begin
                logic_out = data1_i ^ data2_i;
            end
            default:begin
                logic_out = `ZeroWord;
            end
        endcase
    end
end


always @(*) begin
    if(rst) begin
        shift_out = `ZeroWord;
    end else begin
        case (aluop_i)
            `EXE_SLL_OP: begin
                shift_out = data2_i << data1_i[4:0];
            end
            `EXE_SRL_OP : begin
                shift_out = data2_i >> data1_i[4:0];
            end
            `EXE_SRA_OP : begin
                shift_out = ( { 32{data2_i[31]} } << ~data1_i[4:0] ) | (data2_i >> data1_i[4:0]);
            end
            default:begin
                shift_out = `ZeroWord;
            end
        endcase
    end
end



always @(*) begin
    
    waddr_o = waddr_i;


    if ( (aluop_i == `EXE_ADD_OP || aluop_i == `EXE_SUB_OP)
            && over_sum ) begin
        we_o = `Disable;
    end else begin
        we_o = we_i;
    end
    
    case (alusel_i)
        `EXE_RES_LOGIC: begin
            result_o = logic_out;
        end
        `EXE_RES_SHIFT: begin
            result_o = shift_out;
        end
        `EXE_RES_MOVE: begin
            result_o = move_out;
        end
        `EXE_RES_ARITHMETIC: begin
            result_o = arith_out;
        end
        `EXE_RES_MUL: begin
            result_o = mul_out[31:0];
        end
        default:begin
            result_o = `ZeroWord;
        end
    endcase
    
end



always @(*) begin
    if(rst) begin
        whilo_o = `Disable;
        hi_o    = `ZeroWord;
        lo_o    = `ZeroWord;
    end else begin
        case(aluop_i)
            `EXE_MTHI_OP:begin
                whilo_o = `Enable;
                hi_o    = data1_i;
                lo_o    = LO;
            end       
            `EXE_MTLO_OP:begin
                whilo_o = `Enable;
                hi_o    = HI;
                lo_o    = data1_i;
            end
            `EXE_MULT_OP, `EXE_MULTU_OP: begin
                whilo_o = `Enable;                  
                hi_o    = mul_out[63:32];
                lo_o    = mul_out[31:0];
            end
            default begin
                whilo_o = `Disable;
                hi_o    = `ZeroWord;
                lo_o    = `ZeroWord;
            end
        endcase
    end
end


endmodule