data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v
1: b'%Error: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:38: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/477502690/openmsp430/simulation,data/full_repos/permissive/477502690/timescale.v\n             data/full_repos/permissive/477502690/openmsp430/simulation,data/full_repos/permissive/477502690/timescale.v.v\n             data/full_repos/permissive/477502690/openmsp430/simulation,data/full_repos/permissive/477502690/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:41: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:225: Unsupported: Ignoring delay on this delayed statement.\n     forever #10 CLK_100MHz <= ~CLK_100MHz;  \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:231: Unsupported: Ignoring delay on this delayed statement.\n     #100 RESET    = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:232: Unsupported: Ignoring delay on this delayed statement.\n     #600 RESET    = 1\'b0;\n     ^\n%Error: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:351: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_openMSP430_fpga.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:352: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_openMSP430_fpga);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/477502690/openmsp430/simulation/tb_openMSP430_fpga.v:384: syntax error, unexpected \'@\'\n     @(inst_pc===16\'hffff)\n     ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module  tb_openMSP430_fpga;



wire       [15:0] pc    = dut.openMSP430_0.inst_pc;
wire       [15:0] data_addr    = dut.openMSP430_0.eu_mab;
wire        data_rd    = dut.openMSP430_0.eu_mb_en;
wire       [1:0] data_wr    = dut.openMSP430_0.eu_mb_wr;
wire         hwmod_rst = dut.openMSP430_0.hdmod_0.reset;
wire         versa_rst = dut.openMSP430_0.hdmod_0.VERSA_reset;
wire         vrased_rst = dut.openMSP430_0.hdmod_0.vrased_reset;
wire       v_irq_dma = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_irq_dma;
wire       v_atomicity = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_atomicity;
wire       v_rp_gpio = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_rp_gpio;
wire       v_rp_ekey = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_rp_ekey;
wire       v_wp_ekey = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_wp_ekey;
wire       v_wp_ctr = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_wp_ctr;

wire              enter_rom = pc == 16'hA000;
wire              memcmp = pc == 16'hA094;
wire              auth = pc == 16'hA0AA;
wire              exit_rom = pc == 16'hDFFE;
wire              read_gpio = data_addr == 16'h0018;






reg               CLK_100MHz;
reg               RESET;


reg               SW7;
reg               SW6;
reg               SW5;
reg               SW4;
reg               SW3;
reg               SW2;
reg               SW1;
reg               SW0;


reg               BTN2;
reg               BTN1;
reg               BTN0;



wire              LED7;
wire              LED6;
wire              LED5;
wire              LED4;
wire              LED3;
wire              LED2;
wire              LED1;
wire              LED0;


wire              SEG_A;
wire              SEG_B;
wire              SEG_C;
wire              SEG_D;
wire              SEG_E;
wire              SEG_F;
wire              SEG_G;
wire              SEG_DP;
wire              SEG_AN0;
wire              SEG_AN1;
wire              SEG_AN2;
wire              SEG_AN3;


reg               UART_RXD;
wire              UART_TXD;


wire              JB1;
wire              JC1;
wire              JC2;
wire              JC7;







wire       [15:0] inst_pc;




integer           error;
reg               stimulus_done;










wire         [7:0] p3_din = dut.p3_din;
wire         [7:0] p3_dout = dut.p3_dout;
wire         [7:0] p3_dout_en = dut.p3_dout_en;

wire         [7:0] p1_din = dut.p1_din;
wire         [7:0] p1_dout = dut.p1_dout;
wire         [7:0] p1_dout_en = dut.p1_dout_en;

















wire       [15:0] r0    = dut.openMSP430_0.execution_unit_0.register_file_0.r0;
wire       [15:0] r1    = dut.openMSP430_0.execution_unit_0.register_file_0.r1;
wire       [15:0] r2    = dut.openMSP430_0.execution_unit_0.register_file_0.r2;
wire       [15:0] r3    = dut.openMSP430_0.execution_unit_0.register_file_0.r3;
wire       [15:0] r4    = dut.openMSP430_0.execution_unit_0.register_file_0.r4;
wire       [15:0] r5    = dut.openMSP430_0.execution_unit_0.register_file_0.r5;
wire       [15:0] r6    = dut.openMSP430_0.execution_unit_0.register_file_0.r6;
wire       [15:0] r7    = dut.openMSP430_0.execution_unit_0.register_file_0.r7;
wire       [15:0] r8    = dut.openMSP430_0.execution_unit_0.register_file_0.r8;
wire       [15:0] r9    = dut.openMSP430_0.execution_unit_0.register_file_0.r9;
wire       [15:0] r10   = dut.openMSP430_0.execution_unit_0.register_file_0.r10;
wire       [15:0] r11   = dut.openMSP430_0.execution_unit_0.register_file_0.r11;
wire       [15:0] r12   = dut.openMSP430_0.execution_unit_0.register_file_0.r12;
wire       [15:0] r13   = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
wire       [15:0] r14   = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
wire       [15:0] r15   = dut.openMSP430_0.execution_unit_0.register_file_0.r15;



























  
  




initial
  begin
     CLK_100MHz = 1'b0;
     forever #10 CLK_100MHz <= ~CLK_100MHz;
  end

initial
  begin
     RESET         = 1'b0;
     #100 RESET    = 1'b1;
     #600 RESET    = 1'b0;
  end




initial
  begin
     error         = 0;
     stimulus_done = 1;
     SW7           = 1'b0;
     SW6           = 1'b0;
     SW5           = 1'b0;
     SW4           = 1'b0;
     SW3           = 1'b0;
     SW2           = 1'b0;
     SW1           = 1'b0;
     SW0           = 1'b0;
     BTN2          = 1'b0;
     BTN1          = 1'b0;
     BTN0          = 1'b0;
     UART_RXD      = 1'b0;
  end





openMSP430_fpga dut (


    .CLK_100MHz    (CLK_100MHz),



    .SW7          (SW7),
    .SW6          (SW6),
    .SW5          (SW5),
    .SW4          (SW4),
    .SW3          (SW3),
    .SW2          (SW2),
    .SW1          (SW1),
    .SW0          (SW0),


    .BTN3         (RESET),
    .BTN2         (BTN2),
    .BTN1         (BTN1),
    .BTN0         (BTN0),
    

    .UART_RXD     (UART_RXD),
    .UART_TXD     (UART_TXD),  


    .LED8         (LED8),
    .LED7         (LED7),
    .LED6         (LED6),
    .LED5         (LED5),
    .LED4         (LED4),
    .LED3         (LED3),
    .LED2         (LED2),
    .LED1         (LED1),
    .LED0         (LED0),
    
    

    .JB1          (JB1),
    .JC1          (JC1),
    .JC2          (JC2),
    .JC7          (JC7),


    .SEG_A        (SEG_A),
    .SEG_B        (SEG_B),
    .SEG_C        (SEG_C),
    .SEG_D        (SEG_D),
    .SEG_E        (SEG_E),
    .SEG_F        (SEG_F),
    .SEG_G        (SEG_G),
    .SEG_DP       (SEG_DP),
    .SEG_AN0      (SEG_AN0),
    .SEG_AN1      (SEG_AN1),
    .SEG_AN2      (SEG_AN2),
    .SEG_AN3      (SEG_AN3)
    );

   







initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     `ifdef TRN_FILE
        $recordfile ("tb_openMSP430_fpga.trn");
        $recordvars;
     `else
        $dumpfile("tb_openMSP430_fpga.vcd");
        $dumpvars(0, tb_openMSP430_fpga);
     `endif
   `endif
  end





initial
  begin
     @(inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
	  $display("|               SIMULATION FAILED               |");
	  $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
	  $display("|               SIMULATION FAILED               |");
	  $display("|     (the verilog stimulus didn't complete)    |");
       end
     else 
       begin
	  $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end






   task tb_error;
      input [65*8:0] error_string;
      begin
	 $display("ERROR: %s %t", error_string, $time);
	 error = error+1;
      end
   endtask


endmodule
module  tb_openMSP430_fpga;




wire       [15:0] pc    = dut.openMSP430_0.inst_pc;
wire       [15:0] data_addr    = dut.openMSP430_0.eu_mab;
wire        data_rd    = dut.openMSP430_0.eu_mb_en;
wire       [1:0] data_wr    = dut.openMSP430_0.eu_mb_wr;
wire         hwmod_rst = dut.openMSP430_0.hdmod_0.reset;
wire         versa_rst = dut.openMSP430_0.hdmod_0.VERSA_reset;
wire         vrased_rst = dut.openMSP430_0.hdmod_0.vrased_reset;
wire       v_irq_dma = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_irq_dma;
wire       v_atomicity = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_atomicity;
wire       v_rp_gpio = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_rp_gpio;
wire       v_rp_ekey = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_rp_ekey;
wire       v_wp_ekey = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_wp_ekey;
wire       v_wp_ctr = dut.openMSP430_0.hdmod_0.VERSA_0.VERSA_wp_ctr;

wire              enter_rom = pc == 16'hA000;
wire              memcmp = pc == 16'hA094;
wire              auth = pc == 16'hA0AA;
wire              exit_rom = pc == 16'hDFFE;
wire              read_gpio = data_addr == 16'h0018;






reg               CLK_100MHz;
reg               RESET;


reg               SW7;
reg               SW6;
reg               SW5;
reg               SW4;
reg               SW3;
reg               SW2;
reg               SW1;
reg               SW0;


reg               BTN2;
reg               BTN1;
reg               BTN0;



wire              LED7;
wire              LED6;
wire              LED5;
wire              LED4;
wire              LED3;
wire              LED2;
wire              LED1;
wire              LED0;


wire              SEG_A;
wire              SEG_B;
wire              SEG_C;
wire              SEG_D;
wire              SEG_E;
wire              SEG_F;
wire              SEG_G;
wire              SEG_DP;
wire              SEG_AN0;
wire              SEG_AN1;
wire              SEG_AN2;
wire              SEG_AN3;


reg               UART_RXD;
wire              UART_TXD;


wire              JB1;
wire              JC1;
wire              JC2;
wire              JC7;







wire       [15:0] inst_pc;




integer           error;
reg               stimulus_done;










wire         [7:0] p3_din = dut.p3_din;
wire         [7:0] p3_dout = dut.p3_dout;
wire         [7:0] p3_dout_en = dut.p3_dout_en;

wire         [7:0] p1_din = dut.p1_din;
wire         [7:0] p1_dout = dut.p1_dout;
wire         [7:0] p1_dout_en = dut.p1_dout_en;

















wire       [15:0] r0    = dut.openMSP430_0.execution_unit_0.register_file_0.r0;
wire       [15:0] r1    = dut.openMSP430_0.execution_unit_0.register_file_0.r1;
wire       [15:0] r2    = dut.openMSP430_0.execution_unit_0.register_file_0.r2;
wire       [15:0] r3    = dut.openMSP430_0.execution_unit_0.register_file_0.r3;
wire       [15:0] r4    = dut.openMSP430_0.execution_unit_0.register_file_0.r4;
wire       [15:0] r5    = dut.openMSP430_0.execution_unit_0.register_file_0.r5;
wire       [15:0] r6    = dut.openMSP430_0.execution_unit_0.register_file_0.r6;
wire       [15:0] r7    = dut.openMSP430_0.execution_unit_0.register_file_0.r7;
wire       [15:0] r8    = dut.openMSP430_0.execution_unit_0.register_file_0.r8;
wire       [15:0] r9    = dut.openMSP430_0.execution_unit_0.register_file_0.r9;
wire       [15:0] r10   = dut.openMSP430_0.execution_unit_0.register_file_0.r10;
wire       [15:0] r11   = dut.openMSP430_0.execution_unit_0.register_file_0.r11;
wire       [15:0] r12   = dut.openMSP430_0.execution_unit_0.register_file_0.r12;
wire       [15:0] r13   = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
wire       [15:0] r14   = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
wire       [15:0] r15   = dut.openMSP430_0.execution_unit_0.register_file_0.r15;



























  
  




initial
  begin
     CLK_100MHz = 1'b0;
     forever #10 CLK_100MHz <= ~CLK_100MHz;
  end

initial
  begin
     RESET         = 1'b0;
     #100 RESET    = 1'b1;
     #600 RESET    = 1'b0;
  end




initial
  begin
     error         = 0;
     stimulus_done = 1;
     SW7           = 1'b0;
     SW6           = 1'b0;
     SW5           = 1'b0;
     SW4           = 1'b0;
     SW3           = 1'b0;
     SW2           = 1'b0;
     SW1           = 1'b0;
     SW0           = 1'b0;
     BTN2          = 1'b0;
     BTN1          = 1'b0;
     BTN0          = 1'b0;
     UART_RXD      = 1'b0;
  end





openMSP430_fpga dut (


    .CLK_100MHz    (CLK_100MHz),



    .SW7          (SW7),
    .SW6          (SW6),
    .SW5          (SW5),
    .SW4          (SW4),
    .SW3          (SW3),
    .SW2          (SW2),
    .SW1          (SW1),
    .SW0          (SW0),


    .BTN3         (RESET),
    .BTN2         (BTN2),
    .BTN1         (BTN1),
    .BTN0         (BTN0),
    

    .UART_RXD     (UART_RXD),
    .UART_TXD     (UART_TXD),  


    .LED8         (LED8),
    .LED7         (LED7),
    .LED6         (LED6),
    .LED5         (LED5),
    .LED4         (LED4),
    .LED3         (LED3),
    .LED2         (LED2),
    .LED1         (LED1),
    .LED0         (LED0),
    
    

    .JB1          (JB1),
    .JC1          (JC1),
    .JC2          (JC2),
    .JC7          (JC7),


    .SEG_A        (SEG_A),
    .SEG_B        (SEG_B),
    .SEG_C        (SEG_C),
    .SEG_D        (SEG_D),
    .SEG_E        (SEG_E),
    .SEG_F        (SEG_F),
    .SEG_G        (SEG_G),
    .SEG_DP       (SEG_DP),
    .SEG_AN0      (SEG_AN0),
    .SEG_AN1      (SEG_AN1),
    .SEG_AN2      (SEG_AN2),
    .SEG_AN3      (SEG_AN3)
    );

   







initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     `ifdef TRN_FILE
        $recordfile ("tb_openMSP430_fpga.trn");
        $recordvars;
     `else
        $dumpfile("tb_openMSP430_fpga.vcd");
        $dumpvars(0, tb_openMSP430_fpga);
     `endif
   `endif
  end





initial
  begin
     @(inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
	  $display("|               SIMULATION FAILED               |");
	  $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
	  $display("|               SIMULATION FAILED               |");
	  $display("|     (the verilog stimulus didn't complete)    |");
       end
     else 
       begin
	  $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end






   task tb_error;
      input [65*8:0] error_string;
      begin
	 $display("ERROR: %s %t", error_string, $time);
	 error = error+1;
      end
   endtask


endmodule