data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration first part/layer.v
1: b'%Error: Cannot find file containing module: first\n        ... Looked in:\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first.v\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first.sv\n             first\n             first.v\n             first.sv\n             obj_dir/first\n             obj_dir/first.v\n             obj_dir/first.sv\n%Error: Cannot find file containing module: part,data/full_repos/permissive/529176308\n%Error: Cannot find file containing module: data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration\n%Error: Cannot find file containing module: part/layer.v\n%Error: Exiting due to 4 error(s)\n'
module layer(clk,reset,input_fc,weights,output_fc);

parameter DATA_WIDTH = 32;
parameter INPUT_NODES = 100;
parameter OUTPUT_NODES = 32;

input clk, reset;
input [DATA_WIDTH*INPUT_NODES-1:0] input_fc;
input [DATA_WIDTH*OUTPUT_NODES-1:0] weights;
output [DATA_WIDTH*OUTPUT_NODES-1:0] output_fc;

reg [DATA_WIDTH-1:0] selectedInput;
integer j;

genvar i;

generate
	for (i = 0; i < OUTPUT_NODES; i = i + 1) begin
		processingElement PE 
		(
			.clk(clk),
			.reset(reset),
			.floatA(selectedInput),
			.floatB(weights[DATA_WIDTH*i+:DATA_WIDTH]),
			.result(output_fc[DATA_WIDTH*i+:DATA_WIDTH])
		);
	end
endgenerate

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1) begin
		selectedInput = 0;
		j = INPUT_NODES - 1;
	end else if (j < 0) begin
		selectedInput = 0;
	end else begin
		selectedInput = input_fc[DATA_WIDTH*j+:DATA_WIDTH];
		j = j - 1;
	end
end

endmodule
module layer(clk,reset,input_fc,weights,output_fc);


parameter DATA_WIDTH = 32;
parameter INPUT_NODES = 100;
parameter OUTPUT_NODES = 32;

input clk, reset;
input [DATA_WIDTH*INPUT_NODES-1:0] input_fc;
input [DATA_WIDTH*OUTPUT_NODES-1:0] weights;
output [DATA_WIDTH*OUTPUT_NODES-1:0] output_fc;

reg [DATA_WIDTH-1:0] selectedInput;
integer j;

genvar i;

generate
	for (i = 0; i < OUTPUT_NODES; i = i + 1) begin
		processingElement PE 
		(
			.clk(clk),
			.reset(reset),
			.floatA(selectedInput),
			.floatB(weights[DATA_WIDTH*i+:DATA_WIDTH]),
			.result(output_fc[DATA_WIDTH*i+:DATA_WIDTH])
		);
	end
endgenerate

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1) begin
		selectedInput = 0;
		j = INPUT_NODES - 1;
	end else if (j < 0) begin
		selectedInput = 0;
	end else begin
		selectedInput = input_fc[DATA_WIDTH*j+:DATA_WIDTH];
		j = j - 1;
	end
end

endmodule