data/full_repos/permissive/487568919/basic_verilog/leave_one_hot.sv
data/verilator_xmls/ddec8cb1-4a29-464c-98fe-0a8657cf98ad.xml
module leave_one_hot #( parameter
  WIDTH = 32
)(
  input [WIDTH-1:0] in,
  output logic [WIDTH-1:0] out
);


genvar i;
generate
  for( i=1; i<WIDTH; i++ ) begin : gen_for

    always_comb begin
        out[i] <= in[i] && ~( |in[(i-1):0] );
    end

  end
endgenerate

assign out[0] = in[0];

endmodule
module leave_one_hot #( parameter
  WIDTH = 32
)(
  input [WIDTH-1:0] in,
  output logic [WIDTH-1:0] out
);



genvar i;
generate
  for( i=1; i<WIDTH; i++ ) begin : gen_for

    always_comb begin
        out[i] <= in[i] && ~( |in[(i-1):0] );
    end

  end
endgenerate

assign out[0] = in[0];

endmodule