data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5 CLK = ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:45: syntax error, unexpected \'@\'\n        @(negedge CLK);  \n        ^\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:53: syntax error, unexpected \'@\'\n            @(negedge CLK);\n            ^\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:66: Unsupported or unknown PLI call: $srandom\n        $srandom(42);  \n        ^~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:70: Unsupported or unknown PLI call: $urandom\n            D = $urandom;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:74: syntax error, unexpected \'@\'\n            @(negedge CLK);\n            ^\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:85: Unsupported or unknown PLI call: $urandom\n        D = $urandom;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/register_set/regset_tb.v:89: syntax error, unexpected \'@\'\n        @(negedge CLK);\n        ^\n%Error: Exiting due to 7 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regset_tb();


    reg CLK;
    reg RES;
    reg write_enable;
    reg [31 : 0] D;
    reg [4 : 0] A_D;
    reg [4 : 0] A_Q0;
    reg [4 : 0] A_Q1;
    

    wire [31 : 0] Q0;
    wire [31 : 0] Q1;
    
    integer i;
    

    regset dut(.CLK(CLK),
               .RES(RES),
               .write_enable(write_enable),
               .D(D),
               .A_D(A_D),
               .A_Q0(A_Q0),
               .A_Q1(A_Q1),
               .Q0(Q0),
               .Q1(Q1));
    

    initial begin 
        CLK = 1'b0;
    end
    

    always begin
        #5 CLK = ~CLK;
    end    
    

   initial begin
        
        RES = 1;
        @(negedge CLK);
        RES = 0;
        

        for(i = 0; i < 32; i = i + 1)
        begin
        
            A_Q0 = i; A_Q1 = i;
            @(negedge CLK);
            
            if(Q0 != 32'd0 || Q1 != 32'd0)
            begin
                $display("Fault in Reset");
                $finish;
            end    
            
        end
        
        $display("Reset test passed!");
        

        $srandom(42);
        
        for(i = 1; i < 32; i = i + 1)
        begin
            D = $urandom;
            A_D = i;
            write_enable = 1'b1; 
            A_Q0 = i; A_Q1 = i;
            @(negedge CLK);
            write_enable = 1'b0;
            if(Q0 != D && Q0 != D) begin
                $display("Fault in General Purpose read/write");
                $finish;
            end            
        end
        
        $display("General Purpose read/write passed!");
        

        D = $urandom;
        A_D = 5'd0;
        write_enable = 1'b1; 
        A_Q0 = 5'd0; A_Q1 = 5'd0;
        @(negedge CLK);
        write_enable = 1'b0;
        if(Q0 != 32'd0 && Q0 != 32'd0) begin
            $display("Fault in R0 read/write");
            $finish;
        end  
        
        $display("R0 read/write passed!");
        $display("All tests passed!");
        $finish;                  
   end

endmodule
module regset_tb();



    reg CLK;
    reg RES;
    reg write_enable;
    reg [31 : 0] D;
    reg [4 : 0] A_D;
    reg [4 : 0] A_Q0;
    reg [4 : 0] A_Q1;
    

    wire [31 : 0] Q0;
    wire [31 : 0] Q1;
    
    integer i;
    

    regset dut(.CLK(CLK),
               .RES(RES),
               .write_enable(write_enable),
               .D(D),
               .A_D(A_D),
               .A_Q0(A_Q0),
               .A_Q1(A_Q1),
               .Q0(Q0),
               .Q1(Q1));
    

    initial begin 
        CLK = 1'b0;
    end
    

    always begin
        #5 CLK = ~CLK;
    end    
    

   initial begin
        
        RES = 1;
        @(negedge CLK);
        RES = 0;
        

        for(i = 0; i < 32; i = i + 1)
        begin
        
            A_Q0 = i; A_Q1 = i;
            @(negedge CLK);
            
            if(Q0 != 32'd0 || Q1 != 32'd0)
            begin
                $display("Fault in Reset");
                $finish;
            end    
            
        end
        
        $display("Reset test passed!");
        

        $srandom(42);
        
        for(i = 1; i < 32; i = i + 1)
        begin
            D = $urandom;
            A_D = i;
            write_enable = 1'b1; 
            A_Q0 = i; A_Q1 = i;
            @(negedge CLK);
            write_enable = 1'b0;
            if(Q0 != D && Q0 != D) begin
                $display("Fault in General Purpose read/write");
                $finish;
            end            
        end
        
        $display("General Purpose read/write passed!");
        

        D = $urandom;
        A_D = 5'd0;
        write_enable = 1'b1; 
        A_Q0 = 5'd0; A_Q1 = 5'd0;
        @(negedge CLK);
        write_enable = 1'b0;
        if(Q0 != 32'd0 && Q0 != 32'd0) begin
            $display("Fault in R0 read/write");
            $finish;
        end  
        
        $display("R0 read/write passed!");
        $display("All tests passed!");
        $finish;                  
   end

endmodule