data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:21: Cannot find include file: eth_tasks_f36.v\n`include "eth_tasks_f36.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_tasks_f36.v\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_tasks_f36.v.v\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_tasks_f36.v.sv\n             eth_tasks_f36.v\n             eth_tasks_f36.v.v\n             eth_tasks_f36.v.sv\n             obj_dir/eth_tasks_f36.v\n             obj_dir/eth_tasks_f36.v.v\n             obj_dir/eth_tasks_f36.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   always #50 eth_clk = ~eth_clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n   always #173 wb_clk = ~wb_clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   always #77 sys_clk = ~ sys_clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:84: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("simple_gemac_wrapper_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:85: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,simple_gemac_wrapper_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:97: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:99: syntax error, unexpected \'@\'\n   @(posedge wb_clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:106: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:108: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #30000;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:110: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:113: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:115: syntax error, unexpected \'@\'\n @(posedge eth_clk); \n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:118: syntax error, unexpected \'@\'\n   @(posedge sys_clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:121: syntax error, unexpected \'@\'\n   @(posedge sys_clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:125: syntax error, unexpected \'@\'\n   @(posedge sys_clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #90000;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:164: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:166: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #116000;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:174: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:176: syntax error, unexpected \'@\'\n @(posedge eth_clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v:204: syntax error, unexpected \'@\'\n    @(posedge wb_clk);\n    ^\n%Error: Exiting due to 18 error(s), 9 warning(s)\n'
module simple_gemac_wrapper_tb;
`include "eth_tasks_f36.v"
     
   reg reset   = 1;
   initial #1000 reset = 0;
   wire wb_rst 	= reset;

   reg eth_clk     = 0;
   always #50 eth_clk = ~eth_clk;

   reg wb_clk 	= 0;
   always #173 wb_clk = ~wb_clk;

   reg sys_clk 	= 0;
   always #77 sys_clk = ~ sys_clk;
   
   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
   wire [7:0] GMII_RXD, GMII_TXD;

   wire rx_valid, rx_error, rx_ack;
   wire tx_ack, tx_valid, tx_error;
   
   wire [7:0] rx_data, tx_data;
   
   wire GMII_RX_CLK   = GMII_GTX_CLK;

   reg [7:0] FORCE_DAT_ERR = 0;
   reg FORCE_ERR = 0;
   

   assign GMII_RX_DV  = GMII_TX_EN;
   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;


   wire [31:0] wb_dat_o;
   reg [31:0]  wb_dat_i;
   reg [7:0]   wb_adr;
   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
   wire        wb_ack;

   reg [35:0]  tx_f36_data=0;
   reg 	       tx_f36_src_rdy = 0;
   wire        tx_f36_dst_rdy;
   wire [35:0] rx_f36_data;
   wire        rx_f36_src_rdy;
   wire        rx_f36_dst_rdy = 1;
   
   simple_gemac_wrapper simple_gemac_wrapper
     (.clk125(eth_clk),  .reset(reset),
      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),

      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),

      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),

      .mdio(), .mdc(),
      .debug() );
   
   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
   initial $dumpvars(0,simple_gemac_wrapper_tb);

   integer i; 
   reg [7:0] pkt_rom[0:65535];
   reg [1023:0] ROMFile;
   
   initial
     for (i=0;i<65536;i=i+1)
       pkt_rom[i] <= 8'h0;

   initial
     begin
	@(negedge reset);
	repeat (10)
	  @(posedge wb_clk);
	WishboneWR(0,6'b111101); 
	WishboneWR(4,16'hA0B0);
	WishboneWR(8,32'hC0D0_A1B1);
	WishboneWR(12,16'h0000);
	WishboneWR(16,32'h0000_0000);
	
	@(posedge eth_clk);
	SendFlowCtrl(16'h0007);
	@(posedge eth_clk);
	#30000;
	@(posedge eth_clk);
	SendFlowCtrl(16'h0009);
	#10000;
	@(posedge eth_clk);
	SendFlowCtrl(16'h0000);
	@(posedge eth_clk); 

	repeat (1000)
	  @(posedge sys_clk);
	SendPacket_to_fifo36(32'hA0B0C0D0,10);
	repeat (1000)
	  @(posedge sys_clk);

	SendPacket_to_fifo36(32'hAABBCCDD,100);
	repeat (10)
	  @(posedge sys_clk);

	#100000 $finish;
     end


    initial
     begin
	#90000;
	@(posedge eth_clk);
	FORCE_DAT_ERR <= 8'h10;
	@(posedge eth_clk);
	FORCE_DAT_ERR <= 8'h00;
     end


   initial
     begin
	#116000;
	@(posedge eth_clk);
	FORCE_ERR <= 1;
	@(posedge eth_clk);
	FORCE_ERR <= 0;
     end




   task WishboneWR;
      input [7:0] adr;
      input [31:0] value;
      begin
	 wb_adr   <= adr;
	 wb_dat_i <= value;
	 wb_stb   <= 1;
	 wb_cyc   <= 1;
	 wb_we 	  <= 1;
	 while (~wb_ack)
	   @(posedge wb_clk);
	 @(posedge wb_clk);
	 wb_stb <= 0;
	 wb_cyc <= 0;
	 wb_we 	<= 0;
      end
   endtask

endmodule
module simple_gemac_wrapper_tb;

`include "eth_tasks_f36.v"
     
   reg reset   = 1;
   initial #1000 reset = 0;
   wire wb_rst 	= reset;

   reg eth_clk     = 0;
   always #50 eth_clk = ~eth_clk;

   reg wb_clk 	= 0;
   always #173 wb_clk = ~wb_clk;

   reg sys_clk 	= 0;
   always #77 sys_clk = ~ sys_clk;
   
   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
   wire [7:0] GMII_RXD, GMII_TXD;

   wire rx_valid, rx_error, rx_ack;
   wire tx_ack, tx_valid, tx_error;
   
   wire [7:0] rx_data, tx_data;
   
   wire GMII_RX_CLK   = GMII_GTX_CLK;

   reg [7:0] FORCE_DAT_ERR = 0;
   reg FORCE_ERR = 0;
   

   assign GMII_RX_DV  = GMII_TX_EN;
   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;


   wire [31:0] wb_dat_o;
   reg [31:0]  wb_dat_i;
   reg [7:0]   wb_adr;
   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
   wire        wb_ack;

   reg [35:0]  tx_f36_data=0;
   reg 	       tx_f36_src_rdy = 0;
   wire        tx_f36_dst_rdy;
   wire [35:0] rx_f36_data;
   wire        rx_f36_src_rdy;
   wire        rx_f36_dst_rdy = 1;
   
   simple_gemac_wrapper simple_gemac_wrapper
     (.clk125(eth_clk),  .reset(reset),
      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),

      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),

      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),

      .mdio(), .mdc(),
      .debug() );
   
   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
   initial $dumpvars(0,simple_gemac_wrapper_tb);

   integer i; 
   reg [7:0] pkt_rom[0:65535];
   reg [1023:0] ROMFile;
   
   initial
     for (i=0;i<65536;i=i+1)
       pkt_rom[i] <= 8'h0;

   initial
     begin
	@(negedge reset);
	repeat (10)
	  @(posedge wb_clk);
	WishboneWR(0,6'b111101); 
	WishboneWR(4,16'hA0B0);
	WishboneWR(8,32'hC0D0_A1B1);
	WishboneWR(12,16'h0000);
	WishboneWR(16,32'h0000_0000);
	
	@(posedge eth_clk);
	SendFlowCtrl(16'h0007);
	@(posedge eth_clk);
	#30000;
	@(posedge eth_clk);
	SendFlowCtrl(16'h0009);
	#10000;
	@(posedge eth_clk);
	SendFlowCtrl(16'h0000);
	@(posedge eth_clk); 

	repeat (1000)
	  @(posedge sys_clk);
	SendPacket_to_fifo36(32'hA0B0C0D0,10);
	repeat (1000)
	  @(posedge sys_clk);

	SendPacket_to_fifo36(32'hAABBCCDD,100);
	repeat (10)
	  @(posedge sys_clk);

	#100000 $finish;
     end


    initial
     begin
	#90000;
	@(posedge eth_clk);
	FORCE_DAT_ERR <= 8'h10;
	@(posedge eth_clk);
	FORCE_DAT_ERR <= 8'h00;
     end


   initial
     begin
	#116000;
	@(posedge eth_clk);
	FORCE_ERR <= 1;
	@(posedge eth_clk);
	FORCE_ERR <= 0;
     end




   task WishboneWR;
      input [7:0] adr;
      input [31:0] value;
      begin
	 wb_adr   <= adr;
	 wb_dat_i <= value;
	 wb_stb   <= 1;
	 wb_cyc   <= 1;
	 wb_we 	  <= 1;
	 while (~wb_ack)
	   @(posedge wb_clk);
	 @(posedge wb_clk);
	 wb_stb <= 0;
	 wb_cyc <= 0;
	 wb_we 	<= 0;
      end
   endtask

endmodule