data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4.v
data/verilator_xmls/b54bb60a-5e71-49b8-836c-e3f07c4bde0e.xml
module fn_sw_4(a,
               b,
               sel,
               y);
    
    input a;
    input b;
    input[1:0] sel;
    output y;
    
    reg y;
    always @(a or b or sel) begin
        case(sel)
            2'b00:begin y<=a&b; end
            2'b01:begin y<=a|b; end
            2'b10:begin y<=a^b; end
            2'b11:begin y<=~(a^b); end
        endcase
    end
endmodule
module fn_sw_4(a,
               b,
               sel,
               y);

    
    input a;
    input b;
    input[1:0] sel;
    output y;
    
    reg y;
    always @(a or b or sel) begin
        case(sel)
            2'b00:begin y<=a&b; end
            2'b01:begin y<=a|b; end
            2'b10:begin y<=a^b; end
            2'b11:begin y<=~(a^b); end
        endcase
    end
endmodule