data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tri_gen_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #17 rstn<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #20000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L7/tir_gen/tri_gen_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tri_gen_tb ();

reg clk, rstn;
wire [8:0] d_out;

tri_gen U1(
    .clk(clk),
    .rstn(rstn),
    .d_out(d_out)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tri_gen_tb);
    end


initial begin
    clk <= 0;
    rstn <= 0;
    #17 rstn<=1;
    #20000 $finish;
end

always #5 clk <= ~clk;
endmodule
module tri_gen_tb ();


reg clk, rstn;
wire [8:0] d_out;

tri_gen U1(
    .clk(clk),
    .rstn(rstn),
    .d_out(d_out)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tri_gen_tb);
    end


initial begin
    clk <= 0;
    rstn <= 0;
    #17 rstn<=1;
    #20000 $finish;
end

always #5 clk <= ~clk;
endmodule