data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_cmos_pad.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_cmos_pad.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module bw_io_cmos_pad(oe ,bsr_si ,rst_io_l ,se ,rst_val_up ,data ,
     mode_ctl ,clock_dr ,update_dr ,rst_val_dn ,hiz_l ,
     shift_dr ,bso ,to_core ,pad ,por_l, vddo );
output		bso ;
output		to_core ;
input		oe ;
input		bsr_si ;
input		rst_io_l ;
input		se ;
input		rst_val_up ;
input		data ;
input		mode_ctl ;
input		clock_dr ;
input		update_dr ;
input		rst_val_dn ;
input		hiz_l ;
input		shift_dr ;
input		por_l ;
inout		pad ;
input  		vddo ;
supply1		vdd ;
supply0		vss ;
 
wire		q_up_pad ;
wire		net84 ;
wire		rcvr_data ;
wire		bsr_dn_l ;
wire		q_dn_pad_l ;
wire		por ;
wire		bsr_data_to_core ;
wire		sel_data_n ;
wire		pad_up ;
wire		bsr_up ;
wire		pad_dn_l ;
 
 
bw_io_cmos_edgelogic I2 (
     .rcvr_data       (rcvr_data ),
     .to_core         (to_core ),
     .se              (se ),
     .bsr_up          (q_up_pad ),
     .bsr_dn_l        (q_dn_pad_l ),
     .pad_dn_l        (pad_dn_l ),
     .pad_up          (pad_up ),
     .oe              (oe ),
     .data            (data ),
     .por_l           (por_l ),
     .por             (por ),
     .bsr_data_to_core (bsr_data_to_core ),
     .bsr_mode        (mode_ctl ) );
bw_io_hstl_drv I3 (
     .cbu             ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
     .cbd             ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
     .por             (por ),
     .bsr_dn_l        (bsr_dn_l ),
     .bsr_up          (bsr_up ),
     .pad_dn_l        (pad_dn_l ),
     .sel_data_n      (sel_data_n ),
     .pad_up          (pad_up ),
     .pad             (pad ),
     .vddo            (vddo) );
bw_io_dtl_bscan bscan (
     .bsr_data_to_core (bsr_data_to_core ),
     .hiz_l           (hiz_l ),
     .rst_io_l        (rst_io_l ),
     .rst_val_dn      (rst_val_dn ),
     .rst_val_up      (rst_val_up ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .update_dr       (update_dr ),
     .up_open         (vdd ),
     .bsr_so          (bso ),
     .se              (se ),
     .mode_ctl        (mode_ctl ),
     .bsr_si          (bsr_si ),
     .q_up_mux        (bsr_up ),
     .down_25         (vss ),
     .sel_data_n      (sel_data_n ),
     .rcvr_data_to_bsr (rcvr_data ),
     .q25_dn_pad_l    (vdd ),
     .q_dn_pad_l      (q_dn_pad_l ),
     .q_dn_mux_l      (bsr_dn_l ),
     .q25_dn_mux_l    (net84 ),
     .q_up_pad        (q_up_pad ),
     .serial_out      (),
     .bypass_enable   (vss),	       
     .clk             (vss),
     .bypass_in       (vss),
     .serial_in       (vss),
     .ps_select       (vss),	      
     .out_type        (vss) );
bw_io_schmitt I41 (
     .vddo            (vddo ),
     .out             (rcvr_data ),
     .in              (pad ) );
endmodule
module bw_io_cmos_pad(oe ,bsr_si ,rst_io_l ,se ,rst_val_up ,data ,
     mode_ctl ,clock_dr ,update_dr ,rst_val_dn ,hiz_l ,
     shift_dr ,bso ,to_core ,pad ,por_l, vddo );

output		bso ;
output		to_core ;
input		oe ;
input		bsr_si ;
input		rst_io_l ;
input		se ;
input		rst_val_up ;
input		data ;
input		mode_ctl ;
input		clock_dr ;
input		update_dr ;
input		rst_val_dn ;
input		hiz_l ;
input		shift_dr ;
input		por_l ;
inout		pad ;
input  		vddo ;
supply1		vdd ;
supply0		vss ;
 
wire		q_up_pad ;
wire		net84 ;
wire		rcvr_data ;
wire		bsr_dn_l ;
wire		q_dn_pad_l ;
wire		por ;
wire		bsr_data_to_core ;
wire		sel_data_n ;
wire		pad_up ;
wire		bsr_up ;
wire		pad_dn_l ;
 
 
bw_io_cmos_edgelogic I2 (
     .rcvr_data       (rcvr_data ),
     .to_core         (to_core ),
     .se              (se ),
     .bsr_up          (q_up_pad ),
     .bsr_dn_l        (q_dn_pad_l ),
     .pad_dn_l        (pad_dn_l ),
     .pad_up          (pad_up ),
     .oe              (oe ),
     .data            (data ),
     .por_l           (por_l ),
     .por             (por ),
     .bsr_data_to_core (bsr_data_to_core ),
     .bsr_mode        (mode_ctl ) );
bw_io_hstl_drv I3 (
     .cbu             ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
     .cbd             ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
     .por             (por ),
     .bsr_dn_l        (bsr_dn_l ),
     .bsr_up          (bsr_up ),
     .pad_dn_l        (pad_dn_l ),
     .sel_data_n      (sel_data_n ),
     .pad_up          (pad_up ),
     .pad             (pad ),
     .vddo            (vddo) );
bw_io_dtl_bscan bscan (
     .bsr_data_to_core (bsr_data_to_core ),
     .hiz_l           (hiz_l ),
     .rst_io_l        (rst_io_l ),
     .rst_val_dn      (rst_val_dn ),
     .rst_val_up      (rst_val_up ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .update_dr       (update_dr ),
     .up_open         (vdd ),
     .bsr_so          (bso ),
     .se              (se ),
     .mode_ctl        (mode_ctl ),
     .bsr_si          (bsr_si ),
     .q_up_mux        (bsr_up ),
     .down_25         (vss ),
     .sel_data_n      (sel_data_n ),
     .rcvr_data_to_bsr (rcvr_data ),
     .q25_dn_pad_l    (vdd ),
     .q_dn_pad_l      (q_dn_pad_l ),
     .q_dn_mux_l      (bsr_dn_l ),
     .q25_dn_mux_l    (net84 ),
     .q_up_pad        (q_up_pad ),
     .serial_out      (),
     .bypass_enable   (vss),	       
     .clk             (vss),
     .bypass_in       (vss),
     .serial_in       (vss),
     .ps_select       (vss),	      
     .out_type        (vss) );
bw_io_schmitt I41 (
     .vddo            (vddo ),
     .out             (rcvr_data ),
     .in              (pad ) );
endmodule