data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module IFID(clk, do, op, rd, rs, rt, func, imm);
    input clk;
    input [31:0] do;
    output reg [5:0] op,func;
    output reg [5:0] rd,rs,rt;
    output reg [15:0] imm;
    reg [31:0] IF;
    always @ (posedge clk) begin
        IF <= do;
    end
    
    always @(negedge clk)
        begin
            op <= IF[31:26];
            rs <= IF[25:21];
            rt <= IF[20:16];
            rd <= IF[15:11];
            func <= IF[5:0];
            imm <= IF[15:0];
        end
endmodule
module IFID(clk, do, op, rd, rs, rt, func, imm);

    input clk;
    input [31:0] do;
    output reg [5:0] op,func;
    output reg [5:0] rd,rs,rt;
    output reg [15:0] imm;
    reg [31:0] IF;
    always @ (posedge clk) begin
        IF <= do;
    end
    
    always @(negedge clk)
        begin
            op <= IF[31:26];
            rs <= IF[25:21];
            rt <= IF[20:16];
            rd <= IF[15:11];
            func <= IF[5:0];
            imm <= IF[15:0];
        end
endmodule