data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_tidbits_fsm_using_function.v
data/verilator_xmls/aa1f808f-13e8-49dd-8acc-79ebf84b7c98.xml
function (
clock      ,
reset      ,
req_0      ,
req_1      ,
gnt_0      ,
gnt_1      
);

input   clock,reset,req_0,req_1;

output  gnt_0,gnt_1;

wire    clock,reset,req_0,req_1;

reg     gnt_0,gnt_1;

parameter SIZE = 3           ;
parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;

reg   [SIZE-1:0]          state        ;
wire  [SIZE-1:0]          next_state   ;

assign next_state = fsm_function(state, req_0, req_1);

function [SIZE-1:0] fsm_function;
  input  [SIZE-1:0]  state ;	
  input    req_0 ;
  input    req_1 ;
  case(state)
   IDLE : if (req_0 == 1'b1) begin
                fsm_function = GNT0;
              end else if (req_1 == 1'b1) begin
                fsm_function= GNT1;
              end else begin
                fsm_function = IDLE;
              end
   GNT0 : if (req_0 == 1'b1) begin
                fsm_function = GNT0;
              end else begin
                fsm_function = IDLE;
              end
   GNT1 : if (req_1 == 1'b1) begin
                fsm_function = GNT1;
          end else begin
                fsm_function = IDLE;
              end
   default : fsm_function = IDLE;
  endcase
endfunction
function (
clock      ,
reset      ,
req_0      ,
req_1      ,
gnt_0      ,
gnt_1      
);


input   clock,reset,req_0,req_1;

output  gnt_0,gnt_1;

wire    clock,reset,req_0,req_1;

reg     gnt_0,gnt_1;

parameter SIZE = 3           ;
parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;

reg   [SIZE-1:0]          state        ;
wire  [SIZE-1:0]          next_state   ;

assign next_state = fsm_function(state, req_0, req_1);

function [SIZE-1:0] fsm_function;
  input  [SIZE-1:0]  state ;	
  input    req_0 ;
  input    req_1 ;
  case(state)
   IDLE : if (req_0 == 1'b1) begin
                fsm_function = GNT0;
              end else if (req_1 == 1'b1) begin
                fsm_function= GNT1;
              end else begin
                fsm_function = IDLE;
              end
   GNT0 : if (req_0 == 1'b1) begin
                fsm_function = GNT0;
              end else begin
                fsm_function = IDLE;
              end
   GNT1 : if (req_1 == 1'b1) begin
                fsm_function = GNT1;
          end else begin
                fsm_function = IDLE;
              end
   default : fsm_function = IDLE;
  endcase
endfunction