data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%t: %b - %b", $time, a, o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%t: %b - %b", $time, a, o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%t: %b - %b", $time, a, o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%t: %b - %b", $time, a, o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%t: %b - %b", $time, a, o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench/tb_not_gate.v:8: Cannot find file containing module: \'not_gate\'\n    not_gate dut (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench,data/full_repos/permissive/417765606/not_gate\n             data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench,data/full_repos/permissive/417765606/not_gate.v\n             data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/testbench,data/full_repos/permissive/417765606/not_gate.sv\n             not_gate\n             not_gate.v\n             not_gate.sv\n             obj_dir/not_gate\n             obj_dir/not_gate.v\n             obj_dir/not_gate.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_not_gate ();

    reg a;
    wire o;

    not_gate dut (
        .a(a),
        .o(o)
    );


    initial
    begin
        a = 0;
        #10 a = 1;
        #10 a = 0;
        #10 a = 1;
        #10 a = 0;
        #10 a = 1;
        #10 a = 0;
    end

    initial
    begin
        $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #1000;
        $finish;
    end

`ifdef VCD
    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0);
    end
`endif

endmodule
module tb_not_gate ();


    reg a;
    wire o;

    not_gate dut (
        .a(a),
        .o(o)
    );


    initial
    begin
        a = 0;
        #10 a = 1;
        #10 a = 0;
        #10 a = 1;
        #10 a = 0;
        #10 a = 1;
        #10 a = 0;
    end

    initial
    begin
        $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #10 $display("%t: %b - %b", $time, a, o);
        #1000;
        $finish;
    end

`ifdef VCD
    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0);
    end
`endif

endmodule