data/full_repos/permissive/475928601/Assignments/moore_d.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/475928601/Assignments/moore_d.v:26: Cell has missing pin: \'Qb\'\n    DFF DFF0(x, clk, q0, q0b);\n        ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/475928601/Assignments/moore_d.v:32: Cell has missing pin: \'Qb\'\n    DFF DFF1(d1, clk, q1, q1b);\n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/475928601/Assignments/moore_d.v:30: Signal definition not found, creating implicitly: \'q1\'\n                                                                                : ... Suggested alternative: \'d1\'\n    and(xq1q0b, x, q1, q0b);\n                   ^~\n%Warning-IMPLICIT: data/full_repos/permissive/475928601/Assignments/moore_d.v:32: Signal definition not found, creating implicitly: \'q1b\'\n                                                                                : ... Suggested alternative: \'q0b\'\n    DFF DFF1(d1, clk, q1, q1b);\n                          ^~~\n%Error: Exiting due to 4 warning(s)\n'
module DFF(
  input D,
  input clk,
  input reset,
  output reg Q,
  output Qb
);
  initial Q = 0;
  assign Qb = ~Q;
  
  always @(posedge clk or posedge reset)
    Q <= reset ? 0 : D;
endmodule
module DFF(
  input D,
  input clk,
  input reset,
  output reg Q,
  output Qb
);

  initial Q = 0;
  assign Qb = ~Q;
  
  always @(posedge clk or posedge reset)
    Q <= reset ? 0 : D;
endmodule