data/full_repos/permissive/482720319/alu.v
1: b'%Error: data/full_repos/permissive/482720319/alu.v:45: Unsupported or unknown PLI call: $monitor\n            $monitor("opcode : %b, A = %b(%d)B = %b(%d) :::: res = %b(%d) --- %b", opt, At, At, Bt, Bt, res, res, zero);\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482720319/alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #10 $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482720319/alu.v:55: Unsupported: Ignoring delay on this delayed statement.\n            repeat(7) #1 opt = opt + 1;\n                      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

      reg [15:0] At, Bt;
      reg [2:0] opt;

      wire [15:0] res;
      wire zero;

      ALU dut (
            .opcode(opt),
            .A(At),
            .B(Bt),
            .res(res),
            .zero(zero)
      );

      initial
            $monitor("opcode : %b, A = %b(%d)B = %b(%d) :::: res = %b(%d) --- %b", opt, At, At, Bt, Bt, res, res, zero);

      initial begin
            At <= 16'b1110110010101101;
            Bt <= 16'd3;
            #10 $finish;
      end

      initial begin
            opt = 3'd0;
            repeat(7) #1 opt = opt + 1;
      end
endmodule
module tb();


      reg [15:0] At, Bt;
      reg [2:0] opt;

      wire [15:0] res;
      wire zero;

      ALU dut (
            .opcode(opt),
            .A(At),
            .B(Bt),
            .res(res),
            .zero(zero)
      );

      initial
            $monitor("opcode : %b, A = %b(%d)B = %b(%d) :::: res = %b(%d) --- %b", opt, At, At, Bt, Bt, res, res, zero);

      initial begin
            At <= 16'b1110110010101101;
            Bt <= 16'd3;
            #10 $finish;
      end

      initial begin
            opt = 3'd0;
            repeat(7) #1 opt = opt + 1;
      end
endmodule