data/full_repos/permissive/493441306/Verilog Language/more_verilog_features/04_popcount255.v
1: b'%Error: Cannot find file containing module: Language/more_verilog_features,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             Language/more_verilog_features,data/full_repos/permissive/493441306\n             Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/more_verilog_features/04_popcount255.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [254:0] in,
    output [7:0] out );
    
    always@(*) begin
        out = 8'b0;
        for (int i=0; i<$bits(in); i++) begin  
            if(in[i])
                out = out + 8'b1;
        end
    end

endmodule
module top_module( 
    input [254:0] in,
    output [7:0] out );

    
    always@(*) begin
        out = 8'b0;
        for (int i=0; i<$bits(in); i++) begin  
            if(in[i])
                out = out + 8'b1;
        end
    end

endmodule