data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:26: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:41: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("RegisterTestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:42: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,RegisterTestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench.v:44: Unsupported or unknown PLI call: $monitor\n $monitor("T = %d,test_out = %d,test_in = %d,test_clk = %d,test_reset = %d,test_load = %d",$time,test_out,test_in,test_clk,test_reset,test_load );   \n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterTestBench;

parameter sim_time = 750*2;
reg [31:0] test_in;
reg test_clk,test_reset,test_load;
wire  [31:0] test_out;
Register test_reg(.IN(test_in),
				  .Clk(test_clk),
				  .Reset(test_reset),
				  .Load(test_load),
				  .OUT(test_out));

reg Clk,Reset;

initial fork
	test_in=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ;
	#1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;
	#2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;
	#3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench.vcd");
	$dumpvars(0,RegisterTestBench);
	$display(" Test Results" );
	$monitor("T = %d,test_out = %d,test_in = %d,test_clk = %d,test_reset = %d,test_load = %d",$time,test_out,test_in,test_clk,test_reset,test_load );
end

endmodule
module RegisterTestBench;


parameter sim_time = 750*2;
reg [31:0] test_in;
reg test_clk,test_reset,test_load;
wire  [31:0] test_out;
Register test_reg(.IN(test_in),
				  .Clk(test_clk),
				  .Reset(test_reset),
				  .Load(test_load),
				  .OUT(test_out));

reg Clk,Reset;

initial fork
	test_in=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ;
	#1 test_in=1;  #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;
	#2 test_in=1;  #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;
	#3 test_in=0;  #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench.vcd");
	$dumpvars(0,RegisterTestBench);
	$display(" Test Results" );
	$monitor("T = %d,test_out = %d,test_in = %d,test_clk = %d,test_reset = %d,test_load = %d",$time,test_out,test_in,test_clk,test_reset,test_load );
end

endmodule