data/full_repos/permissive/518307247/iiitb_jc_tb.v
1: b'%Error: data/full_repos/permissive/518307247/iiitb_jc_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("iiitb_jc.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/518307247/iiitb_jc_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(1);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518307247/iiitb_jc_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#6 rst =1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518307247/iiitb_jc_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/518307247/iiitb_jc_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\ninitial #68 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_jc_tb;
reg clk;
reg rst;
wire [7:0]q;
iiitb_jc j1(rst,clk,q);

initial
begin
clk=0;
rst = 0;


$dumpfile("iiitb_jc.vcd");
$dumpvars(1);
#6 rst =1;
end

always #2 clk = ~clk;

initial #68 $finish;

endmodule
module iiitb_jc_tb;

reg clk;
reg rst;
wire [7:0]q;
iiitb_jc j1(rst,clk,q);

initial
begin
clk=0;
rst = 0;


$dumpfile("iiitb_jc.vcd");
$dumpvars(1);
#6 rst =1;
end

always #2 clk = ~clk;

initial #68 $finish;

endmodule