data/full_repos/permissive/482470328/lab3/labFiles/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/482470328/lab3/labFiles/tb.v:30: Cannot find file containing module: \'regfile\'\n    regfile rf_module(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470328/lab3/labFiles,data/full_repos/permissive/482470328/regfile\n             data/full_repos/permissive/482470328/lab3/labFiles,data/full_repos/permissive/482470328/regfile.v\n             data/full_repos/permissive/482470328/lab3/labFiles,data/full_repos/permissive/482470328/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

    
    wire wen = 1;
    reg clk;
    reg  [4 :0] raddr1;
    reg  [4 :0] raddr2;
    reg  [4 :0] waddr;
    reg  [31:0] wdata;
    wire  [31:0] rdata1;
    wire  [31:0] rdata2;
    wire  [31:0] test_data;  
    reg  [4 :0] test_addr;
    regfile rf_module(
        .clk   (clk   ),
        .wen   (wen   ),
        .raddr1(raddr1),
        .raddr2(raddr2),
        .waddr (waddr ),
        .wdata (wdata ),
        .rdata1(rdata1),
        .rdata2(rdata2),
        .test_addr(test_addr),
        .test_data(test_data)
    );

    initial begin

        clk = 0;
        raddr1 = 5'd1;
        raddr2 = 5'd2;
        test_addr = 5'd3;

        #10;
        clk = 1;
        waddr = 5'd1;
        wdata = 32'HFFFFFFFF;
        
        #10;
        clk = 0;

        #10;
        clk = 1;
        waddr = 5'd2;
        wdata = 32'H0000FFFF;
        
        #10;
        clk = 0;

        #10;
        clk = 1;
        waddr = 5'd3;
        wdata = 32'HFFFF0000;
    end
endmodule
module tb;


    
    wire wen = 1;
    reg clk;
    reg  [4 :0] raddr1;
    reg  [4 :0] raddr2;
    reg  [4 :0] waddr;
    reg  [31:0] wdata;
    wire  [31:0] rdata1;
    wire  [31:0] rdata2;
    wire  [31:0] test_data;  
    reg  [4 :0] test_addr;
    regfile rf_module(
        .clk   (clk   ),
        .wen   (wen   ),
        .raddr1(raddr1),
        .raddr2(raddr2),
        .waddr (waddr ),
        .wdata (wdata ),
        .rdata1(rdata1),
        .rdata2(rdata2),
        .test_addr(test_addr),
        .test_data(test_data)
    );

    initial begin

        clk = 0;
        raddr1 = 5'd1;
        raddr2 = 5'd2;
        test_addr = 5'd3;

        #10;
        clk = 1;
        waddr = 5'd1;
        wdata = 32'HFFFFFFFF;
        
        #10;
        clk = 0;

        #10;
        clk = 1;
        waddr = 5'd2;
        wdata = 32'H0000FFFF;
        
        #10;
        clk = 0;

        #10;
        clk = 1;
        waddr = 5'd3;
        wdata = 32'HFFFF0000;
    end
endmodule