data/full_repos/permissive/475642691/sources/new/OL.v
data/verilator_xmls/d99b1860-6ffc-4a3d-8a35-58141e84b346.xml
module OL(

     input FS,[3:0]CS,
     output FD   
    );
    assign FD = (~FS & CS[3]) | (CS[3] & CS[2] & CS[1] & CS[0]);
endmodule
module OL(

     input FS,[3:0]CS,
     output FD   
    );

    assign FD = (~FS & CS[3]) | (CS[3] & CS[2] & CS[1] & CS[0]);
endmodule