data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_synch_jl_dl (

syncdata, 

cmp_clk, jbus_rx_sync, coin_edge, arst_l, presyncdata
);


parameter SIZE = 1;
input  cmp_clk;
input  jbus_rx_sync;
input  coin_edge;
input  arst_l;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire   [SIZE-1:0]  presyncdata_in; 
wire   [SIZE-1:0]  presyncdata_in_nxt;
wire   [SIZE-1:0]  syncdata_nxt;

assign presyncdata_in_nxt = jbus_rx_sync ? presyncdata: presyncdata_in; 
   
   dffrl_async_ns  #(SIZE)  u_synch_cl_dl_ff0(
                   .din (presyncdata_in_nxt[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (presyncdata_in[SIZE-1:0]));

assign syncdata_nxt = coin_edge ? presyncdata_in : syncdata;

   dffrl_async_ns  #(SIZE)  u_synch_cl_dl_ff2(
                   .din (syncdata_nxt[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (syncdata[SIZE-1:0]));

endmodule
module ctu_synch_jl_dl (

syncdata, 

cmp_clk, jbus_rx_sync, coin_edge, arst_l, presyncdata
);



parameter SIZE = 1;
input  cmp_clk;
input  jbus_rx_sync;
input  coin_edge;
input  arst_l;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire   [SIZE-1:0]  presyncdata_in; 
wire   [SIZE-1:0]  presyncdata_in_nxt;
wire   [SIZE-1:0]  syncdata_nxt;

assign presyncdata_in_nxt = jbus_rx_sync ? presyncdata: presyncdata_in; 
   
   dffrl_async_ns  #(SIZE)  u_synch_cl_dl_ff0(
                   .din (presyncdata_in_nxt[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (presyncdata_in[SIZE-1:0]));

assign syncdata_nxt = coin_edge ? presyncdata_in : syncdata;

   dffrl_async_ns  #(SIZE)  u_synch_cl_dl_ff2(
                   .din (syncdata_nxt[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (syncdata[SIZE-1:0]));

endmodule