data/full_repos/permissive/521925561/router_top.v
1: b"%Error: data/full_repos/permissive/521925561/router_top.v:11: Cannot find file containing module: 'router_fifo'\nrouter_fifo FIFO_0(.clock  (clock),\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521925561,data/full_repos/permissive/521925561/router_fifo\n             data/full_repos/permissive/521925561,data/full_repos/permissive/521925561/router_fifo.v\n             data/full_repos/permissive/521925561,data/full_repos/permissive/521925561/router_fifo.sv\n             router_fifo\n             router_fifo.v\n             router_fifo.sv\n             obj_dir/router_fifo\n             obj_dir/router_fifo.v\n             obj_dir/router_fifo.sv\n%Error: data/full_repos/permissive/521925561/router_top.v:22: Cannot find file containing module: 'router_fifo'\nrouter_fifo FIFO_1(.clock  (clock),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/521925561/router_top.v:33: Cannot find file containing module: 'router_fifo'\nrouter_fifo FIFO_2(.clock  (clock),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/521925561/router_top.v:46: Cannot find file containing module: 'router_fsm'\nrouter_fsm FSM(.clock   (clock),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/521925561/router_top.v:70: Cannot find file containing module: 'router_sync'\nrouter_sync SYNC(.detect_add (detect_add),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/521925561/router_top.v:95: Cannot find file containing module: 'router_register'\nrouter_register REG(.clock        (clock),\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module router_top(input clock,resetn,read_enb_0,read_enb_1,read_enb_2,pkt_valid,input [7:0]data_in,
                  output [7:0]data_out_0,data_out_1,data_out_2,output vld_out_0,vld_out_1,vld_out_2,error,busy);
				  


wire [2:0] write_enb;
wire [7:0] dout;



router_fifo FIFO_0(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_0),
				   .write_enb	(write_enb[0]),
				   .read_enb	(read_enb_0),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_0),
				   .empty		(empty_0),
				   .full		(full_0));

router_fifo FIFO_1(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_1),
				   .write_enb	(write_enb[1]),
				   .read_enb	(read_enb_1),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_1),
				   .empty		(empty_1),
				   .full		(full_1));
				   
router_fifo FIFO_2(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_2),
				   .write_enb	(write_enb[2]),
				   .read_enb	(read_enb_2),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_2),
				   .empty		(empty_2),
				   .full		(full_2));
				   


router_fsm FSM(.clock			(clock),
			   .resetn			(resetn),
			   .pkt_valid		(pkt_valid),
			   .low_pkt_valid	(low_pkt_valid),
			   .parity_done 	(parity_done),
			   .soft_reset_0	(soft_reset_0),
			   .soft_reset_1	(soft_reset_1),
			   .soft_reset_2	(soft_reset_2),
			   .fifo_full		(fifo_full),
			   .fifo_empty_0	(empty_0),
			   .fifo_empty_1	(empty_1),
			   .fifo_empty_2	(empty_2),
			   .data_in			(data_in[1:0]),
			   .detect_add		(detect_add),
			   .ld_state		(ld_state),
			   .laf_state		(laf_state),
			   .full_state		(full_state),
			   .write_enb_reg	(write_enb_reg),
			   .rst_int_reg		(rst_int_reg),	   
			   .lfd_state		(lfd_state),
	           .busy			(busy));
			   


router_sync SYNC(.detect_add	(detect_add),
                 .write_enb_reg (write_enb_reg),
			     .clock		    (clock),
				 .resetn		(resetn),
				 .empty_0		(empty_0),
				 .empty_1		(empty_1),
				 .empty_2		(empty_2),
				 .full_0		(full_0),
				 .full_1		(full_1),
				 .full_2		(full_2),		  
				 .read_enb_0	(read_enb_0),
				 .read_enb_1	(read_enb_1),
				 .read_enb_2	(read_enb_2),
	             .data_in		(data_in[1:0]),
				 .write_enb	    (write_enb),
				 .fifo_full	    (fifo_full),
				 .soft_reset_0	(soft_reset_0),
				 .soft_reset_1	(soft_reset_1),
				 .soft_reset_2  (soft_reset_2),
				 .vld_out_0	    (vld_out_0),
				 .vld_out_1	    (vld_out_1),
				 .vld_out_2	    (vld_out_2));


 
router_register REG(.clock	       (clock),
					.resetn		   (resetn),
				    .pkt_valid	   (pkt_valid),
				    .fifo_full	   (fifo_full),
				    .rst_int_reg   (rst_int_reg),
					.detect_add	   (detect_add),
				    .ld_state	   (ld_state),
					.laf_state	   (laf_state),
					.full_state	   (full_state),
					.lfd_state	   (lfd_state),
					.data_in	   (data_in),								   
					.parity_done   (parity_done),
					.low_pkt_valid (low_pkt_valid),
					.err	       (error),
					.dout		   (dout)); 
					
endmodule
module router_top(input clock,resetn,read_enb_0,read_enb_1,read_enb_2,pkt_valid,input [7:0]data_in,
                  output [7:0]data_out_0,data_out_1,data_out_2,output vld_out_0,vld_out_1,vld_out_2,error,busy);

				  


wire [2:0] write_enb;
wire [7:0] dout;



router_fifo FIFO_0(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_0),
				   .write_enb	(write_enb[0]),
				   .read_enb	(read_enb_0),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_0),
				   .empty		(empty_0),
				   .full		(full_0));

router_fifo FIFO_1(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_1),
				   .write_enb	(write_enb[1]),
				   .read_enb	(read_enb_1),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_1),
				   .empty		(empty_1),
				   .full		(full_1));
				   
router_fifo FIFO_2(.clock		(clock),
				   .resetn		(resetn),
				   .soft_reset	(soft_reset_2),
				   .write_enb	(write_enb[2]),
				   .read_enb	(read_enb_2),
				   .lfd_state	(lfd_state),
				   .data_in		(dout),
				   .data_out	(data_out_2),
				   .empty		(empty_2),
				   .full		(full_2));
				   


router_fsm FSM(.clock			(clock),
			   .resetn			(resetn),
			   .pkt_valid		(pkt_valid),
			   .low_pkt_valid	(low_pkt_valid),
			   .parity_done 	(parity_done),
			   .soft_reset_0	(soft_reset_0),
			   .soft_reset_1	(soft_reset_1),
			   .soft_reset_2	(soft_reset_2),
			   .fifo_full		(fifo_full),
			   .fifo_empty_0	(empty_0),
			   .fifo_empty_1	(empty_1),
			   .fifo_empty_2	(empty_2),
			   .data_in			(data_in[1:0]),
			   .detect_add		(detect_add),
			   .ld_state		(ld_state),
			   .laf_state		(laf_state),
			   .full_state		(full_state),
			   .write_enb_reg	(write_enb_reg),
			   .rst_int_reg		(rst_int_reg),	   
			   .lfd_state		(lfd_state),
	           .busy			(busy));
			   


router_sync SYNC(.detect_add	(detect_add),
                 .write_enb_reg (write_enb_reg),
			     .clock		    (clock),
				 .resetn		(resetn),
				 .empty_0		(empty_0),
				 .empty_1		(empty_1),
				 .empty_2		(empty_2),
				 .full_0		(full_0),
				 .full_1		(full_1),
				 .full_2		(full_2),		  
				 .read_enb_0	(read_enb_0),
				 .read_enb_1	(read_enb_1),
				 .read_enb_2	(read_enb_2),
	             .data_in		(data_in[1:0]),
				 .write_enb	    (write_enb),
				 .fifo_full	    (fifo_full),
				 .soft_reset_0	(soft_reset_0),
				 .soft_reset_1	(soft_reset_1),
				 .soft_reset_2  (soft_reset_2),
				 .vld_out_0	    (vld_out_0),
				 .vld_out_1	    (vld_out_1),
				 .vld_out_2	    (vld_out_2));


 
router_register REG(.clock	       (clock),
					.resetn		   (resetn),
				    .pkt_valid	   (pkt_valid),
				    .fifo_full	   (fifo_full),
				    .rst_int_reg   (rst_int_reg),
					.detect_add	   (detect_add),
				    .ld_state	   (ld_state),
					.laf_state	   (laf_state),
					.full_state	   (full_state),
					.lfd_state	   (lfd_state),
					.data_in	   (data_in),								   
					.parity_done   (parity_done),
					.low_pkt_valid (low_pkt_valid),
					.err	       (error),
					.dout		   (dout)); 
					
endmodule