data/full_repos/permissive/500727441/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/500727441/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500727441/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500727441/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500727441/verilog/rtl/user_proj_example.v:182: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = ~{(`MPRJ_IO_PADS-1){rst}};\n                       ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output reg wbs_ack_o,
    output reg [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

localparam [31:0] X_INIT = 32'hDE78D681;
localparam [31:0] Y_INIT = 32'hFEEE4640;
localparam [31:0] Z_INIT = 32'hFE8E511B;

    wire clk;
    wire rst;

	wire [31:0]x;
	wire [31:0]y;
	wire [31:0]z;
	
	reg [31:0]x_init, x_data;
	reg [31:0]y_init, y_data;
	reg [31:0]z_init, z_data;
	
	reg [23:0]set_scroll_num;
	reg [3:0]rng_en;
	reg smp_en;
  
  
  wire [31:0] aes_dout;
  wire [31:0] aes_din;
  wire aes_cs;
  wire aes_we;
  reg  crypto_rng_en;

  assign aes_cs  = wbs_stb_i && wbs_cyc_i && ((wbs_adr_i[11:8] == 4'h0) || (wbs_adr_i[11:8] == 4'h9));
  assign aes_we  = wbs_stb_i && wbs_cyc_i && wbs_we_i && ((wbs_adr_i[11:8] == 4'h0) || (wbs_adr_i[11:8] == 4'h9));
  assign aes_din = (wbs_adr_i[11:8] == 4'h0) ? wbs_dat_i :
                   (wbs_adr_i[11:8] == 4'h9) ? x_data : 32'h0;



	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			x_init <= X_INIT;
			y_init <= Y_INIT;
			z_init <= Z_INIT;
			set_scroll_num <= {8'h4d, 8'h4c, 8'h4b};
			rng_en <= 4'h3;
			smp_en <= 1'b0;
      crypto_rng_en <= 1'b0;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h804)begin
			x_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h808)begin
			y_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h80c)begin
			z_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h810)begin
			set_scroll_num <= wbs_dat_i[23:0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h814)begin
			rng_en <= wbs_dat_i[3:0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h818)begin
			smp_en <= wbs_dat_i[0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h840)begin
			crypto_rng_en <= wbs_dat_i[0];
		end else begin
			smp_en <= 1'b0;
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_dat_o <= 32'h0;
		end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
      if (wbs_adr_i[11:8] == 4'h0) begin
        wbs_dat_o <= aes_dout;
      end else begin
        case(wbs_adr_i[11:0])
          12'h804	: wbs_dat_o <= x_init;
          12'h808	: wbs_dat_o <= y_init;
          12'h80c	: wbs_dat_o <= z_init;
          12'h810	: wbs_dat_o <= {8'h0, set_scroll_num};
          12'h814	: wbs_dat_o <= {28'h0, rng_en};
          12'h818	: wbs_dat_o <= smp_en;
          12'h81c	: wbs_dat_o <= x_data;
          12'h820	: wbs_dat_o <= y_data;
          12'h824	: wbs_dat_o <= z_data;
          default	: wbs_dat_o <= 32'h0;
        endcase
      end
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_ack_o <= 1'b0;
		end else begin
			wbs_ack_o <= (wbs_stb_i && wbs_cyc_i);
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			x_data <= 32'h0;
			y_data <= 32'h0;
			z_data <= 32'h0;
		end else if (smp_en) begin
		  x_data <= x;
			y_data <= y;
			z_data <= z;
		end
	end



    assign io_out = crypto_rng_en ? aes_dout : x;
    assign io_oeb = ~{(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{32{1'b0}}, z, y, x};
	

    assign clk = (~la_oenb[96]) ? la_data_in[96]: wb_clk_i;
    assign rst = (~la_oenb[97]) ? la_data_in[97]: wb_rst_i;

    rng_chaos_scroll u_rng_chaos_chaos (
        .clk(clk),
        .rst(rst),
        .en(rng_en),
		.x_init(x_init),
		.y_init(y_init),
		.z_init(z_init),
		.Lx(set_scroll_num[3:0]),
		.Ux(set_scroll_num[6:4]),
		.Ly(set_scroll_num[11:8]),
		.Uy(set_scroll_num[14:12]),
		.Lz(set_scroll_num[19:16]),
		.Uz(set_scroll_num[22:20]),
		.x(x),
		.y(y),
		.z(z)
    );
    
    aes aes_inst(

      .clk(clk),
      .reset_n(~rst),


      .cs(aes_cs),
      .we(aes_we),


      .address(wbs_adr_i[7:0]),
      .write_data(aes_din),
      .read_data(aes_dout)
    );

endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output reg wbs_ack_o,
    output reg [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


localparam [31:0] X_INIT = 32'hDE78D681;
localparam [31:0] Y_INIT = 32'hFEEE4640;
localparam [31:0] Z_INIT = 32'hFE8E511B;

    wire clk;
    wire rst;

	wire [31:0]x;
	wire [31:0]y;
	wire [31:0]z;
	
	reg [31:0]x_init, x_data;
	reg [31:0]y_init, y_data;
	reg [31:0]z_init, z_data;
	
	reg [23:0]set_scroll_num;
	reg [3:0]rng_en;
	reg smp_en;
  
  
  wire [31:0] aes_dout;
  wire [31:0] aes_din;
  wire aes_cs;
  wire aes_we;
  reg  crypto_rng_en;

  assign aes_cs  = wbs_stb_i && wbs_cyc_i && ((wbs_adr_i[11:8] == 4'h0) || (wbs_adr_i[11:8] == 4'h9));
  assign aes_we  = wbs_stb_i && wbs_cyc_i && wbs_we_i && ((wbs_adr_i[11:8] == 4'h0) || (wbs_adr_i[11:8] == 4'h9));
  assign aes_din = (wbs_adr_i[11:8] == 4'h0) ? wbs_dat_i :
                   (wbs_adr_i[11:8] == 4'h9) ? x_data : 32'h0;



	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			x_init <= X_INIT;
			y_init <= Y_INIT;
			z_init <= Z_INIT;
			set_scroll_num <= {8'h4d, 8'h4c, 8'h4b};
			rng_en <= 4'h3;
			smp_en <= 1'b0;
      crypto_rng_en <= 1'b0;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h804)begin
			x_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h808)begin
			y_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h80c)begin
			z_init <= wbs_dat_i;
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h810)begin
			set_scroll_num <= wbs_dat_i[23:0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h814)begin
			rng_en <= wbs_dat_i[3:0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h818)begin
			smp_en <= wbs_dat_i[0];
		end else if (wbs_stb_i && wbs_cyc_i && wbs_we_i && wbs_adr_i[11:0] == 12'h840)begin
			crypto_rng_en <= wbs_dat_i[0];
		end else begin
			smp_en <= 1'b0;
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_dat_o <= 32'h0;
		end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
      if (wbs_adr_i[11:8] == 4'h0) begin
        wbs_dat_o <= aes_dout;
      end else begin
        case(wbs_adr_i[11:0])
          12'h804	: wbs_dat_o <= x_init;
          12'h808	: wbs_dat_o <= y_init;
          12'h80c	: wbs_dat_o <= z_init;
          12'h810	: wbs_dat_o <= {8'h0, set_scroll_num};
          12'h814	: wbs_dat_o <= {28'h0, rng_en};
          12'h818	: wbs_dat_o <= smp_en;
          12'h81c	: wbs_dat_o <= x_data;
          12'h820	: wbs_dat_o <= y_data;
          12'h824	: wbs_dat_o <= z_data;
          default	: wbs_dat_o <= 32'h0;
        endcase
      end
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_ack_o <= 1'b0;
		end else begin
			wbs_ack_o <= (wbs_stb_i && wbs_cyc_i);
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			x_data <= 32'h0;
			y_data <= 32'h0;
			z_data <= 32'h0;
		end else if (smp_en) begin
		  x_data <= x;
			y_data <= y;
			z_data <= z;
		end
	end



    assign io_out = crypto_rng_en ? aes_dout : x;
    assign io_oeb = ~{(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{32{1'b0}}, z, y, x};
	

    assign clk = (~la_oenb[96]) ? la_data_in[96]: wb_clk_i;
    assign rst = (~la_oenb[97]) ? la_data_in[97]: wb_rst_i;

    rng_chaos_scroll u_rng_chaos_chaos (
        .clk(clk),
        .rst(rst),
        .en(rng_en),
		.x_init(x_init),
		.y_init(y_init),
		.z_init(z_init),
		.Lx(set_scroll_num[3:0]),
		.Ux(set_scroll_num[6:4]),
		.Ly(set_scroll_num[11:8]),
		.Uy(set_scroll_num[14:12]),
		.Lz(set_scroll_num[19:16]),
		.Uz(set_scroll_num[22:20]),
		.x(x),
		.y(y),
		.z(z)
    );
    
    aes aes_inst(

      .clk(clk),
      .reset_n(~rst),


      .cs(aes_cs),
      .we(aes_we),


      .address(wbs_adr_i[7:0]),
      .write_data(aes_din),
      .read_data(aes_dout)
    );

endmodule