data/full_repos/permissive/431605717/Code/RV32IM/EX_MEM.v
data/verilator_xmls/bce6d075-a202-4eda-a80c-0dd8988f5b23.xml
module exmemreg(clk,clrn,inst_i,pc_i,next_pc_i,m_addr_i,d_t_mem_i,wreg_i,wr_i,wmem_i,rmem_i,i_load_i,alu_out_i,PCSrc_i,inst_decode_i,inst_o,pc_o,next_pc_o,m_addr_o,d_t_mem_o,wreg_o,wr_o,wmem_o,rmem_o,i_load_o,alu_out_o,PCSrc_o,inst_decode_o);
    input             clk, clrn;
    input      [31:0] pc_i;
    input      [31:0] next_pc_i;
    input      [31:0] inst_i;
    input      [31:0] m_addr_i;
    input      [31:0] d_t_mem_i;
    input             wreg_i;
    input       [4:0] wr_i;
    input             wmem_i;
    input             rmem_i;
    input             i_load_i;
    input      [31:0] alu_out_i;
    input             PCSrc_i;
    input      [36:0] inst_decode_i;
    
    output reg [31:0] next_pc_o;
    output reg [31:0] inst_o;
    output reg [31:0] pc_o;
    output reg [31:0] m_addr_o;
    output reg [31:0] d_t_mem_o;
    output reg        wreg_o;
    output reg  [4:0] wr_o;
    output reg        wmem_o;
    output reg        rmem_o;
    output reg        i_load_o;
    output reg [31:0] alu_out_o;
    output reg        PCSrc_o;
    output reg [36:0] inst_decode_o;

    always @ (posedge clk) begin
        if (clrn) begin
            next_pc_o     <= next_pc_i;
            inst_o        <= inst_i;
            pc_o          <= pc_i;
            m_addr_o      <= m_addr_i;
            d_t_mem_o     <= d_t_mem_i;
            wreg_o        <= wreg_i;
            wr_o          <= wr_i;
            wmem_o        <= wmem_i;
            rmem_o        <= rmem_i;
            i_load_o      <= i_load_i;
            alu_out_o     <= alu_out_i;
            PCSrc_o       <= PCSrc_i;
            inst_decode_o <= inst_decode_i;
        end
        else begin
            next_pc_o     <= 0;
            inst_o        <= 0;
            pc_o          <= 0;
            m_addr_o      <= 0;
            d_t_mem_o     <= 0;
            wreg_o        <= 0;
            wr_o          <= 0;
            wmem_o        <= 0;
            rmem_o        <= 0;
            i_load_o      <= 0;
            alu_out_o     <= 0;
            PCSrc_o       <= 0;
            inst_decode_o <= 0;
        end
    end
    
endmodule
module exmemreg(clk,clrn,inst_i,pc_i,next_pc_i,m_addr_i,d_t_mem_i,wreg_i,wr_i,wmem_i,rmem_i,i_load_i,alu_out_i,PCSrc_i,inst_decode_i,inst_o,pc_o,next_pc_o,m_addr_o,d_t_mem_o,wreg_o,wr_o,wmem_o,rmem_o,i_load_o,alu_out_o,PCSrc_o,inst_decode_o);

    input             clk, clrn;
    input      [31:0] pc_i;
    input      [31:0] next_pc_i;
    input      [31:0] inst_i;
    input      [31:0] m_addr_i;
    input      [31:0] d_t_mem_i;
    input             wreg_i;
    input       [4:0] wr_i;
    input             wmem_i;
    input             rmem_i;
    input             i_load_i;
    input      [31:0] alu_out_i;
    input             PCSrc_i;
    input      [36:0] inst_decode_i;
    
    output reg [31:0] next_pc_o;
    output reg [31:0] inst_o;
    output reg [31:0] pc_o;
    output reg [31:0] m_addr_o;
    output reg [31:0] d_t_mem_o;
    output reg        wreg_o;
    output reg  [4:0] wr_o;
    output reg        wmem_o;
    output reg        rmem_o;
    output reg        i_load_o;
    output reg [31:0] alu_out_o;
    output reg        PCSrc_o;
    output reg [36:0] inst_decode_o;

    always @ (posedge clk) begin
        if (clrn) begin
            next_pc_o     <= next_pc_i;
            inst_o        <= inst_i;
            pc_o          <= pc_i;
            m_addr_o      <= m_addr_i;
            d_t_mem_o     <= d_t_mem_i;
            wreg_o        <= wreg_i;
            wr_o          <= wr_i;
            wmem_o        <= wmem_i;
            rmem_o        <= rmem_i;
            i_load_o      <= i_load_i;
            alu_out_o     <= alu_out_i;
            PCSrc_o       <= PCSrc_i;
            inst_decode_o <= inst_decode_i;
        end
        else begin
            next_pc_o     <= 0;
            inst_o        <= 0;
            pc_o          <= 0;
            m_addr_o      <= 0;
            d_t_mem_o     <= 0;
            wreg_o        <= 0;
            wr_o          <= 0;
            wmem_o        <= 0;
            rmem_o        <= 0;
            i_load_o      <= 0;
            alu_out_o     <= 0;
            PCSrc_o       <= 0;
            inst_decode_o <= 0;
        end
    end
    
endmodule