data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n   initial #32 rst = 0;\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:37: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:39: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:50: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("sd_spi_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:51: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,sd_spi_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n     #10000 $finish();\n     ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sd_spi_tb;

   reg clk = 0;
   always #5 clk = ~clk;
   reg rst = 1;
   initial #32 rst = 0;

   wire sd_clk, sd_mosi, sd_miso;
   wire [7:0] clk_div = 12;
   wire [7:0] send_dat = 23;
   wire [7:0] rcv_dat;

   wire       ready;
   reg 	      go = 0;
   initial 
     begin
	repeat (100)
	  @(posedge clk);
	go <= 1;
	@(posedge clk);
	go <= 0;
     end
   
   sd_spi dut(.clk(clk),.rst(rst),
	      .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
	      .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
	      .go(go),.ready(ready) );

   initial    
     begin 
	$dumpfile("sd_spi_tb.vcd");
	$dumpvars(0,sd_spi_tb);
     end

   initial
     #10000 $finish();
   
endmodule
module sd_spi_tb;


   reg clk = 0;
   always #5 clk = ~clk;
   reg rst = 1;
   initial #32 rst = 0;

   wire sd_clk, sd_mosi, sd_miso;
   wire [7:0] clk_div = 12;
   wire [7:0] send_dat = 23;
   wire [7:0] rcv_dat;

   wire       ready;
   reg 	      go = 0;
   initial 
     begin
	repeat (100)
	  @(posedge clk);
	go <= 1;
	@(posedge clk);
	go <= 0;
     end
   
   sd_spi dut(.clk(clk),.rst(rst),
	      .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
	      .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
	      .go(go),.ready(ready) );

   initial    
     begin 
	$dumpfile("sd_spi_tb.vcd");
	$dumpvars(0,sd_spi_tb);
     end

   initial
     #10000 $finish();
   
endmodule