data/full_repos/permissive/528147991/scr/data_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528147991/scr/data_mem.v:23: Bit extraction of array[100:0] requires 7 bit index, not 21 bits.\n                                                                      : ... In instance data_mem\n   mem[addr] <= write;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/528147991/scr/data_mem.v:27: Bit extraction of array[100:0] requires 7 bit index, not 21 bits.\n                                                                      : ... In instance data_mem\n assign read = mem[addr];\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module data_mem(clk, MemWrite, addr, write, read);

	input clk, MemWrite;
	input [20:0] addr;
	input [31:0] write;
	output [31:0] read;
	integer Spulse = 0;
	
	reg [31:0] mem[100:0];
	
	
	always @(posedge clk) 
	begin
		if (Spulse==0)
		begin
			mem[0] <= 32'd0;
		
		Spulse = 1;
		end
		
		if(MemWrite)
		begin
			mem[addr] <= write;
		end
	end
	
	assign read = mem[addr];
	
endmodule
module data_mem(clk, MemWrite, addr, write, read);


	input clk, MemWrite;
	input [20:0] addr;
	input [31:0] write;
	output [31:0] read;
	integer Spulse = 0;
	
	reg [31:0] mem[100:0];
	
	
	always @(posedge clk) 
	begin
		if (Spulse==0)
		begin
			mem[0] <= 32'd0;
		
		Spulse = 1;
		end
		
		if(MemWrite)
		begin
			mem[addr] <= write;
		end
	end
	
	assign read = mem[addr];
	
endmodule