data/full_repos/permissive/518006745/src/top.v
1: b"%Error: data/full_repos/permissive/518006745/src/top.v:43: Cannot find file containing module: 'mypll'\n    mypll pll (\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/518006745/src,data/full_repos/permissive/518006745/mypll\n             data/full_repos/permissive/518006745/src,data/full_repos/permissive/518006745/mypll.v\n             data/full_repos/permissive/518006745/src,data/full_repos/permissive/518006745/mypll.sv\n             mypll\n             mypll.v\n             mypll.sv\n             obj_dir/mypll\n             obj_dir/mypll.v\n             obj_dir/mypll.sv\n%Error: data/full_repos/permissive/518006745/src/top.v:51: Cannot find file containing module: 'delay'\n    delay #( .ctr_width (4) ) pll_delay (        \n    ^~~~~\n%Error: data/full_repos/permissive/518006745/src/top.v:63: Cannot find file containing module: 'dBounce'\n dBounce #(\n ^~~~~~~\n%Error: data/full_repos/permissive/518006745/src/top.v:88: Cannot find file containing module: 'picorv32'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/518006745/src/top.v:121: Cannot find file containing module: 'myrom'\n    myrom rom (      \n    ^~~~~\n%Error: data/full_repos/permissive/518006745/src/top.v:142: Cannot find file containing module: 'btRAM'\n btRAM #(\n ^~~~~\n%Error: data/full_repos/permissive/518006745/src/top.v:195: Cannot find file containing module: 'simpleuart'\n simpleuart uart (\n ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module top (
		input wire clock27M,
		input wire S1, S2,
		output wire [6:1] LEDS,


		output wire TXD,
		input  wire RXD
	);
	

	localparam ROM_ADDR		=	32'h0000_0000;
	localparam ROM_ADDR_END	=	32'h0000_1FFF;
	localparam RAM_ADDR		=	32'h0000_2000;
	localparam RAM_ADDR_END	=	32'h0000_23ff;
	
	localparam LEDS_ADDR	=	32'h0200_0000;

    localparam UART_DAT_ADDR =  32'h0200_4000;
	localparam UART_DIV_ADDR =  32'h0200_4008;


	
	
	localparam RESET_ADDR	=	ROM_ADDR;
	localparam IRQ_ADDR		=	32'h0000_0008;
	localparam STACK_ADDR	=	RAM_ADDR_END + 1;

	localparam SYSTEM_CLOCK =   50_000_000;

	wire clock_main;
	wire locked;
    wire lock_pre;

    mypll pll (
        .clkout (clock_main),
        .lock   (lock_pre),
        .reset  (~S1),
        .clkin  (clock27M)
    );


    delay #( .ctr_width (4) ) pll_delay (
        .clk_i  (clock_main),
        .rst_i  (lock_pre),
        .rst_o  (locked)
    );



	wire dS2;
	always @(posedge clock_main)
		irq[20] <= ~dS2;

	dBounce #(
        .CLOCK      (SYSTEM_CLOCK),
        .WINDOWSIZE (10_000_000)
    ) db (
        .resetn     (locked),
		.i_clk	    (clock_main),
		.i_db 	    (S2),
		.o_db       (dS2)
	);



	wire mem_valid;
	wire mem_ready;
	wire mem_instr;
	wire [31:0] mem_addr;
	wire [31:0] mem_wdata;
	wire [3:0]  mem_wstrb;
	wire [31:0] mem_rdata;
	reg rom_ready;
	wire trapsig;
	reg [31:0] irq;
	wire [31:0] eoi;


	picorv32 #(
		.ENABLE_COUNTERS	(1),
		.BARREL_SHIFTER	    (1),
		.ENABLE_IRQ			(1),
		.ENABLE_IRQ_TIMER	(1),
		.PROGADDR_RESET	    (RESET_ADDR),
		.PROGADDR_IRQ		(IRQ_ADDR),
		.STACKADDR			(STACK_ADDR)
	) cpu (
		.clk		(clock_main),
		.resetn	    (locked),
		.trap		(trapsig),
		.irq		(irq),
		.eoi		(eoi),

		.mem_valid	(mem_valid),
		.mem_instr	(mem_instr),
		.mem_ready	(mem_ready),
		.mem_addr	(mem_addr),
		.mem_wdata	(mem_wdata),
		.mem_wstrb	(mem_wstrb),
		.mem_rdata	(mem_rdata)
	);






	wire [31:0] romout;
    localparam ROM_DEPTH = 2048;


    myrom rom (
        .dout   (romout),
        .clk    (clock_main),
        .oce    (1'b0),
        .ce     (1'b1),
        .reset  (~locked),
        .ad     (mem_addr[$clog2(ROM_DEPTH)+2-1:2])
    );

	always @(posedge clock_main) 
		rom_ready <= mem_valid && !mem_ready && (mem_addr >= ROM_ADDR) && (mem_addr <= ROM_ADDR_END);

		



	reg ram_ready;
	reg ram_wren;
	wire [31:0] ram_out;
    localparam RAM_DEPTH = 256;

	btRAM #(
		.DATA_WIDTH(32),
		.DATA_DEPTH(RAM_DEPTH)
	) ram (
		.address	(mem_addr[$clog2(RAM_DEPTH)+2-1:2]),
		.byteena    (mem_wstrb),
		.clock	    (clock_main),
		.data		(mem_wdata),
		.wren		(ram_wren),
		.q			(ram_out)
	);


	always @(posedge clock_main) begin
		ram_ready <= mem_valid && !mem_ready && (mem_addr >= RAM_ADDR) && (mem_addr <= RAM_ADDR_END);
		ram_wren <= (mem_valid && !mem_ready &&  (mem_addr >= RAM_ADDR) && (mem_addr <= RAM_ADDR_END) && |mem_wstrb);
	end





	reg leds_ready;
	reg [31:0] ledreg;
	always @(posedge clock_main) 
		leds_ready <= mem_valid && !mem_ready && mem_addr == LEDS_ADDR;

	always @(posedge clock_main) begin
		if (!locked) 
			ledreg <= 32'h0000_0033;
		else if (mem_valid && mem_addr == LEDS_ADDR) begin
			if (mem_wstrb[0]) ledreg[7:0] <= mem_wdata[7:0];
			if (mem_wstrb[1]) ledreg[15:8] <= mem_wdata[15:8];
			if (mem_wstrb[2]) ledreg[23:16] <= mem_wdata[23:16];
			if (mem_wstrb[3]) ledreg[31:24] <= mem_wdata[31:24];
		end
	end
	assign LEDS = ~ledreg[5:0];




	wire uart_div_ready = mem_valid && mem_addr == UART_DIV_ADDR;
	wire [31:0] uart_div_reg_do;
	

	wire uart_dat_wait;
	wire uart_data_ready = mem_valid && (mem_addr == UART_DAT_ADDR);
	

	wire [31:0] uart_dat_do;
	

	simpleuart uart (
		.clk			( clock_main	),
		.resetn			( locked	),
		.ser_tx			( TXD		),
		.ser_rx			( RXD		),


		.reg_div_we		( uart_div_ready ? mem_wstrb : 4'h0),
		.reg_div_di		( mem_wdata	),
		.reg_div_do		( uart_div_reg_do	),


		.reg_dat_we		( uart_data_ready ? mem_wstrb[0] : 1'b0),
		.reg_dat_di		( mem_wdata			),
		.reg_dat_wait	( uart_dat_wait	),
		
		.reg_dat_re		( uart_data_ready && !mem_wstrb ),
		.reg_dat_do		( uart_dat_do		)
	);


	assign mem_ready = rom_ready || 
                        ram_ready || 
                        leds_ready || 
                        uart_div_ready ||
                        uart_data_ready && !uart_dat_wait;
							
	assign mem_rdata = 	rom_ready       ? romout : 
                        ram_ready       ? ram_out :
                        leds_ready      ? ledreg :
                        uart_div_ready  ? uart_div_reg_do :
                        uart_data_ready ? uart_dat_do :
                        32'h0;

endmodule
module top (
		input wire clock27M,
		input wire S1, S2,
		output wire [6:1] LEDS,


		output wire TXD,
		input  wire RXD
	);

	

	localparam ROM_ADDR		=	32'h0000_0000;
	localparam ROM_ADDR_END	=	32'h0000_1FFF;
	localparam RAM_ADDR		=	32'h0000_2000;
	localparam RAM_ADDR_END	=	32'h0000_23ff;
	
	localparam LEDS_ADDR	=	32'h0200_0000;

    localparam UART_DAT_ADDR =  32'h0200_4000;
	localparam UART_DIV_ADDR =  32'h0200_4008;


	
	
	localparam RESET_ADDR	=	ROM_ADDR;
	localparam IRQ_ADDR		=	32'h0000_0008;
	localparam STACK_ADDR	=	RAM_ADDR_END + 1;

	localparam SYSTEM_CLOCK =   50_000_000;

	wire clock_main;
	wire locked;
    wire lock_pre;

    mypll pll (
        .clkout (clock_main),
        .lock   (lock_pre),
        .reset  (~S1),
        .clkin  (clock27M)
    );


    delay #( .ctr_width (4) ) pll_delay (
        .clk_i  (clock_main),
        .rst_i  (lock_pre),
        .rst_o  (locked)
    );



	wire dS2;
	always @(posedge clock_main)
		irq[20] <= ~dS2;

	dBounce #(
        .CLOCK      (SYSTEM_CLOCK),
        .WINDOWSIZE (10_000_000)
    ) db (
        .resetn     (locked),
		.i_clk	    (clock_main),
		.i_db 	    (S2),
		.o_db       (dS2)
	);



	wire mem_valid;
	wire mem_ready;
	wire mem_instr;
	wire [31:0] mem_addr;
	wire [31:0] mem_wdata;
	wire [3:0]  mem_wstrb;
	wire [31:0] mem_rdata;
	reg rom_ready;
	wire trapsig;
	reg [31:0] irq;
	wire [31:0] eoi;


	picorv32 #(
		.ENABLE_COUNTERS	(1),
		.BARREL_SHIFTER	    (1),
		.ENABLE_IRQ			(1),
		.ENABLE_IRQ_TIMER	(1),
		.PROGADDR_RESET	    (RESET_ADDR),
		.PROGADDR_IRQ		(IRQ_ADDR),
		.STACKADDR			(STACK_ADDR)
	) cpu (
		.clk		(clock_main),
		.resetn	    (locked),
		.trap		(trapsig),
		.irq		(irq),
		.eoi		(eoi),

		.mem_valid	(mem_valid),
		.mem_instr	(mem_instr),
		.mem_ready	(mem_ready),
		.mem_addr	(mem_addr),
		.mem_wdata	(mem_wdata),
		.mem_wstrb	(mem_wstrb),
		.mem_rdata	(mem_rdata)
	);






	wire [31:0] romout;
    localparam ROM_DEPTH = 2048;


    myrom rom (
        .dout   (romout),
        .clk    (clock_main),
        .oce    (1'b0),
        .ce     (1'b1),
        .reset  (~locked),
        .ad     (mem_addr[$clog2(ROM_DEPTH)+2-1:2])
    );

	always @(posedge clock_main) 
		rom_ready <= mem_valid && !mem_ready && (mem_addr >= ROM_ADDR) && (mem_addr <= ROM_ADDR_END);

		



	reg ram_ready;
	reg ram_wren;
	wire [31:0] ram_out;
    localparam RAM_DEPTH = 256;

	btRAM #(
		.DATA_WIDTH(32),
		.DATA_DEPTH(RAM_DEPTH)
	) ram (
		.address	(mem_addr[$clog2(RAM_DEPTH)+2-1:2]),
		.byteena    (mem_wstrb),
		.clock	    (clock_main),
		.data		(mem_wdata),
		.wren		(ram_wren),
		.q			(ram_out)
	);


	always @(posedge clock_main) begin
		ram_ready <= mem_valid && !mem_ready && (mem_addr >= RAM_ADDR) && (mem_addr <= RAM_ADDR_END);
		ram_wren <= (mem_valid && !mem_ready &&  (mem_addr >= RAM_ADDR) && (mem_addr <= RAM_ADDR_END) && |mem_wstrb);
	end





	reg leds_ready;
	reg [31:0] ledreg;
	always @(posedge clock_main) 
		leds_ready <= mem_valid && !mem_ready && mem_addr == LEDS_ADDR;

	always @(posedge clock_main) begin
		if (!locked) 
			ledreg <= 32'h0000_0033;
		else if (mem_valid && mem_addr == LEDS_ADDR) begin
			if (mem_wstrb[0]) ledreg[7:0] <= mem_wdata[7:0];
			if (mem_wstrb[1]) ledreg[15:8] <= mem_wdata[15:8];
			if (mem_wstrb[2]) ledreg[23:16] <= mem_wdata[23:16];
			if (mem_wstrb[3]) ledreg[31:24] <= mem_wdata[31:24];
		end
	end
	assign LEDS = ~ledreg[5:0];




	wire uart_div_ready = mem_valid && mem_addr == UART_DIV_ADDR;
	wire [31:0] uart_div_reg_do;
	

	wire uart_dat_wait;
	wire uart_data_ready = mem_valid && (mem_addr == UART_DAT_ADDR);
	

	wire [31:0] uart_dat_do;
	

	simpleuart uart (
		.clk			( clock_main	),
		.resetn			( locked	),
		.ser_tx			( TXD		),
		.ser_rx			( RXD		),


		.reg_div_we		( uart_div_ready ? mem_wstrb : 4'h0),
		.reg_div_di		( mem_wdata	),
		.reg_div_do		( uart_div_reg_do	),


		.reg_dat_we		( uart_data_ready ? mem_wstrb[0] : 1'b0),
		.reg_dat_di		( mem_wdata			),
		.reg_dat_wait	( uart_dat_wait	),
		
		.reg_dat_re		( uart_data_ready && !mem_wstrb ),
		.reg_dat_do		( uart_dat_do		)
	);


	assign mem_ready = rom_ready || 
                        ram_ready || 
                        leds_ready || 
                        uart_div_ready ||
                        uart_data_ready && !uart_dat_wait;
							
	assign mem_rdata = 	rom_ready       ? romout : 
                        ram_ready       ? ram_out :
                        leds_ready      ? ledreg :
                        uart_div_ready  ? uart_div_reg_do :
                        uart_data_ready ? uart_dat_do :
                        32'h0;

endmodule