data/full_repos/permissive/421450529/ID_EX_register.v
data/verilator_xmls/e53f4f01-21b6-40ba-931e-28665a9bdffa.xml
module ID_EX_register(
    input clk,
	 input reset,
	 input stall,
    input[31:0] IR_E_in,
    input[31:0] PC4_E_in,
    input[31:0] PC8_E_in,
    input[31:0] RS_E_trans_in,
    input[31:0] RT_E_trans_in,
    input[31:0] EXT_E_in,
	 input[4:0] write_register_E_in,
	 input Start_E_in,
    output reg[31:0] IR_E_out,
    output reg[31:0] PC4_E_out,
    output reg[31:0] PC8_E_out,
    output reg[31:0] RS_E_trans_out,
    output reg[31:0] RT_E_trans_out,
    output reg[31:0] EXT_E_out,
	 output reg[4:0] write_register_E_out,
	 output reg Start_E_out
    );
	 
	 initial begin
	        IR_E_out= 0;
			  PC4_E_out=0;
			  PC8_E_out=0;
			  RS_E_trans_out=0;
			  RT_E_trans_out=0;
			  EXT_E_out=0;
			  write_register_E_out=0;
			  Start_E_out=0;
	 end
     always@(posedge clk)begin
		  if(reset||stall)begin
			  IR_E_out= 0;
			  PC4_E_out=0;
			  PC8_E_out=0;
			  RS_E_trans_out=0;
			  RT_E_trans_out=0;
			  EXT_E_out=0;
			  write_register_E_out=0;
			  Start_E_out=0;
		  end
		  else begin
			  IR_E_out=IR_E_in;
			  PC4_E_out=PC4_E_in;
			  PC8_E_out=PC8_E_in;
			  RS_E_trans_out=RS_E_trans_in;
			  RT_E_trans_out=RT_E_trans_in;
			  EXT_E_out=EXT_E_in;
			  write_register_E_out=write_register_E_in;
			  Start_E_out=Start_E_in;
	     end
	  end
endmodule
module ID_EX_register(
    input clk,
	 input reset,
	 input stall,
    input[31:0] IR_E_in,
    input[31:0] PC4_E_in,
    input[31:0] PC8_E_in,
    input[31:0] RS_E_trans_in,
    input[31:0] RT_E_trans_in,
    input[31:0] EXT_E_in,
	 input[4:0] write_register_E_in,
	 input Start_E_in,
    output reg[31:0] IR_E_out,
    output reg[31:0] PC4_E_out,
    output reg[31:0] PC8_E_out,
    output reg[31:0] RS_E_trans_out,
    output reg[31:0] RT_E_trans_out,
    output reg[31:0] EXT_E_out,
	 output reg[4:0] write_register_E_out,
	 output reg Start_E_out
    );

	 
	 initial begin
	        IR_E_out= 0;
			  PC4_E_out=0;
			  PC8_E_out=0;
			  RS_E_trans_out=0;
			  RT_E_trans_out=0;
			  EXT_E_out=0;
			  write_register_E_out=0;
			  Start_E_out=0;
	 end
     always@(posedge clk)begin
		  if(reset||stall)begin
			  IR_E_out= 0;
			  PC4_E_out=0;
			  PC8_E_out=0;
			  RS_E_trans_out=0;
			  RT_E_trans_out=0;
			  EXT_E_out=0;
			  write_register_E_out=0;
			  Start_E_out=0;
		  end
		  else begin
			  IR_E_out=IR_E_in;
			  PC4_E_out=PC4_E_in;
			  PC8_E_out=PC8_E_in;
			  RS_E_trans_out=RS_E_trans_in;
			  RT_E_trans_out=RT_E_trans_in;
			  EXT_E_out=EXT_E_in;
			  write_register_E_out=write_register_E_in;
			  Start_E_out=Start_E_in;
	     end
	  end
endmodule