data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v
1: b'%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:3: Cannot find include file: pm_types.vh\n    `include "pm_types.vh" \n             ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog,data/full_repos/permissive/463204869/pm_types.vh\n             data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog,data/full_repos/permissive/463204869/pm_types.vh.v\n             data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog,data/full_repos/permissive/463204869/pm_types.vh.sv\n             pm_types.vh\n             pm_types.vh.v\n             pm_types.vh.sv\n             obj_dir/pm_types.vh\n             obj_dir/pm_types.vh.v\n             obj_dir/pm_types.vh.sv\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:4: Cannot find include file: noc_parameter.vh\n    ,`include "noc_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                       PM_CORE_SELECT = PM_TYPE_NONE,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:7: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                       CLKFREQ_MHZ = 100\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:8: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                     reset_pm_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0]            home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0]            host_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tck_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tms_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tdi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     jtag_tdo_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     jtag_tdo_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     uart_tx_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/pm_domain/source/rtl/verilog/pm_domain.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                     uart_rx_i\n    ^~~~~\n%Error: Exiting due to 22 error(s)\n'
module pm_domain #(
    `include "pm_types.vh"
    ,`include "noc_parameter.vh"
    ,parameter [NOC_MODID_SIZE-1:0] HOME_MODID = 0,
    parameter                       PM_CORE_SELECT = PM_TYPE_NONE,
    parameter                       CLKFREQ_MHZ = 100
)
(
    input  wire                                     clk_pm_i,
    input  wire                                     reset_pm_n_i,
    input  wire    [NOC_CHIPID_SIZE-1:0]            home_chipid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0]            host_chipid_i,
    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,
    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_raddr_o,
    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_waddr_i,
    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,
    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_raddr_i,
    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_waddr_o,

    input wire                                      jtag_tck_i,
    input wire                                      jtag_tms_i,
    input wire                                      jtag_tdi_i,
    output wire                                     jtag_tdo_o,
    output wire                                     jtag_tdo_en_o,

    output wire                                     uart_tx_o,
    input  wire                                     uart_rx_i
);


generate
if (PM_CORE_SELECT == PM_TYPE_ROCKET) begin: rocket
    pm_rocket #(
        .HOME_MODID                 (HOME_MODID),
        .CLKFREQ_MHZ                (CLKFREQ_MHZ)
    ) i_pm_rocket (
        .clk_pm_i                   (clk_pm_i),
        .reset_pm_n_i               (reset_pm_n_i),
        .home_chipid_i              (home_chipid_i),
        .host_chipid_i              (host_chipid_i),
        .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
        .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
        .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
        .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
        .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
        .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),
        
        .jtag_tck_i                 (jtag_tck_i),
        .jtag_tms_i                 (jtag_tms_i),
        .jtag_tdi_i                 (jtag_tdi_i),
        .jtag_tdo_o                 (jtag_tdo_o),
        .jtag_tdo_en_o              (jtag_tdo_en_o),

        .uart_tx_o                  (uart_tx_o),
        .uart_rx_i                  (uart_rx_i)
    );
end
else if (PM_CORE_SELECT == PM_TYPE_BOOM) begin: boom
    pm_boom #(
        .HOME_MODID                 (HOME_MODID),
        .CLKFREQ_MHZ                (CLKFREQ_MHZ)
    ) i_pm_boom (
        .clk_pm_i                   (clk_pm_i),
        .reset_pm_n_i               (reset_pm_n_i),
        .home_chipid_i              (home_chipid_i),
        .host_chipid_i              (host_chipid_i),
        .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
        .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
        .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
        .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
        .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
        .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),

        .jtag_tck_i                 (jtag_tck_i),
        .jtag_tms_i                 (jtag_tms_i),
        .jtag_tdi_i                 (jtag_tdi_i),
        .jtag_tdo_o                 (jtag_tdo_o),
        .jtag_tdo_en_o              (jtag_tdo_en_o),

        .uart_tx_o                  (uart_tx_o),
        .uart_rx_i                  (uart_rx_i)
    );
end
else begin: none
    assign noc_fifo_pm_in_raddr_o = {NOC_ASYNC_FIFO_AWIDTH{1'b0}};
    assign noc_fifo_pm_out_data_o = {NOC_ASYNC_FIFO_PACKET_SIZE{1'b0}};
    assign noc_fifo_pm_out_waddr_o = {NOC_ASYNC_FIFO_AWIDTH{1'b0}};
    assign jtag_tdo_o = 1'b0;
    assign jtag_tdo_en_o = 1'b0;
    assign uart_tx_o = 1'b1;
end
endgenerate

endmodule
module pm_domain #(
    `include "pm_types.vh"
    ,`include "noc_parameter.vh"
    ,parameter [NOC_MODID_SIZE-1:0] HOME_MODID = 0,
    parameter                       PM_CORE_SELECT = PM_TYPE_NONE,
    parameter                       CLKFREQ_MHZ = 100
)
(
    input  wire                                     clk_pm_i,
    input  wire                                     reset_pm_n_i,
    input  wire    [NOC_CHIPID_SIZE-1:0]            home_chipid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0]            host_chipid_i,
    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,
    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_raddr_o,
    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_in_waddr_i,
    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,
    input  wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_raddr_i,
    output wire    [NOC_ASYNC_FIFO_AWIDTH:0]        noc_fifo_pm_out_waddr_o,

    input wire                                      jtag_tck_i,
    input wire                                      jtag_tms_i,
    input wire                                      jtag_tdi_i,
    output wire                                     jtag_tdo_o,
    output wire                                     jtag_tdo_en_o,

    output wire                                     uart_tx_o,
    input  wire                                     uart_rx_i
);



generate
if (PM_CORE_SELECT == PM_TYPE_ROCKET) begin: rocket
    pm_rocket #(
        .HOME_MODID                 (HOME_MODID),
        .CLKFREQ_MHZ                (CLKFREQ_MHZ)
    ) i_pm_rocket (
        .clk_pm_i                   (clk_pm_i),
        .reset_pm_n_i               (reset_pm_n_i),
        .home_chipid_i              (home_chipid_i),
        .host_chipid_i              (host_chipid_i),
        .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
        .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
        .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
        .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
        .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
        .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),
        
        .jtag_tck_i                 (jtag_tck_i),
        .jtag_tms_i                 (jtag_tms_i),
        .jtag_tdi_i                 (jtag_tdi_i),
        .jtag_tdo_o                 (jtag_tdo_o),
        .jtag_tdo_en_o              (jtag_tdo_en_o),

        .uart_tx_o                  (uart_tx_o),
        .uart_rx_i                  (uart_rx_i)
    );
end
else if (PM_CORE_SELECT == PM_TYPE_BOOM) begin: boom
    pm_boom #(
        .HOME_MODID                 (HOME_MODID),
        .CLKFREQ_MHZ                (CLKFREQ_MHZ)
    ) i_pm_boom (
        .clk_pm_i                   (clk_pm_i),
        .reset_pm_n_i               (reset_pm_n_i),
        .home_chipid_i              (home_chipid_i),
        .host_chipid_i              (host_chipid_i),
        .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
        .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
        .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
        .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
        .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
        .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),

        .jtag_tck_i                 (jtag_tck_i),
        .jtag_tms_i                 (jtag_tms_i),
        .jtag_tdi_i                 (jtag_tdi_i),
        .jtag_tdo_o                 (jtag_tdo_o),
        .jtag_tdo_en_o              (jtag_tdo_en_o),

        .uart_tx_o                  (uart_tx_o),
        .uart_rx_i                  (uart_rx_i)
    );
end
else begin: none
    assign noc_fifo_pm_in_raddr_o = {NOC_ASYNC_FIFO_AWIDTH{1'b0}};
    assign noc_fifo_pm_out_data_o = {NOC_ASYNC_FIFO_PACKET_SIZE{1'b0}};
    assign noc_fifo_pm_out_waddr_o = {NOC_ASYNC_FIFO_AWIDTH{1'b0}};
    assign jtag_tdo_o = 1'b0;
    assign jtag_tdo_en_o = 1'b0;
    assign uart_tx_o = 1'b1;
end
endgenerate

endmodule