data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/max-compare-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/max-compare-tb.v:1: Cannot find include file: max-compare.v\n`include "max-compare.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/max-compare.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/max-compare.v.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/max-compare.v.sv\n             max-compare.v\n             max-compare.v.v\n             max-compare.v.sv\n             obj_dir/max-compare.v\n             obj_dir/max-compare.v.v\n             obj_dir/max-compare.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/max-compare-tb.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/max-compare.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/max-compare-tb.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/max-compare-tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module max_compare_tb;

reg signed [7:0] compare_a, compare_b;
wire signed [7:0] max_val;

max_compare dut
(
    compare_a, 
    compare_b, 
    max_val
);
defparam dut.WIDTH = 8; 

initial
begin
    $dumpfile("./build/rtl-sim/vcd/max-compare.vcd");
    $dumpvars;
end

integer i;
initial
begin
    compare_a = -12;
    compare_b = 124;
    #100;
end


endmodule
module max_compare_tb;


reg signed [7:0] compare_a, compare_b;
wire signed [7:0] max_val;

max_compare dut
(
    compare_a, 
    compare_b, 
    max_val
);
defparam dut.WIDTH = 8; 

initial
begin
    $dumpfile("./build/rtl-sim/vcd/max-compare.vcd");
    $dumpvars;
end

integer i;
initial
begin
    compare_a = -12;
    compare_b = 124;
    #100;
end


endmodule