data/full_repos/permissive/42434302/ivltests/pr1639968.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr1639968.v:8: Unsupported or unknown PLI call: $monitor\n $monitor($time,, "rf[0] is %h %h", rf[1], rf_0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr1639968.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $monitor($time,, "rf[0] is %h %h", rf[1], rf_0);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1639968.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 rf[1] = 16\'h0000;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1639968.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 rf[1] = 16\'hbeef;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1639968.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterArrayBug01;

 reg [15:0] rf[0:7];

 wire [15:0] rf_0 = rf[1];

 initial begin
 $monitor($time,, "rf[0] is %h %h", rf[1], rf_0);

 rf[1] = 16'hffff;
 #10 rf[1] = 16'h0000;
 #10 rf[1] = 16'hbeef;
 #10 $finish;
 end

 endmodule
module RegisterArrayBug01;


 reg [15:0] rf[0:7];

 wire [15:0] rf_0 = rf[1];

 initial begin
 $monitor($time,, "rf[0] is %h %h", rf[1], rf_0);

 rf[1] = 16'hffff;
 #10 rf[1] = 16'h0000;
 #10 rf[1] = 16'hbeef;
 #10 $finish;
 end

 endmodule