data/full_repos/permissive/415843050/cpu-src/ctc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/ctc.v:267: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'Address\' generates 3 bits.\n                                                                      : ... In instance CTC\n            if (Select == 1 && (Write_enable == 1 && Address == 4\'b100))\n                                                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/ctc.v:282: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'Address\' generates 3 bits.\n                                                                      : ... In instance CTC\n            if (Select == 1 && (Write_enable == 1 && Address == 4\'b110))\n                                                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module CTC(
    clock,reset,
    Read_enable,Write_enable,Select,Address,
    Write_data_in,Read_data_out,
    Pulse0_in,Pulse1_in,
    CTC0_output,CTC1_output
    );
    
    input clock;
    input reset;
    input Read_enable;
    input Write_enable;
    input Select;
    input[2:0]  Address;
    
    input Pulse0_in;
    input Pulse1_in;
    input[15:0] Write_data_in;
    output[15:0]    Read_data_out;
    
    output      CTC0_output;
    output      CTC1_output;
    
    
    reg     CTC0_output;
    reg     CTC1_output;
    reg[15:0]   Read_data_out;
    
    reg[15:0]   mode0,mode1;
    reg[15:0]   stat0_0,stat1_0;
    reg[15:0]   stat0_1,stat1_1;
    reg[15:0]   status0,status1;
    
    reg[15:0]   init0,init1;
    reg[15:0]   cnt0_0,cnt1_0;
    reg[15:0]   cnt0_1,cnt1_1;
    reg[15:0]   counter0,counter1;
    
    
    initial
    begin
        mode0 = 16'h0000;
        mode1 = 16'h0000;
        status0 = 16'h0000;
        status1 = 16'h0000;
        counter0 = 16'h0000;
        counter1 = 16'h0000;
    end
    

    always @(posedge clock)
    begin
        if (Select == 0 || reset == 1)
        begin
            CTC0_output = 1;
            CTC1_output = 1;
            init0 = 16'h0000;
            init1 = 16'h0000;
            cnt0_0 = 16'h0000;
            cnt1_0 = 16'h0000;
            stat0_0 = 16'h0000;
            stat1_0 = 16'h0000;
        end
        else
        begin
            if (Read_enable == 1)
            begin
                case (Address)

                    3'b000:
                    begin
                        Read_data_out = status0;
                        stat0_0 = status0 & 16'hFFFC;
                    end

                    3'b010:
                    begin
                        Read_data_out = status1;
                        stat1_0 = status1 & 16'hFFFC;
                    end

                    3'b100: Read_data_out = counter0;

                    3'b110: Read_data_out = counter1;
                    default: Read_data_out = 16'hZZZZ;
                endcase
            end
            else if (Write_enable == 1)
            begin
                case (Address)

                    3'b000:
                    begin
                        mode0 = Write_data_in;
                        stat0_0 = status0 & 16'h7FFC;
                    end

                    3'b010:
                    begin
                        mode1 = Write_data_in;
                        stat1_0 = status1 & 16'h7FFC;
                    end

                    3'b100:
                    begin
                        init0 = Write_data_in;
                        stat0_0 = status0 | 16'h8000;
                    end

                    3'b110:
                    begin
                        init1 = Write_data_in;
                        stat1_0 = status1 | 16'h8000;
                    end

                endcase
            end
        end
        

        if (status0[15] == 1'b0)
            CTC0_output = 1'b1;
        else
            if (mode0[0] == 1'b0)
            begin
                if (counter0 == 16'h0001)
                begin
                    CTC0_output = 1'b0;
                    stat0_0 = status0 | 16'h0001;
                    
                    if (mode0[1] == 1'b1)
                        cnt0_0 = init0;
                    else
                    begin
                        stat0_0 = stat0_0 & 16'h7FFF;
                        cnt0_0 = 16'h0000;
                    end
                end
                else
                begin
                    CTC0_output = 1'b1;
                    cnt0_0 = counter0 - 1'b1;
                    stat0_0 = status0 | 16'h8000;
                end
            end
        

        if (status1[15] == 1'b0)
            CTC1_output = 1'b1;
        else
            if (mode1[0] == 1'b0)
            begin
                 if (counter1 == 16'h0001)
                begin
                    CTC1_output = 1'b0;
                    stat1_0 = status1 | 16'h0001;
                    
                    if (mode1[1] == 1'b1)
                        cnt1_0 = init1;
                    else
                    begin
                        stat1_0 = stat1_0 & 16'h7FFF;
                        cnt1_0 = 16'h0000;
                    end
                end
                else
                begin
                    CTC1_output = 1'b1;
                    cnt1_0 = counter1 - 1'b1;
                    stat1_0 = status1 | 16'h8000;
                end
            end
    end
    

    always @(posedge Pulse0_in)
    begin
        if (status0[15] == 1'b1 && mode0[0] == 1'b1)
            if (counter0 == 16'h0001)
            begin
                stat0_1 = status0 | 16'h0002;
                
                if (mode0[1] == 1'b1)
                    cnt0_1 = init0;
                else
                begin
                    stat0_1 = stat0_1 & 16'h7FFF;
                    cnt0_1 = 16'h0000;
                end
            end
            else
            begin
                cnt0_1 = counter0 - 1'b1;
                stat0_1 = status0 | 16'h8000;
            end
    end
    

    always @(posedge Pulse1_in)
    begin
        if (status1[15] == 1'b1 && mode1[0] == 1'b1)
            if (counter1 == 16'h0001)
            begin
                stat1_1 = status1 | 16'h0002;
                
                if (mode1[1] == 1'b1)
                    cnt1_1 = init1;
                else
                begin
                    stat1_1 = stat1_1 & 16'h7FFF;
                    cnt1_1 = 16'h0000;
                end
            end
            else
            begin
                cnt1_1 = counter1 - 1'b1;
                stat1_1 = status1 | 16'h8000;
            end
    end


    always @(stat0_0,stat0_1)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && ((Read_enable && Address == 3'b000) || (Write_enable && Address[1:0] == 2'b00)))
                status0 = stat0_0;
            else
                if (mode0[0] == 0)
                    status0 = stat0_0;
                else
                    status0 = stat0_1;
        end
    end
    

    always @(stat1_0,stat1_1)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && ((Read_enable && Address == 3'b010) || (Write_enable && Address[1:0] == 2'b10)))
                status1 = stat1_0;
            else
                if (mode1[0] == 0)
                    status1 = stat1_0;
                else
                    status1 = stat1_1;
        end
    end
    

    always @(*)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && (Write_enable == 1 && Address == 4'b100))
                counter0 = init0;
            else
                if (mode0[0] == 0)
                    counter0 = cnt0_0;
                else
                    counter0 = cnt0_1;
        end
    end
    

    always @(*)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && (Write_enable == 1 && Address == 4'b110))
                counter1 = init1;
            else
                if (mode1[0] == 0)
                    counter1 = cnt1_0;
                else
                    counter1 = cnt1_1;
        end
    end
endmodule
module CTC(
    clock,reset,
    Read_enable,Write_enable,Select,Address,
    Write_data_in,Read_data_out,
    Pulse0_in,Pulse1_in,
    CTC0_output,CTC1_output
    );

    
    input clock;
    input reset;
    input Read_enable;
    input Write_enable;
    input Select;
    input[2:0]  Address;
    
    input Pulse0_in;
    input Pulse1_in;
    input[15:0] Write_data_in;
    output[15:0]    Read_data_out;
    
    output      CTC0_output;
    output      CTC1_output;
    
    
    reg     CTC0_output;
    reg     CTC1_output;
    reg[15:0]   Read_data_out;
    
    reg[15:0]   mode0,mode1;
    reg[15:0]   stat0_0,stat1_0;
    reg[15:0]   stat0_1,stat1_1;
    reg[15:0]   status0,status1;
    
    reg[15:0]   init0,init1;
    reg[15:0]   cnt0_0,cnt1_0;
    reg[15:0]   cnt0_1,cnt1_1;
    reg[15:0]   counter0,counter1;
    
    
    initial
    begin
        mode0 = 16'h0000;
        mode1 = 16'h0000;
        status0 = 16'h0000;
        status1 = 16'h0000;
        counter0 = 16'h0000;
        counter1 = 16'h0000;
    end
    

    always @(posedge clock)
    begin
        if (Select == 0 || reset == 1)
        begin
            CTC0_output = 1;
            CTC1_output = 1;
            init0 = 16'h0000;
            init1 = 16'h0000;
            cnt0_0 = 16'h0000;
            cnt1_0 = 16'h0000;
            stat0_0 = 16'h0000;
            stat1_0 = 16'h0000;
        end
        else
        begin
            if (Read_enable == 1)
            begin
                case (Address)

                    3'b000:
                    begin
                        Read_data_out = status0;
                        stat0_0 = status0 & 16'hFFFC;
                    end

                    3'b010:
                    begin
                        Read_data_out = status1;
                        stat1_0 = status1 & 16'hFFFC;
                    end

                    3'b100: Read_data_out = counter0;

                    3'b110: Read_data_out = counter1;
                    default: Read_data_out = 16'hZZZZ;
                endcase
            end
            else if (Write_enable == 1)
            begin
                case (Address)

                    3'b000:
                    begin
                        mode0 = Write_data_in;
                        stat0_0 = status0 & 16'h7FFC;
                    end

                    3'b010:
                    begin
                        mode1 = Write_data_in;
                        stat1_0 = status1 & 16'h7FFC;
                    end

                    3'b100:
                    begin
                        init0 = Write_data_in;
                        stat0_0 = status0 | 16'h8000;
                    end

                    3'b110:
                    begin
                        init1 = Write_data_in;
                        stat1_0 = status1 | 16'h8000;
                    end

                endcase
            end
        end
        

        if (status0[15] == 1'b0)
            CTC0_output = 1'b1;
        else
            if (mode0[0] == 1'b0)
            begin
                if (counter0 == 16'h0001)
                begin
                    CTC0_output = 1'b0;
                    stat0_0 = status0 | 16'h0001;
                    
                    if (mode0[1] == 1'b1)
                        cnt0_0 = init0;
                    else
                    begin
                        stat0_0 = stat0_0 & 16'h7FFF;
                        cnt0_0 = 16'h0000;
                    end
                end
                else
                begin
                    CTC0_output = 1'b1;
                    cnt0_0 = counter0 - 1'b1;
                    stat0_0 = status0 | 16'h8000;
                end
            end
        

        if (status1[15] == 1'b0)
            CTC1_output = 1'b1;
        else
            if (mode1[0] == 1'b0)
            begin
                 if (counter1 == 16'h0001)
                begin
                    CTC1_output = 1'b0;
                    stat1_0 = status1 | 16'h0001;
                    
                    if (mode1[1] == 1'b1)
                        cnt1_0 = init1;
                    else
                    begin
                        stat1_0 = stat1_0 & 16'h7FFF;
                        cnt1_0 = 16'h0000;
                    end
                end
                else
                begin
                    CTC1_output = 1'b1;
                    cnt1_0 = counter1 - 1'b1;
                    stat1_0 = status1 | 16'h8000;
                end
            end
    end
    

    always @(posedge Pulse0_in)
    begin
        if (status0[15] == 1'b1 && mode0[0] == 1'b1)
            if (counter0 == 16'h0001)
            begin
                stat0_1 = status0 | 16'h0002;
                
                if (mode0[1] == 1'b1)
                    cnt0_1 = init0;
                else
                begin
                    stat0_1 = stat0_1 & 16'h7FFF;
                    cnt0_1 = 16'h0000;
                end
            end
            else
            begin
                cnt0_1 = counter0 - 1'b1;
                stat0_1 = status0 | 16'h8000;
            end
    end
    

    always @(posedge Pulse1_in)
    begin
        if (status1[15] == 1'b1 && mode1[0] == 1'b1)
            if (counter1 == 16'h0001)
            begin
                stat1_1 = status1 | 16'h0002;
                
                if (mode1[1] == 1'b1)
                    cnt1_1 = init1;
                else
                begin
                    stat1_1 = stat1_1 & 16'h7FFF;
                    cnt1_1 = 16'h0000;
                end
            end
            else
            begin
                cnt1_1 = counter1 - 1'b1;
                stat1_1 = status1 | 16'h8000;
            end
    end


    always @(stat0_0,stat0_1)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && ((Read_enable && Address == 3'b000) || (Write_enable && Address[1:0] == 2'b00)))
                status0 = stat0_0;
            else
                if (mode0[0] == 0)
                    status0 = stat0_0;
                else
                    status0 = stat0_1;
        end
    end
    

    always @(stat1_0,stat1_1)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && ((Read_enable && Address == 3'b010) || (Write_enable && Address[1:0] == 2'b10)))
                status1 = stat1_0;
            else
                if (mode1[0] == 0)
                    status1 = stat1_0;
                else
                    status1 = stat1_1;
        end
    end
    

    always @(*)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && (Write_enable == 1 && Address == 4'b100))
                counter0 = init0;
            else
                if (mode0[0] == 0)
                    counter0 = cnt0_0;
                else
                    counter0 = cnt0_1;
        end
    end
    

    always @(*)
    begin
        if (reset == 0)
        begin
            if (Select == 1 && (Write_enable == 1 && Address == 4'b110))
                counter1 = init1;
            else
                if (mode1[0] == 0)
                    counter1 = cnt1_0;
                else
                    counter1 = cnt1_1;
        end
    end
endmodule