data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_3/fibonacci_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_3,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_3/fibonacci_TB.v\n%Error: Exiting due to 5 error(s)\n'
module fibonacci_TB;
	reg clock;
	reg reset;
	wire [15:0] fib_out;
	
	fibonacci DUT(.clock(clock), .reset(reset), 
				  .fib_out(fib_out));

	always #2 clock = ~clock;

	initial begin
		clock = 0;
		reset = 0;
		#9 reset = 1;
		
		#100 $finish;
	end

	initial begin
		$dumpfile("fibonacci_TB.vcd");
		$dumpvars(0, fibonacci_TB);
	end

endmodule
module fibonacci_TB;

	reg clock;
	reg reset;
	wire [15:0] fib_out;
	
	fibonacci DUT(.clock(clock), .reset(reset), 
				  .fib_out(fib_out));

	always #2 clock = ~clock;

	initial begin
		clock = 0;
		reset = 0;
		#9 reset = 1;
		
		#100 $finish;
	end

	initial begin
		$dumpfile("fibonacci_TB.vcd");
		$dumpvars(0, fibonacci_TB);
	end

endmodule