data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/SEGDRIVE.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/SEGDRIVE.v:63: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'refreshcounter\' generates 3 bits.\n                                                                                          : ... In instance SEGDRIVE\n                    case(refreshcounter)\n                    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/SEGDRIVE.v:94: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'refreshcounter\' generates 3 bits.\n                                                                                          : ... In instance SEGDRIVE\n        case(refreshcounter)\n        ^~~~\n%Error: Exiting due to 2 warning(s)\n'
module SEGDRIVE( 
    input [31:0] inDigit, 
    output reg [6:0] Cnode,
    output dp,
    output reg [7:0] AN,



    input nexysCLK,
    output reg divided_clk = 0
    );
    reg [3:0] singledigit = 0; 
    reg [2:0] refreshcounter = 0;

    
    localparam div_value = 25000;
    
    integer counter_value = 0;
    
    always @(posedge nexysCLK) 
    begin
        if (counter_value == div_value)
            counter_value <= 0;
        else
            counter_value <= counter_value + 1;
    end
    

    always @(posedge nexysCLK)
    begin
        if (counter_value == div_value)
            divided_clk <= ~divided_clk;
        else
            divided_clk <= divided_clk;
    end

     
    always @(posedge divided_clk)
    begin
        refreshcounter <= refreshcounter + 1;
    end
    
            
            always @(refreshcounter)
                begin              

                    case(refreshcounter)
                        4'b0000: singledigit = inDigit[3:0];
                        4'b0001: singledigit = inDigit[7:4];
                        4'b0010: singledigit = inDigit[11:8];
                        4'b0011: singledigit = inDigit[15:12];
                        4'b0100: singledigit = inDigit[19:16];
                        4'b0101: singledigit = inDigit[23:20];
                        4'b0110: singledigit = inDigit[27:24];
                        4'b0111: singledigit = inDigit[31:28];
                    endcase

           end    
    
    always @(refreshcounter )
    begin


        case(refreshcounter)
            4'b0000: AN = 8'b11111110;
            4'b0001: AN = 8'b11111101;
            4'b0010: AN = 8'b11111011;
            4'b0011: AN = 8'b11110111;
            4'b0100: AN = 8'b11101111;
            4'b0101: AN = 8'b11011111;
            4'b0110: AN = 8'b10111111;
            4'b0111: AN = 8'b01111111;
            default: AN = 8'bZZZZZZZZ; 
        endcase 
        end

    
    
    assign dp = 1'b1;
    always@(singledigit)
        begin
            case (singledigit)
                4'd0: Cnode<= 7'b0000001;
                4'd1: Cnode<= 7'b1001111;
                4'd2: Cnode<= 7'b0010010;
                4'd3: Cnode<= 7'b0000110;
                4'd4: Cnode<= 7'b1001100;
                4'd5: Cnode<= 7'b0100100;
                4'd6: Cnode<= 7'b0100000;
                4'd7: Cnode<= 7'b0001111;
                4'd8: Cnode<= 7'b0000000;
                4'd9: Cnode<= 7'b0000100;
                4'd10:Cnode<= 7'b0001000;
                4'd11:Cnode<= 7'b1100000;
                4'd12:Cnode<= 7'b0110001;
                4'd13:Cnode<= 7'b1000010;
                4'd14:Cnode<= 7'b0110000;
                4'd15:Cnode<= 7'b0111000;
                default: Cnode = 7'b0000000;
            endcase
        end
endmodule
module SEGDRIVE( 
    input [31:0] inDigit, 
    output reg [6:0] Cnode,
    output dp,
    output reg [7:0] AN,



    input nexysCLK,
    output reg divided_clk = 0
    );

    reg [3:0] singledigit = 0; 
    reg [2:0] refreshcounter = 0;

    
    localparam div_value = 25000;
    
    integer counter_value = 0;
    
    always @(posedge nexysCLK) 
    begin
        if (counter_value == div_value)
            counter_value <= 0;
        else
            counter_value <= counter_value + 1;
    end
    

    always @(posedge nexysCLK)
    begin
        if (counter_value == div_value)
            divided_clk <= ~divided_clk;
        else
            divided_clk <= divided_clk;
    end

     
    always @(posedge divided_clk)
    begin
        refreshcounter <= refreshcounter + 1;
    end
    
            
            always @(refreshcounter)
                begin              

                    case(refreshcounter)
                        4'b0000: singledigit = inDigit[3:0];
                        4'b0001: singledigit = inDigit[7:4];
                        4'b0010: singledigit = inDigit[11:8];
                        4'b0011: singledigit = inDigit[15:12];
                        4'b0100: singledigit = inDigit[19:16];
                        4'b0101: singledigit = inDigit[23:20];
                        4'b0110: singledigit = inDigit[27:24];
                        4'b0111: singledigit = inDigit[31:28];
                    endcase

           end    
    
    always @(refreshcounter )
    begin


        case(refreshcounter)
            4'b0000: AN = 8'b11111110;
            4'b0001: AN = 8'b11111101;
            4'b0010: AN = 8'b11111011;
            4'b0011: AN = 8'b11110111;
            4'b0100: AN = 8'b11101111;
            4'b0101: AN = 8'b11011111;
            4'b0110: AN = 8'b10111111;
            4'b0111: AN = 8'b01111111;
            default: AN = 8'bZZZZZZZZ; 
        endcase 
        end

    
    
    assign dp = 1'b1;
    always@(singledigit)
        begin
            case (singledigit)
                4'd0: Cnode<= 7'b0000001;
                4'd1: Cnode<= 7'b1001111;
                4'd2: Cnode<= 7'b0010010;
                4'd3: Cnode<= 7'b0000110;
                4'd4: Cnode<= 7'b1001100;
                4'd5: Cnode<= 7'b0100100;
                4'd6: Cnode<= 7'b0100000;
                4'd7: Cnode<= 7'b0001111;
                4'd8: Cnode<= 7'b0000000;
                4'd9: Cnode<= 7'b0000100;
                4'd10:Cnode<= 7'b0001000;
                4'd11:Cnode<= 7'b1100000;
                4'd12:Cnode<= 7'b0110001;
                4'd13:Cnode<= 7'b1000010;
                4'd14:Cnode<= 7'b0110000;
                4'd15:Cnode<= 7'b0111000;
                default: Cnode = 7'b0000000;
            endcase
        end
endmodule