data/full_repos/permissive/434187796/testbench/SQUARE_WAVE_GENERATOR_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/SQUARE_WAVE_GENERATOR_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n                #4000 rst = 1\'b0;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/SQUARE_WAVE_GENERATOR_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n                #4010 $stop;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/SQUARE_WAVE_GENERATOR_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        always #10 clk = ~clk;\n               ^\n%Error: data/full_repos/permissive/434187796/testbench/SQUARE_WAVE_GENERATOR_tb.v:8: Cannot find file containing module: \'SQUARE_WAVE_GENERATOR\'\n        SQUARE_WAVE_GENERATOR #(\n        ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/SQUARE_WAVE_GENERATOR\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/SQUARE_WAVE_GENERATOR.v\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/SQUARE_WAVE_GENERATOR.sv\n             SQUARE_WAVE_GENERATOR\n             SQUARE_WAVE_GENERATOR.v\n             SQUARE_WAVE_GENERATOR.sv\n             obj_dir/SQUARE_WAVE_GENERATOR\n             obj_dir/SQUARE_WAVE_GENERATOR.v\n             obj_dir/SQUARE_WAVE_GENERATOR.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SQUARE_WAVE_GENERATOR_tb;
        reg clk;
        reg rst;
        wire sw;

        SQUARE_WAVE_GENERATOR #(
                .cycle(32'd100)
        ) square_wave_generator_ (
                .clk(clk),
                .rst(rst),
                .sw(sw)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b1;

                #4000 rst = 1'b0;
                #4010 $stop;
        end

        always #10 clk = ~clk;
endmodule
module SQUARE_WAVE_GENERATOR_tb;

        reg clk;
        reg rst;
        wire sw;

        SQUARE_WAVE_GENERATOR #(
                .cycle(32'd100)
        ) square_wave_generator_ (
                .clk(clk),
                .rst(rst),
                .sw(sw)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b1;

                #4000 rst = 1'b0;
                #4010 $stop;
        end

        always #10 clk = ~clk;
endmodule