data/full_repos/permissive/43398611/memory.v
1: b"%Error: data/full_repos/permissive/43398611/memory.v:79: Cannot find file containing module: 'data_mem'\ndata_mem i_data_mem (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/data_mem\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/data_mem.v\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/data_mem.sv\n             data_mem\n             data_mem.v\n             data_mem.sv\n             obj_dir/data_mem\n             obj_dir/data_mem.v\n             obj_dir/data_mem.sv\n%Error: Exiting due to 1 error(s)\n"
module memory(
  input         clk_n,
  input         rst_n,
  input [15:0]  ex_alu_result,
  input [15:0]  ex_register2_data,
  input [2:0]   ex_reg_waddr,
  input         cu_dm_wea,
  input [1:0]   cu_branch,
  input         ex_alu_z,
  output [15:0] m_alu_result,
  output [15:0] m_dm_dout,
  output [2:0]  m_reg_waddr,
  output reg    m_branch_en
);


parameter DBR = 2'b00;
parameter BEQ = 2'b01;
parameter BNE = 2'b10;
parameter JMP = 2'b11;

assign m_alu_result = ex_alu_result;
assign m_reg_waddr  = ex_reg_waddr;



always@( posedge clk_n or negedge rst_n ) begin
  if( rst_n == 1'b0 ) begin
    m_branch_en <= 1'b0;
  end else begin
    case( cu_branch )
    DBR: begin
      m_branch_en <= 1'b0;
    end
    BEQ: begin
      if( ex_alu_z == 1'b1 ) begin
        m_branch_en <= 1'b1;
      end else begin
        m_branch_en <= 1'b0;
      end
    end
    BNE: begin
      if( ex_alu_z == 1'b1 ) begin
        m_branch_en <= 1'b0;
      end else begin
        m_branch_en <= 1'b1;
      end
    end
    JMP: begin
      m_branch_en <= 1'b1;
    end
    endcase
  end
end

data_mem i_data_mem (
  .clka(clk_n),
  .rsta(1'b0),
  .wea(cu_dm_wea),
  .addra(ex_alu_result[6:0]),
  .dina(ex_register2_data),
  .douta(m_dm_dout[15:0])
);

endmodule
module memory(
  input         clk_n,
  input         rst_n,
  input [15:0]  ex_alu_result,
  input [15:0]  ex_register2_data,
  input [2:0]   ex_reg_waddr,
  input         cu_dm_wea,
  input [1:0]   cu_branch,
  input         ex_alu_z,
  output [15:0] m_alu_result,
  output [15:0] m_dm_dout,
  output [2:0]  m_reg_waddr,
  output reg    m_branch_en
);



parameter DBR = 2'b00;
parameter BEQ = 2'b01;
parameter BNE = 2'b10;
parameter JMP = 2'b11;

assign m_alu_result = ex_alu_result;
assign m_reg_waddr  = ex_reg_waddr;



always@( posedge clk_n or negedge rst_n ) begin
  if( rst_n == 1'b0 ) begin
    m_branch_en <= 1'b0;
  end else begin
    case( cu_branch )
    DBR: begin
      m_branch_en <= 1'b0;
    end
    BEQ: begin
      if( ex_alu_z == 1'b1 ) begin
        m_branch_en <= 1'b1;
      end else begin
        m_branch_en <= 1'b0;
      end
    end
    BNE: begin
      if( ex_alu_z == 1'b1 ) begin
        m_branch_en <= 1'b0;
      end else begin
        m_branch_en <= 1'b1;
      end
    end
    JMP: begin
      m_branch_en <= 1'b1;
    end
    endcase
  end
end

data_mem i_data_mem (
  .clka(clk_n),
  .rsta(1'b0),
  .wea(cu_dm_wea),
  .addra(ex_alu_result[6:0]),
  .dina(ex_register2_data),
  .douta(m_dm_dout[15:0])
);

endmodule