data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v
1: b'%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:28: syntax error, unexpected \'@\'\n        @(negedge clock);     \n        ^\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:32: syntax error, unexpected \'@\'\n        @(negedge clock);     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n         #10     clock = ~clock;     \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:63: syntax error, unexpected \'@\'\n            @(negedge clock);     \n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:70: syntax error, unexpected \'@\'\n            @(negedge clock);  \n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:82: syntax error, unexpected \'@\'\n            @(negedge clock);     \n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile_tb.v:87: syntax error, unexpected \'@\'\n            @(negedge clock);  \n            ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module regfile_tb();

    reg            clock, ctrl_writeEn, ctrl_reset;
    reg [4:0]     ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    reg [31:0]    data_writeReg;


    wire [31:0] data_readRegA, data_readRegB;


    integer errors;
    integer index;


    regfile regfile_ut (clock, ctrl_writeEn, ctrl_reset, ctrl_writeReg,
        ctrl_readRegA, ctrl_readRegB, data_writeReg, data_readRegA, data_readRegB);


    initial
    begin
        $display($time, " << Starting the Simulation >>");
        clock = 1'b0;
        errors = 0;

        ctrl_reset = 1'b1;
        @(negedge clock);
        @(negedge clock);

        ctrl_reset = 1'b0;
        @(negedge clock);


        for(index = 0; index <= 31; index = index + 1) begin
            writeRegister(index, 32'h0000DEAD);
            checkRegister(index, 32'h0000DEAD);
        end

        if (errors == 0) begin
            $display("The simulation completed without errors");
        end
        else begin
            $display("The simulation failed with %d errors", errors);
        end

        $stop;
    end




    always
         #10     clock = ~clock;


    task writeRegister;

        input [4:0] writeReg;
        input [31:0] value;

        begin
            @(negedge clock);
            $display($time, " << Writing register %d with %h >>", writeReg, value);

            ctrl_writeEn = 1'b1;
            ctrl_writeReg = writeReg;
            data_writeReg = value;

            @(negedge clock);
            ctrl_writeEn = 1'b0;
        end
    endtask


    task checkRegister;

        input [4:0] checkReg;
        input [31:0] exp;

        begin
            @(negedge clock);

            ctrl_readRegA = checkReg;
            ctrl_readRegB = checkReg;

            @(negedge clock);

            if(data_readRegA !== exp) begin
                $display("**Error on port A: read %h but expected %h.", data_readRegA, exp);
                errors = errors + 1;
            end

            if(data_readRegB !== exp) begin
                $display("**Error on port B: read %h but expected %h.", data_readRegB, exp);
                errors = errors + 1;
            end
        end
    endtask
endmodule
module regfile_tb();


    reg            clock, ctrl_writeEn, ctrl_reset;
    reg [4:0]     ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    reg [31:0]    data_writeReg;


    wire [31:0] data_readRegA, data_readRegB;


    integer errors;
    integer index;


    regfile regfile_ut (clock, ctrl_writeEn, ctrl_reset, ctrl_writeReg,
        ctrl_readRegA, ctrl_readRegB, data_writeReg, data_readRegA, data_readRegB);


    initial
    begin
        $display($time, " << Starting the Simulation >>");
        clock = 1'b0;
        errors = 0;

        ctrl_reset = 1'b1;
        @(negedge clock);
        @(negedge clock);

        ctrl_reset = 1'b0;
        @(negedge clock);


        for(index = 0; index <= 31; index = index + 1) begin
            writeRegister(index, 32'h0000DEAD);
            checkRegister(index, 32'h0000DEAD);
        end

        if (errors == 0) begin
            $display("The simulation completed without errors");
        end
        else begin
            $display("The simulation failed with %d errors", errors);
        end

        $stop;
    end




    always
         #10     clock = ~clock;


    task writeRegister;

        input [4:0] writeReg;
        input [31:0] value;

        begin
            @(negedge clock);
            $display($time, " << Writing register %d with %h >>", writeReg, value);

            ctrl_writeEn = 1'b1;
            ctrl_writeReg = writeReg;
            data_writeReg = value;

            @(negedge clock);
            ctrl_writeEn = 1'b0;
        end
    endtask


    task checkRegister;

        input [4:0] checkReg;
        input [31:0] exp;

        begin
            @(negedge clock);

            ctrl_readRegA = checkReg;
            ctrl_readRegB = checkReg;

            @(negedge clock);

            if(data_readRegA !== exp) begin
                $display("**Error on port A: read %h but expected %h.", data_readRegA, exp);
                errors = errors + 1;
            end

            if(data_readRegB !== exp) begin
                $display("**Error on port B: read %h but expected %h.", data_readRegB, exp);
                errors = errors + 1;
            end
        end
    endtask
endmodule