data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n             #10 \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Error: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY_TB.v:29: Cannot find file containing module: \'MAJORITY\'\n    MAJORITY COMP\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/MAJORITY\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/MAJORITY.v\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/MAJORITY.sv\n             MAJORITY\n             MAJORITY.v\n             MAJORITY.sv\n             obj_dir/MAJORITY\n             obj_dir/MAJORITY.v\n             obj_dir/MAJORITY.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MAJORITY_TB(

    );
    reg x_tb,y_tb,z_tb;
    wire p_tb;
    
    MAJORITY COMP
    (
    .x(x_tb),
    .y(y_tb),
    .z(z_tb),
    .p(p_tb)
    );
    
     initial
            begin:  TST1 
               x_tb = 1'b0;
               y_tb = 1'b0;
               z_tb = 1'b0; 
             #10 
               x_tb = 1'b0;
               y_tb = 1'b1;
               z_tb = 1'b1;
             #10
               x_tb = 1'b1;
               y_tb = 1'b0;
               z_tb = 1'b0;
             #10
               x_tb = 1'b1;
               y_tb = 1'b0;
               z_tb = 1'b1; 
            #10
               x_tb = 1'b1;
               y_tb = 1'b1;
               z_tb = 1'b1; 
            #1000
            $finish; 
            end

endmodule
module MAJORITY_TB(

    );

    reg x_tb,y_tb,z_tb;
    wire p_tb;
    
    MAJORITY COMP
    (
    .x(x_tb),
    .y(y_tb),
    .z(z_tb),
    .p(p_tb)
    );
    
     initial
            begin:  TST1 
               x_tb = 1'b0;
               y_tb = 1'b0;
               z_tb = 1'b0; 
             #10 
               x_tb = 1'b0;
               y_tb = 1'b1;
               z_tb = 1'b1;
             #10
               x_tb = 1'b1;
               y_tb = 1'b0;
               z_tb = 1'b0;
             #10
               x_tb = 1'b1;
               y_tb = 1'b0;
               z_tb = 1'b1; 
            #10
               x_tb = 1'b1;
               y_tb = 1'b1;
               z_tb = 1'b1; 
            #1000
            $finish; 
            end

endmodule