data/full_repos/permissive/493019833/test/testcase/firrtl/GCD/reference/GCD.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/GCD/reference/GCD.v:154: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                 : ... In instance GCD.u_pad_10\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module GCD(
    input clk,
    input reset,
    input [15:0] io_a,
    input [15:0] io_b,
    input io_e,
    output [15:0] io_z,
    output io_v
);
    wire [15:0] _x__q;
    wire [15:0] _x__d;
    DFF_POSCLK #(.width(16)) x (
        .q(_x__q),
        .d(_x__d),
        .clk(clk)
    );
    wire [15:0] _y__q;
    wire [15:0] _y__d;
    DFF_POSCLK #(.width(16)) y (
        .q(_y__q),
        .d(_y__d),
        .clk(clk)
    );
    wire T_7;
    GT_UNSIGNED #(.width(16)) u_gt_1 (
        .y(T_7),
        .a(_x__q),
        .b(_y__q)
    );
    wire [16:0] T_8;
    SUB_UNSIGNED #(.width(16)) u_sub_2 (
        .y(T_8),
        .a(_x__q),
        .b(_y__q)
    );
    wire [15:0] T_9;
    TAIL #(.width(17), .n(1)) tail_3 (
        .y(T_9),
        .in(T_8)
    );
    wire T_10;
    GT_UNSIGNED #(.width(16)) u_gt_4 (
        .y(T_10),
        .a(_x__q),
        .b(_y__q)
    );
    wire T_12;
    EQ_UNSIGNED #(.width(1)) u_eq_5 (
        .y(T_12),
        .a(T_10),
        .b(1'h0)
    );
    wire [16:0] T_13;
    SUB_UNSIGNED #(.width(16)) u_sub_6 (
        .y(T_13),
        .a(_y__q),
        .b(_x__q)
    );
    wire [15:0] T_14;
    TAIL #(.width(17), .n(1)) tail_7 (
        .y(T_14),
        .in(T_13)
    );
    wire [15:0] _node_0;
    MUX_UNSIGNED #(.width(16)) u_mux_8 (
        .y(_node_0),
        .sel(T_7),
        .a(T_9),
        .b(_x__q)
    );
    wire [15:0] _node_1;
    MUX_UNSIGNED #(.width(16)) u_mux_9 (
        .y(_node_1),
        .sel(T_12),
        .a(T_14),
        .b(_y__q)
    );
    wire T_16;
    wire [15:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_10 (
        .y(_WTEMP_0),
        .in(1'h0)
    );
    EQ_UNSIGNED #(.width(16)) u_eq_11 (
        .y(T_16),
        .a(_y__q),
        .b(_WTEMP_0)
    );
    assign io_v = T_16;
    assign io_z = _x__q;
    MUX_UNSIGNED #(.width(16)) u_mux_12 (
        .y(_x__d),
        .sel(io_e),
        .a(io_a),
        .b(_node_0)
    );
    MUX_UNSIGNED #(.width(16)) u_mux_13 (
        .y(_y__d),
        .sel(io_e),
        .a(io_b),
        .b(_node_1)
    );
endmodule
module GCD(
    input clk,
    input reset,
    input [15:0] io_a,
    input [15:0] io_b,
    input io_e,
    output [15:0] io_z,
    output io_v
);

    wire [15:0] _x__q;
    wire [15:0] _x__d;
    DFF_POSCLK #(.width(16)) x (
        .q(_x__q),
        .d(_x__d),
        .clk(clk)
    );
    wire [15:0] _y__q;
    wire [15:0] _y__d;
    DFF_POSCLK #(.width(16)) y (
        .q(_y__q),
        .d(_y__d),
        .clk(clk)
    );
    wire T_7;
    GT_UNSIGNED #(.width(16)) u_gt_1 (
        .y(T_7),
        .a(_x__q),
        .b(_y__q)
    );
    wire [16:0] T_8;
    SUB_UNSIGNED #(.width(16)) u_sub_2 (
        .y(T_8),
        .a(_x__q),
        .b(_y__q)
    );
    wire [15:0] T_9;
    TAIL #(.width(17), .n(1)) tail_3 (
        .y(T_9),
        .in(T_8)
    );
    wire T_10;
    GT_UNSIGNED #(.width(16)) u_gt_4 (
        .y(T_10),
        .a(_x__q),
        .b(_y__q)
    );
    wire T_12;
    EQ_UNSIGNED #(.width(1)) u_eq_5 (
        .y(T_12),
        .a(T_10),
        .b(1'h0)
    );
    wire [16:0] T_13;
    SUB_UNSIGNED #(.width(16)) u_sub_6 (
        .y(T_13),
        .a(_y__q),
        .b(_x__q)
    );
    wire [15:0] T_14;
    TAIL #(.width(17), .n(1)) tail_7 (
        .y(T_14),
        .in(T_13)
    );
    wire [15:0] _node_0;
    MUX_UNSIGNED #(.width(16)) u_mux_8 (
        .y(_node_0),
        .sel(T_7),
        .a(T_9),
        .b(_x__q)
    );
    wire [15:0] _node_1;
    MUX_UNSIGNED #(.width(16)) u_mux_9 (
        .y(_node_1),
        .sel(T_12),
        .a(T_14),
        .b(_y__q)
    );
    wire T_16;
    wire [15:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_10 (
        .y(_WTEMP_0),
        .in(1'h0)
    );
    EQ_UNSIGNED #(.width(16)) u_eq_11 (
        .y(T_16),
        .a(_y__q),
        .b(_WTEMP_0)
    );
    assign io_v = T_16;
    assign io_z = _x__q;
    MUX_UNSIGNED #(.width(16)) u_mux_12 (
        .y(_x__d),
        .sel(io_e),
        .a(io_a),
        .b(_node_0)
    );
    MUX_UNSIGNED #(.width(16)) u_mux_13 (
        .y(_y__d),
        .sel(io_e),
        .a(io_b),
        .b(_node_1)
    );
endmodule