data/full_repos/permissive/522095295/clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522095295/clock.v:12: Unsupported: Ignoring delay on this delayed statement.\n         #1 clk = 0;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522095295/clock.v:13: Unsupported: Ignoring delay on this delayed statement.\n         #1 clk = 1;\n         ^\n%Warning-INFINITELOOP: data/full_repos/permissive/522095295/clock.v:11: Infinite loop (condition always true)\n                                                                      : ... In instance clock\n      forever begin\n      ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock
(
   output clk_o
);
   reg clk;
   initial begin
     clk <= 0;
   end
  
   initial begin
      forever begin
         #1 clk = 0;
         #1 clk = 1;
      end
   end 

   assign clk_o = clk;
endmodule
module clock
(
   output clk_o
);

   reg clk;
   initial begin
     clk <= 0;
   end
  
   initial begin
      forever begin
         #1 clk = 0;
         #1 clk = 1;
      end
   end 

   assign clk_o = clk;
endmodule