data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/blink_clock_divider.v
1: b"%Error: data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/blink_clock_divider.v:15: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/blink_clock_divider.v:23: syntax error, unexpected IDENTIFIER\nclock_divider divider(\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top(
    input  CLK,
    output LEDG_N,
	output LEDR_N,
);





wire slow_clk;

clock_divider divider(
    .clk(CLK),
    .div(24'd6000000),
    .slow_clk(slow_clk)
);




assign LEDG_N = slow_clk;
assign LEDR_N = ~slow_clk;


endmodule
module top(
    input  CLK,
    output LEDG_N,
	output LEDR_N,
);






wire slow_clk;

clock_divider divider(
    .clk(CLK),
    .div(24'd6000000),
    .slow_clk(slow_clk)
);




assign LEDG_N = slow_clk;
assign LEDR_N = ~slow_clk;


endmodule