data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/SubBytes.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/SubBytes.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire[0:7] s, x;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module SubBytes(
x,
z);

  input [127:0] x;
  output [127:0] z;

  generate
    genvar i;
    for (i = 0; i < 16; i = i + 1) begin:SBOX
	  sbox sbox(z[8*(i+1)-1:8*i], x[8*(i+1)-1:8*i]);
    end
  endgenerate


endmodule
module SubBytes(
x,
z);


  input [127:0] x;
  output [127:0] z;

  generate
    genvar i;
    for (i = 0; i < 16; i = i + 1) begin:SBOX
	  sbox sbox(z[8*(i+1)-1:8*i], x[8*(i+1)-1:8*i]);
    end
  endgenerate


endmodule