data/full_repos/permissive/481069643/Day02/ALUwithReg.v
1: b"%Error: data/full_repos/permissive/481069643/Day02/ALUwithReg.v:27: Cannot find file containing module: 'ALU'\nALU AL0(temp_a,temp_b,temp_fun,w_alu_value,out_carry);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/481069643/Day02,data/full_repos/permissive/481069643/ALU\n             data/full_repos/permissive/481069643/Day02,data/full_repos/permissive/481069643/ALU.v\n             data/full_repos/permissive/481069643/Day02,data/full_repos/permissive/481069643/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s)\n"
module ALUwithReg(clk,en,rst,in_a,in_b,fun,out_alu,out_carry);

input clk,en,rst;
input [3:0]in_a;
input [3:0]in_b;
input [3:0]fun;
output out_carry;
output reg [3:0] out_alu;

reg [3:0]temp_a,temp_b,temp_fun;
wire [3:0]w_alu_value;
reg [3:0]current_state,next_state;

ALU AL0(temp_a,temp_b,temp_fun,w_alu_value,out_carry);






always @(posedge clk)
begin
 case (current_state)
 0: begin
        if(en)
            next_state = 1;
        else
            next_state = current_state;
    end
1: begin
        temp_a = in_a;
        temp_b = in_b;
        temp_fun = fun;
        next_state = 2;
    end 
2: begin
    out_alu = w_alu_value;
    next_state = 0;
    end 
default: next_state = 0;
endcase
current_state = next_state;

end 
endmodule
module ALUwithReg(clk,en,rst,in_a,in_b,fun,out_alu,out_carry);


input clk,en,rst;
input [3:0]in_a;
input [3:0]in_b;
input [3:0]fun;
output out_carry;
output reg [3:0] out_alu;

reg [3:0]temp_a,temp_b,temp_fun;
wire [3:0]w_alu_value;
reg [3:0]current_state,next_state;

ALU AL0(temp_a,temp_b,temp_fun,w_alu_value,out_carry);






always @(posedge clk)
begin
 case (current_state)
 0: begin
        if(en)
            next_state = 1;
        else
            next_state = current_state;
    end
1: begin
        temp_a = in_a;
        temp_b = in_b;
        temp_fun = fun;
        next_state = 2;
    end 
2: begin
    out_alu = w_alu_value;
    next_state = 0;
    end 
default: next_state = 0;
endcase
current_state = next_state;

end 
endmodule