data/full_repos/permissive/528252229/mycpu_top.v
1: b'%Error: data/full_repos/permissive/528252229/mycpu_top.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:8: syntax error, unexpected int, expecting IDENTIFIER or \'[\' or do or final\n input [5:0]       int,     \n                   ^~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:12: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]            inst_sram_addr,  \n             ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]             inst_sram_rdata, \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:36: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]  pc_branch_target_address;    \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]  pc_branch_target_address;    \n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:39: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]  pc_pc;                          \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]  pc_pc;                          \n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:40: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]    pc_three;                    \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]    pc_three;                    \n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:44: Define or directive not defined: \'`InstAddrBus\'\n wire [`InstAddrBus]      if_pc;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`InstAddrBus]      if_pc;\n                   ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:45: Define or directive not defined: \'`InstBus\'\n wire [`InstBus]          if_inst;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`InstBus]          if_inst;\n               ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:50: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]  id_pc_i;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]  id_pc_i;\n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:51: Define or directive not defined: \'`InstBus\'\n wire[`InstBus]       id_inst_i;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus]       id_inst_i;\n              ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:52: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]           id_reg1_data_i;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]           id_reg1_data_i;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:53: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]           id_reg2_data_i;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]           id_reg2_data_i;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:56: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus]       id_reg1_addr_o;  \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus]       id_reg1_addr_o;  \n                 ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:57: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus]   id_reg2_addr_o;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus]   id_reg2_addr_o;\n                 ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:59: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus]         id_aluop_o;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus]         id_aluop_o;\n               ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:60: Define or directive not defined: \'`AluSelBus\'\n wire[`AluSelBus]        id_alusel_o;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluSelBus]        id_alusel_o;\n                ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:61: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]           id_reg1_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]           id_reg1_o;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:62: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]           id_reg2_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]           id_reg2_o;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:63: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus]       id_wd_o;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus]       id_wd_o;\n                 ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:64: Define or directive not defined: \'`WriteBus\'\n wire[`WriteBus]         id_wreg_o;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`WriteBus]         id_wreg_o;\n               ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:65: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]      id_return_addr_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]      id_return_addr_o;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:68: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]    id_branch_target_address_o;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]    id_branch_target_address_o;\n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:70: Define or directive not defined: \'`RegBus\'\n wire[`RegBus]     id_inst_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus]     id_inst_o;\n             ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:71: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus]    id_pc_o;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:71: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus]    id_pc_o;\n                  ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:75: Define or directive not defined: \'`WriteBus\'\n wire[`WriteBus]     regfile_we;       \n      ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`WriteBus]     regfile_we;       \n               ^\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:76: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus]  regfile_waddr;    \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mycpu_top.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus]  regfile_waddr;    \n                 ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mycpu_top(

	input wire							clk,
	input wire							resetn,
	
	input [5:0]							int,

	output 								inst_sram_en,		
	output [3:0]						inst_sram_wen,		
	output wire[`RegBus]          		inst_sram_addr,		
	output [31:0]						inst_sram_wdata,	
	input wire[`RegBus]           		inst_sram_rdata,	


	output 								data_sram_en,		
	output [3:0]						data_sram_wen,
	output [31:0]						data_sram_addr, 	
	output [31:0]						data_sram_wdata,	
	input  [31:0]						data_sram_rdata,	

	output [31:0]						debug_wb_pc,		
	output [3:0]						debug_wb_rf_wen,	
	output [4:0]						debug_wb_rf_wnum,	
	output [31:0]						debug_wb_rf_wdata	

	
);
	
	wire rst = resetn;



	wire 					pc_branch_flag;
	wire[`InstAddrBus]		pc_branch_target_address;
	wire					pc_stall;

	wire[`InstAddrBus]		pc_pc;
	wire[`InstAddrBus]   	pc_three;
	wire                  	pc_ce;


	wire [`InstAddrBus]      if_pc;
	wire [`InstBus]          if_inst;
	wire                     if_id_stall;
	wire                     if_id_stall_aluop;


	wire[`InstAddrBus]		id_pc_i;
	wire[`InstBus]      	id_inst_i;
	wire[`RegBus]           id_reg1_data_i;
	wire[`RegBus]           id_reg2_data_i;
	wire                    id_reg1_read_o;
	wire                    id_reg2_read_o;
	wire[`RegAddrBus]       id_reg1_addr_o;  
	wire[`RegAddrBus] 		id_reg2_addr_o;
	
	wire[`AluOpBus]         id_aluop_o;
	wire[`AluSelBus]        id_alusel_o;
	wire[`RegBus]           id_reg1_o;
	wire[`RegBus]           id_reg2_o;
	wire[`RegAddrBus]       id_wd_o;
	wire[`WriteBus]         id_wreg_o;
	wire[`RegBus] 		  	id_return_addr_o;

	wire                    id_branch_flag_o;
	wire[`InstAddrBus]	  	id_branch_target_address_o;

	wire[`RegBus]		  	id_inst_o;
	wire[`InstAddrBus]	  	id_pc_o;
	wire 			      	id_stallreq;


	wire[`WriteBus]		  	regfile_we;       
	wire[`RegAddrBus]		regfile_waddr;    
	wire[`RegBus]			regfile_wdata;   
	
	wire					regfile_re1;      
	wire[`RegAddrBus]		regfile_raddr1;   
	wire[`RegBus]           regfile_rdata1;   
	
	
	wire					regfile_re2;
	wire[`RegAddrBus]		regfile_raddr2;
	wire[`RegBus]           regfile_rdata2;


	wire[`AluOpBus]         	ex_aluop_i;
	wire[`AluSelBus]        	ex_alusel_i;
	wire[`RegBus]           	ex_reg1_i;
	wire[`RegBus]           	ex_reg2_i;
	wire[`RegAddrBus]       	ex_wd_i;
	wire[`WriteBus]           	ex_wreg_i;
	wire[`RegBus] 				ex_return_addr_i; 
	wire[`RegBus]				ex_inst_i;
	wire[`InstAddrBus]			ex_pc_i;

	wire[`RegAddrBus]        	ex_wd_o;
	wire[`WriteBus]          	ex_wreg_o;
	wire[`RegBus]			    ex_wdata_o;
	
	wire[`AluOpBus]				ex_aluop_o;
	wire[`RegBus]				ex_mem_addr_o;
	wire[`RegBus]				ex_reg2_o;
	wire[`InstAddrBus]			ex_pc_o;
	wire 						ex_stallreq;


	wire[`RegAddrBus]       	mem_wd_i;
	wire[`WriteBus]             mem_wreg_i;
	wire[`RegBus]				mem_wdata_i;
	
	wire[`AluOpBus]				mem_aluop_i;
	wire[`RegBus]				mem_addr_i;
	wire[`RegBus]				mem_reg2_i;
	wire[`InstAddrBus]			mem_pc_i;

	wire[`RegAddrBus]     		mem_wd_o;
    wire[`WriteBus]             mem_wreg_o;
	wire[`RegBus]				mem_wdata_o;

	wire[`RegBus]				mem_data_addr_o;
	
	wire[`InstAddrBus]			mem_pc_o;
	wire[`AluOpBus]				mem_aluop_o;
	wire 						mem_stallreq;


    wire[`StopBus]              stall;


	
	assign pc_branch_flag = id_branch_flag_o;
    assign pc_branch_target_address = id_branch_target_address_o;	
    
	pc_reg pc_reg0(
		.clk(clk),
		.rst(rst),
			
		.branch_flag_i(pc_branch_flag),
		.branch_target_address_i(pc_branch_target_address),
		.stall(stall),

		.pc(pc_pc),
		.pc_three(pc_three),
		.ce(inst_sram_en)
	);

	assign inst_sram_addr = pc_pc;
	assign if_pc = pc_pc;
	assign if_inst = inst_sram_rdata;


	if_id if_id0(
		.clk(clk),
		.rst(rst),

		.if_pc(if_pc),
		.if_inst(if_inst),
		.stall(stall),


		.id_pc(id_pc_i),
		.id_inst(id_inst_i)      	
	);
    
    assign id_reg1_data_i = regfile_rdata1;
    assign id_reg2_data_i = regfile_rdata2;


	id id0(
		.rst(rst),
		.pc_i(id_pc_i),
		.inst_i(id_inst_i),


		.ex_wreg_i(ex_wreg_o),
		.ex_wdata_i(ex_wdata_o),
		.ex_wd_i(ex_wd_o),
		.ex_aluop_i(ex_aluop_o),


		.mem_wreg_i(mem_wreg_o),
		.mem_wdata_i(mem_wdata_o),
		.mem_wd_i(mem_wd_o),

		.reg1_data_i(id_reg1_data_i),
		.reg2_data_i(id_reg2_data_i),

		.reg1_read_o(id_reg1_read_o),
		.reg2_read_o(id_reg2_read_o), 	  
		.reg1_addr_o(id_reg1_addr_o),
		.reg2_addr_o(id_reg2_addr_o), 
	  
		.aluop_o(id_aluop_o),
		.alusel_o(id_alusel_o),
		.reg1_o(id_reg1_o),
		.reg2_o(id_reg2_o),
		.wd_o(id_wd_o),
		.wreg_o(id_wreg_o),
		.return_addr_o(id_return_addr_o),

		.branch_flag_o(id_branch_flag_o),			
		.branch_target_address_o(id_branch_target_address_o),		
	
		.inst_o(id_inst_o),
		.pc_o(id_pc_o),
		.stallreq(id_stallreq)
	);

	assign regfile_re1 = id_reg1_read_o;
	assign regfile_re2 = id_reg2_read_o;
	assign regfile_raddr1 = id_reg1_addr_o;
	assign regfile_raddr2 = id_reg2_addr_o;


	regfile regfile1(
		.clk (clk),
		.rst (rst),

		.we	(regfile_we),
		.waddr (regfile_waddr),
		.wdata (regfile_wdata),



		.re1 (regfile_re1),
		.raddr1 (regfile_raddr1),
		.rdata1 (regfile_rdata1),

		.re2 (regfile_re2),
		.raddr2 (regfile_raddr2),
		.rdata2 (regfile_rdata2)

	);


	id_ex id_ex0(
		.clk(clk),
		.rst(rst),
		
		.id_aluop(id_aluop_o),
		.id_alusel(id_alusel_o),
		.id_reg1(id_reg1_o),
		.id_reg2(id_reg2_o),
		.id_wd(id_wd_o),
		.id_wreg(id_wreg_o),
		.id_return_addr(id_return_addr_o),
		.id_inst(id_inst_o),
		.id_pc(id_pc_o),
		.stall(stall),
	
		.ex_aluop(ex_aluop_i),
		.ex_alusel(ex_alusel_i),
		.ex_reg1(ex_reg1_i),
		.ex_reg2(ex_reg2_i),
		.ex_wd(ex_wd_i),
		.ex_wreg(ex_wreg_i),
		.ex_return_addr(ex_return_addr_i),
		.ex_inst(ex_inst_i),
		.ex_pc(ex_pc_i)
	);	


	ex ex0(
		.rst(rst),
	
		.aluop_i(ex_aluop_i),
		.alusel_i(ex_alusel_i),
		.reg1_i(ex_reg1_i),
		.reg2_i(ex_reg2_i),
		.wd_i(ex_wd_i),
		.wreg_i(ex_wreg_i),
		.return_addr_i(ex_return_addr_i),
		.inst_i(ex_inst_i),
		.pc_i(ex_pc_i),
	  
		.wd_o(ex_wd_o),
		.wreg_o(ex_wreg_o),
		.wdata_o(ex_wdata_o),

		.aluop_o(ex_aluop_o),
		.mem_addr_o(ex_mem_addr_o),
		.reg2_o(ex_reg2_o),
		.pc_o(ex_pc_o),
		.stallreq(ex_stallreq)
	);


	ex_mem ex_mem0(
		.clk(clk),
		.rst(rst),
	  
		.ex_wd(ex_wd_o),
		.ex_wreg(ex_wreg_o),
		.ex_wdata(ex_wdata_o),
		.ex_aluop(ex_aluop_o),
		.ex_mem_addr(ex_mem_addr_o),
		.ex_reg2(ex_reg2_o),
		.ex_pc(ex_pc_o),
		.stall(stall),

		.mem_wd(mem_wd_i),
		.mem_wreg(mem_wreg_i),
		.mem_wdata(mem_wdata_i),
		.mem_aluop(mem_aluop_i),
		.mem_mem_addr(mem_addr_i),
		.mem_reg2(mem_reg2_i),
		.mem_pc(mem_pc_i)				       	
	);


	assign data_sram_addr = {3'b0,mem_data_addr_o[28:0]};

	mem mem0(
		.rst(rst),
	
		.wd_i(mem_wd_i),
		.wreg_i(mem_wreg_i),
		.wdata_i(mem_wdata_i),
		.aluop_i(mem_aluop_i),
		.mem_addr_i(mem_addr_i),
		.reg2_i(mem_reg2_i),
		.pc_i(mem_pc_i),

		.mem_data_i(data_sram_rdata),

		.wd_o(mem_wd_o),
		.wreg_o(mem_wreg_o),
		.wdata_o(mem_wdata_o),

		.mem_addr_o(mem_data_addr_o),
		.mem_we_o(data_sram_wen),
		.mem_data_o(data_sram_wdata),
		.mem_ce_o(data_sram_en),
		.aluop_o(mem_aluop_o),
		.pc_o(mem_pc_o),
		.stallreq(mem_stallreq)
	);


	wire[`RegAddrBus]      		wb_wd_i;
	wire[`WriteBus]          	wb_wreg_i;
	wire[`RegBus]				wb_wdata_i;
	wire[`InstAddrBus]			wb_pc_i;
	wire[`AluOpBus]				wb_aluop_i;  

	mem_wb mem_wb0(
		.clk(clk),
		.rst(rst),

		.mem_wd(mem_wd_o),
		.mem_wreg(mem_wreg_o),
		.mem_wdata(mem_wdata_i),
		.mem_pc(mem_pc_o),
		.mem_aluop(mem_aluop_o),
		.stall(stall),
	
		.wb_wd(wb_wd_i),
		.wb_wreg(wb_wreg_i),
		.wb_wdata(wb_wdata_i),
		.wb_pc(wb_pc_i),
		.wb_aluop(wb_aluop_i)
									       	
	);


	assign regfile_we 		= wb_wreg_i;
	assign regfile_waddr 	= wb_wd_i;

    

    ctrl ctrl0(
        .rst(rst),
        .stallreq_from_id(id_stallreq),
        .stallreq_from_ex(ex_stallreq),
        .stallreq_from_mem(mem_stallreq),

        .stall(stall)
    );
    

	assign debug_wb_pc 		= wb_pc_i;
	assign debug_wb_rf_wen 	= 4'b1111;
	assign debug_wb_rf_wnum = wb_wd_i;

	assign debug_wb_rf_wdata= regfile_wdata;
    
    assign regfile_wdata = ((wb_aluop_i == `ALU_OP_LW) || (wb_aluop_i == `ALU_OP_LH) || (wb_aluop_i == `ALU_OP_LB) || (wb_aluop_i == `ALU_OP_NOP)) ? data_sram_rdata : wb_wdata_i;
    
endmodule
module mycpu_top(

	input wire							clk,
	input wire							resetn,
	
	input [5:0]							int,

	output 								inst_sram_en,		
	output [3:0]						inst_sram_wen,		
	output wire[`RegBus]          		inst_sram_addr,		
	output [31:0]						inst_sram_wdata,	
	input wire[`RegBus]           		inst_sram_rdata,	


	output 								data_sram_en,		
	output [3:0]						data_sram_wen,
	output [31:0]						data_sram_addr, 	
	output [31:0]						data_sram_wdata,	
	input  [31:0]						data_sram_rdata,	

	output [31:0]						debug_wb_pc,		
	output [3:0]						debug_wb_rf_wen,	
	output [4:0]						debug_wb_rf_wnum,	
	output [31:0]						debug_wb_rf_wdata	

	
);

	
	wire rst = resetn;



	wire 					pc_branch_flag;
	wire[`InstAddrBus]		pc_branch_target_address;
	wire					pc_stall;

	wire[`InstAddrBus]		pc_pc;
	wire[`InstAddrBus]   	pc_three;
	wire                  	pc_ce;


	wire [`InstAddrBus]      if_pc;
	wire [`InstBus]          if_inst;
	wire                     if_id_stall;
	wire                     if_id_stall_aluop;


	wire[`InstAddrBus]		id_pc_i;
	wire[`InstBus]      	id_inst_i;
	wire[`RegBus]           id_reg1_data_i;
	wire[`RegBus]           id_reg2_data_i;
	wire                    id_reg1_read_o;
	wire                    id_reg2_read_o;
	wire[`RegAddrBus]       id_reg1_addr_o;  
	wire[`RegAddrBus] 		id_reg2_addr_o;
	
	wire[`AluOpBus]         id_aluop_o;
	wire[`AluSelBus]        id_alusel_o;
	wire[`RegBus]           id_reg1_o;
	wire[`RegBus]           id_reg2_o;
	wire[`RegAddrBus]       id_wd_o;
	wire[`WriteBus]         id_wreg_o;
	wire[`RegBus] 		  	id_return_addr_o;

	wire                    id_branch_flag_o;
	wire[`InstAddrBus]	  	id_branch_target_address_o;

	wire[`RegBus]		  	id_inst_o;
	wire[`InstAddrBus]	  	id_pc_o;
	wire 			      	id_stallreq;


	wire[`WriteBus]		  	regfile_we;       
	wire[`RegAddrBus]		regfile_waddr;    
	wire[`RegBus]			regfile_wdata;   
	
	wire					regfile_re1;      
	wire[`RegAddrBus]		regfile_raddr1;   
	wire[`RegBus]           regfile_rdata1;   
	
	
	wire					regfile_re2;
	wire[`RegAddrBus]		regfile_raddr2;
	wire[`RegBus]           regfile_rdata2;


	wire[`AluOpBus]         	ex_aluop_i;
	wire[`AluSelBus]        	ex_alusel_i;
	wire[`RegBus]           	ex_reg1_i;
	wire[`RegBus]           	ex_reg2_i;
	wire[`RegAddrBus]       	ex_wd_i;
	wire[`WriteBus]           	ex_wreg_i;
	wire[`RegBus] 				ex_return_addr_i; 
	wire[`RegBus]				ex_inst_i;
	wire[`InstAddrBus]			ex_pc_i;

	wire[`RegAddrBus]        	ex_wd_o;
	wire[`WriteBus]          	ex_wreg_o;
	wire[`RegBus]			    ex_wdata_o;
	
	wire[`AluOpBus]				ex_aluop_o;
	wire[`RegBus]				ex_mem_addr_o;
	wire[`RegBus]				ex_reg2_o;
	wire[`InstAddrBus]			ex_pc_o;
	wire 						ex_stallreq;


	wire[`RegAddrBus]       	mem_wd_i;
	wire[`WriteBus]             mem_wreg_i;
	wire[`RegBus]				mem_wdata_i;
	
	wire[`AluOpBus]				mem_aluop_i;
	wire[`RegBus]				mem_addr_i;
	wire[`RegBus]				mem_reg2_i;
	wire[`InstAddrBus]			mem_pc_i;

	wire[`RegAddrBus]     		mem_wd_o;
    wire[`WriteBus]             mem_wreg_o;
	wire[`RegBus]				mem_wdata_o;

	wire[`RegBus]				mem_data_addr_o;
	
	wire[`InstAddrBus]			mem_pc_o;
	wire[`AluOpBus]				mem_aluop_o;
	wire 						mem_stallreq;


    wire[`StopBus]              stall;


	
	assign pc_branch_flag = id_branch_flag_o;
    assign pc_branch_target_address = id_branch_target_address_o;	
    
	pc_reg pc_reg0(
		.clk(clk),
		.rst(rst),
			
		.branch_flag_i(pc_branch_flag),
		.branch_target_address_i(pc_branch_target_address),
		.stall(stall),

		.pc(pc_pc),
		.pc_three(pc_three),
		.ce(inst_sram_en)
	);

	assign inst_sram_addr = pc_pc;
	assign if_pc = pc_pc;
	assign if_inst = inst_sram_rdata;


	if_id if_id0(
		.clk(clk),
		.rst(rst),

		.if_pc(if_pc),
		.if_inst(if_inst),
		.stall(stall),


		.id_pc(id_pc_i),
		.id_inst(id_inst_i)      	
	);
    
    assign id_reg1_data_i = regfile_rdata1;
    assign id_reg2_data_i = regfile_rdata2;


	id id0(
		.rst(rst),
		.pc_i(id_pc_i),
		.inst_i(id_inst_i),


		.ex_wreg_i(ex_wreg_o),
		.ex_wdata_i(ex_wdata_o),
		.ex_wd_i(ex_wd_o),
		.ex_aluop_i(ex_aluop_o),


		.mem_wreg_i(mem_wreg_o),
		.mem_wdata_i(mem_wdata_o),
		.mem_wd_i(mem_wd_o),

		.reg1_data_i(id_reg1_data_i),
		.reg2_data_i(id_reg2_data_i),

		.reg1_read_o(id_reg1_read_o),
		.reg2_read_o(id_reg2_read_o), 	  
		.reg1_addr_o(id_reg1_addr_o),
		.reg2_addr_o(id_reg2_addr_o), 
	  
		.aluop_o(id_aluop_o),
		.alusel_o(id_alusel_o),
		.reg1_o(id_reg1_o),
		.reg2_o(id_reg2_o),
		.wd_o(id_wd_o),
		.wreg_o(id_wreg_o),
		.return_addr_o(id_return_addr_o),

		.branch_flag_o(id_branch_flag_o),			
		.branch_target_address_o(id_branch_target_address_o),		
	
		.inst_o(id_inst_o),
		.pc_o(id_pc_o),
		.stallreq(id_stallreq)
	);

	assign regfile_re1 = id_reg1_read_o;
	assign regfile_re2 = id_reg2_read_o;
	assign regfile_raddr1 = id_reg1_addr_o;
	assign regfile_raddr2 = id_reg2_addr_o;


	regfile regfile1(
		.clk (clk),
		.rst (rst),

		.we	(regfile_we),
		.waddr (regfile_waddr),
		.wdata (regfile_wdata),



		.re1 (regfile_re1),
		.raddr1 (regfile_raddr1),
		.rdata1 (regfile_rdata1),

		.re2 (regfile_re2),
		.raddr2 (regfile_raddr2),
		.rdata2 (regfile_rdata2)

	);


	id_ex id_ex0(
		.clk(clk),
		.rst(rst),
		
		.id_aluop(id_aluop_o),
		.id_alusel(id_alusel_o),
		.id_reg1(id_reg1_o),
		.id_reg2(id_reg2_o),
		.id_wd(id_wd_o),
		.id_wreg(id_wreg_o),
		.id_return_addr(id_return_addr_o),
		.id_inst(id_inst_o),
		.id_pc(id_pc_o),
		.stall(stall),
	
		.ex_aluop(ex_aluop_i),
		.ex_alusel(ex_alusel_i),
		.ex_reg1(ex_reg1_i),
		.ex_reg2(ex_reg2_i),
		.ex_wd(ex_wd_i),
		.ex_wreg(ex_wreg_i),
		.ex_return_addr(ex_return_addr_i),
		.ex_inst(ex_inst_i),
		.ex_pc(ex_pc_i)
	);	


	ex ex0(
		.rst(rst),
	
		.aluop_i(ex_aluop_i),
		.alusel_i(ex_alusel_i),
		.reg1_i(ex_reg1_i),
		.reg2_i(ex_reg2_i),
		.wd_i(ex_wd_i),
		.wreg_i(ex_wreg_i),
		.return_addr_i(ex_return_addr_i),
		.inst_i(ex_inst_i),
		.pc_i(ex_pc_i),
	  
		.wd_o(ex_wd_o),
		.wreg_o(ex_wreg_o),
		.wdata_o(ex_wdata_o),

		.aluop_o(ex_aluop_o),
		.mem_addr_o(ex_mem_addr_o),
		.reg2_o(ex_reg2_o),
		.pc_o(ex_pc_o),
		.stallreq(ex_stallreq)
	);


	ex_mem ex_mem0(
		.clk(clk),
		.rst(rst),
	  
		.ex_wd(ex_wd_o),
		.ex_wreg(ex_wreg_o),
		.ex_wdata(ex_wdata_o),
		.ex_aluop(ex_aluop_o),
		.ex_mem_addr(ex_mem_addr_o),
		.ex_reg2(ex_reg2_o),
		.ex_pc(ex_pc_o),
		.stall(stall),

		.mem_wd(mem_wd_i),
		.mem_wreg(mem_wreg_i),
		.mem_wdata(mem_wdata_i),
		.mem_aluop(mem_aluop_i),
		.mem_mem_addr(mem_addr_i),
		.mem_reg2(mem_reg2_i),
		.mem_pc(mem_pc_i)				       	
	);


	assign data_sram_addr = {3'b0,mem_data_addr_o[28:0]};

	mem mem0(
		.rst(rst),
	
		.wd_i(mem_wd_i),
		.wreg_i(mem_wreg_i),
		.wdata_i(mem_wdata_i),
		.aluop_i(mem_aluop_i),
		.mem_addr_i(mem_addr_i),
		.reg2_i(mem_reg2_i),
		.pc_i(mem_pc_i),

		.mem_data_i(data_sram_rdata),

		.wd_o(mem_wd_o),
		.wreg_o(mem_wreg_o),
		.wdata_o(mem_wdata_o),

		.mem_addr_o(mem_data_addr_o),
		.mem_we_o(data_sram_wen),
		.mem_data_o(data_sram_wdata),
		.mem_ce_o(data_sram_en),
		.aluop_o(mem_aluop_o),
		.pc_o(mem_pc_o),
		.stallreq(mem_stallreq)
	);


	wire[`RegAddrBus]      		wb_wd_i;
	wire[`WriteBus]          	wb_wreg_i;
	wire[`RegBus]				wb_wdata_i;
	wire[`InstAddrBus]			wb_pc_i;
	wire[`AluOpBus]				wb_aluop_i;  

	mem_wb mem_wb0(
		.clk(clk),
		.rst(rst),

		.mem_wd(mem_wd_o),
		.mem_wreg(mem_wreg_o),
		.mem_wdata(mem_wdata_i),
		.mem_pc(mem_pc_o),
		.mem_aluop(mem_aluop_o),
		.stall(stall),
	
		.wb_wd(wb_wd_i),
		.wb_wreg(wb_wreg_i),
		.wb_wdata(wb_wdata_i),
		.wb_pc(wb_pc_i),
		.wb_aluop(wb_aluop_i)
									       	
	);


	assign regfile_we 		= wb_wreg_i;
	assign regfile_waddr 	= wb_wd_i;

    

    ctrl ctrl0(
        .rst(rst),
        .stallreq_from_id(id_stallreq),
        .stallreq_from_ex(ex_stallreq),
        .stallreq_from_mem(mem_stallreq),

        .stall(stall)
    );
    

	assign debug_wb_pc 		= wb_pc_i;
	assign debug_wb_rf_wen 	= 4'b1111;
	assign debug_wb_rf_wnum = wb_wd_i;

	assign debug_wb_rf_wdata= regfile_wdata;
    
    assign regfile_wdata = ((wb_aluop_i == `ALU_OP_LW) || (wb_aluop_i == `ALU_OP_LH) || (wb_aluop_i == `ALU_OP_LB) || (wb_aluop_i == `ALU_OP_NOP)) ? data_sram_rdata : wb_wdata_i;
    
endmodule