data/full_repos/permissive/488490114/MX.v
1: b'%Warning-WIDTH: data/full_repos/permissive/488490114/MX.v:9: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'ADDR\' generates 3 bits.\n                                                           : ... In instance MX\n case(ADDR) \n ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module MX(
    input  [23:0] IN,
    input  [2:0] ADDR,
    output reg [3:0] OUT
);

always @ (IN, ADDR)
begin
	case(ADDR)	
		4'd0: 	OUT = IN[3:0];
		4'd1: 	OUT = IN[7:4];
		4'd2: 	OUT = IN[11:8];
		4'd3: 	OUT = IN[15:12];
		4'd4: 	OUT = IN[19:16];
		4'd5: 	OUT = IN[23:20];
		default: OUT = 4'b0000;
	endcase
end

endmodule
module MX(
    input  [23:0] IN,
    input  [2:0] ADDR,
    output reg [3:0] OUT
);


always @ (IN, ADDR)
begin
	case(ADDR)	
		4'd0: 	OUT = IN[3:0];
		4'd1: 	OUT = IN[7:4];
		4'd2: 	OUT = IN[11:8];
		4'd3: 	OUT = IN[15:12];
		4'd4: 	OUT = IN[19:16];
		4'd5: 	OUT = IN[23:20];
		default: OUT = 4'b0000;
	endcase
end

endmodule