data/full_repos/permissive/521256677/iiitb_alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/521256677/iiitb_alu_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/521256677/iiitb_alu_tb.v:49: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("alua.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/521256677/iiitb_alu_tb.v:51: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, iiitb_alu_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521256677/iiitb_alu_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/521256677/iiitb_alu_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    initial #500 $finish;\n            ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_alu_tb;

    reg clk;

    reg [3:0] a, b;

    reg [3:0] in;

    wire [3:0] out;

 

    integer i;



    iiitb_alu alu(.clk(clk), .A(a), .B(b), .instruction(in), .ALU_out(out));

 

    initial clk = 1'b0;

 



    always #10 clk = ~clk;



    initial begin

        a = 4'h7;

        b = 4'ha;

        in = 4'h0;



        $dumpfile("alua.vcd");

        $dumpvars(0, iiitb_alu_tb);

        for (i=0;i<=15;i=i+1) begin

            in = in + 8'h01;

            #20;

        end

    end

    initial #500 $finish;

endmodule
module iiitb_alu_tb;


    reg clk;

    reg [3:0] a, b;

    reg [3:0] in;

    wire [3:0] out;

 

    integer i;



    iiitb_alu alu(.clk(clk), .A(a), .B(b), .instruction(in), .ALU_out(out));

 

    initial clk = 1'b0;

 



    always #10 clk = ~clk;



    initial begin

        a = 4'h7;

        b = 4'ha;

        in = 4'h0;



        $dumpfile("alua.vcd");

        $dumpvars(0, iiitb_alu_tb);

        for (i=0;i<=15;i=i+1) begin

            in = in + 8'h01;

            #20;

        end

    end

    initial #500 $finish;

endmodule