data/full_repos/permissive/527176783/Pipeline/MEM_WB.v
data/verilator_xmls/aaed156f-12e4-4222-bbd7-ee94029ac55f.xml
module MEM_WB(
    input           clk,
    input           rst_n,
    input           regWr_MEM,
    input           Wrback_MEM,

    input [31:0]    ReadMemData_MEM,
    input [31:0]    AluResult_MEM,
    input [4:0]     WriteReg_MEM,

    output reg      regWr_WB,
    output reg      Wrback_WB,

    output reg [31:0] ReadMemData_WB,
    output reg [31:0] AluResult_WB,
    output reg [4:0]  WriteReg_WB
);
    
    always @(posedge clk,negedge rst_n) begin
        if(~rst_n)begin
            regWr_WB            <=   0;
            Wrback_WB           <=   0;
            ReadMemData_WB      <=   0;
            AluResult_WB        <=   0;
            WriteReg_WB         <=   0;
        end
        else begin
            regWr_WB            <=   regWr_MEM;
            Wrback_WB           <=   Wrback_MEM;
            ReadMemData_WB      <=   ReadMemData_MEM;
            AluResult_WB        <=   AluResult_MEM;
            WriteReg_WB         <=   WriteReg_MEM;
        end
    end
    
endmodule
module MEM_WB(
    input           clk,
    input           rst_n,
    input           regWr_MEM,
    input           Wrback_MEM,

    input [31:0]    ReadMemData_MEM,
    input [31:0]    AluResult_MEM,
    input [4:0]     WriteReg_MEM,

    output reg      regWr_WB,
    output reg      Wrback_WB,

    output reg [31:0] ReadMemData_WB,
    output reg [31:0] AluResult_WB,
    output reg [4:0]  WriteReg_WB
);

    
    always @(posedge clk,negedge rst_n) begin
        if(~rst_n)begin
            regWr_WB            <=   0;
            Wrback_WB           <=   0;
            ReadMemData_WB      <=   0;
            AluResult_WB        <=   0;
            WriteReg_WB         <=   0;
        end
        else begin
            regWr_WB            <=   regWr_MEM;
            Wrback_WB           <=   Wrback_MEM;
            ReadMemData_WB      <=   ReadMemData_MEM;
            AluResult_WB        <=   AluResult_MEM;
            WriteReg_WB         <=   WriteReg_MEM;
        end
    end
    
endmodule