data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4_lite_slave_fsm.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4_lite_slave_fsm.v:133: Signal definition not found, creating implicitly: \'ADDR_READ_EN\'\n                                                                                                : ... Suggested alternative: \'ADDR_WRITE_EN\'\n assign ADDR_READ_EN = S_AXI_ARVALID & S_AXI_ARREADY;\n        ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module axi4_lite_slave_fsm #
(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32,
    parameter STRB_WIDTH = (DATA_WIDTH/8)
)(
    input  wire        ACLK,
    input  wire        ARESETn,


    output wire        			 S_AXI_AWREADY,
    input  wire        			 S_AXI_AWVALID,
    input  wire [ADDR_WIDTH-1:0] S_AXI_AWADDR,
    

    output wire        			 S_AXI_WREADY,
    input  wire                  S_AXI_WVALID,
    input  wire [DATA_WIDTH-1:0] S_AXI_WDATA,  
    input  wire [STRB_WIDTH-1:0] S_AXI_WSTRB, 
                                                

    input  wire        S_AXI_BREADY, 
    output wire        S_AXI_BVALID, 
    output wire [1:0]  S_AXI_BRESP,




    output wire        			 S_AXI_ARREADY, 
    input  wire        			 S_AXI_ARVALID, 
    input  wire [ADDR_WIDTH-1:0] S_AXI_ARADDR,


    input  wire        			 S_AXI_RREADY, 
    output wire        			 S_AXI_RVALID, 
    output wire [1:0]  			 S_AXI_RRESP,  
    output wire [DATA_WIDTH-1:0] S_AXI_RDATA
);

    localparam SET_OK   = 2'b00;
    localparam SET_HIGH = 1'b1;
    localparam SET_LOW  = 1'b0;


    reg [DATA_WIDTH-1:0] BRAM[(2**6)-1:0];


	localparam S_WRIDLE = 2'd0,
			   S_WRDATA = 2'd1,
			   S_WRRESP = 2'd2;

	localparam S_RDIDLE = 2'd0,
			   S_RDDATA = 2'd1;
	

	reg [1:0] WRITE_STATE, NEXT_WRITE_STATE;
	reg [ADDR_WIDTH-1:0] WRITE_ADDR;
	wire [ADDR_WIDTH-1:0] MASK;
	wire ADDR_WRITE_EN, WRITE_EN;

	reg [1:0] READ_STATE, NEXT_READ_STATE;
	wire [ADDR_WIDTH-1:0] RADDR;
	reg [ADDR_WIDTH-1:0] RDATA;
	wire ar_hs;



	assign S_AXI_AWREADY = (WRITE_STATE == S_WRIDLE);
	assign S_AXI_WREADY  = (WRITE_STATE == S_WRDATA);
	assign S_AXI_BRESP   = SET_OK;
	assign S_AXI_BVALID  = (WRITE_STATE == S_WRRESP);
	assign MASK = {{8{S_AXI_WSTRB[3]}}, {8{S_AXI_WSTRB[2]}}, {8{S_AXI_WSTRB[1]}}, {8{S_AXI_WSTRB[0]}}};
	assign ADDR_WRITE_EN = S_AXI_AWVALID & S_AXI_AWREADY;
	assign WRITE_EN = S_AXI_WVALID & S_AXI_WREADY;


	always @(posedge ACLK)
	begin
		if (!ARESETn)
			WRITE_STATE <= S_WRIDLE;
		else
			WRITE_STATE <= NEXT_WRITE_STATE;
	end
	

	always @(*)
	begin
		case (WRITE_STATE)
			S_WRIDLE:
				if (S_AXI_AWVALID)
					NEXT_WRITE_STATE = S_WRDATA;
				else
					NEXT_WRITE_STATE = S_WRIDLE;
			S_WRDATA:
				if (S_AXI_AWVALID)
					NEXT_WRITE_STATE = S_WRRESP;
				else
					NEXT_WRITE_STATE = S_WRDATA;
			S_WRRESP:
				if (S_AXI_BREADY)
					NEXT_WRITE_STATE = S_WRIDLE;
				else
					NEXT_WRITE_STATE = S_WRRESP;
			default:
				NEXT_WRITE_STATE = S_WRIDLE;
		endcase
	end
	

	always @(posedge ACLK)
	begin
		if (ADDR_WRITE_EN)
			WRITE_ADDR <= S_AXI_AWADDR[ADDR_WIDTH-1:0];
	end
	

	assign S_AXI_ARREADY = (READ_STATE == S_RDIDLE);
	assign S_AXI_RDATA = RDATA;
	assign S_AXI_RRESP = SET_OK;  
	assign S_AXI_RVALID = (READ_STATE == S_RDDATA);
	assign ADDR_READ_EN = S_AXI_ARVALID & S_AXI_ARREADY;
	assign RADDR = S_AXI_ARADDR[ADDR_WIDTH-1:0];
	

	always @(posedge ACLK)
	begin
		if (!ARESETn)
			READ_STATE <= S_RDIDLE;
		else
			READ_STATE <= NEXT_READ_STATE;
	end


	always @(*) 
	begin
		case (READ_STATE)
			S_RDIDLE:
				if (S_AXI_ARVALID)
					NEXT_READ_STATE = S_RDDATA;
				else
					NEXT_READ_STATE = S_RDIDLE;
			S_RDDATA:
				if (S_AXI_RREADY)
					NEXT_READ_STATE = S_RDIDLE;
				else
					NEXT_READ_STATE = S_RDDATA;
			default:
				NEXT_READ_STATE = S_RDIDLE;
		endcase
	end
	

	always @(posedge ACLK)
	begin
	    if (!ARESETn)
	        RDATA <= 0;
		else if (ADDR_READ_EN)
			RDATA <= BRAM[RADDR];
	end


    always @(posedge ACLK)
	begin
	    if (!ARESETn)
	    begin
            WRITE_ADDR <= 0;
        end
		else if (WRITE_EN)
		begin
			BRAM[WRITE_ADDR] <= S_AXI_WDATA;
	    end
	end
	

endmodule
module axi4_lite_slave_fsm #
(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32,
    parameter STRB_WIDTH = (DATA_WIDTH/8)
)(
    input  wire        ACLK,
    input  wire        ARESETn,


    output wire        			 S_AXI_AWREADY,
    input  wire        			 S_AXI_AWVALID,
    input  wire [ADDR_WIDTH-1:0] S_AXI_AWADDR,
    

    output wire        			 S_AXI_WREADY,
    input  wire                  S_AXI_WVALID,
    input  wire [DATA_WIDTH-1:0] S_AXI_WDATA,  
    input  wire [STRB_WIDTH-1:0] S_AXI_WSTRB, 
                                                

    input  wire        S_AXI_BREADY, 
    output wire        S_AXI_BVALID, 
    output wire [1:0]  S_AXI_BRESP,




    output wire        			 S_AXI_ARREADY, 
    input  wire        			 S_AXI_ARVALID, 
    input  wire [ADDR_WIDTH-1:0] S_AXI_ARADDR,


    input  wire        			 S_AXI_RREADY, 
    output wire        			 S_AXI_RVALID, 
    output wire [1:0]  			 S_AXI_RRESP,  
    output wire [DATA_WIDTH-1:0] S_AXI_RDATA
);


    localparam SET_OK   = 2'b00;
    localparam SET_HIGH = 1'b1;
    localparam SET_LOW  = 1'b0;


    reg [DATA_WIDTH-1:0] BRAM[(2**6)-1:0];


	localparam S_WRIDLE = 2'd0,
			   S_WRDATA = 2'd1,
			   S_WRRESP = 2'd2;

	localparam S_RDIDLE = 2'd0,
			   S_RDDATA = 2'd1;
	

	reg [1:0] WRITE_STATE, NEXT_WRITE_STATE;
	reg [ADDR_WIDTH-1:0] WRITE_ADDR;
	wire [ADDR_WIDTH-1:0] MASK;
	wire ADDR_WRITE_EN, WRITE_EN;

	reg [1:0] READ_STATE, NEXT_READ_STATE;
	wire [ADDR_WIDTH-1:0] RADDR;
	reg [ADDR_WIDTH-1:0] RDATA;
	wire ar_hs;



	assign S_AXI_AWREADY = (WRITE_STATE == S_WRIDLE);
	assign S_AXI_WREADY  = (WRITE_STATE == S_WRDATA);
	assign S_AXI_BRESP   = SET_OK;
	assign S_AXI_BVALID  = (WRITE_STATE == S_WRRESP);
	assign MASK = {{8{S_AXI_WSTRB[3]}}, {8{S_AXI_WSTRB[2]}}, {8{S_AXI_WSTRB[1]}}, {8{S_AXI_WSTRB[0]}}};
	assign ADDR_WRITE_EN = S_AXI_AWVALID & S_AXI_AWREADY;
	assign WRITE_EN = S_AXI_WVALID & S_AXI_WREADY;


	always @(posedge ACLK)
	begin
		if (!ARESETn)
			WRITE_STATE <= S_WRIDLE;
		else
			WRITE_STATE <= NEXT_WRITE_STATE;
	end
	

	always @(*)
	begin
		case (WRITE_STATE)
			S_WRIDLE:
				if (S_AXI_AWVALID)
					NEXT_WRITE_STATE = S_WRDATA;
				else
					NEXT_WRITE_STATE = S_WRIDLE;
			S_WRDATA:
				if (S_AXI_AWVALID)
					NEXT_WRITE_STATE = S_WRRESP;
				else
					NEXT_WRITE_STATE = S_WRDATA;
			S_WRRESP:
				if (S_AXI_BREADY)
					NEXT_WRITE_STATE = S_WRIDLE;
				else
					NEXT_WRITE_STATE = S_WRRESP;
			default:
				NEXT_WRITE_STATE = S_WRIDLE;
		endcase
	end
	

	always @(posedge ACLK)
	begin
		if (ADDR_WRITE_EN)
			WRITE_ADDR <= S_AXI_AWADDR[ADDR_WIDTH-1:0];
	end
	

	assign S_AXI_ARREADY = (READ_STATE == S_RDIDLE);
	assign S_AXI_RDATA = RDATA;
	assign S_AXI_RRESP = SET_OK;  
	assign S_AXI_RVALID = (READ_STATE == S_RDDATA);
	assign ADDR_READ_EN = S_AXI_ARVALID & S_AXI_ARREADY;
	assign RADDR = S_AXI_ARADDR[ADDR_WIDTH-1:0];
	

	always @(posedge ACLK)
	begin
		if (!ARESETn)
			READ_STATE <= S_RDIDLE;
		else
			READ_STATE <= NEXT_READ_STATE;
	end


	always @(*) 
	begin
		case (READ_STATE)
			S_RDIDLE:
				if (S_AXI_ARVALID)
					NEXT_READ_STATE = S_RDDATA;
				else
					NEXT_READ_STATE = S_RDIDLE;
			S_RDDATA:
				if (S_AXI_RREADY)
					NEXT_READ_STATE = S_RDIDLE;
				else
					NEXT_READ_STATE = S_RDDATA;
			default:
				NEXT_READ_STATE = S_RDIDLE;
		endcase
	end
	

	always @(posedge ACLK)
	begin
	    if (!ARESETn)
	        RDATA <= 0;
		else if (ADDR_READ_EN)
			RDATA <= BRAM[RADDR];
	end


    always @(posedge ACLK)
	begin
	    if (!ARESETn)
	    begin
            WRITE_ADDR <= 0;
        end
		else if (WRITE_EN)
		begin
			BRAM[WRITE_ADDR] <= S_AXI_WDATA;
	    end
	end
	

endmodule