data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v
1: b'%Error: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:22: Cannot find include file: decoder_4x16.v\n`include "decoder_4x16.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476728999/Experiment4,data/full_repos/permissive/476728999/decoder_4x16.v\n             data/full_repos/permissive/476728999/Experiment4,data/full_repos/permissive/476728999/decoder_4x16.v.v\n             data/full_repos/permissive/476728999/Experiment4,data/full_repos/permissive/476728999/decoder_4x16.v.sv\n             decoder_4x16.v\n             decoder_4x16.v.v\n             decoder_4x16.v.sv\n             obj_dir/decoder_4x16.v\n             obj_dir/decoder_4x16.v.v\n             obj_dir/decoder_4x16.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=0; c=1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=1; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=1; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=0; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=0; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=1; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=1; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=0; c=0; w=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=0; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=1; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=0; b=1; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=0; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=0; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=1; c=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n            #25 a=1; b=1; c=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment4/decoder_4x16_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #25 $finish;\n            ^\n%Error: Exiting due to 1 error(s), 16 warning(s)\n'
module decoder_4x16_tb;
    reg a,b,c,w;
    wire [15:0] d;
    
    decoder_4x16 UUT (.a(a), .b(b), .c(c), .w(w), .d(d));
    
    initial
        begin
            a=0; b=0; c=0; w=0;
            #25 a=0; b=0; c=1;
            #25 a=0; b=1; c=0;
            #25 a=0; b=1; c=1;
            #25 a=1; b=0; c=0;
            #25 a=1; b=0; c=1;
            #25 a=1; b=1; c=0;
            #25 a=1; b=1; c=1;
            #25 a=0; b=0; c=0; w=1;
            #25 a=0; b=0; c=1;
            #25 a=0; b=1; c=0;
            #25 a=0; b=1; c=1;
            #25 a=1; b=0; c=0;
            #25 a=1; b=0; c=1;
            #25 a=1; b=1; c=0;
            #25 a=1; b=1; c=1;
            #25 $finish;
    end

endmodule
module decoder_4x16_tb;

    reg a,b,c,w;
    wire [15:0] d;
    
    decoder_4x16 UUT (.a(a), .b(b), .c(c), .w(w), .d(d));
    
    initial
        begin
            a=0; b=0; c=0; w=0;
            #25 a=0; b=0; c=1;
            #25 a=0; b=1; c=0;
            #25 a=0; b=1; c=1;
            #25 a=1; b=0; c=0;
            #25 a=1; b=0; c=1;
            #25 a=1; b=1; c=0;
            #25 a=1; b=1; c=1;
            #25 a=0; b=0; c=0; w=1;
            #25 a=0; b=0; c=1;
            #25 a=0; b=1; c=0;
            #25 a=0; b=1; c=1;
            #25 a=1; b=0; c=0;
            #25 a=1; b=0; c=1;
            #25 a=1; b=1; c=0;
            #25 a=1; b=1; c=1;
            #25 $finish;
    end

endmodule