data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Lemmings 2.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Lemmings\n%Error: Cannot find file containing module: 2.v\n%Error: Exiting due to 6 error(s)\n'
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 


    parameter left = 0, fall_left = 1, right = 2, fall_right = 3;
    reg [1:0] current, next;
    
    always @(*) begin
        case(current)
            left: if(!ground) next<= fall_left;
            	else if(bump_left) next<=right;
            	else next<=left;
            right: if(!ground) next<=fall_right;
            	else if(bump_right) next<=left;
            	else next<= right;
            fall_left: if(!ground)	next<=fall_left;
            	else next<=left;
            fall_right: if(!ground) next<=fall_right;
            	else next<= right;
        endcase
    end
    
    always @ (posedge clk or posedge areset) begin
        if(areset) current<=left;
        else current<=next;
    end
    
    assign walk_left = (current==left);
    assign walk_right = (current==right);
    assign aaah = (current== fall_left | current==fall_right);
            
endmodule
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah );
 


    parameter left = 0, fall_left = 1, right = 2, fall_right = 3;
    reg [1:0] current, next;
    
    always @(*) begin
        case(current)
            left: if(!ground) next<= fall_left;
            	else if(bump_left) next<=right;
            	else next<=left;
            right: if(!ground) next<=fall_right;
            	else if(bump_right) next<=left;
            	else next<= right;
            fall_left: if(!ground)	next<=fall_left;
            	else next<=left;
            fall_right: if(!ground) next<=fall_right;
            	else next<= right;
        endcase
    end
    
    always @ (posedge clk or posedge areset) begin
        if(areset) current<=left;
        else current<=next;
    end
    
    assign walk_left = (current==left);
    assign walk_right = (current==right);
    assign aaah = (current== fall_left | current==fall_right);
            
endmodule