data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src/vga_mem.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src/vga_mem.v:24: Signal definition not found, creating implicitly: \'blank\'\nassign RED = (blank?0:color[7:5]);\n              ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src/vga_mem.v:20: Cannot find file containing module: \'vga\'\nvga v(.CLK (CLK), .HS (HS), .VS (VS), .x (cx), .y (y), .blank (blank));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src,data/full_repos/permissive/52871302/vga\n             data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src,data/full_repos/permissive/52871302/vga.v\n             data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src,data/full_repos/permissive/52871302/vga.sv\n             vga\n             vga.v\n             vga.sv\n             obj_dir/vga\n             obj_dir/vga.v\n             obj_dir/vga.sv\n%Warning-WIDTH: data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src/vga_mem.v:22: Operator DIV expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'y\' generates 10 bits.\n                                                                                         : ... In instance vga_mem\nassign mem_index = (y / 8) * 80 + x / 8;  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/52871302/elbert2/ch09_vga_mem/src/vga_mem.v:22: Operator DIV expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'x\' generates 10 bits.\n                                                                                         : ... In instance vga_mem\nassign mem_index = (y / 8) * 80 + x / 8;  \n                                    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module vga_mem(
    input CLK,
    output HS,
    output VS,
    output [2:0] RED,
    output [2:0] GREEN,
    output [1:0] BLUE
    );

wire [9:0] x, y;

reg [7:0] mem[4799:0];
wire [12:0] mem_index;
wire [7:0] color;

initial begin
  $readmemh("flag.txt", mem);
end

vga v(.CLK (CLK), .HS (HS), .VS (VS), .x (cx), .y (y), .blank (blank));

assign mem_index = (y / 8) * 80 + x / 8;
assign color = mem[mem_index];
assign RED = (blank?0:color[7:5]);
assign GREEN = (blank?0:color[4:2]);
assign BLUE = (blank?0:color[1:0]);

endmodule
module vga_mem(
    input CLK,
    output HS,
    output VS,
    output [2:0] RED,
    output [2:0] GREEN,
    output [1:0] BLUE
    );


wire [9:0] x, y;

reg [7:0] mem[4799:0];
wire [12:0] mem_index;
wire [7:0] color;

initial begin
  $readmemh("flag.txt", mem);
end

vga v(.CLK (CLK), .HS (HS), .VS (VS), .x (cx), .y (y), .blank (blank));

assign mem_index = (y / 8) * 80 + x / 8;
assign color = mem[mem_index];
assign RED = (blank?0:color[7:5]);
assign GREEN = (blank?0:color[4:2]);
assign BLUE = (blank?0:color[1:0]);

endmodule