data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:15: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:18: Unsupported: Ignoring delay on this delayed statement.\n #50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:18: Unsupported: Ignoring delay on this delayed statement.\n #50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:18: Unsupported: Ignoring delay on this delayed statement.\n #50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:18: Unsupported: Ignoring delay on this delayed statement.\n #50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;\n                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:19: Unsupported: Ignoring delay on this delayed statement.\n #70 MFA = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32\'hAAAA_AAAA;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32\'hAAAA_AAAA;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32\'hAAAA_AAAA;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32\'hAAAA_AAAA;\n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32\'hAAAA_AAAA;\n                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:24: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:26: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:29: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("memorytestbench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/memory/MEM_256B_TEST.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,memorytestbench);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memorytestbench;

parameter sim_time = 750*2;

wire  MFC;
wire [31:0] MEMDAT;
reg [31:0] MEMDAT_BUFF;
reg MFA,READ_WRITE,WORD_BYTE, Reset ,Clk;
reg [7:0] MEMADD;

assign MEMDAT = MEMDAT_BUFF;


memory mem( MEMDAT, MFC,  MFA, READ_WRITE,  MEMADD,  WORD_BYTE, Reset);
initial fork
	Reset =1; Clk = 0; MEMADD=0;MFA=0;MEMADD=0; MEMDAT_BUFF = 32'hzzzz_zzzz;
	#1 Reset = 0;
	#50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;
	#70 MFA = 0;
	#100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32'hAAAA_AAAA;
join
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("memorytestbench.vcd");
	$dumpvars(0,memorytestbench);
	$display(" Test Results" );

end

endmodule
module memorytestbench;


parameter sim_time = 750*2;

wire  MFC;
wire [31:0] MEMDAT;
reg [31:0] MEMDAT_BUFF;
reg MFA,READ_WRITE,WORD_BYTE, Reset ,Clk;
reg [7:0] MEMADD;

assign MEMDAT = MEMDAT_BUFF;


memory mem( MEMDAT, MFC,  MFA, READ_WRITE,  MEMADD,  WORD_BYTE, Reset);
initial fork
	Reset =1; Clk = 0; MEMADD=0;MFA=0;MEMADD=0; MEMDAT_BUFF = 32'hzzzz_zzzz;
	#1 Reset = 0;
	#50 MEMADD = 0 ; #50 READ_WRITE  =1 ; #50 WORD_BYTE = 0 ;  #50 MFA = 1;
	#70 MFA = 0;
	#100 MEMADD = 0 ; #100 READ_WRITE  =0 ; #100 WORD_BYTE = 0 ;  #100 MFA = 1; #100  MEMDAT_BUFF = 32'hAAAA_AAAA;
join
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("memorytestbench.vcd");
	$dumpvars(0,memorytestbench);
	$display(" Test Results" );

end

endmodule