data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_test_stub_scan.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_test_stub_scan.v:25: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_test_stub_scan (

se, so_0, 

global_shift_enable, ctu_tst_scan_disable, 

ctu_tst_short_chain, long_chain_so_0, short_chain_so_0
);

   input        global_shift_enable;
   input        ctu_tst_scan_disable;

   input 	ctu_tst_short_chain;
   input 	long_chain_so_0;
   input 	short_chain_so_0;
   
   output 	se;
   output 	so_0;


   wire         short_chain_select;


   assign  se                 = ~ctu_tst_scan_disable & global_shift_enable;

   assign  short_chain_select = ctu_tst_short_chain;
   assign  so_0               = short_chain_select ? short_chain_so_0 : long_chain_so_0;
   
endmodule
module ctu_test_stub_scan (

se, so_0, 

global_shift_enable, ctu_tst_scan_disable, 

ctu_tst_short_chain, long_chain_so_0, short_chain_so_0
);


   input        global_shift_enable;
   input        ctu_tst_scan_disable;

   input 	ctu_tst_short_chain;
   input 	long_chain_so_0;
   input 	short_chain_so_0;
   
   output 	se;
   output 	so_0;


   wire         short_chain_select;


   assign  se                 = ~ctu_tst_scan_disable & global_shift_enable;

   assign  short_chain_select = ctu_tst_short_chain;
   assign  so_0               = short_chain_select ? short_chain_so_0 : long_chain_so_0;
   
endmodule