data/full_repos/permissive/499494419/bocing.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499494419/bocing.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bocing.v:53: Unsupported: Ignoring delay on this delayed statement.\n always #10 sys_clk=~sys_clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bocing.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #200 sys_rst_n=~sys_rst_n;\n        ^\n%Error: data/full_repos/permissive/499494419/bocing.v:35: Cannot find file containing module: \'miantiao\'\n miantiao uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/miantiao\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/miantiao.v\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/miantiao.sv\n             miantiao\n             miantiao.v\n             miantiao.sv\n             obj_dir/miantiao\n             obj_dir/miantiao.v\n             obj_dir/miantiao.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bocing;


	reg sys_clk;
	reg sys_rst_n;


	wire [24:0] cnt;


	miantiao uut (
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n), 
		.cnt(cnt)
	);

	initial begin

		sys_clk = 0;
		sys_rst_n = 1;
		


		#100;
        


	end
	always #10 sys_clk=~sys_clk;
	always #200 sys_rst_n=~sys_rst_n;
	
      
endmodule
module bocing;



	reg sys_clk;
	reg sys_rst_n;


	wire [24:0] cnt;


	miantiao uut (
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n), 
		.cnt(cnt)
	);

	initial begin

		sys_clk = 0;
		sys_rst_n = 1;
		


		#100;
        


	end
	always #10 sys_clk=~sys_clk;
	always #200 sys_rst_n=~sys_rst_n;
	
      
endmodule