data/full_repos/permissive/459277146/multiplier.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/multiplier.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459277146/multiplier.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/multiplier.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/multiplier.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Error: data/full_repos/permissive/459277146/multiplier.v:138: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd"); $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/multiplier.v:138: Unsupported or unknown PLI call: $dumpvars\n  $dumpfile("dump.vcd"); $dumpvars;\n                         ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder (in1, in2, carry_in, sum, carry_out);
parameter DATA_WID = 8;

input [DATA_WID - 1:0] in1;
input [DATA_WID - 1:0] in2;
input carry_in;
output [DATA_WID - 1:0] sum;
output carry_out;



wire [DATA_WID - 1:0] gen;
wire [DATA_WID - 1:0] pro;
wire [DATA_WID:0] carry_tmp;

genvar j, i;
generate

 assign carry_tmp[0] = carry_in;
 

 for(j = 0; j < DATA_WID; j = j + 1) begin: carry_generator
 assign gen[j] = in1[j] & in2[j];
 assign pro[j] = in1[j] | in2[j];
 assign carry_tmp[j+1] = gen[j] | pro[j] & carry_tmp[j];
 end
 

 assign carry_out = carry_tmp[DATA_WID];
 


 for(i = 0; i < DATA_WID; i = i+1) begin: sum_without_carry
 assign sum[i] = in1[i] ^ in2[i] ^ carry_tmp[i];
 end 
endgenerate 
endmodule
module adder (in1, in2, carry_in, sum, carry_out);

parameter DATA_WID = 8;

input [DATA_WID - 1:0] in1;
input [DATA_WID - 1:0] in2;
input carry_in;
output [DATA_WID - 1:0] sum;
output carry_out;



wire [DATA_WID - 1:0] gen;
wire [DATA_WID - 1:0] pro;
wire [DATA_WID:0] carry_tmp;

genvar j, i;
generate

 assign carry_tmp[0] = carry_in;
 

 for(j = 0; j < DATA_WID; j = j + 1) begin: carry_generator
 assign gen[j] = in1[j] & in2[j];
 assign pro[j] = in1[j] | in2[j];
 assign carry_tmp[j+1] = gen[j] | pro[j] & carry_tmp[j];
 end
 

 assign carry_out = carry_tmp[DATA_WID];
 


 for(i = 0; i < DATA_WID; i = i+1) begin: sum_without_carry
 assign sum[i] = in1[i] ^ in2[i] ^ carry_tmp[i];
 end 
endgenerate 
endmodule