data/full_repos/permissive/524553217/src/program_counter.v
data/verilator_xmls/ed3067f5-abc5-4b87-9735-7990f0504b33.xml
module program_counter(
    input [31:0] pc_in,
    input rst,
    input clk,
    output reg [31:0] pc_out
    );

    initial begin
        pc_out = 32'h00010000;
    end

    always @(posedge clk) begin
        if(rst) pc_out <= 32'h00010000;
        else pc_out <= pc_in;
    end
    
endmodule
module program_counter(
    input [31:0] pc_in,
    input rst,
    input clk,
    output reg [31:0] pc_out
    );


    initial begin
        pc_out = 32'h00010000;
    end

    always @(posedge clk) begin
        if(rst) pc_out <= 32'h00010000;
        else pc_out <= pc_in;
    end
    
endmodule