data/full_repos/permissive/440792992/hardware/decode_stage.v
1: b'%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:9: Cannot find include file: configure.h\n`include "configure.h" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.v\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.sv\n             configure.h\n             configure.h.v\n             configure.h.sv\n             obj_dir/configure.h\n             obj_dir/configure.h.v\n             obj_dir/configure.h.sv\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:59: Define or directive not defined: \'`I_type\'\n        inst_type    = `I_type;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        inst_type    = `I_type;\n                              ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:60: Define or directive not defined: \'`SRC1_RS1\'\n        src1_sel    = `SRC1_RS1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        src1_sel    = `SRC1_RS1;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:61: Define or directive not defined: \'`SRC2_IMM\'\n        src2_sel    = `SRC2_IMM;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        src2_sel    = `SRC2_IMM;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:63: Define or directive not defined: \'`ALU_ADD\'\n        alu_op      = `ALU_ADD;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        alu_op      = `ALU_ADD;\n                              ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:64: Define or directive not defined: \'`RS_ALU\'\n        rs_type     = `RS_ALU;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rs_type     = `RS_ALU;\n                             ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:75: Define or directive not defined: \'`U_type\'\n                inst_type  = `U_type;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                inst_type  = `U_type;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:76: Define or directive not defined: \'`SRC1_ZERO\'\n                src1_sel  = `SRC1_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src1_sel  = `SRC1_ZERO;\n                                      ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:81: Define or directive not defined: \'`U_type\'\n                inst_type  = `U_type;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                inst_type  = `U_type;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:82: Define or directive not defined: \'`SRC1_PC\'\n    src1_sel  = `SRC1_PC;   \n                ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    src1_sel  = `SRC1_PC;   \n                        ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:87: Define or directive not defined: \'`SRC1_PC\'\n                src1_sel  = `SRC1_PC;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src1_sel  = `SRC1_PC;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:88: Define or directive not defined: \'`SRC2_FOUR\'\n                src2_sel  = `SRC2_FOUR;    \n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src2_sel  = `SRC2_FOUR;    \n                                      ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:89: Define or directive not defined: \'`RS_JAL\'\n                rs_type   = `RS_JAL;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                rs_type   = `RS_JAL;\n                                   ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:93: Define or directive not defined: \'`SRC1_PC\'\n                src1_sel  = `SRC1_PC;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src1_sel  = `SRC1_PC;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:94: Define or directive not defined: \'`SRC2_FOUR\'\n                src2_sel  = `SRC2_FOUR;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src2_sel  = `SRC2_FOUR;\n                                      ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:96: Define or directive not defined: \'`RS_JALR\'\n                rs_type   = `RS_JALR;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                rs_type   = `RS_JALR;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:101: Define or directive not defined: \'`SRC2_RS2\'\n                src2_sel  = `SRC2_RS2;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src2_sel  = `SRC2_RS2;\n                                     ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:102: Define or directive not defined: \'`RS_BRANCH\'\n    rs_type   = `RS_BRANCH;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    rs_type   = `RS_BRANCH;\n                          ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:104: Define or directive not defined: \'`ALU_SEQ\'\n                    3\'b000  : alu_op   = `ALU_SEQ;   \n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    3\'b000  : alu_op   = `ALU_SEQ;   \n                                                 ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:105: Define or directive not defined: \'`ALU_SNE\'\n                    3\'b001  : alu_op   = `ALU_SNE;   \n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    3\'b001  : alu_op   = `ALU_SNE;   \n                                                 ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:106: Define or directive not defined: \'`ALU_SLT\'\n                    3\'b100  : alu_op   = `ALU_SLT;   \n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    3\'b100  : alu_op   = `ALU_SLT;   \n                                                 ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:107: Define or directive not defined: \'`ALU_SGE\'\n                    3\'b101  : alu_op   = `ALU_SGE;   \n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    3\'b101  : alu_op   = `ALU_SGE;   \n                                                 ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:108: Define or directive not defined: \'`ALU_SLTU\'\n     3\'b110  : alu_op   = `ALU_SLTU;  \n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     3\'b110  : alu_op   = `ALU_SLTU;  \n                                   ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:109: Define or directive not defined: \'`ALU_SGEU\'\n                    3\'b111  : alu_op   = `ALU_SGEU;  \n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    3\'b111  : alu_op   = `ALU_SGEU;  \n                                                  ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:116: Define or directive not defined: \'`RS_LDST\'\n                rs_type    = `RS_LDST;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                rs_type    = `RS_LDST;\n                                     ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_stage.v:126: Define or directive not defined: \'`S_type\'\n                inst_type   = `S_type;\n                              ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Decoder
(
    input      [31:0] inst,
    
	output     [4:0]  rd,
    output     [4:0]  rs1,
    output     [4:0]  rs2,
	output reg        rd_valid,
    output reg        rs1_valid,
    output reg        rs2_valid,
    
	output reg [2:0]  inst_type,
    output reg [1:0]  src1_sel,
    output reg [1:0]  src2_sel,
    output reg        ill_inst,
    output reg [3:0]  alu_op,
    output reg [2:0]  rs_type,

`ifdef ENABLE_MULDIV
	output reg [1:0]  muldiv_op,
    output reg        muldiv_rs1_signed,
    output reg        muldiv_rs2_signed,
    output reg [1:0]  muldiv_out_sel,
`endif

    output reg        dmem_valid,
    output reg [3:0]  dmem_wrstrb,
	output reg [3:0]  dmem_rdstrb
);
    wire [3:0]        srl_or_sra;
    wire [3:0]        add_or_sub;
    wire [2:0]        rs_type_md;
   
    wire [6:0]        opcode  = inst[6:0];
    wire [6:0]        funct7  = inst[31:25];
    wire [11:0]       funct12 = inst[31:20];
    wire [2:0]        funct3  = inst[14:12];
    reg  [3:0]        alu_op_arith;
   
    assign rd  = inst[11:7];
    assign rs1 = inst[19:15];
    assign rs2 = inst[24:20];
   
    always @(*) begin
        rd_valid    = 1'b0;
        rs1_valid   = 1'b1;
        rs2_valid   = 1'b0;

        inst_type    = `I_type;
        src1_sel    = `SRC1_RS1;
        src2_sel    = `SRC2_IMM;
        ill_inst    = 1'b0;
        alu_op      = `ALU_ADD;
        rs_type     = `RS_ALU;
		
        dmem_valid  = 1'b0;
        dmem_wrstrb = 4'b0;
		dmem_rdstrb = 4'b0;

        (* parallel_case, full_case *)
        case (opcode)
            7'b0110111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                inst_type  = `U_type;
                src1_sel  = `SRC1_ZERO;
			end
            7'b0010111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                inst_type  = `U_type;
				src1_sel  = `SRC1_PC;   
            end
            7'b1101111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                src1_sel  = `SRC1_PC;
                src2_sel  = `SRC2_FOUR;    
                rs_type   = `RS_JAL;
            end
            7'b1100111 : begin
                rd_valid  = 1'b1;
                src1_sel  = `SRC1_PC;
                src2_sel  = `SRC2_FOUR;
                ill_inst  = (funct3 != 0);
                rs_type   = `RS_JALR;
            end
            7'b1100011 : begin

				rs2_valid = 1'b1;
                src2_sel  = `SRC2_RS2;
				rs_type   = `RS_BRANCH;
                case (funct3)
                    3'b000  : alu_op   = `ALU_SEQ;
                    3'b001  : alu_op   = `ALU_SNE;
                    3'b100  : alu_op   = `ALU_SLT;
                    3'b101  : alu_op   = `ALU_SGE;
					3'b110  : alu_op   = `ALU_SLTU;
                    3'b111  : alu_op   = `ALU_SGEU;
                    default : ill_inst = 1'b1;
                endcase    
            end
            7'b0000011 : begin
                dmem_valid = 1'b1;
                rd_valid   = 1'b1;
                rs_type    = `RS_LDST;
				(* full_case *)
				case (funct3)
				    3'b000: dmem_rdstrb = 4'b0001;
					3'b001: dmem_rdstrb = 4'b0011;
					3'b010: dmem_rdstrb = 4'b1111;
				endcase
            end
            7'b0100011 : begin
                rs2_valid  = 1'b1;
                inst_type   = `S_type;
                dmem_valid = 1'b1;
                rs_type    = `RS_LDST;
				(* full_case *)
				case (funct3)
				    3'b000: dmem_wrstrb = 4'b0001;
					3'b001: dmem_wrstrb = 4'b0011;
					3'b010: dmem_wrstrb = 4'b1111;
				endcase
            end
            7'b0010011 : begin
                rd_valid   = 1'b1;
                case (funct3)
                    3'b000  : alu_op   = `ALU_ADD;
                    3'b010  : alu_op   = `ALU_SLT;
                    3'b011  : alu_op   = `ALU_SLT;
                    3'b100  : alu_op   = `ALU_XOR;
					3'b110  : alu_op   = `ALU_OR;
                    3'b111  : alu_op   = `ALU_AND;
					3'b001  : begin
					      if (funct7 == 7'b0000000) begin
						      alu_op   = `ALU_SLL;
						  end else begin
						      ill_inst = 1'b1;
						  end
					end
					3'b101 : begin
					      if (funct7 == 7'b0000000) begin
						      alu_op   = `ALU_SRL;
						  end else if (funct7 == 7'b0100000) begin
						      alu_op   = `ALU_SRA;
					      end else
						      ill_inst = 1'b1;
						  end
                    default : ill_inst = 1'b1;
                endcase  
            end
            7'b0110011 : begin
                rd_valid   = 1'b1;
				rs2_valid  = 1'b1;
                src2_sel   = `SRC2_RS2;
				if (funct7 == 7'b0000001) begin

`ifdef ENABLE_MULDIV
                    rs_type = ( (funct3 == 3'b000) ||
                                (funct3 == 3'b001) ||
                                (funct3 == 3'b010) ||
                                (funct3 == 3'b011) )?
                                `RS_MUL : `RS_DIV;
`else
					ill_inst = 1'b1;
`endif

                end else begin
					case (funct3)
						3'b000  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_ADD;
							end else if (funct7 == 7'b0100000) begin
								alu_op   = `ALU_SUB;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b001  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLL;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b010  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLT;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b011  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLT;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b100  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_XOR;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b101  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SRL;
							end else if (funct7 == 7'b0100000) begin
								alu_op   = `ALU_SRA;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b110  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_OR;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b111  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_AND;
							end else begin
								ill_inst = 1'b1;
							end
						end
						default : ill_inst = 1'b1;
					endcase
				end
            end
            default : begin
                ill_inst = 1'b1;
            end
        endcase
    end


`ifdef ENABLE_MULDIV  
    always @(*) begin
        muldiv_op         = `MUL;
        muldiv_rs1_signed = 1'b0;
        muldiv_rs2_signed = 1'b0;
        muldiv_out_sel    = `OUT_LOW;
        case (funct3)
            3'b000 : begin
            end
            3'b001 : begin
                muldiv_rs1_signed = 1'b1;
                muldiv_rs2_signed = 1'b1;
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b010 : begin
                muldiv_rs1_signed = 1'b1;
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b011 : begin
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b100 : begin
                muldiv_op         = `DIV;
                muldiv_rs1_signed = 1'b1;
                muldiv_rs2_signed = 1'b1;
            end
            3'b101 : begin
                muldiv_op         = `DIV;
            end
            3'b110 : begin
                muldiv_op         = `REM;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel    = `OUT_REM;
            end
            3'b111 : begin
                muldiv_op         = `REM;
                muldiv_out_sel    = `OUT_REM;
            end
        endcase
    end
`endif

endmodule
module Decoder
(
    input      [31:0] inst,
    
	output     [4:0]  rd,
    output     [4:0]  rs1,
    output     [4:0]  rs2,
	output reg        rd_valid,
    output reg        rs1_valid,
    output reg        rs2_valid,
    
	output reg [2:0]  inst_type,
    output reg [1:0]  src1_sel,
    output reg [1:0]  src2_sel,
    output reg        ill_inst,
    output reg [3:0]  alu_op,
    output reg [2:0]  rs_type,

`ifdef ENABLE_MULDIV
	output reg [1:0]  muldiv_op,
    output reg        muldiv_rs1_signed,
    output reg        muldiv_rs2_signed,
    output reg [1:0]  muldiv_out_sel,
`endif

    output reg        dmem_valid,
    output reg [3:0]  dmem_wrstrb,
	output reg [3:0]  dmem_rdstrb
);

    wire [3:0]        srl_or_sra;
    wire [3:0]        add_or_sub;
    wire [2:0]        rs_type_md;
   
    wire [6:0]        opcode  = inst[6:0];
    wire [6:0]        funct7  = inst[31:25];
    wire [11:0]       funct12 = inst[31:20];
    wire [2:0]        funct3  = inst[14:12];
    reg  [3:0]        alu_op_arith;
   
    assign rd  = inst[11:7];
    assign rs1 = inst[19:15];
    assign rs2 = inst[24:20];
   
    always @(*) begin
        rd_valid    = 1'b0;
        rs1_valid   = 1'b1;
        rs2_valid   = 1'b0;

        inst_type    = `I_type;
        src1_sel    = `SRC1_RS1;
        src2_sel    = `SRC2_IMM;
        ill_inst    = 1'b0;
        alu_op      = `ALU_ADD;
        rs_type     = `RS_ALU;
		
        dmem_valid  = 1'b0;
        dmem_wrstrb = 4'b0;
		dmem_rdstrb = 4'b0;

        (* parallel_case, full_case *)
        case (opcode)
            7'b0110111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                inst_type  = `U_type;
                src1_sel  = `SRC1_ZERO;
			end
            7'b0010111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                inst_type  = `U_type;
				src1_sel  = `SRC1_PC;   
            end
            7'b1101111 : begin
                rd_valid  = 1'b1;
				rs1_valid = 1'b0;
                src1_sel  = `SRC1_PC;
                src2_sel  = `SRC2_FOUR;    
                rs_type   = `RS_JAL;
            end
            7'b1100111 : begin
                rd_valid  = 1'b1;
                src1_sel  = `SRC1_PC;
                src2_sel  = `SRC2_FOUR;
                ill_inst  = (funct3 != 0);
                rs_type   = `RS_JALR;
            end
            7'b1100011 : begin

				rs2_valid = 1'b1;
                src2_sel  = `SRC2_RS2;
				rs_type   = `RS_BRANCH;
                case (funct3)
                    3'b000  : alu_op   = `ALU_SEQ;
                    3'b001  : alu_op   = `ALU_SNE;
                    3'b100  : alu_op   = `ALU_SLT;
                    3'b101  : alu_op   = `ALU_SGE;
					3'b110  : alu_op   = `ALU_SLTU;
                    3'b111  : alu_op   = `ALU_SGEU;
                    default : ill_inst = 1'b1;
                endcase    
            end
            7'b0000011 : begin
                dmem_valid = 1'b1;
                rd_valid   = 1'b1;
                rs_type    = `RS_LDST;
				(* full_case *)
				case (funct3)
				    3'b000: dmem_rdstrb = 4'b0001;
					3'b001: dmem_rdstrb = 4'b0011;
					3'b010: dmem_rdstrb = 4'b1111;
				endcase
            end
            7'b0100011 : begin
                rs2_valid  = 1'b1;
                inst_type   = `S_type;
                dmem_valid = 1'b1;
                rs_type    = `RS_LDST;
				(* full_case *)
				case (funct3)
				    3'b000: dmem_wrstrb = 4'b0001;
					3'b001: dmem_wrstrb = 4'b0011;
					3'b010: dmem_wrstrb = 4'b1111;
				endcase
            end
            7'b0010011 : begin
                rd_valid   = 1'b1;
                case (funct3)
                    3'b000  : alu_op   = `ALU_ADD;
                    3'b010  : alu_op   = `ALU_SLT;
                    3'b011  : alu_op   = `ALU_SLT;
                    3'b100  : alu_op   = `ALU_XOR;
					3'b110  : alu_op   = `ALU_OR;
                    3'b111  : alu_op   = `ALU_AND;
					3'b001  : begin
					      if (funct7 == 7'b0000000) begin
						      alu_op   = `ALU_SLL;
						  end else begin
						      ill_inst = 1'b1;
						  end
					end
					3'b101 : begin
					      if (funct7 == 7'b0000000) begin
						      alu_op   = `ALU_SRL;
						  end else if (funct7 == 7'b0100000) begin
						      alu_op   = `ALU_SRA;
					      end else
						      ill_inst = 1'b1;
						  end
                    default : ill_inst = 1'b1;
                endcase  
            end
            7'b0110011 : begin
                rd_valid   = 1'b1;
				rs2_valid  = 1'b1;
                src2_sel   = `SRC2_RS2;
				if (funct7 == 7'b0000001) begin

`ifdef ENABLE_MULDIV
                    rs_type = ( (funct3 == 3'b000) ||
                                (funct3 == 3'b001) ||
                                (funct3 == 3'b010) ||
                                (funct3 == 3'b011) )?
                                `RS_MUL : `RS_DIV;
`else
					ill_inst = 1'b1;
`endif

                end else begin
					case (funct3)
						3'b000  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_ADD;
							end else if (funct7 == 7'b0100000) begin
								alu_op   = `ALU_SUB;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b001  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLL;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b010  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLT;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b011  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SLT;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b100  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_XOR;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b101  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_SRL;
							end else if (funct7 == 7'b0100000) begin
								alu_op   = `ALU_SRA;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b110  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_OR;
							end else begin
								ill_inst = 1'b1;
							end
						end
						3'b111  : begin
							if (funct7 == 7'b0000000) begin
								alu_op   = `ALU_AND;
							end else begin
								ill_inst = 1'b1;
							end
						end
						default : ill_inst = 1'b1;
					endcase
				end
            end
            default : begin
                ill_inst = 1'b1;
            end
        endcase
    end


`ifdef ENABLE_MULDIV  
    always @(*) begin
        muldiv_op         = `MUL;
        muldiv_rs1_signed = 1'b0;
        muldiv_rs2_signed = 1'b0;
        muldiv_out_sel    = `OUT_LOW;
        case (funct3)
            3'b000 : begin
            end
            3'b001 : begin
                muldiv_rs1_signed = 1'b1;
                muldiv_rs2_signed = 1'b1;
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b010 : begin
                muldiv_rs1_signed = 1'b1;
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b011 : begin
                muldiv_out_sel    = `OUT_HIGH;
            end
            3'b100 : begin
                muldiv_op         = `DIV;
                muldiv_rs1_signed = 1'b1;
                muldiv_rs2_signed = 1'b1;
            end
            3'b101 : begin
                muldiv_op         = `DIV;
            end
            3'b110 : begin
                muldiv_op         = `REM;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel    = `OUT_REM;
            end
            3'b111 : begin
                muldiv_op         = `REM;
                muldiv_out_sel    = `OUT_REM;
            end
        endcase
    end
`endif

endmodule