data/full_repos/permissive/458134463/Modules/adder_32bit.v
1: b"%Error: data/full_repos/permissive/458134463/Modules/adder_32bit.v:21: Cannot find file containing module: 'adder_4bit'\nadder_4bit add_1(value1[3:0]  , value2[3:0]  , sum[3:0],   c_4_7  ,   carry_in, temp_overflow),\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/adder_4bit\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/adder_4bit.v\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/adder_4bit.sv\n             adder_4bit\n             adder_4bit.v\n             adder_4bit.sv\n             obj_dir/adder_4bit\n             obj_dir/adder_4bit.v\n             obj_dir/adder_4bit.sv\n%Error: Exiting due to 1 error(s)\n"
module adder_32bit(value1, value2, sum, carry_out, carry_in, overflow);

input [31:0] value1;
input [31:0] value2;
input carry_in;

output [31:0] sum;
output carry_out;
output overflow;

wire c_4_7;
wire c_8_11;
wire c_12_15;
wire c_16_19;
wire c_20_23;
wire c_24_27;
wire c_28_31;
wire temp_overflow;


adder_4bit add_1(value1[3:0]  , value2[3:0]  , sum[3:0],   c_4_7  ,   carry_in, temp_overflow),
			  add_2(value1[7:4]  , value2[7:4]  , sum[7:4],   c_8_11 ,   c_4_7   , temp_overflow),
			  add_3(value1[11:8] , value2[11:8] , sum[11:8],  c_12_15,   c_8_11  , temp_overflow),
			  add_4(value1[15:12], value2[15:12], sum[15:12], c_16_19,   c_12_15 , temp_overflow),
			  add_5(value1[19:16], value2[19:16], sum[19:16], c_20_23,   c_16_19 , temp_overflow),
			  add_6(value1[23:20], value2[23:20], sum[23:20], c_24_27,   c_20_23 , temp_overflow),
			  add_7(value1[27:24], value2[27:24], sum[27:24], c_28_31,   c_24_27 , temp_overflow),
			  add_8(value1[31:28], value2[31:28], sum[31:28], carry_out, c_28_31 , overflow);

endmodule
module adder_32bit(value1, value2, sum, carry_out, carry_in, overflow);


input [31:0] value1;
input [31:0] value2;
input carry_in;

output [31:0] sum;
output carry_out;
output overflow;

wire c_4_7;
wire c_8_11;
wire c_12_15;
wire c_16_19;
wire c_20_23;
wire c_24_27;
wire c_28_31;
wire temp_overflow;


adder_4bit add_1(value1[3:0]  , value2[3:0]  , sum[3:0],   c_4_7  ,   carry_in, temp_overflow),
			  add_2(value1[7:4]  , value2[7:4]  , sum[7:4],   c_8_11 ,   c_4_7   , temp_overflow),
			  add_3(value1[11:8] , value2[11:8] , sum[11:8],  c_12_15,   c_8_11  , temp_overflow),
			  add_4(value1[15:12], value2[15:12], sum[15:12], c_16_19,   c_12_15 , temp_overflow),
			  add_5(value1[19:16], value2[19:16], sum[19:16], c_20_23,   c_16_19 , temp_overflow),
			  add_6(value1[23:20], value2[23:20], sum[23:20], c_24_27,   c_20_23 , temp_overflow),
			  add_7(value1[27:24], value2[27:24], sum[27:24], c_28_31,   c_24_27 , temp_overflow),
			  add_8(value1[31:28], value2[31:28], sum[31:28], carry_out, c_28_31 , overflow);

endmodule