data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v:11: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                                              : ... In instance opt_share_test\n      0: res = a + b;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v:11: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 11 bits.\n                                                                                              : ... In instance opt_share_test\n      0: res = a + b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v:12: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                                              : ... In instance opt_share_test\n      1: res = a - b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v:12: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 11 bits.\n                                                                                              : ... In instance opt_share_test\n      1: res = a - b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_extend.v:13: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                                              : ... In instance opt_share_test\n      2: res = a + c;\n                 ^\n%Error: Exiting due to 5 warning(s)\n'
module opt_share_test(
  input signed [7:0]       a,
  input signed [10:0]      b,
  input signed [15:0]      c,
  input [1:0]              sel,
  output reg signed [15:0] res
  );

  always @* begin
    case(sel)
      0: res = a + b;
      1: res = a - b;
      2: res = a + c;
      default: res = 16'bx;
    endcase
  end

endmodule
module opt_share_test(
  input signed [7:0]       a,
  input signed [10:0]      b,
  input signed [15:0]      c,
  input [1:0]              sel,
  output reg signed [15:0] res
  );


  always @* begin
    case(sel)
      0: res = a + b;
      1: res = a - b;
      2: res = a + c;
      default: res = 16'bx;
    endcase
  end

endmodule