data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v:84: Operator XOR expects 2 bits on the RHS, but RHS\'s VARREF \'temp3\' generates 1 bits.\n                                                                                                                                    : ... In instance bm_dag3_lpm_log_mod.top_b\n temp2 <= seventh | eight ^ temp3;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module b(clock,
		seventh,
		eight,
		out3);

input	clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0]    out3;
reg [`BITS-1:0] out3;

c myb_c(clock, seventh[0], eight[0], temp3);

always @(posedge clock)
begin
	temp2 <= seventh | eight ^ temp3;
	out3 <= seventh ^ temp2;
end

endmodule
module b(clock,
		seventh,
		eight,
		out3);


input	clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0]    out3;
reg [`BITS-1:0] out3;

c myb_c(clock, seventh[0], eight[0], temp3);

always @(posedge clock)
begin
	temp2 <= seventh | eight ^ temp3;
	out3 <= seventh ^ temp2;
end

endmodule