data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v:35: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #30 hit <= ~hit;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #15 input1 <= input1 + 32\'b00000000000000000000000000000100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/ProgramCounter_TEST.v:40: Cannot find file containing module: \'ProgramCounter32bits\'\n ProgramCounter32bits uut (\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ProgramCounter32bits\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ProgramCounter32bits.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ProgramCounter32bits.sv\n             ProgramCounter32bits\n             ProgramCounter32bits.v\n             ProgramCounter32bits.sv\n             obj_dir/ProgramCounter32bits\n             obj_dir/ProgramCounter32bits.v\n             obj_dir/ProgramCounter32bits.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ProgramCounter_TEST;


	reg [31:0] input1;
	reg clock;
	reg hit;


	wire [31:0] out;

	always #20 clock <= ~clock;
	always #30 hit <= ~hit;
	always #15 input1 <= input1 + 32'b00000000000000000000000000000100;


	ProgramCounter32bits uut (
		.input1(input1), 
		.clock(clock),
		.hit(hit),
		.out(out)
	);

	initial begin


		input1 <= 32'h000000;
		clock <= 0;
		hit <= 0;
		
		

		#1000 $finish;
        


	end
      
endmodule
module ProgramCounter_TEST;



	reg [31:0] input1;
	reg clock;
	reg hit;


	wire [31:0] out;

	always #20 clock <= ~clock;
	always #30 hit <= ~hit;
	always #15 input1 <= input1 + 32'b00000000000000000000000000000100;


	ProgramCounter32bits uut (
		.input1(input1), 
		.clock(clock),
		.hit(hit),
		.out(out)
	);

	initial begin


		input1 <= 32'h000000;
		clock <= 0;
		hit <= 0;
		
		

		#1000 $finish;
        


	end
      
endmodule