data/full_repos/permissive/493019833/code/db/macro_cells.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/493019833/code/db/macro_cells.v:11: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'ADD_UNSIGNED\'\nmodule ADD_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'ADD_SIGNED\'\nmodule ADD_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'SUB_UNSIGNED\'\nmodule SUB_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'SUB_SIGNED\'\nmodule SUB_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'MUL_UNSIGNED\'\nmodule MUL_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'MUL_SIGNED\'\nmodule MUL_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'DIV_UNSIGNED\'\nmodule DIV_UNSIGNED(y, num, den);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'DIV_SIGNED\'\nmodule DIV_SIGNED(y, num, den);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'REM_UNSIGNED\'\nmodule REM_UNSIGNED(y, num, den);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'REM_SIGNED\'\nmodule REM_SIGNED(y, num, den);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'LT_UNSIGNED\'\nmodule LT_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~\n                                                                                : ... Top module \'LT_SIGNED\'\nmodule LT_SIGNED(y, a, b);\n       ^~~~~~~~~\n                                                                                : ... Top module \'LEQ_UNSIGNED\'\nmodule LEQ_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'LEQ_SIGNED\'\nmodule LEQ_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'GT_UNSIGNED\'\nmodule GT_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~\n                                                                                : ... Top module \'GT_SIGNED\'\nmodule GT_SIGNED(y, a, b);\n       ^~~~~~~~~\n                                                                                : ... Top module \'GEQ_UNSIGNED\'\nmodule GEQ_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'GEQ_SIGNED\'\nmodule GEQ_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'EQ_UNSIGNED\'\nmodule EQ_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~\n                                                                                : ... Top module \'EQ_SIGNED\'\nmodule EQ_SIGNED(y, a, b);\n       ^~~~~~~~~\n                                                                                : ... Top module \'NEQ_UNSIGNED\'\nmodule NEQ_UNSIGNED(y, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'NEQ_SIGNED\'\nmodule NEQ_SIGNED(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'PAD_UNSIGNED\'\nmodule PAD_UNSIGNED(y, in);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'PAD_SIGNED\'\nmodule PAD_SIGNED(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'ASUINT\'\nmodule ASUINT(y, in);\n       ^~~~~~\n                                                                                : ... Top module \'ASSINT\'\nmodule ASSINT(y, in);\n       ^~~~~~\n                                                                                : ... Top module \'SHL_UNSIGNED\'\nmodule SHL_UNSIGNED(y, in);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'SHL_SIGNED\'\nmodule SHL_SIGNED(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'SHR_UNSIGNED\'\nmodule SHR_UNSIGNED(y, in);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'SHR_SIGNED\'\nmodule SHR_SIGNED(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'DSHL_UNSIGNED\'\nmodule DSHL_UNSIGNED(y, in, n);\n       ^~~~~~~~~~~~~\n                                                                                : ... Top module \'DSHL_SIGNED\'\nmodule DSHL_SIGNED(y, in, n);\n       ^~~~~~~~~~~\n                                                                                : ... Top module \'DSHR_UNSIGNED\'\nmodule DSHR_UNSIGNED(y, in, n);\n       ^~~~~~~~~~~~~\n                                                                                : ... Top module \'DSHR_SIGNED\'\nmodule DSHR_SIGNED(y, in, n);\n       ^~~~~~~~~~~\n                                                                                : ... Top module \'CVT_UNSIGNED\'\nmodule CVT_UNSIGNED(y, in);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'CVT_SIGNED\'\nmodule CVT_SIGNED(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'NEG_UNSIGNED\'\nmodule NEG_UNSIGNED(y, in);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'NEG_SIGNED\'\nmodule NEG_SIGNED(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'NEG_UNSIGNED_ST\'\nmodule NEG_UNSIGNED_ST(y, in);\n       ^~~~~~~~~~~~~~~\n                                                                                : ... Top module \'NEG_SIGNED_ST\'\nmodule NEG_SIGNED_ST(y, in);\n       ^~~~~~~~~~~~~\n                                                                                : ... Top module \'BITWISENOT\'\nmodule BITWISENOT(y, in);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'BITWISEAND\'\nmodule BITWISEAND(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'BITWISEOR\'\nmodule BITWISEOR(y, a, b);\n       ^~~~~~~~~\n                                                                                : ... Top module \'BITWISEXOR\'\nmodule BITWISEXOR(y, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'ANDR\'\nmodule ANDR(y, in);\n       ^~~~\n                                                                                : ... Top module \'ORR\'\nmodule ORR(y, in);\n       ^~~\n                                                                                : ... Top module \'XORR\'\nmodule XORR(y, in);\n       ^~~~\n                                                                                : ... Top module \'CAT\'\nmodule CAT(y, a, b);\n       ^~~\n                                                                                : ... Top module \'BITS\'\nmodule BITS(y, in);\n       ^~~~\n                                                                                : ... Top module \'HEAD\'\nmodule HEAD(y, in);\n       ^~~~\n                                                                                : ... Top module \'TAIL\'\nmodule TAIL(y, in);\n       ^~~~\n                                                                                : ... Top module \'DFF_POSCLK\'\nmodule DFF_POSCLK(q, d, clk);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'DFF_NEGCLK\'\nmodule DFF_NEGCLK(q, d, clk);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'DFF_POSCLK_POSASYNCRST\'\nmodule DFF_POSCLK_POSASYNCRST(q, d, rst, rstval, clk);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'DFF_POSCLK_NEGASYNCRST\'\nmodule DFF_POSCLK_NEGASYNCRST(q, d, rst, rstval, clk);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'DFF_NEGCLK_POSASYNCRST\'\nmodule DFF_NEGCLK_POSASYNCRST(q, d, rst, rstval, clk);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'DFF_NEGCLK_NEGASYNCRST\'\nmodule DFF_NEGCLK_NEGASYNCRST(q, d, rst, rstval, clk);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'MUX_UNSIGNED\'\nmodule MUX_UNSIGNED(y, sel, a, b);\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'MUX_SIGNED\'\nmodule MUX_SIGNED(y, sel, a, b);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'ROMMEM\'\nmodule ROMMEM(read_data, read_clk, read_en, read_addr);\n       ^~~~~~\n                                                                                : ... Top module \'RAMMEM\'\nmodule RAMMEM(read_data, read_clk, read_en, read_addr, write_clk, write_en, write_mask, write_addr, write_data);\n       ^~~~~~\n                                                                                : ... Top module \'MRROMMEM\'\nmodule MRROMMEM(read_datas, read_clks, read_ens, read_addrs);\n       ^~~~~~~~\n                                                                                : ... Top module \'MRMWMEM\'\nmodule MRMWMEM(read_datas, read_clks, read_ens, read_addrs, write_clks, write_ens, write_masks, write_addrs, write_datas);\n       ^~~~~~~\n%Error: data/full_repos/permissive/493019833/code/db/macro_cells.v:660: Expecting expression to be constant, but variable isn\'t const: \'read_ens\'\n                                                                      : ... In instance MRMWMEM\n                if (read_ens[gv_k]) begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/493019833/code/db/macro_cells.v:660: Generate If condition must evaluate to constant\n                                                                      : ... In instance MRMWMEM\n                if (read_ens[gv_k]) begin\n                            ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module MUX_UNSIGNED(y, sel, a, b);
    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a; 
    input [width-1:0] b; 
    assign y = sel ? a : b;
endmodule
module MUX_UNSIGNED(y, sel, a, b);

    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a; 
    input [width-1:0] b; 
    assign y = sel ? a : b;
endmodule