data/full_repos/permissive/492462267/martianmips.v
1: b'%Error: data/full_repos/permissive/492462267/martianmips.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/martianmips.v:17: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   rom_data_i,      \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegDataBus]   rom_data_i,      \n                            ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:18: Define or directive not defined: \'`RegDataBus\'\n    output  wire[`RegDataBus]   rom_addr_o,      \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:23: Define or directive not defined: \'`InstAddrBus\'\nwire[`InstAddrBus]  ifid_pc;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstAddrBus]  ifid_pc;\n                 ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:27: Define or directive not defined: \'`InstAddrBus\'\nwire[`InstAddrBus]  id_pc;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstAddrBus]  id_pc;\n                 ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:28: Define or directive not defined: \'`InstBus\'\nwire[`InstBus]      id_inst;\n     ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstBus]      id_inst;\n             ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:29: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   id_rdata1;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   id_rdata1;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:30: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   id_rdata2;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   id_rdata2;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:35: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]   regfile_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]   regfile_waddr;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:36: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   regfile_wdata;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   regfile_wdata;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:38: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]   regfile_raddr1;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]   regfile_raddr1;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:40: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]   regfile_raddr2;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]   regfile_raddr2;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:43: Define or directive not defined: \'`AluOpBus\'\nwire[`AluOpBus]     idex_aluop;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`AluOpBus]     idex_aluop;\n              ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:44: Define or directive not defined: \'`AluSelBus\'\nwire[`AluSelBus]    idex_alusel;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`AluSelBus]    idex_alusel;\n               ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:45: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   idex_data1;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   idex_data1;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:46: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   idex_data2;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   idex_data2;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:47: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]   idex_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]   idex_waddr;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:52: Define or directive not defined: \'`AluOpBus\'\nwire[`AluOpBus]    ex_aluop;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`AluOpBus]    ex_aluop;\n              ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:53: Define or directive not defined: \'`AluSelBus\'\nwire[`AluSelBus]   ex_alusel;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`AluSelBus]   ex_alusel;\n               ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:54: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]  ex_data1;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]  ex_data1;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:55: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]  ex_data2;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]  ex_data2;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:56: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]  ex_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]  ex_waddr;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:58: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]  ex_hi_i;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]  ex_hi_i;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:59: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]  ex_lo_i;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]  ex_lo_i;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:62: Define or directive not defined: \'`RegDataBus\'\nwire[`RegDataBus]   exmem_result;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegDataBus]   exmem_result;\n                ^\n%Error: data/full_repos/permissive/492462267/martianmips.v:64: Define or directive not defined: \'`RegAddrBus\'\nwire[`RegAddrBus]   exmem_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/martianmips.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`RegAddrBus]   exmem_waddr;\n                ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module martianmips (
    input   wire    clk,
    input   wire    rst,

    input   wire[`RegDataBus]   rom_data_i,
    output  wire[`RegDataBus]   rom_addr_o,
    output  wire                rom_ce_o
);


wire[`InstAddrBus]  ifid_pc;



wire[`InstAddrBus]  id_pc;
wire[`InstBus]      id_inst;
wire[`RegDataBus]   id_rdata1;
wire[`RegDataBus]   id_rdata2;



wire                regfile_we;
wire[`RegAddrBus]   regfile_waddr;
wire[`RegDataBus]   regfile_wdata;
wire                regfile_re1;
wire[`RegAddrBus]   regfile_raddr1;
wire                regfile_re2;
wire[`RegAddrBus]   regfile_raddr2;


wire[`AluOpBus]     idex_aluop;
wire[`AluSelBus]    idex_alusel;
wire[`RegDataBus]   idex_data1;
wire[`RegDataBus]   idex_data2;
wire[`RegAddrBus]   idex_waddr;
wire                idex_we;



wire[`AluOpBus]    ex_aluop;
wire[`AluSelBus]   ex_alusel;
wire[`RegDataBus]  ex_data1;
wire[`RegDataBus]  ex_data2;
wire[`RegAddrBus]  ex_waddr;
wire               ex_we;
wire[`RegDataBus]  ex_hi_i;
wire[`RegDataBus]  ex_lo_i;


wire[`RegDataBus]   exmem_result;
wire                exmem_we;
wire[`RegAddrBus]   exmem_waddr;
wire[`RegDataBus]   exmem_ex_hi;
wire[`RegDataBus]   exmem_ex_lo;
wire                exmem_ex_whilo;



wire[`RegDataBus]   mem_result;
wire[`RegAddrBus]   mem_waddr;
wire                mem_we;
wire[`RegDataBus]   mem_hi_i;
wire[`RegDataBus]   mem_lo_i;
wire                mem_whilo_i;


wire                memwb_we;
wire[`RegAddrBus]   memwb_waddr;
wire[`RegDataBus]   memwb_result;
wire[`RegDataBus]   memwb_mem_hi;
wire[`RegDataBus]   memwb_mem_lo;
wire                memwb_mem_whilo;



wire hilo_we;
wire[`RegDataBus]   hilo_hi_i;
wire[`RegDataBus]   hilo_lo_i;


wire ctrl_stall_from_id;
wire ctrl_stall_from_ex;
wire[5:0] ctrl_stall;



ctrl ctrl0(
    .rst(rst),
    .stall_from_id(ctrl_stall_from_id),
    .stall_from_ex(ctrl_stall_from_ex),
    .stall(ctrl_stall)
);


pc_reg  pc_reg0(
    .clk(clk),
    .rst(rst),
    .ce(rom_ce_o),
    .pc(ifid_pc),
    .stall(ctrl_stall)
);


assign rom_addr_o = ifid_pc;



if_id if_id0(
    .clk(clk),
    .rst(rst),
    .if_pc(ifid_pc),
    .if_inst(rom_data_i),
    .id_pc(id_pc),       
    .id_inst(id_inst),
    .stall(ctrl_stall)
);


id id0(
    .rst(rst),
    .pc_i(id_pc),
    .inst_i(id_inst),


    .re1_o(regfile_re1),
    .re2_o(regfile_re2),
    .raddr1_o(regfile_raddr1),
    .raddr2_o(regfile_raddr2),
    .rdata1_i(id_rdata1),
    .rdata2_i(id_rdata2),
    


    .we_o(idex_we),
    .waddr_o(idex_waddr),


    .aluop_o(idex_aluop),
    .alusel_o(idex_alusel),
    .data1_o(idex_data1),
    .data2_o(idex_data2),


    .ex_we_i(exmem_we),
    .ex_waddr_i(exmem_waddr),
    .ex_wdata_i(exmem_result),


    .mem_we_i(memwb_we),
    .mem_waddr_i(memwb_waddr),
    .mem_wdata_i(memwb_result),

    .stallreq(ctrl_stall_from_id)
);







regfile regfile0(
    .clk(clk),
    .rst(rst),


    .we(regfile_we),
    .waddr(regfile_waddr),
    .wdata(regfile_wdata),


    .re1(regfile_re1),
    .raddr_1(regfile_raddr1),
    .rdata_1(id_rdata1),


    .re2(regfile_re2),
    .raddr_2(regfile_raddr2),
    .rdata_2(id_rdata2)

);



id_ex id_ex0(
    .clk(clk),
    .rst(rst),


    .id_aluop(idex_aluop),
    .id_alusel(idex_alusel),
    .id_data1(idex_data1),
    .id_data2(idex_data2),
    .id_waddr(idex_waddr),
    .id_we(idex_we),


    .ex_aluop(ex_aluop),
    .ex_alusel(ex_alusel),
    .ex_data1(ex_data1),
    .ex_data2(ex_data2),
    .ex_waddr(ex_waddr),
    .ex_we(ex_we),
    .stall(ctrl_stall)
);


ex ex0(
    .rst(rst),


    .aluop_i(ex_aluop),
    .alusel_i(ex_alusel),
    .data1_i(ex_data1),
    .data2_i(ex_data2),
    .waddr_i(ex_waddr),
    .we_i(ex_we),


    .we_o(exmem_we),
    .waddr_o(exmem_waddr),
    .result_o(exmem_result),


    .hi_i(ex_hi_i),
    .lo_i(ex_lo_i),
    .mem_whilo_i(memwb_mem_whilo),
    .mem_hi_i(memwb_mem_hi),
    .mem_lo_i(memwb_mem_lo),
    .wb_whilo_i(hilo_we),
    .wb_hi_i(hilo_hi_i),
    .wb_lo_i(hilo_lo_i),
    .whilo_o(exmem_ex_whilo),
    .hi_o(exmem_ex_hi),
    .lo_o(exmem_ex_lo),

    .stallreq(ctrl_stall_from_ex)
);



ex_mem ex_mem0(
    .clk(clk),
    .rst(rst),


    .ex_result(exmem_result),
    .ex_we(exmem_we),
    .ex_waddr(exmem_waddr),
    .ex_hi(exmem_ex_hi),
    .ex_lo(exmem_ex_lo),
    .ex_whilo(exmem_ex_whilo),


    .mem_result(mem_result),
    .mem_we(mem_we),
    .mem_waddr(mem_waddr),
    .mem_hi(mem_hi_i),
    .mem_lo(mem_lo_i),
    .mem_whilo(mem_whilo_i),

    .stall(ctrl_stall)
);



mem mem0(
    .rst(rst),


    .result_i(mem_result),
    .waddr_i(mem_waddr),
    .we_i(mem_we),
    .hi_i(mem_hi_i),
    .lo_i(mem_lo_i),
    .whilo_i(mem_whilo_i),


    .result_o(memwb_result),
    .waddr_o(memwb_waddr),
    .we_o(memwb_we),
    .hi_o(memwb_mem_hi),
    .lo_o(memwb_mem_lo),
    .whilo_o(memwb_mem_whilo)
);



mem_wb mem_wb0(
    .clk(clk),
    .rst(rst),


    .mem_we(memwb_we),
    .mem_waddr(memwb_waddr),
    .mem_result(memwb_result),
    .mem_hi(memwb_mem_hi),
    .mem_lo(memwb_mem_lo),
    .mem_whilo(memwb_mem_whilo),


    .wb_we(regfile_we),
    .wb_waddr(regfile_waddr),
    .wb_result(regfile_wdata),
    .wb_hi(hilo_hi_i),
    .wb_lo(hilo_lo_i),
    .wb_whilo(hilo_we),
    
    .stall(ctrl_stall)
);



hilo_reg hilo_reg0(
    .clk(clk),
    .rst(rst),
    .we(hilo_we),
    .hi_i(hilo_hi_i),
    .lo_i(hilo_lo_i),
    .hi_o(ex_hi_i),
    .lo_o(ex_lo_i)
);

endmodule
module martianmips (
    input   wire    clk,
    input   wire    rst,

    input   wire[`RegDataBus]   rom_data_i,
    output  wire[`RegDataBus]   rom_addr_o,
    output  wire                rom_ce_o
);



wire[`InstAddrBus]  ifid_pc;



wire[`InstAddrBus]  id_pc;
wire[`InstBus]      id_inst;
wire[`RegDataBus]   id_rdata1;
wire[`RegDataBus]   id_rdata2;



wire                regfile_we;
wire[`RegAddrBus]   regfile_waddr;
wire[`RegDataBus]   regfile_wdata;
wire                regfile_re1;
wire[`RegAddrBus]   regfile_raddr1;
wire                regfile_re2;
wire[`RegAddrBus]   regfile_raddr2;


wire[`AluOpBus]     idex_aluop;
wire[`AluSelBus]    idex_alusel;
wire[`RegDataBus]   idex_data1;
wire[`RegDataBus]   idex_data2;
wire[`RegAddrBus]   idex_waddr;
wire                idex_we;



wire[`AluOpBus]    ex_aluop;
wire[`AluSelBus]   ex_alusel;
wire[`RegDataBus]  ex_data1;
wire[`RegDataBus]  ex_data2;
wire[`RegAddrBus]  ex_waddr;
wire               ex_we;
wire[`RegDataBus]  ex_hi_i;
wire[`RegDataBus]  ex_lo_i;


wire[`RegDataBus]   exmem_result;
wire                exmem_we;
wire[`RegAddrBus]   exmem_waddr;
wire[`RegDataBus]   exmem_ex_hi;
wire[`RegDataBus]   exmem_ex_lo;
wire                exmem_ex_whilo;



wire[`RegDataBus]   mem_result;
wire[`RegAddrBus]   mem_waddr;
wire                mem_we;
wire[`RegDataBus]   mem_hi_i;
wire[`RegDataBus]   mem_lo_i;
wire                mem_whilo_i;


wire                memwb_we;
wire[`RegAddrBus]   memwb_waddr;
wire[`RegDataBus]   memwb_result;
wire[`RegDataBus]   memwb_mem_hi;
wire[`RegDataBus]   memwb_mem_lo;
wire                memwb_mem_whilo;



wire hilo_we;
wire[`RegDataBus]   hilo_hi_i;
wire[`RegDataBus]   hilo_lo_i;


wire ctrl_stall_from_id;
wire ctrl_stall_from_ex;
wire[5:0] ctrl_stall;



ctrl ctrl0(
    .rst(rst),
    .stall_from_id(ctrl_stall_from_id),
    .stall_from_ex(ctrl_stall_from_ex),
    .stall(ctrl_stall)
);


pc_reg  pc_reg0(
    .clk(clk),
    .rst(rst),
    .ce(rom_ce_o),
    .pc(ifid_pc),
    .stall(ctrl_stall)
);


assign rom_addr_o = ifid_pc;



if_id if_id0(
    .clk(clk),
    .rst(rst),
    .if_pc(ifid_pc),
    .if_inst(rom_data_i),
    .id_pc(id_pc),       
    .id_inst(id_inst),
    .stall(ctrl_stall)
);


id id0(
    .rst(rst),
    .pc_i(id_pc),
    .inst_i(id_inst),


    .re1_o(regfile_re1),
    .re2_o(regfile_re2),
    .raddr1_o(regfile_raddr1),
    .raddr2_o(regfile_raddr2),
    .rdata1_i(id_rdata1),
    .rdata2_i(id_rdata2),
    


    .we_o(idex_we),
    .waddr_o(idex_waddr),


    .aluop_o(idex_aluop),
    .alusel_o(idex_alusel),
    .data1_o(idex_data1),
    .data2_o(idex_data2),


    .ex_we_i(exmem_we),
    .ex_waddr_i(exmem_waddr),
    .ex_wdata_i(exmem_result),


    .mem_we_i(memwb_we),
    .mem_waddr_i(memwb_waddr),
    .mem_wdata_i(memwb_result),

    .stallreq(ctrl_stall_from_id)
);







regfile regfile0(
    .clk(clk),
    .rst(rst),


    .we(regfile_we),
    .waddr(regfile_waddr),
    .wdata(regfile_wdata),


    .re1(regfile_re1),
    .raddr_1(regfile_raddr1),
    .rdata_1(id_rdata1),


    .re2(regfile_re2),
    .raddr_2(regfile_raddr2),
    .rdata_2(id_rdata2)

);



id_ex id_ex0(
    .clk(clk),
    .rst(rst),


    .id_aluop(idex_aluop),
    .id_alusel(idex_alusel),
    .id_data1(idex_data1),
    .id_data2(idex_data2),
    .id_waddr(idex_waddr),
    .id_we(idex_we),


    .ex_aluop(ex_aluop),
    .ex_alusel(ex_alusel),
    .ex_data1(ex_data1),
    .ex_data2(ex_data2),
    .ex_waddr(ex_waddr),
    .ex_we(ex_we),
    .stall(ctrl_stall)
);


ex ex0(
    .rst(rst),


    .aluop_i(ex_aluop),
    .alusel_i(ex_alusel),
    .data1_i(ex_data1),
    .data2_i(ex_data2),
    .waddr_i(ex_waddr),
    .we_i(ex_we),


    .we_o(exmem_we),
    .waddr_o(exmem_waddr),
    .result_o(exmem_result),


    .hi_i(ex_hi_i),
    .lo_i(ex_lo_i),
    .mem_whilo_i(memwb_mem_whilo),
    .mem_hi_i(memwb_mem_hi),
    .mem_lo_i(memwb_mem_lo),
    .wb_whilo_i(hilo_we),
    .wb_hi_i(hilo_hi_i),
    .wb_lo_i(hilo_lo_i),
    .whilo_o(exmem_ex_whilo),
    .hi_o(exmem_ex_hi),
    .lo_o(exmem_ex_lo),

    .stallreq(ctrl_stall_from_ex)
);



ex_mem ex_mem0(
    .clk(clk),
    .rst(rst),


    .ex_result(exmem_result),
    .ex_we(exmem_we),
    .ex_waddr(exmem_waddr),
    .ex_hi(exmem_ex_hi),
    .ex_lo(exmem_ex_lo),
    .ex_whilo(exmem_ex_whilo),


    .mem_result(mem_result),
    .mem_we(mem_we),
    .mem_waddr(mem_waddr),
    .mem_hi(mem_hi_i),
    .mem_lo(mem_lo_i),
    .mem_whilo(mem_whilo_i),

    .stall(ctrl_stall)
);



mem mem0(
    .rst(rst),


    .result_i(mem_result),
    .waddr_i(mem_waddr),
    .we_i(mem_we),
    .hi_i(mem_hi_i),
    .lo_i(mem_lo_i),
    .whilo_i(mem_whilo_i),


    .result_o(memwb_result),
    .waddr_o(memwb_waddr),
    .we_o(memwb_we),
    .hi_o(memwb_mem_hi),
    .lo_o(memwb_mem_lo),
    .whilo_o(memwb_mem_whilo)
);



mem_wb mem_wb0(
    .clk(clk),
    .rst(rst),


    .mem_we(memwb_we),
    .mem_waddr(memwb_waddr),
    .mem_result(memwb_result),
    .mem_hi(memwb_mem_hi),
    .mem_lo(memwb_mem_lo),
    .mem_whilo(memwb_mem_whilo),


    .wb_we(regfile_we),
    .wb_waddr(regfile_waddr),
    .wb_result(regfile_wdata),
    .wb_hi(hilo_hi_i),
    .wb_lo(hilo_lo_i),
    .wb_whilo(hilo_we),
    
    .stall(ctrl_stall)
);



hilo_reg hilo_reg0(
    .clk(clk),
    .rst(rst),
    .we(hilo_we),
    .hi_i(hilo_hi_i),
    .lo_i(hilo_lo_i),
    .hi_o(ex_hi_i),
    .lo_o(ex_lo_i)
);

endmodule