data/full_repos/permissive/433122322/src/FSK.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433122322/src/FSK.v:14: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'N\' generates 1 bits.\n                                                                 : ... In instance FSK\n  address1 <= address1 + N + 1;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433122322/src/FSK.v:23: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'N\' generates 1 bits.\n                                                                 : ... In instance FSK\n  address2 <= address2 + N + 5;\n                       ^\n%Error: data/full_repos/permissive/433122322/src/FSK.v:30: Cannot find file containing module: \'sin_256\'\nsin_256 sin1(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256.v\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256.sv\n             sin_256\n             sin_256.v\n             sin_256.sv\n             obj_dir/sin_256\n             obj_dir/sin_256.v\n             obj_dir/sin_256.sv\n%Error: data/full_repos/permissive/433122322/src/FSK.v:37: Cannot find file containing module: \'sin_256\'\nsin_256 sin2(\n^~~~~~~\n%Error: data/full_repos/permissive/433122322/src/FSK.v:46: Cannot find file containing module: \'CLK\'\nCLK clk_div(\n^~~\n%Error: data/full_repos/permissive/433122322/src/FSK.v:52: Cannot find file containing module: \'MXL\'\nMXL mxl(\n^~~\n%Error: data/full_repos/permissive/433122322/src/FSK.v:57: Cannot find file containing module: \'choose_FSK\'\nchoose_FSK ch(\n^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module FSK(
	input clk, rst_n,
	input N,
	output [7: 0] dout_FSK
);


reg [7: 0] address1;
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address1 <= 0;
	else 
		address1 <= address1 + N + 1;
end

reg [7: 0] address2;
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address2 <= 0;
	else 
		address2 <= address2 + N + 5;
end


wire [7: 0] sin_wave1;
wire [7: 0] sin_wave2;

sin_256 sin1(
	.address(address1),
	.clock(clk),
	.q(sin_wave1)
);


sin_256 sin2(
	.address(address2),
	.clock(clk),
	.q(sin_wave2)
);



wire clk_out;
CLK clk_div(
	.clk(clk),
	.clk_out(clk_out)
);

wire mxl_out;
MXL mxl(
	.clk(clk_out),
	.out(mxl_out)
);

choose_FSK ch(
	.data_in1(sin_wave1),
	.data_in2(sin_wave2),
	.sel(mxl_out),
	.data_out(dout_FSK)
);

endmodule
module FSK(
	input clk, rst_n,
	input N,
	output [7: 0] dout_FSK
);



reg [7: 0] address1;
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address1 <= 0;
	else 
		address1 <= address1 + N + 1;
end

reg [7: 0] address2;
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address2 <= 0;
	else 
		address2 <= address2 + N + 5;
end


wire [7: 0] sin_wave1;
wire [7: 0] sin_wave2;

sin_256 sin1(
	.address(address1),
	.clock(clk),
	.q(sin_wave1)
);


sin_256 sin2(
	.address(address2),
	.clock(clk),
	.q(sin_wave2)
);



wire clk_out;
CLK clk_div(
	.clk(clk),
	.clk_out(clk_out)
);

wire mxl_out;
MXL mxl(
	.clk(clk_out),
	.out(mxl_out)
);

choose_FSK ch(
	.data_in1(sin_wave1),
	.data_in2(sin_wave2),
	.sel(mxl_out),
	.data_out(dout_FSK)
);

endmodule