data/full_repos/permissive/527249789/src/ICache.v
1: b"%Error: data/full_repos/permissive/527249789/src/ICache.v:78: Cannot find file containing module: 'tagv_ram'\ntagv_ram Tagv_ram0 (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/tagv_ram\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/tagv_ram.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/tagv_ram.sv\n             tagv_ram\n             tagv_ram.v\n             tagv_ram.sv\n             obj_dir/tagv_ram\n             obj_dir/tagv_ram.v\n             obj_dir/tagv_ram.sv\n%Error: data/full_repos/permissive/527249789/src/ICache.v:85: Cannot find file containing module: 'tagv_ram'\ntagv_ram Tagv_ram1 (\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:109: Cannot find file containing module: 'bank_ram'\nbank_ram Bank0_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way0[0]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:110: Cannot find file containing module: 'bank_ram'\nbank_ram Bank1_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way0[1]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:111: Cannot find file containing module: 'bank_ram'\nbank_ram Bank2_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way0[2]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:112: Cannot find file containing module: 'bank_ram'\nbank_ram Bank3_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way0[3]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:113: Cannot find file containing module: 'bank_ram'\nbank_ram Bank4_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way0[4]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:114: Cannot find file containing module: 'bank_ram'\nbank_ram Bank5_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way0[5]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:115: Cannot find file containing module: 'bank_ram'\nbank_ram Bank6_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way0[6]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:116: Cannot find file containing module: 'bank_ram'\nbank_ram Bank7_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way0[7]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:119: Cannot find file containing module: 'bank_ram'\nbank_ram Bank0_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way1[0]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:120: Cannot find file containing module: 'bank_ram'\nbank_ram Bank1_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way1[1]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:121: Cannot find file containing module: 'bank_ram'\nbank_ram Bank2_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way1[2]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:122: Cannot find file containing module: 'bank_ram'\nbank_ram Bank3_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way1[3]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:123: Cannot find file containing module: 'bank_ram'\nbank_ram Bank4_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way1[4]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:124: Cannot find file containing module: 'bank_ram'\nbank_ram Bank5_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way1[5]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:125: Cannot find file containing module: 'bank_ram'\nbank_ram Bank6_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way1[6]));\n^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ICache.v:126: Cannot find file containing module: 'bank_ram'\nbank_ram Bank7_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way1[7]));\n^~~~~~~~\n%Error: Exiting due to 18 error(s)\n"
module ICache (
    input   wire        clk, 
    input   wire        rst,


    input   wire        rreq_inst_cpu_i,
    input   wire[31 :0] vaddr_inst_cpu_i,
    input   wire[31 :0] paddr_inst_tlb_i,
    output  reg         valid_inst_cpu_o,
    output  wire        arready_inst_cpu_o,
    output  wire[31 :0] inst_cpu_o,
    output  wire        hit_inst_cpu_o,


    input   wire[255:0] inst_mem_i,
    input   wire        valid_mem_i,
    output  wire        ren_inst_mem_o,
    output  wire[31 :0] addr_inst_mem_o
    




);


reg [3:0]       current_state;
reg [3:0]       next_state;
localparam      IDLE = 4'h0,
                TAG_COMPARE = 4'h2,
                ALLOCATE = 4'h4,
                WRITE_BACK = 4'h8;



 wire [19:  0]  cache_tag    = paddr_inst_tlb_i[31:12];
 wire [ 6:  0]  cache_index  = vaddr_inst_cpu_i[11: 5];
 wire [ 4:  0]  cache_offset = vaddr_inst_cpu_i[ 4: 0];













wire [20:0] tagv_w0;
wire [20:0] tagv_w1;
wire [3: 0] wea_way0;
wire [3: 0] wea_way1;

tagv_ram Tagv_ram0 (
              .clka     (clk                ),
              .ena      (1                  ),
              .wea      (wea_way0           ),
              .addra    (cache_index        ),
              .dina     ({1'b1,cache_tag}   ),
              .douta    (tagv_w0)           );
tagv_ram Tagv_ram1 (
              .clka     (clk                ),
              .ena      (1                  ),
              .wea      (wea_way1           ),
              .addra    (cache_index        ),
              .dina     ({1'b1,cache_tag}   ),
              .douta    (tagv_w1)           );


wire    hit_way0   = (tagv_w0[19:0]==cache_tag)&&(tagv_w0[20]);
wire    hit_way1   = (tagv_w1[19:0]==cache_tag)&&(tagv_w1[20]);

wire    hit        = (current_state == TAG_COMPARE)&&(hit_way0||hit_way1);

assign  hit_inst_cpu_o = hit;








wire [31:0]cache_way0[0:7];
bank_ram Bank0_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way0[0]));
bank_ram Bank1_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way0[1]));
bank_ram Bank2_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way0[2]));
bank_ram Bank3_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way0[3]));
bank_ram Bank4_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way0[4]));
bank_ram Bank5_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way0[5]));
bank_ram Bank6_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way0[6]));
bank_ram Bank7_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way0[7]));

wire [31:0]cache_way1[0:7];
bank_ram Bank0_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way1[0]));
bank_ram Bank1_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way1[1]));
bank_ram Bank2_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way1[2]));
bank_ram Bank3_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way1[3]));
bank_ram Bank4_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way1[4]));
bank_ram Bank5_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way1[5]));
bank_ram Bank6_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way1[6]));
bank_ram Bank7_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way1[7]));












reg [127:0]LRU;
always@(posedge clk) begin
    if(!rst)    LRU <= 0;

    else if(valid_inst_cpu_o && hit_way0) begin

                LRU[cache_index] <= 1;
    end else if(valid_inst_cpu_o && hit_way1) begin
                LRU[cache_index] <= 0;
    end else    LRU <= LRU;
end




always@(posedge clk) begin
    if(!rst) begin
        current_state <= IDLE;
    end else begin
        current_state <= next_state;
    end
end



reg valid_from_mem;
always@(*) begin
    if(!rst)                            valid_from_mem = 0;
    else if(valid_mem_i==1)             valid_from_mem = 1;
    else if(current_state==WRITE_BACK)  valid_from_mem = 0;
end

always@(posedge clk) begin
    if(!rst) begin
        next_state <= IDLE;
    end else begin
        case(current_state) 

            IDLE: begin
                if(rreq_inst_cpu_i==1) next_state <= TAG_COMPARE;

            end


            TAG_COMPARE: begin
                if(hit) next_state <= IDLE;
                else next_state <= ALLOCATE;
            end


            ALLOCATE: begin
                if (valid_from_mem) next_state <= WRITE_BACK;

            end
            


            WRITE_BACK: begin
                next_state <= IDLE;
            end
            default: next_state <= next_state;
        endcase
    end
end






wire [31:0]inst_way0 = cache_way0[cache_offset[4:2]];
wire [31:0]inst_way1 = cache_way1[cache_offset[4:2]];


assign ren_inst_mem_o   = (current_state== ALLOCATE && ~hit && !valid_from_mem);
assign addr_inst_mem_o  = paddr_inst_tlb_i;

reg [255:0]inst_from_mem;
always@(posedge clk) begin
    if(!rst)inst_from_mem <= 0;
    else if(current_state==ALLOCATE) 
            inst_from_mem <= inst_mem_i;
    else    inst_from_mem <= inst_from_mem;
end
assign wea_way0=(current_state==WRITE_BACK && LRU[cache_index]==0)?4'hf:4'h0;
assign wea_way1=(current_state==WRITE_BACK && LRU[cache_index]==1)?4'hf:4'h0;


assign inst_cpu_o = (current_state==TAG_COMPARE && hit_way0)?inst_way0:
                    (current_state==TAG_COMPARE && hit_way1)?inst_way1:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h0)?inst_from_mem[32*1-1:32*0]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h1)?inst_from_mem[32*2-1:32*1]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h2)?inst_from_mem[32*3-1:32*2]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h3)?inst_from_mem[32*4-1:32*3]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h4)?inst_from_mem[32*5-1:32*4]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h5)?inst_from_mem[32*6-1:32*5]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h6)?inst_from_mem[32*7-1:32*6]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h7)?inst_from_mem[32*8-1:32*7]:0;

reg do_req;
always@(posedge clk) begin
    if(!rst)    do_req <= 1'b0;
    else if(valid_inst_cpu_o&&current_state==IDLE)
                do_req <= 1'b0;
    else if(rreq_inst_cpu_i==1&&!do_req)
                do_req <= 1'b1;
end
always@(posedge clk) begin
    if(!rst) valid_inst_cpu_o <= 0;
    else     valid_inst_cpu_o <= (current_state==TAG_COMPARE&&do_req) && hit ? 1 :
                                 (current_state==WRITE_BACK&&do_req)         ? 1 : 0;
end



assign arready_inst_cpu_o = !do_req;

endmodule
module ICache (
    input   wire        clk, 
    input   wire        rst,


    input   wire        rreq_inst_cpu_i,
    input   wire[31 :0] vaddr_inst_cpu_i,
    input   wire[31 :0] paddr_inst_tlb_i,
    output  reg         valid_inst_cpu_o,
    output  wire        arready_inst_cpu_o,
    output  wire[31 :0] inst_cpu_o,
    output  wire        hit_inst_cpu_o,


    input   wire[255:0] inst_mem_i,
    input   wire        valid_mem_i,
    output  wire        ren_inst_mem_o,
    output  wire[31 :0] addr_inst_mem_o
    




);



reg [3:0]       current_state;
reg [3:0]       next_state;
localparam      IDLE = 4'h0,
                TAG_COMPARE = 4'h2,
                ALLOCATE = 4'h4,
                WRITE_BACK = 4'h8;



 wire [19:  0]  cache_tag    = paddr_inst_tlb_i[31:12];
 wire [ 6:  0]  cache_index  = vaddr_inst_cpu_i[11: 5];
 wire [ 4:  0]  cache_offset = vaddr_inst_cpu_i[ 4: 0];













wire [20:0] tagv_w0;
wire [20:0] tagv_w1;
wire [3: 0] wea_way0;
wire [3: 0] wea_way1;

tagv_ram Tagv_ram0 (
              .clka     (clk                ),
              .ena      (1                  ),
              .wea      (wea_way0           ),
              .addra    (cache_index        ),
              .dina     ({1'b1,cache_tag}   ),
              .douta    (tagv_w0)           );
tagv_ram Tagv_ram1 (
              .clka     (clk                ),
              .ena      (1                  ),
              .wea      (wea_way1           ),
              .addra    (cache_index        ),
              .dina     ({1'b1,cache_tag}   ),
              .douta    (tagv_w1)           );


wire    hit_way0   = (tagv_w0[19:0]==cache_tag)&&(tagv_w0[20]);
wire    hit_way1   = (tagv_w1[19:0]==cache_tag)&&(tagv_w1[20]);

wire    hit        = (current_state == TAG_COMPARE)&&(hit_way0||hit_way1);

assign  hit_inst_cpu_o = hit;








wire [31:0]cache_way0[0:7];
bank_ram Bank0_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way0[0]));
bank_ram Bank1_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way0[1]));
bank_ram Bank2_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way0[2]));
bank_ram Bank3_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way0[3]));
bank_ram Bank4_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way0[4]));
bank_ram Bank5_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way0[5]));
bank_ram Bank6_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way0[6]));
bank_ram Bank7_way0(.clka(clk),.ena(1),.wea(wea_way0),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way0[7]));

wire [31:0]cache_way1[0:7];
bank_ram Bank0_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*1-1:32*0]),.douta(cache_way1[0]));
bank_ram Bank1_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*2-1:32*1]),.douta(cache_way1[1]));
bank_ram Bank2_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*3-1:32*2]),.douta(cache_way1[2]));
bank_ram Bank3_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*4-1:32*3]),.douta(cache_way1[3]));
bank_ram Bank4_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*5-1:32*4]),.douta(cache_way1[4]));
bank_ram Bank5_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*6-1:32*5]),.douta(cache_way1[5]));
bank_ram Bank6_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*7-1:32*6]),.douta(cache_way1[6]));
bank_ram Bank7_way1(.clka(clk),.ena(1),.wea(wea_way1),.addra(cache_index),.dina(inst_from_mem[32*8-1:32*7]),.douta(cache_way1[7]));












reg [127:0]LRU;
always@(posedge clk) begin
    if(!rst)    LRU <= 0;

    else if(valid_inst_cpu_o && hit_way0) begin

                LRU[cache_index] <= 1;
    end else if(valid_inst_cpu_o && hit_way1) begin
                LRU[cache_index] <= 0;
    end else    LRU <= LRU;
end




always@(posedge clk) begin
    if(!rst) begin
        current_state <= IDLE;
    end else begin
        current_state <= next_state;
    end
end



reg valid_from_mem;
always@(*) begin
    if(!rst)                            valid_from_mem = 0;
    else if(valid_mem_i==1)             valid_from_mem = 1;
    else if(current_state==WRITE_BACK)  valid_from_mem = 0;
end

always@(posedge clk) begin
    if(!rst) begin
        next_state <= IDLE;
    end else begin
        case(current_state) 

            IDLE: begin
                if(rreq_inst_cpu_i==1) next_state <= TAG_COMPARE;

            end


            TAG_COMPARE: begin
                if(hit) next_state <= IDLE;
                else next_state <= ALLOCATE;
            end


            ALLOCATE: begin
                if (valid_from_mem) next_state <= WRITE_BACK;

            end
            


            WRITE_BACK: begin
                next_state <= IDLE;
            end
            default: next_state <= next_state;
        endcase
    end
end






wire [31:0]inst_way0 = cache_way0[cache_offset[4:2]];
wire [31:0]inst_way1 = cache_way1[cache_offset[4:2]];


assign ren_inst_mem_o   = (current_state== ALLOCATE && ~hit && !valid_from_mem);
assign addr_inst_mem_o  = paddr_inst_tlb_i;

reg [255:0]inst_from_mem;
always@(posedge clk) begin
    if(!rst)inst_from_mem <= 0;
    else if(current_state==ALLOCATE) 
            inst_from_mem <= inst_mem_i;
    else    inst_from_mem <= inst_from_mem;
end
assign wea_way0=(current_state==WRITE_BACK && LRU[cache_index]==0)?4'hf:4'h0;
assign wea_way1=(current_state==WRITE_BACK && LRU[cache_index]==1)?4'hf:4'h0;


assign inst_cpu_o = (current_state==TAG_COMPARE && hit_way0)?inst_way0:
                    (current_state==TAG_COMPARE && hit_way1)?inst_way1:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h0)?inst_from_mem[32*1-1:32*0]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h1)?inst_from_mem[32*2-1:32*1]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h2)?inst_from_mem[32*3-1:32*2]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h3)?inst_from_mem[32*4-1:32*3]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h4)?inst_from_mem[32*5-1:32*4]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h5)?inst_from_mem[32*6-1:32*5]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h6)?inst_from_mem[32*7-1:32*6]:
                    (current_state==WRITE_BACK && cache_offset[4:2]==3'h7)?inst_from_mem[32*8-1:32*7]:0;

reg do_req;
always@(posedge clk) begin
    if(!rst)    do_req <= 1'b0;
    else if(valid_inst_cpu_o&&current_state==IDLE)
                do_req <= 1'b0;
    else if(rreq_inst_cpu_i==1&&!do_req)
                do_req <= 1'b1;
end
always@(posedge clk) begin
    if(!rst) valid_inst_cpu_o <= 0;
    else     valid_inst_cpu_o <= (current_state==TAG_COMPARE&&do_req) && hit ? 1 :
                                 (current_state==WRITE_BACK&&do_req)         ? 1 : 0;
end



assign arready_inst_cpu_o = !do_req;

endmodule