data/full_repos/permissive/525452387/testbench/gen_dff_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    always #1 begin\n           ^\n%Error: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:59: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("gen_pipe_dff.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/gen_dff_tb.v:60: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, gen_pipe_dff_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_dff_test_bench;
    reg gen_pipe_dff_1_clk;
    reg gen_pipe_dff_1_rst_;
    reg[31:0] gen_pipe_dff_1_default_val;
    reg[31:0] gen_pipe_dff_1_d_i;
    wire[31:0] gen_pipe_dff_1_q_o;

    gen_pipe_dff gen_pipe_dff_1 (
        .clk  (gen_pipe_dff_1_clk),
        .rst_ (gen_pipe_dff_1_rst_),
        .default_val(gen_pipe_dff_1_default_val),
        .d_i(gen_pipe_dff_1_d_i),
        .q_o(gen_pipe_dff_1_q_o)
    );

    initial begin
        #0 begin
            gen_pipe_dff_1_clk <= 1'b1;
            gen_pipe_dff_1_rst_ <= 0;
            gen_pipe_dff_1_default_val <= 32'hDEADBEEF;
        end


        #1 begin
            if (gen_pipe_dff_1_q_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            gen_pipe_dff_1_rst_ <= 1;
            gen_pipe_dff_1_d_i <= 32'h42;
        end


        #1 begin
            if (gen_pipe_dff_1_q_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        gen_pipe_dff_1_clk <= ~gen_pipe_dff_1_clk;
    end

    initial begin
        $dumpfile("gen_pipe_dff.vcd");
        $dumpvars(0, gen_pipe_dff_1);
    end

endmodule
module gen_dff_test_bench;

    reg gen_pipe_dff_1_clk;
    reg gen_pipe_dff_1_rst_;
    reg[31:0] gen_pipe_dff_1_default_val;
    reg[31:0] gen_pipe_dff_1_d_i;
    wire[31:0] gen_pipe_dff_1_q_o;

    gen_pipe_dff gen_pipe_dff_1 (
        .clk  (gen_pipe_dff_1_clk),
        .rst_ (gen_pipe_dff_1_rst_),
        .default_val(gen_pipe_dff_1_default_val),
        .d_i(gen_pipe_dff_1_d_i),
        .q_o(gen_pipe_dff_1_q_o)
    );

    initial begin
        #0 begin
            gen_pipe_dff_1_clk <= 1'b1;
            gen_pipe_dff_1_rst_ <= 0;
            gen_pipe_dff_1_default_val <= 32'hDEADBEEF;
        end


        #1 begin
            if (gen_pipe_dff_1_q_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            gen_pipe_dff_1_rst_ <= 1;
            gen_pipe_dff_1_d_i <= 32'h42;
        end


        #1 begin
            if (gen_pipe_dff_1_q_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        gen_pipe_dff_1_clk <= ~gen_pipe_dff_1_clk;
    end

    initial begin
        $dumpfile("gen_pipe_dff.vcd");
        $dumpvars(0, gen_pipe_dff_1);
    end

endmodule