data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:486: Signal definition not found, creating implicitly: \'MEMWB_OUT_1\'\n                                                                                                                              : ... Suggested alternative: \'MEM_OUT_1\'\n    assign MEMWB_HILO_we=MEMWB_OUT_1;\n                         ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:488: Signal definition not found, creating implicitly: \'MEMWB_OUT_2\'\n                                                                                                                              : ... Suggested alternative: \'MEMWB_OUT_1\'\n    assign MEMWB_hi_data=MEMWB_OUT_2;\n                         ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:488: Signal definition not found, creating implicitly: \'MEMWB_hi_data\'\n    assign MEMWB_hi_data=MEMWB_OUT_2;\n           ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:490: Signal definition not found, creating implicitly: \'MEMWB_OUT_3\'\n                                                                                                                              : ... Suggested alternative: \'MEMWB_OUT_1\'\n    assign MEMWB_lo_data=MEMWB_OUT_3;\n                         ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:490: Signal definition not found, creating implicitly: \'MEMWB_lo_data\'\n                                                                                                                              : ... Suggested alternative: \'MEMWB_hi_data\'\n    assign MEMWB_lo_data=MEMWB_OUT_3;\n           ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:512: Signal definition not found, creating implicitly: \'CL_OUT_1\'\n                                                                                                                              : ... Suggested alternative: \'EX_OUT_1\'\n    assign CL_PC_stall=CL_OUT_1;\n                       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:517: Signal definition not found, creating implicitly: \'CL_OUT_2\'\n                                                                                                                              : ... Suggested alternative: \'CL_OUT_1\'\n    assign CL_PC_flush=CL_OUT_2;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:196: Cannot find file containing module: \'light_show\'\nlight_show LS_cpu(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new,data/full_repos/permissive/473511254/light_show\n             data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new,data/full_repos/permissive/473511254/light_show.v\n             data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new,data/full_repos/permissive/473511254/light_show.sv\n             light_show\n             light_show.v\n             light_show.sv\n             obj_dir/light_show\n             obj_dir/light_show.v\n             obj_dir/light_show.sv\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:205: Cannot find file containing module: \'Program_Counter\'\nProgram_Counter PC_cpu(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:219: Cannot find file containing module: \'Instruction_Memory\'\nInstruction_Memory IM_cpu(\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:224: Cannot find file containing module: \'IF_ID\'\nIF_ID IFID_cpu(\n^~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:238: Cannot find file containing module: \'Instruction_Decoder\'\nInstruction_Decoder ID_cpu(\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:285: Cannot find file containing module: \'ID_EX\'\nID_EX IDEX_cpu(\n^~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:319: Cannot find file containing module: \'EX\'\nEX EX_cpu(\n^~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:373: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'EX_OUT_3\' generates 5 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign EX_ID_wreg_addr=EX_OUT_3 ;\n                          ^\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:376: Cannot find file containing module: \'EX_MEM\'\nEX_MEM EXMEM_cpu(\n^~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:416: Cannot find file containing module: \'MEM\'\nMEM MEM_cpu(\n^~~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:445: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MEM_OUT_2\' generates 5 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign MEM_MEMWB_mem_wreg_addr=MEM_OUT_2;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:446: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MEM_OUT_2\' generates 5 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign MEM_ID_wreg_addr=MEM_OUT_2;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:449: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'MEM_OUT_4\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign MEM_MEMWB_mem_whilo=MEM_OUT_4;\n                              ^\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:457: Cannot find file containing module: \'Data_Memory\'\nData_Memory DM_cpu(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:467: Cannot find file containing module: \'MEM_WB\'\nMEM_WB MEMWB_cpu(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:489: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MEMWB_OUT_2\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign MEMWB_EX_hi=MEMWB_OUT_2;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:491: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MEMWB_OUT_3\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign MEMWB_EX_lo=MEMWB_OUT_3;\n                      ^\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:493: Cannot find file containing module: \'HILO\'\nHILO HILO_cpu(\n^~~~\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:503: Cannot find file containing module: \'Ctrl\'\nCtrl CL_cpu(\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:512: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'CL_OUT_1\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign CL_PC_stall=CL_OUT_1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:513: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'CL_OUT_1\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign CL_IFID_stall=CL_OUT_1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:514: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'CL_OUT_1\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign CL_IDEX_stall=CL_OUT_1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:515: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'CL_OUT_1\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign CL_EXMEM_stall=CL_OUT_1;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:516: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'CL_OUT_1\' generates 1 bits.\n                                                                                                                           : ... In instance TOP_CPU\n    assign CL_MEMWB_stall=CL_OUT_1;\n                         ^\n%Error: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/TOP_CPU.v:524: Cannot find file containing module: \'Register_File\'\nRegister_File RF_cpu(\n^~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s), 18 warning(s)\n'
module TOP_CPU(
    input sys_clk,
    input rst,
    output reg[7:0] test,
    output      [6:0] O_led,
    output      [3:0] O_px
);
    






wire [5:0] CL_PC_stall;
wire CL_PC_flush;
wire [31:0] CL_PC_newpc;
wire ID_PC_branchflag;
wire [31:0] ID_PC_branch_taraddr;
wire [31:0] PC_OUT_1;

wire [31:0] PC_IM_addr;

wire [5:0] CL_IFID_stall;
wire CL_IFID_flush;
wire [31:0] PC_IFID_pc;
wire [31:0] IM_IFID_ins;

wire [31:0] IFID_ID_pc;
wire [31:0] IFID_ID_ins;
wire [7:0] EX_ID_aluop;
wire EX_ID_wreg;
wire [31:0] EX_ID_wreg_addr;
wire [31:0] EX_ID_wreg_data;
wire MEM_ID_wreg;
wire [31:0] MEM_ID_wreg_addr;
wire [31:0] MEM_ID_wreg_data;
wire IDEX_ID_isindelayslot;
wire [31:0] RF_ID_reg1_data;
wire [31:0] RF_ID_reg2_data;

wire [4:0] ID_RF_reg1_addr;
wire [4:0] ID_RF_reg2_addr;
wire ID_RF_reg1;
wire ID_RF_reg2;




wire [5:0] CL_IDEX_stall;
wire CL_IDEX_flush;
wire [7:0] ID_IDEX_aluop;
wire [2:0] ID_IDEX_alusel;
wire [31:0] ID_IDEX_reg1;
wire [31:0] ID_IDEX_reg2;
wire ID_IDEX_wreg;
wire [4:0] ID_IDEX_wreg_addr;
wire [31:0] ID_IDEX_ins;
wire [31:0] ID_IDEX_ins_addr;
wire ID_IDEX_isindelaysolt;
wire ID_IDEX_next_isindelaysolt;


wire [7:0] IDEX_EX_aluop;
wire [2:0] IDEX_EX_alusel;
wire [31:0] IDEX_EX_reg1_data;
wire [31:0] IDEX_EX_reg2_data;
wire IDEX_EX_wreg;
wire [4:0] IDEX_EX_wreg_addr;
wire [31:0] IDEX_EX_ins;
wire [31:0] IDEX_EX_ins_addr;
wire IDEX_EX_isindelayslot;
wire [31:0] HILO_EX_hi;
wire [31:0] HILO_EX_lo;
wire [31:0] MEMWB_EX_hi;
wire [31:0] MEMWB_EX_lo;
wire MEMWB_EX_whilo;
wire [31:0] MEM_EX_hi;
wire [31:0] MEM_EX_lo;
wire MEM_EX_whilo;

wire [63:0] EXMEM_EX_hilo_temp;
wire [1:0] EXMEM_EX_cnt;
wire DIV_EX_div_res;
wire DIV_EX_ready;

wire [5:0] CL_EXMEM_stall;
wire CL_EXMEM_flush;
wire [31:0] EX_EXMEM_mem_addr;
wire [31:0] EX_EXMEM_reg2;
wire [31:0] EX_EXMEM_hi;
wire [31:0] EX_EXMEM_lo;
wire EX_EXMEM_whilo;
wire [63:0] EX_EXMEM_hilo;
wire [1:0] EX_EXMEM_cnt;
wire EX_EXMEM_isindelaysolt;
wire [31:0] EX_EXMEM_ins_addr;
wire [7:0] EX_EXMEM_aluop;
wire EX_EXMEM_wreg;
wire [4:0] EX_EXMEM_wreg_addr;
wire [31:0] EX_EXMEM_wreg_data;

wire EXMEM_MEM_wreg;
wire [31:0] EXMEM_MEM_wreg_addr;
wire [31:0] EXMEM_MEM_wreg_data;
wire [63:0] EXMEM_MEM_whilo;
wire [31:0] EXMEM_MEM_hi;
wire [31:0] EXMEM_MEM_lo;
wire [7:0] EXMEM_MEM_aluop;
wire [31:0] EXMEM_MEM_mem_addr;
wire [31:0] DM_MEM_mem_data;
wire [31:0] EXMEM_MEM_reg2;
wire EXMEM_MEM_isindelayslot;
wire [31:0] EXMEM_MEM_ins_addr;
wire [31:0] DM_data;

wire [31:0] MEM_DM_mem_addr;
wire MEM_DM_mem_we;
wire [31:0] MEM_DM_mem_data;


wire [5:0] CL_MEMWB_stall;
wire CL_MEMWB_flush;
wire MEM_MEMWB_mem_wreg;
wire [31:0] MEM_MEMWB_mem_wreg_addr;
wire [31:0] MEM_MEMWB_mem_wreg_data;
wire [63:0] MEM_MEMWB_mem_whilo;
wire [31:0] MEM_MEMWB_mem_hi;
wire [31:0] MEM_MEMWB_mem_lo;

wire MEMWB_HILO_we;
wire [31:0] MEMWB_HILO_hi;
wire [31:0] MEMWB_HILO_lo;

wire stallreq_from_EX;
wire stallreq_from_ID;

wire ID_RF_re1;
wire ID_RF_re2;
wire [31:0] ID_RF_re1_addr;
wire [31:0] ID_RF_re2_addr;
wire MEMWB_RF_wreg;
wire [31:0] MEMWB_RF_wreg_addr;
wire [31:0] MEMWB_RF_wreg_data;


reg clk;
integer cnt = 0;
always @(posedge sys_clk or negedge rst)begin
    if(rst == 1'b0) begin
        clk <= 0;
        cnt = 0;

    end else if(cnt < 2) begin
        cnt = cnt + 1;
    end else begin
        clk <= ~clk;
        cnt = 0;
    end
end

reg [31:0]show_num;
always @(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
        show_num = 32'hffffff;
    end else begin
        if(MEM_DM_mem_we) begin
            show_num <= MEM_DM_mem_data;
        end
    end
end

light_show LS_cpu(
    .I_clk(sys_clk),
    .I_rst_n(rst),
    .I_show_num(show_num),
    .O_led(O_led),
    .O_px(O_px)
);


Program_Counter PC_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromCL_stall(CL_PC_stall),
    .I_FromCL_flush(CL_PC_flush),
    .I_FromCL_newpc(CL_PC_newpc),
    .I_FromID_branchflag(ID_PC_branchflag),
    .I_FromID_branch_taraddr(ID_PC_branch_taraddr),
    .O_ToIM_IFID_pc(PC_OUT_1)

);
    assign PC_IM_addr=PC_OUT_1;
    assign PC_IFID_pc=PC_OUT_1;
    
Instruction_Memory IM_cpu(
    .a(PC_IM_addr),
    .spo(IM_IFID_ins)
);

IF_ID IFID_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_IFID_stall),
    .CL_flush(CL_IFID_flush),
    .IF_pc(PC_IFID_pc),
    .IF_ins(IM_IFID_ins),
    .ID_pc(IFID_ID_pc),
    .ID_ins(IFID_ID_ins)
);


wire ID_IDEX_next_isindelayslot;
wire IDEX_ID_is_indelayslot;
Instruction_Decoder ID_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromIFID_pc(IFID_ID_pc),
    .I_FromIFID_ins(IFID_ID_ins),

    .I_FromRF_reg1_data(RF_ID_reg1_data),
    .I_FromRF_reg2_data(RF_ID_reg2_data),
    .O_ToRF_reg1(ID_RF_reg1),
    .O_ToRF_reg2(ID_RF_reg2),
    .O_ToRF_reg1_addr(ID_RF_reg1_addr),
    .O_ToRF_reg2_addr(ID_RF_reg2_addr),
    .O_ToIDEX_wreg(ID_IDEX_wreg),
    .O_ToIDEX_wreg_addr(ID_IDEX_wreg_addr),
    .O_ToIDEX_aluop(ID_IDEX_aluop),
    .O_ToIDEX_alusel(ID_IDEX_alusel),
    .O_ToIDEX_reg1(ID_IDEX_reg1),
    .O_ToIDEX_reg2(ID_IDEX_reg2),

    .I_FromEX_wreg(EX_ID_wreg),
    .I_FromEX_wreg_addr(EX_ID_wreg_addr),
    .I_FromEX_wreg_data(EX_ID_wreg_data),
    .I_FromEX_aluop(EX_ID_aluop),
    .I_FromMEM_wreg(MEM_ID_wreg),
    .I_FromMEM_wreg_addr(MEM_ID_wreg_addr),
    .I_FromMEM_wreg_data(MEM_ID_wreg_data),

    .I_FromIDEX_isindelayslot(IDEX_ID_is_indelayslot),
    .O_ToIDEX_isindelayslot(ID_IDEX_isindelaysolt),
    .O_ToPC_branchflag(ID_PC_branchflag),
    .O_ToPC_branch_taraddr(ID_PC_branch_taraddr),

    .stallreq(stallreq_from_ID),
    .O_ToIDEX_ins_addr(ID_IDEX_ins_addr),
    .O_ToIDEX_ins(ID_IDEX_ins),




     .O_ToIDEX_next_isindelayslot(ID_IDEX_next_isindelayslot)



);



ID_EX IDEX_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_IDEX_stall),
    .CL_flush(CL_IDEX_flush),
    .ID_alusel(ID_IDEX_alusel),
    .ID_aluop(ID_IDEX_aluop),
    .ID_reg1(ID_IDEX_reg1),
    .ID_reg2(ID_IDEX_reg2),
    .ID_wreg(ID_IDEX_wreg),
    .ID_wreg_addr(ID_IDEX_wreg_addr),
    .ID_ins(ID_IDEX_ins),
    .ID_ins_addr(ID_IDEX_ins_addr),
    .ID_isindelayslot(ID_IDEX_isindelaysolt),
    .ID_next_ins_isindelayslot(ID_IDEX_next_isindelayslot),
    
    .EX_alusel(IDEX_EX_alusel),
    .EX_aluop(IDEX_EX_aluop),
    .EX_reg1(IDEX_EX_reg1_data),
    .EX_reg2(IDEX_EX_reg2_data),
    .EX_wreg_addr(IDEX_EX_wreg_addr),
    .EX_wreg(IDEX_EX_wreg),
    .EX_ins(IDEX_EX_ins),
    .EX_ins_addr(IDEX_EX_ins_addr),
    .EX_isindelayslot(IDEX_EX_isindelayslot),
    .IDEX_ID_isindelayslot(IDEX_ID_is_indelayslot)
);


wire EX_OUT_1;
wire [7:0] EX_OUT_2;
wire [4:0] EX_OUT_3;
wire [31:0] EX_OUT_4;

EX EX_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromIDEX_alusel(IDEX_EX_alusel),
    .I_FromIDEX_aluop(IDEX_EX_aluop),
    .I_FromIDEX_reg1(IDEX_EX_reg1_data),
    .I_FromIDEX_reg2(IDEX_EX_reg2_data),
    .I_FromIDEX_wreg(IDEX_EX_wreg),
    .I_FromIDEX_wreg_addr(IDEX_EX_wreg_addr),
    .I_FromIDEX_ins(IDEX_EX_ins),
    .I_FromIDEX_ins_addr(IDEX_EX_ins_addr),
    .O_ToEXMEM_reg2(EX_EXMEM_reg2),

    .I_FromHILO_hi(HILO_EX_hi),
    .I_FromHILO_lo(HILO_EX_lo),

    .I_FromMEM_whilo(MEM_EX_whilo),
    .I_FromMEM_wb_hi(MEM_EX_hi),
    .I_FromMEM_wb_lo(MEM_EX_lo),

    .I_FromMEMWB_whilo(MEMWB_EX_whilo),
    .I_FromMEMWB_wb_hi(MEMWB_EX_hi),
    .I_FromMEMWB_wb_lo(MEMWB_EX_lo),

    .I_FromEXMEM_hilo_temp(EXMEM_EX_hilo_temp),
    .I_FromEXMEM_cnt(EXMEM_EX_cnt),
    .O_ToEXMEM_hilo_temp(EX_EXMEM_hilo),
    .O_ToEXMEM_cnt(EX_EXMEM_cnt),

    .I_FromDIV_divready(DIV_EX_ready),
    .I_FromDIV_divres(),
    .O_ToDIV_signediv(),
    .O_ToDIV_opdata1(),
    .O_ToDIV_opdata2(),
    .O_ToDIV_divstart(),

    .I_FromIDEX_isindelayslot(IDEX_EX_isindelayslot),
    .O_TOEXMEM_isindelayslot(EX_EXMEM_isindelaysolt),

    .O_To_EXMEM_mem_addr(EX_EXMEM_mem_addr),
    .O_To_ID_EXMEM_wreg(EX_OUT_1),
    .O_To_ID_EXMEM_aluop(EX_OUT_2),
    .O_To_ID_EXMEM_wreg_addr(EX_OUT_3),
    .O_To_ID_EXMEM_wreg_data(EX_OUT_4),

    .stallreq(stallreq_from_EX)
);

    assign EX_EXMEM_aluop=EX_OUT_2;
    assign EX_EXMEM_wreg=EX_OUT_1 ;
    assign EX_EXMEM_wreg_addr=EX_OUT_3 ;
    assign EX_EXMEM_wreg_data=EX_OUT_4 ;
    assign EX_ID_aluop=EX_OUT_2 ;
    assign EX_ID_wreg=EX_OUT_1 ;
    assign EX_ID_wreg_addr=EX_OUT_3 ;
    assign EX_ID_wreg_data=EX_OUT_4 ;
    
EX_MEM EXMEM_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_EXMEM_stall),
    .CL_flush(CL_EXMEM_flush),
    .EX_mem_addr(EX_EXMEM_mem_addr),
    .EX_reg2(EX_EXMEM_reg2),
    .EX_whilo(EX_EXMEM_whilo),
    .EX_hi(EX_EXMEM_hi),
    .EX_lo(EX_EXMEM_lo),
    .EX_hilo(EX_EXMEM_hilo),
    .EX_cnt(EX_EXMEM_cnt),
    .EX_isindelayslot(EX_EXMEM_isindelaysolt),
    .EX_ins_addr(EX_EXMEM_ins_addr),
    .EX_aluop(EX_EXMEM_aluop),
    .EX_wreg(EX_EXMEM_wreg),
    .EX_wreg_addr(EX_EXMEM_wreg_addr),
    .EX_wreg_data(EX_EXMEM_wreg_data),
    .MEM_wreg(EXMEM_MEM_wreg),
    .MEM_wreg_addr(EXMEM_MEM_wreg_addr),
    .MEM_wreg_data(EXMEM_MEM_wreg_data),
    .MEM_hi(EXMEM_MEM_hi),
    .MEM_lo(EXMEM_MEM_lo),
    .MEM_whilo(EXMEM_MEM_whilo),
    .MEM_aluop(EXMEM_MEM_aluop),
    .MEM_mem_addr(EXMEM_MEM_mem_addr),
    .MEM_reg2(EXMEM_MEM_reg2),
    .MEM_isindelayslot(EXMEM_MEM_isindelayslot),
    .MEM_ins_addr(EXMEM_MEM_ins_addr),
    .EXMEM_EX_hilo(EXMEM_EX_hilo_temp),
    .EXMEM_EX_cnt(EXMEM_EX_cnt) 
);

wire MEM_OUT_1;
wire [4:0] MEM_OUT_2;
wire [31:0] MEM_OUT_3;
wire MEM_OUT_4;
wire [31:0] MEM_OUT_5;
wire [31:0] MEM_OUT_6;

MEM MEM_cpu(
    .rst(rst),
    .I_FROMEX_MEM_wreg(EXMEM_MEM_wreg),
    .I_FROMEX_MEM_wd(EXMEM_MEM_wreg_addr),
    .I_FROMEX_MEM_wdata(EXMEM_MEM_wreg_data),
    .O_TOMEM_WB_ID_wreg(MEM_OUT_1),
    .O_TOMEM_WB_ID_wd(MEM_OUT_2),
    .O_TOMEM_WB_ID_wdata(MEM_OUT_3),
    .I_FROMEX_MEM_whilo(EXMEM_MEM_whilo),
    .I_FROMEX_MEM_hi(EXMEM_MEM_hi),
    .I_FROMEX_MEM_lo(EXMEM_MEM_lo),
    .O_TOMEM_WB_EX_whilo(MEM_OUT_4),
    .O_TOMEM_WB_EX_hi(MEM_OUT_5),
    .O_TOMEM_WB_EX_lo(MEM_OUT_6),
    .I_FROMEX_MEM_aloup(EXMEM_MEM_aluop),
    .I_FROMEX_MEM_mem_addr(EXMEM_MEM_mem_addr),
    .I_FROMEX_MEM_reg2(EXMEM_MEM_reg2),

    . I_FROMDATA_RAM_mem_data(DM_data),
	.O_TODATA_RAM_mem_addr(MEM_DM_mem_addr),
	.O_TODATA_RAM_mem_we(MEM_DM_mem_we),
	.O_TODATA_RAM_mem_sel(),
	.O_TODATA_RAM_mem_data(MEM_DM_mem_data),
    .I_FROMEX_MEM_isindelayslot(EXMEM_MEM_isindelayslot),
    .O_TOMEM_WB_isindelayslot()
);

    assign MEM_MEMWB_mem_wreg=MEM_OUT_1;
    assign MEM_ID_wreg=MEM_OUT_1;
    assign MEM_MEMWB_mem_wreg_addr=MEM_OUT_2;
    assign MEM_ID_wreg_addr=MEM_OUT_2;
    assign MEM_MEMWB_mem_wreg_data=MEM_OUT_3;
    assign MEM_ID_wreg_data=MEM_OUT_3;
    assign MEM_MEMWB_mem_whilo=MEM_OUT_4;
    assign MEM_EX_whilo=MEM_OUT_4;
    assign MEM_MEMWB_mem_hi=MEM_OUT_5;
    assign MEM_EX_hi=MEM_OUT_5;
    assign MEM_MEMWB_mem_lo=MEM_OUT_6;
    assign MEM_EX_lo=MEM_OUT_6;


Data_Memory DM_cpu(
    .clk(clk),
    .a(MEM_DM_mem_addr[15:0]),
    .d(MEM_DM_mem_data),
    .we(MEM_DM_mem_we),
    .spo(DM_data)
);



MEM_WB MEMWB_cpu(
    .clk(clk),
    .rst(rst),
    .MEM_wreg(MEM_MEMWB_mem_wreg),
    .MEM_wreg_addr(MEM_MEMWB_mem_wreg_addr),
    .MEM_wreg_data(MEM_MEMWB_mem_wreg_data),
    .WB_wreg(MEMWB_RF_wreg),
    .WB_wreg_addr(MEMWB_RF_wreg_addr),
    .WB_wreg_data(MEMWB_RF_wreg_data),

    .MEM_whilo(MEM_MEMWB_mem_whilo),
    .MEM_hi_data(MEM_MEMWB_mem_hi),
    .MEM_lo_data(MEM_MEMWB_mem_lo),
    .WB_whilo(MEMWB_OUT_1),
    .WB_hi_data(MEMWB_OUT_2),
    .WB_lo_data(MEMWB_OUT_3),
    .CL_stall(CL_MEMWB_stall),
    .CL_flush(CL_MEMWB_flush)
);
    assign MEMWB_HILO_we=MEMWB_OUT_1;
    assign MEMWB_EX_whilo=MEMWB_OUT_1;
    assign MEMWB_hi_data=MEMWB_OUT_2;
    assign MEMWB_EX_hi=MEMWB_OUT_2;
    assign MEMWB_lo_data=MEMWB_OUT_3;
    assign MEMWB_EX_lo=MEMWB_OUT_3;
    
HILO HILO_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromMEMWB_wreg(MEMWB_HILO_we),
    .I_FromMEMWB_hi(MEMWB_hi_data),
    .I_FromMEMWB_lo(MEMWB_lo_data),
    .O_ToEX_hi(HILO_EX_hi),
    .O_ToEX_lo(HILO_EX_lo)
);

Ctrl CL_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromID_stallreq(stallreq_from_ID),
    .I_FromEX_stallreq(stallreq_from_EX),
    .stall(CL_OUT_1),
    .flush(CL_OUT_2),
    .O_ToPC_new_pc(CL_PC_newpc)
);
    assign CL_PC_stall=CL_OUT_1;
    assign CL_IFID_stall=CL_OUT_1;
    assign CL_IDEX_stall=CL_OUT_1;
    assign CL_EXMEM_stall=CL_OUT_1;
    assign CL_MEMWB_stall=CL_OUT_1;
    assign CL_PC_flush=CL_OUT_2;
    assign CL_IFID_flush=CL_OUT_2;
    assign CL_IDEX_flush=CL_OUT_2;
    assign CL_EXMEM_flush=CL_OUT_2;
    assign CL_MEMWB_flush=CL_OUT_2;


Register_File RF_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromMEM_WB_we(MEMWB_RF_wreg),
    .I_FromMEM_WB_waddr(MEMWB_RF_wreg_addr),
    .I_FromMEM_WB_wdata(MEMWB_RF_wreg_data),
	.I_FromID_re1(ID_RF_reg1),
	.I_FromID_raddr1(ID_RF_reg1_addr),
	.O_ToID_rdata1(RF_ID_reg1_data),
    .I_FromID_re2(ID_RF_reg2),
    .I_FromID_raddr2(ID_RF_reg2_addr),
    .O_ToID_rdata2(RF_ID_reg2_data)
);

always @ (posedge clk or negedge rst) begin
    if(rst==1'b0) begin
        test <= test;
    end else begin
        test <= PC_IFID_pc[7:0];
    end
end


endmodule
module TOP_CPU(
    input sys_clk,
    input rst,
    output reg[7:0] test,
    output      [6:0] O_led,
    output      [3:0] O_px
);

    






wire [5:0] CL_PC_stall;
wire CL_PC_flush;
wire [31:0] CL_PC_newpc;
wire ID_PC_branchflag;
wire [31:0] ID_PC_branch_taraddr;
wire [31:0] PC_OUT_1;

wire [31:0] PC_IM_addr;

wire [5:0] CL_IFID_stall;
wire CL_IFID_flush;
wire [31:0] PC_IFID_pc;
wire [31:0] IM_IFID_ins;

wire [31:0] IFID_ID_pc;
wire [31:0] IFID_ID_ins;
wire [7:0] EX_ID_aluop;
wire EX_ID_wreg;
wire [31:0] EX_ID_wreg_addr;
wire [31:0] EX_ID_wreg_data;
wire MEM_ID_wreg;
wire [31:0] MEM_ID_wreg_addr;
wire [31:0] MEM_ID_wreg_data;
wire IDEX_ID_isindelayslot;
wire [31:0] RF_ID_reg1_data;
wire [31:0] RF_ID_reg2_data;

wire [4:0] ID_RF_reg1_addr;
wire [4:0] ID_RF_reg2_addr;
wire ID_RF_reg1;
wire ID_RF_reg2;




wire [5:0] CL_IDEX_stall;
wire CL_IDEX_flush;
wire [7:0] ID_IDEX_aluop;
wire [2:0] ID_IDEX_alusel;
wire [31:0] ID_IDEX_reg1;
wire [31:0] ID_IDEX_reg2;
wire ID_IDEX_wreg;
wire [4:0] ID_IDEX_wreg_addr;
wire [31:0] ID_IDEX_ins;
wire [31:0] ID_IDEX_ins_addr;
wire ID_IDEX_isindelaysolt;
wire ID_IDEX_next_isindelaysolt;


wire [7:0] IDEX_EX_aluop;
wire [2:0] IDEX_EX_alusel;
wire [31:0] IDEX_EX_reg1_data;
wire [31:0] IDEX_EX_reg2_data;
wire IDEX_EX_wreg;
wire [4:0] IDEX_EX_wreg_addr;
wire [31:0] IDEX_EX_ins;
wire [31:0] IDEX_EX_ins_addr;
wire IDEX_EX_isindelayslot;
wire [31:0] HILO_EX_hi;
wire [31:0] HILO_EX_lo;
wire [31:0] MEMWB_EX_hi;
wire [31:0] MEMWB_EX_lo;
wire MEMWB_EX_whilo;
wire [31:0] MEM_EX_hi;
wire [31:0] MEM_EX_lo;
wire MEM_EX_whilo;

wire [63:0] EXMEM_EX_hilo_temp;
wire [1:0] EXMEM_EX_cnt;
wire DIV_EX_div_res;
wire DIV_EX_ready;

wire [5:0] CL_EXMEM_stall;
wire CL_EXMEM_flush;
wire [31:0] EX_EXMEM_mem_addr;
wire [31:0] EX_EXMEM_reg2;
wire [31:0] EX_EXMEM_hi;
wire [31:0] EX_EXMEM_lo;
wire EX_EXMEM_whilo;
wire [63:0] EX_EXMEM_hilo;
wire [1:0] EX_EXMEM_cnt;
wire EX_EXMEM_isindelaysolt;
wire [31:0] EX_EXMEM_ins_addr;
wire [7:0] EX_EXMEM_aluop;
wire EX_EXMEM_wreg;
wire [4:0] EX_EXMEM_wreg_addr;
wire [31:0] EX_EXMEM_wreg_data;

wire EXMEM_MEM_wreg;
wire [31:0] EXMEM_MEM_wreg_addr;
wire [31:0] EXMEM_MEM_wreg_data;
wire [63:0] EXMEM_MEM_whilo;
wire [31:0] EXMEM_MEM_hi;
wire [31:0] EXMEM_MEM_lo;
wire [7:0] EXMEM_MEM_aluop;
wire [31:0] EXMEM_MEM_mem_addr;
wire [31:0] DM_MEM_mem_data;
wire [31:0] EXMEM_MEM_reg2;
wire EXMEM_MEM_isindelayslot;
wire [31:0] EXMEM_MEM_ins_addr;
wire [31:0] DM_data;

wire [31:0] MEM_DM_mem_addr;
wire MEM_DM_mem_we;
wire [31:0] MEM_DM_mem_data;


wire [5:0] CL_MEMWB_stall;
wire CL_MEMWB_flush;
wire MEM_MEMWB_mem_wreg;
wire [31:0] MEM_MEMWB_mem_wreg_addr;
wire [31:0] MEM_MEMWB_mem_wreg_data;
wire [63:0] MEM_MEMWB_mem_whilo;
wire [31:0] MEM_MEMWB_mem_hi;
wire [31:0] MEM_MEMWB_mem_lo;

wire MEMWB_HILO_we;
wire [31:0] MEMWB_HILO_hi;
wire [31:0] MEMWB_HILO_lo;

wire stallreq_from_EX;
wire stallreq_from_ID;

wire ID_RF_re1;
wire ID_RF_re2;
wire [31:0] ID_RF_re1_addr;
wire [31:0] ID_RF_re2_addr;
wire MEMWB_RF_wreg;
wire [31:0] MEMWB_RF_wreg_addr;
wire [31:0] MEMWB_RF_wreg_data;


reg clk;
integer cnt = 0;
always @(posedge sys_clk or negedge rst)begin
    if(rst == 1'b0) begin
        clk <= 0;
        cnt = 0;

    end else if(cnt < 2) begin
        cnt = cnt + 1;
    end else begin
        clk <= ~clk;
        cnt = 0;
    end
end

reg [31:0]show_num;
always @(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
        show_num = 32'hffffff;
    end else begin
        if(MEM_DM_mem_we) begin
            show_num <= MEM_DM_mem_data;
        end
    end
end

light_show LS_cpu(
    .I_clk(sys_clk),
    .I_rst_n(rst),
    .I_show_num(show_num),
    .O_led(O_led),
    .O_px(O_px)
);


Program_Counter PC_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromCL_stall(CL_PC_stall),
    .I_FromCL_flush(CL_PC_flush),
    .I_FromCL_newpc(CL_PC_newpc),
    .I_FromID_branchflag(ID_PC_branchflag),
    .I_FromID_branch_taraddr(ID_PC_branch_taraddr),
    .O_ToIM_IFID_pc(PC_OUT_1)

);
    assign PC_IM_addr=PC_OUT_1;
    assign PC_IFID_pc=PC_OUT_1;
    
Instruction_Memory IM_cpu(
    .a(PC_IM_addr),
    .spo(IM_IFID_ins)
);

IF_ID IFID_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_IFID_stall),
    .CL_flush(CL_IFID_flush),
    .IF_pc(PC_IFID_pc),
    .IF_ins(IM_IFID_ins),
    .ID_pc(IFID_ID_pc),
    .ID_ins(IFID_ID_ins)
);


wire ID_IDEX_next_isindelayslot;
wire IDEX_ID_is_indelayslot;
Instruction_Decoder ID_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromIFID_pc(IFID_ID_pc),
    .I_FromIFID_ins(IFID_ID_ins),

    .I_FromRF_reg1_data(RF_ID_reg1_data),
    .I_FromRF_reg2_data(RF_ID_reg2_data),
    .O_ToRF_reg1(ID_RF_reg1),
    .O_ToRF_reg2(ID_RF_reg2),
    .O_ToRF_reg1_addr(ID_RF_reg1_addr),
    .O_ToRF_reg2_addr(ID_RF_reg2_addr),
    .O_ToIDEX_wreg(ID_IDEX_wreg),
    .O_ToIDEX_wreg_addr(ID_IDEX_wreg_addr),
    .O_ToIDEX_aluop(ID_IDEX_aluop),
    .O_ToIDEX_alusel(ID_IDEX_alusel),
    .O_ToIDEX_reg1(ID_IDEX_reg1),
    .O_ToIDEX_reg2(ID_IDEX_reg2),

    .I_FromEX_wreg(EX_ID_wreg),
    .I_FromEX_wreg_addr(EX_ID_wreg_addr),
    .I_FromEX_wreg_data(EX_ID_wreg_data),
    .I_FromEX_aluop(EX_ID_aluop),
    .I_FromMEM_wreg(MEM_ID_wreg),
    .I_FromMEM_wreg_addr(MEM_ID_wreg_addr),
    .I_FromMEM_wreg_data(MEM_ID_wreg_data),

    .I_FromIDEX_isindelayslot(IDEX_ID_is_indelayslot),
    .O_ToIDEX_isindelayslot(ID_IDEX_isindelaysolt),
    .O_ToPC_branchflag(ID_PC_branchflag),
    .O_ToPC_branch_taraddr(ID_PC_branch_taraddr),

    .stallreq(stallreq_from_ID),
    .O_ToIDEX_ins_addr(ID_IDEX_ins_addr),
    .O_ToIDEX_ins(ID_IDEX_ins),




     .O_ToIDEX_next_isindelayslot(ID_IDEX_next_isindelayslot)



);



ID_EX IDEX_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_IDEX_stall),
    .CL_flush(CL_IDEX_flush),
    .ID_alusel(ID_IDEX_alusel),
    .ID_aluop(ID_IDEX_aluop),
    .ID_reg1(ID_IDEX_reg1),
    .ID_reg2(ID_IDEX_reg2),
    .ID_wreg(ID_IDEX_wreg),
    .ID_wreg_addr(ID_IDEX_wreg_addr),
    .ID_ins(ID_IDEX_ins),
    .ID_ins_addr(ID_IDEX_ins_addr),
    .ID_isindelayslot(ID_IDEX_isindelaysolt),
    .ID_next_ins_isindelayslot(ID_IDEX_next_isindelayslot),
    
    .EX_alusel(IDEX_EX_alusel),
    .EX_aluop(IDEX_EX_aluop),
    .EX_reg1(IDEX_EX_reg1_data),
    .EX_reg2(IDEX_EX_reg2_data),
    .EX_wreg_addr(IDEX_EX_wreg_addr),
    .EX_wreg(IDEX_EX_wreg),
    .EX_ins(IDEX_EX_ins),
    .EX_ins_addr(IDEX_EX_ins_addr),
    .EX_isindelayslot(IDEX_EX_isindelayslot),
    .IDEX_ID_isindelayslot(IDEX_ID_is_indelayslot)
);


wire EX_OUT_1;
wire [7:0] EX_OUT_2;
wire [4:0] EX_OUT_3;
wire [31:0] EX_OUT_4;

EX EX_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromIDEX_alusel(IDEX_EX_alusel),
    .I_FromIDEX_aluop(IDEX_EX_aluop),
    .I_FromIDEX_reg1(IDEX_EX_reg1_data),
    .I_FromIDEX_reg2(IDEX_EX_reg2_data),
    .I_FromIDEX_wreg(IDEX_EX_wreg),
    .I_FromIDEX_wreg_addr(IDEX_EX_wreg_addr),
    .I_FromIDEX_ins(IDEX_EX_ins),
    .I_FromIDEX_ins_addr(IDEX_EX_ins_addr),
    .O_ToEXMEM_reg2(EX_EXMEM_reg2),

    .I_FromHILO_hi(HILO_EX_hi),
    .I_FromHILO_lo(HILO_EX_lo),

    .I_FromMEM_whilo(MEM_EX_whilo),
    .I_FromMEM_wb_hi(MEM_EX_hi),
    .I_FromMEM_wb_lo(MEM_EX_lo),

    .I_FromMEMWB_whilo(MEMWB_EX_whilo),
    .I_FromMEMWB_wb_hi(MEMWB_EX_hi),
    .I_FromMEMWB_wb_lo(MEMWB_EX_lo),

    .I_FromEXMEM_hilo_temp(EXMEM_EX_hilo_temp),
    .I_FromEXMEM_cnt(EXMEM_EX_cnt),
    .O_ToEXMEM_hilo_temp(EX_EXMEM_hilo),
    .O_ToEXMEM_cnt(EX_EXMEM_cnt),

    .I_FromDIV_divready(DIV_EX_ready),
    .I_FromDIV_divres(),
    .O_ToDIV_signediv(),
    .O_ToDIV_opdata1(),
    .O_ToDIV_opdata2(),
    .O_ToDIV_divstart(),

    .I_FromIDEX_isindelayslot(IDEX_EX_isindelayslot),
    .O_TOEXMEM_isindelayslot(EX_EXMEM_isindelaysolt),

    .O_To_EXMEM_mem_addr(EX_EXMEM_mem_addr),
    .O_To_ID_EXMEM_wreg(EX_OUT_1),
    .O_To_ID_EXMEM_aluop(EX_OUT_2),
    .O_To_ID_EXMEM_wreg_addr(EX_OUT_3),
    .O_To_ID_EXMEM_wreg_data(EX_OUT_4),

    .stallreq(stallreq_from_EX)
);

    assign EX_EXMEM_aluop=EX_OUT_2;
    assign EX_EXMEM_wreg=EX_OUT_1 ;
    assign EX_EXMEM_wreg_addr=EX_OUT_3 ;
    assign EX_EXMEM_wreg_data=EX_OUT_4 ;
    assign EX_ID_aluop=EX_OUT_2 ;
    assign EX_ID_wreg=EX_OUT_1 ;
    assign EX_ID_wreg_addr=EX_OUT_3 ;
    assign EX_ID_wreg_data=EX_OUT_4 ;
    
EX_MEM EXMEM_cpu(
    .clk(clk),
    .rst(rst),
    .CL_stall(CL_EXMEM_stall),
    .CL_flush(CL_EXMEM_flush),
    .EX_mem_addr(EX_EXMEM_mem_addr),
    .EX_reg2(EX_EXMEM_reg2),
    .EX_whilo(EX_EXMEM_whilo),
    .EX_hi(EX_EXMEM_hi),
    .EX_lo(EX_EXMEM_lo),
    .EX_hilo(EX_EXMEM_hilo),
    .EX_cnt(EX_EXMEM_cnt),
    .EX_isindelayslot(EX_EXMEM_isindelaysolt),
    .EX_ins_addr(EX_EXMEM_ins_addr),
    .EX_aluop(EX_EXMEM_aluop),
    .EX_wreg(EX_EXMEM_wreg),
    .EX_wreg_addr(EX_EXMEM_wreg_addr),
    .EX_wreg_data(EX_EXMEM_wreg_data),
    .MEM_wreg(EXMEM_MEM_wreg),
    .MEM_wreg_addr(EXMEM_MEM_wreg_addr),
    .MEM_wreg_data(EXMEM_MEM_wreg_data),
    .MEM_hi(EXMEM_MEM_hi),
    .MEM_lo(EXMEM_MEM_lo),
    .MEM_whilo(EXMEM_MEM_whilo),
    .MEM_aluop(EXMEM_MEM_aluop),
    .MEM_mem_addr(EXMEM_MEM_mem_addr),
    .MEM_reg2(EXMEM_MEM_reg2),
    .MEM_isindelayslot(EXMEM_MEM_isindelayslot),
    .MEM_ins_addr(EXMEM_MEM_ins_addr),
    .EXMEM_EX_hilo(EXMEM_EX_hilo_temp),
    .EXMEM_EX_cnt(EXMEM_EX_cnt) 
);

wire MEM_OUT_1;
wire [4:0] MEM_OUT_2;
wire [31:0] MEM_OUT_3;
wire MEM_OUT_4;
wire [31:0] MEM_OUT_5;
wire [31:0] MEM_OUT_6;

MEM MEM_cpu(
    .rst(rst),
    .I_FROMEX_MEM_wreg(EXMEM_MEM_wreg),
    .I_FROMEX_MEM_wd(EXMEM_MEM_wreg_addr),
    .I_FROMEX_MEM_wdata(EXMEM_MEM_wreg_data),
    .O_TOMEM_WB_ID_wreg(MEM_OUT_1),
    .O_TOMEM_WB_ID_wd(MEM_OUT_2),
    .O_TOMEM_WB_ID_wdata(MEM_OUT_3),
    .I_FROMEX_MEM_whilo(EXMEM_MEM_whilo),
    .I_FROMEX_MEM_hi(EXMEM_MEM_hi),
    .I_FROMEX_MEM_lo(EXMEM_MEM_lo),
    .O_TOMEM_WB_EX_whilo(MEM_OUT_4),
    .O_TOMEM_WB_EX_hi(MEM_OUT_5),
    .O_TOMEM_WB_EX_lo(MEM_OUT_6),
    .I_FROMEX_MEM_aloup(EXMEM_MEM_aluop),
    .I_FROMEX_MEM_mem_addr(EXMEM_MEM_mem_addr),
    .I_FROMEX_MEM_reg2(EXMEM_MEM_reg2),

    . I_FROMDATA_RAM_mem_data(DM_data),
	.O_TODATA_RAM_mem_addr(MEM_DM_mem_addr),
	.O_TODATA_RAM_mem_we(MEM_DM_mem_we),
	.O_TODATA_RAM_mem_sel(),
	.O_TODATA_RAM_mem_data(MEM_DM_mem_data),
    .I_FROMEX_MEM_isindelayslot(EXMEM_MEM_isindelayslot),
    .O_TOMEM_WB_isindelayslot()
);

    assign MEM_MEMWB_mem_wreg=MEM_OUT_1;
    assign MEM_ID_wreg=MEM_OUT_1;
    assign MEM_MEMWB_mem_wreg_addr=MEM_OUT_2;
    assign MEM_ID_wreg_addr=MEM_OUT_2;
    assign MEM_MEMWB_mem_wreg_data=MEM_OUT_3;
    assign MEM_ID_wreg_data=MEM_OUT_3;
    assign MEM_MEMWB_mem_whilo=MEM_OUT_4;
    assign MEM_EX_whilo=MEM_OUT_4;
    assign MEM_MEMWB_mem_hi=MEM_OUT_5;
    assign MEM_EX_hi=MEM_OUT_5;
    assign MEM_MEMWB_mem_lo=MEM_OUT_6;
    assign MEM_EX_lo=MEM_OUT_6;


Data_Memory DM_cpu(
    .clk(clk),
    .a(MEM_DM_mem_addr[15:0]),
    .d(MEM_DM_mem_data),
    .we(MEM_DM_mem_we),
    .spo(DM_data)
);



MEM_WB MEMWB_cpu(
    .clk(clk),
    .rst(rst),
    .MEM_wreg(MEM_MEMWB_mem_wreg),
    .MEM_wreg_addr(MEM_MEMWB_mem_wreg_addr),
    .MEM_wreg_data(MEM_MEMWB_mem_wreg_data),
    .WB_wreg(MEMWB_RF_wreg),
    .WB_wreg_addr(MEMWB_RF_wreg_addr),
    .WB_wreg_data(MEMWB_RF_wreg_data),

    .MEM_whilo(MEM_MEMWB_mem_whilo),
    .MEM_hi_data(MEM_MEMWB_mem_hi),
    .MEM_lo_data(MEM_MEMWB_mem_lo),
    .WB_whilo(MEMWB_OUT_1),
    .WB_hi_data(MEMWB_OUT_2),
    .WB_lo_data(MEMWB_OUT_3),
    .CL_stall(CL_MEMWB_stall),
    .CL_flush(CL_MEMWB_flush)
);
    assign MEMWB_HILO_we=MEMWB_OUT_1;
    assign MEMWB_EX_whilo=MEMWB_OUT_1;
    assign MEMWB_hi_data=MEMWB_OUT_2;
    assign MEMWB_EX_hi=MEMWB_OUT_2;
    assign MEMWB_lo_data=MEMWB_OUT_3;
    assign MEMWB_EX_lo=MEMWB_OUT_3;
    
HILO HILO_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromMEMWB_wreg(MEMWB_HILO_we),
    .I_FromMEMWB_hi(MEMWB_hi_data),
    .I_FromMEMWB_lo(MEMWB_lo_data),
    .O_ToEX_hi(HILO_EX_hi),
    .O_ToEX_lo(HILO_EX_lo)
);

Ctrl CL_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromID_stallreq(stallreq_from_ID),
    .I_FromEX_stallreq(stallreq_from_EX),
    .stall(CL_OUT_1),
    .flush(CL_OUT_2),
    .O_ToPC_new_pc(CL_PC_newpc)
);
    assign CL_PC_stall=CL_OUT_1;
    assign CL_IFID_stall=CL_OUT_1;
    assign CL_IDEX_stall=CL_OUT_1;
    assign CL_EXMEM_stall=CL_OUT_1;
    assign CL_MEMWB_stall=CL_OUT_1;
    assign CL_PC_flush=CL_OUT_2;
    assign CL_IFID_flush=CL_OUT_2;
    assign CL_IDEX_flush=CL_OUT_2;
    assign CL_EXMEM_flush=CL_OUT_2;
    assign CL_MEMWB_flush=CL_OUT_2;


Register_File RF_cpu(
    .clk(clk),
    .rst(rst),
    .I_FromMEM_WB_we(MEMWB_RF_wreg),
    .I_FromMEM_WB_waddr(MEMWB_RF_wreg_addr),
    .I_FromMEM_WB_wdata(MEMWB_RF_wreg_data),
	.I_FromID_re1(ID_RF_reg1),
	.I_FromID_raddr1(ID_RF_reg1_addr),
	.O_ToID_rdata1(RF_ID_reg1_data),
    .I_FromID_re2(ID_RF_reg2),
    .I_FromID_raddr2(ID_RF_reg2_addr),
    .O_ToID_rdata2(RF_ID_reg2_data)
);

always @ (posedge clk or negedge rst) begin
    if(rst==1'b0) begin
        test <= test;
    end else begin
        test <= PC_IFID_pc[7:0];
    end
end


endmodule