data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v
1: b'%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:106: Cannot find file containing module: \'ComWithCC3200\'\n    ComWithCC3200    ComWithCC3200  (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/ComWithCC3200\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/ComWithCC3200.v\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/ComWithCC3200.sv\n             ComWithCC3200\n             ComWithCC3200.v\n             ComWithCC3200.sv\n             obj_dir/ComWithCC3200\n             obj_dir/ComWithCC3200.v\n             obj_dir/ComWithCC3200.sv\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:153: Cannot find file containing module: \'PLL\'\n PLL PLL_inst (\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:275: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h50\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   else if(Pulse_Counter < (Line_Period + 8\'d80))   \n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:299: Cannot find file containing module: \'Transmit\'\n Transmit Transmit_Inst(\n ^~~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:327: Cannot find file containing module: \'LVDS_AD\'\n LVDS_AD LVDS_AD_inst_A (\n ^~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:349: Cannot find file containing module: \'AD9273_SPI_Config\'\n  AD9273_SPI_Config AD9273_SPI_Config_Inst(\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:366: Cannot find file containing module: \'TGC_ROM\'\n TGC_ROM TGC_ROM_inst (\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:392: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n     sdin         <= Send_Data[8\'d18-Send_Counter];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:412: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n     sdin         <= Send_Data[8\'d18-Send_Counter];\n                              ^\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:452: Cannot find file containing module: \'Receive\'\n Receive Receive_Inst(\n ^~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:484: Cannot find file containing module: \'matchfilter\'\n    matchfilter MatchFilter_Inst(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:533: Cannot find file containing module: \'ABS\'\n ABS ABS_inst (\n ^~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:545: Cannot find file containing module: \'lf\'\n lf LF_Inst(\n ^~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:561: Operator GT expects 18 bits on the LHS, but LHS\'s SEL generates 17 bits.\n                                                                                      : ... In instance ArrayUltrasound\n  assign Log_IN =(LF_Data[30])?13\'d0:((LF_Data[30:14] > 18\'d8091)?13\'d8191:LF_Data[26:14]);\n                                                      ^\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:567: Cannot find file containing module: \'LOG_Table\'\n LOG_Table LOG_Table_inst (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:611: Cannot find file containing module: \'Test\'\n Test Test_inst (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:622: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   WR_RAM_ADDR[8:0] <= 8\'d0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'Log1\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log2\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log3\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log4\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log5\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log6\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log7\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log8\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log9\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log10\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log11\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log12\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log13\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log14\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:641: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'Log15\' generates 8 bits.\n                                                                                      : ... In instance ArrayUltrasound\n   Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;  \n                                                                                        ^\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/ArrayUltrasound.v:727: Cannot find file containing module: \'IMG_TRI_BUFFER\'\nIMG_TRI_BUFFER IMG_TRI_BUFFER_inst (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s), 20 warning(s)\n'
module ArrayUltrasound(

	input          sysclk,

	output [15:0]  E_P,
	output [15:0]  E_N,

	output         HV_SW_CLR,
	output         HV_SW_LE,
	output         HV_SW_CLK,
	output         HV_SW_DOUT,
	output         HV_EN,

	output [3:0]   AX, 
	output [2:0]   AY,
	output         MT_CS,
	output         MT_Strobe,
	output         MT_Data,

	output         ADCLK, 

	input          FCO,
	input          OUTA,
	input          OUTB,
	input          OUTC,
	input          OUTD,
	input          OUTE,
	input          OUTF,
	input          OUTG,
	input          OUTH,

	output         SPI_CLK,
	inout          SPI_Data,
	output         SPI_CS,
	output         STBY,
	output         PWDN,

	output         sclk,
	output reg     sync,
	output reg     sdin,
	
	


	
	
	

	

	













	input            CC3200_SPI_CLK,
	input            CC3200_SPI_CS,
	output           CC3200_SPI_DIN,
	input            CC3200_SPI_DOUT,
	input            Envelop
	
);



   reg RST_n;
	
   reg [31:0] RST_Counter;
   
	always @(posedge sysclk) begin
		if(RST_Counter <= 32'd48) begin
			RST_Counter <= RST_Counter + 1'b1;
			RST_n <= 1'b1;
		end
		else if(RST_Counter <= 32'd96000) begin
			RST_Counter <= RST_Counter + 1'b1;
			RST_n <= 1'b0;
		end
		else begin
			RST_n <= 1'b1;
		end
    end



    
    reg        Enable;
    wire [1:0] Zoom  ;
    wire [5:0] Gain;
    reg  [7:0] Line_Num;
    wire [7:0] Line_Num_tmp;
    wire [8:0] Trans_Addr;
    wire [8:0] Trans_Data;
    

    
    ComWithCC3200    ComWithCC3200  (
	.CC3200_SPI_CLK  (CC3200_SPI_CLK),
	.CC3200_SPI_CS   (CC3200_SPI_CS),
	.CC3200_SPI_DIN  (CC3200_SPI_DIN),
	.CC3200_SPI_DOUT (CC3200_SPI_DOUT),
	.Envelop         (Envelop),
	.Line_Num        (Line_Num_tmp), 
	.Enable          (),
	.Zoom            (Zoom),
	.Gain            (Gain),
	.Trans_Data      (Trans_Data[8:1]),
	.Trans_Addr      (Trans_Addr)

);


	always @(posedge Envelop) begin
		
		Line_Num <= Line_Num_tmp;
	end
	
	
    reg [31:0] Idle_Counter;
	 
	 
    always @( posedge sysclk or posedge Envelop) begin
		if(Envelop) begin
			Idle_Counter <= 32'd0;
			Enable       <= 1'b1;
		end 
		else begin
			if(Idle_Counter <= 32'd25000000) begin
			    	Enable       <= 1'b1;
				   Idle_Counter <= Idle_Counter + 1'b1;
			end
			else begin
				   Enable      <= 1'b0;
			end
		end
	end	



	wire CLK_100M;
	
	wire CLK_20M;
	
	PLL	PLL_inst (
		.inclk0 ( sysclk ),
		.c0     ( CLK_100M ),
		.c1     (CLK_20M)
		);
	
	
	
	
	assign ADCLK=sysclk;
	
	wire   AD_CLK;
	
	reg [31:0]  Pulse_Counter;
	reg         Pr_Gate;
	reg         RX_Gate;
	reg         End_Gate;
	wire       Sample_Gate;
	
	


	
	reg [1:0] Focus_Num ;
	
	reg [1:0] Focus_Num_Pre ;

  


	always @(posedge RX_Gate or posedge Envelop) begin       
		if(Envelop) begin
			Focus_Num_Pre <= 2'b0;
	
		end
		else begin
			if(Focus_Num_Pre[1:0] == 2'b00) begin
				Focus_Num_Pre[1:0] <= 2'b10;
			end

			else if(Focus_Num_Pre[1:0] == 2'b10) begin
				Focus_Num_Pre[1:0] <= 2'b11;     
			end
			else if(Focus_Num_Pre[1:0] == 2'b11) begin
				Focus_Num_Pre[1:0] <= 2'b00;     
			end
			else 
			begin
				Focus_Num_Pre[1:0] <= 2'b00;     
			end			
			
		

		end
	end
	
	
	always @(posedge End_Gate) begin
		Focus_Num <= Focus_Num_Pre;
	end
	

	
	

	reg [31:0] Envelop_Counter;
	

	
	reg [31:0] Line_Period;
	
	always @(posedge Pr_Gate) begin
		case(Focus_Num[1:0]) 
			2'b00:
				Line_Period=32'd12000;
			2'b01:
				Line_Period=32'd12000;
			2'b10:
				Line_Period=32'd29000;
			2'b11:
				Line_Period=32'd29000;
		endcase
	end

    
 	always @(posedge CLK_100M or posedge Envelop) begin
		if(Envelop) begin
			  Pulse_Counter <= 32'd0;
		end
		else begin
			if(Pulse_Counter < 32'd3000)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b1;
				RX_Gate       <= 1'b0;
				End_Gate      <= 1'b0;
			end
			else if(Pulse_Counter < 32'd3250)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b0;
				RX_Gate       <= 1'b1;
				End_Gate      <= 1'b0;
			end
			else if(Pulse_Counter < Line_Period)  
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate      <= 1'b0;
				RX_Gate      <= 1'b0;
				End_Gate     <= 1'b0;
			end
			else if(Pulse_Counter < (Line_Period + 8'd80))
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b0;
				RX_Gate       <= 1'b0;
				End_Gate      <= 1'b1;
			end		
			else begin
				
				if(Focus_Num_Pre >2'b00) 
					Pulse_Counter <= 32'd0;
				else 
					Pulse_Counter <= 32'd65536;
					
				Pr_Gate     <= 1'b0;
				RX_Gate     <= 1'b0;
				End_Gate    <= 1'b0;
			end	
		end
	end 

	


 Transmit	Transmit_Inst(
	.Transmit_CLK   (CLK_100M),     
	.Line_Num       (Line_Num),
	.Focus_Num      (Focus_Num),
	.Pr_Gate        (Pr_Gate),
	.RX_Gate        (RX_Gate),
	.Sample_Gate    (Sample_Gate),
	.P              (E_P),
	.N              (E_N),
	.HV_SW_CLR      (HV_SW_CLR),
	.HV_SW_LE       (HV_SW_LE),
	.HV_SW_CLK      (HV_SW_CLK),
	.HV_SW_DOUT     (HV_SW_DOUT),
	.AX             (AX),
	.AY             (AY),
	.MT_CS          (MT_CS),
	.MT_Strobe      (MT_Strobe),
	.MT_Data        (MT_Data)	
	
);


	wire [11:0] Data_A,Data_B,Data_C,Data_D;
	
	wire [11:0] Data_E,Data_F,Data_G,Data_H;
	
	
	
	LVDS_AD	LVDS_AD_inst_A (
		.rx_in       ({OUTA,OUTB,OUTC,OUTD,OUTE,OUTF,OUTG,OUTH} ),
		.rx_inclock  ( FCO ),
		.rx_out      ({Data_A,Data_B,Data_C,Data_D,Data_E,Data_F,Data_G,Data_H} ),
		.rx_outclock ( AD_CLK )
		);
  
		

     
	assign HV_EN   = ~Enable; 
	
	    
   assign STBY    = ~Enable;
	
	assign PWDN    = ~Enable; 
	
    
  assign  SPI_CLK = CLK_20M;
  
  
	
  AD9273_SPI_Config AD9273_SPI_Config_Inst(
		.RST_n     (RST_n),
		.SPI_CLK   (SPI_CLK),
		.SPI_Data  (SPI_Data),
		.SPI_CS    (SPI_CS)
);
    

	reg [3:0]   div_Sclk;
	reg [7:0]   Send_Counter;
	reg [15:0]  Send_Data;
	reg [8:0]   Tgc_Counter;
	
	assign sclk = CLK_20M;
	
	wire [6:0] Tgc_Data;
	
	TGC_ROM	TGC_ROM_inst (
	.address ( Tgc_Counter[7:1] ),
	.clock   ( CLK_20M ),
	.q       (Tgc_Data )
	);	
	
	always @(posedge CLK_20M or posedge Pr_Gate) 
	 begin
		if(Pr_Gate) 
		   begin
			Tgc_Counter <= 9'd0;
			Send_Counter <= 8'b0;			
	   	end
		else  begin
			if(Tgc_Counter < 9'd255) begin
				if( Send_Counter <8'd3) begin
					sync         <= 1'b1;
					Send_Counter <= Send_Counter + 1'b1;


					Send_Data <= {2'b0,({1'b0,Tgc_Data[6:0]}+{1'b0,Gain[5:0],1'b0}),6'b0};  

				end
				else if(Send_Counter <8'd19) begin
					Send_Counter <= Send_Counter + 1'b1;
					sync         <= 1'b0;
					sdin         <= Send_Data[8'd18-Send_Counter];
				end
				else begin
					sync         <= 1'b1;
					Send_Counter <= 8'd0;
					Tgc_Counter  <= Tgc_Counter + 1'b1;
				end
			end
			else begin
			    
				if( Send_Counter <8'd3) begin
					sync         <= 1'b1;
					Send_Counter <= Send_Counter + 1'b1;

					Send_Data    <= {2'b0,8'h0,6'b0};  

				end
				else if(Send_Counter <8'd19) begin
					Send_Counter <= Send_Counter + 1'b1;
					sync         <= 1'b0;
					sdin         <= Send_Data[8'd18-Send_Counter];
				end
				else begin
					sync         <= 1'b1;
					Send_Counter <= 8'd0;
				end	
				
			end
		end
	end     
     
	  
	  
	  
	reg RX_Gate_Reg;
	
	reg Pr_Gate_Reg;
	
	reg Sample_Gate_Reg;
	
	reg End_Gate_Reg;
	
	always @(posedge AD_CLK) 
	 begin
		RX_Gate_Reg     <= RX_Gate;
		
		Pr_Gate_Reg     <= Pr_Gate;
		
		Sample_Gate_Reg <= Sample_Gate;
		
		End_Gate_Reg    <= End_Gate;
	 end   
   
    wire [15:0] DAS_Value;
	 
    wire        So_Gate;
	 
    wire [7:0] Coheren_Coff;
	 
	 
	Receive Receive_Inst(
		.AD_CLK      (AD_CLK),
		.Data_A      (Data_A),
		.Data_B      (Data_B),
		.Data_C      (Data_C),
		.Data_D      (Data_D),
		.Data_E      (Data_E),
		.Data_F      (Data_F),
		.Data_G      (Data_G),
		.Data_H      (Data_H),
		.Line_Num    (Line_Num),
		.Focus_Num   (Focus_Num),
		.Pr_Gate     (Pr_Gate_Reg),
		.RX_Gate     (RX_Gate_Reg),
		.Sample_Gate (Sample_Gate_Reg),
		.End_Gate    (End_Gate_Reg),
		.So_Gate     (So_Gate),
		.DAS_Value   (DAS_Value),
		.Coheren_Coff(Coheren_Coff),
	);
   

		

   

    wire [29:0] Match_Filter_Data; 
	 
    wire MF_Output_RDY;
	 
    wire MF_Output_Valid;
    
   	matchfilter MatchFilter_Inst(
		.clk            (AD_CLK),
		.reset_n        (1'b1),
		.ast_sink_data  (DAS_Value[14:0]),
		.ast_sink_valid (So_Gate),
		.ast_source_ready(1'b1),
		.ast_sink_error  (2'b00),
		.ast_source_data (Match_Filter_Data),
		.ast_sink_ready  (MF_Output_RDY),
		.ast_source_valid(MF_Output_Valid),
		.ast_source_error()
		);


   
    wire [29:0] ABS_Data;
	ABS	ABS_inst (
	.data    (Match_Filter_Data),
	.result  (ABS_Data)
	);
	
	

    
    wire LF_Valid;
	 
    wire [30:0] LF_Data;
	 
	lf LF_Inst(
		.clk             (AD_CLK),
		.reset_n         (1'b1),
		.ast_sink_data   (ABS_Data[26:12]),
		.ast_sink_valid  (MF_Output_Valid),
		.ast_source_ready(1'b1),
		.ast_sink_error  (2'b00),
		.ast_source_data (LF_Data),
		.ast_sink_ready  (),
		.ast_source_valid(LF_Valid),
		.ast_source_error()
		);


  wire [12:0] Log_IN;
  
  assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:14] > 18'd8091)?13'd8191:LF_Data[26:14]);
  

  wire [7:0] Log_OUT;
  
  
 LOG_Table	LOG_Table_inst (
	.address ( Log_IN),
	.clock   (AD_CLK ),
	.q       (Log_OUT )
	);


	
	reg [8:0] WR_RAM_ADDR;
	
	reg [7:0] LF_Reg;
	
	reg [7:0] Interlace_Counter; 
	
	reg [7:0] Log1,Log2,Log3,Log4,Log5,Log6,Log7,Log8,Log9,Log10,Log11,Log12,Log13,Log14,Log15;
	
	reg [11:0] Sum_Log;
	
	reg [15:0] Sample_Counter;
	
	reg        Seg_Enable;	
	
	reg [7:0] Interlace;
	
	always @(*) begin
		case(Zoom)
		2'b00:
			Interlace <= 8'd10;
		2'b01:
		    Interlace <= 8'd15;
		2'b10:
			Interlace <= 8'd19;
		2'b11:
			Interlace <= 8'd24;
		endcase
	end
	
   wire [7:0] Base_Noise1;
	
   wire [7:0] Base_Noise2;
	

    wire [7:0] Line_Num_Test;
	 
	Test	Test_inst (
	.address   (1'b0 ),
	.clock     (AD_CLK ),
	.q         ({Base_Noise1,Base_Noise2})
	);
		
	
	
	always @(posedge AD_CLK or negedge LF_Valid ) begin
		if(~LF_Valid) begin
			Interlace_Counter <= 8'd0;
			WR_RAM_ADDR[8:0] <= 8'd0;
			Sample_Counter <= 16'd0;
		end
		else begin
			Log15 <= Log14;
			Log14 <= Log13;
			Log13 <= Log12;
			Log12 <= Log11;
			Log11 <= Log10;
			Log10 <= Log9;
			Log9  <= Log8;
			Log8  <= Log7;
			Log7  <= Log6;
			Log6  <= Log5;
			Log5  <= Log4;
			Log4  <= Log3;
			Log3  <= Log2;
			Log2  <= Log1;
			Log1  <= Log_OUT;
			Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;		
		   
		    if(Sample_Counter <16'd16000) begin
				Sample_Counter <= Sample_Counter + 1'b1;
			end
			
			if(Sample_Counter <=16'd2000) begin
				if(Focus_Num[1:0] == 2'b00) begin
					Seg_Enable <= 1'b1;
				end
				else begin
					Seg_Enable <= 1'b0;
				end
				
				LF_Reg <= (Sum_Log[11:4]>Base_Noise1)? (Sum_Log[11:4]-Base_Noise1): 8'd0 ;				
			end

			else begin
				if(Focus_Num[1:0] == 2'b11) begin
					Seg_Enable <= 1'b1;
				end
				else begin
					Seg_Enable <= 1'b0;
				end	
				LF_Reg <= (Sum_Log[11:4]>Base_Noise2)? (Sum_Log[11:4]-Base_Noise2): 8'd0 ;		
			end
			
		    
			if(Interlace_Counter < Interlace) begin   
				Interlace_Counter <= Interlace_Counter + 1'b1;
			end
			else begin
				if(WR_RAM_ADDR[8:0] <9'd511) begin
					WR_RAM_ADDR[8:0] <= WR_RAM_ADDR[8:0]  + 1'b1;
				end
				Interlace_Counter <= 8'd0;
			end
		end
		
	end


	
	


	reg [1:0] Toggle;

	always @(posedge Envelop) begin
		Toggle  <= Toggle + 1'b1;
	end
	
	
	
	wire [7:0] Trans_Data1,Trans_Data2;
	
	
IMG_TRI_BUFFER	IMG_TRI_BUFFER_inst (
	.data        (LF_Reg),
	.rdaddress_a ({Toggle[1:0]-2'b01,Trans_Addr}),
	.rdaddress_b ({Toggle[1:0]-2'b10,Trans_Addr} ),
	.rdclock     (CC3200_SPI_CS ),
	.wraddress   ({Toggle[1:0],WR_RAM_ADDR}),
	.wrclock     (AD_CLK ),
	.wren       (LF_Valid & Seg_Enable ),
	.qa         (Trans_Data1 ),
	.qb         (Trans_Data2 )
	);
	
	
	

assign Trans_Data ={1'b0,Trans_Data1} + {1'b0,Trans_Data2};
	




	
    
endmodule
module ArrayUltrasound(

	input          sysclk,

	output [15:0]  E_P,
	output [15:0]  E_N,

	output         HV_SW_CLR,
	output         HV_SW_LE,
	output         HV_SW_CLK,
	output         HV_SW_DOUT,
	output         HV_EN,

	output [3:0]   AX, 
	output [2:0]   AY,
	output         MT_CS,
	output         MT_Strobe,
	output         MT_Data,

	output         ADCLK, 

	input          FCO,
	input          OUTA,
	input          OUTB,
	input          OUTC,
	input          OUTD,
	input          OUTE,
	input          OUTF,
	input          OUTG,
	input          OUTH,

	output         SPI_CLK,
	inout          SPI_Data,
	output         SPI_CS,
	output         STBY,
	output         PWDN,

	output         sclk,
	output reg     sync,
	output reg     sdin,
	
	


	
	
	

	

	













	input            CC3200_SPI_CLK,
	input            CC3200_SPI_CS,
	output           CC3200_SPI_DIN,
	input            CC3200_SPI_DOUT,
	input            Envelop
	
);




   reg RST_n;
	
   reg [31:0] RST_Counter;
   
	always @(posedge sysclk) begin
		if(RST_Counter <= 32'd48) begin
			RST_Counter <= RST_Counter + 1'b1;
			RST_n <= 1'b1;
		end
		else if(RST_Counter <= 32'd96000) begin
			RST_Counter <= RST_Counter + 1'b1;
			RST_n <= 1'b0;
		end
		else begin
			RST_n <= 1'b1;
		end
    end



    
    reg        Enable;
    wire [1:0] Zoom  ;
    wire [5:0] Gain;
    reg  [7:0] Line_Num;
    wire [7:0] Line_Num_tmp;
    wire [8:0] Trans_Addr;
    wire [8:0] Trans_Data;
    

    
    ComWithCC3200    ComWithCC3200  (
	.CC3200_SPI_CLK  (CC3200_SPI_CLK),
	.CC3200_SPI_CS   (CC3200_SPI_CS),
	.CC3200_SPI_DIN  (CC3200_SPI_DIN),
	.CC3200_SPI_DOUT (CC3200_SPI_DOUT),
	.Envelop         (Envelop),
	.Line_Num        (Line_Num_tmp), 
	.Enable          (),
	.Zoom            (Zoom),
	.Gain            (Gain),
	.Trans_Data      (Trans_Data[8:1]),
	.Trans_Addr      (Trans_Addr)

);


	always @(posedge Envelop) begin
		
		Line_Num <= Line_Num_tmp;
	end
	
	
    reg [31:0] Idle_Counter;
	 
	 
    always @( posedge sysclk or posedge Envelop) begin
		if(Envelop) begin
			Idle_Counter <= 32'd0;
			Enable       <= 1'b1;
		end 
		else begin
			if(Idle_Counter <= 32'd25000000) begin
			    	Enable       <= 1'b1;
				   Idle_Counter <= Idle_Counter + 1'b1;
			end
			else begin
				   Enable      <= 1'b0;
			end
		end
	end	



	wire CLK_100M;
	
	wire CLK_20M;
	
	PLL	PLL_inst (
		.inclk0 ( sysclk ),
		.c0     ( CLK_100M ),
		.c1     (CLK_20M)
		);
	
	
	
	
	assign ADCLK=sysclk;
	
	wire   AD_CLK;
	
	reg [31:0]  Pulse_Counter;
	reg         Pr_Gate;
	reg         RX_Gate;
	reg         End_Gate;
	wire       Sample_Gate;
	
	


	
	reg [1:0] Focus_Num ;
	
	reg [1:0] Focus_Num_Pre ;

  


	always @(posedge RX_Gate or posedge Envelop) begin       
		if(Envelop) begin
			Focus_Num_Pre <= 2'b0;
	
		end
		else begin
			if(Focus_Num_Pre[1:0] == 2'b00) begin
				Focus_Num_Pre[1:0] <= 2'b10;
			end

			else if(Focus_Num_Pre[1:0] == 2'b10) begin
				Focus_Num_Pre[1:0] <= 2'b11;     
			end
			else if(Focus_Num_Pre[1:0] == 2'b11) begin
				Focus_Num_Pre[1:0] <= 2'b00;     
			end
			else 
			begin
				Focus_Num_Pre[1:0] <= 2'b00;     
			end			
			
		

		end
	end
	
	
	always @(posedge End_Gate) begin
		Focus_Num <= Focus_Num_Pre;
	end
	

	
	

	reg [31:0] Envelop_Counter;
	

	
	reg [31:0] Line_Period;
	
	always @(posedge Pr_Gate) begin
		case(Focus_Num[1:0]) 
			2'b00:
				Line_Period=32'd12000;
			2'b01:
				Line_Period=32'd12000;
			2'b10:
				Line_Period=32'd29000;
			2'b11:
				Line_Period=32'd29000;
		endcase
	end

    
 	always @(posedge CLK_100M or posedge Envelop) begin
		if(Envelop) begin
			  Pulse_Counter <= 32'd0;
		end
		else begin
			if(Pulse_Counter < 32'd3000)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b1;
				RX_Gate       <= 1'b0;
				End_Gate      <= 1'b0;
			end
			else if(Pulse_Counter < 32'd3250)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b0;
				RX_Gate       <= 1'b1;
				End_Gate      <= 1'b0;
			end
			else if(Pulse_Counter < Line_Period)  
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate      <= 1'b0;
				RX_Gate      <= 1'b0;
				End_Gate     <= 1'b0;
			end
			else if(Pulse_Counter < (Line_Period + 8'd80))
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate       <= 1'b0;
				RX_Gate       <= 1'b0;
				End_Gate      <= 1'b1;
			end		
			else begin
				
				if(Focus_Num_Pre >2'b00) 
					Pulse_Counter <= 32'd0;
				else 
					Pulse_Counter <= 32'd65536;
					
				Pr_Gate     <= 1'b0;
				RX_Gate     <= 1'b0;
				End_Gate    <= 1'b0;
			end	
		end
	end 

	


 Transmit	Transmit_Inst(
	.Transmit_CLK   (CLK_100M),     
	.Line_Num       (Line_Num),
	.Focus_Num      (Focus_Num),
	.Pr_Gate        (Pr_Gate),
	.RX_Gate        (RX_Gate),
	.Sample_Gate    (Sample_Gate),
	.P              (E_P),
	.N              (E_N),
	.HV_SW_CLR      (HV_SW_CLR),
	.HV_SW_LE       (HV_SW_LE),
	.HV_SW_CLK      (HV_SW_CLK),
	.HV_SW_DOUT     (HV_SW_DOUT),
	.AX             (AX),
	.AY             (AY),
	.MT_CS          (MT_CS),
	.MT_Strobe      (MT_Strobe),
	.MT_Data        (MT_Data)	
	
);


	wire [11:0] Data_A,Data_B,Data_C,Data_D;
	
	wire [11:0] Data_E,Data_F,Data_G,Data_H;
	
	
	
	LVDS_AD	LVDS_AD_inst_A (
		.rx_in       ({OUTA,OUTB,OUTC,OUTD,OUTE,OUTF,OUTG,OUTH} ),
		.rx_inclock  ( FCO ),
		.rx_out      ({Data_A,Data_B,Data_C,Data_D,Data_E,Data_F,Data_G,Data_H} ),
		.rx_outclock ( AD_CLK )
		);
  
		

     
	assign HV_EN   = ~Enable; 
	
	    
   assign STBY    = ~Enable;
	
	assign PWDN    = ~Enable; 
	
    
  assign  SPI_CLK = CLK_20M;
  
  
	
  AD9273_SPI_Config AD9273_SPI_Config_Inst(
		.RST_n     (RST_n),
		.SPI_CLK   (SPI_CLK),
		.SPI_Data  (SPI_Data),
		.SPI_CS    (SPI_CS)
);
    

	reg [3:0]   div_Sclk;
	reg [7:0]   Send_Counter;
	reg [15:0]  Send_Data;
	reg [8:0]   Tgc_Counter;
	
	assign sclk = CLK_20M;
	
	wire [6:0] Tgc_Data;
	
	TGC_ROM	TGC_ROM_inst (
	.address ( Tgc_Counter[7:1] ),
	.clock   ( CLK_20M ),
	.q       (Tgc_Data )
	);	
	
	always @(posedge CLK_20M or posedge Pr_Gate) 
	 begin
		if(Pr_Gate) 
		   begin
			Tgc_Counter <= 9'd0;
			Send_Counter <= 8'b0;			
	   	end
		else  begin
			if(Tgc_Counter < 9'd255) begin
				if( Send_Counter <8'd3) begin
					sync         <= 1'b1;
					Send_Counter <= Send_Counter + 1'b1;


					Send_Data <= {2'b0,({1'b0,Tgc_Data[6:0]}+{1'b0,Gain[5:0],1'b0}),6'b0};  

				end
				else if(Send_Counter <8'd19) begin
					Send_Counter <= Send_Counter + 1'b1;
					sync         <= 1'b0;
					sdin         <= Send_Data[8'd18-Send_Counter];
				end
				else begin
					sync         <= 1'b1;
					Send_Counter <= 8'd0;
					Tgc_Counter  <= Tgc_Counter + 1'b1;
				end
			end
			else begin
			    
				if( Send_Counter <8'd3) begin
					sync         <= 1'b1;
					Send_Counter <= Send_Counter + 1'b1;

					Send_Data    <= {2'b0,8'h0,6'b0};  

				end
				else if(Send_Counter <8'd19) begin
					Send_Counter <= Send_Counter + 1'b1;
					sync         <= 1'b0;
					sdin         <= Send_Data[8'd18-Send_Counter];
				end
				else begin
					sync         <= 1'b1;
					Send_Counter <= 8'd0;
				end	
				
			end
		end
	end     
     
	  
	  
	  
	reg RX_Gate_Reg;
	
	reg Pr_Gate_Reg;
	
	reg Sample_Gate_Reg;
	
	reg End_Gate_Reg;
	
	always @(posedge AD_CLK) 
	 begin
		RX_Gate_Reg     <= RX_Gate;
		
		Pr_Gate_Reg     <= Pr_Gate;
		
		Sample_Gate_Reg <= Sample_Gate;
		
		End_Gate_Reg    <= End_Gate;
	 end   
   
    wire [15:0] DAS_Value;
	 
    wire        So_Gate;
	 
    wire [7:0] Coheren_Coff;
	 
	 
	Receive Receive_Inst(
		.AD_CLK      (AD_CLK),
		.Data_A      (Data_A),
		.Data_B      (Data_B),
		.Data_C      (Data_C),
		.Data_D      (Data_D),
		.Data_E      (Data_E),
		.Data_F      (Data_F),
		.Data_G      (Data_G),
		.Data_H      (Data_H),
		.Line_Num    (Line_Num),
		.Focus_Num   (Focus_Num),
		.Pr_Gate     (Pr_Gate_Reg),
		.RX_Gate     (RX_Gate_Reg),
		.Sample_Gate (Sample_Gate_Reg),
		.End_Gate    (End_Gate_Reg),
		.So_Gate     (So_Gate),
		.DAS_Value   (DAS_Value),
		.Coheren_Coff(Coheren_Coff),
	);
   

		

   

    wire [29:0] Match_Filter_Data; 
	 
    wire MF_Output_RDY;
	 
    wire MF_Output_Valid;
    
   	matchfilter MatchFilter_Inst(
		.clk            (AD_CLK),
		.reset_n        (1'b1),
		.ast_sink_data  (DAS_Value[14:0]),
		.ast_sink_valid (So_Gate),
		.ast_source_ready(1'b1),
		.ast_sink_error  (2'b00),
		.ast_source_data (Match_Filter_Data),
		.ast_sink_ready  (MF_Output_RDY),
		.ast_source_valid(MF_Output_Valid),
		.ast_source_error()
		);


   
    wire [29:0] ABS_Data;
	ABS	ABS_inst (
	.data    (Match_Filter_Data),
	.result  (ABS_Data)
	);
	
	

    
    wire LF_Valid;
	 
    wire [30:0] LF_Data;
	 
	lf LF_Inst(
		.clk             (AD_CLK),
		.reset_n         (1'b1),
		.ast_sink_data   (ABS_Data[26:12]),
		.ast_sink_valid  (MF_Output_Valid),
		.ast_source_ready(1'b1),
		.ast_sink_error  (2'b00),
		.ast_source_data (LF_Data),
		.ast_sink_ready  (),
		.ast_source_valid(LF_Valid),
		.ast_source_error()
		);


  wire [12:0] Log_IN;
  
  assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:14] > 18'd8091)?13'd8191:LF_Data[26:14]);
  

  wire [7:0] Log_OUT;
  
  
 LOG_Table	LOG_Table_inst (
	.address ( Log_IN),
	.clock   (AD_CLK ),
	.q       (Log_OUT )
	);


	
	reg [8:0] WR_RAM_ADDR;
	
	reg [7:0] LF_Reg;
	
	reg [7:0] Interlace_Counter; 
	
	reg [7:0] Log1,Log2,Log3,Log4,Log5,Log6,Log7,Log8,Log9,Log10,Log11,Log12,Log13,Log14,Log15;
	
	reg [11:0] Sum_Log;
	
	reg [15:0] Sample_Counter;
	
	reg        Seg_Enable;	
	
	reg [7:0] Interlace;
	
	always @(*) begin
		case(Zoom)
		2'b00:
			Interlace <= 8'd10;
		2'b01:
		    Interlace <= 8'd15;
		2'b10:
			Interlace <= 8'd19;
		2'b11:
			Interlace <= 8'd24;
		endcase
	end
	
   wire [7:0] Base_Noise1;
	
   wire [7:0] Base_Noise2;
	

    wire [7:0] Line_Num_Test;
	 
	Test	Test_inst (
	.address   (1'b0 ),
	.clock     (AD_CLK ),
	.q         ({Base_Noise1,Base_Noise2})
	);
		
	
	
	always @(posedge AD_CLK or negedge LF_Valid ) begin
		if(~LF_Valid) begin
			Interlace_Counter <= 8'd0;
			WR_RAM_ADDR[8:0] <= 8'd0;
			Sample_Counter <= 16'd0;
		end
		else begin
			Log15 <= Log14;
			Log14 <= Log13;
			Log13 <= Log12;
			Log12 <= Log11;
			Log11 <= Log10;
			Log10 <= Log9;
			Log9  <= Log8;
			Log8  <= Log7;
			Log7  <= Log6;
			Log6  <= Log5;
			Log5  <= Log4;
			Log4  <= Log3;
			Log3  <= Log2;
			Log2  <= Log1;
			Log1  <= Log_OUT;
			Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;		
		   
		    if(Sample_Counter <16'd16000) begin
				Sample_Counter <= Sample_Counter + 1'b1;
			end
			
			if(Sample_Counter <=16'd2000) begin
				if(Focus_Num[1:0] == 2'b00) begin
					Seg_Enable <= 1'b1;
				end
				else begin
					Seg_Enable <= 1'b0;
				end
				
				LF_Reg <= (Sum_Log[11:4]>Base_Noise1)? (Sum_Log[11:4]-Base_Noise1): 8'd0 ;				
			end

			else begin
				if(Focus_Num[1:0] == 2'b11) begin
					Seg_Enable <= 1'b1;
				end
				else begin
					Seg_Enable <= 1'b0;
				end	
				LF_Reg <= (Sum_Log[11:4]>Base_Noise2)? (Sum_Log[11:4]-Base_Noise2): 8'd0 ;		
			end
			
		    
			if(Interlace_Counter < Interlace) begin   
				Interlace_Counter <= Interlace_Counter + 1'b1;
			end
			else begin
				if(WR_RAM_ADDR[8:0] <9'd511) begin
					WR_RAM_ADDR[8:0] <= WR_RAM_ADDR[8:0]  + 1'b1;
				end
				Interlace_Counter <= 8'd0;
			end
		end
		
	end


	
	


	reg [1:0] Toggle;

	always @(posedge Envelop) begin
		Toggle  <= Toggle + 1'b1;
	end
	
	
	
	wire [7:0] Trans_Data1,Trans_Data2;
	
	
IMG_TRI_BUFFER	IMG_TRI_BUFFER_inst (
	.data        (LF_Reg),
	.rdaddress_a ({Toggle[1:0]-2'b01,Trans_Addr}),
	.rdaddress_b ({Toggle[1:0]-2'b10,Trans_Addr} ),
	.rdclock     (CC3200_SPI_CS ),
	.wraddress   ({Toggle[1:0],WR_RAM_ADDR}),
	.wrclock     (AD_CLK ),
	.wren       (LF_Valid & Seg_Enable ),
	.qa         (Trans_Data1 ),
	.qb         (Trans_Data2 )
	);
	
	
	

assign Trans_Data ={1'b0,Trans_Data1} + {1'b0,Trans_Data2};
	




	
    
endmodule