data/full_repos/permissive/447668373/SISO/siso.v
data/verilator_xmls/74c64489-ee6a-4885-91cf-9ec8ae7d8b84.xml
module dff(d, clk, reset, q);
    input d, clk, reset;
    output q;
    reg q = 0;
    always @ (posedge clk)
    begin
        if(reset == 1'b1)
            q <= 1'b0;
        else
        begin
            q <= d;
        end
    end
endmodule
module dff(d, clk, reset, q);

    input d, clk, reset;
    output q;
    reg q = 0;
    always @ (posedge clk)
    begin
        if(reset == 1'b1)
            q <= 1'b0;
        else
        begin
            q <= d;
        end
    end
endmodule