data/full_repos/permissive/409594175/made/SignExtend1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/409594175/made/SignExtend1.v:6: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                         : ... In instance SignExtend1\n    assign data_out_32 = {{32{1\'b0}}, data_in};\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module SignExtend1(
    input  wire         data_in,
    output wire [31:0]  data_out_32 
);

    assign data_out_32 = {{32{1'b0}}, data_in};

endmodule
module SignExtend1(
    input  wire         data_in,
    output wire [31:0]  data_out_32 
);


    assign data_out_32 = {{32{1'b0}}, data_in};

endmodule