data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v:50: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 4 bits.\n                                                                                 : ... In instance part2\n   3\'b011: ALUtemp = (Data|Data_b) ? 8\'b00000001 : 8\'b0;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rippleadder(a, b, c_in, s, c_out);
	
	input [3:0]a,b;
	input c_in;
	output [3:0]s;
	output [3:0]c_out;
	
	fulladder u0(a[0],b[0],c_in,s[0],c_out[0]);
	fulladder u1(a[1],b[1],c_out[0],s[1],c_out[1]);
	fulladder u2(a[2],b[2],c_out[1],s[2],c_out[2]);
	fulladder u3(a[3],b[3],c_out[2],s[3],c_out[3]);

endmodule
module rippleadder(a, b, c_in, s, c_out);

	
	input [3:0]a,b;
	input c_in;
	output [3:0]s;
	output [3:0]c_out;
	
	fulladder u0(a[0],b[0],c_in,s[0],c_out[0]);
	fulladder u1(a[1],b[1],c_out[0],s[1],c_out[1]);
	fulladder u2(a[2],b[2],c_out[1],s[2],c_out[2]);
	fulladder u3(a[3],b[3],c_out[2],s[3],c_out[3]);

endmodule