data/full_repos/permissive/522095295/alu.v
1: b'%Error: data/full_repos/permissive/522095295/alu.v:1: Cannot find include file: itype.v\n`include "itype.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v.sv\n             itype.v\n             itype.v.v\n             itype.v.sv\n             obj_dir/itype.v\n             obj_dir/itype.v.v\n             obj_dir/itype.v.sv\n%Error: data/full_repos/permissive/522095295/alu.v:2: Cannot find include file: opcode.v\n`include "opcode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:67: Define or directive not defined: \'`RTYPE\'\n            if (itype_i == `RTYPE) begin\n                           ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if (itype_i == `RTYPE) begin\n                                 ^\n%Error: data/full_repos/permissive/522095295/alu.v:69: Define or directive not defined: \'`ADD7\'\n               if (r7 == `ADD7 && r3 == `ADD3) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:69: Define or directive not defined: \'`ADD3\'\n               if (r7 == `ADD7 && r3 == `ADD3) begin\n                                        ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:73: Define or directive not defined: \'`SUB7\'\n               else if (r7 == `SUB7 && r3 == `SUB3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:73: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n               else if (r7 == `SUB7 && r3 == `SUB3) begin\n                                    ^~\n%Error: data/full_repos/permissive/522095295/alu.v:73: Define or directive not defined: \'`SUB3\'\n               else if (r7 == `SUB7 && r3 == `SUB3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:77: Define or directive not defined: \'`SLL7\'\n               else if (r7 == `SLL7 && r3 == `SLL3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:77: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n               else if (r7 == `SLL7 && r3 == `SLL3) begin\n                                    ^~\n%Error: data/full_repos/permissive/522095295/alu.v:77: Define or directive not defined: \'`SLL3\'\n               else if (r7 == `SLL7 && r3 == `SLL3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:81: Define or directive not defined: \'`SLT7\'\n               else if (r7 == `SLT7 && r3 == `SLT3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:81: Define or directive not defined: \'`SLT3\'\n               else if (r7 == `SLT7 && r3 == `SLT3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:90: Define or directive not defined: \'`SLTU7\'\n               else if (r7 == `SLTU7 && r3 == `SLTU3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:90: Define or directive not defined: \'`SLTU3\'\n               else if (r7 == `SLTU7 && r3 == `SLTU3) begin\n                                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:99: Define or directive not defined: \'`XOR7\'\n               else if (r7 == `XOR7 && r3 == `XOR3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:99: Define or directive not defined: \'`XOR3\'\n               else if (r7 == `XOR7 && r3 == `XOR3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:103: Define or directive not defined: \'`SRL7\'\n               else if (r7 == `SRL7 && r3 == `SRL3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:103: Define or directive not defined: \'`SRL3\'\n               else if (r7 == `SRL7 && r3 == `SRL3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:107: Define or directive not defined: \'`SRA7\'\n               else if (r7 == `SRA7 && r3 == `SRA3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:107: Define or directive not defined: \'`SRA3\'\n               else if (r7 == `SRA7 && r3 == `SRA3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:111: Define or directive not defined: \'`OR7\'\n               else if (r7 == `OR7 && r3 == `OR3) begin\n                              ^~~~\n%Error: data/full_repos/permissive/522095295/alu.v:111: Define or directive not defined: \'`OR3\'\n               else if (r7 == `OR7 && r3 == `OR3) begin\n                                            ^~~~\n%Error: data/full_repos/permissive/522095295/alu.v:115: Define or directive not defined: \'`AND7\'\n               else if (r7 == `AND7 && r3 == `AND3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:115: Define or directive not defined: \'`AND3\'\n               else if (r7 == `AND7 && r3 == `AND3) begin\n                                             ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:119: Define or directive not defined: \'`ITYPE\'\n            else if (itype_i == `ITYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:121: Define or directive not defined: \'`ADDI3\'\n               if (r3 == `ADDI3) begin\n                         ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:125: Define or directive not defined: \'`SLTI3\'\n               else if (r3 == `SLTI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:134: Define or directive not defined: \'`SLTIU3\'\n               else if (r3 == `SLTIU3) begin\n                              ^~~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:143: Define or directive not defined: \'`XORI3\'\n               else if (r3 == `XORI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:147: Define or directive not defined: \'`ORI3\'\n               else if (r3 == `ORI3) begin\n                              ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:151: Define or directive not defined: \'`ANDI3\'\n               else if (r3 == `ANDI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:155: Define or directive not defined: \'`SLLI7\'\n               else if (r7 == `SLLI7 && r3 == `SLLI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:155: Define or directive not defined: \'`SLLI3\'\n               else if (r7 == `SLLI7 && r3 == `SLLI3) begin\n                                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:159: Define or directive not defined: \'`SRLI7\'\n               else if (r7 == `SRLI7 && r3 == `SRLI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:159: Define or directive not defined: \'`SRLI3\'\n               else if (r7 == `SRLI7 && r3 == `SRLI3) begin\n                                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:163: Define or directive not defined: \'`SRAI7\'\n               else if (r7 == `SRAI7 && r3 == `SRAI3) begin\n                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:163: Define or directive not defined: \'`SRAI3\'\n               else if (r7 == `SRAI7 && r3 == `SRAI3) begin\n                                              ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:167: Define or directive not defined: \'`STYPE\'\n            else if (itype_i == `STYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:171: Define or directive not defined: \'`BTYPE\'\n            else if (itype_i == `BTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:173: Define or directive not defined: \'`BEQ3\'\n               if (r3 == `BEQ3) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:181: Define or directive not defined: \'`BNE3\'\n               if (r3 == `BNE3) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:189: Define or directive not defined: \'`BLT3\'\n               if (r3 == `BLT3) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:198: Define or directive not defined: \'`BGE3\'\n               if (r3 == `BGE3) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:206: Define or directive not defined: \'`BLTU3\'\n               if (r3 == `BLTU3) begin\n                         ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:214: Define or directive not defined: \'`BGEU3\'\n               if (r3 == `BGEU3) begin\n                         ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:222: Define or directive not defined: \'`UTYPE\'\n            else if (itype_i == `UTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:225: Define or directive not defined: \'`LTYPE\'\n            else if (itype_i == `LTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/alu.v:228: Define or directive not defined: \'`JRTYPE\'\n            else if (itype_i == `JRTYPE) begin\n                                ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module alu
(
   input wire clk,
   input wire reset,
   input wire [31:0] readd_a_i,
   input wire [31:0] readd_b_i,
   input wire [31:0] readd_pass_i,
   input wire readin_a_i,
   input wire readin_b_i,
   input wire readin_pass_i,
   input wire [2:0] stage_i,
   input wire [31:0] ir_i,
   input wire [4:0] itype_i,
   output reg [31:0] y_o,
   output reg [31:0] pass_o,
   input wire [31:0] pc_i
);
   reg [31:0] a;
   reg [31:0] b;
   reg [31:0] pass;
   

   always @ (posedge readin_a_i) begin
      if (reset) begin
         a <= 0;
      end
      else begin
         if (readin_a_i) begin
            a <= readd_a_i;
         end
      end
   end

   always @ (posedge readin_b_i) begin
      if (reset) begin
         b <= 0;
      end
      else begin
         if (readin_b_i) begin
            b <= readd_b_i;
         end
      end
   end

   always @ (posedge readin_pass_i) begin
      if (reset) begin
         pass <= 0;
      end
      else begin
         if (readin_pass_i) begin
            pass <= readd_pass_i;
         end
      end
   end

   wire [6:0] r7 = ir_i[31:25];
   wire [2:0] r3 = ir_i[14:12];


   always @ (posedge clk) begin
      if (!reset) begin

         if (stage_i == 3) begin
            if (itype_i == `RTYPE) begin

               if (r7 == `ADD7 && r3 == `ADD3) begin
                     y_o <= a + b;
               end

               else if (r7 == `SUB7 && r3 == `SUB3) begin
                     y_o <= a - b;
               end

               else if (r7 == `SLL7 && r3 == `SLL3) begin
                     y_o <= a << b;
               end

               else if (r7 == `SLT7 && r3 == `SLT3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r7 == `SLTU7 && r3 == `SLTU3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r7 == `XOR7 && r3 == `XOR3) begin
                     y_o <= a ^ b;
               end

               else if (r7 == `SRL7 && r3 == `SRL3) begin
                     y_o <= a >> b;
               end

               else if (r7 == `SRA7 && r3 == `SRA3) begin
                     y_o <= a >>> b;
               end

               else if (r7 == `OR7 && r3 == `OR3) begin
                     y_o <= a | b;
               end

               else if (r7 == `AND7 && r3 == `AND3) begin
                     y_o <= a & b;
               end
            end
            else if (itype_i == `ITYPE) begin

               if (r3 == `ADDI3) begin
                     y_o <= a + b;
               end

               else if (r3 == `SLTI3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r3 == `SLTIU3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r3 == `XORI3) begin
                     y_o <= a ^ b;
               end

               else if (r3 == `ORI3) begin
                     y_o <= a | b;
               end

               else if (r3 == `ANDI3) begin
                     y_o <= a & b;
               end

               else if (r7 == `SLLI7 && r3 == `SLLI3) begin
                     y_o <= a << b;
               end

               else if (r7 == `SRLI7 && r3 == `SRLI3) begin
                     y_o <= a >> b;
               end

               else if (r7 == `SRAI7 && r3 == `SRAI3) begin
                     y_o <= a >>> b;
               end
            end
            else if (itype_i == `STYPE) begin
               y_o <= a + b;
               pass_o <= pass;
            end
            else if (itype_i == `BTYPE) begin

               if (r3 == `BEQ3) begin
                  if (a == b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BNE3) begin
                  if ((a - b) != 0) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BLT3) begin
                  if (a < b) begin
                     y_o <= pass;
                  end
                  else begin
                     y_o <= 4;
                  end
               end

               if (r3 == `BGE3) begin
                  if (a >= b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BLTU3) begin
                  if (a < b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BGEU3) begin
                  if (a > b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end
            end
            else if (itype_i == `UTYPE) begin
               y_o <= a;
            end
            else if (itype_i == `LTYPE) begin
               y_o <= a + b;
            end
            else if (itype_i == `JRTYPE) begin
               y_o <= a;
            end
         end
      end
   end

   initial begin
      a = 0;
      b = 0;
      pass = 0;
      y_o = 0;
      pass_o = 0;
   end
endmodule
module alu
(
   input wire clk,
   input wire reset,
   input wire [31:0] readd_a_i,
   input wire [31:0] readd_b_i,
   input wire [31:0] readd_pass_i,
   input wire readin_a_i,
   input wire readin_b_i,
   input wire readin_pass_i,
   input wire [2:0] stage_i,
   input wire [31:0] ir_i,
   input wire [4:0] itype_i,
   output reg [31:0] y_o,
   output reg [31:0] pass_o,
   input wire [31:0] pc_i
);

   reg [31:0] a;
   reg [31:0] b;
   reg [31:0] pass;
   

   always @ (posedge readin_a_i) begin
      if (reset) begin
         a <= 0;
      end
      else begin
         if (readin_a_i) begin
            a <= readd_a_i;
         end
      end
   end

   always @ (posedge readin_b_i) begin
      if (reset) begin
         b <= 0;
      end
      else begin
         if (readin_b_i) begin
            b <= readd_b_i;
         end
      end
   end

   always @ (posedge readin_pass_i) begin
      if (reset) begin
         pass <= 0;
      end
      else begin
         if (readin_pass_i) begin
            pass <= readd_pass_i;
         end
      end
   end

   wire [6:0] r7 = ir_i[31:25];
   wire [2:0] r3 = ir_i[14:12];


   always @ (posedge clk) begin
      if (!reset) begin

         if (stage_i == 3) begin
            if (itype_i == `RTYPE) begin

               if (r7 == `ADD7 && r3 == `ADD3) begin
                     y_o <= a + b;
               end

               else if (r7 == `SUB7 && r3 == `SUB3) begin
                     y_o <= a - b;
               end

               else if (r7 == `SLL7 && r3 == `SLL3) begin
                     y_o <= a << b;
               end

               else if (r7 == `SLT7 && r3 == `SLT3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r7 == `SLTU7 && r3 == `SLTU3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r7 == `XOR7 && r3 == `XOR3) begin
                     y_o <= a ^ b;
               end

               else if (r7 == `SRL7 && r3 == `SRL3) begin
                     y_o <= a >> b;
               end

               else if (r7 == `SRA7 && r3 == `SRA3) begin
                     y_o <= a >>> b;
               end

               else if (r7 == `OR7 && r3 == `OR3) begin
                     y_o <= a | b;
               end

               else if (r7 == `AND7 && r3 == `AND3) begin
                     y_o <= a & b;
               end
            end
            else if (itype_i == `ITYPE) begin

               if (r3 == `ADDI3) begin
                     y_o <= a + b;
               end

               else if (r3 == `SLTI3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r3 == `SLTIU3) begin
                     if (a < b) begin
                        y_o <= 1;
                     end
                     else begin
                        y_o <= 0;
                     end
               end

               else if (r3 == `XORI3) begin
                     y_o <= a ^ b;
               end

               else if (r3 == `ORI3) begin
                     y_o <= a | b;
               end

               else if (r3 == `ANDI3) begin
                     y_o <= a & b;
               end

               else if (r7 == `SLLI7 && r3 == `SLLI3) begin
                     y_o <= a << b;
               end

               else if (r7 == `SRLI7 && r3 == `SRLI3) begin
                     y_o <= a >> b;
               end

               else if (r7 == `SRAI7 && r3 == `SRAI3) begin
                     y_o <= a >>> b;
               end
            end
            else if (itype_i == `STYPE) begin
               y_o <= a + b;
               pass_o <= pass;
            end
            else if (itype_i == `BTYPE) begin

               if (r3 == `BEQ3) begin
                  if (a == b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BNE3) begin
                  if ((a - b) != 0) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BLT3) begin
                  if (a < b) begin
                     y_o <= pass;
                  end
                  else begin
                     y_o <= 4;
                  end
               end

               if (r3 == `BGE3) begin
                  if (a >= b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BLTU3) begin
                  if (a < b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end

               if (r3 == `BGEU3) begin
                  if (a > b) begin
                     y_o <= pass;
                  end
                  else
                     y_o <= 4;
               end
            end
            else if (itype_i == `UTYPE) begin
               y_o <= a;
            end
            else if (itype_i == `LTYPE) begin
               y_o <= a + b;
            end
            else if (itype_i == `JRTYPE) begin
               y_o <= a;
            end
         end
      end
   end

   initial begin
      a = 0;
      b = 0;
      pass = 0;
      y_o = 0;
      pass_o = 0;
   end
endmodule