data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:62: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:77: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:80: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:83: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:92: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:95: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:98: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:101: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/452016975/src/MiniMIPS_testbench.v:6: Cannot find file containing module: \'MiniMIPS\'\nMiniMIPS obj(clk,pc);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452016975/src,data/full_repos/permissive/452016975/MiniMIPS\n             data/full_repos/permissive/452016975/src,data/full_repos/permissive/452016975/MiniMIPS.v\n             data/full_repos/permissive/452016975/src,data/full_repos/permissive/452016975/MiniMIPS.sv\n             MiniMIPS\n             MiniMIPS.v\n             MiniMIPS.sv\n             obj_dir/MiniMIPS\n             obj_dir/MiniMIPS.v\n             obj_dir/MiniMIPS.sv\n%Error: Exiting due to 1 error(s), 30 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MiniMIPS_testbench();
 `define DELAY 20
reg clk;
reg [31:0]pc;

MiniMIPS obj(clk,pc);

initial clk = 0;
initial pc = 0;

initial begin 
	 clk = ~clk;
	 pc=32'd0;
#`DELAY;
	 clk = ~clk;
	 pc=32'd1;
#`DELAY;
	 clk = ~clk;
	 pc=32'd2;
#`DELAY;
	 clk = ~clk;
	 pc=32'd3;
#`DELAY;
	 clk = ~clk;
	 pc=32'd4;
#`DELAY;
	clk = ~clk;
	 pc=32'd5;
#`DELAY;
	 clk = ~clk;
	 pc=32'd6;
#`DELAY;
	 clk = ~clk;
	 pc=32'd7;
#`DELAY;
	 clk = ~clk;
	 pc=32'd8;
#`DELAY;
	 clk = ~clk;
	 pc=32'd9;
#`DELAY;
	clk = ~clk;
	 pc=32'd10;
#`DELAY;
	 clk = ~clk;
	 pc=32'd11;
#`DELAY;
	 clk = ~clk;
	 pc=32'd12;
#`DELAY;
	 clk = ~clk;
	 pc=32'd13;
#`DELAY;
	 clk = ~clk;
	 pc=32'd14;
#`DELAY;
	clk = ~clk;
	 pc=32'd15;
#`DELAY;
	 clk = ~clk;
	 pc=32'd16;
#`DELAY;
	 clk = ~clk;
	 pc=32'd17;
#`DELAY;
	 clk = ~clk;
	 pc=32'd18;
#`DELAY;
	 clk = ~clk;
	 pc=32'd19;
#`DELAY;
	clk = ~clk;
	 pc=32'd19;
#`DELAY;
	 clk = ~clk;
	 pc=32'd20;
#`DELAY;
	 clk = ~clk;
	 pc=32'd21;
#`DELAY;
	 clk = ~clk;
	 pc=32'd22;
#`DELAY;
	 clk = ~clk;
	 pc=32'd23;
#`DELAY;
	clk = ~clk;
	 pc=32'd24;
#`DELAY;
	 clk = ~clk;
	 pc=32'd25;
#`DELAY;
	 clk = ~clk;
	 pc=32'd26;
#`DELAY;
	 clk = ~clk;
	 pc=32'd27;
#`DELAY;
	 clk = ~clk;
	 pc=32'd28;
#`DELAY;
	clk = ~clk;
	 pc=32'd29;
end


endmodule
module MiniMIPS_testbench();

 `define DELAY 20
reg clk;
reg [31:0]pc;

MiniMIPS obj(clk,pc);

initial clk = 0;
initial pc = 0;

initial begin 
	 clk = ~clk;
	 pc=32'd0;
#`DELAY;
	 clk = ~clk;
	 pc=32'd1;
#`DELAY;
	 clk = ~clk;
	 pc=32'd2;
#`DELAY;
	 clk = ~clk;
	 pc=32'd3;
#`DELAY;
	 clk = ~clk;
	 pc=32'd4;
#`DELAY;
	clk = ~clk;
	 pc=32'd5;
#`DELAY;
	 clk = ~clk;
	 pc=32'd6;
#`DELAY;
	 clk = ~clk;
	 pc=32'd7;
#`DELAY;
	 clk = ~clk;
	 pc=32'd8;
#`DELAY;
	 clk = ~clk;
	 pc=32'd9;
#`DELAY;
	clk = ~clk;
	 pc=32'd10;
#`DELAY;
	 clk = ~clk;
	 pc=32'd11;
#`DELAY;
	 clk = ~clk;
	 pc=32'd12;
#`DELAY;
	 clk = ~clk;
	 pc=32'd13;
#`DELAY;
	 clk = ~clk;
	 pc=32'd14;
#`DELAY;
	clk = ~clk;
	 pc=32'd15;
#`DELAY;
	 clk = ~clk;
	 pc=32'd16;
#`DELAY;
	 clk = ~clk;
	 pc=32'd17;
#`DELAY;
	 clk = ~clk;
	 pc=32'd18;
#`DELAY;
	 clk = ~clk;
	 pc=32'd19;
#`DELAY;
	clk = ~clk;
	 pc=32'd19;
#`DELAY;
	 clk = ~clk;
	 pc=32'd20;
#`DELAY;
	 clk = ~clk;
	 pc=32'd21;
#`DELAY;
	 clk = ~clk;
	 pc=32'd22;
#`DELAY;
	 clk = ~clk;
	 pc=32'd23;
#`DELAY;
	clk = ~clk;
	 pc=32'd24;
#`DELAY;
	 clk = ~clk;
	 pc=32'd25;
#`DELAY;
	 clk = ~clk;
	 pc=32'd26;
#`DELAY;
	 clk = ~clk;
	 pc=32'd27;
#`DELAY;
	 clk = ~clk;
	 pc=32'd28;
#`DELAY;
	clk = ~clk;
	 pc=32'd29;
end


endmodule