data/full_repos/permissive/497337299/basics/tb/tb_reg8.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:15: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk; \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #30 en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = $random; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = $random; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #30 en = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = $random; \n        ^\n%Error: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:9: Cannot find file containing module: \'reg8\'\n    reg8 dut (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/reg8\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/reg8.v\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/reg8.sv\n             reg8\n             reg8.v\n             reg8.sv\n             obj_dir/reg8\n             obj_dir/reg8.v\n             obj_dir/reg8.sv\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:23: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance tb_reg8\n        d = $random; \n          ^\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:25: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance tb_reg8\n        #10 d = $random; \n              ^\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance tb_reg8\n        #10 d = $random; \n              ^\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/tb/tb_reg8.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance tb_reg8\n        #10 d = $random; \n              ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_reg8 ();
    parameter n = 8;
    reg rst, clk, en;
    reg [n-1: 0] d;
    wire [n-1: 0] q;


    reg8 dut (
        .clk(clk), .rst(rst), .en(en), 
        .d(d), .q(q)
    ); 


    always #5 clk = ~clk; 


    initial begin 
        clk = 0; 
        en = 0; 
        rst = 1; 
        #10 rst = 0; 
        d = $random; 
        #30 en = 1;
        #10 d = $random; 
        #10 d = $random; 
        #30 en = 0; 
        #10 d = $random; 

    end
endmodule
module tb_reg8 ();

    parameter n = 8;
    reg rst, clk, en;
    reg [n-1: 0] d;
    wire [n-1: 0] q;


    reg8 dut (
        .clk(clk), .rst(rst), .en(en), 
        .d(d), .q(q)
    ); 


    always #5 clk = ~clk; 


    initial begin 
        clk = 0; 
        en = 0; 
        rst = 1; 
        #10 rst = 0; 
        d = $random; 
        #30 en = 1;
        #10 d = $random; 
        #10 d = $random; 
        #30 en = 0; 
        #10 d = $random; 

    end
endmodule