data/full_repos/permissive/468929885/verilog/rtl/c_elem.v
data/verilator_xmls/2d299db5-e6e0-4415-92f3-a52c0465bcc4.xml
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]					in,

	output							out

);


(* keep = "true" *) reg out_r = 0;

assign out = out_r;

always@(*)
begin
	if(rst)
	begin
		out_r = 0;
	end
	else
	begin
		if(!(|in))
		begin
			out_r = 0;
		end
		if(&in)
		begin
			out_r = 1;
		end
	end
end



endmodule
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]					in,

	output							out

);



(* keep = "true" *) reg out_r = 0;

assign out = out_r;

always@(*)
begin
	if(rst)
	begin
		out_r = 0;
	end
	else
	begin
		if(!(|in))
		begin
			out_r = 0;
		end
		if(&in)
		begin
			out_r = 1;
		end
	end
end



endmodule