data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv
1: b'%Warning-IMPLICIT: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:390: Signal definition not found, creating implicitly: \'sw_wr_en_4\'\n                                                                                              : ... Suggested alternative: \'sw_wr_en_0\'\nassign  sw_wr_en_4 = sw_wr_en && (sw_addr==4);\n        ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:391: Signal definition not found, creating implicitly: \'sw_wr_en_5\'\n                                                                                              : ... Suggested alternative: \'sw_wr_en_0\'\nassign  sw_wr_en_5 = sw_wr_en && (sw_addr==5);\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:223: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_clkbuf_pll     (.A (pll_clk_out[0]), . X(int_pll_clock));\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/rtl/wb_host/src,data/full_repos/permissive/504248338/ctech_clk_buf\n             data/full_repos/permissive/504248338/verilog/rtl/wb_host/src,data/full_repos/permissive/504248338/ctech_clk_buf.v\n             data/full_repos/permissive/504248338/verilog/rtl/wb_host/src,data/full_repos/permissive/504248338/ctech_clk_buf.sv\n             ctech_clk_buf\n             ctech_clk_buf.v\n             ctech_clk_buf.sv\n             obj_dir/ctech_clk_buf\n             obj_dir/ctech_clk_buf.v\n             obj_dir/ctech_clk_buf.sv\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:224: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:238: Cannot find file containing module: \'ctech_buf\'\nctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));\n^~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:239: Cannot find file containing module: \'ctech_buf\'\nctech_buf u_buf_pll_rst       (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n));\n^~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:246: Cannot find file containing module: \'reset_sync\'\nreset_sync  u_wbm_rst (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:253: Cannot find file containing module: \'reset_sync\'\nreset_sync  u_wbs_rst (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:261: Cannot find file containing module: \'uart2wb\'\nuart2wb u_uart2wb (  \n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:298: Cannot find file containing module: \'wb_arb\'\nwb_arb u_arb(\n^~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:327: Cannot find file containing module: \'clk_skew_adjust\'\nclk_skew_adjust u_skew_wh\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:348: Cannot find file containing module: \'ctech_delay_buf\'\nctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i));\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:349: Cannot find file containing module: \'ctech_delay_buf\'\nctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1));\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:350: Cannot find file containing module: \'ctech_delay_buf\'\nctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));\n^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:426: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                           : ... In instance wb_host\n  reg_out [31:0] = 8\'d0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:428: Operator CASE expects 3 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n                                                                                           : ... In instance wb_host\n  case (sw_addr [1:0])\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:440: Cannot find file containing module: \'generic_register\'\ngeneric_register #(32,0  ) u_glb_ctrl (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:450: Cannot find file containing module: \'generic_register\'\ngeneric_register #(16,16\'h1000 ) u_bank_sel (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:461: Cannot find file containing module: \'generic_register\'\ngeneric_register #(32,0  ) u_clk_ctrl1 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:471: Cannot find file containing module: \'generic_register\'\ngeneric_register #(32,0  ) u_clk_ctrl2 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:480: Cannot find file containing module: \'generic_register\'\ngeneric_register #(32,0  ) u_pll_ctrl (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:497: Cannot find file containing module: \'async_wb\'\nasync_wb u_async_wb(\n^~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:528: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(2) u_pll_ref_clk (\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:539: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(3) u_pllclk (\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:564: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:567: Cannot find file containing module: \'ctech_mux2x1\'\nctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S  (cfg_wb_clk_div), .X  (wbs_clk_out));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:570: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(4) u_wbclk (\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:596: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:599: Cannot find file containing module: \'ctech_mux2x1\'\nctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S  (cfg_cpu_clk_div),     .X  (cpu_clk_int));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:601: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:603: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(4) u_cpuclk (\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:619: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:621: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(7) u_rtcclk (\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:646: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:648: Cannot find file containing module: \'ctech_mux2x1\'\nctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S  (cfg_usb_clk_div), .X  (usb_clk_int));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:651: Cannot find file containing module: \'ctech_clk_buf\'\nctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/wb_host/src/wb_host.sv:653: Cannot find file containing module: \'clk_ctl\'\nclk_ctl #(4) u_usbclk (\n^~~~~~~\n%Error: Exiting due to 33 error(s), 4 warning(s)\n'
module wb_host (

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
       input logic                 user_clock1      ,
       input logic                 user_clock2      ,

       output logic                cpu_clk          ,
       output logic                rtc_clk          ,
       output logic                usb_clk          ,

       output logic                wbd_int_rst_n    ,
       output logic                wbd_pll_rst_n    ,


       input   logic               wbm_rst_i        ,
       input   logic               wbm_clk_i        ,
       input   logic               wbm_cyc_i        ,
       input   logic               wbm_stb_i        ,
       input   logic [31:0]        wbm_adr_i        ,
       input   logic               wbm_we_i         ,
       input   logic [31:0]        wbm_dat_i        ,
       input   logic [3:0]         wbm_sel_i        ,
       output  logic [31:0]        wbm_dat_o        ,
       output  logic               wbm_ack_o        ,
       output  logic               wbm_err_o        ,


       input   logic               wbd_clk_int      , 
       output  logic               wbd_clk_wh       ,
       input   logic [3:0]         cfg_cska_wh      ,


       output  logic               wbs_clk_out      ,
       input   logic               wbs_clk_i        ,
       output  logic               wbs_cyc_o        ,
       output  logic               wbs_stb_o        ,
       output  logic [31:0]        wbs_adr_o        ,
       output  logic               wbs_we_o         ,
       output  logic [31:0]        wbs_dat_o        ,
       output  logic [3:0]         wbs_sel_o        ,
       input   logic [31:0]        wbs_dat_i        ,
       input   logic               wbs_ack_i        ,
       input   logic               wbs_err_i        ,

       output logic [31:0]         cfg_clk_ctrl1    ,

       output logic                cfg_pll_enb      ,
       output logic[4:0]           cfg_pll_fed_div  ,
       output logic                cfg_dco_mode     ,
       output logic[25:0]          cfg_dc_trim      ,
       output logic                pll_ref_clk      ,
       input  logic [1:0]          pll_clk_out      ,

       input  logic [17:0]         la_data_in       ,

       input  logic                uartm_rxd        ,
       output logic                uartm_txd        ,

       output logic                dbg_clk_mon

    );






logic               wbm_rst_n;
logic               wbs_rst_n;

logic               reg_sel    ;
logic [2:0]         sw_addr    ;
logic               sw_rd_en   ;
logic               sw_wr_en   ;
logic [31:0]        reg_rdata  ;
logic [31:0]        reg_out    ;
logic               reg_ack    ;
logic [7:0]         config_reg ;    
logic [31:0]        clk_ctrl1 ;    
logic [31:0]        clk_ctrl2 ;    
logic               sw_wr_en_0;
logic               sw_wr_en_1;
logic               sw_wr_en_2;
logic               sw_wr_en_3;
logic [15:0]        cfg_bank_sel;
logic [31:0]        reg_0;
logic [31:0]        cfg_clk_ctrl2;

logic  [31:0]       cfg_pll_ctrl; 
logic  [7:0]        cfg_wb_clk_ctrl;
logic  [7:0]        cfg_cpu_clk_ctrl;
logic  [7:0]        cfg_rtc_clk_ctrl;
logic  [7:0]        cfg_usb_clk_ctrl;
logic  [31:0]       cfg_glb_ctrl;



logic               wbm_uart_cyc_i        ;
logic               wbm_uart_stb_i        ;
logic [31:0]        wbm_uart_adr_i        ;
logic               wbm_uart_we_i         ;
logic [31:0]        wbm_uart_dat_i        ;
logic [3:0]         wbm_uart_sel_i        ;
logic [31:0]        wbm_uart_dat_o        ;
logic               wbm_uart_ack_o        ;
logic               wbm_uart_err_o        ;


logic               wb_cyc_i              ;
logic               wb_stb_i              ;
logic [31:0]        wb_adr_i              ;
logic               wb_we_i               ;
logic [31:0]        wb_dat_i              ;
logic [3:0]         wb_sel_i              ;
logic [31:0]        wb_dat_o              ;
logic               wb_ack_o              ;
logic               wb_err_o              ;
logic [31:0]        wb_adr_int            ;
logic               wb_stb_int            ;
logic [31:0]        wb_dat_int            ;
logic               wb_ack_int            ;
logic               wb_err_int            ;

logic [3:0]         cfg_mon_sel           ;
logic               int_pll_clock         ;
logic               pll_clk_div16         ;
logic               pll_clk_div16_buf     ;
logic [2:0]         cfg_ref_pll_div       ;


assign cfg_pll_enb      = cfg_glb_ctrl[15];
assign cfg_ref_pll_div  = cfg_glb_ctrl[14:12];
assign cfg_mon_sel      = cfg_glb_ctrl[11:8];

assign cfg_dco_mode     = cfg_pll_ctrl[31];
assign cfg_pll_fed_div  = cfg_pll_ctrl[30:26];
assign cfg_dc_trim      = cfg_pll_ctrl[25:0];


ctech_clk_buf u_clkbuf_pll     (.A (pll_clk_out[0]), . X(int_pll_clock));
ctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf));



assign dbg_clk_mon  = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf:
	              (cfg_mon_sel == 4'b001) ? pll_ref_clk  :
	              (cfg_mon_sel == 4'b010) ? wbs_clk_out  :
	              (cfg_mon_sel == 4'b011) ? cpu_clk_int  :
	              (cfg_mon_sel == 4'b100) ? rtc_clk_div  :
	              (cfg_mon_sel == 4'b101) ? usb_clk_int  : 1'b0;




ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
ctech_buf u_buf_pll_rst       (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n));





wire    arst_n = !wbm_rst_i & la_data_in[0];
reset_sync  u_wbm_rst (
	      .scan_mode  (1'b0           ),
              .dclk       (wbm_clk_i      ),
	      .arst_n     (arst_n         ),
              .srst_n     (wbm_rst_n      )
          );

reset_sync  u_wbs_rst (
	      .scan_mode  (1'b0           ),
              .dclk       (wbs_clk_i      ),
	      .arst_n     (arst_n         ),
              .srst_n     (wbs_rst_n      )
          );


uart2wb u_uart2wb (  
        .arst_n          (wbm_rst_n         ),
        .app_clk         (wbm_clk_i         ),


       .cfg_tx_enable    (la_data_in[1]     ),
       .cfg_rx_enable    (la_data_in[2]     ),
       .cfg_stop_bit     (la_data_in[3]     ),
       .cfg_baud_16x     (la_data_in[15:4]  ),
       .cfg_pri_mod      (la_data_in[17:16] ),


       .wbm_cyc_o        (wbm_uart_cyc_i ),
       .wbm_stb_o        (wbm_uart_stb_i ),
       .wbm_adr_o        (wbm_uart_adr_i ),
       .wbm_we_o         (wbm_uart_we_i  ),
       .wbm_dat_o        (wbm_uart_dat_i ),
       .wbm_sel_o        (wbm_uart_sel_i ),
       .wbm_dat_i        (wbm_uart_dat_o ),
       .wbm_ack_i        (wbm_uart_ack_o ),
       .wbm_err_i        (wbm_uart_err_o ),


       .frm_error        (),
       .par_error        (),

       .baud_clk_16x     (),


       .rxd              (uartm_rxd) ,
       .txd              (uartm_txd)

     );



wire [1:0] grnt;
wb_arb u_arb(
	.clk      (wbm_clk_i), 
	.rstn     (wbm_rst_n), 
	.req      ({2'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), 
	.gnt      (grnt)
        );


assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i               : wbm_uart_cyc_i; 
assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i; 
assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i; 
assign wb_we_i  = (grnt == 2'b00) ? wbm_we_i  : wbm_uart_we_i; 
assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i; 
assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i : wbm_uart_sel_i; 

assign wbm_dat_o = (grnt == 2'b00) ? wb_dat_o : 'h0;
assign wbm_ack_o = (grnt == 2'b00) ? wb_ack_o : 'h0;
assign wbm_err_o = (grnt == 2'b00) ? wb_err_o : 'h0;


assign wbm_uart_dat_o = (grnt == 2'b01) ? wb_dat_o : 'h0;
assign wbm_uart_ack_o = (grnt == 2'b01) ? wb_ack_o : 'h0;
assign wbm_uart_err_o = (grnt == 2'b01) ? wb_err_o : 'h0;






clk_skew_adjust u_skew_wh
       (
`ifdef USE_POWER_PINS
               .vccd1      (vccd1                      ),
               .vssd1      (vssd1                      ),
`endif
	       .clk_in     (wbd_clk_int               ), 
	       .sel        (cfg_cska_wh               ), 
	       .clk_out    (wbd_clk_wh                ) 
       );




wire [31:0]  wb_dat_o1   = (reg_sel) ? reg_rdata : wb_dat_int;
wire         wb_ack_o1   = (reg_sel) ? reg_ack   : wb_ack_int;
wire         wb_err_o1   = (reg_sel) ? 1'b0      : wb_err_int;

logic wb_req;

wire  wb_stb_d1,wb_stb_d2,wb_stb_d3;
ctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i));
ctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1));
ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));
always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
    if ( wbm_rst_n == 1'b0 ) begin
        wb_req    <= '0;
	wb_dat_o <= '0;
	wb_ack_o <= '0;
	wb_err_o <= '0;
   end else begin
       wb_req   <= wb_stb_d3 && ((wb_ack_o == 0) && (wb_ack_o1 == 0)) ;
       wb_ack_o <= wb_ack_o1;
       wb_err_o <= wb_err_o1;
       if(wb_ack_o1)
          wb_dat_o <= wb_dat_o1;
   end
end















assign reg_sel       = wb_req & (wb_adr_i[19] == 1'b1);

assign sw_addr       = wb_adr_i [4:2];
assign sw_rd_en      = reg_sel & !wb_we_i;
assign sw_wr_en      = reg_sel & wb_we_i;

assign  sw_wr_en_0 = sw_wr_en && (sw_addr==0);
assign  sw_wr_en_1 = sw_wr_en && (sw_addr==1);
assign  sw_wr_en_2 = sw_wr_en && (sw_addr==2);
assign  sw_wr_en_3 = sw_wr_en && (sw_addr==3);
assign  sw_wr_en_4 = sw_wr_en && (sw_addr==4);
assign  sw_wr_en_5 = sw_wr_en && (sw_addr==5);

always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin : preg_out_Seq
   if (wbm_rst_n == 1'b0)
   begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end
   else if (sw_rd_en && !reg_ack) 
   begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end
   else if (sw_wr_en && !reg_ack) 
      reg_ack          <= 1'b1;
   else
   begin
      reg_ack        <= 1'b0;
   end
end





assign cfg_glb_ctrl         = reg_0[31:0];
assign cfg_wb_clk_ctrl      = cfg_clk_ctrl2[7:0];
assign cfg_rtc_clk_ctrl     = cfg_clk_ctrl2[15:8];
assign cfg_usb_clk_ctrl     = cfg_clk_ctrl2[23:16];
assign cfg_cpu_clk_ctrl     = cfg_clk_ctrl2[31:24];


always @( *)
begin 
  reg_out [31:0] = 8'd0;

  case (sw_addr [1:0])
    3'b000 :   reg_out [31:0] = reg_0;
    3'b001 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
    3'b010 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
    3'b011 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];    
    3'b100 :   reg_out [31:0] = cfg_pll_ctrl [31:0];     
    default : reg_out [31:0] = 'h0;
  endcase
end



generic_register #(32,0  ) u_glb_ctrl (
	      .we            ({32{sw_wr_en_0}}   ),		 
	      .data_in       (wb_dat_i[31:0]    ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (reg_0[31:0])
          );

generic_register #(16,16'h1000 ) u_bank_sel (
	      .we            ({16{sw_wr_en_1}}   ),		 
	      .data_in       (wb_dat_i[15:0]    ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_bank_sel[15:0] )
          );


generic_register #(32,0  ) u_clk_ctrl1 (
	      .we            ({32{sw_wr_en_2}}   ),		 
	      .data_in       (wb_dat_i[31:0]    ),
	      .reset_n       (wbm_rst_n          ),
	      .clk           (wbm_clk_i          ),
	      

	      .data_out      (cfg_clk_ctrl1[31:0])
          );

generic_register #(32,0  ) u_clk_ctrl2 (
	      .we            ({32{sw_wr_en_3}}  ),		 
	      .data_in       (wb_dat_i[31:0]   ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_clk_ctrl2[31:0])
          );
generic_register #(32,0  ) u_pll_ctrl (
	      .we            ({32{sw_wr_en_4}}  ),		 
	      .data_in       (wb_dat_i[31:0]   ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_pll_ctrl[31:0])
          );


assign wb_stb_int = wb_req & !reg_sel;



assign wb_adr_int = {cfg_bank_sel[15:3],wb_adr_i[18:0]};  

async_wb u_async_wb(

       .wbm_rst_n   (wbm_rst_n     ),  
       .wbm_clk_i   (wbm_clk_i     ),  
       .wbm_cyc_i   (wb_cyc_i      ),  
       .wbm_stb_i   (wb_stb_int    ),  
       .wbm_adr_i   (wb_adr_int    ),  
       .wbm_we_i    (wb_we_i       ),  
       .wbm_dat_i   (wb_dat_i      ),  
       .wbm_sel_i   (wb_sel_i      ),  
       .wbm_dat_o   (wb_dat_int    ),  
       .wbm_ack_o   (wb_ack_int    ),  
       .wbm_err_o   (wb_err_int    ),  


       .wbs_rst_n   (wbs_rst_n     ),  
       .wbs_clk_i   (wbs_clk_i     ),  
       .wbs_cyc_o   (wbs_cyc_o     ),  
       .wbs_stb_o   (wbs_stb_o     ),  
       .wbs_adr_o   (wbs_adr_o     ),  
       .wbs_we_o    (wbs_we_o      ),  
       .wbs_dat_o   (wbs_dat_o     ),  
       .wbs_sel_o   (wbs_sel_o     ),  
       .wbs_dat_i   (wbs_dat_i     ),  
       .wbs_ack_i   (wbs_ack_i     ),  
       .wbs_err_i   (wbs_err_i     )

    );



clk_ctl #(2) u_pll_ref_clk (

       .clk_o         (pll_ref_clk      ),

       .mclk          (user_clock1      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_ref_pll_div  )
   );



clk_ctl #(3) u_pllclk (

       .clk_o         (pll_clk_div16    ),

       .mclk          (int_pll_clock    ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (4'hF )
   );




logic       wb_clk_div;
logic       wbs_ref_clk_int;
logic       wbs_ref_clk;

wire  [1:0]   cfg_wb_clk_src_sel   =  cfg_wb_clk_ctrl[7:6];
wire          cfg_wb_clk_div       =  cfg_wb_clk_ctrl[5];
wire  [4:0]   cfg_wb_clk_ratio     =  cfg_wb_clk_ctrl[4:0];


assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
                         (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;

ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));


ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S  (cfg_wb_clk_div), .X  (wbs_clk_out));


clk_ctl #(4) u_wbclk (

       .clk_o         (wb_clk_div      ),

       .mclk          (wbs_ref_clk       ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_wb_clk_ratio )
   );





wire   cpu_clk_div;
wire   cpu_ref_clk_int;
wire   cpu_ref_clk;
wire   cpu_clk_int;

wire [1:0] cfg_cpu_clk_src_sel   = cfg_cpu_clk_ctrl[7:6];
wire       cfg_cpu_clk_div       = cfg_cpu_clk_ctrl[5];
wire [4:0] cfg_cpu_clk_ratio     = cfg_cpu_clk_ctrl[4:0];

assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
                         (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;

ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));


ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S  (cfg_cpu_clk_div),     .X  (cpu_clk_int));

ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));

clk_ctl #(4) u_cpuclk (

       .clk_o         (cpu_clk_div      ),

       .mclk          (cpu_ref_clk      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_cpu_clk_ratio)
   );




wire   rtc_clk_div;
wire [7:0] cfg_rtc_clk_ratio     = cfg_rtc_clk_ctrl[7:0];


ctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk));

clk_ctl #(7) u_rtcclk (

       .clk_o         (rtc_clk_div      ),

       .mclk          (user_clock2      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_rtc_clk_ratio)
   );





wire   usb_clk_div;
wire   usb_ref_clk_int;
wire   usb_ref_clk;
wire   usb_clk_int;

wire [1:0] cfg_usb_clk_sel_sel   = cfg_usb_clk_ctrl[7:6];
wire       cfg_usb_clk_div       = cfg_usb_clk_ctrl[5];
wire [4:0] cfg_usb_clk_ratio     = cfg_usb_clk_ctrl[4:0];

assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 :
                         (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;
ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk));

ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S  (cfg_usb_clk_div), .X  (usb_clk_int));


ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));

clk_ctl #(4) u_usbclk (

       .clk_o         (usb_clk_div      ),

       .mclk          (usb_ref_clk      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_usb_clk_ratio)
   );

endmodule
module wb_host (

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
       input logic                 user_clock1      ,
       input logic                 user_clock2      ,

       output logic                cpu_clk          ,
       output logic                rtc_clk          ,
       output logic                usb_clk          ,

       output logic                wbd_int_rst_n    ,
       output logic                wbd_pll_rst_n    ,


       input   logic               wbm_rst_i        ,
       input   logic               wbm_clk_i        ,
       input   logic               wbm_cyc_i        ,
       input   logic               wbm_stb_i        ,
       input   logic [31:0]        wbm_adr_i        ,
       input   logic               wbm_we_i         ,
       input   logic [31:0]        wbm_dat_i        ,
       input   logic [3:0]         wbm_sel_i        ,
       output  logic [31:0]        wbm_dat_o        ,
       output  logic               wbm_ack_o        ,
       output  logic               wbm_err_o        ,


       input   logic               wbd_clk_int      , 
       output  logic               wbd_clk_wh       ,
       input   logic [3:0]         cfg_cska_wh      ,


       output  logic               wbs_clk_out      ,
       input   logic               wbs_clk_i        ,
       output  logic               wbs_cyc_o        ,
       output  logic               wbs_stb_o        ,
       output  logic [31:0]        wbs_adr_o        ,
       output  logic               wbs_we_o         ,
       output  logic [31:0]        wbs_dat_o        ,
       output  logic [3:0]         wbs_sel_o        ,
       input   logic [31:0]        wbs_dat_i        ,
       input   logic               wbs_ack_i        ,
       input   logic               wbs_err_i        ,

       output logic [31:0]         cfg_clk_ctrl1    ,

       output logic                cfg_pll_enb      ,
       output logic[4:0]           cfg_pll_fed_div  ,
       output logic                cfg_dco_mode     ,
       output logic[25:0]          cfg_dc_trim      ,
       output logic                pll_ref_clk      ,
       input  logic [1:0]          pll_clk_out      ,

       input  logic [17:0]         la_data_in       ,

       input  logic                uartm_rxd        ,
       output logic                uartm_txd        ,

       output logic                dbg_clk_mon

    );







logic               wbm_rst_n;
logic               wbs_rst_n;

logic               reg_sel    ;
logic [2:0]         sw_addr    ;
logic               sw_rd_en   ;
logic               sw_wr_en   ;
logic [31:0]        reg_rdata  ;
logic [31:0]        reg_out    ;
logic               reg_ack    ;
logic [7:0]         config_reg ;    
logic [31:0]        clk_ctrl1 ;    
logic [31:0]        clk_ctrl2 ;    
logic               sw_wr_en_0;
logic               sw_wr_en_1;
logic               sw_wr_en_2;
logic               sw_wr_en_3;
logic [15:0]        cfg_bank_sel;
logic [31:0]        reg_0;
logic [31:0]        cfg_clk_ctrl2;

logic  [31:0]       cfg_pll_ctrl; 
logic  [7:0]        cfg_wb_clk_ctrl;
logic  [7:0]        cfg_cpu_clk_ctrl;
logic  [7:0]        cfg_rtc_clk_ctrl;
logic  [7:0]        cfg_usb_clk_ctrl;
logic  [31:0]       cfg_glb_ctrl;



logic               wbm_uart_cyc_i        ;
logic               wbm_uart_stb_i        ;
logic [31:0]        wbm_uart_adr_i        ;
logic               wbm_uart_we_i         ;
logic [31:0]        wbm_uart_dat_i        ;
logic [3:0]         wbm_uart_sel_i        ;
logic [31:0]        wbm_uart_dat_o        ;
logic               wbm_uart_ack_o        ;
logic               wbm_uart_err_o        ;


logic               wb_cyc_i              ;
logic               wb_stb_i              ;
logic [31:0]        wb_adr_i              ;
logic               wb_we_i               ;
logic [31:0]        wb_dat_i              ;
logic [3:0]         wb_sel_i              ;
logic [31:0]        wb_dat_o              ;
logic               wb_ack_o              ;
logic               wb_err_o              ;
logic [31:0]        wb_adr_int            ;
logic               wb_stb_int            ;
logic [31:0]        wb_dat_int            ;
logic               wb_ack_int            ;
logic               wb_err_int            ;

logic [3:0]         cfg_mon_sel           ;
logic               int_pll_clock         ;
logic               pll_clk_div16         ;
logic               pll_clk_div16_buf     ;
logic [2:0]         cfg_ref_pll_div       ;


assign cfg_pll_enb      = cfg_glb_ctrl[15];
assign cfg_ref_pll_div  = cfg_glb_ctrl[14:12];
assign cfg_mon_sel      = cfg_glb_ctrl[11:8];

assign cfg_dco_mode     = cfg_pll_ctrl[31];
assign cfg_pll_fed_div  = cfg_pll_ctrl[30:26];
assign cfg_dc_trim      = cfg_pll_ctrl[25:0];


ctech_clk_buf u_clkbuf_pll     (.A (pll_clk_out[0]), . X(int_pll_clock));
ctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf));



assign dbg_clk_mon  = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf:
	              (cfg_mon_sel == 4'b001) ? pll_ref_clk  :
	              (cfg_mon_sel == 4'b010) ? wbs_clk_out  :
	              (cfg_mon_sel == 4'b011) ? cpu_clk_int  :
	              (cfg_mon_sel == 4'b100) ? rtc_clk_div  :
	              (cfg_mon_sel == 4'b101) ? usb_clk_int  : 1'b0;




ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
ctech_buf u_buf_pll_rst       (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n));





wire    arst_n = !wbm_rst_i & la_data_in[0];
reset_sync  u_wbm_rst (
	      .scan_mode  (1'b0           ),
              .dclk       (wbm_clk_i      ),
	      .arst_n     (arst_n         ),
              .srst_n     (wbm_rst_n      )
          );

reset_sync  u_wbs_rst (
	      .scan_mode  (1'b0           ),
              .dclk       (wbs_clk_i      ),
	      .arst_n     (arst_n         ),
              .srst_n     (wbs_rst_n      )
          );


uart2wb u_uart2wb (  
        .arst_n          (wbm_rst_n         ),
        .app_clk         (wbm_clk_i         ),


       .cfg_tx_enable    (la_data_in[1]     ),
       .cfg_rx_enable    (la_data_in[2]     ),
       .cfg_stop_bit     (la_data_in[3]     ),
       .cfg_baud_16x     (la_data_in[15:4]  ),
       .cfg_pri_mod      (la_data_in[17:16] ),


       .wbm_cyc_o        (wbm_uart_cyc_i ),
       .wbm_stb_o        (wbm_uart_stb_i ),
       .wbm_adr_o        (wbm_uart_adr_i ),
       .wbm_we_o         (wbm_uart_we_i  ),
       .wbm_dat_o        (wbm_uart_dat_i ),
       .wbm_sel_o        (wbm_uart_sel_i ),
       .wbm_dat_i        (wbm_uart_dat_o ),
       .wbm_ack_i        (wbm_uart_ack_o ),
       .wbm_err_i        (wbm_uart_err_o ),


       .frm_error        (),
       .par_error        (),

       .baud_clk_16x     (),


       .rxd              (uartm_rxd) ,
       .txd              (uartm_txd)

     );



wire [1:0] grnt;
wb_arb u_arb(
	.clk      (wbm_clk_i), 
	.rstn     (wbm_rst_n), 
	.req      ({2'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), 
	.gnt      (grnt)
        );


assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i               : wbm_uart_cyc_i; 
assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i; 
assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i; 
assign wb_we_i  = (grnt == 2'b00) ? wbm_we_i  : wbm_uart_we_i; 
assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i; 
assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i : wbm_uart_sel_i; 

assign wbm_dat_o = (grnt == 2'b00) ? wb_dat_o : 'h0;
assign wbm_ack_o = (grnt == 2'b00) ? wb_ack_o : 'h0;
assign wbm_err_o = (grnt == 2'b00) ? wb_err_o : 'h0;


assign wbm_uart_dat_o = (grnt == 2'b01) ? wb_dat_o : 'h0;
assign wbm_uart_ack_o = (grnt == 2'b01) ? wb_ack_o : 'h0;
assign wbm_uart_err_o = (grnt == 2'b01) ? wb_err_o : 'h0;






clk_skew_adjust u_skew_wh
       (
`ifdef USE_POWER_PINS
               .vccd1      (vccd1                      ),
               .vssd1      (vssd1                      ),
`endif
	       .clk_in     (wbd_clk_int               ), 
	       .sel        (cfg_cska_wh               ), 
	       .clk_out    (wbd_clk_wh                ) 
       );




wire [31:0]  wb_dat_o1   = (reg_sel) ? reg_rdata : wb_dat_int;
wire         wb_ack_o1   = (reg_sel) ? reg_ack   : wb_ack_int;
wire         wb_err_o1   = (reg_sel) ? 1'b0      : wb_err_int;

logic wb_req;

wire  wb_stb_d1,wb_stb_d2,wb_stb_d3;
ctech_delay_buf u_delay1_stb0 (.X(wb_stb_d1),.A(wb_stb_i));
ctech_delay_buf u_delay2_stb1 (.X(wb_stb_d2),.A(wb_stb_d1));
ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));
always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
    if ( wbm_rst_n == 1'b0 ) begin
        wb_req    <= '0;
	wb_dat_o <= '0;
	wb_ack_o <= '0;
	wb_err_o <= '0;
   end else begin
       wb_req   <= wb_stb_d3 && ((wb_ack_o == 0) && (wb_ack_o1 == 0)) ;
       wb_ack_o <= wb_ack_o1;
       wb_err_o <= wb_err_o1;
       if(wb_ack_o1)
          wb_dat_o <= wb_dat_o1;
   end
end















assign reg_sel       = wb_req & (wb_adr_i[19] == 1'b1);

assign sw_addr       = wb_adr_i [4:2];
assign sw_rd_en      = reg_sel & !wb_we_i;
assign sw_wr_en      = reg_sel & wb_we_i;

assign  sw_wr_en_0 = sw_wr_en && (sw_addr==0);
assign  sw_wr_en_1 = sw_wr_en && (sw_addr==1);
assign  sw_wr_en_2 = sw_wr_en && (sw_addr==2);
assign  sw_wr_en_3 = sw_wr_en && (sw_addr==3);
assign  sw_wr_en_4 = sw_wr_en && (sw_addr==4);
assign  sw_wr_en_5 = sw_wr_en && (sw_addr==5);

always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin : preg_out_Seq
   if (wbm_rst_n == 1'b0)
   begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end
   else if (sw_rd_en && !reg_ack) 
   begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end
   else if (sw_wr_en && !reg_ack) 
      reg_ack          <= 1'b1;
   else
   begin
      reg_ack        <= 1'b0;
   end
end





assign cfg_glb_ctrl         = reg_0[31:0];
assign cfg_wb_clk_ctrl      = cfg_clk_ctrl2[7:0];
assign cfg_rtc_clk_ctrl     = cfg_clk_ctrl2[15:8];
assign cfg_usb_clk_ctrl     = cfg_clk_ctrl2[23:16];
assign cfg_cpu_clk_ctrl     = cfg_clk_ctrl2[31:24];


always @( *)
begin 
  reg_out [31:0] = 8'd0;

  case (sw_addr [1:0])
    3'b000 :   reg_out [31:0] = reg_0;
    3'b001 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
    3'b010 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
    3'b011 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];    
    3'b100 :   reg_out [31:0] = cfg_pll_ctrl [31:0];     
    default : reg_out [31:0] = 'h0;
  endcase
end



generic_register #(32,0  ) u_glb_ctrl (
	      .we            ({32{sw_wr_en_0}}   ),		 
	      .data_in       (wb_dat_i[31:0]    ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (reg_0[31:0])
          );

generic_register #(16,16'h1000 ) u_bank_sel (
	      .we            ({16{sw_wr_en_1}}   ),		 
	      .data_in       (wb_dat_i[15:0]    ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_bank_sel[15:0] )
          );


generic_register #(32,0  ) u_clk_ctrl1 (
	      .we            ({32{sw_wr_en_2}}   ),		 
	      .data_in       (wb_dat_i[31:0]    ),
	      .reset_n       (wbm_rst_n          ),
	      .clk           (wbm_clk_i          ),
	      

	      .data_out      (cfg_clk_ctrl1[31:0])
          );

generic_register #(32,0  ) u_clk_ctrl2 (
	      .we            ({32{sw_wr_en_3}}  ),		 
	      .data_in       (wb_dat_i[31:0]   ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_clk_ctrl2[31:0])
          );
generic_register #(32,0  ) u_pll_ctrl (
	      .we            ({32{sw_wr_en_4}}  ),		 
	      .data_in       (wb_dat_i[31:0]   ),
	      .reset_n       (wbm_rst_n         ),
	      .clk           (wbm_clk_i         ),
	      

	      .data_out      (cfg_pll_ctrl[31:0])
          );


assign wb_stb_int = wb_req & !reg_sel;



assign wb_adr_int = {cfg_bank_sel[15:3],wb_adr_i[18:0]};  

async_wb u_async_wb(

       .wbm_rst_n   (wbm_rst_n     ),  
       .wbm_clk_i   (wbm_clk_i     ),  
       .wbm_cyc_i   (wb_cyc_i      ),  
       .wbm_stb_i   (wb_stb_int    ),  
       .wbm_adr_i   (wb_adr_int    ),  
       .wbm_we_i    (wb_we_i       ),  
       .wbm_dat_i   (wb_dat_i      ),  
       .wbm_sel_i   (wb_sel_i      ),  
       .wbm_dat_o   (wb_dat_int    ),  
       .wbm_ack_o   (wb_ack_int    ),  
       .wbm_err_o   (wb_err_int    ),  


       .wbs_rst_n   (wbs_rst_n     ),  
       .wbs_clk_i   (wbs_clk_i     ),  
       .wbs_cyc_o   (wbs_cyc_o     ),  
       .wbs_stb_o   (wbs_stb_o     ),  
       .wbs_adr_o   (wbs_adr_o     ),  
       .wbs_we_o    (wbs_we_o      ),  
       .wbs_dat_o   (wbs_dat_o     ),  
       .wbs_sel_o   (wbs_sel_o     ),  
       .wbs_dat_i   (wbs_dat_i     ),  
       .wbs_ack_i   (wbs_ack_i     ),  
       .wbs_err_i   (wbs_err_i     )

    );



clk_ctl #(2) u_pll_ref_clk (

       .clk_o         (pll_ref_clk      ),

       .mclk          (user_clock1      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_ref_pll_div  )
   );



clk_ctl #(3) u_pllclk (

       .clk_o         (pll_clk_div16    ),

       .mclk          (int_pll_clock    ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (4'hF )
   );




logic       wb_clk_div;
logic       wbs_ref_clk_int;
logic       wbs_ref_clk;

wire  [1:0]   cfg_wb_clk_src_sel   =  cfg_wb_clk_ctrl[7:6];
wire          cfg_wb_clk_div       =  cfg_wb_clk_ctrl[5];
wire  [4:0]   cfg_wb_clk_ratio     =  cfg_wb_clk_ctrl[4:0];


assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
                         (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;

ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));


ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S  (cfg_wb_clk_div), .X  (wbs_clk_out));


clk_ctl #(4) u_wbclk (

       .clk_o         (wb_clk_div      ),

       .mclk          (wbs_ref_clk       ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_wb_clk_ratio )
   );





wire   cpu_clk_div;
wire   cpu_ref_clk_int;
wire   cpu_ref_clk;
wire   cpu_clk_int;

wire [1:0] cfg_cpu_clk_src_sel   = cfg_cpu_clk_ctrl[7:6];
wire       cfg_cpu_clk_div       = cfg_cpu_clk_ctrl[5];
wire [4:0] cfg_cpu_clk_ratio     = cfg_cpu_clk_ctrl[4:0];

assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
                         (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;

ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));


ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S  (cfg_cpu_clk_div),     .X  (cpu_clk_int));

ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));

clk_ctl #(4) u_cpuclk (

       .clk_o         (cpu_clk_div      ),

       .mclk          (cpu_ref_clk      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_cpu_clk_ratio)
   );




wire   rtc_clk_div;
wire [7:0] cfg_rtc_clk_ratio     = cfg_rtc_clk_ctrl[7:0];


ctech_clk_buf u_clkbuf_rtc (.A (rtc_clk_div), . X(rtc_clk));

clk_ctl #(7) u_rtcclk (

       .clk_o         (rtc_clk_div      ),

       .mclk          (user_clock2      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_rtc_clk_ratio)
   );





wire   usb_clk_div;
wire   usb_ref_clk_int;
wire   usb_ref_clk;
wire   usb_clk_int;

wire [1:0] cfg_usb_clk_sel_sel   = cfg_usb_clk_ctrl[7:6];
wire       cfg_usb_clk_div       = cfg_usb_clk_ctrl[5];
wire [4:0] cfg_usb_clk_ratio     = cfg_usb_clk_ctrl[4:0];

assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 :
                         (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 :	
	                 int_pll_clock;
ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk));

ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S  (cfg_usb_clk_div), .X  (usb_clk_int));


ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));

clk_ctl #(4) u_usbclk (

       .clk_o         (usb_clk_div      ),

       .mclk          (usb_ref_clk      ),
       .reset_n       (wbm_rst_n        ), 
       .clk_div_ratio (cfg_usb_clk_ratio)
   );

endmodule