data/full_repos/permissive/46989236/memory/memory_tb.v
1: b'%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:9: Cannot find include file: attributes.v\n`include "attributes.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v.v\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v.sv\n             attributes.v\n             attributes.v.v\n             attributes.v.sv\n             obj_dir/attributes.v\n             obj_dir/attributes.v.v\n             obj_dir/attributes.v.sv\n%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:3: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1:0]addr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:4: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1:0]d_in;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:5: Define or directive not defined: \'`INSTR_WIDTH\'\nwire [`INSTR_WIDTH-1:0]d_out;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:12: Unsupported or unknown PLI call: $monitor\n$monitor ("%d\\t%d\\tr!w=%b,d_out=%b,d_in=%b",$time,addr,rwbar,d_out,d_in);\n^~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("plot.vcd");\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46989236/memory/memory_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 addr = addr +1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module memory_tb;
reg rwbar;
reg [`ADDR_WIDTH-1:0]addr;
reg [`INSTR_WIDTH-1:0]d_in;
wire [`INSTR_WIDTH-1:0]d_out;

initial
begin
`include "attributes.v"
addr = 8'b00000000;
rwbar = 1'b1;
$monitor ("%d\t%d\tr!w=%b,d_out=%b,d_in=%b",$time,addr,rwbar,d_out,d_in);
$dumpfile("plot.vcd");
end

always begin
#5 addr = addr +1;
if (addr == 8'd255)
$finish;
end

memory mem(
.addr (addr),
.d_in (d_in),
.rwbar (rwbar),
.d_out (d_out)
);
endmodule
module memory_tb;

reg rwbar;
reg [`ADDR_WIDTH-1:0]addr;
reg [`INSTR_WIDTH-1:0]d_in;
wire [`INSTR_WIDTH-1:0]d_out;

initial
begin
`include "attributes.v"
addr = 8'b00000000;
rwbar = 1'b1;
$monitor ("%d\t%d\tr!w=%b,d_out=%b,d_in=%b",$time,addr,rwbar,d_out,d_in);
$dumpfile("plot.vcd");
end

always begin
#5 addr = addr +1;
if (addr == 8'd255)
$finish;
end

memory mem(
.addr (addr),
.d_in (d_in),
.rwbar (rwbar),
.d_out (d_out)
);
endmodule