data/full_repos/permissive/482719158/verilog/rtl/wrapper/RAM512.v
1: b"%Error: data/full_repos/permissive/482719158/verilog/rtl/wrapper/RAM512.v:3: syntax error, unexpected ')', expecting '['\n) (\n^\n%Error: data/full_repos/permissive/482719158/verilog/rtl/wrapper/RAM512.v:13: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input [BITS-1:0] A0\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module RAM512 #(
    parameter BITS=9,
) (
`ifdef USE_POWER_PINS
    inout VPWR,
    inout VGND,
`endif
    input CLK,
    input [7:0] WE0,
    input EN0,
    input [63:0] Di0,
    output reg [63:0] Do0,
    input [BITS-1:0] A0
);

endmodule
module RAM512 #(
    parameter BITS=9,
) (
`ifdef USE_POWER_PINS
    inout VPWR,
    inout VGND,
`endif
    input CLK,
    input [7:0] WE0,
    input EN0,
    input [63:0] Di0,
    output reg [63:0] Do0,
    input [BITS-1:0] A0
);


endmodule