data/full_repos/permissive/495276914/rv_sim_file.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/495276914/rv_sim_file.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 rsttb = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/495276914/rv_sim_file.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #40 rsttb = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/495276914/rv_sim_file.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #700 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/495276914/rv_sim_file.v:34: Unsupported: Ignoring delay on this delayed statement.\n    always #20 clktb=~clktb;\n           ^\n%Error: data/full_repos/permissive/495276914/rv_sim_file.v:35: Cannot find file containing module: \'RV32I\'\n    RV32I rv(clktb, rsttb, LEDtb); \n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/495276914,data/full_repos/permissive/495276914/RV32I\n             data/full_repos/permissive/495276914,data/full_repos/permissive/495276914/RV32I.v\n             data/full_repos/permissive/495276914,data/full_repos/permissive/495276914/RV32I.sv\n             RV32I\n             RV32I.v\n             RV32I.sv\n             obj_dir/RV32I\n             obj_dir/RV32I.v\n             obj_dir/RV32I.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rv_sim_file(
    );
    reg clktb,rsttb;
    wire [7:0] LEDtb;

    initial begin
        clktb=0;rsttb=0;
        #10 rsttb = 1;
        #40 rsttb = 0;  
        #700 $finish;
    end
    always #20 clktb=~clktb;
    RV32I rv(clktb, rsttb, LEDtb); 
    
endmodule
module rv_sim_file(
    );

    reg clktb,rsttb;
    wire [7:0] LEDtb;

    initial begin
        clktb=0;rsttb=0;
        #10 rsttb = 1;
        #40 rsttb = 0;  
        #700 $finish;
    end
    always #20 clktb=~clktb;
    RV32I rv(clktb, rsttb, LEDtb); 
    
endmodule