data/full_repos/permissive/513806017/verilog/hello_top.v
1: b"%Error: data/full_repos/permissive/513806017/verilog/hello_top.v:14: Cannot find file containing module: 'Hello'\n  Hello h(\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/513806017/verilog,data/full_repos/permissive/513806017/Hello\n             data/full_repos/permissive/513806017/verilog,data/full_repos/permissive/513806017/Hello.v\n             data/full_repos/permissive/513806017/verilog,data/full_repos/permissive/513806017/Hello.sv\n             Hello\n             Hello.v\n             Hello.sv\n             obj_dir/Hello\n             obj_dir/Hello.v\n             obj_dir/Hello.sv\n%Error: Exiting due to 1 error(s)\n"
module hello_top(input sysclk, output led1, output led2, output pio1);
  wire h_io_led1;
  wire h_io_led2;
  wire h_io_pio1;

  wire rst;

  assign led1 = h_io_led1;
  assign led2 = h_io_led2;
  assign pio1 = h_io_pio1;

  assign rst = 1'h0;

  Hello h(
       .clock(sysclk),
       .reset(rst),
       .io_led1( h_io_led1 ),
       .io_led2( h_io_led2 ),
       .io_txd( h_io_pio1 ));
endmodule
module hello_top(input sysclk, output led1, output led2, output pio1);

  wire h_io_led1;
  wire h_io_led2;
  wire h_io_pio1;

  wire rst;

  assign led1 = h_io_led1;
  assign led2 = h_io_led2;
  assign pio1 = h_io_pio1;

  assign rst = 1'h0;

  Hello h(
       .clock(sysclk),
       .reset(rst),
       .io_led1( h_io_led1 ),
       .io_led2( h_io_led2 ),
       .io_txd( h_io_pio1 ));
endmodule