data/full_repos/permissive/473778924/Basys3/DemoIO/FourSegDisplay.v
data/verilator_xmls/356eaf9a-e6e8-4768-ada8-21488615e920.xml
module FourSegDisplay (

  input        clk
, input        rst 


, input      [1:0] Address
, input      [7:0] Data_Bus_in
, output reg [7:0] Data_Bus_out
, input            Cen
, input            Rd
, input            Wr


, output wire segA
, output wire segB
, output wire segC
, output wire segD
, output wire segE
, output wire segF
, output wire segG
, output wire segDP

, output wire [3:0] segAnode
);


  wire rstb = ~rst;
  

  reg [7:0] Control; 


  reg [7:0] Divisor;


  reg [7:0] SegmentPairA;
  reg [7:0] SegmentPairB;


  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Data_Bus_out <= 8'h00;
    else if ( Rd == 1'b1 )
      case( Address )
        2'b00 : Data_Bus_out <= Control;
        2'b01 : Data_Bus_out <= Divisor; 
        2'b10 : Data_Bus_out <= SegmentPairA;
        2'b11 : Data_Bus_out <= SegmentPairB;
      endcase
    else
      Data_Bus_out <= Data_Bus_out;


  always @ (negedge clk or posedge rstb)
    if( rstb == 1'b1 ) 
      begin
        Control      = 8'h00;
        Divisor      = 8'h00;
        SegmentPairA = 8'h00;
        SegmentPairB = 8'h00;
      end
    else if (Wr == 1'b1)
      case(Address)
        2'b00   : begin
                    Control      = Data_Bus_in;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
        2'b01   : begin
                    Control      = Control;
                    Divisor      = Data_Bus_in;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
        2'b10   : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = Data_Bus_in;
                    SegmentPairB = SegmentPairB;
                  end
        2'b11   : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = Data_Bus_in;
                  end
        default : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
      endcase
    else
      begin
        Control      = Control;
        Divisor      = Divisor;
        SegmentPairA = SegmentPairA;
        SegmentPairB = SegmentPairB;
      end


  reg  [5:0] Bit;
  wire [3:0] BitA = SegmentPairA[7:4]; 
  wire [3:0] BitB = SegmentPairA[3:0]; 
  wire [3:0] BitC = SegmentPairB[7:4]; 
  wire [3:0] BitD = SegmentPairB[3:0]; 
  wire [6:0] Segments;
  wire       SegmentsDp;


  assign segDP = SegmentsDp;
  assign segA  = Segments[6];
  assign segB  = Segments[5];
  assign segC  = Segments[4];
  assign segD  = Segments[3];
  assign segE  = Segments[2];
  assign segF  = Segments[1];
  assign segG  = Segments[0];
  

  always @*
    case(segAnode)
      4'b0111 : Bit <= {Control[7:6], BitA};
      4'b1011 : Bit <= {Control[5:4], BitB};
      4'b1101 : Bit <= {Control[3:2], BitC};
      4'b1110 : Bit <= {Control[1:0], BitD};
      default : Bit <= 6'b000000;
    endcase
  
  reg  [23:0] Counter  = 0;
  wire [23:0] Divider  = {Divisor, 16'h0000};
  wire        advAnode = (Divider == Counter);
  
  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Counter <= 0;
    else if( advAnode == 1'b1 )
      Counter <= 0;
    else
      Counter <= Counter + 1;
  
  SegmentDecoder segmentDec   (clk, rst, advAnode, Bit[5], Bit[4], Bit[3:0], segAnode, Segments, SegmentsDp);

endmodule
module FourSegDisplay (

  input        clk
, input        rst 


, input      [1:0] Address
, input      [7:0] Data_Bus_in
, output reg [7:0] Data_Bus_out
, input            Cen
, input            Rd
, input            Wr


, output wire segA
, output wire segB
, output wire segC
, output wire segD
, output wire segE
, output wire segF
, output wire segG
, output wire segDP

, output wire [3:0] segAnode
);



  wire rstb = ~rst;
  

  reg [7:0] Control; 


  reg [7:0] Divisor;


  reg [7:0] SegmentPairA;
  reg [7:0] SegmentPairB;


  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Data_Bus_out <= 8'h00;
    else if ( Rd == 1'b1 )
      case( Address )
        2'b00 : Data_Bus_out <= Control;
        2'b01 : Data_Bus_out <= Divisor; 
        2'b10 : Data_Bus_out <= SegmentPairA;
        2'b11 : Data_Bus_out <= SegmentPairB;
      endcase
    else
      Data_Bus_out <= Data_Bus_out;


  always @ (negedge clk or posedge rstb)
    if( rstb == 1'b1 ) 
      begin
        Control      = 8'h00;
        Divisor      = 8'h00;
        SegmentPairA = 8'h00;
        SegmentPairB = 8'h00;
      end
    else if (Wr == 1'b1)
      case(Address)
        2'b00   : begin
                    Control      = Data_Bus_in;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
        2'b01   : begin
                    Control      = Control;
                    Divisor      = Data_Bus_in;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
        2'b10   : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = Data_Bus_in;
                    SegmentPairB = SegmentPairB;
                  end
        2'b11   : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = Data_Bus_in;
                  end
        default : begin
                    Control      = Control;
                    Divisor      = Divisor;
                    SegmentPairA = SegmentPairA;
                    SegmentPairB = SegmentPairB;
                  end
      endcase
    else
      begin
        Control      = Control;
        Divisor      = Divisor;
        SegmentPairA = SegmentPairA;
        SegmentPairB = SegmentPairB;
      end


  reg  [5:0] Bit;
  wire [3:0] BitA = SegmentPairA[7:4]; 
  wire [3:0] BitB = SegmentPairA[3:0]; 
  wire [3:0] BitC = SegmentPairB[7:4]; 
  wire [3:0] BitD = SegmentPairB[3:0]; 
  wire [6:0] Segments;
  wire       SegmentsDp;


  assign segDP = SegmentsDp;
  assign segA  = Segments[6];
  assign segB  = Segments[5];
  assign segC  = Segments[4];
  assign segD  = Segments[3];
  assign segE  = Segments[2];
  assign segF  = Segments[1];
  assign segG  = Segments[0];
  

  always @*
    case(segAnode)
      4'b0111 : Bit <= {Control[7:6], BitA};
      4'b1011 : Bit <= {Control[5:4], BitB};
      4'b1101 : Bit <= {Control[3:2], BitC};
      4'b1110 : Bit <= {Control[1:0], BitD};
      default : Bit <= 6'b000000;
    endcase
  
  reg  [23:0] Counter  = 0;
  wire [23:0] Divider  = {Divisor, 16'h0000};
  wire        advAnode = (Divider == Counter);
  
  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Counter <= 0;
    else if( advAnode == 1'b1 )
      Counter <= 0;
    else
      Counter <= Counter + 1;
  
  SegmentDecoder segmentDec   (clk, rst, advAnode, Bit[5], Bit[4], Bit[3:0], segAnode, Segments, SegmentsDp);

endmodule