data/full_repos/permissive/443770883/lab1/iter1/atestbench.v
1: b'%Error: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:7: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("dump.vcd");\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:8: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,tb);\n^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:10: Unsupported or unknown PLI call: $monitor\ninitial begin $monitor(t_a,t_b,t_w,t_x,t_y,t_z);  \n              ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10  \n^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10  \n^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab1/iter1/atestbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n#10  \n^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
reg t_a;
reg t_b;
wire t_w,t_x,t_y,t_z;

and1 a1(.a(t_a),.b(t_b),.w(t_w),.x(t_x),.y(t_y),.z(t_z));
initial begin $dumpfile("dump.vcd");
$dumpvars(0,tb);
end
initial begin $monitor(t_a,t_b,t_w,t_x,t_y,t_z);
t_a=1'b0;
t_b=1'b0;
#10
t_a=1'b0;
t_b=1'b1;
#10
t_a=1'b1;
t_b=1'b0;
#10
t_a=1'b1;
t_b=1'b1;
#10
t_a=0;
t_b=0;
end
endmodule
module tb;

reg t_a;
reg t_b;
wire t_w,t_x,t_y,t_z;

and1 a1(.a(t_a),.b(t_b),.w(t_w),.x(t_x),.y(t_y),.z(t_z));
initial begin $dumpfile("dump.vcd");
$dumpvars(0,tb);
end
initial begin $monitor(t_a,t_b,t_w,t_x,t_y,t_z);
t_a=1'b0;
t_b=1'b0;
#10
t_a=1'b0;
t_b=1'b1;
#10
t_a=1'b1;
t_b=1'b0;
#10
t_a=1'b1;
t_b=1'b1;
#10
t_a=0;
t_b=0;
end
endmodule