data/full_repos/permissive/522123651/testbench.v
1: b'%Error: data/full_repos/permissive/522123651/testbench.v:57: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/522123651/testbench.v:58: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,test); \n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n  forever #50000000 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1000000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Error: data/full_repos/permissive/522123651/testbench.v:97: Unsupported: wait statements\nwait(Alarm);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:98: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:99: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:100: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:101: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:102: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/522123651/testbench.v:103: Unsupported: Ignoring delay on this delayed statement.\n#1000000000;\n^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

 reg reset;
 reg clk;
 reg [1:0] H_in1;
 reg [3:0] H_in0;
 reg [3:0] M_in1;
 reg [3:0] M_in0;
 reg LD_time;
 reg LD_alarm;
 reg STOP_al;
 reg AL_ON;


 wire Alarm;
 wire [1:0] H_out1;
 wire [3:0] H_out0;
 wire [3:0] M_out1;
 wire [3:0] M_out0;
 wire [3:0] S_out1;
 wire [3:0] S_out0;

 
 clock uut (
 .reset(reset), 
 .clk(clk), 
 .H_in1(H_in1), 
 .H_in0(H_in0), 
 .M_in1(M_in1), 
 .M_in0(M_in0), 
 .LD_time(LD_time), 
 .LD_alarm(LD_alarm), 
 .STOP_al(STOP_al), 
 .AL_ON(AL_ON), 
 .Alarm(Alarm), 
 .H_out1(H_out1), 
 .H_out0(H_out0), 
 .M_out1(M_out1), 
 .M_out0(M_out0), 
 .S_out1(S_out1), 
 .S_out0(S_out0)
 );

 initial begin
  $dumpfile("test.vcd");
  $dumpvars(0,test); 
  clk = 0;
  forever #50000000 clk = ~clk;
 end
 initial begin

 reset = 1;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 1;
 M_in0 = 9;
 LD_time = 0;
 LD_alarm = 0;
 STOP_al = 0;
 AL_ON = 0;

 #1000000000;
 reset = 0;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 2;
 M_in0 = 0;
 LD_time = 0;
 LD_alarm = 1;
 STOP_al = 0;
 AL_ON = 1; 
 

#1000000000;
 reset = 0;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 2;
 M_in0 = 0;
 LD_time = 0;
 LD_alarm = 0;
 STOP_al = 0;
 AL_ON = 1;

wait(Alarm);
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
STOP_al = 1;

 
 end
endmodule
module test;


 reg reset;
 reg clk;
 reg [1:0] H_in1;
 reg [3:0] H_in0;
 reg [3:0] M_in1;
 reg [3:0] M_in0;
 reg LD_time;
 reg LD_alarm;
 reg STOP_al;
 reg AL_ON;


 wire Alarm;
 wire [1:0] H_out1;
 wire [3:0] H_out0;
 wire [3:0] M_out1;
 wire [3:0] M_out0;
 wire [3:0] S_out1;
 wire [3:0] S_out0;

 
 clock uut (
 .reset(reset), 
 .clk(clk), 
 .H_in1(H_in1), 
 .H_in0(H_in0), 
 .M_in1(M_in1), 
 .M_in0(M_in0), 
 .LD_time(LD_time), 
 .LD_alarm(LD_alarm), 
 .STOP_al(STOP_al), 
 .AL_ON(AL_ON), 
 .Alarm(Alarm), 
 .H_out1(H_out1), 
 .H_out0(H_out0), 
 .M_out1(M_out1), 
 .M_out0(M_out0), 
 .S_out1(S_out1), 
 .S_out0(S_out0)
 );

 initial begin
  $dumpfile("test.vcd");
  $dumpvars(0,test); 
  clk = 0;
  forever #50000000 clk = ~clk;
 end
 initial begin

 reset = 1;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 1;
 M_in0 = 9;
 LD_time = 0;
 LD_alarm = 0;
 STOP_al = 0;
 AL_ON = 0;

 #1000000000;
 reset = 0;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 2;
 M_in0 = 0;
 LD_time = 0;
 LD_alarm = 1;
 STOP_al = 0;
 AL_ON = 1; 
 

#1000000000;
 reset = 0;
 H_in1 = 1;
 H_in0 = 0;
 M_in1 = 2;
 M_in0 = 0;
 LD_time = 0;
 LD_alarm = 0;
 STOP_al = 0;
 AL_ON = 1;

wait(Alarm);
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
STOP_al = 1;

 
 end
endmodule