data/full_repos/permissive/476728999/Experiment5/Dflipflop.v
data/verilator_xmls/47220a7c-2b1d-4120-9403-62638ab182b2.xml
module Dflipflop(Q, Q_inv, D, clock, reset);
    input D, clock, reset;
    output reg Q, Q_inv;
    always @(posedge clock or posedge reset)
    if (reset) begin
        Q <= 0;
        Q_inv <= 1; end
    else begin
        Q <= D;
        Q_inv <= ~D;
    end
    
endmodule
module Dflipflop(Q, Q_inv, D, clock, reset);

    input D, clock, reset;
    output reg Q, Q_inv;
    always @(posedge clock or posedge reset)
    if (reset) begin
        Q <= 0;
        Q_inv <= 1; end
    else begin
        Q <= D;
        Q_inv <= ~D;
    end
    
endmodule