data/full_repos/permissive/469273213/multiplier/rtl/boothEnc.v
data/verilator_xmls/ce8a8b99-7708-44ff-a66b-32008649f100.xml
module boothEnc (
    input   wire    [2:0]   in,
    output  reg     single,
    output  reg     double,
    output  reg     neg
);
    always @(in) begin

        case (in)
            3'd0: {single, double, neg} = 3'b000;
            3'd1: {single, double, neg} = 3'b100;
            3'd2: {single, double, neg} = 3'b100;
            3'd3: {single, double, neg} = 3'b010;
            3'd4: {single, double, neg} = 3'b011;
            3'd5: {single, double, neg} = 3'b101;
            3'd6: {single, double, neg} = 3'b101;
            3'd7: {single, double, neg} = 3'b001;
            default: {single, double, neg} = 3'b000;
        endcase
    end
    
endmodule
module boothEnc (
    input   wire    [2:0]   in,
    output  reg     single,
    output  reg     double,
    output  reg     neg
);

    always @(in) begin

        case (in)
            3'd0: {single, double, neg} = 3'b000;
            3'd1: {single, double, neg} = 3'b100;
            3'd2: {single, double, neg} = 3'b100;
            3'd3: {single, double, neg} = 3'b010;
            3'd4: {single, double, neg} = 3'b011;
            3'd5: {single, double, neg} = 3'b101;
            3'd6: {single, double, neg} = 3'b101;
            3'd7: {single, double, neg} = 3'b001;
            default: {single, double, neg} = 3'b000;
        endcase
    end
    
endmodule