data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv
1: b'%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:167: Extracting 4 bits from only 2 bit number\n                                                                                               : ... In instance sspim_cfg\n  case (sw_addr [3:0])\n                ^\n%Warning-SELRANGE: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:167: Selection index out of range: 3:0 outside 1:0\n                                                                                                          : ... In instance sspim_cfg\n  case (sw_addr [3:0])\n                ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:190: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_ctrl_be0 (\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl,data/full_repos/permissive/421663164/generic_register\n             data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl,data/full_repos/permissive/421663164/generic_register.v\n             data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl,data/full_repos/permissive/421663164/generic_register.sv\n             generic_register\n             generic_register.v\n             generic_register.sv\n             obj_dir/generic_register\n             obj_dir/generic_register.v\n             obj_dir/generic_register.sv\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:201: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_ctrl_be1 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:212: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_ctrl_be2 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:225: Cannot find file containing module: \'req_register\'\nreq_register #(0  ) u_spi_ctrl_req (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:245: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_din_be0 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:256: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_din_be1 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:267: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_din_be2 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_cfg.sv:279: Cannot find file containing module: \'generic_register\'\ngeneric_register #(8,0  ) u_spi_din_be3 (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module sspim_cfg (
              input  logic          mclk               ,
              input  logic          reset_n            ,
              
              output logic [1:0]    cfg_tgt_sel        ,
              
              output logic          cfg_op_req         ,
              output logic [1:0]    cfg_op_type        ,
              output logic [1:0]    cfg_transfer_size  ,
              output logic [5:0]    cfg_sck_period     ,
              output logic [4:0]    cfg_sck_cs_period  ,
              output logic [7:0]    cfg_cs_byte        ,
              output logic [31:0]   cfg_datain         ,
              input  logic [31:0]   cfg_dataout        ,
              input  logic          hware_op_done      ,
              



              input logic           reg_cs             ,
              input logic           reg_wr             ,
              input logic [7:0]     reg_addr           ,
              input logic [31:0]    reg_wdata          ,
              input logic [3:0]     reg_be             ,
              

              output logic [31:0]   reg_rdata          ,
              output logic          reg_ack            


        );






logic           sw_rd_en               ;
logic           sw_wr_en;
logic   [1:0]   sw_addr;
logic   [31:0]  sw_reg_wdata;
logic   [3:0]   wr_be  ;
logic           reg_cs_l;
logic           reg_cs_2l;

logic  [31:0]    reg_0;
logic  [31:0]    reg_1;
logic  [31:0]    reg_2;
logic  [31:0]    reg_out;








always @ (posedge mclk or negedge reset_n)
begin 
   if (reset_n == 1'b0)
   begin
    sw_addr       <= '0;
    sw_rd_en      <= '0;
    sw_wr_en      <= '0;
    sw_reg_wdata  <= '0;
    wr_be         <= '0;
    reg_cs_l      <= '0;
    reg_cs_2l     <= '0;
  end else begin
    sw_addr       <= reg_addr [3:2];
    sw_rd_en      <= reg_cs & !reg_wr;
    sw_wr_en      <= reg_cs & reg_wr;
    sw_reg_wdata  <= reg_wdata;
    wr_be         <= reg_be;
    reg_cs_l      <= reg_cs;
    reg_cs_2l     <= reg_cs_l;
  end
end





always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata [31:0]  <= 32'h0000_0000;
      reg_ack           <= 1'b0;
   end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
      reg_rdata [31:0]  <= reg_out [31:0];
      reg_ack           <= 1'b1;
   end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin 
      reg_ack           <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end



wire   sw_wr_en_0   = sw_wr_en & (sw_addr == 2'h0);
wire   sw_rd_en_0   = sw_rd_en & (sw_addr == 2'h0);
wire   sw_wr_en_1   = sw_wr_en & (sw_addr == 2'h1);
wire   sw_rd_en_1   = sw_rd_en & (sw_addr == 2'h1);
wire   sw_wr_en_2   = sw_wr_en & (sw_addr == 2'h2);
wire   sw_rd_en_2   = sw_rd_en & (sw_addr == 2'h2);
wire   sw_wr_en_3   = sw_wr_en & (sw_addr == 2'h3);
wire   sw_rd_en_3   = sw_rd_en & (sw_addr == 2'h3);


always @( *)
begin : preg_sel_Com

  reg_out [31:0] = 32'd0;

  case (sw_addr [3:0])
    4'b0000 : reg_out [31:0] = reg_0 [31:0];     
    4'b0001 : reg_out [31:0] = reg_1 [31:0];    
    4'b0010 : reg_out [31:0] = reg_2 [31:0];     
    default : reg_out [31:0] = 32'h0;
  endcase
end








assign    cfg_op_req         = reg_0[31];
assign    cfg_tgt_sel        = reg_0[24:23];
assign    cfg_op_type        = reg_0[22:21];
assign    cfg_transfer_size  = reg_0[20:19];
assign    cfg_sck_period     = reg_0[18:13];
assign    cfg_sck_cs_period  = reg_0[12:8];
assign    cfg_cs_byte        = reg_0[7:0];

generic_register #(8,0  ) u_spi_ctrl_be0 (
	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[7:0]        )
          );

generic_register #(8,0  ) u_spi_ctrl_be1 (
	      .we            ({8{sw_wr_en_0 & 
                                wr_be[1]   }}  ),		 
	      .data_in       (sw_reg_wdata[15:8]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[15:8]       )
          );

generic_register #(8,0  ) u_spi_ctrl_be2 (
	      .we            ({8{sw_wr_en_0 & 
                                wr_be[2]   }}  ),		 
	      .data_in       (sw_reg_wdata[23:16] ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[23:16]       )
          );

assign reg_0[30:24] = 7'h0;

req_register #(0  ) u_spi_ctrl_req (
	      .cpu_we       ({sw_wr_en_0 & 
                             wr_be[3]   }       ),		 
	      .cpu_req      (sw_reg_wdata[31]      ),
	      .hware_ack    (hware_op_done      ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[31]         )
          );







assign   cfg_datain        = reg_1[31:0]; 

generic_register #(8,0  ) u_spi_din_be0 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[7:0]        )
          );

generic_register #(8,0  ) u_spi_din_be1 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[1]   }}  ),		 
	      .data_in       (sw_reg_wdata[15:8]   ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[15:8]       )
          );

generic_register #(8,0  ) u_spi_din_be2 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[2]   }}  ),		 
	      .data_in       (sw_reg_wdata[23:16]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[23:16]      )
          );


generic_register #(8,0  ) u_spi_din_be3 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[3]   }}  ),		 
	      .data_in       (sw_reg_wdata[31:24]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[31:24]      )
          );





assign  reg_2 = cfg_dataout; 



endmodule
module sspim_cfg (
              input  logic          mclk               ,
              input  logic          reset_n            ,
              
              output logic [1:0]    cfg_tgt_sel        ,
              
              output logic          cfg_op_req         ,
              output logic [1:0]    cfg_op_type        ,
              output logic [1:0]    cfg_transfer_size  ,
              output logic [5:0]    cfg_sck_period     ,
              output logic [4:0]    cfg_sck_cs_period  ,
              output logic [7:0]    cfg_cs_byte        ,
              output logic [31:0]   cfg_datain         ,
              input  logic [31:0]   cfg_dataout        ,
              input  logic          hware_op_done      ,
              



              input logic           reg_cs             ,
              input logic           reg_wr             ,
              input logic [7:0]     reg_addr           ,
              input logic [31:0]    reg_wdata          ,
              input logic [3:0]     reg_be             ,
              

              output logic [31:0]   reg_rdata          ,
              output logic          reg_ack            


        );







logic           sw_rd_en               ;
logic           sw_wr_en;
logic   [1:0]   sw_addr;
logic   [31:0]  sw_reg_wdata;
logic   [3:0]   wr_be  ;
logic           reg_cs_l;
logic           reg_cs_2l;

logic  [31:0]    reg_0;
logic  [31:0]    reg_1;
logic  [31:0]    reg_2;
logic  [31:0]    reg_out;








always @ (posedge mclk or negedge reset_n)
begin 
   if (reset_n == 1'b0)
   begin
    sw_addr       <= '0;
    sw_rd_en      <= '0;
    sw_wr_en      <= '0;
    sw_reg_wdata  <= '0;
    wr_be         <= '0;
    reg_cs_l      <= '0;
    reg_cs_2l     <= '0;
  end else begin
    sw_addr       <= reg_addr [3:2];
    sw_rd_en      <= reg_cs & !reg_wr;
    sw_wr_en      <= reg_cs & reg_wr;
    sw_reg_wdata  <= reg_wdata;
    wr_be         <= reg_be;
    reg_cs_l      <= reg_cs;
    reg_cs_2l     <= reg_cs_l;
  end
end





always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata [31:0]  <= 32'h0000_0000;
      reg_ack           <= 1'b0;
   end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
      reg_rdata [31:0]  <= reg_out [31:0];
      reg_ack           <= 1'b1;
   end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin 
      reg_ack           <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end



wire   sw_wr_en_0   = sw_wr_en & (sw_addr == 2'h0);
wire   sw_rd_en_0   = sw_rd_en & (sw_addr == 2'h0);
wire   sw_wr_en_1   = sw_wr_en & (sw_addr == 2'h1);
wire   sw_rd_en_1   = sw_rd_en & (sw_addr == 2'h1);
wire   sw_wr_en_2   = sw_wr_en & (sw_addr == 2'h2);
wire   sw_rd_en_2   = sw_rd_en & (sw_addr == 2'h2);
wire   sw_wr_en_3   = sw_wr_en & (sw_addr == 2'h3);
wire   sw_rd_en_3   = sw_rd_en & (sw_addr == 2'h3);


always @( *)
begin : preg_sel_Com

  reg_out [31:0] = 32'd0;

  case (sw_addr [3:0])
    4'b0000 : reg_out [31:0] = reg_0 [31:0];     
    4'b0001 : reg_out [31:0] = reg_1 [31:0];    
    4'b0010 : reg_out [31:0] = reg_2 [31:0];     
    default : reg_out [31:0] = 32'h0;
  endcase
end








assign    cfg_op_req         = reg_0[31];
assign    cfg_tgt_sel        = reg_0[24:23];
assign    cfg_op_type        = reg_0[22:21];
assign    cfg_transfer_size  = reg_0[20:19];
assign    cfg_sck_period     = reg_0[18:13];
assign    cfg_sck_cs_period  = reg_0[12:8];
assign    cfg_cs_byte        = reg_0[7:0];

generic_register #(8,0  ) u_spi_ctrl_be0 (
	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[7:0]        )
          );

generic_register #(8,0  ) u_spi_ctrl_be1 (
	      .we            ({8{sw_wr_en_0 & 
                                wr_be[1]   }}  ),		 
	      .data_in       (sw_reg_wdata[15:8]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[15:8]       )
          );

generic_register #(8,0  ) u_spi_ctrl_be2 (
	      .we            ({8{sw_wr_en_0 & 
                                wr_be[2]   }}  ),		 
	      .data_in       (sw_reg_wdata[23:16] ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[23:16]       )
          );

assign reg_0[30:24] = 7'h0;

req_register #(0  ) u_spi_ctrl_req (
	      .cpu_we       ({sw_wr_en_0 & 
                             wr_be[3]   }       ),		 
	      .cpu_req      (sw_reg_wdata[31]      ),
	      .hware_ack    (hware_op_done      ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[31]         )
          );







assign   cfg_datain        = reg_1[31:0]; 

generic_register #(8,0  ) u_spi_din_be0 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[7:0]        )
          );

generic_register #(8,0  ) u_spi_din_be1 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[1]   }}  ),		 
	      .data_in       (sw_reg_wdata[15:8]   ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[15:8]       )
          );

generic_register #(8,0  ) u_spi_din_be2 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[2]   }}  ),		 
	      .data_in       (sw_reg_wdata[23:16]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[23:16]      )
          );


generic_register #(8,0  ) u_spi_din_be3 (
	      .we            ({8{sw_wr_en_1 & 
                                wr_be[3]   }}  ),		 
	      .data_in       (sw_reg_wdata[31:24]  ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_1[31:24]      )
          );





assign  reg_2 = cfg_dataout; 



endmodule