data/full_repos/permissive/488490114/ANODE_DC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/488490114/ANODE_DC.v:9: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'ANODE_CNT\' generates 3 bits.\n                                                                 : ... In instance ANODE_DC\n case(ANODE_CNT)\n ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ANODE_DC(
input [2:0]ANODE_CNT,
output reg [5:0]ANODE
);


always@ *
begin
	case(ANODE_CNT)
		4'd0: ANODE = 6'b000001;
		4'd1: ANODE = 6'b000010;
		4'd2: ANODE = 6'b000100;
		4'd4: ANODE = 6'b001000;
		4'd3: ANODE = 6'b010000;
		4'd5: ANODE = 6'b100000;
		default: ANODE = 6'b000000;
	endcase
end

endmodule
module ANODE_DC(
input [2:0]ANODE_CNT,
output reg [5:0]ANODE
);



always@ *
begin
	case(ANODE_CNT)
		4'd0: ANODE = 6'b000001;
		4'd1: ANODE = 6'b000010;
		4'd2: ANODE = 6'b000100;
		4'd4: ANODE = 6'b001000;
		4'd3: ANODE = 6'b010000;
		4'd5: ANODE = 6'b100000;
		default: ANODE = 6'b000000;
	endcase
end

endmodule