data/full_repos/permissive/433389019/lib/mul.v
1: b'%Error: data/full_repos/permissive/433389019/lib/mul.v:1: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433389019/lib,data/full_repos/permissive/433389019/defines.vh\n             data/full_repos/permissive/433389019/lib,data/full_repos/permissive/433389019/defines.vh.v\n             data/full_repos/permissive/433389019/lib,data/full_repos/permissive/433389019/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/433389019/lib/mul.v:42: Define or directive not defined: \'`MulFree\'\n   state <= `MulFree;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   state <= `MulFree;\n                    ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:43: Define or directive not defined: \'`ZeroWord\'\n   result_o <= {`ZeroWord,`ZeroWord};\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:43: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   result_o <= {`ZeroWord,`ZeroWord};\n                         ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:43: Define or directive not defined: \'`ZeroWord\'\n   result_o <= {`ZeroWord,`ZeroWord};\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:44: Define or directive not defined: \'`MulResultNotReady\'\n   ready_o <= `MulResultNotReady;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ready_o <= `MulResultNotReady;\n                                ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:47: Define or directive not defined: \'`MulFree\'\n    `MulFree: begin    \n    ^~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:47: syntax error, unexpected \':\', expecting endcase\n    `MulFree: begin    \n            ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:48: Define or directive not defined: \'`MulStart\'\n     if (start_i == `MulStart && annul_i == 1\'b0) begin\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:49: Define or directive not defined: \'`ZeroWord\'\n      if(opdata1_i == `ZeroWord || opdata2_i == `ZeroWord) begin    \n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:49: Define or directive not defined: \'`ZeroWord\'\n      if(opdata1_i == `ZeroWord || opdata2_i == `ZeroWord) begin    \n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:50: Define or directive not defined: \'`MulByZero\'\n       state <= `MulByZero;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:52: Define or directive not defined: \'`MulOn\'\n       state <= `MulOn;      \n                ^~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:64: Define or directive not defined: \'`ZeroWord\'\n       product <= {`ZeroWord, `ZeroWord};\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:64: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n       product <= {`ZeroWord, `ZeroWord};\n                            ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:64: Define or directive not defined: \'`ZeroWord\'\n       product <= {`ZeroWord, `ZeroWord};\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:67: syntax error, unexpected end\n     end else begin\n     ^~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:68: Define or directive not defined: \'`MulResultNotReady\'\n      ready_o <= `MulResultNotReady;\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:69: Define or directive not defined: \'`ZeroWord\'\n      result_o <= {`ZeroWord, `ZeroWord};\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:69: Define or directive not defined: \'`ZeroWord\'\n      result_o <= {`ZeroWord, `ZeroWord};\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:73: Define or directive not defined: \'`MulByZero\'\n    `MulByZero: begin    \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:74: Define or directive not defined: \'`ZeroWord\'\n     product <= {`ZeroWord, `ZeroWord};\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:74: Define or directive not defined: \'`ZeroWord\'\n     product <= {`ZeroWord, `ZeroWord};\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:75: Define or directive not defined: \'`MulEnd\'\n     state <= `MulEnd;\n              ^~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:78: Define or directive not defined: \'`MulOn\'\n    `MulOn: begin     \n    ^~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:91: Define or directive not defined: \'`MulEnd\'\n       state <= `MulEnd;\n                ^~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:95: Define or directive not defined: \'`MulFree\'\n      state <= `MulFree;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:99: Define or directive not defined: \'`MulEnd\'\n    `MulEnd: begin    \n    ^~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:101: Define or directive not defined: \'`MulResultReady\'\n     ready_o <= `MulResultReady;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:102: Define or directive not defined: \'`MulStop\'\n     if (start_i == `MulStop) begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:102: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     if (start_i == `MulStop) begin\n                            ^\n%Error: data/full_repos/permissive/433389019/lib/mul.v:103: Define or directive not defined: \'`MulFree\'\n      state <= `MulFree;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:104: Define or directive not defined: \'`MulResultNotReady\'\n      ready_o <= `MulResultNotReady;\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:105: Define or directive not defined: \'`ZeroWord\'\n      result_o <= {`ZeroWord, `ZeroWord};\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/lib/mul.v:105: Define or directive not defined: \'`ZeroWord\'\n      result_o <= {`ZeroWord, `ZeroWord};\n                              ^~~~~~~~~\n%Error: Cannot continue\n'
module mul(
	input wire rst,
	input wire clk,
	input wire signed_mul_i,
	input wire[31:0] opdata1_i,
	input wire[31:0] opdata2_i,
	input wire start_i,
	input wire annul_i,
	output reg[63:0] result_o,
	output reg ready_o
);
	reg [5:0] cnt;
	reg [63:0] product;
	reg [1:0] state;
	reg[63:0] multiplicand;
	reg[31:0] temp_op1;
	reg[31:0] temp_op2;
	
	always @ (posedge clk) begin
		if (rst) begin
			state <= `MulFree;
			result_o <= {`ZeroWord,`ZeroWord};
			ready_o <= `MulResultNotReady;
		end else begin
			case(state)
				`MulFree: begin
					if (start_i == `MulStart && annul_i == 1'b0) begin
						if(opdata1_i == `ZeroWord || opdata2_i == `ZeroWord) begin
							state <= `MulByZero;
						end else begin
							state <= `MulOn;
							cnt <= 6'b000000;
							if(signed_mul_i == 1'b1 && opdata1_i[31] == 1'b1) begin
								temp_op1 = ~opdata1_i + 1;
							end else begin
								temp_op1 = opdata1_i;
							end
							if (signed_mul_i == 1'b1 && opdata2_i[31] == 1'b1 ) begin
								temp_op2 = ~opdata2_i + 1;
							end else begin
								temp_op2 = opdata2_i;
							end
							product <= {`ZeroWord, `ZeroWord};
							multiplicand <= {32'b0,temp_op1};
						end
					end else begin
						ready_o <= `MulResultNotReady;
						result_o <= {`ZeroWord, `ZeroWord};
					end
				end
				
				`MulByZero: begin
					product <= {`ZeroWord, `ZeroWord};
					state <= `MulEnd;
				end
				
				`MulOn: begin
					if(annul_i == 1'b0) begin
						if(cnt != 6'b100000) begin
							if (temp_op2[0] == 1'b1) begin
								product <= product + multiplicand;
							end
							multiplicand = {multiplicand[62:0],1'b0};
							temp_op2 = {1'b0,temp_op2[31:1]};
							cnt <= cnt +1;
						end else begin
							if ((signed_mul_i == 1'b1) && ((opdata1_i[31] ^ opdata2_i[31]) == 1'b1)) begin
								product <= (~product + 1);
							end
							state <= `MulEnd;
							cnt <= 6'b000000;
						end
					end else begin	
						state <= `MulFree;
					end
				end
				
				`MulEnd: begin
					result_o <= product;
					ready_o <= `MulResultReady;
					if (start_i == `MulStop) begin
						state <= `MulFree;
						ready_o <= `MulResultNotReady;
						result_o <= {`ZeroWord, `ZeroWord};
					end
				end
			endcase
		end
	end


endmodule
module mul(
	input wire rst,
	input wire clk,
	input wire signed_mul_i,
	input wire[31:0] opdata1_i,
	input wire[31:0] opdata2_i,
	input wire start_i,
	input wire annul_i,
	output reg[63:0] result_o,
	output reg ready_o
);

	reg [5:0] cnt;
	reg [63:0] product;
	reg [1:0] state;
	reg[63:0] multiplicand;
	reg[31:0] temp_op1;
	reg[31:0] temp_op2;
	
	always @ (posedge clk) begin
		if (rst) begin
			state <= `MulFree;
			result_o <= {`ZeroWord,`ZeroWord};
			ready_o <= `MulResultNotReady;
		end else begin
			case(state)
				`MulFree: begin
					if (start_i == `MulStart && annul_i == 1'b0) begin
						if(opdata1_i == `ZeroWord || opdata2_i == `ZeroWord) begin
							state <= `MulByZero;
						end else begin
							state <= `MulOn;
							cnt <= 6'b000000;
							if(signed_mul_i == 1'b1 && opdata1_i[31] == 1'b1) begin
								temp_op1 = ~opdata1_i + 1;
							end else begin
								temp_op1 = opdata1_i;
							end
							if (signed_mul_i == 1'b1 && opdata2_i[31] == 1'b1 ) begin
								temp_op2 = ~opdata2_i + 1;
							end else begin
								temp_op2 = opdata2_i;
							end
							product <= {`ZeroWord, `ZeroWord};
							multiplicand <= {32'b0,temp_op1};
						end
					end else begin
						ready_o <= `MulResultNotReady;
						result_o <= {`ZeroWord, `ZeroWord};
					end
				end
				
				`MulByZero: begin
					product <= {`ZeroWord, `ZeroWord};
					state <= `MulEnd;
				end
				
				`MulOn: begin
					if(annul_i == 1'b0) begin
						if(cnt != 6'b100000) begin
							if (temp_op2[0] == 1'b1) begin
								product <= product + multiplicand;
							end
							multiplicand = {multiplicand[62:0],1'b0};
							temp_op2 = {1'b0,temp_op2[31:1]};
							cnt <= cnt +1;
						end else begin
							if ((signed_mul_i == 1'b1) && ((opdata1_i[31] ^ opdata2_i[31]) == 1'b1)) begin
								product <= (~product + 1);
							end
							state <= `MulEnd;
							cnt <= 6'b000000;
						end
					end else begin	
						state <= `MulFree;
					end
				end
				
				`MulEnd: begin
					result_o <= product;
					ready_o <= `MulResultReady;
					if (start_i == `MulStop) begin
						state <= `MulFree;
						ready_o <= `MulResultNotReady;
						result_o <= {`ZeroWord, `ZeroWord};
					end
				end
			endcase
		end
	end


endmodule