data/full_repos/permissive/440792992/hardware/instMEM.v
1: b'%Error: data/full_repos/permissive/440792992/hardware/instMEM.v:8: Cannot find include file: configure.h\n`include "configure.h" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.v\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.sv\n             configure.h\n             configure.h.v\n             configure.h.sv\n             obj_dir/configure.h\n             obj_dir/configure.h.v\n             obj_dir/configure.h.sv\n%Error: data/full_repos/permissive/440792992/hardware/instMEM.v:14: Define or directive not defined: \'`IMEM_ADDRW\'\n    input      [`IMEM_ADDRW-1:0] raddr,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/instMEM.v:19: Define or directive not defined: \'`IMEM_DEPTH\'\n    reg [32*4-1:0] instmem [0:`IMEM_DEPTH-1];\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/instMEM.v:34: syntax error, unexpected INTEGER NUMBER\n            rinst <= (32*4)\'b0;\n                           ^~~\n%Error: Exiting due to 4 error(s)\n'
module instMEM(
    input                        i_clk,
    input                        i_resetn,
    input                        valid,
    input      [`IMEM_ADDRW-1:0] raddr,
    output                       ready,
    output reg [32*4-1:0]        rinst
);
   
    reg [32*4-1:0] instmem [0:`IMEM_DEPTH-1];
    
    initial begin
        if (INST_MEM_INIT_FILE != "") begin
            $display("Preloading instruction memory data from %s", INST_MEM_INIT_FILE);
            $readmemh(INST_MEM_INIT_FILE, instmem);
        end
    end
    
    reg rd_ready;   
    assign ready = valid && rd_ready;
    
    always @(posedge i_clk or negedge i_resetn) begin
        if(~i_resetn) begin
            rd_ready <= 1'b0;
            rinst <= (32*4)'b0;
        end else begin
            if(valid) begin
                rd_ready <= 1'b1;
                rinst <= instmem[raddr];
            end else begin
                rd_ready <= 1'b0;
            end
        end
    end
endmodule
module instMEM(
    input                        i_clk,
    input                        i_resetn,
    input                        valid,
    input      [`IMEM_ADDRW-1:0] raddr,
    output                       ready,
    output reg [32*4-1:0]        rinst
);

   
    reg [32*4-1:0] instmem [0:`IMEM_DEPTH-1];
    
    initial begin
        if (INST_MEM_INIT_FILE != "") begin
            $display("Preloading instruction memory data from %s", INST_MEM_INIT_FILE);
            $readmemh(INST_MEM_INIT_FILE, instmem);
        end
    end
    
    reg rd_ready;   
    assign ready = valid && rd_ready;
    
    always @(posedge i_clk or negedge i_resetn) begin
        if(~i_resetn) begin
            rd_ready <= 1'b0;
            rinst <= (32*4)'b0;
        end else begin
            if(valid) begin
                rd_ready <= 1'b1;
                rinst <= instmem[raddr];
            end else begin
                rd_ready <= 1'b0;
            end
        end
    end
endmodule