data/full_repos/permissive/44929513/main.v
1: b'%Error: data/full_repos/permissive/44929513/main.v:2: Cannot find include file: contador.v\n`include "contador.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/contador.v\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/contador.v.v\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/contador.v.sv\n             contador.v\n             contador.v.v\n             contador.v.sv\n             obj_dir/contador.v\n             obj_dir/contador.v.v\n             obj_dir/contador.v.sv\n%Error: data/full_repos/permissive/44929513/main.v:3: Cannot find include file: fsmGB.v\n`include "fsmGB.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/44929513/main.v:17: Unsupported or unknown PLI call: $monitor\n    $monitor("%g\\t %d  %d %b    %d %b    %b %d", $time, clock, a,a,b,b, ab_result,ab_result);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5 a <= 4;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #5 start <=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #30;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #5 start <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #30 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/main.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1 clock <= ~clock;\n    ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module main;
reg signed [3:0] a,b;
wire signed [7:0] ab_result;
reg clock, reset, start;
wire initCount, bigger_than_max;
wire [2:0] val;
initial begin
    clock<= 0;
    reset <=0;
    start<=0;
    a<=0;
    b<=0;
    $display("time\t clock   a       b         result");
    $monitor("%g\t %d  %d %b    %d %b    %b %d", $time, clock, a,a,b,b, ab_result,ab_result);
    #5 a <= 4;
    b <= 3;
    start <=1;
    #5 start <=0;
    #30;
    a <= -3;
    b <= 5;
    start <= 1;
    #5 start <= 0;
    #30 $finish;
end

always @(*)
    #1 clock <= ~clock;

contador U_contador(
    .reset(!initCount),
    .max_number(val),
    .clock(clock),
    .bigger_than_max(bigger_than_max)
);

fsm U_fsm(
    .clock(clock),
    .reset(reset),
    .start(start),
    .a(a),
    .b(b),
    .contBETval(bigger_than_max),
    .initCount(initCount),
    .countVal(val),
    .ab_result(ab_result)
);

endmodule
module main;

reg signed [3:0] a,b;
wire signed [7:0] ab_result;
reg clock, reset, start;
wire initCount, bigger_than_max;
wire [2:0] val;
initial begin
    clock<= 0;
    reset <=0;
    start<=0;
    a<=0;
    b<=0;
    $display("time\t clock   a       b         result");
    $monitor("%g\t %d  %d %b    %d %b    %b %d", $time, clock, a,a,b,b, ab_result,ab_result);
    #5 a <= 4;
    b <= 3;
    start <=1;
    #5 start <=0;
    #30;
    a <= -3;
    b <= 5;
    start <= 1;
    #5 start <= 0;
    #30 $finish;
end

always @(*)
    #1 clock <= ~clock;

contador U_contador(
    .reset(!initCount),
    .max_number(val),
    .clock(clock),
    .bigger_than_max(bigger_than_max)
);

fsm U_fsm(
    .clock(clock),
    .reset(reset),
    .start(start),
    .a(a),
    .b(b),
    .contBETval(bigger_than_max),
    .initCount(initCount),
    .countVal(val),
    .ab_result(ab_result)
);

endmodule