data/full_repos/permissive/494664634/AxiS2MMTest/src/hdl/AxiS2MMTest.v
data/verilator_xmls/8782da5f-17bb-4ce7-b810-c4989e6c3866.xml
module DmaInfo(
  input  [31:0] addr,
  input  [31:0] blength,
  output [31:0] offset,
  output [31:0] wlength
);
  wire [29:0] waddr = addr[31:2];
  wire [31:0] addr_n = addr + blength;
  wire [31:0] _wlength_T_1 = addr_n + 32'h3;
  wire [29:0] _wlength_T_4 = _wlength_T_1[31:2] - waddr;
  assign offset = {waddr, 2'h0};
  assign wlength = {{2'd0}, _wlength_T_4};
endmodule
module DmaInfo(
  input  [31:0] addr,
  input  [31:0] blength,
  output [31:0] offset,
  output [31:0] wlength
);

  wire [29:0] waddr = addr[31:2];
  wire [31:0] addr_n = addr + blength;
  wire [31:0] _wlength_T_1 = addr_n + 32'h3;
  wire [29:0] _wlength_T_4 = _wlength_T_1[31:2] - waddr;
  assign offset = {waddr, 2'h0};
  assign wlength = {{2'd0}, _wlength_T_4};
endmodule