data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.sv:50: Logical Operator IF expects 1 bit on the If, but If\'s TESTPLUSARGS \'DISPLAY_ERR_RAM_OFF\' generates 32 bits.\n                                                                                                                                          : ... In instance iramrwpx\n   if($test$plusargs("DISPLAY_ERR_RAM_OFF"))  DISPLAY_ERR_RAM=1\'b0;\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.sv:56: Operator ASSOCSEL expects 32 bits on the Associative select, but Associative select\'s VARREF \'wa\' generates 9 bits.\n                                                                                                                                          : ... In instance iramrwpx\n         ram[wa] = wdi;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.sv:59: Operator ASSOCSEL expects 32 bits on the Associative select, but Associative select\'s VARREF \'wa\' generates 9 bits.\n                                                                                                                                          : ... In instance iramrwpx\n         ram[wa] = wdi;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.sv:76: Operator ASSOCSEL expects 32 bits on the Associative select, but Associative select\'s VARREF \'ra\' generates 9 bits.\n                                                                                                                                          : ... In instance iramrwpx\n          rdo  <= ram[ra];\n                     ^\n%Error: Exiting due to 4 warning(s)\n'
module iramrwpx
    (
     wclk,
     wa,
     we,
     wdi,
     
     rclk,
     ra,
     re,
     rdo,
     
     test,
     mask
     );

parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               wclk;
input bit [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   wdi;
input               rclk;
input bit [ADDRBIT-1:0] ra;
input               re;
output logic [WIDTH-1:0]  rdo;
input               mask;
input               test;

bit [WIDTH-1:0] ram [int];

bit  DISPLAY_ERR_RAM;
initial begin
   if($test$plusargs("DISPLAY_ERR_RAM_OFF"))  DISPLAY_ERR_RAM=1'b0;
	 else DISPLAY_ERR_RAM=1'b1;
end
always @ (posedge wclk) begin
   if (we & (!test)) begin
      if (re & (wa === ra)) begin
         ram[wa] = wdi;
         if (DISPLAY_ERR_RAM) $display("%m ERR_RAM: WR and RD at the same address @wclk at %h %t",ra,$time);
      end else begin
         ram[wa] = wdi;
      end
   end
end

always @ (posedge rclk) 
	begin
   	if (test)   rdo <= {WIDTH{1'b0}};
   	else if (re | mask) 
		begin
      	if (we & (wa === ra)) 
	      	begin
          	rdo <= {WIDTH{1'bx}};
          	if (DISPLAY_ERR_RAM) $display("%m ERR_RAM: RD and WR at the same address @rclk at %h %t",ra,$time);
          	end 
	  	else 
	     	begin
         	rdo  <= ram[ra];
         	end
	  	end 
	else 
		begin
        rdo  <= {WIDTH{1'b0}};
	    end
    end


wire   sameaddr;
assign sameaddr = re & we & (wa === ra);

endmodule
module iramrwpx
    (
     wclk,
     wa,
     we,
     wdi,
     
     rclk,
     ra,
     re,
     rdo,
     
     test,
     mask
     );


parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               wclk;
input bit [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   wdi;
input               rclk;
input bit [ADDRBIT-1:0] ra;
input               re;
output logic [WIDTH-1:0]  rdo;
input               mask;
input               test;

bit [WIDTH-1:0] ram [int];

bit  DISPLAY_ERR_RAM;
initial begin
   if($test$plusargs("DISPLAY_ERR_RAM_OFF"))  DISPLAY_ERR_RAM=1'b0;
	 else DISPLAY_ERR_RAM=1'b1;
end
always @ (posedge wclk) begin
   if (we & (!test)) begin
      if (re & (wa === ra)) begin
         ram[wa] = wdi;
         if (DISPLAY_ERR_RAM) $display("%m ERR_RAM: WR and RD at the same address @wclk at %h %t",ra,$time);
      end else begin
         ram[wa] = wdi;
      end
   end
end

always @ (posedge rclk) 
	begin
   	if (test)   rdo <= {WIDTH{1'b0}};
   	else if (re | mask) 
		begin
      	if (we & (wa === ra)) 
	      	begin
          	rdo <= {WIDTH{1'bx}};
          	if (DISPLAY_ERR_RAM) $display("%m ERR_RAM: RD and WR at the same address @rclk at %h %t",ra,$time);
          	end 
	  	else 
	     	begin
         	rdo  <= ram[ra];
         	end
	  	end 
	else 
		begin
        rdo  <= {WIDTH{1'b0}};
	    end
    end


wire   sameaddr;
assign sameaddr = re & we & (wa === ra);

endmodule