data/full_repos/permissive/501625904/src/tb/tb_timer_core.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:96: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:110: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:165: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:184: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:187: Unsupported: Ignoring delay on this delayed statement.\n          #(CLK_PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:237: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:239: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:242: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:131: Can\'t find definition of \'start\' in dotted variable: \'dut.start\'\n        dut.start, dut.stop, dut.ready);\n            ^~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:131: Can\'t find definition of \'stop\' in dotted variable: \'dut.stop\'\n        dut.start, dut.stop, dut.ready);\n                       ^~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:131: Can\'t find definition of \'ready\' in dotted variable: \'dut.ready\'\n        dut.start, dut.stop, dut.ready);\n                                 ^~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:133: Can\'t find definition of \'prescaler_value\' in dotted variable: \'dut.prescaler_value\'\n        dut.prescaler_value, dut.timer_value);\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:133: Can\'t find definition of \'timer_value\' in dotted variable: \'dut.timer_value\'\n        dut.prescaler_value, dut.timer_value);\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:137: Can\'t find definition of \'prescaler_reg\' in dotted variable: \'dut.prescaler_reg\'\n        dut.prescaler_reg, dut.prescaler_new);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:137: Can\'t find definition of \'prescaler_new\' in dotted variable: \'dut.prescaler_new\'\n        dut.prescaler_reg, dut.prescaler_new);\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:139: Can\'t find definition of \'prescaler_set\' in dotted variable: \'dut.prescaler_set\'\n        dut.prescaler_set, dut.prescaler_dec);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:139: Can\'t find definition of \'prescaler_dec\' in dotted variable: \'dut.prescaler_dec\'\n        dut.prescaler_set, dut.prescaler_dec);\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:142: Can\'t find definition of \'timer_reg\' in dotted variable: \'dut.timer_reg\'\n        dut.timer_reg, dut.timer_new);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:142: Can\'t find definition of \'timer_new\' in dotted variable: \'dut.timer_new\'\n        dut.timer_reg, dut.timer_new);\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:144: Can\'t find definition of \'timer_set\' in dotted variable: \'dut.timer_set\'\n        dut.timer_set, dut.timer_dec);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:144: Can\'t find definition of \'timer_dec\' in dotted variable: \'dut.timer_dec\'\n        dut.timer_set, dut.timer_dec);\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:147: Can\'t find definition of \'core_ctrl_reg\' in dotted variable: \'dut.core_ctrl_reg\'\n        dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:147: Can\'t find definition of \'core_ctrl_new\' in dotted variable: \'dut.core_ctrl_new\'\n        dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501625904/src/tb/tb_timer_core.v:147: Can\'t find definition of \'core_ctrl_we\' in dotted variable: \'dut.core_ctrl_we\'\n        dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n                                                  ^~~~~~~~~~~~\n%Error: Exiting due to 16 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_timer_core();




  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_start;
  reg           tb_stop;
  reg  [31 : 0] tb_prescaler;
  reg  [31 : 0] tb_timer;
  wire [31 : 0] tb_curr_prescaler;
  wire [31 : 0] tb_curr_timer;
  wire          tb_ready;





  timer_core dut(
		 .clk(tb_clk),
                 .reset_n(tb_reset_n),
                 .prescaler_value(tb_prescaler),
		 .timer_value(tb_timer),
		 .start(tb_start),
		 .stop(tb_stop),
		 .curr_prescaler(tb_curr_prescaler),
		 .curr_timer(tb_curr_timer),
		 .ready(tb_ready)
                );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("");
      $display("Inputs and outputs:");
      $display("start: 0x%1x, stop: 0x%1x, ready: 0x%1x",
	       dut.start, dut.stop, dut.ready);
      $display("prescaler_value: 0x%08x, timer_value: 0x%08x",
	       dut.prescaler_value, dut.timer_value);
      $display("");
      $display("Internal state:");
      $display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x",
	       dut.prescaler_reg, dut.prescaler_new);
      $display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x",
	       dut.prescaler_set, dut.prescaler_dec);
      $display("");
      $display("timer_reg: 0x%08x, timer_new: 0x%08x",
	       dut.timer_reg, dut.timer_new);
      $display("timer_set: 0x%1x, timer_dec: 0x%1x",
	       dut.timer_set, dut.timer_dec);
      $display("");
      $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
	       dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
      $display("");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("--- DUT before reset:");
      dump_dut_state();
      $display("--- Toggling reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
      $display("--- DUT after reset:");
      dump_dut_state();
    end
  endtask











  task wait_ready;
    begin
      #(2 * CLK_PERIOD);
      while (!tb_ready)
        begin
          #(CLK_PERIOD);
          if (DUMP_WAIT)
            begin
              dump_dut_state();
            end
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk     = 0;
      tb_reset_n = 1;

      tb_start     = 1'h0;
      tb_stop      = 1'h0;
      tb_prescaler = 32'h0;
      tb_timer     = 32'h0;
    end
  endtask









  task test1;
    begin
      tc_ctr = tc_ctr + 1;
      tb_monitor = 1;

      $display("--- test1 started.");
      dump_dut_state();
      tb_prescaler = 32'h6;
      tb_timer     = 32'h9;
      #(CLK_PERIOD);
      tb_start = 1'h1;
      #(CLK_PERIOD);
      tb_start = 1'h0;
      wait_ready();
      #(CLK_PERIOD);
      tb_monitor = 0;
      $display("--- test1 completed.");
      $display("");
    end
  endtask







  initial
    begin : timer_core_test
      $display("--- Simulation of TIMER core started.");
      $display("");

      init_sim();
      reset_dut();

      test1();

      $display("");
      $display("--- Simulation of timer core completed.");
      $finish;
    end
endmodule
module tb_timer_core();





  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_start;
  reg           tb_stop;
  reg  [31 : 0] tb_prescaler;
  reg  [31 : 0] tb_timer;
  wire [31 : 0] tb_curr_prescaler;
  wire [31 : 0] tb_curr_timer;
  wire          tb_ready;





  timer_core dut(
		 .clk(tb_clk),
                 .reset_n(tb_reset_n),
                 .prescaler_value(tb_prescaler),
		 .timer_value(tb_timer),
		 .start(tb_start),
		 .stop(tb_stop),
		 .curr_prescaler(tb_curr_prescaler),
		 .curr_timer(tb_curr_timer),
		 .ready(tb_ready)
                );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("");
      $display("Inputs and outputs:");
      $display("start: 0x%1x, stop: 0x%1x, ready: 0x%1x",
	       dut.start, dut.stop, dut.ready);
      $display("prescaler_value: 0x%08x, timer_value: 0x%08x",
	       dut.prescaler_value, dut.timer_value);
      $display("");
      $display("Internal state:");
      $display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x",
	       dut.prescaler_reg, dut.prescaler_new);
      $display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x",
	       dut.prescaler_set, dut.prescaler_dec);
      $display("");
      $display("timer_reg: 0x%08x, timer_new: 0x%08x",
	       dut.timer_reg, dut.timer_new);
      $display("timer_set: 0x%1x, timer_dec: 0x%1x",
	       dut.timer_set, dut.timer_dec);
      $display("");
      $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
	       dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
      $display("");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("--- DUT before reset:");
      dump_dut_state();
      $display("--- Toggling reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
      $display("--- DUT after reset:");
      dump_dut_state();
    end
  endtask











  task wait_ready;
    begin
      #(2 * CLK_PERIOD);
      while (!tb_ready)
        begin
          #(CLK_PERIOD);
          if (DUMP_WAIT)
            begin
              dump_dut_state();
            end
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk     = 0;
      tb_reset_n = 1;

      tb_start     = 1'h0;
      tb_stop      = 1'h0;
      tb_prescaler = 32'h0;
      tb_timer     = 32'h0;
    end
  endtask









  task test1;
    begin
      tc_ctr = tc_ctr + 1;
      tb_monitor = 1;

      $display("--- test1 started.");
      dump_dut_state();
      tb_prescaler = 32'h6;
      tb_timer     = 32'h9;
      #(CLK_PERIOD);
      tb_start = 1'h1;
      #(CLK_PERIOD);
      tb_start = 1'h0;
      wait_ready();
      #(CLK_PERIOD);
      tb_monitor = 0;
      $display("--- test1 completed.");
      $display("");
    end
  endtask







  initial
    begin : timer_core_test
      $display("--- Simulation of TIMER core started.");
      $display("");

      init_sim();
      reset_dut();

      test1();

      $display("");
      $display("--- Simulation of timer core completed.");
      $finish;
    end
endmodule