data/full_repos/permissive/460664642/ssd_tb.v
1: b'%Error: data/full_repos/permissive/460664642/ssd_tb.v:1: Cannot find include file: ssd.v\n`include "ssd.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/ssd.v\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/ssd.v.v\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/ssd.v.sv\n             ssd.v\n             ssd.v.v\n             ssd.v.sv\n             obj_dir/ssd.v\n             obj_dir/ssd.v.v\n             obj_dir/ssd.v.sv\n%Error: data/full_repos/permissive/460664642/ssd_tb.v:10: Unsupported or unknown PLI call: $monitor\n  $monitor("BCD=%d,Seg=%b",BCD,seg);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460664642/ssd_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5 BCD = i;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module ssd_tb();

reg[3:0] BCD;
wire[6:0] seg;

integer i;

initial begin
  $monitor("BCD=%d,Seg=%b",BCD,seg);
  BCD = 0;
  for (i = 1; i <= 10; i = i + 1)
  begin
    #5 BCD = i;
  end
end

BCDTo7Seg B_7seg(
BCD,
seg
);

endmodule
module ssd_tb();


reg[3:0] BCD;
wire[6:0] seg;

integer i;

initial begin
  $monitor("BCD=%d,Seg=%b",BCD,seg);
  BCD = 0;
  for (i = 1; i <= 10; i = i + 1)
  begin
    #5 BCD = i;
  end
end

BCDTo7Seg B_7seg(
BCD,
seg
);

endmodule