data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv
1: b'%Error: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:36: Unsupported: Static in this context\n    static int seed = $urandom + 0;\n    ^~~~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:36: Unsupported or unknown PLI call: $urandom\n    static int seed = $urandom + 0;\n                      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:76: Unsupported: Ignoring delay on this delayed statement.\n        #200 rRstb = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:84: Unsupported or unknown PLI call: $dist_normal\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n                  ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:84: Unsupported: Ignoring delay on this delayed statement.\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/pwm_tb.sv:94: Unsupported: Ignoring delay on this delayed statement.\n            #100us; \n            ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_tb ();




    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_LEVEL_WIDTH     = 8;

    



    

    static int seed = $urandom + 0;





    

    reg rRstb;
    reg rClk;
    

    reg [C_LEVEL_WIDTH - 1 : 0] rLevel;


    wire wOut;








    pwm #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_LEVEL_WIDTH(C_LEVEL_WIDTH)
    ) DUT (
        .rstb(rRstb), 
        .clk(rClk), 
        .level(rLevel), 
        .out(wOut)
    );



    initial begin
		$display ($time, " << Starting the Simulation >> ");
        rRstb = 1'b0;
		rClk = 1'b0;
        #200 rRstb = 1'b1;
        rLevel = 1'b0;
    end




    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end  
	


	always begin
		
        for (int i = 0; i <= C_LEVEL_WIDTH; i++) begin
            rLevel = 2**i - 1;
            #100us; 
		end
		

        $finish;
	end

endmodule
module pwm_tb ();





    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_LEVEL_WIDTH     = 8;

    



    

    static int seed = $urandom + 0;





    

    reg rRstb;
    reg rClk;
    

    reg [C_LEVEL_WIDTH - 1 : 0] rLevel;


    wire wOut;








    pwm #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_LEVEL_WIDTH(C_LEVEL_WIDTH)
    ) DUT (
        .rstb(rRstb), 
        .clk(rClk), 
        .level(rLevel), 
        .out(wOut)
    );



    initial begin
		$display ($time, " << Starting the Simulation >> ");
        rRstb = 1'b0;
		rClk = 1'b0;
        #200 rRstb = 1'b1;
        rLevel = 1'b0;
    end




    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end  
	


	always begin
		
        for (int i = 0; i <= C_LEVEL_WIDTH; i++) begin
            rLevel = 2**i - 1;
            #100us; 
		end
		

        $finish;
	end

endmodule