data/full_repos/permissive/458737381/src/verilog-parser/tests/task_calling.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/task_calling.v:5: Cannot find include file: mytask.v\n`include "mytask.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/mytask.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/mytask.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/mytask.v.sv\n             mytask.v\n             mytask.v.v\n             mytask.v.sv\n             obj_dir/mytask.v\n             obj_dir/mytask.v.v\n             obj_dir/mytask.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  task_calling (temp_a, temp_b, temp_c, temp_d);
input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
  	 
always @ (temp_a)
begin	
  convert (temp_a, temp_b);
end  

always @ (temp_c)
begin	
  convert (temp_c, temp_d);
end  
  	 
endmodule
module  task_calling (temp_a, temp_b, temp_c, temp_d);

input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
  	 
always @ (temp_a)
begin	
  convert (temp_a, temp_b);
end  

always @ (temp_c)
begin	
  convert (temp_c, temp_d);
end  
  	 
endmodule