data/full_repos/permissive/427221126/src/ConvLayer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ConvLayer.v:459: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ConvLayer\'\nmodule ConvLayer\n       ^~~~~~~~~\n                                                                           : ... Top module \'ConvCore_nC\'\nmodule ConvCore_nC\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:129: Operator ASSIGNDLY expects 41 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n      psum[0] <= mul[0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:140: Operator ADD expects 41 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n          psum[ii] <= mul[ii] + psum[ii-1];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:423: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g] ;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:425: Operator ADD expects 48 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g]  + psum[g-1];\n                                          ^\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:243: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.sv\n             ShiftRegSIPOnB\n             ShiftRegSIPOnB.v\n             ShiftRegSIPOnB.sv\n             obj_dir/ShiftRegSIPOnB\n             obj_dir/ShiftRegSIPOnB.v\n             obj_dir/ShiftRegSIPOnB.sv\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:255: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:290: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:623: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:639: Cannot find file containing module: \'FIFOsync\'\n  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:651: Cannot find file containing module: \'FIFOpi\'\n  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (\n  ^~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module ConvCore3x3 
  #(
    parameter INWIDTH = 16
  )
  (
    input clk,
    input reset, 
    input en,

    input signed [INWIDTH-1:0] h0,
    input signed [INWIDTH-1:0] h1,
    input signed [INWIDTH-1:0] h2,
    input signed [INWIDTH-1:0] h3,
    input signed [INWIDTH-1:0] h4,
    input signed [INWIDTH-1:0] h5,
    input signed [INWIDTH-1:0] h6,
    input signed [INWIDTH-1:0] h7,
    input signed [INWIDTH-1:0] h8,

    input signed [INWIDTH-1:0] x0,
    input signed [INWIDTH-1:0] x1,
    input signed [INWIDTH-1:0] x2,
    input signed [INWIDTH-1:0] x3,
    input signed [INWIDTH-1:0] x4,
    input signed [INWIDTH-1:0] x5,
    input signed [INWIDTH-1:0] x6,
    input signed [INWIDTH-1:0] x7,
    input signed [INWIDTH-1:0] x8,

    output signed [INWIDTH*2+8:0] y
  );
  reg signed [INWIDTH-1:0] h_ibuf[0:8];
  reg signed [INWIDTH-1:0] x_ibuf[0:8];
  genvar ii;

  reg signed [INWIDTH*2-1:0] mul[0:8];

  reg signed [INWIDTH*2+8:0] psum[0:8];

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      h_ibuf[0] <= 0; h_ibuf[1] <= 0; h_ibuf[2] <= 0;
      h_ibuf[3] <= 0; h_ibuf[4] <= 0; h_ibuf[5] <= 0;
      h_ibuf[6] <= 0; h_ibuf[7] <= 0; h_ibuf[8] <= 0;
      
      x_ibuf[0] <= 0; x_ibuf[1] <= 0; x_ibuf[2] <= 0;
      x_ibuf[3] <= 0; x_ibuf[4] <= 0; x_ibuf[5] <= 0;
      x_ibuf[6] <= 0; x_ibuf[7] <= 0; x_ibuf[8] <= 0;
    end
    else if (en) begin
      h_ibuf[0] <= h0; h_ibuf[1] <= h1; h_ibuf[2] <= h2;
      h_ibuf[3] <= h3; h_ibuf[4] <= h4; h_ibuf[5] <= h5;
      h_ibuf[6] <= h6; h_ibuf[7] <= h7; h_ibuf[8] <= h8;

      x_ibuf[0] <= x0; x_ibuf[1] <= x1; x_ibuf[2] <= x2;
      x_ibuf[3] <= x3; x_ibuf[4] <= x4; x_ibuf[5] <= x5;
      x_ibuf[6] <= x6; x_ibuf[7] <= x7; x_ibuf[8] <= x8;
    end
  end

  generate
    for (ii = 0; ii < 9; ii = ii + 1) begin : mult
      always @(posedge clk) begin
        if (reset == 1'b1) begin
          mul[ii] <= 0;
        end
        else if (en) begin
          mul[ii] <= x_ibuf[ii] * h_ibuf[ii];
        end
      end
    end
  endgenerate

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      psum[0] <= 0;
    end
    else if (en) begin
      psum[0] <= mul[0];
    end
  end
  
  generate
    for (ii = 1; ii < 9; ii = ii + 1) begin : partial_sum
      always @(posedge clk) begin
        if (reset == 1'b1) begin
          psum[ii] <= 0;
        end
        else if (en) begin
          psum[ii] <= mul[ii] + psum[ii-1];
        end
      end
    end
  endgenerate

  assign y = psum[8];
endmodule
module ConvCore3x3 
  #(
    parameter INWIDTH = 16
  )
  (
    input clk,
    input reset, 
    input en,

    input signed [INWIDTH-1:0] h0,
    input signed [INWIDTH-1:0] h1,
    input signed [INWIDTH-1:0] h2,
    input signed [INWIDTH-1:0] h3,
    input signed [INWIDTH-1:0] h4,
    input signed [INWIDTH-1:0] h5,
    input signed [INWIDTH-1:0] h6,
    input signed [INWIDTH-1:0] h7,
    input signed [INWIDTH-1:0] h8,

    input signed [INWIDTH-1:0] x0,
    input signed [INWIDTH-1:0] x1,
    input signed [INWIDTH-1:0] x2,
    input signed [INWIDTH-1:0] x3,
    input signed [INWIDTH-1:0] x4,
    input signed [INWIDTH-1:0] x5,
    input signed [INWIDTH-1:0] x6,
    input signed [INWIDTH-1:0] x7,
    input signed [INWIDTH-1:0] x8,

    output signed [INWIDTH*2+8:0] y
  );

  reg signed [INWIDTH-1:0] h_ibuf[0:8];
  reg signed [INWIDTH-1:0] x_ibuf[0:8];
  genvar ii;

  reg signed [INWIDTH*2-1:0] mul[0:8];

  reg signed [INWIDTH*2+8:0] psum[0:8];

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      h_ibuf[0] <= 0; h_ibuf[1] <= 0; h_ibuf[2] <= 0;
      h_ibuf[3] <= 0; h_ibuf[4] <= 0; h_ibuf[5] <= 0;
      h_ibuf[6] <= 0; h_ibuf[7] <= 0; h_ibuf[8] <= 0;
      
      x_ibuf[0] <= 0; x_ibuf[1] <= 0; x_ibuf[2] <= 0;
      x_ibuf[3] <= 0; x_ibuf[4] <= 0; x_ibuf[5] <= 0;
      x_ibuf[6] <= 0; x_ibuf[7] <= 0; x_ibuf[8] <= 0;
    end
    else if (en) begin
      h_ibuf[0] <= h0; h_ibuf[1] <= h1; h_ibuf[2] <= h2;
      h_ibuf[3] <= h3; h_ibuf[4] <= h4; h_ibuf[5] <= h5;
      h_ibuf[6] <= h6; h_ibuf[7] <= h7; h_ibuf[8] <= h8;

      x_ibuf[0] <= x0; x_ibuf[1] <= x1; x_ibuf[2] <= x2;
      x_ibuf[3] <= x3; x_ibuf[4] <= x4; x_ibuf[5] <= x5;
      x_ibuf[6] <= x6; x_ibuf[7] <= x7; x_ibuf[8] <= x8;
    end
  end

  generate
    for (ii = 0; ii < 9; ii = ii + 1) begin : mult
      always @(posedge clk) begin
        if (reset == 1'b1) begin
          mul[ii] <= 0;
        end
        else if (en) begin
          mul[ii] <= x_ibuf[ii] * h_ibuf[ii];
        end
      end
    end
  endgenerate

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      psum[0] <= 0;
    end
    else if (en) begin
      psum[0] <= mul[0];
    end
  end
  
  generate
    for (ii = 1; ii < 9; ii = ii + 1) begin : partial_sum
      always @(posedge clk) begin
        if (reset == 1'b1) begin
          psum[ii] <= 0;
        end
        else if (en) begin
          psum[ii] <= mul[ii] + psum[ii-1];
        end
      end
    end
  endgenerate

  assign y = psum[8];
endmodule