data/full_repos/permissive/469195529/sources/hdl/muxMain.v
data/verilator_xmls/331157db-f12d-49a3-b7c1-3af06b9a0c7a.xml
module muxMain(
    input [5:0] min1, min2, sec1, sec2,
    input sel,
    output reg[5:0] min_out, sec_out
    );
    
    always@(min1 or min2 or sec1 or sec2 or sel) begin
        if(sel) begin
            min_out <= min2;
            sec_out <= sec2;
        end else begin
            min_out <= min1;
            sec_out <= sec1;
        end
    end
endmodule
module muxMain(
    input [5:0] min1, min2, sec1, sec2,
    input sel,
    output reg[5:0] min_out, sec_out
    );

    
    always@(min1 or min2 or sec1 or sec2 or sel) begin
        if(sel) begin
            min_out <= min2;
            sec_out <= sec2;
        end else begin
            min_out <= min1;
            sec_out <= sec1;
        end
    end
endmodule