data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:49: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:50: Unsupported: Ignoring delay on this delayed statement.\n always #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:51: Unsupported: Ignoring delay on this delayed statement.\n always #10 next_pc = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #10 hit <= ~hit;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/IF_ID_Register_TEST.v:39: Cannot find file containing module: \'IF_ID_Register\'\n IF_ID_Register uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/IF_ID_Register\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/IF_ID_Register.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/IF_ID_Register.sv\n             IF_ID_Register\n             IF_ID_Register.v\n             IF_ID_Register.sv\n             obj_dir/IF_ID_Register\n             obj_dir/IF_ID_Register.v\n             obj_dir/IF_ID_Register.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IF_ID_Register_TEST;


	reg clock;
	reg [31:0] next_pc;
	reg [31:0] instruction;
	reg hit;


	wire [31:0] instruction_out;
	wire [31:0] next_pc_out;
	wire hit_out;


	IF_ID_Register uut (
		.clock(clock), 
		.next_pc(next_pc), 
		.instruction(instruction), 
		.hit(hit), 
		.instruction_out(instruction_out), 
		.next_pc_out(next_pc_out), 
		.hit_out(hit_out)
	);

	always #20 clock <= ~clock;
	always #10 instruction = $random;
	always #10 next_pc = $random;
	always #10 hit <= ~hit;
	
	initial begin

		clock = 0;
		next_pc = 0;
		instruction = 0;
		hit = 0;


		#100;
        


	end
      
endmodule
module IF_ID_Register_TEST;



	reg clock;
	reg [31:0] next_pc;
	reg [31:0] instruction;
	reg hit;


	wire [31:0] instruction_out;
	wire [31:0] next_pc_out;
	wire hit_out;


	IF_ID_Register uut (
		.clock(clock), 
		.next_pc(next_pc), 
		.instruction(instruction), 
		.hit(hit), 
		.instruction_out(instruction_out), 
		.next_pc_out(next_pc_out), 
		.hit_out(hit_out)
	);

	always #20 clock <= ~clock;
	always #10 instruction = $random;
	always #10 next_pc = $random;
	always #10 hit <= ~hit;
	
	initial begin

		clock = 0;
		next_pc = 0;
		instruction = 0;
		hit = 0;


		#100;
        


	end
      
endmodule