data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module.v
1: b"%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module.v:23: Cannot find file containing module: 'my_dff8'\n  my_dff8 m1 (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8,data/full_repos/permissive/500128826/my_dff8\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8,data/full_repos/permissive/500128826/my_dff8.v\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8,data/full_repos/permissive/500128826/my_dff8.sv\n             my_dff8\n             my_dff8.v\n             my_dff8.sv\n             obj_dir/my_dff8\n             obj_dir/my_dff8.v\n             obj_dir/my_dff8.sv\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module.v:28: Cannot find file containing module: 'my_dff8'\n  my_dff8 m2 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module.v:33: Cannot find file containing module: 'my_dff8'\n  my_dff8 m3 (\n  ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module (
    input wire clk,
    input wire [7:0] d,
    input wire [1:0] sel,
    output wire [7:0] q
);

  reg  [7:0] q_i;

  wire [7:0] q1;
  wire [7:0] q2;
  wire [7:0] q3;

  my_dff8 m1 (
      clk,
      d,
      q1
  );
  my_dff8 m2 (
      clk,
      q1,
      q2
  );
  my_dff8 m3 (
      clk,
      q2,
      q3
  );

  assign q = q_i;

  always @(*) begin
    case (sel)
      2'd1: q_i = q1;
      2'd2: q_i = q2;
      2'd3: q_i = q3;
      default: q_i = d;
    endcase
  end

endmodule
module top_module (
    input wire clk,
    input wire [7:0] d,
    input wire [1:0] sel,
    output wire [7:0] q
);


  reg  [7:0] q_i;

  wire [7:0] q1;
  wire [7:0] q2;
  wire [7:0] q3;

  my_dff8 m1 (
      clk,
      d,
      q1
  );
  my_dff8 m2 (
      clk,
      q1,
      q2
  );
  my_dff8 m3 (
      clk,
      q2,
      q3
  );

  assign q = q_i;

  always @(*) begin
    case (sel)
      2'd1: q_i = q1;
      2'd2: q_i = q2;
      2'd3: q_i = q3;
      default: q_i = d;
    endcase
  end

endmodule