data/full_repos/permissive/439087417/cntr.v
data/verilator_xmls/dce2d0cc-298a-431e-8fc1-798aef195d1c.xml
module cntr #(parameter rndw = 4)
(  input clk, clr, c_up,
	output reg [rndw-1:0] q
    );

always @(posedge clk) begin
	if(clr) q <= 0;
	if(c_up) q <= q + 1;
end
endmodule
module cntr #(parameter rndw = 4)
(  input clk, clr, c_up,
	output reg [rndw-1:0] q
    );


always @(posedge clk) begin
	if(clr) q <= 0;
	if(c_up) q <= q + 1;
end
endmodule