data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b101;   \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b111;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b010;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b011;   \n  ^\n%Error: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:7: Cannot find file containing module: \'adder_32\'\n adder_32 adder(.in_x (~in_multiplier),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bit_pair_recoder_32_tb;

	reg [31:0] multiplier;
	reg [2:0] bit_pair;
	wire [63:0] recode;
	
	parameter delay = 10;
	
	bit_pair_recoder_32 DUT(.in_multiplier (multiplier),
		.in_bit_pair (bit_pair),
		.out_recode (recode));
	
	initial begin
		multiplier = 32'hd; bit_pair = 3'b100;
		#(delay) bit_pair = 3'b101;
		#(delay) bit_pair = 3'b111;
		#(delay) bit_pair = 3'b010;
		#(delay) bit_pair = 3'b011;
	end

endmodule
module bit_pair_recoder_32_tb;


	reg [31:0] multiplier;
	reg [2:0] bit_pair;
	wire [63:0] recode;
	
	parameter delay = 10;
	
	bit_pair_recoder_32 DUT(.in_multiplier (multiplier),
		.in_bit_pair (bit_pair),
		.out_recode (recode));
	
	initial begin
		multiplier = 32'hd; bit_pair = 3'b100;
		#(delay) bit_pair = 3'b101;
		#(delay) bit_pair = 3'b111;
		#(delay) bit_pair = 3'b010;
		#(delay) bit_pair = 3'b011;
	end

endmodule