data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/IF.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/IF.v:60: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'mux4_1\'\nmodule mux4_1(input [31:0] ina, inb, inc, ind,\n       ^~~~~~\n                                                                                              : ... Top module \'IF\'\nmodule IF (input clk, reset, PCSrc, PC_write, \n       ^~\n%Error: Exiting due to 1 warning(s)\n'
module IF (input clk, reset, PCSrc, PC_write, 
           input [31:0] PC_Branch, 
           output [31:0] PC_IF, INSTRUCTION_IF);
    wire [31:0]res_adder, res_mux;
    adder add(4, PC_IF, res_adder);
    mux2_1 mux(res_adder, PC_Branch, PCSrc, res_mux);
    PC pc(clk, reset, PC_write, res_mux, PC_IF);
    instruction_memory instr(PC_IF[11:2], INSTRUCTION_IF);
endmodule
module IF (input clk, reset, PCSrc, PC_write, 
           input [31:0] PC_Branch, 
           output [31:0] PC_IF, INSTRUCTION_IF);

    wire [31:0]res_adder, res_mux;
    adder add(4, PC_IF, res_adder);
    mux2_1 mux(res_adder, PC_Branch, PCSrc, res_mux);
    PC pc(clk, reset, PC_write, res_mux, PC_IF);
    instruction_memory instr(PC_IF[11:2], INSTRUCTION_IF);
endmodule