data/full_repos/permissive/406635962/src/rtl/ifu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:27: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:30: Define or directive not defined: \'`PC_SIZE\'\n   input [`PC_SIZE-1:0] pc_rtvec,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:32: Define or directive not defined: \'`INSTR_SIZE\'\n  output [`INSTR_SIZE-1:0] ifu_o_ir, \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:33: Define or directive not defined: \'`PC_SIZE\'\n  output [`PC_SIZE-1:0] ifu_o_pc,    \n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:34: Define or directive not defined: \'`RFIDX_WIDTH\'\n  output [`RFIDX_WIDTH-1:0] ifu_o_rs1idx,\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:35: Define or directive not defined: \'`RFIDX_WIDTH\'\n  output [`RFIDX_WIDTH-1:0] ifu_o_rs2idx,\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:43: Define or directive not defined: \'`PC_SIZE\'\n  input   [`PC_SIZE-1:0] pipe_flush_add_op1,  \n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:44: Define or directive not defined: \'`PC_SIZE\'\n  input   [`PC_SIZE-1:0] pipe_flush_add_op2,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:48: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,  \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:52: Define or directive not defined: \'`ITCM_RAM_DW\'\n  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata, \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:56: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] rf2ifu_x1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:57: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] rf2ifu_rs1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:61: Define or directive not defined: \'`RFIDX_WIDTH\'\n  input  [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:73: Define or directive not defined: \'`PC_SIZE\'\n  wire [`PC_SIZE-1:0]   ifu_req_pc; \n        ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu.v:76: Define or directive not defined: \'`INSTR_SIZE\'\n  wire [`INSTR_SIZE-1:0] ifu_rsp_instr; \n        ^~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module ifu (
   input [`PC_SIZE-1:0] pc_rtvec,

  output [`INSTR_SIZE-1:0] ifu_o_ir,
  output [`PC_SIZE-1:0] ifu_o_pc,
  output [`RFIDX_WIDTH-1:0] ifu_o_rs1idx,
  output [`RFIDX_WIDTH-1:0] ifu_o_rs2idx,
  output ifu_o_prdt_taken,

  output ifu_o_valid,
  input  ifu_o_ready,

  output  pipe_flush_ack,
  input   pipe_flush_req,
  input   [`PC_SIZE-1:0] pipe_flush_add_op1,  
  input   [`PC_SIZE-1:0] pipe_flush_add_op2,

  output ifu2itcm_cmd_valid,
  input  ifu2itcm_cmd_ready,
  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,

  input  ifu2itcm_rsp_valid,
  output ifu2itcm_rsp_ready,
  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata, 

  input  oitf_empty,

  input  [`XLEN-1:0] rf2ifu_x1,
  input  [`XLEN-1:0] rf2ifu_rs1,

  input  dec2ifu_rden,
  input  dec2ifu_rs1en,
  input  [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,





  input  clk,
  input  rst_n
);

  wire ifu_req_valid; 
  wire ifu_req_ready; 
  wire [`PC_SIZE-1:0]   ifu_req_pc; 
  wire ifu_rsp_valid; 
  wire ifu_rsp_ready; 
  wire [`INSTR_SIZE-1:0] ifu_rsp_instr; 

  
  ifu_ifetch u_ifu_ifetch(
    .pc_rtvec      (pc_rtvec),  

    .ifu_req_valid (ifu_req_valid),
    .ifu_req_ready (ifu_req_ready),
    .ifu_req_pc    (ifu_req_pc   ),
    .ifu_rsp_valid (ifu_rsp_valid),
    .ifu_rsp_ready (ifu_rsp_ready),
    .ifu_rsp_instr (ifu_rsp_instr),
    .ifu_o_ir      (ifu_o_ir     ),
    .ifu_o_pc      (ifu_o_pc     ),
    .ifu_o_rs1idx  (ifu_o_rs1idx),
    .ifu_o_rs2idx  (ifu_o_rs2idx),
    .ifu_o_prdt_taken(ifu_o_prdt_taken),
    .ifu_o_valid   (ifu_o_valid  ),
    .ifu_o_ready   (ifu_o_ready  ),
    .pipe_flush_ack (pipe_flush_ack),
    .pipe_flush_req     (pipe_flush_req),
    .pipe_flush_add_op1 (pipe_flush_add_op1),     
    .pipe_flush_add_op2 (pipe_flush_add_op2), 

    .oitf_empty    (oitf_empty   ),
    .rf2ifu_x1     (rf2ifu_x1    ),
    .rf2ifu_rs1    (rf2ifu_rs1   ),
    .dec2ifu_rden  (dec2ifu_rden ),
    .dec2ifu_rs1en (dec2ifu_rs1en),
    .dec2ifu_rdidx (dec2ifu_rdidx),
    .clk           (clk),
    .rst_n         (rst_n) 
  );

  ifu_ifu2itcm u_ifu_ifu2itcm (
    .ifu_req_valid (ifu_req_valid),
    .ifu_req_ready (ifu_req_ready),
    .ifu_req_pc    (ifu_req_pc),

    .ifu_rsp_valid (ifu_rsp_valid),
    .ifu_rsp_ready (ifu_rsp_ready),
    .ifu_rsp_instr (ifu_rsp_instr),
    
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata)
  );
endmodule
module ifu (
   input [`PC_SIZE-1:0] pc_rtvec,

  output [`INSTR_SIZE-1:0] ifu_o_ir,
  output [`PC_SIZE-1:0] ifu_o_pc,
  output [`RFIDX_WIDTH-1:0] ifu_o_rs1idx,
  output [`RFIDX_WIDTH-1:0] ifu_o_rs2idx,
  output ifu_o_prdt_taken,

  output ifu_o_valid,
  input  ifu_o_ready,

  output  pipe_flush_ack,
  input   pipe_flush_req,
  input   [`PC_SIZE-1:0] pipe_flush_add_op1,  
  input   [`PC_SIZE-1:0] pipe_flush_add_op2,

  output ifu2itcm_cmd_valid,
  input  ifu2itcm_cmd_ready,
  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,

  input  ifu2itcm_rsp_valid,
  output ifu2itcm_rsp_ready,
  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata, 

  input  oitf_empty,

  input  [`XLEN-1:0] rf2ifu_x1,
  input  [`XLEN-1:0] rf2ifu_rs1,

  input  dec2ifu_rden,
  input  dec2ifu_rs1en,
  input  [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,





  input  clk,
  input  rst_n
);


  wire ifu_req_valid; 
  wire ifu_req_ready; 
  wire [`PC_SIZE-1:0]   ifu_req_pc; 
  wire ifu_rsp_valid; 
  wire ifu_rsp_ready; 
  wire [`INSTR_SIZE-1:0] ifu_rsp_instr; 

  
  ifu_ifetch u_ifu_ifetch(
    .pc_rtvec      (pc_rtvec),  

    .ifu_req_valid (ifu_req_valid),
    .ifu_req_ready (ifu_req_ready),
    .ifu_req_pc    (ifu_req_pc   ),
    .ifu_rsp_valid (ifu_rsp_valid),
    .ifu_rsp_ready (ifu_rsp_ready),
    .ifu_rsp_instr (ifu_rsp_instr),
    .ifu_o_ir      (ifu_o_ir     ),
    .ifu_o_pc      (ifu_o_pc     ),
    .ifu_o_rs1idx  (ifu_o_rs1idx),
    .ifu_o_rs2idx  (ifu_o_rs2idx),
    .ifu_o_prdt_taken(ifu_o_prdt_taken),
    .ifu_o_valid   (ifu_o_valid  ),
    .ifu_o_ready   (ifu_o_ready  ),
    .pipe_flush_ack (pipe_flush_ack),
    .pipe_flush_req     (pipe_flush_req),
    .pipe_flush_add_op1 (pipe_flush_add_op1),     
    .pipe_flush_add_op2 (pipe_flush_add_op2), 

    .oitf_empty    (oitf_empty   ),
    .rf2ifu_x1     (rf2ifu_x1    ),
    .rf2ifu_rs1    (rf2ifu_rs1   ),
    .dec2ifu_rden  (dec2ifu_rden ),
    .dec2ifu_rs1en (dec2ifu_rs1en),
    .dec2ifu_rdidx (dec2ifu_rdidx),
    .clk           (clk),
    .rst_n         (rst_n) 
  );

  ifu_ifu2itcm u_ifu_ifu2itcm (
    .ifu_req_valid (ifu_req_valid),
    .ifu_req_ready (ifu_req_ready),
    .ifu_req_pc    (ifu_req_pc),

    .ifu_rsp_valid (ifu_rsp_valid),
    .ifu_rsp_ready (ifu_rsp_ready),
    .ifu_rsp_instr (ifu_rsp_instr),
    
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata)
  );
endmodule