data/full_repos/permissive/52811404/spi/slave.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52811404/spi/slave.v:110: Unsupported: Ignoring delay on this delayed statement.\n    always #27 sck <= ~sck;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52811404/spi/slave.v:111: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/52811404/spi/slave.v:124: Unsupported: Ignoring delay on this delayed statement.\n    initial #10000 $finish;\n            ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_slave_tb (
);

    reg clk, sck, ss, mosi;
    initial clk = 1'b0;
    initial sck = 1'b0;
    initial ss = 1'b0;
    initial mosi = 1'b0;

    wire strobe;
    wire [7:0] data;

    spi_slave S (
        .clk(clk),
        .sck(sck),
        .ss(ss),
        .mosi(mosi),
        .data(data),
        .strobe(strobe)
    );

    always #27 sck <= ~sck;
    always #5 clk <= ~clk;

    always @ (posedge clk)
    begin
        if (strobe)
            $display(data);
    end

    always @ (posedge sck)
    begin
        mosi <= ~mosi;
    end

    initial #10000 $finish;

endmodule
module spi_slave_tb (
);


    reg clk, sck, ss, mosi;
    initial clk = 1'b0;
    initial sck = 1'b0;
    initial ss = 1'b0;
    initial mosi = 1'b0;

    wire strobe;
    wire [7:0] data;

    spi_slave S (
        .clk(clk),
        .sck(sck),
        .ss(ss),
        .mosi(mosi),
        .data(data),
        .strobe(strobe)
    );

    always #27 sck <= ~sck;
    always #5 clk <= ~clk;

    always @ (posedge clk)
    begin
        if (strobe)
            $display(data);
    end

    always @ (posedge sck)
    begin
        mosi <= ~mosi;
    end

    initial #10000 $finish;

endmodule