data/full_repos/permissive/449071180/tb_bi_shift_register.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:45: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:47: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:49: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:52: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:55: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:57: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:60: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:64: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:66: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:68: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:71: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:74: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:76: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:79: Unsupported: Ignoring delay on this delayed statement.\n#5; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:83: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:85: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:87: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:89: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:96: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:98: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:103: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:105: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:111: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bi_shift_register.v:113: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_bi_shift_register.v:12: Cannot find file containing module: \'bi_shift_register\'\nbi_shift_register port_map(\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bi_shift_register\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bi_shift_register.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bi_shift_register.sv\n             bi_shift_register\n             bi_shift_register.v\n             bi_shift_register.sv\n             obj_dir/bi_shift_register\n             obj_dir/bi_shift_register.v\n             obj_dir/bi_shift_register.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_bi_shift_register.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'num_test\' generates 32 bits.\n                                                                              : ... In instance tb_bi_shift_register\nload_in_test=num_test;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_bi_shift_register.v:62: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'num_test\' generates 32 bits.\n                                                                              : ... In instance tb_bi_shift_register\nload_in_test=num_test;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_bi_shift_register.v:81: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'num_test\' generates 32 bits.\n                                                                              : ... In instance tb_bi_shift_register\nload_in_test=num_test;\n            ^\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_bi_shift_register();
reg clk_test,shift_right_test,shift_left_test,reset_test,set_test;
reg [7:0] load_ups_test,load_downs_test,load_in_test,load_ups_values_test,load_downs_values_test;
wire [7:0] parallel_out_test;

integer num_test;
integer count_right = 0;
integer count_left = 0;
integer count_up = 0;
integer count_down = 0;

bi_shift_register port_map(

.clk(clk_test),
.shift_right(shift_right_test),
.shift_left(shift_left_test),
.reset(reset_test),
.set(set_test),
.load_ups(load_ups_test),
.load_downs(load_downs_test),
.load_in(load_in_test),
.load_ups_values(load_ups_values_test),
.load_downs_values(load_downs_values_test),
.parallel_out(parallel_out_test)

);

initial begin
clk_test = 0;
shift_right_test = 0;
shift_left_test = 0;
reset_test = 0;
set_test = 0;
load_ups_test = 0;
load_downs_test = 0;
load_in_test = 0;
load_ups_values_test = 8'b0;
load_downs_values_test = 8'b0;
end

always begin 
for(num_test = 1; num_test < 256; num_test = num_test + 1) begin
load_in_test=num_test;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;

shift_right_test = 1;
#5;
for(count_right = 0; count_right < 8; count_right = count_right + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
end
shift_right_test =  0;
#5;

load_in_test=num_test;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;

shift_left_test = 1;
#5;
for(count_left = 0; count_left < 8; count_left = count_left + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
end
shift_left_test = 0;
#5; 

load_in_test=num_test;
set_test = 1;
#5;
set_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;


load_ups_values_test = 8'b11111111;
load_ups_test = 8'b10000000;
for(count_up = 0; count_up < 8; count_up = count_up + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
load_ups_test = load_ups_test >> 1;
end

reset_test = 1;
#5;
reset_test = 0;
#5;

load_downs_values_test = 8'b11111111;
load_downs_test = 8'b10000000;
for(count_down = 0; count_down < 8; count_down = count_down + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
load_downs_test = load_downs_test >> 1;
end

end

end


endmodule
module tb_bi_shift_register();

reg clk_test,shift_right_test,shift_left_test,reset_test,set_test;
reg [7:0] load_ups_test,load_downs_test,load_in_test,load_ups_values_test,load_downs_values_test;
wire [7:0] parallel_out_test;

integer num_test;
integer count_right = 0;
integer count_left = 0;
integer count_up = 0;
integer count_down = 0;

bi_shift_register port_map(

.clk(clk_test),
.shift_right(shift_right_test),
.shift_left(shift_left_test),
.reset(reset_test),
.set(set_test),
.load_ups(load_ups_test),
.load_downs(load_downs_test),
.load_in(load_in_test),
.load_ups_values(load_ups_values_test),
.load_downs_values(load_downs_values_test),
.parallel_out(parallel_out_test)

);

initial begin
clk_test = 0;
shift_right_test = 0;
shift_left_test = 0;
reset_test = 0;
set_test = 0;
load_ups_test = 0;
load_downs_test = 0;
load_in_test = 0;
load_ups_values_test = 8'b0;
load_downs_values_test = 8'b0;
end

always begin 
for(num_test = 1; num_test < 256; num_test = num_test + 1) begin
load_in_test=num_test;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;

shift_right_test = 1;
#5;
for(count_right = 0; count_right < 8; count_right = count_right + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
end
shift_right_test =  0;
#5;

load_in_test=num_test;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;

shift_left_test = 1;
#5;
for(count_left = 0; count_left < 8; count_left = count_left + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
end
shift_left_test = 0;
#5; 

load_in_test=num_test;
set_test = 1;
#5;
set_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;


load_ups_values_test = 8'b11111111;
load_ups_test = 8'b10000000;
for(count_up = 0; count_up < 8; count_up = count_up + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
load_ups_test = load_ups_test >> 1;
end

reset_test = 1;
#5;
reset_test = 0;
#5;

load_downs_values_test = 8'b11111111;
load_downs_test = 8'b10000000;
for(count_down = 0; count_down < 8; count_down = count_down + 1) begin
clk_test = 0;
#5;
clk_test = 1;
#5;
load_downs_test = load_downs_test >> 1;
end

end

end


endmodule