data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v:71: syntax error, unexpected \'@\'\n  @(negedge tb_clk);  \n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v:77: syntax error, unexpected \'@\'\n  @(posedge tb_clk);  \n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OUT_REG_tb.v:92: Unsupported or unknown PLI call: $monitor\n$monitor($time, " tb_clk=%b, tb_reset=%b, tb_set=%b, Data in=%d, Data out=%d", \n^~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OUT_REG_tb();



parameter tb_data_width=16;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_reset;
reg tb_set;
reg [tb_data_width-1:0] tb_data_in;


wire [tb_data_width-1:0] tb_data_out;



OUT_REG #(.REG_DATA_WIDTH(tb_data_width)) Out_Reg(

.OUT_REG_Clk(tb_clk),
.OUT_REG_Reset(tb_reset),
.OUT_REG_Set(tb_set),
.OUT_REG_Input_Data(tb_data_in),
.OUT_REG_Output_Data(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	$display($time, " << Starting the Simulation >>");
	tb_reset<=1'b0; 
	tb_set<=1'b0;
	tb_data_in<=0;
	
	for (i=0; i<10;i=i+1)begin
		@(negedge tb_clk);
		tb_reset<=1'b1; 
		tb_set<=1'b1;
		tb_data_in<=tb_data_in+1;
		verify_output(tb_data_out,tb_data_in);
		
		@(posedge tb_clk);
		tb_set<=1'b0;
		verify_output(tb_data_out,tb_data_in-1);
	end
	
	$display($time," << Test passed >> ");
	$stop;

end


initial 

begin

$monitor($time, " tb_clk=%b, tb_reset=%b, tb_set=%b, Data in=%d, Data out=%d", 
tb_clk,tb_reset,tb_set,tb_data_in,tb_data_out);

end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask




endmodule
module OUT_REG_tb();




parameter tb_data_width=16;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_reset;
reg tb_set;
reg [tb_data_width-1:0] tb_data_in;


wire [tb_data_width-1:0] tb_data_out;



OUT_REG #(.REG_DATA_WIDTH(tb_data_width)) Out_Reg(

.OUT_REG_Clk(tb_clk),
.OUT_REG_Reset(tb_reset),
.OUT_REG_Set(tb_set),
.OUT_REG_Input_Data(tb_data_in),
.OUT_REG_Output_Data(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	$display($time, " << Starting the Simulation >>");
	tb_reset<=1'b0; 
	tb_set<=1'b0;
	tb_data_in<=0;
	
	for (i=0; i<10;i=i+1)begin
		@(negedge tb_clk);
		tb_reset<=1'b1; 
		tb_set<=1'b1;
		tb_data_in<=tb_data_in+1;
		verify_output(tb_data_out,tb_data_in);
		
		@(posedge tb_clk);
		tb_set<=1'b0;
		verify_output(tb_data_out,tb_data_in-1);
	end
	
	$display($time," << Test passed >> ");
	$stop;

end


initial 

begin

$monitor($time, " tb_clk=%b, tb_reset=%b, tb_set=%b, Data in=%d, Data out=%d", 
tb_clk,tb_reset,tb_set,tb_data_in,tb_data_out);

end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask




endmodule