data/full_repos/permissive/42414927/fetch-decode/decode.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:73: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                            : ... In instance decode\n     src1 = rs_wire;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:74: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                            : ... In instance decode\n     src2 = rt_wire;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:89: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                            : ... In instance decode\n     src1 = rt_wire;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:106: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:122: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:138: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:139: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:153: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:154: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:168: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:169: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:184: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:200: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:215: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:216: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:231: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:232: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:247: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:248: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:262: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:263: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:277: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:278: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:292: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:293: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:307: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:308: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:322: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:323: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:337: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:338: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:352: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:353: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:367: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:368: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:382: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:383: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:397: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:398: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:412: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:413: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:426: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:427: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rt_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:429: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'fn_wire\' generates 6 bits.\n                                                                             : ... In instance decode\n    funct = fn_wire;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:444: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src1 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:460: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n    src2 = rs_wire;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:510: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:511: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:525: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:526: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:540: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:556: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:570: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:585: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:600: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:615: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:630: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:645: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:676: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:692: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:707: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:722: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:723: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:737: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:738: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:752: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:753: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:767: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src1 = rs_wire;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/42414927/fetch-decode/decode.v:768: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rt_wire\' generates 5 bits.\n                                                                             : ... In instance decode\n   src2 = rt_wire;\n        ^\n%Error: Exiting due to 69 warning(s)\n'
module decode (clk, insn, pc, src1, src2, dst, imm, instbits, funct, addr, b_ctrl, dmem_func, wb_func, j);


	input	      clk;
	input  [31:0] insn;
	input  [31:0] pc;


	output [5:0]  src1;
	output [5:0]  src2;
	output [4:0]  dst;
	output [15:0] imm;
	output [4:0]  funct;
	output [5:0]  instbits;
	output [25:0] addr;
	output        b_ctrl;
	output [2:0]  dmem_func;
	output [2:0]  wb_func;
	output [1:0]  j;


	reg  [31:0]   pc_reg = 0;
	reg  [5:0]    instbits = 0;
	reg  [5:0]    src1 = 0;
	reg  [5:0]    src2 = 0;
	reg  [4:0]    dst = 0;
	reg  [15:0]   imm = 0;
	reg  [4:0]    funct = 0;
	reg  [25:0]   addr = 0;
	reg  		  b_ctrl = 0;
	reg  [2:0]    dmem_func = 0;
	reg  [2:0]    wb_func = 0;
	reg	 [1:0]    j = 0;


	wire [5:0]    inst_wire;
	wire [4:0]    rs_wire;
	wire [4:0]    rt_wire;
	wire [4:0]    rd_wire;	
	wire [4:0]    sa_wire;
	wire [5:0]    fn_wire;
	wire [15:0]   imm_wire;
	wire [25:0]   idx_wire;


	assign inst_wire = insn[31:26];
	assign rs_wire = insn[25:21];
	assign rt_wire = insn[20:16];
	assign rd_wire = insn[15:11];
	assign sa_wire = insn[10:6];		
	assign fn_wire = insn[5:0];
	assign imm_wire = insn[15:0];
	assign idx_wire = insn[25:0];


	always @(insn)
	begin

		pc_reg = pc;


		instbits[5:0] = inst_wire;

		if (inst_wire[5:0] == 'b000000)
		begin

			if (fn_wire == 'b000000)
			begin
				if (rt_wire == 'b00000 && rd_wire == 'b00000 && sa_wire == 'b00000)
				begin

					src1 = rs_wire;
					src2 = rt_wire;
					dst = rd_wire;
					funct = 'b00000;
					imm[15:5] = 0;
					imm[4:0] = sa_wire;
					addr = 0;
					b_ctrl = 0;
					dmem_func = 3'b000;
					wb_func = 3'b000;
					j = 0;
					$display("%h\tNOP", pc);
				end
				else
				begin

					src1 = rt_wire;
					src2 = 0;
					dst = rd_wire;
					funct = 'b00000;
					imm[15:5] = 0;
					imm[4:0] = sa_wire;
					addr = 0;
					b_ctrl = 1;
					dmem_func = 3'b000;
					wb_func = 3'b011;
					j = 0;
					$display("%h\tSLL\tR%d, R%d, %d", pc, rd_wire, rt_wire, sa_wire);
				end
			end
			else if (fn_wire == 'b000010)
			begin

				src1 = rt_wire;
				src2 = 0;
				dst = rd_wire;
				funct = 'b00001;
				imm[15:5] = 0;
				imm[4:0] = sa_wire;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRL\tR%d, R%d, %d", pc, rd_wire, rt_wire, sa_wire);
			end
			else if (fn_wire == 'b000011)
			begin			

				src1 = rt_wire;
				src2 = 0;
				dst = rd_wire;
				funct = 'b00010;
				imm[15:5] = 0;
				imm[4:0] = sa_wire;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRA\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b000100)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLLV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b000110)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRLV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b000111)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRAV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b001000)
			begin

				src1 = 0;
				src2 = rs_wire;
				dst = 0;
				funct = 'b00000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 2;
				
				$display("%h\tJR\tR%d", pc, rs_wire);
			end
			else if (fn_wire == 'b001001)
			begin

				src1 = 32;
				src2 = rs_wire;
				dst = rd_wire;
				funct = 'b01001;
				imm = 'b0000000000000100;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 2;
				
				$display("%h\tJALR\tR%d, R%d", pc, rd_wire, rs_wire);
			end
			else if (fn_wire == 'b010000)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00011;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				
				$display("%h\tMFHI\tR%d", pc, rd_wire);
			end
			else if (fn_wire == 'b010010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00100;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				
				$display("%h\tMFLO\tR%d", pc, rd_wire);
			end
			else if (fn_wire == 'b011010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00110;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;
				$display("%h\tDIV\tR%d, R%d", pc, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b011011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00111;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tDIVU\tR%d, R%d", pc, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100000)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tADD\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100001)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tADDU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSUB\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSUBU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100100)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01100;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tAND\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100101)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01101;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100110)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01110;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tXOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100111)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01111;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tNOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b101010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b10000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLT\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b101011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b10001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLTU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else
			begin
				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = fn_wire;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;
				$display("%h\tUNDEF %b", pc, insn);
			end
		end
		
		else if (inst_wire[5:0] == 'b000001)
		begin			
			if (rt_wire == 'b00000)
			begin
				src1 = rs_wire;
				src2 = 0;
				dst = 0;
				funct = 'b10100;
				imm = imm_wire;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;

				$display("%h\tBLTZ R%d, %d", pc, rs_wire, $signed(imm_wire));
			end
			else if (rt_wire == 'b00001)
			begin
				src1 = 0;
				src2 = rs_wire;
				dst = 0;
				funct = 'b10110;
				imm = imm_wire;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;

				$display("%h\tBGEZ R%d, %d", pc, rs_wire, $signed(imm_wire));
			end
			else
			begin
				$display("%h\tUNDEF %b", pc, insn);
			end
		end
		
		else if (inst_wire[5:0] == 'b000010)
		begin
			src1 = 0;
			src2 = 0;
			dst = 0;
			funct = 'b01001;
			imm = 0;
			addr = idx_wire;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 1;

			$display("%h\tJ\t%h", pc, idx_wire);
		end
		else if (inst_wire[5:0] == 'b000011)
		begin
			src1 = 32;
			src2 = 0;
			dst = 31;
			funct = 'b01001;
			imm = 'b0000000000000100;
			addr = idx_wire;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 1;

			$display("%h\tJAL\t%h", pc, idx_wire);
		end
		else if (inst_wire[5:0] == 'b000100)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b10011;			
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBEQ\tR%d, R%d, %d", pc, rs_wire, rt_wire, $signed(imm_wire));
		end		
		else if (inst_wire[5:0] == 'b000101)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b10101;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBNE\tR%d, R%d, %d", pc, rs_wire, rt_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b000110)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = 0;
			funct = 'b10110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBLEZ\tR%d, %d", pc, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b000111)
		begin
			src1 = 0;
			src2 = rs_wire;
			dst = 0;
			funct = 'b10110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBGTZ\tR%d, %d", pc, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001001)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tADDIU\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001010)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tSLTI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001011)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10001;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tSLTIU\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001101)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01101;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tORI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001100)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01100;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tANDI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001110)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tXORI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001111)
		begin
			src1 = 0;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10010;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tLUI\tR%d, %d", pc, rt_wire, $signed(imm_wire));
		end
		
		else if (inst_wire[5:0] == 'b100000)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b101;
			wb_func = 3'b101;
			j = 0;

			
			$display("%h\tLB\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b100011)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b001;
			wb_func = 3'b001;
			j = 0;

			$display("%h\tLW\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b100100)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b101;
			wb_func = 3'b001;
			j = 0;

			$display("%h\tLBU\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101000)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b111;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tSB\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101001)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b011;
			wb_func = 3'b100;
			j = 0;

			$display("%h\tSH\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101011)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b011;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tSW\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b011100)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = rd_wire;
			funct = 'b00101;
			imm = 0;
			addr = 0;
			b_ctrl = 0;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tMUL\tR%d, R%d, R%d)", pc, rd_wire, rs_wire, rt_wire);
		end
		
		else
		begin
			$display("%h\tUNDEF %b", pc, insn);			
		end
	end

endmodule
module decode (clk, insn, pc, src1, src2, dst, imm, instbits, funct, addr, b_ctrl, dmem_func, wb_func, j);



	input	      clk;
	input  [31:0] insn;
	input  [31:0] pc;


	output [5:0]  src1;
	output [5:0]  src2;
	output [4:0]  dst;
	output [15:0] imm;
	output [4:0]  funct;
	output [5:0]  instbits;
	output [25:0] addr;
	output        b_ctrl;
	output [2:0]  dmem_func;
	output [2:0]  wb_func;
	output [1:0]  j;


	reg  [31:0]   pc_reg = 0;
	reg  [5:0]    instbits = 0;
	reg  [5:0]    src1 = 0;
	reg  [5:0]    src2 = 0;
	reg  [4:0]    dst = 0;
	reg  [15:0]   imm = 0;
	reg  [4:0]    funct = 0;
	reg  [25:0]   addr = 0;
	reg  		  b_ctrl = 0;
	reg  [2:0]    dmem_func = 0;
	reg  [2:0]    wb_func = 0;
	reg	 [1:0]    j = 0;


	wire [5:0]    inst_wire;
	wire [4:0]    rs_wire;
	wire [4:0]    rt_wire;
	wire [4:0]    rd_wire;	
	wire [4:0]    sa_wire;
	wire [5:0]    fn_wire;
	wire [15:0]   imm_wire;
	wire [25:0]   idx_wire;


	assign inst_wire = insn[31:26];
	assign rs_wire = insn[25:21];
	assign rt_wire = insn[20:16];
	assign rd_wire = insn[15:11];
	assign sa_wire = insn[10:6];		
	assign fn_wire = insn[5:0];
	assign imm_wire = insn[15:0];
	assign idx_wire = insn[25:0];


	always @(insn)
	begin

		pc_reg = pc;


		instbits[5:0] = inst_wire;

		if (inst_wire[5:0] == 'b000000)
		begin

			if (fn_wire == 'b000000)
			begin
				if (rt_wire == 'b00000 && rd_wire == 'b00000 && sa_wire == 'b00000)
				begin

					src1 = rs_wire;
					src2 = rt_wire;
					dst = rd_wire;
					funct = 'b00000;
					imm[15:5] = 0;
					imm[4:0] = sa_wire;
					addr = 0;
					b_ctrl = 0;
					dmem_func = 3'b000;
					wb_func = 3'b000;
					j = 0;
					$display("%h\tNOP", pc);
				end
				else
				begin

					src1 = rt_wire;
					src2 = 0;
					dst = rd_wire;
					funct = 'b00000;
					imm[15:5] = 0;
					imm[4:0] = sa_wire;
					addr = 0;
					b_ctrl = 1;
					dmem_func = 3'b000;
					wb_func = 3'b011;
					j = 0;
					$display("%h\tSLL\tR%d, R%d, %d", pc, rd_wire, rt_wire, sa_wire);
				end
			end
			else if (fn_wire == 'b000010)
			begin

				src1 = rt_wire;
				src2 = 0;
				dst = rd_wire;
				funct = 'b00001;
				imm[15:5] = 0;
				imm[4:0] = sa_wire;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRL\tR%d, R%d, %d", pc, rd_wire, rt_wire, sa_wire);
			end
			else if (fn_wire == 'b000011)
			begin			

				src1 = rt_wire;
				src2 = 0;
				dst = rd_wire;
				funct = 'b00010;
				imm[15:5] = 0;
				imm[4:0] = sa_wire;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRA\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b000100)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLLV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b000110)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRLV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b000111)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSRAV\tR%d, R%d, R%d", pc, rd_wire, rt_wire, rs_wire);
			end
			else if (fn_wire == 'b001000)
			begin

				src1 = 0;
				src2 = rs_wire;
				dst = 0;
				funct = 'b00000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 2;
				
				$display("%h\tJR\tR%d", pc, rs_wire);
			end
			else if (fn_wire == 'b001001)
			begin

				src1 = 32;
				src2 = rs_wire;
				dst = rd_wire;
				funct = 'b01001;
				imm = 'b0000000000000100;
				addr = 0;
				b_ctrl = 1;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 2;
				
				$display("%h\tJALR\tR%d, R%d", pc, rd_wire, rs_wire);
			end
			else if (fn_wire == 'b010000)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00011;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				
				$display("%h\tMFHI\tR%d", pc, rd_wire);
			end
			else if (fn_wire == 'b010010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00100;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				
				$display("%h\tMFLO\tR%d", pc, rd_wire);
			end
			else if (fn_wire == 'b011010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00110;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;
				$display("%h\tDIV\tR%d, R%d", pc, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b011011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b00111;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tDIVU\tR%d, R%d", pc, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100000)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tADD\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100001)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tADDU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSUB\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01010;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSUBU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100100)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01100;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tAND\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100101)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01101;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100110)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01110;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tXOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b100111)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b01111;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tNOR\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b101010)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b10000;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLT\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else if (fn_wire == 'b101011)
			begin

				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = 'b10001;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b011;
				j = 0;
				$display("%h\tSLTU\tR%d, R%d, R%d", pc, rd_wire, rs_wire, rt_wire);
			end
			else
			begin
				src1 = rs_wire;
				src2 = rt_wire;
				dst = rd_wire;
				funct = fn_wire;
				imm = 0;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;
				$display("%h\tUNDEF %b", pc, insn);
			end
		end
		
		else if (inst_wire[5:0] == 'b000001)
		begin			
			if (rt_wire == 'b00000)
			begin
				src1 = rs_wire;
				src2 = 0;
				dst = 0;
				funct = 'b10100;
				imm = imm_wire;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;

				$display("%h\tBLTZ R%d, %d", pc, rs_wire, $signed(imm_wire));
			end
			else if (rt_wire == 'b00001)
			begin
				src1 = 0;
				src2 = rs_wire;
				dst = 0;
				funct = 'b10110;
				imm = imm_wire;
				addr = 0;
				b_ctrl = 0;
				dmem_func = 3'b000;
				wb_func = 3'b000;
				j = 0;

				$display("%h\tBGEZ R%d, %d", pc, rs_wire, $signed(imm_wire));
			end
			else
			begin
				$display("%h\tUNDEF %b", pc, insn);
			end
		end
		
		else if (inst_wire[5:0] == 'b000010)
		begin
			src1 = 0;
			src2 = 0;
			dst = 0;
			funct = 'b01001;
			imm = 0;
			addr = idx_wire;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 1;

			$display("%h\tJ\t%h", pc, idx_wire);
		end
		else if (inst_wire[5:0] == 'b000011)
		begin
			src1 = 32;
			src2 = 0;
			dst = 31;
			funct = 'b01001;
			imm = 'b0000000000000100;
			addr = idx_wire;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 1;

			$display("%h\tJAL\t%h", pc, idx_wire);
		end
		else if (inst_wire[5:0] == 'b000100)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b10011;			
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBEQ\tR%d, R%d, %d", pc, rs_wire, rt_wire, $signed(imm_wire));
		end		
		else if (inst_wire[5:0] == 'b000101)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b10101;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBNE\tR%d, R%d, %d", pc, rs_wire, rt_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b000110)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = 0;
			funct = 'b10110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBLEZ\tR%d, %d", pc, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b000111)
		begin
			src1 = 0;
			src2 = rs_wire;
			dst = 0;
			funct = 'b10110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 0;
			dmem_func = 3'b000;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tBGTZ\tR%d, %d", pc, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001001)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tADDIU\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001010)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tSLTI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001011)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10001;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tSLTIU\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001101)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01101;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tORI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001100)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01100;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tANDI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001110)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01110;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tXORI\tR%d, R%d, %d", pc, rt_wire, rs_wire, $signed(imm_wire));
		end
		else if (inst_wire[5:0] == 'b001111)
		begin
			src1 = 0;
			src2 = 0;
			dst = rt_wire;
			funct = 'b10010;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b000;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tLUI\tR%d, %d", pc, rt_wire, $signed(imm_wire));
		end
		
		else if (inst_wire[5:0] == 'b100000)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b101;
			wb_func = 3'b101;
			j = 0;

			
			$display("%h\tLB\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b100011)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b001;
			wb_func = 3'b001;
			j = 0;

			$display("%h\tLW\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b100100)
		begin
			src1 = rs_wire;
			src2 = 0;
			dst = rt_wire;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b101;
			wb_func = 3'b001;
			j = 0;

			$display("%h\tLBU\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101000)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b111;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tSB\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101001)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b011;
			wb_func = 3'b100;
			j = 0;

			$display("%h\tSH\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b101011)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = 0;
			funct = 'b01000;
			imm = imm_wire;
			addr = 0;
			b_ctrl = 1;
			dmem_func = 3'b011;
			wb_func = 3'b000;
			j = 0;

			$display("%h\tSW\tR%d, %d(R%d)", pc, rt_wire, $signed(imm_wire), rs_wire);
		end
		else if (inst_wire[5:0] == 'b011100)
		begin
			src1 = rs_wire;
			src2 = rt_wire;
			dst = rd_wire;
			funct = 'b00101;
			imm = 0;
			addr = 0;
			b_ctrl = 0;
			wb_func = 3'b011;
			j = 0;

			$display("%h\tMUL\tR%d, R%d, R%d)", pc, rd_wire, rs_wire, rt_wire);
		end
		
		else
		begin
			$display("%h\tUNDEF %b", pc, insn);			
		end
	end

endmodule