data/full_repos/permissive/426864978/lab1/task4/mod10.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/426864978/lab1/task4/mod10.sv:5: Operator LTE expects 5 bits on the RHS, but RHS\'s CONST \'4\'h9\' generates 4 bits.\n                                                                          : ... In instance mod10\n    assign lsd = (in <= 4\'d9) ? in[3:0] : ones;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mod10(input [4:0] in, output [3:0] lsd);
    integer i;
    reg [3:0] ones;

    assign lsd = (in <= 4'd9) ? in[3:0] : ones;





    always @(in) begin
        ones = 4'd0;
        for (i = 4; i >= 0; i = i - 1) begin
            if (ones >= 4'd5)
                ones = ones + 4'd3;
            ones = ones << 1;
            ones[0] = in[i];
        end
    end
endmodule
module mod10(input [4:0] in, output [3:0] lsd);

    integer i;
    reg [3:0] ones;

    assign lsd = (in <= 4'd9) ? in[3:0] : ones;





    always @(in) begin
        ones = 4'd0;
        for (i = 4; i >= 0; i = i - 1) begin
            if (ones >= 4'd5)
                ones = ones + 4'd3;
            ones = ones << 1;
            ones[0] = in[i];
        end
    end
endmodule