data/full_repos/permissive/459277146/and_er.v
data/verilator_xmls/440c2fcf-8846-4236-a9f2-f4b759e90fae.xml
module and_er #(parameter DWIDTH = 8) (din1,din2,dout_and_er);
input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_and_er;

assign dout_and_er = din1 & din2;

endmodule
module and_er #(parameter DWIDTH = 8) (din1,din2,dout_and_er);

input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_and_er;

assign dout_and_er = din1 & din2;

endmodule