data/full_repos/permissive/48250786/keymem.v
data/verilator_xmls/31223b3b-d426-4098-993e-50c1dc3d912a.xml
module keymem(
	 output reg [127:0] dout,
	 input [3:0] add,
	 input clock,
	 input en
    );
	 
	 reg [127:0] memkey [0:15];
	 
	 initial begin
		$readmemh("roundkeys.table", memkey, 0, 15);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout <= memkey[add];
		end
	 end
	
endmodule
module keymem(
	 output reg [127:0] dout,
	 input [3:0] add,
	 input clock,
	 input en
    );

	 
	 reg [127:0] memkey [0:15];
	 
	 initial begin
		$readmemh("roundkeys.table", memkey, 0, 15);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout <= memkey[add];
		end
	 end
	
endmodule