data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:516: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                         : ... In instance lab7_2self.u7.M4\n  cnt  =4\'d0;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:27: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer1\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b100 )? timer1 :\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:29: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer3\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b010 )? timer3 :4\'b0;\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module 	control(clk, reset, enable, nightcomes, timer3, timer2,	timer1, timer0,
				greenredman_work, NS_lights, EW_lights);
input	clk, reset, enable, nightcomes;

output	[2:0]NS_lights, EW_lights;


parameter 	GREEN_LIGHT = 2'b00,
			YELLOW_LIGHT= 2'b01,
			RED_LIGHT   = 2'b10,
			NIGHT		= 2'b11;



parameter 	GREEN_COUNT = 6'h22,
			YELLOW_COUNT= 6'h05,
			RED_COUNT  	= 6'h25,
			NIGHT_COUNT	= 6'h06;

reg		[2:0]NS_lights, EW_lights, next_NS_lights, next_EW_lights;
reg		[1:0]traffic_state, next_state;
reg		timer_clr, EW_side, next_timer_clr, next_EW_side;
reg		timer_clr2,next_timer_clr2;

output	[3:0]timer0,timer2;
output	[1:0]timer1,timer3;
wire	[3:0]timer0,timer2;
wire	[1:0]timer1,timer3;

reg		[3:0]timer0reg,timer2reg;
reg		[1:0]timer1reg,timer3reg;


assign 	timer0 = timer0reg;
assign	timer1 = timer1reg;
assign 	timer2 = timer2reg;
assign	timer3 = timer3reg;

reg		[1:0]greenredman_work_reg, next_greenredman_work;

output	wire [1:0]greenredman_work;

assign	greenredman_work=greenredman_work_reg;


always @(posedge clk or posedge reset)
begin
  if (reset) begin
	traffic_state <= #1 GREEN_LIGHT;
    timer_clr     <= #1 1'b1;
	timer_clr2    <= #1 1'b1;
    EW_side       <= #1 1'b1;
    EW_lights     <= #1 3'b100;
    NS_lights     <= #1 3'b001;
	greenredman_work_reg<= #1 2'b00;
	end
  else

	begin
	  traffic_state <= #1 next_state;
	  timer_clr     <= #1 next_timer_clr;
	  timer_clr2    <= #1 next_timer_clr2;
	  EW_side       <= #1 next_EW_side;
	  EW_lights     <= #1 next_EW_lights;
	  NS_lights     <= #1 next_NS_lights;

	  greenredman_work_reg	<= #1 next_greenredman_work;
	end
end

always @(traffic_state  or EW_side  or EW_lights or NS_lights  or nightcomes
			or timer_clr or timer_clr2
			or timer1reg or timer0reg or timer3reg or timer2reg
			or greenredman_work_reg)
begin
    next_state     = traffic_state;
    next_timer_clr = timer_clr;
	next_timer_clr2= timer_clr2;
    next_EW_side   = EW_side;
    next_EW_lights = EW_lights;
    next_NS_lights = NS_lights;
	next_greenredman_work	= greenredman_work_reg;
    case (traffic_state)
      GREEN_LIGHT : begin
				next_timer_clr = 1'b0;

				next_greenredman_work=2'b00;
				if (EW_side==1'b1) begin
					next_EW_lights = 3'b100;
					next_NS_lights = 3'b001;
					end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b100;
					
					end
				if ({timer1reg,timer0reg}==6'h10) begin

					next_state     = YELLOW_LIGHT;
					end
				if (nightcomes==1'b1) begin
					next_timer_clr = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
					end				
		    end

      YELLOW_LIGHT : begin
				

				
				if (EW_side==1'b1) begin
					next_EW_lights = 3'b010;
					next_NS_lights = 3'b001;
					end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b010;
					end
				if ({timer1reg,timer0reg}==6'h04) begin

					next_state     = RED_LIGHT;
					end
				if (nightcomes==1'b1) begin
					next_timer_clr2 = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
					end	
		    end

      RED_LIGHT : begin

				
				next_greenredman_work=2'b01;
				if(EW_side==1'b1) begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b001;
				end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b001;
				end
				if({timer1reg,timer0reg}==6'h01) begin
					next_timer_clr = 1'b1;
					next_state     = GREEN_LIGHT;
					next_EW_side   = ~EW_side;
					
				end
				if (nightcomes==1'b1) begin
					next_timer_clr = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
				end
					
		    end
	  NIGHT:  begin
				next_timer_clr2 = 1'b0;
				next_EW_lights = 3'b010;
				next_NS_lights = 3'b010;
				if({timer3reg,timer2reg}==6'h01) begin
					next_timer_clr2	= 1'b1;
					if(nightcomes==1'b0)
					next_state		= GREEN_LIGHT;
					else
					next_state		=NIGHT;
				end
			end
      default	: begin
		    next_state     = GREEN_LIGHT;
			next_timer_clr = 1'b0;
		    next_EW_side   = 1'b1;
		    next_EW_lights = 3'b100;
		    next_NS_lights = 3'b001;
			next_greenredman_work=2'b00;
			
		  end
    endcase
end

always @(posedge clk or posedge reset)
begin
	if(reset) 
		begin
		timer1reg<=2'd3;
		timer0reg<=4'd1;
		end
	else 	

			if (timer_clr==1'b1)begin
				timer1reg<=2'd2;
				timer0reg<=4'd0;
				end
			else
				if({timer1reg,timer0reg}>6'd0)
					if(timer0reg>4'd0)
							timer0reg<=timer0reg-4'd1;				
					else begin
						timer0reg<=4'd9;
						timer1reg<=timer1reg-2'd1;
						end
				else begin
					timer1reg<=2'd2;
					timer0reg<=4'd0;
					end
end

always @(posedge clk or posedge reset)
begin
	if(reset) 
		begin
		timer3reg<=2'd3;
		timer2reg<=4'd1;
		end
	else 	

			if (timer_clr2==1'b1)begin
				timer3reg<=2'd0;
				timer2reg<=4'd6;
				end
			else
				if({timer3reg,timer2reg}>6'd0)
					if(timer2reg>4'd0)
							timer2reg<=timer2reg-4'd1;				
					else begin
						timer2reg<=4'd9;
						timer3reg<=timer3reg-2'd1;
						end
				else begin
					timer3reg<=2'd0;
					timer2reg<=4'd6;
					end
end
endmodule
module 	control(clk, reset, enable, nightcomes, timer3, timer2,	timer1, timer0,
				greenredman_work, NS_lights, EW_lights);

input	clk, reset, enable, nightcomes;

output	[2:0]NS_lights, EW_lights;


parameter 	GREEN_LIGHT = 2'b00,
			YELLOW_LIGHT= 2'b01,
			RED_LIGHT   = 2'b10,
			NIGHT		= 2'b11;



parameter 	GREEN_COUNT = 6'h22,
			YELLOW_COUNT= 6'h05,
			RED_COUNT  	= 6'h25,
			NIGHT_COUNT	= 6'h06;

reg		[2:0]NS_lights, EW_lights, next_NS_lights, next_EW_lights;
reg		[1:0]traffic_state, next_state;
reg		timer_clr, EW_side, next_timer_clr, next_EW_side;
reg		timer_clr2,next_timer_clr2;

output	[3:0]timer0,timer2;
output	[1:0]timer1,timer3;
wire	[3:0]timer0,timer2;
wire	[1:0]timer1,timer3;

reg		[3:0]timer0reg,timer2reg;
reg		[1:0]timer1reg,timer3reg;


assign 	timer0 = timer0reg;
assign	timer1 = timer1reg;
assign 	timer2 = timer2reg;
assign	timer3 = timer3reg;

reg		[1:0]greenredman_work_reg, next_greenredman_work;

output	wire [1:0]greenredman_work;

assign	greenredman_work=greenredman_work_reg;


always @(posedge clk or posedge reset)
begin
  if (reset) begin
	traffic_state <= #1 GREEN_LIGHT;
    timer_clr     <= #1 1'b1;
	timer_clr2    <= #1 1'b1;
    EW_side       <= #1 1'b1;
    EW_lights     <= #1 3'b100;
    NS_lights     <= #1 3'b001;
	greenredman_work_reg<= #1 2'b00;
	end
  else

	begin
	  traffic_state <= #1 next_state;
	  timer_clr     <= #1 next_timer_clr;
	  timer_clr2    <= #1 next_timer_clr2;
	  EW_side       <= #1 next_EW_side;
	  EW_lights     <= #1 next_EW_lights;
	  NS_lights     <= #1 next_NS_lights;

	  greenredman_work_reg	<= #1 next_greenredman_work;
	end
end

always @(traffic_state  or EW_side  or EW_lights or NS_lights  or nightcomes
			or timer_clr or timer_clr2
			or timer1reg or timer0reg or timer3reg or timer2reg
			or greenredman_work_reg)
begin
    next_state     = traffic_state;
    next_timer_clr = timer_clr;
	next_timer_clr2= timer_clr2;
    next_EW_side   = EW_side;
    next_EW_lights = EW_lights;
    next_NS_lights = NS_lights;
	next_greenredman_work	= greenredman_work_reg;
    case (traffic_state)
      GREEN_LIGHT : begin
				next_timer_clr = 1'b0;

				next_greenredman_work=2'b00;
				if (EW_side==1'b1) begin
					next_EW_lights = 3'b100;
					next_NS_lights = 3'b001;
					end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b100;
					
					end
				if ({timer1reg,timer0reg}==6'h10) begin

					next_state     = YELLOW_LIGHT;
					end
				if (nightcomes==1'b1) begin
					next_timer_clr = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
					end				
		    end

      YELLOW_LIGHT : begin
				

				
				if (EW_side==1'b1) begin
					next_EW_lights = 3'b010;
					next_NS_lights = 3'b001;
					end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b010;
					end
				if ({timer1reg,timer0reg}==6'h04) begin

					next_state     = RED_LIGHT;
					end
				if (nightcomes==1'b1) begin
					next_timer_clr2 = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
					end	
		    end

      RED_LIGHT : begin

				
				next_greenredman_work=2'b01;
				if(EW_side==1'b1) begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b001;
				end
				else begin
					next_EW_lights = 3'b001;
					next_NS_lights = 3'b001;
				end
				if({timer1reg,timer0reg}==6'h01) begin
					next_timer_clr = 1'b1;
					next_state     = GREEN_LIGHT;
					next_EW_side   = ~EW_side;
					
				end
				if (nightcomes==1'b1) begin
					next_timer_clr = 1'b1;
					next_state     = NIGHT;
					next_greenredman_work=2'b10;
				end
					
		    end
	  NIGHT:  begin
				next_timer_clr2 = 1'b0;
				next_EW_lights = 3'b010;
				next_NS_lights = 3'b010;
				if({timer3reg,timer2reg}==6'h01) begin
					next_timer_clr2	= 1'b1;
					if(nightcomes==1'b0)
					next_state		= GREEN_LIGHT;
					else
					next_state		=NIGHT;
				end
			end
      default	: begin
		    next_state     = GREEN_LIGHT;
			next_timer_clr = 1'b0;
		    next_EW_side   = 1'b1;
		    next_EW_lights = 3'b100;
		    next_NS_lights = 3'b001;
			next_greenredman_work=2'b00;
			
		  end
    endcase
end

always @(posedge clk or posedge reset)
begin
	if(reset) 
		begin
		timer1reg<=2'd3;
		timer0reg<=4'd1;
		end
	else 	

			if (timer_clr==1'b1)begin
				timer1reg<=2'd2;
				timer0reg<=4'd0;
				end
			else
				if({timer1reg,timer0reg}>6'd0)
					if(timer0reg>4'd0)
							timer0reg<=timer0reg-4'd1;				
					else begin
						timer0reg<=4'd9;
						timer1reg<=timer1reg-2'd1;
						end
				else begin
					timer1reg<=2'd2;
					timer0reg<=4'd0;
					end
end

always @(posedge clk or posedge reset)
begin
	if(reset) 
		begin
		timer3reg<=2'd3;
		timer2reg<=4'd1;
		end
	else 	

			if (timer_clr2==1'b1)begin
				timer3reg<=2'd0;
				timer2reg<=4'd6;
				end
			else
				if({timer3reg,timer2reg}>6'd0)
					if(timer2reg>4'd0)
							timer2reg<=timer2reg-4'd1;				
					else begin
						timer2reg<=4'd9;
						timer3reg<=timer3reg-2'd1;
						end
				else begin
					timer3reg<=2'd0;
					timer2reg<=4'd6;
					end
end
endmodule