data/full_repos/permissive/530250155/verilog/rtl/site/wb_slave.v
1: b'%Error: data/full_repos/permissive/530250155/verilog/rtl/site/wb_slave.v:22: Cannot find include file: ../toysram.vh\n`include "../toysram.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.v\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.sv\n             ../toysram.vh\n             ../toysram.vh.v\n             ../toysram.vh.sv\n             obj_dir/../toysram.vh\n             obj_dir/../toysram.vh.v\n             obj_dir/../toysram.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module wb_slave #(
   parameter BASE_ADDR = 'h30000000,
   parameter BASE_MASK = 'hF0000000
) (
`ifdef USE_POWER_PINS
   inout                vccd1,
   inout                vssd1,
`endif
   input                clk,
   input                rst,
   input                wbs_stb_i,
   input                wbs_cyc_i,
   input                wbs_we_i,
   input  [3:0]         wbs_sel_i,
   input  [31:0]        wbs_dat_i,
   input  [31:0]        wbs_adr_i,
   output               wbs_ack_o,
   output [31:0]        wbs_dat_o,
   output               cmd_val,
   output [31:0]        cmd_adr,
   output               cmd_we,
   output [3:0]         cmd_sel,
   output [31:0]        cmd_dat,
   input                rd_ack,
   input  [31:0]        rd_dat

);

   reg                  cmd_val_q;
   wire                 cmd_val_d;
   reg    [31:0]        cmd_adr_q;
   wire   [31:0]        cmd_adr_d;
   reg                  cmd_we_q;
   wire                 cmd_we_d;
   reg    [3:0]         cmd_sel_q;
   wire   [3:0]         cmd_sel_d;
   reg    [31:0]        cmd_dat_q;
   wire   [31:0]        cmd_dat_d;
   reg                  rd_ack_q;
   wire                 rd_ack_d;
   reg    [31:0]        rd_dat_q;
   wire   [31:0]        rd_dat_d;

   wire                 stall;
   wire                 base_match;
   wire                 ack;


   always @(posedge clk) begin
      if (rst) begin
         cmd_val_q <= 1'b0;
         cmd_adr_q <= 31'h0;
         cmd_we_q <= 1'b0;
         cmd_sel_q <= 4'b0;
         cmd_dat_q <= 32'h0;
         rd_ack_q <= 1'b0;
         rd_dat_q <= 32'h0;
      end else begin
         cmd_val_q <= cmd_val_d;
         cmd_adr_q <= cmd_adr_d;
         cmd_we_q <= cmd_we_d;
         cmd_sel_q <= cmd_sel_d;
         cmd_dat_q <= cmd_dat_d;
         rd_ack_q <= rd_ack_d;
         rd_dat_q <= rd_dat_d;
      end
   end



   assign stall = 'b0;
   assign base_match = wbs_cyc_i & ((wbs_adr_i & BASE_MASK) == BASE_ADDR);




   assign cmd_val_d = base_match & wbs_stb_i & ~stall & ~ack;
   assign cmd_adr_d = {4'b0, wbs_adr_i[27:0]};
   assign cmd_we_d = wbs_we_i;
   assign cmd_sel_d = wbs_sel_i;
   assign cmd_dat_d = wbs_dat_i;
   assign ack = rd_ack_q | (cmd_val_q & cmd_we_q);
   assign wbs_ack_o = ack;
   assign wbs_dat_o = rd_dat_q;



   assign cmd_val = cmd_val_q;
   assign cmd_adr = cmd_adr_q;
   assign cmd_we = cmd_we_q;
   assign cmd_sel = cmd_sel_q;
   assign cmd_dat = cmd_dat_q;


   assign rd_ack_d = rd_ack;
   assign rd_dat_d = rd_dat;

endmodule
module wb_slave #(
   parameter BASE_ADDR = 'h30000000,
   parameter BASE_MASK = 'hF0000000
) (
`ifdef USE_POWER_PINS
   inout                vccd1,
   inout                vssd1,
`endif
   input                clk,
   input                rst,
   input                wbs_stb_i,
   input                wbs_cyc_i,
   input                wbs_we_i,
   input  [3:0]         wbs_sel_i,
   input  [31:0]        wbs_dat_i,
   input  [31:0]        wbs_adr_i,
   output               wbs_ack_o,
   output [31:0]        wbs_dat_o,
   output               cmd_val,
   output [31:0]        cmd_adr,
   output               cmd_we,
   output [3:0]         cmd_sel,
   output [31:0]        cmd_dat,
   input                rd_ack,
   input  [31:0]        rd_dat

);


   reg                  cmd_val_q;
   wire                 cmd_val_d;
   reg    [31:0]        cmd_adr_q;
   wire   [31:0]        cmd_adr_d;
   reg                  cmd_we_q;
   wire                 cmd_we_d;
   reg    [3:0]         cmd_sel_q;
   wire   [3:0]         cmd_sel_d;
   reg    [31:0]        cmd_dat_q;
   wire   [31:0]        cmd_dat_d;
   reg                  rd_ack_q;
   wire                 rd_ack_d;
   reg    [31:0]        rd_dat_q;
   wire   [31:0]        rd_dat_d;

   wire                 stall;
   wire                 base_match;
   wire                 ack;


   always @(posedge clk) begin
      if (rst) begin
         cmd_val_q <= 1'b0;
         cmd_adr_q <= 31'h0;
         cmd_we_q <= 1'b0;
         cmd_sel_q <= 4'b0;
         cmd_dat_q <= 32'h0;
         rd_ack_q <= 1'b0;
         rd_dat_q <= 32'h0;
      end else begin
         cmd_val_q <= cmd_val_d;
         cmd_adr_q <= cmd_adr_d;
         cmd_we_q <= cmd_we_d;
         cmd_sel_q <= cmd_sel_d;
         cmd_dat_q <= cmd_dat_d;
         rd_ack_q <= rd_ack_d;
         rd_dat_q <= rd_dat_d;
      end
   end



   assign stall = 'b0;
   assign base_match = wbs_cyc_i & ((wbs_adr_i & BASE_MASK) == BASE_ADDR);




   assign cmd_val_d = base_match & wbs_stb_i & ~stall & ~ack;
   assign cmd_adr_d = {4'b0, wbs_adr_i[27:0]};
   assign cmd_we_d = wbs_we_i;
   assign cmd_sel_d = wbs_sel_i;
   assign cmd_dat_d = wbs_dat_i;
   assign ack = rd_ack_q | (cmd_val_q & cmd_we_q);
   assign wbs_ack_o = ack;
   assign wbs_dat_o = rd_dat_q;



   assign cmd_val = cmd_val_q;
   assign cmd_adr = cmd_adr_q;
   assign cmd_we = cmd_we_q;
   assign cmd_sel = cmd_sel_q;
   assign cmd_dat = cmd_dat_q;


   assign rd_ack_d = rd_ack;
   assign rd_dat_d = rd_dat;

endmodule