data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v
1: b"%Error: data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v:10: syntax error, unexpected '(', expecting IDENTIFIER\n        and_dlo(Z1, CP, A1, B1);\n                ^~\n%Error: data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v:42: syntax error, unexpected '(', expecting IDENTIFIER\n        and_dlo(Z1, CP, A1, B1);\n                ^~\n%Error: data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v:74: syntax error, unexpected '(', expecting IDENTIFIER\n        xor_dlo(Z1, CP, A1, B1);\n                ^~\n%Error: data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v:106: syntax error, unexpected '(', expecting IDENTIFIER\n        xor_dlo(Z1, CP, A1, B1);\n                ^~\n%Error: data/full_repos/permissive/514437299/library/liberate/dlo/vlog/hgo_library_dlo.v:137: syntax error, unexpected '(', expecting IDENTIFIER\n        xor_dlo(Z1, CP, A1, B1);\n                ^~\n%Error: Exiting due to 5 error(s)\n"
module XOR_DLO_D1 (Z1, Z2, A1, A2, B1, B2, CP);
	output Z1;
	output Z2;
	input A1, B1, CP;
	input A2, B2;

        xor_dlo(Z1, CP, A1, B1);
        xnor_dlo (Z2, CP, A2, B2);

	specify
		if ((~B1 & CP))
			(A1 => Z1) = 0;
		if ((~A1 & CP))
			(B1 => Z1) = 0;
		if ((A1 & ~B1))
			(CP => Z1) = 0;
		if ((~A1 & B1))
			(CP => Z1) = 0;
		if ((B2 & CP))
			(A2 => Z2) = 0;
		if ((A2 & CP))
			(B2 => Z2) = 0;
		if ((A2 & B2))
			(CP => Z2) = 0;
		if ((~A2 & ~B2))
			(CP => Z2) = 0;
	endspecify
endmodule
module XOR_DLO_D1 (Z1, Z2, A1, A2, B1, B2, CP);

	output Z1;
	output Z2;
	input A1, B1, CP;
	input A2, B2;

        xor_dlo(Z1, CP, A1, B1);
        xnor_dlo (Z2, CP, A2, B2);

	specify
		if ((~B1 & CP))
			(A1 => Z1) = 0;
		if ((~A1 & CP))
			(B1 => Z1) = 0;
		if ((A1 & ~B1))
			(CP => Z1) = 0;
		if ((~A1 & B1))
			(CP => Z1) = 0;
		if ((B2 & CP))
			(A2 => Z2) = 0;
		if ((A2 & CP))
			(B2 => Z2) = 0;
		if ((A2 & B2))
			(CP => Z2) = 0;
		if ((~A2 & ~B2))
			(CP => Z2) = 0;
	endspecify
endmodule