data/full_repos/permissive/449071180/clock_register.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449071180/clock_register.v:42: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'count\' generates 7 bits.\n                                                                        : ... In instance clock_register\n  if(count == 1000010)begin\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clock_register(reset,clk_main,clk_move,clk_head,clk_shift_register,clk_serial);

input reset,clk_main;

output reg clk_move,clk_head,clk_shift_register,clk_serial;

reg[6:0] count;

always@(posedge clk_main,posedge reset) begin

	if(reset == 1) begin 
		count = 7'b0;
		clk_move = 0;
		clk_head = 0;
		clk_shift_register = 0;
		clk_serial = 0;
	end else begin
		if(count == 7'b0) begin
		clk_move = 1;
		clk_head = 0;
		clk_shift_register = 0;
		clk_serial = 0;
		end else begin
			if(count == 7'b1) begin
			clk_head = 1;
			clk_move = 0;
			clk_shift_register = 0;
		   clk_serial = 0;
			end else begin
				if(count == 7'b10) begin
				clk_shift_register = 1;
				clk_move = 0;
		      clk_head = 0;
				clk_serial = 0;
				end else begin
				clk_serial = ~clk_serial;
				end
			end
		end
		
		if(count == 1000010)begin
		count = 7'b0;
		end else begin
		count = count + 7'b1;
		end

	end

end



endmodule
module clock_register(reset,clk_main,clk_move,clk_head,clk_shift_register,clk_serial);


input reset,clk_main;

output reg clk_move,clk_head,clk_shift_register,clk_serial;

reg[6:0] count;

always@(posedge clk_main,posedge reset) begin

	if(reset == 1) begin 
		count = 7'b0;
		clk_move = 0;
		clk_head = 0;
		clk_shift_register = 0;
		clk_serial = 0;
	end else begin
		if(count == 7'b0) begin
		clk_move = 1;
		clk_head = 0;
		clk_shift_register = 0;
		clk_serial = 0;
		end else begin
			if(count == 7'b1) begin
			clk_head = 1;
			clk_move = 0;
			clk_shift_register = 0;
		   clk_serial = 0;
			end else begin
				if(count == 7'b10) begin
				clk_shift_register = 1;
				clk_move = 0;
		      clk_head = 0;
				clk_serial = 0;
				end else begin
				clk_serial = ~clk_serial;
				end
			end
		end
		
		if(count == 1000010)begin
		count = 7'b0;
		end else begin
		count = count + 7'b1;
		end

	end

end



endmodule