data/full_repos/permissive/461069000/timer/src/timer_register.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:52: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire ctrl_register_selected = (address == CTRL_REGISTER_ADDR);\n                                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:53: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire status_register_selected = (address == STATUS_REGISTER_ADDR);\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:54: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire cmp_1_register_selected = (address == CMP_1_REGISTER_ADDR);\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:55: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire cmp_0_register_selected = (address == CMP_0_REGISTER_ADDR);\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:56: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire count_register_selected = (address == COUNT_REGISTER_ADDR);\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:57: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire count_min_selected = (address == COUNT_MIN_REGISTER_ADDR);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:58: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'address\' generates 4 bits.\n                                                                                  : ... In instance timer_register\n    wire count_max_selected = (address == COUNT_MAX_REGISTER_ADDR);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:116: Operator SUB expects 32 or 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                   : ... In instance timer_register\n        COUNTER_BIT_WIDTH-2\'d0\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/461069000/timer/src/timer_register.v:116: Unsized numbers/parameters not allowed in concatenations.\n                                                                                         : ... In instance timer_register\n        COUNTER_BIT_WIDTH-2\'d0\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/461069000/timer/src/timer_register.v:115: Unsized numbers/parameters not allowed in replications.\n                                                                                         : ... In instance timer_register\n        cmp_0_f,\n               ^\n%Warning-WIDTH: data/full_repos/permissive/461069000/timer/src/timer_register.v:188: Operator CASE expects 6 bits on the Case expression, but Case expression\'s VARREF \'address\' generates 4 bits.\n                                                                                   : ... In instance timer_register\n        case(address)\n        ^~~~\n%Error: Exiting due to 11 warning(s)\n'
module timer_register
#(
    parameter COUNTER_BIT_WIDTH = 8
)(
    input clk,
    input rst,
    input enable,
    input write_enable,
    input [COUNTER_BIT_WIDTH-1:0] write_data,
    output [COUNTER_BIT_WIDTH-1:0] read_data,
    input [3:0] address,

    output reg clock_selector,
    output reg cmp_0_int_en,
    output reg cmp_1_int_en,
    output reg count_mode,
    output reg start,
    input cmp_1_f,
    input cmp_0_f,
    output reg [COUNTER_BIT_WIDTH-6:0] prescaler,
    input wire [COUNTER_BIT_WIDTH-1:0] count,
    output reg  [COUNTER_BIT_WIDTH-1:0] count_max,
    output reg  [COUNTER_BIT_WIDTH-1:0] count_min,
    output reg[COUNTER_BIT_WIDTH-1:0] cmp_1_value,
    output reg[COUNTER_BIT_WIDTH-1:0] cmp_0_value
    
);
    localparam  CTRL_REGISTER_ADDR = 6'h0;
    localparam  STATUS_REGISTER_ADDR = 6'h1;
    localparam  COUNT_REGISTER_ADDR = 6'h2;
    localparam  CMP_1_REGISTER_ADDR = 6'h3;
    localparam  CMP_0_REGISTER_ADDR = 6'h4;
    localparam  COUNT_MIN_REGISTER_ADDR = 6'h5;
    localparam  COUNT_MAX_REGISTER_ADDR = 6'h6;

    localparam  CTRL_REGISTER_RST = 8'd0;
    localparam  STATUS_REGISTER_RST = 8'd0;
    localparam  CMP_1_REGISTER_RST = 8'd0;
    localparam  CMP_0_REGISTER_RST = 8'd0;
    localparam  COUNT_REGISTER_RST = 8'h0;
    localparam  COUNT_MIN_REGISTER_RST = 8'h0;
    localparam  COUNT_MAX_REGISTER_RST = 8'hFF;




    
    reg  [COUNTER_BIT_WIDTH-1:0] read_data_out = 0;


    wire ctrl_register_selected = (address == CTRL_REGISTER_ADDR);
    wire status_register_selected = (address == STATUS_REGISTER_ADDR);
    wire cmp_1_register_selected = (address == CMP_1_REGISTER_ADDR);
    wire cmp_0_register_selected = (address == CMP_0_REGISTER_ADDR);
    wire count_register_selected = (address == COUNT_REGISTER_ADDR);
    wire count_min_selected = (address == COUNT_MIN_REGISTER_ADDR);
    wire count_max_selected = (address == COUNT_MAX_REGISTER_ADDR);



    wire read_enabled = !write_enable & enable; 
    wire write_enabled = write_enable & enable;




    wire [COUNTER_BIT_WIDTH-1:0] ctrl_reg = {
        cmp_1_int_en,
        cmp_0_int_en,
        clock_selector,
        count_mode,
        start,
        prescaler
    };





    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
        begin
            cmp_1_int_en = CTRL_REGISTER_RST[7];
            cmp_0_int_en = CTRL_REGISTER_RST[6];
            clock_selector = CTRL_REGISTER_RST[5];
            count_mode = CTRL_REGISTER_RST[4];
            start = CTRL_REGISTER_RST[3];
            prescaler = CTRL_REGISTER_RST[2:0];  
        end
        else
        begin 
            if(ctrl_register_selected & write_enabled)  
            begin
                cmp_1_int_en = write_data[7];
                cmp_0_int_en = write_data[6];
                clock_selector = write_data[5];
                count_mode = write_data[4];
                start = write_data[3];
                prescaler = write_data[2:0];  
            end
        end
    end


    wire clear_cmp_1_flag = status_register_selected & cmp_1_int_en & write_enabled & write_data[7];
    wire clear_cmp_0_flag = status_register_selected & cmp_0_int_en & write_enabled & write_data[6];

    reg cmp_1_flag_register = 0;
    reg cmp_0_flag_register = 0;

    wire [COUNTER_BIT_WIDTH-1:0] status_reg = {
        cmp_1_f,
        cmp_0_f,
        COUNTER_BIT_WIDTH-2'd0
    };

    always @(posedge clk, negedge rst, cmp_0_f) begin
        if(!rst)
        begin
            cmp_0_flag_register = 0;
        end
        else
        begin
            cmp_0_flag_register <= clear_cmp_0_flag ? 0 : cmp_0_flag_register |  cmp_0_f;
        end

    end

    always @(posedge clk, negedge rst, cmp_1_f) begin
        if(!rst)
        begin
            cmp_1_flag_register = 0;
        end
        else
        begin
            cmp_1_flag_register <= clear_cmp_1_flag ? 0 : cmp_1_flag_register |  cmp_1_f;
        end

    end


    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            cmp_0_value = CMP_0_REGISTER_RST;
        else 
            if(cmp_0_register_selected & write_enabled)  
                cmp_0_value = write_data;

    end

    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            cmp_1_value = CMP_1_REGISTER_RST;
        else   
            if(cmp_1_register_selected & write_enabled)  
                cmp_1_value = write_data;

    end

    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            count_min = COUNT_MIN_REGISTER_RST;
        else   
            if(count_min_selected & write_enabled)
                count_min = write_data;

    end


    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            count_max = COUNT_MAX_REGISTER_RST;
        else   
            if(count_max_selected & write_enabled)
                count_max = write_data;

    end



    always @(*) begin
        case(address)
            CTRL_REGISTER_ADDR: read_data_out = ctrl_reg;
            STATUS_REGISTER_ADDR: read_data_out = status_reg;
            CMP_1_REGISTER_ADDR: read_data_out = cmp_1_value;
            CMP_0_REGISTER_ADDR: read_data_out = cmp_0_value;
            COUNT_REGISTER_ADDR: read_data_out = count;
            COUNT_MIN_REGISTER_ADDR: read_data_out = count_min;
            COUNT_MAX_REGISTER_ADDR: read_data_out = count_max;
            default: read_data_out = 0;
        endcase
    end

    assign read_data = read_data_out & {COUNTER_BIT_WIDTH{read_enabled}};

endmodule
module timer_register
#(
    parameter COUNTER_BIT_WIDTH = 8
)(
    input clk,
    input rst,
    input enable,
    input write_enable,
    input [COUNTER_BIT_WIDTH-1:0] write_data,
    output [COUNTER_BIT_WIDTH-1:0] read_data,
    input [3:0] address,

    output reg clock_selector,
    output reg cmp_0_int_en,
    output reg cmp_1_int_en,
    output reg count_mode,
    output reg start,
    input cmp_1_f,
    input cmp_0_f,
    output reg [COUNTER_BIT_WIDTH-6:0] prescaler,
    input wire [COUNTER_BIT_WIDTH-1:0] count,
    output reg  [COUNTER_BIT_WIDTH-1:0] count_max,
    output reg  [COUNTER_BIT_WIDTH-1:0] count_min,
    output reg[COUNTER_BIT_WIDTH-1:0] cmp_1_value,
    output reg[COUNTER_BIT_WIDTH-1:0] cmp_0_value
    
);

    localparam  CTRL_REGISTER_ADDR = 6'h0;
    localparam  STATUS_REGISTER_ADDR = 6'h1;
    localparam  COUNT_REGISTER_ADDR = 6'h2;
    localparam  CMP_1_REGISTER_ADDR = 6'h3;
    localparam  CMP_0_REGISTER_ADDR = 6'h4;
    localparam  COUNT_MIN_REGISTER_ADDR = 6'h5;
    localparam  COUNT_MAX_REGISTER_ADDR = 6'h6;

    localparam  CTRL_REGISTER_RST = 8'd0;
    localparam  STATUS_REGISTER_RST = 8'd0;
    localparam  CMP_1_REGISTER_RST = 8'd0;
    localparam  CMP_0_REGISTER_RST = 8'd0;
    localparam  COUNT_REGISTER_RST = 8'h0;
    localparam  COUNT_MIN_REGISTER_RST = 8'h0;
    localparam  COUNT_MAX_REGISTER_RST = 8'hFF;




    
    reg  [COUNTER_BIT_WIDTH-1:0] read_data_out = 0;


    wire ctrl_register_selected = (address == CTRL_REGISTER_ADDR);
    wire status_register_selected = (address == STATUS_REGISTER_ADDR);
    wire cmp_1_register_selected = (address == CMP_1_REGISTER_ADDR);
    wire cmp_0_register_selected = (address == CMP_0_REGISTER_ADDR);
    wire count_register_selected = (address == COUNT_REGISTER_ADDR);
    wire count_min_selected = (address == COUNT_MIN_REGISTER_ADDR);
    wire count_max_selected = (address == COUNT_MAX_REGISTER_ADDR);



    wire read_enabled = !write_enable & enable; 
    wire write_enabled = write_enable & enable;




    wire [COUNTER_BIT_WIDTH-1:0] ctrl_reg = {
        cmp_1_int_en,
        cmp_0_int_en,
        clock_selector,
        count_mode,
        start,
        prescaler
    };





    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
        begin
            cmp_1_int_en = CTRL_REGISTER_RST[7];
            cmp_0_int_en = CTRL_REGISTER_RST[6];
            clock_selector = CTRL_REGISTER_RST[5];
            count_mode = CTRL_REGISTER_RST[4];
            start = CTRL_REGISTER_RST[3];
            prescaler = CTRL_REGISTER_RST[2:0];  
        end
        else
        begin 
            if(ctrl_register_selected & write_enabled)  
            begin
                cmp_1_int_en = write_data[7];
                cmp_0_int_en = write_data[6];
                clock_selector = write_data[5];
                count_mode = write_data[4];
                start = write_data[3];
                prescaler = write_data[2:0];  
            end
        end
    end


    wire clear_cmp_1_flag = status_register_selected & cmp_1_int_en & write_enabled & write_data[7];
    wire clear_cmp_0_flag = status_register_selected & cmp_0_int_en & write_enabled & write_data[6];

    reg cmp_1_flag_register = 0;
    reg cmp_0_flag_register = 0;

    wire [COUNTER_BIT_WIDTH-1:0] status_reg = {
        cmp_1_f,
        cmp_0_f,
        COUNTER_BIT_WIDTH-2'd0
    };

    always @(posedge clk, negedge rst, cmp_0_f) begin
        if(!rst)
        begin
            cmp_0_flag_register = 0;
        end
        else
        begin
            cmp_0_flag_register <= clear_cmp_0_flag ? 0 : cmp_0_flag_register |  cmp_0_f;
        end

    end

    always @(posedge clk, negedge rst, cmp_1_f) begin
        if(!rst)
        begin
            cmp_1_flag_register = 0;
        end
        else
        begin
            cmp_1_flag_register <= clear_cmp_1_flag ? 0 : cmp_1_flag_register |  cmp_1_f;
        end

    end


    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            cmp_0_value = CMP_0_REGISTER_RST;
        else 
            if(cmp_0_register_selected & write_enabled)  
                cmp_0_value = write_data;

    end

    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            cmp_1_value = CMP_1_REGISTER_RST;
        else   
            if(cmp_1_register_selected & write_enabled)  
                cmp_1_value = write_data;

    end

    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            count_min = COUNT_MIN_REGISTER_RST;
        else   
            if(count_min_selected & write_enabled)
                count_min = write_data;

    end


    always @(posedge clk, negedge rst) 
    begin
        if(!rst)
            count_max = COUNT_MAX_REGISTER_RST;
        else   
            if(count_max_selected & write_enabled)
                count_max = write_data;

    end



    always @(*) begin
        case(address)
            CTRL_REGISTER_ADDR: read_data_out = ctrl_reg;
            STATUS_REGISTER_ADDR: read_data_out = status_reg;
            CMP_1_REGISTER_ADDR: read_data_out = cmp_1_value;
            CMP_0_REGISTER_ADDR: read_data_out = cmp_0_value;
            COUNT_REGISTER_ADDR: read_data_out = count;
            COUNT_MIN_REGISTER_ADDR: read_data_out = count_min;
            COUNT_MAX_REGISTER_ADDR: read_data_out = count_max;
            default: read_data_out = 0;
        endcase
    end

    assign read_data = read_data_out & {COUNTER_BIT_WIDTH{read_enabled}};

endmodule