data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv
1: b"%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:18: Cannot find file containing module: 'naive_bus'\nnaive_bus  bus_masters[3]();\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL,data/full_repos/permissive/435890256/naive_bus\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL,data/full_repos/permissive/435890256/naive_bus.v\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL,data/full_repos/permissive/435890256/naive_bus.sv\n             naive_bus\n             naive_bus.v\n             naive_bus.sv\n             obj_dir/naive_bus\n             obj_dir/naive_bus.v\n             obj_dir/naive_bus.sv\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:19: Cannot find file containing module: 'naive_bus'\nnaive_bus  bus_slaves[5]();\n^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:22: Cannot find file containing module: 'isp_uart'\nisp_uart  #(\n^~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:36: Cannot find file containing module: 'core_top'\ncore_top core_top_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:45: Cannot find file containing module: 'instr_rom'\ninstr_rom instr_rom_inst(\n^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:52: Cannot find file containing module: 'ram_bus_wrapper'\nram_bus_wrapper instr_ram_inst(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:59: Cannot find file containing module: 'ram_bus_wrapper'\nram_bus_wrapper data_ram_inst(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:67: Cannot find file containing module: 'video_ram'\nvideo_ram  #(\n^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/soc_top.sv:94: Cannot find file containing module: 'naive_bus_router'\nnaive_bus_router #(\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module soc_top  #(
    parameter  UART_RX_CLK_DIV = 108,
    parameter  UART_TX_CLK_DIV = 434,
    parameter  VGA_CLK_DIV     = 1
)(

    input  logic clk,

    input  logic isp_uart_rx,
    output logic isp_uart_tx,

    output logic vga_hsync, vga_vsync,
    output logic vga_red, vga_green, vga_blue
);
logic rst_n;
logic [31:0] boot_addr;

naive_bus  bus_masters[3]();
naive_bus  bus_slaves[5]();


isp_uart  #(
   .UART_RX_CLK_DIV    ( UART_RX_CLK_DIV),
   .UART_TX_CLK_DIV    ( UART_TX_CLK_DIV)
) isp_uart_inst(
    .clk               ( clk            ),
    .i_uart_rx         ( isp_uart_rx    ),
    .o_uart_tx         ( isp_uart_tx    ),
    .o_rst_n           ( rst_n          ),
    .o_boot_addr       ( boot_addr      ),
    .bus               ( bus_masters[0] ),
    .user_uart_bus     ( bus_slaves[4]  )
);


core_top core_top_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .i_boot_addr       ( boot_addr      ),
    .instr_master      ( bus_masters[2] ),
    .data_master       ( bus_masters[1] )
);


instr_rom instr_rom_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[0]  )
);


ram_bus_wrapper instr_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[1]  )
);


ram_bus_wrapper data_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[2]  )
);



video_ram  #(
    .VGA_CLK_DIV       ( VGA_CLK_DIV    )
)video_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[3]  ),
    .o_vsync           ( vga_vsync      ),
    .o_hsync           ( vga_hsync      ),
    .o_red             ( vga_red        ),
    .o_green           ( vga_green      ),
    .o_blue            ( vga_blue       )
);















naive_bus_router #(
    .N_MASTER          ( 3 ),
    .N_SLAVE           ( 5 ),
    .SLAVES_MASK       ( { 32'h0000_0003 , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff  , 32'h0000_0fff } ),
    .SLAVES_BASE       ( { 32'h0003_0000 , 32'h0002_0000 , 32'h0001_0000 , 32'h0000_8000  , 32'h0000_0000 } )
) soc_bus_router_inst (
    .clk               ( clk          ),
    .rst_n             ( rst_n        ),
    .masters           ( bus_masters  ),
    .slaves            ( bus_slaves   )
);

endmodule
module soc_top  #(
    parameter  UART_RX_CLK_DIV = 108,
    parameter  UART_TX_CLK_DIV = 434,
    parameter  VGA_CLK_DIV     = 1
)(

    input  logic clk,

    input  logic isp_uart_rx,
    output logic isp_uart_tx,

    output logic vga_hsync, vga_vsync,
    output logic vga_red, vga_green, vga_blue
);

logic rst_n;
logic [31:0] boot_addr;

naive_bus  bus_masters[3]();
naive_bus  bus_slaves[5]();


isp_uart  #(
   .UART_RX_CLK_DIV    ( UART_RX_CLK_DIV),
   .UART_TX_CLK_DIV    ( UART_TX_CLK_DIV)
) isp_uart_inst(
    .clk               ( clk            ),
    .i_uart_rx         ( isp_uart_rx    ),
    .o_uart_tx         ( isp_uart_tx    ),
    .o_rst_n           ( rst_n          ),
    .o_boot_addr       ( boot_addr      ),
    .bus               ( bus_masters[0] ),
    .user_uart_bus     ( bus_slaves[4]  )
);


core_top core_top_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .i_boot_addr       ( boot_addr      ),
    .instr_master      ( bus_masters[2] ),
    .data_master       ( bus_masters[1] )
);


instr_rom instr_rom_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[0]  )
);


ram_bus_wrapper instr_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[1]  )
);


ram_bus_wrapper data_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[2]  )
);



video_ram  #(
    .VGA_CLK_DIV       ( VGA_CLK_DIV    )
)video_ram_inst(
    .clk               ( clk            ),
    .rst_n             ( rst_n          ),
    .bus               ( bus_slaves[3]  ),
    .o_vsync           ( vga_vsync      ),
    .o_hsync           ( vga_hsync      ),
    .o_red             ( vga_red        ),
    .o_green           ( vga_green      ),
    .o_blue            ( vga_blue       )
);















naive_bus_router #(
    .N_MASTER          ( 3 ),
    .N_SLAVE           ( 5 ),
    .SLAVES_MASK       ( { 32'h0000_0003 , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff  , 32'h0000_0fff } ),
    .SLAVES_BASE       ( { 32'h0003_0000 , 32'h0002_0000 , 32'h0001_0000 , 32'h0000_8000  , 32'h0000_0000 } )
) soc_bus_router_inst (
    .clk               ( clk          ),
    .rst_n             ( rst_n        ),
    .masters           ( bus_masters  ),
    .slaves            ( bus_slaves   )
);

endmodule