data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module adder_tb;

    localparam WIDTH = 32;
    localparam LOGWIDTH = $clog2(WIDTH);

    reg  [WIDTH-1:0]    a, b;
    reg  [0:0]          ci;
    wire [WIDTH-1:0]    muv0_s, muv1_s, muv2_s, muv3_s;
    wire [0:0]          muv0_c, muv1_c, muv2_c, muv3_c;
    

    `TB_INIT(adder_tb, "adder_tb.vcd", 0, 50_000)

    rca muv0( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv0_s),
	    .co(muv0_c)
    );

    csa32_8 muv1( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv1_s),
	    .co(muv1_c)
    );

    csa32_16 muv2( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv2_s),
	    .co(muv2_c)
    );

    cla muv3( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv3_s),
	    .co(muv3_c)
    );


    wire [WIDTH-1:0] golden_s;
    wire golden_c;
    assign {golden_c,golden_s} =  a + b + ci;


    always @(golden_c or golden_s) begin
        #1;
        if(golden_s != muv0_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv0_c, muv0_s, golden_c, golden_s);
        else if(golden_c != muv0_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv0_c, muv0_s, golden_c, golden_s);
        else if(golden_s != muv1_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv1_c, muv1_s, golden_c, golden_s);
        else if(golden_c != muv1_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv1_c, muv1_s, golden_c, golden_s);    
        else if(golden_s != muv2_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv2_c, muv2_s, golden_c, golden_s);
        else if(golden_c != muv2_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv2_c, muv2_s, golden_c, golden_s);
    end

    initial begin
        a = 20;
        b = 30;
        ci = 0;
        #10;
        ci = 1;
        #10;
        a = -20;
        b = -30;
        #10;
        ci = 0;
        #50;
        a = 10000;
        b = 3400000;
        #10;
        a = -100;
        b = 30;
        #10;
        ci = 1;
        #10;
        a = -100;
        b = 100;
        #10;
        a = -100;
        b = 200;
        #10;
        a = -400;
        b = 300;
        #10;
        a = 32'hFFFF_FFFF;
        b = 1;
        #10;
        ci = 0;
        #10;
        $finish;
    end
endmodule
module adder_tb;


    localparam WIDTH = 32;
    localparam LOGWIDTH = $clog2(WIDTH);

    reg  [WIDTH-1:0]    a, b;
    reg  [0:0]          ci;
    wire [WIDTH-1:0]    muv0_s, muv1_s, muv2_s, muv3_s;
    wire [0:0]          muv0_c, muv1_c, muv2_c, muv3_c;
    

    `TB_INIT(adder_tb, "adder_tb.vcd", 0, 50_000)

    rca muv0( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv0_s),
	    .co(muv0_c)
    );

    csa32_8 muv1( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv1_s),
	    .co(muv1_c)
    );

    csa32_16 muv2( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv2_s),
	    .co(muv2_c)
    );

    cla muv3( 
	    .a(a), .b(b),
	    .ci(ci),
	    .s(muv3_s),
	    .co(muv3_c)
    );


    wire [WIDTH-1:0] golden_s;
    wire golden_c;
    assign {golden_c,golden_s} =  a + b + ci;


    always @(golden_c or golden_s) begin
        #1;
        if(golden_s != muv0_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv0_c, muv0_s, golden_c, golden_s);
        else if(golden_c != muv0_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv0_c, muv0_s, golden_c, golden_s);
        else if(golden_s != muv1_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv1_c, muv1_s, golden_c, golden_s);
        else if(golden_c != muv1_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv1_c, muv1_s, golden_c, golden_s);    
        else if(golden_s != muv2_s)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv2_c, muv2_s, golden_c, golden_s);
        else if(golden_c != muv2_c)
            $display("Test Failed - %x + %x + %x= %x, %c (should be %x, %x)", a, b, ci, muv2_c, muv2_s, golden_c, golden_s);
    end

    initial begin
        a = 20;
        b = 30;
        ci = 0;
        #10;
        ci = 1;
        #10;
        a = -20;
        b = -30;
        #10;
        ci = 0;
        #50;
        a = 10000;
        b = 3400000;
        #10;
        a = -100;
        b = 30;
        #10;
        ci = 1;
        #10;
        a = -100;
        b = 100;
        #10;
        a = -100;
        b = 200;
        #10;
        a = -400;
        b = 300;
        #10;
        a = 32'hFFFF_FFFF;
        b = 1;
        #10;
        ci = 0;
        #10;
        $finish;
    end
endmodule