data/full_repos/permissive/500128826/but-2-led-clocked/top.v
data/verilator_xmls/9f691416-5a21-4949-8261-ad6f0af1f52d.xml
module top (
    input  wire CLK,
    input  wire BUT1,
    input  wire BUT2,
    output wire LED1,
    output wire LED2
);

  reg LED1_r;
  reg LED2_r;

  assign LED1 = LED1_r;
  assign LED2 = LED2_r;

  always @(posedge CLK) begin
    LED1_r <= ~BUT1;
    LED2_r <= ~BUT2;
  end

endmodule
module top (
    input  wire CLK,
    input  wire BUT1,
    input  wire BUT2,
    output wire LED1,
    output wire LED2
);


  reg LED1_r;
  reg LED2_r;

  assign LED1 = LED1_r;
  assign LED2 = LED2_r;

  always @(posedge CLK) begin
    LED1_r <= ~BUT1;
    LED2_r <= ~BUT2;
  end

endmodule