data/full_repos/permissive/449071180/three_bit_mux.v
data/verilator_xmls/7f5c9e28-bc5d-4f83-9ab2-68ea1c7e23bf.xml
module three_bit_mux(in1,in2,cntrl,out1);
input [2:0] in1;
input [2:0] in2;

input cntrl;

output reg [2:0] out1;

always@(in1,in2,cntrl) begin
if( cntrl == 0) begin
out1 = in2;
end else begin
out1 = in1;
end
end

endmodule
module three_bit_mux(in1,in2,cntrl,out1);

input [2:0] in1;
input [2:0] in2;

input cntrl;

output reg [2:0] out1;

always@(in1,in2,cntrl) begin
if( cntrl == 0) begin
out1 = in2;
end else begin
out1 = in1;
end
end

endmodule