data/full_repos/permissive/460468583/data/yosys/intel/cyclone10lp/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/intel/cyclone10lp/cells_sim.v:23: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                   : ... Top module \'VCC\'\nmodule VCC (output V);\n       ^~~\n                                                                                                   : ... Top module \'GND\'\nmodule GND (output G);\n       ^~~\n                                                                                                   : ... Top module \'cyclone10lp_io_ibuf\'\nmodule cyclone10lp_io_ibuf\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'cyclone10lp_io_obuf\'\nmodule cyclone10lp_io_obuf\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'cyclone10lp_lcell_comb\'\nmodule cyclone10lp_lcell_comb\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'dffeas\'\nmodule dffeas\n       ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/460468583/data/yosys/intel/cyclone10lp/cells_sim.v:30: Assigning to input/const variable: \'ibar\'\n   assign ibar = ibar;\n          ^~~~\n%Error-ASSIGNIN: data/full_repos/permissive/460468583/data/yosys/intel/cyclone10lp/cells_sim.v:38: Assigning to input/const variable: \'oe\'\n   assign oe = oe;\n          ^~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module dffeas
  (output q,
   input d, clk, clrn, prn, ena,
   input asdata, aload, sclr, sload);


   parameter power_up="dontcare";
   parameter is_wysiwyg="false";

   reg   q_tmp;
   wire  reset;
   reg [7:0] debug_net;

   assign reset       = (prn && sclr && ~clrn && ena);
   assign q           = q_tmp & 1'b1;

   always @(posedge clk, posedge aload) begin
      if(reset)        q_tmp <= 0;
      else q_tmp <= d;
   end
   assign q = q_tmp;

endmodule
module dffeas
  (output q,
   input d, clk, clrn, prn, ena,
   input asdata, aload, sclr, sload);



   parameter power_up="dontcare";
   parameter is_wysiwyg="false";

   reg   q_tmp;
   wire  reset;
   reg [7:0] debug_net;

   assign reset       = (prn && sclr && ~clrn && ena);
   assign q           = q_tmp & 1'b1;

   always @(posedge clk, posedge aload) begin
      if(reset)        q_tmp <= 0;
      else q_tmp <= d;
   end
   assign q = q_tmp;

endmodule