data/full_repos/permissive/493019833/test/testcase/firrtl/TrimTypeCircuit/reference/TrimTypeCircuit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/TrimTypeCircuit/reference/TrimTypeCircuit.v:87: Operator COND expects 20 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 11 bits.\n                                                                                                                        : ... In instance TrimTypeCircuit.s_pad_5\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/TrimTypeCircuit/reference/TrimTypeCircuit.v:87: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 9 bits.\n                                                                                                                        : ... In instance TrimTypeCircuit.s_pad_6\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module TrimTypeCircuit(
    input clock,
    input reset,
    input [3:0] io_a,
    input [3:0] io_b,
    output [9:0] io_multiplyRoundHalfUp,
    output [19:0] io_multiplyNoTrim
);
    wire [7:0] _T_2;
    MUL2_SIGNED #(.width_a(4), .width_b(4)) s_mul2_1 (
        .y(_T_2),
        .a(io_a),
        .b(io_b)
    );
    wire [7:0] _regMultiplyRoundHalfUp__q;
    wire [7:0] _regMultiplyRoundHalfUp__d;
    DFF_POSCLK #(.width(8)) regMultiplyRoundHalfUp (
        .q(_regMultiplyRoundHalfUp__q),
        .d(_regMultiplyRoundHalfUp__d),
        .clk(clock)
    );
    wire [7:0] _T_4;
    MUL2_SIGNED #(.width_a(4), .width_b(4)) s_mul2_2 (
        .y(_T_4),
        .a(io_a),
        .b(io_b)
    );
    wire [7:0] _regMultiplyNoTrim__q;
    wire [7:0] _regMultiplyNoTrim__d;
    DFF_POSCLK #(.width(8)) regMultiplyNoTrim (
        .q(_regMultiplyNoTrim__q),
        .d(_regMultiplyNoTrim__d),
        .clk(clock)
    );
    wire [8:0] _node_0;
    SHL_SIGNED #(.width(8), .n(1)) s_shl_3 (
        .y(_node_0),
        .in(_regMultiplyRoundHalfUp__q)
    );
    wire [10:0] _node_1;
    SHL_SIGNED #(.width(8), .n(3)) s_shl_4 (
        .y(_node_1),
        .in(_regMultiplyNoTrim__q)
    );
    PAD_SIGNED #(.width(11), .n(20)) s_pad_5 (
        .y(io_multiplyNoTrim),
        .in(_node_1)
    );
    PAD_SIGNED #(.width(9), .n(10)) s_pad_6 (
        .y(io_multiplyRoundHalfUp),
        .in(_node_0)
    );
    assign _regMultiplyNoTrim__d = _T_4;
    assign _regMultiplyRoundHalfUp__d = _T_2;
endmodule
module TrimTypeCircuit(
    input clock,
    input reset,
    input [3:0] io_a,
    input [3:0] io_b,
    output [9:0] io_multiplyRoundHalfUp,
    output [19:0] io_multiplyNoTrim
);

    wire [7:0] _T_2;
    MUL2_SIGNED #(.width_a(4), .width_b(4)) s_mul2_1 (
        .y(_T_2),
        .a(io_a),
        .b(io_b)
    );
    wire [7:0] _regMultiplyRoundHalfUp__q;
    wire [7:0] _regMultiplyRoundHalfUp__d;
    DFF_POSCLK #(.width(8)) regMultiplyRoundHalfUp (
        .q(_regMultiplyRoundHalfUp__q),
        .d(_regMultiplyRoundHalfUp__d),
        .clk(clock)
    );
    wire [7:0] _T_4;
    MUL2_SIGNED #(.width_a(4), .width_b(4)) s_mul2_2 (
        .y(_T_4),
        .a(io_a),
        .b(io_b)
    );
    wire [7:0] _regMultiplyNoTrim__q;
    wire [7:0] _regMultiplyNoTrim__d;
    DFF_POSCLK #(.width(8)) regMultiplyNoTrim (
        .q(_regMultiplyNoTrim__q),
        .d(_regMultiplyNoTrim__d),
        .clk(clock)
    );
    wire [8:0] _node_0;
    SHL_SIGNED #(.width(8), .n(1)) s_shl_3 (
        .y(_node_0),
        .in(_regMultiplyRoundHalfUp__q)
    );
    wire [10:0] _node_1;
    SHL_SIGNED #(.width(8), .n(3)) s_shl_4 (
        .y(_node_1),
        .in(_regMultiplyNoTrim__q)
    );
    PAD_SIGNED #(.width(11), .n(20)) s_pad_5 (
        .y(io_multiplyNoTrim),
        .in(_node_1)
    );
    PAD_SIGNED #(.width(9), .n(10)) s_pad_6 (
        .y(io_multiplyRoundHalfUp),
        .in(_node_0)
    );
    assign _regMultiplyNoTrim__d = _T_4;
    assign _regMultiplyRoundHalfUp__d = _T_2;
endmodule