data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:28: Cannot find file containing module: 'and_cell'\n  and_cell gate1 (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.v\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.sv\n             and_cell\n             and_cell.v\n             and_cell.sv\n             obj_dir/and_cell\n             obj_dir/and_cell.v\n             obj_dir/and_cell.sv\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:31: Cannot find file containing module: 'or_cell'\n  or_cell gate2 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:34: Cannot find file containing module: 'xor_cell'\n  xor_cell gate3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:37: Cannot find file containing module: 'nand_cell'\n  nand_cell gate4 (\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:40: Cannot find file containing module: 'not_cell'\n  not_cell gate5 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:43: Cannot find file containing module: 'buffer_cell'\n  buffer_cell gate6 (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:46: Cannot find file containing module: 'mux_cell'\n  mux_cell mux1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:49: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:52: Cannot find file containing module: 'not_cell'\n  not_cell gate9 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:56: Cannot find file containing module: 'not_cell'\n  not_cell gate10 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:60: Cannot find file containing module: 'not_cell'\n  not_cell gate7 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:64: Cannot find file containing module: 'not_cell'\n  not_cell gate8 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:68: Cannot find file containing module: 'not_cell'\n  not_cell gate11 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:72: Cannot find file containing module: 'not_cell'\n  not_cell gate12 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:76: Cannot find file containing module: 'and_cell'\n  and_cell gate13 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:81: Cannot find file containing module: 'and_cell'\n  and_cell gate14 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:86: Cannot find file containing module: 'or_cell'\n  or_cell gate15 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341192621088047698.v:91: Cannot find file containing module: 'not_cell'\n  not_cell gate16 (\n  ^~~~~~~~\n%Error: Exiting due to 18 error(s)\n"
module user_module_341192621088047698(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5 = 1'b0;
  wire net6 = 1'b1;
  wire net7 = 1'b1;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;

  assign io_out[0] = net4;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate9 (
    .in (net3),
    .out (net8)
  );
  not_cell gate10 (
    .in (net8),
    .out (net9)
  );
  not_cell gate7 (
    .in (net1),
    .out (net10)
  );
  not_cell gate8 (
    .in (net2),
    .out (net11)
  );
  not_cell gate11 (
    .in (net10),
    .out (net12)
  );
  not_cell gate12 (
    .in (net11),
    .out (net13)
  );
  and_cell gate13 (
    .a (net12),
    .b (net9),
    .out (net14)
  );
  and_cell gate14 (
    .a (net13),
    .b (net8),
    .out (net15)
  );
  or_cell gate15 (
    .a (net14),
    .b (net15),
    .out (net16)
  );
  not_cell gate16 (
    .in (net16),
    .out (net4)
  );
endmodule
module user_module_341192621088047698(
  input [7:0] io_in,
  output [7:0] io_out
);

  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5 = 1'b0;
  wire net6 = 1'b1;
  wire net7 = 1'b1;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;

  assign io_out[0] = net4;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate9 (
    .in (net3),
    .out (net8)
  );
  not_cell gate10 (
    .in (net8),
    .out (net9)
  );
  not_cell gate7 (
    .in (net1),
    .out (net10)
  );
  not_cell gate8 (
    .in (net2),
    .out (net11)
  );
  not_cell gate11 (
    .in (net10),
    .out (net12)
  );
  not_cell gate12 (
    .in (net11),
    .out (net13)
  );
  and_cell gate13 (
    .a (net12),
    .b (net9),
    .out (net14)
  );
  and_cell gate14 (
    .a (net13),
    .b (net8),
    .out (net15)
  );
  or_cell gate15 (
    .a (net14),
    .b (net15),
    .out (net16)
  );
  not_cell gate16 (
    .in (net16),
    .out (net4)
  );
endmodule