data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v
1: b'%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:32: Cannot find include file: sd_defines.h\n`include "sd_defines.h" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.v\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.sv\n             sd_defines.h\n             sd_defines.h.v\n             sd_defines.h.sv\n             obj_dir/sd_defines.h\n             obj_dir/sd_defines.h.v\n             obj_dir/sd_defines.h.sv\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:40: Define or directive not defined: \'`DATA_TIMEOUT_W\'\n    input [`DATA_TIMEOUT_W-1:0] timeout_i,\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:54: Define or directive not defined: \'`INT_DATA_SIZE\'\n    output reg [`INT_DATA_SIZE-1:0] int_status_o,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:64: Define or directive not defined: \'`DATA_TIMEOUT_W\'\nreg [`DATA_TIMEOUT_W-1:0] watchdog;\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:116: Define or directive not defined: \'`INT_DATA_CFE\'\n                        int_status_o[`INT_DATA_CFE] <= 1;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:116: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_CFE] <= 1;\n                                                  ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:117: Define or directive not defined: \'`INT_DATA_EI\'\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                                 ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:125: Define or directive not defined: \'`INT_DATA_CFE\'\n                        int_status_o[`INT_DATA_CFE] <= 1;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_CFE] <= 1;\n                                                  ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:126: Define or directive not defined: \'`INT_DATA_EI\'\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                                 ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:134: Define or directive not defined: \'`INT_DATA_CTE\'\n                    int_status_o[`INT_DATA_CTE] <= 1;\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:134: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    int_status_o[`INT_DATA_CTE] <= 1;\n                                              ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:135: Define or directive not defined: \'`INT_DATA_EI\'\n                    int_status_o[`INT_DATA_EI] <= 1;\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:135: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    int_status_o[`INT_DATA_EI] <= 1;\n                                             ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:143: Define or directive not defined: \'`INT_DATA_CCRCE\'\n                        int_status_o[`INT_DATA_CCRCE] <= 1;\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:143: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_CCRCE] <= 1;\n                                                    ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:144: Define or directive not defined: \'`INT_DATA_EI\'\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:144: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_EI] <= 1;\n                                                 ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:146: Define or directive not defined: \'`INT_DATA_CC\'\n                        int_status_o[`INT_DATA_CC] <= 1;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_master.v:146: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        int_status_o[`INT_DATA_CC] <= 1;\n                                                 ^\n%Error: Exiting due to 22 error(s)\n'
module sd_data_master (
    input clock,
    input clock_posedge,
    input rst,
    input start_tx_i,
    input start_rx_i,
    input [`DATA_TIMEOUT_W-1:0] timeout_i,

    output reg d_write_o,
    output reg d_read_o,

    output reg start_tx_fifo_o,
    output reg start_rx_fifo_o,
    input tx_fifo_empty_i,
    input tx_fifo_ready_i,
    input rx_fifo_full_i,

    input xfr_complete_i,
    input crc_ok_i,

    output reg [`INT_DATA_SIZE-1:0] int_status_o,
    input int_status_rst_i
);

reg [3:0] state;
localparam IDLE          = 4'b0001;
localparam START_TX_FIFO = 4'b0010;
localparam START_RX_FIFO = 4'b0100;
localparam DATA_TRANSFER = 4'b1000;

reg [`DATA_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg watchdog_alarm;
reg tx_cycle;

always @(posedge clock) begin
    if (rst) begin
        start_tx_fifo_o <= 0;
        start_rx_fifo_o <= 0;
        d_write_o <= 0;
        d_read_o <= 0;
        tx_cycle <= 0;
        int_status_o <= 0;
        watchdog <= 0;
        watchdog_enable <= 0;
        watchdog_alarm <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                start_tx_fifo_o <= 0;
                start_rx_fifo_o <= 0;
                d_write_o <= 0;
                d_read_o <= 0;
                tx_cycle <= 0;
                watchdog <= 0;
                watchdog_enable <= timeout_i != 0;
                watchdog_alarm <= 0;
                if (start_tx_i) state <= START_TX_FIFO;
                else if (start_rx_i) state <= START_RX_FIFO;
            end
            START_RX_FIFO: begin
                start_rx_fifo_o <= 1;
                start_tx_fifo_o <= 0;
                tx_cycle <= 0;
                d_read_o <= 1;
                if (!xfr_complete_i) state <= DATA_TRANSFER;
            end
            START_TX_FIFO:  begin
                start_rx_fifo_o <= 0;
                start_tx_fifo_o <= 1;
                tx_cycle <= 1;
                if (tx_fifo_ready_i) begin
                    d_write_o <= 1;
                    if (!xfr_complete_i) state <= DATA_TRANSFER;
                end
            end
            DATA_TRANSFER: begin
                d_read_o <= 0;
                d_write_o <= 0;
                if (tx_cycle) begin
                    if (tx_fifo_empty_i) begin
                        int_status_o[`INT_DATA_CFE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                        state <= IDLE;

                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end else begin
                    if (rx_fifo_full_i) begin
                        int_status_o[`INT_DATA_CFE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                        state <= IDLE;

                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end
                if (watchdog_alarm) begin
                    int_status_o[`INT_DATA_CTE] <= 1;
                    int_status_o[`INT_DATA_EI] <= 1;
                    state <= IDLE;

                    d_write_o <= 1;
                    d_read_o <= 1;
                end else if (xfr_complete_i) begin
                    state <= IDLE;
                    if (!crc_ok_i) begin
                        int_status_o[`INT_DATA_CCRCE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                    end else begin
                        int_status_o[`INT_DATA_CC] <= 1;
                    end
                end else if (watchdog_enable) begin
                    watchdog <= watchdog + 1;
                    if (watchdog >= timeout_i) watchdog_alarm <= 1;
                end
            end
        endcase
        if (int_status_rst_i)
            int_status_o <= 0;
    end
end

endmodule
module sd_data_master (
    input clock,
    input clock_posedge,
    input rst,
    input start_tx_i,
    input start_rx_i,
    input [`DATA_TIMEOUT_W-1:0] timeout_i,

    output reg d_write_o,
    output reg d_read_o,

    output reg start_tx_fifo_o,
    output reg start_rx_fifo_o,
    input tx_fifo_empty_i,
    input tx_fifo_ready_i,
    input rx_fifo_full_i,

    input xfr_complete_i,
    input crc_ok_i,

    output reg [`INT_DATA_SIZE-1:0] int_status_o,
    input int_status_rst_i
);


reg [3:0] state;
localparam IDLE          = 4'b0001;
localparam START_TX_FIFO = 4'b0010;
localparam START_RX_FIFO = 4'b0100;
localparam DATA_TRANSFER = 4'b1000;

reg [`DATA_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg watchdog_alarm;
reg tx_cycle;

always @(posedge clock) begin
    if (rst) begin
        start_tx_fifo_o <= 0;
        start_rx_fifo_o <= 0;
        d_write_o <= 0;
        d_read_o <= 0;
        tx_cycle <= 0;
        int_status_o <= 0;
        watchdog <= 0;
        watchdog_enable <= 0;
        watchdog_alarm <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                start_tx_fifo_o <= 0;
                start_rx_fifo_o <= 0;
                d_write_o <= 0;
                d_read_o <= 0;
                tx_cycle <= 0;
                watchdog <= 0;
                watchdog_enable <= timeout_i != 0;
                watchdog_alarm <= 0;
                if (start_tx_i) state <= START_TX_FIFO;
                else if (start_rx_i) state <= START_RX_FIFO;
            end
            START_RX_FIFO: begin
                start_rx_fifo_o <= 1;
                start_tx_fifo_o <= 0;
                tx_cycle <= 0;
                d_read_o <= 1;
                if (!xfr_complete_i) state <= DATA_TRANSFER;
            end
            START_TX_FIFO:  begin
                start_rx_fifo_o <= 0;
                start_tx_fifo_o <= 1;
                tx_cycle <= 1;
                if (tx_fifo_ready_i) begin
                    d_write_o <= 1;
                    if (!xfr_complete_i) state <= DATA_TRANSFER;
                end
            end
            DATA_TRANSFER: begin
                d_read_o <= 0;
                d_write_o <= 0;
                if (tx_cycle) begin
                    if (tx_fifo_empty_i) begin
                        int_status_o[`INT_DATA_CFE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                        state <= IDLE;

                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end else begin
                    if (rx_fifo_full_i) begin
                        int_status_o[`INT_DATA_CFE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                        state <= IDLE;

                        d_write_o <= 1;
                        d_read_o <= 1;
                    end
                end
                if (watchdog_alarm) begin
                    int_status_o[`INT_DATA_CTE] <= 1;
                    int_status_o[`INT_DATA_EI] <= 1;
                    state <= IDLE;

                    d_write_o <= 1;
                    d_read_o <= 1;
                end else if (xfr_complete_i) begin
                    state <= IDLE;
                    if (!crc_ok_i) begin
                        int_status_o[`INT_DATA_CCRCE] <= 1;
                        int_status_o[`INT_DATA_EI] <= 1;
                    end else begin
                        int_status_o[`INT_DATA_CC] <= 1;
                    end
                end else if (watchdog_enable) begin
                    watchdog <= watchdog + 1;
                    if (watchdog >= timeout_i) watchdog_alarm <= 1;
                end
            end
        endcase
        if (int_status_rst_i)
            int_status_o <= 0;
    end
end

endmodule