data/full_repos/permissive/42434302/vpi/memwide.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/memwide.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 $display("!!!VERILOG: big_reg=%h",big_reg);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/memwide.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 big_reg=33\'h1_2345_6789;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/memwide.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 $display("!!!VERILOG: big_reg=%h",big_reg);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/memwide.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/42434302/vpi/memwide.v:22: Little bit endian vector: MSB < LSB of bit range: 0:32\n  reg [0:32] big_reg;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/42434302/vpi/memwide.v:23: Little bit endian vector: MSB < LSB of bit range: 0:32\n  reg [0:32] my_mem[0:16];\n      ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

  reg [0:32]	big_reg;
  reg [0:32]	my_mem[0:16];
  reg		event_trigger;

  initial begin
    #10 $display("!!!VERILOG: big_reg=%h",big_reg);
        $display("            my_mem[1]=%h",my_mem[1]);
        event_trigger=1;
    #10 big_reg=33'h1_2345_6789;
        my_mem[1]=33'h1_5432_9876;
    #10 $display("!!!VERILOG: big_reg=%h",big_reg);
        $display("            my_mem[1]=%h",my_mem[1]);
        event_trigger=!event_trigger;
    #10 $finish;
  end

endmodule
module test;


  reg [0:32]	big_reg;
  reg [0:32]	my_mem[0:16];
  reg		event_trigger;

  initial begin
    #10 $display("!!!VERILOG: big_reg=%h",big_reg);
        $display("            my_mem[1]=%h",my_mem[1]);
        event_trigger=1;
    #10 big_reg=33'h1_2345_6789;
        my_mem[1]=33'h1_5432_9876;
    #10 $display("!!!VERILOG: big_reg=%h",big_reg);
        $display("            my_mem[1]=%h",my_mem[1]);
        event_trigger=!event_trigger;
    #10 $finish;
  end

endmodule