data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_serialdp/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_serialdp,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_serialdp/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire clk,
    input wire in,
    input wire reset,
    output wire [7:0] out_byte,
    output wire done
);

  wire [2:0] state, next_state;
  wire [4:0] bits;
  wire [9:0] data;


  fsm_next_state ns (
      .in(in),
      .state(state),
      .bits(bits),
      .next_state(next_state)
  );


  fsm_state_transition st (
      .clk(clk),
      .in(in),
      .reset(reset),
      .next_state(next_state),
      .bits(bits),
      .state(state),
      .data(data)
  );


  fsm_output o (
      .state(state),
      .data(data),
      .out_byte(out_byte),
      .done(done)
  );
endmodule
module top_module (
    input wire clk,
    input wire in,
    input wire reset,
    output wire [7:0] out_byte,
    output wire done
);


  wire [2:0] state, next_state;
  wire [4:0] bits;
  wire [9:0] data;


  fsm_next_state ns (
      .in(in),
      .state(state),
      .bits(bits),
      .next_state(next_state)
  );


  fsm_state_transition st (
      .clk(clk),
      .in(in),
      .reset(reset),
      .next_state(next_state),
      .bits(bits),
      .state(state),
      .data(data)
  );


  fsm_output o (
      .state(state),
      .data(data),
      .out_byte(out_byte),
      .done(done)
  );
endmodule