data/full_repos/permissive/488894374/headers/mem.sv
data/verilator_xmls/b4697738-0340-4261-a715-f507526018de.xml
module mem #(
        parameter  ADDR_LEN  = 11
    ) (
        input  clk, rst,
        input  [ADDR_LEN-1:0] addr,
        output reg [31:0] rd_data,
        input  wr_req,
        input  [31:0] wr_data
    );
    localparam MEM_SIZE = 1<<ADDR_LEN;
    reg [31:0] ram_cell [MEM_SIZE];

    always @ (posedge clk)
        if(rst)
            rd_data <= 0;
        else
            rd_data <= ram_cell[addr];

    always @ (posedge clk)
        if(wr_req)
            ram_cell[addr] <= wr_data;

endmodule
module mem #(
        parameter  ADDR_LEN  = 11
    ) (
        input  clk, rst,
        input  [ADDR_LEN-1:0] addr,
        output reg [31:0] rd_data,
        input  wr_req,
        input  [31:0] wr_data
    );

    localparam MEM_SIZE = 1<<ADDR_LEN;
    reg [31:0] ram_cell [MEM_SIZE];

    always @ (posedge clk)
        if(rst)
            rd_data <= 0;
        else
            rd_data <= ram_cell[addr];

    always @ (posedge clk)
        if(wr_req)
            ram_cell[addr] <= wr_data;

endmodule