data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v:68: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v:38: Cannot find file containing module: \'clk_generator\'\n clk_generator uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/clk_generator\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/clk_generator.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/clk_generator.sv\n             clk_generator\n             clk_generator.v\n             clk_generator.sv\n             obj_dir/clk_generator\n             obj_dir/clk_generator.v\n             obj_dir/clk_generator.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/gen_clk_tst.v:46: Cannot find file containing module: \'clk_counter\'\n clk_counter counter(\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_clk_tst;


	reg clk;
	reg rst;
	reg en;
	reg [31:0] limit;
	wire [31:0] count;


	wire clk_0;


	clk_generator uut (
		.clk(clk), 
		.en(en), 
		.limit(limit), 
		.count(count), 
		.clk_0(clk_0)
	);
	
	clk_counter counter(
		.clk(clk), 
		.en(en), 
		.rst(rst), 
		.count(count)
	);
	
	initial begin

		clk = 0;
		rst = 1;
		en = 0;
		limit = 0;


		#100;
      rst = 0;

		limit = 32'h000000FF;
		#100;
		en = 1;
	end
   always #5 clk = ~clk;
endmodule
module gen_clk_tst;



	reg clk;
	reg rst;
	reg en;
	reg [31:0] limit;
	wire [31:0] count;


	wire clk_0;


	clk_generator uut (
		.clk(clk), 
		.en(en), 
		.limit(limit), 
		.count(count), 
		.clk_0(clk_0)
	);
	
	clk_counter counter(
		.clk(clk), 
		.en(en), 
		.rst(rst), 
		.count(count)
	);
	
	initial begin

		clk = 0;
		rst = 1;
		en = 0;
		limit = 0;


		#100;
      rst = 0;

		limit = 32'h000000FF;
		#100;
		en = 1;
	end
   always #5 clk = ~clk;
endmodule