data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v
1: b'%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:36: Cannot find include file: pcie_defines.v\n`include "pcie_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/pcie_defines.v\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/pcie_defines.v.v\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/pcie_defines.v.sv\n             pcie_defines.v\n             pcie_defines.v.v\n             pcie_defines.v.sv\n             obj_dir/pcie_defines.v\n             obj_dir/pcie_defines.v.v\n             obj_dir/pcie_defines.v.sv\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:81: Define or directive not defined: \'`BAR_ADDR0\'\nassign  w_cfg_addr[0] = `BAR_ADDR0 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:81: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[0] = `BAR_ADDR0 >> 2;\n                                   ^~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:82: Define or directive not defined: \'`BAR_ADDR1\'\nassign  w_cfg_addr[1] = `BAR_ADDR1 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:82: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[1] = `BAR_ADDR1 >> 2;\n                                   ^~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:83: Define or directive not defined: \'`BAR_ADDR2\'\nassign  w_cfg_addr[2] = `BAR_ADDR2 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:83: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[2] = `BAR_ADDR2 >> 2;\n                                   ^~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:84: Define or directive not defined: \'`BAR_ADDR3\'\nassign  w_cfg_addr[3] = `BAR_ADDR3 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:84: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[3] = `BAR_ADDR3 >> 2;\n                                   ^~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:85: Define or directive not defined: \'`BAR_ADDR4\'\nassign  w_cfg_addr[4] = `BAR_ADDR4 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:85: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[4] = `BAR_ADDR4 >> 2;\n                                   ^~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:86: Define or directive not defined: \'`BAR_ADDR5\'\nassign  w_cfg_addr[5] = `BAR_ADDR5 >> 2;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/config_parser.v:86: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign  w_cfg_addr[5] = `BAR_ADDR5 >> 2;\n                                   ^~\n%Error: Exiting due to 13 error(s)\n'
module config_parser (
  input                     rst,
  input                     clk,

  input                     i_en,
  output  reg               o_finished,


  input       [31:0]        i_cfg_do,
  input                     i_cfg_rd_wr_done,
  output reg  [9:0]         o_cfg_dwaddr,
  output reg                o_cfg_rd_en,




  output  reg [31:0]        o_bar_addr0,
  output  reg [31:0]        o_bar_addr1,
  output  reg [31:0]        o_bar_addr2,
  output  reg [31:0]        o_bar_addr3,
  output  reg [31:0]        o_bar_addr4,
  output  reg [31:0]        o_bar_addr5
);



localparam  IDLE          = 4'h0;
localparam  PREP_ADDR     = 4'h1;
localparam  WAIT_STATE    = 4'h2;
localparam  READ_DATA     = 4'h3;
localparam  READ_NEXT     = 4'h4;



reg   [3:0]   state;
reg   [3:0]   index;
wire  [9:0]   w_cfg_addr[0:`MAX_READ_COUNT];




assign  w_cfg_addr[0] = `BAR_ADDR0 >> 2;
assign  w_cfg_addr[1] = `BAR_ADDR1 >> 2;
assign  w_cfg_addr[2] = `BAR_ADDR2 >> 2;
assign  w_cfg_addr[3] = `BAR_ADDR3 >> 2;
assign  w_cfg_addr[4] = `BAR_ADDR4 >> 2;
assign  w_cfg_addr[5] = `BAR_ADDR5 >> 2;




always @ (posedge clk) begin
  o_cfg_rd_en         <=  0;
  if (rst) begin
    state             <=  IDLE;
    index             <=  0;

    o_cfg_dwaddr      <=  w_cfg_addr[0];

    o_bar_addr0       <=  0;
    o_bar_addr1       <=  0;
    o_bar_addr2       <=  0;
    o_bar_addr3       <=  0;
    o_bar_addr4       <=  0;
    o_bar_addr5       <=  0;

    o_finished        <=  0;
  end
  else begin
    case (state)
      IDLE: begin
        o_finished        <=  0;
        index             <=  0;
        if (i_en) begin
          state           <=  PREP_ADDR;
        end
      end
      PREP_ADDR: begin
        case (index)
          0: begin

            o_cfg_dwaddr  <=  4;
          end
          1: begin

            o_cfg_dwaddr  <=  5;
          end
          2: begin

            o_cfg_dwaddr  <=  6;
          end
          3: begin

            o_cfg_dwaddr  <=  7;
          end
          4: begin

            o_cfg_dwaddr  <=  8;
          end
          5: begin

            o_cfg_dwaddr  <=  9;
          end
        endcase
        state             <=  WAIT_STATE;
      end
      WAIT_STATE: begin
        o_cfg_rd_en       <=  1;
        if (i_cfg_rd_wr_done) begin
          state           <=  READ_DATA;
        end
      end
      READ_DATA: begin
        o_cfg_rd_en       <=  1;
        if (i_cfg_rd_wr_done) begin
          case (index)
            0: begin
              o_bar_addr0 <=  i_cfg_do;
            end
            1: begin
              o_bar_addr1 <=  i_cfg_do;
            end
            2: begin
              o_bar_addr2 <=  i_cfg_do;
            end
            3: begin
              o_bar_addr3 <=  i_cfg_do;
            end
            4: begin
              o_bar_addr4 <=  i_cfg_do;
            end
            5: begin
              o_bar_addr5 <=  i_cfg_do;
            end
            default: begin
            end
          endcase
          state           <=  READ_NEXT;
        end
      end
      READ_NEXT: begin
        if (!i_cfg_rd_wr_done) begin
          if (index < `MAX_READ_COUNT + 1) begin
            state         <=  PREP_ADDR;
            index         <=  index + 1;
          end
          else begin
            o_finished    <=  1;
            if (!i_en) begin
              state       <=  IDLE;
            end
          end
        end
      end
      default: begin
        state             <=  IDLE;
      end
    endcase
  end
end


endmodule
module config_parser (
  input                     rst,
  input                     clk,

  input                     i_en,
  output  reg               o_finished,


  input       [31:0]        i_cfg_do,
  input                     i_cfg_rd_wr_done,
  output reg  [9:0]         o_cfg_dwaddr,
  output reg                o_cfg_rd_en,




  output  reg [31:0]        o_bar_addr0,
  output  reg [31:0]        o_bar_addr1,
  output  reg [31:0]        o_bar_addr2,
  output  reg [31:0]        o_bar_addr3,
  output  reg [31:0]        o_bar_addr4,
  output  reg [31:0]        o_bar_addr5
);




localparam  IDLE          = 4'h0;
localparam  PREP_ADDR     = 4'h1;
localparam  WAIT_STATE    = 4'h2;
localparam  READ_DATA     = 4'h3;
localparam  READ_NEXT     = 4'h4;



reg   [3:0]   state;
reg   [3:0]   index;
wire  [9:0]   w_cfg_addr[0:`MAX_READ_COUNT];




assign  w_cfg_addr[0] = `BAR_ADDR0 >> 2;
assign  w_cfg_addr[1] = `BAR_ADDR1 >> 2;
assign  w_cfg_addr[2] = `BAR_ADDR2 >> 2;
assign  w_cfg_addr[3] = `BAR_ADDR3 >> 2;
assign  w_cfg_addr[4] = `BAR_ADDR4 >> 2;
assign  w_cfg_addr[5] = `BAR_ADDR5 >> 2;




always @ (posedge clk) begin
  o_cfg_rd_en         <=  0;
  if (rst) begin
    state             <=  IDLE;
    index             <=  0;

    o_cfg_dwaddr      <=  w_cfg_addr[0];

    o_bar_addr0       <=  0;
    o_bar_addr1       <=  0;
    o_bar_addr2       <=  0;
    o_bar_addr3       <=  0;
    o_bar_addr4       <=  0;
    o_bar_addr5       <=  0;

    o_finished        <=  0;
  end
  else begin
    case (state)
      IDLE: begin
        o_finished        <=  0;
        index             <=  0;
        if (i_en) begin
          state           <=  PREP_ADDR;
        end
      end
      PREP_ADDR: begin
        case (index)
          0: begin

            o_cfg_dwaddr  <=  4;
          end
          1: begin

            o_cfg_dwaddr  <=  5;
          end
          2: begin

            o_cfg_dwaddr  <=  6;
          end
          3: begin

            o_cfg_dwaddr  <=  7;
          end
          4: begin

            o_cfg_dwaddr  <=  8;
          end
          5: begin

            o_cfg_dwaddr  <=  9;
          end
        endcase
        state             <=  WAIT_STATE;
      end
      WAIT_STATE: begin
        o_cfg_rd_en       <=  1;
        if (i_cfg_rd_wr_done) begin
          state           <=  READ_DATA;
        end
      end
      READ_DATA: begin
        o_cfg_rd_en       <=  1;
        if (i_cfg_rd_wr_done) begin
          case (index)
            0: begin
              o_bar_addr0 <=  i_cfg_do;
            end
            1: begin
              o_bar_addr1 <=  i_cfg_do;
            end
            2: begin
              o_bar_addr2 <=  i_cfg_do;
            end
            3: begin
              o_bar_addr3 <=  i_cfg_do;
            end
            4: begin
              o_bar_addr4 <=  i_cfg_do;
            end
            5: begin
              o_bar_addr5 <=  i_cfg_do;
            end
            default: begin
            end
          endcase
          state           <=  READ_NEXT;
        end
      end
      READ_NEXT: begin
        if (!i_cfg_rd_wr_done) begin
          if (index < `MAX_READ_COUNT + 1) begin
            state         <=  PREP_ADDR;
            index         <=  index + 1;
          end
          else begin
            o_finished    <=  1;
            if (!i_en) begin
              state       <=  IDLE;
            end
          end
        end
      end
      default: begin
        state             <=  IDLE;
      end
    endcase
  end
end


endmodule