data/full_repos/permissive/42434302/ivltests/pr1936363.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:5: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:9: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1936363.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tern;

reg [13:0] fdbk_err_wide;
initial begin
	#10;
	$display(fdbk_err_wide, fdbk_err);


	#10;
	fdbk_err_wide = 42;
	#10;
	$display(fdbk_err_wide, fdbk_err);

	#10;
	fdbk_err_wide = 14'bxxxxxxxxxxxxxx;
	#10;

	$display(fdbk_err_wide, fdbk_err);
	#10;
	$finish();
end


wire [11:0] fdbk_err = ((fdbk_err_wide[13:12]==2'b00) | (fdbk_err_wide[13:12]==2'b11)) ?
       fdbk_err_wide[12:1] : {fdbk_err_wide[13],{11{~fdbk_err_wide[13]}}};

endmodule
module tern;


reg [13:0] fdbk_err_wide;
initial begin
	#10;
	$display(fdbk_err_wide, fdbk_err);


	#10;
	fdbk_err_wide = 42;
	#10;
	$display(fdbk_err_wide, fdbk_err);

	#10;
	fdbk_err_wide = 14'bxxxxxxxxxxxxxx;
	#10;

	$display(fdbk_err_wide, fdbk_err);
	#10;
	$finish();
end


wire [11:0] fdbk_err = ((fdbk_err_wide[13:12]==2'b00) | (fdbk_err_wide[13:12]==2'b11)) ?
       fdbk_err_wide[12:1] : {fdbk_err_wide[13],{11{~fdbk_err_wide[13]}}};

endmodule