data/full_repos/permissive/487568919/basic_verilog/benchmark_projects/gowin_benchmark/src/main.sv
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/benchmark_projects/gowin_benchmark/src/main.sv:29: Cannot find file containing module: 'dynamic_delay'\ndynamic_delay #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/benchmark_projects/gowin_benchmark/src,data/full_repos/permissive/487568919/dynamic_delay\n             data/full_repos/permissive/487568919/basic_verilog/benchmark_projects/gowin_benchmark/src,data/full_repos/permissive/487568919/dynamic_delay.v\n             data/full_repos/permissive/487568919/basic_verilog/benchmark_projects/gowin_benchmark/src,data/full_repos/permissive/487568919/dynamic_delay.sv\n             dynamic_delay\n             dynamic_delay.v\n             dynamic_delay.sv\n             obj_dir/dynamic_delay\n             obj_dir/dynamic_delay.v\n             obj_dir/dynamic_delay.sv\n%Error: Exiting due to 1 error(s)\n"
module main(

  input clk,
  input nrst,

  input [`WIDTH-1:0] id,
  input [`SEL_W-1:0] sel,
  output [`WIDTH-1:0] od
);

dynamic_delay #(
  .LENGTH( `LENGTH ),
  .WIDTH( 1 ),
  .SEL_W( `SEL_W )
) dd [`WIDTH-1:0] (
  .clk( {`WIDTH{clk}} ),
  .nrst( {`WIDTH{nrst}} ),
  .ena( {`WIDTH{1'b1}} ),
  .in( id[`WIDTH-1:0] ),
  .sel( {`WIDTH{sel[`SEL_W-1:0]}} ),
  .out( od[`WIDTH-1:0] )
);

endmodule
module main(

  input clk,
  input nrst,

  input [`WIDTH-1:0] id,
  input [`SEL_W-1:0] sel,
  output [`WIDTH-1:0] od
);


dynamic_delay #(
  .LENGTH( `LENGTH ),
  .WIDTH( 1 ),
  .SEL_W( `SEL_W )
) dd [`WIDTH-1:0] (
  .clk( {`WIDTH{clk}} ),
  .nrst( {`WIDTH{nrst}} ),
  .ena( {`WIDTH{1'b1}} ),
  .in( id[`WIDTH-1:0] ),
  .sel( {`WIDTH{sel[`SEL_W-1:0]}} ),
  .out( od[`WIDTH-1:0] )
);

endmodule