data/full_repos/permissive/514437299/digital/rtl/rf.v
data/verilator_xmls/f9f96bce-2ef4-43d5-9b38-a353dcdcb91c.xml
module rf(
  input wire        clk,
  input wire        rst_n,
  input wire  [8:0] i_rf_waddr,
  input wire  [1:0] i_rf_wdata,
  input wire        i_rf_wen,
  input wire  [8:0] i_rf_raddr,
  output wire [1:0] o_rf_rdata);



endmodule
module rf(
  input wire        clk,
  input wire        rst_n,
  input wire  [8:0] i_rf_waddr,
  input wire  [1:0] i_rf_wdata,
  input wire        i_rf_wen,
  input wire  [8:0] i_rf_raddr,
  output wire [1:0] o_rf_rdata);




endmodule