data/full_repos/permissive/494696040/Instruction_Fetch_Module.v
data/verilator_xmls/ef8fa199-6104-4c8a-a3e8-6d654ff259f9.xml
module Instruction_Fetch_Module(
    input RESET,
    input CLK,

    input wire [31:0] PC_in,
    output reg [31:0]  IR,
    output wire [31:0] adder_output
    );
    reg [31:0] PC;
    wire [31:0] PC_out;

    wire [31:0] read_address;
    wire [31:0] instruction;
    
    reg [31:0] instruction_memory [0:4096];



    assign adder_output = PC_out + 32'h00000004;





    assign PC_out = PC;


    initial begin
        PC <= 32'h00000000;
    end
    

    always @(posedge CLK)
    begin

        if (RESET) PC <= 32'h00000000;

        else
        begin



            PC <= PC_in;
        end
    end





    assign read_address = PC_out;
    assign instruction =  instruction_memory[read_address >> 2];




    always @(negedge CLK)
    begin
        IR <= instruction;
    end








    initial begin

        instruction_memory[0] <= {6'd0, 5'd0, 5'd0, 5'd1, 5'd0, 6'h20};



        instruction_memory[1] <= {6'h23, 5'd0, 5'd2, 16'd4};

        instruction_memory[2] <= {6'h23, 5'd0, 5'd3, 16'd8};

        instruction_memory[3] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h20};

        instruction_memory[4] <= {6'h2b, 5'd0, 5'd4, 16'd12};
 


        instruction_memory[5] <= {6'h23, 5'd0, 5'd2, 16'd12};

        instruction_memory[6] <= {6'h23, 5'd0, 5'd3, 16'd16};

        instruction_memory[7] <= {6'd0, 5'd2, 5'd3, 5'd5, 5'd0, 6'h22};



        instruction_memory[8] <= {6'h23, 5'd0, 5'd2, 16'd20};

        instruction_memory[9] <= {6'h23, 5'd0, 5'd3, 16'd24};

        instruction_memory[10] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h24};


        instruction_memory[11] <= {6'd0, 5'd2, 5'd3, 5'd5, 5'd0, 6'h25};


        instruction_memory[12] <= {6'd0, 5'd4, 5'd5, 5'd6, 5'd0, 6'h2a};

        instruction_memory[13] <= {6'd0, 5'd5, 5'd4, 5'd6, 5'd0, 6'h2a};




        instruction_memory[14] <= {6'h23, 5'd0, 5'd3, 16'd20};


        instruction_memory[15] <= {6'h4, 5'd2, 5'd4, 16'd5};


        instruction_memory[16] <= {6'h4, 5'd2, 5'd3, 16'd4};
        

        instruction_memory[17] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[18] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[19] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[20] <= {6'h23, 5'd0, 5'd4, 16'd20};
        


        instruction_memory[21] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h22};



        instruction_memory[22] <= {6'h2, 26'd5};
    end




endmodule
module Instruction_Fetch_Module(
    input RESET,
    input CLK,

    input wire [31:0] PC_in,
    output reg [31:0]  IR,
    output wire [31:0] adder_output
    );

    reg [31:0] PC;
    wire [31:0] PC_out;

    wire [31:0] read_address;
    wire [31:0] instruction;
    
    reg [31:0] instruction_memory [0:4096];



    assign adder_output = PC_out + 32'h00000004;





    assign PC_out = PC;


    initial begin
        PC <= 32'h00000000;
    end
    

    always @(posedge CLK)
    begin

        if (RESET) PC <= 32'h00000000;

        else
        begin



            PC <= PC_in;
        end
    end





    assign read_address = PC_out;
    assign instruction =  instruction_memory[read_address >> 2];




    always @(negedge CLK)
    begin
        IR <= instruction;
    end








    initial begin

        instruction_memory[0] <= {6'd0, 5'd0, 5'd0, 5'd1, 5'd0, 6'h20};



        instruction_memory[1] <= {6'h23, 5'd0, 5'd2, 16'd4};

        instruction_memory[2] <= {6'h23, 5'd0, 5'd3, 16'd8};

        instruction_memory[3] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h20};

        instruction_memory[4] <= {6'h2b, 5'd0, 5'd4, 16'd12};
 


        instruction_memory[5] <= {6'h23, 5'd0, 5'd2, 16'd12};

        instruction_memory[6] <= {6'h23, 5'd0, 5'd3, 16'd16};

        instruction_memory[7] <= {6'd0, 5'd2, 5'd3, 5'd5, 5'd0, 6'h22};



        instruction_memory[8] <= {6'h23, 5'd0, 5'd2, 16'd20};

        instruction_memory[9] <= {6'h23, 5'd0, 5'd3, 16'd24};

        instruction_memory[10] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h24};


        instruction_memory[11] <= {6'd0, 5'd2, 5'd3, 5'd5, 5'd0, 6'h25};


        instruction_memory[12] <= {6'd0, 5'd4, 5'd5, 5'd6, 5'd0, 6'h2a};

        instruction_memory[13] <= {6'd0, 5'd5, 5'd4, 5'd6, 5'd0, 6'h2a};




        instruction_memory[14] <= {6'h23, 5'd0, 5'd3, 16'd20};


        instruction_memory[15] <= {6'h4, 5'd2, 5'd4, 16'd5};


        instruction_memory[16] <= {6'h4, 5'd2, 5'd3, 16'd4};
        

        instruction_memory[17] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[18] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[19] <= {6'h23, 5'd0, 5'd4, 16'd20};
        instruction_memory[20] <= {6'h23, 5'd0, 5'd4, 16'd20};
        


        instruction_memory[21] <= {6'd0, 5'd2, 5'd3, 5'd4, 5'd0, 6'h22};



        instruction_memory[22] <= {6'h2, 26'd5};
    end




endmodule