data/full_repos/permissive/482006041/6-1/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:6: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("wave.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:7: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0, tb);\n       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n       #500 $finish;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst_n = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-1/user/sim/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_100MHz <= ~clk_100MHz;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb ();

    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #500 $finish;
    end

    reg rst_n = 1;
    initial begin
        #10 rst_n = 0;
        #10 rst_n = 1;
    end

    reg clk_100MHz = 0;
    always 
        #5 clk_100MHz <= ~clk_100MHz;

    wire 	clk_10MHz;
    wire 	clk_6667KHz;

    clock_div u_clock_div(

        .reset       		( rst_n       		),
        .clk_100MHz  		( clk_100MHz  		),
        .clk_10MHz   		( clk_10MHz   		),
        .clk_6667KHz 		( clk_6667KHz 		)
    );











endmodule
module tb ();


    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #500 $finish;
    end

    reg rst_n = 1;
    initial begin
        #10 rst_n = 0;
        #10 rst_n = 1;
    end

    reg clk_100MHz = 0;
    always 
        #5 clk_100MHz <= ~clk_100MHz;

    wire 	clk_10MHz;
    wire 	clk_6667KHz;

    clock_div u_clock_div(

        .reset       		( rst_n       		),
        .clk_100MHz  		( clk_100MHz  		),
        .clk_10MHz   		( clk_10MHz   		),
        .clk_6667KHz 		( clk_6667KHz 		)
    );











endmodule