data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/MEM.v
1: b"%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/MEM.v:22: Cannot find file containing module: 'data_memory'\n    data_memory data_memory1(clk, MemRead, MemWrite, REG_DATA2[11:2], ALU_out, DATA_MEMORY_out);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/data_memory\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/data_memory.v\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/data_memory.sv\n             data_memory\n             data_memory.v\n             data_memory.sv\n             obj_dir/data_memory\n             obj_dir/data_memory.v\n             obj_dir/data_memory.sv\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/MEM.v:23: Cannot find file containing module: 'Branch'\n    Branch branch1(Branch, zero_flag, PC_Src);\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module MEM(
    input clk,
    input MemRead,
    input MemtoReg,
    input MemWrite,
    input RegWrite,
    input Branch,
    input zero_flag,
    input [31:0] PC,
    input [31:0] ALU_out,
    input [31:0] REG_DATA2,
    input [4:0] RD,
    output RegWrite_out,
    output MemtoReg_out,
    output [31:0] DATA_MEMORY_out,
    output [31:0] ALU_out_WB,
    output [4:0] RD_out,
    output PC_Src
    );
    data_memory data_memory1(clk, MemRead, MemWrite, REG_DATA2[11:2], ALU_out, DATA_MEMORY_out);
    Branch branch1(Branch, zero_flag, PC_Src);
    
    assign RegWrite_out = RegWrite;
    assign MemtoReg_out = MemtoReg;
    assign ALU_out_WB = ALU_out;
    assign RD_out = RD;
endmodule
module MEM(
    input clk,
    input MemRead,
    input MemtoReg,
    input MemWrite,
    input RegWrite,
    input Branch,
    input zero_flag,
    input [31:0] PC,
    input [31:0] ALU_out,
    input [31:0] REG_DATA2,
    input [4:0] RD,
    output RegWrite_out,
    output MemtoReg_out,
    output [31:0] DATA_MEMORY_out,
    output [31:0] ALU_out_WB,
    output [4:0] RD_out,
    output PC_Src
    );

    data_memory data_memory1(clk, MemRead, MemWrite, REG_DATA2[11:2], ALU_out, DATA_MEMORY_out);
    Branch branch1(Branch, zero_flag, PC_Src);
    
    assign RegWrite_out = RegWrite;
    assign MemtoReg_out = MemtoReg;
    assign ALU_out_WB = ALU_out;
    assign RD_out = RD;
endmodule