data/full_repos/permissive/470803657/modules/alu.v
data/verilator_xmls/dfe57ea7-ce7e-4b8e-b067-2629a3beb05b.xml
module alu (input  wire [7:0] in_a,
            input  wire [7:0] in_b,
            input  wire       add_sub,
            output wire [7:0] out_alu);

assign out_alu = add_sub ? in_a - in_b : in_a + in_b;

endmodule
module alu (input  wire [7:0] in_a,
            input  wire [7:0] in_b,
            input  wire       add_sub,
            output wire [7:0] out_alu);


assign out_alu = add_sub ? in_a - in_b : in_a + in_b;

endmodule