data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/ALU.v
data/verilator_xmls/861678e0-dae9-41c6-80ab-4d136eee7b61.xml
module ALU(
    input [2:0] ALUSel,
    input [31:0] ALUIn1,
    input [31:0] ALUIn2,
    input [4:0] shamt,
    output reg [31:0] ALUOut 
    );
    
    always @(ALUSel or ALUIn1 or ALUIn2) begin
        if(ALUSel == 3'b010) begin
            ALUOut <= ALUIn1 + ALUIn2;
        end
        else if (ALUSel == 3'b110) begin
           ALUOut <= ALUIn1 - ALUIn2;
        end
        else if (ALUSel == 3'b011) begin
            ALUOut <= ALUIn2 << shamt;
        end
        else if (ALUSel == 3'b100) begin
            ALUOut <= ALUIn2 << ALUIn1;
        end
        else if (ALUSel == 3'b101) begin
            ALUOut <= ALUIn2 >>> ALUIn1;
        end
    end
endmodule
module ALU(
    input [2:0] ALUSel,
    input [31:0] ALUIn1,
    input [31:0] ALUIn2,
    input [4:0] shamt,
    output reg [31:0] ALUOut 
    );

    
    always @(ALUSel or ALUIn1 or ALUIn2) begin
        if(ALUSel == 3'b010) begin
            ALUOut <= ALUIn1 + ALUIn2;
        end
        else if (ALUSel == 3'b110) begin
           ALUOut <= ALUIn1 - ALUIn2;
        end
        else if (ALUSel == 3'b011) begin
            ALUOut <= ALUIn2 << shamt;
        end
        else if (ALUSel == 3'b100) begin
            ALUOut <= ALUIn2 << ALUIn1;
        end
        else if (ALUSel == 3'b101) begin
            ALUOut <= ALUIn2 >>> ALUIn1;
        end
    end
endmodule