data/full_repos/permissive/423539813/source_files/register_file.v
data/verilator_xmls/ebaab92c-9ccc-40a9-ac04-685e2014bfb0.xml
module register_file(Port_A, Port_B, hardwire, RESULT, Addr_A, Addr_B, Addr_Wr, wr, clk,rst);
output reg [31:0] Port_A, Port_B,hardwire; 
input [31:0] RESULT; 
input [4:0] Addr_A, Addr_B, Addr_Wr; 
input wr, clk,rst; 
reg [31:0] Reg_File [31:0]; 
always @ (*) begin
Reg_File[0] <= 0;
Port_A <= Reg_File[Addr_A[4:0]];
Port_B <= Reg_File[Addr_B[4:0]];
hardwire= Reg_File[8];
end
 always @(posedge clk) begin
 if(wr)
    Reg_File[Addr_Wr]=RESULT[31:0];
 end
endmodule
module register_file(Port_A, Port_B, hardwire, RESULT, Addr_A, Addr_B, Addr_Wr, wr, clk,rst);

output reg [31:0] Port_A, Port_B,hardwire; 
input [31:0] RESULT; 
input [4:0] Addr_A, Addr_B, Addr_Wr; 
input wr, clk,rst; 
reg [31:0] Reg_File [31:0]; 
always @ (*) begin
Reg_File[0] <= 0;
Port_A <= Reg_File[Addr_A[4:0]];
Port_B <= Reg_File[Addr_B[4:0]];
hardwire= Reg_File[8];
end
 always @(posedge clk) begin
 if(wr)
    Reg_File[Addr_Wr]=RESULT[31:0];
 end
endmodule