data/full_repos/permissive/520038878/rtl/segment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/520038878/rtl/segment.v:58: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance sevenSeg.s1\n assign segment_led = dis ? 8\'h0 : {data[4], seg[data[3:0]]};\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/520038878/rtl/segment.v:58: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                     : ... In instance sevenSeg.s1\n assign segment_led = dis ? 8\'h0 : {data[4], seg[data[3:0]]};\n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module a_segment (
		input wire dis,
		input wire [4:0] data,
		output wire [8:0] segment_led
	);
	
	reg [6:0] seg [15:0];
	initial begin
		seg[0] = 7'h3f;
		seg[1] = 7'h06;
		seg[2] = 7'h5b;
		seg[3] = 7'h4f;
		seg[4] = 7'h66;
		seg[5] = 7'h6d;
		seg[6] = 7'h7d;
		seg[7] = 7'h07;
		seg[8] = 7'h7f;
		seg[9] = 7'h6f;
		seg[10]= 7'h77;
		seg[11]= 7'h7C;
		seg[12]= 7'h39;
		seg[13]= 7'h5e;
		seg[14]= 7'h79;
		seg[15]= 7'h71;
	end
	assign segment_led = dis ? 8'h0 : {data[4], seg[data[3:0]]};
endmodule
module a_segment (
		input wire dis,
		input wire [4:0] data,
		output wire [8:0] segment_led
	);

	
	reg [6:0] seg [15:0];
	initial begin
		seg[0] = 7'h3f;
		seg[1] = 7'h06;
		seg[2] = 7'h5b;
		seg[3] = 7'h4f;
		seg[4] = 7'h66;
		seg[5] = 7'h6d;
		seg[6] = 7'h7d;
		seg[7] = 7'h07;
		seg[8] = 7'h7f;
		seg[9] = 7'h6f;
		seg[10]= 7'h77;
		seg[11]= 7'h7C;
		seg[12]= 7'h39;
		seg[13]= 7'h5e;
		seg[14]= 7'h79;
		seg[15]= 7'h71;
	end
	assign segment_led = dis ? 8'h0 : {data[4], seg[data[3:0]]};
endmodule