data/full_repos/permissive/411831376/Futaba.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/411831376/Futaba.v:63: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'Futaba\'\nmodule Futaba( output reg TCLKQ,\n       ^~~~~~\n                                                                   : ... Top module \'DTT\'\nmodule DTT #(parameter N = 1) (output reg [N-1:0]Q, input [N-1:0]D, input C, aR);\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/411831376/Futaba.v:71: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'E\' generates 1 bits.\n                                                                : ... In instance Futaba.DC\n assign Y = E << X;\n              ^~\n%Error: data/full_repos/permissive/411831376/Futaba.v:30: Cannot find file containing module: \'CD\'\n CD CD( .a(CDa),\n ^~\n        ... Looked in:\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD.v\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD.sv\n             CD\n             CD.v\n             CD.sv\n             obj_dir/CD\n             obj_dir/CD.v\n             obj_dir/CD.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module DC #(parameter N = 0) (output [(2**N)-1:0]Y, input [N-1:0]X, input E);
	assign Y = E << X;
endmodule
module DC #(parameter N = 0) (output [(2**N)-1:0]Y, input [N-1:0]X, input E);

	assign Y = E << X;
endmodule