data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/div/div_q.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/div/div_q.v:24: Cannot find file containing module: 'DW_div'\n  DW_div #(width, width, tc_mode, rem_mode)\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/div,data/full_repos/permissive/486954482/DW_div\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/div,data/full_repos/permissive/486954482/DW_div.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/div,data/full_repos/permissive/486954482/DW_div.sv\n             DW_div\n             DW_div.v\n             DW_div.sv\n             obj_dir/DW_div\n             obj_dir/DW_div.v\n             obj_dir/DW_div.sv\n%Error: Exiting due to 1 error(s)\n"
module div_q(g_input, e_input, o);
  parameter width    = 32;
  parameter tc_mode  = 0;
  parameter rem_mode = 1;

  input  [width-1 : 0] g_input;
  input  [width-1 : 0] e_input;
  output [width-1:0  ] o;

  wire   [width-1 : 0] quotient;
  wire   [width-1 : 0] remainder;

  assign o = quotient;
  


  DW_div #(width, width, tc_mode, rem_mode)
    U1 (.a(g_input), .b(e_input),
        .quotient(quotient), .remainder(remainder));

endmodule
module div_q(g_input, e_input, o);

  parameter width    = 32;
  parameter tc_mode  = 0;
  parameter rem_mode = 1;

  input  [width-1 : 0] g_input;
  input  [width-1 : 0] e_input;
  output [width-1:0  ] o;

  wire   [width-1 : 0] quotient;
  wire   [width-1 : 0] remainder;

  assign o = quotient;
  


  DW_div #(width, width, tc_mode, rem_mode)
    U1 (.a(g_input), .b(e_input),
        .quotient(quotient), .remainder(remainder));

endmodule