data/full_repos/permissive/445357518/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445357518/cpu.v:43: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                             : ... In instance cpu\n assign pc = {8\'b0, PC};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445357518/cpu.v:45: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.sv\n             vDFF1\n             vDFF1.v\n             vDFF1.sv\n             obj_dir/vDFF1\n             obj_dir/vDFF1.v\n             obj_dir/vDFF1.sv\n%Error: data/full_repos/permissive/445357518/cpu.v:54: Cannot find file containing module: \'datapath\'\n datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)\n ^~~~~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:64: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);\n ^~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:73: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);\n ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module vDFF2(clk,D,Q);
  parameter n=1;
  input clk;
  input [n-1:0] D;
  output [n-1:0] Q;
  reg [n-1:0] Q;


  always @(posedge clk)
    Q <= D;
endmodule
module vDFF2(clk,D,Q);

  parameter n=1;
  input clk;
  input [n-1:0] D;
  output [n-1:0] Q;
  reg [n-1:0] Q;


  always @(posedge clk)
    Q <= D;
endmodule