data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control_write_pixel.sv
1: b"%Error: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control_write_pixel.sv:29: Cannot find file containing module: 'vga_sync_fifo'\n vga_sync_fifo #(35, 64, 6) VRAMWRITE_FIFO(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_sync_fifo\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_sync_fifo.v\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_sync_fifo.sv\n             vga_sync_fifo\n             vga_sync_fifo.v\n             vga_sync_fifo.sv\n             obj_dir/vga_sync_fifo\n             obj_dir/vga_sync_fifo.v\n             obj_dir/vga_sync_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module vga_vram_control_write_pixel(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC_IF,

		input wire iPIXEL_REQ,
		input wire [18:0] iPIXEL_ADDR,
		input wire [15:0] iPIXEL_DATA,
		output wire oPIXEL_FULL,

		output wire oMEM_REQ,
		output wire [18:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY
	);


	wire writefifo_empty;
	wire writefifo_almost_empty;
	wire [18:0] writefifo_addr;
	wire [15:0] writefifo_data;

	vga_sync_fifo #(35, 64, 6) VRAMWRITE_FIFO(
		.inRESET(inRESET),
		.iCLOCK(iCLOCK),
		.iREMOVE(iRESET_SYNC_IF),
		.oCOUNT(),
		.iWR_EN(iPIXEL_REQ),
		.iWR_DATA({iPIXEL_ADDR, iPIXEL_DATA}),
		.oWR_FULL(oPIXEL_FULL),

		.iRD_EN(!iMEM_BUSY && !writefifo_empty),
		.oRD_DATA({writefifo_addr, writefifo_data}),
		.oRD_EMPTY(writefifo_empty),
		.oRD_ALMOST_EMPTY(writefifo_almost_empty)
	);


	assign oMEM_REQ = !writefifo_empty;
	assign oMEM_ADDR = writefifo_addr;
	assign oMEM_DATA = writefifo_data;


endmodule
module vga_vram_control_write_pixel(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC_IF,

		input wire iPIXEL_REQ,
		input wire [18:0] iPIXEL_ADDR,
		input wire [15:0] iPIXEL_DATA,
		output wire oPIXEL_FULL,

		output wire oMEM_REQ,
		output wire [18:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY
	);



	wire writefifo_empty;
	wire writefifo_almost_empty;
	wire [18:0] writefifo_addr;
	wire [15:0] writefifo_data;

	vga_sync_fifo #(35, 64, 6) VRAMWRITE_FIFO(
		.inRESET(inRESET),
		.iCLOCK(iCLOCK),
		.iREMOVE(iRESET_SYNC_IF),
		.oCOUNT(),
		.iWR_EN(iPIXEL_REQ),
		.iWR_DATA({iPIXEL_ADDR, iPIXEL_DATA}),
		.oWR_FULL(oPIXEL_FULL),

		.iRD_EN(!iMEM_BUSY && !writefifo_empty),
		.oRD_DATA({writefifo_addr, writefifo_data}),
		.oRD_EMPTY(writefifo_empty),
		.oRD_ALMOST_EMPTY(writefifo_almost_empty)
	);


	assign oMEM_REQ = !writefifo_empty;
	assign oMEM_ADDR = writefifo_addr;
	assign oMEM_DATA = writefifo_data;


endmodule