data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Latches and Flip-Flops/Dual-edge triggered flip-flop.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Dual-edge\n%Error: Cannot find file containing module: triggered\n%Error: Cannot find file containing module: flip-flop.v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input d,
    output q
);
    reg pedge, nedge;

    always @(posedge clk) begin
        pedge <= d;
    end

    always @(negedge clk) begin
        nedge <= d;
    end

    assign q = clk ? pedge : nedge;
endmodule
module top_module (
    input clk,
    input d,
    output q
);

    reg pedge, nedge;

    always @(posedge clk) begin
        pedge <= d;
    end

    always @(negedge clk) begin
        nedge <= d;
    end

    assign q = clk ? pedge : nedge;
endmodule