data/full_repos/permissive/501791642/ISE_devel/uart_rx_test.v
1: b"%Error: data/full_repos/permissive/501791642/ISE_devel/uart_rx_test.v:11: Cannot find file containing module: 'uart_rx'\nuart_rx uart (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx.v\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: Exiting due to 1 error(s)\n"
module uart_rx_test (
	input CLK,
	input DI,
	output reg [7:0] PO = 0
);

wire dv;

wire [7:0] uart_out;

uart_rx uart (
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.DI(DI),
	.DV(dv),
	.PO(uart_out)
);

always @(posedge CLK)
	if (dv)
		PO <= uart_out;
		

endmodule
module uart_rx_test (
	input CLK,
	input DI,
	output reg [7:0] PO = 0
);


wire dv;

wire [7:0] uart_out;

uart_rx uart (
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.DI(DI),
	.DV(dv),
	.PO(uart_out)
);

always @(posedge CLK)
	if (dv)
		PO <= uart_out;
		

endmodule