data/full_repos/permissive/48602886/src/device/mmc/mmc_spi_initial_clock.sv
data/verilator_xmls/95cadb5a-df30-4af4-ad9a-3272b1220591.xml
module mmc_spi_initial_clock(
		input wire iMMC_CLOCK,
		input wire iMMC_RESET_SYNC,
		input wire inRESET,
		output wire oMMC_INIT_CLOCK
	);

	reg [4:0] b_counter;
	always@(posedge iMMC_CLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_counter <= 5'h0;
		end
		else if(iMMC_RESET_SYNC) begin
			b_counter <= 5'h0;
		end
		else begin
			b_counter <= b_counter + 5'h1;
		end
	end

	reg b_initial_clock;
	always@(posedge iMMC_CLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_initial_clock <= 1'b0;
		end
		else if(iMMC_RESET_SYNC) begin
			b_initial_clock <= 1'b0;
		end
		else begin
			if(b_counter == 5'h0)begin
				b_initial_clock <= !b_initial_clock;
			end
		end
	end

	assign oMMC_INIT_CLOCK = b_initial_clock;


endmodule
module mmc_spi_initial_clock(
		input wire iMMC_CLOCK,
		input wire iMMC_RESET_SYNC,
		input wire inRESET,
		output wire oMMC_INIT_CLOCK
	);


	reg [4:0] b_counter;
	always@(posedge iMMC_CLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_counter <= 5'h0;
		end
		else if(iMMC_RESET_SYNC) begin
			b_counter <= 5'h0;
		end
		else begin
			b_counter <= b_counter + 5'h1;
		end
	end

	reg b_initial_clock;
	always@(posedge iMMC_CLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_initial_clock <= 1'b0;
		end
		else if(iMMC_RESET_SYNC) begin
			b_initial_clock <= 1'b0;
		end
		else begin
			if(b_counter == 5'h0)begin
				b_initial_clock <= !b_initial_clock;
			end
		end
	end

	assign oMMC_INIT_CLOCK = b_initial_clock;


endmodule