data/full_repos/permissive/501791642/sim/midi_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK = ~CLK; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'h90;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d69;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'h80;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d70;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d50;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #20 DATA = 8\'h80;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d69;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d50;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #20 DATA = 8\'hc0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d127;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d50;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'hc0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d30;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d50;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'hff;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d30;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'h90;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d69;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #20 DATA = 8\'d100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #2 DV = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/midi_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #2  DV = 0;\n ^\n%Error: data/full_repos/permissive/501791642/sim/midi_tb.v:26: Cannot find file containing module: \'midi\'\nmidi midi1(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/midi\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/midi.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/midi.sv\n             midi\n             midi.v\n             midi.sv\n             obj_dir/midi\n             obj_dir/midi.v\n             obj_dir/midi.sv\n%Error: Exiting due to 1 error(s), 64 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module midi_tb;

reg CLK;
reg CE;
reg DV;
reg RST;
reg [7:0] DATA;
wire [6:0] NOTE_NUM;
wire [6:0] NOTE_VEL;
wire [6:0] PROGRAM;



initial begin
    CLK = 0;
    CE = 1;
	RST = 0;
	DV = 0;
	DATA = 0;
end

always #1 CLK = ~CLK; 

midi midi1(
	.CLK(CLK),
	.CE(CE),
	.RST(RST),
	.data(DATA),
	.dv(DV),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM)
);

initial begin

	#20 DATA = 8'h90;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd100;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'h80;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd70;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;

    #20 DATA = 8'h80;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;

    #20 DATA = 8'hc0;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd127;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'hc0;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd30;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'hff;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd30;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	

	#20 DATA = 8'h90;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd100;
	#2	DV = 1;
	#2 	DV = 0;



end


endmodule
module midi_tb;


reg CLK;
reg CE;
reg DV;
reg RST;
reg [7:0] DATA;
wire [6:0] NOTE_NUM;
wire [6:0] NOTE_VEL;
wire [6:0] PROGRAM;



initial begin
    CLK = 0;
    CE = 1;
	RST = 0;
	DV = 0;
	DATA = 0;
end

always #1 CLK = ~CLK; 

midi midi1(
	.CLK(CLK),
	.CE(CE),
	.RST(RST),
	.data(DATA),
	.dv(DV),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM)
);

initial begin

	#20 DATA = 8'h90;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd100;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'h80;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd70;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;

    #20 DATA = 8'h80;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;

    #20 DATA = 8'hc0;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd127;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'hc0;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd30;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	
	#20 DATA = 8'hff;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd30;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd50;
	#2	DV = 1;
	#2 	DV = 0;
	

	#20 DATA = 8'h90;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd69;
	#2	DV = 1;
	#2 	DV = 0;
	#20	DATA = 8'd100;
	#2	DV = 1;
	#2 	DV = 0;



end


endmodule