data/full_repos/permissive/458208177/hdl/mux_2_1.v
data/verilator_xmls/ba868854-a3d3-42f5-8063-28daa7f1efde.xml
module mux_2_1(
    output              Y,

    input               A, B,
    input               select
);

assign Y = select ? B : A;

endmodule
module mux_2_1(
    output              Y,

    input               A, B,
    input               select
);


assign Y = select ? B : A;

endmodule