data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/modules/dut/BASIC/v_rtl/dut_Add_9Sx8U_10S_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/modules/dut/BASIC/v_rtl/dut_Add_9Sx8U_10S_1.v:36: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in1\' generates 8 bits.\n                                                                                                                                : ... In instance dut_Add_9Sx8U_10S_1\n +(in1);\n ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dut_Add_9Sx8U_10S_1 (
	in2,
	in1,
	out1
	);
input [8:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;

assign asc001 = 
	+({in2[8], in2})
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_9Sx8U_10S_1 (
	in2,
	in1,
	out1
	);

input [8:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;

assign asc001 = 
	+({in2[8], in2})
	+(in1);

assign out1 = asc001;
endmodule