data/full_repos/permissive/472097485/Chu05/DebounceTest_00/DualEdgeMoore.v
data/verilator_xmls/2359b126-5bfa-4682-880a-a5683d738573.xml
module DualEdgeMoore( input clk, input reset, input sig, output ege );




	
	reg in, out;
	wire next_in, next_out;


	always @( posedge clk, posedge reset )
	begin
		if( reset )
		begin
			in = sig;
			out = 1'b0;
		end
		else
		begin
			in = next_in;
			out = next_out;
		end
	end
	

	assign next_in = sig;
	assign next_out = ~out && in != next_in;
	

	assign ege = out;

endmodule
module DualEdgeMoore( input clk, input reset, input sig, output ege );





	
	reg in, out;
	wire next_in, next_out;


	always @( posedge clk, posedge reset )
	begin
		if( reset )
		begin
			in = sig;
			out = 1'b0;
		end
		else
		begin
			in = next_in;
			out = next_out;
		end
	end
	

	assign next_in = sig;
	assign next_out = ~out && in != next_in;
	

	assign ege = out;

endmodule