data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_wb_ram.v
1: b'%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_wb_ram.v:57: Unsupported or unknown PLI call: $from_myhdl\n    $from_myhdl(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_wb_ram.v:68: Unsupported or unknown PLI call: $to_myhdl\n    $to_myhdl(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_wb_ram.v:74: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test_wb_ram.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_wb_ram.v:75: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test_wb_ram);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_wb_ram;


parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;


reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;


wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;

initial begin

    $from_myhdl(
        clk,
        rst,
        current_test,
        adr_i,
        dat_i,
        we_i,
        sel_i,
        stb_i,
        cyc_i
    );
    $to_myhdl(
        dat_o,
        ack_o
    );


    $dumpfile("test_wb_ram.lxt");
    $dumpvars(0, test_wb_ram);
end

wb_ram #(
    .DATA_WIDTH(DATA_WIDTH),
    .ADDR_WIDTH(ADDR_WIDTH),
    .SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
    .clk(clk),
    .adr_i(adr_i),
    .dat_i(dat_i),
    .dat_o(dat_o),
    .we_i(we_i),
    .sel_i(sel_i),
    .stb_i(stb_i),
    .ack_o(ack_o),
    .cyc_i(cyc_i)
);

endmodule
module test_wb_ram;



parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;


reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;


wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;

initial begin

    $from_myhdl(
        clk,
        rst,
        current_test,
        adr_i,
        dat_i,
        we_i,
        sel_i,
        stb_i,
        cyc_i
    );
    $to_myhdl(
        dat_o,
        ack_o
    );


    $dumpfile("test_wb_ram.lxt");
    $dumpvars(0, test_wb_ram);
end

wb_ram #(
    .DATA_WIDTH(DATA_WIDTH),
    .ADDR_WIDTH(ADDR_WIDTH),
    .SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
    .clk(clk),
    .adr_i(adr_i),
    .dat_i(dat_i),
    .dat_o(dat_o),
    .we_i(we_i),
    .sel_i(sel_i),
    .stb_i(stb_i),
    .ack_o(ack_o),
    .cyc_i(cyc_i)
);

endmodule