data/full_repos/permissive/440575220/miriscv_lsu.v
1: b'%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:1: Cannot find include file: miriscv_defines.v\n`include "miriscv_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440575220,data/full_repos/permissive/440575220/miriscv_defines.v\n             data/full_repos/permissive/440575220,data/full_repos/permissive/440575220/miriscv_defines.v.v\n             data/full_repos/permissive/440575220,data/full_repos/permissive/440575220/miriscv_defines.v.sv\n             miriscv_defines.v\n             miriscv_defines.v.v\n             miriscv_defines.v.sv\n             obj_dir/miriscv_defines.v\n             obj_dir/miriscv_defines.v.v\n             obj_dir/miriscv_defines.v.sv\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:42: Define or directive not defined: \'`LDST_B\'\n           `LDST_B: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:42: syntax error, unexpected \':\', expecting endcase\n           `LDST_B: begin  \n                  ^\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:53: Define or directive not defined: \'`LDST_H\'\n           `LDST_H: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `LDST_H: begin  \n                    ^~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:61: Define or directive not defined: \'`LDST_H\'\n           `LDST_H: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:61: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `LDST_H: begin  \n                    ^~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:65: syntax error, unexpected endcase\n         endcase  \n         ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:73: syntax error, unexpected else\n      else begin\n      ^~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:75: Define or directive not defined: \'`LDST_B\'\n           `LDST_B: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:83: Define or directive not defined: \'`LDST_H\'\n           `LDST_H: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:89: Define or directive not defined: \'`LDST_W\'\n           `LDST_W: begin  \n           ^~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:92: Define or directive not defined: \'`LDST_BU\'\n           `LDST_BU: begin  \n           ^~~~~~~~\n%Error: data/full_repos/permissive/440575220/miriscv_lsu.v:100: Define or directive not defined: \'`LDST_HU\'\n           `LDST_HU: begin  \n           ^~~~~~~~\n%Error: Cannot continue\n'
module miriscv_lsu(
                    input             clk_i,
                    input             arstn_i,


                    input [31:0]      lsu_addr_i,
                    input             lsu_we_i,
                    input [2:0]       lsu_size_i,
                    input [31:0]      lsu_data_i,
                    input             lsu_req_i,
                    output            lsu_stall_req_o,
                    output reg [31:0] lsu_data_o,


                    input [31:0]      data_rdata_i,
                    output reg        data_req_o,
                    output reg        data_we_o,
                    output reg [3:0]  data_be_o,
                    output reg [31:0] data_addr_o,
                    output reg [31:0] data_wdata_o
                    );

   reg                            last_pos_stall;

   assign lsu_stall_req_o = lsu_req_i && ~last_pos_stall;
   always @(posedge clk_i) last_pos_stall <= lsu_stall_req_o;


   wire [1:0]                     byteoffset = lsu_addr_i[1:0];

   always @(*) begin

      if(~arstn_i) begin
         lsu_data_o <= 0;
         last_pos_stall <= 0;
      end

      if(lsu_stall_req_o) begin
         case(lsu_size_i)
           `LDST_B: begin
              case(byteoffset)
                2'b00: data_be_o <= 4'b0001;
                2'b01: data_be_o <= 4'b0010;
                2'b10: data_be_o <= 4'b0100;
                2'b11: data_be_o <= 4'b1000;
              endcase


              data_wdata_o <= { 4{lsu_data_i[7:0]} };
           end
           `LDST_H: begin
              case(byteoffset)
                2'b00: data_be_o <= 4'b0011;
                2'b10: data_be_o <= 4'b1100;
              endcase

              data_wdata_o <= { 2{lsu_data_i[15:0]} };
           end
           `LDST_H: begin
              data_be_o <= 4'b1111;
              data_wdata_o <= lsu_data_i[31:0];
           end
         endcase


         data_we_o <= lsu_we_i;
         data_req_o <= lsu_req_i;

         data_addr_o <= lsu_addr_i;
      end
      else begin
         case(lsu_size_i)
           `LDST_B: begin
              case(byteoffset)
                2'b00: lsu_data_o <= { {24{data_rdata_i[7]}}, data_rdata_i[7:0] };
                2'b01: lsu_data_o <= { {24{data_rdata_i[15]}}, data_rdata_i[15:8] };
                2'b10: lsu_data_o <= { {24{data_rdata_i[23]}}, data_rdata_i[23:16] };
                2'b11: lsu_data_o <= { {24{data_rdata_i[31]}}, data_rdata_i[31:24] };
              endcase
           end
           `LDST_H: begin
              case(byteoffset)
                2'b00: lsu_data_o <= { {16{data_rdata_i[15]}}, data_rdata_i[15:0] };
                2'b10: lsu_data_o <= { {16{data_rdata_i[31]}}, data_rdata_i[31:16] };
              endcase
           end
           `LDST_W: begin
              lsu_data_o <= data_rdata_i[31:0];
           end
           `LDST_BU: begin
              case(byteoffset)
                2'b00: lsu_data_o <= {24'b0, data_rdata_i[7:0]};
                2'b01: lsu_data_o <= {24'b0, data_rdata_i[15:8]};
                2'b10: lsu_data_o <= {24'b0, data_rdata_i[23:16]};
                2'b11: lsu_data_o <= {24'b0, data_rdata_i[31:24]};
              endcase
           end
           `LDST_HU: begin
              case(byteoffset)
                2'b00: lsu_data_o <= {16'b0, data_rdata_i[15:0]};
                2'b10: lsu_data_o <= {16'b0, data_rdata_i[31:16]};
              endcase
           end
         endcase
         data_we_o <= 0;
         data_req_o <= 0;

      end
   end


endmodule
module miriscv_lsu(
                    input             clk_i,
                    input             arstn_i,


                    input [31:0]      lsu_addr_i,
                    input             lsu_we_i,
                    input [2:0]       lsu_size_i,
                    input [31:0]      lsu_data_i,
                    input             lsu_req_i,
                    output            lsu_stall_req_o,
                    output reg [31:0] lsu_data_o,


                    input [31:0]      data_rdata_i,
                    output reg        data_req_o,
                    output reg        data_we_o,
                    output reg [3:0]  data_be_o,
                    output reg [31:0] data_addr_o,
                    output reg [31:0] data_wdata_o
                    );


   reg                            last_pos_stall;

   assign lsu_stall_req_o = lsu_req_i && ~last_pos_stall;
   always @(posedge clk_i) last_pos_stall <= lsu_stall_req_o;


   wire [1:0]                     byteoffset = lsu_addr_i[1:0];

   always @(*) begin

      if(~arstn_i) begin
         lsu_data_o <= 0;
         last_pos_stall <= 0;
      end

      if(lsu_stall_req_o) begin
         case(lsu_size_i)
           `LDST_B: begin
              case(byteoffset)
                2'b00: data_be_o <= 4'b0001;
                2'b01: data_be_o <= 4'b0010;
                2'b10: data_be_o <= 4'b0100;
                2'b11: data_be_o <= 4'b1000;
              endcase


              data_wdata_o <= { 4{lsu_data_i[7:0]} };
           end
           `LDST_H: begin
              case(byteoffset)
                2'b00: data_be_o <= 4'b0011;
                2'b10: data_be_o <= 4'b1100;
              endcase

              data_wdata_o <= { 2{lsu_data_i[15:0]} };
           end
           `LDST_H: begin
              data_be_o <= 4'b1111;
              data_wdata_o <= lsu_data_i[31:0];
           end
         endcase


         data_we_o <= lsu_we_i;
         data_req_o <= lsu_req_i;

         data_addr_o <= lsu_addr_i;
      end
      else begin
         case(lsu_size_i)
           `LDST_B: begin
              case(byteoffset)
                2'b00: lsu_data_o <= { {24{data_rdata_i[7]}}, data_rdata_i[7:0] };
                2'b01: lsu_data_o <= { {24{data_rdata_i[15]}}, data_rdata_i[15:8] };
                2'b10: lsu_data_o <= { {24{data_rdata_i[23]}}, data_rdata_i[23:16] };
                2'b11: lsu_data_o <= { {24{data_rdata_i[31]}}, data_rdata_i[31:24] };
              endcase
           end
           `LDST_H: begin
              case(byteoffset)
                2'b00: lsu_data_o <= { {16{data_rdata_i[15]}}, data_rdata_i[15:0] };
                2'b10: lsu_data_o <= { {16{data_rdata_i[31]}}, data_rdata_i[31:16] };
              endcase
           end
           `LDST_W: begin
              lsu_data_o <= data_rdata_i[31:0];
           end
           `LDST_BU: begin
              case(byteoffset)
                2'b00: lsu_data_o <= {24'b0, data_rdata_i[7:0]};
                2'b01: lsu_data_o <= {24'b0, data_rdata_i[15:8]};
                2'b10: lsu_data_o <= {24'b0, data_rdata_i[23:16]};
                2'b11: lsu_data_o <= {24'b0, data_rdata_i[31:24]};
              endcase
           end
           `LDST_HU: begin
              case(byteoffset)
                2'b00: lsu_data_o <= {16'b0, data_rdata_i[15:0]};
                2'b10: lsu_data_o <= {16'b0, data_rdata_i[31:16]};
              endcase
           end
         endcase
         data_we_o <= 0;
         data_req_o <= 0;

      end
   end


endmodule