data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/wire.v
data/verilator_xmls/c0ff8e44-2581-4c83-b28f-3aa0d0d5e87f.xml
module top_module( 
    input in, 
    output out );

    assign out = in;
endmodule
module top_module( 
    input in, 
    output out );


    assign out = in;
endmodule