data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/test_canny_hist.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/test_canny_hist.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/test_canny_hist.v:71: Unsupported: Ignoring delay on this delayed statement.\n #5 clk1=~clk1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/test_canny_hist.v:74: Unsupported: Ignoring delay on this delayed statement.\n #2.5 clk2=~clk2;\n ^\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/test_canny_hist.v:41: Cannot find file containing module: \'canny\'\n canny uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/canny\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/canny.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/canny.sv\n             canny\n             canny.v\n             canny.sv\n             obj_dir/canny\n             obj_dir/canny.v\n             obj_dir/canny.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_canny_hist;


	reg clk1;
	reg clk2;
	reg rst;
	reg [7:0] mag1;
	reg [7:0] mag2;
	reg [5:0] dir1;
	reg [5:0] dir2;


	wire [17:0] addr;
	wire canny_edge;


	canny uut (
		.clk1(clk1), 
		.clk2(clk2), 
		.rst(rst), 
		.mag1(mag1), 
		.mag2(mag2), 
		.dir1(dir1), 

		.addr(addr), 
		.canny_edge(canny_edge)
	);

	initial begin

		clk1 = 0;
		clk2 = 0;
		rst = 0;
		mag1 = 0;
		mag2 = 0;
		dir1 = 0;
		dir2 = 0;


		#100;
      rst=1;  


	end
	
	always
	#5 clk1=~clk1;
	
	always
	#2.5 clk2=~clk2;
	
	always@(posedge clk1 or negedge rst)
	begin
		if(!rst)
		begin
			mag1<=0;
		end
		else
		begin
			if(mag1<128)
				mag1<=mag1+1;
			else
				mag1<=0;
		end
	end
      
endmodule
module test_canny_hist;



	reg clk1;
	reg clk2;
	reg rst;
	reg [7:0] mag1;
	reg [7:0] mag2;
	reg [5:0] dir1;
	reg [5:0] dir2;


	wire [17:0] addr;
	wire canny_edge;


	canny uut (
		.clk1(clk1), 
		.clk2(clk2), 
		.rst(rst), 
		.mag1(mag1), 
		.mag2(mag2), 
		.dir1(dir1), 

		.addr(addr), 
		.canny_edge(canny_edge)
	);

	initial begin

		clk1 = 0;
		clk2 = 0;
		rst = 0;
		mag1 = 0;
		mag2 = 0;
		dir1 = 0;
		dir2 = 0;


		#100;
      rst=1;  


	end
	
	always
	#5 clk1=~clk1;
	
	always
	#2.5 clk2=~clk2;
	
	always@(posedge clk1 or negedge rst)
	begin
		if(!rst)
		begin
			mag1<=0;
		end
		else
		begin
			if(mag1<128)
				mag1<=mag1+1;
			else
				mag1<=0;
		end
	end
      
endmodule