data/full_repos/permissive/515245706/milestone3/countDown/countDown.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515245706/milestone3/countDown/countDown.v:23: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'minuteOut\' generates 4 bits.\n                                                                                        : ... In instance countDown\n    secondOut <= minuteOut;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module countDown(clk, resetn, enable, minuteIn, secondIn, minuteOut, secondOut);
	input resetn, clk, enable;
	input [3: 0] minuteIn;
	input [5: 0] secondIn;
	output reg [3: 0] minuteOut;
	output reg [5: 0] secondOut;
	
	wire secondClk;
	
	rateDivider r0(
		.load(26'd49999999),
		.enable(enable),
		.clk(clk),
		.resetn(resetn),
		.out(secondClk)
	);
	
	always @(posedge clk)
	begin
		if (resetn == 1'b0)
			begin
				minuteOut <= minuteIn;
				secondOut <= minuteOut;
			end
		else if (enable == 1'b1 && secondClk == 1'b1)
			begin
				if (secondOut > 0)
					secondOut <= secondOut - 1;
				else if (secondOut == 0 && minuteOut > 0)
					begin
						secondOut <= 6'd59;
						minuteOut <= minuteOut - 1;
					end
			end
	end
	
endmodule
module countDown(clk, resetn, enable, minuteIn, secondIn, minuteOut, secondOut);

	input resetn, clk, enable;
	input [3: 0] minuteIn;
	input [5: 0] secondIn;
	output reg [3: 0] minuteOut;
	output reg [5: 0] secondOut;
	
	wire secondClk;
	
	rateDivider r0(
		.load(26'd49999999),
		.enable(enable),
		.clk(clk),
		.resetn(resetn),
		.out(secondClk)
	);
	
	always @(posedge clk)
	begin
		if (resetn == 1'b0)
			begin
				minuteOut <= minuteIn;
				secondOut <= minuteOut;
			end
		else if (enable == 1'b1 && secondClk == 1'b1)
			begin
				if (secondOut > 0)
					secondOut <= secondOut - 1;
				else if (secondOut == 0 && minuteOut > 0)
					begin
						secondOut <= 6'd59;
						minuteOut <= minuteOut - 1;
					end
			end
	end
	
endmodule