data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_PERIOD/2) io_clock <= (io_clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK_PERIOD/2) clock <= (clock === 1\'b0);\n        ^\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:52: syntax error, unexpected \'@\'\n   repeat (10000) @(posedge clock);\n                  ^\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:90: Unsupported: wait statements\n        wait(message == 2\'d1);\n        ^~~~\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:91: Unsupported: wait statements\n        wait(message == 2\'d0);\n        ^~~~\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:104: Unsupported: wait statements\n  wait(message == 2\'d1); \n  ^~~~\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:109: Unsupported: wait statements\n  wait(message == 2\'d2); \n  ^~~~\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:114: syntax error, unexpected \'@\'\n  @(posedge io_clock);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD*3000);\n  ^\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:119: syntax error, unexpected \'@\'\n        @(negedge io_clock) glb2io_1 = 1\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:134: syntax error, unexpected \'@\'\n            @(negedge io_clock);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/479253203/verilog/dv/cgra/cgra_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: Exiting due to 8 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cgra_tb;
	reg clock;
	reg io_clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [1:0] message = mprj_io[37:36];




    localparam CLK_PERIOD = 16;
	always #(CLK_PERIOD/2) io_clock <= (io_clock === 1'b0);
	always #(CLK_PERIOD/2) clock <= (clock === 1'b0);

	initial begin
		io_clock = 1;
		clock = 0;
	end

	integer c;
	initial begin
		c = 0;




		repeat (200) begin
			repeat (10000) @(posedge clock);
			c = c + 10;
			$display(" - %0d k cycles", c);
		end
		$display("%c[1;31m",27);
	
		$display ("Monitor: Timeout, Test (RTL) Failed");

		$display("%c[0m",27);
		$finish;
	end

	integer input_pgm_file;
    integer conv_3_3_bs_file;
    integer conv_3_3_bs_out_file;
	initial begin
		input_pgm_file = $fopen("./data/input.pgm.raw", "r");
        conv_3_3_bs_file = $fopen("./data/conv_3_3.bs.out", "w");
        conv_3_3_bs_out_file = $fopen("./data/conv_3_3.bs.out.valid", "w");
	end

	integer i, j;
	reg [15:0] input_pgm_in;

	reg [15:0] glb2io_16;
	reg        glb2io_1;
	reg        io_reset;

	assign mprj_io[15:0] = glb2io_16;
	assign mprj_io[16]   = glb2io_1;

	assign mprj_io[34] = io_clock;
	assign mprj_io[35] = io_reset;




    initial begin
        wait(message == 2'd1);
        wait(message == 2'd0);
        $display("Regtest failed... simulation end");
        $finish;
    end

	initial begin

		glb2io_16 = 16'd0;
        glb2io_1  = 1'b0;
		io_reset = 1'b1;

        $display("[Monitor]: Waiting configuration to start...");

		wait(message == 2'd1); 
		$display("[Monitor]: Configuration Start");
		io_reset = 1'b0;


		wait(message == 2'd2); 
		$display("[Monitor]: Configuration End");


		$display("[Monitor]: Wait 3k cycles to make sure sel changes to IO clock/reset");
		@(posedge io_clock);
		#(CLK_PERIOD*3000);


		$display("[Monitor]: Start feeding inputs to CGRA");
        @(negedge io_clock) glb2io_1 = 1'd1;
        @(negedge io_clock) glb2io_1 = 1'd0;
		for (i=0; i<4096; i=i+1) begin
            input_pgm_in = 0;
            for (j=0; j<2; j=j+1) begin
                input_pgm_in |= $fgetc(input_pgm_file) << (8 * j);
            end
            glb2io_16 = input_pgm_in;
            #1;
            for (j = 0; j < 2; j=j+1) begin
                $fwrite(conv_3_3_bs_file, "%c", (mprj_io[32:17] >> (8 * j)) & 8'hFF);
            end
            for (j = 0; j < 1; j=j+1) begin
                $fwrite(conv_3_3_bs_out_file, "%c", (mprj_io[33] >> (8 * j)) & 8'hFF);
            end
            @(negedge io_clock);
        end
        $fclose(input_pgm_file);
        $fclose(conv_3_3_bs_file);
        $fclose(conv_3_3_bs_out_file);

		$display("[Monitor]: ALL outputs catched, Simulation Finish, please check outputs");
        #(CLK_PERIOD*3);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("cgra.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module cgra_tb;

	reg clock;
	reg io_clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [1:0] message = mprj_io[37:36];




    localparam CLK_PERIOD = 16;
	always #(CLK_PERIOD/2) io_clock <= (io_clock === 1'b0);
	always #(CLK_PERIOD/2) clock <= (clock === 1'b0);

	initial begin
		io_clock = 1;
		clock = 0;
	end

	integer c;
	initial begin
		c = 0;




		repeat (200) begin
			repeat (10000) @(posedge clock);
			c = c + 10;
			$display(" - %0d k cycles", c);
		end
		$display("%c[1;31m",27);
	
		$display ("Monitor: Timeout, Test (RTL) Failed");

		$display("%c[0m",27);
		$finish;
	end

	integer input_pgm_file;
    integer conv_3_3_bs_file;
    integer conv_3_3_bs_out_file;
	initial begin
		input_pgm_file = $fopen("./data/input.pgm.raw", "r");
        conv_3_3_bs_file = $fopen("./data/conv_3_3.bs.out", "w");
        conv_3_3_bs_out_file = $fopen("./data/conv_3_3.bs.out.valid", "w");
	end

	integer i, j;
	reg [15:0] input_pgm_in;

	reg [15:0] glb2io_16;
	reg        glb2io_1;
	reg        io_reset;

	assign mprj_io[15:0] = glb2io_16;
	assign mprj_io[16]   = glb2io_1;

	assign mprj_io[34] = io_clock;
	assign mprj_io[35] = io_reset;




    initial begin
        wait(message == 2'd1);
        wait(message == 2'd0);
        $display("Regtest failed... simulation end");
        $finish;
    end

	initial begin

		glb2io_16 = 16'd0;
        glb2io_1  = 1'b0;
		io_reset = 1'b1;

        $display("[Monitor]: Waiting configuration to start...");

		wait(message == 2'd1); 
		$display("[Monitor]: Configuration Start");
		io_reset = 1'b0;


		wait(message == 2'd2); 
		$display("[Monitor]: Configuration End");


		$display("[Monitor]: Wait 3k cycles to make sure sel changes to IO clock/reset");
		@(posedge io_clock);
		#(CLK_PERIOD*3000);


		$display("[Monitor]: Start feeding inputs to CGRA");
        @(negedge io_clock) glb2io_1 = 1'd1;
        @(negedge io_clock) glb2io_1 = 1'd0;
		for (i=0; i<4096; i=i+1) begin
            input_pgm_in = 0;
            for (j=0; j<2; j=j+1) begin
                input_pgm_in |= $fgetc(input_pgm_file) << (8 * j);
            end
            glb2io_16 = input_pgm_in;
            #1;
            for (j = 0; j < 2; j=j+1) begin
                $fwrite(conv_3_3_bs_file, "%c", (mprj_io[32:17] >> (8 * j)) & 8'hFF);
            end
            for (j = 0; j < 1; j=j+1) begin
                $fwrite(conv_3_3_bs_out_file, "%c", (mprj_io[33] >> (8 * j)) & 8'hFF);
            end
            @(negedge io_clock);
        end
        $fclose(input_pgm_file);
        $fclose(conv_3_3_bs_file);
        $fclose(conv_3_3_bs_out_file);

		$display("[Monitor]: ALL outputs catched, Simulation Finish, please check outputs");
        #(CLK_PERIOD*3);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("cgra.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule