data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp/counterup36_8_2clk_async_resetp.v
1: b"%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp/counterup36_8_2clk_async_resetp.v:42: Cannot find file containing module: 'counterup8_1clk_async_resetp'\n counterup8_1clk_async_resetp ins0(.clk(clock0), .reset(reset), .count(out [7:0]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp,data/full_repos/permissive/451270484/counterup8_1clk_async_resetp\n             data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp,data/full_repos/permissive/451270484/counterup8_1clk_async_resetp.v\n             data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp,data/full_repos/permissive/451270484/counterup8_1clk_async_resetp.sv\n             counterup8_1clk_async_resetp\n             counterup8_1clk_async_resetp.v\n             counterup8_1clk_async_resetp.sv\n             obj_dir/counterup8_1clk_async_resetp\n             obj_dir/counterup8_1clk_async_resetp.v\n             obj_dir/counterup8_1clk_async_resetp.sv\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp/counterup36_8_2clk_async_resetp.v:43: Cannot find file containing module: 'counterup12_1clk_async_resetp'\n counterup12_1clk_async_resetp ins1(.clk(clock0), .reset(reset), .count(out [19:8]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp/counterup36_8_2clk_async_resetp.v:44: Cannot find file containing module: 'counterup16_1clk_async_resetp'\n counterup16_1clk_async_resetp ins2(.clk(clock0), .reset(reset), .count(out [35:20]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterup36_8_2clk_async_resetp/counterup36_8_2clk_async_resetp.v:18: Cannot find file containing module: 'counterup10_1clk_async_resetp'\n counterup10_1clk_async_resetp b0(.clk(clock0), .reset(reset), .count(out2));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module counterup36_8_2clk_async_resetp (clock0,reset,out1,out2);
	parameter N=36;
	parameter size = 77;
	input clock0;
	input reset;
	output [(size*N)-1:0] out1;
	wire [N-1:0] count_w;
	output [9:0] out2;


	cluster_counters a0(clock0, reset, count_w);
	counterup10_1clk_async_resetp b0(.clk(clock0), .reset(reset), .count(out2));

	generate
	genvar k;
	for(k=0;k < size; k=k+1)begin
	   assign out1[((N-1)+k*N):(k*N)] = count_w;
	end
	endgenerate

endmodule
module counterup36_8_2clk_async_resetp (clock0,reset,out1,out2);

	parameter N=36;
	parameter size = 77;
	input clock0;
	input reset;
	output [(size*N)-1:0] out1;
	wire [N-1:0] count_w;
	output [9:0] out2;


	cluster_counters a0(clock0, reset, count_w);
	counterup10_1clk_async_resetp b0(.clk(clock0), .reset(reset), .count(out2));

	generate
	genvar k;
	for(k=0;k < size; k=k+1)begin
	   assign out1[((N-1)+k*N):(k*N)] = count_w;
	end
	endgenerate

endmodule