data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Main.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #5 clear = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Main.v:52: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clock = ~clock;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Main.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #40 $finish;\n  ^\n%Error: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Main.v:41: Cannot find file containing module: \'Datapath\'\n Datapath datapath(clock, clear);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46132596/processor/SingleCycleDatapath,data/full_repos/permissive/46132596/Datapath\n             data/full_repos/permissive/46132596/processor/SingleCycleDatapath,data/full_repos/permissive/46132596/Datapath.v\n             data/full_repos/permissive/46132596/processor/SingleCycleDatapath,data/full_repos/permissive/46132596/Datapath.sv\n             Datapath\n             Datapath.v\n             Datapath.sv\n             obj_dir/Datapath\n             obj_dir/Datapath.v\n             obj_dir/Datapath.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Main;


	reg clock;
	reg clear;
	Datapath datapath(clock, clear);


	initial begin
		clear = 1;
		#5 clear = 0;
	end


	initial begin
		clock = 1;
		forever #5 clock = ~clock;
	end


	initial begin
		#40 $finish;
	end
endmodule
module Main;



	reg clock;
	reg clear;
	Datapath datapath(clock, clear);


	initial begin
		clear = 1;
		#5 clear = 0;
	end


	initial begin
		clock = 1;
		forever #5 clock = ~clock;
	end


	initial begin
		#40 $finish;
	end
endmodule