data/full_repos/permissive/458313092/Prescaler/Prescaler.v
data/verilator_xmls/eacc573f-e5d9-48b7-bfe3-d7cb61a640de.xml
module Prescaler #(
    parameter divide_factor = 10
) (
    input wire CLK,
    input wire CE,
    input wire CLR,
    output wire CEO
);
    reg [($clog2(divide_factor)-1):0] DIVIDER;


    assign  CEO =  ( DIVIDER ==  (divide_factor -1) && (CE == 1'b1) ) ? 1'b1 : 1'b0;

    always @(posedge CLK, posedge CLR) begin
        if (CLR == 1'b1) DIVIDER <= 0;
        else if (CLK == 1'b1)
            if (CE == 1'b1) 
                if (DIVIDER == (divide_factor -1 ))
                    DIVIDER <= 0;
                else 
                    DIVIDER <= DIVIDER +1;
    
    end


endmodule
module Prescaler #(
    parameter divide_factor = 10
) (
    input wire CLK,
    input wire CE,
    input wire CLR,
    output wire CEO
);

    reg [($clog2(divide_factor)-1):0] DIVIDER;


    assign  CEO =  ( DIVIDER ==  (divide_factor -1) && (CE == 1'b1) ) ? 1'b1 : 1'b0;

    always @(posedge CLK, posedge CLR) begin
        if (CLR == 1'b1) DIVIDER <= 0;
        else if (CLK == 1'b1)
            if (CE == 1'b1) 
                if (DIVIDER == (divide_factor -1 ))
                    DIVIDER <= 0;
                else 
                    DIVIDER <= DIVIDER +1;
    
    end


endmodule