data/full_repos/permissive/499944578/rtl/src/memory/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:178: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                                   : ... Top module \'single_port_ram\'\nmodule single_port_ram\n       ^~~~~~~~~~~~~~~\n                                                                                   : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                                   : ... Top module \'simple_ram_dual_clock\'\nmodule simple_ram_dual_clock #(\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:247: Little bit endian vector: MSB < LSB of bit range: -1:0\n    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module single_port_ram
(
	input [7:0] data,
	input [5:0] addr,
	input we, clk,
	output [7:0] q
);


	reg [7:0] ram[63:0];
	

	reg [5:0] addr_reg;
	
	always @ (posedge clk)
	begin

		if (we)
			ram[addr] <= data;
		
		addr_reg <= addr;
		
	end
		



	assign q = ram[addr_reg];
	
endmodule
module single_port_ram
(
	input [7:0] data,
	input [5:0] addr,
	input we, clk,
	output [7:0] q
);



	reg [7:0] ram[63:0];
	

	reg [5:0] addr_reg;
	
	always @ (posedge clk)
	begin

		if (we)
			ram[addr] <= data;
		
		addr_reg <= addr;
		
	end
		



	assign q = ram[addr_reg];
	
endmodule