data/full_repos/permissive/493441306/Verilog Language/modules_hierarchy/03_moduleshift.v
1: b'%Error: Cannot find file containing module: Language/modules_hierarchy,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             Language/modules_hierarchy,data/full_repos/permissive/493441306\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/modules_hierarchy/03_moduleshift.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( input clk, input d, output q );
    
    wire q1, q2;
    my_dff instance1(.clk(clk), .d(d), .q(q1) );
    my_dff instance2(.clk(clk), .d(q1), .q(q2) );
    my_dff instance3(.clk(clk), .d(q2), .q(q) );

endmodule
module top_module ( input clk, input d, output q );

    
    wire q1, q2;
    my_dff instance1(.clk(clk), .d(d), .q(q1) );
    my_dff instance2(.clk(clk), .d(q1), .q(q2) );
    my_dff instance3(.clk(clk), .d(q2), .q(q) );

endmodule