data/full_repos/permissive/494148647/src/peripherals/pdm/pdm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/494148647/src/peripherals/pdm/pdm.v:29: Operator GT expects 9 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                 : ... In instance pdm\n            if (accumulator_q > {DUTY_BITS{1\'b1}}) begin\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pdm#(parameter DUTY_BITS = 8) (
    input clk,
    input rst,
    input en,
    input [DUTY_BITS-1:0] duty,
    output pdm
    );

    reg pdm_d, pdm_q;
    reg [DUTY_BITS:0] accumulator_d, accumulator_q;


    assign pdm = pdm_q;


    always @(accumulator_q, duty, en) begin
        if (en) begin
            if (accumulator_q > {DUTY_BITS{1'b1}}) begin
                accumulator_d = accumulator_q - {DUTY_BITS{1'b1}} - 1 + duty;
                pdm_d = 1'b1;
            end else begin
                accumulator_d = accumulator_q + duty;
                pdm_d = 1'b0;
            end
        end else begin
            accumulator_d = accumulator_q;
            pdm_d = 1'b0;
        end
    end


    always @(posedge clk, posedge rst) begin
        if (rst) begin
            accumulator_q <= {(DUTY_BITS+1){1'b0}};
            pdm_q <= 1'b0;
        end else begin
            accumulator_q <= accumulator_d;
            pdm_q <= pdm_d;
        end
    end

endmodule
module pdm#(parameter DUTY_BITS = 8) (
    input clk,
    input rst,
    input en,
    input [DUTY_BITS-1:0] duty,
    output pdm
    );


    reg pdm_d, pdm_q;
    reg [DUTY_BITS:0] accumulator_d, accumulator_q;


    assign pdm = pdm_q;


    always @(accumulator_q, duty, en) begin
        if (en) begin
            if (accumulator_q > {DUTY_BITS{1'b1}}) begin
                accumulator_d = accumulator_q - {DUTY_BITS{1'b1}} - 1 + duty;
                pdm_d = 1'b1;
            end else begin
                accumulator_d = accumulator_q + duty;
                pdm_d = 1'b0;
            end
        end else begin
            accumulator_d = accumulator_q;
            pdm_d = 1'b0;
        end
    end


    always @(posedge clk, posedge rst) begin
        if (rst) begin
            accumulator_q <= {(DUTY_BITS+1){1'b0}};
            pdm_q <= 1'b0;
        end else begin
            accumulator_q <= accumulator_d;
            pdm_q <= pdm_d;
        end
    end

endmodule