data/full_repos/permissive/501115231/DMA/internalMem.v
1: b'%Error: data/full_repos/permissive/501115231/DMA/internalMem.v:88: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n     file=$fopen(DM_LOCATE);\n          ^~~~~~\n%Error: data/full_repos/permissive/501115231/DMA/internalMem.v:91: Unsupported: Use $fdisplay with %x format instead: $fdisplayh\n      $fdisplayh(file, i[DMA_SIZE-1:0], "\\t", dmData[i]);\n      ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_int #(parameter 
           `ifdef IGNORE
                    DM_LOCATE="intmemload.mem",
           `endif
                    DMA_SIZE=3, DMD_SIZE=4)
			(
				input wire clk,
				input wire ps_dm_cslt,
				input wire ps_dm_wrb,
				input wire[DMA_SIZE-1:0] dg_dm_add,
				input wire[DMD_SIZE-1:0] bc_dt,
				output reg[DMD_SIZE-1:0] dm_bc_dt
			);




		integer file, i;

		reg [DMD_SIZE-1:0] dmData [(2**DMA_SIZE)-1:0];
		reg [DMD_SIZE-1:0] dm [2*(2**DMA_SIZE)-1:0];

		reg dm_cslt;
		reg dm_wrb;
		reg [DMA_SIZE-1:0] dm_add;
		wire [DMD_SIZE-1:0] dmBypData;

 `ifdef IGNORE



	





		initial
		begin
			$readmemh(DM_LOCATE,dm);
			for(i=0; i<(2*(2**DMA_SIZE)); i=i+2)
			begin
				dmData[i/2]=dm[i+1];
			end
		end 
 `endif



		


		always@(posedge clk)
		begin
			if(ps_dm_cslt && ~ps_dm_wrb)
			begin
					dm_bc_dt<=dmData[dg_dm_add];
			end
		end



		always@(posedge clk)
		begin
			if(ps_dm_wrb && ps_dm_cslt)
			begin
					dm_cslt <= ps_dm_cslt;
					dm_wrb  <= ps_dm_wrb;
					dm_add  <= dg_dm_add;
			end
		end


		always@(posedge clk )
		begin
			if(dm_cslt)
			begin
				if(dm_wrb)
				begin
					dmData[dm_add][DMD_SIZE-1:0] <= bc_dt ;
 `ifdef IGNORE
					file=$fopen(DM_LOCATE);
					for(i=0; i<(2**DMA_SIZE); i=i+1)
					begin
						$fdisplayh(file, i[DMA_SIZE-1:0], "\t", dmData[i]);
					end
					$fclose(file);
 `endif
				end
			end
		end

endmodule
module memory_int #(parameter 
           `ifdef IGNORE
                    DM_LOCATE="intmemload.mem",
           `endif
                    DMA_SIZE=3, DMD_SIZE=4)
			(
				input wire clk,
				input wire ps_dm_cslt,
				input wire ps_dm_wrb,
				input wire[DMA_SIZE-1:0] dg_dm_add,
				input wire[DMD_SIZE-1:0] bc_dt,
				output reg[DMD_SIZE-1:0] dm_bc_dt
			);





		integer file, i;

		reg [DMD_SIZE-1:0] dmData [(2**DMA_SIZE)-1:0];
		reg [DMD_SIZE-1:0] dm [2*(2**DMA_SIZE)-1:0];

		reg dm_cslt;
		reg dm_wrb;
		reg [DMA_SIZE-1:0] dm_add;
		wire [DMD_SIZE-1:0] dmBypData;

 `ifdef IGNORE



	





		initial
		begin
			$readmemh(DM_LOCATE,dm);
			for(i=0; i<(2*(2**DMA_SIZE)); i=i+2)
			begin
				dmData[i/2]=dm[i+1];
			end
		end 
 `endif



		


		always@(posedge clk)
		begin
			if(ps_dm_cslt && ~ps_dm_wrb)
			begin
					dm_bc_dt<=dmData[dg_dm_add];
			end
		end



		always@(posedge clk)
		begin
			if(ps_dm_wrb && ps_dm_cslt)
			begin
					dm_cslt <= ps_dm_cslt;
					dm_wrb  <= ps_dm_wrb;
					dm_add  <= dg_dm_add;
			end
		end


		always@(posedge clk )
		begin
			if(dm_cslt)
			begin
				if(dm_wrb)
				begin
					dmData[dm_add][DMD_SIZE-1:0] <= bc_dt ;
 `ifdef IGNORE
					file=$fopen(DM_LOCATE);
					for(i=0; i<(2**DMA_SIZE); i=i+1)
					begin
						$fdisplayh(file, i[DMA_SIZE-1:0], "\t", dmData[i]);
					end
					$fclose(file);
 `endif
				end
			end
		end

endmodule