data/full_repos/permissive/527249789/src/ex_mem.v
1: b'%Error: data/full_repos/permissive/527249789/src/ex_mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:7: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]                  pc_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstAddrBus]                  pc_i,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:8: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]               pc_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:11: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:12: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:13: Define or directive not defined: \'`AluOpBus\'\n    input   [`AluOpBus]                     aluop_i,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:14: Define or directive not defined: \'`DataAddrBus\'\n    input   [`DataAddrBus]                  data_addr_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]                waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:17: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]                waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:18: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    wdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:19: Define or directive not defined: \'`AluOpBus\'\n    output  reg[`AluOpBus]                  aluop_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:20: Define or directive not defined: \'`DataAddrBus\'\n    output  reg[`DataAddrBus]               data_addr_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:24: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       hi_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:25: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       lo_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegBus]                    hi_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:27: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    hi_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:28: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    lo_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:32: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:33: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   cp0_reg_waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:35: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegBus]                    cp0_reg_wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:35: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    cp0_reg_wdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:36: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]                cp0_reg_waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:39: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       exception_type_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:40: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    exception_type_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:46: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input   [`RegBus]                       data_rdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:46: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       data_rdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:47: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    data_rdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:54: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:55: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:56: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:57: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:58: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:59: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:60: Define or directive not defined: \'`ZeroWord\'\n        data_addr_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:61: Define or directive not defined: \'`ZeroWord\'\n        data_rdata_o <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:62: Define or directive not defined: \'`WriteDisable\'\n        hilo_wen_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:63: Define or directive not defined: \'`ZeroWord\'\n        hi_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:64: Define or directive not defined: \'`ZeroWord\'\n        lo_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:65: Define or directive not defined: \'`WriteDisable\'\n        cp0_reg_wen_o <= `WriteDisable;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:66: Define or directive not defined: \'`ZeroWord\'\n        cp0_reg_wdata_o <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:67: Define or directive not defined: \'`ZeroRegAddr\'\n        cp0_reg_waddr_o <= `ZeroRegAddr;\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:68: Define or directive not defined: \'`ZeroWord\'\n        exception_type_o <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:69: Define or directive not defined: \'`NotInDelaySlot\'\n        is_in_delayslot_o <= `NotInDelaySlot;\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:70: Define or directive not defined: \'`FlushEnable\'\n    end else if (flush == `FlushEnable) begin\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:71: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:72: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:73: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:74: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/ex_mem.v:75: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex_mem(
    input                                   clk,
    input                                   resetn,

    input   [`InstAddrBus]                  pc_i,
    output  reg[`InstAddrBus]               pc_o,

    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       wdata_i,
    input   [`AluOpBus]                     aluop_i,
    input   [`DataAddrBus]                  data_addr_i,

    output  reg                             wen_o,
    output  reg[`RegAddrBus]                waddr_o,
    output  reg[`RegBus]                    wdata_o,
    output  reg[`AluOpBus]                  aluop_o,
    output  reg[`DataAddrBus]               data_addr_o,


    input                                   hilo_wen_i,
    input   [`RegBus]                       hi_i,
    input   [`RegBus]                       lo_i,
    output  reg                             hilo_wen_o,
    output  reg[`RegBus]                    hi_o,
    output  reg[`RegBus]                    lo_o,


    input                                   cp0_reg_wen_i,
    input   [`RegBus]                       cp0_reg_wdata_i,
    input   [`RegAddrBus]                   cp0_reg_waddr_i,
    output  reg                             cp0_reg_wen_o,
    output  reg[`RegBus]                    cp0_reg_wdata_o,
    output  reg[`RegAddrBus]                cp0_reg_waddr_o,


    input   [`RegBus]                       exception_type_i,
    output  reg[`RegBus]                    exception_type_o,


    input                                   is_in_delayslot_i,
    output  reg                             is_in_delayslot_o,

    input   [`RegBus]                       data_rdata_i,
    output  reg[`RegBus]                    data_rdata_o,

    input                                   flush,
    input   [3:0]                           stall_i
);

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if ((stall_i[2] == `Stop) && (stall_i[3] == `NoStop)) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (stall_i[2] == `NoStop) begin
        pc_o <= pc_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        wdata_o <= wdata_i;
        aluop_o <= aluop_i;
        data_addr_o <= data_addr_i;
        data_rdata_o <= data_rdata_i;
        hilo_wen_o <= hilo_wen_i;
        hi_o <= hi_i;
        lo_o <= lo_i;
        cp0_reg_wen_o <= cp0_reg_wen_i;
        cp0_reg_wdata_o <= cp0_reg_wdata_i;
        cp0_reg_waddr_o <= cp0_reg_waddr_i;
        exception_type_o <= exception_type_i;
        is_in_delayslot_o <= is_in_delayslot_i;
    end
end

endmodule
module ex_mem(
    input                                   clk,
    input                                   resetn,

    input   [`InstAddrBus]                  pc_i,
    output  reg[`InstAddrBus]               pc_o,

    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       wdata_i,
    input   [`AluOpBus]                     aluop_i,
    input   [`DataAddrBus]                  data_addr_i,

    output  reg                             wen_o,
    output  reg[`RegAddrBus]                waddr_o,
    output  reg[`RegBus]                    wdata_o,
    output  reg[`AluOpBus]                  aluop_o,
    output  reg[`DataAddrBus]               data_addr_o,


    input                                   hilo_wen_i,
    input   [`RegBus]                       hi_i,
    input   [`RegBus]                       lo_i,
    output  reg                             hilo_wen_o,
    output  reg[`RegBus]                    hi_o,
    output  reg[`RegBus]                    lo_o,


    input                                   cp0_reg_wen_i,
    input   [`RegBus]                       cp0_reg_wdata_i,
    input   [`RegAddrBus]                   cp0_reg_waddr_i,
    output  reg                             cp0_reg_wen_o,
    output  reg[`RegBus]                    cp0_reg_wdata_o,
    output  reg[`RegAddrBus]                cp0_reg_waddr_o,


    input   [`RegBus]                       exception_type_i,
    output  reg[`RegBus]                    exception_type_o,


    input                                   is_in_delayslot_i,
    output  reg                             is_in_delayslot_o,

    input   [`RegBus]                       data_rdata_i,
    output  reg[`RegBus]                    data_rdata_o,

    input                                   flush,
    input   [3:0]                           stall_i
);


always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if ((stall_i[2] == `Stop) && (stall_i[3] == `NoStop)) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        aluop_o <= `EXE_NOP_OP;
        data_addr_o <= `ZeroWord;
        data_rdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (stall_i[2] == `NoStop) begin
        pc_o <= pc_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        wdata_o <= wdata_i;
        aluop_o <= aluop_i;
        data_addr_o <= data_addr_i;
        data_rdata_o <= data_rdata_i;
        hilo_wen_o <= hilo_wen_i;
        hi_o <= hi_i;
        lo_o <= lo_i;
        cp0_reg_wen_o <= cp0_reg_wen_i;
        cp0_reg_wdata_o <= cp0_reg_wdata_i;
        cp0_reg_waddr_o <= cp0_reg_waddr_i;
        exception_type_o <= exception_type_i;
        is_in_delayslot_o <= is_in_delayslot_i;
    end
end

endmodule