data/full_repos/permissive/488660558/clk_1Hz.v
data/verilator_xmls/d498a50d-70f2-48e6-b89a-ae14491ef7f3.xml
module clk_1Hz(clk,clk1,reset);
    input clk,reset;
    output clk1;
    reg [28:0] count;
    
    always @(posedge clk)
    begin
        if (reset) count <= 29'b0;
        else count <= count +1'b1;
    end
    
    assign clk1=count[28];
endmodule
module clk_1Hz(clk,clk1,reset);

    input clk,reset;
    output clk1;
    reg [28:0] count;
    
    always @(posedge clk)
    begin
        if (reset) count <= 29'b0;
        else count <= count +1'b1;
    end
    
    assign clk1=count[28];
endmodule