data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_nstep.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_nstep.v:26: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_clsp_clkgn_nstep(

cmp_nstep_sel, jbus_nstep_sel, dram_nstep_sel, 

io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_dram, 
jtag_clock_dr_jbus, jtag_clsp_force_cken_jbus, 
jtag_clsp_force_cken_dram, jtag_clsp_force_cken_cmp, 
jtag_nstep_count, jtag_nstep_domain, jtag_nstep_vld, cmp_gclk_bypass, 
dram_gclk_bypass, jbus_gclk_bypass, capture_l, start_clk_early_jl, 
testmode_l, shadreg_div_cmult, shadreg_div_jmult, shadreg_div_dmult
);


input io_pwron_rst_l;
input jtag_clock_dr_cmp;
input jtag_clock_dr_dram;
input jtag_clock_dr_jbus;
input jtag_clsp_force_cken_jbus;
input jtag_clsp_force_cken_dram;
input jtag_clsp_force_cken_cmp;

input [3:0] jtag_nstep_count;
input [2:0] jtag_nstep_domain;
input jtag_nstep_vld;

input cmp_gclk_bypass;
input dram_gclk_bypass;
input jbus_gclk_bypass;


input capture_l;
input start_clk_early_jl;
input testmode_l;

input [13:0] shadreg_div_cmult;
input [9:0] shadreg_div_jmult;
input [9:0] shadreg_div_dmult;

output cmp_nstep_sel;
output jbus_nstep_sel;
output dram_nstep_sel;




   ctu_clsp_clkgn_nstep_cnt u_cmp(

				  .nstep_sel(cmp_nstep_sel),

				  .io_pwron_rst_l(io_pwron_rst_l),
				  .clk	(cmp_gclk_bypass),
				  .jtag_clock_dr(jtag_clock_dr_cmp),
				  .jtag_nstep_count(jtag_nstep_count[3:0]),
				  .jtag_nstep_domain(jtag_nstep_domain[0]),
				  .jtag_nstep_vld(jtag_nstep_vld),
				  .capture_l(capture_l),
				  .testmode_l(testmode_l),
				  .start_clk_early_jl(start_clk_early_jl),
				  .shadreg_div_mult(shadreg_div_cmult[13:0]),
				  .force_cken(jtag_clsp_force_cken_cmp));



   
   ctu_clsp_clkgn_nstep_cnt u_jbus(

				   .nstep_sel(jbus_nstep_sel),

				   .io_pwron_rst_l(io_pwron_rst_l),
				   .clk	(jbus_gclk_bypass),
				   .jtag_clock_dr(jtag_clock_dr_jbus),
				   .jtag_nstep_count(jtag_nstep_count[3:0]),
				   .jtag_nstep_domain(jtag_nstep_domain[2]),
				   .jtag_nstep_vld(jtag_nstep_vld),
				   .capture_l(capture_l),
				   .testmode_l(testmode_l),
				   .start_clk_early_jl(start_clk_early_jl),
				   .shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}),
				   .force_cken(jtag_clsp_force_cken_jbus));




    ctu_clsp_clkgn_nstep_cnt u_dram(

				    .nstep_sel(dram_nstep_sel),

				    .io_pwron_rst_l(io_pwron_rst_l),
				    .clk(dram_gclk_bypass),
				    .jtag_clock_dr(jtag_clock_dr_dram),
				    .jtag_nstep_count(jtag_nstep_count[3:0]),
				    .jtag_nstep_domain(jtag_nstep_domain[1]),
				    .jtag_nstep_vld(jtag_nstep_vld),
				    .capture_l(capture_l),
				    .testmode_l(testmode_l),
				    .start_clk_early_jl(start_clk_early_jl),
				    .shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}),
				    .force_cken(jtag_clsp_force_cken_dram));


endmodule
module ctu_clsp_clkgn_nstep(

cmp_nstep_sel, jbus_nstep_sel, dram_nstep_sel, 

io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_dram, 
jtag_clock_dr_jbus, jtag_clsp_force_cken_jbus, 
jtag_clsp_force_cken_dram, jtag_clsp_force_cken_cmp, 
jtag_nstep_count, jtag_nstep_domain, jtag_nstep_vld, cmp_gclk_bypass, 
dram_gclk_bypass, jbus_gclk_bypass, capture_l, start_clk_early_jl, 
testmode_l, shadreg_div_cmult, shadreg_div_jmult, shadreg_div_dmult
);



input io_pwron_rst_l;
input jtag_clock_dr_cmp;
input jtag_clock_dr_dram;
input jtag_clock_dr_jbus;
input jtag_clsp_force_cken_jbus;
input jtag_clsp_force_cken_dram;
input jtag_clsp_force_cken_cmp;

input [3:0] jtag_nstep_count;
input [2:0] jtag_nstep_domain;
input jtag_nstep_vld;

input cmp_gclk_bypass;
input dram_gclk_bypass;
input jbus_gclk_bypass;


input capture_l;
input start_clk_early_jl;
input testmode_l;

input [13:0] shadreg_div_cmult;
input [9:0] shadreg_div_jmult;
input [9:0] shadreg_div_dmult;

output cmp_nstep_sel;
output jbus_nstep_sel;
output dram_nstep_sel;




   ctu_clsp_clkgn_nstep_cnt u_cmp(

				  .nstep_sel(cmp_nstep_sel),

				  .io_pwron_rst_l(io_pwron_rst_l),
				  .clk	(cmp_gclk_bypass),
				  .jtag_clock_dr(jtag_clock_dr_cmp),
				  .jtag_nstep_count(jtag_nstep_count[3:0]),
				  .jtag_nstep_domain(jtag_nstep_domain[0]),
				  .jtag_nstep_vld(jtag_nstep_vld),
				  .capture_l(capture_l),
				  .testmode_l(testmode_l),
				  .start_clk_early_jl(start_clk_early_jl),
				  .shadreg_div_mult(shadreg_div_cmult[13:0]),
				  .force_cken(jtag_clsp_force_cken_cmp));



   
   ctu_clsp_clkgn_nstep_cnt u_jbus(

				   .nstep_sel(jbus_nstep_sel),

				   .io_pwron_rst_l(io_pwron_rst_l),
				   .clk	(jbus_gclk_bypass),
				   .jtag_clock_dr(jtag_clock_dr_jbus),
				   .jtag_nstep_count(jtag_nstep_count[3:0]),
				   .jtag_nstep_domain(jtag_nstep_domain[2]),
				   .jtag_nstep_vld(jtag_nstep_vld),
				   .capture_l(capture_l),
				   .testmode_l(testmode_l),
				   .start_clk_early_jl(start_clk_early_jl),
				   .shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}),
				   .force_cken(jtag_clsp_force_cken_jbus));




    ctu_clsp_clkgn_nstep_cnt u_dram(

				    .nstep_sel(dram_nstep_sel),

				    .io_pwron_rst_l(io_pwron_rst_l),
				    .clk(dram_gclk_bypass),
				    .jtag_clock_dr(jtag_clock_dr_dram),
				    .jtag_nstep_count(jtag_nstep_count[3:0]),
				    .jtag_nstep_domain(jtag_nstep_domain[1]),
				    .jtag_nstep_vld(jtag_nstep_vld),
				    .capture_l(capture_l),
				    .testmode_l(testmode_l),
				    .start_clk_early_jl(start_clk_early_jl),
				    .shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}),
				    .force_cken(jtag_clsp_force_cken_dram));


endmodule