data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/fflopxe.v
data/verilator_xmls/5f88948a-a521-4146-b4ef-62b31dec686b.xml
module fflopxe
    (
     clk,
     rst_,
     latch_en,
     idat,
     odat
     );

parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk, rst_, latch_en;
input   [WIDTH-1:0] idat;

output  [WIDTH-1:0] odat;
reg     [WIDTH-1:0] odat;

always @ (posedge clk or negedge rst_)
    begin
    if(!rst_) odat <= RESET_VALUE;
    else if (latch_en) odat <= idat;
    end

endmodule
module fflopxe
    (
     clk,
     rst_,
     latch_en,
     idat,
     odat
     );


parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk, rst_, latch_en;
input   [WIDTH-1:0] idat;

output  [WIDTH-1:0] odat;
reg     [WIDTH-1:0] odat;

always @ (posedge clk or negedge rst_)
    begin
    if(!rst_) odat <= RESET_VALUE;
    else if (latch_en) odat <= idat;
    end

endmodule