data/full_repos/permissive/43856783/j1_soc/hdl/UART/peripheral_uart.v
1: b"%Error: data/full_repos/permissive/43856783/j1_soc/hdl/UART/peripheral_uart.v:60: Cannot find file containing module: 'uart'\nuart uart(.uart_busy(uart_busy), .uart_tx(uart_tx), .uart_wr_i(cs && wr && (addr != 4'h4) ), .uart_dat_i(d_in_uart), .sys_clk_i(clk), .sys_rst_i(rst)); \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/UART,data/full_repos/permissive/43856783/uart\n             data/full_repos/permissive/43856783/j1_soc/hdl/UART,data/full_repos/permissive/43856783/uart.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/UART,data/full_repos/permissive/43856783/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s)\n"
module peripheral_uart(clk , rst , d_in , cs , addr , rd , wr, d_out,  uart_tx, ledout );
  
  input clk;
  input rst;
  input [15:0]d_in;
  input cs;
  input [3:0]addr;
  input rd;
  input wr;
  output reg [15:0]d_out;

   output uart_tx;
   output reg ledout=0;



reg [2:0] s;

reg [7:0] d_in_uart;

wire uart_busy;






always @(*) begin
case (addr)
4'h0:begin s = (cs && rd) ? 3'b001 : 3'b000 ;end

4'h2:begin s = (cs && wr) ? 3'b010 : 3'b000 ;end
4'h4:begin s = (cs && wr) ? 3'b100 : 3'b000 ;end
default:begin s=3'b000 ; end
endcase
end





always @(negedge clk) begin

d_in_uart= (s[1]) ? d_in[7:0] : d_in_uart;
ledout = (s[2]) ? d_in[0] : ledout;

end




always @(negedge clk) begin
case (s)
3'b001: d_out[0]= uart_busy;
default: d_out=0;
endcase
end


uart uart(.uart_busy(uart_busy), .uart_tx(uart_tx), .uart_wr_i(cs && wr && (addr != 4'h4) ), .uart_dat_i(d_in_uart), .sys_clk_i(clk), .sys_rst_i(rst));


endmodule
module peripheral_uart(clk , rst , d_in , cs , addr , rd , wr, d_out,  uart_tx, ledout );

  
  input clk;
  input rst;
  input [15:0]d_in;
  input cs;
  input [3:0]addr;
  input rd;
  input wr;
  output reg [15:0]d_out;

   output uart_tx;
   output reg ledout=0;



reg [2:0] s;

reg [7:0] d_in_uart;

wire uart_busy;






always @(*) begin
case (addr)
4'h0:begin s = (cs && rd) ? 3'b001 : 3'b000 ;end

4'h2:begin s = (cs && wr) ? 3'b010 : 3'b000 ;end
4'h4:begin s = (cs && wr) ? 3'b100 : 3'b000 ;end
default:begin s=3'b000 ; end
endcase
end





always @(negedge clk) begin

d_in_uart= (s[1]) ? d_in[7:0] : d_in_uart;
ledout = (s[2]) ? d_in[0] : ledout;

end




always @(negedge clk) begin
case (s)
3'b001: d_out[0]= uart_busy;
default: d_out=0;
endcase
end


uart uart(.uart_busy(uart_busy), .uart_tx(uart_tx), .uart_wr_i(cs && wr && (addr != 4'h4) ), .uart_dat_i(d_in_uart), .sys_clk_i(clk), .sys_rst_i(rst));


endmodule