data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/jtag,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/jtag,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/jtag,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:21: Define or directive not defined: \'`MemAddrBus\'\n    output wire [`MemAddrBus]   jtag_axi_awaddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output wire [`MemAddrBus]   jtag_axi_awaddr , \n                            ^\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 jtag_axi_awvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 jtag_axi_awready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemBus]       jtag_axi_wdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:26: Define or directive not defined: \'`MemBus\'\n    output wire [`MemBus]       jtag_axi_wdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 jtag_axi_wvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 jtag_axi_wready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [1:0]           jtag_axi_bresp  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 jtag_axi_bvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 jtag_axi_bready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemAddrBus]   jtag_axi_araddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:35: Define or directive not defined: \'`MemAddrBus\'\n    output wire [`MemAddrBus]   jtag_axi_araddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 jtag_axi_arvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 jtag_axi_arready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemBus]       jtag_axi_rdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:40: Define or directive not defined: \'`MemBus\'\n    input  wire [`MemBus]       jtag_axi_rdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 jtag_axi_rvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 jtag_axi_rready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire halt_req_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire reset_req_o\n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:63: syntax error, unexpected assign\n    assign jtag_axi_awaddr = {mem_addr_o[31:2], 2\'b00}; \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/jtag/jtag_top.v:89: syntax error, unexpected IDENTIFIER\n    jtag_driver #(\n    ^~~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module jtag_top (

    input wire clk,
    input wire jtag_rst_n,

    input wire jtag_pin_TCK,
    input wire jtag_pin_TMS,
    input wire jtag_pin_TDI,
    output wire jtag_pin_TDO,

    output wire reg_we_o,
    output wire[4:0] reg_addr_o,
    output wire[31:0] reg_wdata_o,
    input wire[31:0] reg_rdata_i,



    output wire [`MemAddrBus]   jtag_axi_awaddr ,
    output wire [2:0]           jtag_axi_awprot ,
    output wire                 jtag_axi_awvalid,
    input  wire                 jtag_axi_awready,

    output wire [`MemBus]       jtag_axi_wdata  ,
    output wire [3:0]           jtag_axi_wstrb  ,
    output wire                 jtag_axi_wvalid ,
    input  wire                 jtag_axi_wready ,

    input  wire [1:0]           jtag_axi_bresp  ,
    input  wire                 jtag_axi_bvalid ,
    output wire                 jtag_axi_bready ,

    output wire [`MemAddrBus]   jtag_axi_araddr ,
    output wire [2:0]           jtag_axi_arprot ,
    output wire                 jtag_axi_arvalid,
    input  wire                 jtag_axi_arready,

    input  wire [`MemBus]       jtag_axi_rdata  ,
    input  wire [1:0]           jtag_axi_rresp  ,
    input  wire                 jtag_axi_rvalid ,
    output wire                 jtag_axi_rready ,

    output wire halt_req_o,
    output wire reset_req_o

    );
    localparam DMI_ADDR_BITS = 6;
    localparam DMI_DATA_BITS = 32;
    localparam DMI_OP_BITS = 2;
    localparam DM_RESP_BITS = DMI_ADDR_BITS + DMI_DATA_BITS + DMI_OP_BITS;
    localparam DTM_REQ_BITS = DMI_ADDR_BITS + DMI_DATA_BITS + DMI_OP_BITS;


    wire req_valid_o;
    wire mem_we_o;
    wire[31:0] mem_addr_o;
    wire[31:0] mem_wdata_o;
    wire[31:0] mem_rdata_i;
    wire[3:0] mem_sel_o;

    assign jtag_axi_awaddr = {mem_addr_o[31:2], 2'b00};
    assign jtag_axi_awvalid = req_valid_o & mem_we_o;
    assign jtag_axi_wdata = mem_wdata_o;
    assign jtag_axi_wstrb = mem_sel_o;
    assign jtag_axi_wvalid = req_valid_o & mem_we_o;
    assign jtag_axi_araddr = {mem_addr_o[31:2], 2'b00};
    assign jtag_axi_arvalid = req_valid_o & ~mem_we_o;
    assign mem_rdata_i = jtag_axi_rdata;

    assign jtag_axi_awprot = 3'h0;
    assign jtag_axi_bready = 1'b1;
    assign jtag_axi_arprot = 3'h0;
    assign jtag_axi_rready = 1'b1;


    wire dtm_ack_o;
    wire dtm_req_valid_o;
    wire[DTM_REQ_BITS - 1:0] dtm_req_data_o;


    wire dm_ack_o;
    wire[DM_RESP_BITS-1:0] dm_resp_data_o;
    wire dm_resp_valid_o;
    wire dm_halt_req_o;
    wire dm_reset_req_o;

    jtag_driver #(
        .DMI_ADDR_BITS(DMI_ADDR_BITS),
        .DMI_DATA_BITS(DMI_DATA_BITS),
        .DMI_OP_BITS(DMI_OP_BITS)
    ) u_jtag_driver(
        .rst_n(jtag_rst_n),
        .jtag_TCK(jtag_pin_TCK),
        .jtag_TDI(jtag_pin_TDI),
        .jtag_TMS(jtag_pin_TMS),
        .jtag_TDO(jtag_pin_TDO),
        .dm_resp_i(dm_resp_valid_o),
        .dm_resp_data_i(dm_resp_data_o),
        .dtm_ack_o(dtm_ack_o),
        .dm_ack_i(dm_ack_o),
        .dtm_req_valid_o(dtm_req_valid_o),
        .dtm_req_data_o(dtm_req_data_o)
    );

    jtag_dm #(
        .DMI_ADDR_BITS(DMI_ADDR_BITS),
        .DMI_DATA_BITS(DMI_DATA_BITS),
        .DMI_OP_BITS(DMI_OP_BITS)
    ) u_jtag_dm(
        .clk(clk),
        .rst_n(jtag_rst_n),
        .dm_ack_o(dm_ack_o),
        .dtm_req_valid_i(dtm_req_valid_o),
        .dtm_req_data_i(dtm_req_data_o),
        .dtm_ack_i(dtm_ack_o),
        .dm_resp_data_o(dm_resp_data_o),
        .dm_resp_valid_o(dm_resp_valid_o),
        .dm_reg_we_o(reg_we_o),
        .dm_reg_addr_o(reg_addr_o),
        .dm_reg_wdata_o(reg_wdata_o),
        .dm_reg_rdata_i(reg_rdata_i),
        .dm_mem_we_o(mem_we_o),
        .dm_mem_addr_o(mem_addr_o),
        .dm_mem_wdata_o(mem_wdata_o),
        .dm_mem_rdata_i(mem_rdata_i),
        .dm_mem_sel_o(mem_sel_o),
        .req_valid_o(req_valid_o),
        .dm_halt_req_o(halt_req_o),
        .dm_reset_req_o(reset_req_o)
    );

endmodule
module jtag_top (

    input wire clk,
    input wire jtag_rst_n,

    input wire jtag_pin_TCK,
    input wire jtag_pin_TMS,
    input wire jtag_pin_TDI,
    output wire jtag_pin_TDO,

    output wire reg_we_o,
    output wire[4:0] reg_addr_o,
    output wire[31:0] reg_wdata_o,
    input wire[31:0] reg_rdata_i,



    output wire [`MemAddrBus]   jtag_axi_awaddr ,
    output wire [2:0]           jtag_axi_awprot ,
    output wire                 jtag_axi_awvalid,
    input  wire                 jtag_axi_awready,

    output wire [`MemBus]       jtag_axi_wdata  ,
    output wire [3:0]           jtag_axi_wstrb  ,
    output wire                 jtag_axi_wvalid ,
    input  wire                 jtag_axi_wready ,

    input  wire [1:0]           jtag_axi_bresp  ,
    input  wire                 jtag_axi_bvalid ,
    output wire                 jtag_axi_bready ,

    output wire [`MemAddrBus]   jtag_axi_araddr ,
    output wire [2:0]           jtag_axi_arprot ,
    output wire                 jtag_axi_arvalid,
    input  wire                 jtag_axi_arready,

    input  wire [`MemBus]       jtag_axi_rdata  ,
    input  wire [1:0]           jtag_axi_rresp  ,
    input  wire                 jtag_axi_rvalid ,
    output wire                 jtag_axi_rready ,

    output wire halt_req_o,
    output wire reset_req_o

    );

    localparam DMI_ADDR_BITS = 6;
    localparam DMI_DATA_BITS = 32;
    localparam DMI_OP_BITS = 2;
    localparam DM_RESP_BITS = DMI_ADDR_BITS + DMI_DATA_BITS + DMI_OP_BITS;
    localparam DTM_REQ_BITS = DMI_ADDR_BITS + DMI_DATA_BITS + DMI_OP_BITS;


    wire req_valid_o;
    wire mem_we_o;
    wire[31:0] mem_addr_o;
    wire[31:0] mem_wdata_o;
    wire[31:0] mem_rdata_i;
    wire[3:0] mem_sel_o;

    assign jtag_axi_awaddr = {mem_addr_o[31:2], 2'b00};
    assign jtag_axi_awvalid = req_valid_o & mem_we_o;
    assign jtag_axi_wdata = mem_wdata_o;
    assign jtag_axi_wstrb = mem_sel_o;
    assign jtag_axi_wvalid = req_valid_o & mem_we_o;
    assign jtag_axi_araddr = {mem_addr_o[31:2], 2'b00};
    assign jtag_axi_arvalid = req_valid_o & ~mem_we_o;
    assign mem_rdata_i = jtag_axi_rdata;

    assign jtag_axi_awprot = 3'h0;
    assign jtag_axi_bready = 1'b1;
    assign jtag_axi_arprot = 3'h0;
    assign jtag_axi_rready = 1'b1;


    wire dtm_ack_o;
    wire dtm_req_valid_o;
    wire[DTM_REQ_BITS - 1:0] dtm_req_data_o;


    wire dm_ack_o;
    wire[DM_RESP_BITS-1:0] dm_resp_data_o;
    wire dm_resp_valid_o;
    wire dm_halt_req_o;
    wire dm_reset_req_o;

    jtag_driver #(
        .DMI_ADDR_BITS(DMI_ADDR_BITS),
        .DMI_DATA_BITS(DMI_DATA_BITS),
        .DMI_OP_BITS(DMI_OP_BITS)
    ) u_jtag_driver(
        .rst_n(jtag_rst_n),
        .jtag_TCK(jtag_pin_TCK),
        .jtag_TDI(jtag_pin_TDI),
        .jtag_TMS(jtag_pin_TMS),
        .jtag_TDO(jtag_pin_TDO),
        .dm_resp_i(dm_resp_valid_o),
        .dm_resp_data_i(dm_resp_data_o),
        .dtm_ack_o(dtm_ack_o),
        .dm_ack_i(dm_ack_o),
        .dtm_req_valid_o(dtm_req_valid_o),
        .dtm_req_data_o(dtm_req_data_o)
    );

    jtag_dm #(
        .DMI_ADDR_BITS(DMI_ADDR_BITS),
        .DMI_DATA_BITS(DMI_DATA_BITS),
        .DMI_OP_BITS(DMI_OP_BITS)
    ) u_jtag_dm(
        .clk(clk),
        .rst_n(jtag_rst_n),
        .dm_ack_o(dm_ack_o),
        .dtm_req_valid_i(dtm_req_valid_o),
        .dtm_req_data_i(dtm_req_data_o),
        .dtm_ack_i(dtm_ack_o),
        .dm_resp_data_o(dm_resp_data_o),
        .dm_resp_valid_o(dm_resp_valid_o),
        .dm_reg_we_o(reg_we_o),
        .dm_reg_addr_o(reg_addr_o),
        .dm_reg_wdata_o(reg_wdata_o),
        .dm_reg_rdata_i(reg_rdata_i),
        .dm_mem_we_o(mem_we_o),
        .dm_mem_addr_o(mem_addr_o),
        .dm_mem_wdata_o(mem_wdata_o),
        .dm_mem_rdata_i(mem_rdata_i),
        .dm_mem_sel_o(mem_sel_o),
        .req_valid_o(req_valid_o),
        .dm_halt_req_o(halt_req_o),
        .dm_reset_req_o(reset_req_o)
    );

endmodule