data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v:50: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                               : ... In instance DMem\n                    ram[addr][7:0] <= data_in[7:0];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v:52: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                               : ... In instance DMem\n                    ram[addr][15:8] <= data_in[15:8];                    \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v:54: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                               : ... In instance DMem\n                    ram[addr][23:16] <= data_in[23:16];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v:56: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                               : ... In instance DMem\n                    ram[addr][31:24] <= data_in[31:24];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DMem.v:58: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                               : ... In instance DMem\n                    d_out <= ram[addr];\n                                ^\n%Error: Exiting due to 5 warning(s)\n'
module DMem(
    input wire clk,
    input wire rd,
    input wire [3:0] we,
    input wire [31:0] addr_in,
    input wire [31:0] data_in,
    output wire [31:0] data_out
);


    reg [31:0] ram [0:`RAM_LENGTH_WORDS-1];


    wire [11:0] addr = (addr_in[`RAM_ADDR_BITS-1:0]>>2);

    reg [31:0] d_out;

    always @(posedge clk) begin  
        if (addr < 12'd1024) begin
            if (addr_in[`STARTING_ADDR_BIT-1]) begin
                if (rd) begin
                    if(addr=='d0)
                        d_out <= 32'h`TANISHA;
                    else if(addr=='d1)
                        d_out <= 32'h`ANANT;
                    else if(addr=='d2)
                        d_out <= 32'h`EESHA;
                end
            end  
            else begin      
                if (we[0])
                    ram[addr][7:0] <= data_in[7:0];
                if (we[1])
                    ram[addr][15:8] <= data_in[15:8];                    
                if (we[2])
                    ram[addr][23:16] <= data_in[23:16];
                if (we[3])
                    ram[addr][31:24] <= data_in[31:24];
                if (rd)
                    d_out <= ram[addr];
            end
        end
    end
    
    assign data_out = d_out;
    
endmodule
module DMem(
    input wire clk,
    input wire rd,
    input wire [3:0] we,
    input wire [31:0] addr_in,
    input wire [31:0] data_in,
    output wire [31:0] data_out
);



    reg [31:0] ram [0:`RAM_LENGTH_WORDS-1];


    wire [11:0] addr = (addr_in[`RAM_ADDR_BITS-1:0]>>2);

    reg [31:0] d_out;

    always @(posedge clk) begin  
        if (addr < 12'd1024) begin
            if (addr_in[`STARTING_ADDR_BIT-1]) begin
                if (rd) begin
                    if(addr=='d0)
                        d_out <= 32'h`TANISHA;
                    else if(addr=='d1)
                        d_out <= 32'h`ANANT;
                    else if(addr=='d2)
                        d_out <= 32'h`EESHA;
                end
            end  
            else begin      
                if (we[0])
                    ram[addr][7:0] <= data_in[7:0];
                if (we[1])
                    ram[addr][15:8] <= data_in[15:8];                    
                if (we[2])
                    ram[addr][23:16] <= data_in[23:16];
                if (we[3])
                    ram[addr][31:24] <= data_in[31:24];
                if (rd)
                    d_out <= ram[addr];
            end
        end
    end
    
    assign data_out = d_out;
    
endmodule