data/full_repos/permissive/494148647/src/mb_soc_top_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:8: Cannot find include file: sdram.vh\n`include "sdram.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/sdram.vh\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/sdram.vh.v\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/sdram.vh.sv\n             sdram.vh\n             sdram.vh.v\n             sdram.vh.sv\n             obj_dir/sdram.vh\n             obj_dir/sdram.vh.v\n             obj_dir/sdram.vh.sv\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:45: Define or directive not defined: \'`SDRAM_WIRE_DECLS\'\n    `SDRAM_WIRE_DECLS;\n    ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:111: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("mb_soc_top_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:112: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(2, mb_soc_top_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #1e6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:120: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top_tb.v:122: syntax error, unexpected \'@\'\n        repeat(16) @(posedge clk);\n                   ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module mb_soc_top_tb#(
    parameter GCNT_BITS = 56,
    parameter PDM_COUNT = 4,
    parameter IRQ_COUNT = 8
    ) ( );



    reg clk;

    wire rst_n;

    reg cclk;

    wire [7:0]led;

    wire spi_miso;
    reg spi_ss;
    reg spi_mosi;
    reg spi_sck;

    wire [3:0] spi_channel;

    reg avr_tx;
    wire avr_rx;
    reg avr_rx_busy;

    wire uart0_tx;
    reg  uart0_rx;

    wire [PDM_COUNT-1:0]pdm;


    `SDRAM_WIRE_DECLS;

    integer seed = 377;
    integer err_count = 0;

    mb_soc_top#(
        .GCNT_BITS(GCNT_BITS),
        .PDM_COUNT(PDM_COUNT),
        .IRQ_COUNT(IRQ_COUNT)
    ) DUT (
        .clk(clk),
        .rst_n(rst_n),
        .cclk(cclk),
        .led(led),
        .spi_miso(spi_miso),
        .spi_ss(spi_ss),
        .spi_mosi(spi_mosi),
        .spi_sck(spi_sck),
        .spi_channel(spi_channel),
        .avr_tx(avr_tx),
        .avr_rx(avr_rx),
        .avr_rx_busy(avr_rx_busy),
        .uart0_tx(uart0_tx),
        .uart0_rx(uart0_rx),
        .pdm(pdm),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_dqm(sdram_dqm),
        .sdram_cs(sdram_cs),
        .sdram_we(sdram_we),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq)
    );


    btn_bounce#(
        .ACTIVE_STATE(1'b0)
    ) button (
        .btn(rst_n)
    );


    mt48lc32m8a2 ram_model (
        .Dq(sdram_dq),
        .Addr(sdram_a),
        .Ba(sdram_ba),
        .Clk(sdram_clk),
        .Cke(sdram_cle),
        .Cs_n(sdram_cs),
        .Ras_n(sdram_ras),
        .Cas_n(sdram_cas),
        .We_n(sdram_we),
        .Dqm(sdram_dqm)
    );


    initial begin
        clk = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("mb_soc_top_tb.vcd");
        $dumpvars(2, mb_soc_top_tb);


        #1e6;
        button.press(50e6, seed);


        #100000;
        @(posedge clk);

        repeat(16) @(posedge clk);
        $display("testbench completed with %d errors", err_count);
        $finish;
    end
endmodule
module mb_soc_top_tb#(
    parameter GCNT_BITS = 56,
    parameter PDM_COUNT = 4,
    parameter IRQ_COUNT = 8
    ) ( );




    reg clk;

    wire rst_n;

    reg cclk;

    wire [7:0]led;

    wire spi_miso;
    reg spi_ss;
    reg spi_mosi;
    reg spi_sck;

    wire [3:0] spi_channel;

    reg avr_tx;
    wire avr_rx;
    reg avr_rx_busy;

    wire uart0_tx;
    reg  uart0_rx;

    wire [PDM_COUNT-1:0]pdm;


    `SDRAM_WIRE_DECLS;

    integer seed = 377;
    integer err_count = 0;

    mb_soc_top#(
        .GCNT_BITS(GCNT_BITS),
        .PDM_COUNT(PDM_COUNT),
        .IRQ_COUNT(IRQ_COUNT)
    ) DUT (
        .clk(clk),
        .rst_n(rst_n),
        .cclk(cclk),
        .led(led),
        .spi_miso(spi_miso),
        .spi_ss(spi_ss),
        .spi_mosi(spi_mosi),
        .spi_sck(spi_sck),
        .spi_channel(spi_channel),
        .avr_tx(avr_tx),
        .avr_rx(avr_rx),
        .avr_rx_busy(avr_rx_busy),
        .uart0_tx(uart0_tx),
        .uart0_rx(uart0_rx),
        .pdm(pdm),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_dqm(sdram_dqm),
        .sdram_cs(sdram_cs),
        .sdram_we(sdram_we),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq)
    );


    btn_bounce#(
        .ACTIVE_STATE(1'b0)
    ) button (
        .btn(rst_n)
    );


    mt48lc32m8a2 ram_model (
        .Dq(sdram_dq),
        .Addr(sdram_a),
        .Ba(sdram_ba),
        .Clk(sdram_clk),
        .Cke(sdram_cle),
        .Cs_n(sdram_cs),
        .Ras_n(sdram_ras),
        .Cas_n(sdram_cas),
        .We_n(sdram_we),
        .Dqm(sdram_dqm)
    );


    initial begin
        clk = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("mb_soc_top_tb.vcd");
        $dumpvars(2, mb_soc_top_tb);


        #1e6;
        button.press(50e6, seed);


        #100000;
        @(posedge clk);

        repeat(16) @(posedge clk);
        $display("testbench completed with %d errors", err_count);
        $finish;
    end
endmodule