data/full_repos/permissive/450072296/verilog/rtl/jku_logo.v
data/verilator_xmls/d195c6fa-f76c-42ff-83f9-33ad0b5e72c5.xml
module jku_logo(
	input jku
);


wire dummy1 = jku;


endmodule
module jku_logo(
	input jku
);



wire dummy1 = jku;


endmodule