data/full_repos/permissive/463395574/alu.v
1: b'%Error: data/full_repos/permissive/463395574/alu.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/alu.v:6: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0]   a,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:7: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0]   b,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:10: Define or directive not defined: \'`WORD_LEN\'\n    output reg [`WORD_LEN-1:0] ALUOut\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:14: Define or directive not defined: \'`ALU_CTRL_MOVEA\'\n        `ALU_CTRL_MOVEA:  ALUOut <= a;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:14: syntax error, unexpected \':\', expecting endcase\n        `ALU_CTRL_MOVEA:  ALUOut <= a;\n                       ^\n%Error: data/full_repos/permissive/463395574/alu.v:15: Define or directive not defined: \'`ALU_CTRL_ADD\'\n        `ALU_CTRL_ADD:  ALUOut <= a + b;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:17: Define or directive not defined: \'`ALU_CTRL_OR\'\n        `ALU_CTRL_OR:   ALUOut <= a | b;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:18: Define or directive not defined: \'`ALU_CTRL_XOR\'\n        `ALU_CTRL_XOR:   ALUOut <= a ^ b;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:19: Define or directive not defined: \'`ALU_CTRL_AND\'\n        `ALU_CTRL_AND:      ALUOut <= a & b;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:21: Define or directive not defined: \'`ALU_CTRL_SLL\'\n        `ALU_CTRL_SLL:      ALUOut <= a << (b & 5\'b11111);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:22: Define or directive not defined: \'`ALU_CTRL_SRL\'\n        `ALU_CTRL_SRL:      ALUOut <= a >> (b & 5\'b11111);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:23: Define or directive not defined: \'`ALU_CTRL_SRA\'\n        `ALU_CTRL_SRA:      ALUOut <= $signed(a) >>> (b & 5\'b11111);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:25: Define or directive not defined: \'`ALU_CTRL_SUB\'\n        `ALU_CTRL_SUB:      ALUOut <= a - b;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:26: Define or directive not defined: \'`ALU_CTRL_SLT\'\n        `ALU_CTRL_SLT:      ALUOut <= $signed(a) < $signed(b) ? 1 : 0;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:27: Define or directive not defined: \'`ALU_CTRL_SLTU\'\n        `ALU_CTRL_SLTU:     ALUOut <= a < b ? 1 : 0;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:29: Define or directive not defined: \'`ALU_CTRL_LUI\'\n        `ALU_CTRL_LUI:  ALUOut <= b;  \n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:30: Define or directive not defined: \'`ALU_CTRL_AUIPC\'\n        `ALU_CTRL_AUIPC: ALUOut <= a + $signed(b);  \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/alu.v:33: Define or directive not defined: \'`WORD_LEN\'\n        default:    ALUOut <= `WORD_LEN\'b0;\n                              ^~~~~~~~~\n%Error: Cannot continue\n'
module ALU(
    input [`WORD_LEN-1:0]   a,
    input [`WORD_LEN-1:0]   b,
    input [3:0]             ALUCtrl,

    output reg [`WORD_LEN-1:0] ALUOut
);
    always @(*)
    case(ALUCtrl)
        `ALU_CTRL_MOVEA: 	ALUOut <= a;
        `ALU_CTRL_ADD:		ALUOut <= a + b;

        `ALU_CTRL_OR: 		ALUOut <= a | b;
        `ALU_CTRL_XOR: 		ALUOut <= a ^ b;
        `ALU_CTRL_AND:      ALUOut <= a & b;

        `ALU_CTRL_SLL:      ALUOut <= a << (b & 5'b11111);
        `ALU_CTRL_SRL:      ALUOut <= a >> (b & 5'b11111);
        `ALU_CTRL_SRA:      ALUOut <= $signed(a) >>> (b & 5'b11111);

        `ALU_CTRL_SUB:      ALUOut <= a - b;
        `ALU_CTRL_SLT:      ALUOut <= $signed(a) < $signed(b) ? 1 : 0;
        `ALU_CTRL_SLTU:     ALUOut <= a < b ? 1 : 0;

        `ALU_CTRL_LUI:		ALUOut <= b;
        `ALU_CTRL_AUIPC:	ALUOut <= a + $signed(b);


        default: 			ALUOut <= `WORD_LEN'b0;
    endcase
endmodule
module ALU(
    input [`WORD_LEN-1:0]   a,
    input [`WORD_LEN-1:0]   b,
    input [3:0]             ALUCtrl,

    output reg [`WORD_LEN-1:0] ALUOut
);

    always @(*)
    case(ALUCtrl)
        `ALU_CTRL_MOVEA: 	ALUOut <= a;
        `ALU_CTRL_ADD:		ALUOut <= a + b;

        `ALU_CTRL_OR: 		ALUOut <= a | b;
        `ALU_CTRL_XOR: 		ALUOut <= a ^ b;
        `ALU_CTRL_AND:      ALUOut <= a & b;

        `ALU_CTRL_SLL:      ALUOut <= a << (b & 5'b11111);
        `ALU_CTRL_SRL:      ALUOut <= a >> (b & 5'b11111);
        `ALU_CTRL_SRA:      ALUOut <= $signed(a) >>> (b & 5'b11111);

        `ALU_CTRL_SUB:      ALUOut <= a - b;
        `ALU_CTRL_SLT:      ALUOut <= $signed(a) < $signed(b) ? 1 : 0;
        `ALU_CTRL_SLTU:     ALUOut <= a < b ? 1 : 0;

        `ALU_CTRL_LUI:		ALUOut <= b;
        `ALU_CTRL_AUIPC:	ALUOut <= a + $signed(b);


        default: 			ALUOut <= `WORD_LEN'b0;
    endcase
endmodule