data/full_repos/permissive/43264243/ptrfifo.v
1: b"%Error: data/full_repos/permissive/43264243/ptrfifo.v:62: Cannot find file containing module: 'counter'\n counter ipctr(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/43264243/ptrfifo.v:71: Cannot find file containing module: 'counter'\n counter opctr(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/ptrfifo.v:80: Cannot find file containing module: 'counter'\n counter accounting(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/ptrfifo.v:89: Cannot find file containing module: 'dualportram'\n dualportram dpram(\n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ptrfifo #( 

	parameter WIDTH = 64, 
	parameter DEPTH = 6
	) (

	input wire clk,
	input wire rstn,
	input wire loaden,
	input wire unloaden,
	input wire [WIDTH-1: 0] datain,
	output wire empty,
	output wire full,
	output wire [WIDTH-1: 0] dataout,
	output wire [DEPTH-1: 0] itemsinfifo
	);
	
	wire [DEPTH-1: 0] inptr;
	wire [DEPTH-1: 0] outptr;
	wire [WIDTH-1: 0] a_dataout;
	wire [WIDTH-1: 0] b_datain = 0;
	wire [DEPTH-1: 0] itemsinfifo_int;
	wire qual_loaden;
	wire qual_unloaden;
	reg empty_int;
	reg full_int;
	
	
	

	counter ipctr(
	.clk(clk),
	.up(qual_loaden),
	.down(1'b0),
	.rstn(rstn),
	.count(inptr)
	);
	

	counter opctr(
	.clk(clk),
	.up(qual_unloaden),
	.down(1'b0),
	.rstn(rstn),
	.count(outptr)
	);
	

	counter accounting(
	.clk(clk),
	.up(qual_loaden),
	.down(qual_unloaden),
	.rstn(rstn),
	.count(itemsinfifo_int)
	);
	

	dualportram dpram(
	.clk_a(clk),
	.we_a(qual_loaden),
	.addr_a(inptr),
	.din_a(datain),
	.dout_a(a_dataout),
	
	.clk_b(clk),
	.we_b(1'b0),
	.addr_b(outptr),
	.din_b(b_datain),
	.dout_b(dataout)
	);
	

	defparam dpram.DEPTH = DEPTH;
	defparam dpram.WIDTH = WIDTH;
	defparam ipctr.WIDTH = DEPTH;
	defparam opctr.WIDTH = DEPTH;
	defparam accounting.WIDTH = DEPTH;
	
	assign empty = empty_int;
	assign full = full_int;
	assign qual_loaden = loaden & ~full_int;
	assign qual_unloaden = unloaden & ~empty_int;
	assign itemsinfifo = itemsinfifo_int;
	

	always @(*) begin
		empty_int <= 0;
		full_int <= 0;
		if(itemsinfifo_int == 0) begin
			empty_int <= 1;
		end	
		if(itemsinfifo_int == (2**DEPTH) - 1) begin
			full_int <= 1;
		end
	end
	

endmodule
module ptrfifo #( 

	parameter WIDTH = 64, 
	parameter DEPTH = 6
	) (

	input wire clk,
	input wire rstn,
	input wire loaden,
	input wire unloaden,
	input wire [WIDTH-1: 0] datain,
	output wire empty,
	output wire full,
	output wire [WIDTH-1: 0] dataout,
	output wire [DEPTH-1: 0] itemsinfifo
	);

	
	wire [DEPTH-1: 0] inptr;
	wire [DEPTH-1: 0] outptr;
	wire [WIDTH-1: 0] a_dataout;
	wire [WIDTH-1: 0] b_datain = 0;
	wire [DEPTH-1: 0] itemsinfifo_int;
	wire qual_loaden;
	wire qual_unloaden;
	reg empty_int;
	reg full_int;
	
	
	

	counter ipctr(
	.clk(clk),
	.up(qual_loaden),
	.down(1'b0),
	.rstn(rstn),
	.count(inptr)
	);
	

	counter opctr(
	.clk(clk),
	.up(qual_unloaden),
	.down(1'b0),
	.rstn(rstn),
	.count(outptr)
	);
	

	counter accounting(
	.clk(clk),
	.up(qual_loaden),
	.down(qual_unloaden),
	.rstn(rstn),
	.count(itemsinfifo_int)
	);
	

	dualportram dpram(
	.clk_a(clk),
	.we_a(qual_loaden),
	.addr_a(inptr),
	.din_a(datain),
	.dout_a(a_dataout),
	
	.clk_b(clk),
	.we_b(1'b0),
	.addr_b(outptr),
	.din_b(b_datain),
	.dout_b(dataout)
	);
	

	defparam dpram.DEPTH = DEPTH;
	defparam dpram.WIDTH = WIDTH;
	defparam ipctr.WIDTH = DEPTH;
	defparam opctr.WIDTH = DEPTH;
	defparam accounting.WIDTH = DEPTH;
	
	assign empty = empty_int;
	assign full = full_int;
	assign qual_loaden = loaden & ~full_int;
	assign qual_unloaden = unloaden & ~empty_int;
	assign itemsinfifo = itemsinfifo_int;
	

	always @(*) begin
		empty_int <= 0;
		full_int <= 0;
		if(itemsinfifo_int == 0) begin
			empty_int <= 1;
		end	
		if(itemsinfifo_int == (2**DEPTH) - 1) begin
			full_int <= 1;
		end
	end
	

endmodule