data/full_repos/permissive/52871302/mojo/ch08_alarm/src/alarm.v
data/verilator_xmls/b1b77850-de38-4b8b-b931-b1e143271972.xml
module alarm(
    input CLK,
    input enable,
    output reg BUZZER
    );

reg [25:0] count;

always @(posedge CLK) 
begin
  count <= count + 1;
  if ((count == 26'd50000) & enable)
  begin
    BUZZER <= ~ BUZZER;
    count <= 0;
  end
end

endmodule
module alarm(
    input CLK,
    input enable,
    output reg BUZZER
    );


reg [25:0] count;

always @(posedge CLK) 
begin
  count <= count + 1;
  if ((count == 26'd50000) & enable)
  begin
    BUZZER <= ~ BUZZER;
    count <= 0;
  end
end

endmodule