data/full_repos/permissive/42149584/Lab6-Part1/BaudRateGeneratorI2C.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part1/BaudRateGeneratorI2C.v:19: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance BaudRateGeneratorI2C\n  if (Reset == 1) begin baud_count <= 1\'b0; ClockI2C <= 1\'b1; end\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part1/BaudRateGeneratorI2C.v:20: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance BaudRateGeneratorI2C\n  else if(Enable == 0) begin  baud_count <= 1\'b0; ClockI2C <= 1\'b1; end\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part1/BaudRateGeneratorI2C.v:23: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance BaudRateGeneratorI2C\n    baud_count <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part1/BaudRateGeneratorI2C.v:21: Operator EQ expects 32 or 30 bits on the LHS, but LHS\'s VARREF \'baud_count\' generates 16 bits.\n                                                                                        : ... In instance BaudRateGeneratorI2C\n  else if(baud_count == ClockFrequency/(BaudRate*3)) \n                     ^~\n%Error: Exiting due to 4 warning(s)\n'
module BaudRateGeneratorI2C(Enable, ClockI2C, Reset, clock, BaudRate, ClockFrequency);
	input [19:0] BaudRate;
	input [29:0] ClockFrequency;
	input clock, Reset, Enable;
	output reg ClockI2C;
	reg [15:0] baud_count;
	reg [15:0] counter;

	always @(posedge clock or posedge Reset)
		if (Reset == 1) begin baud_count <= 1'b0; ClockI2C <= 1'b1; end
		else if(Enable == 0) begin  baud_count <= 1'b0; ClockI2C <= 1'b1; end
		else if(baud_count == ClockFrequency/(BaudRate*3)) 
				begin
				baud_count <= 1'b0;
				ClockI2C <= ~ClockI2C;
				end
		else begin baud_count <= baud_count + 1'b1; end
endmodule
module BaudRateGeneratorI2C(Enable, ClockI2C, Reset, clock, BaudRate, ClockFrequency);

	input [19:0] BaudRate;
	input [29:0] ClockFrequency;
	input clock, Reset, Enable;
	output reg ClockI2C;
	reg [15:0] baud_count;
	reg [15:0] counter;

	always @(posedge clock or posedge Reset)
		if (Reset == 1) begin baud_count <= 1'b0; ClockI2C <= 1'b1; end
		else if(Enable == 0) begin  baud_count <= 1'b0; ClockI2C <= 1'b1; end
		else if(baud_count == ClockFrequency/(BaudRate*3)) 
				begin
				baud_count <= 1'b0;
				ClockI2C <= ~ClockI2C;
				end
		else begin baud_count <= baud_count + 1'b1; end
endmodule