data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:128: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'deoxys_rnd\'\nmodule deoxys_rnd ( \n       ^~~~~~~~~~\n                                                                                            : ... Top module \'aes_sbox\'\nmodule aes_sbox ( \n       ^~~~~~~~\n                                                                                            : ... Top module \'deoxys_lfsr2_16\'\nmodule deoxys_lfsr2_16 ( \n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'deoxys_lfsr3_16\'\nmodule deoxys_lfsr3_16 ( \n       ^~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:536: Little bit endian vector: MSB < LSB of bit range: 0:7\n   wire [0:7]         s, x;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:91: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                        : ... In instance deoxys_rnd\n         assign rndconstant[i] = constant[7+8*i:0+8*i];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:101: Operator XOR expects 128 bits on the RHS, but RHS\'s REPLICATE generates 120 bits.\n                                                                                         : ... In instance deoxys_rnd\n         assign rkey[i] = rndkey[i] ^ rndcnt[i] ^ rndtweak[i] ^\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:835: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                         : ... In instance deoxys_lfsr3_16\n            assign m[i+1][7+8*j:8*j] = {m[i][6]^m[i][0],m[i][7+8*j:8*j]};\n                                     ^\n%Error: Exiting due to 5 warning(s)\n'
module tweak2_expansion (

   ko,

   ki
   ) ;

   output [127:0] ko;
   input [127:0]  ki;

   wire [127:0]   kp;

   assign kp[127:120] = ki[ 23: 16];
   assign kp[119:112] = ki[ 15:  8];
   assign kp[111:104] = ki[  7:  0];
   assign kp[103: 96] = ki[ 31: 24];
   assign kp[ 95: 88] = ki[127:120];
   assign kp[ 87: 80] = ki[119:112];
   assign kp[ 79: 72] = ki[111:104];
   assign kp[ 71: 64] = ki[103: 96];
   assign kp[ 63: 56] = ki[ 71: 64];
   assign kp[ 55: 48] = ki[ 95: 88];
   assign kp[ 47: 40] = ki[ 87: 80];
   assign kp[ 39: 32] = ki[ 79: 72];
   assign kp[ 31: 24] = ki[ 47: 40];
   assign kp[ 23: 16] = ki[ 39: 32];
   assign kp[ 15:  8] = ki[ 63: 56];
   assign kp[  7:  0] = ki[ 55: 48];

   assign ko[127:120] = {kp[126:120],kp[127]^kp[125]};
   assign ko[119:112] = {kp[118:112],kp[119]^kp[117]};
   assign ko[111:104] = {kp[110:104],kp[111]^kp[109]};
   assign ko[103: 96] = {kp[102: 96],kp[103]^kp[101]};
   assign ko[ 95: 88] = {kp[ 94: 88],kp[ 95]^kp[ 93]};
   assign ko[ 87: 80] = {kp[ 86: 80],kp[ 87]^kp[ 85]};
   assign ko[ 79: 72] = {kp[ 78: 72],kp[ 79]^kp[ 77]};
   assign ko[ 71: 64] = {kp[ 70: 64],kp[ 71]^kp[ 69]};
   assign ko[ 63: 56] = {kp[ 62: 56],kp[ 63]^kp[ 61]};
   assign ko[ 55: 48] = {kp[ 54: 48],kp[ 55]^kp[ 53]};
   assign ko[ 47: 40] = {kp[ 46: 40],kp[ 47]^kp[ 45]};
   assign ko[ 39: 32] = {kp[ 38: 32],kp[ 39]^kp[ 37]};
   assign ko[ 31: 24] = {kp[ 30: 24],kp[ 31]^kp[ 29]};
   assign ko[ 23: 16] = {kp[ 22: 16],kp[ 23]^kp[ 21]};
   assign ko[ 15:  8] = {kp[ 14:  8],kp[ 15]^kp[ 13]};
   assign ko[  7:  0] = {kp[  6:  0],kp[  7]^kp[  5]};

endmodule
module tweak2_expansion (

   ko,

   ki
   ) ;


   output [127:0] ko;
   input [127:0]  ki;

   wire [127:0]   kp;

   assign kp[127:120] = ki[ 23: 16];
   assign kp[119:112] = ki[ 15:  8];
   assign kp[111:104] = ki[  7:  0];
   assign kp[103: 96] = ki[ 31: 24];
   assign kp[ 95: 88] = ki[127:120];
   assign kp[ 87: 80] = ki[119:112];
   assign kp[ 79: 72] = ki[111:104];
   assign kp[ 71: 64] = ki[103: 96];
   assign kp[ 63: 56] = ki[ 71: 64];
   assign kp[ 55: 48] = ki[ 95: 88];
   assign kp[ 47: 40] = ki[ 87: 80];
   assign kp[ 39: 32] = ki[ 79: 72];
   assign kp[ 31: 24] = ki[ 47: 40];
   assign kp[ 23: 16] = ki[ 39: 32];
   assign kp[ 15:  8] = ki[ 63: 56];
   assign kp[  7:  0] = ki[ 55: 48];

   assign ko[127:120] = {kp[126:120],kp[127]^kp[125]};
   assign ko[119:112] = {kp[118:112],kp[119]^kp[117]};
   assign ko[111:104] = {kp[110:104],kp[111]^kp[109]};
   assign ko[103: 96] = {kp[102: 96],kp[103]^kp[101]};
   assign ko[ 95: 88] = {kp[ 94: 88],kp[ 95]^kp[ 93]};
   assign ko[ 87: 80] = {kp[ 86: 80],kp[ 87]^kp[ 85]};
   assign ko[ 79: 72] = {kp[ 78: 72],kp[ 79]^kp[ 77]};
   assign ko[ 71: 64] = {kp[ 70: 64],kp[ 71]^kp[ 69]};
   assign ko[ 63: 56] = {kp[ 62: 56],kp[ 63]^kp[ 61]};
   assign ko[ 55: 48] = {kp[ 54: 48],kp[ 55]^kp[ 53]};
   assign ko[ 47: 40] = {kp[ 46: 40],kp[ 47]^kp[ 45]};
   assign ko[ 39: 32] = {kp[ 38: 32],kp[ 39]^kp[ 37]};
   assign ko[ 31: 24] = {kp[ 30: 24],kp[ 31]^kp[ 29]};
   assign ko[ 23: 16] = {kp[ 22: 16],kp[ 23]^kp[ 21]};
   assign ko[ 15:  8] = {kp[ 14:  8],kp[ 15]^kp[ 13]};
   assign ko[  7:  0] = {kp[  6:  0],kp[  7]^kp[  5]};

endmodule