data/full_repos/permissive/491934675/ECE251/cpu/cpu.v
1: b'%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:4: Cannot find include file: ../decoder/decoder.v\n`include "../decoder/decoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491934675/ECE251/cpu,data/full_repos/permissive/491934675/../decoder/decoder.v\n             data/full_repos/permissive/491934675/ECE251/cpu,data/full_repos/permissive/491934675/../decoder/decoder.v.v\n             data/full_repos/permissive/491934675/ECE251/cpu,data/full_repos/permissive/491934675/../decoder/decoder.v.sv\n             ../decoder/decoder.v\n             ../decoder/decoder.v.v\n             ../decoder/decoder.v.sv\n             obj_dir/../decoder/decoder.v\n             obj_dir/../decoder/decoder.v.v\n             obj_dir/../decoder/decoder.v.sv\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:5: Cannot find include file: ../instruction/imem.v\n`include "../instruction/imem.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:6: Cannot find include file: ../mux2in1out/mux221.v\n`include "../mux2in1out/mux221.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:7: Cannot find include file: ../ALU/ALU.v\n`include "../ALU/ALU.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:8: Cannot find include file: ../Buffer/8bitbuffer.v\n`include "../Buffer/8bitbuffer.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:9: Cannot find include file: ../instruction/ram.v\n`include "../instruction/ram.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:10: Cannot find include file: ../registerfile/regfile.v\n`include "../registerfile/regfile.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:11: Cannot find include file: ../controller/controller.v\n`include "../controller/controller.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:62: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("cpu.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/cpu/cpu.v:66: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, cpu);\n    ^~~~~~~~~\n%Error: Exiting due to 10 error(s), 1 warning(s)\n'
module cpu();


wire [15:0] instruction;
wire [3:0] opcode;
wire [2:0] opcode2, shiftamt;
wire [1:0] Rm, Rs1, Rs2;
wire [7:0] constant;
wire [7:0] outputofmem;
wire [7:0] regA, regB, alubuffer, data, databuffer, aluOut;
wire [1:0] aluflag, storedflag;
wire [7:0] pc;

reg clk;


wire jumpenable, regwrite, writetomem, bufenable, muxsel, ret0;

insdecoder instrucdecoder(instruction, opcode, opcode2, shiftamt, Rm, Rs1, Rs2, constant);
ALU alu1(opcode, shiftamt, regA, alubuffer, aluOut, aluflag);
buffer8bit buf1(data, bufenable, databuffer);
registers regis(regwrite, Rm, Rs1, Rs2, aluflag, databuffer, regA, regB, storedflag);
mux2in1 memorymux(muxsel, outputofmem, aluOut, data);
mux2in1 immediatemux(opcode[3], constant, regB, alubuffer);
ram dataram256(constant, regA, writetomem, writetomem, outputofmem);
Imem instructionmemory(pc, instruction);
controller maincontroller(clk, instruction, storedflag, pc, bufenable, regwrite, muxsel, jumpenable, ret0, writetomem);




always @(posedge clk ) begin
    if(ret0 == 1) begin
        $finish;
    end

end


initial begin
clk = 0;
end

always begin
    #10;
    clk = ~clk;
end

initial begin
    $dumpfile("cpu.vcd");



    $dumpvars(0, cpu);



    $display("finish");
end


endmodule
module cpu();



wire [15:0] instruction;
wire [3:0] opcode;
wire [2:0] opcode2, shiftamt;
wire [1:0] Rm, Rs1, Rs2;
wire [7:0] constant;
wire [7:0] outputofmem;
wire [7:0] regA, regB, alubuffer, data, databuffer, aluOut;
wire [1:0] aluflag, storedflag;
wire [7:0] pc;

reg clk;


wire jumpenable, regwrite, writetomem, bufenable, muxsel, ret0;

insdecoder instrucdecoder(instruction, opcode, opcode2, shiftamt, Rm, Rs1, Rs2, constant);
ALU alu1(opcode, shiftamt, regA, alubuffer, aluOut, aluflag);
buffer8bit buf1(data, bufenable, databuffer);
registers regis(regwrite, Rm, Rs1, Rs2, aluflag, databuffer, regA, regB, storedflag);
mux2in1 memorymux(muxsel, outputofmem, aluOut, data);
mux2in1 immediatemux(opcode[3], constant, regB, alubuffer);
ram dataram256(constant, regA, writetomem, writetomem, outputofmem);
Imem instructionmemory(pc, instruction);
controller maincontroller(clk, instruction, storedflag, pc, bufenable, regwrite, muxsel, jumpenable, ret0, writetomem);




always @(posedge clk ) begin
    if(ret0 == 1) begin
        $finish;
    end

end


initial begin
clk = 0;
end

always begin
    #10;
    clk = ~clk;
end

initial begin
    $dumpfile("cpu.vcd");



    $dumpvars(0, cpu);



    $display("finish");
end


endmodule