data/full_repos/permissive/431362747/Processor-prev-versions/Vivado Project/ImageDownSample.srcs/sources_1/new/MDR.v
1: b'%Error: Cannot find file containing module: Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n        ... Looked in:\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/431362747/Processor-prev-versions/Vivado\n%Error: Cannot find file containing module: Project/ImageDownSample.srcs/sources_1/new/MDR.v\n%Error: Exiting due to 3 error(s)\n'
module MDR(
    input clk,
    input w_en,
    input write_en,
    input read_en,
    output reg [27:0] data_out,
    input [27:0] data_in,
    input [7:0] DRam_in,
    output reg [7:0] DRam_out
    );
    
    always @(posedge clk)
    
    begin
        if (w_en==1)
            data_out<=data_in;
            else if (read_en)
            data_out<= {20'b0000000000,DRam_in};
            else if (write_en)
            DRam_out<=data_in[7:0];
        end
                
    
endmodule
module MDR(
    input clk,
    input w_en,
    input write_en,
    input read_en,
    output reg [27:0] data_out,
    input [27:0] data_in,
    input [7:0] DRam_in,
    output reg [7:0] DRam_out
    );

    
    always @(posedge clk)
    
    begin
        if (w_en==1)
            data_out<=data_in;
            else if (read_en)
            data_out<= {20'b0000000000,DRam_in};
            else if (write_en)
            DRam_out<=data_in[7:0];
        end
                
    
endmodule