data/full_repos/permissive/458737381/src/verilog-parser/tests/logical_operators.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/logical_operators.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module logical_operators();

initial begin

  $display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1));
  $display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0));
  $display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx));

  $display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0));
  $display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0));
  $display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));

  $display ("! 1'b1       = %b", (!  1'b1));
  $display ("! 1'b0       = %b", (!  1'b0));
  #10 $finish;
end

endmodule
module logical_operators();


initial begin

  $display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1));
  $display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0));
  $display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx));

  $display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0));
  $display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0));
  $display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));

  $display ("! 1'b1       = %b", (!  1'b1));
  $display ("! 1'b0       = %b", (!  1'b0));
  #10 $finish;
end

endmodule