data/full_repos/permissive/476411617/Tile.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:69: Little bit endian vector: MSB < LSB of bit range: 0:31\ninput[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WIN;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:70: Little bit endian vector: MSB < LSB of bit range: 0:31\ninput[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EIN;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:71: Little bit endian vector: MSB < LSB of bit range: 0:31\ninput[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SIN;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:72: Little bit endian vector: MSB < LSB of bit range: 0:31\ninput[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NIN;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:73: Little bit endian vector: MSB < LSB of bit range: 0:31\noutput[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WOUT;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:74: Little bit endian vector: MSB < LSB of bit range: 0:31\noutput[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EOUT;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:75: Little bit endian vector: MSB < LSB of bit range: 0:31\noutput[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SOUT;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/Tile.v:76: Little bit endian vector: MSB < LSB of bit range: 0:31\noutput[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NOUT;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Tile.v:100: Bit extraction of array[1:0] requires 1 bit index, not 8 bits.\n                                                               : ... In instance Tile\nassign DOA = wDOA[BRAM_i][BRAM_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Tile.v:100: Bit extraction of array[1:0] requires 1 bit index, not 8 bits.\n                                                               : ... In instance Tile\nassign DOA = wDOA[BRAM_i][BRAM_j];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Tile.v:101: Bit extraction of array[1:0] requires 1 bit index, not 8 bits.\n                                                               : ... In instance Tile\nassign DOB = wDOB[BRAM_i][BRAM_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Tile.v:101: Bit extraction of array[1:0] requires 1 bit index, not 8 bits.\n                                                               : ... In instance Tile\nassign DOB = wDOB[BRAM_i][BRAM_j];\n                         ^\n%Error: data/full_repos/permissive/476411617/Tile.v:104: Cannot find file containing module: \'BS_Controller\'\nBS_Controller #(MAX_WORD_LENGTH, Slice_Size) FSM\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BS_Controller\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BS_Controller.v\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BS_Controller.sv\n             BS_Controller\n             BS_Controller.v\n             BS_Controller.sv\n             obj_dir/BS_Controller\n             obj_dir/BS_Controller.v\n             obj_dir/BS_Controller.sv\n%Error: data/full_repos/permissive/476411617/Tile.v:143: Cannot find file containing module: \'BS_PE_Block\'\n  BS_PE_Block #(TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) block \n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 12 warning(s)\n'
module Tile #(parameter TILE_DIM = 2, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)(
    clk, 
    reset,
    start,
    instruction,
	external,
    BRAM_i,
    BRAM_j,
 	WEA,
    WEB,
    ADDRA,
    ADDRB,
    DIA,
    DIB,
    DOA,
    DOB,
    EIN,
	WIN,
	NIN,
    SIN,  
    EOUT,
	WOUT,
    NOUT,
    SOUT
    );


input clk;
input reset;
input start;
input external;
wire[3:0] alu_op;
input[31:0] instruction;
input[7:0] BRAM_i;
input[7:0] BRAM_j;
input WEA;
input WEB;
input[9:0] ADDRA;
input[9:0] ADDRB;
input[15:0] DIA;
input[15:0] DIB;
output[15:0] DOA;
output[15:0] DOB;
input[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WIN;
input[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EIN;
input[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SIN;
input[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NIN;
output[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WOUT;
output[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EOUT;
output[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SOUT;
output[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NOUT;


wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;


wire[9:0] count;
wire[2:0] state;
wire [31:0] rs1_cnt;
wire [31:0] rs2_cnt;

wire[(Slice_Size*PE_H*2-1):0] EtoW[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_H*2-1):0] WtoE[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_W*2-1):0] StoN[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_W*2-1):0] NtoS[TILE_DIM-1:0][TILE_DIM-1:0];

wire[15:0] wDOA[TILE_DIM-1:0][TILE_DIM-1:0];
wire[15:0] wDOB[TILE_DIM-1:0][TILE_DIM-1:0];

assign DOA = wDOA[BRAM_i][BRAM_j];
assign DOB = wDOB[BRAM_i][BRAM_j];


BS_Controller #(MAX_WORD_LENGTH, Slice_Size) FSM
		(
			clk, 
			reset,
			start,
			instruction,

			alu_op,

			wea,
			web,
			addra, 
			addrb,

			east,	
			west,	
			south,	
			north,
			east_mode,
			west_mode,
			south_mode,
			north_mode,
			

			count,
			state,
			rs1_cnt,
			rs2_cnt
		);


generate

genvar gi;
genvar gj;

for (gi=0; gi<TILE_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<TILE_DIM; gj=gj+1) begin : COL

		BS_PE_Block #(TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) block 
		(
			clk,
			reset,


			alu_op,

			(gi==BRAM_i && gj==BRAM_j? (external? WEA : wea) : wea),
			(gi==BRAM_i && gj==BRAM_j? (external? WEB : web) : web),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRA : addra) : addra),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRB : addrb) : addrb),
            gi==BRAM_i && gj==BRAM_j? DIA : 16'hzzzz,
            gi==BRAM_i && gj==BRAM_j? DIB : 16'hzzzz,
		    wDOA[gi][gj],
            wDOB[gi][gj],
            external,

			count,


			state,

			east,	
			west,	
			south,		
			north,		





			gj==TILE_DIM-1              ? EIN[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] : WtoE[gi][gj+1],
			gj==0                   ? WIN[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] : EtoW[gi][gj-1],
			gi==0   			    ? NIN[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] : StoN[gi-1][gj],
			gi==TILE_DIM-1              ? SIN[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] : NtoS[gi+1][gj],
		    EtoW[gi][gj],
			WtoE[gi][gj],
			NtoS[gi][gj],
			StoN[gi][gj],
			
			rs1_cnt,
			rs2_cnt
		);
		assign EOUT[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] = EtoW[gi][TILE_DIM-1];
		assign WOUT[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] = WtoE[gi][0];
		assign SOUT[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] = StoN[TILE_DIM-1][gj];
		assign NOUT[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] = NtoS[0][gj];
	end
  end
  
endgenerate
endmodule
module Tile #(parameter TILE_DIM = 2, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)(
    clk, 
    reset,
    start,
    instruction,
	external,
    BRAM_i,
    BRAM_j,
 	WEA,
    WEB,
    ADDRA,
    ADDRB,
    DIA,
    DIB,
    DOA,
    DOB,
    EIN,
	WIN,
	NIN,
    SIN,  
    EOUT,
	WOUT,
    NOUT,
    SOUT
    );



input clk;
input reset;
input start;
input external;
wire[3:0] alu_op;
input[31:0] instruction;
input[7:0] BRAM_i;
input[7:0] BRAM_j;
input WEA;
input WEB;
input[9:0] ADDRA;
input[9:0] ADDRB;
input[15:0] DIA;
input[15:0] DIB;
output[15:0] DOA;
output[15:0] DOB;
input[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WIN;
input[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EIN;
input[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SIN;
input[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NIN;
output[0:TILE_DIM*(Slice_Size*PE_H*2)-1] WOUT;
output[0:TILE_DIM*(Slice_Size*PE_H*2)-1] EOUT;
output[0:TILE_DIM*(Slice_Size*PE_W*2)-1] SOUT;
output[0:TILE_DIM*(Slice_Size*PE_W*2)-1] NOUT;


wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;


wire[9:0] count;
wire[2:0] state;
wire [31:0] rs1_cnt;
wire [31:0] rs2_cnt;

wire[(Slice_Size*PE_H*2-1):0] EtoW[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_H*2-1):0] WtoE[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_W*2-1):0] StoN[TILE_DIM-1:0][TILE_DIM-1:0];
wire[(Slice_Size*PE_W*2-1):0] NtoS[TILE_DIM-1:0][TILE_DIM-1:0];

wire[15:0] wDOA[TILE_DIM-1:0][TILE_DIM-1:0];
wire[15:0] wDOB[TILE_DIM-1:0][TILE_DIM-1:0];

assign DOA = wDOA[BRAM_i][BRAM_j];
assign DOB = wDOB[BRAM_i][BRAM_j];


BS_Controller #(MAX_WORD_LENGTH, Slice_Size) FSM
		(
			clk, 
			reset,
			start,
			instruction,

			alu_op,

			wea,
			web,
			addra, 
			addrb,

			east,	
			west,	
			south,	
			north,
			east_mode,
			west_mode,
			south_mode,
			north_mode,
			

			count,
			state,
			rs1_cnt,
			rs2_cnt
		);


generate

genvar gi;
genvar gj;

for (gi=0; gi<TILE_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<TILE_DIM; gj=gj+1) begin : COL

		BS_PE_Block #(TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) block 
		(
			clk,
			reset,


			alu_op,

			(gi==BRAM_i && gj==BRAM_j? (external? WEA : wea) : wea),
			(gi==BRAM_i && gj==BRAM_j? (external? WEB : web) : web),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRA : addra) : addra),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRB : addrb) : addrb),
            gi==BRAM_i && gj==BRAM_j? DIA : 16'hzzzz,
            gi==BRAM_i && gj==BRAM_j? DIB : 16'hzzzz,
		    wDOA[gi][gj],
            wDOB[gi][gj],
            external,

			count,


			state,

			east,	
			west,	
			south,		
			north,		





			gj==TILE_DIM-1              ? EIN[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] : WtoE[gi][gj+1],
			gj==0                   ? WIN[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] : EtoW[gi][gj-1],
			gi==0   			    ? NIN[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] : StoN[gi-1][gj],
			gi==TILE_DIM-1              ? SIN[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] : NtoS[gi+1][gj],
		    EtoW[gi][gj],
			WtoE[gi][gj],
			NtoS[gi][gj],
			StoN[gi][gj],
			
			rs1_cnt,
			rs2_cnt
		);
		assign EOUT[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] = EtoW[gi][TILE_DIM-1];
		assign WOUT[(Slice_Size*PE_H*2)*gi+:(Slice_Size*PE_H*2)] = WtoE[gi][0];
		assign SOUT[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] = StoN[TILE_DIM-1][gj];
		assign NOUT[(Slice_Size*PE_W*2)*gj+:(Slice_Size*PE_W*2)] = NtoS[0][gj];
	end
  end
  
endgenerate
endmodule