data/full_repos/permissive/497337299/basics/tb/tb_count4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:7: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk; \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #0 clk=0; rst=0; ld=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #20     rst=1; ld=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #20     rst=1; ld=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #20     rst=1; ld=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #20     rst=1; ld=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #20     rst=0; ld=0;    \n        ^\n%Error: data/full_repos/permissive/497337299/basics/tb/tb_count4.v:5: Cannot find file containing module: \'count4\'\n    count4 dut (.clk(clk),.ld(ld),.rst(rst),.q(q));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/count4\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/count4.v\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/count4.sv\n             count4\n             count4.v\n             count4.sv\n             obj_dir/count4\n             obj_dir/count4.v\n             obj_dir/count4.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_count4 ();
    reg clk,ld,rst;
    wire [3:0] q;
    count4 dut (.clk(clk),.ld(ld),.rst(rst),.q(q));
    
    always #5 clk = ~clk; 
    initial begin
        #0 clk=0; rst=0; ld=0;
        #20     rst=1; ld=0;
        #20     rst=1; ld=0;
        #20     rst=1; ld=1;
        #20     rst=1; ld=0;
        #20     rst=0; ld=0;    
    end
    endmodule
module tb_count4 ();

    reg clk,ld,rst;
    wire [3:0] q;
    count4 dut (.clk(clk),.ld(ld),.rst(rst),.q(q));
    
    always #5 clk = ~clk; 
    initial begin
        #0 clk=0; rst=0; ld=0;
        #20     rst=1; ld=0;
        #20     rst=1; ld=0;
        #20     rst=1; ld=1;
        #20     rst=1; ld=0;
        #20     rst=0; ld=0;    
    end
    endmodule