data/full_repos/permissive/524567962/designs/Mod4Counter/Mod4_Counter.sv
data/verilator_xmls/b5c47d64-640b-43a7-b96f-a2feffde785b.xml
module flop(
  input logic d, clk, reset,

  output logic q, qn
);

  always_ff @(posedge clk, posedge reset)
  begin
    if (reset)
    begin
      q <= 0;
      qn <= 1;
    end
    else
    begin
      q  <= d;
      qn <= ~d;
    end
  end
endmodule
module flop(
  input logic d, clk, reset,

  output logic q, qn
);


  always_ff @(posedge clk, posedge reset)
  begin
    if (reset)
    begin
      q <= 0;
      qn <= 1;
    end
    else
    begin
      q  <= d;
      qn <= ~d;
    end
  end
endmodule