data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/Register.v
data/verilator_xmls/fd355984-9c36-4291-894a-e27117f3e94c.xml
module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
reg [31:0] d;
assign OUT = d;
always@(negedge Clk)
begin
	if(Load)
		d=IN;
end

always@(Reset)
	d=0;

endmodule
module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);

reg [31:0] d;
assign OUT = d;
always@(negedge Clk)
begin
	if(Load)
		d=IN;
end

always@(Reset)
	d=0;

endmodule