data/full_repos/permissive/497337299/basics/src/dff_gates.v
data/verilator_xmls/f0cf1c70-c144-4763-ada7-f1860471f9ab.xml
module dff_gates (
    input x,clk,rst,
    output z
);
    reg a,b,c ;

    always @ (posedge clk,negedge rst )begin
        if (rst==0) begin
        a <= 0;
        end
        else begin
            a <= x ^ a ;
        end 
    end

    always @ (posedge clk, negedge rst)begin
        if (rst==0)begin
            b <= 0;
        end
        else begin
            b <= x & ~b;
        end
    end

    always @ (posedge clk, negedge rst)begin
        if (rst==0)begin
            c <= 0;
        end
        else begin
            c <= x | ~c;
        end
    end

    assign z = ~(a | b | c);

endmodule
module dff_gates (
    input x,clk,rst,
    output z
);

    reg a,b,c ;

    always @ (posedge clk,negedge rst )begin
        if (rst==0) begin
        a <= 0;
        end
        else begin
            a <= x ^ a ;
        end 
    end

    always @ (posedge clk, negedge rst)begin
        if (rst==0)begin
            b <= 0;
        end
        else begin
            b <= x & ~b;
        end
    end

    always @ (posedge clk, negedge rst)begin
        if (rst==0)begin
            c <= 0;
        end
        else begin
            c <= x | ~c;
        end
    end

    assign z = ~(a | b | c);

endmodule