data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_full_adder_gates.v
data/verilator_xmls/ae7679d5-e9ca-416d-b8e8-544eedfdab85.xml
module full_adder_gates(x,y,z,sum,carry);
input x,y,z;
output sum,carry;
wire and1,and2,and3,sum1;

and U_and1 (and1,x,y),
    U_and2 (and2,x,z),
    U_and3 (and3,y,z);
or  U_or   (carry,and1,and2,and3);
xor U_sum (sum,x,y,z);

endmodule
module full_adder_gates(x,y,z,sum,carry);

input x,y,z;
output sum,carry;
wire and1,and2,and3,sum1;

and U_and1 (and1,x,y),
    U_and2 (and2,x,z),
    U_and3 (and3,y,z);
or  U_or   (carry,and1,and2,and3);
xor U_sum (sum,x,y,z);

endmodule