data/full_repos/permissive/434840709/作业/加法器2/cg.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82/cg.v:20: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                                                                                 : ... Top module \'add1\'\n        module add1 ( \n               ^~~~\n%Error: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82/cg.v:15: Cannot find file containing module: \'add16\'\nadd16 A16_2(a[15:0],b[15:0],0,sum[15:0],tempout);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82,data/full_repos/permissive/434840709/add16\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82,data/full_repos/permissive/434840709/add16.v\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82,data/full_repos/permissive/434840709/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa82/cg.v:16: Cannot find file containing module: \'add16\'\nadd16 A16_1(a[31:16],b[31:16],tempout,sum[31:16],sky1);\n^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top_module(

                input [31:0] a,

                input [31:0] b,

                output [31:0] sum

        );


wire tempout,sky1;


add16 A16_2(a[15:0],b[15:0],0,sum[15:0],tempout);
add16 A16_1(a[31:16],b[31:16],tempout,sum[31:16],sky1);
endmodule
module top_module(

                input [31:0] a,

                input [31:0] b,

                output [31:0] sum

        );



wire tempout,sky1;


add16 A16_2(a[15:0],b[15:0],0,sum[15:0],tempout);
add16 A16_1(a[31:16],b[31:16],tempout,sum[31:16],sky1);
endmodule