data/full_repos/permissive/439597284/rtl/mips_cpu/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/439597284/rtl/mips_cpu/alu.v:44: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance alu\n assign A_unsign = {1\'b0 + a};\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/439597284/rtl/mips_cpu/alu.v:44: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                          : ... In instance alu\n assign A_unsign = {1\'b0 + a};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/439597284/rtl/mips_cpu/alu.v:45: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance alu\n assign B_unsign = {1\'b0 + b};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/439597284/rtl/mips_cpu/alu.v:45: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                          : ... In instance alu\n assign B_unsign = {1\'b0 + b};\n                 ^\n%Error: Exiting due to 4 warning(s)\n'
module alu(
	input logic[3:0] ALUOperation,
	input logic signed[31:0] a,
	input logic signed[31:0] b,
	input logic unsign,
	input logic fixed_shift,
	input logic branch_equal,
	input logic[4:0] instr10_6,
	output logic[31:0] ALU_result,
	output logic[63:0] ALU_MULTorDIV_result,
	output logic zero
);



	logic[32:0] ALU_temp_result, B_unsign, A_unsign, quotient_unsign, remainder_unsign;
	logic[65:0] ALU_temp_MULTorDIV_result;
	logic[31:0] remainder, quotient;
	logic [63:0] A_extend, B_extend;

	
	typedef enum logic[3:0] {
        ADD 						= 4'b0000,
        LOGICAL_AND 				= 4'b0001,
        SUBTRACT 					= 4'b0010,
        SET_GREATER_OR_EQUAL_ZERO	= 4'b0011,
		SET_ON_GREATER_THAN_ZERO	= 4'b0100,
		SET_LESS_OR_EQUAL_ZERO 		= 4'b0101,
        SET_ON_LESS_THAN_ZERO 		= 4'b0110,
		MULTIPLY 					= 4'b0111,
		DIVIDE 						= 4'b1000,
        LOGICAL_OR 					= 4'b1001,
		LOGICAL_XOR 				= 4'b1010,
		SHIFT_LEFT 					= 4'b1011,
		SHIFT_RIGHT 				= 4'b1100,
		SHIFT_RIGHT_SIGNED 			= 4'b1101,
		SET_ON_LESS_THAN			= 4'b1110
	} ALUOperation_t;

	assign A_unsign = {1'b0 + a};
	assign B_unsign = {1'b0 + b};
    assign zero = (ALU_result == 0) ? (branch_equal==1)?0:1 :(branch_equal == 1) ? 1 : 0;
	


	

	always @(*) begin
		if(unsign == 1) begin 
			case(ALUOperation)




				SUBTRACT: 					ALU_temp_result = A_unsign - B_unsign;
				MULTIPLY:		
										begin
											ALU_temp_MULTorDIV_result = A_unsign * B_unsign;
											ALU_MULTorDIV_result = ALU_temp_MULTorDIV_result[63:0];
										end
			 	DIVIDE:					begin
											quotient_unsign = A_unsign / B_unsign; 
											remainder_unsign = A_unsign % B_unsign;
											ALU_MULTorDIV_result = {remainder_unsign[31:0],quotient_unsign[31:0]};
										end



				SET_ON_LESS_THAN:		begin
					ALU_temp_result = (A_unsign < B_unsign) ? 1 : 0;
				end




				default: ALU_temp_result = 0;
			endcase
			
			ALU_result = ALU_temp_result[31:0];
		end 
		
		else begin
			
			case(ALUOperation)
				LOGICAL_AND: 			ALU_result = a & b;
				LOGICAL_OR: 			ALU_result = a | b;
				LOGICAL_XOR: 			ALU_result = a ^ b;
				ADD: 					ALU_result = a + b;
				SUBTRACT: 				ALU_result = a - b;
				MULTIPLY:				begin



											ALU_MULTorDIV_result = a * b;
										end
				DIVIDE:					begin 										
											remainder = a % b;
											quotient = a / b;
											ALU_MULTorDIV_result = {remainder,quotient};
										end				
				SET_GREATER_OR_EQUAL_ZERO:	ALU_result = (a >= 0) ? 0 : 1;
				SET_ON_GREATER_THAN_ZERO:	ALU_result = (a > 0) ? 0 : 1;
				SET_LESS_OR_EQUAL_ZERO:		ALU_result = (a <= 0) ? 0 : 1;
				SET_ON_LESS_THAN_ZERO:		ALU_result = (a < 0) ? 0 : 1;

				SET_ON_LESS_THAN:			ALU_result = (a < b) ? 1 : 0;


				SHIFT_RIGHT:				ALU_result = (fixed_shift == 1) ? b >> instr10_6 : b >> a;
				SHIFT_LEFT:					ALU_result = (fixed_shift == 1) ? b << instr10_6 : b << a;
				SHIFT_RIGHT_SIGNED:			ALU_result = (fixed_shift == 1) ? b >>> instr10_6 : b >>> a;

				default: ALU_result = 0;
			endcase
		end





	end







endmodule
module alu(
	input logic[3:0] ALUOperation,
	input logic signed[31:0] a,
	input logic signed[31:0] b,
	input logic unsign,
	input logic fixed_shift,
	input logic branch_equal,
	input logic[4:0] instr10_6,
	output logic[31:0] ALU_result,
	output logic[63:0] ALU_MULTorDIV_result,
	output logic zero
);




	logic[32:0] ALU_temp_result, B_unsign, A_unsign, quotient_unsign, remainder_unsign;
	logic[65:0] ALU_temp_MULTorDIV_result;
	logic[31:0] remainder, quotient;
	logic [63:0] A_extend, B_extend;

	
	typedef enum logic[3:0] {
        ADD 						= 4'b0000,
        LOGICAL_AND 				= 4'b0001,
        SUBTRACT 					= 4'b0010,
        SET_GREATER_OR_EQUAL_ZERO	= 4'b0011,
		SET_ON_GREATER_THAN_ZERO	= 4'b0100,
		SET_LESS_OR_EQUAL_ZERO 		= 4'b0101,
        SET_ON_LESS_THAN_ZERO 		= 4'b0110,
		MULTIPLY 					= 4'b0111,
		DIVIDE 						= 4'b1000,
        LOGICAL_OR 					= 4'b1001,
		LOGICAL_XOR 				= 4'b1010,
		SHIFT_LEFT 					= 4'b1011,
		SHIFT_RIGHT 				= 4'b1100,
		SHIFT_RIGHT_SIGNED 			= 4'b1101,
		SET_ON_LESS_THAN			= 4'b1110
	} ALUOperation_t;

	assign A_unsign = {1'b0 + a};
	assign B_unsign = {1'b0 + b};
    assign zero = (ALU_result == 0) ? (branch_equal==1)?0:1 :(branch_equal == 1) ? 1 : 0;
	


	

	always @(*) begin
		if(unsign == 1) begin 
			case(ALUOperation)




				SUBTRACT: 					ALU_temp_result = A_unsign - B_unsign;
				MULTIPLY:		
										begin
											ALU_temp_MULTorDIV_result = A_unsign * B_unsign;
											ALU_MULTorDIV_result = ALU_temp_MULTorDIV_result[63:0];
										end
			 	DIVIDE:					begin
											quotient_unsign = A_unsign / B_unsign; 
											remainder_unsign = A_unsign % B_unsign;
											ALU_MULTorDIV_result = {remainder_unsign[31:0],quotient_unsign[31:0]};
										end



				SET_ON_LESS_THAN:		begin
					ALU_temp_result = (A_unsign < B_unsign) ? 1 : 0;
				end




				default: ALU_temp_result = 0;
			endcase
			
			ALU_result = ALU_temp_result[31:0];
		end 
		
		else begin
			
			case(ALUOperation)
				LOGICAL_AND: 			ALU_result = a & b;
				LOGICAL_OR: 			ALU_result = a | b;
				LOGICAL_XOR: 			ALU_result = a ^ b;
				ADD: 					ALU_result = a + b;
				SUBTRACT: 				ALU_result = a - b;
				MULTIPLY:				begin



											ALU_MULTorDIV_result = a * b;
										end
				DIVIDE:					begin 										
											remainder = a % b;
											quotient = a / b;
											ALU_MULTorDIV_result = {remainder,quotient};
										end				
				SET_GREATER_OR_EQUAL_ZERO:	ALU_result = (a >= 0) ? 0 : 1;
				SET_ON_GREATER_THAN_ZERO:	ALU_result = (a > 0) ? 0 : 1;
				SET_LESS_OR_EQUAL_ZERO:		ALU_result = (a <= 0) ? 0 : 1;
				SET_ON_LESS_THAN_ZERO:		ALU_result = (a < 0) ? 0 : 1;

				SET_ON_LESS_THAN:			ALU_result = (a < b) ? 1 : 0;


				SHIFT_RIGHT:				ALU_result = (fixed_shift == 1) ? b >> instr10_6 : b >> a;
				SHIFT_LEFT:					ALU_result = (fixed_shift == 1) ? b << instr10_6 : b << a;
				SHIFT_RIGHT_SIGNED:			ALU_result = (fixed_shift == 1) ? b >>> instr10_6 : b >>> a;

				default: ALU_result = 0;
			endcase
		end





	end







endmodule