data/full_repos/permissive/511241767/barrel_shifter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/511241767/barrel_shifter.v:352: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                         : ... In instance barrel_shifter.cl\n    assign a2 = {a[4],a[3],a[2],a[0],a[7],a[6],a[5]};\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module barrel_shifter(a,s,opcode,y,overflow);
    input [7:0] a;
    input [2:0] s,opcode;
    output reg [7:0] y;
    output reg overflow;
    wire [7:0] t1,t2,t3,t4,t5,t6;
    wire flag;


    ar_left al(a,s,t1,flag);
    log_left ll(a,s,t2);
    cr_left cl(a,s,t3);
    ar_right ar(a,s,t4);
    log_right lr(a,s,t5);
    cr_right cr(a,s,t6);

    parameter [2:0]
    ARLEFT = 3'b000,
    LOGLEFT = 3'b001,
    CRLEFT = 3'b010,
    ARRIGHT = 3'b100,
    LOGRIGHT = 3'b101,
    CRRIGHT = 3'b110;

    always@(*)
    begin
        case(opcode)
            ARLEFT: begin
                y = t1;
                overflow = flag;
            end

            LOGLEFT: begin
                y = t2;
                overflow = 1'b0;
            end

            CRLEFT: begin
                y = t3;
                overflow = 1'b0;
            end

            ARRIGHT: begin
                y = t4;
                overflow = 1'b0;
            end

            LOGRIGHT: begin
                y = t5;
                overflow = 1'b0;
            end

            CRRIGHT: begin
                y = t6;
                overflow = 1'b0;
            end

            default: begin

                y = 8'd0;
                overflow = 1'b0;

            end
        endcase
    end

endmodule
module barrel_shifter(a,s,opcode,y,overflow);

    input [7:0] a;
    input [2:0] s,opcode;
    output reg [7:0] y;
    output reg overflow;
    wire [7:0] t1,t2,t3,t4,t5,t6;
    wire flag;


    ar_left al(a,s,t1,flag);
    log_left ll(a,s,t2);
    cr_left cl(a,s,t3);
    ar_right ar(a,s,t4);
    log_right lr(a,s,t5);
    cr_right cr(a,s,t6);

    parameter [2:0]
    ARLEFT = 3'b000,
    LOGLEFT = 3'b001,
    CRLEFT = 3'b010,
    ARRIGHT = 3'b100,
    LOGRIGHT = 3'b101,
    CRRIGHT = 3'b110;

    always@(*)
    begin
        case(opcode)
            ARLEFT: begin
                y = t1;
                overflow = flag;
            end

            LOGLEFT: begin
                y = t2;
                overflow = 1'b0;
            end

            CRLEFT: begin
                y = t3;
                overflow = 1'b0;
            end

            ARRIGHT: begin
                y = t4;
                overflow = 1'b0;
            end

            LOGRIGHT: begin
                y = t5;
                overflow = 1'b0;
            end

            CRRIGHT: begin
                y = t6;
                overflow = 1'b0;
            end

            default: begin

                y = 8'd0;
                overflow = 1'b0;

            end
        endcase
    end

endmodule