data/full_repos/permissive/424292861/guia9/Exemplo_0901.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #12 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b0; \n  ^\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:40: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n always @(posedge clock & on) begin\n                        ^\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:54: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Exemplo_0801.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:55: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0901.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #120 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigger(signal,on,clock);
	input on,clock;
	output signal;
	reg signal;
	
	always @(posedge clock & on) begin
		#60	signal = 1'b1;
		#60	signal = 1'b0;
	end
endmodule
module trigger(signal,on,clock);

	input on,clock;
	output signal;
	reg signal;
	
	always @(posedge clock & on) begin
		#60	signal = 1'b1;
		#60	signal = 1'b0;
	end
endmodule