data/full_repos/permissive/46981098/alu_control/TB_alu_control.v
1: b'%Error: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:17: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b00;  funct = 6\'b100000; #20\n                                       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:19: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b00;  funct = 6\'b110000; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:21: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b01;  funct = 6\'b101010; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:23: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b100000; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:25: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b100010; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:27: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b100100; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:29: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b100101; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:31: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b101010; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:33: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b10;  funct = 6\'b100010; #20\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/alu_control/TB_alu_control.v:35: Unsupported: Ignoring delay on this delayed statement.\n    ALUOp = 2\'b11;  funct = 6\'b100000; #20\n                                       ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_control_t();


  reg [1:0] ALUOp;
  reg [5:0] funct;

  wire [3:0] ALUCon;


  alu_control test(ALUOp, funct, ALUCon);

  initial begin

    $dumpfile("dump.vcd");
      $dumpvars(1);

    ALUOp = 2'b00;  funct = 6'b100000; #20

    ALUOp = 2'b00;  funct = 6'b110000; #20

    ALUOp = 2'b01;  funct = 6'b101010; #20

    ALUOp = 2'b10;  funct = 6'b100000; #20

    ALUOp = 2'b10;  funct = 6'b100010; #20

    ALUOp = 2'b10;  funct = 6'b100100; #20

    ALUOp = 2'b10;  funct = 6'b100101; #20

    ALUOp = 2'b10;  funct = 6'b101010; #20

    ALUOp = 2'b10;  funct = 6'b100010; #20

    ALUOp = 2'b11;  funct = 6'b100000; #20



    $finish;
  end

endmodule
module alu_control_t();



  reg [1:0] ALUOp;
  reg [5:0] funct;

  wire [3:0] ALUCon;


  alu_control test(ALUOp, funct, ALUCon);

  initial begin

    $dumpfile("dump.vcd");
      $dumpvars(1);

    ALUOp = 2'b00;  funct = 6'b100000; #20

    ALUOp = 2'b00;  funct = 6'b110000; #20

    ALUOp = 2'b01;  funct = 6'b101010; #20

    ALUOp = 2'b10;  funct = 6'b100000; #20

    ALUOp = 2'b10;  funct = 6'b100010; #20

    ALUOp = 2'b10;  funct = 6'b100100; #20

    ALUOp = 2'b10;  funct = 6'b100101; #20

    ALUOp = 2'b10;  funct = 6'b101010; #20

    ALUOp = 2'b10;  funct = 6'b100010; #20

    ALUOp = 2'b11;  funct = 6'b100000; #20



    $finish;
  end

endmodule