data/full_repos/permissive/477054115/Mips16_singlecycle/ALU.v
1: b"%Error: data/full_repos/permissive/477054115/Mips16_singlecycle/ALU.v:11: Cannot find file containing module: 'sll_barrel'\nsll_barrel sll0(.a(a), .b(b[2:0]), .c(sll_temp));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/477054115/Mips16_singlecycle,data/full_repos/permissive/477054115/sll_barrel\n             data/full_repos/permissive/477054115/Mips16_singlecycle,data/full_repos/permissive/477054115/sll_barrel.v\n             data/full_repos/permissive/477054115/Mips16_singlecycle,data/full_repos/permissive/477054115/sll_barrel.sv\n             sll_barrel\n             sll_barrel.v\n             sll_barrel.sv\n             obj_dir/sll_barrel\n             obj_dir/sll_barrel.v\n             obj_dir/sll_barrel.sv\n%Error: data/full_repos/permissive/477054115/Mips16_singlecycle/ALU.v:12: Cannot find file containing module: 'srl_barrel'\nsrl_barrel srl0(.a(a), .b(b[2:0]), .c(srl_temp));\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module alu(       
      input          [15:0]     a,
      input          [15:0]     b,
      input          [2:0]     alu_control,
      output     reg     [15:0]     result,
      output zero  
   );
wire [15:0]     sll_temp, srl_temp;
sll_barrel sll0(.a(a), .b(b[2:0]), .c(sll_temp));
srl_barrel srl0(.a(a), .b(b[2:0]), .c(srl_temp));

 always @(*)
 begin   
      case(alu_control)  
      3'b000: result = a + b;
      3'b001: result = a - b;
      3'b010: result = a & b;
      3'b011: result = a | b;
      3'b100: begin if (a<b) result = 16'd1;  
                     else result = 16'd0;  
                     end
      3'b101: result = a[7:0] * b[7:0];
      3'b110: result = sll_temp;
      3'b111: result = srl_temp;
      default:result = a + b;
      endcase  
 end  
 assign zero = (result==16'd0) ? 1'b1: 1'b0;  
 endmodule
module alu(       
      input          [15:0]     a,
      input          [15:0]     b,
      input          [2:0]     alu_control,
      output     reg     [15:0]     result,
      output zero  
   );

wire [15:0]     sll_temp, srl_temp;
sll_barrel sll0(.a(a), .b(b[2:0]), .c(sll_temp));
srl_barrel srl0(.a(a), .b(b[2:0]), .c(srl_temp));

 always @(*)
 begin   
      case(alu_control)  
      3'b000: result = a + b;
      3'b001: result = a - b;
      3'b010: result = a & b;
      3'b011: result = a | b;
      3'b100: begin if (a<b) result = 16'd1;  
                     else result = 16'd0;  
                     end
      3'b101: result = a[7:0] * b[7:0];
      3'b110: result = sll_temp;
      3'b111: result = srl_temp;
      default:result = a + b;
      endcase  
 end  
 assign zero = (result==16'd0) ? 1'b1: 1'b0;  
 endmodule