data/full_repos/permissive/459277146/or_er.v
data/verilator_xmls/7027b191-b8d1-45a2-aa9c-b213e1eac7c5.xml
module or_er #(parameter DWIDTH = 8) (din1,din2,dout_or_er);
input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_or_er;

assign dout_or_er = din1|din2;

endmodule
module or_er #(parameter DWIDTH = 8) (din1,din2,dout_or_er);

input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_or_er;

assign dout_or_er = din1|din2;

endmodule