data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:11: Define or directive not defined: \'`DTCM_RAM_AW\'\n    input [`DTCM_RAM_AW-1:0] addr,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:12: Define or directive not defined: \'`DTCM_RAM_DW\'\n    input [`DTCM_RAM_DW-1:0] din,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:13: Define or directive not defined: \'`DTCM_RAM_MW\'\n    input [`DTCM_RAM_MW-1:0] wem,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:14: Define or directive not defined: \'`DTCM_RAM_DW\'\n    output [`DTCM_RAM_DW-1:0] dout\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:17: Define or directive not defined: \'`DTCM_RAM_DP\'\n    .DP(`DTCM_RAM_DP),\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:18: Define or directive not defined: \'`DTCM_RAM_DW\'\n    .DW(`DTCM_RAM_DW),\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:19: Define or directive not defined: \'`DTCM_RAM_MW\'\n    .MW(`DTCM_RAM_MW),\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ram.v:20: Define or directive not defined: \'`DTCM_RAM_AW\'\n    .AW(`DTCM_RAM_AW),\n        ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module dtcm_ram (
    input clk,
    input we,
    input [`DTCM_RAM_AW-1:0] addr,
    input [`DTCM_RAM_DW-1:0] din,
    input [`DTCM_RAM_MW-1:0] wem,
    output [`DTCM_RAM_DW-1:0] dout
);
    sim_ram#(
    .DP(`DTCM_RAM_DP),
    .DW(`DTCM_RAM_DW),
    .MW(`DTCM_RAM_MW),
    .AW(`DTCM_RAM_AW),
    .FORCE_X2ZERO(0),
    .ITCM(0),
    .DTCM(1)
    ) u_dtcm_gnrl_ram(
    .clk(clk),
    .din(din),
    .addr(addr),
    .we(we),
    .wem(wem),
    .dout(dout)
);
endmodule
module dtcm_ram (
    input clk,
    input we,
    input [`DTCM_RAM_AW-1:0] addr,
    input [`DTCM_RAM_DW-1:0] din,
    input [`DTCM_RAM_MW-1:0] wem,
    output [`DTCM_RAM_DW-1:0] dout
);

    sim_ram#(
    .DP(`DTCM_RAM_DP),
    .DW(`DTCM_RAM_DW),
    .MW(`DTCM_RAM_MW),
    .AW(`DTCM_RAM_AW),
    .FORCE_X2ZERO(0),
    .ITCM(0),
    .DTCM(1)
    ) u_dtcm_gnrl_ram(
    .clk(clk),
    .din(din),
    .addr(addr),
    .we(we),
    .wem(wem),
    .dout(dout)
);
endmodule