data/full_repos/permissive/487568919/basic_verilog/gray2bin.sv
data/verilator_xmls/42b5833a-2bc1-4b80-9b64-1e4e8a913f94.xml
module gray2bin #( parameter
   WIDTH = 32
)(
   input [WIDTH-1:0] gray_in,
   output [WIDTH-1:0] bin_out
);

genvar i;
generate
   for( i=0; i<WIDTH; i++ ) begin
      assign bin_out[i] = ^gray_in[WIDTH-1:i];
   end
endgenerate

endmodule
module gray2bin #( parameter
   WIDTH = 32
)(
   input [WIDTH-1:0] gray_in,
   output [WIDTH-1:0] bin_out
);


genvar i;
generate
   for( i=0; i<WIDTH; i++ ) begin
      assign bin_out[i] = ^gray_in[WIDTH-1:i];
   end
endgenerate

endmodule