data/full_repos/permissive/47037127/RevisionB/intpipe.v
1: b"%Error: data/full_repos/permissive/47037127/RevisionB/intpipe.v:77: Cannot find file containing module: 'ALU'\nALU crunchinator(opShifter[1], curFlgs, operandA, operandB, flgs, aluOut, aluWriteback);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/47037127/RevisionB,data/full_repos/permissive/47037127/ALU\n             data/full_repos/permissive/47037127/RevisionB,data/full_repos/permissive/47037127/ALU.v\n             data/full_repos/permissive/47037127/RevisionB,data/full_repos/permissive/47037127/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s)\n"
module intpipe(op, clk, rst, opWt, regWt, aSel, bSel, cSel, aDat, bDat, flgIn, FLGWRI, COUT, CWRI, AS, BS, CS, FLGOUT);

input [3:0] op;
input clk;
input rst;

input opWt;
input regWt;
input [2:0] aSel;
input [2:0] bSel;
input [2:0] cSel;
input [15:0] aDat;
input [15:0] bDat;
input [7:0] flgIn;
output [15:0] COUT;
output [2:0] AS;
output [2:0] BS;
output [2:0] CS;
output CWRI; 
output FLGWRI;
output [7:0] FLGOUT;

assign AS=aSel;
assign BS=bSel;


reg [3:0] opShifter[2:0];
reg [2:0] destShifter[2:0];
reg [15:0] operandA;
reg [15:0] operandB;
reg [15:0] operandC;
reg cwr;

wire [2:0] dest0;
wire [2:0] dest1;
wire [2:0] dest2;
assign dest0=destShifter[0];
assign dest1=destShifter[1];
assign dest2=destShifter[2];

assign CS=destShifter[2];
assign CWRI=cwr;

wire [15:0] aluOut;
wire [7:0] flgs;
wire aluWriteback;
reg [7:0] curFlgs;
assign COUT=aluOut;

wire [3:0] curOp;
assign curOp=opShifter[1];








wire aluASelect;
wire aluBSelect;

assign aluASelect=(aSel==destShifter[1]);
assign aluBSelect=(bSel==destShifter[1]);








ALU crunchinator(opShifter[1], curFlgs, operandA, operandB, flgs, aluOut, aluWriteback);

always@(posedge clk) begin

	if(~opWt&&~regWt) begin
		opShifter[0]<=op;
		opShifter[1]<=opShifter[0];
		opShifter[2]<=opShifter[1];

		destShifter[0]<=cSel;
		destShifter[1]<=destShifter[0];
		destShifter[2]<=destShifter[1];
	end


	cwr<=aluWriteback;



	operandC<=aluOut;

	if(aluASelect) begin
		operandA<=aluOut;
	end






	else begin
		operandA<=aDat;
	end

	if(aluBSelect) begin
		operandB<=aluOut;
	end





	else begin
		operandB<=bDat;
	end


end

initial begin
	destShifter[0]=0;
	destShifter[1]=0;
	destShifter[2]=0;
end
endmodule
module intpipe(op, clk, rst, opWt, regWt, aSel, bSel, cSel, aDat, bDat, flgIn, FLGWRI, COUT, CWRI, AS, BS, CS, FLGOUT);


input [3:0] op;
input clk;
input rst;

input opWt;
input regWt;
input [2:0] aSel;
input [2:0] bSel;
input [2:0] cSel;
input [15:0] aDat;
input [15:0] bDat;
input [7:0] flgIn;
output [15:0] COUT;
output [2:0] AS;
output [2:0] BS;
output [2:0] CS;
output CWRI; 
output FLGWRI;
output [7:0] FLGOUT;

assign AS=aSel;
assign BS=bSel;


reg [3:0] opShifter[2:0];
reg [2:0] destShifter[2:0];
reg [15:0] operandA;
reg [15:0] operandB;
reg [15:0] operandC;
reg cwr;

wire [2:0] dest0;
wire [2:0] dest1;
wire [2:0] dest2;
assign dest0=destShifter[0];
assign dest1=destShifter[1];
assign dest2=destShifter[2];

assign CS=destShifter[2];
assign CWRI=cwr;

wire [15:0] aluOut;
wire [7:0] flgs;
wire aluWriteback;
reg [7:0] curFlgs;
assign COUT=aluOut;

wire [3:0] curOp;
assign curOp=opShifter[1];








wire aluASelect;
wire aluBSelect;

assign aluASelect=(aSel==destShifter[1]);
assign aluBSelect=(bSel==destShifter[1]);








ALU crunchinator(opShifter[1], curFlgs, operandA, operandB, flgs, aluOut, aluWriteback);

always@(posedge clk) begin

	if(~opWt&&~regWt) begin
		opShifter[0]<=op;
		opShifter[1]<=opShifter[0];
		opShifter[2]<=opShifter[1];

		destShifter[0]<=cSel;
		destShifter[1]<=destShifter[0];
		destShifter[2]<=destShifter[1];
	end


	cwr<=aluWriteback;



	operandC<=aluOut;

	if(aluASelect) begin
		operandA<=aluOut;
	end






	else begin
		operandA<=aDat;
	end

	if(aluBSelect) begin
		operandB<=aluOut;
	end





	else begin
		operandB<=bDat;
	end


end

initial begin
	destShifter[0]=0;
	destShifter[1]=0;
	destShifter[2]=0;
end
endmodule