data/full_repos/permissive/507307707/generated/D_EB.v
data/verilator_xmls/ab634c9a-00f3-4f0e-988f-3861db72edb0.xml
module D_EB(
  input        clock,
  input        reset,
  input  [7:0] io_d_p,
  input        io_v_p,
  input        io_a_n,
  output [7:0] io_d_n,
  output       io_v_n,
  output       io_a_p
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  main_clock;
  wire  main_reset;
  wire [7:0] main_io_in;
  wire  main_io_en;
  wire [7:0] main_io_out;
  wire  aux_clock;
  wire  aux_reset;
  wire [7:0] aux_io_in;
  wire  aux_io_en;
  wire [7:0] aux_io_out;
  wire  reg_1_clock;
  wire  reg_1_reset;
  wire  reg_1_io_in;
  wire  reg_1_io_en;
  wire  reg_1_io_out;
  wire  reg_2_clock;
  wire  reg_2_reset;
  wire  reg_2_io_in;
  wire  reg_2_io_en;
  wire  reg_2_io_out;
  reg  reg_;
  wire  mux2_out = reg_ ? reg_1_io_out : reg_2_io_out;
  RegEnable main (
    .clock(main_clock),
    .reset(main_reset),
    .io_in(main_io_in),
    .io_en(main_io_en),
    .io_out(main_io_out)
  );
  RegEnable aux (
    .clock(aux_clock),
    .reset(aux_reset),
    .io_in(aux_io_in),
    .io_en(aux_io_en),
    .io_out(aux_io_out)
  );
  RegEnable_2 reg_1 (
    .clock(reg_1_clock),
    .reset(reg_1_reset),
    .io_in(reg_1_io_in),
    .io_en(reg_1_io_en),
    .io_out(reg_1_io_out)
  );
  RegEnable_2 reg_2 (
    .clock(reg_2_clock),
    .reset(reg_2_reset),
    .io_in(reg_2_io_in),
    .io_en(reg_2_io_en),
    .io_out(reg_2_io_out)
  );
  assign io_d_n = reg_ ? main_io_out : aux_io_out;
  assign io_v_n = reg_ ? reg_1_io_out : reg_2_io_out;
  assign io_a_p = reg_ | ~io_v_p;
  assign main_clock = clock;
  assign main_reset = reset;
  assign main_io_in = io_d_p;
  assign main_io_en = io_a_p;
  assign aux_clock = clock;
  assign aux_reset = reset;
  assign aux_io_in = main_io_out;
  assign aux_io_en = reg_;
  assign reg_1_clock = clock;
  assign reg_1_reset = reset;
  assign reg_1_io_in = io_v_p;
  assign reg_1_io_en = io_a_p;
  assign reg_2_clock = clock;
  assign reg_2_reset = reset;
  assign reg_2_io_in = reg_1_io_out;
  assign reg_2_io_en = reg_;
  always @(posedge clock) begin
    if (reset) begin
      reg_ <= 1'h0;
    end else begin
      reg_ <= io_a_n | ~mux2_out;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module D_EB(
  input        clock,
  input        reset,
  input  [7:0] io_d_p,
  input        io_v_p,
  input        io_a_n,
  output [7:0] io_d_n,
  output       io_v_n,
  output       io_a_p
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  main_clock;
  wire  main_reset;
  wire [7:0] main_io_in;
  wire  main_io_en;
  wire [7:0] main_io_out;
  wire  aux_clock;
  wire  aux_reset;
  wire [7:0] aux_io_in;
  wire  aux_io_en;
  wire [7:0] aux_io_out;
  wire  reg_1_clock;
  wire  reg_1_reset;
  wire  reg_1_io_in;
  wire  reg_1_io_en;
  wire  reg_1_io_out;
  wire  reg_2_clock;
  wire  reg_2_reset;
  wire  reg_2_io_in;
  wire  reg_2_io_en;
  wire  reg_2_io_out;
  reg  reg_;
  wire  mux2_out = reg_ ? reg_1_io_out : reg_2_io_out;
  RegEnable main (
    .clock(main_clock),
    .reset(main_reset),
    .io_in(main_io_in),
    .io_en(main_io_en),
    .io_out(main_io_out)
  );
  RegEnable aux (
    .clock(aux_clock),
    .reset(aux_reset),
    .io_in(aux_io_in),
    .io_en(aux_io_en),
    .io_out(aux_io_out)
  );
  RegEnable_2 reg_1 (
    .clock(reg_1_clock),
    .reset(reg_1_reset),
    .io_in(reg_1_io_in),
    .io_en(reg_1_io_en),
    .io_out(reg_1_io_out)
  );
  RegEnable_2 reg_2 (
    .clock(reg_2_clock),
    .reset(reg_2_reset),
    .io_in(reg_2_io_in),
    .io_en(reg_2_io_en),
    .io_out(reg_2_io_out)
  );
  assign io_d_n = reg_ ? main_io_out : aux_io_out;
  assign io_v_n = reg_ ? reg_1_io_out : reg_2_io_out;
  assign io_a_p = reg_ | ~io_v_p;
  assign main_clock = clock;
  assign main_reset = reset;
  assign main_io_in = io_d_p;
  assign main_io_en = io_a_p;
  assign aux_clock = clock;
  assign aux_reset = reset;
  assign aux_io_in = main_io_out;
  assign aux_io_en = reg_;
  assign reg_1_clock = clock;
  assign reg_1_reset = reset;
  assign reg_1_io_in = io_v_p;
  assign reg_1_io_en = io_a_p;
  assign reg_2_clock = clock;
  assign reg_2_reset = reset;
  assign reg_2_io_in = reg_1_io_out;
  assign reg_2_io_en = reg_;
  always @(posedge clock) begin
    if (reset) begin
      reg_ <= 1'h0;
    end else begin
      reg_ <= io_a_n | ~mux2_out;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule