data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:320: Signal definition not found, creating implicitly: \'reuslt_o\'\n                                                                                                 : ... Suggested alternative: \'result_o\'\nassign reuslt_o = w_result_0 + w_result_1 + w_result_2 + w_result_3; \n       ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:208: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_cnt_read\' generates 31 bits.\n                                                                                              : ... In instance data_mover_bram\nassign addr_b0_o  = addr_cnt_read;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:227: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_cnt_read\' generates 31 bits.\n                                                                                              : ... In instance data_mover_bram\nassign addr_b1_o = addr_cnt_read;\n                 ^\n%Error: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:257: Cannot find file containing module: \'fully_connected_core\'\nfully_connected_core\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503973366/RTL/Fully_Connected,data/full_repos/permissive/503973366/fully_connected_core\n             data/full_repos/permissive/503973366/RTL/Fully_Connected,data/full_repos/permissive/503973366/fully_connected_core.v\n             data/full_repos/permissive/503973366/RTL/Fully_Connected,data/full_repos/permissive/503973366/fully_connected_core.sv\n             fully_connected_core\n             fully_connected_core.v\n             fully_connected_core.sv\n             obj_dir/fully_connected_core\n             obj_dir/fully_connected_core.v\n             obj_dir/fully_connected_core.sv\n%Error: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:271: Cannot find file containing module: \'fully_connected_core\'\nfully_connected_core\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:285: Cannot find file containing module: \'fully_connected_core\'\nfully_connected_core\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:299: Cannot find file containing module: \'fully_connected_core\'\nfully_connected_core\n^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Fully_Connected/data_mover_bram.v:320: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                              : ... In instance data_mover_bram\nassign reuslt_o = w_result_0 + w_result_1 + w_result_2 + w_result_3; \n                ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module data_mover_bram 
# (
    parameter CNT_BIT = 31,


    parameter DWIDTH = 32,
    parameter AWIDTH = 12,
    parameter MEM_SIZE = 4096,
    parameter IN_DATA_WIDTH = 8
)
(

    input clk,
    input reset_n,


    input start_run_i, 
    input [CNT_BIT - 1 : 0] run_count_i, 


    input [DWIDTH - 1 : 0] q_b0_i,


    input [DWIDTH - 1 : 0] q_b1_i,


    output idle_o,
    output read_o,
    output write_o,
    output done_o,


    output [AWIDTH - 1 : 0] addr_b0_o,
    output ce_b0_o,
    output we_b0_o,
    output [DWIDTH - 1 : 0] d_b0_o,
 

    output [AWIDTH - 1 : 0] addr_b1_o,
    output ce_b1_o,
    output we_b1_o,
    output [DWIDTH - 1 : 0] d_b1_o,






    output [DWIDTH - 1 : 0] result_o
);


localparam S_IDLE = 2'b00;
localparam S_RUN = 2'b01;
localparam S_DONE = 2'b10;


reg [1 : 0] c_state_read;
reg [1 : 0] n_state_read;
reg [1 : 0] c_state_write;
reg [1 : 0] n_state_write;


wire is_write_done;
wire is_read_done;


always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        c_state_read <= S_IDLE;
    end else begin
        c_state_read <= n_state_read;
    end
end

always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        c_state_write <= S_IDLE;
    end else begin
        c_state_write <= n_state_write;
    end
end


always @(*) begin
    n_state_read = c_state_read;
    
    case(c_state_read)
        S_IDLE : if(start_run_i)   begin n_state_read = S_RUN; end
        S_RUN  : if(is_read_done)  begin n_state_read = S_DONE; end
        S_DONE : n_state_read = S_IDLE; 
    endcase
end

always @(*) begin
    n_state_write = c_state_write;
 
    case(c_state_write)
        S_IDLE : if(start_run_i)   begin n_state_write = S_RUN; end
        S_RUN  : if(is_write_done) begin n_state_write = S_DONE; end
        S_DONE : n_state_write = S_IDLE; 
    endcase
end


assign idle_o   = (c_state_read == S_IDLE) && (c_state_write == S_IDLE);
assign read_o   = (c_state_read == S_RUN);
assign write_o  = (c_state_write == S_RUN);
assign done_o   = (c_state_write == S_DONE);



reg [CNT_BIT - 1 : 0] num_cnt;
always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        num_cnt <= 0;
    end else if (start_run_i) begin
        num_cnt <= run_count_i;
    end else if (done_o) begin
        num_cnt <= 0; 
    end
end


reg [CNT_BIT - 1 : 0] addr_cnt_read;
reg [CNT_BIT - 1 : 0] addr_cnt_write;
assign is_read_done = read_o && (addr_cnt_read == num_cnt - 1); 
assign is_write_done = write_o && (addr_cnt_write == num_cnt - 1);

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        addr_cnt_read <= 0;
    end else if (is_read_done) begin
        addr_cnt_read <= 0;
    end else if (read_o) begin
        addr_cnt_read <= addr_cnt_read + 1;
    end
end





wire result_valid;

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        addr_cnt_write <= 0;
    end else if (is_write_done) begin
        addr_cnt_write <= 0;

    end else if (write_o && result_valid) begin
        addr_cnt_write <= addr_cnt_write + 1;
    end
end


assign addr_b0_o  = addr_cnt_read;
assign ce_b0_o    = read_o;
assign we_b0_o    = 1'b0;
assign d_b0_o     = {DWIDTH{1'b0}};

reg  r_valid;
wire [DWIDTH - 1 : 0]   mem_data_0;


always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        r_valid <= 1'b0;
    end else begin
        r_valid <= read_o;
    end
end
assign mem_data_0 = q_b0_i;


assign addr_b1_o = addr_cnt_read;
assign ce_b1_o = read_o;
assign we_b1_o = 1'b0;
assign d_b1_o = {DWIDTH{1'b0}};

wire [DWIDTH - 1 : 0]   mem_data_1;

assign mem_data_1 = q_b1_i;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_0 = mem_data_0[(4*IN_DATA_WIDTH) - 1 : (3*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_0 = mem_data_1[(4*IN_DATA_WIDTH) - 1 : (3*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_0;
wire                                w_valid_0;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_1 = mem_data_0[(3*IN_DATA_WIDTH) - 1 : (2*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_1 = mem_data_1[(3*IN_DATA_WIDTH) - 1 : (2*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_1;
wire                                w_valid_1;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_2 = mem_data_0[(2*IN_DATA_WIDTH) - 1 : (1*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_2 = mem_data_1[(2*IN_DATA_WIDTH) - 1 : (1*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_2;
wire                                w_valid_2;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_3 = mem_data_0[(1*IN_DATA_WIDTH) - 1 : (0*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_3 = mem_data_1[(1*IN_DATA_WIDTH) - 1 : (0*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_3;
wire                                w_valid_3;


fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_1 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_0),
    .weight_i(w_b_0),
    .result_o(w_result_0),
    .valid_o(w_valid_0)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_2 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_1),
    .weight_i(w_b_1),
    .result_o(w_result_1),
    .valid_o(w_valid_1)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_3 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_2),
    .weight_i(w_b_2),
    .result_o(w_result_2),
    .valid_o(w_valid_2)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_4 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_3),
    .weight_i(w_b_3),
    .result_o(w_result_3),
    .valid_o(w_valid_3)
);


assign result_valid = w_valid_0 & w_valid_1 & w_valid_2 & w_valid_3;





assign reuslt_o = w_result_0 + w_result_1 + w_result_2 + w_result_3; 
endmodule
module data_mover_bram 
# (
    parameter CNT_BIT = 31,


    parameter DWIDTH = 32,
    parameter AWIDTH = 12,
    parameter MEM_SIZE = 4096,
    parameter IN_DATA_WIDTH = 8
)
(

    input clk,
    input reset_n,


    input start_run_i, 
    input [CNT_BIT - 1 : 0] run_count_i, 


    input [DWIDTH - 1 : 0] q_b0_i,


    input [DWIDTH - 1 : 0] q_b1_i,


    output idle_o,
    output read_o,
    output write_o,
    output done_o,


    output [AWIDTH - 1 : 0] addr_b0_o,
    output ce_b0_o,
    output we_b0_o,
    output [DWIDTH - 1 : 0] d_b0_o,
 

    output [AWIDTH - 1 : 0] addr_b1_o,
    output ce_b1_o,
    output we_b1_o,
    output [DWIDTH - 1 : 0] d_b1_o,






    output [DWIDTH - 1 : 0] result_o
);



localparam S_IDLE = 2'b00;
localparam S_RUN = 2'b01;
localparam S_DONE = 2'b10;


reg [1 : 0] c_state_read;
reg [1 : 0] n_state_read;
reg [1 : 0] c_state_write;
reg [1 : 0] n_state_write;


wire is_write_done;
wire is_read_done;


always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        c_state_read <= S_IDLE;
    end else begin
        c_state_read <= n_state_read;
    end
end

always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        c_state_write <= S_IDLE;
    end else begin
        c_state_write <= n_state_write;
    end
end


always @(*) begin
    n_state_read = c_state_read;
    
    case(c_state_read)
        S_IDLE : if(start_run_i)   begin n_state_read = S_RUN; end
        S_RUN  : if(is_read_done)  begin n_state_read = S_DONE; end
        S_DONE : n_state_read = S_IDLE; 
    endcase
end

always @(*) begin
    n_state_write = c_state_write;
 
    case(c_state_write)
        S_IDLE : if(start_run_i)   begin n_state_write = S_RUN; end
        S_RUN  : if(is_write_done) begin n_state_write = S_DONE; end
        S_DONE : n_state_write = S_IDLE; 
    endcase
end


assign idle_o   = (c_state_read == S_IDLE) && (c_state_write == S_IDLE);
assign read_o   = (c_state_read == S_RUN);
assign write_o  = (c_state_write == S_RUN);
assign done_o   = (c_state_write == S_DONE);



reg [CNT_BIT - 1 : 0] num_cnt;
always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        num_cnt <= 0;
    end else if (start_run_i) begin
        num_cnt <= run_count_i;
    end else if (done_o) begin
        num_cnt <= 0; 
    end
end


reg [CNT_BIT - 1 : 0] addr_cnt_read;
reg [CNT_BIT - 1 : 0] addr_cnt_write;
assign is_read_done = read_o && (addr_cnt_read == num_cnt - 1); 
assign is_write_done = write_o && (addr_cnt_write == num_cnt - 1);

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        addr_cnt_read <= 0;
    end else if (is_read_done) begin
        addr_cnt_read <= 0;
    end else if (read_o) begin
        addr_cnt_read <= addr_cnt_read + 1;
    end
end





wire result_valid;

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        addr_cnt_write <= 0;
    end else if (is_write_done) begin
        addr_cnt_write <= 0;

    end else if (write_o && result_valid) begin
        addr_cnt_write <= addr_cnt_write + 1;
    end
end


assign addr_b0_o  = addr_cnt_read;
assign ce_b0_o    = read_o;
assign we_b0_o    = 1'b0;
assign d_b0_o     = {DWIDTH{1'b0}};

reg  r_valid;
wire [DWIDTH - 1 : 0]   mem_data_0;


always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        r_valid <= 1'b0;
    end else begin
        r_valid <= read_o;
    end
end
assign mem_data_0 = q_b0_i;


assign addr_b1_o = addr_cnt_read;
assign ce_b1_o = read_o;
assign we_b1_o = 1'b0;
assign d_b1_o = {DWIDTH{1'b0}};

wire [DWIDTH - 1 : 0]   mem_data_1;

assign mem_data_1 = q_b1_i;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_0 = mem_data_0[(4*IN_DATA_WIDTH) - 1 : (3*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_0 = mem_data_1[(4*IN_DATA_WIDTH) - 1 : (3*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_0;
wire                                w_valid_0;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_1 = mem_data_0[(3*IN_DATA_WIDTH) - 1 : (2*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_1 = mem_data_1[(3*IN_DATA_WIDTH) - 1 : (2*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_1;
wire                                w_valid_1;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_2 = mem_data_0[(2*IN_DATA_WIDTH) - 1 : (1*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_2 = mem_data_1[(2*IN_DATA_WIDTH) - 1 : (1*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_2;
wire                                w_valid_2;

wire [IN_DATA_WIDTH - 1 : 0]        w_a_3 = mem_data_0[(1*IN_DATA_WIDTH) - 1 : (0*IN_DATA_WIDTH)];
wire [IN_DATA_WIDTH - 1 : 0]        w_b_3 = mem_data_1[(1*IN_DATA_WIDTH) - 1 : (0*IN_DATA_WIDTH)];
wire [(4*IN_DATA_WIDTH) - 1 : 0]    w_result_3;
wire                                w_valid_3;


fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_1 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_0),
    .weight_i(w_b_0),
    .result_o(w_result_0),
    .valid_o(w_valid_0)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_2 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_1),
    .weight_i(w_b_1),
    .result_o(w_result_1),
    .valid_o(w_valid_1)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_3 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_2),
    .weight_i(w_b_2),
    .result_o(w_result_2),
    .valid_o(w_valid_2)
);

fully_connected_core
# (
    .IN_DATA_WIDTH(IN_DATA_WIDTH)
) fully_connected_core_8bit_inst_4 (
    .clk(clk),
    .reset_n(reset_n),
    .run_i(start_run_i),
    .valid_i(r_valid),
    .node_i(w_a_3),
    .weight_i(w_b_3),
    .result_o(w_result_3),
    .valid_o(w_valid_3)
);


assign result_valid = w_valid_0 & w_valid_1 & w_valid_2 & w_valid_3;





assign reuslt_o = w_result_0 + w_result_1 + w_result_2 + w_result_3; 
endmodule