data/full_repos/permissive/488093047/Verilog Codes/NOR.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/NOR.v\n%Error: Exiting due to 3 error(s)\n'
module NOR #(parameter N=32)(A,B,NOR);
input [N-1:0]A,B;
output [N-1:0]NOR;
genvar i;
generate
for(i=0;i<N;i=i+1)begin
nor DUT1(NOR[i],A[i],B[i]);
end
endgenerate
endmodule
module NOR #(parameter N=32)(A,B,NOR);

input [N-1:0]A,B;
output [N-1:0]NOR;
genvar i;
generate
for(i=0;i<N;i=i+1)begin
nor DUT1(NOR[i],A[i],B[i]);
end
endgenerate
endmodule