data/full_repos/permissive/515624136/rtl/REG_POS.v
data/verilator_xmls/a62dbfe6-1aff-4cc0-ac13-0d244c8b6b04.xml
module REG_POS #(parameter REG_DATA_WIDTH=32, parameter [REG_DATA_WIDTH-1:0] RESET_VALUE= 32'h00000000)(


REG_Clk,
REG_Reset,
REG_Set,
REG_Data_InBUS,

REG_Data_OutBUS
);




input REG_Clk;
input REG_Reset;
input REG_Set;
input signed [REG_DATA_WIDTH-1:0] REG_Data_InBUS;
output signed [REG_DATA_WIDTH-1:0] REG_Data_OutBUS;





reg signed [REG_DATA_WIDTH-1:0] Internal_Signal_Reg;
reg signed[REG_DATA_WIDTH-1:0] Internal_Data_Reg;




always@(*)
begin
	if(REG_Set)
		Internal_Signal_Reg=REG_Data_InBUS;
	else
		Internal_Signal_Reg=Internal_Data_Reg;
end





always@(posedge REG_Clk or negedge REG_Reset)
begin
	if(!REG_Reset)
		Internal_Data_Reg<=RESET_VALUE;
	else
		Internal_Data_Reg<=Internal_Signal_Reg;
end




assign REG_Data_OutBUS=Internal_Data_Reg;

endmodule
module REG_POS #(parameter REG_DATA_WIDTH=32, parameter [REG_DATA_WIDTH-1:0] RESET_VALUE= 32'h00000000)(


REG_Clk,
REG_Reset,
REG_Set,
REG_Data_InBUS,

REG_Data_OutBUS
);





input REG_Clk;
input REG_Reset;
input REG_Set;
input signed [REG_DATA_WIDTH-1:0] REG_Data_InBUS;
output signed [REG_DATA_WIDTH-1:0] REG_Data_OutBUS;





reg signed [REG_DATA_WIDTH-1:0] Internal_Signal_Reg;
reg signed[REG_DATA_WIDTH-1:0] Internal_Data_Reg;




always@(*)
begin
	if(REG_Set)
		Internal_Signal_Reg=REG_Data_InBUS;
	else
		Internal_Signal_Reg=Internal_Data_Reg;
end





always@(posedge REG_Clk or negedge REG_Reset)
begin
	if(!REG_Reset)
		Internal_Data_Reg<=RESET_VALUE;
	else
		Internal_Data_Reg<=Internal_Signal_Reg;
end




assign REG_Data_OutBUS=Internal_Data_Reg;

endmodule