data/full_repos/permissive/459277146/top.v
1: b'%Error: data/full_repos/permissive/459277146/top.v:20: Cannot find file containing module: \'adder\'\nadder add1(din1,din2,dout_adder);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder.v\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/459277146/top.v:21: Cannot find file containing module: \'subtractor\'\nsubtractor sub1(clk,din1,din2,dout_subtractor);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:22: Cannot find file containing module: \'multiplier\'\nmultiplier mult1(din1,din2,dout_multiplier);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:23: Cannot find file containing module: \'divider\'\ndivider div1(.clk(clk),.x(din1),.y(din2),.dout(dout_divider));\n^~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:24: Cannot find file containing module: \'comparator\'\ncomparator comp1(din1,din2,dout_comparator);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:33: Cannot find file containing module: \'and_er\'\nand_er and1(din1,din2,dout_and);\n^~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:34: Cannot find file containing module: \'or_er\'\nor_er or1(din1,din2,dout_or);\n^~~~~\n%Error: data/full_repos/permissive/459277146/top.v:35: Cannot find file containing module: \'xor_er\'\nxor_er xor1(din1,din2,dout_xor);\n^~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:36: Cannot find file containing module: \'not_er\'\nnot_er not1(din1,dout_not);\n^~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:37: Cannot find file containing module: \'shift_er\'\nshift_er shift1(din1,dir,dout_shift);\n^~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:38: Cannot find file containing module: \'ashift_er\'\nashift_er ashift1(din1,dir,dout_ashift);\n^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:41: Cannot find file containing module: \'BCD_Convert\'\nBCD_Convert bin_to_bcd(dout[DWIDTH-1:0], ssd_temp);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:42: Cannot find file containing module: \'ssd_out\'\nssd_out d2(ssd_temp[11:8] , HEX[2]);\n^~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:43: Cannot find file containing module: \'ssd_out\'\nssd_out d1(ssd_temp[7:4]  , HEX[1]);\n^~~~~~~\n%Error: data/full_repos/permissive/459277146/top.v:44: Cannot find file containing module: \'ssd_out\'\nssd_out d0(ssd_temp[3:0]  , HEX[0]);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:68: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_and\' generates 8 bits.\n                                                             : ... In instance top\n       : (op==0 ? dout_and\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:69: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_or\' generates 8 bits.\n                                                             : ... In instance top\n          : op==1 ? dout_or\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:70: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_xor\' generates 8 bits.\n                                                             : ... In instance top\n        : op==2 ? dout_xor \n                ^\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:71: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_not\' generates 8 bits.\n                                                             : ... In instance top\n        : op==3 ? dout_not\n                ^\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:72: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_shift\' generates 8 bits.\n                                                             : ... In instance top\n        : op==4 ? dout_shift\n                ^\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:73: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'dout_ashift\' generates 8 bits.\n                                                             : ... In instance top\n        : op==5 ? dout_ashift  \n                ^\n%Warning-WIDTH: data/full_repos/permissive/459277146/top.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'result\' generates 16 bits.\n                                                             : ... In instance top\n dout <= result;\n      ^~\n%Error: Exiting due to 15 error(s), 7 warning(s)\n'
module top #(parameter DWIDTH = 8)(
inout clk,
input mode,
input [2:0] op,
input [DWIDTH-1:0] din1,
input [DWIDTH-1:0] din2,
output reg [DWIDTH-1:0] dout
);
reg done;
reg [(DWIDTH<<1):0]counter;

reg [(DWIDTH<<1)-1:0] result;

wire [(DWIDTH<<1)-1:0] dout_adder;
wire [(DWIDTH<<1)-1:0] dout_subtractor;
wire [(DWIDTH<<1)-1:0] dout_multiplier;
wire [(DWIDTH<<1)-1:0] dout_divider;
wire [(DWIDTH<<1)-1:0] dout_comparator;

adder add1(din1,din2,dout_adder);
subtractor sub1(clk,din1,din2,dout_subtractor);
multiplier mult1(din1,din2,dout_multiplier);
divider div1(.clk(clk),.x(din1),.y(din2),.dout(dout_divider));
comparator comp1(din1,din2,dout_comparator);

wire [DWIDTH-1:0] dout_and;
wire [DWIDTH-1:0] dout_or;
wire [DWIDTH-1:0] dout_xor;
wire [DWIDTH-1:0] dout_not;
wire [DWIDTH-1:0] dout_shift;
wire [DWIDTH-1:0] dout_ashift;

and_er and1(din1,din2,dout_and);
or_er or1(din1,din2,dout_or);
xor_er xor1(din1,din2,dout_xor);
not_er not1(din1,dout_not);
shift_er shift1(din1,dir,dout_shift);
ashift_er ashift1(din1,dir,dout_ashift);

wire [11:0] ssd_temp;
BCD_Convert bin_to_bcd(dout[DWIDTH-1:0], ssd_temp);
ssd_out d2(ssd_temp[11:8] , HEX[2]);
ssd_out d1(ssd_temp[7:4]  , HEX[1]);
ssd_out d0(ssd_temp[3:0]  , HEX[0]);

always @(posedge clk)
begin
	if(done) begin 
	done <= 0;
	counter <= 1;
	end
	else if(~done & mode & op==3) begin
	counter <= counter << 1; 
	done <= (counter == 1<<(DWIDTH<<1) );
	end
	else 
	done <= 1;
end

always @(posedge clk)
begin
	result <= mode ? (op==0 ? dout_adder
						 	: op==1 ? dout_subtractor 
						 	: op==2 ? dout_multiplier 
						 	: op==3 ? dout_divider
						 	: op==4 ? dout_comparator 
						 	: 		  0)
				   : (op==0 ? dout_and
				   			: op==1 ? dout_or
						 	: op==2 ? dout_xor 
						 	: op==3 ? dout_not
						 	: op==4 ? dout_shift
						 	: op==5 ? dout_ashift  
						 	:   	  0 );
end
always @(posedge done)
begin
	dout <= result;
end
endmodule
module top #(parameter DWIDTH = 8)(
inout clk,
input mode,
input [2:0] op,
input [DWIDTH-1:0] din1,
input [DWIDTH-1:0] din2,
output reg [DWIDTH-1:0] dout
);

reg done;
reg [(DWIDTH<<1):0]counter;

reg [(DWIDTH<<1)-1:0] result;

wire [(DWIDTH<<1)-1:0] dout_adder;
wire [(DWIDTH<<1)-1:0] dout_subtractor;
wire [(DWIDTH<<1)-1:0] dout_multiplier;
wire [(DWIDTH<<1)-1:0] dout_divider;
wire [(DWIDTH<<1)-1:0] dout_comparator;

adder add1(din1,din2,dout_adder);
subtractor sub1(clk,din1,din2,dout_subtractor);
multiplier mult1(din1,din2,dout_multiplier);
divider div1(.clk(clk),.x(din1),.y(din2),.dout(dout_divider));
comparator comp1(din1,din2,dout_comparator);

wire [DWIDTH-1:0] dout_and;
wire [DWIDTH-1:0] dout_or;
wire [DWIDTH-1:0] dout_xor;
wire [DWIDTH-1:0] dout_not;
wire [DWIDTH-1:0] dout_shift;
wire [DWIDTH-1:0] dout_ashift;

and_er and1(din1,din2,dout_and);
or_er or1(din1,din2,dout_or);
xor_er xor1(din1,din2,dout_xor);
not_er not1(din1,dout_not);
shift_er shift1(din1,dir,dout_shift);
ashift_er ashift1(din1,dir,dout_ashift);

wire [11:0] ssd_temp;
BCD_Convert bin_to_bcd(dout[DWIDTH-1:0], ssd_temp);
ssd_out d2(ssd_temp[11:8] , HEX[2]);
ssd_out d1(ssd_temp[7:4]  , HEX[1]);
ssd_out d0(ssd_temp[3:0]  , HEX[0]);

always @(posedge clk)
begin
	if(done) begin 
	done <= 0;
	counter <= 1;
	end
	else if(~done & mode & op==3) begin
	counter <= counter << 1; 
	done <= (counter == 1<<(DWIDTH<<1) );
	end
	else 
	done <= 1;
end

always @(posedge clk)
begin
	result <= mode ? (op==0 ? dout_adder
						 	: op==1 ? dout_subtractor 
						 	: op==2 ? dout_multiplier 
						 	: op==3 ? dout_divider
						 	: op==4 ? dout_comparator 
						 	: 		  0)
				   : (op==0 ? dout_and
				   			: op==1 ? dout_or
						 	: op==2 ? dout_xor 
						 	: op==3 ? dout_not
						 	: op==4 ? dout_shift
						 	: op==5 ? dout_ashift  
						 	:   	  0 );
end
always @(posedge done)
begin
	dout <= result;
end
endmodule