data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'b10000000000000000000000000000000; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'d199999999; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'d90000000; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'b00000000000000000000000000000001; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'d98888888; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'b11111111111111111111111111111110; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'d100000000; \n^\n%Error: data/full_repos/permissive/458134463/Modules/sub_32bit_tb.v:41: Unsupported or unknown PLI call: $monitor\n$monitor("\\nTime  : %1d\\nvalue1: %32b (%8h) (%11d)\\nvalue2: %32b (%8h) (%11d)\\nresult: %32b (%8h) (%11d) - overflow: %1b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sub_32bit_tb();

reg signed [31:0] value1;
reg signed [31:0] value2;

wire signed [31:0] result;
wire overflow;


sub_32bit sub32(value1, value2, result, overflow);


initial begin
        value1   = 32'd222222; 
	     value2   = 32'd200000;
	 
#`DELAY value1   = 32'b10000000000000000000000000000000; 
	     value2   = 32'b01111111111111111111111111111111; 
 
#`DELAY value1   = 32'd199999999; 
	     value2   = 32'd1; 

#`DELAY value1   = 32'd90000000; 
	     value2   = 32'd11111111; 

#`DELAY value1   = 32'b00000000000000000000000000000001; 
        value2   = 32'b00000000000000000000000000000010; 

#`DELAY value1   = 32'd98888888; 
        value2   = 32'd10000091; 

#`DELAY value1   = 32'b11111111111111111111111111111110; 
	     value2   = 32'b01010101010101010101010101010101; 

#`DELAY value1   = 32'd100000000; 
        value2   = 32'd200000000; 
end

initial begin
$monitor("\nTime  : %1d\nvalue1: %32b (%8h) (%11d)\nvalue2: %32b (%8h) (%11d)\nresult: %32b (%8h) (%11d) - overflow: %1b", 
			$time, 
			value1, value1, value1, 
			value2, value2, value2,
			result, result, result,
			overflow);
end

endmodule
module sub_32bit_tb();


reg signed [31:0] value1;
reg signed [31:0] value2;

wire signed [31:0] result;
wire overflow;


sub_32bit sub32(value1, value2, result, overflow);


initial begin
        value1   = 32'd222222; 
	     value2   = 32'd200000;
	 
#`DELAY value1   = 32'b10000000000000000000000000000000; 
	     value2   = 32'b01111111111111111111111111111111; 
 
#`DELAY value1   = 32'd199999999; 
	     value2   = 32'd1; 

#`DELAY value1   = 32'd90000000; 
	     value2   = 32'd11111111; 

#`DELAY value1   = 32'b00000000000000000000000000000001; 
        value2   = 32'b00000000000000000000000000000010; 

#`DELAY value1   = 32'd98888888; 
        value2   = 32'd10000091; 

#`DELAY value1   = 32'b11111111111111111111111111111110; 
	     value2   = 32'b01010101010101010101010101010101; 

#`DELAY value1   = 32'd100000000; 
        value2   = 32'd200000000; 
end

initial begin
$monitor("\nTime  : %1d\nvalue1: %32b (%8h) (%11d)\nvalue2: %32b (%8h) (%11d)\nresult: %32b (%8h) (%11d) - overflow: %1b", 
			$time, 
			value1, value1, value1, 
			value2, value2, value2,
			result, result, result,
			overflow);
end

endmodule