data/full_repos/permissive/456436315/workshop/chap3/cpu/sim.sv
1: b'%Error: data/full_repos/permissive/456436315/workshop/chap3/cpu/sim.sv:20: Unsupported or unknown PLI call: $monitor\n  $monitor("%d: rst=%d pc=%02x insn=%04x reg0_wr=%d reg0=%02x",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/456436315/workshop/chap3/cpu/sim.sv:29: Unsupported: Ignoring delay on this delayed statement.\n  #3\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456436315/workshop/chap3/cpu/sim.sv:34: Unsupported: Ignoring delay on this delayed statement.\nalways #5 begin\n       ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Simulation;

localparam STDIN  = 'h8000_0000;
localparam STDERR = 'h8000_0002;
localparam TIMEOUT = 1000;

logic [15:0] sim_input[0:1023];
logic [15:0] insn;
logic [9:0] pc;
integer num_insn = 0;

assign insn = sim_input[pc];

initial begin

  while ($fscanf(STDIN, "%x", sim_input[num_insn]) == 1)
    num_insn++;


  $monitor("%d: rst=%d pc=%02x insn=%04x reg0_wr=%d reg0=%02x",
           $time, rst, pc, insn, reg0_wr, reg0);


  pc <= 0;
  rst <= 1;
  clk <= 1;


  #3
    rst <= 0;
end


always #5 begin
  clk <= ~clk;
end


always @(posedge clk) begin
  if (rst)
    pc <= 0;
  else if (pc < num_insn - 1)
    pc <= pc + 1;
end


always @(posedge clk) begin
  if (reg0_wr) begin
    $fdisplay(STDERR, "%x", reg0);
    $finish;
  end
  else if ($time > TIMEOUT) begin
    $fdisplay(STDERR, "timeout");
    $finish;
  end
end


logic rst, clk, reg0_wr;
logic [7:0] reg0;
cpu cpu(
  .*,
  .insn(sim_input[pc])
);

endmodule
module Simulation;


localparam STDIN  = 'h8000_0000;
localparam STDERR = 'h8000_0002;
localparam TIMEOUT = 1000;

logic [15:0] sim_input[0:1023];
logic [15:0] insn;
logic [9:0] pc;
integer num_insn = 0;

assign insn = sim_input[pc];

initial begin

  while ($fscanf(STDIN, "%x", sim_input[num_insn]) == 1)
    num_insn++;


  $monitor("%d: rst=%d pc=%02x insn=%04x reg0_wr=%d reg0=%02x",
           $time, rst, pc, insn, reg0_wr, reg0);


  pc <= 0;
  rst <= 1;
  clk <= 1;


  #3
    rst <= 0;
end


always #5 begin
  clk <= ~clk;
end


always @(posedge clk) begin
  if (rst)
    pc <= 0;
  else if (pc < num_insn - 1)
    pc <= pc + 1;
end


always @(posedge clk) begin
  if (reg0_wr) begin
    $fdisplay(STDERR, "%x", reg0);
    $finish;
  end
  else if ($time > TIMEOUT) begin
    $fdisplay(STDERR, "timeout");
    $finish;
  end
end


logic rst, clk, reg0_wr;
logic [7:0] reg0;
cpu cpu(
  .*,
  .insn(sim_input[pc])
);

endmodule