data/full_repos/permissive/473787826/verilog/rtl/SRAM16K.v
1: b"%Error: data/full_repos/permissive/473787826/verilog/rtl/SRAM16K.v:40: Cannot find file containing module: 'sky130_sram_2kbyte_1rw1r_32x512_8'\n            sky130_sram_2kbyte_1rw1r_32x512_8 RAM(\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473787826/verilog/rtl,data/full_repos/permissive/473787826/sky130_sram_2kbyte_1rw1r_32x512_8\n             data/full_repos/permissive/473787826/verilog/rtl,data/full_repos/permissive/473787826/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/473787826/verilog/rtl,data/full_repos/permissive/473787826/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             sky130_sram_2kbyte_1rw1r_32x512_8\n             sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n%Error: Exiting due to 1 error(s)\n"
module SRAM16K(
    input wire clk,
    input wire  [11:0]  addr,
    input wire  [31:0]  wdata,
    output wire [31:0]  rdata,
    input  wire         cs,
    input wire  [3:0]   wen
);


    wire [31:0] sram_rdata[7:0];

    wire [7:0] sram_dec = {
                            (addr[11:9]=='d7),
                            (addr[11:9]=='d6),
                            (addr[11:9]=='d5),
                            (addr[11:9]=='d4),
                            (addr[11:9]=='d3),
                            (addr[11:9]=='d2),
                            (addr[11:9]=='d1),
                            (addr[11:9]=='d0)
                        };

    wire [7:0] sram_csb = ~({8{cs}} & sram_dec);

    reg [2:0] sram_sel;

    always @(posedge clk)
        sram_sel <= addr[11:9];

    assign rdata = sram_rdata[sram_sel];

    generate
        genvar i;
        for(i=0; i<8; i=i+1) begin : BANK
            sky130_sram_2kbyte_1rw1r_32x512_8 RAM(

                .clk0(clk),
                .csb0(sram_csb[i]),
                .web0(~|wen),
                .wmask0(wen),
                .addr0(addr[8:0]),
                .din0(wdata),
                .dout0(sram_rdata[i]),

                .clk1(1'b1),
                .csb1(1'b1),
                .addr1(9'h1FF)

            );
        end
    endgenerate

endmodule
module SRAM16K(
    input wire clk,
    input wire  [11:0]  addr,
    input wire  [31:0]  wdata,
    output wire [31:0]  rdata,
    input  wire         cs,
    input wire  [3:0]   wen
);



    wire [31:0] sram_rdata[7:0];

    wire [7:0] sram_dec = {
                            (addr[11:9]=='d7),
                            (addr[11:9]=='d6),
                            (addr[11:9]=='d5),
                            (addr[11:9]=='d4),
                            (addr[11:9]=='d3),
                            (addr[11:9]=='d2),
                            (addr[11:9]=='d1),
                            (addr[11:9]=='d0)
                        };

    wire [7:0] sram_csb = ~({8{cs}} & sram_dec);

    reg [2:0] sram_sel;

    always @(posedge clk)
        sram_sel <= addr[11:9];

    assign rdata = sram_rdata[sram_sel];

    generate
        genvar i;
        for(i=0; i<8; i=i+1) begin : BANK
            sky130_sram_2kbyte_1rw1r_32x512_8 RAM(

                .clk0(clk),
                .csb0(sram_csb[i]),
                .web0(~|wen),
                .wmask0(wen),
                .addr0(addr[8:0]),
                .din0(wdata),
                .dout0(sram_rdata[i]),

                .clk1(1'b1),
                .csb1(1'b1),
                .addr1(9'h1FF)

            );
        end
    endgenerate

endmodule