data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:768: Bit extraction of var[119:0] requires 7 bit index, not 1 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T83 = io_chanxy_config[2\'h2 :1\'h0 ];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:770: Bit extraction of var[319:0] requires 9 bit index, not 1 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T85 = io_chanxy_in[3\'h7 :1\'h0 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:776: Bit extraction of var[119:0] requires 7 bit index, not 2 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T91 = io_chanxy_config[3\'h5 :2\'h3 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:778: Bit extraction of var[319:0] requires 9 bit index, not 4 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T93 = io_chanxy_in[4\'hf :4\'h8 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:784: Bit extraction of var[119:0] requires 7 bit index, not 3 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T99 = io_chanxy_config[4\'h8 :3\'h6 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:786: Bit extraction of var[319:0] requires 9 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T101 = io_chanxy_in[5\'h17 :5\'h10 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:792: Bit extraction of var[119:0] requires 7 bit index, not 4 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T107 = io_chanxy_config[4\'hb :4\'h9 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:794: Bit extraction of var[319:0] requires 9 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T109 = io_chanxy_in[5\'h1f :5\'h18 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:800: Bit extraction of var[119:0] requires 7 bit index, not 4 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T115 = io_chanxy_config[4\'he :4\'hc ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:802: Bit extraction of var[319:0] requires 9 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T117 = io_chanxy_in[6\'h27 :6\'h20 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:808: Bit extraction of var[119:0] requires 7 bit index, not 4 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T123 = io_chanxy_config[5\'h11 :4\'hf ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:810: Bit extraction of var[319:0] requires 9 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T125 = io_chanxy_in[6\'h2f :6\'h28 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:816: Bit extraction of var[119:0] requires 7 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T131 = io_chanxy_config[5\'h14 :5\'h12 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:818: Bit extraction of var[319:0] requires 9 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T133 = io_chanxy_in[6\'h37 :6\'h30 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:824: Bit extraction of var[119:0] requires 7 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T139 = io_chanxy_config[5\'h17 :5\'h15 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:826: Bit extraction of var[319:0] requires 9 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T141 = io_chanxy_in[6\'h3f :6\'h38 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:832: Bit extraction of var[119:0] requires 7 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T147 = io_chanxy_config[5\'h1a :5\'h18 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:834: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T149 = io_chanxy_in[7\'h47 :7\'h40 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:840: Bit extraction of var[119:0] requires 7 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T155 = io_chanxy_config[5\'h1d :5\'h1b ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:842: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T157 = io_chanxy_in[7\'h4f :7\'h48 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:848: Bit extraction of var[119:0] requires 7 bit index, not 5 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T163 = io_chanxy_config[6\'h20 :5\'h1e ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:850: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T165 = io_chanxy_in[7\'h57 :7\'h50 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:856: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T171 = io_chanxy_config[6\'h23 :6\'h21 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:858: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T173 = io_chanxy_in[7\'h5f :7\'h58 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:864: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T179 = io_chanxy_config[6\'h26 :6\'h24 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:866: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T181 = io_chanxy_in[7\'h67 :7\'h60 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:872: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T187 = io_chanxy_config[6\'h29 :6\'h27 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:874: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T189 = io_chanxy_in[7\'h6f :7\'h68 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:880: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T195 = io_chanxy_config[6\'h2c :6\'h2a ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:882: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T197 = io_chanxy_in[7\'h77 :7\'h70 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:888: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T203 = io_chanxy_config[6\'h2f :6\'h2d ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:890: Bit extraction of var[319:0] requires 9 bit index, not 7 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T205 = io_chanxy_in[7\'h7f :7\'h78 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:896: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T211 = io_chanxy_config[6\'h32 :6\'h30 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:898: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T213 = io_chanxy_in[8\'h87 :8\'h80 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:904: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T219 = io_chanxy_config[6\'h35 :6\'h33 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:906: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T221 = io_chanxy_in[8\'h8f :8\'h88 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:912: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T227 = io_chanxy_config[6\'h38 :6\'h36 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:914: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T229 = io_chanxy_in[8\'h97 :8\'h90 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:920: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T235 = io_chanxy_config[6\'h3b :6\'h39 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:922: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T237 = io_chanxy_in[8\'h9f :8\'h98 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:928: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T243 = io_chanxy_config[6\'h3e :6\'h3c ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:930: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T245 = io_chanxy_in[8\'ha7 :8\'ha0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:936: Bit extraction of var[119:0] requires 7 bit index, not 6 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T251 = io_chanxy_config[7\'h41 :6\'h3f ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:938: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T253 = io_chanxy_in[8\'haf :8\'ha8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:946: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T261 = io_chanxy_in[8\'hb7 :8\'hb0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:954: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T269 = io_chanxy_in[8\'hbf :8\'hb8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:962: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T277 = io_chanxy_in[8\'hc7 :8\'hc0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:970: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T285 = io_chanxy_in[8\'hcf :8\'hc8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:978: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T293 = io_chanxy_in[8\'hd7 :8\'hd0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:986: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T301 = io_chanxy_in[8\'hdf :8\'hd8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:994: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance lut_tile.this_sbcb\n  assign T309 = io_chanxy_in[8\'he7 :8\'he0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1002: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T317 = io_chanxy_in[8\'hef :8\'he8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1010: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T325 = io_chanxy_in[8\'hf7 :8\'hf0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1018: Bit extraction of var[319:0] requires 9 bit index, not 8 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T333 = io_chanxy_in[8\'hff :8\'hf8 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1113: Bit extraction of var[51:0] requires 6 bit index, not 1 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T427 = io_ipin_config[2\'h3 :1\'h0 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1115: Bit extraction of var[155:0] requires 8 bit index, not 1 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T429 = io_ipin_in[4\'hb :1\'h0 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1121: Bit extraction of var[51:0] requires 6 bit index, not 3 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T435 = io_ipin_config[3\'h7 :3\'h4 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1123: Bit extraction of var[155:0] requires 8 bit index, not 4 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T437 = io_ipin_in[5\'h17 :4\'hc ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1129: Bit extraction of var[51:0] requires 6 bit index, not 4 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T443 = io_ipin_config[4\'hb :4\'h8 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1131: Bit extraction of var[155:0] requires 8 bit index, not 5 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T445 = io_ipin_in[6\'h23 :5\'h18 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1137: Bit extraction of var[51:0] requires 6 bit index, not 4 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T451 = io_ipin_config[4\'hf :4\'hc ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1139: Bit extraction of var[155:0] requires 8 bit index, not 6 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T453 = io_ipin_in[6\'h2f :6\'h24 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1145: Bit extraction of var[51:0] requires 6 bit index, not 5 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T459 = io_ipin_config[5\'h13 :5\'h10 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1147: Bit extraction of var[155:0] requires 8 bit index, not 6 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T461 = io_ipin_in[6\'h3b :6\'h30 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1153: Bit extraction of var[51:0] requires 6 bit index, not 5 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T467 = io_ipin_config[5\'h17 :5\'h14 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1155: Bit extraction of var[155:0] requires 8 bit index, not 6 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T469 = io_ipin_in[7\'h47 :6\'h3c ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1161: Bit extraction of var[51:0] requires 6 bit index, not 5 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T475 = io_ipin_config[5\'h1b :5\'h18 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1163: Bit extraction of var[155:0] requires 8 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T477 = io_ipin_in[7\'h53 :7\'h48 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1169: Bit extraction of var[51:0] requires 6 bit index, not 5 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T483 = io_ipin_config[5\'h1f :5\'h1c ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1171: Bit extraction of var[155:0] requires 8 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T485 = io_ipin_in[7\'h5f :7\'h54 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1179: Bit extraction of var[155:0] requires 8 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T493 = io_ipin_in[7\'h6b :7\'h60 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1187: Bit extraction of var[155:0] requires 8 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T501 = io_ipin_in[7\'h77 :7\'h6c ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1195: Bit extraction of var[155:0] requires 8 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile.this_sbcb\n  assign T509 = io_ipin_in[8\'h83 :7\'h78 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:84: Bit extraction of var[4:0] requires 3 bit index, not 2 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T3 = io_mux_configs[2\'h3 :2\'h3 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:85: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T4 = io_lut_configs[6\'h3f :6\'h30 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:86: Bit extraction of var[19:0] requires 5 bit index, not 4 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T5 = io_clb_in[4\'hf :4\'hc ];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:87: Bit extraction of var[4:0] requires 3 bit index, not 2 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T6 = io_mux_configs[2\'h2 :2\'h2 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:88: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T7 = io_lut_configs[6\'h2f :6\'h20 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:89: Bit extraction of var[19:0] requires 5 bit index, not 4 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T8 = io_clb_in[4\'hb :4\'h8 ];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:90: Bit extraction of var[4:0] requires 3 bit index, not 1 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T9 = io_mux_configs[1\'h1 :1\'h1 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:91: Bit extraction of var[79:0] requires 7 bit index, not 5 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T10 = io_lut_configs[5\'h1f :5\'h10 ];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:92: Bit extraction of var[19:0] requires 5 bit index, not 3 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T11 = io_clb_in[3\'h7 :3\'h4 ];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:93: Bit extraction of var[4:0] requires 3 bit index, not 1 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T12 = io_mux_configs[1\'h0 :1\'h0 ];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:94: Bit extraction of var[79:0] requires 7 bit index, not 1 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T13 = io_lut_configs[4\'hf :1\'h0 ];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:95: Bit extraction of var[19:0] requires 5 bit index, not 1 bits.\n                                                                                                                                       : ... In instance lut_tile.this_clb\n  assign T14 = io_clb_in[2\'h3 :1\'h0 ];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1235: Bit extraction of var[383:0] requires 9 bit index, not 8 bits.\n                                                                                                                                         : ... In instance lut_tile\n  assign T0 = this_config_io_configs_out[9\'h164 :8\'hed ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1236: Bit extraction of var[383:0] requires 9 bit index, not 8 bits.\n                                                                                                                                         : ... In instance lut_tile\n  assign T1 = this_config_io_configs_out[8\'hec :8\'hb9 ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1237: Bit extraction of var[383:0] requires 9 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile\n  assign T2 = this_config_io_configs_out[8\'hb8 :7\'h55 ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1239: Bit extraction of var[383:0] requires 9 bit index, not 7 bits.\n                                                                                                                                         : ... In instance lut_tile\n  assign T4 = this_config_io_configs_out[7\'h54 :7\'h50 ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1240: Bit extraction of var[383:0] requires 9 bit index, not 1 bits.\n                                                                                                                                         : ... In instance lut_tile\n  assign T5 = this_config_io_configs_out[7\'h4f :1\'h0 ];\n                                        ^\n%Error: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1249: Cannot find file containing module: \'xbar\'\n  xbar this_xbar(.clk(clk), .reset(reset),\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src,data/full_repos/permissive/49670587/xbar\n             data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src,data/full_repos/permissive/49670587/xbar.v\n             data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src,data/full_repos/permissive/49670587/xbar.sv\n             xbar\n             xbar.v\n             xbar.sv\n             obj_dir/xbar\n             obj_dir/xbar.v\n             obj_dir/xbar.sv\n%Error: data/full_repos/permissive/49670587/archipelago/verilog/lut_tile/sweep/lut_tile_4_5_12_8_80/generated-src/lut_tile.v:1253: Cannot find file containing module: \'configs_latches\'\n  configs_latches this_config(.clk(clk), .reset(reset),\n  ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 90 warning(s)\n'
module lut_tile(input clk, input reset,
    input  io_ff_en,
    input [31:0] io_configs_in,
    input [11:0] io_configs_en,
    input [155:0] io_ipin_in,
    input [319:0] io_chanxy_in,
    output[39:0] io_chanxy_out,
    output[4:0] io_opin_out);

  wire[119:0] T0;
  wire[383:0] this_config_io_configs_out;
  wire[51:0] T1;
  wire[99:0] T2;
  wire[17:0] T3;
  wire[12:0] this_sbcb_io_ipin_out;
  wire[4:0] this_clb_io_clb_out;
  wire[4:0] T4;
  wire[79:0] T5;
  wire[19:0] this_xbar_io_xbar_out;
  wire[39:0] this_sbcb_io_chanxy_out;

  assign T0 = this_config_io_configs_out[9'h164:8'hed];
  assign T1 = this_config_io_configs_out[8'hec:8'hb9];
  assign T2 = this_config_io_configs_out[8'hb8:7'h55];
  assign T3 = {this_clb_io_clb_out, this_sbcb_io_ipin_out};
  assign T4 = this_config_io_configs_out[7'h54:7'h50];
  assign T5 = this_config_io_configs_out[7'h4f:1'h0];
  assign io_opin_out = this_clb_io_clb_out;
  assign io_chanxy_out = this_sbcb_io_chanxy_out;
  clb this_clb(.clk(clk), .reset(reset),
       .io_clb_in( this_xbar_io_xbar_out ),
       .io_clb_out( this_clb_io_clb_out ),
       .io_lut_configs( T5 ),
       .io_mux_configs( T4 ),
       .io_ff_en( io_ff_en ));
  xbar this_xbar(.clk(clk), .reset(reset),
       .io_xbar_in( T3 ),
       .io_xbar_out( this_xbar_io_xbar_out ),
       .io_mux_configs( T2 ));
  configs_latches this_config(.clk(clk), .reset(reset),
       .io_d_in( io_configs_in ),
       .io_configs_out( this_config_io_configs_out ),
       .io_configs_en( io_configs_en ));
  sbcb this_sbcb(
       .io_ipin_in( io_ipin_in ),
       .io_ipin_config( T1 ),
       .io_chanxy_in( io_chanxy_in ),
       .io_chanxy_config( T0 ),
       .io_ipin_out( this_sbcb_io_ipin_out ),
       .io_chanxy_out( this_sbcb_io_chanxy_out ));
endmodule
module lut_tile(input clk, input reset,
    input  io_ff_en,
    input [31:0] io_configs_in,
    input [11:0] io_configs_en,
    input [155:0] io_ipin_in,
    input [319:0] io_chanxy_in,
    output[39:0] io_chanxy_out,
    output[4:0] io_opin_out);


  wire[119:0] T0;
  wire[383:0] this_config_io_configs_out;
  wire[51:0] T1;
  wire[99:0] T2;
  wire[17:0] T3;
  wire[12:0] this_sbcb_io_ipin_out;
  wire[4:0] this_clb_io_clb_out;
  wire[4:0] T4;
  wire[79:0] T5;
  wire[19:0] this_xbar_io_xbar_out;
  wire[39:0] this_sbcb_io_chanxy_out;

  assign T0 = this_config_io_configs_out[9'h164:8'hed];
  assign T1 = this_config_io_configs_out[8'hec:8'hb9];
  assign T2 = this_config_io_configs_out[8'hb8:7'h55];
  assign T3 = {this_clb_io_clb_out, this_sbcb_io_ipin_out};
  assign T4 = this_config_io_configs_out[7'h54:7'h50];
  assign T5 = this_config_io_configs_out[7'h4f:1'h0];
  assign io_opin_out = this_clb_io_clb_out;
  assign io_chanxy_out = this_sbcb_io_chanxy_out;
  clb this_clb(.clk(clk), .reset(reset),
       .io_clb_in( this_xbar_io_xbar_out ),
       .io_clb_out( this_clb_io_clb_out ),
       .io_lut_configs( T5 ),
       .io_mux_configs( T4 ),
       .io_ff_en( io_ff_en ));
  xbar this_xbar(.clk(clk), .reset(reset),
       .io_xbar_in( T3 ),
       .io_xbar_out( this_xbar_io_xbar_out ),
       .io_mux_configs( T2 ));
  configs_latches this_config(.clk(clk), .reset(reset),
       .io_d_in( io_configs_in ),
       .io_configs_out( this_config_io_configs_out ),
       .io_configs_en( io_configs_en ));
  sbcb this_sbcb(
       .io_ipin_in( io_ipin_in ),
       .io_ipin_config( T1 ),
       .io_chanxy_in( io_chanxy_in ),
       .io_chanxy_config( T0 ),
       .io_ipin_out( this_sbcb_io_ipin_out ),
       .io_chanxy_out( this_sbcb_io_chanxy_out ));
endmodule