data/full_repos/permissive/46804359/sign_extender_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46804359/sign_extender_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46804359/sign_extender_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Error: data/full_repos/permissive/46804359/sign_extender_tb.v:8: Cannot find file containing module: \'sign_extender\'\nsign_extender DUT(clk, in, out);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/sign_extender\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/sign_extender.v\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/sign_extender.sv\n             sign_extender\n             sign_extender.v\n             sign_extender.sv\n             obj_dir/sign_extender\n             obj_dir/sign_extender.v\n             obj_dir/sign_extender.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sign_extender_tb;

reg clk;
reg [15:0] in;

wire [31:0] out;

sign_extender DUT(clk, in, out);


initial begin
    clk=0;
end


always #5 clk=~clk;


initial begin
    in = 16'b0000000000000000;

    #15
    in = 16'b1000000000000000;
end

endmodule
module sign_extender_tb;


reg clk;
reg [15:0] in;

wire [31:0] out;

sign_extender DUT(clk, in, out);


initial begin
    clk=0;
end


always #5 clk=~clk;


initial begin
    in = 16'b0000000000000000;

    #15
    in = 16'b1000000000000000;
end

endmodule