data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:83: syntax error, unexpected \'@\'\n @(negedge tb_clk_50)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:87: syntax error, unexpected \'@\'\n @(negedge tb_clk_50)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:92: syntax error, unexpected \'@\'\n  @(negedge tb_clk_50)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/MUXDC_tb.v:97: syntax error, unexpected \'@\'\n @(negedge tb_clk_50)\n ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MUXDC_tb();


parameter LENGTHBUS=9;
parameter BITWIDTH_W_COLUMS=4; 
parameter BITWIDTH_MAX_W_SIZE=9;
integer i;



reg tb_clk_50;
reg tb_Reset;
reg tb_Set_Conf;
reg tb_Set_Conf_Already_Ok;
reg [BITWIDTH_W_COLUMS-1:0] tb_W_Colums;
reg [BITWIDTH_MAX_W_SIZE-1:0] tb_W_ROXCL;


wire [LENGTHBUS-2:0] tb_Muxes_Sel;
wire tb_Set_Conf_Already;




MUXDC #(.LENGTHBUS(LENGTHBUS-1)) Muxdc(


.MUXDC_Clk(tb_clk_50),
.MUXDC_Reset(tb_Reset),
.MUXDC_Set_Conf(tb_Set_Conf),
.MUXDC_Set_Conf_Already_Ok(tb_Set_Conf_Already_Ok),
.MUXDC_W_Colums(tb_W_Colums),
.MUXDC_W_ROXCL(tb_W_ROXCL),


.MUXDC_Muxes_Sel(tb_Muxes_Sel),
.MUXDC_Set_Conf_Already(tb_Set_Conf_Already)

);


always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end


initial
begin

	tb_Reset<=0;
	tb_Set_Conf<=0;
	tb_Set_Conf_Already_Ok<=0;
	tb_W_Colums<=3;
	tb_W_ROXCL<=(9-1);
	 
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf<=1;
	tb_Reset<=1;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf<=0;
	
	for(i=0;tb_Set_Conf_Already == 1'b0 ;i=i+1)begin
		@(negedge tb_clk_50)
		@(posedge tb_clk_50);
	end
	
	tb_Set_Conf_Already_Ok<=1'b1;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf_Already_Ok<=1'b0;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	
	$stop;

end



endmodule
module MUXDC_tb();



parameter LENGTHBUS=9;
parameter BITWIDTH_W_COLUMS=4; 
parameter BITWIDTH_MAX_W_SIZE=9;
integer i;



reg tb_clk_50;
reg tb_Reset;
reg tb_Set_Conf;
reg tb_Set_Conf_Already_Ok;
reg [BITWIDTH_W_COLUMS-1:0] tb_W_Colums;
reg [BITWIDTH_MAX_W_SIZE-1:0] tb_W_ROXCL;


wire [LENGTHBUS-2:0] tb_Muxes_Sel;
wire tb_Set_Conf_Already;




MUXDC #(.LENGTHBUS(LENGTHBUS-1)) Muxdc(


.MUXDC_Clk(tb_clk_50),
.MUXDC_Reset(tb_Reset),
.MUXDC_Set_Conf(tb_Set_Conf),
.MUXDC_Set_Conf_Already_Ok(tb_Set_Conf_Already_Ok),
.MUXDC_W_Colums(tb_W_Colums),
.MUXDC_W_ROXCL(tb_W_ROXCL),


.MUXDC_Muxes_Sel(tb_Muxes_Sel),
.MUXDC_Set_Conf_Already(tb_Set_Conf_Already)

);


always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end


initial
begin

	tb_Reset<=0;
	tb_Set_Conf<=0;
	tb_Set_Conf_Already_Ok<=0;
	tb_W_Colums<=3;
	tb_W_ROXCL<=(9-1);
	 
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf<=1;
	tb_Reset<=1;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf<=0;
	
	for(i=0;tb_Set_Conf_Already == 1'b0 ;i=i+1)begin
		@(negedge tb_clk_50)
		@(posedge tb_clk_50);
	end
	
	tb_Set_Conf_Already_Ok<=1'b1;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_Set_Conf_Already_Ok<=1'b0;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	
	$stop;

end



endmodule