data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv
1: b'%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:41: Unsupported: Static in this context\n    static int seed = $urandom + 0;\n    ^~~~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:41: Unsupported or unknown PLI call: $urandom\n    static int seed = $urandom + 0;\n                      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:100: Unsupported: Ignoring delay on this delayed statement.\n        #(2 * C_CLK_PERIOD) rRstb <= 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:101: Unsupported: Ignoring delay on this delayed statement.\n        #(10 * C_CLK_PERIOD) rRstb <= 1\'b1;\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:108: Unsupported or unknown PLI call: $dist_normal\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n                  ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:108: Unsupported: Ignoring delay on this delayed statement.\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:114: Unsupported: Ignoring delay on this delayed statement.\n        #(C_UART_PERIOD / 2);\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:122: Unsupported or unknown PLI call: $dist_normal\n        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));\n          ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:122: Unsupported: Ignoring delay on this delayed statement.\n        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:128: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:131: Unsupported or unknown PLI call: $urandom_range\n            rData <= $urandom_range(0, 255);\n                     ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:132: Unsupported: Ignoring delay on this delayed statement.\n            #1 rSend <= 1\'b1;\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:135: Unsupported: wait statements\n            wait(wBusy == 1\'b1);\n            ^~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:136: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Rx_tb.sv:137: Unsupported: Ignoring delay on this delayed statement.\n            #1 rSend <= 1\'b0;\n            ^\n%Error: Exiting due to 8 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_Rx_tb();
    



    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_RATE       = 1000000;
    parameter C_UART_DATA_WIDTH = 8;
    parameter C_UART_PARITY     = 0;
    parameter C_UART_STOP       = 1;
    localparam real C_UART_PERIOD = 1E9 / C_UART_RATE;






        

    static int seed = $urandom + 0;

    
    



    

    reg rRstb;
    reg rClk;
    reg rUART_Clk;
    

    wire wTx;
    wire wBusy;
    wire wErr;
                   

    reg [C_UART_DATA_WIDTH - 1:0] rData;
    reg rSend;








    UART_Tx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH) 
    ) DUT (
        .rstb(rRstb),
        .clk(rClk),
        .data(rData),
        .send(rSend),
        .busy(wBusy),
        .error(wError),
        .tx(wTx)
    );
    
    
        



    

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rUART_Clk = 1'b0; 
        rSend = 1'b0;
             

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    

    always begin
        #(C_UART_PERIOD / 2);
        rUART_Clk <= ! rUART_Clk;
    end      
    

    always begin
        

        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));
                

        if (wBusy == 1'b0) begin
            

            @(posedge rClk);
            

            rData <= $urandom_range(0, 255);
            #1 rSend <= 1'b1;
        

            wait(wBusy == 1'b1);
            @(posedge rClk);
            #1 rSend <= 1'b0;
        end
   end        
endmodule
module UART_Rx_tb();

    



    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_RATE       = 1000000;
    parameter C_UART_DATA_WIDTH = 8;
    parameter C_UART_PARITY     = 0;
    parameter C_UART_STOP       = 1;
    localparam real C_UART_PERIOD = 1E9 / C_UART_RATE;






        

    static int seed = $urandom + 0;

    
    



    

    reg rRstb;
    reg rClk;
    reg rUART_Clk;
    

    wire wTx;
    wire wBusy;
    wire wErr;
                   

    reg [C_UART_DATA_WIDTH - 1:0] rData;
    reg rSend;








    UART_Tx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH) 
    ) DUT (
        .rstb(rRstb),
        .clk(rClk),
        .data(rData),
        .send(rSend),
        .busy(wBusy),
        .error(wError),
        .tx(wTx)
    );
    
    
        



    

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rUART_Clk = 1'b0; 
        rSend = 1'b0;
             

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    

    always begin
        #(C_UART_PERIOD / 2);
        rUART_Clk <= ! rUART_Clk;
    end      
    

    always begin
        

        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));
                

        if (wBusy == 1'b0) begin
            

            @(posedge rClk);
            

            rData <= $urandom_range(0, 255);
            #1 rSend <= 1'b1;
        

            wait(wBusy == 1'b1);
            @(posedge rClk);
            #1 rSend <= 1'b0;
        end
   end        
endmodule