data/full_repos/permissive/469273213/counter/rtl/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;       \n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, counter_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #3 rst_n = 1\'b0; #5 rst_n = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #3 rst_n = 1\'b0; #5 rst_n = 1\'b1;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5 en = 1\'b1; #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5 en = 1\'b1; #5;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #30 load = 1\'b1; #10 load = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #30 load = 1\'b1; #10 load = 1\'b0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20 dn = 1\'b1; #20 dn = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20 dn = 1\'b1; #20 dn = 1\'b0;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #15 en = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #30 load = 1\'b1; #10 load = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #30 load = 1\'b1; #10 load = 1\'b0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20 dn = 1\'b1; #20 dn = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20 dn = 1\'b1; #20 dn = 1\'b0;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 en = 1\'b1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/counter/rtl/counter_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #30 $finish();\n        ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;

    parameter WIDTH = 4;
    reg clk, rst_n, en, dn, load;
    reg [WIDTH-1:0] data;
    wire [WIDTH-1:0] count;

    initial begin
        forever #5 clk = ~clk;
    end
    initial begin
        $dumpfile("counter.vcd");
        $dumpvars(0, counter_tb);
        clk = 1'b0; rst_n = 1'b1; en = 1'b0; dn = 1'b0; load = 1'b0; data = 7;
        #3 rst_n = 1'b0; #5 rst_n = 1'b1;
        #5 en = 1'b1; #5;
        #30 load = 1'b1; #10 load = 1'b0;
        #20 dn = 1'b1; #20 dn = 1'b0;
        #15 en = 1'b0;
        #30 load = 1'b1; #10 load = 1'b0;
        #20 dn = 1'b1; #20 dn = 1'b0;
        #10 en = 1'b1; 
        #30 $finish();
    end

    counter # (.WIDTH(WIDTH)) dut (.clk(clk), .rst_n(rst_n), .en(en), .dn(dn), 
        .load(load), .data(data), .count(count));
    
endmodule
module counter_tb;


    parameter WIDTH = 4;
    reg clk, rst_n, en, dn, load;
    reg [WIDTH-1:0] data;
    wire [WIDTH-1:0] count;

    initial begin
        forever #5 clk = ~clk;
    end
    initial begin
        $dumpfile("counter.vcd");
        $dumpvars(0, counter_tb);
        clk = 1'b0; rst_n = 1'b1; en = 1'b0; dn = 1'b0; load = 1'b0; data = 7;
        #3 rst_n = 1'b0; #5 rst_n = 1'b1;
        #5 en = 1'b1; #5;
        #30 load = 1'b1; #10 load = 1'b0;
        #20 dn = 1'b1; #20 dn = 1'b0;
        #15 en = 1'b0;
        #30 load = 1'b1; #10 load = 1'b0;
        #20 dn = 1'b1; #20 dn = 1'b0;
        #10 en = 1'b1; 
        #30 $finish();
    end

    counter # (.WIDTH(WIDTH)) dut (.clk(clk), .rst_n(rst_n), .en(en), .dn(dn), 
        .load(load), .data(data), .count(count));
    
endmodule