data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/cachelib/v_rtl/dut_LessThan_8Sx8S_1U_4.v
data/verilator_xmls/338b766d-b431-468b-aa48-0f3db5a54d01.xml
module dut_LessThan_8Sx8S_1U_4 (
	in2,
	in1,
	out1
	);
input [7:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((13'B1000000000000 ^ {{5{in1[7]}}, in1})>(13'B1000000000000 ^ {{5{in2[7]}}, in2}));

assign out1 = asc001;
endmodule
module dut_LessThan_8Sx8S_1U_4 (
	in2,
	in1,
	out1
	);

input [7:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((13'B1000000000000 ^ {{5{in1[7]}}, in1})>(13'B1000000000000 ^ {{5{in2[7]}}, in2}));

assign out1 = asc001;
endmodule