data/full_repos/permissive/407964434/submodules/hdl_rosetta_stone/verilog/hdl/axistream_wait_until.v
data/verilator_xmls/62df0828-aa62-4ee1-a897-32f31ddf2cef.xml
module axistream_wait_until
  (
   clk,
   rst,

   src_tvalid,
   src_tready,
   src_tdata,
   src_tlast,

   dest_tvalid,
   dest_tready,
   dest_tdata,
   dest_tlast,
   go
   );

   parameter DATA_WIDTH = 8;
   input clk;
   input rst;
   
   input src_tvalid;
   output src_tready;
   input  [DATA_WIDTH-1:0] src_tdata;
   input  src_tlast;
   output dest_tvalid;
   input dest_tready;
   output [DATA_WIDTH-1:0] dest_tdata;
   output dest_tlast;
   input  go;
   
   localparam SM_WAIT = 0;
   localparam SM_GO = 1;
   
   reg sm;
   
   assign dest_tvalid = (sm == SM_GO) ? src_tvalid && !rst : 1'b0;
   assign src_tready  = (sm == SM_GO) ? dest_tready && !rst : 1'b0;
   assign dest_tlast  = (sm == SM_GO) ? dest_tlast && dest_tvalid : 1'b0;
   assign dest_tdata  = src_tdata;

   initial begin
      sm <= SM_WAIT;
   end

   always @(posedge clk) begin
      case (sm)
	SM_WAIT: sm <= (go) ? SM_WAIT : SM_GO;
	SM_GO  : sm <= (dest_tvalid && dest_tready && dest_tlast)?SM_WAIT:SM_GO;
      endcase 
      if (rst) begin
	 sm <= SM_WAIT;
      end
   end

endmodule
module axistream_wait_until
  (
   clk,
   rst,

   src_tvalid,
   src_tready,
   src_tdata,
   src_tlast,

   dest_tvalid,
   dest_tready,
   dest_tdata,
   dest_tlast,
   go
   );


   parameter DATA_WIDTH = 8;
   input clk;
   input rst;
   
   input src_tvalid;
   output src_tready;
   input  [DATA_WIDTH-1:0] src_tdata;
   input  src_tlast;
   output dest_tvalid;
   input dest_tready;
   output [DATA_WIDTH-1:0] dest_tdata;
   output dest_tlast;
   input  go;
   
   localparam SM_WAIT = 0;
   localparam SM_GO = 1;
   
   reg sm;
   
   assign dest_tvalid = (sm == SM_GO) ? src_tvalid && !rst : 1'b0;
   assign src_tready  = (sm == SM_GO) ? dest_tready && !rst : 1'b0;
   assign dest_tlast  = (sm == SM_GO) ? dest_tlast && dest_tvalid : 1'b0;
   assign dest_tdata  = src_tdata;

   initial begin
      sm <= SM_WAIT;
   end

   always @(posedge clk) begin
      case (sm)
	SM_WAIT: sm <= (go) ? SM_WAIT : SM_GO;
	SM_GO  : sm <= (dest_tvalid && dest_tready && dest_tlast)?SM_WAIT:SM_GO;
      endcase 
      if (rst) begin
	 sm <= SM_WAIT;
      end
   end

endmodule