data/full_repos/permissive/424292861/guia9/Exemplo_0904.v
1: b'%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:1: Cannot find include file: clock.v\n`include "clock.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/424292861/guia9,data/full_repos/permissive/424292861/clock.v\n             data/full_repos/permissive/424292861/guia9,data/full_repos/permissive/424292861/clock.v.v\n             data/full_repos/permissive/424292861/guia9,data/full_repos/permissive/424292861/clock.v.sv\n             clock.v\n             clock.v.v\n             clock.v.sv\n             obj_dir/clock.v\n             obj_dir/clock.v.v\n             obj_dir/clock.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #6 signal = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #6 signal = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #6 signal = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:21: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Exemplo_0804.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:22: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0904.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #120 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module pulseMeio(clock,signal);
	input clock;
	output signal;
	reg signal;
	always @ (posedge clock) begin
			signal = 1'b1;
		#6 signal = 1'b0;
		#6 signal = 1'b1;
		#6 signal = 1'b0;
	end
endmodule
module pulseMeio(clock,signal);

	input clock;
	output signal;
	reg signal;
	always @ (posedge clock) begin
			signal = 1'b1;
		#6 signal = 1'b0;
		#6 signal = 1'b1;
		#6 signal = 1'b0;
	end
endmodule