data/full_repos/permissive/492462267/min_sopc_testbench.v
1: b'%Error: data/full_repos/permissive/492462267/min_sopc_testbench.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/492462267/min_sopc_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk_50 = ~clk_50;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492462267/min_sopc_testbench.v:20: Define or directive not defined: \'`Enable\'\n   rst      = `Enable;\n              ^~~~~~~\n%Error: data/full_repos/permissive/492462267/min_sopc_testbench.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   rst      = `Enable;\n                     ^\n%Error: data/full_repos/permissive/492462267/min_sopc_testbench.v:21: Define or directive not defined: \'`Disable\'\n   #195 rst = `Disable;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/min_sopc_testbench.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   #195 rst = `Disable;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/492462267/min_sopc_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #195 rst = `Disable;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/492462267/min_sopc_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #1000 $stop;  \n   ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module min_sopc_testbench ();

reg clk_50;
reg rst;


initial begin
    clk_50 = 1'b0;
    forever #10 clk_50 = ~clk_50;
end



initial begin
   rst      = `Enable;
   #195 rst = `Disable;
   #1000 $stop;  
end



min_sopc min_sopc0(
    .clk(clk_50),
    .rst(rst)
);

endmodule
module min_sopc_testbench ();


reg clk_50;
reg rst;


initial begin
    clk_50 = 1'b0;
    forever #10 clk_50 = ~clk_50;
end



initial begin
   rst      = `Enable;
   #195 rst = `Disable;
   #1000 $stop;  
end



min_sopc min_sopc0(
    .clk(clk_50),
    .rst(rst)
);

endmodule