data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module mirror #(parameter WIDTH=32 ) (
	input wire [WIDTH-1:0]  in, 
	output reg [WIDTH-1:0]  out
);
    integer i;
    localparam LAST_BIT = WIDTH - 1;
    always @*
        for(i=0; i<WIDTH; i=i+1)
            out[i] = in[LAST_BIT-i];
endmodule
module mirror #(parameter WIDTH=32 ) (
	input wire [WIDTH-1:0]  in, 
	output reg [WIDTH-1:0]  out
);

    integer i;
    localparam LAST_BIT = WIDTH - 1;
    always @*
        for(i=0; i<WIDTH; i=i+1)
            out[i] = in[LAST_BIT-i];
endmodule