data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v
1: b'%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:201: Cannot find file containing module: \'prcfg_adc\'\n          prcfg_adc #(\n          ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common,data/full_repos/permissive/40989439/prcfg_adc\n             data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common,data/full_repos/permissive/40989439/prcfg_adc.v\n             data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common,data/full_repos/permissive/40989439/prcfg_adc.sv\n             prcfg_adc\n             prcfg_adc.v\n             prcfg_adc.sv\n             obj_dir/prcfg_adc\n             obj_dir/prcfg_adc.v\n             obj_dir/prcfg_adc.sv\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:216: Cannot find file containing module: \'prcfg_dac\'\n        prcfg_dac #(\n        ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:257: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'core_dac_0_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_dac_data_s[0] = core_dac_0_data;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:260: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'core_dac_1_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_dac_data_s[1] = core_dac_1_data;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:263: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'core_dac_2_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_dac_data_s[2] = core_dac_2_data;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:266: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'core_dac_3_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_dac_data_s[3] = core_dac_3_data;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:270: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_dac_0_data = dma_dac_data_s[0];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:273: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_dac_1_data = dma_dac_data_s[1];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:276: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_dac_2_data = dma_dac_data_s[2];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:279: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_dac_3_data = dma_dac_data_s[3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:283: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_adc_0_data = core_adc_data_s[0];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:286: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_adc_1_data = core_adc_data_s[1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:289: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_adc_2_data = core_adc_data_s[2];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:292: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign core_adc_3_data = core_adc_data_s[3];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:296: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_adc_0_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_adc_data_s[0] = dma_adc_0_data;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:299: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_adc_1_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_adc_data_s[1] = dma_adc_1_data;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:302: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_adc_2_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_adc_data_s[2] = dma_adc_2_data;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/prcfg/common/prcfg_top.v:305: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_adc_3_data\' generates 64 bits.\n                                                                                                  : ... In instance prcfg_top\n  assign dma_adc_data_s[3] = dma_adc_3_data;\n                           ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n'
module prcfg_top(

  clk,


  dac_gpio_input,
  dac_gpio_output,
  adc_gpio_input,
  adc_gpio_output,


  dma_dac_0_enable,
  dma_dac_0_data,
  dma_dac_0_valid,
  dma_dac_1_enable,
  dma_dac_1_data,
  dma_dac_1_valid,
  dma_dac_2_enable,
  dma_dac_2_data,
  dma_dac_2_valid,
  dma_dac_3_enable,
  dma_dac_3_data,
  dma_dac_3_valid,

  core_dac_0_enable,
  core_dac_0_data,
  core_dac_0_valid,
  core_dac_1_enable,
  core_dac_1_data,
  core_dac_1_valid,
  core_dac_2_enable,
  core_dac_2_data,
  core_dac_2_valid,
  core_dac_3_enable,
  core_dac_3_data,
  core_dac_3_valid,


  dma_adc_0_enable,
  dma_adc_0_data,
  dma_adc_0_valid,
  dma_adc_1_enable,
  dma_adc_1_data,
  dma_adc_1_valid,
  dma_adc_2_enable,
  dma_adc_2_data,
  dma_adc_2_valid,
  dma_adc_3_enable,
  dma_adc_3_data,
  dma_adc_3_valid,

  core_adc_0_enable,
  core_adc_0_data,
  core_adc_0_valid,
  core_adc_1_enable,
  core_adc_1_data,
  core_adc_1_valid,
  core_adc_2_enable,
  core_adc_2_data,
  core_adc_2_valid,
  core_adc_3_enable,
  core_adc_3_data,
  core_adc_3_valid
);

  localparam  ENABELED    = 1;
  localparam  DATA_WIDTH  = 16;

  parameter   NUM_CHANNEL = 4;
  parameter   ADC_EN      = 1;
  parameter   DAC_EN      = 1;

  localparam  DBUS_WIDTH  = DATA_WIDTH * NUM_CHANNEL;

  input                             clk;

  input   [31:0]                    dac_gpio_input;
  output  [31:0]                    dac_gpio_output;
  input   [31:0]                    adc_gpio_input;
  output  [31:0]                    adc_gpio_output;

  input                             dma_dac_0_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_0_data;
  input                             dma_dac_0_valid;
  input                             dma_dac_1_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_1_data;
  input                             dma_dac_1_valid;
  input                             dma_dac_2_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_2_data;
  input                             dma_dac_2_valid;
  input                             dma_dac_3_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_3_data;
  input                             dma_dac_3_valid;

  output                            core_dac_0_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_0_data;
  output                            core_dac_0_valid;
  output                            core_dac_1_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_1_data;
  output                            core_dac_1_valid;
  output                            core_dac_2_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_2_data;
  output                            core_dac_2_valid;
  output                            core_dac_3_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_3_data;
  output                            core_dac_3_valid;


  input                             dma_adc_0_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_0_data;
  input                             dma_adc_0_valid;
  input                             dma_adc_1_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_1_data;
  input                             dma_adc_1_valid;
  input                             dma_adc_2_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_2_data;
  input                             dma_adc_2_valid;
  input                             dma_adc_3_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_3_data;
  input                             dma_adc_3_valid;

  output                            core_adc_0_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_0_data;
  output                            core_adc_0_valid;
  output                            core_adc_1_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_1_data;
  output                            core_adc_1_valid;
  output                            core_adc_2_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_2_data;
  output                            core_adc_2_valid;
  output                            core_adc_3_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_3_data;
  output                            core_adc_3_valid;

  wire    [31:0]                    adc_gpio_out_s[(NUM_CHANNEL - 1):0];
  wire    [(NUM_CHANNEL - 1):0]     adc_gpio_out_s_inv[31:0];

  wire    [31:0]                    dac_gpio_out_s[(NUM_CHANNEL - 1):0];
  wire    [(NUM_CHANNEL - 1):0]     dac_gpio_out_s_inv[31:0];

  wire    [(NUM_CHANNEL - 1):0]     core_adc_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     core_adc_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     core_adc_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     core_dac_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     core_dac_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     core_dac_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_data_s[15:0];

  genvar l_inst;

  generate
    for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
      if(ADC_EN == ENABELED) begin
          prcfg_adc #(
            .CHANNEL_ID(l_inst)
          ) i_prcfg_adc_i (
            .clk(clk),
            .control(adc_gpio_input),
            .status(adc_gpio_out_s[l_inst]),
            .src_adc_enable(core_adc_enable_s[l_inst]),
            .src_adc_valid(core_adc_valid_s[l_inst]),
            .src_adc_data(core_adc_data_s[l_inst]),
            .dst_adc_enable(dma_adc_enable_s[l_inst]),
            .dst_adc_valid(dma_adc_valid_s[l_inst]),
            .dst_adc_data(dma_adc_data_s[l_inst])
          );
      end
      if(DAC_EN == ENABELED) begin
        prcfg_dac #(
          .CHANNEL_ID(l_inst)
        ) i_prcfg_dac_i (
          .clk(clk),
          .control(dac_gpio_input),
          .status(dac_gpio_out_s[l_inst]),
          .src_dac_enable(dma_dac_enable_s[l_inst]),
          .src_dac_data(dma_dac_data_s[l_inst]),
          .src_dac_valid(dma_dac_valid_s[l_inst]),
          .dst_dac_enable(core_dac_enable_s[l_inst]),
          .dst_dac_data(core_dac_data_s[l_inst]),
          .dst_dac_valid(core_dac_valid_s[l_inst])
        );
      end
    end
  endgenerate

  genvar i;
  genvar j;

  generate
  for(i = 0; i < 32; i = i + 1) begin
    for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
      assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
      assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
    end
  end
  endgenerate


  generate
  for(i = 0; i < 32; i = i + 1) begin
    assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
    assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
  end
  endgenerate



  assign core_dac_0_enable = core_dac_enable_s[0];
  assign core_dac_0_valid = core_dac_valid_s[0];
  assign core_dac_data_s[0] = core_dac_0_data;
  assign core_dac_1_enable = core_dac_enable_s[1];
  assign core_dac_1_valid = core_dac_valid_s[1];
  assign core_dac_data_s[1] = core_dac_1_data;
  assign core_dac_2_enable = core_dac_enable_s[2];
  assign core_dac_2_valid = core_dac_valid_s[2];
  assign core_dac_data_s[2] = core_dac_2_data;
  assign core_dac_3_enable = core_dac_enable_s[3];
  assign core_dac_3_valid = core_dac_valid_s[3];
  assign core_dac_data_s[3] = core_dac_3_data;

  assign dma_dac_enable_s[0] = dma_dac_0_enable;
  assign dma_dac_valid_s[0] = dma_dac_0_valid;
  assign dma_dac_0_data = dma_dac_data_s[0];
  assign dma_dac_enable_s[1] = dma_dac_1_enable;
  assign dma_dac_valid_s[1] = dma_dac_1_valid;
  assign dma_dac_1_data = dma_dac_data_s[1];
  assign dma_dac_enable_s[2] = dma_dac_2_enable;
  assign dma_dac_valid_s[2] = dma_dac_2_valid;
  assign dma_dac_2_data = dma_dac_data_s[2];
  assign dma_dac_enable_s[3] = dma_dac_3_enable;
  assign dma_dac_valid_s[3] = dma_dac_3_valid;
  assign dma_dac_3_data = dma_dac_data_s[3];

  assign core_adc_0_enable = core_adc_enable_s[0];
  assign core_adc_0_valid = core_adc_valid_s[0];
  assign core_adc_0_data = core_adc_data_s[0];
  assign core_adc_1_enable = core_adc_enable_s[1];
  assign core_adc_1_valid = core_adc_valid_s[1];
  assign core_adc_1_data = core_adc_data_s[1];
  assign core_adc_2_enable = core_adc_enable_s[2];
  assign core_adc_2_valid = core_adc_valid_s[2];
  assign core_adc_2_data = core_adc_data_s[2];
  assign core_adc_3_enable = core_adc_enable_s[3];
  assign core_adc_3_valid = core_adc_valid_s[3];
  assign core_adc_3_data = core_adc_data_s[3];

  assign dma_adc_enable_s[0] = dma_adc_0_enable;
  assign dma_adc_valid_s[0] = dma_adc_0_valid;
  assign dma_adc_data_s[0] = dma_adc_0_data;
  assign dma_adc_enable_s[1] = dma_adc_1_enable;
  assign dma_adc_valid_s[1] = dma_adc_1_valid;
  assign dma_adc_data_s[1] = dma_adc_1_data;
  assign dma_adc_enable_s[2] = dma_adc_2_enable;
  assign dma_adc_valid_s[2] = dma_adc_2_valid;
  assign dma_adc_data_s[2] = dma_adc_2_data;
  assign dma_adc_enable_s[3] = dma_adc_3_enable;
  assign dma_adc_valid_s[3] = dma_adc_3_valid;
  assign dma_adc_data_s[3] = dma_adc_3_data;

endmodule
module prcfg_top(

  clk,


  dac_gpio_input,
  dac_gpio_output,
  adc_gpio_input,
  adc_gpio_output,


  dma_dac_0_enable,
  dma_dac_0_data,
  dma_dac_0_valid,
  dma_dac_1_enable,
  dma_dac_1_data,
  dma_dac_1_valid,
  dma_dac_2_enable,
  dma_dac_2_data,
  dma_dac_2_valid,
  dma_dac_3_enable,
  dma_dac_3_data,
  dma_dac_3_valid,

  core_dac_0_enable,
  core_dac_0_data,
  core_dac_0_valid,
  core_dac_1_enable,
  core_dac_1_data,
  core_dac_1_valid,
  core_dac_2_enable,
  core_dac_2_data,
  core_dac_2_valid,
  core_dac_3_enable,
  core_dac_3_data,
  core_dac_3_valid,


  dma_adc_0_enable,
  dma_adc_0_data,
  dma_adc_0_valid,
  dma_adc_1_enable,
  dma_adc_1_data,
  dma_adc_1_valid,
  dma_adc_2_enable,
  dma_adc_2_data,
  dma_adc_2_valid,
  dma_adc_3_enable,
  dma_adc_3_data,
  dma_adc_3_valid,

  core_adc_0_enable,
  core_adc_0_data,
  core_adc_0_valid,
  core_adc_1_enable,
  core_adc_1_data,
  core_adc_1_valid,
  core_adc_2_enable,
  core_adc_2_data,
  core_adc_2_valid,
  core_adc_3_enable,
  core_adc_3_data,
  core_adc_3_valid
);


  localparam  ENABELED    = 1;
  localparam  DATA_WIDTH  = 16;

  parameter   NUM_CHANNEL = 4;
  parameter   ADC_EN      = 1;
  parameter   DAC_EN      = 1;

  localparam  DBUS_WIDTH  = DATA_WIDTH * NUM_CHANNEL;

  input                             clk;

  input   [31:0]                    dac_gpio_input;
  output  [31:0]                    dac_gpio_output;
  input   [31:0]                    adc_gpio_input;
  output  [31:0]                    adc_gpio_output;

  input                             dma_dac_0_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_0_data;
  input                             dma_dac_0_valid;
  input                             dma_dac_1_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_1_data;
  input                             dma_dac_1_valid;
  input                             dma_dac_2_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_2_data;
  input                             dma_dac_2_valid;
  input                             dma_dac_3_enable;
  output  [(DBUS_WIDTH-1):0]        dma_dac_3_data;
  input                             dma_dac_3_valid;

  output                            core_dac_0_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_0_data;
  output                            core_dac_0_valid;
  output                            core_dac_1_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_1_data;
  output                            core_dac_1_valid;
  output                            core_dac_2_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_2_data;
  output                            core_dac_2_valid;
  output                            core_dac_3_enable;
  input   [(DBUS_WIDTH-1):0]        core_dac_3_data;
  output                            core_dac_3_valid;


  input                             dma_adc_0_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_0_data;
  input                             dma_adc_0_valid;
  input                             dma_adc_1_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_1_data;
  input                             dma_adc_1_valid;
  input                             dma_adc_2_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_2_data;
  input                             dma_adc_2_valid;
  input                             dma_adc_3_enable;
  input   [(DBUS_WIDTH-1):0]        dma_adc_3_data;
  input                             dma_adc_3_valid;

  output                            core_adc_0_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_0_data;
  output                            core_adc_0_valid;
  output                            core_adc_1_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_1_data;
  output                            core_adc_1_valid;
  output                            core_adc_2_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_2_data;
  output                            core_adc_2_valid;
  output                            core_adc_3_enable;
  output  [(DBUS_WIDTH-1):0]        core_adc_3_data;
  output                            core_adc_3_valid;

  wire    [31:0]                    adc_gpio_out_s[(NUM_CHANNEL - 1):0];
  wire    [(NUM_CHANNEL - 1):0]     adc_gpio_out_s_inv[31:0];

  wire    [31:0]                    dac_gpio_out_s[(NUM_CHANNEL - 1):0];
  wire    [(NUM_CHANNEL - 1):0]     dac_gpio_out_s_inv[31:0];

  wire    [(NUM_CHANNEL - 1):0]     core_adc_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     core_adc_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     core_adc_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_adc_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     core_dac_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     core_dac_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     core_dac_data_s[15:0];
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_enable_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_valid_s;
  wire    [(NUM_CHANNEL - 1):0]     dma_dac_data_s[15:0];

  genvar l_inst;

  generate
    for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
      if(ADC_EN == ENABELED) begin
          prcfg_adc #(
            .CHANNEL_ID(l_inst)
          ) i_prcfg_adc_i (
            .clk(clk),
            .control(adc_gpio_input),
            .status(adc_gpio_out_s[l_inst]),
            .src_adc_enable(core_adc_enable_s[l_inst]),
            .src_adc_valid(core_adc_valid_s[l_inst]),
            .src_adc_data(core_adc_data_s[l_inst]),
            .dst_adc_enable(dma_adc_enable_s[l_inst]),
            .dst_adc_valid(dma_adc_valid_s[l_inst]),
            .dst_adc_data(dma_adc_data_s[l_inst])
          );
      end
      if(DAC_EN == ENABELED) begin
        prcfg_dac #(
          .CHANNEL_ID(l_inst)
        ) i_prcfg_dac_i (
          .clk(clk),
          .control(dac_gpio_input),
          .status(dac_gpio_out_s[l_inst]),
          .src_dac_enable(dma_dac_enable_s[l_inst]),
          .src_dac_data(dma_dac_data_s[l_inst]),
          .src_dac_valid(dma_dac_valid_s[l_inst]),
          .dst_dac_enable(core_dac_enable_s[l_inst]),
          .dst_dac_data(core_dac_data_s[l_inst]),
          .dst_dac_valid(core_dac_valid_s[l_inst])
        );
      end
    end
  endgenerate

  genvar i;
  genvar j;

  generate
  for(i = 0; i < 32; i = i + 1) begin
    for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
      assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
      assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
    end
  end
  endgenerate


  generate
  for(i = 0; i < 32; i = i + 1) begin
    assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
    assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
  end
  endgenerate



  assign core_dac_0_enable = core_dac_enable_s[0];
  assign core_dac_0_valid = core_dac_valid_s[0];
  assign core_dac_data_s[0] = core_dac_0_data;
  assign core_dac_1_enable = core_dac_enable_s[1];
  assign core_dac_1_valid = core_dac_valid_s[1];
  assign core_dac_data_s[1] = core_dac_1_data;
  assign core_dac_2_enable = core_dac_enable_s[2];
  assign core_dac_2_valid = core_dac_valid_s[2];
  assign core_dac_data_s[2] = core_dac_2_data;
  assign core_dac_3_enable = core_dac_enable_s[3];
  assign core_dac_3_valid = core_dac_valid_s[3];
  assign core_dac_data_s[3] = core_dac_3_data;

  assign dma_dac_enable_s[0] = dma_dac_0_enable;
  assign dma_dac_valid_s[0] = dma_dac_0_valid;
  assign dma_dac_0_data = dma_dac_data_s[0];
  assign dma_dac_enable_s[1] = dma_dac_1_enable;
  assign dma_dac_valid_s[1] = dma_dac_1_valid;
  assign dma_dac_1_data = dma_dac_data_s[1];
  assign dma_dac_enable_s[2] = dma_dac_2_enable;
  assign dma_dac_valid_s[2] = dma_dac_2_valid;
  assign dma_dac_2_data = dma_dac_data_s[2];
  assign dma_dac_enable_s[3] = dma_dac_3_enable;
  assign dma_dac_valid_s[3] = dma_dac_3_valid;
  assign dma_dac_3_data = dma_dac_data_s[3];

  assign core_adc_0_enable = core_adc_enable_s[0];
  assign core_adc_0_valid = core_adc_valid_s[0];
  assign core_adc_0_data = core_adc_data_s[0];
  assign core_adc_1_enable = core_adc_enable_s[1];
  assign core_adc_1_valid = core_adc_valid_s[1];
  assign core_adc_1_data = core_adc_data_s[1];
  assign core_adc_2_enable = core_adc_enable_s[2];
  assign core_adc_2_valid = core_adc_valid_s[2];
  assign core_adc_2_data = core_adc_data_s[2];
  assign core_adc_3_enable = core_adc_enable_s[3];
  assign core_adc_3_valid = core_adc_valid_s[3];
  assign core_adc_3_data = core_adc_data_s[3];

  assign dma_adc_enable_s[0] = dma_adc_0_enable;
  assign dma_adc_valid_s[0] = dma_adc_0_valid;
  assign dma_adc_data_s[0] = dma_adc_0_data;
  assign dma_adc_enable_s[1] = dma_adc_1_enable;
  assign dma_adc_valid_s[1] = dma_adc_1_valid;
  assign dma_adc_data_s[1] = dma_adc_1_data;
  assign dma_adc_enable_s[2] = dma_adc_2_enable;
  assign dma_adc_valid_s[2] = dma_adc_2_valid;
  assign dma_adc_data_s[2] = dma_adc_2_data;
  assign dma_adc_enable_s[3] = dma_adc_3_enable;
  assign dma_adc_valid_s[3] = dma_adc_3_valid;
  assign dma_adc_data_s[3] = dma_adc_3_data;

endmodule