data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:52: Define or directive not defined: \'`A_FROM_REG_SOURCE\'\n  `A_FROM_REG_SOURCE:\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:52: syntax error, unexpected \':\', expecting endcase\n  `A_FROM_REG_SOURCE:\n                    ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:54: Define or directive not defined: \'`A_FROM_IMM10_6\'\n  `A_FROM_IMM10_6:   \n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:56: Define or directive not defined: \'`A_FROM_PC\'\n  `A_FROM_PC:        \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:63: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n  `B_FROM_REG_TARGET:\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:65: Define or directive not defined: \'`B_FROM_IMM\'\n  `B_FROM_IMM:       \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:67: Define or directive not defined: \'`B_FROM_SIGNED_IMM\'\n  `B_FROM_SIGNED_IMM:\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:69: Define or directive not defined: \'`B_FROM_IMMX4\'\n  `B_FROM_IMMX4:     \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:76: Define or directive not defined: \'`C_FROM_NULL\'\n  `C_FROM_NULL:       \n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:78: Define or directive not defined: \'`C_FROM_ALU\'\n  `C_FROM_ALU:        \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:80: Define or directive not defined: \'`C_FROM_SHIFT\'\n  `C_FROM_SHIFT:      \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:82: Define or directive not defined: \'`C_FROM_MULT\'\n  `C_FROM_MULT:       \n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:84: Define or directive not defined: \'`C_FROM_MEMORY\'\n  `C_FROM_MEMORY:     \n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:86: Define or directive not defined: \'`C_FROM_PC\'\n  `C_FROM_PC:         \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:88: Define or directive not defined: \'`C_FROM_PC_PLUS4\'\n  `C_FROM_PC_PLUS4:   \n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:90: Define or directive not defined: \'`C_FROM_IMM_SHIFT16\'\n  `C_FROM_IMM_SHIFT16:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:92: Define or directive not defined: \'`C_FROM_REG_SOURCEN\'\n  `C_FROM_REG_SOURCEN:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:99: Define or directive not defined: \'`BRANCH_LTZ\'\n  `BRANCH_LTZ:\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:101: Define or directive not defined: \'`BRANCH_LEZ\'\n  `BRANCH_LEZ:\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:103: Define or directive not defined: \'`BRANCH_EQ\'\n  `BRANCH_EQ:\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:105: Define or directive not defined: \'`BRANCH_NE\'\n  `BRANCH_NE: \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:107: Define or directive not defined: \'`BRANCH_GEZ\'\n  `BRANCH_GEZ:\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:109: Define or directive not defined: \'`BRANCH_GTZ\'\n  `BRANCH_GTZ:\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:111: Define or directive not defined: \'`BRANCH_YES\'\n  `BRANCH_YES:\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Bus_Mux.v:113: Define or directive not defined: \'`BRANCH_NO\'\n  `BRANCH_NO: \n  ^~~~~~~~~~\n%Error: Cannot continue\n'
module Bus_Mux
(
	imm_in,
	reg_source,
	a_mux,
	a_out,
	reg_target,
	b_mux,
	b_out,
	c_bus,
	c_memory,
	c_pc,
	c_pc_plus4,
	c_mux,
	reg_dest_out,
	branch_func,
	take_branch
);

	input 	[15:0] 	imm_in;
	input 	[31:0]	reg_source;
	input   [1:0]	a_mux;
	output 	[31:0]	a_out;
	reg 	[31:0]	a_out;

	input 	[31:0]	reg_target;
	input   [1:0]	b_mux;
	output 	[31:0]	b_out;
	reg 	[31:0]	b_out;

	input 	[31:0]	c_bus;
	input 	[31:0]	c_memory;
	input 	[31:2]	c_pc;
	input 	[31:2] 	c_pc_plus4;
	input 	[2:0] 	c_mux;
	output 	[31:0] 	reg_dest_out;
	reg 	[31:0] 	reg_dest_out;

	input 	[2:0]   branch_func;
	output   		take_branch;
	reg 			take_branch;
   
	always@(*)
	begin
		a_out<=32'b0;
		b_out<=32'b0;
		reg_dest_out<=32'b0;
		take_branch<=0;
		case(a_mux)
		`A_FROM_REG_SOURCE:
			a_out<=reg_source;
		`A_FROM_IMM10_6:   
			a_out<={27'b0,imm_in[10:6]};
		`A_FROM_PC:        
			a_out<={c_pc,2'b0};
		default:
			a_out<=32'b0;
		endcase
		
		case(b_mux)
		`B_FROM_REG_TARGET:
			b_out<=reg_target;
		`B_FROM_IMM:       
			b_out<={16'b0,imm_in};
		`B_FROM_SIGNED_IMM:
			b_out<={{16{imm_in[15]}},imm_in};
		`B_FROM_IMMX4:     
			b_out<={14'b0,imm_in,2'b0};
		default:
			b_out<=32'b0;
		endcase
		
		case(c_mux)
		`C_FROM_NULL:       
			reg_dest_out<=32'b0;
		`C_FROM_ALU:        
			reg_dest_out<=c_bus;
		`C_FROM_SHIFT:      
			reg_dest_out<=c_bus;
		`C_FROM_MULT:       
			reg_dest_out<=c_bus;
		`C_FROM_MEMORY:     
			reg_dest_out<=c_memory;
		`C_FROM_PC:         
			reg_dest_out<={c_pc,2'b0};
		`C_FROM_PC_PLUS4:   
			reg_dest_out<={c_pc_plus4,2'b0};
		`C_FROM_IMM_SHIFT16:
			reg_dest_out<={imm_in,16'b0};
		`C_FROM_REG_SOURCEN:
			reg_dest_out<=reg_source;
		default:
			reg_dest_out<=32'b0;
		endcase
		
		case(branch_func)
		`BRANCH_LTZ:
			take_branch<=(c_bus[31])?1:0;
		`BRANCH_LEZ:
			take_branch<=(c_bus[31])?1:(c_bus==32'b0)?1:0;
		`BRANCH_EQ:
			take_branch<=(c_bus==32'b0)?1:0;
		`BRANCH_NE: 
			take_branch<=(c_bus==32'b0)?0:1;
		`BRANCH_GEZ:
			take_branch<=(c_bus[31])?0:1;
		`BRANCH_GTZ:
			take_branch<=(c_bus[31])?0:(c_bus==32'b0)?0:1;
		`BRANCH_YES:
			take_branch<=1;
		`BRANCH_NO: 
			take_branch<=0;
		default:
			take_branch<=0;
		endcase
	end
endmodule
module Bus_Mux
(
	imm_in,
	reg_source,
	a_mux,
	a_out,
	reg_target,
	b_mux,
	b_out,
	c_bus,
	c_memory,
	c_pc,
	c_pc_plus4,
	c_mux,
	reg_dest_out,
	branch_func,
	take_branch
);


	input 	[15:0] 	imm_in;
	input 	[31:0]	reg_source;
	input   [1:0]	a_mux;
	output 	[31:0]	a_out;
	reg 	[31:0]	a_out;

	input 	[31:0]	reg_target;
	input   [1:0]	b_mux;
	output 	[31:0]	b_out;
	reg 	[31:0]	b_out;

	input 	[31:0]	c_bus;
	input 	[31:0]	c_memory;
	input 	[31:2]	c_pc;
	input 	[31:2] 	c_pc_plus4;
	input 	[2:0] 	c_mux;
	output 	[31:0] 	reg_dest_out;
	reg 	[31:0] 	reg_dest_out;

	input 	[2:0]   branch_func;
	output   		take_branch;
	reg 			take_branch;
   
	always@(*)
	begin
		a_out<=32'b0;
		b_out<=32'b0;
		reg_dest_out<=32'b0;
		take_branch<=0;
		case(a_mux)
		`A_FROM_REG_SOURCE:
			a_out<=reg_source;
		`A_FROM_IMM10_6:   
			a_out<={27'b0,imm_in[10:6]};
		`A_FROM_PC:        
			a_out<={c_pc,2'b0};
		default:
			a_out<=32'b0;
		endcase
		
		case(b_mux)
		`B_FROM_REG_TARGET:
			b_out<=reg_target;
		`B_FROM_IMM:       
			b_out<={16'b0,imm_in};
		`B_FROM_SIGNED_IMM:
			b_out<={{16{imm_in[15]}},imm_in};
		`B_FROM_IMMX4:     
			b_out<={14'b0,imm_in,2'b0};
		default:
			b_out<=32'b0;
		endcase
		
		case(c_mux)
		`C_FROM_NULL:       
			reg_dest_out<=32'b0;
		`C_FROM_ALU:        
			reg_dest_out<=c_bus;
		`C_FROM_SHIFT:      
			reg_dest_out<=c_bus;
		`C_FROM_MULT:       
			reg_dest_out<=c_bus;
		`C_FROM_MEMORY:     
			reg_dest_out<=c_memory;
		`C_FROM_PC:         
			reg_dest_out<={c_pc,2'b0};
		`C_FROM_PC_PLUS4:   
			reg_dest_out<={c_pc_plus4,2'b0};
		`C_FROM_IMM_SHIFT16:
			reg_dest_out<={imm_in,16'b0};
		`C_FROM_REG_SOURCEN:
			reg_dest_out<=reg_source;
		default:
			reg_dest_out<=32'b0;
		endcase
		
		case(branch_func)
		`BRANCH_LTZ:
			take_branch<=(c_bus[31])?1:0;
		`BRANCH_LEZ:
			take_branch<=(c_bus[31])?1:(c_bus==32'b0)?1:0;
		`BRANCH_EQ:
			take_branch<=(c_bus==32'b0)?1:0;
		`BRANCH_NE: 
			take_branch<=(c_bus==32'b0)?0:1;
		`BRANCH_GEZ:
			take_branch<=(c_bus[31])?0:1;
		`BRANCH_GTZ:
			take_branch<=(c_bus[31])?0:(c_bus==32'b0)?0:1;
		`BRANCH_YES:
			take_branch<=1;
		`BRANCH_NO: 
			take_branch<=0;
		default:
			take_branch<=0;
		endcase
	end
endmodule