data/full_repos/permissive/443556793/lab_4/rtl/maindec.v
1: b'%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:22: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh.v\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:49: Define or directive not defined: \'`EXE_SPECIAL_INST\'\n        `EXE_SPECIAL_INST:\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:49: syntax error, unexpected \':\', expecting endcase\n        `EXE_SPECIAL_INST:\n                         ^\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:52: Define or directive not defined: \'`EXE_MFHI\'\n                `EXE_MFHI:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:54: Define or directive not defined: \'`EXE_MFLO\'\n                `EXE_MFLO:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:56: Define or directive not defined: \'`EXE_MTHI\'\n                `EXE_MTHI:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:58: Define or directive not defined: \'`EXE_MTLO\'\n                `EXE_MTLO:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:60: Define or directive not defined: \'`EXE_JR\'\n                `EXE_JR:\n                ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:62: Define or directive not defined: \'`EXE_JALR\'\n                `EXE_JALR:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:64: Define or directive not defined: \'`EXE_MULT\'\n                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:64: Define or directive not defined: \'`EXE_MULTU\'\n                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:64: Define or directive not defined: \'`EXE_DIV\'\n                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:64: Define or directive not defined: \'`EXE_DIVU\'\n                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:70: Define or directive not defined: \'`EXE_LB\'\n        `EXE_LB:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:72: Define or directive not defined: \'`EXE_LBU\'\n        `EXE_LBU:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:74: Define or directive not defined: \'`EXE_LH\'\n        `EXE_LH:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:76: Define or directive not defined: \'`EXE_LHU\'\n        `EXE_LHU:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:78: Define or directive not defined: \'`EXE_LW\'\n        `EXE_LW:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:80: Define or directive not defined: \'`EXE_SB\'\n        `EXE_SB:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:82: Define or directive not defined: \'`EXE_SH\'\n        `EXE_SH:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:84: Define or directive not defined: \'`EXE_SW\'\n        `EXE_SW:\n        ^~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:86: Define or directive not defined: \'`EXE_BEQ\'\n        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:86: Define or directive not defined: \'`EXE_BNE\'\n        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:86: Define or directive not defined: \'`EXE_BGTZ\'\n        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:86: Define or directive not defined: \'`EXE_BLEZ\'\n        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:88: Define or directive not defined: \'`EXE_ADDI\'\n        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:88: Define or directive not defined: \'`EXE_ADDIU\'\n        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:88: Define or directive not defined: \'`EXE_SLTI\'\n        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:88: Define or directive not defined: \'`EXE_SLTIU\'\n        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:90: Define or directive not defined: \'`EXE_ORI\'\n        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:90: Define or directive not defined: \'`EXE_ANDI\'\n        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:90: Define or directive not defined: \'`EXE_XORI\'\n        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:90: Define or directive not defined: \'`EXE_LUI\'\n        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:92: Define or directive not defined: \'`EXE_J\'\n        `EXE_J:\n        ^~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:94: Define or directive not defined: \'`EXE_JAL\'\n        `EXE_JAL:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:96: Define or directive not defined: \'`EXE_REGIMM_INST\'\n        `EXE_REGIMM_INST:\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:99: Define or directive not defined: \'`EXE_BLTZ\'\n                `EXE_BLTZ:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:101: Define or directive not defined: \'`EXE_BLTZAL\'\n                `EXE_BLTZAL:\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:103: Define or directive not defined: \'`EXE_BGEZ\'\n                `EXE_BGEZ:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/maindec.v:105: Define or directive not defined: \'`EXE_BGEZAL\'\n                `EXE_BGEZAL:\n                ^~~~~~~~~~~\n%Error: Cannot continue\n'
module maindec(
           input wire[5:0] op,
           input wire[5:0] funct,
           input wire[4:0] rt,
           output wire memtoreg,
           output wire[3:0] memwrite,
           output wire branch,alusrc,
           output wire regdst,regwrite,
           output wire jump,
           output wire[2:0] lshb,
           output wire jr,
           output wire jal,
           output wire pceight,
           output wire sign,
           output wire hilowrite,
           output wire hilotoreg,
           output wire hiloalu,
           output wire hiloread
       );
reg[20:0] controls;
assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,lshb,jr,jal,pceight,sign,hilowrite,hilotoreg,hiloalu,hiloread} = controls;
always @(*)
begin
    case (op)
        6'b111111:
            controls <= 21'b1100_0000_0010_0000_1000_0;
        `EXE_SPECIAL_INST:
        begin
            case (funct)
                `EXE_MFHI:
                    controls <= 21'b1100_0000_0010_0000_0010_1;
                `EXE_MFLO:
                    controls <= 21'b1100_0000_1010_0000_0010_1;
                `EXE_MTHI:
                    controls <= 21'b0000_0000_0010_0000_0100_0;
                `EXE_MTLO:
                    controls <= 21'b0000_0000_0010_0000_0100_0;
                `EXE_JR:
                    controls <= 21'b0000_0000_0010_0100_1000_0;
                `EXE_JALR:
                    controls <= 21'b1000_0000_0010_0111_1000_0;
                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:
                    controls <= 21'b1100_0000_0010_0000_1101_0;
                default:
                    controls <= 21'b1100_0000_0010_0000_1000_0;
            endcase
        end
        `EXE_LB:
            controls <= 21'b1010_0000_1000_0000_1000_0;
        `EXE_LBU:
            controls <= 21'b1010_0000_1000_1000_1000_0;
        `EXE_LH:
            controls <= 21'b1010_0000_1001_0000_1000_0;
        `EXE_LHU:
            controls <= 21'b1010_0000_1001_1000_1000_0;
        `EXE_LW:
            controls <= 21'b1010_0000_1010_0000_1000_0;
        `EXE_SB:
            controls <= 21'b0010_1111_0010_1000_1000_0;
        `EXE_SH:
            controls <= 21'b0010_1111_0011_0000_1000_0;
        `EXE_SW:
            controls <= 21'b0010_1111_0011_1000_1000_0;
        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:
            controls <= 21'b0001_0000_0010_0000_1000_0;
        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:
            controls <= 21'b1010_0000_0010_0000_1000_0;
        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:
            controls <= 21'b1010_0000_0010_0000_0000_0;
        `EXE_J:
            controls <= 21'b0000_0000_0110_0000_1000_0;
        `EXE_JAL:
            controls <= 21'b1000_0000_0110_0011_1000_0;
        `EXE_REGIMM_INST:
        begin
            case (rt)
                `EXE_BLTZ:
                    controls <= 21'b0001_0000_0010_0000_1000_0;
                `EXE_BLTZAL:
                    controls <= 21'b1001_0000_0010_0011_1000_0;
                `EXE_BGEZ:
                    controls <= 21'b0001_0000_0010_0000_1000_0;
                `EXE_BGEZAL:
                    controls <= 21'b1001_0000_0010_0011_1000_0;
            endcase
        end
        default:
            controls <= 21'b0000_0000_0010_0000_1000_0;
    endcase
end
endmodule
module maindec(
           input wire[5:0] op,
           input wire[5:0] funct,
           input wire[4:0] rt,
           output wire memtoreg,
           output wire[3:0] memwrite,
           output wire branch,alusrc,
           output wire regdst,regwrite,
           output wire jump,
           output wire[2:0] lshb,
           output wire jr,
           output wire jal,
           output wire pceight,
           output wire sign,
           output wire hilowrite,
           output wire hilotoreg,
           output wire hiloalu,
           output wire hiloread
       );

reg[20:0] controls;
assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,lshb,jr,jal,pceight,sign,hilowrite,hilotoreg,hiloalu,hiloread} = controls;
always @(*)
begin
    case (op)
        6'b111111:
            controls <= 21'b1100_0000_0010_0000_1000_0;
        `EXE_SPECIAL_INST:
        begin
            case (funct)
                `EXE_MFHI:
                    controls <= 21'b1100_0000_0010_0000_0010_1;
                `EXE_MFLO:
                    controls <= 21'b1100_0000_1010_0000_0010_1;
                `EXE_MTHI:
                    controls <= 21'b0000_0000_0010_0000_0100_0;
                `EXE_MTLO:
                    controls <= 21'b0000_0000_0010_0000_0100_0;
                `EXE_JR:
                    controls <= 21'b0000_0000_0010_0100_1000_0;
                `EXE_JALR:
                    controls <= 21'b1000_0000_0010_0111_1000_0;
                `EXE_MULT,`EXE_MULTU,`EXE_DIV,`EXE_DIVU:
                    controls <= 21'b1100_0000_0010_0000_1101_0;
                default:
                    controls <= 21'b1100_0000_0010_0000_1000_0;
            endcase
        end
        `EXE_LB:
            controls <= 21'b1010_0000_1000_0000_1000_0;
        `EXE_LBU:
            controls <= 21'b1010_0000_1000_1000_1000_0;
        `EXE_LH:
            controls <= 21'b1010_0000_1001_0000_1000_0;
        `EXE_LHU:
            controls <= 21'b1010_0000_1001_1000_1000_0;
        `EXE_LW:
            controls <= 21'b1010_0000_1010_0000_1000_0;
        `EXE_SB:
            controls <= 21'b0010_1111_0010_1000_1000_0;
        `EXE_SH:
            controls <= 21'b0010_1111_0011_0000_1000_0;
        `EXE_SW:
            controls <= 21'b0010_1111_0011_1000_1000_0;
        `EXE_BEQ,`EXE_BNE,`EXE_BGTZ,`EXE_BLEZ:
            controls <= 21'b0001_0000_0010_0000_1000_0;
        `EXE_ADDI,`EXE_ADDIU,`EXE_SLTI,`EXE_SLTIU:
            controls <= 21'b1010_0000_0010_0000_1000_0;
        `EXE_ORI,`EXE_ANDI,`EXE_XORI,`EXE_LUI:
            controls <= 21'b1010_0000_0010_0000_0000_0;
        `EXE_J:
            controls <= 21'b0000_0000_0110_0000_1000_0;
        `EXE_JAL:
            controls <= 21'b1000_0000_0110_0011_1000_0;
        `EXE_REGIMM_INST:
        begin
            case (rt)
                `EXE_BLTZ:
                    controls <= 21'b0001_0000_0010_0000_1000_0;
                `EXE_BLTZAL:
                    controls <= 21'b1001_0000_0010_0011_1000_0;
                `EXE_BGEZ:
                    controls <= 21'b0001_0000_0010_0000_1000_0;
                `EXE_BGEZAL:
                    controls <= 21'b1001_0000_0010_0011_1000_0;
            endcase
        end
        default:
            controls <= 21'b0000_0000_0010_0000_1000_0;
    endcase
end
endmodule