data/full_repos/permissive/446997925/hw4/alu_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/alu_testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw4/alu_testbench.v:66: Unsupported or unknown PLI call: $monitor\n$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b, zero=%1b", $time, a, b, sel, out, zero);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_testbench();

reg [31:0] a, b;
reg [2:0] sel;
wire [31:0] out;
wire zero;

ALU_3_bit_op alu_test( zero,out[31:0],a [31:0],b [31:0],sel);

initial begin

a = 32'd2;
b = 32'd6;
sel = 3'b001;
#`DELAY;

a = 32'd2147483647;
b = 32'd2147483647;
sel = 3'b001;
#`DELAY;

a = 32'd15;
b = 32'd3;
sel = 3'b010;
#`DELAY;

a = 32'd0;
b = 32'd2147483647;
sel = 3'b010;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b000;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b101;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b011;
#`DELAY;

a = 32'd2;
b = 32'd2;
sel = 3'b010;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b100;

#`DELAY;
a = 32'd9;
b = 32'd8;
sel = 3'b110;
#`DELAY;
end

initial
begin
$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b, zero=%1b", $time, a, b, sel, out, zero);
end


endmodule
module alu_testbench();


reg [31:0] a, b;
reg [2:0] sel;
wire [31:0] out;
wire zero;

ALU_3_bit_op alu_test( zero,out[31:0],a [31:0],b [31:0],sel);

initial begin

a = 32'd2;
b = 32'd6;
sel = 3'b001;
#`DELAY;

a = 32'd2147483647;
b = 32'd2147483647;
sel = 3'b001;
#`DELAY;

a = 32'd15;
b = 32'd3;
sel = 3'b010;
#`DELAY;

a = 32'd0;
b = 32'd2147483647;
sel = 3'b010;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b000;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b101;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b011;
#`DELAY;

a = 32'd2;
b = 32'd2;
sel = 3'b010;
#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 3'b100;

#`DELAY;
a = 32'd9;
b = 32'd8;
sel = 3'b110;
#`DELAY;
end

initial
begin
$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b, zero=%1b", $time, a, b, sel, out, zero);
end


endmodule