data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v
1: b'%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:40: Cannot find include file: openGFX430_defines.v\n`include "openGFX430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.sv\n             openGFX430_defines.v\n             openGFX430_defines.v.v\n             openGFX430_defines.v.sv\n             obj_dir/openGFX430_defines.v\n             obj_dir/openGFX430_defines.v.v\n             obj_dir/openGFX430_defines.v.sv\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:151: Cannot find include file: openGFX430_undefines.v\n`include "openGFX430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:68: Define or directive not defined: \'`APIX_MSB\'\noutput   [`APIX_MSB:0] vid_ram_addr_nxt_o;     \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:68: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput   [`APIX_MSB:0] vid_ram_addr_nxt_o;     \n                   ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:74: Define or directive not defined: \'`LPIX_MSB\'\ninput    [`LPIX_MSB:0] display_width_i;        \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:74: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput    [`LPIX_MSB:0] display_width_i;        \n                   ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:80: Define or directive not defined: \'`APIX_MSB\'\ninput    [`APIX_MSB:0] vid_ram_addr_i;         \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:80: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput    [`APIX_MSB:0] vid_ram_addr_i;         \n                   ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:83: Define or directive not defined: \'`LPIX_MSB\'\ninput    [`LPIX_MSB:0] vid_ram_width_i;        \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:83: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput    [`LPIX_MSB:0] vid_ram_width_i;        \n                   ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:92: Define or directive not defined: \'`APIX_MSB\'\nreg    [`APIX_MSB:0] vid_ram_line_addr;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:92: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg    [`APIX_MSB:0] vid_ram_line_addr;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:93: Define or directive not defined: \'`LPIX_MSB\'\nreg    [`LPIX_MSB:0] vid_ram_column_count;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:93: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg    [`LPIX_MSB:0] vid_ram_column_count;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:96: Define or directive not defined: \'`LPIX_MSB\'\nwire                 vid_ram_line_done    = vid_ram_addr_step_i & (vid_ram_column_count==(vid_ram_width_i-{{`LPIX_MSB{1\'b0}}, 1\'b1}));\n                                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:99: Define or directive not defined: \'`LPIX_MSB\'\nwire   [`LPIX_MSB:0] vid_ram_length_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:99: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`LPIX_MSB:0] vid_ram_length_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:102: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4\'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:102: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4\'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:102: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4\'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |\n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:102: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4\'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |\n                                                                                                                      ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:103: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3\'b000,  vid_ram_length_mux[`LPIX_MSB:0], 1\'b0   } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:103: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3\'b000,  vid_ram_length_mux[`LPIX_MSB:0], 1\'b0   } |\n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:104: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2\'b00,   vid_ram_length_mux[`LPIX_MSB:0], 2\'b00  } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:104: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2\'b00,   vid_ram_length_mux[`LPIX_MSB:0], 2\'b00  } |\n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:105: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1\'b0,    vid_ram_length_mux[`LPIX_MSB:0], 3\'b000 } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:105: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1\'b0,    vid_ram_length_mux[`LPIX_MSB:0], 3\'b000 } |\n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:106: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_16_bpp_i}} & {         vid_ram_length_mux[`LPIX_MSB:0], 4\'b0000} ;\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:106: Define or directive not defined: \'`LPIX_MSB\'\n                                             {`LPIX_MSB+5{gfx_mode_16_bpp_i}} & {         vid_ram_length_mux[`LPIX_MSB:0], 4\'b0000} ;\n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:108: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4\'b0000, {{`VRAM_MSB{1\'b0}}, 1\'b1}               } |\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:108: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4\'b0000, {{`VRAM_MSB{1\'b0}}, 1\'b1}               } |\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:108: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4\'b0000, {{`VRAM_MSB{1\'b0}}, 1\'b1}               } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:108: Define or directive not defined: \'`VRAM_MSB\'\nwire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4\'b0000, {{`VRAM_MSB{1\'b0}}, 1\'b1}               } |\n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:109: Define or directive not defined: \'`APIX_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3\'b000,  {{`VRAM_MSB{1\'b0}}, 1\'b1},       1\'b0   } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:109: Define or directive not defined: \'`VRAM_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3\'b000,  {{`VRAM_MSB{1\'b0}}, 1\'b1},       1\'b0   } |\n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:110: Define or directive not defined: \'`APIX_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2\'b00,   {{`VRAM_MSB{1\'b0}}, 1\'b1},       2\'b00  } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:110: Define or directive not defined: \'`VRAM_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2\'b00,   {{`VRAM_MSB{1\'b0}}, 1\'b1},       2\'b00  } |\n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:111: Define or directive not defined: \'`APIX_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1\'b0,    {{`VRAM_MSB{1\'b0}}, 1\'b1},       3\'b000 } |\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:111: Define or directive not defined: \'`VRAM_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1\'b0,    {{`VRAM_MSB{1\'b0}}, 1\'b1},       3\'b000 } |\n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:112: Define or directive not defined: \'`APIX_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_16_bpp_i}} & {         {{`VRAM_MSB{1\'b0}}, 1\'b1},       4\'b0000} ;\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:112: Define or directive not defined: \'`VRAM_MSB\'\n                                             {`APIX_MSB+1{gfx_mode_16_bpp_i}} & {         {{`VRAM_MSB{1\'b0}}, 1\'b1},       4\'b0000} ;\n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:115: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1\'b0}}, vid_ram_length_align};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:115: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1\'b0}}, vid_ram_length_align};\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:115: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1\'b0}}, vid_ram_length_align};\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:115: Define or directive not defined: \'`LPIX_MSB\'\nwire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1\'b0}}, vid_ram_length_align};\n                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:118: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] next_base_addr       =  (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i    :\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:118: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] next_base_addr       =  (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i    :\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:121: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] next_addr            =   next_base_addr\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:121: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] next_addr            =   next_base_addr\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_gpu_dma_addr.v:122: Define or directive not defined: \'`APIX_MSB\'\n                                            + (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1\'b0}})\n                                                                   ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module  ogfx_gpu_dma_addr (


    vid_ram_addr_nxt_o,


    mclk,
    puc_rst,
    display_width_i,
    gfx_mode_1_bpp_i,
    gfx_mode_2_bpp_i,
    gfx_mode_4_bpp_i,
    gfx_mode_8_bpp_i,
    gfx_mode_16_bpp_i,
    vid_ram_addr_i,
    vid_ram_addr_init_i,
    vid_ram_addr_step_i,
    vid_ram_width_i,
    vid_ram_win_x_swap_i,
    vid_ram_win_y_swap_i,
    vid_ram_win_cl_swap_i
);



output   [`APIX_MSB:0] vid_ram_addr_nxt_o;



input                  mclk;
input                  puc_rst;
input    [`LPIX_MSB:0] display_width_i;
input                  gfx_mode_1_bpp_i;
input                  gfx_mode_2_bpp_i;
input                  gfx_mode_4_bpp_i;
input                  gfx_mode_8_bpp_i;
input                  gfx_mode_16_bpp_i;
input    [`APIX_MSB:0] vid_ram_addr_i;
input                  vid_ram_addr_init_i;
input                  vid_ram_addr_step_i;
input    [`LPIX_MSB:0] vid_ram_width_i;
input                  vid_ram_win_x_swap_i;
input                  vid_ram_win_y_swap_i;
input                  vid_ram_win_cl_swap_i;





reg    [`APIX_MSB:0] vid_ram_line_addr;
reg    [`LPIX_MSB:0] vid_ram_column_count;


wire                 vid_ram_line_done    = vid_ram_addr_step_i & (vid_ram_column_count==(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));


wire   [`LPIX_MSB:0] vid_ram_length_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;


wire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |
                                             {`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3'b000,  vid_ram_length_mux[`LPIX_MSB:0], 1'b0   } |
                                             {`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2'b00,   vid_ram_length_mux[`LPIX_MSB:0], 2'b00  } |
                                             {`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1'b0,    vid_ram_length_mux[`LPIX_MSB:0], 3'b000 } |
                                             {`LPIX_MSB+5{gfx_mode_16_bpp_i}} & {         vid_ram_length_mux[`LPIX_MSB:0], 4'b0000} ;

wire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1}               } |
                                             {`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3'b000,  {{`VRAM_MSB{1'b0}}, 1'b1},       1'b0   } |
                                             {`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2'b00,   {{`VRAM_MSB{1'b0}}, 1'b1},       2'b00  } |
                                             {`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1'b0,    {{`VRAM_MSB{1'b0}}, 1'b1},       3'b000 } |
                                             {`APIX_MSB+1{gfx_mode_16_bpp_i}} & {         {{`VRAM_MSB{1'b0}}, 1'b1},       4'b0000} ;


wire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1'b0}}, vid_ram_length_align};


wire   [`APIX_MSB:0] next_base_addr       =  (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i    :
                                                                                          vid_ram_line_addr ;

wire   [`APIX_MSB:0] next_addr            =   next_base_addr
                                            + (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            - (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            + (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            - (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});

wire                 update_line_addr     =   vid_ram_addr_init_i | vid_ram_line_done;
wire                 update_pixel_addr    =   update_line_addr    | vid_ram_addr_step_i;


always @(posedge mclk or posedge puc_rst)
  if (puc_rst)               vid_ram_line_addr  <=  {`APIX_MSB+1{1'b0}};
  else if (update_line_addr) vid_ram_line_addr  <=  next_addr;


assign vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;



always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_init_i)  vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_line_done)    vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_step_i)  vid_ram_column_count  <=  vid_ram_column_count + {{`LPIX_MSB{1'b0}}, 1'b1};


endmodule
module  ogfx_gpu_dma_addr (


    vid_ram_addr_nxt_o,


    mclk,
    puc_rst,
    display_width_i,
    gfx_mode_1_bpp_i,
    gfx_mode_2_bpp_i,
    gfx_mode_4_bpp_i,
    gfx_mode_8_bpp_i,
    gfx_mode_16_bpp_i,
    vid_ram_addr_i,
    vid_ram_addr_init_i,
    vid_ram_addr_step_i,
    vid_ram_width_i,
    vid_ram_win_x_swap_i,
    vid_ram_win_y_swap_i,
    vid_ram_win_cl_swap_i
);




output   [`APIX_MSB:0] vid_ram_addr_nxt_o;



input                  mclk;
input                  puc_rst;
input    [`LPIX_MSB:0] display_width_i;
input                  gfx_mode_1_bpp_i;
input                  gfx_mode_2_bpp_i;
input                  gfx_mode_4_bpp_i;
input                  gfx_mode_8_bpp_i;
input                  gfx_mode_16_bpp_i;
input    [`APIX_MSB:0] vid_ram_addr_i;
input                  vid_ram_addr_init_i;
input                  vid_ram_addr_step_i;
input    [`LPIX_MSB:0] vid_ram_width_i;
input                  vid_ram_win_x_swap_i;
input                  vid_ram_win_y_swap_i;
input                  vid_ram_win_cl_swap_i;





reg    [`APIX_MSB:0] vid_ram_line_addr;
reg    [`LPIX_MSB:0] vid_ram_column_count;


wire                 vid_ram_line_done    = vid_ram_addr_step_i & (vid_ram_column_count==(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));


wire   [`LPIX_MSB:0] vid_ram_length_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;


wire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |
                                             {`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3'b000,  vid_ram_length_mux[`LPIX_MSB:0], 1'b0   } |
                                             {`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2'b00,   vid_ram_length_mux[`LPIX_MSB:0], 2'b00  } |
                                             {`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1'b0,    vid_ram_length_mux[`LPIX_MSB:0], 3'b000 } |
                                             {`LPIX_MSB+5{gfx_mode_16_bpp_i}} & {         vid_ram_length_mux[`LPIX_MSB:0], 4'b0000} ;

wire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1}               } |
                                             {`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3'b000,  {{`VRAM_MSB{1'b0}}, 1'b1},       1'b0   } |
                                             {`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2'b00,   {{`VRAM_MSB{1'b0}}, 1'b1},       2'b00  } |
                                             {`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1'b0,    {{`VRAM_MSB{1'b0}}, 1'b1},       3'b000 } |
                                             {`APIX_MSB+1{gfx_mode_16_bpp_i}} & {         {{`VRAM_MSB{1'b0}}, 1'b1},       4'b0000} ;


wire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1'b0}}, vid_ram_length_align};


wire   [`APIX_MSB:0] next_base_addr       =  (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i    :
                                                                                          vid_ram_line_addr ;

wire   [`APIX_MSB:0] next_addr            =   next_base_addr
                                            + (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            - (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            + (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                            - (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});

wire                 update_line_addr     =   vid_ram_addr_init_i | vid_ram_line_done;
wire                 update_pixel_addr    =   update_line_addr    | vid_ram_addr_step_i;


always @(posedge mclk or posedge puc_rst)
  if (puc_rst)               vid_ram_line_addr  <=  {`APIX_MSB+1{1'b0}};
  else if (update_line_addr) vid_ram_line_addr  <=  next_addr;


assign vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;



always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_init_i)  vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_line_done)    vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_step_i)  vid_ram_column_count  <=  vid_ram_column_count + {{`LPIX_MSB{1'b0}}, 1'b1};


endmodule