data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/techmap_01.v
data/verilator_xmls/cc90293f-6480-4800-a245-96ff6705d012.xml
module test(input [31:0]  a, b,
            output [31:0] y);
assign y = a + b;
endmodule
module test(input [31:0]  a, b,
            output [31:0] y);

assign y = a + b;
endmodule