data/full_repos/permissive/481307378/source_files/TrafficLight/ctrl_ampel.v
1: b"%Error: data/full_repos/permissive/481307378/source_files/TrafficLight/ctrl_ampel.v:22: Cannot find file containing module: 'timer'\n    timer tmr(.RES(CNTR_RES), .CLK(CLK), .TICK(TICK));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/481307378/source_files/TrafficLight,data/full_repos/permissive/481307378/timer\n             data/full_repos/permissive/481307378/source_files/TrafficLight,data/full_repos/permissive/481307378/timer.v\n             data/full_repos/permissive/481307378/source_files/TrafficLight,data/full_repos/permissive/481307378/timer.sv\n             timer\n             timer.v\n             timer.sv\n             obj_dir/timer\n             obj_dir/timer.v\n             obj_dir/timer.sv\n%Error: Exiting due to 1 error(s)\n"
module ctrl_ampel(

    input RES,
    input CLK,
    input BTN,
    
    output CNTR_RES, 
    output [2 : 0] RGB
);
    

    parameter CLOCK_SIGNALS = 32'd500000000;
   
    
    reg [2 : 0] state;
    reg [2 : 0] rgb_val;
    reg  tmr_res;
    
    wire TICK;
    

    timer tmr(.RES(CNTR_RES), .CLK(CLK), .TICK(TICK));
    defparam tmr.CLOCK_SIGNALS = CLOCK_SIGNALS;
    

    always @(posedge CLK, posedge RES)
    begin
        if(RES == 1'b1) begin 
            state = 3'd1;
            tmr_res = 1'd1;  
         end       
        
        else begin 
        

                
            case(state)
            
                3'd1 : begin 
                if (BTN == 1'b1) begin
                    state = 3'd2;
                    tmr_res = 1'd1;
                    end   
                end
                
                3'd2 : begin 
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd3;
                    tmr_res = 1'd1;
                    end    
                end
                
                3'd3 : begin
                tmr_res = 1'd0; 
                if (TICK == 1'b1) begin
                    state = 3'd4;
                    tmr_res = 1'd1;
                    end               
                end
                
                3'd4 : begin
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd5;
                    tmr_res = 1'd1;
                    end          
                end
                
                3'd5 : begin
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd1;
                    tmr_res = 1'd1; 
                    end   
                end
                
                default : state = 3'd1;
               
            endcase 
             
        end
           
    end
    

    always @(state)
    begin
        case(state)
            3'd1 : rgb_val <= 3'b100;
            3'd2 : rgb_val <= 3'b100;
            3'd3 : rgb_val <= 3'b110;
            3'd4 : rgb_val <= 3'b010;
            3'd5 : rgb_val <= 3'b110;
            default : rgb_val <= 3'b100;
        endcase
    end
    
    assign RGB = rgb_val;
    assign CNTR_RES = tmr_res;
    
endmodule
module ctrl_ampel(

    input RES,
    input CLK,
    input BTN,
    
    output CNTR_RES, 
    output [2 : 0] RGB
);

    

    parameter CLOCK_SIGNALS = 32'd500000000;
   
    
    reg [2 : 0] state;
    reg [2 : 0] rgb_val;
    reg  tmr_res;
    
    wire TICK;
    

    timer tmr(.RES(CNTR_RES), .CLK(CLK), .TICK(TICK));
    defparam tmr.CLOCK_SIGNALS = CLOCK_SIGNALS;
    

    always @(posedge CLK, posedge RES)
    begin
        if(RES == 1'b1) begin 
            state = 3'd1;
            tmr_res = 1'd1;  
         end       
        
        else begin 
        

                
            case(state)
            
                3'd1 : begin 
                if (BTN == 1'b1) begin
                    state = 3'd2;
                    tmr_res = 1'd1;
                    end   
                end
                
                3'd2 : begin 
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd3;
                    tmr_res = 1'd1;
                    end    
                end
                
                3'd3 : begin
                tmr_res = 1'd0; 
                if (TICK == 1'b1) begin
                    state = 3'd4;
                    tmr_res = 1'd1;
                    end               
                end
                
                3'd4 : begin
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd5;
                    tmr_res = 1'd1;
                    end          
                end
                
                3'd5 : begin
                tmr_res = 1'd0;
                if (TICK == 1'b1) begin
                    state = 3'd1;
                    tmr_res = 1'd1; 
                    end   
                end
                
                default : state = 3'd1;
               
            endcase 
             
        end
           
    end
    

    always @(state)
    begin
        case(state)
            3'd1 : rgb_val <= 3'b100;
            3'd2 : rgb_val <= 3'b100;
            3'd3 : rgb_val <= 3'b110;
            3'd4 : rgb_val <= 3'b010;
            3'd5 : rgb_val <= 3'b110;
            default : rgb_val <= 3'b100;
        endcase
    end
    
    assign RGB = rgb_val;
    assign CNTR_RES = tmr_res;
    
endmodule