data/full_repos/permissive/510938582/rtl/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/510938582/rtl/alu.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bzzzz\' generates 4 bits.\n                                                                 : ... In instance alu\n  default: dout = 4\'bz;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu(alus,ac, bus, dout);
input[7:0] ac,bus;
input[3:0] alus;
output reg[7:0] dout;
always@(alus or ac or bus)
	case(alus)
		4'b0000:	dout = 8'b00000000;
		4'b0001:	dout = ac + bus;
		4'b0010:	dout = ac - bus;
		4'b0011:	dout = ac+ 8'b00000001;
		4'b0100:	dout = bus+8'b00000000;
		4'b0101:	dout = ac & bus;
		4'b0110:	dout = ac | bus;
		4'b0111:	dout = ~ac;
		4'b1000:	dout = (~ac & bus) | (ac & ~bus);
		4'b1001: dout = bus+8'b00000000;
		default: dout = 4'bz;
	endcase
endmodule
module alu(alus,ac, bus, dout);

input[7:0] ac,bus;
input[3:0] alus;
output reg[7:0] dout;
always@(alus or ac or bus)
	case(alus)
		4'b0000:	dout = 8'b00000000;
		4'b0001:	dout = ac + bus;
		4'b0010:	dout = ac - bus;
		4'b0011:	dout = ac+ 8'b00000001;
		4'b0100:	dout = bus+8'b00000000;
		4'b0101:	dout = ac & bus;
		4'b0110:	dout = ac | bus;
		4'b0111:	dout = ~ac;
		4'b1000:	dout = (~ac & bus) | (ac & ~bus);
		4'b1001: dout = bus+8'b00000000;
		default: dout = 4'bz;
	endcase
endmodule