data/full_repos/permissive/455421905/src/fifo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/455421905/src/fifo.v:57: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'ONE_ENTRY_FIFO\'\nmodule ONE_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'DFIFO\'\nmodule DFIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~\n                                                                     : ... Top module \'BS_FIFO\'\nmodule BS_FIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~~~\n                                                                     : ... Top module \'RAM_LAYER_FIFO\'\nmodule RAM_LAYER_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'MULTI_CHANNEL_TWOENTRY_FIFO\'\nmodule MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:375: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.sv\n             BRAM\n             BRAM.v\n             BRAM.sv\n             obj_dir/BRAM\n             obj_dir/BRAM.v\n             obj_dir/BRAM.sv\n%Error: data/full_repos/permissive/455421905/src/fifo.v:127: Cannot find file containing module: \'BRAM\'\n  BRAM #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:332: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module DFIFO #(parameter                    FIFO_SIZE  =  4,
               parameter                    FIFO_WIDTH = 32)
              (input  wire                  CLK,
               input  wire                  RST,
               input  wire                  enq,
               input  wire                  deq,
               input  wire [FIFO_WIDTH-1:0] din,
               output wire [FIFO_WIDTH-1:0] dot,
               output wire                  emp,
               output wire                  full,
               output reg  [FIFO_SIZE:0]    cnt);

  reg [FIFO_SIZE-1:0]  head, tail;
  reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];

  assign emp  = ~|cnt;
  assign full = cnt[FIFO_SIZE];
  assign dot  = mem[head];

  always @(posedge CLK) begin
    if (RST) {cnt, head, tail} <= 0;
    else begin
      case ({enq, deq})
        2'b01: begin head<=head+1;               cnt<=cnt-1; end
        2'b10: begin               tail<=tail+1; cnt<=cnt+1; end
        2'b11: begin head<=head+1; tail<=tail+1;             end
      endcase
    end
  end
  always @(posedge CLK) begin
    if (enq) mem[tail] <= din;
  end

endmodule
module DFIFO #(parameter                    FIFO_SIZE  =  4,
               parameter                    FIFO_WIDTH = 32)
              (input  wire                  CLK,
               input  wire                  RST,
               input  wire                  enq,
               input  wire                  deq,
               input  wire [FIFO_WIDTH-1:0] din,
               output wire [FIFO_WIDTH-1:0] dot,
               output wire                  emp,
               output wire                  full,
               output reg  [FIFO_SIZE:0]    cnt);


  reg [FIFO_SIZE-1:0]  head, tail;
  reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];

  assign emp  = ~|cnt;
  assign full = cnt[FIFO_SIZE];
  assign dot  = mem[head];

  always @(posedge CLK) begin
    if (RST) {cnt, head, tail} <= 0;
    else begin
      case ({enq, deq})
        2'b01: begin head<=head+1;               cnt<=cnt-1; end
        2'b10: begin               tail<=tail+1; cnt<=cnt+1; end
        2'b11: begin head<=head+1; tail<=tail+1;             end
      endcase
    end
  end
  always @(posedge CLK) begin
    if (enq) mem[tail] <= din;
  end

endmodule