data/full_repos/permissive/435516446/MIPS/cache_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/cache_TEST.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/cache_TEST.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #500 address <= 32\'b00000000000000000000000110101100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/cache_TEST.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/cache_TEST.v:37: Cannot find file containing module: \'cache\'\n cache uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/cache\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/cache.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/cache.sv\n             cache\n             cache.v\n             cache.sv\n             obj_dir/cache\n             obj_dir/cache.v\n             obj_dir/cache.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Cache_TEST;


	reg clock;
	reg [31:0] address;
	reg [127:0] data_line;


	wire hit;
	wire [31:0] instruction;


	cache uut (
		.clock(clock), 
		.address(address), 
		.data_line(data_line), 
		.hit(hit), 
		.instruction(instruction)
	);
	always #10 clock <= ~clock;

	initial begin

		clock = 0;
		address <= 32'b00000000000000000000000010000100;
		data_line <= {$random, $random, $random, $random};
	
		#500 address <= 32'b00000000000000000000000110101100;
		#1000 $finish;
        


	end
      
endmodule
module Cache_TEST;



	reg clock;
	reg [31:0] address;
	reg [127:0] data_line;


	wire hit;
	wire [31:0] instruction;


	cache uut (
		.clock(clock), 
		.address(address), 
		.data_line(data_line), 
		.hit(hit), 
		.instruction(instruction)
	);
	always #10 clock <= ~clock;

	initial begin

		clock = 0;
		address <= 32'b00000000000000000000000010000100;
		data_line <= {$random, $random, $random, $random};
	
		#500 address <= 32'b00000000000000000000000110101100;
		#1000 $finish;
        


	end
      
endmodule