data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2/test_sclk.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2/test_sclk.v:24: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2/test_sclk.v:29: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2/test_sclk.v:15: Cannot find file containing module: \'slowClock\'\n slowClock uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2,data/full_repos/permissive/448192472/slowClock\n             data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2,data/full_repos/permissive/448192472/slowClock.v\n             data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2,data/full_repos/permissive/448192472/slowClock.sv\n             slowClock\n             slowClock.v\n             slowClock.sv\n             obj_dir/slowClock\n             obj_dir/slowClock.v\n             obj_dir/slowClock.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_sclk;


	reg clk;


	wire sclk;


	slowClock uut (
		.clk(clk), 
		.sclk(sclk)
	);

	initial 
	begin

	clk = 0;
#1000;
$finish;

	end

always #10 clk = ~clk;
      
endmodule
module test_sclk;



	reg clk;


	wire sclk;


	slowClock uut (
		.clk(clk), 
		.sclk(sclk)
	);

	initial 
	begin

	clk = 0;
#1000;
$finish;

	end

always #10 clk = ~clk;
      
endmodule