data/full_repos/permissive/479253203/verilog/rtl/user_proj_cgra.v
1: b"%Error: data/full_repos/permissive/479253203/verilog/rtl/user_proj_cgra.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479253203/verilog/rtl/user_proj_cgra.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479253203/verilog/rtl/user_proj_cgra.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module user_proj_example #(
    parameter BITS = 32,
    parameter WISHBONE_BASE_ADDR = 32'h30000000
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);




    wire [31:0] CGRA_read_config_data;
    wire [31:0] CGRA_config_config_addr;
	wire [31:0] CGRA_config_config_data;
	wire        CGRA_config_read;
	wire        CGRA_config_write;
    wire  [3:0] CGRA_stall;
    wire  [1:0] message;

    wire sel = la_data_in[96];
    wire ckmux_clk;
    wire ckmux_rst;
    ckmux ckmux_u0 (
      .select  ( sel       )
    , .clk0    ( wb_clk_i  )
    , .clk1    ( io_in[34] )
    , .out_clk ( ckmux_clk )
    );
    assign ckmux_rst = (sel) ? io_in[35] : wb_rst_i;

    wishbone_ctl #(
        .WISHBONE_BASE_ADDR(WISHBONE_BASE_ADDR)
    ) wbs_ctl_u0 (

      .wb_clk_i  ( ckmux_clk  )
    , .wb_rst_i  ( ckmux_rst  )
    , .wbs_stb_i ( wbs_stb_i )
    , .wbs_cyc_i ( wbs_cyc_i )
    , .wbs_we_i  ( wbs_we_i  )
    , .wbs_sel_i ( wbs_sel_i )
    , .wbs_dat_i ( wbs_dat_i )
    , .wbs_adr_i ( wbs_adr_i )

    , .wbs_ack_o ( wbs_ack_o )
    , .wbs_dat_o ( wbs_dat_o )

    , .CGRA_read_config_data ( CGRA_read_config_data )

    , .CGRA_config_config_addr( CGRA_config_config_addr )
	, .CGRA_config_config_data( CGRA_config_config_data )
	, .CGRA_config_read       ( CGRA_config_read        )
	, .CGRA_config_write      ( CGRA_config_write       )
    , .CGRA_stall             ( CGRA_stall              )
    , .message                ( message                 )
);

assign io_out[36] = message[0];
assign io_out[37] = message[1];
assign io_out[34] = 1'b0;
assign io_out[35] = 1'b0; 




localparam P = 8;
wire [31:0] POHAN_BUF_CGRA_config_config_data [0:P-1];
wire [31:0] POHAN_BUF_CGRA_config_config_addr [0:P-1];
wire [3:0]  POHAN_BUF_CGRA_stall [0:P-1];
genvar i, j, k;
generate

    for (j=0; j<32; j=j+1) begin : BUF_STAGE_0_CONFIG_BIT

        sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_DATA (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_config_config_data[j]), 
            .X(POHAN_BUF_CGRA_config_config_data[0][j])
        );

        sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_ADDR (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_config_config_addr[j]), 
            .X(POHAN_BUF_CGRA_config_config_addr[0][j])
        );
    end
    for (k=0; k<4; k=k+1) begin : BUF_STAGE_0_STALL_BIT

        sky130_fd_sc_hd__buf_12 POHAN_BUF_STALL (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_stall[k]),
            .X(POHAN_BUF_CGRA_stall[0][k])
        );
    end

    for (i=0; i<(P-1); i=i+1) begin : BUF_STAGE
        for (j=0; j<32; j=j+1) begin : CONFIG_BIT

            sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_DATA (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_config_config_data[i][j]),
                .X(POHAN_BUF_CGRA_config_config_data[i+1][j])
            );
            sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_ADDR (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_config_config_addr[i][j]),
                .X(POHAN_BUF_CGRA_config_config_addr[i+1][j])
            );
        end
        for (k=0; k<4; k=k+1) begin : STALL_BIT

            sky130_fd_sc_hd__buf_12 POHAN_BUF_STALL (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_stall[i][k]),
                .X(POHAN_BUF_CGRA_stall[i+1][k])
            );
        end
    end
endgenerate






    wire [15:0] glb2io_16_X00_Y00 = io_in[15:0];
    wire [15:0] glb2io_16_X01_Y00 = io_in[32:17];
    wire        glb2io_1_X00_Y00  = io_in[16];
    wire        glb2io_1_X01_Y00  = io_in[33];
    wire [15:0] io2glb_16_X00_Y00;
    wire [15:0] io2glb_16_X01_Y00;
    wire        io2glb_1_X00_Y00;
    wire        io2glb_1_X01_Y00;

    assign io_out[15:0]  = io2glb_16_X00_Y00;
    assign io_out[32:17] = io2glb_16_X01_Y00;
    assign io_out[16]    = io2glb_1_X00_Y00;
    assign io_out[33]    = io2glb_1_X01_Y00;

    Interconnect Interconnect_inst0 (

        .clk                  ( ckmux_clk             ),
        .reset                ( ckmux_rst             ),
        .stall                ( POHAN_BUF_CGRA_stall[P-1]            ),
        .read_config_data     ( CGRA_read_config_data ),

        .config_0_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_0_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_0_read        ( CGRA_config_read        ),
        .config_0_write       ( CGRA_config_write       ),
        .config_1_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_1_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_1_read        ( CGRA_config_read        ),
        .config_1_write       ( CGRA_config_write       ),
        .config_2_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_2_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_2_read        ( CGRA_config_read        ),
        .config_2_write       ( CGRA_config_write       ),
        .config_3_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_3_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_3_read        ( CGRA_config_read        ),
        .config_3_write       ( CGRA_config_write       ),

        .glb2io_16_X00_Y00    ( glb2io_16_X00_Y00 ),
        .glb2io_16_X01_Y00    ( glb2io_16_X01_Y00 ),
        .glb2io_1_X00_Y00     ( glb2io_1_X00_Y00  ),
        .glb2io_1_X01_Y00     ( glb2io_1_X01_Y00  ),

        .io2glb_16_X00_Y00    ( io2glb_16_X00_Y00 ),
        .io2glb_16_X01_Y00    ( io2glb_16_X01_Y00 ),
        .io2glb_1_X00_Y00     ( io2glb_1_X00_Y00  ),
        .io2glb_1_X01_Y00     ( io2glb_1_X01_Y00  ),

        .glb2io_16_X02_Y00    ( 16'd0 ),
        .glb2io_16_X03_Y00    ( 16'd0 ),
        .glb2io_1_X02_Y00     ( 1'b0  ),
        .glb2io_1_X03_Y00     ( 1'b0  ),
        .io2glb_16_X02_Y00    (       ),
        .io2glb_16_X03_Y00    (       ),
        .io2glb_1_X02_Y00     (       ),
        .io2glb_1_X03_Y00     (       )
    );








    assign io_oeb = la_data_in[37:0];


    assign irq = 3'b000;
    assign la_data_out = 128'd0;

endmodule
module user_proj_example #(
    parameter BITS = 32,
    parameter WISHBONE_BASE_ADDR = 32'h30000000
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);





    wire [31:0] CGRA_read_config_data;
    wire [31:0] CGRA_config_config_addr;
	wire [31:0] CGRA_config_config_data;
	wire        CGRA_config_read;
	wire        CGRA_config_write;
    wire  [3:0] CGRA_stall;
    wire  [1:0] message;

    wire sel = la_data_in[96];
    wire ckmux_clk;
    wire ckmux_rst;
    ckmux ckmux_u0 (
      .select  ( sel       )
    , .clk0    ( wb_clk_i  )
    , .clk1    ( io_in[34] )
    , .out_clk ( ckmux_clk )
    );
    assign ckmux_rst = (sel) ? io_in[35] : wb_rst_i;

    wishbone_ctl #(
        .WISHBONE_BASE_ADDR(WISHBONE_BASE_ADDR)
    ) wbs_ctl_u0 (

      .wb_clk_i  ( ckmux_clk  )
    , .wb_rst_i  ( ckmux_rst  )
    , .wbs_stb_i ( wbs_stb_i )
    , .wbs_cyc_i ( wbs_cyc_i )
    , .wbs_we_i  ( wbs_we_i  )
    , .wbs_sel_i ( wbs_sel_i )
    , .wbs_dat_i ( wbs_dat_i )
    , .wbs_adr_i ( wbs_adr_i )

    , .wbs_ack_o ( wbs_ack_o )
    , .wbs_dat_o ( wbs_dat_o )

    , .CGRA_read_config_data ( CGRA_read_config_data )

    , .CGRA_config_config_addr( CGRA_config_config_addr )
	, .CGRA_config_config_data( CGRA_config_config_data )
	, .CGRA_config_read       ( CGRA_config_read        )
	, .CGRA_config_write      ( CGRA_config_write       )
    , .CGRA_stall             ( CGRA_stall              )
    , .message                ( message                 )
);

assign io_out[36] = message[0];
assign io_out[37] = message[1];
assign io_out[34] = 1'b0;
assign io_out[35] = 1'b0; 




localparam P = 8;
wire [31:0] POHAN_BUF_CGRA_config_config_data [0:P-1];
wire [31:0] POHAN_BUF_CGRA_config_config_addr [0:P-1];
wire [3:0]  POHAN_BUF_CGRA_stall [0:P-1];
genvar i, j, k;
generate

    for (j=0; j<32; j=j+1) begin : BUF_STAGE_0_CONFIG_BIT

        sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_DATA (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_config_config_data[j]), 
            .X(POHAN_BUF_CGRA_config_config_data[0][j])
        );

        sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_ADDR (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_config_config_addr[j]), 
            .X(POHAN_BUF_CGRA_config_config_addr[0][j])
        );
    end
    for (k=0; k<4; k=k+1) begin : BUF_STAGE_0_STALL_BIT

        sky130_fd_sc_hd__buf_12 POHAN_BUF_STALL (
        `ifdef USE_POWER_PINS
            .VPWR(vccd1),
            .VGND(vssd1),
        `endif
            .A(CGRA_stall[k]),
            .X(POHAN_BUF_CGRA_stall[0][k])
        );
    end

    for (i=0; i<(P-1); i=i+1) begin : BUF_STAGE
        for (j=0; j<32; j=j+1) begin : CONFIG_BIT

            sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_DATA (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_config_config_data[i][j]),
                .X(POHAN_BUF_CGRA_config_config_data[i+1][j])
            );
            sky130_fd_sc_hd__buf_12 POHAN_BUF_CONFIG_ADDR (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_config_config_addr[i][j]),
                .X(POHAN_BUF_CGRA_config_config_addr[i+1][j])
            );
        end
        for (k=0; k<4; k=k+1) begin : STALL_BIT

            sky130_fd_sc_hd__buf_12 POHAN_BUF_STALL (
            `ifdef USE_POWER_PINS
                .VPWR(vccd1),
                .VGND(vssd1),
            `endif
                .A(POHAN_BUF_CGRA_stall[i][k]),
                .X(POHAN_BUF_CGRA_stall[i+1][k])
            );
        end
    end
endgenerate






    wire [15:0] glb2io_16_X00_Y00 = io_in[15:0];
    wire [15:0] glb2io_16_X01_Y00 = io_in[32:17];
    wire        glb2io_1_X00_Y00  = io_in[16];
    wire        glb2io_1_X01_Y00  = io_in[33];
    wire [15:0] io2glb_16_X00_Y00;
    wire [15:0] io2glb_16_X01_Y00;
    wire        io2glb_1_X00_Y00;
    wire        io2glb_1_X01_Y00;

    assign io_out[15:0]  = io2glb_16_X00_Y00;
    assign io_out[32:17] = io2glb_16_X01_Y00;
    assign io_out[16]    = io2glb_1_X00_Y00;
    assign io_out[33]    = io2glb_1_X01_Y00;

    Interconnect Interconnect_inst0 (

        .clk                  ( ckmux_clk             ),
        .reset                ( ckmux_rst             ),
        .stall                ( POHAN_BUF_CGRA_stall[P-1]            ),
        .read_config_data     ( CGRA_read_config_data ),

        .config_0_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_0_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_0_read        ( CGRA_config_read        ),
        .config_0_write       ( CGRA_config_write       ),
        .config_1_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_1_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_1_read        ( CGRA_config_read        ),
        .config_1_write       ( CGRA_config_write       ),
        .config_2_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_2_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_2_read        ( CGRA_config_read        ),
        .config_2_write       ( CGRA_config_write       ),
        .config_3_config_addr ( POHAN_BUF_CGRA_config_config_addr[P-1] ),
        .config_3_config_data ( POHAN_BUF_CGRA_config_config_data[P-1] ),
        .config_3_read        ( CGRA_config_read        ),
        .config_3_write       ( CGRA_config_write       ),

        .glb2io_16_X00_Y00    ( glb2io_16_X00_Y00 ),
        .glb2io_16_X01_Y00    ( glb2io_16_X01_Y00 ),
        .glb2io_1_X00_Y00     ( glb2io_1_X00_Y00  ),
        .glb2io_1_X01_Y00     ( glb2io_1_X01_Y00  ),

        .io2glb_16_X00_Y00    ( io2glb_16_X00_Y00 ),
        .io2glb_16_X01_Y00    ( io2glb_16_X01_Y00 ),
        .io2glb_1_X00_Y00     ( io2glb_1_X00_Y00  ),
        .io2glb_1_X01_Y00     ( io2glb_1_X01_Y00  ),

        .glb2io_16_X02_Y00    ( 16'd0 ),
        .glb2io_16_X03_Y00    ( 16'd0 ),
        .glb2io_1_X02_Y00     ( 1'b0  ),
        .glb2io_1_X03_Y00     ( 1'b0  ),
        .io2glb_16_X02_Y00    (       ),
        .io2glb_16_X03_Y00    (       ),
        .io2glb_1_X02_Y00     (       ),
        .io2glb_1_X03_Y00     (       )
    );








    assign io_oeb = la_data_in[37:0];


    assign irq = 3'b000;
    assign la_data_out = 128'd0;

endmodule