data/full_repos/permissive/4695331/hdl_harness/mode_setter.v
1: b"%Error: data/full_repos/permissive/4695331/hdl_harness/mode_setter.v:47: syntax error, unexpected ')', expecting '['\n          );\n          ^\n%Error: data/full_repos/permissive/4695331/hdl_harness/mode_setter.v:87: syntax error, unexpected IDENTIFIER\nasync_receiver receiver \n^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mode_setter
          (
           clk_fast,
			  clk_slow,
			  rx,
			  recv_pulse,
			  pace_en,
			  SA_rest,
			  AV_forw,
			  PACen,
			  PVCen,
          );
			 

input clk_fast;
input clk_slow;
input rx;
output recv_pulse;
output pace_en;
output [15:0] SA_rest;
output [15:0] AV_forw;
output  PACen;
output  PVCen;
			 

parameter s_idle = 1'b0;
parameter s_out = 1'b1;
parameter CLOCK_RATIO = 16'd33334;
parameter NUM_BYTES = 4'd4;


wire [7:0] recv_data;
wire recv_data_ready;
reg [7:0] recv_data_reg;

reg state;
reg recv_pulse_reg = 1'b0;
reg [15:0] SA_rest_reg = 16'd900;
reg [15:0] SA_rest_temp_reg = 16'd900;
reg pace_en_reg = 1'b1;
reg pace_en_temp_reg = 1'b1;
reg [15:0] AV_forw_reg = 16'd50;
reg [15:0] AV_forw_temp_reg = 16'd50;
reg PACen_reg = 1'd0;
reg PACen_temp_reg = 1'd0;
reg PVCen_reg = 1'd0;
reg PVCen_temp_reg = 1'd0;
reg [15:0] cnt = 16'd0;
reg [3:0] byte_cnt = 4'd0;


async_receiver receiver 
			(
			.clk(clk_fast), 
			.RxD(rx), 
			.RxD_data_ready(recv_data_ready), 
			.RxD_data(recv_data), 


			);
	
always @(posedge clk_fast) begin
		case(state)
			s_idle:
			begin
				state <= (byte_cnt >= NUM_BYTES) ? s_out : s_idle;

				recv_pulse_reg <= 1'b0;
				PACen_reg <= 1'b0;
				PVCen_reg <= 1'b0;

				recv_data_reg = recv_data;
				if (recv_data_ready && byte_cnt == 4'd0) begin
					SA_rest_temp_reg[7:0] = recv_data_reg;
				end
				else if (recv_data_ready && byte_cnt == 4'd1) begin
					SA_rest_temp_reg[14:8] = recv_data_reg[6:0];
					SA_rest_temp_reg[15] = 1'b0;
					pace_en_temp_reg = recv_data_reg[7];
				end
				else if (recv_data_ready && byte_cnt == 4'd2) begin
					AV_forw_temp_reg[7:0] = recv_data_reg;
				end
				else if (recv_data_ready && byte_cnt == 4'd3) begin
					AV_forw_temp_reg[15:8] = {2'b0,recv_data_reg[5:0]};
					PACen_temp_reg = recv_data_reg[6];
					PVCen_temp_reg = recv_data_reg[7];
				end
				cnt <= 16'd0;
				if (recv_data_ready)
					byte_cnt <= byte_cnt + 4'd1;
			end
			s_out:
			begin
				state <= (cnt >= CLOCK_RATIO) ? s_idle : s_out;
				recv_pulse_reg <= 1'b1;
				SA_rest_reg <= SA_rest_temp_reg;
				pace_en_reg <= pace_en_temp_reg;
				AV_forw_reg <= AV_forw_temp_reg;
				PACen_reg <= PACen_temp_reg;
				PVCen_reg <= PVCen_temp_reg;
				cnt <= cnt + 16'd1;
				byte_cnt <= 4'd0;
			end
		endcase
end
			


assign recv_pulse = recv_pulse_reg;
assign pace_en = pace_en_reg;
assign SA_rest = SA_rest_reg;
assign AV_forw = AV_forw_reg;
assign PACen = PACen_reg;
assign PVCen = PVCen_reg;

endmodule
module mode_setter
          (
           clk_fast,
			  clk_slow,
			  rx,
			  recv_pulse,
			  pace_en,
			  SA_rest,
			  AV_forw,
			  PACen,
			  PVCen,
          );

			 

input clk_fast;
input clk_slow;
input rx;
output recv_pulse;
output pace_en;
output [15:0] SA_rest;
output [15:0] AV_forw;
output  PACen;
output  PVCen;
			 

parameter s_idle = 1'b0;
parameter s_out = 1'b1;
parameter CLOCK_RATIO = 16'd33334;
parameter NUM_BYTES = 4'd4;


wire [7:0] recv_data;
wire recv_data_ready;
reg [7:0] recv_data_reg;

reg state;
reg recv_pulse_reg = 1'b0;
reg [15:0] SA_rest_reg = 16'd900;
reg [15:0] SA_rest_temp_reg = 16'd900;
reg pace_en_reg = 1'b1;
reg pace_en_temp_reg = 1'b1;
reg [15:0] AV_forw_reg = 16'd50;
reg [15:0] AV_forw_temp_reg = 16'd50;
reg PACen_reg = 1'd0;
reg PACen_temp_reg = 1'd0;
reg PVCen_reg = 1'd0;
reg PVCen_temp_reg = 1'd0;
reg [15:0] cnt = 16'd0;
reg [3:0] byte_cnt = 4'd0;


async_receiver receiver 
			(
			.clk(clk_fast), 
			.RxD(rx), 
			.RxD_data_ready(recv_data_ready), 
			.RxD_data(recv_data), 


			);
	
always @(posedge clk_fast) begin
		case(state)
			s_idle:
			begin
				state <= (byte_cnt >= NUM_BYTES) ? s_out : s_idle;

				recv_pulse_reg <= 1'b0;
				PACen_reg <= 1'b0;
				PVCen_reg <= 1'b0;

				recv_data_reg = recv_data;
				if (recv_data_ready && byte_cnt == 4'd0) begin
					SA_rest_temp_reg[7:0] = recv_data_reg;
				end
				else if (recv_data_ready && byte_cnt == 4'd1) begin
					SA_rest_temp_reg[14:8] = recv_data_reg[6:0];
					SA_rest_temp_reg[15] = 1'b0;
					pace_en_temp_reg = recv_data_reg[7];
				end
				else if (recv_data_ready && byte_cnt == 4'd2) begin
					AV_forw_temp_reg[7:0] = recv_data_reg;
				end
				else if (recv_data_ready && byte_cnt == 4'd3) begin
					AV_forw_temp_reg[15:8] = {2'b0,recv_data_reg[5:0]};
					PACen_temp_reg = recv_data_reg[6];
					PVCen_temp_reg = recv_data_reg[7];
				end
				cnt <= 16'd0;
				if (recv_data_ready)
					byte_cnt <= byte_cnt + 4'd1;
			end
			s_out:
			begin
				state <= (cnt >= CLOCK_RATIO) ? s_idle : s_out;
				recv_pulse_reg <= 1'b1;
				SA_rest_reg <= SA_rest_temp_reg;
				pace_en_reg <= pace_en_temp_reg;
				AV_forw_reg <= AV_forw_temp_reg;
				PACen_reg <= PACen_temp_reg;
				PVCen_reg <= PVCen_temp_reg;
				cnt <= cnt + 16'd1;
				byte_cnt <= 4'd0;
			end
		endcase
end
			


assign recv_pulse = recv_pulse_reg;
assign pace_en = pace_en_reg;
assign SA_rest = SA_rest_reg;
assign AV_forw = AV_forw_reg;
assign PACen = PACen_reg;
assign PVCen = PVCen_reg;

endmodule