data/full_repos/permissive/495276914/PC_gen.v
data/verilator_xmls/bc8f85c7-fc72-42de-acec-388933502330.xml
module PC_gen(clk,br_ctrl,rst,pc_br,pc);
    input clk, rst,br_ctrl;
    input [31:0] pc_br;
    output reg[31:0] pc;
    
     always @ (posedge clk) begin  
    if(rst)  
      pc <= 0;
    else if(br_ctrl == 1)
      pc <= pc_br;  
    else  
      pc <= pc + 4;  
  end  
endmodule
module PC_gen(clk,br_ctrl,rst,pc_br,pc);

    input clk, rst,br_ctrl;
    input [31:0] pc_br;
    output reg[31:0] pc;
    
     always @ (posedge clk) begin  
    if(rst)  
      pc <= 0;
    else if(br_ctrl == 1)
      pc <= pc_br;  
    else  
      pc <= pc + 4;  
  end  
endmodule