data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:30: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("design.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:31: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,iiitb_r2_4bit_bm_tb );\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:32: Unsupported or unknown PLI call: $monitor\n       $monitor ( $time, " Q = %b, M = %b, P = %b,Q_t = %b, Q-1 = %b, A = %b", Q, M, P, dut.Q_temp, dut.Q_minus_one, dut.A);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/524458365/iiitb_r2_4bit_bm_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #150 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_r2_4bit_bm_tb;


	reg clk;
	reg load;
	reg reset;
	reg [3:0] M;
	reg [3:0] Q;


	wire [7:0] P;


	 iiitb_r2_4bit_bm dut (
		.clk(clk), 
		.load(load), 
		.reset(reset), 
		.M(M), 
		.Q(Q), 
		.P(P)
	);
	
	always
		#10 clk = ~clk;
  
  initial 
    begin
      	$dumpfile("design.vcd");
        $dumpvars(0,iiitb_r2_4bit_bm_tb );
      	$monitor ( $time, " Q = %b, M = %b, P = %b,Q_t = %b, Q-1 = %b, A = %b", Q, M, P, dut.Q_temp, dut.Q_minus_one, dut.A);
    end
	
	initial begin

		clk  	= 0;
		load 	= 0;
		reset 	= 1'b1;
		M 		= 4'b1010;
		Q 		= 4'b1011;
		#20;
		load  	= 1;
		reset 	= 1'b0;
		#20;
		load 	= 0;
		#150 $finish;

	end
      
endmodule
module iiitb_r2_4bit_bm_tb;



	reg clk;
	reg load;
	reg reset;
	reg [3:0] M;
	reg [3:0] Q;


	wire [7:0] P;


	 iiitb_r2_4bit_bm dut (
		.clk(clk), 
		.load(load), 
		.reset(reset), 
		.M(M), 
		.Q(Q), 
		.P(P)
	);
	
	always
		#10 clk = ~clk;
  
  initial 
    begin
      	$dumpfile("design.vcd");
        $dumpvars(0,iiitb_r2_4bit_bm_tb );
      	$monitor ( $time, " Q = %b, M = %b, P = %b,Q_t = %b, Q-1 = %b, A = %b", Q, M, P, dut.Q_temp, dut.Q_minus_one, dut.A);
    end
	
	initial begin

		clk  	= 0;
		load 	= 0;
		reset 	= 1'b1;
		M 		= 4'b1010;
		Q 		= 4'b1011;
		#20;
		load  	= 1;
		reset 	= 1'b0;
		#20;
		load 	= 0;
		#150 $finish;

	end
      
endmodule