data/full_repos/permissive/471089853/src/lzocshiftersticky_32_to_7_counting_64_f400_uid22.v
data/verilator_xmls/ee3f93a2-0de3-4936-a391-27d119301b08.xml
module LZOCShifterSticky_32_to_7_counting_64_F400_uid22(clk, I, OZb, Count, O, Sticky);
  reg _00_;
  reg _01_;
  reg [30:0] _02_;
  reg _03_;
  reg _04_;
  reg _05_;
  reg _06_;
  reg _07_;
  reg _08_;
  reg _09_;
  reg _10_;
  reg _11_;
  reg [9:0] _12_;
  reg _13_;
  reg _14_;
  reg _15_;
  reg _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg _21_;
  reg _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire [31:0] _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  reg _33_;
  wire _34_;
  wire [30:0] _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  reg _44_;
  wire _45_;
  wire [14:0] _46_;
  wire _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire _51_;
  wire _52_;
  wire _53_;
  wire _54_;
  reg _55_;
  wire _56_;
  wire _57_;
  wire _58_;
  wire [9:0] _59_;
  wire _60_;
  wire _61_;
  wire _62_;
  wire _63_;
  wire _64_;
  wire _65_;
  reg [31:0] _66_;
  wire _67_;
  wire _68_;
  wire _69_;
  wire _70_;
  wire _71_;
  wire [7:0] _72_;
  wire _73_;
  wire _74_;
  wire _75_;
  wire _76_;
  reg _77_;
  wire _78_;
  wire _79_;
  wire _80_;
  wire _81_;
  wire _82_;
  wire [6:0] _83_;
  wire _84_;
  wire _85_;
  wire _86_;
  wire _87_;
  reg _88_;
  wire _89_;
  wire _90_;
  output [5:0] Count;
  input [31:0] I;
  output [6:0] O;
  input OZb;
  output Sticky;
  input clk;
  wire count0;
  wire count1;
  wire count1_d1;
  wire count2;
  wire count2_d1;
  wire count3;
  wire count3_d1;
  wire count3_d2;
  wire count4;
  wire count4_d1;
  wire count4_d2;
  wire count5;
  wire count5_d1;
  wire count5_d2;
  wire count5_d3;
  wire [6:0] level0;
  wire [7:0] level1;
  wire [9:0] level2;
  wire [9:0] level2_d1;
  wire [14:0] level3;
  wire [30:0] level4;
  wire [30:0] level4_d1;
  wire [31:0] level5;
  wire [31:0] level5_d1;
  wire [31:0] level6;
  wire [5:0] scount;
  wire sozb;
  wire sozb_d1;
  wire sozb_d2;
  wire sozb_d3;
  wire sticky0;
  wire sticky1;
  wire sticky2;
  wire sticky2_d1;
  wire sticky3;
  wire sticky4;
  wire sticky4_d1;
  wire sticky5;
  wire sticky5_d1;
  wire sticky6;
  wire sticky_high_0;
  wire sticky_high_1;
  wire sticky_high_1_d1;
  wire sticky_high_2;
  wire sticky_high_3;
  wire sticky_high_3_d1;
  wire sticky_high_4;
  wire sticky_high_4_d1;
  wire sticky_high_5;
  wire sticky_low_0;
  wire sticky_low_0_d1;
  wire sticky_low_0_d2;
  wire sticky_low_0_d3;
  wire sticky_low_1;
  wire sticky_low_1_d1;
  wire sticky_low_1_d2;
  wire sticky_low_1_d3;
  wire sticky_low_2;
  wire sticky_low_3;
  wire sticky_low_3_d1;
  wire sticky_low_4;
  wire sticky_low_4_d1;
  wire sticky_low_5;
  assign _34_ = ~ count4;
  assign _35_ = _34_ ? level5_d1[31:1] : { level5_d1[15:0], 15'h0000 };
  assign _36_ = level5[0] == 1'h0;
  assign _37_ = _36_ ? 1'h0 : 1'h1;
  assign _38_ = sticky5_d1 | sticky_high_4_d1;
  assign _39_ = ~ count4;
  assign _40_ = _39_ ? _38_ : _41_;
  assign _41_ = sticky5_d1 | sticky_low_4_d1;
  assign _42_ = level4[30:23] == { sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1 };
  assign _43_ = _42_ ? 1'h1 : 1'h0;
  assign _45_ = ~ count3_d1;
  assign _46_ = _45_ ? level4_d1[30:16] : level4_d1[22:8];
  assign _47_ = level4[15:0] == 16'h0000;
  assign _48_ = _47_ ? 1'h0 : 1'h1;
  assign _49_ = level4[7:0] == 8'h00;
  assign _50_ = _49_ ? 1'h0 : 1'h1;
  assign _51_ = sticky4_d1 | sticky_high_3_d1;
  assign _52_ = ~ count3_d1;
  assign _53_ = _52_ ? _51_ : _54_;
  assign _54_ = sticky4_d1 | sticky_low_3_d1;
  assign _56_ = level3[14:11] == { sozb_d2, sozb_d2, sozb_d2, sozb_d2 };
  assign _57_ = _56_ ? 1'h1 : 1'h0;
  assign _58_ = ~ count2;
  assign _59_ = _58_ ? level3[14:5] : level3[10:1];
  assign _60_ = level3[4:0] == 5'h00;
  assign _61_ = _60_ ? 1'h0 : 1'h1;
  assign _62_ = level3[0] == 1'h0;
  assign _63_ = _62_ ? 1'h0 : 1'h1;
  assign _64_ = sticky3 | sticky_high_2;
  assign _65_ = ~ count2;
  assign _67_ = _65_ ? _64_ : _68_;
  assign _68_ = sticky3 | sticky_low_2;
  assign _69_ = level2[9:8] == { sozb_d2, sozb_d2 };
  assign _70_ = _69_ ? 1'h1 : 1'h0;
  assign _71_ = ~ count1_d1;
  assign _72_ = _71_ ? level2_d1[9:2] : level2_d1[7:0];
  assign _73_ = level2[1:0] == 2'h0;
  assign _74_ = _73_ ? 1'h0 : 1'h1;
  assign _75_ = sticky2_d1 | sticky_high_1_d1;
  assign _76_ = ~ count1_d1;
  assign _78_ = _76_ ? _75_ : _79_;
  assign _79_ = sticky2_d1 | sticky_low_1_d3;
  assign _80_ = level1[7] == sozb_d3;
  assign _81_ = _80_ ? 1'h1 : 1'h0;
  assign _82_ = ~ count0;
  assign _83_ = _82_ ? level1[7:1] : level1[6:0];
  assign _84_ = level1[0] == 1'h0;
  assign _85_ = _84_ ? 1'h0 : 1'h1;
  assign _86_ = sticky1 | sticky_high_0;
  assign _87_ = ~ count0;
  assign _89_ = _87_ ? _86_ : _90_;
  assign _90_ = sticky1 | sticky_low_0_d3;
  always @(posedge clk)
    _00_ <= sozb;
  always @(posedge clk)
    _11_ <= sozb_d1;
  always @(posedge clk)
    _22_ <= sozb_d2;
  always @(posedge clk)
    _33_ <= count5;
  always @(posedge clk)
    _44_ <= count5_d1;
  always @(posedge clk)
    _55_ <= count5_d2;
  always @(posedge clk)
    _66_ <= level5;
  always @(posedge clk)
    _77_ <= sticky5;
  always @(posedge clk)
    _88_ <= count4;
  always @(posedge clk)
    _01_ <= count4_d1;
  always @(posedge clk)
    _02_ <= level4;
  always @(posedge clk)
    _03_ <= sticky_high_4;
  always @(posedge clk)
    _04_ <= sticky_low_4;
  always @(posedge clk)
    _05_ <= sticky4;
  always @(posedge clk)
    _06_ <= count3;
  always @(posedge clk)
    _07_ <= count3_d1;
  always @(posedge clk)
    _08_ <= sticky_high_3;
  always @(posedge clk)
    _09_ <= sticky_low_3;
  always @(posedge clk)
    _10_ <= count2;
  always @(posedge clk)
    _12_ <= level2;
  always @(posedge clk)
    _13_ <= sticky2;
  always @(posedge clk)
    _14_ <= count1;
  always @(posedge clk)
    _15_ <= sticky_high_1;
  always @(posedge clk)
    _16_ <= sticky_low_1;
  always @(posedge clk)
    _17_ <= sticky_low_1_d1;
  always @(posedge clk)
    _18_ <= sticky_low_1_d2;
  always @(posedge clk)
    _19_ <= sticky_low_0;
  always @(posedge clk)
    _20_ <= sticky_low_0_d1;
  always @(posedge clk)
    _21_ <= sticky_low_0_d2;
  assign _23_ = level6 == { sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb };
  assign _24_ = _23_ ? 1'h1 : 1'h0;
  assign _25_ = ~ count5;
  assign _26_ = _25_ ? level6 : 32'd0;
  assign _27_ = sticky6 | sticky_high_5;
  assign _28_ = ~ count5;
  assign _29_ = _28_ ? _27_ : _30_;
  assign _30_ = sticky6 | sticky_low_5;
  assign _31_ = level5_d1[31:16] == { sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1 };
  assign _32_ = _31_ ? 1'h1 : 1'h0;
  assign level6 = I;
  assign sozb = OZb;
  assign sozb_d1 = _00_;
  assign sozb_d2 = _11_;
  assign sozb_d3 = _22_;
  assign sticky6 = 1'h0;
  assign count5 = _24_;
  assign count5_d1 = _33_;
  assign count5_d2 = _44_;
  assign count5_d3 = _55_;
  assign level5 = _26_;
  assign level5_d1 = _66_;
  assign sticky_high_5 = 1'h0;
  assign sticky_low_5 = 1'h0;
  assign sticky5 = _29_;
  assign sticky5_d1 = _77_;
  assign count4 = _32_;
  assign count4_d1 = _88_;
  assign count4_d2 = _01_;
  assign level4 = _35_;
  assign level4_d1 = _02_;
  assign sticky_high_4 = _37_;
  assign sticky_high_4_d1 = _03_;
  assign sticky_low_4 = 1'h0;
  assign sticky_low_4_d1 = _04_;
  assign sticky4 = _40_;
  assign sticky4_d1 = _05_;
  assign count3 = _43_;
  assign count3_d1 = _06_;
  assign count3_d2 = _07_;
  assign level3 = _46_;
  assign sticky_high_3 = _48_;
  assign sticky_high_3_d1 = _08_;
  assign sticky_low_3 = _50_;
  assign sticky_low_3_d1 = _09_;
  assign sticky3 = _53_;
  assign count2 = _57_;
  assign count2_d1 = _10_;
  assign level2 = _59_;
  assign level2_d1 = _12_;
  assign sticky_high_2 = _61_;
  assign sticky_low_2 = _63_;
  assign sticky2 = _67_;
  assign sticky2_d1 = _13_;
  assign count1 = _70_;
  assign count1_d1 = _14_;
  assign level1 = _72_;
  assign sticky_high_1 = _74_;
  assign sticky_high_1_d1 = _15_;
  assign sticky_low_1 = 1'h0;
  assign sticky_low_1_d1 = _16_;
  assign sticky_low_1_d2 = _17_;
  assign sticky_low_1_d3 = _18_;
  assign sticky1 = _78_;
  assign count0 = _81_;
  assign level0 = _83_;
  assign sticky_high_0 = _85_;
  assign sticky_low_0 = 1'h0;
  assign sticky_low_0_d1 = _19_;
  assign sticky_low_0_d2 = _20_;
  assign sticky_low_0_d3 = _21_;
  assign sticky0 = _89_;
  assign scount = { count5_d3, count4_d2, count3_d2, count2_d1, count1_d1, count0 };
  assign Count = scount;
  assign O = level0;
  assign Sticky = sticky0;
endmodule
module LZOCShifterSticky_32_to_7_counting_64_F400_uid22(clk, I, OZb, Count, O, Sticky);

  reg _00_;
  reg _01_;
  reg [30:0] _02_;
  reg _03_;
  reg _04_;
  reg _05_;
  reg _06_;
  reg _07_;
  reg _08_;
  reg _09_;
  reg _10_;
  reg _11_;
  reg [9:0] _12_;
  reg _13_;
  reg _14_;
  reg _15_;
  reg _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg _21_;
  reg _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire [31:0] _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  reg _33_;
  wire _34_;
  wire [30:0] _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  reg _44_;
  wire _45_;
  wire [14:0] _46_;
  wire _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire _51_;
  wire _52_;
  wire _53_;
  wire _54_;
  reg _55_;
  wire _56_;
  wire _57_;
  wire _58_;
  wire [9:0] _59_;
  wire _60_;
  wire _61_;
  wire _62_;
  wire _63_;
  wire _64_;
  wire _65_;
  reg [31:0] _66_;
  wire _67_;
  wire _68_;
  wire _69_;
  wire _70_;
  wire _71_;
  wire [7:0] _72_;
  wire _73_;
  wire _74_;
  wire _75_;
  wire _76_;
  reg _77_;
  wire _78_;
  wire _79_;
  wire _80_;
  wire _81_;
  wire _82_;
  wire [6:0] _83_;
  wire _84_;
  wire _85_;
  wire _86_;
  wire _87_;
  reg _88_;
  wire _89_;
  wire _90_;
  output [5:0] Count;
  input [31:0] I;
  output [6:0] O;
  input OZb;
  output Sticky;
  input clk;
  wire count0;
  wire count1;
  wire count1_d1;
  wire count2;
  wire count2_d1;
  wire count3;
  wire count3_d1;
  wire count3_d2;
  wire count4;
  wire count4_d1;
  wire count4_d2;
  wire count5;
  wire count5_d1;
  wire count5_d2;
  wire count5_d3;
  wire [6:0] level0;
  wire [7:0] level1;
  wire [9:0] level2;
  wire [9:0] level2_d1;
  wire [14:0] level3;
  wire [30:0] level4;
  wire [30:0] level4_d1;
  wire [31:0] level5;
  wire [31:0] level5_d1;
  wire [31:0] level6;
  wire [5:0] scount;
  wire sozb;
  wire sozb_d1;
  wire sozb_d2;
  wire sozb_d3;
  wire sticky0;
  wire sticky1;
  wire sticky2;
  wire sticky2_d1;
  wire sticky3;
  wire sticky4;
  wire sticky4_d1;
  wire sticky5;
  wire sticky5_d1;
  wire sticky6;
  wire sticky_high_0;
  wire sticky_high_1;
  wire sticky_high_1_d1;
  wire sticky_high_2;
  wire sticky_high_3;
  wire sticky_high_3_d1;
  wire sticky_high_4;
  wire sticky_high_4_d1;
  wire sticky_high_5;
  wire sticky_low_0;
  wire sticky_low_0_d1;
  wire sticky_low_0_d2;
  wire sticky_low_0_d3;
  wire sticky_low_1;
  wire sticky_low_1_d1;
  wire sticky_low_1_d2;
  wire sticky_low_1_d3;
  wire sticky_low_2;
  wire sticky_low_3;
  wire sticky_low_3_d1;
  wire sticky_low_4;
  wire sticky_low_4_d1;
  wire sticky_low_5;
  assign _34_ = ~ count4;
  assign _35_ = _34_ ? level5_d1[31:1] : { level5_d1[15:0], 15'h0000 };
  assign _36_ = level5[0] == 1'h0;
  assign _37_ = _36_ ? 1'h0 : 1'h1;
  assign _38_ = sticky5_d1 | sticky_high_4_d1;
  assign _39_ = ~ count4;
  assign _40_ = _39_ ? _38_ : _41_;
  assign _41_ = sticky5_d1 | sticky_low_4_d1;
  assign _42_ = level4[30:23] == { sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1 };
  assign _43_ = _42_ ? 1'h1 : 1'h0;
  assign _45_ = ~ count3_d1;
  assign _46_ = _45_ ? level4_d1[30:16] : level4_d1[22:8];
  assign _47_ = level4[15:0] == 16'h0000;
  assign _48_ = _47_ ? 1'h0 : 1'h1;
  assign _49_ = level4[7:0] == 8'h00;
  assign _50_ = _49_ ? 1'h0 : 1'h1;
  assign _51_ = sticky4_d1 | sticky_high_3_d1;
  assign _52_ = ~ count3_d1;
  assign _53_ = _52_ ? _51_ : _54_;
  assign _54_ = sticky4_d1 | sticky_low_3_d1;
  assign _56_ = level3[14:11] == { sozb_d2, sozb_d2, sozb_d2, sozb_d2 };
  assign _57_ = _56_ ? 1'h1 : 1'h0;
  assign _58_ = ~ count2;
  assign _59_ = _58_ ? level3[14:5] : level3[10:1];
  assign _60_ = level3[4:0] == 5'h00;
  assign _61_ = _60_ ? 1'h0 : 1'h1;
  assign _62_ = level3[0] == 1'h0;
  assign _63_ = _62_ ? 1'h0 : 1'h1;
  assign _64_ = sticky3 | sticky_high_2;
  assign _65_ = ~ count2;
  assign _67_ = _65_ ? _64_ : _68_;
  assign _68_ = sticky3 | sticky_low_2;
  assign _69_ = level2[9:8] == { sozb_d2, sozb_d2 };
  assign _70_ = _69_ ? 1'h1 : 1'h0;
  assign _71_ = ~ count1_d1;
  assign _72_ = _71_ ? level2_d1[9:2] : level2_d1[7:0];
  assign _73_ = level2[1:0] == 2'h0;
  assign _74_ = _73_ ? 1'h0 : 1'h1;
  assign _75_ = sticky2_d1 | sticky_high_1_d1;
  assign _76_ = ~ count1_d1;
  assign _78_ = _76_ ? _75_ : _79_;
  assign _79_ = sticky2_d1 | sticky_low_1_d3;
  assign _80_ = level1[7] == sozb_d3;
  assign _81_ = _80_ ? 1'h1 : 1'h0;
  assign _82_ = ~ count0;
  assign _83_ = _82_ ? level1[7:1] : level1[6:0];
  assign _84_ = level1[0] == 1'h0;
  assign _85_ = _84_ ? 1'h0 : 1'h1;
  assign _86_ = sticky1 | sticky_high_0;
  assign _87_ = ~ count0;
  assign _89_ = _87_ ? _86_ : _90_;
  assign _90_ = sticky1 | sticky_low_0_d3;
  always @(posedge clk)
    _00_ <= sozb;
  always @(posedge clk)
    _11_ <= sozb_d1;
  always @(posedge clk)
    _22_ <= sozb_d2;
  always @(posedge clk)
    _33_ <= count5;
  always @(posedge clk)
    _44_ <= count5_d1;
  always @(posedge clk)
    _55_ <= count5_d2;
  always @(posedge clk)
    _66_ <= level5;
  always @(posedge clk)
    _77_ <= sticky5;
  always @(posedge clk)
    _88_ <= count4;
  always @(posedge clk)
    _01_ <= count4_d1;
  always @(posedge clk)
    _02_ <= level4;
  always @(posedge clk)
    _03_ <= sticky_high_4;
  always @(posedge clk)
    _04_ <= sticky_low_4;
  always @(posedge clk)
    _05_ <= sticky4;
  always @(posedge clk)
    _06_ <= count3;
  always @(posedge clk)
    _07_ <= count3_d1;
  always @(posedge clk)
    _08_ <= sticky_high_3;
  always @(posedge clk)
    _09_ <= sticky_low_3;
  always @(posedge clk)
    _10_ <= count2;
  always @(posedge clk)
    _12_ <= level2;
  always @(posedge clk)
    _13_ <= sticky2;
  always @(posedge clk)
    _14_ <= count1;
  always @(posedge clk)
    _15_ <= sticky_high_1;
  always @(posedge clk)
    _16_ <= sticky_low_1;
  always @(posedge clk)
    _17_ <= sticky_low_1_d1;
  always @(posedge clk)
    _18_ <= sticky_low_1_d2;
  always @(posedge clk)
    _19_ <= sticky_low_0;
  always @(posedge clk)
    _20_ <= sticky_low_0_d1;
  always @(posedge clk)
    _21_ <= sticky_low_0_d2;
  assign _23_ = level6 == { sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb, sozb };
  assign _24_ = _23_ ? 1'h1 : 1'h0;
  assign _25_ = ~ count5;
  assign _26_ = _25_ ? level6 : 32'd0;
  assign _27_ = sticky6 | sticky_high_5;
  assign _28_ = ~ count5;
  assign _29_ = _28_ ? _27_ : _30_;
  assign _30_ = sticky6 | sticky_low_5;
  assign _31_ = level5_d1[31:16] == { sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1, sozb_d1 };
  assign _32_ = _31_ ? 1'h1 : 1'h0;
  assign level6 = I;
  assign sozb = OZb;
  assign sozb_d1 = _00_;
  assign sozb_d2 = _11_;
  assign sozb_d3 = _22_;
  assign sticky6 = 1'h0;
  assign count5 = _24_;
  assign count5_d1 = _33_;
  assign count5_d2 = _44_;
  assign count5_d3 = _55_;
  assign level5 = _26_;
  assign level5_d1 = _66_;
  assign sticky_high_5 = 1'h0;
  assign sticky_low_5 = 1'h0;
  assign sticky5 = _29_;
  assign sticky5_d1 = _77_;
  assign count4 = _32_;
  assign count4_d1 = _88_;
  assign count4_d2 = _01_;
  assign level4 = _35_;
  assign level4_d1 = _02_;
  assign sticky_high_4 = _37_;
  assign sticky_high_4_d1 = _03_;
  assign sticky_low_4 = 1'h0;
  assign sticky_low_4_d1 = _04_;
  assign sticky4 = _40_;
  assign sticky4_d1 = _05_;
  assign count3 = _43_;
  assign count3_d1 = _06_;
  assign count3_d2 = _07_;
  assign level3 = _46_;
  assign sticky_high_3 = _48_;
  assign sticky_high_3_d1 = _08_;
  assign sticky_low_3 = _50_;
  assign sticky_low_3_d1 = _09_;
  assign sticky3 = _53_;
  assign count2 = _57_;
  assign count2_d1 = _10_;
  assign level2 = _59_;
  assign level2_d1 = _12_;
  assign sticky_high_2 = _61_;
  assign sticky_low_2 = _63_;
  assign sticky2 = _67_;
  assign sticky2_d1 = _13_;
  assign count1 = _70_;
  assign count1_d1 = _14_;
  assign level1 = _72_;
  assign sticky_high_1 = _74_;
  assign sticky_high_1_d1 = _15_;
  assign sticky_low_1 = 1'h0;
  assign sticky_low_1_d1 = _16_;
  assign sticky_low_1_d2 = _17_;
  assign sticky_low_1_d3 = _18_;
  assign sticky1 = _78_;
  assign count0 = _81_;
  assign level0 = _83_;
  assign sticky_high_0 = _85_;
  assign sticky_low_0 = 1'h0;
  assign sticky_low_0_d1 = _19_;
  assign sticky_low_0_d2 = _20_;
  assign sticky_low_0_d3 = _21_;
  assign sticky0 = _89_;
  assign scount = { count5_d3, count4_d2, count3_d2, count2_d1, count1_d1, count0 };
  assign Count = scount;
  assign O = level0;
  assign Sticky = sticky0;
endmodule