data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:293: Unsupported: Ignoring delay on this delayed statement.\n        #0\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:113: Cannot find file containing module: \'SyncResetA\'\n   SyncResetA#(.RSTDELAY(1))  syncReset (.IN_RST(sRST)\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA.v\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA.sv\n             SyncResetA\n             SyncResetA.v\n             SyncResetA.sv\n             obj_dir/SyncResetA\n             obj_dir/SyncResetA.v\n             obj_dir/SyncResetA.sv\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:247: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n             fifoMem[i] = {((dataWidth + 1)/2){2\'b10}} ;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:249: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n        dDoutReg     = {((dataWidth + 1)/2){2\'b10}} ;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:252: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n        sGEnqPtr = {((indxWidth + 2)/2){2\'b10}} ;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:262: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        sSyncReg1 = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:263: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        sDeqPtr   = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:264: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        dSyncReg1 = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:265: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        dEnqPtr   = sGEnqPtr ;\n                  ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testSyncFIFO() ;
   parameter dsize = 8;
   parameter fifodepth = 32;
   parameter fifoidx = 5;

   wire      sCLK,  dCLK, dRST ;
   wire      sENQ, dDEQ;
   wire      sFULL_N, dEMPTY_N ;
   wire [dsize -1:0] sDIN, dDOUT ;

   reg [dsize -1:0]  sCNT, dCNT ;
   reg sRST, sCLR ;

   ClockGen#(15,14,10)  sc( sCLK );
   ClockGen#(11,12,2600)  dc( dCLK );

   initial
     begin
        sCNT = 0;
        dCNT = 0;
        sCLR = 1'b0 ;

        sRST = `BSV_RESET_VALUE ;
        $display( "running test" ) ;

        $dumpfile("SyncFIFO.vcd");
        $dumpvars(5,testSyncFIFO) ;
        $dumpon ;
        #200 ;
        sRST = !`BSV_RESET_VALUE ;


        #100000 $finish ;
     end
   initial
     begin
        #50000 ;
        @(posedge sCLK ) ;
        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
        @(posedge sCLK ) ;
        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;

      end

   SyncFIFO #(dsize,fifodepth,fifoidx)
     dut( sCLK, sRST, dCLK, sENQ, sDIN,
          sFULL_N,
          dDEQ, dDOUT, dEMPTY_N );

   assign sDIN = sCNT ;
   assign sENQ = sFULL_N ;


   always @(posedge sCLK)
     begin
        if (sENQ )
          begin
             sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
          end
      end

   assign dDEQ = dEMPTY_N ;

   always @(posedge dCLK)
     begin
        if (dDEQ )
           begin
              $display( "dequeing %d", dDOUT ) ;
           end
     end

endmodule
module testSyncFIFO() ;

   parameter dsize = 8;
   parameter fifodepth = 32;
   parameter fifoidx = 5;

   wire      sCLK,  dCLK, dRST ;
   wire      sENQ, dDEQ;
   wire      sFULL_N, dEMPTY_N ;
   wire [dsize -1:0] sDIN, dDOUT ;

   reg [dsize -1:0]  sCNT, dCNT ;
   reg sRST, sCLR ;

   ClockGen#(15,14,10)  sc( sCLK );
   ClockGen#(11,12,2600)  dc( dCLK );

   initial
     begin
        sCNT = 0;
        dCNT = 0;
        sCLR = 1'b0 ;

        sRST = `BSV_RESET_VALUE ;
        $display( "running test" ) ;

        $dumpfile("SyncFIFO.vcd");
        $dumpvars(5,testSyncFIFO) ;
        $dumpon ;
        #200 ;
        sRST = !`BSV_RESET_VALUE ;


        #100000 $finish ;
     end
   initial
     begin
        #50000 ;
        @(posedge sCLK ) ;
        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
        @(posedge sCLK ) ;
        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;

      end

   SyncFIFO #(dsize,fifodepth,fifoidx)
     dut( sCLK, sRST, dCLK, sENQ, sDIN,
          sFULL_N,
          dDEQ, dDOUT, dEMPTY_N );

   assign sDIN = sCNT ;
   assign sENQ = sFULL_N ;


   always @(posedge sCLK)
     begin
        if (sENQ )
          begin
             sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
          end
      end

   assign dDEQ = dEMPTY_N ;

   always @(posedge dCLK)
     begin
        if (dDEQ )
           begin
              $display( "dequeing %d", dDOUT ) ;
           end
     end

endmodule