data/full_repos/permissive/449071180/control_signal_mux.v
data/verilator_xmls/54b0c57b-4df0-435a-a086-97721958e6d9.xml
module control_signal_mux(select,in,out);
input select;
input [2:0] in;
output reg [2:0] out;

always@* begin
if(select == 1) begin 
out = in;
end else begin
out = 3'b111;
end



end
endmodule
module control_signal_mux(select,in,out);

input select;
input [2:0] in;
output reg [2:0] out;

always@* begin
if(select == 1) begin 
out = in;
end else begin
out = 3'b111;
end



end
endmodule