data/full_repos/permissive/528252229/if_id.v
1: b'%Error: data/full_repos/permissive/528252229/if_id.v:2: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/if_id.v:9: Define or directive not defined: \'`InstAddrBus\'\n input  wire [`InstAddrBus]      if_pc,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input  wire [`InstAddrBus]      if_pc,\n                          ^\n%Error: data/full_repos/permissive/528252229/if_id.v:10: Define or directive not defined: \'`InstBus\'\n input  wire [`InstBus]          if_inst,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:11: Define or directive not defined: \'`StopBus\'\n input  wire [`StopBus]          stall,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:14: Define or directive not defined: \'`InstAddrBus\'\n output reg  [`InstAddrBus]      id_pc,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:15: Define or directive not defined: \'`InstBus\'\n output wire  [`InstBus]         id_inst\n               ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:22: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:23: Define or directive not defined: \'`InitialPc\'\n            id_pc   <= `InitialPc;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:26: Define or directive not defined: \'`Stop\'\n        else if(stall[1] == `Stop && stall[2] == `NoStop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:26: Define or directive not defined: \'`NoStop\'\n        else if(stall[1] == `Stop && stall[2] == `NoStop) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:27: Define or directive not defined: \'`InitialPc\'\n            id_pc   <= `InitialPc;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:29: Define or directive not defined: \'`NoStop\'\n        end else if(stall[1] == `NoStop) begin\n                                ^~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:39: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:40: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:42: Define or directive not defined: \'`ZeroWord\'\n            inst_lock  <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:52: Define or directive not defined: \'`NoStop\'\n    assign id_inst = (stall_lock1[1] == `NoStop && stall_lock[1] == `Stop) ? inst_lock :\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:52: Define or directive not defined: \'`Stop\'\n    assign id_inst = (stall_lock1[1] == `NoStop && stall_lock[1] == `Stop) ? inst_lock :\n                                                                    ^~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:53: Define or directive not defined: \'`Stop\'\n                     (stall_lock1[1] == `Stop && stall_lock[1] == `Stop) ? inst_lock1 : if_inst;\n                                        ^~~~~\n%Error: data/full_repos/permissive/528252229/if_id.v:53: Define or directive not defined: \'`Stop\'\n                     (stall_lock1[1] == `Stop && stall_lock[1] == `Stop) ? inst_lock1 : if_inst;\n                                                                  ^~~~~\n%Error: Exiting due to 20 error(s)\n'
module if_id(

	input  wire                     clk,
	input  wire                     rst,
	
	input  wire [`InstAddrBus]      if_pc,
	input  wire [`InstBus]          if_inst,
	input  wire [`StopBus]          stall,

    
	output reg  [`InstAddrBus]      id_pc,
	output wire  [`InstBus]         id_inst
	
    );
   


	always @(posedge clk) begin
        if(rst == `RstDisable) begin
            id_pc   <= `InitialPc;

        end
        else if(stall[1] == `Stop && stall[2] == `NoStop) begin
            id_pc   <= `InitialPc;

        end else if(stall[1] == `NoStop) begin
            id_pc   <= if_pc;
        end
    end
    
    reg [5:0] stall_lock;
    reg [5:0] stall_lock1;
    reg [31:0] inst_lock;
    reg [31:0] inst_lock1;
    
    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            stall_lock <= 6'b000000;
            inst_lock  <= `ZeroWord;
        end
        else begin
            stall_lock <= stall;
            stall_lock1 <= stall_lock;
            inst_lock <= if_inst;
            inst_lock1 <= inst_lock;
        end
    end
    
    assign id_inst = (stall_lock1[1] == `NoStop && stall_lock[1] == `Stop) ? inst_lock :
                     (stall_lock1[1] == `Stop && stall_lock[1] == `Stop) ? inst_lock1 : if_inst;

endmodule
module if_id(

	input  wire                     clk,
	input  wire                     rst,
	
	input  wire [`InstAddrBus]      if_pc,
	input  wire [`InstBus]          if_inst,
	input  wire [`StopBus]          stall,

    
	output reg  [`InstAddrBus]      id_pc,
	output wire  [`InstBus]         id_inst
	
    );

   


	always @(posedge clk) begin
        if(rst == `RstDisable) begin
            id_pc   <= `InitialPc;

        end
        else if(stall[1] == `Stop && stall[2] == `NoStop) begin
            id_pc   <= `InitialPc;

        end else if(stall[1] == `NoStop) begin
            id_pc   <= if_pc;
        end
    end
    
    reg [5:0] stall_lock;
    reg [5:0] stall_lock1;
    reg [31:0] inst_lock;
    reg [31:0] inst_lock1;
    
    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            stall_lock <= 6'b000000;
            inst_lock  <= `ZeroWord;
        end
        else begin
            stall_lock <= stall;
            stall_lock1 <= stall_lock;
            inst_lock <= if_inst;
            inst_lock1 <= inst_lock;
        end
    end
    
    assign id_inst = (stall_lock1[1] == `NoStop && stall_lock[1] == `Stop) ? inst_lock :
                     (stall_lock1[1] == `Stop && stall_lock[1] == `Stop) ? inst_lock1 : if_inst;

endmodule