data/full_repos/permissive/434840709/week14/5/5.v
data/verilator_xmls/1d8e46e7-0564-4f96-8945-216b5222c6de.xml
module top_module(
    input clk,
    input reset,
    input in,
    output reg disc,
    output reg flag,
    output reg err
);
    parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, discard=7, err_=8, flag_=9;
    reg [3:0] state,next_state;
    always @(posedge clk) begin
        if (reset) begin
            {disc,flag,err}=3'b000;
        end
        else begin
            case (state)
                S0:
                begin
                    if (in==1) begin
                        next_state = S1; 
                    end
                    else begin
                        next_state = S0; 
                end
            end
                S1:
                begin
                    if (in==1) begin
                        next_state = S2; 
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S2:
                begin
                    if (in==1) begin
                        next_state = S3;  
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S3:
                begin
                    if (in==1) begin
                        next_state = S4; 
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S4:
                begin
                    if (in==1) begin
                        next_state = S5;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S5:
                begin
                    if (in==1) begin
                        next_state = S6; 
                    end
                    else begin
                        next_state = discard;
                    end
                end
                S6:
                begin
                    if (in==1) begin
                        next_state = err_;
                    end
                    else begin
                        next_state = flag_; 
                    end
                end
                discard:
                begin
                    if (in==1) begin
                        next_state = S1;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                err_:
                begin
                    if (in==1) begin
                        next_state = err_;
                    end
                    else begin
                        next_state = S1;
                    end
                end
                flag_:
                begin
                    if (in==1) begin
                        next_state = S1;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                default: next_state = S0;
            endcase
        end
    end

    always @(*) begin
        state <= next_state;
        case (state)
            S0:
                {disc,flag,err}=3'b000;
            S1:
                {disc,flag,err}=3'b000;
            S2:
                {disc,flag,err}=3'b000;
            S3:
                {disc,flag,err}=3'b000;
            S4:
                {disc,flag,err}=3'b000;
            S5:
                {disc,flag,err}=3'b000;
            S6:
                {disc,flag,err}=3'b000;
            discard:
                {disc,flag,err}=3'b100;
            err_:
                {disc,flag,err}=3'b001;
            flag_:
                {disc,flag,err}=3'b010;
        endcase
    end

endmodule
module top_module(
    input clk,
    input reset,
    input in,
    output reg disc,
    output reg flag,
    output reg err
);

    parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, discard=7, err_=8, flag_=9;
    reg [3:0] state,next_state;
    always @(posedge clk) begin
        if (reset) begin
            {disc,flag,err}=3'b000;
        end
        else begin
            case (state)
                S0:
                begin
                    if (in==1) begin
                        next_state = S1; 
                    end
                    else begin
                        next_state = S0; 
                end
            end
                S1:
                begin
                    if (in==1) begin
                        next_state = S2; 
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S2:
                begin
                    if (in==1) begin
                        next_state = S3;  
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S3:
                begin
                    if (in==1) begin
                        next_state = S4; 
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S4:
                begin
                    if (in==1) begin
                        next_state = S5;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                S5:
                begin
                    if (in==1) begin
                        next_state = S6; 
                    end
                    else begin
                        next_state = discard;
                    end
                end
                S6:
                begin
                    if (in==1) begin
                        next_state = err_;
                    end
                    else begin
                        next_state = flag_; 
                    end
                end
                discard:
                begin
                    if (in==1) begin
                        next_state = S1;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                err_:
                begin
                    if (in==1) begin
                        next_state = err_;
                    end
                    else begin
                        next_state = S1;
                    end
                end
                flag_:
                begin
                    if (in==1) begin
                        next_state = S1;
                    end
                    else begin
                        next_state = S0;
                    end
                end
                default: next_state = S0;
            endcase
        end
    end

    always @(*) begin
        state <= next_state;
        case (state)
            S0:
                {disc,flag,err}=3'b000;
            S1:
                {disc,flag,err}=3'b000;
            S2:
                {disc,flag,err}=3'b000;
            S3:
                {disc,flag,err}=3'b000;
            S4:
                {disc,flag,err}=3'b000;
            S5:
                {disc,flag,err}=3'b000;
            S6:
                {disc,flag,err}=3'b000;
            discard:
                {disc,flag,err}=3'b100;
            err_:
                {disc,flag,err}=3'b001;
            flag_:
                {disc,flag,err}=3'b010;
        endcase
    end

endmodule