data/full_repos/permissive/436123010/design_sources/arith_logic_unit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436123010/design_sources/arith_logic_unit.v:35: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                         : ... In instance arith_logic_unit\n                    result = $signed(op1) < $signed(op2);\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module arith_logic_unit(
    input wire [31:0] op1, [31:0] op2, 
    input wire [4:0] shamt,
    input wire [3:0] alu_control,
    output reg zeroFlag,
    output reg[31:0] result    
    );
        always @*
        begin
            case(alu_control)
                4'b0010:
                begin
                   result = op1 + op2;
                   zeroFlag = 0;
                end
                4'b0110:
                begin
                   result = op1 - op2;
                   zeroFlag = (op1 - op2) == 0;
                end 
                4'b0000:
                begin
                    result = op1 & op2;
                    zeroFlag = 0;
                end           
                4'b0001:
                begin
                    result = op1 | op2;
                    zeroFlag = 0;
                end          
                4'b0111:
                begin
                    result = $signed(op1) < $signed(op2);
                    zeroFlag = 0;
                end  
                4'b1111:
                begin
                    result = op2 << shamt; 
                    zeroFlag = 0;
                end
                default:                    
                    zeroFlag = 0;
            endcase                    
        end
endmodule
module arith_logic_unit(
    input wire [31:0] op1, [31:0] op2, 
    input wire [4:0] shamt,
    input wire [3:0] alu_control,
    output reg zeroFlag,
    output reg[31:0] result    
    );

        always @*
        begin
            case(alu_control)
                4'b0010:
                begin
                   result = op1 + op2;
                   zeroFlag = 0;
                end
                4'b0110:
                begin
                   result = op1 - op2;
                   zeroFlag = (op1 - op2) == 0;
                end 
                4'b0000:
                begin
                    result = op1 & op2;
                    zeroFlag = 0;
                end           
                4'b0001:
                begin
                    result = op1 | op2;
                    zeroFlag = 0;
                end          
                4'b0111:
                begin
                    result = $signed(op1) < $signed(op2);
                    zeroFlag = 0;
                end  
                4'b1111:
                begin
                    result = op2 << shamt; 
                    zeroFlag = 0;
                end
                default:                    
                    zeroFlag = 0;
            endcase                    
        end
endmodule