data/full_repos/permissive/487568919/basic_verilog/bin2gray.sv
data/verilator_xmls/f3446e63-64db-48c4-b43f-02e4c34a2ac6.xml
module bin2gray #( parameter
  WIDTH = 32
)(
  input [WIDTH-1:0] bin_in,
  output logic[WIDTH-1:0] gray_out
);

always_comb begin
  gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0]^(bin_in[WIDTH-1:0]>>1);
end

endmodule
module bin2gray #( parameter
  WIDTH = 32
)(
  input [WIDTH-1:0] bin_in,
  output logic[WIDTH-1:0] gray_out
);


always_comb begin
  gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0]^(bin_in[WIDTH-1:0]>>1);
end

endmodule