data/full_repos/permissive/476411617/Sigmoid_PLAN.v
data/verilator_xmls/68049eb6-c2aa-4a7c-863b-d93a2de9c5eb.xml
module Sigmoid_PLAN
    #(parameter N = 32)
    (input clk,
    input [N-1:0] x,
    output reg [N-1:0] out,
	output reg ready
    );
    
parameter [N/2-1:0] z16 = 0;
parameter [N/2-2:0] z15 = 0;
parameter [N/2-3:0] z14 = 0;
parameter [N/2-4:0] z13 = 0;
parameter [N/2-6:0] z11 = 0;


    reg [N-1:0] shif_x, out_tmp;
    reg [N-1:0] abs_x;
    reg [3:0] state = 4'b0;
    always @(posedge clk, x)
    begin
        case(state)
        4'b0000:
        begin
            if ($signed(x) < 0) 
                abs_x = -x;
            else 
                abs_x = x;
            if(abs_x > {z13, 3'b101, z16})
            begin
                state = 4'b0001;
            end
            else if(abs_x < {z13, 3'b101, z16} &&  abs_x >= {z14,5'b10011,z13})
            begin
                state = 4'b0010;
            end
            else if(abs_x >= {z15, 1'b1, z16} &&  abs_x < {z14,5'b10011,z13})
            begin
                state = 4'b0011;
            end
            else if(abs_x < {z15, 1'b1, z16})
            begin
                state = 4'b0100;
            end
        end
        4'b0001:
        begin

            out_tmp[N-1:0] = {z15, 1'b1, z16};
            state = 4'b0101;
        end
        4'b0010:
        begin

            shif_x = abs_x >> 5;
            out_tmp = shif_x + {z16,5'b11011,z11};

            state = 4'b0101;
        end
        4'b0011:
        begin

            shif_x = abs_x >> 3;
            out_tmp = shif_x + {z16,3'b101,z13};

            state = 4'b0101; 
        end
        4'b0100:
        begin

            shif_x = abs_x >> 2;
            out_tmp = shif_x + {z16,1'b1,z15};

            state = 4'b0101; 
        end
        4'b0101:
        begin
            if ($signed(x) > 0) out = out_tmp;
            else out = {z15, 1'b1, z16} - out_tmp;
            state = 4'b0110;
        end
        4'b0110:
        begin
			ready = 1'b1;
            state = 4'b0000;
        end
        endcase
    






    end
endmodule
module Sigmoid_PLAN
    #(parameter N = 32)
    (input clk,
    input [N-1:0] x,
    output reg [N-1:0] out,
	output reg ready
    );

    
parameter [N/2-1:0] z16 = 0;
parameter [N/2-2:0] z15 = 0;
parameter [N/2-3:0] z14 = 0;
parameter [N/2-4:0] z13 = 0;
parameter [N/2-6:0] z11 = 0;


    reg [N-1:0] shif_x, out_tmp;
    reg [N-1:0] abs_x;
    reg [3:0] state = 4'b0;
    always @(posedge clk, x)
    begin
        case(state)
        4'b0000:
        begin
            if ($signed(x) < 0) 
                abs_x = -x;
            else 
                abs_x = x;
            if(abs_x > {z13, 3'b101, z16})
            begin
                state = 4'b0001;
            end
            else if(abs_x < {z13, 3'b101, z16} &&  abs_x >= {z14,5'b10011,z13})
            begin
                state = 4'b0010;
            end
            else if(abs_x >= {z15, 1'b1, z16} &&  abs_x < {z14,5'b10011,z13})
            begin
                state = 4'b0011;
            end
            else if(abs_x < {z15, 1'b1, z16})
            begin
                state = 4'b0100;
            end
        end
        4'b0001:
        begin

            out_tmp[N-1:0] = {z15, 1'b1, z16};
            state = 4'b0101;
        end
        4'b0010:
        begin

            shif_x = abs_x >> 5;
            out_tmp = shif_x + {z16,5'b11011,z11};

            state = 4'b0101;
        end
        4'b0011:
        begin

            shif_x = abs_x >> 3;
            out_tmp = shif_x + {z16,3'b101,z13};

            state = 4'b0101; 
        end
        4'b0100:
        begin

            shif_x = abs_x >> 2;
            out_tmp = shif_x + {z16,1'b1,z15};

            state = 4'b0101; 
        end
        4'b0101:
        begin
            if ($signed(x) > 0) out = out_tmp;
            else out = {z15, 1'b1, z16} - out_tmp;
            state = 4'b0110;
        end
        4'b0110:
        begin
			ready = 1'b1;
            state = 4'b0000;
        end
        endcase
    






    end
endmodule