data/full_repos/permissive/467899092/assignment-des.v
data/verilator_xmls/3166d384-cc47-4fb4-9037-9c4e4faa073c.xml
module majority(
    input a,
    input b,
    input c,
    output x);
  
  wire b_c, and_out, bc;
  
  and (and_out,a,b_c);
  and (bc,c,b);
  or  (b_c,b,c);
  or  (x,and_out,bc);
endmodule
module majority(
    input a,
    input b,
    input c,
    output x);

  
  wire b_c, and_out, bc;
  
  and (and_out,a,b_c);
  and (bc,c,b);
  or  (b_c,b,c);
  or  (x,and_out,bc);
endmodule