data/full_repos/permissive/500001079/blink_1hz.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500001079/blink_1hz.v:29: Operator EQ expects 28 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                   : ... In instance top\n clkout <= (counter == 5\'d0);\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error-PROCASSWIRE: data/full_repos/permissive/500001079/blink_1hz.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'LED1\'\n                                                                       : ... In instance top\n  LED1 <= 0;\n  ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/500001079/blink_1hz.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'LED1\'\n                                                                       : ... In instance top\n  LED1 <= ~LED1;\n  ^~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top (input CLK, input RESETBTN, output LED1);
reg [27:0] counter;
reg clkout;

parameter sys_clk	= 100000000;
parameter clk_out	= 1;
parameter max		  = sys_clk / (2*clk_out);

always @(posedge clkout) begin
	if (RESETBTN == 0) begin
		LED1 <= 0;
	end else begin
		LED1 <= ~LED1;
	end
end



always@(posedge CLK) begin
	if (counter == max-1)
	begin
		counter <= 0;
		clkout <= ~clkout;
	end
	else
	begin
		counter <= counter + 1'd1;
	end
	clkout <= (counter == 5'd0);
end

endmodule
module top (input CLK, input RESETBTN, output LED1);

reg [27:0] counter;
reg clkout;

parameter sys_clk	= 100000000;
parameter clk_out	= 1;
parameter max		  = sys_clk / (2*clk_out);

always @(posedge clkout) begin
	if (RESETBTN == 0) begin
		LED1 <= 0;
	end else begin
		LED1 <= ~LED1;
	end
end



always@(posedge CLK) begin
	if (counter == max-1)
	begin
		counter <= 0;
		clkout <= ~clkout;
	end
	else
	begin
		counter <= counter + 1'd1;
	end
	clkout <= (counter == 5'd0);
end

endmodule