data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/clk_generator_e.v
data/verilator_xmls/d5ba6bc7-0e6c-4b8c-be67-df0c377515be.xml
module clk_generator_e(clk_32f, reset, clk_4f_e, clk_2f_e, clk_f_e);
  (* src = "clk_generator_e.v:12" *)
  reg _00_;
  (* src = "clk_generator_e.v:12" *)
  reg _01_;
  (* src = "clk_generator_e.v:12" *)
  reg _02_;
  (* src = "clk_generator_e.v:12" *)
  reg [3:0] _03_;
  (* src = "clk_generator_e.v:12" *)
  reg [2:0] _04_;
  (* src = "clk_generator_e.v:12" *)
  reg [1:0] _05_;
  (* src = "clk_generator_e.v:23" *)
  reg _06_;
  (* src = "clk_generator_e.v:23" *)
  reg _07_;
  (* src = "clk_generator_e.v:23" *)
  reg _08_;
  (* src = "clk_generator_e.v:23" *)
  reg [3:0] _09_;
  (* src = "clk_generator_e.v:23" *)
  reg [2:0] _10_;
  (* src = "clk_generator_e.v:23" *)
  reg [1:0] _11_;
  (* src = "clk_generator_e.v:13" *)
  wire _12_;
  (* src = "clk_generator_e.v:5" *)
  output clk_2f_e;
  reg clk_2f_e;
  (* src = "clk_generator_e.v:2" *)
  input clk_32f;
  (* src = "clk_generator_e.v:4" *)
  output clk_4f_e;
  reg clk_4f_e;
  (* src = "clk_generator_e.v:6" *)
  output clk_f_e;
  reg clk_f_e;
  (* src = "clk_generator_e.v:10" *)
  reg [3:0] conteo;
  (* src = "clk_generator_e.v:9" *)
  reg [2:0] conteo_2;
  (* src = "clk_generator_e.v:8" *)
  reg [1:0] conteo_4;
  (* src = "clk_generator_e.v:3" *)
  input reset;
  assign _12_ = ~(* src = "clk_generator_e.v:13" *) reset;
  always @* begin
    _04_ = conteo_2;
    _03_ = conteo;
    _02_ = clk_f_e;
    _05_ = conteo_4;
    _01_ = clk_4f_e;
    _00_ = clk_2f_e;
    (* src = "clk_generator_e.v:13" *)
    casez (_12_)

      1'h1:
        begin
          _05_ = 2'h3;
          _04_ = 3'h7;
          _03_ = 4'hf;
          _01_ = 1'h0;
          _00_ = 1'h0;
          _02_ = 1'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      conteo_2 <= _04_;
      conteo <= _03_;
      clk_f_e <= _02_;
      conteo_4 <= _05_;
      clk_4f_e <= _01_;
      clk_2f_e <= _00_;
  end
  always @* begin
    _10_ = conteo_2;
    _09_ = conteo;
    _08_ = clk_f_e;
    _11_ = conteo_4;
    _07_ = clk_4f_e;
    _06_ = clk_2f_e;
    (* src = "clk_generator_e.v:24" *)
    casez (conteo_4)

      2'h0:
          _11_ = 2'h1;

      2'h1:
          _11_ = 2'h2;

      2'h2:
          _11_ = 2'h3;

      2'h3:
        begin
          _11_ = 2'h0;
          (* src = "clk_generator_e.v:31" *)
          casez (clk_4f_e)

            1'h0:
                _07_ = 1'h1;

            1'h1:
                _07_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
    (* src = "clk_generator_e.v:37" *)
    casez (conteo_2)

      3'h0:
          _10_ = 3'h1;

      3'h1:
          _10_ = 3'h2;

      3'h2:
          _10_ = 3'h3;

      3'h3:
          _10_ = 3'h4;

      3'h4:
          _10_ = 3'h5;

      3'h5:
          _10_ = 3'h6;

      3'h6:
          _10_ = 3'h7;

      3'h7:
        begin
          _10_ = 3'h0;
          (* src = "clk_generator_e.v:48" *)
          casez (clk_2f_e)

            1'h0:
                _06_ = 1'h1;

            1'h1:
                _06_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
    (* src = "clk_generator_e.v:54" *)
    casez (conteo)

      4'h0:
          _09_ = 4'h1;

      4'h1:
          _09_ = 4'h2;

      4'h2:
          _09_ = 4'h3;

      4'h3:
          _09_ = 4'h4;

      4'h4:
          _09_ = 4'h5;

      4'h5:
          _09_ = 4'h6;

      4'h6:
          _09_ = 4'h7;

      4'h7:
          _09_ = 4'h8;

      4'h8:
          _09_ = 4'h9;

      4'h9:
          _09_ = 4'ha;

      4'ha:
          _09_ = 4'hb;

      4'hb:
          _09_ = 4'hc;

      4'hc:
          _09_ = 4'hd;

      4'hd:
          _09_ = 4'he;

      4'he:
          _09_ = 4'hf;

      4'hf:
        begin
          _09_ = 4'h0;
          (* src = "clk_generator_e.v:73" *)
          casez (clk_f_e)

            1'h0:
                _08_ = 1'h1;

            1'h1:
                _08_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
  end
  always @(posedge clk_32f) begin
      conteo_2 <= _10_;
      conteo <= _09_;
      clk_f_e <= _08_;
      conteo_4 <= _11_;
      clk_4f_e <= _07_;
      clk_2f_e <= _06_;
  end
endmodule
module clk_generator_e(clk_32f, reset, clk_4f_e, clk_2f_e, clk_f_e);

  (* src = "clk_generator_e.v:12" *)
  reg _00_;
  (* src = "clk_generator_e.v:12" *)
  reg _01_;
  (* src = "clk_generator_e.v:12" *)
  reg _02_;
  (* src = "clk_generator_e.v:12" *)
  reg [3:0] _03_;
  (* src = "clk_generator_e.v:12" *)
  reg [2:0] _04_;
  (* src = "clk_generator_e.v:12" *)
  reg [1:0] _05_;
  (* src = "clk_generator_e.v:23" *)
  reg _06_;
  (* src = "clk_generator_e.v:23" *)
  reg _07_;
  (* src = "clk_generator_e.v:23" *)
  reg _08_;
  (* src = "clk_generator_e.v:23" *)
  reg [3:0] _09_;
  (* src = "clk_generator_e.v:23" *)
  reg [2:0] _10_;
  (* src = "clk_generator_e.v:23" *)
  reg [1:0] _11_;
  (* src = "clk_generator_e.v:13" *)
  wire _12_;
  (* src = "clk_generator_e.v:5" *)
  output clk_2f_e;
  reg clk_2f_e;
  (* src = "clk_generator_e.v:2" *)
  input clk_32f;
  (* src = "clk_generator_e.v:4" *)
  output clk_4f_e;
  reg clk_4f_e;
  (* src = "clk_generator_e.v:6" *)
  output clk_f_e;
  reg clk_f_e;
  (* src = "clk_generator_e.v:10" *)
  reg [3:0] conteo;
  (* src = "clk_generator_e.v:9" *)
  reg [2:0] conteo_2;
  (* src = "clk_generator_e.v:8" *)
  reg [1:0] conteo_4;
  (* src = "clk_generator_e.v:3" *)
  input reset;
  assign _12_ = ~(* src = "clk_generator_e.v:13" *) reset;
  always @* begin
    _04_ = conteo_2;
    _03_ = conteo;
    _02_ = clk_f_e;
    _05_ = conteo_4;
    _01_ = clk_4f_e;
    _00_ = clk_2f_e;
    (* src = "clk_generator_e.v:13" *)
    casez (_12_)

      1'h1:
        begin
          _05_ = 2'h3;
          _04_ = 3'h7;
          _03_ = 4'hf;
          _01_ = 1'h0;
          _00_ = 1'h0;
          _02_ = 1'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      conteo_2 <= _04_;
      conteo <= _03_;
      clk_f_e <= _02_;
      conteo_4 <= _05_;
      clk_4f_e <= _01_;
      clk_2f_e <= _00_;
  end
  always @* begin
    _10_ = conteo_2;
    _09_ = conteo;
    _08_ = clk_f_e;
    _11_ = conteo_4;
    _07_ = clk_4f_e;
    _06_ = clk_2f_e;
    (* src = "clk_generator_e.v:24" *)
    casez (conteo_4)

      2'h0:
          _11_ = 2'h1;

      2'h1:
          _11_ = 2'h2;

      2'h2:
          _11_ = 2'h3;

      2'h3:
        begin
          _11_ = 2'h0;
          (* src = "clk_generator_e.v:31" *)
          casez (clk_4f_e)

            1'h0:
                _07_ = 1'h1;

            1'h1:
                _07_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
    (* src = "clk_generator_e.v:37" *)
    casez (conteo_2)

      3'h0:
          _10_ = 3'h1;

      3'h1:
          _10_ = 3'h2;

      3'h2:
          _10_ = 3'h3;

      3'h3:
          _10_ = 3'h4;

      3'h4:
          _10_ = 3'h5;

      3'h5:
          _10_ = 3'h6;

      3'h6:
          _10_ = 3'h7;

      3'h7:
        begin
          _10_ = 3'h0;
          (* src = "clk_generator_e.v:48" *)
          casez (clk_2f_e)

            1'h0:
                _06_ = 1'h1;

            1'h1:
                _06_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
    (* src = "clk_generator_e.v:54" *)
    casez (conteo)

      4'h0:
          _09_ = 4'h1;

      4'h1:
          _09_ = 4'h2;

      4'h2:
          _09_ = 4'h3;

      4'h3:
          _09_ = 4'h4;

      4'h4:
          _09_ = 4'h5;

      4'h5:
          _09_ = 4'h6;

      4'h6:
          _09_ = 4'h7;

      4'h7:
          _09_ = 4'h8;

      4'h8:
          _09_ = 4'h9;

      4'h9:
          _09_ = 4'ha;

      4'ha:
          _09_ = 4'hb;

      4'hb:
          _09_ = 4'hc;

      4'hc:
          _09_ = 4'hd;

      4'hd:
          _09_ = 4'he;

      4'he:
          _09_ = 4'hf;

      4'hf:
        begin
          _09_ = 4'h0;
          (* src = "clk_generator_e.v:73" *)
          casez (clk_f_e)

            1'h0:
                _08_ = 1'h1;

            1'h1:
                _08_ = 1'h0;
            default:
;
          endcase
        end
      default:
;
    endcase
  end
  always @(posedge clk_32f) begin
      conteo_2 <= _10_;
      conteo <= _09_;
      clk_f_e <= _08_;
      conteo_4 <= _11_;
      clk_4f_e <= _07_;
      clk_2f_e <= _06_;
  end
endmodule