data/full_repos/permissive/445379100/a4/check_misalign.v
data/verilator_xmls/5bc3a32d-2dea-4c74-92b4-d9016a116828.xml
module check_misalign (
    input [31:0] daddr ,
    input [6:0] opcode ,
    input [3:0] dwe ,
    input [31:0] dwdata ,
    input [3:0] rf_we ,
    input [31:0] drdata ,
    output reg [3:0] dwe_checked ,
    output reg [31:0] dwdata_checked ,
    output reg [3:0] rf_we_checked ,
    output reg [31:0] drdata_checked
);
    always @(*) begin
        
        if ( dwe != 4'd0 ) begin
            

            if ( dwe == 4'd1 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = dwe ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b01 ) begin
                dwe_checked = 4'b0010 ;
                dwdata_checked = dwdata<<8 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b10 ) begin
                dwe_checked = 4'b0100 ;
                dwdata_checked = dwdata<<16 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b11 ) begin
                dwe_checked = 4'b1000 ;
                dwdata_checked = dwdata<<24 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end


            else if ( dwe == 4'd3 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = 4'b0011 ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd3 && daddr[1:0] == 2'b10 ) begin
                dwe_checked = 4'b1100 ;
                dwdata_checked = dwdata<<16 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end


            else if ( dwe == 4'd15 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = 4'b1111 ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else begin
                dwe_checked = 0 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
                dwdata_checked = 0 ;
            end

        end

        else if ( rf_we != 4'd0 && opcode == 7'b0000011) begin
            

            if ( rf_we == 4'b0001 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b01 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>8 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b10 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>16 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b11 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>24 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end


            else if ( rf_we == 4'b0011 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b0011 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0011 && daddr[1:0] == 2'b10 ) begin
                rf_we_checked = 4'b0011 ;
                drdata_checked = drdata>>16 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end


            else if ( rf_we == 4'b1111 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b1111 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else begin
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

        end
        
        else begin
            dwe_checked = dwe ;
            dwdata_checked = dwdata ;
            rf_we_checked = rf_we ;
            drdata_checked = drdata ;
        end

    end

endmodule
module check_misalign (
    input [31:0] daddr ,
    input [6:0] opcode ,
    input [3:0] dwe ,
    input [31:0] dwdata ,
    input [3:0] rf_we ,
    input [31:0] drdata ,
    output reg [3:0] dwe_checked ,
    output reg [31:0] dwdata_checked ,
    output reg [3:0] rf_we_checked ,
    output reg [31:0] drdata_checked
);

    always @(*) begin
        
        if ( dwe != 4'd0 ) begin
            

            if ( dwe == 4'd1 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = dwe ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b01 ) begin
                dwe_checked = 4'b0010 ;
                dwdata_checked = dwdata<<8 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b10 ) begin
                dwe_checked = 4'b0100 ;
                dwdata_checked = dwdata<<16 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd1 && daddr[1:0] == 2'b11 ) begin
                dwe_checked = 4'b1000 ;
                dwdata_checked = dwdata<<24 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end


            else if ( dwe == 4'd3 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = 4'b0011 ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else if ( dwe == 4'd3 && daddr[1:0] == 2'b10 ) begin
                dwe_checked = 4'b1100 ;
                dwdata_checked = dwdata<<16 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end


            else if ( dwe == 4'd15 && daddr[1:0] == 2'b00 ) begin
                dwe_checked = 4'b1111 ;
                dwdata_checked = dwdata ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
            end

            else begin
                dwe_checked = 0 ;
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
                dwdata_checked = 0 ;
            end

        end

        else if ( rf_we != 4'd0 && opcode == 7'b0000011) begin
            

            if ( rf_we == 4'b0001 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b01 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>8 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b10 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>16 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0001 && daddr[1:0] == 2'b11 ) begin
                rf_we_checked = 4'b0001 ;
                drdata_checked = drdata>>24 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end


            else if ( rf_we == 4'b0011 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b0011 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else if ( rf_we == 4'b0011 && daddr[1:0] == 2'b10 ) begin
                rf_we_checked = 4'b0011 ;
                drdata_checked = drdata>>16 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end


            else if ( rf_we == 4'b1111 && daddr[1:0] == 2'b00 ) begin
                rf_we_checked = 4'b1111 ;
                drdata_checked = drdata ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

            else begin
                rf_we_checked = 0 ;
                drdata_checked = 0 ;
                dwe_checked = 0 ;
                dwdata_checked = 0 ;
            end

        end
        
        else begin
            dwe_checked = dwe ;
            dwdata_checked = dwdata ;
            rf_we_checked = rf_we ;
            drdata_checked = drdata ;
        end

    end

endmodule