data/full_repos/permissive/49522715/rtl/design/dec_counter.v
data/verilator_xmls/4c257ea9-53f9-431a-a71f-69b20f003455.xml
module dec_counter
  (

  expired, counter,

  clk, rst, load, load_value
  );

  input        clk;
  input        rst;
  input        load;
  input [23:0] load_value;

  output        expired;
  output [24:0] counter;



  reg			expired;




  reg [24:0]   counter;
  reg          counter_d;

  always @(posedge clk) begin
    if (rst == 1'b0) begin
      counter <= 25'h1ffffff;
      counter_d <= 1'b1;
    end
    else begin
      if (load == 1'b1) begin
	counter <= {1'b0, load_value};
	counter_d <= 1'b0;
      end
      else begin
	counter_d <= counter[24];
	if (counter[24] == 1'b0) begin
	  counter <= counter - 1;
	end
	else begin
	  counter <= counter;
	end
      end
    end
  end

  always @(posedge clk) begin
    if (~rst) begin
      expired <= 1'b0;
    end
    else begin
      expired = counter[24] == 1'b1 & counter[24] != counter_d;
    end
  end

endmodule
module dec_counter
  (

  expired, counter,

  clk, rst, load, load_value
  );


  input        clk;
  input        rst;
  input        load;
  input [23:0] load_value;

  output        expired;
  output [24:0] counter;



  reg			expired;




  reg [24:0]   counter;
  reg          counter_d;

  always @(posedge clk) begin
    if (rst == 1'b0) begin
      counter <= 25'h1ffffff;
      counter_d <= 1'b1;
    end
    else begin
      if (load == 1'b1) begin
	counter <= {1'b0, load_value};
	counter_d <= 1'b0;
      end
      else begin
	counter_d <= counter[24];
	if (counter[24] == 1'b0) begin
	  counter <= counter - 1;
	end
	else begin
	  counter <= counter;
	end
      end
    end
  end

  always @(posedge clk) begin
    if (~rst) begin
      expired <= 1'b0;
    end
    else begin
      expired = counter[24] == 1'b1 & counter[24] != counter_d;
    end
  end

endmodule