data/full_repos/permissive/419115923/example.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419115923/example.v:42: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_counter\' generates 4 bits.\n                                                                 : ... In instance the_top_module\n   assign counter = r_counter;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lfsr (
  input        clk,
  input        rst,
  input        en,
  output logic out
);
  logic [7:0] r_lfsr;
  logic [7:0] n_lfsr;

  assign n_lfsr = rst? '0 : ({r_lfsr[6:0], ~(r_lfsr[7] ^ r_lfsr[6])});

   always @(posedge clk)
     r_lfsr <= en? n_lfsr : r_lfsr;

  assign out = r_lfsr[0];
endmodule
module lfsr (
  input        clk,
  input        rst,
  input        en,
  output logic out
);

  logic [7:0] r_lfsr;
  logic [7:0] n_lfsr;

  assign n_lfsr = rst? '0 : ({r_lfsr[6:0], ~(r_lfsr[7] ^ r_lfsr[6])});

   always @(posedge clk)
     r_lfsr <= en? n_lfsr : r_lfsr;

  assign out = r_lfsr[0];
endmodule