data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:60: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'RBUF\'\nmodule RBUF\n       ^~~~\n                                                                                  : ... Top module \'CLKDIV\'\nmodule CLKDIV\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:80: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                               : ... In instance CLKDIV\n                if(cnt == (DIV_CNT-1)) begin\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:25: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n    assign dout = read ? bufdat[curhead] : 0;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:50: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n                    bufdat[curtail] <= din;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:53: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n                    bufdat[curtail] <= din;\n                          ^\n%Error: Exiting due to 5 warning(s)\n'
module RBUF
    #(
        parameter WORDLEN = 8,
        parameter BUFSIZE = 16)
    (
        input clk,
        input rstn,
        input read,
        input write,
        input [WORDLEN-1 : 0] din,
        output [WORDLEN-1 : 0] dout);

    reg [WORDLEN-1 : 0] bufdat [0:BUFSIZE-1];



    reg [4:0] curhead;
    reg [4:0] curtail;
    wire empty;

    integer i;

    assign dout = read ? bufdat[curhead] : 0;
    assign empty = (curhead == curtail);

    always @ (posedge clk) begin
        if(!rstn) begin
            for(i=0; i<BUFSIZE; i=i+1) begin
               bufdat[i] <= 0; 
            end

            curhead <= 0;
            curtail <= 0;
        end else begin
            if (read) begin


                if (curhead+1 == BUFSIZE) begin
                    curhead <= 0;
                end else begin
                    curhead <= curhead + 1;
                end
            end
            if (write) begin

                if (curtail+1 == BUFSIZE) begin
                    curtail <= 0;
                    bufdat[curtail] <= din;
                end else begin
                    curtail <= curtail + 1;
                    bufdat[curtail] <= din;
                end
            end
        end
    end
endmodule
module RBUF
    #(
        parameter WORDLEN = 8,
        parameter BUFSIZE = 16)
    (
        input clk,
        input rstn,
        input read,
        input write,
        input [WORDLEN-1 : 0] din,
        output [WORDLEN-1 : 0] dout);


    reg [WORDLEN-1 : 0] bufdat [0:BUFSIZE-1];



    reg [4:0] curhead;
    reg [4:0] curtail;
    wire empty;

    integer i;

    assign dout = read ? bufdat[curhead] : 0;
    assign empty = (curhead == curtail);

    always @ (posedge clk) begin
        if(!rstn) begin
            for(i=0; i<BUFSIZE; i=i+1) begin
               bufdat[i] <= 0; 
            end

            curhead <= 0;
            curtail <= 0;
        end else begin
            if (read) begin


                if (curhead+1 == BUFSIZE) begin
                    curhead <= 0;
                end else begin
                    curhead <= curhead + 1;
                end
            end
            if (write) begin

                if (curtail+1 == BUFSIZE) begin
                    curtail <= 0;
                    bufdat[curtail] <= din;
                end else begin
                    curtail <= curtail + 1;
                    bufdat[curtail] <= din;
                end
            end
        end
    end
endmodule