data/full_repos/permissive/525452387/core/ex.v
1: b'%Error: data/full_repos/permissive/525452387/core/ex.v:1: Cannot find include file: utils/defines.v\n`include "utils/defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525452387/core,data/full_repos/permissive/525452387/utils/defines.v\n             data/full_repos/permissive/525452387/core,data/full_repos/permissive/525452387/utils/defines.v.v\n             data/full_repos/permissive/525452387/core,data/full_repos/permissive/525452387/utils/defines.v.sv\n             utils/defines.v\n             utils/defines.v.v\n             utils/defines.v.sv\n             obj_dir/utils/defines.v\n             obj_dir/utils/defines.v.v\n             obj_dir/utils/defines.v.sv\n%Error: data/full_repos/permissive/525452387/core/ex.v:52: Define or directive not defined: \'`OPCODE_I\'\n        `OPCODE_I: begin\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:52: syntax error, unexpected \':\', expecting endcase\n        `OPCODE_I: begin\n                 ^\n%Error: data/full_repos/permissive/525452387/core/ex.v:54: Define or directive not defined: \'`FUNCT3_ADDI\'\n                `FUNCT3_ADDI: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:57: Define or directive not defined: \'`FUNCT3_SLTI\'\n                `FUNCT3_SLTI: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:57: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_SLTI: begin\n                              ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:60: Define or directive not defined: \'`FUNCT3_SLTIU\'\n                `FUNCT3_SLTIU: begin\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:60: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_SLTIU: begin\n                               ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:63: Define or directive not defined: \'`FUNCT3_XORI\'\n                `FUNCT3_XORI: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_XORI: begin\n                              ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:66: Define or directive not defined: \'`FUNCT3_ORI\'\n                `FUNCT3_ORI: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:66: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_ORI: begin\n                             ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:69: Define or directive not defined: \'`FUNCT3_ANDI\'\n                `FUNCT3_ANDI: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_ANDI: begin\n                              ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:72: Define or directive not defined: \'`FUNCT3_SLLI\'\n                `FUNCT3_SLLI: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:72: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_SLLI: begin\n                              ^~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:75: Define or directive not defined: \'`FUNCT3_SRI\'\n                `FUNCT3_SRI: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/525452387/core/ex.v:75: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `FUNCT3_SRI: begin\n                             ^~~~~\n%Error: Cannot continue\n'
module ex(
    input wire[31:0] inst_i,

    input wire[4:0] reg_waddr_i,

    input wire[31:0] op1_i,
    input wire[31:0] op2_i,

    output wire[31:0] reg_wdata_o,
    output wire[4:0] reg_waddr_o
);

reg[31:0] reg_wdata;

wire[6:0] opcode;
wire[2:0] funct3;
wire[6:0] funct7;
wire[4:0] rd;
wire[4:0] uimm;

wire[31:0] sri_shift;
wire[31:0] sri_shift_mask;

wire[31:0] op1_plus_op2_res;

wire op1_gte_op2_signed;
wire op1_gte_op2_unsigned;
wire op1_equ_op2;

assign opcode = inst_i[6:0];
assign funct3 = inst_i[14:12];
assign funct7 = inst_i[31:25];
assign rd = inst_i[11:7];
assign uimm = inst_i[19:15];

assign sri_shift = op1_i >> inst_i[24:20];
assign sri_shift_mask = 32'hffffffff >> inst_i[24:20];

assign op1_plus_op2_res     = op1_i + op2_i;

assign op1_gte_op2_signed   = $signed(op1_i) >= $signed(op2_i);
assign op1_gte_op2_unsigned = op1_i >= op2_i;
assign op1_equ_op2          = (op1_i == op2_i);

assign reg_waddr_o = reg_waddr_i;
assign reg_wdata_o = reg_wdata;

always @ (*) begin
    case (opcode)
        `OPCODE_I: begin
            case (funct3)
                `FUNCT3_ADDI: begin
                    reg_wdata = op1_plus_op2_res;
                end
                `FUNCT3_SLTI: begin
                    reg_wdata = {32{(~op1_gte_op2_signed)}} & 32'h1;
                end
                `FUNCT3_SLTIU: begin
                    reg_wdata = {32{(~op1_gte_op2_unsigned)}} & 32'h1;
                end
                `FUNCT3_XORI: begin
                    reg_wdata = op1_i ^ op2_i;
                end
                `FUNCT3_ORI: begin
                    reg_wdata = op1_i | op2_i;
                end
                `FUNCT3_ANDI: begin
                    reg_wdata = op1_i & op2_i;
                end
                `FUNCT3_SLLI: begin
                    reg_wdata = op1_i << inst_i[24:20];
                end
                `FUNCT3_SRI: begin

                    if (inst_i[30] == 1'b1) begin
                        reg_wdata = (sri_shift & sri_shift_mask) |
                            ({32{op1_i[31]}} & (~sri_shift_mask));

                    end else begin
                        reg_wdata = op1_i >> inst_i[24:20];
                    end
                end
                default: begin
                    reg_wdata = 32'b0;
                end
            endcase
        end
    endcase
end

endmodule
module ex(
    input wire[31:0] inst_i,

    input wire[4:0] reg_waddr_i,

    input wire[31:0] op1_i,
    input wire[31:0] op2_i,

    output wire[31:0] reg_wdata_o,
    output wire[4:0] reg_waddr_o
);


reg[31:0] reg_wdata;

wire[6:0] opcode;
wire[2:0] funct3;
wire[6:0] funct7;
wire[4:0] rd;
wire[4:0] uimm;

wire[31:0] sri_shift;
wire[31:0] sri_shift_mask;

wire[31:0] op1_plus_op2_res;

wire op1_gte_op2_signed;
wire op1_gte_op2_unsigned;
wire op1_equ_op2;

assign opcode = inst_i[6:0];
assign funct3 = inst_i[14:12];
assign funct7 = inst_i[31:25];
assign rd = inst_i[11:7];
assign uimm = inst_i[19:15];

assign sri_shift = op1_i >> inst_i[24:20];
assign sri_shift_mask = 32'hffffffff >> inst_i[24:20];

assign op1_plus_op2_res     = op1_i + op2_i;

assign op1_gte_op2_signed   = $signed(op1_i) >= $signed(op2_i);
assign op1_gte_op2_unsigned = op1_i >= op2_i;
assign op1_equ_op2          = (op1_i == op2_i);

assign reg_waddr_o = reg_waddr_i;
assign reg_wdata_o = reg_wdata;

always @ (*) begin
    case (opcode)
        `OPCODE_I: begin
            case (funct3)
                `FUNCT3_ADDI: begin
                    reg_wdata = op1_plus_op2_res;
                end
                `FUNCT3_SLTI: begin
                    reg_wdata = {32{(~op1_gte_op2_signed)}} & 32'h1;
                end
                `FUNCT3_SLTIU: begin
                    reg_wdata = {32{(~op1_gte_op2_unsigned)}} & 32'h1;
                end
                `FUNCT3_XORI: begin
                    reg_wdata = op1_i ^ op2_i;
                end
                `FUNCT3_ORI: begin
                    reg_wdata = op1_i | op2_i;
                end
                `FUNCT3_ANDI: begin
                    reg_wdata = op1_i & op2_i;
                end
                `FUNCT3_SLLI: begin
                    reg_wdata = op1_i << inst_i[24:20];
                end
                `FUNCT3_SRI: begin

                    if (inst_i[30] == 1'b1) begin
                        reg_wdata = (sri_shift & sri_shift_mask) |
                            ({32{op1_i[31]}} & (~sri_shift_mask));

                    end else begin
                        reg_wdata = op1_i >> inst_i[24:20];
                    end
                end
                default: begin
                    reg_wdata = 32'b0;
                end
            endcase
        end
    endcase
end

endmodule