data/full_repos/permissive/452305748/L1/nand_gate/nand_gate.v
data/verilator_xmls/1b503476-4031-4f43-b691-967e7f123c67.xml
module nand_gate(A,
                 B,
                 Y);
    input A;
    input B;
    output Y;
    
    assign Y = ~(A&B);
endmodule
module nand_gate(A,
                 B,
                 Y);

    input A;
    input B;
    output Y;
    
    assign Y = ~(A&B);
endmodule