data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:25: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:28: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:44: Define or directive not defined: \'`CPX_WIDTH\'\n   output [`CPX_WIDTH-1:0]  io_cpx_data_ca2; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:48: Define or directive not defined: \'`CPX_WIDTH\'\n   input [`CPX_WIDTH-1:0]  io_cpx_data_ca; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:57: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_s #(`CPX_WIDTH) dff_io_cpx_data(\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:58: Define or directive not defined: \'`CPX_WIDTH\'\n            .din           (io_cpx_data_ca[`CPX_WIDTH-1:0]),\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:59: Define or directive not defined: \'`CPX_WIDTH\'\n     .q             (io_cpx_data_ca2[`CPX_WIDTH-1:0]),\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/io_cpx_reqdata_ff.v:62: Define or directive not defined: \'`CPX_WIDTH\'\n     .si            (`CPX_WIDTH\'d0),\n                     ^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module io_cpx_reqdata_ff(

   io_cpx_data_ca2, io_cpx_req_cq2, scan_out, 

   io_cpx_data_ca, io_cpx_req_cq, rclk, scan_in, se
   );
   

   output [`CPX_WIDTH-1:0]		io_cpx_data_ca2;	
   output [7:0]		io_cpx_req_cq2;	
   output 		scan_out;
   
   input [`CPX_WIDTH-1:0]		io_cpx_data_ca;	
   input [7:0]		io_cpx_req_cq;	

   input 		rclk;
   input 		scan_in;
   input 		se;
   

   
   dff_s #(`CPX_WIDTH) dff_io_cpx_data(
            .din           (io_cpx_data_ca[`CPX_WIDTH-1:0]),
	    .q             (io_cpx_data_ca2[`CPX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (se),
	    .si            (`CPX_WIDTH'd0),
	    .so            ());




      dff_s #(8) dff_cpx_datardy_io(
            .din           (io_cpx_req_cq[7:0]),
	    .q             (io_cpx_req_cq2[7:0]),
	    .clk           (rclk),
	    .se            (se),
	    .si            (8'd0),
	    .so            ());


endmodule
module io_cpx_reqdata_ff(

   io_cpx_data_ca2, io_cpx_req_cq2, scan_out, 

   io_cpx_data_ca, io_cpx_req_cq, rclk, scan_in, se
   );

   

   output [`CPX_WIDTH-1:0]		io_cpx_data_ca2;	
   output [7:0]		io_cpx_req_cq2;	
   output 		scan_out;
   
   input [`CPX_WIDTH-1:0]		io_cpx_data_ca;	
   input [7:0]		io_cpx_req_cq;	

   input 		rclk;
   input 		scan_in;
   input 		se;
   

   
   dff_s #(`CPX_WIDTH) dff_io_cpx_data(
            .din           (io_cpx_data_ca[`CPX_WIDTH-1:0]),
	    .q             (io_cpx_data_ca2[`CPX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (se),
	    .si            (`CPX_WIDTH'd0),
	    .so            ());




      dff_s #(8) dff_cpx_datardy_io(
            .din           (io_cpx_req_cq[7:0]),
	    .q             (io_cpx_req_cq2[7:0]),
	    .clk           (rclk),
	    .se            (se),
	    .si            (8'd0),
	    .so            ());


endmodule