data/full_repos/permissive/419115923/example.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419115923/example.v:42: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_counter\' generates 4 bits.\n                                                                 : ... In instance the_top_module\n   assign counter = r_counter;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module the_top_module (
  input 	     clk,
  input 	     rst,
  input 	     en_counter,
  input 	     en_lfsr,
  output logic [1:0] counter,
  output logic 	     lfsr
);

  logic [3:0] r_counter = '0;
  logic [3:0] n_counter;

  lfsr a_submodule (
    .clk(clk),
    .rst(rst),
    .en(en_lfsr),
    .out(lfsr)
  );

  assign n_counter = rst? '0 : (r_counter + 4'd1);
  
  always @(posedge clk)
    r_counter <= en_counter? n_counter : r_counter;

   assign counter = r_counter;
endmodule
module the_top_module (
  input 	     clk,
  input 	     rst,
  input 	     en_counter,
  input 	     en_lfsr,
  output logic [1:0] counter,
  output logic 	     lfsr
);


  logic [3:0] r_counter = '0;
  logic [3:0] n_counter;

  lfsr a_submodule (
    .clk(clk),
    .rst(rst),
    .en(en_lfsr),
    .out(lfsr)
  );

  assign n_counter = rst? '0 : (r_counter + 4'd1);
  
  always @(posedge clk)
    r_counter <= en_counter? n_counter : r_counter;

   assign counter = r_counter;
endmodule