data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v
1: b'%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:25: Cannot find include file: wb_host.lvs.powered.v\n`include "wb_host.lvs.powered.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421663164/foss/frontend/exp1/pgate,data/full_repos/permissive/421663164/wb_host.lvs.powered.v\n             data/full_repos/permissive/421663164/foss/frontend/exp1/pgate,data/full_repos/permissive/421663164/wb_host.lvs.powered.v.v\n             data/full_repos/permissive/421663164/foss/frontend/exp1/pgate,data/full_repos/permissive/421663164/wb_host.lvs.powered.v.sv\n             wb_host.lvs.powered.v\n             wb_host.lvs.powered.v.v\n             wb_host.lvs.powered.v.sv\n             obj_dir/wb_host.lvs.powered.v\n             obj_dir/wb_host.lvs.powered.v.v\n             obj_dir/wb_host.lvs.powered.v.sv\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:26: Cannot find include file: ../libs.ref/sky130_fd_sc_hd/verilog/primitives.v\n`include "../libs.ref/sky130_fd_sc_hd/verilog/primitives.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:27: Cannot find include file: ../libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v\n`include "../libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:64: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #200;  \n   ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:92: syntax error, unexpected \'@\'\n   repeat (10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:95: Unsupported: fork statements\n   fork\n   ^~~~\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:100: syntax error, unexpected \'@\'\n        repeat (2) @(posedge clock);\n                   ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:105: syntax error, unexpected \'@\'\n         repeat (1000) @(posedge clock);\n                       ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:109: Unsupported: disable fork statements\n   disable fork;  \n   ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:155: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:163: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:164: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:173: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:183: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:191: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:193: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/tb_top.v:206: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 16 error(s), 8 warning(s)\n'
module tb_top;

reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

reg            test_fail     ;
reg [31:0]     read_data     ;

integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("tb_top.vcd");
	   	$dumpvars(0,tb_top);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   test_fail = 0;
   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Uart Test Started");
  
   fork
     begin 
        wb_user_core_write('h3000_0000,'h11223344);
        wb_user_core_write('h3000_0004,'h55667788);

        repeat (2) @(posedge clock);
        wb_user_core_read_check('h3000_0000,'h11223344,read_data);
        wb_user_core_read_check('h3000_0004,'h55667788,read_data);
    end
    begin
         repeat (1000) @(posedge clock);
	 test_fail = 1;
    end
   join_any
   disable fork;



  $display("########################");
  if(test_fail)
     $display ("TEST FAILED");
  else
     $display ("TEST PASSED");
  $display("########################");
  #100
  $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


wb_host u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wbm_clk_i   (clock),
    .wbm_rst_i   (wb_rst_i),

    .wbm_cyc_i   (wbd_ext_cyc_i),
    .wbm_stb_i   (wbd_ext_stb_i),
    .wbm_adr_i   (wbd_ext_adr_i),
    .wbm_we_i    (wbd_ext_we_i),
    .wbm_dat_i   (wbd_ext_dat_i),
    .wbm_sel_i   (wbd_ext_sel_i),

    .wbm_dat_o   (wbd_ext_dat_o),
    .wbm_ack_o   (wbd_ext_ack_o)


);



task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
input [31:0] exp_data;
output [31:0] rx_data;
reg    [31:0] rx_data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  rx_data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(exp_data != rx_data) begin
      $display("ERROR: WB USER ACCESS READ Address : %x, Exp: %x Rxd : %x",address,exp_data,rx_data);
      test_fail = 1;
  end else
      $display("STATUS: WB USER ACCESS READ Address : %x, Data : %x",address,rx_data);
  repeat (2) @(posedge clock);
end
endtask




endmodule
module tb_top;


reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

reg            test_fail     ;
reg [31:0]     read_data     ;

integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("tb_top.vcd");
	   	$dumpvars(0,tb_top);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   test_fail = 0;
   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Uart Test Started");
  
   fork
     begin 
        wb_user_core_write('h3000_0000,'h11223344);
        wb_user_core_write('h3000_0004,'h55667788);

        repeat (2) @(posedge clock);
        wb_user_core_read_check('h3000_0000,'h11223344,read_data);
        wb_user_core_read_check('h3000_0004,'h55667788,read_data);
    end
    begin
         repeat (1000) @(posedge clock);
	 test_fail = 1;
    end
   join_any
   disable fork;



  $display("########################");
  if(test_fail)
     $display ("TEST FAILED");
  else
     $display ("TEST PASSED");
  $display("########################");
  #100
  $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


wb_host u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wbm_clk_i   (clock),
    .wbm_rst_i   (wb_rst_i),

    .wbm_cyc_i   (wbd_ext_cyc_i),
    .wbm_stb_i   (wbd_ext_stb_i),
    .wbm_adr_i   (wbd_ext_adr_i),
    .wbm_we_i    (wbd_ext_we_i),
    .wbm_dat_i   (wbd_ext_dat_i),
    .wbm_sel_i   (wbd_ext_sel_i),

    .wbm_dat_o   (wbd_ext_dat_o),
    .wbm_ack_o   (wbd_ext_ack_o)


);



task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
input [31:0] exp_data;
output [31:0] rx_data;
reg    [31:0] rx_data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  rx_data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(exp_data != rx_data) begin
      $display("ERROR: WB USER ACCESS READ Address : %x, Exp: %x Rxd : %x",address,exp_data,rx_data);
      test_fail = 1;
  end else
      $display("STATUS: WB USER ACCESS READ Address : %x, Data : %x",address,rx_data);
  repeat (2) @(posedge clock);
end
endtask




endmodule