data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_wb.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_wb.v:10: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module UART_wb (clk,
        wb_rst_i, 

	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, 

	we_o

	
        );

input				clk;


input				wb_rst_i;



input				wb_we_i;
input				wb_stb_i;
input				wb_cyc_i;
output				wb_ack_o;

output				we_o;



reg				we_o;
reg				wb_ack_o;



always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i == 1)
	begin
		we_o <= #1 0;
		wb_ack_o <= #1 0;
	end
	else
	begin
		we_o <= #1 wb_we_i & wb_cyc_i & wb_stb_i;
		wb_ack_o <= #1 wb_stb_i & wb_cyc_i;
	end
end

endmodule
module UART_wb (clk,
        wb_rst_i, 

	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, 

	we_o

	
        );


input				clk;


input				wb_rst_i;



input				wb_we_i;
input				wb_stb_i;
input				wb_cyc_i;
output				wb_ack_o;

output				we_o;



reg				we_o;
reg				wb_ack_o;



always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i == 1)
	begin
		we_o <= #1 0;
		wb_ack_o <= #1 0;
	end
	else
	begin
		we_o <= #1 wb_we_i & wb_cyc_i & wb_stb_i;
		wb_ack_o <= #1 wb_stb_i & wb_cyc_i;
	end
end

endmodule