data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit_tb.v:36: Cannot find file containing module: \'FAnbit\'\n  FAnbit\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FAnbit\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FAnbit.v\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FAnbit.sv\n             FAnbit\n             FAnbit.v\n             FAnbit.sv\n             obj_dir/FAnbit\n             obj_dir/FAnbit.v\n             obj_dir/FAnbit.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FAnbit_tb
#(parameter DT_TB=4)
(

    );
  
  reg [DT_TB-1:0] abit_tb, bbit_tb;
  reg cinbit_tb;
  
  
  wire [DT_TB-1:0] sumbit_tb;
  wire coutbit_tb;
  
  FAnbit
  #(
    .DT(DT_TB)
  )  
  
    FA_TB_NBITS
    (
                 .cinbit(cinbit_tb),
                 .abit(abit_tb),
                 .bbit(bbit_tb),
                 .sumbit(sumbit_tb),
                 .coutbit(coutbit_tb)
    );
    
    initial
            begin:  TST1 
               abit_tb = 4;
               bbit_tb = 7;
               cinbit_tb = 0; 
               
               
            #1000
            $finish; 
            end

    
    
    
    
endmodule
module FAnbit_tb
#(parameter DT_TB=4)
(

    );

  
  reg [DT_TB-1:0] abit_tb, bbit_tb;
  reg cinbit_tb;
  
  
  wire [DT_TB-1:0] sumbit_tb;
  wire coutbit_tb;
  
  FAnbit
  #(
    .DT(DT_TB)
  )  
  
    FA_TB_NBITS
    (
                 .cinbit(cinbit_tb),
                 .abit(abit_tb),
                 .bbit(bbit_tb),
                 .sumbit(sumbit_tb),
                 .coutbit(coutbit_tb)
    );
    
    initial
            begin:  TST1 
               abit_tb = 4;
               bbit_tb = 7;
               cinbit_tb = 0; 
               
               
            #1000
            $finish; 
            end

    
    
    
    
endmodule