data/full_repos/permissive/437141606/MIPS_fpga.v
1: b"%Error: data/full_repos/permissive/437141606/MIPS_fpga.v:33: Cannot find file containing module: 'mips'\n mips mips(clksec, reset,writedata, dataadr, \n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.v\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s)\n"
module clk_gen(
	input			clk50MHz, reset, 
	output reg		clksec );

	reg 			clk_5KHz;
	integer 		count, count1;
	
	always@(posedge clk50MHz) begin
		if(reset) begin
			count = 0;
			count1 = 0;
			clksec = 0;
			clk_5KHz =0;
		end else begin
			if (count == 50000000) begin

				clksec = ~clksec;
				count = 0;
			end
			if (count1 == 20000) begin
				clk_5KHz = ~clk_5KHz;
				count1 = 0;
			end
			count = count + 1;
			count1 = count1 + 1;
		end
	end
endmodule
module clk_gen(
	input			clk50MHz, reset, 
	output reg		clksec );


	reg 			clk_5KHz;
	integer 		count, count1;
	
	always@(posedge clk50MHz) begin
		if(reset) begin
			count = 0;
			count1 = 0;
			clksec = 0;
			clk_5KHz =0;
		end else begin
			if (count == 50000000) begin

				clksec = ~clksec;
				count = 0;
			end
			if (count1 == 20000) begin
				clk_5KHz = ~clk_5KHz;
				count1 = 0;
			end
			count = count + 1;
			count1 = count1 + 1;
		end
	end
endmodule