data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/03_Arithmetic_Circuits/03_3-bit-binary_adder.v
data/verilator_xmls/1503852d-f30f-47c4-bcbf-d80c10f08d09.xml
module top_module( 
    input [2:0] a, b,
    input cin,
    output reg [2:0] cout,
    output reg [2:0] sum
);
    
    full_adder my_RCA [2:0] (
        .a(a),
        .b(b),
        .cin({cout[1:0], cin}),
        .cout(cout),
        .sum(sum)
    );

endmodule
module top_module( 
    input [2:0] a, b,
    input cin,
    output reg [2:0] cout,
    output reg [2:0] sum
);

    
    full_adder my_RCA [2:0] (
        .a(a),
        .b(b),
        .cin({cout[1:0], cin}),
        .cout(cout),
        .sum(sum)
    );

endmodule