data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_tsr.v
data/verilator_xmls/da882340-30c3-4a15-93a1-2e666f74d265.xml
module bw_tsr (
	vdd_tsr,
	div,
	clk,
	reset_l,
	tsel,
   	dout,
   	testio,
	i50,
	v0p5,
	vreg_selbg_l);

	input  vdd_tsr;
	input  [9:1] div;
	input  clk;
	input  reset_l;
	input  [7:0] tsel;
	input  vreg_selbg_l;

   	output [7:0] dout;
   	output [1:0] testio;
	output [7:0] i50;
	output v0p5;
















endmodule
module bw_tsr (
	vdd_tsr,
	div,
	clk,
	reset_l,
	tsel,
   	dout,
   	testio,
	i50,
	v0p5,
	vreg_selbg_l);


	input  vdd_tsr;
	input  [9:1] div;
	input  clk;
	input  reset_l;
	input  [7:0] tsel;
	input  vreg_selbg_l;

   	output [7:0] dout;
   	output [1:0] testio;
	output [7:0] i50;
	output v0p5;
















endmodule