data/full_repos/permissive/423006272/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/423006272/verilog/rtl/user_proj_example.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423006272/verilog/rtl/user_proj_example.v:73: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423006272/verilog/rtl/user_proj_example.v:74: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    localparam INPUTA_ADDR  = 0;
    localparam INPUTB_ADDR  = 1;
    localparam OUTPUT_ADDR  = 2;

    wire clk;
    wire rst;

    reg  [31:0] input_regA;
    reg  [31:0] input_regB;
    reg  [31:0] output_reg;

    reg         wbs_done;
    reg  [31:0] rdata; 
    wire [31:0] wdata;
    wire        valid;
    wire [3:0]  wstrb;
    wire        addr_valid;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;
    assign addr_valid = (wbs_adr_i[31:28] == 3) ? 1 : 0;
    assign wbs_ack_o  = wbs_done;

    assign clk = wb_clk_i;
    assign rst = wb_rst_i;

always@(posedge clk) begin
		if(rst) begin
			input_reg    <= 0;
			output_reg   <= 0;
            rdata        <= 0; 
            wbs_done <= 0;
		end
		else begin
			wbs_done <= 0;
			if (valid && addr_valid)  begin     
				case(wbs_adr_i[7:2])   
					INPUTA_ADDR: 
 						       begin	
                                   rdata <= input_regA;
		                           if(wstrb[0])
		                             input_regA <= wdata;
						       end            
  				INPUTB_ADDR: 
 						       begin	
                                   rdata <= input_regB;
		                           if(wstrb[0])
		                             input_regB <= wdata;
						       end            
          OUTPUT_ADDR: 
 						begin	
                        	rdata <= output_reg;
						end            
            default: ;
				endcase
 			 wbs_done <= 1; 
			end
    end 
 end




always@(posedge clk) begin

  output_reg <= input_regA + input_regB ;

end 


endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


    localparam INPUTA_ADDR  = 0;
    localparam INPUTB_ADDR  = 1;
    localparam OUTPUT_ADDR  = 2;

    wire clk;
    wire rst;

    reg  [31:0] input_regA;
    reg  [31:0] input_regB;
    reg  [31:0] output_reg;

    reg         wbs_done;
    reg  [31:0] rdata; 
    wire [31:0] wdata;
    wire        valid;
    wire [3:0]  wstrb;
    wire        addr_valid;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;
    assign addr_valid = (wbs_adr_i[31:28] == 3) ? 1 : 0;
    assign wbs_ack_o  = wbs_done;

    assign clk = wb_clk_i;
    assign rst = wb_rst_i;

always@(posedge clk) begin
		if(rst) begin
			input_reg    <= 0;
			output_reg   <= 0;
            rdata        <= 0; 
            wbs_done <= 0;
		end
		else begin
			wbs_done <= 0;
			if (valid && addr_valid)  begin     
				case(wbs_adr_i[7:2])   
					INPUTA_ADDR: 
 						       begin	
                                   rdata <= input_regA;
		                           if(wstrb[0])
		                             input_regA <= wdata;
						       end            
  				INPUTB_ADDR: 
 						       begin	
                                   rdata <= input_regB;
		                           if(wstrb[0])
		                             input_regB <= wdata;
						       end            
          OUTPUT_ADDR: 
 						begin	
                        	rdata <= output_reg;
						end            
            default: ;
				endcase
 			 wbs_done <= 1; 
			end
    end 
 end




always@(posedge clk) begin

  output_reg <= input_regA + input_regB ;

end 


endmodule