data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        forever # 5 clk_i = ~clk_i;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        # 2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        # 20 rstn_i = ~rstn_i;\n        ^\n%Error: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:40: syntax error, unexpected \'@\'\n            @ (posedge clk_i) begin           \n            ^\n%Error: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:41: Unsupported or unknown PLI call: $urandom_range\n                _vld = $urandom_range(1, 0);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:44: Unsupported or unknown PLI call: $urandom_range\n                    data_i <= $urandom_range(DATA_RANGE);  \n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/497037186/Histogram-IP/Histogram_tb.v:59: syntax error, unexpected end\n    end\n    ^~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Histogram_tb();   
    
    parameter C_DATA_WIDTH = 8;
    parameter C_QUANTITY = 16;
    
    reg clk_i;
    reg rstn_i;
    reg valid_i;
    reg write_en_i;
    reg last_i;
    reg [C_DATA_WIDTH - 1 : 0] data_i;
    
    wire last_o;
    wire valid_o;
    wire [$clog2(C_QUANTITY) - 1 : 0] data_o;
    
    localparam DATA_RANGE = 15;
    localparam NUM_TEST_DATA = 256;
    
    reg _vld = 0;
    
    initial begin
        clk_i      = 0;
        rstn_i     = 0;
        valid_i    = 0;
        last_i     = 0;
    end
    
    initial begin
        # 2 
        forever # 5 clk_i = ~clk_i;
    end
    
    integer i, _outPixelCnt;
    initial begin
        # 20 rstn_i = ~rstn_i;
        for (i = 0; i < NUM_TEST_DATA; i = i + 1) begin
            @ (posedge clk_i) begin           
                _vld = $urandom_range(1, 0);
                valid_i <= _vld;
                if (_vld == 1) begin
                    data_i <= $urandom_range(DATA_RANGE);
                    $display("The clk number: %d and data: %d.", i, data_i);
                    if (i < (NUM_TEST_DATA-1)) begin
                        last_i <= 0;
                    end
                    else if (i == (NUM_TEST_DATA-1)) begin
                        last_i <= 1;
                        valid_i <= 0;
                    end
                end
                else begin
                    last_i <= 0;
                end
            end
        end
    end
    
    Histogram Histogram_uut
    (
       .clk_i(clk_i),
       .rstn_i(rstn_i),
       .valid_i(valid_i),
       .write_en_i(),
       .last_i(last_i),
       .data_i(data_i),
       .last_o(last_o),
       .valid_o(valid_o),
       .data_o(data_o)       
    );
    





    
endmodule
module Histogram_tb();
   
    
    parameter C_DATA_WIDTH = 8;
    parameter C_QUANTITY = 16;
    
    reg clk_i;
    reg rstn_i;
    reg valid_i;
    reg write_en_i;
    reg last_i;
    reg [C_DATA_WIDTH - 1 : 0] data_i;
    
    wire last_o;
    wire valid_o;
    wire [$clog2(C_QUANTITY) - 1 : 0] data_o;
    
    localparam DATA_RANGE = 15;
    localparam NUM_TEST_DATA = 256;
    
    reg _vld = 0;
    
    initial begin
        clk_i      = 0;
        rstn_i     = 0;
        valid_i    = 0;
        last_i     = 0;
    end
    
    initial begin
        # 2 
        forever # 5 clk_i = ~clk_i;
    end
    
    integer i, _outPixelCnt;
    initial begin
        # 20 rstn_i = ~rstn_i;
        for (i = 0; i < NUM_TEST_DATA; i = i + 1) begin
            @ (posedge clk_i) begin           
                _vld = $urandom_range(1, 0);
                valid_i <= _vld;
                if (_vld == 1) begin
                    data_i <= $urandom_range(DATA_RANGE);
                    $display("The clk number: %d and data: %d.", i, data_i);
                    if (i < (NUM_TEST_DATA-1)) begin
                        last_i <= 0;
                    end
                    else if (i == (NUM_TEST_DATA-1)) begin
                        last_i <= 1;
                        valid_i <= 0;
                    end
                end
                else begin
                    last_i <= 0;
                end
            end
        end
    end
    
    Histogram Histogram_uut
    (
       .clk_i(clk_i),
       .rstn_i(rstn_i),
       .valid_i(valid_i),
       .write_en_i(),
       .last_i(last_i),
       .data_i(data_i),
       .last_o(last_o),
       .valid_o(valid_o),
       .data_o(data_o)       
    );
    





    
endmodule