data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:213: Operator ADD expects 3 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n      +  idata[1]  \n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:213: Operator ADD expects 3 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n      +  idata[1]  \n      ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:214: Operator ADD expects 3 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n      +  idata[2] ) \n      ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:215: Operator ADD expects 3 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n      +  idata[3]  ;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:231: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'nan_num_in_8byte\' generates 3 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n            {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:241: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n            {mon_inf_in_count,inf_in_count[31:0]} <= 32\'d0;\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v:243: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'inf_num_in_8byte\' generates 3 bits.\n                                                                                                                                    : ... In instance NV_NVDLA_CDP_DP_nan\n            {mon_inf_in_count,inf_in_count[31:0]} <= inf_in_count + inf_num_in_8byte;\n                                                                  ^\n%Error: Exiting due to 7 warning(s)\n'
function [2:0] fun_bit_sum_4;
  input [3:0] idata;
  reg [2:0] ocnt;
  begin
    ocnt =
        ( idata[0]  
      +  idata[1]  
      +  idata[2] ) 
      +  idata[3]  ;
    fun_bit_sum_4 = ocnt;
  end
endfunction
function [2:0] fun_bit_sum_4;

  input [3:0] idata;
  reg [2:0] ocnt;
  begin
    ocnt =
        ( idata[0]  
      +  idata[1]  
      +  idata[2] ) 
      +  idata[3]  ;
    fun_bit_sum_4 = ocnt;
  end
endfunction