data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v
1: b'%Error: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:17: Cannot find file containing module: \'Memory\'\n    Memory mem3(clk, addr_div, 1\'b1, ena[3], din_shift[31:24], dout_o[31:24]);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Memory\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Memory.v\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Memory.sv\n             Memory\n             Memory.v\n             Memory.sv\n             obj_dir/Memory\n             obj_dir/Memory.v\n             obj_dir/Memory.sv\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:18: Cannot find file containing module: \'Memory\'\n    Memory mem2(clk, addr_div, 1\'b1, ena[2], din_shift[23:16], dout_o[23:16]);\n    ^~~~~~\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:19: Cannot find file containing module: \'Memory\'\n    Memory mem1(clk, addr_div, 1\'b1, ena[1], din_shift[15:08], dout_o[15:08]);\n    ^~~~~~\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:20: Cannot find file containing module: \'Memory\'\n    Memory mem0(clk, addr_div, 1\'b1, ena[0], din_shift[07:00], dout_o[07:00]);\n    ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:25: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'width\' generates 2 bits.\n                                                                        : ... In instance RAM\n    assign err = width == 2\'d2 | (width & addr_mod) != 2\'d0;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:25: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance RAM\n    assign err = width == 2\'d2 | (width & addr_mod) != 2\'d0;\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:26: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'width\' generates 2 bits.\n                                                                        : ... In instance RAM\n    assign ena = {4{wea & ~err}} & (4\'hf << addr_mod) & ~(4\'hf << (addr_mod + width + 32\'d1));\n                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:28: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'width\' generates 2 bits.\n                                                                        : ... In instance RAM\n    assign hi = (width + 5\'d1) << 32\'d3;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/RAM.v:28: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                        : ... In instance RAM\n    assign hi = (width + 5\'d1) << 32\'d3;\n                       ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module RAM(clk, addr, wea, width, sign, din, dout, err);
    input clk;
    input [31:0] addr;
    input wea;
    input [1:0] width;
    input sign;
    input [31:0] din;
    output [31:0] dout;
    output err;

    wire [31:0] addr_div, addr_mod;
    wire [31:0] din_shift;
    wire [31:0] dout_o;
    wire [31:0] dout_shift;
    wire [31:0] hi;
    wire [3:0] ena;
    Memory mem3(clk, addr_div, 1'b1, ena[3], din_shift[31:24], dout_o[31:24]);
    Memory mem2(clk, addr_div, 1'b1, ena[2], din_shift[23:16], dout_o[23:16]);
    Memory mem1(clk, addr_div, 1'b1, ena[1], din_shift[15:08], dout_o[15:08]);
    Memory mem0(clk, addr_div, 1'b1, ena[0], din_shift[07:00], dout_o[07:00]);

    assign addr_div = addr >> 32'd2;
    assign addr_mod = addr & 32'b11;
    assign din_shift = din << (addr_mod << 32'd3);
    assign err = width == 2'd2 | (width & addr_mod) != 2'd0;
    assign ena = {4{wea & ~err}} & (4'hf << addr_mod) & ~(4'hf << (addr_mod + width + 32'd1));
    assign dout_shift = dout_o >> (addr_mod << 32'd3);
    assign hi = (width + 5'd1) << 32'd3;
    assign dout = wea ? 32'hz : dout_shift & ~(32'hffffffff << hi) | {32{sign & dout_shift[hi - 1]}} << hi;
endmodule
module RAM(clk, addr, wea, width, sign, din, dout, err);

    input clk;
    input [31:0] addr;
    input wea;
    input [1:0] width;
    input sign;
    input [31:0] din;
    output [31:0] dout;
    output err;

    wire [31:0] addr_div, addr_mod;
    wire [31:0] din_shift;
    wire [31:0] dout_o;
    wire [31:0] dout_shift;
    wire [31:0] hi;
    wire [3:0] ena;
    Memory mem3(clk, addr_div, 1'b1, ena[3], din_shift[31:24], dout_o[31:24]);
    Memory mem2(clk, addr_div, 1'b1, ena[2], din_shift[23:16], dout_o[23:16]);
    Memory mem1(clk, addr_div, 1'b1, ena[1], din_shift[15:08], dout_o[15:08]);
    Memory mem0(clk, addr_div, 1'b1, ena[0], din_shift[07:00], dout_o[07:00]);

    assign addr_div = addr >> 32'd2;
    assign addr_mod = addr & 32'b11;
    assign din_shift = din << (addr_mod << 32'd3);
    assign err = width == 2'd2 | (width & addr_mod) != 2'd0;
    assign ena = {4{wea & ~err}} & (4'hf << addr_mod) & ~(4'hf << (addr_mod + width + 32'd1));
    assign dout_shift = dout_o >> (addr_mod << 32'd3);
    assign hi = (width + 5'd1) << 32'd3;
    assign dout = wea ? 32'hz : dout_shift & ~(32'hffffffff << hi) | {32{sign & dout_shift[hi - 1]}} << hi;
endmodule