data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Lemmings4/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Lemmings4,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Lemmings4/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  wire [3:0] activity;
  wire aaah;

  reg clk = 1'd1;
  reg areset = 1'd0;
  reg bump_left = 1'd0;
  reg bump_right = 1'd0;
  reg ground = 1'd1;
  reg dig = 1'd0;

  localparam ITERATIONS = 2000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #20 dig = 1'b1;
    #10 dig = 1'b0;
    #10 bump_left = 1'b1;
    #10 bump_left = 1'b0;
    #10 ground = 1'b0;
    #30 ground = 1'b1;
    dig = 1'b1;
    #10 dig = 1'b0;
    #50;
    #10 bump_right = 1'b1;
    #10 bump_right = 1'b0;
    #50;
    #10 ground = 1'b0;
    #200 ground = 1'b1;
    #50;
    #10 ground = 1'b0;
    #210 ground = 1'b1;
    #50;
    #10 ground = 1'b0;
    #300 ground = 1'b1;
  end

  initial begin
    #72 areset = 1'b1;
    #1 areset = 1'b0;
  end

  initial begin
    #892 areset = 1'b1;
    #1 areset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .bump_left(bump_left),
      .bump_right(bump_right),
      .ground(ground),
      .dig(dig),
      .walk_left(activity[1]),
      .walk_right(activity[0]),
      .aaah(activity[2]),
      .digging(activity[3])
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire [3:0] activity;
  wire aaah;

  reg clk = 1'd1;
  reg areset = 1'd0;
  reg bump_left = 1'd0;
  reg bump_right = 1'd0;
  reg ground = 1'd1;
  reg dig = 1'd0;

  localparam ITERATIONS = 2000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #20 dig = 1'b1;
    #10 dig = 1'b0;
    #10 bump_left = 1'b1;
    #10 bump_left = 1'b0;
    #10 ground = 1'b0;
    #30 ground = 1'b1;
    dig = 1'b1;
    #10 dig = 1'b0;
    #50;
    #10 bump_right = 1'b1;
    #10 bump_right = 1'b0;
    #50;
    #10 ground = 1'b0;
    #200 ground = 1'b1;
    #50;
    #10 ground = 1'b0;
    #210 ground = 1'b1;
    #50;
    #10 ground = 1'b0;
    #300 ground = 1'b1;
  end

  initial begin
    #72 areset = 1'b1;
    #1 areset = 1'b0;
  end

  initial begin
    #892 areset = 1'b1;
    #1 areset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .bump_left(bump_left),
      .bump_right(bump_right),
      .ground(ground),
      .dig(dig),
      .walk_left(activity[1]),
      .walk_right(activity[0]),
      .aaah(activity[2]),
      .digging(activity[3])
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule