data/full_repos/permissive/521337848/Hardware/procesor/insideTimer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/insideTimer.v:49: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'div_input\'\nmodule div_input(\n       ^~~~~~~~~\n                                                                                          : ... Top module \'timer\'\nmodule timer (\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module div_input(
	input clk,
	input rst,
	output reg clkm
);

reg[15:0] f_licz;
reg[15:0] n_licz;
reg clka = 0;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		clka <= 0;
	end 
	else begin
		clka <= clkm;
	end
end

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_licz <= 0;
	end 
	else begin
		f_licz <= n_licz;
	end
end

always@(*)begin
	n_licz = f_licz + 15'b1;
	
	if(f_licz == 50000)begin
		n_licz = 0;
	end
end

always@(*)begin
	clkm = 0;
	
	if(f_licz == 50000)begin
		clkm = 1;
	end
	
end

endmodule
module div_input(
	input clk,
	input rst,
	output reg clkm
);


reg[15:0] f_licz;
reg[15:0] n_licz;
reg clka = 0;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		clka <= 0;
	end 
	else begin
		clka <= clkm;
	end
end

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_licz <= 0;
	end 
	else begin
		f_licz <= n_licz;
	end
end

always@(*)begin
	n_licz = f_licz + 15'b1;
	
	if(f_licz == 50000)begin
		n_licz = 0;
	end
end

always@(*)begin
	clkm = 0;
	
	if(f_licz == 50000)begin
		clkm = 1;
	end
	
end

endmodule