data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_rx_glue.v
data/verilator_xmls/62df24ac-d74e-4626-8f15-74583a3a0da4.xml
module dsp_rx_glue
#(

    parameter DSPNO = 0,


    parameter WIDTH = 24
)
(

    input clock, input reset, input clear, input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    input [WIDTH-1:0] frontend_i,
    input [WIDTH-1:0] frontend_q,


    output [WIDTH-1:0] ddc_in_i,
    output [WIDTH-1:0] ddc_in_q,


    input [31:0] ddc_out_sample,
    input ddc_out_strobe,
    output ddc_out_enable,


    output [31:0] bb_sample,
    output bb_strobe,


    output [31:0] debug
);

    generate
        if (DSPNO==0) begin
            `ifndef RX_DSP0_MODULE
            assign ddc_in_i = frontend_i;
            assign ddc_in_q = frontend_q;
            assign bb_sample = ddc_out_sample;
            assign bb_strobe = ddc_out_strobe;
            assign ddc_out_enable = enable;
            `else
            `RX_DSP0_MODULE #(.WIDTH(WIDTH)) rx_dsp0_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
        else begin
            `ifndef RX_DSP1_MODULE
            assign ddc_in_i = frontend_i;
            assign ddc_in_q = frontend_q;
            assign bb_sample = ddc_out_sample;
            assign bb_strobe = ddc_out_strobe;
            assign ddc_out_enable = enable;
            `else
            `RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
    endgenerate

endmodule
module dsp_rx_glue
#(

    parameter DSPNO = 0,


    parameter WIDTH = 24
)
(

    input clock, input reset, input clear, input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    input [WIDTH-1:0] frontend_i,
    input [WIDTH-1:0] frontend_q,


    output [WIDTH-1:0] ddc_in_i,
    output [WIDTH-1:0] ddc_in_q,


    input [31:0] ddc_out_sample,
    input ddc_out_strobe,
    output ddc_out_enable,


    output [31:0] bb_sample,
    output bb_strobe,


    output [31:0] debug
);


    generate
        if (DSPNO==0) begin
            `ifndef RX_DSP0_MODULE
            assign ddc_in_i = frontend_i;
            assign ddc_in_q = frontend_q;
            assign bb_sample = ddc_out_sample;
            assign bb_strobe = ddc_out_strobe;
            assign ddc_out_enable = enable;
            `else
            `RX_DSP0_MODULE #(.WIDTH(WIDTH)) rx_dsp0_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
        else begin
            `ifndef RX_DSP1_MODULE
            assign ddc_in_i = frontend_i;
            assign ddc_in_q = frontend_q;
            assign bb_sample = ddc_out_sample;
            assign bb_strobe = ddc_out_strobe;
            assign ddc_out_enable = enable;
            `else
            `RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
                .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
    endgenerate

endmodule