data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count_clock_2/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826\n             Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count_clock_2,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count_clock_2/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [23:0] Q
);

  reg [16:0] secondcounter;
  wire [5:0] seconds;
  wire [5:0] minutes;
  wire [4:0] hours;

  always @(posedge clk) begin
    if (reset) secondcounter = 1'd0;
    else if (enable) begin
      if (secondcounter == 17'd86399)
        secondcounter <= 1'd0;
      else
        secondcounter = secondcounter + 1'd1;
    end
  end

  assign seconds = secondcounter % 60;
  assign minutes = secondcounter / 60 % 60;
  assign hours = secondcounter / 60 / 60 % 60;

  assign Q[3:0] = seconds % 10;
  assign Q[7:4] = seconds / 10;
  assign Q[11:8] = minutes % 10;
  assign Q[15:12] = minutes / 10;
  assign Q[19:16] = hours % 10;
  assign Q[23:20] = hours / 10;

endmodule
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [23:0] Q
);


  reg [16:0] secondcounter;
  wire [5:0] seconds;
  wire [5:0] minutes;
  wire [4:0] hours;

  always @(posedge clk) begin
    if (reset) secondcounter = 1'd0;
    else if (enable) begin
      if (secondcounter == 17'd86399)
        secondcounter <= 1'd0;
      else
        secondcounter = secondcounter + 1'd1;
    end
  end

  assign seconds = secondcounter % 60;
  assign minutes = secondcounter / 60 % 60;
  assign hours = secondcounter / 60 / 60 % 60;

  assign Q[3:0] = seconds % 10;
  assign Q[7:4] = seconds / 10;
  assign Q[11:8] = minutes % 10;
  assign Q[15:12] = minutes / 10;
  assign Q[19:16] = hours % 10;
  assign Q[23:20] = hours / 10;

endmodule