data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:14: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t%h\\t%h\\t%h\\t", enable, opEn, pc, in, out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; opEn=0; pc=12\'h0F0; in=12\'hA00;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; opEn=1; pc=12\'h0F0; in=12\'hA00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; opEn=0; pc=12\'h0F0; in=12\'hA00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; opEn=1; pc=12\'h0F0; in=12\'hA00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/pc_add/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    reg enable;
    reg opEn;
    reg [11:0] pc;
    reg [11:0] in;
    wire [11:0] out;

    pc_add PCADD(enable, opEn, pc, in, out);

    initial begin
        enable=0; opEn=0; pc=12'h000; in=12'h000;

        $display("\nenable\topEn\tpc\tin\tout");
        $monitor("%b\t%b\t%h\t%h\t%h\t", enable, opEn, pc, in, out);

        #2 enable=0; opEn=0; pc=12'h0F0; in=12'hA00;
        #2 enable=0; opEn=1; pc=12'h0F0; in=12'hA00;
        #2 enable=1; opEn=0; pc=12'h0F0; in=12'hA00;
        #2 enable=1; opEn=1; pc=12'h0F0; in=12'hA00;

        #2 $finish;
    end


endmodule
module testbench();

    reg enable;
    reg opEn;
    reg [11:0] pc;
    reg [11:0] in;
    wire [11:0] out;

    pc_add PCADD(enable, opEn, pc, in, out);

    initial begin
        enable=0; opEn=0; pc=12'h000; in=12'h000;

        $display("\nenable\topEn\tpc\tin\tout");
        $monitor("%b\t%b\t%h\t%h\t%h\t", enable, opEn, pc, in, out);

        #2 enable=0; opEn=0; pc=12'h0F0; in=12'hA00;
        #2 enable=0; opEn=1; pc=12'h0F0; in=12'hA00;
        #2 enable=1; opEn=0; pc=12'h0F0; in=12'hA00;
        #2 enable=1; opEn=1; pc=12'h0F0; in=12'hA00;

        #2 $finish;
    end


endmodule