data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:21: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\nmodule variable_latency_interconnect import tcdm_interconnect_pkg::topo_e; #(\n                                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:24: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned NumOut            = 64,                     \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:25: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned AddrWidth         = 32,                     \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:26: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned DataWidth         = 32,                     \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:27: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned BeWidth           = DataWidth/8,            \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:28: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned AddrMemWidth      = 12,                     \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:29: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter bit AxiVldRdy                  = 1'b1,                   \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:33: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter logic [63:0] SpillRegisterReq  = 64'h0,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:34: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter logic [63:0] SpillRegisterResp = 64'h0,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:35: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter bit FallThroughRegister        = 1'b0,                   \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:38: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned ByteOffWidth      = $clog2(DataWidth-1)-3,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:40: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter topo_e Topology = tcdm_interconnect_pkg::LIC,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:43: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:45: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                                rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:47: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0]                    req_valid_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:48: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0]                    req_ready_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:49: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][AddrWidth-1:0]     req_tgt_addr_i,   \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:50: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0]                    req_wen_i,        \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:51: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][DataWidth-1:0]     req_wdata_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:52: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][BeWidth-1:0]       req_be_i,         \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:53: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0]                    resp_valid_o,     \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:54: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0]                    resp_ready_i,     \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:55: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0][DataWidth-1:0]     resp_rdata_o,     \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:57: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0]                   req_valid_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:58: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumOut-1:0]                   req_ready_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:59: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0][NumInLog2-1:0]    req_ini_addr_o,   \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:60: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0][AddrMemWidth-1:0] req_tgt_addr_o,   \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:61: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0]                   req_wen_o,        \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:62: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0][DataWidth-1:0]    req_wdata_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:63: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0][BeWidth-1:0]      req_be_o,         \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:64: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumOut-1:0]                   resp_valid_i,     \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:65: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumOut-1:0]                   resp_ready_o,     \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:66: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumOut-1:0][NumInLog2-1:0]    resp_ini_addr_i,  \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:67: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumOut-1:0][DataWidth-1:0]    resp_rdata_i      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:68: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:85: syntax error, unexpected ::, expecting ':'\n  logic [NumIn-1:0][cf_math_pkg::idx_width(NumOut)-1:0] tgt_sel;\n                               ^~\n                                                                                                                                                             : ... Perhaps 'cf_math_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv:197: syntax error, unexpected assign\n    assign req_rr  = '0;\n    ^~~~~~\n%Error: Exiting due to 37 error(s)\n"
module variable_latency_interconnect import tcdm_interconnect_pkg::topo_e; #(

  parameter int unsigned NumIn             = 32,
  parameter int unsigned NumOut            = 64,
  parameter int unsigned AddrWidth         = 32,
  parameter int unsigned DataWidth         = 32,
  parameter int unsigned BeWidth           = DataWidth/8,
  parameter int unsigned AddrMemWidth      = 12,
  parameter bit AxiVldRdy                  = 1'b1,



  parameter logic [63:0] SpillRegisterReq  = 64'h0,
  parameter logic [63:0] SpillRegisterResp = 64'h0,
  parameter bit FallThroughRegister        = 1'b0,


  parameter int unsigned ByteOffWidth      = $clog2(DataWidth-1)-3,

  parameter topo_e Topology = tcdm_interconnect_pkg::LIC,

  parameter int unsigned NumInLog2         = NumIn == 1 ? 1 : $clog2(NumIn)
) (
  input  logic                                clk_i,
  input  logic                                rst_ni,

  input  logic [NumIn-1:0]                    req_valid_i,
  output logic [NumIn-1:0]                    req_ready_o,
  input  logic [NumIn-1:0][AddrWidth-1:0]     req_tgt_addr_i,
  input  logic [NumIn-1:0]                    req_wen_i,
  input  logic [NumIn-1:0][DataWidth-1:0]     req_wdata_i,
  input  logic [NumIn-1:0][BeWidth-1:0]       req_be_i,
  output logic [NumIn-1:0]                    resp_valid_o,
  input  logic [NumIn-1:0]                    resp_ready_i,
  output logic [NumIn-1:0][DataWidth-1:0]     resp_rdata_o,

  output logic [NumOut-1:0]                   req_valid_o,
  input  logic [NumOut-1:0]                   req_ready_i,
  output logic [NumOut-1:0][NumInLog2-1:0]    req_ini_addr_o,
  output logic [NumOut-1:0][AddrMemWidth-1:0] req_tgt_addr_o,
  output logic [NumOut-1:0]                   req_wen_o,
  output logic [NumOut-1:0][DataWidth-1:0]    req_wdata_o,
  output logic [NumOut-1:0][BeWidth-1:0]      req_be_o,
  input  logic [NumOut-1:0]                   resp_valid_i,
  output logic [NumOut-1:0]                   resp_ready_o,
  input  logic [NumOut-1:0][NumInLog2-1:0]    resp_ini_addr_i,
  input  logic [NumOut-1:0][DataWidth-1:0]    resp_rdata_i
);





  localparam int unsigned NumOutLog2      = $clog2(NumOut);
  localparam int unsigned IniAggDataWidth = 1 + BeWidth + AddrMemWidth + DataWidth;



  logic [NumIn-1:0][IniAggDataWidth-1:0]  data_agg_in;
  logic [NumOut-1:0][IniAggDataWidth-1:0] data_agg_out;
  logic [NumIn-1:0][cf_math_pkg::idx_width(NumOut)-1:0] tgt_sel;

  for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs

    if (NumIn == 1) begin
      assign tgt_sel[j] = '0;
    end else begin
      if (NumOut == 1) begin
        assign tgt_sel[j] = 0;
      end else begin
        assign tgt_sel[j] = req_tgt_addr_i[j][ByteOffWidth +: NumOutLog2];
      end
    end


    assign data_agg_in[j] = {req_wen_i[j], req_be_i[j], req_tgt_addr_i[j][ByteOffWidth + NumOutLog2 +: AddrMemWidth], req_wdata_i[j]};
  end


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
    assign {req_wen_o[k], req_be_o[k], req_tgt_addr_o[k], req_wdata_o[k]} = data_agg_out[k];
  end




  if (NumIn < 2 && NumOut < 2) begin : gen_con
    assign req_valid_o    = req_valid_i;
    assign req_ready_o    = req_ready_i;
    assign req_ini_addr_o = '0;
    assign data_agg_out   = data_agg_in;
    assign resp_valid_o   = resp_valid_i;
    assign resp_ready_o   = resp_ready_i;
    assign resp_rdata_o   = resp_rdata_i;

  end else if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic
    full_duplex_xbar #(
      .NumIn              (NumIn               ),
      .NumOut             (NumOut              ),
      .ReqDataWidth       (IniAggDataWidth     ),
      .RespDataWidth      (DataWidth           ),
      .AxiVldRdy          (AxiVldRdy           ),
      .SpillRegisterReq   (SpillRegisterReq[0] ),
      .SpillRegisterResp  (SpillRegisterResp[0]),
      .FallThroughRegister(FallThroughRegister )
    ) i_xbar (
      .clk_i          (clk_i          ),
      .rst_ni         (rst_ni         ),

      .req_rr_i       ('0             ),
      .resp_rr_i      ('0             ),

      .req_valid_i    (req_valid_i    ),
      .req_ready_o    (req_ready_o    ),
      .req_tgt_addr_i (tgt_sel        ),
      .req_wdata_i    (data_agg_in    ),
      .resp_valid_o   (resp_valid_o   ),
      .resp_rdata_o   (resp_rdata_o   ),
      .resp_ready_i   (resp_ready_i   ),

      .req_valid_o    (req_valid_o    ),
      .req_ini_addr_o (req_ini_addr_o ),
      .req_ready_i    (req_ready_i    ),
      .req_wdata_o    (data_agg_out   ),
      .resp_valid_i   (resp_valid_i   ),
      .resp_ready_o   (resp_ready_o   ),
      .resp_ini_addr_i(resp_ini_addr_i),
      .resp_rdata_i   (resp_rdata_i   )
    );
  end


  else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin: gen_bfly
    localparam int unsigned Radix = 2**Topology;

    logic [$clog2(NumOut)-1:0] req_rr ;
    logic [$clog2(NumOut)-1:0] resp_rr;








    assign req_rr  = '0;
    assign resp_rr = '0;

    variable_latency_bfly_net #(
      .NumIn              (NumIn               ),
      .NumOut             (NumOut              ),
      .DataWidth          (IniAggDataWidth     ),
      .Radix              (Radix               ),
      .ExtPrio            (1'b0                ),
      .SpillRegister      (SpillRegisterReq    ),
      .AxiVldRdy          (AxiVldRdy           ),
      .FallThroughRegister(FallThroughRegister )
    ) i_req_bfly_net (
      .clk_i     (clk_i          ),
      .rst_ni    (rst_ni         ),

      .rr_i      (req_rr         ),

      .valid_i   (req_valid_i    ),
      .ready_o   (req_ready_o    ),
      .tgt_addr_i(tgt_sel        ),
      .wdata_i   (data_agg_in    ),

      .valid_o   (req_valid_o    ),
      .ini_addr_o(req_ini_addr_o ),
      .ready_i   (req_ready_i    ),
      .wdata_o   (data_agg_out   )
    );

    variable_latency_bfly_net #(
      .NumIn              (NumOut              ),
      .NumOut             (NumIn               ),
      .DataWidth          (DataWidth           ),
      .Radix              (Radix               ),
      .ExtPrio            (1'b0                ),
      .SpillRegister      (SpillRegisterResp   ),
      .AxiVldRdy          (AxiVldRdy           ),
      .FallThroughRegister(FallThroughRegister )
    ) i_resp_bfly_net (
      .clk_i     (clk_i          ),
      .rst_ni    (rst_ni         ),

      .rr_i      (resp_rr        ),

      .valid_i   (resp_valid_i   ),
      .ready_o   (resp_ready_o   ),
      .tgt_addr_i(resp_ini_addr_i),
      .wdata_i   (resp_rdata_i   ),

      .valid_o   (resp_valid_o   ),
      .ready_i   (resp_ready_i   ),
      .ini_addr_o(),
      .wdata_o   (resp_rdata_o   )
    );
  end


  else begin: gen_unknown
    $fatal(1, "[variable_latency_interconnect] Unknown TCDM configuration %d.", Topology);
  end



  if (NumOut != 1 && AddrMemWidth + NumOutLog2 > AddrWidth)
    $fatal(1, "[variable_latency_interconnect] Address is not wide enough to accommodate the requested TCDM configuration.");

  if (Topology != tcdm_interconnect_pkg::LIC && NumOut < NumIn)
    $fatal(1, "[variable_latency_interconnect] NumOut < NumIn is not supported with the chosen TCDM configuration.");

endmodule
module variable_latency_interconnect import tcdm_interconnect_pkg::topo_e;
 #(

  parameter int unsigned NumIn             = 32,
  parameter int unsigned NumOut            = 64,
  parameter int unsigned AddrWidth         = 32,
  parameter int unsigned DataWidth         = 32,
  parameter int unsigned BeWidth           = DataWidth/8,
  parameter int unsigned AddrMemWidth      = 12,
  parameter bit AxiVldRdy                  = 1'b1,



  parameter logic [63:0] SpillRegisterReq  = 64'h0,
  parameter logic [63:0] SpillRegisterResp = 64'h0,
  parameter bit FallThroughRegister        = 1'b0,


  parameter int unsigned ByteOffWidth      = $clog2(DataWidth-1)-3,

  parameter topo_e Topology = tcdm_interconnect_pkg::LIC,

  parameter int unsigned NumInLog2         = NumIn == 1 ? 1 : $clog2(NumIn)
) (
  input  logic                                clk_i,
  input  logic                                rst_ni,

  input  logic [NumIn-1:0]                    req_valid_i,
  output logic [NumIn-1:0]                    req_ready_o,
  input  logic [NumIn-1:0][AddrWidth-1:0]     req_tgt_addr_i,
  input  logic [NumIn-1:0]                    req_wen_i,
  input  logic [NumIn-1:0][DataWidth-1:0]     req_wdata_i,
  input  logic [NumIn-1:0][BeWidth-1:0]       req_be_i,
  output logic [NumIn-1:0]                    resp_valid_o,
  input  logic [NumIn-1:0]                    resp_ready_i,
  output logic [NumIn-1:0][DataWidth-1:0]     resp_rdata_o,

  output logic [NumOut-1:0]                   req_valid_o,
  input  logic [NumOut-1:0]                   req_ready_i,
  output logic [NumOut-1:0][NumInLog2-1:0]    req_ini_addr_o,
  output logic [NumOut-1:0][AddrMemWidth-1:0] req_tgt_addr_o,
  output logic [NumOut-1:0]                   req_wen_o,
  output logic [NumOut-1:0][DataWidth-1:0]    req_wdata_o,
  output logic [NumOut-1:0][BeWidth-1:0]      req_be_o,
  input  logic [NumOut-1:0]                   resp_valid_i,
  output logic [NumOut-1:0]                   resp_ready_o,
  input  logic [NumOut-1:0][NumInLog2-1:0]    resp_ini_addr_i,
  input  logic [NumOut-1:0][DataWidth-1:0]    resp_rdata_i
);





  localparam int unsigned NumOutLog2      = $clog2(NumOut);
  localparam int unsigned IniAggDataWidth = 1 + BeWidth + AddrMemWidth + DataWidth;



  logic [NumIn-1:0][IniAggDataWidth-1:0]  data_agg_in;
  logic [NumOut-1:0][IniAggDataWidth-1:0] data_agg_out;
  logic [NumIn-1:0][cf_math_pkg::idx_width(NumOut)-1:0] tgt_sel;

  for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs

    if (NumIn == 1) begin
      assign tgt_sel[j] = '0;
    end else begin
      if (NumOut == 1) begin
        assign tgt_sel[j] = 0;
      end else begin
        assign tgt_sel[j] = req_tgt_addr_i[j][ByteOffWidth +: NumOutLog2];
      end
    end


    assign data_agg_in[j] = {req_wen_i[j], req_be_i[j], req_tgt_addr_i[j][ByteOffWidth + NumOutLog2 +: AddrMemWidth], req_wdata_i[j]};
  end


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
    assign {req_wen_o[k], req_be_o[k], req_tgt_addr_o[k], req_wdata_o[k]} = data_agg_out[k];
  end




  if (NumIn < 2 && NumOut < 2) begin : gen_con
    assign req_valid_o    = req_valid_i;
    assign req_ready_o    = req_ready_i;
    assign req_ini_addr_o = '0;
    assign data_agg_out   = data_agg_in;
    assign resp_valid_o   = resp_valid_i;
    assign resp_ready_o   = resp_ready_i;
    assign resp_rdata_o   = resp_rdata_i;

  end else if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic
    full_duplex_xbar #(
      .NumIn              (NumIn               ),
      .NumOut             (NumOut              ),
      .ReqDataWidth       (IniAggDataWidth     ),
      .RespDataWidth      (DataWidth           ),
      .AxiVldRdy          (AxiVldRdy           ),
      .SpillRegisterReq   (SpillRegisterReq[0] ),
      .SpillRegisterResp  (SpillRegisterResp[0]),
      .FallThroughRegister(FallThroughRegister )
    ) i_xbar (
      .clk_i          (clk_i          ),
      .rst_ni         (rst_ni         ),

      .req_rr_i       ('0             ),
      .resp_rr_i      ('0             ),

      .req_valid_i    (req_valid_i    ),
      .req_ready_o    (req_ready_o    ),
      .req_tgt_addr_i (tgt_sel        ),
      .req_wdata_i    (data_agg_in    ),
      .resp_valid_o   (resp_valid_o   ),
      .resp_rdata_o   (resp_rdata_o   ),
      .resp_ready_i   (resp_ready_i   ),

      .req_valid_o    (req_valid_o    ),
      .req_ini_addr_o (req_ini_addr_o ),
      .req_ready_i    (req_ready_i    ),
      .req_wdata_o    (data_agg_out   ),
      .resp_valid_i   (resp_valid_i   ),
      .resp_ready_o   (resp_ready_o   ),
      .resp_ini_addr_i(resp_ini_addr_i),
      .resp_rdata_i   (resp_rdata_i   )
    );
  end


  else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin: gen_bfly
    localparam int unsigned Radix = 2**Topology;

    logic [$clog2(NumOut)-1:0] req_rr ;
    logic [$clog2(NumOut)-1:0] resp_rr;








    assign req_rr  = '0;
    assign resp_rr = '0;

    variable_latency_bfly_net #(
      .NumIn              (NumIn               ),
      .NumOut             (NumOut              ),
      .DataWidth          (IniAggDataWidth     ),
      .Radix              (Radix               ),
      .ExtPrio            (1'b0                ),
      .SpillRegister      (SpillRegisterReq    ),
      .AxiVldRdy          (AxiVldRdy           ),
      .FallThroughRegister(FallThroughRegister )
    ) i_req_bfly_net (
      .clk_i     (clk_i          ),
      .rst_ni    (rst_ni         ),

      .rr_i      (req_rr         ),

      .valid_i   (req_valid_i    ),
      .ready_o   (req_ready_o    ),
      .tgt_addr_i(tgt_sel        ),
      .wdata_i   (data_agg_in    ),

      .valid_o   (req_valid_o    ),
      .ini_addr_o(req_ini_addr_o ),
      .ready_i   (req_ready_i    ),
      .wdata_o   (data_agg_out   )
    );

    variable_latency_bfly_net #(
      .NumIn              (NumOut              ),
      .NumOut             (NumIn               ),
      .DataWidth          (DataWidth           ),
      .Radix              (Radix               ),
      .ExtPrio            (1'b0                ),
      .SpillRegister      (SpillRegisterResp   ),
      .AxiVldRdy          (AxiVldRdy           ),
      .FallThroughRegister(FallThroughRegister )
    ) i_resp_bfly_net (
      .clk_i     (clk_i          ),
      .rst_ni    (rst_ni         ),

      .rr_i      (resp_rr        ),

      .valid_i   (resp_valid_i   ),
      .ready_o   (resp_ready_o   ),
      .tgt_addr_i(resp_ini_addr_i),
      .wdata_i   (resp_rdata_i   ),

      .valid_o   (resp_valid_o   ),
      .ready_i   (resp_ready_i   ),
      .ini_addr_o(),
      .wdata_o   (resp_rdata_o   )
    );
  end


  else begin: gen_unknown
    $fatal(1, "[variable_latency_interconnect] Unknown TCDM configuration %d.", Topology);
  end



  if (NumOut != 1 && AddrMemWidth + NumOutLog2 > AddrWidth)
    $fatal(1, "[variable_latency_interconnect] Address is not wide enough to accommodate the requested TCDM configuration.");

  if (Topology != tcdm_interconnect_pkg::LIC && NumOut < NumIn)
    $fatal(1, "[variable_latency_interconnect] NumOut < NumIn is not supported with the chosen TCDM configuration.");

endmodule