data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/COUNTER_NEXT_ROW.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/COUNTER_NEXT_ROW.v:59: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'COUNTER_NEXT_ROW_Stride\' generates 4 bits.\n                                                                                                                             : ... In instance COUNTER_NEXT_ROW\n   counter<=counter +COUNTER_NEXT_ROW_Stride;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/COUNTER_NEXT_ROW.v:65: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'COUNTER_NEXT_ROW_Offset\' generates 4 bits.\n                                                                                                                             : ... In instance COUNTER_NEXT_ROW\nassign COUNTER_NEXT_ROW_Next_Row=counter+COUNTER_NEXT_ROW_Offset;\n                                        ^\n%Error: Exiting due to 2 warning(s)\n'
module COUNTER_NEXT_ROW #(parameter BITWIDTH_ROW=4, parameter BITWIDTH_IF_ROWS=10, parameter BITWIDTH_STRIDE=4)(



COUNTER_NEXT_ROW_clk,
COUNTER_NEXT_ROW_Stride,
COUNTER_NEXT_ROW_Offset,
COUNTER_NEXT_ROW_En,
COUNTER_NEXT_ROW_Clr,


COUNTER_NEXT_ROW_Next_Row
);



input COUNTER_NEXT_ROW_clk;
input [BITWIDTH_STRIDE-1:0] COUNTER_NEXT_ROW_Stride;
input [BITWIDTH_ROW-1:0] COUNTER_NEXT_ROW_Offset;
input COUNTER_NEXT_ROW_En;
input COUNTER_NEXT_ROW_Clr;
output [BITWIDTH_IF_ROWS-1:0] COUNTER_NEXT_ROW_Next_Row;




reg [BITWIDTH_IF_ROWS-1:0] counter;





always@(posedge COUNTER_NEXT_ROW_clk or negedge COUNTER_NEXT_ROW_Clr)
begin
		if(!COUNTER_NEXT_ROW_Clr)
			counter<=0;
		else if(COUNTER_NEXT_ROW_En)
			counter<=counter +COUNTER_NEXT_ROW_Stride;
end




assign COUNTER_NEXT_ROW_Next_Row=counter+COUNTER_NEXT_ROW_Offset;

endmodule
module COUNTER_NEXT_ROW #(parameter BITWIDTH_ROW=4, parameter BITWIDTH_IF_ROWS=10, parameter BITWIDTH_STRIDE=4)(



COUNTER_NEXT_ROW_clk,
COUNTER_NEXT_ROW_Stride,
COUNTER_NEXT_ROW_Offset,
COUNTER_NEXT_ROW_En,
COUNTER_NEXT_ROW_Clr,


COUNTER_NEXT_ROW_Next_Row
);




input COUNTER_NEXT_ROW_clk;
input [BITWIDTH_STRIDE-1:0] COUNTER_NEXT_ROW_Stride;
input [BITWIDTH_ROW-1:0] COUNTER_NEXT_ROW_Offset;
input COUNTER_NEXT_ROW_En;
input COUNTER_NEXT_ROW_Clr;
output [BITWIDTH_IF_ROWS-1:0] COUNTER_NEXT_ROW_Next_Row;




reg [BITWIDTH_IF_ROWS-1:0] counter;





always@(posedge COUNTER_NEXT_ROW_clk or negedge COUNTER_NEXT_ROW_Clr)
begin
		if(!COUNTER_NEXT_ROW_Clr)
			counter<=0;
		else if(COUNTER_NEXT_ROW_En)
			counter<=counter +COUNTER_NEXT_ROW_Stride;
end




assign COUNTER_NEXT_ROW_Next_Row=counter+COUNTER_NEXT_ROW_Offset;

endmodule