data/full_repos/permissive/501791642/src/volume_rom.v
data/verilator_xmls/55130d9c-9b9f-4b59-a6e6-c4476418d47d.xml
module volume_rom (
	input CLK,
	input CE,
	input [7:0] SAMPLE,
	input [6:0] VEL,
	output reg [7:0] SAMPLE_OUT
);

   	reg [7:0] volume_rom [(2**15)-1:0];
   
   	initial
		$readmemh("volume_rom.mem", volume_rom );

   	always @(posedge CLK)
    	if (CE)
        	 SAMPLE_OUT <= volume_rom[{SAMPLE,VEL}];

endmodule
module volume_rom (
	input CLK,
	input CE,
	input [7:0] SAMPLE,
	input [6:0] VEL,
	output reg [7:0] SAMPLE_OUT
);


   	reg [7:0] volume_rom [(2**15)-1:0];
   
   	initial
		$readmemh("volume_rom.mem", volume_rom );

   	always @(posedge CLK)
    	if (CE)
        	 SAMPLE_OUT <= volume_rom[{SAMPLE,VEL}];

endmodule