data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:10: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\n  import prim_pad_wrapper_pkg::*;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output logic       in_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:24: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic       in_raw_o,  \n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:25: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input              ie_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:32: Define or directive not defined: '`ASSERT_INIT'\n  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:36: syntax error, unexpected assign\n  assign unused_sigs = ^{attr_i.slew_rate,\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:49: syntax error, unexpected assign\n    assign unused_sigs = ^{out_i,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:55: syntax error, unexpected assign\n    assign in_raw_o = (ie_i) ? in  : 1'bz;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:68: syntax error, unexpected assign\n    assign in_raw_o = (ie_i) ? in  : 1'bz;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:73: syntax error, unexpected assign\n    assign out      = out_i ^ attr_i.invert;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv:87: syntax error, unexpected assign\n    assign unused_sigs = ^{out_i,\n    ^~~~~~\n%Error: Exiting due to 11 error(s)\n"
module prim_xilinx_pad_wrapper
  import prim_pad_wrapper_pkg::*;
#(

  parameter pad_type_e PadType = BidirStd,
  parameter scan_role_e ScanRole = NoScan
) (

  input              clk_scan_i,
  input              scanmode_i,

  input pad_pok_t    pok_i,

  inout wire         inout_io,
  output logic       in_o,
  output logic       in_raw_o,
  input              ie_i,
  input              out_i,
  input              oe_i,
  input pad_attr_t   attr_i
);


  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)


  logic unused_sigs;
  assign unused_sigs = ^{attr_i.slew_rate,
                         attr_i.drive_strength,
                         attr_i.od_en,
                         attr_i.schmitt_en,
                         attr_i.keep_en,
                         attr_i.pull_en,
                         attr_i.pull_select,
                         scanmode_i,
                         pok_i};


  if (PadType == InputStd) begin : gen_input_only
    logic unused_sigs;
    assign unused_sigs = ^{out_i,
                           oe_i,
                           attr_i.virt_od_en};


    logic in;
    assign in_raw_o = (ie_i) ? in  : 1'bz;
    assign in_o = attr_i.invert ^ in_raw_o;

    IBUF u_ibuf (
      .I ( inout_io ),
      .O ( in       )
    );
  end else if (PadType == BidirTol ||
               PadType == BidirOd ||
               PadType == BidirStd) begin : gen_bidir


    logic in;
    assign in_raw_o = (ie_i) ? in  : 1'bz;
    assign in_o = attr_i.invert ^ in_raw_o;


    logic oe_n, out;
    assign out      = out_i ^ attr_i.invert;


    assign oe_n     = ~oe_i | (out & attr_i.virt_od_en);

    IOBUF u_iobuf (
      .T  ( oe_n     ),
      .I  ( out      ),
      .O  ( in       ),
      .IO ( inout_io )
    );
  end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog

    logic unused_sigs;
    assign unused_sigs = ^{out_i,
                           oe_i,
                           attr_i.invert,
                           attr_i.virt_od_en};

    IBUF u_ibuf (
      .I ( inout_io ),
      .O ( in_raw_o )
    );

    assign in_raw_o = inout_io;

  end else begin : gen_invalid_config

    assert_static_in_generate_config_not_available
        assert_static_in_generate_config_not_available();
  end

endmodule
module prim_xilinx_pad_wrapper
  import prim_pad_wrapper_pkg::*;

#(

  parameter pad_type_e PadType = BidirStd,
  parameter scan_role_e ScanRole = NoScan
) (

  input              clk_scan_i,
  input              scanmode_i,

  input pad_pok_t    pok_i,

  inout wire         inout_io,
  output logic       in_o,
  output logic       in_raw_o,
  input              ie_i,
  input              out_i,
  input              oe_i,
  input pad_attr_t   attr_i
);


  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)


  logic unused_sigs;
  assign unused_sigs = ^{attr_i.slew_rate,
                         attr_i.drive_strength,
                         attr_i.od_en,
                         attr_i.schmitt_en,
                         attr_i.keep_en,
                         attr_i.pull_en,
                         attr_i.pull_select,
                         scanmode_i,
                         pok_i};


  if (PadType == InputStd) begin : gen_input_only
    logic unused_sigs;
    assign unused_sigs = ^{out_i,
                           oe_i,
                           attr_i.virt_od_en};


    logic in;
    assign in_raw_o = (ie_i) ? in  : 1'bz;
    assign in_o = attr_i.invert ^ in_raw_o;

    IBUF u_ibuf (
      .I ( inout_io ),
      .O ( in       )
    );
  end else if (PadType == BidirTol ||
               PadType == BidirOd ||
               PadType == BidirStd) begin : gen_bidir


    logic in;
    assign in_raw_o = (ie_i) ? in  : 1'bz;
    assign in_o = attr_i.invert ^ in_raw_o;


    logic oe_n, out;
    assign out      = out_i ^ attr_i.invert;


    assign oe_n     = ~oe_i | (out & attr_i.virt_od_en);

    IOBUF u_iobuf (
      .T  ( oe_n     ),
      .I  ( out      ),
      .O  ( in       ),
      .IO ( inout_io )
    );
  end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog

    logic unused_sigs;
    assign unused_sigs = ^{out_i,
                           oe_i,
                           attr_i.invert,
                           attr_i.virt_od_en};

    IBUF u_ibuf (
      .I ( inout_io ),
      .O ( in_raw_o )
    );

    assign in_raw_o = inout_io;

  end else begin : gen_invalid_config

    assert_static_in_generate_config_not_available
        assert_static_in_generate_config_not_available();
  end

endmodule