data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/encode_inv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/encode_inv.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 9 bits.\n                                                                                                                                 : ... In instance encode_inv\n        if (in[i-1]) out = i[OUTW:0] - 1;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module encode_inv
    (
     in,
     out,
     nonz
     );



parameter       INW  = 256;
parameter       OUTW = 8;



input [INW-1:0]     in;
output [OUTW-1:0]   out;
output              nonz;







wire                nonz;
assign              nonz    = |in;

integer             i;
reg [OUTW-1:0]      out;
always @ (in)
    begin
    out = {OUTW{1'b0}};
    for (i=INW;i>0;i=i-1)
        begin
        if (in[i-1]) out = i[OUTW:0] - 1;
        end
    end

endmodule
module encode_inv
    (
     in,
     out,
     nonz
     );




parameter       INW  = 256;
parameter       OUTW = 8;



input [INW-1:0]     in;
output [OUTW-1:0]   out;
output              nonz;







wire                nonz;
assign              nonz    = |in;

integer             i;
reg [OUTW-1:0]      out;
always @ (in)
    begin
    out = {OUTW{1'b0}};
    for (i=INW;i>0;i=i-1)
        begin
        if (in[i-1]) out = i[OUTW:0] - 1;
        end
    end

endmodule