data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/cluster_clock_buffer.sv
data/verilator_xmls/9fb8f526-53c2-4c7e-890d-1c7802321f49.xml
module cluster_clock_buffer
  (
   input  logic clk_i,
   output logic clk_o
   );
   
   assign clk_o = clk_i;
   
endmodule
module cluster_clock_buffer
  (
   input  logic clk_i,
   output logic clk_o
   );

   
   assign clk_o = clk_i;
   
endmodule