data/full_repos/permissive/52666593/vga/tb_clock_divider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52666593/vga/tb_clock_divider.v:10: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52666593/vga/tb_clock_divider.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/52666593/vga/tb_clock_divider.v:5: Cannot find file containing module: \'clock_divider\'\nclock_divider cd(clk,reset,div_clk);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/clock_divider\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/clock_divider.v\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_clock_divider;
reg clk;
reg reset;
wire div_clk;
clock_divider cd(clk,reset,div_clk);

initial begin
clk<=1'b0;
reset<=1'b1;
#5
reset<=1'b0;
end
always #5 clk <= ~clk;
endmodule
module tb_clock_divider;

reg clk;
reg reset;
wire div_clk;
clock_divider cd(clk,reset,div_clk);

initial begin
clk<=1'b0;
reset<=1'b1;
#5
reset<=1'b0;
end
always #5 clk <= ~clk;
endmodule