data/full_repos/permissive/475928601/Assignments/mealey_sr.v
data/verilator_xmls/214695bb-4023-4c37-a969-8f5472f00c18.xml
module sr(
    input s,
    input r,
    input clk,
    output reg q,
    output qb
);
    initial q = 0;
    assign qb = ~q;

    always @(posedge clk) begin
        if (s) q <= 1'b1;
        if (r) q <= 1'b0;
    end
endmodule
module sr(
    input s,
    input r,
    input clk,
    output reg q,
    output qb
);

    initial q = 0;
    assign qb = ~q;

    always @(posedge clk) begin
        if (s) q <= 1'b1;
        if (r) q <= 1'b0;
    end
endmodule