data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/1f6ccde0-9916-4182-aaec-a478bf50f701.xml
module dut_vlwrapper(
      clk,
       rst,
       finish,
       find_max_x_out_busy,
       find_max_x_out_vld,
       find_max_x_out_data,
       find_max_return_in_busy,
       find_max_return_in_vld,
       find_max_return_in_data

    );

	input clk;
	input rst;
	output finish;
	reg finish;
	wire m_finish;
	input find_max_x_out_busy;
	output find_max_x_out_vld;
	reg find_max_x_out_vld;
	wire m_find_max_x_out_vld;
	output [31:0] find_max_x_out_data;
	reg[31:0] find_max_x_out_data;
	wire [31:0] m_find_max_x_out_data;
	output find_max_return_in_busy;
	reg find_max_return_in_busy;
	wire m_find_max_return_in_busy;
	input find_max_return_in_vld;
	input [31:0] find_max_return_in_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .finish(m_finish),
         .find_max_x_out_busy(find_max_x_out_busy),
         .find_max_x_out_vld(m_find_max_x_out_vld),
         .find_max_x_out_data(m_find_max_x_out_data),
         .find_max_return_in_busy(m_find_max_return_in_busy),
         .find_max_return_in_vld(find_max_return_in_vld),
         .find_max_return_in_data(find_max_return_in_data)

    );




    always @(m_finish)
     begin
      finish <= m_finish;
     end
    always @(m_find_max_x_out_vld)
     begin
      find_max_x_out_vld <= m_find_max_x_out_vld;
     end
    always @(m_find_max_x_out_data)
     begin
      find_max_x_out_data <= m_find_max_x_out_data;
     end
    always @(m_find_max_return_in_busy)
     begin
      find_max_return_in_busy <= m_find_max_return_in_busy;
     end


endmodule
module dut_vlwrapper(
      clk,
       rst,
       finish,
       find_max_x_out_busy,
       find_max_x_out_vld,
       find_max_x_out_data,
       find_max_return_in_busy,
       find_max_return_in_vld,
       find_max_return_in_data

    );


	input clk;
	input rst;
	output finish;
	reg finish;
	wire m_finish;
	input find_max_x_out_busy;
	output find_max_x_out_vld;
	reg find_max_x_out_vld;
	wire m_find_max_x_out_vld;
	output [31:0] find_max_x_out_data;
	reg[31:0] find_max_x_out_data;
	wire [31:0] m_find_max_x_out_data;
	output find_max_return_in_busy;
	reg find_max_return_in_busy;
	wire m_find_max_return_in_busy;
	input find_max_return_in_vld;
	input [31:0] find_max_return_in_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .finish(m_finish),
         .find_max_x_out_busy(find_max_x_out_busy),
         .find_max_x_out_vld(m_find_max_x_out_vld),
         .find_max_x_out_data(m_find_max_x_out_data),
         .find_max_return_in_busy(m_find_max_return_in_busy),
         .find_max_return_in_vld(find_max_return_in_vld),
         .find_max_return_in_data(find_max_return_in_data)

    );




    always @(m_finish)
     begin
      finish <= m_finish;
     end
    always @(m_find_max_x_out_vld)
     begin
      find_max_x_out_vld <= m_find_max_x_out_vld;
     end
    always @(m_find_max_x_out_data)
     begin
      find_max_x_out_data <= m_find_max_x_out_data;
     end
    always @(m_find_max_return_in_busy)
     begin
      find_max_return_in_busy <= m_find_max_return_in_busy;
     end


endmodule