data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/sg_list_requester.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/sg_list_requester.v:93: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module sg_list_requester #(
	parameter C_FIFO_DATA_WIDTH = 9'd64,
	parameter C_FIFO_DEPTH = 1024,
	parameter C_MAX_READ_REQ = 2,

	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
	parameter C_WORDS_PER_ELEM = 4,
	parameter C_MAX_ELEMS = 200,
	parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
	parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
	input CLK,
	input RST,
	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,

	input USER_RST,
	
	output BUF_RECVD,
	input [31:0] BUF_DATA,
	input BUF_LEN_VALID,
	input BUF_ADDR_HI_VALID,
	input BUF_ADDR_LO_VALID,

	input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT,
	output FIFO_FLUSH,
	input FIFO_FLUSHED,
	output FIFO_RST,

	output RX_REQ,
	output [63:0] RX_ADDR,
	output [9:0] RX_LEN,
	input RX_REQ_ACK,
	input RX_DONE
);

`include "functions.vh"

reg		[31:0]			rData=0, _rData=0;
reg						rAddrHiValid=0, _rAddrHiValid=0;
reg						rAddrLoValid=0, _rAddrLoValid=0;
reg						rLenValid=0, _rLenValid=0;

(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg		[7:0]			rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg						rDone=0, _rDone=0;
reg						rDelay=0, _rDelay=0;
reg		[2:0]			rCarry=0, _rCarry=0;
reg		[3:0]			rValsProp=0, _rValsProp=0;
reg		[63:0]			rAddr=64'd0, _rAddr=64'd0;
reg		[31:0]			rBufWords=0, _rBufWords=0;
reg		[10:0]			rPageRem=0, _rPageRem=0;
reg						rPageSpill=0, _rPageSpill=0;
reg		[10:0]			rPreLen=0, _rPreLen=0;
reg		[2:0]			rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg		[2:0]			rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg		[9:0]			rMaxPayload=0, _rMaxPayload=0;
reg						rPayloadSpill=0, _rPayloadSpill=0;
reg		[9:0]			rLen=0, _rLen=0;
reg						rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg						rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg						rUserRst=0, _rUserRst=0;

reg						rRecvdAll=0, _rRecvdAll=0;
reg		[10:0]			rAckCount=0, _rAckCount=0;


assign BUF_RECVD = rDone;

assign FIFO_FLUSH = rState[7];
assign FIFO_RST = (rUserRst & rState[0]);

assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4];



always @ (posedge CLK) begin
	rData <= #1 _rData;
	rAddrHiValid <= #1 _rAddrHiValid;
	rAddrLoValid <= #1 _rAddrLoValid;
	rLenValid <= #1 _rLenValid;
end

always @ (*) begin
	_rData = BUF_DATA;
	_rAddrHiValid = BUF_ADDR_HI_VALID;
	_rAddrLoValid = BUF_ADDR_LO_VALID;
	_rLenValid = BUF_LEN_VALID;
end



wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
	rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
	rDone <= #1 (RST ? 1'd0 : _rDone);
	rDelay <= #1 _rDelay;
	rAddr <= #1 _rAddr;
	rCarry <= #1 _rCarry;
	rBufWords <= #1 _rBufWords;
	rValsProp <= #1 _rValsProp;
	rPageRem <= #1 _rPageRem;
	rPageSpill <= #1 _rPageSpill;
	rPreLen <= #1 _rPreLen;
	rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
	rMaxPayloadShift <= #1 _rMaxPayloadShift;
	rMaxPayload <= #1 _rMaxPayload;
	rPayloadSpill <= #1 _rPayloadSpill;
	rLen <= #1 _rLen;
	rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
	rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
	rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end

always @ (*) begin
	_rState = rState;
	_rDone = rDone;
	_rDelay = rDelay;

	_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
	_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
	{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
	{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
	{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
				 _rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
	_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
	_rPageRem = (wAddrLoInv + 1'd1);	
	_rPageSpill = (rBufWords > rPageRem);	
	_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);			
	_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
	_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
	_rMaxPayload = (6'd32<<rMaxPayloadShift);
	_rPayloadSpill = (rPreLen > rMaxPayload);
	_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
	_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
	_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);

	case (rState)

	`S_SGREQ_IDLE: begin
		_rDone = 0;
		if (rLenValid)
			_rState = `S_SGREQ_WAIT_0;
	end

	`S_SGREQ_WAIT_0: begin
		_rDelay = 0;
		_rState = `S_SGREQ_WAIT_1;
	end

	`S_SGREQ_WAIT_1: begin
		_rDelay = 1;
		if (rDelay)
			_rState = `S_SGREQ_CHECK;
	end

	`S_SGREQ_CHECK: begin
		if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
			_rState = `S_SGREQ_ISSUE;
		else if (rUserRst)
			_rState = `S_SGREQ_COUNT;
	end
	
	`S_SGREQ_ISSUE: begin
		if (RX_REQ_ACK)
			_rState = `S_SGREQ_UPDATE;
	end

	`S_SGREQ_UPDATE: begin
		if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
			_rState = `S_SGREQ_COUNT;
		else if (rValsProp[3])
			_rState = `S_SGREQ_ISSUE;
	end

	`S_SGREQ_COUNT: begin
		if (rRecvdAll)
			_rState = `S_SGREQ_FLUSH;
	end

	`S_SGREQ_FLUSH: begin
		if (FIFO_FLUSHED) begin
			_rDone = !rUserRst;
			_rState = `S_SGREQ_IDLE;
		end
	end

	default: begin
		_rState = `S_SGREQ_IDLE;
	end

	endcase
end




always @ (posedge CLK) begin
	rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
	rRecvdAll <= #1 _rRecvdAll;
end

always @ (*) begin

	_rRecvdAll = (rAckCount == 10'd0);
	if (rState[0])
		_rAckCount = 0;
	else
		_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE; 
end


endmodule
module sg_list_requester #(
	parameter C_FIFO_DATA_WIDTH = 9'd64,
	parameter C_FIFO_DEPTH = 1024,
	parameter C_MAX_READ_REQ = 2,

	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
	parameter C_WORDS_PER_ELEM = 4,
	parameter C_MAX_ELEMS = 200,
	parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
	parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
	input CLK,
	input RST,
	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,

	input USER_RST,
	
	output BUF_RECVD,
	input [31:0] BUF_DATA,
	input BUF_LEN_VALID,
	input BUF_ADDR_HI_VALID,
	input BUF_ADDR_LO_VALID,

	input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT,
	output FIFO_FLUSH,
	input FIFO_FLUSHED,
	output FIFO_RST,

	output RX_REQ,
	output [63:0] RX_ADDR,
	output [9:0] RX_LEN,
	input RX_REQ_ACK,
	input RX_DONE
);


`include "functions.vh"

reg		[31:0]			rData=0, _rData=0;
reg						rAddrHiValid=0, _rAddrHiValid=0;
reg						rAddrLoValid=0, _rAddrLoValid=0;
reg						rLenValid=0, _rLenValid=0;

(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg		[7:0]			rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg						rDone=0, _rDone=0;
reg						rDelay=0, _rDelay=0;
reg		[2:0]			rCarry=0, _rCarry=0;
reg		[3:0]			rValsProp=0, _rValsProp=0;
reg		[63:0]			rAddr=64'd0, _rAddr=64'd0;
reg		[31:0]			rBufWords=0, _rBufWords=0;
reg		[10:0]			rPageRem=0, _rPageRem=0;
reg						rPageSpill=0, _rPageSpill=0;
reg		[10:0]			rPreLen=0, _rPreLen=0;
reg		[2:0]			rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg		[2:0]			rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg		[9:0]			rMaxPayload=0, _rMaxPayload=0;
reg						rPayloadSpill=0, _rPayloadSpill=0;
reg		[9:0]			rLen=0, _rLen=0;
reg						rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg						rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg						rUserRst=0, _rUserRst=0;

reg						rRecvdAll=0, _rRecvdAll=0;
reg		[10:0]			rAckCount=0, _rAckCount=0;


assign BUF_RECVD = rDone;

assign FIFO_FLUSH = rState[7];
assign FIFO_RST = (rUserRst & rState[0]);

assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4];



always @ (posedge CLK) begin
	rData <= #1 _rData;
	rAddrHiValid <= #1 _rAddrHiValid;
	rAddrLoValid <= #1 _rAddrLoValid;
	rLenValid <= #1 _rLenValid;
end

always @ (*) begin
	_rData = BUF_DATA;
	_rAddrHiValid = BUF_ADDR_HI_VALID;
	_rAddrLoValid = BUF_ADDR_LO_VALID;
	_rLenValid = BUF_LEN_VALID;
end



wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
	rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
	rDone <= #1 (RST ? 1'd0 : _rDone);
	rDelay <= #1 _rDelay;
	rAddr <= #1 _rAddr;
	rCarry <= #1 _rCarry;
	rBufWords <= #1 _rBufWords;
	rValsProp <= #1 _rValsProp;
	rPageRem <= #1 _rPageRem;
	rPageSpill <= #1 _rPageSpill;
	rPreLen <= #1 _rPreLen;
	rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
	rMaxPayloadShift <= #1 _rMaxPayloadShift;
	rMaxPayload <= #1 _rMaxPayload;
	rPayloadSpill <= #1 _rPayloadSpill;
	rLen <= #1 _rLen;
	rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
	rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
	rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end

always @ (*) begin
	_rState = rState;
	_rDone = rDone;
	_rDelay = rDelay;

	_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
	_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
	{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
	{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
	{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
				 _rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
	_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
	_rPageRem = (wAddrLoInv + 1'd1);	
	_rPageSpill = (rBufWords > rPageRem);	
	_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);			
	_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
	_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
	_rMaxPayload = (6'd32<<rMaxPayloadShift);
	_rPayloadSpill = (rPreLen > rMaxPayload);
	_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
	_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
	_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);

	case (rState)

	`S_SGREQ_IDLE: begin
		_rDone = 0;
		if (rLenValid)
			_rState = `S_SGREQ_WAIT_0;
	end

	`S_SGREQ_WAIT_0: begin
		_rDelay = 0;
		_rState = `S_SGREQ_WAIT_1;
	end

	`S_SGREQ_WAIT_1: begin
		_rDelay = 1;
		if (rDelay)
			_rState = `S_SGREQ_CHECK;
	end

	`S_SGREQ_CHECK: begin
		if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
			_rState = `S_SGREQ_ISSUE;
		else if (rUserRst)
			_rState = `S_SGREQ_COUNT;
	end
	
	`S_SGREQ_ISSUE: begin
		if (RX_REQ_ACK)
			_rState = `S_SGREQ_UPDATE;
	end

	`S_SGREQ_UPDATE: begin
		if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
			_rState = `S_SGREQ_COUNT;
		else if (rValsProp[3])
			_rState = `S_SGREQ_ISSUE;
	end

	`S_SGREQ_COUNT: begin
		if (rRecvdAll)
			_rState = `S_SGREQ_FLUSH;
	end

	`S_SGREQ_FLUSH: begin
		if (FIFO_FLUSHED) begin
			_rDone = !rUserRst;
			_rState = `S_SGREQ_IDLE;
		end
	end

	default: begin
		_rState = `S_SGREQ_IDLE;
	end

	endcase
end




always @ (posedge CLK) begin
	rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
	rRecvdAll <= #1 _rRecvdAll;
end

always @ (*) begin

	_rRecvdAll = (rAckCount == 10'd0);
	if (rState[0])
		_rAckCount = 0;
	else
		_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE; 
end


endmodule