data/full_repos/permissive/446997925/hw3/or.v
data/verilator_xmls/91d6b0c7-80e9-4fd8-b698-4e241996a499.xml
module or_4(out, a, b);
input [3:0] a, b;
output [3:0] out;

or_2 f(out[1:0], a[1:0], b[1:0]),
          s(out[3:2], a[3:2], b[3:2]);
endmodule
module or_4(out, a, b);

input [3:0] a, b;
output [3:0] out;

or_2 f(out[1:0], a[1:0], b[1:0]),
          s(out[3:2], a[3:2], b[3:2]);
endmodule