data/full_repos/permissive/507506290/RTL_Files/ADD_Branch.v
data/verilator_xmls/4e41198c-ef52-4af6-b9eb-0652ef5be0e0.xml
module ADD_Branch(i_op1 , i_op2 , o_out);
input [`WIDTH_BRANCH-1:0] i_op1 ;
input [`WIDTH_BRANCH-1:0] i_op2 ;
output [`WIDTH_BRANCH-1:0] o_out;


assign o_out = i_op1 + i_op2 ;
endmodule
module ADD_Branch(i_op1 , i_op2 , o_out);

input [`WIDTH_BRANCH-1:0] i_op1 ;
input [`WIDTH_BRANCH-1:0] i_op2 ;
output [`WIDTH_BRANCH-1:0] o_out;


assign o_out = i_op1 + i_op2 ;
endmodule