data/full_repos/permissive/464638001/generated/UartBlink.v
data/verilator_xmls/a285465c-e567-49e4-9ea4-f9e2f7ab9ba3.xml
module UartBlink(
  input   clock,
  input   reset,
  output  io_ledg0,
  output  io_txd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  reg [31:0] cntReg;
  reg  blkReg;
  wire [31:0] _T_1 = cntReg + 32'h1;
  wire [7:0] _GEN_0 = blkReg ? 8'h30 : 8'h31;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  assign io_ledg0 = blkReg;
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = cntReg == 32'h17d783f;
  assign tx_io_channel_bits = cntReg == 32'h17d783f ? _GEN_0 : 8'h0;
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 32'h0;
    end else if (cntReg == 32'h17d783f) begin
      cntReg <= 32'h0;
    end else begin
      cntReg <= _T_1;
    end
    if (reset) begin
      blkReg <= 1'h0;
    end else if (cntReg == 32'h17d783f) begin
      blkReg <= ~blkReg;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  blkReg = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module UartBlink(
  input   clock,
  input   reset,
  output  io_ledg0,
  output  io_txd
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  reg [31:0] cntReg;
  reg  blkReg;
  wire [31:0] _T_1 = cntReg + 32'h1;
  wire [7:0] _GEN_0 = blkReg ? 8'h30 : 8'h31;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  assign io_ledg0 = blkReg;
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = cntReg == 32'h17d783f;
  assign tx_io_channel_bits = cntReg == 32'h17d783f ? _GEN_0 : 8'h0;
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 32'h0;
    end else if (cntReg == 32'h17d783f) begin
      cntReg <= 32'h0;
    end else begin
      cntReg <= _T_1;
    end
    if (reset) begin
      blkReg <= 1'h0;
    end else if (cntReg == 32'h17d783f) begin
      blkReg <= ~blkReg;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  blkReg = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule