data/full_repos/permissive/485085993/verilog/rtl/logical_tile_io_mode_physical__iopad.v
1: b"%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_io_mode_physical__iopad.v:49: Cannot find file containing module: 'GPIO'\n GPIO GPIO_0_ (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/GPIO\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/GPIO.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/GPIO.sv\n             GPIO\n             GPIO.v\n             GPIO.sv\n             obj_dir/GPIO\n             obj_dir/GPIO.v\n             obj_dir/GPIO.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_io_mode_physical__iopad.v:55: Cannot find file containing module: 'GPIO_SRAM_mem'\n GPIO_SRAM_mem GPIO_SRAM_mem (\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module logical_tile_io_mode_physical__iopad(gfpga_pad_GPIO_PAD,
                                            iopad_outpad,
                                            bl,
                                            wl,
                                            iopad_inpad);

inout [0:0] gfpga_pad_GPIO_PAD;

input [0:0] iopad_outpad;

input [0:0] bl;

input [0:0] wl;

output [0:0] iopad_inpad;


wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;







wire [0:0] GPIO_0_DIR;
wire [0:0] GPIO_SRAM_mem_undriven_mem_outb;






	GPIO GPIO_0_ (
		.PAD(gfpga_pad_GPIO_PAD),
		.A(iopad_outpad),
		.DIR(GPIO_0_DIR),
		.Y(iopad_inpad));

	GPIO_SRAM_mem GPIO_SRAM_mem (
		.bl(bl),
		.wl(wl),
		.mem_out(GPIO_0_DIR),
		.mem_outb(GPIO_SRAM_mem_undriven_mem_outb));

endmodule
module logical_tile_io_mode_physical__iopad(gfpga_pad_GPIO_PAD,
                                            iopad_outpad,
                                            bl,
                                            wl,
                                            iopad_inpad);


inout [0:0] gfpga_pad_GPIO_PAD;

input [0:0] iopad_outpad;

input [0:0] bl;

input [0:0] wl;

output [0:0] iopad_inpad;


wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;







wire [0:0] GPIO_0_DIR;
wire [0:0] GPIO_SRAM_mem_undriven_mem_outb;






	GPIO GPIO_0_ (
		.PAD(gfpga_pad_GPIO_PAD),
		.A(iopad_outpad),
		.DIR(GPIO_0_DIR),
		.Y(iopad_inpad));

	GPIO_SRAM_mem GPIO_SRAM_mem (
		.bl(bl),
		.wl(wl),
		.mem_out(GPIO_0_DIR),
		.mem_outb(GPIO_SRAM_mem_undriven_mem_outb));

endmodule