data/full_repos/permissive/514992586/1_Verilog_language/Modules/27_Module_cseladd.v
1: b"%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/27_Module_cseladd.v:12: Cannot find file containing module: 'add16'\n    add16 instance1(.a(a[15:0]),\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16.v\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/27_Module_cseladd.v:17: Cannot find file containing module: 'add16'\n    add16 instance2(.a(a[31:16]),\n    ^~~~~\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/27_Module_cseladd.v:21: Cannot find file containing module: 'add16'\n    add16 instance3(.a(a[31:16]),\n    ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire sel;
    wire [15:0] sum1;
    wire [15:0] sum2;
    wire [15:0] sum3;
    wire [15:0] sum4;
    add16 instance1(.a(a[15:0]),
                    .b(b[15:0]),
                    .cin(1'b0),
                    .sum(sum1),
                    .cout(sel));
    add16 instance2(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(1'b0),
                    .sum(sum2));
    add16 instance3(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(1'b1),
                    .sum(sum3));
    always @(*)
        begin
            case (sel)
                0: sum4 = sum2;
                1: sum4 = sum3;
            endcase
        end
    assign sum = {sum4, sum1};
    
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);


    wire sel;
    wire [15:0] sum1;
    wire [15:0] sum2;
    wire [15:0] sum3;
    wire [15:0] sum4;
    add16 instance1(.a(a[15:0]),
                    .b(b[15:0]),
                    .cin(1'b0),
                    .sum(sum1),
                    .cout(sel));
    add16 instance2(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(1'b0),
                    .sum(sum2));
    add16 instance3(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(1'b1),
                    .sum(sum3));
    always @(*)
        begin
            case (sel)
                0: sum4 = sum2;
                1: sum4 = sum3;
            endcase
        end
    assign sum = {sum4, sum1};
    
endmodule