data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module MEMWB(clk, mwreg, mm2reg, mrn, maluOut, dmOut,
             wwreg, wm2reg, wrn, waluOut, wdmOut);
    input clk, mwreg, mm2reg;
    input [31:0] maluOut, dmOut; 
    input [4:0] mrn;
    

    reg mwreg2, mm2reg2;
    reg [31:0] maluOut2, dmOut2;
    reg [4:0] mrn2;
    
    output reg wwreg, wm2reg;
    output reg [31:0] waluOut, wdmOut;
    output reg [4:0] wrn;

    always @(posedge clk) begin
        mwreg2 <= mwreg;
        mm2reg2 <= mm2reg;
        maluOut2 <= maluOut;
        dmOut2 <= dmOut;
        mrn2 <= mrn;
    end
    
    always @(negedge clk) begin
        wwreg <= mwreg2;
        wm2reg <= mm2reg2;
        waluOut <= maluOut2;
        wdmOut <= dmOut2;
        wrn <= mrn2;
    end
endmodule
module MEMWB(clk, mwreg, mm2reg, mrn, maluOut, dmOut,
             wwreg, wm2reg, wrn, waluOut, wdmOut);

    input clk, mwreg, mm2reg;
    input [31:0] maluOut, dmOut; 
    input [4:0] mrn;
    

    reg mwreg2, mm2reg2;
    reg [31:0] maluOut2, dmOut2;
    reg [4:0] mrn2;
    
    output reg wwreg, wm2reg;
    output reg [31:0] waluOut, wdmOut;
    output reg [4:0] wrn;

    always @(posedge clk) begin
        mwreg2 <= mwreg;
        mm2reg2 <= mm2reg;
        maluOut2 <= maluOut;
        dmOut2 <= dmOut;
        mrn2 <= mrn;
    end
    
    always @(negedge clk) begin
        wwreg <= mwreg2;
        wm2reg <= mm2reg2;
        waluOut <= maluOut2;
        wdmOut <= dmOut2;
        wrn <= mrn2;
    end
endmodule