data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/Mux4x1.v
data/verilator_xmls/b6137a0a-e2ff-428f-b02f-4f35b1f7c760.xml
module Mux4x1  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input 	wire [W-1:0] 	In3,
	input 	wire [W-1:0] 	In4,
	input 	wire [1:0]		Sel,
	output 	wire [W-1:0]	Out
);
	
	wire 	[W-1:0] temp1;
	wire 	[W-1:0] temp2;
	
	assign temp1	= Sel[0] ? In4 : In3;
	assign temp2	= Sel[0] ? In2 : In1;
	
	assign Out 		= Sel[1] ?  temp1 : temp2;











endmodule
module Mux4x1  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input 	wire [W-1:0] 	In3,
	input 	wire [W-1:0] 	In4,
	input 	wire [1:0]		Sel,
	output 	wire [W-1:0]	Out
);

	
	wire 	[W-1:0] temp1;
	wire 	[W-1:0] temp2;
	
	assign temp1	= Sel[0] ? In4 : In3;
	assign temp2	= Sel[0] ? In2 : In1;
	
	assign Out 		= Sel[1] ?  temp1 : temp2;











endmodule