data/full_repos/permissive/469509877/rtl/V4.v
data/verilator_xmls/a89d121a-fac9-4245-b6f9-81390c3476ff.xml
module V4(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );
    
    assign Red[3] = (Hcount >= 10'b0100110100) & (Hcount <= 10'b0100111011) &  & 
                    ((Vcount[9] | Vcount[8] | Vcount[7] | Vcount[6] | Vcount[5] | Vcount[4] | Vcount[3]) & 
                    (~(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];                          
endmodule
module V4(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );

    
    assign Red[3] = (Hcount >= 10'b0100110100) & (Hcount <= 10'b0100111011) &  & 
                    ((Vcount[9] | Vcount[8] | Vcount[7] | Vcount[6] | Vcount[5] | Vcount[4] | Vcount[3]) & 
                    (~(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];                          
endmodule