data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #11\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #(10);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #9\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:9: Cannot find file containing module: \'tp_mem\'\ntp_mem tp_TEST(data_out, data_in, clk, rst, 1\'b1);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508935683/iverilog_dct,data/full_repos/permissive/508935683/tp_mem\n             data/full_repos/permissive/508935683/iverilog_dct,data/full_repos/permissive/508935683/tp_mem.v\n             data/full_repos/permissive/508935683/iverilog_dct,data/full_repos/permissive/508935683/tp_mem.sv\n             tp_mem\n             tp_mem.v\n             tp_mem.sv\n             obj_dir/tp_mem\n             obj_dir/tp_mem.v\n             obj_dir/tp_mem.sv\n%Warning-WIDTH: data/full_repos/permissive/508935683/iverilog_dct/tb_tp_mem.v:21: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                : ... In instance tb_tp_mem\n            data_in <= j;\n                    ^~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_tp_mem();

reg clk, rst;
reg [7:0] data_in;
wire [7:0] data_out;

tp_mem tp_TEST(data_out, data_in, clk, rst, 1'b1);

integer i, j;

initial begin
    rst <= 1;
    clk <= 1;
    #11
    rst <= 0;
    #9
    for (i=0;i<4;i=i+1) begin
        for (j=0;j<64;j=j+1) begin
            data_in <= j;
            #(10);
        end
    end
end

always #5 clk <= ~clk;

endmodule
module tb_tp_mem();


reg clk, rst;
reg [7:0] data_in;
wire [7:0] data_out;

tp_mem tp_TEST(data_out, data_in, clk, rst, 1'b1);

integer i, j;

initial begin
    rst <= 1;
    clk <= 1;
    #11
    rst <= 0;
    #9
    for (i=0;i<4;i=i+1) begin
        for (j=0;j<64;j=j+1) begin
            data_in <= j;
            #(10);
        end
    end
end

always #5 clk <= ~clk;

endmodule