data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/logic_and.v
data/verilator_xmls/1b9917de-6ad1-4bf7-a035-c20b9ee8bd6c.xml
module logic_and (in_a, in_b, out);
	input [31:0] in_a, in_b;
	output [31:0] out;
	genvar i;
	generate
	for(i = 0; i < 32; i = i+1) begin: generate_block_identifier1
		and and_1(out[i], in_a[i], in_b[i]);
	end
	endgenerate
endmodule
module logic_and (in_a, in_b, out);

	input [31:0] in_a, in_b;
	output [31:0] out;
	genvar i;
	generate
	for(i = 0; i < 32; i = i+1) begin: generate_block_identifier1
		and and_1(out[i], in_a[i], in_b[i]);
	end
	endgenerate
endmodule