data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:22: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:23: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:24: Cannot find include file: ctu.h\n`include "ctu.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:81: Define or directive not defined: \'`CTU_BIST_CNT\'\ninput [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:81: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\ninput [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;\n                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:130: Define or directive not defined: \'`UCB_BUF_HI\'\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:130: Define or directive not defined: \'`UCB_BUF_LO\'\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:130: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:131: Define or directive not defined: \'`UCB_THR_HI\'\nwire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:131: Define or directive not defined: \'`UCB_THR_LO\'\nwire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:131: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:153: Define or directive not defined: \'`UCB_BUF_HI\'\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:153: Define or directive not defined: \'`UCB_BUF_LO\'\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:153: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:154: Define or directive not defined: \'`UCB_THR_HI\'\nwire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:154: Define or directive not defined: \'`UCB_THR_LO\'\nwire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:154: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:186: Define or directive not defined: \'`UCB_SIZE_HI\'\nreg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:186: Define or directive not defined: \'`UCB_SIZE_LO\'\nreg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:186: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;\n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:187: Define or directive not defined: \'`UCB_BUF_HI\'\nreg [`UCB_BUF_HI-`UCB_BUF_LO:0]   ucbout_buf_id;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:187: Define or directive not defined: \'`UCB_BUF_LO\'\nreg [`UCB_BUF_HI-`UCB_BUF_LO:0]   ucbout_buf_id;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:187: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`UCB_BUF_HI-`UCB_BUF_LO:0]   ucbout_buf_id;\n                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:188: Define or directive not defined: \'`UCB_THR_HI\'\nreg [`UCB_THR_HI-`UCB_THR_LO:0]   ucbout_thr_id;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:188: Define or directive not defined: \'`UCB_THR_LO\'\nreg [`UCB_THR_HI-`UCB_THR_LO:0]   ucbout_thr_id;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:188: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`UCB_THR_HI-`UCB_THR_LO:0]   ucbout_thr_id;\n                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:189: Define or directive not defined: \'`UCB_PKT_HI\'\nreg [`UCB_PKT_HI-`UCB_PKT_LO:0]  ucbout_request_code;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:189: Define or directive not defined: \'`UCB_PKT_LO\'\nreg [`UCB_PKT_HI-`UCB_PKT_LO:0]  ucbout_request_code;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:189: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`UCB_PKT_HI-`UCB_PKT_LO:0]  ucbout_request_code;\n                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:325: Define or directive not defined: \'`CTU_BIST_CNT\'\n      rt_data_out = { {32-(`CTU_BIST_CNT*2){1\'b0}}, bist_jtag_result };\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:325: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n      rt_data_out = { {32-(`CTU_BIST_CNT*2){1\'b0}}, bist_jtag_result };\n                                        ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:421: Define or directive not defined: \'`UCB_READ_ACK\'\n      ucbout_request_code = `UCB_READ_ACK;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:421: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_request_code = `UCB_READ_ACK;\n                                         ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:425: Define or directive not defined: \'`UCB_WRITE_REQ\'\n      ucbout_request_code = `UCB_WRITE_REQ;\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:425: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_request_code = `UCB_WRITE_REQ;\n                                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:429: Define or directive not defined: \'`UCB_READ_REQ\'\n      ucbout_request_code = `UCB_READ_REQ;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:429: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_request_code = `UCB_READ_REQ;\n                                         ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:440: Define or directive not defined: \'`UCB_SIZE_HI\'\n      ucbout_size   = {(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1\'b0}};\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:440: Define or directive not defined: \'`UCB_SIZE_LO\'\n      ucbout_size   = {(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1\'b0}};\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:447: Define or directive not defined: \'`PCX_SZ_8B\'\n      ucbout_size = `PCX_SZ_8B;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:447: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_size = `PCX_SZ_8B;\n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:448: Define or directive not defined: \'`UCB_BID_TAP\'\n      ucbout_buf_id = `UCB_BID_TAP;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:448: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_buf_id = `UCB_BID_TAP;\n                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:449: Define or directive not defined: \'`UCB_THR_HI\'\n      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1\'b0}};\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:449: Define or directive not defined: \'`UCB_THR_LO\'\n      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1\'b0}};\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:454: Define or directive not defined: \'`PCX_SZ_8B\'\n      ucbout_size = `PCX_SZ_8B;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:454: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_size = `PCX_SZ_8B;\n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:455: Define or directive not defined: \'`UCB_BID_TAP\'\n      ucbout_buf_id = `UCB_BID_TAP;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:455: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      ucbout_buf_id = `UCB_BID_TAP;\n                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_dft_creg.v:456: Define or directive not defined: \'`UCB_THR_HI\'\n      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1\'b0}};\n                        ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctu_dft_creg (

creg_jtag_scratch_data, creg_jtag_rdrtrn_data, creg_jtag_rdrtrn_vld, 
tap_iob_stall, tap_iob_vld, tap_iob_data, rt_ack, rt_data_out, 

io_tck, jbus_clk, jbus_rst_l, io_pwron_rst_l, test_mode_pin, 
bist_mode_pin, start_clk_jl, jtag_creg_addr, jtag_creg_data, 
jtag_creg_rd_en, jtag_creg_wr_en, jtag_creg_addr_en, 
jtag_creg_data_en, jtag_creg_rdrtrn_complete, iob_tap_vld, 
iob_tap_data, iob_tap_stall, rt_valid, rt_addr_data, rt_read_write, 
rt_high_low, rt_data_in, bist_jtag_result
);


input 	      io_tck;
input 	      jbus_clk;
input 	      jbus_rst_l;
input 	      io_pwron_rst_l;
input 	      test_mode_pin;
input 	      bist_mode_pin;


input 	      start_clk_jl;


input [39:0] jtag_creg_addr;
input [63:0] jtag_creg_data;
input 	     jtag_creg_rd_en;
input 	     jtag_creg_wr_en;
input 	     jtag_creg_addr_en;
input 	     jtag_creg_data_en;
output [63:0] creg_jtag_scratch_data;
output [63:0] creg_jtag_rdrtrn_data;
output 	      creg_jtag_rdrtrn_vld;
input 	      jtag_creg_rdrtrn_complete;


output 	      tap_iob_stall;
input 	      iob_tap_vld;
input [7:0]   iob_tap_data;

output 	      tap_iob_vld;
output [7:0]  tap_iob_data;
input 	      iob_tap_stall;


input 	      rt_valid;
input 	      rt_addr_data;
input 	      rt_read_write;
input 	      rt_high_low;
input [31:0]  rt_data_in;
output 	      rt_ack;
output [31:0] rt_data_out;


input [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;





wire [63:0]   creg_jtag_scratch_data;
wire [63:0]   creg_jtag_rdrtrn_data;
wire 	      creg_jtag_rdrtrn_vld;
wire 	      tap_iob_stall;
wire 	      tap_iob_vld;
wire [7:0]    tap_iob_data;
wire 	      rt_ack;
reg [31:0]    rt_data_out;






wire 	      jtag_creg_rd_en_sync;
wire 	      jtag_creg_wr_en_sync;
wire 	      jtag_creg_addr_en_sync;
wire 	      jtag_creg_data_en_sync;
wire [39:0]   jtag_creg_addr_sync;
wire [63:0]   jtag_creg_data_sync;
wire 	      jtag_creg_rdrtrn_complete_sync;

wire [39:0]   jtag_addr_reg;
wire [63:0]   jtag_data_reg;
wire [63:0]   scratch_reg;
wire [63:0]   rdrtrn_reg;
wire 	      rdrtrn_reg_vld;
wire [7:0]    rt_addr_high;
wire [31:0]   rt_addr_low;
wire [31:0]   rt_data_high;
wire [31:0]   rt_data_low;
wire [7:0]    ramtest_addr_high;
wire [31:0]   ramtest_addr_low;
wire [31:0]   ramtest_data_high;
wire [31:0]   ramtest_data_low;
wire 	      ramtest_rw;
wire [63:0]   ramtest_rdrtrn;
wire 	      ramtest_req;
wire 	      ramtest_rd_pend;
wire 	      jtag_rd_req;
wire 	      jtag_wr_req;
wire 	      jtag_rd_pend;
wire 	      csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;
wire [39:0]   next_jtag_addr_reg;
wire [63:0]   next_jtag_data_reg;   
wire [63:0]   next_scratch_reg;
wire [63:0]   next_rdrtrn_reg;
wire 	      next_rdrtrn_reg_vld;
reg [7:0]     next_rt_addr_high;
reg [31:0]    next_rt_addr_low;
reg [31:0]    next_rt_data_high;
reg [31:0]    next_rt_data_low;
wire [7:0]    next_ramtest_addr_high;
wire [31:0]   next_ramtest_addr_low;
wire [31:0]   next_ramtest_data_high;
wire [31:0]   next_ramtest_data_low;
wire 	      next_ramtest_rw;
wire [63:0]   next_ramtest_rdrtrn;
wire 	      next_ramtest_req;
wire 	      next_ramtest_rd_pend;
wire 	      next_jtag_rd_req;
wire 	      next_jtag_wr_req;
wire 	      next_jtag_rd_pend;
wire 	      next_csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;
wire 	      next_rt_ack;

wire 	      jtag_addr_reg_en;
wire 	      jtag_data_reg_en;
wire 	      scratch_reg_en;
wire 	      rdrtrn_reg_en;
wire 	      rt_addr_high_en;
wire 	      rt_addr_low_en;
wire 	      rt_data_high_en;
wire 	      rt_data_low_en;
wire 	      ramtest_addr_high_en;
wire 	      ramtest_addr_low_en;
wire 	      ramtest_data_high_en;
wire 	      ramtest_data_low_en;
wire 	      ramtest_rw_en;
wire 	      ramtest_rdrtrn_en;
wire 	      csr_buf_id_en;
wire 	      csr_thr_id_en;

wire [63:0]   scratch_reg_sync;
wire [63:0]   rdrtrn_reg_sync;
wire 	      rdrtrn_reg_vld_sync;

wire 	      jtag_creg_wr_en_sync_d1;
wire 	      jtag_creg_rd_en_sync_d1;

wire 	      ucbout_write_pulse;
wire 	      ucbout_read_pulse;
wire 	      ucbout_ack_pulse;
reg [63:0]    ucbout_data;
reg [39:0]    ucbout_addr;
reg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;
reg [`UCB_BUF_HI-`UCB_BUF_LO:0]   ucbout_buf_id;
reg [`UCB_THR_HI-`UCB_THR_LO:0]   ucbout_thr_id;
reg [`UCB_PKT_HI-`UCB_PKT_LO:0]  ucbout_request_code;
reg [15:0]    ucbout_vec;
wire [127:0]  ucbout_buf;
wire 	      ucbout_outdata_busy;
wire 	      ucbout_outdata_wr;

wire [127:0]  ucbin_buf;
wire 	      ucbin_buf_vld;
wire [3:0]    ucbin_request;
wire [63:0]   ucbin_data;

wire 	      ucbin_rdrtrn_req;
wire 	      ucbin_write_req;
wire 	      ucbin_read_req;

wire 	      rt_valid_sync;
wire 	      rt_valid_sync_d1;
wire 	      rt_valid_negedge;
wire 	      req_acpt;
wire 	      ack_acpt;

wire 	      ramtest_rd_pend_sync;
wire 	      ramtest_rd_pend_sync_d1;
wire 	      ramtest_rd_pend_sync_negedge;
wire [63:0]   ramtest_rdrtrn_sync;

wire 	      rt_read_write_d1;
wire 	      rt_read_write_negedge;

wire 	      start_clk_jl_sync;

/rt_addr_high or rt_addr_high_en or rt_data_in) begin
   if (rt_addr_high_en)
      next_rt_addr_high = rt_data_in[7:0];
   else
      next_rt_addr_high = rt_addr_high;
end

assign rt_addr_low_en   = test_mode_pin & rt_valid &  rt_addr_data & ~rt_high_low;
always @ (rt_addr_low or rt_addr_low_en or rt_data_in) begin
   if (rt_addr_low_en)
      next_rt_addr_low = rt_data_in;
   else
      next_rt_addr_low= rt_addr_low;
end

assign rt_data_high_en   = test_mode_pin & rt_valid & ~rt_addr_data &  rt_high_low;
always @ (rt_data_high or rt_data_high_en or rt_data_in) begin
   if (rt_data_high_en)
      next_rt_data_high = rt_data_in;
   else
      next_rt_data_high = rt_data_high;
end

assign rt_data_low_en   = test_mode_pin & rt_valid & ~rt_addr_data & ~rt_high_low;
always @ (rt_data_in or rt_data_low or rt_data_low_en) begin
   if (rt_data_low_en)
      next_rt_data_low = rt_data_in;
   else
      next_rt_data_low = rt_data_low;
end

assign ramtest_rd_pend_sync_negedge = ~ramtest_rd_pend_sync & ramtest_rd_pend_sync_d1;
assign rt_read_write_negedge        = test_mode_pin & ~rt_read_write & rt_read_write_d1;
assign next_rt_ack =  start_clk_jl_sync
                    & (  (~rt_ack & ramtest_rd_pend_sync_negedge)
                       | ( rt_ack & ~rt_read_write_negedge));

always @ (bist_jtag_result or bist_mode_pin
	  or ramtest_rdrtrn_sync or rt_high_low or test_mode_pin) begin
   if (test_mode_pin & bist_mode_pin)
      rt_data_out = { {32-(`CTU_BIST_CNT*2){1'b0}}, bist_jtag_result };
   else begin
      if (rt_high_low)
	 rt_data_out = ramtest_rdrtrn_sync[63:32];
      else
	 rt_data_out = ramtest_rdrtrn_sync[31: 0];
   end
end






assign rt_valid_negedge = test_mode_pin & ~rt_valid_sync & rt_valid_sync_d1;


assign next_ramtest_addr_high = rt_addr_high;
assign ramtest_addr_high_en   = rt_valid_negedge;

assign next_ramtest_addr_low = rt_addr_low;
assign ramtest_addr_low_en   = rt_valid_negedge;

assign next_ramtest_data_high = rt_data_high;
assign ramtest_data_high_en   = rt_valid_negedge;

assign next_ramtest_data_low = rt_data_low;
assign ramtest_data_low_en   = rt_valid_negedge;

assign next_ramtest_rw         = rt_read_write;
assign ramtest_rw_en           = rt_valid_negedge;


assign next_ramtest_rdrtrn     = ucbin_data;
assign ramtest_rdrtrn_en       = ramtest_rd_pend & ucbin_rdrtrn_req;

/csr_ack_req or ucbout_write_pulse) begin
   if (csr_ack_req) begin
      ucbout_vec = 16'hffff;
      ucbout_request_code = `UCB_READ_ACK;
   end
   else if (ucbout_write_pulse) begin
      ucbout_vec = 16'hffff;
      ucbout_request_code = `UCB_WRITE_REQ;
   end
   else begin
      ucbout_vec = 16'h00ff;
      ucbout_request_code = `UCB_READ_REQ;
   end
end

always @ (csr_ack_req or csr_buf_id or csr_thr_id
	  or jtag_addr_reg or jtag_data_reg or ramtest_addr_high
	  or ramtest_addr_low or ramtest_data_high or ramtest_data_low
	  or ramtest_req or scratch_reg) begin
   if (csr_ack_req) begin
      ucbout_data   = scratch_reg;
      ucbout_addr   = {40{1'b0}};
      ucbout_size   = {(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}};
      ucbout_buf_id = csr_buf_id;
      ucbout_thr_id = csr_thr_id;
   end
   else if (ramtest_req) begin
      ucbout_data = {ramtest_data_high, ramtest_data_low};
      ucbout_addr = {ramtest_addr_high[7:0], ramtest_addr_low};
      ucbout_size = `PCX_SZ_8B;
      ucbout_buf_id = `UCB_BID_TAP;
      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
   end
   else begin
      ucbout_data = jtag_data_reg;
      ucbout_addr = jtag_addr_reg;
      ucbout_size = `PCX_SZ_8B;
      ucbout_buf_id = `UCB_BID_TAP;
      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
   end
end

assign ucbout_buf = { ucbout_data,
		      {9{1'b0}},
		      ucbout_addr,
		      ucbout_size,
		      ucbout_buf_id,
		      ucbout_thr_id,
		      ucbout_request_code};





ucb_bus_in #(8,64) u_ucb_in 
   (
     .stall          (tap_iob_stall),
     .indata_buf_vld (ucbin_buf_vld),
     .indata_buf     (ucbin_buf),


     .rst_l          (jbus_rst_l),
     .clk            (jbus_clk),
     .vld            (iob_tap_vld),
     .data           (iob_tap_data),
     .stall_a1       (csr_ack_req)
     );








assign ucbin_request = ucbin_buf[`UCB_PKT_HI:`UCB_PKT_LO];

assign ucbin_data    = ucbin_buf[`UCB_DATA_HI:`UCB_DATA_LO];

assign ucbin_rdrtrn_req = ucbin_buf_vld & ucbin_request == `UCB_READ_ACK;
assign ucbin_write_req  = ucbin_buf_vld & ucbin_request == `UCB_WRITE_REQ;
assign ucbin_read_req   = ucbin_buf_vld & ucbin_request == `UCB_READ_REQ;



assign csr_thr_id_en   = ucbin_read_req;
assign next_csr_thr_id = ucbin_buf[`UCB_THR_HI:`UCB_THR_LO];

assign csr_buf_id_en   = ucbin_read_req;
assign next_csr_buf_id = ucbin_buf[`UCB_BUF_HI:`UCB_BUF_LO];

assign next_csr_ack_req =  ucbin_read_req
                         | csr_ack_req & ~ack_acpt;


/ramtest_rd_pend or rt_valid_negedge) begin
   if (ramtest_rd_pend && rt_valid_negedge)
      $display ("%d %m: ERROR - new ramtest request received before previous ramtest read has completed",
		$time);
end
  
always @ (jtag_rd_req or jtag_wr_req) begin
   if (jtag_rd_req & jtag_wr_req)
      $display ("%d %m: ERROR - concurrent jtag read and write request to IOB",
		$time);
end


endmodule
module ctu_dft_creg (

creg_jtag_scratch_data, creg_jtag_rdrtrn_data, creg_jtag_rdrtrn_vld, 
tap_iob_stall, tap_iob_vld, tap_iob_data, rt_ack, rt_data_out, 

io_tck, jbus_clk, jbus_rst_l, io_pwron_rst_l, test_mode_pin, 
bist_mode_pin, start_clk_jl, jtag_creg_addr, jtag_creg_data, 
jtag_creg_rd_en, jtag_creg_wr_en, jtag_creg_addr_en, 
jtag_creg_data_en, jtag_creg_rdrtrn_complete, iob_tap_vld, 
iob_tap_data, iob_tap_stall, rt_valid, rt_addr_data, rt_read_write, 
rt_high_low, rt_data_in, bist_jtag_result
);



input 	      io_tck;
input 	      jbus_clk;
input 	      jbus_rst_l;
input 	      io_pwron_rst_l;
input 	      test_mode_pin;
input 	      bist_mode_pin;


input 	      start_clk_jl;


input [39:0] jtag_creg_addr;
input [63:0] jtag_creg_data;
input 	     jtag_creg_rd_en;
input 	     jtag_creg_wr_en;
input 	     jtag_creg_addr_en;
input 	     jtag_creg_data_en;
output [63:0] creg_jtag_scratch_data;
output [63:0] creg_jtag_rdrtrn_data;
output 	      creg_jtag_rdrtrn_vld;
input 	      jtag_creg_rdrtrn_complete;


output 	      tap_iob_stall;
input 	      iob_tap_vld;
input [7:0]   iob_tap_data;

output 	      tap_iob_vld;
output [7:0]  tap_iob_data;
input 	      iob_tap_stall;


input 	      rt_valid;
input 	      rt_addr_data;
input 	      rt_read_write;
input 	      rt_high_low;
input [31:0]  rt_data_in;
output 	      rt_ack;
output [31:0] rt_data_out;


input [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;





wire [63:0]   creg_jtag_scratch_data;
wire [63:0]   creg_jtag_rdrtrn_data;
wire 	      creg_jtag_rdrtrn_vld;
wire 	      tap_iob_stall;
wire 	      tap_iob_vld;
wire [7:0]    tap_iob_data;
wire 	      rt_ack;
reg [31:0]    rt_data_out;






wire 	      jtag_creg_rd_en_sync;
wire 	      jtag_creg_wr_en_sync;
wire 	      jtag_creg_addr_en_sync;
wire 	      jtag_creg_data_en_sync;
wire [39:0]   jtag_creg_addr_sync;
wire [63:0]   jtag_creg_data_sync;
wire 	      jtag_creg_rdrtrn_complete_sync;

wire [39:0]   jtag_addr_reg;
wire [63:0]   jtag_data_reg;
wire [63:0]   scratch_reg;
wire [63:0]   rdrtrn_reg;
wire 	      rdrtrn_reg_vld;
wire [7:0]    rt_addr_high;
wire [31:0]   rt_addr_low;
wire [31:0]   rt_data_high;
wire [31:0]   rt_data_low;
wire [7:0]    ramtest_addr_high;
wire [31:0]   ramtest_addr_low;
wire [31:0]   ramtest_data_high;
wire [31:0]   ramtest_data_low;
wire 	      ramtest_rw;
wire [63:0]   ramtest_rdrtrn;
wire 	      ramtest_req;
wire 	      ramtest_rd_pend;
wire 	      jtag_rd_req;
wire 	      jtag_wr_req;
wire 	      jtag_rd_pend;
wire 	      csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;
wire [39:0]   next_jtag_addr_reg;
wire [63:0]   next_jtag_data_reg;   
wire [63:0]   next_scratch_reg;
wire [63:0]   next_rdrtrn_reg;
wire 	      next_rdrtrn_reg_vld;
reg [7:0]     next_rt_addr_high;
reg [31:0]    next_rt_addr_low;
reg [31:0]    next_rt_data_high;
reg [31:0]    next_rt_data_low;
wire [7:0]    next_ramtest_addr_high;
wire [31:0]   next_ramtest_addr_low;
wire [31:0]   next_ramtest_data_high;
wire [31:0]   next_ramtest_data_low;
wire 	      next_ramtest_rw;
wire [63:0]   next_ramtest_rdrtrn;
wire 	      next_ramtest_req;
wire 	      next_ramtest_rd_pend;
wire 	      next_jtag_rd_req;
wire 	      next_jtag_wr_req;
wire 	      next_jtag_rd_pend;
wire 	      next_csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;
wire 	      next_rt_ack;

wire 	      jtag_addr_reg_en;
wire 	      jtag_data_reg_en;
wire 	      scratch_reg_en;
wire 	      rdrtrn_reg_en;
wire 	      rt_addr_high_en;
wire 	      rt_addr_low_en;
wire 	      rt_data_high_en;
wire 	      rt_data_low_en;
wire 	      ramtest_addr_high_en;
wire 	      ramtest_addr_low_en;
wire 	      ramtest_data_high_en;
wire 	      ramtest_data_low_en;
wire 	      ramtest_rw_en;
wire 	      ramtest_rdrtrn_en;
wire 	      csr_buf_id_en;
wire 	      csr_thr_id_en;

wire [63:0]   scratch_reg_sync;
wire [63:0]   rdrtrn_reg_sync;
wire 	      rdrtrn_reg_vld_sync;

wire 	      jtag_creg_wr_en_sync_d1;
wire 	      jtag_creg_rd_en_sync_d1;

wire 	      ucbout_write_pulse;
wire 	      ucbout_read_pulse;
wire 	      ucbout_ack_pulse;
reg [63:0]    ucbout_data;
reg [39:0]    ucbout_addr;
reg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;
reg [`UCB_BUF_HI-`UCB_BUF_LO:0]   ucbout_buf_id;
reg [`UCB_THR_HI-`UCB_THR_LO:0]   ucbout_thr_id;
reg [`UCB_PKT_HI-`UCB_PKT_LO:0]  ucbout_request_code;
reg [15:0]    ucbout_vec;
wire [127:0]  ucbout_buf;
wire 	      ucbout_outdata_busy;
wire 	      ucbout_outdata_wr;

wire [127:0]  ucbin_buf;
wire 	      ucbin_buf_vld;
wire [3:0]    ucbin_request;
wire [63:0]   ucbin_data;

wire 	      ucbin_rdrtrn_req;
wire 	      ucbin_write_req;
wire 	      ucbin_read_req;

wire 	      rt_valid_sync;
wire 	      rt_valid_sync_d1;
wire 	      rt_valid_negedge;
wire 	      req_acpt;
wire 	      ack_acpt;

wire 	      ramtest_rd_pend_sync;
wire 	      ramtest_rd_pend_sync_d1;
wire 	      ramtest_rd_pend_sync_negedge;
wire [63:0]   ramtest_rdrtrn_sync;

wire 	      rt_read_write_d1;
wire 	      rt_read_write_negedge;

wire 	      start_clk_jl_sync;

/rt_addr_high or rt_addr_high_en or rt_data_in) begin
   if (rt_addr_high_en)
      next_rt_addr_high = rt_data_in[7:0];
   else
      next_rt_addr_high = rt_addr_high;
end

assign rt_addr_low_en   = test_mode_pin & rt_valid &  rt_addr_data & ~rt_high_low;
always @ (rt_addr_low or rt_addr_low_en or rt_data_in) begin
   if (rt_addr_low_en)
      next_rt_addr_low = rt_data_in;
   else
      next_rt_addr_low= rt_addr_low;
end

assign rt_data_high_en   = test_mode_pin & rt_valid & ~rt_addr_data &  rt_high_low;
always @ (rt_data_high or rt_data_high_en or rt_data_in) begin
   if (rt_data_high_en)
      next_rt_data_high = rt_data_in;
   else
      next_rt_data_high = rt_data_high;
end

assign rt_data_low_en   = test_mode_pin & rt_valid & ~rt_addr_data & ~rt_high_low;
always @ (rt_data_in or rt_data_low or rt_data_low_en) begin
   if (rt_data_low_en)
      next_rt_data_low = rt_data_in;
   else
      next_rt_data_low = rt_data_low;
end

assign ramtest_rd_pend_sync_negedge = ~ramtest_rd_pend_sync & ramtest_rd_pend_sync_d1;
assign rt_read_write_negedge        = test_mode_pin & ~rt_read_write & rt_read_write_d1;
assign next_rt_ack =  start_clk_jl_sync
                    & (  (~rt_ack & ramtest_rd_pend_sync_negedge)
                       | ( rt_ack & ~rt_read_write_negedge));

always @ (bist_jtag_result or bist_mode_pin
	  or ramtest_rdrtrn_sync or rt_high_low or test_mode_pin) begin
   if (test_mode_pin & bist_mode_pin)
      rt_data_out = { {32-(`CTU_BIST_CNT*2){1'b0}}, bist_jtag_result };
   else begin
      if (rt_high_low)
	 rt_data_out = ramtest_rdrtrn_sync[63:32];
      else
	 rt_data_out = ramtest_rdrtrn_sync[31: 0];
   end
end






assign rt_valid_negedge = test_mode_pin & ~rt_valid_sync & rt_valid_sync_d1;


assign next_ramtest_addr_high = rt_addr_high;
assign ramtest_addr_high_en   = rt_valid_negedge;

assign next_ramtest_addr_low = rt_addr_low;
assign ramtest_addr_low_en   = rt_valid_negedge;

assign next_ramtest_data_high = rt_data_high;
assign ramtest_data_high_en   = rt_valid_negedge;

assign next_ramtest_data_low = rt_data_low;
assign ramtest_data_low_en   = rt_valid_negedge;

assign next_ramtest_rw         = rt_read_write;
assign ramtest_rw_en           = rt_valid_negedge;


assign next_ramtest_rdrtrn     = ucbin_data;
assign ramtest_rdrtrn_en       = ramtest_rd_pend & ucbin_rdrtrn_req;

/csr_ack_req or ucbout_write_pulse) begin
   if (csr_ack_req) begin
      ucbout_vec = 16'hffff;
      ucbout_request_code = `UCB_READ_ACK;
   end
   else if (ucbout_write_pulse) begin
      ucbout_vec = 16'hffff;
      ucbout_request_code = `UCB_WRITE_REQ;
   end
   else begin
      ucbout_vec = 16'h00ff;
      ucbout_request_code = `UCB_READ_REQ;
   end
end

always @ (csr_ack_req or csr_buf_id or csr_thr_id
	  or jtag_addr_reg or jtag_data_reg or ramtest_addr_high
	  or ramtest_addr_low or ramtest_data_high or ramtest_data_low
	  or ramtest_req or scratch_reg) begin
   if (csr_ack_req) begin
      ucbout_data   = scratch_reg;
      ucbout_addr   = {40{1'b0}};
      ucbout_size   = {(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}};
      ucbout_buf_id = csr_buf_id;
      ucbout_thr_id = csr_thr_id;
   end
   else if (ramtest_req) begin
      ucbout_data = {ramtest_data_high, ramtest_data_low};
      ucbout_addr = {ramtest_addr_high[7:0], ramtest_addr_low};
      ucbout_size = `PCX_SZ_8B;
      ucbout_buf_id = `UCB_BID_TAP;
      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
   end
   else begin
      ucbout_data = jtag_data_reg;
      ucbout_addr = jtag_addr_reg;
      ucbout_size = `PCX_SZ_8B;
      ucbout_buf_id = `UCB_BID_TAP;
      ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
   end
end

assign ucbout_buf = { ucbout_data,
		      {9{1'b0}},
		      ucbout_addr,
		      ucbout_size,
		      ucbout_buf_id,
		      ucbout_thr_id,
		      ucbout_request_code};





ucb_bus_in #(8,64) u_ucb_in 
   (
     .stall          (tap_iob_stall),
     .indata_buf_vld (ucbin_buf_vld),
     .indata_buf     (ucbin_buf),


     .rst_l          (jbus_rst_l),
     .clk            (jbus_clk),
     .vld            (iob_tap_vld),
     .data           (iob_tap_data),
     .stall_a1       (csr_ack_req)
     );








assign ucbin_request = ucbin_buf[`UCB_PKT_HI:`UCB_PKT_LO];

assign ucbin_data    = ucbin_buf[`UCB_DATA_HI:`UCB_DATA_LO];

assign ucbin_rdrtrn_req = ucbin_buf_vld & ucbin_request == `UCB_READ_ACK;
assign ucbin_write_req  = ucbin_buf_vld & ucbin_request == `UCB_WRITE_REQ;
assign ucbin_read_req   = ucbin_buf_vld & ucbin_request == `UCB_READ_REQ;



assign csr_thr_id_en   = ucbin_read_req;
assign next_csr_thr_id = ucbin_buf[`UCB_THR_HI:`UCB_THR_LO];

assign csr_buf_id_en   = ucbin_read_req;
assign next_csr_buf_id = ucbin_buf[`UCB_BUF_HI:`UCB_BUF_LO];

assign next_csr_ack_req =  ucbin_read_req
                         | csr_ack_req & ~ack_acpt;


/ramtest_rd_pend or rt_valid_negedge) begin
   if (ramtest_rd_pend && rt_valid_negedge)
      $display ("%d %m: ERROR - new ramtest request received before previous ramtest read has completed",
		$time);
end
  
always @ (jtag_rd_req or jtag_wr_req) begin
   if (jtag_rd_req & jtag_wr_req)
      $display ("%d %m: ERROR - concurrent jtag read and write request to IOB",
		$time);
end


endmodule