data/full_repos/permissive/408955603/Sesion6/sumador4bits.v
1: b'%Error: data/full_repos/permissive/408955603/Sesion6/sumador4bits.v:1: Cannot find include file: sumadorCompleto.v\n`include "sumadorCompleto.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/sumadorCompleto.v\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/sumadorCompleto.v.v\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/sumadorCompleto.v.sv\n             sumadorCompleto.v\n             sumadorCompleto.v.v\n             sumadorCompleto.v.sv\n             obj_dir/sumadorCompleto.v\n             obj_dir/sumadorCompleto.v.v\n             obj_dir/sumadorCompleto.v.sv\n%Error: data/full_repos/permissive/408955603/Sesion6/sumador4bits.v:23: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | | %b + %b (%b) = %b (%b) || %d + %d = %d", E[7:4], E[3:0], E[8], S, Co, E[7:4], E[3:0], S);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion6/sumador4bits.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #18;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion6/sumador4bits.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #1 if((16*Co+S) != SC)\n   ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module test;
	reg [8:0] E;
	integer SC;
	wire [3:0] S;
	wire Co;

	Sum4bit s4b(S, Co, E[7:4], E[3:0], E[8]);

	initial
	begin
		$monitor($time, " | | %b + %b (%b) = %b (%b) || %d + %d = %d", E[7:4], E[3:0], E[8], S, Co, E[7:4], E[3:0], S);
		E = 0;

		SC = E[7:4]+E[3:0]+E[8];

		while(E != 'b111111111) 
		begin
			#18;
			#1 if((16*Co+S) != SC)
				$display("ERROR");
			
			E += 1;
			SC = E[7:4]+E[3:0]+E[8];
		end
	end
endmodule
module test;

	reg [8:0] E;
	integer SC;
	wire [3:0] S;
	wire Co;

	Sum4bit s4b(S, Co, E[7:4], E[3:0], E[8]);

	initial
	begin
		$monitor($time, " | | %b + %b (%b) = %b (%b) || %d + %d = %d", E[7:4], E[3:0], E[8], S, Co, E[7:4], E[3:0], S);
		E = 0;

		SC = E[7:4]+E[3:0]+E[8];

		while(E != 'b111111111) 
		begin
			#18;
			#1 if((16*Co+S) != SC)
				$display("ERROR");
			
			E += 1;
			SC = E[7:4]+E[3:0]+E[8];
		end
	end
endmodule