data/full_repos/permissive/464047548/top.v
1: b"%Error: data/full_repos/permissive/464047548/top.v:35: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/464047548/top.v:39: syntax error, unexpected IDENTIFIER\n    BUFG bufg_clk(.I(CLK), .O(clk));\n    ^~~~\n%Error: data/full_repos/permissive/464047548/top.v:44: syntax error, unexpected IDENTIFIER\n    display_clocks_simple #(      \n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:66: syntax error, unexpected IDENTIFIER\n    display_timings #(    \n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:101: syntax error, unexpected IDENTIFIER\n    bram_sdp #(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:116: syntax error, unexpected assign\n    assign VIDEO_IN = CK_IO[7];\n    ^~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:138: syntax error, unexpected IDENTIFIER\n    debounce #(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:178: syntax error, unexpected assign\n    assign fb_addr_write = {py[8:0], px[8:0]};   \n    ^~~~~~\n%Error: data/full_repos/permissive/464047548/top.v:230: syntax error, unexpected always\n    always @(posedge vga_clk) begin\n    ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module top(
    input  wire CLK,
    input  wire RST_BTN,
    input  wire [3:0] BTN,
    input  wire [13:0] CK_IO,
    output wire [3:0] LED,


    output wire VGA_HS,
    output wire VGA_VS,
    output wire [3:0] VGA_R,
    output wire [3:0] VGA_G,
    output wire [3:0] VGA_B,
);


    wire clk;
    BUFG bufg_clk(.I(CLK), .O(clk));


    wire vga_clk;
    wire vga_clk_lock;
    display_clocks_simple #(      
        .MULT(6.5),
        .DIV(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN), 
       .o_clk(vga_clk),
       .o_locked(vga_clk_lock)
    );


    wire signed [15:0] vga_sx;
    wire signed [15:0] vga_sy;
    wire vga_hsync;
    wire vga_vsync;
    wire vga_de;
    wire vga_frame;


    display_timings #(
        .H_RES(1024),
        .V_RES(768),
        .H_FP(24),
        .H_SYNC(136),
        .H_BP(160),
        .V_FP(3),
        .V_SYNC(6),
        .V_BP(29),
        .H_POL(1),
        .V_POL(1)
    )
    display_timings_inst (
        .i_pix_clk(vga_clk),
        .i_rst(!vga_clk_lock),
        .o_hs(vga_hsync),
        .o_vs(vga_vsync),
        .o_de(vga_de),
        .o_frame(vga_frame),
        .o_sx(vga_sx),
        .o_sy(vga_sy)
    );


    localparam FB_WIDTH  = 512;
    localparam FB_HEIGHT = 384;
    localparam FB_PIXELS = FB_WIDTH * FB_HEIGHT;
    localparam FB_ADDRW  = $clog2(FB_PIXELS);
    localparam FB_DATAW  = 1;

    reg fb_we;
    wire [FB_ADDRW-1:0] fb_addr_write;
    wire [FB_ADDRW-1:0] fb_addr_read;
    wire [FB_DATAW-1:0] fb_colr_write;
    wire [FB_DATAW-1:0] fb_colr_read;
    bram_sdp #(
        .WIDTH(FB_DATAW),
        .DEPTH(FB_PIXELS),
    ) bram_inst (
        .clk_write(clk),
        .clk_read(vga_clk),
        .we(fb_we),
        .addr_write(fb_addr_write),
        .addr_read(fb_addr_read),
        .data_in(fb_colr_write),
        .data_out(fb_colr_read),
    );


    wire VIDEO_IN, HSYNC_IN, VSYNC_IN;
    assign VIDEO_IN = CK_IO[7];
    assign HSYNC_IN = CK_IO[6];
    assign VSYNC_IN = CK_IO[5];









    localparam CTRW = 16;
    localparam CTR_INC = 5133;
    reg [CTRW-1:0] ctr_inc = CTR_INC;



    reg [3:0] samp_ctr, samp_offset = 2;


    wire [3:0] btn_val, btn_strb;
    debounce #(
        .DEBOUNCE_TIME(400_000),
        .BUTTONS(4),
    )
    debounce (
        .clk(clk),
        .btn(BTN),
        .val(btn_val),
        .strb(btn_strb),
    );
    always @(posedge clk) begin
        if (btn_strb[0] && btn_val[0]) begin
            ctr_inc <= ctr_inc - 1;
        end
        if (btn_strb[1] && btn_val[1]) begin
            ctr_inc <= ctr_inc + 1;
        end
        if (btn_strb[2] && btn_val[2]) begin
            samp_offset <= samp_offset - 1;
        end
        if (btn_strb[3] && btn_val[3]) begin
            samp_offset <= samp_offset + 1;
        end
    end




    reg [23:0] get_signal_ctr;
    wire get_signal_n = &get_signal_ctr;



    localparam PX_START = -177;
    localparam PY_START = -8;
    reg [CTRW-1:0] mac_ctr;

    reg last_vsync, last_hsync, last_video, last_vsync1, last_hsync1, last_video1;
    reg signed [15:0] px, py;

    assign fb_addr_write = {py[8:0], px[8:0]};
    assign fb_colr_write = last_video1;

    always @(posedge clk) begin

        if (!last_vsync1 && last_vsync) begin
            py <= PY_START;
            get_signal_ctr <= 0;


        end else if (last_hsync1 && !last_hsync) begin
            mac_ctr <= 0;
            py <= py + 1;
            px <= PX_START;
            get_signal_ctr <= 0;



        end else if (mac_ctr[CTRW-1]) begin
            samp_ctr <= 0;
            mac_ctr <= mac_ctr[CTRW-2:0] + ctr_inc;
            px <= px + 1;



        end else begin
            samp_ctr <= samp_ctr + 1;
            mac_ctr <= mac_ctr + ctr_inc;
            fb_we <= (samp_ctr == samp_offset && px >= 0 && px < 512 && py >= 0 && py < 342);
            get_signal_ctr <= get_signal_ctr + !get_signal_n;
        end

        last_video1 <= ~last_video;
        last_vsync1 <= last_vsync;
        last_hsync1 <= last_hsync;
        last_video <= VIDEO_IN;
        last_vsync <= VSYNC_IN;
        last_hsync <= HSYNC_IN;
    end





    assign fb_addr_read = {vga_sy[9:1], vga_sx[9:1]};





    reg [3:0] pix_out;
    reg vga_de1, hs1, vs1, vga_de2, hs2, vs2;
    always @(posedge vga_clk) begin
        pix_out <= vga_de1 && fb_colr_read ? 4'hf : 4'h0;
        hs2 <= hs1;
        vs2 <= vs1;
        vga_de1 <= vga_de && !get_signal_n;
        hs1 <= vga_hsync && !get_signal_n;
        vs1 <= vga_vsync && !get_signal_n;
    end


    assign VGA_HS   = hs2;
    assign VGA_VS   = vs2;
    assign VGA_R    = pix_out;
    assign VGA_G    = pix_out;
    assign VGA_B    = pix_out;
endmodule
module top(
    input  wire CLK,
    input  wire RST_BTN,
    input  wire [3:0] BTN,
    input  wire [13:0] CK_IO,
    output wire [3:0] LED,


    output wire VGA_HS,
    output wire VGA_VS,
    output wire [3:0] VGA_R,
    output wire [3:0] VGA_G,
    output wire [3:0] VGA_B,
);



    wire clk;
    BUFG bufg_clk(.I(CLK), .O(clk));


    wire vga_clk;
    wire vga_clk_lock;
    display_clocks_simple #(      
        .MULT(6.5),
        .DIV(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN), 
       .o_clk(vga_clk),
       .o_locked(vga_clk_lock)
    );


    wire signed [15:0] vga_sx;
    wire signed [15:0] vga_sy;
    wire vga_hsync;
    wire vga_vsync;
    wire vga_de;
    wire vga_frame;


    display_timings #(
        .H_RES(1024),
        .V_RES(768),
        .H_FP(24),
        .H_SYNC(136),
        .H_BP(160),
        .V_FP(3),
        .V_SYNC(6),
        .V_BP(29),
        .H_POL(1),
        .V_POL(1)
    )
    display_timings_inst (
        .i_pix_clk(vga_clk),
        .i_rst(!vga_clk_lock),
        .o_hs(vga_hsync),
        .o_vs(vga_vsync),
        .o_de(vga_de),
        .o_frame(vga_frame),
        .o_sx(vga_sx),
        .o_sy(vga_sy)
    );


    localparam FB_WIDTH  = 512;
    localparam FB_HEIGHT = 384;
    localparam FB_PIXELS = FB_WIDTH * FB_HEIGHT;
    localparam FB_ADDRW  = $clog2(FB_PIXELS);
    localparam FB_DATAW  = 1;

    reg fb_we;
    wire [FB_ADDRW-1:0] fb_addr_write;
    wire [FB_ADDRW-1:0] fb_addr_read;
    wire [FB_DATAW-1:0] fb_colr_write;
    wire [FB_DATAW-1:0] fb_colr_read;
    bram_sdp #(
        .WIDTH(FB_DATAW),
        .DEPTH(FB_PIXELS),
    ) bram_inst (
        .clk_write(clk),
        .clk_read(vga_clk),
        .we(fb_we),
        .addr_write(fb_addr_write),
        .addr_read(fb_addr_read),
        .data_in(fb_colr_write),
        .data_out(fb_colr_read),
    );


    wire VIDEO_IN, HSYNC_IN, VSYNC_IN;
    assign VIDEO_IN = CK_IO[7];
    assign HSYNC_IN = CK_IO[6];
    assign VSYNC_IN = CK_IO[5];









    localparam CTRW = 16;
    localparam CTR_INC = 5133;
    reg [CTRW-1:0] ctr_inc = CTR_INC;



    reg [3:0] samp_ctr, samp_offset = 2;


    wire [3:0] btn_val, btn_strb;
    debounce #(
        .DEBOUNCE_TIME(400_000),
        .BUTTONS(4),
    )
    debounce (
        .clk(clk),
        .btn(BTN),
        .val(btn_val),
        .strb(btn_strb),
    );
    always @(posedge clk) begin
        if (btn_strb[0] && btn_val[0]) begin
            ctr_inc <= ctr_inc - 1;
        end
        if (btn_strb[1] && btn_val[1]) begin
            ctr_inc <= ctr_inc + 1;
        end
        if (btn_strb[2] && btn_val[2]) begin
            samp_offset <= samp_offset - 1;
        end
        if (btn_strb[3] && btn_val[3]) begin
            samp_offset <= samp_offset + 1;
        end
    end




    reg [23:0] get_signal_ctr;
    wire get_signal_n = &get_signal_ctr;



    localparam PX_START = -177;
    localparam PY_START = -8;
    reg [CTRW-1:0] mac_ctr;

    reg last_vsync, last_hsync, last_video, last_vsync1, last_hsync1, last_video1;
    reg signed [15:0] px, py;

    assign fb_addr_write = {py[8:0], px[8:0]};
    assign fb_colr_write = last_video1;

    always @(posedge clk) begin

        if (!last_vsync1 && last_vsync) begin
            py <= PY_START;
            get_signal_ctr <= 0;


        end else if (last_hsync1 && !last_hsync) begin
            mac_ctr <= 0;
            py <= py + 1;
            px <= PX_START;
            get_signal_ctr <= 0;



        end else if (mac_ctr[CTRW-1]) begin
            samp_ctr <= 0;
            mac_ctr <= mac_ctr[CTRW-2:0] + ctr_inc;
            px <= px + 1;



        end else begin
            samp_ctr <= samp_ctr + 1;
            mac_ctr <= mac_ctr + ctr_inc;
            fb_we <= (samp_ctr == samp_offset && px >= 0 && px < 512 && py >= 0 && py < 342);
            get_signal_ctr <= get_signal_ctr + !get_signal_n;
        end

        last_video1 <= ~last_video;
        last_vsync1 <= last_vsync;
        last_hsync1 <= last_hsync;
        last_video <= VIDEO_IN;
        last_vsync <= VSYNC_IN;
        last_hsync <= HSYNC_IN;
    end





    assign fb_addr_read = {vga_sy[9:1], vga_sx[9:1]};





    reg [3:0] pix_out;
    reg vga_de1, hs1, vs1, vga_de2, hs2, vs2;
    always @(posedge vga_clk) begin
        pix_out <= vga_de1 && fb_colr_read ? 4'hf : 4'h0;
        hs2 <= hs1;
        vs2 <= vs1;
        vga_de1 <= vga_de && !get_signal_n;
        hs1 <= vga_hsync && !get_signal_n;
        vs1 <= vga_vsync && !get_signal_n;
    end


    assign VGA_HS   = hs2;
    assign VGA_VS   = vs2;
    assign VGA_R    = pix_out;
    assign VGA_G    = pix_out;
    assign VGA_B    = pix_out;
endmodule