data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:146: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'rbm_0_data\'\nmodule rbm_0_data(CLK, \n       ^~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_edges\'\nmodule rbm_0_edges(CLK, rbm_0_edges_CE0, rbm_0_edges_A0, rbm_0_edges_D0, rbm_0_edges_WE0, rbm_0_edges_WEM0, rbm_0_edges_CE2, rbm_0_edges_A2, rbm_0_edges_Q2, rbm_0_edges_CE1, rbm_0_edges_A1, rbm_0_edges_Q1,\n       ^~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_hidden_unit\'\nmodule rbm_0_hidden_unit(CLK, rbm_0_hidden_unit_CE1, rbm_0_hidden_unit_A1, rbm_0_hidden_unit_D1, rbm_0_hidden_unit_WE1, rbm_0_hidden_unit_WEM1, rbm_0_hidden_unit_CE3, rbm_0_hidden_unit_A3, rbm_0_hidden_unit_Q3, rbm_0_hidden_unit_CE0, rbm_0_hidden_unit_A0, rbm_0_hidden_unit_D0, rbm_0_hidden_unit_WE0, rbm_0_hidden_unit_WEM0, rbm_0_hidden_unit_CE2, rbm_0_hidden_unit_A2, rbm_0_hidden_unit_Q2,\n       ^~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_mt\'\nmodule rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1, \n       ^~~~~~~~\n                                                                                                : ... Top module \'rbm_0_neg\'\nmodule rbm_0_neg(CLK, rbm_0_neg_CE0, rbm_0_neg_A0, rbm_0_neg_D0, rbm_0_neg_WE0, rbm_0_neg_WEM0, rbm_0_neg_CE1, rbm_0_neg_A1, rbm_0_neg_Q1,\n       ^~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_pos\'\nmodule rbm_0_pos(CLK, rbm_0_pos_CE0, rbm_0_pos_A0, rbm_0_pos_D0, rbm_0_pos_WE0, rbm_0_pos_WEM0, rbm_0_pos_CE1, rbm_0_pos_A1, rbm_0_pos_Q1,\n       ^~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_predict_result\'\nmodule rbm_0_predict_result(CLK, rbm_0_predict_result_CE1, rbm_0_predict_result_A1, rbm_0_predict_result_Q1, rbm_0_predict_result_CE0, rbm_0_predict_result_A0, rbm_0_predict_result_D0, rbm_0_predict_result_WE0, rbm_0_predict_result_WEM0,\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_visibleEnergies\'\n                                                                                                : ... Top module \'pow2_mem\'\nmodule pow2_mem(CLK, RST, waddr, wdata, wen, raddr, rdata, gm_step);\n       ^~~~~~~~\n                                                                                                : ... Top module \'predict_vector_mem\'\nmodule predict_vector_mem(CLK, RST, waddr, wdata,wen, raddr, rdata, gm_step);\n       ^~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'visible_unit_mem\'\nmodule visible_unit_mem(CLK, RST, waddr0, wdata0, wen0, waddr1, wdata1, wen1, raddr, rdata, gm_step);\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:35: Input/output/inout declaration not found for port: \'RST\'\n    RST\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:159: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:275: Input/output/inout declaration not found for port: \'gm_waddr1\'\n    gm_waddr1,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:276: Input/output/inout declaration not found for port: \'gm_wen1\'\n    gm_wen1,\n    ^~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:277: Input/output/inout declaration not found for port: \'gm_wdata1\'\n    gm_wdata1,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:284: Input/output/inout declaration not found for port: \'RST\'\n    RST \n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:554: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:667: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:787: Input/output/inout declaration not found for port: \'RST\'\n    RST  );\n    ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:882: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:895: Can\'t find definition of variable: \'gm_pwaddr\'\n                                                                                     : ... Suggested alternative: \'gm_waddr0\'\n                GM_addr  <= gm_pwaddr;\n                            ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:744: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:626: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:387: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:416: Can\'t find definition of variable: \'igm_step\'\n                                                                                     : ... Suggested alternative: \'gm_step\'\n            else if(igm_step & gm_wen1 ) begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:416: Can\'t find definition of variable: \'gm_wen1\'\n                                                                                     : ... Suggested alternative: \'gm_wen0\'\n            else if(igm_step & gm_wen1 ) begin\n                               ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:238: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:117: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: Exiting due to 12 error(s), 7 warning(s)\n'
module rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1, 
     RST);
  input CLK;

  input rbm_0_mt_CE0;
  input [9:0] rbm_0_mt_A0;
  input [31:0] rbm_0_mt_D0;
  input rbm_0_mt_WE0;
  input [31:0] rbm_0_mt_WEM0;

  input rbm_0_mt_CE1;
  input [9:0] rbm_0_mt_A1;
  output [31:0] rbm_0_mt_Q1;

  input RST;


   wire concrete_val_0;
    jasper_model_mpram #( 
        .READ_PORTS(1),
        .WRITE_PORTS(1),
        .ADDR_WIDTH(10),
        .DATA_WIDTH(32),
        .MAX_DEPTH(4),
        .MEM_STYLE(0),
        .RESET_STYLE(0),
        .RD_DATA_DLY(0)
        )
    mem_mpram
    (
        .clk(CLR),
        .rstN(~RST),
        .addr_rd( 
            { rbm_0_mt_A1 }),
        .data_rd(
            { rbm_0_mt_Q1 }),
        .read_allocate(
            {   rbm_0_mt_CE1 } ),
        .read( {1'b1 } ),

        .write( {rbm_0_mt_WE0} ),
        .write_allocate( {rbm_0_mt_CE0} ),
        .addr_wr({rbm_0_mt_A0}),
        .data_wr({rbm_0_mt_D0}),
        .concrete({concrete_val_0 })
    );


endmodule
module rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1, 
     RST);

  input CLK;

  input rbm_0_mt_CE0;
  input [9:0] rbm_0_mt_A0;
  input [31:0] rbm_0_mt_D0;
  input rbm_0_mt_WE0;
  input [31:0] rbm_0_mt_WEM0;

  input rbm_0_mt_CE1;
  input [9:0] rbm_0_mt_A1;
  output [31:0] rbm_0_mt_Q1;

  input RST;


   wire concrete_val_0;
    jasper_model_mpram #( 
        .READ_PORTS(1),
        .WRITE_PORTS(1),
        .ADDR_WIDTH(10),
        .DATA_WIDTH(32),
        .MAX_DEPTH(4),
        .MEM_STYLE(0),
        .RESET_STYLE(0),
        .RD_DATA_DLY(0)
        )
    mem_mpram
    (
        .clk(CLR),
        .rstN(~RST),
        .addr_rd( 
            { rbm_0_mt_A1 }),
        .data_rd(
            { rbm_0_mt_Q1 }),
        .read_allocate(
            {   rbm_0_mt_CE1 } ),
        .read( {1'b1 } ),

        .write( {rbm_0_mt_WE0} ),
        .write_allocate( {rbm_0_mt_CE0} ),
        .addr_wr({rbm_0_mt_A0}),
        .data_wr({rbm_0_mt_D0}),
        .concrete({concrete_val_0 })
    );


endmodule