data/full_repos/permissive/493019833/test/testcase/firrtl/ZeroPortMem/sbt/ZeroPortMem.v
data/verilator_xmls/3bec8721-ccfa-4593-9649-8c37ffa07766.xml
module ZeroPortMem(
  input   clock,
  input   reset
);
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
endmodule
module ZeroPortMem(
  input   clock,
  input   reset
);

  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
endmodule