data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:288: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb } + { 1\'b0, inpa} + cin:\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:289: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb } - { 1\'b0, inpa} - cin;\n                                       ^\n%Error: Exiting due to 16 warning(s)\n'
module rowDecoder( input [15:0] ird,
	output logic [15:0] row, output noCcrEn, output logic isArX);



	wire eaRdir = (ird[ 5:4] == 2'b00);

	wire eaAdir = (ird[ 5:3] == 3'b001);
	wire size11 = ird[7] & ird[6];
	
	always_comb begin
		case( ird[15:12])
		'h4,
		'h9,
		'hd:
			isArX = row[10] | row[12];
		default:
			isArX = 1'b0;
		endcase
	end

	always_comb begin
		unique case( ird[15:12])

		'h4:  begin
				if( ird[8])
					row = `ALU_ROW_06;
				else case( ird[11:9])
					'b000: row = `ALU_ROW_10;
					'b001: row = `ALU_ROW_04;
					'b010: row = `ALU_ROW_05;
					'b011: row = `ALU_ROW_11;
					'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09;
					'b101: row = `ALU_ROW_15;
					default: row = 0;
				endcase
			end

		'h0: begin
				if( ird[8])
					row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
				else case( ird[ 11:9])
					'b000:   row = `ALU_ROW_14;
					'b001:   row = `ALU_ROW_04;
					'b010:   row = `ALU_ROW_05;
					'b011:   row = `ALU_ROW_02;
					'b100:   row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
					'b101:   row = `ALU_ROW_13;
					'b110:   row = `ALU_ROW_06;
					default: row = 0;
					endcase
				end
				




		'h1,'h2,'h3:   row = `ALU_ROW_02;
		
		'h5:
			if( size11)										
               row = `ALU_ROW_15;
			else
				row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02;
		'h6:	row = 0;
		'h7:	row = `ALU_ROW_02;
		'h8:
			if( size11)
				row = `ALU_ROW_01;
			else if( ird[8] & eaRdir)
				row = `ALU_ROW_09;
			else
				row = `ALU_ROW_14;
		'h9:
			if( ird[8] & ~size11 & eaRdir)
				row = `ALU_ROW_10;
			else
				row = `ALU_ROW_05;
		'hb:
			if( ird[8] & ~size11 & ~eaAdir)
				row = `ALU_ROW_13;
			else
				row = `ALU_ROW_06;
		'hc:
			if( size11)
				row = `ALU_ROW_07;
			else if( ird[8] & eaRdir)
				row = `ALU_ROW_03;
			else
				row = `ALU_ROW_04;
		'hd:
			if( ird[8] & ~size11 & eaRdir)
				row = `ALU_ROW_12;
			else
				row = `ALU_ROW_02;
		'he:
			begin
				reg [1:0] stype;
				
				if( size11)
					stype = ird[ 10:9];
				else
					stype = ird[ 4:3];

				case( {stype, ird[8]})
				0: row = `ALU_ROW_02;
				1: row = `ALU_ROW_03;
				2: row = `ALU_ROW_05;
				3: row = `ALU_ROW_04;
				4: row = `ALU_ROW_08;
				5: row = `ALU_ROW_11;
				6: row = `ALU_ROW_10;
				7: row = `ALU_ROW_09;
				endcase
			end
			
		default:	row = 0;
		endcase
	end
   



	assign noCcrEn =

		( ird[15] & ~ird[13] & ird[12] & size11) |

		( (ird[15:12] == 4'h5) & eaAdir) |

		( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
        
endmodule
module rowDecoder( input [15:0] ird,
	output logic [15:0] row, output noCcrEn, output logic isArX);




	wire eaRdir = (ird[ 5:4] == 2'b00);

	wire eaAdir = (ird[ 5:3] == 3'b001);
	wire size11 = ird[7] & ird[6];
	
	always_comb begin
		case( ird[15:12])
		'h4,
		'h9,
		'hd:
			isArX = row[10] | row[12];
		default:
			isArX = 1'b0;
		endcase
	end

	always_comb begin
		unique case( ird[15:12])

		'h4:  begin
				if( ird[8])
					row = `ALU_ROW_06;
				else case( ird[11:9])
					'b000: row = `ALU_ROW_10;
					'b001: row = `ALU_ROW_04;
					'b010: row = `ALU_ROW_05;
					'b011: row = `ALU_ROW_11;
					'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09;
					'b101: row = `ALU_ROW_15;
					default: row = 0;
				endcase
			end

		'h0: begin
				if( ird[8])
					row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
				else case( ird[ 11:9])
					'b000:   row = `ALU_ROW_14;
					'b001:   row = `ALU_ROW_04;
					'b010:   row = `ALU_ROW_05;
					'b011:   row = `ALU_ROW_02;
					'b100:   row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
					'b101:   row = `ALU_ROW_13;
					'b110:   row = `ALU_ROW_06;
					default: row = 0;
					endcase
				end
				




		'h1,'h2,'h3:   row = `ALU_ROW_02;
		
		'h5:
			if( size11)										
               row = `ALU_ROW_15;
			else
				row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02;
		'h6:	row = 0;
		'h7:	row = `ALU_ROW_02;
		'h8:
			if( size11)
				row = `ALU_ROW_01;
			else if( ird[8] & eaRdir)
				row = `ALU_ROW_09;
			else
				row = `ALU_ROW_14;
		'h9:
			if( ird[8] & ~size11 & eaRdir)
				row = `ALU_ROW_10;
			else
				row = `ALU_ROW_05;
		'hb:
			if( ird[8] & ~size11 & ~eaAdir)
				row = `ALU_ROW_13;
			else
				row = `ALU_ROW_06;
		'hc:
			if( size11)
				row = `ALU_ROW_07;
			else if( ird[8] & eaRdir)
				row = `ALU_ROW_03;
			else
				row = `ALU_ROW_04;
		'hd:
			if( ird[8] & ~size11 & eaRdir)
				row = `ALU_ROW_12;
			else
				row = `ALU_ROW_02;
		'he:
			begin
				reg [1:0] stype;
				
				if( size11)
					stype = ird[ 10:9];
				else
					stype = ird[ 4:3];

				case( {stype, ird[8]})
				0: row = `ALU_ROW_02;
				1: row = `ALU_ROW_03;
				2: row = `ALU_ROW_05;
				3: row = `ALU_ROW_04;
				4: row = `ALU_ROW_08;
				5: row = `ALU_ROW_11;
				6: row = `ALU_ROW_10;
				7: row = `ALU_ROW_09;
				endcase
			end
			
		default:	row = 0;
		endcase
	end
   



	assign noCcrEn =

		( ird[15] & ~ird[13] & ird[12] & size11) |

		( (ird[15:12] == 4'h5) & eaAdir) |

		( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
        
endmodule