data/full_repos/permissive/43339463/register.v
1: b'%Error: data/full_repos/permissive/43339463/register.v:59: Unsupported or unknown PLI call: $monitor\n  $monitor("%t: rw = %b, o = %x, i = %x", $time, rw, oline, iline);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/register.v:89: Unsupported: Ignoring delay on this delayed statement.\n always #10 begin\n        ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_test;
	reg clk;
	reg [1:0] rw;
	wire [15:0] oline;
	reg [15:0] iline;
	
	register register(clk, iline, oline, rw);

	initial begin
		$monitor("%t: rw = %b, o = %x, i = %x", $time, rw, oline, iline);
		
		clk <= 0;
		#10
		rw <= 2'b11;
		iline <= 16'h1234;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b11;
		iline <= 16'h4567;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b01;
		iline <= 16'h89AB;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b10;
		iline <= 16'hCDEF;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10 $finish;
	end
	
	always #10 begin
		clk <= ~clk;
	end
endmodule
module register_test;

	reg clk;
	reg [1:0] rw;
	wire [15:0] oline;
	reg [15:0] iline;
	
	register register(clk, iline, oline, rw);

	initial begin
		$monitor("%t: rw = %b, o = %x, i = %x", $time, rw, oline, iline);
		
		clk <= 0;
		#10
		rw <= 2'b11;
		iline <= 16'h1234;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b11;
		iline <= 16'h4567;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b01;
		iline <= 16'h89AB;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10
		rw <= 2'b10;
		iline <= 16'hCDEF;
		#10
		rw <= 2'b00;
		iline <= 16'hz;
		#10 $finish;
	end
	
	always #10 begin
		clk <= ~clk;
	end
endmodule