data/full_repos/permissive/494490807/bench/ISCAS/Verilog2/s420.1_synth.v
data/verilator_xmls/6ac9e76e-51f0-402f-8a26-7b1dbc49592b.xml
module \s420.1.bench (\P.0 , \C.16 , \C.15 , \C.14 , \C.13 , \C.12 , \C.11 , \C.10 , \C.9 , \C.8 , \C.7 , \C.6 , \C.5 , \C.4 , \C.3 , \C.2 , \C.1 , \C.0 , Z);
input
  \P.0 ,
  \C.0 ,
  \C.1 ,
  \C.2 ,
  \C.3 ,
  \C.4 ,
  \C.5 ,
  \C.6 ,
  \C.7 ,
  \C.8 ,
  \C.9 ,
  \C.10 ,
  \C.11 ,
  \C.12 ,
  \C.13 ,
  \C.14 ,
  \C.15 ,
  \C.16 ;
output
  Z;
reg
  \X.10 ,
  \X.11 ,
  \X.12 ,
  \X.13 ,
  \X.14 ,
  \X.15 ,
  \X.16 ,
  \X.1 ,
  \X.2 ,
  \X.3 ,
  \X.4 ,
  \X.5 ,
  \X.6 ,
  \X.7 ,
  \X.8 ,
  \X.9 ;
wire
  I110,
  I111,
  I112,
  I113,
  \[26] ,
  \[27] ,
  \[42] ,
  \[28] ,
  \[29] ,
  \[44] ,
  I306,
  I307,
  I308,
  I309,
  \[46] ,
  \[47] ,
  \[48] ,
  \[49] ,
  I12,
  I13,
  I14,
  I15,
  \[30] ,
  \[16] ,
  \[31] ,
  \[17] ,
  \[32] ,
  \[18] ,
  \[19] ,
  I208,
  I209,
  I210,
  I211,
  \[50] ,
  \[37] ,
  \[52] ,
  \[53] ,
  \[54] ,
  \[20] ,
  \[55] ,
  \[21] ,
  \[22] ,
  \I1.2 ,
  \I1.3 ,
  \I1.4 ,
  \[23] ,
  \[24] ,
  \[25] ;
assign
  I110 = (~\[47]  & (~\I1.3  & \X.7 )) | (~\I1.3  & \X.8 ),
  I111 = (~\[47]  & ~\X.7 ) | (\[47]  & \X.7 ),
  I112 = (~\[48]  & ~\X.6 ) | (\[48]  & \X.6 ),
  I113 = (~\I1.2  & \X.5 ) | (\I1.2  & ~\X.5 ),
  \[26]  = I209,
  \[27]  = I210,
  \[42]  = (\[37]  & (~\X.9  & (~\X.10  & (~\X.6  & (~\X.7  & ~\X.8 ))))) | ((~\X.9  & (\X.10  & (~\X.6  & (~\X.7  & (~\X.8  & \C.10 ))))) | ((\X.9  & (~\X.6  & (~\X.7  & (~\X.8  & \C.9 )))) | ((~\X.6  & (~\X.7  & (\X.8  & \C.8 ))) | ((~\X.6  & (\X.7  & \C.7 )) | (\X.6  & \C.6 ))))),
  \[28]  = I211,
  \[29]  = I306,
  \[44]  = ~\X.1  | ~\P.0 ,
  I306 = (~\[52]  & ~\X.16 ) | (\[52]  & \X.16 ),
  I307 = (~\[53]  & ~\X.15 ) | (\[53]  & \X.15 ),
  I308 = (~\[54]  & ~\X.14 ) | (\[54]  & \X.14 ),
  I309 = (~\I1.4  & \X.13 ) | (\I1.4  & ~\X.13 ),
  Z = \[16] ,
  \[46]  = ~\X.2  | I14,
  \[47]  = ~\X.6  | I112,
  \[48]  = ~\I1.2  | ~\X.5 ,
  \[49]  = ~\X.10  | I210,
  I12 = (~\[46]  & (~\I1.2  & \X.3 )) | (~\I1.2  & \X.4 ),
  I13 = (~\[46]  & ~\X.3 ) | (\[46]  & \X.3 ),
  I14 = (~\[44]  & ~\X.2 ) | (\[44]  & \X.2 ),
  I15 = (~\X.1  & \P.0 ) | (\X.1  & ~\P.0 ),
  \[30]  = I307,
  \[16]  = (\[55]  & (~\X.1  & \P.0 )) | ((~\[44]  & \C.1 ) | (\C.0  & \P.0 )),
  \[31]  = I308,
  \[17]  = I12,
  \[32]  = I309,
  \[18]  = I13,
  \[19]  = I14,
  I208 = (~\[49]  & (~\I1.4  & \X.11 )) | (~\I1.4  & \X.12 ),
  I209 = (~\[49]  & ~\X.11 ) | (\[49]  & \X.11 ),
  I210 = (~\[50]  & ~\X.10 ) | (\[50]  & \X.10 ),
  I211 = (~\I1.3  & \X.9 ) | (\I1.3  & ~\X.9 ),
  \[50]  = ~\I1.3  | ~\X.9 ,
  \[37]  = (~\X.13  & (~\X.14  & (~\X.15  & (\X.16  & (~\X.11  & (~\X.12  & \C.16 )))))) | ((~\X.13  & (~\X.14  & (\X.15  & (~\X.11  & (~\X.12  & \C.15 ))))) | ((~\X.13  & (\X.14  & (~\X.11  & (~\X.12  & \C.14 )))) | ((\X.13  & (~\X.11  & (~\X.12  & \C.13 ))) | ((~\X.11  & (\X.12  & \C.12 )) | (\X.11  & \C.11 ))))),
  \[52]  = ~\X.15  | I307,
  \[53]  = ~\X.14  | I308,
  \[54]  = ~\I1.4  | ~\X.13 ,
  \[20]  = I15,
  \[55]  = (\[42]  & (~\X.5  & (~\X.2  & (~\X.3  & ~\X.4 )))) | ((\X.5  & (~\X.2  & (~\X.3  & (~\X.4  & \C.5 )))) | ((~\X.2  & (~\X.3  & (\X.4  & \C.4 ))) | ((~\X.2  & (\X.3  & \C.3 )) | (\X.2  & \C.2 )))),
  \[21]  = I110,
  \[22]  = I111,
  \I1.2  = ~\[44]  & (\X.2  & (\X.3  & \X.4 )),
  \I1.3  = ~\[48]  & (\X.6  & (\X.7  & \X.8 )),
  \I1.4  = ~\[50]  & (\X.10  & (\X.11  & \X.12 )),
  \[23]  = I112,
  \[24]  = I113,
  \[25]  = I208;
always begin
  \X.10  = \[27] ;
  \X.11  = \[26] ;
  \X.12  = \[25] ;
  \X.13  = \[32] ;
  \X.14  = \[31] ;
  \X.15  = \[30] ;
  \X.16  = \[29] ;
  \X.1  = \[20] ;
  \X.2  = \[19] ;
  \X.3  = \[18] ;
  \X.4  = \[17] ;
  \X.5  = \[24] ;
  \X.6  = \[23] ;
  \X.7  = \[22] ;
  \X.8  = \[21] ;
  \X.9  = \[28] ;
end
initial begin
  \X.10  = 0;
  \X.11  = 0;
  \X.12  = 0;
  \X.13  = 0;
  \X.14  = 0;
  \X.15  = 0;
  \X.16  = 0;
  \X.1  = 0;
  \X.2  = 0;
  \X.3  = 0;
  \X.4  = 0;
  \X.5  = 0;
  \X.6  = 0;
  \X.7  = 0;
  \X.8  = 0;
  \X.9  = 0;
end
endmodule
module \s420.1.bench (\P.0 , \C.16 , \C.15 , \C.14 , \C.13 , \C.12 , \C.11 , \C.10 , \C.9 , \C.8 , \C.7 , \C.6 , \C.5 , \C.4 , \C.3 , \C.2 , \C.1 , \C.0 , Z);

input
  \P.0 ,
  \C.0 ,
  \C.1 ,
  \C.2 ,
  \C.3 ,
  \C.4 ,
  \C.5 ,
  \C.6 ,
  \C.7 ,
  \C.8 ,
  \C.9 ,
  \C.10 ,
  \C.11 ,
  \C.12 ,
  \C.13 ,
  \C.14 ,
  \C.15 ,
  \C.16 ;
output
  Z;
reg
  \X.10 ,
  \X.11 ,
  \X.12 ,
  \X.13 ,
  \X.14 ,
  \X.15 ,
  \X.16 ,
  \X.1 ,
  \X.2 ,
  \X.3 ,
  \X.4 ,
  \X.5 ,
  \X.6 ,
  \X.7 ,
  \X.8 ,
  \X.9 ;
wire
  I110,
  I111,
  I112,
  I113,
  \[26] ,
  \[27] ,
  \[42] ,
  \[28] ,
  \[29] ,
  \[44] ,
  I306,
  I307,
  I308,
  I309,
  \[46] ,
  \[47] ,
  \[48] ,
  \[49] ,
  I12,
  I13,
  I14,
  I15,
  \[30] ,
  \[16] ,
  \[31] ,
  \[17] ,
  \[32] ,
  \[18] ,
  \[19] ,
  I208,
  I209,
  I210,
  I211,
  \[50] ,
  \[37] ,
  \[52] ,
  \[53] ,
  \[54] ,
  \[20] ,
  \[55] ,
  \[21] ,
  \[22] ,
  \I1.2 ,
  \I1.3 ,
  \I1.4 ,
  \[23] ,
  \[24] ,
  \[25] ;
assign
  I110 = (~\[47]  & (~\I1.3  & \X.7 )) | (~\I1.3  & \X.8 ),
  I111 = (~\[47]  & ~\X.7 ) | (\[47]  & \X.7 ),
  I112 = (~\[48]  & ~\X.6 ) | (\[48]  & \X.6 ),
  I113 = (~\I1.2  & \X.5 ) | (\I1.2  & ~\X.5 ),
  \[26]  = I209,
  \[27]  = I210,
  \[42]  = (\[37]  & (~\X.9  & (~\X.10  & (~\X.6  & (~\X.7  & ~\X.8 ))))) | ((~\X.9  & (\X.10  & (~\X.6  & (~\X.7  & (~\X.8  & \C.10 ))))) | ((\X.9  & (~\X.6  & (~\X.7  & (~\X.8  & \C.9 )))) | ((~\X.6  & (~\X.7  & (\X.8  & \C.8 ))) | ((~\X.6  & (\X.7  & \C.7 )) | (\X.6  & \C.6 ))))),
  \[28]  = I211,
  \[29]  = I306,
  \[44]  = ~\X.1  | ~\P.0 ,
  I306 = (~\[52]  & ~\X.16 ) | (\[52]  & \X.16 ),
  I307 = (~\[53]  & ~\X.15 ) | (\[53]  & \X.15 ),
  I308 = (~\[54]  & ~\X.14 ) | (\[54]  & \X.14 ),
  I309 = (~\I1.4  & \X.13 ) | (\I1.4  & ~\X.13 ),
  Z = \[16] ,
  \[46]  = ~\X.2  | I14,
  \[47]  = ~\X.6  | I112,
  \[48]  = ~\I1.2  | ~\X.5 ,
  \[49]  = ~\X.10  | I210,
  I12 = (~\[46]  & (~\I1.2  & \X.3 )) | (~\I1.2  & \X.4 ),
  I13 = (~\[46]  & ~\X.3 ) | (\[46]  & \X.3 ),
  I14 = (~\[44]  & ~\X.2 ) | (\[44]  & \X.2 ),
  I15 = (~\X.1  & \P.0 ) | (\X.1  & ~\P.0 ),
  \[30]  = I307,
  \[16]  = (\[55]  & (~\X.1  & \P.0 )) | ((~\[44]  & \C.1 ) | (\C.0  & \P.0 )),
  \[31]  = I308,
  \[17]  = I12,
  \[32]  = I309,
  \[18]  = I13,
  \[19]  = I14,
  I208 = (~\[49]  & (~\I1.4  & \X.11 )) | (~\I1.4  & \X.12 ),
  I209 = (~\[49]  & ~\X.11 ) | (\[49]  & \X.11 ),
  I210 = (~\[50]  & ~\X.10 ) | (\[50]  & \X.10 ),
  I211 = (~\I1.3  & \X.9 ) | (\I1.3  & ~\X.9 ),
  \[50]  = ~\I1.3  | ~\X.9 ,
  \[37]  = (~\X.13  & (~\X.14  & (~\X.15  & (\X.16  & (~\X.11  & (~\X.12  & \C.16 )))))) | ((~\X.13  & (~\X.14  & (\X.15  & (~\X.11  & (~\X.12  & \C.15 ))))) | ((~\X.13  & (\X.14  & (~\X.11  & (~\X.12  & \C.14 )))) | ((\X.13  & (~\X.11  & (~\X.12  & \C.13 ))) | ((~\X.11  & (\X.12  & \C.12 )) | (\X.11  & \C.11 ))))),
  \[52]  = ~\X.15  | I307,
  \[53]  = ~\X.14  | I308,
  \[54]  = ~\I1.4  | ~\X.13 ,
  \[20]  = I15,
  \[55]  = (\[42]  & (~\X.5  & (~\X.2  & (~\X.3  & ~\X.4 )))) | ((\X.5  & (~\X.2  & (~\X.3  & (~\X.4  & \C.5 )))) | ((~\X.2  & (~\X.3  & (\X.4  & \C.4 ))) | ((~\X.2  & (\X.3  & \C.3 )) | (\X.2  & \C.2 )))),
  \[21]  = I110,
  \[22]  = I111,
  \I1.2  = ~\[44]  & (\X.2  & (\X.3  & \X.4 )),
  \I1.3  = ~\[48]  & (\X.6  & (\X.7  & \X.8 )),
  \I1.4  = ~\[50]  & (\X.10  & (\X.11  & \X.12 )),
  \[23]  = I112,
  \[24]  = I113,
  \[25]  = I208;
always begin
  \X.10  = \[27] ;
  \X.11  = \[26] ;
  \X.12  = \[25] ;
  \X.13  = \[32] ;
  \X.14  = \[31] ;
  \X.15  = \[30] ;
  \X.16  = \[29] ;
  \X.1  = \[20] ;
  \X.2  = \[19] ;
  \X.3  = \[18] ;
  \X.4  = \[17] ;
  \X.5  = \[24] ;
  \X.6  = \[23] ;
  \X.7  = \[22] ;
  \X.8  = \[21] ;
  \X.9  = \[28] ;
end
initial begin
  \X.10  = 0;
  \X.11  = 0;
  \X.12  = 0;
  \X.13  = 0;
  \X.14  = 0;
  \X.15  = 0;
  \X.16  = 0;
  \X.1  = 0;
  \X.2  = 0;
  \X.3  = 0;
  \X.4  = 0;
  \X.5  = 0;
  \X.6  = 0;
  \X.7  = 0;
  \X.8  = 0;
  \X.9  = 0;
end
endmodule