data/full_repos/permissive/503053625/fpga_projects/SPGD/src/LED_CONTROLLER.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/LED_CONTROLLER.v:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                               : ... In instance LED_CONTROLLER\n    reg [LED_WIDTH-1:0] LED=8\'b00000000;\n                            ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LED_CONTROLLER
#(
    parameter LED_WIDTH = 1
)
(
    input [LED_WIDTH - 1:0] val,
    output [LED_WIDTH - 1:0] led_o
);

    integer i;
    reg [LED_WIDTH-1:0] LED=8'b00000000;
    assign led_o = LED;
    localparam
        ON = 1'b1,
        OFF = 1'b0;

    always @(val) 
    begin
        for(i = 0; i < LED_WIDTH; i = i + 1) begin
            case (val[i])
                1'b1: LED[i] = ON;
                1'b0: LED[i] = OFF;
                default: LED[i] = 1'b0;
            endcase
        end
    end
endmodule
module LED_CONTROLLER
#(
    parameter LED_WIDTH = 1
)
(
    input [LED_WIDTH - 1:0] val,
    output [LED_WIDTH - 1:0] led_o
);


    integer i;
    reg [LED_WIDTH-1:0] LED=8'b00000000;
    assign led_o = LED;
    localparam
        ON = 1'b1,
        OFF = 1'b0;

    always @(val) 
    begin
        for(i = 0; i < LED_WIDTH; i = i + 1) begin
            case (val[i])
                1'b1: LED[i] = ON;
                1'b0: LED[i] = OFF;
                default: LED[i] = 1'b0;
            endcase
        end
    end
endmodule