data/full_repos/permissive/461569093/Mini ALU/equal.v
1: b'%Error: Cannot find file containing module: ALU,data/full_repos/permissive/461569093\n        ... Looked in:\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.v\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.sv\n             ALU,data/full_repos/permissive/461569093\n             ALU,data/full_repos/permissive/461569093.v\n             ALU,data/full_repos/permissive/461569093.sv\n             obj_dir/ALU,data/full_repos/permissive/461569093\n             obj_dir/ALU,data/full_repos/permissive/461569093.v\n             obj_dir/ALU,data/full_repos/permissive/461569093.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461569093/Mini\n%Error: Cannot find file containing module: ALU/equal.v\n%Error: Exiting due to 3 error(s)\n'
module equal
   (
    input  wire[1:0] a, b,
    output wire aeqb
   );


   wire e0, e1;




   basis eq_bit0_unit (.i0(a[0]), .i1(b[0]), .eq(e0));
   



   basis eq_bit1_unit (.eq(e1), .i0(a[1]), .i1(b[1]));


   assign aeqb = e0 & e1;

endmodule
module equal
   (
    input  wire[1:0] a, b,
    output wire aeqb
   );



   wire e0, e1;




   basis eq_bit0_unit (.i0(a[0]), .i1(b[0]), .eq(e0));
   



   basis eq_bit1_unit (.eq(e1), .i0(a[1]), .i1(b[1]));


   assign aeqb = e0 & e1;

endmodule