data/full_repos/permissive/458935738/starter/speedctl.v
1: b"%Error: data/full_repos/permissive/458935738/starter/speedctl.v:26: syntax error, unexpected localparam, expecting ';'\nlocalparam IDLE = 2'b00;\n^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module speedctl (
    input clk,
    input enable,
    input encoder,
    input [15:0] deg_s,
    output wire PWM
);

localparam TICKS = 32'd16000000



localparam IDLE = 2'b00;
localparam COUNT = 2'b01;
localparam UPDATE = 2'b10;
reg [1:0] current_state, next_state;

reg enc1, enc2, enc3;
wire pulse;
always @(posedge clk) begin
    enc1 <= encoder;
    enc2 <= enc1;
    enc3 <= enc2;
end
assign pulse = ~enc3 & enc2;

reg signed [15:0] speed;
reg signed [15:0] acceleration;
reg [31:0] timer, timer_next;
reg signed [15:0] counter, counter_next;

pwm pwm_generator(clk, enable, speed, PWM);

always @(posedge clk) begin

end

always @(*) begin







    case (current_state)
        IDLE: begin
            next_state = enable ? COUNT : IDLE;
        end

        COUNT: begin

        end

        UPDATE: begin

        end
    endcase
end

endmodule
module speedctl (
    input clk,
    input enable,
    input encoder,
    input [15:0] deg_s,
    output wire PWM
);


localparam TICKS = 32'd16000000



localparam IDLE = 2'b00;
localparam COUNT = 2'b01;
localparam UPDATE = 2'b10;
reg [1:0] current_state, next_state;

reg enc1, enc2, enc3;
wire pulse;
always @(posedge clk) begin
    enc1 <= encoder;
    enc2 <= enc1;
    enc3 <= enc2;
end
assign pulse = ~enc3 & enc2;

reg signed [15:0] speed;
reg signed [15:0] acceleration;
reg [31:0] timer, timer_next;
reg signed [15:0] counter, counter_next;

pwm pwm_generator(clk, enable, speed, PWM);

always @(posedge clk) begin

end

always @(*) begin







    case (current_state)
        IDLE: begin
            next_state = enable ? COUNT : IDLE;
        end

        COUNT: begin

        end

        UPDATE: begin

        end
    endcase
end

endmodule