data/full_repos/permissive/487110065/ClockDivider.v
data/verilator_xmls/da10dfc0-e85b-4018-b1cc-9905d5dec93f.xml
module ClockDivider(
    clockIn,
    halt,
    clockOut
);

input clockIn;
input halt;

output reg clockOut;

reg [27:0] counter = 28'd0;
parameter DIVISOR = 28'd1;






always @(posedge clockIn) begin
    if (halt) begin
        counter = counter;
        clockOut = clockOut;
    end else begin
        counter = counter + 28'b1;
        if (counter >= DIVISOR) begin
            counter = 28'b0;
            clockOut = ~clockOut;
        end
    end
end

endmodule
module ClockDivider(
    clockIn,
    halt,
    clockOut
);


input clockIn;
input halt;

output reg clockOut;

reg [27:0] counter = 28'd0;
parameter DIVISOR = 28'd1;






always @(posedge clockIn) begin
    if (halt) begin
        counter = counter;
        clockOut = clockOut;
    end else begin
        counter = counter + 28'b1;
        if (counter >= DIVISOR) begin
            counter = 28'b0;
            clockOut = ~clockOut;
        end
    end
end

endmodule