data/full_repos/permissive/481044442/BDCDrv/pwm_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:60: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                           : ... In instance pwm_module\n  counter<=12\'d0;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:62: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                           : ... In instance pwm_module\n  counter<=12\'d0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:90: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                           : ... In instance pwm_module\n     i<=12\'d0;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:96: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                           : ... In instance pwm_module\n                 i<=12\'d0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:109: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                            : ... In instance pwm_module\n                  i<=12\'d0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:122: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                            : ... In instance pwm_module\n                  i<=12\'d0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/pwm_module.v:135: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                            : ... In instance pwm_module\n                   i<=12\'d0;\n                    ^~\n%Error: Exiting due to 7 warning(s)\n'
module pwm_module(clk,reset,Start_En_Sig,work_mode,pwm1,pwm2,Done_Sig);
input clk;
input reset;
input Start_En_Sig;
input [3:0] work_mode;
output reg pwm1;
output reg pwm2;
output reg Done_Sig;



reg [27:0] counter_1hz;
wire clk_1hz;
reg [3:0] timers_5s;
reg [19:0] updated_threshold;
always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					counter_1hz<=28'd0;
					timers_5s<=4'd0;
					updated_threshold<=20'd491520;
				end
	else if(counter_1hz==28'd49152000)	begin
											counter_1hz<=28'd0;

											if(timers_5s==4'd1)	begin
																	timers_5s<=4'd0;
																	if((updated_threshold-20'd200000)>=20'd492) 
																		updated_threshold<=updated_threshold-20'd200000;
																	else
																		updated_threshold<=20'd491520;
																end
											else
												timers_5s<=timers_5s+1'b1;
										end
	else
		counter_1hz<=counter_1hz+1'b1;
end
assign clk_1hz=(counter_1hz==28'd49152000)?1'b1:1'b0;












reg [19:0] counter;
wire clk_100khz;

wire duty_cycle_pulse;

always@(posedge clk or posedge reset)
begin
	if(reset) 
		counter<=12'd0;
	else if(counter==updated_threshold)	
		counter<=12'd0;
	else
		counter<=counter+1'b1;
end

assign clk_100khz=(counter==updated_threshold)?1'b1:1'b0;

assign duty_cycle_pulse=(counter==updated_threshold/2)?1'b1:1'b0;









parameter i_THRESHOLD_Tiny=28'd1000;
parameter i_THRESHOLD_Small=28'd2000;
parameter i_THRESHOLD_Normay=28'd5000;
parameter i_THRESHOLD_Large=28'd10000;
reg [27:0] i;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
					pwm1<=1'b0;
					pwm2<=1'b0;
					Done_Sig<=1'b0;
					i<=12'd0;
			  end
	else if(Start_En_Sig) begin
							case(work_mode)
								4'd0: begin
										if(i==i_THRESHOLD_Tiny) begin
																	i<=12'd0;
																	pwm2<=1'b0;
																	Done_Sig<=1'b1;
										    					end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
			              				end
								4'd1: begin
										if(i==i_THRESHOLD_Small) 	begin
																		i<=12'd0;
																		pwm2<=1'b0;
																		Done_Sig<=1'b1;
										    						end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
									  end
								4'd2: begin
										if(i==i_THRESHOLD_Normay) 	begin
																		i<=12'd0;
																		pwm2<=1'b0;
																		Done_Sig<=1'b1;
										    						end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
									  end
								4'd3: begin
											if(i==i_THRESHOLD_Normay) 	begin
																			i<=12'd0;
																			pwm2<=1'b0;
																			Done_Sig<=1'b1;
										    							end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end
									  end
								4'd15: 	begin
												if(clk_100khz)
													pwm2<=1'b1;
												else if(duty_cycle_pulse)
													pwm2<=1'b0;
										end
								default: begin 
											pwm2<=1'b0;
								  		 end
							endcase
						end
	else begin
			pwm1<=1'b0;
			pwm2<=1'b0;
			Done_Sig<=1'b0;
	     end
end
endmodule
module pwm_module(clk,reset,Start_En_Sig,work_mode,pwm1,pwm2,Done_Sig);

input clk;
input reset;
input Start_En_Sig;
input [3:0] work_mode;
output reg pwm1;
output reg pwm2;
output reg Done_Sig;



reg [27:0] counter_1hz;
wire clk_1hz;
reg [3:0] timers_5s;
reg [19:0] updated_threshold;
always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					counter_1hz<=28'd0;
					timers_5s<=4'd0;
					updated_threshold<=20'd491520;
				end
	else if(counter_1hz==28'd49152000)	begin
											counter_1hz<=28'd0;

											if(timers_5s==4'd1)	begin
																	timers_5s<=4'd0;
																	if((updated_threshold-20'd200000)>=20'd492) 
																		updated_threshold<=updated_threshold-20'd200000;
																	else
																		updated_threshold<=20'd491520;
																end
											else
												timers_5s<=timers_5s+1'b1;
										end
	else
		counter_1hz<=counter_1hz+1'b1;
end
assign clk_1hz=(counter_1hz==28'd49152000)?1'b1:1'b0;












reg [19:0] counter;
wire clk_100khz;

wire duty_cycle_pulse;

always@(posedge clk or posedge reset)
begin
	if(reset) 
		counter<=12'd0;
	else if(counter==updated_threshold)	
		counter<=12'd0;
	else
		counter<=counter+1'b1;
end

assign clk_100khz=(counter==updated_threshold)?1'b1:1'b0;

assign duty_cycle_pulse=(counter==updated_threshold/2)?1'b1:1'b0;









parameter i_THRESHOLD_Tiny=28'd1000;
parameter i_THRESHOLD_Small=28'd2000;
parameter i_THRESHOLD_Normay=28'd5000;
parameter i_THRESHOLD_Large=28'd10000;
reg [27:0] i;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
					pwm1<=1'b0;
					pwm2<=1'b0;
					Done_Sig<=1'b0;
					i<=12'd0;
			  end
	else if(Start_En_Sig) begin
							case(work_mode)
								4'd0: begin
										if(i==i_THRESHOLD_Tiny) begin
																	i<=12'd0;
																	pwm2<=1'b0;
																	Done_Sig<=1'b1;
										    					end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
			              				end
								4'd1: begin
										if(i==i_THRESHOLD_Small) 	begin
																		i<=12'd0;
																		pwm2<=1'b0;
																		Done_Sig<=1'b1;
										    						end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
									  end
								4'd2: begin
										if(i==i_THRESHOLD_Normay) 	begin
																		i<=12'd0;
																		pwm2<=1'b0;
																		Done_Sig<=1'b1;
										    						end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end	
									  end
								4'd3: begin
											if(i==i_THRESHOLD_Normay) 	begin
																			i<=12'd0;
																			pwm2<=1'b0;
																			Done_Sig<=1'b1;
										    							end
										else begin
												if(clk_100khz)
														begin pwm2<=1'b1; i<=i+1'b1; end
												else if(duty_cycle_pulse)
														begin pwm2<=1'b0; end
								 			 end
									  end
								4'd15: 	begin
												if(clk_100khz)
													pwm2<=1'b1;
												else if(duty_cycle_pulse)
													pwm2<=1'b0;
										end
								default: begin 
											pwm2<=1'b0;
								  		 end
							endcase
						end
	else begin
			pwm1<=1'b0;
			pwm2<=1'b0;
			Done_Sig<=1'b0;
	     end
end
endmodule