data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/sync_output.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/sync_output.sv:54: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                : ... In instance sync_output\n        out_clk   <= 2\'b00;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/sync_output.sv:55: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                : ... In instance sync_output\n        out_clk_n <= 2\'b00;\n                  ^~\n%Error: Exiting due to 2 warning(s)\n'
module sync_output #(
    parameter   GEN_CLOCK   = 0
) (
    input  wire                                           in_rst,
    input  wire                                           in_clk, 

    output reg                                            out_clk,
    output reg                                            out_clk_n 
);


reg out_clk_low = '0;
reg new_clk = '0;
reg new_clk_n = '0;

reg rstn_clk_l = '0;
reg rstn_clk   = '0;

always @ (posedge in_clk or negedge in_rst)
    if(!in_rst) begin
        rstn_clk   <= '0;
        rstn_clk_l <= '0;
    end
    else begin
        rstn_clk   <= rstn_clk_l;
        rstn_clk_l <= 1'b1;
    end



always @ (posedge in_clk or negedge in_rst)
    if(!in_rst) begin
        out_clk   <= 2'b00;
        out_clk_n <= 2'b00;
    end
    else begin


        {out_clk,out_clk_n} <= {out_clk,out_clk_n} + 2'b01;
    end
    
assign out_clk   = new_clk;
assign out_clk_n = new_clk_n;    


endmodule
module sync_output #(
    parameter   GEN_CLOCK   = 0
) (
    input  wire                                           in_rst,
    input  wire                                           in_clk, 

    output reg                                            out_clk,
    output reg                                            out_clk_n 
);



reg out_clk_low = '0;
reg new_clk = '0;
reg new_clk_n = '0;

reg rstn_clk_l = '0;
reg rstn_clk   = '0;

always @ (posedge in_clk or negedge in_rst)
    if(!in_rst) begin
        rstn_clk   <= '0;
        rstn_clk_l <= '0;
    end
    else begin
        rstn_clk   <= rstn_clk_l;
        rstn_clk_l <= 1'b1;
    end



always @ (posedge in_clk or negedge in_rst)
    if(!in_rst) begin
        out_clk   <= 2'b00;
        out_clk_n <= 2'b00;
    end
    else begin


        {out_clk,out_clk_n} <= {out_clk,out_clk_n} + 2'b01;
    end
    
assign out_clk   = new_clk;
assign out_clk_n = new_clk_n;    


endmodule