data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:30: Signal definition not found, creating implicitly: \'load_ir\'\n  ir ir_0 (clk, reset, load_ir, ins, cur_ins);\n                       ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:31: Signal definition not found, creating implicitly: \'wr_reg\'\n  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);\n                                                                                                          ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:2: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_0 (clk, reset, load, din[\'h0], dout[\'h0]);\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab8/studentCopy(referRough),data/full_repos/permissive/443770883/dfrl\n             data/full_repos/permissive/443770883/lab8/studentCopy(referRough),data/full_repos/permissive/443770883/dfrl.v\n             data/full_repos/permissive/443770883/lab8/studentCopy(referRough),data/full_repos/permissive/443770883/dfrl.sv\n             dfrl\n             dfrl.v\n             dfrl.sv\n             obj_dir/dfrl\n             obj_dir/dfrl.v\n             obj_dir/dfrl.sv\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:3: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_1 (clk, reset, load, din[\'h1], dout[\'h1]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:4: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_2 (clk, reset, load, din[\'h2], dout[\'h2]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:5: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_3 (clk, reset, load, din[\'h3], dout[\'h3]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:6: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_4 (clk, reset, load, din[\'h4], dout[\'h4]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:7: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_5 (clk, reset, load, din[\'h5], dout[\'h5]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:8: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_6 (clk, reset, load, din[\'h6], dout[\'h6]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:9: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_7 (clk, reset, load, din[\'h7], dout[\'h7]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:10: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_8 (clk, reset, load, din[\'h8], dout[\'h8]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:11: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_9 (clk, reset, load, din[\'h9], dout[\'h9]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:12: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_a (clk, reset, load, din[\'ha], dout[\'ha]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:13: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_b (clk, reset, load, din[\'hb], dout[\'hb]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:14: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_c (clk, reset, load, din[\'hc], dout[\'hc]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:15: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_d (clk, reset, load, din[\'hd], dout[\'hd]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:16: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_e (clk, reset, load, din[\'he], dout[\'he]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:17: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_f (clk, reset, load, din[\'hf], dout[\'hf]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:29: Cannot find file containing module: \'pc\'\n  pc pc_0 (clk, reset, pc_inc, 1\'b0, 1\'b0, 16\'b0, addr);\n  ^~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/mproc.v:32: Cannot find file containing module: \'reg_alu\'\n  reg_alu reg_alu_0 (clk, reset, 1\'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16\'b0, d_out_a, d_out_b, cout);\n  ^~~~~~~\n%Error: Exiting due to 18 error(s), 2 warning(s)\n'
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);



endmodule
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);




endmodule