data/full_repos/permissive/521337848/Hardware/GRAPHICS/VRAM.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VRAM.v:29: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'spriteRAM\'\nmodule spriteRAM(\n       ^~~~~~~~~\n                                                                                   : ... Top module \'VRAM\'\nmodule VRAM(\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VRAM.v:20: Bit extraction of array[1023:0] requires 10 bit index, not 9 bits.\n                                                                                : ... In instance spriteRAM\n if(w) memory[waddr] <= save;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VRAM.v:22: Bit extraction of array[1023:0] requires 10 bit index, not 9 bits.\n                                                                                : ... In instance spriteRAM\n out <= memory[addr];\n              ^\n%Error: Exiting due to 3 warning(s)\n'
module VRAM(
	input clk,
	input[12:0] addr,
	
	input[12:0] waddr,
	input w,
	input[7:0] in,
	
	input ws,
	input sel,
	input[3:0] ins,
	
	output reg[7:0] out
);

reg[3:0] memory1[6143:0];
reg[3:0] memory2[6143:0];

localparam A = 2'd0;
localparam B = 2'd1;
localparam C = 2'd2;
localparam D = 2'd3;

	
	
always@(posedge clk)begin
		
		if(ws)begin
			if(sel) memory2[waddr-2048] <= ins;
			else memory1[waddr-2048] <= ins;
		end
		if(w) begin
			memory1[waddr-2048] <= in[3:0];
			memory2[waddr-2048] <= in[7:4];
		end
		
		out <= {memory2[addr-2048],memory1[addr-2048]};
	end
endmodule
module VRAM(
	input clk,
	input[12:0] addr,
	
	input[12:0] waddr,
	input w,
	input[7:0] in,
	
	input ws,
	input sel,
	input[3:0] ins,
	
	output reg[7:0] out
);


reg[3:0] memory1[6143:0];
reg[3:0] memory2[6143:0];

localparam A = 2'd0;
localparam B = 2'd1;
localparam C = 2'd2;
localparam D = 2'd3;

	
	
always@(posedge clk)begin
		
		if(ws)begin
			if(sel) memory2[waddr-2048] <= ins;
			else memory1[waddr-2048] <= ins;
		end
		if(w) begin
			memory1[waddr-2048] <= in[3:0];
			memory2[waddr-2048] <= in[7:4];
		end
		
		out <= {memory2[addr-2048],memory1[addr-2048]};
	end
endmodule