data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v
1: b'%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:15: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A+B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:21: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A XOR B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:27: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A-B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:28: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:33: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A>B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:34: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:39: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A NOR B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:40: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu.v:45: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d, A =%32b, B=%32b, A OR B=%32b,S=%3b",$time, A, B,F,S);\n ^~~~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_Alu();
	
	reg [31:0]A,B;
	reg Ci;
	reg [2:0]S;
	wire[31:0]F;
	wire Co;
	alu_32_bit ahmet (A,B,S[0],S[1],S[2],Ci,F,Co);
initial begin
	A = 32'b00000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b000;
	$monitor("time = %2d, A =%32b, B=%32b, A+B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b00000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b001;
	$monitor("time = %2d, A =%32b, B=%32b, A XOR B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b1; 
	S=3'b010;
	$monitor("time = %2d, A =%32b, B=%32b, A-B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b100;
	$monitor("time = %2d, A =%32b, B=%32b, A>B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b101;
	$monitor("time = %2d, A =%32b, B=%32b, A NOR B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b111;
	$monitor("time = %2d, A =%32b, B=%32b, A OR B=%32b,S=%3b",$time, A, B,F,S);
end
endmodule
module test_bench_Alu();

	
	reg [31:0]A,B;
	reg Ci;
	reg [2:0]S;
	wire[31:0]F;
	wire Co;
	alu_32_bit ahmet (A,B,S[0],S[1],S[2],Ci,F,Co);
initial begin
	A = 32'b00000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b000;
	$monitor("time = %2d, A =%32b, B=%32b, A+B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b00000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b001;
	$monitor("time = %2d, A =%32b, B=%32b, A XOR B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b1; 
	S=3'b010;
	$monitor("time = %2d, A =%32b, B=%32b, A-B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b100;
	$monitor("time = %2d, A =%32b, B=%32b, A>B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b101;
	$monitor("time = %2d, A =%32b, B=%32b, A NOR B=%32b,S=%3b",$time, A, B,F,S);
#`DELAY;
	A = 32'b10000001000000010000000100000001;
	B = 32'b01100001011000010110000101100001; 
	Ci=1'b0; 
	S=3'b111;
	$monitor("time = %2d, A =%32b, B=%32b, A OR B=%32b,S=%3b",$time, A, B,F,S);
end
endmodule