data/full_repos/permissive/410481985/src/module/vsdmemsoc.v
1: b"%Error: data/full_repos/permissive/410481985/src/module/vsdmemsoc.v:19: Cannot find file containing module: 'controller'\n    controller cntlr (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/410481985/src/module,data/full_repos/permissive/410481985/controller\n             data/full_repos/permissive/410481985/src/module,data/full_repos/permissive/410481985/controller.v\n             data/full_repos/permissive/410481985/src/module,data/full_repos/permissive/410481985/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/410481985/src/module/vsdmemsoc.v:35: Cannot find file containing module: 'sram_32_256_sky130A'\n    sram_32_256_sky130A mem (\n    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module vsdmemsoc (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    output [9:0] OUT,
    input CLK,
    input reset,
    input init_en,
    input [7:0] init_addr,
    input [31:0] init_data
);

    wire        mem_wr;
    wire [7:0]  mem_addr;
    
    wire [31:0] imem_data;

    controller cntlr (
`ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
`endif
        .OUT(OUT),
        .CLK(CLK),
        .reset(reset),

        .mem_wr(mem_wr),
        .mem_addr(mem_addr),
        .init_en(init_en),
        .init_addr(init_addr),
        .imem_data(imem_data)
    );

    sram_32_256_sky130A mem (
`ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
`endif
        .clk0(CLK),
        .csb0(1'b0),
        .web0(mem_wr),
        .addr0(mem_addr),
        .din0(init_data),
        .dout0(imem_data)
    );
    
endmodule
module vsdmemsoc (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    output [9:0] OUT,
    input CLK,
    input reset,
    input init_en,
    input [7:0] init_addr,
    input [31:0] init_data
);


    wire        mem_wr;
    wire [7:0]  mem_addr;
    
    wire [31:0] imem_data;

    controller cntlr (
`ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
`endif
        .OUT(OUT),
        .CLK(CLK),
        .reset(reset),

        .mem_wr(mem_wr),
        .mem_addr(mem_addr),
        .init_en(init_en),
        .init_addr(init_addr),
        .imem_data(imem_data)
    );

    sram_32_256_sky130A mem (
`ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
`endif
        .clk0(CLK),
        .csb0(1'b0),
        .web0(mem_wr),
        .addr0(mem_addr),
        .din0(init_data),
        .dout0(imem_data)
    );
    
endmodule