data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #10 rst = 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #10 rst = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #1000000000      \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n%Error: data/full_repos/permissive/434840709/lab1/Flash_led_top_tb.v:41: Cannot find file containing module: \'flash_led_top\'\n    flash_led_top flash_led_top(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab1,data/full_repos/permissive/434840709/flash_led_top\n             data/full_repos/permissive/434840709/lab1,data/full_repos/permissive/434840709/flash_led_top.v\n             data/full_repos/permissive/434840709/lab1,data/full_repos/permissive/434840709/flash_led_top.sv\n             flash_led_top\n             flash_led_top.v\n             flash_led_top.sv\n             obj_dir/flash_led_top\n             obj_dir/flash_led_top.v\n             obj_dir/flash_led_top.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module flash_led_top_tb;
 	 	reg clk,rst,sw0;
 	 	wire [15:0] led;
 	  	initial begin
 	 		clk = 1'b0;
 	 		rst = 1'b1;
 	 		sw0 = 1'b0;
 	 		#10 rst = 1'b0;
 	 		#10 rst = 1'b1;
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		sw0 = 1'b1;
 	 	end
 	 	always #5 clk <= ~clk;
 	 	flash_led_top flash_led_top(
 	 		.clk( clk ),
 	 		.rst_n( rst ),
 	 		.sw0( sw0 ),
 	 		.led( led )
 	 	);
endmodule
module flash_led_top_tb;

 	 	reg clk,rst,sw0;
 	 	wire [15:0] led;
 	  	initial begin
 	 		clk = 1'b0;
 	 		rst = 1'b1;
 	 		sw0 = 1'b0;
 	 		#10 rst = 1'b0;
 	 		#10 rst = 1'b1;
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		sw0 = 1'b1;
 	 	end
 	 	always #5 clk <= ~clk;
 	 	flash_led_top flash_led_top(
 	 		.clk( clk ),
 	 		.rst_n( rst ),
 	 		.sw0( sw0 ),
 	 		.led( led )
 	 	);
endmodule