data/full_repos/permissive/514437299/digital/rtl/clkg.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514437299/digital/rtl/clkg.v:151: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'mux8\'\nmodule mux8(input  wire [2:0] i_sel,\n       ^~~~\n                                                                              : ... Top module \'clkg\'\nmodule clkg #(parameter NINVERTER = 66) (\n       ^~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:65: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:217: Cannot find file containing module: \'INVLONG_OSC37\'\n  INVLONG_OSC37 U_CLK_OSC(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:223: Cannot find file containing module: \'INVD2\'\n  INVD2 U_CLK_OSC_DRV(\n  ^~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:227: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_OSC(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:233: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_FCK(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:364: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_MEM(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:370: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_RNG(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:376: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_SMP(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:382: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_CMO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:397: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_DLO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:407: Cannot find file containing module: \'CKLHQD1\'\n  CKLHQD1 U_CLK_GATE_PCH(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:413: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_PLN(\n  ^~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module lfsr8(input wire        clk,
             input wire        rst_n,
             input wire        i_en,
             input wire        i_ptb,
             input wire        i_ptb_valid,
             input wire        i_si,
             input wire        i_sr_valid,
             output reg [7:0]  o_state,
             output wire       o_p25,
             output wire       o_p50,
             output wire       o_p75);

  wire feedback;


  assign feedback = (~(o_state[7] ^
                       o_state[5] ^
                       o_state[4] ^
                       o_state[3])) ^ (i_ptb & i_ptb_valid);


  assign o_p25 = o_state[7] & o_state[6];
  assign o_p50 = o_state[7] ^ o_state[6];
  assign o_p75 = o_state[7] | o_state[6];
  
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      o_state <= 8'b0;
    else
      if (i_en) begin

        if ((~(&o_state[6:0])) || (~feedback))
          o_state <= {o_state[6:0], feedback};
      end else if (i_sr_valid) o_state <= {o_state[6:0], i_si};

endmodule
module lfsr8(input wire        clk,
             input wire        rst_n,
             input wire        i_en,
             input wire        i_ptb,
             input wire        i_ptb_valid,
             input wire        i_si,
             input wire        i_sr_valid,
             output reg [7:0]  o_state,
             output wire       o_p25,
             output wire       o_p50,
             output wire       o_p75);


  wire feedback;


  assign feedback = (~(o_state[7] ^
                       o_state[5] ^
                       o_state[4] ^
                       o_state[3])) ^ (i_ptb & i_ptb_valid);


  assign o_p25 = o_state[7] & o_state[6];
  assign o_p50 = o_state[7] ^ o_state[6];
  assign o_p75 = o_state[7] | o_state[6];
  
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      o_state <= 8'b0;
    else
      if (i_en) begin

        if ((~(&o_state[6:0])) || (~feedback))
          o_state <= {o_state[6:0], feedback};
      end else if (i_sr_valid) o_state <= {o_state[6:0], i_si};

endmodule