data/full_repos/permissive/434840709/USTB_verilog_elevator/src/counter.v
data/verilator_xmls/aa6335c6-e40b-4eae-b449-176762d49d72.xml
module counter(
    input clk,
    input start,
    input [7:0] m_time,
    output done
);
    reg [7:0] count = 0;
    assign done = start && count >= m_time;

    always @(posedge clk) begin
       if(start == 0) begin
           count <= 0;
       end
       else count <= done ? count : count + 1;
    end

endmodule
module counter(
    input clk,
    input start,
    input [7:0] m_time,
    output done
);

    reg [7:0] count = 0;
    assign done = start && count >= m_time;

    always @(posedge clk) begin
       if(start == 0) begin
           count <= 0;
       end
       else count <= done ? count : count + 1;
    end

endmodule