data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#t clk= ~clk;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:28: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:30: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:37: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:41: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:45: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:53: syntax error, unexpected \'@\'\n@(negedge clk)\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:57: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:60: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:62: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:65: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:73: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:77: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:81: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:84: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:86: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:93: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:97: syntax error, unexpected \'@\'\n@(negedge clk)\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:102: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:105: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:108: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#10 t1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_fsm_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: Exiting due to 20 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module router_fsm_tb();

reg clk,resetn,pkt_valid,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid;
reg [1:0] data_in;
wire  write_enb_reg,detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,busy;

router_fsm dut(clk,resetn,pkt_valid,data_in,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid,write_enb_reg,detect_add,ld_state,
                   laf_state,lfd_state,full_state,rst_int_reg,busy);
parameter t=10;

always
begin
#t clk= ~clk;
end

task initialize;
begin
resetn=1'b1;
{clk,pkt_valid,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid}=0;
end
endtask

task reset;
begin
@(negedge clk);
   resetn= 1'b0;
@(negedge clk);
   resetn=1'b1;
end
endtask

task t1;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b01;
fifo_empty_1=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

task t2;
begin
@(negedge clk)
pkt_valid=1;
data_in=2'b00;
fifo_empty_0=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=1'b1;
@(negedge clk);
fifo_full=1'b0;
@(negedge clk);
parity_done=0;
low_pkt_valid=1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

task t3;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b10;
fifo_empty_2=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=1;
@(negedge clk);
fifo_full=0;
@(negedge clk);
parity_done=1;
end
endtask

task t4;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b01;
fifo_empty_1=1;
@(negedge clk)
fifo_full=1;
@(negedge clk);

fifo_full=0;
@(negedge clk);
parity_done=0;
low_pkt_valid=0;
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

initial
begin
initialize;
reset;
#10 t1;
#20;
 t2;
#20;
 t3;
#20;
 t4;
$finish;
end 
endmodule
module router_fsm_tb();


reg clk,resetn,pkt_valid,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid;
reg [1:0] data_in;
wire  write_enb_reg,detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,busy;

router_fsm dut(clk,resetn,pkt_valid,data_in,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid,write_enb_reg,detect_add,ld_state,
                   laf_state,lfd_state,full_state,rst_int_reg,busy);
parameter t=10;

always
begin
#t clk= ~clk;
end

task initialize;
begin
resetn=1'b1;
{clk,pkt_valid,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,
                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_pkt_valid}=0;
end
endtask

task reset;
begin
@(negedge clk);
   resetn= 1'b0;
@(negedge clk);
   resetn=1'b1;
end
endtask

task t1;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b01;
fifo_empty_1=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

task t2;
begin
@(negedge clk)
pkt_valid=1;
data_in=2'b00;
fifo_empty_0=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=1'b1;
@(negedge clk);
fifo_full=1'b0;
@(negedge clk);
parity_done=0;
low_pkt_valid=1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

task t3;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b10;
fifo_empty_2=1'b1;
@(negedge clk);
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=1;
@(negedge clk);
fifo_full=0;
@(negedge clk);
parity_done=1;
end
endtask

task t4;
begin
@(negedge clk);
pkt_valid=1;
data_in=2'b01;
fifo_empty_1=1;
@(negedge clk)
fifo_full=1;
@(negedge clk);

fifo_full=0;
@(negedge clk);
parity_done=0;
low_pkt_valid=0;
@(negedge clk);
fifo_full=0;
pkt_valid=0;
@(negedge clk);
@(negedge clk);
fifo_full=0;
end
endtask

initial
begin
initialize;
reset;
#10 t1;
#20;
 t2;
#20;
 t3;
#20;
 t4;
$finish;
end 
endmodule