data/full_repos/permissive/408955603/Sesion8/biestableRS.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:50: Unsupported: Ignoring delay on this delayed statement.\n always #7 C = ~C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:54: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | | %b CLR: %b, CE: %b, C: %b, SnP: %b, Is: %b, Ip: %b, O: %b", O, nCLR, CE, C, SP, Is, Ip, O[0]);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:56: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("salida.dmp");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:57: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #5 nCLR = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #5 Is = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #5 Is = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #30 nCLR = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #5 nCLR = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #5 SP = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #5 nCLR = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #5 nCLR = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10 SP = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #5 CE = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableRS.v:84: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: Exiting due to 4 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RS1bit(output wire O, input wire SP, input wire Is, input wire Ip, input wire C, input wire nCLR);
	wire nI, IsSP, IpNsp, nsp1, I;

	not(nsp1, SP);

	and(IsSP, Is, SP);
	and(IpNsp, Ip, nsp1);

	nor(nI, IsSP, IpNsp);

	not(I, nI);

	RS rs1(O, , nI, I, C, nCLR);
endmodule
module RS1bit(output wire O, input wire SP, input wire Is, input wire Ip, input wire C, input wire nCLR);

	wire nI, IsSP, IpNsp, nsp1, I;

	not(nsp1, SP);

	and(IsSP, Is, SP);
	and(IpNsp, Ip, nsp1);

	nor(nI, IsSP, IpNsp);

	not(I, nI);

	RS rs1(O, , nI, I, C, nCLR);
endmodule