data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ControlUnit(inst_CU, wreg, m2reg, wmem, aluc, aluimm, regrt);
    input [31:0] inst_CU;
    wire [5:0] op, func;
    output reg wreg, m2reg, wmem, aluimm, regrt;
    output reg [3:0] aluc;
    assign op = inst_CU[31:26];
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end

    always @ (op) begin
        if(op == 6'b100011) begin
            wreg <= 1'b1;
            m2reg <= 1'b1;
            wmem <= 1'b0;
            aluimm <= 1'b1;
            regrt <= 1'b1;
            aluc <= 4'b0010;
        end
    end
endmodule
module ControlUnit(inst_CU, wreg, m2reg, wmem, aluc, aluimm, regrt);

    input [31:0] inst_CU;
    wire [5:0] op, func;
    output reg wreg, m2reg, wmem, aluimm, regrt;
    output reg [3:0] aluc;
    assign op = inst_CU[31:26];
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end

    always @ (op) begin
        if(op == 6'b100011) begin
            wreg <= 1'b1;
            m2reg <= 1'b1;
            wmem <= 1'b0;
            aluimm <= 1'b1;
            regrt <= 1'b1;
            aluc <= 4'b0010;
        end
    end
endmodule