data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_dds.v
1: b"%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_dds.v:90: Cannot find file containing module: 'ad_dds_1'\n  ad_dds_1 i_dds_1_0 (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_dds_1\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_dds_1.v\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_dds_1.sv\n             ad_dds_1\n             ad_dds_1.v\n             ad_dds_1.sv\n             obj_dir/ad_dds_1\n             obj_dir/ad_dds_1.v\n             obj_dir/ad_dds_1.sv\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_dds.v:98: Cannot find file containing module: 'ad_dds_1'\n  ad_dds_1 i_dds_1_1 (\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ad_dds (



  clk,
  dds_format,
  dds_phase_0,
  dds_scale_0,
  dds_phase_1,
  dds_scale_1,
  dds_data);



  input           clk;
  input           dds_format;
  input   [15:0]  dds_phase_0;
  input   [15:0]  dds_scale_0;
  input   [15:0]  dds_phase_1;
  input   [15:0]  dds_scale_1;
  output  [15:0]  dds_data;



  reg     [15:0]  dds_data_int = 'd0;
  reg     [15:0]  dds_data = 'd0;

  reg     [15:0]  dds_scale_0_r = 'd0;
  reg     [15:0]  dds_scale_1_r = 'd0;


  wire    [15:0]  dds_data_0_s;
  wire    [15:0]  dds_data_1_s;



  always @(posedge clk) begin
    dds_data_int <= dds_data_0_s + dds_data_1_s;
    dds_data[15:15] <= dds_data_int[15] ^ dds_format;
    dds_data[14: 0] <= dds_data_int[14:0];
  end

  always @(posedge clk) begin
    dds_scale_0_r <= dds_scale_0;
    dds_scale_1_r <= dds_scale_1;
  end


  ad_dds_1 i_dds_1_0 (
    .clk (clk),
    .angle (dds_phase_0),
    .scale (dds_scale_0_r),
    .dds_data (dds_data_0_s));



  ad_dds_1 i_dds_1_1 (
    .clk (clk),
    .angle (dds_phase_1),
    .scale (dds_scale_1_r),
    .dds_data (dds_data_1_s));

endmodule
module ad_dds (



  clk,
  dds_format,
  dds_phase_0,
  dds_scale_0,
  dds_phase_1,
  dds_scale_1,
  dds_data);




  input           clk;
  input           dds_format;
  input   [15:0]  dds_phase_0;
  input   [15:0]  dds_scale_0;
  input   [15:0]  dds_phase_1;
  input   [15:0]  dds_scale_1;
  output  [15:0]  dds_data;



  reg     [15:0]  dds_data_int = 'd0;
  reg     [15:0]  dds_data = 'd0;

  reg     [15:0]  dds_scale_0_r = 'd0;
  reg     [15:0]  dds_scale_1_r = 'd0;


  wire    [15:0]  dds_data_0_s;
  wire    [15:0]  dds_data_1_s;



  always @(posedge clk) begin
    dds_data_int <= dds_data_0_s + dds_data_1_s;
    dds_data[15:15] <= dds_data_int[15] ^ dds_format;
    dds_data[14: 0] <= dds_data_int[14:0];
  end

  always @(posedge clk) begin
    dds_scale_0_r <= dds_scale_0;
    dds_scale_1_r <= dds_scale_1;
  end


  ad_dds_1 i_dds_1_0 (
    .clk (clk),
    .angle (dds_phase_0),
    .scale (dds_scale_0_r),
    .dds_data (dds_data_0_s));



  ad_dds_1 i_dds_1_1 (
    .clk (clk),
    .angle (dds_phase_1),
    .scale (dds_scale_1_r),
    .dds_data (dds_data_1_s));

endmodule