data/full_repos/permissive/447976230/fpga/usrp1/megacells/add32_bb.v
data/verilator_xmls/ef6f19a5-b24c-41f7-a53d-a706a9618ac4.xml
module add32 (
	dataa,
	datab,
	result);

	input	[7:0]  dataa;
	input	[7:0]  datab;
	output	[7:0]  result;

endmodule
module add32 (
	dataa,
	datab,
	result);


	input	[7:0]  dataa;
	input	[7:0]  datab;
	output	[7:0]  result;

endmodule