data/full_repos/permissive/43858668/final_verilog/src/clib/c_samq_ctrl.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_samq_ctrl.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_samq_ctrl.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_samq_ctrl.v:60: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_samq_ctrl.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 4 error(s)\n'
module c_samq_ctrl
  (clk, reset, push_active, push_valid, push_sel_qu, push_addr_qu, pop_active, 
   pop_valid, pop_sel_qu, pop_addr_qu, pop_next_addr_qu, almost_empty_qu, 
   empty_qu, full_qu, errors_qu);
   
`include "c_functions.v"
`include "c_constants.v"
   
   



   

   parameter num_queues = 4;
   

   parameter num_slots_per_queue = 8;
   

   parameter fast_almost_empty = 0;
   

   parameter enable_bypass = 0;
   

   parameter fast_pop_next_addr = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam num_slots = num_queues * num_slots_per_queue;
   

   localparam addr_width = clogb(num_slots);
   

   localparam queue_addr_width = clogb(num_slots_per_queue);
   

   localparam addr_pad_width = addr_width - queue_addr_width;
   
   



   
   input clk;
   input reset;


   input push_active;


   input push_valid;
   

   input [0:num_queues-1] push_sel_qu;
   

   output [0:num_queues*addr_width-1] push_addr_qu;
   wire [0:num_queues*addr_width-1]   push_addr_qu;
   

   input 			      pop_active;
   

   input 			      pop_valid;
   

   input [0:num_queues-1] 	      pop_sel_qu;
   

   output [0:num_queues*addr_width-1] pop_addr_qu;
   wire [0:num_queues*addr_width-1]   pop_addr_qu;
   

   output [0:num_queues*addr_width-1] pop_next_addr_qu;
   wire [0:num_queues*addr_width-1]   pop_next_addr_qu;
   

   output [0:num_queues-1] 	      almost_empty_qu;
   wire [0:num_queues-1] 	      almost_empty_qu;
   output [0:num_queues-1] 	      empty_qu;
   wire [0:num_queues-1] 	      empty_qu;
   output [0:num_queues-1] 	      full_qu;
   wire [0:num_queues-1] 	      full_qu;
   

   output [0:num_queues*2-1] 	      errors_qu;
   wire [0:num_queues*2-1] 	      errors_qu;
   
   
   genvar 			      queue;
   
   generate
      
      for(queue = 0; queue < num_queues; queue = queue + 1)
	begin:queues

	   wire push_sel;
	   assign push_sel = push_sel_qu[queue];
	   
	   wire push;
	   assign push = push_valid & push_sel;
	   
	   wire pop_sel;
	   assign pop_sel = pop_sel_qu[queue];
	   
	   wire pop;
	   assign pop = pop_valid & pop_sel;
	   
	   wire [0:addr_width-1] push_addr;
	   wire [0:addr_width-1] pop_addr;
	   wire 		 almost_empty;
	   wire 		 empty;
	   wire 		 full;
	   wire [0:1] 		 errors;
	   c_fifo_ctrl
	     #(.depth(num_slots_per_queue),
	       .extra_addr_width(addr_pad_width),
	       .offset(queue * num_slots_per_queue),
	       .fast_almost_empty(fast_almost_empty),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   fc
	     (.clk(clk),
	      .reset(reset),
	      .push_active(push_active),
	      .pop_active(pop_active),
	      .push(push),
	      .pop(pop),
	      .push_addr(push_addr),
	      .pop_addr(pop_addr),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .full(full),
	      .errors(errors));
	   
	   wire [0:addr_width-1] pop_next_addr;
	   
	   if(num_slots_per_queue == 1)
	     assign pop_next_addr = pop_addr;
	   else if(num_slots_per_queue > 1)
	     begin
		
		if(fast_pop_next_addr)
		  begin
		     
		     wire [0:addr_width-1] pop_next_addr_inc;
		     c_incr
		       #(.width(addr_width),
			 .min_value(queue * num_slots_per_queue),
			 .max_value((queue + 1) * num_slots_per_queue - 1))
		     pop_next_addr_inc_incr
		       (.data_in(pop_next_addr),
			.data_out(pop_next_addr_inc));
		     
		     wire [0:addr_width-1] pop_next_addr_s, pop_next_addr_q;
		     assign pop_next_addr_s
		       = pop ? pop_next_addr_inc : pop_next_addr_q;
		     c_dff
		       #(.width(addr_width),
			 .reset_value(queue * num_slots_per_queue + 1),
			 .reset_type(reset_type))
		     pop_next_addrq
		       (.clk(clk),
			.reset(reset),
			.active(pop_active),
			.d(pop_next_addr_s),
			.q(pop_next_addr_q));
		     
		     assign pop_next_addr = pop_next_addr_q;
		     
		  end
		else
		  begin
		     
		     c_incr
		       #(.width(addr_width),
			 .min_value(queue * num_slots_per_queue),
			 .max_value((queue + 1) * num_slots_per_queue - 1))
		     pop_next_addr_incr
		       (.data_in(pop_addr),
			.data_out(pop_next_addr));
		     
		  end
		
	     end
	   
	   assign push_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = push_addr;
	   assign pop_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = pop_addr;
	   assign pop_next_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = pop_next_addr;
	   assign full_qu[queue] = full;
	   assign almost_empty_qu[queue] = almost_empty;
	   assign empty_qu[queue] = empty;
	   assign errors_qu[queue*2:queue*2+1] = errors;
	   
	end
      
   endgenerate
   
endmodule
module c_samq_ctrl
  (clk, reset, push_active, push_valid, push_sel_qu, push_addr_qu, pop_active, 
   pop_valid, pop_sel_qu, pop_addr_qu, pop_next_addr_qu, almost_empty_qu, 
   empty_qu, full_qu, errors_qu);

   
`include "c_functions.v"
`include "c_constants.v"
   
   



   

   parameter num_queues = 4;
   

   parameter num_slots_per_queue = 8;
   

   parameter fast_almost_empty = 0;
   

   parameter enable_bypass = 0;
   

   parameter fast_pop_next_addr = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam num_slots = num_queues * num_slots_per_queue;
   

   localparam addr_width = clogb(num_slots);
   

   localparam queue_addr_width = clogb(num_slots_per_queue);
   

   localparam addr_pad_width = addr_width - queue_addr_width;
   
   



   
   input clk;
   input reset;


   input push_active;


   input push_valid;
   

   input [0:num_queues-1] push_sel_qu;
   

   output [0:num_queues*addr_width-1] push_addr_qu;
   wire [0:num_queues*addr_width-1]   push_addr_qu;
   

   input 			      pop_active;
   

   input 			      pop_valid;
   

   input [0:num_queues-1] 	      pop_sel_qu;
   

   output [0:num_queues*addr_width-1] pop_addr_qu;
   wire [0:num_queues*addr_width-1]   pop_addr_qu;
   

   output [0:num_queues*addr_width-1] pop_next_addr_qu;
   wire [0:num_queues*addr_width-1]   pop_next_addr_qu;
   

   output [0:num_queues-1] 	      almost_empty_qu;
   wire [0:num_queues-1] 	      almost_empty_qu;
   output [0:num_queues-1] 	      empty_qu;
   wire [0:num_queues-1] 	      empty_qu;
   output [0:num_queues-1] 	      full_qu;
   wire [0:num_queues-1] 	      full_qu;
   

   output [0:num_queues*2-1] 	      errors_qu;
   wire [0:num_queues*2-1] 	      errors_qu;
   
   
   genvar 			      queue;
   
   generate
      
      for(queue = 0; queue < num_queues; queue = queue + 1)
	begin:queues

	   wire push_sel;
	   assign push_sel = push_sel_qu[queue];
	   
	   wire push;
	   assign push = push_valid & push_sel;
	   
	   wire pop_sel;
	   assign pop_sel = pop_sel_qu[queue];
	   
	   wire pop;
	   assign pop = pop_valid & pop_sel;
	   
	   wire [0:addr_width-1] push_addr;
	   wire [0:addr_width-1] pop_addr;
	   wire 		 almost_empty;
	   wire 		 empty;
	   wire 		 full;
	   wire [0:1] 		 errors;
	   c_fifo_ctrl
	     #(.depth(num_slots_per_queue),
	       .extra_addr_width(addr_pad_width),
	       .offset(queue * num_slots_per_queue),
	       .fast_almost_empty(fast_almost_empty),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   fc
	     (.clk(clk),
	      .reset(reset),
	      .push_active(push_active),
	      .pop_active(pop_active),
	      .push(push),
	      .pop(pop),
	      .push_addr(push_addr),
	      .pop_addr(pop_addr),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .full(full),
	      .errors(errors));
	   
	   wire [0:addr_width-1] pop_next_addr;
	   
	   if(num_slots_per_queue == 1)
	     assign pop_next_addr = pop_addr;
	   else if(num_slots_per_queue > 1)
	     begin
		
		if(fast_pop_next_addr)
		  begin
		     
		     wire [0:addr_width-1] pop_next_addr_inc;
		     c_incr
		       #(.width(addr_width),
			 .min_value(queue * num_slots_per_queue),
			 .max_value((queue + 1) * num_slots_per_queue - 1))
		     pop_next_addr_inc_incr
		       (.data_in(pop_next_addr),
			.data_out(pop_next_addr_inc));
		     
		     wire [0:addr_width-1] pop_next_addr_s, pop_next_addr_q;
		     assign pop_next_addr_s
		       = pop ? pop_next_addr_inc : pop_next_addr_q;
		     c_dff
		       #(.width(addr_width),
			 .reset_value(queue * num_slots_per_queue + 1),
			 .reset_type(reset_type))
		     pop_next_addrq
		       (.clk(clk),
			.reset(reset),
			.active(pop_active),
			.d(pop_next_addr_s),
			.q(pop_next_addr_q));
		     
		     assign pop_next_addr = pop_next_addr_q;
		     
		  end
		else
		  begin
		     
		     c_incr
		       #(.width(addr_width),
			 .min_value(queue * num_slots_per_queue),
			 .max_value((queue + 1) * num_slots_per_queue - 1))
		     pop_next_addr_incr
		       (.data_in(pop_addr),
			.data_out(pop_next_addr));
		     
		  end
		
	     end
	   
	   assign push_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = push_addr;
	   assign pop_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = pop_addr;
	   assign pop_next_addr_qu[queue*addr_width:(queue+1)*addr_width-1]
	     = pop_next_addr;
	   assign full_qu[queue] = full;
	   assign almost_empty_qu[queue] = almost_empty;
	   assign empty_qu[queue] = empty;
	   assign errors_qu[queue*2:queue*2+1] = errors;
	   
	end
      
   endgenerate
   
endmodule