data/full_repos/permissive/440081696/test_uart.v
1: b'%Error: data/full_repos/permissive/440081696/test_uart.v:24: Cannot find file containing module: \'uart\'\n  uart uart_inst(\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/uart\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/uart.v\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Warning-WIDTH: data/full_repos/permissive/440081696/test_uart.v:55: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'8\'hd\' generates 8 bits.\n                                                                   : ... In instance test_uart\n      if(dout_32b_valid_o == 1\'b1 && dout_32b_o == 8\'h0d)  \n                                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/440081696/test_uart.v:109: Cannot find file containing module: \'fifo_8b_512\'\n  fifo_8b_512 data(\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module test_uart(
  input           sys_clk,
  input           rst_n,
  input           uart_rx,
  output  wire    uart_tx
);

  (* mark_debug = "true"*)reg   [31:0]  addr_32b_i;
  (* mark_debug = "true"*)reg           wren_i,rden_i;
  (* mark_debug = "true"*)reg   [31:0]  din_32b_i;
  (* mark_debug = "true"*)wire  [31:0]  dout_32b_o;
  (* mark_debug = "true"*)wire          dout_32b_valid_o;
  (* mark_debug = "true"*)wire          interrupt_o;

  uart uart_inst(
    .clk_50m_i(sys_clk),
    .rst_n_i(rst_n),
    .uart_tx_o(uart_tx),
    .uart_rx_i(uart_rx),
    .addr_32b_i(addr_32b_i),
    .wren_i(wren_i),
    .rden_i(rden_i),
    .din_32b_i(din_32b_i),
    .dout_32b_o(dout_32b_o),
    .dout_32b_valid_o(dout_32b_valid_o),
    .interrupt_o(interrupt_o)
  );


  reg         rden_data;
  wire  [7:0] dout_data;
  wire        empty_data;




  (* mark_debug = "true"*)reg   [7:0] num_string; 
  (* mark_debug = "true"*)reg         add_1_str, sub_1_str;
  always @(posedge sys_clk or negedge rst_n) begin
    if(!rst_n) begin
      num_string    <= 8'b0;
      add_1_str     <= 1'b0;
      sub_1_str     <= 1'b0;
    end
    else begin
      if(dout_32b_valid_o == 1'b1 && dout_32b_o == 8'h0d)
        add_1_str   <= 1'b1;
      else
        add_1_str   <= 1'b0;
      if(wren_i == 1'b1 && din_32b_i[7:0] == 8'h0d)
        sub_1_str   <= 1'b1;
      else
        sub_1_str   <= 1'b0;
      (*full_case, parallel_case*)
      case({add_1_str,sub_1_str})
        2'd0,2'd3:  num_string  <= num_string;
        2'd1:       num_string  <= num_string - 8'd1;
        2'd2:       num_string  <= num_string + 8'd1;
      endcase
    end
  end


  reg [3:0]   cnt_wait_clk;
  always @(posedge sys_clk or negedge rst_n) begin
    if(!rst_n) begin
      wren_i        <= 1'b0;
      rden_i        <= 1'b0;
      din_32b_i     <= 32'b0;
      addr_32b_i    <= 32'b0;
      cnt_wait_clk  <= 4'b0;
      rden_data     <= 1'b0;
    end
    else begin
      rden_data     <= 1'b0;
      rden_i        <= 1'b0;
      wren_i        <= 1'b0;
      cnt_wait_clk  <= 4'b1 + cnt_wait_clk;
      if(interrupt_o == 1'b1 && cnt_wait_clk == 4'b0) begin
        rden_i      <= 1'b1;
        addr_32b_i  <= 32'h10010000;
      end
      else if(num_string != 8'd0 && cnt_wait_clk == 4'b0) begin
        rden_data   <= 1'b1;
        wren_i      <= 1'b1;
        addr_32b_i  <= 32'h10010004;
        if(dout_data == 8'h41)
          din_32b_i <= {24'b0,8'h42};
        else
          din_32b_i <= {24'b0,dout_data};
      end
      else if(num_string == 8'd0 && cnt_wait_clk == 4'b0 && din_32b_i[7:0] == 8'h0d) begin
        wren_i      <= 1'b1;
        addr_32b_i  <= 32'h10010004;
        din_32b_i   <= {24'b0,8'h0a};
      end
    end
  end

  fifo_8b_512 data(
    .clk(sys_clk),
    .srst(!rst_n),
    .din(dout_32b_o[7:0]),
    .wr_en(dout_32b_valid_o),
    .rd_en(rden_data),
    .dout(dout_data),
    .full(),
    .empty(empty_data),
    .data_count()
  );




endmodule
module test_uart(
  input           sys_clk,
  input           rst_n,
  input           uart_rx,
  output  wire    uart_tx
);


  (* mark_debug = "true"*)reg   [31:0]  addr_32b_i;
  (* mark_debug = "true"*)reg           wren_i,rden_i;
  (* mark_debug = "true"*)reg   [31:0]  din_32b_i;
  (* mark_debug = "true"*)wire  [31:0]  dout_32b_o;
  (* mark_debug = "true"*)wire          dout_32b_valid_o;
  (* mark_debug = "true"*)wire          interrupt_o;

  uart uart_inst(
    .clk_50m_i(sys_clk),
    .rst_n_i(rst_n),
    .uart_tx_o(uart_tx),
    .uart_rx_i(uart_rx),
    .addr_32b_i(addr_32b_i),
    .wren_i(wren_i),
    .rden_i(rden_i),
    .din_32b_i(din_32b_i),
    .dout_32b_o(dout_32b_o),
    .dout_32b_valid_o(dout_32b_valid_o),
    .interrupt_o(interrupt_o)
  );


  reg         rden_data;
  wire  [7:0] dout_data;
  wire        empty_data;




  (* mark_debug = "true"*)reg   [7:0] num_string; 
  (* mark_debug = "true"*)reg         add_1_str, sub_1_str;
  always @(posedge sys_clk or negedge rst_n) begin
    if(!rst_n) begin
      num_string    <= 8'b0;
      add_1_str     <= 1'b0;
      sub_1_str     <= 1'b0;
    end
    else begin
      if(dout_32b_valid_o == 1'b1 && dout_32b_o == 8'h0d)
        add_1_str   <= 1'b1;
      else
        add_1_str   <= 1'b0;
      if(wren_i == 1'b1 && din_32b_i[7:0] == 8'h0d)
        sub_1_str   <= 1'b1;
      else
        sub_1_str   <= 1'b0;
      (*full_case, parallel_case*)
      case({add_1_str,sub_1_str})
        2'd0,2'd3:  num_string  <= num_string;
        2'd1:       num_string  <= num_string - 8'd1;
        2'd2:       num_string  <= num_string + 8'd1;
      endcase
    end
  end


  reg [3:0]   cnt_wait_clk;
  always @(posedge sys_clk or negedge rst_n) begin
    if(!rst_n) begin
      wren_i        <= 1'b0;
      rden_i        <= 1'b0;
      din_32b_i     <= 32'b0;
      addr_32b_i    <= 32'b0;
      cnt_wait_clk  <= 4'b0;
      rden_data     <= 1'b0;
    end
    else begin
      rden_data     <= 1'b0;
      rden_i        <= 1'b0;
      wren_i        <= 1'b0;
      cnt_wait_clk  <= 4'b1 + cnt_wait_clk;
      if(interrupt_o == 1'b1 && cnt_wait_clk == 4'b0) begin
        rden_i      <= 1'b1;
        addr_32b_i  <= 32'h10010000;
      end
      else if(num_string != 8'd0 && cnt_wait_clk == 4'b0) begin
        rden_data   <= 1'b1;
        wren_i      <= 1'b1;
        addr_32b_i  <= 32'h10010004;
        if(dout_data == 8'h41)
          din_32b_i <= {24'b0,8'h42};
        else
          din_32b_i <= {24'b0,dout_data};
      end
      else if(num_string == 8'd0 && cnt_wait_clk == 4'b0 && din_32b_i[7:0] == 8'h0d) begin
        wren_i      <= 1'b1;
        addr_32b_i  <= 32'h10010004;
        din_32b_i   <= {24'b0,8'h0a};
      end
    end
  end

  fifo_8b_512 data(
    .clk(sys_clk),
    .srst(!rst_n),
    .din(dout_32b_o[7:0]),
    .wr_en(dout_32b_valid_o),
    .rd_en(rden_data),
    .dout(dout_data),
    .full(),
    .empty(empty_data),
    .data_count()
  );




endmodule