data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:23: Unsupported: Ignoring delay on this delayed statement.\nalways  #5  clk = ~clk;    \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:24: Unsupported: Ignoring delay on this delayed statement.\ninitial #40 rst_n = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:50: Can\'t find definition of \'rd_gnt\' in dotted variable: \'bus_slaves__BRA__??__KET__.rd_gnt\'\nassign bus_slaves[0].rd_gnt = 1\'b1;\n                     ^~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:51: Can\'t find definition of \'wr_gnt\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_gnt\'\nassign bus_slaves[0].wr_gnt = 1\'b1;\n                     ^~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:55: Can\'t find definition of \'rd_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.rd_data\'\n        bus_slaves[0].rd_data <= 0;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:57: Can\'t find definition of \'rd_addr\' in dotted variable: \'bus_slaves__BRA__??__KET__.rd_addr\'\n        bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];\n                                                   ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:57: Can\'t find definition of \'rd_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.rd_data\'\n        bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];\n                      ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:62: Can\'t find definition of \'wr_be\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_be\'\n        if(bus_slaves[0].wr_be[0])\n                         ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:63: Can\'t find definition of \'wr_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_data\'\n            ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:63: Can\'t find definition of \'wr_addr\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_addr\'\n            ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];\n                              ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:64: Can\'t find definition of \'wr_be\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_be\'\n        if(bus_slaves[0].wr_be[1])\n                         ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:65: Can\'t find definition of \'wr_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_data\'\n            ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:65: Can\'t find definition of \'wr_addr\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_addr\'\n            ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];\n                              ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:66: Can\'t find definition of \'wr_be\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_be\'\n        if(bus_slaves[0].wr_be[2])\n                         ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:67: Can\'t find definition of \'wr_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_data\'\n            ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:67: Can\'t find definition of \'wr_addr\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_addr\'\n            ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];\n                              ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:68: Can\'t find definition of \'wr_be\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_be\'\n        if(bus_slaves[0].wr_be[3])\n                         ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:69: Can\'t find definition of \'wr_data\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_data\'\n            ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.srcs/sim_1/new/tb_core.sv:69: Can\'t find definition of \'wr_addr\' in dotted variable: \'bus_slaves__BRA__??__KET__.wr_addr\'\n            ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];\n                              ^~~~~~~\n%Error: Exiting due to 17 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_core #(


    

    parameter INSTRUCTION_STREAM_FILE = "E:\\FPGAcommon\\USTCRVSoC\\hardware\\Simulation_RiscvCPU\\RISCV_RV32I_Test\\testA_InstructionStream.txt"


)();

logic [31:0] ram [4096];

initial $readmemh(INSTRUCTION_STREAM_FILE, ram);

logic clk = 1'b1, rst_n = 1'b0;
always  #5  clk = ~clk;
initial #40 rst_n = 1'b1;

naive_bus  bus_masters[2]();
naive_bus  bus_slaves [1]();


core_top core_top_inst(
    .clk          ( clk               ),
    .rst_n        ( rst_n             ),
    .i_boot_addr  ( 0                 ),
    .instr_master ( bus_masters[1]    ),
    .data_master  ( bus_masters[0]    )
);

naive_bus_router #(
    .N_MASTER     ( 2                 ),
    .N_SLAVE      ( 1                 ),
    .SLAVES_MASK  ( { 32'h0000_ffff } ),
    .SLAVES_BASE  ( { 32'h0000_0000 } )
) soc_bus_router_inst (
    .clk          ( clk               ),
    .rst_n        ( rst_n             ),
    .masters      ( bus_masters       ),
    .slaves       ( bus_slaves        )
);

assign bus_slaves[0].rd_gnt = 1'b1;
assign bus_slaves[0].wr_gnt = 1'b1;

always @ (posedge clk or negedge rst_n)
    if(~rst_n)
        bus_slaves[0].rd_data <= 0;
    else
        bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];
    
always @ (posedge clk or negedge rst_n)
    if(~rst_n) begin
    end else begin
        if(bus_slaves[0].wr_be[0])
            ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];
        if(bus_slaves[0].wr_be[1])
            ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];
        if(bus_slaves[0].wr_be[2])
            ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];
        if(bus_slaves[0].wr_be[3])
            ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];
    end

endmodule
module tb_core #(


    

    parameter INSTRUCTION_STREAM_FILE = "E:\\FPGAcommon\\USTCRVSoC\\hardware\\Simulation_RiscvCPU\\RISCV_RV32I_Test\\testA_InstructionStream.txt"


)();


logic [31:0] ram [4096];

initial $readmemh(INSTRUCTION_STREAM_FILE, ram);

logic clk = 1'b1, rst_n = 1'b0;
always  #5  clk = ~clk;
initial #40 rst_n = 1'b1;

naive_bus  bus_masters[2]();
naive_bus  bus_slaves [1]();


core_top core_top_inst(
    .clk          ( clk               ),
    .rst_n        ( rst_n             ),
    .i_boot_addr  ( 0                 ),
    .instr_master ( bus_masters[1]    ),
    .data_master  ( bus_masters[0]    )
);

naive_bus_router #(
    .N_MASTER     ( 2                 ),
    .N_SLAVE      ( 1                 ),
    .SLAVES_MASK  ( { 32'h0000_ffff } ),
    .SLAVES_BASE  ( { 32'h0000_0000 } )
) soc_bus_router_inst (
    .clk          ( clk               ),
    .rst_n        ( rst_n             ),
    .masters      ( bus_masters       ),
    .slaves       ( bus_slaves        )
);

assign bus_slaves[0].rd_gnt = 1'b1;
assign bus_slaves[0].wr_gnt = 1'b1;

always @ (posedge clk or negedge rst_n)
    if(~rst_n)
        bus_slaves[0].rd_data <= 0;
    else
        bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];
    
always @ (posedge clk or negedge rst_n)
    if(~rst_n) begin
    end else begin
        if(bus_slaves[0].wr_be[0])
            ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];
        if(bus_slaves[0].wr_be[1])
            ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];
        if(bus_slaves[0].wr_be[2])
            ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];
        if(bus_slaves[0].wr_be[3])
            ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];
    end

endmodule