data/full_repos/permissive/51595169/VerilogSource/CPU/Register2Buff.v
1: b"%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/Register2Buff.v:4: Cannot find file containing module: 'Register2'\nRegister2 register( IN,IN2, Clk, Reset,Load,Load2, _OUT);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51595169/VerilogSource/CPU,data/full_repos/permissive/51595169/Register2\n             data/full_repos/permissive/51595169/VerilogSource/CPU,data/full_repos/permissive/51595169/Register2.v\n             data/full_repos/permissive/51595169/VerilogSource/CPU,data/full_repos/permissive/51595169/Register2.sv\n             Register2\n             Register2.v\n             Register2.sv\n             obj_dir/Register2\n             obj_dir/Register2.v\n             obj_dir/Register2.sv\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/Register2Buff.v:6: Cannot find file containing module: 'Buffer32_32'\nBuffer32_32 buff1( _OUT, Store, IN);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/Register2Buff.v:8: Cannot find file containing module: 'Buffer32_32'\nBuffer32_32 buff2( _OUT, Store2,IN2);\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Register2Buff(inout [31:0] IN,IN2,input Clk, Reset,Load,Load2,Store,Store2);
wire [31:0] _OUT;

Register2 register( IN,IN2, Clk, Reset,Load,Load2, _OUT);

Buffer32_32 buff1( _OUT, Store, IN);

Buffer32_32 buff2( _OUT, Store2,IN2);
endmodule
module Register2Buff(inout [31:0] IN,IN2,input Clk, Reset,Load,Load2,Store,Store2);

wire [31:0] _OUT;

Register2 register( IN,IN2, Clk, Reset,Load,Load2, _OUT);

Buffer32_32 buff1( _OUT, Store, IN);

Buffer32_32 buff2( _OUT, Store2,IN2);
endmodule