data/full_repos/permissive/424312442/Lab_7_automated test benches/sources_1/new/test_vectors.v
1: b'%Error: Cannot find file containing module: benches/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/Lab_7_automated/benches/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/Lab_7_automated/benches/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/Lab_7_automated/benches/sources_1/new,data/full_repos/permissive/424312442.sv\n             benches/sources_1/new,data/full_repos/permissive/424312442\n             benches/sources_1/new,data/full_repos/permissive/424312442.v\n             benches/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/benches/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/benches/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/benches/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/Lab_7_automated\n%Error: Cannot find file containing module: benches/sources_1/new/test_vectors.v\n%Error: Exiting due to 3 error(s)\n'
module adder4bit_tb;

    reg [3:0] x;
    reg [3:0] y;
    reg ci;
    wire [3:0] s;
    wire co;
    adder4bit dut(x, y, ci, s, co);
    

    reg clk;
    integer vectornum, errors;
    reg [13:0] testvectors [999:0];
    reg expected_co;
    reg [3:0] expected_s;


    always begin
        clk = 0; #10; clk = 1; #10;
    end


    initial begin

        $readmemb("C:/Users/keajacm/Documents/Digital/Lab_7/Lab_7.srcs/sim_1/imports/Digital/testvectors.txt", testvectors);
        vectornum = 0;
        errors = 0;
    end
    

    always @(negedge clk) begin
        {x, y, ci, expected_co, expected_s} = testvectors[vectornum];
    end


    always @(posedge clk) begin

        if ({co, s} !== {expected_co, expected_s}) begin
            $display("Error! %d + %d + %d -> %d, expecting %d",
                     x, y, ci, {co, s}, {expected_co, expected_s});






            errors = errors + 1;
        end
        

        vectornum = vectornum + 1;
        




        if (testvectors[vectornum] === 14'bx) begin
            $display("Done! %d tests completed with %d errors.",
                     vectornum, errors);
            $finish;
        end
    end
endmodule
module adder4bit_tb;


    reg [3:0] x;
    reg [3:0] y;
    reg ci;
    wire [3:0] s;
    wire co;
    adder4bit dut(x, y, ci, s, co);
    

    reg clk;
    integer vectornum, errors;
    reg [13:0] testvectors [999:0];
    reg expected_co;
    reg [3:0] expected_s;


    always begin
        clk = 0; #10; clk = 1; #10;
    end


    initial begin

        $readmemb("C:/Users/keajacm/Documents/Digital/Lab_7/Lab_7.srcs/sim_1/imports/Digital/testvectors.txt", testvectors);
        vectornum = 0;
        errors = 0;
    end
    

    always @(negedge clk) begin
        {x, y, ci, expected_co, expected_s} = testvectors[vectornum];
    end


    always @(posedge clk) begin

        if ({co, s} !== {expected_co, expected_s}) begin
            $display("Error! %d + %d + %d -> %d, expecting %d",
                     x, y, ci, {co, s}, {expected_co, expected_s});






            errors = errors + 1;
        end
        

        vectornum = vectornum + 1;
        




        if (testvectors[vectornum] === 14'bx) begin
            $display("Done! %d tests completed with %d errors.",
                     vectornum, errors);
            $finish;
        end
    end
endmodule