data/full_repos/permissive/445929378/mult_66.v
1: b'%Error: data/full_repos/permissive/445929378/mult_66.v:50: Cannot find file containing module: \'mult_34\'\n   mult_34 mult_a(\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_34\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_34.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_34.sv\n             mult_34\n             mult_34.v\n             mult_34.sv\n             obj_dir/mult_34\n             obj_dir/mult_34.v\n             obj_dir/mult_34.sv\n%Error: data/full_repos/permissive/445929378/mult_66.v:64: Cannot find file containing module: \'mult_34\'\n   mult_34 mult_d(\n   ^~~~~~~\n%Error: data/full_repos/permissive/445929378/mult_66.v:78: Cannot find file containing module: \'mult_36\'\n   mult_36 mult_e(\n   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:95: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                 : ... In instance mult_66_pipeline_2\n  rdy_flg <= 2\'b00;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:109: Operator SHIFTL expects 66 bits on the LHS, but LHS\'s VARREF \'a_reg\' generates 34 bits.\n                                                                  : ... In instance mult_66_pipeline_2\n        output_reg <= a_reg << (34);\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:110: Operator SUB expects 36 bits on the RHS, but RHS\'s VARREF \'d_reg\' generates 34 bits.\n                                                                  : ... In instance mult_66_pipeline_2\n        e_reg <= e_reg - d_reg - a_reg;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:110: Operator SUB expects 36 bits on the RHS, but RHS\'s VARREF \'a_reg\' generates 34 bits.\n                                                                  : ... In instance mult_66_pipeline_2\n        e_reg <= e_reg - d_reg - a_reg;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:114: Operator SHIFTL expects 66 bits on the LHS, but LHS\'s VARREF \'e_reg\' generates 36 bits.\n                                                                  : ... In instance mult_66_pipeline_2\n        bufer_reg <= e_reg << (17);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_66.v:118: Operator ADD expects 66 bits on the RHS, but RHS\'s VARREF \'d_reg\' generates 34 bits.\n                                                                  : ... In instance mult_66_pipeline_2\n        output_reg <= output_reg + bufer_reg + d_reg;     \n                                             ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module mult_66_pipeline_2(
			  input wire 	     clk, rst,
			  input wire [33:0]  input_a_tdata, input_b_tdata,
			  input wire 	     input_a_tvalid, input_b_tvalid,
			  output wire 	     input_a_tready, input_b_tready,
			  output wire [65:0] output_tdata,
			  output wire 	     output_tvalid,
			  input wire 	     output_tready
			  );

   wire 					    karatsuba_rdy;
   
   wire [16:0] 					    input_a_high;
   wire [16:0] 					    input_a_low;
   
   wire [16:0] 					    input_b_high;
   wire [16:0] 					    input_b_low;

   wire [17:0] 					    e_high_tdata, e_low_tdata;

   reg [65:0] 					    output_reg;
   reg [65:0] 					    bufer_reg = 0;

   reg [2:0] 					    rdy_flg = 0;
   
   wire 					    data_tready;
   wire 					    a_output_tvalid, d_output_tvalid, e_output_tvalid;
   
   wire [33:0] 					    a, d;
   wire [35:0] 					    e;
   reg [33:0] 					    a_reg, d_reg;
   reg [35:0] 					    e_reg = 0;
   
   assign {input_a_high, input_a_low} = input_a_tdata;
   assign {input_b_high, input_b_low} = input_b_tdata;

   assign e_high_tdata = input_a_high + input_a_low;
   assign e_low_tdata = input_b_high + input_b_low;
   
   assign input_a_tready = input_b_tvalid & output_tready;
   assign input_b_tready = input_a_tvalid & output_tready;
   
   assign data_tready = input_a_tready & input_b_tready & output_tready;
   assign karatsuba_rdy = a_output_tvalid & d_output_tvalid & e_output_tvalid;

   assign output_tvalid = rdy_flg[2];
   
   assign output_tdata = output_reg;
	
   mult_34 mult_a(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_high),
			     .input_b_tdata(input_b_high),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(a),
			     .output_tvalid(a_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_34 mult_d(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_low),
			     .input_b_tdata(input_b_low),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(d),
			     .output_tvalid(d_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_36 mult_e(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(e_high_tdata),
			     .input_b_tdata(e_low_tdata),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(e),
			     .output_tvalid(e_output_tvalid),
			     .output_tready(data_tready)
			     );


   always @(posedge clk) begin
      if(rst) begin
	 rdy_flg <= 2'b00;
	 output_reg <= 0;
	 a_reg <= a;
	 e_reg <= e;
	 d_reg <= d;	 
      end else begin 
	 if(karatsuba_rdy) begin
	    if(rdy_flg[1:0] == 2'b00) begin
	       a_reg <= a;
	       e_reg <= e;
	       d_reg <= d;
	       rdy_flg[1:0] <= 2'b01;
	    end	 
	    if(rdy_flg[1:0] == 2'b01) begin
	       output_reg <= a_reg << (34);
	       e_reg <= e_reg - d_reg - a_reg;
	       rdy_flg[1:0] <= 2'b10;
	    end
	    else if (rdy_flg[1:0] == 2'b10) begin
	       bufer_reg <= e_reg << (17);
	       rdy_flg[1:0] <= 2'b11;
	    end
	    else if (rdy_flg[1:0] == 2'b11) begin
	       output_reg <= output_reg + bufer_reg + d_reg;	    
	       rdy_flg <= 3'b100;
	    end
	 end
      end
   end
endmodule
module mult_66_pipeline_2(
			  input wire 	     clk, rst,
			  input wire [33:0]  input_a_tdata, input_b_tdata,
			  input wire 	     input_a_tvalid, input_b_tvalid,
			  output wire 	     input_a_tready, input_b_tready,
			  output wire [65:0] output_tdata,
			  output wire 	     output_tvalid,
			  input wire 	     output_tready
			  );


   wire 					    karatsuba_rdy;
   
   wire [16:0] 					    input_a_high;
   wire [16:0] 					    input_a_low;
   
   wire [16:0] 					    input_b_high;
   wire [16:0] 					    input_b_low;

   wire [17:0] 					    e_high_tdata, e_low_tdata;

   reg [65:0] 					    output_reg;
   reg [65:0] 					    bufer_reg = 0;

   reg [2:0] 					    rdy_flg = 0;
   
   wire 					    data_tready;
   wire 					    a_output_tvalid, d_output_tvalid, e_output_tvalid;
   
   wire [33:0] 					    a, d;
   wire [35:0] 					    e;
   reg [33:0] 					    a_reg, d_reg;
   reg [35:0] 					    e_reg = 0;
   
   assign {input_a_high, input_a_low} = input_a_tdata;
   assign {input_b_high, input_b_low} = input_b_tdata;

   assign e_high_tdata = input_a_high + input_a_low;
   assign e_low_tdata = input_b_high + input_b_low;
   
   assign input_a_tready = input_b_tvalid & output_tready;
   assign input_b_tready = input_a_tvalid & output_tready;
   
   assign data_tready = input_a_tready & input_b_tready & output_tready;
   assign karatsuba_rdy = a_output_tvalid & d_output_tvalid & e_output_tvalid;

   assign output_tvalid = rdy_flg[2];
   
   assign output_tdata = output_reg;
	
   mult_34 mult_a(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_high),
			     .input_b_tdata(input_b_high),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(a),
			     .output_tvalid(a_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_34 mult_d(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_low),
			     .input_b_tdata(input_b_low),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(d),
			     .output_tvalid(d_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_36 mult_e(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(e_high_tdata),
			     .input_b_tdata(e_low_tdata),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(e),
			     .output_tvalid(e_output_tvalid),
			     .output_tready(data_tready)
			     );


   always @(posedge clk) begin
      if(rst) begin
	 rdy_flg <= 2'b00;
	 output_reg <= 0;
	 a_reg <= a;
	 e_reg <= e;
	 d_reg <= d;	 
      end else begin 
	 if(karatsuba_rdy) begin
	    if(rdy_flg[1:0] == 2'b00) begin
	       a_reg <= a;
	       e_reg <= e;
	       d_reg <= d;
	       rdy_flg[1:0] <= 2'b01;
	    end	 
	    if(rdy_flg[1:0] == 2'b01) begin
	       output_reg <= a_reg << (34);
	       e_reg <= e_reg - d_reg - a_reg;
	       rdy_flg[1:0] <= 2'b10;
	    end
	    else if (rdy_flg[1:0] == 2'b10) begin
	       bufer_reg <= e_reg << (17);
	       rdy_flg[1:0] <= 2'b11;
	    end
	    else if (rdy_flg[1:0] == 2'b11) begin
	       output_reg <= output_reg + bufer_reg + d_reg;	    
	       rdy_flg <= 3'b100;
	    end
	 end
      end
   end
endmodule