data/full_repos/permissive/450223699/or_gate.v
data/verilator_xmls/7385a8f1-e943-4d8c-b05b-c7e6cfa71587.xml
module or_gate(
    input A,
    input B,
    output Out
    );
    assign Out = A | B;
endmodule
module or_gate(
    input A,
    input B,
    output Out
    );

    assign Out = A | B;
endmodule