data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:32: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:71: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]        pcx_iob_data_px2;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:76: Define or directive not defined: \'`PCX_RQ_HI\'\n   output [`PCX_RQ_HI-`PCX_RQ_LO:0]   pcx_iob_req;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:76: Define or directive not defined: \'`PCX_RQ_LO\'\n   output [`PCX_RQ_HI-`PCX_RQ_LO:0]   pcx_iob_req;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:76: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`PCX_RQ_HI-`PCX_RQ_LO:0]   pcx_iob_req;\n                                ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:77: Define or directive not defined: \'`PCX_AD_HI\'\n   output [`PCX_AD_HI-`PCX_AD_LO:0]   pcx_iob_addr;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:77: Define or directive not defined: \'`PCX_AD_LO\'\n   output [`PCX_AD_HI-`PCX_AD_LO:0]   pcx_iob_addr;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:77: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`PCX_AD_HI-`PCX_AD_LO:0]   pcx_iob_addr;\n                                ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:78: Define or directive not defined: \'`PCX_CP_HI\'\n   output [`PCX_CP_HI-`PCX_TH_LO:0]   pcx_iob_cputhr;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:78: Define or directive not defined: \'`PCX_TH_LO\'\n   output [`PCX_CP_HI-`PCX_TH_LO:0]   pcx_iob_cputhr;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:78: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`PCX_CP_HI-`PCX_TH_LO:0]   pcx_iob_cputhr;\n                                ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:90: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   input [`IOB_MONDO_DATA_INDEX-1:0]  mondo_data_addr_p0_d1;\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:94: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   wire [`IOB_INT_BUF_WIDTH-1:0]      int_buf_din;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:97: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   assign  int_buf_din_raw = {{(160-`IOB_INT_BUF_WIDTH){1\'b0}},int_buf_din};\n                                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:97: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  int_buf_din_raw = {{(160-`IOB_INT_BUF_WIDTH){1\'b0}},int_buf_din};\n                                                      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:101: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data0_din_s;\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:102: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data1_din_s;\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:103: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   input [`IOB_MONDO_SRC_WIDTH-1:0]   io_mondo_source_din_s;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:112: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:113: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_dout;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:114: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:115: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_dout;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:127: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   assign  mondo_data0_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data0_din};\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:127: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  mondo_data0_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data0_din};\n                                                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:128: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   assign  mondo_data0_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data0_din};\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:128: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  mondo_data0_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data0_din};\n                                                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:129: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   assign  mondo_data0_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?\n                                                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:130: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n                     mondo_data0_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :\n                                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:131: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n                     mondo_data0_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];\n                                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:133: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   assign  mondo_data1_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data1_din};\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:133: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  mondo_data1_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data1_din};\n                                                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:134: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   assign  mondo_data1_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data1_din};\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:134: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  mondo_data1_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1\'b0}},mondo_data1_din};\n                                                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:135: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   assign  mondo_data1_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?\n                                                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:136: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n                     mondo_data1_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :\n                                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:137: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n                     mondo_data1_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];\n                                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:139: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   output [`IOB_MONDO_SRC_WIDTH-1:0]  mondo_source_din;\n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:140: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   input [`IOB_MONDO_SRC_WIDTH-1:0]   mondo_source_dout;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:147: Define or directive not defined: \'`PCX_WIDTH\'\n   wire [`PCX_WIDTH-1:0]        cpu_buf_din;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:152: Define or directive not defined: \'`PCX_WIDTH\'\n   assign       cpu_buf_din_hi = {{(129-`PCX_WIDTH){1\'b0}},cpu_buf_din[`PCX_WIDTH-1:64]};\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:152: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign       cpu_buf_din_hi = {{(129-`PCX_WIDTH){1\'b0}},cpu_buf_din[`PCX_WIDTH-1:64]};\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:152: Define or directive not defined: \'`PCX_WIDTH\'\n   assign       cpu_buf_din_hi = {{(129-`PCX_WIDTH){1\'b0}},cpu_buf_din[`PCX_WIDTH-1:64]};\n                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:156: Define or directive not defined: \'`PCX_WIDTH\'\n   wire [`PCX_WIDTH-1:0]        pcx_iob_data;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:157: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data0_din;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:158: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data1_din;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:159: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   wire [`IOB_MONDO_SRC_WIDTH-1:0]    io_mondo_source_din;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:161: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din_d1;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:162: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din_d1;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fdp.v:163: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   wire [`IOB_MONDO_SRC_WIDTH-1:0]    mondo_source_din_d1;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module c2i_fdp (

   pcx_iob_vld, pcx_iob_req, pcx_iob_addr, pcx_iob_cputhr, 
   int_buf_din_raw, tap_mondo_dout_d2_f, mondo_data0_din_lo, 
   mondo_data0_din_hi, mondo_data1_din_lo, mondo_data1_din_hi, 
   mondo_source_din, mondo_busy_din_p1, mondo_busy_din_p2, 
   cpu_buf_din_lo, cpu_buf_din_hi, 

   cpu_clk, tx_sync, rx_sync, pcx_iob_data_px2, io_mondo_data_wr, 
   mondo_data_bypass_d1, mondo_addr_creg_mdata0_dec_d1, 
   mondo_addr_creg_mdata1_dec_d1, mondo_addr_creg_mbusy_dec_d1, 
   cpu_mondo_rd_d1, tap_mondo_rd_d1, cpu_mondo_rd_d2, 
   cpu_mondo_addr_invld_d2, mondo_data_addr_p0_d1, 
   io_mondo_data0_din_s, io_mondo_data1_din_s, io_mondo_source_din_s, 
   tap_mondo_din_s, mondo_data0_dout_lo, mondo_data0_dout_hi, 
   mondo_data1_dout_lo, mondo_data1_dout_hi, mondo_source_dout, 
   mondo_busy_dout
   );
   




   input 			      cpu_clk;
   input 			      tx_sync;
   input 			      rx_sync;
   
   

   input [`PCX_WIDTH-1:0] 	      pcx_iob_data_px2;



   output 		              pcx_iob_vld;
   output [`PCX_RQ_HI-`PCX_RQ_LO:0]   pcx_iob_req;
   output [`PCX_AD_HI-`PCX_AD_LO:0]   pcx_iob_addr;
   output [`PCX_CP_HI-`PCX_TH_LO:0]   pcx_iob_cputhr;
   
   input 			      io_mondo_data_wr;
   input 			      mondo_data_bypass_d1;
   input 			      mondo_addr_creg_mdata0_dec_d1;
   input 			      mondo_addr_creg_mdata1_dec_d1;
   input 			      mondo_addr_creg_mbusy_dec_d1;
   input 			      cpu_mondo_rd_d1;
   input 			      tap_mondo_rd_d1;
   input 			      cpu_mondo_rd_d2;
   input 			      cpu_mondo_addr_invld_d2;
   
   input [`IOB_MONDO_DATA_INDEX-1:0]  mondo_data_addr_p0_d1;

   

   wire [`IOB_INT_BUF_WIDTH-1:0]      int_buf_din;
   output [159:0] 		      int_buf_din_raw;

   assign 	int_buf_din_raw = {{(160-`IOB_INT_BUF_WIDTH){1'b0}},int_buf_din};

   

   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data0_din_s;
   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data1_din_s;
   input [`IOB_MONDO_SRC_WIDTH-1:0]   io_mondo_source_din_s;



   input [63:0] 		      tap_mondo_din_s;
   output [63:0] 		      tap_mondo_dout_d2_f;

   

   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_dout;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_dout;
   
   output [64:0] 		      mondo_data0_din_lo;
   input [64:0] 		      mondo_data0_dout_lo;
   output [64:0] 		      mondo_data0_din_hi;
   input [64:0] 		      mondo_data0_dout_hi;
   
   output [64:0] 		      mondo_data1_din_lo;
   input [64:0] 		      mondo_data1_dout_lo;
   output [64:0] 		      mondo_data1_din_hi;
   input [64:0] 		      mondo_data1_dout_hi;
   
   assign 	mondo_data0_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data0_din};
   assign 	mondo_data0_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data0_din};
   assign 	mondo_data0_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?
		                   mondo_data0_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :
		                   mondo_data0_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];
   
   assign 	mondo_data1_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data1_din};
   assign 	mondo_data1_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data1_din};
   assign 	mondo_data1_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?
		                   mondo_data1_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :
		                   mondo_data1_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];
   
   output [`IOB_MONDO_SRC_WIDTH-1:0]  mondo_source_din;
   input [`IOB_MONDO_SRC_WIDTH-1:0]   mondo_source_dout;
   output 			      mondo_busy_din_p1;
   output 			      mondo_busy_din_p2;
   input 			      mondo_busy_dout;
   
   

   wire [`PCX_WIDTH-1:0] 	      cpu_buf_din;
   output [64:0] 		      cpu_buf_din_lo;
   output [64:0] 		      cpu_buf_din_hi;
   
   assign       cpu_buf_din_lo = {1'b0,cpu_buf_din[63:0]};
   assign       cpu_buf_din_hi = {{(129-`PCX_WIDTH){1'b0}},cpu_buf_din[`PCX_WIDTH-1:64]};

   

   wire [`PCX_WIDTH-1:0] 	      pcx_iob_data;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data0_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data1_din;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    io_mondo_source_din;
   wire [63:0] 			      tap_mondo_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din_d1;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din_d1;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    mondo_source_din_d1;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_dout_byp;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_dout_byp;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    mondo_source_dout_byp;
   wire [63:0] 			      mondo_dout;
   wire [63:0] 			      cpu_mondo_dout_d2;
   wire [`IOB_CPU_INDEX-1:0] 	      cpu_mondo_cpu_id_d1;
   wire [`IOB_CPU_INDEX-1:0] 	      cpu_mondo_cpu_id_d2;
   wire [`IOB_THR_INDEX-1:0] 	      cpu_mondo_thr_id_d1;
   wire [`IOB_THR_INDEX-1:0] 	      cpu_mondo_thr_id_d2;
   wire [`PCX_P_HI-`PCX_P_LO:0]       cpu_mondo_pkt_id_d1;
   wire [`PCX_P_HI-`PCX_P_LO:0]       cpu_mondo_pkt_id_d2;
   wire 			      cpu_mondo_b109_d1;
   wire 			      cpu_mondo_b109_d2;
   wire [`IOB_CPU_WIDTH-1:0] 	      cpu_mondo_cpu_id_dec_d2;
   wire [63:0] 			      tap_mondo_dout_d2;
   





   dff_ns #(`PCX_WIDTH) pcx_iob_data_ff (.din(pcx_iob_data_px2),
					 .clk(cpu_clk),
					 .q(pcx_iob_data));

   assign       cpu_buf_din = pcx_iob_data;
   
   assign 	pcx_iob_vld = pcx_iob_data[`PCX_VLD];
   assign 	pcx_iob_req = pcx_iob_data[`PCX_RQ_HI:`PCX_RQ_LO];
   assign 	pcx_iob_addr = pcx_iob_data[`PCX_AD_HI:`PCX_AD_LO];
   assign 	pcx_iob_cputhr = pcx_iob_data[`PCX_CP_HI:`PCX_TH_LO];
   



   dffe_ns #(`IOB_MONDO_DATA_WIDTH) io_mondo_data0_din_ff (.din(io_mondo_data0_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data0_din));
   
   dffe_ns #(`IOB_MONDO_DATA_WIDTH) io_mondo_data1_din_ff (.din(io_mondo_data1_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data1_din));
   
   dffe_ns #(`IOB_MONDO_SRC_WIDTH) io_mondo_source_din_ff (.din(io_mondo_source_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_source_din));
   
   dffe_ns #(64) tap_mondo_din_ff (.din(tap_mondo_din_s),
				   .en(rx_sync),
				   .clk(cpu_clk),
				   .q(tap_mondo_din));

   assign 	mondo_data0_din = io_mondo_data_wr ? io_mondo_data0_din :
	                                             tap_mondo_din;
   
   dff_ns #(`IOB_MONDO_DATA_WIDTH) mondo_data0_din_d1_ff (.din(mondo_data0_din),
							  .clk(cpu_clk),
							  .q(mondo_data0_din_d1));
   
   assign 	mondo_data1_din = io_mondo_data_wr ? io_mondo_data1_din :
	                                             tap_mondo_din;
   
   dff_ns #(`IOB_MONDO_DATA_WIDTH) mondo_data1_din_d1_ff (.din(mondo_data1_din),
							  .clk(cpu_clk),
							  .q(mondo_data1_din_d1));
   
   assign 	mondo_source_din = io_mondo_data_wr ? io_mondo_source_din :
	                                              tap_mondo_din[`IOB_MONDO_SRC_WIDTH-1:0];
   
   dff_ns #(`IOB_MONDO_SRC_WIDTH) mondo_source_din_d1_ff (.din(mondo_source_din),
							  .clk(cpu_clk),
							  .q(mondo_source_din_d1));

   assign 	mondo_busy_din_p1 = io_mondo_data_wr ? 1'b1 :
		                                       tap_mondo_din[`IOB_MONDO_BUSY];
   
   assign 	mondo_busy_din_p2 = pcx_iob_data[`IOB_MONDO_BUSY];
   
   

   assign 	mondo_data0_dout_byp = mondo_data_bypass_d1 ? mondo_data0_din_d1 :
	                                                      mondo_data0_dout;
   
   assign 	mondo_data1_dout_byp = mondo_data_bypass_d1 ? mondo_data1_din_d1 :
	                                                      mondo_data1_dout;
   
   assign 	mondo_source_dout_byp = mondo_data_bypass_d1 ? mondo_source_din_d1 :
	                                                       mondo_source_dout;


   assign 	mondo_dout = ({64{mondo_addr_creg_mdata0_dec_d1}}  & mondo_data0_dout_byp) |
                             ({64{mondo_addr_creg_mdata1_dec_d1}}  & mondo_data1_dout_byp) |
		             ({64{mondo_addr_creg_mbusy_dec_d1}}   & {58'b0,mondo_busy_dout,mondo_source_dout_byp});
   
   dffe_ns #(64) cpu_mondo_dout_d2_ff (.din(mondo_dout),
				       .en(cpu_mondo_rd_d1),
				       .clk(cpu_clk),
				       .q(cpu_mondo_dout_d2));

   
   dff_ns #(`IOB_CPU_INDEX) cpu_mondo_cpu_id_d1_ff (.din(pcx_iob_data[`PCX_CP_HI:`PCX_CP_LO]),
						    .clk(cpu_clk),
						    .q(cpu_mondo_cpu_id_d1));
   
   dff_ns #(`IOB_CPU_INDEX) cpu_mondo_cpu_id_d2_ff (.din(cpu_mondo_cpu_id_d1),
						    .clk(cpu_clk),
						    .q(cpu_mondo_cpu_id_d2));
   
   
   dff_ns #(`IOB_THR_INDEX) cpu_mondo_thr_id_d1_ff (.din(pcx_iob_data[`PCX_TH_HI:`PCX_TH_LO]),
						    .clk(cpu_clk),
						    .q(cpu_mondo_thr_id_d1));
   
   dff_ns #(`IOB_THR_INDEX) cpu_mondo_thr_id_d2_ff (.din(cpu_mondo_thr_id_d1),
						    .clk(cpu_clk),
						    .q(cpu_mondo_thr_id_d2));

   
   dff_ns #(`PCX_P_HI-`PCX_P_LO+1) cpu_mondo_pkt_id_d1_ff (.din(pcx_iob_data[`PCX_P_HI:`PCX_P_LO]),
							   .clk(cpu_clk),
							   .q(cpu_mondo_pkt_id_d1));
   
   dff_ns #(`PCX_P_HI-`PCX_P_LO+1) cpu_mondo_pkt_id_d2_ff (.din(cpu_mondo_pkt_id_d1),
							   .clk(cpu_clk),
							   .q(cpu_mondo_pkt_id_d2));

   
   dff_ns #(1) cpu_mondo_b109_d1_ff (.din(pcx_iob_data[109]),
				     .clk(cpu_clk),
				     .q(cpu_mondo_b109_d1));
   
   dff_ns #(1) cpu_mondo_b109_d2_ff (.din(cpu_mondo_b109_d1),
				     .clk(cpu_clk),
				     .q(cpu_mondo_b109_d2));

   
   assign 	cpu_mondo_cpu_id_dec_d2 = 1'b1 << cpu_mondo_cpu_id_d2;
   
   assign 	int_buf_din = cpu_mondo_rd_d2 ?

		              {cpu_mondo_cpu_id_dec_d2,
			       1'b1,
			       `LOAD_RET,
			       1'b0,cpu_mondo_addr_invld_d2,1'b0,
			       1'b1,
			       cpu_mondo_thr_id_d2,
			       3'b0,
			       3'b0,
	                       cpu_mondo_dout_d2,
			       cpu_mondo_dout_d2} :

		              {cpu_mondo_cpu_id_dec_d2,
			       1'b1,
			       `ST_ACK,
			       3'b0,
			       1'b1,
			       cpu_mondo_thr_id_d2,
			       2'b0,
			       cpu_mondo_pkt_id_d2,
			       1'b0,
			       1'b0,
			       2'b0,
			       cpu_mondo_b109_d2,
			       4'b0,
			       cpu_mondo_cpu_id_d2,
			       118'b0};
   
   

   dffe_ns #(64) tap_mondo_dout_d2_ff (.din(mondo_dout),
				       .en(tap_mondo_rd_d1),
				       .clk(cpu_clk),
				       .q(tap_mondo_dout_d2));


   dffe_ns #(64) tap_mondo_dout_d2_f_ff (.din(tap_mondo_dout_d2),
					 .en(tx_sync),
					 .clk(cpu_clk),
					 .q(tap_mondo_dout_d2_f));
   

endmodule
module c2i_fdp (

   pcx_iob_vld, pcx_iob_req, pcx_iob_addr, pcx_iob_cputhr, 
   int_buf_din_raw, tap_mondo_dout_d2_f, mondo_data0_din_lo, 
   mondo_data0_din_hi, mondo_data1_din_lo, mondo_data1_din_hi, 
   mondo_source_din, mondo_busy_din_p1, mondo_busy_din_p2, 
   cpu_buf_din_lo, cpu_buf_din_hi, 

   cpu_clk, tx_sync, rx_sync, pcx_iob_data_px2, io_mondo_data_wr, 
   mondo_data_bypass_d1, mondo_addr_creg_mdata0_dec_d1, 
   mondo_addr_creg_mdata1_dec_d1, mondo_addr_creg_mbusy_dec_d1, 
   cpu_mondo_rd_d1, tap_mondo_rd_d1, cpu_mondo_rd_d2, 
   cpu_mondo_addr_invld_d2, mondo_data_addr_p0_d1, 
   io_mondo_data0_din_s, io_mondo_data1_din_s, io_mondo_source_din_s, 
   tap_mondo_din_s, mondo_data0_dout_lo, mondo_data0_dout_hi, 
   mondo_data1_dout_lo, mondo_data1_dout_hi, mondo_source_dout, 
   mondo_busy_dout
   );

   




   input 			      cpu_clk;
   input 			      tx_sync;
   input 			      rx_sync;
   
   

   input [`PCX_WIDTH-1:0] 	      pcx_iob_data_px2;



   output 		              pcx_iob_vld;
   output [`PCX_RQ_HI-`PCX_RQ_LO:0]   pcx_iob_req;
   output [`PCX_AD_HI-`PCX_AD_LO:0]   pcx_iob_addr;
   output [`PCX_CP_HI-`PCX_TH_LO:0]   pcx_iob_cputhr;
   
   input 			      io_mondo_data_wr;
   input 			      mondo_data_bypass_d1;
   input 			      mondo_addr_creg_mdata0_dec_d1;
   input 			      mondo_addr_creg_mdata1_dec_d1;
   input 			      mondo_addr_creg_mbusy_dec_d1;
   input 			      cpu_mondo_rd_d1;
   input 			      tap_mondo_rd_d1;
   input 			      cpu_mondo_rd_d2;
   input 			      cpu_mondo_addr_invld_d2;
   
   input [`IOB_MONDO_DATA_INDEX-1:0]  mondo_data_addr_p0_d1;

   

   wire [`IOB_INT_BUF_WIDTH-1:0]      int_buf_din;
   output [159:0] 		      int_buf_din_raw;

   assign 	int_buf_din_raw = {{(160-`IOB_INT_BUF_WIDTH){1'b0}},int_buf_din};

   

   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data0_din_s;
   input [`IOB_MONDO_DATA_WIDTH-1:0]  io_mondo_data1_din_s;
   input [`IOB_MONDO_SRC_WIDTH-1:0]   io_mondo_source_din_s;



   input [63:0] 		      tap_mondo_din_s;
   output [63:0] 		      tap_mondo_dout_d2_f;

   

   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_dout;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_dout;
   
   output [64:0] 		      mondo_data0_din_lo;
   input [64:0] 		      mondo_data0_dout_lo;
   output [64:0] 		      mondo_data0_din_hi;
   input [64:0] 		      mondo_data0_dout_hi;
   
   output [64:0] 		      mondo_data1_din_lo;
   input [64:0] 		      mondo_data1_dout_lo;
   output [64:0] 		      mondo_data1_din_hi;
   input [64:0] 		      mondo_data1_dout_hi;
   
   assign 	mondo_data0_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data0_din};
   assign 	mondo_data0_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data0_din};
   assign 	mondo_data0_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?
		                   mondo_data0_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :
		                   mondo_data0_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];
   
   assign 	mondo_data1_din_lo = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data1_din};
   assign 	mondo_data1_din_hi = {{(65-`IOB_MONDO_DATA_WIDTH){1'b0}},mondo_data1_din};
   assign 	mondo_data1_dout = mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1] ?
		                   mondo_data1_dout_hi[`IOB_MONDO_DATA_WIDTH-1:0] :
		                   mondo_data1_dout_lo[`IOB_MONDO_DATA_WIDTH-1:0];
   
   output [`IOB_MONDO_SRC_WIDTH-1:0]  mondo_source_din;
   input [`IOB_MONDO_SRC_WIDTH-1:0]   mondo_source_dout;
   output 			      mondo_busy_din_p1;
   output 			      mondo_busy_din_p2;
   input 			      mondo_busy_dout;
   
   

   wire [`PCX_WIDTH-1:0] 	      cpu_buf_din;
   output [64:0] 		      cpu_buf_din_lo;
   output [64:0] 		      cpu_buf_din_hi;
   
   assign       cpu_buf_din_lo = {1'b0,cpu_buf_din[63:0]};
   assign       cpu_buf_din_hi = {{(129-`PCX_WIDTH){1'b0}},cpu_buf_din[`PCX_WIDTH-1:64]};

   

   wire [`PCX_WIDTH-1:0] 	      pcx_iob_data;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data0_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   io_mondo_data1_din;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    io_mondo_source_din;
   wire [63:0] 			      tap_mondo_din;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_din_d1;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_din_d1;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    mondo_source_din_d1;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data0_dout_byp;
   wire [`IOB_MONDO_DATA_WIDTH-1:0]   mondo_data1_dout_byp;
   wire [`IOB_MONDO_SRC_WIDTH-1:0]    mondo_source_dout_byp;
   wire [63:0] 			      mondo_dout;
   wire [63:0] 			      cpu_mondo_dout_d2;
   wire [`IOB_CPU_INDEX-1:0] 	      cpu_mondo_cpu_id_d1;
   wire [`IOB_CPU_INDEX-1:0] 	      cpu_mondo_cpu_id_d2;
   wire [`IOB_THR_INDEX-1:0] 	      cpu_mondo_thr_id_d1;
   wire [`IOB_THR_INDEX-1:0] 	      cpu_mondo_thr_id_d2;
   wire [`PCX_P_HI-`PCX_P_LO:0]       cpu_mondo_pkt_id_d1;
   wire [`PCX_P_HI-`PCX_P_LO:0]       cpu_mondo_pkt_id_d2;
   wire 			      cpu_mondo_b109_d1;
   wire 			      cpu_mondo_b109_d2;
   wire [`IOB_CPU_WIDTH-1:0] 	      cpu_mondo_cpu_id_dec_d2;
   wire [63:0] 			      tap_mondo_dout_d2;
   





   dff_ns #(`PCX_WIDTH) pcx_iob_data_ff (.din(pcx_iob_data_px2),
					 .clk(cpu_clk),
					 .q(pcx_iob_data));

   assign       cpu_buf_din = pcx_iob_data;
   
   assign 	pcx_iob_vld = pcx_iob_data[`PCX_VLD];
   assign 	pcx_iob_req = pcx_iob_data[`PCX_RQ_HI:`PCX_RQ_LO];
   assign 	pcx_iob_addr = pcx_iob_data[`PCX_AD_HI:`PCX_AD_LO];
   assign 	pcx_iob_cputhr = pcx_iob_data[`PCX_CP_HI:`PCX_TH_LO];
   



   dffe_ns #(`IOB_MONDO_DATA_WIDTH) io_mondo_data0_din_ff (.din(io_mondo_data0_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data0_din));
   
   dffe_ns #(`IOB_MONDO_DATA_WIDTH) io_mondo_data1_din_ff (.din(io_mondo_data1_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data1_din));
   
   dffe_ns #(`IOB_MONDO_SRC_WIDTH) io_mondo_source_din_ff (.din(io_mondo_source_din_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_source_din));
   
   dffe_ns #(64) tap_mondo_din_ff (.din(tap_mondo_din_s),
				   .en(rx_sync),
				   .clk(cpu_clk),
				   .q(tap_mondo_din));

   assign 	mondo_data0_din = io_mondo_data_wr ? io_mondo_data0_din :
	                                             tap_mondo_din;
   
   dff_ns #(`IOB_MONDO_DATA_WIDTH) mondo_data0_din_d1_ff (.din(mondo_data0_din),
							  .clk(cpu_clk),
							  .q(mondo_data0_din_d1));
   
   assign 	mondo_data1_din = io_mondo_data_wr ? io_mondo_data1_din :
	                                             tap_mondo_din;
   
   dff_ns #(`IOB_MONDO_DATA_WIDTH) mondo_data1_din_d1_ff (.din(mondo_data1_din),
							  .clk(cpu_clk),
							  .q(mondo_data1_din_d1));
   
   assign 	mondo_source_din = io_mondo_data_wr ? io_mondo_source_din :
	                                              tap_mondo_din[`IOB_MONDO_SRC_WIDTH-1:0];
   
   dff_ns #(`IOB_MONDO_SRC_WIDTH) mondo_source_din_d1_ff (.din(mondo_source_din),
							  .clk(cpu_clk),
							  .q(mondo_source_din_d1));

   assign 	mondo_busy_din_p1 = io_mondo_data_wr ? 1'b1 :
		                                       tap_mondo_din[`IOB_MONDO_BUSY];
   
   assign 	mondo_busy_din_p2 = pcx_iob_data[`IOB_MONDO_BUSY];
   
   

   assign 	mondo_data0_dout_byp = mondo_data_bypass_d1 ? mondo_data0_din_d1 :
	                                                      mondo_data0_dout;
   
   assign 	mondo_data1_dout_byp = mondo_data_bypass_d1 ? mondo_data1_din_d1 :
	                                                      mondo_data1_dout;
   
   assign 	mondo_source_dout_byp = mondo_data_bypass_d1 ? mondo_source_din_d1 :
	                                                       mondo_source_dout;


   assign 	mondo_dout = ({64{mondo_addr_creg_mdata0_dec_d1}}  & mondo_data0_dout_byp) |
                             ({64{mondo_addr_creg_mdata1_dec_d1}}  & mondo_data1_dout_byp) |
		             ({64{mondo_addr_creg_mbusy_dec_d1}}   & {58'b0,mondo_busy_dout,mondo_source_dout_byp});
   
   dffe_ns #(64) cpu_mondo_dout_d2_ff (.din(mondo_dout),
				       .en(cpu_mondo_rd_d1),
				       .clk(cpu_clk),
				       .q(cpu_mondo_dout_d2));

   
   dff_ns #(`IOB_CPU_INDEX) cpu_mondo_cpu_id_d1_ff (.din(pcx_iob_data[`PCX_CP_HI:`PCX_CP_LO]),
						    .clk(cpu_clk),
						    .q(cpu_mondo_cpu_id_d1));
   
   dff_ns #(`IOB_CPU_INDEX) cpu_mondo_cpu_id_d2_ff (.din(cpu_mondo_cpu_id_d1),
						    .clk(cpu_clk),
						    .q(cpu_mondo_cpu_id_d2));
   
   
   dff_ns #(`IOB_THR_INDEX) cpu_mondo_thr_id_d1_ff (.din(pcx_iob_data[`PCX_TH_HI:`PCX_TH_LO]),
						    .clk(cpu_clk),
						    .q(cpu_mondo_thr_id_d1));
   
   dff_ns #(`IOB_THR_INDEX) cpu_mondo_thr_id_d2_ff (.din(cpu_mondo_thr_id_d1),
						    .clk(cpu_clk),
						    .q(cpu_mondo_thr_id_d2));

   
   dff_ns #(`PCX_P_HI-`PCX_P_LO+1) cpu_mondo_pkt_id_d1_ff (.din(pcx_iob_data[`PCX_P_HI:`PCX_P_LO]),
							   .clk(cpu_clk),
							   .q(cpu_mondo_pkt_id_d1));
   
   dff_ns #(`PCX_P_HI-`PCX_P_LO+1) cpu_mondo_pkt_id_d2_ff (.din(cpu_mondo_pkt_id_d1),
							   .clk(cpu_clk),
							   .q(cpu_mondo_pkt_id_d2));

   
   dff_ns #(1) cpu_mondo_b109_d1_ff (.din(pcx_iob_data[109]),
				     .clk(cpu_clk),
				     .q(cpu_mondo_b109_d1));
   
   dff_ns #(1) cpu_mondo_b109_d2_ff (.din(cpu_mondo_b109_d1),
				     .clk(cpu_clk),
				     .q(cpu_mondo_b109_d2));

   
   assign 	cpu_mondo_cpu_id_dec_d2 = 1'b1 << cpu_mondo_cpu_id_d2;
   
   assign 	int_buf_din = cpu_mondo_rd_d2 ?

		              {cpu_mondo_cpu_id_dec_d2,
			       1'b1,
			       `LOAD_RET,
			       1'b0,cpu_mondo_addr_invld_d2,1'b0,
			       1'b1,
			       cpu_mondo_thr_id_d2,
			       3'b0,
			       3'b0,
	                       cpu_mondo_dout_d2,
			       cpu_mondo_dout_d2} :

		              {cpu_mondo_cpu_id_dec_d2,
			       1'b1,
			       `ST_ACK,
			       3'b0,
			       1'b1,
			       cpu_mondo_thr_id_d2,
			       2'b0,
			       cpu_mondo_pkt_id_d2,
			       1'b0,
			       1'b0,
			       2'b0,
			       cpu_mondo_b109_d2,
			       4'b0,
			       cpu_mondo_cpu_id_d2,
			       118'b0};
   
   

   dffe_ns #(64) tap_mondo_dout_d2_ff (.din(mondo_dout),
				       .en(tap_mondo_rd_d1),
				       .clk(cpu_clk),
				       .q(tap_mondo_dout_d2));


   dffe_ns #(64) tap_mondo_dout_d2_f_ff (.din(tap_mondo_dout_d2),
					 .en(tx_sync),
					 .clk(cpu_clk),
					 .q(tap_mondo_dout_d2_f));
   

endmodule