data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:60: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'RBUF\'\nmodule RBUF\n       ^~~~\n                                                                                  : ... Top module \'CLKDIV\'\nmodule CLKDIV\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:80: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                               : ... In instance CLKDIV\n                if(cnt == (DIV_CNT-1)) begin\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:25: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n    assign dout = read ? bufdat[curhead] : 0;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:50: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n                    bufdat[curtail] <= din;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/467394306/verilog/ctrl/ctrl_aux.v:53: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance RBUF\n                    bufdat[curtail] <= din;\n                          ^\n%Error: Exiting due to 5 warning(s)\n'
module CLKDIV
    #(parameter DIV_CNT = 8, parameter BITS = 3)
    (
        input clk,
        input rstn,
        input enable,
        output clkout
    );


    reg [BITS-1:0] cnt;
    reg clkreg;
    assign clkout = clkreg;

    always @ (posedge clk) begin
        if(!rstn) begin
            clkreg <= 1;
            cnt <= 0;
        end else begin
            if(enable) begin
                if(cnt == (DIV_CNT-1)) begin
                    clkreg <= ~clkreg;
                    cnt <= 0;
                end else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end
endmodule
module CLKDIV
    #(parameter DIV_CNT = 8, parameter BITS = 3)
    (
        input clk,
        input rstn,
        input enable,
        output clkout
    );



    reg [BITS-1:0] cnt;
    reg clkreg;
    assign clkout = clkreg;

    always @ (posedge clk) begin
        if(!rstn) begin
            clkreg <= 1;
            cnt <= 0;
        end else begin
            if(enable) begin
                if(cnt == (DIV_CNT-1)) begin
                    clkreg <= ~clkreg;
                    cnt <= 0;
                end else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end
endmodule