data/full_repos/permissive/46981098/register_mem/tb_regmem.v
1: b'%Error: data/full_repos/permissive/46981098/register_mem/tb_regmem.v:19: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/46981098/register_mem/tb_regmem.v:20: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46981098/register_mem/tb_regmem.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46981098/register_mem/tb_regmem.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/register_mem/tb_regmem.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registerMemory_tb();
	
  	reg[4:0]read_reg1;
  	reg[4:0]read_reg2;
  	reg[4:0]write_reg;
  	reg regwrite_con;
  	reg[31:0]write_data;
  	reg[31:0]data1;
  	reg[31:0]data2;

  

  registerMemory tb(read_reg1,read_reg2,write_reg,regwrite_con,write_data,data1,data2);
   
  initial 
    begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
      repeat (100);
    end
  initial begin

      read_reg1    = 5'b00000;
      read_reg2    = 5'b01000;
      write_reg    = 5'b01000;
      write_data   = 5'b01111;
      regwrite_con = 1'b1;
      #10
      read_reg1    = 5'b00011;
      read_reg2    = 5'b00000;
      write_reg    = 5'b00011;
      write_data   = 5'b00111;
      regwrite_con = 1'b1;
      #10
      read_reg1    = 5'b00000;
      read_reg2    = 5'b01000;
      write_reg    = 5'b01000;
      write_data   = 5'b01111;
      regwrite_con = 1'b0;
      #10
      $finish;
    end
endmodule
module registerMemory_tb();

	
  	reg[4:0]read_reg1;
  	reg[4:0]read_reg2;
  	reg[4:0]write_reg;
  	reg regwrite_con;
  	reg[31:0]write_data;
  	reg[31:0]data1;
  	reg[31:0]data2;

  

  registerMemory tb(read_reg1,read_reg2,write_reg,regwrite_con,write_data,data1,data2);
   
  initial 
    begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
      repeat (100);
    end
  initial begin

      read_reg1    = 5'b00000;
      read_reg2    = 5'b01000;
      write_reg    = 5'b01000;
      write_data   = 5'b01111;
      regwrite_con = 1'b1;
      #10
      read_reg1    = 5'b00011;
      read_reg2    = 5'b00000;
      write_reg    = 5'b00011;
      write_data   = 5'b00111;
      regwrite_con = 1'b1;
      #10
      read_reg1    = 5'b00000;
      read_reg2    = 5'b01000;
      write_reg    = 5'b01000;
      write_data   = 5'b01111;
      regwrite_con = 1'b0;
      #10
      $finish;
    end
endmodule