data/full_repos/permissive/479997390/src/PC.v
data/verilator_xmls/66b0258d-99c4-4ae8-8ace-b5c52a470ac2.xml
module PC (

   clk, rst, WriteEnable,
   NextPC, PC

);

   input clk, rst;
   input WriteEnable;
   input [31:0] NextPC;









   output reg [31:0] PC;



   
   always @(posedge clk or posedge rst) begin
      if (rst) begin
         PC <= 32'h00003000;
      end else begin
         if (WriteEnable) begin
            PC <= NextPC;
         end else begin
            PC <= PC;
         end













      end
   end












endmodule
module PC (

   clk, rst, WriteEnable,
   NextPC, PC

);


   input clk, rst;
   input WriteEnable;
   input [31:0] NextPC;









   output reg [31:0] PC;



   
   always @(posedge clk or posedge rst) begin
      if (rst) begin
         PC <= 32'h00003000;
      end else begin
         if (WriteEnable) begin
            PC <= NextPC;
         end else begin
            PC <= PC;
         end













      end
   end












endmodule