data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v
1: b'%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:18: Cannot find include file: mikroislem.vh\n`include "mikroislem.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh.v\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh.sv\n             mikroislem.vh\n             mikroislem.vh.v\n             mikroislem.vh.sv\n             obj_dir/mikroislem.vh\n             obj_dir/mikroislem.vh.v\n             obj_dir/mikroislem.vh.sv\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:31: Define or directive not defined: \'`ADD\'\n            `ADD:   sonuc_c = islec1_g + islec2_g                                ;\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:31: syntax error, unexpected \':\', expecting endcase\n            `ADD:   sonuc_c = islec1_g + islec2_g                                ;\n                ^\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:32: Define or directive not defined: \'`SUB\'\n            `SUB:   sonuc_c = islec1_g - islec2_g                                ;\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:33: Define or directive not defined: \'`AND\'\n            `AND:   sonuc_c = islec1_g & islec2_g                                ;\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:34: Define or directive not defined: \'`OR\'\n            `OR:    sonuc_c = islec1_g | islec2_g                                ;\n            ^~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:35: Define or directive not defined: \'`XOR\'\n            `XOR:   sonuc_c = islec1_g ^ islec2_g                                ;\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:36: Define or directive not defined: \'`SLT\'\n            `SLT:   sonuc_c = ($signed(islec1_g) < $signed(islec2_g))            ; \n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:37: Define or directive not defined: \'`SLTU\'\n            `SLTU:  sonuc_c = (islec1_g < islec2_g)                              ; \n            ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:38: Define or directive not defined: \'`SLL\'\n            `SLL:   sonuc_c = islec1_g << islec2_g[4:0]                          ; \n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:39: Define or directive not defined: \'`SRL\'\n            `SRL:   sonuc_c = $signed({1\'b0, islec1_g}) >>> islec2_g[4:0]        ; \n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:40: Define or directive not defined: \'`SRA\'\n            `SRA:   sonuc_c = $signed({islec1_g[31], islec1_g}) >>> islec2_g[4:0]; \n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:41: Define or directive not defined: \'`LUI\'\n            `LUI:   sonuc_c = islec2_g[19:0]  << 12                              ;  \n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/aritmetik_mantik_birimi.v:42: Define or directive not defined: \'`AUIPC\'\n            `AUIPC: sonuc_c = islec1_g + (islec2_g[19:0]  << 12)                 ;  \n            ^~~~~~\n%Error: Cannot continue\n'
module aritmetik_mantik_birimi(
    input         [11:0]    islev_kodu_g                                         ,
    input         [31:0]    islec1_g                                             ,
    input         [31:0]    islec2_g                                             ,
    output reg    [31:0]    sonuc_c
    );
    
    always@* begin
        sonuc_c             = 0                                                  ;
        case(islev_kodu_g)
            `ADD:   sonuc_c = islec1_g + islec2_g                                ;
            `SUB:   sonuc_c = islec1_g - islec2_g                                ;
            `AND:   sonuc_c = islec1_g & islec2_g                                ;
            `OR:    sonuc_c = islec1_g | islec2_g                                ;
            `XOR:   sonuc_c = islec1_g ^ islec2_g                                ;
            `SLT:   sonuc_c = ($signed(islec1_g) < $signed(islec2_g))            ; 
            `SLTU:  sonuc_c = (islec1_g < islec2_g)                              ; 
            `SLL:   sonuc_c = islec1_g << islec2_g[4:0]                          ; 
            `SRL:   sonuc_c = $signed({1'b0, islec1_g}) >>> islec2_g[4:0]        ; 
            `SRA:   sonuc_c = $signed({islec1_g[31], islec1_g}) >>> islec2_g[4:0]; 
            `LUI:   sonuc_c = islec2_g[19:0]  << 12                              ;
            `AUIPC: sonuc_c = islec1_g + (islec2_g[19:0]  << 12)                 ;
        endcase
    end

    
endmodule
module aritmetik_mantik_birimi(
    input         [11:0]    islev_kodu_g                                         ,
    input         [31:0]    islec1_g                                             ,
    input         [31:0]    islec2_g                                             ,
    output reg    [31:0]    sonuc_c
    );

    
    always@* begin
        sonuc_c             = 0                                                  ;
        case(islev_kodu_g)
            `ADD:   sonuc_c = islec1_g + islec2_g                                ;
            `SUB:   sonuc_c = islec1_g - islec2_g                                ;
            `AND:   sonuc_c = islec1_g & islec2_g                                ;
            `OR:    sonuc_c = islec1_g | islec2_g                                ;
            `XOR:   sonuc_c = islec1_g ^ islec2_g                                ;
            `SLT:   sonuc_c = ($signed(islec1_g) < $signed(islec2_g))            ; 
            `SLTU:  sonuc_c = (islec1_g < islec2_g)                              ; 
            `SLL:   sonuc_c = islec1_g << islec2_g[4:0]                          ; 
            `SRL:   sonuc_c = $signed({1'b0, islec1_g}) >>> islec2_g[4:0]        ; 
            `SRA:   sonuc_c = $signed({islec1_g[31], islec1_g}) >>> islec2_g[4:0]; 
            `LUI:   sonuc_c = islec2_g[19:0]  << 12                              ;
            `AUIPC: sonuc_c = islec1_g + (islec2_g[19:0]  << 12)                 ;
        endcase
    end

    
endmodule