data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/acc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/acc.v:14: Operator ASSIGNDLY expects 34 bits on the Assign RHS, but Assign RHS\'s VARREF \'addend\' generates 31 bits.\n                                                                                   : ... In instance acc\n       sum <= #1 addend;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/acc.v:16: Operator ADD expects 34 bits on the RHS, but RHS\'s VARREF \'addend\' generates 31 bits.\n                                                                                   : ... In instance acc\n       sum <= #1 sum + addend;\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
	    input signed [30:0] addend, output reg signed [33:0] sum );

   always @(posedge clock)
     if(reset)
       sum <= #1 34'd0;




     else if(clear)
       sum <= #1 addend;
     else if(enable_in)
       sum <= #1 sum + addend;

   always @(posedge clock)
     enable_out <= #1 enable_in;
   
endmodule
module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
	    input signed [30:0] addend, output reg signed [33:0] sum );


   always @(posedge clock)
     if(reset)
       sum <= #1 34'd0;




     else if(clear)
       sum <= #1 addend;
     else if(enable_in)
       sum <= #1 sum + addend;

   always @(posedge clock)
     enable_out <= #1 enable_in;
   
endmodule