data/full_repos/permissive/412289941/m_sequence.v
data/verilator_xmls/e2bc150b-2b4a-4462-af6f-abaec5fa5a3e.xml
module m_sequence(clk,rst,ena,data_out,load);

input clk;
input rst;
input ena;
output data_out;
output load;
reg data_out,load;
reg [6:0]temp;

always @(posedge clk or negedge rst) begin
    if(!rst) begin
            data_out <= 0;
            load <= 1'b0;
            temp <= 7'b1111_111;
    end
    else begin
        if(ena) begin

                load <= 1'b1;
                temp <= {temp[5:0],temp[2]^temp[6]};

            if(load)    data_out <= temp[6];
        end
        else load <= 1'b0;
    end
end

endmodule
module m_sequence(clk,rst,ena,data_out,load);


input clk;
input rst;
input ena;
output data_out;
output load;
reg data_out,load;
reg [6:0]temp;

always @(posedge clk or negedge rst) begin
    if(!rst) begin
            data_out <= 0;
            load <= 1'b0;
            temp <= 7'b1111_111;
    end
    else begin
        if(ena) begin

                load <= 1'b1;
                temp <= {temp[5:0],temp[2]^temp[6]};

            if(load)    data_out <= temp[6];
        end
        else load <= 1'b0;
    end
end

endmodule