data/full_repos/permissive/439379810/rtl/alu74181.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/439379810/rtl/alu74181.v:64: Multiple top level modules\n                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                         : ... Top module \'alu74181\'\nmodule alu74181(\n       ^~~~~~~~\n                                                                         : ... Top module \'cla74182\'\nmodule cla74182(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module cla74182(
	input wire [3:0] g,
	input wire [3:0] p,
	input wire cin,

	output wire pout,
	output wire gout,
	output wire coutx,
	output wire couty,
	output wire coutz
);
	assign coutx = p[0] &
		(cin | g[0]);
	assign couty = p[1] &
		(p[0] | g[1]) &
		(cin | g[0] | g[1]);
	assign coutz = p[2] &
		(p[1] | g[2]) &
		(p[0] | g[1] | g[2]) &
		(cin | g[0] | g[1] | g[2]);

	assign gout = g[0] | g[1] | g[2] | g[3];
	assign pout = p[3] &
		(p[2] | g[3]) &
		(p[1] | g[2] | g[3]) &
		(p[0] | g[1] | g[2] | g[3]);
endmodule
module cla74182(
	input wire [3:0] g,
	input wire [3:0] p,
	input wire cin,

	output wire pout,
	output wire gout,
	output wire coutx,
	output wire couty,
	output wire coutz
);

	assign coutx = p[0] &
		(cin | g[0]);
	assign couty = p[1] &
		(p[0] | g[1]) &
		(cin | g[0] | g[1]);
	assign coutz = p[2] &
		(p[1] | g[2]) &
		(p[0] | g[1] | g[2]) &
		(cin | g[0] | g[1] | g[2]);

	assign gout = g[0] | g[1] | g[2] | g[3];
	assign pout = p[3] &
		(p[2] | g[3]) &
		(p[1] | g[2] | g[3]) &
		(p[0] | g[1] | g[2] | g[3]);
endmodule