data/full_repos/permissive/519420376/RTL/test_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/519420376/RTL/test_top.v:49: Unsupported: Ignoring delay on this delayed statement.\n   always #5 i_clk = ~i_clk ;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519420376/RTL/test_top.v:55: Unsupported: Ignoring delay on this delayed statement.\n           #4 i_rst_n = 1\'b1 ;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/519420376/RTL/test_top.v:56: Unsupported: Ignoring delay on this delayed statement.\n            #2 d_in = 12\'b0000_0111_0001_0000;\n            ^\n%Error: data/full_repos/permissive/519420376/RTL/test_top.v:32: Cannot find file containing module: \'Top_design\'\nTop_design DUT(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Top_design\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Top_design.v\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Top_design.sv\n             Top_design\n             Top_design.v\n             Top_design.sv\n             obj_dir/Top_design\n             obj_dir/Top_design.v\n             obj_dir/Top_design.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top();
reg i_clk ; 
reg i_rst_n  ;
reg [11:0] d_in ;  
wire H_sync ; 
wire V_sync ;
wire [11:0]RGB_out ;


Top_design DUT(
i_clk , 
i_rst_n  ,
 d_in ,  
H_sync , 
V_sync ,  
RGB_out
);


initial
 begin
  i_clk = 1'b0;
   i_rst_n = 1'b0;
   d_in = 12'b0000_0010_0010_0011;
   end
   
   always #5 i_clk = ~i_clk ;
   
   
   
   initial
         begin
           #4 i_rst_n = 1'b1 ;
            #2 d_in = 12'b0000_0111_0001_0000;
            end 
            
endmodule
module test_top();

reg i_clk ; 
reg i_rst_n  ;
reg [11:0] d_in ;  
wire H_sync ; 
wire V_sync ;
wire [11:0]RGB_out ;


Top_design DUT(
i_clk , 
i_rst_n  ,
 d_in ,  
H_sync , 
V_sync ,  
RGB_out
);


initial
 begin
  i_clk = 1'b0;
   i_rst_n = 1'b0;
   d_in = 12'b0000_0010_0010_0011;
   end
   
   always #5 i_clk = ~i_clk ;
   
   
   
   initial
         begin
           #4 i_rst_n = 1'b1 ;
            #2 d_in = 12'b0000_0111_0001_0000;
            end 
            
endmodule