data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_1/d_ff.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_1,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_1/d_ff.v\n%Error: Exiting due to 5 error(s)\n'
module d_ff(
	input clock,
	input reset,
	input data_in,
	output reg q
);

	always @(posedge clock or negedge reset)
		if(~reset)
			q <= 0;
		else
			q <= data_in;

endmodule
module d_ff(
	input clock,
	input reset,
	input data_in,
	output reg q
);


	always @(posedge clock or negedge reset)
		if(~reset)
			q <= 0;
		else
			q <= data_in;

endmodule