data/full_repos/permissive/46804359/Adder_32b.v
data/verilator_xmls/02645d73-622d-4312-8b7a-eeaa387a5aee.xml
module Adder_32b(input0, input1, out, clk);

    input wire [31:0] input0;
    input wire [31:0] input1;
    input wire clk;

    output reg[31:0] out;

    always@(posedge clk)
    begin
        out <= input0 + input1;
    end
endmodule
module Adder_32b(input0, input1, out, clk);


    input wire [31:0] input0;
    input wire [31:0] input1;
    input wire clk;

    output reg[31:0] out;

    always@(posedge clk)
    begin
        out <= input0 + input1;
    end
endmodule