data/full_repos/permissive/497870922/testbench/tb_spi.v
1: b'%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:87: Unsupported: event data types\n event read, write, compare, acknow, check, change_cpol, change_cpha;\n ^~~~~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:102: syntax error, unexpected \';\', expecting IDENTIFIER or do or final\n wire int;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:111: Unsupported: Ignoring delay on this delayed statement.\n      # HALF_CLOCK_PERIOD_50M;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:113: Unsupported: Ignoring delay on this delayed statement.\n      # HALF_CLOCK_PERIOD_50M;\n      ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:119: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:120: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:121: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD;\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:140: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:145: syntax error, unexpected ->\n   -> write;\n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:149: syntax error, unexpected \')\', expecting "\'{"\n    while (~int) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:160: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:163: syntax error, unexpected ->\n   -> read;\n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:166: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:176: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:179: syntax error, unexpected ->\n   -> compare;\n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:185: syntax error, unexpected ->\n   -> acknow;\n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:209: syntax error, unexpected \')\', expecting "\'{"\n  .Int   (int)\n             ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:217: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do  (miso),\n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:217: syntax error, unexpected \'(\', expecting \')\'\n  .do  (miso),\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:234: Unsupported: Ignoring delay on this delayed statement.\n       #5;\n       ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:236: syntax error, unexpected \'@\'\n       repeat(1) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:241: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:252: syntax error, unexpected ->\n        ->change_cpha;\n        ^~\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:253: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:256: syntax error, unexpected ->\n        ->change_cpol;\n        ^~\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:283: syntax error, unexpected ->\n            -> check;\n            ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_spi.v:286: Unsupported: Use $display with %x format instead: $displayh\n      $displayh("MEM data: %p",spi_slave.mem);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_spi.v:300: Unsupported: Ignoring delay on this delayed statement.\n       #250000;  \n       ^\n%Error: Exiting due to 21 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_spi();




	reg  clk;
	reg  rstn;

	reg [1:0] cpol, cpha;
	reg [2:0] e = 0;

	wire sck, mosi, miso;
	wire [7:0] ss;
	reg [7:0] q;

	wire test_spi_cpol;
	wire test_spi_cpha;


	parameter HALF_CLOCK_PERIOD_50M 	= 10;
	parameter HALF_CLOCK_PERIOD_10M 	= 50;
	parameter HALF_CLOCK_PERIOD_1M 		= 500;
	parameter HALF_CLOCK_PERIOD_100K 	= 5000;
	parameter PERIOD = 100;

	event read, write, compare, acknow, check, change_cpol, change_cpha;




	integer n;

	reg wr_en = 0;
	reg rd_en = 0;
	reg [7:0] addr = 0;
	reg [7:0] data_i = 0;
	wire [7:0] data_o;

	reg en_slv = 0;

	wire int;

	integer div;

	parameter PRESCALE_DIV = 15;


	always begin		
    		clk   = 1;
    		# HALF_CLOCK_PERIOD_50M;
    		clk   = 0;
    		# HALF_CLOCK_PERIOD_50M;
	end


	task WaitClock;
		begin
			@(posedge clk);
			#PERIOD;
			#PERIOD;
		end
	endtask

	task DivCalc;
		begin
			case (e[1:0])
	      		2'b00: div <= 4;
	      		2'b01: div <= 8;
	      		2'b10: div <= 16;
	      		2'b11: div <= 2*(PRESCALE_DIV+1);
	    	endcase
	    end
	endtask

	task write_reg; 
		input [7:0] sel_addr;
		input [7:0] data_w;
		begin
			@(posedge clk);
			addr   = sel_addr;
			data_i = data_w;
			wr_en  = 1'b1;

			-> write;
			@(posedge clk);
			wr_en  = 1'b0;
			if(sel_addr == `SPIBUFF) begin
				while (~int) @(posedge clk);
			end
			data_i = {8{1'bz}};
			addr   = {8{1'bz}};
			wr_en  = 1'b0;
		end		
	endtask	

	task read_reg; 
		input  [7:0] sel_addr;
		begin
			@(posedge clk);
			addr   = sel_addr;
			rd_en  = 1'b1;
			-> read;
			@(negedge clk);
			$display("Read data: %h",data_o);
			@(posedge clk);
			addr   = {8{1'bz}};
			rd_en  = 1'b0;
		end		
	endtask	

	task comp_reg;
		input [7:0] sel_addr; 
		input [7:0] d_exp;		
		begin
			@(posedge clk);
			addr   = sel_addr;
			rd_en  = 1'b1;
			-> compare;
			@(negedge clk);
			@(posedge clk);
			addr   = {8{1'bz}};
			rd_en  = 1'b0;

			-> acknow;
			if(d_exp != data_o) $display("Data compare error. Received %h, expected %h with clock divider: %d", data_o, d_exp, div);
			else $display("Data compare correct. Received %h, expected %h with clock divider: %d", data_o, d_exp, div);
			
		end
	endtask


	spi_master_top spi_top (
		.Clk 	 (clk),
		.Rst_n 	 (rstn),

		.Wr 	 (wr_en),
		.Rd 	 (rd_en),

		.Addr 	 (addr),
		.DataIn  (data_i),
		.DataOut (data_o),

		.SCLK 	 (sck),
		.MOSI	 (mosi),
		.MISO	 (miso),
		.SS 	 (ss),

		.Int 	 (int)
	);

	spi_slave_model_2 spi_slave (
		.clock  (clk),
		.csn 	(ss[0]),
		.sck 	(sck),
		.di 	(mosi),
		.do 	(miso),

		.cpol_i (test_spi_cpol  ),
		.cpha_i (test_spi_cpha  )
	);

	assign test_spi_cpol = spi_top.MSTR_CTRL.CPol;
	assign test_spi_cpha = spi_top.MSTR_CTRL.CPha;

	initial
	  begin
	      $display("\nStatus: Testbench started\n");


	      clk = 0;

	      rstn = 1'b1;
	      #5;
	      rstn = 1'b0;
	      repeat(1) @(posedge clk);
	      rstn = 1'b1;

	      $display("Reset Done");

	      @(posedge clk);

	      cpol = 0;
	      cpha = 0;





		for (cpha=0; cpha<=1; cpha=cpha+1) begin

	      	->change_cpha;
			#20;

		for (cpol=0; cpol<=1; cpol=cpol+1) begin
	      	->change_cpol;

		#20;
		
		$display("\n/////////////////////");
		$display("CPOL = %b   CPHA = %b", cpol[0], cpha[0]);
	      for (e=0; e<=3; e=e+1)
	      begin

	      	  DivCalc;



	          write_reg(`SPICTRL, {4'b1101,cpol[0],cpha[0],e[1:0]});


	          write_reg(`SPIPRE, PRESCALE_DIV);


	          write_reg(`SPISS, 8'h00);


	          for(n=0;n<8;n=n+1) begin


		          write_reg(`SPIBUFF, {cpol[0],cpha[0],e[1:0],n[3:0]});

		          -> check;
				  $display("Write data: %h",{cpol[0],cpha[0],e[1:0],n[3:0]});
				  
				  $displayh("MEM data: %p",spi_slave.mem);

		      end

		      for(n=0;n<8;n=n+1) begin


		          write_reg(`SPIBUFF, ~n);

		          comp_reg(`SPIBUFF,{cpol[0],cpha[0],e[1:0],n[3:0]});
	          end
	      end
		end
		end
	      #250000;
	      $display("\n\nStatus: Testbench done\n\n");
 	      $stop;
	  end

endmodule
module tb_spi();





	reg  clk;
	reg  rstn;

	reg [1:0] cpol, cpha;
	reg [2:0] e = 0;

	wire sck, mosi, miso;
	wire [7:0] ss;
	reg [7:0] q;

	wire test_spi_cpol;
	wire test_spi_cpha;


	parameter HALF_CLOCK_PERIOD_50M 	= 10;
	parameter HALF_CLOCK_PERIOD_10M 	= 50;
	parameter HALF_CLOCK_PERIOD_1M 		= 500;
	parameter HALF_CLOCK_PERIOD_100K 	= 5000;
	parameter PERIOD = 100;

	event read, write, compare, acknow, check, change_cpol, change_cpha;




	integer n;

	reg wr_en = 0;
	reg rd_en = 0;
	reg [7:0] addr = 0;
	reg [7:0] data_i = 0;
	wire [7:0] data_o;

	reg en_slv = 0;

	wire int;

	integer div;

	parameter PRESCALE_DIV = 15;


	always begin		
    		clk   = 1;
    		# HALF_CLOCK_PERIOD_50M;
    		clk   = 0;
    		# HALF_CLOCK_PERIOD_50M;
	end


	task WaitClock;
		begin
			@(posedge clk);
			#PERIOD;
			#PERIOD;
		end
	endtask

	task DivCalc;
		begin
			case (e[1:0])
	      		2'b00: div <= 4;
	      		2'b01: div <= 8;
	      		2'b10: div <= 16;
	      		2'b11: div <= 2*(PRESCALE_DIV+1);
	    	endcase
	    end
	endtask

	task write_reg; 
		input [7:0] sel_addr;
		input [7:0] data_w;
		begin
			@(posedge clk);
			addr   = sel_addr;
			data_i = data_w;
			wr_en  = 1'b1;

			-> write;
			@(posedge clk);
			wr_en  = 1'b0;
			if(sel_addr == `SPIBUFF) begin
				while (~int) @(posedge clk);
			end
			data_i = {8{1'bz}};
			addr   = {8{1'bz}};
			wr_en  = 1'b0;
		end		
	endtask	

	task read_reg; 
		input  [7:0] sel_addr;
		begin
			@(posedge clk);
			addr   = sel_addr;
			rd_en  = 1'b1;
			-> read;
			@(negedge clk);
			$display("Read data: %h",data_o);
			@(posedge clk);
			addr   = {8{1'bz}};
			rd_en  = 1'b0;
		end		
	endtask	

	task comp_reg;
		input [7:0] sel_addr; 
		input [7:0] d_exp;		
		begin
			@(posedge clk);
			addr   = sel_addr;
			rd_en  = 1'b1;
			-> compare;
			@(negedge clk);
			@(posedge clk);
			addr   = {8{1'bz}};
			rd_en  = 1'b0;

			-> acknow;
			if(d_exp != data_o) $display("Data compare error. Received %h, expected %h with clock divider: %d", data_o, d_exp, div);
			else $display("Data compare correct. Received %h, expected %h with clock divider: %d", data_o, d_exp, div);
			
		end
	endtask


	spi_master_top spi_top (
		.Clk 	 (clk),
		.Rst_n 	 (rstn),

		.Wr 	 (wr_en),
		.Rd 	 (rd_en),

		.Addr 	 (addr),
		.DataIn  (data_i),
		.DataOut (data_o),

		.SCLK 	 (sck),
		.MOSI	 (mosi),
		.MISO	 (miso),
		.SS 	 (ss),

		.Int 	 (int)
	);

	spi_slave_model_2 spi_slave (
		.clock  (clk),
		.csn 	(ss[0]),
		.sck 	(sck),
		.di 	(mosi),
		.do 	(miso),

		.cpol_i (test_spi_cpol  ),
		.cpha_i (test_spi_cpha  )
	);

	assign test_spi_cpol = spi_top.MSTR_CTRL.CPol;
	assign test_spi_cpha = spi_top.MSTR_CTRL.CPha;

	initial
	  begin
	      $display("\nStatus: Testbench started\n");


	      clk = 0;

	      rstn = 1'b1;
	      #5;
	      rstn = 1'b0;
	      repeat(1) @(posedge clk);
	      rstn = 1'b1;

	      $display("Reset Done");

	      @(posedge clk);

	      cpol = 0;
	      cpha = 0;





		for (cpha=0; cpha<=1; cpha=cpha+1) begin

	      	->change_cpha;
			#20;

		for (cpol=0; cpol<=1; cpol=cpol+1) begin
	      	->change_cpol;

		#20;
		
		$display("\n/////////////////////");
		$display("CPOL = %b   CPHA = %b", cpol[0], cpha[0]);
	      for (e=0; e<=3; e=e+1)
	      begin

	      	  DivCalc;



	          write_reg(`SPICTRL, {4'b1101,cpol[0],cpha[0],e[1:0]});


	          write_reg(`SPIPRE, PRESCALE_DIV);


	          write_reg(`SPISS, 8'h00);


	          for(n=0;n<8;n=n+1) begin


		          write_reg(`SPIBUFF, {cpol[0],cpha[0],e[1:0],n[3:0]});

		          -> check;
				  $display("Write data: %h",{cpol[0],cpha[0],e[1:0],n[3:0]});
				  
				  $displayh("MEM data: %p",spi_slave.mem);

		      end

		      for(n=0;n<8;n=n+1) begin


		          write_reg(`SPIBUFF, ~n);

		          comp_reg(`SPIBUFF,{cpol[0],cpha[0],e[1:0],n[3:0]});
	          end
	      end
		end
		end
	      #250000;
	      $display("\n\nStatus: Testbench done\n\n");
 	      $stop;
	  end

endmodule