data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module csa32_8( 
	input [31:0] 	a, b,
	input 			ci,
	output [31:0]	s,
	output			co
);
	wire 		co0, co1, co2, co3;
	wire [3:1] 	c0, c1;
	wire [7:0] 	s0[3:1], s1[3:1];
	wire		lo, hi; 

	sky130_fd_sc_hd__conb_1 TIE (.LO(lo), .HI(hi));

	rca #(8) A00  (.a(a[7:0]), .b(b[7:0]), .ci(ci), .co(co0), .s(s[7:0]) );
	
	rca #(8) A10  (.a(a[15:8]), .b(b[15:8]), .ci(lo), .co(c0[1]), .s(s0[1]) );
	rca #(8) A11  (.a(a[15:8]), .b(b[15:8]), .ci(hi), .co(c1[1]), .s(s1[1]) );
    assign s[15:8] = co0 ? s1[1] : s0[1];
    assign co1 = co0 ? c1[1] : c0[1];
	
	rca #(8) A20  (.a(a[23:16]), .b(b[23:16]), .ci(lo), .co(c0[2]), .s(s0[2]) );
	rca #(8) A21  (.a(a[23:16]), .b(b[23:16]), .ci(hi), .co(c1[2]), .s(s1[2]) );
    assign s[23:16] = co1 ? s1[2] : s0[2];
    assign co2 = co1 ? c1[2] : c0[2];

	rca #(8) A30  (.a(a[31:24]), .b(b[31:24]), .ci(lo), .co(c0[3]), .s(s0[3]) );
	rca #(8) A31  (.a(a[31:24]), .b(b[31:24]), .ci(hi), .co(c1[3]), .s(s1[3]) );
    assign s[31:24] = co2 ? s1[3] : s0[3];
    assign co = co2 ? c1[3] : c0[3];

endmodule
module csa32_8( 
	input [31:0] 	a, b,
	input 			ci,
	output [31:0]	s,
	output			co
);

	wire 		co0, co1, co2, co3;
	wire [3:1] 	c0, c1;
	wire [7:0] 	s0[3:1], s1[3:1];
	wire		lo, hi; 

	sky130_fd_sc_hd__conb_1 TIE (.LO(lo), .HI(hi));

	rca #(8) A00  (.a(a[7:0]), .b(b[7:0]), .ci(ci), .co(co0), .s(s[7:0]) );
	
	rca #(8) A10  (.a(a[15:8]), .b(b[15:8]), .ci(lo), .co(c0[1]), .s(s0[1]) );
	rca #(8) A11  (.a(a[15:8]), .b(b[15:8]), .ci(hi), .co(c1[1]), .s(s1[1]) );
    assign s[15:8] = co0 ? s1[1] : s0[1];
    assign co1 = co0 ? c1[1] : c0[1];
	
	rca #(8) A20  (.a(a[23:16]), .b(b[23:16]), .ci(lo), .co(c0[2]), .s(s0[2]) );
	rca #(8) A21  (.a(a[23:16]), .b(b[23:16]), .ci(hi), .co(c1[2]), .s(s1[2]) );
    assign s[23:16] = co1 ? s1[2] : s0[2];
    assign co2 = co1 ? c1[2] : c0[2];

	rca #(8) A30  (.a(a[31:24]), .b(b[31:24]), .ci(lo), .co(c0[3]), .s(s0[3]) );
	rca #(8) A31  (.a(a[31:24]), .b(b[31:24]), .ci(hi), .co(c1[3]), .s(s1[3]) );
    assign s[31:24] = co2 ? s1[3] : s0[3];
    assign co = co2 ? c1[3] : c0[3];

endmodule