data/full_repos/permissive/504550651/verilog/rtl/user_project_wrapper1.v
1: b"%Error: data/full_repos/permissive/504550651/verilog/rtl/user_project_wrapper1.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/user_project_wrapper1.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/user_project_wrapper1.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/user_project_wrapper1.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper1 #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);
    wire gpio_0_0;
    wire gpio_0_1;
    wire gpio_0_2;
    wire gpio_0_3;

    wire spi_0_dq_0;
    wire spi_0_dq_1;
    wire spi_0_dq_2;
    wire spi_0_dq_3;

    wire spi_1_dq_0;
    wire spi_1_dq_1;
    wire spi_1_dq_2;
    wire spi_1_dq_3;

    assign io_in[34]  = gpio_0_0;
    assign io_out[34] = gpio_0_0;
    assign io_in[35]  = gpio_0_1;
    assign io_out[35] = gpio_0_1;
    assign io_in[36]  = gpio_0_2;
    assign io_out[36] = gpio_0_2;
    assign io_in[37]  = gpio_0_3;
    assign io_out[37] = gpio_0_3;
    
    assign io_in[21]  = spi_0_dq_0;
    assign io_out[21] = spi_0_dq_0;
    assign io_in[22]  = spi_0_dq_1;
    assign io_out[22] = spi_0_dq_1;
    assign io_in[23]  = spi_0_dq_2;
    assign io_out[23] = spi_0_dq_2;
    assign io_in[24]  = spi_0_dq_3;
    assign io_out[24] = spi_0_dq_3;

    assign io_in[27]  = spi_1_dq_0;
    assign io_out[27] = spi_1_dq_0;
    assign io_in[28]  = spi_1_dq_1;
    assign io_out[28] = spi_1_dq_1;
    assign io_in[29]  = spi_1_dq_2;
    assign io_out[29] = spi_1_dq_2;
    assign io_in[30]  = spi_1_dq_3;
    assign io_out[30] = spi_1_dq_3;



ChipTop Inst_ChipTop (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
  .io_oeb(io_oeb),
  .jtag_TCK(io_in[15]),
  .jtag_TMS(io_in[16]),
  .jtag_TDI(io_in[17]),
  .jtag_TDO(io_out[18]),


  .serial_tl_clock(la_data_out[1]),
  .serial_tl_bits_in_ready(la_data_out[2]),
  .serial_tl_bits_in_valid(la_data_in[2]),
  .serial_tl_bits_in_bits(la_data_in[41:10]),
  .serial_tl_bits_out_ready(la_data_in[3]),
  .serial_tl_bits_out_valid(la_data_out[3]),
  .serial_tl_bits_out_bits(la_data_out[81:50]),

  .custom_boot(io_in[11]),
  .clock_clock(wb_clk_i),
  .reset(io_in[12]),

  .gpio_0_0(gpio_0_0),
  .gpio_0_1(gpio_0_1),
  .gpio_0_2(gpio_0_2),
  .gpio_0_3(gpio_0_3),


  .spi_0_sck(io_out[19]),
  .spi_0_cs_0(io_out[20]),
  .spi_0_dq_0(spi_0_dq_0),
  .spi_0_dq_1(spi_0_dq_1),
  .spi_0_dq_2(spi_0_dq_2),
  .spi_0_dq_3(spi_0_dq_3),


  .spi_1_sck(io_out[25]),
  .spi_1_cs_0(io_out[26]),
  .spi_1_dq_0(spi_1_dq_0),
  .spi_1_dq_1(spi_1_dq_1),
  .spi_1_dq_2(spi_1_dq_2),
  .spi_1_dq_3(spi_1_dq_3),

  .uart_0_txd(io_out[13]),
  .uart_0_rxd(io_in[14]),

  .uart_1_txd(io_out[32]),
  .uart_1_rxd(io_in[33])
);

`ifndef VERBOSE
  `define VERBOSE 0
`endif

endmodule
module user_project_wrapper1 #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);

    wire gpio_0_0;
    wire gpio_0_1;
    wire gpio_0_2;
    wire gpio_0_3;

    wire spi_0_dq_0;
    wire spi_0_dq_1;
    wire spi_0_dq_2;
    wire spi_0_dq_3;

    wire spi_1_dq_0;
    wire spi_1_dq_1;
    wire spi_1_dq_2;
    wire spi_1_dq_3;

    assign io_in[34]  = gpio_0_0;
    assign io_out[34] = gpio_0_0;
    assign io_in[35]  = gpio_0_1;
    assign io_out[35] = gpio_0_1;
    assign io_in[36]  = gpio_0_2;
    assign io_out[36] = gpio_0_2;
    assign io_in[37]  = gpio_0_3;
    assign io_out[37] = gpio_0_3;
    
    assign io_in[21]  = spi_0_dq_0;
    assign io_out[21] = spi_0_dq_0;
    assign io_in[22]  = spi_0_dq_1;
    assign io_out[22] = spi_0_dq_1;
    assign io_in[23]  = spi_0_dq_2;
    assign io_out[23] = spi_0_dq_2;
    assign io_in[24]  = spi_0_dq_3;
    assign io_out[24] = spi_0_dq_3;

    assign io_in[27]  = spi_1_dq_0;
    assign io_out[27] = spi_1_dq_0;
    assign io_in[28]  = spi_1_dq_1;
    assign io_out[28] = spi_1_dq_1;
    assign io_in[29]  = spi_1_dq_2;
    assign io_out[29] = spi_1_dq_2;
    assign io_in[30]  = spi_1_dq_3;
    assign io_out[30] = spi_1_dq_3;



ChipTop Inst_ChipTop (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
  .io_oeb(io_oeb),
  .jtag_TCK(io_in[15]),
  .jtag_TMS(io_in[16]),
  .jtag_TDI(io_in[17]),
  .jtag_TDO(io_out[18]),


  .serial_tl_clock(la_data_out[1]),
  .serial_tl_bits_in_ready(la_data_out[2]),
  .serial_tl_bits_in_valid(la_data_in[2]),
  .serial_tl_bits_in_bits(la_data_in[41:10]),
  .serial_tl_bits_out_ready(la_data_in[3]),
  .serial_tl_bits_out_valid(la_data_out[3]),
  .serial_tl_bits_out_bits(la_data_out[81:50]),

  .custom_boot(io_in[11]),
  .clock_clock(wb_clk_i),
  .reset(io_in[12]),

  .gpio_0_0(gpio_0_0),
  .gpio_0_1(gpio_0_1),
  .gpio_0_2(gpio_0_2),
  .gpio_0_3(gpio_0_3),


  .spi_0_sck(io_out[19]),
  .spi_0_cs_0(io_out[20]),
  .spi_0_dq_0(spi_0_dq_0),
  .spi_0_dq_1(spi_0_dq_1),
  .spi_0_dq_2(spi_0_dq_2),
  .spi_0_dq_3(spi_0_dq_3),


  .spi_1_sck(io_out[25]),
  .spi_1_cs_0(io_out[26]),
  .spi_1_dq_0(spi_1_dq_0),
  .spi_1_dq_1(spi_1_dq_1),
  .spi_1_dq_2(spi_1_dq_2),
  .spi_1_dq_3(spi_1_dq_3),

  .uart_0_txd(io_out[13]),
  .uart_0_rxd(io_in[14]),

  .uart_1_txd(io_out[32]),
  .uart_1_rxd(io_in[33])
);

`ifndef VERBOSE
  `define VERBOSE 0
`endif

endmodule