data/full_repos/permissive/505761772/code/ModemCore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/ModemCore.v:204: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'DEMODULATOR\'\nmodule DEMODULATOR  ( input             CLK,\n       ^~~~~~~~~~~\n                                                                            : ... Top module \'NCO\'\nmodule NCO( input CLK,\n       ^~~\n                                                                            : ... Top module \'DESERIALIZER\'\nmodule DESERIALIZER(  input CLK,\n       ^~~~~~~~~~~~\n                                                                            : ... Top module \'SERIALIZER\'\nmodule SERIALIZER(  input       CLK,\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:34: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 36 bits.\n                                                                        : ... In instance DEMODULATOR.MULT8\nassign P = (P36>>>17);\n         ^\n%Error: data/full_repos/permissive/505761772/code/ModemCore.v:35: Cannot find file containing module: \'MULT18X18\'\nMULT18X18 mult ( .P(P36),\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.v\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.sv\n             MULT18X18\n             MULT18X18.v\n             MULT18X18.sv\n             obj_dir/MULT18X18\n             obj_dir/MULT18X18.v\n             obj_dir/MULT18X18.sv\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:10: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h1d000\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] X = 17\'h1D000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:11: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] Y = 17\'h00000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:192: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                         : ... In instance DEMODULATOR\n    if(cnt == 4\'h1)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:240: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'he800\' generates 17 bits.\n                                                                         : ... In instance NCO\n      X <= 17\'h0E800;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:241: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                         : ... In instance NCO\n      Y <= 17\'h00000;\n        ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module NCO( input CLK,
            input DET,
            input DATA,
            output signed [17:0] S);

reg DATA_old;

initial begin
  DATA_old  = DATA;
end

parameter n_bits = 12;


parameter k1 = 8;
parameter Ac1 = 8;


parameter k2 = 26;
parameter Ac2 = 4;

reg signed [17:0] X;
reg signed [17:0] Y;

wire signed [17:0] X1;
assign X1 = X - (( (DATA ? k2 : k1) * X) >>> n_bits) + Y;

always @(negedge CLK) begin
  if( (DATA != DATA_old)) begin
    DATA_old <= DATA;
    Y <= (DATA ? (Y*29)>>>4 : (Y*9)>>>4);
  end else begin
    if(DET) begin
      Y <= X1 - (( (DATA ? k2 : k1) * X1 ) >>> n_bits ) - X;
      X <= X1;
    end else begin
      X <= 17'h0E800;
      Y <= 17'h00000;
    end
  end
end

assign S = Y * (DATA ? Ac2 : Ac1);

endmodule
module NCO( input CLK,
            input DET,
            input DATA,
            output signed [17:0] S);


reg DATA_old;

initial begin
  DATA_old  = DATA;
end

parameter n_bits = 12;


parameter k1 = 8;
parameter Ac1 = 8;


parameter k2 = 26;
parameter Ac2 = 4;

reg signed [17:0] X;
reg signed [17:0] Y;

wire signed [17:0] X1;
assign X1 = X - (( (DATA ? k2 : k1) * X) >>> n_bits) + Y;

always @(negedge CLK) begin
  if( (DATA != DATA_old)) begin
    DATA_old <= DATA;
    Y <= (DATA ? (Y*29)>>>4 : (Y*9)>>>4);
  end else begin
    if(DET) begin
      Y <= X1 - (( (DATA ? k2 : k1) * X1 ) >>> n_bits ) - X;
      X <= X1;
    end else begin
      X <= 17'h0E800;
      Y <= 17'h00000;
    end
  end
end

assign S = Y * (DATA ? Ac2 : Ac1);

endmodule