data/full_repos/permissive/505451992/Encoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:50: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                 : ... In instance encoder\n            current_state <= Error; \n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:63: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'Min\' generates 11 bits.\n                                                                 : ... In instance encoder\n         current_P <= Min;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:56: Operator LTS expects 11 bits on the LHS, but LHS\'s VARREF \'current_P\' generates 10 bits.\n                                                                 : ... In instance encoder\n       if(current_P < Max ) \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:77: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'Max\' generates 11 bits.\n                                                                 : ... In instance encoder\n          current_P <= Max;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:70: Operator GTS expects 11 bits on the LHS, but LHS\'s VARREF \'current_P\' generates 10 bits.\n                                                                 : ... In instance encoder\n          if(current_P > Min ) \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:67: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                 : ... In instance encoder\n    else if (next_state == S4  && current_state == S1 )\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:67: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                 : ... In instance encoder\n    else if (next_state == S4  && current_state == S1 )\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:53: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                 : ... In instance encoder\n      if( next_state == S1  && current_state == S4 ) \n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:53: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                 : ... In instance encoder\n      if( next_state == S1  && current_state == S4 ) \n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:107: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                next_state = S2 ;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:112: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                 next_state = S4 ;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:116: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                  : ... In instance encoder\n                            next_state = S1 ;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:120: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 4 bits.\n                                                                  : ... In instance encoder\n                            next_state = S3;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:124: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                  : ... In instance encoder\n                        next_state =  Error;                          \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:134: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                       next_state = S1;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:138: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                           next_state = S2;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:144: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                            next_state = S4;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:149: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                   next_state =  Error;                          \n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:156: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                             next_state = S2;\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:160: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                               next_state = S3;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:164: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                               next_state = S1;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:167: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                     next_state =  Error;                          \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:174: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                       next_state = S3;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:178: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                       next_state = S4;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:182: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                       next_state = S2;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:187: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                        next_state =  Error;                          \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:197: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                                         next_state = S1;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:204: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                                         next_state = S4;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:208: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                                         next_state = S3;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:212: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'Error\' generates 4 bits.\n                                                                  : ... In instance encoder\n                                                          next_state =  Error;                          \n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:98: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'Error\' generates 4 bits.\n                                                                 : ... In instance encoder\n   case(current_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:98: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'S1\' generates 4 bits.\n                                                                 : ... In instance encoder\n   case(current_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:98: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'S2\' generates 4 bits.\n                                                                 : ... In instance encoder\n   case(current_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:98: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'S3\' generates 4 bits.\n                                                                 : ... In instance encoder\n   case(current_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/Encoder.v:98: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'S4\' generates 4 bits.\n                                                                 : ... In instance encoder\n   case(current_state)\n   ^~~~\n%Error: Exiting due to 35 warning(s)\n'
module encoder(
input reset,
input clk,
input A,
input B,
input[9:0] PPR,
output signed [9:0] P
    );
    
    wire [10:0] PPR_1;
    wire signed [10:0] Max;
    wire signed [10:0] Min;
 
  
  
  reg signed [9:0] current_P;
  reg signed [9:0] next_P;
  reg [4:0] current_state;
  reg [4:0] next_state;
  wire signed  [10:0] lim1;
  wire signed [10:0] lim2;


  
   
   parameter Error= 4'h0;
   parameter S1= 4'h1;
   parameter S2= 4'h2;
   parameter S3 = 4'h3;
   parameter S4 = 4'h4;

   
   
    assign PPR_1 = PPR + 1;
    assign Max = (PPR_1/2)-1; 
    assign Min = ((-PPR_1)/2); 


    

   


  always@(posedge clk or posedge reset) begin 
        if (reset)
            begin
            current_P <= 0;
            current_state <= Error; 
            end
        else begin
			   if( next_state == S1  && current_state == S4 )	
					begin 

					  if(current_P < Max ) 
							begin 
							  current_P <= current_P + 1'b1;
							  
							end
						else 
							begin
							  current_P <= Min;
							end	
								
				    end
				else if (next_state == S4  && current_state == S1 )
					begin

					     if(current_P > Min ) 
							 begin 
							  current_P <= current_P - 1'b1;

						     end
						else 
							 begin
							   current_P <= Max;

						     end	
					end	
					
				else 
					begin
				       current_P <= current_P;
				
				   end
					 
					 
              current_state <= next_state;
       
          end
	
end	
   
      
  always@(current_state or A or B) begin   

   case(current_state)

     Error: 
                begin



                     if (A==1 && B==0)
                            begin
                                next_state = S2 ;
							
                            end        
                     else if (A==0 && B==1)
                             begin
                                 next_state = S4 ;
                             end
                  else  if (A==0 && B==0)
                        begin
                            next_state = S1 ;
                        end	
                  else  if (A==1 && B==1)
                        begin
                            next_state = S3;
                        end		
						
                     else
                        next_state =  Error;                          
                end
          
		  
		
     S1: 
                           begin
							   
                               if (A==0 && B==0)
                                   begin
                                       next_state = S1;
                                   end
                               else if (A==1 && B==0)
                                       begin
                                           next_state = S2;

										   
                                       end        
                                else if (A==0 && B==1)
                                        begin
                                            next_state = S4;


                                        end              
                                else
                                   next_state =  Error;                          
                           end
                           
     S2: 
                               begin
                                  if (A==1 && B==0)
                                         begin
                                             next_state = S2;
                                          end
                                  else if (A==1 && B==1)
                                          begin
                                               next_state = S3;
                                           end        
                                  else if (A==0 && B==0)
                                           begin
                                               next_state = S1;
                                            end              
                                  else
                                     next_state =  Error;                          
                                end                           
                              
      S3: 
                 begin
                            if (A== 1 && B==1)
                                 begin
                                       next_state = S3;
                                  end
                            else if (A==0 && B==1)
                                     begin
                                       next_state = S4;
                                     end        
                            else if (A==1 && B==0)
                                      begin
                                       next_state = S2;
                                       
                                    
                                      end              
                              else
                                        next_state =  Error;                          
                        end              
		

                                    
       S4: 
                                   begin   
									  
                                              if (A==0 && B==0)
                                                   begin
                                                         next_state = S1;


														 
                                                    end
                                              else if (A==0 && B==1)
                                                       begin
                                                         next_state = S4;
                                                       end        
                                              else if (A==1 && B==1)
                                                        begin
                                                         next_state = S3;

                                                        end              
                                                else
                                                          next_state =  Error;                          
                                          end                                                  
                                    
              
                                                                              
   endcase                                                                                                         
      
                                                                                     
  
  end      


 
        
 
  
    assign P = current_P;



	
	endmodule
module encoder(
input reset,
input clk,
input A,
input B,
input[9:0] PPR,
output signed [9:0] P
    );

    
    wire [10:0] PPR_1;
    wire signed [10:0] Max;
    wire signed [10:0] Min;
 
  
  
  reg signed [9:0] current_P;
  reg signed [9:0] next_P;
  reg [4:0] current_state;
  reg [4:0] next_state;
  wire signed  [10:0] lim1;
  wire signed [10:0] lim2;


  
   
   parameter Error= 4'h0;
   parameter S1= 4'h1;
   parameter S2= 4'h2;
   parameter S3 = 4'h3;
   parameter S4 = 4'h4;

   
   
    assign PPR_1 = PPR + 1;
    assign Max = (PPR_1/2)-1; 
    assign Min = ((-PPR_1)/2); 


    

   


  always@(posedge clk or posedge reset) begin 
        if (reset)
            begin
            current_P <= 0;
            current_state <= Error; 
            end
        else begin
			   if( next_state == S1  && current_state == S4 )	
					begin 

					  if(current_P < Max ) 
							begin 
							  current_P <= current_P + 1'b1;
							  
							end
						else 
							begin
							  current_P <= Min;
							end	
								
				    end
				else if (next_state == S4  && current_state == S1 )
					begin

					     if(current_P > Min ) 
							 begin 
							  current_P <= current_P - 1'b1;

						     end
						else 
							 begin
							   current_P <= Max;

						     end	
					end	
					
				else 
					begin
				       current_P <= current_P;
				
				   end
					 
					 
              current_state <= next_state;
       
          end
	
end	
   
      
  always@(current_state or A or B) begin   

   case(current_state)

     Error: 
                begin



                     if (A==1 && B==0)
                            begin
                                next_state = S2 ;
							
                            end        
                     else if (A==0 && B==1)
                             begin
                                 next_state = S4 ;
                             end
                  else  if (A==0 && B==0)
                        begin
                            next_state = S1 ;
                        end	
                  else  if (A==1 && B==1)
                        begin
                            next_state = S3;
                        end		
						
                     else
                        next_state =  Error;                          
                end
          
		  
		
     S1: 
                           begin
							   
                               if (A==0 && B==0)
                                   begin
                                       next_state = S1;
                                   end
                               else if (A==1 && B==0)
                                       begin
                                           next_state = S2;

										   
                                       end        
                                else if (A==0 && B==1)
                                        begin
                                            next_state = S4;


                                        end              
                                else
                                   next_state =  Error;                          
                           end
                           
     S2: 
                               begin
                                  if (A==1 && B==0)
                                         begin
                                             next_state = S2;
                                          end
                                  else if (A==1 && B==1)
                                          begin
                                               next_state = S3;
                                           end        
                                  else if (A==0 && B==0)
                                           begin
                                               next_state = S1;
                                            end              
                                  else
                                     next_state =  Error;                          
                                end                           
                              
      S3: 
                 begin
                            if (A== 1 && B==1)
                                 begin
                                       next_state = S3;
                                  end
                            else if (A==0 && B==1)
                                     begin
                                       next_state = S4;
                                     end        
                            else if (A==1 && B==0)
                                      begin
                                       next_state = S2;
                                       
                                    
                                      end              
                              else
                                        next_state =  Error;                          
                        end              
		

                                    
       S4: 
                                   begin   
									  
                                              if (A==0 && B==0)
                                                   begin
                                                         next_state = S1;


														 
                                                    end
                                              else if (A==0 && B==1)
                                                       begin
                                                         next_state = S4;
                                                       end        
                                              else if (A==1 && B==1)
                                                        begin
                                                         next_state = S3;

                                                        end              
                                                else
                                                          next_state =  Error;                          
                                          end                                                  
                                    
              
                                                                              
   endcase                                                                                                         
      
                                                                                     
  
  end      


 
        
 
  
    assign P = current_P;



	
	endmodule