data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk200 = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:17: Unsupported: Ignoring delay on this delayed statement.\n    #2.5 clk200 = ~clk200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:23: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk33 = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n    #15.151 clk33 = ~clk33;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:30: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:32: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:35: Unsupported: Ignoring delay on this delayed statement.\n    #9985 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:45: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst_once = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst_once = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:47: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst_once = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:84: Unsupported: Ignoring delay on this delayed statement.\n  #0 start = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:85: Unsupported: Ignoring delay on this delayed statement.\n  #100 start = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:86: Unsupported: Ignoring delay on this delayed statement.\n  #20 start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:112: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n) checker (\n  ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/prbs_gen_chk_tb.sv:113: syntax error, unexpected \'(\', expecting IDENTIFIER\n  .clk( clk200 ),\n  ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module prbs_gen_chk_tb();

logic clk200;
initial begin
  #0 clk200 = 1'b0;
  forever
    #2.5 clk200 = ~clk200;
end


logic clk33;
initial begin
  #0 clk33 = 1'b0;
  forever
    #15.151 clk33 = ~clk33;
end

logic rst;
initial begin
  #0 rst = 1'b0;
  #10.2 rst = 1'b1;
  #5 rst = 1'b0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #0 rst_once = 1'b0;
  #10.2 rst_once = 1'b1;
  #5 rst_once = 1'b0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .ena( 1'b1 ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
edge_detect ed1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand rng1 (
  .clk( clk200 ),
  .rst( rst_once ),
  .reseed( 1'b0 ),
  .seed_val( DerivedClocks[31:0] ),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100 start = 1'b1;
  #20 start = 1'b0;
end



logic [31:0] d1;
prbs_gen_chk #(
  .WIDTH( 32 ),
  .CHK_MODE( 0 ),
  .INV_PATTERN( 1 ),
  .POLY_LEN( 31 ),
  .POLY_TAP( 28 )
) gen (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .en( 1'b1 ),
  .data_in( {2{RandomNumber1[15:0]}} ),
  .data_out( d1[31:0] )
);

prbs_gen_chk #(
  .WIDTH( 32 ),
  .CHK_MODE( 1 ),
  .INV_PATTERN( 1 ),
  .POLY_LEN( 31 ),
  .POLY_TAP( 28 )
) checker (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .en( 1'b1 ),
  .data_in( d1[31:0] ),
  .data_out(  )
);


endmodule
module prbs_gen_chk_tb();


logic clk200;
initial begin
  #0 clk200 = 1'b0;
  forever
    #2.5 clk200 = ~clk200;
end


logic clk33;
initial begin
  #0 clk33 = 1'b0;
  forever
    #15.151 clk33 = ~clk33;
end

logic rst;
initial begin
  #0 rst = 1'b0;
  #10.2 rst = 1'b1;
  #5 rst = 1'b0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #0 rst_once = 1'b0;
  #10.2 rst_once = 1'b1;
  #5 rst_once = 1'b0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .ena( 1'b1 ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
edge_detect ed1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand rng1 (
  .clk( clk200 ),
  .rst( rst_once ),
  .reseed( 1'b0 ),
  .seed_val( DerivedClocks[31:0] ),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100 start = 1'b1;
  #20 start = 1'b0;
end



logic [31:0] d1;
prbs_gen_chk #(
  .WIDTH( 32 ),
  .CHK_MODE( 0 ),
  .INV_PATTERN( 1 ),
  .POLY_LEN( 31 ),
  .POLY_TAP( 28 )
) gen (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .en( 1'b1 ),
  .data_in( {2{RandomNumber1[15:0]}} ),
  .data_out( d1[31:0] )
);

prbs_gen_chk #(
  .WIDTH( 32 ),
  .CHK_MODE( 1 ),
  .INV_PATTERN( 1 ),
  .POLY_LEN( 31 ),
  .POLY_TAP( 28 )
) checker (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .en( 1'b1 ),
  .data_in( d1[31:0] ),
  .data_out(  )
);


endmodule