data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/pulp_sync_wedge.sv
1: b"%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/pulp_sync_wedge.sv:31: Cannot find file containing module: 'pulp_sync'\n    pulp_sync #(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/pulp_sync\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/pulp_sync.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/pulp_sync.sv\n             pulp_sync\n             pulp_sync.v\n             pulp_sync.sv\n             obj_dir/pulp_sync\n             obj_dir/pulp_sync.v\n             obj_dir/pulp_sync.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/pulp_sync_wedge.sv:40: Cannot find file containing module: 'pulp_clock_gating'\n    pulp_clock_gating i_pulp_clock_gating (\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module pulp_sync_wedge #(
    parameter int unsigned STAGES = 2
) (
    input  logic clk_i,
    input  logic rstn_i,
    input  logic en_i,
    input  logic serial_i,
    output logic r_edge_o,
    output logic f_edge_o,
    output logic serial_o
);
    logic clk;
    logic serial, serial_q;

    assign serial_o =  serial_q;
    assign f_edge_o = ~serial &  serial_q;
    assign r_edge_o =  serial & ~serial_q;

    pulp_sync #(
        .STAGES(STAGES)
    ) i_pulp_sync (
        .clk_i,
        .rstn_i,
        .serial_i,
        .serial_o ( serial )
    );

    pulp_clock_gating i_pulp_clock_gating (
        .clk_i,
        .en_i,
        .test_en_i ( 1'b0    ),
        .clk_o     ( clk )
    );

    always_ff @(posedge clk, negedge rstn_i) begin
        if (!rstn_i) begin
            serial_q <= 1'b0;
        end else begin
            serial_q <= serial;
        end
    end

endmodule
module pulp_sync_wedge #(
    parameter int unsigned STAGES = 2
) (
    input  logic clk_i,
    input  logic rstn_i,
    input  logic en_i,
    input  logic serial_i,
    output logic r_edge_o,
    output logic f_edge_o,
    output logic serial_o
);

    logic clk;
    logic serial, serial_q;

    assign serial_o =  serial_q;
    assign f_edge_o = ~serial &  serial_q;
    assign r_edge_o =  serial & ~serial_q;

    pulp_sync #(
        .STAGES(STAGES)
    ) i_pulp_sync (
        .clk_i,
        .rstn_i,
        .serial_i,
        .serial_o ( serial )
    );

    pulp_clock_gating i_pulp_clock_gating (
        .clk_i,
        .en_i,
        .test_en_i ( 1'b0    ),
        .clk_o     ( clk )
    );

    always_ff @(posedge clk, negedge rstn_i) begin
        if (!rstn_i) begin
            serial_q <= 1'b0;
        end else begin
            serial_q <= serial;
        end
    end

endmodule