data/full_repos/permissive/46343463/src/HazardDetectionUnit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46343463/src/HazardDetectionUnit.v:13: Unsupported: Ignoring delay on this delayed statement.\n   #(10)\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module HazardDetectionUnit
(
	input		[4:0]	IFID_Rs_i,
	input		[4:0]	IFID_Rt_i,
	input 		[4:0]	IDEX_Rt_i,
	input				IDEX_Mem_cs,
	output reg 			stall
);

	always @ (*) begin
		if(IDEX_Mem_cs && ((IDEX_Rt_i == IFID_Rs_i) || (IDEX_Rt_i == IFID_Rt_i))) begin
			stall = 1'b1;
			#(10)
			stall = 1'b0;
		end
		else
			stall = 1'b0;
	end
	


endmodule
module HazardDetectionUnit
(
	input		[4:0]	IFID_Rs_i,
	input		[4:0]	IFID_Rt_i,
	input 		[4:0]	IDEX_Rt_i,
	input				IDEX_Mem_cs,
	output reg 			stall
);


	always @ (*) begin
		if(IDEX_Mem_cs && ((IDEX_Rt_i == IFID_Rs_i) || (IDEX_Rt_i == IFID_Rt_i))) begin
			stall = 1'b1;
			#(10)
			stall = 1'b0;
		end
		else
			stall = 1'b0;
	end
	


endmodule