data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #40 sys_clk_i <= ~sys_clk_i;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:70: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:71: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:76: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:77: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:79: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:80: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:81: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:87: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:93: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:109: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:115: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:122: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 0; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:130: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:137: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:141: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:148: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:152: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:159: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 0; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:163: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:170: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 0; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:175: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:182: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 0; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:187: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:194: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:199: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:206: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:210: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:211: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:218: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 0; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:223: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:230: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:235: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:242: Unsupported: wait statements\n  wait(sys_clk_i);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_d_i = 1; ps2_c_i = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:245: Unsupported: Ignoring delay on this delayed statement.\n  #50000  ps2_c_i = 1;\n  ^\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:246: Unsupported: wait statements\n  wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:247: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:247: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:248: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:248: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:249: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:249: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:250: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:250: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:251: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:251: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:252: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:252: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:253: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:253: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:254: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:254: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n                   ^~~~\n%Error: data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/T_uxa_ps2.v:255: Unsupported: wait statements\n  wait(sys_clk_i); wait(~sys_clk_i);\n  ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module T_uxa_ps2;


	reg ps2_d_i;
	reg ps2_c_i;
	reg sys_clk_i;
	reg sys_reset_i;
	reg io_stb_i;
	reg io_we_i;
	reg [9:8] io_dat_i;


	wire ps2_c_oe_o;
	wire ps2_d_oe_o;
	wire io_ack_o;
	wire [15:0] io_dat_o;


	M_uxa_ps2 uut (
		.ps2_c_oe_o(ps2_c_oe_o), 
		.ps2_d_oe_o(ps2_d_oe_o), 
		.ps2_d_i(ps2_d_i), 
		.ps2_c_i(ps2_c_i), 
		.sys_clk_i(sys_clk_i), 
		.sys_reset_i(sys_reset_i), 
		.io_ack_o(io_ack_o), 
		.io_stb_i(io_stb_i), 
		.io_we_i(io_we_i), 
		.io_dat_i(io_dat_i), 
		.io_dat_o(io_dat_o)
	);

	always begin
		#40 sys_clk_i <= ~sys_clk_i;
	end

	initial begin

		ps2_d_i <= 1;
		ps2_c_i <= 1;
		sys_clk_i <= 0;
		sys_reset_i <= 0;
		io_stb_i <= 0;
		io_we_i <= 0;
		io_dat_i <= 2'b11;
		wait(~sys_clk_i);
		wait(sys_clk_i);



		sys_reset_i <= 1;
		wait(~sys_clk_i);
		wait(sys_clk_i);
		sys_reset_i <= 0;
		wait(~sys_clk_i);
		wait(sys_clk_i);
		wait(~sys_clk_i);
		
		if (io_ack_o != 0) begin
			$display("Bus expected to be idle."); $stop;
		end
		
		wait(sys_clk_i);




		io_stb_i <= 1;  io_we_i <= 0;
		wait(~sys_clk_i);
		if (io_ack_o != 1) begin
			$display("Single-cycle response time expected when reading"); $stop;
		end
		if (io_dat_o[13] != 0) begin
			$display("When reading, bit 13 of the register should always be zero."); $stop;
		end
		if (io_dat_o[12] != 0) begin
			$display("When reading, bit 12 of the register should always be zero."); $stop;
		end
		if (io_dat_o[11] != 0) begin
			$display("When reading, bit 11 of the register should always be zero."); $stop;
		end
		if (io_dat_o[10] != 0) begin
			$display("When reading, bit 10 of the register should always be zero."); $stop;
		end
		wait(sys_clk_i);





		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("Nothing pushed into the queue yet; expected no data available."); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("Nothing pushed into the queue yet; how can it be full?"); $stop;
		end
		wait(sys_clk_i);
		




		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending start bit, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending start bit, F should be clear"); $stop;
		end
		wait(sys_clk_i);

		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 0, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 0, F should be clear"); $stop;
		end
		wait(sys_clk_i);
	
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 1, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 1, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 2, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 2, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 3, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 3, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 4, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 4, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 5, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 5, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 6, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 6, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 7, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 7, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending parity, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending parity, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		if (io_dat_o[15] != 1) begin
			$display("After sending stop bit, V should be set"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending stop bit, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
	end


endmodule
module T_uxa_ps2;



	reg ps2_d_i;
	reg ps2_c_i;
	reg sys_clk_i;
	reg sys_reset_i;
	reg io_stb_i;
	reg io_we_i;
	reg [9:8] io_dat_i;


	wire ps2_c_oe_o;
	wire ps2_d_oe_o;
	wire io_ack_o;
	wire [15:0] io_dat_o;


	M_uxa_ps2 uut (
		.ps2_c_oe_o(ps2_c_oe_o), 
		.ps2_d_oe_o(ps2_d_oe_o), 
		.ps2_d_i(ps2_d_i), 
		.ps2_c_i(ps2_c_i), 
		.sys_clk_i(sys_clk_i), 
		.sys_reset_i(sys_reset_i), 
		.io_ack_o(io_ack_o), 
		.io_stb_i(io_stb_i), 
		.io_we_i(io_we_i), 
		.io_dat_i(io_dat_i), 
		.io_dat_o(io_dat_o)
	);

	always begin
		#40 sys_clk_i <= ~sys_clk_i;
	end

	initial begin

		ps2_d_i <= 1;
		ps2_c_i <= 1;
		sys_clk_i <= 0;
		sys_reset_i <= 0;
		io_stb_i <= 0;
		io_we_i <= 0;
		io_dat_i <= 2'b11;
		wait(~sys_clk_i);
		wait(sys_clk_i);



		sys_reset_i <= 1;
		wait(~sys_clk_i);
		wait(sys_clk_i);
		sys_reset_i <= 0;
		wait(~sys_clk_i);
		wait(sys_clk_i);
		wait(~sys_clk_i);
		
		if (io_ack_o != 0) begin
			$display("Bus expected to be idle."); $stop;
		end
		
		wait(sys_clk_i);




		io_stb_i <= 1;  io_we_i <= 0;
		wait(~sys_clk_i);
		if (io_ack_o != 1) begin
			$display("Single-cycle response time expected when reading"); $stop;
		end
		if (io_dat_o[13] != 0) begin
			$display("When reading, bit 13 of the register should always be zero."); $stop;
		end
		if (io_dat_o[12] != 0) begin
			$display("When reading, bit 12 of the register should always be zero."); $stop;
		end
		if (io_dat_o[11] != 0) begin
			$display("When reading, bit 11 of the register should always be zero."); $stop;
		end
		if (io_dat_o[10] != 0) begin
			$display("When reading, bit 10 of the register should always be zero."); $stop;
		end
		wait(sys_clk_i);





		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("Nothing pushed into the queue yet; expected no data available."); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("Nothing pushed into the queue yet; how can it be full?"); $stop;
		end
		wait(sys_clk_i);
		




		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending start bit, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending start bit, F should be clear"); $stop;
		end
		wait(sys_clk_i);

		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 0, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 0, F should be clear"); $stop;
		end
		wait(sys_clk_i);
	
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 1, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 1, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 2, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 2, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 3, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 3, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 4, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 4, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 5, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 5, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 6, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 6, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 0; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending bit 7, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending bit 7, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		if (io_dat_o[15] != 0) begin
			$display("After sending parity, V should be clear"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending parity, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
		#50000  ps2_d_i = 1; ps2_c_i = 0;
		#50000  ps2_c_i = 1;
		wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		wait(sys_clk_i); wait(~sys_clk_i);
		if (io_dat_o[15] != 1) begin
			$display("After sending stop bit, V should be set"); $stop;
		end
		if (io_dat_o[14] != 0) begin
			$display("After sending stop bit, F should be clear"); $stop;
		end
		wait(sys_clk_i);
		
	end


endmodule