data/full_repos/permissive/515646879/Behavioral.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #5 A=4\'b1110;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #5 B=4\'b1101;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #5 A=4\'b1110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #5 B=4\'b1111;\n      ^\n%Error: data/full_repos/permissive/515646879/Behavioral.v:34: Unsupported or unknown PLI call: $monitor\n       $monitor("time=%t,A=%b,B=%b,Y=%b",$time,A,B,Y);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Behavioral.v:35: Unsupported: Ignoring delay on this delayed statement.\n         #80 $finish;\n         ^\n%Error: data/full_repos/permissive/515646879/Behavioral.v:38: Unsupported or unknown PLI call: $dumpfile\n         $dumpfile("multiplier4bit.vcd");\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/515646879/Behavioral.v:39: Unsupported or unknown PLI call: $dumpvars\n         $dumpvars(0,multiplier4bit_tb);\n         ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier4bit(A,B,Y);
    input [3:0]A,B;
    output [7:0]Y;
  
  integer i=0;
  
  always @(A or B)
    begin
      Y=0;
      for(i=0;i<4;i++)
        begin 
          if(B[i]==1)
            Y=Y+(A<<i);
          else
            Y=Y;
        end
    end 
endmodule
module multiplier4bit(A,B,Y);

    input [3:0]A,B;
    output [7:0]Y;
  
  integer i=0;
  
  always @(A or B)
    begin
      Y=0;
      for(i=0;i<4;i++)
        begin 
          if(B[i]==1)
            Y=Y+(A<<i);
          else
            Y=Y;
        end
    end 
endmodule