data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module branch_compare #(parameter data_width = 32)(
    input [data_width-1:0] Rdata1,
    input [data_width-1:0] Rdata2,
    input Branch,
    input [2:0] funct3,
    output reg en
);
    initial begin en = 0; end
    always @(*) begin
        if (Branch == 0) begin en <= 0; end
        else begin
            case (funct3)
                3'b000: en <= (Rdata1 == Rdata2)? 1:0;
                3'b001: en <= (Rdata1 == Rdata2)? 0:1;
                3'b100: en <= (Rdata1 < Rdata2)? 1:0;
                3'b101: en <= (Rdata1 < Rdata2)? 0:1;
            endcase
        end
    end
endmodule
module branch_compare #(parameter data_width = 32)(
    input [data_width-1:0] Rdata1,
    input [data_width-1:0] Rdata2,
    input Branch,
    input [2:0] funct3,
    output reg en
);

    initial begin en = 0; end
    always @(*) begin
        if (Branch == 0) begin en <= 0; end
        else begin
            case (funct3)
                3'b000: en <= (Rdata1 == Rdata2)? 1:0;
                3'b001: en <= (Rdata1 == Rdata2)? 0:1;
                3'b100: en <= (Rdata1 < Rdata2)? 1:0;
                3'b101: en <= (Rdata1 < Rdata2)? 0:1;
            endcase
        end
    end
endmodule