data/full_repos/permissive/46132596/processor/SingleCycleDatapath/DataMemory.v
data/verilator_xmls/75c83425-1305-4efc-9f65-630a1d2b6350.xml
module DataMemory(input clock,
		input clear,
		input[31:0] address,
		input write,
		input[31:0] write_data,
		output[31:0] read_data);


	reg[31:0] content[255:0];
	integer i;
	
	always @(posedge clear, negedge clock)
		if (clear) begin


			for (i = 0; i < 256; i = i + 1)
				content[i] = 0;




			content[0] = 100;
			content[1] = 200;

		end else if (write
				&& address >= 32'h10010000
				&& address < 32'h10014000)
		begin



			content[(address - 32'h10001000) >> 2] = write_data;
			$display("\tM[%x] = %x (hex)", address, write_data);
		end


	assign read_data = address >= 32'h10010000
			&& address < 32'h10014000 ?
			content[(address - 32'h10010000) >> 2] : 0;
	
endmodule
module DataMemory(input clock,
		input clear,
		input[31:0] address,
		input write,
		input[31:0] write_data,
		output[31:0] read_data);



	reg[31:0] content[255:0];
	integer i;
	
	always @(posedge clear, negedge clock)
		if (clear) begin


			for (i = 0; i < 256; i = i + 1)
				content[i] = 0;




			content[0] = 100;
			content[1] = 200;

		end else if (write
				&& address >= 32'h10010000
				&& address < 32'h10014000)
		begin



			content[(address - 32'h10001000) >> 2] = write_data;
			$display("\tM[%x] = %x (hex)", address, write_data);
		end


	assign read_data = address >= 32'h10010000
			&& address < 32'h10014000 ?
			content[(address - 32'h10010000) >> 2] : 0;
	
endmodule