data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v
1: b'%Error: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:34: Cannot find file containing module: \'RTC\'\nRTC rtc(.clk(clk),\n^~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC.v\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC.sv\n             RTC\n             RTC.v\n             RTC.sv\n             obj_dir/RTC\n             obj_dir/RTC.v\n             obj_dir/RTC.sv\n%Error: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:60: Cannot find file containing module: \'UART_TEST\'\nUART_TEST ut(.clk(clk),\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:76: Input port connection \'sel\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'sel\' generates 2 bits.\n                                                                              : ... In instance IOmodule\n      .sel(sel),\n       ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module uartSelector(
	input clk,
	input rst,
	
	input sel,
	
	input txIn,
	
	output reg txIn1,
	output reg txIn2,
	
	input rxIn1,
	input rxIn2,
	
	output reg rxIn

);


always@(posedge clk or posedge rst)begin
	if(rst)begin
		rxIn <= 0;
		txIn1 <= 0;
		txIn2 <= 0;
	end else if(sel)begin
		rxIn <= rxIn2;
		txIn1 <= 0;
		txIn2 <= txIn;
	
	end else
	begin
		rxIn <= rxIn1;
		txIn1 <= txIn;
		txIn2 <= 0;
	end
end

endmodule
module uartSelector(
	input clk,
	input rst,
	
	input sel,
	
	input txIn,
	
	output reg txIn1,
	output reg txIn2,
	
	input rxIn1,
	input rxIn2,
	
	output reg rxIn

);



always@(posedge clk or posedge rst)begin
	if(rst)begin
		rxIn <= 0;
		txIn1 <= 0;
		txIn2 <= 0;
	end else if(sel)begin
		rxIn <= rxIn2;
		txIn1 <= 0;
		txIn2 <= txIn;
	
	end else
	begin
		rxIn <= rxIn1;
		txIn1 <= txIn;
		txIn2 <= 0;
	end
end

endmodule