data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:40: Cannot find include file: brams_init_36.vh\n  `include "brams_init_36.vh" \n           ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_36.vh\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_36.vh.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_36.vh.sv\n             brams_init_36.vh\n             brams_init_36.vh.v\n             brams_init_36.vh.sv\n             obj_dir/brams_init_36.vh\n             obj_dir/brams_init_36.vh.v\n             obj_dir/brams_init_36.vh.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:109: Cannot find include file: brams_init_18.vh\n  `include "brams_init_18.vh" \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:189: Cannot find include file: brams_init_36.vh\n   `include "brams_init_36.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:231: Cannot find include file: brams_init_32.vh\n   `include "brams_init_32.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:311: Cannot find include file: brams_init_18.vh\n   `include "brams_init_18.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xcu_brams_map.v:354: Cannot find include file: brams_init_16.vh\n   `include "brams_init_16.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [18431:0] INIT = 18432'bx;

	input CLK2;
	input CLK3;

	input [8:0] A1ADDR;
	output [35:0] A1DATA;
	input A1EN;

	input [8:0] B1ADDR;
	input [35:0] B1DATA;
	input [3:0] B1EN;

	wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
	wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	RAMB18E2 #(
		.READ_WIDTH_A(36),
		.WRITE_WIDTH_B(36),
		.WRITE_MODE_A("READ_FIRST"),
		.WRITE_MODE_B("READ_FIRST"),
		.DOA_REG(0),
		.DOB_REG(0),
		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
		`include "brams_init_18.vh"
	) _TECHMAP_REPLACE_ (
		.DOUTBDOUT(DO[31:16]),
		.DOUTADOUT(DO[15:0]),
		.DOUTPBDOUTP(DOP[3:2]),
		.DOUTPADOUTP(DOP[1:0]),
		.DINBDIN(DI[31:16]),
		.DINADIN(DI[15:0]),
		.DINPBDINP(DIP[3:2]),
		.DINPADINP(DIP[1:0]),

		.ADDRARDADDR(A1ADDR_14),
		.CLKARDCLK(CLK2),
		.ENARDEN(A1EN),
		.ADDRENA(|1),
		.REGCEAREGCE(|1),
		.RSTRAMARSTRAM(|0),
		.RSTREGARSTREG(|0),
		.WEA(2'b0),

		.ADDRBWRADDR(B1ADDR_14),
		.CLKBWRCLK(CLK3),
		.ENBWREN(|1),
		.ADDRENB(|1),
		.REGCEB(|1),
		.RSTRAMB(|0),
		.RSTREGB(|0),
		.WEBWE(B1EN),

		.SLEEP(|0)
	);
endmodule
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [18431:0] INIT = 18432'bx;

	input CLK2;
	input CLK3;

	input [8:0] A1ADDR;
	output [35:0] A1DATA;
	input A1EN;

	input [8:0] B1ADDR;
	input [35:0] B1DATA;
	input [3:0] B1EN;

	wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
	wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	RAMB18E2 #(
		.READ_WIDTH_A(36),
		.WRITE_WIDTH_B(36),
		.WRITE_MODE_A("READ_FIRST"),
		.WRITE_MODE_B("READ_FIRST"),
		.DOA_REG(0),
		.DOB_REG(0),
		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
		`include "brams_init_18.vh"
	) _TECHMAP_REPLACE_ (
		.DOUTBDOUT(DO[31:16]),
		.DOUTADOUT(DO[15:0]),
		.DOUTPBDOUTP(DOP[3:2]),
		.DOUTPADOUTP(DOP[1:0]),
		.DINBDIN(DI[31:16]),
		.DINADIN(DI[15:0]),
		.DINPBDINP(DIP[3:2]),
		.DINPADINP(DIP[1:0]),

		.ADDRARDADDR(A1ADDR_14),
		.CLKARDCLK(CLK2),
		.ENARDEN(A1EN),
		.ADDRENA(|1),
		.REGCEAREGCE(|1),
		.RSTRAMARSTRAM(|0),
		.RSTREGARSTREG(|0),
		.WEA(2'b0),

		.ADDRBWRADDR(B1ADDR_14),
		.CLKBWRCLK(CLK3),
		.ENBWREN(|1),
		.ADDRENB(|1),
		.REGCEB(|1),
		.RSTRAMB(|0),
		.RSTREGB(|0),
		.WEBWE(B1EN),

		.SLEEP(|0)
	);
endmodule