data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/UPDOWN_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/UPDOWN_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_tb = ~clk_tb;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/UPDOWN_TB.v:9: Cannot find file containing module: \'UPDOWN\'\n    UPDOWN COMP (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/UPDOWN\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/UPDOWN.v\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/UPDOWN.sv\n             UPDOWN\n             UPDOWN.v\n             UPDOWN.sv\n             obj_dir/UPDOWN\n             obj_dir/UPDOWN.v\n             obj_dir/UPDOWN.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UPDOWN_TB(
    );
    reg clk_tb,rst_tb;

    reg ud_tb;
    wire [3:0] cnt_tb;
    wire [3:0] cnt_tb2;     
    UPDOWN COMP (
    .clk1(clk_tb),
    .rst1(rst_tb),

    .ud(ud_tb),
    .tmp(cnt_tb),
    .tmp2(cnt_tb2)       
    );    
    initial 
        begin
        clk_tb = 0;
        rst_tb = 0;
        ud_tb = 1;

        end        
    always   
        begin
        #5 clk_tb = ~clk_tb;
        end  

      
   
endmodule
module UPDOWN_TB(
    );

    reg clk_tb,rst_tb;

    reg ud_tb;
    wire [3:0] cnt_tb;
    wire [3:0] cnt_tb2;     
    UPDOWN COMP (
    .clk1(clk_tb),
    .rst1(rst_tb),

    .ud(ud_tb),
    .tmp(cnt_tb),
    .tmp2(cnt_tb2)       
    );    
    initial 
        begin
        clk_tb = 0;
        rst_tb = 0;
        ud_tb = 1;

        end        
    always   
        begin
        #5 clk_tb = ~clk_tb;
        end  

      
   
endmodule