data/full_repos/permissive/423852699/verilog/ID_EXE_reg.v
data/verilator_xmls/58cb6262-0669-4b74-b99d-dd34de1543e6.xml
module ID_EXE_reg (
    input wire clk,
    input wire reset,
    input wire ena,
    input wire[31:0] id_instr_in,
    input wire[31:0] id_pc_in,

    input wire[31:0] ext_result_in,
    input wire[31:0] id_GPR_rs_in,
    input wire[31:0] id_GPR_rt_in,

    input wire id_GPR_we_in,
    input wire[4:0] id_GPR_waddr_in,
    input wire[1:0] id_GPR_wdata_select_in,


    output reg[31:0] exe_alu_opr1_out,
    output reg[31:0] exe_alu_opr2_out,
    output wire[3:0] exe_alu_contorl,
    output reg exe_GPR_we,
    output reg[4:0] exe_GPR_waddr,
    output reg[1:0] exe_GPR_wdata_select,
    output reg[31:0] exe_GPR_rt_out,
    output reg[31:0] exe_pc_out,
    output reg[31:0] exe_instr_out
);

    wire alu_opr1_select = ~id_instr_in[29] & ~id_instr_in[28] & ~id_instr_in[27] & ~id_instr_in[26] & ~id_instr_in[5] & ~id_instr_in[3] & ~id_instr_in[2];
    wire alu_opr2_select = (id_instr_in[29] | id_instr_in[31]);

    always @(posedge clk or negedge reset) begin
        if (!reset) begin
            exe_pc_out <= 32'h00000000;
            exe_instr_out <= 32'h00000000;

            exe_alu_opr1_out <= 0;
            exe_alu_opr2_out <= 0;
            exe_GPR_waddr <= 0;
            exe_GPR_wdata_select <= 0;
            exe_GPR_rt_out <= 0;
            exe_GPR_we <= 0;
        end
        else if (ena) begin
            exe_pc_out <= id_pc_in;
            exe_instr_out <= id_instr_in;

            exe_alu_opr1_out <= alu_opr1_select ? ext_result_in : id_GPR_rs_in;
            exe_alu_opr2_out <= alu_opr2_select ? ext_result_in : id_GPR_rt_in;

            exe_GPR_we <= id_GPR_we_in & ena;
            exe_GPR_waddr <= id_GPR_waddr_in;
            exe_GPR_wdata_select <= id_GPR_wdata_select_in;
            exe_GPR_rt_out <= id_GPR_rt_in;
        end
    end

    reg[3:0] alu_control_reg;
    assign exe_alu_contorl = alu_control_reg;



    always @(*) begin
        case (exe_instr_out[31:26])
            6'b000000:
            begin
                case (exe_instr_out[5:0])
                    6'b100000:
                    begin
                        alu_control_reg = 4'b0010;
                    end 

                    6'b100001:
                    begin
                        alu_control_reg = 4'b0011;
                    end

                    6'b100010:
                    begin
                        alu_control_reg = 4'b0100;
                    end

                    6'b100011:
                    begin
                        alu_control_reg = 4'b0101;
                    end

                    6'b100100:
                    begin
                        alu_control_reg = 4'b0110;
                    end

                    6'b100101:
                    begin
                        alu_control_reg = 4'b0111;
                    end

                    6'b100110:
                    begin
                        alu_control_reg = 4'b1000;
                    end

                    6'b100111:
                    begin
                        alu_control_reg = 4'b1001;
                    end

                    6'b101010:
                    begin
                        alu_control_reg = 4'b1010;
                    end

                    6'b101011:
                    begin
                        alu_control_reg = 4'b1011;
                    end

                    6'b000000,
                    6'b000100:
                    begin
                        alu_control_reg = 4'b1110;
                    end

                    6'b000010,
                    6'b000110:
                    begin
                        alu_control_reg = 4'b1100;
                    end

                    6'b000011,
                    6'b000111:
                    begin
                        alu_control_reg = 4'b1101;
                    end

                    6'b001011:
                    begin
                        alu_control_reg = 4'b0001;
                    end

                    6'b001010:
                    begin
                        alu_control_reg = 4'b0000;
                    end
                    default:
                    begin
                        alu_control_reg = 4'b0000;
                    end
                endcase
            end 
            6'b001000:
            begin
                alu_control_reg = 4'b0010;
            end

            6'b100011,
            6'b101011,
            6'b001001:
            begin
                alu_control_reg = 4'b0011;
            end

            6'b001100:
            begin
                alu_control_reg = 4'b0110;
            end

            6'b001101:
            begin
                alu_control_reg = 4'b0111;
            end

            6'b001110:
            begin
                alu_control_reg = 4'b1000;
            end

            6'b001010:
            begin
                alu_control_reg = 4'b1010;
            end

            6'b001011:
            begin
                alu_control_reg = 4'b1011;
            end

            6'b001111:
            begin
                alu_control_reg = 4'b1111;
            end
            default:
            begin
                alu_control_reg = 4'b0110;
            end
        endcase
    end



























endmodule
module ID_EXE_reg (
    input wire clk,
    input wire reset,
    input wire ena,
    input wire[31:0] id_instr_in,
    input wire[31:0] id_pc_in,

    input wire[31:0] ext_result_in,
    input wire[31:0] id_GPR_rs_in,
    input wire[31:0] id_GPR_rt_in,

    input wire id_GPR_we_in,
    input wire[4:0] id_GPR_waddr_in,
    input wire[1:0] id_GPR_wdata_select_in,


    output reg[31:0] exe_alu_opr1_out,
    output reg[31:0] exe_alu_opr2_out,
    output wire[3:0] exe_alu_contorl,
    output reg exe_GPR_we,
    output reg[4:0] exe_GPR_waddr,
    output reg[1:0] exe_GPR_wdata_select,
    output reg[31:0] exe_GPR_rt_out,
    output reg[31:0] exe_pc_out,
    output reg[31:0] exe_instr_out
);


    wire alu_opr1_select = ~id_instr_in[29] & ~id_instr_in[28] & ~id_instr_in[27] & ~id_instr_in[26] & ~id_instr_in[5] & ~id_instr_in[3] & ~id_instr_in[2];
    wire alu_opr2_select = (id_instr_in[29] | id_instr_in[31]);

    always @(posedge clk or negedge reset) begin
        if (!reset) begin
            exe_pc_out <= 32'h00000000;
            exe_instr_out <= 32'h00000000;

            exe_alu_opr1_out <= 0;
            exe_alu_opr2_out <= 0;
            exe_GPR_waddr <= 0;
            exe_GPR_wdata_select <= 0;
            exe_GPR_rt_out <= 0;
            exe_GPR_we <= 0;
        end
        else if (ena) begin
            exe_pc_out <= id_pc_in;
            exe_instr_out <= id_instr_in;

            exe_alu_opr1_out <= alu_opr1_select ? ext_result_in : id_GPR_rs_in;
            exe_alu_opr2_out <= alu_opr2_select ? ext_result_in : id_GPR_rt_in;

            exe_GPR_we <= id_GPR_we_in & ena;
            exe_GPR_waddr <= id_GPR_waddr_in;
            exe_GPR_wdata_select <= id_GPR_wdata_select_in;
            exe_GPR_rt_out <= id_GPR_rt_in;
        end
    end

    reg[3:0] alu_control_reg;
    assign exe_alu_contorl = alu_control_reg;



    always @(*) begin
        case (exe_instr_out[31:26])
            6'b000000:
            begin
                case (exe_instr_out[5:0])
                    6'b100000:
                    begin
                        alu_control_reg = 4'b0010;
                    end 

                    6'b100001:
                    begin
                        alu_control_reg = 4'b0011;
                    end

                    6'b100010:
                    begin
                        alu_control_reg = 4'b0100;
                    end

                    6'b100011:
                    begin
                        alu_control_reg = 4'b0101;
                    end

                    6'b100100:
                    begin
                        alu_control_reg = 4'b0110;
                    end

                    6'b100101:
                    begin
                        alu_control_reg = 4'b0111;
                    end

                    6'b100110:
                    begin
                        alu_control_reg = 4'b1000;
                    end

                    6'b100111:
                    begin
                        alu_control_reg = 4'b1001;
                    end

                    6'b101010:
                    begin
                        alu_control_reg = 4'b1010;
                    end

                    6'b101011:
                    begin
                        alu_control_reg = 4'b1011;
                    end

                    6'b000000,
                    6'b000100:
                    begin
                        alu_control_reg = 4'b1110;
                    end

                    6'b000010,
                    6'b000110:
                    begin
                        alu_control_reg = 4'b1100;
                    end

                    6'b000011,
                    6'b000111:
                    begin
                        alu_control_reg = 4'b1101;
                    end

                    6'b001011:
                    begin
                        alu_control_reg = 4'b0001;
                    end

                    6'b001010:
                    begin
                        alu_control_reg = 4'b0000;
                    end
                    default:
                    begin
                        alu_control_reg = 4'b0000;
                    end
                endcase
            end 
            6'b001000:
            begin
                alu_control_reg = 4'b0010;
            end

            6'b100011,
            6'b101011,
            6'b001001:
            begin
                alu_control_reg = 4'b0011;
            end

            6'b001100:
            begin
                alu_control_reg = 4'b0110;
            end

            6'b001101:
            begin
                alu_control_reg = 4'b0111;
            end

            6'b001110:
            begin
                alu_control_reg = 4'b1000;
            end

            6'b001010:
            begin
                alu_control_reg = 4'b1010;
            end

            6'b001011:
            begin
                alu_control_reg = 4'b1011;
            end

            6'b001111:
            begin
                alu_control_reg = 4'b1111;
            end
            default:
            begin
                alu_control_reg = 4'b0110;
            end
        endcase
    end



























endmodule