data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v
1: b'%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:50: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v.v\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:127: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do(miso)\n   ^~\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:127: syntax error, unexpected \'(\', expecting \')\'\n  .do(miso)\n      ^~~~\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:139: Unsupported: Verilog 1995 force\n       force spi_slave.debug = 1\'b0;  \n       ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:149: Unsupported: Ignoring delay on this delayed statement.\n       #2;\n       ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:151: syntax error, unexpected \'@\'\n       repeat(1) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:156: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:166: Unsupported: Verilog 1995 force\n           force spi_slave.cpol=cpol[0];\n           ^~~~~\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:167: Unsupported: Verilog 1995 force\n           force spi_slave.cpha=cpha[0];\n           ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/tst_bench_top.v:212: Unsupported: Ignoring delay on this delayed statement.\n       #250000;  \n       ^\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module tst_bench_top();




	reg  clk;
	reg  rstn;

	wire [31:0] adr;
	wire [ 7:0] dat_i, dat_o;
	wire we;
	wire stb;
	wire cyc;
	wire ack;
	wire inta;

	reg [1:0] cpol, cpha;
	reg [2:0] e;

	wire sck, mosi, miso;
	reg [7:0] q;

	parameter SPCR = 2'b00;
	parameter SPSR = 2'b01;
	parameter SPDR = 2'b10;
	parameter SPER = 2'b11;




	integer n;


	always #5 clk = ~clk;


	wb_master_model #(8, 32) u0 (
		.clk (clk),
		.rst (rstn),
		.adr (adr),
		.din (dat_i),
		.dout(dat_o),
		.cyc (cyc),
		.stb (stb),
		.we  (we),
		.sel (),
		.ack (ack),
		.err (1'b0),
		.rty (1'b0)
	);


	simple_spi_top spi_top (

		.clk_i (clk),
		.rst_i (rstn),
		.cyc_i (cyc),
		.stb_i (stb),
		.adr_i (adr[1:0]),
		.we_i  (we),
		.dat_i (dat_o),
		.dat_o (dat_i),
		.ack_o (ack),
		.inta_o(inta),

		.sck_o (sck),
		.mosi_o(mosi),
		.miso_i(miso)
	);


	spi_slave_model spi_slave (
		.csn(1'b0),
		.sck(sck),
		.di(mosi),
		.do(miso)
	);

	initial
	  begin
	      `ifdef WAVES
	         $shm_open("waves");
	         $shm_probe("AS",tst_bench_top,"AS");
	         $display("INFO: Signal dump enabled ...\n\n");
	      `endif


	      force spi_slave.debug = 1'b0;

	      $display("\nstatus: %t Testbench started\n\n", $time);



	      clk = 0;


	      rstn = 1'b1;
	      #2;
	      rstn = 1'b0;
	      repeat(1) @(posedge clk);
	      rstn = 1'b1;

	      $display("status: %t done reset", $time);

	      @(posedge clk);




	      for (cpol=0; cpol<=1; cpol=cpol+1)
	      for (cpha=0; cpha<=1; cpha=cpha+1) 
	      for (e=0; e<=3; e=e+1)
	      begin

	          force spi_slave.cpol=cpol[0];
	          force spi_slave.cpha=cpha[0];
	          $display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);




	          u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );

	          u0.wb_cmp  (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );

	          

	          u0.wb_write(1,SPER,8'h0);

	          u0.wb_cmp (0,SPER,8'h0);


	          for(n=0;n<8;n=n+1) begin
	            u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});

	            u0.wb_read(1,SPSR,q);
	            while(~q[7]) u0.wb_read(1,SPSR,q);

	            u0.wb_write(1,SPSR,8'h80);
	          end


	          for(n=0;n<8;n=n+1) begin
	            u0.wb_write(1,SPDR,~n);

	            u0.wb_read(1,SPSR,q);
	            while(~q[7]) u0.wb_read(1,SPSR,q);

	            u0.wb_write(1,SPSR,8'h80);

	            u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
	          end
	      end







	      #250000;
	      $display("\n\nstatus: %t Testbench done", $time);
	      $finish;
	  end

endmodule
module tst_bench_top();





	reg  clk;
	reg  rstn;

	wire [31:0] adr;
	wire [ 7:0] dat_i, dat_o;
	wire we;
	wire stb;
	wire cyc;
	wire ack;
	wire inta;

	reg [1:0] cpol, cpha;
	reg [2:0] e;

	wire sck, mosi, miso;
	reg [7:0] q;

	parameter SPCR = 2'b00;
	parameter SPSR = 2'b01;
	parameter SPDR = 2'b10;
	parameter SPER = 2'b11;




	integer n;


	always #5 clk = ~clk;


	wb_master_model #(8, 32) u0 (
		.clk (clk),
		.rst (rstn),
		.adr (adr),
		.din (dat_i),
		.dout(dat_o),
		.cyc (cyc),
		.stb (stb),
		.we  (we),
		.sel (),
		.ack (ack),
		.err (1'b0),
		.rty (1'b0)
	);


	simple_spi_top spi_top (

		.clk_i (clk),
		.rst_i (rstn),
		.cyc_i (cyc),
		.stb_i (stb),
		.adr_i (adr[1:0]),
		.we_i  (we),
		.dat_i (dat_o),
		.dat_o (dat_i),
		.ack_o (ack),
		.inta_o(inta),

		.sck_o (sck),
		.mosi_o(mosi),
		.miso_i(miso)
	);


	spi_slave_model spi_slave (
		.csn(1'b0),
		.sck(sck),
		.di(mosi),
		.do(miso)
	);

	initial
	  begin
	      `ifdef WAVES
	         $shm_open("waves");
	         $shm_probe("AS",tst_bench_top,"AS");
	         $display("INFO: Signal dump enabled ...\n\n");
	      `endif


	      force spi_slave.debug = 1'b0;

	      $display("\nstatus: %t Testbench started\n\n", $time);



	      clk = 0;


	      rstn = 1'b1;
	      #2;
	      rstn = 1'b0;
	      repeat(1) @(posedge clk);
	      rstn = 1'b1;

	      $display("status: %t done reset", $time);

	      @(posedge clk);




	      for (cpol=0; cpol<=1; cpol=cpol+1)
	      for (cpha=0; cpha<=1; cpha=cpha+1) 
	      for (e=0; e<=3; e=e+1)
	      begin

	          force spi_slave.cpol=cpol[0];
	          force spi_slave.cpha=cpha[0];
	          $display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);




	          u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );

	          u0.wb_cmp  (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );

	          

	          u0.wb_write(1,SPER,8'h0);

	          u0.wb_cmp (0,SPER,8'h0);


	          for(n=0;n<8;n=n+1) begin
	            u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});

	            u0.wb_read(1,SPSR,q);
	            while(~q[7]) u0.wb_read(1,SPSR,q);

	            u0.wb_write(1,SPSR,8'h80);
	          end


	          for(n=0;n<8;n=n+1) begin
	            u0.wb_write(1,SPDR,~n);

	            u0.wb_read(1,SPSR,q);
	            while(~q[7]) u0.wb_read(1,SPSR,q);

	            u0.wb_write(1,SPSR,8'h80);

	            u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
	          end
	      end







	      #250000;
	      $display("\n\nstatus: %t Testbench done", $time);
	      $finish;
	  end

endmodule