data/full_repos/permissive/488835089/level-1/level-2/timer_input_control.v
1: b'%Error: data/full_repos/permissive/488835089/level-1/level-2/timer_input_control.v:1: Cannot find include file: level-3/counter_0_7.v\n`include "level-3/counter_0_7.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488835089/level-1/level-2,data/full_repos/permissive/488835089/level-3/counter_0_7.v\n             data/full_repos/permissive/488835089/level-1/level-2,data/full_repos/permissive/488835089/level-3/counter_0_7.v.v\n             data/full_repos/permissive/488835089/level-1/level-2,data/full_repos/permissive/488835089/level-3/counter_0_7.v.sv\n             level-3/counter_0_7.v\n             level-3/counter_0_7.v.v\n             level-3/counter_0_7.v.sv\n             obj_dir/level-3/counter_0_7.v\n             obj_dir/level-3/counter_0_7.v.v\n             obj_dir/level-3/counter_0_7.v.sv\n%Error: data/full_repos/permissive/488835089/level-1/level-2/timer_input_control.v:2: Cannot find include file: level-3/div_freq_100hz.v\n`include "level-3/div_freq_100hz.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488835089/level-1/level-2/timer_input_control.v:3: Cannot find include file: level-3/encoder_dec_to_bcd.v\n`include "level-3/encoder_dec_to_bcd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488835089/level-1/level-2/timer_input_control.v:4: Cannot find include file: level-3/mux_2to1.v\n`include "level-3/mux_2to1.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module timer_input_control(input wire [9:0] KPAD,
                           input wire EN_N,
                           input CLK_100HZ,
                           output wire [3:0] D,
                           output wire LOAD_N,
                           output wire CLK_1HZ
                           );

    wire mux_D0_debouncer_0_7, mux_D1_clk_1hz;


encoder_dec_to_bcd encoder(KPAD, EN_N, D, LOAD_N);
counter_0_7 counter(CLK_100HZ, LOAD_N, mux_D0_debouncer_0_7);
div_freq_100hz freq_div100(CLK_100HZ, mux_D1_clk_1hz);
mux_2to1 mux2to1(EN_N, mux_D0_debouncer_0_7 ,mux_D1_clk_1hz, CLK_1HZ);

endmodule
module timer_input_control(input wire [9:0] KPAD,
                           input wire EN_N,
                           input CLK_100HZ,
                           output wire [3:0] D,
                           output wire LOAD_N,
                           output wire CLK_1HZ
                           );


    wire mux_D0_debouncer_0_7, mux_D1_clk_1hz;


encoder_dec_to_bcd encoder(KPAD, EN_N, D, LOAD_N);
counter_0_7 counter(CLK_100HZ, LOAD_N, mux_D0_debouncer_0_7);
div_freq_100hz freq_div100(CLK_100HZ, mux_D1_clk_1hz);
mux_2to1 mux2to1(EN_N, mux_D0_debouncer_0_7 ,mux_D1_clk_1hz, CLK_1HZ);

endmodule