data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/intfdemux8.v
data/verilator_xmls/53cc2f08-75a5-4bc7-8ae0-06017c5f61ce.xml
module intfdemux8
    (
     rst_,
     synclk,
     
     idat,
     isyn,
   
     odat
     );




parameter LINEBIT = 1;
parameter DEMUX   = 4;
parameter BITTS   = 3;
parameter MAXTS   = 6;
parameter DATABIT = DEMUX*LINEBIT;




input                rst_;
input [LINEBIT-1:0]  idat;
input                isyn;

input                synclk;
output [DATABIT-1:0] odat;




reg [2:0]   shfdet;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) shfdet <= 3'd0;
    else      shfdet <= {shfdet[1:0],isyn};
    end

wire    posdet;
assign  posdet = shfdet == 3'b011;

reg [MAXTS-5:0] posdetpipe;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) posdetpipe <= {(MAXTS-4){1'b0}};
    else      posdetpipe <= {posdetpipe[MAXTS-6:0],posdet};
    end

wire    capture;
assign  capture = posdetpipe[MAXTS-5];

reg [BITTS-1:0] cntts;
wire            endcntts;
assign          endcntts = cntts == (MAXTS-1);

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_)         cntts <= {BITTS{1'b0}};
    else if(capture)  cntts <= {BITTS{1'b0}};
    else if(endcntts) cntts <= {BITTS{1'b0}};
    else              cntts <= cntts + 1'b1;
    end
    
reg [2:0] cntph;
wire      endcntph;
assign    endcntph = cntph == (DEMUX-1);

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) cntph <= 3'd0;
    else if(capture)  cntph <= 3'd0;
    else if(endcntph) cntph <= DEMUX-1;
    else if(endcntts) cntph <= cntph + 1'b1;
    end

wire    shiften;

assign  shiften = capture | ((cntph < (DEMUX-1)) & endcntts);

reg [DATABIT-1:0] dashf;
wire [DATABIT+LINEBIT-1:0] dacap;
assign                     dacap = {dashf,idat};

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_)        dashf <= {DATABIT{1'b0}};
    else if(shiften) dashf <= dacap[DATABIT-1:0];
    end



reg [DATABIT-1:0] odat;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) odat <= {DATABIT{1'b0}};
    else if(endcntts & (cntph == (DEMUX-2))) odat <= dacap[DATABIT-1:0];
    end

endmodule
module intfdemux8
    (
     rst_,
     synclk,
     
     idat,
     isyn,
   
     odat
     );





parameter LINEBIT = 1;
parameter DEMUX   = 4;
parameter BITTS   = 3;
parameter MAXTS   = 6;
parameter DATABIT = DEMUX*LINEBIT;




input                rst_;
input [LINEBIT-1:0]  idat;
input                isyn;

input                synclk;
output [DATABIT-1:0] odat;




reg [2:0]   shfdet;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) shfdet <= 3'd0;
    else      shfdet <= {shfdet[1:0],isyn};
    end

wire    posdet;
assign  posdet = shfdet == 3'b011;

reg [MAXTS-5:0] posdetpipe;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) posdetpipe <= {(MAXTS-4){1'b0}};
    else      posdetpipe <= {posdetpipe[MAXTS-6:0],posdet};
    end

wire    capture;
assign  capture = posdetpipe[MAXTS-5];

reg [BITTS-1:0] cntts;
wire            endcntts;
assign          endcntts = cntts == (MAXTS-1);

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_)         cntts <= {BITTS{1'b0}};
    else if(capture)  cntts <= {BITTS{1'b0}};
    else if(endcntts) cntts <= {BITTS{1'b0}};
    else              cntts <= cntts + 1'b1;
    end
    
reg [2:0] cntph;
wire      endcntph;
assign    endcntph = cntph == (DEMUX-1);

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) cntph <= 3'd0;
    else if(capture)  cntph <= 3'd0;
    else if(endcntph) cntph <= DEMUX-1;
    else if(endcntts) cntph <= cntph + 1'b1;
    end

wire    shiften;

assign  shiften = capture | ((cntph < (DEMUX-1)) & endcntts);

reg [DATABIT-1:0] dashf;
wire [DATABIT+LINEBIT-1:0] dacap;
assign                     dacap = {dashf,idat};

always @(posedge synclk or negedge rst_)
    begin
    if(!rst_)        dashf <= {DATABIT{1'b0}};
    else if(shiften) dashf <= dacap[DATABIT-1:0];
    end



reg [DATABIT-1:0] odat;
always @(posedge synclk or negedge rst_)
    begin
    if(!rst_) odat <= {DATABIT{1'b0}};
    else if(endcntts & (cntph == (DEMUX-2))) odat <= dacap[DATABIT-1:0];
    end

endmodule