data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v
1: b'%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:17: Cannot find include file: ../driver.v\n`include "../driver.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524532083/verilog/dv/system_10dot_test,data/full_repos/permissive/524532083/../driver.v\n             data/full_repos/permissive/524532083/verilog/dv/system_10dot_test,data/full_repos/permissive/524532083/../driver.v.v\n             data/full_repos/permissive/524532083/verilog/dv/system_10dot_test,data/full_repos/permissive/524532083/../driver.v.sv\n             ../driver.v\n             ../driver.v.v\n             ../driver.v.sv\n             obj_dir/../driver.v\n             obj_dir/../driver.v.v\n             obj_dir/../driver.v.sv\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:114: syntax error, unexpected (-for-strength, expecting \'(\'\n pulldown (weak0,strong1) p (gpio);\n           ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n always #40 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n always #150 spi_clock <= (spi_clock === 1\'b0);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:161: syntax error, unexpected \'@\'\n         @(posedge clock);\n         ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:172: syntax error, unexpected \'@\'\n   @(negedge spi_clock);\n   ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:176: syntax error, unexpected \'@\'\n   @(posedge spi_clock)\n   ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:181: syntax error, unexpected \'@\'\n  @(posedge clock);\n  ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:262: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:268: syntax error, unexpected \'@\'\n      @(posedge update_cycle_complete);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:278: syntax error, unexpected \'@\'\n      @(posedge update_cycle_complete);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:302: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:304: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:306: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:325: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:337: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:339: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:352: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:354: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:356: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:387: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:435: syntax error, unexpected \'@\'\n          @(posedge clock);\n          ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:444: syntax error, unexpected \'@\'\n          @(posedge clock);\n          ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:461: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:500: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n  seed = $random(seed);\n         ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/524532083/verilog/dv/system_10dot_test/system_10dot_test_tb.v:500: ../V3Ast.cpp:358: Null item passed to setOp1p\n  seed = $random(seed);\n       ^\n'
module sky130_ef_sc_hd__decap_12 (
    VPWR,
    VGND,
    VPB ,
    VNB
);


    input VPWR;
    input VGND;
    input VPB ;
    input VNB ;

endmodule
module sky130_ef_sc_hd__decap_12 (
    VPWR,
    VGND,
    VPB ,
    VNB
);



    input VPWR;
    input VGND;
    input VPB ;
    input VNB ;

endmodule