data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:16: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:17: Cannot find include file: UART_defines.v\n`include "UART_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:34: Cannot find include file: FIFO_inc.v\n`include "FIFO_inc.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:38: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word0 = fifo[0];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:39: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word1 = fifo[1];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:40: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word2 = fifo[2];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:41: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word3 = fifo[3];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:42: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word4 = fifo[4];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:43: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word5 = fifo[5];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:44: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word6 = fifo[6];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:45: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word7 = fifo[7];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:47: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word8 = fifo[8];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:48: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word9 = fifo[9];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:49: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word10 = fifo[10];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:50: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word11 = fifo[11];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:51: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word12 = fifo[12];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:52: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word13 = fifo[13];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:53: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word14 = fifo[14];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_RX_FIFO.v:54: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] word15 = fifo[15];\n      ^~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module UART_RX_FIFO (clk,
	wb_rst_i, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count,
	error_bit
	);

output		error_bit;
wire		error_bit;

`include "FIFO_inc.v"



wire	[`FIFO_REC_WIDTH-1:0]	word0 = fifo[0];
wire	[`FIFO_REC_WIDTH-1:0]	word1 = fifo[1];
wire	[`FIFO_REC_WIDTH-1:0]	word2 = fifo[2];
wire	[`FIFO_REC_WIDTH-1:0]	word3 = fifo[3];
wire	[`FIFO_REC_WIDTH-1:0]	word4 = fifo[4];
wire	[`FIFO_REC_WIDTH-1:0]	word5 = fifo[5];
wire	[`FIFO_REC_WIDTH-1:0]	word6 = fifo[6];
wire	[`FIFO_REC_WIDTH-1:0]	word7 = fifo[7];

wire	[`FIFO_REC_WIDTH-1:0]	word8 = fifo[8];
wire	[`FIFO_REC_WIDTH-1:0]	word9 = fifo[9];
wire	[`FIFO_REC_WIDTH-1:0]	word10 = fifo[10];
wire	[`FIFO_REC_WIDTH-1:0]	word11 = fifo[11];
wire	[`FIFO_REC_WIDTH-1:0]	word12 = fifo[12];
wire	[`FIFO_REC_WIDTH-1:0]	word13 = fifo[13];
wire	[`FIFO_REC_WIDTH-1:0]	word14 = fifo[14];
wire	[`FIFO_REC_WIDTH-1:0]	word15 = fifo[15];


assign	error_bit = |(word0[1:0]  | word1[1:0]  | word2[1:0]  | word3[1:0]  |
		      word4[1:0]  | word5[1:0]  | word6[1:0]  | word7[1:0]  |
		      word8[1:0]  | word9[1:0]  | word10[1:0] | word11[1:0] |
		      word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );

endmodule
module UART_RX_FIFO (clk,
	wb_rst_i, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count,
	error_bit
	);


output		error_bit;
wire		error_bit;

`include "FIFO_inc.v"



wire	[`FIFO_REC_WIDTH-1:0]	word0 = fifo[0];
wire	[`FIFO_REC_WIDTH-1:0]	word1 = fifo[1];
wire	[`FIFO_REC_WIDTH-1:0]	word2 = fifo[2];
wire	[`FIFO_REC_WIDTH-1:0]	word3 = fifo[3];
wire	[`FIFO_REC_WIDTH-1:0]	word4 = fifo[4];
wire	[`FIFO_REC_WIDTH-1:0]	word5 = fifo[5];
wire	[`FIFO_REC_WIDTH-1:0]	word6 = fifo[6];
wire	[`FIFO_REC_WIDTH-1:0]	word7 = fifo[7];

wire	[`FIFO_REC_WIDTH-1:0]	word8 = fifo[8];
wire	[`FIFO_REC_WIDTH-1:0]	word9 = fifo[9];
wire	[`FIFO_REC_WIDTH-1:0]	word10 = fifo[10];
wire	[`FIFO_REC_WIDTH-1:0]	word11 = fifo[11];
wire	[`FIFO_REC_WIDTH-1:0]	word12 = fifo[12];
wire	[`FIFO_REC_WIDTH-1:0]	word13 = fifo[13];
wire	[`FIFO_REC_WIDTH-1:0]	word14 = fifo[14];
wire	[`FIFO_REC_WIDTH-1:0]	word15 = fifo[15];


assign	error_bit = |(word0[1:0]  | word1[1:0]  | word2[1:0]  | word3[1:0]  |
		      word4[1:0]  | word5[1:0]  | word6[1:0]  | word7[1:0]  |
		      word8[1:0]  | word9[1:0]  | word10[1:0] | word11[1:0] |
		      word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );

endmodule