data/full_repos/permissive/423539813/source_files/instruction_memory.v
data/verilator_xmls/48e7c218-bb95-4f72-812c-2b9d695f0fd7.xml
module instruction_memory (input [31:0] pc,output reg [31:0] instruction);

 always@(*) begin
 case(pc)
 
 32'h0: instruction =  32'h00C00413;
 32'h4: instruction =  32'h00900493;

 32'h8: instruction =  32'h00940C63;
 32'hC: instruction =  32'h00944663;
 32'h10: instruction = 32'h40940433;
 32'h14: instruction = 32'hFE000AE3;

 32'h18: instruction = 32'h408484B3;
 32'h1C: instruction = 32'hFE0006E3;

 32'h20: instruction = 32'h00000063;

 endcase
 end
endmodule
module instruction_memory (input [31:0] pc,output reg [31:0] instruction);


 always@(*) begin
 case(pc)
 
 32'h0: instruction =  32'h00C00413;
 32'h4: instruction =  32'h00900493;

 32'h8: instruction =  32'h00940C63;
 32'hC: instruction =  32'h00944663;
 32'h10: instruction = 32'h40940433;
 32'h14: instruction = 32'hFE000AE3;

 32'h18: instruction = 32'h408484B3;
 32'h1C: instruction = 32'hFE0006E3;

 32'h20: instruction = 32'h00000063;

 endcase
 end
endmodule