data/full_repos/permissive/41334298/tests/elementary/t5.v
data/verilator_xmls/22e4d4ec-b1a4-4fd6-95af-6d81c1bb1ff4.xml
module top (a, b, c, y);
input a, b, c;
output y;

wire x;

and (x, a, b, c);
not (y, x);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;

wire x;

and (x, a, b, c);
not (y, x);

endmodule