data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v
1: b"%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:181: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule AES_Comp_EncCore(di, ki, Rrg, do, ko);\n                                     ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:184: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [127:0] do, ko;\n                 ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:205: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n  assign do = ((Rrg[0] == 1)? sr: mx) ^ ki;\n         ^~\n%Error: Exiting due to 3 error(s)\n"
module AES_Comp_ENC(Kin, Din, Dout, Krdy, Drdy, RSTn, EN, CLK, BSY, Kvld, Dvld);
  input  [127:0] Kin;
  input  [127:0] Din;
  output [127:0] Dout;
  input  Krdy;
  input  Drdy;
  input  RSTn;
  input  EN;
  input  CLK;
  output BSY;
  output Kvld;
  output Dvld;

  reg  [127:0] Drg;
  reg  [127:0] Krg;
  reg  [127:0] KrgX;
  reg  [9:0]   Rrg;
  reg  Kvldrg, Dvldrg, BSYrg;
  wire [127:0] Dnext, Knext;

  AES_Comp_EncCore EC (Drg, KrgX, Rrg, Dnext, Knext);

  assign Kvld = Kvldrg;
  assign Dvld = Dvldrg;
  assign Dout = Drg;
  assign BSY  = BSYrg;

  always @(posedge CLK) begin
    if (RSTn == 0) begin
      Krg    <= 128'h0000000000000000;
      KrgX   <= 128'h0000000000000000;
      Rrg    <= 10'b0000000001;
      Kvldrg <= 0;
      Dvldrg <= 0;
      BSYrg  <= 0;
    end
    else if (EN == 1) begin
      if (BSYrg == 0) begin
        if (Krdy == 1) begin
          Krg    <= Kin;
          KrgX   <= Kin;
          Kvldrg <= 1;
          Dvldrg <= 0;
        end
        else if (Drdy == 1) begin
          Rrg    <= {Rrg[8:0], Rrg[9]};
          KrgX   <= Knext;
          Drg    <= Din ^ Krg;
          Dvldrg <= 0;
          BSYrg  <= 1;
        end
      end
      else begin
        Drg <= Dnext;
        if (Rrg[0] == 1) begin
          KrgX   <= Krg;
          Dvldrg <= 1;
          BSYrg  <= 0;
        end
        else begin
          Rrg    <= {Rrg[8:0], Rrg[9]};
          KrgX   <= Knext;
        end
      end
    end
  end
 
  
endmodule
module AES_Comp_ENC(Kin, Din, Dout, Krdy, Drdy, RSTn, EN, CLK, BSY, Kvld, Dvld);

  input  [127:0] Kin;
  input  [127:0] Din;
  output [127:0] Dout;
  input  Krdy;
  input  Drdy;
  input  RSTn;
  input  EN;
  input  CLK;
  output BSY;
  output Kvld;
  output Dvld;

  reg  [127:0] Drg;
  reg  [127:0] Krg;
  reg  [127:0] KrgX;
  reg  [9:0]   Rrg;
  reg  Kvldrg, Dvldrg, BSYrg;
  wire [127:0] Dnext, Knext;

  AES_Comp_EncCore EC (Drg, KrgX, Rrg, Dnext, Knext);

  assign Kvld = Kvldrg;
  assign Dvld = Dvldrg;
  assign Dout = Drg;
  assign BSY  = BSYrg;

  always @(posedge CLK) begin
    if (RSTn == 0) begin
      Krg    <= 128'h0000000000000000;
      KrgX   <= 128'h0000000000000000;
      Rrg    <= 10'b0000000001;
      Kvldrg <= 0;
      Dvldrg <= 0;
      BSYrg  <= 0;
    end
    else if (EN == 1) begin
      if (BSYrg == 0) begin
        if (Krdy == 1) begin
          Krg    <= Kin;
          KrgX   <= Kin;
          Kvldrg <= 1;
          Dvldrg <= 0;
        end
        else if (Drdy == 1) begin
          Rrg    <= {Rrg[8:0], Rrg[9]};
          KrgX   <= Knext;
          Drg    <= Din ^ Krg;
          Dvldrg <= 0;
          BSYrg  <= 1;
        end
      end
      else begin
        Drg <= Dnext;
        if (Rrg[0] == 1) begin
          KrgX   <= Krg;
          Dvldrg <= 1;
          BSYrg  <= 0;
        end
        else begin
          Rrg    <= {Rrg[8:0], Rrg[9]};
          KrgX   <= Knext;
        end
      end
    end
  end
 
  
endmodule