data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Error: data/full_repos/permissive/428158935/sim_1/new/testbench_ALU_32bit.v:11: Cannot find file containing module: \'ALU_32bit\'\n    ALU_32bit uut(a,b,CI,F,dir,bite,S,CO);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428158935/sim_1/new,data/full_repos/permissive/428158935/ALU_32bit\n             data/full_repos/permissive/428158935/sim_1/new,data/full_repos/permissive/428158935/ALU_32bit.v\n             data/full_repos/permissive/428158935/sim_1/new,data/full_repos/permissive/428158935/ALU_32bit.sv\n             ALU_32bit\n             ALU_32bit.v\n             ALU_32bit.sv\n             obj_dir/ALU_32bit\n             obj_dir/ALU_32bit.v\n             obj_dir/ALU_32bit.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_alu();
    reg [31:0] a;
    reg [31:0] b;
    reg CI;
    reg [2:0] F;
    reg [1:0] dir;
    reg [4:0] bite;
    wire [31:0] S;
    wire CO;
    ALU_32bit uut(a,b,CI,F,dir,bite,S,CO);
    initial begin

        CI=0;
        F=0;
        a=0;
        b=0;
        dir=0;
        bite=0;
        #25;
        

        F=3'b001;
        a=32'b1111111;
        b=32'b11111;
        dir=0;
        bite=0;
        #25;


        a=32'b1111111111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b00;
        bite=5'b00111;
        #25;


        a=32'b111111111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b10;
        bite=5'b00011;
        #25;
        

        a=32'b111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b01;
        bite=5'b00111;
        #25;
        

        a=32'b111111111111111111;
        b=0;
        F=3'b010;       
        dir=2'b11;
        bite=5'b00111;
        #25;
        

        a=32'b111111111111111111111111111111;
        b=0;
        F=3'b011;
        dir=2'b00;
        bite=5'b11110;  
        #25;
         

        a=32'b1111111111111111111111111111111;
        b=0;
        F=3'b011;
        dir=2'b10;
        bite=5'b11110;  
        #25;
          

        a=32'b1111111;
        b=32'b1110000;
        F=3'b100;
        dir=0;
        bite=0;
        #25;


        a=32'b1110110;
        b=32'b110000;
        F=3'b101;
        dir=0;
        bite=0;
        #25;


        a=32'b1111111;
        b=0;
        F=3'b110;
        dir=0;
        bite=0;
        #25;


        a=32'b11111111;
        b=32'b1000111;
        F=3'b111;
        dir=0;
        bite=0;
        #25;
        end
endmodule
module test_alu();

    reg [31:0] a;
    reg [31:0] b;
    reg CI;
    reg [2:0] F;
    reg [1:0] dir;
    reg [4:0] bite;
    wire [31:0] S;
    wire CO;
    ALU_32bit uut(a,b,CI,F,dir,bite,S,CO);
    initial begin

        CI=0;
        F=0;
        a=0;
        b=0;
        dir=0;
        bite=0;
        #25;
        

        F=3'b001;
        a=32'b1111111;
        b=32'b11111;
        dir=0;
        bite=0;
        #25;


        a=32'b1111111111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b00;
        bite=5'b00111;
        #25;


        a=32'b111111111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b10;
        bite=5'b00011;
        #25;
        

        a=32'b111111111111111111;
        b=0;
        F=3'b010;
        dir=2'b01;
        bite=5'b00111;
        #25;
        

        a=32'b111111111111111111;
        b=0;
        F=3'b010;       
        dir=2'b11;
        bite=5'b00111;
        #25;
        

        a=32'b111111111111111111111111111111;
        b=0;
        F=3'b011;
        dir=2'b00;
        bite=5'b11110;  
        #25;
         

        a=32'b1111111111111111111111111111111;
        b=0;
        F=3'b011;
        dir=2'b10;
        bite=5'b11110;  
        #25;
          

        a=32'b1111111;
        b=32'b1110000;
        F=3'b100;
        dir=0;
        bite=0;
        #25;


        a=32'b1110110;
        b=32'b110000;
        F=3'b101;
        dir=0;
        bite=0;
        #25;


        a=32'b1111111;
        b=0;
        F=3'b110;
        dir=0;
        bite=0;
        #25;


        a=32'b11111111;
        b=32'b1000111;
        F=3'b111;
        dir=0;
        bite=0;
        #25;
        end
endmodule