data/full_repos/permissive/438129974/gameserver/LFSR.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/438129974/gameserver/LFSR.v:25: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'LFSR1\'\nmodule LFSR1(clk, rst_n, out);\n       ^~~~~\n                                                                            : ... Top module \'LFSR2\'\nmodule LFSR2(clk, rst_n, out);\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module LFSR1(clk, rst_n, out);
	input clk;
	input rst_n;
	output reg [7:0] out;
	reg [7:0] DFF;
	wire D1, D2, D3;
	assign D1 = out[7]^out[1];
	assign D2 = out[7]^out[2];
	assign D3 = out[7]^out[3];
	always@(posedge clk)begin
		if(rst_n)begin
			out <= 8'b10111101;
			DFF <= 8'b10111101;
		end else begin
			out <= DFF;
		end
	end
	always@(*) begin
		DFF = {out[6:4], D3, D2, D1, out[0], out[7]};
	end

endmodule
module LFSR1(clk, rst_n, out);

	input clk;
	input rst_n;
	output reg [7:0] out;
	reg [7:0] DFF;
	wire D1, D2, D3;
	assign D1 = out[7]^out[1];
	assign D2 = out[7]^out[2];
	assign D3 = out[7]^out[3];
	always@(posedge clk)begin
		if(rst_n)begin
			out <= 8'b10111101;
			DFF <= 8'b10111101;
		end else begin
			out <= DFF;
		end
	end
	always@(*) begin
		DFF = {out[6:4], D3, D2, D1, out[0], out[7]};
	end

endmodule