data/full_repos/permissive/472097485/Chu03/Barrel_01/RorL.v
data/verilator_xmls/7c76c097-6114-4fff-b175-053d722d5624.xml
module RorL( input [7:0] a, input rr, output [7:0] r );

	assign r = rr ? { a[0], a[7:1] } : { a[6:0], a[7] };

endmodule
module RorL( input [7:0] a, input rr, output [7:0] r );


	assign r = rr ? { a[0], a[7:1] } : { a[6:0], a[7] };

endmodule