data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:38: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h.sv\n             iop.h\n             iop.h.v\n             iop.h.sv\n             obj_dir/iop.h\n             obj_dir/iop.h.v\n             obj_dir/iop.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:43: Cannot find include file: tlu.h\n`include "tlu.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:110: Define or directive not defined: \'`TLU_SCPD_DATA_WIDTH\'\n   input [`TLU_SCPD_DATA_WIDTH-1:0] tlu_scpd_asi_rdata_g;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:111: Define or directive not defined: \'`TLU_ASI_QUE_WIDTH\'\n   input [`TLU_ASI_QUE_WIDTH-1:0]   tlu_asi_queue_rdata_g;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:524: Define or directive not defined: \'`TLU_SCPD_DATA_WIDTH\'\n      .in2  (tlu_scpd_asi_rdata_g[`TLU_SCPD_DATA_WIDTH-1:0]),\n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:525: Define or directive not defined: \'`TLU_ASI_QUE_WIDTH\'\n      .in3  ({50\'b0, tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0],6\'b0}),\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:560: Define or directive not defined: \'`INT_THR_HI\'\n   assign  indr_wr_pkt = {lsu_tlu_st_rs3_data_g[`INT_THR_HI:`INT_THR_LO], \n                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:560: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  indr_wr_pkt = {lsu_tlu_st_rs3_data_g[`INT_THR_HI:`INT_THR_LO], \n                                                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:560: Define or directive not defined: \'`INT_THR_LO\'\n   assign  indr_wr_pkt = {lsu_tlu_st_rs3_data_g[`INT_THR_HI:`INT_THR_LO], \n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:561: Define or directive not defined: \'`INT_VEC_HI\'\n     lsu_tlu_st_rs3_data_g[`INT_VEC_HI:`INT_VEC_LO]};\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:561: Define or directive not defined: \'`INT_VEC_LO\'\n     lsu_tlu_st_rs3_data_g[`INT_VEC_HI:`INT_VEC_LO]};\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:635: Define or directive not defined: \'`INT_RQ\'\n       {`INT_RQ},                \n        ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_intdp.v:635: Unsupported: empty queues ("{ }")\n       {`INT_RQ},                \n       ^\n%Error: Exiting due to 13 error(s)\n'
module sparc_tlu_intdp (

   int_pending_i2_l, ind_inc_thrid_i1,
   ind_inc_type_i1, tlu_lsu_int_ldxa_data_w2, int_tlu_rstid_m, 
   tlu_lsu_pcxpkt, so, 




   rclk, se, si, tlu_rst_l, lsu_tlu_st_rs3_data_g,
   inc_ind_ld_int_i1, inc_ind_rstthr_i1, inc_ind_asi_thr, 
   inc_ind_asi_wr_indr, inc_ind_indr_grant,
   inc_ind_thr_m, inc_ind_asi_wr_inrr, inc_ind_asi_rd_invr, 
   inc_indr_req_valid, inc_indr_req_thrid, tlu_asi_rdata_mxsel_g,
   tlu_asi_queue_rdata_g, tlu_scpd_asi_rdata_g, lsu_ind_intpkt_id,
   lsu_ind_intpkt_type, lsu_ind_intpkt_thr 
   );




   input      rclk, se, si, tlu_rst_l;



   input [63:0]  lsu_tlu_st_rs3_data_g;


   input [3:0] 	 inc_ind_ld_int_i1;
   input [3:0] 	 inc_ind_rstthr_i1;
   


   input [3:0] 	 inc_ind_asi_thr;
   input [3:0] 	 inc_ind_asi_wr_indr;


   input [3:0] 	 inc_ind_indr_grant;




   input [3:0]	 inc_ind_thr_m;
   

   input [3:0] 	 inc_ind_asi_wr_inrr;
   input [3:0] 	 inc_ind_asi_rd_invr;
   

   input 	 inc_indr_req_valid;
   input [1:0] 	 inc_indr_req_thrid;


   input [3:0] tlu_asi_rdata_mxsel_g;

   input [`TLU_SCPD_DATA_WIDTH-1:0] tlu_scpd_asi_rdata_g;
   input [`TLU_ASI_QUE_WIDTH-1:0]   tlu_asi_queue_rdata_g;
   input [4:0]  lsu_ind_intpkt_thr;
   input [1:0]  lsu_ind_intpkt_type;
   input [5:0]  lsu_ind_intpkt_id;


   output [3:0]  int_pending_i2_l;


   output [4:0]  ind_inc_thrid_i1;
   output [1:0]  ind_inc_type_i1;
   

   output [63:0] tlu_lsu_int_ldxa_data_w2;
   output [5:0]  int_tlu_rstid_m;
   
   output [25:0] tlu_lsu_pcxpkt;
   
   output 	 so;




   wire local_rst;

   wire [63:0] int_tlu_asi_data;

   wire [5:0] 	 int_id_i1;
   wire [5:0] 	 t0_rstid_i2,
		 t1_rstid_i2,
		 t2_rstid_i2,
		 t3_rstid_i2,
		 next_t0_rstid_i1,
		 next_t1_rstid_i1,
		 next_t2_rstid_i1,
		 next_t3_rstid_i1;


   wire [63:0]	 inrr_dec_i1,
		 inrr_rd_data_i2;

   wire [63:0] 	 t0_inrr_i2,
 		 t1_inrr_i2,
		 t2_inrr_i2,
		 t3_inrr_i2,
		 t0_inrr_aw_i2,
		 t1_inrr_aw_i2,
		 t2_inrr_aw_i2,
		 t3_inrr_aw_i2,
		 t0_inrr_arw_i1,
		 t1_inrr_arw_i1,
		 t2_inrr_arw_i1,
		 t3_inrr_arw_i1,
		 next_t0_inrr_i1,
		 next_t1_inrr_i1,
		 next_t2_inrr_i1,
		 next_t3_inrr_i1;
   
   wire [63:0] 	 new_t0_inrr_i1,
		 new_t1_inrr_i1,
		 new_t2_inrr_i1,
		 new_t3_inrr_i1;


   wire [63:0]   t0_asi_wr_data,
		 t1_asi_wr_data,
		 t2_asi_wr_data,
		 t3_asi_wr_data;


   wire [5:0] 	 t0_invr_i3,
 		 t1_invr_i3,
 		 t2_invr_i3,
 		 t3_invr_i3,
    		 t0_invr_i2,
 		 t1_invr_i2,
 		 t2_invr_i2,
 		 t3_invr_i2;
   wire [5:0] 	 invr_rd_data_i3;


   wire [63:0] 	 pe_ivec_i3,
		 t0_pe_ivec_i3,
		 t1_pe_ivec_i3,
		 t2_pe_ivec_i3,
		 t3_pe_ivec_i3;




   wire [10:0] 	 indr_wr_pkt;



   wire [10:0] 	 indr_pcxpkt,
		 t0_indr,
		 t1_indr,
		 t2_indr,
		 t3_indr,
		 t0_indr_next,
		 t1_indr_next,
		 t2_indr_next,
		 t3_indr_next;


   wire clk;







   assign clk = rclk;






   assign local_rst = ~tlu_rst_l;
   




   assign  int_id_i1[5:0]        = lsu_ind_intpkt_id[5:0];
   assign  ind_inc_type_i1[1:0]  = lsu_ind_intpkt_type[1:0];
   assign  ind_inc_thrid_i1[4:0] = lsu_ind_intpkt_thr[4:0];


   dp_mux2es #6 rid_mux0(.dout  (next_t0_rstid_i1[5:0]),
			 .in0   (t0_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[0]));

`ifdef FPGA_SYN_1THREAD
     dff_s #6 rid0_reg(.din (next_t0_rstid_i1[5:0]),
		   .q   (t0_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign  int_tlu_rstid_m[5:0] = t0_rstid_i2[5:0];
   
`else
 
   dp_mux2es #6 rid_mux1(.dout  (next_t1_rstid_i1[5:0]),
			 .in0   (t1_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[1]));
   
   dp_mux2es #6 rid_mux2(.dout  (next_t2_rstid_i1[5:0]),
			 .in0   (t2_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[2]));
   
   dp_mux2es #6 rid_mux3(.dout  (next_t3_rstid_i1[5:0]),
			 .in0   (t3_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[3]));


   dff_s #6 rid0_reg(.din (next_t0_rstid_i1[5:0]),
		   .q   (t0_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid1_reg(.din (next_t1_rstid_i1[5:0]),
		   .q   (t1_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid2_reg(.din (next_t2_rstid_i1[5:0]),
		   .q   (t2_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid3_reg(.din (next_t3_rstid_i1[5:0]),
		   .q   (t3_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   



   dp_mux4ds #6 tlurid_mux(.dout (int_tlu_rstid_m[5:0]),
			   .in0  (t0_rstid_i2[5:0]),
			   .in1  (t1_rstid_i2[5:0]),
			   .in2  (t2_rstid_i2[5:0]),
			   .in3  (t3_rstid_i2[5:0]),
			   .sel0_l (~inc_ind_thr_m[0]),
			   .sel1_l (~inc_ind_thr_m[1]),
			   .sel2_l (~inc_ind_thr_m[2]),
			   .sel3_l (~inc_ind_thr_m[3]));

`endif

   sparc_tlu_dec64 iv_dec(.in  (int_id_i1[5:0]),
			  .out (inrr_dec_i1[63:0]));


   assign  new_t0_inrr_i1 = inrr_dec_i1 | t0_inrr_arw_i1;
   assign  new_t1_inrr_i1 = inrr_dec_i1 | t1_inrr_arw_i1;
   assign  new_t2_inrr_i1 = inrr_dec_i1 | t2_inrr_arw_i1;
   assign  new_t3_inrr_i1 = inrr_dec_i1 | t3_inrr_arw_i1;


   dp_mux2es #64 inrr_en_mux0(.dout  (next_t0_inrr_i1[63:0]),
			  .in0   (t0_inrr_arw_i1[63:0]),
			  .in1   (new_t0_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[0]));
`ifdef FPGA_SYN_1THREAD


   dffr_s #64 t0_inrr (.din (next_t0_inrr_i1[63:0]),
		     .q   (t0_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   assign   inrr_rd_data_i2[63:0] = t0_inrr_i2[63:0];

`else
   
   dp_mux2es #64 inrr_en_mux1(.dout  (next_t1_inrr_i1[63:0]),
			  .in0   (t1_inrr_arw_i1[63:0]),
			  .in1   (new_t1_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[1]));
   dp_mux2es #64 inrr_en_mux2(.dout  (next_t2_inrr_i1[63:0]),
			  .in0   (t2_inrr_arw_i1[63:0]),
			  .in1   (new_t2_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[2]));
   dp_mux2es #64 inrr_en_mux3(.dout  (next_t3_inrr_i1[63:0]),
			  .in0   (t3_inrr_arw_i1[63:0]),
			  .in1   (new_t3_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[3]));



   dffr_s #64 t0_inrr (.din (next_t0_inrr_i1[63:0]),
		     .q   (t0_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t1_inrr (.din (next_t1_inrr_i1[63:0]),
		     .q   (t1_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t2_inrr (.din (next_t2_inrr_i1[63:0]),
		     .q   (t2_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t3_inrr (.din (next_t3_inrr_i1[63:0]),
		     .q   (t3_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());





   dp_mux4ds #64 inrr_rd_mux(.dout (inrr_rd_data_i2[63:0]),
			 .in0  (t0_inrr_i2[63:0]),
			 .in1  (t1_inrr_i2[63:0]),
			 .in2  (t2_inrr_i2[63:0]),
			 .in3  (t3_inrr_i2[63:0]),
			 .sel0_l (~inc_ind_asi_thr[0]),
			 .sel1_l (~inc_ind_asi_thr[1]),
			 .sel2_l (~inc_ind_asi_thr[2]),
			 .sel3_l (~inc_ind_asi_thr[3]));

`endif
		     

   sparc_tlu_zcmp64  zcmp0(.in  (t0_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[0]));

`ifdef FPGA_SYN_1THREAD
   assign t0_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[0]}});
   assign t0_inrr_aw_i2 = t0_inrr_i2 & t0_asi_wr_data;
   sparc_tlu_penc64 t0_invr_penc(.in  (t0_inrr_i2[63:0]),
				 .out (t0_invr_i2[5:0]));
   dff_s #6 t0_invr (.din (t0_invr_i2[5:0]),
		   .q   (t0_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign invr_rd_data_i3[5:0] = t0_invr_i3[5:0];
   
`else
   
   sparc_tlu_zcmp64  zcmp1(.in  (t1_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[1]));
   sparc_tlu_zcmp64  zcmp2(.in  (t2_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[2]));
   sparc_tlu_zcmp64  zcmp3(.in  (t3_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[3]));




   assign  t0_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[0]}});
   assign  t1_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[1]}});
   assign  t2_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[2]}});
   assign  t3_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[3]}});
   
   assign  t0_inrr_aw_i2 = t0_inrr_i2 & t0_asi_wr_data;
   assign  t1_inrr_aw_i2 = t1_inrr_i2 & t1_asi_wr_data;
   assign  t2_inrr_aw_i2 = t2_inrr_i2 & t2_asi_wr_data;
   assign  t3_inrr_aw_i2 = t3_inrr_i2 & t3_asi_wr_data;



   sparc_tlu_penc64 t0_invr_penc(.in  (t0_inrr_i2[63:0]),
				 .out (t0_invr_i2[5:0]));
   sparc_tlu_penc64 t1_invr_penc(.in  (t1_inrr_i2[63:0]),
				 .out (t1_invr_i2[5:0]));
   sparc_tlu_penc64 t2_invr_penc(.in  (t2_inrr_i2[63:0]),
				 .out (t2_invr_i2[5:0]));
   sparc_tlu_penc64 t3_invr_penc(.in  (t3_inrr_i2[63:0]),
				 .out (t3_invr_i2[5:0]));



   dff_s #6 t0_invr (.din (t0_invr_i2[5:0]),
		   .q   (t0_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t1_invr (.din (t1_invr_i2[5:0]),
		   .q   (t1_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t2_invr (.din (t2_invr_i2[5:0]),
		   .q   (t2_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t3_invr (.din (t3_invr_i2[5:0]),
		   .q   (t3_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());





   dp_mux4ds #6 invr_rd_mux(.dout (invr_rd_data_i3[5:0]),
			    .in0  (t0_invr_i3[5:0]),
			    .in1  (t1_invr_i3[5:0]),
			    .in2  (t2_invr_i3[5:0]),
			    .in3  (t3_invr_i3[5:0]),
			    .sel0_l (~inc_ind_asi_thr[0]),
			    .sel1_l (~inc_ind_asi_thr[1]),
			    .sel2_l (~inc_ind_asi_thr[2]),
			    .sel3_l (~inc_ind_asi_thr[3]));
`endif
   



   dp_mux4ds #(64) asi_rd_mux(
			   .in0  ({58'b0, invr_rd_data_i3[5:0]}),
			   .in1  (inrr_rd_data_i2[63:0]),
			   .in2  (tlu_scpd_asi_rdata_g[`TLU_SCPD_DATA_WIDTH-1:0]),
			   .in3  ({50'b0, tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0],6'b0}),
			   .sel0_l (~tlu_asi_rdata_mxsel_g[0]),
			   .sel1_l (~tlu_asi_rdata_mxsel_g[1]),
			   .sel2_l (~tlu_asi_rdata_mxsel_g[2]),
			   .sel3_l (~tlu_asi_rdata_mxsel_g[3]),
               .dout (int_tlu_asi_data[63:0]));

   dff_s #(64) dff_tlu_lsu_int_ldxa_data_w2 (
        .din (int_tlu_asi_data[63:0]),
		.q   (tlu_lsu_int_ldxa_data_w2[63:0]),
		.clk (clk),
		.se  (se), 
        .si(), 
        .so());
   
   sparc_tlu_dec64 inrr_pe_dec(.in  (invr_rd_data_i3[5:0]),
			       .out (pe_ivec_i3[63:0]));


   assign  t0_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[0]}};
   assign  t1_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[1]}};
   assign  t2_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[2]}};
   assign  t3_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[3]}};

   assign  t0_inrr_arw_i1 = t0_inrr_aw_i2 & ~t0_pe_ivec_i3;
   assign  t1_inrr_arw_i1 = t1_inrr_aw_i2 & ~t1_pe_ivec_i3;
   assign  t2_inrr_arw_i1 = t2_inrr_aw_i2 & ~t2_pe_ivec_i3;
   assign  t3_inrr_arw_i1 = t3_inrr_aw_i2 & ~t3_pe_ivec_i3;







   assign  indr_wr_pkt = {lsu_tlu_st_rs3_data_g[`INT_THR_HI:`INT_THR_LO], 
			  lsu_tlu_st_rs3_data_g[`INT_VEC_HI:`INT_VEC_LO]};




   
   dp_mux2es  #11   t0_indr_mux(.dout (t0_indr_next[10:0]),
				.in0  (t0_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[0]));
`ifdef FPGA_SYN_1THREAD
   dff_s #11 t0_indr_reg(.din (t0_indr_next[10:0]),
		   .q   (t0_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign  indr_pcxpkt[10:0] = t0_indr[10:0];
   
`else
   
   dp_mux2es  #11   t1_indr_mux(.dout (t1_indr_next[10:0]),
				.in0  (t1_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[1]));
   dp_mux2es  #11   t2_indr_mux(.dout (t2_indr_next[10:0]),
				.in0  (t2_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[2]));
   dp_mux2es  #11   t3_indr_mux(.dout (t3_indr_next[10:0]),
				.in0  (t3_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[3]));
   
   dff_s #11 t0_indr_reg(.din (t0_indr_next[10:0]),
		   .q   (t0_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t1_indr_reg(.din (t1_indr_next[10:0]),
		   .q   (t1_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t2_indr_reg(.din (t2_indr_next[10:0]),
		   .q   (t2_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t3_indr_reg(.din (t3_indr_next[10:0]),
		   .q   (t3_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());



   dp_mux4ds #11 int_dsp_mux(.dout (indr_pcxpkt[10:0]),
			     .in0  (t0_indr[10:0]),
			     .in1  (t1_indr[10:0]),
			     .in2  (t2_indr[10:0]),
			     .in3  (t3_indr[10:0]),
			     .sel0_l (~inc_ind_indr_grant[0]),
			     .sel1_l (~inc_ind_indr_grant[1]),
			     .sel2_l (~inc_ind_indr_grant[2]),
			     .sel3_l (~inc_ind_indr_grant[3]));
`endif
   
   
   assign  tlu_lsu_pcxpkt[25:0] = {inc_indr_req_valid,
				   {`INT_RQ},
				   inc_indr_req_thrid[1:0],

				   {2'b00},
				   3'b0,
				   indr_pcxpkt[10:6],
				   2'b0,
				   indr_pcxpkt[5:0]};
   


   
endmodule
module sparc_tlu_intdp (

   int_pending_i2_l, ind_inc_thrid_i1,
   ind_inc_type_i1, tlu_lsu_int_ldxa_data_w2, int_tlu_rstid_m, 
   tlu_lsu_pcxpkt, so, 




   rclk, se, si, tlu_rst_l, lsu_tlu_st_rs3_data_g,
   inc_ind_ld_int_i1, inc_ind_rstthr_i1, inc_ind_asi_thr, 
   inc_ind_asi_wr_indr, inc_ind_indr_grant,
   inc_ind_thr_m, inc_ind_asi_wr_inrr, inc_ind_asi_rd_invr, 
   inc_indr_req_valid, inc_indr_req_thrid, tlu_asi_rdata_mxsel_g,
   tlu_asi_queue_rdata_g, tlu_scpd_asi_rdata_g, lsu_ind_intpkt_id,
   lsu_ind_intpkt_type, lsu_ind_intpkt_thr 
   );





   input      rclk, se, si, tlu_rst_l;



   input [63:0]  lsu_tlu_st_rs3_data_g;


   input [3:0] 	 inc_ind_ld_int_i1;
   input [3:0] 	 inc_ind_rstthr_i1;
   


   input [3:0] 	 inc_ind_asi_thr;
   input [3:0] 	 inc_ind_asi_wr_indr;


   input [3:0] 	 inc_ind_indr_grant;




   input [3:0]	 inc_ind_thr_m;
   

   input [3:0] 	 inc_ind_asi_wr_inrr;
   input [3:0] 	 inc_ind_asi_rd_invr;
   

   input 	 inc_indr_req_valid;
   input [1:0] 	 inc_indr_req_thrid;


   input [3:0] tlu_asi_rdata_mxsel_g;

   input [`TLU_SCPD_DATA_WIDTH-1:0] tlu_scpd_asi_rdata_g;
   input [`TLU_ASI_QUE_WIDTH-1:0]   tlu_asi_queue_rdata_g;
   input [4:0]  lsu_ind_intpkt_thr;
   input [1:0]  lsu_ind_intpkt_type;
   input [5:0]  lsu_ind_intpkt_id;


   output [3:0]  int_pending_i2_l;


   output [4:0]  ind_inc_thrid_i1;
   output [1:0]  ind_inc_type_i1;
   

   output [63:0] tlu_lsu_int_ldxa_data_w2;
   output [5:0]  int_tlu_rstid_m;
   
   output [25:0] tlu_lsu_pcxpkt;
   
   output 	 so;




   wire local_rst;

   wire [63:0] int_tlu_asi_data;

   wire [5:0] 	 int_id_i1;
   wire [5:0] 	 t0_rstid_i2,
		 t1_rstid_i2,
		 t2_rstid_i2,
		 t3_rstid_i2,
		 next_t0_rstid_i1,
		 next_t1_rstid_i1,
		 next_t2_rstid_i1,
		 next_t3_rstid_i1;


   wire [63:0]	 inrr_dec_i1,
		 inrr_rd_data_i2;

   wire [63:0] 	 t0_inrr_i2,
 		 t1_inrr_i2,
		 t2_inrr_i2,
		 t3_inrr_i2,
		 t0_inrr_aw_i2,
		 t1_inrr_aw_i2,
		 t2_inrr_aw_i2,
		 t3_inrr_aw_i2,
		 t0_inrr_arw_i1,
		 t1_inrr_arw_i1,
		 t2_inrr_arw_i1,
		 t3_inrr_arw_i1,
		 next_t0_inrr_i1,
		 next_t1_inrr_i1,
		 next_t2_inrr_i1,
		 next_t3_inrr_i1;
   
   wire [63:0] 	 new_t0_inrr_i1,
		 new_t1_inrr_i1,
		 new_t2_inrr_i1,
		 new_t3_inrr_i1;


   wire [63:0]   t0_asi_wr_data,
		 t1_asi_wr_data,
		 t2_asi_wr_data,
		 t3_asi_wr_data;


   wire [5:0] 	 t0_invr_i3,
 		 t1_invr_i3,
 		 t2_invr_i3,
 		 t3_invr_i3,
    		 t0_invr_i2,
 		 t1_invr_i2,
 		 t2_invr_i2,
 		 t3_invr_i2;
   wire [5:0] 	 invr_rd_data_i3;


   wire [63:0] 	 pe_ivec_i3,
		 t0_pe_ivec_i3,
		 t1_pe_ivec_i3,
		 t2_pe_ivec_i3,
		 t3_pe_ivec_i3;




   wire [10:0] 	 indr_wr_pkt;



   wire [10:0] 	 indr_pcxpkt,
		 t0_indr,
		 t1_indr,
		 t2_indr,
		 t3_indr,
		 t0_indr_next,
		 t1_indr_next,
		 t2_indr_next,
		 t3_indr_next;


   wire clk;







   assign clk = rclk;






   assign local_rst = ~tlu_rst_l;
   




   assign  int_id_i1[5:0]        = lsu_ind_intpkt_id[5:0];
   assign  ind_inc_type_i1[1:0]  = lsu_ind_intpkt_type[1:0];
   assign  ind_inc_thrid_i1[4:0] = lsu_ind_intpkt_thr[4:0];


   dp_mux2es #6 rid_mux0(.dout  (next_t0_rstid_i1[5:0]),
			 .in0   (t0_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[0]));

`ifdef FPGA_SYN_1THREAD
     dff_s #6 rid0_reg(.din (next_t0_rstid_i1[5:0]),
		   .q   (t0_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign  int_tlu_rstid_m[5:0] = t0_rstid_i2[5:0];
   
`else
 
   dp_mux2es #6 rid_mux1(.dout  (next_t1_rstid_i1[5:0]),
			 .in0   (t1_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[1]));
   
   dp_mux2es #6 rid_mux2(.dout  (next_t2_rstid_i1[5:0]),
			 .in0   (t2_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[2]));
   
   dp_mux2es #6 rid_mux3(.dout  (next_t3_rstid_i1[5:0]),
			 .in0   (t3_rstid_i2[5:0]),
			 .in1   (int_id_i1[5:0]),
			 .sel   (inc_ind_rstthr_i1[3]));


   dff_s #6 rid0_reg(.din (next_t0_rstid_i1[5:0]),
		   .q   (t0_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid1_reg(.din (next_t1_rstid_i1[5:0]),
		   .q   (t1_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid2_reg(.din (next_t2_rstid_i1[5:0]),
		   .q   (t2_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 rid3_reg(.din (next_t3_rstid_i1[5:0]),
		   .q   (t3_rstid_i2[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   



   dp_mux4ds #6 tlurid_mux(.dout (int_tlu_rstid_m[5:0]),
			   .in0  (t0_rstid_i2[5:0]),
			   .in1  (t1_rstid_i2[5:0]),
			   .in2  (t2_rstid_i2[5:0]),
			   .in3  (t3_rstid_i2[5:0]),
			   .sel0_l (~inc_ind_thr_m[0]),
			   .sel1_l (~inc_ind_thr_m[1]),
			   .sel2_l (~inc_ind_thr_m[2]),
			   .sel3_l (~inc_ind_thr_m[3]));

`endif

   sparc_tlu_dec64 iv_dec(.in  (int_id_i1[5:0]),
			  .out (inrr_dec_i1[63:0]));


   assign  new_t0_inrr_i1 = inrr_dec_i1 | t0_inrr_arw_i1;
   assign  new_t1_inrr_i1 = inrr_dec_i1 | t1_inrr_arw_i1;
   assign  new_t2_inrr_i1 = inrr_dec_i1 | t2_inrr_arw_i1;
   assign  new_t3_inrr_i1 = inrr_dec_i1 | t3_inrr_arw_i1;


   dp_mux2es #64 inrr_en_mux0(.dout  (next_t0_inrr_i1[63:0]),
			  .in0   (t0_inrr_arw_i1[63:0]),
			  .in1   (new_t0_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[0]));
`ifdef FPGA_SYN_1THREAD


   dffr_s #64 t0_inrr (.din (next_t0_inrr_i1[63:0]),
		     .q   (t0_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   assign   inrr_rd_data_i2[63:0] = t0_inrr_i2[63:0];

`else
   
   dp_mux2es #64 inrr_en_mux1(.dout  (next_t1_inrr_i1[63:0]),
			  .in0   (t1_inrr_arw_i1[63:0]),
			  .in1   (new_t1_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[1]));
   dp_mux2es #64 inrr_en_mux2(.dout  (next_t2_inrr_i1[63:0]),
			  .in0   (t2_inrr_arw_i1[63:0]),
			  .in1   (new_t2_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[2]));
   dp_mux2es #64 inrr_en_mux3(.dout  (next_t3_inrr_i1[63:0]),
			  .in0   (t3_inrr_arw_i1[63:0]),
			  .in1   (new_t3_inrr_i1[63:0]),
			  .sel   (inc_ind_ld_int_i1[3]));



   dffr_s #64 t0_inrr (.din (next_t0_inrr_i1[63:0]),
		     .q   (t0_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t1_inrr (.din (next_t1_inrr_i1[63:0]),
		     .q   (t1_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t2_inrr (.din (next_t2_inrr_i1[63:0]),
		     .q   (t2_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());
   dffr_s #64 t3_inrr (.din (next_t3_inrr_i1[63:0]),
		     .q   (t3_inrr_i2[63:0]),
		     .clk (clk),



   		     .rst (local_rst),
		     .se  (se), .si(), .so());





   dp_mux4ds #64 inrr_rd_mux(.dout (inrr_rd_data_i2[63:0]),
			 .in0  (t0_inrr_i2[63:0]),
			 .in1  (t1_inrr_i2[63:0]),
			 .in2  (t2_inrr_i2[63:0]),
			 .in3  (t3_inrr_i2[63:0]),
			 .sel0_l (~inc_ind_asi_thr[0]),
			 .sel1_l (~inc_ind_asi_thr[1]),
			 .sel2_l (~inc_ind_asi_thr[2]),
			 .sel3_l (~inc_ind_asi_thr[3]));

`endif
		     

   sparc_tlu_zcmp64  zcmp0(.in  (t0_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[0]));

`ifdef FPGA_SYN_1THREAD
   assign t0_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[0]}});
   assign t0_inrr_aw_i2 = t0_inrr_i2 & t0_asi_wr_data;
   sparc_tlu_penc64 t0_invr_penc(.in  (t0_inrr_i2[63:0]),
				 .out (t0_invr_i2[5:0]));
   dff_s #6 t0_invr (.din (t0_invr_i2[5:0]),
		   .q   (t0_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign invr_rd_data_i3[5:0] = t0_invr_i3[5:0];
   
`else
   
   sparc_tlu_zcmp64  zcmp1(.in  (t1_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[1]));
   sparc_tlu_zcmp64  zcmp2(.in  (t2_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[2]));
   sparc_tlu_zcmp64  zcmp3(.in  (t3_inrr_i2[63:0]),
			   .zero (int_pending_i2_l[3]));




   assign  t0_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[0]}});
   assign  t1_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[1]}});
   assign  t2_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[2]}});
   assign  t3_asi_wr_data = ~(~lsu_tlu_st_rs3_data_g & 
			      {64{inc_ind_asi_wr_inrr[3]}});
   
   assign  t0_inrr_aw_i2 = t0_inrr_i2 & t0_asi_wr_data;
   assign  t1_inrr_aw_i2 = t1_inrr_i2 & t1_asi_wr_data;
   assign  t2_inrr_aw_i2 = t2_inrr_i2 & t2_asi_wr_data;
   assign  t3_inrr_aw_i2 = t3_inrr_i2 & t3_asi_wr_data;



   sparc_tlu_penc64 t0_invr_penc(.in  (t0_inrr_i2[63:0]),
				 .out (t0_invr_i2[5:0]));
   sparc_tlu_penc64 t1_invr_penc(.in  (t1_inrr_i2[63:0]),
				 .out (t1_invr_i2[5:0]));
   sparc_tlu_penc64 t2_invr_penc(.in  (t2_inrr_i2[63:0]),
				 .out (t2_invr_i2[5:0]));
   sparc_tlu_penc64 t3_invr_penc(.in  (t3_inrr_i2[63:0]),
				 .out (t3_invr_i2[5:0]));



   dff_s #6 t0_invr (.din (t0_invr_i2[5:0]),
		   .q   (t0_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t1_invr (.din (t1_invr_i2[5:0]),
		   .q   (t1_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t2_invr (.din (t2_invr_i2[5:0]),
		   .q   (t2_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #6 t3_invr (.din (t3_invr_i2[5:0]),
		   .q   (t3_invr_i3[5:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());





   dp_mux4ds #6 invr_rd_mux(.dout (invr_rd_data_i3[5:0]),
			    .in0  (t0_invr_i3[5:0]),
			    .in1  (t1_invr_i3[5:0]),
			    .in2  (t2_invr_i3[5:0]),
			    .in3  (t3_invr_i3[5:0]),
			    .sel0_l (~inc_ind_asi_thr[0]),
			    .sel1_l (~inc_ind_asi_thr[1]),
			    .sel2_l (~inc_ind_asi_thr[2]),
			    .sel3_l (~inc_ind_asi_thr[3]));
`endif
   



   dp_mux4ds #(64) asi_rd_mux(
			   .in0  ({58'b0, invr_rd_data_i3[5:0]}),
			   .in1  (inrr_rd_data_i2[63:0]),
			   .in2  (tlu_scpd_asi_rdata_g[`TLU_SCPD_DATA_WIDTH-1:0]),
			   .in3  ({50'b0, tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0],6'b0}),
			   .sel0_l (~tlu_asi_rdata_mxsel_g[0]),
			   .sel1_l (~tlu_asi_rdata_mxsel_g[1]),
			   .sel2_l (~tlu_asi_rdata_mxsel_g[2]),
			   .sel3_l (~tlu_asi_rdata_mxsel_g[3]),
               .dout (int_tlu_asi_data[63:0]));

   dff_s #(64) dff_tlu_lsu_int_ldxa_data_w2 (
        .din (int_tlu_asi_data[63:0]),
		.q   (tlu_lsu_int_ldxa_data_w2[63:0]),
		.clk (clk),
		.se  (se), 
        .si(), 
        .so());
   
   sparc_tlu_dec64 inrr_pe_dec(.in  (invr_rd_data_i3[5:0]),
			       .out (pe_ivec_i3[63:0]));


   assign  t0_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[0]}};
   assign  t1_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[1]}};
   assign  t2_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[2]}};
   assign  t3_pe_ivec_i3 = pe_ivec_i3 & {64{inc_ind_asi_rd_invr[3]}};

   assign  t0_inrr_arw_i1 = t0_inrr_aw_i2 & ~t0_pe_ivec_i3;
   assign  t1_inrr_arw_i1 = t1_inrr_aw_i2 & ~t1_pe_ivec_i3;
   assign  t2_inrr_arw_i1 = t2_inrr_aw_i2 & ~t2_pe_ivec_i3;
   assign  t3_inrr_arw_i1 = t3_inrr_aw_i2 & ~t3_pe_ivec_i3;







   assign  indr_wr_pkt = {lsu_tlu_st_rs3_data_g[`INT_THR_HI:`INT_THR_LO], 
			  lsu_tlu_st_rs3_data_g[`INT_VEC_HI:`INT_VEC_LO]};




   
   dp_mux2es  #11   t0_indr_mux(.dout (t0_indr_next[10:0]),
				.in0  (t0_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[0]));
`ifdef FPGA_SYN_1THREAD
   dff_s #11 t0_indr_reg(.din (t0_indr_next[10:0]),
		   .q   (t0_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   assign  indr_pcxpkt[10:0] = t0_indr[10:0];
   
`else
   
   dp_mux2es  #11   t1_indr_mux(.dout (t1_indr_next[10:0]),
				.in0  (t1_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[1]));
   dp_mux2es  #11   t2_indr_mux(.dout (t2_indr_next[10:0]),
				.in0  (t2_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[2]));
   dp_mux2es  #11   t3_indr_mux(.dout (t3_indr_next[10:0]),
				.in0  (t3_indr[10:0]),
				.in1  (indr_wr_pkt[10:0]),
				.sel  (inc_ind_asi_wr_indr[3]));
   
   dff_s #11 t0_indr_reg(.din (t0_indr_next[10:0]),
		   .q   (t0_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t1_indr_reg(.din (t1_indr_next[10:0]),
		   .q   (t1_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t2_indr_reg(.din (t2_indr_next[10:0]),
		   .q   (t2_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());
   dff_s #11 t3_indr_reg(.din (t3_indr_next[10:0]),
		   .q   (t3_indr[10:0]),
		   .clk (clk),
		   .se  (se), .si(), .so());



   dp_mux4ds #11 int_dsp_mux(.dout (indr_pcxpkt[10:0]),
			     .in0  (t0_indr[10:0]),
			     .in1  (t1_indr[10:0]),
			     .in2  (t2_indr[10:0]),
			     .in3  (t3_indr[10:0]),
			     .sel0_l (~inc_ind_indr_grant[0]),
			     .sel1_l (~inc_ind_indr_grant[1]),
			     .sel2_l (~inc_ind_indr_grant[2]),
			     .sel3_l (~inc_ind_indr_grant[3]));
`endif
   
   
   assign  tlu_lsu_pcxpkt[25:0] = {inc_indr_req_valid,
				   {`INT_RQ},
				   inc_indr_req_thrid[1:0],

				   {2'b00},
				   3'b0,
				   indr_pcxpkt[10:6],
				   2'b0,
				   indr_pcxpkt[5:0]};
   


   
endmodule