data/full_repos/permissive/425573648/fpga/seven_segment.v
data/verilator_xmls/7b9cd276-acce-46f2-a0ac-532d68a1eb77.xml
module seven_segment (
	input en,
	input [3:0]i,
	output reg [6:0]o
);


always@(*)
	begin
		if (en)
			begin
				case (i)

					4'b0000: o = 7'b0000001;
					4'b0001: o = 7'b1001111;
					4'b0010: o = 7'b0010010;
					4'b0011: o = 7'b0000110;
					4'b0100: o = 7'b1001100;
					4'b0101: o = 7'b0100100;
					4'b0110: o = 7'b0100000;
					4'b0111: o = 7'b0001111;
					4'b1000: o = 7'b0000000;
					4'b1001: o = 7'b0000100;
					
					
					default: o = 7'b1111111;
				endcase
			end
		else
			begin

				o = 7'b1111111;
			end
		
		
	end

endmodule
module seven_segment (
	input en,
	input [3:0]i,
	output reg [6:0]o
);



always@(*)
	begin
		if (en)
			begin
				case (i)

					4'b0000: o = 7'b0000001;
					4'b0001: o = 7'b1001111;
					4'b0010: o = 7'b0010010;
					4'b0011: o = 7'b0000110;
					4'b0100: o = 7'b1001100;
					4'b0101: o = 7'b0100100;
					4'b0110: o = 7'b0100000;
					4'b0111: o = 7'b0001111;
					4'b1000: o = 7'b0000000;
					4'b1001: o = 7'b0000100;
					
					
					default: o = 7'b1111111;
				endcase
			end
		else
			begin

				o = 7'b1111111;
			end
		
		
	end

endmodule