data/full_repos/permissive/518304577/iiitb_rv32i_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518304577/iiitb_rv32i_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clk=!clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/518304577/iiitb_rv32i_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n$dumpfile ("iiitb_rv32i.vcd");  \n^~~~~~~~~\n%Error: data/full_repos/permissive/518304577/iiitb_rv32i_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n$dumpvars (0, iiitb_rv32i_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518304577/iiitb_rv32i_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5 RN = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/518304577/iiitb_rv32i_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #300 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_rv32i_tb;

reg clk,RN;
wire [31:0]WB_OUT,NPC;

iiitb_rv32i rv32(clk,RN,NPC,WB_OUT);


always #3 clk=!clk;

initial begin 
RN  = 1'b1;
clk = 1'b1;

$dumpfile ("iiitb_rv32i.vcd");
$dumpvars (0, iiitb_rv32i_tb);
  
  #5 RN = 1'b0;
  
  #300 $finish;

end
endmodule
module iiitb_rv32i_tb;


reg clk,RN;
wire [31:0]WB_OUT,NPC;

iiitb_rv32i rv32(clk,RN,NPC,WB_OUT);


always #3 clk=!clk;

initial begin 
RN  = 1'b1;
clk = 1'b1;

$dumpfile ("iiitb_rv32i.vcd");
$dumpvars (0, iiitb_rv32i_tb);
  
  #5 RN = 1'b0;
  
  #300 $finish;

end
endmodule