data/full_repos/permissive/521337848/Hardware/procesor/inProcesor.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/inProcesor.v:16: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'bufexcp\'\nmodule bufexcp(\n       ^~~~~~~\n                                                                                         : ... Top module \'inselector\'\nmodule inselector(\n       ^~~~~~~~~~\n                                                                                         : ... Top module \'bufferIn\'\nmodule bufferIn(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module inselector(
	input clk,
	input rst,
	
	input insel,
	input[15:0] insIn1,
	input[15:0] insIn2,
	
	input saveExcp,
	input[15:0] timeIn,
	
	output reg[15:0] insIn
);

reg[15:0] f_insIn;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_insIn <= 0;
	end else
	begin
		f_insIn <= insIn;
	end
end

always@(*) begin

	insIn = f_insIn;
	
	if(insel) insIn = insIn2;
	else insIn = insIn1;
end

endmodule
module inselector(
	input clk,
	input rst,
	
	input insel,
	input[15:0] insIn1,
	input[15:0] insIn2,
	
	input saveExcp,
	input[15:0] timeIn,
	
	output reg[15:0] insIn
);


reg[15:0] f_insIn;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_insIn <= 0;
	end else
	begin
		f_insIn <= insIn;
	end
end

always@(*) begin

	insIn = f_insIn;
	
	if(insel) insIn = insIn2;
	else insIn = insIn1;
end

endmodule