data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #5 i_clk = ~i_clk ;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #20 clr = 1\'b1 ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\ninitial repeat (49) #10 sr = ~sr ;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\ninitial repeat (44) #10 sl = ~sl ;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #5 sel_mux = $random() ;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 in = $random() ;\n  ^\n%Error: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:35: Cannot find file containing module: \'universal_Shift_reg_top\'\nuniversal_Shift_reg_top DUT (\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/453449880,data/full_repos/permissive/453449880/universal_Shift_reg_top\n             data/full_repos/permissive/453449880,data/full_repos/permissive/453449880/universal_Shift_reg_top.v\n             data/full_repos/permissive/453449880,data/full_repos/permissive/453449880/universal_Shift_reg_top.sv\n             universal_Shift_reg_top\n             universal_Shift_reg_top.v\n             universal_Shift_reg_top.sv\n             obj_dir/universal_Shift_reg_top\n             obj_dir/universal_Shift_reg_top.v\n             obj_dir/universal_Shift_reg_top.sv\n%Warning-WIDTH: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:73: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                    : ... In instance universal_Shift_reg_top_tb\n  #5 sel_mux = $random() ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/453449880/universal_Shift_reg_top_tb.v:81: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                    : ... In instance universal_Shift_reg_top_tb\n  #10 in = $random() ;\n         ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module universal_Shift_reg_top_tb();
parameter DATA_WIDTH = 4  ;
parameter DATA_WIDTH1 = 2 ;
reg  i_clk  ;
reg clr ;
reg sr ;
reg sl ;
reg [DATA_WIDTH-1:0] in ;
wire  [DATA_WIDTH-1:0] q_out ;
reg [DATA_WIDTH1-1:0] sel_mux ;


universal_Shift_reg_top DUT (
i_clk ,
clr ,
in ,
sel_mux ,
sr, 
sl ,  
q_out  
);


initial 
  begin
  i_clk = 1'b0 ;
  clr = 1'b0 ;
  in = 4'b0000 ;
  sel_mux = 2'b00 ;
  sr = 1'b0 ;
  sl = 1'b0 ;
  end


always #5 i_clk = ~i_clk ;

initial
  begin
   #20 clr = 1'b1 ;
   end

initial repeat (49) #10 sr = ~sr ;
initial repeat (44) #10 sl = ~sl ;

integer i ;

initial
 begin
for (i = 0 ; i<40 ; i = i+ 1)
  begin
  #5 sel_mux = $random() ;
  end
  end
  
  initial
    begin
    for (i = 0 ; i<40 ; i = i+ 1)
  begin
  #10 in = $random() ;
  end
  end
  




endmodule
module universal_Shift_reg_top_tb();

parameter DATA_WIDTH = 4  ;
parameter DATA_WIDTH1 = 2 ;
reg  i_clk  ;
reg clr ;
reg sr ;
reg sl ;
reg [DATA_WIDTH-1:0] in ;
wire  [DATA_WIDTH-1:0] q_out ;
reg [DATA_WIDTH1-1:0] sel_mux ;


universal_Shift_reg_top DUT (
i_clk ,
clr ,
in ,
sel_mux ,
sr, 
sl ,  
q_out  
);


initial 
  begin
  i_clk = 1'b0 ;
  clr = 1'b0 ;
  in = 4'b0000 ;
  sel_mux = 2'b00 ;
  sr = 1'b0 ;
  sl = 1'b0 ;
  end


always #5 i_clk = ~i_clk ;

initial
  begin
   #20 clr = 1'b1 ;
   end

initial repeat (49) #10 sr = ~sr ;
initial repeat (44) #10 sl = ~sl ;

integer i ;

initial
 begin
for (i = 0 ; i<40 ; i = i+ 1)
  begin
  #5 sel_mux = $random() ;
  end
  end
  
  initial
    begin
    for (i = 0 ; i<40 ; i = i+ 1)
  begin
  #10 in = $random() ;
  end
  end
  




endmodule