data/full_repos/permissive/491573622/pc.v
data/verilator_xmls/c2bb8f7e-9aaa-44f3-a8e4-3e2583643b08.xml
module pc(
    input clk,
    input reset,
    input pcwr,
    input [31:0] npc,
    output reg [31:0] pc
    );
    initial
    begin
        pc <= 32'h00003000;
    end
    always@(posedge clk)
    begin
        if(reset)
            pc <= 32'h00003000;
        else if(pcwr)
            pc <= npc;
    end
endmodule
module pc(
    input clk,
    input reset,
    input pcwr,
    input [31:0] npc,
    output reg [31:0] pc
    );

    initial
    begin
        pc <= 32'h00003000;
    end
    always@(posedge clk)
    begin
        if(reset)
            pc <= 32'h00003000;
        else if(pcwr)
            pc <= npc;
    end
endmodule