data/full_repos/permissive/471089853/src/lzocshifter_6_to_6_counting_8_f400_uid18.v
data/verilator_xmls/1cd02f03-e1a5-4b89-99c0-eee4df392a71.xml
module LZOCShifter_6_to_6_counting_8_F400_uid18(clk, I, OZb, Count, O);
  reg _00_;
  wire _01_;
  wire _02_;
  wire [5:0] _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire [5:0] _07_;
  reg _08_;
  reg [5:0] _09_;
  reg _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire [5:0] _14_;
  wire _15_;
  output [2:0] Count;
  input [5:0] I;
  output [5:0] O;
  input OZb;
  input clk;
  wire count0;
  wire count1;
  wire count1_d1;
  wire count2;
  wire count2_d1;
  wire [5:0] level0;
  wire [5:0] level1;
  wire [5:0] level2;
  wire [5:0] level2_d1;
  wire [5:0] level3;
  wire [2:0] scount;
  wire sozb;
  wire sozb_d1;
  always @(posedge clk)
    _00_ <= sozb;
  always @(posedge clk)
    _08_ <= count2;
  always @(posedge clk)
    _09_ <= level2;
  always @(posedge clk)
    _10_ <= count1;
  assign _11_ = level3[5:2] == { sozb, sozb, sozb, sozb };
  assign _12_ = _11_ ? 1'h1 : 1'h0;
  assign _13_ = ~ count2;
  assign _14_ = _13_ ? level3 : { level3[1:0], 4'h0 };
  assign _15_ = level2[5:4] == { sozb, sozb };
  assign _01_ = _15_ ? 1'h1 : 1'h0;
  assign _02_ = ~ count1_d1;
  assign _03_ = _02_ ? level2_d1 : { level2_d1[3:0], 2'h0 };
  assign _04_ = level1[5] == sozb_d1;
  assign _05_ = _04_ ? 1'h1 : 1'h0;
  assign _06_ = ~ count0;
  assign _07_ = _06_ ? level1 : { level1[4:0], 1'h0 };
  assign level3 = I;
  assign sozb = OZb;
  assign sozb_d1 = _00_;
  assign count2 = _12_;
  assign count2_d1 = _08_;
  assign level2 = _14_;
  assign level2_d1 = _09_;
  assign count1 = _01_;
  assign count1_d1 = _10_;
  assign level1 = _03_;
  assign count0 = _05_;
  assign level0 = _07_;
  assign scount = { count2_d1, count1_d1, count0 };
  assign Count = scount;
  assign O = level0;
endmodule
module LZOCShifter_6_to_6_counting_8_F400_uid18(clk, I, OZb, Count, O);

  reg _00_;
  wire _01_;
  wire _02_;
  wire [5:0] _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire [5:0] _07_;
  reg _08_;
  reg [5:0] _09_;
  reg _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire [5:0] _14_;
  wire _15_;
  output [2:0] Count;
  input [5:0] I;
  output [5:0] O;
  input OZb;
  input clk;
  wire count0;
  wire count1;
  wire count1_d1;
  wire count2;
  wire count2_d1;
  wire [5:0] level0;
  wire [5:0] level1;
  wire [5:0] level2;
  wire [5:0] level2_d1;
  wire [5:0] level3;
  wire [2:0] scount;
  wire sozb;
  wire sozb_d1;
  always @(posedge clk)
    _00_ <= sozb;
  always @(posedge clk)
    _08_ <= count2;
  always @(posedge clk)
    _09_ <= level2;
  always @(posedge clk)
    _10_ <= count1;
  assign _11_ = level3[5:2] == { sozb, sozb, sozb, sozb };
  assign _12_ = _11_ ? 1'h1 : 1'h0;
  assign _13_ = ~ count2;
  assign _14_ = _13_ ? level3 : { level3[1:0], 4'h0 };
  assign _15_ = level2[5:4] == { sozb, sozb };
  assign _01_ = _15_ ? 1'h1 : 1'h0;
  assign _02_ = ~ count1_d1;
  assign _03_ = _02_ ? level2_d1 : { level2_d1[3:0], 2'h0 };
  assign _04_ = level1[5] == sozb_d1;
  assign _05_ = _04_ ? 1'h1 : 1'h0;
  assign _06_ = ~ count0;
  assign _07_ = _06_ ? level1 : { level1[4:0], 1'h0 };
  assign level3 = I;
  assign sozb = OZb;
  assign sozb_d1 = _00_;
  assign count2 = _12_;
  assign count2_d1 = _08_;
  assign level2 = _14_;
  assign level2_d1 = _09_;
  assign count1 = _01_;
  assign count1_d1 = _10_;
  assign level1 = _03_;
  assign count0 = _05_;
  assign level0 = _07_;
  assign scount = { count2_d1, count1_d1, count0 };
  assign Count = scount;
  assign O = level0;
endmodule