data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v
1: b'%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:39: Cannot find include file: Sdram_Params.h\n`include        "Sdram_Params.h" \n                ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498667445/Camera/V_Sdram_Control,data/full_repos/permissive/498667445/Sdram_Params.h\n             data/full_repos/permissive/498667445/Camera/V_Sdram_Control,data/full_repos/permissive/498667445/Sdram_Params.h.v\n             data/full_repos/permissive/498667445/Camera/V_Sdram_Control,data/full_repos/permissive/498667445/Sdram_Params.h.sv\n             Sdram_Params.h\n             Sdram_Params.h.v\n             Sdram_Params.h.sv\n             obj_dir/Sdram_Params.h\n             obj_dir/Sdram_Params.h.v\n             obj_dir/Sdram_Params.h.sv\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:45: Define or directive not defined: \'`DSIZE\'\ninput   [`DSIZE-1:0]            WR_DATA;                \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:47: Define or directive not defined: \'`ASIZE\'\ninput   [`ASIZE-1:0]        WR_ADDR;     \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:48: Define or directive not defined: \'`ASIZE\'\ninput   [`ASIZE-1:0]        WR_MAX_ADDR;    \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:56: Define or directive not defined: \'`DSIZE\'\noutput  [`DSIZE-1:0]            RD_DATA;                \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:58: Define or directive not defined: \'`ASIZE\'\ninput   [`ASIZE-1:0]        RD_ADDR;     \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:59: Define or directive not defined: \'`ASIZE\'\ninput   [`ASIZE-1:0]        RD_MAX_ADDR;    \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:66: Define or directive not defined: \'`SASIZE\'\noutput  [`SASIZE-1:0]           SA;                      \n         ^~~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:73: Define or directive not defined: \'`DSIZE\'\ninout   [`DSIZE-1:0]            DQ;                      \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:74: Define or directive not defined: \'`DSIZE\'\noutput  [`DSIZE/8-1:0]          DQM;                     \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:74: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\noutput  [`DSIZE/8-1:0]          DQM;                     \n               ^\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:78: Define or directive not defined: \'`ASIZE\'\nreg  [`ASIZE-1:0]     mADDR;      \n      ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:80: Define or directive not defined: \'`ASIZE\'\nreg  [`ASIZE-1:0]     rWR_ADDR;     \n      ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:82: Define or directive not defined: \'`ASIZE\'\nreg  [`ASIZE-1:0]    rRD_ADDR;     \n      ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:95: Define or directive not defined: \'`DSIZE\'\nreg     [`DSIZE-1:0]         mDATAOUT;                \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:97: Define or directive not defined: \'`DSIZE\'\nwire    [`DSIZE-1:0]           mDATAIN;                 \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:100: Define or directive not defined: \'`DSIZE\'\nreg   [`DSIZE/8-1:0]            DQM;                     \n       ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:100: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\nreg   [`DSIZE/8-1:0]            DQM;                     \n             ^\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:101: Define or directive not defined: \'`SASIZE\'\nreg     [`SASIZE-1:0]           SA;                      \n         ^~~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:108: Define or directive not defined: \'`DSIZE\'\nwire    [`DSIZE-1:0]            DQOUT;      \n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:109: Define or directive not defined: \'`DSIZE\'\nwire   [`DSIZE/8-1:0]         IDQM;                    \n        ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:109: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\nwire   [`DSIZE/8-1:0]         IDQM;                    \n              ^\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:110: Define or directive not defined: \'`SASIZE\'\nwire    [`SASIZE-1:0]           ISA;                     \n         ^~~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:124: Define or directive not defined: \'`ASIZE\'\nwire    [`ASIZE-1:0]            saddr;\n         ^~~~~~\n%Error: data/full_repos/permissive/498667445/Camera/V_Sdram_Control/Sdram_Control.v:264: Define or directive not defined: \'`DSIZE\'\nassign  DQ = oe ? DQOUT : `DSIZE\'hzzzz;\n                          ^~~~~~\n%Error: Exiting due to 25 error(s)\n'
module Sdram_Control(

      REF_CLK,
      RESET_N,
		CLK,

      WR_DATA,
		WR,
		WR_ADDR,
		WR_MAX_ADDR,
		WR_LENGTH,
		WR_LOAD,
		WR_CLK,
		WR_FULL,
		WR_USE,

      RD_DATA,
		RD,
		RD_ADDR,
		RD_MAX_ADDR,
		RD_LENGTH,
		RD_LOAD,	
		RD_CLK,
		RD_EMPTY,
		RD_USE,

        SA,
        BA,
        CS_N,
        CKE,
        RAS_N,
        CAS_N,
        WE_N,
        DQ,
        DQM
        );


`include        "Sdram_Params.h"

input                           REF_CLK;
input                           RESET_N;


input   [`DSIZE-1:0]            WR_DATA;
input							        WR;
input	  [`ASIZE-1:0]			     WR_ADDR;
input	  [`ASIZE-1:0]			     WR_MAX_ADDR;
input	  [8:0]					     WR_LENGTH;
input							        WR_LOAD;
input							        WR_CLK;
output							     WR_FULL;
output  [15:0]					     WR_USE;


output  [`DSIZE-1:0]            RD_DATA;
input							        RD;
input	  [`ASIZE-1:0]			     RD_ADDR;
input	  [`ASIZE-1:0]			     RD_MAX_ADDR;
input	  [8:0]					     RD_LENGTH;
input							        RD_LOAD;
input							        RD_CLK;
output							     RD_EMPTY;
output	[15:0]					  RD_USE;

output  [`SASIZE-1:0]           SA;
output  [1:0]                   BA;
output  [1:0]                   CS_N;
output                          CKE;
output                          RAS_N;
output                          CAS_N;
output                          WE_N;
inout   [`DSIZE-1:0]            DQ;
output  [`DSIZE/8-1:0]          DQM;



reg		[`ASIZE-1:0]			  mADDR;
reg		[8:0]					     mLENGTH;
reg		[`ASIZE-1:0]			  rWR_ADDR;
				
reg		[`ASIZE-1:0]			 rRD_ADDR;
reg							       WR_MASK;
reg							       RD_MASK;
reg								    mWR_DONE;
reg								    mRD_DONE;
reg								    mWR,Pre_WR;
reg								    mRD,Pre_RD;
reg 	[9:0] 					    ST;
reg		[1:0] 					 CMD;
reg								    PM_STOP;
reg								    PM_DONE;
reg								    Read;
reg								    Write;
reg	    [`DSIZE-1:0]         mDATAOUT;

wire    [`DSIZE-1:0]           mDATAIN;
wire                           CMDACK;

reg  	[`DSIZE/8-1:0]            DQM;
reg     [`SASIZE-1:0]           SA;
reg     [1:0]                   BA;
reg     [1:0]                   CS_N;
reg                             CKE;
reg                             RAS_N;
reg                             CAS_N;
reg                             WE_N;
wire    [`DSIZE-1:0]            DQOUT;
wire  	[`DSIZE/8-1:0]         IDQM;
wire    [`SASIZE-1:0]           ISA;
wire    [1:0]                   IBA;
wire    [1:0]                   ICS_N;
wire                            ICKE;
wire                            IRAS_N;
wire                            ICAS_N;
wire                            IWE_N;

reg								OUT_VALID;
reg								IN_REQ;
wire	[15:0]					write_side_fifo_rusedw;
wire	[15:0]					read_side_fifo_wusedw;


wire    [`ASIZE-1:0]            saddr;
wire                            load_mode;
wire                            nop;
wire                            reada;
wire                            writea;
wire                            refresh;
wire                            precharge;
wire                            oe;
wire							ref_ack;
wire							ref_req;
wire							init_req;
wire							cm_ack;
wire							active;
input                  CLK;

	







		







control_interface control1 (                                                                                                                               
                .CLK(CLK),
                .RESET_N(RESET_N),
                .CMD(CMD),
                .ADDR(mADDR),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
                .PRECHARGE(precharge),
                .LOAD_MODE(load_mode),
                .SADDR(saddr),
                .REF_REQ(ref_req),
				    .INIT_REQ(init_req),
                .CMD_ACK(CMDACK)
                );

command command1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .SADDR(saddr),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
				    .LOAD_MODE(load_mode),
                .PRECHARGE(precharge),
                .REF_REQ(ref_req),
				    .INIT_REQ(init_req),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .OE(oe),
				    .PM_STOP(PM_STOP),
				    .PM_DONE(PM_DONE),
                .SA(ISA),
                .BA(IBA),
                .CS_N(ICS_N),
                .CKE(ICKE),
                .RAS_N(IRAS_N),
                .CAS_N(ICAS_N),
                .WE_N(IWE_N)
                );
                
sdr_data_path data_path1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .DATAIN(mDATAIN),
                .DM(2'b00),
                .DQOUT(DQOUT),
                .DQM(IDQM)
                );

Sdram_WR_FIFO 	write_fifo1(
				.data(WR_DATA),
				.wrreq(WR),
				.wrclk(WR_CLK),
				.aclr(WR_LOAD),
				.rdreq(IN_REQ&WR_MASK),
				.rdclk(CLK),
				.q(mDATAIN),
				.wrfull(WR_FULL),
				.wrusedw(WR_USE),
				.rdusedw(write_side_fifo_rusedw)
				);
				
reg flag;	 
always@(posedge CLK or negedge RESET_N)
begin
 if(!RESET_N)
 flag	<=	0;
 else
 begin
  if(write_side_fifo_rusedw==WR_LENGTH)
  flag	<=	1;
 end
end				


Sdram_RD_FIFO 	read_fifo1(
				.data(mDATAOUT),
				.wrreq(OUT_VALID&RD_MASK),
				.wrclk(CLK),
				.aclr(RD_LOAD),
				.rdreq(RD),
				.rdclk(RD_CLK),
				.q(RD_DATA),
				.wrusedw(read_side_fifo_wusedw),
				.rdempty(RD_EMPTY),
				.rdusedw(RD_USE)
				);
				

always @(posedge CLK)
begin
	SA      <= (ST==SC_CL+mLENGTH)			?	13'h200	:	ISA;
    BA      <= IBA;
    CS_N    <= ICS_N;
    CKE     <= ICKE;
    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
	mDATAOUT<= DQ;
end

assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
assign	active	=	Read | Write;

always@(posedge CLK or negedge RESET_N)
begin
	if(RESET_N==0)
	begin
		CMD			<=  0;
		ST			<=  0;
		Pre_RD		<=  0;
		Pre_WR		<=  0;
		Read		<=	0;
		Write		<=	0;
		OUT_VALID	<=	0;
		IN_REQ		<=	0;
		mWR_DONE	<=	0;
		mRD_DONE	<=	0;
	end
	else
	begin
		Pre_RD	<=	mRD;
		Pre_WR	<=	mWR;
		case(ST)
		0:	begin
				if({Pre_RD,mRD}==2'b01)
				begin
					Read	<=	1;
					Write	<=	0;
					CMD		<=	2'b01;
					ST		<=	1;
				end
				else if({Pre_WR,mWR}==2'b01)
				begin
					Read	<=	0;
					Write	<=	1;
					CMD		<=	2'b10;
					ST		<=	1;
				end
			end
		1:	begin
				if(CMDACK==1)
				begin
					CMD<=2'b00;
					ST<=2;
				end
			end
		default:	
			begin	
				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
				ST<=ST+1;
				else
				ST<=0;
			end
		endcase
	
		if(Read)
		begin
			if(ST==SC_CL+SC_RCD+1)
			OUT_VALID	<=	1;
			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
			begin
				OUT_VALID	<=	0;
				Read		<=	0;
				mRD_DONE	<=	1;
			end
		end
		else
		mRD_DONE	<=	0;
		
		if(Write)
		begin
			if(ST==SC_CL-1)
			IN_REQ	<=	1;
			else if(ST==SC_CL+mLENGTH-1)
			IN_REQ	<=	0;
			else if(ST==SC_CL+SC_RCD+mLENGTH)
			begin
				Write	<=	0;
				mWR_DONE<=	1;
			end
		end
		else
		mWR_DONE<=	0;

	end
end

always@(posedge CLK or negedge RESET_N)
begin
	if(!RESET_N)
	begin
		rWR_ADDR		<=	WR_ADDR;
		rRD_ADDR		<=	RD_ADDR;
	end
	else
	begin

		if(WR_LOAD)
			rWR_ADDR	<=	WR_ADDR;
		else if(mWR_DONE&WR_MASK)
		begin
			if(rWR_ADDR<WR_MAX_ADDR-WR_LENGTH)
			rWR_ADDR	<=	rWR_ADDR+WR_LENGTH;
			else
			rWR_ADDR	<=	WR_ADDR;
		end


		if(RD_LOAD)
			rRD_ADDR	<=	RD_ADDR;
		else if(mRD_DONE&RD_MASK)
		begin
			if(rRD_ADDR<RD_MAX_ADDR-RD_LENGTH)
			rRD_ADDR	<=	rRD_ADDR+RD_LENGTH;
			else
			rRD_ADDR	<=	RD_ADDR;
		end
	end
end

always@(posedge CLK or negedge RESET_N)
begin
	if(!RESET_N)
	begin
		mWR		<=	0;
		mRD		<=	0;
		mADDR	<=	0;
		mLENGTH	<=	0;
		WR_MASK <=	0;
		RD_MASK <=	0;
	end
	else
	begin
		if( (mWR==0) && (mRD==0) && (ST==0) &&
			(WR_MASK==0)	&&	(RD_MASK==0) &&
			(WR_LOAD==0)	&&	(RD_LOAD==0) &&(flag==1) )
		begin
		

			 if( (write_side_fifo_rusedw >= WR_LENGTH) && (WR_LENGTH!=0) )
			begin
				mADDR	<=	rWR_ADDR;
				mLENGTH	<=	WR_LENGTH;
				WR_MASK	<=	1'b1;
				RD_MASK	<=	1'b0;
				mWR		<=	1;
				mRD		<=	0;
			end

			else if( (read_side_fifo_wusedw < RD_LENGTH) )
			begin
				mADDR	<=	rRD_ADDR;
				mLENGTH	<=	RD_LENGTH;
				WR_MASK	<=	1'b0;
				RD_MASK	<=	1'b1;
				mWR		<=	0;
				mRD		<=	1;				
			end

		end
		if(mWR_DONE)
		begin
			WR_MASK	<=	0;
			mWR		<=	0;
		end
		if(mRD_DONE)
		begin
			RD_MASK	<=	0;
			mRD		<=	0;
		end
	end
end

endmodule
module Sdram_Control(

      REF_CLK,
      RESET_N,
		CLK,

      WR_DATA,
		WR,
		WR_ADDR,
		WR_MAX_ADDR,
		WR_LENGTH,
		WR_LOAD,
		WR_CLK,
		WR_FULL,
		WR_USE,

      RD_DATA,
		RD,
		RD_ADDR,
		RD_MAX_ADDR,
		RD_LENGTH,
		RD_LOAD,	
		RD_CLK,
		RD_EMPTY,
		RD_USE,

        SA,
        BA,
        CS_N,
        CKE,
        RAS_N,
        CAS_N,
        WE_N,
        DQ,
        DQM
        );



`include        "Sdram_Params.h"

input                           REF_CLK;
input                           RESET_N;


input   [`DSIZE-1:0]            WR_DATA;
input							        WR;
input	  [`ASIZE-1:0]			     WR_ADDR;
input	  [`ASIZE-1:0]			     WR_MAX_ADDR;
input	  [8:0]					     WR_LENGTH;
input							        WR_LOAD;
input							        WR_CLK;
output							     WR_FULL;
output  [15:0]					     WR_USE;


output  [`DSIZE-1:0]            RD_DATA;
input							        RD;
input	  [`ASIZE-1:0]			     RD_ADDR;
input	  [`ASIZE-1:0]			     RD_MAX_ADDR;
input	  [8:0]					     RD_LENGTH;
input							        RD_LOAD;
input							        RD_CLK;
output							     RD_EMPTY;
output	[15:0]					  RD_USE;

output  [`SASIZE-1:0]           SA;
output  [1:0]                   BA;
output  [1:0]                   CS_N;
output                          CKE;
output                          RAS_N;
output                          CAS_N;
output                          WE_N;
inout   [`DSIZE-1:0]            DQ;
output  [`DSIZE/8-1:0]          DQM;



reg		[`ASIZE-1:0]			  mADDR;
reg		[8:0]					     mLENGTH;
reg		[`ASIZE-1:0]			  rWR_ADDR;
				
reg		[`ASIZE-1:0]			 rRD_ADDR;
reg							       WR_MASK;
reg							       RD_MASK;
reg								    mWR_DONE;
reg								    mRD_DONE;
reg								    mWR,Pre_WR;
reg								    mRD,Pre_RD;
reg 	[9:0] 					    ST;
reg		[1:0] 					 CMD;
reg								    PM_STOP;
reg								    PM_DONE;
reg								    Read;
reg								    Write;
reg	    [`DSIZE-1:0]         mDATAOUT;

wire    [`DSIZE-1:0]           mDATAIN;
wire                           CMDACK;

reg  	[`DSIZE/8-1:0]            DQM;
reg     [`SASIZE-1:0]           SA;
reg     [1:0]                   BA;
reg     [1:0]                   CS_N;
reg                             CKE;
reg                             RAS_N;
reg                             CAS_N;
reg                             WE_N;
wire    [`DSIZE-1:0]            DQOUT;
wire  	[`DSIZE/8-1:0]         IDQM;
wire    [`SASIZE-1:0]           ISA;
wire    [1:0]                   IBA;
wire    [1:0]                   ICS_N;
wire                            ICKE;
wire                            IRAS_N;
wire                            ICAS_N;
wire                            IWE_N;

reg								OUT_VALID;
reg								IN_REQ;
wire	[15:0]					write_side_fifo_rusedw;
wire	[15:0]					read_side_fifo_wusedw;


wire    [`ASIZE-1:0]            saddr;
wire                            load_mode;
wire                            nop;
wire                            reada;
wire                            writea;
wire                            refresh;
wire                            precharge;
wire                            oe;
wire							ref_ack;
wire							ref_req;
wire							init_req;
wire							cm_ack;
wire							active;
input                  CLK;

	







		







control_interface control1 (                                                                                                                               
                .CLK(CLK),
                .RESET_N(RESET_N),
                .CMD(CMD),
                .ADDR(mADDR),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
                .PRECHARGE(precharge),
                .LOAD_MODE(load_mode),
                .SADDR(saddr),
                .REF_REQ(ref_req),
				    .INIT_REQ(init_req),
                .CMD_ACK(CMDACK)
                );

command command1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .SADDR(saddr),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
				    .LOAD_MODE(load_mode),
                .PRECHARGE(precharge),
                .REF_REQ(ref_req),
				    .INIT_REQ(init_req),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .OE(oe),
				    .PM_STOP(PM_STOP),
				    .PM_DONE(PM_DONE),
                .SA(ISA),
                .BA(IBA),
                .CS_N(ICS_N),
                .CKE(ICKE),
                .RAS_N(IRAS_N),
                .CAS_N(ICAS_N),
                .WE_N(IWE_N)
                );
                
sdr_data_path data_path1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .DATAIN(mDATAIN),
                .DM(2'b00),
                .DQOUT(DQOUT),
                .DQM(IDQM)
                );

Sdram_WR_FIFO 	write_fifo1(
				.data(WR_DATA),
				.wrreq(WR),
				.wrclk(WR_CLK),
				.aclr(WR_LOAD),
				.rdreq(IN_REQ&WR_MASK),
				.rdclk(CLK),
				.q(mDATAIN),
				.wrfull(WR_FULL),
				.wrusedw(WR_USE),
				.rdusedw(write_side_fifo_rusedw)
				);
				
reg flag;	 
always@(posedge CLK or negedge RESET_N)
begin
 if(!RESET_N)
 flag	<=	0;
 else
 begin
  if(write_side_fifo_rusedw==WR_LENGTH)
  flag	<=	1;
 end
end				


Sdram_RD_FIFO 	read_fifo1(
				.data(mDATAOUT),
				.wrreq(OUT_VALID&RD_MASK),
				.wrclk(CLK),
				.aclr(RD_LOAD),
				.rdreq(RD),
				.rdclk(RD_CLK),
				.q(RD_DATA),
				.wrusedw(read_side_fifo_wusedw),
				.rdempty(RD_EMPTY),
				.rdusedw(RD_USE)
				);
				

always @(posedge CLK)
begin
	SA      <= (ST==SC_CL+mLENGTH)			?	13'h200	:	ISA;
    BA      <= IBA;
    CS_N    <= ICS_N;
    CKE     <= ICKE;
    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
	mDATAOUT<= DQ;
end

assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
assign	active	=	Read | Write;

always@(posedge CLK or negedge RESET_N)
begin
	if(RESET_N==0)
	begin
		CMD			<=  0;
		ST			<=  0;
		Pre_RD		<=  0;
		Pre_WR		<=  0;
		Read		<=	0;
		Write		<=	0;
		OUT_VALID	<=	0;
		IN_REQ		<=	0;
		mWR_DONE	<=	0;
		mRD_DONE	<=	0;
	end
	else
	begin
		Pre_RD	<=	mRD;
		Pre_WR	<=	mWR;
		case(ST)
		0:	begin
				if({Pre_RD,mRD}==2'b01)
				begin
					Read	<=	1;
					Write	<=	0;
					CMD		<=	2'b01;
					ST		<=	1;
				end
				else if({Pre_WR,mWR}==2'b01)
				begin
					Read	<=	0;
					Write	<=	1;
					CMD		<=	2'b10;
					ST		<=	1;
				end
			end
		1:	begin
				if(CMDACK==1)
				begin
					CMD<=2'b00;
					ST<=2;
				end
			end
		default:	
			begin	
				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
				ST<=ST+1;
				else
				ST<=0;
			end
		endcase
	
		if(Read)
		begin
			if(ST==SC_CL+SC_RCD+1)
			OUT_VALID	<=	1;
			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
			begin
				OUT_VALID	<=	0;
				Read		<=	0;
				mRD_DONE	<=	1;
			end
		end
		else
		mRD_DONE	<=	0;
		
		if(Write)
		begin
			if(ST==SC_CL-1)
			IN_REQ	<=	1;
			else if(ST==SC_CL+mLENGTH-1)
			IN_REQ	<=	0;
			else if(ST==SC_CL+SC_RCD+mLENGTH)
			begin
				Write	<=	0;
				mWR_DONE<=	1;
			end
		end
		else
		mWR_DONE<=	0;

	end
end

always@(posedge CLK or negedge RESET_N)
begin
	if(!RESET_N)
	begin
		rWR_ADDR		<=	WR_ADDR;
		rRD_ADDR		<=	RD_ADDR;
	end
	else
	begin

		if(WR_LOAD)
			rWR_ADDR	<=	WR_ADDR;
		else if(mWR_DONE&WR_MASK)
		begin
			if(rWR_ADDR<WR_MAX_ADDR-WR_LENGTH)
			rWR_ADDR	<=	rWR_ADDR+WR_LENGTH;
			else
			rWR_ADDR	<=	WR_ADDR;
		end


		if(RD_LOAD)
			rRD_ADDR	<=	RD_ADDR;
		else if(mRD_DONE&RD_MASK)
		begin
			if(rRD_ADDR<RD_MAX_ADDR-RD_LENGTH)
			rRD_ADDR	<=	rRD_ADDR+RD_LENGTH;
			else
			rRD_ADDR	<=	RD_ADDR;
		end
	end
end

always@(posedge CLK or negedge RESET_N)
begin
	if(!RESET_N)
	begin
		mWR		<=	0;
		mRD		<=	0;
		mADDR	<=	0;
		mLENGTH	<=	0;
		WR_MASK <=	0;
		RD_MASK <=	0;
	end
	else
	begin
		if( (mWR==0) && (mRD==0) && (ST==0) &&
			(WR_MASK==0)	&&	(RD_MASK==0) &&
			(WR_LOAD==0)	&&	(RD_LOAD==0) &&(flag==1) )
		begin
		

			 if( (write_side_fifo_rusedw >= WR_LENGTH) && (WR_LENGTH!=0) )
			begin
				mADDR	<=	rWR_ADDR;
				mLENGTH	<=	WR_LENGTH;
				WR_MASK	<=	1'b1;
				RD_MASK	<=	1'b0;
				mWR		<=	1;
				mRD		<=	0;
			end

			else if( (read_side_fifo_wusedw < RD_LENGTH) )
			begin
				mADDR	<=	rRD_ADDR;
				mLENGTH	<=	RD_LENGTH;
				WR_MASK	<=	1'b0;
				RD_MASK	<=	1'b1;
				mWR		<=	0;
				mRD		<=	1;				
			end

		end
		if(mWR_DONE)
		begin
			WR_MASK	<=	0;
			mWR		<=	0;
		end
		if(mRD_DONE)
		begin
			RD_MASK	<=	0;
			mRD		<=	0;
		end
	end
end

endmodule