data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleCaseClassModule/reference/SimpleCaseClassModule.v
data/verilator_xmls/af4df54e-20ce-417a-83fc-afc7864a0499.xml
module SimpleCaseClassModule(
    input clock,
    input reset,
    input [4:0] io_in_underlying,
    output [4:0] io_out_underlying
);
    wire [4:0] _register1_underlying__q;
    wire [4:0] _register1_underlying__d;
    DFF_POSCLK #(.width(5)) register1_underlying (
        .q(_register1_underlying__q),
        .d(_register1_underlying__d),
        .clk(clock)
    );
    assign io_out_underlying = _register1_underlying__q;
    assign _register1_underlying__d = io_in_underlying;
endmodule
module SimpleCaseClassModule(
    input clock,
    input reset,
    input [4:0] io_in_underlying,
    output [4:0] io_out_underlying
);

    wire [4:0] _register1_underlying__q;
    wire [4:0] _register1_underlying__d;
    DFF_POSCLK #(.width(5)) register1_underlying (
        .q(_register1_underlying__q),
        .d(_register1_underlying__d),
        .clk(clock)
    );
    assign io_out_underlying = _register1_underlying__q;
    assign _register1_underlying__d = io_in_underlying;
endmodule