data/full_repos/permissive/419984230/tests/sipo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/sipo_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #90;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/sipo_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/sipo_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/sipo_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/sipo_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/419984230/tests/sipo_tb.v:20: Cannot find file containing module: \'sipo\'\n sipo uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/sipo\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/sipo.v\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/sipo.sv\n             sipo\n             sipo.v\n             sipo.sv\n             obj_dir/sipo\n             obj_dir/sipo.v\n             obj_dir/sipo.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sipo_tb;


	reg en;
	reg clk;
	reg din;
	reg rst;
	reg [1:0] mode;
	integer i;
	integer j;
	reg [69:0] data [13:0];


	wire load;
	wire [69:0] dout;
	wire [3:0]  row;


	sipo uut (
		.en(en), 
		.clk(clk), 
		.din(din), 
		.rst(rst), 

		.load(load), 
		.dout(dout),
		.row(row)
	);
	
	initial begin

		en = 0;	mode = 2'b01;
		data [0] = 70'h204016000000000000;
		data [1] = 70'h004023000000000000;
		data [2] = 70'h0040234CCCC0000000;
		data [3] = 70'h003FD06C4C5974E65C;
		data [4] = 70'h0040B41E83DD97F62B;
		data [5] = 70'h00407F48BC6A7EF9DB;
		data [6] = 70'h00407F48BC6A7EF9DB;
		data [7] = 70'h004048684D129F5D32;
		data [8] = 70'h003F72611593C60001;
		data [9] = 70'h00C0100FF20BD91970;
		data [10] = 70'h00C0BAD7E6A5048159;
		data [11] = 70'h0040BBC674C4140EF3;
		data [12] = 70'h0040A69E94DB886091;
		data [13] = 70'h00C07D46072866091F;
		clk = 0;
		din = 0;
		rst = 1;


		#90;
		rst = 0;
		#10 en = 1;
		for (j=0; j<=13; j=j+1) begin
			for (i=69; i>=0; i=i-1) begin
				din = data [j][i];
				#10;
			end
		end
		#10; 
		$finish();
	end

	always #5 clk = ~clk;
      
endmodule
module sipo_tb;



	reg en;
	reg clk;
	reg din;
	reg rst;
	reg [1:0] mode;
	integer i;
	integer j;
	reg [69:0] data [13:0];


	wire load;
	wire [69:0] dout;
	wire [3:0]  row;


	sipo uut (
		.en(en), 
		.clk(clk), 
		.din(din), 
		.rst(rst), 

		.load(load), 
		.dout(dout),
		.row(row)
	);
	
	initial begin

		en = 0;	mode = 2'b01;
		data [0] = 70'h204016000000000000;
		data [1] = 70'h004023000000000000;
		data [2] = 70'h0040234CCCC0000000;
		data [3] = 70'h003FD06C4C5974E65C;
		data [4] = 70'h0040B41E83DD97F62B;
		data [5] = 70'h00407F48BC6A7EF9DB;
		data [6] = 70'h00407F48BC6A7EF9DB;
		data [7] = 70'h004048684D129F5D32;
		data [8] = 70'h003F72611593C60001;
		data [9] = 70'h00C0100FF20BD91970;
		data [10] = 70'h00C0BAD7E6A5048159;
		data [11] = 70'h0040BBC674C4140EF3;
		data [12] = 70'h0040A69E94DB886091;
		data [13] = 70'h00C07D46072866091F;
		clk = 0;
		din = 0;
		rst = 1;


		#90;
		rst = 0;
		#10 en = 1;
		for (j=0; j<=13; j=j+1) begin
			for (i=69; i>=0; i=i-1) begin
				din = data [j][i];
				#10;
			end
		end
		#10; 
		$finish();
	end

	always #5 clk = ~clk;
      
endmodule