data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:47: Signal definition not found, creating implicitly: \'o_ABS_256H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_256H_n\'\n            o_ABS_256H, \n            ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:48: Signal definition not found, creating implicitly: \'o_ABS_128H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_256H\'\n            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, \n            ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:48: Signal definition not found, creating implicitly: \'o_ABS_64H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_128H\'\n            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, \n                        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:48: Signal definition not found, creating implicitly: \'o_ABS_32H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_128H\'\n            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, \n                                    ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:48: Signal definition not found, creating implicitly: \'o_ABS_16H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_128H\'\n            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, \n                                                ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:49: Signal definition not found, creating implicitly: \'o_ABS_8H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_128H\'\n            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H\n            ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:49: Signal definition not found, creating implicitly: \'o_ABS_4H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_64H\'\n            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H\n                        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:49: Signal definition not found, creating implicitly: \'o_ABS_2H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_32H\'\n            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H\n                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:49: Signal definition not found, creating implicitly: \'o_ABS_1H\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_16H\'\n            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H\n                                                ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:53: Signal definition not found, creating implicitly: \'o_ABS_256V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_256H\'\n            o_ABS_256V, \n            ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:54: Signal definition not found, creating implicitly: \'o_ABS_128V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_128H\'\n            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, \n            ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:54: Signal definition not found, creating implicitly: \'o_ABS_64V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_64H\'\n            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, \n                        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:54: Signal definition not found, creating implicitly: \'o_ABS_32V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_32H\'\n            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, \n                                    ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:54: Signal definition not found, creating implicitly: \'o_ABS_16V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_16H\'\n            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, \n                                                ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:55: Signal definition not found, creating implicitly: \'o_ABS_8V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_8H\'\n            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V\n            ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:55: Signal definition not found, creating implicitly: \'o_ABS_4V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_4H\'\n            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V\n                        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:55: Signal definition not found, creating implicitly: \'o_ABS_2V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_2H\'\n            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V\n                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521104862/resources/Psychic5_core_ModelSim/Psychic5_component/hybrid/N8633S.v:55: Signal definition not found, creating implicitly: \'o_ABS_1V\'\n                                                                                                                              : ... Suggested alternative: \'o_ABS_16V\'\n            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V\n                                                ^~~~~~~~\n%Error: Exiting due to 18 warning(s)\n'
module N8633S
(
    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_CLK6MPCEN_n,

    input   wire            i_FLIP,
    input   wire            i_CNTRSEL,

    output  wire            o_ABS_256H_n,
    output  wire            o_FLIP_64HA,

    output  wire    [8:0]   o_ABS_H_CNTR,
    output  wire    [8:0]   o_ABS_V_CNTR,

    output  wire    [7:0]   o_FLIP_HV_BUS
);

reg     [8:0]   horizontal_counter = 9'd128;
reg     [8:0]   vertical_counter = 9'd220;

assign  o_ABS_H_CNTR = horizontal_counter;
assign  o_ABS_V_CNTR = vertical_counter;

assign  {
            o_ABS_256H, 
            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, 
            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H
        } = horizontal_counter;

assign  {
            o_ABS_256V, 
            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, 
            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V
        } = vertical_counter;

assign  o_ABS_256H_n = ~o_ABS_256H;


always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(horizontal_counter == 9'd511)
        begin
            horizontal_counter <= 9'd128;

            if(vertical_counter == 9'd511)
            begin
                vertical_counter <= 9'd220;
            end
            else
            begin
                vertical_counter <= vertical_counter + 9'd1;
            end
        end
        else
        begin
            horizontal_counter <= horizontal_counter + 9'd1;
        end
    end
end


wire            FLIP_64HA = (o_ABS_64H ^ i_FLIP) & ~o_ABS_256H;
wire            FLIP_128HA = (o_ABS_128H ^ i_FLIP) & o_ABS_256H;
assign  o_FLIP_64HA = FLIP_64HA;

wire    [7:0]   FLIP_H_CNTR = {FLIP_128HA | FLIP_64HA, horizontal_counter[6:0] ^ {7{i_FLIP}}};

reg     [7:0]   FLIP_V_CNTR;
always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(horizontal_counter[4:0] == 5'd15)
        begin
            FLIP_V_CNTR <= vertical_counter[7:0] ^ {8{i_FLIP}};
        end
    end
end


assign  o_FLIP_HV_BUS = i_CNTRSEL ? FLIP_H_CNTR : FLIP_V_CNTR;

endmodule
module N8633S
(
    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_CLK6MPCEN_n,

    input   wire            i_FLIP,
    input   wire            i_CNTRSEL,

    output  wire            o_ABS_256H_n,
    output  wire            o_FLIP_64HA,

    output  wire    [8:0]   o_ABS_H_CNTR,
    output  wire    [8:0]   o_ABS_V_CNTR,

    output  wire    [7:0]   o_FLIP_HV_BUS
);


reg     [8:0]   horizontal_counter = 9'd128;
reg     [8:0]   vertical_counter = 9'd220;

assign  o_ABS_H_CNTR = horizontal_counter;
assign  o_ABS_V_CNTR = vertical_counter;

assign  {
            o_ABS_256H, 
            o_ABS_128H, o_ABS_64H,  o_ABS_32H,  o_ABS_16H, 
            o_ABS_8H,   o_ABS_4H,   o_ABS_2H,   o_ABS_1H
        } = horizontal_counter;

assign  {
            o_ABS_256V, 
            o_ABS_128V, o_ABS_64V,  o_ABS_32V,  o_ABS_16V, 
            o_ABS_8V,   o_ABS_4V,   o_ABS_2V,   o_ABS_1V
        } = vertical_counter;

assign  o_ABS_256H_n = ~o_ABS_256H;


always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(horizontal_counter == 9'd511)
        begin
            horizontal_counter <= 9'd128;

            if(vertical_counter == 9'd511)
            begin
                vertical_counter <= 9'd220;
            end
            else
            begin
                vertical_counter <= vertical_counter + 9'd1;
            end
        end
        else
        begin
            horizontal_counter <= horizontal_counter + 9'd1;
        end
    end
end


wire            FLIP_64HA = (o_ABS_64H ^ i_FLIP) & ~o_ABS_256H;
wire            FLIP_128HA = (o_ABS_128H ^ i_FLIP) & o_ABS_256H;
assign  o_FLIP_64HA = FLIP_64HA;

wire    [7:0]   FLIP_H_CNTR = {FLIP_128HA | FLIP_64HA, horizontal_counter[6:0] ^ {7{i_FLIP}}};

reg     [7:0]   FLIP_V_CNTR;
always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(horizontal_counter[4:0] == 5'd15)
        begin
            FLIP_V_CNTR <= vertical_counter[7:0] ^ {8{i_FLIP}};
        end
    end
end


assign  o_FLIP_HV_BUS = i_CNTRSEL ? FLIP_H_CNTR : FLIP_V_CNTR;

endmodule