data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/dtu/rtl/pa_dtu_cdc_lvl.v
data/verilator_xmls/61d5bca4-3941-412f-a0ee-19a54b72c2b0.xml
module pa_dtu_cdc_lvl(
  clk,
  dst_lvl,
  rst_b,
  src_lvl
);


input        clk;    
input        rst_b;  
input        src_lvl; 
output       dst_lvl; 


reg          sync1;  
reg          sync2;  
reg          sync3;  


wire         clk;    
wire         dst_lvl; 
wire         rst_b;  
wire         src_lvl; 


always @(posedge clk or negedge rst_b)
begin
  if(!rst_b)
    begin
      sync1 <= 1'b0;
      sync2 <= 1'b0;
      sync3 <= 1'b0;
    end
  else 
    begin
      sync1 <= src_lvl;
      sync2 <= sync1;  
      sync3 <= sync2;
    end
end
assign dst_lvl = sync3;


endmodule
module pa_dtu_cdc_lvl(
  clk,
  dst_lvl,
  rst_b,
  src_lvl
);



input        clk;    
input        rst_b;  
input        src_lvl; 
output       dst_lvl; 


reg          sync1;  
reg          sync2;  
reg          sync3;  


wire         clk;    
wire         dst_lvl; 
wire         rst_b;  
wire         src_lvl; 


always @(posedge clk or negedge rst_b)
begin
  if(!rst_b)
    begin
      sync1 <= 1'b0;
      sync2 <= 1'b0;
      sync3 <= 1'b0;
    end
  else 
    begin
      sync1 <= src_lvl;
      sync2 <= sync1;  
      sync3 <= sync2;
    end
end
assign dst_lvl = sync3;


endmodule