data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg.v
1: b"%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg.v:77: Cannot find file containing module: 'jtopl_noise'\njtopl_noise u_noise(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_noise\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_noise.v\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_noise.sv\n             jtopl_noise\n             jtopl_noise.v\n             jtopl_noise.sv\n             obj_dir/jtopl_noise\n             obj_dir/jtopl_noise.v\n             obj_dir/jtopl_noise.sv\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg.v:84: Cannot find file containing module: 'jtopl_pg_comb'\njtopl_pg_comb u_comb(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg.v:112: Cannot find file containing module: 'jtopl_sh_rst'\njtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg.v:120: Cannot find file containing module: 'jtopl_sh_rst'\njtopl_sh_rst #( .width(10), .stages(2) ) u_pad(\n^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module jtopl_pg(
    input wire              rst,
    input wire              clk,
    input wire              cenop,
    input wire      [17:0]  slot,
    input wire              rhy_en,

    input wire      [ 9:0]  fnum_I,
    input wire      [ 2:0]  block_I,

    input wire      [ 3:0]  mul_II,

    input wire      [ 2:0]  vib_cnt,
    input wire              vib_dep,
    input wire              viben_I,

    input  wire             pg_rst_II,
    
    output  reg [ 3:0]  keycode_II,
    output  wire    [ 9:0]  phase_IV
);

parameter CH=9;

wire [ 3:0] keycode_I;
wire [16:0] phinc_I;
reg  [16:0] phinc_II;
wire [18:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
wire        noise;
reg  [ 9:0] hh, tc;
reg         rm_xor;
wire        hh_en, sd_en, tc_en;

always @(posedge clk) if(cenop) begin
    keycode_II      <= keycode_I;
    phinc_II        <= phinc_I;
end


always @(posedge clk, posedge rst) begin
    if( rst ) begin
        hh <= 10'd0;
        tc <= 10'd0;
    end else begin
        if( slot[13] ) hh <= phase_drop[18:9];
        if( slot[17] ) tc <= phase_drop[18:9];
        rm_xor <= (hh[2]^hh[7]) | (hh[3]^tc[5]) | (tc[3]^tc[5]);
    end
end

assign  hh_en = rhy_en & slot[14];
assign  sd_en = rhy_en & slot[17];
assign  tc_en = rhy_en & slot[ 0];

jtopl_noise u_noise(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),
    .noise  ( noise     )
);

jtopl_pg_comb u_comb(
    .block      ( block_I       ),
    .fnum       ( fnum_I        ),

    .vib_cnt    ( vib_cnt       ),
    .vib_dep    ( vib_dep       ),
    .viben      ( viben_I       ),

    .keycode    ( keycode_I     ),

    .phinc_out  ( phinc_I       ),

    .mul        ( mul_II        ),
    .phase_in   ( phase_drop    ),
    .pg_rst     ( pg_rst_II     ),
    .phinc_in   ( phinc_II      ),

    .hh_en      ( hh_en         ),
    .sd_en      ( sd_en         ),
    .tc_en      ( tc_en         ),
    .rm_xor     ( rm_xor        ),
    .noise      ( noise         ),
    .hh         ( hh            ),

    .phase_out  ( phase_in      ),
    .phase_op   ( phase_II      )
);

jtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),
    .din    ( phase_in  ),
    .drop   ( phase_drop)
);

jtopl_sh_rst #( .width(10), .stages(2) ) u_pad(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),  
    .din    ( phase_II  ),
    .drop   ( phase_IV  )
);

endmodule
module jtopl_pg(
    input wire              rst,
    input wire              clk,
    input wire              cenop,
    input wire      [17:0]  slot,
    input wire              rhy_en,

    input wire      [ 9:0]  fnum_I,
    input wire      [ 2:0]  block_I,

    input wire      [ 3:0]  mul_II,

    input wire      [ 2:0]  vib_cnt,
    input wire              vib_dep,
    input wire              viben_I,

    input  wire             pg_rst_II,
    
    output  reg [ 3:0]  keycode_II,
    output  wire    [ 9:0]  phase_IV
);


parameter CH=9;

wire [ 3:0] keycode_I;
wire [16:0] phinc_I;
reg  [16:0] phinc_II;
wire [18:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
wire        noise;
reg  [ 9:0] hh, tc;
reg         rm_xor;
wire        hh_en, sd_en, tc_en;

always @(posedge clk) if(cenop) begin
    keycode_II      <= keycode_I;
    phinc_II        <= phinc_I;
end


always @(posedge clk, posedge rst) begin
    if( rst ) begin
        hh <= 10'd0;
        tc <= 10'd0;
    end else begin
        if( slot[13] ) hh <= phase_drop[18:9];
        if( slot[17] ) tc <= phase_drop[18:9];
        rm_xor <= (hh[2]^hh[7]) | (hh[3]^tc[5]) | (tc[3]^tc[5]);
    end
end

assign  hh_en = rhy_en & slot[14];
assign  sd_en = rhy_en & slot[17];
assign  tc_en = rhy_en & slot[ 0];

jtopl_noise u_noise(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),
    .noise  ( noise     )
);

jtopl_pg_comb u_comb(
    .block      ( block_I       ),
    .fnum       ( fnum_I        ),

    .vib_cnt    ( vib_cnt       ),
    .vib_dep    ( vib_dep       ),
    .viben      ( viben_I       ),

    .keycode    ( keycode_I     ),

    .phinc_out  ( phinc_I       ),

    .mul        ( mul_II        ),
    .phase_in   ( phase_drop    ),
    .pg_rst     ( pg_rst_II     ),
    .phinc_in   ( phinc_II      ),

    .hh_en      ( hh_en         ),
    .sd_en      ( sd_en         ),
    .tc_en      ( tc_en         ),
    .rm_xor     ( rm_xor        ),
    .noise      ( noise         ),
    .hh         ( hh            ),

    .phase_out  ( phase_in      ),
    .phase_op   ( phase_II      )
);

jtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),
    .din    ( phase_in  ),
    .drop   ( phase_drop)
);

jtopl_sh_rst #( .width(10), .stages(2) ) u_pad(
    .clk    ( clk       ),
    .cen    ( cenop     ),
    .rst    ( rst       ),  
    .din    ( phase_II  ),
    .drop   ( phase_IV  )
);

endmodule