data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv/conv_cal.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv/conv_cal.v:39: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'rlt_c\' generates 4 bits.\n                                                                                                           : ... In instance conv_cal\nassign addr = rlt_l * result_width + rlt_c;   \n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv/conv_cal.v:55: Bit extraction of array[8:0] requires 4 bit index, not 16 bits.\n                                                                                                           : ... In instance conv_cal\n            rdata[addr] = data_link;\n                 ^\n%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv/conv_cal.v:78: Cannot find file containing module: \'mult_add\'\nmult_add u_mult_add(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv,data/full_repos/permissive/514467334/mult_add\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv,data/full_repos/permissive/514467334/mult_add.v\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/Conv,data/full_repos/permissive/514467334/mult_add.sv\n             mult_add\n             mult_add.v\n             mult_add.sv\n             obj_dir/mult_add\n             obj_dir/mult_add.v\n             obj_dir/mult_add.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module conv_cal #(
           parameter weight_width = 2,
           parameter weight_height = 2,

           parameter img_width = 4,
           parameter img_height = 4,

           parameter padding_enable = 0,
           parameter padding = 0,

           parameter stride = 1,
           parameter bitwidth = 3,
           parameter result_width = (img_width - weight_width + 2 * padding) / stride + 1,
           parameter result_height = (img_height - weight_height + 2 * padding) / stride + 1,
           parameter expand = 1
       ) (
           input clk_en,
           input rst_n,
           input conv_on,
           input srh_fin,

           input chge_rlt,
           input chge_rlt_q,

           input [3: 0] rlt_l,
           input [3: 0] rlt_c,

           input [bitwidth - 1: 0] bias,
           input [bitwidth - 1: 0] img_cal,
           input [bitwidth - 1: 0] wei_cal,

           output [expand * 2 * result_width * result_height * bitwidth - 1: 0] result
       );



wire [23: 0] data_link;
wire [15: 0] addr;
assign addr = rlt_l * result_width + rlt_c;
reg [23: 0] rdata [0: result_width * result_height - 1];
reg [3: 0] i;
always @(posedge clk_en) begin
    if (!rst_n) begin
        for (i = 0;i < result_width * result_height;i = i + 1) begin
            rdata[i] = 0;
        end
    end
    else if (conv_on) begin
        if (chge_rlt_q) begin
            for (i = 0;i < result_width * result_height;i = i + 1) begin
                rdata[i] = rdata[i];
            end
        end
        else begin
            rdata[addr] = data_link;
        end
    end
    else begin
        for (i = 0;i < result_width * result_height;i = i + 1) begin
            rdata[i] = rdata[i];
        end
    end
end


generate
    genvar j;
    for (j = 0;j < result_width * result_height;j = j + 1) begin
        assign result[j * (expand * 2 * bitwidth) +: (expand * 2 * bitwidth)] = rdata[j][(expand * 2 * bitwidth) - 1: 0] + {{(expand * 2 - 1) * bitwidth{1'b0}}, bias};
    end
endgenerate


wire reload;
assign reload = chge_rlt | srh_fin;


mult_add u_mult_add(

             .sys_clk_i ( clk_en ),
             .sys_rst_n_i ( ~rst_n ),
             .sys_is_add_i ( 1'b0 ),
             .am_num_A0_i ( img_cal ),
             .am_num_A1_i ( wei_cal ),
             .am_num_B0_i ( conv_on ),
             .am_num_B1_i ( reload ),
             .am_mult_o ( data_link )
         );


endmodule
module conv_cal #(
           parameter weight_width = 2,
           parameter weight_height = 2,

           parameter img_width = 4,
           parameter img_height = 4,

           parameter padding_enable = 0,
           parameter padding = 0,

           parameter stride = 1,
           parameter bitwidth = 3,
           parameter result_width = (img_width - weight_width + 2 * padding) / stride + 1,
           parameter result_height = (img_height - weight_height + 2 * padding) / stride + 1,
           parameter expand = 1
       ) (
           input clk_en,
           input rst_n,
           input conv_on,
           input srh_fin,

           input chge_rlt,
           input chge_rlt_q,

           input [3: 0] rlt_l,
           input [3: 0] rlt_c,

           input [bitwidth - 1: 0] bias,
           input [bitwidth - 1: 0] img_cal,
           input [bitwidth - 1: 0] wei_cal,

           output [expand * 2 * result_width * result_height * bitwidth - 1: 0] result
       );




wire [23: 0] data_link;
wire [15: 0] addr;
assign addr = rlt_l * result_width + rlt_c;
reg [23: 0] rdata [0: result_width * result_height - 1];
reg [3: 0] i;
always @(posedge clk_en) begin
    if (!rst_n) begin
        for (i = 0;i < result_width * result_height;i = i + 1) begin
            rdata[i] = 0;
        end
    end
    else if (conv_on) begin
        if (chge_rlt_q) begin
            for (i = 0;i < result_width * result_height;i = i + 1) begin
                rdata[i] = rdata[i];
            end
        end
        else begin
            rdata[addr] = data_link;
        end
    end
    else begin
        for (i = 0;i < result_width * result_height;i = i + 1) begin
            rdata[i] = rdata[i];
        end
    end
end


generate
    genvar j;
    for (j = 0;j < result_width * result_height;j = j + 1) begin
        assign result[j * (expand * 2 * bitwidth) +: (expand * 2 * bitwidth)] = rdata[j][(expand * 2 * bitwidth) - 1: 0] + {{(expand * 2 - 1) * bitwidth{1'b0}}, bias};
    end
endgenerate


wire reload;
assign reload = chge_rlt | srh_fin;


mult_add u_mult_add(

             .sys_clk_i ( clk_en ),
             .sys_rst_n_i ( ~rst_n ),
             .sys_is_add_i ( 1'b0 ),
             .am_num_A0_i ( img_cal ),
             .am_num_A1_i ( wei_cal ),
             .am_num_B0_i ( conv_on ),
             .am_num_B1_i ( reload ),
             .am_mult_o ( data_link )
         );


endmodule