data/full_repos/permissive/427221126/src/nntop_ctrl.v
1: b'%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:22: Cannot find include file: nn_microops.v\n`include "nn_microops.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/nn_microops.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/nn_microops.v.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/nn_microops.v.sv\n             nn_microops.v\n             nn_microops.v.v\n             nn_microops.v.sv\n             obj_dir/nn_microops.v\n             obj_dir/nn_microops.v.v\n             obj_dir/nn_microops.v.sv\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:423: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign ram_glb_we    = ;\n                         ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:424: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign ram_glb_addr1 = ;\n                         ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:425: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign ram_glb_addr2 = ;\n                         ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:430: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign datafifo_read  = ;\n                          ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:432: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign wbfifo_read    = ;\n                          ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:434: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign cc_din0_valid = ;\n                         ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:435: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign cc_din1_valid = ;\n                         ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:436: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign cc_sum_en = ;\n                     ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:439: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign poolavg_start     = ;\n                             ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:440: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign poolavg_din_valid = ;\n                             ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:441: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign poolavg_dout_ready = ;\n                              ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:443: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign dense_din_valid  = ;\n                            ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:444: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign dense_win_valid  = ;\n                            ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:445: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign dense_dout_ready = ;\n                            ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:449: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign addlayer_start      = ;\n                               ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:450: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign addlayer_din_valid  = ;\n                               ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:451: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign addlayer_dout_ready = ;\n                               ^\n%Error: data/full_repos/permissive/427221126/src/nntop_ctrl.v:454: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign fmap_din_valid = ;\n                          ^\n%Error: Exiting due to 19 error(s)\n'
module NNTopCtrl
  #(
    parameter NUM_CHANNELS = 15,
              GLB_ADDR_WIDTH = 16,
              HEIGHT_WIDTH = 5
  )
  (
    input  clk  ,
    input  reset,
    input  en   ,
    

    output din_ready    ,
    input  din_valid    ,
    input  din_param    ,
    

    output                      ram_glb_we   ,
    output [GLB_ADDR_WIDTH-1:0] ram_glb_addr1,
    output [GLB_ADDR_WIDTH-1:0] ram_glb_addr2,


    input   [30:0]  inst_in       ,
    output          instfifo_write,
    output          instfifo_read ,
    input           instfifo_empty,
    input           instfifo_full ,


    output datafifo_write ,
    output datafifo_read  ,
    input  datafifo_empty ,
    input  datafifo_full  ,


    output  wbfifo_write  ,
    output  wbfifo_read   ,
    input   wbfifo_empty  ,
    input   wbfifo_full   ,


    output cc_din0_valid,
    output cc_din1_valid,
    output cc_sum_en    ,
    input  cc_dout_valid,
    

    output [1:0]  poolavg_plty      ,
    output        poolavg_start     ,
    output        poolavg_din_valid ,
    input         poolavg_din_ready ,
    input         poolavg_dout_valid,
    output        poolavg_dout_ready,
    

    output dense_din_valid  ,
    output dense_win_valid  ,
    output dense_dout_ready ,
    input  dense_dout_valid ,


    output [HEIGHT_WIDTH-1:0] addlayer_height     ,
    output [HEIGHT_WIDTH-1:0] addlayer_width      ,
    output                    addlayer_start      ,
    input                     addlayer_din_ready  ,
    output                    addlayer_din_valid  ,
    output                    addlayer_dout_ready ,
    input                     addlayer_dout_valid ,
    

    input  fmap_dout_valid,
    output fmap_a_we      ,
    output fmap_b_we      ,
    output fmap_c_we      ,
    output fmap_d_we      ,
    output fmap_din_valid ,


    output relu_xin_valid ,
    input  relu_yout_valid,


    output ofifo_write,


    output [0:0] din_sel  ,
    output [1:0] glb_sel  ,
    output [0:0] relu_sel ,
    output [2:0] smob_sel  
  );


  parameter INST_FETCH  = 3'b000,
            DECODE1     = 3'b001,
            DECODE2     = 3'b011,
            GLB_ACCESS  = 3'b010,
            EXECUTION   = 3'b110,
            WRITEBACK   = 3'b111;


  reg   [2:0] Sreg, Snext;
  reg         has_ga;
  reg         has_exec, has_wb;
  wire        done_ga, done_exec, done_wb;


  reg   [GLB_ADDR_WIDTH-1:0]  ga_counter  ;
  reg   [GLB_ADDR_WIDTH-1:0]  ga_maxcount ;
  wire                        ga_wrap     ;
  reg                         gacnt_next  ;

  wire  ififo_write     ;
  wire  ififo_rdtf      ;
  wire  dfifo_write     ;
  reg   ififo_read      ;
  reg   wfifo_write     ;


  reg   busy;
  reg   backwriting;


  reg   [5:0] submod_en       ;
  wire        submod_ctrl_en  ;
  wire        submod_conv_en  ;
  wire        submod_pool_en  ;
  wire        submod_dense_en ;
  wire        submod_addl_en  ;
  wire        submod_fmar_en  ;


  reg   [0:0] din_sel_reg ;
  reg   [1:0] glb_sel_reg ;
  reg   [0:0] relu_sel_reg;
  reg   [2:0] smob_sel_reg;


  reg   [30 :0] inst_reg;
  wire  [2  :0] inst_submod;
  wire  [3  :0] inst_opcode;
  wire  [5  :0] inst_config;
  wire  [15 :0] inst_baseaddr;


  reg   [HEIGHT_WIDTH-1 :0] addl_h, addl_w;
  reg   [1:0]               pool_plty;
  wire                      is_addl_setx;
  reg   [3:0]               fma_we;
  wire                      is_ctrl_setsel;
  reg                       ofifo_write_enable;


  reg   smob_dout_valid;


  assign dfifo_write = din_param;
  assign ififo_write = !din_param;

  always @(posedge clk) begin
    if (reset) 
      Sreg <= INST_FETCH;
    else if (en)
      Sreg <= Snext;
  end

  assign ififo_rdtf = instfifo_read && !instfifo_empty;
  always @(*) begin
    case (Sreg)
      INST_FETCH  : 
        if (ififo_rdtf)  
          Snext = DECODE1;
        else
          Snext = INST_FETCH;
      DECODE1     : Snext = DECODE2;
      DECODE2     :
        casez({has_ga, has_exec, has_wb})
          3'b1??: Snext = GLB_ACCESS;
          3'b01?: Snext = EXECUTION;
          3'b001: Snext = WRITEBACK;
          default Snext = INST_FETCH;
        endcase
      GLB_ACCESS  :
        if (!done_ga)
          Snext = GLB_ACCESS;
        else
          if (has_exec) Snext = EXECUTION;
          else if (has_wb) Snext = WRITEBACK;
          else Snext = INST_FETCH;
      EXECUTION   :
        if (!done_exec)
          Snext = EXECUTION;
        else
          if (has_wb) Snext = WRITEBACK;
          else Snext = INST_FETCH;
      WRITEBACK   : 
        if (done_wb) Snext = INST_FETCH;
        else Snext = WRITEBACK;      
      default     : Snext = INST_FETCH;
    endcase
  end


  always @(posedge clk) begin
    if (reset) begin
      inst_reg <= 31'h0000;
    end
    else if (en) begin
      if (ififo_rdtf)
        inst_reg <= inst_in;
    end
  end
  assign inst_baseaddr = inst_reg[NNMICROOPS_BASEADDR_MSB:NNMICROOPS_BASEADDR_LSB];
  assign inst_config = inst_reg[NNMICROOPS_CONFIG_MSB:NNMICROOPS_CONFIG_LSB];
  assign inst_opcode = inst_reg[NNMICROOPS_OPCODE_MSB:NNMICROOPS_OPCODE_LSB];
  assign inst_submod = inst_reg[NNMICROOPS_SUBMOD_MSB:NNMICROOPS_SUBMOD_LSB];

  always @(posedge clk) begin
    if (reset) begin
      ififo_read <= 1'b0;
    end
    else if (en) begin
      if (Sreg == INST_FETCH)
        ififo_read <= 1'b1;
      else if (ififo_rdtf)
        ififo_read <= 1'b0;
    end
  end


  always @(posedge clk) begin
    if (reset)
      has_ga <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1) begin
        if (inst_submod != NNMICROOPS_SUBMOD_FMAROUND)
          has_ga <= (inst_opcode[3:2] == 2'b00);
        else 
          has_ga <= (inst_opcode[2] == 1'b1);
      end
    end
  end

  always @(posedge clk) begin
    if (reset)
      has_exec <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1)
        has_exec <= !(inst_opcode[2] == 1'b0);
    end
  end

  always @(posedge clk) begin
    if (reset)
      has_wb <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1) begin
        if (submod_ctrl_en && inst_opcode == NNMICROOPS_OPCODE_CTRL_WB)
          has_wb <= 1'b1;
        else
          has_wb <= 1'b0;
      end
    end
  end

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      submod_en <= 6'h00;
    end
    else if (en) begin
      if (Sreg == DECODE1) begin
        case (inst_submod)
          NNMICROOPS_SUBMOD_CTRL    : submod_en <= 6'b000001;
          NNMICROOPS_SUBMOD_CONV    : submod_en <= 6'b000010;
          NNMICROOPS_SUBMOD_POOLAVG : submod_en <= 6'b000100;
          NNMICROOPS_SUBMOD_DENSE   : submod_en <= 6'b001000;
          NNMICROOPS_SUBMOD_ADDLY   : submod_en <= 6'b010000;
          NNMICROOPS_SUBMOD_FMAROUND: submod_en <= 6'b100000;
          default                   : submod_en <= 6'b000000;
        endcase
      end
      else if (Sreg == INST_FETCH)
        submod_en <= 6'b000000;
    end
  end


  always @(posedge clk) begin
    if (reset)
      pool_plty <= 2'b00;
    else if (en) begin
      if (Sreg == DECODE2)
        if (submod_pool_en && inst_opcode[2] == 1'b1)
          pool_plty <= inst_config[1:0];
    end
  end

  assign is_addl_setx = (submod_addly_en) && (inst_opcode[2] == 1'b1);
  always @(posedge clk) begin
    if (reset) begin
      addl_h <= 0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && is_addl_setx && (inst_config[0] == 1'b1))
        addl_h <= inst_baseaddr[4:0];
    end
  end
  always @(posedge clk) begin
    if (reset) begin
      addl_w <= 0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && is_addl_setx && (inst_config[1] == 1'b1))
        addl_w <= inst_baseaddr[9:5];
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      fma_we <= 4'h0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && submod_fmar_en && inst_opcode == NNMICROOPS_OPCODE_SET)
        fma_we <= inst_config[3:0];
    end
  end

  assign is_ctrl_setsel = (submod_ctrl_en && inst_opcode[3:2] == 2'b01);
  always @(posedge clk) begin
    if (reset) begin
      din_sel_reg <= 1'b0;
      glb_sel_reg <= 2'b00;
      relu_sel_reg <= 1'b0;
      smob_sel_reg <= 3'b000;
    end
    else if (en) begin
      if (inst_opcode[1:0] == 2'b00) begin
        din_sel_reg <= inst_config[0:0];
      end
      if (inst_opcode[1:0] == 2'b01) begin
        glb_sel_reg <= inst_config[1:0];
      end
      if (inst_opcode[1:0] == 2'b10) begin
        relu_sel_reg <= inst_config[0:0];
      end
      if (inst_opcode[1:0] == 2'b11) begin
        smob_sel_reg <= inst_config[2:0];
      end
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      ofifo_write_enable <= 1'b0;
    end
    else if (en) begin
      if (Sreg == DECODE2)
        if (submod_ctrl_en && inst_opcode == NNMICROOPS_OPCODE_CTRL_OEN)
          ofifo_write_enable <= 1'b1;
      else if (Sreg == EXECUTION && done_exec)
        ofifo_write_enable <= 1'b0;
    end
  end

  always @(*) begin
    case (smob_sel)
      3'd1: smob_dout_valid = cc_dout_valid       ;
      3'd2: smob_dout_valid = poolavg_dout_valid  ;
      3'd3: smob_dout_valid = dense_dout_valid    ;
      3'd4: smob_dout_valid = addlayer_dout_valid ;
      3'd5: smob_dout_valid = fmap_dout_valid     ;
      3'd6: smob_dout_valid = 1'b1;
      default smob_dout_valid = 1'b0;
    endcase
  end













  assign submod_ctrl_en = submod_en[NNMICROOPS_SUBMOD_CTRL    ];
  assign submod_conv_en = submod_en[NNMICROOPS_SUBMOD_CONV    ];
  assign submod_pool_en = submod_en[NNMICROOPS_SUBMOD_POOLAVG ];
  assign submod_dense_en = submod_en[NNMICROOPS_SUBMOD_DENSE  ];
  assign submod_addl_en = submod_en[NNMICROOPS_SUBMOD_ADDLY   ];
  assign submod_fmar_en = submod_en[NNMICROOPS_SUBMOD_FMAROUND];

  


  assign din_ready = (!instfifo_empty) && (!datafifo_empty);

  assign ram_glb_we    = ;
  assign ram_glb_addr1 = ;
  assign ram_glb_addr2 = ;

  assign instfifo_write = ififo_write ;
  assign instfifo_read  = ififo_read  ;
  assign datafifo_write = dfifo_write ;
  assign datafifo_read  = ;
  assign wbfifo_write   = wfifo_write ;
  assign wbfifo_read    = ;

  assign cc_din0_valid = ;
  assign cc_din1_valid = ;
  assign cc_sum_en = ;
  
  assign poolavg_plty = pool_plty;
  assign poolavg_start     = ;
  assign poolavg_din_valid = ;
  assign poolavg_dout_ready = ;

  assign dense_din_valid  = ;
  assign dense_win_valid  = ;
  assign dense_dout_ready = ;
  
  assign addlayer_height = addl_h;
  assign addlayer_width  = addl_w;
  assign addlayer_start      = ;
  assign addlayer_din_valid  = ;
  assign addlayer_dout_ready = ;

  assign {fmap_d_we, fmap_c_we, fmap_b_we, fmap_a_we} = fma_we;
  assign fmap_din_valid = ;

  assign relu_xin_valid = smob_dout_valid;

  assign ofifo_write = (ofifo_write_enable) ? relu_yout_valid : 1'b0;

  assign din_sel  = din_sel_reg ;
  assign glb_sel  = glb_sel_reg ;
  assign relu_sel = relu_sel_reg;
  assign smob_sel = smob_sel_reg;
endmodule
module NNTopCtrl
  #(
    parameter NUM_CHANNELS = 15,
              GLB_ADDR_WIDTH = 16,
              HEIGHT_WIDTH = 5
  )
  (
    input  clk  ,
    input  reset,
    input  en   ,
    

    output din_ready    ,
    input  din_valid    ,
    input  din_param    ,
    

    output                      ram_glb_we   ,
    output [GLB_ADDR_WIDTH-1:0] ram_glb_addr1,
    output [GLB_ADDR_WIDTH-1:0] ram_glb_addr2,


    input   [30:0]  inst_in       ,
    output          instfifo_write,
    output          instfifo_read ,
    input           instfifo_empty,
    input           instfifo_full ,


    output datafifo_write ,
    output datafifo_read  ,
    input  datafifo_empty ,
    input  datafifo_full  ,


    output  wbfifo_write  ,
    output  wbfifo_read   ,
    input   wbfifo_empty  ,
    input   wbfifo_full   ,


    output cc_din0_valid,
    output cc_din1_valid,
    output cc_sum_en    ,
    input  cc_dout_valid,
    

    output [1:0]  poolavg_plty      ,
    output        poolavg_start     ,
    output        poolavg_din_valid ,
    input         poolavg_din_ready ,
    input         poolavg_dout_valid,
    output        poolavg_dout_ready,
    

    output dense_din_valid  ,
    output dense_win_valid  ,
    output dense_dout_ready ,
    input  dense_dout_valid ,


    output [HEIGHT_WIDTH-1:0] addlayer_height     ,
    output [HEIGHT_WIDTH-1:0] addlayer_width      ,
    output                    addlayer_start      ,
    input                     addlayer_din_ready  ,
    output                    addlayer_din_valid  ,
    output                    addlayer_dout_ready ,
    input                     addlayer_dout_valid ,
    

    input  fmap_dout_valid,
    output fmap_a_we      ,
    output fmap_b_we      ,
    output fmap_c_we      ,
    output fmap_d_we      ,
    output fmap_din_valid ,


    output relu_xin_valid ,
    input  relu_yout_valid,


    output ofifo_write,


    output [0:0] din_sel  ,
    output [1:0] glb_sel  ,
    output [0:0] relu_sel ,
    output [2:0] smob_sel  
  );



  parameter INST_FETCH  = 3'b000,
            DECODE1     = 3'b001,
            DECODE2     = 3'b011,
            GLB_ACCESS  = 3'b010,
            EXECUTION   = 3'b110,
            WRITEBACK   = 3'b111;


  reg   [2:0] Sreg, Snext;
  reg         has_ga;
  reg         has_exec, has_wb;
  wire        done_ga, done_exec, done_wb;


  reg   [GLB_ADDR_WIDTH-1:0]  ga_counter  ;
  reg   [GLB_ADDR_WIDTH-1:0]  ga_maxcount ;
  wire                        ga_wrap     ;
  reg                         gacnt_next  ;

  wire  ififo_write     ;
  wire  ififo_rdtf      ;
  wire  dfifo_write     ;
  reg   ififo_read      ;
  reg   wfifo_write     ;


  reg   busy;
  reg   backwriting;


  reg   [5:0] submod_en       ;
  wire        submod_ctrl_en  ;
  wire        submod_conv_en  ;
  wire        submod_pool_en  ;
  wire        submod_dense_en ;
  wire        submod_addl_en  ;
  wire        submod_fmar_en  ;


  reg   [0:0] din_sel_reg ;
  reg   [1:0] glb_sel_reg ;
  reg   [0:0] relu_sel_reg;
  reg   [2:0] smob_sel_reg;


  reg   [30 :0] inst_reg;
  wire  [2  :0] inst_submod;
  wire  [3  :0] inst_opcode;
  wire  [5  :0] inst_config;
  wire  [15 :0] inst_baseaddr;


  reg   [HEIGHT_WIDTH-1 :0] addl_h, addl_w;
  reg   [1:0]               pool_plty;
  wire                      is_addl_setx;
  reg   [3:0]               fma_we;
  wire                      is_ctrl_setsel;
  reg                       ofifo_write_enable;


  reg   smob_dout_valid;


  assign dfifo_write = din_param;
  assign ififo_write = !din_param;

  always @(posedge clk) begin
    if (reset) 
      Sreg <= INST_FETCH;
    else if (en)
      Sreg <= Snext;
  end

  assign ififo_rdtf = instfifo_read && !instfifo_empty;
  always @(*) begin
    case (Sreg)
      INST_FETCH  : 
        if (ififo_rdtf)  
          Snext = DECODE1;
        else
          Snext = INST_FETCH;
      DECODE1     : Snext = DECODE2;
      DECODE2     :
        casez({has_ga, has_exec, has_wb})
          3'b1??: Snext = GLB_ACCESS;
          3'b01?: Snext = EXECUTION;
          3'b001: Snext = WRITEBACK;
          default Snext = INST_FETCH;
        endcase
      GLB_ACCESS  :
        if (!done_ga)
          Snext = GLB_ACCESS;
        else
          if (has_exec) Snext = EXECUTION;
          else if (has_wb) Snext = WRITEBACK;
          else Snext = INST_FETCH;
      EXECUTION   :
        if (!done_exec)
          Snext = EXECUTION;
        else
          if (has_wb) Snext = WRITEBACK;
          else Snext = INST_FETCH;
      WRITEBACK   : 
        if (done_wb) Snext = INST_FETCH;
        else Snext = WRITEBACK;      
      default     : Snext = INST_FETCH;
    endcase
  end


  always @(posedge clk) begin
    if (reset) begin
      inst_reg <= 31'h0000;
    end
    else if (en) begin
      if (ififo_rdtf)
        inst_reg <= inst_in;
    end
  end
  assign inst_baseaddr = inst_reg[NNMICROOPS_BASEADDR_MSB:NNMICROOPS_BASEADDR_LSB];
  assign inst_config = inst_reg[NNMICROOPS_CONFIG_MSB:NNMICROOPS_CONFIG_LSB];
  assign inst_opcode = inst_reg[NNMICROOPS_OPCODE_MSB:NNMICROOPS_OPCODE_LSB];
  assign inst_submod = inst_reg[NNMICROOPS_SUBMOD_MSB:NNMICROOPS_SUBMOD_LSB];

  always @(posedge clk) begin
    if (reset) begin
      ififo_read <= 1'b0;
    end
    else if (en) begin
      if (Sreg == INST_FETCH)
        ififo_read <= 1'b1;
      else if (ififo_rdtf)
        ififo_read <= 1'b0;
    end
  end


  always @(posedge clk) begin
    if (reset)
      has_ga <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1) begin
        if (inst_submod != NNMICROOPS_SUBMOD_FMAROUND)
          has_ga <= (inst_opcode[3:2] == 2'b00);
        else 
          has_ga <= (inst_opcode[2] == 1'b1);
      end
    end
  end

  always @(posedge clk) begin
    if (reset)
      has_exec <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1)
        has_exec <= !(inst_opcode[2] == 1'b0);
    end
  end

  always @(posedge clk) begin
    if (reset)
      has_wb <= 1'b0;
    else if (en) begin
      if (Sreg == DECODE1) begin
        if (submod_ctrl_en && inst_opcode == NNMICROOPS_OPCODE_CTRL_WB)
          has_wb <= 1'b1;
        else
          has_wb <= 1'b0;
      end
    end
  end

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      submod_en <= 6'h00;
    end
    else if (en) begin
      if (Sreg == DECODE1) begin
        case (inst_submod)
          NNMICROOPS_SUBMOD_CTRL    : submod_en <= 6'b000001;
          NNMICROOPS_SUBMOD_CONV    : submod_en <= 6'b000010;
          NNMICROOPS_SUBMOD_POOLAVG : submod_en <= 6'b000100;
          NNMICROOPS_SUBMOD_DENSE   : submod_en <= 6'b001000;
          NNMICROOPS_SUBMOD_ADDLY   : submod_en <= 6'b010000;
          NNMICROOPS_SUBMOD_FMAROUND: submod_en <= 6'b100000;
          default                   : submod_en <= 6'b000000;
        endcase
      end
      else if (Sreg == INST_FETCH)
        submod_en <= 6'b000000;
    end
  end


  always @(posedge clk) begin
    if (reset)
      pool_plty <= 2'b00;
    else if (en) begin
      if (Sreg == DECODE2)
        if (submod_pool_en && inst_opcode[2] == 1'b1)
          pool_plty <= inst_config[1:0];
    end
  end

  assign is_addl_setx = (submod_addly_en) && (inst_opcode[2] == 1'b1);
  always @(posedge clk) begin
    if (reset) begin
      addl_h <= 0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && is_addl_setx && (inst_config[0] == 1'b1))
        addl_h <= inst_baseaddr[4:0];
    end
  end
  always @(posedge clk) begin
    if (reset) begin
      addl_w <= 0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && is_addl_setx && (inst_config[1] == 1'b1))
        addl_w <= inst_baseaddr[9:5];
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      fma_we <= 4'h0;
    end
    else if (en) begin
      if (Sreg == DECODE2 && submod_fmar_en && inst_opcode == NNMICROOPS_OPCODE_SET)
        fma_we <= inst_config[3:0];
    end
  end

  assign is_ctrl_setsel = (submod_ctrl_en && inst_opcode[3:2] == 2'b01);
  always @(posedge clk) begin
    if (reset) begin
      din_sel_reg <= 1'b0;
      glb_sel_reg <= 2'b00;
      relu_sel_reg <= 1'b0;
      smob_sel_reg <= 3'b000;
    end
    else if (en) begin
      if (inst_opcode[1:0] == 2'b00) begin
        din_sel_reg <= inst_config[0:0];
      end
      if (inst_opcode[1:0] == 2'b01) begin
        glb_sel_reg <= inst_config[1:0];
      end
      if (inst_opcode[1:0] == 2'b10) begin
        relu_sel_reg <= inst_config[0:0];
      end
      if (inst_opcode[1:0] == 2'b11) begin
        smob_sel_reg <= inst_config[2:0];
      end
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      ofifo_write_enable <= 1'b0;
    end
    else if (en) begin
      if (Sreg == DECODE2)
        if (submod_ctrl_en && inst_opcode == NNMICROOPS_OPCODE_CTRL_OEN)
          ofifo_write_enable <= 1'b1;
      else if (Sreg == EXECUTION && done_exec)
        ofifo_write_enable <= 1'b0;
    end
  end

  always @(*) begin
    case (smob_sel)
      3'd1: smob_dout_valid = cc_dout_valid       ;
      3'd2: smob_dout_valid = poolavg_dout_valid  ;
      3'd3: smob_dout_valid = dense_dout_valid    ;
      3'd4: smob_dout_valid = addlayer_dout_valid ;
      3'd5: smob_dout_valid = fmap_dout_valid     ;
      3'd6: smob_dout_valid = 1'b1;
      default smob_dout_valid = 1'b0;
    endcase
  end













  assign submod_ctrl_en = submod_en[NNMICROOPS_SUBMOD_CTRL    ];
  assign submod_conv_en = submod_en[NNMICROOPS_SUBMOD_CONV    ];
  assign submod_pool_en = submod_en[NNMICROOPS_SUBMOD_POOLAVG ];
  assign submod_dense_en = submod_en[NNMICROOPS_SUBMOD_DENSE  ];
  assign submod_addl_en = submod_en[NNMICROOPS_SUBMOD_ADDLY   ];
  assign submod_fmar_en = submod_en[NNMICROOPS_SUBMOD_FMAROUND];

  


  assign din_ready = (!instfifo_empty) && (!datafifo_empty);

  assign ram_glb_we    = ;
  assign ram_glb_addr1 = ;
  assign ram_glb_addr2 = ;

  assign instfifo_write = ififo_write ;
  assign instfifo_read  = ififo_read  ;
  assign datafifo_write = dfifo_write ;
  assign datafifo_read  = ;
  assign wbfifo_write   = wfifo_write ;
  assign wbfifo_read    = ;

  assign cc_din0_valid = ;
  assign cc_din1_valid = ;
  assign cc_sum_en = ;
  
  assign poolavg_plty = pool_plty;
  assign poolavg_start     = ;
  assign poolavg_din_valid = ;
  assign poolavg_dout_ready = ;

  assign dense_din_valid  = ;
  assign dense_win_valid  = ;
  assign dense_dout_ready = ;
  
  assign addlayer_height = addl_h;
  assign addlayer_width  = addl_w;
  assign addlayer_start      = ;
  assign addlayer_din_valid  = ;
  assign addlayer_dout_ready = ;

  assign {fmap_d_we, fmap_c_we, fmap_b_we, fmap_a_we} = fma_we;
  assign fmap_din_valid = ;

  assign relu_xin_valid = smob_dout_valid;

  assign ofifo_write = (ofifo_write_enable) ? relu_yout_valid : 1'b0;

  assign din_sel  = din_sel_reg ;
  assign glb_sel  = glb_sel_reg ;
  assign relu_sel = relu_sel_reg;
  assign smob_sel = smob_sel_reg;
endmodule