data/full_repos/permissive/418753455/smart_run/logical/system/cpu_sub_system_ahb.v
1: b"%Error: data/full_repos/permissive/418753455/smart_run/logical/system/cpu_sub_system_ahb.v:291: Cannot find file containing module: 'openE906'\nopenE906  x_e906_top (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418753455/smart_run/logical/system,data/full_repos/permissive/418753455/openE906\n             data/full_repos/permissive/418753455/smart_run/logical/system,data/full_repos/permissive/418753455/openE906.v\n             data/full_repos/permissive/418753455/smart_run/logical/system,data/full_repos/permissive/418753455/openE906.sv\n             openE906\n             openE906.v\n             openE906.sv\n             obj_dir/openE906\n             obj_dir/openE906.v\n             obj_dir/openE906.sv\n%Error: data/full_repos/permissive/418753455/smart_run/logical/system/cpu_sub_system_ahb.v:477: Cannot find file containing module: 'tdt_dmi_top'\ntdt_dmi_top  x_tdt_dmi_top (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/system/cpu_sub_system_ahb.v:585: Cannot find file containing module: 'dahb_mem_ctrl'\ndahb_mem_ctrl  x_dahb_mem_ctrl (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/system/cpu_sub_system_ahb.v:659: Cannot find file containing module: 'iahb_mem_ctrl'\niahb_mem_ctrl  x_iahb_mem_ctrl (\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module cpu_sub_system_ahb(
  biu_pad_haddr,
  biu_pad_hburst,
  biu_pad_hprot,
  biu_pad_hsize,
  biu_pad_htrans,
  biu_pad_hwdata,
  biu_pad_hwrite,
  biu_pad_lpmd_b,
  clk_en,
  corec_pmu_sleep_out,
  cpu_clk,
  had_pad_jtg_tdo,
  nmi_wake_int_lower,
  pad_biu_bigend_b,
  pad_biu_hrdata,
  pad_biu_hready,
  pad_biu_hresp,
  pad_cpu_rst_b,
  pad_had_jtg_tclk,
  pad_had_jtg_tdi,
  pad_had_jtg_tms,
  pad_had_jtg_trst_b,
  pad_vic_int_vld,
  pad_yy_icg_scan_en,
  pad_yy_scan_enable,
  pad_yy_scan_mode,
  pad_yy_scan_rst_b,
  pg_reset_b,
  pmu_corec_isolation,
  pmu_corec_sleep_in,
  sys_rst
);


input            clk_en;                
input            cpu_clk;               
input   [1  :0]  nmi_wake_int_lower;    
input            pad_biu_bigend_b;      
input   [31 :0]  pad_biu_hrdata;        
input            pad_biu_hready;        
input   [1  :0]  pad_biu_hresp;         
input            pad_cpu_rst_b;         
input            pad_had_jtg_tclk;      
input            pad_had_jtg_tdi;       
input            pad_had_jtg_tms;       
input            pad_had_jtg_trst_b;    
input   [31 :0]  pad_vic_int_vld;       
input            pad_yy_icg_scan_en;    
input            pad_yy_scan_enable;    
input            pad_yy_scan_mode;      
input            pad_yy_scan_rst_b;     
input            pg_reset_b;            
input            pmu_corec_isolation;   
input            pmu_corec_sleep_in;    
output  [31 :0]  biu_pad_haddr;         
output  [2  :0]  biu_pad_hburst;        
output  [3  :0]  biu_pad_hprot;         
output  [2  :0]  biu_pad_hsize;         
output  [1  :0]  biu_pad_htrans;        
output  [31 :0]  biu_pad_hwdata;        
output           biu_pad_hwrite;        
output  [1  :0]  biu_pad_lpmd_b;        
output           corec_pmu_sleep_out;   
output           had_pad_jtg_tdo;       
output           sys_rst;               


reg     [1  :0]  biu_addr;              
reg     [1  :0]  biu_size;              
reg              cpu_clk_div2;          
reg     [1  :0]  dahbl_addr;            
reg     [1  :0]  dahbl_size;            
reg     [1  :0]  iahbl_addr;            
reg     [1  :0]  iahbl_size;            
reg     [31 :0]  pad_biu_hrdata_mux;    
reg     [63 :0]  pad_cpu_sys_cnt;       
reg     [31 :0]  pad_dahbl_hrdata_mux;  
reg     [31 :0]  pad_iahbl_hrdata_mux;  


wire    [31 :0]  biu_pad_haddr;         
wire    [2  :0]  biu_pad_hburst;        
wire             biu_pad_hlock;         
wire    [3  :0]  biu_pad_hprot;         
wire    [2  :0]  biu_pad_hsize;         
wire    [1  :0]  biu_pad_htrans;        
wire    [31 :0]  biu_pad_hwdata;        
wire             biu_pad_hwrite;        
wire    [1  :0]  biu_pad_lpmd_b;        
wire             biu_pad_retire;        
wire    [31 :0]  biu_pad_retire_pc;     
wire    [31 :0]  biu_pad_wb1_gpr_data;  
wire             biu_pad_wb1_gpr_en;    
wire    [5  :0]  biu_pad_wb1_gpr_index; 
wire    [31 :0]  biu_pad_wb_gpr_data;   
wire             biu_pad_wb_gpr_en;     
wire    [5  :0]  biu_pad_wb_gpr_index;  
wire             clk_en;                
wire    [31 :0]  cp0_pad_mcause;        
wire    [31 :0]  cp0_pad_mintstatus;    
wire    [31 :0]  cp0_pad_mstatus;       
wire             cpu_clk;               
wire             cpu_pad_dfs_ack;       
wire             cpu_pad_halted;        
wire             cpu_pad_lockup;        
wire    [1  :0]  cpu_pad_soft_rst;      
wire             cpu_rst;               
wire    [31 :0]  dahbl_pad_haddr;       
wire    [2  :0]  dahbl_pad_hburst;      
wire             dahbl_pad_hlock;       
wire    [3  :0]  dahbl_pad_hprot;       
wire    [2  :0]  dahbl_pad_hsize;       
wire    [1  :0]  dahbl_pad_htrans;      
wire    [31 :0]  dahbl_pad_hwdata;      
wire             dahbl_pad_hwrite;      
wire             had_pad_jtg_tdo;       
wire    [31 :0]  iahbl_pad_haddr;       
wire    [2  :0]  iahbl_pad_hburst;      
wire             iahbl_pad_hlock;       
wire    [3  :0]  iahbl_pad_hprot;       
wire    [2  :0]  iahbl_pad_hsize;       
wire    [1  :0]  iahbl_pad_htrans;      
wire    [31 :0]  iahbl_pad_hwdata;      
wire             iahbl_pad_hwrite;      
wire             nmi_req;               
wire    [1  :0]  nmi_wake_int_lower;    
wire             pad_biu_bigend_b;      
wire    [31 :0]  pad_biu_hrdata;        
wire             pad_biu_hready;        
wire    [1  :0]  pad_biu_hresp;         
wire             pad_biu_hresp_0;       
wire    [ 128 - 1 :0]  pad_clic_int_vld;
wire             pad_cpu_dfs_req;       
wire             pad_cpu_ext_int_b;     
wire             pad_cpu_rst_b;         
wire    [31 :0]  pad_dahbl_hrdata;      
wire             pad_dahbl_hready;      
wire    [1  :0]  pad_dahbl_hresp;       
wire             pad_dahbl_hresp_0;     
wire             pad_had_jtg_tclk;      
wire             pad_had_jtg_tdi;       
wire             pad_had_jtg_tms;       
wire             pad_had_jtg_trst_b;    
wire    [31 :0]  pad_iahbl_hrdata;      
wire             pad_iahbl_hready;      
wire    [1  :0]  pad_iahbl_hresp;       
wire             pad_iahbl_hresp_0;     
wire    [31 :0]  pad_vic_int_vld;       
wire             pad_yy_icg_scan_en;    
wire             pad_yy_scan_enable;    
wire             pad_yy_scan_mode;      
wire             pad_yy_scan_rst_b;     
wire             pg_reset_b;            
wire             rtu_pad_inst_split;    
wire    [31 :0]  rtu_pad_wb2_data;      
wire    [5  :0]  rtu_pad_wb2_preg;      
wire             rtu_pad_wb2_vld;       




wire    [4 :0]  rtu_pad_wb_freg;
wire            rtu_pad_wb_freg_vld;


wire    [31:0]  rtu_pad_wb_freg_data;


wire             sys_rst;               
wire             tdt_dm_pad_hartreset_n; 
wire             tdt_dm_pad_ndmreset_n; 
wire    [11 :0]  tdt_dmi_paddr;         
wire             tdt_dmi_penable;       
wire    [31 :0]  tdt_dmi_prdata;        
wire             tdt_dmi_pready;        
wire             tdt_dmi_psel;          
wire             tdt_dmi_pslverr;       
wire    [31 :0]  tdt_dmi_pwdata;        
wire             tdt_dmi_pwrite;        
wire             tdt_dtm_pad_tdo_en;    
wire             tdt_dtm_pad_tms_o;     
wire             tdt_dtm_pad_tms_oe;    
wire             wakeup_req;            


















































































assign pad_clic_int_vld[ 31 : 0] = pad_vic_int_vld[ 31 : 0];

assign pad_clic_int_vld[128 - 1 : 32] = 'h0;

assign pad_cpu_ext_int_b  =1'b1;





openE906  x_e906_top (
  .biu_pad_haddr             (biu_pad_haddr            ),
  .biu_pad_hburst            (biu_pad_hburst           ),
  .biu_pad_hlock             (biu_pad_hlock            ),
  .biu_pad_hprot             (biu_pad_hprot            ),
  .biu_pad_hsize             (biu_pad_hsize            ),
  .biu_pad_htrans            (biu_pad_htrans           ),
  .biu_pad_hwdata            (biu_pad_hwdata           ),
  .biu_pad_hwrite            (biu_pad_hwrite           ),
  .clk_en                    (clk_en                   ),
  .cp0_pad_mcause            (cp0_pad_mcause           ),
  .cp0_pad_mintstatus        (cp0_pad_mintstatus       ),
  .cp0_pad_mstatus           (cp0_pad_mstatus          ),
  .cpu_pad_dfs_ack           (cpu_pad_dfs_ack          ),
  .cpu_pad_halted            (cpu_pad_halted           ),
  .cpu_pad_lockup            (cpu_pad_lockup           ),
  .cpu_pad_soft_rst          (cpu_pad_soft_rst         ),
  .dahbl_pad_haddr           (dahbl_pad_haddr          ),
  .dahbl_pad_hburst          (dahbl_pad_hburst         ),
  .dahbl_pad_hlock           (dahbl_pad_hlock          ),
  .dahbl_pad_hprot           (dahbl_pad_hprot          ),
  .dahbl_pad_hsize           (dahbl_pad_hsize          ),
  .dahbl_pad_htrans          (dahbl_pad_htrans         ),
  .dahbl_pad_hwdata          (dahbl_pad_hwdata         ),
  .dahbl_pad_hwrite          (dahbl_pad_hwrite         ),
  .iahbl_pad_haddr           (iahbl_pad_haddr          ),
  .iahbl_pad_hburst          (iahbl_pad_hburst         ),
  .iahbl_pad_hlock           (iahbl_pad_hlock          ),
  .iahbl_pad_hprot           (iahbl_pad_hprot          ),
  .iahbl_pad_hsize           (iahbl_pad_hsize          ),
  .iahbl_pad_htrans          (iahbl_pad_htrans         ),
  .iahbl_pad_hwdata          (iahbl_pad_hwdata         ),
  .iahbl_pad_hwrite          (iahbl_pad_hwrite         ),
  .pad_biu_hrdata            (pad_biu_hrdata_mux       ),
  .pad_biu_hready            (pad_biu_hready           ),
  .pad_biu_hresp             (pad_biu_hresp_0          ),
  .pad_bmu_dahbl_base        (12'h200                  ),
  .pad_bmu_dahbl_mask        (12'hfff                  ),
  .pad_bmu_iahbl_base        (12'h000                  ),
  .pad_bmu_iahbl_mask        (12'he00                  ),
  .pad_clic_int_vld          (pad_clic_int_vld         ),
  .pad_cpu_dfs_req           (pad_cpu_dfs_req          ),
  .pad_cpu_ext_int_b         (pad_cpu_ext_int_b        ),
  .pad_cpu_nmi               (nmi_req                  ),
  .pad_cpu_rst_addr          (32'h0000_0000            ),
  .pad_cpu_rst_b             (cpu_rst                  ),
  .pad_cpu_sys_cnt           (pad_cpu_sys_cnt          ),
  .pad_cpu_sysmap_addr0      (20'h20000                ),
  .pad_cpu_sysmap_addr0_attr (3'b011                   ),
  .pad_cpu_sysmap_addr1      (20'h30000                ),
  .pad_cpu_sysmap_addr1_attr (3'b011                   ),
  .pad_cpu_sysmap_addr2      (20'h40000                ),
  .pad_cpu_sysmap_addr2_attr (3'b000                   ),
  .pad_cpu_sysmap_addr3      (20'h50000                ),
  .pad_cpu_sysmap_addr3_attr (3'b100                   ),
  .pad_cpu_sysmap_addr4      (20'h60000                ),
  .pad_cpu_sysmap_addr4_attr (3'b000                   ),
  .pad_cpu_sysmap_addr5      (20'h70000                ),
  .pad_cpu_sysmap_addr5_attr (3'b100                   ),
  .pad_cpu_sysmap_addr6      (20'he0000                ),
  .pad_cpu_sysmap_addr6_attr (3'b000                   ),
  .pad_cpu_sysmap_addr7      (20'hfffff                ),
  .pad_cpu_sysmap_addr7_attr (3'b100                   ),
  .pad_cpu_tcip_base         (32'he000_0000            ),
  .pad_cpu_wakeup_event      (wakeup_req               ),
  .pad_dahbl_hrdata          (pad_dahbl_hrdata_mux     ),
  .pad_dahbl_hready          (pad_dahbl_hready         ),
  .pad_dahbl_hresp           (pad_dahbl_hresp_0        ),
  .pad_iahbl_hrdata          (pad_iahbl_hrdata_mux     ),
  .pad_iahbl_hready          (pad_iahbl_hready         ),
  .pad_iahbl_hresp           (pad_iahbl_hresp_0        ),
  .pad_tdt_dm_core_unavail   (1'b0                     ),
  .pad_yy_icg_scan_en        (pad_yy_icg_scan_en       ),
  .pad_yy_scan_enable        (pad_yy_scan_enable       ),
  .pad_yy_scan_mode          (pad_yy_scan_mode         ),
  .pad_yy_scan_rst_b         (pad_yy_scan_rst_b        ),
  .pll_core_cpuclk           (cpu_clk                  ),
  .rtu_pad_inst_retire       (biu_pad_retire           ),
  .rtu_pad_inst_split        (rtu_pad_inst_split       ),
  .rtu_pad_retire_pc         (biu_pad_retire_pc        ),
  .rtu_pad_wb0_data          (biu_pad_wb_gpr_data      ),
  .rtu_pad_wb0_preg          (biu_pad_wb_gpr_index     ),
  .rtu_pad_wb0_vld           (biu_pad_wb_gpr_en        ),
  .rtu_pad_wb1_data          (biu_pad_wb1_gpr_data     ),
  .rtu_pad_wb1_preg          (biu_pad_wb1_gpr_index    ),
  .rtu_pad_wb1_vld           (biu_pad_wb1_gpr_en       ),
  .rtu_pad_wb2_data          (rtu_pad_wb2_data         ),
  .rtu_pad_wb2_preg          (rtu_pad_wb2_preg         ),
  .rtu_pad_wb2_vld           (rtu_pad_wb2_vld          ),

  .rtu_pad_wb_freg           (rtu_pad_wb_freg          ),
.rtu_pad_wb_freg_data      (rtu_pad_wb_freg_data     ),
.rtu_pad_wb_freg_vld       (rtu_pad_wb_freg_vld      ),





  .sys_apb_clk               (cpu_clk_div2             ),
  .sys_apb_rst_b             (pad_cpu_rst_b            ),
  .sysio_pad_lpmd_b          (biu_pad_lpmd_b           ),
  .tdt_dm_pad_hartreset_n    (tdt_dm_pad_hartreset_n   ),
  .tdt_dm_pad_ndmreset_n     (tdt_dm_pad_ndmreset_n    ),

  

  

  .pad_yy_dft_clk_rst_b      (1'b1                     ),


  .tdt_dmi_paddr             (tdt_dmi_paddr            ),
  .tdt_dmi_penable           (tdt_dmi_penable          ),
  .tdt_dmi_prdata            (tdt_dmi_prdata           ),
  .tdt_dmi_pready            (tdt_dmi_pready           ),
  .tdt_dmi_psel              (tdt_dmi_psel             ),
  .tdt_dmi_pslverr           (tdt_dmi_pslverr          ),
  .tdt_dmi_pwdata            (tdt_dmi_pwdata           ),
  .tdt_dmi_pwrite            (tdt_dmi_pwrite           )
);























































        
always@(posedge cpu_clk or negedge pad_cpu_rst_b) begin
  if(!pad_cpu_rst_b)
    cpu_clk_div2 <= 1'b0;
  else
    cpu_clk_div2 <= ~cpu_clk_div2;
end




tdt_dmi_top  x_tdt_dmi_top (
`ifdef SELECT_2_WIRE_JTAG
  .pad_tdt_dtm_jtag2_sel (1'b1                 ),
`else
  .pad_tdt_dtm_jtag2_sel (1'b0                 ),
`endif
  .pad_tdt_dtm_tap_en    (1'b1                 ),
  .pad_tdt_dtm_tclk      (pad_had_jtg_tclk     ),
  .pad_tdt_dtm_tdi       (pad_had_jtg_tdi      ),
  .pad_tdt_dtm_tms_i     (pad_had_jtg_tms      ),
  .pad_tdt_dtm_trst_b    (pad_had_jtg_trst_b   ),
  .pad_tdt_icg_scan_en   (1'b0                 ),
  .pad_yy_scan_mode      (1'b0                 ),
  .pad_yy_scan_rst_b     (1'b1                 ),
  .sys_apb_clk           (cpu_clk_div2         ),
  .sys_apb_rst_b         (pad_cpu_rst_b        ),
  .tdt_dmi_paddr         (tdt_dmi_paddr        ),
  .tdt_dmi_penable       (tdt_dmi_penable      ),
  .tdt_dmi_prdata        (tdt_dmi_prdata       ),
  .tdt_dmi_pready        (tdt_dmi_pready       ),
  .tdt_dmi_psel          (tdt_dmi_psel         ),
  .tdt_dmi_pslverr       (tdt_dmi_pslverr      ),
  .tdt_dmi_pwdata        (tdt_dmi_pwdata       ),
  .tdt_dmi_pwrite        (tdt_dmi_pwrite       ),
  .tdt_dtm_pad_tdo       (had_pad_jtg_tdo      ),
  .tdt_dtm_pad_tdo_en    (tdt_dtm_pad_tdo_en   ),
  .tdt_dtm_pad_tms_o     (tdt_dtm_pad_tms_o    ),
  .tdt_dtm_pad_tms_oe    (tdt_dtm_pad_tms_oe   )
);






















assign pad_cpu_dfs_req = 0;
assign nmi_req = nmi_wake_int_lower[0];
assign wakeup_req = nmi_wake_int_lower[1];


always@(posedge cpu_clk or negedge pg_reset_b)
begin
  if (!pg_reset_b)
    pad_cpu_sys_cnt[63:0] <= 64'b0;
  else
    pad_cpu_sys_cnt[63:0] <= pad_cpu_sys_cnt[63:0] + 1'b1;
end

assign cpu_rst = pg_reset_b & tdt_dm_pad_hartreset_n;
assign sys_rst = tdt_dm_pad_ndmreset_n;












assign pad_biu_hresp_0 = pad_biu_hresp[0];
always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      biu_size[1:0] <= 2'h2;
      biu_addr[1:0] <= 2'b0;
    end
    else if((biu_pad_htrans == 2) && (!biu_pad_hwrite) && pad_biu_hready) begin
      biu_size[1:0] <= biu_pad_hsize[1:0];
      biu_addr[1:0] <= biu_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({biu_size[1:0],biu_addr[1:0]})
        4'b0000:pad_biu_hrdata_mux[31:0] = {24'h0,pad_biu_hrdata[7:0]};
        4'b0001:pad_biu_hrdata_mux[31:0] = {16'h0,pad_biu_hrdata[15:8],8'h0};
        4'b0010:pad_biu_hrdata_mux[31:0] = {8'h0,pad_biu_hrdata[23:16],16'h0};
        4'b0011:pad_biu_hrdata_mux[31:0] = {pad_biu_hrdata[31:24],24'h0};
        4'b0100: pad_biu_hrdata_mux[31:0] = {16'h0,pad_biu_hrdata[15:0]};
        4'b0110: pad_biu_hrdata_mux[31:0] = {pad_biu_hrdata[31:16],16'h0};
        4'b1000: pad_biu_hrdata_mux[31:0] = pad_biu_hrdata[31:0];
        default: pad_biu_hrdata_mux[31:0] = 32'h0;
    endcase
end





dahb_mem_ctrl  x_dahb_mem_ctrl (
  .lite_mmc_hsel       (dahbl_pad_htrans[1]),
  .lite_yy_haddr       (dahbl_pad_haddr    ),
  .lite_yy_hsize       (dahbl_pad_hsize    ),
  .lite_yy_htrans      (dahbl_pad_htrans   ),
  .lite_yy_hwdata      (dahbl_pad_hwdata   ),
  .lite_yy_hwrite      (dahbl_pad_hwrite   ),
  .mmc_lite_hrdata     (pad_dahbl_hrdata   ),
  .mmc_lite_hready     (pad_dahbl_hready   ),
  .mmc_lite_hresp      (pad_dahbl_hresp    ),
  .pad_biu_bigend_b    (pad_biu_bigend_b   ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pll_core_cpuclk     (cpu_clk            )
);














assign pad_dahbl_hresp_0 = pad_dahbl_hresp[0];


always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      dahbl_size[1:0] <= 2'h2;
      dahbl_addr[1:0] <= 2'b0;
    end
    else if((dahbl_pad_htrans == 2) && (!dahbl_pad_hwrite) && pad_dahbl_hready) begin
      dahbl_size[1:0] <= dahbl_pad_hsize[1:0];
      dahbl_addr[1:0] <= dahbl_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({dahbl_size[1:0],dahbl_addr[1:0]})
        4'b0000:pad_dahbl_hrdata_mux[31:0] = {24'h0,pad_dahbl_hrdata[7:0]};
        4'b0001:pad_dahbl_hrdata_mux[31:0] = {16'h0,pad_dahbl_hrdata[15:8],8'h0};
        4'b0010:pad_dahbl_hrdata_mux[31:0] = {8'h0,pad_dahbl_hrdata[23:16],16'h0};
        4'b0011:pad_dahbl_hrdata_mux[31:0] = {pad_dahbl_hrdata[31:24],24'h0};
        4'b0100: pad_dahbl_hrdata_mux[31:0] = {16'h0,pad_dahbl_hrdata[15:0]};
        4'b0110: pad_dahbl_hrdata_mux[31:0] = {pad_dahbl_hrdata[31:16],16'h0};
        4'b1000: pad_dahbl_hrdata_mux[31:0] = pad_dahbl_hrdata[31:0];
        default: pad_dahbl_hrdata_mux[31:0] = 32'h0;
    endcase
end



















iahb_mem_ctrl  x_iahb_mem_ctrl (
  .lite_mmc_hsel       (iahbl_pad_htrans[1]),
  .lite_yy_haddr       (iahbl_pad_haddr    ),
  .lite_yy_hsize       (iahbl_pad_hsize    ),
  .lite_yy_htrans      (iahbl_pad_htrans   ),
  .lite_yy_hwdata      (iahbl_pad_hwdata   ),
  .lite_yy_hwrite      (iahbl_pad_hwrite   ),
  .mmc_lite_hrdata     (pad_iahbl_hrdata   ),
  .mmc_lite_hready     (pad_iahbl_hready   ),
  .mmc_lite_hresp      (pad_iahbl_hresp    ),
  .pad_biu_bigend_b    (pad_biu_bigend_b   ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pll_core_cpuclk     (cpu_clk            )
);













assign pad_iahbl_hresp_0 = pad_iahbl_hresp[0];
always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      iahbl_size[1:0] <= 2'h2;
      iahbl_addr[1:0] <= 2'b0;
    end
    else if((iahbl_pad_htrans == 2) && (!iahbl_pad_hwrite) && pad_iahbl_hready) begin
      iahbl_size[1:0] <= iahbl_pad_hsize[1:0];
      iahbl_addr[1:0] <= iahbl_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({iahbl_size[1:0],iahbl_addr[1:0]})
        4'b0000:pad_iahbl_hrdata_mux[31:0] = {24'h0,pad_iahbl_hrdata[7:0]};
        4'b0001:pad_iahbl_hrdata_mux[31:0] = {16'h0,pad_iahbl_hrdata[15:8],8'h0};
        4'b0010:pad_iahbl_hrdata_mux[31:0] = {8'h0,pad_iahbl_hrdata[23:16],16'h0};
        4'b0011:pad_iahbl_hrdata_mux[31:0] = {pad_iahbl_hrdata[31:24],24'h0};
        4'b0100: pad_iahbl_hrdata_mux[31:0] = {16'h0,pad_iahbl_hrdata[15:0]};
        4'b0110: pad_iahbl_hrdata_mux[31:0] = {pad_iahbl_hrdata[31:16],16'h0};
        4'b1000: pad_iahbl_hrdata_mux[31:0] = pad_iahbl_hrdata[31:0];
        default: pad_iahbl_hrdata_mux[31:0] = 32'h0;
    endcase
end




























endmodule
module cpu_sub_system_ahb(
  biu_pad_haddr,
  biu_pad_hburst,
  biu_pad_hprot,
  biu_pad_hsize,
  biu_pad_htrans,
  biu_pad_hwdata,
  biu_pad_hwrite,
  biu_pad_lpmd_b,
  clk_en,
  corec_pmu_sleep_out,
  cpu_clk,
  had_pad_jtg_tdo,
  nmi_wake_int_lower,
  pad_biu_bigend_b,
  pad_biu_hrdata,
  pad_biu_hready,
  pad_biu_hresp,
  pad_cpu_rst_b,
  pad_had_jtg_tclk,
  pad_had_jtg_tdi,
  pad_had_jtg_tms,
  pad_had_jtg_trst_b,
  pad_vic_int_vld,
  pad_yy_icg_scan_en,
  pad_yy_scan_enable,
  pad_yy_scan_mode,
  pad_yy_scan_rst_b,
  pg_reset_b,
  pmu_corec_isolation,
  pmu_corec_sleep_in,
  sys_rst
);



input            clk_en;                
input            cpu_clk;               
input   [1  :0]  nmi_wake_int_lower;    
input            pad_biu_bigend_b;      
input   [31 :0]  pad_biu_hrdata;        
input            pad_biu_hready;        
input   [1  :0]  pad_biu_hresp;         
input            pad_cpu_rst_b;         
input            pad_had_jtg_tclk;      
input            pad_had_jtg_tdi;       
input            pad_had_jtg_tms;       
input            pad_had_jtg_trst_b;    
input   [31 :0]  pad_vic_int_vld;       
input            pad_yy_icg_scan_en;    
input            pad_yy_scan_enable;    
input            pad_yy_scan_mode;      
input            pad_yy_scan_rst_b;     
input            pg_reset_b;            
input            pmu_corec_isolation;   
input            pmu_corec_sleep_in;    
output  [31 :0]  biu_pad_haddr;         
output  [2  :0]  biu_pad_hburst;        
output  [3  :0]  biu_pad_hprot;         
output  [2  :0]  biu_pad_hsize;         
output  [1  :0]  biu_pad_htrans;        
output  [31 :0]  biu_pad_hwdata;        
output           biu_pad_hwrite;        
output  [1  :0]  biu_pad_lpmd_b;        
output           corec_pmu_sleep_out;   
output           had_pad_jtg_tdo;       
output           sys_rst;               


reg     [1  :0]  biu_addr;              
reg     [1  :0]  biu_size;              
reg              cpu_clk_div2;          
reg     [1  :0]  dahbl_addr;            
reg     [1  :0]  dahbl_size;            
reg     [1  :0]  iahbl_addr;            
reg     [1  :0]  iahbl_size;            
reg     [31 :0]  pad_biu_hrdata_mux;    
reg     [63 :0]  pad_cpu_sys_cnt;       
reg     [31 :0]  pad_dahbl_hrdata_mux;  
reg     [31 :0]  pad_iahbl_hrdata_mux;  


wire    [31 :0]  biu_pad_haddr;         
wire    [2  :0]  biu_pad_hburst;        
wire             biu_pad_hlock;         
wire    [3  :0]  biu_pad_hprot;         
wire    [2  :0]  biu_pad_hsize;         
wire    [1  :0]  biu_pad_htrans;        
wire    [31 :0]  biu_pad_hwdata;        
wire             biu_pad_hwrite;        
wire    [1  :0]  biu_pad_lpmd_b;        
wire             biu_pad_retire;        
wire    [31 :0]  biu_pad_retire_pc;     
wire    [31 :0]  biu_pad_wb1_gpr_data;  
wire             biu_pad_wb1_gpr_en;    
wire    [5  :0]  biu_pad_wb1_gpr_index; 
wire    [31 :0]  biu_pad_wb_gpr_data;   
wire             biu_pad_wb_gpr_en;     
wire    [5  :0]  biu_pad_wb_gpr_index;  
wire             clk_en;                
wire    [31 :0]  cp0_pad_mcause;        
wire    [31 :0]  cp0_pad_mintstatus;    
wire    [31 :0]  cp0_pad_mstatus;       
wire             cpu_clk;               
wire             cpu_pad_dfs_ack;       
wire             cpu_pad_halted;        
wire             cpu_pad_lockup;        
wire    [1  :0]  cpu_pad_soft_rst;      
wire             cpu_rst;               
wire    [31 :0]  dahbl_pad_haddr;       
wire    [2  :0]  dahbl_pad_hburst;      
wire             dahbl_pad_hlock;       
wire    [3  :0]  dahbl_pad_hprot;       
wire    [2  :0]  dahbl_pad_hsize;       
wire    [1  :0]  dahbl_pad_htrans;      
wire    [31 :0]  dahbl_pad_hwdata;      
wire             dahbl_pad_hwrite;      
wire             had_pad_jtg_tdo;       
wire    [31 :0]  iahbl_pad_haddr;       
wire    [2  :0]  iahbl_pad_hburst;      
wire             iahbl_pad_hlock;       
wire    [3  :0]  iahbl_pad_hprot;       
wire    [2  :0]  iahbl_pad_hsize;       
wire    [1  :0]  iahbl_pad_htrans;      
wire    [31 :0]  iahbl_pad_hwdata;      
wire             iahbl_pad_hwrite;      
wire             nmi_req;               
wire    [1  :0]  nmi_wake_int_lower;    
wire             pad_biu_bigend_b;      
wire    [31 :0]  pad_biu_hrdata;        
wire             pad_biu_hready;        
wire    [1  :0]  pad_biu_hresp;         
wire             pad_biu_hresp_0;       
wire    [ 128 - 1 :0]  pad_clic_int_vld;
wire             pad_cpu_dfs_req;       
wire             pad_cpu_ext_int_b;     
wire             pad_cpu_rst_b;         
wire    [31 :0]  pad_dahbl_hrdata;      
wire             pad_dahbl_hready;      
wire    [1  :0]  pad_dahbl_hresp;       
wire             pad_dahbl_hresp_0;     
wire             pad_had_jtg_tclk;      
wire             pad_had_jtg_tdi;       
wire             pad_had_jtg_tms;       
wire             pad_had_jtg_trst_b;    
wire    [31 :0]  pad_iahbl_hrdata;      
wire             pad_iahbl_hready;      
wire    [1  :0]  pad_iahbl_hresp;       
wire             pad_iahbl_hresp_0;     
wire    [31 :0]  pad_vic_int_vld;       
wire             pad_yy_icg_scan_en;    
wire             pad_yy_scan_enable;    
wire             pad_yy_scan_mode;      
wire             pad_yy_scan_rst_b;     
wire             pg_reset_b;            
wire             rtu_pad_inst_split;    
wire    [31 :0]  rtu_pad_wb2_data;      
wire    [5  :0]  rtu_pad_wb2_preg;      
wire             rtu_pad_wb2_vld;       




wire    [4 :0]  rtu_pad_wb_freg;
wire            rtu_pad_wb_freg_vld;


wire    [31:0]  rtu_pad_wb_freg_data;


wire             sys_rst;               
wire             tdt_dm_pad_hartreset_n; 
wire             tdt_dm_pad_ndmreset_n; 
wire    [11 :0]  tdt_dmi_paddr;         
wire             tdt_dmi_penable;       
wire    [31 :0]  tdt_dmi_prdata;        
wire             tdt_dmi_pready;        
wire             tdt_dmi_psel;          
wire             tdt_dmi_pslverr;       
wire    [31 :0]  tdt_dmi_pwdata;        
wire             tdt_dmi_pwrite;        
wire             tdt_dtm_pad_tdo_en;    
wire             tdt_dtm_pad_tms_o;     
wire             tdt_dtm_pad_tms_oe;    
wire             wakeup_req;            


















































































assign pad_clic_int_vld[ 31 : 0] = pad_vic_int_vld[ 31 : 0];

assign pad_clic_int_vld[128 - 1 : 32] = 'h0;

assign pad_cpu_ext_int_b  =1'b1;





openE906  x_e906_top (
  .biu_pad_haddr             (biu_pad_haddr            ),
  .biu_pad_hburst            (biu_pad_hburst           ),
  .biu_pad_hlock             (biu_pad_hlock            ),
  .biu_pad_hprot             (biu_pad_hprot            ),
  .biu_pad_hsize             (biu_pad_hsize            ),
  .biu_pad_htrans            (biu_pad_htrans           ),
  .biu_pad_hwdata            (biu_pad_hwdata           ),
  .biu_pad_hwrite            (biu_pad_hwrite           ),
  .clk_en                    (clk_en                   ),
  .cp0_pad_mcause            (cp0_pad_mcause           ),
  .cp0_pad_mintstatus        (cp0_pad_mintstatus       ),
  .cp0_pad_mstatus           (cp0_pad_mstatus          ),
  .cpu_pad_dfs_ack           (cpu_pad_dfs_ack          ),
  .cpu_pad_halted            (cpu_pad_halted           ),
  .cpu_pad_lockup            (cpu_pad_lockup           ),
  .cpu_pad_soft_rst          (cpu_pad_soft_rst         ),
  .dahbl_pad_haddr           (dahbl_pad_haddr          ),
  .dahbl_pad_hburst          (dahbl_pad_hburst         ),
  .dahbl_pad_hlock           (dahbl_pad_hlock          ),
  .dahbl_pad_hprot           (dahbl_pad_hprot          ),
  .dahbl_pad_hsize           (dahbl_pad_hsize          ),
  .dahbl_pad_htrans          (dahbl_pad_htrans         ),
  .dahbl_pad_hwdata          (dahbl_pad_hwdata         ),
  .dahbl_pad_hwrite          (dahbl_pad_hwrite         ),
  .iahbl_pad_haddr           (iahbl_pad_haddr          ),
  .iahbl_pad_hburst          (iahbl_pad_hburst         ),
  .iahbl_pad_hlock           (iahbl_pad_hlock          ),
  .iahbl_pad_hprot           (iahbl_pad_hprot          ),
  .iahbl_pad_hsize           (iahbl_pad_hsize          ),
  .iahbl_pad_htrans          (iahbl_pad_htrans         ),
  .iahbl_pad_hwdata          (iahbl_pad_hwdata         ),
  .iahbl_pad_hwrite          (iahbl_pad_hwrite         ),
  .pad_biu_hrdata            (pad_biu_hrdata_mux       ),
  .pad_biu_hready            (pad_biu_hready           ),
  .pad_biu_hresp             (pad_biu_hresp_0          ),
  .pad_bmu_dahbl_base        (12'h200                  ),
  .pad_bmu_dahbl_mask        (12'hfff                  ),
  .pad_bmu_iahbl_base        (12'h000                  ),
  .pad_bmu_iahbl_mask        (12'he00                  ),
  .pad_clic_int_vld          (pad_clic_int_vld         ),
  .pad_cpu_dfs_req           (pad_cpu_dfs_req          ),
  .pad_cpu_ext_int_b         (pad_cpu_ext_int_b        ),
  .pad_cpu_nmi               (nmi_req                  ),
  .pad_cpu_rst_addr          (32'h0000_0000            ),
  .pad_cpu_rst_b             (cpu_rst                  ),
  .pad_cpu_sys_cnt           (pad_cpu_sys_cnt          ),
  .pad_cpu_sysmap_addr0      (20'h20000                ),
  .pad_cpu_sysmap_addr0_attr (3'b011                   ),
  .pad_cpu_sysmap_addr1      (20'h30000                ),
  .pad_cpu_sysmap_addr1_attr (3'b011                   ),
  .pad_cpu_sysmap_addr2      (20'h40000                ),
  .pad_cpu_sysmap_addr2_attr (3'b000                   ),
  .pad_cpu_sysmap_addr3      (20'h50000                ),
  .pad_cpu_sysmap_addr3_attr (3'b100                   ),
  .pad_cpu_sysmap_addr4      (20'h60000                ),
  .pad_cpu_sysmap_addr4_attr (3'b000                   ),
  .pad_cpu_sysmap_addr5      (20'h70000                ),
  .pad_cpu_sysmap_addr5_attr (3'b100                   ),
  .pad_cpu_sysmap_addr6      (20'he0000                ),
  .pad_cpu_sysmap_addr6_attr (3'b000                   ),
  .pad_cpu_sysmap_addr7      (20'hfffff                ),
  .pad_cpu_sysmap_addr7_attr (3'b100                   ),
  .pad_cpu_tcip_base         (32'he000_0000            ),
  .pad_cpu_wakeup_event      (wakeup_req               ),
  .pad_dahbl_hrdata          (pad_dahbl_hrdata_mux     ),
  .pad_dahbl_hready          (pad_dahbl_hready         ),
  .pad_dahbl_hresp           (pad_dahbl_hresp_0        ),
  .pad_iahbl_hrdata          (pad_iahbl_hrdata_mux     ),
  .pad_iahbl_hready          (pad_iahbl_hready         ),
  .pad_iahbl_hresp           (pad_iahbl_hresp_0        ),
  .pad_tdt_dm_core_unavail   (1'b0                     ),
  .pad_yy_icg_scan_en        (pad_yy_icg_scan_en       ),
  .pad_yy_scan_enable        (pad_yy_scan_enable       ),
  .pad_yy_scan_mode          (pad_yy_scan_mode         ),
  .pad_yy_scan_rst_b         (pad_yy_scan_rst_b        ),
  .pll_core_cpuclk           (cpu_clk                  ),
  .rtu_pad_inst_retire       (biu_pad_retire           ),
  .rtu_pad_inst_split        (rtu_pad_inst_split       ),
  .rtu_pad_retire_pc         (biu_pad_retire_pc        ),
  .rtu_pad_wb0_data          (biu_pad_wb_gpr_data      ),
  .rtu_pad_wb0_preg          (biu_pad_wb_gpr_index     ),
  .rtu_pad_wb0_vld           (biu_pad_wb_gpr_en        ),
  .rtu_pad_wb1_data          (biu_pad_wb1_gpr_data     ),
  .rtu_pad_wb1_preg          (biu_pad_wb1_gpr_index    ),
  .rtu_pad_wb1_vld           (biu_pad_wb1_gpr_en       ),
  .rtu_pad_wb2_data          (rtu_pad_wb2_data         ),
  .rtu_pad_wb2_preg          (rtu_pad_wb2_preg         ),
  .rtu_pad_wb2_vld           (rtu_pad_wb2_vld          ),

  .rtu_pad_wb_freg           (rtu_pad_wb_freg          ),
.rtu_pad_wb_freg_data      (rtu_pad_wb_freg_data     ),
.rtu_pad_wb_freg_vld       (rtu_pad_wb_freg_vld      ),





  .sys_apb_clk               (cpu_clk_div2             ),
  .sys_apb_rst_b             (pad_cpu_rst_b            ),
  .sysio_pad_lpmd_b          (biu_pad_lpmd_b           ),
  .tdt_dm_pad_hartreset_n    (tdt_dm_pad_hartreset_n   ),
  .tdt_dm_pad_ndmreset_n     (tdt_dm_pad_ndmreset_n    ),

  

  

  .pad_yy_dft_clk_rst_b      (1'b1                     ),


  .tdt_dmi_paddr             (tdt_dmi_paddr            ),
  .tdt_dmi_penable           (tdt_dmi_penable          ),
  .tdt_dmi_prdata            (tdt_dmi_prdata           ),
  .tdt_dmi_pready            (tdt_dmi_pready           ),
  .tdt_dmi_psel              (tdt_dmi_psel             ),
  .tdt_dmi_pslverr           (tdt_dmi_pslverr          ),
  .tdt_dmi_pwdata            (tdt_dmi_pwdata           ),
  .tdt_dmi_pwrite            (tdt_dmi_pwrite           )
);























































        
always@(posedge cpu_clk or negedge pad_cpu_rst_b) begin
  if(!pad_cpu_rst_b)
    cpu_clk_div2 <= 1'b0;
  else
    cpu_clk_div2 <= ~cpu_clk_div2;
end




tdt_dmi_top  x_tdt_dmi_top (
`ifdef SELECT_2_WIRE_JTAG
  .pad_tdt_dtm_jtag2_sel (1'b1                 ),
`else
  .pad_tdt_dtm_jtag2_sel (1'b0                 ),
`endif
  .pad_tdt_dtm_tap_en    (1'b1                 ),
  .pad_tdt_dtm_tclk      (pad_had_jtg_tclk     ),
  .pad_tdt_dtm_tdi       (pad_had_jtg_tdi      ),
  .pad_tdt_dtm_tms_i     (pad_had_jtg_tms      ),
  .pad_tdt_dtm_trst_b    (pad_had_jtg_trst_b   ),
  .pad_tdt_icg_scan_en   (1'b0                 ),
  .pad_yy_scan_mode      (1'b0                 ),
  .pad_yy_scan_rst_b     (1'b1                 ),
  .sys_apb_clk           (cpu_clk_div2         ),
  .sys_apb_rst_b         (pad_cpu_rst_b        ),
  .tdt_dmi_paddr         (tdt_dmi_paddr        ),
  .tdt_dmi_penable       (tdt_dmi_penable      ),
  .tdt_dmi_prdata        (tdt_dmi_prdata       ),
  .tdt_dmi_pready        (tdt_dmi_pready       ),
  .tdt_dmi_psel          (tdt_dmi_psel         ),
  .tdt_dmi_pslverr       (tdt_dmi_pslverr      ),
  .tdt_dmi_pwdata        (tdt_dmi_pwdata       ),
  .tdt_dmi_pwrite        (tdt_dmi_pwrite       ),
  .tdt_dtm_pad_tdo       (had_pad_jtg_tdo      ),
  .tdt_dtm_pad_tdo_en    (tdt_dtm_pad_tdo_en   ),
  .tdt_dtm_pad_tms_o     (tdt_dtm_pad_tms_o    ),
  .tdt_dtm_pad_tms_oe    (tdt_dtm_pad_tms_oe   )
);






















assign pad_cpu_dfs_req = 0;
assign nmi_req = nmi_wake_int_lower[0];
assign wakeup_req = nmi_wake_int_lower[1];


always@(posedge cpu_clk or negedge pg_reset_b)
begin
  if (!pg_reset_b)
    pad_cpu_sys_cnt[63:0] <= 64'b0;
  else
    pad_cpu_sys_cnt[63:0] <= pad_cpu_sys_cnt[63:0] + 1'b1;
end

assign cpu_rst = pg_reset_b & tdt_dm_pad_hartreset_n;
assign sys_rst = tdt_dm_pad_ndmreset_n;












assign pad_biu_hresp_0 = pad_biu_hresp[0];
always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      biu_size[1:0] <= 2'h2;
      biu_addr[1:0] <= 2'b0;
    end
    else if((biu_pad_htrans == 2) && (!biu_pad_hwrite) && pad_biu_hready) begin
      biu_size[1:0] <= biu_pad_hsize[1:0];
      biu_addr[1:0] <= biu_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({biu_size[1:0],biu_addr[1:0]})
        4'b0000:pad_biu_hrdata_mux[31:0] = {24'h0,pad_biu_hrdata[7:0]};
        4'b0001:pad_biu_hrdata_mux[31:0] = {16'h0,pad_biu_hrdata[15:8],8'h0};
        4'b0010:pad_biu_hrdata_mux[31:0] = {8'h0,pad_biu_hrdata[23:16],16'h0};
        4'b0011:pad_biu_hrdata_mux[31:0] = {pad_biu_hrdata[31:24],24'h0};
        4'b0100: pad_biu_hrdata_mux[31:0] = {16'h0,pad_biu_hrdata[15:0]};
        4'b0110: pad_biu_hrdata_mux[31:0] = {pad_biu_hrdata[31:16],16'h0};
        4'b1000: pad_biu_hrdata_mux[31:0] = pad_biu_hrdata[31:0];
        default: pad_biu_hrdata_mux[31:0] = 32'h0;
    endcase
end





dahb_mem_ctrl  x_dahb_mem_ctrl (
  .lite_mmc_hsel       (dahbl_pad_htrans[1]),
  .lite_yy_haddr       (dahbl_pad_haddr    ),
  .lite_yy_hsize       (dahbl_pad_hsize    ),
  .lite_yy_htrans      (dahbl_pad_htrans   ),
  .lite_yy_hwdata      (dahbl_pad_hwdata   ),
  .lite_yy_hwrite      (dahbl_pad_hwrite   ),
  .mmc_lite_hrdata     (pad_dahbl_hrdata   ),
  .mmc_lite_hready     (pad_dahbl_hready   ),
  .mmc_lite_hresp      (pad_dahbl_hresp    ),
  .pad_biu_bigend_b    (pad_biu_bigend_b   ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pll_core_cpuclk     (cpu_clk            )
);














assign pad_dahbl_hresp_0 = pad_dahbl_hresp[0];


always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      dahbl_size[1:0] <= 2'h2;
      dahbl_addr[1:0] <= 2'b0;
    end
    else if((dahbl_pad_htrans == 2) && (!dahbl_pad_hwrite) && pad_dahbl_hready) begin
      dahbl_size[1:0] <= dahbl_pad_hsize[1:0];
      dahbl_addr[1:0] <= dahbl_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({dahbl_size[1:0],dahbl_addr[1:0]})
        4'b0000:pad_dahbl_hrdata_mux[31:0] = {24'h0,pad_dahbl_hrdata[7:0]};
        4'b0001:pad_dahbl_hrdata_mux[31:0] = {16'h0,pad_dahbl_hrdata[15:8],8'h0};
        4'b0010:pad_dahbl_hrdata_mux[31:0] = {8'h0,pad_dahbl_hrdata[23:16],16'h0};
        4'b0011:pad_dahbl_hrdata_mux[31:0] = {pad_dahbl_hrdata[31:24],24'h0};
        4'b0100: pad_dahbl_hrdata_mux[31:0] = {16'h0,pad_dahbl_hrdata[15:0]};
        4'b0110: pad_dahbl_hrdata_mux[31:0] = {pad_dahbl_hrdata[31:16],16'h0};
        4'b1000: pad_dahbl_hrdata_mux[31:0] = pad_dahbl_hrdata[31:0];
        default: pad_dahbl_hrdata_mux[31:0] = 32'h0;
    endcase
end



















iahb_mem_ctrl  x_iahb_mem_ctrl (
  .lite_mmc_hsel       (iahbl_pad_htrans[1]),
  .lite_yy_haddr       (iahbl_pad_haddr    ),
  .lite_yy_hsize       (iahbl_pad_hsize    ),
  .lite_yy_htrans      (iahbl_pad_htrans   ),
  .lite_yy_hwdata      (iahbl_pad_hwdata   ),
  .lite_yy_hwrite      (iahbl_pad_hwrite   ),
  .mmc_lite_hrdata     (pad_iahbl_hrdata   ),
  .mmc_lite_hready     (pad_iahbl_hready   ),
  .mmc_lite_hresp      (pad_iahbl_hresp    ),
  .pad_biu_bigend_b    (pad_biu_bigend_b   ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pll_core_cpuclk     (cpu_clk            )
);













assign pad_iahbl_hresp_0 = pad_iahbl_hresp[0];
always@(posedge cpu_clk or negedge pg_reset_b)
begin
    if(!pg_reset_b) begin
      iahbl_size[1:0] <= 2'h2;
      iahbl_addr[1:0] <= 2'b0;
    end
    else if((iahbl_pad_htrans == 2) && (!iahbl_pad_hwrite) && pad_iahbl_hready) begin
      iahbl_size[1:0] <= iahbl_pad_hsize[1:0];
      iahbl_addr[1:0] <= iahbl_pad_haddr[1:0];
    end
end
always@(*)
begin
    case({iahbl_size[1:0],iahbl_addr[1:0]})
        4'b0000:pad_iahbl_hrdata_mux[31:0] = {24'h0,pad_iahbl_hrdata[7:0]};
        4'b0001:pad_iahbl_hrdata_mux[31:0] = {16'h0,pad_iahbl_hrdata[15:8],8'h0};
        4'b0010:pad_iahbl_hrdata_mux[31:0] = {8'h0,pad_iahbl_hrdata[23:16],16'h0};
        4'b0011:pad_iahbl_hrdata_mux[31:0] = {pad_iahbl_hrdata[31:24],24'h0};
        4'b0100: pad_iahbl_hrdata_mux[31:0] = {16'h0,pad_iahbl_hrdata[15:0]};
        4'b0110: pad_iahbl_hrdata_mux[31:0] = {pad_iahbl_hrdata[31:16],16'h0};
        4'b1000: pad_iahbl_hrdata_mux[31:0] = pad_iahbl_hrdata[31:0];
        default: pad_iahbl_hrdata_mux[31:0] = 32'h0;
    endcase
end




























endmodule