data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v
1: b"%Error: data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v:58: Cannot find file containing module: 'sgmii_8b10b_decode'\n    sgmii_8b10b_decode sgmii_8b10b_decode\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51896788/ip/enet/rtl,data/full_repos/permissive/51896788/sgmii_8b10b_decode\n             data/full_repos/permissive/51896788/ip/enet/rtl,data/full_repos/permissive/51896788/sgmii_8b10b_decode.v\n             data/full_repos/permissive/51896788/ip/enet/rtl,data/full_repos/permissive/51896788/sgmii_8b10b_decode.sv\n             sgmii_8b10b_decode\n             sgmii_8b10b_decode.v\n             sgmii_8b10b_decode.sv\n             obj_dir/sgmii_8b10b_decode\n             obj_dir/sgmii_8b10b_decode.v\n             obj_dir/sgmii_8b10b_decode.sv\n%Error: data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v:71: Cannot find file containing module: 'sgmii_autoneg'\n    sgmii_autoneg #(.LINK_TIMER(LINK_TIMER)) sgmii_autoneg\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v:105: Cannot find file containing module: 'sgmii_rx_buf'\n    sgmii_rx_buf sgmii_rx_buf\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v:141: Cannot find file containing module: 'sgmii_tx_buf'\n    sgmii_tx_buf #(.LINK_TIMER(LINK_TIMER)) sgmii_tx_buf\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/51896788/ip/enet/rtl/sgmii_tbi.v:161: Cannot find file containing module: 'sgmii_8b10b_encode'\n    sgmii_8b10b_encode sgmii_8b10b_encode\n    ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module sgmii_tbi
(
    input clk_125mhz,
    input rst,

    output reg autoneg_complete,
    output reg [15:0] config_reg,

    output [7:0] gmii_rxd,
    output gmii_rx_dv,
    output gmii_rx_err,

    input [7:0] gmii_txd,
    input gmii_tx_en,
    input gmii_tx_err,

    input tbi_rx_clk,
    input [9:0] tbi_rxd,

    input tbi_tx_clk,
    output [9:0] tbi_txd,

    output [31:0] dbg_rx,
    output [31:0] dbg_tx
);
    parameter LINK_TIMER = 16'd40000;





    wire [7:0] rx_byte;
    wire rx_is_k;
    wire rx_disp_err;
    wire sgmii_autoneg_start;
    wire sgmii_autoneg_ack;
    wire sgmii_autoneg_idle;
    wire sgmii_autoneg_done;
    wire [15:0] sgmii_config;

    wire [9:0] tbi_rxd_flip;

    assign tbi_rxd_flip = {tbi_rxd[0], tbi_rxd[1], tbi_rxd[2],
                           tbi_rxd[3], tbi_rxd[4], tbi_rxd[5],
                           tbi_rxd[6], tbi_rxd[7], tbi_rxd[8],
                           tbi_rxd[9]};

    sgmii_8b10b_decode sgmii_8b10b_decode
    (
        .clk(tbi_rx_clk),

        .sgmii_autoneg_start(sgmii_autoneg_start),

        .ten_bit(tbi_rxd_flip),

        .eight_bit(rx_byte),
        .is_k(rx_is_k),
        .disp_err(rx_disp_err)
    );

    sgmii_autoneg #(.LINK_TIMER(LINK_TIMER)) sgmii_autoneg
    (
        .rst(rst),
        .tbi_rx_clk(tbi_rx_clk),

        .rx_byte(rx_byte),
        .rx_is_k(rx_is_k),
        .rx_disp_err(1'b0),

        .sgmii_autoneg_start(sgmii_autoneg_start),
        .sgmii_autoneg_ack(sgmii_autoneg_ack),
        .sgmii_autoneg_idle(sgmii_autoneg_idle),
        .sgmii_autoneg_done(sgmii_autoneg_done),
        .sgmii_config(sgmii_config)
    );

    always @ (posedge clk_125mhz)
    begin
        autoneg_complete <= sgmii_autoneg_done;
        config_reg <= sgmii_config;
    end







    sgmii_rx_buf sgmii_rx_buf
    (
        .clk_125mhz(clk_125mhz),
        .rst(rst),

        .tbi_rx_clk(tbi_rx_clk),

        .sgmii_autoneg_done(sgmii_autoneg_done),
        .rx_byte(rx_byte),
        .rx_is_k(rx_is_k),

        .gmii_rxd(gmii_rxd),
        .gmii_rx_dv(gmii_rx_dv),
        .gmii_rx_err(gmii_rx_err)
    );





    wire [7:0] tx_byte;
    wire tx_is_k;

    wire [9:0] tbi_txd_flip;

    assign tbi_txd = {tbi_txd_flip[0], tbi_txd_flip[1], tbi_txd_flip[2],
                      tbi_txd_flip[3], tbi_txd_flip[4], tbi_txd_flip[5],
                      tbi_txd_flip[6], tbi_txd_flip[7], tbi_txd_flip[8],
                      tbi_txd_flip[9]};


    sgmii_tx_buf #(.LINK_TIMER(LINK_TIMER)) sgmii_tx_buf
    (
        .clk_125mhz(clk_125mhz),
        .rst(rst),

        .tbi_tx_clk(tbi_tx_clk),

        .sgmii_autoneg_start(sgmii_autoneg_start),
        .sgmii_autoneg_ack(sgmii_autoneg_ack),
        .sgmii_autoneg_idle(sgmii_autoneg_idle),
        .sgmii_autoneg_done(sgmii_autoneg_done),

        .gmii_txd(gmii_txd),
        .gmii_tx_en(gmii_tx_en),
        .gmii_tx_err(gmii_tx_err),

        .tx_byte(tx_byte),
        .tx_is_k(tx_is_k)
    );

    sgmii_8b10b_encode sgmii_8b10b_encode
    (
        .clk(tbi_tx_clk),
        .rst(rst),

        .eight_bit(tx_byte),
        .is_k(tx_is_k),

        .ten_bit(tbi_txd_flip)
    );

    assign dbg_rx = {sgmii_autoneg_done, sgmii_autoneg_idle, sgmii_autoneg_ack, sgmii_autoneg_start,
                     2'd0, rx_disp_err, rx_is_k, rx_byte, 16'd0};

    assign dbg_tx = {4'd0, 3'd0, tx_is_k, tx_byte, 16'd0};

endmodule
module sgmii_tbi
(
    input clk_125mhz,
    input rst,

    output reg autoneg_complete,
    output reg [15:0] config_reg,

    output [7:0] gmii_rxd,
    output gmii_rx_dv,
    output gmii_rx_err,

    input [7:0] gmii_txd,
    input gmii_tx_en,
    input gmii_tx_err,

    input tbi_rx_clk,
    input [9:0] tbi_rxd,

    input tbi_tx_clk,
    output [9:0] tbi_txd,

    output [31:0] dbg_rx,
    output [31:0] dbg_tx
);

    parameter LINK_TIMER = 16'd40000;





    wire [7:0] rx_byte;
    wire rx_is_k;
    wire rx_disp_err;
    wire sgmii_autoneg_start;
    wire sgmii_autoneg_ack;
    wire sgmii_autoneg_idle;
    wire sgmii_autoneg_done;
    wire [15:0] sgmii_config;

    wire [9:0] tbi_rxd_flip;

    assign tbi_rxd_flip = {tbi_rxd[0], tbi_rxd[1], tbi_rxd[2],
                           tbi_rxd[3], tbi_rxd[4], tbi_rxd[5],
                           tbi_rxd[6], tbi_rxd[7], tbi_rxd[8],
                           tbi_rxd[9]};

    sgmii_8b10b_decode sgmii_8b10b_decode
    (
        .clk(tbi_rx_clk),

        .sgmii_autoneg_start(sgmii_autoneg_start),

        .ten_bit(tbi_rxd_flip),

        .eight_bit(rx_byte),
        .is_k(rx_is_k),
        .disp_err(rx_disp_err)
    );

    sgmii_autoneg #(.LINK_TIMER(LINK_TIMER)) sgmii_autoneg
    (
        .rst(rst),
        .tbi_rx_clk(tbi_rx_clk),

        .rx_byte(rx_byte),
        .rx_is_k(rx_is_k),
        .rx_disp_err(1'b0),

        .sgmii_autoneg_start(sgmii_autoneg_start),
        .sgmii_autoneg_ack(sgmii_autoneg_ack),
        .sgmii_autoneg_idle(sgmii_autoneg_idle),
        .sgmii_autoneg_done(sgmii_autoneg_done),
        .sgmii_config(sgmii_config)
    );

    always @ (posedge clk_125mhz)
    begin
        autoneg_complete <= sgmii_autoneg_done;
        config_reg <= sgmii_config;
    end







    sgmii_rx_buf sgmii_rx_buf
    (
        .clk_125mhz(clk_125mhz),
        .rst(rst),

        .tbi_rx_clk(tbi_rx_clk),

        .sgmii_autoneg_done(sgmii_autoneg_done),
        .rx_byte(rx_byte),
        .rx_is_k(rx_is_k),

        .gmii_rxd(gmii_rxd),
        .gmii_rx_dv(gmii_rx_dv),
        .gmii_rx_err(gmii_rx_err)
    );





    wire [7:0] tx_byte;
    wire tx_is_k;

    wire [9:0] tbi_txd_flip;

    assign tbi_txd = {tbi_txd_flip[0], tbi_txd_flip[1], tbi_txd_flip[2],
                      tbi_txd_flip[3], tbi_txd_flip[4], tbi_txd_flip[5],
                      tbi_txd_flip[6], tbi_txd_flip[7], tbi_txd_flip[8],
                      tbi_txd_flip[9]};


    sgmii_tx_buf #(.LINK_TIMER(LINK_TIMER)) sgmii_tx_buf
    (
        .clk_125mhz(clk_125mhz),
        .rst(rst),

        .tbi_tx_clk(tbi_tx_clk),

        .sgmii_autoneg_start(sgmii_autoneg_start),
        .sgmii_autoneg_ack(sgmii_autoneg_ack),
        .sgmii_autoneg_idle(sgmii_autoneg_idle),
        .sgmii_autoneg_done(sgmii_autoneg_done),

        .gmii_txd(gmii_txd),
        .gmii_tx_en(gmii_tx_en),
        .gmii_tx_err(gmii_tx_err),

        .tx_byte(tx_byte),
        .tx_is_k(tx_is_k)
    );

    sgmii_8b10b_encode sgmii_8b10b_encode
    (
        .clk(tbi_tx_clk),
        .rst(rst),

        .eight_bit(tx_byte),
        .is_k(tx_is_k),

        .ten_bit(tbi_txd_flip)
    );

    assign dbg_rx = {sgmii_autoneg_done, sgmii_autoneg_idle, sgmii_autoneg_ack, sgmii_autoneg_start,
                     2'd0, rx_disp_err, rx_is_k, rx_byte, 16'd0};

    assign dbg_tx = {4'd0, 3'd0, tx_is_k, tx_byte, 16'd0};

endmodule