data/full_repos/permissive/514519566/pipeline/src/source/Branch.v
data/verilator_xmls/bd0d1eb8-771f-4371-b96e-9cde12e84217.xml
module Branch(In1, In2, BranchOp, flag, branch_hazard);
    input [31:0] In1, In2;
    input [2:0] BranchOp;
    input [4:0] flag;

    output reg branch_hazard;

    always @(*)
        begin
            case (BranchOp)
                3'h4:
                    branch_hazard <= In1 == In2;
                3'h7:
                    branch_hazard <= ~(In1[31] || | In1);
                3'h6:
                    branch_hazard <= In1[31] || ~| In1;
                3'h1:
                    branch_hazard <= (flag == 5'b00001) ? ~In1[31] :
                        (flag == 5'b0) ? In1[31] : 0;
                3'h5:
                    branch_hazard <= ~(In1 == In2);
                default:
                branch_hazard <= 0;
            endcase
        end

endmodule
module Branch(In1, In2, BranchOp, flag, branch_hazard);

    input [31:0] In1, In2;
    input [2:0] BranchOp;
    input [4:0] flag;

    output reg branch_hazard;

    always @(*)
        begin
            case (BranchOp)
                3'h4:
                    branch_hazard <= In1 == In2;
                3'h7:
                    branch_hazard <= ~(In1[31] || | In1);
                3'h6:
                    branch_hazard <= In1[31] || ~| In1;
                3'h1:
                    branch_hazard <= (flag == 5'b00001) ? ~In1[31] :
                        (flag == 5'b0) ? In1[31] : 0;
                3'h5:
                    branch_hazard <= ~(In1 == In2);
                default:
                branch_hazard <= 0;
            endcase
        end

endmodule