data/full_repos/permissive/523043017/Verilog microcontroller/PC_unit.v
1: b'%Error: Cannot find file containing module: microcontroller,data/full_repos/permissive/523043017\n        ... Looked in:\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.v\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.sv\n             microcontroller,data/full_repos/permissive/523043017\n             microcontroller,data/full_repos/permissive/523043017.v\n             microcontroller,data/full_repos/permissive/523043017.sv\n             obj_dir/microcontroller,data/full_repos/permissive/523043017\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.v\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/523043017/Verilog\n%Error: Cannot find file containing module: microcontroller/PC_unit.v\n%Error: Exiting due to 3 error(s)\n'
module PC_unit(
  input wire clock,
  input wire write,
  input wire [7:0] wdata,
  output reg [7:0] count
);

  reg[7:0] next;

  initial
  begin
	count <= 8'h00;
	next <= 8'h01;
  end

  always @(posedge write)
    next <= wdata;

  always @(posedge clock)
  begin
      count <= next;
      next <= next + 8'h01;
  end

endmodule
module PC_unit(
  input wire clock,
  input wire write,
  input wire [7:0] wdata,
  output reg [7:0] count
);


  reg[7:0] next;

  initial
  begin
	count <= 8'h00;
	next <= 8'h01;
  end

  always @(posedge write)
    next <= wdata;

  always @(posedge clock)
  begin
      count <= next;
      next <= next + 8'h01;
  end

endmodule