data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:183: Signal definition not found, creating implicitly: \'mem2_addr_o\'\n                                                                                                     : ... Suggested alternative: \'mem_addr_o\'\n    assign mem2_addr_o   = wire_mem0_addr + mem0_addr_offset;\n           ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:184: Signal definition not found, creating implicitly: \'mem2_ce_o\'\n                                                                                                     : ... Suggested alternative: \'mem_ce_o\'\n    assign mem2_ce_o     = reg_mem0_ce0;\n           ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:185: Signal definition not found, creating implicitly: \'mem2_we_o\'\n                                                                                                     : ... Suggested alternative: \'mem_we_o\'\n    assign mem2_we_o     = 1\'b1;\n           ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:200: Signal definition not found, creating implicitly: \'finish\'\n                                                                                                     : ... Suggested alternative: \'finish_o\'\n    assign finish = r_finish;\n           ^~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:34: Little bit endian vector: MSB < LSB of bit range: 0:12\n    reg [0:PE_SIZE-2] r_buffer_en;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:35: Little bit endian vector: MSB < LSB of bit range: 0:13\n    wire [0:PE_SIZE-1] buffer_en;\n         ^\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:60: Cannot find file containing module: \'up_counter_v3\'\n    up_counter_v3 #(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER,data/full_repos/permissive/503973366/up_counter_v3\n             data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER,data/full_repos/permissive/503973366/up_counter_v3.v\n             data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER,data/full_repos/permissive/503973366/up_counter_v3.sv\n             up_counter_v3\n             up_counter_v3.v\n             up_counter_v3.sv\n             obj_dir/up_counter_v3\n             obj_dir/up_counter_v3.v\n             obj_dir/up_counter_v3.sv\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:101: Cannot find file containing module: \'Counter\'\n    Counter #(\n    ^~~~~~~\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:125: Cannot find file containing module: \'up_counter_v3\'\n    up_counter_v3#(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:153: Cannot find file containing module: \'up_counter_v4\'\n    up_counter_v4 #(\n    ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:172: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'buffer_index_overflow_check\' generates 3 bits.\n                                                                                                  : ... In instance Ofmap_buffer\n        end else if(buffer_index_overflow_check == buffer_index_overflow) begin\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:183: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'mem0_addr_offset\' generates 4 bits.\n                                                                                                  : ... In instance Ofmap_buffer\n    assign mem2_addr_o   = wire_mem0_addr + mem0_addr_offset;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:183: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                                                  : ... In instance Ofmap_buffer\n    assign mem2_addr_o   = wire_mem0_addr + mem0_addr_offset;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/Convolution/DATA_MOVER/Ofmap_buffer.v:194: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'mem2_addr_o\' generates 1 bits.\n                                                                                                  : ... In instance Ofmap_buffer\n        if(mem2_addr_o == MEM_DEPTH-1) begin\n                       ^~\n%Error: Exiting due to 4 error(s), 10 warning(s)\n'
module Ofmap_buffer # (
    parameter FIFO_DATA_WIDTH = 8,
    parameter PE_SIZE = 14,
    parameter integer MEM_DEPTH = 896,
    parameter integer MEM_ADDR_WIDTH = 10,
    parameter integer MEM_DATA_WIDTH = 112,
    parameter integer OC = 64
)
(
    input clk,
    input rst_n,

    input wire en,
    input wire [(FIFO_DATA_WIDTH)*(PE_SIZE)-1:0] ofmap_row_i,

    output wire [MEM_DATA_WIDTH-1:0] mem_d_o,
    output wire [MEM_ADDR_WIDTH-1:0] mem_addr_o,
    output wire mem_ce_o,
    output wire mem_we_o,
    output wire finish_o
);
    localparam MEM_CNT = (PE_SIZE)*(OC);
    localparam MEM_CNT_ADDR_WIDTH = $clog2(MEM_CNT);

    localparam OVERALL_BUFF_ADDR = $clog2(PE_SIZE*PE_SIZE);
    localparam SINGLE_BUFF_ADDR = $clog2(PE_SIZE);
    localparam OC_ADDR_WIDTH = $clog2(OC);
    localparam  buffer_index_overflow = OC / PE_SIZE;
    localparam  buffer_index_overflow_width = $clog2((OC / PE_SIZE)+1);
    localparam  buffer_index_remainder = (OC % PE_SIZE);
    genvar i;


    reg [0:PE_SIZE-2] r_buffer_en;
    wire [0:PE_SIZE-1] buffer_en;
        generate
            for (i=0; i < PE_SIZE-2; i=i+1) begin 
                always @(posedge clk) begin
                    r_buffer_en[i+1] <= r_buffer_en[i];
                end
            end
        endgenerate

    always @(posedge clk) begin
        r_buffer_en[0] <= en;
    end

        generate
            for (i=1; i < PE_SIZE; i=i+1) begin 
                assign buffer_en[i] = r_buffer_en[i-1]; 
            end
        endgenerate
    assign buffer_en[0] = en;


    wire [(OVERALL_BUFF_ADDR)*(PE_SIZE)-1:0] buffer_addr;
    reg  [(OVERALL_BUFF_ADDR)*(PE_SIZE-1)-1:0] reg_buffer_addr;
    wire buffer_is_done;

    up_counter_v3 #(
        .CNT(PE_SIZE),
        .CNT_WIDTH(OVERALL_BUFF_ADDR),
        .OFFSET(PE_SIZE)
    ) up_counter (
        .clk(clk),
        .rst_n(rst_n),
        .en(buffer_en[0]),
        .cnt_o(buffer_addr[OVERALL_BUFF_ADDR-1:0]),
        .is_done_o(buffer_is_done)
    );

    generate
        for (i=0; i < PE_SIZE-2; i=i+1) begin 
            always @(posedge clk) begin
                reg_buffer_addr[(OVERALL_BUFF_ADDR)*(i+1)+:OVERALL_BUFF_ADDR] <= reg_buffer_addr[OVERALL_BUFF_ADDR*i+:OVERALL_BUFF_ADDR];
            end
        end
    endgenerate
    always @(posedge clk) begin
        reg_buffer_addr[0 +: OVERALL_BUFF_ADDR] <= buffer_addr[0 +: OVERALL_BUFF_ADDR];
    end
    generate
        for (i=1; i < PE_SIZE; i=i+1) begin 
            assign buffer_addr[i*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR] = reg_buffer_addr[(i-1)*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR]; 
        end
    endgenerate

    reg [(FIFO_DATA_WIDTH)*(PE_SIZE)*(PE_SIZE)-1:0] buffer;
    generate
        for (i=0; i < PE_SIZE; i=i+1) begin 
            always @(posedge clk) begin
                if(buffer_en[i]) begin
                    buffer[(i+buffer_addr[i*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR])+FIFO_DATA_WIDTH-:FIFO_DATA_WIDTH] <= ofmap_row_i[(FIFO_DATA_WIDTH)*(PE_SIZE)-1-(i*FIFO_DATA_WIDTH)-:FIFO_DATA_WIDTH];
                end
            end
        end
    endgenerate


    wire data_mover_done;
    Counter #(
        .COUNT_NUM(OC-1)
    ) Counter_for_mem0_wait (
        .clk(clk),
        .rst_n(rst_n),
        .start_i(buffer_is_done),
        .done_o(data_mover_done)
    );

    reg reg_mem0_ce0;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            reg_mem0_ce0 <= 0;
        end else if(data_mover_done) begin
            reg_mem0_ce0 <= 0;
        end else if(buffer_is_done) begin
            reg_mem0_ce0 <= 1'b1;
        end
    end


    wire [MEM_ADDR_WIDTH-1:0] wire_mem0_addr;
    reg  [SINGLE_BUFF_ADDR-1:0] mem0_addr_offset;
    wire offset_up;
    up_counter_v3#(
        .CNT(OC),
        .CNT_WIDTH(MEM_ADDR_WIDTH),
        .OFFSET(PE_SIZE)
    ) up_counter_for_mem0_addr (
        .clk(clk),
        .rst_n(rst_n),
        .en(reg_mem0_ce0),
        .cnt_o(wire_mem0_addr),
        .is_done_o(offset_up)
    );    

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            mem0_addr_offset <= 0;
        end else if(offset_up) begin
            mem0_addr_offset <= mem0_addr_offset + 1;
        end else if(mem0_addr_offset == PE_SIZE) begin
            mem0_addr_offset <= 0;
        end
    end

    wire [OVERALL_BUFF_ADDR-1:0] buffer_index;
    wire buffer_index_done_1;
    wire buffer_index_done_2;

    reg         [buffer_index_overflow_width-1:0] buffer_index_overflow_check;
    reg         buffer_index_sel;
    up_counter_v4 #(
        .CNT_1(PE_SIZE),
        .CNT_2(buffer_index_remainder),
        .CNT_WIDTH(OVERALL_BUFF_ADDR),
        .OFFSET(PE_SIZE)
    ) up_counter_for_buffer_index (
        .clk(clk),
        .rst_n(rst_n),
        .en(reg_mem0_ce0),
        .sel(buffer_index_sel),
        .cnt_o(buffer_index),
        .is_done_o_1(buffer_index_done_1),
        .is_done_o_2(buffer_index_done_2)
    );

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 0;
        end else if(buffer_index_overflow_check == buffer_index_overflow) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 1;
        end else if(buffer_index_done_2) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 0;
        end else if(buffer_index_done_1) begin
            buffer_index_overflow_check <= buffer_index_overflow_check + 1;
        end
    end    

    assign mem2_addr_o   = wire_mem0_addr + mem0_addr_offset;
    assign mem2_ce_o     = reg_mem0_ce0;
    assign mem2_we_o     = 1'b1;
    generate
        for (i=0; i < PE_SIZE; i=i+1) begin   
            assign mem_d_o[(PE_SIZE)*(FIFO_DATA_WIDTH)-1-(i*(FIFO_DATA_WIDTH))-: FIFO_DATA_WIDTH] = buffer[buffer_index + i*(FIFO_DATA_WIDTH)-1-:FIFO_DATA_WIDTH];
        end
    endgenerate

    reg r_finish;
    always @(*) begin
        if(mem2_addr_o == MEM_DEPTH-1) begin
            r_finish <= 1'b1;
        end else begin
            r_finish <= 1'b0;
        end
    end
    assign finish = r_finish;
endmodule
module Ofmap_buffer # (
    parameter FIFO_DATA_WIDTH = 8,
    parameter PE_SIZE = 14,
    parameter integer MEM_DEPTH = 896,
    parameter integer MEM_ADDR_WIDTH = 10,
    parameter integer MEM_DATA_WIDTH = 112,
    parameter integer OC = 64
)
(
    input clk,
    input rst_n,

    input wire en,
    input wire [(FIFO_DATA_WIDTH)*(PE_SIZE)-1:0] ofmap_row_i,

    output wire [MEM_DATA_WIDTH-1:0] mem_d_o,
    output wire [MEM_ADDR_WIDTH-1:0] mem_addr_o,
    output wire mem_ce_o,
    output wire mem_we_o,
    output wire finish_o
);

    localparam MEM_CNT = (PE_SIZE)*(OC);
    localparam MEM_CNT_ADDR_WIDTH = $clog2(MEM_CNT);

    localparam OVERALL_BUFF_ADDR = $clog2(PE_SIZE*PE_SIZE);
    localparam SINGLE_BUFF_ADDR = $clog2(PE_SIZE);
    localparam OC_ADDR_WIDTH = $clog2(OC);
    localparam  buffer_index_overflow = OC / PE_SIZE;
    localparam  buffer_index_overflow_width = $clog2((OC / PE_SIZE)+1);
    localparam  buffer_index_remainder = (OC % PE_SIZE);
    genvar i;


    reg [0:PE_SIZE-2] r_buffer_en;
    wire [0:PE_SIZE-1] buffer_en;
        generate
            for (i=0; i < PE_SIZE-2; i=i+1) begin 
                always @(posedge clk) begin
                    r_buffer_en[i+1] <= r_buffer_en[i];
                end
            end
        endgenerate

    always @(posedge clk) begin
        r_buffer_en[0] <= en;
    end

        generate
            for (i=1; i < PE_SIZE; i=i+1) begin 
                assign buffer_en[i] = r_buffer_en[i-1]; 
            end
        endgenerate
    assign buffer_en[0] = en;


    wire [(OVERALL_BUFF_ADDR)*(PE_SIZE)-1:0] buffer_addr;
    reg  [(OVERALL_BUFF_ADDR)*(PE_SIZE-1)-1:0] reg_buffer_addr;
    wire buffer_is_done;

    up_counter_v3 #(
        .CNT(PE_SIZE),
        .CNT_WIDTH(OVERALL_BUFF_ADDR),
        .OFFSET(PE_SIZE)
    ) up_counter (
        .clk(clk),
        .rst_n(rst_n),
        .en(buffer_en[0]),
        .cnt_o(buffer_addr[OVERALL_BUFF_ADDR-1:0]),
        .is_done_o(buffer_is_done)
    );

    generate
        for (i=0; i < PE_SIZE-2; i=i+1) begin 
            always @(posedge clk) begin
                reg_buffer_addr[(OVERALL_BUFF_ADDR)*(i+1)+:OVERALL_BUFF_ADDR] <= reg_buffer_addr[OVERALL_BUFF_ADDR*i+:OVERALL_BUFF_ADDR];
            end
        end
    endgenerate
    always @(posedge clk) begin
        reg_buffer_addr[0 +: OVERALL_BUFF_ADDR] <= buffer_addr[0 +: OVERALL_BUFF_ADDR];
    end
    generate
        for (i=1; i < PE_SIZE; i=i+1) begin 
            assign buffer_addr[i*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR] = reg_buffer_addr[(i-1)*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR]; 
        end
    endgenerate

    reg [(FIFO_DATA_WIDTH)*(PE_SIZE)*(PE_SIZE)-1:0] buffer;
    generate
        for (i=0; i < PE_SIZE; i=i+1) begin 
            always @(posedge clk) begin
                if(buffer_en[i]) begin
                    buffer[(i+buffer_addr[i*OVERALL_BUFF_ADDR+:OVERALL_BUFF_ADDR])+FIFO_DATA_WIDTH-:FIFO_DATA_WIDTH] <= ofmap_row_i[(FIFO_DATA_WIDTH)*(PE_SIZE)-1-(i*FIFO_DATA_WIDTH)-:FIFO_DATA_WIDTH];
                end
            end
        end
    endgenerate


    wire data_mover_done;
    Counter #(
        .COUNT_NUM(OC-1)
    ) Counter_for_mem0_wait (
        .clk(clk),
        .rst_n(rst_n),
        .start_i(buffer_is_done),
        .done_o(data_mover_done)
    );

    reg reg_mem0_ce0;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            reg_mem0_ce0 <= 0;
        end else if(data_mover_done) begin
            reg_mem0_ce0 <= 0;
        end else if(buffer_is_done) begin
            reg_mem0_ce0 <= 1'b1;
        end
    end


    wire [MEM_ADDR_WIDTH-1:0] wire_mem0_addr;
    reg  [SINGLE_BUFF_ADDR-1:0] mem0_addr_offset;
    wire offset_up;
    up_counter_v3#(
        .CNT(OC),
        .CNT_WIDTH(MEM_ADDR_WIDTH),
        .OFFSET(PE_SIZE)
    ) up_counter_for_mem0_addr (
        .clk(clk),
        .rst_n(rst_n),
        .en(reg_mem0_ce0),
        .cnt_o(wire_mem0_addr),
        .is_done_o(offset_up)
    );    

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            mem0_addr_offset <= 0;
        end else if(offset_up) begin
            mem0_addr_offset <= mem0_addr_offset + 1;
        end else if(mem0_addr_offset == PE_SIZE) begin
            mem0_addr_offset <= 0;
        end
    end

    wire [OVERALL_BUFF_ADDR-1:0] buffer_index;
    wire buffer_index_done_1;
    wire buffer_index_done_2;

    reg         [buffer_index_overflow_width-1:0] buffer_index_overflow_check;
    reg         buffer_index_sel;
    up_counter_v4 #(
        .CNT_1(PE_SIZE),
        .CNT_2(buffer_index_remainder),
        .CNT_WIDTH(OVERALL_BUFF_ADDR),
        .OFFSET(PE_SIZE)
    ) up_counter_for_buffer_index (
        .clk(clk),
        .rst_n(rst_n),
        .en(reg_mem0_ce0),
        .sel(buffer_index_sel),
        .cnt_o(buffer_index),
        .is_done_o_1(buffer_index_done_1),
        .is_done_o_2(buffer_index_done_2)
    );

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 0;
        end else if(buffer_index_overflow_check == buffer_index_overflow) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 1;
        end else if(buffer_index_done_2) begin
            buffer_index_overflow_check <= 0;
            buffer_index_sel <= 0;
        end else if(buffer_index_done_1) begin
            buffer_index_overflow_check <= buffer_index_overflow_check + 1;
        end
    end    

    assign mem2_addr_o   = wire_mem0_addr + mem0_addr_offset;
    assign mem2_ce_o     = reg_mem0_ce0;
    assign mem2_we_o     = 1'b1;
    generate
        for (i=0; i < PE_SIZE; i=i+1) begin   
            assign mem_d_o[(PE_SIZE)*(FIFO_DATA_WIDTH)-1-(i*(FIFO_DATA_WIDTH))-: FIFO_DATA_WIDTH] = buffer[buffer_index + i*(FIFO_DATA_WIDTH)-1-:FIFO_DATA_WIDTH];
        end
    endgenerate

    reg r_finish;
    always @(*) begin
        if(mem2_addr_o == MEM_DEPTH-1) begin
            r_finish <= 1'b1;
        end else begin
            r_finish <= 1'b0;
        end
    end
    assign finish = r_finish;
endmodule