data/full_repos/permissive/468066752/rtl/ControlUnit.sv
data/verilator_xmls/372f7b85-0a71-4d1e-bdee-053d0f6f2ac9.xml
module ControlUnit (
    input  logic [06:00] opcode,
    input  logic [02:00] func3,
    input  logic [06:00] func7,
    input  logic [31:00] portA,
    input  logic [31:00] portB,
    output logic         RegWrite,
    output logic [01:00] portBSrc,
    output logic [04:00] aluop,
    output logic         stallALU,
    output logic [03:00] stallCycles,
    output logic         memRead,
    output logic         memWrite,
    output logic [01:00] memNoBytes,
    output logic [01:00] busWSel,
    output logic         auipc,
    output logic         jal,
    output logic         jalr,
    output logic         branch
);

  always_comb begin
    RegWrite    = 1'b0;
    portBSrc    = 2'd0;
    aluop       = 5'd0;
    memRead     = 1'b0;
    memWrite    = 1'b0;
    memNoBytes  = 2'd0;
    auipc       = 1'b0;
    jal         = 1'b0;
    jalr        = 1'b0;
    branch      = 1'b0;
    busWSel     = 2'd0;
    stallALU    = 1'b0;
    stallCycles = 4'd0;
    case (opcode)
      7'b0110111:
        begin
          aluop    = 5'd18;
          RegWrite = 1'd1;
          portBSrc = 2'd3;
        end
      7'b0010111:
        begin
          aluop    = 5'd0;
          RegWrite = 1'd1;
          portBSrc = 2'd3;
          auipc    = 1'b1;
        end
      7'b1101111:
        begin
          RegWrite = 1'b1;
          jal      = 1'b1;
          busWSel  = 2'd2;
        end
      7'b1100111:
        begin
          if (func3 == 3'd0) begin
            RegWrite = 1'd1;
            jalr     = 1'b1;
            portBSrc = 2'd1;
            busWSel  = 2'd2;
          end
        end
      7'b1100011:
        begin
          case (func3)
            3'b000:
              begin
                branch = portA == portB;
              end
            3'b001:
              begin
                branch = portA != portB;
              end
            3'b100:
              begin
                branch = $signed(portA) < $signed(portB);
              end
            3'b101:
              begin
                branch = $signed(portA) >= $signed(portB);
              end
            3'b110:
              begin
                branch = portA < portB;
              end
            3'b111:
              begin
                branch = portA >= portB;
              end
            default:
              begin
                branch = 1'b0;
              end
          endcase
        end
      7'b0000011:
        begin
          case (func3)
            3'b000:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b001:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b010:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd2;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b100:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b101:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            default:
              begin
                RegWrite   = 1'b0;
                memRead    = 1'b0;
              end
          endcase
        end
      7'b0100011:
        begin
          case (func3)
            3'b000:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            3'b001:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            3'b010:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd2;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            default:
              begin
                memWrite   = 1'b0;
              end
          endcase
        end
      7'b0010011:
        begin
          case (func3)
            3'b000:
            begin
              aluop      = 5'd0;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b010:
            begin
              aluop      = 5'd2;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b011:
            begin
              aluop      = 5'd3;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b100:
            begin
              aluop      = 5'd6;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b110:
            begin
              aluop      = 5'd5;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b111:
            begin
              aluop      = 5'd4;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b001:
            begin
              aluop      = 5'd7;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b101:
            begin
              if (func7 == 7'd0) begin

                aluop      = 5'd8;
                portBSrc   = 2'd1;
                RegWrite   = 1'b1;
              end
              else begin

                aluop      = 5'd9;
                portBSrc   = 2'd1;
                RegWrite   = 1'b1;
              end
            end
          endcase
        end
      7'b0110011:
        begin
          if (func7 == 7'b0000001) begin
            case (func3)
              3'b000:
                begin
                  aluop       = 5'd10;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b001:
                begin
                  aluop       = 5'd11;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b010:
                begin
                  aluop       = 5'd13;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b011:
                begin
                  aluop       = 5'd12;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b100:
                begin
                  aluop       = 5'd14;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b101:
                begin
                  aluop       = 5'd15;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b110:
                begin
                  aluop       = 5'd16;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b111:
                begin
                  aluop       = 5'd17;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
            endcase
          end
          else begin
            case (func3)
              3'b000:
                begin
                  if (func7 == 7'd0) begin

                    aluop      = 5'd0;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                  else begin

                    aluop      = 5'd1;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                end
              3'b010:
                begin
                  aluop      = 5'd2;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b011:
                begin
                  aluop      = 5'd3;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b100:
                begin
                  aluop      = 5'd6;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b110:
                begin
                  aluop      = 5'd5;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b111:
                begin
                  aluop      = 5'd4;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b001:
                begin
                  aluop      = 5'd7;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b101:
                begin
                  if (func7 == 7'd0) begin

                    aluop      = 5'd8;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                  else begin

                    aluop      = 5'd9;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                end
            endcase
          end
        end
      default:
        begin
          RegWrite    = 1'b0;
          portBSrc    = 2'd0;
          aluop       = 5'd0;
          memRead     = 1'b0;
          memWrite    = 1'b0;
          memNoBytes  = 2'd0;
          auipc       = 1'b0;
          jal         = 1'b0;
          jalr        = 1'b0;
          branch      = 1'b0;
          busWSel     = 2'd0;
          stallALU    = 1'b0;
          stallCycles = 4'd0;
        end
    endcase
  end
endmodule
module ControlUnit (
    input  logic [06:00] opcode,
    input  logic [02:00] func3,
    input  logic [06:00] func7,
    input  logic [31:00] portA,
    input  logic [31:00] portB,
    output logic         RegWrite,
    output logic [01:00] portBSrc,
    output logic [04:00] aluop,
    output logic         stallALU,
    output logic [03:00] stallCycles,
    output logic         memRead,
    output logic         memWrite,
    output logic [01:00] memNoBytes,
    output logic [01:00] busWSel,
    output logic         auipc,
    output logic         jal,
    output logic         jalr,
    output logic         branch
);


  always_comb begin
    RegWrite    = 1'b0;
    portBSrc    = 2'd0;
    aluop       = 5'd0;
    memRead     = 1'b0;
    memWrite    = 1'b0;
    memNoBytes  = 2'd0;
    auipc       = 1'b0;
    jal         = 1'b0;
    jalr        = 1'b0;
    branch      = 1'b0;
    busWSel     = 2'd0;
    stallALU    = 1'b0;
    stallCycles = 4'd0;
    case (opcode)
      7'b0110111:
        begin
          aluop    = 5'd18;
          RegWrite = 1'd1;
          portBSrc = 2'd3;
        end
      7'b0010111:
        begin
          aluop    = 5'd0;
          RegWrite = 1'd1;
          portBSrc = 2'd3;
          auipc    = 1'b1;
        end
      7'b1101111:
        begin
          RegWrite = 1'b1;
          jal      = 1'b1;
          busWSel  = 2'd2;
        end
      7'b1100111:
        begin
          if (func3 == 3'd0) begin
            RegWrite = 1'd1;
            jalr     = 1'b1;
            portBSrc = 2'd1;
            busWSel  = 2'd2;
          end
        end
      7'b1100011:
        begin
          case (func3)
            3'b000:
              begin
                branch = portA == portB;
              end
            3'b001:
              begin
                branch = portA != portB;
              end
            3'b100:
              begin
                branch = $signed(portA) < $signed(portB);
              end
            3'b101:
              begin
                branch = $signed(portA) >= $signed(portB);
              end
            3'b110:
              begin
                branch = portA < portB;
              end
            3'b111:
              begin
                branch = portA >= portB;
              end
            default:
              begin
                branch = 1'b0;
              end
          endcase
        end
      7'b0000011:
        begin
          case (func3)
            3'b000:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b001:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b010:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd2;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b100:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            3'b101:
              begin
                RegWrite   = 1'b1;
                memRead    = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                busWSel    = 2'd1;
                portBSrc   = 2'd1;
              end
            default:
              begin
                RegWrite   = 1'b0;
                memRead    = 1'b0;
              end
          endcase
        end
      7'b0100011:
        begin
          case (func3)
            3'b000:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd0;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            3'b001:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd1;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            3'b010:
              begin
                memWrite   = 1'b1;
                memNoBytes = 2'd2;
                aluop      = 5'd0;
                portBSrc   = 2'd2;
              end
            default:
              begin
                memWrite   = 1'b0;
              end
          endcase
        end
      7'b0010011:
        begin
          case (func3)
            3'b000:
            begin
              aluop      = 5'd0;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b010:
            begin
              aluop      = 5'd2;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b011:
            begin
              aluop      = 5'd3;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b100:
            begin
              aluop      = 5'd6;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b110:
            begin
              aluop      = 5'd5;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b111:
            begin
              aluop      = 5'd4;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b001:
            begin
              aluop      = 5'd7;
              portBSrc   = 2'd1;
              RegWrite   = 1'b1;
            end
            3'b101:
            begin
              if (func7 == 7'd0) begin

                aluop      = 5'd8;
                portBSrc   = 2'd1;
                RegWrite   = 1'b1;
              end
              else begin

                aluop      = 5'd9;
                portBSrc   = 2'd1;
                RegWrite   = 1'b1;
              end
            end
          endcase
        end
      7'b0110011:
        begin
          if (func7 == 7'b0000001) begin
            case (func3)
              3'b000:
                begin
                  aluop       = 5'd10;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b001:
                begin
                  aluop       = 5'd11;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b010:
                begin
                  aluop       = 5'd13;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b011:
                begin
                  aluop       = 5'd12;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd3;
                end
              3'b100:
                begin
                  aluop       = 5'd14;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b101:
                begin
                  aluop       = 5'd15;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b110:
                begin
                  aluop       = 5'd16;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
              3'b111:
                begin
                  aluop       = 5'd17;
                  RegWrite    = 1'b1;
                  stallALU    = 1'b1;
                  stallCycles = 4'd11;
                end
            endcase
          end
          else begin
            case (func3)
              3'b000:
                begin
                  if (func7 == 7'd0) begin

                    aluop      = 5'd0;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                  else begin

                    aluop      = 5'd1;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                end
              3'b010:
                begin
                  aluop      = 5'd2;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b011:
                begin
                  aluop      = 5'd3;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b100:
                begin
                  aluop      = 5'd6;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b110:
                begin
                  aluop      = 5'd5;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b111:
                begin
                  aluop      = 5'd4;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b001:
                begin
                  aluop      = 5'd7;
                  RegWrite   = 1'b1;
                  stallALU    = 1'b0;
                  stallCycles = 4'd0;
                end
              3'b101:
                begin
                  if (func7 == 7'd0) begin

                    aluop      = 5'd8;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                  else begin

                    aluop      = 5'd9;
                    RegWrite   = 1'b1;
                    stallALU    = 1'b0;
                    stallCycles = 4'd0;
                  end
                end
            endcase
          end
        end
      default:
        begin
          RegWrite    = 1'b0;
          portBSrc    = 2'd0;
          aluop       = 5'd0;
          memRead     = 1'b0;
          memWrite    = 1'b0;
          memNoBytes  = 2'd0;
          auipc       = 1'b0;
          jal         = 1'b0;
          jalr        = 1'b0;
          branch      = 1'b0;
          busWSel     = 2'd0;
          stallALU    = 1'b0;
          stallCycles = 4'd0;
        end
    endcase
  end
endmodule