data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/cachelib/v_rtl/dut_Add3u8u8u8_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/cachelib/v_rtl/dut_Add3u8u8u8_1.v:39: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'in3\' generates 8 bits.\n                                                                                                                             : ... In instance dut_Add3u8u8u8_1\n +(in2);\n ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/cachelib/v_rtl/dut_Add3u8u8u8_1.v:39: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in2\' generates 8 bits.\n                                                                                                                             : ... In instance dut_Add3u8u8u8_1\n +(in2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/cachelib/v_rtl/dut_Add3u8u8u8_1.v:41: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in1\' generates 8 bits.\n                                                                                                                             : ... In instance dut_Add3u8u8u8_1\n +(in1);\n ^\n%Error: Exiting due to 3 warning(s)\n'
module dut_Add3u8u8u8_1 (
	in3,
	in2,
	in1,
	out1
	);
input [7:0] in3,
	in2,
	in1;
output [9:0] out1;
wire [9:0] asc001;

wire [9:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in3)
	+(in2);
assign asc001 = asc001_tmp_0
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add3u8u8u8_1 (
	in3,
	in2,
	in1,
	out1
	);

input [7:0] in3,
	in2,
	in1;
output [9:0] out1;
wire [9:0] asc001;

wire [9:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in3)
	+(in2);
assign asc001 = asc001_tmp_0
	+(in1);

assign out1 = asc001;
endmodule