data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/rrarbiter.sv
1: b"%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/rrarbiter.sv:43: Cannot find file containing module: 'rr_arb_tree'\n  rr_arb_tree #(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/rr_arb_tree\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/rr_arb_tree.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/rr_arb_tree.sv\n             rr_arb_tree\n             rr_arb_tree.v\n             rr_arb_tree.sv\n             obj_dir/rr_arb_tree\n             obj_dir/rr_arb_tree.v\n             obj_dir/rr_arb_tree.sv\n%Error: Exiting due to 1 error(s)\n"
module rrarbiter #(
  parameter int unsigned NUM_REQ   = 64,
  parameter bit          LOCK_IN   = 1'b0
) (
  input logic                         clk_i,
  input logic                         rst_ni,

  input logic                         flush_i,
  input logic                         en_i,
  input logic [NUM_REQ-1:0]           req_i,

  output logic [NUM_REQ-1:0]          ack_o,
  output logic                        vld_o,
  output logic [$clog2(NUM_REQ)-1:0]  idx_o
);

  logic req;
  assign vld_o = (|req_i) & en_i;

  rr_arb_tree #(
    .NumIn     ( NUM_REQ ),
    .DataWidth ( 1       ),
    .LockIn    ( LOCK_IN ))
  i_rr_arb_tree (
    .clk_i   ( clk_i      ),
    .rst_ni  ( rst_ni     ),
    .flush_i ( flush_i    ),
    .rr_i    ( '0         ),
    .req_i   ( req_i      ),
    .gnt_o   ( ack_o      ),
    .data_i  ( '0         ),
    .gnt_i   ( en_i & req ),
    .req_o   ( req        ),
    .data_o  (            ),
    .idx_o   ( idx_o      )
  );

endmodule
module rrarbiter #(
  parameter int unsigned NUM_REQ   = 64,
  parameter bit          LOCK_IN   = 1'b0
) (
  input logic                         clk_i,
  input logic                         rst_ni,

  input logic                         flush_i,
  input logic                         en_i,
  input logic [NUM_REQ-1:0]           req_i,

  output logic [NUM_REQ-1:0]          ack_o,
  output logic                        vld_o,
  output logic [$clog2(NUM_REQ)-1:0]  idx_o
);


  logic req;
  assign vld_o = (|req_i) & en_i;

  rr_arb_tree #(
    .NumIn     ( NUM_REQ ),
    .DataWidth ( 1       ),
    .LockIn    ( LOCK_IN ))
  i_rr_arb_tree (
    .clk_i   ( clk_i      ),
    .rst_ni  ( rst_ni     ),
    .flush_i ( flush_i    ),
    .rr_i    ( '0         ),
    .req_i   ( req_i      ),
    .gnt_o   ( ack_o      ),
    .data_i  ( '0         ),
    .gnt_i   ( en_i & req ),
    .req_o   ( req        ),
    .data_o  (            ),
    .idx_o   ( idx_o      )
  );

endmodule