data/full_repos/permissive/445695969/src_rtl/protected/hpc2_1/skinny_sbox8_hpc2_1_str_non_pipelined.v
data/verilator_xmls/9b24d4ff-cfbd-4b53-b0e7-bddb8f507a06.xml
module hpc2_1_str_sbox8_cfn_fr (

   f,

   a, b, z, r, clk
   ) ;
   (*equivalent_register_removal = "no" *)output [1:0]        f;
   (*equivalent_register_removal = "no" *)input [1:0]         a, b, z;
   (*equivalent_register_removal = "no" *)input [1:0]	       r;
   (*equivalent_register_removal = "no" *)input 	       clk;

   (*equivalent_register_removal = "no" *)wire [1:0] 	       x;
   (*equivalent_register_removal = "no" *)reg [1:0] 	       y;
   
   (*equivalent_register_removal = "no" *)reg [7:0] 	       rg;

   assign x = {a[1],~a[0]};
   
   always @ (posedge clk) begin
      y <= {b[1],~b[0]} ^ {r[1],r[1]}; 
      
      rg[0] <= y[0];
      rg[1] <= x[0] & rg[0];
      rg[2] <= r[0] & ~x[0];
      rg[3] <= x[0] & (y[1]^r[0]);

      rg[4] <= y[1];
      rg[5] <= x[1] & rg[4];
      rg[6] <= r[0] & ~x[1];
      rg[7] <= x[1] & (y[0]^r[0]);                 
   end

   assign f[0] = ^rg[3:1] ^ z[0];
   assign f[1] = ^rg[7:5] ^ z[1]; 

endmodule
module hpc2_1_str_sbox8_cfn_fr (

   f,

   a, b, z, r, clk
   ) ;

   (*equivalent_register_removal = "no" *)output [1:0]        f;
   (*equivalent_register_removal = "no" *)input [1:0]         a, b, z;
   (*equivalent_register_removal = "no" *)input [1:0]	       r;
   (*equivalent_register_removal = "no" *)input 	       clk;

   (*equivalent_register_removal = "no" *)wire [1:0] 	       x;
   (*equivalent_register_removal = "no" *)reg [1:0] 	       y;
   
   (*equivalent_register_removal = "no" *)reg [7:0] 	       rg;

   assign x = {a[1],~a[0]};
   
   always @ (posedge clk) begin
      y <= {b[1],~b[0]} ^ {r[1],r[1]}; 
      
      rg[0] <= y[0];
      rg[1] <= x[0] & rg[0];
      rg[2] <= r[0] & ~x[0];
      rg[3] <= x[0] & (y[1]^r[0]);

      rg[4] <= y[1];
      rg[5] <= x[1] & rg[4];
      rg[6] <= r[0] & ~x[1];
      rg[7] <= x[1] & (y[0]^r[0]);                 
   end

   assign f[0] = ^rg[3:1] ^ z[0];
   assign f[1] = ^rg[7:5] ^ z[1]; 

endmodule