data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:100: Little bit endian vector: MSB < LSB of bit range: 0:15\n      wire [0:LUT_DEPTH-1]            lut_lookup_hit;\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:123: Little bit endian vector: MSB < LSB of bit range: 0:15\n      wire [0:LUT_DEPTH-1]            lut_learn_hit;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:139: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 55 bits.\n                                                                                                                                                                     : ... In instance mac_cam_lut\n    lut[i] <= {(NUM_OUTPUT_QUEUES+48-1){1\'b0}};\n           ^~\n%Error: Exiting due to 3 warning(s)\n'
function integer log2;
    input integer number;
    begin
      log2=0;
      while(2**log2<number) begin
      log2=log2+1;
      end
    end
  endfunction
function integer log2;

    input integer number;
    begin
      log2=0;
      while(2**log2<number) begin
      log2=log2+1;
      end
    end
  endfunction