data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #OFFSET\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #1000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:30: Cannot find file containing module: \'TopLevel\'\nTopLevel UUT (.clkin(clkin), .btnU(btnU), .btnD(btnD), .btnL(btnL), .btnR(btnR), .sw(sw),\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/TopLevel\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/TopLevel.v\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/TopLevel.sv\n             TopLevel\n             TopLevel.v\n             TopLevel.sv\n             obj_dir/TopLevel\n             obj_dir/TopLevel.v\n             obj_dir/TopLevel.sv\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/TopLevel_sim.v:54: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                       : ... In instance TopLevel_sim\n   sw[15:0] = 1\'b0;\n            ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TopLevel_sim();

reg clkin, btnU, btnD, btnL, btnR;
reg [15:0] sw;
wire Hsync, Vsync;
wire [3:0] vgaRed, vgaBlue, vgaGreen;

TopLevel UUT (.clkin(clkin), .btnU(btnU), .btnD(btnD), .btnL(btnL), .btnR(btnR), .sw(sw),
              .Hsync(Hsync), .Vsync(Vsync), .vgaRed(vgaRed), .vgaBlue(vgaBlue), .vgaGreen(vgaGreen));


parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clkin = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;
        end
	end
	
   initial
   begin
   btnU = 1'b0;
   btnD = 1'b0;
   btnR = 1'b0;
   btnL = 1'b0;
   sw[15:0] = 1'b0;
   #1000;
   sw[1] = 1'b1;
   #100;
   sw[1] = 1'b0;
   #100;
   
	end
endmodule
module TopLevel_sim();


reg clkin, btnU, btnD, btnL, btnR;
reg [15:0] sw;
wire Hsync, Vsync;
wire [3:0] vgaRed, vgaBlue, vgaGreen;

TopLevel UUT (.clkin(clkin), .btnU(btnU), .btnD(btnD), .btnL(btnL), .btnR(btnR), .sw(sw),
              .Hsync(Hsync), .Vsync(Vsync), .vgaRed(vgaRed), .vgaBlue(vgaBlue), .vgaGreen(vgaGreen));


parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clkin = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;
        end
	end
	
   initial
   begin
   btnU = 1'b0;
   btnD = 1'b0;
   btnR = 1'b0;
   btnL = 1'b0;
   sw[15:0] = 1'b0;
   #1000;
   sw[1] = 1'b1;
   #100;
   sw[1] = 1'b0;
   #100;
   
	end
endmodule