data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:38: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:49: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:51: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:63: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:63: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:95: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n `FLOW_CTRL_TYPE_CREDIT:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:95: syntax error, unexpected \':\', expecting endcase\n `FLOW_CTRL_TYPE_CREDIT:\n                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flow_ctrl_input.v:150: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n'
module rtr_flow_ctrl_input
  (clk, reset, active, flow_ctrl_in, fc_event_valid_out, 
   fc_event_sel_out_ovc);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   
   



   
   input clk;
   input reset;
   input active;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   output 		       fc_event_valid_out;
   wire 		       fc_event_valid_out;
   

   output [0:num_vcs-1] 	  fc_event_sel_out_ovc;
   wire [0:num_vcs-1] 		  fc_event_sel_out_ovc;
   
   



   
   generate
      
      case(flow_ctrl_type)
	
	`FLOW_CTRL_TYPE_CREDIT:
	  begin
	     
	     wire cred_valid_q;
	     







	     
	     wire cred_active;
	     assign cred_active = active | cred_valid_q;
	     
	     wire cred_valid_s;
	     assign cred_valid_s = flow_ctrl_in[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     cred_validq
	       (.clk(clk),
		.reset(reset),
		.active(cred_active),
		.d(cred_valid_s),
		.q(cred_valid_q));
	     
	     assign fc_event_valid_out = cred_valid_q;
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] cred_vc_s, cred_vc_q;
		  assign cred_vc_s = flow_ctrl_in[1:vc_idx_width];
		  c_dff
		    #(.width(vc_idx_width),
		      .reset_type(reset_type))
		  cred_vcq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(active),
		     .d(cred_vc_s),
		     .q(cred_vc_q));
		  
		  c_decode
		    #(.num_ports(num_vcs))
		  fc_event_sel_out_ovc_dec
		    (.data_in(cred_vc_q),
		     .data_out(fc_event_sel_out_ovc));
		  
	       end
	     else
	       assign fc_event_sel_out_ovc = 1'b1;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule
module rtr_flow_ctrl_input
  (clk, reset, active, flow_ctrl_in, fc_event_valid_out, 
   fc_event_sel_out_ovc);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   
   



   
   input clk;
   input reset;
   input active;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   output 		       fc_event_valid_out;
   wire 		       fc_event_valid_out;
   

   output [0:num_vcs-1] 	  fc_event_sel_out_ovc;
   wire [0:num_vcs-1] 		  fc_event_sel_out_ovc;
   
   



   
   generate
      
      case(flow_ctrl_type)
	
	`FLOW_CTRL_TYPE_CREDIT:
	  begin
	     
	     wire cred_valid_q;
	     







	     
	     wire cred_active;
	     assign cred_active = active | cred_valid_q;
	     
	     wire cred_valid_s;
	     assign cred_valid_s = flow_ctrl_in[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     cred_validq
	       (.clk(clk),
		.reset(reset),
		.active(cred_active),
		.d(cred_valid_s),
		.q(cred_valid_q));
	     
	     assign fc_event_valid_out = cred_valid_q;
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] cred_vc_s, cred_vc_q;
		  assign cred_vc_s = flow_ctrl_in[1:vc_idx_width];
		  c_dff
		    #(.width(vc_idx_width),
		      .reset_type(reset_type))
		  cred_vcq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(active),
		     .d(cred_vc_s),
		     .q(cred_vc_q));
		  
		  c_decode
		    #(.num_ports(num_vcs))
		  fc_event_sel_out_ovc_dec
		    (.data_in(cred_vc_q),
		     .data_out(fc_event_sel_out_ovc));
		  
	       end
	     else
	       assign fc_event_sel_out_ovc = 1'b1;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule