data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:3: Cannot find include file: tcu_parameter.vh\n    `include "tcu_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.sv\n             tcu_parameter.vh\n             tcu_parameter.vh.v\n             tcu_parameter.vh.sv\n             obj_dir/tcu_parameter.vh\n             obj_dir/tcu_parameter.vh.v\n             obj_dir/tcu_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter TCU_LOG_MEM_DATAWIDTH = 128,  \n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:5: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter TCU_LOG_MEM_ADDRWIDTH  = $clog2(TCU_LOG_REG_COUNT/2)\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:6: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                         reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                         tcu_log_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [TCU_LOG_DATA_SIZE-1:0] tcu_log_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                  [63:0] tcu_log_cur_time_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                         tcu_log_reg_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wben_i,  \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [TCU_REG_ADDR_SIZE-1:0] tcu_log_reg_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_rdata_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:20: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_log.v:45: syntax error, unexpected assign\n    assign tcu_log_reg_rdata_o = (r_log_reg_addr == TCU_REGADDR_TCU_LOG) ? r_log_mem_addr :\n    ^~~~~~\n%Error: Exiting due to 15 error(s)\n'
module tcu_log #(
    `include "tcu_parameter.vh"
    ,parameter TCU_LOG_MEM_DATAWIDTH = 128,
    parameter TCU_LOG_MEM_ADDRWIDTH  = $clog2(TCU_LOG_REG_COUNT/2)
)(
    input  wire                         clk_i,
    input  wire                         reset_n_i,

    input  wire                         tcu_log_en_i,
    input  wire [TCU_LOG_DATA_SIZE-1:0] tcu_log_data_i,

    input  wire                  [63:0] tcu_log_cur_time_i,

    input  wire                         tcu_log_reg_en_i,
    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wben_i,
    input  wire [TCU_REG_ADDR_SIZE-1:0] tcu_log_reg_addr_i,
    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wdata_i,
    output wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_rdata_o
);

    localparam TCU_REG_LOG2_DATA_SIZE = $clog2(TCU_REG_DATA_SIZE);

    integer i;

    reg                              r_log_mem_en;
    reg                       [31:0] r_log_mem_addr, rin_log_mem_addr;
    reg  [TCU_LOG_MEM_DATAWIDTH-1:0] r_log_mem_wdata;

    reg      [TCU_REG_ADDR_SIZE-1:0] r_log_reg_addr;

    reg      [TCU_REG_DATA_SIZE-1:0] r_log_select, rin_log_select;


    wire [TCU_LOG_MEM_ADDRWIDTH-1:0] log_mem_reg_addr = (tcu_log_reg_addr_i-TCU_REGADDR_TCU_LOG-16) >> 4;
    wire [TCU_LOG_MEM_DATAWIDTH-1:0] log_mem_reg_rdata;

    wire [TCU_REG_LOG2_DATA_SIZE-1:0] log_id_decr = tcu_log_data_i[TCU_LOG_ID_SIZE-1:0] - 1;
    wire                              log_valid = r_log_select[log_id_decr];





    assign tcu_log_reg_rdata_o = (r_log_reg_addr == TCU_REGADDR_TCU_LOG) ? r_log_mem_addr :
                                    (r_log_reg_addr == (TCU_REGADDR_TCU_LOG+8)) ? r_log_select :
                                    (r_log_reg_addr[3:0] == 4'h0) ? log_mem_reg_rdata[63:0] : log_mem_reg_rdata[127:64];



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            r_log_mem_en <= 1'b0;
            r_log_mem_addr <= 32'h0;
            r_log_mem_wdata <= {TCU_LOG_MEM_DATAWIDTH{1'b0}};

            r_log_reg_addr <= {TCU_REG_ADDR_SIZE{1'b0}};

            r_log_select <= {TCU_REG_DATA_SIZE{1'b1}};
        end
        else begin
            r_log_mem_en <= tcu_log_en_i && log_valid;
            r_log_mem_addr <= rin_log_mem_addr;
            r_log_mem_wdata <= {tcu_log_data_i, tcu_log_cur_time_i[35:4]};

            r_log_reg_addr <= tcu_log_reg_addr_i;

            r_log_select <= rin_log_select;
        end
    end

    always @* begin
        rin_log_mem_addr = r_log_mem_addr;



        if (r_log_mem_en) begin
            rin_log_mem_addr = r_log_mem_addr + 1;
        end
    end


    always @* begin
        rin_log_select = r_log_select;

        if (tcu_log_reg_en_i && (tcu_log_reg_addr_i == (TCU_REGADDR_TCU_LOG+8))) begin
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                if(tcu_log_reg_wben_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE]) begin
                    rin_log_select[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = tcu_log_reg_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                end
            end
        end
    end


    mem_tp_wrap #(
        .MEM_TYPE     ("ultra"),
        .MEM_DATAWIDTH(TCU_LOG_MEM_DATAWIDTH),
        .MEM_ADDRWIDTH(TCU_LOG_MEM_ADDRWIDTH)
    ) i_tcu_log_mem (
        .clk    (clk_i),
        .reset  (~reset_n_i),

        .ena    (r_log_mem_en),
        .wea    ({((TCU_LOG_MEM_DATAWIDTH+7)/8){1'b1}}),
        .addra  (r_log_mem_addr[TCU_LOG_MEM_ADDRWIDTH-1:0]),
        .dina   (r_log_mem_wdata),

        .enb    (tcu_log_reg_en_i),
        .addrb  (log_mem_reg_addr),
        .doutb  (log_mem_reg_rdata)
    );


endmodule
module tcu_log #(
    `include "tcu_parameter.vh"
    ,parameter TCU_LOG_MEM_DATAWIDTH = 128,
    parameter TCU_LOG_MEM_ADDRWIDTH  = $clog2(TCU_LOG_REG_COUNT/2)
)(
    input  wire                         clk_i,
    input  wire                         reset_n_i,

    input  wire                         tcu_log_en_i,
    input  wire [TCU_LOG_DATA_SIZE-1:0] tcu_log_data_i,

    input  wire                  [63:0] tcu_log_cur_time_i,

    input  wire                         tcu_log_reg_en_i,
    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wben_i,
    input  wire [TCU_REG_ADDR_SIZE-1:0] tcu_log_reg_addr_i,
    input  wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_wdata_i,
    output wire [TCU_REG_DATA_SIZE-1:0] tcu_log_reg_rdata_o
);


    localparam TCU_REG_LOG2_DATA_SIZE = $clog2(TCU_REG_DATA_SIZE);

    integer i;

    reg                              r_log_mem_en;
    reg                       [31:0] r_log_mem_addr, rin_log_mem_addr;
    reg  [TCU_LOG_MEM_DATAWIDTH-1:0] r_log_mem_wdata;

    reg      [TCU_REG_ADDR_SIZE-1:0] r_log_reg_addr;

    reg      [TCU_REG_DATA_SIZE-1:0] r_log_select, rin_log_select;


    wire [TCU_LOG_MEM_ADDRWIDTH-1:0] log_mem_reg_addr = (tcu_log_reg_addr_i-TCU_REGADDR_TCU_LOG-16) >> 4;
    wire [TCU_LOG_MEM_DATAWIDTH-1:0] log_mem_reg_rdata;

    wire [TCU_REG_LOG2_DATA_SIZE-1:0] log_id_decr = tcu_log_data_i[TCU_LOG_ID_SIZE-1:0] - 1;
    wire                              log_valid = r_log_select[log_id_decr];





    assign tcu_log_reg_rdata_o = (r_log_reg_addr == TCU_REGADDR_TCU_LOG) ? r_log_mem_addr :
                                    (r_log_reg_addr == (TCU_REGADDR_TCU_LOG+8)) ? r_log_select :
                                    (r_log_reg_addr[3:0] == 4'h0) ? log_mem_reg_rdata[63:0] : log_mem_reg_rdata[127:64];



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            r_log_mem_en <= 1'b0;
            r_log_mem_addr <= 32'h0;
            r_log_mem_wdata <= {TCU_LOG_MEM_DATAWIDTH{1'b0}};

            r_log_reg_addr <= {TCU_REG_ADDR_SIZE{1'b0}};

            r_log_select <= {TCU_REG_DATA_SIZE{1'b1}};
        end
        else begin
            r_log_mem_en <= tcu_log_en_i && log_valid;
            r_log_mem_addr <= rin_log_mem_addr;
            r_log_mem_wdata <= {tcu_log_data_i, tcu_log_cur_time_i[35:4]};

            r_log_reg_addr <= tcu_log_reg_addr_i;

            r_log_select <= rin_log_select;
        end
    end

    always @* begin
        rin_log_mem_addr = r_log_mem_addr;



        if (r_log_mem_en) begin
            rin_log_mem_addr = r_log_mem_addr + 1;
        end
    end


    always @* begin
        rin_log_select = r_log_select;

        if (tcu_log_reg_en_i && (tcu_log_reg_addr_i == (TCU_REGADDR_TCU_LOG+8))) begin
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                if(tcu_log_reg_wben_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE]) begin
                    rin_log_select[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = tcu_log_reg_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                end
            end
        end
    end


    mem_tp_wrap #(
        .MEM_TYPE     ("ultra"),
        .MEM_DATAWIDTH(TCU_LOG_MEM_DATAWIDTH),
        .MEM_ADDRWIDTH(TCU_LOG_MEM_ADDRWIDTH)
    ) i_tcu_log_mem (
        .clk    (clk_i),
        .reset  (~reset_n_i),

        .ena    (r_log_mem_en),
        .wea    ({((TCU_LOG_MEM_DATAWIDTH+7)/8){1'b1}}),
        .addra  (r_log_mem_addr[TCU_LOG_MEM_ADDRWIDTH-1:0]),
        .dina   (r_log_mem_wdata),

        .enb    (tcu_log_reg_en_i),
        .addrb  (log_mem_reg_addr),
        .doutb  (log_mem_reg_rdata)
    );


endmodule