data/full_repos/permissive/469509877/rtl/H3.v
data/verilator_xmls/7e9f7c5c-77d8-4820-bad3-174138ee5d77.xml
module H3(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );
    
    assign Red[3] = (Vcount >= 10'b0010110010) & (Vcount <= 10'b0010111001) & 
                    ((Hcount[9] | Hcount[8] | Hcount[7] | Hcount[6] | Hcount[5] | Hcount[4] | Hcount[3]) & 
                    (~(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];                          
endmodule
module H3(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );

    
    assign Red[3] = (Vcount >= 10'b0010110010) & (Vcount <= 10'b0010111001) & 
                    ((Hcount[9] | Hcount[8] | Hcount[7] | Hcount[6] | Hcount[5] | Hcount[4] | Hcount[3]) & 
                    (~(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];                          
endmodule