data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ONEDCONV_SET_EN.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ONEDCONV_SET_EN.v:71: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                            : ... In instance ONEDCONV_SET_EN\n  Set_counter<=1\'b0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ONEDCONV_SET_EN #(parameter BITWIDTH_OF_COLUMS=11)(


ONEDCONV_SET_EN_clk,
ONEDCONV_SET_EN_Eqcw,
ONEDCONV_SET_EN_Eqst,
ONEDCONV_SET_EN_En,
ONEDCONV_SET_EN_Clr, 
ONEDCONV_SET_Flag_Out_Full, 
ONEDCONV_SET_EN_Of_Colums,


ONEDCONV_SET_EN_Rptclr,
ONEDCONV_SET_EN_Oen_clr,
ONEDCONV_SET_EN_set_en,
ONEDCONV_SET_EN_Flag_Om_Full

);




input ONEDCONV_SET_EN_clk;
input ONEDCONV_SET_EN_Eqcw;
input ONEDCONV_SET_EN_Eqst;
input ONEDCONV_SET_EN_En;
input ONEDCONV_SET_EN_Clr;
input ONEDCONV_SET_Flag_Out_Full;
input [BITWIDTH_OF_COLUMS-1:0] ONEDCONV_SET_EN_Of_Colums;

output ONEDCONV_SET_EN_Rptclr;
output ONEDCONV_SET_EN_Oen_clr;
output ONEDCONV_SET_EN_set_en;
output ONEDCONV_SET_EN_Flag_Om_Full;





reg [BITWIDTH_OF_COLUMS-1:0] Set_counter;

reg Set_en;
reg Oe_Clr;
reg Rptclr;

always@(posedge ONEDCONV_SET_EN_clk)
begin

	if(!ONEDCONV_SET_EN_Clr)begin	
		Set_counter<=1'b0;
		Set_en<=1'b0;
		Rptclr<=1'b1;
		Oe_Clr<=1'b1;
	end
	
	else 
		begin
			
			if(ONEDCONV_SET_EN_En)begin
				
				if(ONEDCONV_SET_EN_Eqcw || ONEDCONV_SET_EN_Eqst)begin
					Set_en<=1'b1;
					Set_counter<=Set_counter+1'b1;
				end
				
				else 
					Set_en<=1'b0;
			end

			else
				Set_en<=1'b0;
			
			
			if(ONEDCONV_SET_Flag_Out_Full)begin
				Rptclr<=1'b0;
				Oe_Clr<=1'b0;
			end
			
			else
				begin
					Oe_Clr<=1'b1;
					Rptclr<=1'b1;
				end
				
		end
end







assign ONEDCONV_SET_EN_Rptclr=Rptclr;
assign ONEDCONV_SET_EN_Oen_clr=Oe_Clr; 
assign ONEDCONV_SET_EN_set_en=Set_en;
assign ONEDCONV_SET_EN_Flag_Om_Full = (Set_counter== ONEDCONV_SET_EN_Of_Colums) ? 1'b1 : 1'b0;



endmodule
module ONEDCONV_SET_EN #(parameter BITWIDTH_OF_COLUMS=11)(


ONEDCONV_SET_EN_clk,
ONEDCONV_SET_EN_Eqcw,
ONEDCONV_SET_EN_Eqst,
ONEDCONV_SET_EN_En,
ONEDCONV_SET_EN_Clr, 
ONEDCONV_SET_Flag_Out_Full, 
ONEDCONV_SET_EN_Of_Colums,


ONEDCONV_SET_EN_Rptclr,
ONEDCONV_SET_EN_Oen_clr,
ONEDCONV_SET_EN_set_en,
ONEDCONV_SET_EN_Flag_Om_Full

);





input ONEDCONV_SET_EN_clk;
input ONEDCONV_SET_EN_Eqcw;
input ONEDCONV_SET_EN_Eqst;
input ONEDCONV_SET_EN_En;
input ONEDCONV_SET_EN_Clr;
input ONEDCONV_SET_Flag_Out_Full;
input [BITWIDTH_OF_COLUMS-1:0] ONEDCONV_SET_EN_Of_Colums;

output ONEDCONV_SET_EN_Rptclr;
output ONEDCONV_SET_EN_Oen_clr;
output ONEDCONV_SET_EN_set_en;
output ONEDCONV_SET_EN_Flag_Om_Full;





reg [BITWIDTH_OF_COLUMS-1:0] Set_counter;

reg Set_en;
reg Oe_Clr;
reg Rptclr;

always@(posedge ONEDCONV_SET_EN_clk)
begin

	if(!ONEDCONV_SET_EN_Clr)begin	
		Set_counter<=1'b0;
		Set_en<=1'b0;
		Rptclr<=1'b1;
		Oe_Clr<=1'b1;
	end
	
	else 
		begin
			
			if(ONEDCONV_SET_EN_En)begin
				
				if(ONEDCONV_SET_EN_Eqcw || ONEDCONV_SET_EN_Eqst)begin
					Set_en<=1'b1;
					Set_counter<=Set_counter+1'b1;
				end
				
				else 
					Set_en<=1'b0;
			end

			else
				Set_en<=1'b0;
			
			
			if(ONEDCONV_SET_Flag_Out_Full)begin
				Rptclr<=1'b0;
				Oe_Clr<=1'b0;
			end
			
			else
				begin
					Oe_Clr<=1'b1;
					Rptclr<=1'b1;
				end
				
		end
end







assign ONEDCONV_SET_EN_Rptclr=Rptclr;
assign ONEDCONV_SET_EN_Oen_clr=Oe_Clr; 
assign ONEDCONV_SET_EN_set_en=Set_en;
assign ONEDCONV_SET_EN_Flag_Om_Full = (Set_counter== ONEDCONV_SET_EN_Of_Colums) ? 1'b1 : 1'b0;



endmodule