data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:34: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ALU\'\nmodule ALU(a, b, s, r, zero, overflow, negative);\n       ^~~\n                                                                           : ... Top module \'MUL\'\nmodule MUL(a, b, r, sign);\n       ^~~\n                                                                           : ... Top module \'DIV\'\nmodule DIV(a, b, q, r, sign, dbz);\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:113: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n    assign q_abs = ((!(d00 < b_abs)) << 5\'d00) + ((!(d01 < b_abs)) << 5\'d01) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:113: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n    assign q_abs = ((!(d00 < b_abs)) << 5\'d00) + ((!(d01 < b_abs)) << 5\'d01) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:114: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d02 < b_abs)) << 5\'d02) + ((!(d03 < b_abs)) << 5\'d03) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:114: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d02 < b_abs)) << 5\'d02) + ((!(d03 < b_abs)) << 5\'d03) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:115: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d04 < b_abs)) << 5\'d04) + ((!(d05 < b_abs)) << 5\'d05) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:115: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d04 < b_abs)) << 5\'d04) + ((!(d05 < b_abs)) << 5\'d05) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:116: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d06 < b_abs)) << 5\'d06) + ((!(d07 < b_abs)) << 5\'d07) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:116: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d06 < b_abs)) << 5\'d06) + ((!(d07 < b_abs)) << 5\'d07) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:117: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d08 < b_abs)) << 5\'d08) + ((!(d09 < b_abs)) << 5\'d09) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:117: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d08 < b_abs)) << 5\'d08) + ((!(d09 < b_abs)) << 5\'d09) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:118: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d10 < b_abs)) << 5\'d10) + ((!(d11 < b_abs)) << 5\'d11) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:118: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d10 < b_abs)) << 5\'d10) + ((!(d11 < b_abs)) << 5\'d11) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:119: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d12 < b_abs)) << 5\'d12) + ((!(d13 < b_abs)) << 5\'d13) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:119: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d12 < b_abs)) << 5\'d12) + ((!(d13 < b_abs)) << 5\'d13) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:120: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d14 < b_abs)) << 5\'d14) + ((!(d15 < b_abs)) << 5\'d15) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:120: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d14 < b_abs)) << 5\'d14) + ((!(d15 < b_abs)) << 5\'d15) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:121: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d16 < b_abs)) << 5\'d16) + ((!(d17 < b_abs)) << 5\'d17) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:121: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d16 < b_abs)) << 5\'d16) + ((!(d17 < b_abs)) << 5\'d17) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:122: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d18 < b_abs)) << 5\'d18) + ((!(d19 < b_abs)) << 5\'d19) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:122: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d18 < b_abs)) << 5\'d18) + ((!(d19 < b_abs)) << 5\'d19) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:123: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d20 < b_abs)) << 5\'d20) + ((!(d21 < b_abs)) << 5\'d21) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:123: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d20 < b_abs)) << 5\'d20) + ((!(d21 < b_abs)) << 5\'d21) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:124: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d22 < b_abs)) << 5\'d22) + ((!(d23 < b_abs)) << 5\'d23) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:124: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d22 < b_abs)) << 5\'d22) + ((!(d23 < b_abs)) << 5\'d23) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:125: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d24 < b_abs)) << 5\'d24) + ((!(d25 < b_abs)) << 5\'d25) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:125: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d24 < b_abs)) << 5\'d24) + ((!(d25 < b_abs)) << 5\'d25) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:126: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d26 < b_abs)) << 5\'d26) + ((!(d27 < b_abs)) << 5\'d27) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:126: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d26 < b_abs)) << 5\'d26) + ((!(d27 < b_abs)) << 5\'d27) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:127: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d28 < b_abs)) << 5\'d28) + ((!(d29 < b_abs)) << 5\'d29) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:127: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d28 < b_abs)) << 5\'d28) + ((!(d29 < b_abs)) << 5\'d29) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:128: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d30 < b_abs)) << 5\'d30) + ((!(d31 < b_abs)) << 5\'d31);\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:128: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d30 < b_abs)) << 5\'d30) + ((!(d31 < b_abs)) << 5\'d31);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:25: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LTS generates 1 bits.\n                                                                        : ... In instance ALU\n              (s == 4\'b1011 ? $signed(a) < $signed(b) :\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:26: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LT generates 1 bits.\n                                                                        : ... In instance ALU\n              (s == 4\'b1010 ? a < b :\n                            ^\n%Error: Exiting due to 35 warning(s)\n'
module ALU(a, b, s, r, zero, overflow, negative);
    input [31:0] a;
    input [31:0] b;
    input [3:0] s;
    output [31:0] r;
    output zero;
    output overflow;
    output negative;

    wire [32:0] r_ext;
    assign r_ext = s == 4'b0010 ? {a[31], a} + {b[31], b} : {a[31], a} - {b[31], b};
    assign zero = r == 0;
    assign overflow = (r_ext[32] ^ r_ext[31]) & (s == 4'b0010 | s == 4'b0011);
    assign negative = r[31];
    assign r = s == 4'b0000 ? a + b :
              (s == 4'b0010 ? a + b :
              (s == 4'b0001 ? a - b :
              (s == 4'b0011 ? a - b :
              (s == 4'b0100 ? a & b :
              (s == 4'b0101 ? a | b :
              (s == 4'b0110 ? a ^ b :
              (s == 4'b0111 ? ~(a | b) :
              (s == 4'b1000 ? {b[15:0], 16'b0} :
              (s == 4'b1001 ? {b[15:0], 16'b0} :
              (s == 4'b1011 ? $signed(a) < $signed(b) :
              (s == 4'b1010 ? a < b :
              (s == 4'b1100 ? $signed($signed(b) >>> a[4:0]):
              (s == 4'b1110 ? b << a[4:0] :
              (s == 4'b1111 ? b << a[4:0] :
              (s == 4'b1101 ? b >> a[4:0] :
               32'b0)))))))))))))));
endmodule
module ALU(a, b, s, r, zero, overflow, negative);

    input [31:0] a;
    input [31:0] b;
    input [3:0] s;
    output [31:0] r;
    output zero;
    output overflow;
    output negative;

    wire [32:0] r_ext;
    assign r_ext = s == 4'b0010 ? {a[31], a} + {b[31], b} : {a[31], a} - {b[31], b};
    assign zero = r == 0;
    assign overflow = (r_ext[32] ^ r_ext[31]) & (s == 4'b0010 | s == 4'b0011);
    assign negative = r[31];
    assign r = s == 4'b0000 ? a + b :
              (s == 4'b0010 ? a + b :
              (s == 4'b0001 ? a - b :
              (s == 4'b0011 ? a - b :
              (s == 4'b0100 ? a & b :
              (s == 4'b0101 ? a | b :
              (s == 4'b0110 ? a ^ b :
              (s == 4'b0111 ? ~(a | b) :
              (s == 4'b1000 ? {b[15:0], 16'b0} :
              (s == 4'b1001 ? {b[15:0], 16'b0} :
              (s == 4'b1011 ? $signed(a) < $signed(b) :
              (s == 4'b1010 ? a < b :
              (s == 4'b1100 ? $signed($signed(b) >>> a[4:0]):
              (s == 4'b1110 ? b << a[4:0] :
              (s == 4'b1111 ? b << a[4:0] :
              (s == 4'b1101 ? b >> a[4:0] :
               32'b0)))))))))))))));
endmodule