data/full_repos/permissive/480154458/Gateware/riscv/src/mailbox.v
1: b"%Error: data/full_repos/permissive/480154458/Gateware/riscv/src/mailbox.v:47: Cannot find file containing module: 'fifo1'\n fifo1 #(.DSIZE(8), .ASIZE(4)) uofifo(\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/480154458/Gateware/riscv/src,data/full_repos/permissive/480154458/fifo1\n             data/full_repos/permissive/480154458/Gateware/riscv/src,data/full_repos/permissive/480154458/fifo1.v\n             data/full_repos/permissive/480154458/Gateware/riscv/src,data/full_repos/permissive/480154458/fifo1.sv\n             fifo1\n             fifo1.v\n             fifo1.sv\n             obj_dir/fifo1\n             obj_dir/fifo1.v\n             obj_dir/fifo1.sv\n%Error: Exiting due to 1 error(s)\n"
module mailbox(

	input	clk,
			reset,
			

	input 	cs,
			we,
			addr,
	input [7:0]	din,
	output reg [7:0] dout,
	

	input	mbx_oclk,
			mbx_orst,
	output [7:0] mbx_odat,
	output	mbx_ompt,
	input	mbx_ord,
	

	output [11:0] mbx_diag
);

	wire write = cs&we&(addr==1'b1);
	reg dwrite;
	always @(posedge clk)
		dwrite <= write;
	wire winc = write & !dwrite;
	

	wire read = mbx_ord;
	reg dread;
	always @(posedge mbx_oclk)
		dread <= read;
	wire rinc = read & !dread;
	

	wire wfull;
	wire [4:0] waddr, raddr;
	fifo1 #(.DSIZE(8), .ASIZE(4)) uofifo(
		.rdata(mbx_odat),
		.wfull(wfull),
		.rempty(mbx_ompt),
		.wdata(din),
		.winc(winc),
		.wclk(clk),
		.wrst_n(!reset),
		.rinc(rinc),
		.rclk(mbx_oclk),
		.rrst_n(!mbx_orst),
		.waddr(waddr),
		.raddr(raddr)
	);
	

	wire rempty = 1'b1;
	wire [7:0] rx_dat = 8'h00;


	wire [7:0] status = 
	{
		6'b000000,
		wfull,
		rempty
	};


	always @(posedge clk)
	begin
		if(reset)
		begin
			dout <= 8'h00;
		end
		else
		begin
			if(cs & ~we)
			begin
				if(addr)
					dout <= rx_dat;
				else
					dout <= status;
			end
		end
	end
	

	assign mbx_diag = {waddr,winc,raddr,rinc};

endmodule
module mailbox(

	input	clk,
			reset,
			

	input 	cs,
			we,
			addr,
	input [7:0]	din,
	output reg [7:0] dout,
	

	input	mbx_oclk,
			mbx_orst,
	output [7:0] mbx_odat,
	output	mbx_ompt,
	input	mbx_ord,
	

	output [11:0] mbx_diag
);


	wire write = cs&we&(addr==1'b1);
	reg dwrite;
	always @(posedge clk)
		dwrite <= write;
	wire winc = write & !dwrite;
	

	wire read = mbx_ord;
	reg dread;
	always @(posedge mbx_oclk)
		dread <= read;
	wire rinc = read & !dread;
	

	wire wfull;
	wire [4:0] waddr, raddr;
	fifo1 #(.DSIZE(8), .ASIZE(4)) uofifo(
		.rdata(mbx_odat),
		.wfull(wfull),
		.rempty(mbx_ompt),
		.wdata(din),
		.winc(winc),
		.wclk(clk),
		.wrst_n(!reset),
		.rinc(rinc),
		.rclk(mbx_oclk),
		.rrst_n(!mbx_orst),
		.waddr(waddr),
		.raddr(raddr)
	);
	

	wire rempty = 1'b1;
	wire [7:0] rx_dat = 8'h00;


	wire [7:0] status = 
	{
		6'b000000,
		wfull,
		rempty
	};


	always @(posedge clk)
	begin
		if(reset)
		begin
			dout <= 8'h00;
		end
		else
		begin
			if(cs & ~we)
			begin
				if(addr)
					dout <= rx_dat;
				else
					dout <= status;
			end
		end
	end
	

	assign mbx_diag = {waddr,winc,raddr,rinc};

endmodule