data/full_repos/permissive/497870922/rtl/spi module/spi_master_registers.v
1: b'%Error: Cannot find file containing module: module,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.sv\n             module,data/full_repos/permissive/497870922\n             module,data/full_repos/permissive/497870922.v\n             module,data/full_repos/permissive/497870922.sv\n             obj_dir/module,data/full_repos/permissive/497870922\n             obj_dir/module,data/full_repos/permissive/497870922.v\n             obj_dir/module,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/rtl/spi\n%Error: Cannot find file containing module: module/spi_master_registers.v\n%Error: Exiting due to 3 error(s)\n'
module spi_master_registers(
   Clk
  ,Rst_n
  ,Wr
  ,Rd
  ,Addr
  ,DataIn
  ,DataOut
  ,CPol
  ,CPha
  ,Spr1
  ,Spr0
  ,CPre
  ,SS
  ,Busy
  ,SpiSRRx
  ,SpiBuf
  ,WrBuf
  ,Spie
  ,Spse
  ,LoadMaster
);
parameter SIZE = 8;


input             Clk;
input             Rst_n;


input             Wr;
input             Rd;
input  [SIZE-1:0] Addr;
input  [SIZE-1:0] DataIn;
output [SIZE-1:0] DataOut;


output            CPol;
output            CPha;
output            Spr1,Spr0;
output [SIZE-1:0] CPre;


output [SIZE-1:0] SS;


input             Busy;
input  [SIZE-1:0] SpiSRRx;
output [SIZE-1:0] SpiBuf;
input             WrBuf;
output            Spie;
output            Spse;
output            LoadMaster;



reg [SIZE-1:0] spiCtrl;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    spiCtrl <= 8'h10;
  else if(Wr & (Addr == `SPICTRL))
    spiCtrl <= DataIn;


assign Spie = spiCtrl[7];
assign Spse = spiCtrl[6];
assign CPol = spiCtrl[3];
assign CPha = spiCtrl[2];
assign Spr1 = spiCtrl[1];
assign Spr0 = spiCtrl[0];


reg [1:0] loadMaster_aux;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    loadMaster_aux <= 2'b00;
  else
    loadMaster_aux <= {loadMaster_aux[0],(Wr & (Addr == `SPIBUFF))};

assign LoadMaster = loadMaster_aux[1];



reg wcol;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    wcol <= 1'b0;
  else if(Wr & (Addr == `SPIBUFF) & Busy)
    wcol <= 1'b1;
  else if(!Busy)
    wcol <= 1'b0;


reg bf;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    bf <= 1'b0;
  else if(WrBuf)
    bf <= 1'b1;
  else if((Rd | Wr) & (Addr == `SPIBUFF))
    bf <= 1'b0;



reg [SIZE-1:0] SpiBuf;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                       SpiBuf <= 8'h00;
  else if(Wr & (Addr == `SPIBUFF)) SpiBuf <= DataIn;
  else if(WrBuf)                   SpiBuf <= SpiSRRx;



reg [SIZE-1:0] SS;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                     SS <= 8'hFF;
  else if(Wr & (Addr == `SPISS)) SS <= DataIn;



reg [SIZE-1:0] CPre;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                      CPre <= 8'h07;
  else if(Wr & (Addr == `SPIPRE)) CPre <= DataIn;



reg [SIZE-1:0] DataOut;

always @(Addr or Spie or Spse or CPol or CPha or Spr1 or
         Spr0 or SpiBuf or SS or CPre or wcol or Busy or bf)
  case(Addr)
    `SPICTRL  : DataOut = {Spie,Spse,1'b1,1'b1,CPol,CPha,Spr1,Spr0};
    `SPISTAT  : DataOut = {wcol,5'b0_0000,Busy,bf};
    `SPIBUFF  : DataOut = SpiBuf;
    `SPISS    : DataOut = SS;
    `SPIPRE   : DataOut = CPre;
    default   : DataOut = 8'h00;
  endcase

endmodule
module spi_master_registers(
   Clk
  ,Rst_n
  ,Wr
  ,Rd
  ,Addr
  ,DataIn
  ,DataOut
  ,CPol
  ,CPha
  ,Spr1
  ,Spr0
  ,CPre
  ,SS
  ,Busy
  ,SpiSRRx
  ,SpiBuf
  ,WrBuf
  ,Spie
  ,Spse
  ,LoadMaster
);

parameter SIZE = 8;


input             Clk;
input             Rst_n;


input             Wr;
input             Rd;
input  [SIZE-1:0] Addr;
input  [SIZE-1:0] DataIn;
output [SIZE-1:0] DataOut;


output            CPol;
output            CPha;
output            Spr1,Spr0;
output [SIZE-1:0] CPre;


output [SIZE-1:0] SS;


input             Busy;
input  [SIZE-1:0] SpiSRRx;
output [SIZE-1:0] SpiBuf;
input             WrBuf;
output            Spie;
output            Spse;
output            LoadMaster;



reg [SIZE-1:0] spiCtrl;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    spiCtrl <= 8'h10;
  else if(Wr & (Addr == `SPICTRL))
    spiCtrl <= DataIn;


assign Spie = spiCtrl[7];
assign Spse = spiCtrl[6];
assign CPol = spiCtrl[3];
assign CPha = spiCtrl[2];
assign Spr1 = spiCtrl[1];
assign Spr0 = spiCtrl[0];


reg [1:0] loadMaster_aux;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    loadMaster_aux <= 2'b00;
  else
    loadMaster_aux <= {loadMaster_aux[0],(Wr & (Addr == `SPIBUFF))};

assign LoadMaster = loadMaster_aux[1];



reg wcol;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    wcol <= 1'b0;
  else if(Wr & (Addr == `SPIBUFF) & Busy)
    wcol <= 1'b1;
  else if(!Busy)
    wcol <= 1'b0;


reg bf;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)
    bf <= 1'b0;
  else if(WrBuf)
    bf <= 1'b1;
  else if((Rd | Wr) & (Addr == `SPIBUFF))
    bf <= 1'b0;



reg [SIZE-1:0] SpiBuf;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                       SpiBuf <= 8'h00;
  else if(Wr & (Addr == `SPIBUFF)) SpiBuf <= DataIn;
  else if(WrBuf)                   SpiBuf <= SpiSRRx;



reg [SIZE-1:0] SS;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                     SS <= 8'hFF;
  else if(Wr & (Addr == `SPISS)) SS <= DataIn;



reg [SIZE-1:0] CPre;

always @(negedge Clk or negedge Rst_n)
  if(!Rst_n)                      CPre <= 8'h07;
  else if(Wr & (Addr == `SPIPRE)) CPre <= DataIn;



reg [SIZE-1:0] DataOut;

always @(Addr or Spie or Spse or CPol or CPha or Spr1 or
         Spr0 or SpiBuf or SS or CPre or wcol or Busy or bf)
  case(Addr)
    `SPICTRL  : DataOut = {Spie,Spse,1'b1,1'b1,CPol,CPha,Spr1,Spr0};
    `SPISTAT  : DataOut = {wcol,5'b0_0000,Busy,bf};
    `SPIBUFF  : DataOut = SpiBuf;
    `SPISS    : DataOut = SS;
    `SPIPRE   : DataOut = CPre;
    default   : DataOut = 8'h00;
  endcase

endmodule