data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo.v
1: b"%Error: data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo.v:30: Cannot find file containing module: 'async_fifo_in'\n    async_fifo_in #(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/async_fifo_in\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/async_fifo_in.v\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/async_fifo_in.sv\n             async_fifo_in\n             async_fifo_in.v\n             async_fifo_in.sv\n             obj_dir/async_fifo_in\n             obj_dir/async_fifo_in.v\n             obj_dir/async_fifo_in.sv\n%Error: data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo.v:49: Cannot find file containing module: 'async_fifo_out'\n    async_fifo_out #(\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module async_fifo #(
    parameter DATA_WIDTH          = 16,
    parameter ADDR_WIDTH          = 2,
    parameter ALMOST_FULL_BUFFER  = 2,
    parameter ALMOST_EMPTY_BUFFER = 2
)(
    input  wire                   aresetn_i,
    input  wire                   scan_mode_i,

    input  wire                   rclk_i,
    input  wire                   rd_en_i,
    output wire  [DATA_WIDTH-1:0] rdata_o,
    output wire                   ralmost_empty_o,
    output wire                   rempty_o,

    input  wire                   wclk_i,
    input  wire                   wr_en_i,
    input  wire  [DATA_WIDTH-1:0] wdata_i,
    output wire                   walmost_full_o,
    output wire                   wfull_o
);


    wire   [ADDR_WIDTH:0] wr_ptr;
    wire   [ADDR_WIDTH:0] rd_ptr;
    wire [DATA_WIDTH-1:0] rdata;


    async_fifo_in #(
        .DATA_WIDTH         (DATA_WIDTH),
        .ADDR_WIDTH         (ADDR_WIDTH),
        .ALMOST_FULL_BUFFER (ALMOST_FULL_BUFFER)
    ) i_async_fifo_in (
        .aresetn_i          (aresetn_i),
        .scan_mode_i        (scan_mode_i),

        .wr_ptr_o           (wr_ptr),
        .rdata_o            (rdata),

        .wclk_i             (wclk_i),
        .wr_en_i            (wr_en_i),
        .wdata_i            (wdata_i),
        .rd_ptr_i           (rd_ptr),
        .walmost_full_o     (walmost_full_o),
        .wfull_o            (wfull_o)
    );

    async_fifo_out #(
        .DATA_WIDTH          (DATA_WIDTH),
        .ADDR_WIDTH          (ADDR_WIDTH),
        .ALMOST_EMPTY_BUFFER (ALMOST_EMPTY_BUFFER)
    ) i_async_fifo_out (
        .aresetn_i           (aresetn_i),
        .scan_mode_i         (scan_mode_i),

        .rclk_i              (rclk_i),
        .rd_en_i             (rd_en_i),
        .rdata_o             (rdata_o),
        .rd_ptr_o            (rd_ptr),
        .ralmost_empty_o     (ralmost_empty_o),
        .rempty_o            (rempty_o),

        .wr_ptr_i            (wr_ptr),
        .rdata_i             (rdata)
    );


endmodule
module async_fifo #(
    parameter DATA_WIDTH          = 16,
    parameter ADDR_WIDTH          = 2,
    parameter ALMOST_FULL_BUFFER  = 2,
    parameter ALMOST_EMPTY_BUFFER = 2
)(
    input  wire                   aresetn_i,
    input  wire                   scan_mode_i,

    input  wire                   rclk_i,
    input  wire                   rd_en_i,
    output wire  [DATA_WIDTH-1:0] rdata_o,
    output wire                   ralmost_empty_o,
    output wire                   rempty_o,

    input  wire                   wclk_i,
    input  wire                   wr_en_i,
    input  wire  [DATA_WIDTH-1:0] wdata_i,
    output wire                   walmost_full_o,
    output wire                   wfull_o
);



    wire   [ADDR_WIDTH:0] wr_ptr;
    wire   [ADDR_WIDTH:0] rd_ptr;
    wire [DATA_WIDTH-1:0] rdata;


    async_fifo_in #(
        .DATA_WIDTH         (DATA_WIDTH),
        .ADDR_WIDTH         (ADDR_WIDTH),
        .ALMOST_FULL_BUFFER (ALMOST_FULL_BUFFER)
    ) i_async_fifo_in (
        .aresetn_i          (aresetn_i),
        .scan_mode_i        (scan_mode_i),

        .wr_ptr_o           (wr_ptr),
        .rdata_o            (rdata),

        .wclk_i             (wclk_i),
        .wr_en_i            (wr_en_i),
        .wdata_i            (wdata_i),
        .rd_ptr_i           (rd_ptr),
        .walmost_full_o     (walmost_full_o),
        .wfull_o            (wfull_o)
    );

    async_fifo_out #(
        .DATA_WIDTH          (DATA_WIDTH),
        .ADDR_WIDTH          (ADDR_WIDTH),
        .ALMOST_EMPTY_BUFFER (ALMOST_EMPTY_BUFFER)
    ) i_async_fifo_out (
        .aresetn_i           (aresetn_i),
        .scan_mode_i         (scan_mode_i),

        .rclk_i              (rclk_i),
        .rd_en_i             (rd_en_i),
        .rdata_o             (rdata_o),
        .rd_ptr_o            (rd_ptr),
        .ralmost_empty_o     (ralmost_empty_o),
        .rempty_o            (rempty_o),

        .wr_ptr_i            (wr_ptr),
        .rdata_i             (rdata)
    );


endmodule