data/full_repos/permissive/42434302/ivltests/drive_strength2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/drive_strength2.v:31: Unsupported: Ignoring delay on this delayed statement.\n    initial begin clk = 0 ; forever #5 clk = ~clk ; end\n                                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/drive_strength2.v:32: Unsupported: Ignoring delay on this delayed statement.\n    initial begin c = 0 ; #40 $finish ; end\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/drive_strength2.v:24: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'iA\' generates 1 bits.\n                                                                                 : ... In instance main.N\n    assign  ioS = (iC) ? iA : \'bz ;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/drive_strength2.v:24: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                 : ... In instance main.N\n    assign  ioS = (iC) ? iA : \'bz ;\n                ^\n%Warning-INFINITELOOP: data/full_repos/permissive/42434302/ivltests/drive_strength2.v:31: Infinite loop (condition always true)\n                                                                                        : ... In instance main\n    initial begin clk = 0 ; forever #5 clk = ~clk ; end\n                            ^~~~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  main;

    reg     clk, c ;
    initial begin clk = 0 ; forever #5 clk = ~clk ; end
    initial begin c = 0 ; #40 $finish ; end

    wire    a, b, s ;

    assign  a = 'b0 ;
    assign  b = 'b1 ;

    always @(posedge clk) c <= ~c ;

    drvz M ( clk, a, c,  s ) ;
    drvz N ( clk, b, ~c, s ) ;

    always @(posedge clk)
        $display("%b %b %b", s, a, b );

endmodule
module  main;


    reg     clk, c ;
    initial begin clk = 0 ; forever #5 clk = ~clk ; end
    initial begin c = 0 ; #40 $finish ; end

    wire    a, b, s ;

    assign  a = 'b0 ;
    assign  b = 'b1 ;

    always @(posedge clk) c <= ~c ;

    drvz M ( clk, a, c,  s ) ;
    drvz N ( clk, b, ~c, s ) ;

    always @(posedge clk)
        $display("%b %b %b", s, a, b );

endmodule