data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_if_else.v
data/verilator_xmls/b106f90e-cdb2-4e6a-8384-b2846b1ec9ba.xml
module if_else();

reg dff;
wire clk,din,reset;

always @ (posedge clk)
if (reset) begin
  dff <= 0;
end else  begin
  dff <= din;
end

endmodule
module if_else();


reg dff;
wire clk,din,reset;

always @ (posedge clk)
if (reset) begin
  dff <= 0;
end else  begin
  dff <= din;
end

endmodule