data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_ddr.v
1: b'%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_ddr.v:37: Cannot find include file: toysram.vh\n`include "toysram.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.sv\n             toysram.vh\n             toysram.vh.v\n             toysram.vh.sv\n             obj_dir/toysram.vh\n             obj_dir/toysram.vh.v\n             obj_dir/toysram.vh.sv\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_ddr.v:80: Define or directive not defined: \'`GENMODE\'\n parameter GENMODE = `GENMODE;          \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_ddr.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter GENMODE = `GENMODE;          \n                             ^\n%Error: Exiting due to 3 error(s)\n'
module ra_bist_ddr (

    clk,
    reset,
    ctl,
    status,
    rd0_enb_in,
    rd0_adr_in,
    rd1_enb_in,
    rd1_adr_in,
    rd2_enb_in,
    rd2_adr_in,
    rd3_enb_in,
    rd3_adr_in,
    wr0_enb_in,
    wr0_adr_in,
    wr0_dat_in,
    wr1_enb_in,
    wr1_adr_in,
    wr1_dat_in,
    rd0_enb_out,
    rd0_adr_out,
    rd0_dat,
    rd1_enb_out,
    rd1_adr_out,
    rd1_dat,
    rd2_enb_out,
    rd2_adr_out,
    rd2_dat,
    rd3_enb_out,
    rd3_adr_out,
    rd3_dat,
    wr0_enb_out,
    wr0_adr_out,
    wr0_dat_out,
    wr1_enb_out,
    wr1_adr_out,
    wr1_dat_out

);

 parameter GENMODE = `GENMODE;

   input          clk;
   input          reset;
   input  [0:31]  ctl;

   input          rd0_enb_in;
   input  [0:5]   rd0_adr_in;
   input          rd1_enb_in;
   input  [0:5]   rd1_adr_in;
   input          rd2_enb_in;
   input  [0:5]   rd2_adr_in;
   input          rd3_enb_in;
   input  [0:5]   rd3_adr_in;
   input          wr0_enb_in;
   input  [0:5]   wr0_adr_in;
   input  [0:71]  wr0_dat_in;
   input          wr1_enb_in;
   input  [0:5]   wr1_adr_in;
   input  [0:71]  wr1_dat_in;

   output [0:31]  status;
   output         rd0_enb_out;
   output [0:5]   rd0_adr_out;
   input  [0:71]  rd0_dat;
   output         rd1_enb_out;
   output [0:5]   rd1_adr_out;
   input  [0:71]  rd1_dat;
   output         rd2_enb_out;
   output [0:5]   rd2_adr_out;
   input  [0:71]  rd2_dat;
   output         rd3_enb_out;
   output [0:5]   rd3_adr_out;
   input  [0:71]  rd3_dat;
   output         wr0_enb_out;
   output [0:5]   wr0_adr_out;
   output [0:71]  wr0_dat_out;
   output         wr1_enb_out;
   output [0:5]   wr1_adr_out;
   output [0:71]  wr1_dat_out;

   reg    [0:5]   seq_q;
   wire   [0:5]   seq_d;
   wire           active;
   wire           bist_rd0_enb;
   wire   [0:5]   bist_rd0_adr;
   wire           bist_rd1_enb;
   wire   [0:5]   bist_rd1_adr;
   wire           bist_rd2_enb;
   wire   [0:5]   bist_rd2_adr;
   wire           bist_rd3_enb;
   wire   [0:5]   bist_rd3_adr;
   wire           bist_wr0_enb;
   wire   [0:5]   bist_wr0_adr;
   wire   [0:71]  bist_wr0_dat;
   wire           bist_wr1_enb;
   wire   [0:5]   bist_wr1_adr;
   wire   [0:71]  bist_wr1_dat;


   always @ (posedge clk) begin
      if (reset)
         seq_q <= 6'h3F;
      else
         seq_q <= seq_d;
   end


   assign seq_d = seq_q;
   assign active = seq_q != 6'h3F;
   assign status = 0;


   assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
   assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
   assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
   assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
   assign rd2_enb_out = (active) ? bist_rd2_enb : rd2_enb_in;
   assign rd2_adr_out = (active) ? bist_rd2_adr : rd2_adr_in;
   assign rd3_enb_out = (active) ? bist_rd3_enb : rd3_enb_in;
   assign rd3_adr_out = (active) ? bist_rd3_adr : rd3_adr_in;
   assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
   assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
   assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
   assign wr1_enb_out = (active) ? bist_wr1_enb : wr1_enb_in;
   assign wr1_adr_out = (active) ? bist_wr1_adr : wr1_adr_in;
   assign wr1_dat_out = (active) ? bist_wr1_dat : wr1_dat_in;

endmodule
module ra_bist_ddr (

    clk,
    reset,
    ctl,
    status,
    rd0_enb_in,
    rd0_adr_in,
    rd1_enb_in,
    rd1_adr_in,
    rd2_enb_in,
    rd2_adr_in,
    rd3_enb_in,
    rd3_adr_in,
    wr0_enb_in,
    wr0_adr_in,
    wr0_dat_in,
    wr1_enb_in,
    wr1_adr_in,
    wr1_dat_in,
    rd0_enb_out,
    rd0_adr_out,
    rd0_dat,
    rd1_enb_out,
    rd1_adr_out,
    rd1_dat,
    rd2_enb_out,
    rd2_adr_out,
    rd2_dat,
    rd3_enb_out,
    rd3_adr_out,
    rd3_dat,
    wr0_enb_out,
    wr0_adr_out,
    wr0_dat_out,
    wr1_enb_out,
    wr1_adr_out,
    wr1_dat_out

);


 parameter GENMODE = `GENMODE;

   input          clk;
   input          reset;
   input  [0:31]  ctl;

   input          rd0_enb_in;
   input  [0:5]   rd0_adr_in;
   input          rd1_enb_in;
   input  [0:5]   rd1_adr_in;
   input          rd2_enb_in;
   input  [0:5]   rd2_adr_in;
   input          rd3_enb_in;
   input  [0:5]   rd3_adr_in;
   input          wr0_enb_in;
   input  [0:5]   wr0_adr_in;
   input  [0:71]  wr0_dat_in;
   input          wr1_enb_in;
   input  [0:5]   wr1_adr_in;
   input  [0:71]  wr1_dat_in;

   output [0:31]  status;
   output         rd0_enb_out;
   output [0:5]   rd0_adr_out;
   input  [0:71]  rd0_dat;
   output         rd1_enb_out;
   output [0:5]   rd1_adr_out;
   input  [0:71]  rd1_dat;
   output         rd2_enb_out;
   output [0:5]   rd2_adr_out;
   input  [0:71]  rd2_dat;
   output         rd3_enb_out;
   output [0:5]   rd3_adr_out;
   input  [0:71]  rd3_dat;
   output         wr0_enb_out;
   output [0:5]   wr0_adr_out;
   output [0:71]  wr0_dat_out;
   output         wr1_enb_out;
   output [0:5]   wr1_adr_out;
   output [0:71]  wr1_dat_out;

   reg    [0:5]   seq_q;
   wire   [0:5]   seq_d;
   wire           active;
   wire           bist_rd0_enb;
   wire   [0:5]   bist_rd0_adr;
   wire           bist_rd1_enb;
   wire   [0:5]   bist_rd1_adr;
   wire           bist_rd2_enb;
   wire   [0:5]   bist_rd2_adr;
   wire           bist_rd3_enb;
   wire   [0:5]   bist_rd3_adr;
   wire           bist_wr0_enb;
   wire   [0:5]   bist_wr0_adr;
   wire   [0:71]  bist_wr0_dat;
   wire           bist_wr1_enb;
   wire   [0:5]   bist_wr1_adr;
   wire   [0:71]  bist_wr1_dat;


   always @ (posedge clk) begin
      if (reset)
         seq_q <= 6'h3F;
      else
         seq_q <= seq_d;
   end


   assign seq_d = seq_q;
   assign active = seq_q != 6'h3F;
   assign status = 0;


   assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
   assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
   assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
   assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
   assign rd2_enb_out = (active) ? bist_rd2_enb : rd2_enb_in;
   assign rd2_adr_out = (active) ? bist_rd2_adr : rd2_adr_in;
   assign rd3_enb_out = (active) ? bist_rd3_enb : rd3_enb_in;
   assign rd3_adr_out = (active) ? bist_rd3_adr : rd3_adr_in;
   assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
   assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
   assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
   assign wr1_enb_out = (active) ? bist_wr1_enb : wr1_enb_in;
   assign wr1_adr_out = (active) ? bist_wr1_adr : wr1_adr_in;
   assign wr1_dat_out = (active) ? bist_wr1_dat : wr1_dat_in;

endmodule