data/full_repos/permissive/506208052/src/hdl/AXIInputRegisters_1.0/hdl/AXIInputRegisters_v1_0_S00_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/AXIInputRegisters_1.0/hdl/AXIInputRegisters_v1_0_S00_AXI.v:269: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                                           : ... In instance AXIInputRegisters_v1_0_S00_AXI\n       axi_araddr  <= 32\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module AXIInputRegisters_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 6
	)
	(


        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg0_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg1_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg2_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg3_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg4_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg5_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg6_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg7_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg8_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg9_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg10_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg11_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg12_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg13_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg14_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg15_input,



		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 3;




	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      reg_data_out <= 0;
	    end 
	  else
	    begin    

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
                4'h0   : reg_data_out <= reg0_input;
                4'h1   : reg_data_out <= reg1_input;
                4'h2   : reg_data_out <= reg2_input;
                4'h3   : reg_data_out <= reg3_input;
                4'h4   : reg_data_out <= reg4_input;
                4'h5   : reg_data_out <= reg5_input;
                4'h6   : reg_data_out <= reg6_input;
                4'h7   : reg_data_out <= reg7_input;
                4'h8   : reg_data_out <= reg8_input;
                4'h9   : reg_data_out <= reg9_input;
                4'hA   : reg_data_out <= reg10_input;
                4'hB   : reg_data_out <= reg11_input;
                4'hC   : reg_data_out <= reg12_input;
                4'hD   : reg_data_out <= reg13_input;
                4'hE   : reg_data_out <= reg14_input;
                4'hF   : reg_data_out <= reg15_input;
	        default : reg_data_out <= 0;
	      endcase
	    end   
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    





	endmodule
module AXIInputRegisters_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 6
	)
	(


        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg0_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg1_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg2_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg3_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg4_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg5_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg6_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg7_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg8_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg9_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg10_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg11_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg12_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg13_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg14_input,
        input wire [C_S_AXI_DATA_WIDTH-1 : 0] reg15_input,



		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);



	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 3;




	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      reg_data_out <= 0;
	    end 
	  else
	    begin    

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
                4'h0   : reg_data_out <= reg0_input;
                4'h1   : reg_data_out <= reg1_input;
                4'h2   : reg_data_out <= reg2_input;
                4'h3   : reg_data_out <= reg3_input;
                4'h4   : reg_data_out <= reg4_input;
                4'h5   : reg_data_out <= reg5_input;
                4'h6   : reg_data_out <= reg6_input;
                4'h7   : reg_data_out <= reg7_input;
                4'h8   : reg_data_out <= reg8_input;
                4'h9   : reg_data_out <= reg9_input;
                4'hA   : reg_data_out <= reg10_input;
                4'hB   : reg_data_out <= reg11_input;
                4'hC   : reg_data_out <= reg12_input;
                4'hD   : reg_data_out <= reg13_input;
                4'hE   : reg_data_out <= reg14_input;
                4'hF   : reg_data_out <= reg15_input;
	        default : reg_data_out <= 0;
	      endcase
	    end   
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    





	endmodule