data/full_repos/permissive/463395574/mux.v
1: b'%Error: data/full_repos/permissive/463395574/mux.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/mux.v:6: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] seqAddr,  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:7: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] jmpAddr,  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:10: Define or directive not defined: \'`ADDR_SIZE\'\n    output [`ADDR_SIZE-1:0] out\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:16: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] reg1Data,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:17: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] pc,       \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:20: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] out\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:22: Define or directive not defined: \'`WORD_LEN\'\n    assign out = (ALUSrcA == 0) ? reg1Data : {{{`WORD_LEN-`ADDR_SIZE}{1\'b0}}, pc};\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:22: Define or directive not defined: \'`ADDR_SIZE\'\n    assign out = (ALUSrcA == 0) ? reg1Data : {{{`WORD_LEN-`ADDR_SIZE}{1\'b0}}, pc};\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:22: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    assign out = (ALUSrcA == 0) ? reg1Data : {{{`WORD_LEN-`ADDR_SIZE}{1\'b0}}, pc};\n                                                                    ^\n%Error: data/full_repos/permissive/463395574/mux.v:26: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] reg2Data,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:27: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] immData,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:30: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] out\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:36: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] ALUResult,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:37: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] memData,    \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:38: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] newSeqAddr,  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/mux.v:41: Define or directive not defined: \'`WORD_LEN\'\n    output reg [`WORD_LEN-1:0] out\n                ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module ALUSrcBMux (
    input [`WORD_LEN-1:0] reg2Data,
    input [`WORD_LEN-1:0] immData,
    input ALUSrcB,

    output [`WORD_LEN-1:0] out
);
    assign out = (ALUSrcB == 0) ? reg2Data : immData;
endmodule
module ALUSrcBMux (
    input [`WORD_LEN-1:0] reg2Data,
    input [`WORD_LEN-1:0] immData,
    input ALUSrcB,

    output [`WORD_LEN-1:0] out
);

    assign out = (ALUSrcB == 0) ? reg2Data : immData;
endmodule