data/full_repos/permissive/437677776/rtl/verilog/sync_clk_core.v
1: b'%Error: data/full_repos/permissive/437677776/rtl/verilog/sync_clk_core.v:39: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module sync_clk_core(

  clk_xgmii_tx, reset_xgmii_tx_n
  );

input         clk_xgmii_tx;
input         reset_xgmii_tx_n;
























endmodule
module sync_clk_core(

  clk_xgmii_tx, reset_xgmii_tx_n
  );


input         clk_xgmii_tx;
input         reset_xgmii_tx_n;
























endmodule