data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/52_Mt2015_eq2.v
data/verilator_xmls/f76ad24b-943d-474c-89c2-436ef931951d.xml
module top_module ( input [1:0] A, input [1:0] B, output z ); 







    assign z = (A[1:0] == B[1:0]);







endmodule
module top_module ( input [1:0] A, input [1:0] B, output z );
 







    assign z = (A[1:0] == B[1:0]);







endmodule