data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/minutes.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: breadboard),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: breadboard)/minutes.v\n%Error: Exiting due to 9 error(s)\n'
module minutes(
    input tick_in,
    output tick_hours,
    output [5:0] minutes
    );
    
    reg [5:0] minutes_counter = 0;
    
    always @(negedge tick_in) begin
        if(minutes_counter == 59)
            minutes_counter <= 0;
        else
            minutes_counter <= minutes_counter + 1;
    end
    
    assign minutes = minutes_counter;
    assign tick_hours = (minutes_counter == 59) ? 1 : 0;
    
endmodule
module minutes(
    input tick_in,
    output tick_hours,
    output [5:0] minutes
    );

    
    reg [5:0] minutes_counter = 0;
    
    always @(negedge tick_in) begin
        if(minutes_counter == 59)
            minutes_counter <= 0;
        else
            minutes_counter <= minutes_counter + 1;
    end
    
    assign minutes = minutes_counter;
    assign tick_hours = (minutes_counter == 59) ? 1 : 0;
    
endmodule