data/full_repos/permissive/468043930/verilog/rtl/azadi_soc_top_caravel.v
1: b"%Error: data/full_repos/permissive/468043930/verilog/rtl/azadi_soc_top_caravel.v:168: Cannot find file containing module: 'azadi_soc_top'\n  azadi_soc_top soc_top(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468043930/verilog/rtl,data/full_repos/permissive/468043930/azadi_soc_top\n             data/full_repos/permissive/468043930/verilog/rtl,data/full_repos/permissive/468043930/azadi_soc_top.v\n             data/full_repos/permissive/468043930/verilog/rtl,data/full_repos/permissive/468043930/azadi_soc_top.sv\n             azadi_soc_top\n             azadi_soc_top.v\n             azadi_soc_top.sv\n             obj_dir/azadi_soc_top\n             obj_dir/azadi_soc_top.v\n             obj_dir/azadi_soc_top.sv\n%Error: Exiting due to 1 error(s)\n"
module azadi_soc_top_caravel (
  `ifdef USE_POWER_PINS
      inout vdda1,
      inout vdda2,
      inout vssa1,
      inout vssa2,
      inout vccd1,
      inout vccd2,
      inout vssd1,
      inout vssd2,
  `endif


    input         wb_clk_i,
    input         wb_rst_i,
    input         wbs_stb_i,
    input         wbs_cyc_i,
    input         wbs_we_i,
    input [3:0]   wbs_sel_i,
    input [31:0]  wbs_dat_i,
    input [31:0]  wbs_adr_i,
    output        wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-2:0] io_in,  
    output [`MPRJ_IO_PADS-2:0] io_out,
    output [`MPRJ_IO_PADS-2:0] io_oeb,





    inout [`MPRJ_IO_PADS-11:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);

  wire clk_i;  
  wire rst_ni; 
  wire prog;
  wire led;
  

  wire [15:0] clks_per_bit;  


  wire [19:0] gpio_i;
  wire [19:0] gpio_o;
  wire [19:0] gpio_oe;



  wire uart_tx;
  wire uart_rx;


  wire pwm_o_1;
  wire pwm_o_2;
  wire pwm1_oe;
  wire pwm2_oe;


  wire [1:0] ss_o;        
  wire       sclk_o;      
  wire       sd_o;
  wire       sd_oe;       
  wire       sd_i;

  wire       qsclk_o;
  wire       qcs_o;
  wire [3:0] qsd_i;
  wire [3:0] qsd_o;
  wire [3:0] qsd_oe;



  assign io_out[0] = sclk_o;
  assign io_oeb[0] = 1'b0;
  assign io_out[1] = sd_o;
  assign io_oeb[1] = ~sd_oe;

  assign sd_i      = io_in[2];
  assign io_oeb[2] = 1'b1;
  assign io_out[2] = 1'b0;

  assign io_out[3] = ss_o[0];
  assign io_oeb[3] = 1'b0;
  assign io_out[4] = ss_o[1];
  assign io_oeb[4] = 1'b0;



  assign uart_rx   = io_in[5];
  assign io_oeb[5] = 1'b1;
  assign io_out[5] = 1'b0;

  assign io_out[6] = uart_tx;
  assign io_oeb[6] = 1'b0;



  assign prog      = io_in[7];
  assign io_oeb[7] = 1'b1;
  assign io_out[7] = 1'b0;



  assign io_out[8] = pwm_o_1;
  assign io_oeb[8] = ~pwm1_oe;
  assign io_out[9] = pwm_o_2;
  assign io_oeb[9] = ~pwm2_oe;



  assign io_out[29:10] = gpio_o;
  assign gpio_i        = io_in[29:10];
  assign io_oeb[29:10] = ~gpio_oe;



  assign io_out[30] = led;
  assign io_oeb[30] = 1'b0;


  assign io_out[31] = qcs_o;
  assign io_oeb[31] = 1'b0;

  assign io_out[32] = qsclk_o;
  assign io_oeb[32] = 1'b0;

  assign io_out[36:33] = qsd_o;
  assign qsd_i         = io_in[36:33];
  assign io_oeb[36:33] = ~qsd_oe;


  assign clks_per_bit  = la_data_in[15:0];

  azadi_soc_top soc_top(
  `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
  `endif
    .clk_i(wb_clk_i),
    .rst_ni(~wb_rst_i),
    .prog(prog),
    .boot_led(led),


    .clks_per_bit(clks_per_bit), 


    .gpio_i(gpio_i),
    .gpio_o(gpio_o),
    .gpio_oe(gpio_oe),


    .uart_tx(uart_tx),
    .uart_rx(uart_rx),


    .pwm_o(pwm_o_1),
    .pwm_o_2(pwm_o_2),
    .pwm1_oe(pwm1_oe),
    .pwm2_oe(pwm2_oe),


    .ss_o(ss_o),
    .sclk_o(sclk_o),      
    .sd_o(sd_o),
    .sd_oe(sd_oe),       
    .sd_i(sd_i),



    .qsclk_o (qsclk_o),
    .qcs_o   (qcs_o),
    .qsd_i   (qsd_i),
    .qsd_o   (qsd_o),
    .qsd_oe  (qsd_oe)
  );

endmodule
module azadi_soc_top_caravel (
  `ifdef USE_POWER_PINS
      inout vdda1,
      inout vdda2,
      inout vssa1,
      inout vssa2,
      inout vccd1,
      inout vccd2,
      inout vssd1,
      inout vssd2,
  `endif


    input         wb_clk_i,
    input         wb_rst_i,
    input         wbs_stb_i,
    input         wbs_cyc_i,
    input         wbs_we_i,
    input [3:0]   wbs_sel_i,
    input [31:0]  wbs_dat_i,
    input [31:0]  wbs_adr_i,
    output        wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-2:0] io_in,  
    output [`MPRJ_IO_PADS-2:0] io_out,
    output [`MPRJ_IO_PADS-2:0] io_oeb,





    inout [`MPRJ_IO_PADS-11:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);


  wire clk_i;  
  wire rst_ni; 
  wire prog;
  wire led;
  

  wire [15:0] clks_per_bit;  


  wire [19:0] gpio_i;
  wire [19:0] gpio_o;
  wire [19:0] gpio_oe;



  wire uart_tx;
  wire uart_rx;


  wire pwm_o_1;
  wire pwm_o_2;
  wire pwm1_oe;
  wire pwm2_oe;


  wire [1:0] ss_o;        
  wire       sclk_o;      
  wire       sd_o;
  wire       sd_oe;       
  wire       sd_i;

  wire       qsclk_o;
  wire       qcs_o;
  wire [3:0] qsd_i;
  wire [3:0] qsd_o;
  wire [3:0] qsd_oe;



  assign io_out[0] = sclk_o;
  assign io_oeb[0] = 1'b0;
  assign io_out[1] = sd_o;
  assign io_oeb[1] = ~sd_oe;

  assign sd_i      = io_in[2];
  assign io_oeb[2] = 1'b1;
  assign io_out[2] = 1'b0;

  assign io_out[3] = ss_o[0];
  assign io_oeb[3] = 1'b0;
  assign io_out[4] = ss_o[1];
  assign io_oeb[4] = 1'b0;



  assign uart_rx   = io_in[5];
  assign io_oeb[5] = 1'b1;
  assign io_out[5] = 1'b0;

  assign io_out[6] = uart_tx;
  assign io_oeb[6] = 1'b0;



  assign prog      = io_in[7];
  assign io_oeb[7] = 1'b1;
  assign io_out[7] = 1'b0;



  assign io_out[8] = pwm_o_1;
  assign io_oeb[8] = ~pwm1_oe;
  assign io_out[9] = pwm_o_2;
  assign io_oeb[9] = ~pwm2_oe;



  assign io_out[29:10] = gpio_o;
  assign gpio_i        = io_in[29:10];
  assign io_oeb[29:10] = ~gpio_oe;



  assign io_out[30] = led;
  assign io_oeb[30] = 1'b0;


  assign io_out[31] = qcs_o;
  assign io_oeb[31] = 1'b0;

  assign io_out[32] = qsclk_o;
  assign io_oeb[32] = 1'b0;

  assign io_out[36:33] = qsd_o;
  assign qsd_i         = io_in[36:33];
  assign io_oeb[36:33] = ~qsd_oe;


  assign clks_per_bit  = la_data_in[15:0];

  azadi_soc_top soc_top(
  `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
  `endif
    .clk_i(wb_clk_i),
    .rst_ni(~wb_rst_i),
    .prog(prog),
    .boot_led(led),


    .clks_per_bit(clks_per_bit), 


    .gpio_i(gpio_i),
    .gpio_o(gpio_o),
    .gpio_oe(gpio_oe),


    .uart_tx(uart_tx),
    .uart_rx(uart_rx),


    .pwm_o(pwm_o_1),
    .pwm_o_2(pwm_o_2),
    .pwm1_oe(pwm1_oe),
    .pwm2_oe(pwm2_oe),


    .ss_o(ss_o),
    .sclk_o(sclk_o),      
    .sd_o(sd_o),
    .sd_oe(sd_oe),       
    .sd_i(sd_i),



    .qsclk_o (qsclk_o),
    .qcs_o   (qcs_o),
    .qsd_i   (qsd_i),
    .qsd_o   (qsd_o),
    .qsd_oe  (qsd_oe)
  );

endmodule