data/full_repos/permissive/434840709/作业/adder练习/cg.v
data/verilator_xmls/95d718c6-b0a4-4d52-a06f-c20c3c462df6.xml
module add1(
    input a,input b,input cin,output sum,output cout
);
assign sum = (a&b&cin)|(~a&~b&cin)|(a&~b&~cin)|(~a&b&~cin);
assign cout = a&b|a&cin|b&cin;
endmodule
module add1(
    input a,input b,input cin,output sum,output cout
);

assign sum = (a&b&cin)|(~a&~b&cin)|(a&~b&~cin)|(~a&b&~cin);
assign cout = a&b|a&cin|b&cin;
endmodule