data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/odin_no_signal_logic.v
data/verilator_xmls/2570d63b-0eab-485d-af69-45f4d66ba7d9.xml
module foobar (clk,d_in, d_out);

input clk;
input  d_in;
output  d_out;



assign d_out = a;
wire  a;
wire  b;





assign a = (b & d_in);




endmodule
module foobar (clk,d_in, d_out);


input clk;
input  d_in;
output  d_out;



assign d_out = a;
wire  a;
wire  b;





assign a = (b & d_in);




endmodule