data/full_repos/permissive/461569093/Mini ALU/alumain.v
1: b'%Error: Cannot find file containing module: ALU,data/full_repos/permissive/461569093\n        ... Looked in:\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.v\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.sv\n             ALU,data/full_repos/permissive/461569093\n             ALU,data/full_repos/permissive/461569093.v\n             ALU,data/full_repos/permissive/461569093.sv\n             obj_dir/ALU,data/full_repos/permissive/461569093\n             obj_dir/ALU,data/full_repos/permissive/461569093.v\n             obj_dir/ALU,data/full_repos/permissive/461569093.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461569093/Mini\n%Error: Cannot find file containing module: ALU/alumain.v\n%Error: Exiting due to 3 error(s)\n'
module alumain(
    input [2:0] fxn,
    input [5:0] a,b,
    output [5:0] finalresult
    );
    reg [5:0] temp;
    wire selin;
    assign selin = 1'b0;
    wire [5:0] result1,result2,result3,result4,result6,result7,result8;
    wire result5;
    wire overflowout, carryout;
    


    alufirst DUT5 (.x1(a), .y1(b), .c1(result1)); 

    alusecond DUT6 (.x2(a), .y2(b), .c2(result2)); 

    bit6_addsub DUT3  (.x(-a), .y(b-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result3));

    bit6_addsub DUT4  (.x(a-a), .y(-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result4)); 

    bit8 DUT7 (.x3(a), .y3(b), .c3(result5)); 

    xnoralu DUT8(.i0(a[0]),.i1(b[0]),.op(result6[0])); 
    xnoralu DUT9(.i0(a[1]),.i1(b[1]),.op(result6[1]));
    xnoralu DUT10(.i0(a[2]),.i1(b[2]),.op(result6[2]));
    xnoralu DUT11(.i0(a[3]),.i1(b[3]),.op(result6[3]));
    xnoralu DUT12(.i0(a[4]),.i1(b[4]),.op(result6[4]));
    xnoralu DUT13(.i0(a[5]),.i1(b[5]),.op(result6[5]));

    bit6_addsub DUT1  (.x(a), .y(b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result7));

    bit6_addsub DUT2  (.x(a), .y(-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result8));
   
    always @(*)
    begin
        case (fxn)
        3'b000: temp = result1;
        3'b001: temp = result2;
        3'b010: temp = result3;
        3'b011: temp = result4;
        3'b100: temp = result5;
        3'b101: temp = result6;
        3'b110: temp = result7;
        3'b111: temp = result8;
           
       endcase
     end
    assign finalresult = temp;
    initial
    begin
    $monitor("A: %b  B:  %b  -A:  %b  -B: %b  A<B :  %b  A nxor B : %b  A+B :  %b  A-B :  %b  - finalresult(DEPENDING ON FXN VALUE) -  %b", result1, result2, result3, result4, result5, result6, result7, result8, finalresult);
    
    end
endmodule
module alumain(
    input [2:0] fxn,
    input [5:0] a,b,
    output [5:0] finalresult
    );

    reg [5:0] temp;
    wire selin;
    assign selin = 1'b0;
    wire [5:0] result1,result2,result3,result4,result6,result7,result8;
    wire result5;
    wire overflowout, carryout;
    


    alufirst DUT5 (.x1(a), .y1(b), .c1(result1)); 

    alusecond DUT6 (.x2(a), .y2(b), .c2(result2)); 

    bit6_addsub DUT3  (.x(-a), .y(b-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result3));

    bit6_addsub DUT4  (.x(a-a), .y(-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result4)); 

    bit8 DUT7 (.x3(a), .y3(b), .c3(result5)); 

    xnoralu DUT8(.i0(a[0]),.i1(b[0]),.op(result6[0])); 
    xnoralu DUT9(.i0(a[1]),.i1(b[1]),.op(result6[1]));
    xnoralu DUT10(.i0(a[2]),.i1(b[2]),.op(result6[2]));
    xnoralu DUT11(.i0(a[3]),.i1(b[3]),.op(result6[3]));
    xnoralu DUT12(.i0(a[4]),.i1(b[4]),.op(result6[4]));
    xnoralu DUT13(.i0(a[5]),.i1(b[5]),.op(result6[5]));

    bit6_addsub DUT1  (.x(a), .y(b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result7));

    bit6_addsub DUT2  (.x(a), .y(-b), .sel(selin), .overflow(overflowout), .c_out(carryout), .sum(result8));
   
    always @(*)
    begin
        case (fxn)
        3'b000: temp = result1;
        3'b001: temp = result2;
        3'b010: temp = result3;
        3'b011: temp = result4;
        3'b100: temp = result5;
        3'b101: temp = result6;
        3'b110: temp = result7;
        3'b111: temp = result8;
           
       endcase
     end
    assign finalresult = temp;
    initial
    begin
    $monitor("A: %b  B:  %b  -A:  %b  -B: %b  A<B :  %b  A nxor B : %b  A+B :  %b  A-B :  %b  - finalresult(DEPENDING ON FXN VALUE) -  %b", result1, result2, result3, result4, result5, result6, result7, result8, finalresult);
    
    end
endmodule