data/full_repos/permissive/500711628/register_writer/register_writer.v
data/verilator_xmls/d568c5c5-43bd-4d9f-89ad-4bf2227bc391.xml
function [19:0] f (
		input [15:0] _instr,
		input [15:0] _ALU_data,
		input [15:0] _memory_data,
		input _rawf,
		input _rbwf
	);
		begin
	
			reg [1:0] op1 = _instr[15:14];
			reg [2:0] rawa = _instr[13:11];
			reg [2:0] rbwa = _instr[10:8];
			
			reg [15:0] _write_data;
			reg [2:0] _write_address;
			reg _is_write;
			
			_write_data = (op1 == 2'b00 ? _memory_data : _ALU_data);
			
			if(_rawf) begin
				_write_address = rawa;
			end
			else if(_rbwf) begin
				_write_address = rbwa;
			end
			else begin
				_write_address = 3'b000;
			end
			
			_is_write = (_rawf || _rbwf);
			
			f = {_write_data,_write_address,_is_write};
			
		end
	
	endfunction
function [19:0] f (
		input [15:0] _instr,
		input [15:0] _ALU_data,
		input [15:0] _memory_data,
		input _rawf,
		input _rbwf
	);

		begin
	
			reg [1:0] op1 = _instr[15:14];
			reg [2:0] rawa = _instr[13:11];
			reg [2:0] rbwa = _instr[10:8];
			
			reg [15:0] _write_data;
			reg [2:0] _write_address;
			reg _is_write;
			
			_write_data = (op1 == 2'b00 ? _memory_data : _ALU_data);
			
			if(_rawf) begin
				_write_address = rawa;
			end
			else if(_rbwf) begin
				_write_address = rbwa;
			end
			else begin
				_write_address = 3'b000;
			end
			
			_is_write = (_rawf || _rbwf);
			
			f = {_write_data,_write_address,_is_write};
			
		end
	
	endfunction