data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:162: Cannot find file containing module: 'BUFGCE'\nBUFGCE apb_clk_buf\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE.sv\n             BUFGCE\n             BUFGCE.v\n             BUFGCE.sv\n             obj_dir/BUFGCE\n             obj_dir/BUFGCE.v\n             obj_dir/BUFGCE.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:201: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_data_bist_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:241: Cannot find file containing module: 'BUFGCE'\nBUFGCE data_bank0_clk_buf\n^~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:247: Cannot find file containing module: 'BUFGCE'\nBUFGCE data_bank1_clk_buf\n^~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:306: Cannot find file containing module: 'BUFGCE'\nBUFGCE tag_bank0_clk_buf\n^~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v:312: Cannot find file containing module: 'BUFGCE'\nBUFGCE tag_bank1_clk_buf\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module ct_mp_clk_top(
  apb_clk,
  apb_clk_en,
  axim_clk_en,
  axim_clk_en_f,
  forever_core0_clk,
  forever_core1_clk,
  forever_cpuclk,
  forever_jtgclk,
  l2c_data_clk_bank_0,
  l2c_data_clk_bank_1,
  l2c_data_ram_clk_en_bank_0,
  l2c_data_ram_clk_en_bank_1,
  l2c_tag_clk_bank_0,
  l2c_tag_clk_bank_1,
  l2c_tag_ram_clk_en_bank_0,
  l2c_tag_ram_clk_en_bank_1,
  pad_had_jtg_tclk,
  pad_l2c_data_mbist_clk_ratio,
  pad_l2c_tag_mbist_clk_ratio,
  pad_yy_dft_clk_rst_b,
  pad_yy_icg_scan_en,
  pad_yy_mbist_mode,
  pad_yy_scan_mode,
  phl_rst_b,
  pll_cpu_clk
);


input          axim_clk_en;                   
input          l2c_data_ram_clk_en_bank_0;    
input          l2c_data_ram_clk_en_bank_1;    
input          l2c_tag_ram_clk_en_bank_0;     
input          l2c_tag_ram_clk_en_bank_1;     
input          pad_had_jtg_tclk;              
input   [2:0]  pad_l2c_data_mbist_clk_ratio;  
input   [2:0]  pad_l2c_tag_mbist_clk_ratio;   
input          pad_yy_dft_clk_rst_b;          
input          pad_yy_icg_scan_en;            
input          pad_yy_mbist_mode;             
input          pad_yy_scan_mode;              
input          phl_rst_b;                     
input          pll_cpu_clk;                   
output         apb_clk;                       
output         apb_clk_en;                    
output         axim_clk_en_f;                 
output         forever_core0_clk;             
output         forever_core1_clk;             
output         forever_cpuclk;                
output         forever_jtgclk;                
output         l2c_data_clk_bank_0;           
output         l2c_data_clk_bank_1;           
output         l2c_tag_clk_bank_0;            
output         l2c_tag_clk_bank_1;            


reg            apb_clk_en_f;                  
reg            axim_clk_en_f;                 
reg     [2:0]  l2c_data_ram_bist_clk_ratio;   
reg     [2:0]  l2c_tag_ram_bist_clk_ratio;    
reg            peripheral_clk_en;             


wire           apb_clk_en;                    
wire           axim_clk_en;                   
wire           bist_clk;                      
wire           bist_clk_en;                   
wire           data_ram_bist_cnt_idle;        
wire           data_ram_clk_en_bank_0;        
wire           data_ram_clk_en_bank_1;        
wire           forever_core0_clk;             
wire           forever_core1_clk;             
wire           forever_cpuclk;                
wire           forever_jtgclk;                
wire           l2c_data_clk_bank_0;           
wire           l2c_data_clk_bank_0_before_occ; 
wire           l2c_data_clk_bank_1;           
wire           l2c_data_clk_bank_1_before_occ; 
wire           l2c_data_ram_clk_en_bank_0;    
wire           l2c_data_ram_clk_en_bank_1;    
wire           l2c_tag_clk_bank_0;            
wire           l2c_tag_clk_bank_0_before_occ; 
wire           l2c_tag_clk_bank_1;            
wire           l2c_tag_clk_bank_1_before_occ; 
wire           l2c_tag_ram_clk_en_bank_0;     
wire           l2c_tag_ram_clk_en_bank_1;     
wire           pad_had_jtg_tclk;              
wire    [2:0]  pad_l2c_data_mbist_clk_ratio;  
wire    [2:0]  pad_l2c_tag_mbist_clk_ratio;   
wire           pad_yy_dft_clk_rst_b;          
wire           pad_yy_icg_scan_en;            
wire           pad_yy_mbist_mode;             
wire           pad_yy_scan_mode;              
wire           phl_rst_b;                     
wire           pll_cpu_clk;                   
wire           tag_ram_bist_cnt_idle;         
wire           tag_ram_clk_en_bank_0;         
wire           tag_ram_clk_en_bank_1;         







assign forever_cpuclk = pll_cpu_clk;




assign forever_core0_clk = forever_cpuclk;

assign forever_core1_clk = forever_cpuclk;







assign forever_jtgclk = pad_had_jtg_tclk;







always@(posedge pll_cpu_clk or negedge phl_rst_b)
begin
  if (!phl_rst_b)
    peripheral_clk_en <= 1'b0;
  else
    peripheral_clk_en <= ~peripheral_clk_en;
end

always@(posedge pll_cpu_clk)
begin
  apb_clk_en_f <= peripheral_clk_en;
end

assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;



BUFGCE apb_clk_buf
(.O   (apb_clk),
 .I   (pll_cpu_clk),
 .CE  (apb_clk_en_f)
);























always@(posedge forever_cpuclk)
begin
  axim_clk_en_f <= axim_clk_en;
end





assign bist_clk_en = pad_yy_mbist_mode | pad_yy_scan_mode;

gated_clk_cell  x_data_bist_gated_clk (
  .clk_in             (pll_cpu_clk       ),
  .clk_out            (bist_clk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (bist_clk_en       ),
  .module_en          (1'b0              ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b) 
begin
  if (!pad_yy_dft_clk_rst_b)
    l2c_data_ram_bist_clk_ratio[2:0] <= 3'b0;
  else if (bist_clk_en) begin
    if (data_ram_bist_cnt_idle)
      l2c_data_ram_bist_clk_ratio[2:0] <= pad_l2c_data_mbist_clk_ratio[2:0];
    else
      l2c_data_ram_bist_clk_ratio[2:0] <= l2c_data_ram_bist_clk_ratio[2:0] - 3'b001;
  end
end

assign data_ram_bist_cnt_idle = l2c_data_ram_bist_clk_ratio[2:0] == 3'b000;

assign data_ram_clk_en_bank_0 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_0;
assign data_ram_clk_en_bank_1 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_1;






BUFGCE data_bank0_clk_buf
(.O   (l2c_data_clk_bank_0_before_occ),
 .I   (pll_cpu_clk),
 .CE  (data_ram_clk_en_bank_0)
);

BUFGCE data_bank1_clk_buf
(.O   (l2c_data_clk_bank_1_before_occ),
 .I   (pll_cpu_clk),
 .CE  (data_ram_clk_en_bank_1)
);





















assign l2c_data_clk_bank_0 = l2c_data_clk_bank_0_before_occ;
assign l2c_data_clk_bank_1 = l2c_data_clk_bank_1_before_occ;






         



always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b)
begin
  if (!pad_yy_dft_clk_rst_b)
    l2c_tag_ram_bist_clk_ratio[2:0] <= 3'b0;
  else if (bist_clk_en) begin
    if (tag_ram_bist_cnt_idle)
      l2c_tag_ram_bist_clk_ratio[2:0] <= pad_l2c_tag_mbist_clk_ratio[2:0];
    else
      l2c_tag_ram_bist_clk_ratio[2:0] <= l2c_tag_ram_bist_clk_ratio[2:0] - 3'b001;
  end
end

assign tag_ram_bist_cnt_idle = l2c_tag_ram_bist_clk_ratio[2:0] == 3'b000;

assign tag_ram_clk_en_bank_0 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_0;
assign tag_ram_clk_en_bank_1 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_1;





BUFGCE tag_bank0_clk_buf
(.O   (l2c_tag_clk_bank_0_before_occ),
 .I   (pll_cpu_clk),
 .CE  (tag_ram_clk_en_bank_0)
);

BUFGCE tag_bank1_clk_buf
(.O   (l2c_tag_clk_bank_1_before_occ),
 .I   (pll_cpu_clk),
 .CE  (tag_ram_clk_en_bank_1)
);





















assign l2c_tag_clk_bank_0 = l2c_tag_clk_bank_0_before_occ;
assign l2c_tag_clk_bank_1 = l2c_tag_clk_bank_1_before_occ;








endmodule
module ct_mp_clk_top(
  apb_clk,
  apb_clk_en,
  axim_clk_en,
  axim_clk_en_f,
  forever_core0_clk,
  forever_core1_clk,
  forever_cpuclk,
  forever_jtgclk,
  l2c_data_clk_bank_0,
  l2c_data_clk_bank_1,
  l2c_data_ram_clk_en_bank_0,
  l2c_data_ram_clk_en_bank_1,
  l2c_tag_clk_bank_0,
  l2c_tag_clk_bank_1,
  l2c_tag_ram_clk_en_bank_0,
  l2c_tag_ram_clk_en_bank_1,
  pad_had_jtg_tclk,
  pad_l2c_data_mbist_clk_ratio,
  pad_l2c_tag_mbist_clk_ratio,
  pad_yy_dft_clk_rst_b,
  pad_yy_icg_scan_en,
  pad_yy_mbist_mode,
  pad_yy_scan_mode,
  phl_rst_b,
  pll_cpu_clk
);



input          axim_clk_en;                   
input          l2c_data_ram_clk_en_bank_0;    
input          l2c_data_ram_clk_en_bank_1;    
input          l2c_tag_ram_clk_en_bank_0;     
input          l2c_tag_ram_clk_en_bank_1;     
input          pad_had_jtg_tclk;              
input   [2:0]  pad_l2c_data_mbist_clk_ratio;  
input   [2:0]  pad_l2c_tag_mbist_clk_ratio;   
input          pad_yy_dft_clk_rst_b;          
input          pad_yy_icg_scan_en;            
input          pad_yy_mbist_mode;             
input          pad_yy_scan_mode;              
input          phl_rst_b;                     
input          pll_cpu_clk;                   
output         apb_clk;                       
output         apb_clk_en;                    
output         axim_clk_en_f;                 
output         forever_core0_clk;             
output         forever_core1_clk;             
output         forever_cpuclk;                
output         forever_jtgclk;                
output         l2c_data_clk_bank_0;           
output         l2c_data_clk_bank_1;           
output         l2c_tag_clk_bank_0;            
output         l2c_tag_clk_bank_1;            


reg            apb_clk_en_f;                  
reg            axim_clk_en_f;                 
reg     [2:0]  l2c_data_ram_bist_clk_ratio;   
reg     [2:0]  l2c_tag_ram_bist_clk_ratio;    
reg            peripheral_clk_en;             


wire           apb_clk_en;                    
wire           axim_clk_en;                   
wire           bist_clk;                      
wire           bist_clk_en;                   
wire           data_ram_bist_cnt_idle;        
wire           data_ram_clk_en_bank_0;        
wire           data_ram_clk_en_bank_1;        
wire           forever_core0_clk;             
wire           forever_core1_clk;             
wire           forever_cpuclk;                
wire           forever_jtgclk;                
wire           l2c_data_clk_bank_0;           
wire           l2c_data_clk_bank_0_before_occ; 
wire           l2c_data_clk_bank_1;           
wire           l2c_data_clk_bank_1_before_occ; 
wire           l2c_data_ram_clk_en_bank_0;    
wire           l2c_data_ram_clk_en_bank_1;    
wire           l2c_tag_clk_bank_0;            
wire           l2c_tag_clk_bank_0_before_occ; 
wire           l2c_tag_clk_bank_1;            
wire           l2c_tag_clk_bank_1_before_occ; 
wire           l2c_tag_ram_clk_en_bank_0;     
wire           l2c_tag_ram_clk_en_bank_1;     
wire           pad_had_jtg_tclk;              
wire    [2:0]  pad_l2c_data_mbist_clk_ratio;  
wire    [2:0]  pad_l2c_tag_mbist_clk_ratio;   
wire           pad_yy_dft_clk_rst_b;          
wire           pad_yy_icg_scan_en;            
wire           pad_yy_mbist_mode;             
wire           pad_yy_scan_mode;              
wire           phl_rst_b;                     
wire           pll_cpu_clk;                   
wire           tag_ram_bist_cnt_idle;         
wire           tag_ram_clk_en_bank_0;         
wire           tag_ram_clk_en_bank_1;         







assign forever_cpuclk = pll_cpu_clk;




assign forever_core0_clk = forever_cpuclk;

assign forever_core1_clk = forever_cpuclk;







assign forever_jtgclk = pad_had_jtg_tclk;







always@(posedge pll_cpu_clk or negedge phl_rst_b)
begin
  if (!phl_rst_b)
    peripheral_clk_en <= 1'b0;
  else
    peripheral_clk_en <= ~peripheral_clk_en;
end

always@(posedge pll_cpu_clk)
begin
  apb_clk_en_f <= peripheral_clk_en;
end

assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;



BUFGCE apb_clk_buf
(.O   (apb_clk),
 .I   (pll_cpu_clk),
 .CE  (apb_clk_en_f)
);























always@(posedge forever_cpuclk)
begin
  axim_clk_en_f <= axim_clk_en;
end





assign bist_clk_en = pad_yy_mbist_mode | pad_yy_scan_mode;

gated_clk_cell  x_data_bist_gated_clk (
  .clk_in             (pll_cpu_clk       ),
  .clk_out            (bist_clk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (bist_clk_en       ),
  .module_en          (1'b0              ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b) 
begin
  if (!pad_yy_dft_clk_rst_b)
    l2c_data_ram_bist_clk_ratio[2:0] <= 3'b0;
  else if (bist_clk_en) begin
    if (data_ram_bist_cnt_idle)
      l2c_data_ram_bist_clk_ratio[2:0] <= pad_l2c_data_mbist_clk_ratio[2:0];
    else
      l2c_data_ram_bist_clk_ratio[2:0] <= l2c_data_ram_bist_clk_ratio[2:0] - 3'b001;
  end
end

assign data_ram_bist_cnt_idle = l2c_data_ram_bist_clk_ratio[2:0] == 3'b000;

assign data_ram_clk_en_bank_0 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_0;
assign data_ram_clk_en_bank_1 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_1;






BUFGCE data_bank0_clk_buf
(.O   (l2c_data_clk_bank_0_before_occ),
 .I   (pll_cpu_clk),
 .CE  (data_ram_clk_en_bank_0)
);

BUFGCE data_bank1_clk_buf
(.O   (l2c_data_clk_bank_1_before_occ),
 .I   (pll_cpu_clk),
 .CE  (data_ram_clk_en_bank_1)
);





















assign l2c_data_clk_bank_0 = l2c_data_clk_bank_0_before_occ;
assign l2c_data_clk_bank_1 = l2c_data_clk_bank_1_before_occ;






         



always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b)
begin
  if (!pad_yy_dft_clk_rst_b)
    l2c_tag_ram_bist_clk_ratio[2:0] <= 3'b0;
  else if (bist_clk_en) begin
    if (tag_ram_bist_cnt_idle)
      l2c_tag_ram_bist_clk_ratio[2:0] <= pad_l2c_tag_mbist_clk_ratio[2:0];
    else
      l2c_tag_ram_bist_clk_ratio[2:0] <= l2c_tag_ram_bist_clk_ratio[2:0] - 3'b001;
  end
end

assign tag_ram_bist_cnt_idle = l2c_tag_ram_bist_clk_ratio[2:0] == 3'b000;

assign tag_ram_clk_en_bank_0 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_0;
assign tag_ram_clk_en_bank_1 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_1;





BUFGCE tag_bank0_clk_buf
(.O   (l2c_tag_clk_bank_0_before_occ),
 .I   (pll_cpu_clk),
 .CE  (tag_ram_clk_en_bank_0)
);

BUFGCE tag_bank1_clk_buf
(.O   (l2c_tag_clk_bank_1_before_occ),
 .I   (pll_cpu_clk),
 .CE  (tag_ram_clk_en_bank_1)
);





















assign l2c_tag_clk_bank_0 = l2c_tag_clk_bank_0_before_occ;
assign l2c_tag_clk_bank_1 = l2c_tag_clk_bank_1_before_occ;








endmodule