data/full_repos/permissive/504478691/clock/display.v
1: b"%Error: data/full_repos/permissive/504478691/clock/display.v:4: Cannot find file containing module: 'clock'\nclock clk_inst(.CLK(clk), .rst(rst), .pause(pause), .oData(Data), .dp(dp_input));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/clock,data/full_repos/permissive/504478691/clock\n             data/full_repos/permissive/504478691/clock,data/full_repos/permissive/504478691/clock.v\n             data/full_repos/permissive/504478691/clock,data/full_repos/permissive/504478691/clock.sv\n             clock\n             clock.v\n             clock.sv\n             obj_dir/clock\n             obj_dir/clock.v\n             obj_dir/clock.sv\n%Error: data/full_repos/permissive/504478691/clock/display.v:9: Cannot find file containing module: 'divider800Hz'\ndivider800Hz div_inst(.I_CLK(clk), .O_CLK(O_CLK));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504478691/clock/display.v:10: Cannot find file containing module: 'display7'\ndisplay7 dis_inst(.iData(iData), .oData(cathode));\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module display(input clk, input rst, input pause, output reg [7:0] anode, output [6:0] cathode, output reg dp);
wire [31:0] Data;
wire [7:0] dp_input;
clock clk_inst(.CLK(clk), .rst(rst), .pause(pause), .oData(Data), .dp(dp_input));

reg [2:0] i_a = 0;
reg [3:0] iData;
wire O_CLK;
divider800Hz div_inst(.I_CLK(clk), .O_CLK(O_CLK));
display7 dis_inst(.iData(iData), .oData(cathode));
always @(posedge O_CLK)
begin
    iData = {Data[i_a * 4 + 3], Data[i_a * 4 + 2], Data[i_a * 4 + 1], Data[i_a * 4]};
    dp = dp_input[i_a];
    anode = 8'b11111111;
    anode[i_a] = 0;
    i_a = i_a + 1;
end
endmodule
module display(input clk, input rst, input pause, output reg [7:0] anode, output [6:0] cathode, output reg dp);

wire [31:0] Data;
wire [7:0] dp_input;
clock clk_inst(.CLK(clk), .rst(rst), .pause(pause), .oData(Data), .dp(dp_input));

reg [2:0] i_a = 0;
reg [3:0] iData;
wire O_CLK;
divider800Hz div_inst(.I_CLK(clk), .O_CLK(O_CLK));
display7 dis_inst(.iData(iData), .oData(cathode));
always @(posedge O_CLK)
begin
    iData = {Data[i_a * 4 + 3], Data[i_a * 4 + 2], Data[i_a * 4 + 1], Data[i_a * 4]};
    dp = dp_input[i_a];
    anode = 8'b11111111;
    anode[i_a] = 0;
    i_a = i_a + 1;
end
endmodule