data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:78: Cannot find file containing module: \'fflopx\'\nfflopx #(16) ib3cnt (clk,rst,ob3cnt,b3cnt);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s SEL generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator XOR expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator XOR expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator XOR expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:90: Operator XOR expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                                                                  : ... In instance db_b3check8\n                         ivld & cfgv5mod ? (v5pos ? 2\'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  \n                                                                                                     ^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:92: Cannot find file containing module: \'fflopx\'\nfflopx #(8) ib3sum (clk,rst,ob3sum,b3sum);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:96: Cannot find file containing module: \'fflopx\'\nfflopx #(8) ib3pre (clk,rst,ob3pre,b3pre);\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:100: Operator EQ expects 16 bits on the RHS, but RHS\'s VARREF \'cfgb3\' generates 13 bits.\n                                                                                                                                   : ... In instance db_b3check8\nassign          b3pos = ivld & (b3cnt == cfgb3);\n                                      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:115: Cannot find file containing module: \'af6ces48rtl_prbscheck\'\naf6ces48rtl_prbscheck prbs15mon (.ivld(ivld),.idat(idat),.iprbs(oprbs),.oprbs(iprbs),.oerr(prbserr),.osyn(prbssyn));\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:118: Cannot find file containing module: \'fflopx\'\nfflopx #(1) b3prbserr (clk,rst,(cfgcep ? ob3err : ivld & prbserr),ob3prbserr);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/db_b3check8.v:119: Cannot find file containing module: \'fflopx\'\nfflopx #(1) ppprbssyn (clk,rst,(cfgcep ? ij1 & ivld : ivld & prbssyn),oprbssyn);\n^~~~~~\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module db_b3check8  
    (clk,
     rst,

     cfgcep,
     cfgvc3,
     cfgb3,
     
     ivld,
     idat,
     ij1,
     
     ob3prbserr,
     oprbssyn
     );



input           clk,
                rst;

input           cfgcep;
input           cfgvc3;
input [12:0]    cfgb3;
    
input           ivld;
input [7:0]     idat;
input           ij1;

output          ob3prbserr;
output          oprbssyn;






parameter       PKMOD = 0;












(* keep = "true" *) reg [15:0]  b3max = 16'd783;
always @ (posedge clk)
    begin
    b3max <= (cfgb3 == 13'd86) ? 16'd765 :
             (cfgb3 == 13'd88) ? 16'd783 :
             (cfgb3 == 13'd262) ? 16'd2349 : 
             (cfgb3 == 13'd1045) ? 16'd9396 : 16'd37584;
    end

wire [15:0]     ob3cnt,b3cnt;
assign          ob3cnt = ivld & ij1 ? 16'd2 :

                         ivld & (b3cnt >= b3max) ? 16'd1 :
                         ivld                    ? b3cnt + 1'b1 : b3cnt;
fflopx #(16) ib3cnt (clk,rst,ob3cnt,b3cnt);


wire            j1pos,v5pos;
assign          j1pos = ij1 | ((b3cnt == 16'd1) & (PKMOD == 1));
assign          v5pos = j1pos;

wire            cfgv5mod = !cfgvc3;
wire            cfgb3mod = cfgvc3;

wire [7:0]      ob3sum,b3sum;
assign          ob3sum = ivld & cfgb3mod ? (j1pos ? idat : b3sum^idat) : 
                         ivld & cfgv5mod ? (v5pos ? 2'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  
                                           b3sum;
fflopx #(8) ib3sum (clk,rst,ob3sum,b3sum);

wire [7:0]      ob3pre,b3pre;
assign          ob3pre = ivld & j1pos ? b3sum : b3pre;
fflopx #(8) ib3pre (clk,rst,ob3pre,b3pre);

wire            b3pos;

assign          b3pos = ivld & (b3cnt == cfgb3);


wire            ob3err;
assign          ob3err = cfgb3mod ? b3pos & (|(b3pre^idat)) : ivld & v5pos & (b3sum[1:0]!=idat[7:6]);


wire [14:0]     iprbs;
reg [14:0]      oprbs;
always @ (posedge clk or posedge rst)
    begin
    if (rst)        oprbs <= 15'h7FFF;
    else if (ivld)  oprbs <= iprbs;
    end
wire            prbserr,prbssyn;
af6ces48rtl_prbscheck prbs15mon (.ivld(ivld),.idat(idat),.iprbs(oprbs),.oprbs(iprbs),.oerr(prbserr),.osyn(prbssyn));


fflopx #(1) b3prbserr (clk,rst,(cfgcep ? ob3err : ivld & prbserr),ob3prbserr);
fflopx #(1) ppprbssyn (clk,rst,(cfgcep ? ij1 & ivld : ivld & prbssyn),oprbssyn);

endmodule
module db_b3check8  
    (clk,
     rst,

     cfgcep,
     cfgvc3,
     cfgb3,
     
     ivld,
     idat,
     ij1,
     
     ob3prbserr,
     oprbssyn
     );




input           clk,
                rst;

input           cfgcep;
input           cfgvc3;
input [12:0]    cfgb3;
    
input           ivld;
input [7:0]     idat;
input           ij1;

output          ob3prbserr;
output          oprbssyn;






parameter       PKMOD = 0;












(* keep = "true" *) reg [15:0]  b3max = 16'd783;
always @ (posedge clk)
    begin
    b3max <= (cfgb3 == 13'd86) ? 16'd765 :
             (cfgb3 == 13'd88) ? 16'd783 :
             (cfgb3 == 13'd262) ? 16'd2349 : 
             (cfgb3 == 13'd1045) ? 16'd9396 : 16'd37584;
    end

wire [15:0]     ob3cnt,b3cnt;
assign          ob3cnt = ivld & ij1 ? 16'd2 :

                         ivld & (b3cnt >= b3max) ? 16'd1 :
                         ivld                    ? b3cnt + 1'b1 : b3cnt;
fflopx #(16) ib3cnt (clk,rst,ob3cnt,b3cnt);


wire            j1pos,v5pos;
assign          j1pos = ij1 | ((b3cnt == 16'd1) & (PKMOD == 1));
assign          v5pos = j1pos;

wire            cfgv5mod = !cfgvc3;
wire            cfgb3mod = cfgvc3;

wire [7:0]      ob3sum,b3sum;
assign          ob3sum = ivld & cfgb3mod ? (j1pos ? idat : b3sum^idat) : 
                         ivld & cfgv5mod ? (v5pos ? 2'b00 : b3sum[1:0])^idat[7:6]^idat[5:4]^idat[3:2]^idat[1:0] :  
                                           b3sum;
fflopx #(8) ib3sum (clk,rst,ob3sum,b3sum);

wire [7:0]      ob3pre,b3pre;
assign          ob3pre = ivld & j1pos ? b3sum : b3pre;
fflopx #(8) ib3pre (clk,rst,ob3pre,b3pre);

wire            b3pos;

assign          b3pos = ivld & (b3cnt == cfgb3);


wire            ob3err;
assign          ob3err = cfgb3mod ? b3pos & (|(b3pre^idat)) : ivld & v5pos & (b3sum[1:0]!=idat[7:6]);


wire [14:0]     iprbs;
reg [14:0]      oprbs;
always @ (posedge clk or posedge rst)
    begin
    if (rst)        oprbs <= 15'h7FFF;
    else if (ivld)  oprbs <= iprbs;
    end
wire            prbserr,prbssyn;
af6ces48rtl_prbscheck prbs15mon (.ivld(ivld),.idat(idat),.iprbs(oprbs),.oprbs(iprbs),.oerr(prbserr),.osyn(prbssyn));


fflopx #(1) b3prbserr (clk,rst,(cfgcep ? ob3err : ivld & prbserr),ob3prbserr);
fflopx #(1) ppprbssyn (clk,rst,(cfgcep ? ij1 & ivld : ivld & prbssyn),oprbssyn);

endmodule