data/full_repos/permissive/513306128/ECEN248/half_adder.v
data/verilator_xmls/bd222cca-f15c-4fb0-9288-6c7ac1493cf2.xml
module half_adder(S,Cout,A,B);

    input wire A,B;

    wire andAB, axorb;

    output wire S, Cout;
    
    assign Cout = A&B;
    assign S = A^B;
endmodule
module half_adder(S,Cout,A,B);


    input wire A,B;

    wire andAB, axorb;

    output wire S, Cout;
    
    assign Cout = A&B;
    assign S = A^B;
endmodule