data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v
1: b"%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:52: Define or directive not defined: '`MPRJ_IO_PADS'\n  input  [`MPRJ_IO_PADS-1:0] io_in,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:53: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_out,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:54: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_oeb,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:62: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_in;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:63: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_out;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_oeb;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:98: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:116: syntax error, unexpected ||, expecting ')' or ',' or or\n  always @(la_data_in || la_oenb || la_sel || o_nonce || o_block_header || o_target) begin\n                      ^~\n%Error: Exiting due to 8 error(s)\n"
module btc_miner_top #(
  parameter BITS = 32
)(
`ifdef USE_POWER_PINS
  inout vccd1,
  inout vssd1,
`endif


  input wb_clk_i,
  input wb_rst_i,
  input wbs_stb_i,
  input wbs_cyc_i,
  input wbs_we_i,
  input [3:0] wbs_sel_i,
  input [31:0] wbs_dat_i,
  input [31:0] wbs_adr_i,
  output wbs_ack_o,
  output [31:0] wbs_dat_o,


  input  [127:0] la_data_in,
  output [127:0] la_data_out,
  input  [127:0] la_oenb,


  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,


  output [2:0] irq
);
  wire clk;
  wire rst;

  wire [`MPRJ_IO_PADS-1:0] io_in;
  wire [`MPRJ_IO_PADS-1:0] io_out;
  wire [`MPRJ_IO_PADS-1:0] io_oeb;


  wire [31:0] rdata; 
  wire [31:0] wdata;

  wire valid;
  wire [3:0] wstrb;


  wire [31:0] la_write0;
  wire [31:0] la_write1;
  wire [31:0] la_write2;
  wire [31:0] la_write3;


  wire [BITS-1:0] o_nonce;
  wire o_idle;
  wire [639:0] o_block_header;
  wire [255:0] o_target;
  reg [127:0] la_data_out;


  wire [5:0] la_sel;
  assign la_sel = la_data_in[127:122];


  assign valid = wbs_cyc_i && wbs_stb_i; 
  assign wstrb = wbs_sel_i & {4{wbs_we_i}};
  assign wbs_dat_o = rdata;
  assign wdata = wbs_dat_i;


  assign io_out = o_nonce;
  assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


  assign irq = 3'b000;



  assign la_write0 = ~la_oenb[31:0] & ~{BITS{valid}};
  assign la_write1 = ~la_oenb[63:32] & ~{BITS{valid}};
  assign la_write2 = ~la_oenb[95:64] & ~{BITS{valid}};
  assign la_write3 = ~la_oenb[127:96] & ~{BITS{valid}};


  assign clk = (~la_oenb[106]) ? la_data_in[106] : wb_clk_i;
  assign rst = (~la_oenb[107]) ? la_data_in[107] : wb_rst_i;



  always @(la_data_in || la_oenb || la_sel || o_nonce || o_block_header || o_target) begin
    case (la_sel)
      6'b000000:
        la_data_out[95:0] <= {{(95-BITS){1'b0}}, o_nonce};
      6'b000001:
        la_data_out[95:0] <= o_block_header[95:0];
      6'b000010:
        la_data_out[95:0] <= o_block_header[191:96];
      6'b000011:
        la_data_out[95:0] <= o_block_header[287:192];

      default:
        begin

        end
    endcase
  end


  miner_ctrl #(
    .BITS(BITS)
  ) miner_ctrl(
    .clk(clk),
    .rst(rst),
    .valid(valid),
    .wb_we(wbs_we_i),
    .wdata(wbs_dat_i),
    .la_write0(la_write0),
    .la_write3(la_write3),
    .la_input0(la_data_in[31:0]),
    .la_input3(la_data_in[127:96]),
    .ready(wbs_ack_o),
    .rdata(rdata),
    .block_header(o_block_header),
    .target(o_target),
    .nonce(o_nonce),
    .idle(o_idle)
  );

endmodule
module btc_miner_top #(
  parameter BITS = 32
)(
`ifdef USE_POWER_PINS
  inout vccd1,
  inout vssd1,
`endif


  input wb_clk_i,
  input wb_rst_i,
  input wbs_stb_i,
  input wbs_cyc_i,
  input wbs_we_i,
  input [3:0] wbs_sel_i,
  input [31:0] wbs_dat_i,
  input [31:0] wbs_adr_i,
  output wbs_ack_o,
  output [31:0] wbs_dat_o,


  input  [127:0] la_data_in,
  output [127:0] la_data_out,
  input  [127:0] la_oenb,


  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,


  output [2:0] irq
);

  wire clk;
  wire rst;

  wire [`MPRJ_IO_PADS-1:0] io_in;
  wire [`MPRJ_IO_PADS-1:0] io_out;
  wire [`MPRJ_IO_PADS-1:0] io_oeb;


  wire [31:0] rdata; 
  wire [31:0] wdata;

  wire valid;
  wire [3:0] wstrb;


  wire [31:0] la_write0;
  wire [31:0] la_write1;
  wire [31:0] la_write2;
  wire [31:0] la_write3;


  wire [BITS-1:0] o_nonce;
  wire o_idle;
  wire [639:0] o_block_header;
  wire [255:0] o_target;
  reg [127:0] la_data_out;


  wire [5:0] la_sel;
  assign la_sel = la_data_in[127:122];


  assign valid = wbs_cyc_i && wbs_stb_i; 
  assign wstrb = wbs_sel_i & {4{wbs_we_i}};
  assign wbs_dat_o = rdata;
  assign wdata = wbs_dat_i;


  assign io_out = o_nonce;
  assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


  assign irq = 3'b000;



  assign la_write0 = ~la_oenb[31:0] & ~{BITS{valid}};
  assign la_write1 = ~la_oenb[63:32] & ~{BITS{valid}};
  assign la_write2 = ~la_oenb[95:64] & ~{BITS{valid}};
  assign la_write3 = ~la_oenb[127:96] & ~{BITS{valid}};


  assign clk = (~la_oenb[106]) ? la_data_in[106] : wb_clk_i;
  assign rst = (~la_oenb[107]) ? la_data_in[107] : wb_rst_i;



  always @(la_data_in || la_oenb || la_sel || o_nonce || o_block_header || o_target) begin
    case (la_sel)
      6'b000000:
        la_data_out[95:0] <= {{(95-BITS){1'b0}}, o_nonce};
      6'b000001:
        la_data_out[95:0] <= o_block_header[95:0];
      6'b000010:
        la_data_out[95:0] <= o_block_header[191:96];
      6'b000011:
        la_data_out[95:0] <= o_block_header[287:192];

      default:
        begin

        end
    endcase
  end


  miner_ctrl #(
    .BITS(BITS)
  ) miner_ctrl(
    .clk(clk),
    .rst(rst),
    .valid(valid),
    .wb_we(wbs_we_i),
    .wdata(wbs_dat_i),
    .la_write0(la_write0),
    .la_write3(la_write3),
    .la_input0(la_data_in[31:0]),
    .la_input3(la_data_in[127:96]),
    .ready(wbs_ack_o),
    .rdata(rdata),
    .block_header(o_block_header),
    .target(o_target),
    .nonce(o_nonce),
    .idle(o_idle)
  );

endmodule