data/full_repos/permissive/412289941/delvb.v
data/verilator_xmls/05ec5e02-3bad-4974-a1ea-fdefe2fb4929.xml
module delvb(rst_n, indata, outdata,clk);

input rst_n,clk;
input [1:0]indata;
output outdata;
reg [3:0]buffer;
reg bufferdata;
reg counterv;

always@(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
    buffer[3]<=0;
    buffer[2]<=0;
    buffer[1]<=0;
    buffer[0]<=0;
end
else begin
    buffer[3]<=buffer[2];
    buffer[2]<=buffer[1];
    buffer[1]<=buffer[0];
    buffer[0]<=bufferdata;
end
end


always @(posedge clk or negedge rst_n) begin

    if(!rst_n) bufferdata <= 0;
    else begin
        if(indata==2'b01) begin

            counterv <= 0;
            bufferdata<=1;
        end
        else if(indata==2'b00) begin

            counterv <= 0;
            bufferdata<=0;
        end
        else if(indata==2'b11) begin

            counterv <= 1;
            bufferdata<=0;
        end
    end
end

assign outdata = (counterv == 1)  ? 0 : buffer[2];

endmodule
module delvb(rst_n, indata, outdata,clk);


input rst_n,clk;
input [1:0]indata;
output outdata;
reg [3:0]buffer;
reg bufferdata;
reg counterv;

always@(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
    buffer[3]<=0;
    buffer[2]<=0;
    buffer[1]<=0;
    buffer[0]<=0;
end
else begin
    buffer[3]<=buffer[2];
    buffer[2]<=buffer[1];
    buffer[1]<=buffer[0];
    buffer[0]<=bufferdata;
end
end


always @(posedge clk or negedge rst_n) begin

    if(!rst_n) bufferdata <= 0;
    else begin
        if(indata==2'b01) begin

            counterv <= 0;
            bufferdata<=1;
        end
        else if(indata==2'b00) begin

            counterv <= 0;
            bufferdata<=0;
        end
        else if(indata==2'b11) begin

            counterv <= 1;
            bufferdata<=0;
        end
    end
end

assign outdata = (counterv == 1)  ? 0 : buffer[2];

endmodule