data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v
1: b'%Error: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:20: Cannot find file containing module: \'multi_seven_seg_6\'\n  multi_seven_seg_6 seg_display (\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469312749/FINAL1/work/verilog,data/full_repos/permissive/469312749/multi_seven_seg_6\n             data/full_repos/permissive/469312749/FINAL1/work/verilog,data/full_repos/permissive/469312749/multi_seven_seg_6.v\n             data/full_repos/permissive/469312749/FINAL1/work/verilog,data/full_repos/permissive/469312749/multi_seven_seg_6.sv\n             multi_seven_seg_6\n             multi_seven_seg_6.v\n             multi_seven_seg_6.sv\n             obj_dir/multi_seven_seg_6\n             obj_dir/multi_seven_seg_6.v\n             obj_dir/multi_seven_seg_6.sv\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:29: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    seg_tolight = 1\'h0;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:30: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    dig_tolight = 1\'h0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h3\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h4\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h5\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h6\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h7\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h8\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h9\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'ha\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'hb\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'hc\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'hd\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'he\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'hf\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h10\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h11\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_split_out_3.v:33: Operator CASE expects 16 bits on the Case Item, but Case Item\'s CONST \'5\'h12\' generates 5 bits.\n                                                                                                   : ... In instance seven_seg_split_out_3\n    case (split_chosen)\n    ^~~~\n%Error: Exiting due to 1 error(s), 21 warning(s)\n'
module seven_seg_split_out_3 (
    input clk,
    input rst,
    input [15:0] split_chosen,
    output reg [6:0] seg_tolight,
    output reg [1:0] dig_tolight
  );
  
  
  
  wire [7-1:0] M_seg_display_seg;
  wire [2-1:0] M_seg_display_sel;
  reg [10-1:0] M_seg_display_values;
  multi_seven_seg_6 seg_display (
    .clk(clk),
    .rst(rst),
    .values(M_seg_display_values),
    .seg(M_seg_display_seg),
    .sel(M_seg_display_sel)
  );
  
  always @* begin
    seg_tolight = 1'h0;
    dig_tolight = 1'h0;
    M_seg_display_values = 10'h000;
    
    case (split_chosen)
      5'h00: begin
        M_seg_display_values = 10'h000;
      end
      5'h01: begin
        M_seg_display_values = 10'h020;
      end
      5'h02: begin
        M_seg_display_values = 10'h040;
      end
      5'h03: begin
        M_seg_display_values = 10'h060;
      end
      5'h04: begin
        M_seg_display_values = 10'h080;
      end
      5'h05: begin
        M_seg_display_values = 10'h0a0;
      end
      5'h06: begin
        M_seg_display_values = 10'h0c0;
      end
      5'h07: begin
        M_seg_display_values = 10'h0e0;
      end
      5'h08: begin
        M_seg_display_values = 10'h100;
      end
      5'h09: begin
        M_seg_display_values = 10'h120;
      end
      5'h0a: begin
        M_seg_display_values = 10'h020;
      end
      5'h0b: begin
        M_seg_display_values = 10'h021;
      end
      5'h0c: begin
        M_seg_display_values = 10'h022;
      end
      5'h0d: begin
        M_seg_display_values = 10'h023;
      end
      5'h0e: begin
        M_seg_display_values = 10'h024;
      end
      5'h0f: begin
        M_seg_display_values = 10'h025;
      end
      5'h10: begin
        M_seg_display_values = 10'h1a1;
      end
      5'h11: begin
        M_seg_display_values = 10'h1a2;
      end
      5'h12: begin
        M_seg_display_values = 10'h280;
      end
      default: begin
        M_seg_display_values = 10'h3ff;
      end
    endcase
    seg_tolight = ~M_seg_display_seg;
    dig_tolight = ~M_seg_display_sel;
  end
endmodule
module seven_seg_split_out_3 (
    input clk,
    input rst,
    input [15:0] split_chosen,
    output reg [6:0] seg_tolight,
    output reg [1:0] dig_tolight
  );

  
  
  
  wire [7-1:0] M_seg_display_seg;
  wire [2-1:0] M_seg_display_sel;
  reg [10-1:0] M_seg_display_values;
  multi_seven_seg_6 seg_display (
    .clk(clk),
    .rst(rst),
    .values(M_seg_display_values),
    .seg(M_seg_display_seg),
    .sel(M_seg_display_sel)
  );
  
  always @* begin
    seg_tolight = 1'h0;
    dig_tolight = 1'h0;
    M_seg_display_values = 10'h000;
    
    case (split_chosen)
      5'h00: begin
        M_seg_display_values = 10'h000;
      end
      5'h01: begin
        M_seg_display_values = 10'h020;
      end
      5'h02: begin
        M_seg_display_values = 10'h040;
      end
      5'h03: begin
        M_seg_display_values = 10'h060;
      end
      5'h04: begin
        M_seg_display_values = 10'h080;
      end
      5'h05: begin
        M_seg_display_values = 10'h0a0;
      end
      5'h06: begin
        M_seg_display_values = 10'h0c0;
      end
      5'h07: begin
        M_seg_display_values = 10'h0e0;
      end
      5'h08: begin
        M_seg_display_values = 10'h100;
      end
      5'h09: begin
        M_seg_display_values = 10'h120;
      end
      5'h0a: begin
        M_seg_display_values = 10'h020;
      end
      5'h0b: begin
        M_seg_display_values = 10'h021;
      end
      5'h0c: begin
        M_seg_display_values = 10'h022;
      end
      5'h0d: begin
        M_seg_display_values = 10'h023;
      end
      5'h0e: begin
        M_seg_display_values = 10'h024;
      end
      5'h0f: begin
        M_seg_display_values = 10'h025;
      end
      5'h10: begin
        M_seg_display_values = 10'h1a1;
      end
      5'h11: begin
        M_seg_display_values = 10'h1a2;
      end
      5'h12: begin
        M_seg_display_values = 10'h280;
      end
      default: begin
        M_seg_display_values = 10'h3ff;
      end
    endcase
    seg_tolight = ~M_seg_display_seg;
    dig_tolight = ~M_seg_display_sel;
  end
endmodule