data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_addbit.v
data/verilator_xmls/dc6f1128-b6c0-4332-816c-4a8f614d2145.xml
module addbit (
a      ,
b      ,
ci     ,
sum    ,
co
);

input a;
input b;
input ci;

output sum;
output co;

wire  a;
wire  b;
wire  ci;
wire  sum;
wire  co;

assign {co,sum} = a + b + ci;

endmodule
module addbit (
a      ,
b      ,
ci     ,
sum    ,
co
);


input a;
input b;
input ci;

output sum;
output co;

wire  a;
wire  b;
wire  ci;
wire  sum;
wire  co;

assign {co,sum} = a + b + ci;

endmodule