data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v
1: b'%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:22: Cannot find include file: ../toysram.vh\n`include "../toysram.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.v\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.sv\n             ../toysram.vh\n             ../toysram.vh.v\n             ../toysram.vh.sv\n             obj_dir/../toysram.vh\n             obj_dir/../toysram.vh.v\n             obj_dir/../toysram.vh.sv\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:77: Define or directive not defined: \'`UNIT_MASK\'\n   assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);\n                                                                       ^\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:77: Define or directive not defined: \'`CTL_ADDR\'\n   assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);\n                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:78: Define or directive not defined: \'`UNIT_MASK\'\n   assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);\n                                                                       ^\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/cfg.v:78: Define or directive not defined: \'`RA0_ADDR\'\n   assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);\n                                                                            ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module cfg (
`ifdef USE_POWER_PINS
   inout vccd1,
   inout vssd1,
`endif

   input          clk,
   input          rst,
   input          wb_cmd_val,
   input  [31:0]  wb_cmd_adr,
   input          wb_cmd_we,
   input  [3:0]   wb_cmd_sel,
   input  [31:0]  wb_cmd_dat,
   output         wb_rd_ack,
   output [31:0]  wb_rd_dat,

   output [31:0]  cmd_adr,
   output         cmd_we,
   output [3:0]   cmd_sel,
   output [31:0]  cmd_dat,

   output         ctl_cmd_val,
   output         ra0_cmd_val,
   input          ctl_rd_ack,
   input  [31:0]  ctl_rd_dat

);

   reg            ack_q;
   wire           ack_d;


   always @(posedge clk) begin
      if (rst) begin
         ack_q <= 1'b0;
      end else begin
         ack_q <= ack_d;
      end
   end


   assign cmd_adr = wb_cmd_adr;
   assign cmd_we = wb_cmd_we;
   assign cmd_sel = wb_cmd_sel;
   assign cmd_dat = wb_cmd_dat;



   assign ack_d = ctl_rd_ack;

   assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);
   assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);

   assign wb_rd_ack = ctl_rd_ack;
   assign wb_rd_dat = ctl_rd_dat;

endmodule
module cfg (
`ifdef USE_POWER_PINS
   inout vccd1,
   inout vssd1,
`endif

   input          clk,
   input          rst,
   input          wb_cmd_val,
   input  [31:0]  wb_cmd_adr,
   input          wb_cmd_we,
   input  [3:0]   wb_cmd_sel,
   input  [31:0]  wb_cmd_dat,
   output         wb_rd_ack,
   output [31:0]  wb_rd_dat,

   output [31:0]  cmd_adr,
   output         cmd_we,
   output [3:0]   cmd_sel,
   output [31:0]  cmd_dat,

   output         ctl_cmd_val,
   output         ra0_cmd_val,
   input          ctl_rd_ack,
   input  [31:0]  ctl_rd_dat

);


   reg            ack_q;
   wire           ack_d;


   always @(posedge clk) begin
      if (rst) begin
         ack_q <= 1'b0;
      end else begin
         ack_q <= ack_d;
      end
   end


   assign cmd_adr = wb_cmd_adr;
   assign cmd_we = wb_cmd_we;
   assign cmd_sel = wb_cmd_sel;
   assign cmd_dat = wb_cmd_dat;



   assign ack_d = ctl_rd_ack;

   assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);
   assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);

   assign wb_rd_ack = ctl_rd_ack;
   assign wb_rd_dat = ctl_rd_dat;

endmodule