data/full_repos/permissive/43856783/Integrador/rsa.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/Integrador/rsa.v:34: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 33 bits.\n                                                                       : ... In instance rsa\n    out[31:0] <= in >> 1;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rsa(
    input clk,
	 input en,
    input shift,
    input [32:0] in,
    output reg [32:0] out
    );
	 
	 initial out <= 0;
	 
	 always @ (negedge clk) begin
		if(en) begin
			if(shift) begin
				out[31:0] <= in >> 1;
				out[32] <= in[32];
			end else out <= in;
		end else out <= out;
	 end
	 
endmodule
module rsa(
    input clk,
	 input en,
    input shift,
    input [32:0] in,
    output reg [32:0] out
    );

	 
	 initial out <= 0;
	 
	 always @ (negedge clk) begin
		if(en) begin
			if(shift) begin
				out[31:0] <= in >> 1;
				out[32] <= in[32];
			end else out <= in;
		end else out <= out;
	 end
	 
endmodule