data/full_repos/permissive/435885222/sources/pc_reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435885222/sources/pc_reg.v:24: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                                        : ... In instance pc_reg\n        else pc<=pc+4\'h4; \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pc_reg(
    input clk,
    input rst,
    input branch_flag_in,
    input [31:0] branch_target_address_in,
    output reg[31:0] pc,
    output reg ce
    );
    always @(posedge clk)begin
        if(rst==1'b1) ce<=1'b0;
        else ce<=1'b1;
    end
    always @(posedge clk)begin
        if(ce==1'b0) pc<=32'h00000000;
        else if(branch_flag_in==1'b1) pc<=branch_target_address_in;
        else pc<=pc+4'h4;
    end
endmodule
module pc_reg(
    input clk,
    input rst,
    input branch_flag_in,
    input [31:0] branch_target_address_in,
    output reg[31:0] pc,
    output reg ce
    );

    always @(posedge clk)begin
        if(rst==1'b1) ce<=1'b0;
        else ce<=1'b1;
    end
    always @(posedge clk)begin
        if(ce==1'b0) pc<=32'h00000000;
        else if(branch_flag_in==1'b1) pc<=branch_target_address_in;
        else pc<=pc+4'h4;
    end
endmodule