data/full_repos/permissive/458737381/src/verilog-parser/tests/loops.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/loops.v:13: Unsupported: wait statements\n    wait (10);\n    ^~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_loops;
    
integer a = 0;

initial begin

    while(a < 10) begin
        a = a + 1;
    end 

    wait (10);

    forever begin
        a = a - 1;
        if( a < 0) $finish;
    end

end

endmodule
module tb_loops;

    
integer a = 0;

initial begin

    while(a < 10) begin
        a = a + 1;
    end 

    wait (10);

    forever begin
        a = a - 1;
        if( a < 0) $finish;
    end

end

endmodule