data/full_repos/permissive/458935738/common/pwm.v
data/verilator_xmls/1e21eecd-72a7-4267-99c4-5ae94c01cd76.xml
module pwm (
    input wire clk,
    input enable,
    input [15:0] timeon,
    output reg PWM
    );
    

    reg [15:0] timerPWM;
    

    always @(posedge clk)
    begin
        if (enable)
        begin
            timerPWM <= timerPWM + 1'b1;
            if (timerPWM == 16'd16000)
            begin
                timerPWM <= 0;
                PWM <= 1'b1;
            end
            
            else if (timerPWM > timeon)
                PWM <= 1'b0;
        end
        
        else
        begin
            timerPWM <=0;
            PWM <= 0;
        end
    end
endmodule
module pwm (
    input wire clk,
    input enable,
    input [15:0] timeon,
    output reg PWM
    );

    

    reg [15:0] timerPWM;
    

    always @(posedge clk)
    begin
        if (enable)
        begin
            timerPWM <= timerPWM + 1'b1;
            if (timerPWM == 16'd16000)
            begin
                timerPWM <= 0;
                PWM <= 1'b1;
            end
            
            else if (timerPWM > timeon)
                PWM <= 1'b0;
        end
        
        else
        begin
            timerPWM <=0;
            PWM <= 0;
        end
    end
endmodule