data/full_repos/permissive/507968444/src/alu/not_word.v
data/verilator_xmls/75fb6fe9-27aa-4119-aa42-34aaefdfdec1.xml
module not_word (	input wire [31:0] a,
			output wire [31:0] not_a);

	genvar i;

	generate
		for (i = 0; i < 32; i = i+1) begin
			not u(not_a[i], a[i]);
		end
	endgenerate

endmodule
module not_word (	input wire [31:0] a,
			output wire [31:0] not_a);


	genvar i;

	generate
		for (i = 0; i < 32; i = i+1) begin
			not u(not_a[i], a[i]);
		end
	endgenerate

endmodule