data/full_repos/permissive/465239880/RTL/D_FF.v
data/verilator_xmls/caf71d5b-688f-43ad-9846-a9944a76b5dd.xml
module D_FF(
    input i_clk,
    input d_in,
    output reg Q 

    );

always @ (posedge i_clk)
     begin
	   Q<= d_in ;

		 end

endmodule
module D_FF(
    input i_clk,
    input d_in,
    output reg Q 

    );


always @ (posedge i_clk)
     begin
	   Q<= d_in ;

		 end

endmodule