data/full_repos/permissive/434886680/src/spi.v
data/verilator_xmls/72faa26d-4cc5-4120-ba24-00ddf2a64da4.xml
module spi
  (
   input  wire        clk,
   input  wire        xres,
   input  wire        ss,
   input  wire        sclk,
   output wire        miso,
   input  wire [11:0] adc_data,
   output wire        adc_soc
   );
  
  reg [2:0] ss_dly;

  wire ss_fall = (ss_dly[2] & ~ss_dly[1]);

  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          ss_dly <= 3'b0;
        end
      else
        begin
          ss_dly <= {ss_dly[1:0], ss};
        end
    end

  reg [2:0] sclk_dly;

  wire sclk_fall = (sclk_dly[2] & ~sclk_dly[1]);

  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          sclk_dly <= 3'b0;
        end
      else
        begin
          sclk_dly <= {sclk_dly[1:0], sclk};
        end
    end

  reg [3:0]  st_spi;

  assign adc_soc      = (st_spi == 4'd0 && ss_fall);
  wire   spi_load_en  = (st_spi == 4'd3 && sclk_fall);
  wire   spi_shift_en = (st_spi != 4'd3 && sclk_fall);


  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          st_spi <= 4'd0;
        end
      else if (sclk_fall)
        begin
          if (st_spi == 4'd15 || ss == 1'b1)
            begin
              st_spi <= 4'd0;
            end
          else
            begin
              st_spi <= st_spi + 1'b1;
            end          
        end
    end

  reg [11:0] obuf;
  assign miso = obuf[11];


  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          obuf <= 0;
        end
      else if (spi_load_en)
        begin
          obuf <= adc_data;
        end
      else if (spi_shift_en)
        begin
          obuf <= {obuf[10:0], 1'b0};
        end
    end

endmodule
module spi
  (
   input  wire        clk,
   input  wire        xres,
   input  wire        ss,
   input  wire        sclk,
   output wire        miso,
   input  wire [11:0] adc_data,
   output wire        adc_soc
   );

  
  reg [2:0] ss_dly;

  wire ss_fall = (ss_dly[2] & ~ss_dly[1]);

  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          ss_dly <= 3'b0;
        end
      else
        begin
          ss_dly <= {ss_dly[1:0], ss};
        end
    end

  reg [2:0] sclk_dly;

  wire sclk_fall = (sclk_dly[2] & ~sclk_dly[1]);

  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          sclk_dly <= 3'b0;
        end
      else
        begin
          sclk_dly <= {sclk_dly[1:0], sclk};
        end
    end

  reg [3:0]  st_spi;

  assign adc_soc      = (st_spi == 4'd0 && ss_fall);
  wire   spi_load_en  = (st_spi == 4'd3 && sclk_fall);
  wire   spi_shift_en = (st_spi != 4'd3 && sclk_fall);


  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          st_spi <= 4'd0;
        end
      else if (sclk_fall)
        begin
          if (st_spi == 4'd15 || ss == 1'b1)
            begin
              st_spi <= 4'd0;
            end
          else
            begin
              st_spi <= st_spi + 1'b1;
            end          
        end
    end

  reg [11:0] obuf;
  assign miso = obuf[11];


  always @(posedge clk, negedge xres)
    begin
      if (!xres)
        begin
          obuf <= 0;
        end
      else if (spi_load_en)
        begin
          obuf <= adc_data;
        end
      else if (spi_shift_en)
        begin
          obuf <= {obuf[10:0], 1'b0};
        end
    end

endmodule