data/full_repos/permissive/431682734/LabK/k2a01_3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431682734/LabK/k2a01_3.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labK;
    reg a, b, flag;
    wire notOutput, lowerInput, tmp, z;

    not my_not(notOutput, b);

    and my_and(z, a, lowerInput);
    assign lowerInput = notOutput;
    initial
    begin
    flag = $value$plusargs("a=%b", a);
    flag = $value$plusargs("b=%b", b);
    #1;
    $display("a=%b b=%b z=%b", a, b, z);
    $finish;
    end
endmodule
module labK;

    reg a, b, flag;
    wire notOutput, lowerInput, tmp, z;

    not my_not(notOutput, b);

    and my_and(z, a, lowerInput);
    assign lowerInput = notOutput;
    initial
    begin
    flag = $value$plusargs("a=%b", a);
    flag = $value$plusargs("b=%b", b);
    #1;
    $display("a=%b b=%b z=%b", a, b, z);
    $finish;
    end
endmodule