data/full_repos/permissive/43856783/j1_soc/hdl/LCD/clk_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/clk_counter.v:30: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                   : ... In instance clk_counter\n   count <= 31\'b0;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clk_counter(
    input clk,
    input en,
    input rst,
    output reg [31:0] count
    );
	 
always@(posedge clk) begin
		if(rst) begin
			count <= 31'b0;
		end
		else if (en) begin
			count = count+1;
		end
	 end

endmodule
module clk_counter(
    input clk,
    input en,
    input rst,
    output reg [31:0] count
    );

	 
always@(posedge clk) begin
		if(rst) begin
			count <= 31'b0;
		end
		else if (en) begin
			count = count+1;
		end
	 end

endmodule