data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v:33: Cannot find include file: random.v\n`include "random.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog,data/full_repos/permissive/447976230/random.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog,data/full_repos/permissive/447976230/random.v.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog,data/full_repos/permissive/447976230/random.v.sv\n             random.v\n             random.v.v\n             random.v.sv\n             obj_dir/random.v\n             obj_dir/random.v.v\n             obj_dir/random.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v:73: Unsupported: Ignoring delay on this delayed statement.\n   always #5 sys_clk_i = ~sys_clk_i;   \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v:84: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n      sys_clk_i = $random(seed);\n                  ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v:84: ../V3Ast.cpp:358: Null item passed to setOp1p\n      sys_clk_i = $random(seed);\n                ^\n'
module aemb2 ();
   parameter IWB=16;
   parameter DWB=16;

   parameter TXE = 0;
   
   parameter MUL = 1;
   parameter BSF = 1;
   parameter FSL = 1;
   parameter DIV = 0;
   
`include "random.v"
   


   wire [6:2]		cwb_adr_o;
   wire [31:0]		cwb_dat_o;
   wire [3:0]		cwb_sel_o;
   wire			cwb_stb_o;
   wire [1:0]		cwb_tga_o;
   wire			cwb_wre_o;
   wire [DWB-1:2]	dwb_adr_o;
   wire			dwb_cyc_o;
   wire [31:0]		dwb_dat_o;
   wire [3:0]		dwb_sel_o;
   wire			dwb_stb_o;
   wire			dwb_tga_o;
   wire			dwb_wre_o;
   wire [IWB-1:2]	iwb_adr_o;
   wire			iwb_stb_o;
   wire			iwb_tga_o;
   wire			iwb_wre_o;



   reg			cwb_ack_i;
   reg			dwb_ack_i;
   reg			iwb_ack_i;
   reg			sys_clk_i;
   reg			sys_int_i;
   reg			sys_rst_i;

  

   

   reg 	     svc;
   integer   inttime;
   integer   seed;   
   integer   theend;
   
   always #5 sys_clk_i = ~sys_clk_i;   

   initial begin


   end
   
   initial begin
      seed = randseed;
      theend = 0;      
      svc = 0;      
      sys_clk_i = $random(seed);
      sys_rst_i = 1;
      sys_int_i = 0;
      #50 sys_rst_i = 0;
      #3500000 $finish;      
   end
   


   reg [31:0]  rom [0:65535];
   reg [31:0]  ram[0:65535];
   reg [31:0]  dwblat;
   reg [15:2]  dadr, iadr;

   wire [31:0] dwb_dat_t = ram[dwb_adr_o];   
   wire [31:0] iwb_dat_i = rom[iadr]; 
   wire [31:0] dwb_dat_i = ram[dadr];     
   wire [31:0] cwb_dat_i = cwb_adr_o;   

`ifdef POSEDGE  
`else
   
   always @(negedge sys_clk_i) 
     if (sys_rst_i) begin


	cwb_ack_i <= 1'h0;
	dwb_ack_i <= 1'h0;
	iwb_ack_i <= 1'h0;

     end else begin
	iwb_ack_i <= #1 iwb_stb_o;      
	dwb_ack_i <= #1 dwb_stb_o;
	cwb_ack_i <= #1 cwb_stb_o;
     end
   
   always @(negedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;      
      dadr <= #1 dwb_adr_o;
      
      if (dwb_wre_o & dwb_stb_o) begin
	 case (dwb_sel_o)
	   4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
	   4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
	   4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
	   4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
	   4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
	   4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
	   4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
	 endcase
      end
   end
   
`endif
   

   integer i;   
   initial begin
      for (i=0;i<65535;i=i+1) begin
	 ram[i] <= $random;
      end
      #1 $readmemh("dump.vmem",rom);
      #1 $readmemh("dump.vmem",ram);
   end



   integer rnd;
   
   always @(posedge sys_clk_i) begin
	      

      if (!dut.sim.rMSR_IE) begin
	 rnd = $random % 30;	 
	 inttime = $stime + 1000 + (rnd*rnd * 10);
      end
      if ($stime > inttime) begin
	 sys_int_i = 1;
	 svc = 0;	 
      end
      if (($stime > inttime + 500) && !svc) begin
	 $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);	 
	 $finish;	 
      end
      if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;

      

      if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
	 $display("\n\tFAIL");	 
	 $finish;
      end
      
      if (iwb_dat_i == 32'hb8000000) begin
	 theend = theend + 1;	 
      end

      if (theend == 5) begin
	 $display("\n\t*** PASSED ALL TESTS ***");
	 $finish;	 
      end
      
   end
   

   
   aeMB2_sim
     #(

       .IWB				(IWB),
       .DWB				(DWB),
       .TXE				(TXE),
       .MUL				(MUL),
       .BSF				(BSF),
       .FSL				(FSL),
       .DIV				(DIV))
   dut (

	.cwb_adr_o			(cwb_adr_o[6:2]),
	.cwb_dat_o			(cwb_dat_o[31:0]),
	.cwb_sel_o			(cwb_sel_o[3:0]),
	.cwb_stb_o			(cwb_stb_o),
	.cwb_tga_o			(cwb_tga_o[1:0]),
	.cwb_wre_o			(cwb_wre_o),
	.dwb_adr_o			(dwb_adr_o[DWB-1:2]),
	.dwb_cyc_o			(dwb_cyc_o),
	.dwb_dat_o			(dwb_dat_o[31:0]),
	.dwb_sel_o			(dwb_sel_o[3:0]),
	.dwb_stb_o			(dwb_stb_o),
	.dwb_tga_o			(dwb_tga_o),
	.dwb_wre_o			(dwb_wre_o),
	.iwb_adr_o			(iwb_adr_o[IWB-1:2]),
	.iwb_stb_o			(iwb_stb_o),
	.iwb_tga_o			(iwb_tga_o),
	.iwb_wre_o			(iwb_wre_o),

	.cwb_ack_i			(cwb_ack_i),
	.cwb_dat_i			(cwb_dat_i[31:0]),
	.dwb_ack_i			(dwb_ack_i),
	.dwb_dat_i			(dwb_dat_i[31:0]),
	.iwb_ack_i			(iwb_ack_i),
	.iwb_dat_i			(iwb_dat_i[31:0]),
	.sys_clk_i			(sys_clk_i),
	.sys_int_i			(sys_int_i),
	.sys_rst_i			(sys_rst_i));

endmodule
module aemb2 ();

   parameter IWB=16;
   parameter DWB=16;

   parameter TXE = 0;
   
   parameter MUL = 1;
   parameter BSF = 1;
   parameter FSL = 1;
   parameter DIV = 0;
   
`include "random.v"
   


   wire [6:2]		cwb_adr_o;
   wire [31:0]		cwb_dat_o;
   wire [3:0]		cwb_sel_o;
   wire			cwb_stb_o;
   wire [1:0]		cwb_tga_o;
   wire			cwb_wre_o;
   wire [DWB-1:2]	dwb_adr_o;
   wire			dwb_cyc_o;
   wire [31:0]		dwb_dat_o;
   wire [3:0]		dwb_sel_o;
   wire			dwb_stb_o;
   wire			dwb_tga_o;
   wire			dwb_wre_o;
   wire [IWB-1:2]	iwb_adr_o;
   wire			iwb_stb_o;
   wire			iwb_tga_o;
   wire			iwb_wre_o;



   reg			cwb_ack_i;
   reg			dwb_ack_i;
   reg			iwb_ack_i;
   reg			sys_clk_i;
   reg			sys_int_i;
   reg			sys_rst_i;

  

   

   reg 	     svc;
   integer   inttime;
   integer   seed;   
   integer   theend;
   
   always #5 sys_clk_i = ~sys_clk_i;   

   initial begin


   end
   
   initial begin
      seed = randseed;
      theend = 0;      
      svc = 0;      
      sys_clk_i = $random(seed);
      sys_rst_i = 1;
      sys_int_i = 0;
      #50 sys_rst_i = 0;
      #3500000 $finish;      
   end
   


   reg [31:0]  rom [0:65535];
   reg [31:0]  ram[0:65535];
   reg [31:0]  dwblat;
   reg [15:2]  dadr, iadr;

   wire [31:0] dwb_dat_t = ram[dwb_adr_o];   
   wire [31:0] iwb_dat_i = rom[iadr]; 
   wire [31:0] dwb_dat_i = ram[dadr];     
   wire [31:0] cwb_dat_i = cwb_adr_o;   

`ifdef POSEDGE  
`else
   
   always @(negedge sys_clk_i) 
     if (sys_rst_i) begin


	cwb_ack_i <= 1'h0;
	dwb_ack_i <= 1'h0;
	iwb_ack_i <= 1'h0;

     end else begin
	iwb_ack_i <= #1 iwb_stb_o;      
	dwb_ack_i <= #1 dwb_stb_o;
	cwb_ack_i <= #1 cwb_stb_o;
     end
   
   always @(negedge sys_clk_i) begin
      iadr <= #1 iwb_adr_o;      
      dadr <= #1 dwb_adr_o;
      
      if (dwb_wre_o & dwb_stb_o) begin
	 case (dwb_sel_o)
	   4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
	   4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
	   4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
	   4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
	   4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
	   4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
	   4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
	 endcase
      end
   end
   
`endif
   

   integer i;   
   initial begin
      for (i=0;i<65535;i=i+1) begin
	 ram[i] <= $random;
      end
      #1 $readmemh("dump.vmem",rom);
      #1 $readmemh("dump.vmem",ram);
   end



   integer rnd;
   
   always @(posedge sys_clk_i) begin
	      

      if (!dut.sim.rMSR_IE) begin
	 rnd = $random % 30;	 
	 inttime = $stime + 1000 + (rnd*rnd * 10);
      end
      if ($stime > inttime) begin
	 sys_int_i = 1;
	 svc = 0;	 
      end
      if (($stime > inttime + 500) && !svc) begin
	 $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);	 
	 $finish;	 
      end
      if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;

      

      if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
	 $display("\n\tFAIL");	 
	 $finish;
      end
      
      if (iwb_dat_i == 32'hb8000000) begin
	 theend = theend + 1;	 
      end

      if (theend == 5) begin
	 $display("\n\t*** PASSED ALL TESTS ***");
	 $finish;	 
      end
      
   end
   

   
   aeMB2_sim
     #(

       .IWB				(IWB),
       .DWB				(DWB),
       .TXE				(TXE),
       .MUL				(MUL),
       .BSF				(BSF),
       .FSL				(FSL),
       .DIV				(DIV))
   dut (

	.cwb_adr_o			(cwb_adr_o[6:2]),
	.cwb_dat_o			(cwb_dat_o[31:0]),
	.cwb_sel_o			(cwb_sel_o[3:0]),
	.cwb_stb_o			(cwb_stb_o),
	.cwb_tga_o			(cwb_tga_o[1:0]),
	.cwb_wre_o			(cwb_wre_o),
	.dwb_adr_o			(dwb_adr_o[DWB-1:2]),
	.dwb_cyc_o			(dwb_cyc_o),
	.dwb_dat_o			(dwb_dat_o[31:0]),
	.dwb_sel_o			(dwb_sel_o[3:0]),
	.dwb_stb_o			(dwb_stb_o),
	.dwb_tga_o			(dwb_tga_o),
	.dwb_wre_o			(dwb_wre_o),
	.iwb_adr_o			(iwb_adr_o[IWB-1:2]),
	.iwb_stb_o			(iwb_stb_o),
	.iwb_tga_o			(iwb_tga_o),
	.iwb_wre_o			(iwb_wre_o),

	.cwb_ack_i			(cwb_ack_i),
	.cwb_dat_i			(cwb_dat_i[31:0]),
	.dwb_ack_i			(dwb_ack_i),
	.dwb_dat_i			(dwb_dat_i[31:0]),
	.iwb_ack_i			(iwb_ack_i),
	.iwb_dat_i			(iwb_dat_i[31:0]),
	.sys_clk_i			(sys_clk_i),
	.sys_int_i			(sys_int_i),
	.sys_rst_i			(sys_rst_i));

endmodule