data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v
1: b"%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:97: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_Addr_Offset  (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG.sv\n             OUT_REG\n             OUT_REG.v\n             OUT_REG.sv\n             obj_dir/OUT_REG\n             obj_dir/OUT_REG.v\n             obj_dir/OUT_REG.sv\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:110: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Rows (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:123: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Colums (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:136: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Channels (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:149: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Rows (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:162: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Colums (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:175: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Channels (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:187: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Rows (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:199: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Colums (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:211: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_Stride (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:223: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(32)) Reg_Default (\n^~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CONFI_REGS.v:236: Cannot find file containing module: 'DEMUX_1_11'\nDEMUX_1_11 Demux_1_11(\n^~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module CONFI_REGS(


CONFI_REGS_Clk,
CONFI_REGS_Reset,
CONFI_REGS_Addr,
CONFI_REGS_Writedata,
CONFI_REGS_We,
CONFI_REGS_Re,


CONFI_REGS_Readdata,
CONFI_REGS_Reg_Addr_Offset,
CONFI_REGS_Reg_If_Rows,
CONFI_REGS_Reg_If_Colums,
CONFI_REGS_Reg_If_Channels,
CONFI_REGS_Reg_W_Rows,
CONFI_REGS_Reg_W_Colums,
CONFI_REGS_Reg_W_Channels,
CONFI_REGS_Reg_Of_Rows,
CONFI_REGS_Reg_Of_Colums,
CONFI_REGS_Reg_Stride

);




localparam [31:0] DEF_VALUE = 32'b0;
localparam MUX_DATA_IN = 1'b1;





input CONFI_REGS_Clk;
input CONFI_REGS_Reset;
input [3:0] CONFI_REGS_Addr;
input [31:0] CONFI_REGS_Writedata;
input CONFI_REGS_We;
input CONFI_REGS_Re;

output reg [31:0] CONFI_REGS_Readdata;
output [31:0] CONFI_REGS_Reg_Addr_Offset;
output [31:0] CONFI_REGS_Reg_If_Rows;
output [31:0] CONFI_REGS_Reg_If_Colums;
output [31:0] CONFI_REGS_Reg_If_Channels;
output [31:0] CONFI_REGS_Reg_W_Rows;
output [31:0] CONFI_REGS_Reg_W_Colums;
output [31:0] CONFI_REGS_Reg_W_Channels;
output [31:0] CONFI_REGS_Reg_Of_Rows;
output [31:0] CONFI_REGS_Reg_Of_Colums;
output [31:0] CONFI_REGS_Reg_Stride;





wire Reg_Addr_Offset_Set;
wire Reg_If_Rows_Set;
wire Reg_If_Colums_Set;
wire Reg_If_Channels_Set;
wire Reg_W_Rows_Set;
wire Reg_W_Colums_Set;
wire Reg_W_Channels_Set;
wire Reg_Of_Rows_Set;
wire Reg_Of_Colums_Set;
wire Reg_Stride_Set;
wire Reg_Default_Set;
wire [31:0] Reg_Default_Out;





OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Addr_Offset  (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Addr_Offset_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Addr_Offset)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Rows)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Colums)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Channels (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Channels_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Channels)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Rows)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Colums)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Channels (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Channels_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Channels)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Of_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Of_Rows)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Of_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Of_Colums)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Stride (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Stride_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Stride)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Default (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Default_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(Reg_Default_Out)

);


DEMUX_1_11 Demux_1_11(


.DEMUX_Data_in(MUX_DATA_IN),
.DEMUX_selector(CONFI_REGS_Addr),
.DEMUX_En(CONFI_REGS_We),


.DEMUX_out0(Reg_Addr_Offset_Set),
.DEMUX_out1(Reg_If_Rows_Set),
.DEMUX_out2(Reg_If_Colums_Set),
.DEMUX_out3(Reg_If_Channels_Set),
.DEMUX_out4(Reg_W_Rows_Set),
.DEMUX_out5(Reg_W_Colums_Set),
.DEMUX_out6(Reg_W_Channels_Set),
.DEMUX_out7(Reg_Of_Rows_Set),
.DEMUX_out8(Reg_Of_Colums_Set),
.DEMUX_out9(Reg_Stride_Set),
.DEMUX_out10(Reg_Default_Set)

);






always @(posedge CONFI_REGS_Clk)
begin	

	if(CONFI_REGS_Re) begin
		
		case(CONFI_REGS_Addr)
	 
			4'b0000:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Addr_Offset;
			
			
			4'b0001:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Rows;
			
	 
			4'b0010:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Colums;
			
				
			4'b0011:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Channels;
	
	 
			4'b0100:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Rows;
		
	 
			4'b0101:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Colums;
				
			
			4'b0110:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Channels;
			
	 
			4'b0111:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Of_Rows;
		
	 
			4'b1000:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Of_Colums;
		
	 
			4'b1001:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Stride;
		
				
			default:
				CONFI_REGS_Readdata<=DEF_VALUE;
		
		endcase
		
	end
	
end



endmodule
module CONFI_REGS(


CONFI_REGS_Clk,
CONFI_REGS_Reset,
CONFI_REGS_Addr,
CONFI_REGS_Writedata,
CONFI_REGS_We,
CONFI_REGS_Re,


CONFI_REGS_Readdata,
CONFI_REGS_Reg_Addr_Offset,
CONFI_REGS_Reg_If_Rows,
CONFI_REGS_Reg_If_Colums,
CONFI_REGS_Reg_If_Channels,
CONFI_REGS_Reg_W_Rows,
CONFI_REGS_Reg_W_Colums,
CONFI_REGS_Reg_W_Channels,
CONFI_REGS_Reg_Of_Rows,
CONFI_REGS_Reg_Of_Colums,
CONFI_REGS_Reg_Stride

);





localparam [31:0] DEF_VALUE = 32'b0;
localparam MUX_DATA_IN = 1'b1;





input CONFI_REGS_Clk;
input CONFI_REGS_Reset;
input [3:0] CONFI_REGS_Addr;
input [31:0] CONFI_REGS_Writedata;
input CONFI_REGS_We;
input CONFI_REGS_Re;

output reg [31:0] CONFI_REGS_Readdata;
output [31:0] CONFI_REGS_Reg_Addr_Offset;
output [31:0] CONFI_REGS_Reg_If_Rows;
output [31:0] CONFI_REGS_Reg_If_Colums;
output [31:0] CONFI_REGS_Reg_If_Channels;
output [31:0] CONFI_REGS_Reg_W_Rows;
output [31:0] CONFI_REGS_Reg_W_Colums;
output [31:0] CONFI_REGS_Reg_W_Channels;
output [31:0] CONFI_REGS_Reg_Of_Rows;
output [31:0] CONFI_REGS_Reg_Of_Colums;
output [31:0] CONFI_REGS_Reg_Stride;





wire Reg_Addr_Offset_Set;
wire Reg_If_Rows_Set;
wire Reg_If_Colums_Set;
wire Reg_If_Channels_Set;
wire Reg_W_Rows_Set;
wire Reg_W_Colums_Set;
wire Reg_W_Channels_Set;
wire Reg_Of_Rows_Set;
wire Reg_Of_Colums_Set;
wire Reg_Stride_Set;
wire Reg_Default_Set;
wire [31:0] Reg_Default_Out;





OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Addr_Offset  (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Addr_Offset_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Addr_Offset)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Rows)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Colums)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_If_Channels (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_If_Channels_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_If_Channels)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Rows)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Colums)

);


OUT_REG #(.REG_DATA_WIDTH(32)) Reg_W_Channels (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_W_Channels_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_W_Channels)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Rows (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Of_Rows_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Of_Rows)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Of_Colums (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Of_Colums_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Of_Colums)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Stride (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Stride_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(CONFI_REGS_Reg_Stride)

);

OUT_REG #(.REG_DATA_WIDTH(32)) Reg_Default (


.OUT_REG_Clk(CONFI_REGS_Clk),
.OUT_REG_Reset(CONFI_REGS_Reset),
.OUT_REG_Set(Reg_Default_Set),
.OUT_REG_Input_Data(CONFI_REGS_Writedata),

.OUT_REG_Output_Data(Reg_Default_Out)

);


DEMUX_1_11 Demux_1_11(


.DEMUX_Data_in(MUX_DATA_IN),
.DEMUX_selector(CONFI_REGS_Addr),
.DEMUX_En(CONFI_REGS_We),


.DEMUX_out0(Reg_Addr_Offset_Set),
.DEMUX_out1(Reg_If_Rows_Set),
.DEMUX_out2(Reg_If_Colums_Set),
.DEMUX_out3(Reg_If_Channels_Set),
.DEMUX_out4(Reg_W_Rows_Set),
.DEMUX_out5(Reg_W_Colums_Set),
.DEMUX_out6(Reg_W_Channels_Set),
.DEMUX_out7(Reg_Of_Rows_Set),
.DEMUX_out8(Reg_Of_Colums_Set),
.DEMUX_out9(Reg_Stride_Set),
.DEMUX_out10(Reg_Default_Set)

);






always @(posedge CONFI_REGS_Clk)
begin	

	if(CONFI_REGS_Re) begin
		
		case(CONFI_REGS_Addr)
	 
			4'b0000:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Addr_Offset;
			
			
			4'b0001:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Rows;
			
	 
			4'b0010:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Colums;
			
				
			4'b0011:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_If_Channels;
	
	 
			4'b0100:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Rows;
		
	 
			4'b0101:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Colums;
				
			
			4'b0110:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_W_Channels;
			
	 
			4'b0111:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Of_Rows;
		
	 
			4'b1000:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Of_Colums;
		
	 
			4'b1001:
				CONFI_REGS_Readdata<=CONFI_REGS_Reg_Stride;
		
				
			default:
				CONFI_REGS_Readdata<=DEF_VALUE;
		
		endcase
		
	end
	
end



endmodule