data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv
1: b'%Error: data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv:1: Cannot find include file: definitions.sv\n`include "definitions.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.v\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.sv\n             definitions.sv\n             definitions.sv.v\n             definitions.sv.sv\n             obj_dir/definitions.sv\n             obj_dir/definitions.sv.v\n             obj_dir/definitions.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv:8: Unsupported: Ignoring delay on this delayed statement.\n        #5 Clock = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv:9: Unsupported: Ignoring delay on this delayed statement.\n        #5 Clock = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n#40 Reset = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/496325532/vga_playground/sv/top_tb.sv:17: Unsupported: Ignoring delay on this delayed statement.\n#100000 $finish;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module top_tb ();
    logic Clock;
    logic Reset;

initial begin: clock_gen
    forever begin
        #5 Clock = 1'b0;
        #5 Clock = 1'b1;
    end
end: clock_gen


initial begin: reset_gen
    Reset = 1'b1;
#40 Reset = 1'b0;
#100000 $finish;
end: reset_gen

logic [1:0] BUTTON;
assign BUTTON = {2{~Reset}};
top top (
        .CLK_50(Clock),
        .SW('1),
        .BUTTON(BUTTON),
        .HEX0(),
        .HEX1(),
        .HEX2(),
        .HEX3(),
        .HEX4(),
        .HEX5(),
        .LED(),
        .RED(),
        .GREEN(),
        .BLUE(),
        .h_sync(),
        .v_sync()
    );

endmodule
module top_tb ();

    logic Clock;
    logic Reset;

initial begin: clock_gen
    forever begin
        #5 Clock = 1'b0;
        #5 Clock = 1'b1;
    end
end: clock_gen


initial begin: reset_gen
    Reset = 1'b1;
#40 Reset = 1'b0;
#100000 $finish;
end: reset_gen

logic [1:0] BUTTON;
assign BUTTON = {2{~Reset}};
top top (
        .CLK_50(Clock),
        .SW('1),
        .BUTTON(BUTTON),
        .HEX0(),
        .HEX1(),
        .HEX2(),
        .HEX3(),
        .HEX4(),
        .HEX5(),
        .LED(),
        .RED(),
        .GREEN(),
        .BLUE(),
        .h_sync(),
        .v_sync()
    );

endmodule