data/full_repos/permissive/451577625/system/registerfile_16x32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/registerfile_16x32.v:142: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 r_clk = ~r_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/registerfile_16x32.v:128: Cell has missing pin: \'in_BAout\'\nregisterfile_16x32 DUT (\n                   ^~~\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:21: Cannot find file containing module: \'decoder_4_to_16\'\n decoder_4_to_16 Adecoder(\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16.sv\n             decoder_4_to_16\n             decoder_4_to_16.v\n             decoder_4_to_16.sv\n             obj_dir/decoder_4_to_16\n             obj_dir/decoder_4_to_16.v\n             obj_dir/decoder_4_to_16.sv\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:28: Cannot find file containing module: \'decoder_4_to_16\'\n decoder_4_to_16 Cdecoder(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:45: Cannot find file containing module: \'register_32\'\n   register_32 register_inst (\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/registerfile_16x32.v:62: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'in_BAout\' generates 1 bits.\n                                                                                   : ... In instance registerfile_16x32_tb.DUT\n    r_data_out = w_reg_out[0]&(~in_BAout);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/registerfile_16x32.v:60: Operator CASE expects 16 bits on the Case expression, but Case expression\'s VARREF \'in_Aselect\' generates 4 bits.\n                                                                                   : ... In instance registerfile_16x32_tb.DUT\n  case (in_Aselect)\n  ^~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registerfile_16x32_tb;

reg [31:0] r_Cdata;
reg [3:0] r_Cselect;

reg [3:0] r_Aselect;
wire [31:0] w_Adata;
reg r_clr;
reg r_write;
reg r_read;
reg r_clk;


parameter Default = 4'b0000;
parameter s_clear_all = 4'b0001;
parameter s_write_to_first = 4'b0010;
parameter s_write_to_first_2 = 4'b0011;
parameter s_write_to_second = 4'b0100;
parameter s_read_from_second = 4'b0101;

reg [3:0] Present_state = Default;

registerfile_16x32 DUT (
	.in_Cdata(r_Cdata),
	.in_Cselect(r_Cselect),
	.in_Aselect(r_Aselect),
	.out_Adata(w_Adata),
	.in_clr(r_clr),
	.in_write(r_write),
	.in_read(r_read),
	.in_clk(r_clk)
 );
 
initial
	begin
		r_clk = 0;
		forever #10 r_clk = ~r_clk;
end

always @ (posedge r_clk)
	begin
		case (Present_state)
			Default : Present_state = s_write_to_first;
			s_write_to_first : Present_state = s_write_to_first_2;
			s_write_to_first_2 : Present_state = s_write_to_second;
			s_write_to_second : Present_state = s_read_from_second;
			s_read_from_second : Present_state = s_clear_all;
		endcase
	end
	
always @ (Present_state)
begin
	case(Present_state)
	Default: begin
		r_Cdata = 'h00000000;
		r_Cselect = 'b0000;
		r_Aselect = 'b0000;
		r_clr = 1;
		r_write = 0;
		r_read = 0;
	end
	s_clear_all: begin
		r_Cdata = 'h00000000;
		r_Cselect = 'b0000;
		r_Aselect = 'b0000;
		r_clr = 0;
		r_write = 0;
		r_read = 0;
	end
	s_write_to_first: begin
		r_Cdata = 'h11111111;
		r_Cselect = 'b0000;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	s_write_to_first_2: begin
		r_Cdata = 'h11110000;
		r_Cselect = 'b0000;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	s_write_to_second: begin
		r_Cdata = 'h11111111;
		r_Cselect = 'b0001;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	endcase
end
	
	
 
	


endmodule
module registerfile_16x32_tb;


reg [31:0] r_Cdata;
reg [3:0] r_Cselect;

reg [3:0] r_Aselect;
wire [31:0] w_Adata;
reg r_clr;
reg r_write;
reg r_read;
reg r_clk;


parameter Default = 4'b0000;
parameter s_clear_all = 4'b0001;
parameter s_write_to_first = 4'b0010;
parameter s_write_to_first_2 = 4'b0011;
parameter s_write_to_second = 4'b0100;
parameter s_read_from_second = 4'b0101;

reg [3:0] Present_state = Default;

registerfile_16x32 DUT (
	.in_Cdata(r_Cdata),
	.in_Cselect(r_Cselect),
	.in_Aselect(r_Aselect),
	.out_Adata(w_Adata),
	.in_clr(r_clr),
	.in_write(r_write),
	.in_read(r_read),
	.in_clk(r_clk)
 );
 
initial
	begin
		r_clk = 0;
		forever #10 r_clk = ~r_clk;
end

always @ (posedge r_clk)
	begin
		case (Present_state)
			Default : Present_state = s_write_to_first;
			s_write_to_first : Present_state = s_write_to_first_2;
			s_write_to_first_2 : Present_state = s_write_to_second;
			s_write_to_second : Present_state = s_read_from_second;
			s_read_from_second : Present_state = s_clear_all;
		endcase
	end
	
always @ (Present_state)
begin
	case(Present_state)
	Default: begin
		r_Cdata = 'h00000000;
		r_Cselect = 'b0000;
		r_Aselect = 'b0000;
		r_clr = 1;
		r_write = 0;
		r_read = 0;
	end
	s_clear_all: begin
		r_Cdata = 'h00000000;
		r_Cselect = 'b0000;
		r_Aselect = 'b0000;
		r_clr = 0;
		r_write = 0;
		r_read = 0;
	end
	s_write_to_first: begin
		r_Cdata = 'h11111111;
		r_Cselect = 'b0000;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	s_write_to_first_2: begin
		r_Cdata = 'h11110000;
		r_Cselect = 'b0000;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	s_write_to_second: begin
		r_Cdata = 'h11111111;
		r_Cselect = 'b0001;
		r_clr = 1;
		r_write = 1;
		r_read = 0;
	end
	endcase
end
	
	
 
	


endmodule