data/full_repos/permissive/480681467/main/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:25: Operator ASSIGN expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                   : ... In instance control.i.x_mod_y\n           p = {p[WIDTH-2:0],A[WIDTH-1]};\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:38: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 65 bits.\n                                                                   : ... In instance control.i.x_mod_y\n   assign R = p,Q = A;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'p\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'q\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:119: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_reg\' generates 32 bits.\n                                                                    : ... In instance control.i\n    assign e = e_reg;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:151: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_plus3\' generates 32 bits.\n                                                                    : ... In instance control.i\n                         b <= e_plus3;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:77: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                   : ... In instance control.m\n            result_reg <= 32\'d1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:190: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'msg_in\' generates 32 bits.\n                                                                    : ... In instance control\n         msg_reg <= msg_in;\n                 ^~\n%Error: Exiting due to 8 warning(s)\n'
module mod(
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] n,
    output [WIDTH-1:0] R,
    output [WIDTH-1:0] Q
    );
   parameter WIDTH = 19;
   reg [WIDTH-1:0] A,N;
   reg [WIDTH:0] p;   
   integer i;
  
   always@ (a or n) begin
       A = a;
       N = n;
       p = 0;
       for(i=0;i < WIDTH;i=i+1) begin 
           p = {p[WIDTH-2:0],A[WIDTH-1]};
           A[WIDTH-1:1] = A[WIDTH-2:0];
           p = p-N;
           if(p[WIDTH-1] == 1)begin
                A[0] = 1'b0;
                p = p + N;   
           end
           else
                A[0] =1'b1;
      end
         
   end    
   
   assign R = p,Q = A;
endmodule
module mod(
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] n,
    output [WIDTH-1:0] R,
    output [WIDTH-1:0] Q
    );

   parameter WIDTH = 19;
   reg [WIDTH-1:0] A,N;
   reg [WIDTH:0] p;   
   integer i;
  
   always@ (a or n) begin
       A = a;
       N = n;
       p = 0;
       for(i=0;i < WIDTH;i=i+1) begin 
           p = {p[WIDTH-2:0],A[WIDTH-1]};
           A[WIDTH-1:1] = A[WIDTH-2:0];
           p = p-N;
           if(p[WIDTH-1] == 1)begin
                A[0] = 1'b0;
                p = p + N;   
           end
           else
                A[0] =1'b1;
      end
         
   end    
   
   assign R = p,Q = A;
endmodule