data/full_repos/permissive/505376079/sources/my_multi_addere.v
data/verilator_xmls/0551fe8a-2932-4097-a665-a232e5a5468d.xml
module my_multi_addere(
  input clk,
  input wire signed [15:0] a,
  input wire signed [15:0] b,
  input wire signed[35:0] c,
  output reg signed [35:0] p
    );

reg signed [35:0] m ;


always @(posedge clk)
begin


  m <= a*b;
  p <= m+c;
end
endmodule
module my_multi_addere(
  input clk,
  input wire signed [15:0] a,
  input wire signed [15:0] b,
  input wire signed[35:0] c,
  output reg signed [35:0] p
    );


reg signed [35:0] m ;


always @(posedge clk)
begin


  m <= a*b;
  p <= m+c;
end
endmodule