data/full_repos/permissive/419538859/lab2/lab2_1/bcd_to_seg7_top.v
data/verilator_xmls/abdad95a-37cc-43da-aa74-61bc254951e1.xml
module bcd_to_seg7(bcd_in, seg7_sel, seg7_out, dpt_out);
input [3:0] bcd_in;
output [2:0] seg7_sel;
output [6:0] seg7_out;
output dpt_out;
bcd_to_seg7_1 m1(bcd_in, seg7_out);
assign seg7_sel = 3'b101;
assign dpt_out= 1'b0; 
endmodule
module bcd_to_seg7(bcd_in, seg7_sel, seg7_out, dpt_out);

input [3:0] bcd_in;
output [2:0] seg7_sel;
output [6:0] seg7_out;
output dpt_out;
bcd_to_seg7_1 m1(bcd_in, seg7_out);
assign seg7_sel = 3'b101;
assign dpt_out= 1'b0; 
endmodule