data/full_repos/permissive/454159683/mux8to1j/mux2to1.v
data/verilator_xmls/f1b190f3-a09d-4339-9d22-013cdeadaccf.xml
module mux2to1(input a, b, sel, output out);
	assign out = (a & !sel) | (b & sel);
endmodule
module mux2to1(input a, b, sel, output out);

	assign out = (a & !sel) | (b & sel);
endmodule