data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module InstructMem(a, do);
    input [31:0] a;
    output reg [31:0] do;
    reg [31:0] IM[0:511];
    initial begin
        IM[32'd100] = 32'h8c220000;
        IM[32'd104] = 32'h8c230004;
        IM[32'd108] = 32'h8c240008;
        IM[32'd112] = 32'h8c25000c;
    end
    
    always @ (a) begin
        do <= IM[a];
    end
endmodule
module InstructMem(a, do);

    input [31:0] a;
    output reg [31:0] do;
    reg [31:0] IM[0:511];
    initial begin
        IM[32'd100] = 32'h8c220000;
        IM[32'd104] = 32'h8c230004;
        IM[32'd108] = 32'h8c240008;
        IM[32'd112] = 32'h8c25000c;
    end
    
    always @ (a) begin
        do <= IM[a];
    end
endmodule