data/full_repos/permissive/497819211/03/Register.v
1: b'%Error: data/full_repos/permissive/497819211/03/Register.v:6: Cannot find include file: Bit.v\n`include "Bit.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v.sv\n             Bit.v\n             Bit.v.v\n             Bit.v.sv\n             obj_dir/Bit.v\n             obj_dir/Bit.v.v\n             obj_dir/Bit.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Register(
	input clk,
	input [15:0] in,
	input load,
	output [15:0] out
);
















    Bit BIT1(.in(in[0]),.load(load),.out(out[0]), .clk(clk));
    Bit BIT2(.in(in[1]),.load(load),.out(out[1]), .clk(clk));
    Bit BIT3(.in(in[2]),.load(load),.out(out[2]), .clk(clk));
    Bit BIT4(.in(in[3]),.load(load),.out(out[3]), .clk(clk));
    Bit BIT5(.in(in[4]),.load(load),.out(out[4]), .clk(clk));
    Bit BIT6(.in(in[5]),.load(load),.out(out[5]), .clk(clk));
    Bit BIT7(.in(in[6]),.load(load),.out(out[6]), .clk(clk));
    Bit BIT8(.in(in[7]),.load(load),.out(out[7]), .clk(clk));
    Bit BIT9(.in(in[8]),.load(load),.out(out[8]), .clk(clk));
    Bit BIT10(.in(in[9]),.load(load),.out(out[9]), .clk(clk));
    Bit BIT11(.in(in[10]),.load(load),.out(out[10]), .clk(clk));
    Bit BIT12(.in(in[11]),.load(load),.out(out[11]), .clk(clk));
    Bit BIT13(.in(in[12]),.load(load),.out(out[12]), .clk(clk));
    Bit BIT14(.in(in[13]),.load(load),.out(out[13]), .clk(clk));
    Bit BIT15(.in(in[14]),.load(load),.out(out[14]), .clk(clk));
    Bit BIT16(.in(in[15]),.load(load),.out(out[15]), .clk(clk));


endmodule
module Register(
	input clk,
	input [15:0] in,
	input load,
	output [15:0] out
);

















    Bit BIT1(.in(in[0]),.load(load),.out(out[0]), .clk(clk));
    Bit BIT2(.in(in[1]),.load(load),.out(out[1]), .clk(clk));
    Bit BIT3(.in(in[2]),.load(load),.out(out[2]), .clk(clk));
    Bit BIT4(.in(in[3]),.load(load),.out(out[3]), .clk(clk));
    Bit BIT5(.in(in[4]),.load(load),.out(out[4]), .clk(clk));
    Bit BIT6(.in(in[5]),.load(load),.out(out[5]), .clk(clk));
    Bit BIT7(.in(in[6]),.load(load),.out(out[6]), .clk(clk));
    Bit BIT8(.in(in[7]),.load(load),.out(out[7]), .clk(clk));
    Bit BIT9(.in(in[8]),.load(load),.out(out[8]), .clk(clk));
    Bit BIT10(.in(in[9]),.load(load),.out(out[9]), .clk(clk));
    Bit BIT11(.in(in[10]),.load(load),.out(out[10]), .clk(clk));
    Bit BIT12(.in(in[11]),.load(load),.out(out[11]), .clk(clk));
    Bit BIT13(.in(in[12]),.load(load),.out(out[12]), .clk(clk));
    Bit BIT14(.in(in[13]),.load(load),.out(out[13]), .clk(clk));
    Bit BIT15(.in(in[14]),.load(load),.out(out[14]), .clk(clk));
    Bit BIT16(.in(in[15]),.load(load),.out(out[15]), .clk(clk));


endmodule