data/full_repos/permissive/527176783/Pipeline/Stall.v
1: b'%Error: data/full_repos/permissive/527176783/Pipeline/Stall.v:3: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Stall(
    input  [4:0] rs_ID,
    input  [4:0] rt_ID,
    input  [4:0] rt_EX,
    input  [4:0] WriteReg_EX,
    input  [4:0] WriteReg_MEM,
    input  Branch_ID,
    input  regWr_EX,
    input  regWr_MEM,
    input  Wrback_EX,
    output reg Stall_IF,
    output reg Stall_ID,
    output reg Flush_EX
);
    wire lwstall;
    wire branchstall;

    initial begin
        Stall_IF = 1'b0;
        Stall_ID = 1'b0;
        Flush_EX = 1'b0;
    end



    assign lwstall = ((rs_ID == rt_EX) | (rt_ID == rt_EX)) & ( Wrback_EX == 1);
    assign branchstall = ((Branch_ID ==1) & (regWr_EX == 1) & ((WriteReg_EX == rs_ID) | (WriteReg_EX == rt_ID)))
                        || ((Branch_ID ==1) & (regWr_MEM == 1) & ((WriteReg_MEM == rs_ID) | (WriteReg_MEM == rt_ID)));

    always @(*) begin
        if((lwstall == 1'b1) | (branchstall == 1'b1))begin
            Stall_IF = 1'b1;
            Stall_ID = 1'b1;
            Flush_EX = 1'b1;
        end
        else begin
            Stall_IF = 1'b0;
            Stall_ID = 1'b0;
            Flush_EX = 1'b0;
        end
    end

endmodule
module Stall(
    input  [4:0] rs_ID,
    input  [4:0] rt_ID,
    input  [4:0] rt_EX,
    input  [4:0] WriteReg_EX,
    input  [4:0] WriteReg_MEM,
    input  Branch_ID,
    input  regWr_EX,
    input  regWr_MEM,
    input  Wrback_EX,
    output reg Stall_IF,
    output reg Stall_ID,
    output reg Flush_EX
);

    wire lwstall;
    wire branchstall;

    initial begin
        Stall_IF = 1'b0;
        Stall_ID = 1'b0;
        Flush_EX = 1'b0;
    end



    assign lwstall = ((rs_ID == rt_EX) | (rt_ID == rt_EX)) & ( Wrback_EX == 1);
    assign branchstall = ((Branch_ID ==1) & (regWr_EX == 1) & ((WriteReg_EX == rs_ID) | (WriteReg_EX == rt_ID)))
                        || ((Branch_ID ==1) & (regWr_MEM == 1) & ((WriteReg_MEM == rs_ID) | (WriteReg_MEM == rt_ID)));

    always @(*) begin
        if((lwstall == 1'b1) | (branchstall == 1'b1))begin
            Stall_IF = 1'b1;
            Stall_ID = 1'b1;
            Flush_EX = 1'b1;
        end
        else begin
            Stall_IF = 1'b0;
            Stall_ID = 1'b0;
            Flush_EX = 1'b0;
        end
    end

endmodule