data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v
1: b'%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:8: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                            : ... In instance TOP\n    if(RST[0]) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:25: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                     : ... In instance TOP\n      cnt3 <= cnt1[0];\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:48: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                     : ... In instance TOP\n      cnt6 <= 7\'d0 + cnt1[1:0];\n                   ^\n%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:73: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                             : ... In instance TOP\n    if(RST[zero]) begin\n          ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module TOP(CLK, RST);
  input CLK, RST;
  reg [7:0] cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7,cnt8,cnt9,cnt10;
  parameter zero = 0;


  always @(posedge CLK) begin
    if(RST[0]) begin
      cnt1 <= 0;
    end else begin
      cnt1 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST)
    if(RST)
      cnt2 <= 0;
    else
      cnt2 <= 8'd1;


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt3 <= cnt1[0];
    end else begin
      cnt3 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST) begin
    cnt4 <= 0;
  end


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt5 <= {2'd0,6'd0};
    end else begin
      cnt5 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt6 <= 7'd0 + cnt1[1:0];
    end else begin
      cnt6 <= 8'd1;
    end
  end


  always @(posedge CLK) begin
    if(!RST) begin
      cnt7 <= 0;
    end else begin
      cnt7 <= 8'd1;
    end
  end


  always @(posedge CLK) begin
    if(RST && RST) begin
      cnt8 <= 0;
    end else begin
      cnt8 <= 8'd1;
    end
  end

  always @(posedge CLK) begin
    if(RST[zero]) begin
      cnt10 <= 0;
    end else begin
      cnt10 <= 8'd1;
    end
  end

  SUB sub(CLK,RST);

endmodule
module TOP(CLK, RST);

  input CLK, RST;
  reg [7:0] cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7,cnt8,cnt9,cnt10;
  parameter zero = 0;


  always @(posedge CLK) begin
    if(RST[0]) begin
      cnt1 <= 0;
    end else begin
      cnt1 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST)
    if(RST)
      cnt2 <= 0;
    else
      cnt2 <= 8'd1;


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt3 <= cnt1[0];
    end else begin
      cnt3 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST) begin
    cnt4 <= 0;
  end


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt5 <= {2'd0,6'd0};
    end else begin
      cnt5 <= 8'd1;
    end
  end


  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      cnt6 <= 7'd0 + cnt1[1:0];
    end else begin
      cnt6 <= 8'd1;
    end
  end


  always @(posedge CLK) begin
    if(!RST) begin
      cnt7 <= 0;
    end else begin
      cnt7 <= 8'd1;
    end
  end


  always @(posedge CLK) begin
    if(RST && RST) begin
      cnt8 <= 0;
    end else begin
      cnt8 <= 8'd1;
    end
  end

  always @(posedge CLK) begin
    if(RST[zero]) begin
      cnt10 <= 0;
    end else begin
      cnt10 <= 8'd1;
    end
  end

  SUB sub(CLK,RST);

endmodule