data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v:195: Unsupported: Ignoring delay on this delayed statement.\n       #10;  \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v:127: Little bit endian vector: MSB < LSB of bit range: 0:23\n output [0:23] rd0_dat;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v:128: Little bit endian vector: MSB < LSB of bit range: 0:23\n output [0:23] rd1_dat;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v:129: Little bit endian vector: MSB < LSB of bit range: 0:23\n input  [0:23] wr0_dat;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/regfile_2r1w_64x24.v:157: Little bit endian vector: MSB < LSB of bit range: 0:23\n reg[0:23] mem[0:63];\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile_2r1w_64x24(

    rd0_c_na0,
    rd0_c_a0,
    rd0_na1_na2,
    rd0_na1_a2,
    rd0_a1_na2,
    rd0_a1_a2,
    rd0_na3,
    rd0_a3,
    rd0_na4_na5,
    rd0_na4_a5,
    rd0_a4_na5,
    rd0_a4_a5,
    rd0_dat,

    rd1_c_na0,
    rd1_c_a0,
    rd1_na1_na2,
    rd1_na1_a2,
    rd1_a1_na2,
    rd1_a1_a2,
    rd1_na3,
    rd1_a3,
    rd1_na4_na5,
    rd1_na4_a5,
    rd1_a4_na5,
    rd1_a4_a5,
    rd1_dat,

    wr0_c_na0,
    wr0_c_a0,
    wr0_na1_na2,
    wr0_na1_a2,
    wr0_a1_na2,
    wr0_a1_a2,
    wr0_na3,
    wr0_a3,
    wr0_na4_na5,
    wr0_na4_a5,
    wr0_a4_na5,
    wr0_a4_a5,
    wr0_dat

);




 input   rd0_c_na0;
 input   rd0_c_a0;

 input   rd0_na1_na2;
 input   rd0_na1_a2;
 input   rd0_a1_na2;
 input   rd0_a1_a2;

 input   rd0_na3;
 input   rd0_a3;

 input   rd0_na4_na5;
 input   rd0_na4_a5;
 input   rd0_a4_na5;
 input   rd0_a4_a5;


 input   rd1_c_na0;
 input   rd1_c_a0;

 input   rd1_na1_na2;
 input   rd1_na1_a2;
 input   rd1_a1_na2;
 input   rd1_a1_a2;

 input   rd1_na3;
 input   rd1_a3;

 input   rd1_na4_na5;
 input   rd1_na4_a5;
 input   rd1_a4_na5;
 input   rd1_a4_a5;


 input   wr0_c_na0;
 input   wr0_c_a0;

 input   wr0_na1_na2;
 input   wr0_na1_a2;
 input   wr0_a1_na2;
 input   wr0_a1_a2;

 input   wr0_na3;
 input   wr0_a3;

 input   wr0_na4_na5;
 input   wr0_na4_a5;
 input   wr0_a4_na5;
 input   wr0_a4_a5;


 output [0:23] rd0_dat;
 output [0:23] rd1_dat;
 input  [0:23] wr0_dat;

 wire rd0_enable;
 wire rd1_enable;
 wire wr0_enable;

 wire rd0_a0;
 wire rd0_a1;
 wire rd0_a2;

 wire rd0_a4;
 wire rd0_a5;

 wire rd1_a0;
 wire rd1_a1;
 wire rd1_a2;

 wire rd1_a4;
 wire rd1_a5;

 wire wr0_a0;
 wire wr0_a1;
 wire wr0_a2;

 wire wr0_a4;
 wire wr0_a5;


 reg[0:23] mem[0:63];


 assign rd0_enable = rd0_c_a0 | rd0_c_na0;
 assign rd0_a0 = rd0_c_a0;
 assign rd0_a1 = rd0_a1_a2 | rd0_a1_na2;
 assign rd0_a2 = rd0_a1_a2 | rd0_na1_a2;

 assign rd0_a4 = rd0_a4_a5 | rd0_a4_na5;
 assign rd0_a5 = rd0_a4_a5 | rd0_na4_a5;


 assign rd1_enable = rd1_c_a0 | rd1_c_na0;
 assign rd1_a0 = rd1_c_a0;
 assign rd1_a1 = rd1_a1_a2 | rd1_a1_na2;
 assign rd1_a2 = rd1_a1_a2 | rd1_na1_a2;

 assign rd1_a4 = rd1_a4_a5 | rd1_a4_na5;
 assign rd1_a5 = rd1_a4_a5 | rd1_na4_a5;



 assign wr0_enable = wr0_c_a0 | wr0_c_na0;
 assign wr0_a0 = wr0_c_a0;
 assign wr0_a1 = wr0_a1_a2 | wr0_a1_na2;
 assign wr0_a2 = wr0_a1_a2 | wr0_na1_a2;

 assign wr0_a4 = wr0_a4_a5 | wr0_a4_na5;
 assign wr0_a5 = wr0_a4_a5 | wr0_na4_a5;



 assign rd0_dat = (rd0_enable) ? mem[{rd0_a0, rd0_a1, rd0_a2, rd0_a3, rd0_a4, rd0_a5}] : 24'bX;
 assign rd1_dat = (rd1_enable) ? mem[{rd1_a0, rd1_a1, rd1_a2, rd1_a3, rd1_a4, rd1_a5}] : 24'bX;


 always @* begin
    if (wr0_enable) begin
       #10;
       if (wr0_enable) begin
          mem[{wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4, wr0_a5}] <= wr0_dat;

       end
    end
 end

endmodule
module regfile_2r1w_64x24(

    rd0_c_na0,
    rd0_c_a0,
    rd0_na1_na2,
    rd0_na1_a2,
    rd0_a1_na2,
    rd0_a1_a2,
    rd0_na3,
    rd0_a3,
    rd0_na4_na5,
    rd0_na4_a5,
    rd0_a4_na5,
    rd0_a4_a5,
    rd0_dat,

    rd1_c_na0,
    rd1_c_a0,
    rd1_na1_na2,
    rd1_na1_a2,
    rd1_a1_na2,
    rd1_a1_a2,
    rd1_na3,
    rd1_a3,
    rd1_na4_na5,
    rd1_na4_a5,
    rd1_a4_na5,
    rd1_a4_a5,
    rd1_dat,

    wr0_c_na0,
    wr0_c_a0,
    wr0_na1_na2,
    wr0_na1_a2,
    wr0_a1_na2,
    wr0_a1_a2,
    wr0_na3,
    wr0_a3,
    wr0_na4_na5,
    wr0_na4_a5,
    wr0_a4_na5,
    wr0_a4_a5,
    wr0_dat

);





 input   rd0_c_na0;
 input   rd0_c_a0;

 input   rd0_na1_na2;
 input   rd0_na1_a2;
 input   rd0_a1_na2;
 input   rd0_a1_a2;

 input   rd0_na3;
 input   rd0_a3;

 input   rd0_na4_na5;
 input   rd0_na4_a5;
 input   rd0_a4_na5;
 input   rd0_a4_a5;


 input   rd1_c_na0;
 input   rd1_c_a0;

 input   rd1_na1_na2;
 input   rd1_na1_a2;
 input   rd1_a1_na2;
 input   rd1_a1_a2;

 input   rd1_na3;
 input   rd1_a3;

 input   rd1_na4_na5;
 input   rd1_na4_a5;
 input   rd1_a4_na5;
 input   rd1_a4_a5;


 input   wr0_c_na0;
 input   wr0_c_a0;

 input   wr0_na1_na2;
 input   wr0_na1_a2;
 input   wr0_a1_na2;
 input   wr0_a1_a2;

 input   wr0_na3;
 input   wr0_a3;

 input   wr0_na4_na5;
 input   wr0_na4_a5;
 input   wr0_a4_na5;
 input   wr0_a4_a5;


 output [0:23] rd0_dat;
 output [0:23] rd1_dat;
 input  [0:23] wr0_dat;

 wire rd0_enable;
 wire rd1_enable;
 wire wr0_enable;

 wire rd0_a0;
 wire rd0_a1;
 wire rd0_a2;

 wire rd0_a4;
 wire rd0_a5;

 wire rd1_a0;
 wire rd1_a1;
 wire rd1_a2;

 wire rd1_a4;
 wire rd1_a5;

 wire wr0_a0;
 wire wr0_a1;
 wire wr0_a2;

 wire wr0_a4;
 wire wr0_a5;


 reg[0:23] mem[0:63];


 assign rd0_enable = rd0_c_a0 | rd0_c_na0;
 assign rd0_a0 = rd0_c_a0;
 assign rd0_a1 = rd0_a1_a2 | rd0_a1_na2;
 assign rd0_a2 = rd0_a1_a2 | rd0_na1_a2;

 assign rd0_a4 = rd0_a4_a5 | rd0_a4_na5;
 assign rd0_a5 = rd0_a4_a5 | rd0_na4_a5;


 assign rd1_enable = rd1_c_a0 | rd1_c_na0;
 assign rd1_a0 = rd1_c_a0;
 assign rd1_a1 = rd1_a1_a2 | rd1_a1_na2;
 assign rd1_a2 = rd1_a1_a2 | rd1_na1_a2;

 assign rd1_a4 = rd1_a4_a5 | rd1_a4_na5;
 assign rd1_a5 = rd1_a4_a5 | rd1_na4_a5;



 assign wr0_enable = wr0_c_a0 | wr0_c_na0;
 assign wr0_a0 = wr0_c_a0;
 assign wr0_a1 = wr0_a1_a2 | wr0_a1_na2;
 assign wr0_a2 = wr0_a1_a2 | wr0_na1_a2;

 assign wr0_a4 = wr0_a4_a5 | wr0_a4_na5;
 assign wr0_a5 = wr0_a4_a5 | wr0_na4_a5;



 assign rd0_dat = (rd0_enable) ? mem[{rd0_a0, rd0_a1, rd0_a2, rd0_a3, rd0_a4, rd0_a5}] : 24'bX;
 assign rd1_dat = (rd1_enable) ? mem[{rd1_a0, rd1_a1, rd1_a2, rd1_a3, rd1_a4, rd1_a5}] : 24'bX;


 always @* begin
    if (wr0_enable) begin
       #10;
       if (wr0_enable) begin
          mem[{wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4, wr0_a5}] <= wr0_dat;

       end
    end
 end

endmodule