data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v
1: b'%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:121: Operator NEGATE expects 5 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                               : ... In instance BIU186_32bSync_2T_DelayRead\n wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:121: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'ISIZE\' generates 3 bits.\n                                                                                               : ... In instance BIU186_32bSync_2T_DelayRead\n wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:133: Operator ASSIGNW expects 48 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 72 bits.\n                                                                                               : ... In instance BIU186_32bSync_2T_DelayRead\n assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3\'b000};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:137: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'data_bound\' generates 1 bits.\n                                                                                               : ... In instance BIU186_32bSync_2T_DelayRead\n assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound; \n                                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:202: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                     : ... In instance BIU186_32bSync_2T_DelayRead\n   qsize <= {newqsize[4:2] + 1, newqsize[1:0]};\n                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/484316383/rtl/Next186/Next186_BIU_2T_delayread.v:202: Unsized numbers/parameters not allowed in replications.\n                                                                                                     : ... In instance BIU186_32bSync_2T_DelayRead\n   qsize <= {newqsize[4:2] + 1, newqsize[1:0]};\n                              ^\n%Error: Exiting due to 6 warning(s)\n'
module BIU186_32bSync_2T_DelayRead(
	input CLK,
	output [47:0]INSTR,
	input [2:0]ISIZE,
	input IFETCH,
	input FLUSH,
	input MREQ,
	input WR,
	input WORD,
	input [20:0]ADDR,
	input [20:0]IADDR,
	output reg CE186,
	input [31:0]RAM_DIN,
	output [31:0]RAM_DOUT,
	output [18:0]RAM_ADDR,
	output RAM_MREQ,
	output wire[3:0]RAM_WMASK,
	output reg [15:0]DOUT,
	input [15:0]DIN,
	input CE,
	output reg data_bound,
	input [1:0]WSEL,
	output reg RAM_RD,
	output reg RAM_WR,
	input IORQ,
	input FASTIO
);

	reg [31:0]queue[3:0];
	reg [1:0]STATE = 0;
	reg OLDSTATE = 1;
	reg [3:0]qpos = 0;
	reg [4:0]qsize = 0;
	reg [1:0]rpos = 0;
	reg [18:0]piaddr = 0;
	reg [7:0]exdata = 0;
	reg rdi = 0;
	
	reg [1:0]NEXTSTATE;
	reg sflush;
	wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
	wire qnofull = qsize < 13;
	reg iread;
	wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
	wire [18:0]MIADDR = sflush ? IADDR[20:2] : piaddr;
	wire split = (&ADDR[1:0]) && WORD;
	wire [15:0]DSWAP = {WSEL[1] ? DIN[15:8] : DIN[7:0], WSEL[0] ? DIN[15:8] : DIN[7:0]};
	wire [1:0]a1 = nqpos[3:2] + 1;
	wire [1:0]a2 = nqpos[3:2] + 2;
	wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
	wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];

	assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};

	assign RAM_DOUT = {DSWAP, DSWAP};
	assign RAM_MREQ = iread || RAM_RD || RAM_WR;
	assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound; 
	assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];

	always @(*) begin
		RAM_RD = 0;
		RAM_WR = 0;
		CE186 = 0;
		sflush = 0;
		data_bound = 0;
		iread = 0;
		
		case(ADDR[1:0])
			2'b00: DOUT = RAM_DIN[15:0];
			2'b01: DOUT = RAM_DIN[23:8];
			2'b10: DOUT = RAM_DIN[31:16];
			2'b11: DOUT = {RAM_DIN[7:0], WORD ? exdata : RAM_DIN[31:24]};
		endcase
		
		case(STATE)
			0: begin
				iread = qnofull;
				NEXTSTATE = 1;
			end
			1: begin
				NEXTSTATE = 1;
				if(FLUSH && IFETCH && !OLDSTATE) begin
					sflush = 1;
					iread = 1;
				end else if((FLUSH && IFETCH && (qsize > 5)) || (qsize > 11)) begin
					NEXTSTATE = 0;
					if(MREQ) begin
						if(WR) begin
							RAM_WR = 1;
							if(split) NEXTSTATE = 3;
							else CE186 = 1;
						end else begin
							RAM_RD = 1;
							NEXTSTATE = split ? 2 : 3;
						end	
					end else begin
						iread = qnofull;
						if(IORQ && !WR && !FASTIO) NEXTSTATE = 3;
						else CE186 = 1;
					end
				end else iread = 1;
			end
			2: begin
				RAM_RD = 1;
				data_bound = 1;
				NEXTSTATE = 3;
			end
			3: begin
				RAM_WR = WR && MREQ;
				iread = !(WR && MREQ) && qnofull;
				data_bound = split; 
				CE186 = 1;
				NEXTSTATE = 0;
			end
		endcase
	end
	
	always @ (posedge CLK) if(CE) begin
		rdi <= iread;
		if(rdi) queue[rpos] <= RAM_DIN;
		if(iread) begin
			qsize <= {newqsize[4:2] + 1, newqsize[1:0]};
			piaddr <= MIADDR + 1;
		end else begin
			qsize <= newqsize;
			piaddr <= MIADDR;
		end
		if(CE186 && IFETCH) qpos <= nqpos;
		if(sflush) rpos <= 0;
		else if(rdi) rpos <= rpos + 1;
		OLDSTATE <= STATE[0];
		STATE <= NEXTSTATE;
		if(data_bound) exdata <= RAM_DIN[31:24];
	end

endmodule
module BIU186_32bSync_2T_DelayRead(
	input CLK,
	output [47:0]INSTR,
	input [2:0]ISIZE,
	input IFETCH,
	input FLUSH,
	input MREQ,
	input WR,
	input WORD,
	input [20:0]ADDR,
	input [20:0]IADDR,
	output reg CE186,
	input [31:0]RAM_DIN,
	output [31:0]RAM_DOUT,
	output [18:0]RAM_ADDR,
	output RAM_MREQ,
	output wire[3:0]RAM_WMASK,
	output reg [15:0]DOUT,
	input [15:0]DIN,
	input CE,
	output reg data_bound,
	input [1:0]WSEL,
	output reg RAM_RD,
	output reg RAM_WR,
	input IORQ,
	input FASTIO
);


	reg [31:0]queue[3:0];
	reg [1:0]STATE = 0;
	reg OLDSTATE = 1;
	reg [3:0]qpos = 0;
	reg [4:0]qsize = 0;
	reg [1:0]rpos = 0;
	reg [18:0]piaddr = 0;
	reg [7:0]exdata = 0;
	reg rdi = 0;
	
	reg [1:0]NEXTSTATE;
	reg sflush;
	wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
	wire qnofull = qsize < 13;
	reg iread;
	wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
	wire [18:0]MIADDR = sflush ? IADDR[20:2] : piaddr;
	wire split = (&ADDR[1:0]) && WORD;
	wire [15:0]DSWAP = {WSEL[1] ? DIN[15:8] : DIN[7:0], WSEL[0] ? DIN[15:8] : DIN[7:0]};
	wire [1:0]a1 = nqpos[3:2] + 1;
	wire [1:0]a2 = nqpos[3:2] + 2;
	wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
	wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];

	assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};

	assign RAM_DOUT = {DSWAP, DSWAP};
	assign RAM_MREQ = iread || RAM_RD || RAM_WR;
	assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound; 
	assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];

	always @(*) begin
		RAM_RD = 0;
		RAM_WR = 0;
		CE186 = 0;
		sflush = 0;
		data_bound = 0;
		iread = 0;
		
		case(ADDR[1:0])
			2'b00: DOUT = RAM_DIN[15:0];
			2'b01: DOUT = RAM_DIN[23:8];
			2'b10: DOUT = RAM_DIN[31:16];
			2'b11: DOUT = {RAM_DIN[7:0], WORD ? exdata : RAM_DIN[31:24]};
		endcase
		
		case(STATE)
			0: begin
				iread = qnofull;
				NEXTSTATE = 1;
			end
			1: begin
				NEXTSTATE = 1;
				if(FLUSH && IFETCH && !OLDSTATE) begin
					sflush = 1;
					iread = 1;
				end else if((FLUSH && IFETCH && (qsize > 5)) || (qsize > 11)) begin
					NEXTSTATE = 0;
					if(MREQ) begin
						if(WR) begin
							RAM_WR = 1;
							if(split) NEXTSTATE = 3;
							else CE186 = 1;
						end else begin
							RAM_RD = 1;
							NEXTSTATE = split ? 2 : 3;
						end	
					end else begin
						iread = qnofull;
						if(IORQ && !WR && !FASTIO) NEXTSTATE = 3;
						else CE186 = 1;
					end
				end else iread = 1;
			end
			2: begin
				RAM_RD = 1;
				data_bound = 1;
				NEXTSTATE = 3;
			end
			3: begin
				RAM_WR = WR && MREQ;
				iread = !(WR && MREQ) && qnofull;
				data_bound = split; 
				CE186 = 1;
				NEXTSTATE = 0;
			end
		endcase
	end
	
	always @ (posedge CLK) if(CE) begin
		rdi <= iread;
		if(rdi) queue[rpos] <= RAM_DIN;
		if(iread) begin
			qsize <= {newqsize[4:2] + 1, newqsize[1:0]};
			piaddr <= MIADDR + 1;
		end else begin
			qsize <= newqsize;
			piaddr <= MIADDR;
		end
		if(CE186 && IFETCH) qpos <= nqpos;
		if(sflush) rpos <= 0;
		else if(rdi) rpos <= rpos + 1;
		OLDSTATE <= STATE[0];
		STATE <= NEXTSTATE;
		if(data_bound) exdata <= RAM_DIN[31:24];
	end

endmodule