data/full_repos/permissive/512649487/verilog/rtl/prediction.v
1: b"%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:86: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:87: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:201: syntax error, unexpected new, expecting IDENTIFIER or '=' or do or final\nreg [2:0] new;\n             ^\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:383: syntax error, unexpected new\nnew=temp;\n   ^\n%Error: Exiting due to 6 error(s)\n"
module mul_matr #(
    parameter BITS =32
) (
               input clk, 
               input [1:0] mat_sel, 
               input [1:0]adr,

               input signed [20:0] w2, 
               output reg [2:0] decision 
               );


reg signed [10:0] mem1 [2:0][2:0];
reg signed [10:0] mem2 [2:0][2:0];
reg signed [20:0] mem3 [2:0][2:0];

reg signed [20:0] mem4 [2:0][2:0];
reg signed [20:0] mem5 [2:0][2:0];
reg signed [40:0] mem6 [2:0][2:0];

integer i;
integer j;
integer k;

integer p;
integer q;

integer r;
integer s;

integer a,b,c;

integer e,f;

reg [2:0] index;

reg signed [40:0] temp;
reg [2:0] temp1;

reg [2:0] new;

always@(posedge clk)
begin







if(mat_sel==2'b00)
begin
	mem1[adr[1]][adr[0]]=w2;	
	
end
	
	
 if(mat_sel==2'b01)
		
begin
	
	mem2[adr[1]][adr[0]]=w2;	
	
end
	
	
	
if(mat_sel==2'b10)
		
begin
	mem5[adr[1]][adr[0]]=w2;	
	
end
	
	

























for (p=0;p<=1;p=p+1)begin
  
  for(q=0;q<=1;q=q+1)begin
   
	mem3[p][q]=0;
	mem6[p][q]=0;

end

  end





for (k=0;k<=1;k=k+1) begin

for (i=0; i<=1;i=i+1)begin
 
  for (j=0;j<=1;j=j+1) begin
    mem3[k][i]=mem3[k][i]+(mem1[k][j]*mem2[j][i]);

    end


end

end







for(r=0;r<=1;r=r+1)begin

  for (s=0;s<=1;s=s+1) begin
   if(mem3[r][s]<=0)
	  mem4[r][s]=0;
	else if(mem3[r][s]>=0)
	   mem4[r][s]=mem3[r][s];
   

  end

end
















for (a=0;a<=1;a=a+1) begin

for (b=0; b<=1;b=b+1)begin
 
  for (c=0;c<=1;c=c+1) begin
    mem6[a][b]=mem6[a][b]+(mem4[a][c]*mem5[c][b]);

    end


end

end




















temp=mem6[0][0];
index=0;
for (e=0;e<=1;e=e+1) begin
 
  for(f=0;f<=1;f=f+1) begin
    index=index+1;
   if (temp<=mem6[e][f]) begin
	

	  temp1=index;
	end
  else if(temp>=mem6[e][f])  begin
       
       temp=temp;
  end
	
	
end


end




new=temp;
decision=temp1;



end




endmodule
module mul_matr #(
    parameter BITS =32
) (
               input clk, 
               input [1:0] mat_sel, 
               input [1:0]adr,

               input signed [20:0] w2, 
               output reg [2:0] decision 
               );



reg signed [10:0] mem1 [2:0][2:0];
reg signed [10:0] mem2 [2:0][2:0];
reg signed [20:0] mem3 [2:0][2:0];

reg signed [20:0] mem4 [2:0][2:0];
reg signed [20:0] mem5 [2:0][2:0];
reg signed [40:0] mem6 [2:0][2:0];

integer i;
integer j;
integer k;

integer p;
integer q;

integer r;
integer s;

integer a,b,c;

integer e,f;

reg [2:0] index;

reg signed [40:0] temp;
reg [2:0] temp1;

reg [2:0] new;

always@(posedge clk)
begin







if(mat_sel==2'b00)
begin
	mem1[adr[1]][adr[0]]=w2;	
	
end
	
	
 if(mat_sel==2'b01)
		
begin
	
	mem2[adr[1]][adr[0]]=w2;	
	
end
	
	
	
if(mat_sel==2'b10)
		
begin
	mem5[adr[1]][adr[0]]=w2;	
	
end
	
	

























for (p=0;p<=1;p=p+1)begin
  
  for(q=0;q<=1;q=q+1)begin
   
	mem3[p][q]=0;
	mem6[p][q]=0;

end

  end





for (k=0;k<=1;k=k+1) begin

for (i=0; i<=1;i=i+1)begin
 
  for (j=0;j<=1;j=j+1) begin
    mem3[k][i]=mem3[k][i]+(mem1[k][j]*mem2[j][i]);

    end


end

end







for(r=0;r<=1;r=r+1)begin

  for (s=0;s<=1;s=s+1) begin
   if(mem3[r][s]<=0)
	  mem4[r][s]=0;
	else if(mem3[r][s]>=0)
	   mem4[r][s]=mem3[r][s];
   

  end

end
















for (a=0;a<=1;a=a+1) begin

for (b=0; b<=1;b=b+1)begin
 
  for (c=0;c<=1;c=c+1) begin
    mem6[a][b]=mem6[a][b]+(mem4[a][c]*mem5[c][b]);

    end


end

end




















temp=mem6[0][0];
index=0;
for (e=0;e<=1;e=e+1) begin
 
  for(f=0;f<=1;f=f+1) begin
    index=index+1;
   if (temp<=mem6[e][f]) begin
	

	  temp1=index;
	end
  else if(temp>=mem6[e][f])  begin
       
       temp=temp;
  end
	
	
end


end




new=temp;
decision=temp1;



end




endmodule