data/full_repos/permissive/529394000/src/ddr_clocking.v
1: b'%Error: data/full_repos/permissive/529394000/src/ddr_clocking.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/529394000/src,data/full_repos/permissive/529394000/defines.v\n             data/full_repos/permissive/529394000/src,data/full_repos/permissive/529394000/defines.v.v\n             data/full_repos/permissive/529394000/src,data/full_repos/permissive/529394000/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ddr_clocking
    (
    input               clk,
	input			    rst,
    input       [3:0]   psda,
    input       [3:0]   fdly,

    output              clk_ddrMain,
    output              clk_ddrWrite,
    output              clk_ddrRead,
    output              clk_ddrClient,
    output              clk_ddrMgmt,

    output              locked
	);


    wire [3:0] duty = psda + 4'b1000;     

    wire lock_pll1;
    pll_ddr1 ddr1_inst
        (
        .clkin(clk),
        .reset(rst),

        .clkout(clk_ddrMain),
        .clkoutp(clk_ddrRead),
        .clkoutd(clk_ddrClient),
        
        .psda(psda),
        .dutyda(duty),
        .fdly(fdly),

		.lock(lock_pll1)
        );
    
    wire lock_pll2;
    wire dummyClock;
    pll_ddr2 ddr2_inst
        (
        .clkin(clk),
        .reset(rst),

        .clkout(dummyClock),
        .clkoutp(clk_ddrWrite),
        .clkoutd(clk_ddrMgmt),

        .lock(lock_pll2)
        );
    
    assign locked = lock_pll1 & lock_pll2;

endmodule
module ddr_clocking
    (
    input               clk,
	input			    rst,
    input       [3:0]   psda,
    input       [3:0]   fdly,

    output              clk_ddrMain,
    output              clk_ddrWrite,
    output              clk_ddrRead,
    output              clk_ddrClient,
    output              clk_ddrMgmt,

    output              locked
	);



    wire [3:0] duty = psda + 4'b1000;     

    wire lock_pll1;
    pll_ddr1 ddr1_inst
        (
        .clkin(clk),
        .reset(rst),

        .clkout(clk_ddrMain),
        .clkoutp(clk_ddrRead),
        .clkoutd(clk_ddrClient),
        
        .psda(psda),
        .dutyda(duty),
        .fdly(fdly),

		.lock(lock_pll1)
        );
    
    wire lock_pll2;
    wire dummyClock;
    pll_ddr2 ddr2_inst
        (
        .clkin(clk),
        .reset(rst),

        .clkout(dummyClock),
        .clkoutp(clk_ddrWrite),
        .clkoutd(clk_ddrMgmt),

        .lock(lock_pll2)
        );
    
    assign locked = lock_pll1 & lock_pll2;

endmodule