data/full_repos/permissive/517239653/square_wave.v
1: b"%Error: data/full_repos/permissive/517239653/square_wave.v:13: Cannot find file containing module: 'divider'\ndivider CLK_DIV(dac_clk, clk, clk_div);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.v\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Error: Exiting due to 1 error(s)\n"
module square_wave(dac_out, clk, clk_div, duty_cycle);

parameter DUTY_CYCLE_BITS = 9;
output reg [7:0] dac_out;
input clk;
input [31:0] clk_div;
input [DUTY_CYCLE_BITS-1:0] duty_cycle;

wire dac_clk;
reg [DUTY_CYCLE_BITS-1:0] counter;


divider CLK_DIV(dac_clk, clk, clk_div);

always @(dac_clk) begin
    counter <= counter + 1;

    if(counter < duty_cycle) begin
        dac_out <= 8'hFF;
    end else begin
        dac_out <= 8'h00;
    end
    
    if (counter == ((1 << DUTY_CYCLE_BITS) - 1)) begin
        counter <= 0;
    end
end

endmodule
module square_wave(dac_out, clk, clk_div, duty_cycle);


parameter DUTY_CYCLE_BITS = 9;
output reg [7:0] dac_out;
input clk;
input [31:0] clk_div;
input [DUTY_CYCLE_BITS-1:0] duty_cycle;

wire dac_clk;
reg [DUTY_CYCLE_BITS-1:0] counter;


divider CLK_DIV(dac_clk, clk, clk_div);

always @(dac_clk) begin
    counter <= counter + 1;

    if(counter < duty_cycle) begin
        dac_out <= 8'hFF;
    end else begin
        dac_out <= 8'h00;
    end
    
    if (counter == ((1 << DUTY_CYCLE_BITS) - 1)) begin
        counter <= 0;
    end
end

endmodule