data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module MemWB(clock, mWREG, mM2REG, mMUX, mALU, mDM);
    input clock, mWREG, mM2REG;
    input [4:0] mMUX;
    input [31:0] mALU, mDM; 

    reg mwreg,mm2reg;
    reg [4:0] mmux;
    reg [31:0] malu,mdm;

    always @(posedge clock) begin
        mwreg <= mWREG;
        mm2reg <= mM2REG;
        mmux <= mMUX;
        malu <= mALU;
        mdm <= mDM;
    end
endmodule
module MemWB(clock, mWREG, mM2REG, mMUX, mALU, mDM);

    input clock, mWREG, mM2REG;
    input [4:0] mMUX;
    input [31:0] mALU, mDM; 

    reg mwreg,mm2reg;
    reg [4:0] mmux;
    reg [31:0] malu,mdm;

    always @(posedge clock) begin
        mwreg <= mWREG;
        mm2reg <= mM2REG;
        mmux <= mMUX;
        malu <= mALU;
        mdm <= mDM;
    end
endmodule