data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 3 bits.\n                                                                                                          : ... In instance Legalize.u_pad_2\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                          : ... In instance Legalize.u_pad_4\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 17 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 16 bits.\n                                                                                                          : ... In instance Legalize.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:18: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                          : ... In instance Legalize\n        .a(1\'d0),\n         ^\n%Error: Exiting due to 4 warning(s)\n'
module NEQ_UNSIGNED(y, a, b);
    parameter width = 4;
    output y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a != b;
endmodule
module NEQ_UNSIGNED(y, a, b);

    parameter width = 4;
    output y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a != b;
endmodule