data/full_repos/permissive/506186384/project-files/lab6/InstrMemory.v
data/verilator_xmls/a40ff6a3-c84a-40e8-b304-32a9a853cad8.xml
module InstrMemory(
    input [31:0] Address,
    output [31:0] ReadInstr
    );
    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    always @ (Address)
        begin
           rd = MemFile[Address>>2];
        end
        
    assign ReadInstr = rd;
    
endmodule
module InstrMemory(
    input [31:0] Address,
    output [31:0] ReadInstr
    );

    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    always @ (Address)
        begin
           rd = MemFile[Address>>2];
        end
        
    assign ReadInstr = rd;
    
endmodule