data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:2: Cannot find include file: syn_tb_defines.vh\n`include "syn_tb_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.sv\n             syn_tb_defines.vh\n             syn_tb_defines.vh.v\n             syn_tb_defines.vh.sv\n             obj_dir/syn_tb_defines.vh\n             obj_dir/syn_tb_defines.vh.v\n             obj_dir/syn_tb_defines.vh.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:27: Define or directive not defined: \'`DLA_ADDR_START\'\nparameter MEM_ADDR_START=`DLA_ADDR_START;  \n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter MEM_ADDR_START=`DLA_ADDR_START;  \n                                        ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:30: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\ninput [`AXI_ADDR_WIDTH-1:0]  slave2mem_addr;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:33: Define or directive not defined: \'`WORD_SIZE\'\noutput reg [`WORD_SIZE-1:0] mem2slave_rdresp_data;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:34: Define or directive not defined: \'`AXI_LEN_WIDTH\'\ninput [`AXI_LEN_WIDTH-1:0]  slave2mem_len;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:35: Define or directive not defined: \'`AXI_SIZE_WIDTH\'\ninput [`AXI_SIZE_WIDTH-1:0]  slave2mem_size;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:36: Define or directive not defined: \'`LOG2_Q\'\noutput [`LOG2_Q-1:0] curr_tail;\n        ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:38: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\noutput [`AXI_ADDR_WIDTH-1-`LOG2_MEM:0] curr_rd_addr;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:38: Define or directive not defined: \'`LOG2_MEM\'\noutput [`AXI_ADDR_WIDTH-1-`LOG2_MEM:0] curr_rd_addr;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput [`AXI_ADDR_WIDTH-1-`LOG2_MEM:0] curr_rd_addr;\n                                   ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:39: Define or directive not defined: \'`AXI_LEN_WIDTH\'\noutput [`AXI_LEN_WIDTH-1:0] curr_rd_len;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:40: Define or directive not defined: \'`WORD_SIZE\'\ninput [`WORD_SIZE-1:0] mem2slave_rdresp_data_tmp;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:43: Define or directive not defined: \'`MSEQ_CONFIG_SIZE\'\nreg [`MSEQ_CONFIG_SIZE-1:0]            config_mem[`NUM_CONFIGS-1:0];\n     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:43: Define or directive not defined: \'`NUM_CONFIGS\'\nreg [`MSEQ_CONFIG_SIZE-1:0]            config_mem[`NUM_CONFIGS-1:0];\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:44: Define or directive not defined: \'`AXI_LEN_WIDTH\'\nreg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:44: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\nreg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:44: Define or directive not defined: \'`LOG2_MEM\'\nreg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:44: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];\n                                             ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:44: Define or directive not defined: \'`QUEUE_SIZE\'\nreg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];\n                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:45: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] s_read_head;\n     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:46: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] s_read_tail;\n     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:47: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] s_read_count;\n     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:48: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] len_count;\n     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:49: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] s_read_count_inc;\n     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:51: Define or directive not defined: \'`LOG2_Q\'\nwire [`LOG2_Q-1:0] s_read_latency;  \n      ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:56: Define or directive not defined: \'`RD_ADDR_RANGE\'\nassign curr_rd_addr = s_read_q [s_read_tail] [`RD_ADDR_RANGE] - (MEM_ADDR_START >> `LOG2_MEM);\n                                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign curr_rd_addr = s_read_q [s_read_tail] [`RD_ADDR_RANGE] - (MEM_ADDR_START >> `LOG2_MEM);\n                                                            ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:56: Define or directive not defined: \'`LOG2_MEM\'\nassign curr_rd_addr = s_read_q [s_read_tail] [`RD_ADDR_RANGE] - (MEM_ADDR_START >> `LOG2_MEM);\n                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:57: Define or directive not defined: \'`RD_LEN_RANGE\'\nassign curr_rd_len  = s_read_q [s_read_tail] [`RD_LEN_RANGE];\n                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign curr_rd_len  = s_read_q [s_read_tail] [`RD_LEN_RANGE];\n                                                           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:58: Define or directive not defined: \'`S0_READ_LATENCY\'\nassign s_read_latency  = config_mem[`S0_READ_LATENCY] - `READ_LATENCY_CORRECTION;  \n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign s_read_latency  = config_mem[`S0_READ_LATENCY] - `READ_LATENCY_CORRECTION;  \n                                                    ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:58: Define or directive not defined: \'`READ_LATENCY_CORRECTION\'\nassign s_read_latency  = config_mem[`S0_READ_LATENCY] - `READ_LATENCY_CORRECTION;  \n                                                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:59: Define or directive not defined: \'`RD_VALID\'\nassign s_read_q_tail_valid = s_read_q[s_read_tail][`RD_VALID];\n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign s_read_q_tail_valid = s_read_q[s_read_tail][`RD_VALID];\n                                                            ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:75: Define or directive not defined: \'`QUEUE_SIZE\'\n        for (i=0; i<`QUEUE_SIZE; i=i+1) begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for (i=0; i<`QUEUE_SIZE; i=i+1) begin\n                               ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:75: syntax error, unexpected \')\', expecting \';\'\n        for (i=0; i<`QUEUE_SIZE; i=i+1) begin\n                                      ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:76: Define or directive not defined: \'`RD_VALID\'\n            s_read_q[i][`RD_VALID] <= 1\'b0;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:78: syntax error, unexpected else\n    end else begin\n        ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:79: Define or directive not defined: \'`QUEUE_SIZE\'\n        if( modSub(s_read_head, s_read_tail, `QUEUE_SIZE) > s_read_latency) begin\n                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:87: Define or directive not defined: \'`RD_VALID\'\n            if( s_read_q[s_read_head][`RD_VALID]) begin\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:92: Define or directive not defined: \'`QUEUE_SIZE\'\n                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1\'b1};\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:92: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1\'b1};\n                                                                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:92: Define or directive not defined: \'`LOG2_MEM\'\n                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1\'b1};\n                                                                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:92: Define or directive not defined: \'`LOG2_MEM\'\n                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1\'b1};\n                                                                                                                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:93: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                  $display("%0t SMEM: Received slave %0d read addr 0x%010x len %d size %d, temp_mem_addr 0x%010x", $time, AXI_SLAVE_ID, slave2mem_addr+i*(1<<slave2mem_size), slave2mem_len, slave2mem_size, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM));  \n                                                                                                                                                                                                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:93: Define or directive not defined: \'`LOG2_MEM\'\n                  $display("%0t SMEM: Received slave %0d read addr 0x%010x len %d size %d, temp_mem_addr 0x%010x", $time, AXI_SLAVE_ID, slave2mem_addr+i*(1<<slave2mem_size), slave2mem_len, slave2mem_size, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM));  \n                                                                                                                                                                                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/slave2mem_rd.v:93: Define or directive not defined: \'`LOG2_MEM\'\n                  $display("%0t SMEM: Received slave %0d read addr 0x%010x len %d size %d, temp_mem_addr 0x%010x", $time, AXI_SLAVE_ID, slave2mem_addr+i*(1<<slave2mem_size), slave2mem_len, slave2mem_size, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM));  \n                                                                                                                                                                                                                                                                                   ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module slave2mem_rd (
    clk,
    reset,
   
    slave2mem_cmd_rd,
    slave2mem_addr,
    slave2mem_len,
    slave2mem_size,
    mem2slave_rd_ready,
    mem2slave_rdresp_vld,
    mem2slave_rdresp_data,
    s_read_q_tail_valid,
    curr_tail,
    curr_rd_addr,
    curr_rd_len,
    mem2slave_rdresp_data_tmp,
    rdresp_data_ready
);

input clk;
input reset;
parameter AXI_SLAVE_ID=0;
parameter MEM_ADDR_START=`DLA_ADDR_START;

input         slave2mem_cmd_rd;
input [`AXI_ADDR_WIDTH-1:0]  slave2mem_addr;
output reg    mem2slave_rd_ready;
output reg    mem2slave_rdresp_vld;
output reg [`WORD_SIZE-1:0] mem2slave_rdresp_data;
input [`AXI_LEN_WIDTH-1:0]  slave2mem_len;
input [`AXI_SIZE_WIDTH-1:0]  slave2mem_size;
output [`LOG2_Q-1:0] curr_tail;
output  s_read_q_tail_valid;
output [`AXI_ADDR_WIDTH-1-`LOG2_MEM:0] curr_rd_addr;
output [`AXI_LEN_WIDTH-1:0] curr_rd_len;
input [`WORD_SIZE-1:0] mem2slave_rdresp_data_tmp;
input rdresp_data_ready;

reg [`MSEQ_CONFIG_SIZE-1:0]            config_mem[`NUM_CONFIGS-1:0];
reg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];
reg [`LOG2_Q-1:0] s_read_head;
reg [`LOG2_Q-1:0] s_read_tail;
reg [`LOG2_Q-1:0] s_read_count;
reg [`LOG2_Q-1:0] len_count;
reg [`LOG2_Q-1:0] s_read_count_inc;
reg s_read_count_dec;
wire [`LOG2_Q-1:0] s_read_latency;
integer i;
reg carry_out;

assign curr_tail = s_read_tail;
assign curr_rd_addr = s_read_q [s_read_tail] [`RD_ADDR_RANGE] - (MEM_ADDR_START >> `LOG2_MEM);
assign curr_rd_len  = s_read_q [s_read_tail] [`RD_LEN_RANGE];
assign s_read_latency  = config_mem[`S0_READ_LATENCY] - `READ_LATENCY_CORRECTION;
assign s_read_q_tail_valid = s_read_q[s_read_tail][`RD_VALID];


initial begin
    $readmemh("slave_mem.cfg", config_mem);
end

always @(posedge clk or negedge reset) begin
    if( !reset) begin
        mem2slave_rd_ready  <= 1;
        mem2slave_rdresp_vld<= 0;
        s_read_head         <= s_read_latency;
        s_read_tail         <= 0;
        s_read_count        <= 0;
        s_read_count_inc    <= 0;
        s_read_count_dec    <= 0;
        for (i=0; i<`QUEUE_SIZE; i=i+1) begin
            s_read_q[i][`RD_VALID] <= 1'b0;
        end
    end else begin
        if( modSub(s_read_head, s_read_tail, `QUEUE_SIZE) > s_read_latency) begin
            mem2slave_rd_ready  <= 0;
        end else begin
            mem2slave_rd_ready  <= 1;
        end


        if( slave2mem_cmd_rd) begin
            if( s_read_q[s_read_head][`RD_VALID]) begin
                $display("%0t SMEM: ERROR: Slave %0d read head detected unread entry! Commands are probably getting dropped.", $time, AXI_SLAVE_ID);
                $finish;
            end else begin
                for( i=0; i<1+slave2mem_len; i++) begin
                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1'b1};
                  $display("%0t SMEM: Received slave %0d read addr 0x%010x len %d size %d, temp_mem_addr 0x%010x", $time, AXI_SLAVE_ID, slave2mem_addr+i*(1<<slave2mem_size), slave2mem_len, slave2mem_size, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM));
                end
		s_read_head <= modAdd(s_read_head, 1 + slave2mem_len, `QUEUE_SIZE);

                s_read_count_inc <= 1 + slave2mem_len;
            end

        end else begin
            s_read_count_inc <= 0;
            if( modSub(s_read_head, s_read_tail, `QUEUE_SIZE) <= s_read_latency) begin
                s_read_head <= modAdd(s_read_tail, s_read_latency, `QUEUE_SIZE);
            end
        end

        if( s_read_q[s_read_tail][`RD_VALID] == 1'b1 ) begin
            if( rdresp_data_ready) begin
                mem2slave_rdresp_vld <= 1;
                mem2slave_rdresp_data <= mem2slave_rdresp_data_tmp;
                $display("%0t SMEM: Slave %0d read address 0x%010x (mem address 0x%x) data 0x%0128x", $time, AXI_SLAVE_ID, ((`AXI_ADDR_WIDTH'b0 + curr_rd_addr) * `MEM_BYTES) + MEM_ADDR_START, curr_rd_addr, mem2slave_rdresp_data_tmp);
                s_read_q[s_read_tail][`RD_VALID] <= 1'b0;
                s_read_count_dec <= 1;
                s_read_tail <= modAdd(s_read_tail, 1'd1, `QUEUE_SIZE);
           end else begin
                mem2slave_rdresp_vld <= 0;
                s_read_count_dec <= 0;
           end
        end else begin
            mem2slave_rdresp_vld <= 0;
            s_read_count_dec <= 0;
            s_read_tail <= modAdd(s_read_tail, 1'd1, `QUEUE_SIZE);
        end




        {carry_out,s_read_count}  <= s_read_count  + s_read_count_inc  - s_read_count_dec;
    end
end

assert_module a2 (.clk(clk), .test(carry_out));

always @* begin
    if( (s_read_head == s_read_tail) && reset )
        $display("%0t SMEM: ERROR: Slave %0d read head caught up to read tail! Commands are probably getting dropped.", $time, AXI_SLAVE_ID);
end


function [`LOG2_Q-1:0] modAdd;
     input [`LOG2_Q-1:0] x;
     input [`LOG2_Q-1:0] delta;
     input [`LOG2_Q:0] wrapSize;

begin
     modAdd = (x + delta) % wrapSize;
end

endfunction


function [`LOG2_Q-1:0] modSub;
     input [`LOG2_Q-1:0] x;
     input [`LOG2_Q-1:0] delta;
     input [`LOG2_Q:0] wrapSize;

begin
     modSub = (x - delta) % wrapSize;
end

endfunction

endmodule
module slave2mem_rd (
    clk,
    reset,
   
    slave2mem_cmd_rd,
    slave2mem_addr,
    slave2mem_len,
    slave2mem_size,
    mem2slave_rd_ready,
    mem2slave_rdresp_vld,
    mem2slave_rdresp_data,
    s_read_q_tail_valid,
    curr_tail,
    curr_rd_addr,
    curr_rd_len,
    mem2slave_rdresp_data_tmp,
    rdresp_data_ready
);


input clk;
input reset;
parameter AXI_SLAVE_ID=0;
parameter MEM_ADDR_START=`DLA_ADDR_START;

input         slave2mem_cmd_rd;
input [`AXI_ADDR_WIDTH-1:0]  slave2mem_addr;
output reg    mem2slave_rd_ready;
output reg    mem2slave_rdresp_vld;
output reg [`WORD_SIZE-1:0] mem2slave_rdresp_data;
input [`AXI_LEN_WIDTH-1:0]  slave2mem_len;
input [`AXI_SIZE_WIDTH-1:0]  slave2mem_size;
output [`LOG2_Q-1:0] curr_tail;
output  s_read_q_tail_valid;
output [`AXI_ADDR_WIDTH-1-`LOG2_MEM:0] curr_rd_addr;
output [`AXI_LEN_WIDTH-1:0] curr_rd_len;
input [`WORD_SIZE-1:0] mem2slave_rdresp_data_tmp;
input rdresp_data_ready;

reg [`MSEQ_CONFIG_SIZE-1:0]            config_mem[`NUM_CONFIGS-1:0];
reg [`AXI_LEN_WIDTH+`AXI_ADDR_WIDTH-`LOG2_MEM:0] s_read_q [`QUEUE_SIZE-1:0];
reg [`LOG2_Q-1:0] s_read_head;
reg [`LOG2_Q-1:0] s_read_tail;
reg [`LOG2_Q-1:0] s_read_count;
reg [`LOG2_Q-1:0] len_count;
reg [`LOG2_Q-1:0] s_read_count_inc;
reg s_read_count_dec;
wire [`LOG2_Q-1:0] s_read_latency;
integer i;
reg carry_out;

assign curr_tail = s_read_tail;
assign curr_rd_addr = s_read_q [s_read_tail] [`RD_ADDR_RANGE] - (MEM_ADDR_START >> `LOG2_MEM);
assign curr_rd_len  = s_read_q [s_read_tail] [`RD_LEN_RANGE];
assign s_read_latency  = config_mem[`S0_READ_LATENCY] - `READ_LATENCY_CORRECTION;
assign s_read_q_tail_valid = s_read_q[s_read_tail][`RD_VALID];


initial begin
    $readmemh("slave_mem.cfg", config_mem);
end

always @(posedge clk or negedge reset) begin
    if( !reset) begin
        mem2slave_rd_ready  <= 1;
        mem2slave_rdresp_vld<= 0;
        s_read_head         <= s_read_latency;
        s_read_tail         <= 0;
        s_read_count        <= 0;
        s_read_count_inc    <= 0;
        s_read_count_dec    <= 0;
        for (i=0; i<`QUEUE_SIZE; i=i+1) begin
            s_read_q[i][`RD_VALID] <= 1'b0;
        end
    end else begin
        if( modSub(s_read_head, s_read_tail, `QUEUE_SIZE) > s_read_latency) begin
            mem2slave_rd_ready  <= 0;
        end else begin
            mem2slave_rd_ready  <= 1;
        end


        if( slave2mem_cmd_rd) begin
            if( s_read_q[s_read_head][`RD_VALID]) begin
                $display("%0t SMEM: ERROR: Slave %0d read head detected unread entry! Commands are probably getting dropped.", $time, AXI_SLAVE_ID);
                $finish;
            end else begin
                for( i=0; i<1+slave2mem_len; i++) begin
                  s_read_q[modAdd(s_read_head, i, `QUEUE_SIZE)] <= {slave2mem_len, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM), 1'b1};
                  $display("%0t SMEM: Received slave %0d read addr 0x%010x len %d size %d, temp_mem_addr 0x%010x", $time, AXI_SLAVE_ID, slave2mem_addr+i*(1<<slave2mem_size), slave2mem_len, slave2mem_size, slave2mem_addr[`AXI_ADDR_WIDTH-1:`LOG2_MEM] + i*((1<<slave2mem_size)>>`LOG2_MEM));
                end
		s_read_head <= modAdd(s_read_head, 1 + slave2mem_len, `QUEUE_SIZE);

                s_read_count_inc <= 1 + slave2mem_len;
            end

        end else begin
            s_read_count_inc <= 0;
            if( modSub(s_read_head, s_read_tail, `QUEUE_SIZE) <= s_read_latency) begin
                s_read_head <= modAdd(s_read_tail, s_read_latency, `QUEUE_SIZE);
            end
        end

        if( s_read_q[s_read_tail][`RD_VALID] == 1'b1 ) begin
            if( rdresp_data_ready) begin
                mem2slave_rdresp_vld <= 1;
                mem2slave_rdresp_data <= mem2slave_rdresp_data_tmp;
                $display("%0t SMEM: Slave %0d read address 0x%010x (mem address 0x%x) data 0x%0128x", $time, AXI_SLAVE_ID, ((`AXI_ADDR_WIDTH'b0 + curr_rd_addr) * `MEM_BYTES) + MEM_ADDR_START, curr_rd_addr, mem2slave_rdresp_data_tmp);
                s_read_q[s_read_tail][`RD_VALID] <= 1'b0;
                s_read_count_dec <= 1;
                s_read_tail <= modAdd(s_read_tail, 1'd1, `QUEUE_SIZE);
           end else begin
                mem2slave_rdresp_vld <= 0;
                s_read_count_dec <= 0;
           end
        end else begin
            mem2slave_rdresp_vld <= 0;
            s_read_count_dec <= 0;
            s_read_tail <= modAdd(s_read_tail, 1'd1, `QUEUE_SIZE);
        end




        {carry_out,s_read_count}  <= s_read_count  + s_read_count_inc  - s_read_count_dec;
    end
end

assert_module a2 (.clk(clk), .test(carry_out));

always @* begin
    if( (s_read_head == s_read_tail) && reset )
        $display("%0t SMEM: ERROR: Slave %0d read head caught up to read tail! Commands are probably getting dropped.", $time, AXI_SLAVE_ID);
end


function [`LOG2_Q-1:0] modAdd;
     input [`LOG2_Q-1:0] x;
     input [`LOG2_Q-1:0] delta;
     input [`LOG2_Q:0] wrapSize;

begin
     modAdd = (x + delta) % wrapSize;
end

endfunction


function [`LOG2_Q-1:0] modSub;
     input [`LOG2_Q-1:0] x;
     input [`LOG2_Q-1:0] delta;
     input [`LOG2_Q:0] wrapSize;

begin
     modSub = (x - delta) % wrapSize;
end

endfunction

endmodule