data/full_repos/permissive/531341619/rtl/fp32_adder_dual_alignment_stage.v
data/verilator_xmls/9082e71d-14c9-4d4a-9070-8adb176ffe6c.xml
module fp32_adder_dual_alignment_stage
#(
  parameter EXPONENT_WIDTH = 8,
  parameter MANTISA_WIDTH = 24
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH:0] exponent_diff_0, exponent_diff_1,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_big_0_in, exponent_big_1_in,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_0_in, mantissa_small_0,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_1_in, mantissa_small_1,
  
  output reg  [EXPONENT_WIDTH-1:0] exponent_big_0_out, exponent_big_1_out,
  output reg  [MANTISA_WIDTH-1:0] mantissa_big_0_out, mantissa_aligned_0,
  output reg  [MANTISA_WIDTH-1:0] mantissa_big_1_out, mantissa_aligned_1
);

  always @(posedge clk)
  begin
    mantissa_aligned_0 <= mantissa_small_0 >>> exponent_diff_0;
    mantissa_aligned_1 <= mantissa_small_1 >>> exponent_diff_1;
    mantissa_big_0_out <= mantissa_big_0_in;
    mantissa_big_1_out <= mantissa_big_1_in;
    exponent_big_0_out <= exponent_big_0_in;
    exponent_big_1_out <= exponent_big_1_in;
  end
endmodule
module fp32_adder_dual_alignment_stage
#(
  parameter EXPONENT_WIDTH = 8,
  parameter MANTISA_WIDTH = 24
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH:0] exponent_diff_0, exponent_diff_1,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_big_0_in, exponent_big_1_in,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_0_in, mantissa_small_0,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_1_in, mantissa_small_1,
  
  output reg  [EXPONENT_WIDTH-1:0] exponent_big_0_out, exponent_big_1_out,
  output reg  [MANTISA_WIDTH-1:0] mantissa_big_0_out, mantissa_aligned_0,
  output reg  [MANTISA_WIDTH-1:0] mantissa_big_1_out, mantissa_aligned_1
);


  always @(posedge clk)
  begin
    mantissa_aligned_0 <= mantissa_small_0 >>> exponent_diff_0;
    mantissa_aligned_1 <= mantissa_small_1 >>> exponent_diff_1;
    mantissa_big_0_out <= mantissa_big_0_in;
    mantissa_big_1_out <= mantissa_big_1_in;
    exponent_big_0_out <= exponent_big_0_in;
    exponent_big_1_out <= exponent_big_1_in;
  end
endmodule