data/full_repos/permissive/418819021/lab-05/test_ret.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:13: Define or directive not defined: \'`STAGE_IF\'\n   `STAGE_IF: begin\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:13: syntax error, unexpected \':\', expecting endcase\n   `STAGE_IF: begin\n            ^\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:16: Define or directive not defined: \'`STAGE_ID\'\n   `STAGE_ID:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:18: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    if(!uut.control.opcode_type == `TYPE_RET) begin \n    ^~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:18: Define or directive not defined: \'`TYPE_RET\'\n    if(!uut.control.opcode_type == `TYPE_RET) begin \n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:19: Define or directive not defined: \'`TYPE_RET\'\n     $display("RET - ID: FAILED %d vs %d", `TYPE_RET, uut.control.opcode_type);\n                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:22: syntax error, unexpected else\n    else if(!uut.control.opcode_group[`GROUP_TWO_CYCLE_MEM]) begin \n    ^~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:22: Define or directive not defined: \'`GROUP_TWO_CYCLE_MEM\'\n    else if(!uut.control.opcode_group[`GROUP_TWO_CYCLE_MEM]) begin \n                                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:25: syntax error, unexpected end\n    end \n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:26: Define or directive not defined: \'`GROUP_STACK\'\n    else if (!uut.control.opcode_group[`GROUP_STACK]) begin \n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:29: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:30: Define or directive not defined: \'`GROUP_CONTROL_FLOW\'\n    else if (!uut.control.opcode_group[`GROUP_CONTROL_FLOW]) begin \n                                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:33: syntax error, unexpected end\n    end  \n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:34: Define or directive not defined: \'`GROUP_LOAD_INDIRECT\'\n    else if (!uut.control.opcode_group[`GROUP_LOAD_INDIRECT]) begin \n                                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:37: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:41: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:44: Define or directive not defined: \'`STAGE_EX\'\n   `STAGE_EX:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:45: Define or directive not defined: \'`CONTROL_STACK_PREINC\'\n    if(!uut.control.signals[`CONTROL_STACK_PREINC]) begin \n                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:48: syntax error, unexpected end\n    end \n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:52: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:54: Define or directive not defined: \'`STAGE_MEM\'\n   `STAGE_MEM:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:55: Define or directive not defined: \'`CONTROL_STACK_PREINC\'\n    if(!uut.control.signals[`CONTROL_STACK_PREINC] \n                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:59: syntax error, unexpected end\n    end \n    ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:63: Define or directive not defined: \'`STAGE_WB\'\n   `STAGE_WB: begin  \n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_ret.vh:67: syntax error, unexpected end\n    end  \n    ^~~\n%Error: Cannot continue\n'
function TEST_RET;
	input integer value;
	input integer saved_pc;
	input integer expected_pc;
	begin
		
		case (uut.pipeline_stage)
			`STAGE_IF: begin
				TEST_RET = 1'b1;
			end
			`STAGE_ID:

				if(!uut.control.opcode_type == `TYPE_RET) begin 
					$display("RET - ID: FAILED %d vs %d", `TYPE_RET, uut.control.opcode_type);
					TEST_RET = 1'bx;
				end 
				else if(!uut.control.opcode_group[`GROUP_TWO_CYCLE_MEM]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_TWO_CYCLE_MEM");
					TEST_RET = 1'bx;
				end 
				else if (!uut.control.opcode_group[`GROUP_STACK]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_STACK");
					TEST_RET = 1'bx;
				end
				else if (!uut.control.opcode_group[`GROUP_CONTROL_FLOW]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_CONTROL_FLOW");
					TEST_RET = 1'bx;
				end  
				else if (!uut.control.opcode_group[`GROUP_LOAD_INDIRECT]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_LOAD_INDIRECT");
					TEST_RET = 1'bx;
				end
				else begin 
					$display("RET - ID: OK");
					TEST_RET = 1'b1;
				end
				
				
			`STAGE_EX:
				if(!uut.control.signals[`CONTROL_STACK_PREINC]) begin 
					$display("RET - EX: FAILED. signal CONTROL_STACK_PREINC should be active");
					TEST_RET = 1'bx;
				end 
				else begin 
					$display("RET - EX: OK");
					TEST_RET = 1'b1;
				end
				
			`STAGE_MEM:
				if(!uut.control.signals[`CONTROL_STACK_PREINC] 
				&& (uut.control.cycle_count == 0)) begin 
					$display("RET - MEM: cycle_count 0, FAILED. signal CONTROL_STACK_PREINC should be active");
					TEST_RET = 1'bx;
				end 
				else begin 
					TEST_RET = 1'b1;
				end
			`STAGE_WB: begin
				if (!(uut.control.saved_pc === saved_pc)) begin 
					$display("RET - MEM: FAILED: saved_pc => %d vs %d", saved_pc, uut.control.saved_pc);
					TEST_RET = 1'bx;
				end  
				else begin
					TEST_RET = 1'b1;
				end
			end
				
		endcase
	end
endfunction
function TEST_RET;

	input integer value;
	input integer saved_pc;
	input integer expected_pc;
	begin
		
		case (uut.pipeline_stage)
			`STAGE_IF: begin
				TEST_RET = 1'b1;
			end
			`STAGE_ID:

				if(!uut.control.opcode_type == `TYPE_RET) begin 
					$display("RET - ID: FAILED %d vs %d", `TYPE_RET, uut.control.opcode_type);
					TEST_RET = 1'bx;
				end 
				else if(!uut.control.opcode_group[`GROUP_TWO_CYCLE_MEM]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_TWO_CYCLE_MEM");
					TEST_RET = 1'bx;
				end 
				else if (!uut.control.opcode_group[`GROUP_STACK]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_STACK");
					TEST_RET = 1'bx;
				end
				else if (!uut.control.opcode_group[`GROUP_CONTROL_FLOW]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_CONTROL_FLOW");
					TEST_RET = 1'bx;
				end  
				else if (!uut.control.opcode_group[`GROUP_LOAD_INDIRECT]) begin 
					$display("RET - ID: FAILED. RET instruction should be in GROUP_LOAD_INDIRECT");
					TEST_RET = 1'bx;
				end
				else begin 
					$display("RET - ID: OK");
					TEST_RET = 1'b1;
				end
				
				
			`STAGE_EX:
				if(!uut.control.signals[`CONTROL_STACK_PREINC]) begin 
					$display("RET - EX: FAILED. signal CONTROL_STACK_PREINC should be active");
					TEST_RET = 1'bx;
				end 
				else begin 
					$display("RET - EX: OK");
					TEST_RET = 1'b1;
				end
				
			`STAGE_MEM:
				if(!uut.control.signals[`CONTROL_STACK_PREINC] 
				&& (uut.control.cycle_count == 0)) begin 
					$display("RET - MEM: cycle_count 0, FAILED. signal CONTROL_STACK_PREINC should be active");
					TEST_RET = 1'bx;
				end 
				else begin 
					TEST_RET = 1'b1;
				end
			`STAGE_WB: begin
				if (!(uut.control.saved_pc === saved_pc)) begin 
					$display("RET - MEM: FAILED: saved_pc => %d vs %d", saved_pc, uut.control.saved_pc);
					TEST_RET = 1'bx;
				end  
				else begin
					TEST_RET = 1'b1;
				end
			end
				
		endcase
	end
endfunction