data/full_repos/permissive/450765583/src - 副本v3.v
1: b'%Error: Invalid Option: -\n'
module D0_display(
    input [3:0] D0_bits,
    input [3:0] D0_NUM,
    output reg [6:0] D0_a_to_g,
    output D0_dot,
    output [3:0] D0_led_bits
);
    assign D0_dot = D0_led_bits[1];
    assign D0_led_bits = D0_bits;
    always @(*) begin
        case(D0_NUM)
            0:D0_a_to_g=7'b1111110;
            1:D0_a_to_g=7'b0110000;
            2:D0_a_to_g=7'b1101101;
            3:D0_a_to_g=7'b1111001;
            4:D0_a_to_g=7'b0110011;
            5:D0_a_to_g=7'b1011011;
            6:D0_a_to_g=7'b1011111;
            7:D0_a_to_g=7'b1110000;
            8:D0_a_to_g=7'b1111111;
            9:D0_a_to_g=7'b1111011;
            default: D0_a_to_g=7'b1111110;
        endcase
    end
endmodule
module D0_display(
    input [3:0] D0_bits,
    input [3:0] D0_NUM,
    output reg [6:0] D0_a_to_g,
    output D0_dot,
    output [3:0] D0_led_bits
);

    assign D0_dot = D0_led_bits[1];
    assign D0_led_bits = D0_bits;
    always @(*) begin
        case(D0_NUM)
            0:D0_a_to_g=7'b1111110;
            1:D0_a_to_g=7'b0110000;
            2:D0_a_to_g=7'b1101101;
            3:D0_a_to_g=7'b1111001;
            4:D0_a_to_g=7'b0110011;
            5:D0_a_to_g=7'b1011011;
            6:D0_a_to_g=7'b1011111;
            7:D0_a_to_g=7'b1110000;
            8:D0_a_to_g=7'b1111111;
            9:D0_a_to_g=7'b1111011;
            default: D0_a_to_g=7'b1111110;
        endcase
    end
endmodule