data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v
1: b'%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:293: Cannot find include file: grp_15_test_large_tb.v.cases\n    `include "grp_15_test_large_tb.v.cases" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large,data/full_repos/permissive/484543204/grp_15_test_large_tb.v.cases\n             data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large,data/full_repos/permissive/484543204/grp_15_test_large_tb.v.cases.v\n             data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large,data/full_repos/permissive/484543204/grp_15_test_large_tb.v.cases.sv\n             grp_15_test_large_tb.v.cases\n             grp_15_test_large_tb.v.cases.v\n             grp_15_test_large_tb.v.cases.sv\n             obj_dir/grp_15_test_large_tb.v.cases\n             obj_dir/grp_15_test_large_tb.v.cases.v\n             obj_dir/grp_15_test_large_tb.v.cases.sv\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  always #12.5 clock = ~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n    #300000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:209: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("grp_15_test_large.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:210: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, grp_15_test_large_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:215: syntax error, unexpected \'@\'\n      repeat (1000) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n    #(3-1);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n    #(10-(3-1)); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n    #10; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n    #(10-(3-1)); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n    #10; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #(10-(3-1)); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #10; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n    #(10-(3-1));\n    ^\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:275: Unsupported: wait statements\n    wait (checkbits == 4\'hA);\n    ^~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:277: Unsupported: wait statements\n    wait (clk == 1);\n    ^~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:278: Unsupported: wait statements\n    wait (clk == 0);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:282: Unsupported: Ignoring delay on this delayed statement.\n    #(10/2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/grp_15_test_large/grp_15_test_large_tb.v:300: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: Exiting due to 7 error(s), 22 warning(s)\n'
module grp_15_test_large_tb;







  reg clock = 1'b0;
  always #12.5 clock = ~clock;



  reg clk = 1'b0;
  always #5 clk = ~clk;





  wire        VDD3V3;
  wire        VDD1V8;
  wire        VSS;
  reg         RSTB;
  reg         CSB;

  wire        gpio;
  wire [37:0] mprj_io;

  wire        flash_csb;
  wire        flash_clk;
  wire        flash_io0;
  wire        flash_io1;

  caravel uut
  (
    .vddio     (VDD3V3),
    .vddio_2   (VDD3V3),
    .vssio     (VSS),
    .vssio_2   (VSS),
    .vdda      (VDD3V3),
    .vssa      (VSS),
    .vccd      (VDD1V8),
    .vssd      (VSS),
    .vdda1     (VDD3V3),
    .vdda1_2   (VDD3V3),
    .vdda2     (VDD3V3),
    .vssa1     (VSS),
    .vssa1_2   (VSS),
    .vssa2     (VSS),
    .vccd1     (VDD1V8),
    .vccd2     (VDD1V8),
    .vssd1     (VSS),
    .vssd2     (VSS),
    .clock     (clock),
    .gpio      (gpio),
    .mprj_io   (mprj_io),
    .flash_csb (flash_csb),
    .flash_clk (flash_clk),
    .flash_io0 (flash_io0),
    .flash_io1 (flash_io1),
    .resetb    (RSTB)
  );

  spiflash
  #(
    .FILENAME ("grp_15_test_large.hex")
  )
  spiflash
  (
    .csb (flash_csb),
    .clk (flash_clk),
    .io0 (flash_io0),
    .io1 (flash_io1),
    .io2 (),
    .io3 ()
  );







  logic loopthrough_sel;
  logic spi_min_cs;
  logic spi_min_sclk;
  logic spi_min_mosi;
  logic reset;

  assign mprj_io[0]  = 0;
  assign mprj_io[3]  = 1;
  assign mprj_io[35] = loopthrough_sel;
  assign mprj_io[8] = spi_min_cs;
  assign mprj_io[9] = spi_min_sclk;
  assign mprj_io[34] = spi_min_mosi;
  assign mprj_io[10] = reset;
  assign mprj_io[11] = clk;



  wire        minion_parity;
  wire        adapter_parity;
  wire        spi_min_miso;
  wire  [3:0] checkbits;

  assign minion_parity  = mprj_io[36];
  assign adapter_parity = mprj_io[37];
  assign spi_min_miso   = mprj_io[33];
  assign checkbits      = mprj_io[31:28];





  initial begin
    RSTB <= 1'b0;
    CSB  <= 1'b1;
    #2000;
    RSTB <= 1'b1;
    #300000;
    CSB = 1'b0;
  end

  reg power1;
  reg power2;
  reg power3;
  reg power4;

  initial begin
    power1 <= 1'b0;
    power2 <= 1'b0;
    power3 <= 1'b0;
    power4 <= 1'b0;
    #100;
    power1 <= 1'b1;
    #100;
    power2 <= 1'b1;
    #100;
    power3 <= 1'b1;
    #100;
    power4 <= 1'b1;
  end

  assign VDD3V3 = power1;
  assign VDD1V8 = power2;
  assign VSS    = 1'b0;





  initial begin
    $dumpfile("grp_15_test_large.vcd");
    $dumpvars(0, grp_15_test_large_tb);
    #1;


    repeat (75) begin
      repeat (1000) @(posedge clock);
    end
    $display("%c[1;31m",27);
    `ifdef GL
      $display ("Monitor: Timeout GL Failed");
    `else
      $display ("Monitor: Timeout RTL Failed");
    `endif
    $display("%c[0m",27);
    $finish;
  end





  integer cycle_count;

  task t
  (
    input logic   ref_adapter_parity,
    input logic   inp_loopthrough_sel,
    input logic   ref_minion_parity,
    input logic   inp_spi_min_cs,
    input logic   ref_spi_min_miso,
    input logic   inp_spi_min_mosi,
    input logic   inp_spi_min_sclk,
    input integer lineno
  );
  begin



    loopthrough_sel  = inp_loopthrough_sel;
    spi_min_cs       = inp_spi_min_cs;
    spi_min_mosi     = inp_spi_min_mosi;
    spi_min_sclk     = inp_spi_min_sclk;



    #`INTRA_CYCLE_TIME;
    `CHECK( lineno, minion_parity,  ref_minion_parity,  "minion_parity (minion_parity in Verilog)"   );
    `CHECK( lineno, adapter_parity, ref_adapter_parity, "adapter_parity (adapter_parity in Verilog)" );
    `CHECK( lineno, spi_min_miso,   ref_spi_min_miso,   "spi_min.miso (spi_min_miso in Verilog)"     );



    #(`CYCLE_TIME-`INTRA_CYCLE_TIME);
    cycle_count += 1;

  end
  endtask





  initial begin


    wait (checkbits == 4'hA);

    wait (clk == 1);
    wait (clk == 0);
    cycle_count = 0;

    reset = 1'b1;
    #(`CYCLE_TIME/2);

    #`VTB_INPUT_DELAY;
    #`CYCLE_TIME;
    cycle_count = 1;
    #`CYCLE_TIME;
    cycle_count = 2;

    reset = 1'b0;


    `include "grp_15_test_large_tb.v.cases"

    $display("");
    $display("  [ passed ]");
    $display("");


    #`CYCLE_TIME;
    cycle_count += 1;
    $finish;

  end

endmodule
module grp_15_test_large_tb;








  reg clock = 1'b0;
  always #12.5 clock = ~clock;



  reg clk = 1'b0;
  always #5 clk = ~clk;





  wire        VDD3V3;
  wire        VDD1V8;
  wire        VSS;
  reg         RSTB;
  reg         CSB;

  wire        gpio;
  wire [37:0] mprj_io;

  wire        flash_csb;
  wire        flash_clk;
  wire        flash_io0;
  wire        flash_io1;

  caravel uut
  (
    .vddio     (VDD3V3),
    .vddio_2   (VDD3V3),
    .vssio     (VSS),
    .vssio_2   (VSS),
    .vdda      (VDD3V3),
    .vssa      (VSS),
    .vccd      (VDD1V8),
    .vssd      (VSS),
    .vdda1     (VDD3V3),
    .vdda1_2   (VDD3V3),
    .vdda2     (VDD3V3),
    .vssa1     (VSS),
    .vssa1_2   (VSS),
    .vssa2     (VSS),
    .vccd1     (VDD1V8),
    .vccd2     (VDD1V8),
    .vssd1     (VSS),
    .vssd2     (VSS),
    .clock     (clock),
    .gpio      (gpio),
    .mprj_io   (mprj_io),
    .flash_csb (flash_csb),
    .flash_clk (flash_clk),
    .flash_io0 (flash_io0),
    .flash_io1 (flash_io1),
    .resetb    (RSTB)
  );

  spiflash
  #(
    .FILENAME ("grp_15_test_large.hex")
  )
  spiflash
  (
    .csb (flash_csb),
    .clk (flash_clk),
    .io0 (flash_io0),
    .io1 (flash_io1),
    .io2 (),
    .io3 ()
  );







  logic loopthrough_sel;
  logic spi_min_cs;
  logic spi_min_sclk;
  logic spi_min_mosi;
  logic reset;

  assign mprj_io[0]  = 0;
  assign mprj_io[3]  = 1;
  assign mprj_io[35] = loopthrough_sel;
  assign mprj_io[8] = spi_min_cs;
  assign mprj_io[9] = spi_min_sclk;
  assign mprj_io[34] = spi_min_mosi;
  assign mprj_io[10] = reset;
  assign mprj_io[11] = clk;



  wire        minion_parity;
  wire        adapter_parity;
  wire        spi_min_miso;
  wire  [3:0] checkbits;

  assign minion_parity  = mprj_io[36];
  assign adapter_parity = mprj_io[37];
  assign spi_min_miso   = mprj_io[33];
  assign checkbits      = mprj_io[31:28];





  initial begin
    RSTB <= 1'b0;
    CSB  <= 1'b1;
    #2000;
    RSTB <= 1'b1;
    #300000;
    CSB = 1'b0;
  end

  reg power1;
  reg power2;
  reg power3;
  reg power4;

  initial begin
    power1 <= 1'b0;
    power2 <= 1'b0;
    power3 <= 1'b0;
    power4 <= 1'b0;
    #100;
    power1 <= 1'b1;
    #100;
    power2 <= 1'b1;
    #100;
    power3 <= 1'b1;
    #100;
    power4 <= 1'b1;
  end

  assign VDD3V3 = power1;
  assign VDD1V8 = power2;
  assign VSS    = 1'b0;





  initial begin
    $dumpfile("grp_15_test_large.vcd");
    $dumpvars(0, grp_15_test_large_tb);
    #1;


    repeat (75) begin
      repeat (1000) @(posedge clock);
    end
    $display("%c[1;31m",27);
    `ifdef GL
      $display ("Monitor: Timeout GL Failed");
    `else
      $display ("Monitor: Timeout RTL Failed");
    `endif
    $display("%c[0m",27);
    $finish;
  end





  integer cycle_count;

  task t
  (
    input logic   ref_adapter_parity,
    input logic   inp_loopthrough_sel,
    input logic   ref_minion_parity,
    input logic   inp_spi_min_cs,
    input logic   ref_spi_min_miso,
    input logic   inp_spi_min_mosi,
    input logic   inp_spi_min_sclk,
    input integer lineno
  );
  begin



    loopthrough_sel  = inp_loopthrough_sel;
    spi_min_cs       = inp_spi_min_cs;
    spi_min_mosi     = inp_spi_min_mosi;
    spi_min_sclk     = inp_spi_min_sclk;



    #`INTRA_CYCLE_TIME;
    `CHECK( lineno, minion_parity,  ref_minion_parity,  "minion_parity (minion_parity in Verilog)"   );
    `CHECK( lineno, adapter_parity, ref_adapter_parity, "adapter_parity (adapter_parity in Verilog)" );
    `CHECK( lineno, spi_min_miso,   ref_spi_min_miso,   "spi_min.miso (spi_min_miso in Verilog)"     );



    #(`CYCLE_TIME-`INTRA_CYCLE_TIME);
    cycle_count += 1;

  end
  endtask





  initial begin


    wait (checkbits == 4'hA);

    wait (clk == 1);
    wait (clk == 0);
    cycle_count = 0;

    reset = 1'b1;
    #(`CYCLE_TIME/2);

    #`VTB_INPUT_DELAY;
    #`CYCLE_TIME;
    cycle_count = 1;
    #`CYCLE_TIME;
    cycle_count = 2;

    reset = 1'b0;


    `include "grp_15_test_large_tb.v.cases"

    $display("");
    $display("  [ passed ]");
    $display("");


    #`CYCLE_TIME;
    cycle_count += 1;
    $finish;

  end

endmodule