data/full_repos/permissive/455223995/src/slzw_codec.v
1: b"%Error: data/full_repos/permissive/455223995/src/slzw_codec.v:127: Cannot find file containing module: 'slzw_codec_csr_regs'\n  slzw_codec_csr_regs\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_codec_csr_regs\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_codec_csr_regs.v\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_codec_csr_regs.sv\n             slzw_codec_csr_regs\n             slzw_codec_csr_regs.v\n             slzw_codec_csr_regs.sv\n             obj_dir/slzw_codec_csr_regs\n             obj_dir/slzw_codec_csr_regs.v\n             obj_dir/slzw_codec_csr_regs.sv\n%Error: data/full_repos/permissive/455223995/src/slzw_codec.v:159: Cannot find file containing module: 'slzw_dict'\n  slzw_dict\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_codec.v:198: Cannot find file containing module: 'slzw_axi4_master'\n  slzw_axi4_master \n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module slzw_codec
#(parameter
  MEMSIZE                      = 10240,
  ARUSER                       = 1'b1,
  ARCACHE                      = 4'b1110
)
(
  input                        clk,
  input                        reset_n,


  input  [3:0]                 avs_csr_address,
  input                        avs_csr_write,
  input  [31:0]                avs_csr_writedata,
  input                        avs_csr_read,
  output [31:0]                avs_csr_readdata,





  output [31:0]                axm_awaddr,
  output  [7:0]                axm_awlen,
  output  [2:0]                axm_awprot,
  output                       axm_awvalid,
  input                        axm_awready,



  output [31:0]                axm_wdata,
  output                       axm_wlast,
  output                       axm_wvalid,
  input                        axm_wready,



  input                        axm_bvalid,
  output                       axm_bready,



  output [31:0]                axm_araddr,
  output  [7:0]                axm_arlen,
  output  [3:0]                axm_arcache,
  output                       axm_aruser,
  output  [2:0]                axm_arprot,
  output                       axm_arvalid,
  input                        axm_arready,



  input  [31:0]                axm_rdata,
  input                        axm_rvalid,
  output                       axm_rready

);





wire                           control_en_acp_win;
wire                           control_mode;
wire                           control_clr;
wire                           control_start;
wire                           control_disable_flush;

wire                           status_finished;

wire [31:0]                    rx_start_addr;
wire [31:0]                    rx_len;
wire [31:0]                    tx_start_addr;
wire [31:0]                    tx_len;
wire                           busy;






assign status_finished         = ~busy;


assign rx_start_addr[1:0]      = 2'b00;
assign tx_start_addr[1:0]      = 2'b00;





  slzw_codec_csr_regs
  #(
    .ADDR_DECODE_WIDTH         (4)
  ) slzw_codec_csr_regs_i
  (
    .clk                       (clk),
    .rst_n                     (rst_n),

    .control_en_acp_win        (control_en_acp_win),
    .control_mode              (control_mode),
    .control_clr               (control_clr),
    .control_start             (control_start),
    .control_disable_flush     (control_disable_flush),

    .status_finished           (status_finished),

    .rx_start_addr_word        (rx_start_addr[31:2]),
    .rx_len                    (rx_len),
    .tx_start_addr_word        (tx_start_addr[31:2]),
    .tx_len                    (tx_len),

    .avs_address               (avs_csr_address[3:0]),
    .avs_write                 (avs_csr_write),
    .avs_writedata             (avs_csr_writedata),
    .avs_read                  (avs_csr_read),
    .avs_readdata              (avs_csr_readdata)
  );





  slzw_dict
  #(
    .MEMSIZE                   (MEMSIZE)
  ) slzw_dict_i
  (
    .clk                       (clk),
    .reset_n                   (reset_n),


    .clr                       (control_clr),


    .compress                  (control_mode),


    .match                     (1'b0),
    .match_code                (12'h000),
    .match_byte                (8'h00),
    .matched                   (),
    .matched_valid             (),


    .build_entry               (1'b0),
    .build_code                (12'h000),
    .build_byte                (8'h00),


    .dict_decomp_ptr           (12'h000),
    .dict_code                 (),
    .dict_byte                 (),

    .op_code_len               ()

  );





  slzw_axi4_master 
  # (
    .USRPORTWIDTH              (8)
  )
  slzw_axi4_master_i
  (
    .aclk                      (clk),
    .aresetn                   (reset_n),
    


    .clear                     (control_clr),
    .start                     (control_start),
    .busy                      (busy),

    .rx_start_addr             (rx_start_addr),
    .rx_len                    (rx_len),
    .tx_start_addr             (tx_start_addr),
    .tx_len                    (tx_len),


    .user_read_byte            (1'b1),
    .user_read_data            (),
    .user_read_data_valid      (),

    .user_write_byte           (1'b0),
    .user_write_data           (8'h00),
    .user_write_ready          (),


    .awaddr                    (axm_awaddr),
    .awlen                     (axm_awlen),
    .awprot                    (axm_awprot),
    .awvalid                   (axm_awvalid),
    .awready                   (axm_awready),
    .wdata                     (axm_wdata),
    .wlast                     (axm_wlast),
    .wvalid                    (axm_wvalid),
    .wready                    (axm_wready),
    .bvalid                    (axm_bvalid),
    .bready                    (axm_bready),
    .araddr                    (axm_araddr),
    .arlen                     (axm_arlen),
    .arcache                   (axm_arcache),
    .aruser                    (axm_aruser),
    .arprot                    (axm_arprot),
    .arvalid                   (axm_arvalid),
    .arready                   (axm_arready),
    .rdata                     (axm_rdata),
    .rvalid                    (axm_rvalid),
    .rready                    (axm_rready)
  );

endmodule
module slzw_codec
#(parameter
  MEMSIZE                      = 10240,
  ARUSER                       = 1'b1,
  ARCACHE                      = 4'b1110
)
(
  input                        clk,
  input                        reset_n,


  input  [3:0]                 avs_csr_address,
  input                        avs_csr_write,
  input  [31:0]                avs_csr_writedata,
  input                        avs_csr_read,
  output [31:0]                avs_csr_readdata,





  output [31:0]                axm_awaddr,
  output  [7:0]                axm_awlen,
  output  [2:0]                axm_awprot,
  output                       axm_awvalid,
  input                        axm_awready,



  output [31:0]                axm_wdata,
  output                       axm_wlast,
  output                       axm_wvalid,
  input                        axm_wready,



  input                        axm_bvalid,
  output                       axm_bready,



  output [31:0]                axm_araddr,
  output  [7:0]                axm_arlen,
  output  [3:0]                axm_arcache,
  output                       axm_aruser,
  output  [2:0]                axm_arprot,
  output                       axm_arvalid,
  input                        axm_arready,



  input  [31:0]                axm_rdata,
  input                        axm_rvalid,
  output                       axm_rready

);






wire                           control_en_acp_win;
wire                           control_mode;
wire                           control_clr;
wire                           control_start;
wire                           control_disable_flush;

wire                           status_finished;

wire [31:0]                    rx_start_addr;
wire [31:0]                    rx_len;
wire [31:0]                    tx_start_addr;
wire [31:0]                    tx_len;
wire                           busy;






assign status_finished         = ~busy;


assign rx_start_addr[1:0]      = 2'b00;
assign tx_start_addr[1:0]      = 2'b00;





  slzw_codec_csr_regs
  #(
    .ADDR_DECODE_WIDTH         (4)
  ) slzw_codec_csr_regs_i
  (
    .clk                       (clk),
    .rst_n                     (rst_n),

    .control_en_acp_win        (control_en_acp_win),
    .control_mode              (control_mode),
    .control_clr               (control_clr),
    .control_start             (control_start),
    .control_disable_flush     (control_disable_flush),

    .status_finished           (status_finished),

    .rx_start_addr_word        (rx_start_addr[31:2]),
    .rx_len                    (rx_len),
    .tx_start_addr_word        (tx_start_addr[31:2]),
    .tx_len                    (tx_len),

    .avs_address               (avs_csr_address[3:0]),
    .avs_write                 (avs_csr_write),
    .avs_writedata             (avs_csr_writedata),
    .avs_read                  (avs_csr_read),
    .avs_readdata              (avs_csr_readdata)
  );





  slzw_dict
  #(
    .MEMSIZE                   (MEMSIZE)
  ) slzw_dict_i
  (
    .clk                       (clk),
    .reset_n                   (reset_n),


    .clr                       (control_clr),


    .compress                  (control_mode),


    .match                     (1'b0),
    .match_code                (12'h000),
    .match_byte                (8'h00),
    .matched                   (),
    .matched_valid             (),


    .build_entry               (1'b0),
    .build_code                (12'h000),
    .build_byte                (8'h00),


    .dict_decomp_ptr           (12'h000),
    .dict_code                 (),
    .dict_byte                 (),

    .op_code_len               ()

  );





  slzw_axi4_master 
  # (
    .USRPORTWIDTH              (8)
  )
  slzw_axi4_master_i
  (
    .aclk                      (clk),
    .aresetn                   (reset_n),
    


    .clear                     (control_clr),
    .start                     (control_start),
    .busy                      (busy),

    .rx_start_addr             (rx_start_addr),
    .rx_len                    (rx_len),
    .tx_start_addr             (tx_start_addr),
    .tx_len                    (tx_len),


    .user_read_byte            (1'b1),
    .user_read_data            (),
    .user_read_data_valid      (),

    .user_write_byte           (1'b0),
    .user_write_data           (8'h00),
    .user_write_ready          (),


    .awaddr                    (axm_awaddr),
    .awlen                     (axm_awlen),
    .awprot                    (axm_awprot),
    .awvalid                   (axm_awvalid),
    .awready                   (axm_awready),
    .wdata                     (axm_wdata),
    .wlast                     (axm_wlast),
    .wvalid                    (axm_wvalid),
    .wready                    (axm_wready),
    .bvalid                    (axm_bvalid),
    .bready                    (axm_bready),
    .araddr                    (axm_araddr),
    .arlen                     (axm_arlen),
    .arcache                   (axm_arcache),
    .aruser                    (axm_aruser),
    .arprot                    (axm_arprot),
    .arvalid                   (axm_arvalid),
    .arready                   (axm_arready),
    .rdata                     (axm_rdata),
    .rvalid                    (axm_rvalid),
    .rready                    (axm_rready)
  );

endmodule