data/full_repos/permissive/46343463/src/Latch.v
data/verilator_xmls/3aa3c63c-edaa-4e2e-8d21-0a0da641c8b5.xml
module Latch #(parameter width=32) (
	input					clk,
	input      				rst,
	input      				we,
	input      	[width-1:0]	data_i,
	output reg 	[width-1:0]	data_o
);
	
	initial begin
		data_o = {width{1'b0}};
	end
	
	always @ (posedge clk or negedge rst) begin
  		if(~rst)
   			data_o <= {width{1'b0}};
  		else begin
			if(we)
    			data_o <= data_i;
			else
				data_o <= data_o;
    	end
	end

endmodule
module Latch #(parameter width=32) (
	input					clk,
	input      				rst,
	input      				we,
	input      	[width-1:0]	data_i,
	output reg 	[width-1:0]	data_o
);

	
	initial begin
		data_o = {width{1'b0}};
	end
	
	always @ (posedge clk or negedge rst) begin
  		if(~rst)
   			data_o <= {width{1'b0}};
  		else begin
			if(we)
    			data_o <= data_i;
			else
				data_o <= data_o;
    	end
	end

endmodule