data/full_repos/permissive/511535464/src/test_pipeline.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/511535464/src/test_pipeline.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/511535464/src/test_pipeline.v:18: Unsupported: Ignoring delay on this delayed statement.\n always #5 sysclk = ~sysclk;\n        ^\n%Error: data/full_repos/permissive/511535464/src/test_pipeline.v:10: Cannot find file containing module: \'PipelineCPU\'\n PipelineCPU pipelineCpu(sysclk, reset, leds, bcd7, an);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/511535464/src,data/full_repos/permissive/511535464/PipelineCPU\n             data/full_repos/permissive/511535464/src,data/full_repos/permissive/511535464/PipelineCPU.v\n             data/full_repos/permissive/511535464/src,data/full_repos/permissive/511535464/PipelineCPU.sv\n             PipelineCPU\n             PipelineCPU.v\n             PipelineCPU.sv\n             obj_dir/PipelineCPU\n             obj_dir/PipelineCPU.v\n             obj_dir/PipelineCPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_pipeline();
	
	reg reset;
	reg sysclk;
	wire [7:0] leds;
	wire [7:0] bcd7;
	wire [3:0] an;
	
	PipelineCPU pipelineCpu(sysclk, reset, leds, bcd7, an);
	
	initial begin
		reset = 1;
		sysclk = 1;
		#10 reset = 0;
	end
	
	always #5 sysclk = ~sysclk;
		
endmodule
module test_pipeline();

	
	reg reset;
	reg sysclk;
	wire [7:0] leds;
	wire [7:0] bcd7;
	wire [3:0] an;
	
	PipelineCPU pipelineCpu(sysclk, reset, leds, bcd7, an);
	
	initial begin
		reset = 1;
		sysclk = 1;
		#10 reset = 0;
	end
	
	always #5 sysclk = ~sysclk;
		
endmodule