data/full_repos/permissive/481069643/Day01/ALU.v
1: b"%Error: data/full_repos/permissive/481069643/Day01/ALU.v:45: Cannot find file containing module: 'adder'\nadder A0(in_a,w_b,w_cin,w_sum,out_carry);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/481069643/Day01,data/full_repos/permissive/481069643/adder\n             data/full_repos/permissive/481069643/Day01,data/full_repos/permissive/481069643/adder.v\n             data/full_repos/permissive/481069643/Day01,data/full_repos/permissive/481069643/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/481069643/Day01/ALU.v:46: Cannot find file containing module: 'LogicalUnit'\nLogicalUnit L0(in_a,w_b,fun[2:0],w_logical);\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ALU(in_a,in_b,fun,out_alu,out_carry);

input [3:0]in_a,in_b;
input [3:0]fun;
output [3:0]out_alu;
output out_carry;

wire [3:0]w_b;
wire w_cin;
wire [3:0] w_sum;
wire [3:0] w_logical;

assign w_cin = (fun[3] & fun[0])?1'b1:1'b0;
assign w_b   = (fun[3] & fun[0])?~in_b:in_b;


adder A0(in_a,w_b,w_cin,w_sum,out_carry);
LogicalUnit L0(in_a,w_b,fun[2:0],w_logical);

assign out_alu = fun[3]?w_sum:w_logical;


endmodule
module ALU(in_a,in_b,fun,out_alu,out_carry);


input [3:0]in_a,in_b;
input [3:0]fun;
output [3:0]out_alu;
output out_carry;

wire [3:0]w_b;
wire w_cin;
wire [3:0] w_sum;
wire [3:0] w_logical;

assign w_cin = (fun[3] & fun[0])?1'b1:1'b0;
assign w_b   = (fun[3] & fun[0])?~in_b:in_b;


adder A0(in_a,w_b,w_cin,w_sum,out_carry);
LogicalUnit L0(in_a,w_b,fun[2:0],w_logical);

assign out_alu = fun[3]?w_sum:w_logical;


endmodule