data/full_repos/permissive/426823752/output_files/blocks.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/426823752/output_files/blocks.sv:10: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffffffff\' generates 32 bits.\n                                                                              : ... In instance blocks\n   Block_Array = 32\'b11111111111111111111111111111111;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error-PROCASSWIRE: data/full_repos/permissive/426823752/output_files/blocks.sv:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'Block_Array\'\n                                                                                  : ... In instance blocks\n   Block_Array = 32\'b11111111111111111111111111111111;\n   ^~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module  blocks ( input Reset, frame_clk,
                output [9:0] Block_SizeX, Block_SizeY,
					 output [32:0] Block_Array);
					

	assign Block_SizeX = 39;  
	assign Block_SizeY = 10;
	always_ff @ (posedge Reset or posedge frame_clk )
	begin
   Block_Array = 32'b11111111111111111111111111111111;
	end
	 endmodule
module  blocks ( input Reset, frame_clk,
                output [9:0] Block_SizeX, Block_SizeY,
					 output [32:0] Block_Array);

					

	assign Block_SizeX = 39;  
	assign Block_SizeY = 10;
	always_ff @ (posedge Reset or posedge frame_clk )
	begin
   Block_Array = 32'b11111111111111111111111111111111;
	end
	 endmodule