data/full_repos/permissive/479923049/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator XOR expects 16 bits on the LHS, but LHS\'s SEL generates 15 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator XOR expects 16 bits on the RHS, but RHS\'s REPLICATE generates 15 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'sub\' generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:45: Operator XOR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:45: Operator XOR expects 2 bits on the RHS, but RHS\'s VARREF \'sub\' generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;\n                                        ^\n%Error: Exiting due to 5 warning(s)\n'
module ALU(Ain,Bin,ALUop,out,status);
    input [15:0] Ain, Bin;
    input [1:0] ALUop;
    output [15:0] out;
    reg [15:0] out;
    output [2:0] status;
    
    wire overflow;
    wire z_flag;
    wire [15:0] addsub_output;
    reg sub;

    AddSub addsub(Ain, Bin, sub, addsub_output, overflow);



    always @(*) begin  
        case(ALUop) 
            2'b00: {sub, out} = {1'b0, Ain + Bin};
            2'b01: {sub, out} = {1'b1, Ain - Bin};
            2'b10: {sub, out} = {1'b0, Ain & Bin};
            2'b11: {sub, out} = {1'b0, ~Bin};
            default: {sub, out} = {17{1'bx}};
        endcase        
    end

    assign z_flag = (out == 16'd0) ? 1'b1 : 1'b0;

    assign status = {out[15], overflow, z_flag};
endmodule
module ALU(Ain,Bin,ALUop,out,status);

    input [15:0] Ain, Bin;
    input [1:0] ALUop;
    output [15:0] out;
    reg [15:0] out;
    output [2:0] status;
    
    wire overflow;
    wire z_flag;
    wire [15:0] addsub_output;
    reg sub;

    AddSub addsub(Ain, Bin, sub, addsub_output, overflow);



    always @(*) begin  
        case(ALUop) 
            2'b00: {sub, out} = {1'b0, Ain + Bin};
            2'b01: {sub, out} = {1'b1, Ain - Bin};
            2'b10: {sub, out} = {1'b0, Ain & Bin};
            2'b11: {sub, out} = {1'b0, ~Bin};
            default: {sub, out} = {17{1'bx}};
        endcase        
    end

    assign z_flag = (out == 16'd0) ? 1'b1 : 1'b0;

    assign status = {out[15], overflow, z_flag};
endmodule