data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:14: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:57: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:62: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:67: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:72: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:77: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:25: Can\'t find definition of \'i\' in dotted scope/variable: \'tb_rtl_task1.dut.i\'\n            if (tb_rtl_task1.dut.i.state !== exp_state) begin\n                                 ^\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:26: Can\'t find definition of \'i\' in dotted scope/variable: \'tb_rtl_task1.dut.i\'\n                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_task1.dut.i.state);\n                                                                                                          ^\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:29: Can\'t find definition of \'rdy\' in dotted variable: \'tb_rtl_task1.dut.rdy\'\n            if (tb_rtl_task1.dut.rdy !== exp_rdy) begin\n                                 ^~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:30: Can\'t find definition of \'rdy\' in dotted variable: \'tb_rtl_task1.dut.rdy\'\n                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_task1.dut.rdy);\n                                                                                                    ^~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:33: Can\'t find definition of \'addr\' in dotted variable: \'tb_rtl_task1.dut.addr\'\n            if (tb_rtl_task1.dut.addr !== exp_addr) begin\n                                 ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:34: Can\'t find definition of \'addr\' in dotted variable: \'tb_rtl_task1.dut.addr\'\n                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_task1.dut.addr);\n                                                                                                       ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:37: Can\'t find definition of \'wrdata\' in dotted variable: \'tb_rtl_task1.dut.wrdata\'\n            if (tb_rtl_task1.dut.wrdata !== exp_wrdata) begin\n                                 ^~~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:38: Can\'t find definition of \'wrdata\' in dotted variable: \'tb_rtl_task1.dut.wrdata\'\n                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_task1.dut.wrdata);\n                                                                                                             ^~~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:41: Can\'t find definition of \'wren\' in dotted variable: \'tb_rtl_task1.dut.wren\'\n            if (tb_rtl_task1.dut.wren !== exp_wren) begin\n                                 ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:42: Can\'t find definition of \'wren\' in dotted variable: \'tb_rtl_task1.dut.wren\'\n                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_task1.dut.wren);\n                                                                                                       ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:82: Can\'t find definition of \'s\' in dotted scope/variable: \'tb_rtl_task1.dut.s\'\n            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin\n                                 ^\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:82: Can\'t find definition of \'altsyncram_component\' in dotted scope/variable: \'tb_rtl_task1.dut.altsyncram_component\'\n            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:82: Can\'t find definition of \'m_default\' in dotted scope/variable: \'tb_rtl_task1.dut.m_default\'\n            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin\n                                                        ^~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:82: Can\'t find definition of \'altsyncram_inst\' in dotted scope/variable: \'tb_rtl_task1.dut.altsyncram_inst\'\n            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin\n                                                                  ^~~~~~~~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:83: Can\'t find definition of \'s\' in dotted scope/variable: \'tb_rtl_task1.dut.s\'\n                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);\n                                                                                                  ^\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:83: Can\'t find definition of \'altsyncram_component\' in dotted scope/variable: \'tb_rtl_task1.dut.altsyncram_component\'\n                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);\n                                                                                                    ^~~~~~~~~~~~~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:83: Can\'t find definition of \'m_default\' in dotted scope/variable: \'tb_rtl_task1.dut.m_default\'\n                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);\n                                                                                                                         ^~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_task1.sv:83: Can\'t find definition of \'altsyncram_inst\' in dotted scope/variable: \'tb_rtl_task1.dut.altsyncram_inst\'\n                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);\n                                                                                                                                   ^~~~~~~~~~~~~~~\n        ... Known scopes under \'tb_rtl_task1.dut\': <no cells found>\n%Error: Exiting due to 18 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_task1();

    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

    task1 dut(.*);

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [31:0] index;
        input [1:0] exp_state;
        input exp_rdy;
        input [7:0] exp_addr, exp_wrdata;
        input exp_wren;
        begin
            $display("CASE %d", index);
            if (tb_rtl_task1.dut.i.state !== exp_state) begin
                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_task1.dut.i.state);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_task1.dut.rdy);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.addr !== exp_addr) begin
                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_task1.dut.addr);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.wrdata !== exp_wrdata) begin
                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_task1.dut.wrdata);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.wren !== exp_wren) begin
                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_task1.dut.wren);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE 1'b0
    `define WRITE 1'b1

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;
        validator(1, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        KEY[3] = 1'b0;
        #30;
        validator(2, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        KEY[3] = 1'b1;
        #10;
        validator(3, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);


        for (int i = 0; i < 256; i++) begin
            #10;
            validator(i, `WRITE, 1'b0, i, i, 1'b1);
        end


        #50;
        validator(5, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);


        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_rtl_task1();


    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

    task1 dut(.*);

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [31:0] index;
        input [1:0] exp_state;
        input exp_rdy;
        input [7:0] exp_addr, exp_wrdata;
        input exp_wren;
        begin
            $display("CASE %d", index);
            if (tb_rtl_task1.dut.i.state !== exp_state) begin
                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_task1.dut.i.state);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_task1.dut.rdy);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.addr !== exp_addr) begin
                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_task1.dut.addr);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.wrdata !== exp_wrdata) begin
                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_task1.dut.wrdata);
                err = 1'b1;
            end
            if (tb_rtl_task1.dut.wren !== exp_wren) begin
                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_task1.dut.wren);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE 1'b0
    `define WRITE 1'b1

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;
        validator(1, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        KEY[3] = 1'b0;
        #30;
        validator(2, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        KEY[3] = 1'b1;
        #10;
        validator(3, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);


        for (int i = 0; i < 256; i++) begin
            #10;
            validator(i, `WRITE, 1'b0, i, i, 1'b1);
        end


        #50;
        validator(5, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);


        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_task1.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule