data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram/tb.v:26: Cannot find file containing module: \'data_ram\'\n    data_ram data_ram_module(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram,data/full_repos/permissive/482470328/data_ram\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram,data/full_repos/permissive/482470328/data_ram.v\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_async/data_ram,data/full_repos/permissive/482470328/data_ram.sv\n             data_ram\n             data_ram.v\n             data_ram.sv\n             obj_dir/data_ram\n             obj_dir/data_ram.v\n             obj_dir/data_ram.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    reg clk;
    reg  [ 4:0] addr;
    reg  [31:0] wdata;
    reg  [ 3:0] wen;
    wire [31:0] rdata;
    reg  [ 4:0] test_addr;
    wire [31:0] test_data;  

    data_ram data_ram_module(
        .clk   (clk   ),
        .wen   (wen   ),
        .addr  (addr),
        .wdata (wdata ),
        .rdata (rdata ),
        .test_addr(test_addr),
        .test_data(test_data)
    );
    
    initial begin
        clk = 0;
        addr = 0;

        #10;
        clk = 1;
        wen = 4'hf;
        wdata = 0;
        
        #10;
        clk = 0;
        
        #10;
        clk = 1;
        wen = 4'b0001;
        wdata = 32'HFFFFFFFF;
    end
endmodule
module tb;

    reg clk;
    reg  [ 4:0] addr;
    reg  [31:0] wdata;
    reg  [ 3:0] wen;
    wire [31:0] rdata;
    reg  [ 4:0] test_addr;
    wire [31:0] test_data;  

    data_ram data_ram_module(
        .clk   (clk   ),
        .wen   (wen   ),
        .addr  (addr),
        .wdata (wdata ),
        .rdata (rdata ),
        .test_addr(test_addr),
        .test_data(test_data)
    );
    
    initial begin
        clk = 0;
        addr = 0;

        #10;
        clk = 1;
        wen = 4'hf;
        wdata = 0;
        
        #10;
        clk = 0;
        
        #10;
        clk = 1;
        wen = 4'b0001;
        wdata = 32'HFFFFFFFF;
    end
endmodule