data/full_repos/permissive/517406069/verilog/rtl/counter.v
1: b"%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:31: syntax error, unexpected ')', expecting '['\n)(\n^\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rst,\n    ^~~~~\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire set_i,\n    ^~~~~\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [WIDTH-1:0] setValue_i,\n    ^~~~~\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [WIDTH-1:0] count_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:39: syntax error, unexpected ')', expecting IDENTIFIER or do or final\n);\n^\n%Error: data/full_repos/permissive/517406069/verilog/rtl/counter.v:43: syntax error, unexpected assign\n    assign count_o = count_r;\n    ^~~~~~\n%Error: Exiting due to 7 error(s)\n"
module counter #(
    parameter WIDTH = 32,
    parameter INCREMENT_AMOUNT = 1,
)(
    input wire clk,
    input wire rst,

    input wire set_i,
    input wire [WIDTH-1:0] setValue_i,

    output wire [WIDTH-1:0] count_o,
);
    reg [WIDTH-1:0] count_r;

    wire [WIDTH-1:0] count_o;
    assign count_o = count_r;

    always @(posedge clk) begin
        if (rst) begin
            count_r <= 0;
        end else begin
            count_r <= next_count;
        end
    end

    always @(*) begin
        if(set) begin
            next_count = setValue_i;
        end else begin
            next_count = count_r + INCREMENT_AMOUNT;
        end
    end
endmodule
module counter #(
    parameter WIDTH = 32,
    parameter INCREMENT_AMOUNT = 1,
)(
    input wire clk,
    input wire rst,

    input wire set_i,
    input wire [WIDTH-1:0] setValue_i,

    output wire [WIDTH-1:0] count_o,
);

    reg [WIDTH-1:0] count_r;

    wire [WIDTH-1:0] count_o;
    assign count_o = count_r;

    always @(posedge clk) begin
        if (rst) begin
            count_r <= 0;
        end else begin
            count_r <= next_count;
        end
    end

    always @(*) begin
        if(set) begin
            next_count = setValue_i;
        end else begin
            next_count = count_r + INCREMENT_AMOUNT;
        end
    end
endmodule