data/full_repos/permissive/468493488/vga_sync.v
data/verilator_xmls/7a9af912-6dae-4b5c-ac62-a93feb80a1b1.xml
module vga_sync(
    input CLK,
    output HS,
    output VS,
    output [9:0] x,
    output [9:0] y,
    output blank
    );
reg [9:0] xc;
reg [9:0] yc;



assign blank = ((xc < 192) | (xc > 832) | (yc > 479));
assign HS = ~ ((xc > 23) & (xc < 65));
assign VS = ~ ((yc > 489) & (yc < 493));

assign x = xc-192;
assign y = yc;

always @(posedge CLK)
begin


	begin
	  if (xc == 832)
	  begin
		 xc <= 0;
		 yc <= yc + 1;
	  end
	  else
	  begin
		 xc <= xc + 1;
	  end
	  if (yc == 520)
	  begin
		 yc <= 0;
	  end
	end
end


endmodule
module vga_sync(
    input CLK,
    output HS,
    output VS,
    output [9:0] x,
    output [9:0] y,
    output blank
    );

reg [9:0] xc;
reg [9:0] yc;



assign blank = ((xc < 192) | (xc > 832) | (yc > 479));
assign HS = ~ ((xc > 23) & (xc < 65));
assign VS = ~ ((yc > 489) & (yc < 493));

assign x = xc-192;
assign y = yc;

always @(posedge CLK)
begin


	begin
	  if (xc == 832)
	  begin
		 xc <= 0;
		 yc <= yc + 1;
	  end
	  else
	  begin
		 xc <= xc + 1;
	  end
	  if (yc == 520)
	  begin
		 yc <= 0;
	  end
	end
end


endmodule