data/full_repos/permissive/423510918/sp_sram_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423510918/sp_sram_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423510918/sp_sram_tb.v:27: syntax error, unexpected \'@\'\n    repeat (2) @ (posedge clk);\n               ^\n%Error: data/full_repos/permissive/423510918/sp_sram_tb.v:29: syntax error, unexpected \'@\'\n      repeat (1) @(posedge clk) addr <= i; we <= 1; cs <=1; oe <= 0; tb_data <= $random;\n                 ^\n%Error: data/full_repos/permissive/423510918/sp_sram_tb.v:32: syntax error, unexpected \'@\'\n      repeat (1) @(posedge clk) addr <= i; we <= 0; cs <= 1; oe <= 1;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/423510918/sp_sram_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
  parameter ADDR_WIDTH = 32;
  parameter DATA_WIDTH = 32;
  parameter DEPTH = 1024;
  reg clk;
  reg cs;
  reg we;
  reg oe;
  reg [ADDR_WIDTH-1:0] addr;
  wire [DATA_WIDTH-1:0] data;
  reg [DATA_WIDTH-1:0] tb_data;
  
  sp_sram #(.DATA_WIDTH(DATA_WIDTH)) u0 (
  .clk(clk),
  .addr(addr),
  .data(data),
  .cs(cs),
  .we(we),
  .oe(oe)
  );
  
  always #10 clk = ~clk;
  assign data = !oe ? tb_data : 'hz;
  
  initial begin
    {clk, cs, we, addr, tb_data, oe} <= 0;
    repeat (2) @ (posedge clk);
    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
      repeat (1) @(posedge clk) addr <= i; we <= 1; cs <=1; oe <= 0; tb_data <= $random;
    end
    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
      repeat (1) @(posedge clk) addr <= i; we <= 0; cs <= 1; oe <= 1;
    end
  #20 $finish;
  end
endmodule
module tb;

  parameter ADDR_WIDTH = 32;
  parameter DATA_WIDTH = 32;
  parameter DEPTH = 1024;
  reg clk;
  reg cs;
  reg we;
  reg oe;
  reg [ADDR_WIDTH-1:0] addr;
  wire [DATA_WIDTH-1:0] data;
  reg [DATA_WIDTH-1:0] tb_data;
  
  sp_sram #(.DATA_WIDTH(DATA_WIDTH)) u0 (
  .clk(clk),
  .addr(addr),
  .data(data),
  .cs(cs),
  .we(we),
  .oe(oe)
  );
  
  always #10 clk = ~clk;
  assign data = !oe ? tb_data : 'hz;
  
  initial begin
    {clk, cs, we, addr, tb_data, oe} <= 0;
    repeat (2) @ (posedge clk);
    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
      repeat (1) @(posedge clk) addr <= i; we <= 1; cs <=1; oe <= 0; tb_data <= $random;
    end
    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
      repeat (1) @(posedge clk) addr <= i; we <= 0; cs <= 1; oe <= 1;
    end
  #20 $finish;
  end
endmodule