data/full_repos/permissive/493212017/blink/simpleTestbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493212017/blink/simpleTestbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #1 signalIn = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493212017/blink/simpleTestbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1 signalIn = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/493212017/blink/simpleTestbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 signalIn = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/493212017/blink/simpleTestbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 signalIn = 1;\n ^\n%Error: data/full_repos/permissive/493212017/blink/simpleTestbench.v:31: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("simpleTestbench.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/493212017/blink/simpleTestbench.v:32: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simpleTestbench;
	reg	signalIn;
	wire	signalOut;

	simple simpleInstance(.inSignal(signalIn), .outSignal(signalOut));

	initial begin

	#1	signalIn = 0;


	#1	signalIn = 1;


	#10	signalIn = 0;


	#1	signalIn = 1;
	end
	initial begin
		$dumpfile("simpleTestbench.vcd");
		$dumpvars;
	end
endmodule
module simpleTestbench;

	reg	signalIn;
	wire	signalOut;

	simple simpleInstance(.inSignal(signalIn), .outSignal(signalOut));

	initial begin

	#1	signalIn = 0;


	#1	signalIn = 1;


	#10	signalIn = 0;


	#1	signalIn = 1;
	end
	initial begin
		$dumpfile("simpleTestbench.vcd");
		$dumpvars;
	end
endmodule