data/full_repos/permissive/500711628/register/register.v
data/verilator_xmls/281fe408-b929-4856-984f-43fc280c8f05.xml
module register
(
	input clock,
	input reset,
	input exec, 
	
	input enable,
	
	input [2:0] radd1,
	input [2:0] radd2,
	input [15:0] wdata,
	input [2:0] wadd,
	input wflag,
	output reg [15:0] rdata1,
	output reg [15:0] rdata2
);
	
	reg [15:0] rgst [7:0];
	integer i;
	
	always @(posedge clock) begin 
		if(reset) begin 
			for(i = 0; i < 8; i = i + 1) begin
				rgst[i] <= 16'b0000_0000_0000_0000;
			end
		end 
		else if(exec) begin 

		end 
		else begin
			if(! enable) begin

			end 
			else begin
				if(wflag) begin
					rgst[wadd] <= wdata;
					if(radd1 == wadd) begin 
						rdata1 <= wdata;
						rdata2 <= rgst[radd2];
					end 
					else if(radd2 == wadd) begin 
						rdata1 <= rgst[radd1];
						rdata2 <= wdata;
					end 
					else begin
						rdata1 <= rgst[radd1];
						rdata2 <= rgst[radd2];
					end
				end
				else begin
					rdata1 <= rgst[radd1];
					rdata2 <= rgst[radd2];
				end
			end
		end
	end

endmodule
module register
(
	input clock,
	input reset,
	input exec, 
	
	input enable,
	
	input [2:0] radd1,
	input [2:0] radd2,
	input [15:0] wdata,
	input [2:0] wadd,
	input wflag,
	output reg [15:0] rdata1,
	output reg [15:0] rdata2
);

	
	reg [15:0] rgst [7:0];
	integer i;
	
	always @(posedge clock) begin 
		if(reset) begin 
			for(i = 0; i < 8; i = i + 1) begin
				rgst[i] <= 16'b0000_0000_0000_0000;
			end
		end 
		else if(exec) begin 

		end 
		else begin
			if(! enable) begin

			end 
			else begin
				if(wflag) begin
					rgst[wadd] <= wdata;
					if(radd1 == wadd) begin 
						rdata1 <= wdata;
						rdata2 <= rgst[radd2];
					end 
					else if(radd2 == wadd) begin 
						rdata1 <= rgst[radd1];
						rdata2 <= wdata;
					end 
					else begin
						rdata1 <= rgst[radd1];
						rdata2 <= rgst[radd2];
					end
				end
				else begin
					rdata1 <= rgst[radd1];
					rdata2 <= rgst[radd2];
				end
			end
		end
	end

endmodule