data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/timescale_syntax.v
data/verilator_xmls/df8cada0-a968-4ed0-b04e-1a239122000f.xml
module timescale_syntax (a,b,c);

input a;
input b;
output c;

assign c = a ^ b;

endmodule
module timescale_syntax (a,b,c);


input a;
input b;
output c;

assign c = a ^ b;

endmodule