data/full_repos/permissive/447223480/01_add/cpu.v
data/verilator_xmls/129a3714-4632-494b-881a-1dcf02d4c0b9.xml
module pmem(addr, data);
	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule
module pmem(addr, data);

	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule