data/full_repos/permissive/448204225/src/accelerator/axi_mm_adapter.v
1: b'%Error: data/full_repos/permissive/448204225/src/accelerator/axi_mm_adapter.v:1: Cannot find include file: axi_consts.vh\n`include "axi_consts.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh.v\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh.sv\n             axi_consts.vh\n             axi_consts.vh.v\n             axi_consts.vh.sv\n             obj_dir/axi_consts.vh\n             obj_dir/axi_consts.vh.v\n             obj_dir/axi_consts.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module axi_mm_adapter #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter AXI_MAX_BURST_LEN = 256
) (
  input clk,
  input resetn,




  output [3:0]            arid,
  (* mark_debug = "True" *) output [AXI_AWIDTH-1:0] araddr,
  (* mark_debug = "True" *) output                  arvalid,
  (* mark_debug = "True" *) input                   arready,
  (* mark_debug = "True" *) output [7:0]            arlen,
  (* mark_debug = "True" *) output [2:0]            arsize,
  (* mark_debug = "True" *) output [1:0]            arburst,



  input  [3:0]            rid,
  (* mark_debug = "True" *) input  [AXI_DWIDTH-1:0] rdata,
  (* mark_debug = "True" *) input                   rvalid,
  (* mark_debug = "True" *) output                  rready,
  (* mark_debug = "True" *) input                   rlast,
  input  [1:0]            rresp,



  output [3:0]            awid,
  (* mark_debug = "True" *) output [AXI_AWIDTH-1:0] awaddr,
  (* mark_debug = "True" *) output                  awvalid,
  (* mark_debug = "True" *) input                   awready,
  (* mark_debug = "True" *) output [7:0]            awlen,
  (* mark_debug = "True" *) output [2:0]            awsize,
  (* mark_debug = "True" *) output [1:0]            awburst,



  output [3:0]            wid,
  (* mark_debug = "True" *) output [AXI_DWIDTH-1:0]   wdata,
  (* mark_debug = "True" *) output                    wvalid,
  (* mark_debug = "True" *) input                     wready,
  (* mark_debug = "True" *) output                    wlast,
  (* mark_debug = "True" *) output [AXI_DWIDTH/8-1:0] wstrb,



  input [3:0] bid,
  input [1:0] bresp,
  input       bvalid,
  output      bready,




  input                   core_read_request_valid,
  output                  core_read_request_ready,
  input  [AXI_AWIDTH-1:0] core_read_addr,
  input  [31:0]           core_read_len,
  input  [2:0]            core_read_size,
  input  [1:0]            core_read_burst,
  output [AXI_DWIDTH-1:0] core_read_data,
  output                  core_read_data_valid,
  input                   core_read_data_ready,



  input                   core_write_request_valid,
  output                  core_write_request_ready,
  input  [AXI_AWIDTH-1:0] core_write_addr,
  input  [31:0]           core_write_len,
  input  [2:0]            core_write_size,
  input  [1:0]            core_write_burst,
  input  [AXI_DWIDTH-1:0] core_write_data,
  input                   core_write_data_valid,
  output                  core_write_data_ready
);

  axi_mm_write #(.AXI_AWIDTH(AXI_AWIDTH), .AXI_DWIDTH(AXI_DWIDTH)) write_unit (
    .clk(clk),
    .resetn(resetn),


    .awid(awid),
    .awaddr(awaddr),
    .awvalid(awvalid),
    .awready(awready),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),


    .wid(wid),
    .wdata(wdata),
    .wvalid(wvalid),
    .wready(wready),
    .wlast(wlast),
    .wstrb(wstrb),


    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready),


    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready)
  );

  axi_mm_read #(.AXI_AWIDTH(AXI_AWIDTH), .AXI_DWIDTH(AXI_DWIDTH)) read_unit (
    .clk(clk),
    .resetn(resetn),


    .arid(arid),
    .araddr(araddr),
    .arvalid(arvalid),
    .arready(arready),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),


    .rid(rid),
    .rdata(rdata),
    .rvalid(rvalid),
    .rready(rready),
    .rlast(rlast),
    .rresp(rresp),


    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready)
  );

endmodule
module axi_mm_adapter #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter AXI_MAX_BURST_LEN = 256
) (
  input clk,
  input resetn,




  output [3:0]            arid,
  (* mark_debug = "True" *) output [AXI_AWIDTH-1:0] araddr,
  (* mark_debug = "True" *) output                  arvalid,
  (* mark_debug = "True" *) input                   arready,
  (* mark_debug = "True" *) output [7:0]            arlen,
  (* mark_debug = "True" *) output [2:0]            arsize,
  (* mark_debug = "True" *) output [1:0]            arburst,



  input  [3:0]            rid,
  (* mark_debug = "True" *) input  [AXI_DWIDTH-1:0] rdata,
  (* mark_debug = "True" *) input                   rvalid,
  (* mark_debug = "True" *) output                  rready,
  (* mark_debug = "True" *) input                   rlast,
  input  [1:0]            rresp,



  output [3:0]            awid,
  (* mark_debug = "True" *) output [AXI_AWIDTH-1:0] awaddr,
  (* mark_debug = "True" *) output                  awvalid,
  (* mark_debug = "True" *) input                   awready,
  (* mark_debug = "True" *) output [7:0]            awlen,
  (* mark_debug = "True" *) output [2:0]            awsize,
  (* mark_debug = "True" *) output [1:0]            awburst,



  output [3:0]            wid,
  (* mark_debug = "True" *) output [AXI_DWIDTH-1:0]   wdata,
  (* mark_debug = "True" *) output                    wvalid,
  (* mark_debug = "True" *) input                     wready,
  (* mark_debug = "True" *) output                    wlast,
  (* mark_debug = "True" *) output [AXI_DWIDTH/8-1:0] wstrb,



  input [3:0] bid,
  input [1:0] bresp,
  input       bvalid,
  output      bready,




  input                   core_read_request_valid,
  output                  core_read_request_ready,
  input  [AXI_AWIDTH-1:0] core_read_addr,
  input  [31:0]           core_read_len,
  input  [2:0]            core_read_size,
  input  [1:0]            core_read_burst,
  output [AXI_DWIDTH-1:0] core_read_data,
  output                  core_read_data_valid,
  input                   core_read_data_ready,



  input                   core_write_request_valid,
  output                  core_write_request_ready,
  input  [AXI_AWIDTH-1:0] core_write_addr,
  input  [31:0]           core_write_len,
  input  [2:0]            core_write_size,
  input  [1:0]            core_write_burst,
  input  [AXI_DWIDTH-1:0] core_write_data,
  input                   core_write_data_valid,
  output                  core_write_data_ready
);


  axi_mm_write #(.AXI_AWIDTH(AXI_AWIDTH), .AXI_DWIDTH(AXI_DWIDTH)) write_unit (
    .clk(clk),
    .resetn(resetn),


    .awid(awid),
    .awaddr(awaddr),
    .awvalid(awvalid),
    .awready(awready),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),


    .wid(wid),
    .wdata(wdata),
    .wvalid(wvalid),
    .wready(wready),
    .wlast(wlast),
    .wstrb(wstrb),


    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready),


    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready)
  );

  axi_mm_read #(.AXI_AWIDTH(AXI_AWIDTH), .AXI_DWIDTH(AXI_DWIDTH)) read_unit (
    .clk(clk),
    .resetn(resetn),


    .arid(arid),
    .araddr(araddr),
    .arvalid(arvalid),
    .arready(arready),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),


    .rid(rid),
    .rdata(rdata),
    .rvalid(rvalid),
    .rready(rready),
    .rlast(rlast),
    .rresp(rresp),


    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready)
  );

endmodule