data/full_repos/permissive/51918867/verilog/fmul_pipline2.v
data/verilator_xmls/4e099cbf-af7d-4203-b396-d43b4bfd0941.xml
module fmul_pipline2(
    input clk,
    input rst,


    input[64:0] x1,
    input[8:0]  base_ei,
    input       enable,


    output[64:0] x2,
    output[8:0]  base_eo,
    output       valid
);


wire       X1_s;
wire[8:0]  X1_exponent;
wire[63:0] X1_significand;

assign X1_s             = x1[64];
assign X1_exponent      = base_ei;
assign X1_significand   = x1[63:0];


reg       rX2_s;
reg[8:0]  rX2_exponent;
reg[63:0] rX2_significand;

reg _valid;


always@(posedge clk)
begin
    if (rst) begin
        rX2_s           <= 0;
        rX2_exponent    <= 0;
        rX2_significand <= 0;
    end
    else if (enable) begin
        if (X1_significand[23]) begin
            rX2_s           <= X1_s;
            rX2_exponent    <= X1_exponent;
            rX2_significand <= X1_significand + 64'h0000_0000_0080_0000;
        end
        else begin
            rX2_s           <= X1_s;
            rX2_exponent    <= X1_exponent;
            rX2_significand <= X1_significand;
        end
    end
    else begin
        rX2_s           <= rX2_s;
        rX2_exponent    <= rX2_exponent;
        rX2_significand <= rX2_significand;
    end
end


always@(posedge clk)
begin
    if (rst)
        _valid <= 1'b0;
    else
        _valid <= enable;
end

assign x2       = {rX2_s, rX2_significand[63:0]};
assign base_eo  = rX2_exponent;
assign valid    = _valid;


endmodule
module fmul_pipline2(
    input clk,
    input rst,


    input[64:0] x1,
    input[8:0]  base_ei,
    input       enable,


    output[64:0] x2,
    output[8:0]  base_eo,
    output       valid
);



wire       X1_s;
wire[8:0]  X1_exponent;
wire[63:0] X1_significand;

assign X1_s             = x1[64];
assign X1_exponent      = base_ei;
assign X1_significand   = x1[63:0];


reg       rX2_s;
reg[8:0]  rX2_exponent;
reg[63:0] rX2_significand;

reg _valid;


always@(posedge clk)
begin
    if (rst) begin
        rX2_s           <= 0;
        rX2_exponent    <= 0;
        rX2_significand <= 0;
    end
    else if (enable) begin
        if (X1_significand[23]) begin
            rX2_s           <= X1_s;
            rX2_exponent    <= X1_exponent;
            rX2_significand <= X1_significand + 64'h0000_0000_0080_0000;
        end
        else begin
            rX2_s           <= X1_s;
            rX2_exponent    <= X1_exponent;
            rX2_significand <= X1_significand;
        end
    end
    else begin
        rX2_s           <= rX2_s;
        rX2_exponent    <= rX2_exponent;
        rX2_significand <= rX2_significand;
    end
end


always@(posedge clk)
begin
    if (rst)
        _valid <= 1'b0;
    else
        _valid <= enable;
end

assign x2       = {rX2_s, rX2_significand[63:0]};
assign base_eo  = rX2_exponent;
assign valid    = _valid;


endmodule