data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv:59: Cannot find file containing module: 'addr_dec_resp_mux'\n  addr_dec_resp_mux #(\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect,data/full_repos/permissive/489147019/addr_dec_resp_mux\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect,data/full_repos/permissive/489147019/addr_dec_resp_mux.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect,data/full_repos/permissive/489147019/addr_dec_resp_mux.sv\n             addr_dec_resp_mux\n             addr_dec_resp_mux.v\n             addr_dec_resp_mux.sv\n             obj_dir/addr_dec_resp_mux\n             obj_dir/addr_dec_resp_mux.v\n             obj_dir/addr_dec_resp_mux.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv:99: Cannot find file containing module: 'rr_arb_tree'\n    rr_arb_tree #(\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module xbar #(
  parameter int unsigned NumIn           = 4,
  parameter int unsigned NumOut          = 4,
  parameter int unsigned ReqDataWidth    = 32,
  parameter int unsigned RespDataWidth   = 32,
  parameter int unsigned RespLat         = 1,
  parameter bit          WriteRespOn     = 1'b1,
  parameter bit          BroadCastOn     = 1'b0,
  parameter bit          ExtPrio         = 1'b0
) (
  input  logic                                  clk_i,
  input  logic                                  rst_ni,

  input  logic [NumOut-1:0][$clog2(NumIn)-1:0]  rr_i,

  input  logic [NumIn-1:0]                      req_i,
  input  logic [NumIn-1:0][$clog2(NumOut)-1:0]  add_i,
  input  logic [NumIn-1:0]                      wen_i,
  input  logic [NumIn-1:0][ReqDataWidth-1:0]    wdata_i,
  output logic [NumIn-1:0]                      gnt_o,
  output logic [NumIn-1:0]                      vld_o,
  output logic [NumIn-1:0][RespDataWidth-1:0]   rdata_o,

  input  logic [NumOut-1:0]                     gnt_i,
  output logic [NumOut-1:0]                     req_o,

  output logic [NumOut-1:0][ReqDataWidth-1:0]   wdata_o,

  input  logic [NumOut-1:0][RespDataWidth-1:0]  rdata_i
);





logic [NumOut-1:0][NumIn-1:0][ReqDataWidth-1:0] sl_data;
logic [NumIn-1:0][NumOut-1:0][ReqDataWidth-1:0] ma_data;
logic [NumOut-1:0][NumIn-1:0] sl_gnt, sl_req;
logic [NumIn-1:0][NumOut-1:0] ma_gnt, ma_req;




for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs
  addr_dec_resp_mux #(
    .NumOut        ( NumOut        ),
    .ReqDataWidth  ( ReqDataWidth  ),
    .RespDataWidth ( RespDataWidth ),
    .RespLat       ( RespLat       ),
    .BroadCastOn   ( BroadCastOn   ),
    .WriteRespOn   ( WriteRespOn   )
  ) i_addr_dec_resp_mux (
    .clk_i   ( clk_i      ),
    .rst_ni  ( rst_ni     ),
    .req_i   ( req_i[j]   ),
    .add_i   ( add_i[j]   ),
    .wen_i   ( wen_i[j]   ),
    .data_i  ( wdata_i[j] ),
    .gnt_o   ( gnt_o[j]   ),
    .vld_o   ( vld_o[j]   ),
    .rdata_o ( rdata_o[j] ),
    .req_o   ( ma_req[j]  ),
    .gnt_i   ( ma_gnt[j]  ),
    .data_o  ( ma_data[j] ),
    .rdata_i ( rdata_i    )
  );


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape
    assign sl_req[k][j]  = ma_req[j][k];
    assign ma_gnt[j][k]  = sl_gnt[k][j];
    assign sl_data[k][j] = ma_data[j][k];
  end
end




for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
  if (NumIn == unsigned'(1)) begin
    assign req_o[k]      = sl_req[k][0];
    assign sl_gnt[k][0]  = gnt_i[k];
    assign wdata_o[k]    = sl_data[k][0];
  end else begin : gen_rr_arb_tree
    rr_arb_tree #(
      .NumIn     ( NumIn        ),
      .DataWidth ( ReqDataWidth ),
      .ExtPrio   ( ExtPrio      )
    ) i_rr_arb_tree (
      .clk_i   ( clk_i      ),
      .rst_ni  ( rst_ni     ),
      .flush_i ( 1'b0       ),
      .rr_i    ( rr_i[k]    ),
      .req_i   ( sl_req[k]  ),
      .gnt_o   ( sl_gnt[k]  ),
      .data_i  ( sl_data[k] ),
      .gnt_i   ( gnt_i[k]   ),
      .req_o   ( req_o[k]   ),
      .data_o  ( wdata_o[k] ),
      .idx_o   (            )
    );
  end
end






initial begin
  assert(NumIn > 0) else
    $fatal(1,"NumIn needs to be larger than 0.");
  assert(NumOut > 0) else
    $fatal(1,"NumOut needs to be larger than 0.");
end


endmodule
module xbar #(
  parameter int unsigned NumIn           = 4,
  parameter int unsigned NumOut          = 4,
  parameter int unsigned ReqDataWidth    = 32,
  parameter int unsigned RespDataWidth   = 32,
  parameter int unsigned RespLat         = 1,
  parameter bit          WriteRespOn     = 1'b1,
  parameter bit          BroadCastOn     = 1'b0,
  parameter bit          ExtPrio         = 1'b0
) (
  input  logic                                  clk_i,
  input  logic                                  rst_ni,

  input  logic [NumOut-1:0][$clog2(NumIn)-1:0]  rr_i,

  input  logic [NumIn-1:0]                      req_i,
  input  logic [NumIn-1:0][$clog2(NumOut)-1:0]  add_i,
  input  logic [NumIn-1:0]                      wen_i,
  input  logic [NumIn-1:0][ReqDataWidth-1:0]    wdata_i,
  output logic [NumIn-1:0]                      gnt_o,
  output logic [NumIn-1:0]                      vld_o,
  output logic [NumIn-1:0][RespDataWidth-1:0]   rdata_o,

  input  logic [NumOut-1:0]                     gnt_i,
  output logic [NumOut-1:0]                     req_o,

  output logic [NumOut-1:0][ReqDataWidth-1:0]   wdata_o,

  input  logic [NumOut-1:0][RespDataWidth-1:0]  rdata_i
);






logic [NumOut-1:0][NumIn-1:0][ReqDataWidth-1:0] sl_data;
logic [NumIn-1:0][NumOut-1:0][ReqDataWidth-1:0] ma_data;
logic [NumOut-1:0][NumIn-1:0] sl_gnt, sl_req;
logic [NumIn-1:0][NumOut-1:0] ma_gnt, ma_req;




for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs
  addr_dec_resp_mux #(
    .NumOut        ( NumOut        ),
    .ReqDataWidth  ( ReqDataWidth  ),
    .RespDataWidth ( RespDataWidth ),
    .RespLat       ( RespLat       ),
    .BroadCastOn   ( BroadCastOn   ),
    .WriteRespOn   ( WriteRespOn   )
  ) i_addr_dec_resp_mux (
    .clk_i   ( clk_i      ),
    .rst_ni  ( rst_ni     ),
    .req_i   ( req_i[j]   ),
    .add_i   ( add_i[j]   ),
    .wen_i   ( wen_i[j]   ),
    .data_i  ( wdata_i[j] ),
    .gnt_o   ( gnt_o[j]   ),
    .vld_o   ( vld_o[j]   ),
    .rdata_o ( rdata_o[j] ),
    .req_o   ( ma_req[j]  ),
    .gnt_i   ( ma_gnt[j]  ),
    .data_o  ( ma_data[j] ),
    .rdata_i ( rdata_i    )
  );


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape
    assign sl_req[k][j]  = ma_req[j][k];
    assign ma_gnt[j][k]  = sl_gnt[k][j];
    assign sl_data[k][j] = ma_data[j][k];
  end
end




for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
  if (NumIn == unsigned'(1)) begin
    assign req_o[k]      = sl_req[k][0];
    assign sl_gnt[k][0]  = gnt_i[k];
    assign wdata_o[k]    = sl_data[k][0];
  end else begin : gen_rr_arb_tree
    rr_arb_tree #(
      .NumIn     ( NumIn        ),
      .DataWidth ( ReqDataWidth ),
      .ExtPrio   ( ExtPrio      )
    ) i_rr_arb_tree (
      .clk_i   ( clk_i      ),
      .rst_ni  ( rst_ni     ),
      .flush_i ( 1'b0       ),
      .rr_i    ( rr_i[k]    ),
      .req_i   ( sl_req[k]  ),
      .gnt_o   ( sl_gnt[k]  ),
      .data_i  ( sl_data[k] ),
      .gnt_i   ( gnt_i[k]   ),
      .req_o   ( req_o[k]   ),
      .data_o  ( wdata_o[k] ),
      .idx_o   (            )
    );
  end
end






initial begin
  assert(NumIn > 0) else
    $fatal(1,"NumIn needs to be larger than 0.");
  assert(NumOut > 0) else
    $fatal(1,"NumOut needs to be larger than 0.");
end


endmodule