data/full_repos/permissive/405799749/amg_new/mult/Unsigned/8/8/Simple_PPG/Wallace_tree/Carry_look-ahead_adder/module.v
data/verilator_xmls/ce7719b1-d539-4194-9332-65b22bd546d7.xml
module UBCLA_15_5_14_0 (S, X, Y);
  output [16:0] S;
  input [15:5] X;
  input [14:0] Y;
  wire [15:5] Z;
  UBExtender_14_5_1000 U0 (Z[15:5], Y[14:5]);
  UBPureCLA_15_5 U1 (S[16:5], X[15:5], Z[15:5]);
  UBCON_4_0 U2 (S[4:0], Y[4:0]);
endmodule
module UBCLA_15_5_14_0 (S, X, Y);

  output [16:0] S;
  input [15:5] X;
  input [14:0] Y;
  wire [15:5] Z;
  UBExtender_14_5_1000 U0 (Z[15:5], Y[14:5]);
  UBPureCLA_15_5 U1 (S[16:5], X[15:5], Z[15:5]);
  UBCON_4_0 U2 (S[4:0], Y[4:0]);
endmodule