data/full_repos/permissive/455421905/test/tb_even_odd.v
1: b'%Error: data/full_repos/permissive/455421905/test/tb_even_odd.v:18: Cannot find include file: even_odd.v\n`include "even_odd.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/test,data/full_repos/permissive/455421905/even_odd.v\n             data/full_repos/permissive/455421905/test,data/full_repos/permissive/455421905/even_odd.v.v\n             data/full_repos/permissive/455421905/test,data/full_repos/permissive/455421905/even_odd.v.sv\n             even_odd.v\n             even_odd.v.v\n             even_odd.v.sv\n             obj_dir/even_odd.v\n             obj_dir/even_odd.v.v\n             obj_dir/even_odd.v.sv\n%Error: data/full_repos/permissive/455421905/test/tb_even_odd.v:19: Cannot find include file: utils.v\n`include "utils.v" \n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/455421905/test/tb_even_odd.v:31: Unsupported: Ignoring delay on this delayed statement.\n  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/455421905/test/tb_even_odd.v:32: Unsupported: Ignoring delay on this delayed statement.\n  reg RST; initial begin RST=1; #400 RST=0; end\n                                ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module tb_even_odd();

  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end

  wire [(`DATW<<`P_LOG)-1:0] init_data;
  wire [(`DATW<<`P_LOG)-1:0] chk_rslt;

  reg                        finish;

  reg  [(`DATW<<`P_LOG)-1:0] DIN;
  reg                        DINEN;

  wire [(`DATW<<`P_LOG)-1:0] DOT;
  wire                       DOTEN;

  EVEN_ODD #(`P_LOG, `FLOAT, `SIGNED, `DATW, `KEYW) even_odd(CLK, RST, DIN, DINEN, DOT, DOTEN);

  genvar i;
  generate
    for (i=0; i<(1<<`P_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_data_key = (1<<`P_LOG) - i;
      wire [`KEYW-1:0] chk_rslt_key  = i + 1;
      if (`PAYW == 0) begin
        assign init_data[`DATW*(i+1)-1:`DATW*i] = init_data_key;
        assign chk_rslt[`DATW*(i+1)-1:`DATW*i]  = chk_rslt_key;
      end else begin
        wire [`PAYW-1:0] init_data_payload = i + 1;
        wire [`PAYW-1:0] chk_rslt_payload  = (1<<`P_LOG) - i;
        assign init_data[`DATW*(i+1)-1:`DATW*i] = {init_data_payload, init_data_key};
        assign chk_rslt[`DATW*(i+1)-1:`DATW*i]  = {chk_rslt_payload, chk_rslt_key};
      end
      always @(posedge CLK) if (DOTEN) $write("%d ", DOT[(`KEYW+`DATW*i)-1:`DATW*i]);
    end
  endgenerate

  always @(posedge CLK) begin
    if (RST) begin
      DIN    <= init_data;
      DINEN  <= 1;
      finish <= 0;
    end else begin
      DINEN  <= 0;
      finish <= DOTEN;
      if (DOTEN && (chk_rslt != DOT)) $write("ERROR!!\n");
      if (finish) begin
        $write("\n");
        $finish();
      end
    end
  end

endmodule
module tb_even_odd();


  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end

  wire [(`DATW<<`P_LOG)-1:0] init_data;
  wire [(`DATW<<`P_LOG)-1:0] chk_rslt;

  reg                        finish;

  reg  [(`DATW<<`P_LOG)-1:0] DIN;
  reg                        DINEN;

  wire [(`DATW<<`P_LOG)-1:0] DOT;
  wire                       DOTEN;

  EVEN_ODD #(`P_LOG, `FLOAT, `SIGNED, `DATW, `KEYW) even_odd(CLK, RST, DIN, DINEN, DOT, DOTEN);

  genvar i;
  generate
    for (i=0; i<(1<<`P_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_data_key = (1<<`P_LOG) - i;
      wire [`KEYW-1:0] chk_rslt_key  = i + 1;
      if (`PAYW == 0) begin
        assign init_data[`DATW*(i+1)-1:`DATW*i] = init_data_key;
        assign chk_rslt[`DATW*(i+1)-1:`DATW*i]  = chk_rslt_key;
      end else begin
        wire [`PAYW-1:0] init_data_payload = i + 1;
        wire [`PAYW-1:0] chk_rslt_payload  = (1<<`P_LOG) - i;
        assign init_data[`DATW*(i+1)-1:`DATW*i] = {init_data_payload, init_data_key};
        assign chk_rslt[`DATW*(i+1)-1:`DATW*i]  = {chk_rslt_payload, chk_rslt_key};
      end
      always @(posedge CLK) if (DOTEN) $write("%d ", DOT[(`KEYW+`DATW*i)-1:`DATW*i]);
    end
  endgenerate

  always @(posedge CLK) begin
    if (RST) begin
      DIN    <= init_data;
      DINEN  <= 1;
      finish <= 0;
    end else begin
      DINEN  <= 0;
      finish <= DOTEN;
      if (DOTEN && (chk_rslt != DOT)) $write("ERROR!!\n");
      if (finish) begin
        $write("\n");
        $finish();
      end
    end
  end

endmodule