data/full_repos/permissive/439514885/testbench/mem16384x96.v
data/verilator_xmls/5e4b10aa-2f35-4a80-9a65-e05b9e4ac1e3.xml
module mem16384x96(

   rdata,


   clk,
   ceb,
   web,
   addr,
   wdata
);

output[95:0] rdata;

input clk;
input ceb;
input web;
input[13:0] addr;
input[95:0] wdata;

reg[95:0] mem[0:16383];
reg[95:0] rdata;



always @(posedge clk)
   begin
      if (!ceb & !web)
         begin
            mem[addr] <= wdata;
         end
   end

always @(posedge clk)
   begin
       if (!ceb & web)
          begin
             rdata <= mem[addr];
          end
   end

endmodule
module mem16384x96(

   rdata,


   clk,
   ceb,
   web,
   addr,
   wdata
);


output[95:0] rdata;

input clk;
input ceb;
input web;
input[13:0] addr;
input[95:0] wdata;

reg[95:0] mem[0:16383];
reg[95:0] rdata;



always @(posedge clk)
   begin
      if (!ceb & !web)
         begin
            mem[addr] <= wdata;
         end
   end

always @(posedge clk)
   begin
       if (!ceb & web)
          begin
             rdata <= mem[addr];
          end
   end

endmodule