data/full_repos/permissive/516359259/APB_slave.v
data/verilator_xmls/e3ef0f28-8a71-4ee8-bb0f-6e9d87e663ae.xml
module APB_slave(input PCLK,
                 input PRESETn,
                 input [4:0] PADDR,
                 input PSELx,
                 input PENABLE,
                 input PWRITE,
                 input [31:0]PWDATA,
                 output reg PREADY,
                 output reg [31:0] PRDATA,
                 output reg PSLVERR = 0);
    
    reg [31:0] mem [0:31];
    
    reg [31:0] temp_data;
    
    always @(*) begin
        if (!PRESETn)
        begin
            PREADY  = 0;
            PSLVERR = 0;
        end
        else
        begin
            if (PSELx && !PENABLE && !PWRITE) begin
                PREADY = 0;
            end
            else if (PSELx && PENABLE && !PWRITE) begin
                PREADY = 1;
                PRDATA = mem[PADDR];
            end
            else if (PSELx && !PENABLE && PWRITE) begin
                PREADY = 0;
            end
            else if (PSELx && PENABLE && PWRITE) begin
                PREADY     = 1;
                mem[PADDR] = PWDATA;
            end
            else
                PREADY = 0;
        end
    end
    
    
endmodule
module APB_slave(input PCLK,
                 input PRESETn,
                 input [4:0] PADDR,
                 input PSELx,
                 input PENABLE,
                 input PWRITE,
                 input [31:0]PWDATA,
                 output reg PREADY,
                 output reg [31:0] PRDATA,
                 output reg PSLVERR = 0);

    
    reg [31:0] mem [0:31];
    
    reg [31:0] temp_data;
    
    always @(*) begin
        if (!PRESETn)
        begin
            PREADY  = 0;
            PSLVERR = 0;
        end
        else
        begin
            if (PSELx && !PENABLE && !PWRITE) begin
                PREADY = 0;
            end
            else if (PSELx && PENABLE && !PWRITE) begin
                PREADY = 1;
                PRDATA = mem[PADDR];
            end
            else if (PSELx && !PENABLE && PWRITE) begin
                PREADY = 0;
            end
            else if (PSELx && PENABLE && PWRITE) begin
                PREADY     = 1;
                mem[PADDR] = PWDATA;
            end
            else
                PREADY = 0;
        end
    end
    
    
endmodule