data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:27: Unsupported: Ignoring delay on this delayed statement.\nalways #50ns clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:32: syntax error, unexpected \'@\'\n    repeat(5) @(negedge clock);\n              ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:34: syntax error, unexpected \'@\'\n    repeat(5) @(negedge clock);\n              ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:36: Unsupported: fork statements\n        fork\n        ^~~~\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:43: Unsupported: wait statements\n        wait(|fin == 1);\n        ^~~~\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:44: syntax error, unexpected \'@\'\n        @(negedge clock);\n        ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:46: syntax error, unexpected \'@\'\n    repeat(5) @(negedge clock);\n              ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:52: syntax error, unexpected \'@\'\n    @(negedge clock);\n    ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:56: Unsupported: wait statements\n    wait (grant[i] == 1);\n    ^~~~\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:57: syntax error, unexpected \'@\'\n    repeat(5) @(negedge clock);\n              ^\n%Error: data/full_repos/permissive/494664634/PacketRRArbiter/src/sim/PacketRRArbiter_tb.sv:60: syntax error, unexpected \'@\'\n    @(negedge clock);\n    ^\n%Error: Exiting due to 10 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PacketRRArbiter_tb();
bit clock=0, reset=1;
bit [3:0] req, fin, grant;
bit ready=1;
always #50ns clock = ~clock;

PacketRRArbiter DUT(.*);

initial begin
    repeat(5) @(negedge clock);
    reset = 0;
    repeat(5) @(negedge clock);
    for (int i=0; i<4; i++) begin
        fork
            automatic int j = i;
            my_thread(j);
        join_none
    end
    
    repeat(4) begin
        wait(|fin == 1);
        @(negedge clock);
    end
    repeat(5) @(negedge clock);
    $finish;
    
end

task automatic my_thread(int i);
    @(negedge clock);
    req[i] = 1;


    wait (grant[i] == 1);
    repeat(5) @(negedge clock);
    fin[i] = 1;
    req[i] = 0;
    @(negedge clock);
    fin[i] = 0;
    
endtask

endmodule
module PacketRRArbiter_tb();

bit clock=0, reset=1;
bit [3:0] req, fin, grant;
bit ready=1;
always #50ns clock = ~clock;

PacketRRArbiter DUT(.*);

initial begin
    repeat(5) @(negedge clock);
    reset = 0;
    repeat(5) @(negedge clock);
    for (int i=0; i<4; i++) begin
        fork
            automatic int j = i;
            my_thread(j);
        join_none
    end
    
    repeat(4) begin
        wait(|fin == 1);
        @(negedge clock);
    end
    repeat(5) @(negedge clock);
    $finish;
    
end

task automatic my_thread(int i);
    @(negedge clock);
    req[i] = 1;


    wait (grant[i] == 1);
    repeat(5) @(negedge clock);
    fin[i] = 1;
    req[i] = 0;
    @(negedge clock);
    fin[i] = 0;
    
endtask

endmodule