data/full_repos/permissive/531012469/verilog/rtl/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:368: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            1 : r_result =  in1 <  in2;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:369: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            2 : r_result = sin1 < sin2;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:256: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'cnt_start\' generates 12 bits.\n                                                                           : ... In instance rvcorep.ploader.serc\n          stage <= (cnt_start == (waitcnt >> 1)) ? \'d1 : stage;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:484: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire w_bmis = ExMa_b & (ExMa_b_rslt ? ExMa_b_rslt_t1 : ExMa_b_rslt_t2);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:485: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [17:0] w_pc_true = {((ExMa_b_rslt) ? ExMa_tkn_pc[17:2]: ExMa_npc[17:2]), 2\'b00};\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:491: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign I_ADDR = {w_npc, 2\'b00};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:623: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[1]) ? IfId_pc + {IfId_ir[31:12], 12\'b0} :   \n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:624: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[2]) ? IfId_pc + 4                       : 0;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IdEx_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:711: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [7:0]  w_lb_t = D_IN >> ({w_adr, 3\'d0});\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:760: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'MaWb_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n        else r_rout <= (MaWb_v) ? MaWb_pc : r_rout;  \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:58: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'initwe\' generates 4 bits.\n                                                                          : ... In instance rvcorep\n        initaddr <= (r_rst) ? 0 : (initwe)   ? initaddr + 4 : initaddr;\n                                             ^\n%Error: Exiting due to 13 warning(s)\n'
module decoder_id(ir, alu_ctrl, bru_ctrl, imm);
    input  wire [31:0] ir;
    output reg  [ 9:0] alu_ctrl;
    output reg  [ 6:0] bru_ctrl;
    output wire [31:0] imm;
    
    wire [4:0] op     = ir[ 6: 2];
    wire [2:0] funct3 = ir[14:12];
    wire [6:0] funct7 = ir[31:25];

    wire r_type = (op==5'b01100);
    wire s_type = (op[4:2]==3'b010);
    wire b_type = (op==5'b11000);
    wire j_type = (op==5'b11011);
    wire u_type = ({op[4], op[2:0]} ==4'b0101);
    wire i_type = (op==5'b11001 || op==5'b00000 || op==5'b00100);

    wire [31:0] imm_U = (u_type) ? {ir[31:12], 12'b0} : 0;
    wire [31:0] imm_I = (i_type) ? {{21{ir[31]}}, ir[30:20]} : 0;
    wire [31:0] imm_S = (s_type) ? {{21{ir[31]}}, ir[30:25], ir[11:7]} : 0;
    wire [31:0] imm_B = (b_type) ? {{20{ir[31]}}, ir[7], ir[30:25] ,ir[11:8], 1'b0} : 0;
    wire [31:0] imm_J = (j_type) ? {{12{ir[31]}}, ir[19:12], ir[20], ir[30:21], 1'b0} : 0;
    assign imm = imm_U ^ imm_I ^ imm_S ^ imm_B ^ imm_J;

    reg [3:0] r_alu_ctrl;
    always @(*) begin
        case(op)
            5'b01100 : r_alu_ctrl = {funct7[5], funct3}; 
            5'b00100 : r_alu_ctrl = (funct3==3'h5) ? {funct7[5], funct3} : {1'b0, funct3};
            default  : r_alu_ctrl = 4'b1111;
        endcase
    end

    always @(*) begin
        case(r_alu_ctrl)
            `ALU_CTRL_SLTU__ : alu_ctrl = 1;
            `ALU_CTRL_SLT___ : alu_ctrl = 2;
            `ALU_CTRL_ADD___ : alu_ctrl = 3;
            `ALU_CTRL_SUB___ : alu_ctrl = 4;
            `ALU_CTRL_XOR___ : alu_ctrl = 5;
            `ALU_CTRL_OR____ : alu_ctrl = 6;
            `ALU_CTRL_AND___ : alu_ctrl = 7;
            `ALU_CTRL_SLL___ : alu_ctrl = 8;
            `ALU_CTRL_SRL___ : alu_ctrl = 9;
            `ALU_CTRL_SRA___ : alu_ctrl = 10;
            default          : alu_ctrl = 0;
        endcase
    end
    
    always @(*) begin
        case(op)
            5'b11011 : bru_ctrl =                    7'b1000000;
            5'b11001 : bru_ctrl =                    7'b1000000;
            5'b11000 : bru_ctrl = (funct3==3'b000) ? 7'b0000001 :
                                  (funct3==3'b001) ? 7'b0000010 :
                                  (funct3==3'b100) ? 7'b0000100 :
                                  (funct3==3'b101) ? 7'b0001000 :
                                  (funct3==3'b110) ? 7'b0010000 :
                                  (funct3==3'b111) ? 7'b0100000 : 0;
            default : bru_ctrl = 0;
        endcase
    end
endmodule
module decoder_id(ir, alu_ctrl, bru_ctrl, imm);

    input  wire [31:0] ir;
    output reg  [ 9:0] alu_ctrl;
    output reg  [ 6:0] bru_ctrl;
    output wire [31:0] imm;
    
    wire [4:0] op     = ir[ 6: 2];
    wire [2:0] funct3 = ir[14:12];
    wire [6:0] funct7 = ir[31:25];

    wire r_type = (op==5'b01100);
    wire s_type = (op[4:2]==3'b010);
    wire b_type = (op==5'b11000);
    wire j_type = (op==5'b11011);
    wire u_type = ({op[4], op[2:0]} ==4'b0101);
    wire i_type = (op==5'b11001 || op==5'b00000 || op==5'b00100);

    wire [31:0] imm_U = (u_type) ? {ir[31:12], 12'b0} : 0;
    wire [31:0] imm_I = (i_type) ? {{21{ir[31]}}, ir[30:20]} : 0;
    wire [31:0] imm_S = (s_type) ? {{21{ir[31]}}, ir[30:25], ir[11:7]} : 0;
    wire [31:0] imm_B = (b_type) ? {{20{ir[31]}}, ir[7], ir[30:25] ,ir[11:8], 1'b0} : 0;
    wire [31:0] imm_J = (j_type) ? {{12{ir[31]}}, ir[19:12], ir[20], ir[30:21], 1'b0} : 0;
    assign imm = imm_U ^ imm_I ^ imm_S ^ imm_B ^ imm_J;

    reg [3:0] r_alu_ctrl;
    always @(*) begin
        case(op)
            5'b01100 : r_alu_ctrl = {funct7[5], funct3}; 
            5'b00100 : r_alu_ctrl = (funct3==3'h5) ? {funct7[5], funct3} : {1'b0, funct3};
            default  : r_alu_ctrl = 4'b1111;
        endcase
    end

    always @(*) begin
        case(r_alu_ctrl)
            `ALU_CTRL_SLTU__ : alu_ctrl = 1;
            `ALU_CTRL_SLT___ : alu_ctrl = 2;
            `ALU_CTRL_ADD___ : alu_ctrl = 3;
            `ALU_CTRL_SUB___ : alu_ctrl = 4;
            `ALU_CTRL_XOR___ : alu_ctrl = 5;
            `ALU_CTRL_OR____ : alu_ctrl = 6;
            `ALU_CTRL_AND___ : alu_ctrl = 7;
            `ALU_CTRL_SLL___ : alu_ctrl = 8;
            `ALU_CTRL_SRL___ : alu_ctrl = 9;
            `ALU_CTRL_SRA___ : alu_ctrl = 10;
            default          : alu_ctrl = 0;
        endcase
    end
    
    always @(*) begin
        case(op)
            5'b11011 : bru_ctrl =                    7'b1000000;
            5'b11001 : bru_ctrl =                    7'b1000000;
            5'b11000 : bru_ctrl = (funct3==3'b000) ? 7'b0000001 :
                                  (funct3==3'b001) ? 7'b0000010 :
                                  (funct3==3'b100) ? 7'b0000100 :
                                  (funct3==3'b101) ? 7'b0001000 :
                                  (funct3==3'b110) ? 7'b0010000 :
                                  (funct3==3'b111) ? 7'b0100000 : 0;
            default : bru_ctrl = 0;
        endcase
    end
endmodule