data/full_repos/permissive/494117590/hdl_src/design/btfly_op.v
1: b"%Error: data/full_repos/permissive/494117590/hdl_src/design/btfly_op.v:84: Cannot find file containing module: 'cplx_mult'\ncplx_mult complex_mult_I(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494117590/hdl_src/design,data/full_repos/permissive/494117590/cplx_mult\n             data/full_repos/permissive/494117590/hdl_src/design,data/full_repos/permissive/494117590/cplx_mult.v\n             data/full_repos/permissive/494117590/hdl_src/design,data/full_repos/permissive/494117590/cplx_mult.sv\n             cplx_mult\n             cplx_mult.v\n             cplx_mult.sv\n             obj_dir/cplx_mult\n             obj_dir/cplx_mult.v\n             obj_dir/cplx_mult.sv\n%Error: data/full_repos/permissive/494117590/hdl_src/design/btfly_op.v:95: Cannot find file containing module: 'cplx_mult'\ncplx_mult complex_mult_II(\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module btfly_op(
  clk ,
  rst_n,

  i_u1_valid_in,
  o_u1_valid_out,
  i_s18_V0_R,  i_s18_V0_I, i_s18_V1_R, i_s18_V1_I,
  i_s18_T0_R,  i_s18_T0_I, i_s18_T1_R, i_s18_T1_I,

  o_s18_O0_R, o_s18_O0_I,
  o_s18_O1_R, o_s18_O1_I
);

input  clk ;
input  rst_n;

input  i_u1_valid_in;
output  o_u1_valid_out;
input signed [17:0] i_s18_V0_R,  i_s18_V0_I, i_s18_V1_R, i_s18_V1_I;
input signed [17:0] i_s18_T0_R,  i_s18_T0_I, i_s18_T1_R, i_s18_T1_I;

output signed [17:0]  o_s18_O0_R, o_s18_O0_I;
output signed [17:0]  o_s18_O1_R, o_s18_O1_I;








wire u1_complex_mult_I_valid, u1_complex_mult_II_valid;


wire signed [17:0] s18_T0V1_V0_R; 
wire signed [17:0] s18_T0V1_V0_I; 
wire signed [17:0] s18_T1V1_V0_R; 
wire signed [17:0] s18_T1V1_V0_I; 


wire signed [17:0] s18_T0V1_R_resized; 
wire signed [17:0] s18_T0V1_I_resized; 
wire signed [17:0] s18_T1V1_R_resized; 
wire signed [17:0] s18_T1V1_I_resized; 


wire signed [47:0] s48_T0V1_R;
wire signed [47:0] s48_T0V1_I;
wire signed [47:0] s48_T1V1_R;
wire signed [47:0] s48_T1V1_I;



reg signed  [17:0]   s18_V0_R_pipe_i ;
reg signed  [17:0]   s18_V0_R_pipe_ii;
reg signed  [17:0]   s18_V0_I_pipe_i ;
reg signed  [17:0]   s18_V0_I_pipe_ii;

assign o_u1_valid_out = u1_complex_mult_I_valid  || u1_complex_mult_II_valid;



assign s18_T0V1_R_resized = s48_T0V1_R[16+18-1:16];
assign s18_T0V1_I_resized = s48_T0V1_I[16+18-1:16];
assign s18_T1V1_R_resized = s48_T1V1_R[16+18-1:16];
assign s18_T1V1_I_resized = s48_T1V1_I[16+18-1:16];

assign s18_T0V1_V0_R  = s18_T0V1_R_resized + s18_V0_R_pipe_ii;
assign s18_T0V1_V0_I  = s18_T0V1_I_resized + s18_V0_I_pipe_ii;
assign s18_T1V1_V0_R  = s18_T1V1_R_resized + s18_V0_R_pipe_ii;
assign s18_T1V1_V0_I  = s18_T1V1_I_resized + s18_V0_I_pipe_ii;


assign o_s18_O0_R[17] = s18_T0V1_V0_R[17] ;
assign o_s18_O0_I[17] = s18_T0V1_V0_I[17];
assign o_s18_O1_R[17] = s18_T1V1_V0_R[17] ;
assign o_s18_O1_I[17] = s18_T1V1_V0_I[17];

assign o_s18_O0_R[16:0] = s18_T0V1_V0_R[17:1]; 
assign o_s18_O0_I[16:0] = s18_T0V1_V0_I[17:1];
assign o_s18_O1_R[16:0] = s18_T1V1_V0_R[17:1]; 
assign o_s18_O1_I[16:0] = s18_T1V1_V0_I[17:1];

cplx_mult complex_mult_I(
  .clk (clk),
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(u1_complex_mult_I_valid),
  .i_s18_AR(i_s18_V1_R), .i_s18_AI(i_s18_V1_I), 
  .i_s18_BR(i_s18_T0_R), .i_s18_BI(i_s18_T0_I),
  .o_s48_R(s48_T0V1_R),
  .o_s48_I(s48_T0V1_I)
);

cplx_mult complex_mult_II(
  .clk (clk),
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(u1_complex_mult_II_valid),
  .i_s18_AR(i_s18_V1_R), .i_s18_AI(i_s18_V1_I), 
  .i_s18_BR(i_s18_T1_R), .i_s18_BI(i_s18_T1_I),
  .o_s48_R(s48_T1V1_R),
  .o_s48_I(s48_T1V1_I)
);

always @(posedge clk ) begin
  if (!rst_n) begin


    s18_V0_R_pipe_i <= 0;
    s18_V0_R_pipe_ii <= 0;

    s18_V0_I_pipe_i <= 0;
    s18_V0_I_pipe_ii <= 0;

  end else begin 


    if( i_u1_valid_in ) begin

      s18_V0_R_pipe_i <= i_s18_V0_R;
      s18_V0_R_pipe_ii <= s18_V0_R_pipe_i;

      s18_V0_I_pipe_i <= i_s18_V0_I;
      s18_V0_I_pipe_ii <= s18_V0_I_pipe_i;

    end
  end
end

endmodule
module btfly_op(
  clk ,
  rst_n,

  i_u1_valid_in,
  o_u1_valid_out,
  i_s18_V0_R,  i_s18_V0_I, i_s18_V1_R, i_s18_V1_I,
  i_s18_T0_R,  i_s18_T0_I, i_s18_T1_R, i_s18_T1_I,

  o_s18_O0_R, o_s18_O0_I,
  o_s18_O1_R, o_s18_O1_I
);


input  clk ;
input  rst_n;

input  i_u1_valid_in;
output  o_u1_valid_out;
input signed [17:0] i_s18_V0_R,  i_s18_V0_I, i_s18_V1_R, i_s18_V1_I;
input signed [17:0] i_s18_T0_R,  i_s18_T0_I, i_s18_T1_R, i_s18_T1_I;

output signed [17:0]  o_s18_O0_R, o_s18_O0_I;
output signed [17:0]  o_s18_O1_R, o_s18_O1_I;








wire u1_complex_mult_I_valid, u1_complex_mult_II_valid;


wire signed [17:0] s18_T0V1_V0_R; 
wire signed [17:0] s18_T0V1_V0_I; 
wire signed [17:0] s18_T1V1_V0_R; 
wire signed [17:0] s18_T1V1_V0_I; 


wire signed [17:0] s18_T0V1_R_resized; 
wire signed [17:0] s18_T0V1_I_resized; 
wire signed [17:0] s18_T1V1_R_resized; 
wire signed [17:0] s18_T1V1_I_resized; 


wire signed [47:0] s48_T0V1_R;
wire signed [47:0] s48_T0V1_I;
wire signed [47:0] s48_T1V1_R;
wire signed [47:0] s48_T1V1_I;



reg signed  [17:0]   s18_V0_R_pipe_i ;
reg signed  [17:0]   s18_V0_R_pipe_ii;
reg signed  [17:0]   s18_V0_I_pipe_i ;
reg signed  [17:0]   s18_V0_I_pipe_ii;

assign o_u1_valid_out = u1_complex_mult_I_valid  || u1_complex_mult_II_valid;



assign s18_T0V1_R_resized = s48_T0V1_R[16+18-1:16];
assign s18_T0V1_I_resized = s48_T0V1_I[16+18-1:16];
assign s18_T1V1_R_resized = s48_T1V1_R[16+18-1:16];
assign s18_T1V1_I_resized = s48_T1V1_I[16+18-1:16];

assign s18_T0V1_V0_R  = s18_T0V1_R_resized + s18_V0_R_pipe_ii;
assign s18_T0V1_V0_I  = s18_T0V1_I_resized + s18_V0_I_pipe_ii;
assign s18_T1V1_V0_R  = s18_T1V1_R_resized + s18_V0_R_pipe_ii;
assign s18_T1V1_V0_I  = s18_T1V1_I_resized + s18_V0_I_pipe_ii;


assign o_s18_O0_R[17] = s18_T0V1_V0_R[17] ;
assign o_s18_O0_I[17] = s18_T0V1_V0_I[17];
assign o_s18_O1_R[17] = s18_T1V1_V0_R[17] ;
assign o_s18_O1_I[17] = s18_T1V1_V0_I[17];

assign o_s18_O0_R[16:0] = s18_T0V1_V0_R[17:1]; 
assign o_s18_O0_I[16:0] = s18_T0V1_V0_I[17:1];
assign o_s18_O1_R[16:0] = s18_T1V1_V0_R[17:1]; 
assign o_s18_O1_I[16:0] = s18_T1V1_V0_I[17:1];

cplx_mult complex_mult_I(
  .clk (clk),
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(u1_complex_mult_I_valid),
  .i_s18_AR(i_s18_V1_R), .i_s18_AI(i_s18_V1_I), 
  .i_s18_BR(i_s18_T0_R), .i_s18_BI(i_s18_T0_I),
  .o_s48_R(s48_T0V1_R),
  .o_s48_I(s48_T0V1_I)
);

cplx_mult complex_mult_II(
  .clk (clk),
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(u1_complex_mult_II_valid),
  .i_s18_AR(i_s18_V1_R), .i_s18_AI(i_s18_V1_I), 
  .i_s18_BR(i_s18_T1_R), .i_s18_BI(i_s18_T1_I),
  .o_s48_R(s48_T1V1_R),
  .o_s48_I(s48_T1V1_I)
);

always @(posedge clk ) begin
  if (!rst_n) begin


    s18_V0_R_pipe_i <= 0;
    s18_V0_R_pipe_ii <= 0;

    s18_V0_I_pipe_i <= 0;
    s18_V0_I_pipe_ii <= 0;

  end else begin 


    if( i_u1_valid_in ) begin

      s18_V0_R_pipe_i <= i_s18_V0_R;
      s18_V0_R_pipe_ii <= s18_V0_R_pipe_i;

      s18_V0_I_pipe_i <= i_s18_V0_I;
      s18_V0_I_pipe_ii <= s18_V0_I_pipe_i;

    end
  end
end

endmodule