data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_r_dcm.v
data/verilator_xmls/0f832701-6dc1-498d-8b23-dfc4751f6f20.xml
module dcm_panel_pair(

   so, bank_hit, rd_data0, rd_data1, 

   cam_en, inv_mask0, inv_mask1, rclk, rd_en, rst_l, rst_tri_en, 
   rst_warm, rw_addr0, rw_addr1, sehold, wr_data0, wr_data1, wr_en, 
   si, se
   );

input [1:0]             cam_en;                 
input [7:0]             inv_mask0;              
input [7:0]             inv_mask1;              
input                   rclk;                   
input [1:0]             rd_en;                  
input                   rst_l;                
input                   rst_tri_en;           
input                   rst_warm;             
input [5:0]             rw_addr0;               
input [5:0]             rw_addr1;               
input                   sehold;               
input [32:0]            wr_data0;               
input [32:0]            wr_data1;               
input [1:0]             wr_en;                  
input			si,se ;

output			so;
output [31:0]           bank_hit;              
output [31:0]           rd_data0;               
output [31:0]           rd_data1;               

wire	[31:0]	lkup_hit0, lkup_hit1;
reg	rst_warm_d;


always  @(posedge rclk)
begin
	rst_warm_d <= ( sehold)? rst_warm_d : rst_warm;
end



        dcm_panel       panel0(.si(),
			       .so(),
			       .se(se),


                               .lkup_hit(lkup_hit0[31:0]),
                               .rd_data (rd_data0[31:0]),

                               .rd_en   (rd_en[0]),
                               .wr_en   (wr_en[0]),
                               .cam_en  (cam_en[0]),
                               .wr_data (wr_data0[32:0]),
                               .rw_addr (rw_addr0[5:0]),
                               .inv_mask(inv_mask0[7:0]),
                               .rst_l   (rst_l),
                               .rclk    (rclk),
                               .rst_warm(rst_warm_d),
                               .rst_tri_en(rst_tri_en),
                               .sehold  (sehold));

        assign   bank_hit      =    lkup_hit0 | lkup_hit1 ;

        dcm_panel       panel1(.si(),
                               .so(),
                               .se(se),


                               .lkup_hit(lkup_hit1[31:0]),
                               .rd_data (rd_data1[31:0]),

                               .rd_en   (rd_en[1]),
                               .wr_en   (wr_en[1]),
                               .cam_en  (cam_en[1]),
                               .wr_data (wr_data1[32:0]),
                               .rw_addr (rw_addr1[5:0]),
                               .inv_mask(inv_mask1[7:0]),
                               .rst_l   (rst_l),
                               .rclk    (rclk),
                               .rst_warm(rst_warm_d),
                               .rst_tri_en(rst_tri_en),
                               .sehold  (sehold));


endmodule
module dcm_panel_pair(

   so, bank_hit, rd_data0, rd_data1, 

   cam_en, inv_mask0, inv_mask1, rclk, rd_en, rst_l, rst_tri_en, 
   rst_warm, rw_addr0, rw_addr1, sehold, wr_data0, wr_data1, wr_en, 
   si, se
   );


input [1:0]             cam_en;                 
input [7:0]             inv_mask0;              
input [7:0]             inv_mask1;              
input                   rclk;                   
input [1:0]             rd_en;                  
input                   rst_l;                
input                   rst_tri_en;           
input                   rst_warm;             
input [5:0]             rw_addr0;               
input [5:0]             rw_addr1;               
input                   sehold;               
input [32:0]            wr_data0;               
input [32:0]            wr_data1;               
input [1:0]             wr_en;                  
input			si,se ;

output			so;
output [31:0]           bank_hit;              
output [31:0]           rd_data0;               
output [31:0]           rd_data1;               

wire	[31:0]	lkup_hit0, lkup_hit1;
reg	rst_warm_d;


always  @(posedge rclk)
begin
	rst_warm_d <= ( sehold)? rst_warm_d : rst_warm;
end



        dcm_panel       panel0(.si(),
			       .so(),
			       .se(se),


                               .lkup_hit(lkup_hit0[31:0]),
                               .rd_data (rd_data0[31:0]),

                               .rd_en   (rd_en[0]),
                               .wr_en   (wr_en[0]),
                               .cam_en  (cam_en[0]),
                               .wr_data (wr_data0[32:0]),
                               .rw_addr (rw_addr0[5:0]),
                               .inv_mask(inv_mask0[7:0]),
                               .rst_l   (rst_l),
                               .rclk    (rclk),
                               .rst_warm(rst_warm_d),
                               .rst_tri_en(rst_tri_en),
                               .sehold  (sehold));

        assign   bank_hit      =    lkup_hit0 | lkup_hit1 ;

        dcm_panel       panel1(.si(),
                               .so(),
                               .se(se),


                               .lkup_hit(lkup_hit1[31:0]),
                               .rd_data (rd_data1[31:0]),

                               .rd_en   (rd_en[1]),
                               .wr_en   (wr_en[1]),
                               .cam_en  (cam_en[1]),
                               .wr_data (wr_data1[32:0]),
                               .rw_addr (rw_addr1[5:0]),
                               .inv_mask(inv_mask1[7:0]),
                               .rst_l   (rst_l),
                               .rclk    (rclk),
                               .rst_warm(rst_warm_d),
                               .rst_tri_en(rst_tri_en),
                               .sehold  (sehold));


endmodule