data/full_repos/permissive/518460376/verilog/rtl/ips/adv_dbg_if/rtl/syncflop.v
data/verilator_xmls/2a5853b0-67a9-4c01-bee3-2dc9b1d0adf6.xml
module syncflop(
                DEST_CLK,
		D_SET,
		D_RST,
		RESETN,
                TOGGLE_IN,
                D_OUT
		);


   input   DEST_CLK;
   input   D_SET;
   input   D_RST;
   input   RESETN;
   input   TOGGLE_IN;
   output  D_OUT;

   reg 	   sync1;
   reg 	   sync2;
   reg 	   syncprev;
   reg 	   srflop;
   
   wire    syncxor;
   wire    srinput;
   wire    D_OUT;


   assign  syncxor = sync2 ^ syncprev;
   assign  srinput = syncxor | D_SET;  
   assign  D_OUT = srflop | syncxor;
 	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) sync1 <= 1'b0;
	else sync1 <= TOGGLE_IN;
     end

	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) sync2 <= 1'b0;
	else sync2 <= sync1;
     end

	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) syncprev <= 1'b0;
	else syncprev <= sync2;
     end

   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN)         srflop <= 1'b0;
	else if(D_RST)    srflop <= 1'b0;
	else if (srinput) srflop <= 1'b1;
     end
   

endmodule
module syncflop(
                DEST_CLK,
		D_SET,
		D_RST,
		RESETN,
                TOGGLE_IN,
                D_OUT
		);



   input   DEST_CLK;
   input   D_SET;
   input   D_RST;
   input   RESETN;
   input   TOGGLE_IN;
   output  D_OUT;

   reg 	   sync1;
   reg 	   sync2;
   reg 	   syncprev;
   reg 	   srflop;
   
   wire    syncxor;
   wire    srinput;
   wire    D_OUT;


   assign  syncxor = sync2 ^ syncprev;
   assign  srinput = syncxor | D_SET;  
   assign  D_OUT = srflop | syncxor;
 	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) sync1 <= 1'b0;
	else sync1 <= TOGGLE_IN;
     end

	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) sync2 <= 1'b0;
	else sync2 <= sync1;
     end

	   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN) syncprev <= 1'b0;
	else syncprev <= sync2;
     end

   

   always @ (posedge DEST_CLK or negedge RESETN)
     begin
	if(~RESETN)         srflop <= 1'b0;
	else if(D_RST)    srflop <= 1'b0;
	else if (srinput) srflop <= 1'b1;
     end
   

endmodule