data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module RAM64M 
       (input [5:0]ADDRA,
        input [5:0]ADDRB,
        input [5:0]ADDRC,
        input [5:0]ADDRD,
        input DIA,
        input DIB,
        input DIC,
        input DID,
        output DOA,
        output DOB,
        output DOC,
        output DOD,
        input WCLK,
        input WE);

	parameter INIT_A = 64'b0;
	parameter INIT_B = 64'b0;
	parameter INIT_C = 64'b0;
	parameter INIT_D = 64'b0;
	parameter IS_WCLK_INVERTED=0;

	reg [63:0]r_0;
	reg [63:0]r_1;
	reg [63:0]r_2;
	reg [63:0]r_3;
	assign DOA = r_0[ADDRA];
	assign DOB = r_1[ADDRB];
	assign DOC = r_2[ADDRC];
	assign DOD = r_3[ADDRD];

	always @(posedge WCLK)
	if (WE) begin
		r_0[ADDRD] <= DIA;
		r_1[ADDRD] <= DIB;
		r_2[ADDRD] <= DIC;
		r_3[ADDRD] <= DID;
	end

endmodule
module RAM64M 
       (input [5:0]ADDRA,
        input [5:0]ADDRB,
        input [5:0]ADDRC,
        input [5:0]ADDRD,
        input DIA,
        input DIB,
        input DIC,
        input DID,
        output DOA,
        output DOB,
        output DOC,
        output DOD,
        input WCLK,
        input WE);


	parameter INIT_A = 64'b0;
	parameter INIT_B = 64'b0;
	parameter INIT_C = 64'b0;
	parameter INIT_D = 64'b0;
	parameter IS_WCLK_INVERTED=0;

	reg [63:0]r_0;
	reg [63:0]r_1;
	reg [63:0]r_2;
	reg [63:0]r_3;
	assign DOA = r_0[ADDRA];
	assign DOB = r_1[ADDRB];
	assign DOC = r_2[ADDRC];
	assign DOD = r_3[ADDRD];

	always @(posedge WCLK)
	if (WE) begin
		r_0[ADDRD] <= DIA;
		r_1[ADDRD] <= DIB;
		r_2[ADDRD] <= DIC;
		r_3[ADDRD] <= DID;
	end

endmodule