data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v
1: b"%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:20: Expecting include filename. Found: SYMBOL\n  initial begin \n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:18: Define or directive not defined: '`VFRAG'\n `VFRAG\n ^~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:20: syntax error, unexpected begin\n   begin\n   ^~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:33: Unsupported or unknown PLI call: $init_sigs\n    $init_sigs(`TOP_TYPE);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:33: Define or directive not defined: '`TOP_TYPE'\n    $init_sigs(`TOP_TYPE);\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:41: Unsupported or unknown PLI call: $dumpon\n          $dumpon;\n          ^~~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:41: syntax error, unexpected ${ignored-bbox-sys}\n          $dumpon;\n                 ^\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:49: syntax error, unexpected <=, expecting IDENTIFIER\n        vcdon <= 1;\n              ^~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:55: Unsupported or unknown PLI call: $tick\n    $tick(exit);\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:63: Unsupported or unknown PLI call: $dumpoff\n        $dumpoff;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/replay.v:63: syntax error, unexpected ${ignored-bbox-sys}\n        $dumpoff;\n                ^\n%Error: Cannot continue\n"
module replay;
  reg clock = 1'b0;
  reg reset = 1'b1;
  reg exit = 1'b0;
  reg [64:0] cycles = 0;

`ifdef VCS 
  always #(`CLOCK_PERIOD / 2.0) clock = ~clock;

  reg vcdon = 1'b0;
  reg [1023:0] vcdfile = 0;
  reg [1023:0] vcdplusfile = 0;
`endif


`include `VFRAG

  initial begin
`ifdef VCS
    if ($value$plusargs("vcdfile=%s", vcdfile))
    begin
      $dumpfile(vcdfile);
      $dumpvars(0, `TOP_TYPE);
      $dumpoff;
    end
    if ($value$plusargs("waveform=%s", vcdplusfile))
    begin
      $vcdplusfile(vcdplusfile);
    end
`endif
    $init_sigs(`TOP_TYPE);
  end

  always @(posedge clock) begin
    if (!reset) begin
      cycles <= cycles + 1;
      if ((vcdfile || vcdplusfile) && !vcdon) begin
        if (vcdfile) begin
          $dumpon;
        end
`ifdef VCS
        if (vcdplusfile) begin
          $vcdpluson(0);
          $vcdplusmemon(0);
        end
`endif
        vcdon <= 1;
      end
    end
  end

  always @(negedge clock) begin
    $tick(exit);
    if (exit) begin
      if (vcdfile && vcdon) begin
`ifdef VCS


        $dumpon;
`else
        $dumpoff;
`endif
      end
`ifdef VCS
      if (vcdplusfile) begin
        $vcdplusclose;
      end
`endif
      $finish;
    end
  end

endmodule
module replay;

  reg clock = 1'b0;
  reg reset = 1'b1;
  reg exit = 1'b0;
  reg [64:0] cycles = 0;

`ifdef VCS 
  always #(`CLOCK_PERIOD / 2.0) clock = ~clock;

  reg vcdon = 1'b0;
  reg [1023:0] vcdfile = 0;
  reg [1023:0] vcdplusfile = 0;
`endif


`include `VFRAG

  initial begin
`ifdef VCS
    if ($value$plusargs("vcdfile=%s", vcdfile))
    begin
      $dumpfile(vcdfile);
      $dumpvars(0, `TOP_TYPE);
      $dumpoff;
    end
    if ($value$plusargs("waveform=%s", vcdplusfile))
    begin
      $vcdplusfile(vcdplusfile);
    end
`endif
    $init_sigs(`TOP_TYPE);
  end

  always @(posedge clock) begin
    if (!reset) begin
      cycles <= cycles + 1;
      if ((vcdfile || vcdplusfile) && !vcdon) begin
        if (vcdfile) begin
          $dumpon;
        end
`ifdef VCS
        if (vcdplusfile) begin
          $vcdpluson(0);
          $vcdplusmemon(0);
        end
`endif
        vcdon <= 1;
      end
    end
  end

  always @(negedge clock) begin
    $tick(exit);
    if (exit) begin
      if (vcdfile && vcdon) begin
`ifdef VCS


        $dumpon;
`else
        $dumpoff;
`endif
      end
`ifdef VCS
      if (vcdplusfile) begin
        $vcdplusclose;
      end
`endif
      $finish;
    end
  end

endmodule