data/full_repos/permissive/502764644/z8420/Interrupt.v
1: b"%Error: data/full_repos/permissive/502764644/z8420/Interrupt.v:89: syntax error, unexpected else\n        end else if (DI == 'hCB) begin\n            ^~~~\n%Error: data/full_repos/permissive/502764644/z8420/Interrupt.v:93: syntax error, unexpected else\n        end else if (DI == 'h4D) begin\n            ^~~~\n%Error: Cannot continue\n"
module Interrupt
(

    input        RESET,

    input  [7:0] DI,
    input        IORQ_n,
    input        RD_n,
    input        M1_n,
    input        IEI,
    output       IEO,
    output       INTO_n,

    output       VECTEN,
    input        INTI,
    input        INTEN
);

wire IREQ;
wire IRES;
wire INTR;
wire IAUTH;
wire AUTHRES;
wire IED1;
wire IED2;
wire ICB;
wire I4D;
wire FETCH;
wire INTA;
wire IENB;
wire iINT;
wire iIEO;


assign INTO_n = iINT;
assign IEO = iIEO;


assign iINT    = (IEI && IREQ && ~IAUTH) ? 0 : 1;
assign iIED    = (((!IED1) && IREQ) || IAUTH || (!IEI));
assign INTA    = ((!M1_n) && (!IORQ_n) && IEI);
assign AUTHRES = RESET || (IEI && IED2 && I4D);
assign FETCH   = M1_n || RD_n;
assign IRES    = RESET || INTA;
assign INTR    = M1_n && (INTI && INTENT);
assign VECTEN  = (INTA && IEI && IAUTH) ? 1 : 0;


always @(IRES or INTR) begin
    if (IRES) begin
        IREQ <= 0;
    end else if (INTR) begin
        IREQ <= 1;
    end
end


always @(AUTHRES or INTA) begin
    if (AUTHRES) begin
        IAUTH <= 0;
    end else if (INTA) begin
        IAUTH <= IREQ;
    end
end


always @(RESET or FETCH) begin
    if (RESET) begin
        IED1 <= 0;
        IED2 <= 0;
        ICB  <= 0;
        I4D  <= 0;
    end else if (FETCH) begin
        IED2 <= IED1;
        if ((DI == 'hED) && ~ICB) begin
            IED1 <= 1;
        end else begin
            IED1 <= 0;
        end else if (DI == 'hCB) begin
            ICB <= 1;
        end else begin
            ICB <= 0;
        end else if (DI == 'h4D) begin
            I4D <= IEI;
        else
            I4D <= 0;
        end
    end
end

endmodule
module Interrupt
(

    input        RESET,

    input  [7:0] DI,
    input        IORQ_n,
    input        RD_n,
    input        M1_n,
    input        IEI,
    output       IEO,
    output       INTO_n,

    output       VECTEN,
    input        INTI,
    input        INTEN
);


wire IREQ;
wire IRES;
wire INTR;
wire IAUTH;
wire AUTHRES;
wire IED1;
wire IED2;
wire ICB;
wire I4D;
wire FETCH;
wire INTA;
wire IENB;
wire iINT;
wire iIEO;


assign INTO_n = iINT;
assign IEO = iIEO;


assign iINT    = (IEI && IREQ && ~IAUTH) ? 0 : 1;
assign iIED    = (((!IED1) && IREQ) || IAUTH || (!IEI));
assign INTA    = ((!M1_n) && (!IORQ_n) && IEI);
assign AUTHRES = RESET || (IEI && IED2 && I4D);
assign FETCH   = M1_n || RD_n;
assign IRES    = RESET || INTA;
assign INTR    = M1_n && (INTI && INTENT);
assign VECTEN  = (INTA && IEI && IAUTH) ? 1 : 0;


always @(IRES or INTR) begin
    if (IRES) begin
        IREQ <= 0;
    end else if (INTR) begin
        IREQ <= 1;
    end
end


always @(AUTHRES or INTA) begin
    if (AUTHRES) begin
        IAUTH <= 0;
    end else if (INTA) begin
        IAUTH <= IREQ;
    end
end


always @(RESET or FETCH) begin
    if (RESET) begin
        IED1 <= 0;
        IED2 <= 0;
        ICB  <= 0;
        I4D  <= 0;
    end else if (FETCH) begin
        IED2 <= IED1;
        if ((DI == 'hED) && ~ICB) begin
            IED1 <= 1;
        end else begin
            IED1 <= 0;
        end else if (DI == 'hCB) begin
            ICB <= 1;
        end else begin
            ICB <= 0;
        end else if (DI == 'h4D) begin
            I4D <= IEI;
        else
            I4D <= 0;
        end
    end
end

endmodule