data/full_repos/permissive/445455582/single/tb/registerFile_tb.v
1: b'%Error: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:23: Cannot find include file: RiSC16_registerFile.v\n`include "RiSC16_registerFile.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:57: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("registerFile_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:58: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, registerFile_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #10     rst     <= 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10     rst     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10     addrT   <= 3\'b001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10     wen     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10     addr1   <= 3\'b001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10     rst     <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10     rst     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10     addrT   <= 3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #10     wen     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #10     $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/registerFile_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    always #7 clk <= ~clk;\n           ^\n%Error: Exiting due to 4 error(s), 11 warning(s)\n'
module registerFile_tb;

    reg [2:0] addr1 = 3'b000;
    reg [2:0] addr2 = 3'b000;
    reg [2:0] addrT = 3'b000;
    reg [15:0] trgt = 16'h0000;
    reg wen = 0;
    reg clk = 0;
    reg rst = 0;


    wire [15:0] src1;
    wire [15:0] src2;

    RiSC16_registerFile #(
        .WORD_LENGTH(16),
        .REG_ADDR_LEN(3),
        .REG_NUM(8)
    ) regFile (
        .addr1(addr1), 
        .src1(src1), 
        .addr2(addr2), 
        .src2(src2), 
        .addrT(addrT), 
        .trgt(trgt),
        .wen(wen), 
        .clk(clk), 
        .rst(rst)
    );

    initial begin
        
        $dumpfile("registerFile_tb.vcd");
        $dumpvars(0, registerFile_tb);

        #10     rst     <= 1;

        #10     rst     <= 0;

        #10     addrT   <= 3'b001;
                trgt    <= 16'h1234;
                wen     <= 1;

        #10     wen     <= 0;
        
        #10     addr1   <= 3'b001;
        
        #10     rst     <= 1;

        #10     rst     <= 0;

        #10     addrT   <= 3'b000;
                trgt    <= 16'h2356;
                wen     <= 1;
                addr1   <= 3'b000;
            
        #10     wen     <= 0;

        #10     $finish;
    end

    always #7 clk <= ~clk;

endmodule
module registerFile_tb;


    reg [2:0] addr1 = 3'b000;
    reg [2:0] addr2 = 3'b000;
    reg [2:0] addrT = 3'b000;
    reg [15:0] trgt = 16'h0000;
    reg wen = 0;
    reg clk = 0;
    reg rst = 0;


    wire [15:0] src1;
    wire [15:0] src2;

    RiSC16_registerFile #(
        .WORD_LENGTH(16),
        .REG_ADDR_LEN(3),
        .REG_NUM(8)
    ) regFile (
        .addr1(addr1), 
        .src1(src1), 
        .addr2(addr2), 
        .src2(src2), 
        .addrT(addrT), 
        .trgt(trgt),
        .wen(wen), 
        .clk(clk), 
        .rst(rst)
    );

    initial begin
        
        $dumpfile("registerFile_tb.vcd");
        $dumpvars(0, registerFile_tb);

        #10     rst     <= 1;

        #10     rst     <= 0;

        #10     addrT   <= 3'b001;
                trgt    <= 16'h1234;
                wen     <= 1;

        #10     wen     <= 0;
        
        #10     addr1   <= 3'b001;
        
        #10     rst     <= 1;

        #10     rst     <= 0;

        #10     addrT   <= 3'b000;
                trgt    <= 16'h2356;
                wen     <= 1;
                addr1   <= 3'b000;
            
        #10     wen     <= 0;

        #10     $finish;
    end

    always #7 clk <= ~clk;

endmodule