data/full_repos/permissive/490649362/single-cycle/src/RegFile.v
data/verilator_xmls/b11dc857-66a0-42a9-b6cf-4549e960db72.xml
module RegFile(clk, RegWrite, read_reg_1, read_reg_2, write_reg, write_data, read_data_1, read_data_2);

    input          clk, RegWrite;
    input  [4:0]   read_reg_1, read_reg_2;
    input  [4:0]   write_reg;
    input  [31:0]  write_data;
    output [31:0]  read_data_1, read_data_2;

    reg    [31:0]  reg_file [0:31];


    initial begin
        for (integer i = 0; i < 32; i = i+1) begin
            reg_file[i] = 32'b0;
        end
    end


    always @(posedge clk) begin
        if(RegWrite == 1) begin
            reg_file[write_reg] = write_data;
        end
    end


    assign read_data_1 = reg_file[read_reg_1];
    assign read_data_2 = reg_file[read_reg_2];


endmodule
module RegFile(clk, RegWrite, read_reg_1, read_reg_2, write_reg, write_data, read_data_1, read_data_2);


    input          clk, RegWrite;
    input  [4:0]   read_reg_1, read_reg_2;
    input  [4:0]   write_reg;
    input  [31:0]  write_data;
    output [31:0]  read_data_1, read_data_2;

    reg    [31:0]  reg_file [0:31];


    initial begin
        for (integer i = 0; i < 32; i = i+1) begin
            reg_file[i] = 32'b0;
        end
    end


    always @(posedge clk) begin
        if(RegWrite == 1) begin
            reg_file[write_reg] = write_data;
        end
    end


    assign read_data_1 = reg_file[read_reg_1];
    assign read_data_2 = reg_file[read_reg_2];


endmodule