data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 stim_a = stim_a + 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #2 stim_b = stim_b + 1;\n    ^\n%Error: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v:38: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v:39: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();

  wire [2:0] out_or_bitwise;
  wire out_or_logical;
  wire [5:0] out_not;

  reg [2:0] stim_a = 2'd0;
  reg [2:0] stim_b = 2'd0;

  localparam ITERATIONS = 32;

  always begin
    #1 stim_a = stim_a + 1;
  end

  always begin
    #2 stim_b = stim_b + 1;
  end

  top_module uut (
      .a(stim_a),
      .b(stim_b),
      .out_or_bitwise(out_or_bitwise),
      .out_or_logical(out_or_logical),
      .out_not(out_not)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  wire [2:0] out_or_bitwise;
  wire out_or_logical;
  wire [5:0] out_not;

  reg [2:0] stim_a = 2'd0;
  reg [2:0] stim_b = 2'd0;

  localparam ITERATIONS = 32;

  always begin
    #1 stim_a = stim_a + 1;
  end

  always begin
    #2 stim_b = stim_b + 1;
  end

  top_module uut (
      .a(stim_a),
      .b(stim_b),
      .out_or_bitwise(out_or_bitwise),
      .out_or_logical(out_or_logical),
      .out_not(out_not)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule