data/full_repos/permissive/496906136/verilog/rtl/fpga_tech.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/496906136/verilog/rtl/fpga_tech.v:35: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'fpga_tech_register\'\nmodule fpga_tech_register\n       ^~~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'fpga_tech_buffer\'\nmodule fpga_tech_buffer\n       ^~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'fpga_tech_clkbuffer\'\nmodule fpga_tech_clkbuffer\n       ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module sky130_fd_sc_hd__clkbuf_1
  (input  A,
   output X);
endmodule
module sky130_fd_sc_hd__clkbuf_1
  (input  A,
   output X);

endmodule