data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v
1: b'%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:5: Cannot find include file: instruction_defs.vh\n`include "instruction_defs.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh.v\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh.sv\n             instruction_defs.vh\n             instruction_defs.vh.v\n             instruction_defs.vh.sv\n             obj_dir/instruction_defs.vh\n             obj_dir/instruction_defs.vh.v\n             obj_dir/instruction_defs.vh.sv\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:63: Define or directive not defined: \'`HLT\'\n   wire core_disabled = instr == `HLT | rst;    \n                                 ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:114: Define or directive not defined: \'`MUL\'\n    wire multiplier_enabled = (instr == `MUL),\n                                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:114: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire multiplier_enabled = (instr == `MUL),\n                                            ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:115: Define or directive not defined: \'`DIV\'\n        divider_enabled = (instr == `DIV);\n                                    ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:119: Define or directive not defined: \'`SHL\'\n    wire alu_instruction = instr <= `SHL,\n                                    ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:119: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    wire alu_instruction = instr <= `SHL,\n                                        ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:142: Define or directive not defined: \'`POP\'\n                else if (instr == `POP || instr == `LDA)\n                                  ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:142: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                else if (instr == `POP || instr == `LDA)\n                                       ^~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:142: Define or directive not defined: \'`LDA\'\n                else if (instr == `POP || instr == `LDA)\n                                                   ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:145: Define or directive not defined: \'`RET\'\n                if (instr == `RET)\n                             ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:145: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                if (instr == `RET)\n                                 ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:188: Define or directive not defined: \'`PUSH\'\n                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);\n                                                   ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:188: Define or directive not defined: \'`CALL\'\n                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);\n                                                                    ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:188: Define or directive not defined: \'`STA\'\n                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);\n                                                                                     ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:188: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);\n                                                                                         ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:193: Define or directive not defined: \'`PUSH\'\n                        `PUSH, `CALL: sp <= sp - 1;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:193: syntax error, unexpected \',\', expecting endcase\n                        `PUSH, `CALL: sp <= sp - 1;\n                             ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:193: Define or directive not defined: \'`CALL\'\n                        `PUSH, `CALL: sp <= sp - 1;\n                               ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:194: Define or directive not defined: \'`POP\'\n                        `POP, `RET: sp = sp + 1;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:194: Define or directive not defined: \'`RET\'\n                        `POP, `RET: sp = sp + 1;\n                              ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:195: Define or directive not defined: \'`STSP\'\n                        `STSP: sp <= selected_v1_or_imm16;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:200: Define or directive not defined: \'`LDA\'\n                        `LDA:  address <= selected_v2;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:201: Define or directive not defined: \'`STA\'\n                        `STA:  address <= selected_v1;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:202: Define or directive not defined: \'`POP\'\n                        `POP, `CALL, `RET, `PUSH:  address <= sp;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:202: Define or directive not defined: \'`CALL\'\n                        `POP, `CALL, `RET, `PUSH:  address <= sp;\n                              ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:202: Define or directive not defined: \'`RET\'\n                        `POP, `CALL, `RET, `PUSH:  address <= sp;\n                                     ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:202: Define or directive not defined: \'`PUSH\'\n                        `POP, `CALL, `RET, `PUSH:  address <= sp;\n                                           ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:207: Define or directive not defined: \'`PUSH\'\n                        `PUSH: memory_obus <= selected_v1_or_imm16;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:208: Define or directive not defined: \'`STA\'\n                        `STA:  memory_obus <= selected_v2;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:209: Define or directive not defined: \'`CALL\'\n                        `CALL: memory_obus <= ip;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:214: Define or directive not defined: \'`JE\'\n                        `JE:  if (flags[0]) ip <= selected_v1_or_imm16;\n                        ^~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:215: Define or directive not defined: \'`JG\'\n                        `JG:  if (flags[1]) ip <= selected_v1_or_imm16;\n                        ^~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:216: Define or directive not defined: \'`JL\'\n                        `JL:  if (flags[2]) ip <= selected_v1_or_imm16;\n                        ^~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:217: Define or directive not defined: \'`JNE\'\n                        `JNE: if (~flags[0]) ip <= selected_v1_or_imm16;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:218: Define or directive not defined: \'`JGE\'\n                        `JGE: if (flags[0] | flags[1]) ip <= selected_v1_or_imm16;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:219: Define or directive not defined: \'`JLE\'\n                        `JLE: if (flags[0] | flags[2]) ip <= selected_v1_or_imm16;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:220: Define or directive not defined: \'`CALL\'\n                        `CALL, `JMP: ip <= selected_v1_or_imm16;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:220: Define or directive not defined: \'`JMP\'\n                        `CALL, `JMP: ip <= selected_v1_or_imm16;\n                               ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:225: Define or directive not defined: \'`MOV\'\n                        `MOV:  r1_result <= selected_v2;\n                        ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:226: Define or directive not defined: \'`SWAP\'\n                        `SWAP: r1_result <= r2_out;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:227: Define or directive not defined: \'`LDSW\'\n                        `LDSW: r1_result <= basys3_switches;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:228: Define or directive not defined: \'`LDSP\'\n                        `LDSP: r1_result <= sp;\n                        ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:234: Define or directive not defined: \'`SWAP\'\n                    if (instr == `SWAP)\n                                 ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:238: Define or directive not defined: \'`CMP\'\n                    if (instr == `CMP) begin\n                                 ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:238: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    if (instr == `CMP) begin\n                                     ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:246: Define or directive not defined: \'`CLKDIV\'\n                    if (instr == `CLKDIV)  \n                                 ^~~~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:246: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    if (instr == `CLKDIV)  \n                                        ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:250: Define or directive not defined: \'`DLED\'\n                    if (instr == `DLED) \n                                 ^~~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/core.v:250: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    if (instr == `DLED) \n                                      ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module core#(parameter memory_size=1023)(
    input clk,

    inout[15:0] memory_io,
    output reg[15:0] address = 0,
    output reg memory_write_flag = 0,

    input[15:0] basys3_switches,
    output reg[15:0] basys3_leds = 0,
    output reg[15:0] basys3_disp = 0
    );
    

    reg rst = 1;
    integer i = 0;
    

    always@(posedge clk) begin
        if (rst) begin
            if (i == 7) begin
                rst <= 0;
            end else i <= i + 1;
        end
    end
    
    
    
    reg[15:0] memory_obus_reg = 0, 
              ip = 0,
              sp = memory_size,
              immediate;
    
    
    reg[7:0] flags = 0,
             state = `STATE_QUERY,
             opcode = 0,
             operand;
    
    
    wire[15:0] incremented_ip = (state == `STATE_FETCH ? address : ip) + 1;
    
    wire[7:0] instr = opcode;

    wire executing = state == `STATE_EXECUTE,
         imm16_source = operand[7];

   wire core_disabled = instr == `HLT | rst;    



    wire[15:0] memory_ibus;
    reg[15:0] memory_obus = 0;
    assign memory_io = memory_write_flag ? memory_obus : 16'hz;
    assign memory_ibus = memory_io;
        
        
        

    wire core_clock, divided_clock;
    reg[31:0] clk_div_factor = 0;
    clock_divider clk_div1(clk, clk_div_factor, divided_clock);
    

    assign core_clock = core_disabled ? 0 : clk_div_factor != 0 ? divided_clock : clk;
    
    

    wire[2:0] r1_sel = operand[2:0], 
              r2_sel = operand[5:3];
              
    wire[15:0] r1_out, r2_out;
    reg[15:0] r1_result = 0, r2_result = 0;
    
    wire regs_update = state == `STATE_FETCH;


    registers regs1(rst ? clk : core_clock, r1_sel, r2_sel, r1_out, r2_out,
                    r1_result, r2_result, regs_update, imm16_source);
    
    wire[15:0] selected_v1 = r1_out,
               selected_v2 = imm16_source ? immediate : r2_out;      
               
    wire[15:0] selected_v1_or_imm16 = imm16_source ? immediate : selected_v1;
    
    

    wire multiplier_enabled = (instr == `MUL),
        divider_enabled = (instr == `DIV);

    wire[15:0] alu_out1, alu_out2;
    
    wire alu_instruction = instr <= `SHL,
         alu_enabled = executing & alu_instruction;

    wire alu_done;
    
    alu alu1(core_clock, alu_enabled, multiplier_enabled, divider_enabled,
            instr, selected_v1, selected_v2, alu_out1, alu_out2, alu_done);
    

    wire stall = ~alu_done;
    
    
    always@(posedge core_clock)  begin
    
        case (state)
            
            `STATE_QUERY: begin
                

                if (alu_instruction) 
                    r1_result <= alu_out1;
                    

                else if (instr == `POP || instr == `LDA)
                    r1_result <= memory_ibus;
                    
                if (instr == `RET)
                    address <= memory_ibus;
                else  address <= ip;
                

                memory_write_flag <= 0;
                state <= `STATE_FETCH;
            end        
            
            `STATE_FETCH: begin
            
                opcode <= memory_ibus[7:0];
                operand = memory_ibus[15:8];
                
                state <= (operand[7]) ? `STATE_FETCH_IMMEDIATE : `STATE_EXECUTE;
                
                ip <= incremented_ip;
                address <= incremented_ip;
            end 
            
            `STATE_FETCH_IMMEDIATE: begin
                state <= `STATE_EXECUTE;
                immediate <= memory_ibus;
                ip <= incremented_ip;
            end
            
            `STATE_EXECUTE: begin
            
                if (~stall)
                    state <= `STATE_QUERY;
                
                
                if (alu_enabled) begin
                    
                    if (alu_done) begin
                        if (multiplier_enabled | divider_enabled) begin
                            operand <= 8'b00001000;
                            r2_result <= alu_out2;
                        end else r2_result <= r2_out;
                    end

                end else begin
                
                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);

                
                    case (instr)
                        
                        `PUSH, `CALL: sp <= sp - 1;
                        `POP, `RET: sp = sp + 1;
                        `STSP: sp <= selected_v1_or_imm16;
                    endcase
                    
                    
                    case (instr)
                        `LDA:  address <= selected_v2;
                        `STA:  address <= selected_v1;
                        `POP, `CALL, `RET, `PUSH:  address <= sp;
                    endcase
                    

                    case (instr)
                        `PUSH: memory_obus <= selected_v1_or_imm16;
                        `STA:  memory_obus <= selected_v2;
                        `CALL: memory_obus <= ip;
                    endcase
                    
                
                    case (instr) 
                        `JE:  if (flags[0]) ip <= selected_v1_or_imm16;
                        `JG:  if (flags[1]) ip <= selected_v1_or_imm16;
                        `JL:  if (flags[2]) ip <= selected_v1_or_imm16;
                        `JNE: if (~flags[0]) ip <= selected_v1_or_imm16;
                        `JGE: if (flags[0] | flags[1]) ip <= selected_v1_or_imm16;
                        `JLE: if (flags[0] | flags[2]) ip <= selected_v1_or_imm16;
                        `CALL, `JMP: ip <= selected_v1_or_imm16;
                    endcase

                    
                    case (instr)
                        `MOV:  r1_result <= selected_v2;
                        `SWAP: r1_result <= r2_out;
                        `LDSW: r1_result <= basys3_switches;
                        `LDSP: r1_result <= sp;
                        default: r1_result <= r1_out;
                    endcase
                            
                    
                                        
                    if (instr == `SWAP)
                        r2_result <= r1_out;
                    else r2_result <= r2_out;
                    
                    if (instr == `CMP) begin
                        flags[0] <= selected_v1 == selected_v2;
                        flags[1] <= selected_v1 > selected_v2;
                        flags[2] <= selected_v1 < selected_v2;
                    end 
                    

                    
                    if (instr == `CLKDIV)
                        clk_div_factor <= {selected_v2, selected_v1} >> 1;           
                    
                    
                    if (instr == `DLED) 
                        basys3_leds <= selected_v1_or_imm16;
                    
                    if (instr == `D7SD) 
                        basys3_disp <= selected_v1_or_imm16;
                end
            end
            
        endcase
    end
    
    
endmodule
module core#(parameter memory_size=1023)(
    input clk,

    inout[15:0] memory_io,
    output reg[15:0] address = 0,
    output reg memory_write_flag = 0,

    input[15:0] basys3_switches,
    output reg[15:0] basys3_leds = 0,
    output reg[15:0] basys3_disp = 0
    );

    

    reg rst = 1;
    integer i = 0;
    

    always@(posedge clk) begin
        if (rst) begin
            if (i == 7) begin
                rst <= 0;
            end else i <= i + 1;
        end
    end
    
    
    
    reg[15:0] memory_obus_reg = 0, 
              ip = 0,
              sp = memory_size,
              immediate;
    
    
    reg[7:0] flags = 0,
             state = `STATE_QUERY,
             opcode = 0,
             operand;
    
    
    wire[15:0] incremented_ip = (state == `STATE_FETCH ? address : ip) + 1;
    
    wire[7:0] instr = opcode;

    wire executing = state == `STATE_EXECUTE,
         imm16_source = operand[7];

   wire core_disabled = instr == `HLT | rst;    



    wire[15:0] memory_ibus;
    reg[15:0] memory_obus = 0;
    assign memory_io = memory_write_flag ? memory_obus : 16'hz;
    assign memory_ibus = memory_io;
        
        
        

    wire core_clock, divided_clock;
    reg[31:0] clk_div_factor = 0;
    clock_divider clk_div1(clk, clk_div_factor, divided_clock);
    

    assign core_clock = core_disabled ? 0 : clk_div_factor != 0 ? divided_clock : clk;
    
    

    wire[2:0] r1_sel = operand[2:0], 
              r2_sel = operand[5:3];
              
    wire[15:0] r1_out, r2_out;
    reg[15:0] r1_result = 0, r2_result = 0;
    
    wire regs_update = state == `STATE_FETCH;


    registers regs1(rst ? clk : core_clock, r1_sel, r2_sel, r1_out, r2_out,
                    r1_result, r2_result, regs_update, imm16_source);
    
    wire[15:0] selected_v1 = r1_out,
               selected_v2 = imm16_source ? immediate : r2_out;      
               
    wire[15:0] selected_v1_or_imm16 = imm16_source ? immediate : selected_v1;
    
    

    wire multiplier_enabled = (instr == `MUL),
        divider_enabled = (instr == `DIV);

    wire[15:0] alu_out1, alu_out2;
    
    wire alu_instruction = instr <= `SHL,
         alu_enabled = executing & alu_instruction;

    wire alu_done;
    
    alu alu1(core_clock, alu_enabled, multiplier_enabled, divider_enabled,
            instr, selected_v1, selected_v2, alu_out1, alu_out2, alu_done);
    

    wire stall = ~alu_done;
    
    
    always@(posedge core_clock)  begin
    
        case (state)
            
            `STATE_QUERY: begin
                

                if (alu_instruction) 
                    r1_result <= alu_out1;
                    

                else if (instr == `POP || instr == `LDA)
                    r1_result <= memory_ibus;
                    
                if (instr == `RET)
                    address <= memory_ibus;
                else  address <= ip;
                

                memory_write_flag <= 0;
                state <= `STATE_FETCH;
            end        
            
            `STATE_FETCH: begin
            
                opcode <= memory_ibus[7:0];
                operand = memory_ibus[15:8];
                
                state <= (operand[7]) ? `STATE_FETCH_IMMEDIATE : `STATE_EXECUTE;
                
                ip <= incremented_ip;
                address <= incremented_ip;
            end 
            
            `STATE_FETCH_IMMEDIATE: begin
                state <= `STATE_EXECUTE;
                immediate <= memory_ibus;
                ip <= incremented_ip;
            end
            
            `STATE_EXECUTE: begin
            
                if (~stall)
                    state <= `STATE_QUERY;
                
                
                if (alu_enabled) begin
                    
                    if (alu_done) begin
                        if (multiplier_enabled | divider_enabled) begin
                            operand <= 8'b00001000;
                            r2_result <= alu_out2;
                        end else r2_result <= r2_out;
                    end

                end else begin
                
                    memory_write_flag <= (instr == `PUSH | instr == `CALL | instr == `STA);

                
                    case (instr)
                        
                        `PUSH, `CALL: sp <= sp - 1;
                        `POP, `RET: sp = sp + 1;
                        `STSP: sp <= selected_v1_or_imm16;
                    endcase
                    
                    
                    case (instr)
                        `LDA:  address <= selected_v2;
                        `STA:  address <= selected_v1;
                        `POP, `CALL, `RET, `PUSH:  address <= sp;
                    endcase
                    

                    case (instr)
                        `PUSH: memory_obus <= selected_v1_or_imm16;
                        `STA:  memory_obus <= selected_v2;
                        `CALL: memory_obus <= ip;
                    endcase
                    
                
                    case (instr) 
                        `JE:  if (flags[0]) ip <= selected_v1_or_imm16;
                        `JG:  if (flags[1]) ip <= selected_v1_or_imm16;
                        `JL:  if (flags[2]) ip <= selected_v1_or_imm16;
                        `JNE: if (~flags[0]) ip <= selected_v1_or_imm16;
                        `JGE: if (flags[0] | flags[1]) ip <= selected_v1_or_imm16;
                        `JLE: if (flags[0] | flags[2]) ip <= selected_v1_or_imm16;
                        `CALL, `JMP: ip <= selected_v1_or_imm16;
                    endcase

                    
                    case (instr)
                        `MOV:  r1_result <= selected_v2;
                        `SWAP: r1_result <= r2_out;
                        `LDSW: r1_result <= basys3_switches;
                        `LDSP: r1_result <= sp;
                        default: r1_result <= r1_out;
                    endcase
                            
                    
                                        
                    if (instr == `SWAP)
                        r2_result <= r1_out;
                    else r2_result <= r2_out;
                    
                    if (instr == `CMP) begin
                        flags[0] <= selected_v1 == selected_v2;
                        flags[1] <= selected_v1 > selected_v2;
                        flags[2] <= selected_v1 < selected_v2;
                    end 
                    

                    
                    if (instr == `CLKDIV)
                        clk_div_factor <= {selected_v2, selected_v1} >> 1;           
                    
                    
                    if (instr == `DLED) 
                        basys3_leds <= selected_v1_or_imm16;
                    
                    if (instr == `D7SD) 
                        basys3_disp <= selected_v1_or_imm16;
                end
            end
            
        endcase
    end
    
    
endmodule