data/full_repos/permissive/472385934/control_unit.v
data/verilator_xmls/8b0e7ebe-7d2e-4a8d-beaa-ba31b453d6b4.xml
module main_decoder(
input [5:0]op,
input rst_n,
output [3:0]aluop,
output regwrite,
output memtoreg,
output memwrite,
output [1:0]branch,
output alusrc,
output regdst,
output jump);

reg [11:0]control;

assign {aluop,regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump}=control;

always@(*) begin
    if(!rst_n)
        control = 12'b0;
    else begin 
        case(op)
            6'b000000: control = 12'b1111_110_00000;
            6'b001000: control = 12'b1000_101_00000;
            6'b001001: control = 12'b0000_101_00000;
            6'b001100: control = 12'b0011_101_00000;
            6'b001101: control = 12'b0010_101_00000;
            6'b001110: control = 12'b0100_101_00000;
            6'b001011: control = 12'b0110_101_00000;
            6'b100011: control = 12'b0000_101_00010;
            6'b101001: control = 12'b0000_001_00100;
            6'b001111: control = 12'b0111_101_00000;
            6'b000101: control = 12'b0001_000_11000;
            6'b000100: control = 12'b0001_000_10000;
            6'b000010: control = 12'b0000_000_00001;
            default:control = 12'b0;
        endcase
    end
end
endmodule
module main_decoder(
input [5:0]op,
input rst_n,
output [3:0]aluop,
output regwrite,
output memtoreg,
output memwrite,
output [1:0]branch,
output alusrc,
output regdst,
output jump);


reg [11:0]control;

assign {aluop,regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump}=control;

always@(*) begin
    if(!rst_n)
        control = 12'b0;
    else begin 
        case(op)
            6'b000000: control = 12'b1111_110_00000;
            6'b001000: control = 12'b1000_101_00000;
            6'b001001: control = 12'b0000_101_00000;
            6'b001100: control = 12'b0011_101_00000;
            6'b001101: control = 12'b0010_101_00000;
            6'b001110: control = 12'b0100_101_00000;
            6'b001011: control = 12'b0110_101_00000;
            6'b100011: control = 12'b0000_101_00010;
            6'b101001: control = 12'b0000_001_00100;
            6'b001111: control = 12'b0111_101_00000;
            6'b000101: control = 12'b0001_000_11000;
            6'b000100: control = 12'b0001_000_10000;
            6'b000010: control = 12'b0000_000_00001;
            default:control = 12'b0;
        endcase
    end
end
endmodule