data/full_repos/permissive/503509790/verilog/rtl/Priority_Arbiter.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/503509790/verilog/rtl/Priority_Arbiter.v:11: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input   wire    [WORD_WIDTH-1:0]    requests,\n                    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/503509790/verilog/rtl/Priority_Arbiter.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output  reg     [WORD_WIDTH-1:0]    grant\n                    ^\n%Error: Exiting due to 2 warning(s)\n'
module Priority_Arbiter
#(
    parameter       WORD_WIDTH          = 0
)
(
    input   wire    [WORD_WIDTH-1:0]    requests,
    output  reg     [WORD_WIDTH-1:0]    grant
);

    initial begin
        grant = 0;
    end

    always @(*) begin
        grant = requests & -requests;
    end

endmodule
module Priority_Arbiter
#(
    parameter       WORD_WIDTH          = 0
)
(
    input   wire    [WORD_WIDTH-1:0]    requests,
    output  reg     [WORD_WIDTH-1:0]    grant
);


    initial begin
        grant = 0;
    end

    always @(*) begin
        grant = requests & -requests;
    end

endmodule