data/full_repos/permissive/470590146/core/id_stage.v
1: b'%Error: data/full_repos/permissive/470590146/core/id_stage.v:79: Cannot find file containing module: \'decoder_2_8\'\ndecoder_2_8   U_dec_funct3 (.in(funct3), .out(funct3_d));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/decoder_2_8\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/decoder_2_8.v\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/decoder_2_8.sv\n             decoder_2_8\n             decoder_2_8.v\n             decoder_2_8.sv\n             obj_dir/decoder_2_8\n             obj_dir/decoder_2_8.v\n             obj_dir/decoder_2_8.sv\n%Error: data/full_repos/permissive/470590146/core/id_stage.v:80: Cannot find file containing module: \'decoder_7_128\'\ndecoder_7_128 U_dec_funct7 (.in(funct7), .out(funct7_d));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470590146/core/id_stage.v:81: Cannot find file containing module: \'decoder_7_128\'\ndecoder_7_128 U_dec_opcode (.in(opcode), .out(op_d))    ;\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/470590146/core/id_stage.v:203: Operator ASSIGNW expects 147 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 151 bits.\n                                                                        : ... In instance id_stage\nassign ds2es_bus_reg = {\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470590146/core/id_stage.v:228: Operator ASSIGNDLY expects 151 bits on the Assign RHS, but Assign RHS\'s VARREF \'ds2es_bus_reg\' generates 147 bits.\n                                                                        : ... In instance id_stage\n        ds2es_bus <= ds2es_bus_reg;\n                  ^~\n%Error: data/full_repos/permissive/470590146/core/id_stage.v:233: Cannot find file containing module: \'regfile\'\nregfile inst_regfile\n^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module id_stage (


	 input  clk
	,input  rst_n


    ,input  fs_valid
    ,input  es_ready
    ,output ds_valid
    ,output ds_ready


	,input  [31:0] fs_inst
	,input  [31:0] fs_pc


	,input  [ 4:0] regfile_waddr
	,input  	   regfile_wen
	,input  [31:0] regfile_wdata

    ,output reg [150:0] ds2es_bus
);

wire [31:0] ds_pc         ;
wire [31:0] ds_src1       ;
wire [31:0] ds_src2       ;
wire [31:0] ds_imm        ;
wire [ 4:0] ds_rd         ;
wire [11:0] ds_alu_control;







wire [ 5:0] ds_ctrl       ;

assign ds_pc = fs_pc;

wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] rd;
wire [2:0] funct3;
wire [6:0] funct7;
wire [6:0] opcode;

assign rs2    = fs_inst[24:20];
assign rs1    = fs_inst[19:15];
assign rd     = fs_inst[11:7 ];
assign funct3 = fs_inst[14:12];
assign funct7 = fs_inst[31:25];
assign opcode = fs_inst[ 6:0 ];


assign ds_rd  = rd;


wire [  7:0] funct3_d;
wire [127:0] funct7_d;
wire [127:0] op_d;



decoder_2_8   U_dec_funct3 (.in(funct3), .out(funct3_d));
decoder_7_128 U_dec_funct7 (.in(funct7), .out(funct7_d));
decoder_7_128 U_dec_opcode (.in(opcode), .out(op_d))    ;

wire [11:0] imm_I;
wire [11:0] imm_S;
wire [12:0] imm_B;
wire [19:0] imm_U;
wire [19:0] imm_J;

wire R_type;
wire I_type;
wire S_type;
wire B_type;
wire U_type;
wire J_type;


assign imm_I  = fs_inst[31:20];
assign imm_S  = {fs_inst[31:25], fs_inst[11:7]};
assign imm_B  = {fs_inst[31], fs_inst[7], fs_inst[30:25], fs_inst[11:8], 1'b0};
assign imm_U  = fs_inst[31:12];
assign imm_J  = {fs_inst[31], fs_inst[19:12], fs_inst[20], fs_inst[30:21]};

assign R_type = op_d[7'h33]                                       ;

assign I_type = op_d[7'h03]   | op_d[7'h0F] | op_d[7'h13]
				| (op_d[7'h23] & funct3_d[3'b011]) | op_d[7'h67] | op_d[7'h73];
assign S_type = op_d[7'h23] & ~funct3_d[3'b011]                   ;
assign B_type = op_d[7'h63]                                       ;
assign U_type = op_d[7'h37] | op_d[7'h17]                         ;
assign J_type = op_d[7'h6F]                                       ;



assign ds_imm =  ({32{I_type}} & {{20{imm_I[11]}}, imm_I})
			| ({32{S_type}} & {{20{imm_S[11]}}, imm_S});





wire op_add ;
wire op_sub ;
wire op_slt ;
wire op_sltu;
wire op_and ;
wire op_nor ;
wire op_or  ;
wire op_xor ;
wire op_sll ;
wire op_srl ;
wire op_sra ;
wire op_lui ;

wire inst_lw ;
wire inst_sw ;
wire inst_beq;
wire inst_add;
wire inst_sub;
wire inst_and;
wire inst_or ;

assign inst_lw = funct3_d[3'b010] & op_d[7'h03]                  ;
assign inst_sw = funct3_d[3'b010] & op_d[7'h23]                  ;
assign inst_beq= funct3_d[3'b000] & op_d[7'h63]                  ;
assign inst_add= funct3_d[3'b000] & op_d[7'h33] & funct7_d[7'h00];
assign inst_sub= funct3_d[3'b000] & op_d[7'h33] & funct7_d[7'h20];
assign inst_and= funct3_d[3'b111] & op_d[7'h33] & funct7_d[7'h00];
assign inst_or = funct3_d[3'b110] & op_d[7'h33] & funct7_d[7'h00];

assign op_add  = inst_lw  | inst_sw | inst_add;
assign op_sub  = inst_sub | inst_beq          ;
assign op_slt  = 0                            ;
assign op_sltu = 0                            ;
assign op_and  = inst_and                     ;
assign op_nor  = 0                            ;
assign op_or   = inst_or                      ;
assign op_xor  = 0                            ;
assign op_sll  = 0                            ;
assign op_srl  = 0                            ;
assign op_sra  = 0                            ;
assign op_lui  = 0                            ;


assign  ds_alu_control[ 0] = op_add ;
assign  ds_alu_control[ 1] = op_sub ;
assign  ds_alu_control[ 2] = op_slt ;
assign  ds_alu_control[ 3] = op_sltu;
assign  ds_alu_control[ 4] = op_and ;
assign  ds_alu_control[ 5] = op_nor ;
assign  ds_alu_control[ 6] = op_or  ;
assign  ds_alu_control[ 7] = op_xor ;
assign  ds_alu_control[ 8] = op_sll ;
assign  ds_alu_control[ 9] = op_srl ;
assign  ds_alu_control[10] = op_sra ;
assign  ds_alu_control[11] = op_lui ;



wire branch    ;
wire mem_read  ;
wire mem_write ;
wire mem2reg   ;
wire alu_src_op;
wire reg_write ;

assign alu_src_op   = inst_lw | inst_sw;
assign branch		= inst_beq;
assign mem_read		= inst_lw;
assign mem_write	= inst_sw;
assign mem2reg		= inst_lw;
assign reg_write  	= R_type  | inst_lw;

assign ds_ctrl = {
    alu_src_op,
    branch    ,
    mem_read  ,
    mem_write ,
    mem2reg   ,
    reg_write
};

wire [146:0] ds2es_bus_reg;
assign ds2es_bus_reg = {
    ds_pc         ,
    ds_src1       ,
    ds_src2       ,
    ds_imm        ,
    ds_rd         ,
    ds_alu_control,
    ds_ctrl
};

reg    ds_ready_pre                                ;
wire   ds_ok_go = 1'b1                             ;
assign ds_ready = !fs_valid || ds_ok_go && es_ready;
assign ds_valid = ds_ready_pre && ds_ok_go         ;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        ds_ready_pre <= 0;
    end
    else if (ds_ready) begin
        ds_ready_pre <= fs_valid;
    end


    if (fs_valid && ds_ready) begin
        ds2es_bus <= ds2es_bus_reg;
    end
end


regfile inst_regfile
	(
		.clk       (clk          ),
		.rd_addr_1 (rs1          ),
		.data_o_1  (ds_src1      ),
		.rd_addr_2 (rs2          ),
		.data_o_2  (ds_src2      ),
		.wr_addr   (regfile_waddr),
		.wr_en     (regfile_wen  ),
		.wr_data   (regfile_wdata)
	);


endmodule
module id_stage (


	 input  clk
	,input  rst_n


    ,input  fs_valid
    ,input  es_ready
    ,output ds_valid
    ,output ds_ready


	,input  [31:0] fs_inst
	,input  [31:0] fs_pc


	,input  [ 4:0] regfile_waddr
	,input  	   regfile_wen
	,input  [31:0] regfile_wdata

    ,output reg [150:0] ds2es_bus
);


wire [31:0] ds_pc         ;
wire [31:0] ds_src1       ;
wire [31:0] ds_src2       ;
wire [31:0] ds_imm        ;
wire [ 4:0] ds_rd         ;
wire [11:0] ds_alu_control;







wire [ 5:0] ds_ctrl       ;

assign ds_pc = fs_pc;

wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] rd;
wire [2:0] funct3;
wire [6:0] funct7;
wire [6:0] opcode;

assign rs2    = fs_inst[24:20];
assign rs1    = fs_inst[19:15];
assign rd     = fs_inst[11:7 ];
assign funct3 = fs_inst[14:12];
assign funct7 = fs_inst[31:25];
assign opcode = fs_inst[ 6:0 ];


assign ds_rd  = rd;


wire [  7:0] funct3_d;
wire [127:0] funct7_d;
wire [127:0] op_d;



decoder_2_8   U_dec_funct3 (.in(funct3), .out(funct3_d));
decoder_7_128 U_dec_funct7 (.in(funct7), .out(funct7_d));
decoder_7_128 U_dec_opcode (.in(opcode), .out(op_d))    ;

wire [11:0] imm_I;
wire [11:0] imm_S;
wire [12:0] imm_B;
wire [19:0] imm_U;
wire [19:0] imm_J;

wire R_type;
wire I_type;
wire S_type;
wire B_type;
wire U_type;
wire J_type;


assign imm_I  = fs_inst[31:20];
assign imm_S  = {fs_inst[31:25], fs_inst[11:7]};
assign imm_B  = {fs_inst[31], fs_inst[7], fs_inst[30:25], fs_inst[11:8], 1'b0};
assign imm_U  = fs_inst[31:12];
assign imm_J  = {fs_inst[31], fs_inst[19:12], fs_inst[20], fs_inst[30:21]};

assign R_type = op_d[7'h33]                                       ;

assign I_type = op_d[7'h03]   | op_d[7'h0F] | op_d[7'h13]
				| (op_d[7'h23] & funct3_d[3'b011]) | op_d[7'h67] | op_d[7'h73];
assign S_type = op_d[7'h23] & ~funct3_d[3'b011]                   ;
assign B_type = op_d[7'h63]                                       ;
assign U_type = op_d[7'h37] | op_d[7'h17]                         ;
assign J_type = op_d[7'h6F]                                       ;



assign ds_imm =  ({32{I_type}} & {{20{imm_I[11]}}, imm_I})
			| ({32{S_type}} & {{20{imm_S[11]}}, imm_S});





wire op_add ;
wire op_sub ;
wire op_slt ;
wire op_sltu;
wire op_and ;
wire op_nor ;
wire op_or  ;
wire op_xor ;
wire op_sll ;
wire op_srl ;
wire op_sra ;
wire op_lui ;

wire inst_lw ;
wire inst_sw ;
wire inst_beq;
wire inst_add;
wire inst_sub;
wire inst_and;
wire inst_or ;

assign inst_lw = funct3_d[3'b010] & op_d[7'h03]                  ;
assign inst_sw = funct3_d[3'b010] & op_d[7'h23]                  ;
assign inst_beq= funct3_d[3'b000] & op_d[7'h63]                  ;
assign inst_add= funct3_d[3'b000] & op_d[7'h33] & funct7_d[7'h00];
assign inst_sub= funct3_d[3'b000] & op_d[7'h33] & funct7_d[7'h20];
assign inst_and= funct3_d[3'b111] & op_d[7'h33] & funct7_d[7'h00];
assign inst_or = funct3_d[3'b110] & op_d[7'h33] & funct7_d[7'h00];

assign op_add  = inst_lw  | inst_sw | inst_add;
assign op_sub  = inst_sub | inst_beq          ;
assign op_slt  = 0                            ;
assign op_sltu = 0                            ;
assign op_and  = inst_and                     ;
assign op_nor  = 0                            ;
assign op_or   = inst_or                      ;
assign op_xor  = 0                            ;
assign op_sll  = 0                            ;
assign op_srl  = 0                            ;
assign op_sra  = 0                            ;
assign op_lui  = 0                            ;


assign  ds_alu_control[ 0] = op_add ;
assign  ds_alu_control[ 1] = op_sub ;
assign  ds_alu_control[ 2] = op_slt ;
assign  ds_alu_control[ 3] = op_sltu;
assign  ds_alu_control[ 4] = op_and ;
assign  ds_alu_control[ 5] = op_nor ;
assign  ds_alu_control[ 6] = op_or  ;
assign  ds_alu_control[ 7] = op_xor ;
assign  ds_alu_control[ 8] = op_sll ;
assign  ds_alu_control[ 9] = op_srl ;
assign  ds_alu_control[10] = op_sra ;
assign  ds_alu_control[11] = op_lui ;



wire branch    ;
wire mem_read  ;
wire mem_write ;
wire mem2reg   ;
wire alu_src_op;
wire reg_write ;

assign alu_src_op   = inst_lw | inst_sw;
assign branch		= inst_beq;
assign mem_read		= inst_lw;
assign mem_write	= inst_sw;
assign mem2reg		= inst_lw;
assign reg_write  	= R_type  | inst_lw;

assign ds_ctrl = {
    alu_src_op,
    branch    ,
    mem_read  ,
    mem_write ,
    mem2reg   ,
    reg_write
};

wire [146:0] ds2es_bus_reg;
assign ds2es_bus_reg = {
    ds_pc         ,
    ds_src1       ,
    ds_src2       ,
    ds_imm        ,
    ds_rd         ,
    ds_alu_control,
    ds_ctrl
};

reg    ds_ready_pre                                ;
wire   ds_ok_go = 1'b1                             ;
assign ds_ready = !fs_valid || ds_ok_go && es_ready;
assign ds_valid = ds_ready_pre && ds_ok_go         ;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        ds_ready_pre <= 0;
    end
    else if (ds_ready) begin
        ds_ready_pre <= fs_valid;
    end


    if (fs_valid && ds_ready) begin
        ds2es_bus <= ds2es_bus_reg;
    end
end


regfile inst_regfile
	(
		.clk       (clk          ),
		.rd_addr_1 (rs1          ),
		.data_o_1  (ds_src1      ),
		.rd_addr_2 (rs2          ),
		.data_o_2  (ds_src2      ),
		.wr_addr   (regfile_waddr),
		.wr_en     (regfile_wen  ),
		.wr_data   (regfile_wdata)
	);


endmodule