data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:65: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'pos0\' generates 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 2) start_at_1 = pos0 + 4;\n                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:66: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'pos0\' generates 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 3) start_at_1 = pos0 + 3;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:67: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'pos0\' generates 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 4) start_at_1 = pos0 + 2;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:67: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 4) start_at_1 = pos0 + 2;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:66: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 3) start_at_1 = pos0 + 3;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:65: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        else if (bytes[pos0] == 2) start_at_1 = pos0 + 4;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:64: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n                                                                                : ... In instance TCP_option_decoder\n        if (bytes[pos0] == 0) start_at_1 = 4;\n                 ^\n%Error: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:112: Cannot find file containing module: \'output_shift_byte_counter\'\n  output_shift_byte_counter decoder0 (.pos(pos0), .data(data), .clk(clk), .reset(reset),\n  ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433225833/TCP,data/full_repos/permissive/433225833/output_shift_byte_counter\n             data/full_repos/permissive/433225833/TCP,data/full_repos/permissive/433225833/output_shift_byte_counter.v\n             data/full_repos/permissive/433225833/TCP,data/full_repos/permissive/433225833/output_shift_byte_counter.sv\n             output_shift_byte_counter\n             output_shift_byte_counter.v\n             output_shift_byte_counter.sv\n             obj_dir/output_shift_byte_counter\n             obj_dir/output_shift_byte_counter.v\n             obj_dir/output_shift_byte_counter.sv\n%Error: data/full_repos/permissive/433225833/TCP/TCP_option_decoder.v:120: Cannot find file containing module: \'output_shift_byte_counter\'\n  output_shift_byte_counter decoder1 (.pos(pos1), .data(data), .clk(clk), .reset(reset),\n  ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module TCP_option_decoder (data, clk, reset,
                           option_av, mss, scale_wnd,
                           sack_nbr, sack_n0, sack_n1, sack_n2, sack_n3,
                           time_stp, option_err);
  input [31:0] data;
  input clk, reset;
  
  output [8:0] option_av;
    output [15:0] mss;
    output [7:0] scale_wnd;
    output [2:0] sack_nbr;
      output [63:0] sack_n0, sack_n1, sack_n2, sack_n3;
    output [63:0] time_stp;
  output [8:0] option_err;
  
  wire [31:0] data;
  wire [7:0] bytes [0:3];
    assign bytes[0] = data[31:24];
    assign bytes[1] = data[23:16];
    assign bytes[2] = data[15:8];
    assign bytes[3] = data[7:0];
  wire clk, reset;
  
  wire [8:0] option_av;
    wire [15:0] mss;
    wire [7:0] scale_wnd;
    wire [2:0] sack_nbr;
      wire [63:0] sack_n0, sack_n1, sack_n2, sack_n3;
    wire [63:0] time_stp;
  wire [8:0] option_err;
  
  

  wire [3:0] option_str_detected;
  genvar i;
  for (i = 0; i < 4; i = i + 1)
    assign option_str_detected[i] = 
      bytes[i] == 0 || bytes[i] == 2 || bytes[i] == 3 || 
      bytes[i] == 4 || bytes[i] == 5 || bytes[i] == 8 ;
  
  reg [2:0] pos0, pos1;
  reg [5:0] start_at_0, start_at_1;
  always @(option_str_detected or start_at_0 or start_at_1) begin
    if (option_str_detected[0] && start_at_0 < 1) pos0 = 0;
    else if (option_str_detected[1] && start_at_0 < 2) pos0 = 1;
    else if (option_str_detected[2] && start_at_0 < 3) pos0 = 2;
    else if (option_str_detected[3] && start_at_0 < 4) pos0 = 3;
    else pos0 = 4;
    
    if (option_str_detected[0] && start_at_1 < 1) pos1 = 0;
    else if (option_str_detected[1] && start_at_1 < 2) pos1 = 1;
    else if (option_str_detected[2] && start_at_1 < 3) pos1 = 2;
    else if (option_str_detected[3] && start_at_1 < 4) pos1 = 3;
    else pos1 = 4;
  end

  
  

  always @(b_left_0 or b_left_1 or bytes[0] or bytes[1] or bytes[2] or bytes[3] or pos0) begin
    if (b_left_0 == 0 && b_left_1 == 0) begin
      start_at_0 = 0;
      if (pos0 < 4) begin
        if (bytes[pos0] == 0) start_at_1 = 4;
        else if (bytes[pos0] == 2) start_at_1 = pos0 + 4;
        else if (bytes[pos0] == 3) start_at_1 = pos0 + 3;
        else if (bytes[pos0] == 4) start_at_1 = pos0 + 2;
      end 
      else start_at_1 = 4;
    end else if (b_left_0 != 0 && b_left_1 == 0) begin
      start_at_0 = 4;
      if (b_left_0 == 1 && bytes[1] == 8'd4) begin
        start_at_1 = 3;
        enable_fix = 1;
      end else begin 
        start_at_1 = b_left_0;
        enable_fix = 0;
      end
    end else if (b_left_0 == 0 && b_left_1 != 0) begin
      start_at_1 = 4;
      if (b_left_1 == 1 & bytes[1] == 8'd4) begin
        start_at_0 = 3;
        enable_fix = 1;
      end else begin
        start_at_0 = b_left_1;
        enable_fix = 0;
      end 
    end
  end

  
  

  reg enable_fix, opt4_av;
  always @(posedge clk)
    if (reset) opt4_av <= 0;
    else if (enable_fix) opt4_av <= 1;

  
  

  wire [8:0] option_av_0, option_av_1;
    wire [15:0] mss_0, mss_1;
    wire [7:0] scale_wnd_0, scale_wnd_1;
    wire [2:0] sack_nbr_0, sack_nbr_1;
      wire [63:0] sack_n0_0, sack_n1_0, sack_n2_0, sack_n3_0,
                  sack_n0_1, sack_n1_1, sack_n2_1, sack_n3_1;
    wire [63:0] time_stp_0, time_stp_1;
  wire [8:0] option_err_0, option_err_1;
  wire [5:0] b_left_0, b_left_1;
  
  output_shift_byte_counter decoder0 (.pos(pos0), .data(data), .clk(clk), .reset(reset),
                                      .option_av(option_av_0), .mss(mss_0), 
                                      .scale_wnd(scale_wnd_0), .sack_nbr(sack_nbr_0),
                                      .sack_n0(sack_n0_0), .sack_n1(sack_n1_0), 
                                      .sack_n2(sack_n2_0), .sack_n3(sack_n3_0),
                                      .time_stp(time_stp_0), .option_err(option_err_0), 
                                      .b_left(b_left_0));
                                  
  output_shift_byte_counter decoder1 (.pos(pos1), .data(data), .clk(clk), .reset(reset),
                                      .option_av(option_av_1), .mss(mss_1), 
                                      .scale_wnd(scale_wnd_1), .sack_nbr(sack_nbr_1),
                                      .sack_n0(sack_n0_1), .sack_n1(sack_n1_1), 
                                      .sack_n2(sack_n2_1), .sack_n3(sack_n3_1),
                                      .time_stp(time_stp_1), .option_err(option_err_1), 
                                      .b_left(b_left_1));
                                      
  assign option_av = option_av_0 | option_av_1 | {4'd0, opt4_av, 4'd0};
  assign mss = mss_0 | mss_1;
  assign scale_wnd = scale_wnd_0 | scale_wnd_1;
  assign sack_nbr = sack_nbr_0 | sack_nbr_1;
  assign sack_n0 = sack_n0_0 | sack_n0_1;
  assign sack_n1 = sack_n1_0 | sack_n1_1;
  assign sack_n2 = sack_n2_0 | sack_n2_1;
  assign sack_n3 = sack_n3_0 | sack_n3_1;
  assign time_stp = time_stp_0 | time_stp_1;
  assign option_err = option_err_0 | option_err_1;

  
endmodule
module TCP_option_decoder (data, clk, reset,
                           option_av, mss, scale_wnd,
                           sack_nbr, sack_n0, sack_n1, sack_n2, sack_n3,
                           time_stp, option_err);

  input [31:0] data;
  input clk, reset;
  
  output [8:0] option_av;
    output [15:0] mss;
    output [7:0] scale_wnd;
    output [2:0] sack_nbr;
      output [63:0] sack_n0, sack_n1, sack_n2, sack_n3;
    output [63:0] time_stp;
  output [8:0] option_err;
  
  wire [31:0] data;
  wire [7:0] bytes [0:3];
    assign bytes[0] = data[31:24];
    assign bytes[1] = data[23:16];
    assign bytes[2] = data[15:8];
    assign bytes[3] = data[7:0];
  wire clk, reset;
  
  wire [8:0] option_av;
    wire [15:0] mss;
    wire [7:0] scale_wnd;
    wire [2:0] sack_nbr;
      wire [63:0] sack_n0, sack_n1, sack_n2, sack_n3;
    wire [63:0] time_stp;
  wire [8:0] option_err;
  
  

  wire [3:0] option_str_detected;
  genvar i;
  for (i = 0; i < 4; i = i + 1)
    assign option_str_detected[i] = 
      bytes[i] == 0 || bytes[i] == 2 || bytes[i] == 3 || 
      bytes[i] == 4 || bytes[i] == 5 || bytes[i] == 8 ;
  
  reg [2:0] pos0, pos1;
  reg [5:0] start_at_0, start_at_1;
  always @(option_str_detected or start_at_0 or start_at_1) begin
    if (option_str_detected[0] && start_at_0 < 1) pos0 = 0;
    else if (option_str_detected[1] && start_at_0 < 2) pos0 = 1;
    else if (option_str_detected[2] && start_at_0 < 3) pos0 = 2;
    else if (option_str_detected[3] && start_at_0 < 4) pos0 = 3;
    else pos0 = 4;
    
    if (option_str_detected[0] && start_at_1 < 1) pos1 = 0;
    else if (option_str_detected[1] && start_at_1 < 2) pos1 = 1;
    else if (option_str_detected[2] && start_at_1 < 3) pos1 = 2;
    else if (option_str_detected[3] && start_at_1 < 4) pos1 = 3;
    else pos1 = 4;
  end

  
  

  always @(b_left_0 or b_left_1 or bytes[0] or bytes[1] or bytes[2] or bytes[3] or pos0) begin
    if (b_left_0 == 0 && b_left_1 == 0) begin
      start_at_0 = 0;
      if (pos0 < 4) begin
        if (bytes[pos0] == 0) start_at_1 = 4;
        else if (bytes[pos0] == 2) start_at_1 = pos0 + 4;
        else if (bytes[pos0] == 3) start_at_1 = pos0 + 3;
        else if (bytes[pos0] == 4) start_at_1 = pos0 + 2;
      end 
      else start_at_1 = 4;
    end else if (b_left_0 != 0 && b_left_1 == 0) begin
      start_at_0 = 4;
      if (b_left_0 == 1 && bytes[1] == 8'd4) begin
        start_at_1 = 3;
        enable_fix = 1;
      end else begin 
        start_at_1 = b_left_0;
        enable_fix = 0;
      end
    end else if (b_left_0 == 0 && b_left_1 != 0) begin
      start_at_1 = 4;
      if (b_left_1 == 1 & bytes[1] == 8'd4) begin
        start_at_0 = 3;
        enable_fix = 1;
      end else begin
        start_at_0 = b_left_1;
        enable_fix = 0;
      end 
    end
  end

  
  

  reg enable_fix, opt4_av;
  always @(posedge clk)
    if (reset) opt4_av <= 0;
    else if (enable_fix) opt4_av <= 1;

  
  

  wire [8:0] option_av_0, option_av_1;
    wire [15:0] mss_0, mss_1;
    wire [7:0] scale_wnd_0, scale_wnd_1;
    wire [2:0] sack_nbr_0, sack_nbr_1;
      wire [63:0] sack_n0_0, sack_n1_0, sack_n2_0, sack_n3_0,
                  sack_n0_1, sack_n1_1, sack_n2_1, sack_n3_1;
    wire [63:0] time_stp_0, time_stp_1;
  wire [8:0] option_err_0, option_err_1;
  wire [5:0] b_left_0, b_left_1;
  
  output_shift_byte_counter decoder0 (.pos(pos0), .data(data), .clk(clk), .reset(reset),
                                      .option_av(option_av_0), .mss(mss_0), 
                                      .scale_wnd(scale_wnd_0), .sack_nbr(sack_nbr_0),
                                      .sack_n0(sack_n0_0), .sack_n1(sack_n1_0), 
                                      .sack_n2(sack_n2_0), .sack_n3(sack_n3_0),
                                      .time_stp(time_stp_0), .option_err(option_err_0), 
                                      .b_left(b_left_0));
                                  
  output_shift_byte_counter decoder1 (.pos(pos1), .data(data), .clk(clk), .reset(reset),
                                      .option_av(option_av_1), .mss(mss_1), 
                                      .scale_wnd(scale_wnd_1), .sack_nbr(sack_nbr_1),
                                      .sack_n0(sack_n0_1), .sack_n1(sack_n1_1), 
                                      .sack_n2(sack_n2_1), .sack_n3(sack_n3_1),
                                      .time_stp(time_stp_1), .option_err(option_err_1), 
                                      .b_left(b_left_1));
                                      
  assign option_av = option_av_0 | option_av_1 | {4'd0, opt4_av, 4'd0};
  assign mss = mss_0 | mss_1;
  assign scale_wnd = scale_wnd_0 | scale_wnd_1;
  assign sack_nbr = sack_nbr_0 | sack_nbr_1;
  assign sack_n0 = sack_n0_0 | sack_n0_1;
  assign sack_n1 = sack_n1_0 | sack_n1_1;
  assign sack_n2 = sack_n2_0 | sack_n2_1;
  assign sack_n3 = sack_n3_0 | sack_n3_1;
  assign time_stp = time_stp_0 | time_stp_1;
  assign option_err = option_err_0 | option_err_1;

  
endmodule