data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/duc.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/duc.v:76: Cannot find file containing module: 'cordic'\n cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cordic\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cordic.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cordic.sv\n             cordic\n             cordic.v\n             cordic.sv\n             obj_dir/cordic\n             obj_dir/cordic.v\n             obj_dir/cordic.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/duc.v:81: Cannot find file containing module: 'cic_interp_2stage'\n cic_interp_2stage #(.bw(bw),.N(4)) \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/duc.v:86: Cannot find file containing module: 'cic_interp_2stage'\n cic_interp_2stage #(.bw(bw),.N(4)) \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/duc.v:91: Cannot find file containing module: 'phase_acc'\n phase_acc #(.resolution(32))\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
function [2:0] log_ceil;
	input [3:0] val;
	
		log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
	endfunction
function [2:0] log_ceil;

	input [3:0] val;
	
		log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
	endfunction