data/full_repos/permissive/516679177/TOP/MUX.v
data/verilator_xmls/d10ad4ba-ccad-43bd-8c77-4efe07be84d2.xml
module MUX #(parameter WIDTH = 8)
    (input [WIDTH-1:0] in_1,
    input [WIDTH-1:0] in_2,
    input sel,
    output reg [WIDTH-1:0] out);

    always @(*) begin

        case (sel)
            1'b0: out = in_1;
            1'b1: out = in_2;
            default: out = {WIDTH{1'bx}};
        endcase

    end

endmodule
module MUX #(parameter WIDTH = 8)
    (input [WIDTH-1:0] in_1,
    input [WIDTH-1:0] in_2,
    input sel,
    output reg [WIDTH-1:0] out);


    always @(*) begin

        case (sel)
            1'b0: out = in_1;
            1'b1: out = in_2;
            default: out = {WIDTH{1'bx}};
        endcase

    end

endmodule