data/full_repos/permissive/465389471/TLC_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/465389471/TLC_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n   forever #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/465389471/TLC_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n   forever #1000 sensor2 = ~sensor2;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/465389471/TLC_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n   forever #1000 sensor1 = ~sensor1;\n           ^\n%Error: data/full_repos/permissive/465389471/TLC_test.v:41: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars();\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/465389471/TLC_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/465389471/TLC_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TLC_tb;

    reg clk; reg reset;
    reg ena; reg sensor1; reg sensor2;

    wire [1:0] TL1; wire [1:0] TL2;
    wire [1:0] TL3; wire [1:0] TL4;
    wire [1:0] TL5; wire [1:0] TL6;
    wire peak; wire pm;
    wire [7:0] hh; wire [7:0] mm; wire [7:0] ss;

TLC_topModule dut0 (
    .clk(clk), .reset(reset), .ena(ena), .sensor1(sensor1), .sensor2(sensor2),
    .TL1(TL1), .TL2(TL2), .TL3(TL3), .TL4(TL4), .TL5(TL5), .TL6(TL6),
    .peak(peak), .pm(pm), .hh(hh), .mm(mm), .ss(ss)
);



 initial begin

   clk = 1'b0;
   forever #1 clk = ~clk;
 end

 initial begin
   sensor2 = 1'b1;
   forever #1000 sensor2 = ~sensor2;
 end

 initial begin
   sensor1 = 1'b0;
   forever #1000 sensor1 = ~sensor1;
 end
  

 initial begin
   $dumpvars();

    reset = 0; ena = 1; 

    #10 reset = 1; 

    #500 $finish;
 end

endmodule
module TLC_tb;


    reg clk; reg reset;
    reg ena; reg sensor1; reg sensor2;

    wire [1:0] TL1; wire [1:0] TL2;
    wire [1:0] TL3; wire [1:0] TL4;
    wire [1:0] TL5; wire [1:0] TL6;
    wire peak; wire pm;
    wire [7:0] hh; wire [7:0] mm; wire [7:0] ss;

TLC_topModule dut0 (
    .clk(clk), .reset(reset), .ena(ena), .sensor1(sensor1), .sensor2(sensor2),
    .TL1(TL1), .TL2(TL2), .TL3(TL3), .TL4(TL4), .TL5(TL5), .TL6(TL6),
    .peak(peak), .pm(pm), .hh(hh), .mm(mm), .ss(ss)
);



 initial begin

   clk = 1'b0;
   forever #1 clk = ~clk;
 end

 initial begin
   sensor2 = 1'b1;
   forever #1000 sensor2 = ~sensor2;
 end

 initial begin
   sensor1 = 1'b0;
   forever #1000 sensor1 = ~sensor1;
 end
  

 initial begin
   $dumpvars();

    reset = 0; ena = 1; 

    #10 reset = 1; 

    #500 $finish;
 end

endmodule