data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_synch_cl_dl(

syncdata, 

cmp_clk, ctu_dram_tx_sync_early, presyncdata
);


parameter SIZE = 1;
input  cmp_clk;
input  ctu_dram_tx_sync_early;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

   
   dffe_ns  #(SIZE)  u_synch_cl_dl_ff0(
                   .din (presyncdata[SIZE-1:0]),
                   .clk (cmp_clk),
                   .en(ctu_dram_tx_sync_early),
                   .q (syncdata[SIZE-1:0]));

endmodule
module ctu_synch_cl_dl(

syncdata, 

cmp_clk, ctu_dram_tx_sync_early, presyncdata
);



parameter SIZE = 1;
input  cmp_clk;
input  ctu_dram_tx_sync_early;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

   
   dffe_ns  #(SIZE)  u_synch_cl_dl_ff0(
                   .din (presyncdata[SIZE-1:0]),
                   .clk (cmp_clk),
                   .en(ctu_dram_tx_sync_early),
                   .q (syncdata[SIZE-1:0]));

endmodule