data/full_repos/permissive/488093047/Verilog Codes/TB_RegisterFile8Reg.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_RegisterFile8Reg.v\n%Error: Exiting due to 3 error(s)\n'
module TB_RegisterFile8Reg();
reg [31:0]Input;
reg [2:0]seti,seto1,seto2;
reg WR,reset,clk;
wire [31:0] Output1,Output2;

RegisterFile8Reg DUT1 (.Input(Input),.seti(seti),.seto1(seto1),.seto2(seto2),.WR(WR),.reset(reset),.clk(clk),.Output1(Output1),.Output2(Output2));
initial begin

Input = 32'd567;
clk = 1'b1;
reset = 1'b1;
WR=1'b0;seti=3'b000;seto1=3'b000;seto2=3'b000;
#50;

reset = 1'b0;
#50 WR=1'b0;seti=3'b000;seto1=3'b000;seto2=3'b000;
#50 WR=1'b0;seti=3'b001;seto1=3'b010;seto2=3'b011;
#50 WR=1'b0;seti=3'b010;seto1=3'b100;seto2=3'b101;
#50 WR=1'b0;seti=3'b011;seto1=3'b110;seto2=3'b111;

#50 WR=1'b1;seti=3'b000;seto1=3'b011;seto2=3'b000;
#50 WR=1'b1;seti=3'b010;seto1=3'b010;seto2=3'b011;
#50 WR=1'b1;seti=3'b101;seto1=3'b100;seto2=3'b101;
#50 WR=1'b1;seti=3'b111;seto1=3'b110;seto2=3'b111;

end

always #10 clk = ~clk;
endmodule
module TB_RegisterFile8Reg();

reg [31:0]Input;
reg [2:0]seti,seto1,seto2;
reg WR,reset,clk;
wire [31:0] Output1,Output2;

RegisterFile8Reg DUT1 (.Input(Input),.seti(seti),.seto1(seto1),.seto2(seto2),.WR(WR),.reset(reset),.clk(clk),.Output1(Output1),.Output2(Output2));
initial begin

Input = 32'd567;
clk = 1'b1;
reset = 1'b1;
WR=1'b0;seti=3'b000;seto1=3'b000;seto2=3'b000;
#50;

reset = 1'b0;
#50 WR=1'b0;seti=3'b000;seto1=3'b000;seto2=3'b000;
#50 WR=1'b0;seti=3'b001;seto1=3'b010;seto2=3'b011;
#50 WR=1'b0;seti=3'b010;seto1=3'b100;seto2=3'b101;
#50 WR=1'b0;seti=3'b011;seto1=3'b110;seto2=3'b111;

#50 WR=1'b1;seti=3'b000;seto1=3'b011;seto2=3'b000;
#50 WR=1'b1;seti=3'b010;seto1=3'b010;seto2=3'b011;
#50 WR=1'b1;seti=3'b101;seto1=3'b100;seto2=3'b101;
#50 WR=1'b1;seti=3'b111;seto1=3'b110;seto2=3'b111;

end

always #10 clk = ~clk;
endmodule