data/full_repos/permissive/446997925/hw4/ADD_n_bit.v
1: b"%Error: data/full_repos/permissive/446997925/hw4/ADD_n_bit.v:15: Cannot find file containing module: 'ADD_1_bit'\nADD_1_bit  ADDER[31:0] ({c_out, c_inner[31:1]}, ADD_out, R2, R3, {c_inner[31:1], c_in});\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446997925/hw4,data/full_repos/permissive/446997925/ADD_1_bit\n             data/full_repos/permissive/446997925/hw4,data/full_repos/permissive/446997925/ADD_1_bit.v\n             data/full_repos/permissive/446997925/hw4,data/full_repos/permissive/446997925/ADD_1_bit.sv\n             ADD_1_bit\n             ADD_1_bit.v\n             ADD_1_bit.sv\n             obj_dir/ADD_1_bit\n             obj_dir/ADD_1_bit.v\n             obj_dir/ADD_1_bit.sv\n%Error: Exiting due to 1 error(s)\n"
module ADD_n_bit(c_out, ADD_out, R2, R3, c_in);

parameter	word_size = 32;

input		[31:0]	R2, R3;
input								c_in;

output	[31:0]	ADD_out;
output							c_out;

wire		[31:0]	c_inner;


ADD_1_bit 	ADDER[31:0]	({c_out, c_inner[31:1]}, ADD_out, R2, R3, {c_inner[31:1], c_in});

endmodule
module ADD_n_bit(c_out, ADD_out, R2, R3, c_in);


parameter	word_size = 32;

input		[31:0]	R2, R3;
input								c_in;

output	[31:0]	ADD_out;
output							c_out;

wire		[31:0]	c_inner;


ADD_1_bit 	ADDER[31:0]	({c_out, c_inner[31:1]}, ADD_out, R2, R3, {c_inner[31:1], c_in});

endmodule