data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:41: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 11 bits.\n                                                                                                                                  : ... In instance MultiExtModuleTester.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:41: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 13 bits.\n                                                                                                                                  : ... In instance MultiExtModuleTester.u_pad_2\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:41: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 7 bits.\n                                                                                                                                  : ... In instance MultiExtModuleTester.u_pad_3\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:7: Cannot find file containing module: \'SimpleExtModule\'\n    SimpleExtModule dut1 (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference,data/full_repos/permissive/493019833/SimpleExtModule\n             data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference,data/full_repos/permissive/493019833/SimpleExtModule.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference,data/full_repos/permissive/493019833/SimpleExtModule.sv\n             SimpleExtModule\n             SimpleExtModule.v\n             SimpleExtModule.sv\n             obj_dir/SimpleExtModule\n             obj_dir/SimpleExtModule.v\n             obj_dir/SimpleExtModule.sv\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:13: Cannot find file containing module: \'SimpleExtModule\'\n    SimpleExtModule dut2 (\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiExtModuleTester/reference/MultiExtModuleTester.v:19: Cannot find file containing module: \'AdderExtModule\'\n    AdderExtModule dut3 (\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module MultiExtModuleTester(
    input clock,
    input reset
);
    wire [15:0] _dut1__foo;
    wire [15:0] _dut1__bar;
    SimpleExtModule dut1 (
        .foo(_dut1__foo),
        .bar(_dut1__bar)
    );
    wire [15:0] _dut2__foo;
    wire [15:0] _dut2__bar;
    SimpleExtModule dut2 (
        .foo(_dut2__foo),
        .bar(_dut2__bar)
    );
    wire [15:0] _dut3__foo;
    wire [15:0] _dut3__bar;
    AdderExtModule dut3 (
        .foo(_dut3__foo),
        .bar(_dut3__bar)
    );
    PAD_UNSIGNED #(.width(11), .n(16)) u_pad_1 (
        .y(_dut1__foo),
        .in(11'h4D2)
    );
    PAD_UNSIGNED #(.width(13), .n(16)) u_pad_2 (
        .y(_dut2__foo),
        .in(13'h162E)
    );
    PAD_UNSIGNED #(.width(7), .n(16)) u_pad_3 (
        .y(_dut3__foo),
        .in(7'h64)
    );
endmodule
module MultiExtModuleTester(
    input clock,
    input reset
);

    wire [15:0] _dut1__foo;
    wire [15:0] _dut1__bar;
    SimpleExtModule dut1 (
        .foo(_dut1__foo),
        .bar(_dut1__bar)
    );
    wire [15:0] _dut2__foo;
    wire [15:0] _dut2__bar;
    SimpleExtModule dut2 (
        .foo(_dut2__foo),
        .bar(_dut2__bar)
    );
    wire [15:0] _dut3__foo;
    wire [15:0] _dut3__bar;
    AdderExtModule dut3 (
        .foo(_dut3__foo),
        .bar(_dut3__bar)
    );
    PAD_UNSIGNED #(.width(11), .n(16)) u_pad_1 (
        .y(_dut1__foo),
        .in(11'h4D2)
    );
    PAD_UNSIGNED #(.width(13), .n(16)) u_pad_2 (
        .y(_dut2__foo),
        .in(13'h162E)
    );
    PAD_UNSIGNED #(.width(7), .n(16)) u_pad_3 (
        .y(_dut3__foo),
        .in(7'h64)
    );
endmodule