data/full_repos/permissive/416058412/hw/rtl/single_clock_wr_ram.sv
data/verilator_xmls/87cfdbeb-845d-4604-aeba-a84a3cb48185.xml
module single_clock_wr_ram
    #(
        parameter DATA_WIDTH = 32,
        parameter ADR_WIDTH  = 8
    )
    (
        output reg [DATA_WIDTH-1:0] q,
        input [DATA_WIDTH-1:0] d,
        input [ADR_WIDTH-1:0] write_address, read_address,
        input we, clk
    );

    reg [DATA_WIDTH-1:0] mem [(2**ADR_WIDTH)-1:0];

    always @ (posedge clk) begin
        if (we)
            mem[write_address] <= d;
        q <= mem[read_address];
    end

endmodule
module single_clock_wr_ram
    #(
        parameter DATA_WIDTH = 32,
        parameter ADR_WIDTH  = 8
    )
    (
        output reg [DATA_WIDTH-1:0] q,
        input [DATA_WIDTH-1:0] d,
        input [ADR_WIDTH-1:0] write_address, read_address,
        input we, clk
    );


    reg [DATA_WIDTH-1:0] mem [(2**ADR_WIDTH)-1:0];

    always @ (posedge clk) begin
        if (we)
            mem[write_address] <= d;
        q <= mem[read_address];
    end

endmodule