data/full_repos/permissive/46989236/alu/alu_tb.v
1: b'%Error: data/full_repos/permissive/46989236/alu/alu_tb.v:14: Unsupported or unknown PLI call: $monitor\n$monitor ("%d\\t%d\\top=%b,b=%b,c=%b,ah=%b,al=%b",$time,clock,opcode,b,c,ah,al);\n^~~~~~~~\n%Error: data/full_repos/permissive/46989236/alu/alu_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("plot.vcd");\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10 b = 4\'d10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10 c = 4\'d2;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#20 opcode = 3\'b111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/alu/alu_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#5 clock = !clock;\n^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb;
reg clock,reset;
reg [3:0]b,c;
wire [3:0]al,ah;
reg [2:0]opcode;

initial
begin
opcode = 3'b000;
reset = 1'b0;
clock = 1'b0;
b = 4'd0;
c = 4'd0;
$monitor ("%d\t%d\top=%b,b=%b,c=%b,ah=%b,al=%b",$time,clock,opcode,b,c,ah,al);
$dumpfile("plot.vcd");
#10 b = 4'd10;
#10 c = 4'd2;
#20 opcode = 3'b001;
#20 opcode = 3'b010;
#20 opcode = 3'b011;
#20 opcode = 3'b100;
#20 opcode = 3'b101;
#20 opcode = 3'b110;
#20 opcode = 3'b111;
$finish;
end

always begin 
#5 clock = !clock;
end


alu a(
.clock (clock),
.opcode (opcode),
.b (b),
.c (c),
.reset (reset),
.al (al),
.ah (ah)
);
endmodule
module alu_tb;

reg clock,reset;
reg [3:0]b,c;
wire [3:0]al,ah;
reg [2:0]opcode;

initial
begin
opcode = 3'b000;
reset = 1'b0;
clock = 1'b0;
b = 4'd0;
c = 4'd0;
$monitor ("%d\t%d\top=%b,b=%b,c=%b,ah=%b,al=%b",$time,clock,opcode,b,c,ah,al);
$dumpfile("plot.vcd");
#10 b = 4'd10;
#10 c = 4'd2;
#20 opcode = 3'b001;
#20 opcode = 3'b010;
#20 opcode = 3'b011;
#20 opcode = 3'b100;
#20 opcode = 3'b101;
#20 opcode = 3'b110;
#20 opcode = 3'b111;
$finish;
end

always begin 
#5 clock = !clock;
end


alu a(
.clock (clock),
.opcode (opcode),
.b (b),
.c (c),
.reset (reset),
.al (al),
.ah (ah)
);
endmodule