data/full_repos/permissive/493514142/verilog/rtl/FPU/LZD_layer4.v
1: b"%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/LZD_layer4.v:19: Cannot find file containing module: 'FPU_LZD_mux'\nFPU_LZD_mux L4_0 (.in_val_2(L4_input_pos_val[9]),   .in_pos_2(L4_input_pos_val[8:5]),   .in_val_1(L4_input_pos_val[4]),  .in_pos_1(L4_input_pos_val[3:0]),  .out_pos(L4_wire_output_pos), .out_val(L4_wire_output_val)); defparam L4_0.layer = 4;\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux.v\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux.sv\n             FPU_LZD_mux\n             FPU_LZD_mux.v\n             FPU_LZD_mux.sv\n             obj_dir/FPU_LZD_mux\n             obj_dir/FPU_LZD_mux.v\n             obj_dir/FPU_LZD_mux.sv\n%Error: Exiting due to 1 error(s)\n"
module LZD_layer_4 (L4_input_pos_val, L4_output_pos, L4_output_valid);

parameter layer = 4;


input [9 :0]L4_input_pos_val;


output [4 : 0] L4_output_pos;
output L4_output_valid;


wire L4_wire_output_val;
wire [layer : 0] L4_wire_output_pos;


FPU_LZD_mux L4_0 (.in_val_2(L4_input_pos_val[9]),   .in_pos_2(L4_input_pos_val[8:5]),   .in_val_1(L4_input_pos_val[4]),  .in_pos_1(L4_input_pos_val[3:0]),  .out_pos(L4_wire_output_pos), .out_val(L4_wire_output_val)); defparam L4_0.layer = 4;

assign L4_output_pos = L4_wire_output_pos;
assign L4_output_valid = L4_wire_output_val;
endmodule
module LZD_layer_4 (L4_input_pos_val, L4_output_pos, L4_output_valid);


parameter layer = 4;


input [9 :0]L4_input_pos_val;


output [4 : 0] L4_output_pos;
output L4_output_valid;


wire L4_wire_output_val;
wire [layer : 0] L4_wire_output_pos;


FPU_LZD_mux L4_0 (.in_val_2(L4_input_pos_val[9]),   .in_pos_2(L4_input_pos_val[8:5]),   .in_val_1(L4_input_pos_val[4]),  .in_pos_1(L4_input_pos_val[3:0]),  .out_pos(L4_wire_output_pos), .out_val(L4_wire_output_val)); defparam L4_0.layer = 4;

assign L4_output_pos = L4_wire_output_pos;
assign L4_output_valid = L4_wire_output_val;
endmodule