data/full_repos/permissive/513398397/verilog/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/513398397/verilog/ALU.v:11: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                     : ... In instance ALU\nwire SLT_cond = (ALUSel == 3\'b010);\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/513398397/verilog/ALU.v:13: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                     : ... In instance ALU\nassign ADD = A + B_compliment + ALUSel[3];\n                              ^\n%Error: data/full_repos/permissive/513398397/verilog/ALU.v:22: Cannot find file containing module: \'COMP32b\'\nCOMP32b COMPARE(SLT, A, B, ALUSel[0]);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.v\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.sv\n             COMP32b\n             COMP32b.v\n             COMP32b.sv\n             obj_dir/COMP32b\n             obj_dir/COMP32b.v\n             obj_dir/COMP32b.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module ALU(
    output [31:0] ALU_o,
    input signed  [31:0] A, B,
    input  [3:0]  ALUSel
);

wire signed [31:0] ADD, SRA, SLL, SRL, XOR, AND, OR, SR;
wire signed [31:0] B_compliment = ALUSel[3] ? ~B : B;
wire signed [4:0] shamt = B[4:0];
wire SLT;
wire SLT_cond = (ALUSel == 3'b010);

assign ADD = A + B_compliment + ALUSel[3];
assign XOR = A ^ B;
assign AND = A & B;
assign OR  = A | B;
assign SLL = A << (shamt);
assign SRL = A >> (shamt);
assign SRA = A >>> (shamt);
assign SR = ALUSel[3] ? SRA : SRL;

COMP32b COMPARE(SLT, A, B, ALUSel[0]);
mux8to1 MUX0(ALU_o, ADD, SLL, {31'b0, SLT}, {31'b0, SLT}, XOR, SR, OR, AND, ALUSel[2:0]);

endmodule
module ALU(
    output [31:0] ALU_o,
    input signed  [31:0] A, B,
    input  [3:0]  ALUSel
);


wire signed [31:0] ADD, SRA, SLL, SRL, XOR, AND, OR, SR;
wire signed [31:0] B_compliment = ALUSel[3] ? ~B : B;
wire signed [4:0] shamt = B[4:0];
wire SLT;
wire SLT_cond = (ALUSel == 3'b010);

assign ADD = A + B_compliment + ALUSel[3];
assign XOR = A ^ B;
assign AND = A & B;
assign OR  = A | B;
assign SLL = A << (shamt);
assign SRL = A >> (shamt);
assign SRA = A >>> (shamt);
assign SR = ALUSel[3] ? SRA : SRL;

COMP32b COMPARE(SLT, A, B, ALUSel[0]);
mux8to1 MUX0(ALU_o, ADD, SLL, {31'b0, SLT}, {31'b0, SLT}, XOR, SR, OR, AND, ALUSel[2:0]);

endmodule