data/full_repos/permissive/458737381/src/verilog-parser/tests/ch_mem.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ch_mem.v:122: Unsupported: Verilog 1995 force\n       force XXDQS = dq_inv;\n       ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ch_mem.v:125: Unsupported: Verilog 1995 release\n       release XXDQS[35:0];\n       ^~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ch_mem (

   XXSDA, XXDQ, XXCB, XXDQS, 

   XXRAS_L, XXCAS_L, XXWE_L, XXCS_L, XXRESET_L, XXADDR, XXBA, XXSA, 
   XXSCL, XXWP, XXCLK, XXCLK_L, XXCKE
   );
   
   input 	 XXRAS_L;
   input 	 XXCAS_L;
   input 	 XXWE_L;
   input [3:0] 	 XXCS_L;
   input 	 XXRESET_L;
   input [14:0]  XXADDR;
   input [2:0]   XXBA;
   input [2:0]   XXSA;
   input  	 XXSCL;
   inout  	 XXSDA;
   input  	 XXWP;
   input [3:0]	 XXCLK;
   input [3:0] 	 XXCLK_L;
   input 	 XXCKE;
   


   inout [127:0] XXDQ;
   inout [15:0]  XXCB;
   inout [35:0]  XXDQS;
   





   integer TRACE_DELAY;
   initial begin 
     if (! $value$plusargs("TRACE_DELAY=%d", TRACE_DELAY)) begin
       TRACE_DELAY = 0 ;
     end
   end
   



   



   wire [3:0]	 #TRACE_DELAY TDCLK   = XXCLK;
   wire [3:0] 	 #TRACE_DELAY TDCLK_L = XXCLK_L;







   wire [2:0] 	 tump = XXCLK_L[3:1];


   reg [35:0] dq_inv;
   reg [3:0] count;
   reg [2:0] count_dqs;
   reg wiggle, force_dqs;

   initial 
    begin 
     dq_inv = 0;
     count = 0;
     count_dqs = 0;
     wiggle = 0;
     force_dqs = 0;
    end


    always @(XXCLK[3]) begin 
     if ($test$plusargs("WIGGLE_DQS")) begin
      dq_inv = ~dq_inv;
      count  <= (count > 0) ? count - 1 : count;
      count_dqs  <= (count_dqs > 0) ? count_dqs - 1 : count_dqs;
      if ( XXRAS_L && !XXCAS_L && !XXWE_L ) begin 
        wiggle <= 1'b1;
        count  <= 4'b1111;
      end
      if ( wiggle && (count == 0) && !force_dqs ) begin 
        force_dqs <= 1'b1;
        count_dqs <= 3'b111;
      end else if (count_dqs == 3'b001 ) begin 
        force_dqs <= 1'b0;
        wiggle <= 1'b0;
      end
    end
    end


   always @(posedge force_dqs or XXCLK[3]) begin 
     if ($test$plusargs("WIGGLE_DQS")) begin

     if(force_dqs == 1) begin 
       force XXDQS = dq_inv;
       $display("%0d : WIGGLE_DQS", $time);
     end else
       release XXDQS[35:0];
     end
   end

 

   
`ifdef DENALI_ON
    denali_ddrII dimm0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
     		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[0]),
		     .Ck_n		(TDCLK_L[0]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[0]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));

    denali_ddrII  dimm1(


		      .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		      .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		      .Addr		(XXADDR[14:0]),
		      .Ba		(XXBA[2:0]),
		      .Ck		(TDCLK[0]),
		      .Ck_n		(TDCLK_L[0]),
		      .Cke		(XXCKE),
		      .Cs_n		(XXCS_L[0]),
		      .Ras_n		(XXRAS_L),
		      .Cas_n		(XXCAS_L),
		      .We_n		(XXWE_L),
		      .Reset_n		(XXRESET_L));
   
`ifdef STACK_DIMM
   denali_ddrII dimms0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[1]),
		     .Ck_n		(TDCLK_L[1]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[1]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));


   denali_ddrII dimms1(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[1]),
		     .Ck_n		(TDCLK_L[1]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[1]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
`endif

`ifdef RANK_DIMM

   denali_ddrII dimmr0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[2]),
		     .Ck_n		(TDCLK_L[2]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[2]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
   denali_ddrII dimmr1(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[2]),
		     .Ck_n		(TDCLK_L[2]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[2]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));

`ifdef STACK_DIMM
   denali_ddrII dimmr2(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[3]),
		     .Ck_n		(TDCLK_L[3]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[3]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
   denali_ddrII dimmr3(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[3]),
		     .Ck_n		(TDCLK_L[3]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[3]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
`endif
`endif

`else

`ifdef DRAM_SAT

    DIMMx4 dimm0( 
		       .DQ		(XXDQ[127: 64]),
		       .CB		(XXCB[15: 8]),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[0]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0000)
			 );

   DIMMx4 dimm1( 
		      .DQ		(XXDQ[63: 0]),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		      .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[0]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0000)
			);

`ifdef STACK_DIMM
    DIMMx4 dimms0( 
		       .DQ		(XXDQ[127: 64]),
		       .CB		(XXCB[15: 8]),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[1]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0001)
			 );

   DIMMx4 dimms1( 
		      .DQ		(XXDQ[63: 0]),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[1]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0001)
			);
`endif

`ifdef RANK_DIMM

    DIMMx4 dimmr0(
		       .DQ		({XXDQ[127: 64]}),
		       .CB		({XXCB[15: 8]}),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[2]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0010)
			);

   DIMMx4 dimmr1( 
		      .DQ		({XXDQ[63: 0]}),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[2]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0010)
			);
   
`ifdef STACK_DIMM
    DIMMx4 dimmr2(
		       .DQ		({XXDQ[127: 64]}),
		       .CB		({XXCB[15: 8]}),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[3]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0011)
			);

   DIMMx4 dimmr3( 
		      .DQ		({XXDQ[63: 0]}),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[3]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0011)
			);
`endif
`endif

`else

    reg     dram_init_done;
    wire new_addr_bit1 = ~XXCS_L[2] | ~XXCS_L[3];
    wire new_addr_bit0 = ~XXCS_L[1] | ~XXCS_L[3];
    wire new_cs = XXCS_L[0] & XXCS_L[1] & XXCS_L[2] & XXCS_L[3];

    wire new_XXRAS_L = XXRAS_L | (dram_init_done & ~XXRAS_L & ~XXCAS_L ? 1'b1 : 1'b0);
    wire new_XXCAS_L = XXCAS_L | (dram_init_done & ~XXRAS_L & ~XXCAS_L ? 1'b1 : 1'b0);

    initial dram_init_done = 1'b0;
    always @ (posedge XXCLK) begin
        if(dram_init_done) dram_init_done = 1'b1;
        if(~dram_init_done & ~XXRAS_L & XXCAS_L & XXWE_L) dram_init_done = 1'b1;
    end

`ifdef INFINEON
    RDIMM_1R_x4 dimm0(
                       .DQ              (XXDQ[127: 64]),
                       .CB              (XXCB[15: 8]),
                       .DQS             ({XXDQS[26],
                                          XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
                                          XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
                       .DM_RDQS         ({XXDQS[35],
                                          XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
                                          XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


                       .Addr            ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2 
                       .BA              (XXBA[1:0]),
`else
                       .BA              (XXBA[2:0]),
`endif  
                       .CK              ({3{TDCLK[0]}}),
                       .bCK             ({3{TDCLK_L[0]}}),
                       .CKE             ({XXCKE,XXCKE}),
                       .bCS             ({new_cs,new_cs}),
                       .bRAS            (new_XXRAS_L),
                       .bCAS            (new_XXCAS_L),
                       .bWE             (XXWE_L),




		       .ODT          (2'b00),
                       .CS_SEL          (8'b0000_0000)
                         );

   RDIMM_1R_x4 dimm1(
                      .DQ               (XXDQ[63: 0]),
                      .CB               ({XXCB[7: 0]}),
                      .DQS              ({XXDQS[8],
                                          XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
                                          XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
                      .DM_RDQS          ({XXDQS[17],
                                          XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
                                          XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


                      .Addr             ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2
                      .BA               (XXBA[1:0]),
`else
                      .BA               (XXBA[2:0]),
`endif
                      .CK               ({3{TDCLK[0]}}),
                      .bCK              ({3{TDCLK_L[0]}}),
                      .CKE              ({XXCKE,XXCKE}),
                      .bCS              ({new_cs,new_cs}),
                      .bRAS             (new_XXRAS_L),
                      .bCAS             (new_XXCAS_L),
                      .bWE              (XXWE_L),




		       .ODT          (2'b00),
                      .CS_SEL           (8'b0000_0000)
                        );
`else

    dimm dimm0(
                       .dataq            (XXDQ[127: 64]),
                       .ecc              (XXCB[15: 8]),
                       .dqs             ({XXDQS[26],
                                          XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
                                          XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
                       .dm_rdqs         ({XXDQS[35],
                                          XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
                                          XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),

                       .addr            ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2 
                       .ba              (XXBA[1:0]),
`else
                       .ba              (XXBA[2:0]),
`endif  
                       .clk              ({3{TDCLK[0]}}),
                       .cs             ({new_cs,new_cs}),
                       .ras            (new_XXRAS_L),
                       .cas            (new_XXCAS_L),
                       .we             (XXWE_L),
                       .cs_sel          (8'b0000_0000)
                         );

   dimm dimm1(
                      .dataq               (XXDQ[63: 0]),
                      .ecc               ({XXCB[7: 0]}),
                      .dqs              ({XXDQS[8],
                                          XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
                                          XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
                      .dm_rdqs          ({XXDQS[17],
                                          XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
                                          XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),

                      .addr             ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2
                      .ba               (XXBA[1:0]),
`else
                      .ba               (XXBA[2:0]),
`endif
                      .clk               ({3{TDCLK[0]}}),
                      .cs              ({new_cs,new_cs}),
                      .ras             (new_XXRAS_L),
                      .cas             (new_XXCAS_L),
                      .we              (XXWE_L),
                      .cs_sel           (8'b0000_0000)
                        );

`endif

`endif
`endif

endmodule
module ch_mem (

   XXSDA, XXDQ, XXCB, XXDQS, 

   XXRAS_L, XXCAS_L, XXWE_L, XXCS_L, XXRESET_L, XXADDR, XXBA, XXSA, 
   XXSCL, XXWP, XXCLK, XXCLK_L, XXCKE
   );

   
   input 	 XXRAS_L;
   input 	 XXCAS_L;
   input 	 XXWE_L;
   input [3:0] 	 XXCS_L;
   input 	 XXRESET_L;
   input [14:0]  XXADDR;
   input [2:0]   XXBA;
   input [2:0]   XXSA;
   input  	 XXSCL;
   inout  	 XXSDA;
   input  	 XXWP;
   input [3:0]	 XXCLK;
   input [3:0] 	 XXCLK_L;
   input 	 XXCKE;
   


   inout [127:0] XXDQ;
   inout [15:0]  XXCB;
   inout [35:0]  XXDQS;
   





   integer TRACE_DELAY;
   initial begin 
     if (! $value$plusargs("TRACE_DELAY=%d", TRACE_DELAY)) begin
       TRACE_DELAY = 0 ;
     end
   end
   



   



   wire [3:0]	 #TRACE_DELAY TDCLK   = XXCLK;
   wire [3:0] 	 #TRACE_DELAY TDCLK_L = XXCLK_L;







   wire [2:0] 	 tump = XXCLK_L[3:1];


   reg [35:0] dq_inv;
   reg [3:0] count;
   reg [2:0] count_dqs;
   reg wiggle, force_dqs;

   initial 
    begin 
     dq_inv = 0;
     count = 0;
     count_dqs = 0;
     wiggle = 0;
     force_dqs = 0;
    end


    always @(XXCLK[3]) begin 
     if ($test$plusargs("WIGGLE_DQS")) begin
      dq_inv = ~dq_inv;
      count  <= (count > 0) ? count - 1 : count;
      count_dqs  <= (count_dqs > 0) ? count_dqs - 1 : count_dqs;
      if ( XXRAS_L && !XXCAS_L && !XXWE_L ) begin 
        wiggle <= 1'b1;
        count  <= 4'b1111;
      end
      if ( wiggle && (count == 0) && !force_dqs ) begin 
        force_dqs <= 1'b1;
        count_dqs <= 3'b111;
      end else if (count_dqs == 3'b001 ) begin 
        force_dqs <= 1'b0;
        wiggle <= 1'b0;
      end
    end
    end


   always @(posedge force_dqs or XXCLK[3]) begin 
     if ($test$plusargs("WIGGLE_DQS")) begin

     if(force_dqs == 1) begin 
       force XXDQS = dq_inv;
       $display("%0d : WIGGLE_DQS", $time);
     end else
       release XXDQS[35:0];
     end
   end

 

   
`ifdef DENALI_ON
    denali_ddrII dimm0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
     		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[0]),
		     .Ck_n		(TDCLK_L[0]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[0]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));

    denali_ddrII  dimm1(


		      .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		      .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		      .Addr		(XXADDR[14:0]),
		      .Ba		(XXBA[2:0]),
		      .Ck		(TDCLK[0]),
		      .Ck_n		(TDCLK_L[0]),
		      .Cke		(XXCKE),
		      .Cs_n		(XXCS_L[0]),
		      .Ras_n		(XXRAS_L),
		      .Cas_n		(XXCAS_L),
		      .We_n		(XXWE_L),
		      .Reset_n		(XXRESET_L));
   
`ifdef STACK_DIMM
   denali_ddrII dimms0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[1]),
		     .Ck_n		(TDCLK_L[1]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[1]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));


   denali_ddrII dimms1(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[1]),
		     .Ck_n		(TDCLK_L[1]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[1]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
`endif

`ifdef RANK_DIMM

   denali_ddrII dimmr0(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[2]),
		     .Ck_n		(TDCLK_L[2]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[2]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
   denali_ddrII dimmr1(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[2]),
		     .Ck_n		(TDCLK_L[2]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[2]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));

`ifdef STACK_DIMM
   denali_ddrII dimmr2(


		     .Dq		({XXCB[15: 8], XXDQ[127: 64]}),
		     .Dqs		({XXDQS[35], XXDQS[26], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22],
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[3]),
		     .Ck_n		(TDCLK_L[3]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[3]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
   denali_ddrII dimmr3(


		     .Dq		({XXCB[7: 0], XXDQ[63: 0]}),
		     .Dqs		({XXDQS[17], XXDQS[8], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4],
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),

		     .Addr		(XXADDR[14:0]),
		     .Ba		(XXBA[2:0]),
		     .Ck		(TDCLK[3]),
		     .Ck_n		(TDCLK_L[3]),
		     .Cke		(XXCKE),
		     .Cs_n		(XXCS_L[3]),
		     .Ras_n		(XXRAS_L),
		     .Cas_n		(XXCAS_L),
		     .We_n		(XXWE_L),
		     .Reset_n		(XXRESET_L));
`endif
`endif

`else

`ifdef DRAM_SAT

    DIMMx4 dimm0( 
		       .DQ		(XXDQ[127: 64]),
		       .CB		(XXCB[15: 8]),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[0]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0000)
			 );

   DIMMx4 dimm1( 
		      .DQ		(XXDQ[63: 0]),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		      .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[0]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0000)
			);

`ifdef STACK_DIMM
    DIMMx4 dimms0( 
		       .DQ		(XXDQ[127: 64]),
		       .CB		(XXCB[15: 8]),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[1]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0001)
			 );

   DIMMx4 dimms1( 
		      .DQ		(XXDQ[63: 0]),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[1]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0001)
			);
`endif

`ifdef RANK_DIMM

    DIMMx4 dimmr0(
		       .DQ		({XXDQ[127: 64]}),
		       .CB		({XXCB[15: 8]}),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[2]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0010)
			);

   DIMMx4 dimmr1( 
		      .DQ		({XXDQ[63: 0]}),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[2]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0010)
			);
   
`ifdef STACK_DIMM
    DIMMx4 dimmr2(
		       .DQ		({XXDQ[127: 64]}),
		       .CB		({XXCB[15: 8]}),
		       .DQS		({XXDQS[26], 
					  XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
					  XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
		       .DM_RDQS		({XXDQS[35], 
					  XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
					  XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


		       .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		       .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		       .CK		({3{TDCLK[0]}}),
		       .bCK		({3{TDCLK_L[0]}}),
		       .CKE		(XXCKE),
		       .bCS		(XXCS_L[3]),
		       .bRAS		(XXRAS_L),
		       .bCAS		(XXCAS_L),
		       .bWE		(XXWE_L),




		       .CS_SEL          (8'b0000_0011)
			);

   DIMMx4 dimmr3( 
		      .DQ		({XXDQ[63: 0]}),
		      .CB		({XXCB[7: 0]}),
		      .DQS		({XXDQS[8], 
					  XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
					  XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
		      .DM_RDQS		({XXDQS[17], 
					  XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
					  XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


		      .Addr		(XXADDR[14:0]),
`ifdef DRAM_BANK_BITS2
		      .BA		(XXBA[1:0]),
`else
		       .BA		(XXBA[2:0]),
`endif
		      .CK		({3{TDCLK[0]}}),
		      .bCK		({3{TDCLK_L[0]}}),
		      .CKE		(XXCKE),
		      .bCS		(XXCS_L[3]),
		      .bRAS		(XXRAS_L),
		      .bCAS		(XXCAS_L),
		      .bWE		(XXWE_L),




		      .CS_SEL           (8'b0000_0011)
			);
`endif
`endif

`else

    reg     dram_init_done;
    wire new_addr_bit1 = ~XXCS_L[2] | ~XXCS_L[3];
    wire new_addr_bit0 = ~XXCS_L[1] | ~XXCS_L[3];
    wire new_cs = XXCS_L[0] & XXCS_L[1] & XXCS_L[2] & XXCS_L[3];

    wire new_XXRAS_L = XXRAS_L | (dram_init_done & ~XXRAS_L & ~XXCAS_L ? 1'b1 : 1'b0);
    wire new_XXCAS_L = XXCAS_L | (dram_init_done & ~XXRAS_L & ~XXCAS_L ? 1'b1 : 1'b0);

    initial dram_init_done = 1'b0;
    always @ (posedge XXCLK) begin
        if(dram_init_done) dram_init_done = 1'b1;
        if(~dram_init_done & ~XXRAS_L & XXCAS_L & XXWE_L) dram_init_done = 1'b1;
    end

`ifdef INFINEON
    RDIMM_1R_x4 dimm0(
                       .DQ              (XXDQ[127: 64]),
                       .CB              (XXCB[15: 8]),
                       .DQS             ({XXDQS[26],
                                          XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
                                          XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
                       .DM_RDQS         ({XXDQS[35],
                                          XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
                                          XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),


                       .Addr            ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2 
                       .BA              (XXBA[1:0]),
`else
                       .BA              (XXBA[2:0]),
`endif  
                       .CK              ({3{TDCLK[0]}}),
                       .bCK             ({3{TDCLK_L[0]}}),
                       .CKE             ({XXCKE,XXCKE}),
                       .bCS             ({new_cs,new_cs}),
                       .bRAS            (new_XXRAS_L),
                       .bCAS            (new_XXCAS_L),
                       .bWE             (XXWE_L),




		       .ODT          (2'b00),
                       .CS_SEL          (8'b0000_0000)
                         );

   RDIMM_1R_x4 dimm1(
                      .DQ               (XXDQ[63: 0]),
                      .CB               ({XXCB[7: 0]}),
                      .DQS              ({XXDQS[8],
                                          XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
                                          XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
                      .DM_RDQS          ({XXDQS[17],
                                          XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
                                          XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),


                      .Addr             ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2
                      .BA               (XXBA[1:0]),
`else
                      .BA               (XXBA[2:0]),
`endif
                      .CK               ({3{TDCLK[0]}}),
                      .bCK              ({3{TDCLK_L[0]}}),
                      .CKE              ({XXCKE,XXCKE}),
                      .bCS              ({new_cs,new_cs}),
                      .bRAS             (new_XXRAS_L),
                      .bCAS             (new_XXCAS_L),
                      .bWE              (XXWE_L),




		       .ODT          (2'b00),
                      .CS_SEL           (8'b0000_0000)
                        );
`else

    dimm dimm0(
                       .dataq            (XXDQ[127: 64]),
                       .ecc              (XXCB[15: 8]),
                       .dqs             ({XXDQS[26],
                                          XXDQS[30], XXDQS[21], XXDQS[29], XXDQS[20],
                                          XXDQS[28], XXDQS[19], XXDQS[27], XXDQS[18]}),
                       .dm_rdqs         ({XXDQS[35],
                                          XXDQS[34], XXDQS[25], XXDQS[33], XXDQS[24],
                                          XXDQS[32], XXDQS[23], XXDQS[31], XXDQS[22]}),

                       .addr            ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2 
                       .ba              (XXBA[1:0]),
`else
                       .ba              (XXBA[2:0]),
`endif  
                       .clk              ({3{TDCLK[0]}}),
                       .cs             ({new_cs,new_cs}),
                       .ras            (new_XXRAS_L),
                       .cas            (new_XXCAS_L),
                       .we             (XXWE_L),
                       .cs_sel          (8'b0000_0000)
                         );

   dimm dimm1(
                      .dataq               (XXDQ[63: 0]),
                      .ecc               ({XXCB[7: 0]}),
                      .dqs              ({XXDQS[8],
                                          XXDQS[12], XXDQS[3], XXDQS[11], XXDQS[2],
                                          XXDQS[10], XXDQS[1], XXDQS[9], XXDQS[0]}),
                      .dm_rdqs          ({XXDQS[17],
                                          XXDQS[16], XXDQS[7], XXDQS[15], XXDQS[6],
                                          XXDQS[14], XXDQS[5], XXDQS[13], XXDQS[4]}),

                      .addr             ({new_addr_bit1, new_addr_bit0, XXADDR[14:0]}),
`ifdef DRAM_BANK_BITS2
                      .ba               (XXBA[1:0]),
`else
                      .ba               (XXBA[2:0]),
`endif
                      .clk               ({3{TDCLK[0]}}),
                      .cs              ({new_cs,new_cs}),
                      .ras             (new_XXRAS_L),
                      .cas             (new_XXCAS_L),
                      .we              (XXWE_L),
                      .cs_sel           (8'b0000_0000)
                        );

`endif

`endif
`endif

endmodule