data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:99: Define or directive not defined: '`BB_ADRES_BIT'\nwire         [`BB_ADRES_BIT-1:0]             bb_addr0                ;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/user_project_wrapper.v:104: Define or directive not defined: '`BB_ADRES_BIT'\nwire         [`BB_ADRES_BIT-1:0]             bb_addr1                ;\n              ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);




wire                                         vb_clk0                 ;
wire                                         vb_csb0                 ;
wire                                         vb_web0                 ;
wire         [3:0]                           vb_wmask0               ;
wire         [12:0]                          vb_addr0                ;
wire         [31:0]                          vb_din0                 ;
wire         [31:0]                          vb_dout0                ;
wire                                         vb_clk1                 ;
wire                                         vb_csb1                 ;
wire         [12:0]                          vb_addr1                ;
wire         [31:0]                          vb_dout1                ;
wire                                         bb_clk0                 ;
wire                                         bb_csb0                 ;
wire                                         bb_web0                 ;
wire         [3:0]                           bb_wmask0               ;
wire         [`BB_ADRES_BIT-1:0]             bb_addr0                ;
wire         [31:0]                          bb_din0                 ;
wire         [31:0]                          bb_dout0                ;
wire                                         bb_clk1                 ;
wire                                         bb_csb1                 ;
wire         [`BB_ADRES_BIT-1:0]             bb_addr1                ;
wire         [31:0]                          bb_dout1                ;    

c0_system mprj (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .clk_g(wb_clk_i),
    .rst_g(wb_rst_i),


    .tx(io_out[1]),
    .rx(io_in[0]),
    .io_gecerli(io_out[2]),
    .io_ps(io_out[34:3]),
    .io_oeb(io_oeb),


    .bb_csb0                                           (bb_csb0)                                                       ,
    .bb_web0                                           (bb_web0)                                                       ,
    .bb_wmask0                                         (bb_wmask0)                                                     ,
    .bb_addr0                                          (bb_addr0)                                                      ,
    .bb_din0                                           (bb_din0)                                                       ,
    .bb_dout0                                          (bb_dout0)                                                      ,

    .bb_csb1                                           (bb_csb1)                                                       ,
    .bb_addr1                                          (bb_addr1)                                                      ,
    .bb_dout1                                          (bb_dout1)                                                      ,

    .vb_csb0                                           (vb_csb0)                                                       ,
    .vb_web0                                           (vb_web0)                                                       ,
    .vb_wmask0                                         (vb_wmask0)                                                     ,
    .vb_addr0                                          (vb_addr0)                                                      ,
    .vb_din0                                           (vb_din0)                                                       ,
    .vb_dout0                                          (vb_dout0)                                                      ,

    .vb_csb1                                           (vb_csb1)                                                       ,
    .vb_addr1                                          (vb_addr1)                                                      ,
    .vb_dout1                                          (vb_dout1) 
);

sky130_sram_2kbyte_1rw1r_32x512_8 VB_SRAM
(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif        

    .clk0               (wb_clk_i)        ,
    .csb0               (vb_csb0)        ,
    .web0               (vb_web0)        ,
    .wmask0             (vb_wmask0)      ,
    .addr0              (vb_addr0)       ,
    .din0               (vb_din0)        ,
    .dout0              (vb_dout0)       ,
    .clk1               (wb_clk_i)        ,
    .csb1               (vb_csb1)        ,
    .addr1              (vb_addr1)       ,
    .dout1              (vb_dout1)     
);

sky130_sram_2kbyte_1rw1r_32x512_8 BB_SRAM
(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif        

    .clk0               (wb_clk_i)      ,
    .csb0               (bb_csb0)      ,
    .web0               (bb_web0)      ,
    .wmask0             (bb_wmask0)    ,
    .addr0              (bb_addr0)     ,
    .din0               (bb_din0)      ,
    .dout0              (bb_dout0)     ,
    .clk1               (wb_clk_i)      ,
    .csb1               (bb_csb1)      ,
    .addr1              (bb_addr1)     ,
    .dout1              (bb_dout1)   
);
endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





wire                                         vb_clk0                 ;
wire                                         vb_csb0                 ;
wire                                         vb_web0                 ;
wire         [3:0]                           vb_wmask0               ;
wire         [12:0]                          vb_addr0                ;
wire         [31:0]                          vb_din0                 ;
wire         [31:0]                          vb_dout0                ;
wire                                         vb_clk1                 ;
wire                                         vb_csb1                 ;
wire         [12:0]                          vb_addr1                ;
wire         [31:0]                          vb_dout1                ;
wire                                         bb_clk0                 ;
wire                                         bb_csb0                 ;
wire                                         bb_web0                 ;
wire         [3:0]                           bb_wmask0               ;
wire         [`BB_ADRES_BIT-1:0]             bb_addr0                ;
wire         [31:0]                          bb_din0                 ;
wire         [31:0]                          bb_dout0                ;
wire                                         bb_clk1                 ;
wire                                         bb_csb1                 ;
wire         [`BB_ADRES_BIT-1:0]             bb_addr1                ;
wire         [31:0]                          bb_dout1                ;    

c0_system mprj (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .clk_g(wb_clk_i),
    .rst_g(wb_rst_i),


    .tx(io_out[1]),
    .rx(io_in[0]),
    .io_gecerli(io_out[2]),
    .io_ps(io_out[34:3]),
    .io_oeb(io_oeb),


    .bb_csb0                                           (bb_csb0)                                                       ,
    .bb_web0                                           (bb_web0)                                                       ,
    .bb_wmask0                                         (bb_wmask0)                                                     ,
    .bb_addr0                                          (bb_addr0)                                                      ,
    .bb_din0                                           (bb_din0)                                                       ,
    .bb_dout0                                          (bb_dout0)                                                      ,

    .bb_csb1                                           (bb_csb1)                                                       ,
    .bb_addr1                                          (bb_addr1)                                                      ,
    .bb_dout1                                          (bb_dout1)                                                      ,

    .vb_csb0                                           (vb_csb0)                                                       ,
    .vb_web0                                           (vb_web0)                                                       ,
    .vb_wmask0                                         (vb_wmask0)                                                     ,
    .vb_addr0                                          (vb_addr0)                                                      ,
    .vb_din0                                           (vb_din0)                                                       ,
    .vb_dout0                                          (vb_dout0)                                                      ,

    .vb_csb1                                           (vb_csb1)                                                       ,
    .vb_addr1                                          (vb_addr1)                                                      ,
    .vb_dout1                                          (vb_dout1) 
);

sky130_sram_2kbyte_1rw1r_32x512_8 VB_SRAM
(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif        

    .clk0               (wb_clk_i)        ,
    .csb0               (vb_csb0)        ,
    .web0               (vb_web0)        ,
    .wmask0             (vb_wmask0)      ,
    .addr0              (vb_addr0)       ,
    .din0               (vb_din0)        ,
    .dout0              (vb_dout0)       ,
    .clk1               (wb_clk_i)        ,
    .csb1               (vb_csb1)        ,
    .addr1              (vb_addr1)       ,
    .dout1              (vb_dout1)     
);

sky130_sram_2kbyte_1rw1r_32x512_8 BB_SRAM
(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif        

    .clk0               (wb_clk_i)      ,
    .csb0               (bb_csb0)      ,
    .web0               (bb_web0)      ,
    .wmask0             (bb_wmask0)    ,
    .addr0              (bb_addr0)     ,
    .din0               (bb_din0)      ,
    .dout0              (bb_dout0)     ,
    .clk1               (wb_clk_i)      ,
    .csb1               (bb_csb1)      ,
    .addr1              (bb_addr1)     ,
    .dout1              (bb_dout1)   
);
endmodule