data/full_repos/permissive/412284801/nand/nand_rtl_tb.v
1: b'%Error: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:1: Cannot find include file: nand_rtl.v\n`include "nand_rtl.v"\n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412284801/nand,data/full_repos/permissive/412284801/nand_rtl.v\n             data/full_repos/permissive/412284801/nand,data/full_repos/permissive/412284801/nand_rtl.v.v\n             data/full_repos/permissive/412284801/nand,data/full_repos/permissive/412284801/nand_rtl.v.sv\n             nand_rtl.v\n             nand_rtl.v.v\n             nand_rtl.v.sv\n             obj_dir/nand_rtl.v\n             obj_dir/nand_rtl.v.v\n             obj_dir/nand_rtl.v.sv\n%Error: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("nand_rtl.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, nand_rtl_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #30 $finish;    \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    always #10 a=~a;    \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    always #20 b=~b;\n           ^\n%Error: data/full_repos/permissive/412284801/nand/nand_rtl_tb.v:22: Unsupported or unknown PLI call: $monitor\n        $monitor("time = %0t, a = %b, b = %b, o = %b", $time, a, b, o);\n        ^~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module nand_rtl_tb();

    reg a, b;
    wire o, d;

    nand_rtl uut(.a(a), .b(b), .o(o));

    initial begin
        $dumpfile("nand_rtl.vcd");
        $dumpvars(0, nand_rtl_tb);
        a = 1'b0;       
        b = 1'b0;

        #30 $finish;    
    end
    
    always #10 a=~a;    
    always #20 b=~b;
    initial begin
        $monitor("time = %0t, a = %b, b = %b, o = %b", $time, a, b, o);
    end

endmodule
module nand_rtl_tb();


    reg a, b;
    wire o, d;

    nand_rtl uut(.a(a), .b(b), .o(o));

    initial begin
        $dumpfile("nand_rtl.vcd");
        $dumpvars(0, nand_rtl_tb);
        a = 1'b0;       
        b = 1'b0;

        #30 $finish;    
    end
    
    always #10 a=~a;    
    always #20 b=~b;
    initial begin
        $monitor("time = %0t, a = %b, b = %b, o = %b", $time, a, b, o);
    end

endmodule