data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_delay_k_clk.v
data/verilator_xmls/97fbcf66-a9b5-4056-907d-1aea73ae632e.xml
module ipsmacge_delay_k_clk
    (
     clk,
     rst_,
     idat,
     odat
     );



parameter K = 3;



input              clk,
                   rst_;
input              idat;
output             odat;
  


wire               odat;



reg [K-1:0] shift_dat;

always @ (posedge clk or negedge rst_)
    begin
    if(!rst_)    
        shift_dat <= {K{1'b0}};
    else        
        shift_dat <= {shift_dat[K-2:0],idat};
    end
assign odat = shift_dat[K-1];

endmodule
module ipsmacge_delay_k_clk
    (
     clk,
     rst_,
     idat,
     odat
     );




parameter K = 3;



input              clk,
                   rst_;
input              idat;
output             odat;
  


wire               odat;



reg [K-1:0] shift_dat;

always @ (posedge clk or negedge rst_)
    begin
    if(!rst_)    
        shift_dat <= {K{1'b0}};
    else        
        shift_dat <= {shift_dat[K-2:0],idat};
    end
assign odat = shift_dat[K-1];

endmodule