data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/axi_sd_fifo.v
data/verilator_xmls/64816f96-2f6c-453d-8dc4-4bbeb29fd9a7.xml
module axi_sd_fifo #(parameter addr_bits = 4) (
    input clk,
    input rst,
    input re,
    input we,
    input [31:0] din,
    output reg [31:0] dout,
    output [addr_bits-1:0] data_len,
    output [addr_bits-1:0] free_len,
    output full,
    output empty);

reg  [31:0] mem [(1<<addr_bits)-1:0];
reg  [addr_bits-1:0] inp_pos;
reg  [addr_bits-1:0] out_pos;
wire [addr_bits-1:0] inp_nxt;
wire [addr_bits-1:0] out_nxt;

assign full = inp_nxt == out_pos;
assign empty = inp_pos == out_pos;
assign inp_nxt = inp_pos + 1;
assign out_nxt = out_pos + 1;
assign data_len = inp_pos - out_pos;
assign free_len = out_pos - inp_nxt;

always @(posedge clk)
    if (rst) begin
        inp_pos <= 0;
        out_pos <= 0;
    end else begin
        if (we && !full) begin
            mem[inp_pos] <= din;
            inp_pos <= inp_nxt;
            if (empty) dout <= din;
        end
        if (re && !empty) begin
            if (we && !full && out_nxt == inp_pos) dout <= din;
            else dout <= mem[out_nxt];
            out_pos <= out_nxt;
        end
    end

endmodule
module axi_sd_fifo #(parameter addr_bits = 4) (
    input clk,
    input rst,
    input re,
    input we,
    input [31:0] din,
    output reg [31:0] dout,
    output [addr_bits-1:0] data_len,
    output [addr_bits-1:0] free_len,
    output full,
    output empty);


reg  [31:0] mem [(1<<addr_bits)-1:0];
reg  [addr_bits-1:0] inp_pos;
reg  [addr_bits-1:0] out_pos;
wire [addr_bits-1:0] inp_nxt;
wire [addr_bits-1:0] out_nxt;

assign full = inp_nxt == out_pos;
assign empty = inp_pos == out_pos;
assign inp_nxt = inp_pos + 1;
assign out_nxt = out_pos + 1;
assign data_len = inp_pos - out_pos;
assign free_len = out_pos - inp_nxt;

always @(posedge clk)
    if (rst) begin
        inp_pos <= 0;
        out_pos <= 0;
    end else begin
        if (we && !full) begin
            mem[inp_pos] <= din;
            inp_pos <= inp_nxt;
            if (empty) dout <= din;
        end
        if (re && !empty) begin
            if (we && !full && out_nxt == inp_pos) dout <= din;
            else dout <= mem[out_nxt];
            out_pos <= out_nxt;
        end
    end

endmodule