data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_exponent_addition.v
data/verilator_xmls/7c4e7b84-f1d8-4c3d-80b2-a4580f2a09a4.xml
module FMADD_Exponent_addition (Exponent_addition_input_A,Exponent_addition_input_B,Exponent_addition_input_Activation_Signal,Exponent_addition_output_exp,Exponent_addition_output_sign,output_underflow_check);
parameter std=31;
parameter man =22;
parameter exp = 7;


input [exp+1:0] Exponent_addition_input_A,Exponent_addition_input_B;
input Exponent_addition_input_Activation_Signal;


output  [exp+1:0] Exponent_addition_output_exp;
output Exponent_addition_output_sign;
output output_underflow_check;
wire [exp+1:0] Exponent_addition_wire_exp;


assign Exponent_addition_wire_exp = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A[exp:0] + Exponent_addition_input_B[exp:0]): {(exp+2){1'b0}};
assign output_underflow_check  = Exponent_addition_wire_exp < 103;
assign Exponent_addition_output_exp = Exponent_addition_wire_exp;
assign Exponent_addition_output_sign = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A [exp+1] ^ Exponent_addition_input_B[exp+1]) : 1'b0;


endmodule
module FMADD_Exponent_addition (Exponent_addition_input_A,Exponent_addition_input_B,Exponent_addition_input_Activation_Signal,Exponent_addition_output_exp,Exponent_addition_output_sign,output_underflow_check);

parameter std=31;
parameter man =22;
parameter exp = 7;


input [exp+1:0] Exponent_addition_input_A,Exponent_addition_input_B;
input Exponent_addition_input_Activation_Signal;


output  [exp+1:0] Exponent_addition_output_exp;
output Exponent_addition_output_sign;
output output_underflow_check;
wire [exp+1:0] Exponent_addition_wire_exp;


assign Exponent_addition_wire_exp = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A[exp:0] + Exponent_addition_input_B[exp:0]): {(exp+2){1'b0}};
assign output_underflow_check  = Exponent_addition_wire_exp < 103;
assign Exponent_addition_output_exp = Exponent_addition_wire_exp;
assign Exponent_addition_output_sign = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A [exp+1] ^ Exponent_addition_input_B[exp+1]) : 1'b0;


endmodule