data/full_repos/permissive/449082818/fifo version/fifo_oscillo.v
1: b'%Error: Cannot find file containing module: version,data/full_repos/permissive/449082818\n        ... Looked in:\n             data/full_repos/permissive/449082818/fifo/version,data/full_repos/permissive/449082818\n             data/full_repos/permissive/449082818/fifo/version,data/full_repos/permissive/449082818.v\n             data/full_repos/permissive/449082818/fifo/version,data/full_repos/permissive/449082818.sv\n             version,data/full_repos/permissive/449082818\n             version,data/full_repos/permissive/449082818.v\n             version,data/full_repos/permissive/449082818.sv\n             obj_dir/version,data/full_repos/permissive/449082818\n             obj_dir/version,data/full_repos/permissive/449082818.v\n             obj_dir/version,data/full_repos/permissive/449082818.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/449082818/fifo\n%Error: Cannot find file containing module: version/fifo_oscillo.v\n%Error: Exiting due to 3 error(s)\n'
module oscillo(clk, TxD, clk_flash, data_flash);
input clk;
output TxD;

input clk_flash;
input [7:0] data_flash;

reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;

wire [7:0] q_fifo;
fifo myfifo(.data(data_flash_reg), .wrreq(wrreq), .wrclk(clk_flash), .wrfull(wrfull), .wrempty(wrempty), .q(q_fifo), .rdreq(rdreq), .rdclk(clk), .rdempty(rdempty));



reg fillfifo;
always @(posedge clk_flash)
if(~fillfifo)
  fillfifo <= wrempty;
else
  fillfifo <= ~wrfull;

assign wrreq = fillfifo;


wire TxD_busy;
wire TxD_start = ~TxD_busy & ~rdempty;
assign rdreq = TxD_start;

async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(q_fifo));

endmodule
module oscillo(clk, TxD, clk_flash, data_flash);

input clk;
output TxD;

input clk_flash;
input [7:0] data_flash;

reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;

wire [7:0] q_fifo;
fifo myfifo(.data(data_flash_reg), .wrreq(wrreq), .wrclk(clk_flash), .wrfull(wrfull), .wrempty(wrempty), .q(q_fifo), .rdreq(rdreq), .rdclk(clk), .rdempty(rdempty));



reg fillfifo;
always @(posedge clk_flash)
if(~fillfifo)
  fillfifo <= wrempty;
else
  fillfifo <= ~wrfull;

assign wrreq = fillfifo;


wire TxD_busy;
wire TxD_start = ~TxD_busy & ~rdempty;
assign rdreq = TxD_start;

async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(q_fifo));

endmodule