data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:38: Define or directive not defined: '`LUT_SIZE'\ngenerate if (`LUT_SIZE == 4) begin\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:38: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\ngenerate if (`LUT_SIZE == 4) begin\n                       ^~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:45: syntax error, unexpected generate\n generate for (i = 0; i < WIDTH; i = i + 1) begin:slice\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:68: syntax error, unexpected generate\n generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:108: syntax error, unexpected input\n input [A_WIDTH-1:0] A;\n ^~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:132: syntax error, unexpected generate\ngenerate if (`LUT_SIZE == 4) begin\n^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:132: Define or directive not defined: '`LUT_SIZE'\ngenerate if (`LUT_SIZE == 4) begin\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:140: syntax error, unexpected generate\n generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:152: syntax error, unexpected end\n end endgenerate\n ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/arith_map.v:172: syntax error, unexpected generate\n generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n ^~~~~~~~\n%Error: Cannot continue\n"
module _80_xilinx_lcu (P, G, CI, CO);
	parameter WIDTH = 2;

	(* force_downto *)
	input [WIDTH-1:0] P, G;
	input CI;

	(* force_downto *)
	output [WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = WIDTH <= 2;

	genvar i;

generate if (`LUT_SIZE == 4) begin

	(* force_downto *)
	wire [WIDTH-1:0] C = {CO, CI};
	(* force_downto *)
	wire [WIDTH-1:0] S = P & ~G;

	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
		MUXCY muxcy (
			.CI(C[i]),
			.DI(G[i]),
			.S(S[i]),
			.O(CO[i])
		);
	end endgenerate

end else begin

	localparam CARRY4_COUNT = (WIDTH + 3) / 4;
	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
	localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;

	(* force_downto *)
	wire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};
	(* force_downto *)
	wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
	(* force_downto *)
	wire [MAX_WIDTH-1:0] C;
	assign CO = C;

	generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
		if (i == 0) begin
			CARRY4 carry4
			(
			.CYINIT(CI),
			.CI    (1'd0),
			.DI    (GG[i*4 +: 4]),
			.S     (S [i*4 +: 4]),
			.CO    (C [i*4 +: 4]),
			);
		end else begin
			CARRY4 carry4
			(
			.CYINIT(1'd0),
			.CI    (C [i*4 - 1]),
			.DI    (GG[i*4 +: 4]),
			.S     (S [i*4 +: 4]),
			.CO    (C [i*4 +: 4]),
			);
		end
	end endgenerate
end endgenerate

endmodule
module _80_xilinx_lcu (P, G, CI, CO);

	parameter WIDTH = 2;

	(* force_downto *)
	input [WIDTH-1:0] P, G;
	input CI;

	(* force_downto *)
	output [WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = WIDTH <= 2;

	genvar i;

generate if (`LUT_SIZE == 4) begin

	(* force_downto *)
	wire [WIDTH-1:0] C = {CO, CI};
	(* force_downto *)
	wire [WIDTH-1:0] S = P & ~G;

	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
		MUXCY muxcy (
			.CI(C[i]),
			.DI(G[i]),
			.S(S[i]),
			.O(CO[i])
		);
	end endgenerate

end else begin

	localparam CARRY4_COUNT = (WIDTH + 3) / 4;
	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
	localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;

	(* force_downto *)
	wire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};
	(* force_downto *)
	wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
	(* force_downto *)
	wire [MAX_WIDTH-1:0] C;
	assign CO = C;

	generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
		if (i == 0) begin
			CARRY4 carry4
			(
			.CYINIT(CI),
			.CI    (1'd0),
			.DI    (GG[i*4 +: 4]),
			.S     (S [i*4 +: 4]),
			.CO    (C [i*4 +: 4]),
			);
		end else begin
			CARRY4 carry4
			(
			.CYINIT(1'd0),
			.CI    (C [i*4 - 1]),
			.DI    (GG[i*4 +: 4]),
			.S     (S [i*4 +: 4]),
			.CO    (C [i*4 +: 4]),
			);
		end
	end endgenerate
end endgenerate

endmodule