data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:18: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/backend,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/backend,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/backend,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:99: Define or directive not defined: \'`S4\'\n assign obuf_addr = ((line_state == `S4) | (line_state == `S1)) ? 3\'d0 : \n                                    ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:99: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign obuf_addr = ((line_state == `S4) | (line_state == `S1)) ? 3\'d0 : \n                                       ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:99: Define or directive not defined: \'`S1\'\n assign obuf_addr = ((line_state == `S4) | (line_state == `S1)) ? 3\'d0 : \n                                                          ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:100: Define or directive not defined: \'`S6\'\n        (line_state == `S6) ? 3\'d2 : \n                       ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:102: Define or directive not defined: \'`S3\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d1 : \n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:102: Define or directive not defined: \'`S5\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d1 : \n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:103: Define or directive not defined: \'`S0\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d4 : 3\'d3\n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:103: Define or directive not defined: \'`S2\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d4 : 3\'d3\n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:105: Define or directive not defined: \'`S3\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d4 : \n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:105: Define or directive not defined: \'`S5\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d4 : \n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:106: Define or directive not defined: \'`S0\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d3 : 3\'d1\n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:106: Define or directive not defined: \'`S2\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d3 : 3\'d1\n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:108: Define or directive not defined: \'`S0\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d1 : \n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:108: Define or directive not defined: \'`S2\'\n        ((line_state == `S0) | (line_state == `S2)) ? 3\'d1 : \n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:109: Define or directive not defined: \'`S3\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d3 : 3\'d4;\n                        ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:109: Define or directive not defined: \'`S5\'\n        ((line_state == `S3) | (line_state == `S5)) ? 3\'d3 : 3\'d4;\n                                              ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:115: Define or directive not defined: \'`S3\'\n   if (line_state == `S3) begin\n                     ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:115: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if (line_state == `S3) begin\n                        ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:120: Define or directive not defined: \'`LS_26\'\n   if (`LS_26 | `LS_04) begin\n       ^~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:120: Define or directive not defined: \'`LS_04\'\n   if (`LS_26 | `LS_04) begin\n                ^~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:120: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if (`LS_26 | `LS_04) begin\n                      ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:123: syntax error, unexpected else\n   end else begin\n       ^~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:130: Define or directive not defined: \'`S0\'\n assign cr_out = ((line_state == `S0) | (line_state == `S2)) ? output_reorderb :\n                                 ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:130: Define or directive not defined: \'`S2\'\n assign cr_out = ((line_state == `S0) | (line_state == `S2)) ? output_reorderb :\n                                                       ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:131: Define or directive not defined: \'`S1\'\n       ((line_state == `S1) | (line_state == `S7)) ? obuf_dataout[15:8]\n                       ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:131: Define or directive not defined: \'`S7\'\n       ((line_state == `S1) | (line_state == `S7)) ? obuf_dataout[15:8]\n                                             ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:133: Define or directive not defined: \'`S4\'\n assign cb_out = ((line_state == `S4) | (line_state == `S6)) ? output_reorderb : \n                                 ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:133: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign cb_out = ((line_state == `S4) | (line_state == `S6)) ? output_reorderb : \n                                    ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:133: Define or directive not defined: \'`S6\'\n assign cb_out = ((line_state == `S4) | (line_state == `S6)) ? output_reorderb : \n                                                       ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:134: Define or directive not defined: \'`S3\'\n       ((line_state == `S3) | (line_state == `S5)) ? obuf_dataout[15:8]\n                       ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/backend/buffer_interface.v:134: Define or directive not defined: \'`S5\'\n       ((line_state == `S3) | (line_state == `S5)) ? obuf_dataout[15:8]\n                                             ^~~\n%Error: Exiting due to 32 error(s)\n'
module buffer_interface(clk, 
								resetn,
								line_state,

								vbuf_addr,
								vbuf_dataout,
								vbuf_we,

								ZBT_datain,
								
								ybuf_addr,
								ybuf_we,

								obuf_datain,
								hbuf_datain,
								hbuf_dataout,

								
								y_out,
								cr_out,
								cb_out
								);
								
	input 			clk;
	input				resetn;
	input [2:0]		line_state;
		

	input [10:0]	vbuf_addr;
	output [15:0]	vbuf_dataout;
	input				vbuf_we;
	
	input [31:0]	ZBT_datain;


	input [9:0]		ybuf_addr;
	input				ybuf_we;

	input [15:0]	obuf_datain;
	input [15:0]	hbuf_datain;
	output [15:0]	hbuf_dataout;

	output [7:0]	y_out;
	output [7:0]	cr_out;
	output [7:0]	cb_out;





	wire [31:0]		vbuf_dataouta;
	wire [31:0]		vbuf_dataoutb;
	reg				bank;
	reg				group;
	
	always @(posedge clk or negedge resetn) begin
		if (~resetn) begin
			bank <= 1'b0;
			group <= 1'b0;
		end else begin
			bank <= vbuf_addr[10];
			group <= vbuf_addr[0];
		end
	end
	
	assign vbuf_dataout = ({bank, group} == 2'b00) ? vbuf_dataouta[31:16] :
								 ({bank, group} == 2'b01) ? vbuf_dataouta[15:0] : 
								 ({bank, group} == 2'b10) ? vbuf_dataoutb[31:16] : 
vbuf_dataoutb[15:0];





	reg [7:0] output_reordera;
	reg [7:0] output_reorderb;
	reg [1:0] obuf_addr_mode;
	wire [15:0] obuf_dataout;
	
	wire [2:0] obuf_addr;
	assign obuf_addr = ((line_state == `S4) | (line_state == `S1)) ? 3'd0 : 
							 (line_state == `S6) ? 3'd2 : 
							 (obuf_addr_mode == 2'b00) ? 
								((line_state == `S3) | (line_state == `S5)) ? 3'd1 : 
								((line_state == `S0) | (line_state == `S2)) ? 3'd4 : 3'd3
						  : (obuf_addr_mode == 2'b01) ? 
								((line_state == `S3) | (line_state == `S5)) ? 3'd4 : 
								((line_state == `S0) | (line_state == `S2)) ? 3'd3 : 3'd1
						  :
								((line_state == `S0) | (line_state == `S2)) ? 3'd1 : 
								((line_state == `S3) | (line_state == `S5)) ? 3'd3 : 3'd4;
	
	always @(posedge clk or negedge resetn) begin
		if (~resetn) begin
			obuf_addr_mode <= 2'd0;
		end else begin
			if (line_state == `S3) begin
				if (obuf_addr_mode == 2'b10) obuf_addr_mode <= 2'b00;
				else obuf_addr_mode <= obuf_addr_mode + 1;
			end
			
			if (`LS_26 | `LS_04) begin
				output_reordera <= obuf_dataout[15:8];
				output_reorderb <= obuf_dataout[7:0];
			end else begin
				output_reordera <= output_reorderb;
				output_reorderb <= obuf_dataout[7:0];
			end
		end
	end
	
	assign cr_out = ((line_state == `S0) | (line_state == `S2)) ? output_reorderb :
						 ((line_state == `S1) | (line_state == `S7)) ? obuf_dataout[15:8]
						 : output_reordera;
	assign cb_out = ((line_state == `S4) | (line_state == `S6)) ? output_reorderb : 
						 ((line_state == `S3) | (line_state == `S5)) ? obuf_dataout[15:8]
						 : output_reordera;
	



	
	RAMB16_S9_S36 a_buffer (

		.DOA		(y_out),
		.ADDRA	({1'b0,ybuf_addr[9:2],2'b11 - ybuf_addr[1:0]}),
		.CLKA		(clk),
		.DIA		(8'h00),
		.ENA		(resetn),
		.WEA		(1'b0),
		.SSRA		(1'b0),
		.DIPA		(1'b0),


		.DOB		(vbuf_dataouta),
		.ADDRB	(vbuf_addr[9:1]),
		.CLKB		(clk),
		.DIB		(ZBT_datain),
		.ENB		(resetn),
		.WEB		((vbuf_we & ~vbuf_addr[10]) | ybuf_we),
		.SSRB		(1'b0),
		.DIPB		(4'h0)
	);



	

	defparam a_buffer.WRITE_MODE_A = "READ_FIRST";
	defparam a_buffer.WRITE_MODE_B = "READ_FIRST";

	




	RAMB16_S36_S36 b_buffer (

		.DOA		(vbuf_dataoutb),
		.ADDRA	(vbuf_addr[9:1]),
		.CLKA		(clk),
		.DIA		(ZBT_datain),
		.ENA		(resetn),
		.WEA		(vbuf_we & vbuf_addr[10]),
		.SSRA		(1'b0),
		.DIPA		(4'h0),
		

		.DOB		({obuf_dataout,hbuf_dataout}),
		.ADDRB	({6'h3f,obuf_addr}),
		.CLKB		(clk),
		.DIB		({obuf_datain,hbuf_datain}),
		.ENB		(resetn),
		.WEB		(1'b1),
		.SSRB		(1'b0),
		.DIPB		(4'h0)
	);
	


	

	defparam b_buffer.WRITE_MODE_A = "READ_FIRST";
	defparam b_buffer.WRITE_MODE_B = "READ_FIRST";

endmodule
module buffer_interface(clk, 
								resetn,
								line_state,

								vbuf_addr,
								vbuf_dataout,
								vbuf_we,

								ZBT_datain,
								
								ybuf_addr,
								ybuf_we,

								obuf_datain,
								hbuf_datain,
								hbuf_dataout,

								
								y_out,
								cr_out,
								cb_out
								);

								
	input 			clk;
	input				resetn;
	input [2:0]		line_state;
		

	input [10:0]	vbuf_addr;
	output [15:0]	vbuf_dataout;
	input				vbuf_we;
	
	input [31:0]	ZBT_datain;


	input [9:0]		ybuf_addr;
	input				ybuf_we;

	input [15:0]	obuf_datain;
	input [15:0]	hbuf_datain;
	output [15:0]	hbuf_dataout;

	output [7:0]	y_out;
	output [7:0]	cr_out;
	output [7:0]	cb_out;





	wire [31:0]		vbuf_dataouta;
	wire [31:0]		vbuf_dataoutb;
	reg				bank;
	reg				group;
	
	always @(posedge clk or negedge resetn) begin
		if (~resetn) begin
			bank <= 1'b0;
			group <= 1'b0;
		end else begin
			bank <= vbuf_addr[10];
			group <= vbuf_addr[0];
		end
	end
	
	assign vbuf_dataout = ({bank, group} == 2'b00) ? vbuf_dataouta[31:16] :
								 ({bank, group} == 2'b01) ? vbuf_dataouta[15:0] : 
								 ({bank, group} == 2'b10) ? vbuf_dataoutb[31:16] : 
vbuf_dataoutb[15:0];





	reg [7:0] output_reordera;
	reg [7:0] output_reorderb;
	reg [1:0] obuf_addr_mode;
	wire [15:0] obuf_dataout;
	
	wire [2:0] obuf_addr;
	assign obuf_addr = ((line_state == `S4) | (line_state == `S1)) ? 3'd0 : 
							 (line_state == `S6) ? 3'd2 : 
							 (obuf_addr_mode == 2'b00) ? 
								((line_state == `S3) | (line_state == `S5)) ? 3'd1 : 
								((line_state == `S0) | (line_state == `S2)) ? 3'd4 : 3'd3
						  : (obuf_addr_mode == 2'b01) ? 
								((line_state == `S3) | (line_state == `S5)) ? 3'd4 : 
								((line_state == `S0) | (line_state == `S2)) ? 3'd3 : 3'd1
						  :
								((line_state == `S0) | (line_state == `S2)) ? 3'd1 : 
								((line_state == `S3) | (line_state == `S5)) ? 3'd3 : 3'd4;
	
	always @(posedge clk or negedge resetn) begin
		if (~resetn) begin
			obuf_addr_mode <= 2'd0;
		end else begin
			if (line_state == `S3) begin
				if (obuf_addr_mode == 2'b10) obuf_addr_mode <= 2'b00;
				else obuf_addr_mode <= obuf_addr_mode + 1;
			end
			
			if (`LS_26 | `LS_04) begin
				output_reordera <= obuf_dataout[15:8];
				output_reorderb <= obuf_dataout[7:0];
			end else begin
				output_reordera <= output_reorderb;
				output_reorderb <= obuf_dataout[7:0];
			end
		end
	end
	
	assign cr_out = ((line_state == `S0) | (line_state == `S2)) ? output_reorderb :
						 ((line_state == `S1) | (line_state == `S7)) ? obuf_dataout[15:8]
						 : output_reordera;
	assign cb_out = ((line_state == `S4) | (line_state == `S6)) ? output_reorderb : 
						 ((line_state == `S3) | (line_state == `S5)) ? obuf_dataout[15:8]
						 : output_reordera;
	



	
	RAMB16_S9_S36 a_buffer (

		.DOA		(y_out),
		.ADDRA	({1'b0,ybuf_addr[9:2],2'b11 - ybuf_addr[1:0]}),
		.CLKA		(clk),
		.DIA		(8'h00),
		.ENA		(resetn),
		.WEA		(1'b0),
		.SSRA		(1'b0),
		.DIPA		(1'b0),


		.DOB		(vbuf_dataouta),
		.ADDRB	(vbuf_addr[9:1]),
		.CLKB		(clk),
		.DIB		(ZBT_datain),
		.ENB		(resetn),
		.WEB		((vbuf_we & ~vbuf_addr[10]) | ybuf_we),
		.SSRB		(1'b0),
		.DIPB		(4'h0)
	);



	

	defparam a_buffer.WRITE_MODE_A = "READ_FIRST";
	defparam a_buffer.WRITE_MODE_B = "READ_FIRST";

	




	RAMB16_S36_S36 b_buffer (

		.DOA		(vbuf_dataoutb),
		.ADDRA	(vbuf_addr[9:1]),
		.CLKA		(clk),
		.DIA		(ZBT_datain),
		.ENA		(resetn),
		.WEA		(vbuf_we & vbuf_addr[10]),
		.SSRA		(1'b0),
		.DIPA		(4'h0),
		

		.DOB		({obuf_dataout,hbuf_dataout}),
		.ADDRB	({6'h3f,obuf_addr}),
		.CLKB		(clk),
		.DIB		({obuf_datain,hbuf_datain}),
		.ENB		(resetn),
		.WEB		(1'b1),
		.SSRB		(1'b0),
		.DIPB		(4'h0)
	);
	


	

	defparam b_buffer.WRITE_MODE_A = "READ_FIRST";
	defparam b_buffer.WRITE_MODE_B = "READ_FIRST";

endmodule