data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v
1: b'%Error: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:2: Cannot find include file: q4.v\n`include "q4.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528677531/LAB-3/Q4,data/full_repos/permissive/528677531/q4.v\n             data/full_repos/permissive/528677531/LAB-3/Q4,data/full_repos/permissive/528677531/q4.v.v\n             data/full_repos/permissive/528677531/LAB-3/Q4,data/full_repos/permissive/528677531/q4.v.sv\n             q4.v\n             q4.v.v\n             q4.v.sv\n             obj_dir/q4.v\n             obj_dir/q4.v.v\n             obj_dir/q4.v.sv\n%Error: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("q4_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,q4_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b0; C=1\'b0; D=1\'b0; #20;\n                                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b0; C=1\'b0; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b0; C=1\'b1; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b0; C=1\'b1; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b1; C=1\'b0; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b1; C=1\'b0; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b1; C=1\'b1; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b0; B=1\'b1; C=1\'b1; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b0; C=1\'b0; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b0; C=1\'b0; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b0; C=1\'b1; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b0; C=1\'b1; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b1; C=1\'b0; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b1; C=1\'b0; D=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b1; C=1\'b1; D=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q4/q4_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\nA=1\'b1; B=1\'b1; C=1\'b1; D=1\'b1; #20;\n                                ^\n%Error: Exiting due to 3 error(s), 16 warning(s)\n'
module q4_tb();
reg A,B,C,D;
wire f;
q4 q4(A,B,C,D,f);
initial
begin
$dumpfile("q4_tb.vcd");
$dumpvars(0,q4_tb);

A=1'b0; B=1'b0; C=1'b0; D=1'b0; #20;
A=1'b0; B=1'b0; C=1'b0; D=1'b1; #20;
A=1'b0; B=1'b0; C=1'b1; D=1'b0; #20;
A=1'b0; B=1'b0; C=1'b1; D=1'b1; #20;
A=1'b0; B=1'b1; C=1'b0; D=1'b0; #20;
A=1'b0; B=1'b1; C=1'b0; D=1'b1; #20;
A=1'b0; B=1'b1; C=1'b1; D=1'b0; #20;
A=1'b0; B=1'b1; C=1'b1; D=1'b1; #20;
A=1'b1; B=1'b0; C=1'b0; D=1'b0; #20;
A=1'b1; B=1'b0; C=1'b0; D=1'b1; #20;
A=1'b1; B=1'b0; C=1'b1; D=1'b0; #20;
A=1'b1; B=1'b0; C=1'b1; D=1'b1; #20;
A=1'b1; B=1'b1; C=1'b0; D=1'b0; #20;
A=1'b1; B=1'b1; C=1'b0; D=1'b1; #20;
A=1'b1; B=1'b1; C=1'b1; D=1'b0; #20;
A=1'b1; B=1'b1; C=1'b1; D=1'b1; #20;

$display("Test Complete");
end
endmodule
module q4_tb();

reg A,B,C,D;
wire f;
q4 q4(A,B,C,D,f);
initial
begin
$dumpfile("q4_tb.vcd");
$dumpvars(0,q4_tb);

A=1'b0; B=1'b0; C=1'b0; D=1'b0; #20;
A=1'b0; B=1'b0; C=1'b0; D=1'b1; #20;
A=1'b0; B=1'b0; C=1'b1; D=1'b0; #20;
A=1'b0; B=1'b0; C=1'b1; D=1'b1; #20;
A=1'b0; B=1'b1; C=1'b0; D=1'b0; #20;
A=1'b0; B=1'b1; C=1'b0; D=1'b1; #20;
A=1'b0; B=1'b1; C=1'b1; D=1'b0; #20;
A=1'b0; B=1'b1; C=1'b1; D=1'b1; #20;
A=1'b1; B=1'b0; C=1'b0; D=1'b0; #20;
A=1'b1; B=1'b0; C=1'b0; D=1'b1; #20;
A=1'b1; B=1'b0; C=1'b1; D=1'b0; #20;
A=1'b1; B=1'b0; C=1'b1; D=1'b1; #20;
A=1'b1; B=1'b1; C=1'b0; D=1'b0; #20;
A=1'b1; B=1'b1; C=1'b0; D=1'b1; #20;
A=1'b1; B=1'b1; C=1'b1; D=1'b0; #20;
A=1'b1; B=1'b1; C=1'b1; D=1'b1; #20;

$display("Test Complete");
end
endmodule