data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:9: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:14: Define or directive not defined: \'`PC_SIZE\'\n  input  [`PC_SIZE-1:0] pc,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:20: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] dec_bjp_imm,  \n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:21: Define or directive not defined: \'`RFIDX_WIDTH\'\n  input  [`RFIDX_WIDTH-1:0] dec_jalr_rs1idx,\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:32: Define or directive not defined: \'`PC_SIZE\'\n  output [`PC_SIZE-1:0] prdt_pc_add_op1,  \n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:33: Define or directive not defined: \'`PC_SIZE\'\n  output [`PC_SIZE-1:0] prdt_pc_add_op2,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:39: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] rf2bpu_x1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:40: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] rf2bpu_rs1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:74: Define or directive not defined: \'`XLEN\'\n  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`XLEN-1]));  \n                                                                     ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:77: Define or directive not defined: \'`RFIDX_WIDTH\'\n  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `RFIDX_WIDTH\'d0);     \n                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:78: Define or directive not defined: \'`RFIDX_WIDTH\'\n  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `RFIDX_WIDTH\'d1);     \n                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:117: Define or directive not defined: \'`PC_SIZE\'\n  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`PC_SIZE-1:0]                        \n                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:118: Define or directive not defined: \'`PC_SIZE\'\n                         : (dec_jalr & dec_jalr_rs1x0) ? `PC_SIZE\'b0                     \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:119: Define or directive not defined: \'`PC_SIZE\'\n                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`PC_SIZE-1:0]         \n                                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:120: Define or directive not defined: \'`PC_SIZE\'\n                         : rf2bpu_rs1[`PC_SIZE-1:0];                                     \n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_bpu.v:123: Define or directive not defined: \'`PC_SIZE\'\n  assign prdt_pc_add_op2 = dec_bjp_imm[`PC_SIZE-1:0];  \n                                       ^~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module ifu_bpu(


  input  [`PC_SIZE-1:0] pc,


  input  dec_jal,  
  input  dec_jalr,
  input  dec_bxx,
  input  [`XLEN-1:0] dec_bjp_imm,
  input  [`RFIDX_WIDTH-1:0] dec_jalr_rs1idx,



  input  oitf_empty,
  input  ir_rs1en,
  input  jalr_rs1idx_match_irrdidx,
  

  output bpu_wait,  
  output prdt_taken,
  output [`PC_SIZE-1:0] prdt_pc_add_op1,  
  output [`PC_SIZE-1:0] prdt_pc_add_op2,

  input  dec_i_valid,


  input  ir_nop_instr,
  input  [`XLEN-1:0] rf2bpu_x1,
  input  [`XLEN-1:0] rf2bpu_rs1,

  input  clk,
  input  rst_n
);


  



  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`XLEN-1]));  


  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `RFIDX_WIDTH'd0);
  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `RFIDX_WIDTH'd1);
  wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);



  wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_match_irrdidx));
  wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_nop_instr));


  assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep;


  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`PC_SIZE-1:0]
                         : (dec_jalr & dec_jalr_rs1x0) ? `PC_SIZE'b0
                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`PC_SIZE-1:0]
                         : rf2bpu_rs1[`PC_SIZE-1:0];
 

  assign prdt_pc_add_op2 = dec_bjp_imm[`PC_SIZE-1:0];  

endmodule
module ifu_bpu(


  input  [`PC_SIZE-1:0] pc,


  input  dec_jal,  
  input  dec_jalr,
  input  dec_bxx,
  input  [`XLEN-1:0] dec_bjp_imm,
  input  [`RFIDX_WIDTH-1:0] dec_jalr_rs1idx,



  input  oitf_empty,
  input  ir_rs1en,
  input  jalr_rs1idx_match_irrdidx,
  

  output bpu_wait,  
  output prdt_taken,
  output [`PC_SIZE-1:0] prdt_pc_add_op1,  
  output [`PC_SIZE-1:0] prdt_pc_add_op2,

  input  dec_i_valid,


  input  ir_nop_instr,
  input  [`XLEN-1:0] rf2bpu_x1,
  input  [`XLEN-1:0] rf2bpu_rs1,

  input  clk,
  input  rst_n
);



  



  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`XLEN-1]));  


  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `RFIDX_WIDTH'd0);
  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `RFIDX_WIDTH'd1);
  wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);



  wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_match_irrdidx));
  wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_nop_instr));


  assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep;


  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`PC_SIZE-1:0]
                         : (dec_jalr & dec_jalr_rs1x0) ? `PC_SIZE'b0
                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`PC_SIZE-1:0]
                         : rf2bpu_rs1[`PC_SIZE-1:0];
 

  assign prdt_pc_add_op2 = dec_bjp_imm[`PC_SIZE-1:0];  

endmodule