data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:9: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:11: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:82: Define or directive not defined: \'`x_or_0\'\n            ig2cq_count <= {5{`x_or_0}};\n                              ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:82: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            ig2cq_count <= {5{`x_or_0}};\n                                     ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:130: Define or directive not defined: \'`x_or_0\'\n            cq2eg_adr <= {4{`x_or_0}};\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:130: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            cq2eg_adr <= {4{`x_or_0}};\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:177: Define or directive not defined: \'`x_or_0\'\n            cq2eg_count_p <= {5{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:177: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            cq2eg_count_p <= {5{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:186: Define or directive not defined: \'`x_or_0\'\n            cq2eg_pvld_p <= `x_or_0;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:186: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            cq2eg_pvld_p <= `x_or_0;\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:207: Define or directive not defined: \'`x_or_0\'\n        cq2eg_pd <= {18{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:207: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        cq2eg_pd <= {18{`x_or_0}};\n                               ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:511: Define or directive not defined: \'`x_or_0\'\n    default: dout = {18{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:511: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {18{`x_or_0}};\n                               ^\n%Error: Exiting due to 14 error(s)\n'
module NV_NVDLA_PDP_RDMA_cq (
      nvdla_core_clk
    , nvdla_core_rstn
    , ig2cq_prdy
    , ig2cq_pvld
    , ig2cq_pd
    , cq2eg_prdy
    , cq2eg_pvld
    , cq2eg_pd
    , pwrbus_ram_pd
    );

input nvdla_core_clk;
input nvdla_core_rstn;
output ig2cq_prdy;
input ig2cq_pvld;
input [17:0] ig2cq_pd;
input cq2eg_prdy;
output cq2eg_pvld;
output [17:0] cq2eg_pd;
input [31:0] pwrbus_ram_pd;











wire nvdla_core_clk_mgated_enable;
wire nvdla_core_clk_mgated;
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );



wire wr_reserving;
reg ig2cq_busy_int;
assign ig2cq_prdy = !ig2cq_busy_int;
assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int;
reg wr_popping;
reg [4:0] ig2cq_count;
wire [4:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1);
wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count;
wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_16 = ( wr_count_next_no_wr_popping == 5'd16 );
wire wr_count_next_is_16 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_16;
wire [4:0] wr_limit_muxed;
wire [4:0] wr_limit_reg = wr_limit_muxed;

wire ig2cq_busy_next = wr_count_next_is_16 ||
                          (wr_limit_reg != 5'd0 &&
                           wr_count_next >= wr_limit_reg) ;

always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        ig2cq_busy_int <= 1'b0;
        ig2cq_count <= 5'd0;
    end else begin
 ig2cq_busy_int <= ig2cq_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     ig2cq_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            ig2cq_count <= {5{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [3:0] ig2cq_adr;

always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        ig2cq_adr <= 4'd0;
    end else begin
        if ( wr_pushing ) begin
     ig2cq_adr <= ig2cq_adr + 1'd1;
        end
    end
end

reg [3:0] cq2eg_adr;
wire ram_we = wr_pushing;
wire [17:0] cq2eg_pd_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ram (
      .clk( nvdla_core_clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( ig2cq_pd )
    , .we ( ram_we )
    , .wa ( ig2cq_adr )
    , .ra ( cq2eg_adr )
    , .dout ( cq2eg_pd_p )
    );
wire rd_popping;
wire [3:0] rd_adr_next_popping = cq2eg_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_adr <= 4'd0;
    end else begin
        if ( rd_popping ) begin
     cq2eg_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            cq2eg_adr <= {4{`x_or_0}};
        end

    end
end



always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        wr_popping <= 1'b0;
    end else begin
 wr_popping <= rd_popping;
    end
end
wire rd_pushing = wr_pushing;



reg cq2eg_pvld_p;
reg cq2eg_pvld_int;
assign cq2eg_pvld = cq2eg_pvld_int;
assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy);
reg [4:0] cq2eg_count_p;

wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p :
                                                                (cq2eg_count_p - 1'd1);
wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) :
                                                                    cq2eg_count_p;

wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
                                              rd_count_p_next_no_rd_popping_not_0;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_count_p <= 5'd0;
        cq2eg_pvld_p <= 1'b0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     cq2eg_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            cq2eg_count_p <= {5{`x_or_0}};
        end

        if ( rd_pushing || rd_popping ) begin
     cq2eg_pvld_p <= (rd_count_p_next_not_0);
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            cq2eg_pvld_p <= `x_or_0;
        end

    end
end
reg [17:0] cq2eg_pd;
wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_pvld_int <= 1'b0;
    end else begin
        cq2eg_pvld_int <= rd_req_next;
    end
end
always @( posedge nvdla_core_clk_mgated ) begin
    if ( (rd_popping) ) begin
        cq2eg_pd <= cq2eg_pd_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        cq2eg_pd <= {18{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit : 5'd0;
`else


assign wr_limit_muxed = 5'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 5'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 5'd0;
`else


reg wr_limit_override;
reg [4:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( nvdla_core_clk )
    , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd16 : wr_limit_reg} )
    , .curr ( {27'd0, ig2cq_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule
module NV_NVDLA_PDP_RDMA_cq (
      nvdla_core_clk
    , nvdla_core_rstn
    , ig2cq_prdy
    , ig2cq_pvld
    , ig2cq_pd
    , cq2eg_prdy
    , cq2eg_pvld
    , cq2eg_pd
    , pwrbus_ram_pd
    );


input nvdla_core_clk;
input nvdla_core_rstn;
output ig2cq_prdy;
input ig2cq_pvld;
input [17:0] ig2cq_pd;
input cq2eg_prdy;
output cq2eg_pvld;
output [17:0] cq2eg_pd;
input [31:0] pwrbus_ram_pd;











wire nvdla_core_clk_mgated_enable;
wire nvdla_core_clk_mgated;
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );



wire wr_reserving;
reg ig2cq_busy_int;
assign ig2cq_prdy = !ig2cq_busy_int;
assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int;
reg wr_popping;
reg [4:0] ig2cq_count;
wire [4:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1);
wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count;
wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_16 = ( wr_count_next_no_wr_popping == 5'd16 );
wire wr_count_next_is_16 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_16;
wire [4:0] wr_limit_muxed;
wire [4:0] wr_limit_reg = wr_limit_muxed;

wire ig2cq_busy_next = wr_count_next_is_16 ||
                          (wr_limit_reg != 5'd0 &&
                           wr_count_next >= wr_limit_reg) ;

always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        ig2cq_busy_int <= 1'b0;
        ig2cq_count <= 5'd0;
    end else begin
 ig2cq_busy_int <= ig2cq_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     ig2cq_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            ig2cq_count <= {5{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [3:0] ig2cq_adr;

always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        ig2cq_adr <= 4'd0;
    end else begin
        if ( wr_pushing ) begin
     ig2cq_adr <= ig2cq_adr + 1'd1;
        end
    end
end

reg [3:0] cq2eg_adr;
wire ram_we = wr_pushing;
wire [17:0] cq2eg_pd_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ram (
      .clk( nvdla_core_clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( ig2cq_pd )
    , .we ( ram_we )
    , .wa ( ig2cq_adr )
    , .ra ( cq2eg_adr )
    , .dout ( cq2eg_pd_p )
    );
wire rd_popping;
wire [3:0] rd_adr_next_popping = cq2eg_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_adr <= 4'd0;
    end else begin
        if ( rd_popping ) begin
     cq2eg_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            cq2eg_adr <= {4{`x_or_0}};
        end

    end
end



always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        wr_popping <= 1'b0;
    end else begin
 wr_popping <= rd_popping;
    end
end
wire rd_pushing = wr_pushing;



reg cq2eg_pvld_p;
reg cq2eg_pvld_int;
assign cq2eg_pvld = cq2eg_pvld_int;
assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy);
reg [4:0] cq2eg_count_p;

wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p :
                                                                (cq2eg_count_p - 1'd1);
wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) :
                                                                    cq2eg_count_p;

wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0;
wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0;
wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 :
                                              rd_count_p_next_no_rd_popping_not_0;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_count_p <= 5'd0;
        cq2eg_pvld_p <= 1'b0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     cq2eg_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            cq2eg_count_p <= {5{`x_or_0}};
        end

        if ( rd_pushing || rd_popping ) begin
     cq2eg_pvld_p <= (rd_count_p_next_not_0);
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            cq2eg_pvld_p <= `x_or_0;
        end

    end
end
reg [17:0] cq2eg_pd;
wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        cq2eg_pvld_int <= 1'b0;
    end else begin
        cq2eg_pvld_int <= rd_req_next;
    end
end
always @( posedge nvdla_core_clk_mgated ) begin
    if ( (rd_popping) ) begin
        cq2eg_pd <= cq2eg_pd_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        cq2eg_pd <= {18{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit : 5'd0;
`else


assign wr_limit_muxed = 5'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 5'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 5'd0;
`else


reg wr_limit_override;
reg [4:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( nvdla_core_clk )
    , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd16 : wr_limit_reg} )
    , .curr ( {27'd0, ig2cq_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule