data/full_repos/permissive/484553918/rtl/top_ulx3s.v
1: b"%Error: data/full_repos/permissive/484553918/rtl/top_ulx3s.v:40: Cannot find file containing module: 'ecp5pll'\necp5pll\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/484553918/rtl,data/full_repos/permissive/484553918/ecp5pll\n             data/full_repos/permissive/484553918/rtl,data/full_repos/permissive/484553918/ecp5pll.v\n             data/full_repos/permissive/484553918/rtl,data/full_repos/permissive/484553918/ecp5pll.sv\n             ecp5pll\n             ecp5pll.v\n             ecp5pll.sv\n             obj_dir/ecp5pll\n             obj_dir/ecp5pll.v\n             obj_dir/ecp5pll.sv\n%Error: data/full_repos/permissive/484553918/rtl/top_ulx3s.v:53: Cannot find file containing module: 'top'\ntop #(\n^~~\n%Error: data/full_repos/permissive/484553918/rtl/top_ulx3s.v:80: Cannot find file containing module: 'hdmi_video'\nhdmi_video hdmi_video\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_ulx3s
(
    input clk_25mhz,

    output [3:0] gpdi_dp,
    output [7:0] led,


    output sdram_csn,
    output sdram_clk,
    output sdram_cke,
    output sdram_rasn,
    output sdram_casn,
    output sdram_wen,
    output [12:0] sdram_a,
    output [1:0] sdram_ba,
    output [1:0] sdram_dqm,
    inout [15:0] sdram_d,

    output ftdi_rxd,
    input ftdi_txd
);



wire hsync_n;
wire vsync_n;
wire blank_n;
wire[23:0] vga_color;

parameter CLK_SYS_HZ = 50_000_000;

wire [3:0] clocks;

wire clk_sys     = clocks[0];
assign sdram_clk = clocks[1];

ecp5pll
#(
    .in_hz(  25_000_000),
    .out0_hz(CLK_SYS_HZ),
    .out1_hz(CLK_SYS_HZ), .out1_deg(90)
)
ecp5pll_inst
(
    .clk_i(clk_25mhz),
    .clk_o(clocks),
    .locked()
);

top #(
    .CLK_SYS_HZ(CLK_SYS_HZ)
)
top_inst(
    .clk_sys,

    .led,

    .sdram_csn,
    .sdram_cke,
    .sdram_rasn,
    .sdram_casn,
    .sdram_wen,
    .sdram_a,
    .sdram_ba,
    .sdram_dqm,
    .sdram_d,

    .ftdi_rxd,
    .ftdi_txd,

    .hsync_n_o(hsync_n),
    .vsync_n_o(vsync_n),
    .blank_n_o(blank_n),
    .vga_color_o(vga_color)
);

hdmi_video hdmi_video
(
    .clk_25mhz(clk_25mhz),

    .hsync_n_i(hsync_n),
    .vsync_n_i(vsync_n),
    .blank_n_i(blank_n),

    .color_i(vga_color),

    .gpdi_dp(gpdi_dp)

);

endmodule
module top_ulx3s
(
    input clk_25mhz,

    output [3:0] gpdi_dp,
    output [7:0] led,


    output sdram_csn,
    output sdram_clk,
    output sdram_cke,
    output sdram_rasn,
    output sdram_casn,
    output sdram_wen,
    output [12:0] sdram_a,
    output [1:0] sdram_ba,
    output [1:0] sdram_dqm,
    inout [15:0] sdram_d,

    output ftdi_rxd,
    input ftdi_txd
);




wire hsync_n;
wire vsync_n;
wire blank_n;
wire[23:0] vga_color;

parameter CLK_SYS_HZ = 50_000_000;

wire [3:0] clocks;

wire clk_sys     = clocks[0];
assign sdram_clk = clocks[1];

ecp5pll
#(
    .in_hz(  25_000_000),
    .out0_hz(CLK_SYS_HZ),
    .out1_hz(CLK_SYS_HZ), .out1_deg(90)
)
ecp5pll_inst
(
    .clk_i(clk_25mhz),
    .clk_o(clocks),
    .locked()
);

top #(
    .CLK_SYS_HZ(CLK_SYS_HZ)
)
top_inst(
    .clk_sys,

    .led,

    .sdram_csn,
    .sdram_cke,
    .sdram_rasn,
    .sdram_casn,
    .sdram_wen,
    .sdram_a,
    .sdram_ba,
    .sdram_dqm,
    .sdram_d,

    .ftdi_rxd,
    .ftdi_txd,

    .hsync_n_o(hsync_n),
    .vsync_n_o(vsync_n),
    .blank_n_o(blank_n),
    .vga_color_o(vga_color)
);

hdmi_video hdmi_video
(
    .clk_25mhz(clk_25mhz),

    .hsync_n_i(hsync_n),
    .vsync_n_i(vsync_n),
    .blank_n_i(blank_n),

    .color_i(vga_color),

    .gpdi_dp(gpdi_dp)

);

endmodule