data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/D_ff_beh.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/D_ff_beh.v\n%Error: Exiting due to 5 error(s)\n'
module D_ff_beh(
	input CLOCK, 
	input D, 
	
	output Q,
	output Q_not

);	

wire CLOCK, D, Q_not;
reg  Q;

assign Q_not = !Q;

always@ (posedge CLOCK) begin
	Q <= D;
  end

endmodule
module D_ff_beh(
	input CLOCK, 
	input D, 
	
	output Q,
	output Q_not

);
	

wire CLOCK, D, Q_not;
reg  Q;

assign Q_not = !Q;

always@ (posedge CLOCK) begin
	Q <= D;
  end

endmodule