data/full_repos/permissive/521337848/Hardware/procesor/output.v
data/verilator_xmls/e34f377b-f21a-473d-be9a-ff8d4f492bca.xml
module bit16Buf(
	input clk,
	
	input s,
	
	input[15:0] in,
	output reg[15:0] out
);

always@(posedge clk)
	if(s) out <= in;
	else out <= 0;
endmodule
module bit16Buf(
	input clk,
	
	input s,
	
	input[15:0] in,
	output reg[15:0] out
);


always@(posedge clk)
	if(s) out <= in;
	else out <= 0;
endmodule