data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/carry_select_adder_32.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/carry_select_adder_32.v:14: Cannot find file containing module: 'carry_select_adder_16'\n carry_select_adder_16 csa_16_1(\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main,data/full_repos/permissive/499137621/carry_select_adder_16\n             data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main,data/full_repos/permissive/499137621/carry_select_adder_16.v\n             data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main,data/full_repos/permissive/499137621/carry_select_adder_16.sv\n             carry_select_adder_16\n             carry_select_adder_16.v\n             carry_select_adder_16.sv\n             obj_dir/carry_select_adder_16\n             obj_dir/carry_select_adder_16.v\n             obj_dir/carry_select_adder_16.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/carry_select_adder_32.v:25: Cannot find file containing module: 'carry_select_adder_16'\n  carry_select_adder_16 csa0_16_2(\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/carry_select_adder_32.v:35: Cannot find file containing module: 'carry_select_adder_16'\n  carry_select_adder_16 csa1_16_2(\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/carry_select_adder_32.v:45: Cannot find file containing module: 'Mux_36to18'\n Mux_36to18 mux_36to18(\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module carry_select_adder_32(a, b, c_in, s, c_out_31, c_in_31);
	input [31:0] a, b;
	input c_in;
	
	output [31:0] s;
	output c_out_31, c_in_31;
	
	wire [15:0]s_1, s_0;
	wire c_15, c_1, c_0;
	wire last_cin_0, last_cin_1;
	wire [3:0]useless;
	

	carry_select_adder_16 csa_16_1(
		.a(a[15:0]),
		.b(b[15:0]),
		.c_in(c_in),
		.s(s[15:0]),
		.c_out(c_15),
		.last_cin_0(useless[0]), 
		.last_cin_1(useless[1])
	);
	

		carry_select_adder_16 csa0_16_2(
		.a(a[31:16]),
		.b(b[31:16]),
		.c_in(1'b0),
		.s(s_0[15:0]),
		.c_out(c_0),
		.last_cin_0(last_cin_0), 
		.last_cin_1(useless[2])
	);
	
		carry_select_adder_16 csa1_16_2(
		.a(a[31:16]),
		.b(b[31:16]),
		.c_in(1'b1),
		.s(s_1[15:0]),
		.c_out(c_1),
		.last_cin_0(useless[3]), 
		.last_cin_1(last_cin_1)
	);
	
	Mux_36to18 mux_36to18(
		.s_0(s_0[15:0]), 
		.s_1(s_1[15:0]), 
		.c_out31_0(c_0), 
		.c_out31_1(c_1), 
		.c_in31_0(last_cin_0), 
		.c_in31_1(last_cin_1), 
		.c_in(c_15), 
		.result(s[31:16]),
		.c_out31(c_out_31), 
		.c_in31(c_in_31)
	);
	

	
endmodule
module carry_select_adder_32(a, b, c_in, s, c_out_31, c_in_31);

	input [31:0] a, b;
	input c_in;
	
	output [31:0] s;
	output c_out_31, c_in_31;
	
	wire [15:0]s_1, s_0;
	wire c_15, c_1, c_0;
	wire last_cin_0, last_cin_1;
	wire [3:0]useless;
	

	carry_select_adder_16 csa_16_1(
		.a(a[15:0]),
		.b(b[15:0]),
		.c_in(c_in),
		.s(s[15:0]),
		.c_out(c_15),
		.last_cin_0(useless[0]), 
		.last_cin_1(useless[1])
	);
	

		carry_select_adder_16 csa0_16_2(
		.a(a[31:16]),
		.b(b[31:16]),
		.c_in(1'b0),
		.s(s_0[15:0]),
		.c_out(c_0),
		.last_cin_0(last_cin_0), 
		.last_cin_1(useless[2])
	);
	
		carry_select_adder_16 csa1_16_2(
		.a(a[31:16]),
		.b(b[31:16]),
		.c_in(1'b1),
		.s(s_1[15:0]),
		.c_out(c_1),
		.last_cin_0(useless[3]), 
		.last_cin_1(last_cin_1)
	);
	
	Mux_36to18 mux_36to18(
		.s_0(s_0[15:0]), 
		.s_1(s_1[15:0]), 
		.c_out31_0(c_0), 
		.c_out31_1(c_1), 
		.c_in31_0(last_cin_0), 
		.c_in31_1(last_cin_1), 
		.c_in(c_15), 
		.result(s[31:16]),
		.c_out31(c_out_31), 
		.c_in31(c_in_31)
	);
	

	
endmodule