data/full_repos/permissive/452016975/src/sign_extend_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/sign_extend_testbench.v:7: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/sign_extend_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/sign_extend_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/452016975/src/sign_extend_testbench.v:14: Unsupported or unknown PLI call: $monitor\n $monitor("time=%2d,number=%6b,result=%32b",$time,A,result);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sign_extend_testbench();
	reg  [5:0] A;
	wire [31:0] result;
	sign_extend my_sign_extend(result,A);
	initial begin
	A = 16'b000000; 
	#20;
	A = 16'b001001; 
	#20;
	A = 16'b111111; 
	#20;
	end
	initial begin
	$monitor("time=%2d,number=%6b,result=%32b",$time,A,result);
	end
endmodule
module sign_extend_testbench();

	reg  [5:0] A;
	wire [31:0] result;
	sign_extend my_sign_extend(result,A);
	initial begin
	A = 16'b000000; 
	#20;
	A = 16'b001001; 
	#20;
	A = 16'b111111; 
	#20;
	end
	initial begin
	$monitor("time=%2d,number=%6b,result=%32b",$time,A,result);
	end
endmodule