data/full_repos/permissive/509809169/Verilog Language/Basics/7458 chip.v
1: b'%Error: Cannot find file containing module: Language/Basics,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169.sv\n             Language/Basics,data/full_repos/permissive/509809169\n             Language/Basics,data/full_repos/permissive/509809169.v\n             Language/Basics,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Basics/7458\n%Error: Cannot find file containing module: chip.v\n%Error: Exiting due to 4 error(s)\n'
module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
    assign p2y= (p2a & p2b) | (p2c & p2d);
endmodule
module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    
    assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
    assign p2y= (p2a & p2b) | (p2c & p2d);
endmodule