data/full_repos/permissive/441359809/src/yosys/tests/simple/attrib03_parameter.v
data/verilator_xmls/422833cf-503c-4aac-9589-cc26aace2146.xml
module bar(clk, rst, inp, out);

  (* bus_width *)
  parameter WIDTH = 2;

  (* an_attribute_on_localparam = 55 *)
  localparam INCREMENT = 5;

  input  wire clk;
  input  wire rst;
  input  wire [WIDTH-1:0] inp;
  output reg  [WIDTH-1:0] out;

  always @(posedge clk)
    if (rst) out <= 0;
    else     out <= inp + INCREMENT;

endmodule
module bar(clk, rst, inp, out);


  (* bus_width *)
  parameter WIDTH = 2;

  (* an_attribute_on_localparam = 55 *)
  localparam INCREMENT = 5;

  input  wire clk;
  input  wire rst;
  input  wire [WIDTH-1:0] inp;
  output reg  [WIDTH-1:0] out;

  always @(posedge clk)
    if (rst) out <= 0;
    else     out <= inp + INCREMENT;

endmodule