data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v
1: b'%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:27: Cannot find include file: toysram.vh\n`include "toysram.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530250155/verilog/rtl/array,data/full_repos/permissive/530250155/toysram.vh\n             data/full_repos/permissive/530250155/verilog/rtl/array,data/full_repos/permissive/530250155/toysram.vh.v\n             data/full_repos/permissive/530250155/verilog/rtl/array,data/full_repos/permissive/530250155/toysram.vh.sv\n             toysram.vh\n             toysram.vh.v\n             toysram.vh.sv\n             obj_dir/toysram.vh\n             obj_dir/toysram.vh.v\n             obj_dir/toysram.vh.sv\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:30: Define or directive not defined: \'`RA_SIM\'\n   parameter RA_SELECT = `RA_SIM\n                         ^~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:120: syntax error, unexpected assign\n   assign rd0_enable = rd0_c_a0 | rd0_c_na0;\n   ^~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:149: Define or directive not defined: \'`RA_SIM\'\n   `RA_SIM: begin         \n   ^~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:156: syntax error, unexpected genvar\n      genvar i;\n      ^~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:159: syntax error, unexpected assign\n         assign q = mem[i];\n         ^~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:179: Define or directive not defined: \'`RA_DFFRAM\'\n   `RA_DFFRAM: begin         \n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:198: Define or directive not defined: \'`RA_TOYSRAM\'\n   `RA_TOYSRAM: begin       \n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/rtl/array/regfile_2r1w_32x32.v:203: Define or directive not defined: \'`RA_TOYSRAM_BARE\'\n   `RA_TOYSRAM_BARE: begin     \n   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module regfile_2r1w_32x32 #(
   parameter RA_SELECT = `RA_SIM
) (

`ifdef USE_POWER_PINS
   input vccd1,
   input vssd1,
`endif

   input   clk,




   input   rd0_c_na0,
   input   rd0_c_a0,

   input   rd0_na1_na2,
   input   rd0_na1_a2,
   input   rd0_a1_na2,
   input   rd0_a1_a2,

   input   rd0_na3,
   input   rd0_a3,

   input   rd0_na4,
   input   rd0_a4,


   input   rd1_c_na0,
   input   rd1_c_a0,

   input   rd1_na1_na2,
   input   rd1_na1_a2,
   input   rd1_a1_na2,
   input   rd1_a1_a2,

   input   rd1_na3,
   input   rd1_a3,

   input   rd1_na4,
   input   rd1_a4,


   input   wr0_c_na0,
   input   wr0_c_a0,

   input   wr0_na1_na2,
   input   wr0_na1_a2,
   input   wr0_a1_na2,
   input   wr0_a1_a2,

   input   wr0_na3,
   input   wr0_a3,

   input   wr0_na4,
   input   wr0_a4,


   output [0:31] rd0_dat,
   output [0:31] rd1_dat,
   input  [0:31] wr0_dat
);

   wire rd0_enable;
   wire rd1_enable;
   wire wr0_enable;

   wire rd0_a0;
   wire rd0_a1;
   wire rd0_a2;



   wire rd1_a0;
   wire rd1_a1;
   wire rd1_a2;



   wire wr0_a0;
   wire wr0_a1;
   wire wr0_a2;



   wire   [0:4] rd0_adr;
   wire   [0:4] rd1_adr;
   wire   [0:4] wr0_adr;


   assign rd0_enable = rd0_c_a0 | rd0_c_na0;
   assign rd0_a0 = rd0_c_a0;
   assign rd0_a1 = rd0_a1_a2 | rd0_a1_na2;
   assign rd0_a2 = rd0_a1_a2 | rd0_na1_a2;




   assign rd1_enable = rd1_c_a0 | rd1_c_na0;
   assign rd1_a0 = rd1_c_a0;
   assign rd1_a1 = rd1_a1_a2 | rd1_a1_na2;
   assign rd1_a2 = rd1_a1_a2 | rd1_na1_a2;




   assign wr0_enable = wr0_c_a0 | wr0_c_na0;
   assign wr0_a0 = wr0_c_a0;
   assign wr0_a1 = wr0_a1_a2 | wr0_a1_na2;
   assign wr0_a2 = wr0_a1_a2 | wr0_na1_a2;



   assign rd0_adr = {rd0_a0, rd0_a1, rd0_a2, rd0_a3, rd0_a4};
   assign rd1_adr = {rd1_a0, rd1_a1, rd1_a2, rd1_a3, rd1_a4};
   assign wr0_adr = {wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4};

generate case (RA_SELECT)

   `RA_SIM: begin


   reg[0:31] mem[0:31];



      genvar i;
      for (i = 0; i < 31; i=i+1) begin: ra
         wire [0:31] q;
         assign q = mem[i];
      end



   assign rd0_dat = (rd0_enable) ? mem[rd0_adr] : 31'bX;
   assign rd1_dat = (rd1_enable) ? mem[rd1_adr] : 31'bX;


   always @* begin
      if (wr0_enable) begin
         #10;
         if (wr0_enable) begin
            mem[wr0_adr] <= wr0_dat;

         end
      end
   end
   end

   `RA_DFFRAM: begin

      DFFRF_2R1W #() mem (
         `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
         `endif
         .CLK(clk),
         .RA(rd0_adr),
         .DA(rd0_dat),
         .RB(rd1_adr),
         .DB(rd1_dat),
         .RW(wr0_adr),
         .WE(wr0_enable),
         .DW(wr0_dat)
      );

   end

   `RA_TOYSRAM: begin


   end

   `RA_TOYSRAM_BARE: begin



   end

endcase

endgenerate

endmodule
module regfile_2r1w_32x32 #(
   parameter RA_SELECT = `RA_SIM
) (

`ifdef USE_POWER_PINS
   input vccd1,
   input vssd1,
`endif

   input   clk,




   input   rd0_c_na0,
   input   rd0_c_a0,

   input   rd0_na1_na2,
   input   rd0_na1_a2,
   input   rd0_a1_na2,
   input   rd0_a1_a2,

   input   rd0_na3,
   input   rd0_a3,

   input   rd0_na4,
   input   rd0_a4,


   input   rd1_c_na0,
   input   rd1_c_a0,

   input   rd1_na1_na2,
   input   rd1_na1_a2,
   input   rd1_a1_na2,
   input   rd1_a1_a2,

   input   rd1_na3,
   input   rd1_a3,

   input   rd1_na4,
   input   rd1_a4,


   input   wr0_c_na0,
   input   wr0_c_a0,

   input   wr0_na1_na2,
   input   wr0_na1_a2,
   input   wr0_a1_na2,
   input   wr0_a1_a2,

   input   wr0_na3,
   input   wr0_a3,

   input   wr0_na4,
   input   wr0_a4,


   output [0:31] rd0_dat,
   output [0:31] rd1_dat,
   input  [0:31] wr0_dat
);


   wire rd0_enable;
   wire rd1_enable;
   wire wr0_enable;

   wire rd0_a0;
   wire rd0_a1;
   wire rd0_a2;



   wire rd1_a0;
   wire rd1_a1;
   wire rd1_a2;



   wire wr0_a0;
   wire wr0_a1;
   wire wr0_a2;



   wire   [0:4] rd0_adr;
   wire   [0:4] rd1_adr;
   wire   [0:4] wr0_adr;


   assign rd0_enable = rd0_c_a0 | rd0_c_na0;
   assign rd0_a0 = rd0_c_a0;
   assign rd0_a1 = rd0_a1_a2 | rd0_a1_na2;
   assign rd0_a2 = rd0_a1_a2 | rd0_na1_a2;




   assign rd1_enable = rd1_c_a0 | rd1_c_na0;
   assign rd1_a0 = rd1_c_a0;
   assign rd1_a1 = rd1_a1_a2 | rd1_a1_na2;
   assign rd1_a2 = rd1_a1_a2 | rd1_na1_a2;




   assign wr0_enable = wr0_c_a0 | wr0_c_na0;
   assign wr0_a0 = wr0_c_a0;
   assign wr0_a1 = wr0_a1_a2 | wr0_a1_na2;
   assign wr0_a2 = wr0_a1_a2 | wr0_na1_a2;



   assign rd0_adr = {rd0_a0, rd0_a1, rd0_a2, rd0_a3, rd0_a4};
   assign rd1_adr = {rd1_a0, rd1_a1, rd1_a2, rd1_a3, rd1_a4};
   assign wr0_adr = {wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4};

generate case (RA_SELECT)

   `RA_SIM: begin


   reg[0:31] mem[0:31];



      genvar i;
      for (i = 0; i < 31; i=i+1) begin: ra
         wire [0:31] q;
         assign q = mem[i];
      end



   assign rd0_dat = (rd0_enable) ? mem[rd0_adr] : 31'bX;
   assign rd1_dat = (rd1_enable) ? mem[rd1_adr] : 31'bX;


   always @* begin
      if (wr0_enable) begin
         #10;
         if (wr0_enable) begin
            mem[wr0_adr] <= wr0_dat;

         end
      end
   end
   end

   `RA_DFFRAM: begin

      DFFRF_2R1W #() mem (
         `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
         `endif
         .CLK(clk),
         .RA(rd0_adr),
         .DA(rd0_dat),
         .RB(rd1_adr),
         .DB(rd1_dat),
         .RW(wr0_adr),
         .WE(wr0_enable),
         .DW(wr0_dat)
      );

   end

   `RA_TOYSRAM: begin


   end

   `RA_TOYSRAM_BARE: begin



   end

endcase

endgenerate

endmodule