data/full_repos/permissive/46132596/processor/SingleCycleDatapath/ShiftLeft.v
data/verilator_xmls/0a81c49b-bf19-4024-8f3b-64378228730f.xml
module ShiftLeft(input[31:0] in,
		output[31:0] out);
	
	assign out = in << 2;

endmodule
module ShiftLeft(input[31:0] in,
		output[31:0] out);

	
	assign out = in << 2;

endmodule