data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:10: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 slow_clock = ~slow_clock;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:78: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:83: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:87: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:91: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:96: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:100: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:107: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:109: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:111: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:115: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:122: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:124: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:126: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:130: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:137: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:139: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:141: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:146: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:149: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:156: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:158: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:160: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:165: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:168: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:175: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:177: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:179: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:183: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:190: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:192: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:194: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:198: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:202: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:209: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:211: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:213: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:218: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:221: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:228: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:230: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:232: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:237: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:240: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:247: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:249: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:251: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:255: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:262: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:264: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:266: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:270: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:274: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:281: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:283: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:285: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:290: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:297: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:299: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:301: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:306: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:313: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:315: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:317: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:321: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:328: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:330: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:332: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:336: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:340: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:347: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:349: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:351: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:356: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:359: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:366: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:368: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:370: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:375: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:382: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:384: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:386: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:390: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:397: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:399: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:401: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:405: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:409: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:416: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:418: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:420: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:424: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:431: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:433: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:435: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:439: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:446: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:448: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:450: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:454: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:461: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:463: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:465: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:469: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:473: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:480: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:482: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:484: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:488: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:495: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:497: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:499: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:506: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:508: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:510: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:517: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:519: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:521: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:528: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:19: Can\'t find definition of \'next_state\' in dotted variable: \'tb_statemachine.dut.next_state\'\n            if (tb_statemachine.dut.next_state !== exp_state) begin\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:20: Can\'t find definition of \'next_state\' in dotted variable: \'tb_statemachine.dut.next_state\'\n                $display("ERROR A: Expected next_state is %b, actual next_state is %b", exp_state, tb_statemachine.dut.next_state);\n                                                                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:23: Can\'t find definition of \'load_pcard1\' in dotted variable: \'tb_statemachine.dut.load_pcard1\'\n            if (tb_statemachine.dut.load_pcard1 !== exp_out[7]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:24: Can\'t find definition of \'load_pcard1\' in dotted variable: \'tb_statemachine.dut.load_pcard1\'\n                $display("ERROR B: Expected load_pcard1 is %b, actual load_pcard1 is %b", exp_out[7], tb_statemachine.dut.load_pcard1);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:27: Can\'t find definition of \'load_pcard2\' in dotted variable: \'tb_statemachine.dut.load_pcard2\'\n            if (tb_statemachine.dut.load_pcard2 !== exp_out[6]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:28: Can\'t find definition of \'load_pcard2\' in dotted variable: \'tb_statemachine.dut.load_pcard2\'\n                $display("ERROR C: Expected load_pcard2 is %b, actual load_pcard2 is %b", exp_out[6], tb_statemachine.dut.load_pcard2);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:31: Can\'t find definition of \'load_pcard3\' in dotted variable: \'tb_statemachine.dut.load_pcard3\'\n            if (tb_statemachine.dut.load_pcard3 !== exp_out[5]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:32: Can\'t find definition of \'load_pcard3\' in dotted variable: \'tb_statemachine.dut.load_pcard3\'\n                $display("ERROR D: Expected load_pcard3 is %b, actual load_pcard3 is %b", exp_out[5], tb_statemachine.dut.load_pcard3);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:35: Can\'t find definition of \'load_dcard1\' in dotted variable: \'tb_statemachine.dut.load_dcard1\'\n            if (tb_statemachine.dut.load_dcard1 !== exp_out[4]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:36: Can\'t find definition of \'load_dcard1\' in dotted variable: \'tb_statemachine.dut.load_dcard1\'\n                $display("ERROR E: Expected load_dcard1 is %b, actual load_dcard1 is %b", exp_out[4], tb_statemachine.dut.load_dcard1);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:39: Can\'t find definition of \'load_dcard2\' in dotted variable: \'tb_statemachine.dut.load_dcard2\'\n            if (tb_statemachine.dut.load_dcard2 !== exp_out[3]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:40: Can\'t find definition of \'load_dcard2\' in dotted variable: \'tb_statemachine.dut.load_dcard2\'\n                $display("ERROR F: Expected load_dcard2 is %b, actual load_dcard2 is %b", exp_out[3], tb_statemachine.dut.load_dcard2);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:43: Can\'t find definition of \'load_dcard3\' in dotted variable: \'tb_statemachine.dut.load_dcard3\'\n            if (tb_statemachine.dut.load_dcard3 !== exp_out[2]) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:44: Can\'t find definition of \'load_dcard3\' in dotted variable: \'tb_statemachine.dut.load_dcard3\'\n                $display("ERROR G: Expected load_dcard3 is %b, actual load_dcard3 is %b", exp_out[2], tb_statemachine.dut.load_dcard3);\n                                                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:47: Can\'t find definition of \'player_win_light\' in dotted variable: \'tb_statemachine.dut.player_win_light\'\n            if (tb_statemachine.dut.player_win_light !== exp_out[1]) begin\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:48: Can\'t find definition of \'player_win_light\' in dotted variable: \'tb_statemachine.dut.player_win_light\'\n                $display("ERROR H: Expected player_win_light is %b, actual player_win_light is %b", exp_out[1], tb_statemachine.dut.player_win_light);\n                                                                                                                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:51: Can\'t find definition of \'dealer_win_light\' in dotted variable: \'tb_statemachine.dut.dealer_win_light\'\n            if (tb_statemachine.dut.dealer_win_light !== exp_out[0]) begin\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab1/task5/tb_statemachine.sv:52: Can\'t find definition of \'dealer_win_light\' in dotted variable: \'tb_statemachine.dut.dealer_win_light\'\n                $display("ERROR I: Expected dealer_win_light is %b, actual dealer_win_light is %b", exp_out[0], tb_statemachine.dut.dealer_win_light);\n                                                                                                                                    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 18 error(s), 119 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_statemachine();

    logic slow_clock, resetb, load_pcard1, load_pcard2, load_pcard3, load_dcard1, load_dcard2, load_dcard3, player_win_light, dealer_win_light, err;
    logic [3:0] dscore, pscore, pcard3;

    statemachine dut(.*);

    initial begin
        slow_clock = 0;
        forever #5 slow_clock = ~slow_clock;
    end

    task validator;
        input [31:0] index;
        input [3:0] exp_state;
        input [7:0] exp_out;
        begin
            $display("TEST %d", index);
            if (tb_statemachine.dut.next_state !== exp_state) begin
                $display("ERROR A: Expected next_state is %b, actual next_state is %b", exp_state, tb_statemachine.dut.next_state);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard1 !== exp_out[7]) begin
                $display("ERROR B: Expected load_pcard1 is %b, actual load_pcard1 is %b", exp_out[7], tb_statemachine.dut.load_pcard1);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard2 !== exp_out[6]) begin
                $display("ERROR C: Expected load_pcard2 is %b, actual load_pcard2 is %b", exp_out[6], tb_statemachine.dut.load_pcard2);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard3 !== exp_out[5]) begin
                $display("ERROR D: Expected load_pcard3 is %b, actual load_pcard3 is %b", exp_out[5], tb_statemachine.dut.load_pcard3);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard1 !== exp_out[4]) begin
                $display("ERROR E: Expected load_dcard1 is %b, actual load_dcard1 is %b", exp_out[4], tb_statemachine.dut.load_dcard1);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard2 !== exp_out[3]) begin
                $display("ERROR F: Expected load_dcard2 is %b, actual load_dcard2 is %b", exp_out[3], tb_statemachine.dut.load_dcard2);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard3 !== exp_out[2]) begin
                $display("ERROR G: Expected load_dcard3 is %b, actual load_dcard3 is %b", exp_out[2], tb_statemachine.dut.load_dcard3);
                err = 1'b1;
            end
            if (tb_statemachine.dut.player_win_light !== exp_out[1]) begin
                $display("ERROR H: Expected player_win_light is %b, actual player_win_light is %b", exp_out[1], tb_statemachine.dut.player_win_light);
                err = 1'b1;
            end
            if (tb_statemachine.dut.dealer_win_light !== exp_out[0]) begin
                $display("ERROR I: Expected dealer_win_light is %b, actual dealer_win_light is %b", exp_out[0], tb_statemachine.dut.dealer_win_light);
                err = 1'b1;
            end
        end
    endtask

    `define WAIT      4'b0000
    `define LOAD_P1   4'b0001
    `define LOAD_P2   4'b0010
    `define LOAD_P3   4'b0011
    `define LOAD_D1   4'b0100
    `define LOAD_D2   4'b0101
    `define LOAD_D3   4'b0110
    `define CALC_RES  4'b0111
    `define P_WIN     4'b1000
    `define D_WIN     4'b1001
    `define TIE       4'b1010

    initial begin
        err = 1'b0;


        validator(1, 4'bx, 8'bx);


        resetb = 1'b0;
        #10;
        validator(2, `LOAD_P1, 8'b10000000);


        resetb = 1'b1;
        #10;
        validator(3, `LOAD_D1, 8'b00010000);


        #10;
        validator(4, `LOAD_P2, 8'b01000000);


        #10;
        validator(5, `LOAD_D2, 8'b00001000);


        dscore = 4'd8; pscore = 4'd3; pcard3 = 4'd0;
        #10;
        validator(6, `D_WIN, 8'b00000001);


        #10;
        validator(7, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd9; dscore = 4'd8; pcard3 = 4'b0;
        #10;
        validator(8, `P_WIN, 8'b00000010);


        #10;
        validator(9, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd8; dscore = 4'd8; pcard3 = 4'b0;
        #10;
        validator(10, `TIE, 8'b00000011);


        #10;
        validator(11, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(12, `LOAD_P3, 8'b00100000);


        pscore = 4'd8;
        #5;
        validator(13, `P_WIN, 8'b00000010);

        #5;
        validator(13, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(14, `LOAD_P3, 8'b00100000);


        pscore = 4'd7;
        #5;
        validator(15, `TIE, 8'b00000011);

        #5;
        validator(16, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(17, `LOAD_P3, 8'b00100000);


        #20;
        validator(18, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd6; pcard3 = 4'd6;
        #10;
        validator(19, `LOAD_P3, 8'b00100000);


        #10;
        validator(20, `LOAD_D3, 8'b00000100);


        #10;
        validator(21, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd6; pcard3 = 4'd4;
        #10;
        validator(22, `LOAD_P3, 8'b00100000);


        pscore = 4'd7;
        #5;
        validator(23, `P_WIN, 8'b00000010);

        #5;
        validator(24, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd6; pcard3 = 4'd8;
        #10;
        validator(25, `LOAD_P3, 8'b00100000);


        pscore = 4'd6;
        #5;
        validator(26, `TIE, 8'b00000011);

        #5;
        validator(27, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd6; pcard3 = 4'd8;
        #10;
        validator(28, `LOAD_P3, 8'b00100000);


        #20;
        validator(29, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd5; pcard3 = 4'd5;
        #10;
        validator(30, `LOAD_P3, 8'b00100000);


        #10;
        validator(31, `LOAD_D3, 8'b00000100);


        #10;
        validator(32, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd5; pcard3 = 4'd3;
        #10;
        validator(33, `LOAD_P3, 8'b00100000);


        pscore = 4'd6;
        #10;
        validator(34, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd5; pcard3 = 4'd2;
        #10;
        validator(35, `LOAD_P3, 8'b00100000);


        pscore = 4'd5;
        #20;
        validator(36, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd5; pcard3 = 4'd9;
        #10;
        validator(37, `LOAD_P3, 8'b00100000);


        #20;
        validator(38, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd4; pcard3 = 4'd5;
        #10;
        validator(39, `LOAD_P3, 8'b00100000);


        #10;
        validator(40, `LOAD_D3, 8'b00000100);


        #10;
        validator(41, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd4; pcard3 = 4'd8;
        #10;
        validator(42, `LOAD_P3, 8'b00100000);


        pscore = 4'd8;
        #5;
        validator(43, `P_WIN, 8'b00000010);

        #5;
        validator(44, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd4; pcard3 = 4'd9;
        #10;
        validator(45, `LOAD_P3, 8'b00100000);


        pscore = 4'd4;
        #20;
        validator(46, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd4; pcard3 = 4'd1;
        #10;
        validator(47, `LOAD_P3, 8'b00100000);


        #20;
        validator(48, `D_WIN, 8'b00000001);
        



        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd3; pcard3 = 4'd1;
        #10;
        validator(49, `LOAD_P3, 8'b00100000);


        #10;
        validator(50, `LOAD_D3, 8'b00000100);


        #10;
        validator(51, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd5; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(52, `LOAD_P3, 8'b00100000);


        #20;
        validator(53, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(54, `LOAD_P3, 8'b00100000);


        #20;
        validator(55, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(56, `LOAD_P3, 8'b00100000);


        #20;
        validator(57, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd2; pcard3 = 4'd8;
        #10;
        validator(58, `LOAD_P3, 8'b00100000);


        #10;
        validator(59, `LOAD_D3, 8'b00000100);


        #10;
        validator(60, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd2; pcard3 = 4'd8;
        #10;
        validator(61, `LOAD_D3, 8'b00000100);


        #10;
        validator(62, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd7; dscore = 4'd6; pcard3 = 4'd0;
        #10;
        validator(63, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd6; pcard3 = 4'd0;
        #10;
        validator(64, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd7; pcard3 = 4'd0;
        #10;
        validator(65, `D_WIN, 8'b00000001);




        resetb = 1'bx; dscore = 4'bx; pscore = 4'bx; pcard3 = 4'bx;
        #10;
        validator(66, 4'bx, 8'bx);


        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end
						
endmodule
module tb_statemachine();


    logic slow_clock, resetb, load_pcard1, load_pcard2, load_pcard3, load_dcard1, load_dcard2, load_dcard3, player_win_light, dealer_win_light, err;
    logic [3:0] dscore, pscore, pcard3;

    statemachine dut(.*);

    initial begin
        slow_clock = 0;
        forever #5 slow_clock = ~slow_clock;
    end

    task validator;
        input [31:0] index;
        input [3:0] exp_state;
        input [7:0] exp_out;
        begin
            $display("TEST %d", index);
            if (tb_statemachine.dut.next_state !== exp_state) begin
                $display("ERROR A: Expected next_state is %b, actual next_state is %b", exp_state, tb_statemachine.dut.next_state);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard1 !== exp_out[7]) begin
                $display("ERROR B: Expected load_pcard1 is %b, actual load_pcard1 is %b", exp_out[7], tb_statemachine.dut.load_pcard1);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard2 !== exp_out[6]) begin
                $display("ERROR C: Expected load_pcard2 is %b, actual load_pcard2 is %b", exp_out[6], tb_statemachine.dut.load_pcard2);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_pcard3 !== exp_out[5]) begin
                $display("ERROR D: Expected load_pcard3 is %b, actual load_pcard3 is %b", exp_out[5], tb_statemachine.dut.load_pcard3);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard1 !== exp_out[4]) begin
                $display("ERROR E: Expected load_dcard1 is %b, actual load_dcard1 is %b", exp_out[4], tb_statemachine.dut.load_dcard1);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard2 !== exp_out[3]) begin
                $display("ERROR F: Expected load_dcard2 is %b, actual load_dcard2 is %b", exp_out[3], tb_statemachine.dut.load_dcard2);
                err = 1'b1;
            end
            if (tb_statemachine.dut.load_dcard3 !== exp_out[2]) begin
                $display("ERROR G: Expected load_dcard3 is %b, actual load_dcard3 is %b", exp_out[2], tb_statemachine.dut.load_dcard3);
                err = 1'b1;
            end
            if (tb_statemachine.dut.player_win_light !== exp_out[1]) begin
                $display("ERROR H: Expected player_win_light is %b, actual player_win_light is %b", exp_out[1], tb_statemachine.dut.player_win_light);
                err = 1'b1;
            end
            if (tb_statemachine.dut.dealer_win_light !== exp_out[0]) begin
                $display("ERROR I: Expected dealer_win_light is %b, actual dealer_win_light is %b", exp_out[0], tb_statemachine.dut.dealer_win_light);
                err = 1'b1;
            end
        end
    endtask

    `define WAIT      4'b0000
    `define LOAD_P1   4'b0001
    `define LOAD_P2   4'b0010
    `define LOAD_P3   4'b0011
    `define LOAD_D1   4'b0100
    `define LOAD_D2   4'b0101
    `define LOAD_D3   4'b0110
    `define CALC_RES  4'b0111
    `define P_WIN     4'b1000
    `define D_WIN     4'b1001
    `define TIE       4'b1010

    initial begin
        err = 1'b0;


        validator(1, 4'bx, 8'bx);


        resetb = 1'b0;
        #10;
        validator(2, `LOAD_P1, 8'b10000000);


        resetb = 1'b1;
        #10;
        validator(3, `LOAD_D1, 8'b00010000);


        #10;
        validator(4, `LOAD_P2, 8'b01000000);


        #10;
        validator(5, `LOAD_D2, 8'b00001000);


        dscore = 4'd8; pscore = 4'd3; pcard3 = 4'd0;
        #10;
        validator(6, `D_WIN, 8'b00000001);


        #10;
        validator(7, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd9; dscore = 4'd8; pcard3 = 4'b0;
        #10;
        validator(8, `P_WIN, 8'b00000010);


        #10;
        validator(9, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd8; dscore = 4'd8; pcard3 = 4'b0;
        #10;
        validator(10, `TIE, 8'b00000011);


        #10;
        validator(11, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(12, `LOAD_P3, 8'b00100000);


        pscore = 4'd8;
        #5;
        validator(13, `P_WIN, 8'b00000010);

        #5;
        validator(13, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(14, `LOAD_P3, 8'b00100000);


        pscore = 4'd7;
        #5;
        validator(15, `TIE, 8'b00000011);

        #5;
        validator(16, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd7; pcard3 = 4'b0;
        #10;
        validator(17, `LOAD_P3, 8'b00100000);


        #20;
        validator(18, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd6; pcard3 = 4'd6;
        #10;
        validator(19, `LOAD_P3, 8'b00100000);


        #10;
        validator(20, `LOAD_D3, 8'b00000100);


        #10;
        validator(21, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd6; pcard3 = 4'd4;
        #10;
        validator(22, `LOAD_P3, 8'b00100000);


        pscore = 4'd7;
        #5;
        validator(23, `P_WIN, 8'b00000010);

        #5;
        validator(24, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd6; pcard3 = 4'd8;
        #10;
        validator(25, `LOAD_P3, 8'b00100000);


        pscore = 4'd6;
        #5;
        validator(26, `TIE, 8'b00000011);

        #5;
        validator(27, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd6; pcard3 = 4'd8;
        #10;
        validator(28, `LOAD_P3, 8'b00100000);


        #20;
        validator(29, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd5; pcard3 = 4'd5;
        #10;
        validator(30, `LOAD_P3, 8'b00100000);


        #10;
        validator(31, `LOAD_D3, 8'b00000100);


        #10;
        validator(32, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd5; pcard3 = 4'd3;
        #10;
        validator(33, `LOAD_P3, 8'b00100000);


        pscore = 4'd6;
        #10;
        validator(34, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd5; pcard3 = 4'd2;
        #10;
        validator(35, `LOAD_P3, 8'b00100000);


        pscore = 4'd5;
        #20;
        validator(36, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd5; pcard3 = 4'd9;
        #10;
        validator(37, `LOAD_P3, 8'b00100000);


        #20;
        validator(38, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd4; pcard3 = 4'd5;
        #10;
        validator(39, `LOAD_P3, 8'b00100000);


        #10;
        validator(40, `LOAD_D3, 8'b00000100);


        #10;
        validator(41, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd4; pcard3 = 4'd8;
        #10;
        validator(42, `LOAD_P3, 8'b00100000);


        pscore = 4'd8;
        #5;
        validator(43, `P_WIN, 8'b00000010);

        #5;
        validator(44, `WAIT, 8'b0);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd4; pcard3 = 4'd9;
        #10;
        validator(45, `LOAD_P3, 8'b00100000);


        pscore = 4'd4;
        #20;
        validator(46, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd2; dscore = 4'd4; pcard3 = 4'd1;
        #10;
        validator(47, `LOAD_P3, 8'b00100000);


        #20;
        validator(48, `D_WIN, 8'b00000001);
        



        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd0; dscore = 4'd3; pcard3 = 4'd1;
        #10;
        validator(49, `LOAD_P3, 8'b00100000);


        #10;
        validator(50, `LOAD_D3, 8'b00000100);


        #10;
        validator(51, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd5; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(52, `LOAD_P3, 8'b00100000);


        #20;
        validator(53, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd3; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(54, `LOAD_P3, 8'b00100000);


        #20;
        validator(55, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd1; dscore = 4'd3; pcard3 = 4'd8;
        #10;
        validator(56, `LOAD_P3, 8'b00100000);


        #20;
        validator(57, `D_WIN, 8'b00000001);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd4; dscore = 4'd2; pcard3 = 4'd8;
        #10;
        validator(58, `LOAD_P3, 8'b00100000);


        #10;
        validator(59, `LOAD_D3, 8'b00000100);


        #10;
        validator(60, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd2; pcard3 = 4'd8;
        #10;
        validator(61, `LOAD_D3, 8'b00000100);


        #10;
        validator(62, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd7; dscore = 4'd6; pcard3 = 4'd0;
        #10;
        validator(63, `P_WIN, 8'b00000010);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd6; pcard3 = 4'd0;
        #10;
        validator(64, `TIE, 8'b00000011);




        resetb = 1'b0; dscore = 4'b0; pscore = 4'b0; pcard3 = 4'b0;
        #10;
        resetb = 1'b1;
        #30;
        pscore = 4'd6; dscore = 4'd7; pcard3 = 4'd0;
        #10;
        validator(65, `D_WIN, 8'b00000001);




        resetb = 1'bx; dscore = 4'bx; pscore = 4'bx; pcard3 = 4'bx;
        #10;
        validator(66, 4'bx, 8'bx);


        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end
						
endmodule