data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/clk_div.v
data/verilator_xmls/bf2ff598-4f20-404b-97f9-26e650ae681a.xml
module clk_div (clkin, tc, clkout);

	parameter	BIT_SZ = 21;

	input				clkin;
	input [BIT_SZ-1:0]	tc;
	output			clkout;

	reg				clkout;
	reg [BIT_SZ-1:0]		ctr;
	initial begin
		clkout = 0;
		ctr = 0;
	end
		
	always @ (posedge clkin)
	  if (ctr==0) begin
		  ctr <= tc;
		  clkout <= ~clkout;
		end
	  else
		  ctr <= ctr - 1'b1;
		  
endmodule
module clk_div (clkin, tc, clkout);


	parameter	BIT_SZ = 21;

	input				clkin;
	input [BIT_SZ-1:0]	tc;
	output			clkout;

	reg				clkout;
	reg [BIT_SZ-1:0]		ctr;
	initial begin
		clkout = 0;
		ctr = 0;
	end
		
	always @ (posedge clkin)
	  if (ctr==0) begin
		  ctr <= tc;
		  clkout <= ~clkout;
		end
	  else
		  ctr <= ctr - 1'b1;
		  
endmodule