data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v:12: Unsupported or unknown PLI call: $monitor\n  $monitor ("X = %b Y = %b F = %b", X, Y, F);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 X = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 Y = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 X = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/and_from_nand.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_from_nand();

reg X, Y;
wire F, W;

nand U1(W,X, Y);
nand U2(F, W, W);


initial begin
  $monitor ("X = %b Y = %b F = %b", X, Y, F);
  X = 0;
  Y = 0;
  #1 X = 1;
  #1 Y = 1;
  #1 X = 0; 
  #1 $finish;
end

endmodule
module and_from_nand();


reg X, Y;
wire F, W;

nand U1(W,X, Y);
nand U2(F, W, W);


initial begin
  $monitor ("X = %b Y = %b F = %b", X, Y, F);
  X = 0;
  Y = 0;
  #1 X = 1;
  #1 Y = 1;
  #1 X = 0; 
  #1 $finish;
end

endmodule