data/full_repos/permissive/433621701/generic_RB_array/generic_RB_array.v
data/verilator_xmls/f286a25c-41cd-4fb2-9dca-4e8b4365cf08.xml
module Full_Adder_RB_Four_In(input last_carry, a_old, a_new, b_old, b_new, carry_in, output carry_out, sum);
    wire FA_in0, FA_in1, FA_carry_in, FA_out0, FA_out1, and0_out, and1_out;
    two_in_and_gate and0(.a(a_old), .b(b_new), .z(and0_out));
    two_in_and_gate and1(.a(a_new), .b(b_old), .z(and1_out));
    tri_state tri_0(.a(and0_out), .enable(b_new), .out(FA_in0));
    tri_state tri_1(.a(and1_out), .enable(b_new), .out(FA_in1));
    tri_state tri_2(.a(carry_in), .enable(b_new), .out(FA_carry_in));
    Full_Adder FA(.a(FA_in0), .b(FA_in1), .carry_in(FA_carry_in), .sum(FA_out1), .carry_out(FA_out0));
    mux mux0(.a(last_carry), .b(FA_out0), .select(b_new), .out(carry_out));
    mux mux1(.a(and1_out), .b(FA_out1), .select(b_new), .out(sum));
endmodule
module Full_Adder_RB_Four_In(input last_carry, a_old, a_new, b_old, b_new, carry_in, output carry_out, sum);

    wire FA_in0, FA_in1, FA_carry_in, FA_out0, FA_out1, and0_out, and1_out;
    two_in_and_gate and0(.a(a_old), .b(b_new), .z(and0_out));
    two_in_and_gate and1(.a(a_new), .b(b_old), .z(and1_out));
    tri_state tri_0(.a(and0_out), .enable(b_new), .out(FA_in0));
    tri_state tri_1(.a(and1_out), .enable(b_new), .out(FA_in1));
    tri_state tri_2(.a(carry_in), .enable(b_new), .out(FA_carry_in));
    Full_Adder FA(.a(FA_in0), .b(FA_in1), .carry_in(FA_carry_in), .sum(FA_out1), .carry_out(FA_out0));
    mux mux0(.a(last_carry), .b(FA_out0), .select(b_new), .out(carry_out));
    mux mux1(.a(and1_out), .b(FA_out1), .select(b_new), .out(sum));
endmodule