data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Mux16B2to1.v
data/verilator_xmls/c8691117-f63e-4284-8d4c-aacc81acffd8.xml
module Mux16B2to1(
    input [15:0] aIn,
    input [15:0] bIn,
    input sel,
    output [15:0] dOut
  );
  
  assign dOut[15:0] = (sel) ? bIn [15:0] : aIn [15:0];
  
endmodule
module Mux16B2to1(
    input [15:0] aIn,
    input [15:0] bIn,
    input sel,
    output [15:0] dOut
  );

  
  assign dOut[15:0] = (sel) ? bIn [15:0] : aIn [15:0];
  
endmodule