data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/pulse_gen.v
data/verilator_xmls/dd7f191a-b197-44e2-9ea5-2690923bde60.xml
module pulse_gen(pulse, in, clk);

	output 			pulse;
	input 			in;
	input 			clk;

	reg [1:0]	state;
	reg	pulse;
	
	parameter	IDLE = 2'b0;
	parameter	IN_HIGH = 2'b01;
	parameter	WAIT_LOW = 2'b10;  
	
	initial state = IDLE;
	
	always @ (posedge clk) 
		begin	
			pulse <= 0;
			case (state)
			IDLE: 	if (in == 1'b1) begin
							state <= IN_HIGH;	pulse <= 1'b1; end
						else 
							state <= IDLE; 
			IN_HIGH: if (in == 1'b1) 
							state <= WAIT_LOW;
						else 
							state <= IDLE; 
			WAIT_LOW: if (in == 1'b1) 
							state <= WAIT_LOW;
						 else  
							state <= IDLE;
			default: ;
			endcase
		end
endmodule
module pulse_gen(pulse, in, clk);


	output 			pulse;
	input 			in;
	input 			clk;

	reg [1:0]	state;
	reg	pulse;
	
	parameter	IDLE = 2'b0;
	parameter	IN_HIGH = 2'b01;
	parameter	WAIT_LOW = 2'b10;  
	
	initial state = IDLE;
	
	always @ (posedge clk) 
		begin	
			pulse <= 0;
			case (state)
			IDLE: 	if (in == 1'b1) begin
							state <= IN_HIGH;	pulse <= 1'b1; end
						else 
							state <= IDLE; 
			IN_HIGH: if (in == 1'b1) 
							state <= WAIT_LOW;
						else 
							state <= IDLE; 
			WAIT_LOW: if (in == 1'b1) 
							state <= WAIT_LOW;
						 else  
							state <= IDLE;
			default: ;
			endcase
		end
endmodule