data/full_repos/permissive/528677531/LAB-1/ADDITIONAL/ad1.v
data/verilator_xmls/f7be6fec-9f3a-4d6c-a957-e0e19e532165.xml
module ad1(a,b,c,f1);
input a,b,c;
output f1;
assign f1=(a&~(c))|(b&c)|(~(b)&~(c));
endmodule
module ad1(a,b,c,f1);

input a,b,c;
output f1;
assign f1=(a&~(c))|(b&c)|(~(b)&~(c));
endmodule