data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/FSM_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/FSM_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/FSM_TB.v:12: Cannot find file containing module: \'FSM\'\n    FSM COMP\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/FSM\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/FSM.v\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/FSM.sv\n             FSM\n             FSM.v\n             FSM.sv\n             obj_dir/FSM\n             obj_dir/FSM.v\n             obj_dir/FSM.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FSM_TB(
    );
    reg [1:0] intb;
    reg buttb;

    wire [1:0] outasmtb;
    wire outsratb;
    wire outsrbtb;
    
    FSM COMP
    (
   .in(intb),
   .but(buttb),

   .outasm(outasmtb),
   .outsra(outsratb),
   .outsrb(outsrbtb)
    );
    initial 
        begin

        buttb = 1;
        intb = 2;
        
        #100
        buttb = 0;
        intb = 1;
        
        end 


    
    
    
endmodule
module FSM_TB(
    );

    reg [1:0] intb;
    reg buttb;

    wire [1:0] outasmtb;
    wire outsratb;
    wire outsrbtb;
    
    FSM COMP
    (
   .in(intb),
   .but(buttb),

   .outasm(outasmtb),
   .outsra(outsratb),
   .outsrb(outsrbtb)
    );
    initial 
        begin

        buttb = 1;
        intb = 2;
        
        #100
        buttb = 0;
        intb = 1;
        
        end 


    
    
    
endmodule