data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_hstl_drv.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_hstl_drv.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_hstl_drv.v:91: Unsupported: Verilog 1995 strength specifiers\nassign (pull1, strong0) #1 pad = out;\n        ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_hstl_drv.v:91: Unsupported: Verilog 1995 strength specifiers\nassign (pull1, strong0) #1 pad = out;\n               ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module bw_io_hstl_drv(


   pad, 
   

   sel_data_n, pad_up, pad_dn_l,  por,
   bsr_up, bsr_dn_l,  cbu, cbd, vddo );

output	pad;
input [8:1] cbu;
input [8:1] cbd;
input	sel_data_n;
input	pad_up;
input	pad_dn_l;
input	por;
input	bsr_up;
input	bsr_dn_l;
inout	vddo;

regout;
always @(bsr_dn_l or bsr_up or pad_dn_l or pad_up or por
	 or sel_data_n) begin



   if (por == 1'b1) out = 1'bz;
   else if (por == 1'b0) begin
      if (sel_data_n == 1'b0) begin
	 case ({pad_up, pad_dn_l})
	   2'b00: out = 1'b0;
	   2'b01: out = 1'bz;
	   2'b11: out = 1'b1;
	   default: out = 1'bx;
	 endcase
      end
      else if (sel_data_n == 1'b1) begin
	 case ({bsr_up, bsr_dn_l})
	   2'b00: out = 1'b0;
	   2'b01: out = 1'bz;
	   2'b11: out = 1'b1;
	   default: out = 1'bx;
	 endcase
      end
      else out = 1'bx;
   end
   else out = 1'bx;













end
   
assign (pull1, strong0) #1 pad = out;
   
endmodule
module bw_io_hstl_drv(


   pad, 
   

   sel_data_n, pad_up, pad_dn_l,  por,
   bsr_up, bsr_dn_l,  cbu, cbd, vddo );


output	pad;
input [8:1] cbu;
input [8:1] cbd;
input	sel_data_n;
input	pad_up;
input	pad_dn_l;
input	por;
input	bsr_up;
input	bsr_dn_l;
inout	vddo;

regout;
always @(bsr_dn_l or bsr_up or pad_dn_l or pad_up or por
	 or sel_data_n) begin



   if (por == 1'b1) out = 1'bz;
   else if (por == 1'b0) begin
      if (sel_data_n == 1'b0) begin
	 case ({pad_up, pad_dn_l})
	   2'b00: out = 1'b0;
	   2'b01: out = 1'bz;
	   2'b11: out = 1'b1;
	   default: out = 1'bx;
	 endcase
      end
      else if (sel_data_n == 1'b1) begin
	 case ({bsr_up, bsr_dn_l})
	   2'b00: out = 1'b0;
	   2'b01: out = 1'bz;
	   2'b11: out = 1'b1;
	   default: out = 1'bx;
	 endcase
      end
      else out = 1'bx;
   end
   else out = 1'bx;













end
   
assign (pull1, strong0) #1 pad = out;
   
endmodule