data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_parallel_if.v
data/verilator_xmls/56fd8730-b6b4-4460-b84b-386d2e8684f3.xml
module parallel_if();

reg [3:0] counter;
wire clk,reset,enable, up_en, down_en;

always @ (posedge clk)

if (reset == 1'b0) begin
   counter <= 4'b0000; 
end else begin

  if (enable == 1'b1 && up_en == 1'b1) begin
    counter <= counter + 1'b1;
  end

  if (enable == 1'b1 && down_en == 1'b1) begin
    counter <= counter - 1'b1;
  end 
end  

endmodule
module parallel_if();


reg [3:0] counter;
wire clk,reset,enable, up_en, down_en;

always @ (posedge clk)

if (reset == 1'b0) begin
   counter <= 4'b0000; 
end else begin

  if (enable == 1'b1 && up_en == 1'b1) begin
    counter <= counter + 1'b1;
  end

  if (enable == 1'b1 && down_en == 1'b1) begin
    counter <= counter - 1'b1;
  end 
end  

endmodule