data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_using_if.v
data/verilator_xmls/7ca41483-d630-4296-9400-cd33f15729ca.xml
module  mux_using_if(
din_0      ,
din_1      ,
sel        ,
mux_out
);

input din_0, din_1, sel ;

output mux_out;

reg  mux_out;

always @ (sel or din_0 or din_1)
begin : MUX
  if (sel == 1'b0) begin
      mux_out = din_0;
  end else begin
      mux_out = din_1 ;
  end
end

endmodule
module  mux_using_if(
din_0      ,
din_1      ,
sel        ,
mux_out
);


input din_0, din_1, sel ;

output mux_out;

reg  mux_out;

always @ (sel or din_0 or din_1)
begin : MUX
  if (sel == 1'b0) begin
      mux_out = din_0;
  end else begin
      mux_out = din_1 ;
  end
end

endmodule