data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_8/reg_file.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_8,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_8/reg_file.v\n%Error: Exiting due to 5 error(s)\n'
module reg_file(
	input clock,
	input write_enable,
	input [2:0] write_address,
	input [2:0] read_address,
	input [7:0] write_data,
	output [7:0] read_data
);

	reg [7:0] reg_file [7:0];

	always @(posedge clock )
		if(write_enable)
			reg_file[write_address] <= write_data;
	
	assign read_data = reg_file[read_address];

endmodule
module reg_file(
	input clock,
	input write_enable,
	input [2:0] write_address,
	input [2:0] read_address,
	input [7:0] write_data,
	output [7:0] read_data
);


	reg [7:0] reg_file [7:0];

	always @(posedge clock )
		if(write_enable)
			reg_file[write_address] <= write_data;
	
	assign read_data = reg_file[read_address];

endmodule