data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:341: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.u_pad_9\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:341: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 5 bits.\n                                                                                                                           : ... In instance RightShiftTester.u_pad_38\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:341: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_pad_5\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:341: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 21 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:334: [0:1] Range extract has backward bit ordering, perhaps you wanted [1:0]\n                                                                                                                   : ... In instance RightShiftTester.dut.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:334: Extracting 2 bits from only 1 bit number\n                                                                                                                   : ... In instance RightShiftTester.dut.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:334: Selection index out of range: 2:1 outside 0:0\n                                                                                                                              : ... In instance RightShiftTester.dut.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:334: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:334: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: [0:1] Range extract has backward bit ordering, perhaps you wanted [1:0]\n                                                                                                                   : ... In instance RightShiftTester.dut.u_shr_1\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Extracting 2 bits from only 1 bit number\n                                                                                                                   : ... In instance RightShiftTester.dut.u_shr_1\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Selection index out of range: 2:1 outside 0:0\n                                                                                                                              : ... In instance RightShiftTester.dut.u_shr_1\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_shr_1\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_shr_1\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: [15:18] Range extract has backward bit ordering, perhaps you wanted [18:15]\n                                                                                                                   : ... In instance RightShiftTester.dut.u_shr_3\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Selection index out of range: 21:18 outside 15:0\n                                                                                                                              : ... In instance RightShiftTester.dut.u_shr_3\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_shr_3\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_shr_3\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RightShiftTester/reference/RightShiftTester.v:327: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                           : ... In instance RightShiftTester.dut.u_shr_4\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Error: Exiting due to 5 error(s), 14 warning(s)\n'
module RightShift(
    input clock,
    input reset,
    input io_i,
    input io_j,
    output io_i_shifted,
    output io_j_shifted,
    output io_k_shifted,
    output io_l_shifted,
    output io_m_shifted,
    output io_n_shifted,
    output [15:0] io_o_shifted
);
    wire [15:0] k;
    wire [31:0] o;
    wire T_19;
    SHR_UNSIGNED #(.width(1), .n(1)) u_shr_1 (
        .y(T_19),
        .in(io_i)
    );
    wire T_20;
    SHR_SIGNED #(.width(1), .n(1)) s_shr_2 (
        .y(T_20),
        .in(io_j)
    );
    wire T_21;
    SHR_UNSIGNED #(.width(16), .n(18)) u_shr_3 (
        .y(T_21),
        .in(k)
    );
    wire T_23;
    assign T_23 = 1'h0;
    wire T_25;
    assign T_25 = -1'sh1;
    wire T_27;
    assign T_27 = 1'sh0;
    wire [15:0] T_28;
    SHR_UNSIGNED #(.width(32), .n(16)) u_shr_4 (
        .y(T_28),
        .in(o)
    );
    assign io_i_shifted = T_19;
    assign io_j_shifted = T_20;
    assign io_k_shifted = T_21;
    assign io_l_shifted = 1'h0;
    assign io_m_shifted = -1'sh1;
    assign io_n_shifted = 1'sh0;
    assign io_o_shifted = T_28;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_5 (
        .y(k),
        .in(1'h1)
    );
    PAD_UNSIGNED #(.width(21), .n(32)) u_pad_6 (
        .y(o),
        .in(21'h12D687)
    );
endmodule
module RightShift(
    input clock,
    input reset,
    input io_i,
    input io_j,
    output io_i_shifted,
    output io_j_shifted,
    output io_k_shifted,
    output io_l_shifted,
    output io_m_shifted,
    output io_n_shifted,
    output [15:0] io_o_shifted
);

    wire [15:0] k;
    wire [31:0] o;
    wire T_19;
    SHR_UNSIGNED #(.width(1), .n(1)) u_shr_1 (
        .y(T_19),
        .in(io_i)
    );
    wire T_20;
    SHR_SIGNED #(.width(1), .n(1)) s_shr_2 (
        .y(T_20),
        .in(io_j)
    );
    wire T_21;
    SHR_UNSIGNED #(.width(16), .n(18)) u_shr_3 (
        .y(T_21),
        .in(k)
    );
    wire T_23;
    assign T_23 = 1'h0;
    wire T_25;
    assign T_25 = -1'sh1;
    wire T_27;
    assign T_27 = 1'sh0;
    wire [15:0] T_28;
    SHR_UNSIGNED #(.width(32), .n(16)) u_shr_4 (
        .y(T_28),
        .in(o)
    );
    assign io_i_shifted = T_19;
    assign io_j_shifted = T_20;
    assign io_k_shifted = T_21;
    assign io_l_shifted = 1'h0;
    assign io_m_shifted = -1'sh1;
    assign io_n_shifted = 1'sh0;
    assign io_o_shifted = T_28;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_5 (
        .y(k),
        .in(1'h1)
    );
    PAD_UNSIGNED #(.width(21), .n(32)) u_pad_6 (
        .y(o),
        .in(21'h12D687)
    );
endmodule