data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round_reg.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round_reg.v:29: Little bit endian vector: MSB < LSB of bit range: -1:0\n     input [bits_in-1:0] in,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round_reg.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n     output reg [bits_out-1:0] out);\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round_reg.v:32: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [bits_out-1:0]     temp;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round_reg.v:34: Cannot find file containing module: \'clip_and_round\'\n   clip_and_round #(.bits_in(bits_in),.bits_out(bits_out),.clip_bits(clip_bits))\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip_and_round\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip_and_round.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip_and_round.sv\n             clip_and_round\n             clip_and_round.v\n             clip_and_round.sv\n             obj_dir/clip_and_round\n             obj_dir/clip_and_round.v\n             obj_dir/clip_and_round.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module clip_and_round_reg
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter clip_bits=0)
    (input clk,
     input [bits_in-1:0] in,
     output reg [bits_out-1:0] out);

   wire [bits_out-1:0] 	   temp;

   clip_and_round #(.bits_in(bits_in),.bits_out(bits_out),.clip_bits(clip_bits))
     clip_and_round (.in(in),.out(temp));

   always@(posedge clk)
     out <= temp;
   
endmodule
module clip_and_round_reg
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter clip_bits=0)
    (input clk,
     input [bits_in-1:0] in,
     output reg [bits_out-1:0] out);


   wire [bits_out-1:0] 	   temp;

   clip_and_round #(.bits_in(bits_in),.bits_out(bits_out),.clip_bits(clip_bits))
     clip_and_round (.in(in),.out(temp));

   always@(posedge clk)
     out <= temp;
   
endmodule