data/full_repos/permissive/477054115/iitb-risc/topModuleTB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/477054115/iitb-risc/topModuleTB.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/477054115/iitb-risc/topModuleTB.v:12: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/477054115/iitb-risc/topModuleTB.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477054115/iitb-risc/topModuleTB.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #500 $finish;  \n   ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipelined_processor_tb;

reg clk, reset;

pipelined_processor uut ( clk, reset );

always #10 clk = ~clk;

initial begin 
    $dumpvars();
    clk = 0;
    reset = 1'b1;
 
    #20
    reset = 1'b0;

   #500 $finish;  
 end
 
endmodule
module pipelined_processor_tb;


reg clk, reset;

pipelined_processor uut ( clk, reset );

always #10 clk = ~clk;

initial begin 
    $dumpvars();
    clk = 0;
    reset = 1'b1;
 
    #20
    reset = 1'b0;

   #500 $finish;  
 end
 
endmodule