data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SyzFETFlagReg.v
data/verilator_xmls/a113872e-be93-458c-85d7-0766f262cf70.xml
module SyzFETFlagReg(
    input clockSig,
    input value,
    input [3:0] sel,
    input write,
    input reset,
    output [15:0] dOut
  );
  
  reg [15:0] data = 16'h0000;
  

  wire wBuf;
  buf #(1) (wBuf, value);
  

  always @ (negedge clockSig) begin
    if(reset) begin
      data[15:0] = 16'h0000;
    end else begin
      if(write) begin
        data[sel] = wBuf;
      end
    end
  end
  

  assign dOut[15:0] = {
    data[15], data[14], data[13], data[12],
    data[11], data[10], data[9], data[8],
    data[7], data[6], data[5], data[4],
    data[3], data[2], data[1], data[0]
  };
  
endmodule
module SyzFETFlagReg(
    input clockSig,
    input value,
    input [3:0] sel,
    input write,
    input reset,
    output [15:0] dOut
  );

  
  reg [15:0] data = 16'h0000;
  

  wire wBuf;
  buf #(1) (wBuf, value);
  

  always @ (negedge clockSig) begin
    if(reset) begin
      data[15:0] = 16'h0000;
    end else begin
      if(write) begin
        data[sel] = wBuf;
      end
    end
  end
  

  assign dOut[15:0] = {
    data[15], data[14], data[13], data[12],
    data[11], data[10], data[9], data[8],
    data[7], data[6], data[5], data[4],
    data[3], data[2], data[1], data[0]
  };
  
endmodule