data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_Add_5U_1_4.v
data/verilator_xmls/4dd956cd-a91a-4d83-b208-4eb10fee0912.xml
module dut_Add_5U_1_4 (
	in2,
	in1,
	out1
	);
input [4:0] in2,
	in1;
output [4:0] out1;
wire [4:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_5U_1_4 (
	in2,
	in1,
	out1
	);

input [4:0] in2,
	in1;
output [4:0] out1;
wire [4:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule