data/full_repos/permissive/509809169/Verilog Language/More Verilog Features/Reduction operators.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/More\n             data/full_repos/permissive/509809169/Verilog/Language/More.v\n             data/full_repos/permissive/509809169/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Features/Reduction\n%Error: Cannot find file containing module: operators.v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input [7:0] in,
    output parity); 
	assign parity = ^in;
endmodule
module top_module (
    input [7:0] in,
    output parity);
 
	assign parity = ^in;
endmodule