data/full_repos/permissive/445379100/a4/pc_plus4.v
data/verilator_xmls/6310590c-7c14-4dac-ab2b-707f8e14fa33.xml
module pc_plus4 (
    input[31:0] input_iaddr ,
    output [31:0] out_pc_plus4
);
    assign out_pc_plus4 = input_iaddr + 32'd4 ;

endmodule
module pc_plus4 (
    input[31:0] input_iaddr ,
    output [31:0] out_pc_plus4
);

    assign out_pc_plus4 = input_iaddr + 32'd4 ;

endmodule