data/full_repos/permissive/439731184/ft.v
1: b'%Error: data/full_repos/permissive/439731184/ft.v:196: Unsupported or unknown PLI call: $urandom\n    i1 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:197: Unsupported or unknown PLI call: $urandom\n    i2 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:198: Unsupported or unknown PLI call: $urandom\n    i3 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:199: Unsupported or unknown PLI call: $urandom\n    i4 = $urandom;\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:195: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/ft.v:204: Unsupported or unknown PLI call: $monitor\n    $monitor("(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ft2 #(parameter N_BITS = 4) (a, b, c, d);

input [2*N_BITS-1:0] a, b;
output [2*N_BITS+1:0] c, d;

add #(N_BITS) A(a[N_BITS-1:0], b[N_BITS-1:0], c[N_BITS:0]);
add #(N_BITS) B(a[2*N_BITS-1:N_BITS], b[2*N_BITS-1:N_BITS], c[2*N_BITS+1:N_BITS+1]);
sub #(N_BITS) C(a[N_BITS-1:0], b[N_BITS-1:0], d[N_BITS:0]);
sub #(N_BITS) D(a[2*N_BITS-1:N_BITS], b[2*N_BITS-1:N_BITS], d[2*N_BITS+1:N_BITS+1]);

endmodule
module ft2 #(parameter N_BITS = 4) (a, b, c, d);


input [2*N_BITS-1:0] a, b;
output [2*N_BITS+1:0] c, d;

add #(N_BITS) A(a[N_BITS-1:0], b[N_BITS-1:0], c[N_BITS:0]);
add #(N_BITS) B(a[2*N_BITS-1:N_BITS], b[2*N_BITS-1:N_BITS], c[2*N_BITS+1:N_BITS+1]);
sub #(N_BITS) C(a[N_BITS-1:0], b[N_BITS-1:0], d[N_BITS:0]);
sub #(N_BITS) D(a[2*N_BITS-1:N_BITS], b[2*N_BITS-1:N_BITS], d[2*N_BITS+1:N_BITS+1]);

endmodule