data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:17: Unsupported or unknown PLI call: $monitor\n       $monitor("%b\\t%b\\t%b\\t%b\\t%b\\t%h\\t%h\\t%h\\t%h\\t%h\\t%h\\t", clk, reset, regEn, litEn, memEn, SA, SB, data, lit, A, B);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n       #1 reset=1;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n       #2 reset=0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=1; litEn=0; memEn=0; SA=4\'h0; SB=4\'h1; data=8\'h11; lit=8\'h00;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=0; litEn=0; memEn=0; SA=4\'h3; SB=4\'h0; data=8\'h00; lit=8\'h44;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=1; litEn=0; memEn=0; SA=4\'h1; SB=4\'h0; data=8\'hff; lit=8\'h44;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=0; litEn=0; memEn=0; SA=4\'h0; SB=4\'h1; data=8\'hff; lit=8\'h44;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=1; litEn=1; memEn=0; SA=4\'h0; SB=4\'he; data=8\'hff; lit=8\'h44;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=0; litEn=0; memEn=0; SA=4\'h0; SB=4\'he; data=8\'hff; lit=8\'h44;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=1; litEn=0; memEn=1; SA=4\'h0; SB=4\'hf; data=8\'h88; lit=8\'h00;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n       #2 regEn=0; litEn=0; memEn=0; SA=4\'h0; SB=4\'hf; data=8\'h88; lit=8\'h00;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n       #2 $finish;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/reg_module/top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk=~clk;\n        ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg clk;
    reg reset;
    reg regEn, litEn, memEn;
    reg [3:0] SA, SB;
    reg [7:0] data, lit;
    wire [7:0] A, B;
    wire [12:0] pcAddData;

    reg_module RMOD(clk, reset, regEn, litEn, memEn, SA, SB, data, lit, A, B, pcAddData);

    initial begin
       clk=0; reset=0; regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'h0; data=8'h00; lit=8'h00;

       $display("\nclk\treset\tregEn\tlitEn\tmemEn\tSA\tSB\tdata\tlit\tA\tB");
       $monitor("%b\t%b\t%b\t%b\t%b\t%h\t%h\t%h\t%h\t%h\t%h\t", clk, reset, regEn, litEn, memEn, SA, SB, data, lit, A, B);

       #1 reset=1;
       #2 reset=0;
       #2 regEn=1; litEn=0; memEn=0; SA=4'h0; SB=4'h1; data=8'h11; lit=8'h00;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h3; SB=4'h0; data=8'h00; lit=8'h44;
       #2 regEn=1; litEn=0; memEn=0; SA=4'h1; SB=4'h0; data=8'hff; lit=8'h44;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'h1; data=8'hff; lit=8'h44;

       #2 regEn=1; litEn=1; memEn=0; SA=4'h0; SB=4'he; data=8'hff; lit=8'h44;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'he; data=8'hff; lit=8'h44;

       #2 regEn=1; litEn=0; memEn=1; SA=4'h0; SB=4'hf; data=8'h88; lit=8'h00;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'hf; data=8'h88; lit=8'h00;

       #2 $finish;
    end


    always
    begin
        #2 clk=~clk;
    end

endmodule
module testbench();


    reg clk;
    reg reset;
    reg regEn, litEn, memEn;
    reg [3:0] SA, SB;
    reg [7:0] data, lit;
    wire [7:0] A, B;
    wire [12:0] pcAddData;

    reg_module RMOD(clk, reset, regEn, litEn, memEn, SA, SB, data, lit, A, B, pcAddData);

    initial begin
       clk=0; reset=0; regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'h0; data=8'h00; lit=8'h00;

       $display("\nclk\treset\tregEn\tlitEn\tmemEn\tSA\tSB\tdata\tlit\tA\tB");
       $monitor("%b\t%b\t%b\t%b\t%b\t%h\t%h\t%h\t%h\t%h\t%h\t", clk, reset, regEn, litEn, memEn, SA, SB, data, lit, A, B);

       #1 reset=1;
       #2 reset=0;
       #2 regEn=1; litEn=0; memEn=0; SA=4'h0; SB=4'h1; data=8'h11; lit=8'h00;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h3; SB=4'h0; data=8'h00; lit=8'h44;
       #2 regEn=1; litEn=0; memEn=0; SA=4'h1; SB=4'h0; data=8'hff; lit=8'h44;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'h1; data=8'hff; lit=8'h44;

       #2 regEn=1; litEn=1; memEn=0; SA=4'h0; SB=4'he; data=8'hff; lit=8'h44;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'he; data=8'hff; lit=8'h44;

       #2 regEn=1; litEn=0; memEn=1; SA=4'h0; SB=4'hf; data=8'h88; lit=8'h00;
       #2 regEn=0; litEn=0; memEn=0; SA=4'h0; SB=4'hf; data=8'h88; lit=8'h00;

       #2 $finish;
    end


    always
    begin
        #2 clk=~clk;
    end

endmodule