data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:45: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:46: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:63: Define or directive not defined: \'`SIG_CQ_TUSER_W\'\n     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:75: Define or directive not defined: \'`SIG_FBE_W\'\n     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:76: Define or directive not defined: \'`SIG_LBE_W\'\n     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:77: Define or directive not defined: \'`SIG_TC_W\'\n     output [`SIG_TC_W-1:0]                   RXR_META_TC,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:78: Define or directive not defined: \'`SIG_ATTR_W\'\n     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:79: Define or directive not defined: \'`SIG_TAG_W\'\n     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:80: Define or directive not defined: \'`SIG_TYPE_W\'\n     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:81: Define or directive not defined: \'`SIG_ADDR_W\'\n     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:82: Define or directive not defined: \'`SIG_BARDECODE_W\'\n     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:83: Define or directive not defined: \'`SIG_REQID_W\'\n     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:84: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:88: Define or directive not defined: \'`EXT_TYPE_W\'\n    function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:89: Define or directive not defined: \'`UPKT_TYPE_W\'\n        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:89: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: Define or directive not defined: \'`UPKT_REQ_RD\'\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: Define or directive not defined: \'`TRLS_REQ_RD\'\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:94: Define or directive not defined: \'`UPKT_REQ_WR\'\n                {`UPKT_REQ_WR,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:94: Define or directive not defined: \'`TRLS_REQ_WR\'\n                {`UPKT_REQ_WR,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:95: Define or directive not defined: \'`UPKT_MSG\'\n                {`UPKT_MSG   ,1\'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:95: Define or directive not defined: \'`TRLS_MSG_ND\'\n                {`UPKT_MSG   ,1\'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:96: Define or directive not defined: \'`UPKT_MSG\'\n                {`UPKT_MSG   ,1\'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:96: Define or directive not defined: \'`TRLS_MSG_WD\'\n                {`UPKT_MSG   ,1\'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:97: Define or directive not defined: \'`TRLS_REQ_RD\'\n                default:             upkt_to_trellis_type = `TRLS_REQ_RD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:104: Define or directive not defined: \'`SIG_FBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:104: Define or directive not defined: \'`SIG_LBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:112: Define or directive not defined: \'`UPKT_RXR_ADDRDW0_I\'\n    localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:113: Define or directive not defined: \'`UPKT_RXR_ADDRDW1_I\'\n    localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:114: Define or directive not defined: \'`UPKT_RXR_METADW0_I\'\n    localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:115: Define or directive not defined: \'`UPKT_RXR_METADW1_I\'\n    localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:116: Define or directive not defined: \'`UPKT_RXR_PAYLOAD_I\'\n    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:119: Define or directive not defined: \'`UPKT_RXR_ADDRDW0_I\'\n    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:120: Define or directive not defined: \'`UPKT_RXR_ADDRDW1_I\'\n    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:121: Define or directive not defined: \'`UPKT_RXR_METADW0_I\'\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:122: Define or directive not defined: \'`UPKT_RXR_METADW1_I\'\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:144: Define or directive not defined: \'`SIG_TYPE_W\'\n    wire [`SIG_TYPE_W-1:0]                              wRxrType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:145: Define or directive not defined: \'`SIG_FBE_W\'\n    wire [`SIG_FBE_W-1:0]                               wRxrMetaFdwbe;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:146: Define or directive not defined: \'`SIG_LBE_W\'\n    wire [`SIG_LBE_W-1:0]                               wRxrMetaLdwbe;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:148: Define or directive not defined: \'`SIG_BARDECODE_W\'\n    wire [`SIG_BARDECODE_W-1:0]                         wRxrBarDecoded;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:162: Define or directive not defined: \'`SIG_BARDECODE_W\'\n    wire [`SIG_BARDECODE_W-1:0]                         wBarDecoded;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:165: Define or directive not defined: \'`SIG_TYPE_W\'\n    wire [`SIG_TYPE_W-1:0]                              wType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:168: Define or directive not defined: \'`UPKT_CQ_TUSER_SOP_R\'\n    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];\n                                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:168: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];\n                                                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:171: Define or directive not defined: \'`UPKT_RXR_BARID_R\'\n    assign wBarDecoded = (8\'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);\n                                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:171: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign wBarDecoded = (8\'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);\n                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: Define or directive not defined: \'`UPKT_RXR_LENGTH_I\'\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                                                ^~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: Define or directive not defined: \'`UPKT_RXR_MAXHDR_W\'\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                                                                       ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;
        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;
        begin

            casex(WR_UPKT_TYPE)
                {`UPKT_REQ_RD,1'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;
                {`UPKT_REQ_WR,1'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;
                {`UPKT_MSG   ,1'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;
                {`UPKT_MSG   ,1'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;
                default:             upkt_to_trellis_type = `TRLS_REQ_RD;
            endcase

        end
    endfunction
function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;

        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;
        begin

            casex(WR_UPKT_TYPE)
                {`UPKT_REQ_RD,1'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;
                {`UPKT_REQ_WR,1'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;
                {`UPKT_MSG   ,1'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;
                {`UPKT_MSG   ,1'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;
                default:             upkt_to_trellis_type = `TRLS_REQ_RD;
            endcase

        end
    endfunction