data/full_repos/permissive/427221126/src/FIFO.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/427221126/src/FIFO.v:349: Cell has missing pin: \'LAST\'\n  FIFOsync_ram #(.INWIDTH(INWIDTH), .DEPTH(DEPTH)) U_fifo (\n                                                   ^~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/427221126/src/FIFO.v:277: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                      : ... Top module \'FIFOsync\'\nmodule FIFOsync \n       ^~~~~~~~\n                                                                      : ... Top module \'FIFOpi\'\nmodule FIFOpi \n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:62: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n      if (tail != MAX_COUNT)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:78: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n      if (head != MAX_COUNT)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:98: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n        if (count != DEPTH)\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:104: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                   : ... In instance FIFOpi.U_fifo\n        if (count == DEPTH)  \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:129: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                   : ... In instance FIFOpi.U_fifo\n  assign FULL = (count == DEPTH);\n                       ^~\n%Error: data/full_repos/permissive/427221126/src/FIFO.v:133: Cannot find file containing module: \'RAM2P_WF_RO\'\n  RAM2P_WF_RO #(.DATA_WIDTH(INWIDTH), .ADDR_WIDTH(PTR_WIDTH)) U_fiforam (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO.sv\n             RAM2P_WF_RO\n             RAM2P_WF_RO.v\n             RAM2P_WF_RO.sv\n             obj_dir/RAM2P_WF_RO\n             obj_dir/RAM2P_WF_RO.v\n             obj_dir/RAM2P_WF_RO.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module FIFOpi 
  #(
    parameter INWIDTH = 16,
              INDEPTH = 9,
              DEPTH = INDEPTH * 2 + 1
  ) (
    input CLK,
    input RESET,
    input EN,
    input [INWIDTH*INDEPTH-1:0] DI,
    input                       WRITE,
    output                      WRITING,
    output [INWIDTH-1:0]        DO,
    input                       READ,
    output                      EMPTY,
    output                      FULL
  );
  reg  [INWIDTH-1:0] ishreg [0:INDEPTH-1];
  wire [INWIDTH-1:0] fifo_di;
  reg  [INDEPTH-1:0] iflag;
  reg  [$clog2(INDEPTH+1)-1:0] sr_addr;
  genvar i;
  
  wire fifo_write;

  generate
    for (i = 0; i < INDEPTH; i = i + 1) begin : shift_reg
      always @(posedge CLK) begin
        if (RESET == 1'b1) begin
          ishreg[i] <= {INWIDTH{1'b0}};
        end
        else if (EN) begin
          if (WRITE) begin
            ishreg[i] <= DI[INWIDTH*(i+1)-1:INWIDTH*i];
          end
        end
      end
    end
  endgenerate

  generate
    for (i = 0; i < INDEPTH; i = i + 1) begin : flags
      always @(posedge CLK) begin
        if (RESET == 1'b1) begin
          iflag[i] <= 1'b0;
        end
        else if (EN) begin
          if (WRITE)
            iflag[i] <= 1'b1;
          else if (sr_addr == i && !FULL) 
            iflag[i] <= 1'b0;
        end
      end
    end
  endgenerate

  always @(posedge CLK) begin
    if (RESET == 1'b1) begin
      sr_addr <= 0;
    end
    else if (EN) begin
      if (WRITE)
        sr_addr <= 0;
      else if (WRITING && !FULL)
        if (sr_addr < (INDEPTH-1)) sr_addr <= sr_addr + 1;
        else sr_addr <= 0;
    end
  end
  
  assign fifo_di = ishreg[sr_addr];
  assign fifo_write = iflag[sr_addr];
  
  FIFOsync_ram #(.INWIDTH(INWIDTH), .DEPTH(DEPTH)) U_fifo (
    .CLK(CLK), .RESET(RESET), .EN(EN),
    .DI(fifo_di),
    .WRITE(fifo_write),
    .DO(DO),
    .READ(READ),
    .EMPTY(EMPTY),
    .FULL(FULL)
  );

  assign WRITING = |iflag;
endmodule
module FIFOpi 
  #(
    parameter INWIDTH = 16,
              INDEPTH = 9,
              DEPTH = INDEPTH * 2 + 1
  ) (
    input CLK,
    input RESET,
    input EN,
    input [INWIDTH*INDEPTH-1:0] DI,
    input                       WRITE,
    output                      WRITING,
    output [INWIDTH-1:0]        DO,
    input                       READ,
    output                      EMPTY,
    output                      FULL
  );

  reg  [INWIDTH-1:0] ishreg [0:INDEPTH-1];
  wire [INWIDTH-1:0] fifo_di;
  reg  [INDEPTH-1:0] iflag;
  reg  [$clog2(INDEPTH+1)-1:0] sr_addr;
  genvar i;
  
  wire fifo_write;

  generate
    for (i = 0; i < INDEPTH; i = i + 1) begin : shift_reg
      always @(posedge CLK) begin
        if (RESET == 1'b1) begin
          ishreg[i] <= {INWIDTH{1'b0}};
        end
        else if (EN) begin
          if (WRITE) begin
            ishreg[i] <= DI[INWIDTH*(i+1)-1:INWIDTH*i];
          end
        end
      end
    end
  endgenerate

  generate
    for (i = 0; i < INDEPTH; i = i + 1) begin : flags
      always @(posedge CLK) begin
        if (RESET == 1'b1) begin
          iflag[i] <= 1'b0;
        end
        else if (EN) begin
          if (WRITE)
            iflag[i] <= 1'b1;
          else if (sr_addr == i && !FULL) 
            iflag[i] <= 1'b0;
        end
      end
    end
  endgenerate

  always @(posedge CLK) begin
    if (RESET == 1'b1) begin
      sr_addr <= 0;
    end
    else if (EN) begin
      if (WRITE)
        sr_addr <= 0;
      else if (WRITING && !FULL)
        if (sr_addr < (INDEPTH-1)) sr_addr <= sr_addr + 1;
        else sr_addr <= 0;
    end
  end
  
  assign fifo_di = ishreg[sr_addr];
  assign fifo_write = iflag[sr_addr];
  
  FIFOsync_ram #(.INWIDTH(INWIDTH), .DEPTH(DEPTH)) U_fifo (
    .CLK(CLK), .RESET(RESET), .EN(EN),
    .DI(fifo_di),
    .WRITE(fifo_write),
    .DO(DO),
    .READ(READ),
    .EMPTY(EMPTY),
    .FULL(FULL)
  );

  assign WRITING = |iflag;
endmodule