data/full_repos/permissive/46804359/Shift_left2_32b.v
data/verilator_xmls/ebe0cedd-7958-4c74-8083-1b91dbaa4310.xml
module Shift_left2_32b(in, out, clk);

    input wire [31:0] in;
    input wire clk;

    output reg [31:0] out;

    always@(posedge clk)
    begin
        out <= in << 2;
    end
endmodule
module Shift_left2_32b(in, out, clk);


    input wire [31:0] in;
    input wire clk;

    output reg [31:0] out;

    always@(posedge clk)
    begin
        out <= in << 2;
    end
endmodule