data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/alu.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                        : ... In instance alu\n            4\'b0101 : result = a < b; \n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/alu.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                                                        : ... In instance alu\n            4\'b0110 : result = (((a<b) && (a[31] == b[31] )) ||( ( a[31] == 1 && b[31] == 0))); \n                             ^\n%Error: Exiting due to 2 warning(s)\n'
module alu(
    input [31:0] a,
    input [31:0] b,
    input [3:0] aluc,
    output reg [31:0] result,
    output zero,
    output sign,
    output reg OF,
    output reg CF,
    output PF
    );
    assign zero = result == 0;
    assign sign = result[31];
    assign PF = ~^result;
    always @(a,b,aluc) 
        begin
        CF = 0;OF = 0;
        case(aluc)
            4'b0000 : begin 
                {CF,result} = a + b;
                OF = a[31]==b[31]&&a[31]!=result[31];
            end
            4'b0001 : begin 
                {CF,result} = a - b;
                OF = a[31]!=b[31]&&a[31]!=result[31];
            end
            4'b0010 : result = b << a;
            4'b0011 : result = a | b;
            4'b0100 : result = a & b;
            4'b0101 : result = a < b;
            4'b0110 : result = (((a<b) && (a[31] == b[31] )) ||( ( a[31] == 1 && b[31] == 0)));
            4'b0111 : result = a ^ b;
            4'b1000: result = ~(a | b);
            4'b1001: result = b << 16;
            4'b1010: result = ((b >> a)|({32{b[31]}}<<(32-a)));
            4'b1011: result = b >> a;
            default: result = 0;
        endcase
        end
endmodule
module alu(
    input [31:0] a,
    input [31:0] b,
    input [3:0] aluc,
    output reg [31:0] result,
    output zero,
    output sign,
    output reg OF,
    output reg CF,
    output PF
    );

    assign zero = result == 0;
    assign sign = result[31];
    assign PF = ~^result;
    always @(a,b,aluc) 
        begin
        CF = 0;OF = 0;
        case(aluc)
            4'b0000 : begin 
                {CF,result} = a + b;
                OF = a[31]==b[31]&&a[31]!=result[31];
            end
            4'b0001 : begin 
                {CF,result} = a - b;
                OF = a[31]!=b[31]&&a[31]!=result[31];
            end
            4'b0010 : result = b << a;
            4'b0011 : result = a | b;
            4'b0100 : result = a & b;
            4'b0101 : result = a < b;
            4'b0110 : result = (((a<b) && (a[31] == b[31] )) ||( ( a[31] == 1 && b[31] == 0)));
            4'b0111 : result = a ^ b;
            4'b1000: result = ~(a | b);
            4'b1001: result = b << 16;
            4'b1010: result = ((b >> a)|({32{b[31]}}<<(32-a)));
            4'b1011: result = b >> a;
            default: result = 0;
        endcase
        end
endmodule