data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/AND_Gate_4.v
data/verilator_xmls/71c80ce6-494f-4491-a5eb-b111f355a634.xml
module AND_Gate_4(out, in);
	
	input [3:0] in;
	output out;
	wire and11_out, and12_out;
	

	and and11(and11_out, in[0], in[1]);
	and and12(and12_out, in[2], in[3]);
	and and21(out, and11_out, and12_out);
	
		
endmodule
module AND_Gate_4(out, in);

	
	input [3:0] in;
	output out;
	wire and11_out, and12_out;
	

	and and11(and11_out, in[0], in[1]);
	and and12(and12_out, in[2], in[3]);
	and and21(out, and11_out, and12_out);
	
		
endmodule