data/full_repos/permissive/528912093/Lab1/1-bit-full_adder.v
1: b'%Error: data/full_repos/permissive/528912093/Lab1/1-bit-full_adder.v:43: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 1 error(s)\n'
module full_adder( cin,a,b,S,C);
 input cin,a,b;
 output S,C;
 wire w2,w3,w4,w5,w7,w8,w12,w14;
 wire w15,w16,w17,w18,w19;
 pmos #(1) pmos_1(w3,vdd,w2);
 pmos #(3) pmos_2(w5,w3,w4);
 nmos #(3) nmos_3(w5,vss,w4);
 nmos #(3) nmos_4(w5,vss,w2);
 pmos #(2) pmos_5(C,vdd,w5);
 nmos #(2) nmos_6(C,vss,w5);
 pmos #(2) pmos_7(w8,vdd,w7);
 nmos #(2) nmos_8(w2,vss,w12);
 pmos #(2) pmos_9(w2,vdd,w12);
 pmos #(3) pmos_10(w14,vdd,b);
 nmos #(3) nmos_11(w14,w15,b);
 nmos #(1) nmos_12(w15,vss,a);
 pmos #(3) pmos_13(w14,vdd,a);
 pmos #(2) pmos_14(w4,vdd,w14);
 nmos #(2) nmos_15(w4,vss,w14);
 pmos #(3) pmos_16(w12,vdd,w7);
 nmos #(3) nmos_17(w12,w16,w7);
 nmos #(1) nmos_18(w16,vss,cin);
 pmos #(3) pmos_19(w12,vdd,cin);
 nmos #(2) nmos_20(S,vss,w17);
 pmos #(2) pmos_21(S,vdd,w17);
 nmos #(2) nmos_22(w17,w7,cin);
 pmos #(2) pmos_23(w17,w8,cin);
 nmos #(2) nmos_24(w8,vss,w7);
 nmos #(3) nmos_25(w7,vss,w18);
 pmos #(3) pmos_26(w7,vdd,w18);
 nmos #(2) nmos_27(w18,a,b);
 pmos #(2) pmos_28(w18,w19,b);
 nmos #(2) nmos_29(w19,vss,a);
 pmos #(2) pmos_30(w19,vdd,a);
endmodule
module full_adder( cin,a,b,S,C);

 input cin,a,b;
 output S,C;
 wire w2,w3,w4,w5,w7,w8,w12,w14;
 wire w15,w16,w17,w18,w19;
 pmos #(1) pmos_1(w3,vdd,w2);
 pmos #(3) pmos_2(w5,w3,w4);
 nmos #(3) nmos_3(w5,vss,w4);
 nmos #(3) nmos_4(w5,vss,w2);
 pmos #(2) pmos_5(C,vdd,w5);
 nmos #(2) nmos_6(C,vss,w5);
 pmos #(2) pmos_7(w8,vdd,w7);
 nmos #(2) nmos_8(w2,vss,w12);
 pmos #(2) pmos_9(w2,vdd,w12);
 pmos #(3) pmos_10(w14,vdd,b);
 nmos #(3) nmos_11(w14,w15,b);
 nmos #(1) nmos_12(w15,vss,a);
 pmos #(3) pmos_13(w14,vdd,a);
 pmos #(2) pmos_14(w4,vdd,w14);
 nmos #(2) nmos_15(w4,vss,w14);
 pmos #(3) pmos_16(w12,vdd,w7);
 nmos #(3) nmos_17(w12,w16,w7);
 nmos #(1) nmos_18(w16,vss,cin);
 pmos #(3) pmos_19(w12,vdd,cin);
 nmos #(2) nmos_20(S,vss,w17);
 pmos #(2) pmos_21(S,vdd,w17);
 nmos #(2) nmos_22(w17,w7,cin);
 pmos #(2) pmos_23(w17,w8,cin);
 nmos #(2) nmos_24(w8,vss,w7);
 nmos #(3) nmos_25(w7,vss,w18);
 pmos #(3) pmos_26(w7,vdd,w18);
 nmos #(2) nmos_27(w18,a,b);
 pmos #(2) pmos_28(w18,w19,b);
 nmos #(2) nmos_29(w19,vss,a);
 pmos #(2) pmos_30(w19,vdd,a);
endmodule