data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Lemmings 1.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Lemmings\n%Error: Cannot find file containing module: 1.v\n%Error: Exiting due to 6 error(s)\n'
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right);

    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin

        case(state)
            LEFT: next_state = bump_left ? RIGHT : LEFT;
            RIGHT: next_state = bump_right ? LEFT : RIGHT;
        endcase
    end

    always @(posedge clk, posedge areset) begin

        if(areset)
            state<=LEFT;
        else state<=next_state;
    end


    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);

endmodule
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right);


    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin

        case(state)
            LEFT: next_state = bump_left ? RIGHT : LEFT;
            RIGHT: next_state = bump_right ? LEFT : RIGHT;
        endcase
    end

    always @(posedge clk, posedge areset) begin

        if(areset)
            state<=LEFT;
        else state<=next_state;
    end


    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);

endmodule