data/full_repos/permissive/481044442/BDCDrv/rx_core.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/rx_core.v:33: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance rx_core\n         4\'d13: begin i<=1\'b0; isDone<=1\'b0; rData<=8\'d0; end\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rx_core(clk,reset,H2L_Sig,RXD,Rx_En_Sig,bps_clk,Rx_Data,Rx_Done_Sig);
input clk;
input reset;
input H2L_Sig;
input RXD;
input Rx_En_Sig;
input bps_clk;

output [7:0] Rx_Data;
output Rx_Done_Sig;


reg [3:0] i;

reg [7:0] rData;
reg isDone;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				i<=4'd0;
				rData<=8'd0;
				isDone<=1'b0;
	          end
	else if(Rx_En_Sig) begin
						 case(i)
						 		4'd0: if(H2L_Sig) begin i<=i+1'b1; end
						 		4'd1: if(bps_clk) begin i<=i+1'b1; end
						 		4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
						 			  if(bps_clk) begin i<=i+1'b1;rData[i-2]<=RXD; end  
						 		4'd10: if(bps_clk) begin i<=i+1'b1; end
						 		4'd11: if(bps_clk) begin i<=i+1'b1; end
						 		4'd12: begin i<=i+1'b1; isDone<=1'b1;end 
						 		4'd13: begin i<=1'b0; isDone<=1'b0; rData<=8'd0; end
						 endcase
	     				end
end
assign Rx_Data=rData;
assign Rx_Done_Sig=isDone;
endmodule
module rx_core(clk,reset,H2L_Sig,RXD,Rx_En_Sig,bps_clk,Rx_Data,Rx_Done_Sig);

input clk;
input reset;
input H2L_Sig;
input RXD;
input Rx_En_Sig;
input bps_clk;

output [7:0] Rx_Data;
output Rx_Done_Sig;


reg [3:0] i;

reg [7:0] rData;
reg isDone;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				i<=4'd0;
				rData<=8'd0;
				isDone<=1'b0;
	          end
	else if(Rx_En_Sig) begin
						 case(i)
						 		4'd0: if(H2L_Sig) begin i<=i+1'b1; end
						 		4'd1: if(bps_clk) begin i<=i+1'b1; end
						 		4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
						 			  if(bps_clk) begin i<=i+1'b1;rData[i-2]<=RXD; end  
						 		4'd10: if(bps_clk) begin i<=i+1'b1; end
						 		4'd11: if(bps_clk) begin i<=i+1'b1; end
						 		4'd12: begin i<=i+1'b1; isDone<=1'b1;end 
						 		4'd13: begin i<=1'b0; isDone<=1'b0; rData<=8'd0; end
						 endcase
	     				end
end
assign Rx_Data=rData;
assign Rx_Done_Sig=isDone;
endmodule