data/full_repos/permissive/514437299/digital/rtl/tst.v
1: b'%Error: data/full_repos/permissive/514437299/digital/rtl/tst.v:17: Cannot find include file: tst_params.vh\n  `include "tst_params.vh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/tst_params.vh\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/tst_params.vh.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/tst_params.vh.sv\n             tst_params.vh\n             tst_params.vh.v\n             tst_params.vh.sv\n             obj_dir/tst_params.vh\n             obj_dir/tst_params.vh.v\n             obj_dir/tst_params.vh.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/tst.v:161: Cannot find include file: tst_params.vh\n  `include "tst_params.vh" \n           ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module jtag_reg
  #( parameter DR_LEN = 0,
     parameter IR_OPCODE = 4'b0)(
    input  wire              tck,
    input  wire              tdi,
    output wire              tdo,
    input  wire              rst_n,
    input  wire              state_tlr,
    input  wire              state_capturedr,
    input  wire              state_shiftdr,
    input  wire              state_updatedr,
    input  wire [3:0]        ir_reg,
    input  wire [DR_LEN-1:0] dr_data_in,
    output reg  [DR_LEN-1:0] dr_data_out);

  reg [DR_LEN-1:0] dr_reg;

  assign tdo = dr_reg[0];

  always @(posedge tck or negedge rst_n) begin
    if(!rst_n) begin
      dr_reg      <= {DR_LEN{1'b0}};
      dr_data_out <= {DR_LEN{1'b0}};
    end else begin
      if(state_tlr) 
        dr_reg <= {DR_LEN{1'b0}};
      if(ir_reg == IR_OPCODE) begin
        if(state_capturedr)
          dr_reg <= dr_data_in;
        else if(state_shiftdr) begin
          if(DR_LEN == 1)
            dr_reg <= tdi;
          else 
            dr_reg <= {tdi, dr_reg[DR_LEN-1:1]};
        end else if(state_updatedr) begin
          dr_data_out <= dr_reg;
        end
      end
    end
  end
endmodule
module jtag_reg
  #( parameter DR_LEN = 0,
     parameter IR_OPCODE = 4'b0)(
    input  wire              tck,
    input  wire              tdi,
    output wire              tdo,
    input  wire              rst_n,
    input  wire              state_tlr,
    input  wire              state_capturedr,
    input  wire              state_shiftdr,
    input  wire              state_updatedr,
    input  wire [3:0]        ir_reg,
    input  wire [DR_LEN-1:0] dr_data_in,
    output reg  [DR_LEN-1:0] dr_data_out);


  reg [DR_LEN-1:0] dr_reg;

  assign tdo = dr_reg[0];

  always @(posedge tck or negedge rst_n) begin
    if(!rst_n) begin
      dr_reg      <= {DR_LEN{1'b0}};
      dr_data_out <= {DR_LEN{1'b0}};
    end else begin
      if(state_tlr) 
        dr_reg <= {DR_LEN{1'b0}};
      if(ir_reg == IR_OPCODE) begin
        if(state_capturedr)
          dr_reg <= dr_data_in;
        else if(state_shiftdr) begin
          if(DR_LEN == 1)
            dr_reg <= tdi;
          else 
            dr_reg <= {tdi, dr_reg[DR_LEN-1:1]};
        end else if(state_updatedr) begin
          dr_data_out <= dr_reg;
        end
      end
    end
  end
endmodule