data/full_repos/permissive/443867168/Verilog/CLA_behavioral.v
data/verilator_xmls/aafce491-881c-4e26-9820-923e934f5417.xml
module CLA (

    input [3:0] a,
    input [3:0] b,
    input Cin,


    output reg [3:0] sum,
    output reg Cout

    );

    reg [3:0] carry;

    reg [3:0] p;

    reg [3:0] g;
    
    always @(*) begin


        g[0] = a[0] & b[0];
        g[1] = a[1] & b[1];
        g[2] = a[2] & b[2];
        g[3] = a[3] & b[3];


        p[0] = a[0] ^ b[0];
        p[1] = a[1] ^ b[1];
        p[2] = a[2] ^ b[2];
        p[3] = a[3] ^ b[3];


        carry[0] = (p[0] & Cin) | g[0];
        carry[1] = (p[1] & carry[0]) | g[1];
        carry[2] = (p[2] & carry[1]) | g[2];
        carry[3] = (p[3] & carry[2]) | g[3]; 

        Cout = carry[3];


        sum[0] = p[0] ^ Cin;
        sum[1] = p[1] ^ carry[0];
        sum[2] = p[2] ^ carry[1];
        sum[3] = p[3] ^ carry[2];
        
    end
endmodule
module CLA (

    input [3:0] a,
    input [3:0] b,
    input Cin,


    output reg [3:0] sum,
    output reg Cout

    );


    reg [3:0] carry;

    reg [3:0] p;

    reg [3:0] g;
    
    always @(*) begin


        g[0] = a[0] & b[0];
        g[1] = a[1] & b[1];
        g[2] = a[2] & b[2];
        g[3] = a[3] & b[3];


        p[0] = a[0] ^ b[0];
        p[1] = a[1] ^ b[1];
        p[2] = a[2] ^ b[2];
        p[3] = a[3] ^ b[3];


        carry[0] = (p[0] & Cin) | g[0];
        carry[1] = (p[1] & carry[0]) | g[1];
        carry[2] = (p[2] & carry[1]) | g[2];
        carry[3] = (p[3] & carry[2]) | g[3]; 

        Cout = carry[3];


        sum[0] = p[0] ^ Cin;
        sum[1] = p[1] ^ carry[0];
        sum[2] = p[2] ^ carry[1];
        sum[3] = p[3] ^ carry[2];
        
    end
endmodule