data/full_repos/permissive/521565546/src/bytehex_to_7seg_tb.v
1: b'%Error: data/full_repos/permissive/521565546/src/bytehex_to_7seg_tb.v:43: Unsupported or unknown PLI call: $monitor\n  $monitor("t=%d a=%2h d1=%8b d0=%8b", $time, a, d1, d0);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521565546/src/bytehex_to_7seg_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  a = 8\'h00; #100;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521565546/src/bytehex_to_7seg_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bytehex_to_7seg_tb;


	reg [7:0] a;


	wire [0:7] d1;
	wire [0:7] d0;
	

	bytehex_to_7seg uut (
		.a(a), 
		.d1(d1), 
		.d0(d0)
	);

	initial begin

		$monitor("t=%d a=%2h d1=%8b d0=%8b", $time, a, d1, d0);
		a = 8'h00; #100;
       

		for (a=0; a<256; a=a+1)
			#100;
		
	end
      
endmodule
module bytehex_to_7seg_tb;



	reg [7:0] a;


	wire [0:7] d1;
	wire [0:7] d0;
	

	bytehex_to_7seg uut (
		.a(a), 
		.d1(d1), 
		.d0(d0)
	);

	initial begin

		$monitor("t=%d a=%2h d1=%8b d0=%8b", $time, a, d1, d0);
		a = 8'h00; #100;
       

		for (a=0; a<256; a=a+1)
			#100;
		
	end
      
endmodule