data/full_repos/permissive/500711628/forwarding_unit/forwarding_unit.v
data/verilator_xmls/49723f42-9826-4ca8-950a-1d8339762e6b.xml
function [63:0] f(
		input [15:0] instr0,
		input [15:0] instr1,
		input [15:0] instr2,
		
		input [15:0] rard0,
		input [15:0] rbrd0,
		input [15:0] rard1,
		
		input [15:0] ALUd1,
		input [15:0] memoryd1,
		input [15:0] ALUd2,
		input [15:0] memoryd2
	);
	
		begin
		
			reg [1:0] op10 = instr0[15:14];
			reg [1:0] op11 = instr1[15:14];
			reg [1:0] op12 = instr2[15:14];
			
			reg [3:0] op30 = instr0[7:4];
			reg [3:0] op31 = instr1[7:4];
			reg [3:0] op32 = instr2[7:4];
			
			reg [2:0] rara0 = instr0[13:11];
			reg [2:0] rawa1 = instr1[13:11]; 
			reg [2:0] rawa2 = instr2[13:11]; 
			
			reg [2:0] rbra0 = instr0[10:8];
			reg [2:0] rbwa1 = instr1[10:8];
			reg [2:0] rbwa2 = instr2[10:8]; 
			
			reg isRaWaEq = (rara0 == rawa1);
			reg isRbWaEq = (rbra0 == rawa1);
			
			reg [15:0] rawd1 = (op11 == 2'b00 ?  memoryd1 : 16'h0000);
			reg [15:0] rbwd1 = ( (op11 == 2'b11 & ( (op31 == 4'b0101) | (op31 == 4'b1101) ) ) ? 16'h0000 : ALUd1 );
			reg [15:0] rawd2 = (op12 == 2'b00 ?  memoryd2 : 16'h0000);
			reg [15:0] rbwd2 = ( (op12 == 2'b11 & ( (op32 == 4'b0101) | (op32 == 4'b1101) ) ) ? 16'h0000 : ALUd2 );
			
			reg [15:0] rad0;
			reg [15:0] rbd0; 
			reg [15:0] rad1;
			reg [15:0] ALUout1;
			
		
			if((rarf0 & rawf1) & (rara0 == rawa1)) begin 
				rad0 = rawd1;
			end 
			else if((rarf0 & rbwf1) & (rara0 == rbwa1)) begin 
				rad0 = rbwd1;
			end 
			else if((rarf0 & rawf2) & (rara0 == rawa2)) begin 
				rad0 = rawd2;
			end
			else if((rarf0 & rbwf2) & (rara0 == rbwa2)) begin 
				rad0 = rbwd2;
			end
			else begin
				rad0 = rard0;
			end
			
			
			if((rbrf0 & rbwf1) & (rbra0 == rbwa1)) begin 
				rbd0 = rbwd1;
			end
			else if((rbrf0 & rawf1) & (rbra0 == rawa1)) begin 
				rbd0 = rawd1;
			end
			else if((rbrf0 & rbwf2) & (rbra0 == rbwa2)) begin 
				rbd0 = rbwd2;
			end
			else if((rbrf0 & rawf2) & (rbra0 == rawa2)) begin 
				rbd0 = rawd2;
			end
			else begin
				rbd0 = rbrd0;
			end
			
			
			if( instr1[15:14] == 2'b01 & instr2[15:14] == 2'b00 & (rawa1 == rawa2)) begin 
				rad1 = rawd2;
			end
			else begin
				rad1 = rard1;
			end
			
			if( instr1[15:14] == 2'b11 && instr1[7:4] == 4'b1101 && instr2[15:14] == 2'b00 && (rawa1 == rawa2)) begin 
				ALUout1 = memoryd2;
			end
			else begin
				ALUout1 = ALUd1; 
			end
			
			
			f = {rad0,rbd0,rad1,ALUout1};
			
		end
		
	endfunction
function [63:0] f(
		input [15:0] instr0,
		input [15:0] instr1,
		input [15:0] instr2,
		
		input [15:0] rard0,
		input [15:0] rbrd0,
		input [15:0] rard1,
		
		input [15:0] ALUd1,
		input [15:0] memoryd1,
		input [15:0] ALUd2,
		input [15:0] memoryd2
	);

	
		begin
		
			reg [1:0] op10 = instr0[15:14];
			reg [1:0] op11 = instr1[15:14];
			reg [1:0] op12 = instr2[15:14];
			
			reg [3:0] op30 = instr0[7:4];
			reg [3:0] op31 = instr1[7:4];
			reg [3:0] op32 = instr2[7:4];
			
			reg [2:0] rara0 = instr0[13:11];
			reg [2:0] rawa1 = instr1[13:11]; 
			reg [2:0] rawa2 = instr2[13:11]; 
			
			reg [2:0] rbra0 = instr0[10:8];
			reg [2:0] rbwa1 = instr1[10:8];
			reg [2:0] rbwa2 = instr2[10:8]; 
			
			reg isRaWaEq = (rara0 == rawa1);
			reg isRbWaEq = (rbra0 == rawa1);
			
			reg [15:0] rawd1 = (op11 == 2'b00 ?  memoryd1 : 16'h0000);
			reg [15:0] rbwd1 = ( (op11 == 2'b11 & ( (op31 == 4'b0101) | (op31 == 4'b1101) ) ) ? 16'h0000 : ALUd1 );
			reg [15:0] rawd2 = (op12 == 2'b00 ?  memoryd2 : 16'h0000);
			reg [15:0] rbwd2 = ( (op12 == 2'b11 & ( (op32 == 4'b0101) | (op32 == 4'b1101) ) ) ? 16'h0000 : ALUd2 );
			
			reg [15:0] rad0;
			reg [15:0] rbd0; 
			reg [15:0] rad1;
			reg [15:0] ALUout1;
			
		
			if((rarf0 & rawf1) & (rara0 == rawa1)) begin 
				rad0 = rawd1;
			end 
			else if((rarf0 & rbwf1) & (rara0 == rbwa1)) begin 
				rad0 = rbwd1;
			end 
			else if((rarf0 & rawf2) & (rara0 == rawa2)) begin 
				rad0 = rawd2;
			end
			else if((rarf0 & rbwf2) & (rara0 == rbwa2)) begin 
				rad0 = rbwd2;
			end
			else begin
				rad0 = rard0;
			end
			
			
			if((rbrf0 & rbwf1) & (rbra0 == rbwa1)) begin 
				rbd0 = rbwd1;
			end
			else if((rbrf0 & rawf1) & (rbra0 == rawa1)) begin 
				rbd0 = rawd1;
			end
			else if((rbrf0 & rbwf2) & (rbra0 == rbwa2)) begin 
				rbd0 = rbwd2;
			end
			else if((rbrf0 & rawf2) & (rbra0 == rawa2)) begin 
				rbd0 = rawd2;
			end
			else begin
				rbd0 = rbrd0;
			end
			
			
			if( instr1[15:14] == 2'b01 & instr2[15:14] == 2'b00 & (rawa1 == rawa2)) begin 
				rad1 = rawd2;
			end
			else begin
				rad1 = rard1;
			end
			
			if( instr1[15:14] == 2'b11 && instr1[7:4] == 4'b1101 && instr2[15:14] == 2'b00 && (rawa1 == rawa2)) begin 
				ALUout1 = memoryd2;
			end
			else begin
				ALUout1 = ALUd1; 
			end
			
			
			f = {rad0,rbd0,rad1,ALUout1};
			
		end
		
	endfunction