data/full_repos/permissive/514217463/core/rtl/clk_divn.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514217463/core/rtl/clk_divn.v:37: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'clk_divn_even\'\nmodule clk_divn_even (\n       ^~~~~~~~~~~~~\n                                                                              : ... Top module \'clk_divn_odd\'\nmodule clk_divn_odd (\n       ^~~~~~~~~~~~\n                                                                              : ... Top module \'clk_div\'\nmodule clk_div (\n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module clk_divn_even (
  input clk, 
  input reset, 
  output clk_out
);

  parameter WIDTH = 3;
  parameter N = 6;

  reg [WIDTH-1:0] r_reg;
  wire [WIDTH-1:0] r_nxt;
  reg clk_track;

  always @(posedge clk or posedge reset)

    begin
      if (reset)
        begin
          r_reg <= 0;
          clk_track <= 1'b0;
        end

      else if (r_nxt == N)
        begin
          r_reg <= 0;
          clk_track <= ~clk_track;
        end

      else 
        r_reg <= r_nxt;
    end

  assign r_nxt = r_reg + 1;   	      
  assign clk_out = clk_track;
endmodule
module clk_divn_even (
  input clk, 
  input reset, 
  output clk_out
);


  parameter WIDTH = 3;
  parameter N = 6;

  reg [WIDTH-1:0] r_reg;
  wire [WIDTH-1:0] r_nxt;
  reg clk_track;

  always @(posedge clk or posedge reset)

    begin
      if (reset)
        begin
          r_reg <= 0;
          clk_track <= 1'b0;
        end

      else if (r_nxt == N)
        begin
          r_reg <= 0;
          clk_track <= ~clk_track;
        end

      else 
        r_reg <= r_nxt;
    end

  assign r_nxt = r_reg + 1;   	      
  assign clk_out = clk_track;
endmodule