data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:274: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h21\' generates 8 bits.\n                                                                                             : ... In instance processor\n    i2c_addr=8\'h21;  \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:289: Bit extraction of array[9:0] requires 4 bit index, not 8 bits.\n                                                                                             : ... In instance processor\n    extradata[bytesread] = rxData;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:455: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     ext_trig_delay = extradata[0];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:511: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                                             : ... In instance processor\n     else getadcadr<=(readdata-110); \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:522: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     nsamp=256*extradata[0]+extradata[1];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:533: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     triggerpoint=256*extradata[0]+extradata[1];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:545: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     nsmp=256*extradata[0]+extradata[1];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     sendincrement=extradata[0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:605: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     triggertype=extradata[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:615: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     triggertot=256*extradata[0]+extradata[1];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:678: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n                                                                                             : ... In instance processor\n     i2c_addr=8\'h20;  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:696: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);  \n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:709: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     i2c_datacounttosend=extradata[0]; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:710: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     i2c_addr=extradata[1];  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:734: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     lockinnumtoshift = 256*extradata[0]+extradata[1];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:766: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n                                                                                             : ... In instance processor\n     i2c_addr=8\'h20;  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:817: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     blockstosend = extradata[0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:827: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     i2c_addr=extradata[0];  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:892: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                             : ... In instance processor\n     nselftrigcoincidentreq = extradata[0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:943: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                             : ... In instance processor\n    thecounterbit=thecounter[clockbitstowait];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:944: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                             : ... In instance processor\n    thecounterbitlockin=thecounter[clockbitstowaitlockin];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:980: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                             : ... In instance processor\n     chan2mean = chan2mean + ram_output3;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:981: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                             : ... In instance processor\n     chan3mean = chan3mean + ram_output4;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:992: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:992: Operator SUB expects 32 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:992: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);  \n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:992: Operator SUB expects 32 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);  \n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:991: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:991: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:998: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:998: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                             : ... In instance processor\n      lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:997: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:997: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1007: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'rdaddress_slow\' generates 12 bits.\n                                                                                              : ... In instance processor\n   if (SendCount[ram_width+1:ram_width]==1) rdadtwo_slow=rdaddress_slow-lockinnumtoshift;\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1007: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n                                                                                              : ... In instance processor\n   if (SendCount[ram_width+1:ram_width]==1) rdadtwo_slow=rdaddress_slow-lockinnumtoshift;\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:976: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                             : ... In instance processor\n   if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1016: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1059: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n    thecounterbit=thecounter[clockbitstowait];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1080: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin  \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1122: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                              : ... In instance processor\n       if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress_slow - wraddress_triggerpoint - 64]=(63-txData[7:2]); \n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1100: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if( thecounter[clockbitstowait]==thecounterbit ) begin\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1134: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n    thecounterbit=thecounter[clockbitstowait];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1152: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin  \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1172: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin  \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1213: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n     thecounterbit=thecounter[clockbitstowait];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1210: Operator GTE expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 11 bits.\n                                                                                              : ... In instance processor\n    if (writesamp>=(nsamp-1)) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1226: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                              : ... In instance processor\n    if (writebyte) txData=adcramdata[11:8];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1225: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n   if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1242: Operator GT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 11 bits.\n                                                                                              : ... In instance processor\n    if (writesamp>(nsamp-1)) state=READ;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1251: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                              : ... In instance processor\n          txData = data[ioCount];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1410: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                              : ... In instance processor\n    i2c_datawr = i2cdata[i2c_datacount];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1448: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                                              : ... In instance processor\n    if (columndata[2:0]>b) screendata[b]=1; \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1448: Operator GT expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                              : ... In instance processor\n    if (columndata[2:0]>b) screendata[b]=1; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1444: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'row\' generates 3 bits.\n                                                                                              : ... In instance processor\n  if (columndata>=8*(row+1)) screendata = 8\'hff;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1459: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                              : ... In instance processor\n   if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1462: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                              : ... In instance processor\n   if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n           ^~\n%Warning-UNSIGNED: data/full_repos/permissive/436884973/max10_adc_firmware/serialprocessor.v:1121: Comparison is constant due to unsigned arithmetic\n                                                                                                 : ... In instance processor\n      if ( (rdaddress_slow-wraddress_triggerpoint-64)>=0 && (rdaddress_slow-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin  \n                                                     ^~\n%Error: Exiting due to 57 warning(s)\n'
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,debug3,debug4,spare,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug, 
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror,   usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdadtwo,trigthreshtwo, debug1,debug2,chip_id, highres,  use_ext_trig,  digital_buffer1, nsmp, outputclk,
phasecounterselect,phaseupdown,phasestep,scanclk,
ext_trig_delay, noselftrig, usb_oe, usb_rd, usb_rxf, usb_pwrsv, clk_rd,
nselftrigcoincidentreq, selftrigtempholdtime, allowsamechancoin
);
   input clk;
	input[7:0] rxData;
   input rxReady;
   input txBusy;
   output reg txStart;
   output reg[7:0] txData;
   output reg[7:0] readdata;
   output wire spare,debug3,debug4;
	reg led1,led2,led3,led4;
	reg io1,io2,io3,io4;
  	output reg get_ext_data;
	input ext_data_ready;
	parameter ram_width=12;
	input wire[ram_width-1:0] wraddress_triggerpoint;
	output wire [ram_width-1:0] rdaddress;
	output wire [ram_width-1:0] rdadtwo;
	reg [ram_width-1:0] rdaddress_slow;
	reg [ram_width-1:0] rdadtwo_slow;
	reg [ram_width-1:0] rdaddress_fast;

	output reg [ram_width-1:0] triggerpoint;
	output reg rden=0;
	input wire [7:0] ram_output1;
	input wire [7:0] ram_output2;
	input wire [7:0] ram_output3;
	input wire [7:0] ram_output4;
	input wire [7:0] digital_buffer1;
	output reg serial_passthrough;
	output reg [1:0] master_clock;
	output reg[7:0] comdata;
	output reg newcomdata;
	output reg imthelast;
	output wire imthefirst;
	output reg rollingtrigger;
	input trigDebug;
	input [11:0] adcdata;
	input adcready;
	input adcvalid;
	output reg getadcdata;
	output reg [4:0] getadcadr;
	output reg adcreset;
	output reg [10:0] writesamp;
	output reg writeadc;
	output reg [11:0] adctestout;
	output reg [7:0] downsample;
	output reg [7:0] screendata;
	output reg screenwren=0;
	output reg [9:0] screenaddr = 10'd0;
	output reg screenreset=0;
	output reg [7:0] trigthresh = 8'h80, trigthreshtwo=8'hff;
	output reg [3:0] trigchannels = 4'b1111;
	output reg [3:0] triggertype = 4'b0001;
   output reg [ram_width:0] triggertot;
	output reg [15:0] SPIsenddata;
	output reg SPIsend;
	input [7:0] delaycounter;
	input [7:0] carrycounter;
	input [3:0] SPIstate;
	output wire[3:0] offset;
	output reg[3:0] gainsw;
	reg[3:0] oversamp;
	output wire debug1,debug2;
	input [63:0] chip_id;
	output reg highres=0;
	output reg use_ext_trig=0;
	output reg outputclk=1;
	output reg[4:0] ext_trig_delay=0;
	output reg noselftrig=0;
	output reg[1:0] nselftrigcoincidentreq=0;
	output reg[7:0] selftrigtempholdtime=10;
	output reg allowsamechancoin=0;
	
	output reg i2c_ena;
	output reg [6:0] i2c_addr;
	output reg i2c_rw;
	output reg [7:0] i2c_datawr;
	input [7:0] i2c_datard;
	input i2c_busy;
	input i2c_ackerror;
	reg [7:0] i2cdata[8];
	reg [3:0] i2c_datacounttosend,i2c_datacount;
	reg i2cgo=0;
	reg i2cdoread=0;

  localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9, 
	WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
	WRITE_USBFAST_EXT1=16, WRITE_USBFAST_EXT2=17,
	LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
	WRITE_USB_EXT1=24, WRITE_USB_EXT2=25, WRITE_USB_EXT3=26, WRITE_USB_EXT4=27, WRITE_USB_EXT5=28,
	PLLCLOCK=30;
  reg[4:0] state,i2cstate;

  reg [7:0] myid;
  assign imthefirst = (myid==0);
  reg [7:0] extradata[10];
  reg [ram_width+2:0] SendCount=0;
  reg [2:0] blockstosend=4;
  reg [15:0] nsamp = 6;
  input [11:0] adcramdata;
  reg writebyte;
  reg[7:0] bytesread, byteswanted;
  reg thecounterbit, thecounterbitlockin;
  reg [7:0] clockbitstowait=5, clockbitstowaitlockin=3;
  reg [3:0] sendincrement = 0;
  output reg [ram_width-1:0] nsmp = 0;
  reg [7:0] chanforscreen=0;
  reg autorearm=0;
  integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
  reg[4:0] serialdelaycounter=0;
  reg addonetoextradata=0;
  
  output wire clk_rd;
  reg [7:0] usb2counter;
  output reg do_usb=0;
  input usb_clk60;
  output wire [7:0] usb_dataio;
  reg [7:0] usb_dataio_slow;
  reg [7:0] usb_dataio_fast;

  input usb_txe_busy;
  reg usb_txe_not_busy;
  output reg usb_oe=1;
  output reg usb_rd=1;
  input usb_rxf;
  output reg usb_pwrsv=1;
  output wire usb_wr, usb_siwu;
  reg usb_wr_slow, usb_siwu_slow;
  reg usb_wr_fast, usb_siwu_fast;
  reg checkfastusbwriting=0;
  

  reg [5:0] screencolumndata [128];
  

  reg[7:0] ioCount, ioCountToSend;
  reg[7:0] data[0:15];
  

  reg [7:0] numlockinbytes=16;
  integer lockinresult1;
  integer lockinresult2;
  reg [15:0] lockinnumtoshift = 0;
  reg [31:0] chan2mean, chan3mean;
  reg calcmeans;
  

  reg[7:0] pllclock_counter=0;
  reg[7:0] scanclk_cycles=0;
  output reg[2:0] phasecounterselect;
  output reg phaseupdown=1;
  output reg phasestep=0;
  output reg scanclk=0;
  
  initial begin
    state<=READ;
	 i2cstate<=READ;
	 usb2state<=USBFAST_IDLE;
	 myid<=200;
	 master_clock<=2'b00;
	 imthelast<=0;
	 rollingtrigger<=1;
	 triggerpoint<=(2**(ram_width-2));
	 downsample<=1;
	 serial_passthrough<=0;
	 usb_siwu_slow<=1;
	 gainsw<=4'b0000;
	 oversamp<=4'b0011;
	 led1<=1;
	 led2<=1;
	 led3<=1;
	 led4<=1;
	 io1<=0;
	 io2<=0;
	 io3<=0;
	 io4<=0;
  end
  

  always @(posedge clk) begin
	thecounter<=thecounter+1;
   if (thecounter[26]==1'b1 ) begin
		if (imthelast) begin
			led1<=0;		led2<=0;		led3<=0;
		end
		else if (myid==0) begin
			led1<=0;		led2<=0;
		end
		else begin
			led1<=0;
		end
	end
	else begin
		if (imthelast) begin
			led1<=1;		led2<=1;		led3<=1;
		end
		else if (myid==0) begin
			led1<=1;		led2<=1;
		end
		else begin
			led1<=1;
		end
	end
	if (thecounter[24]==1'b1 ) begin
		io3 <= 0;
	end
	else begin
		io3 <= 1;
	end
  end
  reg oldled1,oldled2,oldled3,oldled4,oldio1,oldio2,oldio3,oldio4;
  




















  
  always @(posedge clk) begin
    usb_txe_not_busy <= ~usb_txe_busy;
    case (state)
	 
      READ: begin
		  get_ext_data<=0;
		  adcreset<=1;
		  txStart<=0;
		  getadcdata<=0;
		  bytesread<=0;
		  byteswanted<=0;
		  newcomdata<=0;
		  SPIsend<=0;
		  i2cgo=0;
		  usb_wr_slow<=1;
        ioCount = 0;
		  send_fast_usb2=0;
		  addonetoextradata=0;
		  serialdelaycounter=0;
        if (rxReady) begin
			 readdata = rxData;
          state = SOLVING;
        end
		  if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldio1!=io1 || oldio2!=io2 || oldio3!=io3 || oldio4!=io4) begin
			 oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
			 oldio1=io1; oldio2=io2; oldio3=io3; oldio4=io4;

			 i2c_datacounttosend=2;
			 i2c_addr=8'h21;
			 i2cdata[0]=8'h12;
			 i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
			 i2cdata[1][4]=io1; i2cdata[1][5]=io2; i2cdata[1][6]=io3; i2cdata[1][7]=io4;
			 i2cdata[2]=0;
			 if (i2cstate==READ) begin
			   i2cdoread = 0;
				i2cgo=1;
			 end
		  end
      end
		
		READMORE: begin
			newcomdata=0;
			if (rxReady) begin
				extradata[bytesread] = rxData;
				if (addonetoextradata) comdata=rxData+1;
				else comdata=rxData;
				newcomdata=1;
				bytesread = bytesread+1;
				if (bytesread>=byteswanted) state=SOLVING;
			end
		end

      SOLVING: begin
			if (readdata < 10) begin
				myid=readdata;
				if (readdata==0) begin
					master_clock=2'b00;
				end
				else master_clock=2'b01;
				comdata=(readdata+1);
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 9 && readdata < 20) begin
				if (myid==(readdata-10)) begin

					serial_passthrough=0;
					timeoutcounter=0;
					state=WAITING;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
			end
			else if (readdata > 19 && readdata < 30) begin
				if (myid==(readdata-20)) begin
					imthelast=1;
					outputclk=0;
				end
				else begin
					imthelast=0;
					outputclk=1;
				end
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 29 && readdata < 40) begin
				if (myid==(readdata-30)) begin

					serial_passthrough=0;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
				end
				state=READ;
			end
			

			
			else if (readdata==50) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				addonetoextradata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					myid=extradata[0];
					if (extradata[0]==0) begin
						master_clock=2'b00;
					end
					else master_clock=2'b01;
					state=READ;
				end
			end
			else if (readdata==51) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0] || extradata[0]==255) begin

						serial_passthrough=0;
						timeoutcounter=0;
						state=WAITING;
					end
					else begin


							serial_passthrough=1;

						state=READ;
					end
				end
			end
			else if (readdata==52) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0]) begin
						imthelast=1;
						outputclk=0;
					end
					else begin
						imthelast=0;
						outputclk=1;
					end
					state=READ;
				end
			end
			else if (readdata==53) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0]) begin

						serial_passthrough=0;
					end
					else begin


							serial_passthrough=1;

					end
					state=READ;
				end
			end
			
			else if (54==readdata) begin
				if (imthelast) outputclk = ~outputclk;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (55==readdata) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					phasecounterselect=3'b000;

					scanclk=1'b0;
					phasestep=1'b1;
					pllclock_counter=0;
					scanclk_cycles=0;
					state=PLLCLOCK;
				end
			end
			
			else if (readdata==56) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					ext_trig_delay = extradata[0];
					state=READ;
				end
			end
			else if (57==readdata) begin
				noselftrig=~noselftrig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (58==readdata) begin
				do_fast_usb=~do_fast_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (59==readdata) begin
				checkfastusbwriting=~checkfastusbwriting;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end			
			
			else if (100==readdata) begin

				get_ext_data=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (101==readdata) begin

				io1=1;
				rollingtrigger=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (102==readdata) begin

				io1=0;
				rollingtrigger=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (readdata>109 && readdata<120) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					if (readdata==119) getadcadr<=17;
					else getadcadr<=(readdata-110);
					writesamp<=0;
					state=WAIT_ADC1;
				end
			end
			else if (readdata==120) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsamp=256*extradata[0]+extradata[1];
					if (nsamp>4095) nsamp=4095;
					state=READ;
				end
			end
			else if (readdata==121) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggerpoint=256*extradata[0]+extradata[1];
					if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
					else if (triggerpoint<4) triggerpoint=4;
					state=READ;
				end
			end
			else if (readdata==122) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsmp=256*extradata[0]+extradata[1];
					if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
					state=READ;
				end
			end
			else if (readdata==123) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					sendincrement=extradata[0];
					state=READ;
				end
			end
			else if (readdata==124) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>22) extradata[0]=22;
					downsample=extradata[0];
					clockbitstowaitlockin = extradata[0]-2;
					state=READ;
				end
			end
			else if (readdata==125) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					clockbitstowait=extradata[0];
					state=READ;
				end
			end
			else if (readdata==126) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					chanforscreen=extradata[0];
					state=READ;
				end
			end
			
			else if (readdata==127) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh=extradata[0];
					state=READ;
				end
			end
			else if (readdata==128) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertype=extradata[0];
					state=READ;
				end
			end
			else if (readdata==129) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertot=256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (readdata==130) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
					end
					state=READ;
				end
			end
			else if (readdata==131) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					SPIsenddata[15:8]=extradata[0];
					SPIsenddata[7:0]=extradata[1];
					SPIsenddata[15]=1'b0;
					SPIsend=1;
					state=SPIWAIT;
				end
			end
			else if (readdata==132) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=delaycounter;
					state=WRITE1;
				end
			end
			else if (readdata==133) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=carrycounter;
					state=WRITE1;
				end
			end
			else if (readdata==134) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (readdata==135) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
					state=READ;
				end
			end
			else if (readdata==136) begin
				byteswanted=6;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin



					i2c_datacounttosend=extradata[0];
					i2c_addr=extradata[1];
					i2cdata[0]=extradata[2];
					i2cdata[1]=extradata[3];
					i2cdata[2]=extradata[4];
					if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (137==readdata) begin

				do_usb=~do_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==138) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					lockinnumtoshift = 256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (139==readdata) begin

				autorearm=~autorearm;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==140) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthreshtwo = extradata[0];
					state=READ;
				end
			end
			else if (readdata==141) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end			
			else if (readdata==142) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					data[0]=chip_id[7+8*0:8*0];
					data[1]=chip_id[7+8*1:8*1];
					data[2]=chip_id[7+8*2:8*2];
					data[3]=chip_id[7+8*3:8*3];
					data[4]=chip_id[7+8*4:8*4];
					data[5]=chip_id[7+8*5:8*5];
					data[6]=chip_id[7+8*6:8*6];
					data[7]=chip_id[7+8*7:8*7];
					ioCountToSend = 8;
					state=WRITE1;
				end
			end
			else if (143==readdata) begin

				highres=~highres;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (144==readdata) begin

				use_ext_trig=~use_ext_trig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==145) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					blockstosend = extradata[0];
					state=READ;
				end
			end
			else if (readdata==146) begin
				byteswanted=3;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					i2c_addr=extradata[0];
					i2c_datacounttosend=2;
					i2cdata[0]=extradata[1];
					i2cdata[1]=0;
					if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
						i2cdoread = 1;
						i2cgo=1;

						ioCountToSend = 1;
						data[0] = i2c_datard;
						state=WRITE1;
					end
					else state=READ;
				end
			end
			else if (readdata==147) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=21;
					state=WRITE1;
				end
				

				rden=0;
				trigthresh = 8'h80;
				trigthreshtwo=8'hff;
				trigchannels = 4'b1111;
				triggertype = 4'b0001;   
				highres=0;
				use_ext_trig=0;
				ext_trig_delay=0;
				noselftrig=0;
				SendCount=0;
				blockstosend=4;
				nsamp = 6;
				clockbitstowait=5;
				sendincrement = 0;
				nsmp = 0;
				chanforscreen=0;
				autorearm=0;
				do_usb=0;
				checkfastusbwriting=0;
				rollingtrigger=1;
				triggerpoint=(2**(ram_width-2));
				downsample=1;
				gainsw=4'b0000;
				oversamp=4'b0011;
				send_fast_usb2=0;
				do_fast_usb=0;
				usbdonecounterslow=0;
				nselftrigcoincidentreq=0;
				selftrigtempholdtime=10;
				allowsamechancoin=0;
			end
			else if (readdata==148) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nselftrigcoincidentreq = extradata[0];
					state=READ;
				end
			end
			else if (readdata==149) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					selftrigtempholdtime = extradata[0];
					state=READ;
				end
			end
			else if (150==readdata) begin

				allowsamechancoin=~allowsamechancoin;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end			
			
			else state=READ;
      end
		
		SPIWAIT: begin
			newcomdata<=0;

			if (SPIstate==3) begin 
				state=READ;
			end
		end
		
		PLLCLOCK: begin
			pllclock_counter=pllclock_counter+1;
			if (pllclock_counter[4]) begin
				scanclk = ~scanclk;
				pllclock_counter=0;
				scanclk_cycles=scanclk_cycles+1;
				if (scanclk_cycles>5) phasestep=1'b0;
				if (scanclk_cycles>7) state=READ;
			end
		end
		
		WAITING: begin
			newcomdata<=0;
			timeoutcounter=timeoutcounter+1;
			if (ext_data_ready) begin
				SendCount= 0;
				rdaddress_slow = wraddress_triggerpoint - triggerpoint;
				rdadtwo_slow = rdaddress_slow;
				thecounterbit=thecounter[clockbitstowait];
				thecounterbitlockin=thecounter[clockbitstowaitlockin];
				if (lockinnumtoshift>0) begin
					lockinresult1=0;
					lockinresult2=0;
					chan2mean=0;
					chan3mean=0;
					calcmeans=1;
					state=LOCKIN1;
				end
				else begin
					if (do_usb) begin
						if (do_fast_usb) begin
							if (checkfastusbwriting) begin
								do_usb<=0;
								state=WRITE_EXT1;
							end
							else state=WRITE_USBFAST_EXT1;
						end
						else state=WRITE_USB_EXT1;
					end
					else state=WRITE_EXT1;
				end
			end
			if ( timeoutcounter > 100000000 ) begin
				state=READ;



			end
		end
		LOCKIN1: begin
			rden = 1;
			if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
			case(SendCount[ram_width+1:ram_width])
				0: begin

					chan2mean = chan2mean + ram_output3;
					chan3mean = chan3mean + ram_output4;
				end
				1: begin
					if (calcmeans) begin
						calcmeans=0;
						chan2mean = chan2mean/4096;
						chan3mean = chan3mean/4096;
					end


					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);
					end
				end
				2: begin

					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				3: begin
						
				end
			endcase			
			SendCount = SendCount + 1;
			rdaddress_slow = rdaddress_slow + 1;
			if (SendCount[ram_width+1:ram_width]==1) rdadtwo_slow=rdaddress_slow-lockinnumtoshift;
			else rdadtwo_slow=rdaddress_slow;
			state=LOCKIN2;
			end
		end
		LOCKIN2: begin	
			state=LOCKIN3;
		end
		LOCKIN3: begin
			if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
			if(SendCount[ram_width+1:0]==0) begin
				ioCount = 0;
				SendCount = 0;
				state=LOCKINWRITE1;
			end
			else begin
				state=LOCKIN1;
			end
			end
		end
		LOCKINWRITE1: begin
       if (!txBusy) begin
          if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
          else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
          else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
          else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
          else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
          else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
          else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
          else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];			 
			 else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
          else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
          else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
          else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
			 else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
          else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
          else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
          else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
			 else txData = 0;
          txStart = 1;
          state = LOCKINWRITE2;
        end
      end
      LOCKINWRITE2: begin
        txStart = 0;
        if (ioCount < numlockinbytes-1) begin
          ioCount = ioCount + 1;
          state = LOCKINWRITE1;
        end
		  else begin
				rdaddress_slow = wraddress_triggerpoint - triggerpoint;
				rdadtwo_slow = rdaddress_slow;
				thecounterbit=thecounter[clockbitstowait];
				if (do_usb) begin
					if (do_fast_usb) begin
						state=WRITE_USBFAST_EXT1;
					end
					else state=WRITE_USB_EXT1;
				end
				else state=WRITE_EXT1;
        end
      end
		WRITE_EXT1: begin
			timeoutcounter=timeoutcounter+1;
			rden = 1;

			case(SendCount[ram_width+2:ram_width])
			0: txData<=ram_output1;
			1: txData<=ram_output2;
			2: txData<=ram_output3;
			3: txData<=ram_output4;
			4: txData<=digital_buffer1;
			endcase
			if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				txStart<= 1;				
				serialdelaycounter=serialdelaycounter+1;
				SendCount = SendCount + (2**sendincrement);
				rdaddress_slow = rdaddress_slow + (2**sendincrement);
				rdadtwo_slow = rdaddress_slow;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress_slow = wraddress_triggerpoint - triggerpoint;
					rdadtwo_slow = rdaddress_slow;
				end
				state=WRITE_EXT2;
			end
			if ( timeoutcounter > 100000000 ) begin
				rden = 0;
				state=READ;
			end
		end
		WRITE_EXT2: begin
			if( thecounter[clockbitstowait]==thecounterbit ) begin
				txStart<= 0;
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					if (!checkfastusbwriting) begin
						rden = 0;
						if (autorearm) begin

							get_ext_data=1;
						end
						state=READ;
					end
					else begin
						do_usb<=1;
						state=WRITE_USBFAST_EXT1;
					end
				end
				else begin					
					if(serialdelaycounter==0 && serialdelaytimer<serialdelaytimerwait) begin
						serialdelaytimer=serialdelaytimer+1;
					end
					else begin
						if ( (rdaddress_slow-wraddress_triggerpoint-64)>=0 && (rdaddress_slow-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
							if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress_slow - wraddress_triggerpoint - 64]=(63-txData[7:2]);
							screenwren = 1;
						end
						serialdelaytimer=0;
						state=WRITE_EXT1;
					end
				end
			end
		end
		
		WRITE_USB_EXT1: begin
			if (usb_txe_not_busy) begin
				thecounterbit=thecounter[clockbitstowait];
				usb2counter<=0;
				state=WRITE_USB_EXT2;
			end

			rden = 1;
		end
		WRITE_USB_EXT2: begin

			usb2counter<=usb2counter+1;

			case(SendCount[ram_width+2:ram_width])
				0: usb_dataio_slow<=ram_output1;
				1: usb_dataio_slow<=ram_output2;
				2: usb_dataio_slow<=ram_output3;
				3: usb_dataio_slow<=ram_output4;
				4: usb_dataio_slow<=digital_buffer1;
			endcase
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				SendCount = SendCount + (2**sendincrement);
				rdaddress_slow = rdaddress_slow + (2**sendincrement);
				rdadtwo_slow = rdaddress_slow;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress_slow = wraddress_triggerpoint - triggerpoint;
					rdadtwo_slow = rdaddress_slow;
				end
				state=WRITE_USB_EXT3;
			end
		end
		WRITE_USB_EXT3: begin
			usb_wr_slow<= 0;
			usb2counter<=0;
			state=WRITE_USB_EXT4;
		end
		WRITE_USB_EXT4: begin
			usb2counter=usb2counter+1;
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
				usb_wr_slow<= 1;	
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=WRITE_USB_EXT5;
				end
				else begin
					usb2counter=0;
					state=WRITE_USB_EXT1;
				end
			end
		end
		WRITE_USB_EXT5: begin
			usb_siwu_slow=0;
			usb2counter<=usb2counter+1;
			if( (usb2counter>8) ) begin
				state=READ;
				usb_siwu_slow=1;
			end
		end

		WAIT_ADC1: begin
			newcomdata<=0;
			writeadc<=0;
			getadcdata<=1;

				state=WAIT_ADC2;

		end
		WAIT_ADC2: begin
			if (adcvalid) begin
				adctestout<=adcdata;
				writeadc<=1;
				getadcdata<=0;
				if (writesamp>=(nsamp-1)) begin
					writesamp<=0;
					writebyte<=0;
					thecounterbit=thecounter[clockbitstowait];
					state<=WRITE_BYTE1;
				end
				else begin
					writesamp=writesamp+1;
					state=WAIT_ADC1;
				end
			end
		end
		WRITE_BYTE1: begin
			newcomdata<=0;
			writeadc<=0;
			if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
				if (writebyte) txData=adcramdata[11:8];
				else txData=adcramdata[7:0];
				txStart=1;
				serialdelaycounter=serialdelaycounter+1;
				state=WRITE_BYTE2;
			end
		end
		WRITE_BYTE2: begin
			txStart=0;
			if(serialdelaycounter==0 && serialdelaytimer<serialdelaytimerwait) begin
				serialdelaytimer=serialdelaytimer+1;
			end
			else begin
				serialdelaytimer=0;
				if (writebyte) writesamp=writesamp+1;
				writebyte = ~writebyte;
				if (writesamp>(nsamp-1)) state=READ;
				else state=WRITE_BYTE1;
			end
		end
		

		WRITE1: begin
       newcomdata<=0;
       if (!txBusy) begin
          txData = data[ioCount];
          txStart = 1;
          state = WRITE2;
        end
      end
      WRITE2: begin
        txStart = 0;
        if (ioCount < ioCountToSend-1) begin
          ioCount = ioCount + 1;
          state = WRITE1;
        end else begin
          state = READ;
        end
      end
		

		 WRITE_USBFAST_EXT1: begin
			send_fast_usb2=1;
			rden=1;
			if (usbdonecounterslow>1) state=WRITE_USBFAST_EXT2;
			else usbdonecounterslow<=usbdonecounterslow+1;
		 end
		 WRITE_USBFAST_EXT2: begin
			send_fast_usb2=0;
			usbdonecounterslow<=0;
			if (send_fast_usb2_done) begin
				rden=0;
				if (usbdonecounterslow==0) begin





					state=READ;
				end
				else usbdonecounterslow<=usbdonecounterslow-1;
			end
		 end
		
    endcase
	 
  end


assign debug1=send_fast_usb2;
assign debug2=send_fast_usb2_done;
assign debug3=(usb2state[0]);
assign debug4=(usb2state[1]);


reg send_fast_usb2=0;
reg send_fast_usb2_done=0;
reg do_fast_usb=0;
reg[3:0] usbdonecounterfast=0;
reg[3:0] usbdonecounterslow=0;
reg [ram_width:0] SendCount_fast=0;
reg[1:0] usb2state;
localparam USBFAST_IDLE=0, USBFAST_BUSY=1, USBFAST_WRITE=2, USBFAST_DONE=3;
assign rdaddress = ((do_usb && do_fast_usb) ? rdaddress_fast : rdaddress_slow);
assign rdadtwo = ((do_usb && do_fast_usb) ? rdaddress_fast : rdadtwo_slow);
assign usb_dataio = ((do_usb && do_fast_usb) ? usb_dataio_fast : usb_dataio_slow);
assign usb_wr = ((do_usb && do_fast_usb) ? usb_wr_fast : usb_wr_slow);
assign usb_siwu = ((do_usb && do_fast_usb) ? usb_siwu_fast : usb_siwu_slow);
assign clk_rd = ((do_usb && do_fast_usb) ? usb_clk60 : clk);
reg [ram_width:0] nsmp2 = 0;
reg [2:0] SendCount_fast_chan=0;
localparam fastusbpadding=3;
always @(posedge usb_clk60) begin
	case (usb2state)
		USBFAST_IDLE: begin
			send_fast_usb2_done<=0;
			usb_wr_fast<=1;
			usb_siwu_fast<=1;
			if (nsmp>0) nsmp2<=nsmp+fastusbpadding;
			else nsmp2<=(2**ram_width)+fastusbpadding;
			SendCount_fast<=nsmp2-1;
			SendCount_fast_chan<=0;
			rdaddress_fast = wraddress_triggerpoint - triggerpoint - 2*(2**sendincrement);
			usbdonecounterfast<=0;
			if (send_fast_usb2) begin
				usb2state<=USBFAST_BUSY;
			end
		end
		USBFAST_BUSY: begin
			if (!usb_txe_busy) begin
				rdaddress_fast = rdaddress_fast + (2**sendincrement);
				if (usbdonecounterfast>1) begin
					usb_wr_fast<=0;					
					usb2state<=USBFAST_WRITE;
					usbdonecounterfast<=0;
				end
				else usbdonecounterfast<=usbdonecounterfast+1;
			end
		end
		USBFAST_WRITE: begin
			if (!usb_txe_busy) begin
				if(SendCount_fast_chan==blockstosend) begin
					usb_wr_fast<=1;
					send_fast_usb2_done<=1;
					usb_siwu_fast<=0;
					usb2state<=USBFAST_DONE;
				end
				else if (SendCount_fast==0) begin
					usb_wr_fast<=0;
					SendCount_fast <= nsmp2;
					SendCount_fast_chan <= SendCount_fast_chan + 1;
					rdaddress_fast = wraddress_triggerpoint - triggerpoint;
				end
				else begin
					usb_wr_fast<=0;
					SendCount_fast <= SendCount_fast - (2**sendincrement);
					rdaddress_fast = rdaddress_fast + (2**sendincrement);
				end
			end
			else begin
				usb_wr_fast<=1;
				usb2state<=USBFAST_BUSY;
				rdaddress_fast = rdaddress_fast - 3*(2**sendincrement);
			end
		end
		USBFAST_DONE: begin
			if (usbdonecounterfast>1) usb2state<=USBFAST_IDLE;
			else usbdonecounterfast<=usbdonecounterfast+1;
		end
	endcase
	case(SendCount_fast_chan)
		0: usb_dataio_fast=ram_output1;
		1: usb_dataio_fast=ram_output2;
		2: usb_dataio_fast=ram_output3;
		3: usb_dataio_fast=ram_output4;
		4: usb_dataio_fast=digital_buffer1;
	endcase
end
  

  always @(posedge clk) begin
   case (i2cstate)
		READ: begin
			i2c_ena<=0;
			if (i2cgo) begin
				i2cstate=I2CWAIT;
			end
		end
		I2CWAIT: begin
			if (~i2c_busy) begin

				i2c_rw=0;

				i2c_datawr = i2cdata[0];
				i2c_datacount=1;
				i2cstate=I2CSEND1;
			end
		end
		I2CSEND1: begin
			i2c_ena = 1;
			if (i2c_datacount >= i2c_datacounttosend) begin
				i2cstate=READ;
			end
			else if (i2c_busy) begin
				i2c_datawr = i2cdata[i2c_datacount];
				if (i2cdoread) begin
					i2c_rw=1;
				end
				i2cstate=I2CSEND2;
			end
		end
		I2CSEND2: begin
			if (~i2c_busy) begin

				i2c_datacount = i2c_datacount+1;
				i2cstate=I2CSEND1;
			end
		end
	endcase
	end
  

	reg [5:0] columndata;
	reg [2:0] row;
	reg [6:0] column;
	reg [3:0] b;
	always @(posedge clk) begin
		if (screenaddr>1000) screenreset<=1;
		screenaddr = screenaddr + 1;
		row=7-screenaddr[9:7];
		column=screenaddr[6:0];
		


		
		columndata = screencolumndata[column];
		

		if (columndata>=8*(row+1)) screendata = 8'hff;
		else if (columndata>=8*row) begin
			screendata=8'h00; b=0;
			while (b<8) begin
				if (columndata[2:0]>b) screendata[b]=1;
				b=b+1;
			end
		end
		else screendata = 8'h00;
		


		

		if (row==7 & trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end
		if (row==6 & !trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end	
	end
	
endmodule
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,debug3,debug4,spare,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug, 
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror,   usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdadtwo,trigthreshtwo, debug1,debug2,chip_id, highres,  use_ext_trig,  digital_buffer1, nsmp, outputclk,
phasecounterselect,phaseupdown,phasestep,scanclk,
ext_trig_delay, noselftrig, usb_oe, usb_rd, usb_rxf, usb_pwrsv, clk_rd,
nselftrigcoincidentreq, selftrigtempholdtime, allowsamechancoin
);

   input clk;
	input[7:0] rxData;
   input rxReady;
   input txBusy;
   output reg txStart;
   output reg[7:0] txData;
   output reg[7:0] readdata;
   output wire spare,debug3,debug4;
	reg led1,led2,led3,led4;
	reg io1,io2,io3,io4;
  	output reg get_ext_data;
	input ext_data_ready;
	parameter ram_width=12;
	input wire[ram_width-1:0] wraddress_triggerpoint;
	output wire [ram_width-1:0] rdaddress;
	output wire [ram_width-1:0] rdadtwo;
	reg [ram_width-1:0] rdaddress_slow;
	reg [ram_width-1:0] rdadtwo_slow;
	reg [ram_width-1:0] rdaddress_fast;

	output reg [ram_width-1:0] triggerpoint;
	output reg rden=0;
	input wire [7:0] ram_output1;
	input wire [7:0] ram_output2;
	input wire [7:0] ram_output3;
	input wire [7:0] ram_output4;
	input wire [7:0] digital_buffer1;
	output reg serial_passthrough;
	output reg [1:0] master_clock;
	output reg[7:0] comdata;
	output reg newcomdata;
	output reg imthelast;
	output wire imthefirst;
	output reg rollingtrigger;
	input trigDebug;
	input [11:0] adcdata;
	input adcready;
	input adcvalid;
	output reg getadcdata;
	output reg [4:0] getadcadr;
	output reg adcreset;
	output reg [10:0] writesamp;
	output reg writeadc;
	output reg [11:0] adctestout;
	output reg [7:0] downsample;
	output reg [7:0] screendata;
	output reg screenwren=0;
	output reg [9:0] screenaddr = 10'd0;
	output reg screenreset=0;
	output reg [7:0] trigthresh = 8'h80, trigthreshtwo=8'hff;
	output reg [3:0] trigchannels = 4'b1111;
	output reg [3:0] triggertype = 4'b0001;
   output reg [ram_width:0] triggertot;
	output reg [15:0] SPIsenddata;
	output reg SPIsend;
	input [7:0] delaycounter;
	input [7:0] carrycounter;
	input [3:0] SPIstate;
	output wire[3:0] offset;
	output reg[3:0] gainsw;
	reg[3:0] oversamp;
	output wire debug1,debug2;
	input [63:0] chip_id;
	output reg highres=0;
	output reg use_ext_trig=0;
	output reg outputclk=1;
	output reg[4:0] ext_trig_delay=0;
	output reg noselftrig=0;
	output reg[1:0] nselftrigcoincidentreq=0;
	output reg[7:0] selftrigtempholdtime=10;
	output reg allowsamechancoin=0;
	
	output reg i2c_ena;
	output reg [6:0] i2c_addr;
	output reg i2c_rw;
	output reg [7:0] i2c_datawr;
	input [7:0] i2c_datard;
	input i2c_busy;
	input i2c_ackerror;
	reg [7:0] i2cdata[8];
	reg [3:0] i2c_datacounttosend,i2c_datacount;
	reg i2cgo=0;
	reg i2cdoread=0;

  localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9, 
	WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
	WRITE_USBFAST_EXT1=16, WRITE_USBFAST_EXT2=17,
	LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
	WRITE_USB_EXT1=24, WRITE_USB_EXT2=25, WRITE_USB_EXT3=26, WRITE_USB_EXT4=27, WRITE_USB_EXT5=28,
	PLLCLOCK=30;
  reg[4:0] state,i2cstate;

  reg [7:0] myid;
  assign imthefirst = (myid==0);
  reg [7:0] extradata[10];
  reg [ram_width+2:0] SendCount=0;
  reg [2:0] blockstosend=4;
  reg [15:0] nsamp = 6;
  input [11:0] adcramdata;
  reg writebyte;
  reg[7:0] bytesread, byteswanted;
  reg thecounterbit, thecounterbitlockin;
  reg [7:0] clockbitstowait=5, clockbitstowaitlockin=3;
  reg [3:0] sendincrement = 0;
  output reg [ram_width-1:0] nsmp = 0;
  reg [7:0] chanforscreen=0;
  reg autorearm=0;
  integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
  reg[4:0] serialdelaycounter=0;
  reg addonetoextradata=0;
  
  output wire clk_rd;
  reg [7:0] usb2counter;
  output reg do_usb=0;
  input usb_clk60;
  output wire [7:0] usb_dataio;
  reg [7:0] usb_dataio_slow;
  reg [7:0] usb_dataio_fast;

  input usb_txe_busy;
  reg usb_txe_not_busy;
  output reg usb_oe=1;
  output reg usb_rd=1;
  input usb_rxf;
  output reg usb_pwrsv=1;
  output wire usb_wr, usb_siwu;
  reg usb_wr_slow, usb_siwu_slow;
  reg usb_wr_fast, usb_siwu_fast;
  reg checkfastusbwriting=0;
  

  reg [5:0] screencolumndata [128];
  

  reg[7:0] ioCount, ioCountToSend;
  reg[7:0] data[0:15];
  

  reg [7:0] numlockinbytes=16;
  integer lockinresult1;
  integer lockinresult2;
  reg [15:0] lockinnumtoshift = 0;
  reg [31:0] chan2mean, chan3mean;
  reg calcmeans;
  

  reg[7:0] pllclock_counter=0;
  reg[7:0] scanclk_cycles=0;
  output reg[2:0] phasecounterselect;
  output reg phaseupdown=1;
  output reg phasestep=0;
  output reg scanclk=0;
  
  initial begin
    state<=READ;
	 i2cstate<=READ;
	 usb2state<=USBFAST_IDLE;
	 myid<=200;
	 master_clock<=2'b00;
	 imthelast<=0;
	 rollingtrigger<=1;
	 triggerpoint<=(2**(ram_width-2));
	 downsample<=1;
	 serial_passthrough<=0;
	 usb_siwu_slow<=1;
	 gainsw<=4'b0000;
	 oversamp<=4'b0011;
	 led1<=1;
	 led2<=1;
	 led3<=1;
	 led4<=1;
	 io1<=0;
	 io2<=0;
	 io3<=0;
	 io4<=0;
  end
  

  always @(posedge clk) begin
	thecounter<=thecounter+1;
   if (thecounter[26]==1'b1 ) begin
		if (imthelast) begin
			led1<=0;		led2<=0;		led3<=0;
		end
		else if (myid==0) begin
			led1<=0;		led2<=0;
		end
		else begin
			led1<=0;
		end
	end
	else begin
		if (imthelast) begin
			led1<=1;		led2<=1;		led3<=1;
		end
		else if (myid==0) begin
			led1<=1;		led2<=1;
		end
		else begin
			led1<=1;
		end
	end
	if (thecounter[24]==1'b1 ) begin
		io3 <= 0;
	end
	else begin
		io3 <= 1;
	end
  end
  reg oldled1,oldled2,oldled3,oldled4,oldio1,oldio2,oldio3,oldio4;
  




















  
  always @(posedge clk) begin
    usb_txe_not_busy <= ~usb_txe_busy;
    case (state)
	 
      READ: begin
		  get_ext_data<=0;
		  adcreset<=1;
		  txStart<=0;
		  getadcdata<=0;
		  bytesread<=0;
		  byteswanted<=0;
		  newcomdata<=0;
		  SPIsend<=0;
		  i2cgo=0;
		  usb_wr_slow<=1;
        ioCount = 0;
		  send_fast_usb2=0;
		  addonetoextradata=0;
		  serialdelaycounter=0;
        if (rxReady) begin
			 readdata = rxData;
          state = SOLVING;
        end
		  if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldio1!=io1 || oldio2!=io2 || oldio3!=io3 || oldio4!=io4) begin
			 oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
			 oldio1=io1; oldio2=io2; oldio3=io3; oldio4=io4;

			 i2c_datacounttosend=2;
			 i2c_addr=8'h21;
			 i2cdata[0]=8'h12;
			 i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
			 i2cdata[1][4]=io1; i2cdata[1][5]=io2; i2cdata[1][6]=io3; i2cdata[1][7]=io4;
			 i2cdata[2]=0;
			 if (i2cstate==READ) begin
			   i2cdoread = 0;
				i2cgo=1;
			 end
		  end
      end
		
		READMORE: begin
			newcomdata=0;
			if (rxReady) begin
				extradata[bytesread] = rxData;
				if (addonetoextradata) comdata=rxData+1;
				else comdata=rxData;
				newcomdata=1;
				bytesread = bytesread+1;
				if (bytesread>=byteswanted) state=SOLVING;
			end
		end

      SOLVING: begin
			if (readdata < 10) begin
				myid=readdata;
				if (readdata==0) begin
					master_clock=2'b00;
				end
				else master_clock=2'b01;
				comdata=(readdata+1);
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 9 && readdata < 20) begin
				if (myid==(readdata-10)) begin

					serial_passthrough=0;
					timeoutcounter=0;
					state=WAITING;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
			end
			else if (readdata > 19 && readdata < 30) begin
				if (myid==(readdata-20)) begin
					imthelast=1;
					outputclk=0;
				end
				else begin
					imthelast=0;
					outputclk=1;
				end
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 29 && readdata < 40) begin
				if (myid==(readdata-30)) begin

					serial_passthrough=0;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
				end
				state=READ;
			end
			

			
			else if (readdata==50) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				addonetoextradata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					myid=extradata[0];
					if (extradata[0]==0) begin
						master_clock=2'b00;
					end
					else master_clock=2'b01;
					state=READ;
				end
			end
			else if (readdata==51) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0] || extradata[0]==255) begin

						serial_passthrough=0;
						timeoutcounter=0;
						state=WAITING;
					end
					else begin


							serial_passthrough=1;

						state=READ;
					end
				end
			end
			else if (readdata==52) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0]) begin
						imthelast=1;
						outputclk=0;
					end
					else begin
						imthelast=0;
						outputclk=1;
					end
					state=READ;
				end
			end
			else if (readdata==53) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (myid==extradata[0]) begin

						serial_passthrough=0;
					end
					else begin


							serial_passthrough=1;

					end
					state=READ;
				end
			end
			
			else if (54==readdata) begin
				if (imthelast) outputclk = ~outputclk;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (55==readdata) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					phasecounterselect=3'b000;

					scanclk=1'b0;
					phasestep=1'b1;
					pllclock_counter=0;
					scanclk_cycles=0;
					state=PLLCLOCK;
				end
			end
			
			else if (readdata==56) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					ext_trig_delay = extradata[0];
					state=READ;
				end
			end
			else if (57==readdata) begin
				noselftrig=~noselftrig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (58==readdata) begin
				do_fast_usb=~do_fast_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (59==readdata) begin
				checkfastusbwriting=~checkfastusbwriting;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end			
			
			else if (100==readdata) begin

				get_ext_data=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (101==readdata) begin

				io1=1;
				rollingtrigger=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (102==readdata) begin

				io1=0;
				rollingtrigger=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (readdata>109 && readdata<120) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					if (readdata==119) getadcadr<=17;
					else getadcadr<=(readdata-110);
					writesamp<=0;
					state=WAIT_ADC1;
				end
			end
			else if (readdata==120) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsamp=256*extradata[0]+extradata[1];
					if (nsamp>4095) nsamp=4095;
					state=READ;
				end
			end
			else if (readdata==121) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggerpoint=256*extradata[0]+extradata[1];
					if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
					else if (triggerpoint<4) triggerpoint=4;
					state=READ;
				end
			end
			else if (readdata==122) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsmp=256*extradata[0]+extradata[1];
					if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
					state=READ;
				end
			end
			else if (readdata==123) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					sendincrement=extradata[0];
					state=READ;
				end
			end
			else if (readdata==124) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>22) extradata[0]=22;
					downsample=extradata[0];
					clockbitstowaitlockin = extradata[0]-2;
					state=READ;
				end
			end
			else if (readdata==125) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					clockbitstowait=extradata[0];
					state=READ;
				end
			end
			else if (readdata==126) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					chanforscreen=extradata[0];
					state=READ;
				end
			end
			
			else if (readdata==127) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh=extradata[0];
					state=READ;
				end
			end
			else if (readdata==128) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertype=extradata[0];
					state=READ;
				end
			end
			else if (readdata==129) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertot=256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (readdata==130) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
					end
					state=READ;
				end
			end
			else if (readdata==131) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					SPIsenddata[15:8]=extradata[0];
					SPIsenddata[7:0]=extradata[1];
					SPIsenddata[15]=1'b0;
					SPIsend=1;
					state=SPIWAIT;
				end
			end
			else if (readdata==132) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=delaycounter;
					state=WRITE1;
				end
			end
			else if (readdata==133) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=carrycounter;
					state=WRITE1;
				end
			end
			else if (readdata==134) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (readdata==135) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
					state=READ;
				end
			end
			else if (readdata==136) begin
				byteswanted=6;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin



					i2c_datacounttosend=extradata[0];
					i2c_addr=extradata[1];
					i2cdata[0]=extradata[2];
					i2cdata[1]=extradata[3];
					i2cdata[2]=extradata[4];
					if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (137==readdata) begin

				do_usb=~do_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==138) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					lockinnumtoshift = 256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (139==readdata) begin

				autorearm=~autorearm;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==140) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthreshtwo = extradata[0];
					state=READ;
				end
			end
			else if (readdata==141) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end			
			else if (readdata==142) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					data[0]=chip_id[7+8*0:8*0];
					data[1]=chip_id[7+8*1:8*1];
					data[2]=chip_id[7+8*2:8*2];
					data[3]=chip_id[7+8*3:8*3];
					data[4]=chip_id[7+8*4:8*4];
					data[5]=chip_id[7+8*5:8*5];
					data[6]=chip_id[7+8*6:8*6];
					data[7]=chip_id[7+8*7:8*7];
					ioCountToSend = 8;
					state=WRITE1;
				end
			end
			else if (143==readdata) begin

				highres=~highres;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (144==readdata) begin

				use_ext_trig=~use_ext_trig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==145) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					blockstosend = extradata[0];
					state=READ;
				end
			end
			else if (readdata==146) begin
				byteswanted=3;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					i2c_addr=extradata[0];
					i2c_datacounttosend=2;
					i2cdata[0]=extradata[1];
					i2cdata[1]=0;
					if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
						i2cdoread = 1;
						i2cgo=1;

						ioCountToSend = 1;
						data[0] = i2c_datard;
						state=WRITE1;
					end
					else state=READ;
				end
			end
			else if (readdata==147) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=21;
					state=WRITE1;
				end
				

				rden=0;
				trigthresh = 8'h80;
				trigthreshtwo=8'hff;
				trigchannels = 4'b1111;
				triggertype = 4'b0001;   
				highres=0;
				use_ext_trig=0;
				ext_trig_delay=0;
				noselftrig=0;
				SendCount=0;
				blockstosend=4;
				nsamp = 6;
				clockbitstowait=5;
				sendincrement = 0;
				nsmp = 0;
				chanforscreen=0;
				autorearm=0;
				do_usb=0;
				checkfastusbwriting=0;
				rollingtrigger=1;
				triggerpoint=(2**(ram_width-2));
				downsample=1;
				gainsw=4'b0000;
				oversamp=4'b0011;
				send_fast_usb2=0;
				do_fast_usb=0;
				usbdonecounterslow=0;
				nselftrigcoincidentreq=0;
				selftrigtempholdtime=10;
				allowsamechancoin=0;
			end
			else if (readdata==148) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nselftrigcoincidentreq = extradata[0];
					state=READ;
				end
			end
			else if (readdata==149) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					selftrigtempholdtime = extradata[0];
					state=READ;
				end
			end
			else if (150==readdata) begin

				allowsamechancoin=~allowsamechancoin;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end			
			
			else state=READ;
      end
		
		SPIWAIT: begin
			newcomdata<=0;

			if (SPIstate==3) begin 
				state=READ;
			end
		end
		
		PLLCLOCK: begin
			pllclock_counter=pllclock_counter+1;
			if (pllclock_counter[4]) begin
				scanclk = ~scanclk;
				pllclock_counter=0;
				scanclk_cycles=scanclk_cycles+1;
				if (scanclk_cycles>5) phasestep=1'b0;
				if (scanclk_cycles>7) state=READ;
			end
		end
		
		WAITING: begin
			newcomdata<=0;
			timeoutcounter=timeoutcounter+1;
			if (ext_data_ready) begin
				SendCount= 0;
				rdaddress_slow = wraddress_triggerpoint - triggerpoint;
				rdadtwo_slow = rdaddress_slow;
				thecounterbit=thecounter[clockbitstowait];
				thecounterbitlockin=thecounter[clockbitstowaitlockin];
				if (lockinnumtoshift>0) begin
					lockinresult1=0;
					lockinresult2=0;
					chan2mean=0;
					chan3mean=0;
					calcmeans=1;
					state=LOCKIN1;
				end
				else begin
					if (do_usb) begin
						if (do_fast_usb) begin
							if (checkfastusbwriting) begin
								do_usb<=0;
								state=WRITE_EXT1;
							end
							else state=WRITE_USBFAST_EXT1;
						end
						else state=WRITE_USB_EXT1;
					end
					else state=WRITE_EXT1;
				end
			end
			if ( timeoutcounter > 100000000 ) begin
				state=READ;



			end
		end
		LOCKIN1: begin
			rden = 1;
			if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
			case(SendCount[ram_width+1:ram_width])
				0: begin

					chan2mean = chan2mean + ram_output3;
					chan3mean = chan3mean + ram_output4;
				end
				1: begin
					if (calcmeans) begin
						calcmeans=0;
						chan2mean = chan2mean/4096;
						chan3mean = chan3mean/4096;
					end


					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult2 = lockinresult2 + (ram_output3-chan2mean[7:0])*(ram_output4-chan3mean[7:0]);
					end
				end
				2: begin

					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				3: begin
						
				end
			endcase			
			SendCount = SendCount + 1;
			rdaddress_slow = rdaddress_slow + 1;
			if (SendCount[ram_width+1:ram_width]==1) rdadtwo_slow=rdaddress_slow-lockinnumtoshift;
			else rdadtwo_slow=rdaddress_slow;
			state=LOCKIN2;
			end
		end
		LOCKIN2: begin	
			state=LOCKIN3;
		end
		LOCKIN3: begin
			if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
			if(SendCount[ram_width+1:0]==0) begin
				ioCount = 0;
				SendCount = 0;
				state=LOCKINWRITE1;
			end
			else begin
				state=LOCKIN1;
			end
			end
		end
		LOCKINWRITE1: begin
       if (!txBusy) begin
          if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
          else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
          else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
          else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
          else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
          else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
          else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
          else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];			 
			 else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
          else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
          else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
          else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
			 else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
          else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
          else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
          else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
			 else txData = 0;
          txStart = 1;
          state = LOCKINWRITE2;
        end
      end
      LOCKINWRITE2: begin
        txStart = 0;
        if (ioCount < numlockinbytes-1) begin
          ioCount = ioCount + 1;
          state = LOCKINWRITE1;
        end
		  else begin
				rdaddress_slow = wraddress_triggerpoint - triggerpoint;
				rdadtwo_slow = rdaddress_slow;
				thecounterbit=thecounter[clockbitstowait];
				if (do_usb) begin
					if (do_fast_usb) begin
						state=WRITE_USBFAST_EXT1;
					end
					else state=WRITE_USB_EXT1;
				end
				else state=WRITE_EXT1;
        end
      end
		WRITE_EXT1: begin
			timeoutcounter=timeoutcounter+1;
			rden = 1;

			case(SendCount[ram_width+2:ram_width])
			0: txData<=ram_output1;
			1: txData<=ram_output2;
			2: txData<=ram_output3;
			3: txData<=ram_output4;
			4: txData<=digital_buffer1;
			endcase
			if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				txStart<= 1;				
				serialdelaycounter=serialdelaycounter+1;
				SendCount = SendCount + (2**sendincrement);
				rdaddress_slow = rdaddress_slow + (2**sendincrement);
				rdadtwo_slow = rdaddress_slow;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress_slow = wraddress_triggerpoint - triggerpoint;
					rdadtwo_slow = rdaddress_slow;
				end
				state=WRITE_EXT2;
			end
			if ( timeoutcounter > 100000000 ) begin
				rden = 0;
				state=READ;
			end
		end
		WRITE_EXT2: begin
			if( thecounter[clockbitstowait]==thecounterbit ) begin
				txStart<= 0;
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					if (!checkfastusbwriting) begin
						rden = 0;
						if (autorearm) begin

							get_ext_data=1;
						end
						state=READ;
					end
					else begin
						do_usb<=1;
						state=WRITE_USBFAST_EXT1;
					end
				end
				else begin					
					if(serialdelaycounter==0 && serialdelaytimer<serialdelaytimerwait) begin
						serialdelaytimer=serialdelaytimer+1;
					end
					else begin
						if ( (rdaddress_slow-wraddress_triggerpoint-64)>=0 && (rdaddress_slow-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
							if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress_slow - wraddress_triggerpoint - 64]=(63-txData[7:2]);
							screenwren = 1;
						end
						serialdelaytimer=0;
						state=WRITE_EXT1;
					end
				end
			end
		end
		
		WRITE_USB_EXT1: begin
			if (usb_txe_not_busy) begin
				thecounterbit=thecounter[clockbitstowait];
				usb2counter<=0;
				state=WRITE_USB_EXT2;
			end

			rden = 1;
		end
		WRITE_USB_EXT2: begin

			usb2counter<=usb2counter+1;

			case(SendCount[ram_width+2:ram_width])
				0: usb_dataio_slow<=ram_output1;
				1: usb_dataio_slow<=ram_output2;
				2: usb_dataio_slow<=ram_output3;
				3: usb_dataio_slow<=ram_output4;
				4: usb_dataio_slow<=digital_buffer1;
			endcase
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				SendCount = SendCount + (2**sendincrement);
				rdaddress_slow = rdaddress_slow + (2**sendincrement);
				rdadtwo_slow = rdaddress_slow;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress_slow = wraddress_triggerpoint - triggerpoint;
					rdadtwo_slow = rdaddress_slow;
				end
				state=WRITE_USB_EXT3;
			end
		end
		WRITE_USB_EXT3: begin
			usb_wr_slow<= 0;
			usb2counter<=0;
			state=WRITE_USB_EXT4;
		end
		WRITE_USB_EXT4: begin
			usb2counter=usb2counter+1;
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
				usb_wr_slow<= 1;	
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=WRITE_USB_EXT5;
				end
				else begin
					usb2counter=0;
					state=WRITE_USB_EXT1;
				end
			end
		end
		WRITE_USB_EXT5: begin
			usb_siwu_slow=0;
			usb2counter<=usb2counter+1;
			if( (usb2counter>8) ) begin
				state=READ;
				usb_siwu_slow=1;
			end
		end

		WAIT_ADC1: begin
			newcomdata<=0;
			writeadc<=0;
			getadcdata<=1;

				state=WAIT_ADC2;

		end
		WAIT_ADC2: begin
			if (adcvalid) begin
				adctestout<=adcdata;
				writeadc<=1;
				getadcdata<=0;
				if (writesamp>=(nsamp-1)) begin
					writesamp<=0;
					writebyte<=0;
					thecounterbit=thecounter[clockbitstowait];
					state<=WRITE_BYTE1;
				end
				else begin
					writesamp=writesamp+1;
					state=WAIT_ADC1;
				end
			end
		end
		WRITE_BYTE1: begin
			newcomdata<=0;
			writeadc<=0;
			if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
				if (writebyte) txData=adcramdata[11:8];
				else txData=adcramdata[7:0];
				txStart=1;
				serialdelaycounter=serialdelaycounter+1;
				state=WRITE_BYTE2;
			end
		end
		WRITE_BYTE2: begin
			txStart=0;
			if(serialdelaycounter==0 && serialdelaytimer<serialdelaytimerwait) begin
				serialdelaytimer=serialdelaytimer+1;
			end
			else begin
				serialdelaytimer=0;
				if (writebyte) writesamp=writesamp+1;
				writebyte = ~writebyte;
				if (writesamp>(nsamp-1)) state=READ;
				else state=WRITE_BYTE1;
			end
		end
		

		WRITE1: begin
       newcomdata<=0;
       if (!txBusy) begin
          txData = data[ioCount];
          txStart = 1;
          state = WRITE2;
        end
      end
      WRITE2: begin
        txStart = 0;
        if (ioCount < ioCountToSend-1) begin
          ioCount = ioCount + 1;
          state = WRITE1;
        end else begin
          state = READ;
        end
      end
		

		 WRITE_USBFAST_EXT1: begin
			send_fast_usb2=1;
			rden=1;
			if (usbdonecounterslow>1) state=WRITE_USBFAST_EXT2;
			else usbdonecounterslow<=usbdonecounterslow+1;
		 end
		 WRITE_USBFAST_EXT2: begin
			send_fast_usb2=0;
			usbdonecounterslow<=0;
			if (send_fast_usb2_done) begin
				rden=0;
				if (usbdonecounterslow==0) begin





					state=READ;
				end
				else usbdonecounterslow<=usbdonecounterslow-1;
			end
		 end
		
    endcase
	 
  end


assign debug1=send_fast_usb2;
assign debug2=send_fast_usb2_done;
assign debug3=(usb2state[0]);
assign debug4=(usb2state[1]);


reg send_fast_usb2=0;
reg send_fast_usb2_done=0;
reg do_fast_usb=0;
reg[3:0] usbdonecounterfast=0;
reg[3:0] usbdonecounterslow=0;
reg [ram_width:0] SendCount_fast=0;
reg[1:0] usb2state;
localparam USBFAST_IDLE=0, USBFAST_BUSY=1, USBFAST_WRITE=2, USBFAST_DONE=3;
assign rdaddress = ((do_usb && do_fast_usb) ? rdaddress_fast : rdaddress_slow);
assign rdadtwo = ((do_usb && do_fast_usb) ? rdaddress_fast : rdadtwo_slow);
assign usb_dataio = ((do_usb && do_fast_usb) ? usb_dataio_fast : usb_dataio_slow);
assign usb_wr = ((do_usb && do_fast_usb) ? usb_wr_fast : usb_wr_slow);
assign usb_siwu = ((do_usb && do_fast_usb) ? usb_siwu_fast : usb_siwu_slow);
assign clk_rd = ((do_usb && do_fast_usb) ? usb_clk60 : clk);
reg [ram_width:0] nsmp2 = 0;
reg [2:0] SendCount_fast_chan=0;
localparam fastusbpadding=3;
always @(posedge usb_clk60) begin
	case (usb2state)
		USBFAST_IDLE: begin
			send_fast_usb2_done<=0;
			usb_wr_fast<=1;
			usb_siwu_fast<=1;
			if (nsmp>0) nsmp2<=nsmp+fastusbpadding;
			else nsmp2<=(2**ram_width)+fastusbpadding;
			SendCount_fast<=nsmp2-1;
			SendCount_fast_chan<=0;
			rdaddress_fast = wraddress_triggerpoint - triggerpoint - 2*(2**sendincrement);
			usbdonecounterfast<=0;
			if (send_fast_usb2) begin
				usb2state<=USBFAST_BUSY;
			end
		end
		USBFAST_BUSY: begin
			if (!usb_txe_busy) begin
				rdaddress_fast = rdaddress_fast + (2**sendincrement);
				if (usbdonecounterfast>1) begin
					usb_wr_fast<=0;					
					usb2state<=USBFAST_WRITE;
					usbdonecounterfast<=0;
				end
				else usbdonecounterfast<=usbdonecounterfast+1;
			end
		end
		USBFAST_WRITE: begin
			if (!usb_txe_busy) begin
				if(SendCount_fast_chan==blockstosend) begin
					usb_wr_fast<=1;
					send_fast_usb2_done<=1;
					usb_siwu_fast<=0;
					usb2state<=USBFAST_DONE;
				end
				else if (SendCount_fast==0) begin
					usb_wr_fast<=0;
					SendCount_fast <= nsmp2;
					SendCount_fast_chan <= SendCount_fast_chan + 1;
					rdaddress_fast = wraddress_triggerpoint - triggerpoint;
				end
				else begin
					usb_wr_fast<=0;
					SendCount_fast <= SendCount_fast - (2**sendincrement);
					rdaddress_fast = rdaddress_fast + (2**sendincrement);
				end
			end
			else begin
				usb_wr_fast<=1;
				usb2state<=USBFAST_BUSY;
				rdaddress_fast = rdaddress_fast - 3*(2**sendincrement);
			end
		end
		USBFAST_DONE: begin
			if (usbdonecounterfast>1) usb2state<=USBFAST_IDLE;
			else usbdonecounterfast<=usbdonecounterfast+1;
		end
	endcase
	case(SendCount_fast_chan)
		0: usb_dataio_fast=ram_output1;
		1: usb_dataio_fast=ram_output2;
		2: usb_dataio_fast=ram_output3;
		3: usb_dataio_fast=ram_output4;
		4: usb_dataio_fast=digital_buffer1;
	endcase
end
  

  always @(posedge clk) begin
   case (i2cstate)
		READ: begin
			i2c_ena<=0;
			if (i2cgo) begin
				i2cstate=I2CWAIT;
			end
		end
		I2CWAIT: begin
			if (~i2c_busy) begin

				i2c_rw=0;

				i2c_datawr = i2cdata[0];
				i2c_datacount=1;
				i2cstate=I2CSEND1;
			end
		end
		I2CSEND1: begin
			i2c_ena = 1;
			if (i2c_datacount >= i2c_datacounttosend) begin
				i2cstate=READ;
			end
			else if (i2c_busy) begin
				i2c_datawr = i2cdata[i2c_datacount];
				if (i2cdoread) begin
					i2c_rw=1;
				end
				i2cstate=I2CSEND2;
			end
		end
		I2CSEND2: begin
			if (~i2c_busy) begin

				i2c_datacount = i2c_datacount+1;
				i2cstate=I2CSEND1;
			end
		end
	endcase
	end
  

	reg [5:0] columndata;
	reg [2:0] row;
	reg [6:0] column;
	reg [3:0] b;
	always @(posedge clk) begin
		if (screenaddr>1000) screenreset<=1;
		screenaddr = screenaddr + 1;
		row=7-screenaddr[9:7];
		column=screenaddr[6:0];
		


		
		columndata = screencolumndata[column];
		

		if (columndata>=8*(row+1)) screendata = 8'hff;
		else if (columndata>=8*row) begin
			screendata=8'h00; b=0;
			while (b<8) begin
				if (columndata[2:0]>b) screendata[b]=1;
				b=b+1;
			end
		end
		else screendata = 8'h00;
		


		

		if (row==7 & trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end
		if (row==6 & !trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end	
	end
	
endmodule