data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:32: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:93: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data0_din_s; \n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:94: Define or directive not defined: \'`IOB_MONDO_DATA_WIDTH\'\n   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data1_din_s; \n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:95: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   input [`IOB_MONDO_DATA_INDEX-1:0]io_mondo_data_wr_addr_s; \n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:97: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   input [`IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:107: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   input [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_dout; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:108: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:113: Define or directive not defined: \'`TAP_IOB_WIDTH\'\n   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:115: Define or directive not defined: \'`IOB_ADDR_WIDTH\'\n   input [`IOB_ADDR_WIDTH-1:0]tap_mondo_acc_addr_s; \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:128: Define or directive not defined: \'`UCB_NOPAY_PKT_WIDTH\'\n   output [`UCB_NOPAY_PKT_WIDTH-1:0]c2i_rd_nack_packet; \n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:131: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_head_ptr; \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:133: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_tail_ptr; \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:137: Define or directive not defined: \'`IOB_CLK_WIDTH\'\n   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:139: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;  \n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:141: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;  \n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:144: Define or directive not defined: \'`IOB_JBI_WIDTH\'\n   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:146: Define or directive not defined: \'`IOB_SPI_WIDTH\'\n   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:151: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p0; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:152: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p1; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:153: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p2; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:166: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:167: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p1; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:168: Define or directive not defined: \'`IOB_MONDO_SRC_WIDTH\'\n   output [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_din; \n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:176: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   output [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din; \n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:183: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   output [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;  \n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:188: Define or directive not defined: \'`UCB_ADDR_WIDTH\'\n   wire [`UCB_ADDR_WIDTH-1:0]c2i_packet_addr;  \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:191: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_head_s;  \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:191: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_head_s;  \n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:193: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_tail_f;  \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:193: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_tail_f;  \n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:197: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n   wire [`UCB_PKT_WIDTH-1:0]cpu_packet_type;  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:209: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   wire [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0_d1; \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:211: Define or directive not defined: \'`PCX_AD_HI\'\n   wire [`PCX_AD_HI-`PCX_AD_LO:0]pcx_iob_addr;  \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:211: Define or directive not defined: \'`PCX_AD_LO\'\n   wire [`PCX_AD_HI-`PCX_AD_LO:0]pcx_iob_addr;  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:211: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`PCX_AD_HI-`PCX_AD_LO:0]pcx_iob_addr;  \n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:212: Define or directive not defined: \'`PCX_CP_HI\'\n   wire [`PCX_CP_HI-`PCX_TH_LO:0]pcx_iob_cputhr; \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:212: Define or directive not defined: \'`PCX_TH_LO\'\n   wire [`PCX_CP_HI-`PCX_TH_LO:0]pcx_iob_cputhr; \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:212: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`PCX_CP_HI-`PCX_TH_LO:0]pcx_iob_cputhr; \n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:213: Define or directive not defined: \'`PCX_RQ_HI\'\n   wire [`PCX_RQ_HI-`PCX_RQ_LO:0]pcx_iob_req;  \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:213: Define or directive not defined: \'`PCX_RQ_LO\'\n   wire [`PCX_RQ_HI-`PCX_RQ_LO:0]pcx_iob_req;  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:213: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`PCX_RQ_HI-`PCX_RQ_LO:0]pcx_iob_req;  \n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:215: Define or directive not defined: \'`PCX_WIDTH\'\n   wire [`PCX_WIDTH-1:0]pcx_packet;   \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:218: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_iob_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:221: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_packet;  \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:245: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   .mondo_data_addr_p0_d1(mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1:0]),\n                                                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:246: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   .cpu_buf_tail_f (cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:246: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   .cpu_buf_tail_f (cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),\n                                                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:250: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   .mondo_data_addr_p0(mondo_data_addr_p0[`IOB_MONDO_DATA_INDEX-1:0]),\n                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i.v:251: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   .mondo_data_addr_p1(mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1:0]),\n                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module c2i (

   wr_ack_io_buf_din, ucb_buf_acpt, tap_mondo_dout_d2_f, 
   tap_mondo_acc_seq_d2_f, tap_mondo_acc_addr_invld_d2_f, 
   srvc_wr_ack, rd_nack_ucb_sel, mondo_source_wr_l, mondo_source_din, 
   mondo_data_addr_p1, mondo_data_addr_p0, mondo_data1_wr_lo_l, 
   mondo_data1_wr_hi_l, mondo_data1_din_lo, mondo_data1_din_hi, 
   mondo_data0_wr_lo_l, mondo_data0_wr_hi_l, mondo_data0_din_lo, 
   mondo_data0_din_hi, mondo_busy_wr_p2, mondo_busy_wr_p1, 
   mondo_busy_din_p2, mondo_busy_din_p1, mondo_busy_addr_p2, 
   mondo_busy_addr_p1, mondo_busy_addr_p0, iob_tap_stall, 
   iob_pcx_stall_pq, iob_man_ucb_sel, iob_jbi_spi_vld, 
   iob_jbi_spi_data, iob_jbi_pio_vld, iob_jbi_pio_data, 
   iob_int_ucb_sel, iob_dram13_vld, iob_dram13_data, iob_dram02_vld, 
   iob_dram02_data, iob_clk_vld, iob_clk_data, int_buf_din_raw, 
   cpu_mondo_wr_d2, cpu_buf_wr_l, cpu_buf_tail_ptr, cpu_buf_rd_l, 
   cpu_buf_head_ptr, cpu_buf_din_lo, cpu_buf_din_hi, 
   c2i_rd_nack_packet, c2i_packet_is_wr_req, c2i_packet_is_rd_req, 
   bounce_ucb_sel, cpu_mondo_rd_d2, c2i_packet, c2i_packet_vld, 

   tx_sync, tap_mondo_wr_s, tap_mondo_din_s, tap_mondo_acc_seq_s, 
   tap_mondo_acc_addr_s, tap_iob_vld, tap_iob_data, rx_sync, rst_l, 
   rd_nack_ucb_buf_acpt, pcx_iob_data_rdy_px2, pcx_iob_data_px2, 
   mondo_source_dout, mondo_data1_dout_lo, mondo_data1_dout_hi, 
   mondo_data0_dout_lo, mondo_data0_dout_hi, mondo_busy_dout, 
   jbi_iob_spi_stall, jbi_iob_pio_stall, iob_man_ucb_buf_acpt, 
   iob_int_ucb_buf_acpt, io_mondo_source_din_s, io_mondo_data_wr_s, 
   io_mondo_data_wr_addr_s, io_mondo_data1_din_s, 
   io_mondo_data0_din_s, io_buf_avail, int_buf_hit_hwm, 
   dram13_iob_stall, dram02_iob_stall, cpu_rst_l, cpu_clk, 
   cpu_buf_dout_lo, cpu_buf_dout_hi, clk_iob_stall, clk, 
   bounce_ucb_buf_acpt
   );

   





   input		bounce_ucb_buf_acpt;
   input		clk;
   input		clk_iob_stall;
   input [64:0]		cpu_buf_dout_hi;
   input [64:0]		cpu_buf_dout_lo;
   input		cpu_clk;
   input		cpu_rst_l;
   input		dram02_iob_stall;
   input		dram13_iob_stall;
   input		int_buf_hit_hwm;
   input		io_buf_avail;
   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data0_din_s;
   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data1_din_s;
   input [`IOB_MONDO_DATA_INDEX-1:0]io_mondo_data_wr_addr_s;
   input		io_mondo_data_wr_s;
   input [`IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s;
   input		iob_int_ucb_buf_acpt;
   input		iob_man_ucb_buf_acpt;
   input		jbi_iob_pio_stall;
   input		jbi_iob_spi_stall;
   input		mondo_busy_dout;
   input [64:0]		mondo_data0_dout_hi;
   input [64:0]		mondo_data0_dout_lo;
   input [64:0]		mondo_data1_dout_hi;
   input [64:0]		mondo_data1_dout_lo;
   input [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_dout;
   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;
   input		pcx_iob_data_rdy_px2;
   input		rd_nack_ucb_buf_acpt;
   input		rst_l;
   input		rx_sync;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_vld;
   input [`IOB_ADDR_WIDTH-1:0]tap_mondo_acc_addr_s;
   input		tap_mondo_acc_seq_s;
   input [63:0]		tap_mondo_din_s;
   input		tap_mondo_wr_s;
   input		tx_sync;





   output		bounce_ucb_sel;
   output		c2i_packet_is_rd_req;
   output		c2i_packet_is_wr_req;
   output [`UCB_NOPAY_PKT_WIDTH-1:0]c2i_rd_nack_packet;
   output [64:0]	cpu_buf_din_hi;
   output [64:0]	cpu_buf_din_lo;
   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_head_ptr;
   output		cpu_buf_rd_l;
   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_tail_ptr;
   output		cpu_buf_wr_l;
   output		cpu_mondo_wr_d2;
   output [159:0]	int_buf_din_raw;
   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   output		iob_clk_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   output		iob_dram02_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   output		iob_dram13_vld;
   output		iob_int_ucb_sel;
   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   output		iob_jbi_pio_vld;
   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   output		iob_jbi_spi_vld;
   output		iob_man_ucb_sel;
   output		iob_pcx_stall_pq;
   output		iob_tap_stall;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p1;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p2;
   output		mondo_busy_din_p1;
   output		mondo_busy_din_p2;
   output		mondo_busy_wr_p1;
   output		mondo_busy_wr_p2;
   output [64:0]	mondo_data0_din_hi;
   output [64:0]	mondo_data0_din_lo;
   output		mondo_data0_wr_hi_l;
   output		mondo_data0_wr_lo_l;
   output [64:0]	mondo_data1_din_hi;
   output [64:0]	mondo_data1_din_lo;
   output		mondo_data1_wr_hi_l;
   output		mondo_data1_wr_lo_l;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p1;
   output [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_din;
   output		mondo_source_wr_l;
   output		rd_nack_ucb_sel;
   output		srvc_wr_ack;
   output		tap_mondo_acc_addr_invld_d2_f;
   output		tap_mondo_acc_seq_d2_f;
   output [63:0]	tap_mondo_dout_d2_f;
   output		ucb_buf_acpt;
   output [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din;



   output		cpu_mondo_rd_d2;


   output [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;
   output 		c2i_packet_vld;
   


   wire [`UCB_ADDR_WIDTH-1:0]c2i_packet_addr;
   wire			clk_ucb_buf_acpt;
   wire			clk_ucb_sel;
   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_head_s;
   wire			cpu_buf_rd;
   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_tail_f;
   wire			cpu_mondo_addr_invld_d2;
   wire			cpu_mondo_rd_d1;
   wire			cpu_packet_is_req;
   wire [`UCB_PKT_WIDTH-1:0]cpu_packet_type;
   wire			dram0_ucb_buf_acpt;
   wire			dram0_ucb_sel;
   wire			dram1_ucb_buf_acpt;
   wire			dram1_ucb_sel;
   wire			io_mondo_data_wr;
   wire			iob_tap_busy;
   wire			jbi_ucb_buf_acpt;
   wire			jbi_ucb_sel;
   wire			mondo_addr_creg_mbusy_dec_d1;
   wire			mondo_addr_creg_mdata0_dec_d1;
   wire			mondo_addr_creg_mdata1_dec_d1;
   wire [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0_d1;
   wire			mondo_data_bypass_d1;
   wire [`PCX_AD_HI-`PCX_AD_LO:0]pcx_iob_addr;
   wire [`PCX_CP_HI-`PCX_TH_LO:0]pcx_iob_cputhr;
   wire [`PCX_RQ_HI-`PCX_RQ_LO:0]pcx_iob_req;
   wire			pcx_iob_vld;
   wire [`PCX_WIDTH-1:0]pcx_packet;
   wire			spi_ucb_buf_acpt;
   wire			spi_ucb_sel;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_iob_packet;
   wire			tap_iob_packet_vld;
   wire			tap_mondo_rd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_packet;
   wire			tap_sel;

   
   




   c2i_fctrl c2i_fctrl (


			.iob_pcx_stall_pq(iob_pcx_stall_pq),
			.io_mondo_data_wr(io_mondo_data_wr),
			.mondo_data_bypass_d1(mondo_data_bypass_d1),
			.mondo_addr_creg_mdata0_dec_d1(mondo_addr_creg_mdata0_dec_d1),
			.mondo_addr_creg_mdata1_dec_d1(mondo_addr_creg_mdata1_dec_d1),
			.mondo_addr_creg_mbusy_dec_d1(mondo_addr_creg_mbusy_dec_d1),
			.cpu_mondo_rd_d1(cpu_mondo_rd_d1),
			.tap_mondo_rd_d1(tap_mondo_rd_d1),
			.cpu_mondo_rd_d2(cpu_mondo_rd_d2),
			.cpu_mondo_addr_invld_d2(cpu_mondo_addr_invld_d2),
			.mondo_data_addr_p0_d1(mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1:0]),
			.cpu_buf_tail_f	(cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),
			.cpu_mondo_wr_d2(cpu_mondo_wr_d2),
			.tap_mondo_acc_addr_invld_d2_f(tap_mondo_acc_addr_invld_d2_f),
			.tap_mondo_acc_seq_d2_f(tap_mondo_acc_seq_d2_f),
			.mondo_data_addr_p0(mondo_data_addr_p0[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_data_addr_p1(mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_data0_wr_lo_l(mondo_data0_wr_lo_l),
			.mondo_data0_wr_hi_l(mondo_data0_wr_hi_l),
			.mondo_data1_wr_lo_l(mondo_data1_wr_lo_l),
			.mondo_data1_wr_hi_l(mondo_data1_wr_hi_l),
			.mondo_source_wr_l(mondo_source_wr_l),
			.mondo_busy_addr_p0(mondo_busy_addr_p0[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_addr_p1(mondo_busy_addr_p1[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_addr_p2(mondo_busy_addr_p2[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_wr_p1(mondo_busy_wr_p1),
			.mondo_busy_wr_p2(mondo_busy_wr_p2),
			.cpu_buf_wr_l	(cpu_buf_wr_l),
			.cpu_buf_tail_ptr(cpu_buf_tail_ptr[`IOB_CPU_BUF_INDEX-1:0]),

			.cpu_rst_l	(cpu_rst_l),
			.cpu_clk	(cpu_clk),
			.tx_sync	(tx_sync),
			.rx_sync	(rx_sync),
			.pcx_iob_data_rdy_px2(pcx_iob_data_rdy_px2),
			.pcx_iob_vld	(pcx_iob_vld),
			.pcx_iob_req	(pcx_iob_req[`PCX_RQ_HI-`PCX_RQ_LO:0]),
			.pcx_iob_addr	(pcx_iob_addr[`PCX_AD_HI-`PCX_AD_LO:0]),
			.pcx_iob_cputhr	(pcx_iob_cputhr[`PCX_CP_HI-`PCX_TH_LO:0]),
			.cpu_buf_head_s	(cpu_buf_head_s[`IOB_CPU_BUF_INDEX:0]),
			.int_buf_hit_hwm(int_buf_hit_hwm),
			.io_mondo_data_wr_s(io_mondo_data_wr_s),
			.io_mondo_data_wr_addr_s(io_mondo_data_wr_addr_s[`IOB_MONDO_DATA_INDEX-1:0]),
			.tap_mondo_acc_addr_s(tap_mondo_acc_addr_s[`IOB_ADDR_WIDTH-1:0]),
			.tap_mondo_acc_seq_s(tap_mondo_acc_seq_s),
			.tap_mondo_wr_s	(tap_mondo_wr_s));

   

   c2i_fdp c2i_fdp (


		    .pcx_iob_vld	(pcx_iob_vld),
		    .pcx_iob_req	(pcx_iob_req[`PCX_RQ_HI-`PCX_RQ_LO:0]),
		    .pcx_iob_addr	(pcx_iob_addr[`PCX_AD_HI-`PCX_AD_LO:0]),
		    .pcx_iob_cputhr	(pcx_iob_cputhr[`PCX_CP_HI-`PCX_TH_LO:0]),
		    .int_buf_din_raw	(int_buf_din_raw[159:0]),
		    .tap_mondo_dout_d2_f(tap_mondo_dout_d2_f[63:0]),
		    .mondo_data0_din_lo	(mondo_data0_din_lo[64:0]),
		    .mondo_data0_din_hi	(mondo_data0_din_hi[64:0]),
		    .mondo_data1_din_lo	(mondo_data1_din_lo[64:0]),
		    .mondo_data1_din_hi	(mondo_data1_din_hi[64:0]),
		    .mondo_source_din	(mondo_source_din[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .mondo_busy_din_p1	(mondo_busy_din_p1),
		    .mondo_busy_din_p2	(mondo_busy_din_p2),
		    .cpu_buf_din_lo	(cpu_buf_din_lo[64:0]),
		    .cpu_buf_din_hi	(cpu_buf_din_hi[64:0]),

		    .cpu_clk		(cpu_clk),
		    .tx_sync		(tx_sync),
		    .rx_sync		(rx_sync),
		    .pcx_iob_data_px2	(pcx_iob_data_px2[`PCX_WIDTH-1:0]),
		    .io_mondo_data_wr	(io_mondo_data_wr),
		    .mondo_data_bypass_d1(mondo_data_bypass_d1),
		    .mondo_addr_creg_mdata0_dec_d1(mondo_addr_creg_mdata0_dec_d1),
		    .mondo_addr_creg_mdata1_dec_d1(mondo_addr_creg_mdata1_dec_d1),
		    .mondo_addr_creg_mbusy_dec_d1(mondo_addr_creg_mbusy_dec_d1),
		    .cpu_mondo_rd_d1	(cpu_mondo_rd_d1),
		    .tap_mondo_rd_d1	(tap_mondo_rd_d1),
		    .cpu_mondo_rd_d2	(cpu_mondo_rd_d2),
		    .cpu_mondo_addr_invld_d2(cpu_mondo_addr_invld_d2),
		    .mondo_data_addr_p0_d1(mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1:0]),
		    .io_mondo_data0_din_s(io_mondo_data0_din_s[`IOB_MONDO_DATA_WIDTH-1:0]),
		    .io_mondo_data1_din_s(io_mondo_data1_din_s[`IOB_MONDO_DATA_WIDTH-1:0]),
		    .io_mondo_source_din_s(io_mondo_source_din_s[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .tap_mondo_din_s	(tap_mondo_din_s[63:0]),
		    .mondo_data0_dout_lo(mondo_data0_dout_lo[64:0]),
		    .mondo_data0_dout_hi(mondo_data0_dout_hi[64:0]),
		    .mondo_data1_dout_lo(mondo_data1_dout_lo[64:0]),
		    .mondo_data1_dout_hi(mondo_data1_dout_hi[64:0]),
		    .mondo_source_dout	(mondo_source_dout[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .mondo_busy_dout	(mondo_busy_dout));

   

   c2i_sctrl c2i_sctrl (


			.iob_tap_busy	(iob_tap_busy),
			.cpu_buf_rd	(cpu_buf_rd),
			.tap_sel	(tap_sel),
			.cpu_packet_is_req(cpu_packet_is_req),
			.cpu_packet_type(cpu_packet_type[`UCB_PKT_WIDTH-1:0]),
			.cpu_buf_head_s	(cpu_buf_head_s[`IOB_CPU_BUF_INDEX:0]),
			.srvc_wr_ack	(srvc_wr_ack),
			.cpu_buf_head_ptr(cpu_buf_head_ptr[`IOB_CPU_BUF_INDEX-1:0]),
			.cpu_buf_rd_l	(cpu_buf_rd_l),
			.c2i_packet_vld	(c2i_packet_vld),
			.c2i_packet_is_rd_req(c2i_packet_is_rd_req),
			.c2i_packet_is_wr_req(c2i_packet_is_wr_req),
			.jbi_ucb_sel	(jbi_ucb_sel),
			.clk_ucb_sel	(clk_ucb_sel),
			.dram0_ucb_sel	(dram0_ucb_sel),
			.dram1_ucb_sel	(dram1_ucb_sel),
			.iob_man_ucb_sel(iob_man_ucb_sel),
			.iob_int_ucb_sel(iob_int_ucb_sel),
			.spi_ucb_sel	(spi_ucb_sel),
			.bounce_ucb_sel	(bounce_ucb_sel),
			.rd_nack_ucb_sel(rd_nack_ucb_sel),
			.ucb_buf_acpt	(ucb_buf_acpt),

			.rst_l		(rst_l),
			.clk		(clk),
			.tap_iob_packet_vld(tap_iob_packet_vld),
			.pcx_packet	(pcx_packet[`PCX_WIDTH-1:0]),
			.tap_packet	(tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
			.c2i_packet_addr(c2i_packet_addr[`UCB_ADDR_WIDTH-1:0]),
			.cpu_buf_tail_f	(cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),
			.io_buf_avail	(io_buf_avail),
			.jbi_ucb_buf_acpt(jbi_ucb_buf_acpt),
			.clk_ucb_buf_acpt(clk_ucb_buf_acpt),
			.dram0_ucb_buf_acpt(dram0_ucb_buf_acpt),
			.dram1_ucb_buf_acpt(dram1_ucb_buf_acpt),
			.iob_man_ucb_buf_acpt(iob_man_ucb_buf_acpt),
			.iob_int_ucb_buf_acpt(iob_int_ucb_buf_acpt),
			.spi_ucb_buf_acpt(spi_ucb_buf_acpt),
			.bounce_ucb_buf_acpt(bounce_ucb_buf_acpt),
			.rd_nack_ucb_buf_acpt(rd_nack_ucb_buf_acpt));

   

   c2i_sdp c2i_sdp (


		    .pcx_packet		(pcx_packet[`PCX_WIDTH-1:0]),
		    .tap_packet		(tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .c2i_packet_addr	(c2i_packet_addr[`UCB_ADDR_WIDTH-1:0]),
		    .c2i_packet		(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .c2i_rd_nack_packet	(c2i_rd_nack_packet[`UCB_NOPAY_PKT_WIDTH-1:0]),
		    .wr_ack_io_buf_din	(wr_ack_io_buf_din[`IOB_IO_BUF_WIDTH-1:0]),

		    .clk		(clk),
		    .tap_iob_packet	(tap_iob_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .cpu_buf_dout_lo	(cpu_buf_dout_lo[64:0]),
		    .cpu_buf_dout_hi	(cpu_buf_dout_hi[64:0]),
		    .cpu_buf_rd		(cpu_buf_rd),
		    .tap_sel		(tap_sel),
		    .cpu_packet_is_req	(cpu_packet_is_req),
		    .cpu_packet_type	(cpu_packet_type[`UCB_PKT_WIDTH-1:0]));

   



   ucb_bus_in #(`TAP_IOB_WIDTH,64) tap_ucb_buf
     (


      .stall				(iob_tap_stall),
      .indata_buf_vld			(tap_iob_packet_vld),
      .indata_buf			(tap_iob_packet[`UCB_64PAY_PKT_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .vld				(tap_iob_vld),
      .data				(tap_iob_data[`TAP_IOB_WIDTH-1:0]),
      .stall_a1				(iob_tap_busy));

   



   c2i_buf #(64,`IOB_JBI_WIDTH) jbi_ucb_buf
     (


      .ucb_buf_acpt			(jbi_ucb_buf_acpt),
      .iob_ucb_vld			(iob_jbi_pio_vld),
      .iob_ucb_data			(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(jbi_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(jbi_iob_pio_stall));

   



   c2i_buf #(64,`IOB_CLK_WIDTH) clk_ucb_buf
     (


      .ucb_buf_acpt			(clk_ucb_buf_acpt),
      .iob_ucb_vld			(iob_clk_vld),
      .iob_ucb_data			(iob_clk_data[`IOB_CLK_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(clk_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(clk_iob_stall));

   



   c2i_buf #(64,`IOB_DRAM_WIDTH) dram0_ucb_buf
     (


      .ucb_buf_acpt			(dram0_ucb_buf_acpt),
      .iob_ucb_vld			(iob_dram02_vld),
      .iob_ucb_data			(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(dram0_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(dram02_iob_stall));

   



   c2i_buf #(64,`IOB_DRAM_WIDTH) dram1_ucb_buf
     (


      .ucb_buf_acpt			(dram1_ucb_buf_acpt),
      .iob_ucb_vld			(iob_dram13_vld),
      .iob_ucb_data			(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(dram1_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(dram13_iob_stall));

   



   c2i_buf #(64,`IOB_SPI_WIDTH) spi_ucb_buf
     (


      .ucb_buf_acpt			(spi_ucb_buf_acpt),
      .iob_ucb_vld			(iob_jbi_spi_vld),
      .iob_ucb_data			(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(spi_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(jbi_iob_spi_stall));

   
endmodule
module c2i (

   wr_ack_io_buf_din, ucb_buf_acpt, tap_mondo_dout_d2_f, 
   tap_mondo_acc_seq_d2_f, tap_mondo_acc_addr_invld_d2_f, 
   srvc_wr_ack, rd_nack_ucb_sel, mondo_source_wr_l, mondo_source_din, 
   mondo_data_addr_p1, mondo_data_addr_p0, mondo_data1_wr_lo_l, 
   mondo_data1_wr_hi_l, mondo_data1_din_lo, mondo_data1_din_hi, 
   mondo_data0_wr_lo_l, mondo_data0_wr_hi_l, mondo_data0_din_lo, 
   mondo_data0_din_hi, mondo_busy_wr_p2, mondo_busy_wr_p1, 
   mondo_busy_din_p2, mondo_busy_din_p1, mondo_busy_addr_p2, 
   mondo_busy_addr_p1, mondo_busy_addr_p0, iob_tap_stall, 
   iob_pcx_stall_pq, iob_man_ucb_sel, iob_jbi_spi_vld, 
   iob_jbi_spi_data, iob_jbi_pio_vld, iob_jbi_pio_data, 
   iob_int_ucb_sel, iob_dram13_vld, iob_dram13_data, iob_dram02_vld, 
   iob_dram02_data, iob_clk_vld, iob_clk_data, int_buf_din_raw, 
   cpu_mondo_wr_d2, cpu_buf_wr_l, cpu_buf_tail_ptr, cpu_buf_rd_l, 
   cpu_buf_head_ptr, cpu_buf_din_lo, cpu_buf_din_hi, 
   c2i_rd_nack_packet, c2i_packet_is_wr_req, c2i_packet_is_rd_req, 
   bounce_ucb_sel, cpu_mondo_rd_d2, c2i_packet, c2i_packet_vld, 

   tx_sync, tap_mondo_wr_s, tap_mondo_din_s, tap_mondo_acc_seq_s, 
   tap_mondo_acc_addr_s, tap_iob_vld, tap_iob_data, rx_sync, rst_l, 
   rd_nack_ucb_buf_acpt, pcx_iob_data_rdy_px2, pcx_iob_data_px2, 
   mondo_source_dout, mondo_data1_dout_lo, mondo_data1_dout_hi, 
   mondo_data0_dout_lo, mondo_data0_dout_hi, mondo_busy_dout, 
   jbi_iob_spi_stall, jbi_iob_pio_stall, iob_man_ucb_buf_acpt, 
   iob_int_ucb_buf_acpt, io_mondo_source_din_s, io_mondo_data_wr_s, 
   io_mondo_data_wr_addr_s, io_mondo_data1_din_s, 
   io_mondo_data0_din_s, io_buf_avail, int_buf_hit_hwm, 
   dram13_iob_stall, dram02_iob_stall, cpu_rst_l, cpu_clk, 
   cpu_buf_dout_lo, cpu_buf_dout_hi, clk_iob_stall, clk, 
   bounce_ucb_buf_acpt
   );


   





   input		bounce_ucb_buf_acpt;
   input		clk;
   input		clk_iob_stall;
   input [64:0]		cpu_buf_dout_hi;
   input [64:0]		cpu_buf_dout_lo;
   input		cpu_clk;
   input		cpu_rst_l;
   input		dram02_iob_stall;
   input		dram13_iob_stall;
   input		int_buf_hit_hwm;
   input		io_buf_avail;
   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data0_din_s;
   input [`IOB_MONDO_DATA_WIDTH-1:0]io_mondo_data1_din_s;
   input [`IOB_MONDO_DATA_INDEX-1:0]io_mondo_data_wr_addr_s;
   input		io_mondo_data_wr_s;
   input [`IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s;
   input		iob_int_ucb_buf_acpt;
   input		iob_man_ucb_buf_acpt;
   input		jbi_iob_pio_stall;
   input		jbi_iob_spi_stall;
   input		mondo_busy_dout;
   input [64:0]		mondo_data0_dout_hi;
   input [64:0]		mondo_data0_dout_lo;
   input [64:0]		mondo_data1_dout_hi;
   input [64:0]		mondo_data1_dout_lo;
   input [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_dout;
   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;
   input		pcx_iob_data_rdy_px2;
   input		rd_nack_ucb_buf_acpt;
   input		rst_l;
   input		rx_sync;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_vld;
   input [`IOB_ADDR_WIDTH-1:0]tap_mondo_acc_addr_s;
   input		tap_mondo_acc_seq_s;
   input [63:0]		tap_mondo_din_s;
   input		tap_mondo_wr_s;
   input		tx_sync;





   output		bounce_ucb_sel;
   output		c2i_packet_is_rd_req;
   output		c2i_packet_is_wr_req;
   output [`UCB_NOPAY_PKT_WIDTH-1:0]c2i_rd_nack_packet;
   output [64:0]	cpu_buf_din_hi;
   output [64:0]	cpu_buf_din_lo;
   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_head_ptr;
   output		cpu_buf_rd_l;
   output [`IOB_CPU_BUF_INDEX-1:0]cpu_buf_tail_ptr;
   output		cpu_buf_wr_l;
   output		cpu_mondo_wr_d2;
   output [159:0]	int_buf_din_raw;
   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   output		iob_clk_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   output		iob_dram02_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   output		iob_dram13_vld;
   output		iob_int_ucb_sel;
   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   output		iob_jbi_pio_vld;
   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   output		iob_jbi_spi_vld;
   output		iob_man_ucb_sel;
   output		iob_pcx_stall_pq;
   output		iob_tap_stall;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p1;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_busy_addr_p2;
   output		mondo_busy_din_p1;
   output		mondo_busy_din_p2;
   output		mondo_busy_wr_p1;
   output		mondo_busy_wr_p2;
   output [64:0]	mondo_data0_din_hi;
   output [64:0]	mondo_data0_din_lo;
   output		mondo_data0_wr_hi_l;
   output		mondo_data0_wr_lo_l;
   output [64:0]	mondo_data1_din_hi;
   output [64:0]	mondo_data1_din_lo;
   output		mondo_data1_wr_hi_l;
   output		mondo_data1_wr_lo_l;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p1;
   output [`IOB_MONDO_SRC_WIDTH-1:0]mondo_source_din;
   output		mondo_source_wr_l;
   output		rd_nack_ucb_sel;
   output		srvc_wr_ack;
   output		tap_mondo_acc_addr_invld_d2_f;
   output		tap_mondo_acc_seq_d2_f;
   output [63:0]	tap_mondo_dout_d2_f;
   output		ucb_buf_acpt;
   output [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din;



   output		cpu_mondo_rd_d2;


   output [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;
   output 		c2i_packet_vld;
   


   wire [`UCB_ADDR_WIDTH-1:0]c2i_packet_addr;
   wire			clk_ucb_buf_acpt;
   wire			clk_ucb_sel;
   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_head_s;
   wire			cpu_buf_rd;
   wire [`IOB_CPU_BUF_INDEX:0]cpu_buf_tail_f;
   wire			cpu_mondo_addr_invld_d2;
   wire			cpu_mondo_rd_d1;
   wire			cpu_packet_is_req;
   wire [`UCB_PKT_WIDTH-1:0]cpu_packet_type;
   wire			dram0_ucb_buf_acpt;
   wire			dram0_ucb_sel;
   wire			dram1_ucb_buf_acpt;
   wire			dram1_ucb_sel;
   wire			io_mondo_data_wr;
   wire			iob_tap_busy;
   wire			jbi_ucb_buf_acpt;
   wire			jbi_ucb_sel;
   wire			mondo_addr_creg_mbusy_dec_d1;
   wire			mondo_addr_creg_mdata0_dec_d1;
   wire			mondo_addr_creg_mdata1_dec_d1;
   wire [`IOB_MONDO_DATA_INDEX-1:0]mondo_data_addr_p0_d1;
   wire			mondo_data_bypass_d1;
   wire [`PCX_AD_HI-`PCX_AD_LO:0]pcx_iob_addr;
   wire [`PCX_CP_HI-`PCX_TH_LO:0]pcx_iob_cputhr;
   wire [`PCX_RQ_HI-`PCX_RQ_LO:0]pcx_iob_req;
   wire			pcx_iob_vld;
   wire [`PCX_WIDTH-1:0]pcx_packet;
   wire			spi_ucb_buf_acpt;
   wire			spi_ucb_sel;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_iob_packet;
   wire			tap_iob_packet_vld;
   wire			tap_mondo_rd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]tap_packet;
   wire			tap_sel;

   
   




   c2i_fctrl c2i_fctrl (


			.iob_pcx_stall_pq(iob_pcx_stall_pq),
			.io_mondo_data_wr(io_mondo_data_wr),
			.mondo_data_bypass_d1(mondo_data_bypass_d1),
			.mondo_addr_creg_mdata0_dec_d1(mondo_addr_creg_mdata0_dec_d1),
			.mondo_addr_creg_mdata1_dec_d1(mondo_addr_creg_mdata1_dec_d1),
			.mondo_addr_creg_mbusy_dec_d1(mondo_addr_creg_mbusy_dec_d1),
			.cpu_mondo_rd_d1(cpu_mondo_rd_d1),
			.tap_mondo_rd_d1(tap_mondo_rd_d1),
			.cpu_mondo_rd_d2(cpu_mondo_rd_d2),
			.cpu_mondo_addr_invld_d2(cpu_mondo_addr_invld_d2),
			.mondo_data_addr_p0_d1(mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1:0]),
			.cpu_buf_tail_f	(cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),
			.cpu_mondo_wr_d2(cpu_mondo_wr_d2),
			.tap_mondo_acc_addr_invld_d2_f(tap_mondo_acc_addr_invld_d2_f),
			.tap_mondo_acc_seq_d2_f(tap_mondo_acc_seq_d2_f),
			.mondo_data_addr_p0(mondo_data_addr_p0[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_data_addr_p1(mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_data0_wr_lo_l(mondo_data0_wr_lo_l),
			.mondo_data0_wr_hi_l(mondo_data0_wr_hi_l),
			.mondo_data1_wr_lo_l(mondo_data1_wr_lo_l),
			.mondo_data1_wr_hi_l(mondo_data1_wr_hi_l),
			.mondo_source_wr_l(mondo_source_wr_l),
			.mondo_busy_addr_p0(mondo_busy_addr_p0[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_addr_p1(mondo_busy_addr_p1[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_addr_p2(mondo_busy_addr_p2[`IOB_MONDO_DATA_INDEX-1:0]),
			.mondo_busy_wr_p1(mondo_busy_wr_p1),
			.mondo_busy_wr_p2(mondo_busy_wr_p2),
			.cpu_buf_wr_l	(cpu_buf_wr_l),
			.cpu_buf_tail_ptr(cpu_buf_tail_ptr[`IOB_CPU_BUF_INDEX-1:0]),

			.cpu_rst_l	(cpu_rst_l),
			.cpu_clk	(cpu_clk),
			.tx_sync	(tx_sync),
			.rx_sync	(rx_sync),
			.pcx_iob_data_rdy_px2(pcx_iob_data_rdy_px2),
			.pcx_iob_vld	(pcx_iob_vld),
			.pcx_iob_req	(pcx_iob_req[`PCX_RQ_HI-`PCX_RQ_LO:0]),
			.pcx_iob_addr	(pcx_iob_addr[`PCX_AD_HI-`PCX_AD_LO:0]),
			.pcx_iob_cputhr	(pcx_iob_cputhr[`PCX_CP_HI-`PCX_TH_LO:0]),
			.cpu_buf_head_s	(cpu_buf_head_s[`IOB_CPU_BUF_INDEX:0]),
			.int_buf_hit_hwm(int_buf_hit_hwm),
			.io_mondo_data_wr_s(io_mondo_data_wr_s),
			.io_mondo_data_wr_addr_s(io_mondo_data_wr_addr_s[`IOB_MONDO_DATA_INDEX-1:0]),
			.tap_mondo_acc_addr_s(tap_mondo_acc_addr_s[`IOB_ADDR_WIDTH-1:0]),
			.tap_mondo_acc_seq_s(tap_mondo_acc_seq_s),
			.tap_mondo_wr_s	(tap_mondo_wr_s));

   

   c2i_fdp c2i_fdp (


		    .pcx_iob_vld	(pcx_iob_vld),
		    .pcx_iob_req	(pcx_iob_req[`PCX_RQ_HI-`PCX_RQ_LO:0]),
		    .pcx_iob_addr	(pcx_iob_addr[`PCX_AD_HI-`PCX_AD_LO:0]),
		    .pcx_iob_cputhr	(pcx_iob_cputhr[`PCX_CP_HI-`PCX_TH_LO:0]),
		    .int_buf_din_raw	(int_buf_din_raw[159:0]),
		    .tap_mondo_dout_d2_f(tap_mondo_dout_d2_f[63:0]),
		    .mondo_data0_din_lo	(mondo_data0_din_lo[64:0]),
		    .mondo_data0_din_hi	(mondo_data0_din_hi[64:0]),
		    .mondo_data1_din_lo	(mondo_data1_din_lo[64:0]),
		    .mondo_data1_din_hi	(mondo_data1_din_hi[64:0]),
		    .mondo_source_din	(mondo_source_din[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .mondo_busy_din_p1	(mondo_busy_din_p1),
		    .mondo_busy_din_p2	(mondo_busy_din_p2),
		    .cpu_buf_din_lo	(cpu_buf_din_lo[64:0]),
		    .cpu_buf_din_hi	(cpu_buf_din_hi[64:0]),

		    .cpu_clk		(cpu_clk),
		    .tx_sync		(tx_sync),
		    .rx_sync		(rx_sync),
		    .pcx_iob_data_px2	(pcx_iob_data_px2[`PCX_WIDTH-1:0]),
		    .io_mondo_data_wr	(io_mondo_data_wr),
		    .mondo_data_bypass_d1(mondo_data_bypass_d1),
		    .mondo_addr_creg_mdata0_dec_d1(mondo_addr_creg_mdata0_dec_d1),
		    .mondo_addr_creg_mdata1_dec_d1(mondo_addr_creg_mdata1_dec_d1),
		    .mondo_addr_creg_mbusy_dec_d1(mondo_addr_creg_mbusy_dec_d1),
		    .cpu_mondo_rd_d1	(cpu_mondo_rd_d1),
		    .tap_mondo_rd_d1	(tap_mondo_rd_d1),
		    .cpu_mondo_rd_d2	(cpu_mondo_rd_d2),
		    .cpu_mondo_addr_invld_d2(cpu_mondo_addr_invld_d2),
		    .mondo_data_addr_p0_d1(mondo_data_addr_p0_d1[`IOB_MONDO_DATA_INDEX-1:0]),
		    .io_mondo_data0_din_s(io_mondo_data0_din_s[`IOB_MONDO_DATA_WIDTH-1:0]),
		    .io_mondo_data1_din_s(io_mondo_data1_din_s[`IOB_MONDO_DATA_WIDTH-1:0]),
		    .io_mondo_source_din_s(io_mondo_source_din_s[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .tap_mondo_din_s	(tap_mondo_din_s[63:0]),
		    .mondo_data0_dout_lo(mondo_data0_dout_lo[64:0]),
		    .mondo_data0_dout_hi(mondo_data0_dout_hi[64:0]),
		    .mondo_data1_dout_lo(mondo_data1_dout_lo[64:0]),
		    .mondo_data1_dout_hi(mondo_data1_dout_hi[64:0]),
		    .mondo_source_dout	(mondo_source_dout[`IOB_MONDO_SRC_WIDTH-1:0]),
		    .mondo_busy_dout	(mondo_busy_dout));

   

   c2i_sctrl c2i_sctrl (


			.iob_tap_busy	(iob_tap_busy),
			.cpu_buf_rd	(cpu_buf_rd),
			.tap_sel	(tap_sel),
			.cpu_packet_is_req(cpu_packet_is_req),
			.cpu_packet_type(cpu_packet_type[`UCB_PKT_WIDTH-1:0]),
			.cpu_buf_head_s	(cpu_buf_head_s[`IOB_CPU_BUF_INDEX:0]),
			.srvc_wr_ack	(srvc_wr_ack),
			.cpu_buf_head_ptr(cpu_buf_head_ptr[`IOB_CPU_BUF_INDEX-1:0]),
			.cpu_buf_rd_l	(cpu_buf_rd_l),
			.c2i_packet_vld	(c2i_packet_vld),
			.c2i_packet_is_rd_req(c2i_packet_is_rd_req),
			.c2i_packet_is_wr_req(c2i_packet_is_wr_req),
			.jbi_ucb_sel	(jbi_ucb_sel),
			.clk_ucb_sel	(clk_ucb_sel),
			.dram0_ucb_sel	(dram0_ucb_sel),
			.dram1_ucb_sel	(dram1_ucb_sel),
			.iob_man_ucb_sel(iob_man_ucb_sel),
			.iob_int_ucb_sel(iob_int_ucb_sel),
			.spi_ucb_sel	(spi_ucb_sel),
			.bounce_ucb_sel	(bounce_ucb_sel),
			.rd_nack_ucb_sel(rd_nack_ucb_sel),
			.ucb_buf_acpt	(ucb_buf_acpt),

			.rst_l		(rst_l),
			.clk		(clk),
			.tap_iob_packet_vld(tap_iob_packet_vld),
			.pcx_packet	(pcx_packet[`PCX_WIDTH-1:0]),
			.tap_packet	(tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
			.c2i_packet_addr(c2i_packet_addr[`UCB_ADDR_WIDTH-1:0]),
			.cpu_buf_tail_f	(cpu_buf_tail_f[`IOB_CPU_BUF_INDEX:0]),
			.io_buf_avail	(io_buf_avail),
			.jbi_ucb_buf_acpt(jbi_ucb_buf_acpt),
			.clk_ucb_buf_acpt(clk_ucb_buf_acpt),
			.dram0_ucb_buf_acpt(dram0_ucb_buf_acpt),
			.dram1_ucb_buf_acpt(dram1_ucb_buf_acpt),
			.iob_man_ucb_buf_acpt(iob_man_ucb_buf_acpt),
			.iob_int_ucb_buf_acpt(iob_int_ucb_buf_acpt),
			.spi_ucb_buf_acpt(spi_ucb_buf_acpt),
			.bounce_ucb_buf_acpt(bounce_ucb_buf_acpt),
			.rd_nack_ucb_buf_acpt(rd_nack_ucb_buf_acpt));

   

   c2i_sdp c2i_sdp (


		    .pcx_packet		(pcx_packet[`PCX_WIDTH-1:0]),
		    .tap_packet		(tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .c2i_packet_addr	(c2i_packet_addr[`UCB_ADDR_WIDTH-1:0]),
		    .c2i_packet		(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .c2i_rd_nack_packet	(c2i_rd_nack_packet[`UCB_NOPAY_PKT_WIDTH-1:0]),
		    .wr_ack_io_buf_din	(wr_ack_io_buf_din[`IOB_IO_BUF_WIDTH-1:0]),

		    .clk		(clk),
		    .tap_iob_packet	(tap_iob_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .cpu_buf_dout_lo	(cpu_buf_dout_lo[64:0]),
		    .cpu_buf_dout_hi	(cpu_buf_dout_hi[64:0]),
		    .cpu_buf_rd		(cpu_buf_rd),
		    .tap_sel		(tap_sel),
		    .cpu_packet_is_req	(cpu_packet_is_req),
		    .cpu_packet_type	(cpu_packet_type[`UCB_PKT_WIDTH-1:0]));

   



   ucb_bus_in #(`TAP_IOB_WIDTH,64) tap_ucb_buf
     (


      .stall				(iob_tap_stall),
      .indata_buf_vld			(tap_iob_packet_vld),
      .indata_buf			(tap_iob_packet[`UCB_64PAY_PKT_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .vld				(tap_iob_vld),
      .data				(tap_iob_data[`TAP_IOB_WIDTH-1:0]),
      .stall_a1				(iob_tap_busy));

   



   c2i_buf #(64,`IOB_JBI_WIDTH) jbi_ucb_buf
     (


      .ucb_buf_acpt			(jbi_ucb_buf_acpt),
      .iob_ucb_vld			(iob_jbi_pio_vld),
      .iob_ucb_data			(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(jbi_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(jbi_iob_pio_stall));

   



   c2i_buf #(64,`IOB_CLK_WIDTH) clk_ucb_buf
     (


      .ucb_buf_acpt			(clk_ucb_buf_acpt),
      .iob_ucb_vld			(iob_clk_vld),
      .iob_ucb_data			(iob_clk_data[`IOB_CLK_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(clk_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(clk_iob_stall));

   



   c2i_buf #(64,`IOB_DRAM_WIDTH) dram0_ucb_buf
     (


      .ucb_buf_acpt			(dram0_ucb_buf_acpt),
      .iob_ucb_vld			(iob_dram02_vld),
      .iob_ucb_data			(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(dram0_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(dram02_iob_stall));

   



   c2i_buf #(64,`IOB_DRAM_WIDTH) dram1_ucb_buf
     (


      .ucb_buf_acpt			(dram1_ucb_buf_acpt),
      .iob_ucb_vld			(iob_dram13_vld),
      .iob_ucb_data			(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(dram1_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(dram13_iob_stall));

   



   c2i_buf #(64,`IOB_SPI_WIDTH) spi_ucb_buf
     (


      .ucb_buf_acpt			(spi_ucb_buf_acpt),
      .iob_ucb_vld			(iob_jbi_spi_vld),
      .iob_ucb_data			(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .c2i_packet_vld			(c2i_packet_vld),
      .ucb_sel				(spi_ucb_sel),
      .c2i_packet			(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .ucb_iob_stall			(jbi_iob_spi_stall));

   
endmodule