data/full_repos/permissive/489075769/write_address_master.v
1: b"%Error: data/full_repos/permissive/489075769/write_address_master.v:19: Can't find definition of scope/variable: 'write_address_slave'\n  if (o_AWVALID && write_address_slave.AWREADY) \n                   ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module write_address_master(ACLK,ARESETn,i_AWVALID, o_AWVALID, i_AWADDR, o_AWADDR, AWPROT);
	input ACLK;
	input ARESETn;
	input i_AWVALID;
	output reg o_AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
	always @(posedge ARESETn) begin
		o_AWADDR <= 0;
		o_AWVALID <=0;
	end
	
	always @(posedge ACLK) begin
		if(i_AWVALID)
		o_AWVALID=1;

		if (o_AWVALID && write_address_slave.AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 0;
	
	end
endmodule
module write_address_master(ACLK,ARESETn,i_AWVALID, o_AWVALID, i_AWADDR, o_AWADDR, AWPROT);

	input ACLK;
	input ARESETn;
	input i_AWVALID;
	output reg o_AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
	always @(posedge ARESETn) begin
		o_AWADDR <= 0;
		o_AWVALID <=0;
	end
	
	always @(posedge ACLK) begin
		if(i_AWVALID)
		o_AWVALID=1;

		if (o_AWVALID && write_address_slave.AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 0;
	
	end
endmodule