data/full_repos/permissive/485085993/verilog/rtl/logical_tile_io_mode_io_.v
1: b"%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_io_mode_io_.v:50: Can't resolve module reference: 'logical_tile_io_mode_physical__iopad'\n logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module logical_tile_io_mode_io_(gfpga_pad_GPIO_PAD,
                                io_outpad,
                                bl,
                                wl,
                                io_inpad);

inout [0:0] gfpga_pad_GPIO_PAD;

input [0:0] io_outpad;

input [0:0] bl;

input [0:0] wl;

output [0:0] io_inpad;


wire [0:0] io_outpad;
wire [0:0] io_inpad;







wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;






	logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD),
		.iopad_outpad(direct_interc_1_out),
		.bl(bl),
		.wl(wl),
		.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad));

	direct_interc direct_interc_0_ (
		.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
		.out(io_inpad));

	direct_interc direct_interc_1_ (
		.in(io_outpad),
		.out(direct_interc_1_out));

endmodule
module logical_tile_io_mode_io_(gfpga_pad_GPIO_PAD,
                                io_outpad,
                                bl,
                                wl,
                                io_inpad);


inout [0:0] gfpga_pad_GPIO_PAD;

input [0:0] io_outpad;

input [0:0] bl;

input [0:0] wl;

output [0:0] io_inpad;


wire [0:0] io_outpad;
wire [0:0] io_inpad;







wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;






	logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD),
		.iopad_outpad(direct_interc_1_out),
		.bl(bl),
		.wl(wl),
		.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad));

	direct_interc direct_interc_0_ (
		.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
		.out(io_inpad));

	direct_interc direct_interc_1_ (
		.in(io_outpad),
		.out(direct_interc_1_out));

endmodule