data/full_repos/permissive/48602886/src/device/keyboard/keyboard.sv
1: b"%Error: data/full_repos/permissive/48602886/src/device/keyboard/keyboard.sv:66: Cannot find file containing module: 'keyboard_ps2_receiver'\n keyboard_ps2_receiver PS2_IF_KEYBOARD(\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48602886/src/device/keyboard,data/full_repos/permissive/48602886/keyboard_ps2_receiver\n             data/full_repos/permissive/48602886/src/device/keyboard,data/full_repos/permissive/48602886/keyboard_ps2_receiver.v\n             data/full_repos/permissive/48602886/src/device/keyboard,data/full_repos/permissive/48602886/keyboard_ps2_receiver.sv\n             keyboard_ps2_receiver\n             keyboard_ps2_receiver.v\n             keyboard_ps2_receiver.sv\n             obj_dir/keyboard_ps2_receiver\n             obj_dir/keyboard_ps2_receiver.v\n             obj_dir/keyboard_ps2_receiver.sv\n%Error: data/full_repos/permissive/48602886/src/device/keyboard/keyboard.sv:90: Cannot find file containing module: 'keyboard_sync_fifo'\n keyboard_sync_fifo #(8, 32, 5) KEYBOARD_DATA_FIFO(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module keyboard(
		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iDEV_REQ,
		output wire oDEV_BUSY,
		input wire iDEV_RW,
		input wire [31:0] iDEV_ADDR,
		input wire [31:0] iDEV_DATA,

		output wire oDEV_REQ,
		input wire iDEV_BUSY,
		output wire [31:0] oDEV_DATA,

		output wire oDEV_IRQ_REQ,
		input wire iDEV_IRQ_BUSY,
		input wire iDEV_IRQ_ACK,

		input wire iPS2_CLOCK,
		input wire iPS2_DATA
	);

	localparam PL_INTFLAG_ADDR =  32'h00000004;



	reg b_req;
	reg [31:0] b_data;

	wire ps2_if_req;
	wire [7:0] ps2_if_data;

	wire specialmemory_use_condition;
	wire queue_write_condition;
	wire data_rd_condition;
	wire irq_rd_condition;

	wire [31:0] special_memory_rd_data;

	wire data_fifo_full;
	wire data_fifo_empty;
	wire [7:0] data_fifo_data;

	wire irq_counter_full;
	wire irq_counter_empty;


	keyboard_ps2_receiver PS2_IF_KEYBOARD(
		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.oPS2MOD_REQ(ps2_if_req),
		.oPS2MOD_DATA(ps2_if_data),

		.iPS2_CLOCK(iPS2_CLOCK),
		.iPS2_DATA(iPS2_DATA)
	);


	assign queue_write_condition = ps2_if_req && !data_fifo_full;
	assign data_rd_condition = (iDEV_REQ && iDEV_ADDR == 32'h00000000);
	assign irq_rd_condition = !irq_counter_empty && !iDEV_IRQ_BUSY;



	wire [4:0] fifo_counter;
	keyboard_sync_fifo #(8, 32, 5) KEYBOARD_DATA_FIFO(
		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(fifo_counter),
		.iWR_EN(queue_write_condition),
		.iWR_DATA(ps2_if_data),
		.oWR_FULL(data_fifo_full),
		.iRD_EN(data_rd_condition && !data_fifo_empty),
		.oRD_DATA(data_fifo_data),
		.oRD_EMPTY(data_fifo_empty)
	);


	reg b_irq_state;
	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_irq_state <= 1'b0;
		end
		else if(iRESET_SYNC)begin
			b_irq_state <= 1'b0;
		end
		else begin
			case(b_irq_state)
				1'b0:
					begin
						if(queue_write_condition)begin
							b_irq_state <= 1'b1;
						end
					end
				1'b1:
					begin
						if(iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR)begin
							b_irq_state <= 1'b0;
						end
					end
			endcase
		end
	end




	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else begin
			b_req <= (iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR) || data_rd_condition;
			b_data <= (iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR)? {27'h0, fifo_counter} : ((!data_fifo_empty)? {{23{1'b0}}, 1'b1, data_fifo_data} : {32{1'b0}});
		end
	end



	assign oDEV_BUSY = iDEV_BUSY;
	assign oDEV_REQ = b_req;
	assign oDEV_DATA = b_data;
	assign oDEV_IRQ_REQ = !iDEV_IRQ_BUSY && b_irq_state;

endmodule
module keyboard(
		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iDEV_REQ,
		output wire oDEV_BUSY,
		input wire iDEV_RW,
		input wire [31:0] iDEV_ADDR,
		input wire [31:0] iDEV_DATA,

		output wire oDEV_REQ,
		input wire iDEV_BUSY,
		output wire [31:0] oDEV_DATA,

		output wire oDEV_IRQ_REQ,
		input wire iDEV_IRQ_BUSY,
		input wire iDEV_IRQ_ACK,

		input wire iPS2_CLOCK,
		input wire iPS2_DATA
	);


	localparam PL_INTFLAG_ADDR =  32'h00000004;



	reg b_req;
	reg [31:0] b_data;

	wire ps2_if_req;
	wire [7:0] ps2_if_data;

	wire specialmemory_use_condition;
	wire queue_write_condition;
	wire data_rd_condition;
	wire irq_rd_condition;

	wire [31:0] special_memory_rd_data;

	wire data_fifo_full;
	wire data_fifo_empty;
	wire [7:0] data_fifo_data;

	wire irq_counter_full;
	wire irq_counter_empty;


	keyboard_ps2_receiver PS2_IF_KEYBOARD(
		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.oPS2MOD_REQ(ps2_if_req),
		.oPS2MOD_DATA(ps2_if_data),

		.iPS2_CLOCK(iPS2_CLOCK),
		.iPS2_DATA(iPS2_DATA)
	);


	assign queue_write_condition = ps2_if_req && !data_fifo_full;
	assign data_rd_condition = (iDEV_REQ && iDEV_ADDR == 32'h00000000);
	assign irq_rd_condition = !irq_counter_empty && !iDEV_IRQ_BUSY;



	wire [4:0] fifo_counter;
	keyboard_sync_fifo #(8, 32, 5) KEYBOARD_DATA_FIFO(
		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(fifo_counter),
		.iWR_EN(queue_write_condition),
		.iWR_DATA(ps2_if_data),
		.oWR_FULL(data_fifo_full),
		.iRD_EN(data_rd_condition && !data_fifo_empty),
		.oRD_DATA(data_fifo_data),
		.oRD_EMPTY(data_fifo_empty)
	);


	reg b_irq_state;
	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_irq_state <= 1'b0;
		end
		else if(iRESET_SYNC)begin
			b_irq_state <= 1'b0;
		end
		else begin
			case(b_irq_state)
				1'b0:
					begin
						if(queue_write_condition)begin
							b_irq_state <= 1'b1;
						end
					end
				1'b1:
					begin
						if(iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR)begin
							b_irq_state <= 1'b0;
						end
					end
			endcase
		end
	end




	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else begin
			b_req <= (iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR) || data_rd_condition;
			b_data <= (iDEV_REQ && !iDEV_RW && iDEV_ADDR == PL_INTFLAG_ADDR)? {27'h0, fifo_counter} : ((!data_fifo_empty)? {{23{1'b0}}, 1'b1, data_fifo_data} : {32{1'b0}});
		end
	end



	assign oDEV_BUSY = iDEV_BUSY;
	assign oDEV_REQ = b_req;
	assign oDEV_DATA = b_data;
	assign oDEV_IRQ_REQ = !iDEV_IRQ_BUSY && b_irq_state;

endmodule