data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv
1: b'%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:1: Unsupported: classes\nclass riscv_driver extends uvm_driver#(riscv_transaction);\n^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass riscv_driver extends uvm_driver#(riscv_transaction);\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:2: Define or directive not defined: \'`uvm_component_utils\'\n  `uvm_component_utils(riscv_driver)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:4: Unsupported: virtual data type\n  virtual control_if ctrl_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:5: Unsupported: virtual data type\n  virtual dualport_bus instr_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:6: Unsupported: virtual data type\n  virtual dualport_bus mem_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:8: Unsupported: new constructor\n  function new(string name, uvm_component parent);\n           ^~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:8: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function new(string name, uvm_component parent);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:12: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void build_phase(uvm_phase phase);\n                                      ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:15: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual control_if)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:17: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:19: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task run_phase(uvm_phase phase);\n                           ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:29: syntax error, unexpected IDENTIFIER\n    riscv_transaction rv_tx;\n                      ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:32: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:34: syntax error, unexpected \'@\'\n      @(negedge ctrl_vif.clk) begin\n      ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:42: Define or directive not defined: \'`uvm_info\'\n      `uvm_info("rv_driver", $sformatf("and %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:42: syntax error, unexpected \',\'\n      `uvm_info("rv_driver", $sformatf("and %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n                           ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:46: Define or directive not defined: \'`uvm_info\'\n      `uvm_info("rv_driver", $sformatf("or %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:46: syntax error, unexpected \',\'\n      `uvm_info("rv_driver", $sformatf("or %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n                           ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:50: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("xor %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:50: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("xor %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:54: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("add %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:54: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("add %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:58: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("sub %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:58: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("sub %d %d to %d", rv_tx.rs1,rv_tx.rs2,rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:62: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("andi %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:62: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("andi %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:66: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("ori %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:66: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("ori %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:70: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("xori %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:70: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("xori %d with %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:74: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("store to address %d + %d from %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rs2), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:74: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("store to address %d + %d from %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rs2), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:78: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("load from address %d + %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:78: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("load from address %d + %d to %d", rv_tx.rs1,$signed(rv_tx.imm),rv_tx.rd), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:82: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("check equ of %d and %d and jump to %d", rv_tx.rs1,rv_tx.rs2, $signed({rv_tx.imm_jal[12], rv_tx.imm[11:1], 1\'b0})), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:82: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("check equ of %d and %d and jump to %d", rv_tx.rs1,rv_tx.rs2, $signed({rv_tx.imm_jal[12], rv_tx.imm[11:1], 1\'b0})), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:87: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_driver", $sformatf("jump to %d", $signed({rv_tx.imm_jal[20:12], rv_tx.imm[11:1], 1\'b0})), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:87: syntax error, unexpected \',\'\n            `uvm_info("rv_driver", $sformatf("jump to %d", $signed({rv_tx.imm_jal[20:12], rv_tx.imm[11:1], 1\'b0})), UVM_LOW);\n                                 ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:95: Define or directive not defined: \'`uvm_info\'\n        `uvm_info("rv_driver", $sformatf("instr_vif.rd_data:%x", instr_vif.rd_data), UVM_LOW);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:95: syntax error, unexpected \',\'\n        `uvm_info("rv_driver", $sformatf("instr_vif.rd_data:%x", instr_vif.rd_data), UVM_LOW);\n                             ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_driver.sv:101: syntax error, unexpected end\n    end\n    ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    void'(uvm_resource_db#(virtual control_if)::read_by_name
      (.scope("ifs"), .name("control_if"), .val(ctrl_vif)));
    void'(uvm_resource_db#(virtual dualport_bus)::read_by_name
      (.scope("ifs"), .name("dualport_bus_instr"), .val(instr_vif)));
    void'(uvm_resource_db#(virtual dualport_bus)::read_by_name
      (.scope("ifs"), .name("dualport_bus_mem"), .val(mem_vif)));

  endfunction
function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    void'(uvm_resource_db#(virtual control_if)::read_by_name
      (.scope("ifs"), .name("control_if"), .val(ctrl_vif)));
    void'(uvm_resource_db#(virtual dualport_bus)::read_by_name
      (.scope("ifs"), .name("dualport_bus_instr"), .val(instr_vif)));
    void'(uvm_resource_db#(virtual dualport_bus)::read_by_name
      (.scope("ifs"), .name("dualport_bus_mem"), .val(mem_vif)));

  endfunction