data/full_repos/permissive/501470173/verilog/rtl/natalius_processor.v
1: b"%Error: data/full_repos/permissive/501470173/verilog/rtl/natalius_processor.v:60: Cannot find file containing module: 'control_unit'\ncontrol_unit control_unit_i(clk,rst,instruction,z,c,port_addr,write_e,read_e,insel,we,raa,rab,wa,opalu,sh,selpc,ldpc,ldflag,ninst_addr,selk,KTE,stack_addr,wr_en,rd_en,imm,selimm);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501470173/verilog/rtl,data/full_repos/permissive/501470173/control_unit\n             data/full_repos/permissive/501470173/verilog/rtl,data/full_repos/permissive/501470173/control_unit.v\n             data/full_repos/permissive/501470173/verilog/rtl,data/full_repos/permissive/501470173/control_unit.sv\n             control_unit\n             control_unit.v\n             control_unit.sv\n             obj_dir/control_unit\n             obj_dir/control_unit.v\n             obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/501470173/verilog/rtl/natalius_processor.v:61: Cannot find file containing module: 'data_path'\ndata_path data_path_i(clk,rst,data_in,insel,we,raa,rab,wa,opalu,sh,selpc,selk,ldpc,ldflag,wr_en,rd_en,ninst_addr,KTE,imm,selimm, data_out,inst_addr,stack_addr,z,c);\n^~~~~~~~~\n%Error: data/full_repos/permissive/501470173/verilog/rtl/natalius_processor.v:62: Cannot find file containing module: 'dualport_sram'\ndualport_sram inst_mem(\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module natalius_processor(
    input clk,
    input rst,
    output [7:0] port_addr,
    output read_e,
    output write_e,
    input [7:0] data_in,
    output [7:0] data_out,    

    input csb0,
    input web0,
    input [1:0]   wmask0,
    input [10:0]  addr0,
    input [15:0]  din0,
    output [15:0] dout0,
    input   csb1
    );

wire z,c;
wire insel;
wire we;
wire [2:0] raa;
wire [2:0] rab;
wire [2:0] wa;
wire [2:0] opalu;
wire [2:0] sh;
wire selpc;
wire ldpc;
wire ldflag;
wire [10:0] ninst_addr;
wire selk;
wire [7:0] KTE;
wire [10:0] stack_addr;
wire wr_en, rd_en;
wire [7:0] imm;
wire selimm;
wire [15:0] instruction;
wire [10:0] inst_addr;

control_unit control_unit_i(clk,rst,instruction,z,c,port_addr,write_e,read_e,insel,we,raa,rab,wa,opalu,sh,selpc,ldpc,ldflag,ninst_addr,selk,KTE,stack_addr,wr_en,rd_en,imm,selimm);
data_path data_path_i(clk,rst,data_in,insel,we,raa,rab,wa,opalu,sh,selpc,selk,ldpc,ldflag,wr_en,rd_en,ninst_addr,KTE,imm,selimm, data_out,inst_addr,stack_addr,z,c);
dualport_sram inst_mem(

    .clk0(clk),
    .csb0(csb0),
    .web0(web0),
    .wmask0(wmask0),
    .addr0(addr0[10:0]),
    .din0(din0),
    .dout0(dout0),
    .clk1(clk),

    .csb1(csb1),
    .addr1(inst_addr[10:0]),
    .dout1(instruction)
  );


endmodule
module natalius_processor(
    input clk,
    input rst,
    output [7:0] port_addr,
    output read_e,
    output write_e,
    input [7:0] data_in,
    output [7:0] data_out,    

    input csb0,
    input web0,
    input [1:0]   wmask0,
    input [10:0]  addr0,
    input [15:0]  din0,
    output [15:0] dout0,
    input   csb1
    );


wire z,c;
wire insel;
wire we;
wire [2:0] raa;
wire [2:0] rab;
wire [2:0] wa;
wire [2:0] opalu;
wire [2:0] sh;
wire selpc;
wire ldpc;
wire ldflag;
wire [10:0] ninst_addr;
wire selk;
wire [7:0] KTE;
wire [10:0] stack_addr;
wire wr_en, rd_en;
wire [7:0] imm;
wire selimm;
wire [15:0] instruction;
wire [10:0] inst_addr;

control_unit control_unit_i(clk,rst,instruction,z,c,port_addr,write_e,read_e,insel,we,raa,rab,wa,opalu,sh,selpc,ldpc,ldflag,ninst_addr,selk,KTE,stack_addr,wr_en,rd_en,imm,selimm);
data_path data_path_i(clk,rst,data_in,insel,we,raa,rab,wa,opalu,sh,selpc,selk,ldpc,ldflag,wr_en,rd_en,ninst_addr,KTE,imm,selimm, data_out,inst_addr,stack_addr,z,c);
dualport_sram inst_mem(

    .clk0(clk),
    .csb0(csb0),
    .web0(web0),
    .wmask0(wmask0),
    .addr0(addr0[10:0]),
    .din0(din0),
    .dout0(dout0),
    .clk1(clk),

    .csb1(csb1),
    .addr1(inst_addr[10:0]),
    .dout1(instruction)
  );


endmodule