data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#0  value1 = 4\'b0000; value2 = 4\'b0001; carry_in = 1\'b0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b0010; value2 = 4\'b0011; carry_in = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b0100; value2 = 4\'b0101; carry_in = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b0110; value2 = 4\'b0111; carry_in = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b1000; value2 = 4\'b1001; carry_in = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b1010; value2 = 4\'b1011; carry_in = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b1100; value2 = 4\'b1101; carry_in = 1\'b0; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 4\'b1110; value2 = 4\'b1111; carry_in = 1\'b1;\n^\n%Error: data/full_repos/permissive/458134463/Modules/adder_4bit_tb.v:30: Unsupported or unknown PLI call: $monitor\n$monitor("Time: %3d, value1: %4b(%2d), value2: %4b(%2d), carry_in: %1b, sum: %4b(%2d), carry_out: %1b, overflow: %1b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_4bit_tb();

reg signed [3:0] value1;
reg signed [3:0] value2;
reg carry_in;

wire signed [3:0] sum;
wire carry_out;
wire overflow;


adder_4bit add(value1, value2, sum, carry_out, carry_in, overflow);


initial begin
#0  value1 = 4'b0000; value2 = 4'b0001; carry_in = 1'b0;
#20 value1 = 4'b0010; value2 = 4'b0011; carry_in = 1'b1;
 
#20 value1 = 4'b0100; value2 = 4'b0101; carry_in = 1'b0;
#20 value1 = 4'b0110; value2 = 4'b0111; carry_in = 1'b1;

#20 value1 = 4'b1000; value2 = 4'b1001; carry_in = 1'b0;
#20 value1 = 4'b1010; value2 = 4'b1011; carry_in = 1'b1;

#20 value1 = 4'b1100; value2 = 4'b1101; carry_in = 1'b0; 
#20 value1 = 4'b1110; value2 = 4'b1111; carry_in = 1'b1;
end

initial begin
$monitor("Time: %3d, value1: %4b(%2d), value2: %4b(%2d), carry_in: %1b, sum: %4b(%2d), carry_out: %1b, overflow: %1b", 
			$time, 
			value1, value1, 
			value2, value2, 
			carry_in, 
			sum, sum, 
			carry_out,
			overflow);
end

endmodule
module adder_4bit_tb();


reg signed [3:0] value1;
reg signed [3:0] value2;
reg carry_in;

wire signed [3:0] sum;
wire carry_out;
wire overflow;


adder_4bit add(value1, value2, sum, carry_out, carry_in, overflow);


initial begin
#0  value1 = 4'b0000; value2 = 4'b0001; carry_in = 1'b0;
#20 value1 = 4'b0010; value2 = 4'b0011; carry_in = 1'b1;
 
#20 value1 = 4'b0100; value2 = 4'b0101; carry_in = 1'b0;
#20 value1 = 4'b0110; value2 = 4'b0111; carry_in = 1'b1;

#20 value1 = 4'b1000; value2 = 4'b1001; carry_in = 1'b0;
#20 value1 = 4'b1010; value2 = 4'b1011; carry_in = 1'b1;

#20 value1 = 4'b1100; value2 = 4'b1101; carry_in = 1'b0; 
#20 value1 = 4'b1110; value2 = 4'b1111; carry_in = 1'b1;
end

initial begin
$monitor("Time: %3d, value1: %4b(%2d), value2: %4b(%2d), carry_in: %1b, sum: %4b(%2d), carry_out: %1b, overflow: %1b", 
			$time, 
			value1, value1, 
			value2, value2, 
			carry_in, 
			sum, sum, 
			carry_out,
			overflow);
end

endmodule