data/full_repos/permissive/454159683/mul5bc/mul5bc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454159683/mul5bc/mul5bc.v:12: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 5 bits.\n                                                                       : ... In instance mul5bc\n  if (y[0]) r0 = x;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul5bc/mul5bc.v:13: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n                                                                       : ... In instance mul5bc\n  if (y[1])r1 = {x, 1\'b0};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul5bc/mul5bc.v:14: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                       : ... In instance mul5bc\n  if (y[2]) r2  = {x, 2\'b00};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul5bc/mul5bc.v:15: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                       : ... In instance mul5bc\n  if (y[3]) r3 = {x, 3\'b000};\n               ^\n%Error: Exiting due to 4 warning(s)\n'
module mul5bc(input[4:0] x, y, output[9:0] out);
	reg[8:0] r0, r1, r2, r3, r4;	

	always @(x or y)
	begin
		{r0, r1, r2, r3, r4} = 0;
		if (y[0]) r0 = x;
		if (y[1])r1 = {x, 1'b0};
		if (y[2]) r2  = {x, 2'b00};
		if (y[3]) r3 = {x, 3'b000};
		if (y[4]) r4 = {x, 4'b0000};
	end
	




























	assign out = r0 + r1 + r2 + r3 + r4;
endmodule
module mul5bc(input[4:0] x, y, output[9:0] out);

	reg[8:0] r0, r1, r2, r3, r4;	

	always @(x or y)
	begin
		{r0, r1, r2, r3, r4} = 0;
		if (y[0]) r0 = x;
		if (y[1])r1 = {x, 1'b0};
		if (y[2]) r2  = {x, 2'b00};
		if (y[3]) r3 = {x, 3'b000};
		if (y[4]) r4 = {x, 4'b0000};
	end
	




























	assign out = r0 + r1 + r2 + r3 + r4;
endmodule