data/full_repos/permissive/481069643/Day03/ROM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481069643/Day03/ROM.v:25: Value too large for 1 bit number: 2\n  1\'d2: begin data = ROM[address]; next_state = 2\'d3; end \n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/481069643/Day03/ROM.v:26: Value too large for 1 bit number: 3\n  1\'d3: begin done = 1\'b1; next_state = 0; end \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/481069643/Day03/ROM.v:25: Bit extraction of array[3:0] requires 2 bit index, not 4 bits.\n                                                                   : ... In instance ROM_4xn\n  1\'d2: begin data = ROM[address]; next_state = 2\'d3; end \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/481069643/Day03/ROM.v:22: Operator CASE expects 2 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                   : ... In instance ROM_4xn\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/481069643/Day03/ROM.v:22: Operator CASE expects 2 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                   : ... In instance ROM_4xn\n  case(current_state)\n  ^~~~\n%Error: Exiting due to 5 warning(s)\n'
module ROM_4xn(clk,en,rst,address,data,done);
input [3:0]address;
output  reg [3:0]data;
input rst,clk,en;
output reg done;

reg [3:0]ROM[3:0];
reg [1:0]current_state,next_state;
always@(rst)
begin

ROM[0] = 4'b1001;
ROM[1] = 4'b0100;
ROM[2] = 4'b0001;
end

always @(posedge clk)
begin
 if(rst | !en)
    data = 4'bz;
 else
  case(current_state)
  1'd0: begin done = 1'b0; next_state = 1; end 
  1'd1: if(en) next_state = 2; else next_state = 2'd0;
  1'd2: begin data = ROM[address]; next_state = 2'd3; end 
  1'd3: begin done = 1'b1; next_state = 0; end 
  default: next_state = 0;
  endcase
  
  current_state = next_state;
end 

endmodule
module ROM_4xn(clk,en,rst,address,data,done);

input [3:0]address;
output  reg [3:0]data;
input rst,clk,en;
output reg done;

reg [3:0]ROM[3:0];
reg [1:0]current_state,next_state;
always@(rst)
begin

ROM[0] = 4'b1001;
ROM[1] = 4'b0100;
ROM[2] = 4'b0001;
end

always @(posedge clk)
begin
 if(rst | !en)
    data = 4'bz;
 else
  case(current_state)
  1'd0: begin done = 1'b0; next_state = 1; end 
  1'd1: if(en) next_state = 2; else next_state = 2'd0;
  1'd2: begin data = ROM[address]; next_state = 2'd3; end 
  1'd3: begin done = 1'b1; next_state = 0; end 
  default: next_state = 0;
  endcase
  
  current_state = next_state;
end 

endmodule