data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v:45: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'partialProduct\' generates 16 bits.\n                                                                                        : ... In instance booth\n    finalResult <= partialProduct + multiplier;     \n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v:45: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'multiplier\' generates 16 bits.\n                                                                                        : ... In instance booth\n    finalResult <= partialProduct + multiplier;     \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v:51: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'partialProduct\' generates 16 bits.\n                                                                                        : ... In instance booth\n    finalResult <= partialProduct + multiplier;     \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v:51: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'multiplier\' generates 16 bits.\n                                                                                        : ... In instance booth\n    finalResult <= partialProduct + multiplier;     \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/481490387/lab03/simulation/src/kcw/booth.v:56: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                        : ... In instance booth\n   partialProduct <= finalResult[31:0];  \n                  ^~\n%Error: Exiting due to 5 warning(s)\n'
module booth (
    input  wire        clk  ,
	input  wire        rst_n,
	input  wire [15:0] x    ,
	input  wire [15:0] y    ,
	input  wire        start,
	output reg  [31:0] z    ,
	output wire        busy 
);

reg [15:0] multiplicand;
reg [15:0] multiplier;
reg extraDigit;
reg [15:0] minusMultiplicand;
reg [3:0] count;
reg run;
assign busy = run;

always @(posedge clk or negedge rst_n) begin
	if (start || ~rst_n) begin
		multiplicand <= x;
		multiplier <= y;
		minusMultiplicand <= x;
		minusMultiplicand[15] <= ~multiplicand[15];
		extraDigit <= 0;
		run <= 1;
		count <= 0; 
	end
end

reg [15:0] partialProduct;
reg judgeFlag;
reg [31:0] finalResult;


always @(posedge clk or negedge rst_n) begin


		if(busy)begin
				judgeFlag <= extraDigit - multiplier[0];

			if (judgeFlag == 1) begin
				partialProduct <= multiplicand + partialProduct;
				partialProduct <= partialProduct << 16;
				finalResult <= partialProduct + multiplier;
			end

			else if (judgeFlag == -1) begin
				partialProduct <= minusMultiplicand + partialProduct;
				partialProduct <= partialProduct << 16;
				finalResult <= partialProduct + multiplier;
			end

			extraDigit <= finalResult[0];
			finalResult <= finalResult >> 1;
			partialProduct <= finalResult[31:0];
			multiplier <= finalResult[15:0];
			count <= count + 1;
		end

end

endmodule
module booth (
    input  wire        clk  ,
	input  wire        rst_n,
	input  wire [15:0] x    ,
	input  wire [15:0] y    ,
	input  wire        start,
	output reg  [31:0] z    ,
	output wire        busy 
);


reg [15:0] multiplicand;
reg [15:0] multiplier;
reg extraDigit;
reg [15:0] minusMultiplicand;
reg [3:0] count;
reg run;
assign busy = run;

always @(posedge clk or negedge rst_n) begin
	if (start || ~rst_n) begin
		multiplicand <= x;
		multiplier <= y;
		minusMultiplicand <= x;
		minusMultiplicand[15] <= ~multiplicand[15];
		extraDigit <= 0;
		run <= 1;
		count <= 0; 
	end
end

reg [15:0] partialProduct;
reg judgeFlag;
reg [31:0] finalResult;


always @(posedge clk or negedge rst_n) begin


		if(busy)begin
				judgeFlag <= extraDigit - multiplier[0];

			if (judgeFlag == 1) begin
				partialProduct <= multiplicand + partialProduct;
				partialProduct <= partialProduct << 16;
				finalResult <= partialProduct + multiplier;
			end

			else if (judgeFlag == -1) begin
				partialProduct <= minusMultiplicand + partialProduct;
				partialProduct <= partialProduct << 16;
				finalResult <= partialProduct + multiplier;
			end

			extraDigit <= finalResult[0];
			finalResult <= finalResult >> 1;
			partialProduct <= finalResult[31:0];
			multiplier <= finalResult[15:0];
			count <= count + 1;
		end

end

endmodule