data/full_repos/permissive/417288846/List_1/Task_1/JK_latch.v
data/verilator_xmls/b67a8e9c-17d2-48b4-a686-700d01dd3610.xml
module dec_24(input s1, s2, output o1, o2, o3, o4);
    wire ns1, ns2;

    not (ns1, s1);
    not (ns2, s2);

    and (o1, ns1, ns2);
    and (o2, ns1, s2);
    and (o3, s1, ns2);
    and (o4, s1, s2);
endmodule
module dec_24(input s1, s2, output o1, o2, o3, o4);

    wire ns1, ns2;

    not (ns1, s1);
    not (ns2, s2);

    and (o1, ns1, ns2);
    and (o2, ns1, s2);
    and (o3, s1, ns2);
    and (o4, s1, s2);
endmodule