data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/latch_002_gate.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/latch_002_gate.v:13: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                                                    : ... In instance latch_002_gate\n            mask  = (8\'b 11111111)<<((((8)*(sel)))+(0));\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/latch_002_gate.v:14: Operator AND expects 64 bits on the LHS, but LHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                                                    : ... In instance latch_002_gate\n            data  = ((8\'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/latch_002_gate.v:14: Operator AND expects 64 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                                                                    : ... In instance latch_002_gate\n            data  = ((8\'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));\n                                   ^\n%Error: Exiting due to 3 warning(s)\n'
module latch_002_gate(dword, vect, sel, st);
   output reg [63:0] dword;
   input wire [7:0]  vect;
   input wire [7:0]  sel;
   input wire 	     st;
   reg [63:0] 	     mask;
   reg [63:0] 	     data;
   always @*
     case (|(st))
       1'b 1:
         begin
            mask  = (8'b 11111111)<<((((8)*(sel)))+(0));
            data  = ((8'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));
            dword <= ((dword)&(~(mask)))|(data);
         end
     endcase
endmodule
module latch_002_gate(dword, vect, sel, st);

   output reg [63:0] dword;
   input wire [7:0]  vect;
   input wire [7:0]  sel;
   input wire 	     st;
   reg [63:0] 	     mask;
   reg [63:0] 	     data;
   always @*
     case (|(st))
       1'b 1:
         begin
            mask  = (8'b 11111111)<<((((8)*(sel)))+(0));
            data  = ((8'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0));
            dword <= ((dword)&(~(mask)))|(data);
         end
     endcase
endmodule