data/full_repos/permissive/491934675/ECE251/registerfile/demux.v
data/verilator_xmls/5502264f-8f38-4347-ae8a-100a552f8eda.xml
module demux4in1out(
    input [1:0] sel,
    input [7:0] in0, in1, in2, in3,
    output reg [7:0] out1
);

always@(*)begin
    case(sel)
    2'b00 : out1 = in0;
    2'b01 : out1 = in1;
    2'b10 : out1 = in2;
    2'b11 : out1 = in3;
    endcase
end
endmodule
module demux4in1out(
    input [1:0] sel,
    input [7:0] in0, in1, in2, in3,
    output reg [7:0] out1
);


always@(*)begin
    case(sel)
    2'b00 : out1 = in0;
    2'b01 : out1 = in1;
    2'b10 : out1 = in2;
    2'b11 : out1 = in3;
    endcase
end
endmodule