data/full_repos/permissive/420819839/Basics/NorGate.v
data/verilator_xmls/ea32df53-af43-4fe5-91cc-ed12c34484e9.xml
module top_module(
        input a,
        input b,
        output out );
    assign out = !(a || b);
endmodule
module top_module(
        input a,
        input b,
        output out );

    assign out = !(a || b);
endmodule