data/full_repos/permissive/498662723/Circuits/Sequential Logic/Counters/ece241 2014 q7b (Counter1000).v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/498662723.sv\n             Logic/Counters,data/full_repos/permissive/498662723\n             Logic/Counters,data/full_repos/permissive/498662723.v\n             Logic/Counters,data/full_repos/permissive/498662723.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/498662723\n             obj_dir/Logic/Counters,data/full_repos/permissive/498662723.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/ece241\n%Error: Cannot find file containing module: 2014\n%Error: Cannot find file containing module: q7b\n%Error: Cannot find file containing module: (Counter1000).v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); 
    wire [3:0]Q0;
    wire [3:0]Q1;
    wire [3:0]Q2;
    bcdcount counter0 (clk, reset, c_enable[0], Q0);
    bcdcount counter1 (clk, reset, c_enable[1], Q1);
    bcdcount counter2 (clk, reset, c_enable[2], Q2);
    
    assign c_enable[0] = ~reset;
    assign c_enable[1] = ~reset && (Q0 == 4'd9); 
    assign c_enable[2] = ~reset && (Q0 == 4'd9) && (Q1 == 4'd9);
    
    assign OneHertz = ((Q0 == 4'd9) && (Q1 == 4'd9) && (Q2 == 4'd9)) ? 1'b1 : 1'b0;

endmodule
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);
 
    wire [3:0]Q0;
    wire [3:0]Q1;
    wire [3:0]Q2;
    bcdcount counter0 (clk, reset, c_enable[0], Q0);
    bcdcount counter1 (clk, reset, c_enable[1], Q1);
    bcdcount counter2 (clk, reset, c_enable[2], Q2);
    
    assign c_enable[0] = ~reset;
    assign c_enable[1] = ~reset && (Q0 == 4'd9); 
    assign c_enable[2] = ~reset && (Q0 == 4'd9) && (Q1 == 4'd9);
    
    assign OneHertz = ((Q0 == 4'd9) && (Q1 == 4'd9) && (Q2 == 4'd9)) ? 1'b1 : 1'b0;

endmodule