data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/binary_to_gray.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/binary_to_gray.sv:18: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [N-1:0] A,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/binary_to_gray.sv:19: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [N-1:0] Z\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module binary_to_gray #(
    parameter int N = -1
)(
    input  logic [N-1:0] A,
    output logic [N-1:0] Z
);
    assign Z = A ^ (A >> 1);
endmodule
module binary_to_gray #(
    parameter int N = -1
)(
    input  logic [N-1:0] A,
    output logic [N-1:0] Z
);

    assign Z = A ^ (A >> 1);
endmodule