data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:53: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:54: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:55: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:62: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:63: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:78: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module counter #(
    parameter BITS = 2
)(
    input trigger,
    output [BITS-1:0] count
);
    reg [BITS-1:0] count;


    always @(posedge trigger) begin
        count <= count + 1;
    end


endmodule
module counter #(
    parameter BITS = 2
)(
    input trigger,
    output [BITS-1:0] count
);

    reg [BITS-1:0] count;


    always @(posedge trigger) begin
        count <= count + 1;
    end


endmodule