data/full_repos/permissive/456791631/Proyecto1/Proyecto1.v
data/verilator_xmls/45aed586-429d-4ec0-9c8a-9930add58154.xml
module Proyecto1
(
	input a, b,
	output Yand, Yor, Ynot, Ynand, Ynor
);

assign Yand = a & b;
assign Yor = a | b;
assign Ynot = ~a;
assign Ynand = ~(a & b);
assign Ynor = ~(a | b);

endmodule
module Proyecto1
(
	input a, b,
	output Yand, Yor, Ynot, Ynand, Ynor
);


assign Yand = a & b;
assign Yor = a | b;
assign Ynot = ~a;
assign Ynand = ~(a & b);
assign Ynor = ~(a | b);

endmodule