data/full_repos/permissive/455874613/Projects/ModuleSmartHomeSystem/AdderSubtractor32bit.v
data/verilator_xmls/8bb353c9-e153-4bde-a1e9-418160e8226e.xml
module AdderSubtractor32x32 (
	input  [31:0] A    ,
	input  [31:0] B    ,
	input         sel  ,
	output [31:0] S
);




		reg [31:0] s2;
		always @(sel or A or B)
		if(sel)
			begin
				s2=A-B;
			end
		else
			begin
				s2=A+B;
			end
		assign S=s2;
endmodule
module AdderSubtractor32x32 (
	input  [31:0] A    ,
	input  [31:0] B    ,
	input         sel  ,
	output [31:0] S
);





		reg [31:0] s2;
		always @(sel or A or B)
		if(sel)
			begin
				s2=A-B;
			end
		else
			begin
				s2=A+B;
			end
		assign S=s2;
endmodule