data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter/A2Q2_johnson_counter_tb.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter/A2Q2_johnson_counter_tb.v:1: Cannot find include file: A2Q2_johnson_counter.v\n`include "A2Q2_johnson_counter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter,data/full_repos/permissive/450205124/A2Q2_johnson_counter.v\n             data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter,data/full_repos/permissive/450205124/A2Q2_johnson_counter.v.v\n             data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter,data/full_repos/permissive/450205124/A2Q2_johnson_counter.v.sv\n             A2Q2_johnson_counter.v\n             A2Q2_johnson_counter.v.v\n             A2Q2_johnson_counter.v.sv\n             obj_dir/A2Q2_johnson_counter.v\n             obj_dir/A2Q2_johnson_counter.v.v\n             obj_dir/A2Q2_johnson_counter.v.sv\n%Error: data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter/A2Q2_johnson_counter_tb.v:8: Unsupported or unknown PLI call: $monitor\n        $monitor("Time: %3d | %b", $time, q);  \n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter/A2Q2_johnson_counter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module johnson_counter_tb();
    reg clk;
    wire[7:0] q;
    johnson_counter JC(q,clk);
    initial begin
        clk = 0;
        $monitor("Time: %3d | %b", $time, q);
        repeat(32) begin
            #5 clk = ~clk;
        end
        $finish;
    end
endmodule
module johnson_counter_tb();

    reg clk;
    wire[7:0] q;
    johnson_counter JC(q,clk);
    initial begin
        clk = 0;
        $monitor("Time: %3d | %b", $time, q);
        repeat(32) begin
            #5 clk = ~clk;
        end
        $finish;
    end
endmodule