data/full_repos/permissive/435516446/MIPS/DataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:51: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h20\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[20]=32\'b00100000;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:52: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h42\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[21]=32\'b01000010;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[22]=32\'b00000000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:54: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[23]=32\'b00000011;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:58: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[25]=32\'b00001000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:59: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[26]=32\'b00000000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:60: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[27]=32\'b00000000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/DataMemory.v:61: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h14\' generates 32 bits.\n                                                                         : ... In instance DataMemory\n memory[28]=32\'b00010100;\n           ^\n%Error: Exiting due to 8 warning(s)\n'
module DataMemory(
    input clock,
    input [31:0] address,
    input [31:0] writeData,
    input MemRead,
    input MemWrite,
    output reg [31:0] readData
    );

reg [7:0] memory [1023:0];
integer i;
initial begin
	for(i=0; i<1023; i=i+1) begin
		memory[i] = 0;
	end
	

	memory[0]=8'b00100000;
	memory[1]=8'b00000010;
	memory[2]=8'b00000000;
	memory[3]=8'b00000000;
	

	memory[5]=8'b00100000;
	memory[6]=8'b00000011;
	memory[7]=8'b00000000;
	memory[8]=8'b00000000;



	memory[20]=32'b00100000;
	memory[21]=32'b01000010;
	memory[22]=32'b00000000;
	memory[23]=32'b00000011;
	
	

	memory[25]=32'b00001000;
	memory[26]=32'b00000000;
	memory[27]=32'b00000000;
	memory[28]=32'b00010100;
end

always @(posedge clock) begin
	if (MemWrite) begin
		memory[address] = writeData[31:24];
		memory[address+1] = writeData[23:16];
		memory[address+2] = writeData[15:8];
		memory[address+3] = writeData[7:0];
	end
	if (MemRead) begin
		readData = {memory[address],memory[address+1],memory[address+2],memory[address+3]};
	end
end


endmodule
module DataMemory(
    input clock,
    input [31:0] address,
    input [31:0] writeData,
    input MemRead,
    input MemWrite,
    output reg [31:0] readData
    );


reg [7:0] memory [1023:0];
integer i;
initial begin
	for(i=0; i<1023; i=i+1) begin
		memory[i] = 0;
	end
	

	memory[0]=8'b00100000;
	memory[1]=8'b00000010;
	memory[2]=8'b00000000;
	memory[3]=8'b00000000;
	

	memory[5]=8'b00100000;
	memory[6]=8'b00000011;
	memory[7]=8'b00000000;
	memory[8]=8'b00000000;



	memory[20]=32'b00100000;
	memory[21]=32'b01000010;
	memory[22]=32'b00000000;
	memory[23]=32'b00000011;
	
	

	memory[25]=32'b00001000;
	memory[26]=32'b00000000;
	memory[27]=32'b00000000;
	memory[28]=32'b00010100;
end

always @(posedge clock) begin
	if (MemWrite) begin
		memory[address] = writeData[31:24];
		memory[address+1] = writeData[23:16];
		memory[address+2] = writeData[15:8];
		memory[address+3] = writeData[7:0];
	end
	if (MemRead) begin
		readData = {memory[address],memory[address+1],memory[address+2],memory[address+3]};
	end
end


endmodule