data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds4Tester/sbt/SmallOdds4Tester.v
data/verilator_xmls/3969c62e-f779-4158-84d0-b8802f2d9927.xml
module Queue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
`endif
  reg [31:0] ram [0:0];
  wire  ram__T_43_en;
  wire  ram__T_43_addr;
  wire [31:0] ram__T_43_data;
  wire [31:0] ram__T_34_data;
  wire  ram__T_34_addr;
  wire  ram__T_34_mask;
  wire  ram__T_34_en;
  reg  maybe_full;
  wire  _T_26 = ~maybe_full;
  wire  do_enq = io_enq_ready & io_enq_valid;
  wire  do_deq = io_deq_ready & io_deq_valid;
  assign ram__T_43_en = 1'h1;
  assign ram__T_43_addr = 1'h0;
  assign ram__T_43_data = ram[ram__T_43_addr];
  assign ram__T_34_data = io_enq_bits;
  assign ram__T_34_addr = 1'h0;
  assign ram__T_34_mask = 1'h1;
  assign ram__T_34_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full;
  assign io_deq_valid = ~_T_26;
  assign io_deq_bits = ram__T_43_data;
  always @(posedge clock) begin
    if (ram__T_34_en & ram__T_34_mask) begin
      ram[ram__T_34_addr] <= ram__T_34_data;
    end
    if (reset) begin
      maybe_full <= 1'h0;
    end else if (do_enq != do_deq) begin
      maybe_full <= do_enq;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  maybe_full = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Queue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
`endif
  reg [31:0] ram [0:0];
  wire  ram__T_43_en;
  wire  ram__T_43_addr;
  wire [31:0] ram__T_43_data;
  wire [31:0] ram__T_34_data;
  wire  ram__T_34_addr;
  wire  ram__T_34_mask;
  wire  ram__T_34_en;
  reg  maybe_full;
  wire  _T_26 = ~maybe_full;
  wire  do_enq = io_enq_ready & io_enq_valid;
  wire  do_deq = io_deq_ready & io_deq_valid;
  assign ram__T_43_en = 1'h1;
  assign ram__T_43_addr = 1'h0;
  assign ram__T_43_data = ram[ram__T_43_addr];
  assign ram__T_34_data = io_enq_bits;
  assign ram__T_34_addr = 1'h0;
  assign ram__T_34_mask = 1'h1;
  assign ram__T_34_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full;
  assign io_deq_valid = ~_T_26;
  assign io_deq_bits = ram__T_43_data;
  always @(posedge clock) begin
    if (ram__T_34_en & ram__T_34_mask) begin
      ram[ram__T_34_addr] <= ram__T_34_data;
    end
    if (reset) begin
      maybe_full <= 1'h0;
    end else if (do_enq != do_deq) begin
      maybe_full <= do_enq;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  maybe_full = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule