data/full_repos/permissive/493019833/test/testcase/firrtl/Complex2R2WCMem.lo/reference/Complex2R2WCMem.lo.v
data/verilator_xmls/c981a854-060e-4ebd-8318-3d4658714ca0.xml
module CAT(y, a, b);
    parameter width_a = 4;
    parameter width_b = 4;
    output [width_a+width_b-1:0] y;
    input [width_a-1:0] a;
    input [width_b-1:0] b;
    assign y = {a, b};
endmodule
module CAT(y, a, b);

    parameter width_a = 4;
    parameter width_b = 4;
    output [width_a+width_b-1:0] y;
    input [width_a-1:0] a;
    input [width_b-1:0] b;
    assign y = {a, b};
endmodule