data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_utils.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_utils.v:139: Multiple top level modules\n                                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                         : ... Top module \'shift_register\'\nmodule shift_register\n       ^~~~~~~~~~~~~~\n                                                                                                         : ... Top module \'shift_div\'\nmodule shift_div\n       ^~~~~~~~~\n                                                                                                         : ... Top module \'hist_ram\'\nmodule hist_ram\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module simple_dp_ram
#(
	parameter DW = 8,
	parameter AW = 4,
	parameter SZ = 2**AW
)
(
	input          clk,
	input          wren,
	input [AW-1:0] wraddr,
	input [DW-1:0] data,
	input          rden,
	input [AW-1:0] rdaddr,
	output reg [DW-1:0] q
);

	reg [DW-1:0] mem [SZ-1:0];
	always @ (posedge clk) begin
		if (wren) begin
			mem[wraddr] <= data;
		end
	end
	always @ (posedge clk) begin
		if (rden) begin
			q <= mem[rdaddr];
		end
	end
endmodule
module simple_dp_ram
#(
	parameter DW = 8,
	parameter AW = 4,
	parameter SZ = 2**AW
)
(
	input          clk,
	input          wren,
	input [AW-1:0] wraddr,
	input [DW-1:0] data,
	input          rden,
	input [AW-1:0] rdaddr,
	output reg [DW-1:0] q
);


	reg [DW-1:0] mem [SZ-1:0];
	always @ (posedge clk) begin
		if (wren) begin
			mem[wraddr] <= data;
		end
	end
	always @ (posedge clk) begin
		if (rden) begin
			q <= mem[rdaddr];
		end
	end
endmodule