data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:180: Unsupported: Ignoring delay on this delayed statement.\n    initial #1  r_consf_en <= 0;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:207: Define or directive not defined: \'`MC_MODE_CPU\'\n    wire  w_mode_is_mc  = r_mc_mode != `MC_MODE_CPU;\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire  w_mode_is_mc  = r_mc_mode != `MC_MODE_CPU;\n                                                   ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:208: Define or directive not defined: \'`MC_MODE_CPU\'\n    wire  w_mode_is_cpu = r_mc_mode == `MC_MODE_CPU;\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire  w_mode_is_cpu = r_mc_mode == `MC_MODE_CPU;\n                                                   ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:215: Define or directive not defined: \'`ACCESS_CODE\'\n    wire        w_iscode        = (w_tlb_req == `ACCESS_CODE);\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:215: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_iscode        = (w_tlb_req == `ACCESS_CODE);\n                                                            ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:216: Define or directive not defined: \'`ACCESS_READ\'\n    wire        w_isread        = (w_tlb_req == `ACCESS_READ);\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:216: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_isread        = (w_tlb_req == `ACCESS_READ);\n                                                            ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:217: Define or directive not defined: \'`ACCESS_WRITE\'\n    wire        w_iswrite       = (w_tlb_req == `ACCESS_WRITE);\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_iswrite       = (w_tlb_req == `ACCESS_WRITE);\n                                                             ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:231: Define or directive not defined: \'`PRIV_S\'\n                                   (L1_xwr != 0 && ((w_priv == `PRIV_S && (L1_pte[4] && !w_mstatus[18])) ||\n                                                               ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:231: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                                   (L1_xwr != 0 && ((w_priv == `PRIV_S && (L1_pte[4] && !w_mstatus[18])) ||\n                                                                       ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:232: Define or directive not defined: \'`PRIV_U\'\n                                                    (w_priv == `PRIV_U && !L1_pte[4]) ||\n                                                               ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:243: Define or directive not defined: \'`PRIV_S\'\n                                    (w_priv == `PRIV_S && (L0_pte[4] && !w_mstatus[18])) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:243: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                                    (w_priv == `PRIV_S && (L0_pte[4] && !w_mstatus[18])) ||\n                                                       ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:244: Define or directive not defined: \'`PRIV_U\'\n                                    (w_priv == `PRIV_U && !L0_pte[4]) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:248: Define or directive not defined: \'`PTE_A_MASK\'\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:248: Define or directive not defined: \'`PTE_D_MASK\'\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:248: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                                  ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:249: Define or directive not defined: \'`PTE_A_MASK\'\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:249: Define or directive not defined: \'`PTE_D_MASK\'\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:249: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                                  ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:255: Define or directive not defined: \'`CAUSE_FETCH_PAGE_FAULT\'\n    assign w_pagefault          = !page_walk_fail ? ~32\'h0 : (r_iscode) ? `CAUSE_FETCH_PAGE_FAULT :\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:255: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign w_pagefault          = !page_walk_fail ? ~32\'h0 : (r_iscode) ? `CAUSE_FETCH_PAGE_FAULT :\n                                                                                                  ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:256: Define or directive not defined: \'`CAUSE_LOAD_PAGE_FAULT\'\n                                    (r_isread) ? `CAUSE_LOAD_PAGE_FAULT : `CAUSE_STORE_PAGE_FAULT;\n                                                 ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:256: Define or directive not defined: \'`CAUSE_STORE_PAGE_FAULT\'\n                                    (r_isread) ? `CAUSE_LOAD_PAGE_FAULT : `CAUSE_STORE_PAGE_FAULT;\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:263: Define or directive not defined: \'`PRIV_M\'\n                                          && (!(w_priv == `PRIV_M || w_satp[31] == 0)));\n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:263: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                          && (!(w_priv == `PRIV_M || w_satp[31] == 0)));\n                                                                  ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:349: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_inst_r (CLK, 1\'b1, w_tlb_flush, w_tlb_inst_r_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:353: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_data_r (CLK, 1\'b1, w_tlb_flush, w_tlb_data_r_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:357: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_data_w (CLK, 1\'b1, w_tlb_flush, w_tlb_data_w_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:380: Define or directive not defined: \'`PRIV_M\'\n    wire [31:0] w_insn_paddr =  (w_priv == `PRIV_M || w_satp[31] == 0) ? w_insn_addr :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:380: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    wire [31:0] w_insn_paddr =  (w_priv == `PRIV_M || w_satp[31] == 0) ? w_insn_addr :\n                                                   ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:384: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_addr   : r_tlb_addr;\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:384: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_addr   : r_tlb_addr;\n                                                   ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:390: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_ctrl       :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:390: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_ctrl       :\n                                                   ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:392: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (r_pw_state == 0)                       ? `FUNCT3_LW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:393: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (r_pw_state == 2)                       ? `FUNCT3_LW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:394: Define or directive not defined: \'`FUNCT3_SW____\'\n                                (r_pw_state == 5)                       ? `FUNCT3_SW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:405: Define or directive not defined: \'`MEM_BASE_TADDR\'\n                                    && (w_dev == `MEM_BASE_TADDR || w_dev == 0));\n                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:405: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                    && (w_dev == `MEM_BASE_TADDR || w_dev == 0));\n                                                                 ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:409: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0) ? w_data_addr :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:409: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0) ? w_data_addr :\n                                                   ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:413: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (w_iscode && !w_tlb_busy)   ? `FUNCT3_LW____    : w_mem_ctrl;\n                                                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:413: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                                (w_iscode && !w_tlb_busy)   ? `FUNCT3_LW____    : w_mem_ctrl;\n                                                                                ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:421: Define or directive not defined: \'`ACCESS_READ\'\n                    (w_mode_is_mc) ? (w_mc_aces==`ACCESS_READ && w_mc_addr[31:28] != 0) :\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:421: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                    (w_mode_is_mc) ? (w_mc_aces==`ACCESS_READ && w_mc_addr[31:28] != 0) :\n                                                              ^~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/mmu.v:422: Define or directive not defined: \'`PRIV_M\'\n                    (w_priv == `PRIV_M || w_satp[31] == 0) ? (w_iscode || w_isread) :\n                               ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module m_tlb#(parameter ADDR_WIDTH = 20, D_WIDTH = 20, ENTRY = 4)
            (CLK, RST_X, w_flush, w_we, w_waddr, w_raddr, w_idata, w_odata, w_oe);
    input  wire                     CLK, RST_X;
    input  wire                     w_flush, w_we;
    input  wire [ADDR_WIDTH-1:0]    w_waddr, w_raddr;
    input  wire    [D_WIDTH-1:0]    w_idata;
    output wire    [D_WIDTH-1:0]    w_odata;
    output wire                     w_oe;
    reg                               [ENTRY-1:0]   r_valid = 0;
    reg  [(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:0]   mem [0:ENTRY-1];
    integer i;
    initial for(i=0; i<ENTRY; i=i+1) mem[i] = 0;

    wire              [$clog2(ENTRY)-1:0]   w_ridx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_rtag;
    assign {w_rtag, w_ridx} = w_raddr;
    wire [ENTRY-1:0] w_ridx_v = ({{(ENTRY-1){1'b0}},{1'b1}} << w_ridx);
    wire w_tagmatch = (mem[w_ridx][(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:D_WIDTH] == w_rtag);
    assign w_odata  = mem[w_ridx][D_WIDTH-1:0];

    assign w_oe     = (w_tagmatch && (r_valid & w_ridx_v));

    wire              [$clog2(ENTRY)-1:0]   w_widx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_wtag;
    assign {w_wtag, w_widx} = w_waddr;
    wire [ENTRY-1:0] w_widx_v = ({{(ENTRY-1){1'b0}},{1'b1}} << w_widx);
    always  @(posedge  CLK)  begin

        if (!RST_X || w_flush) begin
            r_valid <= 0;
        end
        if (w_we) begin
            mem[w_widx] <= {w_wtag, w_idata};

            r_valid <= r_valid | w_widx_v;
        end
    end
endmodule
module m_tlb#(parameter ADDR_WIDTH = 20, D_WIDTH = 20, ENTRY = 4)
            (CLK, RST_X, w_flush, w_we, w_waddr, w_raddr, w_idata, w_odata, w_oe);

    input  wire                     CLK, RST_X;
    input  wire                     w_flush, w_we;
    input  wire [ADDR_WIDTH-1:0]    w_waddr, w_raddr;
    input  wire    [D_WIDTH-1:0]    w_idata;
    output wire    [D_WIDTH-1:0]    w_odata;
    output wire                     w_oe;
    reg                               [ENTRY-1:0]   r_valid = 0;
    reg  [(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:0]   mem [0:ENTRY-1];
    integer i;
    initial for(i=0; i<ENTRY; i=i+1) mem[i] = 0;

    wire              [$clog2(ENTRY)-1:0]   w_ridx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_rtag;
    assign {w_rtag, w_ridx} = w_raddr;
    wire [ENTRY-1:0] w_ridx_v = ({{(ENTRY-1){1'b0}},{1'b1}} << w_ridx);
    wire w_tagmatch = (mem[w_ridx][(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:D_WIDTH] == w_rtag);
    assign w_odata  = mem[w_ridx][D_WIDTH-1:0];

    assign w_oe     = (w_tagmatch && (r_valid & w_ridx_v));

    wire              [$clog2(ENTRY)-1:0]   w_widx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_wtag;
    assign {w_wtag, w_widx} = w_waddr;
    wire [ENTRY-1:0] w_widx_v = ({{(ENTRY-1){1'b0}},{1'b1}} << w_widx);
    always  @(posedge  CLK)  begin

        if (!RST_X || w_flush) begin
            r_valid <= 0;
        end
        if (w_we) begin
            mem[w_widx] <= {w_wtag, w_idata};

            r_valid <= r_valid | w_widx_v;
        end
    end
endmodule