data/full_repos/permissive/453763315/branch.v
1: b'%Warning-WIDTH: data/full_repos/permissive/453763315/branch.v:11: Bit extraction of var[2:0] requires 2 bit index, not 3 bits.\n                                                                : ... In instance branch\n    flag <= flags[flagsel];  \n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/453763315/branch.v:18: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                : ... In instance branch\n        addrout <= 8\'bzz;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module branch(clk, addrin, flagsel, flags, hilo, btake, addrout);
  input clk;
  input [15:0] addrin;
  input [2:0] flagsel, flags;
  input hilo;
  output reg btake;
  output reg [15:0] addrout;
  reg flag;

  always @ (posedge clk or negedge clk) begin
    flag <= flags[flagsel];
    if ((!flag && !hilo) || (flag && hilo)) begin
        btake <= 1'b0;
        addrout <= addrin;
      end
      else begin
        btake <= 1'b1;
        addrout <= 8'bzz;
      end
  end
endmodule
module branch(clk, addrin, flagsel, flags, hilo, btake, addrout);

  input clk;
  input [15:0] addrin;
  input [2:0] flagsel, flags;
  input hilo;
  output reg btake;
  output reg [15:0] addrout;
  reg flag;

  always @ (posedge clk or negedge clk) begin
    flag <= flags[flagsel];
    if ((!flag && !hilo) || (flag && hilo)) begin
        btake <= 1'b0;
        addrout <= addrin;
      end
      else begin
        btake <= 1'b1;
        addrout <= 8'bzz;
      end
  end
endmodule