data/full_repos/permissive/425157602/test/sim/darksimv.v
1: b'%Error: data/full_repos/permissive/425157602/test/sim/darksimv.v:32: Cannot find include file: ../rtl/config.vh\n`include "../rtl/config.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425157602/test/sim,data/full_repos/permissive/425157602/../rtl/config.vh\n             data/full_repos/permissive/425157602/test/sim,data/full_repos/permissive/425157602/../rtl/config.vh.v\n             data/full_repos/permissive/425157602/test/sim,data/full_repos/permissive/425157602/../rtl/config.vh.sv\n             ../rtl/config.vh\n             ../rtl/config.vh.v\n             ../rtl/config.vh.sv\n             obj_dir/../rtl/config.vh\n             obj_dir/../rtl/config.vh.v\n             obj_dir/../rtl/config.vh.sv\n%Error: data/full_repos/permissive/425157602/test/sim/darksimv.v:42: Define or directive not defined: \'`BOARD_CK\'\n    initial while(1) #(500e6/`BOARD_CK) CLK = !CLK;  \n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/425157602/test/sim/darksimv.v:42: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    initial while(1) #(500e6/`BOARD_CK) CLK = !CLK;  \n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/425157602/test/sim/darksimv.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1e3    RES = 0;             \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module darksimv;

    reg CLK = 0;
    
    reg RES = 1;

    initial while(1) #(500e6/`BOARD_CK) CLK = !CLK;

    initial
    begin
        $display("reset (startup)");
        #1e3    RES = 0;




    end

    wire TX;
    wire RX = 1;

    darksocv darksocv
    (
        .XCLK(CLK),
        .XRES(|RES),
        .UART_RXD(RX),
        .UART_TXD(TX)
    );

endmodule
module darksimv;


    reg CLK = 0;
    
    reg RES = 1;

    initial while(1) #(500e6/`BOARD_CK) CLK = !CLK;

    initial
    begin
        $display("reset (startup)");
        #1e3    RES = 0;




    end

    wire TX;
    wire RX = 1;

    darksocv darksocv
    (
        .XCLK(CLK),
        .XRES(|RES),
        .UART_RXD(RX),
        .UART_TXD(TX)
    );

endmodule