data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:356: Unsupported: Ignoring delay on this delayed statement.\n     #5 reset<=~reset;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:365: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:366: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:367: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:368: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:369: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:370: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:371: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:372: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:373: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:374: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:376: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:377: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:378: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:379: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:380: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:381: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:382: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:383: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:384: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:385: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:386: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:388: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:389: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:390: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:391: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:392: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:393: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:394: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:395: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:396: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:397: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:398: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:401: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:402: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:403: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:404: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:405: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:406: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:407: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:408: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:409: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:410: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:411: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:413: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:414: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:415: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:416: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:417: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:418: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:419: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:420: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:421: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:422: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:423: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:425: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:426: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:427: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:428: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:429: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:430: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:431: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:432: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:433: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:434: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:435: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=add_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:438: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:439: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:440: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:441: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:442: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:443: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:444: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:445: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:446: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:447: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:448: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:450: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:451: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:452: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:453: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:454: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:455: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:456: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:457: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:458: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:459: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:460: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:462: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:463: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:464: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:465: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:466: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:467: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:468: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:469: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:470: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:471: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:472: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:475: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:476: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:477: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:478: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:479: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:480: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:481: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:482: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:483: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:484: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:485: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:487: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:488: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:489: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:490: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:491: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:492: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:493: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:494: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:495: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:496: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:497: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:499: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:500: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:501: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:502: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:503: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:504: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:505: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:506: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:507: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:508: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:509: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:516: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:517: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:518: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:519: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:520: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:521: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:522: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:523: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:524: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:525: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:526: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:528: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:529: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:530: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:531: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:532: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:533: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:534: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:535: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:536: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:537: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:538: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:540: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:541: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:542: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:543: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:544: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:545: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:546: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:547: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:548: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:549: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:550: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar1_2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:553: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:554: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:555: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:556: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:557: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:558: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:559: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:560: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:561: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:562: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:563: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:565: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:566: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:567: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:568: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:569: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:570: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:571: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:572: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:573: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:574: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:575: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:577: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:578: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:579: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:580: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:581: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:582: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:583: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:584: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:585: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:586: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:587: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=sub_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:590: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:591: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:592: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:593: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:594: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:595: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:596: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:597: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:598: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:599: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:600: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:602: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:603: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:604: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:605: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:606: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:607: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:608: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:609: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:610: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:611: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:612: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:614: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:615: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:616: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:617: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:618: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:619: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:620: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:621: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:622: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:623: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:624: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=ar2_2_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:627: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:628: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:629: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:630: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:631: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:632: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:633: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:634: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:635: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:636: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:637: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:639: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:640: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:641: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:642: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:643: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:644: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:645: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:646: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:647: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:648: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:649: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=F0_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:651: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[10];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:652: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[9];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:653: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[8];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:654: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[7];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:655: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[6];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:656: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[5];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:657: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[4];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:658: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[3];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:659: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[2];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:660: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[1];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:661: Unsupported: Ignoring delay on this delayed statement.\n     #80 keyb_data<=equ_scan_code[0];\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:663: Unsupported: Ignoring delay on this delayed statement.\n           #80 keyb_data<=1\'b1; \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:666: Unsupported: Ignoring delay on this delayed statement.\n    #1 sys_clk<=~sys_clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator_modelsim.v:668: Unsupported: Ignoring delay on this delayed statement.\n    #40 keyb_clk<=~keyb_clk;\n    ^\n%Error: Exiting due to 267 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module calculator(sys_clk,reset,keyb_clk,keyb_data,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,a,b,c,disp1,disp2,result,next_calc_state,keyb_data_8bit);
   input sys_clk,reset,keyb_data;
   input keyb_clk;

   output reg [6:0] HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
   parameter [2:0] WAIT_OPERAND1=3'b000,WAIT_OPERATOR=3'b001,WAIT_OPERAND2=3'b010,WAIT_EQ=3'b011,WAIT_F0=3'b100,AFTER_F0=3'b101;
   
   reg [5:0] keyb_clk_samples;
   reg [10:0] keyb_data_reg;
   output reg [7:0] keyb_data_8bit;
   
   output wire [5:0] result;
   wire [5:0] mux;
   output reg [5:0] a;
   output reg [5:0] b;
   output reg [5:0] c;
   reg op;
   

   output reg [2:0] next_calc_state;
   reg [2:0] state;
   

   output reg [6:0] disp1,disp2;
   
   

   
   assign mux=(next_calc_state==WAIT_EQ)?result:c;
   
   assign result=op?a+(~b)+1'b1:a+b;
   
   
   

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_clk_samples<=6'b000000;
	  else
	     keyb_clk_samples<={keyb_clk,keyb_clk_samples[5:1]};
    end
		 

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_data_reg<=11'b11111111111;
	  else if(!keyb_data_reg[0])
	    begin
          keyb_data_8bit<=keyb_data_reg[8:1];
		  keyb_data_reg<=11'b11111111111;
	    end
	  else if(keyb_clk_samples==6'b000111)
		 keyb_data_reg<={keyb_data,keyb_data_reg[10:1]};	 
    end
		 

   always @(*)
    begin
		case(keyb_data_8bit)
		    8'h16: c<=6'd1;
		    8'h1E: c<=6'd2;
		    8'h26: c<=6'd3;
		    8'h25: c<=6'd4;
		    8'h2E: c<=6'd5;
		    8'h36: c<=6'd6;
		    8'h3D: c<=6'd7;
		    8'h3E: c<=6'd8;
		    8'h46: c<=6'd9;
		    8'h45: c<=6'd0;
		    8'h69: c<=6'd1;
		    8'h72: c<=6'd2;
		    8'h7A: c<=6'd3;
		    8'h6B: c<=6'd4;
		    8'h73: c<=6'd5;
		    8'h74: c<=6'd6;
		    8'h6C: c<=6'd7;
		    8'h75: c<=6'd8;
		    8'h7D: c<=6'd9;
		    8'h70: c<=6'd0;
		    default: c<=6'b100000;
		endcase
	end
		 	 

   always @(*)
    begin
		case(mux)
		   -6'd9: 
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010000;
			 end			   
		   -6'd8:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000000;
			 end	
		   -6'd7:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111000;
			 end	
		   -6'd6:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000010;
			 end	
		   -6'd5:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010010;
			 end	
		   -6'd4:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0011001;
			 end	
		   -6'd3:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0110000;
			 end	
		   -6'd2:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0100100;
			 end	
		   -6'd1:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd0:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1000000;
			 end	
		    6'd1:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd2:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0100100;
			 end
		    6'd3:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0110000;
			 end
		    6'd4:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0011001;
			 end
		    6'd5:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010010;
			 end
		    6'd6:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000010;
			 end
		    6'd7:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111000;
			 end
		    6'd8:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000000;
			 end
		    6'd9:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010000;
			 end
		    6'd10:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1000000;
			 end
		    6'd11:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111001;
			 end
		    6'd12:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0100100;
			 end
		    6'd13:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0110000;
			 end
		    6'd14:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0011001;
			 end
		    6'd15:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0010010;
			 end
		    6'd16:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000010;
			 end
		    6'd17:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111000;
			 end
		    6'd18:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000000;
			 end
		    default:
			 begin
               disp1<=7'b0000100; 
			   disp2<=7'b0000100;
			 end
		endcase
	end	 
		 	 

	always @(posedge sys_clk or posedge reset)
	 begin
	  if(reset)
	     begin
			HEX2<=7'b1111111;
			HEX3<=7'b1111111;
			HEX4<=7'b1111111;
			HEX5<=7'b1111111;
			HEX6<=7'b1111111;
			HEX7<=7'b1111111;
			next_calc_state<=WAIT_OPERAND1;
		 end
	  else if(!keyb_data_reg[0])
        case(next_calc_state)
		   WAIT_OPERAND1: begin
							  HEX2<=7'b1111111;
							  HEX3<=7'b1111111;
							  HEX4<=7'b1111111;
							  HEX5<=7'b1111111;
							  HEX6<=7'b1111111;
							  if(c[5]!=1'b1)
								  begin
									 a<=c;
									 next_calc_state<=WAIT_F0;
								  end
							 HEX7<=disp2;
							 state<=WAIT_OPERAND1;
					      end
		   WAIT_OPERATOR: begin
							 case(keyb_data_8bit)
								8'h79: begin
										   HEX6<=7'b0111001;
										   op<=1'b0;
										   next_calc_state<=WAIT_F0;
										 end
								8'h7B: begin
										   HEX6<=7'b0111111;
										   op<=1'b1;
										   next_calc_state<=WAIT_F0;
										 end
								default: HEX6<=7'b0000100;
							 endcase
							 state<=WAIT_OPERATOR;
						  end 					
		   WAIT_OPERAND2: begin
							   if(c[5]!=1'b1)
									begin
									   b<=c;
									   next_calc_state<=WAIT_F0;
									end   
							   HEX5<=disp2;
							   state<=WAIT_OPERAND2;
			              end 
		   WAIT_EQ: begin
					   if(keyb_data_8bit==8'h55)
							begin
							   HEX4<=7'b0111110;
							   HEX3<=disp1;
							   HEX2<=disp2;
							   next_calc_state<=WAIT_F0;
							end
					   else
							HEX4<=7'b0000100;
					   state<=WAIT_EQ;
					end
		   WAIT_F0: begin
					  if(keyb_data_8bit==8'hF0)
						next_calc_state<=AFTER_F0;
			        end
		   AFTER_F0: begin
						  case(state)
							  WAIT_OPERAND1:next_calc_state<=WAIT_OPERATOR; 
							  WAIT_OPERATOR:next_calc_state<=WAIT_OPERAND2;
							  WAIT_OPERAND2:next_calc_state<=WAIT_EQ;
							  default:next_calc_state<=WAIT_OPERAND1;
						  endcase   
		             end   
		   default: begin          
					   HEX2<=7'b1111111;
					   HEX3<=7'b1111111;
					   HEX4<=7'b1111111;
					   HEX5<=7'b1111111;
					   HEX6<=7'b1111111;
					   HEX7<=7'b1111111;
					   next_calc_state<=WAIT_OPERAND1;
					end
		endcase
	 end
endmodule
module calculator(sys_clk,reset,keyb_clk,keyb_data,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,a,b,c,disp1,disp2,result,next_calc_state,keyb_data_8bit);

   input sys_clk,reset,keyb_data;
   input keyb_clk;

   output reg [6:0] HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
   parameter [2:0] WAIT_OPERAND1=3'b000,WAIT_OPERATOR=3'b001,WAIT_OPERAND2=3'b010,WAIT_EQ=3'b011,WAIT_F0=3'b100,AFTER_F0=3'b101;
   
   reg [5:0] keyb_clk_samples;
   reg [10:0] keyb_data_reg;
   output reg [7:0] keyb_data_8bit;
   
   output wire [5:0] result;
   wire [5:0] mux;
   output reg [5:0] a;
   output reg [5:0] b;
   output reg [5:0] c;
   reg op;
   

   output reg [2:0] next_calc_state;
   reg [2:0] state;
   

   output reg [6:0] disp1,disp2;
   
   

   
   assign mux=(next_calc_state==WAIT_EQ)?result:c;
   
   assign result=op?a+(~b)+1'b1:a+b;
   
   
   

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_clk_samples<=6'b000000;
	  else
	     keyb_clk_samples<={keyb_clk,keyb_clk_samples[5:1]};
    end
		 

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_data_reg<=11'b11111111111;
	  else if(!keyb_data_reg[0])
	    begin
          keyb_data_8bit<=keyb_data_reg[8:1];
		  keyb_data_reg<=11'b11111111111;
	    end
	  else if(keyb_clk_samples==6'b000111)
		 keyb_data_reg<={keyb_data,keyb_data_reg[10:1]};	 
    end
		 

   always @(*)
    begin
		case(keyb_data_8bit)
		    8'h16: c<=6'd1;
		    8'h1E: c<=6'd2;
		    8'h26: c<=6'd3;
		    8'h25: c<=6'd4;
		    8'h2E: c<=6'd5;
		    8'h36: c<=6'd6;
		    8'h3D: c<=6'd7;
		    8'h3E: c<=6'd8;
		    8'h46: c<=6'd9;
		    8'h45: c<=6'd0;
		    8'h69: c<=6'd1;
		    8'h72: c<=6'd2;
		    8'h7A: c<=6'd3;
		    8'h6B: c<=6'd4;
		    8'h73: c<=6'd5;
		    8'h74: c<=6'd6;
		    8'h6C: c<=6'd7;
		    8'h75: c<=6'd8;
		    8'h7D: c<=6'd9;
		    8'h70: c<=6'd0;
		    default: c<=6'b100000;
		endcase
	end
		 	 

   always @(*)
    begin
		case(mux)
		   -6'd9: 
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010000;
			 end			   
		   -6'd8:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000000;
			 end	
		   -6'd7:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111000;
			 end	
		   -6'd6:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000010;
			 end	
		   -6'd5:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010010;
			 end	
		   -6'd4:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0011001;
			 end	
		   -6'd3:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0110000;
			 end	
		   -6'd2:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0100100;
			 end	
		   -6'd1:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd0:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1000000;
			 end	
		    6'd1:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd2:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0100100;
			 end
		    6'd3:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0110000;
			 end
		    6'd4:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0011001;
			 end
		    6'd5:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010010;
			 end
		    6'd6:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000010;
			 end
		    6'd7:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111000;
			 end
		    6'd8:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000000;
			 end
		    6'd9:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010000;
			 end
		    6'd10:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1000000;
			 end
		    6'd11:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111001;
			 end
		    6'd12:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0100100;
			 end
		    6'd13:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0110000;
			 end
		    6'd14:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0011001;
			 end
		    6'd15:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0010010;
			 end
		    6'd16:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000010;
			 end
		    6'd17:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111000;
			 end
		    6'd18:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000000;
			 end
		    default:
			 begin
               disp1<=7'b0000100; 
			   disp2<=7'b0000100;
			 end
		endcase
	end	 
		 	 

	always @(posedge sys_clk or posedge reset)
	 begin
	  if(reset)
	     begin
			HEX2<=7'b1111111;
			HEX3<=7'b1111111;
			HEX4<=7'b1111111;
			HEX5<=7'b1111111;
			HEX6<=7'b1111111;
			HEX7<=7'b1111111;
			next_calc_state<=WAIT_OPERAND1;
		 end
	  else if(!keyb_data_reg[0])
        case(next_calc_state)
		   WAIT_OPERAND1: begin
							  HEX2<=7'b1111111;
							  HEX3<=7'b1111111;
							  HEX4<=7'b1111111;
							  HEX5<=7'b1111111;
							  HEX6<=7'b1111111;
							  if(c[5]!=1'b1)
								  begin
									 a<=c;
									 next_calc_state<=WAIT_F0;
								  end
							 HEX7<=disp2;
							 state<=WAIT_OPERAND1;
					      end
		   WAIT_OPERATOR: begin
							 case(keyb_data_8bit)
								8'h79: begin
										   HEX6<=7'b0111001;
										   op<=1'b0;
										   next_calc_state<=WAIT_F0;
										 end
								8'h7B: begin
										   HEX6<=7'b0111111;
										   op<=1'b1;
										   next_calc_state<=WAIT_F0;
										 end
								default: HEX6<=7'b0000100;
							 endcase
							 state<=WAIT_OPERATOR;
						  end 					
		   WAIT_OPERAND2: begin
							   if(c[5]!=1'b1)
									begin
									   b<=c;
									   next_calc_state<=WAIT_F0;
									end   
							   HEX5<=disp2;
							   state<=WAIT_OPERAND2;
			              end 
		   WAIT_EQ: begin
					   if(keyb_data_8bit==8'h55)
							begin
							   HEX4<=7'b0111110;
							   HEX3<=disp1;
							   HEX2<=disp2;
							   next_calc_state<=WAIT_F0;
							end
					   else
							HEX4<=7'b0000100;
					   state<=WAIT_EQ;
					end
		   WAIT_F0: begin
					  if(keyb_data_8bit==8'hF0)
						next_calc_state<=AFTER_F0;
			        end
		   AFTER_F0: begin
						  case(state)
							  WAIT_OPERAND1:next_calc_state<=WAIT_OPERATOR; 
							  WAIT_OPERATOR:next_calc_state<=WAIT_OPERAND2;
							  WAIT_OPERAND2:next_calc_state<=WAIT_EQ;
							  default:next_calc_state<=WAIT_OPERAND1;
						  endcase   
		             end   
		   default: begin          
					   HEX2<=7'b1111111;
					   HEX3<=7'b1111111;
					   HEX4<=7'b1111111;
					   HEX5<=7'b1111111;
					   HEX6<=7'b1111111;
					   HEX7<=7'b1111111;
					   next_calc_state<=WAIT_OPERAND1;
					end
		endcase
	 end
endmodule