data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:61: Signal definition not found, creating implicitly: \'state\'\n   assign header_word  = header_ram[state];\n                                    ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:104: Can\'t find definition of variable: \'ST_SLOWPATH\'\n  ST_SLOWPATH :\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:106: Can\'t find definition of variable: \'ST_ERROR\'\n  ST_ERROR :\n  ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:108: Can\'t find definition of variable: \'ST_PAYLOAD\'\n  ST_PAYLOAD :\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:110: Can\'t find definition of variable: \'ST_FILLER\'\n  ST_FILLER :\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:112: Can\'t find definition of variable: \'ST_END1\'\n  ST_END1 :\n  ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:114: Can\'t find definition of variable: \'ST_END2\'\n                                                                             : ... Suggested alternative: \'ST_END1\'\n  ST_END2 :\n  ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_rx.v:117: Can\'t find definition of variable: \'mismatch\'\n    if(header_word[21] && mismatch)\n                          ^~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module prot_eng_rx
  #(parameter BASE=0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);

   localparam HDR_WIDTH  = 16 + 7;
   localparam HDR_LEN 	 = 32;
   

   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
   wire [HDR_WIDTH-1:0] header_word;
   
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hE0) == BASE))
       header_ram[set_addr[4:0]] <= set_data;

   assign header_word 	= header_ram[state];

   wire consume_input 	= src_rdy_i & dst_rdy_o;
   wire produce_output 	= src_rdy_o & dst_rdy_i;
   

   reg [15:0] pkt_length, fail_word, dataout_int;
   
   reg slowpath, error, sof_o, eof_o, occ_o, odd;

   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};

   wire [15:0] calc_ip_checksum, calc_udp_checksum;
   reg [15:0] rx_ip_checksum, rx_udp_checksum;

   always @(posedge clk) 
     if(header_word[19]) 
       rx_ip_checksum  <= datain[15:0];
   always @(posedge clk) 
     if(header_word[18]) 
       rx_udp_checksum <= datain[15:0];
   
   always @(posedge clk)
     if(reset | clear)
       begin
	  slowpath     <= 0;
	  error        <= 0;
	  state        <= 0;
	  fail_word    <= 0;
	  eof_o        <= 0;
	  occ_o        <= 0;
       end
     else if(src_rdy_i & dst_rdy_i)
       case (state)
	 0 :
	   begin
	      slowpath 	   <= 0;
	      error 	   <= 0;
	      eof_o 	   <= 0;
	      occ_o 	   <= 0;
	      state 	   <= 1;
	   end

	 ST_SLOWPATH :
	   ;
	 ST_ERROR :
	   ;
	 ST_PAYLOAD :
	   ;
	 ST_FILLER :
	   ;
	 ST_END1 :
	   ;
	 ST_END2 :
	   ;
	 default :
	   if(header_word[21] && mismatch)
	     state <= ST_SLOWPATH;
	   else if(header_word[20] && mismatch)
	     state <= ST_ERROR;
	   else if(header_word[22])
	     state <= ST_PAYLOAD;
	   else
	     state <= state + 1;
       endcase
   



   checksum_sm ip_chk
     (.clk(clk), .reset(reset), .in(datain), 
      .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
   
   checksum_sm udp_chk
     (.clk(clk), .reset(reset), .in(datain), 
      .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
   
endmodule
module prot_eng_rx
  #(parameter BASE=0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);


   localparam HDR_WIDTH  = 16 + 7;
   localparam HDR_LEN 	 = 32;
   

   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
   wire [HDR_WIDTH-1:0] header_word;
   
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hE0) == BASE))
       header_ram[set_addr[4:0]] <= set_data;

   assign header_word 	= header_ram[state];

   wire consume_input 	= src_rdy_i & dst_rdy_o;
   wire produce_output 	= src_rdy_o & dst_rdy_i;
   

   reg [15:0] pkt_length, fail_word, dataout_int;
   
   reg slowpath, error, sof_o, eof_o, occ_o, odd;

   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};

   wire [15:0] calc_ip_checksum, calc_udp_checksum;
   reg [15:0] rx_ip_checksum, rx_udp_checksum;

   always @(posedge clk) 
     if(header_word[19]) 
       rx_ip_checksum  <= datain[15:0];
   always @(posedge clk) 
     if(header_word[18]) 
       rx_udp_checksum <= datain[15:0];
   
   always @(posedge clk)
     if(reset | clear)
       begin
	  slowpath     <= 0;
	  error        <= 0;
	  state        <= 0;
	  fail_word    <= 0;
	  eof_o        <= 0;
	  occ_o        <= 0;
       end
     else if(src_rdy_i & dst_rdy_i)
       case (state)
	 0 :
	   begin
	      slowpath 	   <= 0;
	      error 	   <= 0;
	      eof_o 	   <= 0;
	      occ_o 	   <= 0;
	      state 	   <= 1;
	   end

	 ST_SLOWPATH :
	   ;
	 ST_ERROR :
	   ;
	 ST_PAYLOAD :
	   ;
	 ST_FILLER :
	   ;
	 ST_END1 :
	   ;
	 ST_END2 :
	   ;
	 default :
	   if(header_word[21] && mismatch)
	     state <= ST_SLOWPATH;
	   else if(header_word[20] && mismatch)
	     state <= ST_ERROR;
	   else if(header_word[22])
	     state <= ST_PAYLOAD;
	   else
	     state <= state + 1;
       endcase
   



   checksum_sm ip_chk
     (.clk(clk), .reset(reset), .in(datain), 
      .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
   
   checksum_sm udp_chk
     (.clk(clk), .reset(reset), .in(datain), 
      .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
   
endmodule