data/full_repos/permissive/472469504/src/Register.v
data/verilator_xmls/0931dbd5-ca2f-49e0-b2c6-7d34fc52496d.xml
module Register
#(
	parameter N = 32,
	parameter init_val = 0
)
(
	input clk,
	input reset,
	input enable,
	input  [N-1:0] DataInput,
	
	
	output reg [N-1:0] DataOutput
);

always@(negedge reset or posedge clk) begin
	if(reset==0)
		DataOutput <= init_val;
	else	
		if(enable==1)
			DataOutput<=DataInput;
end

endmodule
module Register
#(
	parameter N = 32,
	parameter init_val = 0
)
(
	input clk,
	input reset,
	input enable,
	input  [N-1:0] DataInput,
	
	
	output reg [N-1:0] DataOutput
);


always@(negedge reset or posedge clk) begin
	if(reset==0)
		DataOutput <= init_val;
	else	
		if(enable==1)
			DataOutput<=DataInput;
end

endmodule