data/full_repos/permissive/463439324/decap/f0_times_g0.v
data/verilator_xmls/2e74a9d1-62a3-4f58-a427-374828ad0c52.xml
module f0_times_g0(f0,f1,g0,g1,c0,c1);

input f0;
input f1;
input g0;
input g1;

wire [3:0] sol = {g1,f1,g0,f0};

output reg c0;
output reg c1;



always@(*)
begin
	case(sol[1:0])
		3: c0 = 1;
		default: c0 = 0;
	endcase
end

always@(*)
begin
	case(sol)
		7,11: c1 = 1;
		default: c1 = 0;
	endcase
end


endmodule
module f0_times_g0(f0,f1,g0,g1,c0,c1);


input f0;
input f1;
input g0;
input g1;

wire [3:0] sol = {g1,f1,g0,f0};

output reg c0;
output reg c1;



always@(*)
begin
	case(sol[1:0])
		3: c0 = 1;
		default: c0 = 0;
	endcase
end

always@(*)
begin
	case(sol)
		7,11: c1 = 1;
		default: c1 = 0;
	endcase
end


endmodule