data/full_repos/permissive/43856783/I2C/top_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #115;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #150;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #3750;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #355;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #3625;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:106: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/I2C/top_tst.v:107: Unsupported: Ignoring delay on this delayed statement.\n always #55 clk_frame = ~clk_frame;\n        ^\n%Error: data/full_repos/permissive/43856783/I2C/top_tst.v:51: Cannot find file containing module: \'I2C_Top\'\n I2C_Top uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/I2C,data/full_repos/permissive/43856783/I2C_Top\n             data/full_repos/permissive/43856783/I2C,data/full_repos/permissive/43856783/I2C_Top.v\n             data/full_repos/permissive/43856783/I2C,data/full_repos/permissive/43856783/I2C_Top.sv\n             I2C_Top\n             I2C_Top.v\n             I2C_Top.sv\n             obj_dir/I2C_Top\n             obj_dir/I2C_Top.v\n             obj_dir/I2C_Top.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tst;


	reg clk;
	reg clk_frame;
	reg rst;
	reg en;
	reg start;
	reg stop;
	reg ack_o;
	reg rw;
	reg [7:0] out_byte;


	wire busy;
	wire err;
	wire [7:0] in_byte;
	wire SCL;


	wire SDA;
	
	reg SDA_in, SDA_out, SDA_oen;
	assign SDA = SDA_oen? 1'bz : SDA_out;


	I2C_Top uut (
		.clk(clk), 
		.clk_frame(clk_frame), 
		.rst(rst), 
		.en(en), 
		.start(start), 
		.stop(stop), 
		.ack_o(ack_o), 
		.rw(rw), 
		.out_byte(out_byte), 
		.busy(busy), 
		.err(err), 
		.in_byte(in_byte), 
		.SCL(SCL), 
		.SDA(SDA)
	);

	initial begin

		clk = 0;
		clk_frame = 0;
		rst = 1;
		en = 0;
		start = 0;
		stop = 0;
		ack_o = 1;
		rw = 0;
		out_byte = 0;
		SDA_oen = 1;

		#100;
      rst = 0;

		out_byte = 8'hAA;
		#115;
		en = 1;
		start = 1;
		stop = 0;
		#150;
		en = 0;
		start = 0;
		out_byte = 8'h00;
		#3750;
		SDA_oen = 0;
		SDA_out = 0;
		#355;
		SDA_out = 1;
		en = 1;
		rw = 0;
		#3625;
		SDA_oen = 1;
		SDA_out = 0;
		
	end
	
	always #5 clk = ~clk;
	always #55 clk_frame = ~clk_frame;
	
endmodule
module top_tst;



	reg clk;
	reg clk_frame;
	reg rst;
	reg en;
	reg start;
	reg stop;
	reg ack_o;
	reg rw;
	reg [7:0] out_byte;


	wire busy;
	wire err;
	wire [7:0] in_byte;
	wire SCL;


	wire SDA;
	
	reg SDA_in, SDA_out, SDA_oen;
	assign SDA = SDA_oen? 1'bz : SDA_out;


	I2C_Top uut (
		.clk(clk), 
		.clk_frame(clk_frame), 
		.rst(rst), 
		.en(en), 
		.start(start), 
		.stop(stop), 
		.ack_o(ack_o), 
		.rw(rw), 
		.out_byte(out_byte), 
		.busy(busy), 
		.err(err), 
		.in_byte(in_byte), 
		.SCL(SCL), 
		.SDA(SDA)
	);

	initial begin

		clk = 0;
		clk_frame = 0;
		rst = 1;
		en = 0;
		start = 0;
		stop = 0;
		ack_o = 1;
		rw = 0;
		out_byte = 0;
		SDA_oen = 1;

		#100;
      rst = 0;

		out_byte = 8'hAA;
		#115;
		en = 1;
		start = 1;
		stop = 0;
		#150;
		en = 0;
		start = 0;
		out_byte = 8'h00;
		#3750;
		SDA_oen = 0;
		SDA_out = 0;
		#355;
		SDA_out = 1;
		en = 1;
		rw = 0;
		#3625;
		SDA_oen = 1;
		SDA_out = 0;
		
	end
	
	always #5 clk = ~clk;
	always #55 clk_frame = ~clk_frame;
	
endmodule