data/full_repos/permissive/449071180/random_number_generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449071180/random_number_generator.v:21: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'count\' generates 1 bits.\n                                                                                 : ... In instance random_number_generator\n   if(count == 2) begin\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module random_number_generator(reset,clk,x_output,y_output);

input clk,reset;

output reg[2:0] y_output, x_output;

reg count;

always@(posedge clk,posedge reset) begin

	if (reset == 1) begin
		count = 0;
		y_output = 3'b01;
		x_output = 3'b11;
	end else begin
		count = count + 1;
		if(count == 1) begin
		y_output = 3'b01;
		x_output = 3'b11;
		end else begin
			if(count == 2) begin
			y_output = 3'b100;
	      x_output = 3'b11;
			end else begin
				y_output = 3'b101;
				x_output = 3'b10;
				count = 0;
			end
		
		end

	end

end



endmodule
module random_number_generator(reset,clk,x_output,y_output);


input clk,reset;

output reg[2:0] y_output, x_output;

reg count;

always@(posedge clk,posedge reset) begin

	if (reset == 1) begin
		count = 0;
		y_output = 3'b01;
		x_output = 3'b11;
	end else begin
		count = count + 1;
		if(count == 1) begin
		y_output = 3'b01;
		x_output = 3'b11;
		end else begin
			if(count == 2) begin
			y_output = 3'b100;
	      x_output = 3'b11;
			end else begin
				y_output = 3'b101;
				x_output = 3'b10;
				count = 0;
			end
		
		end

	end

end



endmodule