data/full_repos/permissive/455706578/bondmachine-src/bondmachine.sv
data/verilator_xmls/30d9174f-0823-424c-b6a5-d9529d98a82f.xml
module p0(clock_signal, reset_signal, rom_bus, rom_value,  ram_din, ram_dout, ram_addr, ram_wren, ram_en, i0, i0_valid, i0_received, o0, o0_valid, o0_received);

	input clock_signal;
	input reset_signal;
	output  [7:0] rom_bus;
	input  [9:0] rom_value;
	input  [7:0] ram_dout;
	output [7:0] ram_din;
	output  [7:0] ram_addr;
	output ram_wren, ram_en;

	input [7:0] i0;
	input i0_valid;
	output i0_received;
	output [7:0] o0;
	output o0_valid;
	input o0_received;


	localparam	I2R=2'b00,
			R2O=2'b01,
			INC=2'b10,
			J=2'b11;

	localparam	R0=2'b00,
			R1=2'b01,
			R2=2'b10,
			R3=2'b11;
	localparam			I0=1'b0;
	localparam			O0=1'b0;
	reg [7:0] _auxo0;

	reg [7:0] _ram [0:255];

	(* KEEP = "TRUE" *) reg [7:0] _pc;


	(* KEEP = "TRUE" *) reg [7:0] _r0;
	(* KEEP = "TRUE" *) reg [7:0] _r1;
	(* KEEP = "TRUE" *) reg [7:0] _r2;
	(* KEEP = "TRUE" *) reg [7:0] _r3;

	reg i0_recv;

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if (reset_signal)
		begin
			i0_recv <= #1 1'b0;
		end
		else
		begin
			case(rom_value[9:8])
				I2R: begin
					case (rom_value[5])
					I0 : begin
						i0_recv <= #1 1'b1;
					end
					default: begin
						if (!i0_valid)
						begin
							i0_recv <= #1 1'b0;
						end
					end
					endcase
				end
				default: begin
					if (!i0_valid)
					begin
						i0_recv <= #1 1'b0;
					end
				end
			endcase
		end
	end

	reg o0_val;

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if (reset_signal)
		begin
			o0_val <= #1 1'b0;
		end
		else
		begin
			case(rom_value[9:8])
				R2O: begin
					case (rom_value[5])
					O0 : begin
						o0_val <= 1'b1;
					end
					default: begin
						if (o0_received)
						begin
							o0_val <= #1 1'b0;
						end
					end
					endcase
				end
				default: begin
					if (o0_received)
					begin
						o0_val <= #1 1'b0;
					end
				end
			endcase
		end
	end

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if(reset_signal)
		begin
			_pc <= #1 8'h0;
			_r0 <= #1 8'h0;
			_r1 <= #1 8'h0;
			_r2 <= #1 8'h0;
			_r3 <= #1 8'h0;
		end
		else begin
			$display("Program Counter:%d", _pc);
			$display("Instruction:%b", rom_value);
			$display("Registers r0:%b r1:%b r2:%b r3:%b ", _r0, _r1, _r2, _r3);
				case(rom_value[9:8])
					I2R: begin
						case (rom_value[7:6])
						R0 : begin
							case (rom_value[5])
							I0 : begin
								_r0 <= #1 i0;
								$display("I2R R0 I0");
							end
							endcase
						end
						R1 : begin
							case (rom_value[5])
							I0 : begin
								_r1 <= #1 i0;
								$display("I2R R1 I0");
							end
							endcase
						end
						R2 : begin
							case (rom_value[5])
							I0 : begin
								_r2 <= #1 i0;
								$display("I2R R2 I0");
							end
							endcase
						end
						R3 : begin
							case (rom_value[5])
							I0 : begin
								_r3 <= #1 i0;
								$display("I2R R3 I0");
							end
							endcase
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					R2O: begin
						case (rom_value[7:6])
						R0 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r0;
								$display("R2O R0 O0");
							end
							endcase
						end
						R1 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r1;
								$display("R2O R1 O0");
							end
							endcase
						end
						R2 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r2;
								$display("R2O R2 O0");
							end
							endcase
						end
						R3 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r3;
								$display("R2O R3 O0");
							end
							endcase
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					INC: begin
						case (rom_value[7:6])
						R0 : begin
							_r0 <= #1 _r0 + 1'b1;
							$display("INC R0");
						end
						R1 : begin
							_r1 <= #1 _r1 + 1'b1;
							$display("INC R1");
						end
						R2 : begin
							_r2 <= #1 _r2 + 1'b1;
							$display("INC R2");
						end
						R3 : begin
							_r3 <= #1 _r3 + 1'b1;
							$display("INC R3");
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					J: begin
						_pc <= #1 rom_value[7:0];
						$display("J ", rom_value[7:0]);
					end
					default : begin
						$display("Unknown Opcode");
						_pc <= #1 _pc + 1'b1;
					end
				endcase
		end
	end
	assign rom_bus = _pc;
	assign i0_received = i0_recv;
	assign o0 = _auxo0;
	assign o0_valid = o0_val;
endmodule
module p0(clock_signal, reset_signal, rom_bus, rom_value,  ram_din, ram_dout, ram_addr, ram_wren, ram_en, i0, i0_valid, i0_received, o0, o0_valid, o0_received);


	input clock_signal;
	input reset_signal;
	output  [7:0] rom_bus;
	input  [9:0] rom_value;
	input  [7:0] ram_dout;
	output [7:0] ram_din;
	output  [7:0] ram_addr;
	output ram_wren, ram_en;

	input [7:0] i0;
	input i0_valid;
	output i0_received;
	output [7:0] o0;
	output o0_valid;
	input o0_received;


	localparam	I2R=2'b00,
			R2O=2'b01,
			INC=2'b10,
			J=2'b11;

	localparam	R0=2'b00,
			R1=2'b01,
			R2=2'b10,
			R3=2'b11;
	localparam			I0=1'b0;
	localparam			O0=1'b0;
	reg [7:0] _auxo0;

	reg [7:0] _ram [0:255];

	(* KEEP = "TRUE" *) reg [7:0] _pc;


	(* KEEP = "TRUE" *) reg [7:0] _r0;
	(* KEEP = "TRUE" *) reg [7:0] _r1;
	(* KEEP = "TRUE" *) reg [7:0] _r2;
	(* KEEP = "TRUE" *) reg [7:0] _r3;

	reg i0_recv;

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if (reset_signal)
		begin
			i0_recv <= #1 1'b0;
		end
		else
		begin
			case(rom_value[9:8])
				I2R: begin
					case (rom_value[5])
					I0 : begin
						i0_recv <= #1 1'b1;
					end
					default: begin
						if (!i0_valid)
						begin
							i0_recv <= #1 1'b0;
						end
					end
					endcase
				end
				default: begin
					if (!i0_valid)
					begin
						i0_recv <= #1 1'b0;
					end
				end
			endcase
		end
	end

	reg o0_val;

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if (reset_signal)
		begin
			o0_val <= #1 1'b0;
		end
		else
		begin
			case(rom_value[9:8])
				R2O: begin
					case (rom_value[5])
					O0 : begin
						o0_val <= 1'b1;
					end
					default: begin
						if (o0_received)
						begin
							o0_val <= #1 1'b0;
						end
					end
					endcase
				end
				default: begin
					if (o0_received)
					begin
						o0_val <= #1 1'b0;
					end
				end
			endcase
		end
	end

	always @(posedge clock_signal, posedge reset_signal)
	begin
		if(reset_signal)
		begin
			_pc <= #1 8'h0;
			_r0 <= #1 8'h0;
			_r1 <= #1 8'h0;
			_r2 <= #1 8'h0;
			_r3 <= #1 8'h0;
		end
		else begin
			$display("Program Counter:%d", _pc);
			$display("Instruction:%b", rom_value);
			$display("Registers r0:%b r1:%b r2:%b r3:%b ", _r0, _r1, _r2, _r3);
				case(rom_value[9:8])
					I2R: begin
						case (rom_value[7:6])
						R0 : begin
							case (rom_value[5])
							I0 : begin
								_r0 <= #1 i0;
								$display("I2R R0 I0");
							end
							endcase
						end
						R1 : begin
							case (rom_value[5])
							I0 : begin
								_r1 <= #1 i0;
								$display("I2R R1 I0");
							end
							endcase
						end
						R2 : begin
							case (rom_value[5])
							I0 : begin
								_r2 <= #1 i0;
								$display("I2R R2 I0");
							end
							endcase
						end
						R3 : begin
							case (rom_value[5])
							I0 : begin
								_r3 <= #1 i0;
								$display("I2R R3 I0");
							end
							endcase
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					R2O: begin
						case (rom_value[7:6])
						R0 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r0;
								$display("R2O R0 O0");
							end
							endcase
						end
						R1 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r1;
								$display("R2O R1 O0");
							end
							endcase
						end
						R2 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r2;
								$display("R2O R2 O0");
							end
							endcase
						end
						R3 : begin
							case (rom_value[5])
							O0 : begin
								_auxo0 <= #1 _r3;
								$display("R2O R3 O0");
							end
							endcase
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					INC: begin
						case (rom_value[7:6])
						R0 : begin
							_r0 <= #1 _r0 + 1'b1;
							$display("INC R0");
						end
						R1 : begin
							_r1 <= #1 _r1 + 1'b1;
							$display("INC R1");
						end
						R2 : begin
							_r2 <= #1 _r2 + 1'b1;
							$display("INC R2");
						end
						R3 : begin
							_r3 <= #1 _r3 + 1'b1;
							$display("INC R3");
						end
						endcase
						_pc <= #1 _pc + 1'b1 ;
					end
					J: begin
						_pc <= #1 rom_value[7:0];
						$display("J ", rom_value[7:0]);
					end
					default : begin
						$display("Unknown Opcode");
						_pc <= #1 _pc + 1'b1;
					end
				endcase
		end
	end
	assign rom_bus = _pc;
	assign i0_received = i0_recv;
	assign o0 = _auxo0;
	assign o0_valid = o0_val;
endmodule