data/full_repos/permissive/525152535/MUX4.v
data/verilator_xmls/98165efd-b6b1-4d9b-9f64-197069cd0e68.xml
module MUX4
(
    input      I0, I1, I2, I3,
    input      S0, S1,
    output reg O
);

    always @ (*) begin
        case ({S1, S0})
            2'b00 : O = I0;
            2'b01 : O = I1;
            2'b10 : O = I2;
            2'b11 : O = I3;
        endcase
    end

endmodule
module MUX4
(
    input      I0, I1, I2, I3,
    input      S0, S1,
    output reg O
);


    always @ (*) begin
        case ({S1, S0})
            2'b00 : O = I0;
            2'b01 : O = I1;
            2'b10 : O = I2;
            2'b11 : O = I3;
        endcase
    end

endmodule