data/full_repos/permissive/499944578/rtl/src/memory/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:178: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                                   : ... Top module \'single_port_ram\'\nmodule single_port_ram\n       ^~~~~~~~~~~~~~~\n                                                                                   : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                                   : ... Top module \'simple_ram_dual_clock\'\nmodule simple_ram_dual_clock #(\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:247: Little bit endian vector: MSB < LSB of bit range: -1:0\n    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module FIFO #(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output wire [(DATAWIDTH-1):0] data_out,
    output wire fifo_full, 
    output wire fifo_empty, 
    output wire fifo_lower_threshold, 
    output wire fifo_upper_threshold, 
    output wire fifo_overflow, 
    output wire fifo_underflow,
    input wire clk, 
    input wire resetn, 
    input wire wr, 
    input wire rd, 
    input wire [(DATAWIDTH-1):0] data_in,
    input wire [31:0] threshold_level
);  
    
    wire [$clog2(DEPTH):0] wptr,rptr;  
    wire fifo_we,fifo_rd;   
    write_pointer #(DATAWIDTH, DEPTH) write_pointer_i (wptr,fifo_we,wr,fifo_full,clk,resetn);  
    read_pointer  #(DATAWIDTH, DEPTH) read_pointer_i (rptr,fifo_rd,rd,fifo_empty,clk,resetn);  
    memory_array  #(DATAWIDTH, DEPTH) memory_array_i (data_out, data_in, clk,fifo_we, wptr,rptr);  
    status_signal #(DATAWIDTH, DEPTH) status_signal_i (fifo_full, fifo_empty, fifo_lower_threshold, fifo_upper_threshold, fifo_overflow, fifo_underflow, wr, rd, fifo_we, fifo_rd, wptr,rptr,clk,resetn,threshold_level);  
 endmodule
module FIFO #(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output wire [(DATAWIDTH-1):0] data_out,
    output wire fifo_full, 
    output wire fifo_empty, 
    output wire fifo_lower_threshold, 
    output wire fifo_upper_threshold, 
    output wire fifo_overflow, 
    output wire fifo_underflow,
    input wire clk, 
    input wire resetn, 
    input wire wr, 
    input wire rd, 
    input wire [(DATAWIDTH-1):0] data_in,
    input wire [31:0] threshold_level
);
  
    
    wire [$clog2(DEPTH):0] wptr,rptr;  
    wire fifo_we,fifo_rd;   
    write_pointer #(DATAWIDTH, DEPTH) write_pointer_i (wptr,fifo_we,wr,fifo_full,clk,resetn);  
    read_pointer  #(DATAWIDTH, DEPTH) read_pointer_i (rptr,fifo_rd,rd,fifo_empty,clk,resetn);  
    memory_array  #(DATAWIDTH, DEPTH) memory_array_i (data_out, data_in, clk,fifo_we, wptr,rptr);  
    status_signal #(DATAWIDTH, DEPTH) status_signal_i (fifo_full, fifo_empty, fifo_lower_threshold, fifo_upper_threshold, fifo_overflow, fifo_underflow, wr, rd, fifo_we, fifo_rd, wptr,rptr,clk,resetn,threshold_level);  
 endmodule