data/full_repos/permissive/420259327/IP/testPatternGen.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'rst\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'o_HSync\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'o_VSync\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/420259327/IP/testPatternGen.v:306: Signal definition not found, creating implicitly: \'h_Frame_Start\'\n                                                                               : ... Suggested alternative: \'w_Frame_Start\'\n        if(h_Frame_Start) begin\n           ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:93: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Red[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:94: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Grn[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:95: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Blu[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:168: Operator OR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:168: Operator OR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:169: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[11] = w_Row_Count[7];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:170: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[11] = w_Col_Count[7];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:175: Operator OR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:175: Operator OR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:176: Operator AND expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:176: Operator AND expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:177: Operator XOR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:177: Operator XOR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);\n                                                 ^\n%Error: Exiting due to 17 warning(s)\n'
module testPatternGen



  #(parameter VIDEO_WIDTH = 3)
   
   
  (input       i_Clk,

   input [3:0] i_Pattern,
   input       i_HSync,
   input       i_VSync,
   output reg [VIDEO_WIDTH-1:0] o_Red_Video,
   output reg [VIDEO_WIDTH-1:0] o_Grn_Video,
   output reg [VIDEO_WIDTH-1:0] o_Blu_Video
    );










  
  wire w_VSync;
  wire w_HSync;
  
  

  wire [VIDEO_WIDTH-1:0] Pattern_Red[0:15];
  wire [VIDEO_WIDTH-1:0] Pattern_Grn[0:15];
  wire [VIDEO_WIDTH-1:0] Pattern_Blu[0:15];
  

  wire [10:0] w_Col_Count;
  wire [10:0] w_Row_Count;

  wire [6:0] w_Bar_Width;
  wire [2:0] w_Bar_Select;
  
  
  Sync_To_Count sync (.i_Clk      (i_Clk),
       .i_HSync    (i_HSync),
       .i_VSync    (i_VSync),
       .o_Col_Count(w_Col_Count),
       .o_Row_Count(w_Row_Count)
      );
	  

  



  assign Pattern_Red[0] = 0;
  assign Pattern_Grn[0] = 0;
  assign Pattern_Blu[0] = 0;
  



  assign Pattern_Red[1] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[1] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[1] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[2] = 1'b1;
  assign Pattern_Grn[2] = 1'b1;
  assign Pattern_Blu[2] = 1'b1;
  



  assign Pattern_Red[3] = {VIDEO_WIDTH{1'b1}} ;
  assign Pattern_Grn[3] = 0;
  assign Pattern_Blu[3] = 0;




  assign Pattern_Red[4] = 0;
  assign Pattern_Grn[4] =  {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[4] = 0;
  



  assign Pattern_Red[5] = 0;
  assign Pattern_Grn[5] = 0;
  assign Pattern_Blu[5] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[6] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[6] = 0;
  assign Pattern_Blu[6] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[7] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[7] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[7] = 0;
  



  assign Pattern_Red[8] = 0;
  assign Pattern_Grn[8] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[8] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[9] = w_Col_Count[8] ^ w_Row_Count[8] ? {VIDEO_WIDTH{1'b1}} : 0;
  assign Pattern_Grn[9] = Pattern_Red[9];
  assign Pattern_Blu[9] = Pattern_Red[9];
  
  














  assign Pattern_Red[10] = 0;
  assign Pattern_Red[10] = 0;
  assign Pattern_Red[10] = 0;




  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);
  assign Pattern_Grn[11] = w_Row_Count[7];
  assign Pattern_Blu[11] = w_Col_Count[7];
  



  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);
  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);
  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);
  
  


  always @(posedge i_Clk)
  begin
    case (i_Pattern)
      4'h0 : 
      begin
	    o_Red_Video <= Pattern_Red[0];
        o_Grn_Video <= Pattern_Grn[0];
        o_Blu_Video <= Pattern_Blu[0];
      end
      4'h1 :
      begin
        o_Red_Video <= Pattern_Red[1];
        o_Grn_Video <= Pattern_Grn[1];
        o_Blu_Video <= Pattern_Blu[1];
      end
      4'h2 :
      begin
        o_Red_Video <= Pattern_Red[2];
        o_Grn_Video <= Pattern_Grn[2];
        o_Blu_Video <= Pattern_Blu[2];
      end
      4'h3 :
      begin
        o_Red_Video <= Pattern_Red[3];
        o_Grn_Video <= Pattern_Grn[3];
        o_Blu_Video <= Pattern_Blu[3];
      end
      4'h4 :
      begin
        o_Red_Video <= Pattern_Red[4];
        o_Grn_Video <= Pattern_Grn[4];
        o_Blu_Video <= Pattern_Blu[4];
      end
      4'h5 :
      begin
        o_Red_Video <= Pattern_Red[5];
        o_Grn_Video <= Pattern_Grn[5];
        o_Blu_Video <= Pattern_Blu[5];
      end
      4'h6 :
      begin
        o_Red_Video <= Pattern_Red[6];
        o_Grn_Video <= Pattern_Grn[6];
        o_Blu_Video <= Pattern_Blu[6];
      end
      4'h7 :
      begin
        o_Red_Video <= Pattern_Red[7];
        o_Grn_Video <= Pattern_Grn[7];
        o_Blu_Video <= Pattern_Blu[7];
      end
      4'h8 :
      begin
        o_Red_Video <= Pattern_Red[8];
        o_Grn_Video <= Pattern_Grn[8];
        o_Blu_Video <= Pattern_Blu[8];
      end
      4'h9 :
      begin
        o_Red_Video <= Pattern_Red[9];
        o_Grn_Video <= Pattern_Grn[9];
        o_Blu_Video <= Pattern_Blu[9];
      end
      4'ha :
      begin
        o_Red_Video <= Pattern_Red[9];
        o_Grn_Video <= Pattern_Grn[3];
        o_Blu_Video <= Pattern_Blu[2];
      end
      4'hb :
      begin
        o_Red_Video <= Pattern_Red[11];
        o_Grn_Video <= Pattern_Grn[11];
        o_Blu_Video <= Pattern_Blu[11];
      end
      4'hc :
      begin
        o_Red_Video <= Pattern_Red[12];
        o_Grn_Video <= Pattern_Grn[12];
        o_Blu_Video <= Pattern_Blu[12];
      end
      default:
      begin
        o_Red_Video <= Pattern_Red[0];
        o_Grn_Video <= Pattern_Grn[0];
        o_Blu_Video <= Pattern_Blu[0];
      end
    endcase
  end
endmodule
module testPatternGen



  #(parameter VIDEO_WIDTH = 3)
   
   
  (input       i_Clk,

   input [3:0] i_Pattern,
   input       i_HSync,
   input       i_VSync,
   output reg [VIDEO_WIDTH-1:0] o_Red_Video,
   output reg [VIDEO_WIDTH-1:0] o_Grn_Video,
   output reg [VIDEO_WIDTH-1:0] o_Blu_Video
    );











  
  wire w_VSync;
  wire w_HSync;
  
  

  wire [VIDEO_WIDTH-1:0] Pattern_Red[0:15];
  wire [VIDEO_WIDTH-1:0] Pattern_Grn[0:15];
  wire [VIDEO_WIDTH-1:0] Pattern_Blu[0:15];
  

  wire [10:0] w_Col_Count;
  wire [10:0] w_Row_Count;

  wire [6:0] w_Bar_Width;
  wire [2:0] w_Bar_Select;
  
  
  Sync_To_Count sync (.i_Clk      (i_Clk),
       .i_HSync    (i_HSync),
       .i_VSync    (i_VSync),
       .o_Col_Count(w_Col_Count),
       .o_Row_Count(w_Row_Count)
      );
	  

  



  assign Pattern_Red[0] = 0;
  assign Pattern_Grn[0] = 0;
  assign Pattern_Blu[0] = 0;
  



  assign Pattern_Red[1] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[1] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[1] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[2] = 1'b1;
  assign Pattern_Grn[2] = 1'b1;
  assign Pattern_Blu[2] = 1'b1;
  



  assign Pattern_Red[3] = {VIDEO_WIDTH{1'b1}} ;
  assign Pattern_Grn[3] = 0;
  assign Pattern_Blu[3] = 0;




  assign Pattern_Red[4] = 0;
  assign Pattern_Grn[4] =  {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[4] = 0;
  



  assign Pattern_Red[5] = 0;
  assign Pattern_Grn[5] = 0;
  assign Pattern_Blu[5] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[6] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[6] = 0;
  assign Pattern_Blu[6] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[7] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Grn[7] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[7] = 0;
  



  assign Pattern_Red[8] = 0;
  assign Pattern_Grn[8] = {VIDEO_WIDTH{1'b1}};
  assign Pattern_Blu[8] = {VIDEO_WIDTH{1'b1}};
  



  assign Pattern_Red[9] = w_Col_Count[8] ^ w_Row_Count[8] ? {VIDEO_WIDTH{1'b1}} : 0;
  assign Pattern_Grn[9] = Pattern_Red[9];
  assign Pattern_Blu[9] = Pattern_Red[9];
  
  














  assign Pattern_Red[10] = 0;
  assign Pattern_Red[10] = 0;
  assign Pattern_Red[10] = 0;




  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);
  assign Pattern_Grn[11] = w_Row_Count[7];
  assign Pattern_Blu[11] = w_Col_Count[7];
  



  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);
  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);
  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);
  
  


  always @(posedge i_Clk)
  begin
    case (i_Pattern)
      4'h0 : 
      begin
	    o_Red_Video <= Pattern_Red[0];
        o_Grn_Video <= Pattern_Grn[0];
        o_Blu_Video <= Pattern_Blu[0];
      end
      4'h1 :
      begin
        o_Red_Video <= Pattern_Red[1];
        o_Grn_Video <= Pattern_Grn[1];
        o_Blu_Video <= Pattern_Blu[1];
      end
      4'h2 :
      begin
        o_Red_Video <= Pattern_Red[2];
        o_Grn_Video <= Pattern_Grn[2];
        o_Blu_Video <= Pattern_Blu[2];
      end
      4'h3 :
      begin
        o_Red_Video <= Pattern_Red[3];
        o_Grn_Video <= Pattern_Grn[3];
        o_Blu_Video <= Pattern_Blu[3];
      end
      4'h4 :
      begin
        o_Red_Video <= Pattern_Red[4];
        o_Grn_Video <= Pattern_Grn[4];
        o_Blu_Video <= Pattern_Blu[4];
      end
      4'h5 :
      begin
        o_Red_Video <= Pattern_Red[5];
        o_Grn_Video <= Pattern_Grn[5];
        o_Blu_Video <= Pattern_Blu[5];
      end
      4'h6 :
      begin
        o_Red_Video <= Pattern_Red[6];
        o_Grn_Video <= Pattern_Grn[6];
        o_Blu_Video <= Pattern_Blu[6];
      end
      4'h7 :
      begin
        o_Red_Video <= Pattern_Red[7];
        o_Grn_Video <= Pattern_Grn[7];
        o_Blu_Video <= Pattern_Blu[7];
      end
      4'h8 :
      begin
        o_Red_Video <= Pattern_Red[8];
        o_Grn_Video <= Pattern_Grn[8];
        o_Blu_Video <= Pattern_Blu[8];
      end
      4'h9 :
      begin
        o_Red_Video <= Pattern_Red[9];
        o_Grn_Video <= Pattern_Grn[9];
        o_Blu_Video <= Pattern_Blu[9];
      end
      4'ha :
      begin
        o_Red_Video <= Pattern_Red[9];
        o_Grn_Video <= Pattern_Grn[3];
        o_Blu_Video <= Pattern_Blu[2];
      end
      4'hb :
      begin
        o_Red_Video <= Pattern_Red[11];
        o_Grn_Video <= Pattern_Grn[11];
        o_Blu_Video <= Pattern_Blu[11];
      end
      4'hc :
      begin
        o_Red_Video <= Pattern_Red[12];
        o_Grn_Video <= Pattern_Grn[12];
        o_Blu_Video <= Pattern_Blu[12];
      end
      default:
      begin
        o_Red_Video <= Pattern_Red[0];
        o_Grn_Video <= Pattern_Grn[0];
        o_Blu_Video <= Pattern_Blu[0];
      end
    endcase
  end
endmodule