data/full_repos/permissive/479997390/src/PipelineRegisters.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/479997390/src/PipelineRegisters.v:28: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'IF_ID\'\nmodule IF_ID (\n       ^~~~~\n                                                                                  : ... Top module \'ID_EX\'\nmodule ID_EX (\n       ^~~~~\n                                                                                  : ... Top module \'EX_MEM\'\nmodule EX_MEM (\n       ^~~~~~\n                                                                                  : ... Top module \'MEM_WB\'\nmodule MEM_WB (\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module EX_MEM (
  clk,
  ALUOutIn,

  RegDataIn,
  WriteRegAddrIn,

  MemReadIn,
  MemWriteIn,
  MemToRegIn,
  RegWriteIn,


  ALUOutOut,

  RegDataOut,
  WriteRegAddrOut,

  MemReadOut,
  MemWriteOut,
  MemToRegOut,
  RegWriteOut

);

  input clk;
  input [31:0] ALUOutIn, RegDataIn;
  input [4:0] WriteRegAddrIn;
  input MemReadIn, MemWriteIn, MemToRegIn, RegWriteIn;
  output reg [31:0] ALUOutOut, RegDataOut;
  output reg [4:0] WriteRegAddrOut;
  output reg MemReadOut, MemWriteOut, MemToRegOut, RegWriteOut;

  always @(posedge clk) begin
    ALUOutOut <= ALUOutIn;
    RegDataOut <= RegDataIn;
    WriteRegAddrOut <= WriteRegAddrIn;
    MemReadOut <= MemReadIn;
    MemWriteOut <= MemWriteIn;
    MemToRegOut <= MemToRegIn;
    RegWriteOut <= RegWriteIn;
  end
endmodule
module EX_MEM (
  clk,
  ALUOutIn,

  RegDataIn,
  WriteRegAddrIn,

  MemReadIn,
  MemWriteIn,
  MemToRegIn,
  RegWriteIn,


  ALUOutOut,

  RegDataOut,
  WriteRegAddrOut,

  MemReadOut,
  MemWriteOut,
  MemToRegOut,
  RegWriteOut

);


  input clk;
  input [31:0] ALUOutIn, RegDataIn;
  input [4:0] WriteRegAddrIn;
  input MemReadIn, MemWriteIn, MemToRegIn, RegWriteIn;
  output reg [31:0] ALUOutOut, RegDataOut;
  output reg [4:0] WriteRegAddrOut;
  output reg MemReadOut, MemWriteOut, MemToRegOut, RegWriteOut;

  always @(posedge clk) begin
    ALUOutOut <= ALUOutIn;
    RegDataOut <= RegDataIn;
    WriteRegAddrOut <= WriteRegAddrIn;
    MemReadOut <= MemReadIn;
    MemWriteOut <= MemWriteIn;
    MemToRegOut <= MemToRegIn;
    RegWriteOut <= RegWriteIn;
  end
endmodule