data/full_repos/permissive/468384194/verilog/rtl/bitbang.v
data/verilator_xmls/1450b6a0-d186-4c7b-8bbd-87114debef18.xml
module bitbang (s_clk, s_data, strobe, data, active, clk);
	localparam on_pattern = 16'hFAB1; 
	localparam off_pattern = 16'hFAB0; 
	input s_clk;
	input s_data;
	output reg strobe;
	output reg [31:0] data;
	output reg active = 1'b0;
	input clk; 

	reg [3:0] s_data_sample;
	reg [3:0] s_clk_sample;

	reg [31:0] serial_data;
	reg [15:0] serial_control;

	reg local_strobe;
	reg old_local_strobe;

	always @ (posedge clk)
	begin : p_input_sync
		s_data_sample <= {s_data_sample[3-1:0],s_data};
		s_clk_sample  <= {s_clk_sample[3-1:0],s_clk};
	end

	always @ (posedge clk)
	begin : p_in_shift

		if ((s_clk_sample[3] == 1'b0) && (s_clk_sample[3-1] == 1'b1)) begin
			serial_data <= {serial_data[31-1:0],s_data_sample[3]};
		end

		if ((s_clk_sample[3] == 1'b1) && (s_clk_sample[3-1] == 1'b0)) begin
			serial_control <= {serial_control[15-1:0],s_data_sample[3]};
		end
	end


	always @ (posedge clk)
	begin : p_parallel_load
		local_strobe <= 1'b0;
		if (serial_control == on_pattern) begin
			data <= serial_data;
			local_strobe <= 1'b1;
		end



		old_local_strobe <= local_strobe;
		strobe <= local_strobe & ~old_local_strobe;
	end


	always @ (posedge clk)
	begin : active_FSM
		if (serial_control == on_pattern) begin
			active <= 1'b1;
		end
		if (serial_control == off_pattern) begin
			active <= 1'b0;
		end
	end
















endmodule
module bitbang (s_clk, s_data, strobe, data, active, clk);

	localparam on_pattern = 16'hFAB1; 
	localparam off_pattern = 16'hFAB0; 
	input s_clk;
	input s_data;
	output reg strobe;
	output reg [31:0] data;
	output reg active = 1'b0;
	input clk; 

	reg [3:0] s_data_sample;
	reg [3:0] s_clk_sample;

	reg [31:0] serial_data;
	reg [15:0] serial_control;

	reg local_strobe;
	reg old_local_strobe;

	always @ (posedge clk)
	begin : p_input_sync
		s_data_sample <= {s_data_sample[3-1:0],s_data};
		s_clk_sample  <= {s_clk_sample[3-1:0],s_clk};
	end

	always @ (posedge clk)
	begin : p_in_shift

		if ((s_clk_sample[3] == 1'b0) && (s_clk_sample[3-1] == 1'b1)) begin
			serial_data <= {serial_data[31-1:0],s_data_sample[3]};
		end

		if ((s_clk_sample[3] == 1'b1) && (s_clk_sample[3-1] == 1'b0)) begin
			serial_control <= {serial_control[15-1:0],s_data_sample[3]};
		end
	end


	always @ (posedge clk)
	begin : p_parallel_load
		local_strobe <= 1'b0;
		if (serial_control == on_pattern) begin
			data <= serial_data;
			local_strobe <= 1'b1;
		end



		old_local_strobe <= local_strobe;
		strobe <= local_strobe & ~old_local_strobe;
	end


	always @ (posedge clk)
	begin : active_FSM
		if (serial_control == on_pattern) begin
			active <= 1'b1;
		end
		if (serial_control == off_pattern) begin
			active <= 1'b0;
		end
	end
















endmodule