data/full_repos/permissive/447529080/SP.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447529080/SP.v:184: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'EXE_OUT\' generates 32 bits.\n                                                             : ... In instance SP\n        mem_addr=EXE_OUT;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447529080/SP.v:189: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'EXE_OUT\' generates 32 bits.\n                                                             : ... In instance SP\n        mem_addr=EXE_OUT;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module SP(

	clk,
	rst_n,
	in_valid,
	inst,
	mem_dout,

	out_valid,
	inst_addr,
	mem_wen,
	mem_addr,
	mem_din
);





input                    clk, rst_n, in_valid;
input             [31:0] inst;
input  signed     [31:0] mem_dout;
output reg               out_valid;
output reg        [31:0] inst_addr;
output reg               mem_wen;
output reg        [11:0] mem_addr;
output reg signed [31:0] mem_din;






reg	        [31:0] r      [0:31]; 

reg [31:0]inst_buffer;
wire [5:0] opcode = inst_buffer[31:26];
wire [4:0] rs = inst_buffer[25:21];
wire [4:0] rt = inst_buffer[20:16];
wire [4:0] rd = inst_buffer[15:11];
wire [4:0] shamt = inst_buffer[10:6];
wire [5:0] funct = inst_buffer[5:0];
wire [15:0] immediate = inst_buffer[15:0];
wire [31:0] sign_extend_immediate;
assign sign_extend_immediate = (immediate[15]==1'b1)?{16'hffff,immediate[15:0]}:{16'h0000,immediate[15:0]};
wire [31:0] zero_extend_immediate;
assign zero_extend_immediate = {16'h0000,immediate[15:0]};
reg taken;


reg [2:0]current_state,next_state;
localparam IDLE     = 3'd0;
localparam EXE      = 3'd1;
localparam WB       = 3'd2;
localparam MEM      = 3'd3;
localparam OUT      = 3'd4;


localparam OP_R     = 6'd0;
localparam OP_andi  = 6'd1;
localparam OP_ori   = 6'd2;
localparam OP_addi  = 6'd3;
localparam OP_subi  = 6'd4;
localparam OP_lw    = 6'd5;
localparam OP_sw    = 6'd6;
localparam OP_beq   = 6'd7;
localparam OP_bnq   = 6'd8;

localparam funct_and    = 6'd0;
localparam funct_or     = 6'd1;
localparam funct_add    = 6'd2;
localparam funct_sub    = 6'd3;
localparam funct_slt    = 6'd4;
localparam funct_sll    = 6'd5;


reg signed [31:0] EXE_OUT;
integer i;








always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

always @(*) begin
    case(current_state)
        IDLE:   if(in_valid)    next_state = EXE;
                else            next_state = IDLE;
        EXE:    if((opcode==OP_lw) || (opcode==OP_sw))
                    next_state = MEM;
                else                                    
                    next_state = WB;
        MEM:    next_state = WB;
        WB:     next_state = OUT;
        OUT:    next_state = IDLE;
        default: next_state = IDLE;
    endcase
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        inst_buffer <= 32'd0;

    else if(in_valid) inst_buffer <= inst;
    else inst_buffer <= inst_buffer;
end


always @(*) begin
    case(opcode)

        OP_R: begin
            case(funct)
                funct_and   : EXE_OUT = r[rs] & r[rt];
                funct_or    : EXE_OUT = r[rs] | r[rt];
                funct_add   : EXE_OUT = r[rs] + r[rt];
                funct_sub   : EXE_OUT = r[rs] - r[rt];
                funct_slt   :begin
                    if(signed'(r[rs]) < signed'(r[rt]))
                        EXE_OUT = 32'd1;
                    else
                        EXE_OUT = 32'd0;
                end
                funct_sll   : EXE_OUT = r[rs] << shamt;
                default: EXE_OUT = 0;
            endcase
        end


        OP_andi     : EXE_OUT = r[rs] & zero_extend_immediate;
        OP_ori      : EXE_OUT = r[rs] | zero_extend_immediate;
        OP_addi     : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_subi     : EXE_OUT = r[rs] - sign_extend_immediate;
        OP_lw       : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_sw       : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_beq      : EXE_OUT = 32'd0;
        OP_bnq      : EXE_OUT = 32'd0;
        default: EXE_OUT = 0;
    endcase
end


always @(*) begin
    if(opcode==OP_beq)begin
        if(r[rs]==r[rt]) taken = 1'b1;
        else taken = 1'b0;
    end
    else if(opcode==OP_bnq)begin
        if(r[rs]!=r[rt]) taken = 1'b1;
        else taken = 1'b0;
    end
    else taken = 1'b0;
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)begin
        inst_addr <= 32'd0;
    end
    else if(taken && next_state==WB)begin
        inst_addr <= inst_addr + 4 + (sign_extend_immediate<<2);
    end
    else if(!taken && next_state==WB)begin
        inst_addr <= inst_addr + 4;
    end
    else inst_addr <= inst_addr;
end


always @(*) begin

    if(opcode==OP_lw && current_state==MEM)begin
        mem_wen=1'b1;
        mem_addr=EXE_OUT;
    end

    else if(opcode==OP_sw && current_state==MEM)begin
        mem_wen=0'b0;
        mem_addr=EXE_OUT;
        mem_din = r[rt];
    end
    else
        mem_wen = 1'b1;
end


always @(posedge clk or negedge rst_n) begin

    if (!rst_n) begin
        for(i=0;i<32;i=i+1)begin
            r[i] <= 32'd0;
        end
	end
    else if(current_state==WB)begin
        case(opcode)
            OP_R        : r[rd] <= EXE_OUT;
            OP_andi     : r[rt] <= EXE_OUT;
            OP_ori      : r[rt] <= EXE_OUT;
            OP_addi     : r[rt] <= EXE_OUT;
            OP_subi     : r[rt] <= EXE_OUT;
            OP_lw       : r[rt] <= mem_dout;
        endcase
    end
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n) out_valid <=0;
    else if(next_state==OUT) out_valid <=1;
    else out_valid <=0;
end

endmodule
module SP(

	clk,
	rst_n,
	in_valid,
	inst,
	mem_dout,

	out_valid,
	inst_addr,
	mem_wen,
	mem_addr,
	mem_din
);






input                    clk, rst_n, in_valid;
input             [31:0] inst;
input  signed     [31:0] mem_dout;
output reg               out_valid;
output reg        [31:0] inst_addr;
output reg               mem_wen;
output reg        [11:0] mem_addr;
output reg signed [31:0] mem_din;






reg	        [31:0] r      [0:31]; 

reg [31:0]inst_buffer;
wire [5:0] opcode = inst_buffer[31:26];
wire [4:0] rs = inst_buffer[25:21];
wire [4:0] rt = inst_buffer[20:16];
wire [4:0] rd = inst_buffer[15:11];
wire [4:0] shamt = inst_buffer[10:6];
wire [5:0] funct = inst_buffer[5:0];
wire [15:0] immediate = inst_buffer[15:0];
wire [31:0] sign_extend_immediate;
assign sign_extend_immediate = (immediate[15]==1'b1)?{16'hffff,immediate[15:0]}:{16'h0000,immediate[15:0]};
wire [31:0] zero_extend_immediate;
assign zero_extend_immediate = {16'h0000,immediate[15:0]};
reg taken;


reg [2:0]current_state,next_state;
localparam IDLE     = 3'd0;
localparam EXE      = 3'd1;
localparam WB       = 3'd2;
localparam MEM      = 3'd3;
localparam OUT      = 3'd4;


localparam OP_R     = 6'd0;
localparam OP_andi  = 6'd1;
localparam OP_ori   = 6'd2;
localparam OP_addi  = 6'd3;
localparam OP_subi  = 6'd4;
localparam OP_lw    = 6'd5;
localparam OP_sw    = 6'd6;
localparam OP_beq   = 6'd7;
localparam OP_bnq   = 6'd8;

localparam funct_and    = 6'd0;
localparam funct_or     = 6'd1;
localparam funct_add    = 6'd2;
localparam funct_sub    = 6'd3;
localparam funct_slt    = 6'd4;
localparam funct_sll    = 6'd5;


reg signed [31:0] EXE_OUT;
integer i;








always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

always @(*) begin
    case(current_state)
        IDLE:   if(in_valid)    next_state = EXE;
                else            next_state = IDLE;
        EXE:    if((opcode==OP_lw) || (opcode==OP_sw))
                    next_state = MEM;
                else                                    
                    next_state = WB;
        MEM:    next_state = WB;
        WB:     next_state = OUT;
        OUT:    next_state = IDLE;
        default: next_state = IDLE;
    endcase
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        inst_buffer <= 32'd0;

    else if(in_valid) inst_buffer <= inst;
    else inst_buffer <= inst_buffer;
end


always @(*) begin
    case(opcode)

        OP_R: begin
            case(funct)
                funct_and   : EXE_OUT = r[rs] & r[rt];
                funct_or    : EXE_OUT = r[rs] | r[rt];
                funct_add   : EXE_OUT = r[rs] + r[rt];
                funct_sub   : EXE_OUT = r[rs] - r[rt];
                funct_slt   :begin
                    if(signed'(r[rs]) < signed'(r[rt]))
                        EXE_OUT = 32'd1;
                    else
                        EXE_OUT = 32'd0;
                end
                funct_sll   : EXE_OUT = r[rs] << shamt;
                default: EXE_OUT = 0;
            endcase
        end


        OP_andi     : EXE_OUT = r[rs] & zero_extend_immediate;
        OP_ori      : EXE_OUT = r[rs] | zero_extend_immediate;
        OP_addi     : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_subi     : EXE_OUT = r[rs] - sign_extend_immediate;
        OP_lw       : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_sw       : EXE_OUT = r[rs] + sign_extend_immediate;
        OP_beq      : EXE_OUT = 32'd0;
        OP_bnq      : EXE_OUT = 32'd0;
        default: EXE_OUT = 0;
    endcase
end


always @(*) begin
    if(opcode==OP_beq)begin
        if(r[rs]==r[rt]) taken = 1'b1;
        else taken = 1'b0;
    end
    else if(opcode==OP_bnq)begin
        if(r[rs]!=r[rt]) taken = 1'b1;
        else taken = 1'b0;
    end
    else taken = 1'b0;
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)begin
        inst_addr <= 32'd0;
    end
    else if(taken && next_state==WB)begin
        inst_addr <= inst_addr + 4 + (sign_extend_immediate<<2);
    end
    else if(!taken && next_state==WB)begin
        inst_addr <= inst_addr + 4;
    end
    else inst_addr <= inst_addr;
end


always @(*) begin

    if(opcode==OP_lw && current_state==MEM)begin
        mem_wen=1'b1;
        mem_addr=EXE_OUT;
    end

    else if(opcode==OP_sw && current_state==MEM)begin
        mem_wen=0'b0;
        mem_addr=EXE_OUT;
        mem_din = r[rt];
    end
    else
        mem_wen = 1'b1;
end


always @(posedge clk or negedge rst_n) begin

    if (!rst_n) begin
        for(i=0;i<32;i=i+1)begin
            r[i] <= 32'd0;
        end
	end
    else if(current_state==WB)begin
        case(opcode)
            OP_R        : r[rd] <= EXE_OUT;
            OP_andi     : r[rt] <= EXE_OUT;
            OP_ori      : r[rt] <= EXE_OUT;
            OP_addi     : r[rt] <= EXE_OUT;
            OP_subi     : r[rt] <= EXE_OUT;
            OP_lw       : r[rt] <= mem_dout;
        endcase
    end
end


always @(posedge clk, negedge rst_n) begin
    if(!rst_n) out_valid <=0;
    else if(next_state==OUT) out_valid <=1;
    else out_valid <=0;
end

endmodule