data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/min_max.v
data/verilator_xmls/8f26b607-e87d-4dd4-bc93-316a9f85700a.xml
module min_max(
    input clk,
    input wire enable,
    input wire [31:0] sound_Value,
    output reg [31:0] min,
    output reg [31:0] max
    );


always@(negedge clk) begin
    if (enable == 1'b1) begin
        if (sound_Value < min) begin
            min = sound_Value;
        end
        if (sound_Value > max) begin
            max = sound_Value;
        end 
    end else begin
        min = sound_Value;
        max = sound_Value;
    end
end

endmodule
module min_max(
    input clk,
    input wire enable,
    input wire [31:0] sound_Value,
    output reg [31:0] min,
    output reg [31:0] max
    );



always@(negedge clk) begin
    if (enable == 1'b1) begin
        if (sound_Value < min) begin
            min = sound_Value;
        end
        if (sound_Value > max) begin
            max = sound_Value;
        end 
    end else begin
        min = sound_Value;
        max = sound_Value;
    end
end

endmodule