data/full_repos/permissive/434840709/lab1/2.40.v
data/verilator_xmls/148c3a27-95a4-41f9-9b2e-295295d50429.xml
module f (
    x1,
    x2,
    s,
    f
);
    input x1,x2,s;
    output f;

    assign f = (~s & x1) | (s & x2);

endmodule
module f (
    x1,
    x2,
    s,
    f
);

    input x1,x2,s;
    output f;

    assign f = (~s & x1) | (s & x2);

endmodule