data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:455: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n%Warning-PINMISSING: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:246: Cell has missing pin: \'io_enq_ready\'\n  Queue resDumpQueue(.clk(clk), .reset(reset),\n        ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    R1 = {1{$random}};\n       ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    R4 = {1{$random}};\n       ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:45: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    maybe_full = {1{$random}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:179: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid3 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:180: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid2 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:181: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid1 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:182: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regReqCount = {1{$random}};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:183: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regState = {1{$random}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:185: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regReadAddr = {1{$random}};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:197: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T40 = T41[2\'h3:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:235: Bit extraction of var[24:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T47 = T31[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:236: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s VARREF \'T32\' generates 20 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T31 = T32 << 3\'h5;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:243: Bit extraction of var[24:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T49 = T36[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:244: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s VARREF \'regReadAddr\' generates 20 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T36 = regReadAddr << 3\'h5;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:457: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regState = {1{$random}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:458: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regResetAddr = {1{$random}};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:460: Operator ASSIGN expects 31 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regRowIndsLeftInCol = {1{$random}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:461: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regAligned = {1{$random}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:462: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regStartDump = {1{$random}};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:468: Bit extraction of var[31:0] requires 5 bit index, not 3 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T0 = regRowCount[5\'h15:3\'h6];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:483: Bit extraction of var[31:0] requires 5 bit index, not 2 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign enableBRAMReset = io_ctrl[2\'h2:2\'h2];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:485: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign startAccel = io_ctrl[1\'h0:1\'h0];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:488: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign enableBRAMDump = io_ctrl[1\'h1:1\'h1];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:523: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T46 = rowIndMetadata_TDATA[5\'h1e:1\'h0];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:558: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T95 = T74[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:569: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T98 = T78[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:572: Bit extraction of var[63:0] requires 6 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign rowIndLower = rowIndData_TDATA[5\'h1f:1\'h0];\n                                       ^\n%Error: Exiting due to 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ResultDumper(input clk, input reset,
    input  io_start,
    input [15:0] io_wordCount,
    output io_finished,
    output[19:0] io_readAddr1,
    output[19:0] io_readAddr2,
    input [31:0] io_readData1,
    input [31:0] io_readData2,
    input  resultVector_TREADY,
    output resultVector_TVALID,
    output[63:0] resultVector_TDATA
);

  wire[63:0] T0;
  reg  regValid3;
  wire T37;
  reg  regValid2;
  wire T38;
  reg  regValid1;
  wire T39;
  wire T1;
  wire T2;
  wire T3;
  reg [3:0] regReqCount;
  wire[3:0] T40;
  wire[31:0] T41;
  wire[31:0] T4;
  wire[31:0] T5;
  wire[31:0] T42;
  wire[3:0] T6;
  wire T7;
  reg [1:0] regState;
  wire[1:0] T43;
  wire[1:0] T8;
  wire[1:0] T9;
  wire[1:0] T10;
  wire[1:0] T11;
  wire[1:0] T12;
  wire T13;
  wire T14;
  wire T15;
  reg [31:0] regWordsLeft;
  wire[31:0] T44;
  wire[31:0] T16;
  wire[31:0] T17;
  wire[31:0] T45;
  wire[31:0] T18;
  wire T19;
  wire T20;
  wire T21;
  wire T22;
  wire T23;
  wire[31:0] T24;
  wire T25;
  wire T26;
  wire T27;
  wire hasRoom;
  wire T28;
  wire[31:0] T46;
  wire[3:0] T29;
  wire T30;
  wire[19:0] T47;
  wire[24:0] T31;
  wire[19:0] T32;
  reg [19:0] regReadAddr;
  wire[19:0] T48;
  wire[19:0] T33;
  wire[19:0] T34;
  wire[19:0] T35;
  wire[19:0] T49;
  wire[24:0] T36;
  wire resDumpQueue_io_deq_valid;
  wire[63:0] resDumpQueue_io_deq_bits;
  wire[4:0] resDumpQueue_io_count;

`ifndef SYNTHESIS

  integer initvar;
  initial begin
    #0.002;
    regValid3 = {1{$random}};
    regValid2 = {1{$random}};
    regValid1 = {1{$random}};
    regReqCount = {1{$random}};
    regState = {1{$random}};
    regWordsLeft = {1{$random}};
    regReadAddr = {1{$random}};
  end

`endif

  assign T0 = {io_readData2, io_readData1};
  assign T37 = reset ? 1'h0 : regValid2;
  assign T38 = reset ? 1'h0 : regValid1;
  assign T39 = reset ? 1'h0 : T1;
  assign T1 = T30 & T2;
  assign T2 = T3 ^ 1'h1;
  assign T3 = regReqCount == 4'h0;
  assign T40 = T41[2'h3:1'h0];
  assign T41 = reset ? 32'h0 : T4;
  assign T4 = T1 ? T46 : T5;
  assign T5 = T26 ? T24 : T42;
  assign T42 = {28'h0, T6};
  assign T6 = T7 ? 4'h0 : regReqCount;
  assign T7 = 2'h0 == regState;
  assign T43 = reset ? 2'h0 : T8;
  assign T8 = T21 ? 2'h0 : T9;
  assign T9 = T20 ? 2'h1 : T10;
  assign T10 = T26 ? 2'h2 : T11;
  assign T11 = T14 ? 2'h3 : T12;
  assign T12 = T13 ? 2'h1 : regState;
  assign T13 = T7 & io_start;
  assign T14 = T19 & T15;
  assign T15 = regWordsLeft == 32'h0;
  assign T44 = reset ? 32'h0 : T16;
  assign T16 = T1 ? T18 : T17;
  assign T17 = T7 ? T45 : regWordsLeft;
  assign T45 = {16'h0, io_wordCount};
  assign T18 = regWordsLeft - 32'h1;
  assign T19 = 2'h1 == regState;
  assign T20 = T30 & T3;
  assign T21 = T23 & T22;
  assign T22 = io_start ^ 1'h1;
  assign T23 = 2'h3 == regState;
  assign T24 = T25 ? 32'h3 : regWordsLeft;
  assign T25 = 32'h3 < regWordsLeft;
  assign T26 = T19 & T27;
  assign T27 = T28 & hasRoom;
  assign hasRoom = resDumpQueue_io_count < 5'h9;
  assign T28 = T15 ^ 1'h1;
  assign T46 = {28'h0, T29};
  assign T29 = regReqCount - 4'h1;
  assign T30 = 2'h2 == regState;
  assign resultVector_TDATA = resDumpQueue_io_deq_bits;
  assign resultVector_TVALID = resDumpQueue_io_deq_valid;
  assign io_readAddr2 = T47;
  assign T47 = T31[5'h13:1'h0];
  assign T31 = T32 << 3'h5;
  assign T32 = regReadAddr + 20'h1;
  assign T48 = reset ? 20'h0 : T33;
  assign T33 = T1 ? T35 : T34;
  assign T34 = T7 ? 20'h0 : regReadAddr;
  assign T35 = regReadAddr + 20'h2;
  assign io_readAddr1 = T49;
  assign T49 = T36[5'h13:1'h0];
  assign T36 = regReadAddr << 3'h5;
  assign io_finished = T23;
  Queue resDumpQueue(.clk(clk), .reset(reset),

       .io_enq_valid( regValid3 ),
       .io_enq_bits( T0 ),
       .io_deq_ready( resultVector_TREADY ),
       .io_deq_valid( resDumpQueue_io_deq_valid ),
       .io_deq_bits( resDumpQueue_io_deq_bits ),
       .io_count( resDumpQueue_io_count )
  );

  always @(posedge clk) begin
    if(reset) begin
      regValid3 <= 1'h0;
    end else begin
      regValid3 <= regValid2;
    end
    if(reset) begin
      regValid2 <= 1'h0;
    end else begin
      regValid2 <= regValid1;
    end
    if(reset) begin
      regValid1 <= 1'h0;
    end else begin
      regValid1 <= T1;
    end
    regReqCount <= T40;
    if(reset) begin
      regState <= 2'h0;
    end else if(T21) begin
      regState <= 2'h0;
    end else if(T20) begin
      regState <= 2'h1;
    end else if(T26) begin
      regState <= 2'h2;
    end else if(T14) begin
      regState <= 2'h3;
    end else if(T13) begin
      regState <= 2'h1;
    end
    if(reset) begin
      regWordsLeft <= 32'h0;
    end else if(T1) begin
      regWordsLeft <= T18;
    end else if(T7) begin
      regWordsLeft <= T45;
    end
    if(reset) begin
      regReadAddr <= 20'h0;
    end else if(T1) begin
      regReadAddr <= T35;
    end else if(T7) begin
      regReadAddr <= 20'h0;
    end
  end
endmodule
module ResultDumper(input clk, input reset,
    input  io_start,
    input [15:0] io_wordCount,
    output io_finished,
    output[19:0] io_readAddr1,
    output[19:0] io_readAddr2,
    input [31:0] io_readData1,
    input [31:0] io_readData2,
    input  resultVector_TREADY,
    output resultVector_TVALID,
    output[63:0] resultVector_TDATA
);


  wire[63:0] T0;
  reg  regValid3;
  wire T37;
  reg  regValid2;
  wire T38;
  reg  regValid1;
  wire T39;
  wire T1;
  wire T2;
  wire T3;
  reg [3:0] regReqCount;
  wire[3:0] T40;
  wire[31:0] T41;
  wire[31:0] T4;
  wire[31:0] T5;
  wire[31:0] T42;
  wire[3:0] T6;
  wire T7;
  reg [1:0] regState;
  wire[1:0] T43;
  wire[1:0] T8;
  wire[1:0] T9;
  wire[1:0] T10;
  wire[1:0] T11;
  wire[1:0] T12;
  wire T13;
  wire T14;
  wire T15;
  reg [31:0] regWordsLeft;
  wire[31:0] T44;
  wire[31:0] T16;
  wire[31:0] T17;
  wire[31:0] T45;
  wire[31:0] T18;
  wire T19;
  wire T20;
  wire T21;
  wire T22;
  wire T23;
  wire[31:0] T24;
  wire T25;
  wire T26;
  wire T27;
  wire hasRoom;
  wire T28;
  wire[31:0] T46;
  wire[3:0] T29;
  wire T30;
  wire[19:0] T47;
  wire[24:0] T31;
  wire[19:0] T32;
  reg [19:0] regReadAddr;
  wire[19:0] T48;
  wire[19:0] T33;
  wire[19:0] T34;
  wire[19:0] T35;
  wire[19:0] T49;
  wire[24:0] T36;
  wire resDumpQueue_io_deq_valid;
  wire[63:0] resDumpQueue_io_deq_bits;
  wire[4:0] resDumpQueue_io_count;

`ifndef SYNTHESIS

  integer initvar;
  initial begin
    #0.002;
    regValid3 = {1{$random}};
    regValid2 = {1{$random}};
    regValid1 = {1{$random}};
    regReqCount = {1{$random}};
    regState = {1{$random}};
    regWordsLeft = {1{$random}};
    regReadAddr = {1{$random}};
  end

`endif

  assign T0 = {io_readData2, io_readData1};
  assign T37 = reset ? 1'h0 : regValid2;
  assign T38 = reset ? 1'h0 : regValid1;
  assign T39 = reset ? 1'h0 : T1;
  assign T1 = T30 & T2;
  assign T2 = T3 ^ 1'h1;
  assign T3 = regReqCount == 4'h0;
  assign T40 = T41[2'h3:1'h0];
  assign T41 = reset ? 32'h0 : T4;
  assign T4 = T1 ? T46 : T5;
  assign T5 = T26 ? T24 : T42;
  assign T42 = {28'h0, T6};
  assign T6 = T7 ? 4'h0 : regReqCount;
  assign T7 = 2'h0 == regState;
  assign T43 = reset ? 2'h0 : T8;
  assign T8 = T21 ? 2'h0 : T9;
  assign T9 = T20 ? 2'h1 : T10;
  assign T10 = T26 ? 2'h2 : T11;
  assign T11 = T14 ? 2'h3 : T12;
  assign T12 = T13 ? 2'h1 : regState;
  assign T13 = T7 & io_start;
  assign T14 = T19 & T15;
  assign T15 = regWordsLeft == 32'h0;
  assign T44 = reset ? 32'h0 : T16;
  assign T16 = T1 ? T18 : T17;
  assign T17 = T7 ? T45 : regWordsLeft;
  assign T45 = {16'h0, io_wordCount};
  assign T18 = regWordsLeft - 32'h1;
  assign T19 = 2'h1 == regState;
  assign T20 = T30 & T3;
  assign T21 = T23 & T22;
  assign T22 = io_start ^ 1'h1;
  assign T23 = 2'h3 == regState;
  assign T24 = T25 ? 32'h3 : regWordsLeft;
  assign T25 = 32'h3 < regWordsLeft;
  assign T26 = T19 & T27;
  assign T27 = T28 & hasRoom;
  assign hasRoom = resDumpQueue_io_count < 5'h9;
  assign T28 = T15 ^ 1'h1;
  assign T46 = {28'h0, T29};
  assign T29 = regReqCount - 4'h1;
  assign T30 = 2'h2 == regState;
  assign resultVector_TDATA = resDumpQueue_io_deq_bits;
  assign resultVector_TVALID = resDumpQueue_io_deq_valid;
  assign io_readAddr2 = T47;
  assign T47 = T31[5'h13:1'h0];
  assign T31 = T32 << 3'h5;
  assign T32 = regReadAddr + 20'h1;
  assign T48 = reset ? 20'h0 : T33;
  assign T33 = T1 ? T35 : T34;
  assign T34 = T7 ? 20'h0 : regReadAddr;
  assign T35 = regReadAddr + 20'h2;
  assign io_readAddr1 = T49;
  assign T49 = T36[5'h13:1'h0];
  assign T36 = regReadAddr << 3'h5;
  assign io_finished = T23;
  Queue resDumpQueue(.clk(clk), .reset(reset),

       .io_enq_valid( regValid3 ),
       .io_enq_bits( T0 ),
       .io_deq_ready( resultVector_TREADY ),
       .io_deq_valid( resDumpQueue_io_deq_valid ),
       .io_deq_bits( resDumpQueue_io_deq_bits ),
       .io_count( resDumpQueue_io_count )
  );

  always @(posedge clk) begin
    if(reset) begin
      regValid3 <= 1'h0;
    end else begin
      regValid3 <= regValid2;
    end
    if(reset) begin
      regValid2 <= 1'h0;
    end else begin
      regValid2 <= regValid1;
    end
    if(reset) begin
      regValid1 <= 1'h0;
    end else begin
      regValid1 <= T1;
    end
    regReqCount <= T40;
    if(reset) begin
      regState <= 2'h0;
    end else if(T21) begin
      regState <= 2'h0;
    end else if(T20) begin
      regState <= 2'h1;
    end else if(T26) begin
      regState <= 2'h2;
    end else if(T14) begin
      regState <= 2'h3;
    end else if(T13) begin
      regState <= 2'h1;
    end
    if(reset) begin
      regWordsLeft <= 32'h0;
    end else if(T1) begin
      regWordsLeft <= T18;
    end else if(T7) begin
      regWordsLeft <= T45;
    end
    if(reset) begin
      regReadAddr <= 20'h0;
    end else if(T1) begin
      regReadAddr <= T35;
    end else if(T7) begin
      regReadAddr <= 20'h0;
    end
  end
endmodule