data/full_repos/permissive/525452387/testbench/if_id_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/if_id_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    always #1 begin\n           ^\n%Error: data/full_repos/permissive/525452387/testbench/if_id_tb.v:64: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("if_id.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/if_id_tb.v:65: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, if_id_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module if_id_test_bench;
    reg if_id_1_clk;
    reg if_id_1_rst_;
    reg[31:0] if_id_1_inst_i;
    reg[31:0] if_id_1_inst_addr_i;

    wire[31:0] if_id_1_inst_o;
    wire[31:0] if_id_1_inst_addr_o;

    if_id if_id_1 (
        .clk  (if_id_1_clk),
        .rst_ (if_id_1_rst_),

        .inst_i(if_id_1_inst_i),
        .inst_addr_i(if_id_1_inst_addr_i),

        .inst_o(if_id_1_inst_o),
        .inst_addr_o(if_id_1_inst_addr_o)
    );

    initial begin
        #0 begin
            if_id_1_clk <= 1'b1;
            if_id_1_rst_ <= 0;
        end


        #1 begin
            if (if_id_1_inst_addr_o == 32'h0 && if_id_1_inst_o == 32'h00000013) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            if_id_1_rst_ <= 1;
            if_id_1_inst_addr_i <= 32'hDEADBEEF;
            if_id_1_inst_i <= 32'hBABECAFE;
        end


        #1 begin
            if (if_id_1_inst_addr_o == 32'hDEADBEEF && if_id_1_inst_o == 32'hBABECAFE) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        if_id_1_clk <= ~if_id_1_clk;
    end

    initial begin
        $dumpfile("if_id.vcd");
        $dumpvars(0, if_id_1);
    end

endmodule
module if_id_test_bench;

    reg if_id_1_clk;
    reg if_id_1_rst_;
    reg[31:0] if_id_1_inst_i;
    reg[31:0] if_id_1_inst_addr_i;

    wire[31:0] if_id_1_inst_o;
    wire[31:0] if_id_1_inst_addr_o;

    if_id if_id_1 (
        .clk  (if_id_1_clk),
        .rst_ (if_id_1_rst_),

        .inst_i(if_id_1_inst_i),
        .inst_addr_i(if_id_1_inst_addr_i),

        .inst_o(if_id_1_inst_o),
        .inst_addr_o(if_id_1_inst_addr_o)
    );

    initial begin
        #0 begin
            if_id_1_clk <= 1'b1;
            if_id_1_rst_ <= 0;
        end


        #1 begin
            if (if_id_1_inst_addr_o == 32'h0 && if_id_1_inst_o == 32'h00000013) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            if_id_1_rst_ <= 1;
            if_id_1_inst_addr_i <= 32'hDEADBEEF;
            if_id_1_inst_i <= 32'hBABECAFE;
        end


        #1 begin
            if (if_id_1_inst_addr_o == 32'hDEADBEEF && if_id_1_inst_o == 32'hBABECAFE) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        if_id_1_clk <= ~if_id_1_clk;
    end

    initial begin
        $dumpfile("if_id.vcd");
        $dumpvars(0, if_id_1);
    end

endmodule