data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #2;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:64: Unsupported or unknown PLI call: $urandom\n   a = $urandom & ~(1 << (SIZEIN-1));\n       ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:65: Unsupported or unknown PLI call: $urandom\n   b = $urandom & ~(1 << (SIZEIN-1));\n       ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc_tb.v:77: syntax error, unexpected ref, expecting IDENTIFIER\n macc2 ref (\n       ^~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    parameter SIZEIN = 16, SIZEOUT = 40;
	reg clk, ce, rst;
   	reg signed [SIZEIN-1:0] a, b;
	output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
	output REF_overflow, overflow;

	integer errcount = 0;

	reg ERROR_FLAG = 0;

	task clkcycle;
		begin
			#5;
			clk = ~clk;
			#10;
			clk = ~clk;
			#2;
			ERROR_FLAG = 0;
			if (REF_accum_out !== accum_out) begin
				$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
				errcount = errcount + 1;
				ERROR_FLAG = 1;
			end
			if (REF_overflow !== overflow) begin
				$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
				errcount = errcount + 1;
				ERROR_FLAG = 1;
			end
			#3;
		end
	endtask

	initial begin



		#2;
		clk = 1'b0;
        ce = 1'b0;
        a = 0;
        b = 0;

        rst = 1'b1;
		repeat (10) begin
			#10;
			clk = 1'b1;
			#10;
			clk = 1'b0;
			#10;
			clk = 1'b1;
			#10;
			clk = 1'b0;
		end
		rst = 1'b0;

		repeat (10000) begin
			clkcycle;
            ce = 1;

			a = $urandom & ~(1 << (SIZEIN-1));
			b = $urandom & ~(1 << (SIZEIN-1));
		end

		if (errcount == 0) begin
			$display("All tests passed.");
			$finish;
		end else begin
			$display("Caught %1d errors.", errcount);
			$stop;
		end
	end

	macc2 ref (
        .clk(clk),
        .ce(ce),
        .rst(rst),
        .a(a),
        .b(b),
        .accum_out(REF_accum_out),
        .overflow(REF_overflow)
	);

	macc2_uut uut (
        .clk(clk),
        .ce(ce),
        .rst(rst),
        .a(a),
        .b(b),
        .accum_out(accum_out),
        .overflow(overflow)
	);
endmodule
module testbench;


    parameter SIZEIN = 16, SIZEOUT = 40;
	reg clk, ce, rst;
   	reg signed [SIZEIN-1:0] a, b;
	output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
	output REF_overflow, overflow;

	integer errcount = 0;

	reg ERROR_FLAG = 0;

	task clkcycle;
		begin
			#5;
			clk = ~clk;
			#10;
			clk = ~clk;
			#2;
			ERROR_FLAG = 0;
			if (REF_accum_out !== accum_out) begin
				$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
				errcount = errcount + 1;
				ERROR_FLAG = 1;
			end
			if (REF_overflow !== overflow) begin
				$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
				errcount = errcount + 1;
				ERROR_FLAG = 1;
			end
			#3;
		end
	endtask

	initial begin



		#2;
		clk = 1'b0;
        ce = 1'b0;
        a = 0;
        b = 0;

        rst = 1'b1;
		repeat (10) begin
			#10;
			clk = 1'b1;
			#10;
			clk = 1'b0;
			#10;
			clk = 1'b1;
			#10;
			clk = 1'b0;
		end
		rst = 1'b0;

		repeat (10000) begin
			clkcycle;
            ce = 1;

			a = $urandom & ~(1 << (SIZEIN-1));
			b = $urandom & ~(1 << (SIZEIN-1));
		end

		if (errcount == 0) begin
			$display("All tests passed.");
			$finish;
		end else begin
			$display("Caught %1d errors.", errcount);
			$stop;
		end
	end

	macc2 ref (
        .clk(clk),
        .ce(ce),
        .rst(rst),
        .a(a),
        .b(b),
        .accum_out(REF_accum_out),
        .overflow(REF_overflow)
	);

	macc2_uut uut (
        .clk(clk),
        .ce(ce),
        .rst(rst),
        .a(a),
        .b(b),
        .accum_out(accum_out),
        .overflow(overflow)
	);
endmodule