data/full_repos/permissive/40989439/ohLocal/memory/dv/fifo_async_104x32.v
1: b"%Error: data/full_repos/permissive/40989439/ohLocal/memory/dv/fifo_async_104x32.v:18: Input/output/inout does not appear in port list: 'wr_rst'\n   input           wr_rst;      \n                   ^~~~~~\n%Error: data/full_repos/permissive/40989439/ohLocal/memory/dv/fifo_async_104x32.v:19: Input/output/inout does not appear in port list: 'rd_rst'\n   input           rd_rst;      \n                   ^~~~~~\n%Error: data/full_repos/permissive/40989439/ohLocal/memory/dv/fifo_async_104x32.v:30: Input/output/inout does not appear in port list: 'almost_full'\n   output     almost_full;\n              ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module fifo_async_104x32 
   (

   full, prog_full, dout, empty, valid,

   rst, wr_clk, rd_clk, wr_en, din, rd_en
   );
   
   parameter DW     = 104;
   parameter DEPTH  = 16;






   input           wr_rst;
   input           rd_rst;
   input           wr_clk;
   input           rd_clk;




   input           wr_en;   
   input  [DW-1:0] din;
   output          full;
   output 	   prog_full;
   output 	   almost_full;
   



   input 	   rd_en;
   output [DW-1:0] dout;
   output          empty;
   output          valid;

   input 	   rst;


   defparam fifo_model.DW=104;   
   defparam fifo_model.DEPTH=32;   

   fifo_async_model fifo_model (

				.full		(full),
				.prog_full	(prog_full),

				.dout		(dout[DW-1:0]),
				.empty		(empty),
				.valid		(valid),

				.rst (rst),


				.wr_clk		(wr_clk),
				.rd_clk		(rd_clk),
				.wr_en		(wr_en),
				.din		(din[DW-1:0]),
				.rd_en		(rd_en));
      
      
endmodule
module fifo_async_104x32 
   (

   full, prog_full, dout, empty, valid,

   rst, wr_clk, rd_clk, wr_en, din, rd_en
   );

   
   parameter DW     = 104;
   parameter DEPTH  = 16;






   input           wr_rst;
   input           rd_rst;
   input           wr_clk;
   input           rd_clk;




   input           wr_en;   
   input  [DW-1:0] din;
   output          full;
   output 	   prog_full;
   output 	   almost_full;
   



   input 	   rd_en;
   output [DW-1:0] dout;
   output          empty;
   output          valid;

   input 	   rst;


   defparam fifo_model.DW=104;   
   defparam fifo_model.DEPTH=32;   

   fifo_async_model fifo_model (

				.full		(full),
				.prog_full	(prog_full),

				.dout		(dout[DW-1:0]),
				.empty		(empty),
				.valid		(valid),

				.rst (rst),


				.wr_clk		(wr_clk),
				.rd_clk		(rd_clk),
				.wr_en		(wr_en),
				.din		(din[DW-1:0]),
				.rd_en		(rd_en));
      
      
endmodule