data/full_repos/permissive/439731184/mul.v
1: b'%Error: data/full_repos/permissive/439731184/mul.v:68: Unsupported or unknown PLI call: $urandom\n    r = $urandom;\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/mul.v:63: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/mul.v:74: Unsupported or unknown PLI call: $urandom\n    $urandom(SEED);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/mul.v:76: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%h\\t%h\\t%h\\t%h\\t%b", $time, a, b, c, d, e);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/mul.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #(N_TESTS) $display("TEST PASSED");\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mul #(parameter N_BITS = 4) (a, b, c);

input wire [N_BITS-1:0] a, b;
output wire [2*N_BITS-1:0] c;

wire [2*N_BITS-1:0] d [0:N_BITS-1];
wire [2*N_BITS-2:0] e [0:N_BITS-1];

assign d[0] = b[0] ? {{(N_BITS) {1'b0}}, a} : 0;

genvar i;
    for (i=1; i<N_BITS; i=i+1) begin: block_index
        assign e[i-1] = b[i] ? {{(N_BITS-i) {1'b0}}, a, {i {1'b0}}} : 0;
        add #(2*N_BITS-1) A (d[i-1][2*N_BITS-2:0], e[i-1], d[i]);
    end
generate

assign c = d[N_BITS-1];

endgenerate

endmodule
module mul #(parameter N_BITS = 4) (a, b, c);


input wire [N_BITS-1:0] a, b;
output wire [2*N_BITS-1:0] c;

wire [2*N_BITS-1:0] d [0:N_BITS-1];
wire [2*N_BITS-2:0] e [0:N_BITS-1];

assign d[0] = b[0] ? {{(N_BITS) {1'b0}}, a} : 0;

genvar i;
    for (i=1; i<N_BITS; i=i+1) begin: block_index
        assign e[i-1] = b[i] ? {{(N_BITS-i) {1'b0}}, a, {i {1'b0}}} : 0;
        add #(2*N_BITS-1) A (d[i-1][2*N_BITS-2:0], e[i-1], d[i]);
    end
generate

assign c = d[N_BITS-1];

endgenerate

endmodule