data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #OFFSET\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:68: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #600 btnR = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #80 btnR = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:86: Unsupported: Ignoring delay on this delayed statement.\n     #OFFSET;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:87: Unsupported: Ignoring delay on this delayed statement.\n     #0.1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #880;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:92: Unsupported: Ignoring delay on this delayed statement.\n     #700;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:95: Unsupported: Ignoring delay on this delayed statement.\n     #40;   \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:99: Unsupported: Ignoring delay on this delayed statement.\n       #(640*40);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:101: Unsupported: Ignoring delay on this delayed statement.\n         #(15*40);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:103: Unsupported: Ignoring delay on this delayed statement.\n         #((96)*40);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:105: Unsupported: Ignoring delay on this delayed statement.\n         #(49*40);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:112: Unsupported: Ignoring delay on this delayed statement.\n     #OFFSET;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:113: Unsupported: Ignoring delay on this delayed statement.\n     #0.1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:116: Unsupported: Ignoring delay on this delayed statement.\n     #880;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:117: Unsupported: Ignoring delay on this delayed statement.\n     #700;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:120: Unsupported: Ignoring delay on this delayed statement.\n     #40;   \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:127: Unsupported: Ignoring delay on this delayed statement.\n            #(480*800*40);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #(9*800*40); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:131: Unsupported: Ignoring delay on this delayed statement.\n          #(2*800*40);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:133: Unsupported: Ignoring delay on this delayed statement.\n          #(34*800*40);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:209: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'rgb_error\' generates 1 bits.\n                                                                                                               : ... In instance testSyncs.RUT\n     RGBERRORS  <= RGBERRORS + rgb_error;    \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:180: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'sync_error\' generates 1 bits.\n                                                                                                               : ... In instance testSyncs.GUT\n     SERRORS  <= SERRORS + sync_error;    \n                         ^\n%Error: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads/test2.v:41: Cannot find file containing module: \'TopLevel\'\n   TopLevel UUT (\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads,data/full_repos/permissive/469509877/TopLevel\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads,data/full_repos/permissive/469509877/TopLevel.v\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/imports/Downloads,data/full_repos/permissive/469509877/TopLevel.sv\n             TopLevel\n             TopLevel.v\n             TopLevel.sv\n             obj_dir/TopLevel\n             obj_dir/TopLevel.v\n             obj_dir/TopLevel.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testSyncs();


   reg btnC,btnR,btnD,btnL,btnU;
   reg [15:0] sw;
   reg clkin;


   wire [3:0] an;
   wire dp;
   wire [6:0] seg;
   wire [15:0] led;
   wire HS, VS;
   wire [3:0] vgaRed, vgaBlue, vgaGreen;
   wire oops;
   wire rgb_oops;






   TopLevel UUT (
		.clkin(clkin), 
		.vgaBlue(vgaBlue),
		.vgaRed(vgaRed),
		.vgaGreen(vgaGreen), 	
		.Vsync(VS), 
		.Hsync(HS), 
		.sw(sw) 
   );
   	
	reg good_HS;
	reg good_VS;
	reg activeH;
	reg activeV;
 

   parameter PERIOD = 10;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET = 2;

	initial
	begin
		clkin = 1'b0;
	   #OFFSET
		clkin = 1'b1;
      forever
         begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;
         end
	end
	
	initial
	  begin
       sw = 16'b0;
       btnR = 1'b0;
       btnU = 1'b0;
       btnL = 1'b0;
       btnD = 1'b0;
	   #600 btnR = 1'b1;
	   #80 btnR = 1'b0;
	  end
	 

   initial
	  begin
	    #OFFSET;
	    #0.1;
	   
		activeH = 1'b1;
        good_HS = 1'b1;
        #880;
	    #700;


	    #40;
	    forever 
		    begin
			  activeH = 1'b1;
		     #(640*40);
			  activeH = 1'b0;
	        #(15*40);
	        good_HS = 1'b0;
	        #((96)*40);
	        good_HS = 1'b1;
	        #(49*40);
	       end
     end


   initial
	  begin
	    #OFFSET;
	    #0.1;
		activeV = 1'b1;
	    good_VS = 1'b1;
	    #880;
	    #700;


	    #40;



		 forever 
		    begin
            activeV = 1'b1;
            #(480*800*40);
            activeV=1'b0;		 
		      #(9*800*40); 
	         good_VS = 1'b0;
	         #(2*800*40);
	         good_VS = 1'b1;
	         #(34*800*40);
	       end
     end




   check_the_sync_signals GUT (
		.myHS(HS), 
		.myVS(VS), 
		.correct_HS(good_HS), 
		.correct_VS(good_VS),
		.clk(clkin),
		.btnR(btnR),
		.sync_error(oops)
   );
	


   check_the_rgb_signals RUT (.VB(vgaBlue), .VG(vgaGreen), .VR(vgaRed),
       .activeH(activeH), .activeV(activeV),
	    .clk(clkin),
	 	 .btnR(btnR),
		 .rgb_error(rgb_oops)
   );	

endmodule
module testSyncs();



   reg btnC,btnR,btnD,btnL,btnU;
   reg [15:0] sw;
   reg clkin;


   wire [3:0] an;
   wire dp;
   wire [6:0] seg;
   wire [15:0] led;
   wire HS, VS;
   wire [3:0] vgaRed, vgaBlue, vgaGreen;
   wire oops;
   wire rgb_oops;






   TopLevel UUT (
		.clkin(clkin), 
		.vgaBlue(vgaBlue),
		.vgaRed(vgaRed),
		.vgaGreen(vgaGreen), 	
		.Vsync(VS), 
		.Hsync(HS), 
		.sw(sw) 
   );
   	
	reg good_HS;
	reg good_VS;
	reg activeH;
	reg activeV;
 

   parameter PERIOD = 10;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET = 2;

	initial
	begin
		clkin = 1'b0;
	   #OFFSET
		clkin = 1'b1;
      forever
         begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clkin = ~clkin;
         end
	end
	
	initial
	  begin
       sw = 16'b0;
       btnR = 1'b0;
       btnU = 1'b0;
       btnL = 1'b0;
       btnD = 1'b0;
	   #600 btnR = 1'b1;
	   #80 btnR = 1'b0;
	  end
	 

   initial
	  begin
	    #OFFSET;
	    #0.1;
	   
		activeH = 1'b1;
        good_HS = 1'b1;
        #880;
	    #700;


	    #40;
	    forever 
		    begin
			  activeH = 1'b1;
		     #(640*40);
			  activeH = 1'b0;
	        #(15*40);
	        good_HS = 1'b0;
	        #((96)*40);
	        good_HS = 1'b1;
	        #(49*40);
	       end
     end


   initial
	  begin
	    #OFFSET;
	    #0.1;
		activeV = 1'b1;
	    good_VS = 1'b1;
	    #880;
	    #700;


	    #40;



		 forever 
		    begin
            activeV = 1'b1;
            #(480*800*40);
            activeV=1'b0;		 
		      #(9*800*40); 
	         good_VS = 1'b0;
	         #(2*800*40);
	         good_VS = 1'b1;
	         #(34*800*40);
	       end
     end




   check_the_sync_signals GUT (
		.myHS(HS), 
		.myVS(VS), 
		.correct_HS(good_HS), 
		.correct_VS(good_VS),
		.clk(clkin),
		.btnR(btnR),
		.sync_error(oops)
   );
	


   check_the_rgb_signals RUT (.VB(vgaBlue), .VG(vgaGreen), .VR(vgaRed),
       .activeH(activeH), .activeV(activeV),
	    .clk(clkin),
	 	 .btnR(btnR),
		 .rgb_error(rgb_oops)
   );	

endmodule