data/full_repos/permissive/464991782/ALU8.v
1: b"%Error: data/full_repos/permissive/464991782/ALU8.v:25: Cannot find file containing module: 'ALU1'\n    ALU1 a(F[i], WireCarry[i+1], S1, S0, A[i], B[i], WireCarry[i]);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/ALU1\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/ALU1.v\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/ALU1.sv\n             ALU1\n             ALU1.v\n             ALU1.sv\n             obj_dir/ALU1\n             obj_dir/ALU1.v\n             obj_dir/ALU1.sv\n%Error: Exiting due to 1 error(s)\n"
module ALU8Bit (S1, S0, A, B, CarryIn, CarryOut, F);
input [7:0] A, B;
input S1, S0, CarryIn;
output [7:0] F;
output CarryOut;

wire WireCarry[8:0];
genvar i;
assign CarryOut = WireCarry[8];
assign WireCarry[0] = S1 & ~S0 | CarryIn;

generate
  for (i=0; i < 8; i = i+1)
  begin:ALU
    ALU1 a(F[i], WireCarry[i+1], S1, S0, A[i], B[i], WireCarry[i]);
  end
endgenerate
endmodule
module ALU8Bit (S1, S0, A, B, CarryIn, CarryOut, F);

input [7:0] A, B;
input S1, S0, CarryIn;
output [7:0] F;
output CarryOut;

wire WireCarry[8:0];
genvar i;
assign CarryOut = WireCarry[8];
assign WireCarry[0] = S1 & ~S0 | CarryIn;

generate
  for (i=0; i < 8; i = i+1)
  begin:ALU
    ALU1 a(F[i], WireCarry[i+1], S1, S0, A[i], B[i], WireCarry[i]);
  end
endgenerate
endmodule