data/full_repos/permissive/468612001/Week07/no_pipeline/tb_pipeline.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week07/no_pipeline/tb_pipeline.v:16: Unsupported: Ignoring delay on this delayed statement.\n #400 $stop;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week07/no_pipeline/tb_pipeline.v:20: Unsupported: Ignoring delay on this delayed statement.\n #20 clock = !clock;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week07/no_pipeline/tb_pipeline.v:24: Unsupported: Ignoring delay on this delayed statement.\n #40 a = a + 3\'d1; b = b + 3\'d1; c = c + 3\'d1; d = d + 3\'d1;\n ^\n%Error: data/full_repos/permissive/468612001/Week07/no_pipeline/tb_pipeline.v:10: Cannot find file containing module: \'pipeline\'\npipeline Np1(.a(a), .b(b), .c(c), .d(d), .y(y), .clock(clock), .reset(reset));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week07/no_pipeline,data/full_repos/permissive/468612001/pipeline\n             data/full_repos/permissive/468612001/Week07/no_pipeline,data/full_repos/permissive/468612001/pipeline.v\n             data/full_repos/permissive/468612001/Week07/no_pipeline,data/full_repos/permissive/468612001/pipeline.sv\n             pipeline\n             pipeline.v\n             pipeline.sv\n             obj_dir/pipeline\n             obj_dir/pipeline.v\n             obj_dir/pipeline.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_pipeline();

reg reset, clock;

reg[2:0] a, b, c, d;
wire[7:0] y;

pipeline Np1(.a(a), .b(b), .c(c), .d(d), .y(y), .clock(clock), .reset(reset));

initial begin
	clock = 1'b1; reset = 1'b1;
	a = 3'd1;	b = 3'd2;
	c = 3'd3;	d = 3'd4;
	#400 $stop;
end

always begin
	#20 clock = !clock;
end

always begin
	#40 a = a + 3'd1; b = b + 3'd1; c = c + 3'd1; d = d + 3'd1;
end

endmodule
module tb_pipeline();


reg reset, clock;

reg[2:0] a, b, c, d;
wire[7:0] y;

pipeline Np1(.a(a), .b(b), .c(c), .d(d), .y(y), .clock(clock), .reset(reset));

initial begin
	clock = 1'b1; reset = 1'b1;
	a = 3'd1;	b = 3'd2;
	c = 3'd3;	d = 3'd4;
	#400 $stop;
end

always begin
	#20 clock = !clock;
end

always begin
	#40 a = a + 3'd1; b = b + 3'd1; c = c + 3'd1; d = d + 3'd1;
end

endmodule