data/full_repos/permissive/460183508/rtl/sync_gen.v
1: b"%Error: data/full_repos/permissive/460183508/rtl/sync_gen.v:37: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'WIDTH'\n                                                              : ... In instance sync_gen\n#(parameter WIDTH,\n            ^~~~~\n%Error: data/full_repos/permissive/460183508/rtl/sync_gen.v:38: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ACTIVE_COUNT'\n                                                              : ... In instance sync_gen\n            ACTIVE_COUNT,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/460183508/rtl/sync_gen.v:39: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'FRONT_COUNT'\n                                                              : ... In instance sync_gen\n            FRONT_COUNT,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/460183508/rtl/sync_gen.v:40: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'SYNC_COUNT'\n                                                              : ... In instance sync_gen\n            SYNC_COUNT,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/460183508/rtl/sync_gen.v:41: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'RESET_COUNT'\n                                                              : ... In instance sync_gen\n            RESET_COUNT\n            ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module sync_gen
#(parameter WIDTH,
            ACTIVE_COUNT,
            FRONT_COUNT,
            SYNC_COUNT,
            RESET_COUNT
)
(
    input wire reset,
    input wire clk,
    output wire backporch,
    output wire active,
    output wire frontporch,
    output wire sync
);

    localparam [1:0]
        STATE_BACKPORCH = 2'b00,
        STATE_ACTIVE = 2'b01,
        STATE_FRONTPORCH = 2'b10,
        STATE_SYNC = 2'b11;


    reg[WIDTH-1:0] count = 0;
    

    reg[1:0] state = 0;
    

    wire sm_clk = (count == ACTIVE_COUNT) |
                  (count == FRONT_COUNT) |
                  (count == SYNC_COUNT) |
                  (count == RESET_COUNT);


    assign backporch = (state == STATE_BACKPORCH);
    assign active = (state == STATE_ACTIVE);
    assign frontporch = (state == STATE_FRONTPORCH);
    assign sync = (state == STATE_SYNC);
    

    always @(posedge clk, posedge reset)
    begin
        if (reset) begin

            count <= {WIDTH{1'b0}};
        end
        else if (count == RESET_COUNT) begin

            count <= {WIDTH{1'b0}};
        end
        else begin

            count <= count + 1'b1;
        end
    end
    

    always @(posedge sm_clk, posedge reset)
    begin
        if (reset) begin

            state <= STATE_BACKPORCH;
        end
        else begin
            case (state)
                STATE_BACKPORCH:

                    state <= STATE_ACTIVE;
                
                STATE_ACTIVE:

                    state <= STATE_FRONTPORCH;
                
                STATE_FRONTPORCH:

                    state <= STATE_SYNC;
                
                STATE_SYNC:

                    state <= STATE_BACKPORCH;
            endcase
        end
    end
endmodule
module sync_gen
#(parameter WIDTH,
            ACTIVE_COUNT,
            FRONT_COUNT,
            SYNC_COUNT,
            RESET_COUNT
)
(
    input wire reset,
    input wire clk,
    output wire backporch,
    output wire active,
    output wire frontporch,
    output wire sync
);


    localparam [1:0]
        STATE_BACKPORCH = 2'b00,
        STATE_ACTIVE = 2'b01,
        STATE_FRONTPORCH = 2'b10,
        STATE_SYNC = 2'b11;


    reg[WIDTH-1:0] count = 0;
    

    reg[1:0] state = 0;
    

    wire sm_clk = (count == ACTIVE_COUNT) |
                  (count == FRONT_COUNT) |
                  (count == SYNC_COUNT) |
                  (count == RESET_COUNT);


    assign backporch = (state == STATE_BACKPORCH);
    assign active = (state == STATE_ACTIVE);
    assign frontporch = (state == STATE_FRONTPORCH);
    assign sync = (state == STATE_SYNC);
    

    always @(posedge clk, posedge reset)
    begin
        if (reset) begin

            count <= {WIDTH{1'b0}};
        end
        else if (count == RESET_COUNT) begin

            count <= {WIDTH{1'b0}};
        end
        else begin

            count <= count + 1'b1;
        end
    end
    

    always @(posedge sm_clk, posedge reset)
    begin
        if (reset) begin

            state <= STATE_BACKPORCH;
        end
        else begin
            case (state)
                STATE_BACKPORCH:

                    state <= STATE_ACTIVE;
                
                STATE_ACTIVE:

                    state <= STATE_FRONTPORCH;
                
                STATE_FRONTPORCH:

                    state <= STATE_SYNC;
                
                STATE_SYNC:

                    state <= STATE_BACKPORCH;
            endcase
        end
    end
endmodule