data/full_repos/permissive/504478691/temperature/temperature.v
1: b"%Error: data/full_repos/permissive/504478691/temperature/temperature.v:8: Cannot find file containing module: 'integer_display'\ninteger_display integer_display_inst(.n(tmp), .clk(clk), .blink(0), .blink_ena(0), .anode(anode), .cathode(cathode));\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/temperature,data/full_repos/permissive/504478691/integer_display\n             data/full_repos/permissive/504478691/temperature,data/full_repos/permissive/504478691/integer_display.v\n             data/full_repos/permissive/504478691/temperature,data/full_repos/permissive/504478691/integer_display.sv\n             integer_display\n             integer_display.v\n             integer_display.sv\n             obj_dir/integer_display\n             obj_dir/integer_display.v\n             obj_dir/integer_display.sv\n%Error: Exiting due to 1 error(s)\n"
module temperature(input clk, inout sda, output reg scl = 0, output [7:0] anode, output [6:0] cathode, output dp);
reg [7:0] addr_and_state = 8'b100_1011_1;
reg [7:0] msb, lsb;
wire [15:0] tmp;
assign tmp = ({msb, lsb} >> 3) * 625 / 1000;
reg sda_r = 1, sda_link = 0;
assign sda = sda_link ? sda_r : 1'bz;
integer_display integer_display_inst(.n(tmp), .clk(clk), .blink(0), .blink_ena(0), .anode(anode), .cathode(cathode));
assign dp = anode[1];
reg mid = 0, get_tmp = 0;
integer state = 0, i = 0, n = 0, n_1 = 0;








always @(posedge clk)
begin

    if (n == 250)
    begin
        if (!mid)

            scl = ~scl;
        else
        begin

            if (!scl)

                if (get_tmp)
                    case(state)
                        0: state = 0;
                        1: sda_r = addr_and_state[7 - i];
                        2:
                            begin
                                sda_r = 1;
                                sda_link = 0;
                            end
                        3: sda_link = 0;
                        4:
                            begin
                                sda_r = 0;
                                sda_link = 1;
                            end
                        5: sda_link = 0;
                        6:
                            begin
                                sda_r = 0;
                                sda_link = 1;
                            end
                    endcase
                else
                    state = 0;
            else

                if (get_tmp)
                    case(state)
                        0:
                            begin
                                sda_link = 1;
                                sda_r = 0;
                                state = 1;
                                i = 0;
                            end
                        1:
                            if (i < 7)
                                i = i + 1;
                            else
                                state = 2;
                        2: 
                            begin
                                state = 3;
                                i = 0;
                            end
                        3:
                            begin
                                msb[7 - i] = sda;
                                if (i < 7)
                                    i = i + 1;
                                else
                                    state = 4;
                            end
                        4:
                            begin
                                state = 5;
                                i = 0;
                            end
                        5:
                            begin
                                lsb[7 - i] = sda;
                                if (i < 7)
                                    i = i + 1;
                                else
                                    state = 6;
                            end
                        6:
                            begin
                                sda_r = 1;
                                sda_link = 0;
                                state = 0;
                                get_tmp = 0;
                            end
                    endcase
                else
                    state = 0;
        end
        mid = ~mid;
        n = 1;
        if (n_1 == 50_000_000 / 250)
        begin
            get_tmp = 1;
            n_1 = 1;
        end
        else
            n_1 = n_1 + 1;
    end
    else
        n = n + 1;
end
endmodule
module temperature(input clk, inout sda, output reg scl = 0, output [7:0] anode, output [6:0] cathode, output dp);

reg [7:0] addr_and_state = 8'b100_1011_1;
reg [7:0] msb, lsb;
wire [15:0] tmp;
assign tmp = ({msb, lsb} >> 3) * 625 / 1000;
reg sda_r = 1, sda_link = 0;
assign sda = sda_link ? sda_r : 1'bz;
integer_display integer_display_inst(.n(tmp), .clk(clk), .blink(0), .blink_ena(0), .anode(anode), .cathode(cathode));
assign dp = anode[1];
reg mid = 0, get_tmp = 0;
integer state = 0, i = 0, n = 0, n_1 = 0;








always @(posedge clk)
begin

    if (n == 250)
    begin
        if (!mid)

            scl = ~scl;
        else
        begin

            if (!scl)

                if (get_tmp)
                    case(state)
                        0: state = 0;
                        1: sda_r = addr_and_state[7 - i];
                        2:
                            begin
                                sda_r = 1;
                                sda_link = 0;
                            end
                        3: sda_link = 0;
                        4:
                            begin
                                sda_r = 0;
                                sda_link = 1;
                            end
                        5: sda_link = 0;
                        6:
                            begin
                                sda_r = 0;
                                sda_link = 1;
                            end
                    endcase
                else
                    state = 0;
            else

                if (get_tmp)
                    case(state)
                        0:
                            begin
                                sda_link = 1;
                                sda_r = 0;
                                state = 1;
                                i = 0;
                            end
                        1:
                            if (i < 7)
                                i = i + 1;
                            else
                                state = 2;
                        2: 
                            begin
                                state = 3;
                                i = 0;
                            end
                        3:
                            begin
                                msb[7 - i] = sda;
                                if (i < 7)
                                    i = i + 1;
                                else
                                    state = 4;
                            end
                        4:
                            begin
                                state = 5;
                                i = 0;
                            end
                        5:
                            begin
                                lsb[7 - i] = sda;
                                if (i < 7)
                                    i = i + 1;
                                else
                                    state = 6;
                            end
                        6:
                            begin
                                sda_r = 1;
                                sda_link = 0;
                                state = 0;
                                get_tmp = 0;
                            end
                    endcase
                else
                    state = 0;
        end
        mid = ~mid;
        n = 1;
        if (n_1 == 50_000_000 / 250)
        begin
            get_tmp = 1;
            n_1 = 1;
        end
        else
            n_1 = n_1 + 1;
    end
    else
        n = n + 1;
end
endmodule