data/full_repos/permissive/417288846/List_3/Task_3/stoper.v
data/verilator_xmls/11db30f6-6c84-4996-b994-2b0189c376f4.xml
module BCD(input clk, rst, output [3:0] num, output next);
    reg [3:0] num_buf;
    reg next_buf;
    always @(posedge clk or posedge rst)
    begin
        next_buf <= rst == 1 ? 0 : num_buf == 9;

        num_buf <= rst == 1 ? 0 :
                   num_buf == 9 ? 0 : num_buf + 1;
    end
    assign num = num_buf;
    assign next = next_buf;
endmodule
module BCD(input clk, rst, output [3:0] num, output next);

    reg [3:0] num_buf;
    reg next_buf;
    always @(posedge clk or posedge rst)
    begin
        next_buf <= rst == 1 ? 0 : num_buf == 9;

        num_buf <= rst == 1 ? 0 :
                   num_buf == 9 ? 0 : num_buf + 1;
    end
    assign num = num_buf;
    assign next = next_buf;
endmodule