data/full_repos/permissive/451270484/simple_registers/counters/counterup16_1clk_posedge_async_resetn/counterup16_1clk_posedge_async_resetn.v
data/verilator_xmls/d1d10527-8b2b-432c-8746-522220add70d.xml
module counterup16_1clk_posedge_async_resetn(clock0, reset, count);

	input clock0, reset;
	output [15:0] count;
	reg [15:0] count;  

	initial begin
      	  count <= 0;
    	end                                    

	always @ (posedge clock0 or negedge reset) begin
		if (reset == 1'b0) begin
			count <= 0;
		end 
		else begin
			count <= count + 1;
		end
	end 

endmodule
module counterup16_1clk_posedge_async_resetn(clock0, reset, count);


	input clock0, reset;
	output [15:0] count;
	reg [15:0] count;  

	initial begin
      	  count <= 0;
    	end                                    

	always @ (posedge clock0 or negedge reset) begin
		if (reset == 1'b0) begin
			count <= 0;
		end 
		else begin
			count <= count + 1;
		end
	end 

endmodule