data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module shift_tb;

    localparam WIDTH = 32;
    localparam LOGWIDTH = $clog2(WIDTH);

    reg  signed [WIDTH-1:0]     a;
    reg  [LOGWIDTH-1:0]  shamt;
    reg  [1:0]           type;
    wire [WIDTH-1:0]     r;

    `TB_INIT(shift_tb, "shift_tb.vcd", 0, 50_000)

    shift  muv (
        .a(a),
        .shamt(shamt),
        .type(type),
        .r(r)
    );


    wire [WIDTH-1:0] golden_r;
    assign golden_r =   (type==0) ? (a >> shamt ):
                        (type==2) ? ($signed(a) >>> shamt) :
                        (type==1) ? (a << shamt ) : a;


    always @(r) begin
        #1;
        if(golden_r != r)
            $display("Test Failed - %x %x %x = %x (should be %x)", a, type, shamt, r, golden_r);
    end

    initial begin
        a =32'hAB0BEEF8;
        shamt = 0;
        type = 0;
        #10;
        shamt = 1;
        #10;
        shamt = 2;
        #10;
        shamt = 3;
        #10;
        shamt = 4;
        #10;
        shamt = 5;
        #10;
        shamt = 6;
        #10;
        shamt = 7;
        #10;
        type = 1;
        #10;
        type = 2;
        #10;
        
        $finish;

    end
endmodule
module shift_tb;


    localparam WIDTH = 32;
    localparam LOGWIDTH = $clog2(WIDTH);

    reg  signed [WIDTH-1:0]     a;
    reg  [LOGWIDTH-1:0]  shamt;
    reg  [1:0]           type;
    wire [WIDTH-1:0]     r;

    `TB_INIT(shift_tb, "shift_tb.vcd", 0, 50_000)

    shift  muv (
        .a(a),
        .shamt(shamt),
        .type(type),
        .r(r)
    );


    wire [WIDTH-1:0] golden_r;
    assign golden_r =   (type==0) ? (a >> shamt ):
                        (type==2) ? ($signed(a) >>> shamt) :
                        (type==1) ? (a << shamt ) : a;


    always @(r) begin
        #1;
        if(golden_r != r)
            $display("Test Failed - %x %x %x = %x (should be %x)", a, type, shamt, r, golden_r);
    end

    initial begin
        a =32'hAB0BEEF8;
        shamt = 0;
        type = 0;
        #10;
        shamt = 1;
        #10;
        shamt = 2;
        #10;
        shamt = 3;
        #10;
        shamt = 4;
        #10;
        shamt = 5;
        #10;
        shamt = 6;
        #10;
        shamt = 7;
        #10;
        type = 1;
        #10;
        type = 2;
        #10;
        
        $finish;

    end
endmodule