data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_div_clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_div_clock.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_rst = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_div_clock.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_div_clock.v:48: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_div_clock.v:50: Cannot find file containing module: \'top_double_ram_sy\'\n    top_double_ram_sy test(\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/top_double_ram_sy\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/top_double_ram_sy.v\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/top_double_ram_sy.sv\n             top_double_ram_sy\n             top_double_ram_sy.v\n             top_double_ram_sy.sv\n             obj_dir/top_double_ram_sy\n             obj_dir/top_double_ram_sy.v\n             obj_dir/top_double_ram_sy.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_div_clock(

    );
        
reg clk, cs, rst;
reg [2:0] din_a;
reg [2:0] addr_a;
reg we_a, oe_a;
wire [2:0] dout_a;

reg [2:0] din_b;
reg [2:0] addr_b;
reg we_b, oe_b;
wire [2:0] dout_b;
wire [2:0] memout;
reg clk_rst;
reg load;

    initial begin
        clk  = 0;
        clk_rst = 0;
        #5 clk_rst = 1;
        #5 clk_rst = 0;
    end
    
    always #5 clk = ~clk;

    top_double_ram_sy test(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b,
    clk_rst,
    load
    );
endmodule
module sim_div_clock(

    );

        
reg clk, cs, rst;
reg [2:0] din_a;
reg [2:0] addr_a;
reg we_a, oe_a;
wire [2:0] dout_a;

reg [2:0] din_b;
reg [2:0] addr_b;
reg we_b, oe_b;
wire [2:0] dout_b;
wire [2:0] memout;
reg clk_rst;
reg load;

    initial begin
        clk  = 0;
        clk_rst = 0;
        #5 clk_rst = 1;
        #5 clk_rst = 0;
    end
    
    always #5 clk = ~clk;

    top_double_ram_sy test(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b,
    clk_rst,
    load
    );
endmodule