data/full_repos/permissive/432564927/Lab5 (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new/CPU_Test.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5\n%Error: Cannot find file containing module: (Verilog)/Lab5_Unal/Lab5_Unal.srcs/sim_1/new/CPU_Test.v\n%Error: Exiting due to 3 error(s)\n'
module CPU_Test();

    reg clk;

    wire [31:0] pcin;
    wire [31:0] pcout;
    wire [31:0] do;
    

    wire [5:0] op, func;
    wire [4:0] rd,rs,rt;
    wire [15:0] imm;
    wire [3:0] aluc;
    wire wreg;
    wire m2reg;
    wire wmem;
    wire aluimm;
    wire regrt;
    wire [4:0] rn;
    wire [31:0] qa,qb;
    wire [31:0] immExt;
    

    wire [3:0] ealuc;
    wire ewreg;
    wire em2reg;
    wire ewmem;
    wire ealuimm;
    wire [4:0] ern;
    wire [31:0] eqa, eqb;
    wire [31:0] eimmExt;
    wire [31:0] muxImm;
    wire [31:0] aluOut;
    

    wire mwreg;
    wire mm2reg;
    wire mwmem;
    wire [4:0] mrn;
    wire [31:0] maluOut;
    wire [31:0] mqb;
    wire [31:0] dmOut;
    

    wire wwreg;
    wire wm2reg;
    wire [4:0] wrn;
    wire [31:0] waluOut;
    wire [31:0] wdmOut;
    wire [31:0] wbMuxOut;
    



    PC PC(clk, pcin, pcout);
    PCAdder adder(pcout, pcin);
    InstMem instmem(pcout, do);
    

    IFID ifid(clk,do,
              op,rd,rs,rt,func,imm);
    

    ControlUnit CU(op,func,aluc,wreg,m2reg,wmem,aluimm,regrt);
    ControlMux ctrmux(rd,rt,regrt,rn);
    SignExtend extender(imm, immExt);
    

    IDEXE idexe(clk,wreg,m2reg,wmem,aluc,aluimm,rn,qa,qb,immExt,
                ewreg,em2reg,ewmem,ealuc,ealuimm,ern,eqa,eqb,eimmExt);
    

    ALUMux alumux(eqb,eimmExt,ealuimm,muxImm);
    ALU alu(eqa, muxImm, ealuc, aluOut);
    

    EXEMEM exemem(clk,ewreg,em2reg,ewmem,ern,aluOut,eqb,
                  mwreg,mm2reg,mwmem,mrn,maluOut,mqb);
    

    DataMemory datamem(maluOut,mqb,mwmem,dmOut);
    

    MEMWB memwb(clk,mwreg,mm2reg,mrn,maluOut,dmOut,
                wwreg,wm2reg,wrn,waluOut,wdmOut);
    

    WBMux wbmux(waluOut, wdmOut, wm2reg, wbMuxOut);
    RegFile regfile(clk,rs,rt,qa,qb,wrn,wbMuxOut);
    
    initial begin
        clk = 0;
    end            
    always begin
        #5 clk = !clk;
    end
endmodule
module CPU_Test();


    reg clk;

    wire [31:0] pcin;
    wire [31:0] pcout;
    wire [31:0] do;
    

    wire [5:0] op, func;
    wire [4:0] rd,rs,rt;
    wire [15:0] imm;
    wire [3:0] aluc;
    wire wreg;
    wire m2reg;
    wire wmem;
    wire aluimm;
    wire regrt;
    wire [4:0] rn;
    wire [31:0] qa,qb;
    wire [31:0] immExt;
    

    wire [3:0] ealuc;
    wire ewreg;
    wire em2reg;
    wire ewmem;
    wire ealuimm;
    wire [4:0] ern;
    wire [31:0] eqa, eqb;
    wire [31:0] eimmExt;
    wire [31:0] muxImm;
    wire [31:0] aluOut;
    

    wire mwreg;
    wire mm2reg;
    wire mwmem;
    wire [4:0] mrn;
    wire [31:0] maluOut;
    wire [31:0] mqb;
    wire [31:0] dmOut;
    

    wire wwreg;
    wire wm2reg;
    wire [4:0] wrn;
    wire [31:0] waluOut;
    wire [31:0] wdmOut;
    wire [31:0] wbMuxOut;
    



    PC PC(clk, pcin, pcout);
    PCAdder adder(pcout, pcin);
    InstMem instmem(pcout, do);
    

    IFID ifid(clk,do,
              op,rd,rs,rt,func,imm);
    

    ControlUnit CU(op,func,aluc,wreg,m2reg,wmem,aluimm,regrt);
    ControlMux ctrmux(rd,rt,regrt,rn);
    SignExtend extender(imm, immExt);
    

    IDEXE idexe(clk,wreg,m2reg,wmem,aluc,aluimm,rn,qa,qb,immExt,
                ewreg,em2reg,ewmem,ealuc,ealuimm,ern,eqa,eqb,eimmExt);
    

    ALUMux alumux(eqb,eimmExt,ealuimm,muxImm);
    ALU alu(eqa, muxImm, ealuc, aluOut);
    

    EXEMEM exemem(clk,ewreg,em2reg,ewmem,ern,aluOut,eqb,
                  mwreg,mm2reg,mwmem,mrn,maluOut,mqb);
    

    DataMemory datamem(maluOut,mqb,mwmem,dmOut);
    

    MEMWB memwb(clk,mwreg,mm2reg,mrn,maluOut,dmOut,
                wwreg,wm2reg,wrn,waluOut,wdmOut);
    

    WBMux wbmux(waluOut, wdmOut, wm2reg, wbMuxOut);
    RegFile regfile(clk,rs,rt,qa,qb,wrn,wbMuxOut);
    
    initial begin
        clk = 0;
    end            
    always begin
        #5 clk = !clk;
    end
endmodule