data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_ctu_2xcmp.v
data/verilator_xmls/48fad519-979d-4828-bb72-fdff605eb46a.xml
module bw_clk_cl_ctu_2xcmp(bw_pll_2x_clk_local ,bw_pll_2xclk );
output		bw_pll_2x_clk_local ;
input		bw_pll_2xclk ;
 
assign  bw_pll_2x_clk_local =  bw_pll_2xclk;

endmodule
module bw_clk_cl_ctu_2xcmp(bw_pll_2x_clk_local ,bw_pll_2xclk );

output		bw_pll_2x_clk_local ;
input		bw_pll_2xclk ;
 
assign  bw_pll_2x_clk_local =  bw_pll_2xclk;

endmodule