data/full_repos/permissive/503137469/verilog/gl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/503137469/verilog/gl/user_project_wrapper.v:57: Cannot find file containing module: 'RISC_SPM'\n RISC_SPM RISC_SPM (.clk(wb_clk_i),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503137469/verilog/gl,data/full_repos/permissive/503137469/RISC_SPM\n             data/full_repos/permissive/503137469/verilog/gl,data/full_repos/permissive/503137469/RISC_SPM.v\n             data/full_repos/permissive/503137469/verilog/gl,data/full_repos/permissive/503137469/RISC_SPM.sv\n             RISC_SPM\n             RISC_SPM.v\n             RISC_SPM.sv\n             obj_dir/RISC_SPM\n             obj_dir/RISC_SPM.v\n             obj_dir/RISC_SPM.sv\n%Error: data/full_repos/permissive/503137469/verilog/gl/user_project_wrapper.v:94: Cannot find file containing module: 'asmd_multiplier'\n asmd_multiplier asmd_multiplier (.clk(la_data_in[32]),\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module user_project_wrapper (user_clock2,
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_cyc_i,
    wbs_stb_i,
    wbs_we_i,
    analog_io,
    io_in,
    io_oeb,
    io_out,
    la_data_in,
    la_data_out,
    la_oenb,
    user_irq,
    wbs_adr_i,
    wbs_dat_i,
    wbs_dat_o,
    wbs_sel_i);
 input user_clock2;
 input vccd1;
 input vccd2;
 input vdda1;
 input vdda2;
 input vssa1;
 input vssa2;
 input vssd1;
 input vssd2;
 input wb_clk_i;
 input wb_rst_i;
 output wbs_ack_o;
 input wbs_cyc_i;
 input wbs_stb_i;
 input wbs_we_i;
 inout [28:0] analog_io;
 input [37:0] io_in;
 output [37:0] io_oeb;
 output [37:0] io_out;
 input [127:0] la_data_in;
 output [127:0] la_data_out;
 input [127:0] la_oenb;
 output [2:0] user_irq;
 input [31:0] wbs_adr_i;
 input [31:0] wbs_dat_i;
 output [31:0] wbs_dat_o;
 input [3:0] wbs_sel_i;


 RISC_SPM RISC_SPM (.clk(wb_clk_i),
    .ext_write(io_in[8]),
    .rst(la_data_in[0]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .address_bus({io_in[24],
    io_in[23],
    io_in[22],
    io_in[21],
    io_in[20],
    io_in[19],
    io_in[18],
    io_in[17]}),
    .data_bus({io_in[16],
    io_in[15],
    io_in[14],
    io_in[13],
    io_in[12],
    io_in[11],
    io_in[10],
    io_in[9]}),
    .io_oeb({io_oeb[32],
    io_oeb[31],
    io_oeb[30],
    io_oeb[29],
    io_oeb[28],
    io_oeb[27],
    io_oeb[26],
    io_oeb[25]}),
    .memory_bus({io_out[32],
    io_out[31],
    io_out[30],
    io_out[29],
    io_out[28],
    io_out[27],
    io_out[26],
    io_out[25]}));
 asmd_multiplier asmd_multiplier (.clk(la_data_in[32]),
    .ready(la_data_out[48]),
    .reset(la_data_in[33]),
    .start(la_data_in[34]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .product({la_data_out[56],
    la_data_out[55],
    la_data_out[54],
    la_data_out[53],
    la_data_out[52],
    la_data_out[51],
    la_data_out[50],
    la_data_out[49]}),
    .word0({la_data_in[42],
    la_data_in[41],
    la_data_in[40],
    la_data_in[39]}),
    .word1({la_data_in[38],
    la_data_in[37],
    la_data_in[36],
    la_data_in[35]}));
endmodule
module user_project_wrapper (user_clock2,
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_cyc_i,
    wbs_stb_i,
    wbs_we_i,
    analog_io,
    io_in,
    io_oeb,
    io_out,
    la_data_in,
    la_data_out,
    la_oenb,
    user_irq,
    wbs_adr_i,
    wbs_dat_i,
    wbs_dat_o,
    wbs_sel_i);

 input user_clock2;
 input vccd1;
 input vccd2;
 input vdda1;
 input vdda2;
 input vssa1;
 input vssa2;
 input vssd1;
 input vssd2;
 input wb_clk_i;
 input wb_rst_i;
 output wbs_ack_o;
 input wbs_cyc_i;
 input wbs_stb_i;
 input wbs_we_i;
 inout [28:0] analog_io;
 input [37:0] io_in;
 output [37:0] io_oeb;
 output [37:0] io_out;
 input [127:0] la_data_in;
 output [127:0] la_data_out;
 input [127:0] la_oenb;
 output [2:0] user_irq;
 input [31:0] wbs_adr_i;
 input [31:0] wbs_dat_i;
 output [31:0] wbs_dat_o;
 input [3:0] wbs_sel_i;


 RISC_SPM RISC_SPM (.clk(wb_clk_i),
    .ext_write(io_in[8]),
    .rst(la_data_in[0]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .address_bus({io_in[24],
    io_in[23],
    io_in[22],
    io_in[21],
    io_in[20],
    io_in[19],
    io_in[18],
    io_in[17]}),
    .data_bus({io_in[16],
    io_in[15],
    io_in[14],
    io_in[13],
    io_in[12],
    io_in[11],
    io_in[10],
    io_in[9]}),
    .io_oeb({io_oeb[32],
    io_oeb[31],
    io_oeb[30],
    io_oeb[29],
    io_oeb[28],
    io_oeb[27],
    io_oeb[26],
    io_oeb[25]}),
    .memory_bus({io_out[32],
    io_out[31],
    io_out[30],
    io_out[29],
    io_out[28],
    io_out[27],
    io_out[26],
    io_out[25]}));
 asmd_multiplier asmd_multiplier (.clk(la_data_in[32]),
    .ready(la_data_out[48]),
    .reset(la_data_in[33]),
    .start(la_data_in[34]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .product({la_data_out[56],
    la_data_out[55],
    la_data_out[54],
    la_data_out[53],
    la_data_out[52],
    la_data_out[51],
    la_data_out[50],
    la_data_out[49]}),
    .word0({la_data_in[42],
    la_data_in[41],
    la_data_in[40],
    la_data_in[39]}),
    .word1({la_data_in[38],
    la_data_in[37],
    la_data_in[36],
    la_data_in[35]}));
endmodule