data/full_repos/permissive/469195529/sources/hdl/transLatch.v
data/verilator_xmls/e1307e49-8fdd-4b46-8e9a-87f89e88095a.xml
module transLatch(
    input D, clk,
    output reg Q
    );
    wire clkIn;
    assign clkIn = ~clk;
    always@(clkIn or D) begin
        if(clkIn) Q <= D;
    end
    
endmodule
module transLatch(
    input D, clk,
    output reg Q
    );

    wire clkIn;
    assign clkIn = ~clk;
    always@(clkIn or D) begin
        if(clkIn) Q <= D;
    end
    
endmodule