data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_ref_model.v
data/verilator_xmls/9c2a1959-96da-4993-9f70-49acefbc34c4.xml
module comp_mult_ref_model #(
parameter DWIDTH  = 8,
parameter VERBOSE = 1
)(

input                           clk               ,
input                           rst_n        ,
input                           sw_rst       ,
                                              

input                           op_val       ,
input                           op_rdy       ,
input   [      2*2*DWIDTH -1:0] op_data      ,
                                              

input                           res_val      ,
input                           res_rdy      ,
input   [2*2*(DWIDTH + 1) -1:0] res_data     ,


output  [2*2*(DWIDTH + 1) -1:0] exp_res_data
); 

reg         [  2*2*DWIDTH -1:0] operands_fifo [64-1:0];
reg         [           6 -1:0] wr_ptr; 
reg         [           6 -1:0] rd_ptr;


wire signed [2*(DWIDTH+1) -1:0] dut_xr;
wire signed [2*(DWIDTH+1) -1:0] dut_yr;
                    
reg signed  [      DWIDTH -1:0] l_x1, l_y1, l_x2, l_y2 ;
reg signed  [2*(DWIDTH+1) -1:0] l_xr;
reg signed  [2*(DWIDTH+1) -1:0] l_yr;

assign dut_xr = res_data[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr = res_data[           0+:2*(DWIDTH+1)];


always @(posedge clk or negedge rst_n)
if(~rst_n) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end else 
if(sw_rst) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end 

always @(posedge clk)
if(op_val & op_rdy) begin 
    operands_fifo[wr_ptr] <= op_data;
    wr_ptr <= wr_ptr + 'd1;
end 

always @(posedge clk)
if(res_val & res_rdy) begin 
    {l_x1, l_y1, l_x2, l_y2} = operands_fifo[rd_ptr];
    l_xr = l_x1 * l_x2 - l_y1 * l_y2;
    l_yr = l_x1 * l_y2 + l_y1 * l_x2;
    rd_ptr <= rd_ptr + 'd1;
    if ((dut_xr !== l_xr) | (dut_yr !== l_yr)) begin
        $display("%M %0t ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr, dut_yr, l_xr,l_yr);     
        $stop;
    end 
    else if(VERBOSE)
        $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), same as expected (%0d + %0di)", $time,
         l_x1, l_y1, l_x2, l_y2, dut_xr, dut_yr, l_xr,l_yr);
end 

assign exp_res_data = {l_xr, l_yr}; 


endmodule
module comp_mult_ref_model #(
parameter DWIDTH  = 8,
parameter VERBOSE = 1
)(

input                           clk               ,
input                           rst_n        ,
input                           sw_rst       ,
                                              

input                           op_val       ,
input                           op_rdy       ,
input   [      2*2*DWIDTH -1:0] op_data      ,
                                              

input                           res_val      ,
input                           res_rdy      ,
input   [2*2*(DWIDTH + 1) -1:0] res_data     ,


output  [2*2*(DWIDTH + 1) -1:0] exp_res_data
);
 

reg         [  2*2*DWIDTH -1:0] operands_fifo [64-1:0];
reg         [           6 -1:0] wr_ptr; 
reg         [           6 -1:0] rd_ptr;


wire signed [2*(DWIDTH+1) -1:0] dut_xr;
wire signed [2*(DWIDTH+1) -1:0] dut_yr;
                    
reg signed  [      DWIDTH -1:0] l_x1, l_y1, l_x2, l_y2 ;
reg signed  [2*(DWIDTH+1) -1:0] l_xr;
reg signed  [2*(DWIDTH+1) -1:0] l_yr;

assign dut_xr = res_data[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr = res_data[           0+:2*(DWIDTH+1)];


always @(posedge clk or negedge rst_n)
if(~rst_n) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end else 
if(sw_rst) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end 

always @(posedge clk)
if(op_val & op_rdy) begin 
    operands_fifo[wr_ptr] <= op_data;
    wr_ptr <= wr_ptr + 'd1;
end 

always @(posedge clk)
if(res_val & res_rdy) begin 
    {l_x1, l_y1, l_x2, l_y2} = operands_fifo[rd_ptr];
    l_xr = l_x1 * l_x2 - l_y1 * l_y2;
    l_yr = l_x1 * l_y2 + l_y1 * l_x2;
    rd_ptr <= rd_ptr + 'd1;
    if ((dut_xr !== l_xr) | (dut_yr !== l_yr)) begin
        $display("%M %0t ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr, dut_yr, l_xr,l_yr);     
        $stop;
    end 
    else if(VERBOSE)
        $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), same as expected (%0d + %0di)", $time,
         l_x1, l_y1, l_x2, l_y2, dut_xr, dut_yr, l_xr,l_yr);
end 

assign exp_res_data = {l_xr, l_yr}; 


endmodule