data/full_repos/permissive/495276914/Read.v
1: b'%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 21 bits.\n                                                              : ... In instance Read\n       imm2 = $signed({ins_dec_in[31],ins_dec_in[19:12],ins_dec_in[20],ins_dec_in[30:21],1\'b0});        \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:65: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 13 bits.\n                                                              : ... In instance Read\n       imm3 = $signed({ins_dec_in[31],ins_dec_in[7],ins_dec_in[30:25],ins_dec_in[11:8],1\'b0});   \n            ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:66: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                              : ... In instance Read\n       imm4 = $signed(ins_dec_in[31:20]);         \n            ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:67: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                              : ... In instance Read\n       imm5 = $signed({ins_dec_in[31:25],ins_dec_in[11:7]});          \n            ^\n%Error: Exiting due to 4 warning(s)\n'
module regf( clk,rst,wen1,br_ctrl,
        rs1,rs2,wr1,
        wval1,
        rso1,rso2);
    
    input clk,rst,wen1,br_ctrl;
    input[4:0] rs1,rs2,wr1;
    input[31:0] wval1;
    output reg[31:0] rso1,rso2;
    
    reg[31:0] mem[0:31]; 
    integer i;
    
    always@(posedge clk)begin
        if(rst==1)begin
            for (i = 0; i < 32; i = i + 1)
                mem[i] <= 0;
    
        end
        



        
        else begin
            if(wen1==1)begin 
                mem[wr1] <= wr1==0? 0: wval1;
            end
            else begin
                mem[0] <= 0;
            end
        end
    end
   
    always@(negedge clk)begin
        if(rst==1)begin
            rso1<=0;
            rso2<=0;
        end
        else begin
            rso1<=mem[rs1];
            rso2<=mem[rs2];        
        end
    end
endmodule
module regf( clk,rst,wen1,br_ctrl,
        rs1,rs2,wr1,
        wval1,
        rso1,rso2);

    
    input clk,rst,wen1,br_ctrl;
    input[4:0] rs1,rs2,wr1;
    input[31:0] wval1;
    output reg[31:0] rso1,rso2;
    
    reg[31:0] mem[0:31]; 
    integer i;
    
    always@(posedge clk)begin
        if(rst==1)begin
            for (i = 0; i < 32; i = i + 1)
                mem[i] <= 0;
    
        end
        



        
        else begin
            if(wen1==1)begin 
                mem[wr1] <= wr1==0? 0: wval1;
            end
            else begin
                mem[0] <= 0;
            end
        end
    end
   
    always@(negedge clk)begin
        if(rst==1)begin
            rso1<=0;
            rso2<=0;
        end
        else begin
            rso1<=mem[rs1];
            rso2<=mem[rs2];        
        end
    end
endmodule