data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v
1: b'%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:21: Cannot find include file: svo_defines.vh\n`include "svo_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh.v\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh.sv\n             svo_defines.vh\n             svo_defines.vh.v\n             svo_defines.vh.sv\n             obj_dir/svo_defines.vh\n             obj_dir/svo_defines.vh.v\n             obj_dir/svo_defines.vh.sv\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:24: Define or directive not defined: \'`SVO_DEFAULT_PARAMS\'\n `SVO_DEFAULT_PARAMS,\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:24: syntax error, unexpected \',\', expecting \'[\'\n `SVO_DEFAULT_PARAMS,\n                    ^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:26: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter MEM_DATA_WIDTH = 64,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:27: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter MEM_BURST_LEN = 8,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:28: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter FIFO_DEPTH = 64\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:29: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:48: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_awvalid,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:57: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_bready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:64: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_rready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:69: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [MEM_ADDR_WIDTH-1:0] mem_axi_araddr,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:70: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output     [               7:0] mem_axi_arlen,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:75: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input                           mem_axi_arready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:84: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output                          out_axis_tvalid,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:93: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input            term_axis_tready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:96: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:97: Define or directive not defined: \'`SVO_DECLS\'\n `SVO_DECLS\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:121: syntax error, unexpected always\n always @(posedge oclk)\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:137: syntax error, unexpected assign\n assign reg_resolution[31:16] = SVO_VER_PIXELS, reg_resolution[15:0] = SVO_HOR_PIXELS;\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:190: syntax error, unexpected assign\n assign mem_axi_arlen = MEM_BURST_LEN-1;\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:251: syntax error, unexpected IDENTIFIER\n svo_vdma_crossclock_fifo #(\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:304: syntax error, unexpected always\n always @(posedge oclk) begin\n ^~~~~~\n%Error: Exiting due to 22 error(s)\n'
module svo_vdma #(
	`SVO_DEFAULT_PARAMS,
	parameter MEM_ADDR_WIDTH = 32,
	parameter MEM_DATA_WIDTH = 64,
	parameter MEM_BURST_LEN = 8,
	parameter FIFO_DEPTH = 64
) (


	input clk, oclk, resetn,
	output reg frame_irq,














	input             cfg_axi_awvalid,
	output            cfg_axi_awready,
	input      [ 7:0] cfg_axi_awaddr,

	input             cfg_axi_wvalid,
	output            cfg_axi_wready,
	input      [31:0] cfg_axi_wdata,

	output reg        cfg_axi_bvalid,
	input             cfg_axi_bready,

	input             cfg_axi_arvalid,
	output            cfg_axi_arready,
	input      [ 7:0] cfg_axi_araddr,

	output reg        cfg_axi_rvalid,
	input             cfg_axi_rready,
	output reg [31:0] cfg_axi_rdata,



	output reg [MEM_ADDR_WIDTH-1:0] mem_axi_araddr,
	output     [               7:0] mem_axi_arlen,
	output     [               2:0] mem_axi_arsize,
	output     [               2:0] mem_axi_arprot,
	output     [               1:0] mem_axi_arburst,
	output reg                      mem_axi_arvalid,
	input                           mem_axi_arready,

	input      [MEM_DATA_WIDTH-1:0] mem_axi_rdata,
	input                           mem_axi_rvalid,
	output reg                      mem_axi_rready,




	output                          out_axis_tvalid,
	input                           out_axis_tready,
	output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
	output [                   0:0] out_axis_tuser,




	output reg       term_axis_tvalid,
	input            term_axis_tready,
	output reg [7:0] term_axis_tdata

);
	`SVO_DECLS

	localparam BYTES_PER_PIXEL = (SVO_BITS_PER_PIXEL + 7) / 8;
	localparam BYTES_PER_BURST = MEM_BURST_LEN * MEM_DATA_WIDTH / 8;

	localparam NUM_PIXELS = SVO_HOR_PIXELS * SVO_VER_PIXELS;
	localparam NUM_PIXELS_WIDTH = svo_clog2(NUM_PIXELS);
	
	localparam NUM_BURSTS = (NUM_PIXELS * BYTES_PER_PIXEL + BYTES_PER_BURST - 1) / BYTES_PER_BURST;
	localparam NUM_BURSTS_WIDTH = svo_clog2(NUM_BURSTS);
	
	localparam NUM_WORDS = MEM_BURST_LEN * NUM_BURSTS;
	localparam NUM_WORDS_WIDTH = svo_clog2(NUM_WORDS);

	localparam FIFO_ABITS = svo_clog2(FIFO_DEPTH);





	reg [3:0] oresetn_q, iresetn_q;
	reg oresetn, iresetn;


	always @(posedge oclk)
		{oresetn, oresetn_q} <= {oresetn_q, resetn};


	always @(posedge clk)
		{iresetn, iresetn_q} <= {iresetn_q, oresetn};






	reg [31:0] reg_startaddr;
	reg [31:0] reg_activeframe;
	wire [31:0] reg_resolution;

	assign reg_resolution[31:16] = SVO_VER_PIXELS, reg_resolution[15:0] = SVO_HOR_PIXELS;

	assign {cfg_axi_awready, cfg_axi_wready} = {2{resetn && cfg_axi_awvalid && cfg_axi_wvalid && (!cfg_axi_bvalid || cfg_axi_bready) && !term_axis_tvalid}};
	assign cfg_axi_arready = resetn && cfg_axi_arvalid && (!cfg_axi_rvalid || cfg_axi_rready);

	always @(posedge clk) begin
		if (!resetn) begin
			reg_startaddr <= 0;
			cfg_axi_bvalid <= 0;
			cfg_axi_rvalid <= 0;
			term_axis_tvalid <= 0;
		end else begin
			if (cfg_axi_bready)
				cfg_axi_bvalid <= 0;

			if (cfg_axi_rready)
				cfg_axi_rvalid <= 0;

			if (term_axis_tready)
				term_axis_tvalid <= 0;

			if (cfg_axi_awready) begin
				cfg_axi_bvalid <= 1;
				case (cfg_axi_awaddr)
					8'h00: reg_startaddr <= cfg_axi_wdata;
					8'h0C: begin
						term_axis_tvalid <= 1;
						term_axis_tdata <= cfg_axi_wdata;
					end
				endcase
			end

			if (cfg_axi_arready) begin
				cfg_axi_rvalid <= 1;
				case (cfg_axi_araddr)
					8'h00: cfg_axi_rdata <= reg_startaddr;
					8'h04: cfg_axi_rdata <= reg_activeframe;
					8'h08: cfg_axi_rdata <= reg_resolution;
					default: cfg_axi_rdata <= 'bx;
				endcase
			end
		end
	end






	reg [NUM_BURSTS_WIDTH-1:0] ar_burst_count;
	reg [3:0] ar_burst_delay;
	reg ar_flow_ctrl;

	assign mem_axi_arlen = MEM_BURST_LEN-1;
	assign mem_axi_arsize = svo_clog2(MEM_DATA_WIDTH/8);
	assign mem_axi_arprot = 0;
	assign mem_axi_arburst = 1;

	always @(posedge clk) begin
		frame_irq <= 0;
		if (ar_burst_delay)
			ar_burst_delay <= ar_burst_delay-1;
		if (!iresetn || !resetn) begin
			ar_burst_delay <= 0;
			ar_burst_count <= 0;
			mem_axi_araddr <= 0;
			mem_axi_arvalid <= 0;
			reg_activeframe <= 0;
		end else begin
			if (mem_axi_araddr == 0) begin
				mem_axi_araddr <= reg_startaddr;
				reg_activeframe <= reg_startaddr;
			end else
			if (mem_axi_arready && mem_axi_arvalid) begin
				mem_axi_arvalid <= 0;
				ar_burst_delay <= 6;
			end else
			if (ar_flow_ctrl && !mem_axi_arvalid && !ar_burst_delay) begin
				mem_axi_arvalid <= 1;

				if (ar_burst_count == NUM_BURSTS-1)
					ar_burst_count <= 0;
				else
					ar_burst_count <= ar_burst_count + 1;

				if (ar_burst_count == 0) begin
					mem_axi_araddr <= reg_startaddr;
					reg_activeframe <= reg_startaddr;
					if (!reg_startaddr) begin
						ar_burst_count <= 0;
						mem_axi_arvalid <= 0;
					end else
						frame_irq <= 1;
				end else begin
					mem_axi_araddr <= mem_axi_araddr + (MEM_BURST_LEN*MEM_DATA_WIDTH/8);
				end
			end
		end
	end






	reg [NUM_WORDS_WIDTH-1:0] r_word_count;
	reg [FIFO_ABITS:0] requested_words;

	reg fifo_out_en;
	wire fifo_out_first_word;
	wire [MEM_DATA_WIDTH-1:0] fifo_out_data;
	wire [FIFO_ABITS-1:0] fifo_in_free;
	wire [FIFO_ABITS-1:0] fifo_out_avail;

	svo_vdma_crossclock_fifo #(
		.WIDTH(MEM_DATA_WIDTH+1),
		.DEPTH(FIFO_DEPTH),
		.ABITS(FIFO_ABITS)
	) fifo (
		.in_clk(clk),
		.in_resetn(resetn),
		.in_enable(mem_axi_rvalid && mem_axi_rready),
		.in_data({r_word_count == 0, mem_axi_rdata}),
		.in_free(fifo_in_free),

		.out_clk(oclk),
		.out_resetn(oresetn),
		.out_enable(fifo_out_en),
		.out_data({fifo_out_first_word, fifo_out_data}),
		.out_avail(fifo_out_avail)
	);

	always @(posedge clk) begin
		if (!resetn) begin
			requested_words = 0;
			mem_axi_rready <= 0;
			r_word_count <= 0;
			ar_flow_ctrl <= 0;
		end else begin
			if (mem_axi_arvalid && mem_axi_arready) begin
				requested_words = requested_words + MEM_BURST_LEN;
			end
			if (mem_axi_rvalid && mem_axi_rready) begin
				requested_words = requested_words - 1;
				r_word_count <= r_word_count == NUM_WORDS-1 ? 0 : r_word_count + 1;
			end

			ar_flow_ctrl <= requested_words + MEM_BURST_LEN + 4 < fifo_in_free;
			mem_axi_rready <= fifo_in_free > 4;
		end
	end






	reg [MEM_DATA_WIDTH + 8*BYTES_PER_PIXEL - 9 : 0] outbuf;
	reg [7:0] outbuf_bytes;
	reg outbuf_framestart;

	wire pixel_rd;
	reg [NUM_PIXELS_WIDTH:0] pixel_count;
	reg [SVO_BITS_PER_PIXEL-1:0] pixel_data;

	integer i;

	always @(posedge oclk) begin
		fifo_out_en <= 0;
		if (!oresetn) begin
			outbuf_bytes = 0;
			pixel_count <= NUM_PIXELS;
		end else begin
			outbuf = outbuf;
			outbuf_bytes = outbuf_bytes;

			if (fifo_out_avail && outbuf_bytes < BYTES_PER_PIXEL && (!fifo_out_first_word || pixel_count >= NUM_PIXELS-1)) begin
				for (i = 0; i < BYTES_PER_PIXEL; i = i+1)
					if (outbuf_bytes == i || (!i && fifo_out_first_word)) begin
						outbuf = (fifo_out_data << (8*i)) | (outbuf & ~(~0 << (8*i)));
						outbuf_bytes = MEM_DATA_WIDTH/8 + i;
						fifo_out_en <= 1;
					end
				outbuf_framestart = fifo_out_first_word;
			end

			if (pixel_rd) begin
				pixel_data <= outbuf;
				if (outbuf_framestart || pixel_count > ((NUM_WORDS*(MEM_DATA_WIDTH/8) + BYTES_PER_PIXEL - 1) / BYTES_PER_PIXEL)) begin
					pixel_count <= 0;
				end else
					pixel_count <= pixel_count + 1;
				outbuf_bytes = outbuf_bytes < BYTES_PER_PIXEL ?
						0 : outbuf_bytes - BYTES_PER_PIXEL;
				outbuf = outbuf >> (8*BYTES_PER_PIXEL);
				outbuf_framestart = 0;
			end
		end
	end

	assign pixel_rd = out_axis_tready;
	assign out_axis_tvalid = pixel_count < NUM_PIXELS;
	assign out_axis_tdata = pixel_data;
	assign out_axis_tuser = !pixel_count;
endmodule
module svo_vdma #(
	`SVO_DEFAULT_PARAMS,
	parameter MEM_ADDR_WIDTH = 32,
	parameter MEM_DATA_WIDTH = 64,
	parameter MEM_BURST_LEN = 8,
	parameter FIFO_DEPTH = 64
) (


	input clk, oclk, resetn,
	output reg frame_irq,














	input             cfg_axi_awvalid,
	output            cfg_axi_awready,
	input      [ 7:0] cfg_axi_awaddr,

	input             cfg_axi_wvalid,
	output            cfg_axi_wready,
	input      [31:0] cfg_axi_wdata,

	output reg        cfg_axi_bvalid,
	input             cfg_axi_bready,

	input             cfg_axi_arvalid,
	output            cfg_axi_arready,
	input      [ 7:0] cfg_axi_araddr,

	output reg        cfg_axi_rvalid,
	input             cfg_axi_rready,
	output reg [31:0] cfg_axi_rdata,



	output reg [MEM_ADDR_WIDTH-1:0] mem_axi_araddr,
	output     [               7:0] mem_axi_arlen,
	output     [               2:0] mem_axi_arsize,
	output     [               2:0] mem_axi_arprot,
	output     [               1:0] mem_axi_arburst,
	output reg                      mem_axi_arvalid,
	input                           mem_axi_arready,

	input      [MEM_DATA_WIDTH-1:0] mem_axi_rdata,
	input                           mem_axi_rvalid,
	output reg                      mem_axi_rready,




	output                          out_axis_tvalid,
	input                           out_axis_tready,
	output [SVO_BITS_PER_PIXEL-1:0] out_axis_tdata,
	output [                   0:0] out_axis_tuser,




	output reg       term_axis_tvalid,
	input            term_axis_tready,
	output reg [7:0] term_axis_tdata

);

	`SVO_DECLS

	localparam BYTES_PER_PIXEL = (SVO_BITS_PER_PIXEL + 7) / 8;
	localparam BYTES_PER_BURST = MEM_BURST_LEN * MEM_DATA_WIDTH / 8;

	localparam NUM_PIXELS = SVO_HOR_PIXELS * SVO_VER_PIXELS;
	localparam NUM_PIXELS_WIDTH = svo_clog2(NUM_PIXELS);
	
	localparam NUM_BURSTS = (NUM_PIXELS * BYTES_PER_PIXEL + BYTES_PER_BURST - 1) / BYTES_PER_BURST;
	localparam NUM_BURSTS_WIDTH = svo_clog2(NUM_BURSTS);
	
	localparam NUM_WORDS = MEM_BURST_LEN * NUM_BURSTS;
	localparam NUM_WORDS_WIDTH = svo_clog2(NUM_WORDS);

	localparam FIFO_ABITS = svo_clog2(FIFO_DEPTH);





	reg [3:0] oresetn_q, iresetn_q;
	reg oresetn, iresetn;


	always @(posedge oclk)
		{oresetn, oresetn_q} <= {oresetn_q, resetn};


	always @(posedge clk)
		{iresetn, iresetn_q} <= {iresetn_q, oresetn};






	reg [31:0] reg_startaddr;
	reg [31:0] reg_activeframe;
	wire [31:0] reg_resolution;

	assign reg_resolution[31:16] = SVO_VER_PIXELS, reg_resolution[15:0] = SVO_HOR_PIXELS;

	assign {cfg_axi_awready, cfg_axi_wready} = {2{resetn && cfg_axi_awvalid && cfg_axi_wvalid && (!cfg_axi_bvalid || cfg_axi_bready) && !term_axis_tvalid}};
	assign cfg_axi_arready = resetn && cfg_axi_arvalid && (!cfg_axi_rvalid || cfg_axi_rready);

	always @(posedge clk) begin
		if (!resetn) begin
			reg_startaddr <= 0;
			cfg_axi_bvalid <= 0;
			cfg_axi_rvalid <= 0;
			term_axis_tvalid <= 0;
		end else begin
			if (cfg_axi_bready)
				cfg_axi_bvalid <= 0;

			if (cfg_axi_rready)
				cfg_axi_rvalid <= 0;

			if (term_axis_tready)
				term_axis_tvalid <= 0;

			if (cfg_axi_awready) begin
				cfg_axi_bvalid <= 1;
				case (cfg_axi_awaddr)
					8'h00: reg_startaddr <= cfg_axi_wdata;
					8'h0C: begin
						term_axis_tvalid <= 1;
						term_axis_tdata <= cfg_axi_wdata;
					end
				endcase
			end

			if (cfg_axi_arready) begin
				cfg_axi_rvalid <= 1;
				case (cfg_axi_araddr)
					8'h00: cfg_axi_rdata <= reg_startaddr;
					8'h04: cfg_axi_rdata <= reg_activeframe;
					8'h08: cfg_axi_rdata <= reg_resolution;
					default: cfg_axi_rdata <= 'bx;
				endcase
			end
		end
	end






	reg [NUM_BURSTS_WIDTH-1:0] ar_burst_count;
	reg [3:0] ar_burst_delay;
	reg ar_flow_ctrl;

	assign mem_axi_arlen = MEM_BURST_LEN-1;
	assign mem_axi_arsize = svo_clog2(MEM_DATA_WIDTH/8);
	assign mem_axi_arprot = 0;
	assign mem_axi_arburst = 1;

	always @(posedge clk) begin
		frame_irq <= 0;
		if (ar_burst_delay)
			ar_burst_delay <= ar_burst_delay-1;
		if (!iresetn || !resetn) begin
			ar_burst_delay <= 0;
			ar_burst_count <= 0;
			mem_axi_araddr <= 0;
			mem_axi_arvalid <= 0;
			reg_activeframe <= 0;
		end else begin
			if (mem_axi_araddr == 0) begin
				mem_axi_araddr <= reg_startaddr;
				reg_activeframe <= reg_startaddr;
			end else
			if (mem_axi_arready && mem_axi_arvalid) begin
				mem_axi_arvalid <= 0;
				ar_burst_delay <= 6;
			end else
			if (ar_flow_ctrl && !mem_axi_arvalid && !ar_burst_delay) begin
				mem_axi_arvalid <= 1;

				if (ar_burst_count == NUM_BURSTS-1)
					ar_burst_count <= 0;
				else
					ar_burst_count <= ar_burst_count + 1;

				if (ar_burst_count == 0) begin
					mem_axi_araddr <= reg_startaddr;
					reg_activeframe <= reg_startaddr;
					if (!reg_startaddr) begin
						ar_burst_count <= 0;
						mem_axi_arvalid <= 0;
					end else
						frame_irq <= 1;
				end else begin
					mem_axi_araddr <= mem_axi_araddr + (MEM_BURST_LEN*MEM_DATA_WIDTH/8);
				end
			end
		end
	end






	reg [NUM_WORDS_WIDTH-1:0] r_word_count;
	reg [FIFO_ABITS:0] requested_words;

	reg fifo_out_en;
	wire fifo_out_first_word;
	wire [MEM_DATA_WIDTH-1:0] fifo_out_data;
	wire [FIFO_ABITS-1:0] fifo_in_free;
	wire [FIFO_ABITS-1:0] fifo_out_avail;

	svo_vdma_crossclock_fifo #(
		.WIDTH(MEM_DATA_WIDTH+1),
		.DEPTH(FIFO_DEPTH),
		.ABITS(FIFO_ABITS)
	) fifo (
		.in_clk(clk),
		.in_resetn(resetn),
		.in_enable(mem_axi_rvalid && mem_axi_rready),
		.in_data({r_word_count == 0, mem_axi_rdata}),
		.in_free(fifo_in_free),

		.out_clk(oclk),
		.out_resetn(oresetn),
		.out_enable(fifo_out_en),
		.out_data({fifo_out_first_word, fifo_out_data}),
		.out_avail(fifo_out_avail)
	);

	always @(posedge clk) begin
		if (!resetn) begin
			requested_words = 0;
			mem_axi_rready <= 0;
			r_word_count <= 0;
			ar_flow_ctrl <= 0;
		end else begin
			if (mem_axi_arvalid && mem_axi_arready) begin
				requested_words = requested_words + MEM_BURST_LEN;
			end
			if (mem_axi_rvalid && mem_axi_rready) begin
				requested_words = requested_words - 1;
				r_word_count <= r_word_count == NUM_WORDS-1 ? 0 : r_word_count + 1;
			end

			ar_flow_ctrl <= requested_words + MEM_BURST_LEN + 4 < fifo_in_free;
			mem_axi_rready <= fifo_in_free > 4;
		end
	end






	reg [MEM_DATA_WIDTH + 8*BYTES_PER_PIXEL - 9 : 0] outbuf;
	reg [7:0] outbuf_bytes;
	reg outbuf_framestart;

	wire pixel_rd;
	reg [NUM_PIXELS_WIDTH:0] pixel_count;
	reg [SVO_BITS_PER_PIXEL-1:0] pixel_data;

	integer i;

	always @(posedge oclk) begin
		fifo_out_en <= 0;
		if (!oresetn) begin
			outbuf_bytes = 0;
			pixel_count <= NUM_PIXELS;
		end else begin
			outbuf = outbuf;
			outbuf_bytes = outbuf_bytes;

			if (fifo_out_avail && outbuf_bytes < BYTES_PER_PIXEL && (!fifo_out_first_word || pixel_count >= NUM_PIXELS-1)) begin
				for (i = 0; i < BYTES_PER_PIXEL; i = i+1)
					if (outbuf_bytes == i || (!i && fifo_out_first_word)) begin
						outbuf = (fifo_out_data << (8*i)) | (outbuf & ~(~0 << (8*i)));
						outbuf_bytes = MEM_DATA_WIDTH/8 + i;
						fifo_out_en <= 1;
					end
				outbuf_framestart = fifo_out_first_word;
			end

			if (pixel_rd) begin
				pixel_data <= outbuf;
				if (outbuf_framestart || pixel_count > ((NUM_WORDS*(MEM_DATA_WIDTH/8) + BYTES_PER_PIXEL - 1) / BYTES_PER_PIXEL)) begin
					pixel_count <= 0;
				end else
					pixel_count <= pixel_count + 1;
				outbuf_bytes = outbuf_bytes < BYTES_PER_PIXEL ?
						0 : outbuf_bytes - BYTES_PER_PIXEL;
				outbuf = outbuf >> (8*BYTES_PER_PIXEL);
				outbuf_framestart = 0;
			end
		end
	end

	assign pixel_rd = out_axis_tready;
	assign out_axis_tvalid = pixel_count < NUM_PIXELS;
	assign out_axis_tdata = pixel_data;
	assign out_axis_tuser = !pixel_count;
endmodule