data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/Counter.v
data/verilator_xmls/50ea4bb4-f7c5-4039-82d2-5954c769c5f2.xml
module Counter #(parameter N=20)(
    output reg [N-1:0] counter,
    input nreset,
    input clk
);
    initial counter = 0;
    
    always @(posedge clk or negedge nreset)
    begin
        if(!nreset) counter <= 0;
        else counter <= counter + 1;
    end
endmodule
module Counter #(parameter N=20)(
    output reg [N-1:0] counter,
    input nreset,
    input clk
);

    initial counter = 0;
    
    always @(posedge clk or negedge nreset)
    begin
        if(!nreset) counter <= 0;
        else counter <= counter + 1;
    end
endmodule