data/full_repos/permissive/513628330/Gateware/sim_snd/tb_sndgen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/513628330/Gateware/sim_snd/tb_sndgen.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513628330/Gateware/sim_snd/tb_sndgen.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20.8333 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/513628330/Gateware/sim_snd/tb_sndgen.v:48: Cannot find file containing module: \'sndgen\'\n sndgen uut(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513628330/Gateware/sim_snd,data/full_repos/permissive/513628330/sndgen\n             data/full_repos/permissive/513628330/Gateware/sim_snd,data/full_repos/permissive/513628330/sndgen.v\n             data/full_repos/permissive/513628330/Gateware/sim_snd,data/full_repos/permissive/513628330/sndgen.sv\n             sndgen\n             sndgen.v\n             sndgen.sv\n             obj_dir/sndgen\n             obj_dir/sndgen.v\n             obj_dir/sndgen.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sndgen;
	reg clk;
	reg reset;
	reg snd_sel;
	reg [3:0] we;
	reg [7:0] addr;
	reg [31:0] din;
	wire [1:0] pdm;
	
	initial
	begin
`ifdef icarus
  		$dumpfile("tb_sndgen.vcd");
		$dumpvars;
`endif
		

		clk = 1'b1;
		reset = 1'b1;
		snd_sel = 1'b0;
		we = 4'b0000;
		addr = 8'h00;
		din = 32'd0;
	

		#100
		reset = 1'b0;
		
`ifdef icarus

		#10000000 $finish;
`endif		
	end
	

	always
		#20.8333 clk = ~clk;


	sndgen uut(
		.clk(clk),
		.reset(reset),
		.cs(snd_sel),
		.we(we),
		.addr(addr),
		.din(din),
		.pdm(pdm)
	);
endmodule
module tb_sndgen;

	reg clk;
	reg reset;
	reg snd_sel;
	reg [3:0] we;
	reg [7:0] addr;
	reg [31:0] din;
	wire [1:0] pdm;
	
	initial
	begin
`ifdef icarus
  		$dumpfile("tb_sndgen.vcd");
		$dumpvars;
`endif
		

		clk = 1'b1;
		reset = 1'b1;
		snd_sel = 1'b0;
		we = 4'b0000;
		addr = 8'h00;
		din = 32'd0;
	

		#100
		reset = 1'b0;
		
`ifdef icarus

		#10000000 $finish;
`endif		
	end
	

	always
		#20.8333 clk = ~clk;


	sndgen uut(
		.clk(clk),
		.reset(reset),
		.cs(snd_sel),
		.we(we),
		.addr(addr),
		.din(din),
		.pdm(pdm)
	);
endmodule