data/full_repos/permissive/492140037/CPU/仿真文件/MemOrIO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 addr_in = 32\'hffff_fc60;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 addr_in = 32\'h0000_0004; {mRead,mWrite,ioRead,ioWrite}= 4\'b10_00;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 addr_in = 32\'hffff_fc70; {mRead,mWrite,ioRead,ioWrite}= 4\'b00_10;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:10: Cannot find file containing module: \'MemOrIO\'\nMemOrIO umio(.mRead(mRead),\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/MemOrIO\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/MemOrIO.v\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/MemOrIO.sv\n             MemOrIO\n             MemOrIO.v\n             MemOrIO.sv\n             obj_dir/MemOrIO\n             obj_dir/MemOrIO.v\n             obj_dir/MemOrIO.sv\n%Warning-WIDTH: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/MemOrIO_tb.v:27: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hffff\' generates 32 bits.\n                                                                                     : ... In instance MemOrIO_tb\n    io_rdata = 32\'hffff;\n             ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MemOrIO_tb();
reg mRead,mWrite,ioRead,ioWrite;
reg[31:0] addr_in,m_rdata,r_rdata;
reg[15:0] io_rdata;
wire LEDCtrl,SwitchCtrl;
wire [31:0] addr_out,r_wdata,write_data;

MemOrIO umio(.mRead(mRead),
             .mWrite(mWrite),
             .ioRead(ioRead),
             .ioWrite(ioWrite),
             .addr_in(addr_in),
             .addr_out(addr_out),
             .m_rdata(m_rdata),
             .io_rdata(io_rdata),
             .r_wdata(r_wdata),
             .r_rdata(r_rdata),
             .write_data(write_data),
             .LEDCtrl(LEDCtrl),
             .SwitchCtrl(SwitchCtrl)
             );

initial begin
    m_rdata = 32'hffff_0001;
    io_rdata = 32'hffff;
    r_rdata = 32'h0f0f_0f0f;
    addr_in = 32'h4;
    {mRead,mWrite,ioRead,ioWrite}=4'b01_00;
    #10 addr_in = 32'hffff_fc60;
    {mRead,mWrite,ioRead,ioWrite}= 4'b00_01;
    #10 addr_in = 32'h0000_0004; {mRead,mWrite,ioRead,ioWrite}= 4'b10_00;
    #10 addr_in = 32'hffff_fc70; {mRead,mWrite,ioRead,ioWrite}= 4'b00_10;
    #10 $finish;
end

endmodule
module MemOrIO_tb();

reg mRead,mWrite,ioRead,ioWrite;
reg[31:0] addr_in,m_rdata,r_rdata;
reg[15:0] io_rdata;
wire LEDCtrl,SwitchCtrl;
wire [31:0] addr_out,r_wdata,write_data;

MemOrIO umio(.mRead(mRead),
             .mWrite(mWrite),
             .ioRead(ioRead),
             .ioWrite(ioWrite),
             .addr_in(addr_in),
             .addr_out(addr_out),
             .m_rdata(m_rdata),
             .io_rdata(io_rdata),
             .r_wdata(r_wdata),
             .r_rdata(r_rdata),
             .write_data(write_data),
             .LEDCtrl(LEDCtrl),
             .SwitchCtrl(SwitchCtrl)
             );

initial begin
    m_rdata = 32'hffff_0001;
    io_rdata = 32'hffff;
    r_rdata = 32'h0f0f_0f0f;
    addr_in = 32'h4;
    {mRead,mWrite,ioRead,ioWrite}=4'b01_00;
    #10 addr_in = 32'hffff_fc60;
    {mRead,mWrite,ioRead,ioWrite}= 4'b00_01;
    #10 addr_in = 32'h0000_0004; {mRead,mWrite,ioRead,ioWrite}= 4'b10_00;
    #10 addr_in = 32'hffff_fc70; {mRead,mWrite,ioRead,ioWrite}= 4'b00_10;
    #10 $finish;
end

endmodule