data/full_repos/permissive/41946869/src/robo.v
data/verilator_xmls/37ed37f8-242e-4587-91dd-39a7a3a2842a.xml
module robo (
    clk,
    led0, led1, led2, led3, led4, led5, led6, led7,
    servo0, servo1, servo2, servo3
);

input clk;
output reg led0;
output reg led1;
output reg led2;
output reg led3;
output reg led4;
output reg led5;
output reg led6;
output reg led7;

output reg servo0;
output reg servo1;
output reg servo2;
output reg servo3;






reg [31:0] run;

always @(posedge clk)
    run <= run + 32'b1;



reg [63:0] mem [0:255];
reg [63:0] data;
reg [7:0] ptr;

initial begin
    $readmemh("ram.txt", mem);
end

always @*
    data = mem[ptr];



reg [31:0] tf;
reg tf_reset;
reg tf_en;

always @*
    tf_reset = (tf === 32'd600);

always @*
    tf_en = &run[10:0];

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            tf <= 32'b0;
        end else begin
            tf <= tf + 32'b1;
        end
    end


always @(posedge clk)
    if (tf_en & tf_reset)
        ptr <= ptr + 1;


reg [15:0] t0;
reg t0_valid;

always @*
    t0_valid = |t0;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t0 <= data[15:0];
        end else begin
            if (t0_valid) begin
                t0 <= t0 - 16'b1;
            end
        end
    end


reg [15:0] t1;
reg t1_valid;

always @*
    t1_valid = |t1;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t1 <= data[31:16];
        end else begin
            if (t1_valid) begin
                t1 <= t1 - 16'b1;
            end
        end
    end


reg [15:0] t2;
reg t2_valid;

always @*
    t2_valid = |t2;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t2 <= data[47:32];
        end else begin
            if (t2_valid) begin
                t2 <= t2 - 16'b1;
            end
        end
    end


reg [15:0] t3;
reg t3_valid;

always @*
    t3_valid = |t3;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t3 <= data[63:48];
        end else begin
            if (t3_valid) begin
                t3 <= t3 - 16'b1;
            end
        end
    end

always @* begin
    servo0 = t0_valid;
    servo1 = t1_valid;
    servo2 = t2_valid;
    servo3 = t3_valid;
    led0 = run[24];
    led1 = run[25];
    led2 = run[26];
    led3 = run[27];
    led4 = run[28];
    led5 = run[29];
    led6 = run[30];
    led7 = run[31];
end

endmodule
module robo (
    clk,
    led0, led1, led2, led3, led4, led5, led6, led7,
    servo0, servo1, servo2, servo3
);


input clk;
output reg led0;
output reg led1;
output reg led2;
output reg led3;
output reg led4;
output reg led5;
output reg led6;
output reg led7;

output reg servo0;
output reg servo1;
output reg servo2;
output reg servo3;






reg [31:0] run;

always @(posedge clk)
    run <= run + 32'b1;



reg [63:0] mem [0:255];
reg [63:0] data;
reg [7:0] ptr;

initial begin
    $readmemh("ram.txt", mem);
end

always @*
    data = mem[ptr];



reg [31:0] tf;
reg tf_reset;
reg tf_en;

always @*
    tf_reset = (tf === 32'd600);

always @*
    tf_en = &run[10:0];

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            tf <= 32'b0;
        end else begin
            tf <= tf + 32'b1;
        end
    end


always @(posedge clk)
    if (tf_en & tf_reset)
        ptr <= ptr + 1;


reg [15:0] t0;
reg t0_valid;

always @*
    t0_valid = |t0;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t0 <= data[15:0];
        end else begin
            if (t0_valid) begin
                t0 <= t0 - 16'b1;
            end
        end
    end


reg [15:0] t1;
reg t1_valid;

always @*
    t1_valid = |t1;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t1 <= data[31:16];
        end else begin
            if (t1_valid) begin
                t1 <= t1 - 16'b1;
            end
        end
    end


reg [15:0] t2;
reg t2_valid;

always @*
    t2_valid = |t2;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t2 <= data[47:32];
        end else begin
            if (t2_valid) begin
                t2 <= t2 - 16'b1;
            end
        end
    end


reg [15:0] t3;
reg t3_valid;

always @*
    t3_valid = |t3;

always @(posedge clk)
    if (tf_en) begin
        if (tf_reset) begin
            t3 <= data[63:48];
        end else begin
            if (t3_valid) begin
                t3 <= t3 - 16'b1;
            end
        end
    end

always @* begin
    servo0 = t0_valid;
    servo1 = t1_valid;
    servo2 = t2_valid;
    servo3 = t3_valid;
    led0 = run[24];
    led1 = run[25];
    led2 = run[26];
    led3 = run[27];
    led4 = run[28];
    led5 = run[29];
    led6 = run[30];
    led7 = run[31];
end

endmodule