data/full_repos/permissive/449071180/or_8bit.v
data/verilator_xmls/f92d4f38-6940-4807-ab09-08ae0e8c4385.xml
module or_8bit(in1,in2,in3,in4,out);

input [7:0] in1,in2,in3,in4;

reg [7:0] hold;

output reg out;


always@(in1,in2,in3,in4) begin

hold = in1|in2|in3|in4;

out = hold[7:7]|hold[6:6]|hold[5:5]|hold[4:4]|hold[3:3]|hold[2:2]|hold[1:1]|hold[0:0];

end


endmodule
module or_8bit(in1,in2,in3,in4,out);


input [7:0] in1,in2,in3,in4;

reg [7:0] hold;

output reg out;


always@(in1,in2,in3,in4) begin

hold = in1|in2|in3|in4;

out = hold[7:7]|hold[6:6]|hold[5:5]|hold[4:4]|hold[3:3]|hold[2:2]|hold[1:1]|hold[0:0];

end


endmodule