data/full_repos/permissive/434840709/lab2/mux/mux1.v
data/verilator_xmls/01a4c54f-f6dc-4a37-b49a-60ac606e32a9.xml
module mux1 (
    input wire [1:0] d,
    input wire a,
    output wire y
);

    
    assign y = a == 1'b0 ? d[0]:d[1];

endmodule
module mux1 (
    input wire [1:0] d,
    input wire a,
    output wire y
);


    
    assign y = a == 1'b0 ? d[0]:d[1];

endmodule