data/full_repos/permissive/488093047/Verilog Codes/Register_4bit.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/Register_4bit.v\n%Error: Exiting due to 3 error(s)\n'
module Register_4bit(D,Q,clk,reset);
input [3:0]D;
output [3:0]Q;
input clk,reset;
genvar i;
generate
for(i=0;i<4;i=i+1) begin
D_Flipflop DUT(.Q(Q[i]),.D(D[i]),.clk(clk),.reset(reset));
end
endgenerate

endmodule
module Register_4bit(D,Q,clk,reset);

input [3:0]D;
output [3:0]Q;
input clk,reset;
genvar i;
generate
for(i=0;i<4;i=i+1) begin
D_Flipflop DUT(.Q(Q[i]),.D(D[i]),.clk(clk),.reset(reset));
end
endgenerate

endmodule