data/full_repos/permissive/505451992/Converters.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505451992/Converters.v:16: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'PPR\' generates 10 bits.\n                                                                    : ... In instance Converters\nassign PPR_PWM =  32\'d4290772992/ PPR;  \n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Converters(input [9:0] PPR,
input signed [9:0] P,
output [9:0] Position

    );
wire  [9:0] PP;
wire [31:0] PPR_C ;   
wire [31:0] PPR_PWM;
wire [31:0] Position_32;

assign PP = P + ((PPR+1)/10'd2);

assign PPR_PWM =  32'd4290772992/ PPR;
assign Position_32 = PP * PPR_PWM;
assign Position =  Position_32[31:22];

    
    
    
endmodule
module Converters(input [9:0] PPR,
input signed [9:0] P,
output [9:0] Position

    );

wire  [9:0] PP;
wire [31:0] PPR_C ;   
wire [31:0] PPR_PWM;
wire [31:0] Position_32;

assign PP = P + ((PPR+1)/10'd2);

assign PPR_PWM =  32'd4290772992/ PPR;
assign Position_32 = PP * PPR_PWM;
assign Position =  Position_32[31:22];

    
    
    
endmodule