data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_ctu_2xcmp_b.v
data/verilator_xmls/be57b973-041d-4337-bb4d-a2c9f8f8356b.xml
module bw_clk_cl_ctu_2xcmp_b(bw_pll_2x_clk_local_b ,bw_pll_2xclk_b );
output		bw_pll_2x_clk_local_b ;
input		bw_pll_2xclk_b ;
 
assign bw_pll_2x_clk_local_b =  bw_pll_2xclk_b;

endmodule
module bw_clk_cl_ctu_2xcmp_b(bw_pll_2x_clk_local_b ,bw_pll_2xclk_b );

output		bw_pll_2x_clk_local_b ;
input		bw_pll_2xclk_b ;
 
assign bw_pll_2x_clk_local_b =  bw_pll_2xclk_b;

endmodule