data/full_repos/permissive/51625123/src/quad.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51625123/src/quad.v:26: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'ac\' generates 4 bits.\n                                                                 : ... In instance quad\n  count <= paddlelimiter(count_direction ? count + ac : count - ac);\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/quad.v:26: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'ac\' generates 4 bits.\n                                                                 : ... In instance quad\n  count <= paddlelimiter(count_direction ? count + ac : count - ac);\n                                                              ^\n%Warning-UNSIGNED: data/full_repos/permissive/51625123/src/quad.v:36: Comparison is constant due to unsigned arithmetic\n                                                                    : ... In instance quad\n if (py < PADDLESIZE/2) \n        ^\n%Error: Exiting due to 3 warning(s)\n'
module quad(clk, reset, quadA, quadB, count);
parameter SCREENHEIGHT=0;
parameter PADDLESIZE = 0;
input clk, reset, quadA, quadB;
output [9:0] count;

reg [2:0] quadA_delayed, quadB_delayed;
always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};

wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];

reg [5:0] accelcount;
reg [9:0] count;

wire [3:0] ac = (accelcount == 0) ? 1 : 5;
always @(posedge clk or posedge reset)
begin
  if (reset) begin
	count <= SCREENHEIGHT/2;
  end 
  else begin
	  if(count_enable)
	  begin
		count <= paddlelimiter(count_direction ? count + ac : count - ac);
		accelcount <= -1;
	  end
	  if (accelcount != 0) accelcount <= accelcount - 1;
  end
end

function [9:0] paddlelimiter;
input [9:0] py;
begin
	if (py < PADDLESIZE/2) 
		paddlelimiter = PADDLESIZE/2;
	else 
	if (py > SCREENHEIGHT-PADDLESIZE/2)
		paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
	else
		paddlelimiter = py;
end
endfunction

endmodule
module quad(clk, reset, quadA, quadB, count);

parameter SCREENHEIGHT=0;
parameter PADDLESIZE = 0;
input clk, reset, quadA, quadB;
output [9:0] count;

reg [2:0] quadA_delayed, quadB_delayed;
always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};

wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];

reg [5:0] accelcount;
reg [9:0] count;

wire [3:0] ac = (accelcount == 0) ? 1 : 5;
always @(posedge clk or posedge reset)
begin
  if (reset) begin
	count <= SCREENHEIGHT/2;
  end 
  else begin
	  if(count_enable)
	  begin
		count <= paddlelimiter(count_direction ? count + ac : count - ac);
		accelcount <= -1;
	  end
	  if (accelcount != 0) accelcount <= accelcount - 1;
  end
end

function [9:0] paddlelimiter;
input [9:0] py;
begin
	if (py < PADDLESIZE/2) 
		paddlelimiter = PADDLESIZE/2;
	else 
	if (py > SCREENHEIGHT-PADDLESIZE/2)
		paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
	else
		paddlelimiter = py;
end
endfunction

endmodule