data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v
1: b'%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:5: Cannot find include file: aDefinitions.v\n`include "aDefinitions.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v.v\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v.sv\n             aDefinitions.v\n             aDefinitions.v.v\n             aDefinitions.v.sv\n             obj_dir/aDefinitions.v\n             obj_dir/aDefinitions.v.v\n             obj_dir/aDefinitions.v.sv\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:6: Cannot find include file: collaterals.v\n`include "collaterals.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:7: Cannot find include file: SoundControllerChannel2.v\n`include "SoundControllerChannel2.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:8: Cannot find include file: SoundControllerOSC1.v\n`include "SoundControllerOSC1.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:9: Cannot find include file: SoundControllerOSC2.v\n`include "SoundControllerOSC2.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:28: Define or directive not defined: \'`CLOCK_CYCLE\'\n    #`CLOCK_CYCLE clk = ~clk;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:28: syntax error, unexpected \'=\'\n    #`CLOCK_CYCLE clk = ~clk;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #`CLOCK_CYCLE clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:62: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump_sound_channel2.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:63: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:65: Unsupported or unknown PLI call: $monitor\n    $monitor ("%0d \\t\\t %0d",$time, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:87: syntax error, unexpected \'@\'\n    repeat (2) @ (negedge clk);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel2.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #50_000_000;\n    ^\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module tb;
  
  reg clk;
  wire clk64;
  wire clk256;
  wire clk131k;
  wire clk262k;
  reg rst;
  wire [4:0] out;

  reg [7:0] nr20;
  reg [7:0] nr21;
  reg [7:0] nr22;
  reg [7:0] nr23;
  reg [7:0] nr24;
  
  always begin
    #`CLOCK_CYCLE clk = ~clk;
  end
  
 osc1 o1
  (
    .iClock(clk),
    .iReset(rst),
    .oOut64(clk64),
    .oOut256(clk256)
  );

 osc2 o2
  (
    .iClock(clk),
    .iReset(rst),
    .oOut131k(clk131k),
    .oOut262k(clk262k)
  );


  SoundCtrlChannel2 # () scc2 (
    .iClock(clk),
    .iReset(rst),
    .iOsc64(clk64),
    .iOsc256(clk256),
    .iOsc262k(clk262k),
    .iNR21(nr21),
    .iNR22(nr22),
    .iNR23(nr23),
    .iNR24(nr24),
    .oOut(out)
  );

  initial begin
    $dumpfile("dump_sound_channel2.vcd");
    $dumpvars();
    $display("tiempo \t\t out2");
    $monitor ("%0d \t\t %0d",$time, out);
    clk = 0;
    rst = 1'b0;
    #10 rst = 1'b1;








    repeat (2) @ (negedge clk);
    rst = 1'b0;
    #50_000_000;

    $finish;
  end
  
endmodule
module tb;

  
  reg clk;
  wire clk64;
  wire clk256;
  wire clk131k;
  wire clk262k;
  reg rst;
  wire [4:0] out;

  reg [7:0] nr20;
  reg [7:0] nr21;
  reg [7:0] nr22;
  reg [7:0] nr23;
  reg [7:0] nr24;
  
  always begin
    #`CLOCK_CYCLE clk = ~clk;
  end
  
 osc1 o1
  (
    .iClock(clk),
    .iReset(rst),
    .oOut64(clk64),
    .oOut256(clk256)
  );

 osc2 o2
  (
    .iClock(clk),
    .iReset(rst),
    .oOut131k(clk131k),
    .oOut262k(clk262k)
  );


  SoundCtrlChannel2 # () scc2 (
    .iClock(clk),
    .iReset(rst),
    .iOsc64(clk64),
    .iOsc256(clk256),
    .iOsc262k(clk262k),
    .iNR21(nr21),
    .iNR22(nr22),
    .iNR23(nr23),
    .iNR24(nr24),
    .oOut(out)
  );

  initial begin
    $dumpfile("dump_sound_channel2.vcd");
    $dumpvars();
    $display("tiempo \t\t out2");
    $monitor ("%0d \t\t %0d",$time, out);
    clk = 0;
    rst = 1'b0;
    #10 rst = 1'b1;








    repeat (2) @ (negedge clk);
    rst = 1'b0;
    #50_000_000;

    $finish;
  end
  
endmodule