data/full_repos/permissive/482974019/CORDIC.srcs/sources_1/new/LookUpTable.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482974019/CORDIC.srcs/sources_1/new/LookUpTable.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?h133\' generates 32 or 9 bits.\n                                                                                               : ... In instance LookUpTable\n                gammaF = \'b100110011; \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LookUpTable #(parameter WII = 8, WFI = 8)
    (input [3:0] iterationIndex,
    output reg [(WII+WFI)-1:0] gamma);
    
    reg [WII-1:0] gammaI;
    reg [WFI-1:0] gammaF;
    
    always@(*) begin
        case(iterationIndex)
            0: begin
                gammaI = 'd45;
                gammaF = 'd0; 
            end
            1: begin
                gammaI = 'd26;
                gammaF = 'b100110011; 
            end
            2: begin
                gammaI = 'd14;
                gammaF = 'd0; 
            end
            3: begin
                gammaI = 'd7;
                gammaF = 'b00100000; 
            end 
            4: begin 
                gammaI = 'd3;
                gammaF = 'b10010011; 
            end 
            5: begin 
                gammaI = 'd1;
                gammaF = 'b11001010; 
            end 
            6: begin 
                gammaI = 'd0;
                gammaF = 'b11100101; 
            end 
            7: begin
                gammaI = 'd0;
                gammaF = 'b01110010; 
            end 
            8: begin
                gammaI = 'd0;
                gammaF = 'b00111001; 
            end 
            9: begin
                gammaI = 'd0;
                gammaF = 'b00011100; 
            end
        endcase
        gamma = {gammaI, gammaF};
    end
    
endmodule
module LookUpTable #(parameter WII = 8, WFI = 8)
    (input [3:0] iterationIndex,
    output reg [(WII+WFI)-1:0] gamma);

    
    reg [WII-1:0] gammaI;
    reg [WFI-1:0] gammaF;
    
    always@(*) begin
        case(iterationIndex)
            0: begin
                gammaI = 'd45;
                gammaF = 'd0; 
            end
            1: begin
                gammaI = 'd26;
                gammaF = 'b100110011; 
            end
            2: begin
                gammaI = 'd14;
                gammaF = 'd0; 
            end
            3: begin
                gammaI = 'd7;
                gammaF = 'b00100000; 
            end 
            4: begin 
                gammaI = 'd3;
                gammaF = 'b10010011; 
            end 
            5: begin 
                gammaI = 'd1;
                gammaF = 'b11001010; 
            end 
            6: begin 
                gammaI = 'd0;
                gammaF = 'b11100101; 
            end 
            7: begin
                gammaI = 'd0;
                gammaF = 'b01110010; 
            end 
            8: begin
                gammaI = 'd0;
                gammaF = 'b00111001; 
            end 
            9: begin
                gammaI = 'd0;
                gammaF = 'b00011100; 
            end
        endcase
        gamma = {gammaI, gammaF};
    end
    
endmodule