data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_mapause.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_mapause.v:50: Cannot find file containing module: 'fflopxe'\nfflopxe #(16) ffcappauqua (maclk, marst_, ma_ipauvld, ma_ipauqua, opauqua);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: Exiting due to 1 error(s)\n"
module ipsmacge_mapause
    (
     marst_,
     maclk,

     ma_ipauvld,
     ma_ipauqua,

     opauqua,
     opauvld,

     pwnum
     );






input               marst_;
input               maclk;

input               ma_ipauvld;
input [15:0]        ma_ipauqua;

output [15:0]       opauqua;
output              opauvld;

input [5:0]         pwnum;







fflopxe #(16) ffcappauqua (maclk, marst_, ma_ipauvld, ma_ipauqua, opauqua);

reg [5:0] cntpauvld;
wire      cntpauend;
assign    cntpauend = (cntpauvld >= pwnum);

always @(posedge maclk or negedge marst_)
    begin
    if (~marst_)            cntpauvld <= 6'b0;
    else if (ma_ipauvld)    cntpauvld <= 6'b1;
    else if (|cntpauvld)    cntpauvld <= cntpauend ? 6'b0 : cntpauvld + 1'b1;
    end

reg opauvld;

always @(posedge maclk or negedge marst_)
    begin
    if (!marst_)            opauvld <= 1'b0;
    else if (ma_ipauvld)     opauvld <= 1'b1;
    else                    opauvld <= (|cntpauvld) ? 1'b1 : 1'b0;
    end
              
endmodule
module ipsmacge_mapause
    (
     marst_,
     maclk,

     ma_ipauvld,
     ma_ipauqua,

     opauqua,
     opauvld,

     pwnum
     );







input               marst_;
input               maclk;

input               ma_ipauvld;
input [15:0]        ma_ipauqua;

output [15:0]       opauqua;
output              opauvld;

input [5:0]         pwnum;







fflopxe #(16) ffcappauqua (maclk, marst_, ma_ipauvld, ma_ipauqua, opauqua);

reg [5:0] cntpauvld;
wire      cntpauend;
assign    cntpauend = (cntpauvld >= pwnum);

always @(posedge maclk or negedge marst_)
    begin
    if (~marst_)            cntpauvld <= 6'b0;
    else if (ma_ipauvld)    cntpauvld <= 6'b1;
    else if (|cntpauvld)    cntpauvld <= cntpauend ? 6'b0 : cntpauvld + 1'b1;
    end

reg opauvld;

always @(posedge maclk or negedge marst_)
    begin
    if (!marst_)            opauvld <= 1'b0;
    else if (ma_ipauvld)     opauvld <= 1'b1;
    else                    opauvld <= (|cntpauvld) ? 1'b1 : 1'b0;
    end
              
endmodule