data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:41: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:49: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:57: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:65: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 19 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:12] = {19{in[31]}};   \n                       ^\n%Error: Exiting due to 4 warning(s)\n'
module ID(input clk,
          input [31:0] PC_ID, INSTRUCTION_ID,
          input RegWrite_WB,
          input [31:0] ALU_DATA_WB,
          input [4:0] RD_WB,
          output [31:0] IMM_ID,
          output [31:0] REG_DATA1_ID, REG_DATA2_ID,
          output [2:0] FUNCT3_ID,
          output [6:0] FUNCT7_ID,
          output [6:0] OPCODE_ID,
          output [4:0] RD_ID,
          output [4:0] RS1_ID,
          output [4:0] RS2_ID);
    registers registers1(clk, RegWrite_WB, 
                   INSTRUCTION_ID[19:15], 
                   INSTRUCTION_ID[24:20],
                   RD_WB, ALU_DATA_WB, 
                   REG_DATA1_ID, REG_DATA2_ID);
    imm_gen imm_gen1(INSTRUCTION_ID, IMM_ID);
    assign OPCODE_ID = INSTRUCTION_ID[6:0];
    assign RD_ID = INSTRUCTION_ID[11:7];
    assign FUNCT3_ID = INSTRUCTION_ID[14:12];
    assign RS1_ID = INSTRUCTION_ID[19:15];
    assign RS2_ID = INSTRUCTION_ID[24:20];
    assign FUNCT7_ID = INSTRUCTION_ID[31:25];  
endmodule
module ID(input clk,
          input [31:0] PC_ID, INSTRUCTION_ID,
          input RegWrite_WB,
          input [31:0] ALU_DATA_WB,
          input [4:0] RD_WB,
          output [31:0] IMM_ID,
          output [31:0] REG_DATA1_ID, REG_DATA2_ID,
          output [2:0] FUNCT3_ID,
          output [6:0] FUNCT7_ID,
          output [6:0] OPCODE_ID,
          output [4:0] RD_ID,
          output [4:0] RS1_ID,
          output [4:0] RS2_ID);

    registers registers1(clk, RegWrite_WB, 
                   INSTRUCTION_ID[19:15], 
                   INSTRUCTION_ID[24:20],
                   RD_WB, ALU_DATA_WB, 
                   REG_DATA1_ID, REG_DATA2_ID);
    imm_gen imm_gen1(INSTRUCTION_ID, IMM_ID);
    assign OPCODE_ID = INSTRUCTION_ID[6:0];
    assign RD_ID = INSTRUCTION_ID[11:7];
    assign FUNCT3_ID = INSTRUCTION_ID[14:12];
    assign RS1_ID = INSTRUCTION_ID[19:15];
    assign RS2_ID = INSTRUCTION_ID[24:20];
    assign FUNCT7_ID = INSTRUCTION_ID[31:25];  
endmodule