data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/FanInPrimitive_Req.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/FanInPrimitive_Req.sv:45: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module FanInPrimitive_Req 
#(
    parameter ADDR_WIDTH  = 32, 
    parameter ID_WIDTH    = 16,
    parameter DATA_WIDTH  = 32,
    parameter N_MASTER    = 8,
    parameter BE_WIDTH    = DATA_WIDTH/8
)
(
    input logic                                  PRIO_FLAG,


    input  logic [DATA_WIDTH-1:0]                data_wdata0_i,
    input  logic [DATA_WIDTH-1:0]                data_wdata1_i,
    input  logic [ADDR_WIDTH-1:0]                data_add0_i,
    input  logic [ADDR_WIDTH-1:0]                data_add1_i,
    input  logic                                 data_req0_i,
    input  logic                                 data_req1_i,
    input  logic                                 data_wen0_i,
    input  logic                                 data_wen1_i,
    input  logic [BE_WIDTH-1:0]                  data_be0_i,
    input  logic [BE_WIDTH-1:0]                  data_be1_i,
    input  logic [ID_WIDTH-1:0]                  data_ID0_i,
    input  logic [ID_WIDTH-1:0]                  data_ID1_i,
    input  logic [$clog2(N_MASTER)-1:0]          ID0_i,
    input  logic [$clog2(N_MASTER)-1:0]          ID1_i,
`ifdef GNT_BASED_FC      
    output logic                                 data_gnt0_o,
    output logic                                 data_gnt1_o,
`else
    output logic                                 data_stall0_o,
    output logic                                 data_stall1_o,
`endif

    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [ADDR_WIDTH-1:0]                data_add_o,
    output logic                                 data_req_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
    output logic [$clog2(N_MASTER)-1:0]          ID_o,
    output logic                                 data_wen_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
`ifdef GNT_BASED_FC
    input  logic                                 data_gnt_i
`else
    input  logic                                 data_stall_i
`endif
);

    logic      SEL;

    assign data_req_o       =     data_req0_i | data_req1_i;
    assign SEL              =    ~data_req0_i | ( PRIO_FLAG & data_req1_i);

`ifdef GNT_BASED_FC

    assign data_gnt0_o      =    (( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_gnt_i;
    assign data_gnt1_o      =    ((~data_req0_i &  data_req1_i) | ( data_req1_i &  PRIO_FLAG)) & data_gnt_i;    
`else

    assign data_stall0_o    =   (data_req0_i & data_req1_i & PRIO_FLAG)  |  ((( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_stall_i);
    assign data_stall1_o    =   (data_req0_i & data_req1_i & ~PRIO_FLAG) |  (((~data_req0_i &  data_req1_i) | ( data_req1_i &  PRIO_FLAG)) & data_stall_i);
`endif


    always_comb
    begin : FanIn_MUX2
        case(SEL)
        1'b0:
        begin
            data_wdata_o = data_wdata0_i;
            data_add_o   = data_add0_i;
            data_wen_o   = data_wen0_i;
            data_ID_o    = data_ID0_i;
            data_be_o    = data_be0_i;
            ID_o         = ID0_i;
        end

        1'b1:
        begin
            data_wdata_o = data_wdata1_i;
            data_add_o   = data_add1_i;
            data_wen_o   = data_wen1_i;
            data_ID_o    = data_ID1_i;
            data_be_o    = data_be1_i;
            ID_o         = ID1_i;
        end

        endcase
    end
endmodule
module FanInPrimitive_Req 
#(
    parameter ADDR_WIDTH  = 32, 
    parameter ID_WIDTH    = 16,
    parameter DATA_WIDTH  = 32,
    parameter N_MASTER    = 8,
    parameter BE_WIDTH    = DATA_WIDTH/8
)
(
    input logic                                  PRIO_FLAG,


    input  logic [DATA_WIDTH-1:0]                data_wdata0_i,
    input  logic [DATA_WIDTH-1:0]                data_wdata1_i,
    input  logic [ADDR_WIDTH-1:0]                data_add0_i,
    input  logic [ADDR_WIDTH-1:0]                data_add1_i,
    input  logic                                 data_req0_i,
    input  logic                                 data_req1_i,
    input  logic                                 data_wen0_i,
    input  logic                                 data_wen1_i,
    input  logic [BE_WIDTH-1:0]                  data_be0_i,
    input  logic [BE_WIDTH-1:0]                  data_be1_i,
    input  logic [ID_WIDTH-1:0]                  data_ID0_i,
    input  logic [ID_WIDTH-1:0]                  data_ID1_i,
    input  logic [$clog2(N_MASTER)-1:0]          ID0_i,
    input  logic [$clog2(N_MASTER)-1:0]          ID1_i,
`ifdef GNT_BASED_FC      
    output logic                                 data_gnt0_o,
    output logic                                 data_gnt1_o,
`else
    output logic                                 data_stall0_o,
    output logic                                 data_stall1_o,
`endif

    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [ADDR_WIDTH-1:0]                data_add_o,
    output logic                                 data_req_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
    output logic [$clog2(N_MASTER)-1:0]          ID_o,
    output logic                                 data_wen_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
`ifdef GNT_BASED_FC
    input  logic                                 data_gnt_i
`else
    input  logic                                 data_stall_i
`endif
);


    logic      SEL;

    assign data_req_o       =     data_req0_i | data_req1_i;
    assign SEL              =    ~data_req0_i | ( PRIO_FLAG & data_req1_i);

`ifdef GNT_BASED_FC

    assign data_gnt0_o      =    (( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_gnt_i;
    assign data_gnt1_o      =    ((~data_req0_i &  data_req1_i) | ( data_req1_i &  PRIO_FLAG)) & data_gnt_i;    
`else

    assign data_stall0_o    =   (data_req0_i & data_req1_i & PRIO_FLAG)  |  ((( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_stall_i);
    assign data_stall1_o    =   (data_req0_i & data_req1_i & ~PRIO_FLAG) |  (((~data_req0_i &  data_req1_i) | ( data_req1_i &  PRIO_FLAG)) & data_stall_i);
`endif


    always_comb
    begin : FanIn_MUX2
        case(SEL)
        1'b0:
        begin
            data_wdata_o = data_wdata0_i;
            data_add_o   = data_add0_i;
            data_wen_o   = data_wen0_i;
            data_ID_o    = data_ID0_i;
            data_be_o    = data_be0_i;
            ID_o         = ID0_i;
        end

        1'b1:
        begin
            data_wdata_o = data_wdata1_i;
            data_add_o   = data_add1_i;
            data_wen_o   = data_wen1_i;
            data_ID_o    = data_ID1_i;
            data_be_o    = data_be1_i;
            ID_o         = ID1_i;
        end

        endcase
    end
endmodule