data/full_repos/permissive/468929885/verilog/rtl/el_min.v
1: b"%Error: data/full_repos/permissive/468929885/verilog/rtl/el_min.v:22: Cannot find file containing module: 'el_ed'\nel_ed pair_det [IN_NUM-1 : 0]\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_ed\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_ed.v\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_ed.sv\n             el_ed\n             el_ed.v\n             el_ed.sv\n             obj_dir/el_ed\n             obj_dir/el_ed.v\n             obj_dir/el_ed.sv\n%Error: Internal Error: data/full_repos/permissive/468929885/verilog/rtl/el_min.v:22: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x55e392ae1900 <e120> {c22}  IN_NUM [TEXT]\n                                                                                    : ... In instance el_min\nel_ed pair_det [IN_NUM-1 : 0]\n                ^~~~~~\n"
module el_min#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input							en,
	input	[IN_NUM-1 : 0]			in,

	output							out

);


wire [IN_NUM-1 : 0] pair_w;
wire out_w;
assign out = out_w;

el_ed pair_det [IN_NUM-1 : 0]
(

	.rst(rst),
	
	.en(en),
	.fb(out_w),
	.in(in),
	
	.out(pair_w)
);

c_elem#
(
	.IN_NUM(IN_NUM)
)
c_agg
(
	.rst(rst),
	
	.in(pair_w),
	.out(out_w)
);



endmodule
module el_min#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input							en,
	input	[IN_NUM-1 : 0]			in,

	output							out

);



wire [IN_NUM-1 : 0] pair_w;
wire out_w;
assign out = out_w;

el_ed pair_det [IN_NUM-1 : 0]
(

	.rst(rst),
	
	.en(en),
	.fb(out_w),
	.in(in),
	
	.out(pair_w)
);

c_elem#
(
	.IN_NUM(IN_NUM)
)
c_agg
(
	.rst(rst),
	
	.in(pair_w),
	.out(out_w)
);



endmodule