data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv
1: b'%Error: data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv:12: Cannot find include file: definitions.sv\n`include "definitions.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.v\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.sv\n             definitions.sv\n             definitions.sv.v\n             definitions.sv.sv\n             obj_dir/definitions.sv\n             obj_dir/definitions.sv.v\n             obj_dir/definitions.sv.sv\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv:57: Define or directive not defined: \'`MSFF\'\n`MSFF(mem, next_mem, clock)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv:57: syntax error, unexpected \'(\'\n`MSFF(mem, next_mem, clock)\n      ^~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv:67: Define or directive not defined: \'`MSFF\'\n`MSFF(q, pre_q, clock)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/ram2port_sim.sv:67: syntax error, unexpected \'(\'\n`MSFF(q, pre_q, clock)\n      ^\n%Error: Cannot continue\n'
module ram2port_sim (
    input  logic        clock    ,

    input  logic [12:0] wraddress,
    input  logic [31:0] data     ,
    input  logic        wren     ,

    input  logic [12:0] rdaddress,
    output logic [31:0] q
    );
logic [7:0]  mem     [38400-1:0];
logic [7:0]  next_mem[38400-1:0];
logic [31:0] pre_q;  
logic [15:0] RdAddressByteAl;
logic [15:0] WrAddressByteAl;
assign  WrAddressByteAl = {wraddress,2'b00};
assign  RdAddressByteAl = {rdaddress,2'b00};



logic [7:0] Byte0;
logic [7:0] Byte1;
logic [7:0] Byte2;
logic [7:0] Byte3;
logic [7:0] RdByte0;
logic [7:0] RdByte1;
logic [7:0] RdByte2;
logic [7:0] RdByte3;
assign Byte0 = data[7:0];
assign Byte1 = data[15:8];
assign Byte2 = data[23:16];
assign Byte3 = data[31:24];
always_comb begin
    next_mem = mem;
    if(wren) begin
        next_mem[WrAddressByteAl+0]= Byte0;
        next_mem[WrAddressByteAl+1]= Byte1;
        next_mem[WrAddressByteAl+2]= Byte2;
        next_mem[WrAddressByteAl+3]= Byte3; 
    end
end 



`MSFF(mem, next_mem, clock)



assign RdByte0 = mem[RdAddressByteAl+0];
assign RdByte1 = mem[RdAddressByteAl+1];
assign RdByte2 = mem[RdAddressByteAl+2];
assign RdByte3 = mem[RdAddressByteAl+3];
assign pre_q= {RdByte3, RdByte2, RdByte1, RdByte0};

`MSFF(q, pre_q, clock)

endmodule
module ram2port_sim (
    input  logic        clock    ,

    input  logic [12:0] wraddress,
    input  logic [31:0] data     ,
    input  logic        wren     ,

    input  logic [12:0] rdaddress,
    output logic [31:0] q
    );

logic [7:0]  mem     [38400-1:0];
logic [7:0]  next_mem[38400-1:0];
logic [31:0] pre_q;  
logic [15:0] RdAddressByteAl;
logic [15:0] WrAddressByteAl;
assign  WrAddressByteAl = {wraddress,2'b00};
assign  RdAddressByteAl = {rdaddress,2'b00};



logic [7:0] Byte0;
logic [7:0] Byte1;
logic [7:0] Byte2;
logic [7:0] Byte3;
logic [7:0] RdByte0;
logic [7:0] RdByte1;
logic [7:0] RdByte2;
logic [7:0] RdByte3;
assign Byte0 = data[7:0];
assign Byte1 = data[15:8];
assign Byte2 = data[23:16];
assign Byte3 = data[31:24];
always_comb begin
    next_mem = mem;
    if(wren) begin
        next_mem[WrAddressByteAl+0]= Byte0;
        next_mem[WrAddressByteAl+1]= Byte1;
        next_mem[WrAddressByteAl+2]= Byte2;
        next_mem[WrAddressByteAl+3]= Byte3; 
    end
end 



`MSFF(mem, next_mem, clock)



assign RdByte0 = mem[RdAddressByteAl+0];
assign RdByte1 = mem[RdAddressByteAl+1];
assign RdByte2 = mem[RdAddressByteAl+2];
assign RdByte3 = mem[RdAddressByteAl+3];
assign pre_q= {RdByte3, RdByte2, RdByte1, RdByte0};

`MSFF(q, pre_q, clock)

endmodule