data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'a_in\' generates 1 bits.\n                                                                                                                 : ... In instance v2k_reg\n    adder = a_in + b_in + c_in + data_in;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'b_in\' generates 1 bits.\n                                                                                                                 : ... In instance v2k_reg\n    adder = a_in + b_in + c_in + data_in;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'c_in\' generates 1 bits.\n                                                                                                                 : ... In instance v2k_reg\n    adder = a_in + b_in + c_in + data_in;\n                        ^\n%Error: Exiting due to 3 warning(s)\n'
function signed [7:0] adder;
  input a_in;
  input b_in;
  input c_in;
  input signed [7:0] data_in;
  begin
    adder = a_in + b_in + c_in + data_in;
  end
endfunction
function signed [7:0] adder;

  input a_in;
  input b_in;
  input c_in;
  input signed [7:0] data_in;
  begin
    adder = a_in + b_in + c_in + data_in;
  end
endfunction