data/full_repos/permissive/453980391/src/and_beh_tb.v
1: b'%Error: data/full_repos/permissive/453980391/src/and_beh_tb.v:8: Unsupported or unknown PLI call: $monitor\n        $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/453980391/src/and_beh_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("and_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/453980391/src/and_beh_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, and_beh_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/453980391/src/and_beh_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 0; B = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453980391/src/and_beh_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/453980391/src/and_beh_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/453980391/src/and_beh_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_beh_tb;
    reg A, B;
    wire Y;
    and_b A0 (.out(Y), .x(A), .y(B));
    initial begin
        A = 0; B = 0;

        $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
        $dumpfile("and_tb.vcd");
        $dumpvars(0, and_beh_tb);

        #10 A = 0; B = 1;
        #10 A = 1; B = 0;
        #10 A = 1; B = 1;
        #20 $finish;
    end
endmodule
module and_beh_tb;

    reg A, B;
    wire Y;
    and_b A0 (.out(Y), .x(A), .y(B));
    initial begin
        A = 0; B = 0;

        $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
        $dumpfile("and_tb.vcd");
        $dumpvars(0, and_beh_tb);

        #10 A = 0; B = 1;
        #10 A = 1; B = 0;
        #10 A = 1; B = 1;
        #20 $finish;
    end
endmodule