data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/tb_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/tb_testbench.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/tb_testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire A, B, RES;
wire [1:0] ALUCTRL; 

ALU_test tester (.t1(A), .t2(B), .t3(ALUCTRL), .p1(RES));
ALU         dut (.A(A), .B(B), .ALUCtrl(ALUCTRL), .Res(RES));

always @(A or B or RES or ALUCTRL)
begin
    #1;
    $display("%b %b %2b %b", A, B, ALUCTRL, RES);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire A, B, RES;
wire [1:0] ALUCTRL; 

ALU_test tester (.t1(A), .t2(B), .t3(ALUCTRL), .p1(RES));
ALU         dut (.A(A), .B(B), .ALUCtrl(ALUCTRL), .Res(RES));

always @(A or B or RES or ALUCTRL)
begin
    #1;
    $display("%b %b %2b %b", A, B, ALUCTRL, RES);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule