data/full_repos/permissive/501115231/DMA/fifo.v
data/verilator_xmls/487f092e-1846-4f9a-99e8-c66d28e193d3.xml
module FifoBuffer(buff_out,empty,full,buff_in,wr_en,rd_en,clk,rst);

  input wire clk,rst,rd_en,wr_en;
  input wire[15:0] buff_in;
  
  output wire empty,full;
  output reg[15:0] buff_out;
   
  reg[2:0] rd_ptr=0 ,wr_ptr=0;
  reg[3:0] count=0;
  reg[15:0] buffer[7:0];

  assign empty = (count==0)? 1'b1:1'b0;
  assign full  = (count==8)? 1'b1:1'b0;







  always@(posedge clk or posedge rst)
    begin
      if(rst)
        count<=0;
      else if(!empty && rd_en && !full && wr_en)
        count<=count;   
      else if(!empty && rd_en)
        count<=count-1;
      else if(!full && wr_en)
        count<=count+1; 
      else
        count<=count;
    end
  

  always@(posedge clk or posedge rst)
  begin
      if(rst)
        begin
        rd_ptr<=0;
        wr_ptr<=0;
        end
      else
       begin
         if(!empty && rd_en)
           rd_ptr<=rd_ptr+1;

         if(!full && wr_en)
           wr_ptr<=wr_ptr+1;
       end
   end
  
  always@(posedge clk)
    begin
      if(!full && wr_en)
        buffer[wr_ptr]<=buff_in;
    end
  
  always@(posedge clk)
    begin
      if(!empty && rd_en)
        buff_out<=buffer[rd_ptr];
    end

   

   
endmodule
module FifoBuffer(buff_out,empty,full,buff_in,wr_en,rd_en,clk,rst);


  input wire clk,rst,rd_en,wr_en;
  input wire[15:0] buff_in;
  
  output wire empty,full;
  output reg[15:0] buff_out;
   
  reg[2:0] rd_ptr=0 ,wr_ptr=0;
  reg[3:0] count=0;
  reg[15:0] buffer[7:0];

  assign empty = (count==0)? 1'b1:1'b0;
  assign full  = (count==8)? 1'b1:1'b0;







  always@(posedge clk or posedge rst)
    begin
      if(rst)
        count<=0;
      else if(!empty && rd_en && !full && wr_en)
        count<=count;   
      else if(!empty && rd_en)
        count<=count-1;
      else if(!full && wr_en)
        count<=count+1; 
      else
        count<=count;
    end
  

  always@(posedge clk or posedge rst)
  begin
      if(rst)
        begin
        rd_ptr<=0;
        wr_ptr<=0;
        end
      else
       begin
         if(!empty && rd_en)
           rd_ptr<=rd_ptr+1;

         if(!full && wr_en)
           wr_ptr<=wr_ptr+1;
       end
   end
  
  always@(posedge clk)
    begin
      if(!full && wr_en)
        buffer[wr_ptr]<=buff_in;
    end
  
  always@(posedge clk)
    begin
      if(!empty && rd_en)
        buff_out<=buffer[rd_ptr];
    end

   

   
endmodule