data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:31: Unsupported: Ignoring delay on this delayed statement.\n always #5 C = ~C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:35: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("salida.dmp");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:36: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:39: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | | O: %b, C: %b, num: %d", O, C, O);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:54: Unsupported: Ignoring delay on this delayed statement.\n                #120;\n                ^\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorArbitrario.v:57: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Contador4bitsJK(output wire [2:0] O, input wire C);
	wire [2:0] nQ;
	wire K0, K1;

	JKDown JK0(O[0], nQ[0], nQ[2], K0, C);
	JKDown JK1(O[1], nQ[1], 1'b1, K1, C);
	JKDown JK2(O[2], nQ[2], O[0], nQ[0], C);

	xor(K0, O[2], O[1]);
	and(K1, nQ[2], O[0]);
endmodule
module Contador4bitsJK(output wire [2:0] O, input wire C);

	wire [2:0] nQ;
	wire K0, K1;

	JKDown JK0(O[0], nQ[0], nQ[2], K0, C);
	JKDown JK1(O[1], nQ[1], 1'b1, K1, C);
	JKDown JK2(O[2], nQ[2], O[0], nQ[0], C);

	xor(K0, O[2], O[1]);
	and(K1, nQ[2], O[0]);
endmodule