data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/clic/rtl/pa_clic_expand.v
data/verilator_xmls/b3441bdd-4f96-4f59-9598-d7bbb367b031.xml
module pa_clic_expand(

  data_in_vec,

  expand_out_vec
);

parameter WIDTH = 6;
parameter NUM   = 32;
localparam EXP_WIDTH = 1 <<< WIDTH;

input  [WIDTH*NUM-1:0]      data_in_vec;
output [EXP_WIDTH*NUM-1:0]  expand_out_vec;

wire   [WIDTH*NUM-1:0]      data_in_vec;
wire   [EXP_WIDTH*NUM-1:0]  expand_out_vec;

genvar i;

generate
  for (i = 0; i < NUM; i = i+1)
  begin: EXPAND
    assign expand_out_vec[EXP_WIDTH*i+:EXP_WIDTH] = {{EXP_WIDTH-1{1'b0}}, 1'b1} << data_in_vec[WIDTH*i+:WIDTH];
  end
endgenerate

endmodule
module pa_clic_expand(

  data_in_vec,

  expand_out_vec
);


parameter WIDTH = 6;
parameter NUM   = 32;
localparam EXP_WIDTH = 1 <<< WIDTH;

input  [WIDTH*NUM-1:0]      data_in_vec;
output [EXP_WIDTH*NUM-1:0]  expand_out_vec;

wire   [WIDTH*NUM-1:0]      data_in_vec;
wire   [EXP_WIDTH*NUM-1:0]  expand_out_vec;

genvar i;

generate
  for (i = 0; i < NUM; i = i+1)
  begin: EXPAND
    assign expand_out_vec[EXP_WIDTH*i+:EXP_WIDTH] = {{EXP_WIDTH-1{1'b0}}, 1'b1} << data_in_vec[WIDTH*i+:WIDTH];
  end
endgenerate

endmodule