data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration first part/processingElement16.v
1: b'%Error: Cannot find file containing module: first\n        ... Looked in:\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first.v\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration/first.sv\n             first\n             first.v\n             first.sv\n             obj_dir/first\n             obj_dir/first.v\n             obj_dir/first.sv\n%Error: Cannot find file containing module: part,data/full_repos/permissive/529176308\n%Error: Cannot find file containing module: data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration\n%Error: Cannot find file containing module: part/processingElement16.v\n%Error: Exiting due to 4 error(s)\n'
module processingElement16(clk,reset,floatA,floatB,result);

parameter DATA_WIDTH = 16;

input clk, reset;
input [DATA_WIDTH-1:0] floatA, floatB;
output reg [DATA_WIDTH-1:0] result;

wire [DATA_WIDTH-1:0] multResult;
wire [DATA_WIDTH-1:0] addResult;

floatMult16 FM (floatA,floatB,multResult);
floatAdd16 FADD (multResult,result,addResult);

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1) begin
		result = 0;
	end else begin
		result = addResult;
	end
end

endmodule
module processingElement16(clk,reset,floatA,floatB,result);


parameter DATA_WIDTH = 16;

input clk, reset;
input [DATA_WIDTH-1:0] floatA, floatB;
output reg [DATA_WIDTH-1:0] result;

wire [DATA_WIDTH-1:0] multResult;
wire [DATA_WIDTH-1:0] addResult;

floatMult16 FM (floatA,floatB,multResult);
floatAdd16 FADD (multResult,result,addResult);

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1) begin
		result = 0;
	end else begin
		result = addResult;
	end
end

endmodule