data/full_repos/permissive/423547971/FPGA Projects/PmodENC/encoder.v
1: b'%Error: Cannot find file containing module: Projects/PmodENC,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             Projects/PmodENC,data/full_repos/permissive/423547971\n             Projects/PmodENC,data/full_repos/permissive/423547971.v\n             Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/PmodENC/encoder.v\n%Error: Exiting due to 3 error(s)\n'
module encoder(
    input clk,
    input A,
    input B,
    input BTN,
    output reg [4:0] EncOut,
    output reg [1:0] LED
    ); 
	 
    reg [31:0] curState = "idle";
	reg [31:0] nextState;
	 








	 always@(posedge clk or posedge BTN)
	 begin
			 if (BTN) begin
				 curState <= "idle";
				 EncOut <= 0;
			 end



			 else begin
				 if(curState != nextState) begin
						if(curState == "add") begin
								if(EncOut < 19) begin
									EncOut <= EncOut + 1;
								end
								else begin
									EncOut <= 0;
								end
						end
						else if(curState == "sub") begin
								if(EncOut > 0) begin
									EncOut <= EncOut - 1;
								end
								else begin
									EncOut <= 5'd19;
								end
						end
						else begin
								EncOut <= EncOut;
						end
				 end
				 else begin
						EncOut <= EncOut;
				 end

            curState <= nextState;
			 end
	 end





	 always@(curState or A or B)
	 begin
				 case (curState)

					  "idle" : begin
							 LED <= 2'b00;

							 if (B == 1'b0) begin
								 nextState <= "R1";
							 end
							 else if (A == 1'b0) begin
								 nextState <= "L1";
							 end
							 else begin
								 nextState <= "idle";
							 end
					  end


					  "R1" : begin
							 LED <= 2'b01;

							 if (B == 1'b1) begin
								 nextState <= "idle";
							 end
							 else if (A == 1'b0) begin
								 nextState <= "R2";
							 end
							 else begin
								 nextState <= "R1";
							 end
					  end

					  "R2" : begin
							 LED <= 2'b01;

							 if (A == 1'b1) begin
								 nextState <= "R1";
							 end
							 else if (B == 1'b1) begin
								 nextState <= "R3";
							 end
							 else begin
								 nextState <= "R2";
							 end
					  end

					  "R3" : begin
							 LED <= 2'b01;

							 if (B == 1'b0) begin
								 nextState <= "R2";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "add";
							 end
							 else begin
								 nextState <= "R3";
							 end
					  end

					  "R3" : begin
							 LED <= 2'b01;

							 if (B == 1'b0) begin
								 nextState <= "R2";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "add";
							 end
							 else begin
								 nextState <= "R3";
							 end
					  end

					  "add" : begin
							 LED <= 2'b01;
							 nextState <= "idle";
					  end


					  "L1" : begin
							 LED <= 2'b10;

							 if (A == 1'b1) begin
								 nextState <= "idle";
							 end
							 else if (B == 1'b0) begin
								 nextState <= "L2";
							 end
							 else begin
								 nextState <= "L1";
							 end
					  end

					  "L2" : begin
							 LED <= 2'b10;

							 if (B == 1'b1) begin
								 nextState <= "L1";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "L3";
							 end
							 else begin
								 nextState <= "L2";
							 end
					  end

					  "L3" : begin
							 LED <= 2'b10;

							 if (A == 1'b0) begin
								 nextState <= "L2";
							 end
							 else if (B == 1'b1) begin
								 nextState <= "sub";
							 end
							 else begin
								 nextState <= "L3";
							 end
					  end

					  "sub" : begin
							 LED <= 2'b10;
							 nextState <= "idle";
					  end

					  default : begin
							 LED <= 2'b11;
							 nextState <= "idle";
					  end
				 endcase

	 end

endmodule
module encoder(
    input clk,
    input A,
    input B,
    input BTN,
    output reg [4:0] EncOut,
    output reg [1:0] LED
    );
 
	 
    reg [31:0] curState = "idle";
	reg [31:0] nextState;
	 








	 always@(posedge clk or posedge BTN)
	 begin
			 if (BTN) begin
				 curState <= "idle";
				 EncOut <= 0;
			 end



			 else begin
				 if(curState != nextState) begin
						if(curState == "add") begin
								if(EncOut < 19) begin
									EncOut <= EncOut + 1;
								end
								else begin
									EncOut <= 0;
								end
						end
						else if(curState == "sub") begin
								if(EncOut > 0) begin
									EncOut <= EncOut - 1;
								end
								else begin
									EncOut <= 5'd19;
								end
						end
						else begin
								EncOut <= EncOut;
						end
				 end
				 else begin
						EncOut <= EncOut;
				 end

            curState <= nextState;
			 end
	 end





	 always@(curState or A or B)
	 begin
				 case (curState)

					  "idle" : begin
							 LED <= 2'b00;

							 if (B == 1'b0) begin
								 nextState <= "R1";
							 end
							 else if (A == 1'b0) begin
								 nextState <= "L1";
							 end
							 else begin
								 nextState <= "idle";
							 end
					  end


					  "R1" : begin
							 LED <= 2'b01;

							 if (B == 1'b1) begin
								 nextState <= "idle";
							 end
							 else if (A == 1'b0) begin
								 nextState <= "R2";
							 end
							 else begin
								 nextState <= "R1";
							 end
					  end

					  "R2" : begin
							 LED <= 2'b01;

							 if (A == 1'b1) begin
								 nextState <= "R1";
							 end
							 else if (B == 1'b1) begin
								 nextState <= "R3";
							 end
							 else begin
								 nextState <= "R2";
							 end
					  end

					  "R3" : begin
							 LED <= 2'b01;

							 if (B == 1'b0) begin
								 nextState <= "R2";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "add";
							 end
							 else begin
								 nextState <= "R3";
							 end
					  end

					  "R3" : begin
							 LED <= 2'b01;

							 if (B == 1'b0) begin
								 nextState <= "R2";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "add";
							 end
							 else begin
								 nextState <= "R3";
							 end
					  end

					  "add" : begin
							 LED <= 2'b01;
							 nextState <= "idle";
					  end


					  "L1" : begin
							 LED <= 2'b10;

							 if (A == 1'b1) begin
								 nextState <= "idle";
							 end
							 else if (B == 1'b0) begin
								 nextState <= "L2";
							 end
							 else begin
								 nextState <= "L1";
							 end
					  end

					  "L2" : begin
							 LED <= 2'b10;

							 if (B == 1'b1) begin
								 nextState <= "L1";
							 end
							 else if (A == 1'b1) begin
								 nextState <= "L3";
							 end
							 else begin
								 nextState <= "L2";
							 end
					  end

					  "L3" : begin
							 LED <= 2'b10;

							 if (A == 1'b0) begin
								 nextState <= "L2";
							 end
							 else if (B == 1'b1) begin
								 nextState <= "sub";
							 end
							 else begin
								 nextState <= "L3";
							 end
					  end

					  "sub" : begin
							 LED <= 2'b10;
							 nextState <= "idle";
					  end

					  default : begin
							 LED <= 2'b11;
							 nextState <= "idle";
					  end
				 endcase

	 end

endmodule