data/full_repos/permissive/506186384/project-files/lab6/DataMemory.v
data/verilator_xmls/0717291f-cf05-4f23-8491-9847ecf95497.xml
module DataMemory(
    input Clk,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    input [1:0] MByte,
    output [31:0] ReadData
    );
    
    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    
    always @ (Address or MemFile[Address])
        begin
            rd = 0;
            if(MemRead==1)
                rd = MemFile[Address];
        end
        
    assign ReadData = rd;
    
    always @ (negedge Clk)
        begin
            if(MemWrite==1) begin
                case(MByte)
                    2'b00: MemFile[Address] <= WriteData;
                    2'b01: MemFile[Address][15:0] <= WriteData[15:0];
                    2'b10: MemFile[Address][7:0] <= WriteData[7:0];
                    default: MemFile[Address] <= WriteData;
                endcase 
            end
        end
endmodule
module DataMemory(
    input Clk,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    input [1:0] MByte,
    output [31:0] ReadData
    );

    
    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    
    always @ (Address or MemFile[Address])
        begin
            rd = 0;
            if(MemRead==1)
                rd = MemFile[Address];
        end
        
    assign ReadData = rd;
    
    always @ (negedge Clk)
        begin
            if(MemWrite==1) begin
                case(MByte)
                    2'b00: MemFile[Address] <= WriteData;
                    2'b01: MemFile[Address][15:0] <= WriteData[15:0];
                    2'b10: MemFile[Address][7:0] <= WriteData[7:0];
                    default: MemFile[Address] <= WriteData;
                endcase 
            end
        end
endmodule