data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_up_down_counter.v
data/verilator_xmls/6b134255-557d-4f35-9c53-51a9aadfa6fe.xml
module up_down_counter    (
out      ,
up_down  ,
clk      ,
reset
);

output [7:0] out;

input up_down, clk, reset;

reg [7:0] out;

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (up_down) begin
  out <= out + 1;
end else begin
  out <= out - 1;
end

endmodule
module up_down_counter    (
out      ,
up_down  ,
clk      ,
reset
);


output [7:0] out;

input up_down, clk, reset;

reg [7:0] out;

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (up_down) begin
  out <= out + 1;
end else begin
  out <= out - 1;
end

endmodule