data/full_repos/permissive/425166201/01_test_div/divmod.v
data/verilator_xmls/c3a01cfa-7580-4d0b-bff8-9d6a42427d5a.xml
module divmod
#(parameter WIDTH = 32)
(
    input   wire    [(WIDTH-1):0]  q,
    input   wire    [(WIDTH-1):0]  b,
    input   wire    [(WIDTH-1):0]  r,


    output  wire    [(WIDTH-1):0]  ro,
    output  wire    [(WIDTH-1):0]  qo
);




wire [(WIDTH-1):0] next = {r[(WIDTH-2):0], q[WIDTH-1]};
wire [ WIDTH   :0] subt = next - b;


assign ro = subt[WIDTH] ? next : subt[(WIDTH-1):0];


assign qo = {q[(WIDTH-2):0], ~subt[WIDTH]};

endmodule
module divmod
#(parameter WIDTH = 32)
(
    input   wire    [(WIDTH-1):0]  q,
    input   wire    [(WIDTH-1):0]  b,
    input   wire    [(WIDTH-1):0]  r,


    output  wire    [(WIDTH-1):0]  ro,
    output  wire    [(WIDTH-1):0]  qo
);





wire [(WIDTH-1):0] next = {r[(WIDTH-2):0], q[WIDTH-1]};
wire [ WIDTH   :0] subt = next - b;


assign ro = subt[WIDTH] ? next : subt[(WIDTH-1):0];


assign qo = {q[(WIDTH-2):0], ~subt[WIDTH]};

endmodule