data/full_repos/permissive/488093047/Verilog Codes/AdderSubSign.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/AdderSubSign.v\n%Error: Exiting due to 3 error(s)\n'
module AdderSubSign #(parameter N=32)(A,B,C,S,O);
input wire [N-1:0]A,B;
output wire [N-1:0]C;
wire k;
input S;
output O;
wire [N+1:0]Cin;

assign Cin[0]=S;
genvar i;
generate
for(i=0;i<N;i=i+1) begin:FullAdder
FullAdder DUT_1(.A(A[i]),.B(B[i]^S),.C(Cin[i]),.Cout(Cin[i+1]),.Sum(C[i]));

end
endgenerate


xor DUT3(O,Cin[N],Cin[N-1]);
endmodule
module AdderSubSign #(parameter N=32)(A,B,C,S,O);

input wire [N-1:0]A,B;
output wire [N-1:0]C;
wire k;
input S;
output O;
wire [N+1:0]Cin;

assign Cin[0]=S;
genvar i;
generate
for(i=0;i<N;i=i+1) begin:FullAdder
FullAdder DUT_1(.A(A[i]),.B(B[i]^S),.C(Cin[i]),.Cout(Cin[i+1]),.Sum(C[i]));

end
endgenerate


xor DUT3(O,Cin[N],Cin[N-1]);
endmodule