data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMCH_STATEMACHINE.v
data/verilator_xmls/6ae61f6c-00e8-47aa-b69e-25d0b58455ad.xml
module MEMCH_STATEMACHINE  (


MEMCH_STATEMACHINE_Clk,
MEMCH_STATEMACHINE_Reset,
MEMCH_STATEMACHINE_Start,
MEMCH_STATEMACHINE_New_Channel_Flag,
MEMCH_STATEMACHINE_In_Output_Routine,

MEMCH_STATEMACHINE_Counter_Ch_Clr,
MEMCH_STATEMACHINE_Chmem1_Clr,
MEMCH_STATEMACHINE_Chmem2_Clr,
MEMCH_STATEMACHINE_Chmem3_Clr,
MEMCH_STATEMACHINE_Counter_En

);






localparam State_reset 		= 0;
localparam State_started 	= 1;
localparam State_Wait		= 2;
localparam State_Newch		= 3;





input MEMCH_STATEMACHINE_Clk;
input MEMCH_STATEMACHINE_Reset;
input MEMCH_STATEMACHINE_Start;
input MEMCH_STATEMACHINE_New_Channel_Flag;
input MEMCH_STATEMACHINE_In_Output_Routine;
output reg MEMCH_STATEMACHINE_Counter_Ch_Clr;
output reg MEMCH_STATEMACHINE_Chmem1_Clr;
output reg MEMCH_STATEMACHINE_Chmem2_Clr;
output reg MEMCH_STATEMACHINE_Chmem3_Clr;
output reg MEMCH_STATEMACHINE_Counter_En;



reg [1:0] State_Register;
reg [1:0] State_Signal;


always @(*)
begin
	case (State_Register)
		
		State_reset: if(MEMCH_STATEMACHINE_Start)
							State_Signal=State_started;
						 else
							State_Signal=State_reset;
	   
		State_started: if(!MEMCH_STATEMACHINE_Reset)
								State_Signal=State_reset;
							else if (MEMCH_STATEMACHINE_New_Channel_Flag)
								State_Signal=State_Wait;
							else
								State_Signal=State_started;
								
		State_Wait: if(!MEMCH_STATEMACHINE_In_Output_Routine)	
							State_Signal=State_Newch;
						else
							State_Signal=State_Wait;
		
		State_Newch:State_Signal=State_started;
		
		default : State_Signal = State_reset;
		
	endcase
	
end



always @ (negedge MEMCH_STATEMACHINE_Clk , negedge MEMCH_STATEMACHINE_Reset)
begin
	if (!MEMCH_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end



always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 0;
			MEMCH_STATEMACHINE_Chmem1_Clr = 0;
			MEMCH_STATEMACHINE_Chmem2_Clr = 0;
			MEMCH_STATEMACHINE_Chmem3_Clr = 0;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_started:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_Wait:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_Newch:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 1;
		end
		
		
		default:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 0;
			MEMCH_STATEMACHINE_Chmem1_Clr = 0;
			MEMCH_STATEMACHINE_Chmem2_Clr = 0;
			MEMCH_STATEMACHINE_Chmem3_Clr = 0;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
	
	endcase

end


endmodule
module MEMCH_STATEMACHINE  (


MEMCH_STATEMACHINE_Clk,
MEMCH_STATEMACHINE_Reset,
MEMCH_STATEMACHINE_Start,
MEMCH_STATEMACHINE_New_Channel_Flag,
MEMCH_STATEMACHINE_In_Output_Routine,

MEMCH_STATEMACHINE_Counter_Ch_Clr,
MEMCH_STATEMACHINE_Chmem1_Clr,
MEMCH_STATEMACHINE_Chmem2_Clr,
MEMCH_STATEMACHINE_Chmem3_Clr,
MEMCH_STATEMACHINE_Counter_En

);







localparam State_reset 		= 0;
localparam State_started 	= 1;
localparam State_Wait		= 2;
localparam State_Newch		= 3;





input MEMCH_STATEMACHINE_Clk;
input MEMCH_STATEMACHINE_Reset;
input MEMCH_STATEMACHINE_Start;
input MEMCH_STATEMACHINE_New_Channel_Flag;
input MEMCH_STATEMACHINE_In_Output_Routine;
output reg MEMCH_STATEMACHINE_Counter_Ch_Clr;
output reg MEMCH_STATEMACHINE_Chmem1_Clr;
output reg MEMCH_STATEMACHINE_Chmem2_Clr;
output reg MEMCH_STATEMACHINE_Chmem3_Clr;
output reg MEMCH_STATEMACHINE_Counter_En;



reg [1:0] State_Register;
reg [1:0] State_Signal;


always @(*)
begin
	case (State_Register)
		
		State_reset: if(MEMCH_STATEMACHINE_Start)
							State_Signal=State_started;
						 else
							State_Signal=State_reset;
	   
		State_started: if(!MEMCH_STATEMACHINE_Reset)
								State_Signal=State_reset;
							else if (MEMCH_STATEMACHINE_New_Channel_Flag)
								State_Signal=State_Wait;
							else
								State_Signal=State_started;
								
		State_Wait: if(!MEMCH_STATEMACHINE_In_Output_Routine)	
							State_Signal=State_Newch;
						else
							State_Signal=State_Wait;
		
		State_Newch:State_Signal=State_started;
		
		default : State_Signal = State_reset;
		
	endcase
	
end



always @ (negedge MEMCH_STATEMACHINE_Clk , negedge MEMCH_STATEMACHINE_Reset)
begin
	if (!MEMCH_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end



always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 0;
			MEMCH_STATEMACHINE_Chmem1_Clr = 0;
			MEMCH_STATEMACHINE_Chmem2_Clr = 0;
			MEMCH_STATEMACHINE_Chmem3_Clr = 0;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_started:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_Wait:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
		
		State_Newch:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 1;
			MEMCH_STATEMACHINE_Chmem1_Clr = 1;
			MEMCH_STATEMACHINE_Chmem2_Clr = 1;
			MEMCH_STATEMACHINE_Chmem3_Clr = 1;
			MEMCH_STATEMACHINE_Counter_En = 1;
		end
		
		
		default:
		begin
			MEMCH_STATEMACHINE_Counter_Ch_Clr = 0;
			MEMCH_STATEMACHINE_Chmem1_Clr = 0;
			MEMCH_STATEMACHINE_Chmem2_Clr = 0;
			MEMCH_STATEMACHINE_Chmem3_Clr = 0;
			MEMCH_STATEMACHINE_Counter_En = 0;
		end
	
	endcase

end


endmodule