data/full_repos/permissive/41643185/system.v
1: b"%Error: data/full_repos/permissive/41643185/system.v:439: Cannot find file containing module: 'reg8'\n reg8 counthrreg0(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/41643185,data/full_repos/permissive/41643185/reg8\n             data/full_repos/permissive/41643185,data/full_repos/permissive/41643185/reg8.v\n             data/full_repos/permissive/41643185,data/full_repos/permissive/41643185/reg8.sv\n             reg8\n             reg8.v\n             reg8.sv\n             obj_dir/reg8\n             obj_dir/reg8.v\n             obj_dir/reg8.sv\n%Error: data/full_repos/permissive/41643185/system.v:446: Cannot find file containing module: 'reg8'\n reg8 counthrreg1(\n ^~~~\n%Error: data/full_repos/permissive/41643185/system.v:452: Cannot find file containing module: 'reg8'\n reg8 counthrreg2(\n ^~~~\n%Error: data/full_repos/permissive/41643185/system.v:458: Cannot find file containing module: 'control'\n control ctrl0(\n ^~~~~~~\n%Error: data/full_repos/permissive/41643185/system.v:493: Cannot find file containing module: 'bdcmotorchannel'\n bdcmotorchannel bdcm0(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/41643185/system.v:512: Cannot find file containing module: 'bdcmotorchannel'\n bdcmotorchannel bdcm1(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/41643185/system.v:531: Cannot find file containing module: 'bdcmotorchannel'\n bdcmotorchannel bdcm2(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/41643185/system.v:549: Cannot find file containing module: 'digitalfilter'\n digitalfilter spienfilter(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/41643185/system.v:555: Cannot find file containing module: 'spi'\n spi spi0(\n ^~~\n%Error: Exiting due to 9 error(s)\n"
module freezer(
	input clk,
	input countlread,
	output freeze,
	output highce);
  
	reg highcereg;
	reg [4:0] sr = 5'b00000;
  
	assign highce = highcereg;
	assign freeze = sr[2];
  
	always @(*) begin
		highcereg = 0;
		if((sr[3] == 1) && (sr[4] == 0))
			highcereg = 1;
	end
  
	always @(posedge clk) begin
		sr[4] <= sr[3];
		sr[3] <= sr[2];
		sr[2] <= sr[1];
		sr[1] <= sr[0];
		sr[0] <= countlread;
	end
endmodule
module freezer(
	input clk,
	input countlread,
	output freeze,
	output highce);

  
	reg highcereg;
	reg [4:0] sr = 5'b00000;
  
	assign highce = highcereg;
	assign freeze = sr[2];
  
	always @(*) begin
		highcereg = 0;
		if((sr[3] == 1) && (sr[4] == 0))
			highcereg = 1;
	end
  
	always @(posedge clk) begin
		sr[4] <= sr[3];
		sr[3] <= sr[2];
		sr[2] <= sr[1];
		sr[1] <= sr[0];
		sr[0] <= countlread;
	end
endmodule