data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv
1: b'%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:1: Unsupported: classes\nclass processor_subscriber extends uvm_subscriber #(processor_transaction);\n^~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass processor_subscriber extends uvm_subscriber #(processor_transaction);\n                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:3: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(processor_subscriber)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\ncovergroup cover_processor;\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:8: syntax error, unexpected IDENTIFIER\ncovergroup cover_processor;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\ncoverpoint instruction\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Addition = {[16\'h0000:16\'h0FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Subraction = {[16\'h1000:16\'h1FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Increment = {[16\'h3000:16\'h3FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Decrement = {[16\'h2000:16\'h2FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins AND_NAND = {[16\'h4000:16\'h4FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins OR_NOR = {[16\'h5000:16\'h5FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins EXOR_EXNOR = {[16\'h6000:16\'h6FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Buff_Inv = {[16\'h7000:16\'h7FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Multiplication = {[16\'h8000:16\'h8FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins ShiftL_ShiftR = {[16\'hC000:16\'hCFFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Load = {[16\'hA000:16\'hAFFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Store = {[16\'hB000:16\'hBFFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Move_MoveI = {[16\'h9000:16\'h9FFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins Jump = {[16\'hD000:16\'hDFFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nbins NOP = {[16\'hE000:16\'hEFFF]};\n^~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:28: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\nendgroup\n^~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:30: Unsupported: virtual data type\nvirtual processor_interface processor_vif;\n^~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:32: syntax error, unexpected IDENTIFIER\nuvm_analysis_imp #(processor_transaction,processor_subscriber) aport;\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:35: Unsupported: new constructor\n  function new (string name, uvm_component parent);\n           ^~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:35: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function new (string name, uvm_component parent);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void build_phase(uvm_phase phase);\n                                      ^~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:46: Unsupported: virtual data type\nif(!uvm_config_db#(virtual processor_interface)::get(this, "",\n                   ^~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:48: Define or directive not defined: \'`uvm_error\'\n                                                                                                                : ... Suggested alternative: \'`error\'\n`uvm_error("", "uvm_config_db::get failed")\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/processor_subscriber.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void write(processor_transaction t);\n                                          ^\n%Error: Exiting due to 30 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function new (string name, uvm_component parent);
  begin
    super.new(name,parent);


	cover_processor = new();
  end
  endfunction
function new (string name, uvm_component parent);

  begin
    super.new(name,parent);


	cover_processor = new();
  end
  endfunction