data/full_repos/permissive/487568919/basic_verilog/example_projects/testbench_template_tb/edge_detect.sv
data/verilator_xmls/ea7b8101-a2ff-4530-be85-bf288de5569b.xml
module edge_detect #( parameter
  bit [0:0] REGISTER_OUTPUTS = 1'b0

)(
  input clk,
  input nrst,

  input in,
  output logic rising,
  output logic falling,
  output logic both
);


logic in_d = 0;
always_ff @(posedge clk) begin
  if ( ~nrst ) begin
    in_d <= 0;
  end else begin
    in_d <= in;
  end
end

logic rising_comb;
logic falling_comb;
logic both_comb;
always_comb begin
  rising_comb = nrst && (in && ~in_d);
  falling_comb = nrst && (~in && in_d);
  both_comb = nrst && (rising_comb || falling_comb);
end

generate
  if( REGISTER_OUTPUTS=='0 ) begin


    always_comb begin
      rising = rising_comb;
      falling = falling_comb;
      both = both_comb;
    end

  end else begin


    always_ff @(posedge clk) begin
      if( ~nrst ) begin
        rising <= 0;
        falling <= 0;
        both <= 0;
      end else begin
        rising <= rising_comb;
        falling <= falling_comb;
        both <= both_comb;
      end
    end

  end
endgenerate

endmodule
module edge_detect #( parameter
  bit [0:0] REGISTER_OUTPUTS = 1'b0

)(
  input clk,
  input nrst,

  input in,
  output logic rising,
  output logic falling,
  output logic both
);



logic in_d = 0;
always_ff @(posedge clk) begin
  if ( ~nrst ) begin
    in_d <= 0;
  end else begin
    in_d <= in;
  end
end

logic rising_comb;
logic falling_comb;
logic both_comb;
always_comb begin
  rising_comb = nrst && (in && ~in_d);
  falling_comb = nrst && (~in && in_d);
  both_comb = nrst && (rising_comb || falling_comb);
end

generate
  if( REGISTER_OUTPUTS=='0 ) begin


    always_comb begin
      rising = rising_comb;
      falling = falling_comb;
      both = both_comb;
    end

  end else begin


    always_ff @(posedge clk) begin
      if( ~nrst ) begin
        rising <= 0;
        falling <= 0;
        both <= 0;
      end else begin
        rising <= rising_comb;
        falling <= falling_comb;
        both <= both_comb;
      end
    end

  end
endgenerate

endmodule