data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output reg wbs_ack_o,
    output reg [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    
wire clk;
wire rst;

wire ring_Osc_Output;
wire xor_out_sampledROs;
wire xor_out_analogROs;
wire rng_out_sampled_ROs;
wire rng_out_analog_ROs;
wire figaro_Osc_Output;
wire xor_out_sampledFIGAROs;
wire xor_out_analogFIGAROs;
wire rng_out_sampled_FIGAROs;
wire rng_out_analog_FIGAROs;

wire [11:0]probe ;
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_dat_o <= 32'h0;
		end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
			case(wbs_adr_i[7:0])
				8'h04	: wbs_dat_o <= {20'b0,probe};
				default	: wbs_dat_o <= 32'h0;
			endcase
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_ack_o <= 1'b0;
		end else begin
			wbs_ack_o <= (wbs_stb_i && wbs_cyc_i);
		end
	end
 

    assign irq = 3'b000;

    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};






    assign probe[0] = clk;
    assign probe[1] = ring_Osc_Output;
    assign probe[2] = xor_out_sampledROs;
    assign probe[3] = xor_out_analogROs;
    assign probe[4] = rng_out_sampled_ROs;
    assign probe[5] = rng_out_analog_ROs;
    assign probe[6] = clk;
    assign probe[7] = figaro_Osc_Output;
    assign probe[8] = xor_out_sampledFIGAROs;
    assign probe[9] = xor_out_analogFIGAROs;
    assign probe[10] = rng_out_sampled_FIGAROs;
    assign probe[11] = rng_out_analog_FIGAROs;

    assign io_out[11:0] = probe;
    assign io_out[19:12] = 8'b0;
    assign io_out[31:20] = probe;


    assign la_data_out[11:0] = probe;
    assign la_data_out[31:12] = 20'b0;
    assign la_data_out[43:32] = probe;

    assign la_data_out[127:44] = 84'b0;


    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;

    
    entropy_RO entropy_RO(
        .clk_dff               (clk),
        .o_RO_out              (ring_Osc_Output),
        .o_xor_out_ROs_sampled (xor_out_sampledROs),
        .o_xor_out_ROs_analog  (xor_out_analogROs)
    );
        
    mydff dff_last_sampledRO(.clk(clk), .D(xor_out_sampledROs), .Q(rng_out_sampled_ROs));
    mydff dff_last_analogRO (.clk(clk), .D(xor_out_analogROs) , .Q(rng_out_analog_ROs));

    entropy_FIGARO entropy_FIGARO(
        .clk_dff               (clk),
        .o_FIGARO_out           (figaro_Osc_Output),
        .o_xor_out_FIGAROs_analog   (xor_out_sampledFIGAROs),
        .o_xor_out_FIGAROs_sampled   (xor_out_analogFIGAROs));  

    mydff dff_last_sampledFIGARO(.clk(clk), .D(xor_out_sampledFIGAROs), .Q(rng_out_sampled_FIGAROs));
    mydff dff_last_analogFIGARO (.clk(clk), .D(xor_out_analogFIGAROs) , .Q(rng_out_analog_FIGAROs));
   
    

endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output reg wbs_ack_o,
    output reg [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


    
wire clk;
wire rst;

wire ring_Osc_Output;
wire xor_out_sampledROs;
wire xor_out_analogROs;
wire rng_out_sampled_ROs;
wire rng_out_analog_ROs;
wire figaro_Osc_Output;
wire xor_out_sampledFIGAROs;
wire xor_out_analogFIGAROs;
wire rng_out_sampled_FIGAROs;
wire rng_out_analog_FIGAROs;

wire [11:0]probe ;
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_dat_o <= 32'h0;
		end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
			case(wbs_adr_i[7:0])
				8'h04	: wbs_dat_o <= {20'b0,probe};
				default	: wbs_dat_o <= 32'h0;
			endcase
		end
	end
	

	always @(posedge wb_clk_i) begin 
		if (wb_rst_i) begin
			wbs_ack_o <= 1'b0;
		end else begin
			wbs_ack_o <= (wbs_stb_i && wbs_cyc_i);
		end
	end
 

    assign irq = 3'b000;

    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};






    assign probe[0] = clk;
    assign probe[1] = ring_Osc_Output;
    assign probe[2] = xor_out_sampledROs;
    assign probe[3] = xor_out_analogROs;
    assign probe[4] = rng_out_sampled_ROs;
    assign probe[5] = rng_out_analog_ROs;
    assign probe[6] = clk;
    assign probe[7] = figaro_Osc_Output;
    assign probe[8] = xor_out_sampledFIGAROs;
    assign probe[9] = xor_out_analogFIGAROs;
    assign probe[10] = rng_out_sampled_FIGAROs;
    assign probe[11] = rng_out_analog_FIGAROs;

    assign io_out[11:0] = probe;
    assign io_out[19:12] = 8'b0;
    assign io_out[31:20] = probe;


    assign la_data_out[11:0] = probe;
    assign la_data_out[31:12] = 20'b0;
    assign la_data_out[43:32] = probe;

    assign la_data_out[127:44] = 84'b0;


    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;

    
    entropy_RO entropy_RO(
        .clk_dff               (clk),
        .o_RO_out              (ring_Osc_Output),
        .o_xor_out_ROs_sampled (xor_out_sampledROs),
        .o_xor_out_ROs_analog  (xor_out_analogROs)
    );
        
    mydff dff_last_sampledRO(.clk(clk), .D(xor_out_sampledROs), .Q(rng_out_sampled_ROs));
    mydff dff_last_analogRO (.clk(clk), .D(xor_out_analogROs) , .Q(rng_out_analog_ROs));

    entropy_FIGARO entropy_FIGARO(
        .clk_dff               (clk),
        .o_FIGARO_out           (figaro_Osc_Output),
        .o_xor_out_FIGAROs_analog   (xor_out_sampledFIGAROs),
        .o_xor_out_FIGAROs_sampled   (xor_out_analogFIGAROs));  

    mydff dff_last_sampledFIGARO(.clk(clk), .D(xor_out_sampledFIGAROs), .Q(rng_out_sampled_FIGAROs));
    mydff dff_last_analogFIGARO (.clk(clk), .D(xor_out_analogFIGAROs) , .Q(rng_out_analog_FIGAROs));
   
    

endmodule