data/full_repos/permissive/423547971/FPGA Projects/Coffee Machine No 2(upgraded)/oneHz_gen.v
1: b'%Error: Cannot find file containing module: Projects/Coffee\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Coffee\n             data/full_repos/permissive/423547971/FPGA/Projects/Coffee.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Coffee.sv\n             Projects/Coffee\n             Projects/Coffee.v\n             Projects/Coffee.sv\n             obj_dir/Projects/Coffee\n             obj_dir/Projects/Coffee.v\n             obj_dir/Projects/Coffee.sv\n%Error: Cannot find file containing module: Machine\n%Error: Cannot find file containing module: No\n%Error: Cannot find file containing module: 2(upgraded),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: 2(upgraded)/oneHz_gen.v\n%Error: Exiting due to 6 error(s)\n'
module oneHz_gen(
    input clk_100MHz,
    input reset,
    output clk_1Hz
    );
    
    reg clk_1Hz_reg = 0;
    reg [25:0] counter_reg;
    
    always @(posedge clk_100MHz or posedge reset) begin
        if(reset)
            counter_reg <= 0;
        else
            if(counter_reg == 49_999_999) begin
                counter_reg <= 0;
                clk_1Hz_reg <= ~clk_1Hz_reg;
            end    
            else
                counter_reg <= counter_reg + 1;
    end
    
    assign clk_1Hz = clk_1Hz_reg;
    
endmodule
module oneHz_gen(
    input clk_100MHz,
    input reset,
    output clk_1Hz
    );

    
    reg clk_1Hz_reg = 0;
    reg [25:0] counter_reg;
    
    always @(posedge clk_100MHz or posedge reset) begin
        if(reset)
            counter_reg <= 0;
        else
            if(counter_reg == 49_999_999) begin
                counter_reg <= 0;
                clk_1Hz_reg <= ~clk_1Hz_reg;
            end    
            else
                counter_reg <= counter_reg + 1;
    end
    
    assign clk_1Hz = clk_1Hz_reg;
    
endmodule