data/full_repos/permissive/487110065/Halt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487110065/Halt.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'halt1\' generates 1 bits.\n                                                              : ... In instance Halt\n        haltTotal = halt1;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487110065/Halt.v:19: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'halt1\' generates 1 bits.\n                                                              : ... In instance Halt\n        haltTotal = halt1 + halt2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/487110065/Halt.v:19: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'halt2\' generates 1 bits.\n                                                              : ... In instance Halt\n        haltTotal = halt1 + halt2;\n                          ^\n%Error: Exiting due to 3 warning(s)\n'
module Halt(
    halt1,
    halt2,
    reseta,
    haltOut
);

input wire halt1;
input wire halt2;
input wire reseta;
integer haltTotal = 0;

output wire haltOut;

always @(*) begin
    if (reseta) begin
        haltTotal = halt1;
    end else begin
        haltTotal = halt1 + halt2;
    end
end

assign haltOut = (haltTotal > 0) ? 1'b1 : 1'b0;

endmodule
module Halt(
    halt1,
    halt2,
    reseta,
    haltOut
);


input wire halt1;
input wire halt2;
input wire reseta;
integer haltTotal = 0;

output wire haltOut;

always @(*) begin
    if (reseta) begin
        haltTotal = halt1;
    end else begin
        haltTotal = halt1 + halt2;
    end
end

assign haltOut = (haltTotal > 0) ? 1'b1 : 1'b0;

endmodule