data/full_repos/permissive/42434302/ivltests/pr841.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr841.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr841.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n      ^\n%Warning-INFINITELOOP: data/full_repos/permissive/42434302/ivltests/pr841.v:10: Infinite loop (condition always true)\n                                                                              : ... In instance err\n      #3 forever #10 clk=~clk;\n         ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pll (inclk0);
input  inclk0;

tri0 inclk0;

endmodule
module pll (inclk0);

input  inclk0;

tri0 inclk0;

endmodule