data/full_repos/permissive/421030651/src/peri/uart.sv
1: b'%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:1: Cannot find include file: clkdef.h\n`include "clkdef.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h.v\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h.sv\n             clkdef.h\n             clkdef.h.v\n             clkdef.h.sv\n             obj_dir/clkdef.h\n             obj_dir/clkdef.h.v\n             obj_dir/clkdef.h.sv\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:2: Cannot find include file: uart_define.h\n`include "uart_define.h" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:3: Cannot find include file: uart_mmap.h\n`include "uart_mmap.h" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:26: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] tx_fifo_wdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:28: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] tx_fifo_rdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:33: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] rx_fifo_wdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:35: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] rx_fifo_rdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:59: Define or directive not defined: \'`UART_TXFIFO\'\nassign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];\n                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:59: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nassign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];\n                                                                        ^~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:60: Define or directive not defined: \'`UART_DATA_WIDTH\'\nassign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:106: Define or directive not defined: \'`UART_TXCTRL\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin\n                                                             ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:111: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:113: Define or directive not defined: \'`UART_RXFIFO\'\nassign rx_fifo_rd = apb_rd && s_apb_intf.paddr[11:0] == `UART_RXFIFO;\n                                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:146: Define or directive not defined: \'`UART_RXCTRL\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:146: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin\n                                                             ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:150: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:158: Define or directive not defined: \'`UART_IE\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IE) begin\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:171: Define or directive not defined: \'`UART_IC\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IC) begin\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:190: Define or directive not defined: \'`UART_DIV\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_DIV) begin\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:199: Define or directive not defined: \'`UART_LCR\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_LCR) begin\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:207: Define or directive not defined: \'`UART_TXFIFO\'\n        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31\'b0};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:207: syntax error, unexpected \':\', expecting endcase\n        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31\'b0};\n                    ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:208: Define or directive not defined: \'`UART_RXFIFO\'\n        `UART_RXFIFO: prdata_t = {rx_fifo_empty, 23\'b0, rx_fifo_rdata & {8{~rx_fifo_empty}}};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:209: Define or directive not defined: \'`UART_TXCTRL\'\n        `UART_TXCTRL: prdata_t = {13\'b0, txcnt, 14\'b0, nstop, txen};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:210: Define or directive not defined: \'`UART_RXCTRL\'\n        `UART_RXCTRL: prdata_t = {13\'b0, rxcnt, 14\'b0,  1\'b0, rxen};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:211: Define or directive not defined: \'`UART_IE\'\n        `UART_IE    : prdata_t = {29\'b0, perror_ie, rxwm_ie, txwm_ie};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:212: Define or directive not defined: \'`UART_IP\'\n        `UART_IP    : prdata_t = {29\'b0, perror_ip, rxwm_ip, txwm_ip};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:213: Define or directive not defined: \'`UART_IC\'\n        `UART_IC    : prdata_t = {29\'b0, perror_ip, rxwm_ip, txwm_ip};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:214: Define or directive not defined: \'`UART_DIV\'\n        `UART_DIV   : prdata_t = {16\'b0, div};\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:215: Define or directive not defined: \'`UART_LCR\'\n        `UART_LCR   : prdata_t = {26\'b0, lcr, 3\'b0};\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:237: Define or directive not defined: \'`UART_DATA_WIDTH\'\n    input        [`UART_DATA_WIDTH-1:0] wdata,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:239: Define or directive not defined: \'`UART_DATA_WIDTH\'\n    output logic [`UART_DATA_WIDTH-1:0] rdata,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:248: Define or directive not defined: \'`UART_FIFO_DEPTH\'\nlocalparam PTR_WIDTH = $clog2(`UART_FIFO_DEPTH);\n                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:248: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nlocalparam PTR_WIDTH = $clog2(`UART_FIFO_DEPTH);\n                                              ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:250: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] fifo [`UART_FIFO_DEPTH];\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:250: Define or directive not defined: \'`UART_FIFO_DEPTH\'\nlogic [`UART_DATA_WIDTH-1:0] fifo [`UART_FIFO_DEPTH];\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: Define or directive not defined: \'`UART_FIFO_DEPTH\'\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                                        ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: syntax error, unexpected \')\', expecting \';\'\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                                                   ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:278: Define or directive not defined: \'`UART_DATA_WIDTH\'\n            fifo[i] <= `UART_DATA_WIDTH\'b0;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:281: syntax error, unexpected else\n    else begin\n    ^~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:433: Define or directive not defined: \'`UART_N_SYNC\'\nlogic [`UART_N_SYNC-1:0] uart_tx_dly;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:446: Define or directive not defined: \'`UART_N_SYNC\'\n    if (~rstn) uart_tx_dly <= `UART_N_SYNC\'b0;\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:447: Define or directive not defined: \'`UART_N_SYNC\'\n    else       uart_tx_dly <= {uart_rx, uart_tx_dly[`UART_N_SYNC-1:1]};\n                                                    ^~~~~~~~~~~~\n%Error: Exiting due to 45 error(s)\n'
module tx_ctrl (
    input               clk,
    input               rstn,
    input               enable,
    input        [ 2:0] lcr,
    input               nstop,
    input        [15:0] div,
    input               data_vld,
    input        [ 7:0] data_in,
    output logic        pop,
    output logic        uart_tx
);

localparam STATE_IDLE   = 3'b000;
localparam STATE_START  = 3'b001;
localparam STATE_DATA   = 3'b010;
localparam STATE_PARITY = 3'b011;
localparam STATE_STOP   = 3'b100;

logic [ 2:0] cur_state;
logic [ 2:0] nxt_state;

logic [15:0] cnt;
logic [15:0] rept;
logic [15:0] nxt_rept;
logic        uart_tx_tmp;
logic [ 7:0] data_sft;
logic        data_par;

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) cur_state <= STATE_IDLE;
    else       cur_state <= nxt_state;
end

always_comb begin
    nxt_state = cur_state;
    case (cur_state)
        STATE_IDLE  : nxt_state = enable && data_vld ? STATE_START : STATE_IDLE;
        STATE_START : nxt_state = ~|cnt ? STATE_DATA : STATE_START;
        STATE_DATA  : nxt_state = ~|cnt && ~|rept ? lcr[0] ? STATE_PARITY : STATE_STOP : STATE_DATA;
        STATE_PARITY: nxt_state = ~|cnt ? STATE_STOP : STATE_PARITY;
        STATE_STOP  : nxt_state = ~|cnt && ~|rept ? STATE_IDLE : STATE_STOP;
    endcase
end

always_comb begin
    nxt_rept    = 16'b0;
    uart_tx_tmp = 1'b1;
    pop         = 1'b0;
    case (cur_state)
        STATE_IDLE  : begin
            nxt_rept    = 16'b0;
            uart_tx_tmp = 1'b1;
            pop         = enable && data_vld;
        end
        STATE_START : begin
            nxt_rept    = 16'h7;
            uart_tx_tmp = 1'b0;
        end
        STATE_DATA  : begin
            nxt_rept    = nxt_state == STATE_PARITY ? 16'b0 : {15'b0, nstop};
            uart_tx_tmp = data_sft[0];
        end
        STATE_PARITY: begin
            nxt_rept    = {15'b0, nstop};
            uart_tx_tmp = data_par;
        end
        STATE_STOP  : begin
            uart_tx_tmp = 1'b1;
        end
    endcase
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) uart_tx <= 1'b1;
    else       uart_tx <= uart_tx_tmp;
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        data_sft <= 8'b0;
        data_par <= 1'b0;
    end
    else begin
        if (pop) begin
            data_sft <=  data_in;
            data_par <= ^data_in;
        end
        else if (cur_state == STATE_DATA && ~|cnt) begin
            data_sft <= {1'b0, data_sft[7:1]};
        end
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        cnt <= 16'b0;
    end
    else begin
        if (cur_state == STATE_IDLE) begin
            cnt <= div;
        end
        else begin
            cnt <= |cnt ? cnt - 16'b1 : div;
        end
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        rept <= 16'b0;
    end
    else begin
        if (~|cnt) begin
            rept <= |rept ? rept - 16'b1 : nxt_rept;
        end
    end
end

endmodule
module tx_ctrl (
    input               clk,
    input               rstn,
    input               enable,
    input        [ 2:0] lcr,
    input               nstop,
    input        [15:0] div,
    input               data_vld,
    input        [ 7:0] data_in,
    output logic        pop,
    output logic        uart_tx
);


localparam STATE_IDLE   = 3'b000;
localparam STATE_START  = 3'b001;
localparam STATE_DATA   = 3'b010;
localparam STATE_PARITY = 3'b011;
localparam STATE_STOP   = 3'b100;

logic [ 2:0] cur_state;
logic [ 2:0] nxt_state;

logic [15:0] cnt;
logic [15:0] rept;
logic [15:0] nxt_rept;
logic        uart_tx_tmp;
logic [ 7:0] data_sft;
logic        data_par;

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) cur_state <= STATE_IDLE;
    else       cur_state <= nxt_state;
end

always_comb begin
    nxt_state = cur_state;
    case (cur_state)
        STATE_IDLE  : nxt_state = enable && data_vld ? STATE_START : STATE_IDLE;
        STATE_START : nxt_state = ~|cnt ? STATE_DATA : STATE_START;
        STATE_DATA  : nxt_state = ~|cnt && ~|rept ? lcr[0] ? STATE_PARITY : STATE_STOP : STATE_DATA;
        STATE_PARITY: nxt_state = ~|cnt ? STATE_STOP : STATE_PARITY;
        STATE_STOP  : nxt_state = ~|cnt && ~|rept ? STATE_IDLE : STATE_STOP;
    endcase
end

always_comb begin
    nxt_rept    = 16'b0;
    uart_tx_tmp = 1'b1;
    pop         = 1'b0;
    case (cur_state)
        STATE_IDLE  : begin
            nxt_rept    = 16'b0;
            uart_tx_tmp = 1'b1;
            pop         = enable && data_vld;
        end
        STATE_START : begin
            nxt_rept    = 16'h7;
            uart_tx_tmp = 1'b0;
        end
        STATE_DATA  : begin
            nxt_rept    = nxt_state == STATE_PARITY ? 16'b0 : {15'b0, nstop};
            uart_tx_tmp = data_sft[0];
        end
        STATE_PARITY: begin
            nxt_rept    = {15'b0, nstop};
            uart_tx_tmp = data_par;
        end
        STATE_STOP  : begin
            uart_tx_tmp = 1'b1;
        end
    endcase
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) uart_tx <= 1'b1;
    else       uart_tx <= uart_tx_tmp;
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        data_sft <= 8'b0;
        data_par <= 1'b0;
    end
    else begin
        if (pop) begin
            data_sft <=  data_in;
            data_par <= ^data_in;
        end
        else if (cur_state == STATE_DATA && ~|cnt) begin
            data_sft <= {1'b0, data_sft[7:1]};
        end
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        cnt <= 16'b0;
    end
    else begin
        if (cur_state == STATE_IDLE) begin
            cnt <= div;
        end
        else begin
            cnt <= |cnt ? cnt - 16'b1 : div;
        end
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        rept <= 16'b0;
    end
    else begin
        if (~|cnt) begin
            rept <= |rept ? rept - 16'b1 : nxt_rept;
        end
    end
end

endmodule