data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/FIFO.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/FIFO.v:88: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'FIFO_Rdinc\' generates 1 bits.\n                                                                                                                 : ... In instance FIFO\n   Rdptr<=Rdptr+FIFO_Rdinc;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/FIFO.v:101: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                  : ... In instance FIFO\n   Wrptr<=1\'b0;\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module FIFO #(parameter DATA_WIDTH=16, parameter FIFO_SIZE= 720, parameter ADDR_WIDTH=10)(


FIFO_Clk_1,
FIFO_Clk_2,
FIFO_Rdptclr,
FIFO_Wrptclr,
FIFO_Rdinc,
FIFO_Wrinc,
FIFO_Wen,
FIFO_Ren,
FIFO_Data_in,

FIFO_Data_out
);




input FIFO_Clk_1;
input FIFO_Clk_2;
input FIFO_Rdptclr; 
input FIFO_Wrptclr; 
input FIFO_Rdinc;
input FIFO_Wrinc;
input FIFO_Wen;
input FIFO_Ren;
input [DATA_WIDTH-1:0] FIFO_Data_in;
output [DATA_WIDTH-1:0] FIFO_Data_out;
 



reg [DATA_WIDTH-1:0] Fifo_Array[0:FIFO_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Qtemp;

reg reg_we;
reg reg_re;






always@(*)
begin
	reg_we=FIFO_Wen;
	reg_re=FIFO_Ren;

end

always@(posedge FIFO_Clk_1 or negedge FIFO_Rdptclr)
begin
	
	if(!FIFO_Rdptclr)
		begin
			Rdptr<=0;
		end
	
	else if(reg_re)
		begin
			Qtemp<=Fifo_Array[Rdptr];
			Rdptr<=Rdptr+FIFO_Rdinc;
		end		
	else
		Qtemp<=0;
	
end


always@(posedge FIFO_Clk_2 or negedge FIFO_Wrptclr)
begin
	
	if(!FIFO_Wrptclr)
		begin
			Wrptr<=1'b0;
		end
	
	else if(reg_we)
		begin
			Fifo_Array[Wrptr]<=FIFO_Data_in;
			Wrptr<=Wrptr+1'b1;
		end
end





assign FIFO_Data_out=Qtemp;


endmodule
module FIFO #(parameter DATA_WIDTH=16, parameter FIFO_SIZE= 720, parameter ADDR_WIDTH=10)(


FIFO_Clk_1,
FIFO_Clk_2,
FIFO_Rdptclr,
FIFO_Wrptclr,
FIFO_Rdinc,
FIFO_Wrinc,
FIFO_Wen,
FIFO_Ren,
FIFO_Data_in,

FIFO_Data_out
);





input FIFO_Clk_1;
input FIFO_Clk_2;
input FIFO_Rdptclr; 
input FIFO_Wrptclr; 
input FIFO_Rdinc;
input FIFO_Wrinc;
input FIFO_Wen;
input FIFO_Ren;
input [DATA_WIDTH-1:0] FIFO_Data_in;
output [DATA_WIDTH-1:0] FIFO_Data_out;
 



reg [DATA_WIDTH-1:0] Fifo_Array[0:FIFO_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Qtemp;

reg reg_we;
reg reg_re;






always@(*)
begin
	reg_we=FIFO_Wen;
	reg_re=FIFO_Ren;

end

always@(posedge FIFO_Clk_1 or negedge FIFO_Rdptclr)
begin
	
	if(!FIFO_Rdptclr)
		begin
			Rdptr<=0;
		end
	
	else if(reg_re)
		begin
			Qtemp<=Fifo_Array[Rdptr];
			Rdptr<=Rdptr+FIFO_Rdinc;
		end		
	else
		Qtemp<=0;
	
end


always@(posedge FIFO_Clk_2 or negedge FIFO_Wrptclr)
begin
	
	if(!FIFO_Wrptclr)
		begin
			Wrptr<=1'b0;
		end
	
	else if(reg_we)
		begin
			Fifo_Array[Wrptr]<=FIFO_Data_in;
			Wrptr<=Wrptr+1'b1;
		end
end





assign FIFO_Data_out=Qtemp;


endmodule