data/full_repos/permissive/503973366/RTL/Convolution/MMU/GEMM.v
1: b"%Error: data/full_repos/permissive/503973366/RTL/Convolution/MMU/GEMM.v:80: Cannot find file containing module: 'Top_GLB'\n    Top_GLB #(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503973366/RTL/Convolution/MMU,data/full_repos/permissive/503973366/Top_GLB\n             data/full_repos/permissive/503973366/RTL/Convolution/MMU,data/full_repos/permissive/503973366/Top_GLB.v\n             data/full_repos/permissive/503973366/RTL/Convolution/MMU,data/full_repos/permissive/503973366/Top_GLB.sv\n             Top_GLB\n             Top_GLB.v\n             Top_GLB.sv\n             obj_dir/Top_GLB\n             obj_dir/Top_GLB.v\n             obj_dir/Top_GLB.sv\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/MMU/GEMM.v:122: Cannot find file containing module: 'SA'\n    SA #(\n    ^~\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/MMU/GEMM.v:148: Cannot find file containing module: 'ACC_v2'\n    ACC_v2 #(\n    ^~~~~~\n%Error: data/full_repos/permissive/503973366/RTL/Convolution/MMU/GEMM.v:170: Cannot find file containing module: 'SA_Data_mover_v2'\n    SA_Data_mover_v2 #(\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module GEMM #(

    parameter DATA_WIDTH    = 8,
    parameter PSUM_WIDTH    = 32,
    

    parameter PE_SIZE       = 14,


    parameter SLICING_IDX   = 32,


    parameter OUT_CH        = 64,


    parameter WEIGHT_COL_NUM   = 294,
    parameter WEIGHT_ROW_NUM   = 70,
    

    parameter MEM0_DEPTH       = 4116,
    parameter MEM0_DATA_WIDTH  = 112,
    parameter MEM0_ADDR_WIDTH  = 13,

    parameter MEM1_DEPTH       = 1470,
    parameter MEM1_DATA_WIDTH  = 112,
    parameter MEM1_ADDR_WIDTH  = 11,

    parameter MEM2_DEPTH        = 896,
    parameter MEM2_DATA_WIDTH   = 112,
    parameter MEM2_ADDR_WIDTH   = 10
    )
    (

    

    input clk,
    input rst_n,
    

    input gemm_start_i,
    

    output                          mem0_ce0,  
    output                          mem0_we0,  
    output  [MEM0_ADDR_WIDTH-1:0]   mem0_addr0,
    input   [MEM0_DATA_WIDTH-1:0]   mem0_q0_i, 
    

    output                          mem1_ce0,  
    output                          mem1_we0,  
    output  [MEM1_ADDR_WIDTH-1:0]   mem1_addr0,
    input   [MEM1_DATA_WIDTH-1:0]   mem1_q0_i, 


    output                          mem2_ce0,
    output                          mem2_we0,
    output  [MEM2_ADDR_WIDTH-1:0]   mem2_addr0,
    output  [MEM2_DATA_WIDTH-1:0]   mem2_d0,

    output                          finish_o
    );
    
    
    

    wire    [MEM0_DATA_WIDTH-1:0]       ifmap_row_w;
    wire                                ifmap_valid_w;
    wire    [MEM1_DATA_WIDTH-1:0]       weight_col_w;
    wire    [PE_SIZE-1:0]               weight_en_col_w;
        
    wire    [PSUM_WIDTH*PE_SIZE-1:0]    psum_row_w;
    wire    [PE_SIZE-1:0]               psum_en_row_w;
    
    wire    [PE_SIZE-1:0]               rden_w;
    wire    [MEM0_DATA_WIDTH-1:0]       ofmap_row_w;
    wire                                ofmap_valid_w;
    
    
    
    Top_GLB #(
        .FIFO_DATA_WIDTH    ( DATA_WIDTH      ),
        .PE_SIZE            ( PE_SIZE         ),
        .MEM0_DEPTH         ( MEM0_DEPTH      ),
        .MEM1_DEPTH         ( MEM1_DEPTH      ),
        .MEM0_ADDR_WIDTH    ( MEM0_ADDR_WIDTH ),
        .MEM1_ADDR_WIDTH    ( MEM1_ADDR_WIDTH ),
        .MEM0_DATA_WIDTH    ( MEM0_DATA_WIDTH ),
        .MEM1_DATA_WIDTH    ( MEM1_DATA_WIDTH ),
        .WEIGHT_ROW_NUM     ( WEIGHT_ROW_NUM  ),
        .WEIGHT_COL_NUM     ( WEIGHT_COL_NUM  )
    ) u_Top_GLB (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .en                 ( gemm_start_i  ),

        .mem0_ce0           ( mem0_ce0      ),
        .mem0_we0           ( mem0_we0      ),
        .mem0_addr0         ( mem0_addr0    ),

        .mem0_q0_i          ( mem0_q0_i     ),

        .mem1_ce0           ( mem1_ce0      ),
        .mem1_we0           ( mem1_we0      ),
        .mem1_addr0         ( mem1_addr0    ),

        .mem1_q0_i          ( mem1_q0_i     ),

        .mem0_q0_o          ( ifmap_row_w   ),
        .mem0_q0_vaild      ( ifmap_valid_w ),

        .rdata_o            ( weight_col_w  ),
        .weight_en_col_o    ( weight_en_col_w ),

        .sa_data_mover_en   ( )
    );




    SA #(
        .PE_SIZE            ( PE_SIZE ),
        .DATA_WIDTH         ( DATA_WIDTH ),
        .PSUM_WIDTH         ( PSUM_WIDTH )
    ) u_SA (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .ifmap_row_i        ( ifmap_row_w  ), 
        .weight_col_i       ( weight_col_w ), 
        .psum_row_i         ( {(PE_SIZE*PSUM_WIDTH){1'b0}} ),

        .ifmap_preload_i    ( ifmap_valid_w   ),
        .weight_en_col_i    ( weight_en_col_w ),
        .psum_en_row_i      ( weight_en_col_w ),

        .ifmap_row_o        ( ),
        .weight_col_o       ( ),
        .psum_row_o         ( psum_row_w ),

        .weight_en_col_o    ( ),
        .psum_en_row_o      ( psum_en_row_w )
    );


    ACC_v2 #(
        .PE_SIZE        ( PE_SIZE ),
        .DATA_WIDTH     ( DATA_WIDTH ),
        .PSUM_WIDTH     ( PSUM_WIDTH ),
        .SLICING_IDX    ( SLICING_IDX ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_v2(

        .clk            ( clk            ),
        .rst_n          ( rst_n          ),

        .psum_en_row_i  ( psum_en_row_w  ),

        .psum_row_i     ( psum_row_w     ),
        .ofmap_row_o    ( ofmap_row_w    ),
        .ofmap_valid_o  ( ofmap_valid_w  )
    );




    SA_Data_mover_v2 #(
        .FIFO_DATA_WIDTH    ( DATA_WIDTH      ),
        .PE_SIZE            ( PE_SIZE         ),
        .MEM0_DEPTH         ( MEM2_DEPTH      ),
        .MEM0_ADDR_WIDTH    ( MEM2_ADDR_WIDTH ),
        .MEM0_DATA_WIDTH    ( MEM2_DATA_WIDTH ),
        .OC                 ( OUT_CH          )
    ) u_SA_Data_mover (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .en                 ( ofmap_valid_w ),

        .rden_o             ( ),

        .rdata_i            ( ofmap_row_w ),

        .mem2_d0            ( mem2_d0     ),
        .mem2_addr0         ( mem2_addr0  ),
        .mem2_ce0           ( mem2_ce0    ),
        .mem2_we0           ( mem2_we0    ),
        .finish             ( finish_o    )
    );



endmodule
module GEMM #(

    parameter DATA_WIDTH    = 8,
    parameter PSUM_WIDTH    = 32,
    

    parameter PE_SIZE       = 14,


    parameter SLICING_IDX   = 32,


    parameter OUT_CH        = 64,


    parameter WEIGHT_COL_NUM   = 294,
    parameter WEIGHT_ROW_NUM   = 70,
    

    parameter MEM0_DEPTH       = 4116,
    parameter MEM0_DATA_WIDTH  = 112,
    parameter MEM0_ADDR_WIDTH  = 13,

    parameter MEM1_DEPTH       = 1470,
    parameter MEM1_DATA_WIDTH  = 112,
    parameter MEM1_ADDR_WIDTH  = 11,

    parameter MEM2_DEPTH        = 896,
    parameter MEM2_DATA_WIDTH   = 112,
    parameter MEM2_ADDR_WIDTH   = 10
    )
    (

    

    input clk,
    input rst_n,
    

    input gemm_start_i,
    

    output                          mem0_ce0,  
    output                          mem0_we0,  
    output  [MEM0_ADDR_WIDTH-1:0]   mem0_addr0,
    input   [MEM0_DATA_WIDTH-1:0]   mem0_q0_i, 
    

    output                          mem1_ce0,  
    output                          mem1_we0,  
    output  [MEM1_ADDR_WIDTH-1:0]   mem1_addr0,
    input   [MEM1_DATA_WIDTH-1:0]   mem1_q0_i, 


    output                          mem2_ce0,
    output                          mem2_we0,
    output  [MEM2_ADDR_WIDTH-1:0]   mem2_addr0,
    output  [MEM2_DATA_WIDTH-1:0]   mem2_d0,

    output                          finish_o
    );

    
    
    

    wire    [MEM0_DATA_WIDTH-1:0]       ifmap_row_w;
    wire                                ifmap_valid_w;
    wire    [MEM1_DATA_WIDTH-1:0]       weight_col_w;
    wire    [PE_SIZE-1:0]               weight_en_col_w;
        
    wire    [PSUM_WIDTH*PE_SIZE-1:0]    psum_row_w;
    wire    [PE_SIZE-1:0]               psum_en_row_w;
    
    wire    [PE_SIZE-1:0]               rden_w;
    wire    [MEM0_DATA_WIDTH-1:0]       ofmap_row_w;
    wire                                ofmap_valid_w;
    
    
    
    Top_GLB #(
        .FIFO_DATA_WIDTH    ( DATA_WIDTH      ),
        .PE_SIZE            ( PE_SIZE         ),
        .MEM0_DEPTH         ( MEM0_DEPTH      ),
        .MEM1_DEPTH         ( MEM1_DEPTH      ),
        .MEM0_ADDR_WIDTH    ( MEM0_ADDR_WIDTH ),
        .MEM1_ADDR_WIDTH    ( MEM1_ADDR_WIDTH ),
        .MEM0_DATA_WIDTH    ( MEM0_DATA_WIDTH ),
        .MEM1_DATA_WIDTH    ( MEM1_DATA_WIDTH ),
        .WEIGHT_ROW_NUM     ( WEIGHT_ROW_NUM  ),
        .WEIGHT_COL_NUM     ( WEIGHT_COL_NUM  )
    ) u_Top_GLB (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .en                 ( gemm_start_i  ),

        .mem0_ce0           ( mem0_ce0      ),
        .mem0_we0           ( mem0_we0      ),
        .mem0_addr0         ( mem0_addr0    ),

        .mem0_q0_i          ( mem0_q0_i     ),

        .mem1_ce0           ( mem1_ce0      ),
        .mem1_we0           ( mem1_we0      ),
        .mem1_addr0         ( mem1_addr0    ),

        .mem1_q0_i          ( mem1_q0_i     ),

        .mem0_q0_o          ( ifmap_row_w   ),
        .mem0_q0_vaild      ( ifmap_valid_w ),

        .rdata_o            ( weight_col_w  ),
        .weight_en_col_o    ( weight_en_col_w ),

        .sa_data_mover_en   ( )
    );




    SA #(
        .PE_SIZE            ( PE_SIZE ),
        .DATA_WIDTH         ( DATA_WIDTH ),
        .PSUM_WIDTH         ( PSUM_WIDTH )
    ) u_SA (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .ifmap_row_i        ( ifmap_row_w  ), 
        .weight_col_i       ( weight_col_w ), 
        .psum_row_i         ( {(PE_SIZE*PSUM_WIDTH){1'b0}} ),

        .ifmap_preload_i    ( ifmap_valid_w   ),
        .weight_en_col_i    ( weight_en_col_w ),
        .psum_en_row_i      ( weight_en_col_w ),

        .ifmap_row_o        ( ),
        .weight_col_o       ( ),
        .psum_row_o         ( psum_row_w ),

        .weight_en_col_o    ( ),
        .psum_en_row_o      ( psum_en_row_w )
    );


    ACC_v2 #(
        .PE_SIZE        ( PE_SIZE ),
        .DATA_WIDTH     ( DATA_WIDTH ),
        .PSUM_WIDTH     ( PSUM_WIDTH ),
        .SLICING_IDX    ( SLICING_IDX ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_v2(

        .clk            ( clk            ),
        .rst_n          ( rst_n          ),

        .psum_en_row_i  ( psum_en_row_w  ),

        .psum_row_i     ( psum_row_w     ),
        .ofmap_row_o    ( ofmap_row_w    ),
        .ofmap_valid_o  ( ofmap_valid_w  )
    );




    SA_Data_mover_v2 #(
        .FIFO_DATA_WIDTH    ( DATA_WIDTH      ),
        .PE_SIZE            ( PE_SIZE         ),
        .MEM0_DEPTH         ( MEM2_DEPTH      ),
        .MEM0_ADDR_WIDTH    ( MEM2_ADDR_WIDTH ),
        .MEM0_DATA_WIDTH    ( MEM2_DATA_WIDTH ),
        .OC                 ( OUT_CH          )
    ) u_SA_Data_mover (

        .clk                ( clk   ),
        .rst_n              ( rst_n ),

        .en                 ( ofmap_valid_w ),

        .rden_o             ( ),

        .rdata_i            ( ofmap_row_w ),

        .mem2_d0            ( mem2_d0     ),
        .mem2_addr0         ( mem2_addr0  ),
        .mem2_ce0           ( mem2_ce0    ),
        .mem2_we0           ( mem2_we0    ),
        .finish             ( finish_o    )
    );



endmodule