data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, nand_gate_4bits_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 4\'b0010;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 4\'b0111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate_4bits/nand_gate_4bits_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nand_gate_4bits_tb; 
reg[3:0] aa, bb; 
wire[3:0] yy; 
nand_gate_4bits nand_gate_4bits
(
    .A(aa), 
    .B(bb), 
    .Y(yy)
    );
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, nand_gate_4bits_tb);
    end

    initial begin
        aa     <= 4'b0000;
        bb     <= 4'b1111;
        #10 aa <= 4'b0010;
        bb     <= 4'b0110;
        #10 aa <= 4'b0111;
        bb     <= 4'b0100;
        #10 aa <= 4'b0000;
        bb     <= 4'b1110;
        #10 $finish;
    end
endmodule
module nand_gate_4bits_tb;
 
reg[3:0] aa, bb; 
wire[3:0] yy; 
nand_gate_4bits nand_gate_4bits
(
    .A(aa), 
    .B(bb), 
    .Y(yy)
    );
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, nand_gate_4bits_tb);
    end

    initial begin
        aa     <= 4'b0000;
        bb     <= 4'b1111;
        #10 aa <= 4'b0010;
        bb     <= 4'b0110;
        #10 aa <= 4'b0111;
        bb     <= 4'b0100;
        #10 aa <= 4'b0000;
        bb     <= 4'b1110;
        #10 $finish;
    end
endmodule