data/full_repos/permissive/422178762/verilog/rtl/apbled.v
data/verilator_xmls/46b98d49-588a-458e-bbdf-9394d91f6a5b.xml
module apbled(
  input         clock,
  input         reset,
  input         io_PCLK,
  input         io_PRESETn,
  input  [7:0]  io_PADDR,
  input         io_PPROT,
  input         io_PSEL,
  input         io_PENABLE,
  input         io_PWRITE,
  input  [31:0] io_PWDATA,
  input  [3:0]  io_PSTRB,
  output        io_PREADY,
  output [31:0] io_PRDATA,
  output        io_PSLVERR,
  output        io_LEDOUT
);
  wire  QueueModuleled_clock;
  wire  QueueModuleled_reset;
  wire  QueueModuleled_io_i_ready;
  wire  QueueModuleled_io_i_valid;
  wire [23:0] QueueModuleled_io_i_bits;
  wire  QueueModuleled_io_o_ready;
  wire  QueueModuleled_io_o_valid;
  wire [23:0] QueueModuleled_io_o_bits;
  wire  _T_33;
  reg  _T_36;
  reg [31:0] _RAND_0;
  reg  _T_39;
  reg [31:0] _RAND_1;
  reg [31:0] _T_42;
  reg [31:0] _RAND_2;
  reg [1:0] _T_50;
  reg [31:0] _RAND_3;
  reg [23:0] _T_53;
  reg [31:0] _RAND_4;
  reg  _T_56;
  reg [31:0] _RAND_5;
  reg  _T_59;
  reg [31:0] _RAND_6;
  reg [23:0] _T_62;
  reg [31:0] _RAND_7;
  reg [4:0] _T_65;
  reg [31:0] _RAND_8;
  reg [7:0] _T_68;
  reg [31:0] _RAND_9;
  reg [7:0] _T_71;
  reg [31:0] _RAND_10;
  reg [7:0] _T_74;
  reg [31:0] _RAND_11;
  reg [7:0] _T_77;
  reg [31:0] _RAND_12;
  reg [7:0] _T_80;
  reg [31:0] _RAND_13;
  reg [7:0] _T_83;
  reg [31:0] _RAND_14;
  wire [8:0] _T_84;
  wire [7:0] _T_85;
  wire [8:0] _T_86;
  wire [7:0] _T_87;
  wire  _T_88;
  wire  _T_89;
  wire  _T_98;
  wire  _T_99;
  wire [23:0] _T_100;
  wire [23:0] _GEN_0;
  wire  _T_107;
  wire  _T_108;
  wire [7:0] _T_109;
  wire [7:0] _GEN_2;
  wire  _T_113;
  wire  _T_114;
  wire [7:0] _GEN_3;
  wire  _T_119;
  wire  _T_120;
  wire [7:0] _GEN_4;
  wire  _T_125;
  wire  _T_126;
  wire [7:0] _GEN_5;
  wire  _T_129;
  wire  _T_130;
  wire  _T_132;
  wire  _T_133;
  wire  _T_135;
  wire  _T_136;
  wire  _T_139;
  wire  _T_141;
  wire [30:0] _T_142;
  wire [31:0] _T_143;
  wire [31:0] _GEN_6;
  wire  _T_147;
  wire  _T_149;
  wire  _T_150;
  wire  _T_151;
  wire  _GEN_7;
  wire  _T_152;
  wire [1:0] _T_153;
  wire  _T_156;
  wire  _T_159;
  wire  _T_161;
  wire  _T_164;
  wire [7:0] _T_165;
  wire  _T_166;
  wire  _T_169;
  wire [24:0] _GEN_35;
  wire [24:0] _T_170;
  wire [24:0] _T_171;
  wire [8:0] _T_175;
  wire [7:0] _T_176;
  wire [7:0] _T_177;
  wire  _T_180;
  wire [5:0] _T_183;
  wire [4:0] _T_184;
  wire [4:0] _T_185;
  wire [4:0] _T_186;
  wire [1:0] _T_190;
  wire [1:0] _T_191;
  wire  _T_193;
  wire  _T_197;
  wire  _T_201;
  wire [7:0] _GEN_8;
  wire [24:0] _GEN_9;
  wire [7:0] _GEN_10;
  wire [4:0] _GEN_11;
  wire [1:0] _GEN_12;
  wire  _GEN_13;
  wire  _GEN_14;
  wire  _GEN_15;
  wire [1:0] _GEN_16;
  wire [7:0] _GEN_17;
  wire [24:0] _GEN_18;
  wire [7:0] _GEN_19;
  wire [4:0] _GEN_20;
  wire  _GEN_21;
  wire  _GEN_22;
  wire [24:0] _GEN_23;
  wire [1:0] _GEN_24;
  wire [7:0] _GEN_25;
  wire [7:0] _GEN_26;
  wire [4:0] _GEN_27;
  wire [1:0] _GEN_28;
  wire  _GEN_29;
  wire  _GEN_30;
  wire [24:0] _GEN_31;
  wire [7:0] _GEN_32;
  wire [7:0] _GEN_33;
  wire [4:0] _GEN_34;
  QueueModuleled QueueModuleled (
    .clock(QueueModuleled_clock),
    .reset(QueueModuleled_reset),
    .io_i_ready(QueueModuleled_io_i_ready),
    .io_i_valid(QueueModuleled_io_i_valid),
    .io_i_bits(QueueModuleled_io_i_bits),
    .io_o_ready(QueueModuleled_io_o_ready),
    .io_o_valid(QueueModuleled_io_o_valid),
    .io_o_bits(QueueModuleled_io_o_bits)
  );
  assign _T_33 = ~ io_PRESETn;
  assign _T_84 = _T_68 + _T_71;
  assign _T_85 = _T_84[7:0];
  assign _T_86 = _T_74 + _T_77;
  assign _T_87 = _T_86[7:0];
  assign _T_88 = io_PSEL & io_PWRITE;
  assign _T_89 = _T_88 & io_PENABLE;
  assign _T_98 = io_PADDR == 8'h0;
  assign _T_99 = _T_89 & _T_98;
  assign _T_100 = io_PWDATA[23:0];
  assign _GEN_0 = _T_99 ? _T_100 : 24'h0;
  assign _T_107 = io_PADDR == 8'h8;
  assign _T_108 = _T_89 & _T_107;
  assign _T_109 = io_PWDATA[7:0];
  assign _GEN_2 = _T_108 ? _T_109 : _T_68;
  assign _T_113 = io_PADDR == 8'hc;
  assign _T_114 = _T_89 & _T_113;
  assign _GEN_3 = _T_114 ? _T_109 : _T_71;
  assign _T_119 = io_PADDR == 8'h10;
  assign _T_120 = _T_89 & _T_119;
  assign _GEN_4 = _T_120 ? _T_109 : _T_74;
  assign _T_125 = io_PADDR == 8'h14;
  assign _T_126 = _T_89 & _T_125;
  assign _GEN_5 = _T_126 ? _T_109 : _T_77;
  assign _T_129 = io_PWRITE == 1'h0;
  assign _T_130 = io_PSEL & _T_129;
  assign _T_132 = io_PENABLE == 1'h0;
  assign _T_133 = _T_130 & _T_132;
  assign _T_135 = io_PADDR == 8'h4;
  assign _T_136 = _T_133 & _T_135;
  assign _T_139 = QueueModuleled_io_o_valid == 1'h0;
  assign _T_141 = QueueModuleled_io_i_ready == 1'h0;
  assign _T_142 = {30'h0,_T_139};
  assign _T_143 = {_T_142,_T_141};
  assign _GEN_6 = _T_136 ? _T_143 : _T_42;
  assign _T_147 = _T_88 & _T_132;
  assign _T_149 = io_PADDR == 8'h20;
  assign _T_150 = _T_147 & _T_149;
  assign _T_151 = io_PWDATA[0];
  assign _GEN_7 = _T_150 ? _T_151 : _T_39;
  assign _T_152 = 2'h0 == _T_50;
  assign _T_153 = QueueModuleled_io_o_valid ? 2'h1 : 2'h0;
  assign _T_156 = 2'h1 == _T_50;
  assign _T_159 = QueueModuleled_io_o_valid;
  assign _T_161 = 2'h2 == _T_50;
  assign _T_164 = _T_62[23];
  assign _T_165 = _T_164 ? _T_87 : _T_85;
  assign _T_166 = 2'h3 == _T_50;
  assign _T_169 = _T_83 == _T_80;
  assign _GEN_35 = {{1'd0}, _T_62};
  assign _T_170 = _GEN_35 << 1;
  assign _T_171 = _T_169 ? _T_170 : {{1'd0}, _T_62};
  assign _T_175 = _T_83 + 8'h1;
  assign _T_176 = _T_175[7:0];
  assign _T_177 = _T_169 ? 8'h1 : _T_176;
  assign _T_180 = _T_65 == 5'h17;
  assign _T_183 = _T_65 + 5'h1;
  assign _T_184 = _T_183[4:0];
  assign _T_185 = _T_180 ? 5'h0 : _T_184;
  assign _T_186 = _T_169 ? _T_185 : _T_65;
  assign _T_190 = _T_180 ? 2'h0 : 2'h3;
  assign _T_191 = _T_169 ? _T_190 : _T_50;
  assign _T_193 = _T_83 <= _T_74;
  assign _T_197 = _T_83 <= _T_68;
  assign _T_201 = _T_164 ? _T_193 : _T_197;
  assign _GEN_8 = _T_166 ? _T_165 : _T_80;
  assign _GEN_9 = _T_166 ? _T_171 : {{1'd0}, _T_62};
  assign _GEN_10 = _T_166 ? _T_177 : _T_83;
  assign _GEN_11 = _T_166 ? _T_186 : _T_65;
  assign _GEN_12 = _T_166 ? _T_191 : _T_50;
  assign _GEN_13 = _T_166 ? _T_201 : _T_36;
  assign _GEN_14 = _T_161 ? 1'h0 : _T_59;
  assign _GEN_15 = _T_161 ? 1'h0 : _GEN_13;
  assign _GEN_16 = _T_161 ? 2'h3 : _GEN_12;
  assign _GEN_17 = _T_161 ? _T_165 : _GEN_8;
  assign _GEN_18 = _T_161 ? {{1'd0}, _T_62} : _GEN_9;
  assign _GEN_19 = _T_161 ? _T_83 : _GEN_10;
  assign _GEN_20 = _T_161 ? _T_65 : _GEN_11;
  assign _GEN_21 = _T_156 ? _T_159 : _GEN_14;
  assign _GEN_22 = _T_156 ? 1'h0 : _GEN_15;
  assign _GEN_23 = _T_156 ? {{1'd0}, QueueModuleled_io_o_bits} : _GEN_18;
  assign _GEN_24 = _T_156 ? 2'h2 : _GEN_16;
  assign _GEN_25 = _T_156 ? _T_80 : _GEN_17;
  assign _GEN_26 = _T_156 ? _T_83 : _GEN_19;
  assign _GEN_27 = _T_156 ? _T_65 : _GEN_20;
  assign _GEN_28 = _T_152 ? _T_153 : _GEN_24;
  assign _GEN_29 = _T_152 ? 1'h0 : _GEN_22;
  assign _GEN_30 = _T_152 ? 1'h0 : _GEN_21;
  assign _GEN_31 = _T_152 ? {{1'd0}, _T_62} : _GEN_23;
  assign _GEN_32 = _T_152 ? _T_80 : _GEN_25;
  assign _GEN_33 = _T_152 ? _T_83 : _GEN_26;
  assign _GEN_34 = _T_152 ? _T_65 : _GEN_27;
  assign io_PREADY = 1'h1;
  assign io_PRDATA = _T_42;
  assign io_PSLVERR = 1'h0;
  assign io_LEDOUT = _T_39 ? 1'h0 : _T_36;
  assign QueueModuleled_clock = io_PCLK;
  assign QueueModuleled_reset = ~ io_PRESETn;
  assign QueueModuleled_io_i_valid = _T_56;
  assign QueueModuleled_io_i_bits = _T_53;
  assign QueueModuleled_io_o_ready = _T_59;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  _T_36 = _RAND_0[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  _T_39 = _RAND_1[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  _T_42 = _RAND_2[31:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  _T_50 = _RAND_3[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_4 = {1{`RANDOM}};
  _T_53 = _RAND_4[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_5 = {1{`RANDOM}};
  _T_56 = _RAND_5[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  _T_59 = _RAND_6[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  _T_62 = _RAND_7[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  _T_65 = _RAND_8[4:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_9 = {1{`RANDOM}};
  _T_68 = _RAND_9[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_10 = {1{`RANDOM}};
  _T_71 = _RAND_10[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_11 = {1{`RANDOM}};
  _T_74 = _RAND_11[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_12 = {1{`RANDOM}};
  _T_77 = _RAND_12[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_13 = {1{`RANDOM}};
  _T_80 = _RAND_13[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_14 = {1{`RANDOM}};
  _T_83 = _RAND_14[7:0];
  `endif
  end
`endif
  always @(posedge io_PCLK) begin
    if (_T_33) begin
      _T_36 <= 1'h1;
    end else begin
      if (_T_152) begin
        _T_36 <= 1'h0;
      end else begin
        if (_T_156) begin
          _T_36 <= 1'h0;
        end else begin
          if (_T_161) begin
            _T_36 <= 1'h0;
          end else begin
            if (_T_166) begin
              if (_T_164) begin
                _T_36 <= _T_193;
              end else begin
                _T_36 <= _T_197;
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_39 <= 1'h0;
    end else begin
      if (_T_150) begin
        _T_39 <= _T_151;
      end
    end
    if (_T_33) begin
      _T_42 <= 32'h0;
    end else begin
      if (_T_136) begin
        _T_42 <= _T_143;
      end
    end
    if (_T_33) begin
      _T_50 <= 2'h0;
    end else begin
      if (_T_152) begin
        if (QueueModuleled_io_o_valid) begin
          _T_50 <= 2'h1;
        end else begin
          _T_50 <= 2'h0;
        end
      end else begin
        if (_T_156) begin
          _T_50 <= 2'h2;
        end else begin
          if (_T_161) begin
            _T_50 <= 2'h3;
          end else begin
            if (_T_166) begin
              if (_T_169) begin
                if (_T_180) begin
                  _T_50 <= 2'h0;
                end else begin
                  _T_50 <= 2'h3;
                end
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_53 <= 24'h0;
    end else begin
      if (_T_99) begin
        _T_53 <= _T_100;
      end else begin
        _T_53 <= 24'h0;
      end
    end
    if (_T_33) begin
      _T_56 <= 1'h0;
    end else begin
      _T_56 <= _T_99;
    end
    if (_T_33) begin
      _T_59 <= 1'h0;
    end else begin
      if (_T_152) begin
        _T_59 <= 1'h0;
      end else begin
        if (_T_156) begin
          _T_59 <= _T_159;
        end else begin
          if (_T_161) begin
            _T_59 <= 1'h0;
          end
        end
      end
    end
    if (_T_33) begin
      _T_62 <= 24'h0;
    end else begin
      _T_62 <= _GEN_31[23:0];
    end
    if (_T_33) begin
      _T_65 <= 5'h0;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (!(_T_161)) begin
            if (_T_166) begin
              if (_T_169) begin
                if (_T_180) begin
                  _T_65 <= 5'h0;
                end else begin
                  _T_65 <= _T_184;
                end
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_68 <= 8'h4;
    end else begin
      if (_T_108) begin
        _T_68 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_71 <= 8'h4;
    end else begin
      if (_T_114) begin
        _T_71 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_74 <= 8'h4;
    end else begin
      if (_T_120) begin
        _T_74 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_77 <= 8'h4;
    end else begin
      if (_T_126) begin
        _T_77 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_80 <= 8'h0;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (_T_161) begin
            if (_T_164) begin
              _T_80 <= _T_87;
            end else begin
              _T_80 <= _T_85;
            end
          end else begin
            if (_T_166) begin
              if (_T_164) begin
                _T_80 <= _T_87;
              end else begin
                _T_80 <= _T_85;
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_83 <= 8'h1;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (!(_T_161)) begin
            if (_T_166) begin
              if (_T_169) begin
                _T_83 <= 8'h1;
              end else begin
                _T_83 <= _T_176;
              end
            end
          end
        end
      end
    end
  end
endmodule
module apbled(
  input         clock,
  input         reset,
  input         io_PCLK,
  input         io_PRESETn,
  input  [7:0]  io_PADDR,
  input         io_PPROT,
  input         io_PSEL,
  input         io_PENABLE,
  input         io_PWRITE,
  input  [31:0] io_PWDATA,
  input  [3:0]  io_PSTRB,
  output        io_PREADY,
  output [31:0] io_PRDATA,
  output        io_PSLVERR,
  output        io_LEDOUT
);

  wire  QueueModuleled_clock;
  wire  QueueModuleled_reset;
  wire  QueueModuleled_io_i_ready;
  wire  QueueModuleled_io_i_valid;
  wire [23:0] QueueModuleled_io_i_bits;
  wire  QueueModuleled_io_o_ready;
  wire  QueueModuleled_io_o_valid;
  wire [23:0] QueueModuleled_io_o_bits;
  wire  _T_33;
  reg  _T_36;
  reg [31:0] _RAND_0;
  reg  _T_39;
  reg [31:0] _RAND_1;
  reg [31:0] _T_42;
  reg [31:0] _RAND_2;
  reg [1:0] _T_50;
  reg [31:0] _RAND_3;
  reg [23:0] _T_53;
  reg [31:0] _RAND_4;
  reg  _T_56;
  reg [31:0] _RAND_5;
  reg  _T_59;
  reg [31:0] _RAND_6;
  reg [23:0] _T_62;
  reg [31:0] _RAND_7;
  reg [4:0] _T_65;
  reg [31:0] _RAND_8;
  reg [7:0] _T_68;
  reg [31:0] _RAND_9;
  reg [7:0] _T_71;
  reg [31:0] _RAND_10;
  reg [7:0] _T_74;
  reg [31:0] _RAND_11;
  reg [7:0] _T_77;
  reg [31:0] _RAND_12;
  reg [7:0] _T_80;
  reg [31:0] _RAND_13;
  reg [7:0] _T_83;
  reg [31:0] _RAND_14;
  wire [8:0] _T_84;
  wire [7:0] _T_85;
  wire [8:0] _T_86;
  wire [7:0] _T_87;
  wire  _T_88;
  wire  _T_89;
  wire  _T_98;
  wire  _T_99;
  wire [23:0] _T_100;
  wire [23:0] _GEN_0;
  wire  _T_107;
  wire  _T_108;
  wire [7:0] _T_109;
  wire [7:0] _GEN_2;
  wire  _T_113;
  wire  _T_114;
  wire [7:0] _GEN_3;
  wire  _T_119;
  wire  _T_120;
  wire [7:0] _GEN_4;
  wire  _T_125;
  wire  _T_126;
  wire [7:0] _GEN_5;
  wire  _T_129;
  wire  _T_130;
  wire  _T_132;
  wire  _T_133;
  wire  _T_135;
  wire  _T_136;
  wire  _T_139;
  wire  _T_141;
  wire [30:0] _T_142;
  wire [31:0] _T_143;
  wire [31:0] _GEN_6;
  wire  _T_147;
  wire  _T_149;
  wire  _T_150;
  wire  _T_151;
  wire  _GEN_7;
  wire  _T_152;
  wire [1:0] _T_153;
  wire  _T_156;
  wire  _T_159;
  wire  _T_161;
  wire  _T_164;
  wire [7:0] _T_165;
  wire  _T_166;
  wire  _T_169;
  wire [24:0] _GEN_35;
  wire [24:0] _T_170;
  wire [24:0] _T_171;
  wire [8:0] _T_175;
  wire [7:0] _T_176;
  wire [7:0] _T_177;
  wire  _T_180;
  wire [5:0] _T_183;
  wire [4:0] _T_184;
  wire [4:0] _T_185;
  wire [4:0] _T_186;
  wire [1:0] _T_190;
  wire [1:0] _T_191;
  wire  _T_193;
  wire  _T_197;
  wire  _T_201;
  wire [7:0] _GEN_8;
  wire [24:0] _GEN_9;
  wire [7:0] _GEN_10;
  wire [4:0] _GEN_11;
  wire [1:0] _GEN_12;
  wire  _GEN_13;
  wire  _GEN_14;
  wire  _GEN_15;
  wire [1:0] _GEN_16;
  wire [7:0] _GEN_17;
  wire [24:0] _GEN_18;
  wire [7:0] _GEN_19;
  wire [4:0] _GEN_20;
  wire  _GEN_21;
  wire  _GEN_22;
  wire [24:0] _GEN_23;
  wire [1:0] _GEN_24;
  wire [7:0] _GEN_25;
  wire [7:0] _GEN_26;
  wire [4:0] _GEN_27;
  wire [1:0] _GEN_28;
  wire  _GEN_29;
  wire  _GEN_30;
  wire [24:0] _GEN_31;
  wire [7:0] _GEN_32;
  wire [7:0] _GEN_33;
  wire [4:0] _GEN_34;
  QueueModuleled QueueModuleled (
    .clock(QueueModuleled_clock),
    .reset(QueueModuleled_reset),
    .io_i_ready(QueueModuleled_io_i_ready),
    .io_i_valid(QueueModuleled_io_i_valid),
    .io_i_bits(QueueModuleled_io_i_bits),
    .io_o_ready(QueueModuleled_io_o_ready),
    .io_o_valid(QueueModuleled_io_o_valid),
    .io_o_bits(QueueModuleled_io_o_bits)
  );
  assign _T_33 = ~ io_PRESETn;
  assign _T_84 = _T_68 + _T_71;
  assign _T_85 = _T_84[7:0];
  assign _T_86 = _T_74 + _T_77;
  assign _T_87 = _T_86[7:0];
  assign _T_88 = io_PSEL & io_PWRITE;
  assign _T_89 = _T_88 & io_PENABLE;
  assign _T_98 = io_PADDR == 8'h0;
  assign _T_99 = _T_89 & _T_98;
  assign _T_100 = io_PWDATA[23:0];
  assign _GEN_0 = _T_99 ? _T_100 : 24'h0;
  assign _T_107 = io_PADDR == 8'h8;
  assign _T_108 = _T_89 & _T_107;
  assign _T_109 = io_PWDATA[7:0];
  assign _GEN_2 = _T_108 ? _T_109 : _T_68;
  assign _T_113 = io_PADDR == 8'hc;
  assign _T_114 = _T_89 & _T_113;
  assign _GEN_3 = _T_114 ? _T_109 : _T_71;
  assign _T_119 = io_PADDR == 8'h10;
  assign _T_120 = _T_89 & _T_119;
  assign _GEN_4 = _T_120 ? _T_109 : _T_74;
  assign _T_125 = io_PADDR == 8'h14;
  assign _T_126 = _T_89 & _T_125;
  assign _GEN_5 = _T_126 ? _T_109 : _T_77;
  assign _T_129 = io_PWRITE == 1'h0;
  assign _T_130 = io_PSEL & _T_129;
  assign _T_132 = io_PENABLE == 1'h0;
  assign _T_133 = _T_130 & _T_132;
  assign _T_135 = io_PADDR == 8'h4;
  assign _T_136 = _T_133 & _T_135;
  assign _T_139 = QueueModuleled_io_o_valid == 1'h0;
  assign _T_141 = QueueModuleled_io_i_ready == 1'h0;
  assign _T_142 = {30'h0,_T_139};
  assign _T_143 = {_T_142,_T_141};
  assign _GEN_6 = _T_136 ? _T_143 : _T_42;
  assign _T_147 = _T_88 & _T_132;
  assign _T_149 = io_PADDR == 8'h20;
  assign _T_150 = _T_147 & _T_149;
  assign _T_151 = io_PWDATA[0];
  assign _GEN_7 = _T_150 ? _T_151 : _T_39;
  assign _T_152 = 2'h0 == _T_50;
  assign _T_153 = QueueModuleled_io_o_valid ? 2'h1 : 2'h0;
  assign _T_156 = 2'h1 == _T_50;
  assign _T_159 = QueueModuleled_io_o_valid;
  assign _T_161 = 2'h2 == _T_50;
  assign _T_164 = _T_62[23];
  assign _T_165 = _T_164 ? _T_87 : _T_85;
  assign _T_166 = 2'h3 == _T_50;
  assign _T_169 = _T_83 == _T_80;
  assign _GEN_35 = {{1'd0}, _T_62};
  assign _T_170 = _GEN_35 << 1;
  assign _T_171 = _T_169 ? _T_170 : {{1'd0}, _T_62};
  assign _T_175 = _T_83 + 8'h1;
  assign _T_176 = _T_175[7:0];
  assign _T_177 = _T_169 ? 8'h1 : _T_176;
  assign _T_180 = _T_65 == 5'h17;
  assign _T_183 = _T_65 + 5'h1;
  assign _T_184 = _T_183[4:0];
  assign _T_185 = _T_180 ? 5'h0 : _T_184;
  assign _T_186 = _T_169 ? _T_185 : _T_65;
  assign _T_190 = _T_180 ? 2'h0 : 2'h3;
  assign _T_191 = _T_169 ? _T_190 : _T_50;
  assign _T_193 = _T_83 <= _T_74;
  assign _T_197 = _T_83 <= _T_68;
  assign _T_201 = _T_164 ? _T_193 : _T_197;
  assign _GEN_8 = _T_166 ? _T_165 : _T_80;
  assign _GEN_9 = _T_166 ? _T_171 : {{1'd0}, _T_62};
  assign _GEN_10 = _T_166 ? _T_177 : _T_83;
  assign _GEN_11 = _T_166 ? _T_186 : _T_65;
  assign _GEN_12 = _T_166 ? _T_191 : _T_50;
  assign _GEN_13 = _T_166 ? _T_201 : _T_36;
  assign _GEN_14 = _T_161 ? 1'h0 : _T_59;
  assign _GEN_15 = _T_161 ? 1'h0 : _GEN_13;
  assign _GEN_16 = _T_161 ? 2'h3 : _GEN_12;
  assign _GEN_17 = _T_161 ? _T_165 : _GEN_8;
  assign _GEN_18 = _T_161 ? {{1'd0}, _T_62} : _GEN_9;
  assign _GEN_19 = _T_161 ? _T_83 : _GEN_10;
  assign _GEN_20 = _T_161 ? _T_65 : _GEN_11;
  assign _GEN_21 = _T_156 ? _T_159 : _GEN_14;
  assign _GEN_22 = _T_156 ? 1'h0 : _GEN_15;
  assign _GEN_23 = _T_156 ? {{1'd0}, QueueModuleled_io_o_bits} : _GEN_18;
  assign _GEN_24 = _T_156 ? 2'h2 : _GEN_16;
  assign _GEN_25 = _T_156 ? _T_80 : _GEN_17;
  assign _GEN_26 = _T_156 ? _T_83 : _GEN_19;
  assign _GEN_27 = _T_156 ? _T_65 : _GEN_20;
  assign _GEN_28 = _T_152 ? _T_153 : _GEN_24;
  assign _GEN_29 = _T_152 ? 1'h0 : _GEN_22;
  assign _GEN_30 = _T_152 ? 1'h0 : _GEN_21;
  assign _GEN_31 = _T_152 ? {{1'd0}, _T_62} : _GEN_23;
  assign _GEN_32 = _T_152 ? _T_80 : _GEN_25;
  assign _GEN_33 = _T_152 ? _T_83 : _GEN_26;
  assign _GEN_34 = _T_152 ? _T_65 : _GEN_27;
  assign io_PREADY = 1'h1;
  assign io_PRDATA = _T_42;
  assign io_PSLVERR = 1'h0;
  assign io_LEDOUT = _T_39 ? 1'h0 : _T_36;
  assign QueueModuleled_clock = io_PCLK;
  assign QueueModuleled_reset = ~ io_PRESETn;
  assign QueueModuleled_io_i_valid = _T_56;
  assign QueueModuleled_io_i_bits = _T_53;
  assign QueueModuleled_io_o_ready = _T_59;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  _T_36 = _RAND_0[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  _T_39 = _RAND_1[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  _T_42 = _RAND_2[31:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  _T_50 = _RAND_3[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_4 = {1{`RANDOM}};
  _T_53 = _RAND_4[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_5 = {1{`RANDOM}};
  _T_56 = _RAND_5[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  _T_59 = _RAND_6[0:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  _T_62 = _RAND_7[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  _T_65 = _RAND_8[4:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_9 = {1{`RANDOM}};
  _T_68 = _RAND_9[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_10 = {1{`RANDOM}};
  _T_71 = _RAND_10[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_11 = {1{`RANDOM}};
  _T_74 = _RAND_11[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_12 = {1{`RANDOM}};
  _T_77 = _RAND_12[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_13 = {1{`RANDOM}};
  _T_80 = _RAND_13[7:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_14 = {1{`RANDOM}};
  _T_83 = _RAND_14[7:0];
  `endif
  end
`endif
  always @(posedge io_PCLK) begin
    if (_T_33) begin
      _T_36 <= 1'h1;
    end else begin
      if (_T_152) begin
        _T_36 <= 1'h0;
      end else begin
        if (_T_156) begin
          _T_36 <= 1'h0;
        end else begin
          if (_T_161) begin
            _T_36 <= 1'h0;
          end else begin
            if (_T_166) begin
              if (_T_164) begin
                _T_36 <= _T_193;
              end else begin
                _T_36 <= _T_197;
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_39 <= 1'h0;
    end else begin
      if (_T_150) begin
        _T_39 <= _T_151;
      end
    end
    if (_T_33) begin
      _T_42 <= 32'h0;
    end else begin
      if (_T_136) begin
        _T_42 <= _T_143;
      end
    end
    if (_T_33) begin
      _T_50 <= 2'h0;
    end else begin
      if (_T_152) begin
        if (QueueModuleled_io_o_valid) begin
          _T_50 <= 2'h1;
        end else begin
          _T_50 <= 2'h0;
        end
      end else begin
        if (_T_156) begin
          _T_50 <= 2'h2;
        end else begin
          if (_T_161) begin
            _T_50 <= 2'h3;
          end else begin
            if (_T_166) begin
              if (_T_169) begin
                if (_T_180) begin
                  _T_50 <= 2'h0;
                end else begin
                  _T_50 <= 2'h3;
                end
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_53 <= 24'h0;
    end else begin
      if (_T_99) begin
        _T_53 <= _T_100;
      end else begin
        _T_53 <= 24'h0;
      end
    end
    if (_T_33) begin
      _T_56 <= 1'h0;
    end else begin
      _T_56 <= _T_99;
    end
    if (_T_33) begin
      _T_59 <= 1'h0;
    end else begin
      if (_T_152) begin
        _T_59 <= 1'h0;
      end else begin
        if (_T_156) begin
          _T_59 <= _T_159;
        end else begin
          if (_T_161) begin
            _T_59 <= 1'h0;
          end
        end
      end
    end
    if (_T_33) begin
      _T_62 <= 24'h0;
    end else begin
      _T_62 <= _GEN_31[23:0];
    end
    if (_T_33) begin
      _T_65 <= 5'h0;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (!(_T_161)) begin
            if (_T_166) begin
              if (_T_169) begin
                if (_T_180) begin
                  _T_65 <= 5'h0;
                end else begin
                  _T_65 <= _T_184;
                end
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_68 <= 8'h4;
    end else begin
      if (_T_108) begin
        _T_68 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_71 <= 8'h4;
    end else begin
      if (_T_114) begin
        _T_71 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_74 <= 8'h4;
    end else begin
      if (_T_120) begin
        _T_74 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_77 <= 8'h4;
    end else begin
      if (_T_126) begin
        _T_77 <= _T_109;
      end
    end
    if (_T_33) begin
      _T_80 <= 8'h0;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (_T_161) begin
            if (_T_164) begin
              _T_80 <= _T_87;
            end else begin
              _T_80 <= _T_85;
            end
          end else begin
            if (_T_166) begin
              if (_T_164) begin
                _T_80 <= _T_87;
              end else begin
                _T_80 <= _T_85;
              end
            end
          end
        end
      end
    end
    if (_T_33) begin
      _T_83 <= 8'h1;
    end else begin
      if (!(_T_152)) begin
        if (!(_T_156)) begin
          if (!(_T_161)) begin
            if (_T_166) begin
              if (_T_169) begin
                _T_83 <= 8'h1;
              end else begin
                _T_83 <= _T_176;
              end
            end
          end
        end
      end
    end
  end
endmodule