data/full_repos/permissive/493331294/atlys_spartan_6/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493331294/atlys_spartan_6/main.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #0.5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493331294/atlys_spartan_6/main.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #0.5;\n  ^\n%Error: data/full_repos/permissive/493331294/atlys_spartan_6/main.v:129: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/493331294/atlys_spartan_6/main.v:130: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, Main);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Main
(

	
	output [7:0] led,
	output uarttx
);
	

	

	reg clk;
	reg [7:0] sw;
	reg [5:0] btn;
	reg uartrx;
	reg [7:0] jb_drive;
	wire [7:0] jb;
	

	wire [7:0] SW;
	

	wire BTN_RST;
	wire BTN_UP;
	wire BTN_LEFT;
	wire BTN_DOWN;
	wire BTN_RIGHT;
	wire BTN_CTR;
	

	wire [7:0] LED;
	

	wire UART_RX;
	wire UART_TX;
	

	wire [7:0] PMOD_IN;
	wire [7:0] PMOD_OUT;
	wire [7:0] PMOD_DIR;
	

	reg reset0 = 1;
	reg RST = 1;
	wire reset_trigger;
	

	wire CLK;
	wire LOCKED;
	
 
 

	

	assign jb = jb_drive;
	assign CLK = clk;
	assign LOCKED = 1'd1;
	

	assign SW = sw;
	assign {BTN_CTR, BTN_RIGHT, BTN_DOWN, BTN_LEFT, BTN_UP, BTN_RST} = btn[5:0];
	assign led = LED;
	assign UART_RX = uartrx;
	assign uarttx = UART_TX;
	
	genvar i;
	generate
		for (i = 0; i < 8; i = i + 1) begin
			assign jb[i] = PMOD_DIR[i] ? PMOD_OUT[i] : 1'bz;
			assign PMOD_IN[i] = PMOD_DIR[i] ? 1'd0 : jb[i];
		end
	endgenerate
	

	assign reset_trigger = ~BTN_RST;
	
	always @(posedge CLK or posedge reset_trigger) begin
		if (reset_trigger | ~LOCKED) begin
			reset0 <= 1;
			RST <= 1;
		end
		else begin
			RST <= reset0;
			reset0 <= 0;
		end
	end
	


	
	
	

	assign LED = 0;
	assign PMOD_OUT = 0;
	assign PMOD_DIR = 0;
	assign UART_TX = 0;

	
	

	
	always begin
		clk <= 0;
		#0.5;
		clk <= 1;
		#0.5;
	end
	
	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, Main);
		
		$finish;
	end
	
endmodule
module Main
(

	
	output [7:0] led,
	output uarttx
);

	

	

	reg clk;
	reg [7:0] sw;
	reg [5:0] btn;
	reg uartrx;
	reg [7:0] jb_drive;
	wire [7:0] jb;
	

	wire [7:0] SW;
	

	wire BTN_RST;
	wire BTN_UP;
	wire BTN_LEFT;
	wire BTN_DOWN;
	wire BTN_RIGHT;
	wire BTN_CTR;
	

	wire [7:0] LED;
	

	wire UART_RX;
	wire UART_TX;
	

	wire [7:0] PMOD_IN;
	wire [7:0] PMOD_OUT;
	wire [7:0] PMOD_DIR;
	

	reg reset0 = 1;
	reg RST = 1;
	wire reset_trigger;
	

	wire CLK;
	wire LOCKED;
	
 
 

	

	assign jb = jb_drive;
	assign CLK = clk;
	assign LOCKED = 1'd1;
	

	assign SW = sw;
	assign {BTN_CTR, BTN_RIGHT, BTN_DOWN, BTN_LEFT, BTN_UP, BTN_RST} = btn[5:0];
	assign led = LED;
	assign UART_RX = uartrx;
	assign uarttx = UART_TX;
	
	genvar i;
	generate
		for (i = 0; i < 8; i = i + 1) begin
			assign jb[i] = PMOD_DIR[i] ? PMOD_OUT[i] : 1'bz;
			assign PMOD_IN[i] = PMOD_DIR[i] ? 1'd0 : jb[i];
		end
	endgenerate
	

	assign reset_trigger = ~BTN_RST;
	
	always @(posedge CLK or posedge reset_trigger) begin
		if (reset_trigger | ~LOCKED) begin
			reset0 <= 1;
			RST <= 1;
		end
		else begin
			RST <= reset0;
			reset0 <= 0;
		end
	end
	


	
	
	

	assign LED = 0;
	assign PMOD_OUT = 0;
	assign PMOD_DIR = 0;
	assign UART_TX = 0;

	
	

	
	always begin
		clk <= 0;
		#0.5;
		clk <= 1;
		#0.5;
	end
	
	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, Main);
		
		$finish;
	end
	
endmodule