data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/tests/bram2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/tests/bram2_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/tests/bram2_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 rd_clk <= ~rd_clk;\n          ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/tests/bram2_tb.v:43: syntax error, unexpected \'@\'\n  @(posedge rd_clk);\n  ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/tests/bram2_tb.v:46: syntax error, unexpected \'@\'\n   @(posedge rd_clk);\n   ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [17:0] hash(input [7:0] k);
		reg [31:0] x;
		begin
			x = {k, ~k, k, ~k};
			x = x ^ (x << 13);
			x = x ^ (x >> 17);
			x = x ^ (x << 5);
			hash = x;
		end
	endfunction
function [17:0] hash(input [7:0] k);

		reg [31:0] x;
		begin
			x = {k, ~k, k, ~k};
			x = x ^ (x << 13);
			x = x ^ (x >> 17);
			x = x ^ (x << 5);
			hash = x;
		end
	endfunction