data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:45: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:46: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:63: Define or directive not defined: \'`SIG_CQ_TUSER_W\'\n     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:75: Define or directive not defined: \'`SIG_FBE_W\'\n     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:76: Define or directive not defined: \'`SIG_LBE_W\'\n     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:77: Define or directive not defined: \'`SIG_TC_W\'\n     output [`SIG_TC_W-1:0]                   RXR_META_TC,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:78: Define or directive not defined: \'`SIG_ATTR_W\'\n     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:79: Define or directive not defined: \'`SIG_TAG_W\'\n     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:80: Define or directive not defined: \'`SIG_TYPE_W\'\n     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:81: Define or directive not defined: \'`SIG_ADDR_W\'\n     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:82: Define or directive not defined: \'`SIG_BARDECODE_W\'\n     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:83: Define or directive not defined: \'`SIG_REQID_W\'\n     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:84: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:88: Define or directive not defined: \'`EXT_TYPE_W\'\n    function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:89: Define or directive not defined: \'`UPKT_TYPE_W\'\n        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:89: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: Define or directive not defined: \'`UPKT_REQ_RD\'\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:93: Define or directive not defined: \'`TRLS_REQ_RD\'\n                {`UPKT_REQ_RD,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:94: Define or directive not defined: \'`UPKT_REQ_WR\'\n                {`UPKT_REQ_WR,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:94: Define or directive not defined: \'`TRLS_REQ_WR\'\n                {`UPKT_REQ_WR,1\'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:95: Define or directive not defined: \'`UPKT_MSG\'\n                {`UPKT_MSG   ,1\'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:95: Define or directive not defined: \'`TRLS_MSG_ND\'\n                {`UPKT_MSG   ,1\'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:96: Define or directive not defined: \'`UPKT_MSG\'\n                {`UPKT_MSG   ,1\'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:96: Define or directive not defined: \'`TRLS_MSG_WD\'\n                {`UPKT_MSG   ,1\'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:97: Define or directive not defined: \'`TRLS_REQ_RD\'\n                default:             upkt_to_trellis_type = `TRLS_REQ_RD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:104: Define or directive not defined: \'`SIG_FBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:104: Define or directive not defined: \'`SIG_LBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:112: Define or directive not defined: \'`UPKT_RXR_ADDRDW0_I\'\n    localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:113: Define or directive not defined: \'`UPKT_RXR_ADDRDW1_I\'\n    localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:114: Define or directive not defined: \'`UPKT_RXR_METADW0_I\'\n    localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:115: Define or directive not defined: \'`UPKT_RXR_METADW1_I\'\n    localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:116: Define or directive not defined: \'`UPKT_RXR_PAYLOAD_I\'\n    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:119: Define or directive not defined: \'`UPKT_RXR_ADDRDW0_I\'\n    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:120: Define or directive not defined: \'`UPKT_RXR_ADDRDW1_I\'\n    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:121: Define or directive not defined: \'`UPKT_RXR_METADW0_I\'\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:122: Define or directive not defined: \'`UPKT_RXR_METADW1_I\'\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:144: Define or directive not defined: \'`SIG_TYPE_W\'\n    wire [`SIG_TYPE_W-1:0]                              wRxrType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:145: Define or directive not defined: \'`SIG_FBE_W\'\n    wire [`SIG_FBE_W-1:0]                               wRxrMetaFdwbe;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:146: Define or directive not defined: \'`SIG_LBE_W\'\n    wire [`SIG_LBE_W-1:0]                               wRxrMetaLdwbe;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:148: Define or directive not defined: \'`SIG_BARDECODE_W\'\n    wire [`SIG_BARDECODE_W-1:0]                         wRxrBarDecoded;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:162: Define or directive not defined: \'`SIG_BARDECODE_W\'\n    wire [`SIG_BARDECODE_W-1:0]                         wBarDecoded;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:165: Define or directive not defined: \'`SIG_TYPE_W\'\n    wire [`SIG_TYPE_W-1:0]                              wType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:168: Define or directive not defined: \'`UPKT_CQ_TUSER_SOP_R\'\n    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];\n                                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:168: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];\n                                                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:171: Define or directive not defined: \'`UPKT_RXR_BARID_R\'\n    assign wBarDecoded = (8\'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);\n                                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:171: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign wBarDecoded = (8\'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);\n                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: Define or directive not defined: \'`UPKT_RXR_LENGTH_I\'\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                                                ^~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_ultrascale.v:183: Define or directive not defined: \'`UPKT_RXR_MAXHDR_W\'\n    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);\n                                                                       ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rxr_engine_ultrascale
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                    CLK,


     input                                    RST_IN,


     input                                    M_AXIS_CQ_TVALID,
     input                                    M_AXIS_CQ_TLAST,
     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_CQ_TDATA,
     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_CQ_TKEEP,
     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,
     output                                   M_AXIS_CQ_TREADY,


     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
     output                                   RXR_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
     output                                   RXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
     output                                   RXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
     
     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
     output [`SIG_TC_W-1:0]                   RXR_META_TC,
     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
     output                                   RXR_META_EP
     );

    function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;
        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;
        begin

            casex(WR_UPKT_TYPE)
                {`UPKT_REQ_RD,1'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;
                {`UPKT_REQ_WR,1'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;
                {`UPKT_MSG   ,1'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;
                {`UPKT_MSG   ,1'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;
                default:             upkt_to_trellis_type = `TRLS_REQ_RD;
            endcase

        end
    endfunction


    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);

    localparam C_RX_INPUT_STAGES = 0;
    localparam C_RX_OUTPUT_STAGES = 2;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;


    localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES;
    
    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;


    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);

    wire                                      wMAxisCqSop;
    wire                                      wMAxisCqTlast;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrSop;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrEop;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrDataValid;
    wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
    wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;

    wire                                                wRxrDataValid;
    wire                                                wRxrDataReady;
    wire                                                wRxrDataEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataEndOffset;
    wire                                                wRxrDataStartFlag;
    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataStartOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wRxrDataWordEnable;
    wire [127:0]                                        wRxrHdr;
    wire [`SIG_TYPE_W-1:0]                              wRxrType;
    wire [`SIG_FBE_W-1:0]                               wRxrMetaFdwbe;
    wire [`SIG_LBE_W-1:0]                               wRxrMetaLdwbe;
    wire [C_RX_BE_W-1:0]                                wRxrBe;
    wire [`SIG_BARDECODE_W-1:0]                         wRxrBarDecoded;
    
    wire [127:0]                                        wHdr;
    wire                                                wEndFlag;
    wire                                                wEndFlagLastCycle;
    wire                                                _wEndFlag;    
    wire [C_OFFSET_WIDTH-1:0]                           wEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wEndMask;
    wire                                                _wStartFlag;
    wire                                                wStartFlag;
    wire [1:0]                                          wStartFlags;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wStartMask;
    wire [C_OFFSET_WIDTH-1:0]                           wStartOffset;
    wire [C_RX_BE_W-1:0]                                wByteEnables;                    
    wire [`SIG_BARDECODE_W-1:0]                         wBarDecoded;
    wire                                                wHasPayload;
    
    wire [`SIG_TYPE_W-1:0]                              wType;
    reg                                                 rValid,_rValid;

    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
    assign wMAxisCqTlast = M_AXIS_CQ_TLAST;

    assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
    





    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
    assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];


    assign wStartOffset = 4;
    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);




    assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
    assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];
    assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
    assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
    assign RXR_META_TYPE = wRxrType;
    assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
    assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
    assign RXR_META_FDWBE = wRxrMetaFdwbe;
    assign RXR_META_LDWBE = wRxrMetaLdwbe;
    assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
    assign RXR_DATA_START_OFFSET = 0;
    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
    assign RXR_DATA_END_OFFSET = wEndOffset;
    assign RXR_META_BAR_DECODED = wRxrBarDecoded;
    assign RXR_DATA_VALID = wRxrDataValid;
    assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];

    assign M_AXIS_CQ_TREADY = 1'b1;

    assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
    
    assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
    assign _wStartFlag = wStartFlags != 0;
    assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);

    generate
        if(C_PCI_DATA_WIDTH == 64) begin
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES];
        end else if (C_PCI_DATA_WIDTH == 128) begin    
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES];
        end else begin
            assign wStartFlags[1] = 0;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
        end
    endgenerate

    always @(*) begin
        _rValid = rValid;
        if(_wStartFlag) begin
	        _rValid = 1'b1;
        end else if (wEndFlag) begin
	        _rValid = 1'b0;
        end
    end
    
    always @(posedge CLK) begin
        if(RST_IN) begin
	        rValid <= 1'b0;
        end else begin
	        rValid <= _rValid;
        end
    end

    register
        #(

          .C_WIDTH                      (32))
    meta_DW1_register
        (

         .RD_DATA                       (wHdr[127:96]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_METADW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    metadata_DW0_register
        (

         .RD_DATA                       (wHdr[95:64]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_METADW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    addr_DW1_register
        (

         .RD_DATA                       (wHdr[63:32]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    addr_DW0_register
        (

         .RD_DATA                       (wHdr[31:0]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]));

    register
        #(

          .C_WIDTH                      (C_RX_BE_W))
    be_register
        (

         .RD_DATA                       (wByteEnables),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
         .WR_EN                         (wRxSrSop[C_RX_BE_CYCLE]));



    shiftreg
        #(

          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                     (C_PCI_DATA_WIDTH)
)
    data_shiftreg_inst
        (

         .RD_DATA                       (wRxSrData),

         .WR_DATA                       (M_AXIS_CQ_TDATA),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    sop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrSop),

         .WR_DATA                       (wMAxisCqSop & M_AXIS_CQ_TVALID),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    eop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrEop),

         .WR_DATA                       (wMAxisCqTlast),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    valid_shiftreg_inst
        (

         .RD_DATA                       (wRxSrDataValid),

         .WR_DATA                       (M_AXIS_CQ_TVALID),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));




    shiftreg
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (C_RX_BE_W)
)
    be_shiftreg_inst
        (

         .RD_DATA                       (wRxSrBe),

         .WR_DATA                       (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (1'b0)
)
    start_flag_register
        (

         .RD_DATA                       (wStartFlag),

         .WR_DATA                       (_wStartFlag),
         .WR_EN                         (1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    o2m_ef
        (

         .MASK                          (wEndMask),

         .OFFSET_ENABLE                 (wEndFlag),
         .OFFSET                        (wEndOffset)
);

    generate
        if(C_RX_OUTPUT_STAGES == 0) begin
            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
        end else begin
            register
                #(

                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
                  .C_VALUE              (0)
)
            dw_enable
                (
                 .RD_DATA               (wRxrDataWordEnable),

                 .RST_IN                (~rValid | wHasPayload),
                 .WR_DATA               (wEndMask & wStartMask),
                 .WR_EN                 (1),

                 .CLK                   (CLK));

            pipeline
                #(

                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
                  .C_USE_MEMORY                 (0)
)
            dw_pipeline
                (

                 .WR_DATA_READY                 (),
                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
                 .RD_DATA_VALID                 (),

                 .WR_DATA                       (wRxrDataWordEnable),
                 .WR_DATA_VALID                 (1),
                 .RD_DATA_READY                 (1'b1),


                 .CLK                           (CLK),
                 .RST_IN                        (RST_IN));
        end
    endgenerate

    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) + `SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W + `SIG_TYPE_W),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
         .RD_DATA_VALID                 (wRxrDataValid),

         .WR_DATA                       ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
         .WR_DATA_VALID                 (rValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

endmodule
module rxr_engine_ultrascale
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                    CLK,


     input                                    RST_IN,


     input                                    M_AXIS_CQ_TVALID,
     input                                    M_AXIS_CQ_TLAST,
     input [C_PCI_DATA_WIDTH-1:0]             M_AXIS_CQ_TDATA,
     input [(C_PCI_DATA_WIDTH/32)-1:0]        M_AXIS_CQ_TKEEP,
     input [`SIG_CQ_TUSER_W-1:0]              M_AXIS_CQ_TUSER,
     output                                   M_AXIS_CQ_TREADY,


     output [C_PCI_DATA_WIDTH-1:0]            RXR_DATA,
     output                                   RXR_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]       RXR_DATA_WORD_ENABLE,
     output                                   RXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
     output                                   RXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
     
     output [`SIG_FBE_W-1:0]                  RXR_META_FDWBE,
     output [`SIG_LBE_W-1:0]                  RXR_META_LDWBE,
     output [`SIG_TC_W-1:0]                   RXR_META_TC,
     output [`SIG_ATTR_W-1:0]                 RXR_META_ATTR,
     output [`SIG_TAG_W-1:0]                  RXR_META_TAG,
     output [`SIG_TYPE_W-1:0]                 RXR_META_TYPE,
     output [`SIG_ADDR_W-1:0]                 RXR_META_ADDR,
     output [`SIG_BARDECODE_W-1:0]            RXR_META_BAR_DECODED,
     output [`SIG_REQID_W-1:0]                RXR_META_REQUESTER_ID,
     output [`SIG_LEN_W-1:0]                  RXR_META_LENGTH,
     output                                   RXR_META_EP
     );


    function [ `EXT_TYPE_W - 1: 0 ] upkt_to_trellis_type;
        input [`UPKT_TYPE_W : 0 ] WR_UPKT_TYPE;
        begin

            casex(WR_UPKT_TYPE)
                {`UPKT_REQ_RD,1'bx}: upkt_to_trellis_type = `TRLS_REQ_RD;
                {`UPKT_REQ_WR,1'bx}: upkt_to_trellis_type = `TRLS_REQ_WR;
                {`UPKT_MSG   ,1'b0}: upkt_to_trellis_type = `TRLS_MSG_ND;
                {`UPKT_MSG   ,1'b1}: upkt_to_trellis_type = `TRLS_MSG_WD;
                default:             upkt_to_trellis_type = `TRLS_REQ_RD;
            endcase

        end
    endfunction


    localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);

    localparam C_RX_INPUT_STAGES = 0;
    localparam C_RX_OUTPUT_STAGES = 2;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;


    localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES;
    
    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;


    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);

    wire                                      wMAxisCqSop;
    wire                                      wMAxisCqTlast;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrSop;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrEop;
    wire [C_RX_PIPELINE_DEPTH:0]              wRxSrDataValid;
    wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
    wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;

    wire                                                wRxrDataValid;
    wire                                                wRxrDataReady;
    wire                                                wRxrDataEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataEndOffset;
    wire                                                wRxrDataStartFlag;
    wire [C_OFFSET_WIDTH-1:0]                           wRxrDataStartOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wRxrDataWordEnable;
    wire [127:0]                                        wRxrHdr;
    wire [`SIG_TYPE_W-1:0]                              wRxrType;
    wire [`SIG_FBE_W-1:0]                               wRxrMetaFdwbe;
    wire [`SIG_LBE_W-1:0]                               wRxrMetaLdwbe;
    wire [C_RX_BE_W-1:0]                                wRxrBe;
    wire [`SIG_BARDECODE_W-1:0]                         wRxrBarDecoded;
    
    wire [127:0]                                        wHdr;
    wire                                                wEndFlag;
    wire                                                wEndFlagLastCycle;
    wire                                                _wEndFlag;    
    wire [C_OFFSET_WIDTH-1:0]                           wEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wEndMask;
    wire                                                _wStartFlag;
    wire                                                wStartFlag;
    wire [1:0]                                          wStartFlags;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                    wStartMask;
    wire [C_OFFSET_WIDTH-1:0]                           wStartOffset;
    wire [C_RX_BE_W-1:0]                                wByteEnables;                    
    wire [`SIG_BARDECODE_W-1:0]                         wBarDecoded;
    wire                                                wHasPayload;
    
    wire [`SIG_TYPE_W-1:0]                              wType;
    reg                                                 rValid,_rValid;

    assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
    assign wMAxisCqTlast = M_AXIS_CQ_TLAST;

    assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
    





    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
    assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];


    assign wStartOffset = 4;
    assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);




    assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
    assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];
    assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
    assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
    assign RXR_META_TYPE = wRxrType;
    assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
    assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
    assign RXR_META_FDWBE = wRxrMetaFdwbe;
    assign RXR_META_LDWBE = wRxrMetaLdwbe;
    assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
    assign RXR_DATA_START_OFFSET = 0;
    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
    assign RXR_DATA_END_OFFSET = wEndOffset;
    assign RXR_META_BAR_DECODED = wRxrBarDecoded;
    assign RXR_DATA_VALID = wRxrDataValid;
    assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];

    assign M_AXIS_CQ_TREADY = 1'b1;

    assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
    
    assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
    assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
    assign _wStartFlag = wStartFlags != 0;
    assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);

    generate
        if(C_PCI_DATA_WIDTH == 64) begin
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES];
        end else if (C_PCI_DATA_WIDTH == 128) begin    
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES];
        end else begin
            assign wStartFlags[1] = 0;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
        end
    endgenerate

    always @(*) begin
        _rValid = rValid;
        if(_wStartFlag) begin
	        _rValid = 1'b1;
        end else if (wEndFlag) begin
	        _rValid = 1'b0;
        end
    end
    
    always @(posedge CLK) begin
        if(RST_IN) begin
	        rValid <= 1'b0;
        end else begin
	        rValid <= _rValid;
        end
    end

    register
        #(

          .C_WIDTH                      (32))
    meta_DW1_register
        (

         .RD_DATA                       (wHdr[127:96]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_METADW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    metadata_DW0_register
        (

         .RD_DATA                       (wHdr[95:64]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_METADW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    addr_DW1_register
        (

         .RD_DATA                       (wHdr[63:32]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]));

    register
        #(

          .C_WIDTH                      (32))
    addr_DW0_register
        (

         .RD_DATA                       (wHdr[31:0]),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]));

    register
        #(

          .C_WIDTH                      (C_RX_BE_W))
    be_register
        (

         .RD_DATA                       (wByteEnables),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
         .WR_EN                         (wRxSrSop[C_RX_BE_CYCLE]));



    shiftreg
        #(

          .C_DEPTH                     (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                     (C_PCI_DATA_WIDTH)
)
    data_shiftreg_inst
        (

         .RD_DATA                       (wRxSrData),

         .WR_DATA                       (M_AXIS_CQ_TDATA),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    sop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrSop),

         .WR_DATA                       (wMAxisCqSop & M_AXIS_CQ_TVALID),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    eop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrEop),

         .WR_DATA                       (wMAxisCqTlast),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    valid_shiftreg_inst
        (

         .RD_DATA                       (wRxSrDataValid),

         .WR_DATA                       (M_AXIS_CQ_TVALID),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));




    shiftreg
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (C_RX_BE_W)
)
    be_shiftreg_inst
        (

         .RD_DATA                       (wRxSrBe),

         .WR_DATA                       (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (1'b0)
)
    start_flag_register
        (

         .RD_DATA                       (wStartFlag),

         .WR_DATA                       (_wStartFlag),
         .WR_EN                         (1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    o2m_ef
        (

         .MASK                          (wEndMask),

         .OFFSET_ENABLE                 (wEndFlag),
         .OFFSET                        (wEndOffset)
);

    generate
        if(C_RX_OUTPUT_STAGES == 0) begin
            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
        end else begin
            register
                #(

                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
                  .C_VALUE              (0)
)
            dw_enable
                (
                 .RD_DATA               (wRxrDataWordEnable),

                 .RST_IN                (~rValid | wHasPayload),
                 .WR_DATA               (wEndMask & wStartMask),
                 .WR_EN                 (1),

                 .CLK                   (CLK));

            pipeline
                #(

                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
                  .C_USE_MEMORY                 (0)
)
            dw_pipeline
                (

                 .WR_DATA_READY                 (),
                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
                 .RD_DATA_VALID                 (),

                 .WR_DATA                       (wRxrDataWordEnable),
                 .WR_DATA_VALID                 (1),
                 .RD_DATA_READY                 (1'b1),


                 .CLK                           (CLK),
                 .RST_IN                        (RST_IN));
        end
    endgenerate

    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) + `SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W + `SIG_TYPE_W),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
         .RD_DATA_VALID                 (wRxrDataValid),

         .WR_DATA                       ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
         .WR_DATA_VALID                 (rValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

endmodule