data/full_repos/permissive/459421171/Pipelined/fetch_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=64\'d10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk=~clk;PC=valP;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/459421171/Pipelined/fetch_test.v:58: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d PC=%d icode=%b ifun=%b rA=%d rB=%d,valC=%d,valP=%d,HF=%d,imem_error=%d,instr_Validity=%d\\n",clk,PC,icode,ifun,rA,rB,valC,valP,HF,imem_error,instr_Validity);\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fetch_test;
  reg clk;
  reg [63:0] PC;
  
  wire [3:0] icode;
  wire [3:0] ifun;
  wire [3:0] rA;
  wire [3:0] rB; 
  wire [63:0] valC;
  wire [63:0] valP;
  wire HF;
  wire instr_Validity;
  wire imem_error;

  fetch fetch(
    .clk(clk),
    .PC(PC),
    .rA(rA),
    .rB(rB),
    .iCode(icode),
    .iFun(ifun),
    
    .valC(valC),
    .valP(valP),
    .instr_Validity(instr_Validity), 
    .imem_error(imem_error),
    .HF(HF)
  );
  
  initial begin 
    clk=0;
    PC=64'd0;

    #10 clk=~clk;PC=64'd10;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    
  end 
  
  initial 
		$monitor("clk=%d PC=%d icode=%b ifun=%b rA=%d rB=%d,valC=%d,valP=%d,HF=%d,imem_error=%d,instr_Validity=%d\n",clk,PC,icode,ifun,rA,rB,valC,valP,HF,imem_error,instr_Validity);
endmodule
module fetch_test;

  reg clk;
  reg [63:0] PC;
  
  wire [3:0] icode;
  wire [3:0] ifun;
  wire [3:0] rA;
  wire [3:0] rB; 
  wire [63:0] valC;
  wire [63:0] valP;
  wire HF;
  wire instr_Validity;
  wire imem_error;

  fetch fetch(
    .clk(clk),
    .PC(PC),
    .rA(rA),
    .rB(rB),
    .iCode(icode),
    .iFun(ifun),
    
    .valC(valC),
    .valP(valP),
    .instr_Validity(instr_Validity), 
    .imem_error(imem_error),
    .HF(HF)
  );
  
  initial begin 
    clk=0;
    PC=64'd0;

    #10 clk=~clk;PC=64'd10;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
     #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    
  end 
  
  initial 
		$monitor("clk=%d PC=%d icode=%b ifun=%b rA=%d rB=%d,valC=%d,valP=%d,HF=%d,imem_error=%d,instr_Validity=%d\n",clk,PC,icode,ifun,rA,rB,valC,valP,HF,imem_error,instr_Validity);
endmodule