data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:90: syntax error, unexpected class\nDeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));\n                  ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:98: syntax error, unexpected class, expecting '['\noutput class,\n       ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:202: syntax error, unexpected IDENTIFIER\ncomplement_rejfdb CP_L1_x1 (x1, x1c);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:545: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:553: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:752: syntax error, unexpected class, expecting '['\nmodule convert16_to_1(sig_out, class);\n                               ^~~~~\n%Error: Exiting due to 6 error(s)\n"
module sigmoid_ohbk4(sig, clk, rst, x);
input [15:0] x; 
input clk;
input rst;
output[15:0] sig;
wire [1:0] s;
wire [15:0] x1,x2,x3;
wire [15:0] c1,c2;
wire co;

begin
shiftback2bit S2(x1, x, clk,rst);
shiftback3bit S3(x2, x, clk, rst);
shiftback5bit S5(x3, x, clk, rst);
ifstatement IS(x, s);
compare comp(s,x1,x2,x3,c1);
compare2 comp2(s, c2);
clockadder_rejfdb ad(co, sig, c1, c2,  1'b0);
end

endmodule
module sigmoid_ohbk4(sig, clk, rst, x);

input [15:0] x; 
input clk;
input rst;
output[15:0] sig;
wire [1:0] s;
wire [15:0] x1,x2,x3;
wire [15:0] c1,c2;
wire co;

begin
shiftback2bit S2(x1, x, clk,rst);
shiftback3bit S3(x2, x, clk, rst);
shiftback5bit S5(x3, x, clk, rst);
ifstatement IS(x, s);
compare comp(s,x1,x2,x3,c1);
compare2 comp2(s, c2);
clockadder_rejfdb ad(co, sig, c1, c2,  1'b0);
end

endmodule