data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_DECODE_32U_4_4.v
data/verilator_xmls/86308b8e-6e9b-4c19-bec4-e27a091085ba.xml
module dut_DECODE_32U_4_4 (
	in1,
	out1
	);
input [4:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 32'B00000000000000000000000000000001 << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_32U_4_4 (
	in1,
	out1
	);

input [4:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 32'B00000000000000000000000000000001 << in1;

assign out1 = asc001;
endmodule