data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:1: Cannot find include file: fetch.v\n`include "fetch.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:2: Cannot find include file: decode.v\n`include "decode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:3: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:4: Cannot find include file: Memory.v\n`include "Memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:5: Cannot find include file: pc_update.v\n`include "pc_update.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:39: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("Seq.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:40: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,PC,icode,ifun,rA,rB,valC,valP,valA,valB,valM,valE,instr_valid,Cnd,clock,PC_in,stat,imem_error);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/seq.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 7 error(s), 2 warning(s)\n'
module seq();

reg [63:0]PC_in=0;
wire [63:0]PC;
wire [3:0] icode;
wire [3:0] ifun;
wire [3:0] rA;
wire [3:0] rB;
wire [63:0]valC;
wire [63:0]valP;
wire [63:0]valA;
wire [63:0]valB;
wire [63:0]valM;
wire [63:0]valE;

wire instr_valid;
wire Cnd;
wire imem_error;
wire [1:0]stat;

reg clock;

fetch FETCH(.PC(PC_in),.icode(icode),.ifun(ifun),.rA(rA),.rB(rB),.valC(valC),.valP(valP),.clock(clock),.instr_valid(instr_valid),.imem_error(imem_error));
decode DECODE(.icode(icode),.Cnd(Cnd),.rA(rA),.rB(rB),.valA(valA),.valB(valB),.valE(valE),.valM(valM),.clock(clock));
execute EXECUTE(.icode(icode),.ifun(ifun),.valC(valC),.valA(valA),.valB(valB),.valE(valE),.Cnd(Cnd),.clock(clock));
Memory MEMORY(.icode(icode),.valE(valE),.valA(valA),.valP(valP),.instr_valid(instr_valid),.imem_error(imem_error),.valM(valM),.clock(clock),.stat(stat));
pc_update PC_UPDATE(.PC(PC),.icode(icode),.Cnd(Cnd),.valC(valC),.valM(valM),.valP(valP),.clock(clock));

integer j;

initial begin

	$dumpfile("Seq.vcd");
    	$dumpvars(0,PC,icode,ifun,rA,rB,valC,valP,valA,valB,valM,valE,instr_valid,Cnd,clock,PC_in,stat,imem_error);
	clock=0;


	for(j=0;j<600;j++) begin 

	clock=1;
	#10;
	clock=0;
	#10;
	end
end

always @(posedge clock)
    PC_in<=PC;
endmodule
module seq();


reg [63:0]PC_in=0;
wire [63:0]PC;
wire [3:0] icode;
wire [3:0] ifun;
wire [3:0] rA;
wire [3:0] rB;
wire [63:0]valC;
wire [63:0]valP;
wire [63:0]valA;
wire [63:0]valB;
wire [63:0]valM;
wire [63:0]valE;

wire instr_valid;
wire Cnd;
wire imem_error;
wire [1:0]stat;

reg clock;

fetch FETCH(.PC(PC_in),.icode(icode),.ifun(ifun),.rA(rA),.rB(rB),.valC(valC),.valP(valP),.clock(clock),.instr_valid(instr_valid),.imem_error(imem_error));
decode DECODE(.icode(icode),.Cnd(Cnd),.rA(rA),.rB(rB),.valA(valA),.valB(valB),.valE(valE),.valM(valM),.clock(clock));
execute EXECUTE(.icode(icode),.ifun(ifun),.valC(valC),.valA(valA),.valB(valB),.valE(valE),.Cnd(Cnd),.clock(clock));
Memory MEMORY(.icode(icode),.valE(valE),.valA(valA),.valP(valP),.instr_valid(instr_valid),.imem_error(imem_error),.valM(valM),.clock(clock),.stat(stat));
pc_update PC_UPDATE(.PC(PC),.icode(icode),.Cnd(Cnd),.valC(valC),.valM(valM),.valP(valP),.clock(clock));

integer j;

initial begin

	$dumpfile("Seq.vcd");
    	$dumpvars(0,PC,icode,ifun,rA,rB,valC,valP,valA,valB,valM,valE,instr_valid,Cnd,clock,PC_in,stat,imem_error);
	clock=0;


	for(j=0;j<600;j++) begin 

	clock=1;
	#10;
	clock=0;
	#10;
	end
end

always @(posedge clock)
    PC_in<=PC;
endmodule