data/full_repos/permissive/520428138/verilog/rtl/user_module_340579111348994642.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340579111348994642.v:9: Cannot find file containing module: 'clock'\nclock clock_top (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/clock\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/clock.v\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/clock.sv\n             clock\n             clock.v\n             clock.sv\n             obj_dir/clock\n             obj_dir/clock.v\n             obj_dir/clock.sv\n%Error: Exiting due to 1 error(s)\n"
module user_module_340579111348994642(
  input [7:0] io_in, 
  output [7:0] io_out
);

clock clock_top (
    .i_clk(io_in[0]),
    .i_rst(io_in[1]),
    .i_min_up(io_in[2]),
    .i_hour_up(io_in[3]),
    .i_freq(io_in[4]),
    .o_clk(io_out[0]),
    .o_latch(io_out[1]),
    .o_bit(io_out[2])
);

endmodule
module user_module_340579111348994642(
  input [7:0] io_in, 
  output [7:0] io_out
);


clock clock_top (
    .i_clk(io_in[0]),
    .i_rst(io_in[1]),
    .i_min_up(io_in[2]),
    .i_hour_up(io_in[3]),
    .i_freq(io_in[4]),
    .o_clk(io_out[0]),
    .o_latch(io_out[1]),
    .o_bit(io_out[2])
);

endmodule