data/full_repos/permissive/486598419/6.8/ram2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.8/ram2_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.8/ram2_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #40   ena=1;\n  ^\n%Error: data/full_repos/permissive/486598419/6.8/ram2_tb.v:46: Unsupported: Verilog 1995 force\n  force data=32\'b00000000_00000000_00000000_10000000;\n  ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.8/ram2_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #40  ena=1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.8/ram2_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #40  ena=0;\n   ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram2_tb();
reg clk;
reg ena;
reg wena;
reg[4:0] addr;
wire[31:0] data;

ram2 uut(clk,ena,wena,addr,data);
always
begin
	#20 clk = ~clk;
end

initial
    begin
        clk=1;
        ena=0;
        wena=1;
        addr=5'b00010;
        
  #40   ena=1;
        wena=1;
        addr=5'b00010;
  force data=32'b00000000_00000000_00000000_10000000;
        
   #40  ena=1;
        wena=0;
        addr=5'b00010;
        
   #40  ena=0;
        wena=0;
        addr=5'b00010;
     end 
endmodule
module ram2_tb();

reg clk;
reg ena;
reg wena;
reg[4:0] addr;
wire[31:0] data;

ram2 uut(clk,ena,wena,addr,data);
always
begin
	#20 clk = ~clk;
end

initial
    begin
        clk=1;
        ena=0;
        wena=1;
        addr=5'b00010;
        
  #40   ena=1;
        wena=1;
        addr=5'b00010;
  force data=32'b00000000_00000000_00000000_10000000;
        
   #40  ena=1;
        wena=0;
        addr=5'b00010;
        
   #40  ena=0;
        wena=0;
        addr=5'b00010;
     end 
endmodule