data/full_repos/permissive/481044442/BDCDrv/uart_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/uart_tx.v:49: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'bitIndex\' generates 3 bits.\n                                                                        : ... In instance uart_tx\n      if(bitIndex==7\'b111)  \n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module uart_tx(clk,reset,start,data_in,txd,done,busy);
input clk;
input reset;
input start;
input [7:0] data_in;

output reg txd;
output reg done;
output reg busy;

parameter IDLE=3'b000;
parameter START_BIT=3'b001;
parameter DATA_BITS=3'b010;
parameter STOP_BIT=3'b011;

reg[2:0] fsm=3'b000;

reg[7:0] data_in_lock;
reg[2:0] bitIndex;

always@(posedge clk or posedge reset)
begin
	if(reset) begin
			fsm<=IDLE;
			end
	else
		case(fsm)
			IDLE:begin
					txd<=1'b1;
					done<=1'b0;
					busy<=1'b0;
					bitIndex<=3'd0;
					data_in_lock<=8'd00;
					if(start) begin
								data_in_lock<=data_in;
								fsm<=START_BIT; 
							  end
					else
							fsm<=IDLE;
					end
			START_BIT:begin
						txd<=1'b0;
						busy<=1'b1;
						fsm<=DATA_BITS;
						end
			DATA_BITS:begin
						txd<=data_in_lock[bitIndex];
						if(bitIndex==7'b111)
							fsm<=STOP_BIT;
						else
							bitIndex<=bitIndex+1'b1;
						end
			STOP_BIT:begin
						done<=1'b1;
						fsm<=IDLE;
						end
		endcase
end
endmodule
module uart_tx(clk,reset,start,data_in,txd,done,busy);

input clk;
input reset;
input start;
input [7:0] data_in;

output reg txd;
output reg done;
output reg busy;

parameter IDLE=3'b000;
parameter START_BIT=3'b001;
parameter DATA_BITS=3'b010;
parameter STOP_BIT=3'b011;

reg[2:0] fsm=3'b000;

reg[7:0] data_in_lock;
reg[2:0] bitIndex;

always@(posedge clk or posedge reset)
begin
	if(reset) begin
			fsm<=IDLE;
			end
	else
		case(fsm)
			IDLE:begin
					txd<=1'b1;
					done<=1'b0;
					busy<=1'b0;
					bitIndex<=3'd0;
					data_in_lock<=8'd00;
					if(start) begin
								data_in_lock<=data_in;
								fsm<=START_BIT; 
							  end
					else
							fsm<=IDLE;
					end
			START_BIT:begin
						txd<=1'b0;
						busy<=1'b1;
						fsm<=DATA_BITS;
						end
			DATA_BITS:begin
						txd<=data_in_lock[bitIndex];
						if(bitIndex==7'b111)
							fsm<=STOP_BIT;
						else
							bitIndex<=bitIndex+1'b1;
						end
			STOP_BIT:begin
						done<=1'b1;
						fsm<=IDLE;
						end
		endcase
end
endmodule