data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:146: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'rbm_0_data\'\nmodule rbm_0_data(CLK, \n       ^~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_edges\'\nmodule rbm_0_edges(CLK, rbm_0_edges_CE0, rbm_0_edges_A0, rbm_0_edges_D0, rbm_0_edges_WE0, rbm_0_edges_WEM0, rbm_0_edges_CE2, rbm_0_edges_A2, rbm_0_edges_Q2, rbm_0_edges_CE1, rbm_0_edges_A1, rbm_0_edges_Q1,\n       ^~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_hidden_unit\'\nmodule rbm_0_hidden_unit(CLK, rbm_0_hidden_unit_CE1, rbm_0_hidden_unit_A1, rbm_0_hidden_unit_D1, rbm_0_hidden_unit_WE1, rbm_0_hidden_unit_WEM1, rbm_0_hidden_unit_CE3, rbm_0_hidden_unit_A3, rbm_0_hidden_unit_Q3, rbm_0_hidden_unit_CE0, rbm_0_hidden_unit_A0, rbm_0_hidden_unit_D0, rbm_0_hidden_unit_WE0, rbm_0_hidden_unit_WEM0, rbm_0_hidden_unit_CE2, rbm_0_hidden_unit_A2, rbm_0_hidden_unit_Q2,\n       ^~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_mt\'\nmodule rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1, \n       ^~~~~~~~\n                                                                                                : ... Top module \'rbm_0_neg\'\nmodule rbm_0_neg(CLK, rbm_0_neg_CE0, rbm_0_neg_A0, rbm_0_neg_D0, rbm_0_neg_WE0, rbm_0_neg_WEM0, rbm_0_neg_CE1, rbm_0_neg_A1, rbm_0_neg_Q1,\n       ^~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_pos\'\nmodule rbm_0_pos(CLK, rbm_0_pos_CE0, rbm_0_pos_A0, rbm_0_pos_D0, rbm_0_pos_WE0, rbm_0_pos_WEM0, rbm_0_pos_CE1, rbm_0_pos_A1, rbm_0_pos_Q1,\n       ^~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_predict_result\'\nmodule rbm_0_predict_result(CLK, rbm_0_predict_result_CE1, rbm_0_predict_result_A1, rbm_0_predict_result_Q1, rbm_0_predict_result_CE0, rbm_0_predict_result_A0, rbm_0_predict_result_D0, rbm_0_predict_result_WE0, rbm_0_predict_result_WEM0,\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'rbm_0_visibleEnergies\'\n                                                                                                : ... Top module \'pow2_mem\'\nmodule pow2_mem(CLK, RST, waddr, wdata, wen, raddr, rdata, gm_step);\n       ^~~~~~~~\n                                                                                                : ... Top module \'predict_vector_mem\'\nmodule predict_vector_mem(CLK, RST, waddr, wdata,wen, raddr, rdata, gm_step);\n       ^~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'visible_unit_mem\'\nmodule visible_unit_mem(CLK, RST, waddr0, wdata0, wen0, waddr1, wdata1, wen1, raddr, rdata, gm_step);\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:35: Input/output/inout declaration not found for port: \'RST\'\n    RST\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:159: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:275: Input/output/inout declaration not found for port: \'gm_waddr1\'\n    gm_waddr1,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:276: Input/output/inout declaration not found for port: \'gm_wen1\'\n    gm_wen1,\n    ^~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:277: Input/output/inout declaration not found for port: \'gm_wdata1\'\n    gm_wdata1,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:284: Input/output/inout declaration not found for port: \'RST\'\n    RST \n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:554: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:667: Input/output/inout declaration not found for port: \'RST\'\n    RST );\n    ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:787: Input/output/inout declaration not found for port: \'RST\'\n    RST  );\n    ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:882: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:895: Can\'t find definition of variable: \'gm_pwaddr\'\n                                                                                     : ... Suggested alternative: \'gm_waddr0\'\n                GM_addr  <= gm_pwaddr;\n                            ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:744: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:626: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:387: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:416: Can\'t find definition of variable: \'igm_step\'\n                                                                                     : ... Suggested alternative: \'gm_step\'\n            else if(igm_step & gm_wen1 ) begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:416: Can\'t find definition of variable: \'gm_wen1\'\n                                                                                     : ... Suggested alternative: \'gm_wen0\'\n            else if(igm_step & gm_wen1 ) begin\n                               ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:238: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/437995305/sim/mem_rbm_0_cmos32soi_rtl_jasper.v:117: Signal definition not found, creating implicitly: \'RST\'\n        if(RST) begin\n           ^~~\n%Error: Exiting due to 12 error(s), 7 warning(s)\n'
module rbm_0_predict_result(CLK, rbm_0_predict_result_CE1, rbm_0_predict_result_A1, rbm_0_predict_result_Q1, rbm_0_predict_result_CE0, rbm_0_predict_result_A0, rbm_0_predict_result_D0, rbm_0_predict_result_WE0, rbm_0_predict_result_WEM0,

    gm_raddr0,
    gm_rdata0,

    gm_waddr0,
    gm_wen0,
    gm_wdata0,

    gm_sel,
    gm_step,
    gm_compare,
    impl_rec,
    mismatch,
    RST );
  input CLK;

  input rbm_0_predict_result_CE1;
  input [6:0] rbm_0_predict_result_A1;
  output [3:0] rbm_0_predict_result_Q1;

  input rbm_0_predict_result_CE0;
  input [6:0] rbm_0_predict_result_A0;
  input [3:0] rbm_0_predict_result_D0;
  input rbm_0_predict_result_WE0;
  input [3:0] rbm_0_predict_result_WEM0;



  input impl_rec;
  input gm_sel;
  input gm_step;
  input gm_compare;
  output mismatch;

  input [5:0] gm_raddr0;
  output [3:0]  gm_rdata0;

  input [5:0] gm_waddr0;
  input        gm_wen0;
  input [3:0]  gm_wdata0;

  wire [6:0] gm_praddr = gm_sel ? {1'b0,gm_raddr0} + `NUM_MOVIE_MAX : {1'b0,gm_raddr0} ;
  wire [6:0] gm_pwaddr = gm_sel ? {1'b0,gm_waddr0} + `NUM_MOVIE_MAX : {1'b0,gm_waddr0} ;



   wire concrete_val_0;
   wire concrete_val_1;
    jasper_model_mpram #( 
        .READ_PORTS(1+1),
        .WRITE_PORTS(1),
        .ADDR_WIDTH(7),
        .DATA_WIDTH(4),
        .MAX_DEPTH(8),
        .MEM_STYLE(0),
        .RESET_STYLE(0),
        .RD_DATA_DLY(0)
        )
    mem_mpram
    (
        .clk(CLR),
        .rstN(~RST),
        .addr_rd( 
            { rbm_0_predict_result_A1, gm_praddr  }),
        .data_rd(
            { rbm_0_predict_result_Q1, gm_rdata0}),
        .read_allocate(
            {   impl_rec & rbm_0_predict_result_CE1, 
                gm_step} ),
        .read( {1'b1,1'b1} ),

        .write( {1'b0} ),
        .write_allocate( {1'b0} ),
        .addr_wr({16'd0}),
        .data_wr({1'd0}),
        .concrete({concrete_val_0, concrete_val_1 })
    );
    



    reg [3:0]  IMPL_data;
    reg [6:0] IMPL_addr;
    reg        IMPL_dirty;

    reg [3:0]  GM_data;
    reg [6:0] GM_addr;
    reg        GM_dirty;

    always @(posedge CLK) begin
        if(RST) begin
            IMPL_dirty <= 1'b0;
            GM_dirty <= 1'b0;
        end
        else begin
            if(impl_rec & rbm_0_predict_result_WE0 & rbm_0_predict_result_CE0)  begin
                IMPL_dirty <= 1'b1;
                IMPL_addr  <= rbm_0_predict_result_A0;
                IMPL_data  <= rbm_0_predict_result_D0;
            end

            if (gm_step & gm_wen0) begin
                GM_dirty <= 1'b1;
                GM_addr  <= gm_pwaddr;
                GM_data  <= gm_wdata0;
            end
        end
    end

    assign mismatch = (~gm_compare) ? 1'b0 :
                      (IMPL_dirty != GM_dirty) ? 1'b1 :
                      (IMPL_addr != GM_addr) ? 1'b1 :
                      (IMPL_data != GM_data) ? 1'b1 :
                      1'b0;
    endmodule
module rbm_0_predict_result(CLK, rbm_0_predict_result_CE1, rbm_0_predict_result_A1, rbm_0_predict_result_Q1, rbm_0_predict_result_CE0, rbm_0_predict_result_A0, rbm_0_predict_result_D0, rbm_0_predict_result_WE0, rbm_0_predict_result_WEM0,

    gm_raddr0,
    gm_rdata0,

    gm_waddr0,
    gm_wen0,
    gm_wdata0,

    gm_sel,
    gm_step,
    gm_compare,
    impl_rec,
    mismatch,
    RST );

  input CLK;

  input rbm_0_predict_result_CE1;
  input [6:0] rbm_0_predict_result_A1;
  output [3:0] rbm_0_predict_result_Q1;

  input rbm_0_predict_result_CE0;
  input [6:0] rbm_0_predict_result_A0;
  input [3:0] rbm_0_predict_result_D0;
  input rbm_0_predict_result_WE0;
  input [3:0] rbm_0_predict_result_WEM0;



  input impl_rec;
  input gm_sel;
  input gm_step;
  input gm_compare;
  output mismatch;

  input [5:0] gm_raddr0;
  output [3:0]  gm_rdata0;

  input [5:0] gm_waddr0;
  input        gm_wen0;
  input [3:0]  gm_wdata0;

  wire [6:0] gm_praddr = gm_sel ? {1'b0,gm_raddr0} + `NUM_MOVIE_MAX : {1'b0,gm_raddr0} ;
  wire [6:0] gm_pwaddr = gm_sel ? {1'b0,gm_waddr0} + `NUM_MOVIE_MAX : {1'b0,gm_waddr0} ;



   wire concrete_val_0;
   wire concrete_val_1;
    jasper_model_mpram #( 
        .READ_PORTS(1+1),
        .WRITE_PORTS(1),
        .ADDR_WIDTH(7),
        .DATA_WIDTH(4),
        .MAX_DEPTH(8),
        .MEM_STYLE(0),
        .RESET_STYLE(0),
        .RD_DATA_DLY(0)
        )
    mem_mpram
    (
        .clk(CLR),
        .rstN(~RST),
        .addr_rd( 
            { rbm_0_predict_result_A1, gm_praddr  }),
        .data_rd(
            { rbm_0_predict_result_Q1, gm_rdata0}),
        .read_allocate(
            {   impl_rec & rbm_0_predict_result_CE1, 
                gm_step} ),
        .read( {1'b1,1'b1} ),

        .write( {1'b0} ),
        .write_allocate( {1'b0} ),
        .addr_wr({16'd0}),
        .data_wr({1'd0}),
        .concrete({concrete_val_0, concrete_val_1 })
    );
    



    reg [3:0]  IMPL_data;
    reg [6:0] IMPL_addr;
    reg        IMPL_dirty;

    reg [3:0]  GM_data;
    reg [6:0] GM_addr;
    reg        GM_dirty;

    always @(posedge CLK) begin
        if(RST) begin
            IMPL_dirty <= 1'b0;
            GM_dirty <= 1'b0;
        end
        else begin
            if(impl_rec & rbm_0_predict_result_WE0 & rbm_0_predict_result_CE0)  begin
                IMPL_dirty <= 1'b1;
                IMPL_addr  <= rbm_0_predict_result_A0;
                IMPL_data  <= rbm_0_predict_result_D0;
            end

            if (gm_step & gm_wen0) begin
                GM_dirty <= 1'b1;
                GM_addr  <= gm_pwaddr;
                GM_data  <= gm_wdata0;
            end
        end
    end

    assign mismatch = (~gm_compare) ? 1'b0 :
                      (IMPL_dirty != GM_dirty) ? 1'b1 :
                      (IMPL_addr != GM_addr) ? 1'b1 :
                      (IMPL_data != GM_data) ? 1'b1 :
                      1'b0;
    endmodule