data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:868: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:869: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:870: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:878: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:879: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:880: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:898: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module interface_top (
  input  wire        clk,
  input  wire        rst,
  input  wire        sync,
  input  wire        cs,
  input  wire [ 4:0] data_addr_i,
  input  wire [ 3:0] readout_addr,
  input  wire [31:0] data_in,
  output reg  [31:0] data_out,
  output wire        done_o,
  output wire        mem_set_done_o
);

  localparam W = 16;
  localparam N = 3;



  reg [31:0] next_data_out;


  reg  [2 * W * N * N - 1 : 0] input_registers;
  reg  [2 * W * N * N - 1 : 0] next_input_registers;
  wire [    W * N * N - 1 : 0] C_mat;






  wire [W * N * N - 1 : 0] A_mat;
  wire [W * N * N - 1 : 0] B_mat;

  assign A_mat = input_registers[        0 +: W * N * N];
  assign B_mat = input_registers[W * N * N +: W * N * N];



  reg [2:0]      state;
  reg [2:0] next_state;

  wire [2:0] IDLE    = 3'b000;
  wire [2:0] LOAD    = 3'b001;
  wire [2:0] PROCESS = 3'b010;


  wire [W * N - 1 : 0] A_in;
  wire [W * N - 1 : 0] B_in;

  control #(.W(W), .N(N)) control_inst(
    .i_clk(clk),
    .i_rst(rst),
    .i_en(cs),
    .i_mode(1'b1),
    .i_A(A_mat),
    .i_B(B_mat),
    .o_C(C_mat),
    .o_done(done_o)
  );



  reg [17:0] memory_set;
  reg [17:0] next_memory_set;



  always @(posedge clk) begin

    if (rst | sync) begin

      state           <= IDLE;
      data_out        <= 32'b0;
      memory_set      <= 18'b0;
      input_registers <= 288'b0;
    end
    else begin
      state           <= next_state;
      memory_set      <= next_memory_set;
      input_registers <= next_input_registers;
      data_out 	      <= next_data_out;
    end
  end








  always @(*) begin
    case (state)
      IDLE: begin
	next_state = cs ? PROCESS : IDLE;
      end
      PROCESS: begin
	next_state = (done_o | ~cs) ? IDLE : PROCESS;
      end
      default: begin
	next_state = IDLE;
      end
    endcase
  end



  always @(*) begin
    next_input_registers = input_registers;
    case (data_addr_i)
      5'b00000: begin
	next_input_registers[5'b00000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00001: begin
	next_input_registers[5'b00001 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00010: begin
	next_input_registers[5'b00010 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00011: begin
	next_input_registers[5'b00011 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00100: begin
	next_input_registers[5'b00100 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00101: begin
	next_input_registers[5'b00101 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00110: begin
	next_input_registers[5'b00110 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00111: begin
	next_input_registers[5'b00111 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01000: begin
	next_input_registers[5'b01000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01001: begin
	next_input_registers[5'b01001 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01010: begin
	next_input_registers[5'b01010 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01011: begin
	next_input_registers[5'b01011 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01100: begin
	next_input_registers[5'b01100 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01101: begin
	next_input_registers[5'b01101 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01110: begin
	next_input_registers[5'b01110 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01111: begin
	next_input_registers[5'b01111 * W +: W] = data_in[W - 1 : 0];
      end
      5'b10000: begin
	next_input_registers[5'b10000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b10001: begin
	next_input_registers[5'b10001 * W +: W] = data_in[W - 1 : 0];
      end

      default: begin
	next_input_registers = input_registers;
      end
    endcase
  end


  always @(*) begin
    next_memory_set = memory_set;
    case (data_addr_i)
      5'b00000: begin
        next_memory_set = memory_set | (18'b1 << 0);
      end
      5'b00001: begin
        next_memory_set = memory_set | (18'b1 << 1);
      end
      5'b00010: begin
        next_memory_set = memory_set | (18'b1 << 2);
      end
      5'b00011: begin
        next_memory_set = memory_set | (18'b1 << 3);
      end
      5'b00100: begin
        next_memory_set = memory_set | (18'b1 << 4);
      end
      5'b00101: begin
        next_memory_set = memory_set | (18'b1 << 5);
      end
      5'b00110: begin
        next_memory_set = memory_set | (18'b1 << 6);
      end
      5'b00111: begin
        next_memory_set = memory_set | (18'b1 << 7);
      end
      5'b01000: begin
        next_memory_set = memory_set | (18'b1 << 8);
      end
      5'b01001: begin
        next_memory_set = memory_set | (18'b1 << 9);
      end
      5'b01010: begin
        next_memory_set = memory_set | (18'b1 << 10);
      end
      5'b01011: begin
        next_memory_set = memory_set | (18'b1 << 11);
      end
      5'b01100: begin
        next_memory_set = memory_set | (18'b1 << 12);
      end
      5'b01101: begin
        next_memory_set = memory_set | (18'b1 << 13);
      end
      5'b01110: begin
        next_memory_set = memory_set | (18'b1 << 14);
      end
      5'b01111: begin
        next_memory_set = memory_set | (18'b1 << 15);
      end
      5'b10000: begin
        next_memory_set = memory_set | (18'b1 << 16);
      end
      5'b10001: begin
        next_memory_set = memory_set | (18'b1 << 17);
      end
      default: begin
        next_memory_set = memory_set;
      end
    endcase
  end

  assign mem_set_done_o = memory_set == {(18){1'b1}};


  always @(*) begin
    next_data_out = data_out;
    case (readout_addr)
      4'b0000: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0000 * W +: W];
      end
      4'b0001: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0001 * W +: W];
      end
      4'b0010: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0010 * W +: W];
      end
      4'b0011: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0011 * W +: W];
      end
      4'b0100: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0100 * W +: W];
      end
      4'b0101: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0101 * W +: W];
      end
      4'b0110: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0110 * W +: W];
      end
      4'b0111: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0111 * W +: W];
      end
      4'b1000: begin
        next_data_out[W - 1 : 0] = C_mat[4'b1000 * W +: W];
      end

      default: begin
	next_data_out = data_out;
      end
    endcase
  end

endmodule
module interface_top (
  input  wire        clk,
  input  wire        rst,
  input  wire        sync,
  input  wire        cs,
  input  wire [ 4:0] data_addr_i,
  input  wire [ 3:0] readout_addr,
  input  wire [31:0] data_in,
  output reg  [31:0] data_out,
  output wire        done_o,
  output wire        mem_set_done_o
);


  localparam W = 16;
  localparam N = 3;



  reg [31:0] next_data_out;


  reg  [2 * W * N * N - 1 : 0] input_registers;
  reg  [2 * W * N * N - 1 : 0] next_input_registers;
  wire [    W * N * N - 1 : 0] C_mat;






  wire [W * N * N - 1 : 0] A_mat;
  wire [W * N * N - 1 : 0] B_mat;

  assign A_mat = input_registers[        0 +: W * N * N];
  assign B_mat = input_registers[W * N * N +: W * N * N];



  reg [2:0]      state;
  reg [2:0] next_state;

  wire [2:0] IDLE    = 3'b000;
  wire [2:0] LOAD    = 3'b001;
  wire [2:0] PROCESS = 3'b010;


  wire [W * N - 1 : 0] A_in;
  wire [W * N - 1 : 0] B_in;

  control #(.W(W), .N(N)) control_inst(
    .i_clk(clk),
    .i_rst(rst),
    .i_en(cs),
    .i_mode(1'b1),
    .i_A(A_mat),
    .i_B(B_mat),
    .o_C(C_mat),
    .o_done(done_o)
  );



  reg [17:0] memory_set;
  reg [17:0] next_memory_set;



  always @(posedge clk) begin

    if (rst | sync) begin

      state           <= IDLE;
      data_out        <= 32'b0;
      memory_set      <= 18'b0;
      input_registers <= 288'b0;
    end
    else begin
      state           <= next_state;
      memory_set      <= next_memory_set;
      input_registers <= next_input_registers;
      data_out 	      <= next_data_out;
    end
  end








  always @(*) begin
    case (state)
      IDLE: begin
	next_state = cs ? PROCESS : IDLE;
      end
      PROCESS: begin
	next_state = (done_o | ~cs) ? IDLE : PROCESS;
      end
      default: begin
	next_state = IDLE;
      end
    endcase
  end



  always @(*) begin
    next_input_registers = input_registers;
    case (data_addr_i)
      5'b00000: begin
	next_input_registers[5'b00000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00001: begin
	next_input_registers[5'b00001 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00010: begin
	next_input_registers[5'b00010 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00011: begin
	next_input_registers[5'b00011 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00100: begin
	next_input_registers[5'b00100 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00101: begin
	next_input_registers[5'b00101 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00110: begin
	next_input_registers[5'b00110 * W +: W] = data_in[W - 1 : 0];
      end
      5'b00111: begin
	next_input_registers[5'b00111 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01000: begin
	next_input_registers[5'b01000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01001: begin
	next_input_registers[5'b01001 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01010: begin
	next_input_registers[5'b01010 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01011: begin
	next_input_registers[5'b01011 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01100: begin
	next_input_registers[5'b01100 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01101: begin
	next_input_registers[5'b01101 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01110: begin
	next_input_registers[5'b01110 * W +: W] = data_in[W - 1 : 0];
      end
      5'b01111: begin
	next_input_registers[5'b01111 * W +: W] = data_in[W - 1 : 0];
      end
      5'b10000: begin
	next_input_registers[5'b10000 * W +: W] = data_in[W - 1 : 0];
      end
      5'b10001: begin
	next_input_registers[5'b10001 * W +: W] = data_in[W - 1 : 0];
      end

      default: begin
	next_input_registers = input_registers;
      end
    endcase
  end


  always @(*) begin
    next_memory_set = memory_set;
    case (data_addr_i)
      5'b00000: begin
        next_memory_set = memory_set | (18'b1 << 0);
      end
      5'b00001: begin
        next_memory_set = memory_set | (18'b1 << 1);
      end
      5'b00010: begin
        next_memory_set = memory_set | (18'b1 << 2);
      end
      5'b00011: begin
        next_memory_set = memory_set | (18'b1 << 3);
      end
      5'b00100: begin
        next_memory_set = memory_set | (18'b1 << 4);
      end
      5'b00101: begin
        next_memory_set = memory_set | (18'b1 << 5);
      end
      5'b00110: begin
        next_memory_set = memory_set | (18'b1 << 6);
      end
      5'b00111: begin
        next_memory_set = memory_set | (18'b1 << 7);
      end
      5'b01000: begin
        next_memory_set = memory_set | (18'b1 << 8);
      end
      5'b01001: begin
        next_memory_set = memory_set | (18'b1 << 9);
      end
      5'b01010: begin
        next_memory_set = memory_set | (18'b1 << 10);
      end
      5'b01011: begin
        next_memory_set = memory_set | (18'b1 << 11);
      end
      5'b01100: begin
        next_memory_set = memory_set | (18'b1 << 12);
      end
      5'b01101: begin
        next_memory_set = memory_set | (18'b1 << 13);
      end
      5'b01110: begin
        next_memory_set = memory_set | (18'b1 << 14);
      end
      5'b01111: begin
        next_memory_set = memory_set | (18'b1 << 15);
      end
      5'b10000: begin
        next_memory_set = memory_set | (18'b1 << 16);
      end
      5'b10001: begin
        next_memory_set = memory_set | (18'b1 << 17);
      end
      default: begin
        next_memory_set = memory_set;
      end
    endcase
  end

  assign mem_set_done_o = memory_set == {(18){1'b1}};


  always @(*) begin
    next_data_out = data_out;
    case (readout_addr)
      4'b0000: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0000 * W +: W];
      end
      4'b0001: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0001 * W +: W];
      end
      4'b0010: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0010 * W +: W];
      end
      4'b0011: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0011 * W +: W];
      end
      4'b0100: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0100 * W +: W];
      end
      4'b0101: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0101 * W +: W];
      end
      4'b0110: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0110 * W +: W];
      end
      4'b0111: begin
        next_data_out[W - 1 : 0] = C_mat[4'b0111 * W +: W];
      end
      4'b1000: begin
        next_data_out[W - 1 : 0] = C_mat[4'b1000 * W +: W];
      end

      default: begin
	next_data_out = data_out;
      end
    endcase
  end

endmodule