data/full_repos/permissive/502536946/PWM_Generator_Verilog.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:23: Signal definition not found, creating implicitly: \'clk_div\'\n divfreq D1(.CLK(clk), .speed_ctrl(speed_ctrl), .CLK_time(clk_div));\n                                                          ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:37: Signal definition not found, creating implicitly: \'print_delay_1\'\n assign print_delay_1 = delay_1;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:54: Signal definition not found, creating implicitly: \'print_delay_2\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_2 = delay_2;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:73: Signal definition not found, creating implicitly: \'print_delay_3\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_3 = delay_3;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:92: Signal definition not found, creating implicitly: \'print_delay_4\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_4 = delay_4;\n        ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:131: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                                : ... In instance PWM_Generator_Verilog.D1\n   Count <= 25\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:128: Operator GT expects 26 bits on the RHS, but RHS\'s VARREF \'sp\' generates 15 bits.\n                                                                                : ... In instance PWM_Generator_Verilog.D1\n  if(Count > sp) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:29: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt1 <= 4\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:44: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt2 <= 6\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:62: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt3 <= 8\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:81: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt4 <= 8\'b0;\n          ^~\n%Error: Exiting due to 11 warning(s)\n'
module PWM_Generator_Verilog(
    input           clk,
	 input			  speed_ctrl,
    output          led_out
);

	parameter   DELAY1 = 1;
	parameter   DELAY2 = 5;
	parameter   DELAY3 = 20;
	parameter   DELAY4 = 20;


	wire           delay_1, delay_2, delay_3, delay_4;
	reg            pwm;
	reg     [4:0]	cnt1;
	reg     [6:0]  cnt2;
	reg     [8:0]  cnt3;
	reg     [8:0]  cnt4;
	reg            display_state;
	
	
	divfreq D1(.CLK(clk), .speed_ctrl(speed_ctrl), .CLK_time(clk_div));



	always @(posedge clk_div)begin
		 if(cnt1 == DELAY1 - 1'b1)
			  cnt1 <= 4'b0;
		 else 
			  cnt1 <= cnt1 + 1'b1;
	end

	assign delay_1 = (cnt1 == DELAY1 - 1'b1)? 1'b1:1'b0;


	assign print_delay_1 = delay_1;



	always @(posedge clk_div)begin
		 if(delay_1 == 1'b1)begin
			  if(cnt2 == DELAY2 - 1'b1)    
					cnt2 <= 6'b0;
			  else 
					cnt2 <= cnt2 + 1'b1;
		 end
		 else 
			  cnt2 <= cnt2;
	end
	assign delay_2 = ((delay_1 == 1'b1) && (cnt2 == DELAY2 - 1'b1))? 1'b1:1'b0;


	assign print_delay_2 = delay_2;

		

	always @(posedge clk_div)begin
		 if(delay_2)
		 begin
				if(cnt3 == DELAY3 - 1'b1)
					cnt3 <= 8'b0;
			  else 
					cnt3 <= cnt3 + 1'b1;
		  end
		 else 
			  cnt3 <= cnt3;    
	end

	assign delay_3 = ((delay_2 == 1'b1) && (cnt3 == DELAY3 - 1'b1))? 1'b1:1'b0;


	assign print_delay_3 = delay_3;
	
	

	always @(posedge clk_div)begin
		 if(delay_3)
		 begin
				if(cnt4 == DELAY4 - 1'b1)
					cnt4 <= 8'b0;
			  else 
					cnt4 <= cnt4 + 1'b1;
		  end
		 else 
			  cnt4 <= cnt4;    
	end

	assign delay_4 = ((delay_3 == 1'b1) && (cnt4 == DELAY4 - 1'b1))? 1'b1:1'b0;


	assign print_delay_4 = delay_4;
	
	


	always @(posedge clk_div)begin
		 if(delay_4)
			  display_state <= ~display_state;
		 else 
			  display_state <= display_state;
	end


	always @(posedge clk_div)begin
		 case(display_state)
				1'b0: pwm <= (cnt3 < cnt4)? 1'b1:1'b0;
				1'b1: pwm <= (cnt3 < cnt4)? 1'b0:1'b1;
				default: pwm <= pwm;
		 endcase
	end

	assign led_out = pwm;

endmodule
module PWM_Generator_Verilog(
    input           clk,
	 input			  speed_ctrl,
    output          led_out
);


	parameter   DELAY1 = 1;
	parameter   DELAY2 = 5;
	parameter   DELAY3 = 20;
	parameter   DELAY4 = 20;


	wire           delay_1, delay_2, delay_3, delay_4;
	reg            pwm;
	reg     [4:0]	cnt1;
	reg     [6:0]  cnt2;
	reg     [8:0]  cnt3;
	reg     [8:0]  cnt4;
	reg            display_state;
	
	
	divfreq D1(.CLK(clk), .speed_ctrl(speed_ctrl), .CLK_time(clk_div));



	always @(posedge clk_div)begin
		 if(cnt1 == DELAY1 - 1'b1)
			  cnt1 <= 4'b0;
		 else 
			  cnt1 <= cnt1 + 1'b1;
	end

	assign delay_1 = (cnt1 == DELAY1 - 1'b1)? 1'b1:1'b0;


	assign print_delay_1 = delay_1;



	always @(posedge clk_div)begin
		 if(delay_1 == 1'b1)begin
			  if(cnt2 == DELAY2 - 1'b1)    
					cnt2 <= 6'b0;
			  else 
					cnt2 <= cnt2 + 1'b1;
		 end
		 else 
			  cnt2 <= cnt2;
	end
	assign delay_2 = ((delay_1 == 1'b1) && (cnt2 == DELAY2 - 1'b1))? 1'b1:1'b0;


	assign print_delay_2 = delay_2;

		

	always @(posedge clk_div)begin
		 if(delay_2)
		 begin
				if(cnt3 == DELAY3 - 1'b1)
					cnt3 <= 8'b0;
			  else 
					cnt3 <= cnt3 + 1'b1;
		  end
		 else 
			  cnt3 <= cnt3;    
	end

	assign delay_3 = ((delay_2 == 1'b1) && (cnt3 == DELAY3 - 1'b1))? 1'b1:1'b0;


	assign print_delay_3 = delay_3;
	
	

	always @(posedge clk_div)begin
		 if(delay_3)
		 begin
				if(cnt4 == DELAY4 - 1'b1)
					cnt4 <= 8'b0;
			  else 
					cnt4 <= cnt4 + 1'b1;
		  end
		 else 
			  cnt4 <= cnt4;    
	end

	assign delay_4 = ((delay_3 == 1'b1) && (cnt4 == DELAY4 - 1'b1))? 1'b1:1'b0;


	assign print_delay_4 = delay_4;
	
	


	always @(posedge clk_div)begin
		 if(delay_4)
			  display_state <= ~display_state;
		 else 
			  display_state <= display_state;
	end


	always @(posedge clk_div)begin
		 case(display_state)
				1'b0: pwm <= (cnt3 < cnt4)? 1'b1:1'b0;
				1'b1: pwm <= (cnt3 < cnt4)? 1'b0:1'b1;
				default: pwm <= pwm;
		 endcase
	end

	assign led_out = pwm;

endmodule