data/full_repos/permissive/506562943/DigitalCircuits/1-basic-logic-gates/rtl/not_and_or.v
data/verilator_xmls/e08a4c5c-3a9c-428a-b31b-a3e951ea0331.xml
module not_and_or_gate (
	input k0,
	input k1,
	input k2,
	input k3,
	
	output l0,
	output l1,
	output l2
);



assign l0 = !(!k0);
assign l1 = ((!k1) && (!k2));
assign l2 = ((!k2) || (!k3));

endmodule
module not_and_or_gate (
	input k0,
	input k1,
	input k2,
	input k3,
	
	output l0,
	output l1,
	output l2
);




assign l0 = !(!k0);
assign l1 = ((!k1) && (!k2));
assign l2 = ((!k2) || (!k3));

endmodule