data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #2 BUT1 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #8 BUT1 = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb ();

  wire LED1;
  wire LED2;

  reg  CLK = 0;
  reg  BUT1 = 0;

  localparam ITERATIONS = 100;

  always begin
    #1 CLK = ~CLK;
  end

  always begin
    #2 BUT1 = 1'b0;
    #8 BUT1 = 1'b1;
  end

  top uut (
      .CLK (CLK),
      .BUT1(BUT1),
      .LED1(LED1),
      .LED2(LED2)
  );

  initial begin
    $dumpfile("top_tb.vcd");
    $dumpvars(0, top_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_tb ();


  wire LED1;
  wire LED2;

  reg  CLK = 0;
  reg  BUT1 = 0;

  localparam ITERATIONS = 100;

  always begin
    #1 CLK = ~CLK;
  end

  always begin
    #2 BUT1 = 1'b0;
    #8 BUT1 = 1'b1;
  end

  top uut (
      .CLK (CLK),
      .BUT1(BUT1),
      .LED1(LED1),
      .LED2(LED2)
  );

  initial begin
    $dumpfile("top_tb.vcd");
    $dumpvars(0, top_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule