data/full_repos/permissive/496194828/sasebo_giii_aes/chip_sasebo_giii_aes.v
1: b"%Error: data/full_repos/permissive/496194828/sasebo_giii_aes/chip_sasebo_giii_aes.v:131: Cannot find file containing module: 'IBUFG'\n   IBUFG u10 (.I(clkin), .O(refclk)); \n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/496194828/sasebo_giii_aes,data/full_repos/permissive/496194828/IBUFG\n             data/full_repos/permissive/496194828/sasebo_giii_aes,data/full_repos/permissive/496194828/IBUFG.v\n             data/full_repos/permissive/496194828/sasebo_giii_aes,data/full_repos/permissive/496194828/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/496194828/sasebo_giii_aes/chip_sasebo_giii_aes.v:142: Cannot find file containing module: 'BUFG'\n   BUFG  u12 (.I(refclk),   .O(clk));\n   ^~~~\n%Error: data/full_repos/permissive/496194828/sasebo_giii_aes/chip_sasebo_giii_aes.v:89: Cannot find file containing module: 'LBUS_IF'\n   LBUS_IF lbus_if\n   ^~~~~~~\n%Error: data/full_repos/permissive/496194828/sasebo_giii_aes/chip_sasebo_giii_aes.v:105: Cannot find file containing module: 'aes128_table_ecb'\n   aes128_table_ecb    aes128_table_ecb \n   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module CHIP_SASEBO_GIII_AES
  (
   lbus_di_a, lbus_do, lbus_wrn, lbus_rdn,
   lbus_clkn, lbus_rstn,


   gpio_startn, gpio_endn, gpio_exec, led,


   osc_en_b);
   


   input [15:0]  lbus_di_a;
   output [15:0] lbus_do;
   input         lbus_wrn, lbus_rdn;
   input         lbus_clkn, lbus_rstn;


   output        gpio_startn, gpio_endn, gpio_exec;
   output [9:0]  led;


   output        osc_en_b;



   wire         clk, rst;


   reg [15:0]   lbus_a, lbus_di;
   

   wire [127:0] blk_kin, blk_din, blk_dout;
   wire         blk_krdy, blk_kvld, blk_drdy, blk_dvld;
   wire         blk_encdec, blk_en, blk_rstn, blk_busy;
   reg          blk_drdy_delay;
  

   assign led[0] = rst;
   assign led[1] = lbus_rstn;
   assign led[2] = 1'b0;
   assign led[3] = blk_rstn;
   assign led[4] = blk_encdec;
   assign led[5] = blk_krdy;
   assign led[6] = blk_kvld;
   assign led[7] = 1'b0;
   assign led[8] = blk_dvld;
   assign led[9] = blk_busy;

   assign osc_en_b = 1'b0;

   always @(posedge clk) if (lbus_wrn)  lbus_a  <= lbus_di_a;
   always @(posedge clk) if (~lbus_wrn) lbus_di <= lbus_di_a;

   LBUS_IF lbus_if
     (.lbus_a(lbus_a), .lbus_di(lbus_di), .lbus_do(lbus_do),
      .lbus_wr(lbus_wrn), .lbus_rd(lbus_rdn),
      .blk_kin(blk_kin), .blk_din(blk_din), .blk_dout(blk_dout),
      .blk_krdy(blk_krdy), .blk_drdy(blk_drdy), 
      .blk_kvld(blk_kvld), .blk_dvld(blk_dvld),
      .blk_encdec(blk_encdec), .blk_en(blk_en), .blk_rstn(blk_rstn),
      .clk(clk), .rst(rst));


   assign gpio_startn = ~blk_drdy;
   assign gpio_endn   = 1'b0;
   assign gpio_exec   = 1'b0;

   always @(posedge clk) blk_drdy_delay <= blk_drdy;

   aes128_table_ecb    aes128_table_ecb 
     (.key_in(blk_kin), .text_in(blk_din), .text_out(blk_dout),
      .key_exp(blk_krdy), .start(blk_drdy_delay), .key_val(blk_kvld), .text_val(blk_dvld),
.busy(blk_busy),
      .clock(clk), .resetn(blk_rstn));


   MK_CLKRST mk_clkrst (.clkin(lbus_clkn), .rstnin(lbus_rstn),
                        .clk(clk), .rst(rst));
endmodule
module CHIP_SASEBO_GIII_AES
  (
   lbus_di_a, lbus_do, lbus_wrn, lbus_rdn,
   lbus_clkn, lbus_rstn,


   gpio_startn, gpio_endn, gpio_exec, led,


   osc_en_b);

   


   input [15:0]  lbus_di_a;
   output [15:0] lbus_do;
   input         lbus_wrn, lbus_rdn;
   input         lbus_clkn, lbus_rstn;


   output        gpio_startn, gpio_endn, gpio_exec;
   output [9:0]  led;


   output        osc_en_b;



   wire         clk, rst;


   reg [15:0]   lbus_a, lbus_di;
   

   wire [127:0] blk_kin, blk_din, blk_dout;
   wire         blk_krdy, blk_kvld, blk_drdy, blk_dvld;
   wire         blk_encdec, blk_en, blk_rstn, blk_busy;
   reg          blk_drdy_delay;
  

   assign led[0] = rst;
   assign led[1] = lbus_rstn;
   assign led[2] = 1'b0;
   assign led[3] = blk_rstn;
   assign led[4] = blk_encdec;
   assign led[5] = blk_krdy;
   assign led[6] = blk_kvld;
   assign led[7] = 1'b0;
   assign led[8] = blk_dvld;
   assign led[9] = blk_busy;

   assign osc_en_b = 1'b0;

   always @(posedge clk) if (lbus_wrn)  lbus_a  <= lbus_di_a;
   always @(posedge clk) if (~lbus_wrn) lbus_di <= lbus_di_a;

   LBUS_IF lbus_if
     (.lbus_a(lbus_a), .lbus_di(lbus_di), .lbus_do(lbus_do),
      .lbus_wr(lbus_wrn), .lbus_rd(lbus_rdn),
      .blk_kin(blk_kin), .blk_din(blk_din), .blk_dout(blk_dout),
      .blk_krdy(blk_krdy), .blk_drdy(blk_drdy), 
      .blk_kvld(blk_kvld), .blk_dvld(blk_dvld),
      .blk_encdec(blk_encdec), .blk_en(blk_en), .blk_rstn(blk_rstn),
      .clk(clk), .rst(rst));


   assign gpio_startn = ~blk_drdy;
   assign gpio_endn   = 1'b0;
   assign gpio_exec   = 1'b0;

   always @(posedge clk) blk_drdy_delay <= blk_drdy;

   aes128_table_ecb    aes128_table_ecb 
     (.key_in(blk_kin), .text_in(blk_din), .text_out(blk_dout),
      .key_exp(blk_krdy), .start(blk_drdy_delay), .key_val(blk_kvld), .text_val(blk_dvld),
.busy(blk_busy),
      .clock(clk), .resetn(blk_rstn));


   MK_CLKRST mk_clkrst (.clkin(lbus_clkn), .rstnin(lbus_rstn),
                        .clk(clk), .rst(rst));
endmodule