data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:73: Signal definition not found, creating implicitly: \'rx_data_stp\'\n                                                                          : ... Suggested alternative: \'rx_data\'\nassign rx_data_stp=rx_data;\n       ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:17: Cannot find file containing module: \'power_on_reset\'\npower_on_reset u1 (.clk(clk),.reset(reset));\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset.v\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset.sv\n             power_on_reset\n             power_on_reset.v\n             power_on_reset.sv\n             obj_dir/power_on_reset\n             obj_dir/power_on_reset.v\n             obj_dir/power_on_reset.sv\n%Error: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:23: Cannot find file containing module: \'led_drive\'\nled_drive u2 (.clk(clk),.reset(reset),.led1(led1),.led2(led2),.data_out(data_out));\n^~~~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:32: Cannot find file containing module: \'baudrate_generate\'\nbaudrate_generate u4(.clk(clk),.reset(reset),.txclk(txclk),.rxclk(rxclk),.txclkx4(txclkx4),.rxclkx4(rxclkx4));\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:46: Cannot find file containing module: \'upload_data\'\nupload_data upload_data_u1(.clk(txclk),.reset(reset),.tx_pulse(tx_pulse),.up_bytes(up_bytes));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:49: Cannot find file containing module: \'uart_tx\'\nuart_tx u6(.clk(txclk),.reset(reset),.start(tx_pulse),.data_in(up_bytes),.txd(txd),.done(done),.busy(busy));\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/BDCDrv.v:73: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_data\' generates 8 bits.\n                                                                       : ... In instance BDCDrv\nassign rx_data_stp=rx_data;\n                  ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module BDCDrv(clk,rxd,led1,led2,txd,txclkx4,rxclkx4,fifo_full);



input clk;
input rxd;

output led1;
output led2;
output txd;
output txclkx4;
output rxclkx4;
output fifo_full;


wire reset;
power_on_reset u1 (.clk(clk),.reset(reset));




wire [7:0] data_out;
led_drive u2 (.clk(clk),.reset(reset),.led1(led1),.led2(led2),.data_out(data_out));






wire txclk;
wire rxclk;
baudrate_generate u4(.clk(clk),.reset(reset),.txclk(txclk),.rxclk(rxclk),.txclkx4(txclkx4),.rxclkx4(rxclkx4));











wire tx_pulse;
wire [7:0] up_bytes;
upload_data upload_data_u1(.clk(txclk),.reset(reset),.tx_pulse(tx_pulse),.up_bytes(up_bytes));
wire done;
wire busy;
uart_tx u6(.clk(txclk),.reset(reset),.start(tx_pulse),.data_in(up_bytes),.txd(txd),.done(done),.busy(busy));




wire [7:0] rx_data;
wire rx_done;
wire rx_busy;
wire rx_err;



wire fifo_full;
wire fifo_empty;



wire tx_start;


wire tx_done;
wire tx_busy;


assign rx_data_stp=rx_data;



endmodule
module BDCDrv(clk,rxd,led1,led2,txd,txclkx4,rxclkx4,fifo_full);




input clk;
input rxd;

output led1;
output led2;
output txd;
output txclkx4;
output rxclkx4;
output fifo_full;


wire reset;
power_on_reset u1 (.clk(clk),.reset(reset));




wire [7:0] data_out;
led_drive u2 (.clk(clk),.reset(reset),.led1(led1),.led2(led2),.data_out(data_out));






wire txclk;
wire rxclk;
baudrate_generate u4(.clk(clk),.reset(reset),.txclk(txclk),.rxclk(rxclk),.txclkx4(txclkx4),.rxclkx4(rxclkx4));











wire tx_pulse;
wire [7:0] up_bytes;
upload_data upload_data_u1(.clk(txclk),.reset(reset),.tx_pulse(tx_pulse),.up_bytes(up_bytes));
wire done;
wire busy;
uart_tx u6(.clk(txclk),.reset(reset),.start(tx_pulse),.data_in(up_bytes),.txd(txd),.done(done),.busy(busy));




wire [7:0] rx_data;
wire rx_done;
wire rx_busy;
wire rx_err;



wire fifo_full;
wire fifo_empty;



wire tx_start;


wire tx_done;
wire tx_busy;


assign rx_data_stp=rx_data;



endmodule