data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/hist_test.v
1: b'%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/hist_test.v:353: Cannot find file containing module: \'histogram_ram\'\nhistogram_ram inst_bram_histo (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN,data/full_repos/permissive/514467334/histogram_ram\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN,data/full_repos/permissive/514467334/histogram_ram.v\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN,data/full_repos/permissive/514467334/histogram_ram.sv\n             histogram_ram\n             histogram_ram.v\n             histogram_ram.sv\n             obj_dir/histogram_ram\n             obj_dir/histogram_ram.v\n             obj_dir/histogram_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/hist_test.v:366: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt_clear\' generates 9 bits.\n                                                                                                            : ... In instance calculate_histogram\n        wr_ram_addr = cnt_clear;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/hist_test.v:388: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt_get\' generates 9 bits.\n                                                                                                            : ... In instance calculate_histogram\n        rd_ram_addr = cnt_get;\n                    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module calculate_histogram(
           input wire clk,
           input wire rst,
           input wire pi_hsync,
           input wire pi_vsync,
           input wire pi_data_vld,
           input wire [7: 0] pi_data ,

           output wire po_histo_vld,
           output wire [31: 0] po_histo_data
       );

parameter IMG_WIDTH = 256 ;
parameter IMG_HEIGHT = 256 ;
parameter GRAY_LEVEL	= 256	;

parameter IDLE = 4'b0001;
parameter CLEAR	= 4'b0010;
parameter CALCULATE = 4'b0100;
parameter GET_HISTO = 4'b1000;





reg [3: 0]	state ;
reg [1: 0]	vsync_dd	;




reg [8: 0]	cnt_clear ;
wire	add_cnt_clear;
wire end_cnt_clear;
reg clear_flag	;




reg [12: 0]	cnt_row ;
wire add_cnt_row ;
wire end_cnt_row	;

reg data_vld_dd0;
reg data_vld_dd1;
reg [7: 0]	pi_data_dd0	;
reg [7: 0]	pi_data_dd1	;
reg [31: 0]	cal_pixle	;
reg [31: 0]	cal_value ;
reg cal_value_vld;
reg cal_one_row_done	;
wire [7: 0]	cal_wr_ram_addr;
wire [7: 0]	cal_rd_ram_addr;




reg get_data_flag ;
reg [8: 0]	cnt_get ;
wire add_cnt_get ;
wire end_cnt_get ;
reg histo_data_vld ;
wire [31: 0]	histo_data ;




reg wr_ram_en ;
reg [7: 0]	wr_ram_addr	;
reg [31: 0]	wr_ram_data ;
reg [7: 0]	rd_ram_addr ;
wire	[31: 0]	rd_ram_data	;


assign po_histo_data = (histo_data_vld) ? histo_data : 32'd0;
assign po_histo_vld = histo_data_vld;



always @(posedge clk) begin
    if (rst == 1'b1) begin
        state <= IDLE ;
    end
    else begin
        case (state)
            IDLE : begin

                if (vsync_dd[0] == 1'b1 && vsync_dd[1] == 1'b0) begin
                    state <= CLEAR;
                end
                else begin
                    state <= IDLE;
                end
            end

            CLEAR : begin

                if (end_cnt_clear == 1'b1) begin
                    state <= CALCULATE;
                end
                else begin
                    state <= CLEAR;
                end
            end

            CALCULATE : begin

                if (end_cnt_row == 1'b1) begin
                    state <= GET_HISTO;
                end
                else begin
                    state <= CALCULATE;
                end
            end

            GET_HISTO : begin

                if (end_cnt_get == 1'b1) begin
                    state <= IDLE;
                end
                else begin
                    state <= GET_HISTO;
                end

            end

            default : begin
                state <= IDLE;
            end

        endcase
    end
end



always @(posedge clk) begin
    if (rst == 1'b1) begin
        vsync_dd <= 'd0;
    end
    else begin
        vsync_dd <= {vsync_dd[0], pi_vsync};
    end
end






always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_clear <= 'd0;
    end
    else if (add_cnt_clear) begin
        if (end_cnt_clear)
            cnt_clear <= 'd0;
        else
            cnt_clear <= cnt_clear + 1'b1;
    end
    else begin
        cnt_clear <= 'd0;
    end
end

assign add_cnt_clear = state == CLEAR && wr_ram_en == 1'b1;
assign end_cnt_clear = add_cnt_clear && cnt_clear == GRAY_LEVEL - 1;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        clear_flag <= 1'b0;
    end
    else if (state == CLEAR ) begin
        if (end_cnt_clear == 1'b1) begin
            clear_flag <= 1'b0;
        end
        else begin
            clear_flag <= 1'b1;
        end
    end
    else begin
        clear_flag <= 1'b0;
    end
end







always @(posedge clk) begin
    if (rst == 1'b1) begin
        data_vld_dd0 <= 'd0;
        data_vld_dd1 <= 'd0;
        pi_data_dd0	<= 'd0;
        pi_data_dd1	<= 'd0;
    end
    else begin
        data_vld_dd0 <= pi_data_vld;
        data_vld_dd1 <= data_vld_dd0;
        pi_data_dd0	<= pi_data;
        pi_data_dd1	<= pi_data_dd0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_pixle <= 'd1;
    end
    else if (state == CALCULATE && data_vld_dd0 == 1'b1 ) begin

        if (pi_data != pi_data_dd0 ) begin
            cal_pixle <= 'd1;
        end

        else if (pi_data_vld == 1'b0 ) begin
            cal_pixle <= 'd1;
        end

        else if (pi_data == pi_data_dd0) begin
            cal_pixle <= cal_pixle + 1'b1;
        end
    end
    else begin
        cal_pixle <= 'd1;
    end
end



always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_value <= 'd0;
        cal_value_vld <= 1'b0;
    end
    else if (state == CALCULATE ) begin

        if (pi_data != pi_data_dd0 && data_vld_dd0 == 1'b1) begin

            cal_value <= rd_ram_data + cal_pixle;
            cal_value_vld <= 1'b1;
        end

        else if (pi_data_vld == 1'b0 && data_vld_dd0 == 1'b1) begin
            cal_value <= rd_ram_data + cal_pixle;
            cal_value_vld <= 1'b1;
        end
        else begin
            cal_value <= 'd0;
            cal_value_vld <= 1'b0;
        end
    end
    else begin
        cal_value <= 'd0;
        cal_value_vld <= 1'b0;
    end
end

assign cal_wr_ram_addr = pi_data_dd1;
assign cal_rd_ram_addr = pi_data;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_one_row_done <= 1'b0;
    end

    else if (state == CALCULATE && pi_data_vld == 1'b0 && data_vld_dd0 == 1'b1) begin
        cal_one_row_done <= 1'b1;
    end
    else begin
        cal_one_row_done <= 1'b0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_row <= 'd0;
    end
    else if (add_cnt_row) begin
        if (end_cnt_row)
            cnt_row <= 'd0;
        else
            cnt_row <= cnt_row + 1'b1;
    end
end

assign add_cnt_row = cal_one_row_done == 1'b1;
assign end_cnt_row = add_cnt_row && cnt_row == IMG_HEIGHT - 1;






always @(posedge clk) begin
    if (rst == 1'b1) begin
        get_data_flag <= 1'b0;
    end
    else if (state == GET_HISTO) begin
        if (end_cnt_get == 1'b1) begin
            get_data_flag <= 1'b0;
        end
        else begin
            get_data_flag <= 1'b1;
        end
    end
    else begin
        get_data_flag <= 1'b0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_get <= 'd0;
    end
    else if (add_cnt_get) begin
        if (end_cnt_get)
            cnt_get <= 'd0;
        else
            cnt_get <= cnt_get + 1'b1;
    end
    else begin
        cnt_get <= 'd0;
    end
end

assign add_cnt_get = get_data_flag == 1'b1;
assign end_cnt_get = add_cnt_get && cnt_get == GRAY_LEVEL - 1;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        histo_data_vld <= 1'b0;
    end
    else begin
        histo_data_vld <= get_data_flag;
    end
end

assign histo_data = (histo_data_vld) ? rd_ram_data : 'd0 ;




histogram_ram inst_bram_histo (
                  .clka(clk),
                  .wea(wr_ram_en),
                  .addra(wr_ram_addr),
                  .dina(wr_ram_data),
                  .clkb(clk),
                  .addrb(rd_ram_addr),
                  .doutb(rd_ram_data)
              );


always @( * ) begin
    if (state == CLEAR) begin
        wr_ram_addr = cnt_clear;
        wr_ram_en = clear_flag;
        wr_ram_data = 'd0;
    end
    else if (state == CALCULATE) begin
        wr_ram_addr = cal_wr_ram_addr;
        wr_ram_en = cal_value_vld;
        wr_ram_data = cal_value;
    end
    else begin
        wr_ram_addr = 'd0;
        wr_ram_en = 1'b0;
        wr_ram_data = 'd0;
    end
end


always @( * ) begin
    if (state == CALCULATE) begin
        rd_ram_addr = cal_rd_ram_addr;
    end
    else if (state == GET_HISTO) begin
        rd_ram_addr = cnt_get;
    end
    else begin
        rd_ram_addr = 'd0;
    end
end

endmodule
module calculate_histogram(
           input wire clk,
           input wire rst,
           input wire pi_hsync,
           input wire pi_vsync,
           input wire pi_data_vld,
           input wire [7: 0] pi_data ,

           output wire po_histo_vld,
           output wire [31: 0] po_histo_data
       );


parameter IMG_WIDTH = 256 ;
parameter IMG_HEIGHT = 256 ;
parameter GRAY_LEVEL	= 256	;

parameter IDLE = 4'b0001;
parameter CLEAR	= 4'b0010;
parameter CALCULATE = 4'b0100;
parameter GET_HISTO = 4'b1000;





reg [3: 0]	state ;
reg [1: 0]	vsync_dd	;




reg [8: 0]	cnt_clear ;
wire	add_cnt_clear;
wire end_cnt_clear;
reg clear_flag	;




reg [12: 0]	cnt_row ;
wire add_cnt_row ;
wire end_cnt_row	;

reg data_vld_dd0;
reg data_vld_dd1;
reg [7: 0]	pi_data_dd0	;
reg [7: 0]	pi_data_dd1	;
reg [31: 0]	cal_pixle	;
reg [31: 0]	cal_value ;
reg cal_value_vld;
reg cal_one_row_done	;
wire [7: 0]	cal_wr_ram_addr;
wire [7: 0]	cal_rd_ram_addr;




reg get_data_flag ;
reg [8: 0]	cnt_get ;
wire add_cnt_get ;
wire end_cnt_get ;
reg histo_data_vld ;
wire [31: 0]	histo_data ;




reg wr_ram_en ;
reg [7: 0]	wr_ram_addr	;
reg [31: 0]	wr_ram_data ;
reg [7: 0]	rd_ram_addr ;
wire	[31: 0]	rd_ram_data	;


assign po_histo_data = (histo_data_vld) ? histo_data : 32'd0;
assign po_histo_vld = histo_data_vld;



always @(posedge clk) begin
    if (rst == 1'b1) begin
        state <= IDLE ;
    end
    else begin
        case (state)
            IDLE : begin

                if (vsync_dd[0] == 1'b1 && vsync_dd[1] == 1'b0) begin
                    state <= CLEAR;
                end
                else begin
                    state <= IDLE;
                end
            end

            CLEAR : begin

                if (end_cnt_clear == 1'b1) begin
                    state <= CALCULATE;
                end
                else begin
                    state <= CLEAR;
                end
            end

            CALCULATE : begin

                if (end_cnt_row == 1'b1) begin
                    state <= GET_HISTO;
                end
                else begin
                    state <= CALCULATE;
                end
            end

            GET_HISTO : begin

                if (end_cnt_get == 1'b1) begin
                    state <= IDLE;
                end
                else begin
                    state <= GET_HISTO;
                end

            end

            default : begin
                state <= IDLE;
            end

        endcase
    end
end



always @(posedge clk) begin
    if (rst == 1'b1) begin
        vsync_dd <= 'd0;
    end
    else begin
        vsync_dd <= {vsync_dd[0], pi_vsync};
    end
end






always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_clear <= 'd0;
    end
    else if (add_cnt_clear) begin
        if (end_cnt_clear)
            cnt_clear <= 'd0;
        else
            cnt_clear <= cnt_clear + 1'b1;
    end
    else begin
        cnt_clear <= 'd0;
    end
end

assign add_cnt_clear = state == CLEAR && wr_ram_en == 1'b1;
assign end_cnt_clear = add_cnt_clear && cnt_clear == GRAY_LEVEL - 1;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        clear_flag <= 1'b0;
    end
    else if (state == CLEAR ) begin
        if (end_cnt_clear == 1'b1) begin
            clear_flag <= 1'b0;
        end
        else begin
            clear_flag <= 1'b1;
        end
    end
    else begin
        clear_flag <= 1'b0;
    end
end







always @(posedge clk) begin
    if (rst == 1'b1) begin
        data_vld_dd0 <= 'd0;
        data_vld_dd1 <= 'd0;
        pi_data_dd0	<= 'd0;
        pi_data_dd1	<= 'd0;
    end
    else begin
        data_vld_dd0 <= pi_data_vld;
        data_vld_dd1 <= data_vld_dd0;
        pi_data_dd0	<= pi_data;
        pi_data_dd1	<= pi_data_dd0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_pixle <= 'd1;
    end
    else if (state == CALCULATE && data_vld_dd0 == 1'b1 ) begin

        if (pi_data != pi_data_dd0 ) begin
            cal_pixle <= 'd1;
        end

        else if (pi_data_vld == 1'b0 ) begin
            cal_pixle <= 'd1;
        end

        else if (pi_data == pi_data_dd0) begin
            cal_pixle <= cal_pixle + 1'b1;
        end
    end
    else begin
        cal_pixle <= 'd1;
    end
end



always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_value <= 'd0;
        cal_value_vld <= 1'b0;
    end
    else if (state == CALCULATE ) begin

        if (pi_data != pi_data_dd0 && data_vld_dd0 == 1'b1) begin

            cal_value <= rd_ram_data + cal_pixle;
            cal_value_vld <= 1'b1;
        end

        else if (pi_data_vld == 1'b0 && data_vld_dd0 == 1'b1) begin
            cal_value <= rd_ram_data + cal_pixle;
            cal_value_vld <= 1'b1;
        end
        else begin
            cal_value <= 'd0;
            cal_value_vld <= 1'b0;
        end
    end
    else begin
        cal_value <= 'd0;
        cal_value_vld <= 1'b0;
    end
end

assign cal_wr_ram_addr = pi_data_dd1;
assign cal_rd_ram_addr = pi_data;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cal_one_row_done <= 1'b0;
    end

    else if (state == CALCULATE && pi_data_vld == 1'b0 && data_vld_dd0 == 1'b1) begin
        cal_one_row_done <= 1'b1;
    end
    else begin
        cal_one_row_done <= 1'b0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_row <= 'd0;
    end
    else if (add_cnt_row) begin
        if (end_cnt_row)
            cnt_row <= 'd0;
        else
            cnt_row <= cnt_row + 1'b1;
    end
end

assign add_cnt_row = cal_one_row_done == 1'b1;
assign end_cnt_row = add_cnt_row && cnt_row == IMG_HEIGHT - 1;






always @(posedge clk) begin
    if (rst == 1'b1) begin
        get_data_flag <= 1'b0;
    end
    else if (state == GET_HISTO) begin
        if (end_cnt_get == 1'b1) begin
            get_data_flag <= 1'b0;
        end
        else begin
            get_data_flag <= 1'b1;
        end
    end
    else begin
        get_data_flag <= 1'b0;
    end
end


always @(posedge clk) begin
    if (rst == 1'b1) begin
        cnt_get <= 'd0;
    end
    else if (add_cnt_get) begin
        if (end_cnt_get)
            cnt_get <= 'd0;
        else
            cnt_get <= cnt_get + 1'b1;
    end
    else begin
        cnt_get <= 'd0;
    end
end

assign add_cnt_get = get_data_flag == 1'b1;
assign end_cnt_get = add_cnt_get && cnt_get == GRAY_LEVEL - 1;


always @(posedge clk) begin
    if (rst == 1'b1) begin
        histo_data_vld <= 1'b0;
    end
    else begin
        histo_data_vld <= get_data_flag;
    end
end

assign histo_data = (histo_data_vld) ? rd_ram_data : 'd0 ;




histogram_ram inst_bram_histo (
                  .clka(clk),
                  .wea(wr_ram_en),
                  .addra(wr_ram_addr),
                  .dina(wr_ram_data),
                  .clkb(clk),
                  .addrb(rd_ram_addr),
                  .doutb(rd_ram_data)
              );


always @( * ) begin
    if (state == CLEAR) begin
        wr_ram_addr = cnt_clear;
        wr_ram_en = clear_flag;
        wr_ram_data = 'd0;
    end
    else if (state == CALCULATE) begin
        wr_ram_addr = cal_wr_ram_addr;
        wr_ram_en = cal_value_vld;
        wr_ram_data = cal_value;
    end
    else begin
        wr_ram_addr = 'd0;
        wr_ram_en = 1'b0;
        wr_ram_data = 'd0;
    end
end


always @( * ) begin
    if (state == CALCULATE) begin
        rd_ram_addr = cal_rd_ram_addr;
    end
    else if (state == GET_HISTO) begin
        rd_ram_addr = cnt_get;
    end
    else begin
        rd_ram_addr = 'd0;
    end
end

endmodule