data/full_repos/permissive/492462267/hilo_reg.v
1: b'%Error: data/full_repos/permissive/492462267/hilo_reg.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:9: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   hi_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegDataBus]   hi_i,\n                            ^\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:10: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   lo_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:13: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    hi_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:14: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    lo_o\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:19: Define or directive not defined: \'`ZeroWord\'\n        hi_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/hilo_reg.v:20: Define or directive not defined: \'`ZeroWord\'\n        lo_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module hilo_reg (
    input   wire                clk,
    input   wire                rst,


    input   wire                we,
    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,


    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o
);

always @(posedge clk ) begin
    if(rst) begin
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
    end else if(we) begin
        hi_o <= hi_i;
        lo_o <= lo_i;
    end else begin
        hi_o <= hi_o;
        lo_o <= lo_o;
    end
end

endmodule
module hilo_reg (
    input   wire                clk,
    input   wire                rst,


    input   wire                we,
    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,


    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o
);


always @(posedge clk ) begin
    if(rst) begin
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
    end else if(we) begin
        hi_o <= hi_i;
        lo_o <= lo_i;
    end else begin
        hi_o <= hi_o;
        lo_o <= lo_o;
    end
end

endmodule