data/full_repos/permissive/469195529/sources/hdl/CountTimeMain.v
1: b"%Error: data/full_repos/permissive/469195529/sources/hdl/CountTimeMain.v:33: Cannot find file containing module: 'gateMain_0'\n    gateMain_0 enGate(.clk(clk_1Hz), .enable(enable & ~done), .g_clk(gclk_1Hz));\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469195529/sources/hdl,data/full_repos/permissive/469195529/gateMain_0\n             data/full_repos/permissive/469195529/sources/hdl,data/full_repos/permissive/469195529/gateMain_0.v\n             data/full_repos/permissive/469195529/sources/hdl,data/full_repos/permissive/469195529/gateMain_0.sv\n             gateMain_0\n             gateMain_0.v\n             gateMain_0.sv\n             obj_dir/gateMain_0\n             obj_dir/gateMain_0.v\n             obj_dir/gateMain_0.sv\n%Error: data/full_repos/permissive/469195529/sources/hdl/CountTimeMain.v:34: Cannot find file containing module: 'CounterV2_0'\n    CounterV2_0 secCount(.clk(gclk_1Hz), .reset(reset), .load(loadSec), .loadVal(valSec), .OVF(secOvf), .Q(sec));\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469195529/sources/hdl/CountTimeMain.v:35: Cannot find file containing module: 'CounterV2_0'\n    CounterV2_0 minCount(.clk(secOvf), .reset(reset), .load(loadMin), .loadVal(valMin), .OVF(), .Q(min));\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module CountTimeMain(
    input loadMin, loadSec, clk_1Hz, enable, reset,
    input [5:0] valMin, valSec,
    output [5:0] min, sec
    );
    
    wire secDone, minDone, gclk_1Hz, done, secOvf;
    assign secDone = ~|sec;
    assign minDone = ~|min;
    assign done = secDone & minDone;
    gateMain_0 enGate(.clk(clk_1Hz), .enable(enable & ~done), .g_clk(gclk_1Hz));
    CounterV2_0 secCount(.clk(gclk_1Hz), .reset(reset), .load(loadSec), .loadVal(valSec), .OVF(secOvf), .Q(sec));
    CounterV2_0 minCount(.clk(secOvf), .reset(reset), .load(loadMin), .loadVal(valMin), .OVF(), .Q(min));
    
endmodule
module CountTimeMain(
    input loadMin, loadSec, clk_1Hz, enable, reset,
    input [5:0] valMin, valSec,
    output [5:0] min, sec
    );

    
    wire secDone, minDone, gclk_1Hz, done, secOvf;
    assign secDone = ~|sec;
    assign minDone = ~|min;
    assign done = secDone & minDone;
    gateMain_0 enGate(.clk(clk_1Hz), .enable(enable & ~done), .g_clk(gclk_1Hz));
    CounterV2_0 secCount(.clk(gclk_1Hz), .reset(reset), .load(loadSec), .loadVal(valSec), .OVF(secOvf), .Q(sec));
    CounterV2_0 minCount(.clk(secOvf), .reset(reset), .load(loadMin), .loadVal(valMin), .OVF(), .Q(min));
    
endmodule