data/full_repos/permissive/447223480/02_alu/cpu.v
data/verilator_xmls/7a4fc256-10e2-47ef-8a2b-3d13412b55fb.xml
module cpu(clock, reset);
	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

	wire [15:0] inst;
	pmem pmem(.addr(pc), .data(inst));

	wire [4:0] Rm, Rs, Rd;
	wire [31:0] Rm_data, Rs_data, immediate;
	wire [31:0] new_value;
	wire is_immediate;
	wire [9:0] alu_op;

	decoder decoder(
		.inst(inst), .Rm(Rm), .Rs(Rs), .Rd(Rd),
		.immediate(immediate), .is_immediate(is_immediate),
		.alu_op(alu_op)
	);

	regs regs(
		.clock(clock), .reset(reset),
		.Rm(Rm), .Rs(Rs), .Rd(Rd),
		.Rm_data(Rm_data), .Rs_data(Rs_data), .Rd_data(new_value)
	);

	wire [31:0] alu_in2 = is_immediate ? immediate : Rs_data;

	alu alu(
		.in1(Rm_data), .in2(alu_in2), .op(alu_op), .out(new_value)
	);

endmodule
module cpu(clock, reset);

	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

	wire [15:0] inst;
	pmem pmem(.addr(pc), .data(inst));

	wire [4:0] Rm, Rs, Rd;
	wire [31:0] Rm_data, Rs_data, immediate;
	wire [31:0] new_value;
	wire is_immediate;
	wire [9:0] alu_op;

	decoder decoder(
		.inst(inst), .Rm(Rm), .Rs(Rs), .Rd(Rd),
		.immediate(immediate), .is_immediate(is_immediate),
		.alu_op(alu_op)
	);

	regs regs(
		.clock(clock), .reset(reset),
		.Rm(Rm), .Rs(Rs), .Rd(Rd),
		.Rm_data(Rm_data), .Rs_data(Rs_data), .Rd_data(new_value)
	);

	wire [31:0] alu_in2 = is_immediate ? immediate : Rs_data;

	alu alu(
		.in1(Rm_data), .in2(alu_in2), .op(alu_op), .out(new_value)
	);

endmodule