data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/03_Shift_Registers/08_Shift_register.v
data/verilator_xmls/c34f5633-790e-488c-8d85-abb51028cb61.xml
module MUXDFF (
    input clk,
    input w, R, E, L,
    output reg Q
);
    
    always @(posedge clk) begin
        Q <= L ? R : (E ? w : Q);
    end

endmodule
module MUXDFF (
    input clk,
    input w, R, E, L,
    output reg Q
);

    
    always @(posedge clk) begin
        Q <= L ? R : (E ? w : Q);
    end

endmodule