data/full_repos/permissive/497819211/04/CPU.v
1: b"%Error: data/full_repos/permissive/497819211/04/CPU.v:78: Cannot find file containing module: 'And'\n    And AND1(.a(instruction[15]),.b(instruction[5]),.out(d1));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/And\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/And.v\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/And.sv\n             And\n             And.v\n             And.sv\n             obj_dir/And\n             obj_dir/And.v\n             obj_dir/And.sv\n%Error: data/full_repos/permissive/497819211/04/CPU.v:79: Cannot find file containing module: 'And'\n    And AND2(.a(instruction[15]),.b(instruction[4]),.out(d2));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:80: Cannot find file containing module: 'And'\n    And AND3(.a(instruction[15]),.b(instruction[3]),.out(d3));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:82: Cannot find file containing module: 'And'\n    And AND4(.a(instruction[15]),.b(instruction[2]),.out(j1));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:83: Cannot find file containing module: 'And'\n    And AND5(.a(instruction[15]),.b(instruction[1]),.out(j2));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:84: Cannot find file containing module: 'And'\n    And AND6(.a(instruction[15]),.b(instruction[0]),.out(j3));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:92: Cannot find file containing module: 'Mux16'\n    Mux16 MUX16a(.a(instruction),.b(outputM),.sel(instruction[15]),.out(Ainput));\n    ^~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:93: Cannot find file containing module: 'Not'\n    Not NOT1(.in(instruction[15]), .out(Aload1));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:94: Cannot find file containing module: 'Or'\n    Or OR1(.a(Aload1),.b(d1),.out(Aload));\n    ^~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:95: Cannot find file containing module: 'Register'\n    Register REGISTERa(.in(Ainput),.load(Aload),.out(Areg), .clk(clk));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:100: Cannot find file containing module: 'Register'\n    Register REGISTER1d(.in(outputM),.load(d2),.out(Dreg), .clk(clk));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:106: Cannot find file containing module: 'Mux16'\n    Mux16 MUX16alu(.a(Areg),.b(inM),.sel(instruction[12]),.out(y));\n    ^~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:108: Cannot find file containing module: 'ALUusr'\n    ALUusr ALU(\n    ^~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:133: Cannot find file containing module: 'And'\n    And ANDpc1(.a(ng),.b(j1),.out(tmp1));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:134: Cannot find file containing module: 'And'\n    And ANDpc2(.a(zr),.b(j2),.out(tmp2));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:135: Cannot find file containing module: 'Not'\n    Not NOTpc1(.in(zr), .out(notzr));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:136: Cannot find file containing module: 'Not'\n    Not NOTpc2(.in(ng), .out(notng));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:137: Cannot find file containing module: 'And'\n    And ANDpc3(.a(notzr),.b(notng),.out(ps));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:138: Cannot find file containing module: 'And'\n    And ANDpc4(.a(ps),.b(j3),.out(tmp3));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:139: Cannot find file containing module: 'Or'\n    Or ORpc1(.a(tmp1),.b(tmp2),.out(tmp));\n    ^~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:140: Cannot find file containing module: 'Or'\n    Or ORpc2(.a(tmp),.b(tmp3),.out(jump));\n    ^~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:141: Cannot find file containing module: 'Not'\n    Not NOTpc3(.in(jump), .out(inc));\n    ^~~\n%Error: data/full_repos/permissive/497819211/04/CPU.v:142: Cannot find file containing module: 'PC'\n     PC PC1(\n     ^~\n%Error: Exiting due to 23 error(s)\n"
module CPU(
		input clk,
    	input [15:0] inM,
    	input [15:0] instruction,
		input reset,



    	output [15:0] outM,
    	output writeM,
    	output [15:0] addressM,
    	output [15:0] pc
);



































    wire d1;
    wire d2;
    wire d3;
    wire j1;
    wire j2;
    wire j3;
    And AND1(.a(instruction[15]),.b(instruction[5]),.out(d1));
    And AND2(.a(instruction[15]),.b(instruction[4]),.out(d2));
    And AND3(.a(instruction[15]),.b(instruction[3]),.out(d3));
    assign writeM = d3;
    And AND4(.a(instruction[15]),.b(instruction[2]),.out(j1));
    And AND5(.a(instruction[15]),.b(instruction[1]),.out(j2));
    And AND6(.a(instruction[15]),.b(instruction[0]),.out(j3));


    wire[15:0] outputM;
    wire[15:0] Ainput;
    wire Aload1;
    wire Aload;
    wire[15:0] Areg;
    Mux16 MUX16a(.a(instruction),.b(outputM),.sel(instruction[15]),.out(Ainput));
    Not NOT1(.in(instruction[15]), .out(Aload1));
    Or OR1(.a(Aload1),.b(d1),.out(Aload));
    Register REGISTERa(.in(Ainput),.load(Aload),.out(Areg), .clk(clk));
    assign addressM = Areg;


    wire[15:0] Dreg;
    Register REGISTER1d(.in(outputM),.load(d2),.out(Dreg), .clk(clk));


    wire[15:0] y;
    wire zr;
    wire ng;
    Mux16 MUX16alu(.a(Areg),.b(inM),.sel(instruction[12]),.out(y));
    
    ALUusr ALU(
	    .x(Dreg),
		.y(y),
        .zx(instruction[11]),
        .nx(instruction[10]),
        .zy(instruction[9]),
        .ny(instruction[8]),
        .f(instruction[7]),
        .no(instruction[6]),
	    .out(outputM),
	    .zr(zr),
	    .ng(ng)
	  );
      assign outM = outputM; 


    wire tmp1;
    wire tmp2;
    wire tmp3;
    wire notzr;
    wire notng;
    wire ps;
    wire tmp;
    wire jump;
    wire inc;
    And ANDpc1(.a(ng),.b(j1),.out(tmp1));
    And ANDpc2(.a(zr),.b(j2),.out(tmp2));
    Not NOTpc1(.in(zr), .out(notzr));
    Not NOTpc2(.in(ng), .out(notng));
    And ANDpc3(.a(notzr),.b(notng),.out(ps));
    And ANDpc4(.a(ps),.b(j3),.out(tmp3));
    Or ORpc1(.a(tmp1),.b(tmp2),.out(tmp));
    Or ORpc2(.a(tmp),.b(tmp3),.out(jump));
    Not NOTpc3(.in(jump), .out(inc));
    	PC PC1(
    	.clk(clk),
		.reset(reset),
		.load(jump),
		.inc(inc),
		.in(Areg),
		.out(pc)
  	);

endmodule
module CPU(
		input clk,
    	input [15:0] inM,
    	input [15:0] instruction,
		input reset,



    	output [15:0] outM,
    	output writeM,
    	output [15:0] addressM,
    	output [15:0] pc
);




































    wire d1;
    wire d2;
    wire d3;
    wire j1;
    wire j2;
    wire j3;
    And AND1(.a(instruction[15]),.b(instruction[5]),.out(d1));
    And AND2(.a(instruction[15]),.b(instruction[4]),.out(d2));
    And AND3(.a(instruction[15]),.b(instruction[3]),.out(d3));
    assign writeM = d3;
    And AND4(.a(instruction[15]),.b(instruction[2]),.out(j1));
    And AND5(.a(instruction[15]),.b(instruction[1]),.out(j2));
    And AND6(.a(instruction[15]),.b(instruction[0]),.out(j3));


    wire[15:0] outputM;
    wire[15:0] Ainput;
    wire Aload1;
    wire Aload;
    wire[15:0] Areg;
    Mux16 MUX16a(.a(instruction),.b(outputM),.sel(instruction[15]),.out(Ainput));
    Not NOT1(.in(instruction[15]), .out(Aload1));
    Or OR1(.a(Aload1),.b(d1),.out(Aload));
    Register REGISTERa(.in(Ainput),.load(Aload),.out(Areg), .clk(clk));
    assign addressM = Areg;


    wire[15:0] Dreg;
    Register REGISTER1d(.in(outputM),.load(d2),.out(Dreg), .clk(clk));


    wire[15:0] y;
    wire zr;
    wire ng;
    Mux16 MUX16alu(.a(Areg),.b(inM),.sel(instruction[12]),.out(y));
    
    ALUusr ALU(
	    .x(Dreg),
		.y(y),
        .zx(instruction[11]),
        .nx(instruction[10]),
        .zy(instruction[9]),
        .ny(instruction[8]),
        .f(instruction[7]),
        .no(instruction[6]),
	    .out(outputM),
	    .zr(zr),
	    .ng(ng)
	  );
      assign outM = outputM; 


    wire tmp1;
    wire tmp2;
    wire tmp3;
    wire notzr;
    wire notng;
    wire ps;
    wire tmp;
    wire jump;
    wire inc;
    And ANDpc1(.a(ng),.b(j1),.out(tmp1));
    And ANDpc2(.a(zr),.b(j2),.out(tmp2));
    Not NOTpc1(.in(zr), .out(notzr));
    Not NOTpc2(.in(ng), .out(notng));
    And ANDpc3(.a(notzr),.b(notng),.out(ps));
    And ANDpc4(.a(ps),.b(j3),.out(tmp3));
    Or ORpc1(.a(tmp1),.b(tmp2),.out(tmp));
    Or ORpc2(.a(tmp),.b(tmp3),.out(jump));
    Not NOTpc3(.in(jump), .out(inc));
    	PC PC1(
    	.clk(clk),
		.reset(reset),
		.load(jump),
		.inc(inc),
		.in(Areg),
		.out(pc)
  	);

endmodule