data/full_repos/permissive/461569093/Mini ALU/bit6_addsub.v
1: b'%Error: Cannot find file containing module: ALU,data/full_repos/permissive/461569093\n        ... Looked in:\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.v\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.sv\n             ALU,data/full_repos/permissive/461569093\n             ALU,data/full_repos/permissive/461569093.v\n             ALU,data/full_repos/permissive/461569093.sv\n             obj_dir/ALU,data/full_repos/permissive/461569093\n             obj_dir/ALU,data/full_repos/permissive/461569093.v\n             obj_dir/ALU,data/full_repos/permissive/461569093.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461569093/Mini\n%Error: Cannot find file containing module: ALU/bit6_addsub.v\n%Error: Exiting due to 3 error(s)\n'
module bit6_addsub(
    input [5:0] x,
    input [5:0] y,
    input sel,
    output overflow,
    output c_out,
    output [5:0] sum
    );
    wire [5:0] sel_y;
    wire [5:0] c_outs;
    
    assign sel_y = (sel)? !y : y;
    
    FullAdder b0 (x[0], sel_y[0], sel, sum[0], c_outs[0]);
    FullAdder b1 (x[1], sel_y[1], c_outs[0], sum[1], c_outs[1]);
    FullAdder b2 (x[2], sel_y[2], c_outs[1], sum[2], c_outs[2]);
    FullAdder b3 (x[3], sel_y[3], c_outs[2], sum[3], c_outs[3]);
    FullAdder b4 (x[4], sel_y[4], c_outs[3], sum[4], c_outs[4]);
    FullAdder b5 (x[5], sel_y[5], c_outs[4], sum[5], c_outs[5]);
    xor validgen (overflow, c_outs[4], c_outs[5]);
    assign c_out = c_outs[5];
          
endmodule
module bit6_addsub(
    input [5:0] x,
    input [5:0] y,
    input sel,
    output overflow,
    output c_out,
    output [5:0] sum
    );

    wire [5:0] sel_y;
    wire [5:0] c_outs;
    
    assign sel_y = (sel)? !y : y;
    
    FullAdder b0 (x[0], sel_y[0], sel, sum[0], c_outs[0]);
    FullAdder b1 (x[1], sel_y[1], c_outs[0], sum[1], c_outs[1]);
    FullAdder b2 (x[2], sel_y[2], c_outs[1], sum[2], c_outs[2]);
    FullAdder b3 (x[3], sel_y[3], c_outs[2], sum[3], c_outs[3]);
    FullAdder b4 (x[4], sel_y[4], c_outs[3], sum[4], c_outs[4]);
    FullAdder b5 (x[5], sel_y[5], c_outs[4], sum[5], c_outs[5]);
    xor validgen (overflow, c_outs[4], c_outs[5]);
    assign c_out = c_outs[5];
          
endmodule