data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/reset_generator.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/reset_generator.v:38: Cannot find file containing module: 'synchronizer'\n  synchronizer #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/reset_generator.v:50: Cannot find file containing module: 'synchronizer'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module reset_generator (
  input  wire clk,
  output reg  power_on_reset = 1'b1
);
  
  wire [0:0] counter_enable;
  wire [0:0] initialize;

  synchronizer #(
    .WIDTH            (1),
    .STAGES           (3),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (0)
  ) init_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (1'b1),
    .out (initialize)
  );

  synchronizer #(
    .WIDTH            (1),
    .STAGES           (3),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (0)
  ) counter_en_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (initialize),
    .out (counter_enable)
  );


  localparam CYCLES_IN_RESET = 20;
  reg [7:0] power_on_reset_counter = 8'b0;










  always @(posedge clk) begin : power_on_reset_gen
    if (counter_enable) begin
      if (power_on_reset_counter == CYCLES_IN_RESET-1) begin
        power_on_reset <= 1'b0;
      end else begin
        power_on_reset_counter <= power_on_reset_counter + 1'b1;
        power_on_reset <= 1'b1;
      end
    end
    else if (initialize) begin
      power_on_reset_counter <= 8'b0;
      power_on_reset <= 1'b1;
    end
  end

endmodule
module reset_generator (
  input  wire clk,
  output reg  power_on_reset = 1'b1
);

  
  wire [0:0] counter_enable;
  wire [0:0] initialize;

  synchronizer #(
    .WIDTH            (1),
    .STAGES           (3),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (0)
  ) init_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (1'b1),
    .out (initialize)
  );

  synchronizer #(
    .WIDTH            (1),
    .STAGES           (3),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (0)
  ) counter_en_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (initialize),
    .out (counter_enable)
  );


  localparam CYCLES_IN_RESET = 20;
  reg [7:0] power_on_reset_counter = 8'b0;










  always @(posedge clk) begin : power_on_reset_gen
    if (counter_enable) begin
      if (power_on_reset_counter == CYCLES_IN_RESET-1) begin
        power_on_reset <= 1'b0;
      end else begin
        power_on_reset_counter <= power_on_reset_counter + 1'b1;
        power_on_reset <= 1'b1;
      end
    end
    else if (initialize) begin
      power_on_reset_counter <= 8'b0;
      power_on_reset <= 1'b1;
    end
  end

endmodule