data/full_repos/permissive/494696040/ALU_control.v
data/verilator_xmls/8e38ecb3-70be-4b9c-a81e-e5044f298771.xml
module ALU_control(
    input wire [5:0] instruction,
    input wire [1:0] ALUOp,
    output reg [3:0] ALUoperation
    );
    

    always @(ALUOp or instruction)

    begin
        if (ALUOp == 2'b00) ALUoperation <= 4'b0010;
        else if ((ALUOp == 2'b01) || (ALUOp == 2'b11)) ALUoperation <= 4'b0110;
        else begin
            if (instruction[3:0] == 4'b0000) ALUoperation <= 4'b0010;
            if (instruction[3:0] == 4'b0010) ALUoperation <= 4'b0110;
            if (instruction[3:0] == 4'b0100) ALUoperation <= 4'b0000;
            if (instruction[3:0] == 4'b0101) ALUoperation <= 4'b0001;
            if (instruction[3:0] == 4'b1010) ALUoperation <= 4'b0111;
        end
    end
endmodule
module ALU_control(
    input wire [5:0] instruction,
    input wire [1:0] ALUOp,
    output reg [3:0] ALUoperation
    );

    

    always @(ALUOp or instruction)

    begin
        if (ALUOp == 2'b00) ALUoperation <= 4'b0010;
        else if ((ALUOp == 2'b01) || (ALUOp == 2'b11)) ALUoperation <= 4'b0110;
        else begin
            if (instruction[3:0] == 4'b0000) ALUoperation <= 4'b0010;
            if (instruction[3:0] == 4'b0010) ALUoperation <= 4'b0110;
            if (instruction[3:0] == 4'b0100) ALUoperation <= 4'b0000;
            if (instruction[3:0] == 4'b0101) ALUoperation <= 4'b0001;
            if (instruction[3:0] == 4'b1010) ALUoperation <= 4'b0111;
        end
    end
endmodule