data/full_repos/permissive/514354758/testbench/tb_image_read.v
1: b'%Error: data/full_repos/permissive/514354758/testbench/tb_image_read.v:2: Cannot find include file: image_read.v\n`include "image_read.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/image_read.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/image_read.v.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/image_read.v.sv\n             image_read.v\n             image_read.v.v\n             image_read.v.sv\n             obj_dir/image_read.v\n             obj_dir/image_read.v.v\n             obj_dir/image_read.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_image_read.v:14: Unsupported: Ignoring delay on this delayed statement.\n    always #10 HCLK = ~HCLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/514354758/testbench/tb_image_read.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_image_read.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/514354758/testbench/tb_image_read.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_image_read.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #25\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_image_read.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #1000\n        ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module tb_image_read;
    reg HCLK;
    reg HRESETn;
    wire VSYNC;
    wire HSYNC;
    wire [7:0] data;
    wire ctrl_done;

    image_read image_read_inst(HCLK,HRESETn,VSYNC,HSYNC,data,ctrl_done);

    always #10 HCLK = ~HCLK;

    initial begin
        $dumpfile("tb_image_read.vcd");
        $dumpvars(0);
        HCLK = 0;
        HRESETn = 0;
        #25
        HRESETn = 1;
        #1000
        $finish;
    end

endmodule
module tb_image_read;

    reg HCLK;
    reg HRESETn;
    wire VSYNC;
    wire HSYNC;
    wire [7:0] data;
    wire ctrl_done;

    image_read image_read_inst(HCLK,HRESETn,VSYNC,HSYNC,data,ctrl_done);

    always #10 HCLK = ~HCLK;

    initial begin
        $dumpfile("tb_image_read.vcd");
        $dumpvars(0);
        HCLK = 0;
        HRESETn = 0;
        #25
        HRESETn = 1;
        #1000
        $finish;
    end

endmodule