data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v:122: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v:206: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'current_bit_index\' generates 3 bits.\n                                                                                             : ... In instance spi_slave\n      end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v:202: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'current_bit_index\' generates 3 bits.\n                                                                                             : ... In instance spi_slave\n      if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin\n                            ^~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v:219: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/spi_slave.v:273: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module spi_slave #(
  parameter CLK_FREQUENCY = 50000000,
  parameter SPI_FREQUENCY = 10000000
) (




  input  wire sclk,
  input  wire cs_n,
  input  wire mosi,
  output wire miso,





  input  wire clk,
  input  wire rst,

  output reg  data_in_required,
  input  wire data_in_valid,
  input  wire [7:0] data_in,

  output reg  data_out_valid,
  output reg  [7:0] data_out,

  output wire active
);

  wire [0:0] data_request_clk;
  wire [0:0] reception_complete_clk;





  reg [7:0] receiver_reg;
  reg [2:0] current_bit_index;
  reg       reception_complete_sclk = 1'b0;
  reg [7:0] received_word;

  always @(posedge sclk or posedge cs_n) begin

    if (cs_n) begin
      receiver_reg <= 8'b0;
    end

    else begin

      receiver_reg <= {receiver_reg[6:0], mosi};
    end
  end



  always @(posedge sclk) begin

    if (current_bit_index == 7) begin
      reception_complete_sclk <= 1'b1;
      received_word <= {receiver_reg[6:0], mosi};


    end else if (current_bit_index == 3) begin
      reception_complete_sclk <= 1'b0;
    end
  end





  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) data_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (reception_complete_sclk),
    .out (reception_complete_clk)
  );





  reg reception_complete_clk_delayed = 1'b0;


  always @(posedge clk) begin

    reception_complete_clk_delayed <= reception_complete_clk;
  end


  always @(posedge clk) begin
    if (rst) begin
      data_out_valid <= 1'b0;
      data_out <= 8'b0;
    end
    else begin

      data_out_valid <= 1'b0;


      if (reception_complete_clk & ~reception_complete_clk_delayed) begin


        data_out <= received_word;
        data_out_valid <= 1'b1;
      end
    end
  end









  localparam SCLK_CYCLES_DURING_DATA_REQ  = (8*SPI_FREQUENCY + CLK_FREQUENCY-1)/CLK_FREQUENCY;

  localparam DATA_REQ_BIT_INDEX = 8 - SCLK_CYCLES_DURING_DATA_REQ;

  reg [7:0] transmit_bits;
  reg [7:0] transmit_word;
  reg       data_request_sclk = 1'b0;

  always @(negedge sclk or posedge cs_n) begin

    if (cs_n) begin
      current_bit_index <= 3'b0;
      data_request_sclk <= 1'b0;
      transmit_bits <= 8'b0;
    end

    else begin

      if (current_bit_index == 7) begin
        transmit_bits <= transmit_word;
      end else begin
        transmit_bits <= {transmit_bits[6:0], 1'b0};
      end


      current_bit_index <= current_bit_index + 1'b1;


      if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin
        data_request_sclk <= 1'b1;


      end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin
        data_request_sclk <= 1'b0;
      end
    end
  end


  assign miso = cs_n ? 1'bz : transmit_bits[7];





  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) request_sync_inst (
    .clk (clk),
    .rst (rst),
    .in  (data_request_sclk),
    .out (data_request_clk)
  );





  reg data_request_clk_delayed;

  always @(posedge clk) begin
    if (rst) begin
      data_request_clk_delayed <= 1'b0;
      data_in_required <= 1'b0;
      transmit_word <= 8'b0;
    end
    else begin

      data_in_required <= 1'b0;


      data_request_clk_delayed <= data_request_clk;


      if (~data_request_clk_delayed & data_request_clk) begin
        data_in_required <= 1'b1;
      end


      if (data_in_required) begin
        if (data_in_valid) begin
          transmit_word <= data_in;
        end else begin
          transmit_word <= 8'b0;
        end
      end
    end
  end






  wire cs_n_clk;
  assign active = ~cs_n_clk;
  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b1),
    .FALSE_PATH_TO_IN (1)
  ) active_sync_inst (
    .clk (clk),
    .rst (rst),
    .in  (cs_n),
    .out (cs_n_clk)
  );

endmodule
module spi_slave #(
  parameter CLK_FREQUENCY = 50000000,
  parameter SPI_FREQUENCY = 10000000
) (




  input  wire sclk,
  input  wire cs_n,
  input  wire mosi,
  output wire miso,





  input  wire clk,
  input  wire rst,

  output reg  data_in_required,
  input  wire data_in_valid,
  input  wire [7:0] data_in,

  output reg  data_out_valid,
  output reg  [7:0] data_out,

  output wire active
);


  wire [0:0] data_request_clk;
  wire [0:0] reception_complete_clk;





  reg [7:0] receiver_reg;
  reg [2:0] current_bit_index;
  reg       reception_complete_sclk = 1'b0;
  reg [7:0] received_word;

  always @(posedge sclk or posedge cs_n) begin

    if (cs_n) begin
      receiver_reg <= 8'b0;
    end

    else begin

      receiver_reg <= {receiver_reg[6:0], mosi};
    end
  end



  always @(posedge sclk) begin

    if (current_bit_index == 7) begin
      reception_complete_sclk <= 1'b1;
      received_word <= {receiver_reg[6:0], mosi};


    end else if (current_bit_index == 3) begin
      reception_complete_sclk <= 1'b0;
    end
  end





  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) data_sync_inst (
    .clk (clk),
    .rst (1'b0),
    .in  (reception_complete_sclk),
    .out (reception_complete_clk)
  );





  reg reception_complete_clk_delayed = 1'b0;


  always @(posedge clk) begin

    reception_complete_clk_delayed <= reception_complete_clk;
  end


  always @(posedge clk) begin
    if (rst) begin
      data_out_valid <= 1'b0;
      data_out <= 8'b0;
    end
    else begin

      data_out_valid <= 1'b0;


      if (reception_complete_clk & ~reception_complete_clk_delayed) begin


        data_out <= received_word;
        data_out_valid <= 1'b1;
      end
    end
  end









  localparam SCLK_CYCLES_DURING_DATA_REQ  = (8*SPI_FREQUENCY + CLK_FREQUENCY-1)/CLK_FREQUENCY;

  localparam DATA_REQ_BIT_INDEX = 8 - SCLK_CYCLES_DURING_DATA_REQ;

  reg [7:0] transmit_bits;
  reg [7:0] transmit_word;
  reg       data_request_sclk = 1'b0;

  always @(negedge sclk or posedge cs_n) begin

    if (cs_n) begin
      current_bit_index <= 3'b0;
      data_request_sclk <= 1'b0;
      transmit_bits <= 8'b0;
    end

    else begin

      if (current_bit_index == 7) begin
        transmit_bits <= transmit_word;
      end else begin
        transmit_bits <= {transmit_bits[6:0], 1'b0};
      end


      current_bit_index <= current_bit_index + 1'b1;


      if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin
        data_request_sclk <= 1'b1;


      end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin
        data_request_sclk <= 1'b0;
      end
    end
  end


  assign miso = cs_n ? 1'bz : transmit_bits[7];





  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) request_sync_inst (
    .clk (clk),
    .rst (rst),
    .in  (data_request_sclk),
    .out (data_request_clk)
  );





  reg data_request_clk_delayed;

  always @(posedge clk) begin
    if (rst) begin
      data_request_clk_delayed <= 1'b0;
      data_in_required <= 1'b0;
      transmit_word <= 8'b0;
    end
    else begin

      data_in_required <= 1'b0;


      data_request_clk_delayed <= data_request_clk;


      if (~data_request_clk_delayed & data_request_clk) begin
        data_in_required <= 1'b1;
      end


      if (data_in_required) begin
        if (data_in_valid) begin
          transmit_word <= data_in;
        end else begin
          transmit_word <= 8'b0;
        end
      end
    end
  end






  wire cs_n_clk;
  assign active = ~cs_n_clk;
  synchronizer #(
    .WIDTH            (1),
    .STAGES           (2),
    .INITIAL_VAL      (1'b1),
    .FALSE_PATH_TO_IN (1)
  ) active_sync_inst (
    .clk (clk),
    .rst (rst),
    .in  (cs_n),
    .out (cs_n_clk)
  );

endmodule