data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_lut_2(glb_rstn_i, config_i, logic_i, logic_o);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  input [3:0] config_i;
  input glb_rstn_i;
  input [1:0] logic_i;
  output logic_o;
  wire lut_out;
  wire sublut0_out;
  wire sublut1_out;
  assign _02_ = ~ sublut0_out;
  assign _03_ = ~ sublut1_out;
  assign _04_ = _02_ & _03_;
  assign _05_ = sublut0_out & sublut1_out;
  assign _06_ = ~ logic_i[1];
  assign _07_ = logic_i[1] ? sublut1_out : 1'h0;
  assign _08_ = _06_ ? sublut0_out : _07_;
  assign _09_ = _05_ ? 1'h1 : _08_;
  assign _10_ = _04_ ? 1'h0 : _09_;
  fpga_lut_1 \subluts.sublut0  (
    .config_i(config_i[1:0]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_i[0]),
    .logic_o(_00_)
  );
  fpga_lut_1 \subluts.sublut1  (
    .config_i(config_i[3:2]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_i[0]),
    .logic_o(_01_)
  );
  assign lut_out = _10_;
  assign sublut0_out = _00_;
  assign sublut1_out = _01_;
  assign logic_o = lut_out;
endmodule
module fpga_lut_2(glb_rstn_i, config_i, logic_i, logic_o);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  input [3:0] config_i;
  input glb_rstn_i;
  input [1:0] logic_i;
  output logic_o;
  wire lut_out;
  wire sublut0_out;
  wire sublut1_out;
  assign _02_ = ~ sublut0_out;
  assign _03_ = ~ sublut1_out;
  assign _04_ = _02_ & _03_;
  assign _05_ = sublut0_out & sublut1_out;
  assign _06_ = ~ logic_i[1];
  assign _07_ = logic_i[1] ? sublut1_out : 1'h0;
  assign _08_ = _06_ ? sublut0_out : _07_;
  assign _09_ = _05_ ? 1'h1 : _08_;
  assign _10_ = _04_ ? 1'h0 : _09_;
  fpga_lut_1 \subluts.sublut0  (
    .config_i(config_i[1:0]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_i[0]),
    .logic_o(_00_)
  );
  fpga_lut_1 \subluts.sublut1  (
    .config_i(config_i[3:2]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_i[0]),
    .logic_o(_01_)
  );
  assign lut_out = _10_;
  assign sublut0_out = _00_;
  assign sublut1_out = _01_;
  assign logic_o = lut_out;
endmodule