data/full_repos/permissive/425573648/fpga/output_pwm_gen.v
data/verilator_xmls/80944dbc-6a95-4933-a5fb-b476ba2ab94b.xml
module output_pwm_gen(
	input clk,
	input [15:0]rpm_command,
	output pwm
);


reg [31:0]counter;


always @(posedge clk)
	begin
		if (counter < 500000)
			begin

				counter <= counter + 1;
			end
		else
			begin

				counter <= 0;
			end
	end


assign pwm = (counter < (rpm_command * 50)) ? 1 : 0;

endmodule
module output_pwm_gen(
	input clk,
	input [15:0]rpm_command,
	output pwm
);



reg [31:0]counter;


always @(posedge clk)
	begin
		if (counter < 500000)
			begin

				counter <= counter + 1;
			end
		else
			begin

				counter <= 0;
			end
	end


assign pwm = (counter < (rpm_command * 50)) ? 1 : 0;

endmodule