data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new/SevensegDisplay.v
1: b"%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new/SevensegDisplay.v:43: Cannot find file containing module: 'Counter'\n    Counter #(20) c(counter,nreset,clock);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.v\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new/SevensegDisplay.v:44: Cannot find file containing module: 'Mux4to1'\n    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new/SevensegDisplay.v:45: Cannot find file containing module: 'Decoder4'\n    Decoder4 dec(sel,q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/new/SevensegDisplay.v:46: Cannot find file containing module: 'HexTo7Seg'\n    HexTo7Seg h(seg,d);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module SevensegDisplay(
	output wire [6:0] seg,
	output wire [3:0] an,
    input [3:0] digit0,
    input [3:0] digit1,
    input [3:0] digit2,
    input [3:0] digit3,
	input clock
);
    wire [1:0] q;
    wire [3:0] d;
    wire [3:0] sel;
    wire [19:0] counter;
    reg nreset;

    assign q = {counter[19],counter[18]};
    assign an = ~sel;

    initial nreset <= 1;

    Counter #(20) c(counter,nreset,clock);
    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule
module SevensegDisplay(
	output wire [6:0] seg,
	output wire [3:0] an,
    input [3:0] digit0,
    input [3:0] digit1,
    input [3:0] digit2,
    input [3:0] digit3,
	input clock
);

    wire [1:0] q;
    wire [3:0] d;
    wire [3:0] sel;
    wire [19:0] counter;
    reg nreset;

    assign q = {counter[19],counter[18]};
    assign an = ~sel;

    initial nreset <= 1;

    Counter #(20) c(counter,nreset,clock);
    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule