data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x100.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x100.v:110: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.sv\n             fpga_ram\n             fpga_ram.v\n             fpga_ram.sv\n             obj_dir/fpga_ram\n             obj_dir/fpga_ram.v\n             obj_dir/fpga_ram.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x100.v:117: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(\n^~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x100.v:124: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram2(\n^~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x100.v:131: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram3(\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ct_f_spsram_256x100(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);


input   [7 :0]  A;           
input           CEN;         
input           CLK;         
input   [99:0]  D;           
input           GWEN;        
input   [99:0]  WEN;         
output  [99:0]  Q;           


reg     [7 :0]  addr_holding; 


wire    [7 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [99:0]  D;           
wire            GWEN;        
wire    [99:0]  Q;           
wire    [99:0]  WEN;         
wire    [7 :0]  addr;        
wire    [24:0]  ram_din0;    
wire    [24:0]  ram_din1;    
wire    [24:0]  ram_din2;    
wire    [24:0]  ram_din3;    
wire    [24:0]  ram_dout0;   
wire    [24:0]  ram_dout1;   
wire    [24:0]  ram_dout2;   
wire    [24:0]  ram_dout3;   
wire            ram_wen0;    
wire            ram_wen1;    
wire            ram_wen2;    
wire            ram_wen3;    



parameter ADDR_WIDTH = 8;
parameter WRAP_SIZE  = 25;








assign ram_wen0 = !CEN && !WEN[24] && !GWEN;
assign ram_wen1 = !CEN && !WEN[49] && !GWEN;
assign ram_wen2 = !CEN && !WEN[74] && !GWEN;
assign ram_wen3 = !CEN && !WEN[99] && !GWEN;







assign ram_din0[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram_din1[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];
assign ram_din2[WRAP_SIZE-1:0] = D[3*WRAP_SIZE-1:2*WRAP_SIZE];
assign ram_din3[WRAP_SIZE-1:0] = D[4*WRAP_SIZE-1:3*WRAP_SIZE];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];






assign Q[WRAP_SIZE-1:0]                = ram_dout0[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE]      = ram_dout1[WRAP_SIZE-1:0];
assign Q[3*WRAP_SIZE-1:2*WRAP_SIZE]    = ram_dout2[WRAP_SIZE-1:0];
assign Q[4*WRAP_SIZE-1:3*WRAP_SIZE]    = ram_dout3[WRAP_SIZE-1:0];

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din0),
  .PortAWriteEnable(ram_wen0),
  .PortADataOut(ram_dout0));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din1),
  .PortAWriteEnable(ram_wen1),
  .PortADataOut(ram_dout1));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram2(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din2),
  .PortAWriteEnable(ram_wen2),
  .PortADataOut(ram_dout2));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram3(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din3),
  .PortAWriteEnable(ram_wen3),
  .PortADataOut(ram_dout3));


endmodule
module ct_f_spsram_256x100(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);



input   [7 :0]  A;           
input           CEN;         
input           CLK;         
input   [99:0]  D;           
input           GWEN;        
input   [99:0]  WEN;         
output  [99:0]  Q;           


reg     [7 :0]  addr_holding; 


wire    [7 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [99:0]  D;           
wire            GWEN;        
wire    [99:0]  Q;           
wire    [99:0]  WEN;         
wire    [7 :0]  addr;        
wire    [24:0]  ram_din0;    
wire    [24:0]  ram_din1;    
wire    [24:0]  ram_din2;    
wire    [24:0]  ram_din3;    
wire    [24:0]  ram_dout0;   
wire    [24:0]  ram_dout1;   
wire    [24:0]  ram_dout2;   
wire    [24:0]  ram_dout3;   
wire            ram_wen0;    
wire            ram_wen1;    
wire            ram_wen2;    
wire            ram_wen3;    



parameter ADDR_WIDTH = 8;
parameter WRAP_SIZE  = 25;








assign ram_wen0 = !CEN && !WEN[24] && !GWEN;
assign ram_wen1 = !CEN && !WEN[49] && !GWEN;
assign ram_wen2 = !CEN && !WEN[74] && !GWEN;
assign ram_wen3 = !CEN && !WEN[99] && !GWEN;







assign ram_din0[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram_din1[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];
assign ram_din2[WRAP_SIZE-1:0] = D[3*WRAP_SIZE-1:2*WRAP_SIZE];
assign ram_din3[WRAP_SIZE-1:0] = D[4*WRAP_SIZE-1:3*WRAP_SIZE];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];






assign Q[WRAP_SIZE-1:0]                = ram_dout0[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE]      = ram_dout1[WRAP_SIZE-1:0];
assign Q[3*WRAP_SIZE-1:2*WRAP_SIZE]    = ram_dout2[WRAP_SIZE-1:0];
assign Q[4*WRAP_SIZE-1:3*WRAP_SIZE]    = ram_dout3[WRAP_SIZE-1:0];

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din0),
  .PortAWriteEnable(ram_wen0),
  .PortADataOut(ram_dout0));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din1),
  .PortAWriteEnable(ram_wen1),
  .PortADataOut(ram_dout1));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram2(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din2),
  .PortAWriteEnable(ram_wen2),
  .PortADataOut(ram_dout2));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram3(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram_din3),
  .PortAWriteEnable(ram_wen3),
  .PortADataOut(ram_dout3));


endmodule