data/full_repos/permissive/448935247/cores/s16/hdl/jts16_obj_ram.v
1: b"%Error: data/full_repos/permissive/448935247/cores/s16/hdl/jts16_obj_ram.v:39: Cannot find file containing module: 'jtframe_dual_ram16'\njtframe_dual_ram16 #(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448935247/cores/s16/hdl,data/full_repos/permissive/448935247/jtframe_dual_ram16\n             data/full_repos/permissive/448935247/cores/s16/hdl,data/full_repos/permissive/448935247/jtframe_dual_ram16.v\n             data/full_repos/permissive/448935247/cores/s16/hdl,data/full_repos/permissive/448935247/jtframe_dual_ram16.sv\n             jtframe_dual_ram16\n             jtframe_dual_ram16.v\n             jtframe_dual_ram16.sv\n             obj_dir/jtframe_dual_ram16\n             obj_dir/jtframe_dual_ram16.v\n             obj_dir/jtframe_dual_ram16.sv\n%Error: Exiting due to 1 error(s)\n"
module jts16_obj_ram(
    input              rst,
    input              clk,


    input              obj_cs,
    input      [10:1]  cpu_addr,
    input      [15:0]  cpu_dout,
    input      [ 1:0]  dswn,
    output     [15:0]  cpu_din,


    input      [10:1]  tbl_addr,
    output     [15:0]  tbl_dout,
    input              tbl_we,
    input      [15:0]  tbl_din
);

wire [ 1:0] cpu_we = ~dswn & {2{obj_cs}};

jtframe_dual_ram16 #(
    .aw(10),
    .simfile_lo("obj_lo.bin"),
    .simfile_hi("obj_hi.bin")
) u_ram(
    .clk0   ( clk       ),
    .clk1   ( clk       ),


    .addr0  ( cpu_addr  ),
    .data0  ( cpu_dout  ),
    .we0    ( cpu_we    ),
    .q0     ( cpu_din   ),


    .addr1  ( tbl_addr  ),
    .data1  ( tbl_din   ),
    .we1    ({2{tbl_we}}),
    .q1     ( tbl_dout  )
);

endmodule
module jts16_obj_ram(
    input              rst,
    input              clk,


    input              obj_cs,
    input      [10:1]  cpu_addr,
    input      [15:0]  cpu_dout,
    input      [ 1:0]  dswn,
    output     [15:0]  cpu_din,


    input      [10:1]  tbl_addr,
    output     [15:0]  tbl_dout,
    input              tbl_we,
    input      [15:0]  tbl_din
);


wire [ 1:0] cpu_we = ~dswn & {2{obj_cs}};

jtframe_dual_ram16 #(
    .aw(10),
    .simfile_lo("obj_lo.bin"),
    .simfile_hi("obj_hi.bin")
) u_ram(
    .clk0   ( clk       ),
    .clk1   ( clk       ),


    .addr0  ( cpu_addr  ),
    .data0  ( cpu_dout  ),
    .we0    ( cpu_we    ),
    .q0     ( cpu_din   ),


    .addr1  ( tbl_addr  ),
    .data1  ( tbl_din   ),
    .we1    ({2{tbl_we}}),
    .q1     ( tbl_dout  )
);

endmodule