data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_4f = ~clk_4f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_word32_8bits.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:21: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:25: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:30: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:35: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:41: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #32 $finish;\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:53: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [1:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:53: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:55: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:55: syntax error, unexpected \'[\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                       ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:56: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:58: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:58: syntax error, unexpected \'[\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                         ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/word32-8bits/probador_word32_8bits.v:59: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 15 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_word32_8bits (
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input valid_out_c,
	input [7:0] Data_out_c,
	input valid_out_e,
	input [7:0] Data_out_e
);
	initial clk_4f = 0;
	always #1 clk_4f = ~clk_4f;

	initial begin
		$dumpfile ("prueba_word32_8bits.vcd");
		$dumpvars;
		
		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'h0;
		@(posedge clk_4f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFAAFFBB;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		Data_in <= 'hDDCCDDEE;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 1;
		Data_in <= 'h010F0A03;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		Data_in <= 8'h0;
		valid_in <= 0;
		#32 $finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_word32_8bits (
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input valid_out_c,
	input [7:0] Data_out_c,
	input valid_out_e,
	input [7:0] Data_out_e
);

	initial clk_4f = 0;
	always #1 clk_4f = ~clk_4f;

	initial begin
		$dumpfile ("prueba_word32_8bits.vcd");
		$dumpvars;
		
		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'h0;
		@(posedge clk_4f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFAAFFBB;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		Data_in <= 'hDDCCDDEE;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 1;
		Data_in <= 'h010F0A03;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		Data_in <= 8'h0;
		valid_in <= 0;
		#32 $finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule