data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/testbench/wfg_drive_spi_tb.sv
1: b"%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/testbench/wfg_drive_spi_tb.sv:44: Cannot find file containing module: 'wfg_drive_spi_top'\n    wfg_drive_spi_top wfg_drive_spi_top (\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/testbench,data/full_repos/permissive/500717851/wfg_drive_spi_top\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/testbench,data/full_repos/permissive/500717851/wfg_drive_spi_top.v\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/testbench,data/full_repos/permissive/500717851/wfg_drive_spi_top.sv\n             wfg_drive_spi_top\n             wfg_drive_spi_top.v\n             wfg_drive_spi_top.sv\n             obj_dir/wfg_drive_spi_top\n             obj_dir/wfg_drive_spi_top.v\n             obj_dir/wfg_drive_spi_top.sv\n%Error: Exiting due to 1 error(s)\n"
module wfg_drive_spi_tb #(
    parameter int BUSW = 32,
    parameter int AXIS_DATA_WIDTH = 32
) (

    input               io_wbs_clk,
    input               io_wbs_rst,
    input  [(BUSW-1):0] io_wbs_adr,
    input  [(BUSW-1):0] io_wbs_datwr,
    output [(BUSW-1):0] io_wbs_datrd,
    input               io_wbs_we,
    input               io_wbs_stb,
    output              io_wbs_ack,
    input               io_wbs_cyc,


    input logic wfg_core_sync_i,
    input logic wgf_core_subcycle_i,


    output wire                        wfg_axis_tready,
    input  logic                       wfg_axis_tvalid,
    input  logic                       wfg_axis_tlast,
    input  logic [AXIS_DATA_WIDTH-1:0] wfg_axis_tdata,


    output wire wfg_drive_spi_sclk_o,
    output wire wfg_drive_spi_cs_no,
    output wire wfg_drive_spi_sdo_o,
    input  wire wfg_drive_spi_sdi_i
);

    wfg_drive_spi_top wfg_drive_spi_top (
        .wb_clk_i (io_wbs_clk),
        .wb_rst_i (io_wbs_rst),
        .wbs_stb_i(io_wbs_stb),
        .wbs_cyc_i(io_wbs_cyc),
        .wbs_we_i (io_wbs_we),
        .wbs_sel_i(4'b1111),
        .wbs_dat_i(io_wbs_datwr),
        .wbs_adr_i(io_wbs_adr),
        .wbs_ack_o(io_wbs_ack),
        .wbs_dat_o(io_wbs_datrd),

        .wfg_core_sync_i(wfg_core_sync_i),
        .wfg_core_subcycle_i(wgf_core_subcycle_i),

        .wfg_axis_tready_o(wfg_axis_tready),
        .wfg_axis_tdata_i (wfg_axis_tdata),
        .wfg_axis_tlast_i (wfg_axis_tlast),
        .wfg_axis_tvalid_i(wfg_axis_tvalid),

        .wfg_drive_spi_sclk_o(wfg_drive_spi_sclk_o),
        .wfg_drive_spi_cs_no (wfg_drive_spi_cs_no),
        .wfg_drive_spi_sdo_o (wfg_drive_spi_sdo_o)
    );


`ifndef VERILATOR
    initial begin
        $dumpfile("wfg_drive_spi_tb.vcd");
        $dumpvars(0, wfg_drive_spi_tb);
    end
`endif

endmodule
module wfg_drive_spi_tb #(
    parameter int BUSW = 32,
    parameter int AXIS_DATA_WIDTH = 32
) (

    input               io_wbs_clk,
    input               io_wbs_rst,
    input  [(BUSW-1):0] io_wbs_adr,
    input  [(BUSW-1):0] io_wbs_datwr,
    output [(BUSW-1):0] io_wbs_datrd,
    input               io_wbs_we,
    input               io_wbs_stb,
    output              io_wbs_ack,
    input               io_wbs_cyc,


    input logic wfg_core_sync_i,
    input logic wgf_core_subcycle_i,


    output wire                        wfg_axis_tready,
    input  logic                       wfg_axis_tvalid,
    input  logic                       wfg_axis_tlast,
    input  logic [AXIS_DATA_WIDTH-1:0] wfg_axis_tdata,


    output wire wfg_drive_spi_sclk_o,
    output wire wfg_drive_spi_cs_no,
    output wire wfg_drive_spi_sdo_o,
    input  wire wfg_drive_spi_sdi_i
);


    wfg_drive_spi_top wfg_drive_spi_top (
        .wb_clk_i (io_wbs_clk),
        .wb_rst_i (io_wbs_rst),
        .wbs_stb_i(io_wbs_stb),
        .wbs_cyc_i(io_wbs_cyc),
        .wbs_we_i (io_wbs_we),
        .wbs_sel_i(4'b1111),
        .wbs_dat_i(io_wbs_datwr),
        .wbs_adr_i(io_wbs_adr),
        .wbs_ack_o(io_wbs_ack),
        .wbs_dat_o(io_wbs_datrd),

        .wfg_core_sync_i(wfg_core_sync_i),
        .wfg_core_subcycle_i(wgf_core_subcycle_i),

        .wfg_axis_tready_o(wfg_axis_tready),
        .wfg_axis_tdata_i (wfg_axis_tdata),
        .wfg_axis_tlast_i (wfg_axis_tlast),
        .wfg_axis_tvalid_i(wfg_axis_tvalid),

        .wfg_drive_spi_sclk_o(wfg_drive_spi_sclk_o),
        .wfg_drive_spi_cs_no (wfg_drive_spi_cs_no),
        .wfg_drive_spi_sdo_o (wfg_drive_spi_sdo_o)
    );


`ifndef VERILATOR
    initial begin
        $dumpfile("wfg_drive_spi_tb.vcd");
        $dumpvars(0, wfg_drive_spi_tb);
    end
`endif

endmodule