data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_tidbits_syn_reset.v
data/verilator_xmls/1dce7d19-6f1b-4a1a-be4d-e02e63c0f22a.xml
module syn_reset (clk,reset,a,c);
   input clk;
   input reset;
   input a; 
   output c; 

   wire clk;
   wire reset;   
   wire a;   
   reg c;
  
always @ (posedge clk )
  if ( reset == 1'b1) begin
    c <= 0;
  end else begin
    c <= a;
  end
 
endmodule
module syn_reset (clk,reset,a,c);

   input clk;
   input reset;
   input a; 
   output c; 

   wire clk;
   wire reset;   
   wire a;   
   reg c;
  
always @ (posedge clk )
  if ( reset == 1'b1) begin
    c <= 0;
  end else begin
    c <= a;
  end
 
endmodule