data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v:52: Cannot find include file: ../opl3.vh\n`include "../opl3.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.sv\n             ../opl3.vh\n             ../opl3.vh.v\n             ../opl3.vh.sv\n             obj_dir/../opl3.vh\n             obj_dir/../opl3.vh.v\n             obj_dir/../opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v:58: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v:59: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v:60: Define or directive not defined: \'`REG_KSL_WIDTH\'\n    input wire [`REG_KSL_WIDTH-1:0] ksl,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/ksl_add_rom.v:66: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire [`REG_FNUM_WIDTH-6-1:0] fnum_shifted;\n          ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module ksl_add_rom # (
    KSL_ADD_WIDTH = 8
) (
    input wire clk,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    output reg [KSL_ADD_WIDTH-1:0] ksl_add = 0
);
    reg [6:0] rom_out = 0;
    wire signed [KSL_ADD_WIDTH-1:0] tmp0;
    wire signed [KSL_ADD_WIDTH-1:0] tmp1;
    wire [`REG_FNUM_WIDTH-6-1:0] fnum_shifted;
    
    assign fnum_shifted = fnum >> 6;
    
    always @(posedge clk)
        case (fnum_shifted)
        0: rom_out <= 0;
        1: rom_out <= 32;
        2: rom_out <= 40;
        3: rom_out <= 45;
        4: rom_out <= 48;
        5: rom_out <= 51;
        6: rom_out <= 53;
        7: rom_out <= 55;
        8: rom_out <= 56;
        9: rom_out <= 58;
        10: rom_out <= 59;
        11: rom_out <= 60;
        12: rom_out <= 61;
        13: rom_out <= 62;
        14: rom_out <= 63;
        15: rom_out <= 64;
        endcase
    
    assign tmp0 = block - 8;            
    assign tmp1 = rom_out + (tmp0 << 3);
    
    always @(posedge clk)
        case (ksl)
        0: ksl_add <= 0;
        1: ksl_add <= tmp1 <= 0 ? 0 : tmp1 << 1;
        2: ksl_add <= tmp1 <= 0 ? 0 : tmp1;
        3: ksl_add <= tmp1 <= 0 ? 0 : tmp1 << 2;
        endcase
endmodule
module ksl_add_rom # (
    KSL_ADD_WIDTH = 8
) (
    input wire clk,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    output reg [KSL_ADD_WIDTH-1:0] ksl_add = 0
);

    reg [6:0] rom_out = 0;
    wire signed [KSL_ADD_WIDTH-1:0] tmp0;
    wire signed [KSL_ADD_WIDTH-1:0] tmp1;
    wire [`REG_FNUM_WIDTH-6-1:0] fnum_shifted;
    
    assign fnum_shifted = fnum >> 6;
    
    always @(posedge clk)
        case (fnum_shifted)
        0: rom_out <= 0;
        1: rom_out <= 32;
        2: rom_out <= 40;
        3: rom_out <= 45;
        4: rom_out <= 48;
        5: rom_out <= 51;
        6: rom_out <= 53;
        7: rom_out <= 55;
        8: rom_out <= 56;
        9: rom_out <= 58;
        10: rom_out <= 59;
        11: rom_out <= 60;
        12: rom_out <= 61;
        13: rom_out <= 62;
        14: rom_out <= 63;
        15: rom_out <= 64;
        endcase
    
    assign tmp0 = block - 8;            
    assign tmp1 = rom_out + (tmp0 << 3);
    
    always @(posedge clk)
        case (ksl)
        0: ksl_add <= 0;
        1: ksl_add <= tmp1 <= 0 ? 0 : tmp1 << 1;
        2: ksl_add <= tmp1 <= 0 ? 0 : tmp1;
        3: ksl_add <= tmp1 <= 0 ? 0 : tmp1 << 2;
        endcase
endmodule