data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:45: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:46: Cannot find include file: tlp.vh\n`include "tlp.vh" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:63: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:65: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:66: Define or directive not defined: \'`SIG_BARDECODE_W\'\n     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:77: Define or directive not defined: \'`SIG_FBE_W\'\n     output [`SIG_FBE_W-1:0]                              RXR_META_FDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:78: Define or directive not defined: \'`SIG_LBE_W\'\n     output [`SIG_LBE_W-1:0]                              RXR_META_LDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:79: Define or directive not defined: \'`SIG_TC_W\'\n     output [`SIG_TC_W-1:0]                               RXR_META_TC,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:80: Define or directive not defined: \'`SIG_ATTR_W\'\n     output [`SIG_ATTR_W-1:0]                             RXR_META_ATTR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:81: Define or directive not defined: \'`SIG_TAG_W\'\n     output [`SIG_TAG_W-1:0]                              RXR_META_TAG,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:82: Define or directive not defined: \'`SIG_TYPE_W\'\n     output [`SIG_TYPE_W-1:0]                             RXR_META_TYPE,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:83: Define or directive not defined: \'`SIG_ADDR_W\'\n     output [`SIG_ADDR_W-1:0]                             RXR_META_ADDR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:84: Define or directive not defined: \'`SIG_BARDECODE_W\'\n     output [`SIG_BARDECODE_W-1:0]                        RXR_META_BAR_DECODED,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:85: Define or directive not defined: \'`SIG_REQID_W\'\n     output [`SIG_REQID_W-1:0]                            RXR_META_REQUESTER_ID,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:86: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]                              RXR_META_LENGTH,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:92: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:100: Define or directive not defined: \'`SIG_FBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:100: Define or directive not defined: \'`SIG_LBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:100: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                                                 ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:109: Define or directive not defined: \'`TLP_REQADDRDW1_I\'\n    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:109: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:113: Define or directive not defined: \'`TLP_REQADDRDW0_I\'\n    localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:113: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:114: Define or directive not defined: \'`TLP_REQADDRDW1_I\'\n    localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:114: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:115: Define or directive not defined: \'`TLP_REQMETADW0_I\'\n    localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:115: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:116: Define or directive not defined: \'`TLP_REQMETADW1_I\'\n    localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:116: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:118: Define or directive not defined: \'`TLP_REQADDRDW0_I\'\n    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:118: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:119: Define or directive not defined: \'`TLP_REQADDRDW1_I\'\n    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:119: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:122: Define or directive not defined: \'`TLP_4DWHBIT_I\'\n                                          `TLP_4DWHBIT_I;\n                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                                          `TLP_4DWHBIT_I;\n                                                        ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:124: Define or directive not defined: \'`TLP_REQMETADW0_I\'\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:124: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:125: Define or directive not defined: \'`TLP_REQMETADW1_I\'\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:125: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:129: Define or directive not defined: \'`TLP_MAXHDR_W\'\n    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:134: Define or directive not defined: \'`TLP_TYPE_W\'\n    wire [`TLP_TYPE_W-1:0]                                wType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:135: Define or directive not defined: \'`TLP_LEN_W\'\n    wire [`TLP_LEN_W-1:0]                                 wLength;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:139: Define or directive not defined: \'`TLP_REQADDR_W\'\n    wire [31:0]                                           wAddrMux[(`TLP_REQADDR_W / 32)-1:0];\n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:139: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    wire [31:0]                                           wAddrMux[(`TLP_REQADDR_W / 32)-1:0];\n                                                                                   ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:160: Define or directive not defined: \'`SIG_ADDR_W\'\n    wire [`SIG_ADDR_W-1:0]                                wRxrMetaAddr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:205: Define or directive not defined: \'`TLP_LEN_R\'\n    assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:205: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];\n                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:206: Define or directive not defined: \'`TLP_TC_R\'\n    assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:206: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];\n                                               ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxr_engine_classic.v:207: Define or directive not defined: \'`TLP_ATTR1_R\'\n    assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};\n                                         ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rxr_engine_classic
    #(parameter C_VENDOR = "ALTERA",
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                                CLK,


     input                                                RST_IN,


     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
     input                                                RX_TLP_VALID,
     input                                                RX_TLP_START_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
     input                                                RX_TLP_END_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,


     output [C_PCI_DATA_WIDTH-1:0]                        RXR_DATA,
     output                                               RXR_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXR_DATA_WORD_ENABLE,
     output                                               RXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_START_OFFSET,
     output                                               RXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_END_OFFSET,
    
     output [`SIG_FBE_W-1:0]                              RXR_META_FDWBE,
     output [`SIG_LBE_W-1:0]                              RXR_META_LDWBE,
     output [`SIG_TC_W-1:0]                               RXR_META_TC,
     output [`SIG_ATTR_W-1:0]                             RXR_META_ATTR,
     output [`SIG_TAG_W-1:0]                              RXR_META_TAG,
     output [`SIG_TYPE_W-1:0]                             RXR_META_TYPE,
     output [`SIG_ADDR_W-1:0]                             RXR_META_ADDR,
     output [`SIG_BARDECODE_W-1:0]                        RXR_META_BAR_DECODED,
     output [`SIG_REQID_W-1:0]                            RXR_META_REQUESTER_ID,
     output [`SIG_LEN_W-1:0]                              RXR_META_LENGTH,
     output                                               RXR_META_EP,


     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
     );




    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);

    localparam C_RX_INPUT_STAGES = 1;
    localparam C_RX_OUTPUT_STAGES = 1;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
    


    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;

    localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;

    localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;

    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + 
                                          C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
                                          `TLP_4DWHBIT_I;
    
    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);

    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
    localparam C_MAX_ABLANK_WIDTH = 32;
    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
    localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);

    wire [63:0]                                           wAddrFmt;
    wire [63:0]                                           wMetadata;
    wire [`TLP_TYPE_W-1:0]                                wType;
    wire [`TLP_LEN_W-1:0]                                 wLength;
    wire                                                  wAddrDW0Bit2;
    wire                                                  wAddrDW1Bit2;
    wire                                                  wAddrHiReset;
    wire [31:0]                                           wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
    wire [63:0]                                           wAddr;
    wire                                                  w4DWH;
    wire                                                  wHasPayload;
    wire [2:0]                                            wHdrLength;
    wire [2:0]                                            wHdrLengthM1;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wEndMask;
    wire                                                  _wEndFlag;
    wire                                                  wEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wStartMask;
    wire [3:0]                                            wStartFlags;
    wire                                                  wStartFlag;
    wire                                                  _wStartFlag;
    wire [clog2s(C_MAX_START_OFFSET)-1:0]                 wStartOffset;
    wire                                                  wInsertBlank;
    wire                                                  wRotateAddressField;


    wire [C_PCI_DATA_WIDTH-1:0]                           wRxrData;

    wire [`SIG_ADDR_W-1:0]                                wRxrMetaAddr;
    wire [63:0]                                           wRxrMetadata;
    wire                                                  wRxrDataValid;
    wire                                                  wRxrDataReady;
    wire                                                  wRxrDataEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxrDataWordEnable;
    wire                                                  wRxrDataStartFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataStartOffset;

    wire [C_RX_PIPELINE_DEPTH:0]                          wRxSrSop;

    reg                                                   rValid,_rValid;

    
    assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];



    assign wRotateAddressField = w4DWH;
    assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
    assign wAddrMux[0] = wAddr[31:0];    
    assign wAddrMux[1] = wAddr[63:32];    

    assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
    assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};

    assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
    

    assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank});
    assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;



    assign wRxrDataReady = 1;

    assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
    assign RXR_DATA_VALID = wRxrDataValid;
    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
    assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
    assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;

    assign RXR_META_BAR_DECODED = 0;
    assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
    assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
    assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
    assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
    assign RXR_META_ADDR = wRxrMetaAddr;
    assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
    assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
    assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
    assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
    assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
    
    assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
    assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
    assign _wStartFlag = wStartFlags != 0;
    generate
        if(C_PCI_DATA_WIDTH == 32) begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I];
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I];
        end else if(C_PCI_DATA_WIDTH == 64) begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            if(C_VENDOR == "ALTERA") begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2];
            end else begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I];
            end
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I];
        end else if (C_PCI_DATA_WIDTH == 128) begin    
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            if(C_VENDOR == "ALTERA") begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2];
            end else begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
            end
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I];
        end else begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = 0;
            assign wStartFlags[1] = 0;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
        end
    endgenerate

    
    always @(*) begin
        _rValid = rValid;
        if(_wStartFlag) begin
	        _rValid = 1'b1;
        end else if (wEndFlag) begin
	        _rValid = 1'b0;
        end
    end
    
    always @(posedge CLK) begin
        if(RST_IN) begin
	        rValid <= 1'b0;
        end else begin
	        rValid <= _rValid;
        end
    end
    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    o2m_ef
        (

         .MASK                          (wEndMask),

         .OFFSET_ENABLE                 (wEndFlag),
         .OFFSET                        (wEndOffset[C_OFFSET_WIDTH-1:0])
);
    generate
        if(C_RX_OUTPUT_STAGES == 0) begin
            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
        end else begin
            register
                #(

                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
                  .C_VALUE              (0)
)
            dw_enable
                (
                 .RD_DATA               (wRxrDataWordEnable),

                 .RST_IN                (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
                 .WR_DATA               (wEndMask & wStartMask),
                 .WR_EN                 (1),

                 .CLK                   (CLK));

            pipeline
                #(

                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
                  .C_USE_MEMORY                 (0)
)
            dw_pipeline
                (

                 .WR_DATA_READY                 (),
                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
                 .RD_DATA_VALID                 (),

                 .WR_DATA                       (wRxrDataWordEnable),
                 .WR_DATA_VALID                 (1),
                 .RD_DATA_READY                 (1'b1),


                 .CLK                           (CLK),
                 .RST_IN                        (RST_IN));
        end
    endgenerate
    
    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    metadata_DW0_register
        (

         .RD_DATA                       (wMetadata[31:0]),

         .WR_DATA                       (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    meta_DW1_register
        (

         .RD_DATA                       (wMetadata[63:32]),

         .WR_DATA                       (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    addr_DW0_register
        (

         .RD_DATA                       (wAddr[31:0]),

         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    addr_DW1_register
        (

         .RD_DATA                       (wAddr[63:32]),

         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
         .RST_IN                        (RST_IN | (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE])),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (2),
          .C_VALUE                      (0)
)
    metadata_4DWH_register
        (

         .RD_DATA                       ({wHasPayload,w4DWH}),

         .WR_DATA                       (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
         .WR_EN                         (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (`TLP_TYPE_W),
          .C_VALUE                      (0)
)
    metadata_type_register
        (

         .RD_DATA                       (wType),

         .WR_DATA                       (RX_SR_DATA[(`TLP_TYPE_I) +: `TLP_TYPE_W]),
         .WR_EN                         (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (`TLP_LEN_W),
          .C_VALUE                      (0)
)
    metadata_length_register
        (

         .RD_DATA                       (wLength),

         .WR_DATA                       (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
         .WR_EN                         (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    addr_DW0_bit_2_register
        (

         .RD_DATA                       (wAddrDW0Bit2),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    addr_DW1_bit_2_register
        (

         .RD_DATA                       (wAddrDW1Bit2),

         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    start_flag_register
        (

         .RD_DATA                       (wStartFlag),

         .WR_DATA                       (_wStartFlag),
         .WR_EN                         (1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
    
    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
         .RD_DATA_VALID                 (wRxrDataValid),

         .WR_DATA                       ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
         .WR_DATA_VALID                 (rValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    sop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrSop),

         .WR_DATA                       (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
    
endmodule
module rxr_engine_classic
    #(parameter C_VENDOR = "ALTERA",
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                                CLK,


     input                                                RST_IN,


     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
     input                                                RX_TLP_VALID,
     input                                                RX_TLP_START_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
     input                                                RX_TLP_END_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,


     output [C_PCI_DATA_WIDTH-1:0]                        RXR_DATA,
     output                                               RXR_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXR_DATA_WORD_ENABLE,
     output                                               RXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_START_OFFSET,
     output                                               RXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXR_DATA_END_OFFSET,
    
     output [`SIG_FBE_W-1:0]                              RXR_META_FDWBE,
     output [`SIG_LBE_W-1:0]                              RXR_META_LDWBE,
     output [`SIG_TC_W-1:0]                               RXR_META_TC,
     output [`SIG_ATTR_W-1:0]                             RXR_META_ATTR,
     output [`SIG_TAG_W-1:0]                              RXR_META_TAG,
     output [`SIG_TYPE_W-1:0]                             RXR_META_TYPE,
     output [`SIG_ADDR_W-1:0]                             RXR_META_ADDR,
     output [`SIG_BARDECODE_W-1:0]                        RXR_META_BAR_DECODED,
     output [`SIG_REQID_W-1:0]                            RXR_META_REQUESTER_ID,
     output [`SIG_LEN_W-1:0]                              RXR_META_LENGTH,
     output                                               RXR_META_EP,


     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
     );





    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);

    localparam C_RX_INPUT_STAGES = 1;
    localparam C_RX_OUTPUT_STAGES = 1;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
    


    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;

    localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;

    localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
    localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;

    localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
    localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + 
                                          C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
                                          `TLP_4DWHBIT_I;
    
    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);

    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
    localparam C_MAX_ABLANK_WIDTH = 32;
    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
    localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);

    wire [63:0]                                           wAddrFmt;
    wire [63:0]                                           wMetadata;
    wire [`TLP_TYPE_W-1:0]                                wType;
    wire [`TLP_LEN_W-1:0]                                 wLength;
    wire                                                  wAddrDW0Bit2;
    wire                                                  wAddrDW1Bit2;
    wire                                                  wAddrHiReset;
    wire [31:0]                                           wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
    wire [63:0]                                           wAddr;
    wire                                                  w4DWH;
    wire                                                  wHasPayload;
    wire [2:0]                                            wHdrLength;
    wire [2:0]                                            wHdrLengthM1;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wEndMask;
    wire                                                  _wEndFlag;
    wire                                                  wEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wStartMask;
    wire [3:0]                                            wStartFlags;
    wire                                                  wStartFlag;
    wire                                                  _wStartFlag;
    wire [clog2s(C_MAX_START_OFFSET)-1:0]                 wStartOffset;
    wire                                                  wInsertBlank;
    wire                                                  wRotateAddressField;


    wire [C_PCI_DATA_WIDTH-1:0]                           wRxrData;

    wire [`SIG_ADDR_W-1:0]                                wRxrMetaAddr;
    wire [63:0]                                           wRxrMetadata;
    wire                                                  wRxrDataValid;
    wire                                                  wRxrDataReady;
    wire                                                  wRxrDataEndFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataEndOffset;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxrDataWordEnable;
    wire                                                  wRxrDataStartFlag;
    wire [C_OFFSET_WIDTH-1:0]                             wRxrDataStartOffset;

    wire [C_RX_PIPELINE_DEPTH:0]                          wRxSrSop;

    reg                                                   rValid,_rValid;

    
    assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];



    assign wRotateAddressField = w4DWH;
    assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
    assign wAddrMux[0] = wAddr[31:0];    
    assign wAddrMux[1] = wAddr[63:32];    

    assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
    assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};

    assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
    

    assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank});
    assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;



    assign wRxrDataReady = 1;

    assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
    assign RXR_DATA_VALID = wRxrDataValid;
    assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
    assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
    assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
    assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;

    assign RXR_META_BAR_DECODED = 0;
    assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
    assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
    assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
    assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
    assign RXR_META_ADDR = wRxrMetaAddr;
    assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
    assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
    assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
    assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
    assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
    
    assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
    assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
    assign _wStartFlag = wStartFlags != 0;
    generate
        if(C_PCI_DATA_WIDTH == 32) begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I];
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I];
        end else if(C_PCI_DATA_WIDTH == 64) begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            if(C_VENDOR == "ALTERA") begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2];
            end else begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I];
            end
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I];
        end else if (C_PCI_DATA_WIDTH == 128) begin    
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid;
            if(C_VENDOR == "ALTERA") begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2];
            end else begin
                assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
            end
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I];
        end else begin
            assign wStartFlags[3] = 0;
            assign wStartFlags[2] = 0;
            assign wStartFlags[1] = 0;
            assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
        end
    endgenerate

    
    always @(*) begin
        _rValid = rValid;
        if(_wStartFlag) begin
	        _rValid = 1'b1;
        end else if (wEndFlag) begin
	        _rValid = 1'b0;
        end
    end
    
    always @(posedge CLK) begin
        if(RST_IN) begin
	        rValid <= 1'b0;
        end else begin
	        rValid <= _rValid;
        end
    end
    assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    o2m_ef
        (

         .MASK                          (wEndMask),

         .OFFSET_ENABLE                 (wEndFlag),
         .OFFSET                        (wEndOffset[C_OFFSET_WIDTH-1:0])
);
    generate
        if(C_RX_OUTPUT_STAGES == 0) begin
            assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
        end else begin
            register
                #(

                  .C_WIDTH              (C_PCI_DATA_WIDTH/32),
                  .C_VALUE              (0)
)
            dw_enable
                (
                 .RD_DATA               (wRxrDataWordEnable),

                 .RST_IN                (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
                 .WR_DATA               (wEndMask & wStartMask),
                 .WR_EN                 (1),

                 .CLK                   (CLK));

            pipeline
                #(

                  .C_DEPTH                      (C_RX_OUTPUT_STAGES-1),
                  .C_WIDTH                      (C_PCI_DATA_WIDTH/32),
                  .C_USE_MEMORY                 (0)
)
            dw_pipeline
                (

                 .WR_DATA_READY                 (),
                 .RD_DATA                       (RXR_DATA_WORD_ENABLE),
                 .RD_DATA_VALID                 (),

                 .WR_DATA                       (wRxrDataWordEnable),
                 .WR_DATA_VALID                 (1),
                 .RD_DATA_READY                 (1'b1),


                 .CLK                           (CLK),
                 .RST_IN                        (RST_IN));
        end
    endgenerate
    
    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    metadata_DW0_register
        (

         .RD_DATA                       (wMetadata[31:0]),

         .WR_DATA                       (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW0_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    meta_DW1_register
        (

         .RD_DATA                       (wMetadata[63:32]),

         .WR_DATA                       (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_METADW1_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    addr_DW0_register
        (

         .RD_DATA                       (wAddr[31:0]),

         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW0_CYCLE]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (32),
          .C_VALUE                      (0)
)
    addr_DW1_register
        (

         .RD_DATA                       (wAddr[63:32]),

         .WR_DATA                       (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
         .WR_EN                         (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
         .RST_IN                        (RST_IN | (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE])),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (2),
          .C_VALUE                      (0)
)
    metadata_4DWH_register
        (

         .RD_DATA                       ({wHasPayload,w4DWH}),

         .WR_DATA                       (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
         .WR_EN                         (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (`TLP_TYPE_W),
          .C_VALUE                      (0)
)
    metadata_type_register
        (

         .RD_DATA                       (wType),

         .WR_DATA                       (RX_SR_DATA[(`TLP_TYPE_I) +: `TLP_TYPE_W]),
         .WR_EN                         (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (`TLP_LEN_W),
          .C_VALUE                      (0)
)
    metadata_length_register
        (

         .RD_DATA                       (wLength),

         .WR_DATA                       (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
         .WR_EN                         (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    addr_DW0_bit_2_register
        (

         .RD_DATA                       (wAddrDW0Bit2),

         .CLK                           (CLK),
         .RST_IN                        (RST_IN),
         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    addr_DW1_bit_2_register
        (

         .RD_DATA                       (wAddrDW1Bit2),

         .WR_DATA                       (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
         .WR_EN                         (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    register
        #(

          .C_WIDTH                      (1),
          .C_VALUE                      (0)
)
    start_flag_register
        (

         .RD_DATA                       (wStartFlag),

         .WR_DATA                       (_wStartFlag),
         .WR_EN                         (1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
    
    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
         .RD_DATA_VALID                 (wRxrDataValid),

         .WR_DATA                       ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
         .WR_DATA_VALID                 (rValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));



    shiftreg 
        #(

          .C_DEPTH                      (C_RX_PIPELINE_DEPTH),
          .C_WIDTH                      (1'b1)
)
    sop_shiftreg_inst
        (

         .RD_DATA                       (wRxSrSop),

         .WR_DATA                       (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
    
endmodule