data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv
1: b"%Error: data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv:49: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync J4 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(BSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({j4_dum5,INV,j4_dum3,j4_dum2,B1Y8,B1X8}));\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520811519/rtl/registers,data/full_repos/permissive/520811519/ttl_74174_sync\n             data/full_repos/permissive/520811519/rtl/registers,data/full_repos/permissive/520811519/ttl_74174_sync.v\n             data/full_repos/permissive/520811519/rtl/registers,data/full_repos/permissive/520811519/ttl_74174_sync.sv\n             ttl_74174_sync\n             ttl_74174_sync.v\n             ttl_74174_sync.sv\n             obj_dir/ttl_74174_sync\n             obj_dir/ttl_74174_sync.v\n             obj_dir/ttl_74174_sync.sv\n%Error: data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv:54: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync P3 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(SSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({SBK,p3_dum3,SD_COLOR_BANK}));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv:58: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync M5 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(MSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({F2Y8,F1Y8,F2X8,F1X8,m5_dum}));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv:61: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync P5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F1SY), .D(vdin_r), .Q(F1Y[7:0]));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/registers/IkariWarriorsCore_Registers.sv:64: Cannot find file containing module: 'ttl_74273_sync'\n ttl_74273_sync S5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F2SY), .D(vdin_r), .Q(F2Y[7:0]));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module IkariWarriorsCore_Registers(
  input wire VIDEO_RSTn,
  input wire reset,
  input wire clk,
  input wire [7:0] VD_in,


  input wire BSET,
  output logic INV,
  output logic INVn,
  output logic B1X8,
  output logic B1Y8,


  input wire SSET,
  output logic [1:0] SBK,
  output logic [2:0] SD_COLOR_BANK,


  input wire MSET,
  output logic F2Y8,
  output logic F2X8,
  output logic F1Y8,
  output logic F1X8,


  input wire F1SY,
  output logic [7:0] F1Y,


  input wire F2SY,
  output logic [7:0] F2Y
);
    reg [7:0] vdin_r;

     always @(posedge clk) begin
        vdin_r <= VD_in;
    end


    logic j4_dum5, j4_dum3, j4_dum2;
    ttl_74174_sync J4 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(BSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({j4_dum5,INV,j4_dum3,j4_dum2,B1Y8,B1X8}));
    assign INVn = ~INV;


    logic p3_dum3;
    ttl_74174_sync P3 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(SSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({SBK,p3_dum3,SD_COLOR_BANK}));


    logic [1:0] m5_dum;
    ttl_74174_sync M5 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(MSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({F2Y8,F1Y8,F2X8,F1X8,m5_dum}));


    ttl_74273_sync P5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F1SY), .D(vdin_r), .Q(F1Y[7:0]));


	ttl_74273_sync S5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F2SY), .D(vdin_r), .Q(F2Y[7:0]));
endmodule
module IkariWarriorsCore_Registers(
  input wire VIDEO_RSTn,
  input wire reset,
  input wire clk,
  input wire [7:0] VD_in,


  input wire BSET,
  output logic INV,
  output logic INVn,
  output logic B1X8,
  output logic B1Y8,


  input wire SSET,
  output logic [1:0] SBK,
  output logic [2:0] SD_COLOR_BANK,


  input wire MSET,
  output logic F2Y8,
  output logic F2X8,
  output logic F1Y8,
  output logic F1X8,


  input wire F1SY,
  output logic [7:0] F1Y,


  input wire F2SY,
  output logic [7:0] F2Y
);

    reg [7:0] vdin_r;

     always @(posedge clk) begin
        vdin_r <= VD_in;
    end


    logic j4_dum5, j4_dum3, j4_dum2;
    ttl_74174_sync J4 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(BSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({j4_dum5,INV,j4_dum3,j4_dum2,B1Y8,B1X8}));
    assign INVn = ~INV;


    logic p3_dum3;
    ttl_74174_sync P3 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(SSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({SBK,p3_dum3,SD_COLOR_BANK}));


    logic [1:0] m5_dum;
    ttl_74174_sync M5 (.Reset_n(VIDEO_RSTn), .Clk(clk), .Cen(MSET), .Clr_n(1'b1), .D(vdin_r[5:0]), .Q({F2Y8,F1Y8,F2X8,F1X8,m5_dum}));


    ttl_74273_sync P5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F1SY), .D(vdin_r), .Q(F1Y[7:0]));


	ttl_74273_sync S5(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(F2SY), .D(vdin_r), .Q(F2Y[7:0]));
endmodule