data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/mem2r1wx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/mem2r1wx.v:34: Cannot find file containing module: 'memrwpx'\nmemrwpx #(ADDRBIT,DEPTH,WIDTH) ram1 (rst_,wclk,wa,we,di,rclk1,ra1,do1);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/memrwpx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/memrwpx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/memrwpx.sv\n             memrwpx\n             memrwpx.v\n             memrwpx.sv\n             obj_dir/memrwpx\n             obj_dir/memrwpx.v\n             obj_dir/memrwpx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/mem2r1wx.v:35: Cannot find file containing module: 'memrwpx'\nmemrwpx #(ADDRBIT,DEPTH,WIDTH) ram2 (rst_,wclk,wa,we,di,rclk2,ra2,do2);\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mem2r1wx (rst_,wclk,wa,we,di,rclk1,ra1,do1,rclk2,ra2,do2);

parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               rst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk1;
input [ADDRBIT-1:0] ra1;
output [WIDTH-1:0]  do1;
input               rclk2;
input [ADDRBIT-1:0] ra2;
output [WIDTH-1:0]  do2;

memrwpx #(ADDRBIT,DEPTH,WIDTH) ram1 (rst_,wclk,wa,we,di,rclk1,ra1,do1);
memrwpx #(ADDRBIT,DEPTH,WIDTH) ram2 (rst_,wclk,wa,we,di,rclk2,ra2,do2);

endmodule
module mem2r1wx (rst_,wclk,wa,we,di,rclk1,ra1,do1,rclk2,ra2,do2);


parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               rst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk1;
input [ADDRBIT-1:0] ra1;
output [WIDTH-1:0]  do1;
input               rclk2;
input [ADDRBIT-1:0] ra2;
output [WIDTH-1:0]  do2;

memrwpx #(ADDRBIT,DEPTH,WIDTH) ram1 (rst_,wclk,wa,we,di,rclk1,ra1,do1);
memrwpx #(ADDRBIT,DEPTH,WIDTH) ram2 (rst_,wclk,wa,we,di,rclk2,ra2,do2);

endmodule