data/full_repos/permissive/522534105/RTL_files/Accumulator.v
data/verilator_xmls/2105aee8-5acf-480e-9c53-5efce40deced.xml
module Accumulator(
input i_clk ,   
input ld_Acc ,  
input [`WIDTH_ACC-1:0] i_data , 
output [`WIDTH_ACC-1:0] o_Acc );

reg [`WIDTH_ACC-1:0] o_Aout ;


always @(posedge i_clk )
        begin
           if (ld_Acc  ==1'b1)
                 begin

                           o_Aout <=  {i_data[4] , i_data[4:1]} ;
                           end
                                     else  
                                           begin
                                   o_Aout <=  {o_Aout[4] , o_Aout[4:1]};
                               end
       
    end          
                            
  assign o_Acc = o_Aout ;                           
           
endmodule
module Accumulator(
input i_clk ,   
input ld_Acc ,  
input [`WIDTH_ACC-1:0] i_data , 
output [`WIDTH_ACC-1:0] o_Acc );


reg [`WIDTH_ACC-1:0] o_Aout ;


always @(posedge i_clk )
        begin
           if (ld_Acc  ==1'b1)
                 begin

                           o_Aout <=  {i_data[4] , i_data[4:1]} ;
                           end
                                     else  
                                           begin
                                   o_Aout <=  {o_Aout[4] , o_Aout[4:1]};
                               end
       
    end          
                            
  assign o_Acc = o_Aout ;                           
           
endmodule