data/full_repos/permissive/469195529/sources/hdl/CounterV2.v
data/verilator_xmls/f2294648-09d5-4713-a618-7639d961466f.xml
module CounterV2#(parameter COUNT_TOP = 59, BIT_WIDTH = 6, THRESHOLD = 59)(
        input clk, load, reset,
        input [BIT_WIDTH-1:0]loadVal,
        output [BIT_WIDTH-1:0]Q,
        output OVF
    );
    reg [BIT_WIDTH-1:0] count;
    reg overflow;
    always@(posedge clk or posedge load or posedge reset)begin
        if(reset) count <= 0;
        else if(load) count <= loadVal;
        else begin
            if(~|count) count <= COUNT_TOP;
            else count <= count - 1;
        end
    end
    
    always@(count)begin
        if(count == THRESHOLD) overflow <= 1;
        else overflow <= 0;
    end
    
    assign Q = count;
    assign OVF = overflow;
endmodule
module CounterV2#(parameter COUNT_TOP = 59, BIT_WIDTH = 6, THRESHOLD = 59)(
        input clk, load, reset,
        input [BIT_WIDTH-1:0]loadVal,
        output [BIT_WIDTH-1:0]Q,
        output OVF
    );

    reg [BIT_WIDTH-1:0] count;
    reg overflow;
    always@(posedge clk or posedge load or posedge reset)begin
        if(reset) count <= 0;
        else if(load) count <= loadVal;
        else begin
            if(~|count) count <= COUNT_TOP;
            else count <= count - 1;
        end
    end
    
    always@(count)begin
        if(count == THRESHOLD) overflow <= 1;
        else overflow <= 0;
    end
    
    assign Q = count;
    assign OVF = overflow;
endmodule