data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_barrel_shift.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_barrel_shift.v:54: Cannot find include file: a23_localparams.vh\n`include "a23_localparams.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_localparams.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_localparams.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_localparams.vh.sv\n             a23_localparams.vh\n             a23_localparams.vh.v\n             a23_localparams.vh.sv\n             obj_dir/a23_localparams.vh\n             obj_dir/a23_localparams.vh.v\n             obj_dir/a23_localparams.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module lsl_struct
#( 
  parameter CTRL=5, 
  parameter WIDTH=2**CTRL
)
( 
  input   [WIDTH-1:0] in,
  input   [ CTRL-1:0] shift,
  output  [WIDTH:0] out 
);

  wire [WIDTH:0] tmp [CTRL:0];
  assign tmp[CTRL] = {in[WIDTH-1], in};
  assign out = tmp[0];
  genvar i, j;
  generate
    for (i = 0; i < CTRL; i = i + 1) begin: mux
      assign tmp[i] = shift[i] ? {tmp[i+1][WIDTH-(2**i)], tmp[i+1][WIDTH-(2**i)-1:0], {(2**i){1'b0}}} : tmp[i+1];
    end
  endgenerate
endmodule
module lsl_struct
#( 
  parameter CTRL=5, 
  parameter WIDTH=2**CTRL
)
( 
  input   [WIDTH-1:0] in,
  input   [ CTRL-1:0] shift,
  output  [WIDTH:0] out 
);


  wire [WIDTH:0] tmp [CTRL:0];
  assign tmp[CTRL] = {in[WIDTH-1], in};
  assign out = tmp[0];
  genvar i, j;
  generate
    for (i = 0; i < CTRL; i = i + 1) begin: mux
      assign tmp[i] = shift[i] ? {tmp[i+1][WIDTH-(2**i)], tmp[i+1][WIDTH-(2**i)-1:0], {(2**i){1'b0}}} : tmp[i+1];
    end
  endgenerate
endmodule