data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:19: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk; \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #15 ldsh = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #15 en = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 SI = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10 en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #30 rst = 1; \n        ^\n%Error: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:12: Cannot find file containing module: \'shiftLreg8\'\n    shiftLreg8 dut (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/shiftLreg8\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/shiftLreg8.v\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/shiftLreg8.sv\n             shiftLreg8\n             shiftLreg8.v\n             shiftLreg8.sv\n             obj_dir/shiftLreg8\n             obj_dir/shiftLreg8.v\n             obj_dir/shiftLreg8.sv\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/tb/tb_shiftLreg8.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                 : ... In instance tb_shiftreg8\n        d = $random; \n          ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_shiftreg8 (); 

    parameter N = 8; 

    reg clk, rst, en, ldsh, SI; 
    reg [N-1: 0] d; 
    wire SO; 
    wire [N-1: 0] q;


    shiftLreg8 dut (
        .clk(clk), .rst(rst), .en(en), .ldsh(ldsh), .SI(SI), 
        .d(d), .SO(SO), 
        .q(q)
    );


    always #5 clk = ~clk; 

    initial begin
        clk = 0; 
        rst = 1; 
        en = 0; 
        ldsh = 0; 
        SI = 0; 

        d = $random; 
        #10 rst = 0; 
        #10;
        ldsh = 1; 
        en = 1; 
        SI = 1; 

        #15 ldsh = 0; 
        #15 en = 0; 
        #10 SI = 0; 
        #10 en = 1;

        #30 rst = 1; 
        
        
    end
endmodule
module tb_shiftreg8 ();
 

    parameter N = 8; 

    reg clk, rst, en, ldsh, SI; 
    reg [N-1: 0] d; 
    wire SO; 
    wire [N-1: 0] q;


    shiftLreg8 dut (
        .clk(clk), .rst(rst), .en(en), .ldsh(ldsh), .SI(SI), 
        .d(d), .SO(SO), 
        .q(q)
    );


    always #5 clk = ~clk; 

    initial begin
        clk = 0; 
        rst = 1; 
        en = 0; 
        ldsh = 0; 
        SI = 0; 

        d = $random; 
        #10 rst = 0; 
        #10;
        ldsh = 1; 
        en = 1; 
        SI = 1; 

        #15 ldsh = 0; 
        #15 en = 0; 
        #10 SI = 0; 
        #10 en = 1;

        #30 rst = 1; 
        
        
    end
endmodule