data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("ALU_64bit_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test_alu_64);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:21: Unsupported or unknown PLI call: $monitor\n        $monitor("time=%0d  control=%d  a=%d  b=%d  output=%d  overflow=%d\\n", $time, control, a, b, out, OF);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #5 a=-64\'d543; b=-64\'d464;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'b0111111111111111111111111111111111111111111111111111111111111111; b = 64\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = -64\'d9223372036854775000; b=-64\'d6000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #5 control = 2\'b01; a=-64\'d7478; b=-64\'d46474;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d9223372036854775000; b = 64\'d6000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5 control = 2\'b10; a = 64\'d1092835; b = -64\'d1020;\n        ^\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:33: Unsupported or unknown PLI call: $monitor\n        $monitor("time=%0d  control=%d\\n a:      %d\\n b:      %d\\n output: %d\\n overflow=%d\\n", $time, control, a, b, out, OF);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d7890678653; b = 64\'d4238598110567;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5 control = 2\'b11; a = 64\'d1092835; b = -64\'d1020;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d7890678653; b = 64\'d4238598110567;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #5 control = 2\'b10; a = 64\'d1092835; b = -64\'d1020;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d7890678653; b = 64\'d4238598110567;\n        ^\n%Error: Exiting due to 4 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_alu_64();

reg [1:0] control;
reg signed [63:0] a;
reg signed [63:0] b;

wire signed [63:0] out;
wire OF;

ALU_64bit alu(control, a, b, out, OF);

initial 
    begin
        $dumpfile("ALU_64bit_test.vcd");
        $dumpvars(0, test_alu_64);
        control = 2'b00;
        a = 64'd256;
        b = 64'd255;
        #10

        $monitor("time=%0d  control=%d  a=%d  b=%d  output=%d  overflow=%d\n", $time, control, a, b, out, OF);

        #5 a=-64'd543; b=-64'd464;
        #5 a = 64'b0111111111111111111111111111111111111111111111111111111111111111; b = 64'd1;
        #5 a = -64'd9223372036854775000; b=-64'd6000;

        
        #5 control = 2'b01; a=-64'd7478; b=-64'd46474;
        #5 a = 64'd9223372036854775000; b = 64'd6000;

        #5 control = 2'b10; a = 64'd1092835; b = -64'd1020;

        $monitor("time=%0d  control=%d\n a:      %d\n b:      %d\n output: %d\n overflow=%d\n", $time, control, a, b, out, OF);

        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 control = 2'b11; a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 control = 2'b10; a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

    end
endmodule
module test_alu_64();


reg [1:0] control;
reg signed [63:0] a;
reg signed [63:0] b;

wire signed [63:0] out;
wire OF;

ALU_64bit alu(control, a, b, out, OF);

initial 
    begin
        $dumpfile("ALU_64bit_test.vcd");
        $dumpvars(0, test_alu_64);
        control = 2'b00;
        a = 64'd256;
        b = 64'd255;
        #10

        $monitor("time=%0d  control=%d  a=%d  b=%d  output=%d  overflow=%d\n", $time, control, a, b, out, OF);

        #5 a=-64'd543; b=-64'd464;
        #5 a = 64'b0111111111111111111111111111111111111111111111111111111111111111; b = 64'd1;
        #5 a = -64'd9223372036854775000; b=-64'd6000;

        
        #5 control = 2'b01; a=-64'd7478; b=-64'd46474;
        #5 a = 64'd9223372036854775000; b = 64'd6000;

        #5 control = 2'b10; a = 64'd1092835; b = -64'd1020;

        $monitor("time=%0d  control=%d\n a:      %d\n b:      %d\n output: %d\n overflow=%d\n", $time, control, a, b, out, OF);

        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 control = 2'b11; a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 control = 2'b10; a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

    end
endmodule