data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_mantissa_multiplication.v
data/verilator_xmls/967e4062-3e35-46b2-89bc-01b0afb14424.xml
module FMADD_Mantissa_Multiplication (Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B,Mantissa_Multiplication_input_Activation_Signal,Mantissa_Multiplication_output_Mantissa);
parameter man = 22;
parameter exp = 7;


input [man+1:0] Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B;
input Mantissa_Multiplication_input_Activation_Signal;

output [man+man+3:0] Mantissa_Multiplication_output_Mantissa;


assign Mantissa_Multiplication_output_Mantissa = (Mantissa_Multiplication_input_Activation_Signal) ? Mantissa_Multiplication_input_A * Mantissa_Multiplication_input_B: {2{{2'b00, {man{1'b0}}}}};

endmodule
module FMADD_Mantissa_Multiplication (Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B,Mantissa_Multiplication_input_Activation_Signal,Mantissa_Multiplication_output_Mantissa);

parameter man = 22;
parameter exp = 7;


input [man+1:0] Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B;
input Mantissa_Multiplication_input_Activation_Signal;

output [man+man+3:0] Mantissa_Multiplication_output_Mantissa;


assign Mantissa_Multiplication_output_Mantissa = (Mantissa_Multiplication_input_Activation_Signal) ? Mantissa_Multiplication_input_A * Mantissa_Multiplication_input_B: {2{{2'b00, {man{1'b0}}}}};

endmodule