data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:24: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.sv\n             ./const/parameters_cla.v\n             ./const/parameters_cla.v.v\n             ./const/parameters_cla.v.sv\n             obj_dir/./const/parameters_cla.v\n             obj_dir/./const/parameters_cla.v.v\n             obj_dir/./const/parameters_cla.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:55: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:76: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:106: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:125: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:146: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:172: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:200: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );
input  PIN2;
input  GIN1;
input  GIN2;
input  PHI;
output GOUT;
   assign GOUT = (GIN2 | (PIN2 & GIN1));
endmodule
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );

input  PIN2;
input  GIN1;
input  GIN2;
input  PHI;
output GOUT;
   assign GOUT = (GIN2 | (PIN2 & GIN1));
endmodule