data/full_repos/permissive/487455827/cpu/rtl/core/id.v
1: b'%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:6: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]  pc_i,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus]  pc_i,\n                        ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:7: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus]          inst_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus]    ex_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    ex_wdata_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:12: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]       ex_wd_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus]    mem_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    mem_wdata_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:17: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]       mem_wd_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:19: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           reg1_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:20: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           reg2_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:22: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]   ex_aluop_i,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg                    reg1_read_o,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg                    reg2_read_o,     \n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus]       reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:30: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]       reg1_addr_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:31: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]       reg2_addr_o,        \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:34: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]         aluop_o,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:35: Define or directive not defined: \'`AluSelBus\'\n output reg[`AluSelBus]        alusel_o,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:36: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]           reg1_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:37: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]           reg2_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:38: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]       wd_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire                   stallreq,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg       branch_flag_o,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus]    branch_target_address_o,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:44: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    branch_target_address_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:45: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    link_addr_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:47: Define or directive not defined: \'`RegBus\'\n output [`RegBus]     inst_o,\n         ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:50: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`RegBus]    current_inst_address_o\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:50: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    current_inst_address_o\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:57: Define or directive not defined: \'`RegBus\'\n  reg[`RegBus] imm;\n      ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`RegBus] imm;\n             ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:61: Define or directive not defined: \'`RegBus\'\n  wire[`RegBus] temp_sum;\n       ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`RegBus] temp_sum;\n              ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:62: Define or directive not defined: \'`RegBus\'\n  wire[`RegBus] reg2_o_mux;\n       ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`RegBus] reg2_o_mux;\n              ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:74: syntax error, unexpected assign\n  assign excepttype_o = {19\'b0,excepttype_is_mret,2\'b0,\n  ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:81: Define or directive not defined: \'`EXE_LB_OP\'\n  assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:82: Define or directive not defined: \'`EXE_LBU_OP\'\n          (ex_aluop_i == `EXE_LBU_OP) ||\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:83: Define or directive not defined: \'`EXE_LH_OP\'\n          (ex_aluop_i == `EXE_LH_OP) ||\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:84: Define or directive not defined: \'`EXE_LHU_OP\'\n          (ex_aluop_i == `EXE_LHU_OP) ||\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:85: Define or directive not defined: \'`EXE_LW_OP\'\n          (ex_aluop_i == `EXE_LW_OP) ||\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:86: Define or directive not defined: \'`EXE_LWU_OP\'\n          (ex_aluop_i == `EXE_LWU_OP)) ? 1\'b1 : 1\'b0;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:100: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:101: Define or directive not defined: \'`EXE_NOP_OP\'\n   aluop_o = `EXE_NOP_OP;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:102: Define or directive not defined: \'`EXE_RES_NOP\'\n   alusel_o = `EXE_RES_NOP;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:103: Define or directive not defined: \'`NOPRegAddr\'\n   wd_o = `NOPRegAddr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:104: Define or directive not defined: \'`WriteDisable\'\n   wreg_o = `WriteDisable;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/id.v:105: Define or directive not defined: \'`InstInvalid\'\n   instvalid = `InstInvalid;\n               ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id(

	input wire							rst,
	input wire[`InstAddrBus]		pc_i,
	input wire[`InstBus]          inst_i,
	

	input wire							ex_wreg_i,
	input wire[`RegBus]				ex_wdata_i,
	input wire[`RegAddrBus]       ex_wd_i,
	

	input wire							mem_wreg_i,
	input wire[`RegBus]				mem_wdata_i,
	input wire[`RegAddrBus]       mem_wd_i,

	input wire[`RegBus]           reg1_data_i,
	input wire[`RegBus]           reg2_data_i,
	
	input wire[`AluOpBus]			ex_aluop_i,
	

	input wire[1:0]					curr_mode,


	output reg                    reg1_read_o,
	output reg                    reg2_read_o,     
	output reg[`RegAddrBus]       reg1_addr_o,
	output reg[`RegAddrBus]       reg2_addr_o, 	      
	

	output reg[`AluOpBus]         aluop_o,
	output reg[`AluSelBus]        alusel_o,
	output reg[`RegBus]           reg1_o,
	output reg[`RegBus]           reg2_o,
	output reg[`RegAddrBus]       wd_o,
	output reg                    wreg_o,

	output wire                   stallreq,

	output reg							branch_flag_o,
	output reg[`RegBus]				branch_target_address_o,
	output reg[`RegBus]				link_addr_o,

	output [`RegBus]					inst_o,
	
	output wire[31:0]					excepttype_o,
	output wire[`RegBus]				current_inst_address_o
);

  wire[6:0] op = inst_i[6:0];
  wire[2:0] op2 = inst_i[14:12];
  wire[6:0] op3 = inst_i[31:25];
  wire[5:0] op3_i = inst_i[31:26];
  reg[`RegBus]	imm;
  reg[1:0] get_current_pc;
  reg instvalid;
  wire reg1_lt_reg2;
  wire[`RegBus] temp_sum;
  wire[`RegBus] reg2_o_mux;
  

  reg stallreq_for_reg1_loadrelate;
  reg stallreq_for_reg2_loadrelate;
  wire pre_inst_is_load;
  
  reg excepttype_is_ecall;
  reg excepttype_is_mret;
  


  assign excepttype_o = {19'b0,excepttype_is_mret,2'b0,
  												instvalid, excepttype_is_ecall, 8'b0};
												
	assign current_inst_address_o = pc_i;
  
  assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
  
  assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
										(ex_aluop_i == `EXE_LBU_OP) ||
										(ex_aluop_i == `EXE_LH_OP) ||
										(ex_aluop_i == `EXE_LHU_OP) ||
										(ex_aluop_i == `EXE_LW_OP) ||
										(ex_aluop_i == `EXE_LWU_OP)) ? 1'b1 : 1'b0;
 


 
  assign inst_o = inst_i;
  
  assign reg2_o_mux = (~reg2_o) + 1;
  assign temp_sum = reg1_o + reg2_o_mux;
  assign reg1_lt_reg2 = ((reg1_o[31] && !reg2_o[31]) || 
														(!reg1_o[31] && !reg2_o[31] && temp_sum[31])||
																(reg1_o[31] && reg2_o[31] && temp_sum[31]));
 
	always @ (*) begin	
		if (rst == `RstEnable) begin
			aluop_o = `EXE_NOP_OP;
			alusel_o = `EXE_RES_NOP;
			wd_o = `NOPRegAddr;
			wreg_o = `WriteDisable;
			instvalid = `InstInvalid;
			reg1_read_o = 1'b0;
			reg2_read_o = 1'b0;
			reg1_addr_o = `NOPRegAddr;
			reg2_addr_o = `NOPRegAddr;
			imm = 32'h0;
			link_addr_o = `ZeroWord;
			branch_target_address_o = `ZeroWord;
			branch_flag_o = `NotBranch;


			get_current_pc = 2'b00;
			
			excepttype_is_ecall = `False_v;
			excepttype_is_mret = `False_v;
	  end else begin
			aluop_o = `EXE_NOP_OP;
			alusel_o = `EXE_RES_NOP;
			wd_o = inst_i[11:7];
			wreg_o = `WriteDisable;
			instvalid = `InstValid;  
			reg1_read_o = 1'b0;
			reg2_read_o = 1'b0;
			reg1_addr_o = inst_i[19:15];
			reg2_addr_o = inst_i[24:20];
			imm = `ZeroWord;
			link_addr_o = `ZeroWord;
			branch_target_address_o = `ZeroWord;
			branch_flag_o = `NotBranch;


			get_current_pc = 2'b00;
		  case (op)
			 `EXE_I_INST:	begin
					case(op2) 
						   `EXE_ORI:			begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_OR_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
							`EXE_ANDI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_AND_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];	  	
								instvalid = `InstValid;
							end
							`EXE_XORI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_XOR_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];			  	
								instvalid = `InstValid;
							end
							`EXE_SLLI:		begin
								if(op3_i == 6'b000000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SLL_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];	
									instvalid = `InstValid;
								end
							end
							`EXE_SRLI_SRAI:		begin
								if(op3_i == 6'b000000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SRL_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];
									instvalid = `InstValid;
								end
								if(op3_i == 6'b010000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SRA_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];
									instvalid = `InstValid;
								end
							end
							`EXE_ADDI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_ADDI_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							`EXE_SLTI:	begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLT_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							`EXE_SLTIU:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLTU_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							default:		begin
							end
					endcase
				end
				`EXE_R_INST:		begin
					case(op2)
						`EXE_AND_REMU:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_AND_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_REMU_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_OR_REM:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_OR_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_REM_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_XOR_DIV:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_XOR_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_DIV_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_SLL_MULH:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLL_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULH_OP;
								alusel_o = `EXE_RES_MUL;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_SRL_SRA_DIVU:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SRL_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0100000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SRA_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;	
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_DIVU_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_ADD_SUB_MUL:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_ADD_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0100000)begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SUB_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MUL_OP;
								alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_SLT_MULHSU:	begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLT_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULHSU_OP;
		  						alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
						end
						`EXE_SLTU_MULHU:	begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLTU_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULHU_OP;
		  						alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
						end
						default:		begin
						end
					endcase
				end
				`EXE_B_INST:	begin
					case(op2)
						`EXE_BEQ: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BEQ_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o == reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BNE: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BNE_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o != reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BLT: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BLT_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;




							if(reg1_lt_reg2 == 1'b1) begin
								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BLTU: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BLTU_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o < reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BGE: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BGE_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;




							if(reg1_lt_reg2 == 1'b0) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BGEU: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BGEU_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if((reg1_o > reg2_o) || (reg1_o == reg2_o)) begin
								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);

								branch_flag_o = `Branch;
							end
						end
						default:		begin
						end
					endcase
				end
				`EXE_L_INST: 		begin
					case(op2)
						`EXE_LB:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LB_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;	
						end
						`EXE_LH:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LH_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LBU:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LBU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LHU:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LHU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LW:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LW_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LWU:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LWU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LD:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LD_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						default:		begin
						end
					endcase
				end
				`EXE_S_INST:		begin
					case(op2)
						`EXE_SB:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SB_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SH:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SH_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SW:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SW_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SD: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SD_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
					endcase
				end
				`EXE_LUI:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_OR_OP;
					alusel_o = `EXE_RES_LOGIC;
					reg1_read_o = 1'b1;
					reg1_addr_o = 5'b00000;
					reg2_read_o = 1'b0;

					imm = (inst_i >> 12)<<12;
					wd_o = inst_i[11:7];  	
					instvalid = `InstValid;	
				end
				`EXE_AUIPC_INST:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_ADDI_OP;
					alusel_o = `EXE_RES_ARITHMETIC;
					reg1_read_o = 1'b0;
					reg2_read_o = 1'b0;
					get_current_pc = 2'b01;
					imm = ({{12{inst_i[31]}}, inst_i[31:12]} << 12);
					wd_o = inst_i[11:7];		  	
					instvalid = `InstValid;
				end
				`EXE_JAL:		begin
					 wreg_o = `WriteEnable;
					 aluop_o = `EXE_JAL_OP;
					 alusel_o = `EXE_RES_JUMP_BRANCH;
					 reg1_read_o = 1'b0;
					 reg2_read_o = 1'b0;
					 wd_o = 5'b00001;
					 link_addr_o = pc_i + 4;

					 branch_target_address_o = {{11{inst_i[31]}},{inst_i[31], inst_i[19:12], inst_i[20], inst_i[30:21]} << 1} + pc_i;
					 branch_flag_o = `Branch;		  	
					 instvalid = `InstValid;
				end
				`EXE_JALR:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_JALR_OP;
					alusel_o = `EXE_RES_JUMP_BRANCH;
					reg1_read_o = 1'b1;
					reg2_read_o = 1'b0;
					wd_o = 5'b00000;
					link_addr_o = pc_i + 4;


					branch_target_address_o = (({{20{inst_i[31]}},inst_i[31:20]} >> 1) << 1) + reg1_data_i;
					branch_flag_o = `Branch;
					instvalid = `InstValid;	
				end
				`EXE_CSR_ENV_INST:		begin
					case(op2)
						`EXE_CSRRW:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRW_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRWI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRW_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRS:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRS_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRSI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRS_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRC:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRC_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRCI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRC_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
							`EXE_ECALL_EBREAK_MRET:		begin
								case(inst_i[31:20])
									12'b001100000010:		begin
										wreg_o = `WriteDisable;
										aluop_o = `EXE_MRET_OP;
										alusel_o = `EXE_RES_NOP;
										reg1_read_o = 1'b0;
										reg2_read_o = 1'b0;
										instvalid = `InstValid;
										excepttype_is_mret = `True_v;
									end
									12'b000000000000:		begin
										wreg_o = `WriteDisable;
										aluop_o = `EXE_ECALL_OP;
										alusel_o = `EXE_RES_NOP;
										reg1_read_o = 1'b0;
										reg2_read_o = 1'b0;
										instvalid = `InstValid;
										excepttype_is_ecall = `True_v;
									end
									12'b000000000001:		begin
									end
									default:		begin
									end
								endcase
							end
					endcase
				end
		    default:			begin

		    end
		  endcase
		end
		
		if(inst_i != 32'h00000073) begin
			excepttype_is_ecall = `False_v;
		end
		if(inst_i != 32'h30200073) begin
			excepttype_is_mret = `False_v;
		end
		if((inst_i[6:0] == 7'b1110011) && (inst_i[14:12] != 3'b000) && (curr_mode != `m_mode)) begin
			instvalid = `InstInvalid;
		end else begin
			instvalid = `InstValid;
		end
	end
	
	
	

	always @ (*) begin
		stallreq_for_reg1_loadrelate = `NoStop;
		if(rst == `RstEnable) begin
			reg1_o = `ZeroWord;
		end else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o 
								&& reg1_read_o == 1'b1 ) begin
		  stallreq_for_reg1_loadrelate = `Stop;
		end else if(reg1_read_o == 1'b0) begin
			if(get_current_pc != 2'b01) begin
					reg1_o = imm;
			end else if(get_current_pc == 2'b01) begin
				reg1_o = pc_i;
			end
		end else if(reg1_read_o == 1'b1) begin
			if((ex_wreg_i == 1'b1) && (ex_wd_i == reg1_addr_o)) begin
				reg1_o = ex_wdata_i;
			end else if((mem_wreg_i == 1'b1)&& (mem_wd_i == reg1_addr_o)) begin
				reg1_o = mem_wdata_i;
			end else begin
				reg1_o = reg1_data_i;
			end
		end else begin
	    reg1_o = `ZeroWord;
	  end
	end
	
	always @ (*) begin
		stallreq_for_reg2_loadrelate = `NoStop;
		if(rst == `RstEnable) begin
			reg2_o = `ZeroWord;
		end else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o 
								&& reg2_read_o == 1'b1 ) begin
		  stallreq_for_reg2_loadrelate = `Stop;
		end else if(reg2_read_o == 1'b0) begin
			if(get_current_pc != 2'b10) begin
					reg2_o = imm;
			end else if(get_current_pc == 2'b10) begin
				reg2_o = pc_i;
			end
		end else if(reg2_read_o == 1'b1) begin
			if((ex_wreg_i == 1'b1) && (ex_wd_i == reg2_addr_o)) begin
				reg2_o = ex_wdata_i;
			end else if((mem_wreg_i == 1'b1)&& (mem_wd_i == reg2_addr_o)) begin
				reg2_o = mem_wdata_i;
			end
			else begin
				reg2_o = reg2_data_i;
			end
		end else begin
	    reg2_o = `ZeroWord;
	  end
	end
	


















endmodule
module id(

	input wire							rst,
	input wire[`InstAddrBus]		pc_i,
	input wire[`InstBus]          inst_i,
	

	input wire							ex_wreg_i,
	input wire[`RegBus]				ex_wdata_i,
	input wire[`RegAddrBus]       ex_wd_i,
	

	input wire							mem_wreg_i,
	input wire[`RegBus]				mem_wdata_i,
	input wire[`RegAddrBus]       mem_wd_i,

	input wire[`RegBus]           reg1_data_i,
	input wire[`RegBus]           reg2_data_i,
	
	input wire[`AluOpBus]			ex_aluop_i,
	

	input wire[1:0]					curr_mode,


	output reg                    reg1_read_o,
	output reg                    reg2_read_o,     
	output reg[`RegAddrBus]       reg1_addr_o,
	output reg[`RegAddrBus]       reg2_addr_o, 	      
	

	output reg[`AluOpBus]         aluop_o,
	output reg[`AluSelBus]        alusel_o,
	output reg[`RegBus]           reg1_o,
	output reg[`RegBus]           reg2_o,
	output reg[`RegAddrBus]       wd_o,
	output reg                    wreg_o,

	output wire                   stallreq,

	output reg							branch_flag_o,
	output reg[`RegBus]				branch_target_address_o,
	output reg[`RegBus]				link_addr_o,

	output [`RegBus]					inst_o,
	
	output wire[31:0]					excepttype_o,
	output wire[`RegBus]				current_inst_address_o
);


  wire[6:0] op = inst_i[6:0];
  wire[2:0] op2 = inst_i[14:12];
  wire[6:0] op3 = inst_i[31:25];
  wire[5:0] op3_i = inst_i[31:26];
  reg[`RegBus]	imm;
  reg[1:0] get_current_pc;
  reg instvalid;
  wire reg1_lt_reg2;
  wire[`RegBus] temp_sum;
  wire[`RegBus] reg2_o_mux;
  

  reg stallreq_for_reg1_loadrelate;
  reg stallreq_for_reg2_loadrelate;
  wire pre_inst_is_load;
  
  reg excepttype_is_ecall;
  reg excepttype_is_mret;
  


  assign excepttype_o = {19'b0,excepttype_is_mret,2'b0,
  												instvalid, excepttype_is_ecall, 8'b0};
												
	assign current_inst_address_o = pc_i;
  
  assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
  
  assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
										(ex_aluop_i == `EXE_LBU_OP) ||
										(ex_aluop_i == `EXE_LH_OP) ||
										(ex_aluop_i == `EXE_LHU_OP) ||
										(ex_aluop_i == `EXE_LW_OP) ||
										(ex_aluop_i == `EXE_LWU_OP)) ? 1'b1 : 1'b0;
 


 
  assign inst_o = inst_i;
  
  assign reg2_o_mux = (~reg2_o) + 1;
  assign temp_sum = reg1_o + reg2_o_mux;
  assign reg1_lt_reg2 = ((reg1_o[31] && !reg2_o[31]) || 
														(!reg1_o[31] && !reg2_o[31] && temp_sum[31])||
																(reg1_o[31] && reg2_o[31] && temp_sum[31]));
 
	always @ (*) begin	
		if (rst == `RstEnable) begin
			aluop_o = `EXE_NOP_OP;
			alusel_o = `EXE_RES_NOP;
			wd_o = `NOPRegAddr;
			wreg_o = `WriteDisable;
			instvalid = `InstInvalid;
			reg1_read_o = 1'b0;
			reg2_read_o = 1'b0;
			reg1_addr_o = `NOPRegAddr;
			reg2_addr_o = `NOPRegAddr;
			imm = 32'h0;
			link_addr_o = `ZeroWord;
			branch_target_address_o = `ZeroWord;
			branch_flag_o = `NotBranch;


			get_current_pc = 2'b00;
			
			excepttype_is_ecall = `False_v;
			excepttype_is_mret = `False_v;
	  end else begin
			aluop_o = `EXE_NOP_OP;
			alusel_o = `EXE_RES_NOP;
			wd_o = inst_i[11:7];
			wreg_o = `WriteDisable;
			instvalid = `InstValid;  
			reg1_read_o = 1'b0;
			reg2_read_o = 1'b0;
			reg1_addr_o = inst_i[19:15];
			reg2_addr_o = inst_i[24:20];
			imm = `ZeroWord;
			link_addr_o = `ZeroWord;
			branch_target_address_o = `ZeroWord;
			branch_flag_o = `NotBranch;


			get_current_pc = 2'b00;
		  case (op)
			 `EXE_I_INST:	begin
					case(op2) 
						   `EXE_ORI:			begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_OR_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
							`EXE_ANDI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_AND_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];	  	
								instvalid = `InstValid;
							end
							`EXE_XORI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_XOR_OP;
								alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}},inst_i[31:20]};
								wd_o = inst_i[11:7];			  	
								instvalid = `InstValid;
							end
							`EXE_SLLI:		begin
								if(op3_i == 6'b000000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SLL_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];	
									instvalid = `InstValid;
								end
							end
							`EXE_SRLI_SRAI:		begin
								if(op3_i == 6'b000000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SRL_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];
									instvalid = `InstValid;
								end
								if(op3_i == 6'b010000 & inst_i[25] == 0) begin
									wreg_o = `WriteEnable;
									aluop_o = `EXE_SRA_OP;
									alusel_o = `EXE_RES_SHIFT;
									reg1_read_o = 1'b1;	reg2_read_o = 1'b0;	  	
									imm[5:0] = inst_i[25:20];
									wd_o = inst_i[11:7];
									instvalid = `InstValid;
								end
							end
							`EXE_ADDI:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_ADDI_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							`EXE_SLTI:	begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLT_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							`EXE_SLTIU:		begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLTU_OP;
								alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b0;	  	
								imm = {{20{inst_i[31]}}, inst_i[31:20]};
								wd_o = inst_i[11:7];		  	
								instvalid = `InstValid;
							end
							default:		begin
							end
					endcase
				end
				`EXE_R_INST:		begin
					case(op2)
						`EXE_AND_REMU:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_AND_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_REMU_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_OR_REM:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_OR_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_REM_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_XOR_DIV:		begin
							if(op3 == 7'b0000000) begin
		    					wreg_o = `WriteEnable;
								aluop_o = `EXE_XOR_OP;
		  						alusel_o = `EXE_RES_LOGIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_DIV_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_SLL_MULH:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLL_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULH_OP;
								alusel_o = `EXE_RES_MUL;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_SRL_SRA_DIVU:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SRL_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0100000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SRA_OP;
		  						alusel_o = `EXE_RES_SHIFT;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;	
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_DIVU_OP;
								alusel_o = `EXE_RES_DIV;
		  						reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;	
							end
						end
						`EXE_ADD_SUB_MUL:		begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_ADD_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0100000)begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SUB_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MUL_OP;
								alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
								instvalid = `InstValid;
							end
						end
						`EXE_SLT_MULHSU:	begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLT_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULHSU_OP;
		  						alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
						end
						`EXE_SLTU_MULHU:	begin
							if(op3 == 7'b0000000) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_SLTU_OP;
		  						alusel_o = `EXE_RES_ARITHMETIC;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
							if(op3 == 7'b0000001) begin
								wreg_o = `WriteEnable;
								aluop_o = `EXE_MULHU_OP;
		  						alusel_o = `EXE_RES_MUL;
								reg1_read_o = 1'b1;
								reg2_read_o = 1'b1;
								wd_o = inst_i[11:7];
		  						instvalid = `InstValid;
							end
						end
						default:		begin
						end
					endcase
				end
				`EXE_B_INST:	begin
					case(op2)
						`EXE_BEQ: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BEQ_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o == reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BNE: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BNE_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o != reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BLT: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BLT_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;




							if(reg1_lt_reg2 == 1'b1) begin
								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BLTU: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BLTU_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if(reg1_o < reg2_o) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BGE: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BGE_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;




							if(reg1_lt_reg2 == 1'b0) begin

								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);
								branch_flag_o = `Branch;
							end
						end
						`EXE_BGEU: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_BGEU_OP;
							alusel_o = `EXE_RES_JUMP_BRANCH;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;
							instvalid = `InstValid;	
							if((reg1_o > reg2_o) || (reg1_o == reg2_o)) begin
								branch_target_address_o = pc_i + ({{21{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8]} << 1);

								branch_flag_o = `Branch;
							end
						end
						default:		begin
						end
					endcase
				end
				`EXE_L_INST: 		begin
					case(op2)
						`EXE_LB:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LB_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;	
						end
						`EXE_LH:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LH_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LBU:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LBU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LHU:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LHU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LW:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LW_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LWU:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LWU_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_LD:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_LD_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						default:		begin
						end
					endcase
				end
				`EXE_S_INST:		begin
					case(op2)
						`EXE_SB:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SB_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SH:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SH_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SW:		begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SW_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
						`EXE_SD: 	begin
							wreg_o = `WriteDisable;
							aluop_o = `EXE_SD_OP;
							alusel_o = `EXE_RES_LOAD_STORE;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b1;	  	
							wd_o = inst_i[11:7];
							instvalid = `InstValid;
						end
					endcase
				end
				`EXE_LUI:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_OR_OP;
					alusel_o = `EXE_RES_LOGIC;
					reg1_read_o = 1'b1;
					reg1_addr_o = 5'b00000;
					reg2_read_o = 1'b0;

					imm = (inst_i >> 12)<<12;
					wd_o = inst_i[11:7];  	
					instvalid = `InstValid;	
				end
				`EXE_AUIPC_INST:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_ADDI_OP;
					alusel_o = `EXE_RES_ARITHMETIC;
					reg1_read_o = 1'b0;
					reg2_read_o = 1'b0;
					get_current_pc = 2'b01;
					imm = ({{12{inst_i[31]}}, inst_i[31:12]} << 12);
					wd_o = inst_i[11:7];		  	
					instvalid = `InstValid;
				end
				`EXE_JAL:		begin
					 wreg_o = `WriteEnable;
					 aluop_o = `EXE_JAL_OP;
					 alusel_o = `EXE_RES_JUMP_BRANCH;
					 reg1_read_o = 1'b0;
					 reg2_read_o = 1'b0;
					 wd_o = 5'b00001;
					 link_addr_o = pc_i + 4;

					 branch_target_address_o = {{11{inst_i[31]}},{inst_i[31], inst_i[19:12], inst_i[20], inst_i[30:21]} << 1} + pc_i;
					 branch_flag_o = `Branch;		  	
					 instvalid = `InstValid;
				end
				`EXE_JALR:		begin
					wreg_o = `WriteEnable;
					aluop_o = `EXE_JALR_OP;
					alusel_o = `EXE_RES_JUMP_BRANCH;
					reg1_read_o = 1'b1;
					reg2_read_o = 1'b0;
					wd_o = 5'b00000;
					link_addr_o = pc_i + 4;


					branch_target_address_o = (({{20{inst_i[31]}},inst_i[31:20]} >> 1) << 1) + reg1_data_i;
					branch_flag_o = `Branch;
					instvalid = `InstValid;	
				end
				`EXE_CSR_ENV_INST:		begin
					case(op2)
						`EXE_CSRRW:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRW_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRWI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRW_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRS:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRS_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRSI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRS_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRC:		begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRC_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b1;
							reg2_read_o = 1'b0;
							wd_o = inst_i[11:7];

						end
						`EXE_CSRRCI:	begin
							wreg_o = `WriteEnable;
							aluop_o = `EXE_CSRRC_OP;
							alusel_o = `EXE_RES_LOGIC;
							reg1_read_o = 1'b0;
							reg2_read_o = 1'b0;
							imm = {27'b0,inst_i[19:15]};
							wd_o = inst_i[11:7];

						end
							`EXE_ECALL_EBREAK_MRET:		begin
								case(inst_i[31:20])
									12'b001100000010:		begin
										wreg_o = `WriteDisable;
										aluop_o = `EXE_MRET_OP;
										alusel_o = `EXE_RES_NOP;
										reg1_read_o = 1'b0;
										reg2_read_o = 1'b0;
										instvalid = `InstValid;
										excepttype_is_mret = `True_v;
									end
									12'b000000000000:		begin
										wreg_o = `WriteDisable;
										aluop_o = `EXE_ECALL_OP;
										alusel_o = `EXE_RES_NOP;
										reg1_read_o = 1'b0;
										reg2_read_o = 1'b0;
										instvalid = `InstValid;
										excepttype_is_ecall = `True_v;
									end
									12'b000000000001:		begin
									end
									default:		begin
									end
								endcase
							end
					endcase
				end
		    default:			begin

		    end
		  endcase
		end
		
		if(inst_i != 32'h00000073) begin
			excepttype_is_ecall = `False_v;
		end
		if(inst_i != 32'h30200073) begin
			excepttype_is_mret = `False_v;
		end
		if((inst_i[6:0] == 7'b1110011) && (inst_i[14:12] != 3'b000) && (curr_mode != `m_mode)) begin
			instvalid = `InstInvalid;
		end else begin
			instvalid = `InstValid;
		end
	end
	
	
	

	always @ (*) begin
		stallreq_for_reg1_loadrelate = `NoStop;
		if(rst == `RstEnable) begin
			reg1_o = `ZeroWord;
		end else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o 
								&& reg1_read_o == 1'b1 ) begin
		  stallreq_for_reg1_loadrelate = `Stop;
		end else if(reg1_read_o == 1'b0) begin
			if(get_current_pc != 2'b01) begin
					reg1_o = imm;
			end else if(get_current_pc == 2'b01) begin
				reg1_o = pc_i;
			end
		end else if(reg1_read_o == 1'b1) begin
			if((ex_wreg_i == 1'b1) && (ex_wd_i == reg1_addr_o)) begin
				reg1_o = ex_wdata_i;
			end else if((mem_wreg_i == 1'b1)&& (mem_wd_i == reg1_addr_o)) begin
				reg1_o = mem_wdata_i;
			end else begin
				reg1_o = reg1_data_i;
			end
		end else begin
	    reg1_o = `ZeroWord;
	  end
	end
	
	always @ (*) begin
		stallreq_for_reg2_loadrelate = `NoStop;
		if(rst == `RstEnable) begin
			reg2_o = `ZeroWord;
		end else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o 
								&& reg2_read_o == 1'b1 ) begin
		  stallreq_for_reg2_loadrelate = `Stop;
		end else if(reg2_read_o == 1'b0) begin
			if(get_current_pc != 2'b10) begin
					reg2_o = imm;
			end else if(get_current_pc == 2'b10) begin
				reg2_o = pc_i;
			end
		end else if(reg2_read_o == 1'b1) begin
			if((ex_wreg_i == 1'b1) && (ex_wd_i == reg2_addr_o)) begin
				reg2_o = ex_wdata_i;
			end else if((mem_wreg_i == 1'b1)&& (mem_wd_i == reg2_addr_o)) begin
				reg2_o = mem_wdata_i;
			end
			else begin
				reg2_o = reg2_data_i;
			end
		end else begin
	    reg2_o = `ZeroWord;
	  end
	end
	


















endmodule