data/full_repos/permissive/446997925/hw3/or.v
data/verilator_xmls/91d6b0c7-80e9-4fd8-b698-4e241996a499.xml
module or_32(out, a, b);
input [31:0] a, b;
output [31:0] out;

or_16 f(out[15:0], a[15:0], b[15:0]),
          s(out[31:16], a[31:16], b[31:16]);
endmodule
module or_32(out, a, b);

input [31:0] a, b;
output [31:0] out;

or_16 f(out[15:0], a[15:0], b[15:0]),
          s(out[31:16], a[31:16], b[31:16]);
endmodule