data/full_repos/permissive/458737381/src/verilog-parser/tests/sctag_cpx_rptr_0.v
data/verilator_xmls/9d33a2d3-0006-4f0b-ade5-33e83c785f5b.xml
module sctag_cpx_rptr_0 (

   sig_buf, 

   sig
   );



output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule
module sctag_cpx_rptr_0 (

   sig_buf, 

   sig
   );




output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule