data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_ssiclk.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_ssiclk.v:26: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_clsp_clkgn_ssiclk(

ctu_jbi_ssiclk, 

io_pwron_rst_l, jbus_clk, ssiclk_enable
);

input io_pwron_rst_l;
input jbus_clk;
input ssiclk_enable;
output ctu_jbi_ssiclk;


   wire jbus_clk_stage1_nxt;
   wire jbus_clk_stage1;
   wire ctu_jbi_ssiclk;


      assign  jbus_clk_stage1_nxt =  jbus_clk_stage1 | ctu_jbi_ssiclk?
                                     ~ctu_jbi_ssiclk : (~ctu_jbi_ssiclk & ssiclk_enable);

      dffrl_async_ns u_ctu_jbi_ssiclk_d1 (
                      .din (jbus_clk_stage1_nxt),
                      .clk (jbus_clk),
                      .rst_l(io_pwron_rst_l),
                      .q(jbus_clk_stage1));
      dffrl_async_ns u_ctu_jbi_ssiclk_d2 (
                      .din (jbus_clk_stage1),
                      .clk (jbus_clk),
                      .rst_l(io_pwron_rst_l),
                      .q(ctu_jbi_ssiclk));


endmodule
module ctu_clsp_clkgn_ssiclk(

ctu_jbi_ssiclk, 

io_pwron_rst_l, jbus_clk, ssiclk_enable
);


input io_pwron_rst_l;
input jbus_clk;
input ssiclk_enable;
output ctu_jbi_ssiclk;


   wire jbus_clk_stage1_nxt;
   wire jbus_clk_stage1;
   wire ctu_jbi_ssiclk;


      assign  jbus_clk_stage1_nxt =  jbus_clk_stage1 | ctu_jbi_ssiclk?
                                     ~ctu_jbi_ssiclk : (~ctu_jbi_ssiclk & ssiclk_enable);

      dffrl_async_ns u_ctu_jbi_ssiclk_d1 (
                      .din (jbus_clk_stage1_nxt),
                      .clk (jbus_clk),
                      .rst_l(io_pwron_rst_l),
                      .q(jbus_clk_stage1));
      dffrl_async_ns u_ctu_jbi_ssiclk_d2 (
                      .din (jbus_clk_stage1),
                      .clk (jbus_clk),
                      .rst_l(io_pwron_rst_l),
                      .q(ctu_jbi_ssiclk));


endmodule