data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:39: syntax error, unexpected ',', expecting IDENTIFIER or do or final\nmodule memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);\n                                           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:45: syntax error, unexpected output\noutput y3, y4;\n^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:52: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
    (* gentb_constant=0 *) wire rst;
    reg [7:0] test [0:7];
    integer i;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (i=0; i<8; i=i+1)
                test[i] <= 0;
        end else begin
            test[0][2] <= din[1];
            test[0][5] <= test[0][2];
            test[idx][3] <= din[idx];
            test[idx][6] <= test[idx][2];
            test[idx][idx] <= !test[idx][idx];
        end
    end
    assign dout = test[idx];
endmodule
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);

    (* gentb_constant=0 *) wire rst;
    reg [7:0] test [0:7];
    integer i;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            for (i=0; i<8; i=i+1)
                test[i] <= 0;
        end else begin
            test[0][2] <= din[1];
            test[0][5] <= test[0][2];
            test[idx][3] <= din[idx];
            test[idx][6] <= test[idx][2];
            test[idx][idx] <= !test[idx][idx];
        end
    end
    assign dout = test[idx];
endmodule