data/full_repos/permissive/519183085/src/apf/io_pad_controller.v
1: b'%Error: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:65: Cannot find file containing module: \'synch_3\'\nsynch_3 s00(reset_n, reset_n_s, clk);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519183085/src/apf,data/full_repos/permissive/519183085/synch_3\n             data/full_repos/permissive/519183085/src/apf,data/full_repos/permissive/519183085/synch_3.v\n             data/full_repos/permissive/519183085/src/apf,data/full_repos/permissive/519183085/synch_3.sv\n             synch_3\n             synch_3.v\n             synch_3.sv\n             obj_dir/synch_3\n             obj_dir/synch_3.v\n             obj_dir/synch_3.sv\n%Error: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:68: Cannot find file containing module: \'synch_3\'\nsynch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:143: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            0: cont1_key <= rx_word;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:145: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            2: cont1_trig <= rx_word;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:147: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            3: cont2_key <= rx_word;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:149: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            5: cont2_trig <= rx_word;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:151: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            6: cont3_key <= rx_word;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:153: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            8: cont3_trig <= rx_word;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:155: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n            9: cont4_key <= rx_word;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/apf/io_pad_controller.v:158: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rx_word\' generates 32 bits.\n                                                                                    : ... In instance io_pad_controller\n                cont4_trig <= rx_word;\n                           ^~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module io_pad_controller (

input   wire            clk,
input   wire            reset_n,

inout   reg             pad_1wire,

output  reg     [15:0]  cont1_key,
output  reg     [15:0]  cont2_key,
output  reg     [15:0]  cont3_key,
output  reg     [15:0]  cont4_key,
output  reg     [31:0]  cont1_joy,
output  reg     [31:0]  cont2_joy,
output  reg     [31:0]  cont3_joy,
output  reg     [31:0]  cont4_joy,
output  reg     [15:0]  cont1_trig,
output  reg     [15:0]  cont2_trig,
output  reg     [15:0]  cont3_trig,
output  reg     [15:0]  cont4_trig,

output  reg             rx_timed_out
);

    wire        reset_n_s;
synch_3 s00(reset_n, reset_n_s, clk);

    wire        pad_1wire_s, pad_1wire_r, pad_1wire_f;
synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f);






    reg [20:0]  rx_timeout;
    
    reg [15:0]  auto_poll_cnt;
    reg         auto_poll_queue;
    
    reg [18:0]  heartbeat_cnt;
    reg         heartbeat_queue;
    

    localparam  ST_RESET        = 'd0;
    localparam  ST_IDLE         = 'd1;
    localparam  ST_RX_BUTTON_1  = 'd2;
    localparam  ST_RX_BUTTON_2  = 'd3;
    localparam  ST_TX_SCALER    = 'd4;
    localparam  ST_END_TX       = 'd5;
    
    reg [3:0]   state;
    reg [3:0]   cnt;
    
always @(posedge clk) begin
    tx_word_start <= 0;
    
    auto_poll_cnt <= auto_poll_cnt + 1'b1;
    heartbeat_cnt <= heartbeat_cnt + 1'b1;
    

    rx_timeout <= rx_timeout + 1'b1;
    
    case(state)
    ST_RESET: begin
        reset_tr_n <= 0;
        rx_timed_out <= 0;
        
        if(&rx_timeout[19:0]) begin
            state <= ST_IDLE;
        end
    end
    ST_IDLE: begin

        reset_tr_n <= 1;
        rx_timeout <= 0;
        cnt <= 0;
        if(auto_poll_queue) begin
            auto_poll_queue <= 0;
            
            tx_word_start <= 1;
            tx_word <= 32'h4A10000C;
            
            state <= ST_RX_BUTTON_1;
        end else if(heartbeat_queue) begin
            heartbeat_queue <= 0;
        
            tx_word_start <= 1;
            tx_word <= 32'h4AFE0000;
        
            state <= ST_END_TX;
        end 
    end

    ST_RX_BUTTON_1: begin
        if(tx_word_done) begin
            state <= ST_RX_BUTTON_2;
        end 
    end
    ST_RX_BUTTON_2: begin
        if(rx_word_done) begin
            cnt <= cnt + 1'b1;
            case(cnt)
            0: cont1_key <= rx_word;
            1: cont1_joy <= rx_word;
            2: cont1_trig <= rx_word;
            
            3: cont2_key <= rx_word;
            4: cont2_joy <= rx_word;
            5: cont2_trig <= rx_word;
            
            6: cont3_key <= rx_word;
            7: cont3_joy <= rx_word;
            8: cont3_trig <= rx_word;
            
            9: cont4_key <= rx_word;
            10: cont4_joy <= rx_word;
            11: begin
                cont4_trig <= rx_word;
                state <= ST_IDLE;   
            end
            endcase
        end 
    end

    ST_END_TX: begin

        if(tx_word_done) begin
            state <= ST_IDLE;   
        end
    end
    endcase
    
    
    if(&auto_poll_cnt) begin
        auto_poll_queue <= 1;
    end
    if(&heartbeat_cnt) begin
        heartbeat_queue <= 1;
    end

    if(&rx_timeout) begin

        rx_timed_out <= 1;
        rx_timeout <= 0;
        state <= ST_RESET;
    end
    
    if(~reset_n_s) begin
        state <= ST_RESET;
    end
end








    reg         reset_tr_n;
    localparam  BITLEN = 60;
    
    reg         rx_word_done;
    reg [31:0]  rx_word_shift;
    reg [31:0]  rx_word;
    
    reg         tx_word_start, tx_word_start_1;
    reg         tx_word_done;
    reg [31:0]  tx_word;
    reg [31:0]  tx_word_shift;
    
    reg [7:0]   tr_cnt;
    reg [5:0]   tr_bit;
    
    localparam  TR_IDLE         = 'd1;
    localparam  TR_TX_START     = 'd2;
    localparam  TR_TX_CONTINUE  = 'd3;
    localparam  TR_TX_DONE      = 'd4;
    localparam  TR_RX_START     = 'd5;
    localparam  TR_RX_WAITEDGE  = 'd6;
    localparam  TR_RX_DONE      = 'd7;
    
    reg [3:0]   tr_state;

always @(posedge clk) begin

    rx_word_done <= 0;
    tx_word_done <= 0;
    
    tx_word_start_1 <= tx_word_start;
    
    case(tr_state)
    TR_IDLE: begin
        tr_bit <= 0;
        tr_cnt <= 0;
            
        pad_1wire <= 1'bZ;
        
        if(tx_word_start & ~tx_word_start_1) begin

            tx_word_shift <= tx_word;
            tr_state <= TR_TX_START;
        end
        
        if(pad_1wire_f) begin

            tr_state <= TR_RX_START;
        end
    end
    

    TR_TX_START: begin

        tr_cnt <= tr_cnt + 1'b1;
        if(&tr_cnt) begin

            pad_1wire <= 1'b1;
            tr_state <= TR_TX_CONTINUE;
        end
    end
    TR_TX_CONTINUE: begin
        tr_cnt <= tr_cnt + 1'b1;
        case(tr_cnt)
        0: begin
            pad_1wire <= 1'b0;
        end
        (BITLEN/3): begin
            pad_1wire <= tx_word_shift[31];
        end
        (BITLEN*2/3): begin
            pad_1wire <= 1'b1;
        end
        (BITLEN-1): begin
            tr_cnt <= 0;
            tx_word_shift <= {tx_word_shift[30:0], 1'b1};
            
            tr_bit <= tr_bit + 1'b1;
            if(tr_bit == 31) begin
                tr_state <= TR_TX_DONE;
            end
        end
        endcase
    end
    TR_TX_DONE: begin
        tx_word_done <= 1;
        tr_state <= TR_IDLE;
    end
    

    TR_RX_START: begin
        tr_cnt <= tr_cnt + 1'b1;
        case(tr_cnt)
        (BITLEN/2-4): begin 
            rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s};
        end
        (BITLEN*5/6): begin 
            tr_cnt <= 0;
            

            tr_state <= TR_RX_WAITEDGE;
            tr_bit <= tr_bit + 1'b1;
            if(tr_bit == 31) begin

                tr_state <= TR_RX_DONE;
            end
        end
        endcase
    end
    TR_RX_WAITEDGE: begin
        if(pad_1wire_f) begin
            tr_state <= TR_RX_START;
        end
    end
    TR_RX_DONE: begin
        rx_word <= rx_word_shift;
        rx_word_done <= 1;
        tr_state <= TR_IDLE;
    end
    
    default: begin
        tr_state <= TR_IDLE;
    end
    endcase

    if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE;
end

endmodule
module io_pad_controller (

input   wire            clk,
input   wire            reset_n,

inout   reg             pad_1wire,

output  reg     [15:0]  cont1_key,
output  reg     [15:0]  cont2_key,
output  reg     [15:0]  cont3_key,
output  reg     [15:0]  cont4_key,
output  reg     [31:0]  cont1_joy,
output  reg     [31:0]  cont2_joy,
output  reg     [31:0]  cont3_joy,
output  reg     [31:0]  cont4_joy,
output  reg     [15:0]  cont1_trig,
output  reg     [15:0]  cont2_trig,
output  reg     [15:0]  cont3_trig,
output  reg     [15:0]  cont4_trig,

output  reg             rx_timed_out
);


    wire        reset_n_s;
synch_3 s00(reset_n, reset_n_s, clk);

    wire        pad_1wire_s, pad_1wire_r, pad_1wire_f;
synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f);






    reg [20:0]  rx_timeout;
    
    reg [15:0]  auto_poll_cnt;
    reg         auto_poll_queue;
    
    reg [18:0]  heartbeat_cnt;
    reg         heartbeat_queue;
    

    localparam  ST_RESET        = 'd0;
    localparam  ST_IDLE         = 'd1;
    localparam  ST_RX_BUTTON_1  = 'd2;
    localparam  ST_RX_BUTTON_2  = 'd3;
    localparam  ST_TX_SCALER    = 'd4;
    localparam  ST_END_TX       = 'd5;
    
    reg [3:0]   state;
    reg [3:0]   cnt;
    
always @(posedge clk) begin
    tx_word_start <= 0;
    
    auto_poll_cnt <= auto_poll_cnt + 1'b1;
    heartbeat_cnt <= heartbeat_cnt + 1'b1;
    

    rx_timeout <= rx_timeout + 1'b1;
    
    case(state)
    ST_RESET: begin
        reset_tr_n <= 0;
        rx_timed_out <= 0;
        
        if(&rx_timeout[19:0]) begin
            state <= ST_IDLE;
        end
    end
    ST_IDLE: begin

        reset_tr_n <= 1;
        rx_timeout <= 0;
        cnt <= 0;
        if(auto_poll_queue) begin
            auto_poll_queue <= 0;
            
            tx_word_start <= 1;
            tx_word <= 32'h4A10000C;
            
            state <= ST_RX_BUTTON_1;
        end else if(heartbeat_queue) begin
            heartbeat_queue <= 0;
        
            tx_word_start <= 1;
            tx_word <= 32'h4AFE0000;
        
            state <= ST_END_TX;
        end 
    end

    ST_RX_BUTTON_1: begin
        if(tx_word_done) begin
            state <= ST_RX_BUTTON_2;
        end 
    end
    ST_RX_BUTTON_2: begin
        if(rx_word_done) begin
            cnt <= cnt + 1'b1;
            case(cnt)
            0: cont1_key <= rx_word;
            1: cont1_joy <= rx_word;
            2: cont1_trig <= rx_word;
            
            3: cont2_key <= rx_word;
            4: cont2_joy <= rx_word;
            5: cont2_trig <= rx_word;
            
            6: cont3_key <= rx_word;
            7: cont3_joy <= rx_word;
            8: cont3_trig <= rx_word;
            
            9: cont4_key <= rx_word;
            10: cont4_joy <= rx_word;
            11: begin
                cont4_trig <= rx_word;
                state <= ST_IDLE;   
            end
            endcase
        end 
    end

    ST_END_TX: begin

        if(tx_word_done) begin
            state <= ST_IDLE;   
        end
    end
    endcase
    
    
    if(&auto_poll_cnt) begin
        auto_poll_queue <= 1;
    end
    if(&heartbeat_cnt) begin
        heartbeat_queue <= 1;
    end

    if(&rx_timeout) begin

        rx_timed_out <= 1;
        rx_timeout <= 0;
        state <= ST_RESET;
    end
    
    if(~reset_n_s) begin
        state <= ST_RESET;
    end
end








    reg         reset_tr_n;
    localparam  BITLEN = 60;
    
    reg         rx_word_done;
    reg [31:0]  rx_word_shift;
    reg [31:0]  rx_word;
    
    reg         tx_word_start, tx_word_start_1;
    reg         tx_word_done;
    reg [31:0]  tx_word;
    reg [31:0]  tx_word_shift;
    
    reg [7:0]   tr_cnt;
    reg [5:0]   tr_bit;
    
    localparam  TR_IDLE         = 'd1;
    localparam  TR_TX_START     = 'd2;
    localparam  TR_TX_CONTINUE  = 'd3;
    localparam  TR_TX_DONE      = 'd4;
    localparam  TR_RX_START     = 'd5;
    localparam  TR_RX_WAITEDGE  = 'd6;
    localparam  TR_RX_DONE      = 'd7;
    
    reg [3:0]   tr_state;

always @(posedge clk) begin

    rx_word_done <= 0;
    tx_word_done <= 0;
    
    tx_word_start_1 <= tx_word_start;
    
    case(tr_state)
    TR_IDLE: begin
        tr_bit <= 0;
        tr_cnt <= 0;
            
        pad_1wire <= 1'bZ;
        
        if(tx_word_start & ~tx_word_start_1) begin

            tx_word_shift <= tx_word;
            tr_state <= TR_TX_START;
        end
        
        if(pad_1wire_f) begin

            tr_state <= TR_RX_START;
        end
    end
    

    TR_TX_START: begin

        tr_cnt <= tr_cnt + 1'b1;
        if(&tr_cnt) begin

            pad_1wire <= 1'b1;
            tr_state <= TR_TX_CONTINUE;
        end
    end
    TR_TX_CONTINUE: begin
        tr_cnt <= tr_cnt + 1'b1;
        case(tr_cnt)
        0: begin
            pad_1wire <= 1'b0;
        end
        (BITLEN/3): begin
            pad_1wire <= tx_word_shift[31];
        end
        (BITLEN*2/3): begin
            pad_1wire <= 1'b1;
        end
        (BITLEN-1): begin
            tr_cnt <= 0;
            tx_word_shift <= {tx_word_shift[30:0], 1'b1};
            
            tr_bit <= tr_bit + 1'b1;
            if(tr_bit == 31) begin
                tr_state <= TR_TX_DONE;
            end
        end
        endcase
    end
    TR_TX_DONE: begin
        tx_word_done <= 1;
        tr_state <= TR_IDLE;
    end
    

    TR_RX_START: begin
        tr_cnt <= tr_cnt + 1'b1;
        case(tr_cnt)
        (BITLEN/2-4): begin 
            rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s};
        end
        (BITLEN*5/6): begin 
            tr_cnt <= 0;
            

            tr_state <= TR_RX_WAITEDGE;
            tr_bit <= tr_bit + 1'b1;
            if(tr_bit == 31) begin

                tr_state <= TR_RX_DONE;
            end
        end
        endcase
    end
    TR_RX_WAITEDGE: begin
        if(pad_1wire_f) begin
            tr_state <= TR_RX_START;
        end
    end
    TR_RX_DONE: begin
        rx_word <= rx_word_shift;
        rx_word_done <= 1;
        tr_state <= TR_IDLE;
    end
    
    default: begin
        tr_state <= TR_IDLE;
    end
    endcase

    if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE;
end

endmodule