data/full_repos/permissive/487478597/riscv_mem.v
1: b'%Error: data/full_repos/permissive/487478597/riscv_mem.v:66: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(status == 2\'b01) begin\n                    ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:71: syntax error, unexpected \'{\'\n                    {cache_reg[index][{addr[3:2], 2\'h3}], cache_reg[index][{addr[3:2], 2\'h2}], \n                    ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:74: syntax error, unexpected \'[\', expecting IDENTIFIER\n                else cache_reg[index][addr[3:0]] = Wdata;\n                              ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:79: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    Rdata = {cache_reg[index][{addr[3:2], 2\'h3}], \n                          ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};\n                           ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:95: syntax error, unexpected <=, expecting IDENTIFIER\n           mem_Wdata <= {cache_reg[index][{cnt, 2\'h3}], \n                     ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n            mem_Wdata <= 0;\n                      ^~\n%Warning-STMTDLY: data/full_repos/permissive/487478597/riscv_mem.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #1 request_num = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module CPU (
    input  hit_miss,
    input  clock,
    output read_write,
    output [9:0] address,
    output [31:0] write_data
);
    parameter  request_total = 10;
    reg [4:0]  request_num;
    reg        read_write_test[request_total-1:0];
    reg [9:0]  address_test[request_total-1:0];
    reg [31:0] write_data_test[request_total-1:0]; 
    initial begin
        #1 request_num = 0;
        read_write_test[0] = 0; address_test[0] = 10'h0; write_data_test[0] = 0;
        read_write_test[1] = 1; address_test[1] = 10'h10; write_data_test[1] = 32'hfac;
        read_write_test[2] = 0; address_test[2] = 10'h14; write_data_test[2] = 0;
        read_write_test[3] = 0; address_test[3] = 10'h46; write_data_test[3] = 0;
        read_write_test[4] = 0; address_test[4] = 10'h10; write_data_test[4] = 0;
        read_write_test[5] = 1; address_test[5] = 10'h42; write_data_test[5] = 32'h3f;
        read_write_test[6] = 1; address_test[6] = 10'h0; write_data_test[6] = 32'hffffffff;
        read_write_test[7] = 1; address_test[7] = 10'h8; write_data_test[7] = 32'hffffffff;
        read_write_test[8] = 0; address_test[8] = 10'h40; write_data_test[8] = 0;
        read_write_test[9] = 0; address_test[9] = 10'h1; write_data_test[9] = 0;
    end
    always @(posedge clock) begin
        if (hit_miss == 1) request_num = request_num + 1;
        else request_num = request_num;
    end
    assign address      = address_test[request_num];
    assign read_write   = read_write_test[request_num];
    assign write_data   = write_data_test[request_num]; 
endmodule
module CPU (
    input  hit_miss,
    input  clock,
    output read_write,
    output [9:0] address,
    output [31:0] write_data
);

    parameter  request_total = 10;
    reg [4:0]  request_num;
    reg        read_write_test[request_total-1:0];
    reg [9:0]  address_test[request_total-1:0];
    reg [31:0] write_data_test[request_total-1:0]; 
    initial begin
        #1 request_num = 0;
        read_write_test[0] = 0; address_test[0] = 10'h0; write_data_test[0] = 0;
        read_write_test[1] = 1; address_test[1] = 10'h10; write_data_test[1] = 32'hfac;
        read_write_test[2] = 0; address_test[2] = 10'h14; write_data_test[2] = 0;
        read_write_test[3] = 0; address_test[3] = 10'h46; write_data_test[3] = 0;
        read_write_test[4] = 0; address_test[4] = 10'h10; write_data_test[4] = 0;
        read_write_test[5] = 1; address_test[5] = 10'h42; write_data_test[5] = 32'h3f;
        read_write_test[6] = 1; address_test[6] = 10'h0; write_data_test[6] = 32'hffffffff;
        read_write_test[7] = 1; address_test[7] = 10'h8; write_data_test[7] = 32'hffffffff;
        read_write_test[8] = 0; address_test[8] = 10'h40; write_data_test[8] = 0;
        read_write_test[9] = 0; address_test[9] = 10'h1; write_data_test[9] = 0;
    end
    always @(posedge clock) begin
        if (hit_miss == 1) request_num = request_num + 1;
        else request_num = request_num;
    end
    assign address      = address_test[request_num];
    assign read_write   = read_write_test[request_num];
    assign write_data   = write_data_test[request_num]; 
endmodule