data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:41: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b1, "reg write must be in one tick")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:41: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b1, "reg write must be in one tick")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:48: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "ack must be reseted to zero")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:48: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "ack must be reseted to zero")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:58: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b1, "set another register")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:58: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b1, "set another register")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:64: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "ack must be reseted")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:64: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "ack must be reseted")\n             ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:69: Too many digits for 32 bit number: 32\'h1111_22222\n  data_i <= 32\'h1111_22222;\n            ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:83: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b1, "setup second reg in second thread")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:83: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b1, "setup second reg in second thread")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:90: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "registers setted all must be clean here")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:90: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "registers setted all must be clean here")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:103: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b1, "read from register ack in 1 tick")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:103: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b1, "read from register ack in 1 tick")\n             ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:104: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(data_o, 32\'h1111_1111, "checking read from register")\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:114: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(data_o, 32\'h2222_2222, "checking read r1 thread 1")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:114: syntax error, unexpected \',\'\n  `ASSERT(data_o, 32\'h2222_2222, "checking read r1 thread 1")\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:120: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "all clearing")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:120: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "all clearing")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:139: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(W_ADDR, 32\'hxxxx_xxxx, "do not use bus before W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:139: syntax error, unexpected \',\'\n  `ASSERT(W_ADDR, 32\'hxxxx_xxxx, "do not use bus before W_ACK")\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:144: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "fetch must not set ACK before W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:144: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "fetch must not set ACK before W_ACK")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:151: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "fetch still must not set ACK before W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:151: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "fetch still must not set ACK before W_ACK")\n             ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:152: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(W_ADDR, 32\'h0000_0001, "Set address on W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:153: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(W_DATA_O, 32\'h0000_0011, "Set data on W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:154: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(W_WRITE, 1\'b1, "Writing mode")\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #10 W_CLK <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:163: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b0, "fetch still must not set ACK before W_ACK")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:163: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b0, "fetch still must not set ACK before W_ACK")\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #10 W_CLK <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #10 W_CLK <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #10 W_CLK <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #10 W_CLK <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= 0;\n  ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:180: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(ack, 1\'b1, "Command done")\n  ^~~~~~~\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:180: syntax error, unexpected \',\'\n  `ASSERT(ack, 1\'b1, "Command done")\n             ^\n%Error: data/full_repos/permissive/52359991/cores/CPU/tb/fetch_tb.v:181: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(W_ADDR, 32\'hz, "Buss unsetted")\n  ^~~~~~~\n%Error: Exiting due to 34 error(s), 36 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fetch_tb;

reg clk;
reg f_enable;
reg write_mode;
reg [1:0] thread;
reg [31:0] addr;
reg [31:0] data_i;
wire ack;

wire [31:0] data_o;

reg W_CLK;
wire [31:0] W_ADDR;
wire [31:0] W_DATA_O;
wire W_WRITE;

reg W_ACK;
reg [31:0] W_DATA_I;

FETCH fetch1(clk, f_enable, write_mode, addr, data_i, thread, data_o, ack, W_CLK, W_ACK, W_DATA_I, W_DATA_O, W_ADDR, W_WRITE);


initial
begin:tb

  clk <= 0;
  thread = 0;



  f_enable <= 1;
  write_mode <= 1;
  addr <= 32'hFFFF_FFF0;
  data_i <= 32'h1111_1111;
  
  #10 clk <= 1'b1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "reg write must be in one tick")
  f_enable <= 0;

  #10 clk <= 1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "ack must be reseted to zero")

  f_enable <= 1'b1;
  addr <= 32'hFFFF_FFF1;
  data_i <= 32'h2222_1111;

  #10 clk <= 1'b1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "set another register")
  f_enable <= 1'b0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "ack must be reseted")

  thread <= 2'b01;

  addr <= 32'hFFFF_FFF0;
  data_i <= 32'h1111_22222;

  f_enable <= 1;

  #10 clk <= 1;
  #10 clk <= 0;


  addr <= 32'hFFFF_FFF1;
  data_i <= 32'h2222_2222;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "setup second reg in second thread")

  f_enable <= 0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "registers setted all must be clean here")
  




  write_mode <= 0;
  f_enable <= 1;
  thread <= 0;
  addr <= 32'hFFFF_FFF0;

  #10 clk <= 1;
  #10 clk <= 0;
  `ASSERT(ack, 1'b1, "read from register ack in 1 tick")
  `ASSERT(data_o, 32'h1111_1111, "checking read from register")



  thread <= 1;
  addr <= 32'hFFFF_FFF1;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(data_o, 32'h2222_2222, "checking read r1 thread 1")
  f_enable <= 0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "all clearing")

  #10 clk <= 1;
  #10 clk <= 0;





  W_ACK <= 0; 

  write_mode <= 1;
  addr <= 32'h0000_0001;
  f_enable <= 1;
  data_i <= 32'h0000_0011;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(W_ADDR, 32'hxxxx_xxxx, "do not use bus before W_ACK")

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "fetch must not set ACK before W_ACK")
  
  W_CLK <= 1;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "fetch still must not set ACK before W_ACK")
  `ASSERT(W_ADDR, 32'h0000_0001, "Set address on W_ACK")
  `ASSERT(W_DATA_O, 32'h0000_0011, "Set data on W_ACK")
  `ASSERT(W_WRITE, 1'b1, "Writing mode")

  #10 clk <= 1;
  W_CLK <= 0;

  #10 clk <= 0;
  W_CLK <= 1;

  #10 W_CLK <= 0;
  `ASSERT(ack, 1'b0, "fetch still must not set ACK before W_ACK")
  W_ACK <= 1'b1;

  #10 W_CLK <= 1;
  #10 W_CLK <= 0;

  W_ACK <= 1'b0;

  #10 clk <= 1;
  #10 clk <= 0;

  #10 W_CLK <= 1;
  #10 W_CLK <= 0;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "Command done")
  `ASSERT(W_ADDR, 32'hz, "Buss unsetted")

  $finish;
end

endmodule
module fetch_tb;


reg clk;
reg f_enable;
reg write_mode;
reg [1:0] thread;
reg [31:0] addr;
reg [31:0] data_i;
wire ack;

wire [31:0] data_o;

reg W_CLK;
wire [31:0] W_ADDR;
wire [31:0] W_DATA_O;
wire W_WRITE;

reg W_ACK;
reg [31:0] W_DATA_I;

FETCH fetch1(clk, f_enable, write_mode, addr, data_i, thread, data_o, ack, W_CLK, W_ACK, W_DATA_I, W_DATA_O, W_ADDR, W_WRITE);


initial
begin:tb

  clk <= 0;
  thread = 0;



  f_enable <= 1;
  write_mode <= 1;
  addr <= 32'hFFFF_FFF0;
  data_i <= 32'h1111_1111;
  
  #10 clk <= 1'b1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "reg write must be in one tick")
  f_enable <= 0;

  #10 clk <= 1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "ack must be reseted to zero")

  f_enable <= 1'b1;
  addr <= 32'hFFFF_FFF1;
  data_i <= 32'h2222_1111;

  #10 clk <= 1'b1;

  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "set another register")
  f_enable <= 1'b0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "ack must be reseted")

  thread <= 2'b01;

  addr <= 32'hFFFF_FFF0;
  data_i <= 32'h1111_22222;

  f_enable <= 1;

  #10 clk <= 1;
  #10 clk <= 0;


  addr <= 32'hFFFF_FFF1;
  data_i <= 32'h2222_2222;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "setup second reg in second thread")

  f_enable <= 0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "registers setted all must be clean here")
  




  write_mode <= 0;
  f_enable <= 1;
  thread <= 0;
  addr <= 32'hFFFF_FFF0;

  #10 clk <= 1;
  #10 clk <= 0;
  `ASSERT(ack, 1'b1, "read from register ack in 1 tick")
  `ASSERT(data_o, 32'h1111_1111, "checking read from register")



  thread <= 1;
  addr <= 32'hFFFF_FFF1;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(data_o, 32'h2222_2222, "checking read r1 thread 1")
  f_enable <= 0;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "all clearing")

  #10 clk <= 1;
  #10 clk <= 0;





  W_ACK <= 0; 

  write_mode <= 1;
  addr <= 32'h0000_0001;
  f_enable <= 1;
  data_i <= 32'h0000_0011;

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(W_ADDR, 32'hxxxx_xxxx, "do not use bus before W_ACK")

  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "fetch must not set ACK before W_ACK")
  
  W_CLK <= 1;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b0, "fetch still must not set ACK before W_ACK")
  `ASSERT(W_ADDR, 32'h0000_0001, "Set address on W_ACK")
  `ASSERT(W_DATA_O, 32'h0000_0011, "Set data on W_ACK")
  `ASSERT(W_WRITE, 1'b1, "Writing mode")

  #10 clk <= 1;
  W_CLK <= 0;

  #10 clk <= 0;
  W_CLK <= 1;

  #10 W_CLK <= 0;
  `ASSERT(ack, 1'b0, "fetch still must not set ACK before W_ACK")
  W_ACK <= 1'b1;

  #10 W_CLK <= 1;
  #10 W_CLK <= 0;

  W_ACK <= 1'b0;

  #10 clk <= 1;
  #10 clk <= 0;

  #10 W_CLK <= 1;
  #10 W_CLK <= 0;
  
  #10 clk <= 1;
  #10 clk <= 0;

  `ASSERT(ack, 1'b1, "Command done")
  `ASSERT(W_ADDR, 32'hz, "Buss unsetted")

  $finish;
end

endmodule