data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CHANNEL_MEM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CHANNEL_MEM.v:73: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'CHANNEL_MEM_Wrinc\' generates 1 bits.\n                                                                                                                        : ... In instance CHANNEL_MEM\n  Wrptr<=Wrptr+CHANNEL_MEM_Wrinc;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/CHANNEL_MEM.v:84: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'CHANNEL_MEM_Rdinc\' generates 1 bits.\n                                                                                                                        : ... In instance CHANNEL_MEM\n  Rdptr<=Rdptr+CHANNEL_MEM_Rdinc;\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module CHANNEL_MEM #(parameter DATA_WIDTH = 16, MEM_SIZE=1024  ,ADDR_WIDTH = 10)
(

CHANNEL_MEM_Clk,
CHANNEL_MEM_We,
CHANNEL_MEM_Oe,
CHANNEL_MEM_Rdinc,
CHANNEL_MEM_Wrinc,
CHANNEL_MEM_Wptclr,
CHANNEL_MEM_Rptclr,
CHANNEL_MEM_Data_In,

CHANNEL_MEM_Data_Out
);





input CHANNEL_MEM_Clk;
input CHANNEL_MEM_We;
input CHANNEL_MEM_Oe;
input CHANNEL_MEM_Rdinc;
input CHANNEL_MEM_Wrinc;
input CHANNEL_MEM_Wptclr;
input CHANNEL_MEM_Rptclr;
input [DATA_WIDTH-1:0] CHANNEL_MEM_Data_In;
output [DATA_WIDTH-1:0] CHANNEL_MEM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Q_temp;



always@(negedge CHANNEL_MEM_Clk)
begin
	
	if(!CHANNEL_MEM_Wptclr)
	begin
		Wrptr<=0;
	end	
	
	else if(CHANNEL_MEM_We)
	begin
		Ram_Array[Wrptr]<=CHANNEL_MEM_Data_In;
		Wrptr<=Wrptr+CHANNEL_MEM_Wrinc;
	end
	
	
	if(!CHANNEL_MEM_Rptclr)
	begin
		Rdptr<=0;
	end	
	else if(CHANNEL_MEM_Oe)
	begin
		Q_temp<=Ram_Array[Rdptr];
		Rdptr<=Rdptr+CHANNEL_MEM_Rdinc;
	end
	else
		Q_temp<=16'b0;
	
	
end


assign CHANNEL_MEM_Data_Out= CHANNEL_MEM_Oe==1'b1 ? Q_temp:16'b0;


endmodule
module CHANNEL_MEM #(parameter DATA_WIDTH = 16, MEM_SIZE=1024  ,ADDR_WIDTH = 10)
(

CHANNEL_MEM_Clk,
CHANNEL_MEM_We,
CHANNEL_MEM_Oe,
CHANNEL_MEM_Rdinc,
CHANNEL_MEM_Wrinc,
CHANNEL_MEM_Wptclr,
CHANNEL_MEM_Rptclr,
CHANNEL_MEM_Data_In,

CHANNEL_MEM_Data_Out
);






input CHANNEL_MEM_Clk;
input CHANNEL_MEM_We;
input CHANNEL_MEM_Oe;
input CHANNEL_MEM_Rdinc;
input CHANNEL_MEM_Wrinc;
input CHANNEL_MEM_Wptclr;
input CHANNEL_MEM_Rptclr;
input [DATA_WIDTH-1:0] CHANNEL_MEM_Data_In;
output [DATA_WIDTH-1:0] CHANNEL_MEM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Q_temp;



always@(negedge CHANNEL_MEM_Clk)
begin
	
	if(!CHANNEL_MEM_Wptclr)
	begin
		Wrptr<=0;
	end	
	
	else if(CHANNEL_MEM_We)
	begin
		Ram_Array[Wrptr]<=CHANNEL_MEM_Data_In;
		Wrptr<=Wrptr+CHANNEL_MEM_Wrinc;
	end
	
	
	if(!CHANNEL_MEM_Rptclr)
	begin
		Rdptr<=0;
	end	
	else if(CHANNEL_MEM_Oe)
	begin
		Q_temp<=Ram_Array[Rdptr];
		Rdptr<=Rdptr+CHANNEL_MEM_Rdinc;
	end
	else
		Q_temp<=16'b0;
	
	
end


assign CHANNEL_MEM_Data_Out= CHANNEL_MEM_Oe==1'b1 ? Q_temp:16'b0;


endmodule