data/full_repos/permissive/418753087/E902_RTL_FACTORY/gen_rtl/clic/rtl/cr_clic_kid_dummy.v
1: b"%Error: data/full_repos/permissive/418753087/E902_RTL_FACTORY/gen_rtl/clic/rtl/cr_clic_kid_dummy.v:52: Define or directive not defined: '`CLIC_INTCTLBITS'\nparameter CLICINTCTLBITS = `CLIC_INTCTLBITS;\n                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418753087/E902_RTL_FACTORY/gen_rtl/clic/rtl/cr_clic_kid_dummy.v:52: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nparameter CLICINTCTLBITS = `CLIC_INTCTLBITS;\n                                           ^\n%Error: Exiting due to 2 error(s)\n"
module cr_clic_kid_dummy(
  kid_arb_int_all,
  kid_arb_int_hv,
  kid_arb_int_req,
  kid_busif_rdata,
  kid_ctrl_clicintattr_en,
  kid_ctrl_clicintctl_en,
  kid_ctrl_clicintie_en,
  kid_ctrl_clicintip_en,
  kid_ctrl_sample_en
);


output  [3 :0]  kid_arb_int_all;        
output          kid_arb_int_hv;         
output          kid_arb_int_req;        
output  [31:0]  kid_busif_rdata;        
output          kid_ctrl_clicintattr_en; 
output          kid_ctrl_clicintctl_en; 
output          kid_ctrl_clicintie_en;  
output          kid_ctrl_clicintip_en;  
output          kid_ctrl_sample_en;     




wire    [3 :0]  kid_arb_int_all;        
wire            kid_arb_int_hv;         
wire            kid_arb_int_req;        
wire    [31:0]  kid_busif_rdata;        
wire            kid_ctrl_clicintattr_en; 
wire            kid_ctrl_clicintctl_en; 
wire            kid_ctrl_clicintie_en;  
wire            kid_ctrl_clicintip_en;  
wire            kid_ctrl_sample_en;     


parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;

assign kid_arb_int_all[CLICINTCTLBITS:0] = {CLICINTCTLBITS+1{1'b0}};
assign kid_arb_int_hv = 1'b0;
assign kid_arb_int_req = 1'b0;
assign kid_busif_rdata[31:0] = 32'b0;
assign kid_ctrl_clicintattr_en = 1'b0;
assign kid_ctrl_clicintctl_en = 1'b0;
assign kid_ctrl_clicintie_en = 1'b0;
assign kid_ctrl_clicintip_en = 1'b0;
assign kid_ctrl_sample_en = 1'b0;


endmodule
module cr_clic_kid_dummy(
  kid_arb_int_all,
  kid_arb_int_hv,
  kid_arb_int_req,
  kid_busif_rdata,
  kid_ctrl_clicintattr_en,
  kid_ctrl_clicintctl_en,
  kid_ctrl_clicintie_en,
  kid_ctrl_clicintip_en,
  kid_ctrl_sample_en
);



output  [3 :0]  kid_arb_int_all;        
output          kid_arb_int_hv;         
output          kid_arb_int_req;        
output  [31:0]  kid_busif_rdata;        
output          kid_ctrl_clicintattr_en; 
output          kid_ctrl_clicintctl_en; 
output          kid_ctrl_clicintie_en;  
output          kid_ctrl_clicintip_en;  
output          kid_ctrl_sample_en;     




wire    [3 :0]  kid_arb_int_all;        
wire            kid_arb_int_hv;         
wire            kid_arb_int_req;        
wire    [31:0]  kid_busif_rdata;        
wire            kid_ctrl_clicintattr_en; 
wire            kid_ctrl_clicintctl_en; 
wire            kid_ctrl_clicintie_en;  
wire            kid_ctrl_clicintip_en;  
wire            kid_ctrl_sample_en;     


parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;

assign kid_arb_int_all[CLICINTCTLBITS:0] = {CLICINTCTLBITS+1{1'b0}};
assign kid_arb_int_hv = 1'b0;
assign kid_arb_int_req = 1'b0;
assign kid_busif_rdata[31:0] = 32'b0;
assign kid_ctrl_clicintattr_en = 1'b0;
assign kid_ctrl_clicintctl_en = 1'b0;
assign kid_ctrl_clicintie_en = 1'b0;
assign kid_ctrl_clicintip_en = 1'b0;
assign kid_ctrl_sample_en = 1'b0;


endmodule