data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:97: Define or directive not defined: \'`x_or_0\'\n            idata_pvld_in <= `x_or_0;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            idata_pvld_in <= `x_or_0;\n                                    ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:133: Define or directive not defined: \'`x_or_0\'\n            idata_count <= {3{`x_or_0}};\n                              ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:133: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            idata_count <= {3{`x_or_0}};\n                                     ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:186: Define or directive not defined: \'`x_or_0\'\n            odata_adr <= {2{`x_or_0}};\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:186: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            odata_adr <= {2{`x_or_0}};\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:223: Define or directive not defined: \'`x_or_0\'\n            odata_count_p <= {3{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:223: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            odata_count_p <= {3{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:244: Define or directive not defined: \'`x_or_0\'\n        odata_pd <= {256{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:244: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        odata_pd <= {256{`x_or_0}};\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:542: Unsupported or unknown PLI call: $RollPLI\n        prand_inst0 = $RollPLI(min, max, "auto");\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:593: Unsupported or unknown PLI call: $RollPLI\n        prand_inst1 = $RollPLI(min, max, "auto");\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:712: Define or directive not defined: \'`x_or_0\'\n    default: dout = {256{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v:712: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {256{`x_or_0}};\n                                ^\n%Error: Exiting due to 15 error(s)\n'
module vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 (
   Wa0, we0, Di0,
   Ra0, Do0
   );
input [1:0] Wa0;
input we0;
input [255:0] Di0;
input [1:0] Ra0;
output [255:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 256'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [255:0] mem[3:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [255:0] Q0 = mem[0];
wire [255:0] Q1 = mem[1];
wire [255:0] Q2 = mem[2];
wire [255:0] Q3 = mem[3];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule
module vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 (
   Wa0, we0, Di0,
   Ra0, Do0
   );

input [1:0] Wa0;
input we0;
input [255:0] Di0;
input [1:0] Ra0;
output [255:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 256'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [255:0] mem[3:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [255:0] Q0 = mem[0];
wire [255:0] Q1 = mem[1];
wire [255:0] Q2 = mem[2];
wire [255:0] Q3 = mem[3];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule