data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKROOT1.v
data/verilator_xmls/439afbe0-2a5f-4bdf-99e9-3a380bb5acbb.xml
module ATCKROOT1
    (
     A,
     Y
     );
input A;
output Y;

reg    Y;
always @(A)
    begin

    Y = A;
    end

endmodule
module ATCKROOT1
    (
     A,
     Y
     );

input A;
output Y;

reg    Y;
always @(A)
    begin

    Y = A;
    end

endmodule