data/full_repos/permissive/456771003/rv_core.v
1: b'%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:372: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 20 bits.\n                                                                  : ... In instance rv_core.decode_inst\n    assign imm_31_12   = op[31:12];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:390: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        fmt = \'bx;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d1:  fmt = 3\'d4; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d2:  fmt = 3\'d4; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d3:  fmt = 3\'d5; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d4:  fmt = 3\'d1; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d5:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d6:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d7:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d8:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d9:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d10:  fmt = 3\'d3; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d11:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d12:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d13:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d14:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d15:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d16:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d17:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d18:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d19:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d20:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d21:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d22:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d23:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d24:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d25:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d26:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d27:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d28:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d29:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d30:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d31:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d32:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d33:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d34:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d35:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d36:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d37:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d38:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d39:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d40:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d41:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d42:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d43:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d44:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d45:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d46:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d47:  fmt = 3\'d1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:406: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 22 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            3\'d4: imm = {imm_31_12, 12\'b0};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:407: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            3\'d5: imm = {{19{imm_20}}, imm_20, imm_19_12, imm_11_a20, imm_10_1, 1\'b0};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:473: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            default:        decode_out = {5\'bx,     2\'bx,      2\'bx,      1\'b0, 2\'bx,        2\'d0,  1\'b0, 1\'b0};\n                                       ^\n%Error: data/full_repos/permissive/456771003/rv_core.v:196: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.RESET_VAL(1\'d0)) state_ff(.clk(clk), .rst(rst), .d(state_n), .q(state_q));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar.v\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar.sv\n             ff_ar\n             ff_ar.v\n             ff_ar.sv\n             obj_dir/ff_ar\n             obj_dir/ff_ar.v\n             obj_dir/ff_ar.sv\n%Error: data/full_repos/permissive/456771003/rv_core.v:200: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) pc(.clk(clk), .rst(rst), .d(pc_n), .q(pc_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:203: Cannot find file containing module: \'ff_ar\'\n    ff_ar rf_write_ff(.clk(clk), .rst(rst), .d(rf_write_n && (state_q == 1\'d0)), .q(rf_write_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:206: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(2)) rf_wdata_sel_ff(.clk(clk), .rst(rst), .d(rf_wdata_sel_n), .q(rf_wdata_sel_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:210: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(5)) rd_ff(.clk(clk), .rst(rst), .d(rd_n), .q(rd_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:215: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) alu_reg(.clk(clk), .rst(rst), .d(alu_out), .q(alu_out_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:218: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) rs2_val_ff(.clk(clk), .rst(rst), .d(rs2_val), .q(rs2_val_q));\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:223: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                  : ... In instance rv_core\n    assign addr_n = (state_n == 1\'d0) ? pc_n : alu_out;\n                  ^\n%Error: data/full_repos/permissive/456771003/rv_core.v:224: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(20)) addr_reg(.clk(clk), .rst(rst), .d(addr_n), .q(addr_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:227: Cannot find file containing module: \'ff_ar\'\n    ff_ar write_ff(.clk(clk), .rst(rst), .d(write_n), .q(write_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:230: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.RESET_VAL(1)) read_ff(.clk(clk), .rst(rst), .d(read_n), .q(read_q));\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:251: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                  : ... In instance rv_core\n    assign shamt = {27\'b0, data[24:20]};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:279: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'shamt\' generates 5 bits.\n                                                                  : ... In instance rv_core\n            2\'d2:  alu_in2 = shamt;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:291: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                  : ... In instance rv_core\n            4\'d3:  alu_out = alu_in1 == alu_in2;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:292: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                  : ... In instance rv_core\n            4\'d5 : alu_out = alu_in1 < alu_in2;\n                           ^\n%Error: Exiting due to 10 error(s), 62 warning(s)\n'
module decode(
    input wire [31:0] op,
    output wire [3:0] alu_op,
    output wire [1:0] alu_in1_sel,
    output wire [1:0] alu_in2_sel,
    output reg [31:0] imm,
    output wire [4:0] rd, rs1, rs2,
    output wire rf_write,
    output wire [1:0] rf_wdata_sel,
    output wire [1:0] branch,
    output wire read,
    output wire write
);

    reg [5:0] inst;
    reg [3:0] fmt;

    wire [ 2:0] func3;
    wire [ 6:0] func7;
    wire [11:0] imm_11_0;
    wire [ 4:0] imm_4_0;
    wire [ 6:0] imm_11_5;
    wire        imm_11_a7;
    wire [ 3:0] imm_4_1;
    wire [ 5:0] imm_10_5;
    wire        imm_12;
    wire [ 9:0] imm_31_12;
    wire [ 7:0] imm_19_12;
    wire        imm_11_a20;
    wire [ 9:0] imm_10_1;
    wire        imm_20;

    assign rd          = op[11:7];
    assign rs1         = op[19:15];
    assign rs2         = op[24:20];
    assign func3       = op[14:12];
    assign func7       = op[31:25];
    assign imm_11_0    = op[31:20];
    assign imm_4_0     = op[11:7];
    assign imm_11_5    = op[31:25];
    assign imm_11_a7   = op[7];
    assign imm_4_1     = op[11:8];
    assign imm_10_5    = op[30:25];
    assign imm_12      = op[31];
    assign imm_31_12   = op[31:12];
    assign imm_19_12   = op[19:12];
    assign imm_11_a20  = op[20];
    assign imm_10_1    = op[30:21];
    assign imm_20      = op[31];

    always @(*) begin

        inst = `INST_INVALID;
        if (0) begin
        `define X(MASK, VALUE, FMT, MNEM, STR) \
            end else if ((op & MASK) == VALUE) begin inst = MNEM;
        `OPCODE_LIST
        end
        `undef X
    end

    always @(*) begin
        fmt = 'bx;
        case (inst)
        `define X(MASK, VALUE, FMT, MNEM, STR) \
            MNEM:  fmt = FMT;
            `OPCODE_LIST
        `undef X
        endcase
    end


    always @(*) begin
        imm = 'bx;
        case (fmt)
            `FMT_I: imm = {{20{imm_11_0[11]}}, imm_11_0};
            `FMT_S: imm = {{20{imm_11_5[6]}}, imm_11_5, imm_4_0};
            `FMT_B: imm = {{19{imm_12}}, imm_12, imm_11_a7, imm_10_5, imm_4_1, 1'b0};
            `FMT_U: imm = {imm_31_12, 12'b0};
            `FMT_J: imm = {{19{imm_20}}, imm_20, imm_19_12, imm_11_a20, imm_10_1, 1'b0};
        endcase
    end

    reg [14:0] decode_out;

    assign alu_op       = decode_out[14:11];
    assign alu_in1_sel  = decode_out[10:9];
    assign alu_in2_sel  = decode_out[8:7];
    assign rf_write     = decode_out[6];
    assign rf_wdata_sel = decode_out[5:4];
    assign branch       = decode_out[3:2];
    assign read         = decode_out[1];
    assign write        = decode_out[0];


    always @(*) begin
        decode_out = 15'bx;
        case (inst)
            `INST_LUI:      decode_out = {`ALU_IN2, 2'bx,      `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_AUIPC:    decode_out = {`ALU_ADD, `SEL1_PC,  `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_JAL:      decode_out = {`ALU_ADD, `SEL1_PC,  `SEL2_IMM, 1'b1, `RF_SEL_PC4, `BR_YES, 1'b0, 1'b0};
            `INST_JALR:     decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_PC4, `BR_YES, 1'b0, 1'b0};
            `INST_BEQ:      decode_out = {`ALU_EQ,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BNE:      decode_out = {`ALU_EQ,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_BLT:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BGE:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_BLTU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BGEU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_LB:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LH:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LW:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LBU:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LHU:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_SB:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_SH:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_SW:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_ADDI:     decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTI:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTIU:    decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_XORI:     decode_out = {`ALU_XOR, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ORI:      decode_out = {`ALU_OR,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ANDI:     decode_out = {`ALU_AND, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLLI:     decode_out = {`ALU_SLL, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRLI:     decode_out = {`ALU_SRL, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRAI:     decode_out = {`ALU_SRA, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ADD:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SUB:      decode_out = {`ALU_SUB, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLL:      decode_out = {`ALU_SLL, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLT:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_XOR:      decode_out = {`ALU_XOR, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRL:      decode_out = {`ALU_SRL, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRA:      decode_out = {`ALU_SRA, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_OR:       decode_out = {`ALU_OR,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_AND:      decode_out = {`ALU_AND, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_FENCE:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_FENCE_I:  decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ECALL:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_EBREAK:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRW:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRS:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRC:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRWI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRSI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRCI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            default:        decode_out = {5'bx,     2'bx,      2'bx,      1'b0, 2'bx,        `BR_NO,  1'b0, 1'b0};
        endcase
    end

endmodule
module decode(
    input wire [31:0] op,
    output wire [3:0] alu_op,
    output wire [1:0] alu_in1_sel,
    output wire [1:0] alu_in2_sel,
    output reg [31:0] imm,
    output wire [4:0] rd, rs1, rs2,
    output wire rf_write,
    output wire [1:0] rf_wdata_sel,
    output wire [1:0] branch,
    output wire read,
    output wire write
);


    reg [5:0] inst;
    reg [3:0] fmt;

    wire [ 2:0] func3;
    wire [ 6:0] func7;
    wire [11:0] imm_11_0;
    wire [ 4:0] imm_4_0;
    wire [ 6:0] imm_11_5;
    wire        imm_11_a7;
    wire [ 3:0] imm_4_1;
    wire [ 5:0] imm_10_5;
    wire        imm_12;
    wire [ 9:0] imm_31_12;
    wire [ 7:0] imm_19_12;
    wire        imm_11_a20;
    wire [ 9:0] imm_10_1;
    wire        imm_20;

    assign rd          = op[11:7];
    assign rs1         = op[19:15];
    assign rs2         = op[24:20];
    assign func3       = op[14:12];
    assign func7       = op[31:25];
    assign imm_11_0    = op[31:20];
    assign imm_4_0     = op[11:7];
    assign imm_11_5    = op[31:25];
    assign imm_11_a7   = op[7];
    assign imm_4_1     = op[11:8];
    assign imm_10_5    = op[30:25];
    assign imm_12      = op[31];
    assign imm_31_12   = op[31:12];
    assign imm_19_12   = op[19:12];
    assign imm_11_a20  = op[20];
    assign imm_10_1    = op[30:21];
    assign imm_20      = op[31];

    always @(*) begin

        inst = `INST_INVALID;
        if (0) begin
        `define X(MASK, VALUE, FMT, MNEM, STR) \
            end else if ((op & MASK) == VALUE) begin inst = MNEM;
        `OPCODE_LIST
        end
        `undef X
    end

    always @(*) begin
        fmt = 'bx;
        case (inst)
        `define X(MASK, VALUE, FMT, MNEM, STR) \
            MNEM:  fmt = FMT;
            `OPCODE_LIST
        `undef X
        endcase
    end


    always @(*) begin
        imm = 'bx;
        case (fmt)
            `FMT_I: imm = {{20{imm_11_0[11]}}, imm_11_0};
            `FMT_S: imm = {{20{imm_11_5[6]}}, imm_11_5, imm_4_0};
            `FMT_B: imm = {{19{imm_12}}, imm_12, imm_11_a7, imm_10_5, imm_4_1, 1'b0};
            `FMT_U: imm = {imm_31_12, 12'b0};
            `FMT_J: imm = {{19{imm_20}}, imm_20, imm_19_12, imm_11_a20, imm_10_1, 1'b0};
        endcase
    end

    reg [14:0] decode_out;

    assign alu_op       = decode_out[14:11];
    assign alu_in1_sel  = decode_out[10:9];
    assign alu_in2_sel  = decode_out[8:7];
    assign rf_write     = decode_out[6];
    assign rf_wdata_sel = decode_out[5:4];
    assign branch       = decode_out[3:2];
    assign read         = decode_out[1];
    assign write        = decode_out[0];


    always @(*) begin
        decode_out = 15'bx;
        case (inst)
            `INST_LUI:      decode_out = {`ALU_IN2, 2'bx,      `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_AUIPC:    decode_out = {`ALU_ADD, `SEL1_PC,  `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_JAL:      decode_out = {`ALU_ADD, `SEL1_PC,  `SEL2_IMM, 1'b1, `RF_SEL_PC4, `BR_YES, 1'b0, 1'b0};
            `INST_JALR:     decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_PC4, `BR_YES, 1'b0, 1'b0};
            `INST_BEQ:      decode_out = {`ALU_EQ,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BNE:      decode_out = {`ALU_EQ,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_BLT:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BGE:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_BLTU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF1, 1'b0, 1'b0};
            `INST_BGEU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b0, 2'bx,        `BR_IF0, 1'b0, 1'b0};
            `INST_LB:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LH:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LW:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LBU:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_LHU:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_MEM, `BR_NO,  1'b1, 1'b0};
            `INST_SB:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_SH:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_SW:       decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b0, 2'bx,        `BR_NO,  1'b0, 1'b1};
            `INST_ADDI:     decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTI:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTIU:    decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_XORI:     decode_out = {`ALU_XOR, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ORI:      decode_out = {`ALU_OR,  `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ANDI:     decode_out = {`ALU_AND, `SEL1_RS1, `SEL2_IMM, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLLI:     decode_out = {`ALU_SLL, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRLI:     decode_out = {`ALU_SRL, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRAI:     decode_out = {`ALU_SRA, `SEL1_RS1, `SEL2_SH,  1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ADD:      decode_out = {`ALU_ADD, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SUB:      decode_out = {`ALU_SUB, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLL:      decode_out = {`ALU_SLL, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLT:      decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SLTU:     decode_out = {`ALU_LT,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_XOR:      decode_out = {`ALU_XOR, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRL:      decode_out = {`ALU_SRL, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_SRA:      decode_out = {`ALU_SRA, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_OR:       decode_out = {`ALU_OR,  `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_AND:      decode_out = {`ALU_AND, `SEL1_RS1, `SEL2_RS2, 1'b1, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_FENCE:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_FENCE_I:  decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_ECALL:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_EBREAK:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRW:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRS:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRC:    decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRWI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRSI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            `INST_CSRRCI:   decode_out = {`ALU_IN1, `SEL1_RS1, `SEL2_RS2, 1'b0, `RF_SEL_ALU, `BR_NO,  1'b0, 1'b0};
            default:        decode_out = {5'bx,     2'bx,      2'bx,      1'b0, 2'bx,        `BR_NO,  1'b0, 1'b0};
        endcase
    end

endmodule