data/full_repos/permissive/455223995/test/axi_av_conv.v
data/verilator_xmls/64e08aab-5935-4cc8-a6c3-6c70e6661f6a.xml
module axi_av_conv
(
  input                                aclk,
  input                                aresetn,





  input  [31:0]                        axs_awaddr,
  input   [7:0]                        axs_awlen,
  input   [2:0]                        axs_awprot,
  input                                axs_awvalid,
  output                               axs_awready,



  input  [31:0]                        axs_wdata,
  input                                axs_wlast,
  input                                axs_wvalid,
  output                               axs_wready,



  output                               axs_bvalid,
  input                                axs_bready,



  input  [31:0]                        axs_araddr,
  input   [7:0]                        axs_arlen,
  input   [3:0]                        axs_arcache,
  input                                axs_aruser,
  input   [2:0]                        axs_arprot,
  input                                axs_arvalid,
  output                               axs_arready,



  output [31:0]                        axs_rdata,
  output                               axs_rvalid,
  input                                axs_rready,




  input                                avm_rx_waitrequest,
  output [11:0]                        avm_rx_burstcount,
  output [31:0]                        avm_rx_address,
  output                               avm_rx_read,
  input  [31:0]                        avm_rx_readdata,
  input                                avm_rx_readdatavalid,


  input                                avm_tx_waitrequest,
  output [11:0]                        avm_tx_burstcount,
  output [31:0]                        avm_tx_address,
  output                               avm_tx_write,
  output [31:0]                        avm_tx_writedata
);





reg  [7:0]                             axs_awlen_held;
reg [31:0]                             axs_awaddr_held;
reg                                    axs_wr_busy;




wire   clk                             = aclk;
wire   reset_n                         = aresetn;




assign axs_bvalid                      = 1'b0;






assign avm_rx_address                  = axs_araddr;
assign avm_rx_burstcount               = {3'h0, {1'b0, axs_arlen} + 9'h01};
assign avm_rx_read                     = axs_arvalid;
assign axs_arready                     = ~avm_rx_waitrequest;


assign axs_rdata                       = avm_rx_readdata;
assign axs_rvalid                      = avm_rx_readdatavalid;


assign axs_awready                     = ~axs_wr_busy;
assign avm_tx_burstcount               = {3'h0, {1'b0, axs_awlen_held} + 9'h01};
assign avm_tx_address                  = axs_awaddr_held;


assign axs_wready                      = ~avm_tx_waitrequest;
assign avm_tx_write                    = axs_wvalid;
assign avm_tx_writedata                = axs_wdata;





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    axs_wr_busy                        <= 1'b0;
  end
  else
  begin

    if (axs_wvalid & axs_wready & axs_wlast)
    begin
      axs_wr_busy                      <= 1'b0;
    end



    if (axs_awvalid)
    begin
      axs_awlen_held                   <= axs_awlen;
      axs_awaddr_held                  <= axs_awaddr;
      axs_wr_busy                      <= 1'b1;
    end
  end
end

endmodule
module axi_av_conv
(
  input                                aclk,
  input                                aresetn,





  input  [31:0]                        axs_awaddr,
  input   [7:0]                        axs_awlen,
  input   [2:0]                        axs_awprot,
  input                                axs_awvalid,
  output                               axs_awready,



  input  [31:0]                        axs_wdata,
  input                                axs_wlast,
  input                                axs_wvalid,
  output                               axs_wready,



  output                               axs_bvalid,
  input                                axs_bready,



  input  [31:0]                        axs_araddr,
  input   [7:0]                        axs_arlen,
  input   [3:0]                        axs_arcache,
  input                                axs_aruser,
  input   [2:0]                        axs_arprot,
  input                                axs_arvalid,
  output                               axs_arready,



  output [31:0]                        axs_rdata,
  output                               axs_rvalid,
  input                                axs_rready,




  input                                avm_rx_waitrequest,
  output [11:0]                        avm_rx_burstcount,
  output [31:0]                        avm_rx_address,
  output                               avm_rx_read,
  input  [31:0]                        avm_rx_readdata,
  input                                avm_rx_readdatavalid,


  input                                avm_tx_waitrequest,
  output [11:0]                        avm_tx_burstcount,
  output [31:0]                        avm_tx_address,
  output                               avm_tx_write,
  output [31:0]                        avm_tx_writedata
);






reg  [7:0]                             axs_awlen_held;
reg [31:0]                             axs_awaddr_held;
reg                                    axs_wr_busy;




wire   clk                             = aclk;
wire   reset_n                         = aresetn;




assign axs_bvalid                      = 1'b0;






assign avm_rx_address                  = axs_araddr;
assign avm_rx_burstcount               = {3'h0, {1'b0, axs_arlen} + 9'h01};
assign avm_rx_read                     = axs_arvalid;
assign axs_arready                     = ~avm_rx_waitrequest;


assign axs_rdata                       = avm_rx_readdata;
assign axs_rvalid                      = avm_rx_readdatavalid;


assign axs_awready                     = ~axs_wr_busy;
assign avm_tx_burstcount               = {3'h0, {1'b0, axs_awlen_held} + 9'h01};
assign avm_tx_address                  = axs_awaddr_held;


assign axs_wready                      = ~avm_tx_waitrequest;
assign avm_tx_write                    = axs_wvalid;
assign avm_tx_writedata                = axs_wdata;





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    axs_wr_busy                        <= 1'b0;
  end
  else
  begin

    if (axs_wvalid & axs_wready & axs_wlast)
    begin
      axs_wr_busy                      <= 1'b0;
    end



    if (axs_awvalid)
    begin
      axs_awlen_held                   <= axs_awlen;
      axs_awaddr_held                  <= axs_awaddr;
      axs_wr_busy                      <= 1'b1;
    end
  end
end

endmodule