data/full_repos/permissive/481069643/Day02/ALU_tb.v
1: b'%Error: data/full_repos/permissive/481069643/Day02/ALU_tb.v:45: Unsupported or unknown PLI call: $monitor\n$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b and states are %b and en is %b clk=%b",in_b,in_a,fun,out_alu,out_carry,aluReg0.current_state,en,clk);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#6 rst = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n#12 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#1 en = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#10 en =0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#100 en =1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#50 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day02/ALU_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();

reg clk,en,rst;
reg [3:0]in_a,in_b;
reg [3:0]fun;
wire [3:0]out_alu;
wire out_carry;



ALUwithReg aluReg0(clk,en,rst,in_a,in_b,fun,out_alu,out_carry);

initial
begin
$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b and states are %b and en is %b clk=%b",in_b,in_a,fun,out_alu,out_carry,aluReg0.current_state,en,clk);

rst = 0;
en = 0;

#6 rst = 1;

in_a = 0;
in_b =0;

fun = 0;
#12 rst = 0;
#1 en = 1;
#10 en =0;
#100 en =1;


in_a = 2;
in_b =4;
fun = 9;

#50 $finish;


end 



initial
begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule
module ALU_tb();


reg clk,en,rst;
reg [3:0]in_a,in_b;
reg [3:0]fun;
wire [3:0]out_alu;
wire out_carry;



ALUwithReg aluReg0(clk,en,rst,in_a,in_b,fun,out_alu,out_carry);

initial
begin
$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b and states are %b and en is %b clk=%b",in_b,in_a,fun,out_alu,out_carry,aluReg0.current_state,en,clk);

rst = 0;
en = 0;

#6 rst = 1;

in_a = 0;
in_b =0;

fun = 0;
#12 rst = 0;
#1 en = 1;
#10 en =0;
#100 en =1;


in_a = 2;
in_b =4;
fun = 9;

#50 $finish;


end 



initial
begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule