data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:14: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                   : ... Top module \'GP_DFFS\'\nmodule GP_DFFS(input D, CLK, nSET, output reg Q);\n       ^~~~~~~\n                                                                                                   : ... Top module \'GP_DFFR\'\nmodule GP_DFFR(input D, CLK, nRST, output reg Q);\n       ^~~~~~~\n                                                                                                   : ... Top module \'GP_DFFSI\'\nmodule GP_DFFSI(input D, CLK, nSET, output reg nQ);\n       ^~~~~~~~\n                                                                                                   : ... Top module \'GP_DFFRI\'\nmodule GP_DFFRI(input D, CLK, nRST, output reg nQ);\n       ^~~~~~~~\n                                                                                                   : ... Top module \'GP_DLATCHS\'\nmodule GP_DLATCHS(input D, nCLK, nSET, output reg Q);\n       ^~~~~~~~~~\n                                                                                                   : ... Top module \'GP_DLATCHR\'\nmodule GP_DLATCHR(input D, nCLK, nRST, output reg Q);\n       ^~~~~~~~~~\n                                                                                                   : ... Top module \'GP_DLATCHSI\'\nmodule GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);\n       ^~~~~~~~~~~\n                                                                                                   : ... Top module \'GP_DLATCHRI\'\nmodule GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);\n       ^~~~~~~~~~~\n                                                                                                   : ... Top module \'GP_OBUFT\'\nmodule GP_OBUFT(input IN, input OE, output OUT);\n       ^~~~~~~~\n                                                                                                   : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n                                                                                                   : ... Top module \'$__COUNT_\'\nmodule \\$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:214: Cannot find file containing module: \'GP_COUNT8\'\n   GP_COUNT8 #(\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4,data/full_repos/permissive/441359809/GP_COUNT8\n             data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4,data/full_repos/permissive/441359809/GP_COUNT8.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4,data/full_repos/permissive/441359809/GP_COUNT8.sv\n             GP_COUNT8\n             GP_COUNT8.v\n             GP_COUNT8.sv\n             obj_dir/GP_COUNT8\n             obj_dir/GP_COUNT8.v\n             obj_dir/GP_COUNT8.sv\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:119: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WIDTH-1:0] A;\n       ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:106: Cannot find file containing module: \'GP_IOBUF\'\n GP_IOBUF _TECHMAP_REPLACE_ (\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:94: Cannot find file containing module: \'GP_DLATCHSRI\'\n GP_DLATCHSRI #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:81: Cannot find file containing module: \'GP_DLATCHSRI\'\n GP_DLATCHSRI #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:68: Cannot find file containing module: \'GP_DLATCHSR\'\n GP_DLATCHSR #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:55: Cannot find file containing module: \'GP_DLATCHSR\'\n GP_DLATCHSR #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:42: Cannot find file containing module: \'GP_DFFSRI\'\n GP_DFFSRI #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:29: Cannot find file containing module: \'GP_DFFSRI\'\n GP_DFFSRI #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:16: Cannot find file containing module: \'GP_DFFSR\'\n GP_DFFSR #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/greenpak4/cells_map.v:3: Cannot find file containing module: \'GP_DFFSR\'\n GP_DFFSR #(\n ^~~~~~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n'
module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
	parameter [0:0] INIT = 1'bx;
	GP_DLATCHSR #(
		.INIT(INIT),
		.SRMODE(1'b0),
	) _TECHMAP_REPLACE_ (
		.D(D),
		.nCLK(nCLK),
		.nSR(nRST),
		.Q(Q)
	);
endmodule
module GP_DLATCHR(input D, nCLK, nRST, output reg Q);

	parameter [0:0] INIT = 1'bx;
	GP_DLATCHSR #(
		.INIT(INIT),
		.SRMODE(1'b0),
	) _TECHMAP_REPLACE_ (
		.D(D),
		.nCLK(nCLK),
		.nSR(nRST),
		.Q(Q)
	);
endmodule