data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:24: Cannot find include file: ../genericIOSateliteEnv.v\n`include "../genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:25: Cannot find include file: ../genericIOSateliteEnv_TB.v\n`include "../genericIOSateliteEnv_TB.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:26: Cannot find include file: pwm.v\n`include "pwm.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:39: Define or directive not defined: \'`OSCH_FREQ\'\n OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1\'b0), .OSC(masterClk), .SEDSTDBY ());\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:47: Define or directive not defined: \'`US_NS\'\n  #(`US_NS);\n    ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  #(`US_NS);\n          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:49: Define or directive not defined: \'`US_NS\'\n  #(`US_NS);\n    ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  #(`US_NS);\n          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:51: Define or directive not defined: \'`US_NS\'\n  #(`US_NS);\n    ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:51: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  #(`US_NS);\n          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:53: Define or directive not defined: \'`US_NS\'\n  #(`US_NS);\n    ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:53: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  #(`US_NS);\n          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:58: Define or directive not defined: \'`US_NS\'\n  #(`US_NS);\n    ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  #(`US_NS);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:66: Define or directive not defined: \'`MS_NS\'\n    if($time - t0 > 1000*`MS_NS/125*1.01) begin\n                         ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:66: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    if($time - t0 > 1000*`MS_NS/125*1.01) begin\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:75: Define or directive not defined: \'`MS_NS\'\n    if($time - t0 > 1000*`MS_NS/125*1.01) begin\n                         ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:75: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    if($time - t0 > 1000*`MS_NS/125*1.01) begin\n                               ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:81: syntax error, unexpected \'=\', expecting IDENTIFIER\n   t0 = $time;\n      ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:87: syntax error, unexpected $write\n     $write(".");\n     ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:91: syntax error, unexpected \'=\', expecting IDENTIFIER\n     progress = progress + 1;\n              ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:93: Define or directive not defined: \'`K1_25_NS\'\n    if($time-t0 > setcontrolInput*`K1_25_NS*10/256+setcontrolInput*`K1_25_NS*10/256*0.01) begin      \n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:93: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    if($time-t0 > setcontrolInput*`K1_25_NS*10/256+setcontrolInput*`K1_25_NS*10/256*0.01) begin      \n                                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:93: Define or directive not defined: \'`K1_25_NS\'\n    if($time-t0 > setcontrolInput*`K1_25_NS*10/256+setcontrolInput*`K1_25_NS*10/256*0.01) begin      \n                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:94: Define or directive not defined: \'`K1_25_NS\'\n     $display("pwm: ERROR: pwm pulse length was more than 1 %% longer than expected nominal: %d ns, allowed accuracy +/- %d ns, breaking at %d ns", setcontrolInput*`K1_25_NS*10/256, setcontrolInput*`K1_25_NS*10/256*0.01, $time-t0);\n                                                                                                                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:94: Define or directive not defined: \'`K1_25_NS\'\n     $display("pwm: ERROR: pwm pulse length was more than 1 %% longer than expected nominal: %d ns, allowed accuracy +/- %d ns, breaking at %d ns", setcontrolInput*`K1_25_NS*10/256, setcontrolInput*`K1_25_NS*10/256*0.01, $time-t0);\n                                                                                                                                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:100: Define or directive not defined: \'`K1_25_NS\'\n   if($time-t0 < setcontrolInput*`K1_25_NS*10/256-setcontrolInput*`K1_25_NS*10/256*0.01) begin       \n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:100: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   if($time-t0 < setcontrolInput*`K1_25_NS*10/256-setcontrolInput*`K1_25_NS*10/256*0.01) begin       \n                                          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:100: Define or directive not defined: \'`K1_25_NS\'\n   if($time-t0 < setcontrolInput*`K1_25_NS*10/256-setcontrolInput*`K1_25_NS*10/256*0.01) begin       \n                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:101: Define or directive not defined: \'`K1_25_NS\'\n    $display("pulse: ERROR: pwm pulse > 1 %% shorter than expected, expected nominal %d ns, allowed accuracy +/- %d ns, actual pulselength: %d ns", setcontrolInput*`K1_25_NS*10/256, setcontrolInput*`K1_25_NS*10/256*1000*0.01, $time-t0);\n                                                                                                                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:101: Define or directive not defined: \'`K1_25_NS\'\n    $display("pulse: ERROR: pwm pulse > 1 %% shorter than expected, expected nominal %d ns, allowed accuracy +/- %d ns, actual pulselength: %d ns", setcontrolInput*`K1_25_NS*10/256, setcontrolInput*`K1_25_NS*10/256*1000*0.01, $time-t0);\n                                                                                                                                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:109: syntax error, unexpected $write\n     $write(".");\n     ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n     progress = progress + 1;\n              ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:114: Define or directive not defined: \'`K1_25_NS\'\n    if($time-t0 > `K1_25_NS*10+`K1_25_NS*10*0.01) begin      \n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:114: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    if($time-t0 > `K1_25_NS*10+`K1_25_NS*10*0.01) begin      \n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:114: Define or directive not defined: \'`K1_25_NS\'\n    if($time-t0 > `K1_25_NS*10+`K1_25_NS*10*0.01) begin      \n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:115: Define or directive not defined: \'`K1_25_NS\'\n     $display("pwm: ERROR: pwm cycle length was more than 1 %% longer than expected nominal: %d ns, allowed minimum: %d ns, breaking at %d ns", `K1_25_NS*10, `K1_25_NS*10*0.01, $time-t0);\n                                                                                                                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:115: Define or directive not defined: \'`K1_25_NS\'\n     $display("pwm: ERROR: pwm cycle length was more than 1 %% longer than expected nominal: %d ns, allowed minimum: %d ns, breaking at %d ns", `K1_25_NS*10, `K1_25_NS*10*0.01, $time-t0);\n                                                                                                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:121: Define or directive not defined: \'`K1_25_NS\'\n   if($time-t0 < `K1_25_NS*10-`K1_25_NS*10*0.01) begin       \n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:121: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   if($time-t0 < `K1_25_NS*10-`K1_25_NS*10*0.01) begin       \n                          ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:121: Define or directive not defined: \'`K1_25_NS\'\n   if($time-t0 < `K1_25_NS*10-`K1_25_NS*10*0.01) begin       \n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:122: Define or directive not defined: \'`K1_25_NS\'\n    $display("pwm: ERROR: pwm cycle length > 1 %% shorter than expected, expected nominal %d ns, allowed minimum: %d ns, actual pulselength: %d ns", `K1_25_NS*10, `K1_25_NS*10-`K1_25_NS*10*0.01, $time-t0);\n                                                                                                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:122: Define or directive not defined: \'`K1_25_NS\'\n    $display("pwm: ERROR: pwm cycle length > 1 %% shorter than expected, expected nominal %d ns, allowed minimum: %d ns, actual pulselength: %d ns", `K1_25_NS*10, `K1_25_NS*10-`K1_25_NS*10*0.01, $time-t0);\n                                                                                                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:122: Define or directive not defined: \'`K1_25_NS\'\n    $display("pwm: ERROR: pwm cycle length > 1 %% shorter than expected, expected nominal %d ns, allowed minimum: %d ns, actual pulselength: %d ns", `K1_25_NS*10, `K1_25_NS*10-`K1_25_NS*10*0.01, $time-t0);\n                                                                                                                                                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm_TB.v:132: Define or directive not defined: \'`US_NS\'\n   #(`US_NS);\n     ^~~~~~\n%Error: Cannot continue\n'
module pwm_TB ();
	reg[7:0] controlInput;
	reg load;
	wire masterClk;
	wire pwmOut;

	integer setcontrolInput, t0, progress, i;

	pwm #(.PRESCALE(`SIMPRESCALE)) DUT(.controlInput(controlInput), .load(load), .masterClk(masterClk), .pwmOut(pwmOut));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());
	
	initial begin
		$display("pwm: Running simulation for a pwm generator @ 125 Hz");
		$display("pwm: Initializing simulation for WS2811Decoder");


		load = 1'b0;
		#(`US_NS);
		controlInput=8'h00;
		#(`US_NS);
		load = 1'b1;
		#(`US_NS);
		load = 1'b0;
		#(`US_NS);


		$display("pwm: Running TC-1A: Sweeping all pwm duty-cycles from 1 to 255 with increments of 16, expected +/- 1 %% accuarcy");
		controlInput=8'h01;
		#(`US_NS);
		for(setcontrolInput=1; setcontrolInput<256; setcontrolInput=setcontrolInput+16) begin
			$display("pwm: INFO: Simulating PWM duty cycle %d %%", setcontrolInput*100/256 );
			load=1'b1;
			t0 = $time;
			#10;
			while (pwmOut != 1'b0) begin
				#1;
				if($time - t0 > 1000*`MS_NS/125*1.01) begin
					$display("pwm: ERROR: pwm did not trigger as expected");
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			t0 = $time;
			while (pwmOut != 1'b1) begin
				#1;
				if($time - t0 > 1000*`MS_NS/125*1.01) begin
					$display("pwm: ERROR: pwm did not trigger as expected");
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			t0 = $time;

			progress = 0;
			while (pwmOut != 1'b0) begin
				#1;
				if (progress == 1000000) begin
					$write(".");
					progress = 0;
				end
				else
					progress = progress + 1;

				if($time-t0 > setcontrolInput*`K1_25_NS*`SIMPRESCALE/256+setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01) begin
					$display("pwm: ERROR: pwm pulse length was more than 1 %% longer than expected nominal: %d ns, allowed accuracy +/- %d ns, breaking at %d ns", setcontrolInput*`K1_25_NS*`SIMPRESCALE/256, setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01, $time-t0);
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			$display("");
			if($time-t0 < setcontrolInput*`K1_25_NS*`SIMPRESCALE/256-setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01) begin
				$display("pulse: ERROR: pwm pulse > 1 %% shorter than expected, expected nominal %d ns, allowed accuracy +/- %d ns, actual pulselength: %d ns", setcontrolInput*`K1_25_NS*`SIMPRESCALE/256, setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*1000*0.01, $time-t0);
				$display("pulse: ERROR: stopping simulation...");
				$stop;
			end

			while (pwmOut != 1'b1) begin
				#1;
				if (progress == 1000000) begin
					$write(".");
					progress = 0;
				end
				else
					progress = progress + 1;
				if($time-t0 > `K1_25_NS*`SIMPRESCALE+`K1_25_NS*`SIMPRESCALE*0.01) begin
					$display("pwm: ERROR: pwm cycle length was more than 1 %% longer than expected nominal: %d ns, allowed minimum: %d ns, breaking at %d ns", `K1_25_NS*`SIMPRESCALE, `K1_25_NS*`SIMPRESCALE*0.01, $time-t0);
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			$display("");
			if($time-t0 < `K1_25_NS*`SIMPRESCALE-`K1_25_NS*`SIMPRESCALE*0.01) begin
				$display("pwm: ERROR: pwm cycle length > 1 %% shorter than expected, expected nominal %d ns, allowed minimum: %d ns, actual pulselength: %d ns", `K1_25_NS*`SIMPRESCALE, `K1_25_NS*`SIMPRESCALE-`K1_25_NS*`SIMPRESCALE*0.01, $time-t0);
				$display("pwm: ERROR: stopping simulation...");
				$stop;
			end
			t0 = $time;


			$display("pwm: PASS: pwm duty cycle and repitition was as expected (+/- 1 %%), duty-cycle: %d percent", setcontrolInput*100/256);
			controlInput = controlInput + 8'h10;
			load <= 1'b0;
			#(`US_NS);
		end
		$display("pwm: PASS TC-1A: Sweeping all pwm duty-cycles from 1 to 255 with increments of 16, expected +/- 1 %% accuarcy has passed");
		$stop;
	end
endmodule
module pwm_TB ();

	reg[7:0] controlInput;
	reg load;
	wire masterClk;
	wire pwmOut;

	integer setcontrolInput, t0, progress, i;

	pwm #(.PRESCALE(`SIMPRESCALE)) DUT(.controlInput(controlInput), .load(load), .masterClk(masterClk), .pwmOut(pwmOut));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());
	
	initial begin
		$display("pwm: Running simulation for a pwm generator @ 125 Hz");
		$display("pwm: Initializing simulation for WS2811Decoder");


		load = 1'b0;
		#(`US_NS);
		controlInput=8'h00;
		#(`US_NS);
		load = 1'b1;
		#(`US_NS);
		load = 1'b0;
		#(`US_NS);


		$display("pwm: Running TC-1A: Sweeping all pwm duty-cycles from 1 to 255 with increments of 16, expected +/- 1 %% accuarcy");
		controlInput=8'h01;
		#(`US_NS);
		for(setcontrolInput=1; setcontrolInput<256; setcontrolInput=setcontrolInput+16) begin
			$display("pwm: INFO: Simulating PWM duty cycle %d %%", setcontrolInput*100/256 );
			load=1'b1;
			t0 = $time;
			#10;
			while (pwmOut != 1'b0) begin
				#1;
				if($time - t0 > 1000*`MS_NS/125*1.01) begin
					$display("pwm: ERROR: pwm did not trigger as expected");
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			t0 = $time;
			while (pwmOut != 1'b1) begin
				#1;
				if($time - t0 > 1000*`MS_NS/125*1.01) begin
					$display("pwm: ERROR: pwm did not trigger as expected");
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			t0 = $time;

			progress = 0;
			while (pwmOut != 1'b0) begin
				#1;
				if (progress == 1000000) begin
					$write(".");
					progress = 0;
				end
				else
					progress = progress + 1;

				if($time-t0 > setcontrolInput*`K1_25_NS*`SIMPRESCALE/256+setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01) begin
					$display("pwm: ERROR: pwm pulse length was more than 1 %% longer than expected nominal: %d ns, allowed accuracy +/- %d ns, breaking at %d ns", setcontrolInput*`K1_25_NS*`SIMPRESCALE/256, setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01, $time-t0);
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			$display("");
			if($time-t0 < setcontrolInput*`K1_25_NS*`SIMPRESCALE/256-setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*0.01) begin
				$display("pulse: ERROR: pwm pulse > 1 %% shorter than expected, expected nominal %d ns, allowed accuracy +/- %d ns, actual pulselength: %d ns", setcontrolInput*`K1_25_NS*`SIMPRESCALE/256, setcontrolInput*`K1_25_NS*`SIMPRESCALE/256*1000*0.01, $time-t0);
				$display("pulse: ERROR: stopping simulation...");
				$stop;
			end

			while (pwmOut != 1'b1) begin
				#1;
				if (progress == 1000000) begin
					$write(".");
					progress = 0;
				end
				else
					progress = progress + 1;
				if($time-t0 > `K1_25_NS*`SIMPRESCALE+`K1_25_NS*`SIMPRESCALE*0.01) begin
					$display("pwm: ERROR: pwm cycle length was more than 1 %% longer than expected nominal: %d ns, allowed minimum: %d ns, breaking at %d ns", `K1_25_NS*`SIMPRESCALE, `K1_25_NS*`SIMPRESCALE*0.01, $time-t0);
					$display("pwm: ERROR: stopping simulation...");
					$stop;
				end
			end
			$display("");
			if($time-t0 < `K1_25_NS*`SIMPRESCALE-`K1_25_NS*`SIMPRESCALE*0.01) begin
				$display("pwm: ERROR: pwm cycle length > 1 %% shorter than expected, expected nominal %d ns, allowed minimum: %d ns, actual pulselength: %d ns", `K1_25_NS*`SIMPRESCALE, `K1_25_NS*`SIMPRESCALE-`K1_25_NS*`SIMPRESCALE*0.01, $time-t0);
				$display("pwm: ERROR: stopping simulation...");
				$stop;
			end
			t0 = $time;


			$display("pwm: PASS: pwm duty cycle and repitition was as expected (+/- 1 %%), duty-cycle: %d percent", setcontrolInput*100/256);
			controlInput = controlInput + 8'h10;
			load <= 1'b0;
			#(`US_NS);
		end
		$display("pwm: PASS TC-1A: Sweeping all pwm duty-cycles from 1 to 255 with increments of 16, expected +/- 1 %% accuarcy has passed");
		$stop;
	end
endmodule