data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_DECODE_8U_3_4.v
data/verilator_xmls/8f7854e5-ac67-46df-9fee-9b912db6ee49.xml
module dut_DECODE_8U_3_4 (
	in1,
	out1
	);
input [2:0] in1;
output [7:0] out1;
wire [7:0] asc001;

assign asc001 = 8'B00000001 << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_8U_3_4 (
	in1,
	out1
	);

input [2:0] in1;
output [7:0] out1;
wire [7:0] asc001;

assign asc001 = 8'B00000001 << in1;

assign out1 = asc001;
endmodule