data/full_repos/permissive/417288846/List_3/Task_3/stoper_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_3/stoper_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_3/stoper_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_3/stoper_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        repeat(16000) #1 clk = ~clk;\n                      ^\n%Error: data/full_repos/permissive/417288846/List_3/Task_3/stoper_tb.v:20: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " %d%d:%d%d", num[15:12],  num[11:8], num[7:4], num[3:0]);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    wire [15:0] num;
    reg clk, rst;

    stoper s1(.clk(clk), .rst(rst), .num(num));

    initial begin
        rst = 0;
        clk = 0;
        #1 rst = 1;
        #1 rst = 0;

        repeat(16000) #1 clk = ~clk;

    end

    initial $monitor ($time, " %d%d:%d%d", num[15:12],  num[11:8], num[7:4], num[3:0]);
endmodule
module testbench;

    wire [15:0] num;
    reg clk, rst;

    stoper s1(.clk(clk), .rst(rst), .num(num));

    initial begin
        rst = 0;
        clk = 0;
        #1 rst = 1;
        #1 rst = 0;

        repeat(16000) #1 clk = ~clk;

    end

    initial $monitor ($time, " %d%d:%d%d", num[15:12],  num[11:8], num[7:4], num[3:0]);
endmodule