data/full_repos/permissive/491135068/cpu5.v
1: b"%Error: data/full_repos/permissive/491135068/cpu5.v:64: Cannot find file containing module: 'PC_pipe'\n    PC_pipe PC(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/PC_pipe\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/PC_pipe.v\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/PC_pipe.sv\n             PC_pipe\n             PC_pipe.v\n             PC_pipe.sv\n             obj_dir/PC_pipe\n             obj_dir/PC_pipe.v\n             obj_dir/PC_pipe.sv\n%Error: data/full_repos/permissive/491135068/cpu5.v:71: Cannot find file containing module: 'adder32'\n    adder32 PCplus4Adder(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:77: Cannot find file containing module: 'IF_ID'\n    IF_ID ifid_pipeline(\n    ^~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:89: Cannot find file containing module: 'mux'\n    mux branchMux(\n    ^~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:96: Cannot find file containing module: 'leftShift2Module'\n    leftShift2Module left2(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:101: Cannot find file containing module: 'adder32'\n    adder32 branchAddrAdder(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:107: Cannot find file containing module: 'equalityModule'\n    equalityModule eqMod(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:118: Cannot find file containing module: 'decoder'\n    decoder rsDecoder(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:123: Cannot find file containing module: 'decoder'\n    decoder rtDecoder(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:128: Cannot find file containing module: 'decoder'\n    decoder rdDecoder(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:133: Cannot find file containing module: 'opcode_decoder'\n    opcode_decoder opDecoder(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:147: Cannot find file containing module: 'signExt'\n    signExt sign_extender(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:152: Cannot find file containing module: 'mux'\n    mux ID_Mux(\n    ^~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:159: Cannot find file containing module: 'regfile'\n    regfile register_file(\n    ^~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:173: Cannot find file containing module: 'ID_EX'\n    ID_EX idex_pipeline(\n    ^~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:203: Cannot find file containing module: 'alu32'\n    alu32 ALU(\n    ^~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:213: Cannot find file containing module: 'mux'\n    mux EX_Mux(\n    ^~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:220: Cannot find file containing module: 'comparisonModule'\n    comparisonModule compMod(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:228: Cannot find file containing module: 'mux'\n    mux compMux(\n    ^~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:239: Cannot find file containing module: 'EX_MEM'\n    EX_MEM exmem_pipeline(\n    ^~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:257: Cannot find file containing module: 'triStateBuffer32'\n    triStateBuffer32 databusBuff(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:267: Cannot find file containing module: 'MEM_WB'\n    MEM_WB memwb_pipeline(\n    ^~~~~~\n%Error: data/full_repos/permissive/491135068/cpu5.v:284: Cannot find file containing module: 'mux'\n    mux WB_LoadMux(\n    ^~~\n%Error: Exiting due to 23 error(s)\n"
module cpu5(
    input reset,
    input clk,
    input [31:0] ibus,
    inout [31:0] databus,
    output [31:0] iaddrbus,
    output [31:0] daddrbus
    );
    
    wire
    IDimm, IDcin, IDstore, IDload, eqOut,
    IDset, IDeq, IDeqType, EXset, ALUZ2comp,
    ALUCOUT2comp;
    
    wire [1:0]
    IDsetType, EXsetType;
    
    wire [2:0]
    ID_S, EX_S;
    
    wire[31:0] 

    IFpcplus4, branchMux2PC,

    instrBus2Decoders, Aselect, Bselect, destReg,
    IDextended, IDdselect, IDabus2eq, IDbbus2eq, 
    pcplus4plusbranch, IDeqabus2idex, IDeqbbus2idex,
    IDpcplus4, lshifttwo2adder, Abus2idex, Bbus2idex,

    EXabus, EXbbus, EXboperand, EXextended, EXimm, 
    EXcin, EXstore, EXload, EXdselect, EXdbus2comp,
    compDbus2exmem, compDbus2mux,

    MEMload, MEMstore, MEMdselect, MEMboperand,

    WBdselect, WBdbus, WBload, WBdatabus, regdbus;





    PC_pipe PC(
        .branchIn(branchMux2PC),
        .val(iaddrbus),
        .clk(clk),
        .rst(reset)
    );
    
    adder32 PCplus4Adder(
        .a(32'd4),
        .b(iaddrbus),
        .out(IFpcplus4)
    );
    
    IF_ID ifid_pipeline(
        .clk(clk),
        .ibus(ibus),
        .instruction(instrBus2Decoders),
        .pcPlus4ValIn(IFpcplus4),
        .pcPlus4ValOut(IDpcplus4)
    );
    



    
    mux branchMux(
        .a(pcplus4plusbranch),
        .b(IFpcplus4),
        .sel(eqOut),
        .out(branchMux2PC)
    );
    
    leftShift2Module left2(
        .in(IDextended),
        .out(lshifttwo2adder)
    );
    
    adder32 branchAddrAdder(
        .a(lshifttwo2adder),
        .b(IDpcplus4),
        .out(pcplus4plusbranch)
    );

    equalityModule eqMod(
        .AvalIn(IDabus2eq),
        .BvalIn(IDbbus2eq),
        .AvalOut(IDeqabus2idex),
        .BvalOut(IDeqbbus2idex),
        .eq(IDeq),
        .eqType(IDeqType),
        .eqResult(eqOut),
        .clk(clk)
    );
    
    decoder rsDecoder(
        .r_in(instrBus2Decoders[26:21]),
        .r_out(Aselect)
    );
    
    decoder rtDecoder(
        .r_in(instrBus2Decoders[20:16]),
        .r_out(Bselect)
    );
    
    decoder rdDecoder(
        .r_in(instrBus2Decoders[15:11]),
        .r_out(destReg)
    );

    opcode_decoder opDecoder(
        .ibus_opcode(instrBus2Decoders[31:26]),
        .funct(instrBus2Decoders[5:0]),
        .imm(IDimm),
        .Cin(IDcin),
        .store(IDstore),
        .load(IDload),
        .S(ID_S),
        .set(IDset),
        .eq(IDeq),
        .eqType(IDeqType),
        .setType(IDsetType)
    );

    signExt sign_extender(
        .unex(instrBus2Decoders[15:0]),
        .ext(IDextended)
    );
    
    mux ID_Mux(
        .a(Bselect),
        .b(destReg),
        .sel(IDimm),
        .out(IDdselect)
    );
    
    regfile register_file(
        .Aselect(Aselect),
        .Bselect(Bselect),
        .Dselect(WBdselect),
        .abus(IDabus2eq),
        .bbus(IDbbus2eq),
        .dbus(regdbus),
        .clk(clk)
    );
    




    ID_EX idex_pipeline(
        .dselIn(IDdselect),
        .dSelOut(EXdselect),
        .abus_in(IDeqabus2idex),
        .abus_out(EXabus),
        .bbus_in(IDeqbbus2idex),
        .bbus_out(EXboperand),
        .signExt_in(IDextended),
        .signExt_out(EXextended),
        .imm_in(IDimm),
        .imm_out(EXimm),
        .Cin_in(IDcin),
        .Cin_out(EXcin),
        .S_in(ID_S),
        .S_out(EX_S),
        .storeValIn(IDstore),
        .storeValOut(EXstore),
        .loadValIn(IDload),
        .loadValOut(EXload),
        .setValIn(IDset),
        .setValOut(EXset),
        .setValTypeIn(IDsetType),
        .setValTypeOut(EXsetType),
        .clk(clk)
    );
    




    alu32 ALU(
        .a(EXabus),
        .b(EXbbus),
        .d(EXdbus2comp),
        .S(EX_S),
        .Cin(EXcin),
        .Z(ALUZ2comp),
        .Cout(ALUCOUT2comp)
    );
    
    mux EX_Mux(
        .a(EXextended),
        .b(EXboperand),
        .sel(EXimm),
        .out(EXbbus)
    );
    
    comparisonModule compMod(
        .compInput(EXdbus2comp),
        .compOut(compDbus2mux),
        .C(ALUCOUT2comp),
        .Z(ALUZ2comp),
        .setType(EXsetType)
    );
    
    mux compMux(
        .a(compDbus2mux),
        .b(EXdbus2comp),
        .sel(EXset),
        .out(compDbus2exmem)
    );
    



    
    EX_MEM exmem_pipeline(
        .bOperandIn(EXboperand),
        .bOperandOut(MEMboperand),
        .dbusIn(compDbus2exmem),
        .dbusOut(daddrbus),
        .dSelIn(EXdselect),
        .dSelOut(MEMdselect),
        .storeValIn(EXstore),
        .storeValOut(MEMstore),
        .loadValIn(EXload),
        .loadValOut(MEMload),
        .clk(clk)
    );
    



    
    triStateBuffer32 databusBuff(
        .Q(MEMboperand),
        .select(MEMstore),
        .bus(databus)
    );
    



    
    MEM_WB memwb_pipeline(
        .dbusIn(daddrbus),
        .dbusOut(WBdbus),
        .databusIn(databus),
        .databusOut(WBdatabus),
        .DselIn(MEMdselect),
        .DselOut(WBdselect),
        .loadIn(MEMload),
        .loadOut(WBload),
        .storeIn(MEMstore),
        .clk(clk)
    );
    



    
    mux WB_LoadMux(
        .a(WBdatabus),
        .b(WBdbus),
        .sel(WBload),
        .out(regdbus)
    );
    



    
    
endmodule
module cpu5(
    input reset,
    input clk,
    input [31:0] ibus,
    inout [31:0] databus,
    output [31:0] iaddrbus,
    output [31:0] daddrbus
    );

    
    wire
    IDimm, IDcin, IDstore, IDload, eqOut,
    IDset, IDeq, IDeqType, EXset, ALUZ2comp,
    ALUCOUT2comp;
    
    wire [1:0]
    IDsetType, EXsetType;
    
    wire [2:0]
    ID_S, EX_S;
    
    wire[31:0] 

    IFpcplus4, branchMux2PC,

    instrBus2Decoders, Aselect, Bselect, destReg,
    IDextended, IDdselect, IDabus2eq, IDbbus2eq, 
    pcplus4plusbranch, IDeqabus2idex, IDeqbbus2idex,
    IDpcplus4, lshifttwo2adder, Abus2idex, Bbus2idex,

    EXabus, EXbbus, EXboperand, EXextended, EXimm, 
    EXcin, EXstore, EXload, EXdselect, EXdbus2comp,
    compDbus2exmem, compDbus2mux,

    MEMload, MEMstore, MEMdselect, MEMboperand,

    WBdselect, WBdbus, WBload, WBdatabus, regdbus;





    PC_pipe PC(
        .branchIn(branchMux2PC),
        .val(iaddrbus),
        .clk(clk),
        .rst(reset)
    );
    
    adder32 PCplus4Adder(
        .a(32'd4),
        .b(iaddrbus),
        .out(IFpcplus4)
    );
    
    IF_ID ifid_pipeline(
        .clk(clk),
        .ibus(ibus),
        .instruction(instrBus2Decoders),
        .pcPlus4ValIn(IFpcplus4),
        .pcPlus4ValOut(IDpcplus4)
    );
    



    
    mux branchMux(
        .a(pcplus4plusbranch),
        .b(IFpcplus4),
        .sel(eqOut),
        .out(branchMux2PC)
    );
    
    leftShift2Module left2(
        .in(IDextended),
        .out(lshifttwo2adder)
    );
    
    adder32 branchAddrAdder(
        .a(lshifttwo2adder),
        .b(IDpcplus4),
        .out(pcplus4plusbranch)
    );

    equalityModule eqMod(
        .AvalIn(IDabus2eq),
        .BvalIn(IDbbus2eq),
        .AvalOut(IDeqabus2idex),
        .BvalOut(IDeqbbus2idex),
        .eq(IDeq),
        .eqType(IDeqType),
        .eqResult(eqOut),
        .clk(clk)
    );
    
    decoder rsDecoder(
        .r_in(instrBus2Decoders[26:21]),
        .r_out(Aselect)
    );
    
    decoder rtDecoder(
        .r_in(instrBus2Decoders[20:16]),
        .r_out(Bselect)
    );
    
    decoder rdDecoder(
        .r_in(instrBus2Decoders[15:11]),
        .r_out(destReg)
    );

    opcode_decoder opDecoder(
        .ibus_opcode(instrBus2Decoders[31:26]),
        .funct(instrBus2Decoders[5:0]),
        .imm(IDimm),
        .Cin(IDcin),
        .store(IDstore),
        .load(IDload),
        .S(ID_S),
        .set(IDset),
        .eq(IDeq),
        .eqType(IDeqType),
        .setType(IDsetType)
    );

    signExt sign_extender(
        .unex(instrBus2Decoders[15:0]),
        .ext(IDextended)
    );
    
    mux ID_Mux(
        .a(Bselect),
        .b(destReg),
        .sel(IDimm),
        .out(IDdselect)
    );
    
    regfile register_file(
        .Aselect(Aselect),
        .Bselect(Bselect),
        .Dselect(WBdselect),
        .abus(IDabus2eq),
        .bbus(IDbbus2eq),
        .dbus(regdbus),
        .clk(clk)
    );
    




    ID_EX idex_pipeline(
        .dselIn(IDdselect),
        .dSelOut(EXdselect),
        .abus_in(IDeqabus2idex),
        .abus_out(EXabus),
        .bbus_in(IDeqbbus2idex),
        .bbus_out(EXboperand),
        .signExt_in(IDextended),
        .signExt_out(EXextended),
        .imm_in(IDimm),
        .imm_out(EXimm),
        .Cin_in(IDcin),
        .Cin_out(EXcin),
        .S_in(ID_S),
        .S_out(EX_S),
        .storeValIn(IDstore),
        .storeValOut(EXstore),
        .loadValIn(IDload),
        .loadValOut(EXload),
        .setValIn(IDset),
        .setValOut(EXset),
        .setValTypeIn(IDsetType),
        .setValTypeOut(EXsetType),
        .clk(clk)
    );
    




    alu32 ALU(
        .a(EXabus),
        .b(EXbbus),
        .d(EXdbus2comp),
        .S(EX_S),
        .Cin(EXcin),
        .Z(ALUZ2comp),
        .Cout(ALUCOUT2comp)
    );
    
    mux EX_Mux(
        .a(EXextended),
        .b(EXboperand),
        .sel(EXimm),
        .out(EXbbus)
    );
    
    comparisonModule compMod(
        .compInput(EXdbus2comp),
        .compOut(compDbus2mux),
        .C(ALUCOUT2comp),
        .Z(ALUZ2comp),
        .setType(EXsetType)
    );
    
    mux compMux(
        .a(compDbus2mux),
        .b(EXdbus2comp),
        .sel(EXset),
        .out(compDbus2exmem)
    );
    



    
    EX_MEM exmem_pipeline(
        .bOperandIn(EXboperand),
        .bOperandOut(MEMboperand),
        .dbusIn(compDbus2exmem),
        .dbusOut(daddrbus),
        .dSelIn(EXdselect),
        .dSelOut(MEMdselect),
        .storeValIn(EXstore),
        .storeValOut(MEMstore),
        .loadValIn(EXload),
        .loadValOut(MEMload),
        .clk(clk)
    );
    



    
    triStateBuffer32 databusBuff(
        .Q(MEMboperand),
        .select(MEMstore),
        .bus(databus)
    );
    



    
    MEM_WB memwb_pipeline(
        .dbusIn(daddrbus),
        .dbusOut(WBdbus),
        .databusIn(databus),
        .databusOut(WBdatabus),
        .DselIn(MEMdselect),
        .DselOut(WBdselect),
        .loadIn(MEMload),
        .loadOut(WBload),
        .storeIn(MEMstore),
        .clk(clk)
    );
    



    
    mux WB_LoadMux(
        .a(WBdatabus),
        .b(WBdbus),
        .sel(WBload),
        .out(regdbus)
    );
    



    
    
endmodule