data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_2/bin2bcd_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_2,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_2/bin2bcd_TB.v\n%Error: Exiting due to 5 error(s)\n'
module bin2bcd_TB;

	reg  [7:0] bin_in;
	wire [7:0] bcd_out;

	bin2bcd DUT(.bin_in(bin_in), .bcd_out(bcd_out));

	integer i;
	
	initial begin
		for(i = 0; i < 60; i = i + 1) begin
			bin_in = i;
			#2;
		end
	end

	initial begin
		$dumpfile("bin2bcd_TB.vcd") ;
		$dumpvars(0, bin2bcd_TB) ;
    end

endmodule
module bin2bcd_TB;


	reg  [7:0] bin_in;
	wire [7:0] bcd_out;

	bin2bcd DUT(.bin_in(bin_in), .bcd_out(bcd_out));

	integer i;
	
	initial begin
		for(i = 0; i < 60; i = i + 1) begin
			bin_in = i;
			#2;
		end
	end

	initial begin
		$dumpfile("bin2bcd_TB.vcd") ;
		$dumpvars(0, bin2bcd_TB) ;
    end

endmodule