data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v
1: b'%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:18: Cannot find include file: puf_top.v\n`include "puf_top.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/puf_top.v\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/puf_top.v.v\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/puf_top.v.sv\n             puf_top.v\n             puf_top.v.v\n             puf_top.v.sv\n             obj_dir/puf_top.v\n             obj_dir/puf_top.v.v\n             obj_dir/puf_top.v.sv\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:19: Cannot find include file: design.lvs.v\n`include "design.lvs.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:76: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:76: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:77: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:77: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:78: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:78: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:79: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:79: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:96: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:96: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:97: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:97: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:105: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`ANALOG_PADS-1:0] io_analog,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:128: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:128: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:129: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:129: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:130: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/user_analog_project_wrapper.v:130: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n                        ^~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module user_analog_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,



    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,


    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] user_irq
);




    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [127:0] la_data_out;

    wire out_top;
    wire so_top;
    
    assign io_out[25] = out_top;
    assign la_data_out[0] = out_top;
    assign la_data_out[1] = so_top;

    puf_top puf_top_0 (
        `ifdef USE_POWER_PINS
            .vccd2(vccd2),
            .vssd2(vssd2),
        `endif
        .reset(io_in[26]),
        .puf_sel(io_in[22:23]),
        .clk(io_in[21]),
        .si(io_in[20]),
        .rstn(io_in[19]),
        .length(io_in[17:18]),
        .out(out_top),
        .so(so_top)
    );

    

endmodule
module user_analog_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,



    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,


    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] user_irq
);





    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [127:0] la_data_out;

    wire out_top;
    wire so_top;
    
    assign io_out[25] = out_top;
    assign la_data_out[0] = out_top;
    assign la_data_out[1] = so_top;

    puf_top puf_top_0 (
        `ifdef USE_POWER_PINS
            .vccd2(vccd2),
            .vssd2(vssd2),
        `endif
        .reset(io_in[26]),
        .puf_sel(io_in[22:23]),
        .clk(io_in[21]),
        .si(io_in[20]),
        .rstn(io_in[19]),
        .length(io_in[17:18]),
        .out(out_top),
        .so(so_top)
    );

    

endmodule