data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:120: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'A112\' generates 4 bits.\n                                                                                                                                    : ... In instance mod7681\nassign S1 = A111 + A112 + A12;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:120: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'A12\' generates 4 bits.\n                                                                                                                                    : ... In instance mod7681\nassign S1 = A111 + A112 + A12;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:121: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'A2\' generates 13 bits.\n                                                                                                                                    : ... In instance mod7681\nassign S2 = {S1,9\'d0} + A2;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:126: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'A111\' generates 5 bits.\n                                                                                                                                    : ... In instance mod7681\nassign M1 = A111 + A11;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:127: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'M1\' generates 10 bits.\n                                                                                                                                    : ... In instance mod7681\nassign M2 = A1 + M1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:131: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'M2\' generates 14 bits.\n                                                                                                                                    : ... In instance mod7681\nassign R = S2 - M2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:136: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'13\'h1e01\' generates 13 bits.\n                                                                                                                                    : ... In instance mod7681\nassign w2 = R[15:0] - 13\'d7681;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/mod7681.v:137: Operator SUB expects 16 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n                                                                                                                                    : ... In instance mod7681\nassign w3 = R[15:0] - {13\'d7681,1\'b0};\n                    ^\n%Error: Exiting due to 8 warning(s)\n'
module mod7681(A, B);
input [25:0] A;
output [12:0] B;

wire [12:0] A1, A2;
wire [8:0] A11;
wire [3:0] A12, A112;
wire [4:0] A111;

assign A1 = A[25:13];
assign A2 = A[12:0];
assign A11 = A1[12:4];
assign A12 = A1[3:0];
assign A112 = A11[3:0];
assign A111 = A11[8:4];

wire [5:0] S1;
wire [15:0] S2;

assign S1 = A111 + A112 + A12;
assign S2 = {S1,9'd0} + A2;

wire [9:0] M1;
wire [13:0] M2;

assign M1 = A111 + A11;
assign M2 = A1 + M1;

wire [16:0] R;

assign R = S2 - M2;

wire [12:0] w1;
wire [15:0] w5, w4, w3, w2;
assign w1 = `p + R[12:0];
assign w2 = R[15:0] - `p;
assign w3 = R[15:0] - {`p,1'b0};
assign w4 = R[15:0] - 15'd23043;
assign w5 = R[15:0] - {`p,2'b0};

assign B =   (R[16]==1'b1) ? w1[12:0]
				:(w5[15]==1'b0) ? w5[12:0]
				:(w4[15]==1'b0) ? w4[12:0]
				:(w3[15]==1'b0) ? w3[12:0]
				:(w2[15]==1'b0) ? w2[12:0]
				:R[12:0];	
endmodule
module mod7681(A, B);

input [25:0] A;
output [12:0] B;

wire [12:0] A1, A2;
wire [8:0] A11;
wire [3:0] A12, A112;
wire [4:0] A111;

assign A1 = A[25:13];
assign A2 = A[12:0];
assign A11 = A1[12:4];
assign A12 = A1[3:0];
assign A112 = A11[3:0];
assign A111 = A11[8:4];

wire [5:0] S1;
wire [15:0] S2;

assign S1 = A111 + A112 + A12;
assign S2 = {S1,9'd0} + A2;

wire [9:0] M1;
wire [13:0] M2;

assign M1 = A111 + A11;
assign M2 = A1 + M1;

wire [16:0] R;

assign R = S2 - M2;

wire [12:0] w1;
wire [15:0] w5, w4, w3, w2;
assign w1 = `p + R[12:0];
assign w2 = R[15:0] - `p;
assign w3 = R[15:0] - {`p,1'b0};
assign w4 = R[15:0] - 15'd23043;
assign w5 = R[15:0] - {`p,2'b0};

assign B =   (R[16]==1'b1) ? w1[12:0]
				:(w5[15]==1'b0) ? w5[12:0]
				:(w4[15]==1'b0) ? w4[12:0]
				:(w3[15]==1'b0) ? w3[12:0]
				:(w2[15]==1'b0) ? w2[12:0]
				:R[12:0];	
endmodule