data/full_repos/permissive/426029503/character.v
1: b'%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:38: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                                   : ... In instance character\n       speed = 4\'d4;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:39: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h5\' generates 5 bits.\n                                                                   : ... In instance character\n       dodge = 5\'d5;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:40: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                   : ... In instance character\n       maxSpecial = 4\'d8;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:46: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                                   : ... In instance character\n       speed = 4\'d6;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:47: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h7\' generates 5 bits.\n                                                                   : ... In instance character\n       dodge = 5\'d7;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:48: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                   : ... In instance character\n       maxSpecial = 4\'d10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:53: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                   : ... In instance character\n       speed = 4\'d2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:54: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h5\' generates 5 bits.\n                                                                   : ... In instance character\n       dodge = 5\'d5;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                   : ... In instance character\n       maxSpecial = 4\'d10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:60: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h7\' generates 4 bits.\n                                                                   : ... In instance character\n       speed = 4\'d7;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:61: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h7\' generates 5 bits.\n                                                                   : ... In instance character\n       dodge = 5\'d7;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:62: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                   : ... In instance character\n       maxSpecial = 4\'d8;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:80: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'damage\' generates 6 bits.\n                                                                   : ... In instance character\n             health <= health - damage;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/426029503/character.v:77: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'damage\' generates 6 bits.\n                                                                   : ... In instance character\n           if (health - damage > maxHealth) begin\n                      ^\n%Error: Exiting due to 14 warning(s)\n'
module character(
		  input update,
		  input en,
		  input rst,
		  input [2:0]i,
	     input [5:0]damage,
	     input [2:0]cost,
		  output reg [2:0]speed,
		  output reg [2:0]dodge,
		  output reg [8:0]health,
		  output reg [4:0]special,
		  output reg [2:0]color);
		  


		  
		  reg [8:0]maxHealth;
		  reg [4:0]maxSpecial;
		  
		  












		  
		  always @(*) begin
		      case(i) 
				    0: begin
					    maxHealth = 9'd175;
						 speed = 4'd4;
						 dodge = 5'd5;
						 maxSpecial = 4'd8;
						 color = 3'b110;
					 end
					    
					 1: begin
					    maxHealth = 9'd150;
						 speed = 4'd6;
						 dodge = 5'd7;
						 maxSpecial = 4'd10;
						 color = 3'b011;
					 end
					 2: begin
					    maxHealth = 9'd200;
						 speed = 4'd2;
						 dodge = 5'd5;
						 maxSpecial = 4'd10;
						 color = 3'b0;
					 end
					 default: begin
					    maxHealth = 9'd150;
						 speed = 4'd7;
						 dodge = 5'd7;
						 maxSpecial = 4'd8;
						 color = 3'b010;
					 end
			   endcase
		  end
		 
		  
		  
		  always@(posedge update or posedge rst) begin
		      if (rst == 1'b1) begin
				   health <= maxHealth;
					special <= maxSpecial;
				end else begin
		          if(en == 1'b1) begin
					      
							    if (health - damage > maxHealth) begin
								     health <= 0;
								 end else begin  
								     health <= health - damage;
								 end 
						 
					 end
				end
		  end
		
endmodule
module character(
		  input update,
		  input en,
		  input rst,
		  input [2:0]i,
	     input [5:0]damage,
	     input [2:0]cost,
		  output reg [2:0]speed,
		  output reg [2:0]dodge,
		  output reg [8:0]health,
		  output reg [4:0]special,
		  output reg [2:0]color);

		  


		  
		  reg [8:0]maxHealth;
		  reg [4:0]maxSpecial;
		  
		  












		  
		  always @(*) begin
		      case(i) 
				    0: begin
					    maxHealth = 9'd175;
						 speed = 4'd4;
						 dodge = 5'd5;
						 maxSpecial = 4'd8;
						 color = 3'b110;
					 end
					    
					 1: begin
					    maxHealth = 9'd150;
						 speed = 4'd6;
						 dodge = 5'd7;
						 maxSpecial = 4'd10;
						 color = 3'b011;
					 end
					 2: begin
					    maxHealth = 9'd200;
						 speed = 4'd2;
						 dodge = 5'd5;
						 maxSpecial = 4'd10;
						 color = 3'b0;
					 end
					 default: begin
					    maxHealth = 9'd150;
						 speed = 4'd7;
						 dodge = 5'd7;
						 maxSpecial = 4'd8;
						 color = 3'b010;
					 end
			   endcase
		  end
		 
		  
		  
		  always@(posedge update or posedge rst) begin
		      if (rst == 1'b1) begin
				   health <= maxHealth;
					special <= maxSpecial;
				end else begin
		          if(en == 1'b1) begin
					      
							    if (health - damage > maxHealth) begin
								     health <= 0;
								 end else begin  
								     health <= health - damage;
								 end 
						 
					 end
				end
		  end
		
endmodule