data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:75: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'XOR_SHR_DLO\'\nmodule XOR_SHR_DLO(\n       ^~~~~~~~~~~\n                                                                                              : ... Top module \'INV_SHR_DLO\'\nmodule INV_SHR_DLO(\n       ^~~~~~~~~~~\n                                                                                              : ... Top module \'AN_SHR_DLO\'\nmodule AN_SHR_DLO(\n       ^~~~~~~~~~\n                                                                                              : ... Top module \'OR_SHR_DLO\'\nmodule OR_SHR_DLO(\n       ^~~~~~~~~~\n                                                                                              : ... Top module \'REG_SHR_DLO\'\nmodule REG_SHR_DLO(\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:35: Cannot find file containing module: \'AO_DLO_D0\'\n  AO_DLO_D0 ao1(.CP(CP),  \n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/synth/synth_dlo,data/full_repos/permissive/514437299/AO_DLO_D0\n             data/full_repos/permissive/514437299/digital/synth/synth_dlo,data/full_repos/permissive/514437299/AO_DLO_D0.v\n             data/full_repos/permissive/514437299/digital/synth/synth_dlo,data/full_repos/permissive/514437299/AO_DLO_D0.sv\n             AO_DLO_D0\n             AO_DLO_D0.v\n             AO_DLO_D0.sv\n             obj_dir/AO_DLO_D0\n             obj_dir/AO_DLO_D0.v\n             obj_dir/AO_DLO_D0.sv\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:20: Cannot find file containing module: \'AO_DLO_D0\'\n  AO_DLO_D0 ao1( .CP(CP),\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:247: Cannot find file containing module: \'XOR2D0\'\n  XOR2D0 xor1(.A1(D_S0), .A2(R), .Z(X_S0));\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:248: Cannot find file containing module: \'XOR2D0\'\n  XOR2D0 xor2(.A1(D_S1), .A2(R), .Z(X_S1));\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:250: Cannot find file containing module: \'DFCND1\'\n  DFCND1 ff1(.CP(CP), .CDN(CDN), .D(X_S0), .Q(Q_S0), .QN(Q_S0N));\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:251: Cannot find file containing module: \'DFCND1\'\n  DFCND1 ff2(.CP(CP), .CDN(CDN), .D(X_S1), .Q(Q_S1), .QN(Q_S1N));\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:212: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor1(.CP(CP),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:226: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor2(.CP(CP),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:146: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor1(.CP(CP),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:160: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor2(.CP(CP),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:66: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor0(.CP(CP),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/synth/synth_dlo/gates_dlo.v:70: Cannot find file containing module: \'XOR_DLO_D0\'\n  XOR_DLO_D0 xor1(.CP(CP),\n  ^~~~~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module INV_SHR_DLO(
  input   wire I_S0,
  input   wire I_S1,
  output wire ZN_S0,
  output wire ZN_S1,

  input   wire I_S0N,
  input   wire I_S1N,
  output wire ZN_S0N,
  output wire ZN_S1N
);
  INV_XYZ_DLO inv1(
    .A1(I_S0),  .Z1(ZN_S0) ,
    .A2(I_S0N), .Z2(ZN_S0N));

  assign ZN_S1  = I_S1;
  assign ZN_S1N = I_S1N;
endmodule
module INV_SHR_DLO(
  input   wire I_S0,
  input   wire I_S1,
  output wire ZN_S0,
  output wire ZN_S1,

  input   wire I_S0N,
  input   wire I_S1N,
  output wire ZN_S0N,
  output wire ZN_S1N
);

  INV_XYZ_DLO inv1(
    .A1(I_S0),  .Z1(ZN_S0) ,
    .A2(I_S0N), .Z2(ZN_S0N));

  assign ZN_S1  = I_S1;
  assign ZN_S1N = I_S1N;
endmodule