data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Q3c FSM logic.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Q3c\n%Error: Cannot find file containing module: FSM\n%Error: Cannot find file containing module: logic.v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    always @(*) begin
        case(y)
            3'b000 , 3'b010 : Y0 = x ;
            default : Y0 = ~x ;
        endcase
    end
    
    assign z = (y == 3'b011 || y == 3'b100) ;

endmodule
module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    always @(*) begin
        case(y)
            3'b000 , 3'b010 : Y0 = x ;
            default : Y0 = ~x ;
        endcase
    end
    
    assign z = (y == 3'b011 || y == 3'b100) ;

endmodule