data/full_repos/permissive/48250786/subBytes.v
data/verilator_xmls/0344d871-dd27-4381-ae06-37f5eb414c28.xml
module subBytes(
	 output [7:0] dout,
	 input [7:0] add,
	 input clock,
	 input en,
	 input invbytes
    );
	 
	 reg [15:0] rom [0:255];
	 
	 reg [15:0] dout_in;
	 
	 initial begin
		$readmemh("subbytes.table", rom, 0, 255);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout_in <= rom[add];
		end
	 end
	 
	 assign dout = (invbytes)?(dout_in[7:0]):(dout_in[15:8]);

endmodule
module subBytes(
	 output [7:0] dout,
	 input [7:0] add,
	 input clock,
	 input en,
	 input invbytes
    );

	 
	 reg [15:0] rom [0:255];
	 
	 reg [15:0] dout_in;
	 
	 initial begin
		$readmemh("subbytes.table", rom, 0, 255);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout_in <= rom[add];
		end
	 end
	 
	 assign dout = (invbytes)?(dout_in[7:0]):(dout_in[15:8]);

endmodule