data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v:551: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'wbs_addr\' generates 2 bits.\n                                                                                            : ... In instance string_led_controller.i_registers\n          case (wbs_addr)\n          ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v:612: Selection index out of range: 33:2 outside 31:0\n                                                                                               : ... In instance string_led_controller.i_registers\n    addr[ASIZE-1:0] <= wbs_adr_i[ASIZE+1:2];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v:622: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'wbs_addr\' generates 2 bits.\n                                                                                            : ... In instance string_led_controller.i_registers\n      if (valid && !ready && (wbs_addr == ctrl_reg_addr) && wstrb[31]) begin\n                                       ^~\n%Error: data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v:76: Cannot find file containing module: \'prescaler\'\n  prescaler #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.v\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: data/full_repos/permissive/468755927/verilog/rtl/string_led_controller.v:124: Cannot find file containing module: \'generic_sram_1rw1r\'\n  generic_sram_1rw1r #(\n  ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module bit_generator (
  input  wire  rst_n      ,
  input  wire  clk        ,
  input  wire  clear_n    ,
  input  wire  tick       ,

  input  wire  polarity   ,

  input  wire  bit_value  ,
  input  wire  valid      ,
  output reg   ready      ,

  output reg   sout
);

  localparam val_p  = 5'b11000;
  localparam val_1  = 5'b10000;
  localparam val_0  = 5'b01000;

  reg [4:0]  count;
  reg        dbit ;
  reg        polar;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      count <= val_p;
      ready <= 1'b0;
      dbit  <= 1'b0;
      polar <= 1'b0;
      sout  <= 1'b0;
    end else begin

      if (clear_n == 1'b0) begin
        count <= val_p;
        ready <= 1'b0;
        dbit  <= 1'b0;
        polar <= 1'b0;
        sout  <= 1'b0;
      end else begin

        if (tick == 1'b1) begin
          if (count[4:3] == 2'b11) begin
            if (valid == 1'b1) begin
              count <= 5'b00000;
              dbit  <= bit_value;
              polar <= polarity;
            end
          end else begin
            count <= count + 1'b1;
          end
        end

        if ((tick == 1'b1) && (count[4:3] == 2'b11) && (valid == 1'b1)) begin
          ready <= 1'b1;
        end else begin
          ready <= 1'b0;
        end

        if (((dbit == 1'b0) && ((count[4] == 1'b1) || (count[3] == 1'b1))) ||
            ((dbit == 1'b1) &&  (count[4] == 1'b1)                       ) ) begin
          sout <= polar;
        end else begin
          sout <= ~polar;
        end
      end
    end
  end

endmodule
module bit_generator (
  input  wire  rst_n      ,
  input  wire  clk        ,
  input  wire  clear_n    ,
  input  wire  tick       ,

  input  wire  polarity   ,

  input  wire  bit_value  ,
  input  wire  valid      ,
  output reg   ready      ,

  output reg   sout
);


  localparam val_p  = 5'b11000;
  localparam val_1  = 5'b10000;
  localparam val_0  = 5'b01000;

  reg [4:0]  count;
  reg        dbit ;
  reg        polar;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      count <= val_p;
      ready <= 1'b0;
      dbit  <= 1'b0;
      polar <= 1'b0;
      sout  <= 1'b0;
    end else begin

      if (clear_n == 1'b0) begin
        count <= val_p;
        ready <= 1'b0;
        dbit  <= 1'b0;
        polar <= 1'b0;
        sout  <= 1'b0;
      end else begin

        if (tick == 1'b1) begin
          if (count[4:3] == 2'b11) begin
            if (valid == 1'b1) begin
              count <= 5'b00000;
              dbit  <= bit_value;
              polar <= polarity;
            end
          end else begin
            count <= count + 1'b1;
          end
        end

        if ((tick == 1'b1) && (count[4:3] == 2'b11) && (valid == 1'b1)) begin
          ready <= 1'b1;
        end else begin
          ready <= 1'b0;
        end

        if (((dbit == 1'b0) && ((count[4] == 1'b1) || (count[3] == 1'b1))) ||
            ((dbit == 1'b1) &&  (count[4] == 1'b1)                       ) ) begin
          sout <= polar;
        end else begin
          sout <= ~polar;
        end
      end
    end
  end

endmodule