data/full_repos/permissive/527249789/src/commit.v
1: b'%Error: data/full_repos/permissive/527249789/src/commit.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/commit.v:7: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]              pc_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstAddrBus]              pc_i,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/commit.v:9: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]               waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:10: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:12: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   hi_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:13: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   lo_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:15: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   cp0_reg_wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:16: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]               cp0_reg_waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:18: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]           pc_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]            waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:20: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]            waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:21: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                wdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegBus]                hi_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:23: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                hi_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:24: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                lo_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegBus]                cp0_reg_wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:26: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                cp0_reg_wdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:27: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]            cp0_reg_waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:34: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:35: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:36: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:37: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:38: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:39: Define or directive not defined: \'`WriteDisable\'\n        hilo_wen_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:40: Define or directive not defined: \'`ZeroWord\'\n        hi_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:41: Define or directive not defined: \'`ZeroWord\'\n        lo_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:42: Define or directive not defined: \'`WriteDisable\'\n        cp0_reg_wen_o <= `WriteDisable;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:43: Define or directive not defined: \'`ZeroWord\'\n        cp0_reg_wdata_o <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:44: Define or directive not defined: \'`ZeroRegAddr\'\n        cp0_reg_waddr_o <= `ZeroRegAddr;\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:45: Define or directive not defined: \'`FlushEnable\'\n    end else if (flush == `FlushEnable) begin\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:46: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:47: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:48: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:49: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:50: Define or directive not defined: \'`WriteDisable\'\n        hilo_wen_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:51: Define or directive not defined: \'`ZeroWord\'\n        hi_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:52: Define or directive not defined: \'`ZeroWord\'\n        lo_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:53: Define or directive not defined: \'`WriteDisable\'\n        cp0_reg_wen_o <= `WriteDisable;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:54: Define or directive not defined: \'`ZeroWord\'\n        cp0_reg_wdata_o <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:55: Define or directive not defined: \'`ZeroRegAddr\'\n        cp0_reg_waddr_o <= `ZeroRegAddr;\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/commit.v:56: Define or directive not defined: \'`NoStop\'\n    end else if (stall_i == `NoStop) begin\n                            ^~~~~~~\n%Error: Exiting due to 42 error(s)\n'
module commit(
    input                               clk,
    input                               resetn,

    input   [`InstAddrBus]              pc_i,
    input                               wen_i,
    input   [`RegAddrBus]               waddr_i,
    input   [`RegBus]                   wdata_i,
    input                               hilo_wen_i,
    input   [`RegBus]                   hi_i,
    input   [`RegBus]                   lo_i,
    input                               cp0_reg_wen_i,
    input   [`RegBus]                   cp0_reg_wdata_i,
    input   [`RegAddrBus]               cp0_reg_waddr_i,

    output  reg[`InstAddrBus]           pc_o,
    output  reg                         wen_o,
    output  reg[`RegAddrBus]            waddr_o,
    output  reg[`RegBus]                wdata_o,
    output  reg                         hilo_wen_o,
    output  reg[`RegBus]                hi_o,
    output  reg[`RegBus]                lo_o,
    output  reg                         cp0_reg_wen_o,
    output  reg[`RegBus]                cp0_reg_wdata_o,
    output  reg[`RegAddrBus]            cp0_reg_waddr_o,

    input                               flush,
    input                               stall_i
);

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
    end else if (stall_i == `NoStop) begin
        pc_o <= pc_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        wdata_o <= wdata_i;
        hilo_wen_o <= hilo_wen_i;
        hi_o <= hi_i;
        lo_o <= lo_i;
        cp0_reg_wen_o <= cp0_reg_wen_i;
        cp0_reg_wdata_o <= cp0_reg_wdata_i;
        cp0_reg_waddr_o <= cp0_reg_waddr_i;
    end
end

endmodule
module commit(
    input                               clk,
    input                               resetn,

    input   [`InstAddrBus]              pc_i,
    input                               wen_i,
    input   [`RegAddrBus]               waddr_i,
    input   [`RegBus]                   wdata_i,
    input                               hilo_wen_i,
    input   [`RegBus]                   hi_i,
    input   [`RegBus]                   lo_i,
    input                               cp0_reg_wen_i,
    input   [`RegBus]                   cp0_reg_wdata_i,
    input   [`RegAddrBus]               cp0_reg_waddr_i,

    output  reg[`InstAddrBus]           pc_o,
    output  reg                         wen_o,
    output  reg[`RegAddrBus]            waddr_o,
    output  reg[`RegBus]                wdata_o,
    output  reg                         hilo_wen_o,
    output  reg[`RegBus]                hi_o,
    output  reg[`RegBus]                lo_o,
    output  reg                         cp0_reg_wen_o,
    output  reg[`RegBus]                cp0_reg_wdata_o,
    output  reg[`RegAddrBus]            cp0_reg_waddr_o,

    input                               flush,
    input                               stall_i
);


always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        wdata_o <= `ZeroWord;
        hilo_wen_o <= `WriteDisable;
        hi_o <= `ZeroWord;
        lo_o <= `ZeroWord;
        cp0_reg_wen_o <= `WriteDisable;
        cp0_reg_wdata_o <= `ZeroWord;
        cp0_reg_waddr_o <= `ZeroRegAddr;
    end else if (stall_i == `NoStop) begin
        pc_o <= pc_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        wdata_o <= wdata_i;
        hilo_wen_o <= hilo_wen_i;
        hi_o <= hi_i;
        lo_o <= lo_i;
        cp0_reg_wen_o <= cp0_reg_wen_i;
        cp0_reg_wdata_o <= cp0_reg_wdata_i;
        cp0_reg_waddr_o <= cp0_reg_waddr_i;
    end
end

endmodule