data/full_repos/permissive/423547971/FPGA Projects/Candy_Machine_Basys3/seg7_control.v
1: b'%Error: Cannot find file containing module: Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/Candy_Machine_Basys3/seg7_control.v\n%Error: Exiting due to 3 error(s)\n'
module seg7_control(
    input clk,
    input reset,
    input [1:0] change_high,
    input [3:0] change_low,
    input [2:0] the_state,
    output reg [0:6] seg,
    output reg [3:0] an
    );
    

    parameter NULL  = 7'b111_1111;
    parameter ZERO  = 7'b000_0001;
    parameter ONE   = 7'b100_1111;
    parameter TWO   = 7'b001_0010;
    parameter FIVE  = 7'b010_0100;
    parameter N     = 7'b110_1010;
    parameter J     = 7'b100_0011;
    parameter O     = 7'b110_0010;
    parameter Y     = 7'b100_0100;
    parameter C     = 7'b011_0001;
    parameter H     = 7'b110_1000;
    parameter B     = 7'b110_0000;
    parameter U     = 7'b110_0011;
    
    
    reg [1:0] anode_select;
    reg [16:0] anode_timer;
    
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            anode_select <= 0;
            anode_timer <= 0; 
        end
        else
            if(anode_timer == 99_999) begin
                anode_timer <= 0;
                anode_select <=  anode_select + 1;
            end
            else
                anode_timer <=  anode_timer + 1;
    end
    
    always @(anode_select) begin
        case(anode_select) 
            2'b00 : an = 4'b0111;
            2'b01 : an = 4'b1011;
            2'b10 : an = 4'b1101;
            2'b11 : an = 4'b1110;
        endcase
    end
    
    always @(posedge clk) begin
        case(the_state)
            3'b000 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = B;
                          4'b1101 : seg = U;
                          4'b1110 : seg = Y;
                      endcase
                    end
                    
            3'b001 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = NULL;
                          4'b1101 : seg = FIVE;
                          4'b1110 : seg = NULL;
                      endcase
                    end
            
            3'b010 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = ONE;
                          4'b1101 : seg = ZERO;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b011 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = ONE;
                          4'b1101 : seg = FIVE;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b100 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = TWO;
                          4'b1101 : seg = ZERO;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b101 : begin
                      case(an)
                          4'b0111 : seg = N;
                          4'b1011 : seg = J;
                          4'b1101 : seg = O;
                          4'b1110 : seg = Y;
                      endcase
                    end
                    
            3'b110 : begin
                      case(an)
                          4'b0111 : seg = C;
                          4'b1011 : seg = H;
                          4'b1101 : begin
                                        case(change_high)
                                            2'b00  : seg = NULL;
                                            2'b01  : seg = ONE;
                                            2'b10  : seg = TWO;
                                            default: seg = ZERO;
                                        endcase
                                    end
                          4'b1110 : begin
                                        case(change_low)
                                            4'b0000 : seg = ZERO;
                                            4'b0101 : seg = FIVE;
                                            default : seg = NULL;
                                        endcase
                                    end
                      endcase
                    end
        endcase
    end  
endmodule
module seg7_control(
    input clk,
    input reset,
    input [1:0] change_high,
    input [3:0] change_low,
    input [2:0] the_state,
    output reg [0:6] seg,
    output reg [3:0] an
    );

    

    parameter NULL  = 7'b111_1111;
    parameter ZERO  = 7'b000_0001;
    parameter ONE   = 7'b100_1111;
    parameter TWO   = 7'b001_0010;
    parameter FIVE  = 7'b010_0100;
    parameter N     = 7'b110_1010;
    parameter J     = 7'b100_0011;
    parameter O     = 7'b110_0010;
    parameter Y     = 7'b100_0100;
    parameter C     = 7'b011_0001;
    parameter H     = 7'b110_1000;
    parameter B     = 7'b110_0000;
    parameter U     = 7'b110_0011;
    
    
    reg [1:0] anode_select;
    reg [16:0] anode_timer;
    
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            anode_select <= 0;
            anode_timer <= 0; 
        end
        else
            if(anode_timer == 99_999) begin
                anode_timer <= 0;
                anode_select <=  anode_select + 1;
            end
            else
                anode_timer <=  anode_timer + 1;
    end
    
    always @(anode_select) begin
        case(anode_select) 
            2'b00 : an = 4'b0111;
            2'b01 : an = 4'b1011;
            2'b10 : an = 4'b1101;
            2'b11 : an = 4'b1110;
        endcase
    end
    
    always @(posedge clk) begin
        case(the_state)
            3'b000 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = B;
                          4'b1101 : seg = U;
                          4'b1110 : seg = Y;
                      endcase
                    end
                    
            3'b001 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = NULL;
                          4'b1101 : seg = FIVE;
                          4'b1110 : seg = NULL;
                      endcase
                    end
            
            3'b010 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = ONE;
                          4'b1101 : seg = ZERO;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b011 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = ONE;
                          4'b1101 : seg = FIVE;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b100 : begin
                      case(an)
                          4'b0111 : seg = NULL;
                          4'b1011 : seg = TWO;
                          4'b1101 : seg = ZERO;
                          4'b1110 : seg = NULL;
                      endcase
                    end
                    
            3'b101 : begin
                      case(an)
                          4'b0111 : seg = N;
                          4'b1011 : seg = J;
                          4'b1101 : seg = O;
                          4'b1110 : seg = Y;
                      endcase
                    end
                    
            3'b110 : begin
                      case(an)
                          4'b0111 : seg = C;
                          4'b1011 : seg = H;
                          4'b1101 : begin
                                        case(change_high)
                                            2'b00  : seg = NULL;
                                            2'b01  : seg = ONE;
                                            2'b10  : seg = TWO;
                                            default: seg = ZERO;
                                        endcase
                                    end
                          4'b1110 : begin
                                        case(change_low)
                                            4'b0000 : seg = ZERO;
                                            4'b0101 : seg = FIVE;
                                            default : seg = NULL;
                                        endcase
                                    end
                      endcase
                    end
        endcase
    end  
endmodule