data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Countbcd/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Countbcd/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    output wire [3:1] ena,
    output wire [15:0] q
);

  wire [3:0] cQ0, cQ1, cQ2, cQ3;

  assign ena[1] = cQ0 == 9;
  assign ena[2] = ena[1] & cQ1 == 9;
  assign ena[3] = ena[2] & cQ2 == 9;

  assign q = {cQ3, cQ2, cQ1, cQ0};

  bcdcount counter0 (
      clk,
      reset,
      1'b1,
      cQ0
  );
  bcdcount counter1 (
      clk,
      reset,
      ena[1],
      cQ1
  );
  bcdcount counter2 (
      clk,
      reset,
      ena[2],
      cQ2
  );
  bcdcount counter3 (
      clk,
      reset,
      ena[3],
      cQ3
  );

endmodule
module top_module (
    input wire clk,
    input wire reset,
    output wire [3:1] ena,
    output wire [15:0] q
);


  wire [3:0] cQ0, cQ1, cQ2, cQ3;

  assign ena[1] = cQ0 == 9;
  assign ena[2] = ena[1] & cQ1 == 9;
  assign ena[3] = ena[2] & cQ2 == 9;

  assign q = {cQ3, cQ2, cQ1, cQ0};

  bcdcount counter0 (
      clk,
      reset,
      1'b1,
      cQ0
  );
  bcdcount counter1 (
      clk,
      reset,
      ena[1],
      cQ1
  );
  bcdcount counter2 (
      clk,
      reset,
      ena[2],
      cQ2
  );
  bcdcount counter3 (
      clk,
      reset,
      ena[3],
      cQ3
  );

endmodule