data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_sdr_osu.v
1: b'%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_sdr_osu.v:3: Cannot find include file: toysram.vh\n`include "toysram.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.sv\n             toysram.vh\n             toysram.vh.v\n             toysram.vh.sv\n             obj_dir/toysram.vh\n             obj_dir/toysram.vh.v\n             obj_dir/toysram.vh.sv\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_sdr_osu.v:33: Define or directive not defined: \'`GENMODE\'\n parameter GENMODE = `GENMODE;          \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_bist_sdr_osu.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter GENMODE = `GENMODE;          \n                             ^\n%Error: Exiting due to 3 error(s)\n'
module ra_bist_sdr (

    clk,
    reset, picture,
    ctl,
    status,
    rd0_enb_in,
    rd0_adr_in,
    rd1_enb_in,
    rd1_adr_in,
    wr0_enb_in,
    wr0_adr_in,
    wr0_dat_in,
    rd0_enb_out,
    rd0_adr_out,
    rd0_dat,
    rd1_enb_out,
    rd1_adr_out,
    rd1_dat,
    wr0_enb_out,
    wr0_adr_out,
    wr0_dat_out,
    bist_fail,
    bist_passed


);

 parameter GENMODE = `GENMODE;

   input          clk;
   input          reset;
   input  [31:0]  ctl;

   input          rd0_enb_in;
   input  [5:0]   rd0_adr_in;
   input          rd1_enb_in;
   input  [5:0]   rd1_adr_in;
   input          wr0_enb_in;
   input  [5:0]   wr0_adr_in;
   input  [71:0]  wr0_dat_in;

   output [31:0]  status;
   output         rd0_enb_out;
   output [5:0]   rd0_adr_out;
   input  [71:0]  rd0_dat;
   output         rd1_enb_out;
   output [5:0]   rd1_adr_out;
   input  [71:0]  rd1_dat;
   output         wr0_enb_out;
   output [5:0]   wr0_adr_out;
   output [71:0]  wr0_dat_out;



   reg    [5:0]   seq_q;
   wire   [5:0]   seq_d;
   wire           active;
   wire           bist_rd0_enb;
   wire   [5:0]   bist_rd0_adr;
   wire           bist_rd1_enb;
   wire   [5:0]   bist_rd1_adr;
   wire           bist_wr0_enb;
   wire   [5:0]   bist_wr0_adr;
   wire   [71:0]  bist_wr0_dat;

   output         bist_fail;
   output         bist_passed;


   always @ (posedge clk) begin
      if (reset)
         seq_q <= 6'h3F;
      else
         seq_q <= seq_d;
   end


   assign seq_d = seq_q;
   assign active = seq_q != 6'h3F;
   assign status = 0;

   assign wr0_enb_in  = 1;





   assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
   assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
   assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
   assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
   assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
   assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
   assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;


endmodule
module ra_bist_sdr (

    clk,
    reset, picture,
    ctl,
    status,
    rd0_enb_in,
    rd0_adr_in,
    rd1_enb_in,
    rd1_adr_in,
    wr0_enb_in,
    wr0_adr_in,
    wr0_dat_in,
    rd0_enb_out,
    rd0_adr_out,
    rd0_dat,
    rd1_enb_out,
    rd1_adr_out,
    rd1_dat,
    wr0_enb_out,
    wr0_adr_out,
    wr0_dat_out,
    bist_fail,
    bist_passed


);


 parameter GENMODE = `GENMODE;

   input          clk;
   input          reset;
   input  [31:0]  ctl;

   input          rd0_enb_in;
   input  [5:0]   rd0_adr_in;
   input          rd1_enb_in;
   input  [5:0]   rd1_adr_in;
   input          wr0_enb_in;
   input  [5:0]   wr0_adr_in;
   input  [71:0]  wr0_dat_in;

   output [31:0]  status;
   output         rd0_enb_out;
   output [5:0]   rd0_adr_out;
   input  [71:0]  rd0_dat;
   output         rd1_enb_out;
   output [5:0]   rd1_adr_out;
   input  [71:0]  rd1_dat;
   output         wr0_enb_out;
   output [5:0]   wr0_adr_out;
   output [71:0]  wr0_dat_out;



   reg    [5:0]   seq_q;
   wire   [5:0]   seq_d;
   wire           active;
   wire           bist_rd0_enb;
   wire   [5:0]   bist_rd0_adr;
   wire           bist_rd1_enb;
   wire   [5:0]   bist_rd1_adr;
   wire           bist_wr0_enb;
   wire   [5:0]   bist_wr0_adr;
   wire   [71:0]  bist_wr0_dat;

   output         bist_fail;
   output         bist_passed;


   always @ (posedge clk) begin
      if (reset)
         seq_q <= 6'h3F;
      else
         seq_q <= seq_d;
   end


   assign seq_d = seq_q;
   assign active = seq_q != 6'h3F;
   assign status = 0;

   assign wr0_enb_in  = 1;





   assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
   assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
   assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
   assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
   assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
   assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
   assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;


endmodule