data/full_repos/permissive/488739248/rtl/final_video/module RGB4bit_LUT.sv
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/488739248/rtl/final_video/module\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/final_video,data/full_repos/permissive/488739248/data/full_repos/permissive/488739248/rtl/final_video/module\n             data/full_repos/permissive/488739248/rtl/final_video,data/full_repos/permissive/488739248/data/full_repos/permissive/488739248/rtl/final_video/module.v\n             data/full_repos/permissive/488739248/rtl/final_video,data/full_repos/permissive/488739248/data/full_repos/permissive/488739248/rtl/final_video/module.sv\n             data/full_repos/permissive/488739248/rtl/final_video/module\n             data/full_repos/permissive/488739248/rtl/final_video/module.v\n             data/full_repos/permissive/488739248/rtl/final_video/module.sv\n             obj_dir/data/full_repos/permissive/488739248/rtl/final_video/module\n             obj_dir/data/full_repos/permissive/488739248/rtl/final_video/module.v\n             obj_dir/data/full_repos/permissive/488739248/rtl/final_video/module.sv\n%Error: Cannot find file containing module: RGB4bit_LUT.sv\n%Error: Exiting due to 2 error(s)\n'
module RGB4bit_LUT( 
    input wire   [3:0] COL_4BIT, 
    output logic [7:0] COL_8BIT
);
    reg [11:0] angle; 
    
    always_comb begin
    case (COL_4BIT) 
        4'h0: COL_8BIT = 8'h00;
        4'h1: COL_8BIT = 8'h0B;
        4'h2: COL_8BIT = 8'h1C;
        4'h3: COL_8BIT = 8'h2E;
        4'h4: COL_8BIT = 8'h42;
        4'h5: COL_8BIT = 8'h51;
        4'h6: COL_8BIT = 8'h62;
        4'h7: COL_8BIT = 8'h70;
        4'h8: COL_8BIT = 8'h92;
        4'h9: COL_8BIT = 8'hA1;
        4'hA: COL_8BIT = 8'hB1;
        4'hB: COL_8BIT = 8'hC0;
        4'hC: COL_8BIT = 8'hD4;
        4'hD: COL_8BIT = 8'hE3;
        4'hE: COL_8BIT = 8'hF4;
        4'hF: COL_8BIT = 8'hFF;
    endcase 
    end 
endmodule
module RGB4bit_LUT( 
    input wire   [3:0] COL_4BIT, 
    output logic [7:0] COL_8BIT
);

    reg [11:0] angle; 
    
    always_comb begin
    case (COL_4BIT) 
        4'h0: COL_8BIT = 8'h00;
        4'h1: COL_8BIT = 8'h0B;
        4'h2: COL_8BIT = 8'h1C;
        4'h3: COL_8BIT = 8'h2E;
        4'h4: COL_8BIT = 8'h42;
        4'h5: COL_8BIT = 8'h51;
        4'h6: COL_8BIT = 8'h62;
        4'h7: COL_8BIT = 8'h70;
        4'h8: COL_8BIT = 8'h92;
        4'h9: COL_8BIT = 8'hA1;
        4'hA: COL_8BIT = 8'hB1;
        4'hB: COL_8BIT = 8'hC0;
        4'hC: COL_8BIT = 8'hD4;
        4'hD: COL_8BIT = 8'hE3;
        4'hE: COL_8BIT = 8'hF4;
        4'hF: COL_8BIT = 8'hFF;
    endcase 
    end 
endmodule