data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/mux_2_5.v
data/verilator_xmls/32f067b6-c33b-4443-b54a-0ae77baf9e14.xml
module mux_2_5(
    input flag,
    input [4:0] a,
    input [4:0] b,
    output [4:0] out
    );
    assign out = flag?b:a;
endmodule
module mux_2_5(
    input flag,
    input [4:0] a,
    input [4:0] b,
    output [4:0] out
    );

    assign out = flag?b:a;
endmodule