data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:8: Define or directive not defined: \'`STAGE_COUNT\'\n    input  wire [ `STAGE_COUNT-1:0] pipeline_stage,\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:9: Define or directive not defined: \'`OPCODE_COUNT\'\n    input  wire [`OPCODE_COUNT-1:0] opcode_type   ,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:10: Define or directive not defined: \'`GROUP_COUNT\'\n    input  wire [ `GROUP_COUNT-1:0] opcode_group  ,\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:12: Define or directive not defined: \'`SIGNAL_COUNT\'\n    output wire [`SIGNAL_COUNT-1:0] signals\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:33: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign signals[`CONTROL_REG_RR_READ] =\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_REG_RR_READ] =\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:34: Define or directive not defined: \'`STAGE_ID\'\n        (pipeline_stage == `STAGE_ID) &&\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:35: Define or directive not defined: \'`GROUP_ALU_TWO_OP\'\n            (opcode_group[`GROUP_ALU_TWO_OP] ||\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:36: Define or directive not defined: \'`GROUP_LOAD_INDIRECT\'\n                (opcode_group[`GROUP_LOAD_INDIRECT] && !opcode_group[`GROUP_STACK]) ||\n                              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:36: Define or directive not defined: \'`GROUP_STACK\'\n                (opcode_group[`GROUP_LOAD_INDIRECT] && !opcode_group[`GROUP_STACK]) ||\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:37: Define or directive not defined: \'`GROUP_REGISTER\'\n                opcode_group[`GROUP_REGISTER] ||\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:38: Define or directive not defined: \'`GROUP_STORE\'\n                opcode_group[`GROUP_STORE]);\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:39: Define or directive not defined: \'`CONTROL_REG_RR_WRITE\'\n    assign signals[`CONTROL_REG_RR_WRITE] = 0;\n                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_REG_RR_WRITE] = 0;\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:41: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign signals[`CONTROL_REG_RD_READ] =\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_REG_RD_READ] =\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:42: Define or directive not defined: \'`STAGE_ID\'\n        (pipeline_stage == `STAGE_ID) &&\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:43: Define or directive not defined: \'`GROUP_ALU\'\n            (opcode_group[`GROUP_ALU] ||\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:44: Define or directive not defined: \'`GROUP_STORE_INDIRECT\'\n                ((opcode_group[`GROUP_STORE_INDIRECT] ||  \n                               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:45: Define or directive not defined: \'`GROUP_LOAD_INDIRECT\'\n                        opcode_group[`GROUP_LOAD_INDIRECT]) && !opcode_group[`GROUP_STACK]));\n                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:45: Define or directive not defined: \'`GROUP_STACK\'\n                        opcode_group[`GROUP_LOAD_INDIRECT]) && !opcode_group[`GROUP_STACK]));\n                                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:46: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n    assign signals[`CONTROL_REG_RD_WRITE] =\n                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_REG_RD_WRITE] =\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:47: Define or directive not defined: \'`STAGE_WB\'\n        (pipeline_stage == `STAGE_WB) &&\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:48: Define or directive not defined: \'`GROUP_ALU\'\n            (opcode_group[`GROUP_ALU] ||\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:49: Define or directive not defined: \'`GROUP_REGISTER\'\n                opcode_group[`GROUP_REGISTER] ||\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:50: Define or directive not defined: \'`GROUP_LOAD\'\n                opcode_group[`GROUP_LOAD]);\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:53: Define or directive not defined: \'`CONTROL_MEM_READ\'\n    assign signals[`CONTROL_MEM_READ] =\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_MEM_READ] =\n                                    ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:54: Define or directive not defined: \'`STAGE_MEM\'\n        (pipeline_stage == `STAGE_MEM) &&\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:55: Define or directive not defined: \'`GROUP_LOAD\'\n            opcode_group[`GROUP_LOAD];\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:56: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n    assign signals[`CONTROL_MEM_WRITE] =\n                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_MEM_WRITE] =\n                                     ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:57: Define or directive not defined: \'`STAGE_MEM\'\n        (pipeline_stage == `STAGE_MEM) &&\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:58: Define or directive not defined: \'`GROUP_STORE\'\n            opcode_group[`GROUP_STORE];\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:65: Define or directive not defined: \'`CONTROL_STACK_POSTDEC\'\n    assign signals[`CONTROL_STACK_POSTDEC] =\n                   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_STACK_POSTDEC] =\n                                         ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:66: Define or directive not defined: \'`STAGE_MEM\'\n        (pipeline_stage == `STAGE_MEM) &&\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:67: Define or directive not defined: \'`TYPE_PUSH\'\n            ((opcode_type == `TYPE_PUSH) ||\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:68: Define or directive not defined: \'`TYPE_RCALL\'\n                (opcode_type == `TYPE_RCALL));\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:80: Define or directive not defined: \'`CONTROL_STACK_PREINC\'\n    assign signals[`CONTROL_STACK_PREINC] =\n                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:80: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign signals[`CONTROL_STACK_PREINC] =\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:81: Define or directive not defined: \'`STAGE_EX\'\n        ((pipeline_stage == `STAGE_EX) &&\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:82: Define or directive not defined: \'`TYPE_POP\'\n            ((opcode_type == `TYPE_POP) || (opcode_type == `TYPE_RET))) ||\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:82: Define or directive not defined: \'`TYPE_RET\'\n            ((opcode_type == `TYPE_POP) || (opcode_type == `TYPE_RET))) ||\n                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:83: Define or directive not defined: \'`STAGE_MEM\'\n        (pipeline_stage == `STAGE_MEM && (opcode_type == `TYPE_RET) && cycle_count == 0);\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/signal_generation_unit.v:83: Define or directive not defined: \'`TYPE_RET\'\n        (pipeline_stage == `STAGE_MEM && (opcode_type == `TYPE_RET) && cycle_count == 0);\n                                                         ^~~~~~~~~\n%Error: Exiting due to 48 error(s)\n'
module signal_generation_unit (
    input  wire [ `STAGE_COUNT-1:0] pipeline_stage,
    input  wire [`OPCODE_COUNT-1:0] opcode_type   ,
    input  wire [ `GROUP_COUNT-1:0] opcode_group  ,
    input  wire                     cycle_count   ,
    output wire [`SIGNAL_COUNT-1:0] signals
);





    assign signals[`CONTROL_REG_RR_READ] =
        (pipeline_stage == `STAGE_ID) &&
            (opcode_group[`GROUP_ALU_TWO_OP] ||
                (opcode_group[`GROUP_LOAD_INDIRECT] && !opcode_group[`GROUP_STACK]) ||
                opcode_group[`GROUP_REGISTER] ||
                opcode_group[`GROUP_STORE]);
    assign signals[`CONTROL_REG_RR_WRITE] = 0;

    assign signals[`CONTROL_REG_RD_READ] =
        (pipeline_stage == `STAGE_ID) &&
            (opcode_group[`GROUP_ALU] ||
                ((opcode_group[`GROUP_STORE_INDIRECT] ||
                        opcode_group[`GROUP_LOAD_INDIRECT]) && !opcode_group[`GROUP_STACK]));
    assign signals[`CONTROL_REG_RD_WRITE] =
        (pipeline_stage == `STAGE_WB) &&
            (opcode_group[`GROUP_ALU] ||
                opcode_group[`GROUP_REGISTER] ||
                opcode_group[`GROUP_LOAD]);


    assign signals[`CONTROL_MEM_READ] =
        (pipeline_stage == `STAGE_MEM) &&
            opcode_group[`GROUP_LOAD];
    assign signals[`CONTROL_MEM_WRITE] =
        (pipeline_stage == `STAGE_MEM) &&
            opcode_group[`GROUP_STORE];


    assign signals[`CONTROL_STACK_POSTDEC] =
        (pipeline_stage == `STAGE_MEM) &&
            ((opcode_type == `TYPE_PUSH) ||
                (opcode_type == `TYPE_RCALL));

    assign signals[`CONTROL_STACK_PREINC] =
        ((pipeline_stage == `STAGE_EX) &&
            ((opcode_type == `TYPE_POP) || (opcode_type == `TYPE_RET))) ||
        (pipeline_stage == `STAGE_MEM && (opcode_type == `TYPE_RET) && cycle_count == 0);

endmodule
module signal_generation_unit (
    input  wire [ `STAGE_COUNT-1:0] pipeline_stage,
    input  wire [`OPCODE_COUNT-1:0] opcode_type   ,
    input  wire [ `GROUP_COUNT-1:0] opcode_group  ,
    input  wire                     cycle_count   ,
    output wire [`SIGNAL_COUNT-1:0] signals
);






    assign signals[`CONTROL_REG_RR_READ] =
        (pipeline_stage == `STAGE_ID) &&
            (opcode_group[`GROUP_ALU_TWO_OP] ||
                (opcode_group[`GROUP_LOAD_INDIRECT] && !opcode_group[`GROUP_STACK]) ||
                opcode_group[`GROUP_REGISTER] ||
                opcode_group[`GROUP_STORE]);
    assign signals[`CONTROL_REG_RR_WRITE] = 0;

    assign signals[`CONTROL_REG_RD_READ] =
        (pipeline_stage == `STAGE_ID) &&
            (opcode_group[`GROUP_ALU] ||
                ((opcode_group[`GROUP_STORE_INDIRECT] ||
                        opcode_group[`GROUP_LOAD_INDIRECT]) && !opcode_group[`GROUP_STACK]));
    assign signals[`CONTROL_REG_RD_WRITE] =
        (pipeline_stage == `STAGE_WB) &&
            (opcode_group[`GROUP_ALU] ||
                opcode_group[`GROUP_REGISTER] ||
                opcode_group[`GROUP_LOAD]);


    assign signals[`CONTROL_MEM_READ] =
        (pipeline_stage == `STAGE_MEM) &&
            opcode_group[`GROUP_LOAD];
    assign signals[`CONTROL_MEM_WRITE] =
        (pipeline_stage == `STAGE_MEM) &&
            opcode_group[`GROUP_STORE];


    assign signals[`CONTROL_STACK_POSTDEC] =
        (pipeline_stage == `STAGE_MEM) &&
            ((opcode_type == `TYPE_PUSH) ||
                (opcode_type == `TYPE_RCALL));

    assign signals[`CONTROL_STACK_PREINC] =
        ((pipeline_stage == `STAGE_EX) &&
            ((opcode_type == `TYPE_POP) || (opcode_type == `TYPE_RET))) ||
        (pipeline_stage == `STAGE_MEM && (opcode_type == `TYPE_RET) && cycle_count == 0);

endmodule