data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=0;bb<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=1;bb<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=1;bb<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Error: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:32: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("nand_gate_tb.vcd");  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson1/NAND/nandgate.v:33: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;  \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nand_gate(
    A,
    B,
    Y
);
input   A;
input   B;
output  Y;
assign  Y = ~(A&B);
endmodule
module nand_gate(
    A,
    B,
    Y
);

input   A;
input   B;
output  Y;
assign  Y = ~(A&B);
endmodule