data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_rx_c.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_rx_c.v:1: Cannot find include file: byte_un_striping_c.v\n`include "byte_un_striping_c.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_un_striping_c.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_un_striping_c.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_un_striping_c.v.sv\n             byte_un_striping_c.v\n             byte_un_striping_c.v.v\n             byte_un_striping_c.v.sv\n             obj_dir/byte_un_striping_c.v\n             obj_dir/byte_un_striping_c.v.v\n             obj_dir/byte_un_striping_c.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_rx_c.v:2: Cannot find include file: bits8_32word_c.v\n`include "bits8_32word_c.v"  \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_rx_c.v:3: Cannot find include file: serial_parallel_c.v\n`include "serial_parallel_c.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module phy_rx_c (
	input clk_32f,
	input clk_2f_c,
	input clk_4f_c,
	input reset,
	input Data_in_0,
	input Data_in_1,
	output reg valid_out_c,
	output reg [31:0] Data_out_c
);
	wire clk_32f;
	wire clk_2f_c;
	wire clk_4f_c;
	wire reset;
	wire valid_0_c;
	wire [31:0] lane_0_c;
	wire valid_1_c;
	wire [31:0] lane_1_c;
	wire valid_out_0_c;
	wire [7:0] Data_out_0_c;
	wire valid_out_1_c;
	wire [7:0] Data_out_1_c;
	wire valid_c;
	wire [31:0] Data_c;

	always @(*) begin
		valid_out_c <= valid_c;
		Data_out_c <= Data_c;
	end

	serial_parallel_c serial_parallel_1 (

					     .valid_out_c	(valid_out_0_c),
					     .Data_out_c	(Data_out_0_c[7:0]),

					     .clk_32f		(clk_32f),
					     .reset		(reset),
					     .Data_in		(Data_in_0));

	serial_parallel_c serial_parallel_2 (

					     .valid_out_c	(valid_out_1_c),
					     .Data_out_c	(Data_out_1_c[7:0]),

					     .clk_32f		(clk_32f),
					     .reset		(reset),
					     .Data_in		(Data_in_1));

	bits8_32word_c bits8_32word_1 (

				       .valid_out_c	(valid_0_c),
				       .Data_out_c	(lane_0_c[31:0]),

				       .clk_4f_c	(clk_4f_c),
				       .reset		(reset),
				       .valid_in	(valid_out_0_c),
				       .Data_in		(Data_out_0_c[7:0]));

	bits8_32word_c bits8_32word_2 (

				       .valid_out_c	(valid_1_c),
				       .Data_out_c	(lane_1_c[31:0]),

				       .clk_4f_c	(clk_4f_c),
				       .reset		(reset),
				       .valid_in	(valid_out_1_c),
				       .Data_in		(Data_out_1_c[7:0]));

	byte_un_striping_c byte_un_striping_1 (

					       .valid_out_c	(valid_c),
					       .Data_out_c	(Data_c[31:0]),

					       .clk_2f_c	(clk_2f_c),
					       .reset		(reset),
					       .valid_0		(valid_0_c),
					       .lane_0		(lane_0_c[31:0]),
					       .valid_1		(valid_1_c),
					       .lane_1		(lane_1_c[31:0]));

endmodule
module phy_rx_c (
	input clk_32f,
	input clk_2f_c,
	input clk_4f_c,
	input reset,
	input Data_in_0,
	input Data_in_1,
	output reg valid_out_c,
	output reg [31:0] Data_out_c
);

	wire clk_32f;
	wire clk_2f_c;
	wire clk_4f_c;
	wire reset;
	wire valid_0_c;
	wire [31:0] lane_0_c;
	wire valid_1_c;
	wire [31:0] lane_1_c;
	wire valid_out_0_c;
	wire [7:0] Data_out_0_c;
	wire valid_out_1_c;
	wire [7:0] Data_out_1_c;
	wire valid_c;
	wire [31:0] Data_c;

	always @(*) begin
		valid_out_c <= valid_c;
		Data_out_c <= Data_c;
	end

	serial_parallel_c serial_parallel_1 (

					     .valid_out_c	(valid_out_0_c),
					     .Data_out_c	(Data_out_0_c[7:0]),

					     .clk_32f		(clk_32f),
					     .reset		(reset),
					     .Data_in		(Data_in_0));

	serial_parallel_c serial_parallel_2 (

					     .valid_out_c	(valid_out_1_c),
					     .Data_out_c	(Data_out_1_c[7:0]),

					     .clk_32f		(clk_32f),
					     .reset		(reset),
					     .Data_in		(Data_in_1));

	bits8_32word_c bits8_32word_1 (

				       .valid_out_c	(valid_0_c),
				       .Data_out_c	(lane_0_c[31:0]),

				       .clk_4f_c	(clk_4f_c),
				       .reset		(reset),
				       .valid_in	(valid_out_0_c),
				       .Data_in		(Data_out_0_c[7:0]));

	bits8_32word_c bits8_32word_2 (

				       .valid_out_c	(valid_1_c),
				       .Data_out_c	(lane_1_c[31:0]),

				       .clk_4f_c	(clk_4f_c),
				       .reset		(reset),
				       .valid_in	(valid_out_1_c),
				       .Data_in		(Data_out_1_c[7:0]));

	byte_un_striping_c byte_un_striping_1 (

					       .valid_out_c	(valid_c),
					       .Data_out_c	(Data_c[31:0]),

					       .clk_2f_c	(clk_2f_c),
					       .reset		(reset),
					       .valid_0		(valid_0_c),
					       .lane_0		(lane_0_c[31:0]),
					       .valid_1		(valid_1_c),
					       .lane_1		(lane_1_c[31:0]));

endmodule