data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/ece241_2014_q4/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/ece241_2014_q4,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/ece241_2014_q4/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire x,
    output wire z
);

  wire xor_i, and_i, or_i;
  wire dff1_q, dff2_q, dff3_q;
  wire dff1_qn, dff2_qn, dff3_qn;

  assign xor_i = x ^ dff1_q;
  assign and_i = x & dff2_qn;
  assign or_i  = x | dff3_qn;

  my_dff dff1 (
      clk,
      xor_i,
      dff1_q,
      dff1_qn
  );
  my_dff dff2 (
      clk,
      and_i,
      dff2_q,
      dff2_qn
  );
  my_dff dff3 (
      clk,
      or_i,
      dff3_q,
      dff3_qn
  );

  assign z = ~(dff1_q | dff2_q | dff3_q);


endmodule
module top_module (
    input  wire clk,
    input  wire x,
    output wire z
);


  wire xor_i, and_i, or_i;
  wire dff1_q, dff2_q, dff3_q;
  wire dff1_qn, dff2_qn, dff3_qn;

  assign xor_i = x ^ dff1_q;
  assign and_i = x & dff2_qn;
  assign or_i  = x | dff3_qn;

  my_dff dff1 (
      clk,
      xor_i,
      dff1_q,
      dff1_qn
  );
  my_dff dff2 (
      clk,
      and_i,
      dff2_q,
      dff2_qn
  );
  my_dff dff3 (
      clk,
      or_i,
      dff3_q,
      dff3_qn
  );

  assign z = ~(dff1_q | dff2_q | dff3_q);


endmodule