data/full_repos/permissive/435012493/DP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/435012493/DP.v:43: Signal definition not found, creating implicitly: \'count\'\n                                                               : ... Suggested alternative: \'cnt\'\ncounter    counter1(clk, enC, count, 6\'d32, cnt);\n                              ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435012493/DP.v:48: Input port connection \'P\' expects 65 bits on the pin connection, but pin connection\'s SEL generates 64 bits.\n                                                            : ... In instance DP\ntriStateBuffer buffer(P[64:1], done, result);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/435012493/DP.v:48: Output port connection \'result\' expects 65 bits on the pin connection, but pin connection\'s VARREF \'result\' generates 64 bits.\n                                                            : ... In instance DP\ntriStateBuffer buffer(P[64:1], done, result);\n                                     ^~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module DP(input clk, input [31:0] m, r, 
		    input addResSel, addSel, pSel, enC, enA, enS, enP, done,
			 output [63:0] result, output [1:0] pOut, output cntOut);


wire [64:0] Preg, Sreg, Areg, P, S, A, PRS, outMux1, outMux2, Pv, sum;
				
wire [5:0] cnt;

initialize iniDATA(m, r, Preg, Sreg, Areg);
dReg       Product(clk, enP, Pv, P );
dReg       Svalue(clk, enS, Sreg, S );
dReg       Avalue(clk, enA, Areg, A );

MUX2to1    pMUX(pSel, PRS, Preg, Pv);
MUX2to1    aMUX(addSel, A, S, outMux1);
MUX2to1    rMUX(addResSel, P, sum, outMux2);


assign PRS  = {outMux2[64], outMux2[64:1]};

ADDER      add(P, outMux1, sum);  
counter    counter1(clk, enC, count, 6'd32, cnt);
cmpCNT     cmpCount(cnt, cntOut);

assign pOut = P[1:0];

triStateBuffer buffer(P[64:1], done, result);


endmodule
module DP(input clk, input [31:0] m, r, 
		    input addResSel, addSel, pSel, enC, enA, enS, enP, done,
			 output [63:0] result, output [1:0] pOut, output cntOut);



wire [64:0] Preg, Sreg, Areg, P, S, A, PRS, outMux1, outMux2, Pv, sum;
				
wire [5:0] cnt;

initialize iniDATA(m, r, Preg, Sreg, Areg);
dReg       Product(clk, enP, Pv, P );
dReg       Svalue(clk, enS, Sreg, S );
dReg       Avalue(clk, enA, Areg, A );

MUX2to1    pMUX(pSel, PRS, Preg, Pv);
MUX2to1    aMUX(addSel, A, S, outMux1);
MUX2to1    rMUX(addResSel, P, sum, outMux2);


assign PRS  = {outMux2[64], outMux2[64:1]};

ADDER      add(P, outMux1, sum);  
counter    counter1(clk, enC, count, 6'd32, cnt);
cmpCNT     cmpCount(cnt, cntOut);

assign pOut = P[1:0];

triStateBuffer buffer(P[64:1], done, result);


endmodule