data/full_repos/permissive/421048855/Circuits/Sequential Logic/Latches and Filp-Flops/Edgecapture.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Filp-Flops,data/full_repos/permissive/421048855\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Filp-Flops/Edgecapture.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] in_old;
    always @(posedge clk) begin
        in_old <= in;
    end
    always @(posedge clk) begin
        if(reset) out <= 'b0;
        else begin
            out <= ((in ^ in_old) & (~in)) | out;
        end
    end
endmodule
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] in_old;
    always @(posedge clk) begin
        in_old <= in;
    end
    always @(posedge clk) begin
        if(reset) out <= 'b0;
        else begin
            out <= ((in ^ in_old) & (~in)) | out;
        end
    end
endmodule