data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v
1: b"%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:102: Duplicate declaration of signal: 'carry_bus'\n                                                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg  carry_bus;\n     ^~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:60: ... Location of original declaration\n    output       carry_bus,  \n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:103: Duplicate declaration of signal: 'sync_bus'\nreg  sync_bus;\n     ^~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:63: ... Location of original declaration\n    output       sync_bus,   \n                 ^~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:141: Duplicate declaration of signal: 'bcd_bus'\nreg        bcd_bus;\n           ^~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:54: ... Location of original declaration\n    output       bcd_bus,    \n                 ^~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:142: Duplicate declaration of signal: 'bcd_oen'\nreg        bcd_oen;\n           ^~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:55: ... Location of original declaration\n    output       bcd_oen,    \n                 ^~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:145: Duplicate declaration of signal: 'ia_bus'\nreg        ia_bus;   \n           ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:58: ... Location of original declaration\n    output       ia_bus,     \n                 ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:151: Duplicate declaration of signal: 'is_bus'\nreg        is_bus;\n           ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:46: ... Location of original declaration\n    output       is_bus,     \n                 ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:152: Duplicate declaration of signal: 'is_oen'\nreg        is_oen;\n           ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:47: ... Location of original declaration\n    output       is_oen,      \n                 ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:159: Duplicate declaration of signal: 'ws_bus'\nreg        ws_bus;\n           ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:51: ... Location of original declaration\n    output       ws_bus,     \n                 ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:160: Duplicate declaration of signal: 'ws_oen'\nreg        ws_oen;\n           ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:52: ... Location of original declaration\n    output       ws_oen,   \n                 ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:169: Duplicate declaration of signal: 'sraddr_mux'\nreg [7:0]  sraddr_mux;\n           ^~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:97: ... Location of original declaration\n    output [7:0]  sraddr_mux,\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:171: Duplicate declaration of signal: 'srdata'\nwire [29:0] srdata;\n            ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:98: ... Location of original declaration\n    input  [29:0] srdata\n                  ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:172: Duplicate declaration of signal: 'sram_clk1'\nreg        sram_clk1;\n           ^~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:96: ... Location of original declaration\n    output        sram_clk1,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:195: Duplicate declaration of signal: 'dbg_disable_ctc'\nwire       dbg_disable_ctc;\n           ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:70: ... Location of original declaration\n    input        dbg_disable_ctc,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:196: Duplicate declaration of signal: 'dbg_disable_arc'\nwire       dbg_disable_arc;\n           ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:69: ... Location of original declaration\n    input        dbg_disable_arc,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:197: Duplicate declaration of signal: 'dbg_disable_rom'\nwire       dbg_disable_rom;\n           ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:71: ... Location of original declaration\n    input        dbg_disable_rom,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:198: Duplicate declaration of signal: 'dbg_rom_roe'\nwire [2:0] dbg_rom_roe;\n           ^~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:81: ... Location of original declaration\n    output [2:0] dbg_rom_roe,       \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:199: Duplicate declaration of signal: 'dbg_ctc_state1'\nwire       dbg_ctc_state1;\n           ^~~~~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:82: ... Location of original declaration\n    output       dbg_ctc_state1,    \n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:200: Duplicate declaration of signal: 'dbg_dsbf'\nwire [4:0] dbg_dsbf;\n           ^~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:76: ... Location of original declaration\n    output [4:0] dbg_dsbf,           \n                 ^~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:201: Duplicate declaration of signal: 'dbg_arc_t1'\nwire       dbg_arc_t1;\n           ^~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:77: ... Location of original declaration\n    output       dbg_arc_t1,         \n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:202: Duplicate declaration of signal: 'dbg_arc_t4'\nwire       dbg_arc_t4;\n           ^~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:78: ... Location of original declaration\n    output       dbg_arc_t4,         \n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:203: Duplicate declaration of signal: 'dbg_arc_a1'\nwire       dbg_arc_a1;\n           ^~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:79: ... Location of original declaration\n    output       dbg_arc_a1,         \n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:204: Duplicate declaration of signal: 'dbg_arc_b1'\nwire       dbg_arc_b1;\n           ^~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:80: ... Location of original declaration\n    output       dbg_arc_b1,         \n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:205: Duplicate declaration of signal: 'dbg_arc_dummy'\nwire       dbg_arc_dummy;\n           ^~~~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:72: ... Location of original declaration\n    input        dbg_arc_dummy,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:206: Duplicate declaration of signal: 'dbg_ctc_kdn'\nwire       dbg_ctc_kdn;\n           ^~~~~~~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/hp35_core.v:83: ... Location of original declaration\n    output       dbg_ctc_kdn,        \n                 ^~~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n"
module hp35_core(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif


    input  [4:0] COL,
    input        cdiv_rst,
    input        dbg_internal_cdiv,
    input        osc_in,
    input        phi1_in,
    input        phi2_in,
    output       phi1_out,
    output       phi2_out,
    output       phi_oen,
    input        PWO,
    output [4:0] DD,
    output       START,
    
    input        is_in,
    output       is_bus,
    output       is_oen,

    
    input        ws_in,
    output       ws_bus,
    output       ws_oen,   
    input        bcd_in,
    output       bcd_bus,
    output       bcd_oen,
    
    input        ia_in,
    output       ia_bus,
    output       ia_oen,
    output       carry_bus,
    input        carry_in,
    output       carry_oen,
    output       sync_bus,
    input        sync_in,
    output       sync_oen,



    input        dbg_disable_arc,
    input        dbg_disable_ctc,
    input        dbg_disable_rom,
    input        dbg_arc_dummy,
    input        dbg_force_data,
    input [9:0]  dbg_romdata,
    input        dbg_sram_csb1,
    output [4:0] dbg_dsbf,
    output       dbg_arc_t1,
    output       dbg_arc_t4,
    output       dbg_arc_a1,
    output       dbg_arc_b1,
    output [2:0] dbg_rom_roe,
    output       dbg_ctc_state1,
    output       dbg_ctc_kdn,
    output [5:0] dbg_ctc_q,








    input  [2:0]  dbg_sram_cksel,
    input  [7:0]  sraddr_in,
    input  [1:0]  dbg_sram_wrmode,
    output        sram_clk1,
    output [7:0]  sraddr_mux,
    input  [29:0] srdata
);


reg  carry_bus;
reg  sync_bus;
wire sync_drive_ctc;
wire carry_drive_arc;

reg phi1;
reg phi2;

reg [2:0] xdivr;
reg       xT1r, xT2r, xT3r, xT4r;
reg       phi1r;
reg       phi2r;
always@(posedge osc_in or posedge cdiv_rst) begin
    if(cdiv_rst) begin
        xdivr <= 3'b0;
        xT1r <= 1'b1;
        xT2r <= 1'b0;
        xT3r <= 1'b0;
        xT4r <= 1'b0;
    end else begin
        xdivr <= xdivr + 1'b1;
        if(xdivr == 7) begin
            if(DD[1]&DD[3]) 
                {xT1r, xT2r, xT3r, xT4r} <= 4'b0010;
            else
                {xT1r, xT2r, xT3r, xT4r} <= {xT4r, xT1r, xT2r, xT3r};
        end
        phi1r <= (xdivr == 5);
        phi2r <= (xdivr == 7);
    end
end

assign phi1_out = ~phi1r;
assign phi2_out = ~phi2r;
assign phi_oen  = ~dbg_internal_cdiv;


wire       bcd_internal_active;
wire       bcd_internal_drive;
reg        bcd_bus;
reg        bcd_oen;


reg        ia_bus;
wire       ia_internal_drive;


wire [2:0] is_internal_active;
wire [2:0] is_internal_drive;
reg        is_bus;
reg        is_oen;


wire [2:0] ws_internal_active;
wire [2:0] ws_internal_drive;
wire       ws_internal_active_ctc;
wire       ws_internal_drive_ctc;
reg        ws_bus;
reg        ws_oen;

assign sync_oen  = ~dbg_disable_ctc;
assign carry_oen = ~dbg_disable_arc;
assign ia_oen    = ~dbg_disable_ctc;


wire [7:0] sraddr[2:0];
wire [2:0] srprelatch;
reg [7:0]  sraddr_mux;

wire [29:0] srdata;
reg        sram_clk1;
always @* begin
    case (dbg_sram_wrmode)
        2'b11: sraddr_mux = sraddr_in;
        2'b00: sraddr_mux = sraddr[0]; 
        2'b01: sraddr_mux = sraddr[1]; 
        2'b10: sraddr_mux = sraddr[2]; 
    endcase

    case (dbg_sram_cksel)
        3'b000:  sram_clk1 =  phi2; 
        3'b001:  sram_clk1 = ~phi2; 
        3'b010:  sram_clk1 =  phi1;
        3'b011:  sram_clk1 = ~phi1;
        3'b100:  sram_clk1 = 1'b1;
        3'b101:  sram_clk1 = 1'b0; 
        default: sram_clk1 = 1'bx;
    endcase
end




wire       dbg_disable_ctc;
wire       dbg_disable_arc;
wire       dbg_disable_rom;
wire [2:0] dbg_rom_roe;
wire       dbg_ctc_state1;
wire [4:0] dbg_dsbf;
wire       dbg_arc_t1;
wire       dbg_arc_t4;
wire       dbg_arc_a1;
wire       dbg_arc_b1;
wire       dbg_arc_dummy;
wire       dbg_ctc_kdn;



arithmetic_and_register_20_a u_ARC(
    .A(DD[0]),.B(DD[1]),.C(DD[2]),.D(DD[3]),.E(DD[4]),
    .START      (START              ),
    .CARRY      (carry_drive_arc    ),
    .dbg_dsbf3  (dbg_dsbf[3]        ),
    .dbg_dsbf2  (dbg_dsbf[2]        ),
    .dbg_dsbf1  (dbg_dsbf[1]        ),
    .dbg_dsbf0  (dbg_dsbf[0]        ),
    .dbg_dsbf_dp(dbg_dsbf[4]        ),
    .dbg_t1     (dbg_arc_t1         ),
    .dbg_t4     (dbg_arc_t4         ),
    .dbg_regA1  (dbg_arc_a1         ),
    .dbg_regB1  (dbg_arc_b1         ),
    .PHI2       (phi2               ),
    .IS         (is_bus             ),
    .WS         (ws_bus             ),
    .SYNC       (sync_bus           ),
    .bcd_in     (bcd_in             ),
    .bcd_active (bcd_internal_active),
    .bcd_out    (bcd_internal_drive ),
    .dummy      (dbg_arc_dummy      )
);


control_and_timing_16_a u_CTC(
    .ia_out      (ia_internal_drive     ),
    .ws_in       (ws_bus                ),
    .ws_out      (ws_internal_drive_ctc ),
    .ws_active   (ws_internal_active_ctc),
    .SYNC        (sync_drive_ctc        ),
    .tp_tiny_pin2(dbg_ctc_state1        ),
    .dbg_ctc_kdn (dbg_ctc_kdn           ),
    .PHI2        (phi2                  ),
    .PWO         (PWO                   ),
    .IS          (is_bus                ),
    .CARRY       (carry_bus             ),
    .dbg_q       (dbg_ctc_q             ),

    .ROW0(),.ROW1(),.ROW2(),.ROW3(),.ROW4(),.ROW5(),.ROW6(),.ROW7(),
    .COL0(COL[0]),.COL2(COL[1]),.COL3(COL[2]),.COL4(COL[3]),.COL6(COL[4])
);


genvar gi;
generate
    for(gi=0;gi<3;gi=gi+1) begin : gen_ROM_instances
        read_only_memory_18_a #(.RomNum(gi)) u_ROM(
            .is_active(is_internal_active[gi]),
            .is_out   (is_internal_drive [gi]),
            .is_in    (is_bus                ),
            .ws_out   (ws_internal_drive[gi] ),
            .ws_active(ws_internal_active[gi]),
            .IA       (ia_bus                ),
            .PHI1(phi1),.PHI2(phi2),.PWO(PWO),.SYNC(sync_bus),
            .TP_ROE   (dbg_rom_roe[gi]       ),
            .sraddr   (sraddr[gi]            ),
            .srprelatch(srprelatch[gi]       ),
            .srdata   ({2'b0,srdata}         ),
            .dbg_force_data(dbg_force_data   ),
            .forcedata(dbg_romdata           )
        );
    end
endgenerate








reg ws_mux1;
wire ws_internal_active_rom = |ws_internal_active;
always @* begin

    casex ({ws_internal_active})
        3'b1xx:  ws_mux1 = ws_internal_drive[2];
        3'b01x:  ws_mux1 = ws_internal_drive[1];
        3'b001:  ws_mux1 = ws_internal_drive[0];
        default: ws_mux1 = 1'bx;
    endcase

    casex ({~dbg_disable_ctc, ~dbg_disable_rom, ws_internal_active_ctc, ws_internal_active_rom})
        4'b111x: {ws_oen, ws_bus} = {1'b0, ws_internal_drive_ctc};
        4'b1101: {ws_oen, ws_bus} = {1'b0, ws_mux1};
        4'b101x: {ws_oen, ws_bus} = {1'b0, ws_internal_drive_ctc};
        4'b0101: {ws_oen, ws_bus} = {1'b0, ws_mux1};
        default: {ws_oen, ws_bus} = {1'b1, ws_in};
    endcase


    casex ({~dbg_disable_arc, bcd_internal_active})
        2'b0x:   {bcd_oen, bcd_bus} = {1'b1, bcd_in};
        2'b11:   {bcd_oen, bcd_bus} = {1'b0, bcd_internal_drive};
        default: {bcd_oen, bcd_bus} = {1'b1, bcd_in};
    endcase


    casex ({~dbg_disable_rom,is_internal_active})
        4'b0xxx:  {is_oen, is_bus} = {1'b1, is_in               };
        4'b1100:  {is_oen, is_bus} = {1'b0, is_internal_drive[2]};
        4'b1010:  {is_oen, is_bus} = {1'b0, is_internal_drive[1]};
        4'b1001:  {is_oen, is_bus} = {1'b0, is_internal_drive[0]};
        default:  {is_oen, is_bus} = {1'b1, is_in               };
    endcase


    case ({~dbg_disable_ctc})
        1'b1:    {sync_bus, ia_bus} = {sync_drive_ctc, ia_internal_drive};
        default: {sync_bus, ia_bus} = {sync_in,        ia_in};
    endcase

    case ({~dbg_disable_arc})
        1'b1:     carry_bus = carry_drive_arc;
        default:  carry_bus = carry_in;
    endcase
    
    case ({dbg_internal_cdiv})
        1'b1:     {phi1, phi2} = {phi1_out, phi2_out};
        default:  {phi1, phi2} = {phi1_in,  phi2_in };
    endcase
    
end



endmodule
module hp35_core(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif


    input  [4:0] COL,
    input        cdiv_rst,
    input        dbg_internal_cdiv,
    input        osc_in,
    input        phi1_in,
    input        phi2_in,
    output       phi1_out,
    output       phi2_out,
    output       phi_oen,
    input        PWO,
    output [4:0] DD,
    output       START,
    
    input        is_in,
    output       is_bus,
    output       is_oen,

    
    input        ws_in,
    output       ws_bus,
    output       ws_oen,   
    input        bcd_in,
    output       bcd_bus,
    output       bcd_oen,
    
    input        ia_in,
    output       ia_bus,
    output       ia_oen,
    output       carry_bus,
    input        carry_in,
    output       carry_oen,
    output       sync_bus,
    input        sync_in,
    output       sync_oen,



    input        dbg_disable_arc,
    input        dbg_disable_ctc,
    input        dbg_disable_rom,
    input        dbg_arc_dummy,
    input        dbg_force_data,
    input [9:0]  dbg_romdata,
    input        dbg_sram_csb1,
    output [4:0] dbg_dsbf,
    output       dbg_arc_t1,
    output       dbg_arc_t4,
    output       dbg_arc_a1,
    output       dbg_arc_b1,
    output [2:0] dbg_rom_roe,
    output       dbg_ctc_state1,
    output       dbg_ctc_kdn,
    output [5:0] dbg_ctc_q,








    input  [2:0]  dbg_sram_cksel,
    input  [7:0]  sraddr_in,
    input  [1:0]  dbg_sram_wrmode,
    output        sram_clk1,
    output [7:0]  sraddr_mux,
    input  [29:0] srdata
);



reg  carry_bus;
reg  sync_bus;
wire sync_drive_ctc;
wire carry_drive_arc;

reg phi1;
reg phi2;

reg [2:0] xdivr;
reg       xT1r, xT2r, xT3r, xT4r;
reg       phi1r;
reg       phi2r;
always@(posedge osc_in or posedge cdiv_rst) begin
    if(cdiv_rst) begin
        xdivr <= 3'b0;
        xT1r <= 1'b1;
        xT2r <= 1'b0;
        xT3r <= 1'b0;
        xT4r <= 1'b0;
    end else begin
        xdivr <= xdivr + 1'b1;
        if(xdivr == 7) begin
            if(DD[1]&DD[3]) 
                {xT1r, xT2r, xT3r, xT4r} <= 4'b0010;
            else
                {xT1r, xT2r, xT3r, xT4r} <= {xT4r, xT1r, xT2r, xT3r};
        end
        phi1r <= (xdivr == 5);
        phi2r <= (xdivr == 7);
    end
end

assign phi1_out = ~phi1r;
assign phi2_out = ~phi2r;
assign phi_oen  = ~dbg_internal_cdiv;


wire       bcd_internal_active;
wire       bcd_internal_drive;
reg        bcd_bus;
reg        bcd_oen;


reg        ia_bus;
wire       ia_internal_drive;


wire [2:0] is_internal_active;
wire [2:0] is_internal_drive;
reg        is_bus;
reg        is_oen;


wire [2:0] ws_internal_active;
wire [2:0] ws_internal_drive;
wire       ws_internal_active_ctc;
wire       ws_internal_drive_ctc;
reg        ws_bus;
reg        ws_oen;

assign sync_oen  = ~dbg_disable_ctc;
assign carry_oen = ~dbg_disable_arc;
assign ia_oen    = ~dbg_disable_ctc;


wire [7:0] sraddr[2:0];
wire [2:0] srprelatch;
reg [7:0]  sraddr_mux;

wire [29:0] srdata;
reg        sram_clk1;
always @* begin
    case (dbg_sram_wrmode)
        2'b11: sraddr_mux = sraddr_in;
        2'b00: sraddr_mux = sraddr[0]; 
        2'b01: sraddr_mux = sraddr[1]; 
        2'b10: sraddr_mux = sraddr[2]; 
    endcase

    case (dbg_sram_cksel)
        3'b000:  sram_clk1 =  phi2; 
        3'b001:  sram_clk1 = ~phi2; 
        3'b010:  sram_clk1 =  phi1;
        3'b011:  sram_clk1 = ~phi1;
        3'b100:  sram_clk1 = 1'b1;
        3'b101:  sram_clk1 = 1'b0; 
        default: sram_clk1 = 1'bx;
    endcase
end




wire       dbg_disable_ctc;
wire       dbg_disable_arc;
wire       dbg_disable_rom;
wire [2:0] dbg_rom_roe;
wire       dbg_ctc_state1;
wire [4:0] dbg_dsbf;
wire       dbg_arc_t1;
wire       dbg_arc_t4;
wire       dbg_arc_a1;
wire       dbg_arc_b1;
wire       dbg_arc_dummy;
wire       dbg_ctc_kdn;



arithmetic_and_register_20_a u_ARC(
    .A(DD[0]),.B(DD[1]),.C(DD[2]),.D(DD[3]),.E(DD[4]),
    .START      (START              ),
    .CARRY      (carry_drive_arc    ),
    .dbg_dsbf3  (dbg_dsbf[3]        ),
    .dbg_dsbf2  (dbg_dsbf[2]        ),
    .dbg_dsbf1  (dbg_dsbf[1]        ),
    .dbg_dsbf0  (dbg_dsbf[0]        ),
    .dbg_dsbf_dp(dbg_dsbf[4]        ),
    .dbg_t1     (dbg_arc_t1         ),
    .dbg_t4     (dbg_arc_t4         ),
    .dbg_regA1  (dbg_arc_a1         ),
    .dbg_regB1  (dbg_arc_b1         ),
    .PHI2       (phi2               ),
    .IS         (is_bus             ),
    .WS         (ws_bus             ),
    .SYNC       (sync_bus           ),
    .bcd_in     (bcd_in             ),
    .bcd_active (bcd_internal_active),
    .bcd_out    (bcd_internal_drive ),
    .dummy      (dbg_arc_dummy      )
);


control_and_timing_16_a u_CTC(
    .ia_out      (ia_internal_drive     ),
    .ws_in       (ws_bus                ),
    .ws_out      (ws_internal_drive_ctc ),
    .ws_active   (ws_internal_active_ctc),
    .SYNC        (sync_drive_ctc        ),
    .tp_tiny_pin2(dbg_ctc_state1        ),
    .dbg_ctc_kdn (dbg_ctc_kdn           ),
    .PHI2        (phi2                  ),
    .PWO         (PWO                   ),
    .IS          (is_bus                ),
    .CARRY       (carry_bus             ),
    .dbg_q       (dbg_ctc_q             ),

    .ROW0(),.ROW1(),.ROW2(),.ROW3(),.ROW4(),.ROW5(),.ROW6(),.ROW7(),
    .COL0(COL[0]),.COL2(COL[1]),.COL3(COL[2]),.COL4(COL[3]),.COL6(COL[4])
);


genvar gi;
generate
    for(gi=0;gi<3;gi=gi+1) begin : gen_ROM_instances
        read_only_memory_18_a #(.RomNum(gi)) u_ROM(
            .is_active(is_internal_active[gi]),
            .is_out   (is_internal_drive [gi]),
            .is_in    (is_bus                ),
            .ws_out   (ws_internal_drive[gi] ),
            .ws_active(ws_internal_active[gi]),
            .IA       (ia_bus                ),
            .PHI1(phi1),.PHI2(phi2),.PWO(PWO),.SYNC(sync_bus),
            .TP_ROE   (dbg_rom_roe[gi]       ),
            .sraddr   (sraddr[gi]            ),
            .srprelatch(srprelatch[gi]       ),
            .srdata   ({2'b0,srdata}         ),
            .dbg_force_data(dbg_force_data   ),
            .forcedata(dbg_romdata           )
        );
    end
endgenerate








reg ws_mux1;
wire ws_internal_active_rom = |ws_internal_active;
always @* begin

    casex ({ws_internal_active})
        3'b1xx:  ws_mux1 = ws_internal_drive[2];
        3'b01x:  ws_mux1 = ws_internal_drive[1];
        3'b001:  ws_mux1 = ws_internal_drive[0];
        default: ws_mux1 = 1'bx;
    endcase

    casex ({~dbg_disable_ctc, ~dbg_disable_rom, ws_internal_active_ctc, ws_internal_active_rom})
        4'b111x: {ws_oen, ws_bus} = {1'b0, ws_internal_drive_ctc};
        4'b1101: {ws_oen, ws_bus} = {1'b0, ws_mux1};
        4'b101x: {ws_oen, ws_bus} = {1'b0, ws_internal_drive_ctc};
        4'b0101: {ws_oen, ws_bus} = {1'b0, ws_mux1};
        default: {ws_oen, ws_bus} = {1'b1, ws_in};
    endcase


    casex ({~dbg_disable_arc, bcd_internal_active})
        2'b0x:   {bcd_oen, bcd_bus} = {1'b1, bcd_in};
        2'b11:   {bcd_oen, bcd_bus} = {1'b0, bcd_internal_drive};
        default: {bcd_oen, bcd_bus} = {1'b1, bcd_in};
    endcase


    casex ({~dbg_disable_rom,is_internal_active})
        4'b0xxx:  {is_oen, is_bus} = {1'b1, is_in               };
        4'b1100:  {is_oen, is_bus} = {1'b0, is_internal_drive[2]};
        4'b1010:  {is_oen, is_bus} = {1'b0, is_internal_drive[1]};
        4'b1001:  {is_oen, is_bus} = {1'b0, is_internal_drive[0]};
        default:  {is_oen, is_bus} = {1'b1, is_in               };
    endcase


    case ({~dbg_disable_ctc})
        1'b1:    {sync_bus, ia_bus} = {sync_drive_ctc, ia_internal_drive};
        default: {sync_bus, ia_bus} = {sync_in,        ia_in};
    endcase

    case ({~dbg_disable_arc})
        1'b1:     carry_bus = carry_drive_arc;
        default:  carry_bus = carry_in;
    endcase
    
    case ({dbg_internal_cdiv})
        1'b1:     {phi1, phi2} = {phi1_out, phi2_out};
        default:  {phi1, phi2} = {phi1_in,  phi2_in };
    endcase
    
end



endmodule