data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v
1: b'%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:20: Cannot find include file: Interface0_defs.v\n`include "Interface0_defs.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v.v\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v.sv\n             Interface0_defs.v\n             Interface0_defs.v.v\n             Interface0_defs.v.sv\n             obj_dir/Interface0_defs.v\n             obj_dir/Interface0_defs.v.v\n             obj_dir/Interface0_defs.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:104: Unsupported: Ignoring delay on this delayed statement.\n  always #437.5 PI_MASTER_CLK = !PI_MASTER_CLK;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:105: Unsupported: Ignoring delay on this delayed statement.\n  always #3500 ZX_CLK = !ZX_CLK;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #1750;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #875 PI_IO_CLK = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #875 PI_IO_CLK = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #875 PI_MOSI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #1750\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:142: Unsupported: Ignoring delay on this delayed statement.\n      #875 PI_IO_CLK = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:143: Unsupported: Ignoring delay on this delayed statement.\n      #875\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:157: Unsupported: Ignoring delay on this delayed statement.\n    #3500\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #100 $stop;\n    ^\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:186: Define or directive not defined: \'`ROMCS_CMD\'\n    mosiData(`ROMCS_CMD | `RESET_CMD, 4); \n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:186: Define or directive not defined: \'`RESET_CMD\'\n    mosiData(`ROMCS_CMD | `RESET_CMD, 4); \n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:186: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    mosiData(`ROMCS_CMD | `RESET_CMD, 4); \n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:189: Unsupported: Ignoring delay on this delayed statement.\n    #35000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0_sim.v:193: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 4 error(s), 13 warning(s)\n'
module Interface0_sim;


  reg ZX_CLK;
  reg ZX_M1;
  reg ZX_MREQ;
  reg ZX_IORQ;
  reg ZX_RD;
  reg ZX_WR;
  reg [15:0] ZX_ADDR;




  reg PI_MASTER_CLK;
  reg PI_IO_CLK;
  reg PI_MOSI;



  wire ZX_NMI;
  wire ZX_WAIT;
  wire ZX_RESET;

  wire ZX_ROMCS;


  wire PI_MISO;
  wire PI_IO;


  wire [7:0] ZX_DATA;







  reg [7:0] ZX_DATA_reg = 8'd0;
  reg io = 1'b0;
  reg [15:0] io_data = 16'd0;
  reg [2:0] waitTime = 3'd0;
  integer misoLen = 0;


  Interface0 uut (
    .ZX_CLK(ZX_CLK),
    .ZX_M1(ZX_M1),
    .ZX_MREQ(ZX_MREQ),
    .ZX_IORQ(ZX_IORQ),
    .ZX_RD(ZX_RD),
    .ZX_WR(ZX_WR),
    .ZX_ADDR(ZX_ADDR),
    .ZX_DATA(ZX_DATA),

    .ZX_NMI(ZX_NMI),
    .ZX_WAIT(ZX_WAIT),
    .ZX_RESET(ZX_RESET),


    .ZX_ROMCS(ZX_ROMCS),





    .PI_MASTER_CLK(PI_MASTER_CLK),
    .PI_IO_CLK(PI_IO_CLK),
    .PI_IO(PI_IO),
    .PI_MOSI(PI_MOSI),
    .PI_MISO(PI_MISO)





  );

  assign PI_IO = (PI_MOSI && !PI_MISO) ? io : 1'bz;
  assign ZX_DATA = (!ZX_WR && ZX_RD) ? ZX_DATA_reg : 8'bzzzzzzzz;

  always #437.5 PI_MASTER_CLK = !PI_MASTER_CLK;
  always #3500 ZX_CLK = !ZX_CLK;

  always @(negedge ZX_CLK) begin
    if (ZX_WAIT) begin
      if (waitTime != 3'd0) begin
        waitTime = waitTime - 1;
      end else begin
        ZX_M1 <= 1;
        ZX_MREQ <= 1;
        ZX_IORQ <= 1;
        ZX_RD <= 1;
        ZX_WR <= 1;
      end
    end
  end

  task mosiData(input integer data, input integer count);
  begin
    PI_MOSI <= 1;
    #1750;
    while(count) begin
        count = count - 1;
        io = data[count];
        #875 PI_IO_CLK = 1;
        #875 PI_IO_CLK = 0;
    end
    #875 PI_MOSI = 0;
  end
  endtask

  task misoData(output reg[15:0] readData, output integer misoLen);
  begin
    #1750
    readData <= 16'd0;
    misoLen <= 0;
    while (PI_MISO) begin
      PI_IO_CLK = 1;
      #875 PI_IO_CLK = 0;
      #875
      misoLen <= misoLen + 1;
      readData <= {readData[14:0], PI_IO};
    end
  end
  endtask

  task readFromAddress(input reg[15:0] address);
  begin
    waitTime <= 3'b001;
    ZX_ADDR <= address;
    ZX_M1 <= 0;
    ZX_MREQ <= 0;
    ZX_RD <= 0;
    #3500
    misoData(io_data, misoLen);
  end
  endtask


  initial begin

    ZX_CLK = 0;
    ZX_M1 = 1;
    ZX_MREQ = 1;
    ZX_IORQ = 1;
    ZX_RD = 1;
    ZX_WR = 1;


    ZX_ADDR = 0;





    PI_MASTER_CLK = 0;
    PI_IO_CLK = 0;
    PI_MOSI = 0;
    ZX_DATA_reg = 0;


    #100 $stop;
    mosiData(`ROMCS_CMD | `RESET_CMD, 4);
    readFromAddress(16'd0);
    mosiData(8'b11001101, 8);
    #35000

    $display("t=%3d, %b %b",$time, io_data, ZX_ADDR);

    #100 $finish;
  end

endmodule
module Interface0_sim;



  reg ZX_CLK;
  reg ZX_M1;
  reg ZX_MREQ;
  reg ZX_IORQ;
  reg ZX_RD;
  reg ZX_WR;
  reg [15:0] ZX_ADDR;




  reg PI_MASTER_CLK;
  reg PI_IO_CLK;
  reg PI_MOSI;



  wire ZX_NMI;
  wire ZX_WAIT;
  wire ZX_RESET;

  wire ZX_ROMCS;


  wire PI_MISO;
  wire PI_IO;


  wire [7:0] ZX_DATA;







  reg [7:0] ZX_DATA_reg = 8'd0;
  reg io = 1'b0;
  reg [15:0] io_data = 16'd0;
  reg [2:0] waitTime = 3'd0;
  integer misoLen = 0;


  Interface0 uut (
    .ZX_CLK(ZX_CLK),
    .ZX_M1(ZX_M1),
    .ZX_MREQ(ZX_MREQ),
    .ZX_IORQ(ZX_IORQ),
    .ZX_RD(ZX_RD),
    .ZX_WR(ZX_WR),
    .ZX_ADDR(ZX_ADDR),
    .ZX_DATA(ZX_DATA),

    .ZX_NMI(ZX_NMI),
    .ZX_WAIT(ZX_WAIT),
    .ZX_RESET(ZX_RESET),


    .ZX_ROMCS(ZX_ROMCS),





    .PI_MASTER_CLK(PI_MASTER_CLK),
    .PI_IO_CLK(PI_IO_CLK),
    .PI_IO(PI_IO),
    .PI_MOSI(PI_MOSI),
    .PI_MISO(PI_MISO)





  );

  assign PI_IO = (PI_MOSI && !PI_MISO) ? io : 1'bz;
  assign ZX_DATA = (!ZX_WR && ZX_RD) ? ZX_DATA_reg : 8'bzzzzzzzz;

  always #437.5 PI_MASTER_CLK = !PI_MASTER_CLK;
  always #3500 ZX_CLK = !ZX_CLK;

  always @(negedge ZX_CLK) begin
    if (ZX_WAIT) begin
      if (waitTime != 3'd0) begin
        waitTime = waitTime - 1;
      end else begin
        ZX_M1 <= 1;
        ZX_MREQ <= 1;
        ZX_IORQ <= 1;
        ZX_RD <= 1;
        ZX_WR <= 1;
      end
    end
  end

  task mosiData(input integer data, input integer count);
  begin
    PI_MOSI <= 1;
    #1750;
    while(count) begin
        count = count - 1;
        io = data[count];
        #875 PI_IO_CLK = 1;
        #875 PI_IO_CLK = 0;
    end
    #875 PI_MOSI = 0;
  end
  endtask

  task misoData(output reg[15:0] readData, output integer misoLen);
  begin
    #1750
    readData <= 16'd0;
    misoLen <= 0;
    while (PI_MISO) begin
      PI_IO_CLK = 1;
      #875 PI_IO_CLK = 0;
      #875
      misoLen <= misoLen + 1;
      readData <= {readData[14:0], PI_IO};
    end
  end
  endtask

  task readFromAddress(input reg[15:0] address);
  begin
    waitTime <= 3'b001;
    ZX_ADDR <= address;
    ZX_M1 <= 0;
    ZX_MREQ <= 0;
    ZX_RD <= 0;
    #3500
    misoData(io_data, misoLen);
  end
  endtask


  initial begin

    ZX_CLK = 0;
    ZX_M1 = 1;
    ZX_MREQ = 1;
    ZX_IORQ = 1;
    ZX_RD = 1;
    ZX_WR = 1;


    ZX_ADDR = 0;





    PI_MASTER_CLK = 0;
    PI_IO_CLK = 0;
    PI_MOSI = 0;
    ZX_DATA_reg = 0;


    #100 $stop;
    mosiData(`ROMCS_CMD | `RESET_CMD, 4);
    readFromAddress(16'd0);
    mosiData(8'b11001101, 8);
    #35000

    $display("t=%3d, %b %b",$time, io_data, ZX_ADDR);

    #100 $finish;
  end

endmodule