data/full_repos/permissive/500326609/a6/cpu.v
1: b'%Error: data/full_repos/permissive/500326609/a6/cpu.v:47: Cannot find file containing module: \'control\'\ncontrol CONTROL(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500326609/a6,data/full_repos/permissive/500326609/control\n             data/full_repos/permissive/500326609/a6,data/full_repos/permissive/500326609/control.v\n             data/full_repos/permissive/500326609/a6,data/full_repos/permissive/500326609/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: data/full_repos/permissive/500326609/a6/cpu.v:59: Cannot find file containing module: \'regfile\'\nregfile REGFILE(\n^~~~~~~\n%Error: data/full_repos/permissive/500326609/a6/cpu.v:71: Cannot find file containing module: \'immgen\'\n  immgen IMMGEN(\n  ^~~~~~\n%Error: data/full_repos/permissive/500326609/a6/cpu.v:77: Cannot find file containing module: \'alu32\'\nalu32 ALU32(\n^~~~~\n%Error: data/full_repos/permissive/500326609/a6/cpu.v:87: Cannot find file containing module: \'PC\'\nPC ProgCount(\n^~\n%Warning-WIDTH: data/full_repos/permissive/500326609/a6/cpu.v:134: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                 : ... In instance cpu\nassign regwdata = (reset) ? 0 : (regsrc == 2\'b00) ? imm :      \n                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500326609/a6/cpu.v:135: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                 : ... In instance cpu\n            (regsrc == 2\'b10) ? PC_plus4 : data_reg ;    \n                    ^~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module cpu (
    input clk,
    input reset,
    output [31:0] iaddr,
    input [31:0] idata,
    output [31:0] daddr,
    input [31:0] drdata,
    output [31:0] dwdata,
    output [3:0] dwe
);


wire [2:0] branch;
wire [2:0] regsrc;
wire mem2reg;
wire [5:0] ALUop;
wire alusrc;
wire regwrite;
wire [3:0] memwrite;


wire [31:0] regwdata;
wire [31:0] data_reg;
wire [31:0] datawire1;
wire [31:0] datawire2;


wire [31:0] imm;


wire [31:0] alu_out;
wire condition_out;
wire [6:0] opcode;
assign opcode = idata[6:0];


reg [31:0] PC;
wire [31:0] PC_next;
wire [31:0] PC_plus4;


wire [31:0] ldata;




control CONTROL(
  .idata(idata),
  .branch(branch),
  .regsrc(regsrc),
  .mem2reg(mem2reg),
  .ALUop(ALUop),
  .alusrc(alusrc),
  .regwrite(regwrite),
  .memwrite(memwrite)
	);


regfile REGFILE(
  	.rs1(idata[19:15]),
  	.rs2(idata[24:20]),
  	.rd(idata[11:7]),
  	.we(regwrite),
    .wdata(regwdata),
  	.rv1(datawire1),
  	.rv2(datawire2),
    .clk(clk)
  	);


  immgen IMMGEN(
  .idata(idata),
  .imm(imm)
  );


alu32 ALU32(
  .op(ALUop),
	.rv1((opcode == 7'b0010111) ? iaddr : datawire1),
	.rv2( alusrc ? imm : datawire2),
  .rvout(alu_out),
  .condition_out(condition_out)
	);



PC ProgCount(
		.PC(PC),
		.imm(imm),
		.branch(branch),
		.condition_out(condition_out),
		.alu_out(alu_out),
		.PC_plus4(PC_plus4),
		.PC_next(PC_next)
		);






assign dwe =  (memwrite == 4'b1111 && daddr[1:0]== 2'b00) ? 4'b1111:
      				(memwrite == 4'b0011 && daddr[1:0]== 2'b00) ? 4'b0011:
      				(memwrite == 4'b0011 && daddr[1:0]== 2'b10) ? 4'b1100:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b00) ? 4'b0001:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b01) ? 4'b0010:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b10) ? 4'b0100:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b11) ? 4'b1000:
               4'b0000;


assign dwdata = (idata[14:12] === 3'b000) ? {4{datawire2[7:0]}} :
                (idata[14:12] === 3'b001) ? {2{datawire2[15:0]}}:
                datawire2;


assign daddr = (datawire1+imm);





assign ldata =  ((idata[14:12] === 3'b001 || idata[14:12] === 3'b101) && mem2reg) ?
                ( 32'h0000fff & (drdata >> (daddr[1:0] * 8))) :
                ((idata[14:12] === 3'b000 || idata[14:12] === 3'b100) && mem2reg) ?
                ( 32'h000000ff & (drdata >> (daddr[1:0] * 8))) :
                drdata;



assign data_reg = mem2reg ? ldata  : alu_out;


assign regwdata = (reset) ? 0 : (regsrc == 2'b00) ? imm :
						      (regsrc == 2'b10) ? PC_plus4 : data_reg ;


assign iaddr = PC;


always @(posedge reset or posedge clk) begin
		if (reset) begin
			PC <= 32'h00000000;
		end else begin
			PC <= PC_next;
    end
	end

endmodule
module cpu (
    input clk,
    input reset,
    output [31:0] iaddr,
    input [31:0] idata,
    output [31:0] daddr,
    input [31:0] drdata,
    output [31:0] dwdata,
    output [3:0] dwe
);



wire [2:0] branch;
wire [2:0] regsrc;
wire mem2reg;
wire [5:0] ALUop;
wire alusrc;
wire regwrite;
wire [3:0] memwrite;


wire [31:0] regwdata;
wire [31:0] data_reg;
wire [31:0] datawire1;
wire [31:0] datawire2;


wire [31:0] imm;


wire [31:0] alu_out;
wire condition_out;
wire [6:0] opcode;
assign opcode = idata[6:0];


reg [31:0] PC;
wire [31:0] PC_next;
wire [31:0] PC_plus4;


wire [31:0] ldata;




control CONTROL(
  .idata(idata),
  .branch(branch),
  .regsrc(regsrc),
  .mem2reg(mem2reg),
  .ALUop(ALUop),
  .alusrc(alusrc),
  .regwrite(regwrite),
  .memwrite(memwrite)
	);


regfile REGFILE(
  	.rs1(idata[19:15]),
  	.rs2(idata[24:20]),
  	.rd(idata[11:7]),
  	.we(regwrite),
    .wdata(regwdata),
  	.rv1(datawire1),
  	.rv2(datawire2),
    .clk(clk)
  	);


  immgen IMMGEN(
  .idata(idata),
  .imm(imm)
  );


alu32 ALU32(
  .op(ALUop),
	.rv1((opcode == 7'b0010111) ? iaddr : datawire1),
	.rv2( alusrc ? imm : datawire2),
  .rvout(alu_out),
  .condition_out(condition_out)
	);



PC ProgCount(
		.PC(PC),
		.imm(imm),
		.branch(branch),
		.condition_out(condition_out),
		.alu_out(alu_out),
		.PC_plus4(PC_plus4),
		.PC_next(PC_next)
		);






assign dwe =  (memwrite == 4'b1111 && daddr[1:0]== 2'b00) ? 4'b1111:
      				(memwrite == 4'b0011 && daddr[1:0]== 2'b00) ? 4'b0011:
      				(memwrite == 4'b0011 && daddr[1:0]== 2'b10) ? 4'b1100:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b00) ? 4'b0001:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b01) ? 4'b0010:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b10) ? 4'b0100:
      				(memwrite == 4'b0001 && daddr[1:0]== 2'b11) ? 4'b1000:
               4'b0000;


assign dwdata = (idata[14:12] === 3'b000) ? {4{datawire2[7:0]}} :
                (idata[14:12] === 3'b001) ? {2{datawire2[15:0]}}:
                datawire2;


assign daddr = (datawire1+imm);





assign ldata =  ((idata[14:12] === 3'b001 || idata[14:12] === 3'b101) && mem2reg) ?
                ( 32'h0000fff & (drdata >> (daddr[1:0] * 8))) :
                ((idata[14:12] === 3'b000 || idata[14:12] === 3'b100) && mem2reg) ?
                ( 32'h000000ff & (drdata >> (daddr[1:0] * 8))) :
                drdata;



assign data_reg = mem2reg ? ldata  : alu_out;


assign regwdata = (reset) ? 0 : (regsrc == 2'b00) ? imm :
						      (regsrc == 2'b10) ? PC_plus4 : data_reg ;


assign iaddr = PC;


always @(posedge reset or posedge clk) begin
		if (reset) begin
			PC <= 32'h00000000;
		end else begin
			PC <= PC_next;
    end
	end

endmodule