data/full_repos/permissive/417033152/fft_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b000;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b001;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b010;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b011;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b100;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b101;#10 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\nsel = 3\'b110;#10 \n             ^\n%Error: data/full_repos/permissive/417033152/fft_testbench.v:28: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dump1.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/417033152/fft_testbench.v:29: Unsupported or unknown PLI call: $dumpvars\n$dumpvars;\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/417033152/fft_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n#10000 $finish;\n^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench; 
reg clk;
reg [2:0] sel;
wire [8:0] yr,yi;
dit_fft_8 dit_fft_8_test(.clk(clk),.sel(sel),.yr(yr),.yi(yi)); 
initial
begin clk = 0;
end 
always 
begin

#5
clk = ~clk;
end
initial 
begin
sel = 3'b000;#10 
sel = 3'b001;#10 
sel = 3'b010;#10 
sel = 3'b011;#10 
sel = 3'b100;#10 
sel = 3'b101;#10 
sel = 3'b110;#10 
sel = 3'b111;
end 
initial begin
$dumpfile("dump1.vcd");
$dumpvars;
#10000 $finish;
end
  
endmodule
module testbench;
 
reg clk;
reg [2:0] sel;
wire [8:0] yr,yi;
dit_fft_8 dit_fft_8_test(.clk(clk),.sel(sel),.yr(yr),.yi(yi)); 
initial
begin clk = 0;
end 
always 
begin

#5
clk = ~clk;
end
initial 
begin
sel = 3'b000;#10 
sel = 3'b001;#10 
sel = 3'b010;#10 
sel = 3'b011;#10 
sel = 3'b100;#10 
sel = 3'b101;#10 
sel = 3'b110;#10 
sel = 3'b111;
end 
initial begin
$dumpfile("dump1.vcd");
$dumpvars;
#10000 $finish;
end
  
endmodule