data/full_repos/permissive/444555755/mp4/hdl/hazard_detection.sv
1: b'%Error: data/full_repos/permissive/444555755/mp4/hdl/hazard_detection.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport rv32i_types::*; \n       ^~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module hazard_detection_unit (

    input logic clk,
    input logic rst,

    input logic dmem_read, 
    input logic dmem_write,
    input logic muldiv_start,
    input logic muldiv_resp,
    input logic data_resp_dp,
    input logic inst_resp_dp,
    input rv32i_reg dest, 
    input rv32i_reg src1,
    input rv32i_reg src2, 
    input logic br_en, 
    input logic jump_en,
    input rv32i_opcode opcode,
    output logic inst_read,
    output logic rst_IF_ID, 
    output logic rst_ID_EX,
    output logic rst_EX_MEM, 
    output logic rst_MEM_WB,
    output logic load_IF_ID, 
    output logic load_ID_EX, 
    output logic load_EX_MEM,
    output logic load_MEM_WB,
    output logic load_pc
);
function void set_defaults(); 

    rst_IF_ID = 1'b0; 
    rst_ID_EX = 1'b0; 
    rst_EX_MEM = 1'b0;
    rst_MEM_WB = 1'b0;  
    load_IF_ID = 1'b1; 
    load_ID_EX = 1'b1; 
    load_EX_MEM = 1'b1;
    load_MEM_WB = 1'b1; 
    load_pc = 1'b1; 
    inst_read = 1'b1; 
endfunction

function void load_stall(); 

    load_pc = 1'b0; 
    load_IF_ID = 1'b0; 
    load_ID_EX = 1'b0; 
    load_EX_MEM = 1'b0;
    load_MEM_WB = 1'b0;
endfunction 

function void load_hit();

    if(dest == src1 || dest == src2) begin
        rst_EX_MEM = 1'b1;
        load_pc = 1'b0;
        load_IF_ID = 1'b0; 
        load_ID_EX = 1'b0; 
    end
endfunction 


logic [31:0] counter;
register muldiv_pc (.clk(clk), .rst(rst), .load(muldiv_resp), .in(counter + 32'b1), .out(counter));

always_comb begin 
    set_defaults();
    case({(jump_en || (br_en && opcode == op_br)), inst_resp_dp, dmem_read || dmem_write || muldiv_start, data_resp_dp || muldiv_resp})


    4'b0000: begin 
        load_pc = 1'b0; 
        rst_IF_ID = 1'b1; 
    end 


    4'b0001:;


    4'b0010: begin 
        load_stall();
    end 


    4'b0011: begin
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_pc = 1'b0;
        rst_IF_ID = 1'b1; 
    end 


    4'b0100: begin 
        load_pc = 1'b1; 
        inst_read = 1'b1; 
    end 


    4'b0101:;


    4'b0110: begin 
        load_stall();
    end 


    4'b0111: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
    end


    4'b1000: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1001:;



    4'b1010: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1011: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_pc = 1'b0;
        load_ID_EX = 1'b0; 
        rst_IF_ID = 1'b1;
    end 


    4'b1100: begin 
        load_pc = 1'b1; 
        inst_read = 1'b1; 
        rst_IF_ID = 1'b1; 
        rst_ID_EX = 1'b1; 
    end 


    4'b1101:;


    4'b1110: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1111: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_ID_EX = 1'b0; 
        rst_IF_ID = 1'b1; 
    end 
    endcase 
end 
endmodule
module hazard_detection_unit (

    input logic clk,
    input logic rst,

    input logic dmem_read, 
    input logic dmem_write,
    input logic muldiv_start,
    input logic muldiv_resp,
    input logic data_resp_dp,
    input logic inst_resp_dp,
    input rv32i_reg dest, 
    input rv32i_reg src1,
    input rv32i_reg src2, 
    input logic br_en, 
    input logic jump_en,
    input rv32i_opcode opcode,
    output logic inst_read,
    output logic rst_IF_ID, 
    output logic rst_ID_EX,
    output logic rst_EX_MEM, 
    output logic rst_MEM_WB,
    output logic load_IF_ID, 
    output logic load_ID_EX, 
    output logic load_EX_MEM,
    output logic load_MEM_WB,
    output logic load_pc
);

function void set_defaults(); 

    rst_IF_ID = 1'b0; 
    rst_ID_EX = 1'b0; 
    rst_EX_MEM = 1'b0;
    rst_MEM_WB = 1'b0;  
    load_IF_ID = 1'b1; 
    load_ID_EX = 1'b1; 
    load_EX_MEM = 1'b1;
    load_MEM_WB = 1'b1; 
    load_pc = 1'b1; 
    inst_read = 1'b1; 
endfunction

function void load_stall(); 

    load_pc = 1'b0; 
    load_IF_ID = 1'b0; 
    load_ID_EX = 1'b0; 
    load_EX_MEM = 1'b0;
    load_MEM_WB = 1'b0;
endfunction 

function void load_hit();

    if(dest == src1 || dest == src2) begin
        rst_EX_MEM = 1'b1;
        load_pc = 1'b0;
        load_IF_ID = 1'b0; 
        load_ID_EX = 1'b0; 
    end
endfunction 


logic [31:0] counter;
register muldiv_pc (.clk(clk), .rst(rst), .load(muldiv_resp), .in(counter + 32'b1), .out(counter));

always_comb begin 
    set_defaults();
    case({(jump_en || (br_en && opcode == op_br)), inst_resp_dp, dmem_read || dmem_write || muldiv_start, data_resp_dp || muldiv_resp})


    4'b0000: begin 
        load_pc = 1'b0; 
        rst_IF_ID = 1'b1; 
    end 


    4'b0001:;


    4'b0010: begin 
        load_stall();
    end 


    4'b0011: begin
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_pc = 1'b0;
        rst_IF_ID = 1'b1; 
    end 


    4'b0100: begin 
        load_pc = 1'b1; 
        inst_read = 1'b1; 
    end 


    4'b0101:;


    4'b0110: begin 
        load_stall();
    end 


    4'b0111: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
    end


    4'b1000: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1001:;



    4'b1010: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1011: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_pc = 1'b0;
        load_ID_EX = 1'b0; 
        rst_IF_ID = 1'b1;
    end 


    4'b1100: begin 
        load_pc = 1'b1; 
        inst_read = 1'b1; 
        rst_IF_ID = 1'b1; 
        rst_ID_EX = 1'b1; 
    end 


    4'b1101:;


    4'b1110: begin 
        load_stall();
        rst_IF_ID = 1'b1; 
    end 


    4'b1111: begin 
        if((muldiv_start && (dmem_read && !data_resp_dp)) || (dmem_read && (muldiv_start && !muldiv_resp)))
            load_stall();
        load_ID_EX = 1'b0; 
        rst_IF_ID = 1'b1; 
    end 
    endcase 
end 
endmodule