data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/BUF/dff.v
data/verilator_xmls/22612a95-7960-462d-88e7-5de0259efa30.xml
module DFF #(
    parameter DATA_WIDTH = 8
    )
    (

    input   clk,
    input   rst_n,
    input   en,
    
    input   [DATA_WIDTH-1:0]    d,
    output  [DATA_WIDTH-1:0]    q

    );
    

    reg     [DATA_WIDTH-1:0]    q_temp;
    

    always @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            q_temp <= {(DATA_WIDTH){1'b0}};
        end else if (en) begin
            q_temp <= d;
        end
    end


    assign q = q_temp;

endmodule
module DFF #(
    parameter DATA_WIDTH = 8
    )
    (

    input   clk,
    input   rst_n,
    input   en,
    
    input   [DATA_WIDTH-1:0]    d,
    output  [DATA_WIDTH-1:0]    q

    );

    

    reg     [DATA_WIDTH-1:0]    q_temp;
    

    always @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            q_temp <= {(DATA_WIDTH){1'b0}};
        end else if (en) begin
            q_temp <= d;
        end
    end


    assign q = q_temp;

endmodule