data/full_repos/permissive/440170309/src/uart_rx.v
1: b'%Error: data/full_repos/permissive/440170309/src/uart_rx.v:17: syntax error, unexpected byte, expecting IDENTIFIER or do or final\n    output reg [7:0] byte\n                     ^~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:20: syntax error, unexpected assign\n    assign clk = clk_100M;\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:26: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:30: syntax error, unexpected assign\n    assign rx_neg_edge = ~rx & rx_delay;     \n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:33: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:49: syntax error, unexpected IDENTIFIER\n    baud_gen baud_gen(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:58: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:64: syntax error, unexpected assign\n    assign flag_data = rx_cnt!=0 && rx_cnt!=9;\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module uart_rx (
    input wire clk_100M,
    input wire rst,
    input wire en,
    input wire rx,

    output wire byte_valid,
    output reg [7:0] byte
);
    wire clk;
    assign clk = clk_100M;


    reg rx_delay;
    always @(posedge clk) begin
        rx_delay <= rst ? 1 : rx;
    end
    wire rx_neg_edge;
    assign rx_neg_edge = ~rx & rx_delay;

    reg rx_en;
    always @(posedge clk) begin
        if(rst) begin
            rx_en <= 0;
        end
        else begin
            case(rx_en)
                0: rx_en <= rx_neg_edge ? 1 : 0;
                1: rx_en <= byte_valid  ? 0 : 1;
            endcase
        end
    end


    wire rx_valid;
    baud_gen baud_gen(
        .clk_100M(clk),
        .rst(rst),
        .rx_en(rx_en),

        .rx_valid(rx_valid)
    );

    reg [3: 0] rx_cnt;
    always @(posedge clk) begin
        rx_cnt <= rst | byte_valid  ? 0 :
                  rx_valid          ? rx_cnt + 1 : rx_cnt;
    end

    wire flag_data;
    assign flag_data = rx_cnt!=0 && rx_cnt!=9;

    always @(posedge clk) begin
        if(rst) begin
            byte <= 8'b0;
        end 
        else if(rx_valid & flag_data) begin
            byte <= {rx, byte[7:1]};
        end
    end

    assign byte_valid = rx_valid && (rx_cnt==9);
endmodule
module uart_rx (
    input wire clk_100M,
    input wire rst,
    input wire en,
    input wire rx,

    output wire byte_valid,
    output reg [7:0] byte
);

    wire clk;
    assign clk = clk_100M;


    reg rx_delay;
    always @(posedge clk) begin
        rx_delay <= rst ? 1 : rx;
    end
    wire rx_neg_edge;
    assign rx_neg_edge = ~rx & rx_delay;

    reg rx_en;
    always @(posedge clk) begin
        if(rst) begin
            rx_en <= 0;
        end
        else begin
            case(rx_en)
                0: rx_en <= rx_neg_edge ? 1 : 0;
                1: rx_en <= byte_valid  ? 0 : 1;
            endcase
        end
    end


    wire rx_valid;
    baud_gen baud_gen(
        .clk_100M(clk),
        .rst(rst),
        .rx_en(rx_en),

        .rx_valid(rx_valid)
    );

    reg [3: 0] rx_cnt;
    always @(posedge clk) begin
        rx_cnt <= rst | byte_valid  ? 0 :
                  rx_valid          ? rx_cnt + 1 : rx_cnt;
    end

    wire flag_data;
    assign flag_data = rx_cnt!=0 && rx_cnt!=9;

    always @(posedge clk) begin
        if(rst) begin
            byte <= 8'b0;
        end 
        else if(rx_valid & flag_data) begin
            byte <= {rx, byte[7:1]};
        end
    end

    assign byte_valid = rx_valid && (rx_cnt==9);
endmodule