data/full_repos/permissive/510938582/rtl/r.v
data/verilator_xmls/c8282a09-5821-46cb-a344-097e04c1ac58.xml
module r(din, clk, rst,rload, dout);
input clk,rst,rload;
input [7:0]din;
output reg[7:0]dout;
always@(posedge clk or negedge rst)
begin
	if(rst==0)
		dout<=0;
	else if(rload)
		dout<=din;
end
endmodule
module r(din, clk, rst,rload, dout);

input clk,rst,rload;
input [7:0]din;
output reg[7:0]dout;
always@(posedge clk or negedge rst)
begin
	if(rst==0)
		dout<=0;
	else if(rload)
		dout<=din;
end
endmodule