data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module BOEM #(parameter                       P_LOG = 2,
              parameter                       FLOAT  = "no",
              parameter                       SIGNED = "no",
              parameter                       DATW  = 64,
              parameter                       KEYW  = 32)
             (input  wire                     CLK,
              input  wire [(DATW<<P_LOG)-1:0] DIN,
              output wire [(DATW<<P_LOG)-1:0] DOT);

  localparam PAYW = DATW - KEYW;

  genvar i, j, k;
  generate
    if (PAYW == 0) begin
      reg [(DATW<<P_LOG)-1:0] pd [P_LOG-1:0];
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(DATW<<P_LOG)-1:0] dot;
        if (i == 0) begin
          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: pipelined_cas
            if (j == 0) begin
              reg [DATW-1:0] buf0; always @(posedge CLK) buf0 <= DIN[DATW*(j+1)-1:DATW*j];
              reg [DATW-1:0] buf1; always @(posedge CLK) buf1 <= DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))];
              assign dot[DATW*(j+1)-1:DATW*j] = buf0;
              assign dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))] = buf1;
            end else begin
              CAS #(FLOAT, SIGNED, DATW, KEYW)
              cas(
                  CLK,
                  DIN[DATW*(j+1)-1:DATW*j],
                  DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))],
                  dot[DATW*(j+1)-1:DATW*j],
                  dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))]
                  );
            end
          end
          always @(posedge CLK) pd[i] <= dot;
        end else begin
          for (k=0; k<((1<<i)-1); k=k+1) begin: blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: pipelined_cas
              CAS #(FLOAT, SIGNED, DATW, KEYW)
              cas(
                  CLK,
                  pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                  pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                  dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                  dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]
                  );
            end
          end
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_upper_buf;
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_lower_buf;
          always @(posedge CLK) pd_upper_buf <= pd[i-1][(DATW<<P_LOG)-1:DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) pd_lower_buf <= pd[i-1][DATW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) pd[i] <= {pd_upper_buf,
                                          dot[DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:DATW*(1<<(P_LOG-(i+1)))],
                                          pd_lower_buf};
        end
      end
      assign DOT = pd[P_LOG-1];
    end else begin

      wire [(KEYW<<P_LOG)-1:0] i_key;
      wire [(PAYW<<P_LOG)-1:0] i_payload;
      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_i_data
        assign i_key[KEYW*(i+1)-1:KEYW*i] = DIN[(KEYW+DATW*i)-1:DATW*i];
        assign i_payload[PAYW*(i+1)-1:PAYW*i] = DIN[DATW*(i+1)-1:(KEYW+DATW*i)];
      end

      reg [(KEYW<<P_LOG)-1:0] k_preg [P_LOG-1:0];
      reg [(PAYW<<P_LOG)-1:0] p_preg [P_LOG-1:0];
      integer p;
      reg [(PAYW<<P_LOG)-1:0] p_sreg [P_LOG-1:0];
      always @(posedge CLK) begin
        p_sreg[0] <= i_payload;
        for (p=1; p<P_LOG; p=p+1) begin
          p_sreg[p] <= p_sreg[p-1];
        end
      end
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(KEYW<<P_LOG)-1:0] o_key;
        wire [(PAYW<<P_LOG)-1:0] o_payload;
        if (i == 0) begin

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: pipelined_k_cas
            if (j == 0) begin
              reg [KEYW-1:0] k_buf0; always @(posedge CLK) k_buf0 <= i_key[KEYW*(j+1)-1:KEYW*j];
              reg [KEYW-1:0] k_buf1; always @(posedge CLK) k_buf1 <= i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))];
              assign o_key[KEYW*(j+1)-1:KEYW*j] = k_buf0;
              assign o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))] = k_buf1;
            end else begin: k_cas_exists
              wire o_cmp;
              wire i_cmp;
              K_CAS #(FLOAT, SIGNED, KEYW)
              k_cas(
                    CLK,
                    i_key[KEYW*(j+1)-1:KEYW*j],
                    i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                    o_key[KEYW*(j+1)-1:KEYW*j],
                    o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                    o_cmp
                    );
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          always @(posedge CLK) k_preg[i] <= o_key;

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: p_swaps
            if (j == 0) begin
              assign o_payload[PAYW*(j+1)-1:PAYW*j] = p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j];
              assign o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))] = p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))];
            end else begin
              P_SWAP #(PAYW)
              p_swap(
                     pipelined_k_cas[j].k_cas_exists.i_cmp,
                     p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j],
                     p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))],
                     o_payload[PAYW*(j+1)-1:PAYW*j],
                     o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))]
                     );
            end
          end
          always @(posedge CLK) p_preg[i] <= o_payload;
        end else begin

          for (k=0; k<((1<<i)-1); k=k+1) begin: k_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: pipelined_k_cas
              wire o_cmp;
              wire i_cmp;
              K_CAS #(FLOAT, SIGNED, KEYW)
              k_cas(
                    CLK,
                    k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                    k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                    o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                    o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                    o_cmp
                    );
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_upper_buf;
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_lower_buf;
          always @(posedge CLK) k_preg_upper_buf <= k_preg[i-1][(KEYW<<P_LOG)-1:KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) k_preg_lower_buf <= k_preg[i-1][KEYW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) k_preg[i] <= {k_preg_upper_buf,
                                              o_key[KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:KEYW*(1<<(P_LOG-(i+1)))],
                                              k_preg_lower_buf};

          for (k=0; k<((1<<i)-1); k=k+1) begin: p_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: p_swaps
              P_SWAP #(PAYW)
              p_swap(k_blocks[k].pipelined_k_cas[j].i_cmp,
                     p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                     p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                     o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                     o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]
                     );
            end
          end
          always @(posedge CLK) p_preg[i] <= {p_preg[i-1][(PAYW<<P_LOG)-1:PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))],
                                              o_payload[PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:PAYW*(1<<(P_LOG-(i+1)))],
                                              p_preg[i-1][PAYW*(1<<(P_LOG-(i+1)))-1:0]};
        end
      end

      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_o_data
        assign DOT[DATW*(i+1)-1:DATW*i] = {p_preg[P_LOG-1][PAYW*(i+1)-1:PAYW*i], k_preg[P_LOG-1][KEYW*(i+1)-1:KEYW*i]};
      end
    end
  endgenerate

endmodule
module BOEM #(parameter                       P_LOG = 2,
              parameter                       FLOAT  = "no",
              parameter                       SIGNED = "no",
              parameter                       DATW  = 64,
              parameter                       KEYW  = 32)
             (input  wire                     CLK,
              input  wire [(DATW<<P_LOG)-1:0] DIN,
              output wire [(DATW<<P_LOG)-1:0] DOT);


  localparam PAYW = DATW - KEYW;

  genvar i, j, k;
  generate
    if (PAYW == 0) begin
      reg [(DATW<<P_LOG)-1:0] pd [P_LOG-1:0];
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(DATW<<P_LOG)-1:0] dot;
        if (i == 0) begin
          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: pipelined_cas
            if (j == 0) begin
              reg [DATW-1:0] buf0; always @(posedge CLK) buf0 <= DIN[DATW*(j+1)-1:DATW*j];
              reg [DATW-1:0] buf1; always @(posedge CLK) buf1 <= DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))];
              assign dot[DATW*(j+1)-1:DATW*j] = buf0;
              assign dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))] = buf1;
            end else begin
              CAS #(FLOAT, SIGNED, DATW, KEYW)
              cas(
                  CLK,
                  DIN[DATW*(j+1)-1:DATW*j],
                  DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))],
                  dot[DATW*(j+1)-1:DATW*j],
                  dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))]
                  );
            end
          end
          always @(posedge CLK) pd[i] <= dot;
        end else begin
          for (k=0; k<((1<<i)-1); k=k+1) begin: blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: pipelined_cas
              CAS #(FLOAT, SIGNED, DATW, KEYW)
              cas(
                  CLK,
                  pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                  pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                  dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                  dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]
                  );
            end
          end
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_upper_buf;
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_lower_buf;
          always @(posedge CLK) pd_upper_buf <= pd[i-1][(DATW<<P_LOG)-1:DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) pd_lower_buf <= pd[i-1][DATW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) pd[i] <= {pd_upper_buf,
                                          dot[DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:DATW*(1<<(P_LOG-(i+1)))],
                                          pd_lower_buf};
        end
      end
      assign DOT = pd[P_LOG-1];
    end else begin

      wire [(KEYW<<P_LOG)-1:0] i_key;
      wire [(PAYW<<P_LOG)-1:0] i_payload;
      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_i_data
        assign i_key[KEYW*(i+1)-1:KEYW*i] = DIN[(KEYW+DATW*i)-1:DATW*i];
        assign i_payload[PAYW*(i+1)-1:PAYW*i] = DIN[DATW*(i+1)-1:(KEYW+DATW*i)];
      end

      reg [(KEYW<<P_LOG)-1:0] k_preg [P_LOG-1:0];
      reg [(PAYW<<P_LOG)-1:0] p_preg [P_LOG-1:0];
      integer p;
      reg [(PAYW<<P_LOG)-1:0] p_sreg [P_LOG-1:0];
      always @(posedge CLK) begin
        p_sreg[0] <= i_payload;
        for (p=1; p<P_LOG; p=p+1) begin
          p_sreg[p] <= p_sreg[p-1];
        end
      end
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(KEYW<<P_LOG)-1:0] o_key;
        wire [(PAYW<<P_LOG)-1:0] o_payload;
        if (i == 0) begin

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: pipelined_k_cas
            if (j == 0) begin
              reg [KEYW-1:0] k_buf0; always @(posedge CLK) k_buf0 <= i_key[KEYW*(j+1)-1:KEYW*j];
              reg [KEYW-1:0] k_buf1; always @(posedge CLK) k_buf1 <= i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))];
              assign o_key[KEYW*(j+1)-1:KEYW*j] = k_buf0;
              assign o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))] = k_buf1;
            end else begin: k_cas_exists
              wire o_cmp;
              wire i_cmp;
              K_CAS #(FLOAT, SIGNED, KEYW)
              k_cas(
                    CLK,
                    i_key[KEYW*(j+1)-1:KEYW*j],
                    i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                    o_key[KEYW*(j+1)-1:KEYW*j],
                    o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                    o_cmp
                    );
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          always @(posedge CLK) k_preg[i] <= o_key;

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: p_swaps
            if (j == 0) begin
              assign o_payload[PAYW*(j+1)-1:PAYW*j] = p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j];
              assign o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))] = p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))];
            end else begin
              P_SWAP #(PAYW)
              p_swap(
                     pipelined_k_cas[j].k_cas_exists.i_cmp,
                     p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j],
                     p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))],
                     o_payload[PAYW*(j+1)-1:PAYW*j],
                     o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))]
                     );
            end
          end
          always @(posedge CLK) p_preg[i] <= o_payload;
        end else begin

          for (k=0; k<((1<<i)-1); k=k+1) begin: k_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: pipelined_k_cas
              wire o_cmp;
              wire i_cmp;
              K_CAS #(FLOAT, SIGNED, KEYW)
              k_cas(
                    CLK,
                    k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                    k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                    o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                    o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                    o_cmp
                    );
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_upper_buf;
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_lower_buf;
          always @(posedge CLK) k_preg_upper_buf <= k_preg[i-1][(KEYW<<P_LOG)-1:KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) k_preg_lower_buf <= k_preg[i-1][KEYW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) k_preg[i] <= {k_preg_upper_buf,
                                              o_key[KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:KEYW*(1<<(P_LOG-(i+1)))],
                                              k_preg_lower_buf};

          for (k=0; k<((1<<i)-1); k=k+1) begin: p_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: p_swaps
              P_SWAP #(PAYW)
              p_swap(k_blocks[k].pipelined_k_cas[j].i_cmp,
                     p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                     p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                     o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                     o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]
                     );
            end
          end
          always @(posedge CLK) p_preg[i] <= {p_preg[i-1][(PAYW<<P_LOG)-1:PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))],
                                              o_payload[PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:PAYW*(1<<(P_LOG-(i+1)))],
                                              p_preg[i-1][PAYW*(1<<(P_LOG-(i+1)))-1:0]};
        end
      end

      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_o_data
        assign DOT[DATW*(i+1)-1:DATW*i] = {p_preg[P_LOG-1][PAYW*(i+1)-1:PAYW*i], k_preg[P_LOG-1][KEYW*(i+1)-1:KEYW*i]};
      end
    end
  endgenerate

endmodule