data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv:21: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv:29: syntax error, unexpected \'@\'\n        @(negedge CLOCK_50)\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv:36: syntax error, unexpected \';\'\n        for (int i = 0; i < 256; i++)\n                               ^\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv:36: syntax error, unexpected \')\', expecting \';\'\n        for (int i = 0; i < 256; i++)\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_syn_task1.sv:52: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_task1();

    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [31:0] tdo;

    task1 dut(
            .altera_reserved_tms(32'b0),
            .altera_reserved_tck(32'b0),
            .altera_reserved_tdi(32'b0),
            .altera_reserved_tdo(tdo),
            .*
    );

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        err = 1'b0;


        KEY[3] = 1'b0;
        @(negedge CLOCK_50)


        KEY[3] = 1'b1;
        @(posedge CLOCK_50)


        for (int i = 0; i < 256; i++)
            @(posedge CLOCK_50)


        #50;


        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task1.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_syn_task1.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        KEY[3] = 1'bx;
        #10;

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_syn_task1();


    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [31:0] tdo;

    task1 dut(
            .altera_reserved_tms(32'b0),
            .altera_reserved_tck(32'b0),
            .altera_reserved_tdi(32'b0),
            .altera_reserved_tdo(tdo),
            .*
    );

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        err = 1'b0;


        KEY[3] = 1'b0;
        @(negedge CLOCK_50)


        KEY[3] = 1'b1;
        @(posedge CLOCK_50)


        for (int i = 0; i < 256; i++)
            @(posedge CLOCK_50)


        #50;


        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task1.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_syn_task1.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        KEY[3] = 1'bx;
        #10;

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule