data/full_repos/permissive/458737381/src/verilog-parser/tests/srffrl_ns.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/srffrl_ns.v:60: Signal definition not found, creating implicitly: \'dff\'\n  assign q = dff;\n             ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/srffrl_ns.v:58: Cannot find file containing module: \'dffrle_ns\'\n  dffrle_ns dff_reg (.din(next_dff), .en(dff_en), .q(dff), .rst_l(rst_l), .clk(clk));\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrle_ns\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrle_ns.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrle_ns.sv\n             dffrle_ns\n             dffrle_ns.v\n             dffrle_ns.sv\n             obj_dir/dffrle_ns\n             obj_dir/dffrle_ns.v\n             obj_dir/dffrle_ns.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module srffrl_ns (

  q, 

  set, clr, rst_l, clk
  );

  input  set;
  input  clr;
  input  rst_l;
  input  clk;
  output q;











  wire next_dff = set;
  wire dff_en = ( set | clr );

  dffrle_ns dff_reg (.din(next_dff), .en(dff_en), .q(dff), .rst_l(rst_l), .clk(clk));

  assign q = dff;


  endmodule
module srffrl_ns (

  q, 

  set, clr, rst_l, clk
  );


  input  set;
  input  clr;
  input  rst_l;
  input  clk;
  output q;











  wire next_dff = set;
  wire dff_en = ( set | clr );

  dffrle_ns dff_reg (.din(next_dff), .en(dff_en), .q(dff), .rst_l(rst_l), .clk(clk));

  assign q = dff;


  endmodule