data/full_repos/permissive/488739248/rtl/ym3526/jtopl_csr.v
1: b"%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_csr.v:45: Cannot find file containing module: 'jtopl_sh_rst'\njtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_sh_rst\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_sh_rst.v\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_sh_rst.sv\n             jtopl_sh_rst\n             jtopl_sh_rst.v\n             jtopl_sh_rst.sv\n             obj_dir/jtopl_sh_rst\n             obj_dir/jtopl_sh_rst.v\n             obj_dir/jtopl_sh_rst.sv\n%Error: Exiting due to 1 error(s)\n"
module jtopl_csr #(
    parameter LEN=18, W=34
) (
    input wire          rst,
    input wire          clk,
    input wire          cen,
    input wire  [ 7:0]  din,
    output wire [W-1:0]  shift_out,

    input wire          up_mult,
    input wire          up_ksl_tl,
    input wire          up_ar_dr,
    input wire          up_sl_rr,
    input wire          up_wav,
    input wire          update_op_I,
    input wire          update_op_II,
    input wire          update_op_IV
);


wire [W-1:0] regop_in;

jtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(
    .clk    ( clk          ),
    .cen    ( cen          ),
    .rst    ( rst          ),
    .din    ( regop_in     ),
    .drop   ( shift_out    )
);

wire up_mult_I    = up_mult   & update_op_I;
wire up_mult_II   = up_mult   & update_op_II;
wire up_mult_IV   = up_mult   & update_op_IV;
wire up_ksl_tl_IV = up_ksl_tl & update_op_IV;
wire up_ar_dr_op  = up_ar_dr  & update_op_I;
wire up_sl_rr_op  = up_sl_rr  & update_op_I;
wire up_wav_I     = up_wav    & update_op_I;

assign regop_in[31:0] = {
        up_mult_IV  ? din[7]      : shift_out[31],
        up_mult_I   ? din[6:5]    : shift_out[30:29],
        up_mult_II  ? din[4:0]    : shift_out[28:24],

        up_ksl_tl_IV? din         : shift_out[23:16],

        up_ar_dr_op ? din         : shift_out[15: 8],

        up_sl_rr_op ? din         : shift_out[ 7: 0]
    };





endmodule
module jtopl_csr #(
    parameter LEN=18, W=34
) (
    input wire          rst,
    input wire          clk,
    input wire          cen,
    input wire  [ 7:0]  din,
    output wire [W-1:0]  shift_out,

    input wire          up_mult,
    input wire          up_ksl_tl,
    input wire          up_ar_dr,
    input wire          up_sl_rr,
    input wire          up_wav,
    input wire          update_op_I,
    input wire          update_op_II,
    input wire          update_op_IV
);



wire [W-1:0] regop_in;

jtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(
    .clk    ( clk          ),
    .cen    ( cen          ),
    .rst    ( rst          ),
    .din    ( regop_in     ),
    .drop   ( shift_out    )
);

wire up_mult_I    = up_mult   & update_op_I;
wire up_mult_II   = up_mult   & update_op_II;
wire up_mult_IV   = up_mult   & update_op_IV;
wire up_ksl_tl_IV = up_ksl_tl & update_op_IV;
wire up_ar_dr_op  = up_ar_dr  & update_op_I;
wire up_sl_rr_op  = up_sl_rr  & update_op_I;
wire up_wav_I     = up_wav    & update_op_I;

assign regop_in[31:0] = {
        up_mult_IV  ? din[7]      : shift_out[31],
        up_mult_I   ? din[6:5]    : shift_out[30:29],
        up_mult_II  ? din[4:0]    : shift_out[28:24],

        up_ksl_tl_IV? din         : shift_out[23:16],

        up_ar_dr_op ? din         : shift_out[15: 8],

        up_sl_rr_op ? din         : shift_out[ 7: 0]
    };





endmodule