data/full_repos/permissive/427221126/src/AdderTree.v
1: b"%Error: data/full_repos/permissive/427221126/src/AdderTree.v:102: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_l1 (\n      ^~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.sv\n             Add3\n             Add3.v\n             Add3.sv\n             obj_dir/Add3\n             obj_dir/Add3.v\n             obj_dir/Add3.sv\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:114: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_add3_l2 (\n      ^~~~\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:181: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_L0 (\n      ^~~~\n%Error: Exiting due to 3 error(s)\n"
module AdderTree15
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10
  )
  (
    input                       clk       ,
    input                       reset     ,
    input                       en        ,
    input  [15*INWIDTH-1:0]     din       ,
    input                       din_valid ,
    output signed [INWIDTH+4:0] dout      ,
    output                      dout_valid 
  );
  localparam NUM_INPUTS = 15;
  reg   [5:1] din_valid_d;
  wire        add_en;
  genvar      g;
  
  wire signed [INWIDTH-1:0] din_buf  [0:14] ;
  wire signed [INWIDTH+1:0] add_l1_y [0:5]  ;
  wire signed [INWIDTH+3:0] add_l2_y [0:1]  ;
  reg  signed [INWIDTH+4:0] add_l3_y        ;

  generate
    for (g = 0; g < NUM_INPUTS; g = g + 1) begin : input_buffer
      assign din_buf[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
    end

    for (g = 0; g < NUM_INPUTS/3; g = g + 1) begin : l1
      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_l1 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( add_en && en    ),
        .a    ( din_buf[g*3]    ),
        .d    ( din_buf[g*3+1]  ),
        .c    ( din_buf[g*3+2]  ),
        .y    ( add_l1_y[g]     )
      );
    end

    for (g = 0; g < 2; g = g + 1) begin : L2
      Add3 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_add3_l2 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( add_en && en    ),
        .a    ( add_l1_y[g*3]   ),
        .d    ( add_l1_y[g*3+1] ),
        .c    ( add_l1_y[g*3+2] ),
        .y    ( add_l2_y[g]     )
      );
    end

    always @(posedge clk) begin
      if (reset)
        din_valid_d <= 0;
      else if (en)
        din_valid_d <= {din_valid, din_valid_d[5:2]};
    end

    assign add_en = |{din_valid, din_valid_d};
  endgenerate

  assign add_l1_y[5] = $signed({(INWIDTH+2){1'b0}});

  always @(posedge clk) begin
    if (reset)
      add_l3_y <= 0;
    else if (en && add_en)
      add_l3_y <= add_l2_y[0] + add_l2_y[1];
  end

  assign dout = add_l3_y;
  assign dout_valid = din_valid_d[1];
endmodule
module AdderTree15
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10
  )
  (
    input                       clk       ,
    input                       reset     ,
    input                       en        ,
    input  [15*INWIDTH-1:0]     din       ,
    input                       din_valid ,
    output signed [INWIDTH+4:0] dout      ,
    output                      dout_valid 
  );

  localparam NUM_INPUTS = 15;
  reg   [5:1] din_valid_d;
  wire        add_en;
  genvar      g;
  
  wire signed [INWIDTH-1:0] din_buf  [0:14] ;
  wire signed [INWIDTH+1:0] add_l1_y [0:5]  ;
  wire signed [INWIDTH+3:0] add_l2_y [0:1]  ;
  reg  signed [INWIDTH+4:0] add_l3_y        ;

  generate
    for (g = 0; g < NUM_INPUTS; g = g + 1) begin : input_buffer
      assign din_buf[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
    end

    for (g = 0; g < NUM_INPUTS/3; g = g + 1) begin : l1
      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_l1 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( add_en && en    ),
        .a    ( din_buf[g*3]    ),
        .d    ( din_buf[g*3+1]  ),
        .c    ( din_buf[g*3+2]  ),
        .y    ( add_l1_y[g]     )
      );
    end

    for (g = 0; g < 2; g = g + 1) begin : L2
      Add3 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_add3_l2 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( add_en && en    ),
        .a    ( add_l1_y[g*3]   ),
        .d    ( add_l1_y[g*3+1] ),
        .c    ( add_l1_y[g*3+2] ),
        .y    ( add_l2_y[g]     )
      );
    end

    always @(posedge clk) begin
      if (reset)
        din_valid_d <= 0;
      else if (en)
        din_valid_d <= {din_valid, din_valid_d[5:2]};
    end

    assign add_en = |{din_valid, din_valid_d};
  endgenerate

  assign add_l1_y[5] = $signed({(INWIDTH+2){1'b0}});

  always @(posedge clk) begin
    if (reset)
      add_l3_y <= 0;
    else if (en && add_en)
      add_l3_y <= add_l2_y[0] + add_l2_y[1];
  end

  assign dout = add_l3_y;
  assign dout_valid = din_valid_d[1];
endmodule