data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v:95: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                                               : ... In instance rhodium_gain_ctrl\n      load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5\'b000};\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v:110: Cannot find file containing module: \'rhodium_gain_table\'\nrhodium_gain_table gain_table(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld,data/full_repos/permissive/447976230/rhodium_gain_table\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld,data/full_repos/permissive/447976230/rhodium_gain_table.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/dboards/rh/cpld,data/full_repos/permissive/447976230/rhodium_gain_table.sv\n             rhodium_gain_table\n             rhodium_gain_table.v\n             rhodium_gain_table.sv\n             obj_dir/rhodium_gain_table\n             obj_dir/rhodium_gain_table.v\n             obj_dir/rhodium_gain_table.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module rhodium_gain_ctrl
#(
  parameter TABLE_NUM = 2'b01
) (
  input  wire       load_table_sel,
  input  wire       load_sck,
  input  wire       load_csb,
  input  wire       load_mosi,
  output wire       load_miso,
  input  wire       ctrl_table_sel,
  input  wire       ctrl_sck,
  input  wire       ctrl_csb,
  input  wire       ctrl_mosi,
  output reg        ctrl_miso,
  output wire [4:0] dsa,
  output reg        dsa1_le,
  output reg        dsa2_le
);

localparam CNT_GAIN1_DRIVE = 10,
           CNT_DSA1_LE_RISE = 11,
           CNT_DSA1_LE_FALL = 14,
           CNT_GAIN1_RELEASE = 17;
localparam CNT_GAIN2_DRIVE = 17,
           CNT_DSA2_LE_RISE = 18,
           CNT_DSA2_LE_FALL = 21,
           CNT_GAIN2_RELEASE = 24;


reg  [4:0]  load_bit_cnt;
reg  [1:0]  load_tbl;
reg  [5:0]  load_index;
reg  [15:0] load_rd_data;
reg  [4:0]  load_dsa1;
reg  [4:0]  load_dsa2;
wire [4:0]  load_dsa1_prev;
wire [4:0]  load_dsa2_prev;

assign load_miso = load_rd_data[15];

wire wr_en;
assign wr_en = (!load_csb) && (load_tbl == TABLE_NUM) && (load_bit_cnt == 20) && (load_mosi);


always @ (posedge load_sck or posedge load_csb)
begin
  if (load_csb) begin
    load_bit_cnt <= 5'd0;
  end else if (!load_csb) begin
    {load_dsa1, load_dsa2} <= {load_dsa1[3:0], load_dsa2, load_mosi};

    if (load_bit_cnt < 23) begin
      load_bit_cnt <= load_bit_cnt + 5'd1;
    end
    if (load_bit_cnt < 8) begin
      {load_tbl, load_index} <= {load_tbl[0], load_index, load_mosi};
    end
  end
end


always @ (negedge load_sck)
begin
    if (load_bit_cnt == 9) begin
      load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5'b000};
    end else begin
      load_rd_data <= {load_rd_data[14:0], 1'b0};
    end
end


wire [4:0] ctrl_dsa1;
wire [4:0] ctrl_dsa2;


rhodium_gain_table gain_table(
  .wr_clk(load_sck),
  .wr_en(wr_en),
  .wr_addr({load_table_sel, load_index}),
  .wr_data({load_dsa1, load_dsa2}),
  .wr_data_prev({load_dsa1_prev, load_dsa2_prev}),
  .rd_clk(ctrl_sck),
  .rd_addr({ctrl_table_sel, ctrl_index}),
  .rd_data({ctrl_dsa1, ctrl_dsa2})
);


reg  [4:0]  ctrl_bit_cnt;
reg  [1:0]  ctrl_tbl;
reg  [5:0]  ctrl_index;

reg [5:0] gain1;
reg [5:0] gain2;
reg gain1_t;
reg gain2_t;

assign dsa = !gain1_t ? ctrl_dsa1 :
            (!gain2_t ? ctrl_dsa2 :
                        5'b11111);



always @ (posedge ctrl_sck or posedge ctrl_csb)
begin
  if (ctrl_csb) begin
    ctrl_bit_cnt <= 5'd0;
    dsa1_le      <= 1'b0;
    dsa2_le      <= 1'b0;
    gain1_t      <= 1'b1;
    gain2_t      <= 1'b1;
  end else if (!ctrl_csb) begin
    if (ctrl_bit_cnt < 23) begin
      ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1;
    end

    if (ctrl_bit_cnt < 8) begin
      {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi};
    end

    if (ctrl_tbl == TABLE_NUM) begin
      if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin
        gain1   <= ctrl_index;
        gain1_t <= 1'b0;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin
        dsa1_le <= 1'b1;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin
        dsa1_le <= 1'b0;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin
        gain1_t <= 1'b1;
      end

      if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin
        gain2   <= ctrl_index;
        gain2_t <= 1'b0;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin
        dsa2_le <= 1'b1;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin
        dsa2_le <= 1'b0;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin
        gain2_t <= 1'b1;
      end
    end
  end
end


always @ (negedge ctrl_sck)
begin
  case (ctrl_bit_cnt)
  11:      ctrl_miso <= gain1[5];
  12:      ctrl_miso <= gain1[4];
  13:      ctrl_miso <= gain1[3];
  14:      ctrl_miso <= gain1[2];
  15:      ctrl_miso <= gain1[1];
  16:      ctrl_miso <= gain1[0];
  18:      ctrl_miso <= gain2[5];
  19:      ctrl_miso <= gain2[4];
  20:      ctrl_miso <= gain2[3];
  21:      ctrl_miso <= gain2[2];
  22:      ctrl_miso <= gain2[1];
  23:      ctrl_miso <= gain2[0];
  default: ctrl_miso <= 1'b0;
  endcase
end

endmodule
module rhodium_gain_ctrl
#(
  parameter TABLE_NUM = 2'b01
) (
  input  wire       load_table_sel,
  input  wire       load_sck,
  input  wire       load_csb,
  input  wire       load_mosi,
  output wire       load_miso,
  input  wire       ctrl_table_sel,
  input  wire       ctrl_sck,
  input  wire       ctrl_csb,
  input  wire       ctrl_mosi,
  output reg        ctrl_miso,
  output wire [4:0] dsa,
  output reg        dsa1_le,
  output reg        dsa2_le
);


localparam CNT_GAIN1_DRIVE = 10,
           CNT_DSA1_LE_RISE = 11,
           CNT_DSA1_LE_FALL = 14,
           CNT_GAIN1_RELEASE = 17;
localparam CNT_GAIN2_DRIVE = 17,
           CNT_DSA2_LE_RISE = 18,
           CNT_DSA2_LE_FALL = 21,
           CNT_GAIN2_RELEASE = 24;


reg  [4:0]  load_bit_cnt;
reg  [1:0]  load_tbl;
reg  [5:0]  load_index;
reg  [15:0] load_rd_data;
reg  [4:0]  load_dsa1;
reg  [4:0]  load_dsa2;
wire [4:0]  load_dsa1_prev;
wire [4:0]  load_dsa2_prev;

assign load_miso = load_rd_data[15];

wire wr_en;
assign wr_en = (!load_csb) && (load_tbl == TABLE_NUM) && (load_bit_cnt == 20) && (load_mosi);


always @ (posedge load_sck or posedge load_csb)
begin
  if (load_csb) begin
    load_bit_cnt <= 5'd0;
  end else if (!load_csb) begin
    {load_dsa1, load_dsa2} <= {load_dsa1[3:0], load_dsa2, load_mosi};

    if (load_bit_cnt < 23) begin
      load_bit_cnt <= load_bit_cnt + 5'd1;
    end
    if (load_bit_cnt < 8) begin
      {load_tbl, load_index} <= {load_tbl[0], load_index, load_mosi};
    end
  end
end


always @ (negedge load_sck)
begin
    if (load_bit_cnt == 9) begin
      load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5'b000};
    end else begin
      load_rd_data <= {load_rd_data[14:0], 1'b0};
    end
end


wire [4:0] ctrl_dsa1;
wire [4:0] ctrl_dsa2;


rhodium_gain_table gain_table(
  .wr_clk(load_sck),
  .wr_en(wr_en),
  .wr_addr({load_table_sel, load_index}),
  .wr_data({load_dsa1, load_dsa2}),
  .wr_data_prev({load_dsa1_prev, load_dsa2_prev}),
  .rd_clk(ctrl_sck),
  .rd_addr({ctrl_table_sel, ctrl_index}),
  .rd_data({ctrl_dsa1, ctrl_dsa2})
);


reg  [4:0]  ctrl_bit_cnt;
reg  [1:0]  ctrl_tbl;
reg  [5:0]  ctrl_index;

reg [5:0] gain1;
reg [5:0] gain2;
reg gain1_t;
reg gain2_t;

assign dsa = !gain1_t ? ctrl_dsa1 :
            (!gain2_t ? ctrl_dsa2 :
                        5'b11111);



always @ (posedge ctrl_sck or posedge ctrl_csb)
begin
  if (ctrl_csb) begin
    ctrl_bit_cnt <= 5'd0;
    dsa1_le      <= 1'b0;
    dsa2_le      <= 1'b0;
    gain1_t      <= 1'b1;
    gain2_t      <= 1'b1;
  end else if (!ctrl_csb) begin
    if (ctrl_bit_cnt < 23) begin
      ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1;
    end

    if (ctrl_bit_cnt < 8) begin
      {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi};
    end

    if (ctrl_tbl == TABLE_NUM) begin
      if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin
        gain1   <= ctrl_index;
        gain1_t <= 1'b0;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin
        dsa1_le <= 1'b1;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin
        dsa1_le <= 1'b0;
      end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin
        gain1_t <= 1'b1;
      end

      if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin
        gain2   <= ctrl_index;
        gain2_t <= 1'b0;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin
        dsa2_le <= 1'b1;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin
        dsa2_le <= 1'b0;
      end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin
        gain2_t <= 1'b1;
      end
    end
  end
end


always @ (negedge ctrl_sck)
begin
  case (ctrl_bit_cnt)
  11:      ctrl_miso <= gain1[5];
  12:      ctrl_miso <= gain1[4];
  13:      ctrl_miso <= gain1[3];
  14:      ctrl_miso <= gain1[2];
  15:      ctrl_miso <= gain1[1];
  16:      ctrl_miso <= gain1[0];
  18:      ctrl_miso <= gain2[5];
  19:      ctrl_miso <= gain2[4];
  20:      ctrl_miso <= gain2[3];
  21:      ctrl_miso <= gain2[2];
  22:      ctrl_miso <= gain2[1];
  23:      ctrl_miso <= gain2[0];
  default: ctrl_miso <= 1'b0;
  endcase
end

endmodule