data/full_repos/permissive/469979476/language/13.v
data/verilator_xmls/2327209f-d4c0-4c6f-9f2a-2b3c8320fd89.xml
module top_module( 
    input [31:0] in,
    output [31:0] out );


    assign out = in<<8;
endmodule
module top_module( 
    input [31:0] in,
    output [31:0] out );



    assign out = in<<8;
endmodule