data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:2: Cannot find include file: NOR_G.v\n`include "NOR_G.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate,data/full_repos/permissive/414867793/NOR_G.v\n             data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate,data/full_repos/permissive/414867793/NOR_G.v.v\n             data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate,data/full_repos/permissive/414867793/NOR_G.v.sv\n             NOR_G.v\n             NOR_G.v.v\n             NOR_G.v.sv\n             obj_dir/NOR_G.v\n             obj_dir/NOR_G.v.v\n             obj_dir/NOR_G.v.sv\n%Error: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("NOR_G_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1,NOR_G_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module NOR_G_tb();

reg A,B;
wire C;
NOR_G uut(A,B,C);

initial begin
  $dumpfile("NOR_G_tb.vcd");
  $dumpvars(1,NOR_G_tb);

  A=0;
  B=0;
  #20
  A=1;
  B=0;
  #20
  A=0;
  B=1;
  #20
  A=1;
  B=1;
  #20

  $display("done testing");
  
end

endmodule
module NOR_G_tb();


reg A,B;
wire C;
NOR_G uut(A,B,C);

initial begin
  $dumpfile("NOR_G_tb.vcd");
  $dumpvars(1,NOR_G_tb);

  A=0;
  B=0;
  #20
  A=1;
  B=0;
  #20
  A=0;
  B=1;
  #20
  A=1;
  B=1;
  #20

  $display("done testing");
  
end

endmodule