data/full_repos/permissive/514775464/inputCapture.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514775464/inputCapture.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                      : ... In instance input_capture\n       val<=4\'b0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter(clk,reset,count);
  input clk,reset;

  output reg [7:0] count;
  
  always@(posedge clk ) begin
    if(reset)
      count <= 0;
    else
      count <= count + 1;
  end
  
endmodule
module counter(clk,reset,count);

  input clk,reset;

  output reg [7:0] count;
  
  always@(posedge clk ) begin
    if(reset)
      count <= 0;
    else
      count <= count + 1;
  end
  
endmodule