data/full_repos/permissive/492140037/CPU/设计文件/MemOrIO.v
data/verilator_xmls/692c2715-27f5-4212-9984-fb9203a4fe30.xml
module MemOrIO(mRead, mWrite, ioRead, ioWrite,addr_in, addr_out, m_rdata, io_rdata, r_wdata, r_rdata, write_data, LEDCtrl, SwitchCtrl);
input mRead;
input mWrite;
input ioRead;
input ioWrite;
input[31:0] addr_in;
output[31:0] addr_out;

input[31:0] m_rdata;
input[15:0] io_rdata;
output[31:0] r_wdata;

input[31:0] r_rdata;

output reg[31:0] write_data;
output LEDCtrl;
output SwitchCtrl;

assign addr_out = addr_in;

assign r_wdata = ioRead ? {16'h0000, io_rdata} : m_rdata;

assign LEDCtrl = ioWrite ? 1'b1 : 1'b0;
assign SwitchCtrl = ioRead ? 1'b1 : 1'b0;

always @(*) begin
    if((mWrite == 1)||(ioWrite == 1)) begin

        write_data = mWrite ? r_rdata : {16'h0000, r_rdata[15:0]};
    end
    else begin
        write_data = 32'hZZZZ_ZZZZ;

    end
end

endmodule
module MemOrIO(mRead, mWrite, ioRead, ioWrite,addr_in, addr_out, m_rdata, io_rdata, r_wdata, r_rdata, write_data, LEDCtrl, SwitchCtrl);

input mRead;
input mWrite;
input ioRead;
input ioWrite;
input[31:0] addr_in;
output[31:0] addr_out;

input[31:0] m_rdata;
input[15:0] io_rdata;
output[31:0] r_wdata;

input[31:0] r_rdata;

output reg[31:0] write_data;
output LEDCtrl;
output SwitchCtrl;

assign addr_out = addr_in;

assign r_wdata = ioRead ? {16'h0000, io_rdata} : m_rdata;

assign LEDCtrl = ioWrite ? 1'b1 : 1'b0;
assign SwitchCtrl = ioRead ? 1'b1 : 1'b0;

always @(*) begin
    if((mWrite == 1)||(ioWrite == 1)) begin

        write_data = mWrite ? r_rdata : {16'h0000, r_rdata[15:0]};
    end
    else begin
        write_data = 32'hZZZZ_ZZZZ;

    end
end

endmodule