data/full_repos/permissive/470392519/tests/sub/ImmGen.v
1: b'%Error: data/full_repos/permissive/470392519/tests/sub/ImmGen.v:1: Cannot find include file: ImmGen.v\n`include "ImmGen.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ImmGen.v\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ImmGen.v.v\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ImmGen.v.sv\n             ImmGen.v\n             ImmGen.v.v\n             ImmGen.v.sv\n             obj_dir/ImmGen.v\n             obj_dir/ImmGen.v.v\n             obj_dir/ImmGen.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/470392519/tests/sub/ImmGen.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/470392519/tests/sub/ImmGen.v:32: Unsupported: Ignoring delay on this delayed statement.\n            i_instr = test_vector[i]; #20;\n                                      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module ImmGen_tb;
    reg     [31:0]  i_instr;
    wire    [31:0]  o_imm;

    ImmGen ImmGen_dut(.*);

`ifdef DUMP_VCD
    initial begin
        $dumpfile("obj_dir/sub/ImmGen.vcd");
        $dumpvars;
    end
`endif


    reg [31:0]  test_vector         [0:26];
    reg [31:0]  test_gold_vector    [0:26];
    initial begin
        $readmemh("obj_dir/sub/sub_ImmGen.mem", test_vector);
        $readmemb("obj_dir/sub/sub_ImmGen_gold.mem", test_gold_vector);
    end


    reg [39:0] resultStr;
    integer i = 0, errs = 0;
    initial begin
        $display("Running random ImmGen tests...\n");
        i_instr   = 'd0;
        #20;
        for (i=0; i<27; i=i+1) begin
            i_instr = test_vector[i]; #20;
            if ($signed(o_imm) != $signed(test_gold_vector[i])) resultStr = "ERROR";
            else                                                resultStr = "PASS ";
            $display("Test[ %2d ]: i_instr = 0x%8h || o_imm = %b ... %s",
                i, i_instr, $signed(o_imm), resultStr
            );
            if (resultStr == "ERROR") errs = errs + 1;
        end
        if (errs > 0)   $display("\nFAILED: %0d", errs);
        else            $display("\nPASSED");

    end

endmodule
module ImmGen_tb;

    reg     [31:0]  i_instr;
    wire    [31:0]  o_imm;

    ImmGen ImmGen_dut(.*);

`ifdef DUMP_VCD
    initial begin
        $dumpfile("obj_dir/sub/ImmGen.vcd");
        $dumpvars;
    end
`endif


    reg [31:0]  test_vector         [0:26];
    reg [31:0]  test_gold_vector    [0:26];
    initial begin
        $readmemh("obj_dir/sub/sub_ImmGen.mem", test_vector);
        $readmemb("obj_dir/sub/sub_ImmGen_gold.mem", test_gold_vector);
    end


    reg [39:0] resultStr;
    integer i = 0, errs = 0;
    initial begin
        $display("Running random ImmGen tests...\n");
        i_instr   = 'd0;
        #20;
        for (i=0; i<27; i=i+1) begin
            i_instr = test_vector[i]; #20;
            if ($signed(o_imm) != $signed(test_gold_vector[i])) resultStr = "ERROR";
            else                                                resultStr = "PASS ";
            $display("Test[ %2d ]: i_instr = 0x%8h || o_imm = %b ... %s",
                i, i_instr, $signed(o_imm), resultStr
            );
            if (resultStr == "ERROR") errs = errs + 1;
        end
        if (errs > 0)   $display("\nFAILED: %0d", errs);
        else            $display("\nPASSED");

    end

endmodule