data/full_repos/permissive/443770883/lab1/a.v
data/verilator_xmls/bb1c118c-eb4c-4f62-9297-ece8d18c8c9b.xml
module and1(input wire a,b,output wire w, x, y, z);
assign w=a&b;
assign x=a|b;
assign y=~(a&b);
assign z=~(a|b);
endmodule
module and1(input wire a,b,output wire w, x, y, z);

assign w=a&b;
assign x=a|b;
assign y=~(a&b);
assign z=~(a|b);
endmodule