data/full_repos/permissive/42581625/PersonalComputer/RegisterFile.v
data/verilator_xmls/5d292f9c-a9c0-48ee-88a5-d807bd1f6b69.xml
module RegisterFile(
input clk,
input[4:0] R1,
input[4:0] R2,
input[4:0] WR,
input[31:0] Wdata,
input we,
output[31:0] Rdata1,
output[31:0] Rdata2,
input[4:0] R3,
output[31:0] Rdata3
    );
reg[31:0] regs[31:0];
assign Rdata1 = regs[R1[4:0]];
assign Rdata2 = regs[R2[4:0]];
assign Rdata3 = regs[R3[4:0]];

initial begin
$readmemh("RegisterFile.coe", regs);
end

always@(posedge clk) begin
	if(we)
		regs[WR] <= Wdata;
end

endmodule
module RegisterFile(
input clk,
input[4:0] R1,
input[4:0] R2,
input[4:0] WR,
input[31:0] Wdata,
input we,
output[31:0] Rdata1,
output[31:0] Rdata2,
input[4:0] R3,
output[31:0] Rdata3
    );

reg[31:0] regs[31:0];
assign Rdata1 = regs[R1[4:0]];
assign Rdata2 = regs[R2[4:0]];
assign Rdata3 = regs[R3[4:0]];

initial begin
$readmemh("RegisterFile.coe", regs);
end

always@(posedge clk) begin
	if(we)
		regs[WR] <= Wdata;
end

endmodule