data/full_repos/permissive/521867481/src/Uart8Transmitter.v
1: b'%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:4: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:5: Cannot find include file: src/Uart8Transmitter.v\n`include "src/Uart8Transmitter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:8: Define or directive not defined: \'`DATA_BITS_8\'\n        parameter DATA_BITS = `DATA_BITS_8  \n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )(\n    ^\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire                   en,        \n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire                   start,     \n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire [DATA_BITS - 1:0] in,        \n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output reg                   out,       \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n        output reg                   done,      \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n        output reg                   busy       \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:19: Define or directive not defined: \'`STATE_RESET\'\n    reg [2:0] state  = `STATE_RESET;\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [2:0] state  = `STATE_RESET;\n                                   ^\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:26: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:34: Define or directive not defined: \'`STATE_IDLE\'\n            `STATE_IDLE: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:42: Define or directive not defined: \'`STATE_START_BIT\'\n                    state <= `STATE_START_BIT;\n                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:46: Define or directive not defined: \'`STATE_START_BIT\'\n            `STATE_START_BIT: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:49: Define or directive not defined: \'`STATE_DATA_BITS\'\n                state <= `STATE_DATA_BITS;\n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:52: Define or directive not defined: \'`STATE_DATA_BITS\'\n            `STATE_DATA_BITS: begin  \n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:56: Define or directive not defined: \'`STATE_STOP_BIT\'\n                    state  <= `STATE_STOP_BIT;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:62: Define or directive not defined: \'`STATE_STOP_BIT\'\n            `STATE_STOP_BIT: begin  \n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:66: Define or directive not defined: \'`STATE_IDLE\'\n                state <= `STATE_IDLE;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Transmitter.v:70: Define or directive not defined: \'`STATE_IDLE\'\n                state <= `STATE_IDLE;\n                         ^~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module Uart8Transmitter #(
        parameter DATA_BITS = `DATA_BITS_8
    )(
        input wire                   clk,
        input wire                   en,
        input wire                   start,
        input wire [DATA_BITS - 1:0] in,
        output reg                   out,
        output reg                   done,
        output reg                   busy
    );

    reg [2:0] state  = `STATE_RESET;
    reg [7:0] data   = 0;

    localparam DATA_BITS_WIDTH = $clog2(DATA_BITS);

    reg [DATA_BITS_WIDTH - 1:0] bitIdx = 0;

    initial begin
        out  <= 1;
        done <= 0;
        busy <= 0;
    end

    always @ (posedge clk) begin
        case (state)
            `STATE_IDLE: begin
                out    <= 1;
                done   <= 0;
                busy   <= 0;
                bitIdx <= 0;
                data   <= 0;
                if (start & en) begin
                    data  <= in;
                    state <= `STATE_START_BIT;
                end
            end

            `STATE_START_BIT: begin
                out   <= 1'b0;
                busy  <= 1'b1;
                state <= `STATE_DATA_BITS;
            end

            `STATE_DATA_BITS: begin
                out <= data[bitIdx];
                if (&bitIdx) begin
                    bitIdx <= 0;
                    state  <= `STATE_STOP_BIT;
                end else begin
                    bitIdx <= bitIdx + 1'b1;
                end
            end

            `STATE_STOP_BIT: begin
                done  <= 1'b1;
                data  <= 8'b0;
                out   <= 1'b1;
                state <= `STATE_IDLE;
            end

            default:
                state <= `STATE_IDLE;
        endcase
    end

endmodule
module Uart8Transmitter #(
        parameter DATA_BITS = `DATA_BITS_8
    )(
        input wire                   clk,
        input wire                   en,
        input wire                   start,
        input wire [DATA_BITS - 1:0] in,
        output reg                   out,
        output reg                   done,
        output reg                   busy
    );


    reg [2:0] state  = `STATE_RESET;
    reg [7:0] data   = 0;

    localparam DATA_BITS_WIDTH = $clog2(DATA_BITS);

    reg [DATA_BITS_WIDTH - 1:0] bitIdx = 0;

    initial begin
        out  <= 1;
        done <= 0;
        busy <= 0;
    end

    always @ (posedge clk) begin
        case (state)
            `STATE_IDLE: begin
                out    <= 1;
                done   <= 0;
                busy   <= 0;
                bitIdx <= 0;
                data   <= 0;
                if (start & en) begin
                    data  <= in;
                    state <= `STATE_START_BIT;
                end
            end

            `STATE_START_BIT: begin
                out   <= 1'b0;
                busy  <= 1'b1;
                state <= `STATE_DATA_BITS;
            end

            `STATE_DATA_BITS: begin
                out <= data[bitIdx];
                if (&bitIdx) begin
                    bitIdx <= 0;
                    state  <= `STATE_STOP_BIT;
                end else begin
                    bitIdx <= bitIdx + 1'b1;
                end
            end

            `STATE_STOP_BIT: begin
                done  <= 1'b1;
                data  <= 8'b0;
                out   <= 1'b1;
                state <= `STATE_IDLE;
            end

            default:
                state <= `STATE_IDLE;
        endcase
    end

endmodule