data/full_repos/permissive/436123010/simulation_sources/CPU_SIM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436123010/simulation_sources/CPU_SIM.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436123010/simulation_sources/CPU_SIM.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 left_button_display_data = ~left_button_display_data;\n    ^\n%Error: data/full_repos/permissive/436123010/simulation_sources/CPU_SIM.v:26: Cannot find file containing module: \'CPU\'\n    CPU CPU_SIMULATION(clk,\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/436123010/simulation_sources,data/full_repos/permissive/436123010/CPU\n             data/full_repos/permissive/436123010/simulation_sources,data/full_repos/permissive/436123010/CPU.v\n             data/full_repos/permissive/436123010/simulation_sources,data/full_repos/permissive/436123010/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_SIM();
    reg clk;
    reg left_button_display_data;
    reg center_button_enable_sort;    
    wire [7:0] instruction_counter;
    wire finished_sort;    
    wire clk_enable;

    wire [6:0] DisplaySeg;
    wire [3:0] DisplayAnode;
    


    
    CPU CPU_SIMULATION(clk,
    left_button_display_data,
    center_button_enable_sort,
    instruction_counter,
    finished_sort,    
    clk_enable,    
    DisplaySeg,
    DisplayAnode);
   
    initial 
    begin
     clk = 0; 
     center_button_enable_sort = 1;   
     left_button_display_data = 0;     
    end
    always 
    begin 
    #10 clk = ~clk;
    #10 left_button_display_data = ~left_button_display_data;
    end
endmodule
module CPU_SIM();

    reg clk;
    reg left_button_display_data;
    reg center_button_enable_sort;    
    wire [7:0] instruction_counter;
    wire finished_sort;    
    wire clk_enable;

    wire [6:0] DisplaySeg;
    wire [3:0] DisplayAnode;
    


    
    CPU CPU_SIMULATION(clk,
    left_button_display_data,
    center_button_enable_sort,
    instruction_counter,
    finished_sort,    
    clk_enable,    
    DisplaySeg,
    DisplayAnode);
   
    initial 
    begin
     clk = 0; 
     center_button_enable_sort = 1;   
     left_button_display_data = 0;     
    end
    always 
    begin 
    #10 clk = ~clk;
    #10 left_button_display_data = ~left_button_display_data;
    end
endmodule