data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_Add_4Sx2S_5S_4.v
data/verilator_xmls/44ac696e-b010-4579-895b-c71277923ec1.xml
module dut_Add_4Sx2S_5S_4 (
	in2,
	in1,
	out1
	);
input [3:0] in2;
input [1:0] in1;
output [4:0] out1;
wire [4:0] asc001;

assign asc001 = 
	+({in2[3], in2})
	+({{3{in1[1]}}, in1});

assign out1 = asc001;
endmodule
module dut_Add_4Sx2S_5S_4 (
	in2,
	in1,
	out1
	);

input [3:0] in2;
input [1:0] in1;
output [4:0] out1;
wire [4:0] asc001;

assign asc001 = 
	+({in2[3], in2})
	+({{3{in1[1]}}, in1});

assign out1 = asc001;
endmodule