data/full_repos/permissive/427281804/CORDIC/rtl/CORDIC_pipeline_FA.v
1: b"%Error: data/full_repos/permissive/427281804/CORDIC/rtl/CORDIC_pipeline_FA.v:105: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nwire [Nz-1:0] deg90  = ; \n                       ^\n%Error: data/full_repos/permissive/427281804/CORDIC/rtl/CORDIC_pipeline_FA.v:106: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nwire [Nz-1:0] deg180 = ; \n                       ^\n%Error: data/full_repos/permissive/427281804/CORDIC/rtl/CORDIC_pipeline_FA.v:107: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nwire [Nz-1:0] deg270 = ; \n                       ^\n%Error: data/full_repos/permissive/427281804/CORDIC/rtl/CORDIC_pipeline_FA.v:108: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nwire [Nz-1:0] deg360 = ; \n                       ^\n%Error: Exiting due to 4 error(s)\n"
module CORDIC_pipeline_stage #(
    parameter Nxy = 32,
    parameter Nz  = 32,
    parameter stn = 0
)(

    input            clk,
    input  [Nxy-1:0] xi,
    input  [Nxy-1:0] yi,
    input  [Nz-1 :0] zi,
    output [Nxy-1:0] xo_r,
    output [Nxy-1:0] yo_r,
    output [Nz-1 :0] zo_r
);

reg [Nz-1:0] zROM;
always @* begin
    case (stn)
        00: zROM = 32'b10110100000000000000000000000000;
        01: zROM = 32'b01101010010000101001110011000110;
        02: zROM = 32'b00111000001001010001110100000001;
        03: zROM = 32'b00011100100000000000010001001001;
        04: zROM = 32'b00001110010011100010101010011001;
        05: zROM = 32'b00000111001010001101111001010011;
        06: zROM = 32'b00000011100101001010100001101010;
        07: zROM = 32'b00000001110010100101101101011110;
        08: zROM = 32'b00000000111001010010111010010100;
        09: zROM = 32'b00000000011100101001011101100110;
        10: zROM = 32'b00000000001110010100101110110111;
        11: zROM = 32'b00000000000111001010010111011011;
        12: zROM = 32'b00000000000011100101001011101110;
        13: zROM = 32'b00000000000001110010100101110111;
        14: zROM = 32'b00000000000000111001010010111011;
        15: zROM = 32'b00000000000000011100101001011101;
        16: zROM = 32'b00000000000000001110010100101110;
        17: zROM = 32'b00000000000000000111001010010111;
        18: zROM = 32'b00000000000000000011100101001011;
        19: zROM = 32'b00000000000000000001110010100101;
        20: zROM = 32'b00000000000000000000111001010010;
        21: zROM = 32'b00000000000000000000011100101001;
        22: zROM = 32'b00000000000000000000001110010100;
        23: zROM = 32'b00000000000000000000000111001010;
        24: zROM = 32'b00000000000000000000000011100101;
        25: zROM = 32'b00000000000000000000000001110010;
        26: zROM = 32'b00000000000000000000000000111001;
        27: zROM = 32'b00000000000000000000000000011100;
        28: zROM = 32'b00000000000000000000000000001110;
        29: zROM = 32'b00000000000000000000000000000111;
        30: zROM = 32'b00000000000000000000000000000011;
        31: zROM = 32'b00000000000000000000000000000001;
    endcase
end

wire dir = zi[Nz-1];
reg signed [Nxy-1:0] xo_r, yo_r;
reg signed [Nxy-1:0] xn, yn;
reg signed [Nz-1 :0] zo_r, zn;
always @ (posedge clk) begin
    {xo_r, yo_r, zo_r} <= {xn, yn, zn};
end

always @* begin
    if (dir==0) begin
        xn = xi - (yi>>>stn);
        yn = yi + (xi>>>stn);
        zn = zi - zROM;
    end else begin
        xn = xi + (yi>>>stn);
        yn = yi - (xi>>>stn);
        zn = zi + zROM;
    end
end

endmodule
module CORDIC_pipeline_stage #(
    parameter Nxy = 32,
    parameter Nz  = 32,
    parameter stn = 0
)(

    input            clk,
    input  [Nxy-1:0] xi,
    input  [Nxy-1:0] yi,
    input  [Nz-1 :0] zi,
    output [Nxy-1:0] xo_r,
    output [Nxy-1:0] yo_r,
    output [Nz-1 :0] zo_r
);


reg [Nz-1:0] zROM;
always @* begin
    case (stn)
        00: zROM = 32'b10110100000000000000000000000000;
        01: zROM = 32'b01101010010000101001110011000110;
        02: zROM = 32'b00111000001001010001110100000001;
        03: zROM = 32'b00011100100000000000010001001001;
        04: zROM = 32'b00001110010011100010101010011001;
        05: zROM = 32'b00000111001010001101111001010011;
        06: zROM = 32'b00000011100101001010100001101010;
        07: zROM = 32'b00000001110010100101101101011110;
        08: zROM = 32'b00000000111001010010111010010100;
        09: zROM = 32'b00000000011100101001011101100110;
        10: zROM = 32'b00000000001110010100101110110111;
        11: zROM = 32'b00000000000111001010010111011011;
        12: zROM = 32'b00000000000011100101001011101110;
        13: zROM = 32'b00000000000001110010100101110111;
        14: zROM = 32'b00000000000000111001010010111011;
        15: zROM = 32'b00000000000000011100101001011101;
        16: zROM = 32'b00000000000000001110010100101110;
        17: zROM = 32'b00000000000000000111001010010111;
        18: zROM = 32'b00000000000000000011100101001011;
        19: zROM = 32'b00000000000000000001110010100101;
        20: zROM = 32'b00000000000000000000111001010010;
        21: zROM = 32'b00000000000000000000011100101001;
        22: zROM = 32'b00000000000000000000001110010100;
        23: zROM = 32'b00000000000000000000000111001010;
        24: zROM = 32'b00000000000000000000000011100101;
        25: zROM = 32'b00000000000000000000000001110010;
        26: zROM = 32'b00000000000000000000000000111001;
        27: zROM = 32'b00000000000000000000000000011100;
        28: zROM = 32'b00000000000000000000000000001110;
        29: zROM = 32'b00000000000000000000000000000111;
        30: zROM = 32'b00000000000000000000000000000011;
        31: zROM = 32'b00000000000000000000000000000001;
    endcase
end

wire dir = zi[Nz-1];
reg signed [Nxy-1:0] xo_r, yo_r;
reg signed [Nxy-1:0] xn, yn;
reg signed [Nz-1 :0] zo_r, zn;
always @ (posedge clk) begin
    {xo_r, yo_r, zo_r} <= {xn, yn, zn};
end

always @* begin
    if (dir==0) begin
        xn = xi - (yi>>>stn);
        yn = yi + (xi>>>stn);
        zn = zi - zROM;
    end else begin
        xn = xi + (yi>>>stn);
        yn = yi - (xi>>>stn);
        zn = zi + zROM;
    end
end

endmodule