data/full_repos/permissive/463204869/units/util/source/rtl/verilog/util_clkbuf.v
data/verilator_xmls/c217b97a-9b02-41e0-b12f-dde30fb27878.xml
module util_clkbuf #(
    parameter DELAY = 0.1
)(
    input  wire clk_i,
    output wire clk_o
);

    assign

        #DELAY

        clk_o = clk_i;


endmodule
module util_clkbuf #(
    parameter DELAY = 0.1
)(
    input  wire clk_i,
    output wire clk_o
);


    assign

        #DELAY

        clk_o = clk_i;


endmodule