data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:7: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'wreduce_test0\'\nmodule wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);\n       ^~~~~~~~~~~~~\n                                                                                          : ... Top module \'wreduce_test1\'\nmodule wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w);\n       ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:8: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                       : ... In instance wreduce_test1\n  assign x = a - b, y = a * b, z = a >> b, w = a << b;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:8: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 bits.\n                                                                                       : ... In instance wreduce_test1\n  assign x = a - b, y = a * b, z = a >> b, w = a << b;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:8: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                       : ... In instance wreduce_test1\n  assign x = a - b, y = a * b, z = a >> b, w = a << b;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:8: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 32 bits.\n                                                                                       : ... In instance wreduce_test1\n  assign x = a - b, y = a * b, z = a >> b, w = a << b;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:2: Operator NEGATE expects 16 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n                                                                                       : ... In instance wreduce_test0\n  assign x = -$signed({1\'b0, a});\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:3: Operator ADD expects 16 bits on the LHS, but LHS\'s SIGNED generates 9 bits.\n                                                                                       : ... In instance wreduce_test0\n  assign y = $signed({1\'b0, a}) + $signed({1\'b0, b});\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/wreduce.v:3: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 9 bits.\n                                                                                       : ... In instance wreduce_test0\n  assign y = $signed({1\'b0, a}) + $signed({1\'b0, b});\n                                ^\n%Error: Exiting due to 8 warning(s)\n'
module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);
  assign x = -$signed({1'b0, a});
  assign y = $signed({1'b0, a}) + $signed({1'b0, b});
  assign z = x ^ y;
endmodule
module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);

  assign x = -$signed({1'b0, a});
  assign y = $signed({1'b0, a}) + $signed({1'b0, b});
  assign z = x ^ y;
endmodule