data/full_repos/permissive/469509877/rtl/countU5.v
1: b"%Error: data/full_repos/permissive/469509877/rtl/countU5.v:33: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff0 (.C(clk), .R(reset), .CE(Up), .D(~Q[0]), .Q(Q[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/FDRE\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/FDRE.v\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/469509877/rtl/countU5.v:34: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff1 (.C(clk), .R(reset), .CE(Up & Q[0]), .D(~Q[1]), .Q(Q[1]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/countU5.v:35: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff2 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1]), .D(~Q[2]), .Q(Q[2]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/countU5.v:36: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff3 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2]), .D(~Q[3]), .Q(Q[3]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/countU5.v:37: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff4 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2] & Q[3]), .D(~Q[4]), .Q(Q[4]));\n    ^~~~\n%Error: Exiting due to 5 error(s)\n"
module countU5(
    input clk,
    input Up,
    input reset,
    output [4:0] Q,
    output UTC
    );
    
    wire d0, d1, d2, d3, d4;
    
    FDRE #(.INIT(1'b0) ) ff0 (.C(clk), .R(reset), .CE(Up), .D(~Q[0]), .Q(Q[0]));
    FDRE #(.INIT(1'b0) ) ff1 (.C(clk), .R(reset), .CE(Up & Q[0]), .D(~Q[1]), .Q(Q[1]));
    FDRE #(.INIT(1'b0) ) ff2 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1]), .D(~Q[2]), .Q(Q[2]));
    FDRE #(.INIT(1'b0) ) ff3 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2]), .D(~Q[3]), .Q(Q[3]));
    FDRE #(.INIT(1'b0) ) ff4 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2] & Q[3]), .D(~Q[4]), .Q(Q[4]));
      
    assign UTC = Q[0] & Q[1] & Q[2] & Q[3] & Q[4];
endmodule
module countU5(
    input clk,
    input Up,
    input reset,
    output [4:0] Q,
    output UTC
    );

    
    wire d0, d1, d2, d3, d4;
    
    FDRE #(.INIT(1'b0) ) ff0 (.C(clk), .R(reset), .CE(Up), .D(~Q[0]), .Q(Q[0]));
    FDRE #(.INIT(1'b0) ) ff1 (.C(clk), .R(reset), .CE(Up & Q[0]), .D(~Q[1]), .Q(Q[1]));
    FDRE #(.INIT(1'b0) ) ff2 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1]), .D(~Q[2]), .Q(Q[2]));
    FDRE #(.INIT(1'b0) ) ff3 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2]), .D(~Q[3]), .Q(Q[3]));
    FDRE #(.INIT(1'b0) ) ff4 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2] & Q[3]), .D(~Q[4]), .Q(Q[4]));
      
    assign UTC = Q[0] & Q[1] & Q[2] & Q[3] & Q[4];
endmodule