data/full_repos/permissive/488894374/src/mem_wrapper.v
1: b"%Error: data/full_repos/permissive/488894374/src/mem_wrapper.v:46: Cannot find file containing module: 'dist_mem'\n    dist_mem data_mem (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/dist_mem\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/dist_mem.v\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/dist_mem.sv\n             dist_mem\n             dist_mem.v\n             dist_mem.sv\n             obj_dir/dist_mem\n             obj_dir/dist_mem.v\n             obj_dir/dist_mem.sv\n%Error: data/full_repos/permissive/488894374/src/mem_wrapper.v:56: Cannot find file containing module: 'cache'\n    cache #(\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module mem_wrapper (
        a,
        d,
        dpra,
        clk,
        en,
        we,
        funct3,
        spo,
        dpo,
        io_addr,
        io_dout,
        io_we,
        io_rd,
        io_din,
        miss
    );

    input wire [31 : 0] a;
    input wire [31 : 0] d;
    input wire [9 : 0] dpra;
    input wire clk;
    input wire en;
    input wire we;
    input wire [2: 0] funct3;
    output wire [31 : 0] spo;
    output wire [31 : 0] dpo;
    output wire miss;


    input [31:0]   io_din;
    output [7:0]   io_addr;
    output [31:0]  io_dout;
    output  io_we;
    output  io_rd;

    wire is_mmio = (a[31:8] == 24'h0000ff);
    reg  [31:0] mem_in;
    wire [31:0] shared_out, cache_out;
    wire [31:0] mem_out;
    reg  [31:0] mdr;
    wire is_shared = (a[31:8] < 4);
    wire is_cache  = ~is_shared & ~is_mmio;
    assign spo     = is_mmio? io_din : mdr;
    assign mem_out = is_shared? shared_out: cache_out;
    dist_mem data_mem (
                 .a(a[9:2]),
                 .d(mem_in),
                 .dpra(dpra[9:2]),
                 .clk(clk),
                 .we(we & is_shared),
                 .spo(shared_out),
                 .dpo(dpo)
             );

    cache #(
              .LINE_ADDR_LEN 		( 3 		),
              .SET_ADDR_LEN  		( 3 		),
              .TAG_ADDR_LEN  		( 6 		))
          u_cache(

              .clk     		( clk     		),
              .miss    		( miss    		),
              .addr    		( a    		    ),
              .rd_req  		( en & is_cache ),
              .rd_data 		( cache_out 	),
              .wr_req  		( we & is_cache ),
              .wr_data 		( mem_in 		)
          );


    always @(*) begin
        case (funct3)
            3'b000: begin
                case (a[1:0])
                    2'b00:
                        mdr = {{24{mem_out[7]}}, mem_out[7:0]};
                    2'b01:
                        mdr = {{24{mem_out[15]}}, mem_out[15:8]};
                    2'b10:
                        mdr = {{24{mem_out[23]}}, mem_out[23:16]};
                    2'b11:
                        mdr = {{24{mem_out[31]}}, mem_out[31:24]};
                endcase
            end
            3'b001: begin
                case (a[1])
                    1'b0:
                        mdr = {{16{mem_out[15]}}, mem_out[15:0]};
                    1'b1:
                        mdr = {{16{mem_out[31]}}, mem_out[31:16]};
                endcase
            end
            3'b100: begin
                case (a[1:0])
                    2'b00:
                        mdr = {24'b0, mem_out[7:0]};
                    2'b01:
                        mdr = {24'b0, mem_out[15:8]};
                    2'b10:
                        mdr = {24'b0, mem_out[23:16]};
                    2'b11:
                        mdr = {24'b0, mem_out[31:24]};
                endcase
            end
            3'b101: begin
                case (a[1])
                    1'b0:
                        mdr = {16'b0, mem_out[15:0]};
                    1'b1:
                        mdr = {16'b0, mem_out[31:16]};
                endcase
            end
            default:
                mdr = mem_out;
        endcase
    end

    always @(*) begin
        case (funct3)
            3'b000:
            case (a[1:0])
                2'b00:
                    mem_in = {mem_out[31:8], d[7:0]};
                2'b01:
                    mem_in = {mem_out[31:16], d[7:0], mem_out[7:0]};
                2'b10:
                    mem_in = {mem_out[31:24], d[7:0], mem_out[15:0]};
                2'b11:
                    mem_in = {d[7:0], mem_out[23:0]};
            endcase
            3'b001:
            case (a[1])
                1'b0:
                    mem_in = {mem_out[31:16], d[15:0]};
                1'b1:
                    mem_in = {d[15:0], mem_out[15:0]};
            endcase
            default:
                mem_in = d;
        endcase
    end

    assign io_addr = a[7:0];
    assign io_dout = d;
    assign io_we   = we & is_mmio;
    assign io_rd   = en & is_mmio;

endmodule
module mem_wrapper (
        a,
        d,
        dpra,
        clk,
        en,
        we,
        funct3,
        spo,
        dpo,
        io_addr,
        io_dout,
        io_we,
        io_rd,
        io_din,
        miss
    );


    input wire [31 : 0] a;
    input wire [31 : 0] d;
    input wire [9 : 0] dpra;
    input wire clk;
    input wire en;
    input wire we;
    input wire [2: 0] funct3;
    output wire [31 : 0] spo;
    output wire [31 : 0] dpo;
    output wire miss;


    input [31:0]   io_din;
    output [7:0]   io_addr;
    output [31:0]  io_dout;
    output  io_we;
    output  io_rd;

    wire is_mmio = (a[31:8] == 24'h0000ff);
    reg  [31:0] mem_in;
    wire [31:0] shared_out, cache_out;
    wire [31:0] mem_out;
    reg  [31:0] mdr;
    wire is_shared = (a[31:8] < 4);
    wire is_cache  = ~is_shared & ~is_mmio;
    assign spo     = is_mmio? io_din : mdr;
    assign mem_out = is_shared? shared_out: cache_out;
    dist_mem data_mem (
                 .a(a[9:2]),
                 .d(mem_in),
                 .dpra(dpra[9:2]),
                 .clk(clk),
                 .we(we & is_shared),
                 .spo(shared_out),
                 .dpo(dpo)
             );

    cache #(
              .LINE_ADDR_LEN 		( 3 		),
              .SET_ADDR_LEN  		( 3 		),
              .TAG_ADDR_LEN  		( 6 		))
          u_cache(

              .clk     		( clk     		),
              .miss    		( miss    		),
              .addr    		( a    		    ),
              .rd_req  		( en & is_cache ),
              .rd_data 		( cache_out 	),
              .wr_req  		( we & is_cache ),
              .wr_data 		( mem_in 		)
          );


    always @(*) begin
        case (funct3)
            3'b000: begin
                case (a[1:0])
                    2'b00:
                        mdr = {{24{mem_out[7]}}, mem_out[7:0]};
                    2'b01:
                        mdr = {{24{mem_out[15]}}, mem_out[15:8]};
                    2'b10:
                        mdr = {{24{mem_out[23]}}, mem_out[23:16]};
                    2'b11:
                        mdr = {{24{mem_out[31]}}, mem_out[31:24]};
                endcase
            end
            3'b001: begin
                case (a[1])
                    1'b0:
                        mdr = {{16{mem_out[15]}}, mem_out[15:0]};
                    1'b1:
                        mdr = {{16{mem_out[31]}}, mem_out[31:16]};
                endcase
            end
            3'b100: begin
                case (a[1:0])
                    2'b00:
                        mdr = {24'b0, mem_out[7:0]};
                    2'b01:
                        mdr = {24'b0, mem_out[15:8]};
                    2'b10:
                        mdr = {24'b0, mem_out[23:16]};
                    2'b11:
                        mdr = {24'b0, mem_out[31:24]};
                endcase
            end
            3'b101: begin
                case (a[1])
                    1'b0:
                        mdr = {16'b0, mem_out[15:0]};
                    1'b1:
                        mdr = {16'b0, mem_out[31:16]};
                endcase
            end
            default:
                mdr = mem_out;
        endcase
    end

    always @(*) begin
        case (funct3)
            3'b000:
            case (a[1:0])
                2'b00:
                    mem_in = {mem_out[31:8], d[7:0]};
                2'b01:
                    mem_in = {mem_out[31:16], d[7:0], mem_out[7:0]};
                2'b10:
                    mem_in = {mem_out[31:24], d[7:0], mem_out[15:0]};
                2'b11:
                    mem_in = {d[7:0], mem_out[23:0]};
            endcase
            3'b001:
            case (a[1])
                1'b0:
                    mem_in = {mem_out[31:16], d[15:0]};
                1'b1:
                    mem_in = {d[15:0], mem_out[15:0]};
            endcase
            default:
                mem_in = d;
        endcase
    end

    assign io_addr = a[7:0];
    assign io_dout = d;
    assign io_we   = we & is_mmio;
    assign io_rd   = en & is_mmio;

endmodule