data/full_repos/permissive/427221126/src/ConvLayer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ConvLayer.v:459: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ConvLayer\'\nmodule ConvLayer\n       ^~~~~~~~~\n                                                                           : ... Top module \'ConvCore_nC\'\nmodule ConvCore_nC\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:129: Operator ASSIGNDLY expects 41 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n      psum[0] <= mul[0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:140: Operator ADD expects 41 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n          psum[ii] <= mul[ii] + psum[ii-1];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:423: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g] ;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:425: Operator ADD expects 48 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g]  + psum[g-1];\n                                          ^\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:243: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.sv\n             ShiftRegSIPOnB\n             ShiftRegSIPOnB.v\n             ShiftRegSIPOnB.sv\n             obj_dir/ShiftRegSIPOnB\n             obj_dir/ShiftRegSIPOnB.v\n             obj_dir/ShiftRegSIPOnB.sv\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:255: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:290: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:623: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:639: Cannot find file containing module: \'FIFOsync\'\n  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:651: Cannot find file containing module: \'FIFOpi\'\n  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (\n  ^~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module CasAdder
  #(
    parameter INWIDTH = 16,
              CHAIN_LEN = 45
  )
  (
    input                                 clk       ,
    input                                 reset     , 
    input                                 en        ,
    input         [INWIDTH*CHAIN_LEN-1:0] din       ,
    output                                din_ready ,
    input                                 din_valid ,
    input  signed [INWIDTH-1:0]           scale     ,
    input                                 scl_valid ,
    output signed [47:0]                  dout      ,
    output                                dout_valid 
  );
  reg  signed [INWIDTH-1:0] din_buffer    [0:CHAIN_LEN-1];
  reg  signed [INWIDTH-1:0] scale_buffer  [0:CHAIN_LEN-1];
  genvar  g;
  integer i;
  
  reg [CHAIN_LEN:1] din_valid_d;
  reg               adder_en;
  reg               din_rdy;
  wire              din_transfer;
  
  reg  signed [47:0] psum [0:CHAIN_LEN-1];
  
  reg  signed [2*INWIDTH-1:0] din_mult_scale [0:CHAIN_LEN-1];






  assign din_transfer = din_valid & din_ready;

  generate
    for (g = 0; g < CHAIN_LEN; g = g + 1) begin : buffers
      always @(posedge clk) begin
        if (reset)
          din_buffer[g] = $signed({INWIDTH{1'b0}});
        else if (en)
          if (din_transfer)
            din_buffer[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
      end
      
      always @(posedge clk) begin
        if (reset) begin
          scale_buffer[g] <= 0;
        end
        else if (en)
          if (scl_valid) begin
            scale_buffer[g] <= scale;
          end
      end
    end
  endgenerate

  always @(posedge clk) begin
    if (reset)
      din_valid_d <= {CHAIN_LEN{1'b0}};
    else if (en)
      din_valid_d <= {din_valid_d[CHAIN_LEN-1:1], din_transfer};
  end


  always @(posedge clk) begin
    if (reset)
      adder_en <= 1'b0;
    else if (en)
      adder_en <= |{din_valid_d[CHAIN_LEN-1:1], din_transfer};
  end


  always @(posedge clk) begin
    if (reset)
      din_rdy <= 1'b1;
    else if (en)
      din_rdy <= ({din_valid_d[CHAIN_LEN-2:1], din_transfer} == {(CHAIN_LEN-1){1'b0}});
  end
  assign din_ready = din_rdy;

  generate
    for (g = 0; g < CHAIN_LEN; g = g + 1) begin : adder_chain
      always @(*) begin
        din_mult_scale[g] = din_buffer[g] * scale_buffer[g];
      end

      always @(posedge clk) begin
        if (reset)
          psum[g] <= 0;
        else if (en)
          if (g == 0)
            psum[g] <= din_mult_scale[g];
          else
            psum[g] <= din_mult_scale[g]+ psum[g-1];
      end
    end
  endgenerate

  assign dout = psum[CHAIN_LEN-1];
  assign dout_valid = din_valid_d[CHAIN_LEN];
endmodule
module CasAdder
  #(
    parameter INWIDTH = 16,
              CHAIN_LEN = 45
  )
  (
    input                                 clk       ,
    input                                 reset     , 
    input                                 en        ,
    input         [INWIDTH*CHAIN_LEN-1:0] din       ,
    output                                din_ready ,
    input                                 din_valid ,
    input  signed [INWIDTH-1:0]           scale     ,
    input                                 scl_valid ,
    output signed [47:0]                  dout      ,
    output                                dout_valid 
  );

  reg  signed [INWIDTH-1:0] din_buffer    [0:CHAIN_LEN-1];
  reg  signed [INWIDTH-1:0] scale_buffer  [0:CHAIN_LEN-1];
  genvar  g;
  integer i;
  
  reg [CHAIN_LEN:1] din_valid_d;
  reg               adder_en;
  reg               din_rdy;
  wire              din_transfer;
  
  reg  signed [47:0] psum [0:CHAIN_LEN-1];
  
  reg  signed [2*INWIDTH-1:0] din_mult_scale [0:CHAIN_LEN-1];






  assign din_transfer = din_valid & din_ready;

  generate
    for (g = 0; g < CHAIN_LEN; g = g + 1) begin : buffers
      always @(posedge clk) begin
        if (reset)
          din_buffer[g] = $signed({INWIDTH{1'b0}});
        else if (en)
          if (din_transfer)
            din_buffer[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
      end
      
      always @(posedge clk) begin
        if (reset) begin
          scale_buffer[g] <= 0;
        end
        else if (en)
          if (scl_valid) begin
            scale_buffer[g] <= scale;
          end
      end
    end
  endgenerate

  always @(posedge clk) begin
    if (reset)
      din_valid_d <= {CHAIN_LEN{1'b0}};
    else if (en)
      din_valid_d <= {din_valid_d[CHAIN_LEN-1:1], din_transfer};
  end


  always @(posedge clk) begin
    if (reset)
      adder_en <= 1'b0;
    else if (en)
      adder_en <= |{din_valid_d[CHAIN_LEN-1:1], din_transfer};
  end


  always @(posedge clk) begin
    if (reset)
      din_rdy <= 1'b1;
    else if (en)
      din_rdy <= ({din_valid_d[CHAIN_LEN-2:1], din_transfer} == {(CHAIN_LEN-1){1'b0}});
  end
  assign din_ready = din_rdy;

  generate
    for (g = 0; g < CHAIN_LEN; g = g + 1) begin : adder_chain
      always @(*) begin
        din_mult_scale[g] = din_buffer[g] * scale_buffer[g];
      end

      always @(posedge clk) begin
        if (reset)
          psum[g] <= 0;
        else if (en)
          if (g == 0)
            psum[g] <= din_mult_scale[g];
          else
            psum[g] <= din_mult_scale[g]+ psum[g-1];
      end
    end
  endgenerate

  assign dout = psum[CHAIN_LEN-1];
  assign dout_valid = din_valid_d[CHAIN_LEN];
endmodule