data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:22: Cannot find include file: ../../../../lib/axi4lite_sv/axi_lite.vh\n  `include "../../../../lib/axi4lite_sv/axi_lite.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh.sv\n             ../../../../lib/axi4lite_sv/axi_lite.vh\n             ../../../../lib/axi4lite_sv/axi_lite.vh.v\n             ../../../../lib/axi4lite_sv/axi_lite.vh.sv\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh.v\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:23: Cannot find include file: ../../../../lib/axi4s_sv/axi4s.vh\n  `include "../../../../lib/axi4s_sv/axi4s.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:24: Cannot find include file: ../../../../lib/axi4_sv/axi.vh\n  `include "../../../../lib/axi4_sv/axi.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:39: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n    `AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:39: syntax error, unexpected \',\'\n    `AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:46: Define or directive not defined: \'`AXI4S_ASSIGN\'\n  always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:46: syntax error, unexpected \',\'\n  always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end\n                                       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:47: Define or directive not defined: \'`AXI4S_ASSIGN\'\n  always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:48: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:66: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NRS\'\n    `AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v)\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv:67: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module axi_eth_dma (

  AxiStreamIf.slave  e2c,
  AxiStreamIf.master c2e,
  AxiLiteIf.slave    s_axi_eth_dma,
  AxiIf.master       axi_hp,
  output logic       eth_rx_irq,
  output logic       eth_tx_irq

);

  `include "../../../../lib/axi4lite_sv/axi_lite.vh"
  `include "../../../../lib/axi4s_sv/axi4s.vh"
  `include "../../../../lib/axi4_sv/axi.vh"


  AxiLiteIf_v #(32,10)
    s_axi_eth_dma_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
  AxiIf_v #(128,49)
    axi_hp_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));

  AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH), .USER_WIDTH(c2e.USER_WIDTH), .TUSER(0))
    c2e_v    (c2e.clk, c2e.rst);
  AxiStreamIf #(.DATA_WIDTH(e2c.DATA_WIDTH), .USER_WIDTH(e2c.USER_WIDTH), .TUSER(0))
    e2c_v    (e2c.clk, e2c.rst);

  always_comb begin

    `AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)

    s_axi_eth_dma_v.araddr = 0;
    s_axi_eth_dma_v.araddr[9:0] = s_axi_eth_dma.araddr[9:0];
    s_axi_eth_dma_v.awaddr = 0;
    s_axi_eth_dma_v.awaddr[9:0] = s_axi_eth_dma.awaddr[9:0];
  end
  always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end
  always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end
  always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end

  axi_eth_dma_bd axi_eth_dma_bd_i (
    .clk40      (s_axi_eth_dma.clk),
    .clk40_rstn (!s_axi_eth_dma.rst),
    
    .c2e_tdata  (c2e_v.tdata),
    .c2e_tkeep  (c2e_v.tkeep),
    .c2e_tlast  (c2e_v.tlast),
    .c2e_tready (c2e_v.tready),
    .c2e_tvalid (c2e_v.tvalid),
    
    .e2c_tdata  (e2c_v.tdata),
    .e2c_tkeep  (e2c_v.tkeep),
    .e2c_tlast  (e2c_v.tlast),
    .e2c_tready (e2c_v.tready),
    .e2c_tvalid (e2c_v.tvalid),
    
    `AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v)
    `AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v)
    
    .eth_tx_irq (eth_tx_irq),
    .eth_rx_irq (eth_rx_irq)
  );

endmodule
module axi_eth_dma (

  AxiStreamIf.slave  e2c,
  AxiStreamIf.master c2e,
  AxiLiteIf.slave    s_axi_eth_dma,
  AxiIf.master       axi_hp,
  output logic       eth_rx_irq,
  output logic       eth_tx_irq

);


  `include "../../../../lib/axi4lite_sv/axi_lite.vh"
  `include "../../../../lib/axi4s_sv/axi4s.vh"
  `include "../../../../lib/axi4_sv/axi.vh"


  AxiLiteIf_v #(32,10)
    s_axi_eth_dma_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
  AxiIf_v #(128,49)
    axi_hp_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));

  AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH), .USER_WIDTH(c2e.USER_WIDTH), .TUSER(0))
    c2e_v    (c2e.clk, c2e.rst);
  AxiStreamIf #(.DATA_WIDTH(e2c.DATA_WIDTH), .USER_WIDTH(e2c.USER_WIDTH), .TUSER(0))
    e2c_v    (e2c.clk, e2c.rst);

  always_comb begin

    `AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)

    s_axi_eth_dma_v.araddr = 0;
    s_axi_eth_dma_v.araddr[9:0] = s_axi_eth_dma.araddr[9:0];
    s_axi_eth_dma_v.awaddr = 0;
    s_axi_eth_dma_v.awaddr[9:0] = s_axi_eth_dma.awaddr[9:0];
  end
  always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end
  always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end
  always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end

  axi_eth_dma_bd axi_eth_dma_bd_i (
    .clk40      (s_axi_eth_dma.clk),
    .clk40_rstn (!s_axi_eth_dma.rst),
    
    .c2e_tdata  (c2e_v.tdata),
    .c2e_tkeep  (c2e_v.tkeep),
    .c2e_tlast  (c2e_v.tlast),
    .c2e_tready (c2e_v.tready),
    .c2e_tvalid (c2e_v.tvalid),
    
    .e2c_tdata  (e2c_v.tdata),
    .e2c_tkeep  (e2c_v.tkeep),
    .e2c_tlast  (e2c_v.tlast),
    .e2c_tready (e2c_v.tready),
    .e2c_tvalid (e2c_v.tvalid),
    
    `AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v)
    `AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v)
    
    .eth_tx_irq (eth_tx_irq),
    .eth_rx_irq (eth_rx_irq)
  );

endmodule