data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/RegFile.v
data/verilator_xmls/9b29feb3-6d56-47fe-b418-c01dc80f953e.xml
module RegFile(
    input wire clk,
    input wire rstn,
    input wire we,
    input wire [4:0] rd,
    input wire [4:0] rs1,
    input wire [4:0] rs2,
    input wire [31:0] rd_data_in,
    output wire [31:0] rs1_data,
    output wire [31:0] rs2_data
    );
    

    reg [31:0] r [1:31];
    

    
    integer i;
    
    initial begin
        for (i=1; i<32; i=i+1)
            r[i]<=0;
    end
    
    always @(posedge clk) begin
        if(!rstn) begin
            for (i=1; i<32; i=i+1)
                r[i]<=0;
        end
        else if (we)
            r[rd] <= rd_data_in;
    end
    
    assign rs1_data = (rs1 == 0) ? 0 : r[rs1];
    assign rs2_data = (rs2 == 0) ? 0 : r[rs2];
    
endmodule
module RegFile(
    input wire clk,
    input wire rstn,
    input wire we,
    input wire [4:0] rd,
    input wire [4:0] rs1,
    input wire [4:0] rs2,
    input wire [31:0] rd_data_in,
    output wire [31:0] rs1_data,
    output wire [31:0] rs2_data
    );

    

    reg [31:0] r [1:31];
    

    
    integer i;
    
    initial begin
        for (i=1; i<32; i=i+1)
            r[i]<=0;
    end
    
    always @(posedge clk) begin
        if(!rstn) begin
            for (i=1; i<32; i=i+1)
                r[i]<=0;
        end
        else if (we)
            r[rd] <= rd_data_in;
    end
    
    assign rs1_data = (rs1 == 0) ? 0 : r[rs1];
    assign rs2_data = (rs2 == 0) ? 0 : r[rs2];
    
endmodule