data/full_repos/permissive/494657797/verilog/rtl/sar_logic.v
data/verilator_xmls/abfc2317-331c-4ee4-8dad-a71d7200b02c.xml
module sar_logic (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input clk,
    input comp_in,

    output wire [19:0] output_for_analog,
    output wire [20:0] io_oeb);

    assign io_oeb = 21'b000000000000000000000;

    wire comp_en,sample;
    wire q5,q4,q3,q2,q1,q0;
    wire sw5,sw5b,sw4,sw4b,sw3,sw3b,sw2,sw2b,sw1,sw1b,sw0,sw0b;
    wire d1,d2,d3,d4,d5,d6;
    wire d1b,d2b,d3b,d4b,d5b,d6b;
    wire r0,r1,r2,r3,r4,r5,rs;

    count_monitor ccc ( .clk(clk),
                        .comp_en (comp_en),
                        .sample (sample),
                        .d1 (d1),
                        .d1b (d1b),
                        .d2 (d2),
                        .d2b (d2b),
                        .d3 (d3),
                        .d3b (d3b),
                        .d4 (d4),
                        .d4b (d4b),
                        .d5 (d5),
                        .d5b (d5b),
                        .d6 (d6),
                        .d6b (d6b),
                        .rs (rs));
    
    hold hhh ( .comp_in(comp_in),
                .sample(sample),
                .d1b(d1b),
                .d2b(d2b),
                .d3b(d3b),
                .d4b(d4b),
                .d5b(d5b),
                .d6b(d6b),
                .r5(r5),
                .r4(r4),
                .r3(r3),
                .r2(r2),
                .r1(r1),
                .r0(r0));

    qout qqq ( .sample(sample),
                .rs(rs),
                .r5(r5),
                .r4(r4),
                .r3(r3),
                .r2(r2),
                .r1(r1),
                .r0(r0),
                .q5(q5),
                .q4(q4),
                .q3(q3),
                .q2(q2),
                .q1(q1),
                .q0(q0));

    assign sw5 = sample | r5 | d6;
    assign sw5b = ~sw5;
    assign sw4 = sample | r4 | d5;
    assign sw4b = ~sw4;
    assign sw3 = sample | r3 | d4;
    assign sw3b = ~sw3;
    assign sw2 = sample | r2 | d3;
    assign sw2b = ~sw2;
    assign sw1 = sample | r1 | d2;
    assign sw1b = ~sw1;
    assign sw0 = sample | r0 | d1;
    assign sw0b = ~sw0;

    assign output_for_analog = {comp_en,sample,q5,q4,q3,q2,q1,q0,sw5,sw5b,sw4,sw4b,sw3,sw3b,sw2,sw2b,sw1,sw1b,sw0,sw0b};

        
endmodule
module sar_logic (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input clk,
    input comp_in,

    output wire [19:0] output_for_analog,
    output wire [20:0] io_oeb);


    assign io_oeb = 21'b000000000000000000000;

    wire comp_en,sample;
    wire q5,q4,q3,q2,q1,q0;
    wire sw5,sw5b,sw4,sw4b,sw3,sw3b,sw2,sw2b,sw1,sw1b,sw0,sw0b;
    wire d1,d2,d3,d4,d5,d6;
    wire d1b,d2b,d3b,d4b,d5b,d6b;
    wire r0,r1,r2,r3,r4,r5,rs;

    count_monitor ccc ( .clk(clk),
                        .comp_en (comp_en),
                        .sample (sample),
                        .d1 (d1),
                        .d1b (d1b),
                        .d2 (d2),
                        .d2b (d2b),
                        .d3 (d3),
                        .d3b (d3b),
                        .d4 (d4),
                        .d4b (d4b),
                        .d5 (d5),
                        .d5b (d5b),
                        .d6 (d6),
                        .d6b (d6b),
                        .rs (rs));
    
    hold hhh ( .comp_in(comp_in),
                .sample(sample),
                .d1b(d1b),
                .d2b(d2b),
                .d3b(d3b),
                .d4b(d4b),
                .d5b(d5b),
                .d6b(d6b),
                .r5(r5),
                .r4(r4),
                .r3(r3),
                .r2(r2),
                .r1(r1),
                .r0(r0));

    qout qqq ( .sample(sample),
                .rs(rs),
                .r5(r5),
                .r4(r4),
                .r3(r3),
                .r2(r2),
                .r1(r1),
                .r0(r0),
                .q5(q5),
                .q4(q4),
                .q3(q3),
                .q2(q2),
                .q1(q1),
                .q0(q0));

    assign sw5 = sample | r5 | d6;
    assign sw5b = ~sw5;
    assign sw4 = sample | r4 | d5;
    assign sw4b = ~sw4;
    assign sw3 = sample | r3 | d4;
    assign sw3b = ~sw3;
    assign sw2 = sample | r2 | d3;
    assign sw2b = ~sw2;
    assign sw1 = sample | r1 | d2;
    assign sw1b = ~sw1;
    assign sw0 = sample | r0 | d1;
    assign sw0b = ~sw0;

    assign output_for_analog = {comp_en,sample,q5,q4,q3,q2,q1,q0,sw5,sw5b,sw4,sw4b,sw3,sw3b,sw2,sw2b,sw1,sw1b,sw0,sw0b};

        
endmodule