data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v:14: Signal definition not found, creating implicitly: \'s7\'\n                                                                                             : ... Suggested alternative: \'s0\'\nassign s7 = 1\'b1;\n       ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v:17: Cannot find file containing module: \'voting_rule\'\nvoting_rule u0(A,B,C,i[0],i[1],i[2],i[3]);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506820191/design_entry,data/full_repos/permissive/506820191/voting_rule\n             data/full_repos/permissive/506820191/design_entry,data/full_repos/permissive/506820191/voting_rule.v\n             data/full_repos/permissive/506820191/design_entry,data/full_repos/permissive/506820191/voting_rule.sv\n             voting_rule\n             voting_rule.v\n             voting_rule.sv\n             obj_dir/voting_rule\n             obj_dir/voting_rule.v\n             obj_dir/voting_rule.sv\n%Error: data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v:18: Cannot find file containing module: \'bcd_to_7seg\'\nbcd_to_7seg u1({i[0],i[1],i[2],i[3]},s0,s1,s2,s3,s4,s5,s6);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v:19: Cannot find file containing module: \'led_mux\'\nled_mux     u2(clk_5KHz,rst,{s6,s5,s4,s3,s2,s1,s0},vcc,vcc,vcc,LEDOUT,LEDSEL);\n^~~~~~~\n%Error: data/full_repos/permissive/506820191/design_entry/voting_machine_fpga.v:20: Cannot find file containing module: \'clk_gen\'\nclk_gen  u3(.clk100MHz(clk100MHz), .rst(rst),.clk_4sec(DONT_USE),.clk_5KHz(clk_5KHz));\n^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module voting_machine_fpga(A,B,C,clk100MHz,rst,LEDOUT,LEDSEL);


input A, B, C, clk100MHz, rst;
output[7:0] LEDOUT;
output[3:0] LEDSEL;
supply1[7:0] vcc;
wire s0,s1,s2,s3,s4,s5,s6;
wire [3:0] i;
wire DONT_USE, clk_5KHz;


assign s7 = 1'b1;


voting_rule u0(A,B,C,i[0],i[1],i[2],i[3]);
bcd_to_7seg u1({i[0],i[1],i[2],i[3]},s0,s1,s2,s3,s4,s5,s6);
led_mux     u2(clk_5KHz,rst,{s6,s5,s4,s3,s2,s1,s0},vcc,vcc,vcc,LEDOUT,LEDSEL);
clk_gen		u3(.clk100MHz(clk100MHz), .rst(rst),.clk_4sec(DONT_USE),.clk_5KHz(clk_5KHz));

endmodule
module voting_machine_fpga(A,B,C,clk100MHz,rst,LEDOUT,LEDSEL);



input A, B, C, clk100MHz, rst;
output[7:0] LEDOUT;
output[3:0] LEDSEL;
supply1[7:0] vcc;
wire s0,s1,s2,s3,s4,s5,s6;
wire [3:0] i;
wire DONT_USE, clk_5KHz;


assign s7 = 1'b1;


voting_rule u0(A,B,C,i[0],i[1],i[2],i[3]);
bcd_to_7seg u1({i[0],i[1],i[2],i[3]},s0,s1,s2,s3,s4,s5,s6);
led_mux     u2(clk_5KHz,rst,{s6,s5,s4,s3,s2,s1,s0},vcc,vcc,vcc,LEDOUT,LEDSEL);
clk_gen		u3(.clk100MHz(clk100MHz), .rst(rst),.clk_4sec(DONT_USE),.clk_5KHz(clk_5KHz));

endmodule