data/full_repos/permissive/419538859/lab6/sim/lab6.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/419538859/lab6/sim/lab6.v:110: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'lab6\'\nmodule lab6(clk, reset, column, sel, seg7);\n       ^~~~\n                                                                           : ... Top module \'key_led\'\nmodule  key_led(clk_sel, reset, column, sel, key_code);\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab6/sim/lab6.v:122: Signal definition not found, creating implicitly: \'press_valid\'\nkey_buf6 g3(clk_sel, reset, press_valid, scan_code, display_code);\n                            ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module bcd_to_seg7(bcd_in,seg7);

input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule
module bcd_to_seg7(bcd_in,seg7);


input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule