data/full_repos/permissive/514354758/testbench/tb_remover.v
1: b'%Error: data/full_repos/permissive/514354758/testbench/tb_remover.v:2: Cannot find include file: remover.v\n`include "remover.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/remover.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/remover.v.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/remover.v.sv\n             remover.v\n             remover.v.v\n             remover.v.sv\n             obj_dir/remover.v\n             obj_dir/remover.v.v\n             obj_dir/remover.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:12: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/514354758/testbench/tb_remover.v:15: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_remover.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/514354758/testbench/tb_remover.v:16: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_remover.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module tb_remover;
    reg clk;
    reg rstn;
    reg [7:0] data;
    wire [7:0] VGA_data;

    remover remover_inst(clk,rstn,data,VGA_data);

    always #5 clk = ~clk;

    initial begin
        $dumpfile("tb_remover.vcd");
        $dumpvars(0);
        clk = 0;
        rstn = 1;
        data = 0;
        #10
        rstn = 0;
        #10
        rstn = 1;
        #5
        data = 8'b0_1111111;
        #10
        data = 8'b0_1110110;
        #10
        data = 8'b0_1011011;
        #10
        data = 8'b1_0100101;
        #10
        data = 8'b1_0010111;
        #10
        data = 8'b0_0010111;
        #10
        data = 8'b0_1011010;
        #20
        $finish;
    end

endmodule
module tb_remover;

    reg clk;
    reg rstn;
    reg [7:0] data;
    wire [7:0] VGA_data;

    remover remover_inst(clk,rstn,data,VGA_data);

    always #5 clk = ~clk;

    initial begin
        $dumpfile("tb_remover.vcd");
        $dumpvars(0);
        clk = 0;
        rstn = 1;
        data = 0;
        #10
        rstn = 0;
        #10
        rstn = 1;
        #5
        data = 8'b0_1111111;
        #10
        data = 8'b0_1110110;
        #10
        data = 8'b0_1011011;
        #10
        data = 8'b1_0100101;
        #10
        data = 8'b1_0010111;
        #10
        data = 8'b0_0010111;
        #10
        data = 8'b0_1011010;
        #20
        $finish;
    end

endmodule