data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v
1: b'%Error: data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v:39: Unsupported in C: Block has the same name as variable: \'HAS_TREADY\'\n    begin : HAS_TREADY\n            ^~~~~~~~~~\n        data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v:7: ... Location of original declaration\n  parameter         HAS_TREADY = "FALSE"\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v:38: Found definition of \'HAS_TREADY\' as a BEGIN but expected a variable\n    if(HAS_TREADY == "TRUE")\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v:38: Unsupported in C: Variable has the same name as block: \'HAS_TREADY\'\n    if(HAS_TREADY == "TRUE")\n       ^~~~~~~~~~\n        data/full_repos/permissive/428611613/cores/axis_lfsr_v1_0/axis_lfsr.v:39: ... Location of original declaration\n    begin : HAS_TREADY\n            ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module axis_lfsr #
(
  parameter integer AXIS_TDATA_WIDTH = 64,
  parameter         HAS_TREADY = "FALSE"
)
(

  input  wire                        aclk,
  input  wire                        aresetn,


  input  wire                        m_axis_tready,
  output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
  output wire                        m_axis_tvalid
);

  reg [AXIS_TDATA_WIDTH-1:0] int_lfsr_reg, int_lfsr_next;
  reg int_enbl_reg, int_enbl_next;

  always @(posedge aclk)
  begin
    if(~aresetn)
    begin
      int_lfsr_reg <= 64'h5555555555555555;
      int_enbl_reg <= 1'b0;
    end
    else
    begin
      int_lfsr_reg <= int_lfsr_next;
      int_enbl_reg <= int_enbl_next;
    end
  end

  generate
    if(HAS_TREADY == "TRUE")
    begin : HAS_TREADY
      always @*
      begin
        int_lfsr_next = int_lfsr_reg;
        int_enbl_next = int_enbl_reg;

        if(~int_enbl_reg)
        begin
          int_enbl_next = 1'b1;
        end

        if(int_enbl_reg & m_axis_tready)
        begin
          int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
        end
      end
    end
    else
    begin : NO_TREADY
      always @*
      begin
        int_lfsr_next = int_lfsr_reg;
        int_enbl_next = int_enbl_reg;

        if(~int_enbl_reg)
        begin
          int_enbl_next = 1'b1;
        end

        if(int_enbl_reg)
        begin
          int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
        end
      end
    end
  endgenerate

  assign m_axis_tdata = int_lfsr_reg;
  assign m_axis_tvalid = int_enbl_reg;

endmodule
module axis_lfsr #
(
  parameter integer AXIS_TDATA_WIDTH = 64,
  parameter         HAS_TREADY = "FALSE"
)
(

  input  wire                        aclk,
  input  wire                        aresetn,


  input  wire                        m_axis_tready,
  output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
  output wire                        m_axis_tvalid
);


  reg [AXIS_TDATA_WIDTH-1:0] int_lfsr_reg, int_lfsr_next;
  reg int_enbl_reg, int_enbl_next;

  always @(posedge aclk)
  begin
    if(~aresetn)
    begin
      int_lfsr_reg <= 64'h5555555555555555;
      int_enbl_reg <= 1'b0;
    end
    else
    begin
      int_lfsr_reg <= int_lfsr_next;
      int_enbl_reg <= int_enbl_next;
    end
  end

  generate
    if(HAS_TREADY == "TRUE")
    begin : HAS_TREADY
      always @*
      begin
        int_lfsr_next = int_lfsr_reg;
        int_enbl_next = int_enbl_reg;

        if(~int_enbl_reg)
        begin
          int_enbl_next = 1'b1;
        end

        if(int_enbl_reg & m_axis_tready)
        begin
          int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
        end
      end
    end
    else
    begin : NO_TREADY
      always @*
      begin
        int_lfsr_next = int_lfsr_reg;
        int_enbl_next = int_enbl_reg;

        if(~int_enbl_reg)
        begin
          int_enbl_next = 1'b1;
        end

        if(int_enbl_reg)
        begin
          int_lfsr_next = {int_lfsr_reg[62:0], int_lfsr_reg[62] ~^ int_lfsr_reg[61]};
        end
      end
    end
  endgenerate

  assign m_axis_tdata = int_lfsr_reg;
  assign m_axis_tvalid = int_enbl_reg;

endmodule