data/full_repos/permissive/452215364/rtl/opl2/opl2.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:50: Cannot find include file: operator/opl3.vh\n`include "operator/opl3.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/operator/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/operator/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/operator/opl3.vh.sv\n             operator/opl3.vh\n             operator/opl3.vh.v\n             operator/opl3.vh.sv\n             obj_dir/operator/opl3.vh\n             obj_dir/operator/opl3.vh.v\n             obj_dir/operator/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:80: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n  localparam NUM_OPERATOR_UPDATE_STATES = `NUM_OPERATORS_PER_BANK + 1;\n                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:139: Define or directive not defined: \'`CLOG2\'\n  reg [`CLOG2(OPERATOR_PIPELINE_DELAY)-1:0] delay_counter;\n       ^~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:141: Define or directive not defined: \'`CLOG2\'\n  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] delay_state;\n       ^~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:142: Define or directive not defined: \'`CLOG2\'\n  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] next_delay_state;\n       ^~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:144: Define or directive not defined: \'`CLOG2\'\n  reg [`CLOG2(`NUM_OPERATORS_PER_BANK)-1:0] op_num;\n       ^~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:144: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n  reg [`CLOG2(`NUM_OPERATORS_PER_BANK)-1:0] op_num;\n              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:144: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  reg [`CLOG2(`NUM_OPERATORS_PER_BANK)-1:0] op_num;\n                                     ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:156: Define or directive not defined: \'`SAMPLE_WIDTH\'\n  reg signed [`SAMPLE_WIDTH-1:0] channel_2_op[8:0];\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:158: Define or directive not defined: \'`CHANNEL_ACCUMULATOR_WIDTH\'\n  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp = 0;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:159: Define or directive not defined: \'`CHANNEL_ACCUMULATOR_WIDTH\'\n  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp_p[8:0];\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:160: Define or directive not defined: \'`CHANNEL_ACCUMULATOR_WIDTH\'\n  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp = 0;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:161: Define or directive not defined: \'`CHANNEL_ACCUMULATOR_WIDTH\'\n  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp_p[8:0];\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:163: Define or directive not defined: \'`SAMPLE_WIDTH\'\n  reg signed [`SAMPLE_WIDTH-1:0] channel_a;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:164: Define or directive not defined: \'`SAMPLE_WIDTH\'\n  reg signed [`SAMPLE_WIDTH-1:0] channel_b;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:384: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[0] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:384: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[0] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:392: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[3] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:392: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[3] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:400: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[1] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:400: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[1] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:408: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[4] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:408: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[4] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:416: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[2] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:416: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[2] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:424: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[5] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:424: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[5] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:432: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[6] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:432: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[6] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:440: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[9] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:440: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[9] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:448: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[7] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:448: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[7] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:456: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[10] = `OP_NORMAL;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:456: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[10] = `OP_NORMAL;\n                                ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:464: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[8] = `OP_NORMAL;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:464: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[8] = `OP_NORMAL;\n                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:472: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[11] = `OP_NORMAL;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:472: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    op_type_tmp[11] = `OP_NORMAL;\n                                ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:481: Define or directive not defined: \'`OP_BASS_DRUM\'\n    op_type_tmp[12] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:481: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    op_type_tmp[12] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                                          ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:481: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[12] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:490: Define or directive not defined: \'`OP_BASS_DRUM\'\n    op_type_tmp[15] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:490: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    op_type_tmp[15] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                                          ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:490: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[15] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:499: Define or directive not defined: \'`OP_HI_HAT\'\n    op_type_tmp[13] = ryt ? `OP_HI_HAT : `OP_NORMAL;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:499: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    op_type_tmp[13] = ryt ? `OP_HI_HAT : `OP_NORMAL;\n                                       ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:499: Define or directive not defined: \'`OP_NORMAL\'\n    op_type_tmp[13] = ryt ? `OP_HI_HAT : `OP_NORMAL;\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:508: Define or directive not defined: \'`OP_SNARE_DRUM\'\n    op_type_tmp[16] = ryt ? `OP_SNARE_DRUM : `OP_NORMAL;\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2.v:508: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    op_type_tmp[16] = ryt ? `OP_SNARE_DRUM : `OP_NORMAL;\n                                           ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module opl2(
  clk,
  OPL2_clk,
  reset,
  opl2_we,
  opl2_data,
  opl2_adr,
  kon,
  channel_a,
  channel_b,
  sample_clk,
  sample_clk_128
  );

  input         clk;
  input         OPL2_clk;
  input         reset;
  input         opl2_we;
  input [7:0]   opl2_data;
  input [7:0]   opl2_adr;
  output [8:0]  kon;
  output signed [15:0] channel_a;
  output signed [15:0] channel_b;
  output sample_clk;
  output sample_clk_128;

  localparam OPERATOR_PIPELINE_DELAY = 7;

  localparam NUM_OPERATOR_UPDATE_STATES = `NUM_OPERATORS_PER_BANK + 1;

  localparam
    IDLE = 0,
    CALC_OUTPUTS = 1;

  reg [7:0] opl2_reg[255:0];

  reg [8:0] cntr;
  reg sample_clk_en;

  reg nts;

  reg [17:0] am;
  reg [17:0] vib;
  reg [17:0] egt;
  reg [17:0] ksr;
  reg [3:0] mult[17:0];

  reg [1:0] ksl[17:0];
  reg [5:0] tl[17:0];

  reg [3:0] ar[17:0];
  reg [3:0] dr[17:0];

  reg [3:0] sl[17:0];
  reg [3:0] rr[17:0];

  reg [9:0] fnum[8:0];

  reg [8:0] kon;
  reg [2:0] block[8:0];
  reg sample_clk;
  reg sample_clk_128;

  reg dam;
  reg dvb;
  reg ryt;
  reg bd;
  reg sd;
  reg tom;
  reg tc;
  reg hh;

  reg [8:0] chb;
  reg [8:0] cha;
  reg [2:0] fb[8:0];
  reg [8:0] cnt;

  reg [1:0] ws[17:0];

  reg [9:0] fnum_tmp[17:0];
  reg [2:0] block_tmp[17:0];
  reg [2:0] fb_tmp[17:0];
  reg [2:0] op_type_tmp[17:0];
  reg [17:0] kon_tmp;
  reg [17:0] use_feedback;
  reg signed [12:0] modulation[17:0];

  reg [`CLOG2(OPERATOR_PIPELINE_DELAY)-1:0] delay_counter;

  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] delay_state;
  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] next_delay_state;

  reg [`CLOG2(`NUM_OPERATORS_PER_BANK)-1:0] op_num;

  wire signed [12:0] operator_out_tmp;
  reg signed [12:0] operator_out[17:0];

  wire latch_feedback_pulse;

  reg calc_state = IDLE;
  reg next_calc_state;

  reg [3:0] channel;

  reg signed [`SAMPLE_WIDTH-1:0] channel_2_op[8:0];

  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp = 0;
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp_p[8:0];
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp = 0;
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp_p[8:0];

  reg signed [`SAMPLE_WIDTH-1:0] channel_a;
  reg signed [`SAMPLE_WIDTH-1:0] channel_b;

  genvar i;
  generate
    for (i = 0; i < 256; i = i + 1) begin: named
      always @ (posedge clk) begin
        if (reset)
          opl2_reg[i] <= 8'd0;
        else if (opl2_we && (opl2_adr == i))
          opl2_reg[i] <= opl2_data;
      end
    end
  endgenerate

  always @(posedge OPL2_clk)
    if (reset) begin
      cntr <= 9'd0;
      sample_clk_en <= 1'b0;
      sample_clk <= 1'b0;
    end else begin




      cntr <= cntr == 9'd499 ? 9'd0 : cntr + 1'b1;
      sample_clk_en <= cntr == 9'd0;
      sample_clk <= ~cntr[8];
      sample_clk_128 <= ~cntr[0];
    end


  always @(posedge OPL2_clk)
    if (reset) begin
      nts <= 1'b0;
      dam <= 1'b0;
      dvb <= 1'b0;
      ryt <= 1'b0;
      bd  <= 1'b0;
      sd  <= 1'b0;
      tom <= 1'b0;
      tc  <= 1'b0;
      hh  <= 1'b0;
    end else if (sample_clk_en) begin
      nts <= opl2_reg[8][6];
      dam <= opl2_reg['hBD][7];
      dvb <= opl2_reg['hBD][6];
      ryt <= opl2_reg['hBD][5];
      bd  <= opl2_reg['hBD][4];
      sd  <= opl2_reg['hBD][3];
      tom <= opl2_reg['hBD][2];
      tc  <= opl2_reg['hBD][1];
      hh  <= opl2_reg['hBD][0];
    end

  generate
    for (i = 0; i < 6; i = i + 1) begin: name1
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h20+i][7];
          vib[i]  <= opl2_reg['h20+i][6];
          egt[i]  <= opl2_reg['h20+i][5];
          ksr[i]  <= opl2_reg['h20+i][4];
          mult[i] <= opl2_reg['h20+i][3:0];

          ksl[i] <= opl2_reg['h40+i][7:6];
          tl[i]  <= opl2_reg['h40+i][5:0];

          ar[i] <= opl2_reg['h60+i][7:4];
          dr[i] <= opl2_reg['h60+i][3:0];

          sl[i] <= opl2_reg['h80+i][7:4];
          rr[i] <= opl2_reg['h80+i][3:0];

          ws[i] <= opl2_reg['hE0+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 6; i < 12; i = i + 1) begin: name2
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h22+i][7];
          vib[i]  <= opl2_reg['h22+i][6];
          egt[i]  <= opl2_reg['h22+i][5];
          ksr[i]  <= opl2_reg['h22+i][4];
          mult[i] <= opl2_reg['h22+i][3:0];

          ksl[i] <= opl2_reg['h42+i][7:6];
          tl[i]  <= opl2_reg['h42+i][5:0];

          ar[i] <= opl2_reg['h62+i][7:4];
          dr[i] <= opl2_reg['h62+i][3:0];

          sl[i] <= opl2_reg['h82+i][7:4];
          rr[i] <= opl2_reg['h82+i][3:0];

          ws[i] <= opl2_reg['hE2+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 12; i < 18; i = i + 1) begin: name3
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h24+i][7];
          vib[i]  <= opl2_reg['h24+i][6];
          egt[i]  <= opl2_reg['h24+i][5];
          ksr[i]  <= opl2_reg['h24+i][4];
          mult[i] <= opl2_reg['h24+i][3:0];

          ksl[i] <= opl2_reg['h44+i][7:6];
          tl[i]  <= opl2_reg['h44+i][5:0];

          ar[i] <= opl2_reg['h64+i][7:4];
          dr[i] <= opl2_reg['h64+i][3:0];

          sl[i] <= opl2_reg['h84+i][7:4];
          rr[i] <= opl2_reg['h84+i][3:0];

          ws[i] <= opl2_reg['hE4+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 0; i < 9; i = i + 1) begin: name4
      always @(posedge OPL2_clk) begin
        if (reset) begin
          fnum[i] <= 10'd0;

          kon[i] <= 1'b0;
          block[i] <= 3'd0;

          chb[i] <= 1'b0;
          cha[i] <= 1'b0;
          fb[i]  <= 3'd0;
          cnt[i] <= 1'b0;
        end else if (sample_clk_en) begin
          fnum[i][7:0] <= opl2_reg['hA0+i];
          fnum[i][9:8] <= opl2_reg['hB0+i][1:0];

          kon[i] <= opl2_reg['hB0+i][5];
          block[i] <= opl2_reg['hB0+i][4:2];

          chb[i] <= opl2_reg['hC0+i][5];
          cha[i] <= opl2_reg['hC0+i][4];
          fb[i]  <= opl2_reg['hC0+i][3:1];
          cnt[i] <= opl2_reg['hC0+i][0];
        end
        end
      end
    endgenerate

  always @ (*) begin

    fnum_tmp[0] = fnum[0];
    block_tmp[0] = block[0];
    kon_tmp[0] = kon[0];
    fb_tmp[0] = fb[0];
    op_type_tmp[0] = `OP_NORMAL;
    use_feedback[0] = 1;
    modulation[0] = 0;

    fnum_tmp[3] = fnum[0];
    block_tmp[3] = block[0];
    kon_tmp[3] = kon[0];
    fb_tmp[3] = 0;
    op_type_tmp[3] = `OP_NORMAL;
    use_feedback[3] = 0;
    modulation[3] = cnt[0] ? 0 : operator_out[0];

    fnum_tmp[1] = fnum[1];
    block_tmp[1] = block[1];
    kon_tmp[1] = kon[1];
    fb_tmp[1] = fb[1];
    op_type_tmp[1] = `OP_NORMAL;
    use_feedback[1] = 1;
    modulation[1] = 0;

    fnum_tmp[4] = fnum[1];
    block_tmp[4] = block[1];
    kon_tmp[4] = kon[1];
    fb_tmp[4] = 0;
    op_type_tmp[4] = `OP_NORMAL;
    use_feedback[4] = 0;
    modulation[4] = cnt[1] ? 0 : operator_out[1];

    fnum_tmp[2] = fnum[2];
    block_tmp[2] = block[2];
    kon_tmp[2] = kon[2];
    fb_tmp[2] = fb[2];
    op_type_tmp[2] = `OP_NORMAL;
    use_feedback[2] = 1;
    modulation[2] = 0;

    fnum_tmp[5] = fnum[2];
    block_tmp[5] = block[2];
    kon_tmp[5] = kon[2];
    fb_tmp[5] = 0;
    op_type_tmp[5] = `OP_NORMAL;
    use_feedback[5] = 0;
    modulation[5] = cnt[2] ? 0 : operator_out[2];

    fnum_tmp[6] = fnum[3];
    block_tmp[6] = block[3];
    kon_tmp[6] = kon[3];
    fb_tmp[6] = fb[3];
    op_type_tmp[6] = `OP_NORMAL;
    use_feedback[6] = 1;
    modulation[6] = 0;

    fnum_tmp[9] = fnum[3];
    block_tmp[9] = block[3];
    kon_tmp[9] = kon[3];
    fb_tmp[9] = 0;
    op_type_tmp[9] = `OP_NORMAL;
    use_feedback[9] = 0;
    modulation[9] = cnt[3] ? 0 : operator_out[6];

    fnum_tmp[7] = fnum[4];
    block_tmp[7] = block[4];
    kon_tmp[7] = kon[4];
    fb_tmp[7] = fb[4];
    op_type_tmp[7] = `OP_NORMAL;
    use_feedback[7] = 1;
    modulation[7] = 0;

    fnum_tmp[10] = fnum[4];
    block_tmp[10] = block[4];
    kon_tmp[10] = kon[4];
    fb_tmp[10] = 0;
    op_type_tmp[10] = `OP_NORMAL;
    use_feedback[10] = 0;
    modulation[10] = cnt[4] ? 0 : operator_out[7];

    fnum_tmp[8] = fnum[5];
    block_tmp[8] = block[5];
    kon_tmp[8] = kon[5];
    fb_tmp[8] = fb[5];
    op_type_tmp[8] = `OP_NORMAL;
    use_feedback[8] = 1;
    modulation[8] = 0;

    fnum_tmp[11] = fnum[5];
    block_tmp[11] = block[5];
    kon_tmp[11] = kon[5];
    fb_tmp[11] = 0;
    op_type_tmp[11] = `OP_NORMAL;
    use_feedback[11] = 0;
    modulation[11] = cnt[5] ? 0 : operator_out[8];


    fnum_tmp[12] = fnum[6];
    block_tmp[12] = block[6];
    kon_tmp[12] = kon[6];
    fb_tmp[12] = fb[6];
    op_type_tmp[12] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;
    use_feedback[12] = 1;
    modulation[12] = 0;


    fnum_tmp[15] = fnum[6];
    block_tmp[15] = block[6];
    kon_tmp[15] = kon[6];
    fb_tmp[15] = 0;
    op_type_tmp[15] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;
    use_feedback[15] = 0;
    modulation[15] = cnt[6] ? 0 : operator_out[12];


    fnum_tmp[13] = fnum[7];
    block_tmp[13] = block[7];
    kon_tmp[13] = kon[7];
    fb_tmp[13] = ryt ? 0 : fb[7];
    op_type_tmp[13] = ryt ? `OP_HI_HAT : `OP_NORMAL;
    use_feedback[13] = ryt ? 0 : 1;
    modulation[13] = 0;


    fnum_tmp[16] = fnum[7];
    block_tmp[16] = block[7];
    kon_tmp[16] = kon[7];
    fb_tmp[16] = 0;
    op_type_tmp[16] = ryt ? `OP_SNARE_DRUM : `OP_NORMAL;
    use_feedback[16] = 0;
    modulation[16] = cnt[7] || ryt ? 0 : operator_out[13];


    fnum_tmp[14] = fnum[8];
    block_tmp[14] = block[8];
    kon_tmp[14] = kon[8];
    fb_tmp[14] = ryt ? 0 : fb[8];
    op_type_tmp[14] = ryt ? `OP_TOM_TOM : `OP_NORMAL;
    use_feedback[14] = ryt ? 0 : 1;
    modulation[14] = 0;


    fnum_tmp[17] = fnum[8];
    block_tmp[17] = block[8];
    kon_tmp[17] = kon[8];
    fb_tmp[17] = 0;
    op_type_tmp[17] = ryt ? `OP_TOP_CYMBAL : `OP_NORMAL;
    use_feedback[17] = 0;
    modulation[17] = cnt[8] || ryt ? 0 : operator_out[14];
  end

  always @(posedge OPL2_clk)
    if (reset)
      delay_state <= 5'd0;
    else
      delay_state <= next_delay_state;

  always @ (*)
    if (delay_state == 0)
      next_delay_state = sample_clk_en ? 1 : 0;
    else if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
      if (delay_state == NUM_OPERATOR_UPDATE_STATES - 1)
        next_delay_state = 0;
      else
        next_delay_state = delay_state + 1;
    else
      next_delay_state = delay_state;

  always @(posedge OPL2_clk)
    if (reset)
      delay_counter <= 0;
    else begin
      if (next_delay_state != delay_state)
        delay_counter <= 0;
      else if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
        delay_counter <= 0;
      else
        delay_counter <= delay_counter + 1;
    end

  always @ (*)
    if (delay_state == 0)
      op_num = 0;
    else
      op_num = delay_state - 1;


  operator operator_inst(
    .clk(OPL2_clk),
    .reset(reset),
    .sample_clk_en(delay_state != 0 && delay_counter == 0),
    .op_num(op_num),
    .fnum(fnum_tmp[op_num]),
    .mult(mult[op_num]),
    .block(block_tmp[op_num]),
    .ws(ws[op_num]),
    .vib(vib[op_num]),
    .kon(kon_tmp),
    .ar(ar[op_num]),
    .dr(dr[op_num]),
    .sl(sl[op_num]),
    .rr(rr[op_num]),
    .tl(tl[op_num]),
    .ksr(ksr[op_num]),
    .ksl(ksl[op_num]),
    .egt(egt[op_num]),
    .am(am[op_num]),
    .dam(dam),
    .dvb(dvb),
    .nts(nts),
    .bd(bd),
    .sd(sd),
    .tom(tom),
    .tc(tc),
    .hh(hh),
    .use_feedback(use_feedback[op_num]),
    .fb(fb_tmp[op_num]),
    .modulation(modulation[op_num]),
    .op_type(op_type_tmp[op_num]),
    .latch_feedback_pulse(latch_feedback_pulse),
    .out(operator_out_tmp)
  );

  always @(posedge OPL2_clk) begin
    if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
      operator_out[op_num] <= operator_out_tmp;
  end


  assign
    latch_feedback_pulse = delay_counter == OPERATOR_PIPELINE_DELAY - 1;


  always @(posedge OPL2_clk)
    if (reset)
      calc_state <= IDLE;
    else
      calc_state <= next_calc_state;

  always @ (*)
    case (calc_state)
    IDLE: next_calc_state = sample_clk_en ? CALC_OUTPUTS : IDLE;
    CALC_OUTPUTS: next_calc_state = channel == 8 ? IDLE : CALC_OUTPUTS;
    endcase

  always @(posedge OPL2_clk) begin
    if (calc_state == IDLE || channel == 8)
      channel <= 0;
    else
      channel <= channel + 1;
    end


  always @ (*) begin

    channel_2_op[0] = cnt[0] ? operator_out[0] + operator_out[3]
     : operator_out[3];
    channel_2_op[1] = cnt[1] ? operator_out[1] + operator_out[4]
     : operator_out[4];
    channel_2_op[2] = cnt[2] ? operator_out[2] + operator_out[5]
     : operator_out[5];
    channel_2_op[3] = cnt[3] ? operator_out[6] + operator_out[9]
     : operator_out[9];
    channel_2_op[4] = cnt[4] ? operator_out[7] + operator_out[10]
     : operator_out[10];
    channel_2_op[5] = cnt[5] ? operator_out[8] + operator_out[11]
     : operator_out[11];

    if (ryt)

      channel_2_op[6] = cnt[6] ? operator_out[15] : operator_out[12];
    else
      channel_2_op[6] = cnt[6] ? operator_out[12] + operator_out[15]
       : operator_out[15];


    channel_2_op[7] = cnt[7] || (ryt) ? operator_out[13] + operator_out[16]
     : operator_out[16];


    channel_2_op[8] = cnt[8] || (ryt)  ? operator_out[14] + operator_out[17]
     : operator_out[17];

  end

  always @(posedge OPL2_clk) begin
    channel_a_acc_pre_clamp_p[0] <= cha[0] ? channel_2_op[0] : 0;
    channel_a_acc_pre_clamp_p[1] <= cha[1] ? channel_2_op[1] : 0;
    channel_a_acc_pre_clamp_p[2] <= cha[2] ? channel_2_op[2] : 0;
    channel_a_acc_pre_clamp_p[3] <= cha[3] ? channel_2_op[3] : 0;
    channel_a_acc_pre_clamp_p[4] <= cha[4] ? channel_2_op[4] : 0;
    channel_a_acc_pre_clamp_p[5] <= cha[5] ? channel_2_op[5] : 0;
    channel_a_acc_pre_clamp_p[6] <= cha[6] ? channel_2_op[6] : 0;
    channel_a_acc_pre_clamp_p[7] <= cha[7] ? channel_2_op[7] : 0;
    channel_a_acc_pre_clamp_p[8] <= cha[8] ? channel_2_op[8] : 0;
    channel_b_acc_pre_clamp_p[0] <= chb[0] ? channel_2_op[0] : 0;
    channel_b_acc_pre_clamp_p[1] <= chb[1] ? channel_2_op[1] : 0;
    channel_b_acc_pre_clamp_p[2] <= chb[2] ? channel_2_op[2] : 0;
    channel_b_acc_pre_clamp_p[3] <= chb[3] ? channel_2_op[3] : 0;
    channel_b_acc_pre_clamp_p[4] <= chb[4] ? channel_2_op[4] : 0;
    channel_b_acc_pre_clamp_p[5] <= chb[5] ? channel_2_op[5] : 0;
    channel_b_acc_pre_clamp_p[6] <= chb[6] ? channel_2_op[6] : 0;
    channel_b_acc_pre_clamp_p[7] <= chb[7] ? channel_2_op[7] : 0;
    channel_b_acc_pre_clamp_p[8] <= chb[8] ? channel_2_op[8] : 0;
  end


  always @(posedge OPL2_clk)
    if (sample_clk_en)
      channel_a_acc_pre_clamp <= 0;
    else if (calc_state == CALC_OUTPUTS)
      channel_a_acc_pre_clamp <= channel_a_acc_pre_clamp +
       channel_a_acc_pre_clamp_p[channel];

  always @(posedge OPL2_clk)
    if (sample_clk_en)
      channel_b_acc_pre_clamp <= 0;
    else if (calc_state == CALC_OUTPUTS)
      channel_b_acc_pre_clamp <= channel_b_acc_pre_clamp +
       channel_b_acc_pre_clamp_p[channel];


  always @(posedge OPL2_clk)
    if (sample_clk_en) begin
      if (channel_a_acc_pre_clamp > 2**15 - 1)
        channel_a <= 2**15 - 1;
      else if (channel_a_acc_pre_clamp < -2**15)
        channel_a <= -2**15;
      else
        channel_a <= channel_a_acc_pre_clamp;

      if (channel_b_acc_pre_clamp > 2**15 - 1)
        channel_b <= 2**15 - 1;
      else if (channel_b_acc_pre_clamp < -2**15)
        channel_b <= -2**15;
      else
        channel_b <= channel_b_acc_pre_clamp;
    end

endmodule
module opl2(
  clk,
  OPL2_clk,
  reset,
  opl2_we,
  opl2_data,
  opl2_adr,
  kon,
  channel_a,
  channel_b,
  sample_clk,
  sample_clk_128
  );


  input         clk;
  input         OPL2_clk;
  input         reset;
  input         opl2_we;
  input [7:0]   opl2_data;
  input [7:0]   opl2_adr;
  output [8:0]  kon;
  output signed [15:0] channel_a;
  output signed [15:0] channel_b;
  output sample_clk;
  output sample_clk_128;

  localparam OPERATOR_PIPELINE_DELAY = 7;

  localparam NUM_OPERATOR_UPDATE_STATES = `NUM_OPERATORS_PER_BANK + 1;

  localparam
    IDLE = 0,
    CALC_OUTPUTS = 1;

  reg [7:0] opl2_reg[255:0];

  reg [8:0] cntr;
  reg sample_clk_en;

  reg nts;

  reg [17:0] am;
  reg [17:0] vib;
  reg [17:0] egt;
  reg [17:0] ksr;
  reg [3:0] mult[17:0];

  reg [1:0] ksl[17:0];
  reg [5:0] tl[17:0];

  reg [3:0] ar[17:0];
  reg [3:0] dr[17:0];

  reg [3:0] sl[17:0];
  reg [3:0] rr[17:0];

  reg [9:0] fnum[8:0];

  reg [8:0] kon;
  reg [2:0] block[8:0];
  reg sample_clk;
  reg sample_clk_128;

  reg dam;
  reg dvb;
  reg ryt;
  reg bd;
  reg sd;
  reg tom;
  reg tc;
  reg hh;

  reg [8:0] chb;
  reg [8:0] cha;
  reg [2:0] fb[8:0];
  reg [8:0] cnt;

  reg [1:0] ws[17:0];

  reg [9:0] fnum_tmp[17:0];
  reg [2:0] block_tmp[17:0];
  reg [2:0] fb_tmp[17:0];
  reg [2:0] op_type_tmp[17:0];
  reg [17:0] kon_tmp;
  reg [17:0] use_feedback;
  reg signed [12:0] modulation[17:0];

  reg [`CLOG2(OPERATOR_PIPELINE_DELAY)-1:0] delay_counter;

  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] delay_state;
  reg [`CLOG2(NUM_OPERATOR_UPDATE_STATES)-1:0] next_delay_state;

  reg [`CLOG2(`NUM_OPERATORS_PER_BANK)-1:0] op_num;

  wire signed [12:0] operator_out_tmp;
  reg signed [12:0] operator_out[17:0];

  wire latch_feedback_pulse;

  reg calc_state = IDLE;
  reg next_calc_state;

  reg [3:0] channel;

  reg signed [`SAMPLE_WIDTH-1:0] channel_2_op[8:0];

  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp = 0;
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_a_acc_pre_clamp_p[8:0];
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp = 0;
  reg signed [`CHANNEL_ACCUMULATOR_WIDTH-1:0] channel_b_acc_pre_clamp_p[8:0];

  reg signed [`SAMPLE_WIDTH-1:0] channel_a;
  reg signed [`SAMPLE_WIDTH-1:0] channel_b;

  genvar i;
  generate
    for (i = 0; i < 256; i = i + 1) begin: named
      always @ (posedge clk) begin
        if (reset)
          opl2_reg[i] <= 8'd0;
        else if (opl2_we && (opl2_adr == i))
          opl2_reg[i] <= opl2_data;
      end
    end
  endgenerate

  always @(posedge OPL2_clk)
    if (reset) begin
      cntr <= 9'd0;
      sample_clk_en <= 1'b0;
      sample_clk <= 1'b0;
    end else begin




      cntr <= cntr == 9'd499 ? 9'd0 : cntr + 1'b1;
      sample_clk_en <= cntr == 9'd0;
      sample_clk <= ~cntr[8];
      sample_clk_128 <= ~cntr[0];
    end


  always @(posedge OPL2_clk)
    if (reset) begin
      nts <= 1'b0;
      dam <= 1'b0;
      dvb <= 1'b0;
      ryt <= 1'b0;
      bd  <= 1'b0;
      sd  <= 1'b0;
      tom <= 1'b0;
      tc  <= 1'b0;
      hh  <= 1'b0;
    end else if (sample_clk_en) begin
      nts <= opl2_reg[8][6];
      dam <= opl2_reg['hBD][7];
      dvb <= opl2_reg['hBD][6];
      ryt <= opl2_reg['hBD][5];
      bd  <= opl2_reg['hBD][4];
      sd  <= opl2_reg['hBD][3];
      tom <= opl2_reg['hBD][2];
      tc  <= opl2_reg['hBD][1];
      hh  <= opl2_reg['hBD][0];
    end

  generate
    for (i = 0; i < 6; i = i + 1) begin: name1
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h20+i][7];
          vib[i]  <= opl2_reg['h20+i][6];
          egt[i]  <= opl2_reg['h20+i][5];
          ksr[i]  <= opl2_reg['h20+i][4];
          mult[i] <= opl2_reg['h20+i][3:0];

          ksl[i] <= opl2_reg['h40+i][7:6];
          tl[i]  <= opl2_reg['h40+i][5:0];

          ar[i] <= opl2_reg['h60+i][7:4];
          dr[i] <= opl2_reg['h60+i][3:0];

          sl[i] <= opl2_reg['h80+i][7:4];
          rr[i] <= opl2_reg['h80+i][3:0];

          ws[i] <= opl2_reg['hE0+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 6; i < 12; i = i + 1) begin: name2
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h22+i][7];
          vib[i]  <= opl2_reg['h22+i][6];
          egt[i]  <= opl2_reg['h22+i][5];
          ksr[i]  <= opl2_reg['h22+i][4];
          mult[i] <= opl2_reg['h22+i][3:0];

          ksl[i] <= opl2_reg['h42+i][7:6];
          tl[i]  <= opl2_reg['h42+i][5:0];

          ar[i] <= opl2_reg['h62+i][7:4];
          dr[i] <= opl2_reg['h62+i][3:0];

          sl[i] <= opl2_reg['h82+i][7:4];
          rr[i] <= opl2_reg['h82+i][3:0];

          ws[i] <= opl2_reg['hE2+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 12; i < 18; i = i + 1) begin: name3
      always @(posedge OPL2_clk) begin
        if (reset) begin
          am[i]   <= 1'b0;
          vib[i]  <= 1'b0;
          egt[i]  <= 1'b0;
          ksr[i]  <= 1'b0;
          mult[i] <= 4'd0;

          ksl[i] <= 2'd0;
          tl[i]  <= 6'd0;

          ar[i] <= 4'd0;
          dr[i] <= 4'd0;

          sl[i] <= 4'd0;
          rr[i] <= 4'd0;

          ws[i] <= 2'd0;
        end else if (sample_clk_en) begin
          am[i]   <= opl2_reg['h24+i][7];
          vib[i]  <= opl2_reg['h24+i][6];
          egt[i]  <= opl2_reg['h24+i][5];
          ksr[i]  <= opl2_reg['h24+i][4];
          mult[i] <= opl2_reg['h24+i][3:0];

          ksl[i] <= opl2_reg['h44+i][7:6];
          tl[i]  <= opl2_reg['h44+i][5:0];

          ar[i] <= opl2_reg['h64+i][7:4];
          dr[i] <= opl2_reg['h64+i][3:0];

          sl[i] <= opl2_reg['h84+i][7:4];
          rr[i] <= opl2_reg['h84+i][3:0];

          ws[i] <= opl2_reg['hE4+i][1:0];
        end
        end
      end
    endgenerate

    generate
    for (i = 0; i < 9; i = i + 1) begin: name4
      always @(posedge OPL2_clk) begin
        if (reset) begin
          fnum[i] <= 10'd0;

          kon[i] <= 1'b0;
          block[i] <= 3'd0;

          chb[i] <= 1'b0;
          cha[i] <= 1'b0;
          fb[i]  <= 3'd0;
          cnt[i] <= 1'b0;
        end else if (sample_clk_en) begin
          fnum[i][7:0] <= opl2_reg['hA0+i];
          fnum[i][9:8] <= opl2_reg['hB0+i][1:0];

          kon[i] <= opl2_reg['hB0+i][5];
          block[i] <= opl2_reg['hB0+i][4:2];

          chb[i] <= opl2_reg['hC0+i][5];
          cha[i] <= opl2_reg['hC0+i][4];
          fb[i]  <= opl2_reg['hC0+i][3:1];
          cnt[i] <= opl2_reg['hC0+i][0];
        end
        end
      end
    endgenerate

  always @ (*) begin

    fnum_tmp[0] = fnum[0];
    block_tmp[0] = block[0];
    kon_tmp[0] = kon[0];
    fb_tmp[0] = fb[0];
    op_type_tmp[0] = `OP_NORMAL;
    use_feedback[0] = 1;
    modulation[0] = 0;

    fnum_tmp[3] = fnum[0];
    block_tmp[3] = block[0];
    kon_tmp[3] = kon[0];
    fb_tmp[3] = 0;
    op_type_tmp[3] = `OP_NORMAL;
    use_feedback[3] = 0;
    modulation[3] = cnt[0] ? 0 : operator_out[0];

    fnum_tmp[1] = fnum[1];
    block_tmp[1] = block[1];
    kon_tmp[1] = kon[1];
    fb_tmp[1] = fb[1];
    op_type_tmp[1] = `OP_NORMAL;
    use_feedback[1] = 1;
    modulation[1] = 0;

    fnum_tmp[4] = fnum[1];
    block_tmp[4] = block[1];
    kon_tmp[4] = kon[1];
    fb_tmp[4] = 0;
    op_type_tmp[4] = `OP_NORMAL;
    use_feedback[4] = 0;
    modulation[4] = cnt[1] ? 0 : operator_out[1];

    fnum_tmp[2] = fnum[2];
    block_tmp[2] = block[2];
    kon_tmp[2] = kon[2];
    fb_tmp[2] = fb[2];
    op_type_tmp[2] = `OP_NORMAL;
    use_feedback[2] = 1;
    modulation[2] = 0;

    fnum_tmp[5] = fnum[2];
    block_tmp[5] = block[2];
    kon_tmp[5] = kon[2];
    fb_tmp[5] = 0;
    op_type_tmp[5] = `OP_NORMAL;
    use_feedback[5] = 0;
    modulation[5] = cnt[2] ? 0 : operator_out[2];

    fnum_tmp[6] = fnum[3];
    block_tmp[6] = block[3];
    kon_tmp[6] = kon[3];
    fb_tmp[6] = fb[3];
    op_type_tmp[6] = `OP_NORMAL;
    use_feedback[6] = 1;
    modulation[6] = 0;

    fnum_tmp[9] = fnum[3];
    block_tmp[9] = block[3];
    kon_tmp[9] = kon[3];
    fb_tmp[9] = 0;
    op_type_tmp[9] = `OP_NORMAL;
    use_feedback[9] = 0;
    modulation[9] = cnt[3] ? 0 : operator_out[6];

    fnum_tmp[7] = fnum[4];
    block_tmp[7] = block[4];
    kon_tmp[7] = kon[4];
    fb_tmp[7] = fb[4];
    op_type_tmp[7] = `OP_NORMAL;
    use_feedback[7] = 1;
    modulation[7] = 0;

    fnum_tmp[10] = fnum[4];
    block_tmp[10] = block[4];
    kon_tmp[10] = kon[4];
    fb_tmp[10] = 0;
    op_type_tmp[10] = `OP_NORMAL;
    use_feedback[10] = 0;
    modulation[10] = cnt[4] ? 0 : operator_out[7];

    fnum_tmp[8] = fnum[5];
    block_tmp[8] = block[5];
    kon_tmp[8] = kon[5];
    fb_tmp[8] = fb[5];
    op_type_tmp[8] = `OP_NORMAL;
    use_feedback[8] = 1;
    modulation[8] = 0;

    fnum_tmp[11] = fnum[5];
    block_tmp[11] = block[5];
    kon_tmp[11] = kon[5];
    fb_tmp[11] = 0;
    op_type_tmp[11] = `OP_NORMAL;
    use_feedback[11] = 0;
    modulation[11] = cnt[5] ? 0 : operator_out[8];


    fnum_tmp[12] = fnum[6];
    block_tmp[12] = block[6];
    kon_tmp[12] = kon[6];
    fb_tmp[12] = fb[6];
    op_type_tmp[12] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;
    use_feedback[12] = 1;
    modulation[12] = 0;


    fnum_tmp[15] = fnum[6];
    block_tmp[15] = block[6];
    kon_tmp[15] = kon[6];
    fb_tmp[15] = 0;
    op_type_tmp[15] = ryt ? `OP_BASS_DRUM : `OP_NORMAL;
    use_feedback[15] = 0;
    modulation[15] = cnt[6] ? 0 : operator_out[12];


    fnum_tmp[13] = fnum[7];
    block_tmp[13] = block[7];
    kon_tmp[13] = kon[7];
    fb_tmp[13] = ryt ? 0 : fb[7];
    op_type_tmp[13] = ryt ? `OP_HI_HAT : `OP_NORMAL;
    use_feedback[13] = ryt ? 0 : 1;
    modulation[13] = 0;


    fnum_tmp[16] = fnum[7];
    block_tmp[16] = block[7];
    kon_tmp[16] = kon[7];
    fb_tmp[16] = 0;
    op_type_tmp[16] = ryt ? `OP_SNARE_DRUM : `OP_NORMAL;
    use_feedback[16] = 0;
    modulation[16] = cnt[7] || ryt ? 0 : operator_out[13];


    fnum_tmp[14] = fnum[8];
    block_tmp[14] = block[8];
    kon_tmp[14] = kon[8];
    fb_tmp[14] = ryt ? 0 : fb[8];
    op_type_tmp[14] = ryt ? `OP_TOM_TOM : `OP_NORMAL;
    use_feedback[14] = ryt ? 0 : 1;
    modulation[14] = 0;


    fnum_tmp[17] = fnum[8];
    block_tmp[17] = block[8];
    kon_tmp[17] = kon[8];
    fb_tmp[17] = 0;
    op_type_tmp[17] = ryt ? `OP_TOP_CYMBAL : `OP_NORMAL;
    use_feedback[17] = 0;
    modulation[17] = cnt[8] || ryt ? 0 : operator_out[14];
  end

  always @(posedge OPL2_clk)
    if (reset)
      delay_state <= 5'd0;
    else
      delay_state <= next_delay_state;

  always @ (*)
    if (delay_state == 0)
      next_delay_state = sample_clk_en ? 1 : 0;
    else if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
      if (delay_state == NUM_OPERATOR_UPDATE_STATES - 1)
        next_delay_state = 0;
      else
        next_delay_state = delay_state + 1;
    else
      next_delay_state = delay_state;

  always @(posedge OPL2_clk)
    if (reset)
      delay_counter <= 0;
    else begin
      if (next_delay_state != delay_state)
        delay_counter <= 0;
      else if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
        delay_counter <= 0;
      else
        delay_counter <= delay_counter + 1;
    end

  always @ (*)
    if (delay_state == 0)
      op_num = 0;
    else
      op_num = delay_state - 1;


  operator operator_inst(
    .clk(OPL2_clk),
    .reset(reset),
    .sample_clk_en(delay_state != 0 && delay_counter == 0),
    .op_num(op_num),
    .fnum(fnum_tmp[op_num]),
    .mult(mult[op_num]),
    .block(block_tmp[op_num]),
    .ws(ws[op_num]),
    .vib(vib[op_num]),
    .kon(kon_tmp),
    .ar(ar[op_num]),
    .dr(dr[op_num]),
    .sl(sl[op_num]),
    .rr(rr[op_num]),
    .tl(tl[op_num]),
    .ksr(ksr[op_num]),
    .ksl(ksl[op_num]),
    .egt(egt[op_num]),
    .am(am[op_num]),
    .dam(dam),
    .dvb(dvb),
    .nts(nts),
    .bd(bd),
    .sd(sd),
    .tom(tom),
    .tc(tc),
    .hh(hh),
    .use_feedback(use_feedback[op_num]),
    .fb(fb_tmp[op_num]),
    .modulation(modulation[op_num]),
    .op_type(op_type_tmp[op_num]),
    .latch_feedback_pulse(latch_feedback_pulse),
    .out(operator_out_tmp)
  );

  always @(posedge OPL2_clk) begin
    if (delay_counter == OPERATOR_PIPELINE_DELAY - 1)
      operator_out[op_num] <= operator_out_tmp;
  end


  assign
    latch_feedback_pulse = delay_counter == OPERATOR_PIPELINE_DELAY - 1;


  always @(posedge OPL2_clk)
    if (reset)
      calc_state <= IDLE;
    else
      calc_state <= next_calc_state;

  always @ (*)
    case (calc_state)
    IDLE: next_calc_state = sample_clk_en ? CALC_OUTPUTS : IDLE;
    CALC_OUTPUTS: next_calc_state = channel == 8 ? IDLE : CALC_OUTPUTS;
    endcase

  always @(posedge OPL2_clk) begin
    if (calc_state == IDLE || channel == 8)
      channel <= 0;
    else
      channel <= channel + 1;
    end


  always @ (*) begin

    channel_2_op[0] = cnt[0] ? operator_out[0] + operator_out[3]
     : operator_out[3];
    channel_2_op[1] = cnt[1] ? operator_out[1] + operator_out[4]
     : operator_out[4];
    channel_2_op[2] = cnt[2] ? operator_out[2] + operator_out[5]
     : operator_out[5];
    channel_2_op[3] = cnt[3] ? operator_out[6] + operator_out[9]
     : operator_out[9];
    channel_2_op[4] = cnt[4] ? operator_out[7] + operator_out[10]
     : operator_out[10];
    channel_2_op[5] = cnt[5] ? operator_out[8] + operator_out[11]
     : operator_out[11];

    if (ryt)

      channel_2_op[6] = cnt[6] ? operator_out[15] : operator_out[12];
    else
      channel_2_op[6] = cnt[6] ? operator_out[12] + operator_out[15]
       : operator_out[15];


    channel_2_op[7] = cnt[7] || (ryt) ? operator_out[13] + operator_out[16]
     : operator_out[16];


    channel_2_op[8] = cnt[8] || (ryt)  ? operator_out[14] + operator_out[17]
     : operator_out[17];

  end

  always @(posedge OPL2_clk) begin
    channel_a_acc_pre_clamp_p[0] <= cha[0] ? channel_2_op[0] : 0;
    channel_a_acc_pre_clamp_p[1] <= cha[1] ? channel_2_op[1] : 0;
    channel_a_acc_pre_clamp_p[2] <= cha[2] ? channel_2_op[2] : 0;
    channel_a_acc_pre_clamp_p[3] <= cha[3] ? channel_2_op[3] : 0;
    channel_a_acc_pre_clamp_p[4] <= cha[4] ? channel_2_op[4] : 0;
    channel_a_acc_pre_clamp_p[5] <= cha[5] ? channel_2_op[5] : 0;
    channel_a_acc_pre_clamp_p[6] <= cha[6] ? channel_2_op[6] : 0;
    channel_a_acc_pre_clamp_p[7] <= cha[7] ? channel_2_op[7] : 0;
    channel_a_acc_pre_clamp_p[8] <= cha[8] ? channel_2_op[8] : 0;
    channel_b_acc_pre_clamp_p[0] <= chb[0] ? channel_2_op[0] : 0;
    channel_b_acc_pre_clamp_p[1] <= chb[1] ? channel_2_op[1] : 0;
    channel_b_acc_pre_clamp_p[2] <= chb[2] ? channel_2_op[2] : 0;
    channel_b_acc_pre_clamp_p[3] <= chb[3] ? channel_2_op[3] : 0;
    channel_b_acc_pre_clamp_p[4] <= chb[4] ? channel_2_op[4] : 0;
    channel_b_acc_pre_clamp_p[5] <= chb[5] ? channel_2_op[5] : 0;
    channel_b_acc_pre_clamp_p[6] <= chb[6] ? channel_2_op[6] : 0;
    channel_b_acc_pre_clamp_p[7] <= chb[7] ? channel_2_op[7] : 0;
    channel_b_acc_pre_clamp_p[8] <= chb[8] ? channel_2_op[8] : 0;
  end


  always @(posedge OPL2_clk)
    if (sample_clk_en)
      channel_a_acc_pre_clamp <= 0;
    else if (calc_state == CALC_OUTPUTS)
      channel_a_acc_pre_clamp <= channel_a_acc_pre_clamp +
       channel_a_acc_pre_clamp_p[channel];

  always @(posedge OPL2_clk)
    if (sample_clk_en)
      channel_b_acc_pre_clamp <= 0;
    else if (calc_state == CALC_OUTPUTS)
      channel_b_acc_pre_clamp <= channel_b_acc_pre_clamp +
       channel_b_acc_pre_clamp_p[channel];


  always @(posedge OPL2_clk)
    if (sample_clk_en) begin
      if (channel_a_acc_pre_clamp > 2**15 - 1)
        channel_a <= 2**15 - 1;
      else if (channel_a_acc_pre_clamp < -2**15)
        channel_a <= -2**15;
      else
        channel_a <= channel_a_acc_pre_clamp;

      if (channel_b_acc_pre_clamp > 2**15 - 1)
        channel_b <= 2**15 - 1;
      else if (channel_b_acc_pre_clamp < -2**15)
        channel_b <= -2**15;
      else
        channel_b <= channel_b_acc_pre_clamp;
    end

endmodule