data/full_repos/permissive/490492655/M1_testbench.v
1: b'%Error: data/full_repos/permissive/490492655/M1_testbench.v:16: Unsupported or unknown PLI call: $monitor\n      $monitor ($time, " rst=%b, sel=%d, in1=%d, in2=%d, out=%d", rst,sel,in1,in2,out);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/490492655/M1_testbench.v:23: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("M1.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/490492655/M1_testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, M1_testbench);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/490492655/M1_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #0 rst=1; clk=0; in1=0; in2=7; sel=0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/490492655/M1_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n          #25 clk <= ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/490492655/M1_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n          #25 rst <= (i%5==0) ? 1:0; clk <= ~clk; in1 <= in1 + 1; in2 <= in2 -1 ; sel <= sel + 1;\n          ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module M1_testbench ();

  wire [0:6] out;
  reg rst, clk;
  reg [1:0] sel;
  reg [2:0] in1, in2;
  
  M1 DUT(.out(out), .rst(rst), .clk(clk), .sel(sel), .in1(in1), .in2(in2));
  
  initial 
    begin
      $monitor ($time, " rst=%b, sel=%d, in1=%d, in2=%d, out=%d", rst,sel,in1,in2,out);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("M1.vcd");
      $dumpvars(1, M1_testbench);

      #0 rst=1; clk=0; in1=0; in2=7; sel=0;

      for (i = 1; i <= 14; i = i + 1)
        begin
          #25 clk <= ~clk;
          #25 rst <= (i%5==0) ? 1:0; clk <= ~clk; in1 <= in1 + 1; in2 <= in2 -1 ; sel <= sel + 1;
        end
    end
endmodule
module M1_testbench ();


  wire [0:6] out;
  reg rst, clk;
  reg [1:0] sel;
  reg [2:0] in1, in2;
  
  M1 DUT(.out(out), .rst(rst), .clk(clk), .sel(sel), .in1(in1), .in2(in2));
  
  initial 
    begin
      $monitor ($time, " rst=%b, sel=%d, in1=%d, in2=%d, out=%d", rst,sel,in1,in2,out);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("M1.vcd");
      $dumpvars(1, M1_testbench);

      #0 rst=1; clk=0; in1=0; in2=7; sel=0;

      for (i = 1; i <= 14; i = i + 1)
        begin
          #25 clk <= ~clk;
          #25 rst <= (i%5==0) ? 1:0; clk <= ~clk; in1 <= in1 + 1; in2 <= in2 -1 ; sel <= sel + 1;
        end
    end
endmodule