data/full_repos/permissive/452016975/src/alu_control_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/alu_control_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/452016975/src/alu_control_testbench.v:37: Unsupported or unknown PLI call: $monitor\n $monitor("time=%2d,alu_op=%3b,function=%3b,alu_ctrl=%3b",$time,alu_op,func,alu_ctrl);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_control_testbench();
	
	reg [2:0] alu_op;
	reg [2:0] func;
	wire [2:0] alu_ctrl;
	alu_control my_alu_ctr(alu_op,func,alu_ctrl);
	initial begin
	alu_op = 3'b110; func =3'b110;
	#20;
	alu_op = 3'b011; func =3'b110;
	#20;
	alu_op = 3'b111; func =3'b110;
	#20;
	alu_op = 3'b001; func =3'b110;
	#20;
	alu_op = 3'b010; func =3'b110;
	#20;
	alu_op = 3'b101; func =3'b110;
	#20;
	alu_op = 3'b000; func =3'b110;
	#20;
	alu_op = 3'b100; func =3'b000;
	#20;
	alu_op = 3'b100; func =3'b001;
	#20;
	alu_op = 3'b100; func =3'b010;
	#20;
	alu_op = 3'b100; func =3'b011;
	#20;
	alu_op = 3'b100; func =3'b100;
	#20;
	alu_op = 3'b100; func =3'b101;
	#20;
	
	end
	initial begin
	$monitor("time=%2d,alu_op=%3b,function=%3b,alu_ctrl=%3b",$time,alu_op,func,alu_ctrl);
	end
endmodule
module alu_control_testbench();

	
	reg [2:0] alu_op;
	reg [2:0] func;
	wire [2:0] alu_ctrl;
	alu_control my_alu_ctr(alu_op,func,alu_ctrl);
	initial begin
	alu_op = 3'b110; func =3'b110;
	#20;
	alu_op = 3'b011; func =3'b110;
	#20;
	alu_op = 3'b111; func =3'b110;
	#20;
	alu_op = 3'b001; func =3'b110;
	#20;
	alu_op = 3'b010; func =3'b110;
	#20;
	alu_op = 3'b101; func =3'b110;
	#20;
	alu_op = 3'b000; func =3'b110;
	#20;
	alu_op = 3'b100; func =3'b000;
	#20;
	alu_op = 3'b100; func =3'b001;
	#20;
	alu_op = 3'b100; func =3'b010;
	#20;
	alu_op = 3'b100; func =3'b011;
	#20;
	alu_op = 3'b100; func =3'b100;
	#20;
	alu_op = 3'b100; func =3'b101;
	#20;
	
	end
	initial begin
	$monitor("time=%2d,alu_op=%3b,function=%3b,alu_ctrl=%3b",$time,alu_op,func,alu_ctrl);
	end
endmodule