data/full_repos/permissive/423547971/FPGA Projects/Johnson Counter 4-bit/oneHz_gen.v
1: b'%Error: Cannot find file containing module: Projects/Johnson\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Johnson\n             data/full_repos/permissive/423547971/FPGA/Projects/Johnson.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Johnson.sv\n             Projects/Johnson\n             Projects/Johnson.v\n             Projects/Johnson.sv\n             obj_dir/Projects/Johnson\n             obj_dir/Projects/Johnson.v\n             obj_dir/Projects/Johnson.sv\n%Error: Cannot find file containing module: Counter\n%Error: Cannot find file containing module: 4-bit,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: 4-bit/oneHz_gen.v\n%Error: Exiting due to 5 error(s)\n'
module oneHz_gen(
    input clk_100MHz,
    input reset,
    output clk_1Hz
    );
    
    reg [25:0] r_counter = 0;
    reg clk_out = 0;
    
    always @(posedge clk_100MHz or posedge reset)
        if(reset)
            r_counter <= 26'b0;
        else 
            if(r_counter == 49_999_999) begin
                r_counter <= 26'b0;
                clk_out <= ~clk_out;
            end
            else
                r_counter <= r_counter + 1;
    
    assign clk_1Hz = clk_out;
    
endmodule
module oneHz_gen(
    input clk_100MHz,
    input reset,
    output clk_1Hz
    );

    
    reg [25:0] r_counter = 0;
    reg clk_out = 0;
    
    always @(posedge clk_100MHz or posedge reset)
        if(reset)
            r_counter <= 26'b0;
        else 
            if(r_counter == 49_999_999) begin
                r_counter <= 26'b0;
                clk_out <= ~clk_out;
            end
            else
                r_counter <= r_counter + 1;
    
    assign clk_1Hz = clk_out;
    
endmodule