data/full_repos/permissive/525406203/wallace_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d10; b = 8\'d10; #50;\n                       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d25; b = 8\'d100; #50;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d5; b = 8\'d5; #50;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d64; b = 8\'d69; #100;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d15; b = 8\'d5; #100;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d99; b = 8\'d10; #100;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d78; b = 8\'d90; #100;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'d110; b = 8\'d0; #100;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n a = 8\'b11111110; b = 8\'b10000000; #100;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/525406203/wallace_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: data/full_repos/permissive/525406203/wallace_testbench.v:6: Cannot find file containing module: \'wallace_8\'\nwallace_8 DUT (.a(a),.b(b),.product(product));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525406203,data/full_repos/permissive/525406203/wallace_8\n             data/full_repos/permissive/525406203,data/full_repos/permissive/525406203/wallace_8.v\n             data/full_repos/permissive/525406203,data/full_repos/permissive/525406203/wallace_8.sv\n             wallace_8\n             wallace_8.v\n             wallace_8.sv\n             obj_dir/wallace_8\n             obj_dir/wallace_8.v\n             obj_dir/wallace_8.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wallace_testbench;
reg [7:0]a;
reg [7:0]b;
wire [15:0]product;

wallace_8 DUT (.a(a),.b(b),.product(product));
initial
begin

 
 a = 8'd10; b = 8'd10; #50;
 a = 8'd25; b = 8'd100; #50;
 a = 8'd5; b = 8'd5; #50;
 a = 8'd64; b = 8'd69; #100;
 a = 8'd15; b = 8'd5; #100;
 a = 8'd99; b = 8'd10; #100;
 a = 8'd78; b = 8'd90; #100;
 a = 8'd110; b = 8'd0; #100;
 a = 8'b11111110; b = 8'b10000000; #100;
 #5 $finish;
end
endmodule
module wallace_testbench;

reg [7:0]a;
reg [7:0]b;
wire [15:0]product;

wallace_8 DUT (.a(a),.b(b),.product(product));
initial
begin

 
 a = 8'd10; b = 8'd10; #50;
 a = 8'd25; b = 8'd100; #50;
 a = 8'd5; b = 8'd5; #50;
 a = 8'd64; b = 8'd69; #100;
 a = 8'd15; b = 8'd5; #100;
 a = 8'd99; b = 8'd10; #100;
 a = 8'd78; b = 8'd90; #100;
 a = 8'd110; b = 8'd0; #100;
 a = 8'b11111110; b = 8'b10000000; #100;
 #5 $finish;
end
endmodule