data/full_repos/permissive/426889244/tb/soc_IO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #106\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #30000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #80\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #4000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #80\n        ^\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:35: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            if (soc.core0.IMEM_rdata[31:26] == 6\'b000100 || soc.core0.IMEM_rdata[31:26] == 6\'b000101 || (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001000)) begin\n                    ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:35: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            if (soc.core0.IMEM_rdata[31:26] == 6\'b000100 || soc.core0.IMEM_rdata[31:26] == 6\'b000101 || (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001000)) begin\n                                                                ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:35: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            if (soc.core0.IMEM_rdata[31:26] == 6\'b000100 || soc.core0.IMEM_rdata[31:26] == 6\'b000101 || (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001000)) begin\n                                                                                                             ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:35: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            if (soc.core0.IMEM_rdata[31:26] == 6\'b000100 || soc.core0.IMEM_rdata[31:26] == 6\'b000101 || (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001000)) begin\n                                                                                                                                                         ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:38: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            else if (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001100) begin\n                         ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: data/full_repos/permissive/426889244/tb/soc_IO_tb.v:38: Can\'t find definition of \'core0\' in dotted scope/variable: \'soc.core0\'\n            else if (soc.core0.IMEM_rdata[31:26] == 6\'b000000 && soc.core0.IMEM_rdata[5:0] == 6\'b001100) begin\n                                                                     ^~~~~\n        ... Known scopes under \'soc\': <no cells found>\n%Error: Exiting due to 6 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module soc_tb();
    reg clk;
    reg reset;
    reg[15:0] opr;
    reg interrupt;

    wire[15:0] result;
    wire[7:0] o_seg;
    wire[7:0] o_sel;

    integer blank;
    SoC soc(
        .base_clk(clk),
        .reset(reset),
        .interrupt(interrupt),
        .opr(opr),
        .leds(result),
        .o_seg(o_seg),
        .o_sel(o_sel)
    );

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        blank = 0;
        #1
        forever begin
            #10
            if (soc.core0.IMEM_rdata[31:26] == 6'b000100 || soc.core0.IMEM_rdata[31:26] == 6'b000101 || (soc.core0.IMEM_rdata[31:26] == 6'b000000 && soc.core0.IMEM_rdata[5:0] == 6'b001000)) begin
                blank = blank + 1;
            end
            else if (soc.core0.IMEM_rdata[31:26] == 6'b000000 && soc.core0.IMEM_rdata[5:0] == 6'b001100) begin
                blank = blank + 2;
            end
        end
    end
    initial begin



        reset = 1;
        opr = 32;
        interrupt = 0;

        #106
        reset = 0;

        #30000
        interrupt = 1;

        #80
        interrupt = 0;

        #4000
        interrupt = 1;

        #80
        interrupt = 0;



    end
    
endmodule
module soc_tb();

    reg clk;
    reg reset;
    reg[15:0] opr;
    reg interrupt;

    wire[15:0] result;
    wire[7:0] o_seg;
    wire[7:0] o_sel;

    integer blank;
    SoC soc(
        .base_clk(clk),
        .reset(reset),
        .interrupt(interrupt),
        .opr(opr),
        .leds(result),
        .o_seg(o_seg),
        .o_sel(o_sel)
    );

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        blank = 0;
        #1
        forever begin
            #10
            if (soc.core0.IMEM_rdata[31:26] == 6'b000100 || soc.core0.IMEM_rdata[31:26] == 6'b000101 || (soc.core0.IMEM_rdata[31:26] == 6'b000000 && soc.core0.IMEM_rdata[5:0] == 6'b001000)) begin
                blank = blank + 1;
            end
            else if (soc.core0.IMEM_rdata[31:26] == 6'b000000 && soc.core0.IMEM_rdata[5:0] == 6'b001100) begin
                blank = blank + 2;
            end
        end
    end
    initial begin



        reset = 1;
        opr = 32;
        interrupt = 0;

        #106
        reset = 0;

        #30000
        interrupt = 1;

        #80
        interrupt = 0;

        #4000
        interrupt = 1;

        #80
        interrupt = 0;



    end
    
endmodule