data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:96: Define or directive not defined: \'`x_or_0\'\n            wr_req_in <= `x_or_0;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wr_req_in <= `x_or_0;\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:132: Define or directive not defined: \'`x_or_0\'\n            wr_count <= {2{`x_or_0}};\n                           ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:132: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            wr_count <= {2{`x_or_0}};\n                                  ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:185: Define or directive not defined: \'`x_or_0\'\n            rd_adr <= {1{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:185: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_adr <= {1{`x_or_0}};\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:365: Define or directive not defined: \'`x_or_0\'\n            rd_count_p <= {2{`x_or_0}};\n                             ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:365: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_count_p <= {2{`x_or_0}};\n                                    ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:386: Define or directive not defined: \'`x_or_0\'\n        NV_AFIFO_rd_data <= {34{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:386: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        NV_AFIFO_rd_data <= {34{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:643: Define or directive not defined: \'`x_or_0\'\n    default: dout = {34{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:643: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {34{`x_or_0}};\n                               ^\n%Error: Exiting due to 13 error(s)\n'
module vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 (
   Wa0, we0, Di0,
   Ra0, Do0
   );
input [0:0] Wa0;
input we0;
input [33:0] Di0;
input [0:0] Ra0;
output [33:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 34'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [33:0] mem[1:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [33:0] Q0 = mem[0];
wire [33:0] Q1 = mem[1];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule
module vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 (
   Wa0, we0, Di0,
   Ra0, Do0
   );

input [0:0] Wa0;
input we0;
input [33:0] Di0;
input [0:0] Ra0;
output [33:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 34'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [33:0] mem[1:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [33:0] Q0 = mem[0];
wire [33:0] Q1 = mem[1];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule