data/full_repos/permissive/441359809/src/yosys/tests/simple/arraycells.v
data/verilator_xmls/6aecb8fc-94c6-4b17-b8e6-4cc5b5faeabb.xml
module array_test001(a, b, c, y);
	input a;
	input [31:0] b, c;
	output [31:0] y;

	aoi12 p [31:0] (a, b, c, y);
endmodule
module array_test001(a, b, c, y);

	input a;
	input [31:0] b, c;
	output [31:0] y;

	aoi12 p [31:0] (a, b, c, y);
endmodule