data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/components/one_of_n.tmp.v
data/verilator_xmls/e79aabb7-d5cf-478b-8c55-94b4b098a0fd.xml
module one_of_n(
  
  in0,
  in1,

  sel,
  out);
    parameter WIDTH = 8;
    parameter BHC = 10;
    input [0:0] sel;
    input [WIDTH-1:0] in0,in1;

    output reg [WIDTH-1:0] out;
    always@(*)
    begin
        out={WIDTH{1'b0}};
        case(sel)
        
            1'd0:out=in0;
            1'd1:out=in1;

            default:;
        endcase
    end
endmodule
module one_of_n(
  
  in0,
  in1,

  sel,
  out);

    parameter WIDTH = 8;
    parameter BHC = 10;
    input [0:0] sel;
    input [WIDTH-1:0] in0,in1;

    output reg [WIDTH-1:0] out;
    always@(*)
    begin
        out={WIDTH{1'b0}};
        case(sel)
        
            1'd0:out=in0;
            1'd1:out=in1;

            default:;
        endcase
    end
endmodule