data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/stdcells_S.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/stdcells_S.v:418: Can't resolve module reference: '$_XOR_'\n\\$_XOR_ gate1 ( .A(A), .B(C), .Y(t1) );\n        ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module \$__shift (X, A, Y);

parameter WIDTH = 1;
parameter SHIFT = 0;

input X;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;

genvar i;
generate
	for (i = 0; i < WIDTH; i = i + 1) begin:V
		if (i+SHIFT < 0) begin
			assign Y[i] = 0;
		end else
		if (i+SHIFT < WIDTH) begin
			assign Y[i] = A[i+SHIFT];
		end else begin
			assign Y[i] = X;
		end
	end
endgenerate

endmodule
module \$__shift (X, A, Y);


parameter WIDTH = 1;
parameter SHIFT = 0;

input X;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;

genvar i;
generate
	for (i = 0; i < WIDTH; i = i + 1) begin:V
		if (i+SHIFT < 0) begin
			assign Y[i] = 0;
		end else
		if (i+SHIFT < WIDTH) begin
			assign Y[i] = A[i+SHIFT];
		end else begin
			assign Y[i] = X;
		end
	end
endgenerate

endmodule