data/full_repos/permissive/507383616/rtl/main_gpio_complex.v
1: b'%Error: data/full_repos/permissive/507383616/rtl/main_gpio_complex.v:84: Duplicate declaration of signal: \'output_io_signal\'\n                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire [OUTPUTS - 1 : 0] output_io_signal;\n                           ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/507383616/rtl/main_gpio_complex.v:40: ... Location of original declaration\n    output [OUTPUTS - 1 : 0]output_io_signal,\n                            ^~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/507383616/rtl/main_gpio_complex.v:112: Signal definition not found, creating implicitly: \'xor_reduce_3_out_io\'\n                                                                                   : ... Suggested alternative: \'xor_reduce_1_out_io\'\n    assign xor_reduce_3_out_io = |xor_3_out_io;\n           ^~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module main_gpio_complex #
(
    parameter WORD_SIZE = 32,
    parameter SIZE_WORD = 3,
    parameter INPUT_DATA_SIZE = 52,
    parameter STATUS_SIGNALS = 6,
    parameter DATA_WIDTH = 8,
    parameter BAUD_RATE = 115200,
    parameter CLOCK_SPEED = 125000000,
    parameter OUTPUTS = 32,
    parameter INPUTS = 32
)
(
    input wire clk,
    input wire rx,
    input wire rst,
    input wire [INPUTS - 1 : 0]input_io,
    output [OUTPUTS - 1 : 0]output_io_signal,
    output wire [2:0] trx_error,
    output wire [2:0] output_io_error, 
    output wire [2:0] command_arrive,
    output wire [2:0] command_arrive_discrepancy,
    output tx
    );

    reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);




    wire uart_output_signal;
    wire uart_output_signal_inst_1;
    wire uart_output_signal_inst_2;
    wire uart_output_signal_inst_3;

    assign tx = uart_output_signal;

    wire nand_1_trx;
    wire nand_2_trx;
    wire nand_3_trx;
    wire xor_1_trx;
    wire xor_2_trx;
    wire xor_3_trx;
    wire xor_reduce_1_trx;
    wire xor_reduce_2_trx;
    wire xor_reduce_3_trx;

    (* mark_debug = "true" *) assign nand_1_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_2);
    (* mark_debug = "true" *) assign nand_2_trx  = ~(uart_output_signal_inst_2 & uart_output_signal_inst_3);
    (* mark_debug = "true" *) assign nand_3_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_3);
    (* mark_debug = "true" *) assign uart_output_signal = ~(nand_1_trx & nand_2_trx & nand_3_trx);

    assign xor_1_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_2;
    assign xor_2_trx  = uart_output_signal_inst_2 ^ uart_output_signal_inst_3;
    assign xor_3_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_3;
    assign xor_reduce_1_trx = |xor_1_trx;
    assign xor_reduce_2_trx = |xor_2_trx;
    assign xor_reduce_3_trx = |xor_3_trx;

    

    wire [OUTPUTS - 1 : 0] output_io_signal;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_1;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_2;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_3;



    wire [OUTPUTS - 1 : 0] nand_1_out_io;
    wire [OUTPUTS - 1 : 0] nand_2_out_io;
    wire [OUTPUTS - 1 : 0] nand_3_out_io;
    wire [OUTPUTS - 1 : 0] xor_1_out_io;
    wire [OUTPUTS - 1 : 0] xor_2_out_io;
    wire [OUTPUTS - 1 : 0] xor_3_out_io;
    wire xor_reduce_1_out_io;
    wire xor_reduce_2_out_io;
    wire xor_reduce_3_out_iotrx_error;


    (* mark_debug = "true" *) assign nand_1_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_2);
    (* mark_debug = "true" *) assign nand_2_out_io  = ~(output_io_signal_inst_2 & output_io_signal_inst_3);
    (* mark_debug = "true" *) assign nand_3_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_3);
    (* mark_debug = "true" *) assign output_io_signal = ~(nand_1_out_io & nand_2_out_io & nand_3_out_io);

    assign xor_1_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_2;
    assign xor_2_out_io  = output_io_signal_inst_2 ^ output_io_signal_inst_3;
    assign xor_3_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_3;
    assign xor_reduce_1_out_io = |xor_1_out_io;
    assign xor_reduce_2_out_io = |xor_2_out_io;
    assign xor_reduce_3_out_io = |xor_3_out_io;

    

    wire command_arrive_inst_1;
    wire command_arrive_inst_2;
    wire command_arrive_inst_3;

    wire xor_1_command_in;
    wire xor_2_command_in;
    wire xor_3_command_in;
    wire xor_reduce_1_command_in;
    wire xor_reduce_2_command_in;
    wire xor_reduce_3_command_in;

    assign xor_1_command_in  = command_arrive_inst_1 ^ command_arrive_inst_2;
    assign xor_2_command_in  = command_arrive_inst_2 ^ command_arrive_inst_3;
    assign xor_3_command_in  = command_arrive_inst_1 ^ command_arrive_inst_3;
    assign xor_reduce_1_command_in = |xor_1_command_in;
    assign xor_reduce_2_command_in = |xor_2_command_in;
    assign xor_reduce_3_command_in = |xor_3_command_in;


    assign output_io_error = {xor_reduce_3_out_io,xor_reduce_2_out_io,xor_reduce_1_out_io};
    assign trx_error = {xor_reduce_3_trx,xor_reduce_2_trx, xor_reduce_1_trx};
    assign command_arrive_discrepancy = {xor_reduce_3_command_in,xor_reduce_2_command_in,xor_reduce_1_command_in};
    assign command_arrive = {command_arrive_inst_1,command_arrive_inst_2,command_arrive_inst_3};




    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_1(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_1),
        .valid_io(),
        .output_io(output_io_signal_inst_1),
        .command_valid(command_arrive_inst_1)
    );

    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_2(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_2),
        .valid_io(),
        .output_io(output_io_signal_inst_2),
        .command_valid(command_arrive_inst_2)
    );

    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_3(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_3),
        .valid_io(),
        .output_io(output_io_signal_inst_3),
        .command_valid(command_arrive_inst_3)
    );

endmodule
module main_gpio_complex #
(
    parameter WORD_SIZE = 32,
    parameter SIZE_WORD = 3,
    parameter INPUT_DATA_SIZE = 52,
    parameter STATUS_SIGNALS = 6,
    parameter DATA_WIDTH = 8,
    parameter BAUD_RATE = 115200,
    parameter CLOCK_SPEED = 125000000,
    parameter OUTPUTS = 32,
    parameter INPUTS = 32
)
(
    input wire clk,
    input wire rx,
    input wire rst,
    input wire [INPUTS - 1 : 0]input_io,
    output [OUTPUTS - 1 : 0]output_io_signal,
    output wire [2:0] trx_error,
    output wire [2:0] output_io_error, 
    output wire [2:0] command_arrive,
    output wire [2:0] command_arrive_discrepancy,
    output tx
    );


    reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);




    wire uart_output_signal;
    wire uart_output_signal_inst_1;
    wire uart_output_signal_inst_2;
    wire uart_output_signal_inst_3;

    assign tx = uart_output_signal;

    wire nand_1_trx;
    wire nand_2_trx;
    wire nand_3_trx;
    wire xor_1_trx;
    wire xor_2_trx;
    wire xor_3_trx;
    wire xor_reduce_1_trx;
    wire xor_reduce_2_trx;
    wire xor_reduce_3_trx;

    (* mark_debug = "true" *) assign nand_1_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_2);
    (* mark_debug = "true" *) assign nand_2_trx  = ~(uart_output_signal_inst_2 & uart_output_signal_inst_3);
    (* mark_debug = "true" *) assign nand_3_trx  = ~(uart_output_signal_inst_1 & uart_output_signal_inst_3);
    (* mark_debug = "true" *) assign uart_output_signal = ~(nand_1_trx & nand_2_trx & nand_3_trx);

    assign xor_1_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_2;
    assign xor_2_trx  = uart_output_signal_inst_2 ^ uart_output_signal_inst_3;
    assign xor_3_trx  = uart_output_signal_inst_1 ^ uart_output_signal_inst_3;
    assign xor_reduce_1_trx = |xor_1_trx;
    assign xor_reduce_2_trx = |xor_2_trx;
    assign xor_reduce_3_trx = |xor_3_trx;

    

    wire [OUTPUTS - 1 : 0] output_io_signal;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_1;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_2;
    wire [OUTPUTS - 1 : 0] output_io_signal_inst_3;



    wire [OUTPUTS - 1 : 0] nand_1_out_io;
    wire [OUTPUTS - 1 : 0] nand_2_out_io;
    wire [OUTPUTS - 1 : 0] nand_3_out_io;
    wire [OUTPUTS - 1 : 0] xor_1_out_io;
    wire [OUTPUTS - 1 : 0] xor_2_out_io;
    wire [OUTPUTS - 1 : 0] xor_3_out_io;
    wire xor_reduce_1_out_io;
    wire xor_reduce_2_out_io;
    wire xor_reduce_3_out_iotrx_error;


    (* mark_debug = "true" *) assign nand_1_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_2);
    (* mark_debug = "true" *) assign nand_2_out_io  = ~(output_io_signal_inst_2 & output_io_signal_inst_3);
    (* mark_debug = "true" *) assign nand_3_out_io  = ~(output_io_signal_inst_1 & output_io_signal_inst_3);
    (* mark_debug = "true" *) assign output_io_signal = ~(nand_1_out_io & nand_2_out_io & nand_3_out_io);

    assign xor_1_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_2;
    assign xor_2_out_io  = output_io_signal_inst_2 ^ output_io_signal_inst_3;
    assign xor_3_out_io  = output_io_signal_inst_1 ^ output_io_signal_inst_3;
    assign xor_reduce_1_out_io = |xor_1_out_io;
    assign xor_reduce_2_out_io = |xor_2_out_io;
    assign xor_reduce_3_out_io = |xor_3_out_io;

    

    wire command_arrive_inst_1;
    wire command_arrive_inst_2;
    wire command_arrive_inst_3;

    wire xor_1_command_in;
    wire xor_2_command_in;
    wire xor_3_command_in;
    wire xor_reduce_1_command_in;
    wire xor_reduce_2_command_in;
    wire xor_reduce_3_command_in;

    assign xor_1_command_in  = command_arrive_inst_1 ^ command_arrive_inst_2;
    assign xor_2_command_in  = command_arrive_inst_2 ^ command_arrive_inst_3;
    assign xor_3_command_in  = command_arrive_inst_1 ^ command_arrive_inst_3;
    assign xor_reduce_1_command_in = |xor_1_command_in;
    assign xor_reduce_2_command_in = |xor_2_command_in;
    assign xor_reduce_3_command_in = |xor_3_command_in;


    assign output_io_error = {xor_reduce_3_out_io,xor_reduce_2_out_io,xor_reduce_1_out_io};
    assign trx_error = {xor_reduce_3_trx,xor_reduce_2_trx, xor_reduce_1_trx};
    assign command_arrive_discrepancy = {xor_reduce_3_command_in,xor_reduce_2_command_in,xor_reduce_1_command_in};
    assign command_arrive = {command_arrive_inst_1,command_arrive_inst_2,command_arrive_inst_3};




    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_1(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_1),
        .valid_io(),
        .output_io(output_io_signal_inst_1),
        .command_valid(command_arrive_inst_1)
    );

    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_2(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_2),
        .valid_io(),
        .output_io(output_io_signal_inst_2),
        .command_valid(command_arrive_inst_2)
    );

    control_module #(
        .WORD_SIZE(WORD_SIZE),
        .SIZE_WORD(SIZE_WORD),
        .STATUS_SIGNALS(STATUS_SIGNALS),
        .DATA_WIDTH(DATA_WIDTH),
        .INPUT_DATA_SIZE(INPUT_DATA_SIZE),
        .OUTPUTS(OUTPUTS),
        .INPUTS(INPUTS)
    )
    control_module_inst_3(
        .clk(clk),
        .rtx(rx),
        .rst(rst),
        .preescalar_data_rate(preescalar_data_rate),
        .input_io(input_io),
        .staus_control_module(),
        .trx(uart_output_signal_inst_3),
        .valid_io(),
        .output_io(output_io_signal_inst_3),
        .command_valid(command_arrive_inst_3)
    );

endmodule