data/full_repos/permissive/413440740/source/def_freq_i2c.v
1: b'%Warning-WIDTH: data/full_repos/permissive/413440740/source/def_freq_i2c.v:25: Operator GT expects 9 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance def_freq_i2c\n    assign en_str = cnt == (sv_cnt >> 1\'b1) & (cnt > 1\'b0);\n                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module def_freq_i2c
    #(parameter FPGA_CLK = 50_000_000,
      parameter I2C_CLK  = 100_000,
      parameter NUM_CYC  = FPGA_CLK / I2C_CLK,
      parameter CNT_SZ   = $clog2(NUM_CYC))
    (CLK, RST_n, I_SCL, I_RS_IO_SCL, I_FL_IO_SCL,
     O_MDL_LW_IO_SCL, O_MDL_HG_IO_SCL);



    input wire CLK;
    input wire RST_n;
    input wire I_SCL;
    input wire I_RS_IO_SCL;
    input wire I_FL_IO_SCL;

    output reg O_MDL_LW_IO_SCL;
    output reg O_MDL_HG_IO_SCL;

    reg [CNT_SZ-1:0] cnt;
    reg [CNT_SZ-1:0] sv_cnt;
    wire             en_str;


    assign en_str = cnt == (sv_cnt >> 1'b1) & (cnt > 1'b0);


    always @(posedge CLK or negedge RST_n) begin
        if (!RST_n)
            begin
                cnt <= {CNT_SZ{1'b0}};
                sv_cnt <= {CNT_SZ{1'b0}};
                O_MDL_LW_IO_SCL <= 1'b0;
                O_MDL_HG_IO_SCL <= 1'b0;
            end
        else
            begin
                cnt <= I_FL_IO_SCL || I_RS_IO_SCL ? {CNT_SZ{1'b0}} : cnt + 1'b1;
                sv_cnt <= I_FL_IO_SCL ? cnt : sv_cnt;
                O_MDL_LW_IO_SCL <= !I_SCL & en_str ? 1'b1 : 1'b0;
                O_MDL_HG_IO_SCL <= I_SCL & en_str ? 1'b1 : 1'b0;
            end
    end


endmodule
module def_freq_i2c
    #(parameter FPGA_CLK = 50_000_000,
      parameter I2C_CLK  = 100_000,
      parameter NUM_CYC  = FPGA_CLK / I2C_CLK,
      parameter CNT_SZ   = $clog2(NUM_CYC))
    (CLK, RST_n, I_SCL, I_RS_IO_SCL, I_FL_IO_SCL,
     O_MDL_LW_IO_SCL, O_MDL_HG_IO_SCL);




    input wire CLK;
    input wire RST_n;
    input wire I_SCL;
    input wire I_RS_IO_SCL;
    input wire I_FL_IO_SCL;

    output reg O_MDL_LW_IO_SCL;
    output reg O_MDL_HG_IO_SCL;

    reg [CNT_SZ-1:0] cnt;
    reg [CNT_SZ-1:0] sv_cnt;
    wire             en_str;


    assign en_str = cnt == (sv_cnt >> 1'b1) & (cnt > 1'b0);


    always @(posedge CLK or negedge RST_n) begin
        if (!RST_n)
            begin
                cnt <= {CNT_SZ{1'b0}};
                sv_cnt <= {CNT_SZ{1'b0}};
                O_MDL_LW_IO_SCL <= 1'b0;
                O_MDL_HG_IO_SCL <= 1'b0;
            end
        else
            begin
                cnt <= I_FL_IO_SCL || I_RS_IO_SCL ? {CNT_SZ{1'b0}} : cnt + 1'b1;
                sv_cnt <= I_FL_IO_SCL ? cnt : sv_cnt;
                O_MDL_LW_IO_SCL <= !I_SCL & en_str ? 1'b1 : 1'b0;
                O_MDL_HG_IO_SCL <= I_SCL & en_str ? 1'b1 : 1'b0;
            end
    end


endmodule