data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v
1: b'%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:3: Cannot find include file: ddr4_user_parameter.vh\n    `include "ddr4_user_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/ddr4_user_parameter.vh\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/ddr4_user_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/ddr4_user_parameter.vh.sv\n             ddr4_user_parameter.vh\n             ddr4_user_parameter.vh.v\n             ddr4_user_parameter.vh.sv\n             obj_dir/ddr4_user_parameter.vh\n             obj_dir/ddr4_user_parameter.vh.v\n             obj_dir/ddr4_user_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:4: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          config_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire   [DDR4_STATUS_SIZE-1:0] ddr4_status_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          ddr4_init_calib_complete_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_regfile.v:43: syntax error, unexpected always\n    always @(posedge clk_i or negedge reset_n_i) begin\n    ^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module ddr4_regfile #(
    `include "ddr4_user_parameter.vh"
    ,`include "tcu_parameter.vh"
)
(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                          config_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    input  wire   [DDR4_STATUS_SIZE-1:0] ddr4_status_i,
    input  wire                          ddr4_init_calib_complete_i
);



    localparam REG_DDR4_STATUS              = 32'h00000000;
    localparam REG_DDR4_INIT_CALIB_COMPLETE = 32'h00000008;




    reg   [DDR4_STATUS_SIZE-1:0] r_ddr4_status;
    reg                          r_ddr4_init_calib_complete;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_ddr4_status <= {DDR4_STATUS_SIZE{1'b0}};
            r_ddr4_init_calib_complete <= 1'b0;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_ddr4_status <= ddr4_status_i;
            r_ddr4_init_calib_complete <= ddr4_init_calib_complete_i;

            r_config_rdata <= rin_config_rdata;
        end
    end


    

    always @* begin
        rin_config_rdata = 64'h0;
        








        if (reg_r_en) begin
            case (config_addr_i)
                REG_DDR4_STATUS: begin
                    rin_config_rdata = r_ddr4_status;
                end

                REG_DDR4_INIT_CALIB_COMPLETE: begin
                    rin_config_rdata = r_ddr4_init_calib_complete;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;


endmodule
module ddr4_regfile #(
    `include "ddr4_user_parameter.vh"
    ,`include "tcu_parameter.vh"
)
(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                          config_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    input  wire   [DDR4_STATUS_SIZE-1:0] ddr4_status_i,
    input  wire                          ddr4_init_calib_complete_i
);




    localparam REG_DDR4_STATUS              = 32'h00000000;
    localparam REG_DDR4_INIT_CALIB_COMPLETE = 32'h00000008;




    reg   [DDR4_STATUS_SIZE-1:0] r_ddr4_status;
    reg                          r_ddr4_init_calib_complete;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_ddr4_status <= {DDR4_STATUS_SIZE{1'b0}};
            r_ddr4_init_calib_complete <= 1'b0;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_ddr4_status <= ddr4_status_i;
            r_ddr4_init_calib_complete <= ddr4_init_calib_complete_i;

            r_config_rdata <= rin_config_rdata;
        end
    end


    

    always @* begin
        rin_config_rdata = 64'h0;
        








        if (reg_r_en) begin
            case (config_addr_i)
                REG_DDR4_STATUS: begin
                    rin_config_rdata = r_ddr4_status;
                end

                REG_DDR4_INIT_CALIB_COMPLETE: begin
                    rin_config_rdata = r_ddr4_init_calib_complete;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;


endmodule