data/full_repos/permissive/502544928/regFile.v
data/verilator_xmls/b2f73e3c-eaba-49dc-8db2-06af1c942fcd.xml
module regFile #(parameter REG_DATA_WIDTH = 32, REG_SEL_BITS = 5) (
				clock, reset, read_sel1, read_sel2,
				wEn, write_sel, write_data, 
				read_data1, read_data2
);

input clock, reset, wEn; 
input [REG_DATA_WIDTH-1:0] write_data;
input [REG_SEL_BITS-1:0] read_sel1, read_sel2, write_sel;
output[REG_DATA_WIDTH-1:0] read_data1; 
output[REG_DATA_WIDTH-1:0] read_data2; 

(* ram_style = "distributed" *) 
reg   [REG_DATA_WIDTH-1:0] register_file[0:(1<<REG_SEL_BITS)-1];
integer i; 

always @(posedge clock)
	if(reset==1)
		register_file[0] <= 0; 
	else 
	    if (wEn & write_sel != 0) register_file[write_sel] <= write_data;
	      



assign  read_data1 = register_file[read_sel1];
assign  read_data2 = register_file[read_sel2];

endmodule
module regFile #(parameter REG_DATA_WIDTH = 32, REG_SEL_BITS = 5) (
				clock, reset, read_sel1, read_sel2,
				wEn, write_sel, write_data, 
				read_data1, read_data2
);


input clock, reset, wEn; 
input [REG_DATA_WIDTH-1:0] write_data;
input [REG_SEL_BITS-1:0] read_sel1, read_sel2, write_sel;
output[REG_DATA_WIDTH-1:0] read_data1; 
output[REG_DATA_WIDTH-1:0] read_data2; 

(* ram_style = "distributed" *) 
reg   [REG_DATA_WIDTH-1:0] register_file[0:(1<<REG_SEL_BITS)-1];
integer i; 

always @(posedge clock)
	if(reset==1)
		register_file[0] <= 0; 
	else 
	    if (wEn & write_sel != 0) register_file[write_sel] <= write_data;
	      



assign  read_data1 = register_file[read_sel1];
assign  read_data2 = register_file[read_sel2];

endmodule