data/full_repos/permissive/418897317/verilog/rtl/ip_eth_rx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418897317/verilog/rtl/ip_eth_rx.v:226: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                : ... In instance ip_eth_rx\n        add1c16b = t[15:0] + t[16];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/418897317/verilog/rtl/ip_eth_rx.v:280: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                : ... In instance ip_eth_rx\n            hdr_ptr_next = 16\'d0;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
function [15:0] add1c16b;
    input [15:0] a, b;
    reg [16:0] t;
    begin
        t = a+b;
        add1c16b = t[15:0] + t[16];
    end
endfunction
function [15:0] add1c16b;

    input [15:0] a, b;
    reg [16:0] t;
    begin
        t = a+b;
        add1c16b = t[15:0] + t[16];
    end
endfunction