data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/polmul_optimized/s_mul.v
data/verilator_xmls/fbb50efb-4693-4aae-9240-07364139a478.xml
module small_alu1(Ri, s, a, result);
input [12:0] Ri, a;
input [3:0] s;
output [12:0] result;









wire [12:0] ax3 = a + {a[11:0], 1'b0};

wire [12:0] ax5 = a + {a[10:0], 2'b0};












wire [12:0] a_mul_s = s[2:0] == 3'd0 ? 13'd0
					: s[2:0] == 3'd1 ? a
					: s[2:0] == 3'd2 ? {a[11:0],1'b0}
					: s[2:0] == 3'd3 ? ax3
					: s[2:0] == 3'd4 ? {a[10:0], 2'b0}
					: ax5;











					
					
wire [12:0] result = s[3] ? Ri - a_mul_s : Ri + a_mul_s;






endmodule
module small_alu1(Ri, s, a, result);

input [12:0] Ri, a;
input [3:0] s;
output [12:0] result;









wire [12:0] ax3 = a + {a[11:0], 1'b0};

wire [12:0] ax5 = a + {a[10:0], 2'b0};












wire [12:0] a_mul_s = s[2:0] == 3'd0 ? 13'd0
					: s[2:0] == 3'd1 ? a
					: s[2:0] == 3'd2 ? {a[11:0],1'b0}
					: s[2:0] == 3'd3 ? ax3
					: s[2:0] == 3'd4 ? {a[10:0], 2'b0}
					: ax5;











					
					
wire [12:0] result = s[3] ? Ri - a_mul_s : Ri + a_mul_s;






endmodule