data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module ALU #(parameter data_width = 32, ctrlLen = 4)(
    input [data_width-1:0] in1,
    input [data_width-1:0] in2,
    input [ctrlLen-1:0] ALUctrl,
    output reg [data_width-1:0] ALUResult,
    output wire zero
);
    assign zero = (ALUResult == 0)? 1:0;
    always @(in1, in2, ALUctrl) begin
        case(ALUctrl)
            4'h0: ALUResult = in1 & in2;
            4'h1: ALUResult = in1 | in2;
            4'h2: ALUResult = in1 + in2;
            4'h3: ALUResult = in1 - in2;
            4'h4: ALUResult = (in1 == in2);
            4'h5: ALUResult = in1 << in2;
            4'h6: ALUResult = in1 >> in2;
            4'h7: ALUResult = ($signed(in1)) >>> in2;
            4'h8: ALUResult = ($signed(in1) < $signed(in2))? 0:1;
            4'h9: ALUResult = ($signed(in1) < $signed(in2))? 1:0;
            default: ALUResult = 0;                
        endcase
    end
endmodule
module ALU #(parameter data_width = 32, ctrlLen = 4)(
    input [data_width-1:0] in1,
    input [data_width-1:0] in2,
    input [ctrlLen-1:0] ALUctrl,
    output reg [data_width-1:0] ALUResult,
    output wire zero
);

    assign zero = (ALUResult == 0)? 1:0;
    always @(in1, in2, ALUctrl) begin
        case(ALUctrl)
            4'h0: ALUResult = in1 & in2;
            4'h1: ALUResult = in1 | in2;
            4'h2: ALUResult = in1 + in2;
            4'h3: ALUResult = in1 - in2;
            4'h4: ALUResult = (in1 == in2);
            4'h5: ALUResult = in1 << in2;
            4'h6: ALUResult = in1 >> in2;
            4'h7: ALUResult = ($signed(in1)) >>> in2;
            4'h8: ALUResult = ($signed(in1) < $signed(in2))? 0:1;
            4'h9: ALUResult = ($signed(in1) < $signed(in2))? 1:0;
            default: ALUResult = 0;                
        endcase
    end
endmodule