data/full_repos/permissive/449370139/verilog_code/uart_reciever.v
data/verilator_xmls/6630ddd7-0664-4e86-a0cd-36641df9e0f7.xml
module uart_receiver(
    input clk,
    input clrn,
    input [3:0] cnt,
    input rdn,
    input rxd,
    output reg r_ready,
    output [7:0] d_out,
    output reg parity_error=1'b1,
    output reg frame_error
);


parameter bits=4'b1010;

reg [3:0] sampling_place;
reg [3:0] no_bits;
reg [9:0] r_buffer;
reg clkr;
reg rxd_old,rxd_new;
reg sampling;
reg [7:0] frame;




always @ (posedge clk or negedge clrn)
begin
    if(clrn == 0) begin
        rxd_old <= 1'b1;
        rxd_new <= 1'b1;
    end
    else begin
        rxd_old <= rxd_new;
        rxd_new <= rxd;
    end
end




always @(posedge clk or negedge clrn)
begin
    if(clrn==0)begin
        sampling <= 1'b0;
    end
    else begin
        if(rxd_old && !rxd_new) begin
            if(!sampling)
                sampling_place<= cnt+4'b1000;
            sampling <= 1'b1;
        end
        else begin
            if(no_bits == bits)
                sampling <= 1'b0; 
        end
    end
end




always @ (posedge clk or negedge clrn)
begin
    if(clrn == 0) begin
        clkr<=1'b0;
    end else
    begin
        if(sampling) begin
            if(cnt == sampling_place)
                clkr<=1'b1;
            if(cnt == sampling_place+4'b0001)
                clkr<=1'b0;
        end else
            clkr<= 1'b0;
    end  
end




always@(posedge clkr or negedge sampling)
begin
    if(!sampling) begin
        no_bits<=4'b0000;
    end
    else begin
        no_bits<=no_bits + 4'b0001;
        r_buffer[no_bits]<= rxd;
    end
end




always @(posedge clk or negedge clrn or negedge rdn)
begin
    if(clrn==0) begin
        r_ready <= 1'b0;
        frame_error <=1'b0;
    end
    else begin
        if(!rdn) begin
            r_ready <= 1'b0;
            frame_error <= 1'b0;
        end
        else begin
            if(no_bits == bits) begin
            frame <= r_buffer[8:1];
            r_ready <= 1'b1;
            if(!r_buffer[9]) begin
                frame_error<=1'b1;
            end
            end
        end   
    end
end

assign d_out =!rdn ? frame :8'bz;

endmodule
module uart_receiver(
    input clk,
    input clrn,
    input [3:0] cnt,
    input rdn,
    input rxd,
    output reg r_ready,
    output [7:0] d_out,
    output reg parity_error=1'b1,
    output reg frame_error
);



parameter bits=4'b1010;

reg [3:0] sampling_place;
reg [3:0] no_bits;
reg [9:0] r_buffer;
reg clkr;
reg rxd_old,rxd_new;
reg sampling;
reg [7:0] frame;




always @ (posedge clk or negedge clrn)
begin
    if(clrn == 0) begin
        rxd_old <= 1'b1;
        rxd_new <= 1'b1;
    end
    else begin
        rxd_old <= rxd_new;
        rxd_new <= rxd;
    end
end




always @(posedge clk or negedge clrn)
begin
    if(clrn==0)begin
        sampling <= 1'b0;
    end
    else begin
        if(rxd_old && !rxd_new) begin
            if(!sampling)
                sampling_place<= cnt+4'b1000;
            sampling <= 1'b1;
        end
        else begin
            if(no_bits == bits)
                sampling <= 1'b0; 
        end
    end
end




always @ (posedge clk or negedge clrn)
begin
    if(clrn == 0) begin
        clkr<=1'b0;
    end else
    begin
        if(sampling) begin
            if(cnt == sampling_place)
                clkr<=1'b1;
            if(cnt == sampling_place+4'b0001)
                clkr<=1'b0;
        end else
            clkr<= 1'b0;
    end  
end




always@(posedge clkr or negedge sampling)
begin
    if(!sampling) begin
        no_bits<=4'b0000;
    end
    else begin
        no_bits<=no_bits + 4'b0001;
        r_buffer[no_bits]<= rxd;
    end
end




always @(posedge clk or negedge clrn or negedge rdn)
begin
    if(clrn==0) begin
        r_ready <= 1'b0;
        frame_error <=1'b0;
    end
    else begin
        if(!rdn) begin
            r_ready <= 1'b0;
            frame_error <= 1'b0;
        end
        else begin
            if(no_bits == bits) begin
            frame <= r_buffer[8:1];
            r_ready <= 1'b1;
            if(!r_buffer[9]) begin
                frame_error<=1'b1;
            end
            end
        end   
    end
end

assign d_out =!rdn ? frame :8'bz;

endmodule