data/full_repos/permissive/513398397/verilog/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/513398397/verilog/ALU.v:11: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                     : ... In instance ALU\nwire SLT_cond = (ALUSel == 3\'b010);\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/513398397/verilog/ALU.v:13: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                     : ... In instance ALU\nassign ADD = A + B_compliment + ALUSel[3];\n                              ^\n%Error: data/full_repos/permissive/513398397/verilog/ALU.v:22: Cannot find file containing module: \'COMP32b\'\nCOMP32b COMPARE(SLT, A, B, ALUSel[0]);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.v\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.sv\n             COMP32b\n             COMP32b.v\n             COMP32b.sv\n             obj_dir/COMP32b\n             obj_dir/COMP32b.v\n             obj_dir/COMP32b.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module mux8to1(
    output [31:0] mux_o,
    input  [31:0] mux0, mux1, mux2, mux3, mux4, mux5, mux6, mux7,
    input  [2:0] sel
);

wire [31:0] b0, b1, b2, b3;
wire [31:0] c0, c1;

assign b0 = sel[0] ? mux1 : mux0;
assign b1 = sel[0] ? mux3 : mux2;
assign b2 = sel[0] ? mux5 : mux4;
assign b3 = sel[0] ? mux7 : mux6;

assign c0 = sel[1] ? b1 : b0;
assign c1 = sel[1] ? b3 : b2;

assign mux_o = sel[2] ? c1 : c0;

endmodule
module mux8to1(
    output [31:0] mux_o,
    input  [31:0] mux0, mux1, mux2, mux3, mux4, mux5, mux6, mux7,
    input  [2:0] sel
);


wire [31:0] b0, b1, b2, b3;
wire [31:0] c0, c1;

assign b0 = sel[0] ? mux1 : mux0;
assign b1 = sel[0] ? mux3 : mux2;
assign b2 = sel[0] ? mux5 : mux4;
assign b3 = sel[0] ? mux7 : mux6;

assign c0 = sel[1] ? b1 : b0;
assign c1 = sel[1] ? b3 : b2;

assign mux_o = sel[2] ? c1 : c0;

endmodule