data/full_repos/permissive/426889244/verilog/FullAdder.v
data/verilator_xmls/c0201bb4-2f9d-452c-945b-d85c309c502d.xml
module FullAdder (
    input wire in1,
    input wire in2,
    input wire in3,

    output wire out,
    output wire carry
);
    assign out = ~in1 & ~in2 & in3 | ~in1 & in2 & ~in3 | in1 & ~in2 & ~in3 | in1 & in2 & in3;
    assign carry = in2 & in3 | in1 & in3 | in1 & in2;
endmodule
module FullAdder (
    input wire in1,
    input wire in2,
    input wire in3,

    output wire out,
    output wire carry
);

    assign out = ~in1 & ~in2 & in3 | ~in1 & in2 & ~in3 | in1 & ~in2 & ~in3 | in1 & in2 & in3;
    assign carry = in2 & in3 | in1 & in3 | in1 & in2;
endmodule