data/full_repos/permissive/496030466/Verilog/source/Bus_Reg_X1.v
data/verilator_xmls/6a8cd026-2ca4-4f39-ad80-869ad11d0d02.xml
module Bus_Reg_X1 #(parameter INIT_00  = 0)
 (input             i_Bus_Rst_L,
  input             i_Bus_Clk,
  input             i_Bus_CS,
  input             i_Bus_Wr_Rd_n,
  input [15:0]      i_Bus_Wr_Data,
  output reg [15:0] o_Bus_Rd_Data,
  output reg        o_Bus_Rd_DV,
  input [15:0]      i_Reg_00,
  output reg [15:0] o_Reg_00);

  always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L)
  begin
    if (~i_Bus_Rst_L)
    begin
      o_Bus_Rd_DV <= 1'b0;
      o_Reg_00   <= INIT_00;
    end
    else
    begin
      o_Bus_Rd_DV <= 1'b0;

      if (i_Bus_CS == 1'b1)
      begin
        if (i_Bus_Wr_Rd_n == 1'b1)
          o_Reg_00 <= i_Bus_Wr_Data;
        else
        begin
          o_Bus_Rd_DV   <= 1'b1;
          o_Bus_Rd_Data <= i_Reg_00;
        end
      end
    end
  end

endmodule
module Bus_Reg_X1 #(parameter INIT_00  = 0)
 (input             i_Bus_Rst_L,
  input             i_Bus_Clk,
  input             i_Bus_CS,
  input             i_Bus_Wr_Rd_n,
  input [15:0]      i_Bus_Wr_Data,
  output reg [15:0] o_Bus_Rd_Data,
  output reg        o_Bus_Rd_DV,
  input [15:0]      i_Reg_00,
  output reg [15:0] o_Reg_00);


  always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L)
  begin
    if (~i_Bus_Rst_L)
    begin
      o_Bus_Rd_DV <= 1'b0;
      o_Reg_00   <= INIT_00;
    end
    else
    begin
      o_Bus_Rd_DV <= 1'b0;

      if (i_Bus_CS == 1'b1)
      begin
        if (i_Bus_Wr_Rd_n == 1'b1)
          o_Reg_00 <= i_Bus_Wr_Data;
        else
        begin
          o_Bus_Rd_DV   <= 1'b1;
          o_Bus_Rd_Data <= i_Reg_00;
        end
      end
    end
  end

endmodule