data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_par32.v
data/verilator_xmls/a9610ea8-f586-4690-b17b-94330c702e68.xml
module sparc_ifu_par32 (

   out, 

   in
   );

   input [31:0] in;
   output 	out;

   assign  out = (^in[31:0]);

endmodule
module sparc_ifu_par32 (

   out, 

   in
   );


   input [31:0] in;
   output 	out;

   assign  out = (^in[31:0]);

endmodule