data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #200\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #11000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #200\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #8000\n        ^\n%Error: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:55: Cannot find file containing module: \'SPI_sender\'\n        SPI_sender spi_master (\n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_sender\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_sender.v\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_sender.sv\n             SPI_sender\n             SPI_sender.v\n             SPI_sender.sv\n             obj_dir/SPI_sender\n             obj_dir/SPI_sender.v\n             obj_dir/SPI_sender.sv\n%Error: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi_testbench.v:66: Cannot find file containing module: \'SPI_SLAVE\'\n    SPI_SLAVE #(.m(m)) spi_slave \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_testbench();
    parameter integer m = 16;
    reg GCLK;
    reg st;
    reg LEFT;
    reg RST;
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 16'hdeaf;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 16'b110101100110110;
    
    wire clk_Tbit;

        SPI_sender spi_master (
            .CLK(GCLK),
            .DATA(MASTER_TX),
            .T_DIV(2),
            .RST(RST),
            .ST(st),
            .SCK(SCLK),
            .MOSI(MOSI),
            .SS(SS)
            );
    
    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .RST(RST),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .SS(SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );

    
    always begin
        GCLK = 1'b0;
        #10;
        GCLK = 1'b1;
        #10;
    end
    
    initial begin
        GCLK = 1'b0;
        st = 1'b0;
        LEFT = 1'b1;
        RST = 1'b0;
        #100
        st = 1'b1;
        #200
        st = 1'b0;
        #11000
        MASTER_TX = 16'habcd;
        st = 1'b1;
        #200
        st = 1'b0;
        #8000
        $finish;
    end
endmodule
module SPI_testbench();

    parameter integer m = 16;
    reg GCLK;
    reg st;
    reg LEFT;
    reg RST;
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 16'hdeaf;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 16'b110101100110110;
    
    wire clk_Tbit;

        SPI_sender spi_master (
            .CLK(GCLK),
            .DATA(MASTER_TX),
            .T_DIV(2),
            .RST(RST),
            .ST(st),
            .SCK(SCLK),
            .MOSI(MOSI),
            .SS(SS)
            );
    
    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .RST(RST),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .SS(SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );

    
    always begin
        GCLK = 1'b0;
        #10;
        GCLK = 1'b1;
        #10;
    end
    
    initial begin
        GCLK = 1'b0;
        st = 1'b0;
        LEFT = 1'b1;
        RST = 1'b0;
        #100
        st = 1'b1;
        #200
        st = 1'b0;
        #11000
        MASTER_TX = 16'habcd;
        st = 1'b1;
        #200
        st = 1'b0;
        #8000
        $finish;
    end
endmodule