data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:16: Multiple top level modules\n                                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                      : ... Top module \'f1_test\'\nmodule f1_test(in1, in2, out);\n       ^~~~~~~\n                                                                                                      : ... Top module \'f2_test\'\nmodule f2_test(clk, cond, data);\n       ^~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:38: Cannot find file containing module: \'AND2\'\nAND2 synth_AND(.in({synth_net_0, synth_net_1}), .\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/tests/hana,data/full_repos/permissive/441359809/AND2\n             data/full_repos/permissive/441359809/src/yosys/tests/hana,data/full_repos/permissive/441359809/AND2.v\n             data/full_repos/permissive/441359809/src/yosys/tests/hana,data/full_repos/permissive/441359809/AND2.sv\n             AND2\n             AND2.v\n             AND2.sv\n             obj_dir/AND2\n             obj_dir/AND2.v\n             obj_dir/AND2.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:40: Cannot find file containing module: \'AND2\'\nAND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(\n^~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:42: Cannot find file containing module: \'AND2\'\nAND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(\n^~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:44: Cannot find file containing module: \'AND2\'\nAND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(\n^~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:46: Cannot find file containing module: \'BUF\'\nBUF synth_BUF(.in(synth_net), .out(synth_net_0));\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:47: Cannot find file containing module: \'BUF\'\nBUF \n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:49: Cannot find file containing module: \'BUF\'\nBUF synth_BUF_1(.in(synth_net_8)\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:51: Cannot find file containing module: \'BUF\'\nBUF synth_BUF_2(.in(tmp), .out(synth_net_9));\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:52: Cannot find file containing module: \'MUX2\'\nMUX2 synth_MUX(.\n^~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:54: Cannot find file containing module: \'MUX2\'\nMUX2 \n^~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:57: Cannot find file containing module: \'FF\'\nFF synth_FF(.d(synth_net_11), .clk(clk), .q(data));\n^~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:58: Cannot find file containing module: \'VCC\'\nVCC synth_VCC(.out(\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:60: Cannot find file containing module: \'VCC\'\nVCC synth_VCC_0(.out(synth_net_1));\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:61: Cannot find file containing module: \'VCC\'\nVCC synth_VCC_1(.out(\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:63: Cannot find file containing module: \'VCC\'\nVCC synth_VCC_2(.out(synth_net_10));\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:9: Cannot find file containing module: \'BUF\'\nBUF synth_BUF_0(.in(synth_net_1), .out(out\n^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_vlib.v:11: Cannot find file containing module: \'DIV1\'\nDIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1\n^~~~\n%Error: Exiting due to 17 error(s), 1 warning(s)\n'
module f1_test(in1, in2, out);
input in1;
input in2;
output out;

wire  synth_net_0;
wire  synth_net_1;
BUF synth_BUF_0(.in(synth_net_1), .out(out
    ));
DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
    ));
endmodule
module f1_test(in1, in2, out);

input in1;
input in2;
output out;

wire  synth_net_0;
wire  synth_net_1;
BUF synth_BUF_0(.in(synth_net_1), .out(out
    ));
DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
    ));
endmodule