data/full_repos/permissive/515599642/Simple CPU module using Verilog/top.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/top.v\n%Error: Exiting due to 6 error(s)\n'
module top(A, B, ctrl_bus, clk, Q);

input [3:0] A;
input [3:0] B;
input [7:0] ctrl_bus;
input clk;
output [3:0] Q;


wire [3:0] w0,w1,w2,w3,w4;


MUX M1(B, w0, ctrl_bus[3], w1);
ALU A1(A, w1, ctrl_bus[2:0], w2);
Shift_Reg S1(w2, ctrl_bus[5:4], w3);
Q_Reg Q1(w3, clk, ctrl_bus[6], Q);
R_Reg R1(w2, clk, ctrl_bus[7], w0);


endmodule
module top(A, B, ctrl_bus, clk, Q);


input [3:0] A;
input [3:0] B;
input [7:0] ctrl_bus;
input clk;
output [3:0] Q;


wire [3:0] w0,w1,w2,w3,w4;


MUX M1(B, w0, ctrl_bus[3], w1);
ALU A1(A, w1, ctrl_bus[2:0], w2);
Shift_Reg S1(w2, ctrl_bus[5:4], w3);
Q_Reg Q1(w3, clk, ctrl_bus[6], Q);
R_Reg R1(w2, clk, ctrl_bus[7], w0);


endmodule