data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:572: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.sv\n             AsyncRegInit\n             AsyncRegInit.v\n             AsyncRegInit.sv\n             obj_dir/AsyncRegInit\n             obj_dir/AsyncRegInit.v\n             obj_dir/AsyncRegInit.sv\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:584: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:596: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:608: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:440: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:452: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:464: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:476: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:302: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:314: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:326: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:338: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:524: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:392: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:254: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module SEClkDivider_1(
    input clock,
    input reset,
    input io_reset,
    input io_inClk,
    output io_outClks_3,
    output io_outClks_1,
    output io_outClks_0
);
    wire _AsyncRegInit__out;
    wire _AsyncRegInit__in;
    wire _AsyncRegInit__init;
    wire _AsyncRegInit__reset;
    wire _AsyncRegInit__clk;
    AsyncRegInit AsyncRegInit (
        .out(_AsyncRegInit__out),
        .in(_AsyncRegInit__in),
        .init(_AsyncRegInit__init),
        .reset(_AsyncRegInit__reset),
        .clk(_AsyncRegInit__clk)
    );
    wire _AsyncRegInit_1__out;
    wire _AsyncRegInit_1__in;
    wire _AsyncRegInit_1__init;
    wire _AsyncRegInit_1__reset;
    wire _AsyncRegInit_1__clk;
    AsyncRegInit AsyncRegInit_1 (
        .out(_AsyncRegInit_1__out),
        .in(_AsyncRegInit_1__in),
        .init(_AsyncRegInit_1__init),
        .reset(_AsyncRegInit_1__reset),
        .clk(_AsyncRegInit_1__clk)
    );
    wire _AsyncRegInit_2__out;
    wire _AsyncRegInit_2__in;
    wire _AsyncRegInit_2__init;
    wire _AsyncRegInit_2__reset;
    wire _AsyncRegInit_2__clk;
    AsyncRegInit AsyncRegInit_2 (
        .out(_AsyncRegInit_2__out),
        .in(_AsyncRegInit_2__in),
        .init(_AsyncRegInit_2__init),
        .reset(_AsyncRegInit_2__reset),
        .clk(_AsyncRegInit_2__clk)
    );
    wire _AsyncRegInit_3__out;
    wire _AsyncRegInit_3__in;
    wire _AsyncRegInit_3__init;
    wire _AsyncRegInit_3__reset;
    wire _AsyncRegInit_3__clk;
    AsyncRegInit AsyncRegInit_3 (
        .out(_AsyncRegInit_3__out),
        .in(_AsyncRegInit_3__in),
        .init(_AsyncRegInit_3__init),
        .reset(_AsyncRegInit_3__reset),
        .clk(_AsyncRegInit_3__clk)
    );
    wire _T_22;
    assign _T_22 = _AsyncRegInit_1__out;
    wire _T_23;
    assign _T_23 = _AsyncRegInit_2__out;
    wire _T_24;
    assign _T_24 = _AsyncRegInit__out;
    assign _AsyncRegInit__clk = io_inClk;
    assign _AsyncRegInit__in = _AsyncRegInit_3__out;
    assign _AsyncRegInit__init = 1'h1;
    assign _AsyncRegInit__reset = io_reset;
    assign _AsyncRegInit_1__clk = io_inClk;
    assign _AsyncRegInit_1__in = _AsyncRegInit__out;
    assign _AsyncRegInit_1__init = 1'h0;
    assign _AsyncRegInit_1__reset = io_reset;
    assign _AsyncRegInit_2__clk = io_inClk;
    assign _AsyncRegInit_2__in = _AsyncRegInit_1__out;
    assign _AsyncRegInit_2__init = 1'h0;
    assign _AsyncRegInit_2__reset = io_reset;
    assign _AsyncRegInit_3__clk = io_inClk;
    assign _AsyncRegInit_3__in = _AsyncRegInit_2__out;
    assign _AsyncRegInit_3__init = 1'h0;
    assign _AsyncRegInit_3__reset = io_reset;
    assign io_outClks_0 = _T_22;
    assign io_outClks_1 = _T_23;
    assign io_outClks_3 = _T_24;
endmodule
module SEClkDivider_1(
    input clock,
    input reset,
    input io_reset,
    input io_inClk,
    output io_outClks_3,
    output io_outClks_1,
    output io_outClks_0
);

    wire _AsyncRegInit__out;
    wire _AsyncRegInit__in;
    wire _AsyncRegInit__init;
    wire _AsyncRegInit__reset;
    wire _AsyncRegInit__clk;
    AsyncRegInit AsyncRegInit (
        .out(_AsyncRegInit__out),
        .in(_AsyncRegInit__in),
        .init(_AsyncRegInit__init),
        .reset(_AsyncRegInit__reset),
        .clk(_AsyncRegInit__clk)
    );
    wire _AsyncRegInit_1__out;
    wire _AsyncRegInit_1__in;
    wire _AsyncRegInit_1__init;
    wire _AsyncRegInit_1__reset;
    wire _AsyncRegInit_1__clk;
    AsyncRegInit AsyncRegInit_1 (
        .out(_AsyncRegInit_1__out),
        .in(_AsyncRegInit_1__in),
        .init(_AsyncRegInit_1__init),
        .reset(_AsyncRegInit_1__reset),
        .clk(_AsyncRegInit_1__clk)
    );
    wire _AsyncRegInit_2__out;
    wire _AsyncRegInit_2__in;
    wire _AsyncRegInit_2__init;
    wire _AsyncRegInit_2__reset;
    wire _AsyncRegInit_2__clk;
    AsyncRegInit AsyncRegInit_2 (
        .out(_AsyncRegInit_2__out),
        .in(_AsyncRegInit_2__in),
        .init(_AsyncRegInit_2__init),
        .reset(_AsyncRegInit_2__reset),
        .clk(_AsyncRegInit_2__clk)
    );
    wire _AsyncRegInit_3__out;
    wire _AsyncRegInit_3__in;
    wire _AsyncRegInit_3__init;
    wire _AsyncRegInit_3__reset;
    wire _AsyncRegInit_3__clk;
    AsyncRegInit AsyncRegInit_3 (
        .out(_AsyncRegInit_3__out),
        .in(_AsyncRegInit_3__in),
        .init(_AsyncRegInit_3__init),
        .reset(_AsyncRegInit_3__reset),
        .clk(_AsyncRegInit_3__clk)
    );
    wire _T_22;
    assign _T_22 = _AsyncRegInit_1__out;
    wire _T_23;
    assign _T_23 = _AsyncRegInit_2__out;
    wire _T_24;
    assign _T_24 = _AsyncRegInit__out;
    assign _AsyncRegInit__clk = io_inClk;
    assign _AsyncRegInit__in = _AsyncRegInit_3__out;
    assign _AsyncRegInit__init = 1'h1;
    assign _AsyncRegInit__reset = io_reset;
    assign _AsyncRegInit_1__clk = io_inClk;
    assign _AsyncRegInit_1__in = _AsyncRegInit__out;
    assign _AsyncRegInit_1__init = 1'h0;
    assign _AsyncRegInit_1__reset = io_reset;
    assign _AsyncRegInit_2__clk = io_inClk;
    assign _AsyncRegInit_2__in = _AsyncRegInit_1__out;
    assign _AsyncRegInit_2__init = 1'h0;
    assign _AsyncRegInit_2__reset = io_reset;
    assign _AsyncRegInit_3__clk = io_inClk;
    assign _AsyncRegInit_3__in = _AsyncRegInit_2__out;
    assign _AsyncRegInit_3__init = 1'h0;
    assign _AsyncRegInit_3__reset = io_reset;
    assign io_outClks_0 = _T_22;
    assign io_outClks_1 = _T_23;
    assign io_outClks_3 = _T_24;
endmodule