data/full_repos/permissive/421450529/GRF.v
data/verilator_xmls/07f65d1b-f94b-4e0d-9777-5184afbf2d8c.xml
module GRF(
    input clk,
    input reset,
	 input[31:0] pc,
    input RegWrite_W,
    input[4:0] Read_register1,
	 input[4:0] Read_register2,
	 input[4:0] Write_register_W,
	 input[31:0] Write_data_W,
	 output[31:0] Read_data1,
	 output[31:0] Read_data2
    );
    
	 reg[31:0] register[31:0];
	 integer i;
	 initial begin
	   for(i=0;i<32;i=i+1)begin
				register[i]=0;
			end
	 end
		
	always@(posedge clk)begin
		if(reset)begin
			for(i=0;i<32;i=i+1)begin
				register[i]=0;
			end
		end
		else if(RegWrite_W&&Write_register_W!=0)begin
				register[Write_register_W]=Write_data_W;
				$display("%d@%h: $%d <= %h",$time,pc,Write_register_W,register[Write_register_W]);
		end
	end
	
	assign Read_data1=(Read_register1!=0)?register[Read_register1]:0;
	assign Read_data2=(Read_register2!=0)?register[Read_register2]:0;

endmodule
module GRF(
    input clk,
    input reset,
	 input[31:0] pc,
    input RegWrite_W,
    input[4:0] Read_register1,
	 input[4:0] Read_register2,
	 input[4:0] Write_register_W,
	 input[31:0] Write_data_W,
	 output[31:0] Read_data1,
	 output[31:0] Read_data2
    );

    
	 reg[31:0] register[31:0];
	 integer i;
	 initial begin
	   for(i=0;i<32;i=i+1)begin
				register[i]=0;
			end
	 end
		
	always@(posedge clk)begin
		if(reset)begin
			for(i=0;i<32;i=i+1)begin
				register[i]=0;
			end
		end
		else if(RegWrite_W&&Write_register_W!=0)begin
				register[Write_register_W]=Write_data_W;
				$display("%d@%h: $%d <= %h",$time,pc,Write_register_W,register[Write_register_W]);
		end
	end
	
	assign Read_data1=(Read_register1!=0)?register[Read_register1]:0;
	assign Read_data2=(Read_register2!=0)?register[Read_register2]:0;

endmodule