data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #100  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n     #100\n     ^\n%Error: data/full_repos/permissive/447417093/FullAdder/FullAdder_tb.v:5: Cannot find file containing module: \'FullAdder\'\n    FullAdder simulate_adder (\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447417093/FullAdder,data/full_repos/permissive/447417093/FullAdder\n             data/full_repos/permissive/447417093/FullAdder,data/full_repos/permissive/447417093/FullAdder.v\n             data/full_repos/permissive/447417093/FullAdder,data/full_repos/permissive/447417093/FullAdder.sv\n             FullAdder\n             FullAdder.v\n             FullAdder.sv\n             obj_dir/FullAdder\n             obj_dir/FullAdder.v\n             obj_dir/FullAdder.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FullAdder_tb();
    reg A, B, Cin;
    wire Sum, Cout;

    FullAdder simulate_adder (
        .A(A),
        .B(B),
        .Cin(Cin),
        .Sum(Sum), 
        .Cout(Cout)
    );

    initial
        begin
            $display($time, " <<Starting the Simulation >>");


            assign A = 0;
            assign  B = 0;
            assign Cin = 0;
            #100
	    assign A = 0;
            assign B = 0;
            assign Cin = 1;
            #100
	    assign A = 0;
            assign B = 1;
            assign Cin = 0;
            #100

            assign A = 0;
            assign B = 1;
            assign Cin = 1;
            #100

            assign A = 1;
            assign B = 0;
            assign Cin = 0;
            #100

            assign A = 1;
            assign B = 0;
            assign Cin = 1;
            #100

            assign A = 1;
            assign B = 1;
            assign Cin = 0;
            #100

            assign A = 1;
            assign B = 1;
            assign Cin = 1;
	    #100
	    $finish;
            $display($time, " << Simulation complete>>");
        end
endmodule
module FullAdder_tb();

    reg A, B, Cin;
    wire Sum, Cout;

    FullAdder simulate_adder (
        .A(A),
        .B(B),
        .Cin(Cin),
        .Sum(Sum), 
        .Cout(Cout)
    );

    initial
        begin
            $display($time, " <<Starting the Simulation >>");


            assign A = 0;
            assign  B = 0;
            assign Cin = 0;
            #100
	    assign A = 0;
            assign B = 0;
            assign Cin = 1;
            #100
	    assign A = 0;
            assign B = 1;
            assign Cin = 0;
            #100

            assign A = 0;
            assign B = 1;
            assign Cin = 1;
            #100

            assign A = 1;
            assign B = 0;
            assign Cin = 0;
            #100

            assign A = 1;
            assign B = 0;
            assign Cin = 1;
            #100

            assign A = 1;
            assign B = 1;
            assign Cin = 0;
            #100

            assign A = 1;
            assign B = 1;
            assign Cin = 1;
	    #100
	    $finish;
            $display($time, " << Simulation complete>>");
        end
endmodule