data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:113: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$23  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:114: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$25  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:115: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$27  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n%Error: Exiting due to 3 warning(s)\n'
module frame_clock_synchronizer(rst, clk, frame_start_in, frame_clock);
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
  output frame_clock;
  wire frame_clock;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:50" *)
  input frame_start_in;
  wire frame_start_in;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  reg stage0 = 1'h0;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  wire \stage0$next ;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  reg stage1 = 1'h0;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  wire \stage1$next ;
  always @(posedge clk)
    stage0 <= \stage0$next ;
  always @(posedge clk)
    stage1 <= \stage1$next ;
  assign frame_clock = stage1;
  assign \stage1$next  = stage0;
  assign \stage0$next  = frame_start_in;
endmodule
module frame_clock_synchronizer(rst, clk, frame_start_in, frame_clock);

  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
  output frame_clock;
  wire frame_clock;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:50" *)
  input frame_start_in;
  wire frame_start_in;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  reg stage0 = 1'h0;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  wire \stage0$next ;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  reg stage1 = 1'h0;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
  wire \stage1$next ;
  always @(posedge clk)
    stage0 <= \stage0$next ;
  always @(posedge clk)
    stage1 <= \stage1$next ;
  assign frame_clock = stage1;
  assign \stage1$next  = stage0;
  assign \stage0$next  = frame_start_in;
endmodule