data/full_repos/permissive/447976230/fpga/usrp2/control_lib/mux_32_4.v
data/verilator_xmls/62f03179-6f95-4c42-bbd4-c68064cdcef6.xml
module mux_32_4
  (input [1:0] sel,
   input [31:0] in0,
   input [31:0] in1,
   input [31:0] in2,
   input [31:0] in3,
   output [31:0] out);

   assign 	 out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0);

endmodule
module mux_32_4
  (input [1:0] sel,
   input [31:0] in0,
   input [31:0] in1,
   input [31:0] in2,
   input [31:0] in3,
   output [31:0] out);


   assign 	 out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0);

endmodule