data/full_repos/permissive/497870922/rtl/ubsoc_debug.v
1: b"%Error: data/full_repos/permissive/497870922/rtl/ubsoc_debug.v:93: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do  (spi_miso  ),\n   ^~\n%Error: data/full_repos/permissive/497870922/rtl/ubsoc_debug.v:93: syntax error, unexpected '(', expecting ')'\n  .do  (spi_miso  ),\n        ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ubsoc_debug (
	input clk_i,


	output suart_tx_o,
	input  suart_rx_i,


	output [7:0] gpio_led_o,
	input  [7:0] gpio_switch_i,
	input  [7:0] gpio_button_i,


	output  i2c_scl_mst_o,
	inout  i2c_sda_mst_io,


	input  i2c_scl_slv_i,
	inout  i2c_sda_slv_io












);




	wire spi_cpol_debug, spi_cpha_debug;
	wire spi_miso, spi_mosi, spi_sck;
	wire [7:0] spi_ss;

	ubsoc soc (
		.clk_i    	      (clk_i      	  ),

		.suart_tx_o       (suart_tx_o  	  ),
		.suart_rx_i       (suart_rx_i  	  ),
 
		.gpio_led_o 	  (gpio_led_o     ),
		.gpio_switch_i    (gpio_switch_i  ),
		.gpio_button_i    (gpio_button_i  ),

		.i2c_scl_io       (i2c_scl_mst_o  ),
		.i2c_sda_io       (i2c_sda_mst_io ),

		.spi_sck  		  (spi_sck		  ),
		.spi_ss	    	  (spi_ss[0]   	  ),
		.spi_mosi 		  (spi_mosi 	  ),
	    .spi_miso 		  (spi_miso 	  ),

	    .spi_cpol_debug   (spi_cpol_debug ),
	    .spi_cpha_debug   (spi_cpha_debug )
	);

	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clk_i) begin
		reset_cnt <= reset_cnt + !resetn;
	end

	spi_slave_model_2 spi_slave (
		.clock  (clk_i	   		),
		.csn 	(spi_ss[0]		),
		.sck 	(spi_sck 		),
		.di 	(spi_mosi		),
		.do 	(spi_miso		),

		.cpol_i (spi_cpol_debug ),
		.cpha_i (spi_cpha_debug )
	);

	i2cSlaveTop i2c_slave_full (
		.clk    (clk_i 			),
  		.rst    (!resetn 		),
  		.sda    (i2c_sda_slv_io	),
  		.scl    (i2c_scl_slv_i  ),
  		.myReg0 ()
	);


endmodule
module ubsoc_debug (
	input clk_i,


	output suart_tx_o,
	input  suart_rx_i,


	output [7:0] gpio_led_o,
	input  [7:0] gpio_switch_i,
	input  [7:0] gpio_button_i,


	output  i2c_scl_mst_o,
	inout  i2c_sda_mst_io,


	input  i2c_scl_slv_i,
	inout  i2c_sda_slv_io












);





	wire spi_cpol_debug, spi_cpha_debug;
	wire spi_miso, spi_mosi, spi_sck;
	wire [7:0] spi_ss;

	ubsoc soc (
		.clk_i    	      (clk_i      	  ),

		.suart_tx_o       (suart_tx_o  	  ),
		.suart_rx_i       (suart_rx_i  	  ),
 
		.gpio_led_o 	  (gpio_led_o     ),
		.gpio_switch_i    (gpio_switch_i  ),
		.gpio_button_i    (gpio_button_i  ),

		.i2c_scl_io       (i2c_scl_mst_o  ),
		.i2c_sda_io       (i2c_sda_mst_io ),

		.spi_sck  		  (spi_sck		  ),
		.spi_ss	    	  (spi_ss[0]   	  ),
		.spi_mosi 		  (spi_mosi 	  ),
	    .spi_miso 		  (spi_miso 	  ),

	    .spi_cpol_debug   (spi_cpol_debug ),
	    .spi_cpha_debug   (spi_cpha_debug )
	);

	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clk_i) begin
		reset_cnt <= reset_cnt + !resetn;
	end

	spi_slave_model_2 spi_slave (
		.clock  (clk_i	   		),
		.csn 	(spi_ss[0]		),
		.sck 	(spi_sck 		),
		.di 	(spi_mosi		),
		.do 	(spi_miso		),

		.cpol_i (spi_cpol_debug ),
		.cpha_i (spi_cpha_debug )
	);

	i2cSlaveTop i2c_slave_full (
		.clk    (clk_i 			),
  		.rst    (!resetn 		),
  		.sda    (i2c_sda_slv_io	),
  		.scl    (i2c_scl_slv_i  ),
  		.myReg0 ()
	);


endmodule