data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v
1: b'%Error: data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v:26: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v:27: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);  \n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v:29: Unsupported: Ignoring delay on this delayed statement.\n      D3 = 0; D2 = 0; D1 = 0; D0 = 1; #100;\n                                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v:30: Unsupported: Ignoring delay on this delayed statement.\n      D3 = 0; D2 = 0; D1 = 1; D0 = 0; #100;\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Encoder/fourByTwo/tf.v:31: Unsupported: Ignoring delay on this delayed statement.\n   D3 = 1; D2 = 0; D1 = 0; D0 = 0; #100;\n                                   ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module encodertt;


	reg D3;
	reg D2;
  	reg D1;
  	reg D0;


	wire A1;
  	wire A0;


	encoder uut (
      	.D0(D0),
      	.D1(D1),
      	.D2(D2),
      	.D3(D3),
      	.A1(A1), 
      	.A0(A0)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

      D3 = 0; D2 = 0; D1 = 0; D0 = 1; #100;
      D3 = 0; D2 = 0; D1 = 1; D0 = 0; #100;
	  D3 = 1; D2 = 0; D1 = 0; D0 = 0; #100;
	end
endmodule
module encodertt;



	reg D3;
	reg D2;
  	reg D1;
  	reg D0;


	wire A1;
  	wire A0;


	encoder uut (
      	.D0(D0),
      	.D1(D1),
      	.D2(D2),
      	.D3(D3),
      	.A1(A1), 
      	.A0(A0)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

      D3 = 0; D2 = 0; D1 = 0; D0 = 1; #100;
      D3 = 0; D2 = 0; D1 = 1; D0 = 0; #100;
	  D3 = 1; D2 = 0; D1 = 0; D0 = 0; #100;
	end
endmodule