data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh
1: b'%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:1: Unsupported: classes\nclass uart_seq_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_seq_item extends uvm_sequence_item;\n                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:4: syntax error, unexpected rand\n    rand bit sbe;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:5: syntax error, unexpected rand\n    rand int sbe_clks;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:6: syntax error, unexpected rand\n    rand logic[7:0] data;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:7: syntax error, unexpected rand\n    rand bit fe;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:8: syntax error, unexpected rand\n    rand logic [7:0] lcr;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:9: syntax error, unexpected rand\n    rand bit pe;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:10: syntax error, unexpected rand\n    rand logic [15:0] baud_divisor;\n    ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:12: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint BR_DIVEDE {baud_divisor == 16\'h02;}\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:12: syntax error, unexpected IDENTIFIER\n    constraint BR_DIVEDE {baud_divisor == 16\'h02;}\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint error_dists {fe dist {1 := 1, 0 := 99};\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n    constraint error_dists {fe dist {1 := 1, 0 := 99};\n                               ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:15: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n                            pe dist {1 := 1, 0 := 99};\n                               ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n                            sbe dist {1 := 1, 0 := 50};}\n                                ^~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint clks {delay inside {[0:20]};\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint lcr_setup {lcr == 8\'h3f;}\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:23: Define or directive not defined: \'`uvm_object_utils_begin\'\n    `uvm_object_utils_begin(uart_seq_item)\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:24: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(delay, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:25: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(sbe, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:26: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(sbe_clks, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:27: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(data, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:28: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(fe, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:29: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(lcr, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:30: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(pe, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:31: Define or directive not defined: \'`uvm_field_int\'\n        `uvm_field_int(baud_divisor, UVM_ALL_ON);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:32: Define or directive not defined: \'`uvm_object_utils_end\'\n    `uvm_object_utils_end\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:34: Unsupported: new constructor\n    function new (string name = "uart_seq_item",\n             ^~~\n%Error: data/full_repos/permissive/506636840/agents/uart_agent/uart_seq_item.svh:35: syntax error, unexpected IDENTIFIER, expecting \')\'\n        uvm_sequencer_base sequencer = null,\n                           ^~~~~~~~~\n%Error: Exiting due to 29 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function new (string name = "uart_seq_item",
        uvm_sequencer_base sequencer = null,
        uvm_sequence_base parent_sequence = null);

        super.new(name);
    endfunction
function new (string name = "uart_seq_item",
        uvm_sequencer_base sequencer = null,
        uvm_sequence_base parent_sequence = null);


        super.new(name);
    endfunction