data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/sign_extension/sign_extender.v
data/verilator_xmls/e3725f8e-6467-4752-b457-86f8aca7bcfd.xml
module sign_extender #(parameter N=32, parameter M = 12) (
	input  [M-1:0] in_i,
	output [N-1:0] out_o
);

	assign out_o = { {(N-M){in_i[M-1]}}, in_i[M-1:0]};

endmodule
module sign_extender #(parameter N=32, parameter M = 12) (
	input  [M-1:0] in_i,
	output [N-1:0] out_o
);


	assign out_o = { {(N-M){in_i[M-1]}}, in_i[M-1:0]};

endmodule