data/full_repos/permissive/421380819/verilog/rtl/ramInterface/ramArbiter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/421380819/verilog/rtl/ramInterface/ramArbiter.v:91: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                                             : ... In instance ramArbiter\n            RAM_ADDR_i = CTRL_ADDR1[7:2];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/421380819/verilog/rtl/ramInterface/ramArbiter.v:95: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                                             : ... In instance ramArbiter\n            RAM_ADDR_i = CTRL_ADDR2[7:2];\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module ramArbiter (

    input   wire            CLK,
    input   wire            RSTb,

    input   wire            CTRL_CSb1,
    input   wire            CTRL_WEb1,
    input   wire    [7:0]   CTRL_ADDR1,
    input   wire    [31:0]  CTRL_DATA_IN1,
    output  wire    [31:0]  CTRL_DATA_OUT1,

    input   wire            CTRL_CSb2,
    input   wire            CTRL_WEb2,
    input   wire    [7:0]   CTRL_ADDR2,
    input   wire    [31:0]  CTRL_DATA_IN2,
    output  wire    [31:0]  CTRL_DATA_OUT2,

    output   wire            RAM_CSb0,
    output   wire            RAM_WEb0,
    output   wire    [4:0]   RAM_ADDR0,
    output   wire    [7:0]   RAM_DATA_IN0,
    input    wire    [7:0]   RAM_DATA_OUT0,

    output   wire            RAM_CSb1,
    output   wire            RAM_WEb1,
    output   wire    [4:0]   RAM_ADDR1,
    output   wire    [7:0]   RAM_DATA_IN1,
    input    wire    [7:0]   RAM_DATA_OUT1,

    output   wire            RAM_CSb2,
    output   wire            RAM_WEb2,
    output   wire    [4:0]   RAM_ADDR2,
    output   wire    [7:0]   RAM_DATA_IN2,
    input    wire    [7:0]   RAM_DATA_OUT2,

    output   wire            RAM_CSb3,
    output   wire            RAM_WEb3,
    output   wire    [4:0]   RAM_ADDR3,
    output   wire    [7:0]   RAM_DATA_IN3,
    input    wire    [7:0]   RAM_DATA_OUT3
);

    reg         RAM_WEb_i;
    reg [4:0]   RAM_ADDR_i;
    reg [31:0]  RAM_DATA_IN_i;

    reg [31:0]  READ_DATA1_Q;
    reg [31:0]  READ_DATA1_D;
    reg [31:0]  READ_DATA2_Q;
    reg [31:0]  READ_DATA2_D;


    assign RAM_CSb0     = 1'b0;
    assign RAM_WEb0     = RAM_WEb_i;
    assign RAM_ADDR0    = RAM_ADDR_i;
    assign RAM_DATA_IN0 = RAM_DATA_IN_i[7:0];   
    assign RAM_CSb1     = 1'b0;
    assign RAM_WEb1     = RAM_WEb_i;
    assign RAM_ADDR1    = RAM_ADDR_i;
    assign RAM_DATA_IN1 = RAM_DATA_IN_i[15:8];   
    assign RAM_CSb2     = 1'b0;
    assign RAM_WEb2     = RAM_WEb_i;
    assign RAM_ADDR2    = RAM_ADDR_i;
    assign RAM_DATA_IN2 = RAM_DATA_IN_i[23:16];   
    assign RAM_CSb3     = 1'b0;
    assign RAM_WEb3     = RAM_WEb_i;
    assign RAM_ADDR3    = RAM_ADDR_i;
    assign RAM_DATA_IN3 = RAM_DATA_IN_i[31:24];


    always @(*) begin : if_read_access
        reg [31:0] vRamDataOut;

        READ_DATA1_D <= READ_DATA1_Q;
        READ_DATA2_D <= READ_DATA2_Q;

        vRamDataOut = {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0};

        if(CTRL_CSb1 == 1'b0) READ_DATA1_D <= vRamDataOut;
        else if(CTRL_CSb2 == 1'b0 ) READ_DATA2_D <= vRamDataOut;
    end
    assign CTRL_DATA_OUT1 = (CTRL_CSb1 == 1'b0) ? {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0} : READ_DATA1_Q;
    assign CTRL_DATA_OUT2 = (CTRL_CSb2 == 1'b0) ? {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0} : READ_DATA2_Q;


    always @(*) begin
        if(CTRL_CSb1 == 1'b0) begin
            RAM_WEb_i = CTRL_WEb1;
            RAM_ADDR_i = CTRL_ADDR1[7:2];
            RAM_DATA_IN_i = CTRL_DATA_IN1;
        end else begin
            RAM_WEb_i = CTRL_WEb2;
            RAM_ADDR_i = CTRL_ADDR2[7:2];
            RAM_DATA_IN_i = CTRL_DATA_IN2;
        end
    end
    

    always @(posedge CLK, negedge RSTb) begin
        if(RSTb == 1'b0) begin
            READ_DATA1_Q <= 32'h00_00_00_00;
            READ_DATA2_Q <= 32'h00_00_00_00;
        end else begin
            READ_DATA1_Q <= READ_DATA1_D;
            READ_DATA2_Q <= READ_DATA2_D;
        end
    end
endmodule
module ramArbiter (

    input   wire            CLK,
    input   wire            RSTb,

    input   wire            CTRL_CSb1,
    input   wire            CTRL_WEb1,
    input   wire    [7:0]   CTRL_ADDR1,
    input   wire    [31:0]  CTRL_DATA_IN1,
    output  wire    [31:0]  CTRL_DATA_OUT1,

    input   wire            CTRL_CSb2,
    input   wire            CTRL_WEb2,
    input   wire    [7:0]   CTRL_ADDR2,
    input   wire    [31:0]  CTRL_DATA_IN2,
    output  wire    [31:0]  CTRL_DATA_OUT2,

    output   wire            RAM_CSb0,
    output   wire            RAM_WEb0,
    output   wire    [4:0]   RAM_ADDR0,
    output   wire    [7:0]   RAM_DATA_IN0,
    input    wire    [7:0]   RAM_DATA_OUT0,

    output   wire            RAM_CSb1,
    output   wire            RAM_WEb1,
    output   wire    [4:0]   RAM_ADDR1,
    output   wire    [7:0]   RAM_DATA_IN1,
    input    wire    [7:0]   RAM_DATA_OUT1,

    output   wire            RAM_CSb2,
    output   wire            RAM_WEb2,
    output   wire    [4:0]   RAM_ADDR2,
    output   wire    [7:0]   RAM_DATA_IN2,
    input    wire    [7:0]   RAM_DATA_OUT2,

    output   wire            RAM_CSb3,
    output   wire            RAM_WEb3,
    output   wire    [4:0]   RAM_ADDR3,
    output   wire    [7:0]   RAM_DATA_IN3,
    input    wire    [7:0]   RAM_DATA_OUT3
);


    reg         RAM_WEb_i;
    reg [4:0]   RAM_ADDR_i;
    reg [31:0]  RAM_DATA_IN_i;

    reg [31:0]  READ_DATA1_Q;
    reg [31:0]  READ_DATA1_D;
    reg [31:0]  READ_DATA2_Q;
    reg [31:0]  READ_DATA2_D;


    assign RAM_CSb0     = 1'b0;
    assign RAM_WEb0     = RAM_WEb_i;
    assign RAM_ADDR0    = RAM_ADDR_i;
    assign RAM_DATA_IN0 = RAM_DATA_IN_i[7:0];   
    assign RAM_CSb1     = 1'b0;
    assign RAM_WEb1     = RAM_WEb_i;
    assign RAM_ADDR1    = RAM_ADDR_i;
    assign RAM_DATA_IN1 = RAM_DATA_IN_i[15:8];   
    assign RAM_CSb2     = 1'b0;
    assign RAM_WEb2     = RAM_WEb_i;
    assign RAM_ADDR2    = RAM_ADDR_i;
    assign RAM_DATA_IN2 = RAM_DATA_IN_i[23:16];   
    assign RAM_CSb3     = 1'b0;
    assign RAM_WEb3     = RAM_WEb_i;
    assign RAM_ADDR3    = RAM_ADDR_i;
    assign RAM_DATA_IN3 = RAM_DATA_IN_i[31:24];


    always @(*) begin : if_read_access
        reg [31:0] vRamDataOut;

        READ_DATA1_D <= READ_DATA1_Q;
        READ_DATA2_D <= READ_DATA2_Q;

        vRamDataOut = {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0};

        if(CTRL_CSb1 == 1'b0) READ_DATA1_D <= vRamDataOut;
        else if(CTRL_CSb2 == 1'b0 ) READ_DATA2_D <= vRamDataOut;
    end
    assign CTRL_DATA_OUT1 = (CTRL_CSb1 == 1'b0) ? {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0} : READ_DATA1_Q;
    assign CTRL_DATA_OUT2 = (CTRL_CSb2 == 1'b0) ? {RAM_DATA_OUT3, RAM_DATA_OUT2, RAM_DATA_OUT1, RAM_DATA_OUT0} : READ_DATA2_Q;


    always @(*) begin
        if(CTRL_CSb1 == 1'b0) begin
            RAM_WEb_i = CTRL_WEb1;
            RAM_ADDR_i = CTRL_ADDR1[7:2];
            RAM_DATA_IN_i = CTRL_DATA_IN1;
        end else begin
            RAM_WEb_i = CTRL_WEb2;
            RAM_ADDR_i = CTRL_ADDR2[7:2];
            RAM_DATA_IN_i = CTRL_DATA_IN2;
        end
    end
    

    always @(posedge CLK, negedge RSTb) begin
        if(RSTb == 1'b0) begin
            READ_DATA1_Q <= 32'h00_00_00_00;
            READ_DATA2_Q <= 32'h00_00_00_00;
        end else begin
            READ_DATA1_Q <= READ_DATA1_D;
            READ_DATA2_Q <= READ_DATA2_D;
        end
    end
endmodule