data/full_repos/permissive/522064891/efinity/rom.v
1: b"%Error: data/full_repos/permissive/522064891/efinity/rom.v:16: Cannot find file containing module: 'single_port_rom'\nsingle_port_rom #(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/single_port_rom\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/single_port_rom.v\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/single_port_rom.sv\n             single_port_rom\n             single_port_rom.v\n             single_port_rom.sv\n             obj_dir/single_port_rom\n             obj_dir/single_port_rom.v\n             obj_dir/single_port_rom.sv\n%Error: Exiting due to 1 error(s)\n"
module rom
(
    input        clock,
    input [10:0] address,
    input        select,
    output [7:0] data
);

wire [7:0] romData;

single_port_rom #(
    .DATA_WIDTH(8),
    .ADDR_WIDTH(11),
    .OUTPUT_REG("FALSE"),
    .RAM_INIT_FILE("../src/test.inithex")
) inst_singlePortRom (
    .addr(address),
    .data(romData),
    .clk(clock)
);

assign data = select ? romData : 8'hFF;

endmodule
module rom
(
    input        clock,
    input [10:0] address,
    input        select,
    output [7:0] data
);


wire [7:0] romData;

single_port_rom #(
    .DATA_WIDTH(8),
    .ADDR_WIDTH(11),
    .OUTPUT_REG("FALSE"),
    .RAM_INIT_FILE("../src/test.inithex")
) inst_singlePortRom (
    .addr(address),
    .data(romData),
    .clk(clock)
);

assign data = select ? romData : 8'hFF;

endmodule