data/full_repos/permissive/482168662/lab02_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:56: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt <= 25\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:58: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt <= 25\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:57: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:66: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:73: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt_10Hz <= 22\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:75: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt_10Hz <= 22\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:74: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:83: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Error: Exiting due to 8 warning(s)\n'
module counter(
    input clk,
    input clk_1Hz,
    input clk_10Hz,
    input key_sw0,
    input key_sw3_n,
    output [7:0] led
);
    parameter MAX_model_0 = 8'd127;
    parameter MAX_model_1 = 4'd9;

    reg [7:0] led_reg;
    reg [3:0] high,low;
    reg change_flag;


    always @(posedge clk_1Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            led_reg <= 8'd0;
        else if((change_flag==1'b0) && (led_reg==MAX_model_0))
            led_reg <= 8'd0;
        else if(change_flag==1'b0)
            led_reg <= led_reg + 8'd1;
    end


    always @(posedge clk_1Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            high <= 4'd0;
        else if((change_flag==1'b1) && (high==MAX_model_1))
            high <= 4'd0;
        else if(change_flag==1'b1)
            high <= high + 4'd1;
    end


    always @(posedge clk_10Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            low <= 4'd0;
        else if((change_flag==1'b1) && (low==MAX_model_1))
            low <= 4'd0;
        else if(change_flag==1'b1)
            low <= low + 4'd1;
    end
  

    always @(posedge clk ) begin
        if((~key_sw3_n) && (key_sw0==1'b0))
            change_flag <= 1'b0;
        else if((~key_sw3_n) && (key_sw0==1'b1))
            change_flag <= 1'b1;
    end

    assign led = (change_flag==1'b0) ? led_reg : {high,low};

endmodule
module counter(
    input clk,
    input clk_1Hz,
    input clk_10Hz,
    input key_sw0,
    input key_sw3_n,
    output [7:0] led
);

    parameter MAX_model_0 = 8'd127;
    parameter MAX_model_1 = 4'd9;

    reg [7:0] led_reg;
    reg [3:0] high,low;
    reg change_flag;


    always @(posedge clk_1Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            led_reg <= 8'd0;
        else if((change_flag==1'b0) && (led_reg==MAX_model_0))
            led_reg <= 8'd0;
        else if(change_flag==1'b0)
            led_reg <= led_reg + 8'd1;
    end


    always @(posedge clk_1Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            high <= 4'd0;
        else if((change_flag==1'b1) && (high==MAX_model_1))
            high <= 4'd0;
        else if(change_flag==1'b1)
            high <= high + 4'd1;
    end


    always @(posedge clk_10Hz,negedge key_sw3_n) begin
        if(~key_sw3_n)
            low <= 4'd0;
        else if((change_flag==1'b1) && (low==MAX_model_1))
            low <= 4'd0;
        else if(change_flag==1'b1)
            low <= low + 4'd1;
    end
  

    always @(posedge clk ) begin
        if((~key_sw3_n) && (key_sw0==1'b0))
            change_flag <= 1'b0;
        else if((~key_sw3_n) && (key_sw0==1'b1))
            change_flag <= 1'b1;
    end

    assign led = (change_flag==1'b0) ? led_reg : {high,low};

endmodule