data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top.v
data/verilator_xmls/03323b66-c0ed-4b22-9655-63a864fd8435.xml
module nonblocking (
    input  wire CLK,
    input  wire BUT,
    output wire LED
);

  reg nb1, nb2, nb3;


  always @(posedge CLK) begin
    nb1 <= BUT;
    nb2 <= nb1;
    nb3 <= nb2;
  end

  assign LED = ~nb3;

endmodule
module nonblocking (
    input  wire CLK,
    input  wire BUT,
    output wire LED
);


  reg nb1, nb2, nb3;


  always @(posedge CLK) begin
    nb1 <= BUT;
    nb2 <= nb1;
    nb3 <= nb2;
  end

  assign LED = ~nb3;

endmodule