data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:35: Cannot find include file: brams_init_9.vh\n  `include "brams_init_9.vh" \n           ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.sv\n             brams_init_9.vh\n             brams_init_9.vh.v\n             brams_init_9.vh.sv\n             obj_dir/brams_init_9.vh\n             obj_dir/brams_init_9.vh.v\n             obj_dir/brams_init_9.vh.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:103: Cannot find include file: brams_init_18.vh\n   `include "brams_init_18.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:133: Cannot find include file: brams_init_16.vh\n   `include "brams_init_16.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:202: Cannot find include file: brams_init_9.vh\n   `include "brams_init_9.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:233: Cannot find include file: brams_init_8.vh\n   `include "brams_init_8.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 9;
	parameter CFG_DBITS = 18;
	parameter CFG_ENABLE_B = 2;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [9215:0] INIT = 9216'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
	wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
	wire [1:0] B1EN_2 = {2{B1EN}};

	wire [1:0] DIP, DOP;
	wire [15:0] DI, DO;

	wire [15:0] DOBDO;
	wire [1:0] DOPBDOP;

	assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	generate if (CFG_DBITS > 8) begin
		RAMB8BWER #(
			.RAM_MODE("TDP"),
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_9.vh"
		) _TECHMAP_REPLACE_ (
			.DIADI(16'b0),
			.DIPADIP(2'b0),
			.DOADO(DO),
			.DOPADOP(DOP),
			.ADDRAWRADDR(A1ADDR_13),
			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
			.ENAWREN(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEAWEL(2'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBRDADDR(B1ADDR_13),
			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
			.ENBRDEN(|1),
			.REGCEBREGCE(|0),
			.RSTBRST(|0),
			.WEBWEU(B1EN_2)
		);
	end else begin
		RAMB8BWER #(
			.RAM_MODE("TDP"),
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_8.vh"
		) _TECHMAP_REPLACE_ (
			.DIADI(16'b0),
			.DIPADIP(2'b0),
			.DOADO(DO),
			.DOPADOP(DOP),
			.ADDRAWRADDR(A1ADDR_13),
			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
			.ENAWREN(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEAWEL(2'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBRDADDR(B1ADDR_13),
			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
			.ENBRDEN(|1),
			.REGCEBREGCE(|0),
			.RSTBRST(|0),
			.WEBWEU(B1EN_2)
		);
	end endgenerate
endmodule
module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 9;
	parameter CFG_DBITS = 18;
	parameter CFG_ENABLE_B = 2;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [9215:0] INIT = 9216'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
	wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
	wire [1:0] B1EN_2 = {2{B1EN}};

	wire [1:0] DIP, DOP;
	wire [15:0] DI, DO;

	wire [15:0] DOBDO;
	wire [1:0] DOPBDOP;

	assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	generate if (CFG_DBITS > 8) begin
		RAMB8BWER #(
			.RAM_MODE("TDP"),
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_9.vh"
		) _TECHMAP_REPLACE_ (
			.DIADI(16'b0),
			.DIPADIP(2'b0),
			.DOADO(DO),
			.DOPADOP(DOP),
			.ADDRAWRADDR(A1ADDR_13),
			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
			.ENAWREN(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEAWEL(2'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBRDADDR(B1ADDR_13),
			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
			.ENBRDEN(|1),
			.REGCEBREGCE(|0),
			.RSTBRST(|0),
			.WEBWEU(B1EN_2)
		);
	end else begin
		RAMB8BWER #(
			.RAM_MODE("TDP"),
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_8.vh"
		) _TECHMAP_REPLACE_ (
			.DIADI(16'b0),
			.DIPADIP(2'b0),
			.DOADO(DO),
			.DOPADOP(DOP),
			.ADDRAWRADDR(A1ADDR_13),
			.CLKAWRCLK(CLK2 ^ !CLKPOL2),
			.ENAWREN(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEAWEL(2'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBRDADDR(B1ADDR_13),
			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
			.ENBRDEN(|1),
			.REGCEBREGCE(|0),
			.RSTBRST(|0),
			.WEBWEU(B1EN_2)
		);
	end endgenerate
endmodule