data/full_repos/permissive/504677412/src/fifo/fifo_fwft_adapter.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft_adapter.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [DATA_WIDTH-1:0]  fifo_dout_i,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft_adapter.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output reg [DATA_WIDTH-1:0] dout_o,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft_adapter.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\n   reg [DATA_WIDTH-1:0]  middle_dout;\n       ^\n%Error: Exiting due to 3 warning(s)\n'
module fifo_fwft_adapter
  #(parameter DATA_WIDTH = 0)
   (input 	       clk,
    input 			rst,
    input 			rd_en_i,
    input 			fifo_empty_i,
    output 			fifo_rd_en_o,
    input [DATA_WIDTH-1:0] 	fifo_dout_i,
    output reg [DATA_WIDTH-1:0] dout_o,
    output 			empty_o);
   
   reg 				fifo_valid, middle_valid, dout_valid;
   reg [DATA_WIDTH-1:0] 	middle_dout;
   
   wire 			will_update_middle, will_update_dout;

   assign will_update_middle = fifo_valid && (middle_valid == will_update_dout);
   assign will_update_dout = (middle_valid || fifo_valid) && (rd_en_i || !dout_valid);
   assign fifo_rd_en_o = (!fifo_empty_i) && !(middle_valid && dout_valid && fifo_valid);
   assign empty_o = !dout_valid;

   always @(posedge clk)
      if (rst)
         begin
            fifo_valid <= 0;
            middle_valid <= 0;
            dout_valid <= 0;
            dout_o <= 0;
            middle_dout <= 0;
         end
      else
         begin
            if (will_update_middle)
               middle_dout <= fifo_dout_i;
            
            if (will_update_dout)
               dout_o <= middle_valid ? middle_dout : fifo_dout_i;
            
            if (fifo_rd_en_o)
               fifo_valid <= 1;
            else if (will_update_middle || will_update_dout)
               fifo_valid <= 0;
            
            if (will_update_middle)
               middle_valid <= 1;
            else if (will_update_dout)
               middle_valid <= 0;
            
            if (will_update_dout)
               dout_valid <= 1;
            else if (rd_en_i)
               dout_valid <= 0;
         end 
   
endmodule
module fifo_fwft_adapter
  #(parameter DATA_WIDTH = 0)
   (input 	       clk,
    input 			rst,
    input 			rd_en_i,
    input 			fifo_empty_i,
    output 			fifo_rd_en_o,
    input [DATA_WIDTH-1:0] 	fifo_dout_i,
    output reg [DATA_WIDTH-1:0] dout_o,
    output 			empty_o);

   
   reg 				fifo_valid, middle_valid, dout_valid;
   reg [DATA_WIDTH-1:0] 	middle_dout;
   
   wire 			will_update_middle, will_update_dout;

   assign will_update_middle = fifo_valid && (middle_valid == will_update_dout);
   assign will_update_dout = (middle_valid || fifo_valid) && (rd_en_i || !dout_valid);
   assign fifo_rd_en_o = (!fifo_empty_i) && !(middle_valid && dout_valid && fifo_valid);
   assign empty_o = !dout_valid;

   always @(posedge clk)
      if (rst)
         begin
            fifo_valid <= 0;
            middle_valid <= 0;
            dout_valid <= 0;
            dout_o <= 0;
            middle_dout <= 0;
         end
      else
         begin
            if (will_update_middle)
               middle_dout <= fifo_dout_i;
            
            if (will_update_dout)
               dout_o <= middle_valid ? middle_dout : fifo_dout_i;
            
            if (fifo_rd_en_o)
               fifo_valid <= 1;
            else if (will_update_middle || will_update_dout)
               fifo_valid <= 0;
            
            if (will_update_middle)
               middle_valid <= 1;
            else if (will_update_dout)
               middle_valid <= 0;
            
            if (will_update_dout)
               dout_valid <= 1;
            else if (rd_en_i)
               dout_valid <= 0;
         end 
   
endmodule