data/full_repos/permissive/445379100/a4/control.v
data/verilator_xmls/dadae51a-9b99-444e-8a67-cf954668b74b.xml
module control (
    input reset ,
    input [31:0] idata ,
    input [31:0] iaddr ,
    input clkreset_flag ,
    

    output reg [3:0] alu_op,
    output reg mux1_sel ,
    output reg [1:0] mux2_sel ,
    output reg auipc ,
    output reg jal ,
    output reg [3:0] dwe ,
    output reg [3:0] rf_we ,
    output reg l_unsign_flag ,
    output reg is_branch_type ,
    output reg is_conditional_branch_type ,
    output reg [31:0] branch_condition ,
    

    output reg [4:0] rs1 , 
    output reg [4:0] rs2 ,
    output reg [4:0] rd ,
    output reg [31:0] imm12_ext ,
    output reg [31:0] imm20_ext ,

    output reg [4:0] shamt 


);
    wire [6:0] opcode;
    assign opcode = idata[6:0]; 

    always @(*) begin
	
    if (reset && clkreset_flag) begin
        

        rs1 = 0 ;
        rs2 = 0 ;
        rd = 0 ;
        imm12_ext = 0 ;
        imm20_ext = 0 ;
        shamt = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        alu_op = 4'b1111 ;
        l_unsign_flag = 0 ;
        dwe = 0 ;
        rf_we = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        jal = 0 ;

    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0110011 )
    begin
            

        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        rd = idata[11:7] ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        dwe = 4'b0000 ;
        rf_we = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;

        if (idata[14:12] == 3'b000 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 0 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b000 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) begin
            alu_op = 1 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b001 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 2 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b010 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 3 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b011 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 4 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b100 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin 
            alu_op = 5 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b101 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin 
            alu_op = 6 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b101 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) begin
            alu_op = 7 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b110 && idata[31:25] == 7'b0000000) begin 
            alu_op = 8 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b111 && idata[31:25] == 7'b0000000) begin
            alu_op = 9 ;
            rf_we = 4'b1111 ;

        end   
        
    end



    else if ( clkreset_flag==1'b0 && opcode == 7'b0010011  )
    begin
            
        rs1 = idata[19:15] ;
        rd = idata[11:7] ;
        rs2 = idata[24:20] ;

        rf_we = 0 ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        dwe = 0 ;
        jal = 0 ;

        if ( idata[14:12] == 3'b000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 0 ;
            imm12_ext = {{20{idata[31]}} , idata[31:20]} ;    
            rf_we = 4'b1111 ; 

        end 

        else if ( idata[14:12] == 3'b010 && idata[11:7] != 5'd0) 
        begin
            alu_op = 3 ;
            imm12_ext = {{20{idata[31]}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end 

        else if ( idata[14:12] == 3'b011 && idata[11:7] != 5'd0) 
        begin
            alu_op = 4 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end 

        else if ( idata[14:12] == 3'b100 && idata[11:7] != 5'd0) 
        begin
            alu_op = 5 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ;  
            rf_we = 4'b1111 ; 

        end 

        else if ( idata[14:12] == 3'b110 && idata[11:7] != 5'd0) 
        begin
            alu_op = 8 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end

        
        else if ( idata[14:12] == 3'b111 && idata[11:7] != 5'd0) 
        begin
            alu_op = 9 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ;    
            rf_we = 4'b1111 ;  

        end
        
        if ( idata[14:12] == 3'b001 && idata[11:7] != 5'd0) 
        begin
            alu_op = 2 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end

        else if ( idata[14:12] == 3'b101 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 6 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end
            
        else if ( idata[14:12] == 3'b101 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 7 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end 
        
    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0100011 )
    begin
            
        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        imm12_ext = {{20{idata[31]}} , {idata[31:25]} , {idata[11:7]}} ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        rf_we = 0 ;
        alu_op = 0;

        l_unsign_flag = 0 ;
        dwe = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;
        
        if ( idata[14:12] == 3'b000 ) begin

            dwe = 4'b0001 ;

        end

        else if ( idata[14:12] == 3'b001 ) begin

            dwe = 4'b0011 ;

        end
     
        if ( idata[14:12] == 3'b010 ) begin

            dwe = 4'b1111 ;

        end
     
    end
    

    else if ( clkreset_flag==1'b0 && opcode == 7'b0000011 )
    begin
             
        rs1 = idata[19:15] ;
        rd = idata[11:7] ;
        imm12_ext = {{20{idata[31]}} , idata[31:20]} ;  
        mux1_sel = 1 ;

        alu_op = 0 ;
        dwe = 0 ;
        rs2 = 0 ;
        mux2_sel = 1 ;
        rf_we = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;
        
        if ( idata[14:12] == 3'b000 && idata[11:7] != 0) begin
            rf_we = 4'b0001 ;
            l_unsign_flag = 0 ;

        end

        else if ( idata[14:12] == 3'b001 && idata[11:7] != 0) begin
            rf_we = 4'b0011 ;
            l_unsign_flag = 0 ;

        end

        if ( idata[14:12] == 3'b010 && idata[11:7] != 0) begin
            rf_we = 4'b1111 ;
            l_unsign_flag = 0 ;

        end



        if ( idata[14:12] == 3'b100 && idata[11:7] != 0) begin
            rf_we = 4'b0001 ;
            l_unsign_flag = 1 ;

        end

        if ( idata[14:12] == 3'b101 && idata[11:7] != 0) begin
            rf_we = 4'b0011 ;
            l_unsign_flag = 1 ;

        end
    end
    
    else if ( clkreset_flag==1'b0 && opcode == 7'b0110111 )
    begin
        
        rs1 = 0 ;
        rs2 = 0 ;
        rd = idata[11:7] ;
        imm12_ext = { idata[31:12] , {12{1'b0}} };
        imm20_ext = 0 ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        is_branch_type = 0 ;
        alu_op = 0 ;
        dwe = 0 ;
        rf_we = 4'b1111 ;
        branch_condition  = 0 ;
        is_conditional_branch_type = 0 ;
        auipc = 0 ;
        jal = 0 ;



    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0010111 )
    begin
        rs1 = 0 ;  
        rs2 = 0 ;
        rd = idata[11:7] ;
        mux1_sel = 1 ;
        mux2_sel = 3 ;
        rf_we = 4'b1111 ;
        alu_op = 0 ;
        dwe = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0;
        imm12_ext = { idata[31:12] , {12{1'b0}} } ;
        l_unsign_flag = 0;
        auipc = 1 ;
        jal = 0 ;




    end

    else if ( clkreset_flag==1'b0 && opcode ==  7'b1100011 )
    begin

        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        imm12_ext = { {21{idata[31]}} , idata[7] , {idata[30:25]} , {idata[11:8]} } ;
        alu_op = 0 ;
        rf_we = 0 ;
        dwe = 0 ;
        is_branch_type = 1 ;
        is_conditional_branch_type = 1 ;
        branch_condition  = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        auipc = 0 ;
        jal = 0 ;

        if ( idata[14:12] == 3'b000 ) begin
            alu_op = 10 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b001 ) begin
            alu_op = 10 ;
            branch_condition = 32'b0 ;

        end

        else if (idata[14:12] == 3'b100 ) begin
            alu_op = 3 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b101 ) begin
            alu_op = 3 ;
            branch_condition = 32'b0 ;

        end

        else if (idata[14:12] == 3'b001 ) begin
            alu_op = 4 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b110 ) begin
            alu_op = 4 ;
            branch_condition = 32'b0 ;

        end
    end
    
    else if ( clkreset_flag==1'b0 && opcode == 7'b1100111 )
    begin




        rd = idata[11:7] ;
        rs1 = idata[19:15] ;
        imm12_ext = { {20{idata[31]}} , idata[31:20] } ;
        alu_op = 11 ;  
        rf_we = 4'b1111 ;
        mux1_sel = 1 ;
        mux2_sel = 2 ;
        is_branch_type = 1 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0 ;
        auipc = 0 ;
        jal = 0 ;



    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b1101111 )
    begin



        
        jal = 1 ;
        rs1 = 0 ; 
        rs2 = 0 ;
        imm12_ext = { {13{idata[31]}} , idata[19:12] , idata[20] , idata[30:21] } ;  
        rd = idata[11:7] ;
        mux1_sel = 0 ;
        mux2_sel = 2 ;
        rf_we = 4'b1111 ;
        dwe = 0 ;
        alu_op = 12 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0 ;
        auipc = 0 ;



    end

    else begin
        rs1 = 0 ;
        rs2 = 0 ;
        rd = 0 ;
        imm12_ext = 0 ;
        imm20_ext = 0 ;
        shamt = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        alu_op = 4'b1111 ;
        l_unsign_flag = 0 ;
        dwe = 0 ;
        rf_we = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        jal = 0 ;
    end

    end
endmodule
module control (
    input reset ,
    input [31:0] idata ,
    input [31:0] iaddr ,
    input clkreset_flag ,
    

    output reg [3:0] alu_op,
    output reg mux1_sel ,
    output reg [1:0] mux2_sel ,
    output reg auipc ,
    output reg jal ,
    output reg [3:0] dwe ,
    output reg [3:0] rf_we ,
    output reg l_unsign_flag ,
    output reg is_branch_type ,
    output reg is_conditional_branch_type ,
    output reg [31:0] branch_condition ,
    

    output reg [4:0] rs1 , 
    output reg [4:0] rs2 ,
    output reg [4:0] rd ,
    output reg [31:0] imm12_ext ,
    output reg [31:0] imm20_ext ,

    output reg [4:0] shamt 


);

    wire [6:0] opcode;
    assign opcode = idata[6:0]; 

    always @(*) begin
	
    if (reset && clkreset_flag) begin
        

        rs1 = 0 ;
        rs2 = 0 ;
        rd = 0 ;
        imm12_ext = 0 ;
        imm20_ext = 0 ;
        shamt = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        alu_op = 4'b1111 ;
        l_unsign_flag = 0 ;
        dwe = 0 ;
        rf_we = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        jal = 0 ;

    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0110011 )
    begin
            

        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        rd = idata[11:7] ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        dwe = 4'b0000 ;
        rf_we = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;

        if (idata[14:12] == 3'b000 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 0 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b000 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) begin
            alu_op = 1 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b001 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 2 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b010 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 3 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b011 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin
            alu_op = 4 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b100 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin 
            alu_op = 5 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b101 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) begin 
            alu_op = 6 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b101 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) begin
            alu_op = 7 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b110 && idata[31:25] == 7'b0000000) begin 
            alu_op = 8 ;
            rf_we = 4'b1111 ;

        end

        else if (idata[14:12] == 3'b111 && idata[31:25] == 7'b0000000) begin
            alu_op = 9 ;
            rf_we = 4'b1111 ;

        end   
        
    end



    else if ( clkreset_flag==1'b0 && opcode == 7'b0010011  )
    begin
            
        rs1 = idata[19:15] ;
        rd = idata[11:7] ;
        rs2 = idata[24:20] ;

        rf_we = 0 ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        dwe = 0 ;
        jal = 0 ;

        if ( idata[14:12] == 3'b000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 0 ;
            imm12_ext = {{20{idata[31]}} , idata[31:20]} ;    
            rf_we = 4'b1111 ; 

        end 

        else if ( idata[14:12] == 3'b010 && idata[11:7] != 5'd0) 
        begin
            alu_op = 3 ;
            imm12_ext = {{20{idata[31]}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end 

        else if ( idata[14:12] == 3'b011 && idata[11:7] != 5'd0) 
        begin
            alu_op = 4 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end 

        else if ( idata[14:12] == 3'b100 && idata[11:7] != 5'd0) 
        begin
            alu_op = 5 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ;  
            rf_we = 4'b1111 ; 

        end 

        else if ( idata[14:12] == 3'b110 && idata[11:7] != 5'd0) 
        begin
            alu_op = 8 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ; 
            rf_we = 4'b1111 ;

        end

        
        else if ( idata[14:12] == 3'b111 && idata[11:7] != 5'd0) 
        begin
            alu_op = 9 ;
            imm12_ext = {{20{1'b0}} , idata[31:20]} ;    
            rf_we = 4'b1111 ;  

        end
        
        if ( idata[14:12] == 3'b001 && idata[11:7] != 5'd0) 
        begin
            alu_op = 2 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end

        else if ( idata[14:12] == 3'b101 && idata[31:25] == 7'b0000000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 6 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end
            
        else if ( idata[14:12] == 3'b101 && idata[31:25] == 7'b0100000 && idata[11:7] != 5'd0) 
        begin
            alu_op = 7 ;
            shamt = idata[24:20] ;

            mux1_sel = 0 ;
            rf_we = 4'b1111 ;

        end 
        
    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0100011 )
    begin
            
        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        imm12_ext = {{20{idata[31]}} , {idata[31:25]} , {idata[11:7]}} ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        rf_we = 0 ;
        alu_op = 0;

        l_unsign_flag = 0 ;
        dwe = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;
        
        if ( idata[14:12] == 3'b000 ) begin

            dwe = 4'b0001 ;

        end

        else if ( idata[14:12] == 3'b001 ) begin

            dwe = 4'b0011 ;

        end
     
        if ( idata[14:12] == 3'b010 ) begin

            dwe = 4'b1111 ;

        end
     
    end
    

    else if ( clkreset_flag==1'b0 && opcode == 7'b0000011 )
    begin
             
        rs1 = idata[19:15] ;
        rd = idata[11:7] ;
        imm12_ext = {{20{idata[31]}} , idata[31:20]} ;  
        mux1_sel = 1 ;

        alu_op = 0 ;
        dwe = 0 ;
        rs2 = 0 ;
        mux2_sel = 1 ;
        rf_we = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        jal = 0 ;
        
        if ( idata[14:12] == 3'b000 && idata[11:7] != 0) begin
            rf_we = 4'b0001 ;
            l_unsign_flag = 0 ;

        end

        else if ( idata[14:12] == 3'b001 && idata[11:7] != 0) begin
            rf_we = 4'b0011 ;
            l_unsign_flag = 0 ;

        end

        if ( idata[14:12] == 3'b010 && idata[11:7] != 0) begin
            rf_we = 4'b1111 ;
            l_unsign_flag = 0 ;

        end



        if ( idata[14:12] == 3'b100 && idata[11:7] != 0) begin
            rf_we = 4'b0001 ;
            l_unsign_flag = 1 ;

        end

        if ( idata[14:12] == 3'b101 && idata[11:7] != 0) begin
            rf_we = 4'b0011 ;
            l_unsign_flag = 1 ;

        end
    end
    
    else if ( clkreset_flag==1'b0 && opcode == 7'b0110111 )
    begin
        
        rs1 = 0 ;
        rs2 = 0 ;
        rd = idata[11:7] ;
        imm12_ext = { idata[31:12] , {12{1'b0}} };
        imm20_ext = 0 ;
        mux1_sel = 1 ;
        mux2_sel = 0 ;
        is_branch_type = 0 ;
        alu_op = 0 ;
        dwe = 0 ;
        rf_we = 4'b1111 ;
        branch_condition  = 0 ;
        is_conditional_branch_type = 0 ;
        auipc = 0 ;
        jal = 0 ;



    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b0010111 )
    begin
        rs1 = 0 ;  
        rs2 = 0 ;
        rd = idata[11:7] ;
        mux1_sel = 1 ;
        mux2_sel = 3 ;
        rf_we = 4'b1111 ;
        alu_op = 0 ;
        dwe = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0;
        imm12_ext = { idata[31:12] , {12{1'b0}} } ;
        l_unsign_flag = 0;
        auipc = 1 ;
        jal = 0 ;




    end

    else if ( clkreset_flag==1'b0 && opcode ==  7'b1100011 )
    begin

        rs1 = idata[19:15] ;
        rs2 = idata[24:20] ;
        imm12_ext = { {21{idata[31]}} , idata[7] , {idata[30:25]} , {idata[11:8]} } ;
        alu_op = 0 ;
        rf_we = 0 ;
        dwe = 0 ;
        is_branch_type = 1 ;
        is_conditional_branch_type = 1 ;
        branch_condition  = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        auipc = 0 ;
        jal = 0 ;

        if ( idata[14:12] == 3'b000 ) begin
            alu_op = 10 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b001 ) begin
            alu_op = 10 ;
            branch_condition = 32'b0 ;

        end

        else if (idata[14:12] == 3'b100 ) begin
            alu_op = 3 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b101 ) begin
            alu_op = 3 ;
            branch_condition = 32'b0 ;

        end

        else if (idata[14:12] == 3'b001 ) begin
            alu_op = 4 ;
            branch_condition = 32'b1 ;

        end

        else if (idata[14:12] == 3'b110 ) begin
            alu_op = 4 ;
            branch_condition = 32'b0 ;

        end
    end
    
    else if ( clkreset_flag==1'b0 && opcode == 7'b1100111 )
    begin




        rd = idata[11:7] ;
        rs1 = idata[19:15] ;
        imm12_ext = { {20{idata[31]}} , idata[31:20] } ;
        alu_op = 11 ;  
        rf_we = 4'b1111 ;
        mux1_sel = 1 ;
        mux2_sel = 2 ;
        is_branch_type = 1 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0 ;
        auipc = 0 ;
        jal = 0 ;



    end

    else if ( clkreset_flag==1'b0 && opcode == 7'b1101111 )
    begin



        
        jal = 1 ;
        rs1 = 0 ; 
        rs2 = 0 ;
        imm12_ext = { {13{idata[31]}} , idata[19:12] , idata[20] , idata[30:21] } ;  
        rd = idata[11:7] ;
        mux1_sel = 0 ;
        mux2_sel = 2 ;
        rf_we = 4'b1111 ;
        dwe = 0 ;
        alu_op = 12 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition = 0 ;
        auipc = 0 ;



    end

    else begin
        rs1 = 0 ;
        rs2 = 0 ;
        rd = 0 ;
        imm12_ext = 0 ;
        imm20_ext = 0 ;
        shamt = 0 ;
        is_branch_type = 0 ;
        is_conditional_branch_type = 0 ;
        branch_condition  = 0 ;
        auipc = 0 ;
        alu_op = 4'b1111 ;
        l_unsign_flag = 0 ;
        dwe = 0 ;
        rf_we = 0 ;
        mux1_sel = 0 ;
        mux2_sel = 0 ;
        jal = 0 ;
    end

    end
endmodule