data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v:66: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 9 bits.\n                                                                                                          : ... In instance VcdAdder.do_add.s_pad_2\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DoAdd(
    input clock,
    input [7:0] a,
    input [7:0] b,
    output [9:0] c
);
    wire [8:0] _accum__q;
    wire [8:0] _accum__d;
    DFF_POSCLK #(.width(9)) accum (
        .q(_accum__q),
        .d(_accum__d),
        .clk(clock)
    );
    ADD_SIGNED #(.width(8)) s_add_1 (
        .y(_accum__d),
        .a(a),
        .b(b)
    );
    PAD_SIGNED #(.width(9), .n(10)) s_pad_2 (
        .y(c),
        .in(_accum__q)
    );
endmodule
module DoAdd(
    input clock,
    input [7:0] a,
    input [7:0] b,
    output [9:0] c
);

    wire [8:0] _accum__q;
    wire [8:0] _accum__d;
    DFF_POSCLK #(.width(9)) accum (
        .q(_accum__q),
        .d(_accum__d),
        .clk(clock)
    );
    ADD_SIGNED #(.width(8)) s_add_1 (
        .y(_accum__d),
        .a(a),
        .b(b)
    );
    PAD_SIGNED #(.width(9), .n(10)) s_pad_2 (
        .y(c),
        .in(_accum__q)
    );
endmodule