data/full_repos/permissive/413440740/source/slv_i2c_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/413440740/source/slv_i2c_fsm.v:113: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'cnt_bit_data\' generates 4 bits.\n                                                                             : ... In instance slv_i2c_fsm\n                            if (&(!cnt_bit_data))\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/413440740/source/slv_i2c_fsm.v:165: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'cnt_bit_data\' generates 4 bits.\n                                                                             : ... In instance slv_i2c_fsm\n                            if (&(!cnt_bit_data))\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/413440740/source/slv_i2c_fsm.v:214: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'addr_reg_offset\' generates 8 bits.\n                                                                             : ... In instance slv_i2c_fsm\n                                    nx_o_addr_reg = &(!addr_reg_offset) ? O_ADDR_REG : addr_reg_offset;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/413440740/source/slv_i2c_fsm.v:212: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'cnt_bit_data\' generates 4 bits.\n                                                                             : ... In instance slv_i2c_fsm\n                            if (&(!cnt_bit_data))\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/413440740/source/slv_i2c_fsm.v:235: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'cnt_bit_data\' generates 4 bits.\n                                                                             : ... In instance slv_i2c_fsm\n                            if (&(!cnt_bit_data))\n                                  ^\n%Error: Exiting due to 5 warning(s)\n'
module slv_i2c_fsm
    #(parameter DATA_SZ = 8)
    (CLK, RST_n, I_SCL, I_SDA, I_RS_IO_SCL, I_FL_IO_SCL, I_RS_IO_SDA, I_FL_IO_SDA, I_ACK, I_MDL_LW_IO_SCL, I_DATA_WR,
     O_ADDR_SLV, O_RW, O_ADDR_REG, O_DATA_RD,  O_SDA, O_BUSY, O_CH_CNCT, O_DATA_VL);



    localparam CNT_BIT_DATA_SZ = $clog2(DATA_SZ) + 1;

    localparam ST_SZ     = 9;
    (* syn_encoding = "one-hot" *) reg [ST_SZ-1:0] st;
    localparam IDLE      = 0;
    localparam START     = 1;
    localparam COMM_MSTR = 2;
    localparam ACK_COMM  = 3;
    localparam ADDR_REG  = 4;
    localparam ACK_DATA  = 5;
    localparam WR        = 6;
    localparam RD        = 7;
    localparam MSTR_ACK  = 8;

    input wire               CLK;
    input wire               RST_n;
    input wire               I_SCL;
    input wire               I_SDA;
    input wire               I_RS_IO_SCL;
    input wire               I_FL_IO_SCL;
    input wire               I_RS_IO_SDA;
    input wire               I_FL_IO_SDA;
    input wire               I_ACK;
    input wire               I_MDL_LW_IO_SCL;
    input wire [DATA_SZ-1:0] I_DATA_WR;

    output reg [DATA_SZ-2:0] O_ADDR_SLV;
    output reg               O_RW;
    output reg [DATA_SZ-1:0] O_ADDR_REG;
    output reg [DATA_SZ-1:0] O_DATA_RD;
    output reg               O_SDA;
    output reg               O_BUSY;
    output reg               O_CH_CNCT;
    output reg               O_DATA_VL;

    reg [ST_SZ-1:0]           nx_st;
    reg [DATA_SZ-2:0]         nx_o_addr_slv;
    reg                       nx_o_rw;
    reg [DATA_SZ-1:0]         nx_o_addr_reg;
    reg [DATA_SZ-1:0]         nx_o_data_rd;
    reg                       nx_o_sda;
    reg                       nx_o_busy;
    reg                       nx_o_ch_cnct;
    reg                       nx_o_data_vl;
    reg [DATA_SZ-1:0]         buff_rd;
    reg [DATA_SZ-1:0]         nx_buff_rd;
    reg [DATA_SZ-1:0]         buff_wr;
    reg [DATA_SZ-1:0]         nx_buff_wr;
    reg [CNT_BIT_DATA_SZ-1:0] cnt_bit_data;
    reg [CNT_BIT_DATA_SZ-1:0] nx_cnt_bit_data;
    reg [DATA_SZ-1:0]         comm_slv;
    reg [DATA_SZ-1:0]         nx_comm_slv;
    reg [DATA_SZ-1:0]         pr_comm_slv;
    reg [DATA_SZ-1:0]         nx_pr_comm_slv;
    reg [DATA_SZ-1:0]         pr_addr_reg;
    reg [DATA_SZ-1:0]         nx_pr_addr_reg;
    reg [DATA_SZ-1:0]         addr_reg_offset;
    reg [DATA_SZ-1:0]         nx_addr_reg_offset;
    reg                       ack_from_slave;
    reg                       nx_ack_from_slave;
    reg                       go;
    reg                       nx_go;


    always @(*) begin
        nx_st = st;
        nx_o_addr_slv = O_ADDR_SLV;
        nx_o_rw = O_RW;
        nx_o_addr_reg = O_ADDR_REG;
        nx_o_data_rd = O_DATA_RD;
        nx_o_sda = O_SDA;
        nx_o_busy = O_BUSY;
        nx_o_ch_cnct = O_CH_CNCT;
        nx_o_data_vl = O_DATA_VL;
        nx_buff_rd = buff_rd;
        nx_buff_wr = buff_wr;
        nx_cnt_bit_data = cnt_bit_data;
        nx_comm_slv = comm_slv;
        nx_pr_comm_slv = pr_comm_slv;
        nx_pr_addr_reg = pr_addr_reg;
        nx_addr_reg_offset = addr_reg_offset;
        nx_ack_from_slave = ack_from_slave;
        nx_go = go;
        case (st)
            IDLE     :  begin
                            if (I_FL_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b1;
                                    nx_st = START;
                                end
                        end
            START    :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_cnt_bit_data = DATA_SZ - 1'b1;
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_st = COMM_MSTR;
                                end
                        end
            COMM_MSTR : begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_comm_slv = buff_rd;
                                    nx_o_rw = buff_rd[0];
                                    nx_o_ch_cnct = 1'b1;
                                    nx_o_addr_slv = buff_rd[DATA_SZ-1:1];
                                    if ({pr_comm_slv[DATA_SZ-1:1], 1'b1} == buff_rd)
                                        begin
                                            nx_o_addr_reg = pr_addr_reg;
                                            nx_o_data_vl = 1'b1;
                                        end
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = I_ACK;
                                            nx_ack_from_slave = I_ACK;
                                            nx_go = 1'b1;
                                            nx_o_ch_cnct = 1'b0;
                                            nx_o_data_vl = 1'b0;
                                            nx_st = ACK_COMM;
                                        end
                                end
                        end
            ACK_COMM :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_go = 1'b0;
                                    if (comm_slv[0])
                                        begin
                                            nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                            nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                            nx_st = WR;
                                        end
                                    else nx_o_sda = 1'b1;
                                end
                            if (I_RS_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b0;
                                    nx_st = IDLE;
                                end
                            if (I_FL_IO_SCL & !go)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_st = ADDR_REG;
                                end
                        end
            ADDR_REG :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_o_addr_reg = buff_rd;
                                    nx_addr_reg_offset = {DATA_SZ{1'b0}};
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = ack_from_slave;
                                            nx_go = 1'b1;
                                            nx_st = ACK_DATA;
                                        end
                                end
                        end
            ACK_DATA :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_go = 1'b0;
                                    nx_o_sda = 1'b1;
                                end
                            if (I_RS_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b0;
                                    nx_pr_addr_reg = O_ADDR_REG;
                                    nx_pr_comm_slv = comm_slv;
                                    nx_st = IDLE;
                                end
                            if (I_FL_IO_SCL & !go)
                                begin
                                    if (comm_slv[0])
                                        begin
                                            nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                            nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                            nx_st = WR;
                                        end
                                    else
                                        begin
                                            nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                            nx_st = RD;
                                        end
                                end
                        end
            RD       :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_o_addr_reg = &(!addr_reg_offset) ? O_ADDR_REG : addr_reg_offset;
                                    nx_o_data_rd = buff_rd;
                                    nx_o_data_vl = 1'b1;
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = ack_from_slave;
                                            nx_go = 1'b1;
                                            nx_o_data_vl = 1'b0;
                                            nx_addr_reg_offset = O_ADDR_REG + 1'b1;
                                            nx_st = ACK_DATA;
                                        end
                                end
                        end
            WR       :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_o_sda = buff_wr[DATA_SZ-1];
                                    nx_buff_wr = {buff_wr[DATA_SZ-2:0], 1'b0};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = 1'b1;
                                            nx_st = MSTR_ACK;
                                        end
                                end
                        end
            MSTR_ACK :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    if (I_SDA)
                                        begin
                                            nx_o_busy = 1'b0;
                                            nx_st = IDLE;
                                        end
                                    else
                                        begin
                                            nx_o_addr_reg = O_ADDR_REG + 1'b1;
                                            nx_o_data_vl = 1'b1;
                                        end
                                end
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                    nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                    nx_o_data_vl = 1'b0;
                                    nx_st = WR;
                                end
                        end
            default  :  begin
                            nx_st = IDLE;
                            nx_o_sda = 1'b1;
                            nx_o_busy = 1'b0;
                            nx_o_data_vl = 1'b0;
                            pr_comm_slv = {DATA_SZ{1'b0}};
                            nx_ack_from_slave = 1'b1;
                            nx_addr_reg_offset = {DATA_SZ{1'b0}};
                        end
        endcase
    end


    always @(posedge CLK or negedge RST_n) begin
        if (!RST_n)
            begin
                st              <= IDLE;
                O_ADDR_SLV      <= {DATA_SZ-1{1'b0}};
                O_RW            <= 1'b0;
                O_ADDR_REG      <= {DATA_SZ{1'b0}};
                O_DATA_RD       <= {DATA_SZ{1'b0}};
                O_SDA           <= 1'b1;
                O_BUSY          <= 1'b0;
                O_CH_CNCT       <= 1'b0;
                O_DATA_VL       <= 1'b0;
                buff_rd         <= {DATA_SZ{1'b0}};
                buff_wr         <= {DATA_SZ{1'b0}};
                cnt_bit_data    <= {CNT_BIT_DATA_SZ{1'b0}};
                comm_slv        <= {DATA_SZ{1'b0}};
                pr_comm_slv     <= {DATA_SZ{1'b0}};
                pr_addr_reg     <= {DATA_SZ{1'b0}};
                addr_reg_offset <= {DATA_SZ{1'b0}};
                ack_from_slave  <= 1'b1;
                go              <= 1'b0;
            end
        else
            begin
                st              <= nx_st;
                O_ADDR_SLV      <= nx_o_addr_slv;
                O_RW            <= nx_o_rw;
                O_ADDR_REG      <= nx_o_addr_reg;
                O_DATA_RD       <= nx_o_data_rd;
                O_SDA           <= nx_o_sda;
                O_BUSY          <= nx_o_busy;
                O_CH_CNCT       <= nx_o_ch_cnct;
                O_DATA_VL       <= nx_o_data_vl;
                buff_rd         <= nx_buff_rd;
                buff_wr         <= nx_buff_wr;
                cnt_bit_data    <= nx_cnt_bit_data;
                comm_slv        <= nx_comm_slv;
                pr_comm_slv     <= nx_pr_comm_slv;
                pr_addr_reg     <= nx_pr_addr_reg;
                addr_reg_offset <= nx_addr_reg_offset;
                ack_from_slave  <= nx_ack_from_slave;
                go              <= nx_go;
            end
    end


endmodule
module slv_i2c_fsm
    #(parameter DATA_SZ = 8)
    (CLK, RST_n, I_SCL, I_SDA, I_RS_IO_SCL, I_FL_IO_SCL, I_RS_IO_SDA, I_FL_IO_SDA, I_ACK, I_MDL_LW_IO_SCL, I_DATA_WR,
     O_ADDR_SLV, O_RW, O_ADDR_REG, O_DATA_RD,  O_SDA, O_BUSY, O_CH_CNCT, O_DATA_VL);




    localparam CNT_BIT_DATA_SZ = $clog2(DATA_SZ) + 1;

    localparam ST_SZ     = 9;
    (* syn_encoding = "one-hot" *) reg [ST_SZ-1:0] st;
    localparam IDLE      = 0;
    localparam START     = 1;
    localparam COMM_MSTR = 2;
    localparam ACK_COMM  = 3;
    localparam ADDR_REG  = 4;
    localparam ACK_DATA  = 5;
    localparam WR        = 6;
    localparam RD        = 7;
    localparam MSTR_ACK  = 8;

    input wire               CLK;
    input wire               RST_n;
    input wire               I_SCL;
    input wire               I_SDA;
    input wire               I_RS_IO_SCL;
    input wire               I_FL_IO_SCL;
    input wire               I_RS_IO_SDA;
    input wire               I_FL_IO_SDA;
    input wire               I_ACK;
    input wire               I_MDL_LW_IO_SCL;
    input wire [DATA_SZ-1:0] I_DATA_WR;

    output reg [DATA_SZ-2:0] O_ADDR_SLV;
    output reg               O_RW;
    output reg [DATA_SZ-1:0] O_ADDR_REG;
    output reg [DATA_SZ-1:0] O_DATA_RD;
    output reg               O_SDA;
    output reg               O_BUSY;
    output reg               O_CH_CNCT;
    output reg               O_DATA_VL;

    reg [ST_SZ-1:0]           nx_st;
    reg [DATA_SZ-2:0]         nx_o_addr_slv;
    reg                       nx_o_rw;
    reg [DATA_SZ-1:0]         nx_o_addr_reg;
    reg [DATA_SZ-1:0]         nx_o_data_rd;
    reg                       nx_o_sda;
    reg                       nx_o_busy;
    reg                       nx_o_ch_cnct;
    reg                       nx_o_data_vl;
    reg [DATA_SZ-1:0]         buff_rd;
    reg [DATA_SZ-1:0]         nx_buff_rd;
    reg [DATA_SZ-1:0]         buff_wr;
    reg [DATA_SZ-1:0]         nx_buff_wr;
    reg [CNT_BIT_DATA_SZ-1:0] cnt_bit_data;
    reg [CNT_BIT_DATA_SZ-1:0] nx_cnt_bit_data;
    reg [DATA_SZ-1:0]         comm_slv;
    reg [DATA_SZ-1:0]         nx_comm_slv;
    reg [DATA_SZ-1:0]         pr_comm_slv;
    reg [DATA_SZ-1:0]         nx_pr_comm_slv;
    reg [DATA_SZ-1:0]         pr_addr_reg;
    reg [DATA_SZ-1:0]         nx_pr_addr_reg;
    reg [DATA_SZ-1:0]         addr_reg_offset;
    reg [DATA_SZ-1:0]         nx_addr_reg_offset;
    reg                       ack_from_slave;
    reg                       nx_ack_from_slave;
    reg                       go;
    reg                       nx_go;


    always @(*) begin
        nx_st = st;
        nx_o_addr_slv = O_ADDR_SLV;
        nx_o_rw = O_RW;
        nx_o_addr_reg = O_ADDR_REG;
        nx_o_data_rd = O_DATA_RD;
        nx_o_sda = O_SDA;
        nx_o_busy = O_BUSY;
        nx_o_ch_cnct = O_CH_CNCT;
        nx_o_data_vl = O_DATA_VL;
        nx_buff_rd = buff_rd;
        nx_buff_wr = buff_wr;
        nx_cnt_bit_data = cnt_bit_data;
        nx_comm_slv = comm_slv;
        nx_pr_comm_slv = pr_comm_slv;
        nx_pr_addr_reg = pr_addr_reg;
        nx_addr_reg_offset = addr_reg_offset;
        nx_ack_from_slave = ack_from_slave;
        nx_go = go;
        case (st)
            IDLE     :  begin
                            if (I_FL_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b1;
                                    nx_st = START;
                                end
                        end
            START    :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_cnt_bit_data = DATA_SZ - 1'b1;
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_st = COMM_MSTR;
                                end
                        end
            COMM_MSTR : begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_comm_slv = buff_rd;
                                    nx_o_rw = buff_rd[0];
                                    nx_o_ch_cnct = 1'b1;
                                    nx_o_addr_slv = buff_rd[DATA_SZ-1:1];
                                    if ({pr_comm_slv[DATA_SZ-1:1], 1'b1} == buff_rd)
                                        begin
                                            nx_o_addr_reg = pr_addr_reg;
                                            nx_o_data_vl = 1'b1;
                                        end
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = I_ACK;
                                            nx_ack_from_slave = I_ACK;
                                            nx_go = 1'b1;
                                            nx_o_ch_cnct = 1'b0;
                                            nx_o_data_vl = 1'b0;
                                            nx_st = ACK_COMM;
                                        end
                                end
                        end
            ACK_COMM :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_go = 1'b0;
                                    if (comm_slv[0])
                                        begin
                                            nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                            nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                            nx_st = WR;
                                        end
                                    else nx_o_sda = 1'b1;
                                end
                            if (I_RS_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b0;
                                    nx_st = IDLE;
                                end
                            if (I_FL_IO_SCL & !go)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_st = ADDR_REG;
                                end
                        end
            ADDR_REG :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_o_addr_reg = buff_rd;
                                    nx_addr_reg_offset = {DATA_SZ{1'b0}};
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = ack_from_slave;
                                            nx_go = 1'b1;
                                            nx_st = ACK_DATA;
                                        end
                                end
                        end
            ACK_DATA :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_go = 1'b0;
                                    nx_o_sda = 1'b1;
                                end
                            if (I_RS_IO_SDA & I_SCL)
                                begin
                                    nx_o_busy = 1'b0;
                                    nx_pr_addr_reg = O_ADDR_REG;
                                    nx_pr_comm_slv = comm_slv;
                                    nx_st = IDLE;
                                end
                            if (I_FL_IO_SCL & !go)
                                begin
                                    if (comm_slv[0])
                                        begin
                                            nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                            nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                            nx_st = WR;
                                        end
                                    else
                                        begin
                                            nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                            nx_st = RD;
                                        end
                                end
                        end
            RD       :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    nx_buff_rd = {buff_rd[DATA_SZ-2:0], I_SDA};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    nx_o_addr_reg = &(!addr_reg_offset) ? O_ADDR_REG : addr_reg_offset;
                                    nx_o_data_rd = buff_rd;
                                    nx_o_data_vl = 1'b1;
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = ack_from_slave;
                                            nx_go = 1'b1;
                                            nx_o_data_vl = 1'b0;
                                            nx_addr_reg_offset = O_ADDR_REG + 1'b1;
                                            nx_st = ACK_DATA;
                                        end
                                end
                        end
            WR       :  begin
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_o_sda = buff_wr[DATA_SZ-1];
                                    nx_buff_wr = {buff_wr[DATA_SZ-2:0], 1'b0};
                                    nx_cnt_bit_data = cnt_bit_data - 1'b1;
                                end
                            if (&(!cnt_bit_data))
                                begin
                                    if (I_MDL_LW_IO_SCL)
                                        begin
                                            nx_cnt_bit_data = DATA_SZ - 1'b1;
                                            nx_o_sda = 1'b1;
                                            nx_st = MSTR_ACK;
                                        end
                                end
                        end
            MSTR_ACK :  begin
                            if (I_RS_IO_SCL)
                                begin
                                    if (I_SDA)
                                        begin
                                            nx_o_busy = 1'b0;
                                            nx_st = IDLE;
                                        end
                                    else
                                        begin
                                            nx_o_addr_reg = O_ADDR_REG + 1'b1;
                                            nx_o_data_vl = 1'b1;
                                        end
                                end
                            if (I_MDL_LW_IO_SCL)
                                begin
                                    nx_buff_wr = {I_DATA_WR[DATA_SZ-2:0], 1'b0};
                                    nx_o_sda = I_DATA_WR[DATA_SZ-1];
                                    nx_o_data_vl = 1'b0;
                                    nx_st = WR;
                                end
                        end
            default  :  begin
                            nx_st = IDLE;
                            nx_o_sda = 1'b1;
                            nx_o_busy = 1'b0;
                            nx_o_data_vl = 1'b0;
                            pr_comm_slv = {DATA_SZ{1'b0}};
                            nx_ack_from_slave = 1'b1;
                            nx_addr_reg_offset = {DATA_SZ{1'b0}};
                        end
        endcase
    end


    always @(posedge CLK or negedge RST_n) begin
        if (!RST_n)
            begin
                st              <= IDLE;
                O_ADDR_SLV      <= {DATA_SZ-1{1'b0}};
                O_RW            <= 1'b0;
                O_ADDR_REG      <= {DATA_SZ{1'b0}};
                O_DATA_RD       <= {DATA_SZ{1'b0}};
                O_SDA           <= 1'b1;
                O_BUSY          <= 1'b0;
                O_CH_CNCT       <= 1'b0;
                O_DATA_VL       <= 1'b0;
                buff_rd         <= {DATA_SZ{1'b0}};
                buff_wr         <= {DATA_SZ{1'b0}};
                cnt_bit_data    <= {CNT_BIT_DATA_SZ{1'b0}};
                comm_slv        <= {DATA_SZ{1'b0}};
                pr_comm_slv     <= {DATA_SZ{1'b0}};
                pr_addr_reg     <= {DATA_SZ{1'b0}};
                addr_reg_offset <= {DATA_SZ{1'b0}};
                ack_from_slave  <= 1'b1;
                go              <= 1'b0;
            end
        else
            begin
                st              <= nx_st;
                O_ADDR_SLV      <= nx_o_addr_slv;
                O_RW            <= nx_o_rw;
                O_ADDR_REG      <= nx_o_addr_reg;
                O_DATA_RD       <= nx_o_data_rd;
                O_SDA           <= nx_o_sda;
                O_BUSY          <= nx_o_busy;
                O_CH_CNCT       <= nx_o_ch_cnct;
                O_DATA_VL       <= nx_o_data_vl;
                buff_rd         <= nx_buff_rd;
                buff_wr         <= nx_buff_wr;
                cnt_bit_data    <= nx_cnt_bit_data;
                comm_slv        <= nx_comm_slv;
                pr_comm_slv     <= nx_pr_comm_slv;
                pr_addr_reg     <= nx_pr_addr_reg;
                addr_reg_offset <= nx_addr_reg_offset;
                ack_from_slave  <= nx_ack_from_slave;
                go              <= nx_go;
            end
    end


endmodule