data/full_repos/permissive/509809169/Verilog Language/Procedures/Avoiding latches.v
1: b'%Error: Cannot find file containing module: Language/Procedures,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Procedures,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Procedures,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Procedures,data/full_repos/permissive/509809169.sv\n             Language/Procedures,data/full_repos/permissive/509809169\n             Language/Procedures,data/full_repos/permissive/509809169.v\n             Language/Procedures,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Procedures,data/full_repos/permissive/509809169\n             obj_dir/Language/Procedures,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Procedures,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Procedures/Avoiding\n%Error: Cannot find file containing module: latches.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 

    always @(*) begin
        up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
        case (scancode)
            16'he06b: left=1;
            16'he072: down=1;
            16'he074: right=1;
            16'he075: up=1;
        endcase
    end
endmodule
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  );
 

    always @(*) begin
        up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
        case (scancode)
            16'he06b: left=1;
            16'he072: down=1;
            16'he074: right=1;
            16'he075: up=1;
        endcase
    end
endmodule