data/full_repos/permissive/439731184/ft.v
1: b'%Error: data/full_repos/permissive/439731184/ft.v:196: Unsupported or unknown PLI call: $urandom\n    i1 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:197: Unsupported or unknown PLI call: $urandom\n    i2 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:198: Unsupported or unknown PLI call: $urandom\n    i3 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:199: Unsupported or unknown PLI call: $urandom\n    i4 = $urandom;\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:195: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/ft.v:204: Unsupported or unknown PLI call: $monitor\n    $monitor("(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ft4_tb();

parameter N_BITS = 8;

reg [2*N_BITS-1:0] i1 = 16'b0000001100010000;
reg [2*N_BITS-1:0] i2 = 16'b0000000100010000;
reg [2*N_BITS-1:0] i3 = 16'b0000000100010000;
reg [2*N_BITS-1:0] i4 = 16'b0000000100010000;
wire [2*N_BITS+3:0] o1;
wire [2*N_BITS+3:0] o2;
wire [2*N_BITS+3:0] o3;
wire [2*N_BITS+3:0] o4;

ft4 #(N_BITS) F (i1, i2, i3, i4, 
                 o1, o2, o3, o4);

always #1 begin
    i1 = $urandom;
    i2 = $urandom;
    i3 = $urandom;
    i4 = $urandom;
end

initial begin
    $display("input \t\toutput");
    $monitor("(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n", 
             i1[2*N_BITS-1:N_BITS], i1[N_BITS-1:0], 
             o1[2*N_BITS+3:N_BITS+2], o1[N_BITS+1:0], 
             i2[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], 
             o2[2*N_BITS+3:N_BITS+2], o2[N_BITS+1:0], 
             i3[2*N_BITS-1:N_BITS], i3[N_BITS-1:0], 
             o3[2*N_BITS+3:N_BITS+2], o3[N_BITS+1:0], 
             i4[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], 
             o4[2*N_BITS+3:N_BITS+2], o4[N_BITS+1:0]);
    #100 $finish;
end

endmodule
module ft4_tb();


parameter N_BITS = 8;

reg [2*N_BITS-1:0] i1 = 16'b0000001100010000;
reg [2*N_BITS-1:0] i2 = 16'b0000000100010000;
reg [2*N_BITS-1:0] i3 = 16'b0000000100010000;
reg [2*N_BITS-1:0] i4 = 16'b0000000100010000;
wire [2*N_BITS+3:0] o1;
wire [2*N_BITS+3:0] o2;
wire [2*N_BITS+3:0] o3;
wire [2*N_BITS+3:0] o4;

ft4 #(N_BITS) F (i1, i2, i3, i4, 
                 o1, o2, o3, o4);

always #1 begin
    i1 = $urandom;
    i2 = $urandom;
    i3 = $urandom;
    i4 = $urandom;
end

initial begin
    $display("input \t\toutput");
    $monitor("(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n(%d,%d)\t(%d,%d)\n", 
             i1[2*N_BITS-1:N_BITS], i1[N_BITS-1:0], 
             o1[2*N_BITS+3:N_BITS+2], o1[N_BITS+1:0], 
             i2[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], 
             o2[2*N_BITS+3:N_BITS+2], o2[N_BITS+1:0], 
             i3[2*N_BITS-1:N_BITS], i3[N_BITS-1:0], 
             o3[2*N_BITS+3:N_BITS+2], o3[N_BITS+1:0], 
             i4[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], 
             o4[2*N_BITS+3:N_BITS+2], o4[N_BITS+1:0]);
    #100 $finish;
end

endmodule