data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:143: Little bit endian vector: MSB < LSB of bit range: 31:32\n  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_awaddr;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:144: Little bit endian vector: MSB < LSB of bit range: 31:32\n  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_araddr;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:156: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                                                                            : ... In instance riffa_axi_lite\n    m_axi_lite_arprot = 2\'b0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:157: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                                                                            : ... In instance riffa_axi_lite\n    m_axi_lite_awprot = 2\'b0;\n                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:324: Cannot find file containing module: \'axis_fifo_2clk_32d_4u\'\n  axis_fifo_2clk_32d_4u aw_fifo (\n  ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/axis_fifo_2clk_32d_4u\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/axis_fifo_2clk_32d_4u.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/axis_fifo_2clk_32d_4u.sv\n             axis_fifo_2clk_32d_4u\n             axis_fifo_2clk_32d_4u.v\n             axis_fifo_2clk_32d_4u.sv\n             obj_dir/axis_fifo_2clk_32d_4u\n             obj_dir/axis_fifo_2clk_32d_4u.v\n             obj_dir/axis_fifo_2clk_32d_4u.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:339: Cannot find file containing module: \'axis_fifo_2clk_32d_4u\'\n  axis_fifo_2clk_32d_4u w_fifo (\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:354: Cannot find file containing module: \'axis_fifo_2clk_32d_4u\'\n  axis_fifo_2clk_32d_4u ar_fifo (\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:369: Cannot find file containing module: \'axis_fifo_2clk_32d_4u\'\n  axis_fifo_2clk_32d_4u r_fifo (\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/riffa_axi_lite.sv:384: Cannot find file containing module: \'axis_fifo_2clk_32d_4u\'\n  axis_fifo_2clk_32d_4u tag_fifo (\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module riffa_axi_lite #(
  parameter integer C_PCI_DATA_WIDTH = 128,
  parameter integer C_M_AXI_LITE_ADDR_WIDTH = 32,
  parameter integer C_M_AXI_LITE_DATA_WIDTH = 32,
  parameter integer C_M_AXI_LITE_STRB_WIDTH = C_M_AXI_LITE_DATA_WIDTH/8
)
(
  input  wire                               CLK,
  input  wire                               RST,
  output wire                               CHNL_RX_CLK, 
  input  wire                               CHNL_RX, 
  output wire                               CHNL_RX_ACK, 
  input  wire                               CHNL_RX_LAST, 
  input  wire [31:0]                        CHNL_RX_LEN, 
  input  wire [30:0]                        CHNL_RX_OFF, 
  input  wire [C_PCI_DATA_WIDTH-1:0]        CHNL_RX_DATA, 
  input  wire                               CHNL_RX_DATA_VALID, 
  output wire                               CHNL_RX_DATA_REN,
  
  output wire                               CHNL_TX_CLK, 
  output wire                               CHNL_TX, 
  input  wire                               CHNL_TX_ACK, 
  output wire                               CHNL_TX_LAST, 
  output wire [31:0]                        CHNL_TX_LEN, 
  output wire [30:0]                        CHNL_TX_OFF, 
  output wire [C_PCI_DATA_WIDTH-1:0]        CHNL_TX_DATA, 
  output wire                               CHNL_TX_DATA_VALID, 
  input  wire                               CHNL_TX_DATA_REN,
  
  input  wire                               m_axi_lite_aclk,
  input  wire                               m_axi_lite_aresetn,

  input  wire                               m_axi_lite_arready,
  output reg                                m_axi_lite_arvalid,
  output reg [C_M_AXI_LITE_ADDR_WIDTH-1:0]  m_axi_lite_araddr,
  output reg [2:0]                          m_axi_lite_arprot,


  output reg                                m_axi_lite_rready,
  input  wire                               m_axi_lite_rvalid,
  input  wire [C_M_AXI_LITE_DATA_WIDTH-1:0] m_axi_lite_rdata,
  input  wire [1:0]                         m_axi_lite_rresp,
      

  input  wire                               m_axi_lite_awready,
  output reg                                m_axi_lite_awvalid,
  output reg [C_M_AXI_LITE_ADDR_WIDTH-1:0]  m_axi_lite_awaddr,
  output reg [2:0]                          m_axi_lite_awprot,


  input  wire                               m_axi_lite_wready,
  output reg                                m_axi_lite_wvalid,
  output reg [C_M_AXI_LITE_DATA_WIDTH-1:0]  m_axi_lite_wdata,
  output reg [C_M_AXI_LITE_STRB_WIDTH-1:0]  m_axi_lite_wstrb,
  

  output reg                                m_axi_lite_bready,
  input  wire                               m_axi_lite_bvalid,
  input  wire [1:0]                         m_axi_lite_bresp,

  output reg                                md_error
);

  wire          reset_n;
  
  wire          w_s_tready;  
  reg           w_s_tvalid;  

  wire          aw_s_tready;
  reg           aw_s_tvalid;
  
  wire          ar_s_tready;
  reg           ar_s_tvalid;  
  
  wire          r_m_tvalid;
  reg           r_m_tready;
  wire [31:0]   r_m_tdata;
  wire [3:0]    r_m_tuser;
  
  reg           tag_s_tvalid;
  wire          tag_s_tready;
  wire [31:0]   tag_s_tdata;

  wire          tag_m_tvalid;
  reg           tag_m_tready;
  wire [31:0]   tag_m_tdata;

  reg [31:0]    req_addr;
  reg [31:0]    req_tag;
  reg [31:0]    req_data;
  reg [3:0]     req_strb;

  reg           valid_rd_req;
  reg           valid_wr_req; 
  reg           data_available;
  reg [127:0]   tx_data;

  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_awaddr;
  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_araddr;
  
  enum {S_RX_RESET, S_RX_WAIT_FOR_REQ, S_RX_STORE_RD_REQ, S_RX_STORE_WR_REQ} rx_state;  
  enum {S_TX_RESET, S_TX_WAIT_FOR_DATA, S_TX_SEND_HDR, S_TX_SEND_DATA} tx_state;
  




  assign reset_n = ~RST;    

  always_comb begin
    m_axi_lite_arprot = 2'b0;
    m_axi_lite_awprot = 2'b0;
    m_axi_lite_bready = 1'b1;
    md_error = 1'b0;
  end
  
  assign CHNL_TX_CLK = CLK;
  assign CHNL_RX_CLK = CLK;  
   



  
  assign CHNL_RX_ACK = 1'b1; 
  

  always_comb begin

    valid_rd_req = 0;
    if ((CHNL_RX_DATA[`REQ_TYPE_RANGE] == `C_RD_REQ) && CHNL_RX_DATA_VALID) begin
      valid_rd_req = 1;
    end
    
    valid_wr_req = 0;
    if ((CHNL_RX_DATA[`REQ_TYPE_RANGE] == `C_WR_REQ) && CHNL_RX_DATA_VALID) begin
      valid_wr_req = 1;
    end
  end
  

  always_ff @(posedge CLK, negedge reset_n) begin
    if (!reset_n) begin
      rx_state <= S_RX_RESET;
    end else begin
      case (rx_state)      

        S_RX_RESET: begin
          rx_state <= S_RX_WAIT_FOR_REQ;
        end

        S_RX_WAIT_FOR_REQ: begin
          if (valid_rd_req) begin
            rx_state <= S_RX_STORE_RD_REQ;
          end else if (valid_wr_req) begin
            rx_state <= S_RX_STORE_WR_REQ;
          end
        end

        S_RX_STORE_WR_REQ: begin
          if (aw_s_tready && w_s_tready) begin
            rx_state <= S_RX_WAIT_FOR_REQ;
          end
        end  

        S_RX_STORE_RD_REQ: begin
          if (ar_s_tready && tag_s_tready) begin
            rx_state <= S_RX_WAIT_FOR_REQ;
          end
        end

      endcase
    end
  end

  assign CHNL_RX_DATA_REN = (rx_state==S_RX_WAIT_FOR_REQ) ? 1 : 0;
  
  always_ff @(posedge CLK) begin
    if ((rx_state==S_RX_WAIT_FOR_REQ) && (valid_rd_req || valid_wr_req)) begin
      req_addr = CHNL_RX_DATA[`ADDR_RANGE];
      req_data = CHNL_RX_DATA[`DATA_RANGE];
      req_tag = CHNL_RX_DATA[`TAG_RANGE];
      req_strb = CHNL_RX_DATA[`STRB_RANGE];
    end
  end
    
  always_comb begin

    aw_s_tvalid = 0;
    w_s_tvalid = 0;
    if (rx_state==S_RX_STORE_WR_REQ) begin
      aw_s_tvalid = 1;
      w_s_tvalid = 1;
    end  

    ar_s_tvalid = 0;
    tag_s_tvalid = 0;
    if (rx_state==S_RX_STORE_RD_REQ) begin
      ar_s_tvalid = 1;
      tag_s_tvalid = 1;
    end     
  end

  assign tag_s_tdata = req_tag;

  



  
  always_comb begin
    data_available = 0;
    if (r_m_tvalid && tag_m_tvalid) begin
      data_available = 1;
    end
  end  
  
  always_ff @(posedge CLK, negedge reset_n) begin
    if (!reset_n) begin
      tx_state <= S_TX_RESET;
    end else begin
      case (tx_state)       

        S_TX_RESET: begin
          tx_state <= S_TX_WAIT_FOR_DATA;
        end

        S_TX_WAIT_FOR_DATA: begin
          if (data_available) begin
            tx_state <= S_TX_SEND_HDR;
          end
        end

        S_TX_SEND_HDR: begin
          if (CHNL_TX_ACK) begin
            tx_state <= S_TX_SEND_DATA;
          end
        end

        S_TX_SEND_DATA: begin
          if (CHNL_TX_DATA_REN) begin
            tx_state <= S_TX_WAIT_FOR_DATA;
          end
        end
      endcase
    end
  end    
  
  always_comb begin
    r_m_tready = 0;
    tag_m_tready = 0;
    if (data_available) begin
      r_m_tready = 1;
      tag_m_tready = 1;
    end
  end

  assign CHNL_TX = (tx_state==S_TX_SEND_HDR) ? 1 : 0;
  assign CHNL_TX_LAST = 1'b1; 
  assign CHNL_TX_LEN = 32'd4;
  assign CHNL_TX_OFF = 31'd0;

  assign CHNL_TX_DATA_VALID = (tx_state==S_TX_SEND_DATA) ? 1 : 0;
  
  always_ff @(posedge CLK) begin
    if ((tx_state==S_TX_WAIT_FOR_DATA) && data_available) begin
      tx_data = 128'b0;
      tx_data[`RESP_RANGE] = r_m_tuser[1:0];
      tx_data[`TAG_RANGE] = tag_m_tdata;
      tx_data[`DATA_RANGE] = r_m_tdata;
    end
  end

  assign CHNL_TX_DATA = tx_data;
  



  
  axis_fifo_2clk_32d_4u aw_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (aw_s_tvalid),
    .s_axis_tready    (aw_s_tready),
    .s_axis_tdata     (req_addr),
    .s_axis_tuser     (4'b0),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_awvalid),
    .m_axis_tready    (m_axi_lite_awready),
    .m_axis_tdata     ({dummy_awaddr,m_axi_lite_awaddr}),
    .m_axis_tuser     ()
  );
  
  axis_fifo_2clk_32d_4u w_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (w_s_tvalid),
    .s_axis_tready    (w_s_tready),
    .s_axis_tdata     (req_data),
    .s_axis_tuser     (req_strb),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_wvalid),
    .m_axis_tready    (m_axi_lite_wready),
    .m_axis_tdata     (m_axi_lite_wdata),
    .m_axis_tuser     (m_axi_lite_wstrb)
  );
  
  axis_fifo_2clk_32d_4u ar_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (ar_s_tvalid),
    .s_axis_tready    (ar_s_tready),
    .s_axis_tdata     (req_addr),
    .s_axis_tuser     (4'b0),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_arvalid),
    .m_axis_tready    (m_axi_lite_arready),
    .m_axis_tdata     ({dummy_araddr,m_axi_lite_araddr}),
    .m_axis_tuser     ()
  );
  
  axis_fifo_2clk_32d_4u r_fifo (
    .s_aclk           (m_axi_lite_aclk),
    .s_aresetn        (m_axi_lite_aresetn),
    .s_axis_tvalid    (m_axi_lite_rvalid),
    .s_axis_tready    (m_axi_lite_rready),
    .s_axis_tdata     (m_axi_lite_rdata),
    .s_axis_tuser     ({2'b0,m_axi_lite_rresp}),

    .m_aclk           (CLK),
    .m_axis_tvalid    (r_m_tvalid),
    .m_axis_tready    (r_m_tready),
    .m_axis_tdata     (r_m_tdata),
    .m_axis_tuser     (r_m_tuser)
  );
  
  axis_fifo_2clk_32d_4u tag_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (tag_s_tvalid),
    .s_axis_tready    (tag_s_tready),
    .s_axis_tdata     (tag_s_tdata),
    .s_axis_tuser     (4'b0),

    .m_aclk           (CLK),
    .m_axis_tvalid    (tag_m_tvalid),
    .m_axis_tready    (tag_m_tready),
    .m_axis_tdata     (tag_m_tdata),
    .m_axis_tuser     ()
  );

endmodule
module riffa_axi_lite #(
  parameter integer C_PCI_DATA_WIDTH = 128,
  parameter integer C_M_AXI_LITE_ADDR_WIDTH = 32,
  parameter integer C_M_AXI_LITE_DATA_WIDTH = 32,
  parameter integer C_M_AXI_LITE_STRB_WIDTH = C_M_AXI_LITE_DATA_WIDTH/8
)
(
  input  wire                               CLK,
  input  wire                               RST,
  output wire                               CHNL_RX_CLK, 
  input  wire                               CHNL_RX, 
  output wire                               CHNL_RX_ACK, 
  input  wire                               CHNL_RX_LAST, 
  input  wire [31:0]                        CHNL_RX_LEN, 
  input  wire [30:0]                        CHNL_RX_OFF, 
  input  wire [C_PCI_DATA_WIDTH-1:0]        CHNL_RX_DATA, 
  input  wire                               CHNL_RX_DATA_VALID, 
  output wire                               CHNL_RX_DATA_REN,
  
  output wire                               CHNL_TX_CLK, 
  output wire                               CHNL_TX, 
  input  wire                               CHNL_TX_ACK, 
  output wire                               CHNL_TX_LAST, 
  output wire [31:0]                        CHNL_TX_LEN, 
  output wire [30:0]                        CHNL_TX_OFF, 
  output wire [C_PCI_DATA_WIDTH-1:0]        CHNL_TX_DATA, 
  output wire                               CHNL_TX_DATA_VALID, 
  input  wire                               CHNL_TX_DATA_REN,
  
  input  wire                               m_axi_lite_aclk,
  input  wire                               m_axi_lite_aresetn,

  input  wire                               m_axi_lite_arready,
  output reg                                m_axi_lite_arvalid,
  output reg [C_M_AXI_LITE_ADDR_WIDTH-1:0]  m_axi_lite_araddr,
  output reg [2:0]                          m_axi_lite_arprot,


  output reg                                m_axi_lite_rready,
  input  wire                               m_axi_lite_rvalid,
  input  wire [C_M_AXI_LITE_DATA_WIDTH-1:0] m_axi_lite_rdata,
  input  wire [1:0]                         m_axi_lite_rresp,
      

  input  wire                               m_axi_lite_awready,
  output reg                                m_axi_lite_awvalid,
  output reg [C_M_AXI_LITE_ADDR_WIDTH-1:0]  m_axi_lite_awaddr,
  output reg [2:0]                          m_axi_lite_awprot,


  input  wire                               m_axi_lite_wready,
  output reg                                m_axi_lite_wvalid,
  output reg [C_M_AXI_LITE_DATA_WIDTH-1:0]  m_axi_lite_wdata,
  output reg [C_M_AXI_LITE_STRB_WIDTH-1:0]  m_axi_lite_wstrb,
  

  output reg                                m_axi_lite_bready,
  input  wire                               m_axi_lite_bvalid,
  input  wire [1:0]                         m_axi_lite_bresp,

  output reg                                md_error
);


  wire          reset_n;
  
  wire          w_s_tready;  
  reg           w_s_tvalid;  

  wire          aw_s_tready;
  reg           aw_s_tvalid;
  
  wire          ar_s_tready;
  reg           ar_s_tvalid;  
  
  wire          r_m_tvalid;
  reg           r_m_tready;
  wire [31:0]   r_m_tdata;
  wire [3:0]    r_m_tuser;
  
  reg           tag_s_tvalid;
  wire          tag_s_tready;
  wire [31:0]   tag_s_tdata;

  wire          tag_m_tvalid;
  reg           tag_m_tready;
  wire [31:0]   tag_m_tdata;

  reg [31:0]    req_addr;
  reg [31:0]    req_tag;
  reg [31:0]    req_data;
  reg [3:0]     req_strb;

  reg           valid_rd_req;
  reg           valid_wr_req; 
  reg           data_available;
  reg [127:0]   tx_data;

  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_awaddr;
  wire [31:C_M_AXI_LITE_ADDR_WIDTH] dummy_araddr;
  
  enum {S_RX_RESET, S_RX_WAIT_FOR_REQ, S_RX_STORE_RD_REQ, S_RX_STORE_WR_REQ} rx_state;  
  enum {S_TX_RESET, S_TX_WAIT_FOR_DATA, S_TX_SEND_HDR, S_TX_SEND_DATA} tx_state;
  




  assign reset_n = ~RST;    

  always_comb begin
    m_axi_lite_arprot = 2'b0;
    m_axi_lite_awprot = 2'b0;
    m_axi_lite_bready = 1'b1;
    md_error = 1'b0;
  end
  
  assign CHNL_TX_CLK = CLK;
  assign CHNL_RX_CLK = CLK;  
   



  
  assign CHNL_RX_ACK = 1'b1; 
  

  always_comb begin

    valid_rd_req = 0;
    if ((CHNL_RX_DATA[`REQ_TYPE_RANGE] == `C_RD_REQ) && CHNL_RX_DATA_VALID) begin
      valid_rd_req = 1;
    end
    
    valid_wr_req = 0;
    if ((CHNL_RX_DATA[`REQ_TYPE_RANGE] == `C_WR_REQ) && CHNL_RX_DATA_VALID) begin
      valid_wr_req = 1;
    end
  end
  

  always_ff @(posedge CLK, negedge reset_n) begin
    if (!reset_n) begin
      rx_state <= S_RX_RESET;
    end else begin
      case (rx_state)      

        S_RX_RESET: begin
          rx_state <= S_RX_WAIT_FOR_REQ;
        end

        S_RX_WAIT_FOR_REQ: begin
          if (valid_rd_req) begin
            rx_state <= S_RX_STORE_RD_REQ;
          end else if (valid_wr_req) begin
            rx_state <= S_RX_STORE_WR_REQ;
          end
        end

        S_RX_STORE_WR_REQ: begin
          if (aw_s_tready && w_s_tready) begin
            rx_state <= S_RX_WAIT_FOR_REQ;
          end
        end  

        S_RX_STORE_RD_REQ: begin
          if (ar_s_tready && tag_s_tready) begin
            rx_state <= S_RX_WAIT_FOR_REQ;
          end
        end

      endcase
    end
  end

  assign CHNL_RX_DATA_REN = (rx_state==S_RX_WAIT_FOR_REQ) ? 1 : 0;
  
  always_ff @(posedge CLK) begin
    if ((rx_state==S_RX_WAIT_FOR_REQ) && (valid_rd_req || valid_wr_req)) begin
      req_addr = CHNL_RX_DATA[`ADDR_RANGE];
      req_data = CHNL_RX_DATA[`DATA_RANGE];
      req_tag = CHNL_RX_DATA[`TAG_RANGE];
      req_strb = CHNL_RX_DATA[`STRB_RANGE];
    end
  end
    
  always_comb begin

    aw_s_tvalid = 0;
    w_s_tvalid = 0;
    if (rx_state==S_RX_STORE_WR_REQ) begin
      aw_s_tvalid = 1;
      w_s_tvalid = 1;
    end  

    ar_s_tvalid = 0;
    tag_s_tvalid = 0;
    if (rx_state==S_RX_STORE_RD_REQ) begin
      ar_s_tvalid = 1;
      tag_s_tvalid = 1;
    end     
  end

  assign tag_s_tdata = req_tag;

  



  
  always_comb begin
    data_available = 0;
    if (r_m_tvalid && tag_m_tvalid) begin
      data_available = 1;
    end
  end  
  
  always_ff @(posedge CLK, negedge reset_n) begin
    if (!reset_n) begin
      tx_state <= S_TX_RESET;
    end else begin
      case (tx_state)       

        S_TX_RESET: begin
          tx_state <= S_TX_WAIT_FOR_DATA;
        end

        S_TX_WAIT_FOR_DATA: begin
          if (data_available) begin
            tx_state <= S_TX_SEND_HDR;
          end
        end

        S_TX_SEND_HDR: begin
          if (CHNL_TX_ACK) begin
            tx_state <= S_TX_SEND_DATA;
          end
        end

        S_TX_SEND_DATA: begin
          if (CHNL_TX_DATA_REN) begin
            tx_state <= S_TX_WAIT_FOR_DATA;
          end
        end
      endcase
    end
  end    
  
  always_comb begin
    r_m_tready = 0;
    tag_m_tready = 0;
    if (data_available) begin
      r_m_tready = 1;
      tag_m_tready = 1;
    end
  end

  assign CHNL_TX = (tx_state==S_TX_SEND_HDR) ? 1 : 0;
  assign CHNL_TX_LAST = 1'b1; 
  assign CHNL_TX_LEN = 32'd4;
  assign CHNL_TX_OFF = 31'd0;

  assign CHNL_TX_DATA_VALID = (tx_state==S_TX_SEND_DATA) ? 1 : 0;
  
  always_ff @(posedge CLK) begin
    if ((tx_state==S_TX_WAIT_FOR_DATA) && data_available) begin
      tx_data = 128'b0;
      tx_data[`RESP_RANGE] = r_m_tuser[1:0];
      tx_data[`TAG_RANGE] = tag_m_tdata;
      tx_data[`DATA_RANGE] = r_m_tdata;
    end
  end

  assign CHNL_TX_DATA = tx_data;
  



  
  axis_fifo_2clk_32d_4u aw_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (aw_s_tvalid),
    .s_axis_tready    (aw_s_tready),
    .s_axis_tdata     (req_addr),
    .s_axis_tuser     (4'b0),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_awvalid),
    .m_axis_tready    (m_axi_lite_awready),
    .m_axis_tdata     ({dummy_awaddr,m_axi_lite_awaddr}),
    .m_axis_tuser     ()
  );
  
  axis_fifo_2clk_32d_4u w_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (w_s_tvalid),
    .s_axis_tready    (w_s_tready),
    .s_axis_tdata     (req_data),
    .s_axis_tuser     (req_strb),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_wvalid),
    .m_axis_tready    (m_axi_lite_wready),
    .m_axis_tdata     (m_axi_lite_wdata),
    .m_axis_tuser     (m_axi_lite_wstrb)
  );
  
  axis_fifo_2clk_32d_4u ar_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (ar_s_tvalid),
    .s_axis_tready    (ar_s_tready),
    .s_axis_tdata     (req_addr),
    .s_axis_tuser     (4'b0),

    .m_aclk           (m_axi_lite_aclk),
    .m_axis_tvalid    (m_axi_lite_arvalid),
    .m_axis_tready    (m_axi_lite_arready),
    .m_axis_tdata     ({dummy_araddr,m_axi_lite_araddr}),
    .m_axis_tuser     ()
  );
  
  axis_fifo_2clk_32d_4u r_fifo (
    .s_aclk           (m_axi_lite_aclk),
    .s_aresetn        (m_axi_lite_aresetn),
    .s_axis_tvalid    (m_axi_lite_rvalid),
    .s_axis_tready    (m_axi_lite_rready),
    .s_axis_tdata     (m_axi_lite_rdata),
    .s_axis_tuser     ({2'b0,m_axi_lite_rresp}),

    .m_aclk           (CLK),
    .m_axis_tvalid    (r_m_tvalid),
    .m_axis_tready    (r_m_tready),
    .m_axis_tdata     (r_m_tdata),
    .m_axis_tuser     (r_m_tuser)
  );
  
  axis_fifo_2clk_32d_4u tag_fifo (
    .s_aclk           (CLK),
    .s_aresetn        (reset_n),
    .s_axis_tvalid    (tag_s_tvalid),
    .s_axis_tready    (tag_s_tready),
    .s_axis_tdata     (tag_s_tdata),
    .s_axis_tuser     (4'b0),

    .m_aclk           (CLK),
    .m_axis_tvalid    (tag_m_tvalid),
    .m_axis_tready    (tag_m_tready),
    .m_axis_tdata     (tag_m_tdata),
    .m_axis_tuser     ()
  );

endmodule