data/full_repos/permissive/451577625/system/alu_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hF0F0F0F0; in_b = 32\'hABCDABCD; opcode = 4\'b1011;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h00000001; in_b = 32\'h1; opcode = 4\'b1010;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hFFFFFFFF; in_b = 32\'h0F0F0F0F; opcode = 4\'b0110;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hF0F0F0F0; in_b = 32\'h0F0F0F0F; opcode = 4\'b0111;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0000FFFF; in_b = 32\'h00000001; opcode = 4\'b0000;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0000FFFF; in_b = 32\'h000000FF; opcode = 4\'b0001;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hFFFFFFF3; in_b = 32\'hB; opcode = 4\'b1000;   \n  ^\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/alu_32.v:114: Cell has missing pin: \'clk\'\n alu_32 DUT(.in_a (in_a),\n        ^~~\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/alu_32.v:114: Cell has missing pin: \'in_div_reset\'\n alu_32 DUT(.in_a (in_a),\n        ^~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:37: Cannot find file containing module: \'adder_32\'\n adder_32 adder(.in_x (r_a_pre_process),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:43: Cannot find file containing module: \'shift_rot_32\'\n shift_rot_32 shifter (.in_x (in_a),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:49: Cannot find file containing module: \'multiplier_32\'\n multiplier_32 multiplier (.in_x (in_a),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:53: Cannot find file containing module: \'divider_32\'\n divider_32 divider (.clk (clk),\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:90: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_adder_sum_out\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b1011 : out_result = w_adder_sum_out;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:94: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_shift_rot_out\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0101 : out_result = w_shift_rot_out;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:95: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_and_32\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0110 : out_result = w_and_32;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:96: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_or_32\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0111 : out_result = w_or_32;   \n                        ^\n%Error: Exiting due to 4 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_32_tb;
	reg [31:0] in_a, in_b;
	reg [3:0] opcode;
	wire [63:0] alu_out;
	
	parameter delay = 10;
	
	alu_32 DUT(.in_a (in_a),
		.in_b (in_b),
		.in_opcode (opcode),
		.out_result (alu_out));
	
	initial begin
		in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hF0F0F0F0; in_b = 32'hABCDABCD; opcode = 4'b1011;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h00000001; in_b = 32'h1; opcode = 4'b1010;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hFFFFFFFF; in_b = 32'h0F0F0F0F; opcode = 4'b0110;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hF0F0F0F0; in_b = 32'h0F0F0F0F; opcode = 4'b0111;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h0000FFFF; in_b = 32'h00000001; opcode = 4'b0000;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h0000FFFF; in_b = 32'h000000FF; opcode = 4'b0001;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hFFFFFFF3; in_b = 32'hB; opcode = 4'b1000;


	end
	
endmodule
module alu_32_tb;

	reg [31:0] in_a, in_b;
	reg [3:0] opcode;
	wire [63:0] alu_out;
	
	parameter delay = 10;
	
	alu_32 DUT(.in_a (in_a),
		.in_b (in_b),
		.in_opcode (opcode),
		.out_result (alu_out));
	
	initial begin
		in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hF0F0F0F0; in_b = 32'hABCDABCD; opcode = 4'b1011;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h00000001; in_b = 32'h1; opcode = 4'b1010;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hFFFFFFFF; in_b = 32'h0F0F0F0F; opcode = 4'b0110;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hF0F0F0F0; in_b = 32'h0F0F0F0F; opcode = 4'b0111;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h0000FFFF; in_b = 32'h00000001; opcode = 4'b0000;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'h0000FFFF; in_b = 32'h000000FF; opcode = 4'b0001;
		#(delay) in_a = 32'h0; in_b = 32'h0; opcode = 4'b0;
		#(delay) in_a = 32'hFFFFFFF3; in_b = 32'hB; opcode = 4'b1000;


	end
	
endmodule