data/full_repos/permissive/428611613/cores/port_selector_v1_0/port_selector.v
data/verilator_xmls/7d16681a-bb5c-4d80-9a22-6f3900bb81af.xml
module port_selector #
(
  parameter integer DOUT_WIDTH = 32
)
(
  input  wire                    cfg,
  input  wire [2*DOUT_WIDTH-1:0] din,
  output wire [DOUT_WIDTH-1:0]   dout
);

  assign dout = cfg ? din[2*DOUT_WIDTH-1:DOUT_WIDTH] : din[DOUT_WIDTH-1:0];

endmodule
module port_selector #
(
  parameter integer DOUT_WIDTH = 32
)
(
  input  wire                    cfg,
  input  wire [2*DOUT_WIDTH-1:0] din,
  output wire [DOUT_WIDTH-1:0]   dout
);


  assign dout = cfg ? din[2*DOUT_WIDTH-1:DOUT_WIDTH] : din[DOUT_WIDTH-1:0];

endmodule