data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v
1: b'%Error: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:36: Cannot find file containing module: \'shift_register\'\n shift_register #(BITS, WIDTH, 2) linebuffer(pclk, in_href, in_raw, shiftout, {tap1x, tap0x});\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_register\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_register.v\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_register.sv\n             shift_register\n             shift_register.v\n             shift_register.sv\n             obj_dir/shift_register\n             obj_dir/shift_register.v\n             obj_dir/shift_register.sv\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:203: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p11\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: r = (p11 + p13 + p31 + p33) >> 2;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:203: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p13\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: r = (p11 + p13 + p31 + p33) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:203: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p31\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: r = (p11 + p13 + p31 + p33) >> 2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:203: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p33\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: r = (p11 + p13 + p31 + p33) >> 2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:204: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p12\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b01: r = (p12 + p32) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:204: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p32\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b01: r = (p12 + p32) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:205: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p21\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b10: r = (p21 + p23) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:205: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p23\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b10: r = (p21 + p23) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:206: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'p22\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: r = p22;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:207: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    default: r = {BITS{1\'b0}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:209: Operator GT expects 10 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n   raw2r = r > {BITS{1\'b1}} ? {BITS{1\'b1}} : r[BITS-1:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:221: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p12\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: g = (p12 + p32 + p21 + p23) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:221: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p32\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: g = (p12 + p32 + p21 + p23) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:221: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p21\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: g = (p12 + p32 + p21 + p23) >> 2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:221: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p23\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: g = (p12 + p32 + p21 + p23) >> 2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:222: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'p22\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b01: g = p22;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:223: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'p22\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b10: g = p22;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:224: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p12\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: g = (p12 + p32 + p21 + p23) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:224: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p32\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: g = (p12 + p32 + p21 + p23) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:224: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p21\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: g = (p12 + p32 + p21 + p23) >> 2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:224: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p23\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: g = (p12 + p32 + p21 + p23) >> 2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:225: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    default: g = {BITS{1\'b0}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:227: Operator GT expects 10 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n   raw2g = g > {BITS{1\'b1}} ? {BITS{1\'b1}} : g[BITS-1:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:239: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'p22\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b00: b = p22;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:240: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p21\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b01: b = (p21 + p23) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:240: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p23\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b01: b = (p21 + p23) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:241: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p12\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b10: b = (p12 + p32) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:241: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p32\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b10: b = (p12 + p32) >> 1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:242: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p11\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: b = (p11 + p13 + p31 + p33) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:242: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p13\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: b = (p11 + p13 + p31 + p33) >> 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:242: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p31\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: b = (p11 + p13 + p31 + p33) >> 2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:242: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p33\' generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    2\'b11: b = (p11 + p13 + p31 + p33) >> 2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:243: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n    default: b = {BITS{1\'b0}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_demosaic.v:245: Operator GT expects 10 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                                         : ... In instance isp_demosaic\n   raw2b = b > {BITS{1\'b1}} ? {BITS{1\'b1}} : b[BITS-1:0];\n             ^\n%Error: Exiting due to 1 error(s), 34 warning(s)\n'
module isp_demosaic
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960,
	parameter BAYER = 0
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_raw,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_r,
	output [BITS-1:0] out_g,
	output [BITS-1:0] out_b
);

	wire [BITS-1:0] shiftout;
	wire [BITS-1:0] tap1x, tap0x;
	shift_register #(BITS, WIDTH, 2) linebuffer(pclk, in_href, in_raw, shiftout, {tap1x, tap0x});
	
	reg [BITS-1:0] in_raw_r;
	reg [BITS-1:0] p11,p12,p13;
	reg [BITS-1:0] p21,p22,p23;
	reg [BITS-1:0] p31,p32,p33;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			in_raw_r <= 0;
			p13 <= 0;
			p23 <= 0;
			p33 <= 0;
			p12 <= 0;
			p22 <= 0;
			p32 <= 0;
			p11 <= 0;
			p21 <= 0;
			p31 <= 0;
		end
		else begin
			in_raw_r <= in_raw;
			p11 <= p12;
			p21 <= p22;
			p31 <= p32;
			p12 <= p13;
			p22 <= p23;
			p32 <= p33;
			p13 <= tap1x;
			p23 <= tap0x;
			p33 <= in_raw_r;
		end
	end

	reg odd_pix;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n)
			odd_pix <= 0;
		else if (!in_href)
			odd_pix <= 0;
		else
			odd_pix <= ~odd_pix;
	end
	wire odd_pix_dly = ~odd_pix;
	
	reg prev_href;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) 
			prev_href <= 0;
		else
			prev_href <= in_href;
	end	
	
	reg odd_line;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) 
			odd_line <= 0;
		else if (in_vsync)
			odd_line <= 0;
		else if (prev_href & (~in_href))
			odd_line <= ~odd_line;
		else
			odd_line <= odd_line;
	end
	wire odd_line_dly = ~odd_line;

	reg [BITS-1:0] r_now, g_now, b_now;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_now <=  0;
			g_now <=  0;
			b_now <=  0;
		end
		else begin
			case (BAYER)
				0: begin
					r_now <= raw2r({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				1: begin
					r_now <= raw2r({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				2: begin
					r_now <= raw2r({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				3: begin
					r_now <= raw2r({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				default: begin
					r_now <=  0;
					g_now <=  0;
					b_now <=  0;
				end
			endcase
		end
	end

	localparam DLY_CLK = 4;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end
	
	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_r = out_href ? r_now : {BITS{1'b0}};
	assign out_g = out_href ? g_now : {BITS{1'b0}};
	assign out_b = out_href ? b_now : {BITS{1'b0}};

	function [BITS-1:0] raw2r;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] r;
		begin
			case (format)
				2'b00: r = (p11 + p13 + p31 + p33) >> 2;
				2'b01: r = (p12 + p32) >> 1;
				2'b10: r = (p21 + p23) >> 1;
				2'b11: r = p22;
				default: r = {BITS{1'b0}};
			endcase
			raw2r = r > {BITS{1'b1}} ? {BITS{1'b1}} : r[BITS-1:0];
		end
	endfunction

	function [BITS-1:0] raw2g;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] g;
		begin
			case (format)
				2'b00: g = (p12 + p32 + p21 + p23) >> 2;
				2'b01: g = p22;
				2'b10: g = p22;
				2'b11: g = (p12 + p32 + p21 + p23) >> 2;
				default: g = {BITS{1'b0}};
			endcase
			raw2g = g > {BITS{1'b1}} ? {BITS{1'b1}} : g[BITS-1:0];
		end
	endfunction

	function [BITS-1:0] raw2b;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] b;
		begin
			case (format)
				2'b00: b = p22;
				2'b01: b = (p21 + p23) >> 1;
				2'b10: b = (p12 + p32) >> 1;
				2'b11: b = (p11 + p13 + p31 + p33) >> 2;
				default: b = {BITS{1'b0}};
			endcase
			raw2b = b > {BITS{1'b1}} ? {BITS{1'b1}} : b[BITS-1:0];
		end
	endfunction
endmodule
module isp_demosaic
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960,
	parameter BAYER = 0
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_raw,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_r,
	output [BITS-1:0] out_g,
	output [BITS-1:0] out_b
);


	wire [BITS-1:0] shiftout;
	wire [BITS-1:0] tap1x, tap0x;
	shift_register #(BITS, WIDTH, 2) linebuffer(pclk, in_href, in_raw, shiftout, {tap1x, tap0x});
	
	reg [BITS-1:0] in_raw_r;
	reg [BITS-1:0] p11,p12,p13;
	reg [BITS-1:0] p21,p22,p23;
	reg [BITS-1:0] p31,p32,p33;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			in_raw_r <= 0;
			p13 <= 0;
			p23 <= 0;
			p33 <= 0;
			p12 <= 0;
			p22 <= 0;
			p32 <= 0;
			p11 <= 0;
			p21 <= 0;
			p31 <= 0;
		end
		else begin
			in_raw_r <= in_raw;
			p11 <= p12;
			p21 <= p22;
			p31 <= p32;
			p12 <= p13;
			p22 <= p23;
			p32 <= p33;
			p13 <= tap1x;
			p23 <= tap0x;
			p33 <= in_raw_r;
		end
	end

	reg odd_pix;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n)
			odd_pix <= 0;
		else if (!in_href)
			odd_pix <= 0;
		else
			odd_pix <= ~odd_pix;
	end
	wire odd_pix_dly = ~odd_pix;
	
	reg prev_href;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) 
			prev_href <= 0;
		else
			prev_href <= in_href;
	end	
	
	reg odd_line;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) 
			odd_line <= 0;
		else if (in_vsync)
			odd_line <= 0;
		else if (prev_href & (~in_href))
			odd_line <= ~odd_line;
		else
			odd_line <= odd_line;
	end
	wire odd_line_dly = ~odd_line;

	reg [BITS-1:0] r_now, g_now, b_now;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_now <=  0;
			g_now <=  0;
			b_now <=  0;
		end
		else begin
			case (BAYER)
				0: begin
					r_now <= raw2r({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				1: begin
					r_now <= raw2r({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				2: begin
					r_now <= raw2r({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({~odd_line_dly, odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				3: begin
					r_now <= raw2r({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					g_now <= raw2g({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
					b_now <= raw2b({~odd_line_dly, ~odd_pix_dly},
										p11,p12,p13,
										p21,p22,p23,
										p31,p32,p33);
				end
				default: begin
					r_now <=  0;
					g_now <=  0;
					b_now <=  0;
				end
			endcase
		end
	end

	localparam DLY_CLK = 4;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end
	
	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_r = out_href ? r_now : {BITS{1'b0}};
	assign out_g = out_href ? g_now : {BITS{1'b0}};
	assign out_b = out_href ? b_now : {BITS{1'b0}};

	function [BITS-1:0] raw2r;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] r;
		begin
			case (format)
				2'b00: r = (p11 + p13 + p31 + p33) >> 2;
				2'b01: r = (p12 + p32) >> 1;
				2'b10: r = (p21 + p23) >> 1;
				2'b11: r = p22;
				default: r = {BITS{1'b0}};
			endcase
			raw2r = r > {BITS{1'b1}} ? {BITS{1'b1}} : r[BITS-1:0];
		end
	endfunction

	function [BITS-1:0] raw2g;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] g;
		begin
			case (format)
				2'b00: g = (p12 + p32 + p21 + p23) >> 2;
				2'b01: g = p22;
				2'b10: g = p22;
				2'b11: g = (p12 + p32 + p21 + p23) >> 2;
				default: g = {BITS{1'b0}};
			endcase
			raw2g = g > {BITS{1'b1}} ? {BITS{1'b1}} : g[BITS-1:0];
		end
	endfunction

	function [BITS-1:0] raw2b;
		input [1:0] format;
		input [BITS-1:0] p11,p12,p13;
		input [BITS-1:0] p21,p22,p23;
		input [BITS-1:0] p31,p32,p33;
		reg [BITS+1:0] b;
		begin
			case (format)
				2'b00: b = p22;
				2'b01: b = (p21 + p23) >> 1;
				2'b10: b = (p12 + p32) >> 1;
				2'b11: b = (p11 + p13 + p31 + p33) >> 2;
				default: b = {BITS{1'b0}};
			endcase
			raw2b = b > {BITS{1'b1}} ? {BITS{1'b1}} : b[BITS-1:0];
		end
	endfunction
endmodule