data/full_repos/permissive/446312960/Verilog_Simulation/00_src/tb_nand4.v
1: b'%Error: data/full_repos/permissive/446312960/Verilog_Simulation/00_src/tb_nand4.v:12: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("tb_nand4_out.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/00_src/tb_nand4.v:13: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0,tb);   \n       ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/00_src/tb_nand4.v:14: Unsupported or unknown PLI call: $monitor\n      $monitor("%b",y);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/00_src/tb_nand4.v:22: Unsupported: Ignoring delay on this delayed statement.\n         #20;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_nand4;
   reg [3:0] a;
   wire y;
   integer i;

   nand4_if tb(a,y);


   initial
   begin
      $dumpfile("tb_nand4_out.vcd");
       $dumpvars(0,tb);
      $monitor("%b",y);
   end

   initial
   begin
      a=0;
      for(i=0; i<32; i = i+1)
      begin
         #20;
         a=i;
      end
      $finish;
   end
endmodule
module tb_nand4;

   reg [3:0] a;
   wire y;
   integer i;

   nand4_if tb(a,y);


   initial
   begin
      $dumpfile("tb_nand4_out.vcd");
       $dumpvars(0,tb);
      $monitor("%b",y);
   end

   initial
   begin
      a=0;
      for(i=0; i<32; i = i+1)
      begin
         #20;
         a=i;
      end
      $finish;
   end
endmodule