data/full_repos/permissive/505918157/BUS_controllior_top.v
1: b"%Error: data/full_repos/permissive/505918157/BUS_controllior_top.v:38: Cannot find file containing module: 'Multiplexer4to1'\n    Multiplexer4to1 DATA_MUX(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/Multiplexer4to1\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/Multiplexer4to1.v\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/Multiplexer4to1.sv\n             Multiplexer4to1\n             Multiplexer4to1.v\n             Multiplexer4to1.sv\n             obj_dir/Multiplexer4to1\n             obj_dir/Multiplexer4to1.v\n             obj_dir/Multiplexer4to1.sv\n%Error: data/full_repos/permissive/505918157/BUS_controllior_top.v:47: Cannot find file containing module: 'Multiplexer8to1'\n    Multiplexer8to1 ADDR_MUX(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/BUS_controllior_top.v:60: Cannot find file containing module: 'BUS_controller'\n    BUS_controller CPU_BUS (\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module BUS_controller_top #(
    parameter [6:0] DATA_WIDTH = 32,
    parameter [6:0] ADDR_WIDTH = 32
)
(
    input clk,
    input rst_n,
    input mode,
    input [2:0] addr_CS,
    input [1:0] data_CS,
    input [31:0] ALU_din,
    input [31:0] reg_din0,
    input [31:0] reg_din1,
    input [31:0] IM_din,
    input [31:0] ALU_addrin,
    input [31:0] reg_addrin0,
    input [31:0] reg_addrin1,
    input [31:0] PC_addrin,
    input [31:0] IM_addrin,
    output rdata_valid,
    output write_done,
    input start_transaction,
    output [DATA_WIDTH-1:0] rdata,
    output [ADDR_WIDTH-1:0] BUS_addr,
    output [DATA_WIDTH-1:0] BUS_wdata,
    input [DATA_WIDTH-1:0] BUS_rdata,
    output BUS_valid,
    input BUS_wready,
    output BUS_rready,
    input BUS_rvalid,
    output BUS_mode
);


    wire [31:0] addr;
    wire [31:0] wdata;

    Multiplexer4to1 DATA_MUX(
        .CS(data_CS),
        .din0(ALU_din),
        .din1(reg_din0),
        .din2(reg_din1),
        .din3(IM_din),
        .dout(wdata)
    );

    Multiplexer8to1 ADDR_MUX(
        .CS(addr_CS),
        .din0(ALU_addrin),
        .din1(reg_addrin0),
        .din2(reg_addrin1),
        .din3(PC_addrin),
        .din4(IM_addrin),
        .din5(32'd0),
        .din6(32'd0),
        .din7(32'd0),
        .dout(addr)
    );

    BUS_controller CPU_BUS (
        .clk(clk),
        .rst_n(rst_n),
        .mode(mode),
        .rdata_valid(rdata_valid),
        .write_done(write_done),
        .start_transaction(start_transaction),
        .rdata(rdata),
        .addr(addr),
        .wdata(wdata),
        .BUS_addr(BUS_addr),
        .BUS_wdata(BUS_wdata),
        .BUS_rdata(BUS_rdata),
        .BUS_valid(BUS_valid),
        .BUS_wready(BUS_wready),
        .BUS_rready(BUS_rready),
        .BUS_rvalid(BUS_rvalid),
        .BUS_mode(BUS_mode)
    );

endmodule
module BUS_controller_top #(
    parameter [6:0] DATA_WIDTH = 32,
    parameter [6:0] ADDR_WIDTH = 32
)
(
    input clk,
    input rst_n,
    input mode,
    input [2:0] addr_CS,
    input [1:0] data_CS,
    input [31:0] ALU_din,
    input [31:0] reg_din0,
    input [31:0] reg_din1,
    input [31:0] IM_din,
    input [31:0] ALU_addrin,
    input [31:0] reg_addrin0,
    input [31:0] reg_addrin1,
    input [31:0] PC_addrin,
    input [31:0] IM_addrin,
    output rdata_valid,
    output write_done,
    input start_transaction,
    output [DATA_WIDTH-1:0] rdata,
    output [ADDR_WIDTH-1:0] BUS_addr,
    output [DATA_WIDTH-1:0] BUS_wdata,
    input [DATA_WIDTH-1:0] BUS_rdata,
    output BUS_valid,
    input BUS_wready,
    output BUS_rready,
    input BUS_rvalid,
    output BUS_mode
);



    wire [31:0] addr;
    wire [31:0] wdata;

    Multiplexer4to1 DATA_MUX(
        .CS(data_CS),
        .din0(ALU_din),
        .din1(reg_din0),
        .din2(reg_din1),
        .din3(IM_din),
        .dout(wdata)
    );

    Multiplexer8to1 ADDR_MUX(
        .CS(addr_CS),
        .din0(ALU_addrin),
        .din1(reg_addrin0),
        .din2(reg_addrin1),
        .din3(PC_addrin),
        .din4(IM_addrin),
        .din5(32'd0),
        .din6(32'd0),
        .din7(32'd0),
        .dout(addr)
    );

    BUS_controller CPU_BUS (
        .clk(clk),
        .rst_n(rst_n),
        .mode(mode),
        .rdata_valid(rdata_valid),
        .write_done(write_done),
        .start_transaction(start_transaction),
        .rdata(rdata),
        .addr(addr),
        .wdata(wdata),
        .BUS_addr(BUS_addr),
        .BUS_wdata(BUS_wdata),
        .BUS_rdata(BUS_rdata),
        .BUS_valid(BUS_valid),
        .BUS_wready(BUS_wready),
        .BUS_rready(BUS_rready),
        .BUS_rvalid(BUS_rvalid),
        .BUS_mode(BUS_mode)
    );

endmodule