data/full_repos/permissive/487478597/riscv_mem.v
1: b'%Error: data/full_repos/permissive/487478597/riscv_mem.v:66: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(status == 2\'b01) begin\n                    ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:71: syntax error, unexpected \'{\'\n                    {cache_reg[index][{addr[3:2], 2\'h3}], cache_reg[index][{addr[3:2], 2\'h2}], \n                    ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:74: syntax error, unexpected \'[\', expecting IDENTIFIER\n                else cache_reg[index][addr[3:0]] = Wdata;\n                              ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:79: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    Rdata = {cache_reg[index][{addr[3:2], 2\'h3}], \n                          ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};\n                           ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:95: syntax error, unexpected <=, expecting IDENTIFIER\n           mem_Wdata <= {cache_reg[index][{cnt, 2\'h3}], \n                     ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n            mem_Wdata <= 0;\n                      ^~\n%Warning-STMTDLY: data/full_repos/permissive/487478597/riscv_mem.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #1 request_num = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module risc_mem (
    input isWrite,
    input [9:0] addr,
    input [31:0] Wdata,
    output [31:0] Rdata,
    output hit 
);
    wire mem_Write;
    wire [9:0] mem_addr;
    wire [31:0] mem_Wdata, mem_Rdata;
    wire Done;

    cache utt1(
        isWrite,
        addr,
        Wdata,
        mem_Rdata,
        Done,
        Rdata,
        hit,
        mem_Write,
        mem_addr,
        mem_Wdata
    );

    main_mem utt2(
        mem_addr,
        mem_Write,
        mem_Wdata,
        mem_Rdata,
        Done
    );
endmodule
module risc_mem (
    input isWrite,
    input [9:0] addr,
    input [31:0] Wdata,
    output [31:0] Rdata,
    output hit 
);

    wire mem_Write;
    wire [9:0] mem_addr;
    wire [31:0] mem_Wdata, mem_Rdata;
    wire Done;

    cache utt1(
        isWrite,
        addr,
        Wdata,
        mem_Rdata,
        Done,
        Rdata,
        hit,
        mem_Write,
        mem_addr,
        mem_Wdata
    );

    main_mem utt2(
        mem_addr,
        mem_Write,
        mem_Wdata,
        mem_Rdata,
        Done
    );
endmodule