data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #5 we = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #5 din={DW{1\'b1}};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #5 we = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr=4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/406635962/src/tb/tb_sim_ram.v:20: Cannot find file containing module: \'sim_ram\'\nsim_ram#(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/sim_ram\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/sim_ram.v\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/sim_ram.sv\n             sim_ram\n             sim_ram.v\n             sim_ram.sv\n             obj_dir/sim_ram\n             obj_dir/sim_ram.v\n             obj_dir/sim_ram.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sim_ram;
parameter DW = 32;
parameter DP = 64;
parameter AW = 32;
parameter MW = 4;
parameter FORCE_X2ZERO = 1;

reg clk;
reg[DW-1:0] din;
reg [AW-1:0]addr;
reg we;
reg [MW-1:0] wem;

sim_ram#(
    .DP(DP),
    .DW(DW),
    .MW(MW),
    .AW(AW),
    .FORCE_X2ZERO(FORCE_X2ZERO)
) u_sim_ram(
    .clk(clk),
    .din(din),
    .addr(addr),
    .we(we),
    .wem(wem)
);

initial begin
    clk = 1;
    din = {DW{1'b1}};
    addr = 0;
    we = 1;
    wem = {MW{1'b1}};


    #5 we = 1;
    wem = 4'b1111;
    #5 din={DW{1'b1}};
    addr = 4;
    wem = 4'b1010;
    #5 we = 0;
    addr=0;
    #5 addr=4;
end

initial begin
    forever begin
        #1 clk = ~clk;
    end
end

endmodule
module tb_sim_ram;

parameter DW = 32;
parameter DP = 64;
parameter AW = 32;
parameter MW = 4;
parameter FORCE_X2ZERO = 1;

reg clk;
reg[DW-1:0] din;
reg [AW-1:0]addr;
reg we;
reg [MW-1:0] wem;

sim_ram#(
    .DP(DP),
    .DW(DW),
    .MW(MW),
    .AW(AW),
    .FORCE_X2ZERO(FORCE_X2ZERO)
) u_sim_ram(
    .clk(clk),
    .din(din),
    .addr(addr),
    .we(we),
    .wem(wem)
);

initial begin
    clk = 1;
    din = {DW{1'b1}};
    addr = 0;
    we = 1;
    wem = {MW{1'b1}};


    #5 we = 1;
    wem = 4'b1111;
    #5 din={DW{1'b1}};
    addr = 4;
    wem = 4'b1010;
    #5 we = 0;
    addr=0;
    #5 addr=4;
end

initial begin
    forever begin
        #1 clk = ~clk;
    end
end

endmodule