data/full_repos/permissive/420611307/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:20: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance cpu.ALU\n  4\'b0110: begin F = A < B; end\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420611307/cpu.v:79: Cannot find file containing module: \'instruction_memory\'\n instruction_memory ins_mem (\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory.v\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory.sv\n             instruction_memory\n             instruction_memory.v\n             instruction_memory.sv\n             obj_dir/instruction_memory\n             obj_dir/instruction_memory.v\n             obj_dir/instruction_memory.sv\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:160: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b100011: begin w_r_s = 2\'b01; imm_s = 1; rt_imm_s = 1; wr_data_s = 2\'b01; ALU_OP=3\'b100; end   \n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:161: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b101011: begin imm_s = 1; rt_imm_s = 1; ALU_OP = 3\'b100; Write_Reg = 0; Mem_Write = 1; end   \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:162: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b000100: begin ALU_OP = 3\'b101; PC_s = (ZF)?2\'b10:2\'b00; Write_Reg = 1\'b0; end   \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:163: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b000101: begin ALU_OP = 3\'b101; PC_s = (ZF)?2\'b00:2\'b10; Write_Reg = 1\'b0; end   \n                           ^\n%Error: data/full_repos/permissive/420611307/cpu.v:203: Cannot find file containing module: \'data_memory\'\n data_memory data_mem (\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:215: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                              : ... In instance cpu\n  4\'b0100: begin f = {ZF, OF}; end\n                   ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module cpu(clk, rst, display, f);
	input clk, rst;
	input [3:0] display;
	output reg [31:0] f;
	reg [31:0] PC;
	wire [31:0] PC_new;
	reg [1:0] PC_s;
	wire [31:0] Inst_code;
	initial PC = 32'h00000000;
	assign PC_new = PC + 4;
	always@(negedge clk or posedge rst)
	begin
		if(rst==1) PC <= 32'h00000000;
		else
		begin
			case(PC_s)
			2'b00: begin PC <= PC_new; end
			2'b01: begin PC <= R_Data_A; end
			2'b10: begin PC <= PC_new + (imm_data<<2); end
			2'b11: begin PC <= {PC_new[31:28], address, 2'b00}; end
			endcase
		end
	end

	instruction_memory ins_mem (
		.clka(clk),
		.addra(PC[7:2]),
		.douta(Inst_code)
	);


	wire [5:0] opcode;
	wire [4:0] rs, rt, rd, shamt;
	wire [5:0] func;
	wire [15:0] imm;
	wire [15:0] offset;
	wire [25:0] address;
	reg Write_Reg;
	reg Mem_Write;
	wire [7:0] Mem_Addr;
	reg [31:0] M_W_Data;
	wire [31:0] M_R_Data;
	reg [3:0] ALU_OP;
	wire ZF, OF;
	wire [31:0] F;
	assign opcode = Inst_code[31:26];
	assign rs = Inst_code[25:21];
	assign rt = Inst_code[20:16];
	assign rd = Inst_code[15:11];
	assign shamt = Inst_code[10:6];
	assign func = Inst_code[5:0];
	assign imm = Inst_code[15:0];
	assign offset = Inst_code[15:0];
	assign address = Inst_code[25:0];

	reg [1:0] w_r_s, wr_data_s;
	reg imm_s, rt_imm_s;
	
	always@(*)
	begin

		ALU_OP = 4'b0100;
		PC_s = 2'b00;
		w_r_s = 2'b00;
		wr_data_s = 2'b00;
		imm_s = 1'b0;
		rt_imm_s = 1'b0;
		Write_Reg = 1'b1;
		Mem_Write = 1'b0;
		if(opcode==6'b000000)
		begin
			case(func)
			6'b100000: begin ALU_OP = 4'b0100; end
			6'b100010: begin ALU_OP = 4'b0101; end
			6'b100100: begin ALU_OP = 4'b0000; end
			6'b100101: begin ALU_OP = 4'b0001; end
			6'b100110: begin ALU_OP = 4'b0010; end
			6'b100111: begin ALU_OP = 4'b0011; end
			6'b101011: begin ALU_OP = 4'b0110; end
			6'b000100: begin ALU_OP = 4'b0111; end
			6'b001000: begin Write_Reg = 0; Mem_Write = 0; PC_s = 2'b01; end
		endcase
		end
		else if(opcode==6'b000010)
		begin
			Write_Reg = 1'b0;
			Mem_Write = 1'b0;
			PC_s = 2'b11;
		end
		else if(opcode==6'b000011)
		begin
			w_r_s = 2'b10;
			wr_data_s = 2'b10;
			Write_Reg = 1'b1;
			Mem_Write = 1'b0;
			PC_s = 2'b11;
		end
		else
		begin
			case(opcode)
			6'b001000: begin w_r_s = 2'b01; imm_s = 1; rt_imm_s = 1; ALU_OP = 4'b0100; end
			6'b001100: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0000; end

			6'b001110: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0010; end
			6'b001011: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0110; end
			6'b100011: begin w_r_s = 2'b01; imm_s = 1; rt_imm_s = 1; wr_data_s = 2'b01; ALU_OP=3'b100; end
			6'b101011: begin imm_s = 1; rt_imm_s = 1; ALU_OP = 3'b100; Write_Reg = 0; Mem_Write = 1; end
			6'b000100: begin ALU_OP = 3'b101; PC_s = (ZF)?2'b10:2'b00; Write_Reg = 1'b0; end
			6'b000101: begin ALU_OP = 3'b101; PC_s = (ZF)?2'b00:2'b10; Write_Reg = 1'b0; end
			endcase
		end
	end

	wire [31:0] imm_data;
	assign imm_data = (imm_s)?{{16{imm[15]}},imm}:{{16{1'b0}},imm};
	wire [4:0] W_Addr;
	assign W_Addr = (w_r_s[1])?5'b11111:((w_r_s[0])?rt:rd);
	wire [31:0] W_Data;
	assign W_Data = (wr_data_s[1])?PC_new:((wr_data_s[0])?M_R_Data:F);
	wire [31:0] B_ALU;
	assign B_ALU = (rt_imm_s)?imm_data:R_Data_B;
	assign Mem_Addr = F[7:0];
	


	wire [31:0] R_Data_A, R_Data_B;

	register Register (
		.R_Addr_A(rs),
		.R_Addr_B(rt),
		.W_Addr(W_Addr),
		.W_Data(W_Data),
		.clk(clk),
		.rst(rst),
		.Write_Reg(Write_Reg),
		.R_Data_A(R_Data_A),
		.R_Data_B(R_Data_B)
	);

	alu ALU (
		.A(R_Data_A),
		.B(B_ALU),
		.ALU_OP(ALU_OP),
		.F(F),
		.ZF(ZF),
		.OF(OF)
	);

	data_memory data_mem (
		.clka(clk),
		.wea(Mem_Write),
		.addra(Mem_Addr[7:2]),
		.dina(R_Data_B),
		.douta(M_R_Data)
	);
	
	always@(*)
	begin
		case(display)
		4'b1000: begin f = PC; end
		4'b0100: begin f = {ZF, OF}; end
		4'b0010: begin f = M_R_Data; end
		4'b0001: begin f = F; end
		endcase
	end

endmodule
module cpu(clk, rst, display, f);

	input clk, rst;
	input [3:0] display;
	output reg [31:0] f;
	reg [31:0] PC;
	wire [31:0] PC_new;
	reg [1:0] PC_s;
	wire [31:0] Inst_code;
	initial PC = 32'h00000000;
	assign PC_new = PC + 4;
	always@(negedge clk or posedge rst)
	begin
		if(rst==1) PC <= 32'h00000000;
		else
		begin
			case(PC_s)
			2'b00: begin PC <= PC_new; end
			2'b01: begin PC <= R_Data_A; end
			2'b10: begin PC <= PC_new + (imm_data<<2); end
			2'b11: begin PC <= {PC_new[31:28], address, 2'b00}; end
			endcase
		end
	end

	instruction_memory ins_mem (
		.clka(clk),
		.addra(PC[7:2]),
		.douta(Inst_code)
	);


	wire [5:0] opcode;
	wire [4:0] rs, rt, rd, shamt;
	wire [5:0] func;
	wire [15:0] imm;
	wire [15:0] offset;
	wire [25:0] address;
	reg Write_Reg;
	reg Mem_Write;
	wire [7:0] Mem_Addr;
	reg [31:0] M_W_Data;
	wire [31:0] M_R_Data;
	reg [3:0] ALU_OP;
	wire ZF, OF;
	wire [31:0] F;
	assign opcode = Inst_code[31:26];
	assign rs = Inst_code[25:21];
	assign rt = Inst_code[20:16];
	assign rd = Inst_code[15:11];
	assign shamt = Inst_code[10:6];
	assign func = Inst_code[5:0];
	assign imm = Inst_code[15:0];
	assign offset = Inst_code[15:0];
	assign address = Inst_code[25:0];

	reg [1:0] w_r_s, wr_data_s;
	reg imm_s, rt_imm_s;
	
	always@(*)
	begin

		ALU_OP = 4'b0100;
		PC_s = 2'b00;
		w_r_s = 2'b00;
		wr_data_s = 2'b00;
		imm_s = 1'b0;
		rt_imm_s = 1'b0;
		Write_Reg = 1'b1;
		Mem_Write = 1'b0;
		if(opcode==6'b000000)
		begin
			case(func)
			6'b100000: begin ALU_OP = 4'b0100; end
			6'b100010: begin ALU_OP = 4'b0101; end
			6'b100100: begin ALU_OP = 4'b0000; end
			6'b100101: begin ALU_OP = 4'b0001; end
			6'b100110: begin ALU_OP = 4'b0010; end
			6'b100111: begin ALU_OP = 4'b0011; end
			6'b101011: begin ALU_OP = 4'b0110; end
			6'b000100: begin ALU_OP = 4'b0111; end
			6'b001000: begin Write_Reg = 0; Mem_Write = 0; PC_s = 2'b01; end
		endcase
		end
		else if(opcode==6'b000010)
		begin
			Write_Reg = 1'b0;
			Mem_Write = 1'b0;
			PC_s = 2'b11;
		end
		else if(opcode==6'b000011)
		begin
			w_r_s = 2'b10;
			wr_data_s = 2'b10;
			Write_Reg = 1'b1;
			Mem_Write = 1'b0;
			PC_s = 2'b11;
		end
		else
		begin
			case(opcode)
			6'b001000: begin w_r_s = 2'b01; imm_s = 1; rt_imm_s = 1; ALU_OP = 4'b0100; end
			6'b001100: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0000; end

			6'b001110: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0010; end
			6'b001011: begin w_r_s = 2'b01; rt_imm_s = 1; ALU_OP = 4'b0110; end
			6'b100011: begin w_r_s = 2'b01; imm_s = 1; rt_imm_s = 1; wr_data_s = 2'b01; ALU_OP=3'b100; end
			6'b101011: begin imm_s = 1; rt_imm_s = 1; ALU_OP = 3'b100; Write_Reg = 0; Mem_Write = 1; end
			6'b000100: begin ALU_OP = 3'b101; PC_s = (ZF)?2'b10:2'b00; Write_Reg = 1'b0; end
			6'b000101: begin ALU_OP = 3'b101; PC_s = (ZF)?2'b00:2'b10; Write_Reg = 1'b0; end
			endcase
		end
	end

	wire [31:0] imm_data;
	assign imm_data = (imm_s)?{{16{imm[15]}},imm}:{{16{1'b0}},imm};
	wire [4:0] W_Addr;
	assign W_Addr = (w_r_s[1])?5'b11111:((w_r_s[0])?rt:rd);
	wire [31:0] W_Data;
	assign W_Data = (wr_data_s[1])?PC_new:((wr_data_s[0])?M_R_Data:F);
	wire [31:0] B_ALU;
	assign B_ALU = (rt_imm_s)?imm_data:R_Data_B;
	assign Mem_Addr = F[7:0];
	


	wire [31:0] R_Data_A, R_Data_B;

	register Register (
		.R_Addr_A(rs),
		.R_Addr_B(rt),
		.W_Addr(W_Addr),
		.W_Data(W_Data),
		.clk(clk),
		.rst(rst),
		.Write_Reg(Write_Reg),
		.R_Data_A(R_Data_A),
		.R_Data_B(R_Data_B)
	);

	alu ALU (
		.A(R_Data_A),
		.B(B_ALU),
		.ALU_OP(ALU_OP),
		.F(F),
		.ZF(ZF),
		.OF(OF)
	);

	data_memory data_mem (
		.clka(clk),
		.wea(Mem_Write),
		.addra(Mem_Addr[7:2]),
		.dina(R_Data_B),
		.douta(M_R_Data)
	);
	
	always@(*)
	begin
		case(display)
		4'b1000: begin f = PC; end
		4'b0100: begin f = {ZF, OF}; end
		4'b0010: begin f = M_R_Data; end
		4'b0001: begin f = F; end
		endcase
	end

endmodule