data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v
1: b'%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:102: Operator NEGATE expects 7 bits on the LHS, but LHS\'s VARREF \'regime1_r2\' generates 5 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nwire [Bs+1:0] r1 = rc1_r2 ? {2\'b0,regime1_r2} : -regime1_r2;\n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:103: Operator NEGATE expects 7 bits on the LHS, but LHS\'s VARREF \'regime2_r2\' generates 5 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nwire [Bs+1:0] r2 = rc2_r2 ? {2\'b0,regime2_r2} : -regime2_r2;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:104: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'mult_m_ovf\' generates 1 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nwire [Bs+es+1:0] mult_e  =  {r1, e1_r2} + {r2, e2_r2} + mult_m_ovf;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:107: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s COND generates 13 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nwire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:109: Operator ADD expects 6 bits on the LHS, but LHS\'s LOGOR generates 1 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nwire [Bs:0] r_o = (~mult_e[es+Bs+1] || (|mult_e[es-1:0])) + mult_eN[es+Bs:es];\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/fifo_unit/rtl/mult_N32_ES6_PIPE6.v:127: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                                           : ... In instance mult_N32_ES6_PIPE6\nDSR_right_N_S #(.N(3*N+3), .S(Bs+1)) dsr2 (.a({tmp_o_r3,{N{1\'b0}}}), .b(r_o_r3[Bs] ? {Bs{1\'b1}} : r_o_r3), .c(tmp1_o));\n                                                                                   ^\n%Error: Exiting due to 6 warning(s)\n'
module LOD2_1(in, out, out_v);
input [1:0] in;
output out;
output out_v;

assign out = ~in[1] & in[0];
assign out_v = |in;
endmodule
module LOD2_1(in, out, out_v);

input [1:0] in;
output out;
output out_v;

assign out = ~in[1] & in[0];
assign out_v = |in;
endmodule