data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module ImmGen(
    input [31:0] M, 
    output reg [31:0] imm
);
    always @(M) begin
        if (M[6:0] == 7'h03 || M[6:0] == 7'h0f || M[6:0] == 7'h13 || M[6:0] == 7'h67 || M[6:0] == 7'h73) begin
            imm <= {{21{M[31]}}, M[30:20]};
        end
        else if (M[6:0] == 7'h23) begin
            imm <= {{21{M[31]}}, M[30:25], M[11:7]};
        end
        else if (M[6:0] == 7'h63) begin
            imm <= {{21{M[31]}}, M[7], M[30:25], M[11:8]};
        end
        else if (M[6:0] == 7'h17 || M[6:0] == 7'h37) begin
            imm <= {{13{M[31]}}, M[30:12]};
        end
        else if (M[6:0] == 7'h6f) begin
            imm <= {{13{M[31]}}, M[19:12], M[20], M[30:21]};
        end
        else begin imm <= 0; end
    end
endmodule
module ImmGen(
    input [31:0] M, 
    output reg [31:0] imm
);

    always @(M) begin
        if (M[6:0] == 7'h03 || M[6:0] == 7'h0f || M[6:0] == 7'h13 || M[6:0] == 7'h67 || M[6:0] == 7'h73) begin
            imm <= {{21{M[31]}}, M[30:20]};
        end
        else if (M[6:0] == 7'h23) begin
            imm <= {{21{M[31]}}, M[30:25], M[11:7]};
        end
        else if (M[6:0] == 7'h63) begin
            imm <= {{21{M[31]}}, M[7], M[30:25], M[11:8]};
        end
        else if (M[6:0] == 7'h17 || M[6:0] == 7'h37) begin
            imm <= {{13{M[31]}}, M[30:12]};
        end
        else if (M[6:0] == 7'h6f) begin
            imm <= {{13{M[31]}}, M[19:12], M[20], M[30:21]};
        end
        else begin imm <= 0; end
    end
endmodule