data/full_repos/permissive/421450529/mux2_32.v
data/verilator_xmls/2c80bf3d-4ba7-4aad-8c4c-5e3978a255f6.xml
module mux2_32(
    input[31:0] D1,
	 input[31:0] D2,
	 input control,
	 output[31:0] out
    );
   assign out=control?D2:D1;
	

endmodule
module mux2_32(
    input[31:0] D1,
	 input[31:0] D2,
	 input control,
	 output[31:0] out
    );

   assign out=control?D2:D1;
	

endmodule