data/full_repos/permissive/520038878/rtl/segment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/520038878/rtl/segment.v:58: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance sevenSeg.s1\n assign segment_led = dis ? 8\'h0 : {data[4], seg[data[3:0]]};\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/520038878/rtl/segment.v:58: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                     : ... In instance sevenSeg.s1\n assign segment_led = dis ? 8\'h0 : {data[4], seg[data[3:0]]};\n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module sevenSeg (
		input	wire disable1, disable2,
		input  wire [4:0] seg_data_1, seg_data_2,
		output wire [8:0] segment_led_1, segment_led_2
	);
	
	a_segment s0 ( .dis(disable1), .data(seg_data_1),  .segment_led(segment_led_1) );
	a_segment s1 ( .dis(disable2), .data(seg_data_2),  .segment_led(segment_led_2) );
endmodule
module sevenSeg (
		input	wire disable1, disable2,
		input  wire [4:0] seg_data_1, seg_data_2,
		output wire [8:0] segment_led_1, segment_led_2
	);

	
	a_segment s0 ( .dis(disable1), .data(seg_data_1),  .segment_led(segment_led_1) );
	a_segment s1 ( .dis(disable2), .data(seg_data_2),  .segment_led(segment_led_2) );
endmodule