data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:8: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl,data/full_repos/permissive/509468557/prim_assert.sv\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl,data/full_repos/permissive/509468557/prim_assert.sv.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl,data/full_repos/permissive/509468557/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:11: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\n  import prim_pad_wrapper_pkg::*;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output logic       in_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic       in_raw_o,  \n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:26: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input              ie_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:33: Define or directive not defined: \'`ASSERT_INIT\'\n  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:37: syntax error, unexpected assign\n  assign unused_sigs = ^{attr_i.slew_rate,\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:46: syntax error, unexpected assign\n    assign unused_in_sigs = ^{out_i,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:70: syntax error, unexpected assign\n    assign out = out_i ^ attr_i.invert;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv:88: syntax error, unexpected assign\n    assign unused_ana_sigs = ^{attr_i, out_i, oe_i, ie_i};\n    ^~~~~~\n%Error: Exiting due to 10 error(s)\n'
module prim_generic_pad_wrapper
  import prim_pad_wrapper_pkg::*;
#(

  parameter pad_type_e PadType = BidirStd,
  parameter scan_role_e ScanRole = NoScan
) (

  input              clk_scan_i,
  input              scanmode_i,

  input pad_pok_t    pok_i,

  inout wire         inout_io,
  output logic       in_o,
  output logic       in_raw_o,
  input              ie_i,
  input              out_i,
  input              oe_i,
  input pad_attr_t   attr_i
);


  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)


  logic unused_sigs;
  assign unused_sigs = ^{attr_i.slew_rate,
                         attr_i.drive_strength[3:1],
                         attr_i.od_en,
                         attr_i.schmitt_en,
                         scanmode_i,
                         pok_i};

  if (PadType == InputStd) begin : gen_input_only
    logic unused_in_sigs;
    assign unused_in_sigs = ^{out_i,
                              oe_i,
                              attr_i.virt_od_en,
                              attr_i.drive_strength};

    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;

    assign in_o = attr_i.invert ^ in_raw_o;


  `ifndef VERILATOR

    assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
  `endif
  end else if (PadType == BidirTol ||
               PadType == BidirOd ||
               PadType == BidirStd) begin : gen_bidir

    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;

    assign in_o = attr_i.invert ^ in_raw_o;


    logic oe, out;
    assign out = out_i ^ attr_i.invert;
    assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);


  `ifdef VERILATOR
    assign inout_io = (oe)   ? out : 1'bz;
  `else

    assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
    assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;

    assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;

    assign (weak0, weak1)     inout_io = (attr_i.keep_en) ? inout_io : 1'bz;
  `endif
  end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog

    logic unused_ana_sigs;
    assign unused_ana_sigs = ^{attr_i, out_i, oe_i, ie_i};

    assign in_o = inout_io;
    assign in_raw_o = inout_io;

  end else begin : gen_invalid_config

    assert_static_in_generate_config_not_available
        assert_static_in_generate_config_not_available();
  end

endmodule
module prim_generic_pad_wrapper
  import prim_pad_wrapper_pkg::*;

#(

  parameter pad_type_e PadType = BidirStd,
  parameter scan_role_e ScanRole = NoScan
) (

  input              clk_scan_i,
  input              scanmode_i,

  input pad_pok_t    pok_i,

  inout wire         inout_io,
  output logic       in_o,
  output logic       in_raw_o,
  input              ie_i,
  input              out_i,
  input              oe_i,
  input pad_attr_t   attr_i
);


  `ASSERT_INIT(AnalogNoScan_A, PadType != AnalogIn0 || ScanRole == NoScan)


  logic unused_sigs;
  assign unused_sigs = ^{attr_i.slew_rate,
                         attr_i.drive_strength[3:1],
                         attr_i.od_en,
                         attr_i.schmitt_en,
                         scanmode_i,
                         pok_i};

  if (PadType == InputStd) begin : gen_input_only
    logic unused_in_sigs;
    assign unused_in_sigs = ^{out_i,
                              oe_i,
                              attr_i.virt_od_en,
                              attr_i.drive_strength};

    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;

    assign in_o = attr_i.invert ^ in_raw_o;


  `ifndef VERILATOR

    assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
  `endif
  end else if (PadType == BidirTol ||
               PadType == BidirOd ||
               PadType == BidirStd) begin : gen_bidir

    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;

    assign in_o = attr_i.invert ^ in_raw_o;


    logic oe, out;
    assign out = out_i ^ attr_i.invert;
    assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);


  `ifdef VERILATOR
    assign inout_io = (oe)   ? out : 1'bz;
  `else

    assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
    assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;

    assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;

    assign (weak0, weak1)     inout_io = (attr_i.keep_en) ? inout_io : 1'bz;
  `endif
  end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog

    logic unused_ana_sigs;
    assign unused_ana_sigs = ^{attr_i, out_i, oe_i, ie_i};

    assign in_o = inout_io;
    assign in_raw_o = inout_io;

  end else begin : gen_invalid_config

    assert_static_in_generate_config_not_available
        assert_static_in_generate_config_not_available();
  end

endmodule