data/full_repos/permissive/439087417/cordi_arch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439087417/cordi_arch_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk <= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439087417/cordi_arch_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439087417/cordi_arch_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/439087417/cordi_arch_tb.v:36: Cannot find file containing module: \'cordi_arch\'\n cordi_arch uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/cordi_arch\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/cordi_arch.v\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/cordi_arch.sv\n             cordi_arch\n             cordi_arch.v\n             cordi_arch.sv\n             obj_dir/cordi_arch\n             obj_dir/cordi_arch.v\n             obj_dir/cordi_arch.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cordi_arch_tb;


	reg [15:0] theta;
	reg bgn;
	reg clk;

	wire [15:0] cos;
	wire fin;


	cordi_arch uut (
		.theta(theta), 
		.bgn(bgn), 
		.cos(cos), 
		.fin(fin),
		.clk(clk)
	);
	always begin
		#1 clk <= ~clk;
	end
	initial begin

		theta = 16'b1011_1100_1010_1101;
		bgn = 0;
		clk = 0;

		#100;
      bgn = 1;

		#20;
		bgn = 0;


	end
      
endmodule
module cordi_arch_tb;



	reg [15:0] theta;
	reg bgn;
	reg clk;

	wire [15:0] cos;
	wire fin;


	cordi_arch uut (
		.theta(theta), 
		.bgn(bgn), 
		.cos(cos), 
		.fin(fin),
		.clk(clk)
	);
	always begin
		#1 clk <= ~clk;
	end
	initial begin

		theta = 16'b1011_1100_1010_1101;
		bgn = 0;
		clk = 0;

		#100;
      bgn = 1;

		#20;
		bgn = 0;


	end
      
endmodule