data/full_repos/permissive/492140037/OJ/Ifetc32.v
1: b'%Error: data/full_repos/permissive/492140037/OJ/Ifetc32.v:20: Cannot find file containing module: \'prgrom\'\n    prgrom instmem(.clka(clock), .addra(PC[15:2]), .douta(Instruction));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/prgrom\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/prgrom.v\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/prgrom.sv\n             prgrom\n             prgrom.v\n             prgrom.sv\n             obj_dir/prgrom\n             obj_dir/prgrom.v\n             obj_dir/prgrom.sv\n%Warning-WIDTH: data/full_repos/permissive/492140037/OJ/Ifetc32.v:22: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance Ifetc32\n    assign branch_base_addr = PC + 3\'b100;\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/492140037/OJ/Ifetc32.v:33: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance Ifetc32\n            Next_PC = PC + 3\'b100;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/492140037/OJ/Ifetc32.v:45: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance Ifetc32\n            Jal_address <= PC + 3\'b100;\n                              ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module Ifetc32(Instruction,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr);
    output[31:0] Instruction;
    output[31:0] branch_base_addr;
    input[31:0]  Addr_result;
    input[31:0]  Read_data_1;
    input        Branch;
    input        nBranch;
    input        Jmp;
    input        Jal;
    input        Jr;
    input        Zero;
    input        clock,reset;
    output[31:0] link_addr;

    reg[31:0] PC, Next_PC;
    reg[31:0] Jal_address;

    prgrom instmem(.clka(clock), .addra(PC[15:2]), .douta(Instruction));

    assign branch_base_addr = PC + 3'b100;
    assign link_addr = Jal_address;
    
    always @(*) begin
        if ((Branch == 1 && Zero == 1) || (nBranch == 1 && Zero == 0)) begin
            Next_PC = Addr_result;
        end
        else if (Jr == 1) begin
            Next_PC = Read_data_1;
        end
        else begin
            Next_PC = PC + 3'b100;
        end
    end

    always @(negedge clock or posedge reset) begin
        if (reset == 1) begin
            PC <= 32'h0000_0000;
        end
        else if (Jmp == 1) begin
            PC <= {PC[31:28], Instruction[25:0], 2'b00};
        end
        else if (Jal == 1) begin
            Jal_address <= PC + 3'b100;
            PC <= {PC[31:28], Instruction[25:0], 2'b00};
        end
        else begin
            PC <= Next_PC;
        end
    end
    
endmodule
module Ifetc32(Instruction,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr);

    output[31:0] Instruction;
    output[31:0] branch_base_addr;
    input[31:0]  Addr_result;
    input[31:0]  Read_data_1;
    input        Branch;
    input        nBranch;
    input        Jmp;
    input        Jal;
    input        Jr;
    input        Zero;
    input        clock,reset;
    output[31:0] link_addr;

    reg[31:0] PC, Next_PC;
    reg[31:0] Jal_address;

    prgrom instmem(.clka(clock), .addra(PC[15:2]), .douta(Instruction));

    assign branch_base_addr = PC + 3'b100;
    assign link_addr = Jal_address;
    
    always @(*) begin
        if ((Branch == 1 && Zero == 1) || (nBranch == 1 && Zero == 0)) begin
            Next_PC = Addr_result;
        end
        else if (Jr == 1) begin
            Next_PC = Read_data_1;
        end
        else begin
            Next_PC = PC + 3'b100;
        end
    end

    always @(negedge clock or posedge reset) begin
        if (reset == 1) begin
            PC <= 32'h0000_0000;
        end
        else if (Jmp == 1) begin
            PC <= {PC[31:28], Instruction[25:0], 2'b00};
        end
        else if (Jal == 1) begin
            Jal_address <= PC + 3'b100;
            PC <= {PC[31:28], Instruction[25:0], 2'b00};
        end
        else begin
            PC <= Next_PC;
        end
    end
    
endmodule