data/full_repos/permissive/473722449/SIPO_behave.v
data/verilator_xmls/76200b92-6586-42ba-b20a-dcb492347dd6.xml
module SIPO_behave(
    input d,
    input load,
    input clk,
    output [3:0] q
    );
    reg [3:0] temp;
    always@(posedge clk)
    begin
        if (load == 0)
            temp=temp;
        else
            temp={temp[2:0],d};    
    end
    assign q=temp;
endmodule
module SIPO_behave(
    input d,
    input load,
    input clk,
    output [3:0] q
    );

    reg [3:0] temp;
    always@(posedge clk)
    begin
        if (load == 0)
            temp=temp;
        else
            temp={temp[2:0],d};    
    end
    assign q=temp;
endmodule