data/full_repos/permissive/438129974/playerclient/sevenshow.v
1: b'%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:17: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                : ... In instance sevenshow\n    assign lo[3] = 8\'d0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:20: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                : ... In instance sevenshow\n   tmp <= 8\'d0; \n       ^~\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:26: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'inp\' generates 9 bits.\n                                                                                : ... In instance sevenshow\n  next_tmp = inp;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:28: Output port connection \'out\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n    show_encode se0(.inp(lo[0]), .out(dlo[0]));\n                                  ^~~\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:29: Output port connection \'out\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n show_encode se1(.inp(lo[1]), .out(dlo[1]));\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:30: Output port connection \'out\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n show_encode se2(.inp(lo[2]), .out(dlo[2]));\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:31: Output port connection \'out\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n show_encode se3(.inp(lo[3]), .out(dlo[3]));\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:32: Input port connection \'a\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n seven_show seven_s(.clk(clk), .rst_n(rst_n), .a(dlo[0]), .b(dlo[1]), .c(dlo[2]), .d(dlo[3]), .an(an), .led(seven));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:32: Input port connection \'b\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n seven_show seven_s(.clk(clk), .rst_n(rst_n), .a(dlo[0]), .b(dlo[1]), .c(dlo[2]), .d(dlo[3]), .an(an), .led(seven));\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:32: Input port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n seven_show seven_s(.clk(clk), .rst_n(rst_n), .a(dlo[0]), .b(dlo[1]), .c(dlo[2]), .d(dlo[3]), .an(an), .led(seven));\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/438129974/playerclient/sevenshow.v:32: Input port connection \'d\' expects 8 bits on the pin connection, but pin connection\'s ARRAYSEL generates 9 bits.\n                                                                                : ... In instance sevenshow\n seven_show seven_s(.clk(clk), .rst_n(rst_n), .a(dlo[0]), .b(dlo[1]), .c(dlo[2]), .d(dlo[3]), .an(an), .led(seven));\n                                                                                   ^\n%Error: Exiting due to 11 warning(s)\n'
module seven_show(clk, rst_n, a, b, c, d, an, led);
	input clk, rst_n;
	input [7:0] a, b, c, d;
	output [3:0] an;
	output [7:0] led;
	reg [3:0] an;
	reg [3:0] next_an;
	reg [7:0] led;
	reg [7:0] next_led;
	reg [2:0] next_counter;
	parameter size = 16;
	parameter size2 = 8;
	reg [size - 1:0] clcounter;
	reg [size - 1:0] next_clcounter;
	always @(posedge clk)begin
		if(rst_n)begin
			an <= 4'b0;
			clcounter <= {size{1'b0}};
            led <= 8'b00001111;
		end else begin
			an <= next_an;
       		led <= next_led;
			clcounter <= next_clcounter;
		end
	end
	always @(*)begin
		next_an = an;
		next_led = led;
		next_clcounter = clcounter + {size{1'b1}};
		if(clcounter == {size{1'b1}} ? 1'b1 : 1'b0)begin
			next_an = (an == 4'b1110) ? 4'b1101:
						(an == 4'b1101) ? 4'b1011:
						(an == 4'b1011) ? 4'b0111:
						(an == 4'b0111) ? 4'b1110:4'b1101;
			if(next_an == 4'b1110)begin
                next_led = a;
			end else if(next_an == 4'b1101) begin
				next_led = b;
			end else if(next_an == 4'b1011) begin
				next_led = c;
			end else begin 
				next_led = d;
			end
		end
	end
endmodule
module seven_show(clk, rst_n, a, b, c, d, an, led);

	input clk, rst_n;
	input [7:0] a, b, c, d;
	output [3:0] an;
	output [7:0] led;
	reg [3:0] an;
	reg [3:0] next_an;
	reg [7:0] led;
	reg [7:0] next_led;
	reg [2:0] next_counter;
	parameter size = 16;
	parameter size2 = 8;
	reg [size - 1:0] clcounter;
	reg [size - 1:0] next_clcounter;
	always @(posedge clk)begin
		if(rst_n)begin
			an <= 4'b0;
			clcounter <= {size{1'b0}};
            led <= 8'b00001111;
		end else begin
			an <= next_an;
       		led <= next_led;
			clcounter <= next_clcounter;
		end
	end
	always @(*)begin
		next_an = an;
		next_led = led;
		next_clcounter = clcounter + {size{1'b1}};
		if(clcounter == {size{1'b1}} ? 1'b1 : 1'b0)begin
			next_an = (an == 4'b1110) ? 4'b1101:
						(an == 4'b1101) ? 4'b1011:
						(an == 4'b1011) ? 4'b0111:
						(an == 4'b0111) ? 4'b1110:4'b1101;
			if(next_an == 4'b1110)begin
                next_led = a;
			end else if(next_an == 4'b1101) begin
				next_led = b;
			end else if(next_an == 4'b1011) begin
				next_led = c;
			end else begin 
				next_led = d;
			end
		end
	end
endmodule