data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:744: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'Km\' generates 32 or 4 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n        matchListMatrix[k] <= Km;\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:748: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wdata\' generates 4 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n      matchListMatrix[addr] <= wdata;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:752: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n  assign rdata = matchListMatrix[addr];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:345: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'matchListMatrix_rdata\' generates 4 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign m_assigned = matchListMatrix_rdata;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:348: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign mPrefMatrix_raddr = Km-pc_mIndex;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:370: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'m\' generates 3 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign matchListMatrix_wdata = m;\n                               ^\n%Error: Exiting due to 6 warning(s)\n'
module stable_match
#(
  parameter Kw =8,
  parameter Km =8,
  parameter M  =8,
  parameter W  =8
)
(
  clk,
  rst,
  g_input,
  e_input,
  o
);

  function integer log2;
    input [31:0] value;
    reg [31:0] temp;
  begin
    temp = value - 1;
    for (log2=0; temp>0; log2=log2+1)
      temp = temp>>1;
  end
  endfunction

  localparam logM = log2(M);
  localparam logW = log2(W);
  localparam logKm = log2(Km);
  localparam logKw = log2(Kw);

  localparam state_select_m=0;
  localparam state_select_w=2;
  localparam state_wait_w = 3;
  localparam state_do_proposal = 4;

  input clk,rst;

  input [M*logKw+Km*logW-1:0] g_input;
  input [M*logKw+Km*logW-1:0] e_input;
  output [W*logM-1:0] o;

  wire [M*logKw-1:0] wPref_rev;
  wire [Km*logW-1:0] mPref;
  wire [W*logM-1:0] matchList;

  wire [logKm-1:0]   mPrefMatrix_raddr;
  wire [logW-1:0]    mPrefMatrix_rdata;
  wire [logM-1:0] pc_addr;
  wire [logKm:0]  pc_wdata;
  wire pc_wen;
  wire [logKm:0]  pc_rdata;
  wire [logW-1:0] wIsMatch_addr;
  wire wIsMatch_wdata;
  wire wIsMatch_wen;
  wire wIsMatch_rdata;
  wire [logW-1:0] matchListMatrix_addr;
  wire [logM:0] matchListMatrix_wdata;
  wire matchListMatrix_wen;
  wire [logM:0] matchListMatrix_rdata;

  wire [logM-1:0]   wPref_rev_Matrix_raddr1;
  wire [logKw-1:0]  wPref_rev_Matrix_rdata1;
  wire [logM-1:0]   wPref_rev_Matrix_raddr2;
  wire [logKw-1:0]  wPref_rev_Matrix_rdata2;

  wire [logM-1:0] mIsMatch_waddr1;
  wire mIsMatch_wdata1;
  wire mIsMatch_wen1;
  wire [logM-1:0] mIsMatch_waddr2;
  wire mIsMatch_wdata2;
  wire mIsMatch_wen2;
  wire [logM-1:0] mIsMatch_raddr;
  wire mIsMatch_rdata;

  wire [logM-1:0] mIndex;
  wire [logW-1:0] wIndex;
  wire [2:0] state;
  wire [logM-1:0] m;
  wire [logW-1:0] w;

 wire [M*logKw+Km*logW-1:0] input_xors;
 assign input_xors = g_input^e_input;
 assign wPref_rev = input_xors[M*logKw-1:0];
 assign mPref = input_xors[M*logKw+Km*logW-1:M*logKw];
 assign o = matchList;

  MPrefMatrix
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MPrefMatrix_
  (
    .mPref(mPref),
    .raddr(mPrefMatrix_raddr),
    .rdata(mPrefMatrix_rdata)
  );

  WPref_rev_Matrix
  #(
      .Kw(Kw),
      .Km(Km),
      .M(M),
      .W(W)
  )
  WPref_rev_Matrix_
  (
    .wPref_rev(wPref_rev),
    .raddr1(wPref_rev_Matrix_raddr1),
    .rdata1(wPref_rev_Matrix_rdata1),
    .raddr2(wPref_rev_Matrix_raddr2),
    .rdata2(wPref_rev_Matrix_rdata2)
  );

  PC
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  PC_
  (
    .clk(clk),
    .rst(rst),
    .addr(pc_addr),
    .wdata(pc_wdata),
    .wen(pc_wen),
    .rdata(pc_rdata)
  );

  MIsMatch
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MIsMatch_
  (
    .clk(clk),
    .rst(rst),
    .waddr1(mIsMatch_waddr1),
    .wdata1(mIsMatch_wdata1),
    .wen1(mIsMatch_wen1),
    .waddr2(mIsMatch_waddr2),
    .wdata2(mIsMatch_wdata2),
    .wen2(mIsMatch_wen2),
    .raddr(mIsMatch_raddr),
    .rdata(mIsMatch_rdata)
  );

  WIsMatch
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  WIsMatch_
  (
    .clk(clk),
    .rst(rst),
    .addr(wIsMatch_addr),
    .wdata(wIsMatch_wdata),
    .wen(wIsMatch_wen),
    .rdata(wIsMatch_rdata)
  );

  MatchListMatrix
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MatchListMatrix_
  (
    .clk(clk),
    .rst(rst),
    .addr(matchListMatrix_addr),
    .wdata(matchListMatrix_wdata),
    .wen(matchListMatrix_wen),
    .rdata(matchListMatrix_rdata),
    .matchList(matchList)
  );

  stable_match_core
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  stable_match_core_
  (
    .clk(clk),
    .rst(rst),
    .state(state),
    .mIndex(mIndex),
    .wIndex(wIndex),
    .m(m),
    .w(w),
    .mPrefMatrix_raddr(mPrefMatrix_raddr),
    .mPrefMatrix_rdata(mPrefMatrix_rdata),
    .pc_addr(pc_addr),
    .pc_wdata(pc_wdata),
    .pc_wen(pc_wen),
    .pc_rdata(pc_rdata),
    .wIsMatch_addr(wIsMatch_addr),
    .wIsMatch_wdata(wIsMatch_wdata),
    .wIsMatch_wen(wIsMatch_wen),
    .wIsMatch_rdata(wIsMatch_rdata),
    .matchListMatrix_addr(matchListMatrix_addr),
    .matchListMatrix_wdata(matchListMatrix_wdata),
    .matchListMatrix_wen(matchListMatrix_wen),
    .matchListMatrix_rdata(matchListMatrix_rdata),
    .wPref_rev_Matrix_raddr1(wPref_rev_Matrix_raddr1),
    .wPref_rev_Matrix_rdata1(wPref_rev_Matrix_rdata1),
    .wPref_rev_Matrix_raddr2(wPref_rev_Matrix_raddr2),
    .wPref_rev_Matrix_rdata2(wPref_rev_Matrix_rdata2),
    .mIsMatch_waddr1(mIsMatch_waddr1),
    .mIsMatch_wdata1(mIsMatch_wdata1),
    .mIsMatch_wen1(mIsMatch_wen1),
    .mIsMatch_waddr2(mIsMatch_waddr2),
    .mIsMatch_wdata2(mIsMatch_wdata2),
    .mIsMatch_wen2(mIsMatch_wen2),
    .mIsMatch_raddr(mIsMatch_raddr),
    .mIsMatch_rdata(mIsMatch_rdata)
  );

endmodule
module stable_match
#(
  parameter Kw =8,
  parameter Km =8,
  parameter M  =8,
  parameter W  =8
)
(
  clk,
  rst,
  g_input,
  e_input,
  o
);


  function integer log2;
    input [31:0] value;
    reg [31:0] temp;
  begin
    temp = value - 1;
    for (log2=0; temp>0; log2=log2+1)
      temp = temp>>1;
  end
  endfunction

  localparam logM = log2(M);
  localparam logW = log2(W);
  localparam logKm = log2(Km);
  localparam logKw = log2(Kw);

  localparam state_select_m=0;
  localparam state_select_w=2;
  localparam state_wait_w = 3;
  localparam state_do_proposal = 4;

  input clk,rst;

  input [M*logKw+Km*logW-1:0] g_input;
  input [M*logKw+Km*logW-1:0] e_input;
  output [W*logM-1:0] o;

  wire [M*logKw-1:0] wPref_rev;
  wire [Km*logW-1:0] mPref;
  wire [W*logM-1:0] matchList;

  wire [logKm-1:0]   mPrefMatrix_raddr;
  wire [logW-1:0]    mPrefMatrix_rdata;
  wire [logM-1:0] pc_addr;
  wire [logKm:0]  pc_wdata;
  wire pc_wen;
  wire [logKm:0]  pc_rdata;
  wire [logW-1:0] wIsMatch_addr;
  wire wIsMatch_wdata;
  wire wIsMatch_wen;
  wire wIsMatch_rdata;
  wire [logW-1:0] matchListMatrix_addr;
  wire [logM:0] matchListMatrix_wdata;
  wire matchListMatrix_wen;
  wire [logM:0] matchListMatrix_rdata;

  wire [logM-1:0]   wPref_rev_Matrix_raddr1;
  wire [logKw-1:0]  wPref_rev_Matrix_rdata1;
  wire [logM-1:0]   wPref_rev_Matrix_raddr2;
  wire [logKw-1:0]  wPref_rev_Matrix_rdata2;

  wire [logM-1:0] mIsMatch_waddr1;
  wire mIsMatch_wdata1;
  wire mIsMatch_wen1;
  wire [logM-1:0] mIsMatch_waddr2;
  wire mIsMatch_wdata2;
  wire mIsMatch_wen2;
  wire [logM-1:0] mIsMatch_raddr;
  wire mIsMatch_rdata;

  wire [logM-1:0] mIndex;
  wire [logW-1:0] wIndex;
  wire [2:0] state;
  wire [logM-1:0] m;
  wire [logW-1:0] w;

 wire [M*logKw+Km*logW-1:0] input_xors;
 assign input_xors = g_input^e_input;
 assign wPref_rev = input_xors[M*logKw-1:0];
 assign mPref = input_xors[M*logKw+Km*logW-1:M*logKw];
 assign o = matchList;

  MPrefMatrix
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MPrefMatrix_
  (
    .mPref(mPref),
    .raddr(mPrefMatrix_raddr),
    .rdata(mPrefMatrix_rdata)
  );

  WPref_rev_Matrix
  #(
      .Kw(Kw),
      .Km(Km),
      .M(M),
      .W(W)
  )
  WPref_rev_Matrix_
  (
    .wPref_rev(wPref_rev),
    .raddr1(wPref_rev_Matrix_raddr1),
    .rdata1(wPref_rev_Matrix_rdata1),
    .raddr2(wPref_rev_Matrix_raddr2),
    .rdata2(wPref_rev_Matrix_rdata2)
  );

  PC
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  PC_
  (
    .clk(clk),
    .rst(rst),
    .addr(pc_addr),
    .wdata(pc_wdata),
    .wen(pc_wen),
    .rdata(pc_rdata)
  );

  MIsMatch
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MIsMatch_
  (
    .clk(clk),
    .rst(rst),
    .waddr1(mIsMatch_waddr1),
    .wdata1(mIsMatch_wdata1),
    .wen1(mIsMatch_wen1),
    .waddr2(mIsMatch_waddr2),
    .wdata2(mIsMatch_wdata2),
    .wen2(mIsMatch_wen2),
    .raddr(mIsMatch_raddr),
    .rdata(mIsMatch_rdata)
  );

  WIsMatch
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  WIsMatch_
  (
    .clk(clk),
    .rst(rst),
    .addr(wIsMatch_addr),
    .wdata(wIsMatch_wdata),
    .wen(wIsMatch_wen),
    .rdata(wIsMatch_rdata)
  );

  MatchListMatrix
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  MatchListMatrix_
  (
    .clk(clk),
    .rst(rst),
    .addr(matchListMatrix_addr),
    .wdata(matchListMatrix_wdata),
    .wen(matchListMatrix_wen),
    .rdata(matchListMatrix_rdata),
    .matchList(matchList)
  );

  stable_match_core
  #(
    .Kw(Kw),
    .Km(Km),
    .M(M),
    .W(W)
  )
  stable_match_core_
  (
    .clk(clk),
    .rst(rst),
    .state(state),
    .mIndex(mIndex),
    .wIndex(wIndex),
    .m(m),
    .w(w),
    .mPrefMatrix_raddr(mPrefMatrix_raddr),
    .mPrefMatrix_rdata(mPrefMatrix_rdata),
    .pc_addr(pc_addr),
    .pc_wdata(pc_wdata),
    .pc_wen(pc_wen),
    .pc_rdata(pc_rdata),
    .wIsMatch_addr(wIsMatch_addr),
    .wIsMatch_wdata(wIsMatch_wdata),
    .wIsMatch_wen(wIsMatch_wen),
    .wIsMatch_rdata(wIsMatch_rdata),
    .matchListMatrix_addr(matchListMatrix_addr),
    .matchListMatrix_wdata(matchListMatrix_wdata),
    .matchListMatrix_wen(matchListMatrix_wen),
    .matchListMatrix_rdata(matchListMatrix_rdata),
    .wPref_rev_Matrix_raddr1(wPref_rev_Matrix_raddr1),
    .wPref_rev_Matrix_rdata1(wPref_rev_Matrix_rdata1),
    .wPref_rev_Matrix_raddr2(wPref_rev_Matrix_raddr2),
    .wPref_rev_Matrix_rdata2(wPref_rev_Matrix_rdata2),
    .mIsMatch_waddr1(mIsMatch_waddr1),
    .mIsMatch_wdata1(mIsMatch_wdata1),
    .mIsMatch_wen1(mIsMatch_wen1),
    .mIsMatch_waddr2(mIsMatch_waddr2),
    .mIsMatch_wdata2(mIsMatch_wdata2),
    .mIsMatch_wen2(mIsMatch_wen2),
    .mIsMatch_raddr(mIsMatch_raddr),
    .mIsMatch_rdata(mIsMatch_rdata)
  );

endmodule