data/full_repos/permissive/419984230/rtl/signExpMul.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:72: Operator ADD expects 32 or 13 bits on the LHS, but LHS\'s SEL generates 11 bits.\n                                                                        : ... In instance signExpMul\n            temp_out = isMul ? (data_a[10:0] + data_b[10:0] - (precision == 2\'b01 ? HBIAS : precision == 2\'b10 ? SBIAS : DBIAS)) : data_a[10:0];\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:72: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s SEL generates 11 bits.\n                                                                        : ... In instance signExpMul\n            temp_out = isMul ? (data_a[10:0] + data_b[10:0] - (precision == 2\'b01 ? HBIAS : precision == 2\'b10 ? SBIAS : DBIAS)) : data_a[10:0];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:72: Operator COND expects 32 or 13 bits on the Conditional False, but Conditional False\'s SEL generates 11 bits.\n                                                                        : ... In instance signExpMul\n            temp_out = isMul ? (data_a[10:0] + data_b[10:0] - (precision == 2\'b01 ? HBIAS : precision == 2\'b10 ? SBIAS : DBIAS)) : data_a[10:0];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:85: Operator SUB expects 13 bits on the RHS, but RHS\'s VARREF \'data_c\' generates 11 bits.\n                                                                        : ... In instance signExpMul\n        expdiff = out - data_c;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:86: Operator COND expects 13 bits on the Conditional True, but Conditional True\'s CONST \'8\'hb\' generates 8 bits.\n                                                                        : ... In instance signExpMul\n        shftamt_temp = expdiff + (mode == 01 ? 8\'d11 : mode == 2\'b10 ? 8\'d24 : 8\'d53);   \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:86: Operator COND expects 13 bits on the Conditional True, but Conditional True\'s CONST \'8\'h18\' generates 8 bits.\n                                                                        : ... In instance signExpMul\n        shftamt_temp = expdiff + (mode == 01 ? 8\'d11 : mode == 2\'b10 ? 8\'d24 : 8\'d53);   \n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:86: Operator COND expects 13 bits on the Conditional False, but Conditional False\'s CONST \'8\'h35\' generates 8 bits.\n                                                                        : ... In instance signExpMul\n        shftamt_temp = expdiff + (mode == 01 ? 8\'d11 : mode == 2\'b10 ? 8\'d24 : 8\'d53);   \n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:87: Operator GT expects 13 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                        : ... In instance signExpMul\n        isSat = $signed(shftamt_temp) > 8\'b1111_1111;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/419984230/rtl/signExpMul.v:89: Operator GTE expects 13 bits on the RHS, but RHS\'s VARREF \'data_c\' generates 11 bits.\n                                                                        : ... In instance signExpMul\n        isshft = en ? $signed(out) >= data_c : 1\'b0;\n                                   ^~\n%Error: Exiting due to 9 warning(s)\n'
module signExpMul(
    input       [15:0]  a,
    input       [15:0]  b,
    input       [10:0]  c,
    input               en,
    input       [1:0]   mode,  
    input       [1:0]   precision,
    input               isMul,
    output reg  [12:0]  out,
    output reg          underflow,
    output reg          overflow,
    output reg          inf,
    output reg          NaN,
    output reg          zero,
    output reg          sign,
    output reg          isshft,
    output reg   [7:0]  shftamt,
    output reg   [12:0] expdiff,
    output reg          isSat
);


    parameter   DBIAS    =   1022;
    parameter   SBIAS    =   126;
    parameter   HBIAS    =   14;
    reg [12:0] temp_out;
    reg [15:0] data_a, data_b; 
    reg [10:0] data_c;

    reg [12:0] shftamt_temp;

    always @(*) begin
        {underflow, overflow, inf, NaN, zero} = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
        data_a = en ? a : 16'b0; 
        data_b = en ? b : 16'b0; 
        data_c = en ? c : 11'b0; 
        sign = isMul ? (data_a[11] ^ data_b[11]) : data_a[11];
        
        if (data_a[15]) begin
            out = 13'b0;
            zero = 1'b1;
            if((data_b[13] || data_b [12]) & isMul) begin
                zero = 1'b0; NaN = 1'b1;
                out = 13'b1_1111_1111_1111;
            end
        end
        else if (data_b[15] & isMul) begin
            out = 13'b0;
            zero = 1'b1;
            if(data_a[13] || data_a [12]) begin
                zero = 1'b0; NaN = 1'b1;
                out = 13'b1_1111_1111_1111;
            end
        end else if ( ~data_a[14] || (~data_b[14] & isMul)) begin
            out = 13'b0;
            zero = 1'b1;
        end else if (data_a[13] || data_a[12] || (data_b[13] || data_b[12]) && isMul) begin
            out = 13'b1_1111_1111_1111;
            inf = 1'b1; NaN = 1'b0;
            if (data_a[12] || (data_b[12] && isMul)) begin
                inf = 1'b0; NaN = 1'b1;
            end
        end else begin
            temp_out = isMul ? (data_a[10:0] + data_b[10:0] - (precision == 2'b01 ? HBIAS : precision == 2'b10 ? SBIAS : DBIAS)) : data_a[10:0];
            case (precision)
                2'b01: begin overflow = $signed(temp_out) >= 13'd30 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                2'b10: begin overflow = $signed(temp_out) >= 13'd254 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                2'b11: begin overflow = $signed(temp_out) >= 13'd2046 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                default: begin overflow = $signed(temp_out) >= 13'd2046 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
            endcase
            out = overflow ? 13'b1_1111_1111_1111 : underflow ? 13'b0 : temp_out;
        end
        expdiff = out - data_c;
        shftamt_temp = expdiff + (mode == 01 ? 8'd11 : mode == 2'b10 ? 8'd24 : 8'd53);
        isSat = $signed(shftamt_temp) > 8'b1111_1111;
        shftamt = en ? isSat ? 8'b1111_1111 : shftamt_temp[7:0] : 8'b0;
        isshft = en ? $signed(out) >= data_c : 1'b0;
    end
        
endmodule
module signExpMul(
    input       [15:0]  a,
    input       [15:0]  b,
    input       [10:0]  c,
    input               en,
    input       [1:0]   mode,  
    input       [1:0]   precision,
    input               isMul,
    output reg  [12:0]  out,
    output reg          underflow,
    output reg          overflow,
    output reg          inf,
    output reg          NaN,
    output reg          zero,
    output reg          sign,
    output reg          isshft,
    output reg   [7:0]  shftamt,
    output reg   [12:0] expdiff,
    output reg          isSat
);



    parameter   DBIAS    =   1022;
    parameter   SBIAS    =   126;
    parameter   HBIAS    =   14;
    reg [12:0] temp_out;
    reg [15:0] data_a, data_b; 
    reg [10:0] data_c;

    reg [12:0] shftamt_temp;

    always @(*) begin
        {underflow, overflow, inf, NaN, zero} = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
        data_a = en ? a : 16'b0; 
        data_b = en ? b : 16'b0; 
        data_c = en ? c : 11'b0; 
        sign = isMul ? (data_a[11] ^ data_b[11]) : data_a[11];
        
        if (data_a[15]) begin
            out = 13'b0;
            zero = 1'b1;
            if((data_b[13] || data_b [12]) & isMul) begin
                zero = 1'b0; NaN = 1'b1;
                out = 13'b1_1111_1111_1111;
            end
        end
        else if (data_b[15] & isMul) begin
            out = 13'b0;
            zero = 1'b1;
            if(data_a[13] || data_a [12]) begin
                zero = 1'b0; NaN = 1'b1;
                out = 13'b1_1111_1111_1111;
            end
        end else if ( ~data_a[14] || (~data_b[14] & isMul)) begin
            out = 13'b0;
            zero = 1'b1;
        end else if (data_a[13] || data_a[12] || (data_b[13] || data_b[12]) && isMul) begin
            out = 13'b1_1111_1111_1111;
            inf = 1'b1; NaN = 1'b0;
            if (data_a[12] || (data_b[12] && isMul)) begin
                inf = 1'b0; NaN = 1'b1;
            end
        end else begin
            temp_out = isMul ? (data_a[10:0] + data_b[10:0] - (precision == 2'b01 ? HBIAS : precision == 2'b10 ? SBIAS : DBIAS)) : data_a[10:0];
            case (precision)
                2'b01: begin overflow = $signed(temp_out) >= 13'd30 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                2'b10: begin overflow = $signed(temp_out) >= 13'd254 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                2'b11: begin overflow = $signed(temp_out) >= 13'd2046 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
                default: begin overflow = $signed(temp_out) >= 13'd2046 ? 1'b1 : 1'b0; inf = overflow; 
                    underflow = $signed(temp_out) < 0 ? 1'b1 : 1'b0;  end
            endcase
            out = overflow ? 13'b1_1111_1111_1111 : underflow ? 13'b0 : temp_out;
        end
        expdiff = out - data_c;
        shftamt_temp = expdiff + (mode == 01 ? 8'd11 : mode == 2'b10 ? 8'd24 : 8'd53);
        isSat = $signed(shftamt_temp) > 8'b1111_1111;
        shftamt = en ? isSat ? 8'b1111_1111 : shftamt_temp[7:0] : 8'b0;
        isshft = en ? $signed(out) >= data_c : 1'b0;
    end
        
endmodule