data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:401: Cell has missing pin: \'ram1_clock\'\n   ramclock rc(.ref_clock(clock_65mhz), .fpga_clock(clk),\n            ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:706: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                    : ... Top module \'zbt_6111_sample\'\nmodule zbt_6111_sample(beep, audio_reset_b, \n       ^~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'delayN\'\nmodule delayN(clk,in,out);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:401: Signal definition not found, creating implicitly: \'clk\'\n   ramclock rc(.ref_clock(clock_65mhz), .fpga_clock(clk),\n                                                    ^~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:773: Cannot find file containing module: \'BUFG\'\n   BUFG int_buf (.O(fpga_clock), .I(fpga_clk));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/45259609/BWIMAGE,data/full_repos/permissive/45259609/BUFG\n             data/full_repos/permissive/45259609/BWIMAGE,data/full_repos/permissive/45259609/BUFG.v\n             data/full_repos/permissive/45259609/BWIMAGE,data/full_repos/permissive/45259609/BUFG.sv\n             BUFG\n             BUFG.v\n             BUFG.sv\n             obj_dir/BUFG\n             obj_dir/BUFG.v\n             obj_dir/BUFG.sv\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:775: Cannot find file containing module: \'DCM\'\n   DCM int_dcm (.CLKFB(fpga_clock),\n   ^~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:788: Cannot find file containing module: \'BUFG\'\n   BUFG ext_buf (.O(ram_clock), .I(ram_clk));\n   ^~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:790: Cannot find file containing module: \'IBUFG\'\n   IBUFG fb_buf (.O(fb_clk), .I(clock_feedback_in));\n   ^~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:792: Cannot find file containing module: \'DCM\'\n   DCM ext_dcm (.CLKFB(fb_clk), \n   ^~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:805: Cannot find file containing module: \'SRL16\'\n   SRL16 dcm_rst_sr (.D(1\'b0), .CLK(ref_clk), .Q(dcm_reset),\n   ^~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:810: Cannot find file containing module: \'OFDDRRSE\'\n   OFDDRRSE ddr_reg0 (.Q(ram0_clock), .C0(ram_clock), .C1(~ram_clock),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:812: Cannot find file containing module: \'OFDDRRSE\'\n   OFDDRRSE ddr_reg1 (.Q(ram1_clock), .C0(ram_clock), .C1(~ram_clock),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:814: Cannot find file containing module: \'OFDDRRSE\'\n   OFDDRRSE ddr_reg2 (.Q(clock_feedback_out), .C0(ram_clock), .C1(~ram_clock),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:374: Cannot find file containing module: \'DCM\'\n   DCM vclk1(.CLKIN(clock_27mhz),.CLKFX(clock_65mhz_unbuf));\n   ^~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:379: Cannot find file containing module: \'BUFG\'\n   BUFG vclk2(.O(clock_65mhz),.I(clock_65mhz_unbuf));\n   ^~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:410: Cannot find file containing module: \'SRL16\'\n   SRL16 reset_sr (.D(1\'b0), .CLK(clk), .Q(power_on_reset),\n   ^~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:416: Cannot find file containing module: \'debounce\'\n   debounce db1(power_on_reset, clk, ~button_enter, user_reset);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:422: Cannot find file containing module: \'display_16hex\'\n   display_16hex hexdisp1(reset, clk, dispdata,\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:440: Cannot find file containing module: \'zbt_6111\'\n   zbt_6111 zbt1(clk, 1\'b1, vram_we, vram_addr,\n   ^~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:454: Cannot find file containing module: \'adv7185init\'\n   adv7185init adv7185(.reset(reset), .clock_27mhz(clock_27mhz), \n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:463: Cannot find file containing module: \'ntsc_decode\'\n   ntsc_decode decode (.clk(tv_in_line_clock1), .reset(reset),\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:473: Cannot find file containing module: \'ntsc_to_zbt\'\n   ntsc_to_zbt n2z (clk, tv_in_line_clock1, fvh, dv, ycrcb[29:22],\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:481: Operator COND expects 36 bits on the Conditional True, but Conditional True\'s REPLICATE generates 32 bits.\n                                                                                 : ... In instance zbt_6111_sample\n   wire [35:0]  vpat = ( switch[1] ? {4{count[3+3:3],4\'b0}}\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/45259609/BWIMAGE/zbt_6111_sample.v:481: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s REPLICATE generates 32 bits.\n                                                                                 : ... In instance zbt_6111_sample\n   wire [35:0]  vpat = ( switch[1] ? {4{count[3+3:3],4\'b0}}\n                                   ^\n%Error: Exiting due to 18 error(s), 5 warning(s)\n'
module delayN(clk,in,out);
   input clk;
   input in;
   output out;

   parameter NDELAY = 3;

   reg [NDELAY-1:0] shiftreg;
   wire 	    out = shiftreg[NDELAY-1];

   always @(posedge clk)
     shiftreg <= {shiftreg[NDELAY-2:0],in};

endmodule
module delayN(clk,in,out);

   input clk;
   input in;
   output out;

   parameter NDELAY = 3;

   reg [NDELAY-1:0] shiftreg;
   wire 	    out = shiftreg[NDELAY-1];

   always @(posedge clk)
     shiftreg <= {shiftreg[NDELAY-2:0],in};

endmodule