data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/Edgecapture/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/Edgecapture,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Edgecapture/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    input wire [31:0] in,
    output wire [31:0] out
);

  reg [31:0] previous_pin_r = 31'b0;
  reg [31:0] out_r = 31'b0;

  assign out = out_r;

  always @(posedge clk) begin
    if (reset) begin
      out_r = 31'b0;
    end else begin
      out_r <= (previous_pin_r & ~in) | out_r;
    end
    previous_pin_r <= in;
  end

endmodule
module top_module (
    input wire clk,
    input wire reset,
    input wire [31:0] in,
    output wire [31:0] out
);


  reg [31:0] previous_pin_r = 31'b0;
  reg [31:0] out_r = 31'b0;

  assign out = out_r;

  always @(posedge clk) begin
    if (reset) begin
      out_r = 31'b0;
    end else begin
      out_r <= (previous_pin_r & ~in) | out_r;
    end
    previous_pin_r <= in;
  end

endmodule