data/full_repos/permissive/43858668/final_verilog/src/rtr_flit_type_check.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flit_type_check.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flit_type_check.v:41: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_flit_type_check.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 3 error(s)\n'
module rtr_flit_type_check
  (clk, reset, active, flit_valid, flit_head, flit_tail, error);
   
`include "c_constants.v"
   



   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   
   input clk;
   input reset;
   input active;
   
   input flit_valid;
   input flit_head;
   input flit_tail;
   
   output error;
   wire   error;
   
   



   
   wire   packet_active_s, packet_active_q;
   assign packet_active_s = flit_valid ? 
			    ((packet_active_q | flit_head) & ~flit_tail) :
			    packet_active_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   packet_activeq
     (.clk(clk),
      .reset(reset),
      .active(active),
      .d(packet_active_s),
      .q(packet_active_q));
   
   assign error = flit_valid & (flit_head ~^ packet_active_q);
   

   always @(posedge clk)
     begin
	
	if(error)
	  $display("ERROR: Received flit with unexpected type in module %m.");
	
     end

   
endmodule
module rtr_flit_type_check
  (clk, reset, active, flit_valid, flit_head, flit_tail, error);

   
`include "c_constants.v"
   



   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   
   input clk;
   input reset;
   input active;
   
   input flit_valid;
   input flit_head;
   input flit_tail;
   
   output error;
   wire   error;
   
   



   
   wire   packet_active_s, packet_active_q;
   assign packet_active_s = flit_valid ? 
			    ((packet_active_q | flit_head) & ~flit_tail) :
			    packet_active_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   packet_activeq
     (.clk(clk),
      .reset(reset),
      .active(active),
      .d(packet_active_s),
      .q(packet_active_q));
   
   assign error = flit_valid & (flit_head ~^ packet_active_q);
   

   always @(posedge clk)
     begin
	
	if(error)
	  $display("ERROR: Received flit with unexpected type in module %m.");
	
     end

   
endmodule