data/full_repos/permissive/46078519/crt_test.v
1: b'%Error: data/full_repos/permissive/46078519/crt_test.v:2: Cannot find include file: crt.v\n`include "crt.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v.v\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v.sv\n             crt.v\n             crt.v.v\n             crt.v.sv\n             obj_dir/crt.v\n             obj_dir/crt.v.v\n             obj_dir/crt.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/46078519/crt_test.v:40: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("crt_test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/46078519/crt_test.v:41: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, crt_test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:84: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:88: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:90: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hA;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hC;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:94: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:96: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:97: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:101: Unsupported: Ignoring delay on this delayed statement.\n #1320402;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:114: Unsupported: Ignoring delay on this delayed statement.\n #(2201*1125*2*2+30) $finish;\n ^\n%Error: Exiting due to 3 error(s), 26 warning(s)\n'
module crt_ramdac(clk, pixaddr, ven, qpixel, breq, back);

parameter ADDR_SIZE = 32;
localparam PIXEL_SIZE = 32;

input clk;
input [ADDR_SIZE-1:0] pixaddr;
input ven;
output [PIXEL_SIZE-1:0] qpixel;
output breq;
input back;

always @(posedge clk)
begin
	
end

endmodule
module crt_ramdac(clk, pixaddr, ven, qpixel, breq, back);


parameter ADDR_SIZE = 32;
localparam PIXEL_SIZE = 32;

input clk;
input [ADDR_SIZE-1:0] pixaddr;
input ven;
output [PIXEL_SIZE-1:0] qpixel;
output breq;
input back;

always @(posedge clk)
begin
	
end

endmodule