data/full_repos/permissive/490716708/Verilog/MapROM.v
data/verilator_xmls/591c434b-b27f-4838-84fa-497e2932dccb.xml
module MapROM(input wire [7:0] address, output wire [7:0] data_out);
    reg [7:0] memory[0:255];
    initial begin
        $readmemh("roms/CPU-6309.txt", memory);
    end

    assign data_out = memory[address];
endmodule
module MapROM(input wire [7:0] address, output wire [7:0] data_out);

    reg [7:0] memory[0:255];
    initial begin
        $readmemh("roms/CPU-6309.txt", memory);
    end

    assign data_out = memory[address];
endmodule