data/full_repos/permissive/471089853/src/dspblock_6x6_f400_uid35.v
data/verilator_xmls/a27a68a2-18cf-4667-b265-747ae11e2497.xml
module DSPBlock_6x6_F400_uid35(clk, X, Y, R);
  wire [11:0] _0_;
  output [11:0] R;
  input [5:0] X;
  input [5:0] Y;
  input clk;
  wire [11:0] m;
  wire [11:0] mint;
  wire [11:0] rtmp;
  assign _0_ = $signed({ 6'h00, X }) * $signed({ 6'h00, Y });
  assign mint = _0_;
  assign m = mint;
  assign rtmp = m;
  assign R = rtmp;
endmodule
module DSPBlock_6x6_F400_uid35(clk, X, Y, R);

  wire [11:0] _0_;
  output [11:0] R;
  input [5:0] X;
  input [5:0] Y;
  input clk;
  wire [11:0] m;
  wire [11:0] mint;
  wire [11:0] rtmp;
  assign _0_ = $signed({ 6'h00, X }) * $signed({ 6'h00, Y });
  assign mint = _0_;
  assign m = mint;
  assign rtmp = m;
  assign R = rtmp;
endmodule