data/full_repos/permissive/418749135/ripple_tb.v
1: b'%Error: data/full_repos/permissive/418749135/ripple_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/ripple_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418749135/ripple_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/ripple_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/ripple_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/ripple_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/ripple_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

  reg clk, reset;
  wire [3:0] q;
  

  ripple_carry_counter rcc (q, clk, reset);
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, test);
    

    clk = 1'b0;
    

    reset = 1'b1;
    #10 reset = 1'b0;
    
    #200;
    reset = 1'b1;
    #10 reset = 1'b0;
    
    #50;
    $finish;
  end
  
  always #5 clk = ~clk;

endmodule
module test;


  reg clk, reset;
  wire [3:0] q;
  

  ripple_carry_counter rcc (q, clk, reset);
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, test);
    

    clk = 1'b0;
    

    reset = 1'b1;
    #10 reset = 1'b0;
    
    #200;
    reset = 1'b1;
    #10 reset = 1'b0;
    
    #50;
    $finish;
  end
  
  always #5 clk = ~clk;

endmodule