data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:25: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'BUF\'\nmodule BUF (input in, output out);\n       ^~~\n                                                                                           : ... Top module \'TRIBUF\'\nmodule TRIBUF(input in, enable, output out);\n       ^~~~~~\n                                                                                           : ... Top module \'INV\'\nmodule INV(input in, output out);\n       ^~~\n                                                                                           : ... Top module \'AND2\'\nmodule AND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'AND3\'\nmodule AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'AND4\'\nmodule AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'OR2\'\nmodule OR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~\n                                                                                           : ... Top module \'OR3\'\nmodule OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~\n                                                                                           : ... Top module \'OR4\'\nmodule OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~\n                                                                                           : ... Top module \'NAND2\'\nmodule NAND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'NAND3\'\nmodule NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'NAND4\'\nmodule NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'NOR2\'\nmodule NOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'NOR3\'\nmodule NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'NOR4\'\nmodule NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'XOR2\'\nmodule XOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'XOR3\'\nmodule XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'XOR4\'\nmodule XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~~\n                                                                                           : ... Top module \'XNOR2\'\nmodule XNOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'XNOR3\'\nmodule XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'XNOR4\'\nmodule XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);\n       ^~~~~\n                                                                                           : ... Top module \'DEC1\'\nmodule DEC1 (input in, enable, output reg [1:0] out);\n       ^~~~\n                                                                                           : ... Top module \'DEC2\'\nmodule DEC2 (input [1:0] in, input enable, output reg [3:0] out);\n       ^~~~\n                                                                                           : ... Top module \'DEC3\'\nmodule DEC3 (input [2:0] in, input enable, output reg [7:0] out);\n       ^~~~\n                                                                                           : ... Top module \'DEC4\'\nmodule DEC4 (input [3:0] in, input enable, output reg [15:0] out);\n       ^~~~\n                                                                                           : ... Top module \'DEC5\'\nmodule DEC5 (input [4:0] in, input enable, output reg [31:0] out);\n       ^~~~\n                                                                                           : ... Top module \'DEC6\'\nmodule DEC6 (input [5:0] in, input enable, output reg [63:0] out);\n       ^~~~\n                                                                                           : ... Top module \'MUX2\'\nmodule MUX2(input [1:0] in, input select, output reg out);\n       ^~~~\n                                                                                           : ... Top module \'MUX4\'\nmodule MUX4(input [3:0] in, input [1:0] select, output reg out);\n       ^~~~\n                                                                                           : ... Top module \'MUX8\'\nmodule MUX8(input [7:0] in, input [2:0] select, output reg out);\n       ^~~~\n                                                                                           : ... Top module \'MUX16\'\nmodule MUX16(input [15:0] in, input [3:0] select, output reg out);\n       ^~~~~\n                                                                                           : ... Top module \'MUX32\'\nmodule MUX32(input [31:0] in, input [4:0] select, output reg out);\n       ^~~~~\n                                                                                           : ... Top module \'MUX64\'\nmodule MUX64(input [63:0] in, input [5:0] select, output reg out);\n       ^~~~~\n                                                                                           : ... Top module \'ADD1\'\nmodule ADD1(input in1, in2, cin, output out, cout);\n       ^~~~\n                                                                                           : ... Top module \'ADD2\'\nmodule ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'ADD4\'\nmodule ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'ADD8\'\nmodule ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'ADD16\'\nmodule ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'ADD32\'\nmodule ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'ADD64\'\nmodule ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'SUB1\'\nmodule SUB1(input in1, in2, cin, output out, cout);\n       ^~~~\n                                                                                           : ... Top module \'SUB2\'\nmodule SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'SUB4\'\nmodule SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'SUB8\'\nmodule SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'SUB16\'\nmodule SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'SUB32\'\nmodule SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'SUB64\'\nmodule SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'MUL1\'\nmodule MUL1 #(parameter SIZE = 1)(input in1, in2, output [2*SIZE-1:0] out);\n       ^~~~\n                                                                                           : ... Top module \'MUL2\'\nmodule MUL2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~\n                                                                                           : ... Top module \'MUL4\'\nmodule MUL4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~\n                                                                                           : ... Top module \'MUL8\'\nmodule MUL8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~\n                                                                                           : ... Top module \'MUL16\'\nmodule MUL16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~~\n                                                                                           : ... Top module \'MUL32\'\nmodule MUL32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~~\n                                                                                           : ... Top module \'MUL64\'\nmodule MUL64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);\n       ^~~~~\n                                                                                           : ... Top module \'DIV1\'\nmodule DIV1 #(parameter SIZE = 1)(input in1, in2, output out, rem);\n       ^~~~\n                                                                                           : ... Top module \'DIV2\'\nmodule DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'DIV4\'\nmodule DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'DIV8\'\nmodule DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'DIV16\'\nmodule DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'DIV32\'\nmodule DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'DIV64\'\nmodule DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'FF\'\nmodule FF (input d, clk, output reg q);\n       ^~\n                                                                                           : ... Top module \'RFF\'\nmodule RFF(input d, clk, reset, output reg q);\n       ^~~\n                                                                                           : ... Top module \'SFF\'\nmodule SFF(input d, clk, set, output reg q);\n       ^~~\n                                                                                           : ... Top module \'RSFF\'\nmodule RSFF(input d, clk, set, reset, output reg q);\n       ^~~~\n                                                                                           : ... Top module \'SRFF\'\nmodule SRFF(input d, clk, set, reset, output reg q);\n       ^~~~\n                                                                                           : ... Top module \'LATCH\'\nmodule LATCH(input d, enable, output reg q);\n       ^~~~~\n                                                                                           : ... Top module \'RLATCH\'\nmodule RLATCH(input d, reset, enable, output reg q);\n       ^~~~~~\n                                                                                           : ... Top module \'LSHIFT1\'\nmodule LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);\n       ^~~~~~~\n                                                                                           : ... Top module \'LSHIFT2\'\nmodule LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'LSHIFT4\'\nmodule LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'LSHIFT8\'\nmodule LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'LSHIFT16\'\nmodule LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'LSHIFT32\'\nmodule LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'LSHIFT64\'\nmodule LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'RSHIFT1\'\nmodule RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);\n       ^~~~~~~\n                                                                                           : ... Top module \'RSHIFT2\'\nmodule RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'RSHIFT4\'\nmodule RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'RSHIFT8\'\nmodule RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, \n       ^~~~~~~\n                                                                                           : ... Top module \'RSHIFT16\'\nmodule RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'RSHIFT32\'\nmodule RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'RSHIFT64\'\nmodule RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, \n       ^~~~~~~~\n                                                                                           : ... Top module \'CMP1\'\nmodule CMP1 #(parameter SIZE = 1) (input in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'CMP2\'\nmodule CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'CMP4\'\nmodule CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'CMP8\'\nmodule CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, \n       ^~~~\n                                                                                           : ... Top module \'CMP16\'\nmodule CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'CMP32\'\nmodule CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'CMP64\'\nmodule CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, \n       ^~~~~\n                                                                                           : ... Top module \'VCC\'\nmodule VCC (output supply1 out);\n       ^~~\n                                                                                           : ... Top module \'GND\'\nmodule GND (output supply0 out);\n       ^~~\n                                                                                           : ... Top module \'INC1\'\nmodule INC1 #(parameter SIZE = 1) (input in, output [SIZE:0] out);\n       ^~~~\n                                                                                           : ... Top module \'INC2\'\nmodule INC2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~\n                                                                                           : ... Top module \'INC4\'\nmodule INC4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~\n                                                                                           : ... Top module \'INC8\'\nmodule INC8 #(parameter SIZE = 8) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~\n                                                                                           : ... Top module \'INC16\'\nmodule INC16 #(parameter SIZE = 16) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~~\n                                                                                           : ... Top module \'INC32\'\nmodule INC32 #(parameter SIZE = 32) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~~\n                                                                                           : ... Top module \'INC64\'\nmodule INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:910: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s REPLICATE generates 63 bits.\n                                                                                         : ... In instance RSHIFT64\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:899: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s REPLICATE generates 31 bits.\n                                                                                         : ... In instance RSHIFT32\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:887: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s REPLICATE generates 15 bits.\n                                                                                         : ... In instance RSHIFT16\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:875: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s REPLICATE generates 7 bits.\n                                                                                         : ... In instance RSHIFT8\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:864: Operator SHIFTL expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n                                                                                         : ... In instance RSHIFT4\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:851: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s REPLICATE generates 1 bits.\n                                                                                         : ... In instance RSHIFT2\n     out = out | ({SIZE-1 {1\'b1} } << (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:829: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s REPLICATE generates 63 bits.\n                                                                                         : ... In instance LSHIFT64\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:819: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s REPLICATE generates 31 bits.\n                                                                                         : ... In instance LSHIFT32\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:809: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s REPLICATE generates 15 bits.\n                                                                                         : ... In instance LSHIFT16\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:799: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s REPLICATE generates 7 bits.\n                                                                                         : ... In instance LSHIFT8\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:788: Operator SHIFTR expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n                                                                                         : ... In instance LSHIFT4\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:778: Operator SHIFTR expects 2 bits on the LHS, but LHS\'s REPLICATE generates 1 bits.\n                                                                                         : ... In instance LSHIFT2\n     out = out | ({SIZE-1 {1\'b1} } >> (SIZE-1-shift));\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:601: Operator SUB expects 65 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB64\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:595: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB32\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:588: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB16\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:581: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB8\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:574: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB4\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:567: Operator SUB expects 3 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance SUB2\nassign {cout, out} = in1 - in2 - cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:554: Operator ADD expects 65 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD64\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:548: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD32\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:541: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD16\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD8\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:527: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD4\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/hana_vlib.v:520: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                         : ... In instance ADD2\nassign {cout, out} = in1 + in2 + cin;\n                               ^\n%Error: Exiting due to 25 warning(s)\n'
module DEC6 (input [5:0] in, input enable, output reg [63:0] out);

always @(in or enable)
    if(!enable)
	    out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
	else begin
	   case (in)
	       6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
	       6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
	       6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
	       6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
	       6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
	       6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
	       6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
	       6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
	       6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
	       6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
	       6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
	       6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
	       6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
	       6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
	       6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
	       6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
	       6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
	       6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
	       6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
	       6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
	       6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
	       6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
	       6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
	       6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
	       6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
	       6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
	       6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
	       6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
	       6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
	       6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
	       6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
	       6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;

	       6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
	       6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
	       6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
	       6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
	       6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
	       6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
	       6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
	       6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
	       6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
	       6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
	       6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
	       6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
	       6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
	       6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
	       6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
	       6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
	       6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
	       6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
	       6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
	       6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
	       6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
	       6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
	       6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
	       6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
	       6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
	       6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
	       6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
	       6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
	       6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
	       6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
	       6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
	       6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
	    endcase
	end
endmodule
module DEC6 (input [5:0] in, input enable, output reg [63:0] out);


always @(in or enable)
    if(!enable)
	    out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
	else begin
	   case (in)
	       6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
	       6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
	       6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
	       6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
	       6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
	       6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
	       6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
	       6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
	       6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
	       6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
	       6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
	       6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
	       6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
	       6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
	       6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
	       6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
	       6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
	       6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
	       6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
	       6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
	       6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
	       6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
	       6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
	       6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
	       6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
	       6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
	       6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
	       6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
	       6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
	       6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
	       6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
	       6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;

	       6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
	       6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
	       6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
	       6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
	       6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
	       6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
	       6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
	       6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
	       6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
	       6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
	       6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
	       6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
	       6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
	       6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
	       6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
	       6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
	       6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
	       6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
	       6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
	       6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
	       6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
	       6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
	       6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
	       6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
	       6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
	       6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
	       6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
	       6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
	       6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
	       6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
	       6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
	       6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
	    endcase
	end
endmodule