data/full_repos/permissive/463204869/units/util/source/rtl/verilog/util_reset_sync.v
1: b"%Error: data/full_repos/permissive/463204869/units/util/source/rtl/verilog/util_reset_sync.v:11: Cannot find file containing module: 'util_sync'\n    util_sync i_util_sync (\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/util/source/rtl/verilog,data/full_repos/permissive/463204869/util_sync\n             data/full_repos/permissive/463204869/units/util/source/rtl/verilog,data/full_repos/permissive/463204869/util_sync.v\n             data/full_repos/permissive/463204869/units/util/source/rtl/verilog,data/full_repos/permissive/463204869/util_sync.sv\n             util_sync\n             util_sync.v\n             util_sync.sv\n             obj_dir/util_sync\n             obj_dir/util_sync.v\n             obj_dir/util_sync.sv\n%Error: Exiting due to 1 error(s)\n"
module util_reset_sync (
    input  wire clk_i,
    input  wire reset_q_i,
    input  wire scan_mode_i,
    output wire sync_reset_q_o
);

    wire reset_release_sync;

    util_sync i_util_sync (
        .clk_i     (clk_i),
        .reset_n_i (reset_q_i),
        .data_i    (1'b1),
        .data_o    (reset_release_sync)
    );

    assign sync_reset_q_o = (scan_mode_i) ? reset_q_i : reset_release_sync;


endmodule
module util_reset_sync (
    input  wire clk_i,
    input  wire reset_q_i,
    input  wire scan_mode_i,
    output wire sync_reset_q_o
);


    wire reset_release_sync;

    util_sync i_util_sync (
        .clk_i     (clk_i),
        .reset_n_i (reset_q_i),
        .data_i    (1'b1),
        .data_o    (reset_release_sync)
    );

    assign sync_reset_q_o = (scan_mode_i) ? reset_q_i : reset_release_sync;


endmodule