data/full_repos/permissive/481069643/Day01/LogicalUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481069643/Day01/LogicalUnit.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                           : ... In instance LogicalUnit\ndefault: out_logical = 3\'d0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LogicalUnit(in_a,in_b,fun,out_logical);

input [3:0]in_a,in_b;
input [2:0]fun;
output reg [3:0]out_logical;

always @(*)
begin

case(fun)
3'd0: out_logical = in_a & in_b;
3'd1: out_logical = in_a | in_b;
3'd2: out_logical = ~(in_a & in_b);
3'd3: out_logical = ~(in_a | in_b);
3'd4: out_logical = in_a ^ in_b;
3'd5: out_logical = ~in_a;
default: out_logical = 3'd0;
endcase

end
endmodule
module LogicalUnit(in_a,in_b,fun,out_logical);


input [3:0]in_a,in_b;
input [2:0]fun;
output reg [3:0]out_logical;

always @(*)
begin

case(fun)
3'd0: out_logical = in_a & in_b;
3'd1: out_logical = in_a | in_b;
3'd2: out_logical = ~(in_a & in_b);
3'd3: out_logical = ~(in_a | in_b);
3'd4: out_logical = in_a ^ in_b;
3'd5: out_logical = ~in_a;
default: out_logical = 3'd0;
endcase

end
endmodule