data/full_repos/permissive/409594175/made/Concatenate28to32.v
data/verilator_xmls/4152f5b3-c9fb-4f65-b139-65a441af0f87.xml
module Concatenate28to32(
    input   wire   [31:0]   PC,
    input   wire   [27:0]   Shift_left_out,
    output  wire   [31:0]   Concatenated_32
);

    assign Concatenated_32 = {PC[31:28], Shift_left_out};

endmodule
module Concatenate28to32(
    input   wire   [31:0]   PC,
    input   wire   [27:0]   Shift_left_out,
    output  wire   [31:0]   Concatenated_32
);


    assign Concatenated_32 = {PC[31:28], Shift_left_out};

endmodule