data/full_repos/permissive/495609183/memLCDdriver/src/clockdiv.v
data/verilator_xmls/f0634ef9-bd7a-4fba-841f-ddc6327420e6.xml
module clockdiv #(
	parameter SIZE = 32,
	parameter DIVISOR = 16
)(
    input i_clk,
    input i_reset,

    output reg o_clk_div

 );

	reg [SIZE-1:0] counter;

	always @(posedge i_clk or posedge i_reset) begin
		if (i_reset) begin
			counter <= 0;
			o_clk_div <= 1'b0;
		end else begin
			counter <= counter + 1'b1;
			if (counter == DIVISOR/2) begin
				o_clk_div <= !o_clk_div;
				counter <= 0;
			end
		end
	end

endmodule
module clockdiv #(
	parameter SIZE = 32,
	parameter DIVISOR = 16
)(
    input i_clk,
    input i_reset,

    output reg o_clk_div

 );


	reg [SIZE-1:0] counter;

	always @(posedge i_clk or posedge i_reset) begin
		if (i_reset) begin
			counter <= 0;
			o_clk_div <= 1'b0;
		end else begin
			counter <= counter + 1'b1;
			if (counter == DIVISOR/2) begin
				o_clk_div <= !o_clk_div;
				counter <= 0;
			end
		end
	end

endmodule