data/full_repos/permissive/474582223/MUX/twoByOne/tf.v
1: b'%Error: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:22: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:23: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);  \n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:25: Unsupported: Ignoring delay on this delayed statement.\n  I0 = 0; I1 = 0; S0 = 0; #100;\n                          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:26: Unsupported: Ignoring delay on this delayed statement.\n      I0 = 0; I1 = 0; S0 = 1; #100;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:27: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 0; I1 = 1; S0 = 0; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:28: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 0; I1 = 1; S0 = 1; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:29: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 1; I1 = 0; S0 = 0; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:30: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 1; I1 = 0; S0 = 1; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:31: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 1; I1 = 1; S0 = 0; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/twoByOne/tf.v:32: Unsupported: Ignoring delay on this delayed statement.\n       I0 = 1; I1 = 1; S0 = 1; #100;\n                               ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module twobymux;


	reg I0;
	reg I1;
  	reg S0;


	wire Y;


	twobyonemux uut (
      	.I0(I0), 
      	.I1(I1), 
      	.S0(S0),
      	.Y(Y)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

		I0 = 0; I1 = 0; S0 = 0; #100;
     	I0 = 0; I1 = 0; S0 = 1; #100;
      	I0 = 0; I1 = 1; S0 = 0; #100;
      	I0 = 0; I1 = 1; S0 = 1; #100;
      	I0 = 1; I1 = 0; S0 = 0; #100;
      	I0 = 1; I1 = 0; S0 = 1; #100;
      	I0 = 1; I1 = 1; S0 = 0; #100;
      	I0 = 1; I1 = 1; S0 = 1; #100;
	end
endmodule
module twobymux;



	reg I0;
	reg I1;
  	reg S0;


	wire Y;


	twobyonemux uut (
      	.I0(I0), 
      	.I1(I1), 
      	.S0(S0),
      	.Y(Y)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

		I0 = 0; I1 = 0; S0 = 0; #100;
     	I0 = 0; I1 = 0; S0 = 1; #100;
      	I0 = 0; I1 = 1; S0 = 0; #100;
      	I0 = 0; I1 = 1; S0 = 1; #100;
      	I0 = 1; I1 = 0; S0 = 0; #100;
      	I0 = 1; I1 = 0; S0 = 1; #100;
      	I0 = 1; I1 = 1; S0 = 0; #100;
      	I0 = 1; I1 = 1; S0 = 1; #100;
	end
endmodule