data/full_repos/permissive/493019833/test/testcase/firrtl/Complex3R3WSMem/sbt/Complex3R3WSMem.v
data/verilator_xmls/bfc4ed01-1967-45b7-8f76-aa96edb8ddb9.xml
module Complex3R3WSMem(
  input        clock,
  input        reset,
  input  [3:0] io_rdAddr,
  output [7:0] io_rdData,
  input  [3:0] io_rdAddr2,
  output [7:0] io_rdData2,
  input  [3:0] io_rdAddr3,
  output [7:0] io_rdData3,
  input        io_wrEna,
  input  [7:0] io_wrData,
  input  [3:0] io_wrAddr,
  input        io_wrEna2,
  input  [7:0] io_wrData2,
  input  [3:0] io_wrAddr2,
  input        io_wrEna3,
  input  [7:0] io_wrData3,
  input  [3:0] io_wrAddr3
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [7:0] mem [0:15];
  wire  mem__T_37_en;
  wire [3:0] mem__T_37_addr;
  wire [7:0] mem__T_37_data;
  wire  mem__T_38_en;
  wire [3:0] mem__T_38_addr;
  wire [7:0] mem__T_38_data;
  wire  mem__T_39_en;
  wire [3:0] mem__T_39_addr;
  wire [7:0] mem__T_39_data;
  wire [7:0] mem__T_40_data;
  wire [3:0] mem__T_40_addr;
  wire  mem__T_40_mask;
  wire  mem__T_40_en;
  wire [7:0] mem__T_41_data;
  wire [3:0] mem__T_41_addr;
  wire  mem__T_41_mask;
  wire  mem__T_41_en;
  wire [7:0] mem__T_42_data;
  wire [3:0] mem__T_42_addr;
  wire  mem__T_42_mask;
  wire  mem__T_42_en;
  reg [3:0] mem__T_37_addr_pipe_0;
  reg [3:0] mem__T_38_addr_pipe_0;
  reg [3:0] mem__T_39_addr_pipe_0;
  assign mem__T_37_en = 1'h1;
  assign mem__T_37_addr = mem__T_37_addr_pipe_0;
  assign mem__T_37_data = mem[mem__T_37_addr];
  assign mem__T_38_en = 1'h1;
  assign mem__T_38_addr = mem__T_38_addr_pipe_0;
  assign mem__T_38_data = mem[mem__T_38_addr];
  assign mem__T_39_en = 1'h1;
  assign mem__T_39_addr = mem__T_39_addr_pipe_0;
  assign mem__T_39_data = mem[mem__T_39_addr];
  assign mem__T_40_data = io_wrData;
  assign mem__T_40_addr = io_wrAddr;
  assign mem__T_40_mask = 1'h1;
  assign mem__T_40_en = io_wrEna;
  assign mem__T_41_data = io_wrData2;
  assign mem__T_41_addr = io_wrAddr2;
  assign mem__T_41_mask = 1'h1;
  assign mem__T_41_en = io_wrEna2;
  assign mem__T_42_data = io_wrData3;
  assign mem__T_42_addr = io_wrAddr3;
  assign mem__T_42_mask = 1'h1;
  assign mem__T_42_en = io_wrEna3;
  assign io_rdData = mem__T_37_data;
  assign io_rdData2 = mem__T_38_data;
  assign io_rdData3 = mem__T_39_data;
  always @(posedge clock) begin
    if (mem__T_40_en & mem__T_40_mask) begin
      mem[mem__T_40_addr] <= mem__T_40_data;
    end
    if (mem__T_41_en & mem__T_41_mask) begin
      mem[mem__T_41_addr] <= mem__T_41_data;
    end
    if (mem__T_42_en & mem__T_42_mask) begin
      mem[mem__T_42_addr] <= mem__T_42_data;
    end
    mem__T_37_addr_pipe_0 <= io_rdAddr;
    mem__T_38_addr_pipe_0 <= io_rdAddr2;
    mem__T_39_addr_pipe_0 <= io_rdAddr3;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    mem[initvar] = _RAND_0[7:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  mem__T_37_addr_pipe_0 = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  mem__T_38_addr_pipe_0 = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  mem__T_39_addr_pipe_0 = _RAND_3[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Complex3R3WSMem(
  input        clock,
  input        reset,
  input  [3:0] io_rdAddr,
  output [7:0] io_rdData,
  input  [3:0] io_rdAddr2,
  output [7:0] io_rdData2,
  input  [3:0] io_rdAddr3,
  output [7:0] io_rdData3,
  input        io_wrEna,
  input  [7:0] io_wrData,
  input  [3:0] io_wrAddr,
  input        io_wrEna2,
  input  [7:0] io_wrData2,
  input  [3:0] io_wrAddr2,
  input        io_wrEna3,
  input  [7:0] io_wrData3,
  input  [3:0] io_wrAddr3
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [7:0] mem [0:15];
  wire  mem__T_37_en;
  wire [3:0] mem__T_37_addr;
  wire [7:0] mem__T_37_data;
  wire  mem__T_38_en;
  wire [3:0] mem__T_38_addr;
  wire [7:0] mem__T_38_data;
  wire  mem__T_39_en;
  wire [3:0] mem__T_39_addr;
  wire [7:0] mem__T_39_data;
  wire [7:0] mem__T_40_data;
  wire [3:0] mem__T_40_addr;
  wire  mem__T_40_mask;
  wire  mem__T_40_en;
  wire [7:0] mem__T_41_data;
  wire [3:0] mem__T_41_addr;
  wire  mem__T_41_mask;
  wire  mem__T_41_en;
  wire [7:0] mem__T_42_data;
  wire [3:0] mem__T_42_addr;
  wire  mem__T_42_mask;
  wire  mem__T_42_en;
  reg [3:0] mem__T_37_addr_pipe_0;
  reg [3:0] mem__T_38_addr_pipe_0;
  reg [3:0] mem__T_39_addr_pipe_0;
  assign mem__T_37_en = 1'h1;
  assign mem__T_37_addr = mem__T_37_addr_pipe_0;
  assign mem__T_37_data = mem[mem__T_37_addr];
  assign mem__T_38_en = 1'h1;
  assign mem__T_38_addr = mem__T_38_addr_pipe_0;
  assign mem__T_38_data = mem[mem__T_38_addr];
  assign mem__T_39_en = 1'h1;
  assign mem__T_39_addr = mem__T_39_addr_pipe_0;
  assign mem__T_39_data = mem[mem__T_39_addr];
  assign mem__T_40_data = io_wrData;
  assign mem__T_40_addr = io_wrAddr;
  assign mem__T_40_mask = 1'h1;
  assign mem__T_40_en = io_wrEna;
  assign mem__T_41_data = io_wrData2;
  assign mem__T_41_addr = io_wrAddr2;
  assign mem__T_41_mask = 1'h1;
  assign mem__T_41_en = io_wrEna2;
  assign mem__T_42_data = io_wrData3;
  assign mem__T_42_addr = io_wrAddr3;
  assign mem__T_42_mask = 1'h1;
  assign mem__T_42_en = io_wrEna3;
  assign io_rdData = mem__T_37_data;
  assign io_rdData2 = mem__T_38_data;
  assign io_rdData3 = mem__T_39_data;
  always @(posedge clock) begin
    if (mem__T_40_en & mem__T_40_mask) begin
      mem[mem__T_40_addr] <= mem__T_40_data;
    end
    if (mem__T_41_en & mem__T_41_mask) begin
      mem[mem__T_41_addr] <= mem__T_41_data;
    end
    if (mem__T_42_en & mem__T_42_mask) begin
      mem[mem__T_42_addr] <= mem__T_42_data;
    end
    mem__T_37_addr_pipe_0 <= io_rdAddr;
    mem__T_38_addr_pipe_0 <= io_rdAddr2;
    mem__T_39_addr_pipe_0 <= io_rdAddr3;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    mem[initvar] = _RAND_0[7:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  mem__T_37_addr_pipe_0 = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  mem__T_38_addr_pipe_0 = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  mem__T_39_addr_pipe_0 = _RAND_3[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule