data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #(half_period) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #(4*half_period);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #(2*half_period);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #7;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #(200*half_period);\n    ^\n%Error: data/full_repos/permissive/458313092/UART_TX/UART_TX_tb.v:11: Cannot find file containing module: \'UART_TX\'\nUART_TX #(.clock_per_bit(clock_per_bit_uart)) UUT (.clk(clk), .data_in(data_in), .data_ready(data_ready),\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458313092/UART_TX,data/full_repos/permissive/458313092/UART_TX\n             data/full_repos/permissive/458313092/UART_TX,data/full_repos/permissive/458313092/UART_TX.v\n             data/full_repos/permissive/458313092/UART_TX,data/full_repos/permissive/458313092/UART_TX.sv\n             UART_TX\n             UART_TX.v\n             UART_TX.sv\n             obj_dir/UART_TX\n             obj_dir/UART_TX.v\n             obj_dir/UART_TX.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_TX_tb;
localparam half_period = 4;
localparam clock_per_bit_uart = 10;	
wire TX_out , TX_busy;
reg [7:0] data_in;
reg clk = 1'b0;
reg data_ready = 1'b0;

UART_TX #(.clock_per_bit(clock_per_bit_uart)) UUT (.clk(clk), .data_in(data_in), .data_ready(data_ready),
                                                     .TX_out(TX_out),.TX_busy(TX_busy));

always
    begin
        #(half_period) clk = ~clk;
    end

always  begin
    #(4*half_period);
    data_in = 8'b10101010;
    #1;
    data_ready = 1'b1;
    #(2*half_period);
    data_ready = 1'b0;
    #7;

    #(200*half_period);
	$finish;
end




endmodule
module UART_TX_tb;

localparam half_period = 4;
localparam clock_per_bit_uart = 10;	
wire TX_out , TX_busy;
reg [7:0] data_in;
reg clk = 1'b0;
reg data_ready = 1'b0;

UART_TX #(.clock_per_bit(clock_per_bit_uart)) UUT (.clk(clk), .data_in(data_in), .data_ready(data_ready),
                                                     .TX_out(TX_out),.TX_busy(TX_busy));

always
    begin
        #(half_period) clk = ~clk;
    end

always  begin
    #(4*half_period);
    data_in = 8'b10101010;
    #1;
    data_ready = 1'b1;
    #(2*half_period);
    data_ready = 1'b0;
    #7;

    #(200*half_period);
	$finish;
end




endmodule