data/full_repos/permissive/428601773/tb/tb_alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:58: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b01_10_00; #10; \n                                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:61: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b01_10_01; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:64: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b10_11_11; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:67: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b10_11_10; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:70: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b01_01_01; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:73: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b10_01_00; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:76: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b10_01_01; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:79: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b10_01_11; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:82: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_00_00; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:85: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_00_01; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:88: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_10_10; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:91: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_10_11; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:94: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_11_00; #10; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_alu.v:97: Unsupported: Ignoring delay on this delayed statement.\n        Operation = 6\'b00_11_01; #10; \n                                 ^\n%Error: data/full_repos/permissive/428601773/tb/tb_alu.v:103: Cannot find file containing module: \'alu_mirisc_v\'\nalu_mirisc_v alu_inst0 (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/alu_mirisc_v\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/alu_mirisc_v.v\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/alu_mirisc_v.sv\n             alu_mirisc_v\n             alu_mirisc_v.v\n             alu_mirisc_v.sv\n             obj_dir/alu_mirisc_v\n             obj_dir/alu_mirisc_v.v\n             obj_dir/alu_mirisc_v.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_alu();
    
reg [31: 0]  A, B;
reg [5: 0]   Operation;
wire [31: 0] Result;
wire         flag;

integer seed,i;
initial begin 
    for (i = 0; i < 6; i = i + 1) begin
        $display("\nTest %0d:", i);
        A = $random; 
        B = $random;
        
        Operation = `ALU_ADD; #10; 
        $display("%0d  + %0d = %0d, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_SUB; #10; 
        $display("%0d  - %0d = %0d, flag = %u", A, B, Result, flag);
       
        Operation = `ALU_XOR; #10; 
        $display("%b  ^ %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_OR; #10; 
        $display("%b  | %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_AND; #10; 
        $display("%b  & %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_SRA; #10; 
        $display("%b  >>> %0d = %b, flag = %u", $signed(A), $signed(B), $signed(Result), flag);
        
        Operation = `ALU_SRL; #10; 
        $display("%b  >> %0d = %b, flag = %u", A, B, Result, flag);
       
        Operation = `ALU_SLL; #10; 
        $display("%b  << %0d = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_LTS; #10; 
        $display("%0d  < %0d = %u, flag = %u", $signed(A), $signed(B), Result[0], flag);
        
        Operation = `ALU_LTU; #10; 
        $display("%0d  < %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_GES; #10; 
        $display("%0d  >= %0d = %u, flag = %u", $signed(A), $signed(B), Result[0], flag);
        
        Operation = `ALU_GEU; #10; 
        $display("%0d  >= %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_EQ; #10; 
        $display("%0d  == %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_NE; #10; 
        $display("%0d  =! %0d = %u, flag = %u", A, B, Result[0], flag);
    end 
    $finish;
end

alu_mirisc_v alu_inst0 (
    .operand_A(A),
    .operand_B(B),
    .operation(Operation),
    .result(Result),
    .flag(flag)
);

endmodule
module tb_alu();

    
reg [31: 0]  A, B;
reg [5: 0]   Operation;
wire [31: 0] Result;
wire         flag;

integer seed,i;
initial begin 
    for (i = 0; i < 6; i = i + 1) begin
        $display("\nTest %0d:", i);
        A = $random; 
        B = $random;
        
        Operation = `ALU_ADD; #10; 
        $display("%0d  + %0d = %0d, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_SUB; #10; 
        $display("%0d  - %0d = %0d, flag = %u", A, B, Result, flag);
       
        Operation = `ALU_XOR; #10; 
        $display("%b  ^ %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_OR; #10; 
        $display("%b  | %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_AND; #10; 
        $display("%b  & %b = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_SRA; #10; 
        $display("%b  >>> %0d = %b, flag = %u", $signed(A), $signed(B), $signed(Result), flag);
        
        Operation = `ALU_SRL; #10; 
        $display("%b  >> %0d = %b, flag = %u", A, B, Result, flag);
       
        Operation = `ALU_SLL; #10; 
        $display("%b  << %0d = %b, flag = %u", A, B, Result, flag);
        
        Operation = `ALU_LTS; #10; 
        $display("%0d  < %0d = %u, flag = %u", $signed(A), $signed(B), Result[0], flag);
        
        Operation = `ALU_LTU; #10; 
        $display("%0d  < %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_GES; #10; 
        $display("%0d  >= %0d = %u, flag = %u", $signed(A), $signed(B), Result[0], flag);
        
        Operation = `ALU_GEU; #10; 
        $display("%0d  >= %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_EQ; #10; 
        $display("%0d  == %0d = %u, flag = %u", A, B, Result[0], flag);
        
        Operation = `ALU_NE; #10; 
        $display("%0d  =! %0d = %u, flag = %u", A, B, Result[0], flag);
    end 
    $finish;
end

alu_mirisc_v alu_inst0 (
    .operand_A(A),
    .operand_B(B),
    .operation(Operation),
    .result(Result),
    .flag(flag)
);

endmodule