data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/cluster_clock_gating_xilinx.sv
data/verilator_xmls/0294a61e-b6da-4faa-b814-a918e6594d3d.xml
module cluster_clock_gating
  (
   input  logic clk_i,
   input  logic en_i,
   input  logic test_en_i,
   output logic clk_o
   );

   assign clk_o = clk_i;
   
endmodule
module cluster_clock_gating
  (
   input  logic clk_i,
   input  logic en_i,
   input  logic test_en_i,
   output logic clk_o
   );


   assign clk_o = clk_i;
   
endmodule