data/full_repos/permissive/505451992/PWM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1;#5\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        reset = 0;#5;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        reset = 0;#5;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n       forever #488 CLK_PWM=~CLK_PWM;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n       #500\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n         #1024000\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n              #1024000\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n                #1024000\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/PWM_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n                #1024000\n                ^\n%Error: data/full_repos/permissive/505451992/PWM_tb.v:32: Cannot find file containing module: \'PWM_Generator\'\nPWM_Generator pgc(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/PWM_Generator\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/PWM_Generator.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/PWM_Generator.sv\n             PWM_Generator\n             PWM_Generator.v\n             PWM_Generator.sv\n             obj_dir/PWM_Generator\n             obj_dir/PWM_Generator.v\n             obj_dir/PWM_Generator.sv\n%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_tb.v:43: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh257\' generates 32 or 10 bits.\n                                                                : ... In instance PWM_tb\n        PPR = 599;\n            ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PWM_tb(
);
wire PWM_CD;
reg reset;
reg PPR;
reg[9:0] Position_CD;
reg rate;
reg CLK_PWM;

PWM_Generator pgc(
.reset(reset),
.CLK(CLK_PWM),
.PPR(PPR),
.Position(Position_CD),
.f(rate),
.pwm(PWM_CD)
    );  
   
    
     initial begin
        PPR = 599;
        reset = 1;#5
        reset = 0;#5;
        reset = 0;#5;
        end
        
       initial begin
       CLK_PWM=0;
       forever #488 CLK_PWM=~CLK_PWM;
       end
    
    
    
       

       initial begin
       #500
        Position_CD = 1;
         #1024000
       Position_CD = 1022;
              #1024000
       Position_CD = 400;
                #1024000
       Position_CD = 100;
                #1024000
       Position_CD = 100;
       end
       

endmodule
module PWM_tb(
);

wire PWM_CD;
reg reset;
reg PPR;
reg[9:0] Position_CD;
reg rate;
reg CLK_PWM;

PWM_Generator pgc(
.reset(reset),
.CLK(CLK_PWM),
.PPR(PPR),
.Position(Position_CD),
.f(rate),
.pwm(PWM_CD)
    );  
   
    
     initial begin
        PPR = 599;
        reset = 1;#5
        reset = 0;#5;
        reset = 0;#5;
        end
        
       initial begin
       CLK_PWM=0;
       forever #488 CLK_PWM=~CLK_PWM;
       end
    
    
    
       

       initial begin
       #500
        Position_CD = 1;
         #1024000
       Position_CD = 1022;
              #1024000
       Position_CD = 400;
                #1024000
       Position_CD = 100;
                #1024000
       Position_CD = 100;
       end
       

endmodule