data/full_repos/permissive/487568919/generic_systemverilog_designs_library/full_adder/full_adder.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/generic_systemverilog_designs_library/full_adder/full_adder.sv:9: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'carry_in\' generates 1 bits.\n                                                                                                                     : ... In instance full_adder\n  assign {carry_out, sum} = a + b + carry_in;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module full_adder
  #(parameter WIDTH = 4)
  (input logic [WIDTH - 1: 0] a, 
                              b, 
   input logic carry_in,
   output logic carry_out,
   output logic [WIDTH - 1: 0] sum);

  assign {carry_out, sum} = a + b + carry_in;

endmodule
module full_adder
  #(parameter WIDTH = 4)
  (input logic [WIDTH - 1: 0] a, 
                              b, 
   input logic carry_in,
   output logic carry_out,
   output logic [WIDTH - 1: 0] sum);


  assign {carry_out, sum} = a + b + carry_in;

endmodule