data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/WReg.v
data/verilator_xmls/4804fe76-a0c0-4f37-b14a-1ef02faa1dae.xml
module WReg(
    input clk,
    input RFWEM,
    input MtoRFSelM,
    input [31:0] ALUOutM,
    input [31:0] DMRD,
    input [4:0] RFAM,
    output reg RFWEW,
    output reg MtoRFSelW,
    output reg [31:0] ALUOutW,
    output reg [31:0] DMOutW,
    output reg [4:0] RFAW
    );
    
    always @(posedge clk) begin
        RFWEW <= RFWEM;
        MtoRFSelW <= MtoRFSelM;
        ALUOutW <= ALUOutM;
        DMOutW <= DMRD;
        RFAW <= RFAM;
    end
endmodule
module WReg(
    input clk,
    input RFWEM,
    input MtoRFSelM,
    input [31:0] ALUOutM,
    input [31:0] DMRD,
    input [4:0] RFAM,
    output reg RFWEW,
    output reg MtoRFSelW,
    output reg [31:0] ALUOutW,
    output reg [31:0] DMOutW,
    output reg [4:0] RFAW
    );

    
    always @(posedge clk) begin
        RFWEW <= RFWEM;
        MtoRFSelW <= MtoRFSelM;
        ALUOutW <= ALUOutM;
        DMOutW <= DMRD;
        RFAW <= RFAM;
    end
endmodule