data/full_repos/permissive/484799296/verilog/alu/alu.v
data/verilator_xmls/096c839c-7d4c-428c-9882-676d2879fac4.xml
module alu (
    input [7:0] A, B,
    input [3:0] S,
    input [2:0] n,
    input C_in,
    output [7:0] Y,
    output C, Z
);

    reg [8:0] temp;

    assign Y = temp[7:0];
    assign C = temp[8];
    assign Z = (temp[7:0] == 0);

    always @(A, B, S, n, C_in)
    begin

        case(S)
            4'b0000: temp[7:0] = B;
            4'b0001: temp = { C_in, A & B};
            4'b0010: temp = { C_in, A | B};
            4'b0011: temp = { C_in, ~B};
            4'b0100: temp = { C_in, A ^ B};
            4'b0101: temp = A + B;
            4'b0110: temp = A - B;
            4'b0111: temp = {C_in, B[3:0], B[7:4]};
            4'b1000: temp = {C_in, B[6:0], 1'b0};
            4'b1001: temp = {B, C_in};
            4'b1010: temp = {C_in, 1'b0, B[7:1]};
            4'b1011: temp = {B[0], C_in, B[7:1]};
            4'b1100: temp = B+1;
            4'b1101: temp = B-1;
            4'b1110: temp = {C_in, A & ~(8'h01 << n)};
            4'b1111: temp = {C_in, A | (8'h01 << n)};
            default: temp[7:0] = 0;
        endcase
    end

endmodule
module alu (
    input [7:0] A, B,
    input [3:0] S,
    input [2:0] n,
    input C_in,
    output [7:0] Y,
    output C, Z
);


    reg [8:0] temp;

    assign Y = temp[7:0];
    assign C = temp[8];
    assign Z = (temp[7:0] == 0);

    always @(A, B, S, n, C_in)
    begin

        case(S)
            4'b0000: temp[7:0] = B;
            4'b0001: temp = { C_in, A & B};
            4'b0010: temp = { C_in, A | B};
            4'b0011: temp = { C_in, ~B};
            4'b0100: temp = { C_in, A ^ B};
            4'b0101: temp = A + B;
            4'b0110: temp = A - B;
            4'b0111: temp = {C_in, B[3:0], B[7:4]};
            4'b1000: temp = {C_in, B[6:0], 1'b0};
            4'b1001: temp = {B, C_in};
            4'b1010: temp = {C_in, 1'b0, B[7:1]};
            4'b1011: temp = {B[0], C_in, B[7:1]};
            4'b1100: temp = B+1;
            4'b1101: temp = B-1;
            4'b1110: temp = {C_in, A & ~(8'h01 << n)};
            4'b1111: temp = {C_in, A | (8'h01 << n)};
            default: temp[7:0] = 0;
        endcase
    end

endmodule