data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:65: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("modbus_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:66: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, modbus_test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:70: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:86: Unsupported: wait statements\n     wait(caravel_chip_ready);\n     ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:226: Unsupported: wait statements\n       wait (master_tx_ready);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:227: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:228: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:234: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:235: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:240: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:241: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:256: Unsupported: wait statements\n       wait (master_rx_ready);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:257: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:258: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:264: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:265: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:271: Unsupported: wait statements\n       wait (~clock);\n       ^~~~\n%Error: data/full_repos/permissive/496114710/verilog/dv/modbus_test/modbus_test_tb.v:272: Unsupported: wait statements\n       wait (clock);\n       ^~~~\n%Error: Exiting due to 18 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module modbus_test_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire caravel_rx;
	wire caravel_tx;
	wire caravel_chip_ready;



	reg modbus_check_err;

	reg  [7:0]	rx_byte;

	integer i;

	assign caravel_tx 			= mprj_io[8];
	assign mprj_io[9] 			= caravel_rx;
	assign caravel_chip_ready 	= mprj_io[10];

	reg	 reset;

	assign mprj_io[3] = 1'b1;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		for (i = 0; i < 255; i = i + 1) uut.mprj.sram_inst.mem[i] = 0;
	end

	initial begin
		$dumpfile("modbus_test.vcd");
		$dumpvars(0, modbus_test_tb);


		repeat (250) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Modbus Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		reset = 1'b1;

	   	wait(caravel_chip_ready);
	   	$display("Monitor: Modbus Test Started");

	   	reset = 1'b0;

	   	send_modbus_frame({8'h01, 8'h10, 8'h00, 8'h00, 8'h00, 8'h01, 8'h02, 8'h00, 8'h01, 8'h67, 8'h90}, 11);

	   	check_modbus_frame({8'h01, 8'h10, 8'h00, 8'h00, 8'h00, 8'h01, 8'h01, 8'hc9}, 8, 1);

	   	if (modbus_check_err) begin
	   	`ifdef GL
			$display ("Monitor: Frame Mismatch, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Frame Mismatch, Modbus Test (RTL) Failed");
		`endif
			$finish;
	   	end 

		
	   	send_modbus_frame({8'h01, 8'h03, 8'h00, 8'h80, 8'h00, 8'h04, 8'h45, 8'he1}, 8);

	   	check_modbus_frame({8'h01, 8'h03, 8'h08, 8'h59, 8'h6f, 8'h6e, 8'h67, 8'h61, 8'h74, 8'h65, 8'h6b, 8'hc7, 8'h98}, 13, 1);

	   	if (modbus_check_err) begin
	   	`ifdef GL
			$display ("Monitor: Frame Mismatch, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Frame Mismatch, Modbus Test (RTL) Failed");
		`endif
		  $finish;
	   	end 
	   	
		`ifdef GL
	    	$display("Monitor: Modbus Test (GL) Passed");
		`else
		    $display("Monitor: Modbus Test (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	reg  [7:0] 	master_tx_data;
    wire 		master_tx_ready;
    reg       	master_tx_wren;
    wire [7:0]	master_rx_data;
    wire		master_rx_ready;
    reg       	master_rx_rden;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("modbus_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

	Modbus_UART_Controller #( 434 ) modbus_master
    (

    .i_clk(clock),
    .i_rst(reset),
    .i_enable(1'b1),

    .i_tx_data(master_tx_data),
    .o_tx_ready(master_tx_ready),
    .i_tx_wren(master_tx_wren),
    .o_rx_data(master_rx_data),
    .o_rx_ready(master_rx_ready),
    .i_rx_rden(master_rx_rden),

    .i_rx(caravel_tx),
    .o_tx(caravel_rx)
    );

    task send_modbus_frame(input [255:0] frame, input [4:0] length);
    	begin
    		frame = frame << (32 - length) * 8;

    		for (i = 0; i < length; i = i + 1) begin

    			wait (master_tx_ready);
    			wait (~clock);
    			wait (clock);
    			

    			master_tx_data 	= frame[255:248];
    			master_tx_wren 	= 1'b1;

    			wait (~clock);
    			wait (clock);


    			master_tx_wren	= 1'b0;

    			wait (~clock);
    			wait (clock);

    			frame = frame << 8;
    		end 
    	end
    endtask

    task check_modbus_frame(input [255:0] ref_frame, input [4:0] length, input compare);
    	begin
    		modbus_check_err = 0;

    		ref_frame = ref_frame << (32 - length) * 8;

    		for (i = 0; i < length; i = i + 1) begin

    			wait (master_rx_ready);
    			wait (~clock);
    			wait (clock);


    			rx_byte 		= master_rx_data;
    			master_rx_rden 	= 1'b1;

    			wait (~clock);
    			wait (clock);

    			master_rx_rden	= 1'b0;

    			if (compare) modbus_check_err = (rx_byte != ref_frame[255:248]) ? 1'b1 : modbus_check_err;

    			wait (~clock);
    			wait (clock);

    			ref_frame = ref_frame << 8;
    		end 
    	end
    endtask

endmodule
module modbus_test_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire caravel_rx;
	wire caravel_tx;
	wire caravel_chip_ready;



	reg modbus_check_err;

	reg  [7:0]	rx_byte;

	integer i;

	assign caravel_tx 			= mprj_io[8];
	assign mprj_io[9] 			= caravel_rx;
	assign caravel_chip_ready 	= mprj_io[10];

	reg	 reset;

	assign mprj_io[3] = 1'b1;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		for (i = 0; i < 255; i = i + 1) uut.mprj.sram_inst.mem[i] = 0;
	end

	initial begin
		$dumpfile("modbus_test.vcd");
		$dumpvars(0, modbus_test_tb);


		repeat (250) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Modbus Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		reset = 1'b1;

	   	wait(caravel_chip_ready);
	   	$display("Monitor: Modbus Test Started");

	   	reset = 1'b0;

	   	send_modbus_frame({8'h01, 8'h10, 8'h00, 8'h00, 8'h00, 8'h01, 8'h02, 8'h00, 8'h01, 8'h67, 8'h90}, 11);

	   	check_modbus_frame({8'h01, 8'h10, 8'h00, 8'h00, 8'h00, 8'h01, 8'h01, 8'hc9}, 8, 1);

	   	if (modbus_check_err) begin
	   	`ifdef GL
			$display ("Monitor: Frame Mismatch, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Frame Mismatch, Modbus Test (RTL) Failed");
		`endif
			$finish;
	   	end 

		
	   	send_modbus_frame({8'h01, 8'h03, 8'h00, 8'h80, 8'h00, 8'h04, 8'h45, 8'he1}, 8);

	   	check_modbus_frame({8'h01, 8'h03, 8'h08, 8'h59, 8'h6f, 8'h6e, 8'h67, 8'h61, 8'h74, 8'h65, 8'h6b, 8'hc7, 8'h98}, 13, 1);

	   	if (modbus_check_err) begin
	   	`ifdef GL
			$display ("Monitor: Frame Mismatch, Modbus Test (GL) Failed");
		`else
			$display ("Monitor: Frame Mismatch, Modbus Test (RTL) Failed");
		`endif
		  $finish;
	   	end 
	   	
		`ifdef GL
	    	$display("Monitor: Modbus Test (GL) Passed");
		`else
		    $display("Monitor: Modbus Test (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	reg  [7:0] 	master_tx_data;
    wire 		master_tx_ready;
    reg       	master_tx_wren;
    wire [7:0]	master_rx_data;
    wire		master_rx_ready;
    reg       	master_rx_rden;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("modbus_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

	Modbus_UART_Controller #( 434 ) modbus_master
    (

    .i_clk(clock),
    .i_rst(reset),
    .i_enable(1'b1),

    .i_tx_data(master_tx_data),
    .o_tx_ready(master_tx_ready),
    .i_tx_wren(master_tx_wren),
    .o_rx_data(master_rx_data),
    .o_rx_ready(master_rx_ready),
    .i_rx_rden(master_rx_rden),

    .i_rx(caravel_tx),
    .o_tx(caravel_rx)
    );

    task send_modbus_frame(input [255:0] frame, input [4:0] length);
    	begin
    		frame = frame << (32 - length) * 8;

    		for (i = 0; i < length; i = i + 1) begin

    			wait (master_tx_ready);
    			wait (~clock);
    			wait (clock);
    			

    			master_tx_data 	= frame[255:248];
    			master_tx_wren 	= 1'b1;

    			wait (~clock);
    			wait (clock);


    			master_tx_wren	= 1'b0;

    			wait (~clock);
    			wait (clock);

    			frame = frame << 8;
    		end 
    	end
    endtask

    task check_modbus_frame(input [255:0] ref_frame, input [4:0] length, input compare);
    	begin
    		modbus_check_err = 0;

    		ref_frame = ref_frame << (32 - length) * 8;

    		for (i = 0; i < length; i = i + 1) begin

    			wait (master_rx_ready);
    			wait (~clock);
    			wait (clock);


    			rx_byte 		= master_rx_data;
    			master_rx_rden 	= 1'b1;

    			wait (~clock);
    			wait (clock);

    			master_rx_rden	= 1'b0;

    			if (compare) modbus_check_err = (rx_byte != ref_frame[255:248]) ? 1'b1 : modbus_check_err;

    			wait (~clock);
    			wait (clock);

    			ref_frame = ref_frame << 8;
    		end 
    	end
    endtask

endmodule