data/full_repos/permissive/428225746/verilog/rtl/logic_cell.v
data/verilator_xmls/1753dc25-b520-4b89-89f6-2db2c7df71e9.xml
module logic_cell(
   input clk,
   input rst_n,
   input trig,
   input in_t,
   input in_r,
   input in_b,
   input in_l,
   input in_i,
   input en_i,
   output out_t,
   output out_r,
   output out_b,
   output out_l,
   output out_o
);

reg [1:0] rot;
reg ff;

wire inx_t, inx_r, inx_b, inx_l;
wire outx_t, outx_r, outx_b, outx_l;

wire inr_t, inr_r, inr_b, inr_l;
wire outr_t, outr_r, outr_b, outr_l;



assign inr_t = rot[1] ? in_b : in_t;
assign inr_r = rot[1] ? in_l : in_r;
assign inr_b = rot[1] ? in_t : in_b;
assign inr_l = rot[1] ? in_r : in_l;

assign inx_t = rot[0] ? inr_l : inr_t;
assign inx_r = rot[0] ? inr_t : inr_r;
assign inx_b = rot[0] ? inr_r : inr_b;
assign inx_l = rot[0] ? inr_b : inr_l;

assign outr_t = rot[1] ? outx_b : outx_t;
assign outr_r = rot[1] ? outx_l : outx_r;
assign outr_b = rot[1] ? outx_t : outx_b;
assign outr_l = rot[1] ? outx_r : outx_l;

assign out_t = rot[0] ? outr_r : outr_t;
assign out_r = rot[0] ? outr_b : outr_r;
assign out_b = rot[0] ? outr_l : outr_b;
assign out_l = rot[0] ? outr_t : outr_l;



assign outx_t = ~(inx_r & inx_b);
assign outx_r = inx_l;
assign outx_b = inx_l;
assign outx_l = ff;
assign out_o = ff;

always @ (posedge clk) begin
   if (!rst_n) begin
      rot <= 0;
      ff <= 0;
   end else begin
      if (trig) rot <= rot + 1;
      ff <= en_i ? in_i : inx_t;
   end
end

endmodule
module logic_cell(
   input clk,
   input rst_n,
   input trig,
   input in_t,
   input in_r,
   input in_b,
   input in_l,
   input in_i,
   input en_i,
   output out_t,
   output out_r,
   output out_b,
   output out_l,
   output out_o
);


reg [1:0] rot;
reg ff;

wire inx_t, inx_r, inx_b, inx_l;
wire outx_t, outx_r, outx_b, outx_l;

wire inr_t, inr_r, inr_b, inr_l;
wire outr_t, outr_r, outr_b, outr_l;



assign inr_t = rot[1] ? in_b : in_t;
assign inr_r = rot[1] ? in_l : in_r;
assign inr_b = rot[1] ? in_t : in_b;
assign inr_l = rot[1] ? in_r : in_l;

assign inx_t = rot[0] ? inr_l : inr_t;
assign inx_r = rot[0] ? inr_t : inr_r;
assign inx_b = rot[0] ? inr_r : inr_b;
assign inx_l = rot[0] ? inr_b : inr_l;

assign outr_t = rot[1] ? outx_b : outx_t;
assign outr_r = rot[1] ? outx_l : outx_r;
assign outr_b = rot[1] ? outx_t : outx_b;
assign outr_l = rot[1] ? outx_r : outx_l;

assign out_t = rot[0] ? outr_r : outr_t;
assign out_r = rot[0] ? outr_b : outr_r;
assign out_b = rot[0] ? outr_l : outr_b;
assign out_l = rot[0] ? outr_t : outr_l;



assign outx_t = ~(inx_r & inx_b);
assign outx_r = inx_l;
assign outx_b = inx_l;
assign outx_l = ff;
assign out_o = ff;

always @ (posedge clk) begin
   if (!rst_n) begin
      rot <= 0;
      ff <= 0;
   end else begin
      if (trig) rot <= rot + 1;
      ff <= en_i ? in_i : inx_t;
   end
end

endmodule