data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_par16.v
data/verilator_xmls/7aaaad2a-d7f5-4da2-891f-9b83a4082b42.xml
module sparc_ifu_par16 (

   out, 

   in
   );

   input [15:0] in;
   output 	out;

   assign  out = (^in[15:0]);

endmodule
module sparc_ifu_par16 (

   out, 

   in
   );


   input [15:0] in;
   output 	out;

   assign  out = (^in[15:0]);

endmodule