data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/data_mem.v
data/verilator_xmls/2664009b-ff06-41b0-91d3-5cfedb93dde0.xml
module data_mem(
input [15:0]dM,
input [2:0]aM,
input clk,wr,
output reg [15:0]m
    );
reg [15:0]mem[7:0];	 
integer i;
	 initial 
	  for(i=0;i<8;i=i+1)
	  begin
	  mem[i]=0;
	  end

always@(posedge clk)
begin
 if(wr==1)
  mem[aM]=dM;
end	 


always@(negedge clk)
begin 
m=mem[aM];
end
endmodule
module data_mem(
input [15:0]dM,
input [2:0]aM,
input clk,wr,
output reg [15:0]m
    );

reg [15:0]mem[7:0];	 
integer i;
	 initial 
	  for(i=0;i<8;i=i+1)
	  begin
	  mem[i]=0;
	  end

always@(posedge clk)
begin
 if(wr==1)
  mem[aM]=dM;
end	 


always@(negedge clk)
begin 
m=mem[aM];
end
endmodule