data/full_repos/permissive/481490387/cache.v
1: b"%Error: data/full_repos/permissive/481490387/cache.v:75: Cannot find file containing module: 'blk_mem_gen_0'\n    blk_mem_gen_0 u_cache (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481490387,data/full_repos/permissive/481490387/blk_mem_gen_0\n             data/full_repos/permissive/481490387,data/full_repos/permissive/481490387/blk_mem_gen_0.v\n             data/full_repos/permissive/481490387,data/full_repos/permissive/481490387/blk_mem_gen_0.sv\n             blk_mem_gen_0\n             blk_mem_gen_0.v\n             blk_mem_gen_0.sv\n             obj_dir/blk_mem_gen_0\n             obj_dir/blk_mem_gen_0.v\n             obj_dir/blk_mem_gen_0.sv\n%Error: Exiting due to 1 error(s)\n"
module cache (

        input             clk,
        input             reset,

        input wire [12:0] addr_from_cpu,
        input wire        rreq_from_cpu,
        input wire        wreq_from_cpu,
        input wire [ 7:0] wdata_from_cpu,

        input wire [31:0] rdata_from_mem,
        input wire        rvalid_from_mem,

        output wire [7:0] rdata_to_cpu,
        output wire       hit_to_cpu,

        output reg        rreq_to_mem,
        output reg [12:0] raddr_to_mem,
        output wire       wreq_to_mem,
        output reg [12:0] waddr_to_mem,
        output reg [ 7:0] wdata_to_mem
    );

    reg [3:0] current_state, next_state;
    localparam READY     = 4'b0000,
               TAG_CHECK = 4'b0010,
               REFILL    = 4'b0001;











    wire        wea;
    wire [37:0] cache_line;

    wire [ 5:0] cache_index    = addr_from_cpu[7:2];
    wire [ 4:0] tag_from_cpu   = addr_from_cpu[12:8];
    wire [ 1:0] offset         = addr_from_cpu[1:0];
    wire        valid_bit      = cache_line[37];
    wire [ 4:0] tag_from_cache = cache_line[36:32];

    wire [31:0] wdata_to_cache;
    assign wdata_to_cache = (offset == 2'b00) ? {cache_line[31:8], wdata_from_cpu} :
           (offset == 2'b01) ? {cache_line[31:16], wdata_from_cpu, cache_line[7:0]} :
           (offset == 2'b10) ? {cache_line[31:24], wdata_from_cpu, cache_line[15:0]} :
           {wdata_from_cpu, cache_line[23:0]};

    wire hit  = (current_state == TAG_CHECK) && (valid_bit) && (tag_from_cache == tag_from_cpu);
    wire miss = (tag_from_cache != tag_from_cpu) | (~valid_bit);


    wire [37:0] cache_line_r = {1'b1, tag_from_cpu, wreq_to_mem ? (
                                    (offset == 2'b00) ? {cache_line[31:8], wdata_from_cpu} :
                                    (offset == 2'b01) ? {cache_line[31:16], wdata_from_cpu, cache_line[7:0]} :
                                    (offset == 2'b10) ? {cache_line[31:24], wdata_from_cpu, cache_line[15:0]} :
                                    {wdata_from_cpu, cache_line[23:0]}
                                ) : rdata_from_mem};


    assign rdata_to_cpu = (offset == 2'b00) ? cache_line[7:0] :
           (offset == 2'b01) ? cache_line[15:8] :
           (offset == 2'b10) ? cache_line[23:16] : cache_line[31:24];

    assign hit_to_cpu = hit;


    blk_mem_gen_0 u_cache (
                      .clka   (clk         ),
                      .wea    (wea         ),
                      .addra  (cache_index ),
                      .dina   (cache_line_r),
                      .douta  (cache_line  )
                  );

    always @(posedge clk) begin
        if (reset) begin
            current_state <= READY;
        end
        else begin
            current_state <= next_state;
        end
    end


    always @(*) begin
        case(current_state)
            READY: begin
                if (rreq_from_cpu || wreq_from_cpu) begin
                    next_state = TAG_CHECK;
                end
                else begin
                    next_state = READY;
                end
            end
            TAG_CHECK: begin

                if (miss && !wreq_from_cpu) begin
                    next_state = REFILL;
                end
                else begin
                    next_state = READY;
                end
            end
            REFILL: begin
                if (rvalid_from_mem) begin
                    next_state = TAG_CHECK;
                end
                else begin
                    next_state = REFILL;
                end
            end
            default: begin
                next_state = READY;
            end
        endcase
    end


    assign wea = ((current_state == REFILL) && rvalid_from_mem) || wreq_to_mem;


    always @(posedge clk) begin
        if (reset) begin
            raddr_to_mem <= 0;
            rreq_to_mem <= 0;
        end
        else begin
            case (next_state)
                READY: begin
                    raddr_to_mem <= 0;
                    rreq_to_mem  <= 0;
                end
                TAG_CHECK: begin
                    raddr_to_mem <= addr_from_cpu;
                    rreq_to_mem  <= miss && rreq_from_cpu && !rvalid_from_mem;
                end
                REFILL: begin
                    raddr_to_mem <= addr_from_cpu;
                    rreq_to_mem  <= rreq_from_cpu && !rvalid_from_mem;
                end
                default: begin
                    raddr_to_mem <= 0;
                    rreq_to_mem  <= 0;
                end
            endcase
        end
    end







    assign wreq_to_mem = hit && wreq_from_cpu;

    always @(posedge clk) begin
        if (reset) begin

            waddr_to_mem <= 13'b0;
            wdata_to_mem <= 8'b0;
        end
        else begin
            case (next_state)
                READY: begin
                    waddr_to_mem <= 0;

                end
                TAG_CHECK: begin
                    waddr_to_mem <= addr_from_cpu;

                end
                REFILL: begin
                    waddr_to_mem <= addr_from_cpu;
                    wdata_to_mem <= wdata_from_cpu;

                end
                default: begin
                    waddr_to_mem <= 0;

                end
            endcase
        end
    end


endmodule
module cache (

        input             clk,
        input             reset,

        input wire [12:0] addr_from_cpu,
        input wire        rreq_from_cpu,
        input wire        wreq_from_cpu,
        input wire [ 7:0] wdata_from_cpu,

        input wire [31:0] rdata_from_mem,
        input wire        rvalid_from_mem,

        output wire [7:0] rdata_to_cpu,
        output wire       hit_to_cpu,

        output reg        rreq_to_mem,
        output reg [12:0] raddr_to_mem,
        output wire       wreq_to_mem,
        output reg [12:0] waddr_to_mem,
        output reg [ 7:0] wdata_to_mem
    );


    reg [3:0] current_state, next_state;
    localparam READY     = 4'b0000,
               TAG_CHECK = 4'b0010,
               REFILL    = 4'b0001;











    wire        wea;
    wire [37:0] cache_line;

    wire [ 5:0] cache_index    = addr_from_cpu[7:2];
    wire [ 4:0] tag_from_cpu   = addr_from_cpu[12:8];
    wire [ 1:0] offset         = addr_from_cpu[1:0];
    wire        valid_bit      = cache_line[37];
    wire [ 4:0] tag_from_cache = cache_line[36:32];

    wire [31:0] wdata_to_cache;
    assign wdata_to_cache = (offset == 2'b00) ? {cache_line[31:8], wdata_from_cpu} :
           (offset == 2'b01) ? {cache_line[31:16], wdata_from_cpu, cache_line[7:0]} :
           (offset == 2'b10) ? {cache_line[31:24], wdata_from_cpu, cache_line[15:0]} :
           {wdata_from_cpu, cache_line[23:0]};

    wire hit  = (current_state == TAG_CHECK) && (valid_bit) && (tag_from_cache == tag_from_cpu);
    wire miss = (tag_from_cache != tag_from_cpu) | (~valid_bit);


    wire [37:0] cache_line_r = {1'b1, tag_from_cpu, wreq_to_mem ? (
                                    (offset == 2'b00) ? {cache_line[31:8], wdata_from_cpu} :
                                    (offset == 2'b01) ? {cache_line[31:16], wdata_from_cpu, cache_line[7:0]} :
                                    (offset == 2'b10) ? {cache_line[31:24], wdata_from_cpu, cache_line[15:0]} :
                                    {wdata_from_cpu, cache_line[23:0]}
                                ) : rdata_from_mem};


    assign rdata_to_cpu = (offset == 2'b00) ? cache_line[7:0] :
           (offset == 2'b01) ? cache_line[15:8] :
           (offset == 2'b10) ? cache_line[23:16] : cache_line[31:24];

    assign hit_to_cpu = hit;


    blk_mem_gen_0 u_cache (
                      .clka   (clk         ),
                      .wea    (wea         ),
                      .addra  (cache_index ),
                      .dina   (cache_line_r),
                      .douta  (cache_line  )
                  );

    always @(posedge clk) begin
        if (reset) begin
            current_state <= READY;
        end
        else begin
            current_state <= next_state;
        end
    end


    always @(*) begin
        case(current_state)
            READY: begin
                if (rreq_from_cpu || wreq_from_cpu) begin
                    next_state = TAG_CHECK;
                end
                else begin
                    next_state = READY;
                end
            end
            TAG_CHECK: begin

                if (miss && !wreq_from_cpu) begin
                    next_state = REFILL;
                end
                else begin
                    next_state = READY;
                end
            end
            REFILL: begin
                if (rvalid_from_mem) begin
                    next_state = TAG_CHECK;
                end
                else begin
                    next_state = REFILL;
                end
            end
            default: begin
                next_state = READY;
            end
        endcase
    end


    assign wea = ((current_state == REFILL) && rvalid_from_mem) || wreq_to_mem;


    always @(posedge clk) begin
        if (reset) begin
            raddr_to_mem <= 0;
            rreq_to_mem <= 0;
        end
        else begin
            case (next_state)
                READY: begin
                    raddr_to_mem <= 0;
                    rreq_to_mem  <= 0;
                end
                TAG_CHECK: begin
                    raddr_to_mem <= addr_from_cpu;
                    rreq_to_mem  <= miss && rreq_from_cpu && !rvalid_from_mem;
                end
                REFILL: begin
                    raddr_to_mem <= addr_from_cpu;
                    rreq_to_mem  <= rreq_from_cpu && !rvalid_from_mem;
                end
                default: begin
                    raddr_to_mem <= 0;
                    rreq_to_mem  <= 0;
                end
            endcase
        end
    end







    assign wreq_to_mem = hit && wreq_from_cpu;

    always @(posedge clk) begin
        if (reset) begin

            waddr_to_mem <= 13'b0;
            wdata_to_mem <= 8'b0;
        end
        else begin
            case (next_state)
                READY: begin
                    waddr_to_mem <= 0;

                end
                TAG_CHECK: begin
                    waddr_to_mem <= addr_from_cpu;

                end
                REFILL: begin
                    waddr_to_mem <= addr_from_cpu;
                    wdata_to_mem <= wdata_from_cpu;

                end
                default: begin
                    waddr_to_mem <= 0;

                end
            endcase
        end
    end


endmodule