data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v
1: b"%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:60: Cannot find file containing module: 'Accumulator'\n    Accumulator     ACC( .i_clk(i_clk) ,   .ld_Acc(load_Acc) ,   .i_data(o_Data_Acc) , .o_Acc(o_ACC_out ));\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Accumulator\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Accumulator.v\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Accumulator.sv\n             Accumulator\n             Accumulator.v\n             Accumulator.sv\n             obj_dir/Accumulator\n             obj_dir/Accumulator.v\n             obj_dir/Accumulator.sv\n%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:62: Cannot find file containing module: 'Multiplier'\n    Multiplier      Q_OP( .i_clk(i_clk)  ,.clr_q(i_clr_q)  ,  .i_data_q(i_Op_multiplier),  .i_AQ(AQ) , .ld_Q(load_Q) , .o_data_Q(o_Q_out) );\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:64: Cannot find file containing module: 'Multiplicand_M'\n    Multiplicand_M  M_OP(.i_clk(i_clk) , .i_rst_n(i_rst_n) ,   .ld_M(load_M) ,  .data_M(i_Op_multiplicand)  , .o_data_M(o_M_out));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:68: Cannot find file containing module: 'ADD_SUB'\n   ADD_SUB   ADDER_SUBTRACTOR(.i_a(o_ACC_out), .i_b(o_M_out), .i_cin(c_enable), .i_add_sub(add_sub_en) ,.sum_out(S_out), .c_out(C_o));\n   ^~~~~~~\n%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:70: Cannot find file containing module: 'Mux_2_1'\n    Mux_2_1         MUX(.i_op_1(5'b00000), .i_op_2(S_out) , .i_sel(sel_Mux) ,  .o_out_Mux(o_Data_Acc)  );\n    ^~~~~~~\n%Error: data/full_repos/permissive/522534105/RTL_files/Datapath_unit.v:72: Cannot find file containing module: 'Counter_M'\n    Counter_M COUNT( .i_clk(i_clk),  .i_rst_n(i_rst_n) ,  .o_cnt(cnt_out));\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module Datapath_unit(
input i_clk , 
input i_rst_n ,
input load_Acc , 
input load_Q , 
input load_M , 
input load_Qn ,
input add_sub_en ,
input sel_Mux ,  
input c_enable ,
input i_clr_q ,  
input [`DATA_WIDTH_M-1:0] i_Op_multiplicand , 
input [`DATA_WIDTH-1:0] i_Op_multiplier , 
output [`DATA_OUT_Q-1:0] o_Q_out, 
output[`DATA_OUT_ACC-1:0] o_ACC_out , 
output Q_n, 
output Q ,  
output C_o , 
output o_assert_done  );
    
   

  
      wire  [`CNT_WIDTH-1:0] cnt_out ;  

    wire [`DATA_OUT_ACC-1:0] o_Data_Acc ;
    wire  [`DATA_OUT_M-1:0] o_M_out ;
    wire [`DATA_OUT_M-1:0] S_out ; 

    wire AQ = o_ACC_out[0] ;
    assign  Q =  o_Q_out[1] ;
    assign  Q_n = o_Q_out[0]; 
    Accumulator     ACC( .i_clk(i_clk) ,   .ld_Acc(load_Acc) ,   .i_data(o_Data_Acc) , .o_Acc(o_ACC_out ));
   
    Multiplier      Q_OP( .i_clk(i_clk)  ,.clr_q(i_clr_q)  ,  .i_data_q(i_Op_multiplier),  .i_AQ(AQ) , .ld_Q(load_Q) , .o_data_Q(o_Q_out) );

    Multiplicand_M  M_OP(.i_clk(i_clk) , .i_rst_n(i_rst_n) ,   .ld_M(load_M) ,  .data_M(i_Op_multiplicand)  , .o_data_M(o_M_out));
    

    
   ADD_SUB   ADDER_SUBTRACTOR(.i_a(o_ACC_out), .i_b(o_M_out), .i_cin(c_enable), .i_add_sub(add_sub_en) ,.sum_out(S_out), .c_out(C_o));

    Mux_2_1         MUX(.i_op_1(5'b00000), .i_op_2(S_out) , .i_sel(sel_Mux) ,  .o_out_Mux(o_Data_Acc)  );
    
    Counter_M COUNT( .i_clk(i_clk),  .i_rst_n(i_rst_n) ,  .o_cnt(cnt_out));
   
    assign o_assert_done = (cnt_out == 3'b110)? 1'b1 : 1'b0;
    
     
endmodule
module Datapath_unit(
input i_clk , 
input i_rst_n ,
input load_Acc , 
input load_Q , 
input load_M , 
input load_Qn ,
input add_sub_en ,
input sel_Mux ,  
input c_enable ,
input i_clr_q ,  
input [`DATA_WIDTH_M-1:0] i_Op_multiplicand , 
input [`DATA_WIDTH-1:0] i_Op_multiplier , 
output [`DATA_OUT_Q-1:0] o_Q_out, 
output[`DATA_OUT_ACC-1:0] o_ACC_out , 
output Q_n, 
output Q ,  
output C_o , 
output o_assert_done  );

    
   

  
      wire  [`CNT_WIDTH-1:0] cnt_out ;  

    wire [`DATA_OUT_ACC-1:0] o_Data_Acc ;
    wire  [`DATA_OUT_M-1:0] o_M_out ;
    wire [`DATA_OUT_M-1:0] S_out ; 

    wire AQ = o_ACC_out[0] ;
    assign  Q =  o_Q_out[1] ;
    assign  Q_n = o_Q_out[0]; 
    Accumulator     ACC( .i_clk(i_clk) ,   .ld_Acc(load_Acc) ,   .i_data(o_Data_Acc) , .o_Acc(o_ACC_out ));
   
    Multiplier      Q_OP( .i_clk(i_clk)  ,.clr_q(i_clr_q)  ,  .i_data_q(i_Op_multiplier),  .i_AQ(AQ) , .ld_Q(load_Q) , .o_data_Q(o_Q_out) );

    Multiplicand_M  M_OP(.i_clk(i_clk) , .i_rst_n(i_rst_n) ,   .ld_M(load_M) ,  .data_M(i_Op_multiplicand)  , .o_data_M(o_M_out));
    

    
   ADD_SUB   ADDER_SUBTRACTOR(.i_a(o_ACC_out), .i_b(o_M_out), .i_cin(c_enable), .i_add_sub(add_sub_en) ,.sum_out(S_out), .c_out(C_o));

    Mux_2_1         MUX(.i_op_1(5'b00000), .i_op_2(S_out) , .i_sel(sel_Mux) ,  .o_out_Mux(o_Data_Acc)  );
    
    Counter_M COUNT( .i_clk(i_clk),  .i_rst_n(i_rst_n) ,  .o_cnt(cnt_out));
   
    assign o_assert_done = (cnt_out == 3'b110)? 1'b1 : 1'b0;
    
     
endmodule