data/full_repos/permissive/469195529/sources/hdl/timerOn.v
data/verilator_xmls/1df8eeac-5e07-45a4-8e05-029750e4a399.xml
module timerOn(
    input clk_in,
    output reg led_out
    );
    initial led_out = 0;
    always@(posedge clk_in) led_out = ~led_out;
endmodule
module timerOn(
    input clk_in,
    output reg led_out
    );

    initial led_out = 0;
    always@(posedge clk_in) led_out = ~led_out;
endmodule