data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational Logic/Arithmetic Circuits/adder100.v
1: b'%Error: Cannot find file containing module: Logic/Arithmetic\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Arithmetic\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Arithmetic.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Arithmetic.sv\n             Logic/Arithmetic\n             Logic/Arithmetic.v\n             Logic/Arithmetic.sv\n             obj_dir/Logic/Arithmetic\n             obj_dir/Logic/Arithmetic.v\n             obj_dir/Logic/Arithmetic.sv\n%Error: Cannot find file containing module: Circuits,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational\n%Error: Cannot find file containing module: Circuits/adder100.v\n%Error: Exiting due to 4 error(s)\n'
module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    

    reg [100:0] result;
    assign result = a[99:0] + b[99:0] + cin;
    assign sum = result[99:0];
    assign cout = result[100];
    

    wire [98:0] carry;
    
    full_adder u_full_adder_0(a[0], b[0], cin, carry[0], sum[0]);
    full_adder u_full_adder_99(a[99], b[99], carry[98], cout, sum[99]);
    
    generate
        genvar i;
        for(i = 1; i < 99; i++) begin : add_100
            full_adder u_full_adder(a[i], b[i], carry[i - 1], carry[i], sum[i]);
        end
    endgenerate

endmodule
module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );

    

    reg [100:0] result;
    assign result = a[99:0] + b[99:0] + cin;
    assign sum = result[99:0];
    assign cout = result[100];
    

    wire [98:0] carry;
    
    full_adder u_full_adder_0(a[0], b[0], cin, carry[0], sum[0]);
    full_adder u_full_adder_99(a[99], b[99], carry[98], cout, sum[99]);
    
    generate
        genvar i;
        for(i = 1; i < 99; i++) begin : add_100
            full_adder u_full_adder(a[i], b[i], carry[i - 1], carry[i], sum[i]);
        end
    endgenerate

endmodule