data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:4: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FIFO_DEPTH                 = $clog2(MAX_BURST_LENGTH_MSG),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:7: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter NOC_MASTER                 = 0,   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:8: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FIFO_POP_FULL_BURST_ONLY   = 1,   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FIFO_PUSH_EMPTY_BURST_ONLY = 0    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:10: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_BSEL_SIZE-1:0] noc_bsel_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc_src_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_MODE_SIZE-1:0] noc_mode_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_ADDR_SIZE-1:0] noc_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc_data0_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc_data1_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          noc_stall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          noc_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          noc_burst_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [NOC_BSEL_SIZE-1:0] noc_bsel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [NOC_MODID_SIZE-1:0] noc_src_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [NOC_MODE_SIZE-1:0] noc_mode_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [NOC_DATA_SIZE-1:0] noc_data0_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [NOC_DATA_SIZE-1:0] noc_data1_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_stall_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:46: syntax error, unexpected generate\n    generate\n    ^~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_fifo.v:88: syntax error, unexpected assign\n        assign noc_stall_o = (NOC_MASTER == 1) ? (fifo_full || !fifo_push) : fifo_full;\n        ^~~~~~\n%Error: Exiting due to 35 error(s)\n'
module tcu_noc_fifo #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_NOC_FIFO       = 0,
    parameter FIFO_DEPTH                 = $clog2(MAX_BURST_LENGTH_MSG),
    parameter NOC_MASTER                 = 0,
    parameter FIFO_POP_FULL_BURST_ONLY   = 1,
    parameter FIFO_PUSH_EMPTY_BURST_ONLY = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    input  wire                          noc_wrreq_i,
    input  wire                          noc_burst_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_data1_i,
    output wire                          noc_stall_o,

    output wire                          noc_wrreq_o,
    output wire                          noc_burst_o,
    output wire      [NOC_BSEL_SIZE-1:0] noc_bsel_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_src_modid_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_o,
    output wire      [NOC_MODE_SIZE-1:0] noc_mode_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output wire      [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_DATA_SIZE-1:0] noc_data1_o,
    input  wire                          noc_stall_i
);

    localparam FIFO_WIDTH = NOC_HEADER_SIZE + NOC_PAYLOAD_SIZE - NOC_ARQ_SIZE;

    localparam COUNT_SIZE = 8+1;


    generate
    if (TCU_ENABLE_NOC_FIFO) begin: enable_fifo

        reg [FIFO_WIDTH-1:0] rin_fifo_wdata;

        reg                  rin_noc_wrreq_out;
        reg                  r_noc_burst_in;
        reg                  r_noc_burst_out;
        reg [COUNT_SIZE-1:0] r_burst_count_in, rin_burst_count_in;
        reg [COUNT_SIZE-1:0] r_burst_count_out, rin_burst_count_out;


        wire [FIFO_WIDTH-1:0] fifo_wdata_noburst = {noc_burst_i,
                                                    noc_bsel_i,
                                                    noc_src_modid_i,
                                                    noc_src_chipid_i,
                                                    noc_trg_modid_i,
                                                    noc_trg_chipid_i,
                                                    noc_mode_i,
                                                    noc_addr_i,
                                                    noc_data0_i};

        wire [FIFO_WIDTH-1:0] fifo_wdata_burst = {noc_burst_i,
                                                    noc_bsel_i,
                                                    noc_data1_i,
                                                    noc_data0_i};

        wire [FIFO_WIDTH-1:0] fifo_rdata;

        wire fifo_empty;
        wire fifo_full;
        wire fifo_pop = rin_noc_wrreq_out && !noc_stall_i;
        reg fifo_push;
        wire noc_burst_out = fifo_rdata[FIFO_WIDTH-1];
        

        wire burst_ready = ((r_burst_count_in[COUNT_SIZE-2:0] > r_burst_count_out[COUNT_SIZE-2:0]) &&
                            (r_burst_count_in[COUNT_SIZE-1] == r_burst_count_out[COUNT_SIZE-1])) ||
                                ((r_burst_count_in[COUNT_SIZE-2:0] < r_burst_count_out[COUNT_SIZE-2:0]) &&
                                (r_burst_count_in[COUNT_SIZE-1] != r_burst_count_out[COUNT_SIZE-1]));


        assign noc_stall_o = (NOC_MASTER == 1) ? (fifo_full || !fifo_push) : fifo_full;


        sync_fifo #(
            .DATA_WIDTH (FIFO_WIDTH),
            .ADDR_WIDTH (FIFO_DEPTH),
            .USE_MEM    (1)
        ) i_fifo (
            .clk_i      (clk_i),
            .resetn_i   (reset_n_i),

            .wr_en_i    (fifo_push),
            .wdata_i    (rin_fifo_wdata),
            .wfull_o    (fifo_full),

            .rd_en_i    (fifo_pop),
            .rdata_o    (fifo_rdata),
            .rempty_o   (fifo_empty)
        );



        always @(posedge clk_i or negedge reset_n_i) begin
            if (reset_n_i == 1'b0) begin
                r_noc_burst_in <= 1'b0;
                r_noc_burst_out <= 1'b0;
                r_burst_count_in <= {COUNT_SIZE{1'b0}};
                r_burst_count_out <= {COUNT_SIZE{1'b0}};
            end else begin
                r_noc_burst_in <= (noc_wrreq_i && !noc_stall_o) ? noc_burst_i : r_noc_burst_in;
                r_noc_burst_out <= (noc_wrreq_o && !noc_stall_i) ? noc_burst_out : r_noc_burst_out;
                r_burst_count_in <= rin_burst_count_in;
                r_burst_count_out <= rin_burst_count_out;
            end
        end



        always @* begin
            fifo_push = 1'b0;
            rin_burst_count_in = r_burst_count_in;
            rin_fifo_wdata = {FIFO_WIDTH{1'b0}};


            if (fifo_empty) begin
                rin_burst_count_in = {COUNT_SIZE{1'b0}};
            end


            if (noc_wrreq_i && !fifo_full) begin

                if (!r_noc_burst_in) begin
                    rin_fifo_wdata = fifo_wdata_noburst;


                    if (noc_burst_i) begin
                        if (!FIFO_PUSH_EMPTY_BURST_ONLY || fifo_empty) begin
                            fifo_push = 1'b1;
                        end
                    end


                    else begin
                        fifo_push = 1'b1;
                    end
                end
                

                else begin
                    fifo_push = 1'b1;
                    rin_fifo_wdata = fifo_wdata_burst;


                    if (!noc_burst_i) begin

                        if (fifo_empty) begin
                            rin_burst_count_in = 1;
                        end else begin
                            rin_burst_count_in = r_burst_count_in + 1;
                        end
                    end
                end
            end
        end



        always @* begin
            rin_noc_wrreq_out = 1'b0;
            rin_burst_count_out = r_burst_count_out;

            if (!fifo_empty) begin


                if (!FIFO_POP_FULL_BURST_ONLY || !noc_burst_out || burst_ready) begin
                    rin_noc_wrreq_out = 1'b1;
                end


                if (!noc_burst_out && r_noc_burst_out && !noc_stall_i) begin
                    rin_burst_count_out = r_burst_count_out + 1;
                end
            end
            else begin
                rin_burst_count_out = {COUNT_SIZE{1'b0}};
            end
        end




        assign noc_wrreq_o      = rin_noc_wrreq_out;
        assign noc_burst_o      = noc_burst_out;
        assign noc_bsel_o       = fifo_rdata[FIFO_WIDTH-NOC_BURST_SIZE-1 : FIFO_WIDTH-NOC_BURST_SIZE-NOC_BSEL_SIZE];
        assign noc_src_modid_o  = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+2*NOC_MODID_SIZE+2*NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+2*NOC_CHIPID_SIZE];
        assign noc_src_chipid_o = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+2*NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+NOC_CHIPID_SIZE];
        assign noc_trg_modid_o  = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_CHIPID_SIZE];
        assign noc_trg_chipid_o = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE];
        assign noc_mode_o       = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE-1 : NOC_DATA_SIZE+NOC_ADDR_SIZE];
        assign noc_addr_o       = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE-1 : NOC_DATA_SIZE];
        assign noc_data1_o      = fifo_rdata[2*NOC_DATA_SIZE-1 : NOC_DATA_SIZE];
        assign noc_data0_o      = fifo_rdata[NOC_DATA_SIZE-1 : 0];

        
    end
    else begin: disable_fifo

        assign noc_wrreq_o      = noc_wrreq_i;
        assign noc_burst_o      = noc_burst_i;
        assign noc_bsel_o       = noc_bsel_i;
        assign noc_src_chipid_o = noc_src_chipid_i;
        assign noc_src_modid_o  = noc_src_modid_i;
        assign noc_trg_chipid_o = noc_trg_chipid_i;
        assign noc_trg_modid_o  = noc_trg_modid_i;
        assign noc_mode_o       = noc_mode_i;
        assign noc_addr_o       = noc_addr_i;
        assign noc_data0_o      = noc_data0_i;
        assign noc_data1_o      = noc_data1_i;
        assign noc_stall_o      = noc_stall_i;

    end
    endgenerate


endmodule
module tcu_noc_fifo #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_NOC_FIFO       = 0,
    parameter FIFO_DEPTH                 = $clog2(MAX_BURST_LENGTH_MSG),
    parameter NOC_MASTER                 = 0,
    parameter FIFO_POP_FULL_BURST_ONLY   = 1,
    parameter FIFO_PUSH_EMPTY_BURST_ONLY = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    input  wire                          noc_wrreq_i,
    input  wire                          noc_burst_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_data1_i,
    output wire                          noc_stall_o,

    output wire                          noc_wrreq_o,
    output wire                          noc_burst_o,
    output wire      [NOC_BSEL_SIZE-1:0] noc_bsel_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_src_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_src_modid_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_trg_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_trg_modid_o,
    output wire      [NOC_MODE_SIZE-1:0] noc_mode_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output wire      [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_DATA_SIZE-1:0] noc_data1_o,
    input  wire                          noc_stall_i
);


    localparam FIFO_WIDTH = NOC_HEADER_SIZE + NOC_PAYLOAD_SIZE - NOC_ARQ_SIZE;

    localparam COUNT_SIZE = 8+1;


    generate
    if (TCU_ENABLE_NOC_FIFO) begin: enable_fifo

        reg [FIFO_WIDTH-1:0] rin_fifo_wdata;

        reg                  rin_noc_wrreq_out;
        reg                  r_noc_burst_in;
        reg                  r_noc_burst_out;
        reg [COUNT_SIZE-1:0] r_burst_count_in, rin_burst_count_in;
        reg [COUNT_SIZE-1:0] r_burst_count_out, rin_burst_count_out;


        wire [FIFO_WIDTH-1:0] fifo_wdata_noburst = {noc_burst_i,
                                                    noc_bsel_i,
                                                    noc_src_modid_i,
                                                    noc_src_chipid_i,
                                                    noc_trg_modid_i,
                                                    noc_trg_chipid_i,
                                                    noc_mode_i,
                                                    noc_addr_i,
                                                    noc_data0_i};

        wire [FIFO_WIDTH-1:0] fifo_wdata_burst = {noc_burst_i,
                                                    noc_bsel_i,
                                                    noc_data1_i,
                                                    noc_data0_i};

        wire [FIFO_WIDTH-1:0] fifo_rdata;

        wire fifo_empty;
        wire fifo_full;
        wire fifo_pop = rin_noc_wrreq_out && !noc_stall_i;
        reg fifo_push;
        wire noc_burst_out = fifo_rdata[FIFO_WIDTH-1];
        

        wire burst_ready = ((r_burst_count_in[COUNT_SIZE-2:0] > r_burst_count_out[COUNT_SIZE-2:0]) &&
                            (r_burst_count_in[COUNT_SIZE-1] == r_burst_count_out[COUNT_SIZE-1])) ||
                                ((r_burst_count_in[COUNT_SIZE-2:0] < r_burst_count_out[COUNT_SIZE-2:0]) &&
                                (r_burst_count_in[COUNT_SIZE-1] != r_burst_count_out[COUNT_SIZE-1]));


        assign noc_stall_o = (NOC_MASTER == 1) ? (fifo_full || !fifo_push) : fifo_full;


        sync_fifo #(
            .DATA_WIDTH (FIFO_WIDTH),
            .ADDR_WIDTH (FIFO_DEPTH),
            .USE_MEM    (1)
        ) i_fifo (
            .clk_i      (clk_i),
            .resetn_i   (reset_n_i),

            .wr_en_i    (fifo_push),
            .wdata_i    (rin_fifo_wdata),
            .wfull_o    (fifo_full),

            .rd_en_i    (fifo_pop),
            .rdata_o    (fifo_rdata),
            .rempty_o   (fifo_empty)
        );



        always @(posedge clk_i or negedge reset_n_i) begin
            if (reset_n_i == 1'b0) begin
                r_noc_burst_in <= 1'b0;
                r_noc_burst_out <= 1'b0;
                r_burst_count_in <= {COUNT_SIZE{1'b0}};
                r_burst_count_out <= {COUNT_SIZE{1'b0}};
            end else begin
                r_noc_burst_in <= (noc_wrreq_i && !noc_stall_o) ? noc_burst_i : r_noc_burst_in;
                r_noc_burst_out <= (noc_wrreq_o && !noc_stall_i) ? noc_burst_out : r_noc_burst_out;
                r_burst_count_in <= rin_burst_count_in;
                r_burst_count_out <= rin_burst_count_out;
            end
        end



        always @* begin
            fifo_push = 1'b0;
            rin_burst_count_in = r_burst_count_in;
            rin_fifo_wdata = {FIFO_WIDTH{1'b0}};


            if (fifo_empty) begin
                rin_burst_count_in = {COUNT_SIZE{1'b0}};
            end


            if (noc_wrreq_i && !fifo_full) begin

                if (!r_noc_burst_in) begin
                    rin_fifo_wdata = fifo_wdata_noburst;


                    if (noc_burst_i) begin
                        if (!FIFO_PUSH_EMPTY_BURST_ONLY || fifo_empty) begin
                            fifo_push = 1'b1;
                        end
                    end


                    else begin
                        fifo_push = 1'b1;
                    end
                end
                

                else begin
                    fifo_push = 1'b1;
                    rin_fifo_wdata = fifo_wdata_burst;


                    if (!noc_burst_i) begin

                        if (fifo_empty) begin
                            rin_burst_count_in = 1;
                        end else begin
                            rin_burst_count_in = r_burst_count_in + 1;
                        end
                    end
                end
            end
        end



        always @* begin
            rin_noc_wrreq_out = 1'b0;
            rin_burst_count_out = r_burst_count_out;

            if (!fifo_empty) begin


                if (!FIFO_POP_FULL_BURST_ONLY || !noc_burst_out || burst_ready) begin
                    rin_noc_wrreq_out = 1'b1;
                end


                if (!noc_burst_out && r_noc_burst_out && !noc_stall_i) begin
                    rin_burst_count_out = r_burst_count_out + 1;
                end
            end
            else begin
                rin_burst_count_out = {COUNT_SIZE{1'b0}};
            end
        end




        assign noc_wrreq_o      = rin_noc_wrreq_out;
        assign noc_burst_o      = noc_burst_out;
        assign noc_bsel_o       = fifo_rdata[FIFO_WIDTH-NOC_BURST_SIZE-1 : FIFO_WIDTH-NOC_BURST_SIZE-NOC_BSEL_SIZE];
        assign noc_src_modid_o  = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+2*NOC_MODID_SIZE+2*NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+2*NOC_CHIPID_SIZE];
        assign noc_src_chipid_o = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+2*NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+NOC_CHIPID_SIZE];
        assign noc_trg_modid_o  = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_MODID_SIZE+NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_CHIPID_SIZE];
        assign noc_trg_chipid_o = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE+NOC_CHIPID_SIZE-1 :
                                                NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE];
        assign noc_mode_o       = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE+NOC_MODE_SIZE-1 : NOC_DATA_SIZE+NOC_ADDR_SIZE];
        assign noc_addr_o       = fifo_rdata[NOC_DATA_SIZE+NOC_ADDR_SIZE-1 : NOC_DATA_SIZE];
        assign noc_data1_o      = fifo_rdata[2*NOC_DATA_SIZE-1 : NOC_DATA_SIZE];
        assign noc_data0_o      = fifo_rdata[NOC_DATA_SIZE-1 : 0];

        
    end
    else begin: disable_fifo

        assign noc_wrreq_o      = noc_wrreq_i;
        assign noc_burst_o      = noc_burst_i;
        assign noc_bsel_o       = noc_bsel_i;
        assign noc_src_chipid_o = noc_src_chipid_i;
        assign noc_src_modid_o  = noc_src_modid_i;
        assign noc_trg_chipid_o = noc_trg_chipid_i;
        assign noc_trg_modid_o  = noc_trg_modid_i;
        assign noc_mode_o       = noc_mode_i;
        assign noc_addr_o       = noc_addr_i;
        assign noc_data0_o      = noc_data0_i;
        assign noc_data1_o      = noc_data1_i;
        assign noc_stall_o      = noc_stall_i;

    end
    endgenerate


endmodule