data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(t);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #(t);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #(t)        \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #(t)        \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #(8*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #(8*t)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #(7*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #(3*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(9*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #(6*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(2*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #(2*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #(8*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #(16*T+2*t)      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #(15*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #(2*T)       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #(T*70);\n  ^\n%Error: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/SimTest.v:19: Cannot find file containing module: \'AltDebounce\'\n AltDebounce #( 40, 6 ) altDebounce( clk, reset, sig, debounced );\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/AltDebounce\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/AltDebounce.v\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/AltDebounce.sv\n             AltDebounce\n             AltDebounce.v\n             AltDebounce.sv\n             obj_dir/AltDebounce\n             obj_dir/AltDebounce.v\n             obj_dir/AltDebounce.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SimTest();

	localparam t = 1;
	localparam T = 10;


	reg clk, reset, sig;


	wire debounced;



	AltDebounce #( 40, 6 ) altDebounce( clk, reset, sig, debounced );

	always
	begin
		clk = 1'b1;
		#(t);
		clk = 1'b0;
		#(t);
	end

	initial begin

		reset = 1'b0;
		sig = 1'b0;
		#(t)
		reset = 1'b1;
		#(t)
		reset = 1'b0;
		#(8*t)
		

		#(8*T)
		sig = ~sig;
		

		#(7*T)
		sig = ~sig;
		


		#(3*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		


		#(9*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;


		

		#(6*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;
		

		#(2*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;



		#(16*T+2*t)
		sig = ~sig;


		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;

		
		#(1*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;


		#(T*70);
        

		$stop;
	end
      
endmodule
module SimTest();


	localparam t = 1;
	localparam T = 10;


	reg clk, reset, sig;


	wire debounced;



	AltDebounce #( 40, 6 ) altDebounce( clk, reset, sig, debounced );

	always
	begin
		clk = 1'b1;
		#(t);
		clk = 1'b0;
		#(t);
	end

	initial begin

		reset = 1'b0;
		sig = 1'b0;
		#(t)
		reset = 1'b1;
		#(t)
		reset = 1'b0;
		#(8*t)
		

		#(8*T)
		sig = ~sig;
		

		#(7*T)
		sig = ~sig;
		


		#(3*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		


		#(9*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;


		

		#(6*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;
		

		#(2*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;



		#(16*T+2*t)
		sig = ~sig;


		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;

		
		#(1*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;


		#(T*70);
        

		$stop;
	end
      
endmodule