data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv
1: b'%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:5: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import Sim_Bus_Pkg::*;\n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:12: Unsupported: Ignoring delay on this delayed statement.\n  always #5 r_Bus_Clk = ~r_Bus_Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  Bus_Driver d1 = new(hook);\n                ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:21: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  Sim_Checker c1 = new("Bus_Rd_DPRAM_TB");\n                 ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:37: syntax error, unexpected \'@\'\n    @(posedge r_Bus_Clk);\n    ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:41: syntax error, unexpected \'@\'\n    @(posedge r_Bus_Clk);\n    ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Bus_Rd_DPRAM_TB.sv:43: syntax error, unexpected \'@\'\n    @(posedge r_Bus_Clk);\n    ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module Bus_Rd_DPRAM_TB ();
  
  import Sim_Bus_Pkg::*;
  import Sim_Checker_Pkg::*;

  logic r_Bus_Clk = 1'b0, r_Wr_DV = 1'b0;
  logic [15:0] r_Wr_Data = 0, r_Wr_Addr = 0, w_Rd_Data;
  

  always #5 r_Bus_Clk = ~r_Bus_Clk;


  Bus_Interface hook(.i_Bus_Clk(r_Bus_Clk));


  Bus_Driver d1 = new(hook);


  Sim_Checker c1 = new("Bus_Rd_DPRAM_TB");
  
  Bus_Rd_DPRAM #(.DEPTH(256)) UUT
  (.i_Bus_Clk(r_Bus_Clk),
   .i_Bus_CS(hook.r_Bus_CS),
   .i_Bus_Wr_Rd_n(hook.r_Bus_Wr_Rd_n),
   .i_Bus_Addr8(hook.r_Bus_Addr8[15:0]),
   .o_Bus_Rd_Data(hook.r_Bus_Rd_Data),
   .o_Bus_Rd_DV(hook.r_Bus_Rd_DV),

   .i_Wr_Clk(r_Bus_Clk),
   .i_Wr_Addr(r_Wr_Addr),
   .i_Wr_DV(r_Wr_DV),
   .i_Wr_Data(r_Wr_Data));
  
  task Write_Data(input [15:0] data, input [15:0] addr);
    @(posedge r_Bus_Clk);
    r_Wr_DV   <= 1'b1;
    r_Wr_Data <= data;
    r_Wr_Addr <= addr;
    @(posedge r_Bus_Clk);
    r_Wr_DV   <= 1'b0;
    @(posedge r_Bus_Clk);
  endtask


  initial
    begin

      c1.t_Set_Printing(1);
      d1.t_Bus_Print_Disable();
      

      Write_Data(16'hABCD, 0);
      d1.t_Bus_Rd(0, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hABCD, w_Rd_Data);


      Write_Data(16'hDEAD, 5);
      d1.t_Bus_Rd(5<<1, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hDEAD, w_Rd_Data);
      

      d1.t_Bus_Wr(5, 16'hBEEF);
      d1.t_Bus_Rd(5<<1, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hDEAD, w_Rd_Data);
            
      c1.t_Print_Results();

      $finish();
      
    end
  
endmodule
module Bus_Rd_DPRAM_TB ();

  
  import Sim_Bus_Pkg::*;
  import Sim_Checker_Pkg::*;

  logic r_Bus_Clk = 1'b0, r_Wr_DV = 1'b0;
  logic [15:0] r_Wr_Data = 0, r_Wr_Addr = 0, w_Rd_Data;
  

  always #5 r_Bus_Clk = ~r_Bus_Clk;


  Bus_Interface hook(.i_Bus_Clk(r_Bus_Clk));


  Bus_Driver d1 = new(hook);


  Sim_Checker c1 = new("Bus_Rd_DPRAM_TB");
  
  Bus_Rd_DPRAM #(.DEPTH(256)) UUT
  (.i_Bus_Clk(r_Bus_Clk),
   .i_Bus_CS(hook.r_Bus_CS),
   .i_Bus_Wr_Rd_n(hook.r_Bus_Wr_Rd_n),
   .i_Bus_Addr8(hook.r_Bus_Addr8[15:0]),
   .o_Bus_Rd_Data(hook.r_Bus_Rd_Data),
   .o_Bus_Rd_DV(hook.r_Bus_Rd_DV),

   .i_Wr_Clk(r_Bus_Clk),
   .i_Wr_Addr(r_Wr_Addr),
   .i_Wr_DV(r_Wr_DV),
   .i_Wr_Data(r_Wr_Data));
  
  task Write_Data(input [15:0] data, input [15:0] addr);
    @(posedge r_Bus_Clk);
    r_Wr_DV   <= 1'b1;
    r_Wr_Data <= data;
    r_Wr_Addr <= addr;
    @(posedge r_Bus_Clk);
    r_Wr_DV   <= 1'b0;
    @(posedge r_Bus_Clk);
  endtask


  initial
    begin

      c1.t_Set_Printing(1);
      d1.t_Bus_Print_Disable();
      

      Write_Data(16'hABCD, 0);
      d1.t_Bus_Rd(0, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hABCD, w_Rd_Data);


      Write_Data(16'hDEAD, 5);
      d1.t_Bus_Rd(5<<1, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hDEAD, w_Rd_Data);
      

      d1.t_Bus_Wr(5, 16'hBEEF);
      d1.t_Bus_Rd(5<<1, w_Rd_Data);
      c1.t_Compare_Two_Inputs(16'hDEAD, w_Rd_Data);
            
      c1.t_Print_Results();

      $finish();
      
    end
  
endmodule