data/full_repos/permissive/522139538/uart_tx_16bit.v
1: b"%Error: data/full_repos/permissive/522139538/uart_tx_16bit.v:14: Cannot find file containing module: 'uart_send'\nuart_send u_uart_send(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_send\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_send.v\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_send.sv\n             uart_send\n             uart_send.v\n             uart_send.sv\n             obj_dir/uart_send\n             obj_dir/uart_send.v\n             obj_dir/uart_send.sv\n%Error: Exiting due to 1 error(s)\n"
module uart_top(
    input sys_clk,
    input sys_rst_n,
    
    input send_en,
    input [16-1:0] data_16,
    
    output  uart_tx_busy,
    output  uart_txd
);
reg uart_en;
reg [7:0] data_in;

uart_send u_uart_send(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    
    .uart_en(uart_en),
    .uart_din(data_in),
    .uart_tx_busy(uart_tx_busy),
    .uart_txd(uart_txd)
    );

reg [2:0] state;
always @(posedge sys_clk or negedge sys_rst_n) begin         
    if (!sys_rst_n)  begin
        state <= 0;
        uart_en <= 0;
        data_in <= 0;
    end
    else if( state == 0) begin
        if( send_en == 1) begin
            uart_en <= 1;
            data_in <= data_16[7:0];
            state <= 1;
        end
        else begin
            state <= 0;
            uart_en <= 0;
            data_in <= data_in;
        end
    end
    else if( state == 1) begin
            if( uart_tx_busy == 0) begin
                uart_en <= 1;
                data_in <= data_16[15:8];
                state <= 0;
            end
            else begin
                uart_en <= 0;
                data_in <= data_in;
                state <= 1;
            end
        end
end

endmodule
module uart_top(
    input sys_clk,
    input sys_rst_n,
    
    input send_en,
    input [16-1:0] data_16,
    
    output  uart_tx_busy,
    output  uart_txd
);

reg uart_en;
reg [7:0] data_in;

uart_send u_uart_send(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    
    .uart_en(uart_en),
    .uart_din(data_in),
    .uart_tx_busy(uart_tx_busy),
    .uart_txd(uart_txd)
    );

reg [2:0] state;
always @(posedge sys_clk or negedge sys_rst_n) begin         
    if (!sys_rst_n)  begin
        state <= 0;
        uart_en <= 0;
        data_in <= 0;
    end
    else if( state == 0) begin
        if( send_en == 1) begin
            uart_en <= 1;
            data_in <= data_16[7:0];
            state <= 1;
        end
        else begin
            state <= 0;
            uart_en <= 0;
            data_in <= data_in;
        end
    end
    else if( state == 1) begin
            if( uart_tx_busy == 0) begin
                uart_en <= 1;
                data_in <= data_16[15:8];
                state <= 0;
            end
            else begin
                uart_en <= 0;
                data_in <= data_in;
                state <= 1;
            end
        end
end

endmodule