data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n                #2\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n                #4\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n                #2\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n                #4\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n            #12\n            ^\n%Error: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:182: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("combo2_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:183: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, combo2_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/512077043/combo2_sbit2wrd_fifo_sotp/combo2_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #(DURATION)\n        ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module combo2_tb();


    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;



    

    localparam RGBW_T0H = 16;
    localparam RGBW_T0L = 74;
    localparam RGBW_T1H = 45;
    localparam RGBW_T1L = 45;
    localparam RGBW_STR_RST = 7681;
    localparam COUNTER_MAX = 7800;



    wire                    r_en;
    wire    [DATA_SIZE-1:0] r_data;
    wire                    r_empty;
    wire                    w_full;
    wire                    w_en;
    wire    [DATA_SIZE-1:0] w_data;
    wire                    rgb_wr_fifo_overflow;


    reg                     rgb_sbit_strobe = 1'b0;
    reg                     rgb_sbit_value = 1'b0;
    reg                     rgb_sbit_stream_reset = 1'b0;
    reg                     sbit_rst = 1'b0;


    reg                     rgb_rst = 1'b0;
    wire                    rgbw_out_serial;



    reg                     r_clk = 0;
    reg                     r_rst = 0;
    reg                     w_clk = 0;
    reg                     w_rst = 0;


    reg                     bit_first  = 1'b1;
    reg  [5:0]              where_am_i = 6'd0;



    integer                 i = 0;
    integer                 j = 0;


    localparam DURATION = 25000;


    always begin
        #1
        r_clk <= ~r_clk;
        w_clk <= ~w_clk;
    end


    async_fifo #(
        .DATA_SIZE(DATA_SIZE),
        .ADDR_SIZE(ADDR_SIZE)
    ) fifo (
        .w_data(w_data),
        .w_en(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .r_en(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .w_full(w_full),
        .r_data(r_data),
        .r_empty(r_empty)
    );


    rgb_sbit2wrduut (

        .clk(w_clk),
        .rst(sbit_rst),
        .in_strobe(rgb_sbit_strobe),
        .in_sbit_value(rgb_sbit_value),
        .in_stream_reset(rgb_sbit_stream_reset),
        .in_wr_fifo_full(w_full),

        .out_word(w_data),
        .out_strobe(w_en),
        .out_wr_fifo_overflow(rgb_wr_fifo_overflow)
    );


    rgb_sotp #( 
        .RGBW_T0H(RGBW_T0H),
        .RGBW_T0L(RGBW_T0L),
        .RGBW_T1H(RGBW_T1H),
        .RGBW_T1L(RGBW_T1L),
        .RGBW_STR_RST(RGBW_STR_RST),
        .COUNTER_MAX(COUNTER_MAX)
    ) sotp (

        .clk(r_clk),
        .rst(rgb_rst),
        .in_rd_fifo_empty(r_empty),
        .in_rd_fifo_data(r_data),

        .out_rd_fifo_en(r_en),
        .out_sig(rgbw_out_serial)
    );
    

    initial begin
    


        #10
        r_rst <= 1'b1;
        w_rst <= 1'b1;
        rgb_rst <= 1'b1;
        sbit_rst <= 1'b1;
        #50
        r_rst <= 1'b0;
        w_rst <= 1'b0;
        rgb_rst <= 1'b0;
        sbit_rst <= 1'b0;
        

        #100
        rgb_rst <= 1'b0;


        for (j = 0; j < 4; j = j + 1) begin
            for (i = 0; i < 12; i = i + 1) begin
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = ~bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
            end
            #12
            bit_first = ~bit_first;
        end
        
    end


    initial begin
    

        $dumpfile("combo2_tb.vcd");
        $dumpvars(0, combo2_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end

endmodule
module combo2_tb();



    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;



    

    localparam RGBW_T0H = 16;
    localparam RGBW_T0L = 74;
    localparam RGBW_T1H = 45;
    localparam RGBW_T1L = 45;
    localparam RGBW_STR_RST = 7681;
    localparam COUNTER_MAX = 7800;



    wire                    r_en;
    wire    [DATA_SIZE-1:0] r_data;
    wire                    r_empty;
    wire                    w_full;
    wire                    w_en;
    wire    [DATA_SIZE-1:0] w_data;
    wire                    rgb_wr_fifo_overflow;


    reg                     rgb_sbit_strobe = 1'b0;
    reg                     rgb_sbit_value = 1'b0;
    reg                     rgb_sbit_stream_reset = 1'b0;
    reg                     sbit_rst = 1'b0;


    reg                     rgb_rst = 1'b0;
    wire                    rgbw_out_serial;



    reg                     r_clk = 0;
    reg                     r_rst = 0;
    reg                     w_clk = 0;
    reg                     w_rst = 0;


    reg                     bit_first  = 1'b1;
    reg  [5:0]              where_am_i = 6'd0;



    integer                 i = 0;
    integer                 j = 0;


    localparam DURATION = 25000;


    always begin
        #1
        r_clk <= ~r_clk;
        w_clk <= ~w_clk;
    end


    async_fifo #(
        .DATA_SIZE(DATA_SIZE),
        .ADDR_SIZE(ADDR_SIZE)
    ) fifo (
        .w_data(w_data),
        .w_en(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .r_en(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .w_full(w_full),
        .r_data(r_data),
        .r_empty(r_empty)
    );


    rgb_sbit2wrduut (

        .clk(w_clk),
        .rst(sbit_rst),
        .in_strobe(rgb_sbit_strobe),
        .in_sbit_value(rgb_sbit_value),
        .in_stream_reset(rgb_sbit_stream_reset),
        .in_wr_fifo_full(w_full),

        .out_word(w_data),
        .out_strobe(w_en),
        .out_wr_fifo_overflow(rgb_wr_fifo_overflow)
    );


    rgb_sotp #( 
        .RGBW_T0H(RGBW_T0H),
        .RGBW_T0L(RGBW_T0L),
        .RGBW_T1H(RGBW_T1H),
        .RGBW_T1L(RGBW_T1L),
        .RGBW_STR_RST(RGBW_STR_RST),
        .COUNTER_MAX(COUNTER_MAX)
    ) sotp (

        .clk(r_clk),
        .rst(rgb_rst),
        .in_rd_fifo_empty(r_empty),
        .in_rd_fifo_data(r_data),

        .out_rd_fifo_en(r_en),
        .out_sig(rgbw_out_serial)
    );
    

    initial begin
    


        #10
        r_rst <= 1'b1;
        w_rst <= 1'b1;
        rgb_rst <= 1'b1;
        sbit_rst <= 1'b1;
        #50
        r_rst <= 1'b0;
        w_rst <= 1'b0;
        rgb_rst <= 1'b0;
        sbit_rst <= 1'b0;
        

        #100
        rgb_rst <= 1'b0;


        for (j = 0; j < 4; j = j + 1) begin
            for (i = 0; i < 12; i = i + 1) begin
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = ~bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
            end
            #12
            bit_first = ~bit_first;
        end
        
    end


    initial begin
    

        $dumpfile("combo2_tb.vcd");
        $dumpvars(0, combo2_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end

endmodule