data/full_repos/permissive/502868308/src/cells.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/502868308/src/cells.v:10: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'buffer_cell\'\nmodule buffer_cell (\n       ^~~~~~~~~~~\n                                                                      : ... Top module \'and_cell\'\nmodule and_cell (\n       ^~~~~~~~\n                                                                      : ... Top module \'or_cell\'\nmodule or_cell (\n       ^~~~~~~\n                                                                      : ... Top module \'xor_cell\'\nmodule xor_cell (\n       ^~~~~~~~\n                                                                      : ... Top module \'nand_cell\'\nmodule nand_cell (\n       ^~~~~~~~~\n                                                                      : ... Top module \'not_cell\'\nmodule not_cell (\n       ^~~~~~~~\n                                                                      : ... Top module \'mux_cell\'\nmodule mux_cell (\n       ^~~~~~~~\n                                                                      : ... Top module \'dff_cell\'\nmodule dff_cell (\n       ^~~~~~~~\n                                                                      : ... Top module \'dffsr_cell\'\nmodule dffsr_cell (\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module or_cell (
    input wire a,
    input wire b,
    output wire out
    );

    assign out = a | b;
endmodule
module or_cell (
    input wire a,
    input wire b,
    output wire out
    );


    assign out = a | b;
endmodule