data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/eth_parser.v
data/verilator_xmls/039a0472-3ff1-4d93-9a60-73f09aee4670.xml
module eth_parser
    #(parameter C_S_AXIS_DATA_WIDTH  = 256,
      parameter C_S_AXIS_TUSER_WIDTH = 128,
      parameter SRC_PORT_POS         = 16,
      parameter NUM_QUEUES           = 8
    )
    (

      input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,
      input  [C_S_AXIS_TUSER_WIDTH-1:0]  tuser,
      input                              valid,
      input 				             tlast,


      output reg [47:0]                  dst_mac,
      output reg [47:0]                  src_mac,
      output reg                         eth_done,
      output reg [NUM_QUEUES-1:0]        src_port,
  

      input                              reset,
      input                              clk
    );
    


   localparam NUM_STATES         = 2;
   localparam READ_MAC_ADDRESSES = 1;
   localparam WAIT_EOP           = 2;



   reg [47:0]                  dst_mac_w;
   reg [47:0]                  src_mac_w;
   reg                         eth_done_w;
   reg [NUM_QUEUES-1:0]        src_port_w;
   
   reg [NUM_STATES-1:0]        state, state_next;



   always @(*) begin
      src_mac_w      = 0;
      dst_mac_w      = 0;
      eth_done_w     = 0;
      src_port_w     = 0;
      state_next     = state;
      
	  case(state)

        READ_MAC_ADDRESSES: begin
           if(valid) begin
              src_port_w   = tuser[SRC_PORT_POS+7:SRC_PORT_POS];
              dst_mac_w    = tdata[47:0];
              src_mac_w    = tdata[95:48];
	          eth_done_w   = 1;
              state_next = WAIT_EOP;
           end
        end

        WAIT_EOP: begin
           if(valid && tlast)
              state_next = READ_MAC_ADDRESSES;
           end
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
	     src_port <= {NUM_QUEUES{1'b0}};
		 dst_mac  <= 48'b0;
		 src_mac  <= 48'b0;
		 eth_done <= 0;
		 
         state  <= READ_MAC_ADDRESSES;
      end
      else begin
	     src_port <= src_port_w;
		 dst_mac  <= dst_mac_w;
		 src_mac  <= src_mac_w;
		 eth_done <= eth_done_w;
		 
         state  <= state_next;
      end
   end

endmodule
module eth_parser
    #(parameter C_S_AXIS_DATA_WIDTH  = 256,
      parameter C_S_AXIS_TUSER_WIDTH = 128,
      parameter SRC_PORT_POS         = 16,
      parameter NUM_QUEUES           = 8
    )
    (

      input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,
      input  [C_S_AXIS_TUSER_WIDTH-1:0]  tuser,
      input                              valid,
      input 				             tlast,


      output reg [47:0]                  dst_mac,
      output reg [47:0]                  src_mac,
      output reg                         eth_done,
      output reg [NUM_QUEUES-1:0]        src_port,
  

      input                              reset,
      input                              clk
    );

    


   localparam NUM_STATES         = 2;
   localparam READ_MAC_ADDRESSES = 1;
   localparam WAIT_EOP           = 2;



   reg [47:0]                  dst_mac_w;
   reg [47:0]                  src_mac_w;
   reg                         eth_done_w;
   reg [NUM_QUEUES-1:0]        src_port_w;
   
   reg [NUM_STATES-1:0]        state, state_next;



   always @(*) begin
      src_mac_w      = 0;
      dst_mac_w      = 0;
      eth_done_w     = 0;
      src_port_w     = 0;
      state_next     = state;
      
	  case(state)

        READ_MAC_ADDRESSES: begin
           if(valid) begin
              src_port_w   = tuser[SRC_PORT_POS+7:SRC_PORT_POS];
              dst_mac_w    = tdata[47:0];
              src_mac_w    = tdata[95:48];
	          eth_done_w   = 1;
              state_next = WAIT_EOP;
           end
        end

        WAIT_EOP: begin
           if(valid && tlast)
              state_next = READ_MAC_ADDRESSES;
           end
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
	     src_port <= {NUM_QUEUES{1'b0}};
		 dst_mac  <= 48'b0;
		 src_mac  <= 48'b0;
		 eth_done <= 0;
		 
         state  <= READ_MAC_ADDRESSES;
      end
      else begin
	     src_port <= src_port_w;
		 dst_mac  <= dst_mac_w;
		 src_mac  <= src_mac_w;
		 eth_done <= eth_done_w;
		 
         state  <= state_next;
      end
   end

endmodule