data/full_repos/permissive/497530416/pipe/w_reg.v
1: b"%Error: data/full_repos/permissive/497530416/pipe/w_reg.v:8: Input/output/inout does not appear in port list: 'm_cnd'\noutput reg m_cnd;\n           ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module w_reg_pipe (clk, m_icode, m_valE, m_valM, m_dstE, m_dstM, W_icode, W_valE, W_valM, W_dstE, W_dstM);

input clk;

input [3:0] m_icode, m_dstE, m_dstM;
input [63:0] m_valE, m_valM;

output reg m_cnd;

output reg [3:0] W_icode, W_dstE, W_dstM;
output reg [63:0] W_valE, W_valM;

always @(posedge clk)
    begin


        W_icode <= m_icode;







        W_valE <= m_valE;
        W_valM <= m_valM;
        W_dstE <= m_dstE;
        W_dstM <= m_dstM;
    end
endmodule
module w_reg_pipe (clk, m_icode, m_valE, m_valM, m_dstE, m_dstM, W_icode, W_valE, W_valM, W_dstE, W_dstM);


input clk;

input [3:0] m_icode, m_dstE, m_dstM;
input [63:0] m_valE, m_valM;

output reg m_cnd;

output reg [3:0] W_icode, W_dstE, W_dstM;
output reg [63:0] W_valE, W_valM;

always @(posedge clk)
    begin


        W_icode <= m_icode;







        W_valE <= m_valE;
        W_valM <= m_valM;
        W_dstE <= m_dstE;
        W_dstM <= m_dstM;
    end
endmodule