data/full_repos/permissive/461000256/hdl/Program_Counter.v
data/verilator_xmls/48e236d8-88b1-4003-82d2-94ceda733178.xml
module Program_Counter (
	input  wire 		clk,
	input  wire [`IMW-1:0] in,
	output reg  [`IMW-1:0] out
);
	always @(posedge clk) begin
		out <= #1 in;
	end
	
endmodule
module Program_Counter (
	input  wire 		clk,
	input  wire [`IMW-1:0] in,
	output reg  [`IMW-1:0] out
);

	always @(posedge clk) begin
		out <= #1 in;
	end
	
endmodule