data/full_repos/permissive/515100461/ALU/test_Alu.v
1: b'%Error: data/full_repos/permissive/515100461/ALU/test_Alu.v:12: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515100461/ALU/test_Alu.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test_alu);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:26: Unsupported: Ignoring delay on this delayed statement.\n    b = -676745;#10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:39: Unsupported: Ignoring delay on this delayed statement.\n    b = -676745;#10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n    b = -676745;#10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_Alu.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #40 $finish;\n    ^\n%Error: data/full_repos/permissive/515100461/ALU/test_Alu.v:71: Unsupported or unknown PLI call: $monitor\n    $monitor("Time=%d\\ncontrol = %b\\n a = %b\\t\\t\\t%d\\n b = %b\\t\\t\\t%d\\n end_result = %b\\t\\t%d\\n overflow = %b\\n",\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_alu;

reg signed [63:0] a;
reg signed [63:0] b;
wire signed[63:0] end_result;
wire carry_overflow;
reg[1:0] control;

alu uut(.control(control),.a(a),.b(b),.end_result(end_result),.carry_overflow(carry_overflow));

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,test_alu);

    control = 2'b00;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b01;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b10;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b11;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;
    
    #40 $finish;
end

initial
    $monitor("Time=%d\ncontrol = %b\n a = %b\t\t\t%d\n b = %b\t\t\t%d\n end_result = %b\t\t%d\n overflow = %b\n",
              $time,control,a,a,b,b,end_result,end_result,carry_overflow);

endmodule
module test_alu;


reg signed [63:0] a;
reg signed [63:0] b;
wire signed[63:0] end_result;
wire carry_overflow;
reg[1:0] control;

alu uut(.control(control),.a(a),.b(b),.end_result(end_result),.carry_overflow(carry_overflow));

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,test_alu);

    control = 2'b00;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b01;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b10;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;#10;

      control = 2'b11;
    a = 3;
    b = 1;
    #10
    a = -2456;
    b = 99876;
    #10
    a = 5897;
    b = -123;
    #10
    a = 457869;
    b = -676745;
    
    #40 $finish;
end

initial
    $monitor("Time=%d\ncontrol = %b\n a = %b\t\t\t%d\n b = %b\t\t\t%d\n end_result = %b\t\t%d\n overflow = %b\n",
              $time,control,a,a,b,b,end_result,end_result,carry_overflow);

endmodule