data/full_repos/permissive/524522105/library/sr74194.v
data/verilator_xmls/a8e9e78c-a1ad-48a0-93b0-45562bcd2547.xml
module sr74194 ( input            clock,
                 input            serial_in,
                 output reg [3:0] parallel_out = 4'b0,
                 input      [3:0] parallel_in,
                 input            mode );
  




  always @ ( posedge clock )
    begin
      parallel_out[3:1] <= mode ? parallel_in[3:1] : parallel_out[2:0];
      parallel_out[0] <= mode ? parallel_in[0] : serial_in;
    end
endmodule
module sr74194 ( input            clock,
                 input            serial_in,
                 output reg [3:0] parallel_out = 4'b0,
                 input      [3:0] parallel_in,
                 input            mode );

  




  always @ ( posedge clock )
    begin
      parallel_out[3:1] <= mode ? parallel_in[3:1] : parallel_out[2:0];
      parallel_out[0] <= mode ? parallel_in[0] : serial_in;
    end
endmodule