data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v
1: b'%Error: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:38: Unsupported or unknown PLI call: $urandom\n        waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;\n                             ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:53: Unsupported or unknown PLI call: $urandom\n                waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;\n                                     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Error: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:72: syntax error, unexpected \'@\'\n        @(negedge reset);\n        ^\n%Error: data/full_repos/permissive/429782749/test/testbench/mips_cpu_bus_generic_tb.v:75: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_cpu_bus_generic_tb();
    parameter RAM_INIT_FILE = "";
    parameter EXPECTED_REG_V0 = -1213;
    parameter TIMEOUT_CYCLES = 10_000;
    parameter MAX_WAIT_REQUEST_CYCLES = 3;
    
    logic clk;
    logic reset;


    logic active;
    logic[31:0] register_v0;
   
    logic[31:0] address;
    logic[31:0] prev_address;

    logic write;
    logic read;
    logic waitrequest;
    logic[31:0] writedata;
    logic[3:0] byteenable;
    logic[31:0] readdata;

    logic[11:0] RAM_addr;

    logic prog_read;
    logic prog_write;
    logic[31:0] prog_read_data;
   

    logic stack_read;
    logic stack_write;
    logic[31:0] stack_read_data;

    int waitrequest_cycles;

    initial begin
        waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;

        reset = 0;
        clk = 0;
        #5;
        reset = 1;
        clk = !clk;
        #5;
        clk = !clk;
        #5;
        clk = !clk;
        reset = 0;
        repeat(TIMEOUT_CYCLES) begin
            if(waitrequest_cycles == 0) begin
                waitrequest = 0;
                waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;
            end
            else begin
                waitrequest = 1;
            end

            #5;
            clk = !clk;
            #5;
            clk = !clk;
            waitrequest_cycles -= 1;
        end    
        $display("output: %d", register_v0);
        $fatal(2, "Simulation timeout");
    end


    initial begin

        @(negedge reset);
        @(posedge clk);
        while(active) begin
            @(posedge clk);
        end

        $display("output: %d", register_v0);
        if(register_v0 != EXPECTED_REG_V0) begin
            $fatal(2, "Expected %d for reg_v0, got: %d ", EXPECTED_REG_V0, register_v0);
        end
        $finish;
    end

    assign RAM_addr = address[13:2];

    always_comb begin


        if(prev_address < (4096 << 2)) begin
            readdata = stack_read_data;
        end

        else if(prev_address >= 32'hBFC0_0000 && 
           prev_address < (32'hBFC0_0000 + (4096 << 2)) ) begin
            readdata = prog_read_data;
        end 
        else begin
            readdata = 0;
        end

  
        if(address < (4096 << 2)) begin
            stack_read = read;
            stack_write = write;
        end
        else begin
            stack_read = 0;
            stack_write = 0;
        end

        if(address >= 32'hBFC0_0000 && 
           address < (32'hBFC0_0000 + (4096 << 2)) ) begin
            prog_read = read;
            prog_write = write;
        end
        else begin
            prog_read = 0;
            prog_write = 0;
        end
    end

    always_ff @(posedge clk) begin
        prev_address <= address; 
    end


    RAM_32x4096 #(RAM_INIT_FILE) program_region(
        .clk(clk),
        .address(RAM_addr),
        .read(prog_read),
        .write(prog_write),
        .byteenable(byteenable),
        .writedata(writedata),
        .readdata(prog_read_data)
    );

    RAM_32x4096 stack_region(
        .clk(clk),
        .address(RAM_addr),
        .read(stack_read),
        .write(stack_write),
        .byteenable(byteenable),
        .writedata(writedata),
        .readdata(stack_read_data)
    );  

    mips_cpu_bus mips(.clk(clk), 
                 .reset(reset), 
                 .active(active),
                 .register_v0(register_v0),

                 .address(address),
                 .write(write),
                 .read(read),
                 .waitrequest(waitrequest),
                 .writedata(writedata),
                 .byteenable(byteenable),
                 .readdata(readdata) 
    );
endmodule
module mips_cpu_bus_generic_tb();

    parameter RAM_INIT_FILE = "";
    parameter EXPECTED_REG_V0 = -1213;
    parameter TIMEOUT_CYCLES = 10_000;
    parameter MAX_WAIT_REQUEST_CYCLES = 3;
    
    logic clk;
    logic reset;


    logic active;
    logic[31:0] register_v0;
   
    logic[31:0] address;
    logic[31:0] prev_address;

    logic write;
    logic read;
    logic waitrequest;
    logic[31:0] writedata;
    logic[3:0] byteenable;
    logic[31:0] readdata;

    logic[11:0] RAM_addr;

    logic prog_read;
    logic prog_write;
    logic[31:0] prog_read_data;
   

    logic stack_read;
    logic stack_write;
    logic[31:0] stack_read_data;

    int waitrequest_cycles;

    initial begin
        waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;

        reset = 0;
        clk = 0;
        #5;
        reset = 1;
        clk = !clk;
        #5;
        clk = !clk;
        #5;
        clk = !clk;
        reset = 0;
        repeat(TIMEOUT_CYCLES) begin
            if(waitrequest_cycles == 0) begin
                waitrequest = 0;
                waitrequest_cycles = $urandom % MAX_WAIT_REQUEST_CYCLES + 1;
            end
            else begin
                waitrequest = 1;
            end

            #5;
            clk = !clk;
            #5;
            clk = !clk;
            waitrequest_cycles -= 1;
        end    
        $display("output: %d", register_v0);
        $fatal(2, "Simulation timeout");
    end


    initial begin

        @(negedge reset);
        @(posedge clk);
        while(active) begin
            @(posedge clk);
        end

        $display("output: %d", register_v0);
        if(register_v0 != EXPECTED_REG_V0) begin
            $fatal(2, "Expected %d for reg_v0, got: %d ", EXPECTED_REG_V0, register_v0);
        end
        $finish;
    end

    assign RAM_addr = address[13:2];

    always_comb begin


        if(prev_address < (4096 << 2)) begin
            readdata = stack_read_data;
        end

        else if(prev_address >= 32'hBFC0_0000 && 
           prev_address < (32'hBFC0_0000 + (4096 << 2)) ) begin
            readdata = prog_read_data;
        end 
        else begin
            readdata = 0;
        end

  
        if(address < (4096 << 2)) begin
            stack_read = read;
            stack_write = write;
        end
        else begin
            stack_read = 0;
            stack_write = 0;
        end

        if(address >= 32'hBFC0_0000 && 
           address < (32'hBFC0_0000 + (4096 << 2)) ) begin
            prog_read = read;
            prog_write = write;
        end
        else begin
            prog_read = 0;
            prog_write = 0;
        end
    end

    always_ff @(posedge clk) begin
        prev_address <= address; 
    end


    RAM_32x4096 #(RAM_INIT_FILE) program_region(
        .clk(clk),
        .address(RAM_addr),
        .read(prog_read),
        .write(prog_write),
        .byteenable(byteenable),
        .writedata(writedata),
        .readdata(prog_read_data)
    );

    RAM_32x4096 stack_region(
        .clk(clk),
        .address(RAM_addr),
        .read(stack_read),
        .write(stack_write),
        .byteenable(byteenable),
        .writedata(writedata),
        .readdata(stack_read_data)
    );  

    mips_cpu_bus mips(.clk(clk), 
                 .reset(reset), 
                 .active(active),
                 .register_v0(register_v0),

                 .address(address),
                 .write(write),
                 .read(read),
                 .waitrequest(waitrequest),
                 .writedata(writedata),
                 .byteenable(byteenable),
                 .readdata(readdata) 
    );
endmodule