data/full_repos/permissive/491816568/counter_tb.v
1: b'%Error: data/full_repos/permissive/491816568/counter_tb.v:2: Cannot find include file: counter.v\n`include "counter.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491816568,data/full_repos/permissive/491816568/counter.v\n             data/full_repos/permissive/491816568,data/full_repos/permissive/491816568/counter.v.v\n             data/full_repos/permissive/491816568,data/full_repos/permissive/491816568/counter.v.sv\n             counter.v\n             counter.v.v\n             counter.v.sv\n             obj_dir/counter.v\n             obj_dir/counter.v.v\n             obj_dir/counter.v.sv\n%Error: data/full_repos/permissive/491816568/counter_tb.v:4: Cannot find include file: altera_mf.v\n`include "altera_mf.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491816568/counter_tb.v:7: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491816568/counter_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491816568/counter_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("main.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491816568/counter_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491816568/counter_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst_n = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/491816568/counter_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst_n = 1; wrreq = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/491816568/counter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #2500; $finish;\n    ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module counter_tb;

reg clk;
reg rst_n;
wire shot_o;

reg [7:0] data_in;
reg rdreq, wrreq;
reg sclr;
wire [7:0] data_out;
wire empty_flg, full_flg;
wire [3:0] data_num;

always #1 clk = ~clk;

initial begin
    $dumpfile("main.vcd");
    $dumpvars(0);
    clk = 0;
    rst_n = 0;

    data_in = 8'hAA;
    rdreq = 1'b0;
    wrreq = 1'b0;
    sclr = 1'b0;
    rst_n = 1'b0;
end

initial begin
    #1 rst_n = 0;
    #1 rst_n = 1; wrreq = 1'b1;
    #2500; $finish;
end

always@(negedge clk or negedge rst_n) begin
    if(!rst_n)  data_in <= 8'hAA;
    else if (data_in <= 8'hFF && !rdreq) data_in <= data_in + 1'b1;
end

always@(posedge full_flg or negedge rst_n) begin
    if(!rst_n) rdreq <= 1'b0;
    else if(full_flg) begin
     rdreq <= 1'b1;
     wrreq <= 1'b0;
    end
end

counter u0(
    .clk            (clk),
    .rst_n          (rst_n),
    .en             (1'b1),
    .shot_o         (shot_o)
);


fifo u1(
	.clock      (clk),
	.data       (data_in),
    .q          (data_out),
	.rdreq      (rdreq),
	.wrreq      (wrreq),
	.empty      (empty_flg),
	.full       (full_flg),
	.usedw      (data_num)
);

endmodule
module counter_tb;


reg clk;
reg rst_n;
wire shot_o;

reg [7:0] data_in;
reg rdreq, wrreq;
reg sclr;
wire [7:0] data_out;
wire empty_flg, full_flg;
wire [3:0] data_num;

always #1 clk = ~clk;

initial begin
    $dumpfile("main.vcd");
    $dumpvars(0);
    clk = 0;
    rst_n = 0;

    data_in = 8'hAA;
    rdreq = 1'b0;
    wrreq = 1'b0;
    sclr = 1'b0;
    rst_n = 1'b0;
end

initial begin
    #1 rst_n = 0;
    #1 rst_n = 1; wrreq = 1'b1;
    #2500; $finish;
end

always@(negedge clk or negedge rst_n) begin
    if(!rst_n)  data_in <= 8'hAA;
    else if (data_in <= 8'hFF && !rdreq) data_in <= data_in + 1'b1;
end

always@(posedge full_flg or negedge rst_n) begin
    if(!rst_n) rdreq <= 1'b0;
    else if(full_flg) begin
     rdreq <= 1'b1;
     wrreq <= 1'b0;
    end
end

counter u0(
    .clk            (clk),
    .rst_n          (rst_n),
    .en             (1'b1),
    .shot_o         (shot_o)
);


fifo u1(
	.clock      (clk),
	.data       (data_in),
    .q          (data_out),
	.rdreq      (rdreq),
	.wrreq      (wrreq),
	.empty      (empty_flg),
	.full       (full_flg),
	.usedw      (data_num)
);

endmodule