data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #0 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/527176783/Pipeline/test/PipelineCPU_tb.v:58: Cannot find file containing module: \'PipelineCPU\'\n    PipelineCPU PipelineCPU(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Pipeline/test,data/full_repos/permissive/527176783/PipelineCPU\n             data/full_repos/permissive/527176783/Pipeline/test,data/full_repos/permissive/527176783/PipelineCPU.v\n             data/full_repos/permissive/527176783/Pipeline/test,data/full_repos/permissive/527176783/PipelineCPU.sv\n             PipelineCPU\n             PipelineCPU.v\n             PipelineCPU.sv\n             obj_dir/PipelineCPU\n             obj_dir/PipelineCPU.v\n             obj_dir/PipelineCPU.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PipelineCPU_tb();
reg clk = 0;
reg rst_n = 1;
always begin
    #5;
    clk = ~clk;
end
initial begin
    #0 rst_n = 1;
    #5;
    rst_n = 0;
    #5;
    rst_n = 1;
end
    PipelineCPU PipelineCPU(
        .clk(clk),
        .rst_n(rst_n)
    );
endmodule
module PipelineCPU_tb();

reg clk = 0;
reg rst_n = 1;
always begin
    #5;
    clk = ~clk;
end
initial begin
    #0 rst_n = 1;
    #5;
    rst_n = 0;
    #5;
    rst_n = 1;
end
    PipelineCPU PipelineCPU(
        .clk(clk),
        .rst_n(rst_n)
    );
endmodule