data/full_repos/permissive/482720319/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482720319/test.v:10: Unsupported: Ignoring delay on this delayed statement.\n            #10 r1 <= 2\'b11;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482720319/test.v:14: Unsupported or unknown PLI call: $monitor\n            $monitor("w1 = %b r1 = %b", w1, r1);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

      wire[1:0] w1;
      reg [1:0] r1;

      assign w1 = r1;

      initial begin
            r1 <= 2'b10;
            #10 r1 <= 2'b11;
      end

      initial
            $monitor("w1 = %b r1 = %b", w1, r1);

endmodule
module tb();


      wire[1:0] w1;
      reg [1:0] r1;

      assign w1 = r1;

      initial begin
            r1 <= 2'b10;
            #10 r1 <= 2'b11;
      end

      initial
            $monitor("w1 = %b r1 = %b", w1, r1);

endmodule