data/full_repos/permissive/42434302/ivltests/memidxrng.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memidxrng.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/memidxrng.v:40: Selection index out of range: 14 outside 12:2\n                                                                              : ... In instance memidxrng\n      $display("FAILED: mem[13] = %b, expect x", mem[14]);\n                                                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/memidxrng.v:38: Selection index out of range: 13 outside 12:2\n                                                                              : ... In instance memidxrng\n if (mem[13] !== 1\'bx)\n        ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/memidxrng.v:45: Selection index out of range: 1 outside 12:2\n                                                                              : ... In instance memidxrng\n      $display("FAILED: mem[1] = %b, expect x", mem[1]);\n                                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/memidxrng.v:43: Selection index out of range: 1 outside 12:2\n                                                                              : ... In instance memidxrng\n if (mem[1] !== 1\'bx)\n        ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memidxrng;

   reg mem[12:2];

   reg [7:0] i;
   integer errs = 0;

   initial
     begin
	for (i=0; i<255; i=i+1) mem[i] <= ^i;
	#1;
	for (i=0; i<17; i=i+1)
	  $display("mem[%d] = %b \%b", i, mem[i], ^i);
	if (mem[13] !== 1'bx)
	  begin
	     $display("FAILED: mem[13] = %b, expect x", mem[14]);
	     errs = errs + 1;
	  end
	if (mem[1] !== 1'bx)
	  begin
	     $display("FAILED: mem[1] = %b, expect x", mem[1]);
	     errs = errs + 1;
	  end
	if (errs===0)
	  $display("PASSED");
	$finish;
     end

endmodule
module memidxrng;


   reg mem[12:2];

   reg [7:0] i;
   integer errs = 0;

   initial
     begin
	for (i=0; i<255; i=i+1) mem[i] <= ^i;
	#1;
	for (i=0; i<17; i=i+1)
	  $display("mem[%d] = %b \%b", i, mem[i], ^i);
	if (mem[13] !== 1'bx)
	  begin
	     $display("FAILED: mem[13] = %b, expect x", mem[14]);
	     errs = errs + 1;
	  end
	if (mem[1] !== 1'bx)
	  begin
	     $display("FAILED: mem[1] = %b, expect x", mem[1]);
	     errs = errs + 1;
	  end
	if (errs===0)
	  $display("PASSED");
	$finish;
     end

endmodule