data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_arbiter_synth.sv
1: b"%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_arbiter_synth.sv:23: Cannot find file containing module: 'stream_arbiter'\n        stream_arbiter #(\n        ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/stream_arbiter\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/stream_arbiter.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/stream_arbiter.sv\n             stream_arbiter\n             stream_arbiter.v\n             stream_arbiter.sv\n             obj_dir/stream_arbiter\n             obj_dir/stream_arbiter.v\n             obj_dir/stream_arbiter.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_arbiter_synth.sv:38: Cannot find file containing module: 'stream_arbiter'\n        stream_arbiter #(\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module stream_arbiter_synth (
    input  logic    clk_i,
    input  logic    rst_ni
);

    typedef logic data_t;
    for (genvar n = 2; n < 32; n += 3) begin : gen_n_inp
        data_t [n-1:0]  inp;
        logic  [n-1:0]  inp_valid, inp_rr_ready, inp_prio_ready;
        data_t          oup;
        logic           oup_rr_valid, oup_prio_valid, oup_ready;

        stream_arbiter #(
            .DATA_T     (data_t),
            .N_INP      (n),
            .ARBITER    ("rr")
        ) i_rr_arb (
            .clk_i,
            .rst_ni,
            .inp_data_i     (inp),
            .inp_valid_i    (inp_valid),
            .inp_ready_o    (inp_rr_ready),
            .oup_data_o     (oup),
            .oup_valid_o    (oup_rr_valid),
            .oup_ready_i    (oup_ready)
        );

        stream_arbiter #(
            .DATA_T     (data_t),
            .N_INP      (n),
            .ARBITER    ("prio")
        ) i_prio_arb (
            .clk_i,
            .rst_ni,
            .inp_data_i     (inp),
            .inp_valid_i    (inp_valid),
            .inp_ready_o    (inp_prio_ready),
            .oup_data_o     (oup),
            .oup_valid_o    (oup_prio_valid),
            .oup_ready_i    (oup_ready)
        );
    end

endmodule
module stream_arbiter_synth (
    input  logic    clk_i,
    input  logic    rst_ni
);


    typedef logic data_t;
    for (genvar n = 2; n < 32; n += 3) begin : gen_n_inp
        data_t [n-1:0]  inp;
        logic  [n-1:0]  inp_valid, inp_rr_ready, inp_prio_ready;
        data_t          oup;
        logic           oup_rr_valid, oup_prio_valid, oup_ready;

        stream_arbiter #(
            .DATA_T     (data_t),
            .N_INP      (n),
            .ARBITER    ("rr")
        ) i_rr_arb (
            .clk_i,
            .rst_ni,
            .inp_data_i     (inp),
            .inp_valid_i    (inp_valid),
            .inp_ready_o    (inp_rr_ready),
            .oup_data_o     (oup),
            .oup_valid_o    (oup_rr_valid),
            .oup_ready_i    (oup_ready)
        );

        stream_arbiter #(
            .DATA_T     (data_t),
            .N_INP      (n),
            .ARBITER    ("prio")
        ) i_prio_arb (
            .clk_i,
            .rst_ni,
            .inp_data_i     (inp),
            .inp_valid_i    (inp_valid),
            .inp_ready_o    (inp_prio_ready),
            .oup_data_o     (oup),
            .oup_valid_o    (oup_prio_valid),
            .oup_ready_i    (oup_ready)
        );
    end

endmodule