data/full_repos/permissive/427125539/verilog/rtl/SonarOnChip.v
1: b'%Error: data/full_repos/permissive/427125539/verilog/rtl/SonarOnChip.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427125539/verilog/rtl,data/full_repos/permissive/427125539/defines.v\n             data/full_repos/permissive/427125539/verilog/rtl,data/full_repos/permissive/427125539/defines.v.v\n             data/full_repos/permissive/427125539/verilog/rtl,data/full_repos/permissive/427125539/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Abs
  #(  parameter n=16)( 
  input signed  [n-1:0] data_in,
  output        [n-1:0] data_out);
	
  assign data_out = ~data_in[n-1] ? data_in : ~data_in; 

endmodule
module Abs
  #(  parameter n=16)( 
  input signed  [n-1:0] data_in,
  output        [n-1:0] data_out);

	
  assign data_out = ~data_in[n-1] ? data_in : ~data_in; 

endmodule