data/full_repos/permissive/455874613/Projects/Module03/ModePower.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455874613/Projects/Module03/ModePower.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                     : ... In instance ModePower\n     chs_power = chs_power + chs_conf[i];  \n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ModePower (
	input  [7:0] chs_conf  ,
	output reg [3:0] chs_power ,
	output reg       chs_mode
);

	integer i;

	always@(chs_conf)
	begin
		 chs_power = 0;
		 for(i=0;i<8;i=i+1)
			  chs_power = chs_power + chs_conf[i];
			  
		 if(chs_power[0])
			chs_mode = 1;
		 else
			chs_mode = 0;
	end

endmodule
module ModePower (
	input  [7:0] chs_conf  ,
	output reg [3:0] chs_power ,
	output reg       chs_mode
);


	integer i;

	always@(chs_conf)
	begin
		 chs_power = 0;
		 for(i=0;i<8;i=i+1)
			  chs_power = chs_power + chs_conf[i];
			  
		 if(chs_power[0])
			chs_mode = 1;
		 else
			chs_mode = 0;
	end

endmodule