data/full_repos/permissive/429196919/FPGA/crc4/crc4.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/crc4/crc4.v:37: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/crc4,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/crc4,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/crc4,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: Exiting due to 1 error(s)\n'
module crc4 (input serialClk,
			  input serialData,
			  input reset,
			  input enable,
			  input masterClk,
			  output reg[3:0] crc4);




	reg prevSerialClk;
	reg prevReset;
	always @ (posedge masterClk) begin
		prevSerialClk <= serialClk;
		prevReset <= reset;
	end
	`define CRC_SERIALCLK_POSEDGE (serialClk && !prevSerialClk)
	`define CRC_SERIALCLK_NEGEDGE (!prevSerialClk && prevSerialClk)
	`define CRC_RESET_POSEDGE (reset && !prevReset)
	`define CRC_RESET_NEGEDGE (!reset && prevreset)





	always @ (posedge masterClk) begin
		if(`CRC_RESET_POSEDGE)
			crc4 <= 4'b0000;
		else if(`CRC_SERIALCLK_POSEDGE) begin
			if(enable) begin
				crc4[0] <= serialData + crc4[3];
				crc4[1] <= serialData + crc4[3] + crc4[0];
				crc4[2] <= crc4[1];
				crc4[3] <= crc4[2];
			end
			else begin
				crc4[0] <= 1'b0;
				crc4[1] <= crc4[0];
				crc4[2] <= crc4[1];
				crc4[3] <= crc4[2];
			end
		end
	end

endmodule
module crc4 (input serialClk,
			  input serialData,
			  input reset,
			  input enable,
			  input masterClk,
			  output reg[3:0] crc4);





	reg prevSerialClk;
	reg prevReset;
	always @ (posedge masterClk) begin
		prevSerialClk <= serialClk;
		prevReset <= reset;
	end
	`define CRC_SERIALCLK_POSEDGE (serialClk && !prevSerialClk)
	`define CRC_SERIALCLK_NEGEDGE (!prevSerialClk && prevSerialClk)
	`define CRC_RESET_POSEDGE (reset && !prevReset)
	`define CRC_RESET_NEGEDGE (!reset && prevreset)





	always @ (posedge masterClk) begin
		if(`CRC_RESET_POSEDGE)
			crc4 <= 4'b0000;
		else if(`CRC_SERIALCLK_POSEDGE) begin
			if(enable) begin
				crc4[0] <= serialData + crc4[3];
				crc4[1] <= serialData + crc4[3] + crc4[0];
				crc4[2] <= crc4[1];
				crc4[3] <= crc4[2];
			end
			else begin
				crc4[0] <= 1'b0;
				crc4[1] <= crc4[0];
				crc4[2] <= crc4[1];
				crc4[3] <= crc4[2];
			end
		end
	end

endmodule