data/full_repos/permissive/418749135/mux.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418749135/mux.v:8: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                            : ... In instance mux_4to1_case\n     case(sel)\n     ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/418749135/mux.v:8: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                            : ... In instance mux_4to1_case\n     case(sel)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/418749135/mux.v:8: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                            : ... In instance mux_4to1_case\n     case(sel)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/418749135/mux.v:8: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                            : ... In instance mux_4to1_case\n     case(sel)\n     ^~~~\n%Error: Exiting due to 4 warning(s)\n'
module mux_4to1_case(input [3:0] a,
                     input [3:0] b,
                     input [3:0] c,
                     input [3:0] d,
                     input [3:0] sel,
                     output reg [3:0] out);
 always@ (a or b or c or d or sel)begin
     case(sel)
     2'b00 : out<=a;
     2'b01 : out<=b;
     2'b10 : out<=c;
     2'b11 : out<=d;
     endcase
 end        
endmodule
module mux_4to1_case(input [3:0] a,
                     input [3:0] b,
                     input [3:0] c,
                     input [3:0] d,
                     input [3:0] sel,
                     output reg [3:0] out);

 always@ (a or b or c or d or sel)begin
     case(sel)
     2'b00 : out<=a;
     2'b01 : out<=b;
     2'b10 : out<=c;
     2'b11 : out<=d;
     endcase
 end        
endmodule