data/full_repos/permissive/495525032/TL-Verilog/adder.v
data/verilator_xmls/8d0b74e9-fdf9-4765-aafa-132fabfa9bf7.xml
module adder(input [2:0] a, b,
             output [3:0] c);
    
    assign c = a + b;

endmodule
module adder(input [2:0] a, b,
             output [3:0] c);

    
    assign c = a + b;

endmodule