data/full_repos/permissive/514758517/logic_top.v
1: b'%Error: data/full_repos/permissive/514758517/logic_top.v:2: Cannot find include file: logical_and.v\n`include "logical_and.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logical_and.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logical_and.v.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logical_and.v.sv\n             logical_and.v\n             logical_and.v.v\n             logical_and.v.sv\n             obj_dir/logical_and.v\n             obj_dir/logical_and.v.v\n             obj_dir/logical_and.v.sv\n%Error: data/full_repos/permissive/514758517/logic_top.v:3: Cannot find include file: logical_nand.v\n`include "logical_nand.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514758517/logic_top.v:4: Cannot find include file: logical_nor.v\n`include "logical_nor.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514758517/logic_top.v:5: Cannot find include file: logical_or.v\n`include "logical_or.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module logic_top(in1 , in2 , opcode , out_logic);
	
	input signed [4:0]in1;
	input signed [4:0]in2;
	output reg signed [8:0]out_logic;
	input [2:0]opcode;
	wire [8:0]out_and , out_or , out_nand , out_nor;
	
	logical_or     u0_logical_or     (in1 , in2 , out_or);    
	logical_and    u1_logical_and    (in1 , in2 , out_and);   
	logical_nand   u2_logical_nand   (in1 , in2 , out_nand);  
	logical_nor    u3_logical_nor    (in1 , in2 , out_nor);
	
  always@(opcode , out_and , out_or , out_nand , out_nor)
		begin
			case(opcode[1:0])
				2'b00 : out_logic <= out_or;
				2'b01 : out_logic <= out_and;
				2'b10 : out_logic <= out_nand;
				2'b11 : out_logic <= out_nor;
			endcase
		end
endmodule
module logic_top(in1 , in2 , opcode , out_logic);

	
	input signed [4:0]in1;
	input signed [4:0]in2;
	output reg signed [8:0]out_logic;
	input [2:0]opcode;
	wire [8:0]out_and , out_or , out_nand , out_nor;
	
	logical_or     u0_logical_or     (in1 , in2 , out_or);    
	logical_and    u1_logical_and    (in1 , in2 , out_and);   
	logical_nand   u2_logical_nand   (in1 , in2 , out_nand);  
	logical_nor    u3_logical_nor    (in1 , in2 , out_nor);
	
  always@(opcode , out_and , out_or , out_nand , out_nor)
		begin
			case(opcode[1:0])
				2'b00 : out_logic <= out_or;
				2'b01 : out_logic <= out_and;
				2'b10 : out_logic <= out_nand;
				2'b11 : out_logic <= out_nor;
			endcase
		end
endmodule