data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:23: Cannot find include file: genericIOSateliteEnv.v\n`include "genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v.sv\n             genericIOSateliteEnv.v\n             genericIOSateliteEnv.v.v\n             genericIOSateliteEnv.v.sv\n             obj_dir/genericIOSateliteEnv.v\n             obj_dir/genericIOSateliteEnv.v.v\n             obj_dir/genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:24: Cannot find include file: pulse/pulse.v\n`include "pulse/pulse.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:25: Cannot find include file: pwm/pwm.v\n`include "pwm/pwm.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:26: Cannot find include file: latchReg/latchReg.v\n`include "latchReg/latchReg.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:27: Cannot find include file: shiftReg/shiftReg.v\n`include "shiftReg/shiftReg.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:28: Cannot find include file: ws2811Decoder/ws2811Decoder.v\n`include "ws2811Decoder/ws2811Decoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:29: Cannot find include file: ws2811Encoder/ws2811Encoder.v\n`include "ws2811Encoder/ws2811Encoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:30: Cannot find include file: crc4/crc4.v\n`include "crc4/crc4.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:75: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;\n             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;\n                                  ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`CRC_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`FEEDBACK_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`COMMAND_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`MODE_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`ACTUATOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`SENSOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:106: Define or directive not defined: \'`CRC_WD\'\n   if(rxCnt>`CRC_WD + 1\'b1) begin        \n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:110: Define or directive not defined: \'`CRC_WD\'\n   else if(rxCnt == `CRC_WD + 1\'b1) begin      \n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:115: Define or directive not defined: \'`CRC_WD\'\n   else if( rxCnt < `CRC_WD + 1\'b1 && rxCnt > 7\'b0) begin\n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`CRC_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`FEEDBACK_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`COMMAND_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`MODE_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`ACTUATOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`SENSOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`CRC_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`FEEDBACK_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`COMMAND_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`NO_ACTUATORS\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`MODE_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`NO_ACTUATORS\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`ACTUATOR_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`SENSOR_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:149: Define or directive not defined: \'`CRC_WD\'\n   if(txCnt>`CRC_WD + 1\'b1) begin        \n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:153: Define or directive not defined: \'`CRC_WD\'\n   else if(txCnt == `CRC_WD + 1\'b1 && firstSatShift) begin  \n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:158: Define or directive not defined: \'`CRC_WD\'\n   else if( txCnt < `CRC_WD + 1\'b1 && txCnt > 7\'b0) begin\n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:174: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n  else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)\n                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:174: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)\n                                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:176: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n  else if(watchdogReg>=`WATCHDOG_TIMEOUT_CYC)\n                       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:184: Define or directive not defined: \'`FEEDBACK_REMOTECRCERR\'\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b1;\n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:184: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b1;\n                                   ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:186: Define or directive not defined: \'`FEEDBACK_REMOTECRCERR\'\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b0;\n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:186: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b0;\n                                   ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module logictop(input ws2811wireIn,
	input[7:0] sensorInput,
	input masterClk,
	output[3:0] actuators,
	output ws2811wireOut,
	output wire active,
	output reg crcRxErr,
	output reg wdDisableActuators);
	wire serialDataIn;
	wire serialClk;
	reg prevSerialClk;
	reg prevActive;
	wire serialDataOut;
	reg[3:0] crcRxShift;
	reg[3:0] command;
	reg[3:0] feedback;
	reg[6:0] rxCnt;
	reg[6:0] txCnt;
	reg[7:0] addr;
	reg firstSatShift;
	wire[3:0] crcTxCalcRes;
	wire[3:0] crcRxCalcRes;
	reg freezeRxCrcCalc;
	reg freezeTxCrcCalc;
	reg crcRxReset;
	reg crcTxReset;
	reg shiftCrcTx;
	wire[3:0] rxcrcAddrHash;
	wire[3:0] txcrcAddrHash;
	wire serialAct2Sens;
	reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;
	wire[3:0] preWdActuators;
	reg cmdInverseCrc;
	reg cmdEnable;
	reg cmdWdErr;

	assign rxcrcAddrHash = addr[7:4]^addr[3:0];
	assign txcrcAddrHash[0] = addr[7]^addr[3];
	assign txcrcAddrHash[3] = addr[6]^addr[2];
	assign txcrcAddrHash[2] = addr[5]^addr[1];
	assign txcrcAddrHash[1] = addr[4]^addr[0];

	always @ (posedge masterClk) begin
		prevSerialClk <= serialClk;
		prevActive <= active;
	end
	`define SERIALCLK_POSEDGE serialClk && !prevSerialClk
	`define SERIALCLK_NEGEDGE !prevSerialClk && prevSerialClk
	`define ACTIVE_POSEDGE active && !prevActive
	`define ACTIVE_NEGEDGE !active && prevActive


	always @ (posedge masterClk) begin
		if(`ACTIVE_POSEDGE) begin


			rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			freezeRxCrcCalc <= 1'b0;
			crcRxReset <= 1'b1;
		end
		else if(`SERIALCLK_POSEDGE) begin
			if(rxCnt>`CRC_WD + 1'b1) begin
				rxCnt <= rxCnt - 1'b1;
				crcRxReset <= 0;
			end
			else if(rxCnt == `CRC_WD + 1'b1) begin
				freezeRxCrcCalc <= 1'b1;
				rxCnt <= rxCnt - 1'b1;
			end

			else if( rxCnt < `CRC_WD + 1'b1 && rxCnt > 7'b0) begin
				rxCnt <= rxCnt - 1'b1;
			end
			if(rxCnt == 7'b1) begin
				if (feedback[3])
					addr <= 8'b0000;
				else
					addr <= addr + 8'b0000001;
			end
		end

		if(rxCnt == 7'b0) begin
			if((crcRxCalcRes^rxcrcAddrHash) == crcRxShift)
				crcRxErr <= 1'b0;
			else
				crcRxErr <= 1'b1;

			rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			freezeRxCrcCalc <= 1'b0;
			crcRxReset <= 1'b1;
		end
	end


	always @ (posedge masterClk) begin
		if(`ACTIVE_POSEDGE) begin

			txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			crcTxReset <= 1'b1;
			freezeTxCrcCalc <= 1'b0;
			shiftCrcTx <= 1'b0;
			firstSatShift <= 1'b1;
		end
		else if(`SERIALCLK_POSEDGE) begin
			if(txCnt>`CRC_WD + 1'b1) begin
				txCnt <= txCnt - 1'b1;
				crcTxReset <= 1'b0;
			end
			else if(txCnt == `CRC_WD + 1'b1 && firstSatShift) begin
				txCnt <= txCnt - 1'b1;
				freezeTxCrcCalc <= 1'b1;
				shiftCrcTx <= 1'b1;
			end
			else if( txCnt < `CRC_WD + 1'b1 && txCnt > 7'b0) begin
				txCnt <= txCnt - 1'b1;
			end
		end
		else if(txCnt == 7'b0) begin
			shiftCrcTx <= 1'b0;
			firstSatShift <= 1'b0;
		end
	end


	always @ (posedge masterClk) begin
		if (`ACTIVE_POSEDGE && !crcRxErr) begin
			watchdogReg <= 0;
			wdDisableActuators <= 1'b0;
		end
		else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)
			watchdogReg <= watchdogReg + 1'b1;
		else if(watchdogReg>=`WATCHDOG_TIMEOUT_CYC)
			wdDisableActuators <= 1'b1;
	end


	always @ (posedge masterClk) begin
		if (`ACTIVE_POSEDGE) begin
			if(crcRxErr)
				feedback[`FEEDBACK_REMOTECRCERR] <= 1'b1;
			else
				feedback[`FEEDBACK_REMOTECRCERR] <= 1'b0;

			if (wdDisableActuators || cmdWdErr)
				feedback[`FEEDBACK_WDERR] <= 1'b1;			
			else
				feedback[`FEEDBACK_WDERR] <= 1'b0;
		end
		else if(`SERIALCLK_POSEDGE) begin
			crcRxShift[0] <= serialDataIn;
			crcRxShift[1] <= crcRxShift[0];
			crcRxShift[2] <= crcRxShift[1];
			crcRxShift[3] <= crcRxShift[2];
			feedback[0] <= crcRxShift[3];
			feedback[1] <= feedback[0];
			feedback[2] <= feedback[1];
			feedback[3] <= feedback[2];
			command[0] <= feedback[3];
			command[1] <= command[0];
			command[2] <= command[1];
			command[3] <= command[2];
		end
	end


	always @ (posedge masterClk) begin
		if(`ACTIVE_NEGEDGE) begin
			if (crcRxErr)
				cmdInverseCrc <= 1'b0;
			else begin
				cmdInverseCrc <= command[`COMMAND_INVCRC];
				cmdEnable <= command[`COMMAND_ENABLE];
				cmdWdErr <= command[`COMMAND_WD_ERR];
			end
		end
	end


	ws2811Decoder ws2811Decoder_0(.masterClk (masterClk), .dataIn (ws2811wireIn), .dataOut (serialDataIn), .dataClk (serialClk), .active (active));
	crc4 crcRxCalc(.serialData(serialDataIn), .serialClk(serialClk & ~freezeRxCrcCalc), .reset(crcRxReset), .enable(1'b1), .masterClk(masterClk), .crc4(crcRxCalcRes));
	actuators actuators_0(.serialDataIn (command[3]), .serialClk (serialClk), .enableShift (active), .masterClk (masterClk), .disableActuators(crcRxErr), .actuator (preWdActuators), .serialDataOut(serialAct2Sens));
	sensors sensors_0(.serialDataIn (serialAct2Sens), .serialClk (serialClk), .enableShift (active), .sense (sensorInput), .masterClk (masterClk), .serialDataOut (serialDataOut));
	crc4 crcTxCalc(.serialData(serialDataOut), .serialClk(serialClk), .reset(crcRxReset), .enable(~freezeTxCrcCalc), .masterClk(masterClk), .crc4(crcTxCalcRes));
	ws2811Encoder ws2811Encoder_0(.dataIn ((~shiftCrcTx | ~firstSatShift) & serialDataOut | (shiftCrcTx & firstSatShift) & (crcTxCalcRes[3]^cmdInverseCrc^txcrcAddrHash[txCnt[1:0]])), .dataClk (serialClk), .masterClk (masterClk), .dataOut (ws2811wireOut));
	assign actuators = {preWdActuators[3] & ~wdDisableActuators & cmdEnable, preWdActuators[2] & ~wdDisableActuators & cmdEnable, preWdActuators[1] & ~wdDisableActuators & cmdEnable, preWdActuators[0] & ~wdDisableActuators & cmdEnable};
endmodule
module logictop(input ws2811wireIn,
	input[7:0] sensorInput,
	input masterClk,
	output[3:0] actuators,
	output ws2811wireOut,
	output wire active,
	output reg crcRxErr,
	output reg wdDisableActuators);

	wire serialDataIn;
	wire serialClk;
	reg prevSerialClk;
	reg prevActive;
	wire serialDataOut;
	reg[3:0] crcRxShift;
	reg[3:0] command;
	reg[3:0] feedback;
	reg[6:0] rxCnt;
	reg[6:0] txCnt;
	reg[7:0] addr;
	reg firstSatShift;
	wire[3:0] crcTxCalcRes;
	wire[3:0] crcRxCalcRes;
	reg freezeRxCrcCalc;
	reg freezeTxCrcCalc;
	reg crcRxReset;
	reg crcTxReset;
	reg shiftCrcTx;
	wire[3:0] rxcrcAddrHash;
	wire[3:0] txcrcAddrHash;
	wire serialAct2Sens;
	reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;
	wire[3:0] preWdActuators;
	reg cmdInverseCrc;
	reg cmdEnable;
	reg cmdWdErr;

	assign rxcrcAddrHash = addr[7:4]^addr[3:0];
	assign txcrcAddrHash[0] = addr[7]^addr[3];
	assign txcrcAddrHash[3] = addr[6]^addr[2];
	assign txcrcAddrHash[2] = addr[5]^addr[1];
	assign txcrcAddrHash[1] = addr[4]^addr[0];

	always @ (posedge masterClk) begin
		prevSerialClk <= serialClk;
		prevActive <= active;
	end
	`define SERIALCLK_POSEDGE serialClk && !prevSerialClk
	`define SERIALCLK_NEGEDGE !prevSerialClk && prevSerialClk
	`define ACTIVE_POSEDGE active && !prevActive
	`define ACTIVE_NEGEDGE !active && prevActive


	always @ (posedge masterClk) begin
		if(`ACTIVE_POSEDGE) begin


			rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			freezeRxCrcCalc <= 1'b0;
			crcRxReset <= 1'b1;
		end
		else if(`SERIALCLK_POSEDGE) begin
			if(rxCnt>`CRC_WD + 1'b1) begin
				rxCnt <= rxCnt - 1'b1;
				crcRxReset <= 0;
			end
			else if(rxCnt == `CRC_WD + 1'b1) begin
				freezeRxCrcCalc <= 1'b1;
				rxCnt <= rxCnt - 1'b1;
			end

			else if( rxCnt < `CRC_WD + 1'b1 && rxCnt > 7'b0) begin
				rxCnt <= rxCnt - 1'b1;
			end
			if(rxCnt == 7'b1) begin
				if (feedback[3])
					addr <= 8'b0000;
				else
					addr <= addr + 8'b0000001;
			end
		end

		if(rxCnt == 7'b0) begin
			if((crcRxCalcRes^rxcrcAddrHash) == crcRxShift)
				crcRxErr <= 1'b0;
			else
				crcRxErr <= 1'b1;

			rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			freezeRxCrcCalc <= 1'b0;
			crcRxReset <= 1'b1;
		end
	end


	always @ (posedge masterClk) begin
		if(`ACTIVE_POSEDGE) begin

			txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;
			crcTxReset <= 1'b1;
			freezeTxCrcCalc <= 1'b0;
			shiftCrcTx <= 1'b0;
			firstSatShift <= 1'b1;
		end
		else if(`SERIALCLK_POSEDGE) begin
			if(txCnt>`CRC_WD + 1'b1) begin
				txCnt <= txCnt - 1'b1;
				crcTxReset <= 1'b0;
			end
			else if(txCnt == `CRC_WD + 1'b1 && firstSatShift) begin
				txCnt <= txCnt - 1'b1;
				freezeTxCrcCalc <= 1'b1;
				shiftCrcTx <= 1'b1;
			end
			else if( txCnt < `CRC_WD + 1'b1 && txCnt > 7'b0) begin
				txCnt <= txCnt - 1'b1;
			end
		end
		else if(txCnt == 7'b0) begin
			shiftCrcTx <= 1'b0;
			firstSatShift <= 1'b0;
		end
	end


	always @ (posedge masterClk) begin
		if (`ACTIVE_POSEDGE && !crcRxErr) begin
			watchdogReg <= 0;
			wdDisableActuators <= 1'b0;
		end
		else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)
			watchdogReg <= watchdogReg + 1'b1;
		else if(watchdogReg>=`WATCHDOG_TIMEOUT_CYC)
			wdDisableActuators <= 1'b1;
	end


	always @ (posedge masterClk) begin
		if (`ACTIVE_POSEDGE) begin
			if(crcRxErr)
				feedback[`FEEDBACK_REMOTECRCERR] <= 1'b1;
			else
				feedback[`FEEDBACK_REMOTECRCERR] <= 1'b0;

			if (wdDisableActuators || cmdWdErr)
				feedback[`FEEDBACK_WDERR] <= 1'b1;			
			else
				feedback[`FEEDBACK_WDERR] <= 1'b0;
		end
		else if(`SERIALCLK_POSEDGE) begin
			crcRxShift[0] <= serialDataIn;
			crcRxShift[1] <= crcRxShift[0];
			crcRxShift[2] <= crcRxShift[1];
			crcRxShift[3] <= crcRxShift[2];
			feedback[0] <= crcRxShift[3];
			feedback[1] <= feedback[0];
			feedback[2] <= feedback[1];
			feedback[3] <= feedback[2];
			command[0] <= feedback[3];
			command[1] <= command[0];
			command[2] <= command[1];
			command[3] <= command[2];
		end
	end


	always @ (posedge masterClk) begin
		if(`ACTIVE_NEGEDGE) begin
			if (crcRxErr)
				cmdInverseCrc <= 1'b0;
			else begin
				cmdInverseCrc <= command[`COMMAND_INVCRC];
				cmdEnable <= command[`COMMAND_ENABLE];
				cmdWdErr <= command[`COMMAND_WD_ERR];
			end
		end
	end


	ws2811Decoder ws2811Decoder_0(.masterClk (masterClk), .dataIn (ws2811wireIn), .dataOut (serialDataIn), .dataClk (serialClk), .active (active));
	crc4 crcRxCalc(.serialData(serialDataIn), .serialClk(serialClk & ~freezeRxCrcCalc), .reset(crcRxReset), .enable(1'b1), .masterClk(masterClk), .crc4(crcRxCalcRes));
	actuators actuators_0(.serialDataIn (command[3]), .serialClk (serialClk), .enableShift (active), .masterClk (masterClk), .disableActuators(crcRxErr), .actuator (preWdActuators), .serialDataOut(serialAct2Sens));
	sensors sensors_0(.serialDataIn (serialAct2Sens), .serialClk (serialClk), .enableShift (active), .sense (sensorInput), .masterClk (masterClk), .serialDataOut (serialDataOut));
	crc4 crcTxCalc(.serialData(serialDataOut), .serialClk(serialClk), .reset(crcRxReset), .enable(~freezeTxCrcCalc), .masterClk(masterClk), .crc4(crcTxCalcRes));
	ws2811Encoder ws2811Encoder_0(.dataIn ((~shiftCrcTx | ~firstSatShift) & serialDataOut | (shiftCrcTx & firstSatShift) & (crcTxCalcRes[3]^cmdInverseCrc^txcrcAddrHash[txCnt[1:0]])), .dataClk (serialClk), .masterClk (masterClk), .dataOut (ws2811wireOut));
	assign actuators = {preWdActuators[3] & ~wdDisableActuators & cmdEnable, preWdActuators[2] & ~wdDisableActuators & cmdEnable, preWdActuators[1] & ~wdDisableActuators & cmdEnable, preWdActuators[0] & ~wdDisableActuators & cmdEnable};
endmodule