data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bcd_to_7seg.v
data/verilator_xmls/c76d97af-250d-40e0-bf8e-63c4778afbd7.xml
module bcd_to_7seg(BCD, pattern);
output reg [6:0] pattern; 
input wire [3:0] BCD; 
always @ (BCD) 
begin
case (BCD)
	4'b0000: pattern = 7'b000_1000;
	4'b0001: pattern = 7'b110_1101;
	4'b0010: pattern = 7'b010_0010;
	4'b0011: pattern = 7'b010_0100;
	4'b0100: pattern = 7'b100_0101;
	4'b0101: pattern = 7'b001_0100;
	4'b0110: pattern = 7'b001_0000;
	4'b0111: pattern = 7'b010_1101;
	4'b1000: pattern = 7'b000_0000;
	4'b1001: pattern = 7'b000_0100;
	default: pattern = 7'b111_1111;
endcase
end
endmodule
module bcd_to_7seg(BCD, pattern);

output reg [6:0] pattern; 
input wire [3:0] BCD; 
always @ (BCD) 
begin
case (BCD)
	4'b0000: pattern = 7'b000_1000;
	4'b0001: pattern = 7'b110_1101;
	4'b0010: pattern = 7'b010_0010;
	4'b0011: pattern = 7'b010_0100;
	4'b0100: pattern = 7'b100_0101;
	4'b0101: pattern = 7'b001_0100;
	4'b0110: pattern = 7'b001_0000;
	4'b0111: pattern = 7'b010_1101;
	4'b1000: pattern = 7'b000_0000;
	4'b1001: pattern = 7'b000_0100;
	default: pattern = 7'b111_1111;
endcase
end
endmodule