data/full_repos/permissive/426889244/verilog/GPRByPassProc.v
data/verilator_xmls/3bae5e47-4028-47d9-a3c2-e0bc065339c4.xml
module GPRByPassProc(
    input wire[4:0] EXE_waddr,
    input wire[31:0] EXE_wdata,
    input wire EXE_we,

    input wire[4:0] rs_addr,
    input wire[31:0] rs_data,

    input wire[4:0] rt_addr,
    input wire[31:0] rt_data,

    output wire[31:0] rs_valid_data,
    output wire[31:0] rt_valid_data
);

    assign rs_valid_data = (EXE_we & (rs_addr != 0) & (rs_addr == EXE_waddr)) ? EXE_wdata : rs_data;
    assign rt_valid_data = (EXE_we & (rt_addr != 0) & (rt_addr == EXE_waddr)) ? EXE_wdata : rt_data;
endmodule
module GPRByPassProc(
    input wire[4:0] EXE_waddr,
    input wire[31:0] EXE_wdata,
    input wire EXE_we,

    input wire[4:0] rs_addr,
    input wire[31:0] rs_data,

    input wire[4:0] rt_addr,
    input wire[31:0] rt_data,

    output wire[31:0] rs_valid_data,
    output wire[31:0] rt_valid_data
);


    assign rs_valid_data = (EXE_we & (rs_addr != 0) & (rs_addr == EXE_waddr)) ? EXE_wdata : rs_data;
    assign rt_valid_data = (EXE_we & (rt_addr != 0) & (rt_addr == EXE_waddr)) ? EXE_wdata : rt_data;
endmodule