data/full_repos/permissive/482719158/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/482719158/verilog/rtl/user_project_wrapper.v:58: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/user_project_wrapper.v:59: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/user_project_wrapper.v:60: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,

    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);






    assign wbs_ack_o = 1'b0;
    assign wbs_dat_o = 32'b0;
    assign la_data_out = 128'b0;
    assign user_irq = 3'b0;

    wire clk;


    wire ext_clk;
    wire ext_rst_n;
    wire alt_reset;
    wire jtag_tck;
    wire jtag_tdi;
    wire jtag_tdo;
    wire jtag_tms;
    wire jtag_trst;
    wire spi_flash_clk;
    wire spi_flash_cs_n;
    wire [3:0] spi_flash_i;
    wire [3:0] spi_flash_o;
    wire [3:0] spi_flash_oe;
    wire uart0_rxd;
    wire uart0_txd;

    wire simplebus_clk;
    wire [7:0] simplebus_bus_out;
    wire simplebus_parity_out;
    wire [7:0] simplebus_bus_in;
    wire simplebus_parity_in;

    wire [31:0] gpio_in;
    wire [31:0] gpio_out;
    wire [31:0] gpio_dir;

    wire simplebus_irq;

    wire simplebus_enabled;


    assign spi_flash_i[0] = 0;
    assign spi_flash_i[2] = 0;
    assign spi_flash_i[3] = 0;


    assign gpio_in[31:21] = 11'b0;


    assign jtag_trst = ~ext_rst_n;

    assign clk = user_clock2;


    assign ext_clk = clk;


    assign gpio_in[20] = io_in[0];
    assign io_out[0] = gpio_out[20];
    assign io_oeb[0] = ~gpio_dir[20];


    assign io_out[4:1] = 4'b0;
    assign io_oeb[4:1] = 4'b0;


    assign uart0_rxd = io_in[5];
    assign io_out[5] = 0;
    assign io_oeb[5] = 1;

    assign io_out[6] = uart0_txd;

    assign io_oeb[6] = 0;


    assign ext_rst_n = ~io_in[7];
    assign io_out[7] = 0;
    assign io_oeb[7] = 1;


    assign io_out[8] = spi_flash_cs_n;
    assign io_oeb[8] = 0;

    assign io_out[9] = spi_flash_clk;
    assign io_oeb[9] = 0;

    assign io_out[10] = spi_flash_o[0];
    assign io_oeb[10] = 0;

    assign spi_flash_i[1] = io_in[11];
    assign io_out[11] = 0;
    assign io_oeb[11] = 1;


    assign io_out[12] = jtag_tdo;
    assign io_oeb[12] = 0;

    assign jtag_tms = io_in[13];
    assign io_out[13] = 0;
    assign io_oeb[13] = 1;

    assign jtag_tck = io_in[14];
    assign io_out[14] = 0;
    assign io_oeb[14] = 1;

    assign jtag_tdi = io_in[15];
    assign io_out[15] = 0;
    assign io_oeb[15] = 1;




    assign gpio_in[18:0] = io_in[34:16];
    assign simplebus_bus_in = io_in[33:26];
    assign simplebus_parity_in = io_in[34];


    reg [18:0] muxed_io_oeb;
    reg [18:0] muxed_io_out;

    assign io_oeb[34:16] = muxed_io_oeb;
    assign io_out[34:16] = muxed_io_out;

    always @*
    begin
        if (simplebus_enabled == 0) begin
           muxed_io_oeb = ~gpio_dir[18:0];
           muxed_io_out = gpio_out[18:0];
        end else begin
            muxed_io_oeb[9:0] = 10'b0;
            muxed_io_out[0] = simplebus_clk;
            muxed_io_out[8:1] = simplebus_bus_out;
            muxed_io_out[9] = simplebus_parity_out;

            muxed_io_oeb[18:10] = {9{1'b1}};
            muxed_io_out[18:10] = 0;
        end
    end


    assign alt_reset = io_in[35];
    assign io_out[35] = 0;
    assign io_oeb[35] = 1;


    assign simplebus_irq = io_in[36];
    assign io_out[36] = 0;
    assign io_oeb[36] = 1;


    assign gpio_in[19] = io_in[37];
    assign io_out[37] = gpio_out[19];
    assign io_oeb[37] = ~gpio_dir[19];

    microwatt microwatt_0(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif
        .ext_clk(ext_clk),
        .ext_rst(ext_rst_n),
        .alt_reset(alt_reset),
        .uart0_rxd(uart0_rxd),
        .uart0_txd(uart0_txd),
        .jtag_tck(jtag_tck),
        .jtag_tdi(jtag_tdi),
        .jtag_tms(jtag_tms),
        .jtag_trst(jtag_trst),
        .jtag_tdo(jtag_tdo),
        .spi_flash_cs_n(spi_flash_cs_n),
        .spi_flash_clk(spi_flash_clk),
        .spi_flash_sdat_o(spi_flash_o),
        .spi_flash_sdat_i(spi_flash_i),
        .spi_flash_sdat_oe(spi_flash_oe),
        .simplebus_clk(simplebus_clk),
        .simplebus_bus_out(simplebus_bus_out),
        .simplebus_parity_out(simplebus_parity_out),
        .simplebus_bus_in(simplebus_bus_in),
        .simplebus_parity_in(simplebus_parity_in),
        .simplebus_enabled(simplebus_enabled),
        .simplebus_irq(simplebus_irq),
        .gpio_in(gpio_in),
        .gpio_out(gpio_out),
        .gpio_dir(gpio_dir)
    );
endmodule
module user_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,

    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);







    assign wbs_ack_o = 1'b0;
    assign wbs_dat_o = 32'b0;
    assign la_data_out = 128'b0;
    assign user_irq = 3'b0;

    wire clk;


    wire ext_clk;
    wire ext_rst_n;
    wire alt_reset;
    wire jtag_tck;
    wire jtag_tdi;
    wire jtag_tdo;
    wire jtag_tms;
    wire jtag_trst;
    wire spi_flash_clk;
    wire spi_flash_cs_n;
    wire [3:0] spi_flash_i;
    wire [3:0] spi_flash_o;
    wire [3:0] spi_flash_oe;
    wire uart0_rxd;
    wire uart0_txd;

    wire simplebus_clk;
    wire [7:0] simplebus_bus_out;
    wire simplebus_parity_out;
    wire [7:0] simplebus_bus_in;
    wire simplebus_parity_in;

    wire [31:0] gpio_in;
    wire [31:0] gpio_out;
    wire [31:0] gpio_dir;

    wire simplebus_irq;

    wire simplebus_enabled;


    assign spi_flash_i[0] = 0;
    assign spi_flash_i[2] = 0;
    assign spi_flash_i[3] = 0;


    assign gpio_in[31:21] = 11'b0;


    assign jtag_trst = ~ext_rst_n;

    assign clk = user_clock2;


    assign ext_clk = clk;


    assign gpio_in[20] = io_in[0];
    assign io_out[0] = gpio_out[20];
    assign io_oeb[0] = ~gpio_dir[20];


    assign io_out[4:1] = 4'b0;
    assign io_oeb[4:1] = 4'b0;


    assign uart0_rxd = io_in[5];
    assign io_out[5] = 0;
    assign io_oeb[5] = 1;

    assign io_out[6] = uart0_txd;

    assign io_oeb[6] = 0;


    assign ext_rst_n = ~io_in[7];
    assign io_out[7] = 0;
    assign io_oeb[7] = 1;


    assign io_out[8] = spi_flash_cs_n;
    assign io_oeb[8] = 0;

    assign io_out[9] = spi_flash_clk;
    assign io_oeb[9] = 0;

    assign io_out[10] = spi_flash_o[0];
    assign io_oeb[10] = 0;

    assign spi_flash_i[1] = io_in[11];
    assign io_out[11] = 0;
    assign io_oeb[11] = 1;


    assign io_out[12] = jtag_tdo;
    assign io_oeb[12] = 0;

    assign jtag_tms = io_in[13];
    assign io_out[13] = 0;
    assign io_oeb[13] = 1;

    assign jtag_tck = io_in[14];
    assign io_out[14] = 0;
    assign io_oeb[14] = 1;

    assign jtag_tdi = io_in[15];
    assign io_out[15] = 0;
    assign io_oeb[15] = 1;




    assign gpio_in[18:0] = io_in[34:16];
    assign simplebus_bus_in = io_in[33:26];
    assign simplebus_parity_in = io_in[34];


    reg [18:0] muxed_io_oeb;
    reg [18:0] muxed_io_out;

    assign io_oeb[34:16] = muxed_io_oeb;
    assign io_out[34:16] = muxed_io_out;

    always @*
    begin
        if (simplebus_enabled == 0) begin
           muxed_io_oeb = ~gpio_dir[18:0];
           muxed_io_out = gpio_out[18:0];
        end else begin
            muxed_io_oeb[9:0] = 10'b0;
            muxed_io_out[0] = simplebus_clk;
            muxed_io_out[8:1] = simplebus_bus_out;
            muxed_io_out[9] = simplebus_parity_out;

            muxed_io_oeb[18:10] = {9{1'b1}};
            muxed_io_out[18:10] = 0;
        end
    end


    assign alt_reset = io_in[35];
    assign io_out[35] = 0;
    assign io_oeb[35] = 1;


    assign simplebus_irq = io_in[36];
    assign io_out[36] = 0;
    assign io_oeb[36] = 1;


    assign gpio_in[19] = io_in[37];
    assign io_out[37] = gpio_out[19];
    assign io_oeb[37] = ~gpio_dir[19];

    microwatt microwatt_0(
    `ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
    `endif
        .ext_clk(ext_clk),
        .ext_rst(ext_rst_n),
        .alt_reset(alt_reset),
        .uart0_rxd(uart0_rxd),
        .uart0_txd(uart0_txd),
        .jtag_tck(jtag_tck),
        .jtag_tdi(jtag_tdi),
        .jtag_tms(jtag_tms),
        .jtag_trst(jtag_trst),
        .jtag_tdo(jtag_tdo),
        .spi_flash_cs_n(spi_flash_cs_n),
        .spi_flash_clk(spi_flash_clk),
        .spi_flash_sdat_o(spi_flash_o),
        .spi_flash_sdat_i(spi_flash_i),
        .spi_flash_sdat_oe(spi_flash_oe),
        .simplebus_clk(simplebus_clk),
        .simplebus_bus_out(simplebus_bus_out),
        .simplebus_parity_out(simplebus_parity_out),
        .simplebus_bus_in(simplebus_bus_in),
        .simplebus_parity_in(simplebus_parity_in),
        .simplebus_enabled(simplebus_enabled),
        .simplebus_irq(simplebus_irq),
        .gpio_in(gpio_in),
        .gpio_out(gpio_out),
        .gpio_dir(gpio_dir)
    );
endmodule