data/full_repos/permissive/440792992/hardware/dataMEM.v
1: b'%Error: data/full_repos/permissive/440792992/hardware/dataMEM.v:8: Cannot find include file: cofigure.h\n`include "cofigure.h" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/cofigure.h\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/cofigure.h.v\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/cofigure.h.sv\n             cofigure.h\n             cofigure.h.v\n             cofigure.h.sv\n             obj_dir/cofigure.h\n             obj_dir/cofigure.h.v\n             obj_dir/cofigure.h.sv\n%Error: data/full_repos/permissive/440792992/hardware/dataMEM.v:16: Define or directive not defined: \'`DMEM_ADDRW\'\n    input      [`DMEM_ADDRW-1:0] addr,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/dataMEM.v:22: Define or directive not defined: \'`DMEM_DEPTH\'\n    reg [31:0] datamem [0:`DMEM_DEPTH-1];\n                          ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module dataMEM
(
    input                              i_clk,
    input                              i_resetn,
    input                              valid,
    input                              we,
    input      [`DMEM_ADDRW-1:0] addr,
    input      [31:0]             wdata,
    output                             ready,
    output reg [31:0]             rdata
);

    reg [31:0] datamem [0:`DMEM_DEPTH-1];
    
    initial begin
        if (DATA_MEM_INIT_FILE != "") begin
            $display("Preloading instruction memory data from %s", DATA_MEM_INIT_FILE);
            $readmemh(DATA_MEM_INIT_FILE, datamem);
        end
    end    
    
    reg wr_ready;
    assign ready = valid && wr_ready;
    
    always @(posedge i_clk or negedge i_resetn) begin
        if(~i_resetn) begin
            ready <= 1'b0;
            rdata <= 32'b0;
        end else begin
            if(valid) begin
                if(we) begin
                    wr_ready      <= 1'b1;
                    rdata         <= 32'b0;
                    datamem[addr] <= wdata;                    
                end else begin
                    wr_ready      <= 1'b1;
                    rdata         <= datamem[addr];
                end
            end else begin
                wr_ready  <= 1'b0;
            end
        end
   end
endmodule
module dataMEM
(
    input                              i_clk,
    input                              i_resetn,
    input                              valid,
    input                              we,
    input      [`DMEM_ADDRW-1:0] addr,
    input      [31:0]             wdata,
    output                             ready,
    output reg [31:0]             rdata
);


    reg [31:0] datamem [0:`DMEM_DEPTH-1];
    
    initial begin
        if (DATA_MEM_INIT_FILE != "") begin
            $display("Preloading instruction memory data from %s", DATA_MEM_INIT_FILE);
            $readmemh(DATA_MEM_INIT_FILE, datamem);
        end
    end    
    
    reg wr_ready;
    assign ready = valid && wr_ready;
    
    always @(posedge i_clk or negedge i_resetn) begin
        if(~i_resetn) begin
            ready <= 1'b0;
            rdata <= 32'b0;
        end else begin
            if(valid) begin
                if(we) begin
                    wr_ready      <= 1'b1;
                    rdata         <= 32'b0;
                    datamem[addr] <= wdata;                    
                end else begin
                    wr_ready      <= 1'b1;
                    rdata         <= datamem[addr];
                end
            end else begin
                wr_ready  <= 1'b0;
            end
        end
   end
endmodule