data/full_repos/permissive/418119645/my_vga_clk_generator.v
1: b'%Error: data/full_repos/permissive/418119645/my_vga_clk_generator.v:20: Cannot find include file: my_vga_clk_generator.vh\n`include "my_vga_clk_generator.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418119645,data/full_repos/permissive/418119645/my_vga_clk_generator.vh\n             data/full_repos/permissive/418119645,data/full_repos/permissive/418119645/my_vga_clk_generator.vh.v\n             data/full_repos/permissive/418119645,data/full_repos/permissive/418119645/my_vga_clk_generator.vh.sv\n             my_vga_clk_generator.vh\n             my_vga_clk_generator.vh.v\n             my_vga_clk_generator.vh.sv\n             obj_dir/my_vga_clk_generator.vh\n             obj_dir/my_vga_clk_generator.vh.v\n             obj_dir/my_vga_clk_generator.vh.sv\n%Error: data/full_repos/permissive/418119645/my_vga_clk_generator.v:22: Define or directive not defined: \'`MY_VGA_DEFAULT_PARAMS\'\nmodule my_vga_clk_generator #( `MY_VGA_DEFAULT_PARAMS ) (\n                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418119645/my_vga_clk_generator.v:32: Define or directive not defined: \'`MY_VGA_DECLS\'\n`MY_VGA_DECLS\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module my_vga_clk_generator #( `MY_VGA_DEFAULT_PARAMS ) (
           input pclk,
           output out_hsync,
           output out_vsync,
           output out_blank,
           output reg [10:0] out_hcnt,
           output reg [10:0] out_vcnt,
           input reset_n
       );

`MY_VGA_DECLS




    wire locked;

assign out_vsync = ((out_vcnt >= (VACTIVE + VFP -1)) && (out_vcnt < (VACTIVE + VFP + VSLEN))) ^ ~VPOL;
assign out_hsync = ((out_hcnt >= (HACTIVE + HFP -1)) && (out_hcnt < (HACTIVE + HFP + HSLEN))) ^ ~HPOL;
assign out_blank = (out_hcnt >= HACTIVE) || (out_vcnt >= VACTIVE);

wire hcycle = out_hcnt == (HTOTAL -1) || ~reset_n;
wire vcycle = out_vcnt == (VTOTAL -1) || ~reset_n;

always @(posedge pclk) out_hcnt <= hcycle ? 0 : out_hcnt + 1;

always @(posedge pclk) begin
    if (hcycle) out_vcnt <= vcycle ? 0 : out_vcnt + 1;
end

endmodule
module my_vga_clk_generator #( `MY_VGA_DEFAULT_PARAMS ) (
           input pclk,
           output out_hsync,
           output out_vsync,
           output out_blank,
           output reg [10:0] out_hcnt,
           output reg [10:0] out_vcnt,
           input reset_n
       );


`MY_VGA_DECLS




    wire locked;

assign out_vsync = ((out_vcnt >= (VACTIVE + VFP -1)) && (out_vcnt < (VACTIVE + VFP + VSLEN))) ^ ~VPOL;
assign out_hsync = ((out_hcnt >= (HACTIVE + HFP -1)) && (out_hcnt < (HACTIVE + HFP + HSLEN))) ^ ~HPOL;
assign out_blank = (out_hcnt >= HACTIVE) || (out_vcnt >= VACTIVE);

wire hcycle = out_hcnt == (HTOTAL -1) || ~reset_n;
wire vcycle = out_vcnt == (VTOTAL -1) || ~reset_n;

always @(posedge pclk) out_hcnt <= hcycle ? 0 : out_hcnt + 1;

always @(posedge pclk) begin
    if (hcycle) out_vcnt <= vcycle ? 0 : out_vcnt + 1;
end

endmodule