data/full_repos/permissive/451961217/morse_decoder.v
data/verilator_xmls/3f3bffb6-24f8-4fb7-b4d4-ceb50a066a63.xml
module RateDivider(d,ParLoad,Clearb,Enable,clock);
	
	output Enable;
	input [27:0]d;
	input Clearb, clock, ParLoad;
	reg[27:0] q;
	
	always@(posedge clock, negedge Clearb)
	begin
		if(Clearb==1'b0)
			q <= 28'b0000000000000000000000000000;
		else if(ParLoad  ==  1'b1)
			q <= d;
		else
			q <= q - 1;
	end 
	assign Enable=(q[27:0]==28'b0000000000000000000000000000)?1:0;
endmodule
module RateDivider(d,ParLoad,Clearb,Enable,clock);

	
	output Enable;
	input [27:0]d;
	input Clearb, clock, ParLoad;
	reg[27:0] q;
	
	always@(posedge clock, negedge Clearb)
	begin
		if(Clearb==1'b0)
			q <= 28'b0000000000000000000000000000;
		else if(ParLoad  ==  1'b1)
			q <= d;
		else
			q <= q - 1;
	end 
	assign Enable=(q[27:0]==28'b0000000000000000000000000000)?1:0;
endmodule