data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:36: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:59: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n   parameter connectivity = `CONNECTIVITY_LINE;\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter connectivity = `CONNECTIVITY_LINE;\n                                              ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:62: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:65: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:67: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:88: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:97: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:97: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:98: Define or directive not defined: \'`CONNECTIVITY_RING\'\n (connectivity == `CONNECTIVITY_RING)) ?\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:100: Define or directive not defined: \'`CONNECTIVITY_FULL\'\n       (connectivity == `CONNECTIVITY_FULL) ?\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:151: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n `ROUTING_TYPE_PHASED_DOR:\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:151: syntax error, unexpected \':\', expecting endcase\n `ROUTING_TYPE_PHASED_DOR:\n                         ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:208: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n    `DIM_ORDER_ASCENDING:\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:208: syntax error, unexpected \':\', expecting endcase\n    `DIM_ORDER_ASCENDING:\n                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:216: Define or directive not defined: \'`DIM_ORDER_DESCENDING\'\n    `DIM_ORDER_DESCENDING:\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:217: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:225: Define or directive not defined: \'`DIM_ORDER_BY_CLASS\'\n    `DIM_ORDER_BY_CLASS:\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:226: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:265: syntax error, unexpected endcase\n         endcase\n         ^~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:271: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n    `CONNECTIVITY_LINE:\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:271: syntax error, unexpected \':\', expecting endcase\n    `CONNECTIVITY_LINE:\n                      ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:278: Define or directive not defined: \'`CONNECTIVITY_RING\'\n    `CONNECTIVITY_RING:\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:279: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:326: Define or directive not defined: \'`CONNECTIVITY_FULL\'\n    `CONNECTIVITY_FULL:\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:327: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:368: syntax error, unexpected endcase\n         endcase\n         ^~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:382: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:388: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:404: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_routing_logic.v:441: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n'
module rtr_routing_logic
  (router_address, sel_mc, sel_irc, dest_info, route_op, route_orc);
   
`include "c_functions.v"
`include "c_constants.v"
   
   



   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   parameter num_routers_per_dim = 4;
   

   parameter num_dimensions = 2;
   

   parameter num_nodes_per_router = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam message_class_idx_width = clogb(num_message_classes);
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam num_network_ports = num_ports - num_nodes_per_router;
   
   



   

   input [0:router_addr_width-1] router_address;
   

   input [0:num_message_classes-1] sel_mc;
   

   input [0:num_resource_classes-1] sel_irc;
   

   input [0:dest_info_width-1]     dest_info;
   

   output [0:num_ports-1] 	    route_op;
   wire [0:num_ports-1] 	    route_op;
   

   output [0:num_resource_classes-1] route_orc;
   wire [0:num_resource_classes-1]   route_orc;
   
   



   
   wire [0:num_network_ports-1]      route_onp;
   assign route_op[0:num_network_ports-1] = route_onp;
   
   wire [0:num_resource_classes*num_network_ports-1] route_orc_onp;
   wire 					     eject;
   
   generate
      
      case(routing_type)
	
	`ROUTING_TYPE_PHASED_DOR:
	  begin
	     

	     wire [0:num_resource_classes*
		   router_addr_width-1] dest_router_addr_irc;
	     assign dest_router_addr_irc
	       = dest_info[0:num_resource_classes*router_addr_width-1];
	     
	     wire [0:num_resource_classes-1] reached_dest_irc;
	     
	     genvar 			     irc;
	     
	     for(irc = 0; irc < num_resource_classes; irc = irc + 1)
	       begin:ircs
		  

		  wire [0:router_addr_width-1] dest_router_addr;
		  assign dest_router_addr
		    = dest_router_addr_irc[irc*router_addr_width:
					   (irc+1)*router_addr_width-1];
		  
		  wire [0:num_network_ports-1] route_onp;
		  
		  wire [0:num_dimensions-1]    addr_match_d;
		  
		  genvar 		       dim;
		  
		  for(dim = 0; dim < num_dimensions; dim = dim + 1)
		    begin:dims
		       
		       wire [0:dim_addr_width-1] dest_dim_addr;
		       assign dest_dim_addr
			 = dest_router_addr[dim*dim_addr_width:
					    (dim+1)*dim_addr_width-1];
		       
		       wire [0:dim_addr_width-1] curr_dim_addr;
		       assign curr_dim_addr
			 = router_address[dim*dim_addr_width:
					  (dim+1)*dim_addr_width-1];
		       
		       wire 			 dest_lt_curr;
		       wire [0:dim_addr_width-1] dest_minus_curr;
		       assign {dest_lt_curr, dest_minus_curr}
			 = dest_dim_addr - curr_dim_addr;
		       
		       wire 			 curr_lt_dest;
		       wire [0:dim_addr_width-1] curr_minus_dest;
		       assign {curr_lt_dest, curr_minus_dest}
			 = curr_dim_addr - dest_dim_addr;
		       
		       assign addr_match_d[dim] = ~dest_lt_curr & ~curr_lt_dest;
		       
		       wire 			 dim_sel;
		       
		       case(dim_order)
			 
			 `DIM_ORDER_ASCENDING:
			   begin
			      if(dim == 0)
				assign dim_sel = 1'b1;
			      else
				assign dim_sel = &addr_match_d[0:dim-1];
			   end
			 
			 `DIM_ORDER_DESCENDING:
			   begin
			      if(dim == (num_dimensions - 1))
				assign dim_sel = 1'b1;
			      else
				assign dim_sel
				  = &addr_match_d[dim+1:num_dimensions-1];
			   end
			 
			 `DIM_ORDER_BY_CLASS:
			   begin
			      
			      wire mc_even;
			      
			      if(num_message_classes == 1)
				assign mc_even = 1'b1;
			      else if(num_message_classes > 1)
				begin
				   
				   wire [0:message_class_idx_width-1] mcsel;
				   c_encode
				     #(.num_ports(num_message_classes))
				   mcsel_enc
				     (.data_in(sel_mc),
				      .data_out(mcsel));
				   
				   assign mc_even
				     = ~mcsel[message_class_idx_width-1];
				   
				end
			      
			      if(num_dimensions == 1)
				assign dim_sel = 1'b1;
			      else if(dim == 0)
				assign dim_sel
				  = &addr_match_d[1:num_dimensions-1] | 
				    mc_even;
			      else if(dim == (num_dimensions - 1))
				assign dim_sel
				  = &addr_match_d[0:num_dimensions-2] | 
				    ~mc_even;
			      else
				assign dim_sel
				  = mc_even ? 
				    &addr_match_d[0:dim-1] : 
				    &addr_match_d[dim+1:num_dimensions-1];
			      
			   end
			 
		       endcase
		       
		       wire [0:num_neighbors_per_dim-1] 	      port_dec;
		       
		       case(connectivity)
			 
			 `CONNECTIVITY_LINE:
			   begin
			      
			      assign port_dec = {dest_lt_curr, curr_lt_dest};
			      
			   end
			 
			 `CONNECTIVITY_RING:
			   begin
			      









			      wire tie_break;
			      assign tie_break
				= curr_dim_addr[dim_addr_width-1];
			      

			      
			      wire [0:dim_addr_width] dest_minus_curr_x2;
			      assign dest_minus_curr_x2
				= {dest_minus_curr, tie_break};
			      
			      wire [0:dim_addr_width] curr_minus_dest_x2;
			      assign curr_minus_dest_x2
				= {curr_minus_dest, ~tie_break};
			      
			      wire 		      dest_minus_curr_gt_half;
			      assign dest_minus_curr_gt_half
				= dest_minus_curr_x2 > num_routers_per_dim;
			      
			      wire 		      curr_minus_dest_gt_half;
			      assign curr_minus_dest_gt_half
				= curr_minus_dest_x2 > num_routers_per_dim;
			      
			      wire 		      route_down;
			      assign route_down
				= (curr_lt_dest & dest_minus_curr_gt_half) |
				  (dest_lt_curr & ~curr_minus_dest_gt_half);
			      
			      wire 		      route_up;
			      assign route_up
				= (curr_lt_dest & ~dest_minus_curr_gt_half) |
				  (dest_lt_curr & curr_minus_dest_gt_half);
			      
			      assign port_dec = {route_down, route_up};
			      
			   end
			 
			 `CONNECTIVITY_FULL:
			   begin
			      
			      wire [0:num_routers_per_dim-1] port_sel_up;
			      c_decode
				#(.num_ports(num_routers_per_dim))
			      port_sel_up_dec
				(.data_in(dest_minus_curr),
				 .data_out(port_sel_up));
			      
			      wire [0:num_routers_per_dim-1] port_sel_down_rev;
			      c_decode
				#(.num_ports(num_routers_per_dim))
			      port_sel_down_rev_dec
				(.data_in(curr_minus_dest),
				 .data_out(port_sel_down_rev));
			      
			      wire [0:num_routers_per_dim-1] port_sel_down;
			      c_reverse
				#(.width(num_routers_per_dim))
			      port_sel_down_revr
				(.data_in(port_sel_down_rev),
				 .data_out(port_sel_down));
			      
			      wire [0:num_neighbors_per_dim-1] port_dec_up;
			      assign port_dec_up
				= port_sel_up[1:num_routers_per_dim-1];
			      
			      wire [0:num_neighbors_per_dim-1] port_dec_down;
			      assign port_dec_down
				= port_sel_down[0:num_routers_per_dim-2];
			      
			      c_select_mofn
				#(.num_ports(2),
				  .width(num_neighbors_per_dim))
			      port_dec_sel
				(.select({dest_lt_curr, curr_lt_dest}),
				 .data_in({port_dec_down, port_dec_up}),
				 .data_out(port_dec));
			      
			   end
			 
		       endcase
		       
		       assign route_onp[dim*num_neighbors_per_dim:
					(dim+1)*num_neighbors_per_dim-1]
			 = port_dec & {num_neighbors_per_dim{dim_sel}};
		       
		    end
		  
		  assign route_orc_onp[irc*num_network_ports:
				       (irc+1)*num_network_ports-1]
		    = route_onp;
		  
		  assign reached_dest_irc[irc] = &addr_match_d;
		  
	       end
	     
	     if(num_resource_classes == 1)
	       begin
		  assign eject = reached_dest_irc;
		  assign route_orc = 1'b1;
	       end
	     else
	       begin
		  
		  wire [0:num_resource_classes-1] class_done_irc;
		  assign class_done_irc = sel_irc & reached_dest_irc;
		  
		  wire inc_rc;
		  assign inc_rc = |class_done_irc[0:num_resource_classes-2];
		  
		  assign eject = class_done_irc[num_resource_classes-1];
		  
		  assign route_orc = inc_rc ?
				     {1'b0, sel_irc[0:num_resource_classes-2]} :
				     sel_irc;
		  
	       end
	     
	  end
	
      endcase
      
   endgenerate
   
   c_select_1ofn
     #(.num_ports(num_resource_classes),
       .width(num_network_ports))
   route_onp_sel
     (.select(route_orc),
      .data_in(route_orc_onp),
      .data_out(route_onp));
   
   generate
      
      if(num_nodes_per_router == 1)
	assign route_op[num_ports-1] = eject;
      else if(num_nodes_per_router > 1)
	begin
	   
	   wire [0:node_addr_width-1] dest_node_address;
	   assign dest_node_address
	     = dest_info[dest_info_width-node_addr_width:dest_info_width-1];
	   
	   wire [0:num_nodes_per_router-1] node_sel;
	   c_decode
	     #(.num_ports(num_nodes_per_router))
	   node_sel_dec
	     (.data_in(dest_node_address),
	      .data_out(node_sel));
	   
	   assign route_op[num_ports-num_nodes_per_router:num_ports-1]
		    = node_sel & {num_nodes_per_router{eject}};
	   
	end
      
   endgenerate
   
endmodule
module rtr_routing_logic
  (router_address, sel_mc, sel_irc, dest_info, route_op, route_orc);

   
`include "c_functions.v"
`include "c_constants.v"
   
   



   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   parameter num_routers_per_dim = 4;
   

   parameter num_dimensions = 2;
   

   parameter num_nodes_per_router = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam message_class_idx_width = clogb(num_message_classes);
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam num_network_ports = num_ports - num_nodes_per_router;
   
   



   

   input [0:router_addr_width-1] router_address;
   

   input [0:num_message_classes-1] sel_mc;
   

   input [0:num_resource_classes-1] sel_irc;
   

   input [0:dest_info_width-1]     dest_info;
   

   output [0:num_ports-1] 	    route_op;
   wire [0:num_ports-1] 	    route_op;
   

   output [0:num_resource_classes-1] route_orc;
   wire [0:num_resource_classes-1]   route_orc;
   
   



   
   wire [0:num_network_ports-1]      route_onp;
   assign route_op[0:num_network_ports-1] = route_onp;
   
   wire [0:num_resource_classes*num_network_ports-1] route_orc_onp;
   wire 					     eject;
   
   generate
      
      case(routing_type)
	
	`ROUTING_TYPE_PHASED_DOR:
	  begin
	     

	     wire [0:num_resource_classes*
		   router_addr_width-1] dest_router_addr_irc;
	     assign dest_router_addr_irc
	       = dest_info[0:num_resource_classes*router_addr_width-1];
	     
	     wire [0:num_resource_classes-1] reached_dest_irc;
	     
	     genvar 			     irc;
	     
	     for(irc = 0; irc < num_resource_classes; irc = irc + 1)
	       begin:ircs
		  

		  wire [0:router_addr_width-1] dest_router_addr;
		  assign dest_router_addr
		    = dest_router_addr_irc[irc*router_addr_width:
					   (irc+1)*router_addr_width-1];
		  
		  wire [0:num_network_ports-1] route_onp;
		  
		  wire [0:num_dimensions-1]    addr_match_d;
		  
		  genvar 		       dim;
		  
		  for(dim = 0; dim < num_dimensions; dim = dim + 1)
		    begin:dims
		       
		       wire [0:dim_addr_width-1] dest_dim_addr;
		       assign dest_dim_addr
			 = dest_router_addr[dim*dim_addr_width:
					    (dim+1)*dim_addr_width-1];
		       
		       wire [0:dim_addr_width-1] curr_dim_addr;
		       assign curr_dim_addr
			 = router_address[dim*dim_addr_width:
					  (dim+1)*dim_addr_width-1];
		       
		       wire 			 dest_lt_curr;
		       wire [0:dim_addr_width-1] dest_minus_curr;
		       assign {dest_lt_curr, dest_minus_curr}
			 = dest_dim_addr - curr_dim_addr;
		       
		       wire 			 curr_lt_dest;
		       wire [0:dim_addr_width-1] curr_minus_dest;
		       assign {curr_lt_dest, curr_minus_dest}
			 = curr_dim_addr - dest_dim_addr;
		       
		       assign addr_match_d[dim] = ~dest_lt_curr & ~curr_lt_dest;
		       
		       wire 			 dim_sel;
		       
		       case(dim_order)
			 
			 `DIM_ORDER_ASCENDING:
			   begin
			      if(dim == 0)
				assign dim_sel = 1'b1;
			      else
				assign dim_sel = &addr_match_d[0:dim-1];
			   end
			 
			 `DIM_ORDER_DESCENDING:
			   begin
			      if(dim == (num_dimensions - 1))
				assign dim_sel = 1'b1;
			      else
				assign dim_sel
				  = &addr_match_d[dim+1:num_dimensions-1];
			   end
			 
			 `DIM_ORDER_BY_CLASS:
			   begin
			      
			      wire mc_even;
			      
			      if(num_message_classes == 1)
				assign mc_even = 1'b1;
			      else if(num_message_classes > 1)
				begin
				   
				   wire [0:message_class_idx_width-1] mcsel;
				   c_encode
				     #(.num_ports(num_message_classes))
				   mcsel_enc
				     (.data_in(sel_mc),
				      .data_out(mcsel));
				   
				   assign mc_even
				     = ~mcsel[message_class_idx_width-1];
				   
				end
			      
			      if(num_dimensions == 1)
				assign dim_sel = 1'b1;
			      else if(dim == 0)
				assign dim_sel
				  = &addr_match_d[1:num_dimensions-1] | 
				    mc_even;
			      else if(dim == (num_dimensions - 1))
				assign dim_sel
				  = &addr_match_d[0:num_dimensions-2] | 
				    ~mc_even;
			      else
				assign dim_sel
				  = mc_even ? 
				    &addr_match_d[0:dim-1] : 
				    &addr_match_d[dim+1:num_dimensions-1];
			      
			   end
			 
		       endcase
		       
		       wire [0:num_neighbors_per_dim-1] 	      port_dec;
		       
		       case(connectivity)
			 
			 `CONNECTIVITY_LINE:
			   begin
			      
			      assign port_dec = {dest_lt_curr, curr_lt_dest};
			      
			   end
			 
			 `CONNECTIVITY_RING:
			   begin
			      









			      wire tie_break;
			      assign tie_break
				= curr_dim_addr[dim_addr_width-1];
			      

			      
			      wire [0:dim_addr_width] dest_minus_curr_x2;
			      assign dest_minus_curr_x2
				= {dest_minus_curr, tie_break};
			      
			      wire [0:dim_addr_width] curr_minus_dest_x2;
			      assign curr_minus_dest_x2
				= {curr_minus_dest, ~tie_break};
			      
			      wire 		      dest_minus_curr_gt_half;
			      assign dest_minus_curr_gt_half
				= dest_minus_curr_x2 > num_routers_per_dim;
			      
			      wire 		      curr_minus_dest_gt_half;
			      assign curr_minus_dest_gt_half
				= curr_minus_dest_x2 > num_routers_per_dim;
			      
			      wire 		      route_down;
			      assign route_down
				= (curr_lt_dest & dest_minus_curr_gt_half) |
				  (dest_lt_curr & ~curr_minus_dest_gt_half);
			      
			      wire 		      route_up;
			      assign route_up
				= (curr_lt_dest & ~dest_minus_curr_gt_half) |
				  (dest_lt_curr & curr_minus_dest_gt_half);
			      
			      assign port_dec = {route_down, route_up};
			      
			   end
			 
			 `CONNECTIVITY_FULL:
			   begin
			      
			      wire [0:num_routers_per_dim-1] port_sel_up;
			      c_decode
				#(.num_ports(num_routers_per_dim))
			      port_sel_up_dec
				(.data_in(dest_minus_curr),
				 .data_out(port_sel_up));
			      
			      wire [0:num_routers_per_dim-1] port_sel_down_rev;
			      c_decode
				#(.num_ports(num_routers_per_dim))
			      port_sel_down_rev_dec
				(.data_in(curr_minus_dest),
				 .data_out(port_sel_down_rev));
			      
			      wire [0:num_routers_per_dim-1] port_sel_down;
			      c_reverse
				#(.width(num_routers_per_dim))
			      port_sel_down_revr
				(.data_in(port_sel_down_rev),
				 .data_out(port_sel_down));
			      
			      wire [0:num_neighbors_per_dim-1] port_dec_up;
			      assign port_dec_up
				= port_sel_up[1:num_routers_per_dim-1];
			      
			      wire [0:num_neighbors_per_dim-1] port_dec_down;
			      assign port_dec_down
				= port_sel_down[0:num_routers_per_dim-2];
			      
			      c_select_mofn
				#(.num_ports(2),
				  .width(num_neighbors_per_dim))
			      port_dec_sel
				(.select({dest_lt_curr, curr_lt_dest}),
				 .data_in({port_dec_down, port_dec_up}),
				 .data_out(port_dec));
			      
			   end
			 
		       endcase
		       
		       assign route_onp[dim*num_neighbors_per_dim:
					(dim+1)*num_neighbors_per_dim-1]
			 = port_dec & {num_neighbors_per_dim{dim_sel}};
		       
		    end
		  
		  assign route_orc_onp[irc*num_network_ports:
				       (irc+1)*num_network_ports-1]
		    = route_onp;
		  
		  assign reached_dest_irc[irc] = &addr_match_d;
		  
	       end
	     
	     if(num_resource_classes == 1)
	       begin
		  assign eject = reached_dest_irc;
		  assign route_orc = 1'b1;
	       end
	     else
	       begin
		  
		  wire [0:num_resource_classes-1] class_done_irc;
		  assign class_done_irc = sel_irc & reached_dest_irc;
		  
		  wire inc_rc;
		  assign inc_rc = |class_done_irc[0:num_resource_classes-2];
		  
		  assign eject = class_done_irc[num_resource_classes-1];
		  
		  assign route_orc = inc_rc ?
				     {1'b0, sel_irc[0:num_resource_classes-2]} :
				     sel_irc;
		  
	       end
	     
	  end
	
      endcase
      
   endgenerate
   
   c_select_1ofn
     #(.num_ports(num_resource_classes),
       .width(num_network_ports))
   route_onp_sel
     (.select(route_orc),
      .data_in(route_orc_onp),
      .data_out(route_onp));
   
   generate
      
      if(num_nodes_per_router == 1)
	assign route_op[num_ports-1] = eject;
      else if(num_nodes_per_router > 1)
	begin
	   
	   wire [0:node_addr_width-1] dest_node_address;
	   assign dest_node_address
	     = dest_info[dest_info_width-node_addr_width:dest_info_width-1];
	   
	   wire [0:num_nodes_per_router-1] node_sel;
	   c_decode
	     #(.num_ports(num_nodes_per_router))
	   node_sel_dec
	     (.data_in(dest_node_address),
	      .data_out(node_sel));
	   
	   assign route_op[num_ports-num_nodes_per_router:num_ports-1]
		    = node_sel & {num_nodes_per_router{eject}};
	   
	end
      
   endgenerate
   
endmodule