data/full_repos/permissive/498662723/Circuits/Sequential Logic/Latches and Flip flops/ece241 2013 q7 (create circuit from truth table).v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: flops,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: flops/ece241\n%Error: Cannot find file containing module: 2013\n%Error: Cannot find file containing module: q7\n%Error: Cannot find file containing module: (create\n%Error: Cannot find file containing module: circuit\n%Error: Cannot find file containing module: from\n%Error: Cannot find file containing module: truth\n%Error: Cannot find file containing module: table).v\n%Error: Exiting due to 13 error(s)\n'
module d_ff (input d, clk,
             output reg q);
    
    always @ (posedge clk)
        begin
            q <= d;
        end
endmodule
module d_ff (input d, clk,
             output reg q);

    
    always @ (posedge clk)
        begin
            q <= d;
        end
endmodule