data/full_repos/permissive/484553918/rtl/vga2dvid.v
1: b"%Error: data/full_repos/permissive/484553918/rtl/vga2dvid.v:55: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/484553918/rtl/vga2dvid.v:77: syntax error, unexpected assign\n  assign c_blue = {in_vsync,in_hsync};\n  ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module vga2dvid(
input wire clk_pixel,
input wire clk_shift,
input wire [23:0] in_color,
input wire in_blank,
input wire in_hsync,
input wire in_vsync,
input wire resetn,
output wire [9:0] outp_red,
output wire [9:0] outp_green,
output wire [9:0] outp_blue,
output wire [1:0] out_red,
output wire [1:0] out_green,
output wire [1:0] out_blue,
output wire [1:0] out_clock,
);

parameter C_shift_clock_synchronizer=1'b1;




wire [9:0] encoded_red; wire [9:0] encoded_green; wire [9:0] encoded_blue;
reg [9:0] latched_red; reg [9:0] latched_green; reg [9:0] latched_blue;
reg [9:0] shift_red; reg [9:0] shift_green; reg [9:0] shift_blue;
parameter C_shift_clock_initial = 10'b0000011111;
reg [9:0] shift_clock;
reg R_shift_clock_off_sync;
reg [7:0] R_shift_clock_synchronizer;
reg [6:0] R_sync_fail;
parameter c_red = 1'b0;
parameter c_green = 1'b0;
wire [1:0] c_blue;
wire [7:0] red_d;
wire [7:0] green_d;
wire [7:0] blue_d;

  assign c_blue = {in_vsync,in_hsync};
  assign red_d[7:0] = in_color[23:16];
  assign green_d[7:0] = in_color[15:8];
  assign blue_d[7:0] = in_color[7:0];


  always @(posedge clk_pixel) begin
    if (!resetn)
      R_shift_clock_off_sync <= 1'b0;


    if(shift_clock[5:4] == C_shift_clock_initial[5:4]) begin

      R_shift_clock_off_sync <= 1'b0;
    end
    else begin
      R_shift_clock_off_sync <= 1'b1;
    end
  end


  always @(posedge clk_shift) begin
    if (!resetn)
       R_shift_clock_synchronizer <=  1'b0;
    if(R_shift_clock_off_sync == 1'b1) begin
      if(R_shift_clock_synchronizer[(7)] == 1'b1) begin
        R_shift_clock_synchronizer <= {8{1'b0}};
      end
      else begin
        R_shift_clock_synchronizer <= R_shift_clock_synchronizer + 1;
      end
    end
    else begin
      R_shift_clock_synchronizer <= {8{1'b0}};
    end
  end


  tmds_encoder u21(
      .clk(clk_pixel),
    .data(red_d),
    .c(c_red),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_red));

  tmds_encoder u22(
      .clk(clk_pixel),
    .data(green_d),
    .c(c_green),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_green));

  tmds_encoder u23(
      .clk(clk_pixel),
    .data(blue_d),
    .c(c_blue),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_blue));

  always @(posedge clk_pixel) begin
    if (!resetn)
    begin
      latched_red <= 1'b0;
      latched_green <= 1'b0;
      latched_blue <= 1'b0;
    end
    else
    begin
      latched_red <= encoded_red;
      latched_green <= encoded_green;
      latched_blue <= encoded_blue;
    end
  end

  assign outp_red = latched_red;
  assign outp_green = latched_green;
  assign outp_blue = latched_blue;

  always @(posedge clk_shift) begin
    if (!resetn)
    begin
      shift_red <= 1'b0;
      shift_green <= 1'b0;
      shift_blue <= 1'b0;
      shift_clock <= C_shift_clock_initial;
    end

    if(shift_clock[5:4] == C_shift_clock_initial[5:4]) begin

      shift_red <= latched_red;
      shift_green <= latched_green;
      shift_blue <= latched_blue;
    end
    else begin
      shift_red <= {2'b00,shift_red[9:2]};
      shift_green <= {2'b00,shift_green[9:2]};
      shift_blue <= {2'b00,shift_blue[9:2]};
    end
    if(R_shift_clock_synchronizer[(7)] == 1'b0) begin
      shift_clock <= {shift_clock[1:0],shift_clock[9:2]};
    end
    else begin


      if(R_sync_fail[(6)] == 1'b1) begin
        shift_clock <= C_shift_clock_initial;
        R_sync_fail <= {7{1'b0}};
      end
      else begin
        R_sync_fail <= R_sync_fail + 1;
      end
    end
  end


  assign out_red = shift_red[1:0];
  assign out_green = shift_green[1:0];
  assign out_blue = shift_blue[1:0];
  assign out_clock = shift_clock[1:0];

endmodule
module vga2dvid(
input wire clk_pixel,
input wire clk_shift,
input wire [23:0] in_color,
input wire in_blank,
input wire in_hsync,
input wire in_vsync,
input wire resetn,
output wire [9:0] outp_red,
output wire [9:0] outp_green,
output wire [9:0] outp_blue,
output wire [1:0] out_red,
output wire [1:0] out_green,
output wire [1:0] out_blue,
output wire [1:0] out_clock,
);


parameter C_shift_clock_synchronizer=1'b1;




wire [9:0] encoded_red; wire [9:0] encoded_green; wire [9:0] encoded_blue;
reg [9:0] latched_red; reg [9:0] latched_green; reg [9:0] latched_blue;
reg [9:0] shift_red; reg [9:0] shift_green; reg [9:0] shift_blue;
parameter C_shift_clock_initial = 10'b0000011111;
reg [9:0] shift_clock;
reg R_shift_clock_off_sync;
reg [7:0] R_shift_clock_synchronizer;
reg [6:0] R_sync_fail;
parameter c_red = 1'b0;
parameter c_green = 1'b0;
wire [1:0] c_blue;
wire [7:0] red_d;
wire [7:0] green_d;
wire [7:0] blue_d;

  assign c_blue = {in_vsync,in_hsync};
  assign red_d[7:0] = in_color[23:16];
  assign green_d[7:0] = in_color[15:8];
  assign blue_d[7:0] = in_color[7:0];


  always @(posedge clk_pixel) begin
    if (!resetn)
      R_shift_clock_off_sync <= 1'b0;


    if(shift_clock[5:4] == C_shift_clock_initial[5:4]) begin

      R_shift_clock_off_sync <= 1'b0;
    end
    else begin
      R_shift_clock_off_sync <= 1'b1;
    end
  end


  always @(posedge clk_shift) begin
    if (!resetn)
       R_shift_clock_synchronizer <=  1'b0;
    if(R_shift_clock_off_sync == 1'b1) begin
      if(R_shift_clock_synchronizer[(7)] == 1'b1) begin
        R_shift_clock_synchronizer <= {8{1'b0}};
      end
      else begin
        R_shift_clock_synchronizer <= R_shift_clock_synchronizer + 1;
      end
    end
    else begin
      R_shift_clock_synchronizer <= {8{1'b0}};
    end
  end


  tmds_encoder u21(
      .clk(clk_pixel),
    .data(red_d),
    .c(c_red),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_red));

  tmds_encoder u22(
      .clk(clk_pixel),
    .data(green_d),
    .c(c_green),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_green));

  tmds_encoder u23(
      .clk(clk_pixel),
    .data(blue_d),
    .c(c_blue),
    .blank(in_blank),
    .resetn(resetn),
    .encoded(encoded_blue));

  always @(posedge clk_pixel) begin
    if (!resetn)
    begin
      latched_red <= 1'b0;
      latched_green <= 1'b0;
      latched_blue <= 1'b0;
    end
    else
    begin
      latched_red <= encoded_red;
      latched_green <= encoded_green;
      latched_blue <= encoded_blue;
    end
  end

  assign outp_red = latched_red;
  assign outp_green = latched_green;
  assign outp_blue = latched_blue;

  always @(posedge clk_shift) begin
    if (!resetn)
    begin
      shift_red <= 1'b0;
      shift_green <= 1'b0;
      shift_blue <= 1'b0;
      shift_clock <= C_shift_clock_initial;
    end

    if(shift_clock[5:4] == C_shift_clock_initial[5:4]) begin

      shift_red <= latched_red;
      shift_green <= latched_green;
      shift_blue <= latched_blue;
    end
    else begin
      shift_red <= {2'b00,shift_red[9:2]};
      shift_green <= {2'b00,shift_green[9:2]};
      shift_blue <= {2'b00,shift_blue[9:2]};
    end
    if(R_shift_clock_synchronizer[(7)] == 1'b0) begin
      shift_clock <= {shift_clock[1:0],shift_clock[9:2]};
    end
    else begin


      if(R_sync_fail[(6)] == 1'b1) begin
        shift_clock <= C_shift_clock_initial;
        R_sync_fail <= {7{1'b0}};
      end
      else begin
        R_sync_fail <= R_sync_fail + 1;
      end
    end
  end


  assign out_red = shift_red[1:0];
  assign out_green = shift_green[1:0];
  assign out_blue = shift_blue[1:0];
  assign out_clock = shift_clock[1:0];

endmodule