data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:173: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            f0 <= 1\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:174: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            f1 <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:175: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            f2 <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:176: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            z0 <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:177: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            z1 <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:178: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance fragment_interpolator\n            z2 <= 1\'b0;\n               ^~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:264: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNz0 (z0, zaRecFN);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499944578/rtl/src/fragment_interpolator,data/full_repos/permissive/499944578/fNToRecFN\n             data/full_repos/permissive/499944578/rtl/src/fragment_interpolator,data/full_repos/permissive/499944578/fNToRecFN.v\n             data/full_repos/permissive/499944578/rtl/src/fragment_interpolator,data/full_repos/permissive/499944578/fNToRecFN.sv\n             fNToRecFN\n             fNToRecFN.v\n             fNToRecFN.sv\n             obj_dir/fNToRecFN\n             obj_dir/fNToRecFN.v\n             obj_dir/fNToRecFN.sv\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:265: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNz1 (z1, zbRecFN);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:266: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNz2 (z2, zcRecFN);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:268: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNf0 (f0, faRecFN);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:269: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNf1 (f1, fbRecFN);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:270: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNf2 (f2, fcRecFN);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:272: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNP0x (P0[63:32], PaRecFN[65:33]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:273: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNP0y (P0[31:0], PaRecFN[32:0]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:275: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFnP1x (P1[63:32], PbRecFN[65:33]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:276: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNP1y (P1[31:0], PbRecFN[32:0]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:278: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNP2x (P2[63:32], PcRecFN[65:33]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:279: Cannot find file containing module: \'fNToRecFN\'\n    fNToRecFN#(8,24) fNToRecFNP2y (P2[31:0], PcRecFN[32:0]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:281: Cannot find file containing module: \'attrInterp\'\n    attrInterp attrInterp_inst(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:307: Cannot find file containing module: \'recFNToFN\'\n    recFNToFN#(8,24) recFNToFN15 (fRecFN, f);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/fragment_interpolator/fragment_interpolator.v:308: Cannot find file containing module: \'recFNToFN\'\n    recFNToFN#(8,24) recFNToFN16 (zRecFN, z);\n    ^~~~~~~~~\n%Error: Exiting due to 15 error(s), 6 warning(s)\n'
module fragment_interpolator #(
    parameter DATA_WIDTH=32,
    parameter ADDR_WIDTH=4,
    parameter CYCLES_WAIT_FOR_RECIEVE=4'b0001
)(
    input wire clk,
    input wire resetn,
    input wire en,


    output reg [DATA_WIDTH-1:0] frag_attr_wr_data,       
    output reg [ADDR_WIDTH-1:0] frag_attr_wr_addr, 
    output reg                  frag_attr_wr_en,  


    input  wire [2:0][DATA_WIDTH-1:0] vert_attr_rd_data,       
    output reg  [2:0][ADDR_WIDTH-1:0] vert_attr_rd_addr, 
    output reg  [2:0][0:0]            vert_attr_rd_en,    



    input wire [65:0] Pin,

    input  wire start,
    output reg ready,
    output reg done,   
    

    input  wire noPerspective,
    input  wire flat,
    input  wire provokeMode,
    input  wire [ADDR_WIDTH-1:0] vertexSize
);
    reg isDepth;
    reg [63:0] P0, P1, P2;
    reg [65:0] P;
    
    reg [31:0] z0, z1, z2, f0, f1, f2;
    wire [31:0] f,z;
    reg attrInterp_inValid;
    wire attrInterp_inReady, attrInterp_outValid, attrInterp_en;
    assign attrInterp_en = en;
    


    localparam        IDLE = 3'b000;
    localparam     REQUEST = 3'b001;
    localparam WAIT_FOR_RECIEVE = 3'b011;
    localparam     RECIEVE = 3'b010;
    localparam INTERPOLATE = 3'b110;
    localparam       WRITE = 3'b111;
    
    reg [2:0] processingStage;


    localparam PROC_X = 2'b00;
    localparam PROC_Y = 2'b01;
    localparam PROC_Z = 2'b11;
    localparam PROC_F = 2'b10;
    reg [1:0] thingBeingProcessed;

    reg [ADDR_WIDTH-1:0] rd_wr_addr;
    reg [3:0] passedCyclesWaitForRecieve;

    always @(posedge clk or negedge resetn) begin
        if (resetn == 1'b0) begin
            thingBeingProcessed <= PROC_X;
            processingStage <= IDLE;
            rd_wr_addr <= 'b0;
            passedCyclesWaitForRecieve <= 4'b0001;
            P <= 'b0;
            done <= 1'b0;
            ready <= 1'b0;
            isDepth <= 1'b0;
        end else begin
            case (processingStage)
                IDLE: begin
                    rd_wr_addr <= 'b0;
                    done <= 1'b0;
                    if(start) begin 
                        P <= Pin;
                        processingStage <= REQUEST; 
                        ready <= 1'b0;
                    end else begin
                        ready <= 1'b1;
                    end
                end
                REQUEST: processingStage <= WAIT_FOR_RECIEVE;   
                WAIT_FOR_RECIEVE: begin
                    if(passedCyclesWaitForRecieve == CYCLES_WAIT_FOR_RECIEVE) begin
                        processingStage <= RECIEVE;
                        passedCyclesWaitForRecieve <= 4'b0001;
                    end else begin
                        processingStage <= WAIT_FOR_RECIEVE;
                        passedCyclesWaitForRecieve <= passedCyclesWaitForRecieve + 4'b0001;
                    end
                end
                RECIEVE:
                    case (thingBeingProcessed)
                        PROC_X: begin
                            thingBeingProcessed <= PROC_Y;
                            processingStage <= REQUEST;
                            rd_wr_addr <= 'b01;
                        end
                        PROC_Y: begin
                            thingBeingProcessed <= PROC_Z;
                            processingStage <= REQUEST;
                            rd_wr_addr <= 'b10;
                        end
                        PROC_Z: begin
                            isDepth <= 1'b1;
                            processingStage <= INTERPOLATE;
                        end
                        PROC_F: begin
                            isDepth <= 1'b0;
                            processingStage <= INTERPOLATE;
                        end
                    endcase

                INTERPOLATE: begin
                    if(attrInterp_outValid) begin
                        processingStage <= WRITE;
                    end
                end
                WRITE: begin
                    
                    if(rd_wr_addr < vertexSize) begin
                        rd_wr_addr <= rd_wr_addr + 'b1;
                        processingStage <= REQUEST;
                        if(thingBeingProcessed == PROC_Z) begin
                            thingBeingProcessed <= PROC_F;  
                        end
                           
                    end
                    if(rd_wr_addr == vertexSize) begin
                        thingBeingProcessed <= PROC_X;
                        rd_wr_addr <= 'b0;
                        done <= 1'b1;
                        processingStage <= IDLE;
                    end

                end
            endcase
        end

    end

    reg attrInterp_resetn;
    always @(posedge clk or negedge resetn) begin
        if (resetn == 1'b0) begin
            frag_attr_wr_data <= 'b0;       
            frag_attr_wr_addr <= 'b0; 
            frag_attr_wr_en <= 'b0;  
            vert_attr_rd_addr [0]  <= 'b0; 
            vert_attr_rd_en   [0] <= 'b0;
            vert_attr_rd_addr [1]  <= 'b0; 
            vert_attr_rd_en   [1] <= 'b0;
            vert_attr_rd_addr [2]  <= 'b0; 
            vert_attr_rd_en   [2] <= 'b0;
            
            attrInterp_inValid <= 1'b0;
            attrInterp_resetn <= 1'b1;


            thingBeingProcessed <= PROC_X;
            processingStage <= IDLE;

            P0 <= 'b0;
            P1 <= 'b0;
            P2 <= 'b0;
            f0 <= 1'b0;
            f1 <= 1'b0;
            f2 <= 1'b0;
            z0 <= 1'b0;
            z1 <= 1'b0;
            z2 <= 1'b0;
        end else begin
            case (processingStage)
                IDLE: begin
                    vert_attr_rd_addr<= 'b0; 
                    vert_attr_rd_en <= 'b0;  
                    frag_attr_wr_en <= 1'b0;
                end

                REQUEST: begin
                    vert_attr_rd_addr[0] <= rd_wr_addr;  
                    vert_attr_rd_addr[1] <= rd_wr_addr; 
                    vert_attr_rd_addr[2] <= rd_wr_addr; 
                    vert_attr_rd_en <= 3'b111;  
                    frag_attr_wr_en <= 1'b0;
                    attrInterp_resetn <= 1'b0;
                end          
                RECIEVE: begin
                    attrInterp_resetn <= 1'b1;
                    vert_attr_rd_en <= 3'b000;
                    case(thingBeingProcessed)
                        PROC_X: begin
                            P0[63:32] <= vert_attr_rd_data[0];
                            P1[63:32] <= vert_attr_rd_data[1];
                            P2[63:32] <= vert_attr_rd_data[2];
                        end
                        PROC_Y: begin
                            P0[31:0] <= vert_attr_rd_data[0];
                            P1[31:0] <= vert_attr_rd_data[1];
                            P2[31:0] <= vert_attr_rd_data[2];
                        end
                        PROC_Z: begin
                            z0 <= vert_attr_rd_data[0];
                            z1 <= vert_attr_rd_data[1];
                            z2 <= vert_attr_rd_data[2];

                        end
                        PROC_F: begin
                            f0 <= vert_attr_rd_data[0];
                            f1 <= vert_attr_rd_data[1];
                            f2 <= vert_attr_rd_data[2];
                        end
                    endcase
                end
                INTERPOLATE: begin
                    if(attrInterp_inReady) begin


                        attrInterp_inValid <= 1'b1;
                    end else begin
                        attrInterp_inValid <= 1'b0;
                    end
                    

                end
                WRITE: begin
                    case (thingBeingProcessed)
                    
                        PROC_X: begin
                            
                        end
                        PROC_Y: begin
                            
                        end
                        PROC_Z: begin
                            frag_attr_wr_data <= z; 
                            frag_attr_wr_addr <= rd_wr_addr; 
                            frag_attr_wr_en <= 1'b1;
                        end
                        PROC_F: begin
                            frag_attr_wr_data <= f; 
                            frag_attr_wr_addr <= rd_wr_addr; 
                            frag_attr_wr_en <= 1'b1;
                        end
                    endcase
                    
                end
            endcase
        end

    end
    

    wire [65:0]PRecFN, PaRecFN, PbRecFN, PcRecFN;
    wire [32:0] zaRecFN, zbRecFN, zcRecFN, faRecFN, fbRecFN, fcRecFN, fRecFN, zRecFN;
    
    fNToRecFN#(8,24) fNToRecFNz0 (z0, zaRecFN);
    fNToRecFN#(8,24) fNToRecFNz1 (z1, zbRecFN);
    fNToRecFN#(8,24) fNToRecFNz2 (z2, zcRecFN);

    fNToRecFN#(8,24) fNToRecFNf0 (f0, faRecFN);
    fNToRecFN#(8,24) fNToRecFNf1 (f1, fbRecFN);
    fNToRecFN#(8,24) fNToRecFNf2 (f2, fcRecFN);

    fNToRecFN#(8,24) fNToRecFNP0x (P0[63:32], PaRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP0y (P0[31:0], PaRecFN[32:0]);

    fNToRecFN#(8,24) fNToRecFnP1x (P1[63:32], PbRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP1y (P1[31:0], PbRecFN[32:0]);

    fNToRecFN#(8,24) fNToRecFNP2x (P2[63:32], PcRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP2y (P2[31:0], PcRecFN[32:0]);

    attrInterp attrInterp_inst(
        .clk(clk), 
        .resetn(reset && attrInterp_resetn),
        .en(attrInterp_en),
        .inReady(attrInterp_inReady), 
        .inValid(attrInterp_inValid), 
        .outValid(attrInterp_outValid),

        .P(P),
        .Pa(PaRecFN),
        .Pb(PbRecFN),
        .Pc(PcRecFN),
        
        .za(zaRecFN), 
        .zb(zbRecFN),
        .zc(zcRecFN), 

        .fa(faRecFN), 
        .fb(fbRecFN), 
        .fc(fcRecFN), 

        .f(fRecFN),
        .z(zRecFN),
        .flags({isDepth, noPerspective, flat, provokeMode})
    );

    recFNToFN#(8,24) recFNToFN15 (fRecFN, f);
    recFNToFN#(8,24) recFNToFN16 (zRecFN, z);
    always @(*) begin


        
    end
endmodule
module fragment_interpolator #(
    parameter DATA_WIDTH=32,
    parameter ADDR_WIDTH=4,
    parameter CYCLES_WAIT_FOR_RECIEVE=4'b0001
)(
    input wire clk,
    input wire resetn,
    input wire en,


    output reg [DATA_WIDTH-1:0] frag_attr_wr_data,       
    output reg [ADDR_WIDTH-1:0] frag_attr_wr_addr, 
    output reg                  frag_attr_wr_en,  


    input  wire [2:0][DATA_WIDTH-1:0] vert_attr_rd_data,       
    output reg  [2:0][ADDR_WIDTH-1:0] vert_attr_rd_addr, 
    output reg  [2:0][0:0]            vert_attr_rd_en,    



    input wire [65:0] Pin,

    input  wire start,
    output reg ready,
    output reg done,   
    

    input  wire noPerspective,
    input  wire flat,
    input  wire provokeMode,
    input  wire [ADDR_WIDTH-1:0] vertexSize
);

    reg isDepth;
    reg [63:0] P0, P1, P2;
    reg [65:0] P;
    
    reg [31:0] z0, z1, z2, f0, f1, f2;
    wire [31:0] f,z;
    reg attrInterp_inValid;
    wire attrInterp_inReady, attrInterp_outValid, attrInterp_en;
    assign attrInterp_en = en;
    


    localparam        IDLE = 3'b000;
    localparam     REQUEST = 3'b001;
    localparam WAIT_FOR_RECIEVE = 3'b011;
    localparam     RECIEVE = 3'b010;
    localparam INTERPOLATE = 3'b110;
    localparam       WRITE = 3'b111;
    
    reg [2:0] processingStage;


    localparam PROC_X = 2'b00;
    localparam PROC_Y = 2'b01;
    localparam PROC_Z = 2'b11;
    localparam PROC_F = 2'b10;
    reg [1:0] thingBeingProcessed;

    reg [ADDR_WIDTH-1:0] rd_wr_addr;
    reg [3:0] passedCyclesWaitForRecieve;

    always @(posedge clk or negedge resetn) begin
        if (resetn == 1'b0) begin
            thingBeingProcessed <= PROC_X;
            processingStage <= IDLE;
            rd_wr_addr <= 'b0;
            passedCyclesWaitForRecieve <= 4'b0001;
            P <= 'b0;
            done <= 1'b0;
            ready <= 1'b0;
            isDepth <= 1'b0;
        end else begin
            case (processingStage)
                IDLE: begin
                    rd_wr_addr <= 'b0;
                    done <= 1'b0;
                    if(start) begin 
                        P <= Pin;
                        processingStage <= REQUEST; 
                        ready <= 1'b0;
                    end else begin
                        ready <= 1'b1;
                    end
                end
                REQUEST: processingStage <= WAIT_FOR_RECIEVE;   
                WAIT_FOR_RECIEVE: begin
                    if(passedCyclesWaitForRecieve == CYCLES_WAIT_FOR_RECIEVE) begin
                        processingStage <= RECIEVE;
                        passedCyclesWaitForRecieve <= 4'b0001;
                    end else begin
                        processingStage <= WAIT_FOR_RECIEVE;
                        passedCyclesWaitForRecieve <= passedCyclesWaitForRecieve + 4'b0001;
                    end
                end
                RECIEVE:
                    case (thingBeingProcessed)
                        PROC_X: begin
                            thingBeingProcessed <= PROC_Y;
                            processingStage <= REQUEST;
                            rd_wr_addr <= 'b01;
                        end
                        PROC_Y: begin
                            thingBeingProcessed <= PROC_Z;
                            processingStage <= REQUEST;
                            rd_wr_addr <= 'b10;
                        end
                        PROC_Z: begin
                            isDepth <= 1'b1;
                            processingStage <= INTERPOLATE;
                        end
                        PROC_F: begin
                            isDepth <= 1'b0;
                            processingStage <= INTERPOLATE;
                        end
                    endcase

                INTERPOLATE: begin
                    if(attrInterp_outValid) begin
                        processingStage <= WRITE;
                    end
                end
                WRITE: begin
                    
                    if(rd_wr_addr < vertexSize) begin
                        rd_wr_addr <= rd_wr_addr + 'b1;
                        processingStage <= REQUEST;
                        if(thingBeingProcessed == PROC_Z) begin
                            thingBeingProcessed <= PROC_F;  
                        end
                           
                    end
                    if(rd_wr_addr == vertexSize) begin
                        thingBeingProcessed <= PROC_X;
                        rd_wr_addr <= 'b0;
                        done <= 1'b1;
                        processingStage <= IDLE;
                    end

                end
            endcase
        end

    end

    reg attrInterp_resetn;
    always @(posedge clk or negedge resetn) begin
        if (resetn == 1'b0) begin
            frag_attr_wr_data <= 'b0;       
            frag_attr_wr_addr <= 'b0; 
            frag_attr_wr_en <= 'b0;  
            vert_attr_rd_addr [0]  <= 'b0; 
            vert_attr_rd_en   [0] <= 'b0;
            vert_attr_rd_addr [1]  <= 'b0; 
            vert_attr_rd_en   [1] <= 'b0;
            vert_attr_rd_addr [2]  <= 'b0; 
            vert_attr_rd_en   [2] <= 'b0;
            
            attrInterp_inValid <= 1'b0;
            attrInterp_resetn <= 1'b1;


            thingBeingProcessed <= PROC_X;
            processingStage <= IDLE;

            P0 <= 'b0;
            P1 <= 'b0;
            P2 <= 'b0;
            f0 <= 1'b0;
            f1 <= 1'b0;
            f2 <= 1'b0;
            z0 <= 1'b0;
            z1 <= 1'b0;
            z2 <= 1'b0;
        end else begin
            case (processingStage)
                IDLE: begin
                    vert_attr_rd_addr<= 'b0; 
                    vert_attr_rd_en <= 'b0;  
                    frag_attr_wr_en <= 1'b0;
                end

                REQUEST: begin
                    vert_attr_rd_addr[0] <= rd_wr_addr;  
                    vert_attr_rd_addr[1] <= rd_wr_addr; 
                    vert_attr_rd_addr[2] <= rd_wr_addr; 
                    vert_attr_rd_en <= 3'b111;  
                    frag_attr_wr_en <= 1'b0;
                    attrInterp_resetn <= 1'b0;
                end          
                RECIEVE: begin
                    attrInterp_resetn <= 1'b1;
                    vert_attr_rd_en <= 3'b000;
                    case(thingBeingProcessed)
                        PROC_X: begin
                            P0[63:32] <= vert_attr_rd_data[0];
                            P1[63:32] <= vert_attr_rd_data[1];
                            P2[63:32] <= vert_attr_rd_data[2];
                        end
                        PROC_Y: begin
                            P0[31:0] <= vert_attr_rd_data[0];
                            P1[31:0] <= vert_attr_rd_data[1];
                            P2[31:0] <= vert_attr_rd_data[2];
                        end
                        PROC_Z: begin
                            z0 <= vert_attr_rd_data[0];
                            z1 <= vert_attr_rd_data[1];
                            z2 <= vert_attr_rd_data[2];

                        end
                        PROC_F: begin
                            f0 <= vert_attr_rd_data[0];
                            f1 <= vert_attr_rd_data[1];
                            f2 <= vert_attr_rd_data[2];
                        end
                    endcase
                end
                INTERPOLATE: begin
                    if(attrInterp_inReady) begin


                        attrInterp_inValid <= 1'b1;
                    end else begin
                        attrInterp_inValid <= 1'b0;
                    end
                    

                end
                WRITE: begin
                    case (thingBeingProcessed)
                    
                        PROC_X: begin
                            
                        end
                        PROC_Y: begin
                            
                        end
                        PROC_Z: begin
                            frag_attr_wr_data <= z; 
                            frag_attr_wr_addr <= rd_wr_addr; 
                            frag_attr_wr_en <= 1'b1;
                        end
                        PROC_F: begin
                            frag_attr_wr_data <= f; 
                            frag_attr_wr_addr <= rd_wr_addr; 
                            frag_attr_wr_en <= 1'b1;
                        end
                    endcase
                    
                end
            endcase
        end

    end
    

    wire [65:0]PRecFN, PaRecFN, PbRecFN, PcRecFN;
    wire [32:0] zaRecFN, zbRecFN, zcRecFN, faRecFN, fbRecFN, fcRecFN, fRecFN, zRecFN;
    
    fNToRecFN#(8,24) fNToRecFNz0 (z0, zaRecFN);
    fNToRecFN#(8,24) fNToRecFNz1 (z1, zbRecFN);
    fNToRecFN#(8,24) fNToRecFNz2 (z2, zcRecFN);

    fNToRecFN#(8,24) fNToRecFNf0 (f0, faRecFN);
    fNToRecFN#(8,24) fNToRecFNf1 (f1, fbRecFN);
    fNToRecFN#(8,24) fNToRecFNf2 (f2, fcRecFN);

    fNToRecFN#(8,24) fNToRecFNP0x (P0[63:32], PaRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP0y (P0[31:0], PaRecFN[32:0]);

    fNToRecFN#(8,24) fNToRecFnP1x (P1[63:32], PbRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP1y (P1[31:0], PbRecFN[32:0]);

    fNToRecFN#(8,24) fNToRecFNP2x (P2[63:32], PcRecFN[65:33]);
    fNToRecFN#(8,24) fNToRecFNP2y (P2[31:0], PcRecFN[32:0]);

    attrInterp attrInterp_inst(
        .clk(clk), 
        .resetn(reset && attrInterp_resetn),
        .en(attrInterp_en),
        .inReady(attrInterp_inReady), 
        .inValid(attrInterp_inValid), 
        .outValid(attrInterp_outValid),

        .P(P),
        .Pa(PaRecFN),
        .Pb(PbRecFN),
        .Pc(PcRecFN),
        
        .za(zaRecFN), 
        .zb(zbRecFN),
        .zc(zcRecFN), 

        .fa(faRecFN), 
        .fb(fbRecFN), 
        .fc(fcRecFN), 

        .f(fRecFN),
        .z(zRecFN),
        .flags({isDepth, noPerspective, flat, provokeMode})
    );

    recFNToFN#(8,24) recFNToFN15 (fRecFN, f);
    recFNToFN#(8,24) recFNToFN16 (zRecFN, z);
    always @(*) begin


        
    end
endmodule