data/full_repos/permissive/456824115/testbench/compare2_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:35: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:44: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:48: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:49: Unsupported: Ignoring delay on this delayed statement.\n                #2\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/compare2_tb.sv:54: Unsupported: Ignoring delay on this delayed statement.\n       #200 $finish();\n       ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comparer2_tb;

parameter DATA_WIDTH = 8;
bit clk;
bit arstn;
bit [DATA_WIDTH-1:0]dinA;
bit [DATA_WIDTH-1:0]dinB;

wire [DATA_WIDTH-1:0]max;

wire [DATA_WIDTH-1:0]min;
integer i;
always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        dinA = 0;
        dinB = 0;
       
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=0;i<64;i=i+1)
            begin
                @(posedge clk);
                #2
                dinA = $random()%256;
                dinB = $random()%256;
              
            end
       #200 $finish();
    end

comparer2 #(
    .DATA_WIDTH(DATA_WIDTH)
)DUT(clk,arstn,dinA,dinB,max,min);
endmodule
module comparer2_tb;


parameter DATA_WIDTH = 8;
bit clk;
bit arstn;
bit [DATA_WIDTH-1:0]dinA;
bit [DATA_WIDTH-1:0]dinB;

wire [DATA_WIDTH-1:0]max;

wire [DATA_WIDTH-1:0]min;
integer i;
always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        dinA = 0;
        dinB = 0;
       
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=0;i<64;i=i+1)
            begin
                @(posedge clk);
                #2
                dinA = $random()%256;
                dinB = $random()%256;
              
            end
       #200 $finish();
    end

comparer2 #(
    .DATA_WIDTH(DATA_WIDTH)
)DUT(clk,arstn,dinA,dinB,max,min);
endmodule