data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v
1: b"%Error: data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v:18: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(23)(clk, reset, clk_cnt_dn);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v:19: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(25)(clk, reset, clk_yellow);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v:20: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(15)(clk, reset, clk_sel);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v:22: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select#(2)(clk_sel, reset, seg7_sel);\n                ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1dd/lab7_1.v:34: syntax error, unexpected '(', expecting IDENTIFIER\nryg_ctl (clk_1, clk_2, reset, day_night, g1_cnt, g1_en, light_led);\n         ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module 	ryg_ctl(clk_1, clk_2, reset, day_night, g1_cnt, g1_en, light_led);

input	clk_1, clk_2, reset, day_night;
input	[7:0]g1_cnt;
output	g1_en;
output	[5:0]light_led;
reg 	g1_en;
reg		[5:0]light_led;
reg		[2:0]mode;

always@(posedge clk_1 or posedge reset) 
begin
	if (reset)
		begin
		light_led	= 6'b001_100;
		mode 		= 3'b0;
		g1_en 		= 1'b0;
		end
	else if(day_night == 1'b1)
		case(mode)
		3'd0: 
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		3'd1:
			begin
			light_led	= 6'b010_100;
			if (g1_cnt == 8'b0000_0110)

				mode 	= mode + 3'b1; 
			end	

		3'd2:
			begin
			light_led	= 6'b100_100;  
			if(g1_cnt == 8'b0000_0000) 
				begin
				g1_en 	= 1'b0;
				mode 	= mode + 3'b1; 
				end

		end
		3'd3: 
			begin
			light_led	= 6'b100_001;
			g1_en = 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode+ 3'b1; 
			end

		3'd4:
			begin
			light_led	= 6'b100_010;
			if (g1_cnt == 8'b0000_0110)
				begin
				mode 	= mode + 3'b1; 

				end

			end
		3'd5:
			begin
			light_led	= 6'b100_100;  
			if(g1_cnt == 8'b0000_0000) 
				begin
				g1_en 	= 1'b0;
				mode 	= 3'b0; 
				end
			end
		default:
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		endcase

	else if(day_night == 1'b0)begin
		light_led= {{1'b0, clk_2, 1'b0}, {1'b0, clk_2, 1'b0}};
		g1_en=1'b0;



		end
end
endmodule
module 	ryg_ctl(clk_1, clk_2, reset, day_night, g1_cnt, g1_en, light_led);


input	clk_1, clk_2, reset, day_night;
input	[7:0]g1_cnt;
output	g1_en;
output	[5:0]light_led;
reg 	g1_en;
reg		[5:0]light_led;
reg		[2:0]mode;

always@(posedge clk_1 or posedge reset) 
begin
	if (reset)
		begin
		light_led	= 6'b001_100;
		mode 		= 3'b0;
		g1_en 		= 1'b0;
		end
	else if(day_night == 1'b1)
		case(mode)
		3'd0: 
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		3'd1:
			begin
			light_led	= 6'b010_100;
			if (g1_cnt == 8'b0000_0110)

				mode 	= mode + 3'b1; 
			end	

		3'd2:
			begin
			light_led	= 6'b100_100;  
			if(g1_cnt == 8'b0000_0000) 
				begin
				g1_en 	= 1'b0;
				mode 	= mode + 3'b1; 
				end

		end
		3'd3: 
			begin
			light_led	= 6'b100_001;
			g1_en = 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode+ 3'b1; 
			end

		3'd4:
			begin
			light_led	= 6'b100_010;
			if (g1_cnt == 8'b0000_0110)
				begin
				mode 	= mode + 3'b1; 

				end

			end
		3'd5:
			begin
			light_led	= 6'b100_100;  
			if(g1_cnt == 8'b0000_0000) 
				begin
				g1_en 	= 1'b0;
				mode 	= 3'b0; 
				end
			end
		default:
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			if(g1_cnt == 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		endcase

	else if(day_night == 1'b0)begin
		light_led= {{1'b0, clk_2, 1'b0}, {1'b0, clk_2, 1'b0}};
		g1_en=1'b0;



		end
end
endmodule