data/full_repos/permissive/447976230/fpga/usrp1/megacells/addsub16_bb.v
data/verilator_xmls/33c81b5f-8c9b-4fe7-b074-eb4c01373549.xml
module addsub16 (
	add_sub,
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result);

	input	  add_sub;
	input	[15:0]  dataa;
	input	[15:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[15:0]  result;

endmodule
module addsub16 (
	add_sub,
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result);


	input	  add_sub;
	input	[15:0]  dataa;
	input	[15:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[15:0]  result;

endmodule