data/full_repos/permissive/439635488/TRY_BEEP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/439635488/TRY_BEEP.v:10: Signal definition not found, creating implicitly: \'clk_div\'\ndivfreq_bp dd0 (clk, clk_div);\n                     ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/439635488/TRY_BEEP.v:40: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                  : ... In instance TRY_BEEP.dd0\n          Count <= 25\'b0;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module divfreq_bp(input CLK, output reg CLK_time);
  reg [25:0] Count;
  initial
    begin
      CLK_time = 0;
	 end	
		
  always @(posedge CLK)
    begin
      if(Count > 2500000)
        begin
          Count <= 25'b0;
          CLK_time <= ~CLK_time;
        end
      else
        Count <= Count + 1'b1;
    end
endmodule
module divfreq_bp(input CLK, output reg CLK_time);

  reg [25:0] Count;
  initial
    begin
      CLK_time = 0;
	 end	
		
  always @(posedge CLK)
    begin
      if(Count > 2500000)
        begin
          Count <= 25'b0;
          CLK_time <= ~CLK_time;
        end
      else
        Count <= Count + 1'b1;
    end
endmodule