data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:19: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n            counter_p   <= 16\'b0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:24: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n                counter_p   <= 16\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:32: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n                counter_p   <= 16\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:42: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n            counter_n   <= 16\'b0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:47: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n                counter_n   <= 16\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_odd.v:55: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance clk_div_odd\n                counter_n   <= 16\'b0;\n                            ^~\n%Error: Exiting due to 6 warning(s)\n'
module clk_div_odd (
    input   wire    clk,
    input   wire    rst_n,

    output  wire    clk_div
);

    parameter DIV   = 15;
    parameter DIV_W = 4;

    reg [DIV_W-1:0] counter_p, counter_n;
    reg clk_div_p, clk_div_n;

    always @(posedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter_p   <= 16'b0;
            clk_div_p   <= 1'b0;
        end 
        else if (clk_div_p == 0) begin
            if (counter_p == DIV/2) begin
                counter_p   <= 16'b0;
                clk_div_p   <= ~clk_div_p;
            end
            else
                counter_p   <= counter_p + 1;
        end
        else begin
            if (counter_p == DIV/2-1) begin
                counter_p   <= 16'b0;
                clk_div_p   <= ~clk_div_p;
            end
            else
                counter_p   <= counter_p + 1;
        end
    end

    always @(negedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter_n   <= 16'b0;
            clk_div_n   <= 1'b0;
        end
        else if (clk_div_n == 0) begin
            if (counter_n == DIV/2) begin
                counter_n   <= 16'b0;
                clk_div_n   <= ~clk_div_n;
            end
            else
                counter_n   <= counter_n + 1;
        end
        else begin
            if (counter_n == DIV/2-1) begin
                counter_n   <= 16'b0;
                clk_div_n   <= ~clk_div_n;
            end
            else
                counter_n   <= counter_n + 1;
        end
    end

    assign clk_div = clk_div_p | clk_div_n;

endmodule
module clk_div_odd (
    input   wire    clk,
    input   wire    rst_n,

    output  wire    clk_div
);


    parameter DIV   = 15;
    parameter DIV_W = 4;

    reg [DIV_W-1:0] counter_p, counter_n;
    reg clk_div_p, clk_div_n;

    always @(posedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter_p   <= 16'b0;
            clk_div_p   <= 1'b0;
        end 
        else if (clk_div_p == 0) begin
            if (counter_p == DIV/2) begin
                counter_p   <= 16'b0;
                clk_div_p   <= ~clk_div_p;
            end
            else
                counter_p   <= counter_p + 1;
        end
        else begin
            if (counter_p == DIV/2-1) begin
                counter_p   <= 16'b0;
                clk_div_p   <= ~clk_div_p;
            end
            else
                counter_p   <= counter_p + 1;
        end
    end

    always @(negedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter_n   <= 16'b0;
            clk_div_n   <= 1'b0;
        end
        else if (clk_div_n == 0) begin
            if (counter_n == DIV/2) begin
                counter_n   <= 16'b0;
                clk_div_n   <= ~clk_div_n;
            end
            else
                counter_n   <= counter_n + 1;
        end
        else begin
            if (counter_n == DIV/2-1) begin
                counter_n   <= 16'b0;
                clk_div_n   <= ~clk_div_n;
            end
            else
                counter_n   <= counter_n + 1;
        end
    end

    assign clk_div = clk_div_p | clk_div_n;

endmodule