data/full_repos/permissive/520695407/sim/tb-buffer.sv
1: b'%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:8: Unsupported: event data types\n    input event start,\n          ^~~~~\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:9: Unsupported: event data types\n    input event done\n          ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/520695407/sim/tb-buffer.sv:18: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/520695407/sim/tb-buffer.sv:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:47: Unsupported: wait statements\n    wait (start.triggered);\n    ^~~~\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:51: Unsupported or unknown PLI call: $urandom_range\n    gen_addr = $urandom_range(0, RAM_DEPTH-1);\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:52: Unsupported or unknown PLI call: $urandom_range\n    gen_data = $urandom_range(0, DATA_RANGE-1);\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:56: syntax error, unexpected \'@\'\n    @ (posedge clk);\n    ^\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:61: syntax error, unexpected \'@\'\n    @ (posedge clk);\n    ^\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:66: syntax error, unexpected \'@\'\n    @ (posedge clk);\n    ^\n%Error: data/full_repos/permissive/520695407/sim/tb-buffer.sv:70: syntax error, unexpected ->\n    ->done;\n    ^~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_buffer #(
    parameter DATA_RANGE = 4096,
    parameter RAM_DEPTH = 1024
)(
    input event start,
    input event done
);
  logic clk     = 0,
	en      = 0,
	swap_en = 0,
	w_en    = 0;
  logic [9:0]  addr;
  logic [11:0] din, dout;

  always #10 clk <= ~clk;

  buffer dut(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(w_en),
    .w_addr(addr),
    .r_addr(addr),
    .din(din),
    .dout(dout)
  );

  task automatic mem_status(input string op);
    logic [11:0] a_out, b_out;
    logic ptr;
    #1;
    a_out = dut.buff_a.bram[addr];
    b_out = dut.buff_b.bram[addr];
    ptr = dut.cur_buff;
    $display("%s\t%h\t%h\t%h\t%h\t%b", op, addr, a_out, b_out, dout, ptr);
  endtask

  logic [9:0] gen_addr;
  logic [11:0] gen_data;
  string buff, status;
  logic [9:0] word_a, word_b;

  initial begin
    wait (start.triggered);
    $display("=== BUFFER TEST STARTED ===");
    $display("Test\tAddr\tBuff A\tBuff B\tOutput\tBuff Ptr");

    gen_addr = $urandom_range(0, RAM_DEPTH-1);
    gen_data = $urandom_range(0, DATA_RANGE-1);
    addr = gen_addr;
    din = gen_data;

    @ (posedge clk);
    en <= 1;
    w_en <= 1;
    mem_status("Write");

    @ (posedge clk);
    w_en <= 0;
    swap_en <= 1;
    mem_status("Swap");

    @ (posedge clk);
    swap_en <= 0;
    mem_status("Hold En");
   $display("=== BUFFER TEST FINISHED ===");
    ->done;
  end
endmodule
module tb_buffer #(
    parameter DATA_RANGE = 4096,
    parameter RAM_DEPTH = 1024
)(
    input event start,
    input event done
);

  logic clk     = 0,
	en      = 0,
	swap_en = 0,
	w_en    = 0;
  logic [9:0]  addr;
  logic [11:0] din, dout;

  always #10 clk <= ~clk;

  buffer dut(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(w_en),
    .w_addr(addr),
    .r_addr(addr),
    .din(din),
    .dout(dout)
  );

  task automatic mem_status(input string op);
    logic [11:0] a_out, b_out;
    logic ptr;
    #1;
    a_out = dut.buff_a.bram[addr];
    b_out = dut.buff_b.bram[addr];
    ptr = dut.cur_buff;
    $display("%s\t%h\t%h\t%h\t%h\t%b", op, addr, a_out, b_out, dout, ptr);
  endtask

  logic [9:0] gen_addr;
  logic [11:0] gen_data;
  string buff, status;
  logic [9:0] word_a, word_b;

  initial begin
    wait (start.triggered);
    $display("=== BUFFER TEST STARTED ===");
    $display("Test\tAddr\tBuff A\tBuff B\tOutput\tBuff Ptr");

    gen_addr = $urandom_range(0, RAM_DEPTH-1);
    gen_data = $urandom_range(0, DATA_RANGE-1);
    addr = gen_addr;
    din = gen_data;

    @ (posedge clk);
    en <= 1;
    w_en <= 1;
    mem_status("Write");

    @ (posedge clk);
    w_en <= 0;
    swap_en <= 1;
    mem_status("Swap");

    @ (posedge clk);
    swap_en <= 0;
    mem_status("Hold En");
   $display("=== BUFFER TEST FINISHED ===");
    ->done;
  end
endmodule