data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #100_000_000;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_HALF_PERIOD);\n ^\n%Error: data/full_repos/permissive/531063930/src/user_module_341521390605697619_tb.v:14: Cannot find file containing module: \'user_module_341521390605697619\'\nuser_module_341521390605697619 UUT (.io_in(io_in), .io_out(io_out));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531063930/src,data/full_repos/permissive/531063930/user_module_341521390605697619\n             data/full_repos/permissive/531063930/src,data/full_repos/permissive/531063930/user_module_341521390605697619.v\n             data/full_repos/permissive/531063930/src,data/full_repos/permissive/531063930/user_module_341521390605697619.sv\n             user_module_341521390605697619\n             user_module_341521390605697619.v\n             user_module_341521390605697619.sv\n             obj_dir/user_module_341521390605697619\n             obj_dir/user_module_341521390605697619.v\n             obj_dir/user_module_341521390605697619.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module user_module_341521390605697619_tb;

wire [7:0] io_in;
wire [7:0] io_out;

reg clk;
reg reset = 0;

assign io_in = {6'b0, reset, clk};

user_module_341521390605697619 UUT (.io_in(io_in), .io_out(io_out));






initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
parameter TCLK = 2*CLK_HALF_PERIOD;
always begin
    clk = 1'b1;
    #(CLK_HALF_PERIOD);
    clk = 1'b0;
    #(CLK_HALF_PERIOD);
end

initial 
begin
	#40
	reset = 1;
	#(CLK_HALF_PERIOD);
	reset = 0;
end
























endmodule
module user_module_341521390605697619_tb;


wire [7:0] io_in;
wire [7:0] io_out;

reg clk;
reg reset = 0;

assign io_in = {6'b0, reset, clk};

user_module_341521390605697619 UUT (.io_in(io_in), .io_out(io_out));






initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
parameter TCLK = 2*CLK_HALF_PERIOD;
always begin
    clk = 1'b1;
    #(CLK_HALF_PERIOD);
    clk = 1'b0;
    #(CLK_HALF_PERIOD);
end

initial 
begin
	#40
	reset = 1;
	#(CLK_HALF_PERIOD);
	reset = 0;
end
























endmodule