data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/cachelib/v_rtl/dut_And_1Ux1U_1U_1.v
data/verilator_xmls/7e5025b4-a07e-4c4d-8ad3-fade3d62da6a.xml
module dut_And_1Ux1U_1U_1 (
	in2,
	in1,
	out1
	);
input  in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = 
	(in2)
	&(in1);

assign out1 = asc001;
endmodule
module dut_And_1Ux1U_1U_1 (
	in2,
	in1,
	out1
	);

input  in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = 
	(in2)
	&(in1);

assign out1 = asc001;
endmodule