data/full_repos/permissive/482720319/data_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482720319/data_mem.v:16: Bit extraction of array[100:0] requires 7 bit index, not 16 bits.\n                                                                  : ... In instance Datamemory\n                  Memory[Address] <= Writedata;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482720319/data_mem.v:22: Bit extraction of array[100:0] requires 7 bit index, not 16 bits.\n                                                                  : ... In instance Datamemory\n                  Memdata <= (MemRead) ? Memory[Address] : 16\'bx;\n                                               ^\n%Error: Exiting due to 2 warning(s)\n'
module Datamemory(Address, Writedata, MemRead, MemWrite, Memdata);
      
      input [15:0] Address;
      input [15:0] Writedata;
      input MemWrite, MemRead;
      output reg [15:0] Memdata;

      reg [15:0] Memory [0:100];
      
      initial begin
            $readmemh("mem_init.mem", Memory, 16'h0000, 16'd0100);
      end

      always @(*) begin
            if(MemWrite) begin
                  Memory[Address] <= Writedata;
                  $writememh("mem_fin.mem", Memory);
            end 
            
            
            if (MemRead)
                  Memdata <= (MemRead) ? Memory[Address] : 16'bx;
      end

endmodule
module Datamemory(Address, Writedata, MemRead, MemWrite, Memdata);

      
      input [15:0] Address;
      input [15:0] Writedata;
      input MemWrite, MemRead;
      output reg [15:0] Memdata;

      reg [15:0] Memory [0:100];
      
      initial begin
            $readmemh("mem_init.mem", Memory, 16'h0000, 16'd0100);
      end

      always @(*) begin
            if(MemWrite) begin
                  Memory[Address] <= Writedata;
                  $writememh("mem_fin.mem", Memory);
            end 
            
            
            if (MemRead)
                  Memdata <= (MemRead) ? Memory[Address] : 16'bx;
      end

endmodule