data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v
1: b'%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:12: Cannot find include file: Bitlet_Defs.vh\n`include "Bitlet_Defs.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.v\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.sv\n             Bitlet_Defs.vh\n             Bitlet_Defs.vh.v\n             Bitlet_Defs.vh.sv\n             obj_dir/Bitlet_Defs.vh\n             obj_dir/Bitlet_Defs.vh.v\n             obj_dir/Bitlet_Defs.vh.sv\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:19: Define or directive not defined: \'`Wid_acc\'\n    input       [`Wid_acc-1:0]  Aacc,\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:21: Define or directive not defined: \'`Wid_exs\'\n    input       [`Wid_exs-1:0]  Emax,\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:23: Define or directive not defined: \'`Wid_bin\'\n    output reg  [`Wid_bin-1:0]  res\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:28: Define or directive not defined: \'`Wid_acc\'\nlocalparam  Wid_cnt = $clog2(`Wid_acc);\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nlocalparam  Wid_cnt = $clog2(`Wid_acc);\n                                     ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:31: Define or directive not defined: \'`Wid_acc\'\nassign  Aacc_sig    = Aacc[`Wid_acc-1];\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:34: Define or directive not defined: \'`Wid_exs\'\nreg     [`Wid_exs:0]  Emax_correct;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:34: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg     [`Wid_exs:0]  Emax_correct;\n                 ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:41: Define or directive not defined: \'`Const_bias\'\n        Emax_correct    <= $signed({1\'b0, Emax}) - `Const_bias - `Const_frac;\n                                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:41: Define or directive not defined: \'`Const_frac\'\n        Emax_correct    <= $signed({1\'b0, Emax}) - `Const_bias - `Const_frac;\n                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        Emax_correct    <= $signed({1\'b0, Emax}) - `Const_bias - `Const_frac;\n                                                                            ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:45: Define or directive not defined: \'`Wid_acc\'\nreg     [`Wid_acc-1:0]  Aacc_abs;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:71: Define or directive not defined: \'`Wid_acc\'\nBitlet_FindMSB #(.W(`Wid_acc)) UFINDMSB\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:101: Define or directive not defined: \'`Wid_exs\'\nwire    [`Wid_exs:0]    tmp_exp_norm;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:101: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire    [`Wid_exs:0]    tmp_exp_norm;\n                 ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:102: Define or directive not defined: \'`Wid_abs\'\nwire    [`Wid_abs-1:0]  tmp_abs_norm;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:103: Define or directive not defined: \'`Wid_exp\'\nreg     [`Wid_exp-1:0]  exp_norm;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:104: Define or directive not defined: \'`Wid_exs\'\nreg     [`Wid_exs:0]    abs_sa;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:104: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg     [`Wid_exs:0]    abs_sa;\n                 ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:105: Define or directive not defined: \'`Wid_abs\'\nreg     [`Wid_abs-1:0]  abs_norm;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:110: Define or directive not defined: \'`Wid_man\'\nassign  tmp_abs_norm    = {Aacc_abs, `Wid_man\'b0} >> cnt;\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:123: Define or directive not defined: \'`Const_emin\'\n        exp_norm    <= (($signed(tmp_exp_norm)<`Const_emin)||zero) ? \'b0 : tmp_exp_norm[0+:`Wid_exp];\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:123: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        exp_norm    <= (($signed(tmp_exp_norm)<`Const_emin)||zero) ? \'b0 : tmp_exp_norm[0+:`Wid_exp];\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:123: Define or directive not defined: \'`Wid_exp\'\n        exp_norm    <= (($signed(tmp_exp_norm)<`Const_emin)||zero) ? \'b0 : tmp_exp_norm[0+:`Wid_exp];\n                                                                                           ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:124: Define or directive not defined: \'`Const_emin\'\n        abs_sa      <= (($signed(tmp_exp_norm)<`Const_emin)&&!zero) ? (1-$signed(tmp_exp_norm)) : \'b0;\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:124: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        abs_sa      <= (($signed(tmp_exp_norm)<`Const_emin)&&!zero) ? (1-$signed(tmp_exp_norm)) : \'b0;\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:125: Define or directive not defined: \'`Wid_abs\'\n        abs_norm    <= (zero) ? \'b0 : tmp_abs_norm[0+:`Wid_abs];\n                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        abs_norm    <= (zero) ? \'b0 : tmp_abs_norm[0+:`Wid_abs];\n                                                              ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:126: Define or directive not defined: \'`Const_emax\'\n        fp_inf      <= (($signed(tmp_exp_norm)>`Const_emax)&&(!zero)) ? 1\'b1 : 1\'b0;\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        fp_inf      <= (($signed(tmp_exp_norm)>`Const_emax)&&(!zero)) ? 1\'b1 : 1\'b0;\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:139: Define or directive not defined: \'`Wid_abs\'\nwire    [`Wid_abs-1:0]  tmp_final_abs;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:140: Define or directive not defined: \'`Wid_man\'\nreg     [`Wid_man-1:0]  final_man;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:141: Define or directive not defined: \'`Wid_exp\'\nreg     [`Wid_exp-1:0]  final_exp;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:147: Define or directive not defined: \'`Wid_man\'\n    final_man       = (zero|fp_inf) ? \'b0 : tmp_final_abs[0+:`Wid_man];\n                                                             ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:147: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    final_man       = (zero|fp_inf) ? \'b0 : tmp_final_abs[0+:`Wid_man];\n                                                                     ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_PackFloat.v:148: Define or directive not defined: \'`Const_emax\'\n    final_exp       = (fp_inf) ? (`Const_emax+1) : exp_norm;\n                                  ^~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module Bitlet_PackFloat
(
    input                       clk,
    input                       rst_n,
    input                       Aacc_vld,
    input       [`Wid_acc-1:0]  Aacc,
    input                       Emax_vld,
    input       [`Wid_exs-1:0]  Emax,
    output reg                  res_vld,
    output reg  [`Wid_bin-1:0]  res
);

integer i;

localparam  Wid_cnt = $clog2(`Wid_acc);

wire    Aacc_sig;
assign  Aacc_sig    = Aacc[`Wid_acc-1];


reg     [`Wid_exs:0]  Emax_correct;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Emax_correct    <= 'b0;
    else if (Emax_vld)
        Emax_correct    <= $signed({1'b0, Emax}) - `Const_bias - `Const_frac;
end


reg     [`Wid_acc-1:0]  Aacc_abs;
reg                     abs_vld;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Aacc_abs <= 'b0;
    else if (Aacc_vld)
        Aacc_abs <= (Aacc_sig) ? (~Aacc+1) : Aacc;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        abs_vld <= 1'b0;
    else if (abs_vld!=Aacc_vld)
        abs_vld <= Aacc_vld;
end


wire                    tmp_zero;
wire    [Wid_cnt-1:0]   tmp_cnt;
reg                     zero;
reg     [Wid_cnt-1:0]   cnt;
reg                     cnt_vld;

Bitlet_FindMSB #(.W(`Wid_acc)) UFINDMSB
(
    .DI(Aacc_abs),
    .zero(tmp_zero),
    .cnt(tmp_cnt)
);

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        zero    <= 'b0;
        cnt     <= 'b0;
    end
    else if (abs_vld)
    begin
        zero    <= tmp_zero;
        cnt     <= tmp_cnt;
    end
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        cnt_vld <= 'b0;
    else if (cnt_vld!=abs_vld)
        cnt_vld <= abs_vld;
end


wire    [`Wid_exs:0]    tmp_exp_norm;
wire    [`Wid_abs-1:0]  tmp_abs_norm;
reg     [`Wid_exp-1:0]  exp_norm;
reg     [`Wid_exs:0]    abs_sa;
reg     [`Wid_abs-1:0]  abs_norm;
reg                     fp_inf;
reg                     norm_vld;

assign  tmp_exp_norm    = $signed(Emax_correct) + cnt;
assign  tmp_abs_norm    = {Aacc_abs, `Wid_man'b0} >> cnt;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        exp_norm    <= 'b0;
        abs_sa      <= 'b0;
        abs_norm    <= 'b0;
        fp_inf      <= 'b0;
    end
    else if (cnt_vld)
    begin
        exp_norm    <= (($signed(tmp_exp_norm)<`Const_emin)||zero) ? 'b0 : tmp_exp_norm[0+:`Wid_exp];
        abs_sa      <= (($signed(tmp_exp_norm)<`Const_emin)&&!zero) ? (1-$signed(tmp_exp_norm)) : 'b0;
        abs_norm    <= (zero) ? 'b0 : tmp_abs_norm[0+:`Wid_abs];
        fp_inf      <= (($signed(tmp_exp_norm)>`Const_emax)&&(!zero)) ? 1'b1 : 1'b0;
    end
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        norm_vld    <= 1'b0;
    else if (norm_vld!=cnt_vld)
        norm_vld    <= cnt_vld;
end


wire    [`Wid_abs-1:0]  tmp_final_abs;
reg     [`Wid_man-1:0]  final_man;
reg     [`Wid_exp-1:0]  final_exp;

assign  tmp_final_abs   = abs_norm >> abs_sa;

always @(*)
begin
    final_man       = (zero|fp_inf) ? 'b0 : tmp_final_abs[0+:`Wid_man];
    final_exp       = (fp_inf) ? (`Const_emax+1) : exp_norm;
end


always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        res <= 'b0;
    else if (norm_vld)
        res <= {Aacc_sig, final_exp, final_man};
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        res_vld <= 1'b0;
    else if (res_vld!=norm_vld)
        res_vld <= norm_vld;
end

endmodule
module Bitlet_PackFloat
(
    input                       clk,
    input                       rst_n,
    input                       Aacc_vld,
    input       [`Wid_acc-1:0]  Aacc,
    input                       Emax_vld,
    input       [`Wid_exs-1:0]  Emax,
    output reg                  res_vld,
    output reg  [`Wid_bin-1:0]  res
);


integer i;

localparam  Wid_cnt = $clog2(`Wid_acc);

wire    Aacc_sig;
assign  Aacc_sig    = Aacc[`Wid_acc-1];


reg     [`Wid_exs:0]  Emax_correct;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Emax_correct    <= 'b0;
    else if (Emax_vld)
        Emax_correct    <= $signed({1'b0, Emax}) - `Const_bias - `Const_frac;
end


reg     [`Wid_acc-1:0]  Aacc_abs;
reg                     abs_vld;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Aacc_abs <= 'b0;
    else if (Aacc_vld)
        Aacc_abs <= (Aacc_sig) ? (~Aacc+1) : Aacc;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        abs_vld <= 1'b0;
    else if (abs_vld!=Aacc_vld)
        abs_vld <= Aacc_vld;
end


wire                    tmp_zero;
wire    [Wid_cnt-1:0]   tmp_cnt;
reg                     zero;
reg     [Wid_cnt-1:0]   cnt;
reg                     cnt_vld;

Bitlet_FindMSB #(.W(`Wid_acc)) UFINDMSB
(
    .DI(Aacc_abs),
    .zero(tmp_zero),
    .cnt(tmp_cnt)
);

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        zero    <= 'b0;
        cnt     <= 'b0;
    end
    else if (abs_vld)
    begin
        zero    <= tmp_zero;
        cnt     <= tmp_cnt;
    end
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        cnt_vld <= 'b0;
    else if (cnt_vld!=abs_vld)
        cnt_vld <= abs_vld;
end


wire    [`Wid_exs:0]    tmp_exp_norm;
wire    [`Wid_abs-1:0]  tmp_abs_norm;
reg     [`Wid_exp-1:0]  exp_norm;
reg     [`Wid_exs:0]    abs_sa;
reg     [`Wid_abs-1:0]  abs_norm;
reg                     fp_inf;
reg                     norm_vld;

assign  tmp_exp_norm    = $signed(Emax_correct) + cnt;
assign  tmp_abs_norm    = {Aacc_abs, `Wid_man'b0} >> cnt;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        exp_norm    <= 'b0;
        abs_sa      <= 'b0;
        abs_norm    <= 'b0;
        fp_inf      <= 'b0;
    end
    else if (cnt_vld)
    begin
        exp_norm    <= (($signed(tmp_exp_norm)<`Const_emin)||zero) ? 'b0 : tmp_exp_norm[0+:`Wid_exp];
        abs_sa      <= (($signed(tmp_exp_norm)<`Const_emin)&&!zero) ? (1-$signed(tmp_exp_norm)) : 'b0;
        abs_norm    <= (zero) ? 'b0 : tmp_abs_norm[0+:`Wid_abs];
        fp_inf      <= (($signed(tmp_exp_norm)>`Const_emax)&&(!zero)) ? 1'b1 : 1'b0;
    end
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        norm_vld    <= 1'b0;
    else if (norm_vld!=cnt_vld)
        norm_vld    <= cnt_vld;
end


wire    [`Wid_abs-1:0]  tmp_final_abs;
reg     [`Wid_man-1:0]  final_man;
reg     [`Wid_exp-1:0]  final_exp;

assign  tmp_final_abs   = abs_norm >> abs_sa;

always @(*)
begin
    final_man       = (zero|fp_inf) ? 'b0 : tmp_final_abs[0+:`Wid_man];
    final_exp       = (fp_inf) ? (`Const_emax+1) : exp_norm;
end


always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        res <= 'b0;
    else if (norm_vld)
        res <= {Aacc_sig, final_exp, final_man};
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        res_vld <= 1'b0;
    else if (res_vld!=norm_vld)
        res_vld <= norm_vld;
end

endmodule