data/full_repos/permissive/472097485/Chu05/AltDebounce_01/AltDebounce.v
1: b"%Error: data/full_repos/permissive/472097485/Chu05/AltDebounce_01/AltDebounce.v:18: Cannot find file containing module: 'ModMCounter'\n ModMCounter #( COUNT, BITS ) ms20Clk( clk, reset, timerOn, count );\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/ModMCounter\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/ModMCounter.v\n             data/full_repos/permissive/472097485/Chu05/AltDebounce_01,data/full_repos/permissive/472097485/ModMCounter.sv\n             ModMCounter\n             ModMCounter.v\n             ModMCounter.sv\n             obj_dir/ModMCounter\n             obj_dir/ModMCounter.v\n             obj_dir/ModMCounter.sv\n%Error: Exiting due to 1 error(s)\n"
module AltDebounce #( parameter COUNT = 1, parameter BITS = 1 )( input clk, input reset, input sig, output db );


	localparam ZERO = 2'b00;
	localparam ZERO_WAIT = 2'b01;
	localparam ONE = 2'b10;
	localparam ONE_WAIT = 2'b11;
	
	wire [BITS-1:0] count;
	wire timerOn;
	reg [1:0] state, next;
	
	assign timerOn = state == ZERO_WAIT || state == ONE_WAIT;

	ModMCounter #( COUNT, BITS ) ms20Clk( clk, reset, timerOn, count );


	always @( posedge clk, posedge reset )
	begin
		if( reset )
			state = ZERO;
		else
			state = next;
	end
	

	always @*
	begin
		next = state;
		case (state)
			ZERO		: if( sig ) next = ONE_WAIT;
			ZERO_WAIT: if( 0 == count ) next = sig ? ONE_WAIT : ZERO;
			ONE		: if( ~sig ) next = ZERO_WAIT;
			ONE_WAIT : if( 0 == count ) next = sig ? ONE : ZERO_WAIT;
		endcase
	end
	
	assign db = state == ONE || state == ONE_WAIT;

endmodule
module AltDebounce #( parameter COUNT = 1, parameter BITS = 1 )( input clk, input reset, input sig, output db );



	localparam ZERO = 2'b00;
	localparam ZERO_WAIT = 2'b01;
	localparam ONE = 2'b10;
	localparam ONE_WAIT = 2'b11;
	
	wire [BITS-1:0] count;
	wire timerOn;
	reg [1:0] state, next;
	
	assign timerOn = state == ZERO_WAIT || state == ONE_WAIT;

	ModMCounter #( COUNT, BITS ) ms20Clk( clk, reset, timerOn, count );


	always @( posedge clk, posedge reset )
	begin
		if( reset )
			state = ZERO;
		else
			state = next;
	end
	

	always @*
	begin
		next = state;
		case (state)
			ZERO		: if( sig ) next = ONE_WAIT;
			ZERO_WAIT: if( 0 == count ) next = sig ? ONE_WAIT : ZERO;
			ONE		: if( ~sig ) next = ZERO_WAIT;
			ONE_WAIT : if( 0 == count ) next = sig ? ONE : ZERO_WAIT;
		endcase
	end
	
	assign db = state == ONE || state == ONE_WAIT;

endmodule