data/full_repos/permissive/463204869/units/mem/source/rtl/verilog/xpm_sp_ram.v
1: b"%Error: data/full_repos/permissive/463204869/units/mem/source/rtl/verilog/xpm_sp_ram.v:36: Cannot find file containing module: 'xpm_memory_spram'\n    xpm_memory_spram #(\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_spram\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_spram.v\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_spram.sv\n             xpm_memory_spram\n             xpm_memory_spram.v\n             xpm_memory_spram.sv\n             obj_dir/xpm_memory_spram\n             obj_dir/xpm_memory_spram.v\n             obj_dir/xpm_memory_spram.sv\n%Error: Exiting due to 1 error(s)\n"
module xpm_sp_ram #(
    parameter MEM_TYPE = "auto",
    parameter MEM_DATAWIDTH = 128,
    parameter MEM_ADDRWIDTH = 14
)
(
    input   wire                              clk,
    input   wire                              reset,

    input   wire                              en,
    input   wire    [(MEM_DATAWIDTH+7)/8-1:0] we,
    input   wire          [MEM_ADDRWIDTH-1:0] addr,
    input   wire          [MEM_DATAWIDTH-1:0] din,
    output  wire          [MEM_DATAWIDTH-1:0] dout
);

    localparam MEM_DATAWIDTH_BYTEALIGN = ((MEM_DATAWIDTH+7)/8) << 3;

    wire [MEM_DATAWIDTH_BYTEALIGN-1:0] din_int;
    wire [MEM_DATAWIDTH_BYTEALIGN-1:0] dout_int;

    generate
    if (MEM_DATAWIDTH_BYTEALIGN == MEM_DATAWIDTH) begin: datawidth_aligned
        assign din_int = din;
    end else begin: datawidth_notaligned
        assign din_int = {{(MEM_DATAWIDTH_BYTEALIGN-MEM_DATAWIDTH){1'b0}}, din};
    end
    endgenerate

    assign dout = dout_int[MEM_DATAWIDTH-1:0];




    xpm_memory_spram #(
        .ADDR_WIDTH_A(MEM_ADDRWIDTH),
        .AUTO_SLEEP_TIME(0),
        .BYTE_WRITE_WIDTH_A(8),
        .CASCADE_HEIGHT(0),
        .ECC_MODE("no_ecc"),
        .MEMORY_INIT_FILE("none"),
        .MEMORY_INIT_PARAM("0"),
        .MEMORY_OPTIMIZATION("true"),
        .MEMORY_PRIMITIVE(MEM_TYPE),
        .MEMORY_SIZE(MEM_DATAWIDTH_BYTEALIGN*(1<<MEM_ADDRWIDTH)),
        .MESSAGE_CONTROL(0),
        .READ_DATA_WIDTH_A(MEM_DATAWIDTH_BYTEALIGN),
        .READ_LATENCY_A(1),
        .READ_RESET_VALUE_A("0"),
        .RST_MODE_A("SYNC"),
        .SIM_ASSERT_CHK(0),
        .USE_MEM_INIT(0),
        .WAKEUP_TIME("disable_sleep"),
        .WRITE_DATA_WIDTH_A(MEM_DATAWIDTH_BYTEALIGN),
        .WRITE_MODE_A("read_first")
    )
    xpm_memory_spram_inst (
        .dbiterra(),

        .douta(dout_int),
        .sbiterra(),

        .addra(addr),
        .clka(clk),
        .dina(din_int),
        .ena(en),


        .injectdbiterra(1'b0),


        .injectsbiterra(1'b0),


        .regcea(1'b1),
        .rsta(reset),


        .sleep(1'b0),
        .wea(we)





    );


endmodule
module xpm_sp_ram #(
    parameter MEM_TYPE = "auto",
    parameter MEM_DATAWIDTH = 128,
    parameter MEM_ADDRWIDTH = 14
)
(
    input   wire                              clk,
    input   wire                              reset,

    input   wire                              en,
    input   wire    [(MEM_DATAWIDTH+7)/8-1:0] we,
    input   wire          [MEM_ADDRWIDTH-1:0] addr,
    input   wire          [MEM_DATAWIDTH-1:0] din,
    output  wire          [MEM_DATAWIDTH-1:0] dout
);


    localparam MEM_DATAWIDTH_BYTEALIGN = ((MEM_DATAWIDTH+7)/8) << 3;

    wire [MEM_DATAWIDTH_BYTEALIGN-1:0] din_int;
    wire [MEM_DATAWIDTH_BYTEALIGN-1:0] dout_int;

    generate
    if (MEM_DATAWIDTH_BYTEALIGN == MEM_DATAWIDTH) begin: datawidth_aligned
        assign din_int = din;
    end else begin: datawidth_notaligned
        assign din_int = {{(MEM_DATAWIDTH_BYTEALIGN-MEM_DATAWIDTH){1'b0}}, din};
    end
    endgenerate

    assign dout = dout_int[MEM_DATAWIDTH-1:0];




    xpm_memory_spram #(
        .ADDR_WIDTH_A(MEM_ADDRWIDTH),
        .AUTO_SLEEP_TIME(0),
        .BYTE_WRITE_WIDTH_A(8),
        .CASCADE_HEIGHT(0),
        .ECC_MODE("no_ecc"),
        .MEMORY_INIT_FILE("none"),
        .MEMORY_INIT_PARAM("0"),
        .MEMORY_OPTIMIZATION("true"),
        .MEMORY_PRIMITIVE(MEM_TYPE),
        .MEMORY_SIZE(MEM_DATAWIDTH_BYTEALIGN*(1<<MEM_ADDRWIDTH)),
        .MESSAGE_CONTROL(0),
        .READ_DATA_WIDTH_A(MEM_DATAWIDTH_BYTEALIGN),
        .READ_LATENCY_A(1),
        .READ_RESET_VALUE_A("0"),
        .RST_MODE_A("SYNC"),
        .SIM_ASSERT_CHK(0),
        .USE_MEM_INIT(0),
        .WAKEUP_TIME("disable_sleep"),
        .WRITE_DATA_WIDTH_A(MEM_DATAWIDTH_BYTEALIGN),
        .WRITE_MODE_A("read_first")
    )
    xpm_memory_spram_inst (
        .dbiterra(),

        .douta(dout_int),
        .sbiterra(),

        .addra(addr),
        .clka(clk),
        .dina(din_int),
        .ena(en),


        .injectdbiterra(1'b0),


        .injectsbiterra(1'b0),


        .regcea(1'b1),
        .rsta(reset),


        .sleep(1'b0),
        .wea(we)





    );


endmodule