data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:33: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:60: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]  jbi_iob_data;\n          ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:67: Define or directive not defined: \'`JBI_IOB_MONDO_TRG_WIDTH\'\n   output [`JBI_IOB_MONDO_TRG_WIDTH-1:0] mondo_target;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:68: Define or directive not defined: \'`JBI_IOB_MONDO_SRC_WIDTH\'\n   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0] mondo_source;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:74: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0]   vldreg_next;\n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:75: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0]   vldreg;\n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:76: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;\n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:76: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;\n                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:76: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:77: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;\n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:77: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;\n                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:77: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:87: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   assign   vldreg_next = {vldreg[`JBI_IOB_MONDO_BUS_CYCLE-2:0],jbi_iob_vld};\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:89: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   dffrle_ns #(`JBI_IOB_MONDO_BUS_CYCLE) vldreg_ff (.din(vldreg_next),\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:95: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   assign   datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],\n                                    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:95: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   assign   datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],\n                                                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:95: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   assign   datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],\n                                                              ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:98: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:98: syntax error, unexpected \'*\', expecting \')\'\n   dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),\n                                       ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:98: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_CYCLE\'\n   dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),\n                                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:111: Define or directive not defined: \'`JBI_IOB_MONDO_TRG_HI\'\n   assign   mondo_target = datareg[`JBI_IOB_MONDO_TRG_HI+128:`JBI_IOB_MONDO_TRG_LO+128];\n                                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:111: Define or directive not defined: \'`JBI_IOB_MONDO_TRG_LO\'\n   assign   mondo_target = datareg[`JBI_IOB_MONDO_TRG_HI+128:`JBI_IOB_MONDO_TRG_LO+128];\n                                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:112: Define or directive not defined: \'`JBI_IOB_MONDO_SRC_HI\'\n   assign   mondo_source = datareg[`JBI_IOB_MONDO_SRC_HI+128:`JBI_IOB_MONDO_SRC_LO+128];\n                                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_jbus_mondo_buf.v:112: Define or directive not defined: \'`JBI_IOB_MONDO_SRC_LO\'\n   assign   mondo_source = datareg[`JBI_IOB_MONDO_SRC_HI+128:`JBI_IOB_MONDO_SRC_LO+128];\n                                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module iobdg_jbus_mondo_buf (

   mondo_vld, mondo_data0, mondo_data1, mondo_target, mondo_source, 

   rst_l, clk, jbi_iob_vld, jbi_iob_data, rd_mondo_buf
   );
   
   




   input                                 rst_l;
   input 				 clk;



   input 				 jbi_iob_vld;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]  jbi_iob_data;

   

   output 				 mondo_vld;
   output [63:0] 			 mondo_data0;
   output [63:0] 			 mondo_data1;
   output [`JBI_IOB_MONDO_TRG_WIDTH-1:0] mondo_target;
   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0] mondo_source;

   input 				 rd_mondo_buf;

   

   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] 	 vldreg_next;
   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] 	 vldreg;
   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;
   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;
   wire 				 shift_en;
   
   




   assign 	 vldreg_next = {vldreg[`JBI_IOB_MONDO_BUS_CYCLE-2:0],jbi_iob_vld};
   
   dffrle_ns #(`JBI_IOB_MONDO_BUS_CYCLE) vldreg_ff (.din(vldreg_next),
						    .rst_l(rst_l),
						    .en(shift_en),
						    .clk(clk),
						    .q(vldreg));
   
   assign 	 datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],
				 jbi_iob_data};
   
   dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),
									      .en(shift_en),
									      .clk(clk),
									      .rst_l(rst_l),
									      .q(datareg));

   assign 	 shift_en = ~&vldreg | rd_mondo_buf;
   
   

   assign 	 mondo_vld = &vldreg;
   assign 	 mondo_target = datareg[`JBI_IOB_MONDO_TRG_HI+128:`JBI_IOB_MONDO_TRG_LO+128];
   assign 	 mondo_source = datareg[`JBI_IOB_MONDO_SRC_HI+128:`JBI_IOB_MONDO_SRC_LO+128];
   assign 	 mondo_data0 = datareg[127:64];
   assign 	 mondo_data1 = datareg[63:0];

   
endmodule
module iobdg_jbus_mondo_buf (

   mondo_vld, mondo_data0, mondo_data1, mondo_target, mondo_source, 

   rst_l, clk, jbi_iob_vld, jbi_iob_data, rd_mondo_buf
   );

   
   




   input                                 rst_l;
   input 				 clk;



   input 				 jbi_iob_vld;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]  jbi_iob_data;

   

   output 				 mondo_vld;
   output [63:0] 			 mondo_data0;
   output [63:0] 			 mondo_data1;
   output [`JBI_IOB_MONDO_TRG_WIDTH-1:0] mondo_target;
   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0] mondo_source;

   input 				 rd_mondo_buf;

   

   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] 	 vldreg_next;
   wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] 	 vldreg;
   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;
   wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;
   wire 				 shift_en;
   
   




   assign 	 vldreg_next = {vldreg[`JBI_IOB_MONDO_BUS_CYCLE-2:0],jbi_iob_vld};
   
   dffrle_ns #(`JBI_IOB_MONDO_BUS_CYCLE) vldreg_ff (.din(vldreg_next),
						    .rst_l(rst_l),
						    .en(shift_en),
						    .clk(clk),
						    .q(vldreg));
   
   assign 	 datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],
				 jbi_iob_data};
   
   dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),
									      .en(shift_en),
									      .clk(clk),
									      .rst_l(rst_l),
									      .q(datareg));

   assign 	 shift_en = ~&vldreg | rd_mondo_buf;
   
   

   assign 	 mondo_vld = &vldreg;
   assign 	 mondo_target = datareg[`JBI_IOB_MONDO_TRG_HI+128:`JBI_IOB_MONDO_TRG_LO+128];
   assign 	 mondo_source = datareg[`JBI_IOB_MONDO_SRC_HI+128:`JBI_IOB_MONDO_SRC_LO+128];
   assign 	 mondo_data0 = datareg[127:64];
   assign 	 mondo_data1 = datareg[63:0];

   
endmodule