data/full_repos/permissive/447976230/fpga/usrp1/megacells/pll_bb.v
data/verilator_xmls/684e4904-4fcb-42bd-93f8-3fb87e8712be.xml
module pll (
	inclk0,
	c0);

	input	  inclk0;
	output	  c0;

endmodule
module pll (
	inclk0,
	c0);


	input	  inclk0;
	output	  c0;

endmodule