data/full_repos/permissive/446312960/Verilog_Simulation/01_hello/or_gate.v
data/verilator_xmls/45862748-20de-44d5-a153-f8a2e888ddc3.xml
module or_gate (in1, in2, out);
input in1;
input in2;
output out;

assign out = in1 | in2;


endmodule
module or_gate (in1, in2, out);

input in1;
input in2;
output out;

assign out = in1 | in2;


endmodule