data/full_repos/permissive/432333689/uart with aes/decryption_uart/sources_1/imports/sources_1/new/rx.v
1: b'%Error: Cannot find file containing module: with\n        ... Looked in:\n             data/full_repos/permissive/432333689/uart/with\n             data/full_repos/permissive/432333689/uart/with.v\n             data/full_repos/permissive/432333689/uart/with.sv\n             with\n             with.v\n             with.sv\n             obj_dir/with\n             obj_dir/with.v\n             obj_dir/with.sv\n%Error: Cannot find file containing module: aes/decryption_uart/sources_1/imports/sources_1/new,data/full_repos/permissive/432333689\n%Error: Cannot find file containing module: data/full_repos/permissive/432333689/uart\n%Error: Cannot find file containing module: aes/decryption_uart/sources_1/imports/sources_1/new/rx.v\n%Error: Exiting due to 4 error(s)\n'
module rx(
    clk,
    data_in,
    data_state,
    data_out
    );
input clk,data_in;
output [127:0] data_out;
output  data_state;


parameter clock_speed=100000000;
parameter baud_rate=9600;
parameter clock_per_bit=10417;



reg[1:0] state=2'b0;
localparam init=2'd0,start=2'd1,readdata=2'd2,stop=2'd3;


reg[24:0] clock_counter=24'b0;
reg[24:0] temp_clock_counter=24'b0;
reg[7:0] output_array=8'b0;
reg[6:0] no_data_recieved=7'b0,temp_no_data_recieved=3'b0;
reg[127:0] temp_temp_data_out=128'b0,temp_data_out=128'b0,data_out128=128'b1;

reg temp_data_state=0;
reg [18:0] data_state_counter=0;

always@(posedge clk) begin
case (state)

init:
    begin
    if (clock_counter==clock_per_bit<<3)
    begin
    temp_data_state<=1'b0;  
    clock_counter<=0;
    end
    else
    begin
        
        clock_counter<=clock_counter+1;
    end
 
    if(data_in==0)
    begin
        clock_counter<=0;
        state<=start;
    end  
    end

start:
    begin

    if(clock_counter==(clock_per_bit>>1))
    begin
        if(data_in==0)
        begin
            clock_counter<=0;
            state<=readdata;
        end
        else
        begin
            state<=init;
        end      
    end
    else
    begin
        clock_counter<=clock_counter+1;
    
    end
    end

readdata:
    begin
    if(clock_counter==clock_per_bit)
        begin
            clock_counter<=0;
            output_array<={data_in,output_array[7:1]};

            no_data_recieved<=temp_no_data_recieved;
            if (&no_data_recieved[2:0])
            begin
                clock_counter<=0;
                temp_temp_data_out<=temp_data_out;
                state<=stop;
            end
        end
    else
        begin
        clock_counter<=clock_counter+1;
        end    
    end

stop:
    begin  
    if(~(|no_data_recieved[6:0]))
        begin
        temp_data_state<=1'b1;            
        end 
    else
        begin
        temp_data_state<=1'b0;   
        end
        
    if(clock_counter==clock_per_bit)
    begin
         clock_counter<=0;

        state<=init;
    end
    else
    begin
    clock_counter<=clock_counter+1;
    end
    
    end

default:
    state<=init;
endcase
end

always@(posedge clk) 
    begin
    temp_no_data_recieved<=no_data_recieved+1;
    

    if (state==stop)
        begin
        temp_data_out<={temp_temp_data_out[119:0],output_array};

        if(~(|no_data_recieved[6:0]))
            begin
            data_out128<=temp_data_out;
          
            end
        end
  
    if (state==init)
    begin
        if(temp_clock_counter==clock_per_bit*160)
        begin
            data_out128<=128'b1; 
            temp_clock_counter<=0;
        end
        else
        begin
            temp_clock_counter<=temp_clock_counter+1;
        end   
    end
    else
        begin
            temp_clock_counter<=0;
        end
           
end
assign data_state=temp_data_state;
assign data_out=data_out128;

endmodule
module rx(
    clk,
    data_in,
    data_state,
    data_out
    );

input clk,data_in;
output [127:0] data_out;
output  data_state;


parameter clock_speed=100000000;
parameter baud_rate=9600;
parameter clock_per_bit=10417;



reg[1:0] state=2'b0;
localparam init=2'd0,start=2'd1,readdata=2'd2,stop=2'd3;


reg[24:0] clock_counter=24'b0;
reg[24:0] temp_clock_counter=24'b0;
reg[7:0] output_array=8'b0;
reg[6:0] no_data_recieved=7'b0,temp_no_data_recieved=3'b0;
reg[127:0] temp_temp_data_out=128'b0,temp_data_out=128'b0,data_out128=128'b1;

reg temp_data_state=0;
reg [18:0] data_state_counter=0;

always@(posedge clk) begin
case (state)

init:
    begin
    if (clock_counter==clock_per_bit<<3)
    begin
    temp_data_state<=1'b0;  
    clock_counter<=0;
    end
    else
    begin
        
        clock_counter<=clock_counter+1;
    end
 
    if(data_in==0)
    begin
        clock_counter<=0;
        state<=start;
    end  
    end

start:
    begin

    if(clock_counter==(clock_per_bit>>1))
    begin
        if(data_in==0)
        begin
            clock_counter<=0;
            state<=readdata;
        end
        else
        begin
            state<=init;
        end      
    end
    else
    begin
        clock_counter<=clock_counter+1;
    
    end
    end

readdata:
    begin
    if(clock_counter==clock_per_bit)
        begin
            clock_counter<=0;
            output_array<={data_in,output_array[7:1]};

            no_data_recieved<=temp_no_data_recieved;
            if (&no_data_recieved[2:0])
            begin
                clock_counter<=0;
                temp_temp_data_out<=temp_data_out;
                state<=stop;
            end
        end
    else
        begin
        clock_counter<=clock_counter+1;
        end    
    end

stop:
    begin  
    if(~(|no_data_recieved[6:0]))
        begin
        temp_data_state<=1'b1;            
        end 
    else
        begin
        temp_data_state<=1'b0;   
        end
        
    if(clock_counter==clock_per_bit)
    begin
         clock_counter<=0;

        state<=init;
    end
    else
    begin
    clock_counter<=clock_counter+1;
    end
    
    end

default:
    state<=init;
endcase
end

always@(posedge clk) 
    begin
    temp_no_data_recieved<=no_data_recieved+1;
    

    if (state==stop)
        begin
        temp_data_out<={temp_temp_data_out[119:0],output_array};

        if(~(|no_data_recieved[6:0]))
            begin
            data_out128<=temp_data_out;
          
            end
        end
  
    if (state==init)
    begin
        if(temp_clock_counter==clock_per_bit*160)
        begin
            data_out128<=128'b1; 
            temp_clock_counter<=0;
        end
        else
        begin
            temp_clock_counter<=temp_clock_counter+1;
        end   
    end
    else
        begin
            temp_clock_counter<=0;
        end
           
end
assign data_state=temp_data_state;
assign data_out=data_out128;

endmodule