data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #OFFSET\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:31: Cannot find file containing module: \'VGAController\'\nVGAController UUT (.clk(clk), .Hsync(Hsync), .Vsync(Vsync), .RedIn(RedIn), .BlueIn(BlueIn), .GreenIn(GreenIn), .vgaGreen(vgaGreen),\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/VGAController\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/VGAController.v\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/VGAController.sv\n             VGAController\n             VGAController.v\n             VGAController.sv\n             obj_dir/VGAController\n             obj_dir/VGAController.v\n             obj_dir/VGAController.sv\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:50: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance VGAController_sim\n   RedIn = 1\'b0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance VGAController_sim\n   BlueIn = 1\'b0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Hsync_sim.v:52: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance VGAController_sim\n   GreenIn = 1\'b0;\n           ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module VGAController_sim();

reg clk;
reg [3:0] RedIn, BlueIn, GreenIn;
wire Hsync, Vsync;
wire [3:0] vgaGreen, vgaBlue, vgaRed;
wire [9:0] Hcount, Vcount;

VGAController UUT (.clk(clk), .Hsync(Hsync), .Vsync(Vsync), .RedIn(RedIn), .BlueIn(BlueIn), .GreenIn(GreenIn), .vgaGreen(vgaGreen),
                   .vgaBlue(vgaBlue), .vgaRed(vgaRed));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
   RedIn = 1'b0;
   BlueIn = 1'b0;
   GreenIn = 1'b0;
	end
endmodule
module VGAController_sim();


reg clk;
reg [3:0] RedIn, BlueIn, GreenIn;
wire Hsync, Vsync;
wire [3:0] vgaGreen, vgaBlue, vgaRed;
wire [9:0] Hcount, Vcount;

VGAController UUT (.clk(clk), .Hsync(Hsync), .Vsync(Vsync), .RedIn(RedIn), .BlueIn(BlueIn), .GreenIn(GreenIn), .vgaGreen(vgaGreen),
                   .vgaBlue(vgaBlue), .vgaRed(vgaRed));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
   RedIn = 1'b0;
   BlueIn = 1'b0;
   GreenIn = 1'b0;
	end
endmodule