data/full_repos/permissive/439731184/ft.v
1: b'%Error: data/full_repos/permissive/439731184/ft.v:196: Unsupported or unknown PLI call: $urandom\n    i1 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:197: Unsupported or unknown PLI call: $urandom\n    i2 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:198: Unsupported or unknown PLI call: $urandom\n    i3 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:199: Unsupported or unknown PLI call: $urandom\n    i4 = $urandom;\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:195: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/ft.v:204: Unsupported or unknown PLI call: $monitor\n    $monitor("(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add #(parameter N_BITS = 4) (a, b, c);

    input [N_BITS-1:0] a, b;
    output [N_BITS:0] c;
    
    wire [N_BITS-1:0] a, b, carry, sum, a_and_b, a_or_b, sum_and_carry;
    wire [N_BITS:0] c; 
    
    xor (c[0], a[0], b[0]);
    and (carry[0], a[0], b[0]);
    
    genvar i;
    generate
        for (i=1; i<N_BITS; i=i+1) begin
            xor(sum[i], a[i], b[i]);
            and(a_and_b[i], a[i], b[i]);
            and(sum_and_carry[i], sum[i], carry[i-1]);
            xor(c[i], sum[i], carry[i-1]);
            or(carry[i], a_and_b[i], sum_and_carry[i]);
        end
    endgenerate
    
    buf (c[N_BITS], carry[N_BITS-1]);

endmodule
module add #(parameter N_BITS = 4) (a, b, c);


    input [N_BITS-1:0] a, b;
    output [N_BITS:0] c;
    
    wire [N_BITS-1:0] a, b, carry, sum, a_and_b, a_or_b, sum_and_carry;
    wire [N_BITS:0] c; 
    
    xor (c[0], a[0], b[0]);
    and (carry[0], a[0], b[0]);
    
    genvar i;
    generate
        for (i=1; i<N_BITS; i=i+1) begin
            xor(sum[i], a[i], b[i]);
            and(a_and_b[i], a[i], b[i]);
            and(sum_and_carry[i], sum[i], carry[i-1]);
            xor(c[i], sum[i], carry[i-1]);
            or(carry[i], a_and_b[i], sum_and_carry[i]);
        end
    endgenerate
    
    buf (c[N_BITS], carry[N_BITS-1]);

endmodule