data/full_repos/permissive/465889267/code/led_glow/led_glow.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465889267/code/led_glow/led_glow.v:25: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                : ... In instance led_glow\n for (i=6\'d0;i<(NOUT+6\'d1);i=i+6\'d1)\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465889267/code/led_glow/led_glow.v:25: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                                : ... In instance led_glow\n for (i=6\'d0;i<(NOUT+6\'d1);i=i+6\'d1)\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/465889267/code/led_glow/led_glow.v:25: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                                : ... In instance led_glow\n for (i=6\'d0;i<(NOUT+6\'d1);i=i+6\'d1)\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module led_glow(clk, out);
	parameter NOUT = 55;
	input clk;
	output [NOUT:0] out;

	reg [29:0] cnt;
	wire [NOUT:0] out;

	wire pwmclk;
	
	assign pwmclk = clk;
	
	always @(posedge clk) begin
		cnt = cnt+30'd1;
	end

	wire [3:0] PWM_input1 = cnt[23] ? cnt[22:19] : ~cnt[22:19];

	reg [4:0] PWM1;
	always @(posedge pwmclk) PWM1 <= PWM1[3:0]+PWM_input1;


	genvar i;
	generate
	for (i=6'd0;i<(NOUT+6'd1);i=i+6'd1)
	begin : foo
	  assign out[i] = (i[2:0]==cnt[26:24]) ? (~PWM1[4]) : 1'd0;
	end
	endgenerate

endmodule
module led_glow(clk, out);

	parameter NOUT = 55;
	input clk;
	output [NOUT:0] out;

	reg [29:0] cnt;
	wire [NOUT:0] out;

	wire pwmclk;
	
	assign pwmclk = clk;
	
	always @(posedge clk) begin
		cnt = cnt+30'd1;
	end

	wire [3:0] PWM_input1 = cnt[23] ? cnt[22:19] : ~cnt[22:19];

	reg [4:0] PWM1;
	always @(posedge pwmclk) PWM1 <= PWM1[3:0]+PWM_input1;


	genvar i;
	generate
	for (i=6'd0;i<(NOUT+6'd1);i=i+6'd1)
	begin : foo
	  assign out[i] = (i[2:0]==cnt[26:24]) ? (~PWM1[4]) : 1'd0;
	end
	endgenerate

endmodule