data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdma,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdma,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdma,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:72: Define or directive not defined: \'`x_or_0\'\n            wr_req_in <= `x_or_0;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wr_req_in <= `x_or_0;\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:108: Define or directive not defined: \'`x_or_0\'\n            wr_count <= {8{`x_or_0}};\n                           ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:108: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            wr_count <= {8{`x_or_0}};\n                                  ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:161: Define or directive not defined: \'`x_or_0\'\n            rd_adr <= {7{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:161: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_adr <= {7{`x_or_0}};\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:198: Define or directive not defined: \'`x_or_0\'\n            rd_count_p <= {8{`x_or_0}};\n                             ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:198: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_count_p <= {8{`x_or_0}};\n                                    ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:219: Define or directive not defined: \'`x_or_0\'\n        rd_data <= {11{`x_or_0}};\n                       ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:219: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        rd_data <= {11{`x_or_0}};\n                              ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:1096: Define or directive not defined: \'`x_or_0\'\n    default: dout = {11{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v:1096: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {11{`x_or_0}};\n                               ^\n%Error: Exiting due to 13 error(s)\n'
module NV_NVDLA_CDMA_IMG_sg2pack_fifo (
      clk
    , reset_
    , wr_ready
    , wr_req
    , wr_data
    , rd_ready
    , rd_req
    , rd_data
    , pwrbus_ram_pd
    );

input clk;
input reset_;
output wr_ready;
input wr_req;
input [10:0] wr_data;
input rd_ready;
output rd_req;
output [10:0] rd_data;
input [31:0] pwrbus_ram_pd;











wire clk_mgated_enable;
wire clk_mgated;
NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) );



wire wr_reserving;
reg wr_req_in;
reg wr_busy_in;
assign wr_ready = !wr_busy_in;
wire wr_busy_next;

wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next;
wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving;
wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
                               ;
wire wr_busy_in_int;
always @( posedge clk or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_req_in <= 1'b0;
        wr_busy_in <= 1'b0;
    end else begin
        wr_busy_in <= wr_busy_in_next;
        if ( !wr_busy_in_int ) begin
            wr_req_in <= wr_req && !wr_busy_in;
        end

            else if ( wr_busy_in_int ) begin
        end else begin
            wr_req_in <= `x_or_0;
        end

    end
end
reg wr_busy_int;
assign wr_reserving = wr_req_in && !wr_busy_int;
wire wr_popping;
reg [7:0] wr_count;
wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1);
wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count;
wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 );
wire wr_count_next_is_128 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_128;
wire [7:0] wr_limit_muxed;
wire [7:0] wr_limit_reg = wr_limit_muxed;

assign wr_busy_next = wr_count_next_is_128 ||
                          (wr_limit_reg != 8'd0 &&
                           wr_count_next >= wr_limit_reg) ;

assign wr_busy_in_int = wr_req_in && wr_busy_int;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_busy_int <= 1'b0;
        wr_count <= 8'd0;
    end else begin
 wr_busy_int <= wr_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     wr_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            wr_count <= {8{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [6:0] wr_adr;


wire [6:0] wr_adr_next = wr_adr + 1'd1;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_adr <= 7'd0;
    end else begin
        if ( wr_pushing ) begin
            wr_adr <= wr_adr_next;
        end
    end
end

wire rd_popping;
reg [6:0] rd_adr;
wire ram_we = wr_pushing && (wr_count > 8'd0 || !rd_popping);
wire ram_iwe = !wr_busy_in && wr_req;
wire [10:0] rd_data_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ram (
      .clk( clk )
    , .clk_mgated( clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( wr_data )
    , .iwe ( ram_iwe )
    , .we ( ram_we )
    , .wa ( wr_adr )
    , .ra ( (wr_count == 0) ? 8'd128 : {1'b0,rd_adr} )
    , .dout ( rd_data_p )
    );
wire [6:0] rd_adr_next_popping = rd_adr + 1'd1;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_adr <= 7'd0;
    end else begin
        if ( rd_popping ) begin
     rd_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            rd_adr <= {7{`x_or_0}};
        end

    end
end



assign wr_popping = rd_popping;
wire rd_pushing = wr_pushing;



wire rd_req_p;
reg rd_req_int;
assign rd_req = rd_req_int;
assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready);
reg [7:0] rd_count_p;

wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p :
                                                                (rd_count_p - 1'd1);
wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) :
                                                                    rd_count_p;

wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
assign rd_req_p = rd_count_p != 0 || rd_pushing;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_count_p <= 8'd0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     rd_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            rd_count_p <= {8{`x_or_0}};
        end

    end
end
reg [10:0] rd_data;
wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_req_int <= 1'b0;
    end else begin
        rd_req_int <= rd_req_next;
    end
end
always @( posedge clk_mgated ) begin
    if ( (rd_popping) ) begin
        rd_data <= rd_data_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        rd_data <= {11{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit : 8'd0;
`else


assign wr_limit_muxed = 8'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 8'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 8'd0;
`else


reg wr_limit_override;
reg [7:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( clk )
    , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} )
    , .curr ( {24'd0, wr_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule
module NV_NVDLA_CDMA_IMG_sg2pack_fifo (
      clk
    , reset_
    , wr_ready
    , wr_req
    , wr_data
    , rd_ready
    , rd_req
    , rd_data
    , pwrbus_ram_pd
    );


input clk;
input reset_;
output wr_ready;
input wr_req;
input [10:0] wr_data;
input rd_ready;
output rd_req;
output [10:0] rd_data;
input [31:0] pwrbus_ram_pd;











wire clk_mgated_enable;
wire clk_mgated;
NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) );



wire wr_reserving;
reg wr_req_in;
reg wr_busy_in;
assign wr_ready = !wr_busy_in;
wire wr_busy_next;

wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next;
wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving;
wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
                               ;
wire wr_busy_in_int;
always @( posedge clk or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_req_in <= 1'b0;
        wr_busy_in <= 1'b0;
    end else begin
        wr_busy_in <= wr_busy_in_next;
        if ( !wr_busy_in_int ) begin
            wr_req_in <= wr_req && !wr_busy_in;
        end

            else if ( wr_busy_in_int ) begin
        end else begin
            wr_req_in <= `x_or_0;
        end

    end
end
reg wr_busy_int;
assign wr_reserving = wr_req_in && !wr_busy_int;
wire wr_popping;
reg [7:0] wr_count;
wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1);
wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count;
wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 );
wire wr_count_next_is_128 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_128;
wire [7:0] wr_limit_muxed;
wire [7:0] wr_limit_reg = wr_limit_muxed;

assign wr_busy_next = wr_count_next_is_128 ||
                          (wr_limit_reg != 8'd0 &&
                           wr_count_next >= wr_limit_reg) ;

assign wr_busy_in_int = wr_req_in && wr_busy_int;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_busy_int <= 1'b0;
        wr_count <= 8'd0;
    end else begin
 wr_busy_int <= wr_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     wr_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            wr_count <= {8{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [6:0] wr_adr;


wire [6:0] wr_adr_next = wr_adr + 1'd1;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        wr_adr <= 7'd0;
    end else begin
        if ( wr_pushing ) begin
            wr_adr <= wr_adr_next;
        end
    end
end

wire rd_popping;
reg [6:0] rd_adr;
wire ram_we = wr_pushing && (wr_count > 8'd0 || !rd_popping);
wire ram_iwe = !wr_busy_in && wr_req;
wire [10:0] rd_data_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ram (
      .clk( clk )
    , .clk_mgated( clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( wr_data )
    , .iwe ( ram_iwe )
    , .we ( ram_we )
    , .wa ( wr_adr )
    , .ra ( (wr_count == 0) ? 8'd128 : {1'b0,rd_adr} )
    , .dout ( rd_data_p )
    );
wire [6:0] rd_adr_next_popping = rd_adr + 1'd1;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_adr <= 7'd0;
    end else begin
        if ( rd_popping ) begin
     rd_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            rd_adr <= {7{`x_or_0}};
        end

    end
end



assign wr_popping = rd_popping;
wire rd_pushing = wr_pushing;



wire rd_req_p;
reg rd_req_int;
assign rd_req = rd_req_int;
assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready);
reg [7:0] rd_count_p;

wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p :
                                                                (rd_count_p - 1'd1);
wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) :
                                                                    rd_count_p;

wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
assign rd_req_p = rd_count_p != 0 || rd_pushing;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_count_p <= 8'd0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     rd_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            rd_count_p <= {8{`x_or_0}};
        end

    end
end
reg [10:0] rd_data;
wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ;
always @( posedge clk_mgated or negedge reset_ ) begin
    if ( !reset_ ) begin
        rd_req_int <= 1'b0;
    end else begin
        rd_req_int <= rd_req_next;
    end
end
always @( posedge clk_mgated ) begin
    if ( (rd_popping) ) begin
        rd_data <= rd_data_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        rd_data <= {11{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit : 8'd0;
`else


assign wr_limit_muxed = 8'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 8'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 8'd0;
`else


reg wr_limit_override;
reg [7:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( clk )
    , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} )
    , .curr ( {24'd0, wr_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule