data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #(2/2) clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./dumpfile.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #(2*3) key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #(2/2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #(2*2) key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #(2*100) key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #(2*30) key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #(2*3) key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(2*1) key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #(2*100000)     key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(2*300000)     key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #(2*200000)     key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #(2*400000)     key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #(2*100000)     key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #(2*100000)       key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #(2*1000*1000*4)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(2*1000*1000*4)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #(2*300000)       key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #(2*200000)       key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #(2*400000)       key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(2*100000)       key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #(2*1000)         key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #(2*1000)         key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #(2*500)          key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #(2*5)            key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #(2*50)           key_in <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #(2*1)            key_in <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #(2*1000*1000*4)\n ^\n%Error: Exiting due to 2 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
reg clk;
reg rst_n;
reg key_in;
wire key_out;
always #(`CLK_PEROID/2) clk <= ~clk;

Key_Debounce kd (
	.clk     (clk       ),
	.rst_n   (rst_n     ),
	.key_in  (key_in    ),
	.key_out (key_out   )
);

initial begin
	$dumpfile("./dumpfile.vcd");
	$dumpvars;
	clk<=1'b1;
	rst_n <= 1'b0;
	key_in<=1'b1;
	#`CLK_PEROID
	rst_n <= 1'b1;
	#(`CLK_PEROID/2)
	#(`CLK_PEROID*3)	key_in <= 1'b0;
	#(`CLK_PEROID*2)	key_in <= 1'b1;
	#(`CLK_PEROID*100)	key_in <= 1'b0;
	#(`CLK_PEROID*30)	key_in <= 1'b1;
	#(`CLK_PEROID*3)	key_in <= 1'b0;
	#(`CLK_PEROID*1)	key_in <= 1'b1;


	#(`CLK_PEROID*100000)    	key_in <= 1'b0;
	#(`CLK_PEROID*300000)    	key_in <= 1'b1;
	#(`CLK_PEROID*200000)    	key_in <= 1'b0;
	#(`CLK_PEROID*400000)    	key_in <= 1'b1;
	#(`CLK_PEROID*100000)    	key_in <= 1'b0;

	#(`CLK_PEROID*1000*1000*4)
	#(`CLK_PEROID*1000*1000*4)

	#(`CLK_PEROID*100000)       key_in <= 1'b1;
	#(`CLK_PEROID*300000)       key_in <= 1'b0;
	#(`CLK_PEROID*200000)       key_in <= 1'b1;
	#(`CLK_PEROID*400000)       key_in <= 1'b0;
	#(`CLK_PEROID*100000)       key_in <= 1'b1;
	#(`CLK_PEROID*1000)         key_in <= 1'b0;
	#(`CLK_PEROID*1000)         key_in <= 1'b1;
	#(`CLK_PEROID*500)          key_in <= 1'b0;
	#(`CLK_PEROID*5)            key_in <= 1'b1;
	#(`CLK_PEROID*50)           key_in <= 1'b0;
	#(`CLK_PEROID*1)            key_in <= 1'b1;
	#(`CLK_PEROID*1000*1000*4)
	$finish;
end
endmodule
module tb();

reg clk;
reg rst_n;
reg key_in;
wire key_out;
always #(`CLK_PEROID/2) clk <= ~clk;

Key_Debounce kd (
	.clk     (clk       ),
	.rst_n   (rst_n     ),
	.key_in  (key_in    ),
	.key_out (key_out   )
);

initial begin
	$dumpfile("./dumpfile.vcd");
	$dumpvars;
	clk<=1'b1;
	rst_n <= 1'b0;
	key_in<=1'b1;
	#`CLK_PEROID
	rst_n <= 1'b1;
	#(`CLK_PEROID/2)
	#(`CLK_PEROID*3)	key_in <= 1'b0;
	#(`CLK_PEROID*2)	key_in <= 1'b1;
	#(`CLK_PEROID*100)	key_in <= 1'b0;
	#(`CLK_PEROID*30)	key_in <= 1'b1;
	#(`CLK_PEROID*3)	key_in <= 1'b0;
	#(`CLK_PEROID*1)	key_in <= 1'b1;


	#(`CLK_PEROID*100000)    	key_in <= 1'b0;
	#(`CLK_PEROID*300000)    	key_in <= 1'b1;
	#(`CLK_PEROID*200000)    	key_in <= 1'b0;
	#(`CLK_PEROID*400000)    	key_in <= 1'b1;
	#(`CLK_PEROID*100000)    	key_in <= 1'b0;

	#(`CLK_PEROID*1000*1000*4)
	#(`CLK_PEROID*1000*1000*4)

	#(`CLK_PEROID*100000)       key_in <= 1'b1;
	#(`CLK_PEROID*300000)       key_in <= 1'b0;
	#(`CLK_PEROID*200000)       key_in <= 1'b1;
	#(`CLK_PEROID*400000)       key_in <= 1'b0;
	#(`CLK_PEROID*100000)       key_in <= 1'b1;
	#(`CLK_PEROID*1000)         key_in <= 1'b0;
	#(`CLK_PEROID*1000)         key_in <= 1'b1;
	#(`CLK_PEROID*500)          key_in <= 1'b0;
	#(`CLK_PEROID*5)            key_in <= 1'b1;
	#(`CLK_PEROID*50)           key_in <= 1'b0;
	#(`CLK_PEROID*1)            key_in <= 1'b1;
	#(`CLK_PEROID*1000*1000*4)
	$finish;
end
endmodule