data/full_repos/permissive/461069000/uart/src/uart_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461069000/uart/src/uart_tx.v:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n    reg [3:0] bit_index  = 3\'d0; \n                           ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461069000/uart/src/uart_tx.v:31: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n    reg [3:0] max_bit_index = 3\'d0;\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/461069000/uart/src/uart_tx.v:76: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                          : ... In instance uart_tx\n                    tx     = data[index];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/461069000/uart/src/uart_tx.v:86: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                    bit_index  <= 3\'d0;\n                               ^~\n%Error: Exiting due to 4 warning(s)\n'
module uart_tx (
    input  wire       clk,   
    input  wire       enable, 
    input  wire       rst, 
    input  wire       start,
    input  wire [2:0] bit_count_sel, 
    input  wire [7:0] in,    
    output reg        tx,   
    output reg        done,  
    output reg        busy
);
    
    reg [1:0] state  = `IDLE;
    reg [7:0] data   = 8'd0; 
    reg [3:0] bit_index  = 3'd0; 
    reg [3:0] index;
    reg [3:0] max_bit_index = 3'd0;
    
    always @(*)
    begin
        max_bit_index = bit_count_sel + 4; 
    end
    initial begin
        done <= 1'b0;
        tx <= 1'b1;
    end
    assign index = bit_index;

    always @(posedge clk or negedge rst) 
    begin
        if(!rst)
        begin
            state <= `IDLE;
            tx <= 1'b1;
            done <= 1'b0;
            busy <= 1'b0;
        end   
        else
        begin
            case (state)
                default     : begin
                    state   <= `IDLE;
                end
                `IDLE       : begin
                    tx     <= 1'b1;
                    done    <= 1'b0;
                    busy    <= 1'b0;
                    bit_index  <= 0;
                    data    <= 0;
                    if (start & enable) begin
                        data    <= in; 
                        state   <= `START_BIT;
                    end
                end
                `START_BIT  : begin
                    tx     <= 1'b0; 
                    busy    <= 1'b1;
                    state   <= `DATA_BIT;
                    done    <= 1'b0;
                end
                `DATA_BIT  : begin 
                    tx     = data[index];
                    done    <= 1'b0;
                    if (bit_index == max_bit_index) begin
                        state   <= `STOP_BIT;
                    tx <= 1'b1;
                    end else begin
                        bit_index  <= bit_index + 1'b1;
                    end
                end
                `STOP_BIT   : begin 
                    bit_index  <= 3'd0;
                    tx <= 1'b1;
                    done    <= 1'b1;
                    data    <= 8'b0;
                    state   <= `IDLE;
                end
                default:
                    tx <= 0;
            endcase            
        end
    end

endmodule
module uart_tx (
    input  wire       clk,   
    input  wire       enable, 
    input  wire       rst, 
    input  wire       start,
    input  wire [2:0] bit_count_sel, 
    input  wire [7:0] in,    
    output reg        tx,   
    output reg        done,  
    output reg        busy
);

    
    reg [1:0] state  = `IDLE;
    reg [7:0] data   = 8'd0; 
    reg [3:0] bit_index  = 3'd0; 
    reg [3:0] index;
    reg [3:0] max_bit_index = 3'd0;
    
    always @(*)
    begin
        max_bit_index = bit_count_sel + 4; 
    end
    initial begin
        done <= 1'b0;
        tx <= 1'b1;
    end
    assign index = bit_index;

    always @(posedge clk or negedge rst) 
    begin
        if(!rst)
        begin
            state <= `IDLE;
            tx <= 1'b1;
            done <= 1'b0;
            busy <= 1'b0;
        end   
        else
        begin
            case (state)
                default     : begin
                    state   <= `IDLE;
                end
                `IDLE       : begin
                    tx     <= 1'b1;
                    done    <= 1'b0;
                    busy    <= 1'b0;
                    bit_index  <= 0;
                    data    <= 0;
                    if (start & enable) begin
                        data    <= in; 
                        state   <= `START_BIT;
                    end
                end
                `START_BIT  : begin
                    tx     <= 1'b0; 
                    busy    <= 1'b1;
                    state   <= `DATA_BIT;
                    done    <= 1'b0;
                end
                `DATA_BIT  : begin 
                    tx     = data[index];
                    done    <= 1'b0;
                    if (bit_index == max_bit_index) begin
                        state   <= `STOP_BIT;
                    tx <= 1'b1;
                    end else begin
                        bit_index  <= bit_index + 1'b1;
                    end
                end
                `STOP_BIT   : begin 
                    bit_index  <= 3'd0;
                    tx <= 1'b1;
                    done    <= 1'b1;
                    data    <= 8'b0;
                    state   <= `IDLE;
                end
                default:
                    tx <= 0;
            endcase            
        end
    end

endmodule