data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:24: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.sv\n             ./const/parameters_cla.v\n             ./const/parameters_cla.v.v\n             ./const/parameters_cla.v.sv\n             obj_dir/./const/parameters_cla.v\n             obj_dir/./const/parameters_cla.v.v\n             obj_dir/./const/parameters_cla.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:55: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:76: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:106: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:125: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:146: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:172: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:200: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module XORSTAGE_16 ( A, B, PBIT, PHI, CARRY, SUM, COUT );
`include "./const/parameters_cla.v"


input  [N_16-1:0] A;
input  [N_16-1:0] B;
input  PBIT;
input  PHI;
input  [N_16:0] CARRY;
output [N_16-1:0] SUM;
output COUT;

 genvar l;
  generate
  for(l=0;l<=N_16-1;l=l+1) begin: f_sum
   XXOR1 U20 (A[l] , B[l] , CARRY[l] , PHI , SUM[l] );
  end
  endgenerate
  
   BLOCK1A U1 (PBIT , CARRY[0] , CARRY[N_16] , PHI , COUT );
endmodule
module XORSTAGE_16 ( A, B, PBIT, PHI, CARRY, SUM, COUT );

`include "./const/parameters_cla.v"


input  [N_16-1:0] A;
input  [N_16-1:0] B;
input  PBIT;
input  PHI;
input  [N_16:0] CARRY;
output [N_16-1:0] SUM;
output COUT;

 genvar l;
  generate
  for(l=0;l<=N_16-1;l=l+1) begin: f_sum
   XXOR1 U20 (A[l] , B[l] , CARRY[l] , PHI , SUM[l] );
  end
  endgenerate
  
   BLOCK1A U1 (PBIT , CARRY[0] , CARRY[N_16] , PHI , COUT );
endmodule