data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_synchronizer (

syncdata, 

clk, presyncdata
);


parameter SIZE = 1;

input clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;

wire [SIZE-1:0] presyncdata_tmp;

    bw_u1_syncff_4x u_synchronizer_syncff [SIZE-1:0](.q(presyncdata_tmp),
                     .so(),
                     .ck(clk),
                     .d(presyncdata),
                     .sd(),
                     .se(1'b0)
                     );

    bw_u1_soff_2x u_synchronizer_ff[SIZE-1:0] (.q(syncdata),
                     .so(),
                     .ck(clk),
                     .d(presyncdata_tmp),
                     .sd(),
                     .se(1'b0)
                     );
endmodule
module ctu_synchronizer (

syncdata, 

clk, presyncdata
);



parameter SIZE = 1;

input clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;

wire [SIZE-1:0] presyncdata_tmp;

    bw_u1_syncff_4x u_synchronizer_syncff [SIZE-1:0](.q(presyncdata_tmp),
                     .so(),
                     .ck(clk),
                     .d(presyncdata),
                     .sd(),
                     .se(1'b0)
                     );

    bw_u1_soff_2x u_synchronizer_ff[SIZE-1:0] (.q(syncdata),
                     .so(),
                     .ck(clk),
                     .d(presyncdata_tmp),
                     .sd(),
                     .se(1'b0)
                     );
endmodule