data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/bin2bcdtb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/bin2bcdtb.v:14: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/bin2bcdtb.v:16: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/bin2bcdtb.v:18: Unsupported: Ignoring delay on this delayed statement.\n                #1000\n                ^\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/bin2bcdtb.v:7: Cannot find file containing module: \'bin2bcd\'\n    bin2bcd COMP (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/bin2bcd\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/bin2bcd.v\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/bin2bcd.sv\n             bin2bcd\n             bin2bcd.v\n             bin2bcd.sv\n             obj_dir/bin2bcd\n             obj_dir/bin2bcd.v\n             obj_dir/bin2bcd.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bin2bcdtb();
    reg [7:0]bin_tb;
    wire [7:0] bcd_tb;    
        
    bin2bcd COMP (
    .bin(bin_tb),
    .bcd(bcd_tb)
    ); 
    
     initial
           begin: TEST
                #100
                bin_tb = 8'b00100000;
                #100
                bin_tb = 8'b00010000;
                #1000
                $finish;            
           end
    
    
endmodule
module bin2bcdtb();

    reg [7:0]bin_tb;
    wire [7:0] bcd_tb;    
        
    bin2bcd COMP (
    .bin(bin_tb),
    .bcd(bcd_tb)
    ); 
    
     initial
           begin: TEST
                #100
                bin_tb = 8'b00100000;
                #100
                bin_tb = 8'b00010000;
                #1000
                $finish;            
           end
    
    
endmodule