data/full_repos/permissive/522064891/efinity/baudCounter.v
data/verilator_xmls/18c7bb35-6ff2-4e6b-8f25-cd82ae2eef1f.xml
module baudCounter
(
    input clk,
    output baudClk
);

  reg [3:0] baud;

  initial begin
    baud <= 0;
  end
  
  always @(posedge clk) begin
    baud <= baud + 1;
  end
  
  assign baudClk = baud[3];
endmodule
module baudCounter
(
    input clk,
    output baudClk
);


  reg [3:0] baud;

  initial begin
    baud <= 0;
  end
  
  always @(posedge clk) begin
    baud <= baud + 1;
  end
  
  assign baudClk = baud[3];
endmodule