data/full_repos/permissive/498662723/Circuits/Sequential Logic/Finite State Machines/ece241 2013 q8 (Design a Mealy FSM).v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/ece241\n%Error: Cannot find file containing module: 2013\n%Error: Cannot find file containing module: q8\n%Error: Cannot find file containing module: (Design\n%Error: Cannot find file containing module: a\n%Error: Cannot find file containing module: Mealy\n%Error: Cannot find file containing module: FSM).v\n%Error: Exiting due to 11 error(s)\n'
module top_module (
    input clk,
    input aresetn,
    input x,
    output z ); 
    reg [1:0]	state,next_state;
    parameter S0 = 2'd0,S1 = 2'd1,S2 = 2'd2;
    
    always@(posedge clk or negedge aresetn)begin
        if(~aresetn)begin
            state = S0;
        end
        else begin
            state = next_state;
        end
    end
    
    always@(*)begin
        case(state)
            S0:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S0;
                end
            end
            S1:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S2;
                end
            end
            S2:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S0;
                end
            end
        endcase
    end
    assign z = (state == S2 && x);
endmodule
module top_module (
    input clk,
    input aresetn,
    input x,
    output z );
 
    reg [1:0]	state,next_state;
    parameter S0 = 2'd0,S1 = 2'd1,S2 = 2'd2;
    
    always@(posedge clk or negedge aresetn)begin
        if(~aresetn)begin
            state = S0;
        end
        else begin
            state = next_state;
        end
    end
    
    always@(*)begin
        case(state)
            S0:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S0;
                end
            end
            S1:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S2;
                end
            end
            S2:begin
                if(x)begin
                    next_state = S1;
                end
                else begin
                    next_state = S0;
                end
            end
        endcase
    end
    assign z = (state == S2 && x);
endmodule