data/full_repos/permissive/52703097/multiplier.test.v
1: b'%Error: data/full_repos/permissive/52703097/multiplier.test.v:1: Cannot find include file: multiplier.v\n`include "multiplier.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/multiplier.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/multiplier.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/multiplier.v.sv\n             multiplier.v\n             multiplier.v.v\n             multiplier.v.sv\n             obj_dir/multiplier.v\n             obj_dir/multiplier.v.v\n             obj_dir/multiplier.v.sv\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:2: Cannot find include file: sim.v\n`include "sim.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:8: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH-1:0] a, b;\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:9: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH+`WIDTH-1:0] result, corr_result;\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:9: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH+`WIDTH-1:0] result, corr_result;\n               ^~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:10: Define or directive not defined: \'`WIDTH\'\n    wire[`WIDTH+`WIDTH-1:0] out;\n         ^~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:10: Define or directive not defined: \'`WIDTH\'\n    wire[`WIDTH+`WIDTH-1:0] out;\n                ^~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:19: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/52703097/multiplier.test.v:20: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 start = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 next_reg<= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 next_reg <= 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1 corr_result <= a*b;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 start <= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/multiplier.test.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #10 $finish;\n            ^\n%Error: Exiting due to 9 error(s), 6 warning(s)\n'
module test;

    reg[`WIDTH-1:0] a, b;
    reg[`WIDTH+`WIDTH-1:0] result, corr_result;
    wire[`WIDTH+`WIDTH-1:0] out;
    reg start = 1'b0;
    reg next_reg = 1'b0;

    wire clk, reset, ready, next;
    assign next = next_reg;
    
    integer t;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        #10 start = 1'b1;
        a = $random % 10;
        b = $random % 10;
        t = 0;
    end

    always @(posedge ready) begin
        $display("Result = %d, exp = %d", out, corr_result);
        start <= 1'b0;
        #10 next_reg<= 1'b1;
    end

    always @(posedge next) begin
        a <= $random % 10;
        b <= $random % 10;
        #10 next_reg <= 1'b0;
        #1 corr_result <= a*b;
        #1 start <= 1'b1;

        t = t+1;
        if (t >= `TESTS-1)
            #10 $finish;
    end
            
    multiplier mul(
        .start(start),
        .clk(clk),
        .multiplier(b),
        .multiplicand(a),
        .product(out),
        .ready(ready));

    sim my_sim(.clk(clk), .reset(reset));
endmodule
module test;


    reg[`WIDTH-1:0] a, b;
    reg[`WIDTH+`WIDTH-1:0] result, corr_result;
    wire[`WIDTH+`WIDTH-1:0] out;
    reg start = 1'b0;
    reg next_reg = 1'b0;

    wire clk, reset, ready, next;
    assign next = next_reg;
    
    integer t;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        #10 start = 1'b1;
        a = $random % 10;
        b = $random % 10;
        t = 0;
    end

    always @(posedge ready) begin
        $display("Result = %d, exp = %d", out, corr_result);
        start <= 1'b0;
        #10 next_reg<= 1'b1;
    end

    always @(posedge next) begin
        a <= $random % 10;
        b <= $random % 10;
        #10 next_reg <= 1'b0;
        #1 corr_result <= a*b;
        #1 start <= 1'b1;

        t = t+1;
        if (t >= `TESTS-1)
            #10 $finish;
    end
            
    multiplier mul(
        .start(start),
        .clk(clk),
        .multiplier(b),
        .multiplicand(a),
        .product(out),
        .ready(ready));

    sim my_sim(.clk(clk), .reset(reset));
endmodule