data/full_repos/permissive/513199821/test.v
1: b'%Error: data/full_repos/permissive/513199821/test.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #32;    \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #32;\n  ^\n%Error: data/full_repos/permissive/513199821/test.v:500: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("/tmp/eonsoc.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:501: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:504: Unsupported or unknown PLI call: $timeformat\n  $timeformat (-6, 3, "us", 12);\n  ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:509: Unsupported: Ignoring delay on this delayed statement.\n  #128;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:514: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:516: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:522: Unsupported: Ignoring delay on this delayed statement.\n    # 64;\n    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module spi_ram #(
    parameter MEMORY_BITS = 17
  ) (
    input      clk,
    input      mosi,
    input      ss_n,
    output reg miso
);


localparam CMD_MODE  = 8'h01;
localparam CMD_WRITE = 8'h02;
localparam CMD_READ  = 8'h03;


localparam S_IDLE    = 3'd0;
localparam S_MODE    = 3'd1;
localparam S_ADDR_H  = 3'd2;
localparam S_ADDR_M  = 3'd3;
localparam S_ADDR_L  = 3'd4;
localparam S_DATA    = 3'd5;


localparam rb7 = 3'd0;
localparam rb6 = 3'd1;
localparam rb5 = 3'd2;
localparam rb4 = 3'd3;
localparam rb3 = 3'd4;
localparam rb2 = 3'd5;
localparam rb1 = 3'd6;
localparam rb0 = 3'd7;


localparam sb7 = 3'd0;
localparam sb6 = 3'd1;
localparam sb5 = 3'd2;
localparam sb4 = 3'd3;
localparam sb3 = 3'd4;
localparam sb2 = 3'd5;
localparam sb1 = 3'd6;
localparam sb0 = 3'd7;

reg [2:0] cs;
reg [2:0] st_recv;
reg [2:0] st_send;
reg read, send_now;

reg [7:0] rx_data, send_data;


integer ii;
localparam MEM_BYTES = $pow (2, MEMORY_BITS);
reg [23:0] sram_addr;
reg [ 7:0] sram [MEM_BYTES - 1:0];

initial begin
  for (ii = 0; ii < MEM_BYTES; ii++)
    sram[ii] = ii[7:0];
  st_send   = sb7;
  send_now  = 0;
  st_recv   = rb7;
  st_send   = sb7;
  cs	    = S_IDLE;
  sram_addr = 0;
end


always @(posedge clk) begin
  if (ss_n) begin
    st_recv  <= rb7;
    cs	     <= S_IDLE;
    send_now <= 0;
  end else begin


    case (st_recv)
      rb7: begin st_recv <= rb6; rx_data[7] <= mosi; end
      rb6: begin st_recv <= rb5; rx_data[6] <= mosi; end
      rb5: begin st_recv <= rb4; rx_data[5] <= mosi; end
      rb4: begin st_recv <= rb3; rx_data[4] <= mosi; end
      rb3: begin st_recv <= rb2; rx_data[3] <= mosi; end
      rb2: begin st_recv <= rb1; rx_data[2] <= mosi; end
      rb1: begin st_recv <= rb0; rx_data[1] <= mosi; end
      rb0: begin
	rx_data[0] = mosi;
	st_recv   <= rb7;



	case (cs)
	  S_IDLE: begin

	    case (rx_data)
	      CMD_MODE: begin
		cs <= S_MODE;
	      end
	      CMD_READ: begin
		read <= 1'b1;
		cs   <= S_ADDR_H;
	      end
	      CMD_WRITE: begin
		read <= 1'b0;
		cs   <= S_ADDR_H;
	      end
	      default: begin
		$display ("spislv cmd?? %t = %x", $time, rx_data);
	      end
	    endcase
	  end

	  S_MODE: begin


	    cs <= S_IDLE;
	  end

	  S_ADDR_H: begin
	    sram_addr[23:16] <= rx_data;
	    cs		     <= S_ADDR_M;
	  end

	  S_ADDR_M: begin
	    sram_addr[15:8] <= rx_data;
	    cs		    <= S_ADDR_L;
	  end

	  S_ADDR_L: begin
	    sram_addr[7:0] <= rx_data;
	    cs		   <= S_DATA;
	    send_now	   <= read;
	    st_send	   <= sb6;
	    send_data	   <= sram[{sram_addr[MEMORY_BITS - 1: 8], rx_data}];
	    miso	   <= sram[{sram_addr[MEMORY_BITS - 1: 8], rx_data}][7];

	  end

	  S_DATA: begin

	  end

	endcase
      end
    endcase
  end
end

always @(posedge clk) begin
  if (send_now) begin
    case (st_send)
      sb7: begin st_send = sb6; miso = send_data[7]; end
      sb6: begin st_send = sb5; miso = send_data[6]; end
      sb5: begin st_send = sb4; miso = send_data[5]; end
      sb4: begin st_send = sb3; miso = send_data[4]; end
      sb3: begin st_send = sb2; miso = send_data[3]; end
      sb2: begin st_send = sb1; miso = send_data[2]; end
      sb1: begin st_send = sb0; miso = send_data[1]; sram_addr <= sram_addr + 1'b1; end
      sb0: begin
	st_send   <= sb7;
	miso	  <= send_data[0];
	send_data <= sram[sram_addr];

      end
    endcase
  end
end
endmodule
module spi_ram #(
    parameter MEMORY_BITS = 17
  ) (
    input      clk,
    input      mosi,
    input      ss_n,
    output reg miso
);



localparam CMD_MODE  = 8'h01;
localparam CMD_WRITE = 8'h02;
localparam CMD_READ  = 8'h03;


localparam S_IDLE    = 3'd0;
localparam S_MODE    = 3'd1;
localparam S_ADDR_H  = 3'd2;
localparam S_ADDR_M  = 3'd3;
localparam S_ADDR_L  = 3'd4;
localparam S_DATA    = 3'd5;


localparam rb7 = 3'd0;
localparam rb6 = 3'd1;
localparam rb5 = 3'd2;
localparam rb4 = 3'd3;
localparam rb3 = 3'd4;
localparam rb2 = 3'd5;
localparam rb1 = 3'd6;
localparam rb0 = 3'd7;


localparam sb7 = 3'd0;
localparam sb6 = 3'd1;
localparam sb5 = 3'd2;
localparam sb4 = 3'd3;
localparam sb3 = 3'd4;
localparam sb2 = 3'd5;
localparam sb1 = 3'd6;
localparam sb0 = 3'd7;

reg [2:0] cs;
reg [2:0] st_recv;
reg [2:0] st_send;
reg read, send_now;

reg [7:0] rx_data, send_data;


integer ii;
localparam MEM_BYTES = $pow (2, MEMORY_BITS);
reg [23:0] sram_addr;
reg [ 7:0] sram [MEM_BYTES - 1:0];

initial begin
  for (ii = 0; ii < MEM_BYTES; ii++)
    sram[ii] = ii[7:0];
  st_send   = sb7;
  send_now  = 0;
  st_recv   = rb7;
  st_send   = sb7;
  cs	    = S_IDLE;
  sram_addr = 0;
end


always @(posedge clk) begin
  if (ss_n) begin
    st_recv  <= rb7;
    cs	     <= S_IDLE;
    send_now <= 0;
  end else begin


    case (st_recv)
      rb7: begin st_recv <= rb6; rx_data[7] <= mosi; end
      rb6: begin st_recv <= rb5; rx_data[6] <= mosi; end
      rb5: begin st_recv <= rb4; rx_data[5] <= mosi; end
      rb4: begin st_recv <= rb3; rx_data[4] <= mosi; end
      rb3: begin st_recv <= rb2; rx_data[3] <= mosi; end
      rb2: begin st_recv <= rb1; rx_data[2] <= mosi; end
      rb1: begin st_recv <= rb0; rx_data[1] <= mosi; end
      rb0: begin
	rx_data[0] = mosi;
	st_recv   <= rb7;



	case (cs)
	  S_IDLE: begin

	    case (rx_data)
	      CMD_MODE: begin
		cs <= S_MODE;
	      end
	      CMD_READ: begin
		read <= 1'b1;
		cs   <= S_ADDR_H;
	      end
	      CMD_WRITE: begin
		read <= 1'b0;
		cs   <= S_ADDR_H;
	      end
	      default: begin
		$display ("spislv cmd?? %t = %x", $time, rx_data);
	      end
	    endcase
	  end

	  S_MODE: begin


	    cs <= S_IDLE;
	  end

	  S_ADDR_H: begin
	    sram_addr[23:16] <= rx_data;
	    cs		     <= S_ADDR_M;
	  end

	  S_ADDR_M: begin
	    sram_addr[15:8] <= rx_data;
	    cs		    <= S_ADDR_L;
	  end

	  S_ADDR_L: begin
	    sram_addr[7:0] <= rx_data;
	    cs		   <= S_DATA;
	    send_now	   <= read;
	    st_send	   <= sb6;
	    send_data	   <= sram[{sram_addr[MEMORY_BITS - 1: 8], rx_data}];
	    miso	   <= sram[{sram_addr[MEMORY_BITS - 1: 8], rx_data}][7];

	  end

	  S_DATA: begin

	  end

	endcase
      end
    endcase
  end
end

always @(posedge clk) begin
  if (send_now) begin
    case (st_send)
      sb7: begin st_send = sb6; miso = send_data[7]; end
      sb6: begin st_send = sb5; miso = send_data[6]; end
      sb5: begin st_send = sb4; miso = send_data[5]; end
      sb4: begin st_send = sb3; miso = send_data[4]; end
      sb3: begin st_send = sb2; miso = send_data[3]; end
      sb2: begin st_send = sb1; miso = send_data[2]; end
      sb1: begin st_send = sb0; miso = send_data[1]; sram_addr <= sram_addr + 1'b1; end
      sb0: begin
	st_send   <= sb7;
	miso	  <= send_data[0];
	send_data <= sram[sram_addr];

      end
    endcase
  end
end
endmodule