data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:73: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450382427/verilog/rtl/user_proj_example.v:74: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module adder4bit(a,b,sum,co);
input [3:0]a,b;
output [3:0]sum;
output co;
fa fa1(a[0],b[0],1'b0,sum[0],c1),
   fa2(a[1],b[1],c1,sum[1],c2),
   fa3(a[2],b[2],c2,sum[2],c3),
   fa4(a[3],b[3],c3,sum[3],co);
endmodule
module adder4bit(a,b,sum,co);

input [3:0]a,b;
output [3:0]sum;
output co;
fa fa1(a[0],b[0],1'b0,sum[0],c1),
   fa2(a[1],b[1],c1,sum[1],c2),
   fa3(a[2],b[2],c2,sum[2],c3),
   fa4(a[3],b[3],c3,sum[3],co);
endmodule