data/full_repos/permissive/430026064/shift_left.v
data/verilator_xmls/cd942986-358f-42d3-8000-6d75c51703eb.xml
module shift_left_32bit(in_data, out_data);
	input[31:0] in_data;
	output reg[31:0] out_data;
	
	always@(in_data) begin
		out_data = in_data << 1;
	end
endmodule
module shift_left_32bit(in_data, out_data);

	input[31:0] in_data;
	output reg[31:0] out_data;
	
	always@(in_data) begin
		out_data = in_data << 1;
	end
endmodule