data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sources_1/new/multi_flotante.v
1: b'%Warning-WIDTH: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sources_1/new/multi_flotante.v:135: Operator SUB expects 32 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                                                        : ... In instance multi_flotante\n            exp_a <= a[30:23] - 23 - 127;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sources_1/new/multi_flotante.v:136: Operator SUB expects 32 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                                                        : ... In instance multi_flotante\n            exp_b <= b[30:23] - 23 - 127;\n                              ^\n%Error: Exiting due to 2 warning(s)\n'
module multi_flotante(

    input clk,reset,
    input [31:0]a,b,
    output reg [31:0]c
    );
    
    parameter S_inicial = 4'b0000;
    parameter S_asignacion = 4'b0001;
    parameter S_cero = 4'b0010;
    parameter S_signos = 4'b0011;
    parameter S_mantisa_a= 4'b0100;
    parameter S_mantisa_b = 4'b0101;
    parameter S_exponentes = 4'b0110;
    parameter S_multipli = 4'b0111;
    parameter S_mantisa_c = 4'b1000;
    parameter S_mantisa_c_2 = 4'b1001;
    parameter S_fin = 4'b1010;
      
    reg [3:0] state,nextstate;

      

    reg [31:0]exp_a;
    reg [31:0]exp_b;
    reg [31:0]exp_c;
    reg [31:0]man_a;
    reg [31:0]man_b;
    reg [31:0]man_c;
    reg sig_c;
    

    always@(posedge clk, posedge reset)begin
        if(reset) state <= S_inicial;
        else      state <= nextstate;
    end
    

    always@* begin
        case(state)
            S_inicial: 
                nextstate = S_asignacion;
                
            S_asignacion:
                nextstate = S_cero;
                
            S_cero: 
                if( (man_a == 32'h00800000 && exp_a == 32'hFFFFFF6A) || (man_b == 32'h00800000 && exp_b == 32'hFFFFFF6A) ) nextstate = S_fin;
                else nextstate = S_signos;
            
            S_signos: 
                nextstate = S_mantisa_a;
                                
            S_mantisa_a: 
                if(man_a[0]==0)nextstate = S_mantisa_a;  
                else           nextstate = S_mantisa_b;           
            
            S_mantisa_b: 
                if(man_b[0]==0)nextstate = S_mantisa_b;   
                else           nextstate = S_exponentes; 
            
            S_exponentes: 
                nextstate = S_multipli;            
            
            S_multipli: 
                nextstate = S_mantisa_c; 
                
            S_mantisa_c: 
                if(man_c[31]==0)nextstate = S_mantisa_c;   
                else            nextstate = S_mantisa_c_2; 
                
            S_mantisa_c_2:
                nextstate = S_fin; 
           
            S_fin:
                nextstate = S_fin;
             
        endcase
    end
        

    always@(posedge clk) begin
        if(state == S_inicial)begin
            exp_a <= 0;
            exp_b <= 0;
            exp_c <= 0;
            man_a <= 0;
            man_b <= 0;
            man_c <= 0;
            sig_c <= 0;
        end
        
        else if(state == S_asignacion)begin
            exp_a <= a[30:23] - 23 - 127;
            exp_b <= b[30:23] - 23 - 127;
            man_a[23] <= 1'b1;
            man_b[23] <= 1'b1;
            man_a[22:0] <= a[22:0];
            man_b[22:0] <= b[22:0];
        end
    
        else if(state == S_cero && ( (man_a == 32'h00800000 && exp_a == 32'hFFFFFF6A) || (man_b == 32'h00800000 && exp_b == 32'hFFFFFF6A) ) )begin
            sig_c <= 0;
            man_c <= 0;
            exp_c <= 32'hFFFFFF81;
        end

        else if(state == S_signos)
            sig_c <= a[31] ^ b[31];        

        else if(state == S_mantisa_a && man_a[0]==0)begin 
            man_a <= man_a >> 1;
            exp_a <= exp_a + 1;
        end        
        
        else if(state == S_mantisa_b && man_b[0]==0)begin 
            man_b <= man_b >> 1;
            exp_b <= exp_b + 1;
        end
        
        else if(state == S_exponentes) 
            exp_c <= exp_a + exp_b;

        else if(state == S_multipli) 
            man_c <= man_a * man_b;
        
        else if(state == S_mantisa_c && man_c[31]==0)begin
            man_c <= man_c << 1;
            exp_c <= exp_c - 1;
        end
        
        else if(state == S_mantisa_c_2)begin
            man_c <= man_c << 1;
            exp_c <= exp_c - 1 + 32;
        end
        
        else if(state == S_fin)begin
            c[31] <= sig_c;
            c[30:23] <= exp_c[7:0] + 127;
            c[22:0] <=man_c[31:9];
        end
    end
endmodule
module multi_flotante(

    input clk,reset,
    input [31:0]a,b,
    output reg [31:0]c
    );

    
    parameter S_inicial = 4'b0000;
    parameter S_asignacion = 4'b0001;
    parameter S_cero = 4'b0010;
    parameter S_signos = 4'b0011;
    parameter S_mantisa_a= 4'b0100;
    parameter S_mantisa_b = 4'b0101;
    parameter S_exponentes = 4'b0110;
    parameter S_multipli = 4'b0111;
    parameter S_mantisa_c = 4'b1000;
    parameter S_mantisa_c_2 = 4'b1001;
    parameter S_fin = 4'b1010;
      
    reg [3:0] state,nextstate;

      

    reg [31:0]exp_a;
    reg [31:0]exp_b;
    reg [31:0]exp_c;
    reg [31:0]man_a;
    reg [31:0]man_b;
    reg [31:0]man_c;
    reg sig_c;
    

    always@(posedge clk, posedge reset)begin
        if(reset) state <= S_inicial;
        else      state <= nextstate;
    end
    

    always@* begin
        case(state)
            S_inicial: 
                nextstate = S_asignacion;
                
            S_asignacion:
                nextstate = S_cero;
                
            S_cero: 
                if( (man_a == 32'h00800000 && exp_a == 32'hFFFFFF6A) || (man_b == 32'h00800000 && exp_b == 32'hFFFFFF6A) ) nextstate = S_fin;
                else nextstate = S_signos;
            
            S_signos: 
                nextstate = S_mantisa_a;
                                
            S_mantisa_a: 
                if(man_a[0]==0)nextstate = S_mantisa_a;  
                else           nextstate = S_mantisa_b;           
            
            S_mantisa_b: 
                if(man_b[0]==0)nextstate = S_mantisa_b;   
                else           nextstate = S_exponentes; 
            
            S_exponentes: 
                nextstate = S_multipli;            
            
            S_multipli: 
                nextstate = S_mantisa_c; 
                
            S_mantisa_c: 
                if(man_c[31]==0)nextstate = S_mantisa_c;   
                else            nextstate = S_mantisa_c_2; 
                
            S_mantisa_c_2:
                nextstate = S_fin; 
           
            S_fin:
                nextstate = S_fin;
             
        endcase
    end
        

    always@(posedge clk) begin
        if(state == S_inicial)begin
            exp_a <= 0;
            exp_b <= 0;
            exp_c <= 0;
            man_a <= 0;
            man_b <= 0;
            man_c <= 0;
            sig_c <= 0;
        end
        
        else if(state == S_asignacion)begin
            exp_a <= a[30:23] - 23 - 127;
            exp_b <= b[30:23] - 23 - 127;
            man_a[23] <= 1'b1;
            man_b[23] <= 1'b1;
            man_a[22:0] <= a[22:0];
            man_b[22:0] <= b[22:0];
        end
    
        else if(state == S_cero && ( (man_a == 32'h00800000 && exp_a == 32'hFFFFFF6A) || (man_b == 32'h00800000 && exp_b == 32'hFFFFFF6A) ) )begin
            sig_c <= 0;
            man_c <= 0;
            exp_c <= 32'hFFFFFF81;
        end

        else if(state == S_signos)
            sig_c <= a[31] ^ b[31];        

        else if(state == S_mantisa_a && man_a[0]==0)begin 
            man_a <= man_a >> 1;
            exp_a <= exp_a + 1;
        end        
        
        else if(state == S_mantisa_b && man_b[0]==0)begin 
            man_b <= man_b >> 1;
            exp_b <= exp_b + 1;
        end
        
        else if(state == S_exponentes) 
            exp_c <= exp_a + exp_b;

        else if(state == S_multipli) 
            man_c <= man_a * man_b;
        
        else if(state == S_mantisa_c && man_c[31]==0)begin
            man_c <= man_c << 1;
            exp_c <= exp_c - 1;
        end
        
        else if(state == S_mantisa_c_2)begin
            man_c <= man_c << 1;
            exp_c <= exp_c - 1 + 32;
        end
        
        else if(state == S_fin)begin
            c[31] <= sig_c;
            c[30:23] <= exp_c[7:0] + 127;
            c[22:0] <=man_c[31:9];
        end
    end
endmodule