data/full_repos/permissive/420671157/verilog_files/fa2.v
1: b'%Error: data/full_repos/permissive/420671157/verilog_files/fa2.v:49: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile(" 10.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/420671157/verilog_files/fa2.v:50: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Carry(a,b,c,s,co);
	input [0:0] a;
	input [0:0] b;
	input [0:0] c;
	output [0:0] s;
	output [0:0] co;
	wire [0:0] out1, out2, out3, out4;
	assign out1 = a & b;
	assign out2 = a ^ b;
	assign out3 = out2 & c;
	assign co = out3 | out1;
	assign out4 = a ^ b;
	assign s = out4 ^ c;
endmodule
module Carry(a,b,c,s,co);

	input [0:0] a;
	input [0:0] b;
	input [0:0] c;
	output [0:0] s;
	output [0:0] co;
	wire [0:0] out1, out2, out3, out4;
	assign out1 = a & b;
	assign out2 = a ^ b;
	assign out3 = out2 & c;
	assign co = out3 | out1;
	assign out4 = a ^ b;
	assign s = out4 ^ c;
endmodule