data/full_repos/permissive/426611218/PC.v
data/verilator_xmls/7a65f98d-c01e-40b6-917b-987599d20bb2.xml
module PC (
    input clk, rst,
    input[31:0] count_in,
    output reg[31:0] count_out
);

    always @(posedge clk)
    begin
        assign count_out = count_in + 1;        
    end

    always @(negedge rst) begin
        count_out = 0;        
    end

    
endmodule
module PC (
    input clk, rst,
    input[31:0] count_in,
    output reg[31:0] count_out
);


    always @(posedge clk)
    begin
        assign count_out = count_in + 1;        
    end

    always @(negedge rst) begin
        count_out = 0;        
    end

    
endmodule