data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_seq.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_seq.v:51: Operator ASSIGNDLY expects 1600 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 576 bits.\n                                                                                                    : ... In instance sha3_seq\n   round_reg <= {e_init, g_init};\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_seq.v:90: Cannot find file containing module: \'rconst\'\n  rconst rconst_ \n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst.sv\n             rconst\n             rconst.v\n             rconst.sv\n             obj_dir/rconst\n             obj_dir/rconst.v\n             obj_dir/rconst.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_seq.v:102: Cannot find file containing module: \'round\'\n round \n ^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module sha3_seq
#(
	parameter CC=24
)
(
	clk,
  rst,
	g_init,
  e_init,
	o
);

  input             clk;
  input 						rst;
  input	  [287:0]		g_init;
  input   [287:0]   e_init;
  output  [1599:0]	o;
  
	reg 							init;
  reg		[CC-1:0]		rc_i;
	reg		[24-1:0]		rc_j[24/CC-1:0];
	wire	[63:0]			rc[24/CC-1:0];
  wire	[1599:0]		round_in[24/CC-1:0];
  wire 	[1599:0]		round_out[24/CC-1:0];
	reg 	[1599:0]		round_reg;   

    
	always @ (posedge clk or posedge rst)
	begin
		if (rst) 	
		begin
			init <= 0;
			rc_i <= 0;
			round_reg <= {e_init, g_init};
		end
		else     
		begin
			init <= 1;
			rc_i <= {rc_i[CC-2:0], ~init};
			round_reg <= round_out[24/CC-1];
		end
    end

  assign round_in[0] = round_reg;
	assign o = round_out[24/CC-1];

    integer k,t;
	always@(*)
	begin
		for(k=0;k<24/CC;k=k+1)
		begin
			rc_j[k] = 0;
			for(t=0;t<CC;t=t+1)
			begin
				rc_j[k][(24/CC)*t+k] = rc_i[t];
			end
		end
	end

	genvar q;
	
	generate
	for(q=1;q<24/CC;q=q+1)
	begin:ASSROUND
		assign round_in[q] = round_out[q-1];
	end
	endgenerate
	
	
	generate
	for(q=0;q<24/CC;q=q+1)
	begin:RCONST
		rconst rconst_ 
		(
			.i(rc_j[q]),
			.rc(rc[q])
		);
	end
	endgenerate
	

	generate
	for(q=0;q<24/CC;q=q+1)
	begin:ROUND
	round 
		round_ 
		(
			.in(round_in[q]), 
			.round_const(rc[q]), 
			.out(round_out[q])
		);
	end
	endgenerate
	
endmodule
module sha3_seq
#(
	parameter CC=24
)
(
	clk,
  rst,
	g_init,
  e_init,
	o
);


  input             clk;
  input 						rst;
  input	  [287:0]		g_init;
  input   [287:0]   e_init;
  output  [1599:0]	o;
  
	reg 							init;
  reg		[CC-1:0]		rc_i;
	reg		[24-1:0]		rc_j[24/CC-1:0];
	wire	[63:0]			rc[24/CC-1:0];
  wire	[1599:0]		round_in[24/CC-1:0];
  wire 	[1599:0]		round_out[24/CC-1:0];
	reg 	[1599:0]		round_reg;   

    
	always @ (posedge clk or posedge rst)
	begin
		if (rst) 	
		begin
			init <= 0;
			rc_i <= 0;
			round_reg <= {e_init, g_init};
		end
		else     
		begin
			init <= 1;
			rc_i <= {rc_i[CC-2:0], ~init};
			round_reg <= round_out[24/CC-1];
		end
    end

  assign round_in[0] = round_reg;
	assign o = round_out[24/CC-1];

    integer k,t;
	always@(*)
	begin
		for(k=0;k<24/CC;k=k+1)
		begin
			rc_j[k] = 0;
			for(t=0;t<CC;t=t+1)
			begin
				rc_j[k][(24/CC)*t+k] = rc_i[t];
			end
		end
	end

	genvar q;
	
	generate
	for(q=1;q<24/CC;q=q+1)
	begin:ASSROUND
		assign round_in[q] = round_out[q-1];
	end
	endgenerate
	
	
	generate
	for(q=0;q<24/CC;q=q+1)
	begin:RCONST
		rconst rconst_ 
		(
			.i(rc_j[q]),
			.rc(rc[q])
		);
	end
	endgenerate
	

	generate
	for(q=0;q<24/CC;q=q+1)
	begin:ROUND
	round 
		round_ 
		(
			.in(round_in[q]), 
			.round_const(rc[q]), 
			.out(round_out[q])
		);
	end
	endgenerate
	
endmodule