data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v
1: b'%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:24: Cannot find file containing module: \'clockDivider\'\n    clockDivider #(50000) QD2 (clk, rst, clk_out);      \n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499596866/Simulation/sources_1/new,data/full_repos/permissive/499596866/clockDivider\n             data/full_repos/permissive/499596866/Simulation/sources_1/new,data/full_repos/permissive/499596866/clockDivider.v\n             data/full_repos/permissive/499596866/Simulation/sources_1/new,data/full_repos/permissive/499596866/clockDivider.sv\n             clockDivider\n             clockDivider.v\n             clockDivider.sv\n             obj_dir/clockDivider\n             obj_dir/clockDivider.v\n             obj_dir/clockDivider.sv\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:26: Cannot find file containing module: \'debouncer\'\n    debouncer ins0 (clk, B[0], in[0]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:27: Cannot find file containing module: \'debouncer\'\n    debouncer ins1 (clk, B[1], in[1]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:28: Cannot find file containing module: \'debouncer\'\n    debouncer ins2 (clk, B[2], in[2]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:29: Cannot find file containing module: \'debouncer\'\n    debouncer ins3 (clk, B[3], in[3]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:30: Cannot find file containing module: \'debouncer\'\n    debouncer ins4 (clk, B[4], in[4]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:31: Cannot find file containing module: \'debouncer\'\n    debouncer ins5 (clk, B[5], in[5]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:32: Cannot find file containing module: \'debouncer\'\n    debouncer ins6 (clk, B[6], in[6]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:33: Cannot find file containing module: \'debouncer\'\n    debouncer ins7 (clk, B[7], in[7]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:34: Cannot find file containing module: \'debouncer\'\n    debouncer ins8 (clk, B[8], in[8]);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:36: Cannot find file containing module: \'edge_det\'\n   edge_det ed0 (clk, rst, in[0], key[0]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:37: Cannot find file containing module: \'edge_det\'\n   edge_det ed1 (clk, rst, in[1], key[1]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:38: Cannot find file containing module: \'edge_det\'\n   edge_det ed2 (clk, rst, in[2], key[2]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:39: Cannot find file containing module: \'edge_det\'\n   edge_det ed3 (clk, rst, in[3], key[3]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:40: Cannot find file containing module: \'edge_det\'\n   edge_det ed4 (clk, rst, in[4], key[4]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:41: Cannot find file containing module: \'edge_det\'\n   edge_det ed5 (clk, rst, in[5], key[5]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:42: Cannot find file containing module: \'edge_det\'\n   edge_det ed6 (clk, rst, in[6], key[6]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:43: Cannot find file containing module: \'edge_det\'\n   edge_det ed7 (clk, rst, in[7], key[7]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:44: Cannot find file containing module: \'edge_det\'\n   edge_det ed8 (clk, rst, in[8], key[8]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:46: Cannot find file containing module: \'BCD\'\n   BCD seg1 (num1, 0, out1);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:47: Cannot find file containing module: \'BCD\'\n   BCD seg2 (num2, 1, out2);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:48: Cannot find file containing module: \'BCD\'\n   BCD seg3 (num3, 0, out3);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:49: Cannot find file containing module: \'BCD\'\n   BCD seg4 (num4, 0, out4);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:50: Cannot find file containing module: \'BCD\'\n   BCD seg5 (dig1, 0, out5);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:51: Cannot find file containing module: \'BCD\'\n   BCD seg6 (dig2, 0, out6);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:52: Cannot find file containing module: \'BCD\'\n   BCD seg7 (dig3, 0, out7);\n   ^~~\n%Error: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:53: Cannot find file containing module: \'BCD\'\n   BCD seg8 (dig4, 0, out8);\n   ^~~\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:83: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (num1*\'d10 + num2) + (num3*\'d10 + num4);\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:83: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (num1*\'d10 + num2) + (num3*\'d10 + num4);\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:91: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (~neg)? (num1*4\'d10 + num2) - (num3*4\'d10 + num4):(num3*4\'d10 + num4) - (num1*4\'d10 + num2);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:91: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (~neg)? (num1*4\'d10 + num2) - (num3*4\'d10 + num4):(num3*4\'d10 + num4) - (num1*4\'d10 + num2);\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:91: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (~neg)? (num1*4\'d10 + num2) - (num3*4\'d10 + num4):(num3*4\'d10 + num4) - (num1*4\'d10 + num2);\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:91: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                    result = (~neg)? (num1*4\'d10 + num2) - (num3*4\'d10 + num4):(num3*4\'d10 + num4) - (num1*4\'d10 + num2);\n                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:99: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                result = (num1*4\'d10 + num2) * (num3*4\'d10 + num4);\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:99: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                             : ... In instance calculator\n                result = (num1*4\'d10 + num2) * (num3*4\'d10 + num4);\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:107: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                              : ... In instance calculator\n                        result = (num1*4\'d10 + num2) / (num3*4\'d10 + num4);\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:107: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                              : ... In instance calculator\n                        result = (num1*4\'d10 + num2) / (num3*4\'d10 + num4);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'num2\' generates 4 bits.\n                                                                                              : ... In instance calculator\n        n1 = num1*4\'d10 + num2;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:115: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'num4\' generates 4 bits.\n                                                                                              : ... In instance calculator\n        n2 = num3*4\'d10 + num4; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:118: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 14 bits.\n                                                                                              : ... In instance calculator\n            dig4 = result %10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:122: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 14 bits.\n                                                                                              : ... In instance calculator\n            dig3 = (result/10) %10;     \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:126: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 14 bits.\n                                                                                              : ... In instance calculator\n            dig2 = (result/100) %10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/499596866/Simulation/sources_1/new/calculator.v:130: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 14 bits.\n                                                                                              : ... In instance calculator\n            dig1 = (result/1000) %10;  \n                 ^\n%Error: Exiting due to 27 error(s), 16 warning(s)\n'
module calculator (clk, rst, B, result, n1, n2, mode, neg, out1, out2, out3, out4, out5, out6, out7, out8);

    input clk, rst;
    input [8:0] B;
    output reg [6:0] n1, n2;
    output reg [13:0] result;
     reg [3:0] ssgAnode;
     reg [7:0] ssg;
    output reg mode; 
    
    wire [8:0] in;
    output wire [7:0] out1, out2, out3, out4, out5, out6, out7, out8;
    wire clk_out;
    wire [8:0] key;

    output reg neg;
    reg error;
    reg  pos;
    reg [3:0] num1, num2, num3, num4;
    reg [3:0] dig1, dig2, dig3, dig4;
    reg [1:0] two_bit_counter = 2'b00;
    

    clockDivider #(50000) QD2 (clk, rst, clk_out);

    debouncer ins0 (clk, B[0], in[0]);
    debouncer ins1 (clk, B[1], in[1]);
    debouncer ins2 (clk, B[2], in[2]);
    debouncer ins3 (clk, B[3], in[3]);
    debouncer ins4 (clk, B[4], in[4]);
    debouncer ins5 (clk, B[5], in[5]);
    debouncer ins6 (clk, B[6], in[6]);
    debouncer ins7 (clk, B[7], in[7]);
    debouncer ins8 (clk, B[8], in[8]);
   
   edge_det ed0 (clk, rst, in[0], key[0]);
   edge_det ed1 (clk, rst, in[1], key[1]);
   edge_det ed2 (clk, rst, in[2], key[2]);
   edge_det ed3 (clk, rst, in[3], key[3]);
   edge_det ed4 (clk, rst, in[4], key[4]);
   edge_det ed5 (clk, rst, in[5], key[5]);
   edge_det ed6 (clk, rst, in[6], key[6]);
   edge_det ed7 (clk, rst, in[7], key[7]);
   edge_det ed8 (clk, rst, in[8], key[8]);
   
   BCD seg1 (num1, 0, out1);
   BCD seg2 (num2, 1, out2);
   BCD seg3 (num3, 0, out3);
   BCD seg4 (num4, 0, out4);
   BCD seg5 (dig1, 0, out5);
   BCD seg6 (dig2, 0, out6);
   BCD seg7 (dig3, 0, out7);
   BCD seg8 (dig4, 0, out8);
   

    always @(posedge clk) 
    begin
        if (rst)
            begin
                num1 = 0;
                num2 = 0;
                num3 = 0;
                num4 = 0;
                result = 0;
                mode = 1;
                error = 0;
                neg = 0;
            end
      else 
          begin
          

            if (B[8]) if (mode) num1 = (num1 == 4'd9)? 4'd0 : num1 + 4'd1;
            if (B[7]) if (mode) num2 = (num2 == 4'd9)? 4'd0 : num2 + 4'd1;
            if (B[6]) if (mode) num3 = (num3 == 4'd9)? 4'd0 : num3 + 4'd1;
            if (B[5]) if (mode) num4 = (num4 == 4'd9)? 4'd0 : num4 + 4'd1;
               

            if (B[4])
                begin
                    neg = 0;
                    error = 0;
                    result = (num1*'d10 + num2) + (num3*'d10 + num4);
                    mode = 0;
                end
            if (B[3])
                begin
                    error = 0;
                    neg =0;
                    neg = (num1*'d10 + num2 < num3*'d10 + num4);
                    result = (~neg)? (num1*4'd10 + num2) - (num3*4'd10 + num4):(num3*4'd10 + num4) - (num1*4'd10 + num2);
                    if (neg) pos = (result > 'd9);
                    mode = 0;
                end
            if (B[2])
            begin
                neg = 0;
                error = 0;
                result = (num1*4'd10 + num2) * (num3*4'd10 + num4);
                mode = 0;
            end
            if (B[1])
                begin
                    neg = 0;
                    error = (num3*4'd10 + num4 == 0);
                    if (~error)
                        result = (num1*4'd10 + num2) / (num3*4'd10 + num4);
                    mode = 0;
                end
               
                if (B[0]) mode = ~mode;
            end
       
        n1 = num1*4'd10 + num2;
        n2 = num3*4'd10 + num4; 
             
        if (result > 0) 
            dig4 = result %10;
        else dig4 = 4'd0;
        
        if (result > 0) 
            dig3 = (result/10) %10;     
        else dig3 = 4'd0;
       
        if (result > 0)       
            dig2 = (result/100) %10;
        else dig2 = 4'd0;  
        
        if (result > 0) 
            dig1 = (result/1000) %10;  
        else dig1 = 4'd0;
 
   end

    always @(posedge clk_out) 
    begin
        if (mode) 
            begin
                if (two_bit_counter == 2'b00)
                    begin
                        ssg = out1;
                        ssgAnode = 4'b1110;
                    end
                   
                    else if (two_bit_counter == 2'b01)
                    begin
                        ssg = out2;
                        ssgAnode = 4'b1101;
                    end
           
                    else if (two_bit_counter == 2'b10)
                    begin
                        ssg = out3;
                        ssgAnode = 4'b1011;
                    end
           
                    else if (two_bit_counter == 2'b11)
                    begin
                        ssg = out4;
                        ssgAnode = 4'b0111;
                    end
            end
        else
            begin
                if (error)
                    begin
                        if (two_bit_counter == 2'b00)
                        begin
                            ssg = 8'b11110000;
                            ssgAnode = 4'b0111;
                        end
                       
                        else if (two_bit_counter == 2'b01)
                        begin
                            ssg = 8'b00000010;
                            ssgAnode = 4'b1011;
                        end
                       
                        else if (two_bit_counter == 2'b10)
                        begin
                            ssg = 8'b11110000;
                            ssgAnode = 4'b1101;
                        end
                       
                        else if (two_bit_counter == 2'b11)
                        begin
                            ssg = 8'b01100000;
                            ssgAnode = 4'b1110;
                        end
                    end
               
                else
                begin
                    if (two_bit_counter == 2'b00)
                        begin
                            ssg = out5;
                            ssgAnode = 4'b1110;
                        end
                       
                        else if (two_bit_counter == 2'b01)
                        begin
                            ssg = (pos & neg)? 8'b11111101 : out6;
                            ssgAnode = 4'b1101;
                        end
               
                        else if (two_bit_counter == 2'b10)
                        begin
                            ssg = (~pos & neg)? 8'b11111101 : out7;
                            ssgAnode = 4'b1011;
                        end
               
                        else if (two_bit_counter == 2'b11)
                        begin
                            ssg = out8;
                            ssgAnode = 4'b0111;
                        end
                end
            end
       
        two_bit_counter  <= two_bit_counter  + 'd1;  
    end

endmodule
module calculator (clk, rst, B, result, n1, n2, mode, neg, out1, out2, out3, out4, out5, out6, out7, out8);


    input clk, rst;
    input [8:0] B;
    output reg [6:0] n1, n2;
    output reg [13:0] result;
     reg [3:0] ssgAnode;
     reg [7:0] ssg;
    output reg mode; 
    
    wire [8:0] in;
    output wire [7:0] out1, out2, out3, out4, out5, out6, out7, out8;
    wire clk_out;
    wire [8:0] key;

    output reg neg;
    reg error;
    reg  pos;
    reg [3:0] num1, num2, num3, num4;
    reg [3:0] dig1, dig2, dig3, dig4;
    reg [1:0] two_bit_counter = 2'b00;
    

    clockDivider #(50000) QD2 (clk, rst, clk_out);

    debouncer ins0 (clk, B[0], in[0]);
    debouncer ins1 (clk, B[1], in[1]);
    debouncer ins2 (clk, B[2], in[2]);
    debouncer ins3 (clk, B[3], in[3]);
    debouncer ins4 (clk, B[4], in[4]);
    debouncer ins5 (clk, B[5], in[5]);
    debouncer ins6 (clk, B[6], in[6]);
    debouncer ins7 (clk, B[7], in[7]);
    debouncer ins8 (clk, B[8], in[8]);
   
   edge_det ed0 (clk, rst, in[0], key[0]);
   edge_det ed1 (clk, rst, in[1], key[1]);
   edge_det ed2 (clk, rst, in[2], key[2]);
   edge_det ed3 (clk, rst, in[3], key[3]);
   edge_det ed4 (clk, rst, in[4], key[4]);
   edge_det ed5 (clk, rst, in[5], key[5]);
   edge_det ed6 (clk, rst, in[6], key[6]);
   edge_det ed7 (clk, rst, in[7], key[7]);
   edge_det ed8 (clk, rst, in[8], key[8]);
   
   BCD seg1 (num1, 0, out1);
   BCD seg2 (num2, 1, out2);
   BCD seg3 (num3, 0, out3);
   BCD seg4 (num4, 0, out4);
   BCD seg5 (dig1, 0, out5);
   BCD seg6 (dig2, 0, out6);
   BCD seg7 (dig3, 0, out7);
   BCD seg8 (dig4, 0, out8);
   

    always @(posedge clk) 
    begin
        if (rst)
            begin
                num1 = 0;
                num2 = 0;
                num3 = 0;
                num4 = 0;
                result = 0;
                mode = 1;
                error = 0;
                neg = 0;
            end
      else 
          begin
          

            if (B[8]) if (mode) num1 = (num1 == 4'd9)? 4'd0 : num1 + 4'd1;
            if (B[7]) if (mode) num2 = (num2 == 4'd9)? 4'd0 : num2 + 4'd1;
            if (B[6]) if (mode) num3 = (num3 == 4'd9)? 4'd0 : num3 + 4'd1;
            if (B[5]) if (mode) num4 = (num4 == 4'd9)? 4'd0 : num4 + 4'd1;
               

            if (B[4])
                begin
                    neg = 0;
                    error = 0;
                    result = (num1*'d10 + num2) + (num3*'d10 + num4);
                    mode = 0;
                end
            if (B[3])
                begin
                    error = 0;
                    neg =0;
                    neg = (num1*'d10 + num2 < num3*'d10 + num4);
                    result = (~neg)? (num1*4'd10 + num2) - (num3*4'd10 + num4):(num3*4'd10 + num4) - (num1*4'd10 + num2);
                    if (neg) pos = (result > 'd9);
                    mode = 0;
                end
            if (B[2])
            begin
                neg = 0;
                error = 0;
                result = (num1*4'd10 + num2) * (num3*4'd10 + num4);
                mode = 0;
            end
            if (B[1])
                begin
                    neg = 0;
                    error = (num3*4'd10 + num4 == 0);
                    if (~error)
                        result = (num1*4'd10 + num2) / (num3*4'd10 + num4);
                    mode = 0;
                end
               
                if (B[0]) mode = ~mode;
            end
       
        n1 = num1*4'd10 + num2;
        n2 = num3*4'd10 + num4; 
             
        if (result > 0) 
            dig4 = result %10;
        else dig4 = 4'd0;
        
        if (result > 0) 
            dig3 = (result/10) %10;     
        else dig3 = 4'd0;
       
        if (result > 0)       
            dig2 = (result/100) %10;
        else dig2 = 4'd0;  
        
        if (result > 0) 
            dig1 = (result/1000) %10;  
        else dig1 = 4'd0;
 
   end

    always @(posedge clk_out) 
    begin
        if (mode) 
            begin
                if (two_bit_counter == 2'b00)
                    begin
                        ssg = out1;
                        ssgAnode = 4'b1110;
                    end
                   
                    else if (two_bit_counter == 2'b01)
                    begin
                        ssg = out2;
                        ssgAnode = 4'b1101;
                    end
           
                    else if (two_bit_counter == 2'b10)
                    begin
                        ssg = out3;
                        ssgAnode = 4'b1011;
                    end
           
                    else if (two_bit_counter == 2'b11)
                    begin
                        ssg = out4;
                        ssgAnode = 4'b0111;
                    end
            end
        else
            begin
                if (error)
                    begin
                        if (two_bit_counter == 2'b00)
                        begin
                            ssg = 8'b11110000;
                            ssgAnode = 4'b0111;
                        end
                       
                        else if (two_bit_counter == 2'b01)
                        begin
                            ssg = 8'b00000010;
                            ssgAnode = 4'b1011;
                        end
                       
                        else if (two_bit_counter == 2'b10)
                        begin
                            ssg = 8'b11110000;
                            ssgAnode = 4'b1101;
                        end
                       
                        else if (two_bit_counter == 2'b11)
                        begin
                            ssg = 8'b01100000;
                            ssgAnode = 4'b1110;
                        end
                    end
               
                else
                begin
                    if (two_bit_counter == 2'b00)
                        begin
                            ssg = out5;
                            ssgAnode = 4'b1110;
                        end
                       
                        else if (two_bit_counter == 2'b01)
                        begin
                            ssg = (pos & neg)? 8'b11111101 : out6;
                            ssgAnode = 4'b1101;
                        end
               
                        else if (two_bit_counter == 2'b10)
                        begin
                            ssg = (~pos & neg)? 8'b11111101 : out7;
                            ssgAnode = 4'b1011;
                        end
               
                        else if (two_bit_counter == 2'b11)
                        begin
                            ssg = out8;
                            ssgAnode = 4'b0111;
                        end
                end
            end
       
        two_bit_counter  <= two_bit_counter  + 'd1;  
    end

endmodule