data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n                #1728000 mode = 1\'b0;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n                #72000 $stop;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        always #10 clk[0] = ~clk[0];\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[0] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[0] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[1] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[1] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[2] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[2] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n                #20 mode = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[0] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[0] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[1] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[1] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[2] = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n                #20 clk[2] = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n                #20 $stop;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n                #240 rst = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n                #100 $stop;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        always #10 clk = ~clk;\n               ^\n%Warning-MULTITOP: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:40: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                     : ... Top module \'TIME_MODULE_tb_1\'\nmodule TIME_MODULE_tb_1;\n       ^~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'TIME_MODULE_tb_2\'\nmodule TIME_MODULE_tb_2;\n       ^~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'TIME_SEG_UNIT_tb\'\nmodule TIME_SEG_UNIT_tb;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:93: Cannot find file containing module: \'TIME_SEG_UNIT\'\n        TIME_SEG_UNIT #(\n        ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/TIME_SEG_UNIT\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/TIME_SEG_UNIT.v\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/TIME_SEG_UNIT.sv\n             TIME_SEG_UNIT\n             TIME_SEG_UNIT.v\n             TIME_SEG_UNIT.sv\n             obj_dir/TIME_SEG_UNIT\n             obj_dir/TIME_SEG_UNIT.v\n             obj_dir/TIME_SEG_UNIT.sv\n%Error: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:52: Cannot find file containing module: \'TIME_MODULE\'\n        TIME_MODULE time_module__ (\n        ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:60: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                  : ... In instance TIME_MODULE_tb_2\n                clk = 1\'b0;\n                    ^\n%Error: data/full_repos/permissive/434187796/testbench/TIME_MODULE_tb.v:15: Cannot find file containing module: \'TIME_MODULE\'\n        TIME_MODULE time_module_ (\n        ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TIME_MODULE_tb_2;
        reg [2:0] clk;
        reg rst;
        reg mode;
        wire [23:0] time_data;
        wire [3:0] time_data_5;
        wire [3:0] time_data_4;
        wire [3:0] time_data_3;
        wire [3:0] time_data_2;
        wire [3:0] time_data_1;
        wire [3:0] time_data_0;

        TIME_MODULE time_module__ (
                .clk(clk),
                .rst(rst),
                .mode(mode),
                .time_data(time_data)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b1;
                mode = 1'b0;
                #20 clk[0] = 1'b1;
                #20 clk[0] = 1'b0;
                #20 clk[1] = 1'b1;
                #20 clk[1] = 1'b0;
                #20 clk[2] = 1'b1;
                #20 clk[2] = 1'b0;
                #20 mode = 1'b1;
                #20 clk[0] = 1'b1;
                #20 clk[0] = 1'b0;
                #20 clk[1] = 1'b1;
                #20 clk[1] = 1'b0;
                #20 clk[2] = 1'b1;
                #20 clk[2] = 1'b0;
                #20 $stop;
        end

        assign time_data_5 = time_data[23-:4];
        assign time_data_4 = time_data[19-:4];
        assign time_data_3 = time_data[15-:4];
        assign time_data_2 = time_data[11-:4];
        assign time_data_1 = time_data[07-:4];
        assign time_data_0 = time_data[03-:4];
endmodule
module TIME_MODULE_tb_2;

        reg [2:0] clk;
        reg rst;
        reg mode;
        wire [23:0] time_data;
        wire [3:0] time_data_5;
        wire [3:0] time_data_4;
        wire [3:0] time_data_3;
        wire [3:0] time_data_2;
        wire [3:0] time_data_1;
        wire [3:0] time_data_0;

        TIME_MODULE time_module__ (
                .clk(clk),
                .rst(rst),
                .mode(mode),
                .time_data(time_data)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b1;
                mode = 1'b0;
                #20 clk[0] = 1'b1;
                #20 clk[0] = 1'b0;
                #20 clk[1] = 1'b1;
                #20 clk[1] = 1'b0;
                #20 clk[2] = 1'b1;
                #20 clk[2] = 1'b0;
                #20 mode = 1'b1;
                #20 clk[0] = 1'b1;
                #20 clk[0] = 1'b0;
                #20 clk[1] = 1'b1;
                #20 clk[1] = 1'b0;
                #20 clk[2] = 1'b1;
                #20 clk[2] = 1'b0;
                #20 $stop;
        end

        assign time_data_5 = time_data[23-:4];
        assign time_data_4 = time_data[19-:4];
        assign time_data_3 = time_data[15-:4];
        assign time_data_2 = time_data[11-:4];
        assign time_data_1 = time_data[07-:4];
        assign time_data_0 = time_data[03-:4];
endmodule