data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ControlMux(
    input regrt,
    input [4:0] rd, rt,
    output [4:0] wn
    );
    assign wn = regrt?rt:rd;
endmodule
module ControlMux(
    input regrt,
    input [4:0] rd, rt,
    output [4:0] wn
    );

    assign wn = regrt?rt:rd;
endmodule