data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:169: Signal definition not found, creating implicitly: \'scr0_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_addr\'\n    .BUF_WE(scr0_buf_we),\n            ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:200: Signal definition not found, creating implicitly: \'scr1_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_we\'\n    .BUF_WE(scr1_buf_we),\n            ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:231: Signal definition not found, creating implicitly: \'scr2_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_we\'\n    .BUF_WE(scr2_buf_we),\n            ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:341: Operator SHIFTR expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & \'h7C0;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:341: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'y\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & \'h7C0;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:342: Operator SHIFTR expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_X_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & \'h3E);\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:342: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'x\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & \'h3E);\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:354: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [13:0] rd_scr_q_addr = (priority_i*21) + scr_queue_i;\n                          ^\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:363: Cannot find file containing module: \'jtframe_dual_ram\'\njtframe_dual_ram #(.dw(64), .aw(9)) u_scr_pri_q(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram.v\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram.sv\n             jtframe_dual_ram\n             jtframe_dual_ram.v\n             jtframe_dual_ram.sv\n             obj_dir/jtframe_dual_ram\n             obj_dir/jtframe_dual_ram.v\n             obj_dir/jtframe_dual_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:380: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] tile_num_attr = scr_q_out[63:32];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:381: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [11:0] tile_palette = ((scr_q_out[63:32] >> 12 ) & \'h07F0);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:387: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [3:0] tile_code = (((tile_line >> (tx*4)) & \'h0F));\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:388: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:388: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:390: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'VRENDER\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:390: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:392: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire tile_down = (lines_down >> 3);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:441: Operator ADD expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'VRENDER\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:441: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:465: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        SCR_GP9001RAM_GCU_ADDR <= row+column+1;  \n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:486: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        scroll_queue_priority_n_scan_buf_i <= scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:504: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    SCR_GP9001RAM_GCU_ADDR <= row+column;  \n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:508: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'SCR_GP9001RAM_GCU_DOUT\' generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        tile_num<=SCR_GP9001RAM_GCU_DOUT;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:507: Operator LTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'SCR_GP9001RAM_GCU_DOUT\' generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    if(SCR_GP9001RAM_GCU_DOUT > 0 && SCR_GP9001RAM_GCU_DOUT <= max_tile) begin\n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:517: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    priority_l = (tile_attrib>>8) & \'h0F;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:520: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'x\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:520: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_X_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:521: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'y\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:521: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:529: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    pri_has_tile[priority_i]<=0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:536: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER<=(tile_num_attr & \'h1FFF) << 2;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:537: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'tile_down\' generates 1 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:537: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'scr_x_render\' generates 2 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;\n                                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:538: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_BANK<=(tile_num_attr >> 13) & 7;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:570: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            scroll_queue_priority_n_scan_buf_i<=scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:533: Operator LT expects 16 bits on the RHS, but RHS\'s VARREF \'scroll_queue_priority_n_scan_buf_i\' generates 5 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    if(scr_queue_i < scroll_queue_priority_n_scan_buf_i) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_palette\' generates 12 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_code\' generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:606: Operator NEGATE expects 16 bits on the LHS, but LHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:606: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:614: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1FF;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_palette\' generates 12 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_code\' generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:617: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1ff;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:621: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1ff;\n                                ^~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:99: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr0_line (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:111: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr1_line (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:123: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr2_line (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 49 warning(s)\n'
module raizing_scroll_qr (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    input FLIPX,

    output reg [12:0] SCR_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR_GP9001RAM_GCU_DOUT,

    output reg GFXSCR_CS,
    input GFXSCR_OK,
    output reg [14:0] SCR_TILE_NUMBER,
    output reg [15:0] SCR_TILE_NUMBER_OFFS,
    output reg [3:0] SCR_TILE_BANK,
    input  [31:0] SCR_GFX_DATA,

    input signed [12:0] SCROLL_X_POS,
    input signed [12:0] SCROLL_Y_POS,

    output reg BUSY,
    output reg DONE,
    input START,

    output reg [8:0] BUF_ADDR,
    output reg [14:0] BUF_DATA,
    output reg BUF_WE,

    input [1:0] DEBUG_SCRN
);

localparam max_tile = ('h1000000-1)>>7, max_priority = 16;

reg [7:0] st = 0;
reg [8:0] x = 0;
reg [8:0] y = 0;
wire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & 'h7C0;
wire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & 'h3E);
reg [16:0] tile_num = 0;
reg [15:0] tile_attrib = 0;
reg [4:0] priority_l = 0; 
reg [15:0] scr_queue_i = 0;
reg [4:0] priority_i = 0;
reg [(8*max_priority)-1:0] scroll_queue_priority_n = {max_priority{8'h00}};
reg [4:0] scroll_queue_priority_n_scan_buf_i = 0;
reg [15:0] pri_has_tile = 16'd0;

reg [63:0] wr_scr_q;
reg [8:0] wr_scr_q_addr;
wire [13:0] rd_scr_q_addr = (priority_i*21) + scr_queue_i;
reg scr_q_we;
wire [63:0] scr_q_out;
reg [2:0] tx = 0;

reg [1:0] scr_x_render = 0;

wire pri_q_erase = scr_x_render == 'd2;

jtframe_dual_ram #(.dw(64), .aw(9)) u_scr_pri_q(
    .clk0(CLK96),
    .clk1(CLK96),
    .data0  (wr_scr_q),
    .addr0  (wr_scr_q_addr),
    .we0    (scr_q_we),
    .q0     (),

    .data1  (64'h0),
    .addr1  (rd_scr_q_addr),
    .we1    (pri_q_erase),
    .q1     (scr_q_out)
);


wire signed [15:0] tile_x_pos = scr_q_out[31:16];
wire signed [15:0] tile_y_pos = scr_q_out[15:0];
wire [15:0] tile_num_attr = scr_q_out[63:32];
wire [11:0] tile_palette = ((scr_q_out[63:32] >> 12 ) & 'h07F0);

reg signed [15:0] xpos_t = 0, ypos_t = 0;


reg [31:0] tile_line;
wire [3:0] tile_code = (((tile_line >> (tx*4)) & 'h0F));
wire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);

wire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);
wire [15:0] excess_line = ((lines_down & 7) << 2);
wire tile_down = (lines_down >> 3);









wire [7:0] nb_pixels = {|SCR_GFX_DATA[31:28], |SCR_GFX_DATA[27:24], |SCR_GFX_DATA[23:20], |SCR_GFX_DATA[19:16], 
                        |SCR_GFX_DATA[15:12], |SCR_GFX_DATA[11:8], |SCR_GFX_DATA[7:4], |SCR_GFX_DATA[3:0]};
reg [7:0] drawn_pixels = 8'h0;



always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
        st<=0;
        SCR_GP9001RAM_GCU_ADDR<=0;
        BUSY<=1'b0;
        DONE<=1'b0;
        x<=0;
        y <= 0;
        tile_num<=0;
        tile_attrib=0;
        priority_l = 0;
        scroll_queue_priority_n_scan_buf_i = 0;
        scroll_queue_priority_n<={max_priority{8'h00}};
        pri_has_tile <= 16'd0;
        BUF_WE<=1'b0;
        SCR_TILE_NUMBER<=0;
        SCR_TILE_NUMBER_OFFS<= 0;
        SCR_TILE_BANK<=0;
        GFXSCR_CS<=1'b0;
        scr_x_render<=0;
        wr_scr_q<=0;
        wr_scr_q_addr<=0;
        priority_i=0;
        scr_queue_i<=0;
        scr_q_we<=1'b0;
    end else begin
        if(START && !BUSY && !DONE) begin

            BUSY<=1'b1;
            DONE<=1'b0;
            st<=0;
            SCR_GP9001RAM_GCU_ADDR<=0;
            x<=0;
            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;
            tile_num<=0;
            tile_attrib=0;
            priority_l = 0;
            scr_q_we<=1'b0;
            scroll_queue_priority_n_scan_buf_i = 0;
            BUF_WE<=1'b0;
            scr_queue_i<=0;
            scroll_queue_priority_n<={max_priority{8'h00}};
            pri_has_tile <= 16'd0;
            wr_scr_q<=0;
            wr_scr_q_addr<=0;
            priority_i=0;
            scr_x_render<=0;
            SCR_TILE_NUMBER<=0;
            SCR_TILE_NUMBER_OFFS<= 0;
            SCR_TILE_BANK<=0;
            GFXSCR_CS<=1'b0;
        end else if(BUSY && !DONE) begin
            st<=st+1;
            case(st)
                0: begin

                    if(x<21) begin
                        SCR_GP9001RAM_GCU_ADDR <= row+column+1;
                        scr_q_we<=1'b0;
                    end else begin

                        priority_i = pri_has_tile[0] ? 0 :
                                    pri_has_tile[1] ? 1 :
                                    pri_has_tile[2] ? 2 :
                                    pri_has_tile[3] ? 3 :
                                    pri_has_tile[4] ? 4 :
                                    pri_has_tile[5] ? 5 :
                                    pri_has_tile[6] ? 6 :
                                    pri_has_tile[7] ? 7 :
                                    pri_has_tile[8] ? 8 :
                                    pri_has_tile[9] ? 9 :
                                    pri_has_tile[10] ? 10 :
                                    pri_has_tile[11] ? 11 :
                                    pri_has_tile[12] ? 12 :
                                    pri_has_tile[13] ? 13 :
                                    pri_has_tile[14] ? 14 :
                                    pri_has_tile[15] ? 15 :
                                    16;
                        scroll_queue_priority_n_scan_buf_i <= scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];
                        scr_queue_i <= 0;
                        scr_x_render <= 0;
                        if(scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8] > 0) begin
                            x<=0;
                            st<=5;
                        end else begin
                            BUSY<=1'b0;
                            DONE<=1'b1;
                            BUF_WE<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=0;
                            st<=0;
                            x<=0;
                        end
                    end
                end
                1: begin
                    SCR_GP9001RAM_GCU_ADDR <= row+column;
                end
                2: begin
                    if(SCR_GP9001RAM_GCU_DOUT > 0 && SCR_GP9001RAM_GCU_DOUT <= max_tile) begin
                        tile_num<=SCR_GP9001RAM_GCU_DOUT;
                        scr_q_we<=1'b1;
                    end else begin
                        st<=0;
                        x<=x+1;
                    end
                end
                3: begin
                    tile_attrib = SCR_GP9001RAM_GCU_DOUT;
                    priority_l = (tile_attrib>>8) & 'h0F;
                    pri_has_tile[priority_l & 'h0F] <= 1'b1;
                    scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8] <= scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8] + 1;
                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));
                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));
                    wr_scr_q<={tile_attrib[15:0], tile_num[15:0], xpos_t, ypos_t};
                    wr_scr_q_addr<=((priority_l*21) + scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8]);

                    x<=x+1;
                    st<=0;
                end
                5: begin
                    pri_has_tile[priority_i]<=0;
                    st<=6;
                end
                6: begin
                    if(scr_queue_i < scroll_queue_priority_n_scan_buf_i) begin
                        if(tile_num_attr > 0 ) begin
                            GFXSCR_CS<=1'b1;
                            SCR_TILE_NUMBER<=(tile_num_attr & 'h1FFF) << 2;
                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;
                            SCR_TILE_BANK<=(tile_num_attr >> 13) & 7;
                            st<=7;
                        end else begin
                            GFXSCR_CS<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=scr_queue_i + 1;
                            st<=5;
                        end
                    end else begin
                        if(pri_has_tile > 0) begin
                            st<=5;

                            scr_queue_i<=0;
                            scr_x_render<=0;

                            priority_i = pri_has_tile[0] ? 0 :
                                         pri_has_tile[1] ? 1 :
                                         pri_has_tile[2] ? 2 :
                                         pri_has_tile[3] ? 3 :
                                         pri_has_tile[4] ? 4 :
                                         pri_has_tile[5] ? 5 :
                                         pri_has_tile[6] ? 6 :
                                         pri_has_tile[7] ? 7 :
                                         pri_has_tile[8] ? 8 :
                                         pri_has_tile[9] ? 9 :
                                         pri_has_tile[10] ? 10 :
                                         pri_has_tile[11] ? 11 :
                                         pri_has_tile[12] ? 12 :
                                         pri_has_tile[13] ? 13 :
                                         pri_has_tile[14] ? 14 :
                                         pri_has_tile[15] ? 15 :
                                         16;
                            scroll_queue_priority_n_scan_buf_i<=scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];
                        end else begin
                            BUSY<=1'b0;
                            DONE<=1'b1;
                            BUF_WE<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=0;
                            st<=0;
                            x<=0;
                        end
                    end
                end
                7: st<=8;
                8: begin
                    if(GFXSCR_OK) begin
                        SCR_TILE_NUMBER<=0;
                        SCR_TILE_NUMBER_OFFS<= 0;
                        SCR_TILE_BANK<=0;
                        GFXSCR_CS<=1'b0;


                            tile_line<=SCR_GFX_DATA;
                            tx<= 0;
                            drawn_pixels = 8'h0;
                            BUF_WE<=1'b1;
                            st<=9;
                    end else begin
                        st<=st;
                    end
                end
                9: begin
                    tx <= (tx + 1);
                    if( tile_code > 0 ) begin

                        drawn_pixels[tx] = 1'b1;
                        if(tile_x_pos <= -16 || tile_x_pos >=320) begin
                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin

                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&'h1FF;
                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;
                            end
                        end else if((tile_x_pos > -16 && tile_x_pos <320)) begin


                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1FF;
                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;
                        end else begin
                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1ff;
                            BUF_DATA<=0;
                        end
                    end else begin
                        BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1ff;
                        BUF_DATA<=0;
                    end


                        if(tx==7) begin
                        st<=10;
                        scr_x_render<=scr_x_render+1;
                    end
                    else st<=st;
                end
                10: begin
                    if(scr_x_render == 2) begin
                        scr_queue_i<=scr_queue_i+1;
                        scr_x_render<=0;
                    end
                    drawn_pixels = 8'h0;
                    tx<=0;
                    st<=5;
                    BUF_WE<=1'b0;
                end
            endcase 
        end else begin
            BUSY<=1'b0;
            DONE<=1'b0;
            BUF_WE<=1'b0;
            x<=0;
            st<=0;
        end
    end
end

endmodule
module raizing_scroll_qr (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    input FLIPX,

    output reg [12:0] SCR_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR_GP9001RAM_GCU_DOUT,

    output reg GFXSCR_CS,
    input GFXSCR_OK,
    output reg [14:0] SCR_TILE_NUMBER,
    output reg [15:0] SCR_TILE_NUMBER_OFFS,
    output reg [3:0] SCR_TILE_BANK,
    input  [31:0] SCR_GFX_DATA,

    input signed [12:0] SCROLL_X_POS,
    input signed [12:0] SCROLL_Y_POS,

    output reg BUSY,
    output reg DONE,
    input START,

    output reg [8:0] BUF_ADDR,
    output reg [14:0] BUF_DATA,
    output reg BUF_WE,

    input [1:0] DEBUG_SCRN
);


localparam max_tile = ('h1000000-1)>>7, max_priority = 16;

reg [7:0] st = 0;
reg [8:0] x = 0;
reg [8:0] y = 0;
wire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & 'h7C0;
wire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & 'h3E);
reg [16:0] tile_num = 0;
reg [15:0] tile_attrib = 0;
reg [4:0] priority_l = 0; 
reg [15:0] scr_queue_i = 0;
reg [4:0] priority_i = 0;
reg [(8*max_priority)-1:0] scroll_queue_priority_n = {max_priority{8'h00}};
reg [4:0] scroll_queue_priority_n_scan_buf_i = 0;
reg [15:0] pri_has_tile = 16'd0;

reg [63:0] wr_scr_q;
reg [8:0] wr_scr_q_addr;
wire [13:0] rd_scr_q_addr = (priority_i*21) + scr_queue_i;
reg scr_q_we;
wire [63:0] scr_q_out;
reg [2:0] tx = 0;

reg [1:0] scr_x_render = 0;

wire pri_q_erase = scr_x_render == 'd2;

jtframe_dual_ram #(.dw(64), .aw(9)) u_scr_pri_q(
    .clk0(CLK96),
    .clk1(CLK96),
    .data0  (wr_scr_q),
    .addr0  (wr_scr_q_addr),
    .we0    (scr_q_we),
    .q0     (),

    .data1  (64'h0),
    .addr1  (rd_scr_q_addr),
    .we1    (pri_q_erase),
    .q1     (scr_q_out)
);


wire signed [15:0] tile_x_pos = scr_q_out[31:16];
wire signed [15:0] tile_y_pos = scr_q_out[15:0];
wire [15:0] tile_num_attr = scr_q_out[63:32];
wire [11:0] tile_palette = ((scr_q_out[63:32] >> 12 ) & 'h07F0);

reg signed [15:0] xpos_t = 0, ypos_t = 0;


reg [31:0] tile_line;
wire [3:0] tile_code = (((tile_line >> (tx*4)) & 'h0F));
wire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);

wire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);
wire [15:0] excess_line = ((lines_down & 7) << 2);
wire tile_down = (lines_down >> 3);









wire [7:0] nb_pixels = {|SCR_GFX_DATA[31:28], |SCR_GFX_DATA[27:24], |SCR_GFX_DATA[23:20], |SCR_GFX_DATA[19:16], 
                        |SCR_GFX_DATA[15:12], |SCR_GFX_DATA[11:8], |SCR_GFX_DATA[7:4], |SCR_GFX_DATA[3:0]};
reg [7:0] drawn_pixels = 8'h0;



always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
        st<=0;
        SCR_GP9001RAM_GCU_ADDR<=0;
        BUSY<=1'b0;
        DONE<=1'b0;
        x<=0;
        y <= 0;
        tile_num<=0;
        tile_attrib=0;
        priority_l = 0;
        scroll_queue_priority_n_scan_buf_i = 0;
        scroll_queue_priority_n<={max_priority{8'h00}};
        pri_has_tile <= 16'd0;
        BUF_WE<=1'b0;
        SCR_TILE_NUMBER<=0;
        SCR_TILE_NUMBER_OFFS<= 0;
        SCR_TILE_BANK<=0;
        GFXSCR_CS<=1'b0;
        scr_x_render<=0;
        wr_scr_q<=0;
        wr_scr_q_addr<=0;
        priority_i=0;
        scr_queue_i<=0;
        scr_q_we<=1'b0;
    end else begin
        if(START && !BUSY && !DONE) begin

            BUSY<=1'b1;
            DONE<=1'b0;
            st<=0;
            SCR_GP9001RAM_GCU_ADDR<=0;
            x<=0;
            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;
            tile_num<=0;
            tile_attrib=0;
            priority_l = 0;
            scr_q_we<=1'b0;
            scroll_queue_priority_n_scan_buf_i = 0;
            BUF_WE<=1'b0;
            scr_queue_i<=0;
            scroll_queue_priority_n<={max_priority{8'h00}};
            pri_has_tile <= 16'd0;
            wr_scr_q<=0;
            wr_scr_q_addr<=0;
            priority_i=0;
            scr_x_render<=0;
            SCR_TILE_NUMBER<=0;
            SCR_TILE_NUMBER_OFFS<= 0;
            SCR_TILE_BANK<=0;
            GFXSCR_CS<=1'b0;
        end else if(BUSY && !DONE) begin
            st<=st+1;
            case(st)
                0: begin

                    if(x<21) begin
                        SCR_GP9001RAM_GCU_ADDR <= row+column+1;
                        scr_q_we<=1'b0;
                    end else begin

                        priority_i = pri_has_tile[0] ? 0 :
                                    pri_has_tile[1] ? 1 :
                                    pri_has_tile[2] ? 2 :
                                    pri_has_tile[3] ? 3 :
                                    pri_has_tile[4] ? 4 :
                                    pri_has_tile[5] ? 5 :
                                    pri_has_tile[6] ? 6 :
                                    pri_has_tile[7] ? 7 :
                                    pri_has_tile[8] ? 8 :
                                    pri_has_tile[9] ? 9 :
                                    pri_has_tile[10] ? 10 :
                                    pri_has_tile[11] ? 11 :
                                    pri_has_tile[12] ? 12 :
                                    pri_has_tile[13] ? 13 :
                                    pri_has_tile[14] ? 14 :
                                    pri_has_tile[15] ? 15 :
                                    16;
                        scroll_queue_priority_n_scan_buf_i <= scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];
                        scr_queue_i <= 0;
                        scr_x_render <= 0;
                        if(scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8] > 0) begin
                            x<=0;
                            st<=5;
                        end else begin
                            BUSY<=1'b0;
                            DONE<=1'b1;
                            BUF_WE<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=0;
                            st<=0;
                            x<=0;
                        end
                    end
                end
                1: begin
                    SCR_GP9001RAM_GCU_ADDR <= row+column;
                end
                2: begin
                    if(SCR_GP9001RAM_GCU_DOUT > 0 && SCR_GP9001RAM_GCU_DOUT <= max_tile) begin
                        tile_num<=SCR_GP9001RAM_GCU_DOUT;
                        scr_q_we<=1'b1;
                    end else begin
                        st<=0;
                        x<=x+1;
                    end
                end
                3: begin
                    tile_attrib = SCR_GP9001RAM_GCU_DOUT;
                    priority_l = (tile_attrib>>8) & 'h0F;
                    pri_has_tile[priority_l & 'h0F] <= 1'b1;
                    scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8] <= scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8] + 1;
                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));
                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));
                    wr_scr_q<={tile_attrib[15:0], tile_num[15:0], xpos_t, ypos_t};
                    wr_scr_q_addr<=((priority_l*21) + scroll_queue_priority_n[((priority_l+1)<<3)-1 -: 8]);

                    x<=x+1;
                    st<=0;
                end
                5: begin
                    pri_has_tile[priority_i]<=0;
                    st<=6;
                end
                6: begin
                    if(scr_queue_i < scroll_queue_priority_n_scan_buf_i) begin
                        if(tile_num_attr > 0 ) begin
                            GFXSCR_CS<=1'b1;
                            SCR_TILE_NUMBER<=(tile_num_attr & 'h1FFF) << 2;
                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;
                            SCR_TILE_BANK<=(tile_num_attr >> 13) & 7;
                            st<=7;
                        end else begin
                            GFXSCR_CS<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=scr_queue_i + 1;
                            st<=5;
                        end
                    end else begin
                        if(pri_has_tile > 0) begin
                            st<=5;

                            scr_queue_i<=0;
                            scr_x_render<=0;

                            priority_i = pri_has_tile[0] ? 0 :
                                         pri_has_tile[1] ? 1 :
                                         pri_has_tile[2] ? 2 :
                                         pri_has_tile[3] ? 3 :
                                         pri_has_tile[4] ? 4 :
                                         pri_has_tile[5] ? 5 :
                                         pri_has_tile[6] ? 6 :
                                         pri_has_tile[7] ? 7 :
                                         pri_has_tile[8] ? 8 :
                                         pri_has_tile[9] ? 9 :
                                         pri_has_tile[10] ? 10 :
                                         pri_has_tile[11] ? 11 :
                                         pri_has_tile[12] ? 12 :
                                         pri_has_tile[13] ? 13 :
                                         pri_has_tile[14] ? 14 :
                                         pri_has_tile[15] ? 15 :
                                         16;
                            scroll_queue_priority_n_scan_buf_i<=scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];
                        end else begin
                            BUSY<=1'b0;
                            DONE<=1'b1;
                            BUF_WE<=1'b0;
                            scr_x_render<=0;
                            scr_queue_i<=0;
                            st<=0;
                            x<=0;
                        end
                    end
                end
                7: st<=8;
                8: begin
                    if(GFXSCR_OK) begin
                        SCR_TILE_NUMBER<=0;
                        SCR_TILE_NUMBER_OFFS<= 0;
                        SCR_TILE_BANK<=0;
                        GFXSCR_CS<=1'b0;


                            tile_line<=SCR_GFX_DATA;
                            tx<= 0;
                            drawn_pixels = 8'h0;
                            BUF_WE<=1'b1;
                            st<=9;
                    end else begin
                        st<=st;
                    end
                end
                9: begin
                    tx <= (tx + 1);
                    if( tile_code > 0 ) begin

                        drawn_pixels[tx] = 1'b1;
                        if(tile_x_pos <= -16 || tile_x_pos >=320) begin
                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin

                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&'h1FF;
                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;
                            end
                        end else if((tile_x_pos > -16 && tile_x_pos <320)) begin


                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1FF;
                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;
                        end else begin
                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1ff;
                            BUF_DATA<=0;
                        end
                    end else begin
                        BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&'h1ff;
                        BUF_DATA<=0;
                    end


                        if(tx==7) begin
                        st<=10;
                        scr_x_render<=scr_x_render+1;
                    end
                    else st<=st;
                end
                10: begin
                    if(scr_x_render == 2) begin
                        scr_queue_i<=scr_queue_i+1;
                        scr_x_render<=0;
                    end
                    drawn_pixels = 8'h0;
                    tx<=0;
                    st<=5;
                    BUF_WE<=1'b0;
                end
            endcase 
        end else begin
            BUSY<=1'b0;
            DONE<=1'b0;
            BUF_WE<=1'b0;
            x<=0;
            st<=0;
        end
    end
end

endmodule