data/full_repos/permissive/420611307/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420611307/test.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/420611307/test.v:14: Cannot find file containing module: \'cpu\'\n cpu uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/cpu\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/cpu.v\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 57 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg clk;
	reg rst;
	reg [3:0] display;


	wire [31:0] f;


	cpu uut (
		.clk(clk), 
		.rst(rst), 
		.display(display), 
		.f(f)
	);

	initial begin

		clk = 0;
		rst = 0;
		display = 4'b0001;


		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
	end
endmodule
module test;



	reg clk;
	reg rst;
	reg [3:0] display;


	wire [31:0] f;


	cpu uut (
		.clk(clk), 
		.rst(rst), 
		.display(display), 
		.f(f)
	);

	initial begin

		clk = 0;
		rst = 0;
		display = 4'b0001;


		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
		#100;
		clk = 0;
		#100;
		clk = 1;	
	end
endmodule