data/full_repos/permissive/455223995/src/slzw_lib.v
1: b'%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:50: syntax error, unexpected byte, expecting IDENTIFIER or \'[\' or do or final\n  input   [7:0] byte,\n                ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:56: syntax error, unexpected \'[\', expecting "\'{"\nwire [13:0] num1 = {1\'b0, byte[4:0], byte[7:0]};\n                              ^\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:62: syntax error, unexpected assign\nassign haddr      = num1 + num2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module slzw_fifo
#(parameter
   DEPTH                       = 8,
   WIDTH                       = 32,
   NEARLYFULL                  = (DEPTH/2)
)
(
  input                        clk,
  input                        reset_n,

  input                        clr,

  input                        write,
  input      [WIDTH-1:0]       wdata,

  input                        read,
  output reg [WIDTH-1:0]       rdata,

  output reg                   empty,
  output reg                   full,
  output reg                   nearly_full
);

localparam                     LOG2DEPTH = $clog2(DEPTH);

reg  [WIDTH-1:0]               mem [0:DEPTH-1];
reg  [LOG2DEPTH:0]             wptr;
reg  [LOG2DEPTH:0]             rptr;


wire [LOG2DEPTH:0]             word_count = (wptr - rptr);

always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    wptr                       <= {LOG2DEPTH{1'b0}};
    rptr                       <= {LOG2DEPTH{1'b0}};
    empty                      <= 1'b1;
    full                       <= 1'b0;
    nearly_full                <= 1'b0;
  end
  else
  begin

    if (write && ~full)
    begin
      mem[wptr[LOG2DEPTH-1:0]] <= wdata;
      wptr                     <= wptr + 1;
    end


    if (read && ~empty)
    begin
      rdata                    <= mem[rptr[LOG2DEPTH-1:0]];
      rptr                     <= rptr + 1;
    end




    if (write & ~(read & ~empty))
    begin
      full                     <= (word_count == DEPTH-1)      ? 1'b1 : 1'b0;
      nearly_full              <= (word_count >= NEARLYFULL-1) ? 1'b1 : 1'b0;
      empty                    <= 1'b0;
    end




    if (read & ~(write & ~full))
    begin
      empty                    <= (word_count == 1)            ? 1'b1 : 1'b0;
      nearly_full              <= (word_count <= NEARLYFULL)   ? 1'b0 : 1'b1;
      full                     <= 1'b0;
    end
  end
end

endmodule
module slzw_fifo
#(parameter
   DEPTH                       = 8,
   WIDTH                       = 32,
   NEARLYFULL                  = (DEPTH/2)
)
(
  input                        clk,
  input                        reset_n,

  input                        clr,

  input                        write,
  input      [WIDTH-1:0]       wdata,

  input                        read,
  output reg [WIDTH-1:0]       rdata,

  output reg                   empty,
  output reg                   full,
  output reg                   nearly_full
);


localparam                     LOG2DEPTH = $clog2(DEPTH);

reg  [WIDTH-1:0]               mem [0:DEPTH-1];
reg  [LOG2DEPTH:0]             wptr;
reg  [LOG2DEPTH:0]             rptr;


wire [LOG2DEPTH:0]             word_count = (wptr - rptr);

always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    wptr                       <= {LOG2DEPTH{1'b0}};
    rptr                       <= {LOG2DEPTH{1'b0}};
    empty                      <= 1'b1;
    full                       <= 1'b0;
    nearly_full                <= 1'b0;
  end
  else
  begin

    if (write && ~full)
    begin
      mem[wptr[LOG2DEPTH-1:0]] <= wdata;
      wptr                     <= wptr + 1;
    end


    if (read && ~empty)
    begin
      rdata                    <= mem[rptr[LOG2DEPTH-1:0]];
      rptr                     <= rptr + 1;
    end




    if (write & ~(read & ~empty))
    begin
      full                     <= (word_count == DEPTH-1)      ? 1'b1 : 1'b0;
      nearly_full              <= (word_count >= NEARLYFULL-1) ? 1'b1 : 1'b0;
      empty                    <= 1'b0;
    end




    if (read & ~(write & ~full))
    begin
      empty                    <= (word_count == 1)            ? 1'b1 : 1'b0;
      nearly_full              <= (word_count <= NEARLYFULL)   ? 1'b0 : 1'b1;
      full                     <= 1'b0;
    end
  end
end

endmodule