data/full_repos/permissive/43858668/final_verilog/src/clib/c_damq_tracker.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_damq_tracker.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_damq_tracker.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_damq_tracker.v:62: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_damq_tracker.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 4 error(s)\n'
module c_damq_tracker
  (clk, reset, active, push_valid, push_sel_qu, pop_valid, pop_sel_qu, 
   almost_empty_qu, empty_qu, almost_full_qu, full_qu, two_free_qu, errors_qu);

`include "c_functions.v"
`include "c_constants.v"







   parameter num_queues = 4;
   

   parameter num_slots = 32;
   

   parameter fast_almost_empty = 0;
   

   parameter fast_two_free = 0;
   

   parameter enable_bypass = 0;
   

   parameter enable_reservations = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam num_shared_slots
     = enable_reservations ? (num_slots - num_queues) : num_slots;
   

   localparam num_queue_slots
     = enable_reservations ? (1 + num_shared_slots) : num_slots;
   
   



   
   input clk;
   input reset;
   

   input active;
   

   input push_valid;
   

   input [0:num_queues-1] push_sel_qu;
   

   input 		  pop_valid;
   

   input [0:num_queues-1] pop_sel_qu;
   

   output [0:num_queues-1] almost_empty_qu;
   wire [0:num_queues-1]   almost_empty_qu;
   output [0:num_queues-1] empty_qu;
   wire [0:num_queues-1]   empty_qu;
   output [0:num_queues-1] almost_full_qu;
   wire [0:num_queues-1]   almost_full_qu;
   output [0:num_queues-1] full_qu;
   wire [0:num_queues-1]   full_qu;
   output [0:num_queues-1] two_free_qu;
   wire [0:num_queues-1]   two_free_qu;
   

   output [0:num_queues*2-1] errors_qu;
   wire [0:num_queues*2-1]   errors_qu;
   
   




   wire 		     push_shared;
   wire 		     pop_shared;
   
   generate
      
      if(enable_reservations)
	begin
	   
	   wire push_empty;
	   c_select_1ofn
	     #(.num_ports(num_queues),
	       .width(1))
	   push_empty_sel
	     (.select(push_sel_qu),
	      .data_in(empty_qu),
	      .data_out(push_empty));
	   
	   wire pop_almost_empty;
	   c_select_1ofn
	     #(.num_ports(num_queues),
	       .width(1))
	   pop_almost_empty_sel
	     (.select(pop_sel_qu),
	      .data_in(almost_empty_qu),
	      .data_out(pop_almost_empty));
	   
	   wire same_queue;
	   assign same_queue = |(push_sel_qu & pop_sel_qu);
	   
	   assign push_shared = push_valid & ~push_empty & 
				(~pop_valid | (pop_almost_empty & ~same_queue));
	   
	   if(enable_bypass)
	     assign pop_shared = pop_valid & ~pop_almost_empty & 
				 (~push_valid | (push_empty & ~same_queue));
	   else
	     assign pop_shared = pop_valid & ~pop_almost_empty & 
				 (~push_valid | push_empty);
	   
	end
      else
	begin
	   assign push_shared = push_valid & ~pop_valid;
	   assign pop_shared = pop_valid & ~push_valid;
	end
      
   endgenerate
   
   wire 		     shared_almost_full;
   wire 		     shared_full;
   wire 		     shared_two_free;
   wire [0:1] 		     shared_errors;
   c_fifo_tracker
     #(.depth(num_shared_slots),
       .fast_two_free(fast_two_free),
       .enable_bypass(0),
       .reset_type(reset_type))
   sft
     (.clk(clk),
      .reset(reset),
      .active(active),
      .push(push_shared),
      .pop(pop_shared),
      .almost_empty(),
      .empty(),
      .almost_full(shared_almost_full),
      .full(shared_full),
      .two_free(shared_two_free),
      .errors(shared_errors));
   
   genvar 		     queue;
   
   generate
      
      for(queue = 0; queue < num_queues; queue = queue + 1)
	begin:queues
	   
	   wire push_sel;
	   assign push_sel = push_sel_qu[queue];
	   
	   wire push;
	   assign push = push_valid & push_sel;
	   
	   wire pop_sel;
	   assign pop_sel = pop_sel_qu[queue];
	   
	   wire pop;
	   assign pop = pop_valid & pop_sel;
	   
	   wire almost_empty;
	   wire empty;
	   wire [0:1] private_errors;
	   c_fifo_tracker
	     #(.depth(num_queue_slots),
	       .fast_almost_empty(fast_almost_empty),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   ft
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .push(push),
	      .pop(pop),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .almost_full(),
	      .full(),
	      .two_free(),
	      .errors(private_errors));
	   
	   wire [0:1] errors;
	   assign errors[0] = private_errors[0] | (pop & shared_errors[0]);
	   assign errors[1] = private_errors[1] | (push & shared_errors[1]);
	   
	   wire       almost_full;
	   wire       full;
	   wire       two_free;
	   
	   if(enable_reservations)
	     begin
		assign almost_full = empty ? shared_full : shared_almost_full;
		assign full = ~empty & shared_full;
	   	assign two_free = empty ? shared_almost_full : shared_two_free;
	     end
	   else
	     begin
		assign almost_full = shared_almost_full;
		assign full = shared_full;
	   	assign two_free = shared_two_free;
	     end
	   
	   assign almost_empty_qu[queue] = almost_empty;
	   assign empty_qu[queue] = empty;
	   assign almost_full_qu[queue] = almost_full;
	   assign full_qu[queue] = full;
	   assign two_free_qu[queue] = two_free;
	   assign errors_qu[queue*2:queue*2+1] = errors;
	   
	end
      
   endgenerate
   
endmodule
module c_damq_tracker
  (clk, reset, active, push_valid, push_sel_qu, pop_valid, pop_sel_qu, 
   almost_empty_qu, empty_qu, almost_full_qu, full_qu, two_free_qu, errors_qu);


`include "c_functions.v"
`include "c_constants.v"







   parameter num_queues = 4;
   

   parameter num_slots = 32;
   

   parameter fast_almost_empty = 0;
   

   parameter fast_two_free = 0;
   

   parameter enable_bypass = 0;
   

   parameter enable_reservations = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam num_shared_slots
     = enable_reservations ? (num_slots - num_queues) : num_slots;
   

   localparam num_queue_slots
     = enable_reservations ? (1 + num_shared_slots) : num_slots;
   
   



   
   input clk;
   input reset;
   

   input active;
   

   input push_valid;
   

   input [0:num_queues-1] push_sel_qu;
   

   input 		  pop_valid;
   

   input [0:num_queues-1] pop_sel_qu;
   

   output [0:num_queues-1] almost_empty_qu;
   wire [0:num_queues-1]   almost_empty_qu;
   output [0:num_queues-1] empty_qu;
   wire [0:num_queues-1]   empty_qu;
   output [0:num_queues-1] almost_full_qu;
   wire [0:num_queues-1]   almost_full_qu;
   output [0:num_queues-1] full_qu;
   wire [0:num_queues-1]   full_qu;
   output [0:num_queues-1] two_free_qu;
   wire [0:num_queues-1]   two_free_qu;
   

   output [0:num_queues*2-1] errors_qu;
   wire [0:num_queues*2-1]   errors_qu;
   
   




   wire 		     push_shared;
   wire 		     pop_shared;
   
   generate
      
      if(enable_reservations)
	begin
	   
	   wire push_empty;
	   c_select_1ofn
	     #(.num_ports(num_queues),
	       .width(1))
	   push_empty_sel
	     (.select(push_sel_qu),
	      .data_in(empty_qu),
	      .data_out(push_empty));
	   
	   wire pop_almost_empty;
	   c_select_1ofn
	     #(.num_ports(num_queues),
	       .width(1))
	   pop_almost_empty_sel
	     (.select(pop_sel_qu),
	      .data_in(almost_empty_qu),
	      .data_out(pop_almost_empty));
	   
	   wire same_queue;
	   assign same_queue = |(push_sel_qu & pop_sel_qu);
	   
	   assign push_shared = push_valid & ~push_empty & 
				(~pop_valid | (pop_almost_empty & ~same_queue));
	   
	   if(enable_bypass)
	     assign pop_shared = pop_valid & ~pop_almost_empty & 
				 (~push_valid | (push_empty & ~same_queue));
	   else
	     assign pop_shared = pop_valid & ~pop_almost_empty & 
				 (~push_valid | push_empty);
	   
	end
      else
	begin
	   assign push_shared = push_valid & ~pop_valid;
	   assign pop_shared = pop_valid & ~push_valid;
	end
      
   endgenerate
   
   wire 		     shared_almost_full;
   wire 		     shared_full;
   wire 		     shared_two_free;
   wire [0:1] 		     shared_errors;
   c_fifo_tracker
     #(.depth(num_shared_slots),
       .fast_two_free(fast_two_free),
       .enable_bypass(0),
       .reset_type(reset_type))
   sft
     (.clk(clk),
      .reset(reset),
      .active(active),
      .push(push_shared),
      .pop(pop_shared),
      .almost_empty(),
      .empty(),
      .almost_full(shared_almost_full),
      .full(shared_full),
      .two_free(shared_two_free),
      .errors(shared_errors));
   
   genvar 		     queue;
   
   generate
      
      for(queue = 0; queue < num_queues; queue = queue + 1)
	begin:queues
	   
	   wire push_sel;
	   assign push_sel = push_sel_qu[queue];
	   
	   wire push;
	   assign push = push_valid & push_sel;
	   
	   wire pop_sel;
	   assign pop_sel = pop_sel_qu[queue];
	   
	   wire pop;
	   assign pop = pop_valid & pop_sel;
	   
	   wire almost_empty;
	   wire empty;
	   wire [0:1] private_errors;
	   c_fifo_tracker
	     #(.depth(num_queue_slots),
	       .fast_almost_empty(fast_almost_empty),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   ft
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .push(push),
	      .pop(pop),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .almost_full(),
	      .full(),
	      .two_free(),
	      .errors(private_errors));
	   
	   wire [0:1] errors;
	   assign errors[0] = private_errors[0] | (pop & shared_errors[0]);
	   assign errors[1] = private_errors[1] | (push & shared_errors[1]);
	   
	   wire       almost_full;
	   wire       full;
	   wire       two_free;
	   
	   if(enable_reservations)
	     begin
		assign almost_full = empty ? shared_full : shared_almost_full;
		assign full = ~empty & shared_full;
	   	assign two_free = empty ? shared_almost_full : shared_two_free;
	     end
	   else
	     begin
		assign almost_full = shared_almost_full;
		assign full = shared_full;
	   	assign two_free = shared_two_free;
	     end
	   
	   assign almost_empty_qu[queue] = almost_empty;
	   assign empty_qu[queue] = empty;
	   assign almost_full_qu[queue] = almost_full;
	   assign full_qu[queue] = full;
	   assign two_free_qu[queue] = two_free;
	   assign errors_qu[queue*2:queue*2+1] = errors;
	   
	end
      
   endgenerate
   
endmodule