data/full_repos/permissive/450915285/vga_sync.v
1: b'%Warning-WIDTH: data/full_repos/permissive/450915285/vga_sync.v:27: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                  : ... In instance vga_sync\n        h_count <= h_count + 2\'b01;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/450915285/vga_sync.v:36: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                  : ... In instance vga_sync\n            v_count <= v_count + 2\'b01;\n                               ^\n%Error: Exiting due to 2 warning(s)\n'
module vga_sync(vga_clk,h_count,v_count,video_on,h_sync,v_sync);
  input vga_clk;
  output [9:0] h_count;
  output [9:0] v_count;
  output video_on;
  output h_sync;
  output v_sync;
  reg [9:0] h_count;
  reg [9:0] v_count;
  reg video_on,h_sync,v_sync;
  
  parameter HD = 640; 
  parameter HF = HD+16;
  parameter HR = HF+96;
  parameter HB = HR+48;

  parameter VD = 480; 
  parameter VF = VD+10;
  parameter VR = VF+2;
  parameter VB = VR+33;
  
  always@(posedge vga_clk)
    begin
      if(h_count == HB)
        h_count <= 0;
      else
        h_count <= h_count + 2'b01;
    end
  always@(posedge vga_clk)
    begin
      if(h_count == HB)
        begin
          if(v_count == VB)
            v_count <= 0;
          else
            v_count <= v_count + 2'b01;
        end
    end
  always@(posedge vga_clk)
    begin
      video_on <= ((h_count < HD) && (v_count < VD));
    end
  always@(posedge vga_clk)
    begin
      v_sync = ~((v_count >= VF) && (v_count < VR)); 
      h_sync = ~((h_count >= HF) && (h_count < HR));
    end 
endmodule
module vga_sync(vga_clk,h_count,v_count,video_on,h_sync,v_sync);

  input vga_clk;
  output [9:0] h_count;
  output [9:0] v_count;
  output video_on;
  output h_sync;
  output v_sync;
  reg [9:0] h_count;
  reg [9:0] v_count;
  reg video_on,h_sync,v_sync;
  
  parameter HD = 640; 
  parameter HF = HD+16;
  parameter HR = HF+96;
  parameter HB = HR+48;

  parameter VD = 480; 
  parameter VF = VD+10;
  parameter VR = VF+2;
  parameter VB = VR+33;
  
  always@(posedge vga_clk)
    begin
      if(h_count == HB)
        h_count <= 0;
      else
        h_count <= h_count + 2'b01;
    end
  always@(posedge vga_clk)
    begin
      if(h_count == HB)
        begin
          if(v_count == VB)
            v_count <= 0;
          else
            v_count <= v_count + 2'b01;
        end
    end
  always@(posedge vga_clk)
    begin
      video_on <= ((h_count < HD) && (v_count < VD));
    end
  always@(posedge vga_clk)
    begin
      v_sync = ~((v_count >= VF) && (v_count < VR)); 
      h_sync = ~((h_count >= HF) && (h_count < HR));
    end 
endmodule