data/full_repos/permissive/470590146/core/memory_md.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470590146/core/memory_md.v:38: Bit extraction of array[127:0] requires 7 bit index, not 16 bits.\n                                                                        : ... In instance memory_md\n  rdata <= memo[addr];\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470590146/core/memory_md.v:41: Bit extraction of array[127:0] requires 7 bit index, not 16 bits.\n                                                                        : ... In instance memory_md\n  memo[addr] <= wdata;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module memory_md #(


	parameter DEPTH = 128,
	parameter WIDTH = 32,
	parameter WIDTH_BITS = 16
)(
	 input  	clk

	,input   	ren
	,input   	wen
	,input   	[WIDTH_BITS-1:0] addr
	,input   	[     WIDTH-1:0] wdata

	,output reg [     WIDTH-1:0] rdata
);



reg [WIDTH-1:0] memo [0:DEPTH-1];

always @(posedge clk) begin
	if (ren == 1'b1) begin
		rdata <= memo[addr];
	end
	if (wen == 1'b1) begin
		memo[addr] <= wdata;
	end
end

endmodule
module memory_md #(


	parameter DEPTH = 128,
	parameter WIDTH = 32,
	parameter WIDTH_BITS = 16
)(
	 input  	clk

	,input   	ren
	,input   	wen
	,input   	[WIDTH_BITS-1:0] addr
	,input   	[     WIDTH-1:0] wdata

	,output reg [     WIDTH-1:0] rdata
);




reg [WIDTH-1:0] memo [0:DEPTH-1];

always @(posedge clk) begin
	if (ren == 1'b1) begin
		rdata <= memo[addr];
	end
	if (wen == 1'b1) begin
		memo[addr] <= wdata;
	end
end

endmodule