data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #51 speed_ctrl = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #102 temp = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #250;\n  ^\n%Error: data/full_repos/permissive/502536946/PWM_Generator_Verilog_tb.v:14: Cannot find file containing module: \'PWM_Generator_Verilog\'\n PWM_Generator_Verilog PP(.clk(clk), .speed_ctrl(speed_ctrl), .led_out(led_out));\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502536946,data/full_repos/permissive/502536946/PWM_Generator_Verilog\n             data/full_repos/permissive/502536946,data/full_repos/permissive/502536946/PWM_Generator_Verilog.v\n             data/full_repos/permissive/502536946,data/full_repos/permissive/502536946/PWM_Generator_Verilog.sv\n             PWM_Generator_Verilog\n             PWM_Generator_Verilog.v\n             PWM_Generator_Verilog.sv\n             obj_dir/PWM_Generator_Verilog\n             obj_dir/PWM_Generator_Verilog.v\n             obj_dir/PWM_Generator_Verilog.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PWM_Generator_Verilog_tb();
	reg			clk, speed_ctrl;
	reg [8:0]	temp;
	wire			led_out;
	
	always #50	clk = ~clk;
	
	initial begin
		#51	speed_ctrl = 0;	
		#102	temp = 0;
		#250;
	end
	
	PWM_Generator_Verilog PP(.clk(clk), .speed_ctrl(speed_ctrl), .led_out(led_out));
	
	always@ (posedge clk) begin
		temp <= #1 temp + 1;
		if (temp[8]) begin
			speed_ctrl = 1;
		end
	end
	
endmodule
module PWM_Generator_Verilog_tb();

	reg			clk, speed_ctrl;
	reg [8:0]	temp;
	wire			led_out;
	
	always #50	clk = ~clk;
	
	initial begin
		#51	speed_ctrl = 0;	
		#102	temp = 0;
		#250;
	end
	
	PWM_Generator_Verilog PP(.clk(clk), .speed_ctrl(speed_ctrl), .led_out(led_out));
	
	always@ (posedge clk) begin
		temp <= #1 temp + 1;
		if (temp[8]) begin
			speed_ctrl = 1;
		end
	end
	
endmodule