data/full_repos/permissive/461000256/hdl/ALU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/461000256/hdl/ALU.v:30: Signal definition not found, creating implicitly: \'I\'\n assign I = funct3[2:0];\n        ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:30: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                 : ... In instance ALU\n assign I = funct3[2:0];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:61: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 12 bits.\n                                                                 : ... In instance ALU\n    out = in_r1 + imm;      \n                ^\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:67: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 12 bits.\n                                                                 : ... In instance ALU\n    out = in_r1 ^ imm;      \n                ^\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:71: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 12 bits.\n                                                                 : ... In instance ALU\n    out = in_r1 | imm;      \n                ^\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:73: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 12 bits.\n                                                                 : ... In instance ALU\n    out = in_r1 & imm;      \n                ^\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:72: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h7)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:70: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h6)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:68: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h5 & funct7 == 7\'h00)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:66: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h4)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:64: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h2)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:62: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   else if  (I == 3\'h1 & funct7 == 7\'h00)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/ALU.v:60: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'I\' generates 1 bits.\n                                                                 : ... In instance ALU\n   if   (I == 3\'h0)\n           ^~\n%Error: Exiting due to 13 warning(s)\n'
module ALU (
	input  wire [`DW-1:0] in_r1,	
	input  wire [`DW-1:0] in_r2,
	input  wire [`IW-1:0] in_inst,	
	output reg  [`DW-1:0] out
);



	
	wire [6:0] 	funct7, opcode;
	wire [2:0] 	funct3;
	wire [9:0] 	R;
	wire [11:0] imm;
	wire [`DW-1:0] out_xor;
	
	assign funct7 	= in_inst[31:25];
	assign funct3	= in_inst[14:12];
	assign opcode	= in_inst[6 :0 ];
	assign imm		= in_inst[31:20];
	
	assign R = {funct3,funct7};
	assign I = funct3[2:0];
	

	

	always @(*) begin
		if (opcode == 7'h33) begin


			if 		(R == 10'h000)
				out = in_r1 + in_r2;
			else if 	(R == 10'h020)
				out = in_r1 - in_r2;
			else if 	(R == 10'h100)
				out = in_r1 << in_r2;
			else if 	(R == 10'h200)
				out = (in_r1 < in_r2) ? 1:0;
			else if 	(R == 10'h400)
				out = in_r1 + in_r2;
			else if 	(R == 10'h500)
				out = in_r1 >> in_r2;
			else if 	(R == 10'h600)
				out = in_r1 | in_r2;
			else if 	(R == 10'h700)
				out = in_r1 & in_r2;
			else
				out = 32'hxxxxxxxx;
		end else if (opcode == 7'h13) begin


			if			(I == 3'h0)
				out = in_r1 + imm;
			else if 	(I == 3'h1 & funct7 == 7'h00)
				out = in_r1 << imm;
			else if 	(I == 3'h2)
				out = (in_r1 < imm) ? 1:0;
			else if 	(I == 3'h4)
				out = in_r1 ^ imm;
			else if 	(I == 3'h5 & funct7 == 7'h00)
				out = in_r1 >> imm;
			else if 	(I == 3'h6)
				out = in_r1 | imm;
			else if 	(I == 3'h7)
				out = in_r1 & imm;
			else
				out = 32'hxxxxxxxx;
		end else
				out = 32'hxxxxxxxx;
	end

endmodule
module ALU (
	input  wire [`DW-1:0] in_r1,	
	input  wire [`DW-1:0] in_r2,
	input  wire [`IW-1:0] in_inst,	
	output reg  [`DW-1:0] out
);




	
	wire [6:0] 	funct7, opcode;
	wire [2:0] 	funct3;
	wire [9:0] 	R;
	wire [11:0] imm;
	wire [`DW-1:0] out_xor;
	
	assign funct7 	= in_inst[31:25];
	assign funct3	= in_inst[14:12];
	assign opcode	= in_inst[6 :0 ];
	assign imm		= in_inst[31:20];
	
	assign R = {funct3,funct7};
	assign I = funct3[2:0];
	

	

	always @(*) begin
		if (opcode == 7'h33) begin


			if 		(R == 10'h000)
				out = in_r1 + in_r2;
			else if 	(R == 10'h020)
				out = in_r1 - in_r2;
			else if 	(R == 10'h100)
				out = in_r1 << in_r2;
			else if 	(R == 10'h200)
				out = (in_r1 < in_r2) ? 1:0;
			else if 	(R == 10'h400)
				out = in_r1 + in_r2;
			else if 	(R == 10'h500)
				out = in_r1 >> in_r2;
			else if 	(R == 10'h600)
				out = in_r1 | in_r2;
			else if 	(R == 10'h700)
				out = in_r1 & in_r2;
			else
				out = 32'hxxxxxxxx;
		end else if (opcode == 7'h13) begin


			if			(I == 3'h0)
				out = in_r1 + imm;
			else if 	(I == 3'h1 & funct7 == 7'h00)
				out = in_r1 << imm;
			else if 	(I == 3'h2)
				out = (in_r1 < imm) ? 1:0;
			else if 	(I == 3'h4)
				out = in_r1 ^ imm;
			else if 	(I == 3'h5 & funct7 == 7'h00)
				out = in_r1 >> imm;
			else if 	(I == 3'h6)
				out = in_r1 | imm;
			else if 	(I == 3'h7)
				out = in_r1 & imm;
			else
				out = 32'hxxxxxxxx;
		end else
				out = 32'hxxxxxxxx;
	end

endmodule