data/full_repos/permissive/499137621/CheckPoint3_regfile-main/AND_4.v
data/verilator_xmls/1dc58066-84d2-4228-b9fe-9dfc401a2556.xml
module AND_4(out, A, B, C, D);
	
	input A, B, C, D;
	output out;
	wire and1_out, and2_out;
	
	and and1(and1_out, A, B);
	and and2(and2_out, C, D);	
	and and3(out, and1_out, and2_out);		

endmodule
module AND_4(out, A, B, C, D);

	
	input A, B, C, D;
	output out;
	wire and1_out, and2_out;
	
	and and1(and1_out, A, B);
	and and2(and2_out, C, D);	
	and and3(out, and1_out, and2_out);		

endmodule