data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/Section2.v
1: b"%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/Section2.v:32: Cannot find file containing module: 'Min'\nMin min1 (.clk (clk), .sample (sample), .min (min), .Reset(Reset));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new,data/full_repos/permissive/492007370/Min\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new,data/full_repos/permissive/492007370/Min.v\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new,data/full_repos/permissive/492007370/Min.sv\n             Min\n             Min.v\n             Min.sv\n             obj_dir/Min\n             obj_dir/Min.v\n             obj_dir/Min.sv\n%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/Section2.v:33: Cannot find file containing module: 'Max'\nMax max1 (.clk (clk), .sample (sample), .max (max), .Reset(Reset));\n^~~\n%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/Section2.v:34: Cannot find file containing module: 'Mean'\nMean minMean (.Reset(Reset), .InData(min), .average(minAvg));\n^~~~\n%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/Section2.v:35: Cannot find file containing module: 'Mean'\nMean maxMean (.Reset(Reset), .InData(max), .average(maxAvg));\n^~~~\n%Error: Exiting due to 4 error(s)\n"
module Section2(clk, interval, sample, min, max);

input clk;
input [15:0] interval;
inout [15:0] min, max;      
inout [15:0] sample;
reg Reset;
wire [15:0] minAvg, maxAvg;

Min min1 (.clk (clk), .sample (sample), .min (min), .Reset(Reset));
Max max1 (.clk (clk), .sample (sample), .max (max), .Reset(Reset));
Mean minMean (.Reset(Reset), .InData(min), .average(minAvg));
Mean maxMean (.Reset(Reset), .InData(max), .average(maxAvg));

parameter frequency = 48000;
integer count, intcounter;
reg [15:0] arrMin[50:0];
reg [15:0] arrMax[50:0];


initial begin
    count <= 0;
    intcounter <= 1;
    Reset <= 0;
end

always@(posedge clk) begin



   if (count == interval*frequency)
   begin
      arrMin[intcounter] = min;
      arrMax[intcounter] = max;
      Reset = 1;
      intcounter = intcounter + 1;
      count = 0;
   end else
   Reset = 0;
   count = count + 1;
end

endmodule
module Section2(clk, interval, sample, min, max);


input clk;
input [15:0] interval;
inout [15:0] min, max;      
inout [15:0] sample;
reg Reset;
wire [15:0] minAvg, maxAvg;

Min min1 (.clk (clk), .sample (sample), .min (min), .Reset(Reset));
Max max1 (.clk (clk), .sample (sample), .max (max), .Reset(Reset));
Mean minMean (.Reset(Reset), .InData(min), .average(minAvg));
Mean maxMean (.Reset(Reset), .InData(max), .average(maxAvg));

parameter frequency = 48000;
integer count, intcounter;
reg [15:0] arrMin[50:0];
reg [15:0] arrMax[50:0];


initial begin
    count <= 0;
    intcounter <= 1;
    Reset <= 0;
end

always@(posedge clk) begin



   if (count == interval*frequency)
   begin
      arrMin[intcounter] = min;
      arrMax[intcounter] = max;
      Reset = 1;
      intcounter = intcounter + 1;
      count = 0;
   end else
   Reset = 0;
   count = count + 1;
end

endmodule