data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sources_1/new/ram.v
data/verilator_xmls/4de1950c-5564-49b6-8199-3e0f65182732.xml
module RAM(
    output reg [7:0] dout,
    input [7:0] din,
    input [7:0] addr,
    input oe,
    input we,
    input rst,
    input clk
);

reg [7:0] mem [255:0];

always @(posedge clk)
    begin
        if(rst)
        begin
            mem[0] <= 0;
        end
        if(we)
        begin
            mem[addr] <= din;
        end
        if(oe)
        begin
            dout <= mem[addr];
        end
    end
endmodule
module RAM(
    output reg [7:0] dout,
    input [7:0] din,
    input [7:0] addr,
    input oe,
    input we,
    input rst,
    input clk
);


reg [7:0] mem [255:0];

always @(posedge clk)
    begin
        if(rst)
        begin
            mem[0] <= 0;
        end
        if(we)
        begin
            mem[addr] <= din;
        end
        if(oe)
        begin
            dout <= mem[addr];
        end
    end
endmodule