data/full_repos/permissive/4695331/hdl_harness/clock_transmitter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/4695331/hdl_harness/clock_transmitter.v:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                     : ... In instance clock_transmitter\nreg [31:0] transmit_buf = 8\'d0;\n                          ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/4695331/hdl_harness/clock_transmitter.v:72: Cannot find file containing module: \'rising_edge_detect\'\nrising_edge_detect tx_detect\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/4695331/hdl_harness,data/full_repos/permissive/4695331/rising_edge_detect\n             data/full_repos/permissive/4695331/hdl_harness,data/full_repos/permissive/4695331/rising_edge_detect.v\n             data/full_repos/permissive/4695331/hdl_harness,data/full_repos/permissive/4695331/rising_edge_detect.sv\n             rising_edge_detect\n             rising_edge_detect.v\n             rising_edge_detect.sv\n             obj_dir/rising_edge_detect\n             obj_dir/rising_edge_detect.v\n             obj_dir/rising_edge_detect.sv\n%Error: data/full_repos/permissive/4695331/hdl_harness/clock_transmitter.v:130: Cannot find file containing module: \'async_transmitter\'\nasync_transmitter tx\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module clock_transmitter
          (
           clk_fast,
			  clk_slow,
			  counter,
			  header,
           go,
			  TxD,
			  done
          );
			 
input clk_fast;
input clk_slow;
input [31:0] counter;
input [7:0] header;
input go;
output TxD;
output done;

parameter s_idle = 0;
parameter s_transmit_tx = 1;
parameter s_transmit_wait = 2;
parameter s_inc_byte = 3;
parameter s_finish = 4;

reg[3:0] state = 4'd0;
reg[7:0] data = 8'd0;
reg[3:0] byte_count = 4'd0;

reg go_reg = 1'b0;
reg go_reg_prev = 1'b0;
reg [7:0] header_reg = 8'd0;
reg [31:0] transmit_buf = 8'd0;
wire tx_start_pulse;
reg tx_start = 1'b0;
wire tx_busy;
wire tx_out;



rising_edge_detect tx_detect
(
 .clk(clk_fast),
 .signal(tx_start),
 .pulse(tx_start_pulse)
);






always @(posedge clk_slow) begin
	case(state)
		s_idle:
		begin
			go_reg <= go & !go_reg_prev;

			if (header_reg == 8'd0) header_reg <= header;
			state <= (go_reg) ? s_transmit_tx : s_idle;
			transmit_buf <= (go_reg) ? counter : 32'd0;
			byte_count <= 4'd0;
			go_reg_prev <= go_reg;
		end
			
		s_transmit_tx: 
		begin
			tx_start <= (byte_count < 4'd5); 
			data <= (byte_count == 4'd0) ? header_reg :
					  (byte_count == 4'd1) ? transmit_buf[7:0] :
					  (byte_count == 4'd2) ? transmit_buf[15:8] :
					  (byte_count == 4'd3) ? transmit_buf[23:16] :
					  (byte_count == 4'd4) ? transmit_buf[31:24] :
					  8'b0;
			state <= (byte_count < 4'd5) ? s_transmit_wait : s_finish;
		end
		
		s_transmit_wait: 
		begin
			state <= (tx_busy) ? s_transmit_wait : s_inc_byte;
			tx_start <= 0;
		end
					
		s_inc_byte:
		begin
			byte_count <= byte_count + 4'b1;
			state <= s_transmit_tx;
		end
		
		s_finish:
		begin
			state <= s_idle;
			header_reg <= 8'b0;
		end
	endcase
end


async_transmitter tx
	(
	.clk(clk_fast), 
	.TxD_start(tx_start_pulse), 
	.TxD_data(data), 
	.TxD(tx_out), 
	.TxD_busy(tx_busy)
	);
		

assign done = (state == s_finish);
reg TxD;
always @(posedge clk_fast)
		TxD <= (tx_busy) ? tx_out : 1'b1;
			 
endmodule
module clock_transmitter
          (
           clk_fast,
			  clk_slow,
			  counter,
			  header,
           go,
			  TxD,
			  done
          );

			 
input clk_fast;
input clk_slow;
input [31:0] counter;
input [7:0] header;
input go;
output TxD;
output done;

parameter s_idle = 0;
parameter s_transmit_tx = 1;
parameter s_transmit_wait = 2;
parameter s_inc_byte = 3;
parameter s_finish = 4;

reg[3:0] state = 4'd0;
reg[7:0] data = 8'd0;
reg[3:0] byte_count = 4'd0;

reg go_reg = 1'b0;
reg go_reg_prev = 1'b0;
reg [7:0] header_reg = 8'd0;
reg [31:0] transmit_buf = 8'd0;
wire tx_start_pulse;
reg tx_start = 1'b0;
wire tx_busy;
wire tx_out;



rising_edge_detect tx_detect
(
 .clk(clk_fast),
 .signal(tx_start),
 .pulse(tx_start_pulse)
);






always @(posedge clk_slow) begin
	case(state)
		s_idle:
		begin
			go_reg <= go & !go_reg_prev;

			if (header_reg == 8'd0) header_reg <= header;
			state <= (go_reg) ? s_transmit_tx : s_idle;
			transmit_buf <= (go_reg) ? counter : 32'd0;
			byte_count <= 4'd0;
			go_reg_prev <= go_reg;
		end
			
		s_transmit_tx: 
		begin
			tx_start <= (byte_count < 4'd5); 
			data <= (byte_count == 4'd0) ? header_reg :
					  (byte_count == 4'd1) ? transmit_buf[7:0] :
					  (byte_count == 4'd2) ? transmit_buf[15:8] :
					  (byte_count == 4'd3) ? transmit_buf[23:16] :
					  (byte_count == 4'd4) ? transmit_buf[31:24] :
					  8'b0;
			state <= (byte_count < 4'd5) ? s_transmit_wait : s_finish;
		end
		
		s_transmit_wait: 
		begin
			state <= (tx_busy) ? s_transmit_wait : s_inc_byte;
			tx_start <= 0;
		end
					
		s_inc_byte:
		begin
			byte_count <= byte_count + 4'b1;
			state <= s_transmit_tx;
		end
		
		s_finish:
		begin
			state <= s_idle;
			header_reg <= 8'b0;
		end
	endcase
end


async_transmitter tx
	(
	.clk(clk_fast), 
	.TxD_start(tx_start_pulse), 
	.TxD_data(data), 
	.TxD(tx_out), 
	.TxD_busy(tx_busy)
	);
		

assign done = (state == s_finish);
reg TxD;
always @(posedge clk_fast)
		TxD <= (tx_busy) ? tx_out : 1'b1;
			 
endmodule