data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = 0;\n            ^\n%Error: data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync_tb.v:37: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " out: %d, num: %h, rst %b, clk %b, en %b", out, num, rst, clk, en);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    integer i;
    parameter length = 4;
    reg [4:0] num;
    reg clk, en, rst;
    wire out;

    div_3 div(.num(num), .clk(clk), .en(en), .rst(rst), .divisable(out));

    initial begin
        num = 4'b0;
        rst = 0;
        clk = 0;
        #1 rst = 1;
        #1 rst = 0;
        en = 1;

        for (i = 0; i < 9; i = i + 1)
        begin
            num = i;
            #1 clk = 1;
            #1 clk = 0;
        end

        en = 0;
        for (i = 0; i < 9; i = i + 1)
        begin
            num = i;
            #1 clk = 1;
            #1 clk = 0;
        end
    end

    initial $monitor ($time, " out: %d, num: %h, rst %b, clk %b, en %b", out, num, rst, clk, en);
endmodule
module testbench;

    integer i;
    parameter length = 4;
    reg [4:0] num;
    reg clk, en, rst;
    wire out;

    div_3 div(.num(num), .clk(clk), .en(en), .rst(rst), .divisable(out));

    initial begin
        num = 4'b0;
        rst = 0;
        clk = 0;
        #1 rst = 1;
        #1 rst = 0;
        en = 1;

        for (i = 0; i < 9; i = i + 1)
        begin
            num = i;
            #1 clk = 1;
            #1 clk = 0;
        end

        en = 0;
        for (i = 0; i < 9; i = i + 1)
        begin
            num = i;
            #1 clk = 1;
            #1 clk = 0;
        end
    end

    initial $monitor ($time, " out: %d, num: %h, rst %b, clk %b, en %b", out, num, rst, clk, en);
endmodule