data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module fulladder(a,b,c,s0,s1);
	input a,b,c;
	output s0,s1;
	reg s0,s1;
	wire so1,so2,so3,so4;
	halfsum SOMA1(a,b,so1,so2);	
	halfsum SOMA2(c,so1,s0,so3);
	halfsum SOMA3(so2,so1,so4,s1);
endmodule
module fulladder(a,b,c,s0,s1);

	input a,b,c;
	output s0,s1;
	reg s0,s1;
	wire so1,so2,so3,so4;
	halfsum SOMA1(a,b,so1,so2);	
	halfsum SOMA2(c,so1,s0,so3);
	halfsum SOMA3(so2,so1,so4,s1);
endmodule