data/full_repos/permissive/48330045/rtl/ram_sp.v
data/verilator_xmls/c11e47fa-5b13-4868-864d-a2fa43b7acf3.xml
module ram_sp
#(
  parameter DWIDTH  = 8,
  parameter AWIDTH  = 12,
  parameter CONTENT = "./memory.txt"
) (
  input  wire              clock,
  input  wire              wren,
  input  wire [AWIDTH-1:0] address,
  input  wire [DWIDTH-1:0] data,
  output reg  [DWIDTH-1:0] q
);

reg [DWIDTH-1:0] core [0:2**AWIDTH-1];

initial begin
  $readmemh(CONTENT, core);
end


always @(posedge clock) begin
  if(wren)
    core[address] <= data;
end


always @(posedge clock) begin
  q <= core[address];
end

endmodule
module ram_sp
#(
  parameter DWIDTH  = 8,
  parameter AWIDTH  = 12,
  parameter CONTENT = "./memory.txt"
) (
  input  wire              clock,
  input  wire              wren,
  input  wire [AWIDTH-1:0] address,
  input  wire [DWIDTH-1:0] data,
  output reg  [DWIDTH-1:0] q
);


reg [DWIDTH-1:0] core [0:2**AWIDTH-1];

initial begin
  $readmemh(CONTENT, core);
end


always @(posedge clock) begin
  if(wren)
    core[address] <= data;
end


always @(posedge clock) begin
  q <= core[address];
end

endmodule