data/full_repos/permissive/424312442/lab_6_digital clock/sources_1/new/clock.v
1: b'%Error: Cannot find file containing module: clock/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             clock/sources_1/new,data/full_repos/permissive/424312442\n             clock/sources_1/new,data/full_repos/permissive/424312442.v\n             clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_6_digital\n%Error: Cannot find file containing module: clock/sources_1/new/clock.v\n%Error: Exiting due to 3 error(s)\n'
module bcd_seg_complete(CLK, AN, SEGN);
input CLK;
output [3:0] AN;
output [7:0] SEGN;


wire [3:0] BCD0;
wire [3:0] BCD1;
wire [3:0] BCD2;
wire [3:0] BCD3;
clock_mod (CLK, BCD0, BCD1, BCD2, BCD3);

wire [7:0] SEGN;
reg [3:0] BCD;
reg segn = 1;
wire w1;
assign SEGN[7] = segn;

clock_divider (CLK, w1);

dig_cont (CLK, AN);
bcd_to_sevseg (BCD, SEGN[6:0]);


always @(posedge CLK) begin
    if (AN == 4'b1110) begin
        BCD <= BCD0;
    end else if (AN == 4'b1101) begin
        BCD <= BCD1;
    end else if (AN == 4'b1011) begin
        BCD <= BCD2;
    end else if (AN == 4'b0111) begin
        BCD <= BCD3;
    end else;
end


always @(posedge CLK) begin
    if (AN == 4'b1110) begin
      segn <= !w1;
    end else segn <= 1;
end
endmodule
module bcd_seg_complete(CLK, AN, SEGN);

input CLK;
output [3:0] AN;
output [7:0] SEGN;


wire [3:0] BCD0;
wire [3:0] BCD1;
wire [3:0] BCD2;
wire [3:0] BCD3;
clock_mod (CLK, BCD0, BCD1, BCD2, BCD3);

wire [7:0] SEGN;
reg [3:0] BCD;
reg segn = 1;
wire w1;
assign SEGN[7] = segn;

clock_divider (CLK, w1);

dig_cont (CLK, AN);
bcd_to_sevseg (BCD, SEGN[6:0]);


always @(posedge CLK) begin
    if (AN == 4'b1110) begin
        BCD <= BCD0;
    end else if (AN == 4'b1101) begin
        BCD <= BCD1;
    end else if (AN == 4'b1011) begin
        BCD <= BCD2;
    end else if (AN == 4'b0111) begin
        BCD <= BCD3;
    end else;
end


always @(posedge CLK) begin
    if (AN == 4'b1110) begin
      segn <= !w1;
    end else segn <= 1;
end
endmodule