data/full_repos/permissive/425063349/Transmitter.v
1: b'%Error: data/full_repos/permissive/425063349/Transmitter.v:9: Cannot find file containing module: \'Counter\'\n Counter CT(Done, i, N, up, Reset, Clock);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Counter\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Counter.v\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Warning-WIDTH: data/full_repos/permissive/425063349/Transmitter.v:18: Operator AND expects 64 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                     : ... In instance Transmitter\n   Byte <= M & 8\'hFF;  \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425063349/Transmitter.v:18: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                     : ... In instance Transmitter\n   Byte <= M & 8\'hFF;  \n        ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Transmitter (output reg [7:0] Byte, output Done, input [63:0] Hash, input Reset, Clock);
	reg [63:0] M;
	wire [3:0] N, i;
	assign N = 4'b111;
	
	wire up;
	assign up = ~Reset;
	
	Counter CT(Done, i, N, up, Reset, Clock);


	always @ (posedge Clock) begin
		if (Reset) begin
			Byte <= 8'h0;
			M <= Hash;
		end
		else if (~Done) begin
			Byte <= M & 8'hFF;
			M <= M >> 8;
		end
	end
endmodule
module Transmitter (output reg [7:0] Byte, output Done, input [63:0] Hash, input Reset, Clock);

	reg [63:0] M;
	wire [3:0] N, i;
	assign N = 4'b111;
	
	wire up;
	assign up = ~Reset;
	
	Counter CT(Done, i, N, up, Reset, Clock);


	always @ (posedge Clock) begin
		if (Reset) begin
			Byte <= 8'h0;
			M <= Hash;
		end
		else if (~Done) begin
			Byte <= M & 8'hFF;
			M <= M >> 8;
		end
	end
endmodule