data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v
1: b'%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background\n%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v\n%Error: Exiting due to 3 error(s)\n'
module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z);

    parameter integer rscid   = 1;
    parameter integer width   = 8;
    parameter         ph_clk  =  1'b1;
    parameter         ph_en   =  1'b1;
    parameter         ph_arst =  1'b1;
    parameter         ph_srst =  1'b1;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ld;
    input  [width-1:0] d;
    output             lz;
    output [width-1:0] z;


    generate
    if (ph_clk == 1'b0)
    begin: NEG_EDGE

        mgc_out_reg_neg
        #(
            .rscid   (rscid),
            .width   (width),
            .ph_en   (ph_en),
            .ph_arst (ph_arst),
            .ph_srst (ph_srst)
        )
        mgc_out_reg_neg_inst
        (
            .clk     (clk),
            .en      (en),
            .arst    (arst),
            .srst    (srst),
            .ld      (ld),
            .d       (d),
            .lz      (lz),
            .z       (z)
        );

    end
    else
    begin: POS_EDGE

        mgc_out_reg_pos
        #(
            .rscid   (rscid),
            .width   (width),
            .ph_en   (ph_en),
            .ph_arst (ph_arst),
            .ph_srst (ph_srst)
        )
        mgc_out_reg_pos_inst
        (
            .clk     (clk),
            .en      (en),
            .arst    (arst),
            .srst    (srst),
            .ld      (ld),
            .d       (d),
            .lz      (lz),
            .z       (z)
        );

    end
    endgenerate

endmodule
module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z);


    parameter integer rscid   = 1;
    parameter integer width   = 8;
    parameter         ph_clk  =  1'b1;
    parameter         ph_en   =  1'b1;
    parameter         ph_arst =  1'b1;
    parameter         ph_srst =  1'b1;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ld;
    input  [width-1:0] d;
    output             lz;
    output [width-1:0] z;


    generate
    if (ph_clk == 1'b0)
    begin: NEG_EDGE

        mgc_out_reg_neg
        #(
            .rscid   (rscid),
            .width   (width),
            .ph_en   (ph_en),
            .ph_arst (ph_arst),
            .ph_srst (ph_srst)
        )
        mgc_out_reg_neg_inst
        (
            .clk     (clk),
            .en      (en),
            .arst    (arst),
            .srst    (srst),
            .ld      (ld),
            .d       (d),
            .lz      (lz),
            .z       (z)
        );

    end
    else
    begin: POS_EDGE

        mgc_out_reg_pos
        #(
            .rscid   (rscid),
            .width   (width),
            .ph_en   (ph_en),
            .ph_arst (ph_arst),
            .ph_srst (ph_srst)
        )
        mgc_out_reg_pos_inst
        (
            .clk     (clk),
            .en      (en),
            .arst    (arst),
            .srst    (srst),
            .ld      (ld),
            .d       (d),
            .lz      (lz),
            .z       (z)
        );

    end
    endgenerate

endmodule