data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/cachelib/v_rtl/dut_DECODE_64U_5_1.v
data/verilator_xmls/17fed47e-9d5e-4e0b-ac73-8c2384ed417f.xml
module dut_DECODE_64U_5_1 (
	in1,
	out1
	);
input [5:0] in1;
output [63:0] out1;
wire [63:0] asc001;

assign asc001 = 64'B0000000000000000000000000000000000000000000000000000000000000001 << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_64U_5_1 (
	in1,
	out1
	);

input [5:0] in1;
output [63:0] out1;
wire [63:0] asc001;

assign asc001 = 64'B0000000000000000000000000000000000000000000000000000000000000001 << in1;

assign out1 = asc001;
endmodule