data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/BASIC/v_rtl/dut_Mul_29Ux8U_32U_1.v
data/verilator_xmls/7cad28de-2996-4c85-b174-0225f2a1b056.xml
module dut_Mul_29Ux8U_32U_1 (
	in2,
	in1,
	out1
	);
input [28:0] in2;
input [7:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule
module dut_Mul_29Ux8U_32U_1 (
	in2,
	in1,
	out1
	);

input [28:0] in2;
input [7:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule