data/full_repos/permissive/516759878/RTL/Seven_seg.v
data/verilator_xmls/3e00f7e9-91b7-4f97-9424-54d140022f1a.xml
module Seven_seg(
input [`DATA_WID-1:0] i_data , 
output [`SEVEN_SEG_WIDTH-1:0] seg_out
    );
    reg [`SEVEN_SEG_WIDTH-1:0] seg ;
always @(*)
   begin
         case (i_data)
      4'b0000: seg = 7'b1000_000 ;
      4'b0001: seg = 7'b1111_001;
      4'b0010: seg = 7'b0100_100;
      4'b0011: seg = 7'b0110_000;
      4'b0100: seg = 7'b0011_001;
      4'b0101: seg = 7'b0010_010;
      4'b0110: seg = 7'b0000_010;
      4'b0111: seg = 7'b1111_000;
      4'b1000: seg = 7'b0000_000;
      4'b1001: seg = 7'b0011_000;
      4'b1010: seg = 7'b0001_000;
      4'b1011: seg = 7'b0000_011;
      4'b1100: seg = 7'b1000_110;
      4'b1101: seg = 7'b0100_001;
      4'b1110: seg = 7'b0000_110;
      default : seg = 7'b001_110;
      endcase

   end   
        assign seg_out = seg ;
endmodule
module Seven_seg(
input [`DATA_WID-1:0] i_data , 
output [`SEVEN_SEG_WIDTH-1:0] seg_out
    );

    reg [`SEVEN_SEG_WIDTH-1:0] seg ;
always @(*)
   begin
         case (i_data)
      4'b0000: seg = 7'b1000_000 ;
      4'b0001: seg = 7'b1111_001;
      4'b0010: seg = 7'b0100_100;
      4'b0011: seg = 7'b0110_000;
      4'b0100: seg = 7'b0011_001;
      4'b0101: seg = 7'b0010_010;
      4'b0110: seg = 7'b0000_010;
      4'b0111: seg = 7'b1111_000;
      4'b1000: seg = 7'b0000_000;
      4'b1001: seg = 7'b0011_000;
      4'b1010: seg = 7'b0001_000;
      4'b1011: seg = 7'b0000_011;
      4'b1100: seg = 7'b1000_110;
      4'b1101: seg = 7'b0100_001;
      4'b1110: seg = 7'b0000_110;
      default : seg = 7'b001_110;
      endcase

   end   
        assign seg_out = seg ;
endmodule