data/full_repos/permissive/489075769/slave1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489075769/slave1.v:52: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                : ... In instance slave1\ni_RDATA<=data;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489075769/slave1.v:72: Cannot find file containing module: \'write_address_slave\'\nwrite_address_slave was(ACLK,ARESETn, AWVALID, i_AWREADY, o_AWREADY, i_AWADDR, o_AWADDR);\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/write_address_slave\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/write_address_slave.v\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/write_address_slave.sv\n             write_address_slave\n             write_address_slave.v\n             write_address_slave.sv\n             obj_dir/write_address_slave\n             obj_dir/write_address_slave.v\n             obj_dir/write_address_slave.sv\n%Error: data/full_repos/permissive/489075769/slave1.v:73: Cannot find file containing module: \'write_data_slave\'\nwrite_data_slave wds(ACLK, ARESETn,WVALID, o_WREADY, i_WREADY, i_WDATA, o_WDATA,i_WSTRB, o_WSTRB);\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/slave1.v:74: Cannot find file containing module: \'write_response_slave\'\nwrite_response_slave wrs(ACLK, ARESETn,i_BVALID, o_BVALID, BREADY, i_BRESP, o_BRESP);\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/slave1.v:76: Cannot find file containing module: \'read_address_slave\'\nread_address_slave ras(ACLK, ARESETn, i_ARREADY, o_ARREADY, ARVALID, i_ARADDR, o_ARADDR);\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/slave1.v:77: Cannot find file containing module: \'read_data_slave\'\nread_data_slave rds(ACLK, ARESETn, i_RVALID, o_RVALID, RREADY, i_RDATA, o_RDATA, i_RRESP, o_RRESP);\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module slave1(ACLK, ARESETn,ARVALID,RREADY,o_ARREADY,i_ARADDR,o_RVALID,o_RDATA,o_RRESP,read,
write,AWVALID,WVALID,BREADY,i_AWADDR,i_WDATA,i_WSTRB,i_BRESP,o_AWREADY,o_WREADY,o_BVALID,o_BRESP);
input ACLK;
input ARESETn;

input ARVALID;
input RREADY;
input read;
output  o_ARREADY; 
output  o_RVALID;
input[31:0] i_ARADDR;
output [31:0] o_RDATA;
output [1:0] o_RRESP;
reg i_ARREADY;
reg i_RVALID;
wire [32:0] o_ARADDR;
reg [32:0] i_RDATA;
reg [31:0] data;


input write;
input AWVALID;
input WVALID;
input BREADY;
input [31:0] i_AWADDR;
input [31:0] i_WDATA;
input [3:0] i_WSTRB;
input [1:0] i_BRESP;
output o_AWREADY;
output o_WREADY;
output o_BVALID;
output o_BRESP;
reg i_AWREADY;
reg i_WREADY;
reg i_BVALID;
wire [31:0] o_WDATA; 
wire o_BRESP;

always@(posedge ACLK)
begin
if(ARESETn)
begin
i_ARREADY<=0;
i_RVALID<=0;
end
else
begin 
if(read)
begin
i_ARREADY<=1;
i_RVALID<=1;
i_RDATA<=data;
end
else
begin
i_ARREADY<=0;
i_RVALID<=0;
end
if(write)
begin
i_AWREADY<=1;
i_WREADY<=1;
data<=o_WDATA;
if(BREADY)
i_BVALID<=1; 
else 
i_BVALID<=0;
end

end
end
write_address_slave was(ACLK,ARESETn, AWVALID, i_AWREADY, o_AWREADY, i_AWADDR, o_AWADDR);
write_data_slave wds(ACLK, ARESETn,WVALID, o_WREADY, i_WREADY, i_WDATA, o_WDATA,i_WSTRB, o_WSTRB);
write_response_slave wrs(ACLK, ARESETn,i_BVALID, o_BVALID, BREADY, i_BRESP, o_BRESP);

read_address_slave ras(ACLK, ARESETn, i_ARREADY, o_ARREADY, ARVALID, i_ARADDR, o_ARADDR);
read_data_slave rds(ACLK, ARESETn, i_RVALID, o_RVALID, RREADY, i_RDATA, o_RDATA, i_RRESP, o_RRESP);
endmodule
module slave1(ACLK, ARESETn,ARVALID,RREADY,o_ARREADY,i_ARADDR,o_RVALID,o_RDATA,o_RRESP,read,
write,AWVALID,WVALID,BREADY,i_AWADDR,i_WDATA,i_WSTRB,i_BRESP,o_AWREADY,o_WREADY,o_BVALID,o_BRESP);

input ACLK;
input ARESETn;

input ARVALID;
input RREADY;
input read;
output  o_ARREADY; 
output  o_RVALID;
input[31:0] i_ARADDR;
output [31:0] o_RDATA;
output [1:0] o_RRESP;
reg i_ARREADY;
reg i_RVALID;
wire [32:0] o_ARADDR;
reg [32:0] i_RDATA;
reg [31:0] data;


input write;
input AWVALID;
input WVALID;
input BREADY;
input [31:0] i_AWADDR;
input [31:0] i_WDATA;
input [3:0] i_WSTRB;
input [1:0] i_BRESP;
output o_AWREADY;
output o_WREADY;
output o_BVALID;
output o_BRESP;
reg i_AWREADY;
reg i_WREADY;
reg i_BVALID;
wire [31:0] o_WDATA; 
wire o_BRESP;

always@(posedge ACLK)
begin
if(ARESETn)
begin
i_ARREADY<=0;
i_RVALID<=0;
end
else
begin 
if(read)
begin
i_ARREADY<=1;
i_RVALID<=1;
i_RDATA<=data;
end
else
begin
i_ARREADY<=0;
i_RVALID<=0;
end
if(write)
begin
i_AWREADY<=1;
i_WREADY<=1;
data<=o_WDATA;
if(BREADY)
i_BVALID<=1; 
else 
i_BVALID<=0;
end

end
end
write_address_slave was(ACLK,ARESETn, AWVALID, i_AWREADY, o_AWREADY, i_AWADDR, o_AWADDR);
write_data_slave wds(ACLK, ARESETn,WVALID, o_WREADY, i_WREADY, i_WDATA, o_WDATA,i_WSTRB, o_WSTRB);
write_response_slave wrs(ACLK, ARESETn,i_BVALID, o_BVALID, BREADY, i_BRESP, o_BRESP);

read_address_slave ras(ACLK, ARESETn, i_ARREADY, o_ARREADY, ARVALID, i_ARADDR, o_ARADDR);
read_data_slave rds(ACLK, ARESETn, i_RVALID, o_RVALID, RREADY, i_RDATA, o_RDATA, i_RRESP, o_RRESP);
endmodule