data/full_repos/permissive/435885222/sources/if_id.v
data/verilator_xmls/0848a7f3-2bbe-43fe-ab1b-ca15d946aea3.xml
module if_id(
    input clk,
    input rst,
    input [31:0] if_pc,
    input [31:0] if_inst,
    output reg[31:0] id_pc,
    output reg[31:0] id_inst
    );
    always @(posedge clk)begin
        if(rst==1'b1)begin
            id_pc<=32'h00000000;
            id_inst<=32'h00000000;
        end else begin
                id_pc<=if_pc;
                id_inst<=if_inst;
            end
    end
endmodule
module if_id(
    input clk,
    input rst,
    input [31:0] if_pc,
    input [31:0] if_inst,
    output reg[31:0] id_pc,
    output reg[31:0] id_inst
    );

    always @(posedge clk)begin
        if(rst==1'b1)begin
            id_pc<=32'h00000000;
            id_inst<=32'h00000000;
        end else begin
                id_pc<=if_pc;
                id_inst<=if_inst;
            end
    end
endmodule