data/full_repos/permissive/434840709/week10/8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/434840709/week10/8.v:15: Signal definition not found, creating implicitly: \'temp\'\nassign temp = in1 ^ in2;\n       ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module (

    input in1,

    input in2,

    input in3,

    output out
);




assign temp = in1 ^ in2;
assign out = temp ~^ in3;

endmodule
module top_module (

    input in1,

    input in2,

    input in3,

    output out
);





assign temp = in1 ^ in2;
assign out = temp ~^ in3;

endmodule