data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:88: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'decoder_with_data_in_5to29\'\nmodule decoder_with_data_in_5to29(enable,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'decoder5to29\'\nmodule decoder5to29(enable,\n       ^~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:94: Little bit endian vector: MSB < LSB of bit range: 0:4\ninput [0:4] address;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:96: Little bit endian vector: MSB < LSB of bit range: 0:28\noutput [0:28] data_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:22: Little bit endian vector: MSB < LSB of bit range: 0:4\ninput [0:4] address;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:26: Little bit endian vector: MSB < LSB of bit range: 0:28\noutput [0:28] data_out;\n       ^\n%Error: Exiting due to 5 warning(s)\n'
module decoder_with_data_in_5to29(enable,
                                  address,
                                  data_in,
                                  data_out);

input [0:0] enable;

input [0:4] address;

input [0:0] data_in;

output [0:28] data_out;






reg [0:28] data_out;



always@(address[0:4], enable[0], data_in[0]) begin
	if (enable[0] == 1'b1) begin
		data_out[0:28] = {29{1'bz}};
		case (address[0:4])
			{5{1'b0}} : data_out[0] = data_in[0];
			5'b10000 : data_out[1] = data_in[0];
			5'b01000 : data_out[2] = data_in[0];
			5'b11000 : data_out[3] = data_in[0];
			5'b00100 : data_out[4] = data_in[0];
			5'b10100 : data_out[5] = data_in[0];
			5'b01100 : data_out[6] = data_in[0];
			5'b11100 : data_out[7] = data_in[0];
			5'b00010 : data_out[8] = data_in[0];
			5'b10010 : data_out[9] = data_in[0];
			5'b01010 : data_out[10] = data_in[0];
			5'b11010 : data_out[11] = data_in[0];
			5'b00110 : data_out[12] = data_in[0];
			5'b10110 : data_out[13] = data_in[0];
			5'b01110 : data_out[14] = data_in[0];
			5'b11110 : data_out[15] = data_in[0];
			5'b00001 : data_out[16] = data_in[0];
			5'b10001 : data_out[17] = data_in[0];
			5'b01001 : data_out[18] = data_in[0];
			5'b11001 : data_out[19] = data_in[0];
			5'b00101 : data_out[20] = data_in[0];
			5'b10101 : data_out[21] = data_in[0];
			5'b01101 : data_out[22] = data_in[0];
			5'b11101 : data_out[23] = data_in[0];
			5'b00011 : data_out[24] = data_in[0];
			5'b10011 : data_out[25] = data_in[0];
			5'b01011 : data_out[26] = data_in[0];
			5'b11011 : data_out[27] = data_in[0];
			5'b00111 : data_out[28] = data_in[0];
			default : 		data_out[0:28] = {29{1'bz}};
		endcase
	end
	else begin
		data_out[0:28] = {29{1'bz}};
	end
end

endmodule
module decoder_with_data_in_5to29(enable,
                                  address,
                                  data_in,
                                  data_out);


input [0:0] enable;

input [0:4] address;

input [0:0] data_in;

output [0:28] data_out;






reg [0:28] data_out;



always@(address[0:4], enable[0], data_in[0]) begin
	if (enable[0] == 1'b1) begin
		data_out[0:28] = {29{1'bz}};
		case (address[0:4])
			{5{1'b0}} : data_out[0] = data_in[0];
			5'b10000 : data_out[1] = data_in[0];
			5'b01000 : data_out[2] = data_in[0];
			5'b11000 : data_out[3] = data_in[0];
			5'b00100 : data_out[4] = data_in[0];
			5'b10100 : data_out[5] = data_in[0];
			5'b01100 : data_out[6] = data_in[0];
			5'b11100 : data_out[7] = data_in[0];
			5'b00010 : data_out[8] = data_in[0];
			5'b10010 : data_out[9] = data_in[0];
			5'b01010 : data_out[10] = data_in[0];
			5'b11010 : data_out[11] = data_in[0];
			5'b00110 : data_out[12] = data_in[0];
			5'b10110 : data_out[13] = data_in[0];
			5'b01110 : data_out[14] = data_in[0];
			5'b11110 : data_out[15] = data_in[0];
			5'b00001 : data_out[16] = data_in[0];
			5'b10001 : data_out[17] = data_in[0];
			5'b01001 : data_out[18] = data_in[0];
			5'b11001 : data_out[19] = data_in[0];
			5'b00101 : data_out[20] = data_in[0];
			5'b10101 : data_out[21] = data_in[0];
			5'b01101 : data_out[22] = data_in[0];
			5'b11101 : data_out[23] = data_in[0];
			5'b00011 : data_out[24] = data_in[0];
			5'b10011 : data_out[25] = data_in[0];
			5'b01011 : data_out[26] = data_in[0];
			5'b11011 : data_out[27] = data_in[0];
			5'b00111 : data_out[28] = data_in[0];
			default : 		data_out[0:28] = {29{1'bz}};
		endcase
	end
	else begin
		data_out[0:28] = {29{1'bz}};
	end
end

endmodule