data/full_repos/permissive/448627443/Peripherals/APB_UART/RTL/UART.v
data/verilator_xmls/7840526d-fdcf-42be-abd3-2afae07c246c.xml
module UART_TX (
  input               io_tick,
  input               io_data_valid,
  output reg          io_data_ready,
  input      [7:0]    io_data_payload,
  output              io_txd,
  output              io_busy,
  input               clk,
  input               resetn
);
  reg        [2:0]    subDiv_counter;
  reg                 subDiv_tick;
  wire                when_UART_TX_l30;
  reg        [2:0]    bitCnt_value;
  reg        `UartState_binary_sequential_type stateMac_state;
  reg                 stateMac_txd;
  reg                 io_tick_regNext;
  wire                when_UART_TX_l60;
  wire                when_UART_TX_l74;
  reg                 stateMac_txd_regNext;
  `ifndef SYNTHESIS
  reg [39:0] stateMac_state_string;
  `endif


  `ifndef SYNTHESIS
  always @(*) begin
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : stateMac_state_string = "IDLE ";
      `UartState_binary_sequential_START : stateMac_state_string = "START";
      `UartState_binary_sequential_DATA : stateMac_state_string = "DATA ";
      `UartState_binary_sequential_STOP : stateMac_state_string = "STOP ";
      default : stateMac_state_string = "?????";
    endcase
  end
  `endif

  assign when_UART_TX_l30 = (subDiv_counter == 3'b000);
  always @(*) begin
    io_data_ready = 1'b0;
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
      end
      `UartState_binary_sequential_START : begin
      end
      `UartState_binary_sequential_DATA : begin
        if(when_UART_TX_l74) begin
          io_data_ready = 1'b1;
        end
      end
      default : begin
      end
    endcase
  end

  always @(*) begin
    stateMac_txd = 1'b1;
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
      end
      `UartState_binary_sequential_START : begin
        stateMac_txd = 1'b0;
      end
      `UartState_binary_sequential_DATA : begin
        stateMac_txd = io_data_payload[bitCnt_value];
      end
      default : begin
      end
    endcase
  end

  assign when_UART_TX_l60 = (io_data_valid && io_tick_regNext);
  assign when_UART_TX_l74 = ((bitCnt_value == 3'b111) && subDiv_tick);
  assign io_txd = stateMac_txd_regNext;
  assign io_busy = (stateMac_state != `UartState_binary_sequential_IDLE);
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      subDiv_counter <= 3'b000;
      stateMac_state <= `UartState_binary_sequential_IDLE;
      stateMac_txd_regNext <= 1'b1;
    end else begin
      if(io_tick) begin
        if(when_UART_TX_l30) begin
          subDiv_counter <= 3'b111;
        end else begin
          subDiv_counter <= (subDiv_counter - 3'b001);
        end
      end
      case(stateMac_state)
        `UartState_binary_sequential_IDLE : begin
          if(when_UART_TX_l60) begin
            subDiv_counter <= 3'b111;
            stateMac_state <= `UartState_binary_sequential_START;
          end
        end
        `UartState_binary_sequential_START : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_binary_sequential_DATA;
          end
        end
        `UartState_binary_sequential_DATA : begin
          if(when_UART_TX_l74) begin
            stateMac_state <= `UartState_binary_sequential_STOP;
          end
        end
        default : begin
          if(subDiv_tick) begin
            if(io_data_valid) begin
              stateMac_state <= `UartState_binary_sequential_START;
            end else begin
              stateMac_state <= `UartState_binary_sequential_IDLE;
            end
          end
        end
      endcase
      stateMac_txd_regNext <= stateMac_txd;
    end
  end

  always @(posedge clk) begin
    subDiv_tick <= ((subDiv_counter == 3'b000) && io_tick);
    if(subDiv_tick) begin
      bitCnt_value <= (bitCnt_value + 3'b001);
    end
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
        if(when_UART_TX_l60) begin
          subDiv_tick <= 1'b0;
        end
      end
      `UartState_binary_sequential_START : begin
        if(subDiv_tick) begin
          bitCnt_value <= 3'b000;
        end
      end
      `UartState_binary_sequential_DATA : begin
      end
      default : begin
      end
    endcase
  end

  always @(posedge clk) begin
    io_tick_regNext <= io_tick;
  end


endmodule
module UART_TX (
  input               io_tick,
  input               io_data_valid,
  output reg          io_data_ready,
  input      [7:0]    io_data_payload,
  output              io_txd,
  output              io_busy,
  input               clk,
  input               resetn
);

  reg        [2:0]    subDiv_counter;
  reg                 subDiv_tick;
  wire                when_UART_TX_l30;
  reg        [2:0]    bitCnt_value;
  reg        `UartState_binary_sequential_type stateMac_state;
  reg                 stateMac_txd;
  reg                 io_tick_regNext;
  wire                when_UART_TX_l60;
  wire                when_UART_TX_l74;
  reg                 stateMac_txd_regNext;
  `ifndef SYNTHESIS
  reg [39:0] stateMac_state_string;
  `endif


  `ifndef SYNTHESIS
  always @(*) begin
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : stateMac_state_string = "IDLE ";
      `UartState_binary_sequential_START : stateMac_state_string = "START";
      `UartState_binary_sequential_DATA : stateMac_state_string = "DATA ";
      `UartState_binary_sequential_STOP : stateMac_state_string = "STOP ";
      default : stateMac_state_string = "?????";
    endcase
  end
  `endif

  assign when_UART_TX_l30 = (subDiv_counter == 3'b000);
  always @(*) begin
    io_data_ready = 1'b0;
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
      end
      `UartState_binary_sequential_START : begin
      end
      `UartState_binary_sequential_DATA : begin
        if(when_UART_TX_l74) begin
          io_data_ready = 1'b1;
        end
      end
      default : begin
      end
    endcase
  end

  always @(*) begin
    stateMac_txd = 1'b1;
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
      end
      `UartState_binary_sequential_START : begin
        stateMac_txd = 1'b0;
      end
      `UartState_binary_sequential_DATA : begin
        stateMac_txd = io_data_payload[bitCnt_value];
      end
      default : begin
      end
    endcase
  end

  assign when_UART_TX_l60 = (io_data_valid && io_tick_regNext);
  assign when_UART_TX_l74 = ((bitCnt_value == 3'b111) && subDiv_tick);
  assign io_txd = stateMac_txd_regNext;
  assign io_busy = (stateMac_state != `UartState_binary_sequential_IDLE);
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      subDiv_counter <= 3'b000;
      stateMac_state <= `UartState_binary_sequential_IDLE;
      stateMac_txd_regNext <= 1'b1;
    end else begin
      if(io_tick) begin
        if(when_UART_TX_l30) begin
          subDiv_counter <= 3'b111;
        end else begin
          subDiv_counter <= (subDiv_counter - 3'b001);
        end
      end
      case(stateMac_state)
        `UartState_binary_sequential_IDLE : begin
          if(when_UART_TX_l60) begin
            subDiv_counter <= 3'b111;
            stateMac_state <= `UartState_binary_sequential_START;
          end
        end
        `UartState_binary_sequential_START : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_binary_sequential_DATA;
          end
        end
        `UartState_binary_sequential_DATA : begin
          if(when_UART_TX_l74) begin
            stateMac_state <= `UartState_binary_sequential_STOP;
          end
        end
        default : begin
          if(subDiv_tick) begin
            if(io_data_valid) begin
              stateMac_state <= `UartState_binary_sequential_START;
            end else begin
              stateMac_state <= `UartState_binary_sequential_IDLE;
            end
          end
        end
      endcase
      stateMac_txd_regNext <= stateMac_txd;
    end
  end

  always @(posedge clk) begin
    subDiv_tick <= ((subDiv_counter == 3'b000) && io_tick);
    if(subDiv_tick) begin
      bitCnt_value <= (bitCnt_value + 3'b001);
    end
    case(stateMac_state)
      `UartState_binary_sequential_IDLE : begin
        if(when_UART_TX_l60) begin
          subDiv_tick <= 1'b0;
        end
      end
      `UartState_binary_sequential_START : begin
        if(subDiv_tick) begin
          bitCnt_value <= 3'b000;
        end
      end
      `UartState_binary_sequential_DATA : begin
      end
      default : begin
      end
    endcase
  end

  always @(posedge clk) begin
    io_tick_regNext <= io_tick;
  end


endmodule