data/full_repos/permissive/445216371/ALU.v
1: b'%Error: data/full_repos/permissive/445216371/ALU.v:37: Cannot find include file: parameters.vh\n    `include "parameters.vh" \n             ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.v\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.sv\n             parameters.vh\n             parameters.vh.v\n             parameters.vh.sv\n             obj_dir/parameters.vh\n             obj_dir/parameters.vh.v\n             obj_dir/parameters.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ALU (
    output reg [31:0] out,
    input [31:0] a,b,
    input [3:0] select
    );
    wire [31:0] aout,shout;
    wire lt,eq;
    wire [1:0] sh_select;

    `include "parameters.vh"

    
    add_sub ad(aout, a,b,select[3]);

    shift sh(shout, a,b[4:0],sh_select);

    compare cmp(lt,eq,a,b,select[0]);
    assign sh_select ={(select[2]&&select[0]&&(!select[1])),select[3]};









    always @(*) begin
        case (select)

            Paddition    : out <= aout;
            Psubtraction : out <= aout;

            PSLL         : out <= shout;
            PSRL         : out <= shout;
            PSRA         : out <= shout;

            PLT          : out <= {31'b0,lt};
            PLTU         : out <= {31'b0,lt};
            PEQL         : out <= {31'b0,eq};
            PEQU         : out <= {31'b0,eq};

            PXOR         : out <= a^b;
            POR          : out <= a|b;
            PAND         : out <= a&b;
            Ppassa       : out <=a;
            Ppassb       : out <=b;

            default: out<=32'b0;
        endcase 
    end 

endmodule
module ALU (
    output reg [31:0] out,
    input [31:0] a,b,
    input [3:0] select
    );

    wire [31:0] aout,shout;
    wire lt,eq;
    wire [1:0] sh_select;

    `include "parameters.vh"

    
    add_sub ad(aout, a,b,select[3]);

    shift sh(shout, a,b[4:0],sh_select);

    compare cmp(lt,eq,a,b,select[0]);
    assign sh_select ={(select[2]&&select[0]&&(!select[1])),select[3]};









    always @(*) begin
        case (select)

            Paddition    : out <= aout;
            Psubtraction : out <= aout;

            PSLL         : out <= shout;
            PSRL         : out <= shout;
            PSRA         : out <= shout;

            PLT          : out <= {31'b0,lt};
            PLTU         : out <= {31'b0,lt};
            PEQL         : out <= {31'b0,eq};
            PEQU         : out <= {31'b0,eq};

            PXOR         : out <= a^b;
            POR          : out <= a|b;
            PAND         : out <= a&b;
            Ppassa       : out <=a;
            Ppassb       : out <=b;

            default: out<=32'b0;
        endcase 
    end 

endmodule