data/full_repos/permissive/497870922/testbench/tb_ubsoc.v
1: b'%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:33: Unsupported: event data types\n event ser_sample;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:59: Unsupported: Ignoring delay on this delayed statement.\n     #HALF_CLOCK_PERIOD_50M;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:61: Unsupported: Ignoring delay on this delayed statement.\n     #HALF_CLOCK_PERIOD_50M;\n     ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:71: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:75: syntax error, unexpected \'@\'\n    repeat (ser_half_period) @(posedge clk);\n                             ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:76: syntax error, unexpected \'@\'\n    repeat (ser_half_period) @(posedge clk);\n                             ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:80: syntax error, unexpected ->\n    -> ser_sample;  \n    ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:83: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:84: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:109: Unsupported: Ignoring delay on this delayed statement.\n  repeat(50)  #100000;  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:111: Unsupported: Ignoring delay on this delayed statement.\n  repeat(30)  #100000;  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:113: Unsupported: Ignoring delay on this delayed statement.\n  repeat(150) #100000;  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:121: Unsupported: Ignoring delay on this delayed statement.\n  repeat(150) #100000;  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:185: syntax error, unexpected \'@\'\n  @(negedge ser_tx);\n  ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:187: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:191: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:192: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:194: syntax error, unexpected ->\n   -> ser_sample;  \n   ^~\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:197: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: data/full_repos/permissive/497870922/testbench/tb_ubsoc.v:198: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: Exiting due to 14 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_picosoc;
	reg clk;

	wire [7:0] test_led;
	reg  [7:0] test_button = 0;
	reg  [7:0] test_switch = 0;

	wire ser_tx;
	reg  ser_rx = 1'b1;

	localparam ser_half_period = 217;
	event ser_sample;

	reg [7:0] buffer = {(8){1'bz}};
	reg [7:0] rx_buffer = {(8){1'bz}};

	tri1 test_scl, test_sda;
	reg i2c_slave_rst;

	wire test_spi_miso;
	wire [7:0] test_spi_ss;
	wire test_spi_mosi;
	wire test_spi_sck;
	wire test_spi_cpol;
	wire test_spi_cpha;


	parameter HALF_CLOCK_PERIOD_50M 	= 10;
	parameter HALF_CLOCK_PERIOD_32M		= 15625;
	parameter HALF_CLOCK_PERIOD_10M 	= 50000;
	parameter HALF_CLOCK_PERIOD_1M 		= 500000;
	parameter HALF_CLOCK_PERIOD_100K 	= 5000000;
	parameter HALF_CLOCK_PERIOD_4608 	= 108506944;


	always begin
		clk = 1;
    	#HALF_CLOCK_PERIOD_50M;
    	clk = 0;
    	#HALF_CLOCK_PERIOD_50M;
	end

	task PRESS_KEY;
		input [7:0]	KEY;	
		begin
			buffer = 0;
			ser_rx = 1'b0;
			rx_buffer = KEY;

			repeat (ser_half_period) @(posedge clk);
			-> ser_sample;

			repeat (8) begin
				repeat (ser_half_period) @(posedge clk);
				repeat (ser_half_period) @(posedge clk);
				ser_rx = rx_buffer[0];
				buffer = {ser_rx, buffer[7:1]};
				rx_buffer = {1'b0, rx_buffer[6:1]};
				-> ser_sample;
			end

			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			-> ser_sample;
			
			ser_rx = 1'b1;
		end
	endtask

	task PRESS_ENTER;
		parameter KEY_ENTER = 8'h0D;
		
		begin
			PRESS_KEY(KEY_ENTER);

			if (buffer == KEY_ENTER)
				$display("ENTER PRESSED");
			else
				$display("INCORRECT KEY");			
		end
	endtask	

	initial begin
		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;
		repeat(50)  #100000;		
		PRESS_ENTER;
		repeat(30)  #100000;
		PRESS_KEY(8'h34);
		repeat(150) #100000;

		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;

		PRESS_KEY(8'h31);
		repeat(150) #100000;

		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;

		PRESS_KEY(8'h34);

	end

	ubsoc_debug uut (
		.clk_i    	  (clk      	 ),

		.suart_tx_o       (ser_tx   	 ),
		.suart_rx_i       (ser_rx   	 ),
 
		.gpio_led_o 	  (test_led      ),
		.gpio_switch_i    (test_switch   ),
		.gpio_button_i    (test_button   ),

		.i2c_scl_mst_o    (test_scl      ),
		.i2c_sda_mst_io   (test_sda      ),

		.i2c_scl_slv_i    (test_scl      ),
		.i2c_sda_slv_io   (test_sda      )


	);










	always begin
		@(negedge ser_tx);

		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		repeat (8) begin
			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			buffer = {ser_tx, buffer[7:1]};
			-> ser_sample;
		end

		repeat (ser_half_period) @(posedge clk);
		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		if (buffer < 32 || buffer >= 127) begin
			if (buffer == 13) $display("");
			else if (buffer == 10) ;
			else $write("%d", buffer);
		end
		else
			$write("%c", buffer);
	end

endmodule
module tb_picosoc;

	reg clk;

	wire [7:0] test_led;
	reg  [7:0] test_button = 0;
	reg  [7:0] test_switch = 0;

	wire ser_tx;
	reg  ser_rx = 1'b1;

	localparam ser_half_period = 217;
	event ser_sample;

	reg [7:0] buffer = {(8){1'bz}};
	reg [7:0] rx_buffer = {(8){1'bz}};

	tri1 test_scl, test_sda;
	reg i2c_slave_rst;

	wire test_spi_miso;
	wire [7:0] test_spi_ss;
	wire test_spi_mosi;
	wire test_spi_sck;
	wire test_spi_cpol;
	wire test_spi_cpha;


	parameter HALF_CLOCK_PERIOD_50M 	= 10;
	parameter HALF_CLOCK_PERIOD_32M		= 15625;
	parameter HALF_CLOCK_PERIOD_10M 	= 50000;
	parameter HALF_CLOCK_PERIOD_1M 		= 500000;
	parameter HALF_CLOCK_PERIOD_100K 	= 5000000;
	parameter HALF_CLOCK_PERIOD_4608 	= 108506944;


	always begin
		clk = 1;
    	#HALF_CLOCK_PERIOD_50M;
    	clk = 0;
    	#HALF_CLOCK_PERIOD_50M;
	end

	task PRESS_KEY;
		input [7:0]	KEY;	
		begin
			buffer = 0;
			ser_rx = 1'b0;
			rx_buffer = KEY;

			repeat (ser_half_period) @(posedge clk);
			-> ser_sample;

			repeat (8) begin
				repeat (ser_half_period) @(posedge clk);
				repeat (ser_half_period) @(posedge clk);
				ser_rx = rx_buffer[0];
				buffer = {ser_rx, buffer[7:1]};
				rx_buffer = {1'b0, rx_buffer[6:1]};
				-> ser_sample;
			end

			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			-> ser_sample;
			
			ser_rx = 1'b1;
		end
	endtask

	task PRESS_ENTER;
		parameter KEY_ENTER = 8'h0D;
		
		begin
			PRESS_KEY(KEY_ENTER);

			if (buffer == KEY_ENTER)
				$display("ENTER PRESSED");
			else
				$display("INCORRECT KEY");			
		end
	endtask	

	initial begin
		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;
		repeat(50)  #100000;		
		PRESS_ENTER;
		repeat(30)  #100000;
		PRESS_KEY(8'h34);
		repeat(150) #100000;

		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;

		PRESS_KEY(8'h31);
		repeat(150) #100000;

		#10;
		i2c_slave_rst = 1;
		#100;
		i2c_slave_rst = 0;

		PRESS_KEY(8'h34);

	end

	ubsoc_debug uut (
		.clk_i    	  (clk      	 ),

		.suart_tx_o       (ser_tx   	 ),
		.suart_rx_i       (ser_rx   	 ),
 
		.gpio_led_o 	  (test_led      ),
		.gpio_switch_i    (test_switch   ),
		.gpio_button_i    (test_button   ),

		.i2c_scl_mst_o    (test_scl      ),
		.i2c_sda_mst_io   (test_sda      ),

		.i2c_scl_slv_i    (test_scl      ),
		.i2c_sda_slv_io   (test_sda      )


	);










	always begin
		@(negedge ser_tx);

		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		repeat (8) begin
			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			buffer = {ser_tx, buffer[7:1]};
			-> ser_sample;
		end

		repeat (ser_half_period) @(posedge clk);
		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		if (buffer < 32 || buffer >= 127) begin
			if (buffer == 13) $display("");
			else if (buffer == 10) ;
			else $write("%d", buffer);
		end
		else
			$write("%c", buffer);
	end

endmodule