data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk<=~clk;\n       ^\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top_tb.v:32: Cannot find file containing module: \'top\'\ntop Utop(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/top\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/top.v\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;
	reg				clk		;	
	reg				rst_n	=0;
	reg	[31:0]		cnt=0		;
	reg				key_wei		=1;
	reg				key_shuzi	=1;
	reg				key_enter	=1;
	reg				key_input	=1;
	reg				key_disp	=1;
	wire[7:0]		pos;
	wire[7:0]		seg;






initial
begin
	clk = 0;
	#1000
	rst_n=1;
end
always #10 clk<=~clk;
always@(posedge clk)cnt<=cnt+1;
always@(posedge clk)begin if(cnt<=100000&&cnt> 50000)key_input<=1; else key_input<=0;end
always@(posedge clk)begin if(cnt<=200000&&cnt>150000)key_wei<=1;else key_wei<=0;end
always@(posedge clk)begin if(cnt<=400000&&cnt>350000)key_shuzi<=1; else key_shuzi<=0;end
always@(posedge clk)begin if(cnt<=500000&&cnt>450000)key_enter<=1; else key_enter<=0;end
always@(posedge clk)begin if(cnt<=600000&&cnt>550000)key_disp<=1; else key_disp<=0;end
top Utop(
.clk100mhz	(clk),
.clr		(rst_n),
.key_wei	(key_wei	),
.key_shuzi	(key_shuzi	),
.key_enter	(key_enter	),
.key_input	(key_input	),
.key_disp	(key_disp	),
.pos_b		(),
.seg_b      (),
.pos_f		(),
.seg_f      ()
    );
endmodule
module top_tb;

	reg				clk		;	
	reg				rst_n	=0;
	reg	[31:0]		cnt=0		;
	reg				key_wei		=1;
	reg				key_shuzi	=1;
	reg				key_enter	=1;
	reg				key_input	=1;
	reg				key_disp	=1;
	wire[7:0]		pos;
	wire[7:0]		seg;






initial
begin
	clk = 0;
	#1000
	rst_n=1;
end
always #10 clk<=~clk;
always@(posedge clk)cnt<=cnt+1;
always@(posedge clk)begin if(cnt<=100000&&cnt> 50000)key_input<=1; else key_input<=0;end
always@(posedge clk)begin if(cnt<=200000&&cnt>150000)key_wei<=1;else key_wei<=0;end
always@(posedge clk)begin if(cnt<=400000&&cnt>350000)key_shuzi<=1; else key_shuzi<=0;end
always@(posedge clk)begin if(cnt<=500000&&cnt>450000)key_enter<=1; else key_enter<=0;end
always@(posedge clk)begin if(cnt<=600000&&cnt>550000)key_disp<=1; else key_disp<=0;end
top Utop(
.clk100mhz	(clk),
.clr		(rst_n),
.key_wei	(key_wei	),
.key_shuzi	(key_shuzi	),
.key_enter	(key_enter	),
.key_input	(key_input	),
.key_disp	(key_disp	),
.pos_b		(),
.seg_b      (),
.pos_f		(),
.seg_f      ()
    );
endmodule