data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Arithmetic_Circuits/69_m2014_q4j.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Arithmetic_Circuits/69_m2014_q4j.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sum'\n                                                                                                                             : ... In instance top_module\n            sum[i] = x[i] ^ y[i] ^ cout[i-1];\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Arithmetic_Circuits/69_m2014_q4j.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cout'\n                                                                                                                             : ... In instance top_module\n            cout[i] = x[i] & y[i] | x[i] & cout[i-1] | y[i] & cout[i-1];\n            ^~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);

    integer i;
    wire [3:0] cout;
    assign sum[0] = x[0] ^ y[0];
    assign cout[0] = x[0] & y[0];
    always @(*) begin
        for(i = 1; i < 4; i=i+1) begin
            sum[i] = x[i] ^ y[i] ^ cout[i-1];
            cout[i] = x[i] & y[i] | x[i] & cout[i-1] | y[i] & cout[i-1];
        end
        sum[4] = cout[3];
    end
endmodule
module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);


    integer i;
    wire [3:0] cout;
    assign sum[0] = x[0] ^ y[0];
    assign cout[0] = x[0] & y[0];
    always @(*) begin
        for(i = 1; i < 4; i=i+1) begin
            sum[i] = x[i] ^ y[i] ^ cout[i-1];
            cout[i] = x[i] & y[i] | x[i] & cout[i-1] | y[i] & cout[i-1];
        end
        sum[4] = cout[3];
    end
endmodule