data/full_repos/permissive/458737381/src/verilog-parser/tests/hello_world.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/hello_world.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hello_world ;

initial begin
  $display ("Hello World by Deepak");
  #10 $finish;
end

endmodule
module hello_world ;


initial begin
  $display ("Hello World by Deepak");
  #10 $finish;
end

endmodule