data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v
1: b'%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:53: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\nassign memout_b = mem[addr_b];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:53: Operator ASSIGNW expects 30 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\nassign memout_b = mem[addr_b];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:54: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\nassign memout = mem[addr_a];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:62: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\n            mem[addr_a] <= din_a;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:65: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\n            mem[addr_b] <= din_b;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:77: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\n            dout_a <= mem[addr_a];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/fpga_double_ram_sy.v:80: Bit extraction of array[29:0] requires 5 bit index, not 3 bits.\n                                                                                                        : ... In instance fpga_double_ram_sy\n            dout_b <= mem[addr_b];\n                         ^\n%Error: Exiting due to 7 warning(s)\n'
module fpga_double_ram_sy(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b,
    load,
    memout
);
 output [2:0] memout;
 
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din_a;
input [ADDR_WIDTH-1:0] addr_a;
input we_a, oe_a;
output reg [DATA_WIDTH-1:0] dout_a;


input [DATA_WIDTH-1:0] din_b;
input [ADDR_WIDTH-1:0] addr_b;
input we_b, oe_b;
output reg [DATA_WIDTH-1:0] dout_b;

input load;
integer i;


reg [DATA_WIDTH-1:0] mem[RAM_DEPTH-1:0];
wire [RAM_DEPTH-1:0] memout_b;
assign memout_b = mem[addr_b];
assign memout = mem[addr_a];




always@(posedge load) begin
    if(!cs) begin
        if(we_a) begin
            mem[addr_a] <= din_a;
        end
        if(we_b) begin
            mem[addr_b] <= din_b;
        end
    end
    else begin
        for(i = 0; i < RAM_DEPTH; i = i + 1)
            mem[i] <= 0;
    end 
    end
    

    always@(posedge load) begin
        if(oe_a) begin
            dout_a <= mem[addr_a];
        end
        if(oe_b) begin
            dout_b <= mem[addr_b];
        end
    end


endmodule
module fpga_double_ram_sy(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b,
    load,
    memout
);

 output [2:0] memout;
 
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din_a;
input [ADDR_WIDTH-1:0] addr_a;
input we_a, oe_a;
output reg [DATA_WIDTH-1:0] dout_a;


input [DATA_WIDTH-1:0] din_b;
input [ADDR_WIDTH-1:0] addr_b;
input we_b, oe_b;
output reg [DATA_WIDTH-1:0] dout_b;

input load;
integer i;


reg [DATA_WIDTH-1:0] mem[RAM_DEPTH-1:0];
wire [RAM_DEPTH-1:0] memout_b;
assign memout_b = mem[addr_b];
assign memout = mem[addr_a];




always@(posedge load) begin
    if(!cs) begin
        if(we_a) begin
            mem[addr_a] <= din_a;
        end
        if(we_b) begin
            mem[addr_b] <= din_b;
        end
    end
    else begin
        for(i = 0; i < RAM_DEPTH; i = i + 1)
            mem[i] <= 0;
    end 
    end
    

    always@(posedge load) begin
        if(oe_a) begin
            dout_a <= mem[addr_a];
        end
        if(oe_b) begin
            dout_b <= mem[addr_b];
        end
    end


endmodule