data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/fifo_v2.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/fifo_v2.sv:89: Operator COND expects 18 bits on the Conditional True, but Conditional True\'s VARREF \'fifo_rdata\' generates 17 bits.\n                                                                                            : ... In instance fifo_v2\nassign {output_rlast, output_rdata} = dvalid ? fifo_rdata : datareg;\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489980666/old_ip/axi4lite-ddr-sdram/fifo_v2.sv:89: Operator COND expects 18 bits on the Conditional False, but Conditional False\'s VARREF \'datareg\' generates 17 bits.\n                                                                                            : ... In instance fifo_v2\nassign {output_rlast, output_rdata} = dvalid ? fifo_rdata : datareg;\n                                             ^\n%Error: Exiting due to 2 warning(s)\n'
module fifo_v2
#(
    parameter       DQ_LEVEL           = 1,
    parameter       AXI_DATA_WIDTH     = 16,
    parameter       ADDR_WIDTH         = 10,
    parameter       DATA_WIDTH         = 1 + AXI_DATA_WIDTH
)(
    input  wire                       rready,
    input  reg                        rstn,
    input  reg                        clk,
    input  reg                        input_valid_state,
    input  wire    [AXI_DATA_WIDTH:0] data,
    output wire    [AXI_DATA_WIDTH:0] output_rdata,
    output wire                       output_rlast,
    output wire                       read_valid,
    output wire                       read_accessible, 
    output wire                       read_respdone
);
  
reg  [ADDR_WIDTH-1:0] wpt = '0, rpt = '0;
reg  [DATA_WIDTH-1:0] datareg = '0;
reg  [DATA_WIDTH-1:0] fifo_rdata;
reg  [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)];
reg                   dvalid = '0;
reg                   valid = '0;
wire                  rreq;
wire   emptyn  = rpt != wpt;
wire   itready = rpt != (wpt + (ADDR_WIDTH)'(1));


always @ (posedge clk or negedge rstn)
    if(~rstn)
        wpt <= 0;
    else if(input_valid_state & itready)
        wpt <= wpt + (ADDR_WIDTH)'(1);
    
always @ (posedge clk or negedge rstn)
    if(~rstn)
        rpt <= 0;
    else if(rreq & emptyn)
        rpt <= rpt + (ADDR_WIDTH)'(1);

always @ (posedge clk or negedge rstn)
    if(~rstn) begin
        dvalid <= 1'b0;
        valid  <= 1'b0;
        datareg <= 0;
    end else begin
        dvalid <= rreq;
        if(dvalid)
            datareg <= fifo_rdata;
        if(rready)
            valid <= 1'b0;
        else if(dvalid)
            valid <= 1'b1;
    end

always @ (posedge clk)
    if(input_valid_state)
        mem[wpt] <= data;

always @ (posedge clk)
    fifo_rdata <= mem[rpt];
 
assign read_valid  = valid | dvalid;
assign rreq        = emptyn & ( rready | ~read_valid );
assign {output_rlast, output_rdata} = dvalid ? fifo_rdata : datareg;

assign read_accessible = ~read_valid;
assign read_respdone   = read_valid;

    
endmodule
module fifo_v2
#(
    parameter       DQ_LEVEL           = 1,
    parameter       AXI_DATA_WIDTH     = 16,
    parameter       ADDR_WIDTH         = 10,
    parameter       DATA_WIDTH         = 1 + AXI_DATA_WIDTH
)(
    input  wire                       rready,
    input  reg                        rstn,
    input  reg                        clk,
    input  reg                        input_valid_state,
    input  wire    [AXI_DATA_WIDTH:0] data,
    output wire    [AXI_DATA_WIDTH:0] output_rdata,
    output wire                       output_rlast,
    output wire                       read_valid,
    output wire                       read_accessible, 
    output wire                       read_respdone
);

  
reg  [ADDR_WIDTH-1:0] wpt = '0, rpt = '0;
reg  [DATA_WIDTH-1:0] datareg = '0;
reg  [DATA_WIDTH-1:0] fifo_rdata;
reg  [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)];
reg                   dvalid = '0;
reg                   valid = '0;
wire                  rreq;
wire   emptyn  = rpt != wpt;
wire   itready = rpt != (wpt + (ADDR_WIDTH)'(1));


always @ (posedge clk or negedge rstn)
    if(~rstn)
        wpt <= 0;
    else if(input_valid_state & itready)
        wpt <= wpt + (ADDR_WIDTH)'(1);
    
always @ (posedge clk or negedge rstn)
    if(~rstn)
        rpt <= 0;
    else if(rreq & emptyn)
        rpt <= rpt + (ADDR_WIDTH)'(1);

always @ (posedge clk or negedge rstn)
    if(~rstn) begin
        dvalid <= 1'b0;
        valid  <= 1'b0;
        datareg <= 0;
    end else begin
        dvalid <= rreq;
        if(dvalid)
            datareg <= fifo_rdata;
        if(rready)
            valid <= 1'b0;
        else if(dvalid)
            valid <= 1'b1;
    end

always @ (posedge clk)
    if(input_valid_state)
        mem[wpt] <= data;

always @ (posedge clk)
    fifo_rdata <= mem[rpt];
 
assign read_valid  = valid | dvalid;
assign rreq        = emptyn & ( rready | ~read_valid );
assign {output_rlast, output_rdata} = dvalid ? fifo_rdata : datareg;

assign read_accessible = ~read_valid;
assign read_respdone   = read_valid;

    
endmodule