data/full_repos/permissive/409259817/Delay_2_Reg.v
data/verilator_xmls/aff7f2c2-442f-4be3-aa48-fe0a4e52d0b8.xml
module Delay_2_Reg(
   clk_a,
   clk_b,
   rst_n,
   data_in,
   data_out);
   
   input               clk_a;
   input               clk_b;
   input               rst_n;
   input    [15:0]     data_in;
   output   [15:0]     data_out;
   
   reg      [15:0]     data_out_r1;
   reg      [15:0]     data_out_r2;
   always @ (posedge clk_b or negedge rst_n) begin
      if(!rst_n)
         begin
            data_out_r1 <= 16'd0;
            data_out_r1 <= 16'd0;
         end
      else
         begin
            data_out_r1 <= data_in;
            data_out_r2 <= data_out_r1;
         end
   end
   
   assign data_out = data_out_r2;

endmodule
module Delay_2_Reg(
   clk_a,
   clk_b,
   rst_n,
   data_in,
   data_out);

   
   input               clk_a;
   input               clk_b;
   input               rst_n;
   input    [15:0]     data_in;
   output   [15:0]     data_out;
   
   reg      [15:0]     data_out_r1;
   reg      [15:0]     data_out_r2;
   always @ (posedge clk_b or negedge rst_n) begin
      if(!rst_n)
         begin
            data_out_r1 <= 16'd0;
            data_out_r1 <= 16'd0;
         end
      else
         begin
            data_out_r1 <= data_in;
            data_out_r2 <= data_out_r1;
         end
   end
   
   assign data_out = data_out_r2;

endmodule