data/full_repos/permissive/523038000/lab3/seven_segments.v
1: b"%Error: data/full_repos/permissive/523038000/lab3/seven_segments.v:40: Cannot find file containing module: 'segments'\nsegments seg_inst0(word2display[3:0]  ,seven_segment0);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab3,data/full_repos/permissive/523038000/segments\n             data/full_repos/permissive/523038000/lab3,data/full_repos/permissive/523038000/segments.v\n             data/full_repos/permissive/523038000/lab3,data/full_repos/permissive/523038000/segments.sv\n             segments\n             segments.v\n             segments.sv\n             obj_dir/segments\n             obj_dir/segments.v\n             obj_dir/segments.sv\n%Error: data/full_repos/permissive/523038000/lab3/seven_segments.v:41: Cannot find file containing module: 'segments'\nsegments seg_inst1(word2display[7:4]  ,seven_segment1);\n^~~~~~~~\n%Error: data/full_repos/permissive/523038000/lab3/seven_segments.v:42: Cannot find file containing module: 'segments'\nsegments seg_inst2(word2display[11:8] ,seven_segment2);\n^~~~~~~~\n%Error: data/full_repos/permissive/523038000/lab3/seven_segments.v:43: Cannot find file containing module: 'segments'\nsegments seg_inst3(word2display[15:12],seven_segment3);\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module seven_segments(
	input clk,
	input [15:0] word2display,
	output reg [6:0] seven_segment,
	output dp,
	output reg [3:0] an
    );

reg [63:0] count;
wire [6:0] seven_segment0;
wire [6:0] seven_segment1;
wire [6:0] seven_segment2;
wire [6:0] seven_segment3;
	
assign dp = 1;

always@(posedge clk)
	count <= #1 count+1;

segments seg_inst0(word2display[3:0]  ,seven_segment0);
segments seg_inst1(word2display[7:4]  ,seven_segment1);
segments seg_inst2(word2display[11:8] ,seven_segment2);
segments seg_inst3(word2display[15:12],seven_segment3);

always@(posedge clk)
begin
	case(count[12:11])
	2'd0: begin seven_segment = ~seven_segment0; an = 4'b1110;end
	2'd1: begin seven_segment = ~seven_segment1; an = 4'b1101;end
	2'd2: begin seven_segment = ~seven_segment2; an = 4'b1011;end
	2'd3: begin seven_segment = ~seven_segment3; an = 4'b0111;end
	endcase
end
	
endmodule
module seven_segments(
	input clk,
	input [15:0] word2display,
	output reg [6:0] seven_segment,
	output dp,
	output reg [3:0] an
    );


reg [63:0] count;
wire [6:0] seven_segment0;
wire [6:0] seven_segment1;
wire [6:0] seven_segment2;
wire [6:0] seven_segment3;
	
assign dp = 1;

always@(posedge clk)
	count <= #1 count+1;

segments seg_inst0(word2display[3:0]  ,seven_segment0);
segments seg_inst1(word2display[7:4]  ,seven_segment1);
segments seg_inst2(word2display[11:8] ,seven_segment2);
segments seg_inst3(word2display[15:12],seven_segment3);

always@(posedge clk)
begin
	case(count[12:11])
	2'd0: begin seven_segment = ~seven_segment0; an = 4'b1110;end
	2'd1: begin seven_segment = ~seven_segment1; an = 4'b1101;end
	2'd2: begin seven_segment = ~seven_segment2; an = 4'b1011;end
	2'd3: begin seven_segment = ~seven_segment3; an = 4'b0111;end
	endcase
end
	
endmodule