data/full_repos/permissive/452305748/L4/counter/counter_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L4/counter/counter_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L4/counter/counter_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, counter_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L4/counter/counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #17 res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L4/counter/counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #6000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L4/counter/counter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk<=~clk;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;

reg clk,res;

wire [7:0] y;

counter counter(
    .clk(clk),
    .res(res),
    .y(y)
);

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, counter_tb);
    end

initial begin
        clk <= 0;
        res <= 0;
    #17 res <= 1;
    #6000 $finish;
end
always #5 clk<=~clk;
endmodule
module counter_tb;


reg clk,res;

wire [7:0] y;

counter counter(
    .clk(clk),
    .res(res),
    .y(y)
);

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, counter_tb);
    end

initial begin
        clk <= 0;
        res <= 0;
    #17 res <= 1;
    #6000 $finish;
end
always #5 clk<=~clk;
endmodule