data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_efuse_reg.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_efuse_reg.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_efuse_reg.v:32: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_efuse_reg.v:49: Define or directive not defined: \'`IOB_FUSE_WIDTH\'\n   parameter REG_WIDTH = `IOB_FUSE_WIDTH;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_efuse_reg.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter REG_WIDTH = `IOB_FUSE_WIDTH;\n                                        ^\n%Error: Exiting due to 4 error(s)\n'
module iobdg_efuse_reg (

   fuse_reg, 

   arst_l, fuse_clk, data_in, shift_en
   );


   parameter REG_WIDTH = `IOB_FUSE_WIDTH;
   



   input                     arst_l;
   input                     fuse_clk;
   input 		     data_in;
   input 		     shift_en;
   output [REG_WIDTH-1:0]    fuse_reg;
   
   wire [REG_WIDTH-1:0]      fuse_reg_next;
   
   




   assign 	fuse_reg_next = shift_en ? {fuse_reg[REG_WIDTH-2:0],data_in} :
		                           fuse_reg;
   
   dffsl_async_ns #(REG_WIDTH) fuse_reg_ff (.din(fuse_reg_next),
					    .set_l(arst_l),
					    .clk(fuse_clk),
					    .q(fuse_reg));

   
endmodule
module iobdg_efuse_reg (

   fuse_reg, 

   arst_l, fuse_clk, data_in, shift_en
   );



   parameter REG_WIDTH = `IOB_FUSE_WIDTH;
   



   input                     arst_l;
   input                     fuse_clk;
   input 		     data_in;
   input 		     shift_en;
   output [REG_WIDTH-1:0]    fuse_reg;
   
   wire [REG_WIDTH-1:0]      fuse_reg_next;
   
   




   assign 	fuse_reg_next = shift_en ? {fuse_reg[REG_WIDTH-2:0],data_in} :
		                           fuse_reg;
   
   dffsl_async_ns #(REG_WIDTH) fuse_reg_ff (.din(fuse_reg_next),
					    .set_l(arst_l),
					    .clk(fuse_clk),
					    .q(fuse_reg));

   
endmodule