data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v
1: b'%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:26: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:28: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:38: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:42: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:51: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:54: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:65: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:71: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/433225833/Testbench/buffer_memory_tb.v:82: Unsupported or unknown PLI call: $monitor\n    $monitor("%3d\\t%h\\t%h\\t%h\\t%h\\t%h\\t%h\\t%h\\t%h",\n    ^~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module buffer_memory_tb ();
  reg [13:0] addr_wr, addr_rd;
  reg [31:0] data_in;
  reg rd_en, wr_en, clk, reset;
  wire [31:0] data_out;
  
  initial begin
    clk = 0;
    reset_mem();
    write_mem(0, 'hABCD);
    write_mem(1, 'hEF01);
    write_mem(2, 'h2345);
    
    read_mem(0);
    read_mem(1);
    read_mem(2);
    
    read_write_mem(0, 'hAAAA_AAAA, 0);
    read_write_mem(1, 'hBBBB_BBBB, 2);
    
    $finish;
  end
  
  task reset_mem;
    begin
      @(negedge clk);
      reset = 1;
      @(negedge clk);
      reset = 0;
    end
  endtask
  
  task write_mem;
    input [13:0] addr_wr_value;
    input [31:0] data_in_value;
    
    begin
      @(negedge clk)
      wr_en = 1;
      addr_wr = addr_wr_value;
      data_in = data_in_value;
      @(negedge clk)
      wr_en = 0;
    end
  endtask
  
  task read_mem;
    input [13:0] addr_rd_value;
    
    begin
      @(negedge clk)
      rd_en = 1;
      addr_rd = addr_rd_value;
      @(negedge clk);
      rd_en = 0;
    end
  endtask
  
  task read_write_mem;
    input [13:0] addr_wr_value;
    input [31:0] data_in_value;
    input [13:0] addr_rd_value;
    
    begin
      @(negedge clk)
      rd_en = 1;
      wr_en = 1;
      addr_wr = addr_wr_value;
      data_in = data_in_value;
      addr_rd = addr_rd_value;
      @(negedge clk)
      wr_en = 0;
      rd_en = 0;
    end
  endtask
  
  always
    #1 clk = ~clk;
  
  initial begin
    $display("  T\taddrWr\tadddRd\tdin\t\trd_en\twr_en\tclk\treset\tdout");
    $monitor("%3d\t%h\t%h\t%h\t%h\t%h\t%h\t%h\t%h",
             $time, addr_wr, addr_rd, data_in, rd_en, wr_en, clk, reset, data_out);
  end
  
  buffer_memory dut 
  (.addr_wr(addr_wr), .addr_rd(addr_rd), .data_in(data_in),
                     .rd_en(rd_en), .wr_en(wr_en), .clk(clk), .reset(reset),
                     .data_out(data_out));
  
endmodule
module buffer_memory_tb ();

  reg [13:0] addr_wr, addr_rd;
  reg [31:0] data_in;
  reg rd_en, wr_en, clk, reset;
  wire [31:0] data_out;
  
  initial begin
    clk = 0;
    reset_mem();
    write_mem(0, 'hABCD);
    write_mem(1, 'hEF01);
    write_mem(2, 'h2345);
    
    read_mem(0);
    read_mem(1);
    read_mem(2);
    
    read_write_mem(0, 'hAAAA_AAAA, 0);
    read_write_mem(1, 'hBBBB_BBBB, 2);
    
    $finish;
  end
  
  task reset_mem;
    begin
      @(negedge clk);
      reset = 1;
      @(negedge clk);
      reset = 0;
    end
  endtask
  
  task write_mem;
    input [13:0] addr_wr_value;
    input [31:0] data_in_value;
    
    begin
      @(negedge clk)
      wr_en = 1;
      addr_wr = addr_wr_value;
      data_in = data_in_value;
      @(negedge clk)
      wr_en = 0;
    end
  endtask
  
  task read_mem;
    input [13:0] addr_rd_value;
    
    begin
      @(negedge clk)
      rd_en = 1;
      addr_rd = addr_rd_value;
      @(negedge clk);
      rd_en = 0;
    end
  endtask
  
  task read_write_mem;
    input [13:0] addr_wr_value;
    input [31:0] data_in_value;
    input [13:0] addr_rd_value;
    
    begin
      @(negedge clk)
      rd_en = 1;
      wr_en = 1;
      addr_wr = addr_wr_value;
      data_in = data_in_value;
      addr_rd = addr_rd_value;
      @(negedge clk)
      wr_en = 0;
      rd_en = 0;
    end
  endtask
  
  always
    #1 clk = ~clk;
  
  initial begin
    $display("  T\taddrWr\tadddRd\tdin\t\trd_en\twr_en\tclk\treset\tdout");
    $monitor("%3d\t%h\t%h\t%h\t%h\t%h\t%h\t%h\t%h",
             $time, addr_wr, addr_rd, data_in, rd_en, wr_en, clk, reset, data_out);
  end
  
  buffer_memory dut 
  (.addr_wr(addr_wr), .addr_rd(addr_rd), .data_in(data_in),
                     .rd_en(rd_en), .wr_en(wr_en), .clk(clk), .reset(reset),
                     .data_out(data_out));
  
endmodule