data/full_repos/permissive/407433468/2010-PRJ0_BASE_1/rtl/CC_AND.v
data/verilator_xmls/a6e7feb9-f2df-432b-a280-74e53831ac82.xml
module CC_AND (



	CC_AND_OutBUS,
	


	CC_AND_dataA_InBUS,
	CC_AND_dataB_InBUS
);



parameter NUMBER_DATAWIDTH = 8;




output 	[NUMBER_DATAWIDTH-1:0] CC_AND_OutBUS;

input 	[NUMBER_DATAWIDTH-1:0] CC_AND_dataA_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_AND_dataB_InBUS;








and(CC_AND_OutBUS, CC_AND_dataA_InBUS, CC_AND_dataB_InBUS);

endmodule
module CC_AND (



	CC_AND_OutBUS,
	


	CC_AND_dataA_InBUS,
	CC_AND_dataB_InBUS
);




parameter NUMBER_DATAWIDTH = 8;




output 	[NUMBER_DATAWIDTH-1:0] CC_AND_OutBUS;

input 	[NUMBER_DATAWIDTH-1:0] CC_AND_dataA_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_AND_dataB_InBUS;








and(CC_AND_OutBUS, CC_AND_dataA_InBUS, CC_AND_dataB_InBUS);

endmodule