data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_dtoh_sh.v
data/verilator_xmls/fe6f9cbf-4aae-482a-9b59-5a73692b79d3.xml
module ct_fcnvt_dtoh_sh(
  dtos_sh_cnt,
  dtos_sh_f_v,
  dtos_sh_f_x,
  dtos_sh_src
);


input   [10:0]  dtos_sh_cnt; 
input   [51:0]  dtos_sh_src; 
output  [10:0]  dtos_sh_f_v; 
output  [53:0]  dtos_sh_f_x; 


reg     [10:0]  dtos_sh_f_v; 
reg     [53:0]  dtos_sh_f_x; 


wire    [10:0]  dtos_sh_cnt; 
wire    [51:0]  dtos_sh_src; 




always @( dtos_sh_cnt[10:0]
       or dtos_sh_src[51:0])
begin
case(dtos_sh_cnt[10:0])
  11'h3f0: begin
  dtos_sh_f_v[10:0] = {2'b1,dtos_sh_src[51:43]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[42:0],11'b0};
  end
  11'h3ef: begin
  dtos_sh_f_v[10:0] = {3'b1,dtos_sh_src[51:44]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[43:0],10'b0};
  end
  11'h3ee: begin
  dtos_sh_f_v[10:0] = {4'b1,dtos_sh_src[51:45]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[44:0],9'b0};
  end
  11'h3ed: begin
  dtos_sh_f_v[10:0] = {5'b1,dtos_sh_src[51:46]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[45:0],8'b0};
  end
  11'h3ec: begin
  dtos_sh_f_v[10:0] = {6'b1,dtos_sh_src[51:47]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[46:0],7'b0};
  end
  11'h3eb: begin
  dtos_sh_f_v[10:0] = {7'b1,dtos_sh_src[51:48]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[47:0],6'b0};
  end
  11'h3ea: begin
  dtos_sh_f_v[10:0] = {8'b1,dtos_sh_src[51:49]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[48:0],5'b0};
  end
  11'h3e9: begin
  dtos_sh_f_v[10:0] = {9'b1,dtos_sh_src[51:50]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[49:0],4'b0};
  end
  11'h3e8: begin
  dtos_sh_f_v[10:0] = {10'b1,dtos_sh_src[51]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[50:0],3'b0};
  end
  11'h3e7: begin
  dtos_sh_f_v[10:0] = {11'b1};
  dtos_sh_f_x[53:0] = {dtos_sh_src[51:0],2'b0};
  end
  11'h3e6: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {1'b1,dtos_sh_src[51:0],1'b0};
  end
  11'h3e5: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {2'b1,dtos_sh_src[51:0]};
  end
  default: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {3'b1,51'b0};
  end
endcase

end



endmodule
module ct_fcnvt_dtoh_sh(
  dtos_sh_cnt,
  dtos_sh_f_v,
  dtos_sh_f_x,
  dtos_sh_src
);



input   [10:0]  dtos_sh_cnt; 
input   [51:0]  dtos_sh_src; 
output  [10:0]  dtos_sh_f_v; 
output  [53:0]  dtos_sh_f_x; 


reg     [10:0]  dtos_sh_f_v; 
reg     [53:0]  dtos_sh_f_x; 


wire    [10:0]  dtos_sh_cnt; 
wire    [51:0]  dtos_sh_src; 




always @( dtos_sh_cnt[10:0]
       or dtos_sh_src[51:0])
begin
case(dtos_sh_cnt[10:0])
  11'h3f0: begin
  dtos_sh_f_v[10:0] = {2'b1,dtos_sh_src[51:43]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[42:0],11'b0};
  end
  11'h3ef: begin
  dtos_sh_f_v[10:0] = {3'b1,dtos_sh_src[51:44]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[43:0],10'b0};
  end
  11'h3ee: begin
  dtos_sh_f_v[10:0] = {4'b1,dtos_sh_src[51:45]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[44:0],9'b0};
  end
  11'h3ed: begin
  dtos_sh_f_v[10:0] = {5'b1,dtos_sh_src[51:46]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[45:0],8'b0};
  end
  11'h3ec: begin
  dtos_sh_f_v[10:0] = {6'b1,dtos_sh_src[51:47]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[46:0],7'b0};
  end
  11'h3eb: begin
  dtos_sh_f_v[10:0] = {7'b1,dtos_sh_src[51:48]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[47:0],6'b0};
  end
  11'h3ea: begin
  dtos_sh_f_v[10:0] = {8'b1,dtos_sh_src[51:49]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[48:0],5'b0};
  end
  11'h3e9: begin
  dtos_sh_f_v[10:0] = {9'b1,dtos_sh_src[51:50]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[49:0],4'b0};
  end
  11'h3e8: begin
  dtos_sh_f_v[10:0] = {10'b1,dtos_sh_src[51]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[50:0],3'b0};
  end
  11'h3e7: begin
  dtos_sh_f_v[10:0] = {11'b1};
  dtos_sh_f_x[53:0] = {dtos_sh_src[51:0],2'b0};
  end
  11'h3e6: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {1'b1,dtos_sh_src[51:0],1'b0};
  end
  11'h3e5: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {2'b1,dtos_sh_src[51:0]};
  end
  default: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {3'b1,51'b0};
  end
endcase

end



endmodule