data/full_repos/permissive/520695407/sim/tb-display-controller.sv
1: b'%Error: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:5: Unsupported: event data types\n    input event start,\n          ^~~~~\n%Error: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:6: Unsupported: event data types\n    input event done\n          ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:16: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk <= ~clk;  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:33: Unsupported: wait statements\n    wait (start.triggered);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:36: Unsupported: Ignoring delay on this delayed statement.\n    #38400;\n    ^\n%Error: data/full_repos/permissive/520695407/sim/tb-display-controller.sv:37: syntax error, unexpected ->\n    ->done;\n    ^~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dspl_ctrl (
    input event start,
    input event done
);
  logic clk = 0,
	rst = 0;
  logic [11:0] din_top, din_btm;
  logic [9:0] r_addr;
  logic sclk, latch, blank;
  logic [2:0] dout_top, dout_btm;
  logic [3:0] row_sel;

  always #5 clk <= ~clk;

  dspl_ctrl dut(
    .clk(clk),
    .rst(rst),
    .din_top(din_top),
    .din_btm(din_btm),
    .r_addr(r_addr),
    .sclk(sclk),
    .latch(latch),
    .blank(blank),
    .dout_top(dout_top),
    .dout_btm(dout_btm),
    .row_sel(row_sel)
  );

  initial begin
    wait (start.triggered);
    $display("=== DISPLAY CONTROLLER TEST STARTED ===");
    $display("=== DISPLAY CONTROLLER TEST FINISHED ===");
    #38400;
    ->done;
  end
endmodule
module tb_dspl_ctrl (
    input event start,
    input event done
);

  logic clk = 0,
	rst = 0;
  logic [11:0] din_top, din_btm;
  logic [9:0] r_addr;
  logic sclk, latch, blank;
  logic [2:0] dout_top, dout_btm;
  logic [3:0] row_sel;

  always #5 clk <= ~clk;

  dspl_ctrl dut(
    .clk(clk),
    .rst(rst),
    .din_top(din_top),
    .din_btm(din_btm),
    .r_addr(r_addr),
    .sclk(sclk),
    .latch(latch),
    .blank(blank),
    .dout_top(dout_top),
    .dout_btm(dout_btm),
    .row_sel(row_sel)
  );

  initial begin
    wait (start.triggered);
    $display("=== DISPLAY CONTROLLER TEST STARTED ===");
    $display("=== DISPLAY CONTROLLER TEST FINISHED ===");
    #38400;
    ->done;
  end
endmodule