data/full_repos/permissive/471677942/verilog/rtl/comparator.v
data/verilator_xmls/393ae5ef-c623-45ad-a7d2-8e3dd581d5b5.xml
module comparator(
`ifdef USE_POWER_PINS
    inout VDD,
    inout GND,
`endif
    input Vn,
    input Vp,
    input CLK,
    input CLKBAR,
    output Outn,
    output Outp
);

    
endmodule
module comparator(
`ifdef USE_POWER_PINS
    inout VDD,
    inout GND,
`endif
    input Vn,
    input Vp,
    input CLK,
    input CLKBAR,
    output Outn,
    output Outp
);


    
endmodule