data/full_repos/permissive/459233267/cpu.v
1: b'%Error: data/full_repos/permissive/459233267/cpu.v:3: Cannot find include file: eprom.v\n`include "eprom.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v.v\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v.sv\n             eprom.v\n             eprom.v.v\n             eprom.v.sv\n             obj_dir/eprom.v\n             obj_dir/eprom.v.v\n             obj_dir/eprom.v.sv\n%Error: data/full_repos/permissive/459233267/cpu.v:4: Cannot find include file: sram.v\n`include "sram.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:175: Unsupported: Ignoring delay on this delayed statement.\n    #3 rst = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:180: Unsupported: Ignoring delay on this delayed statement.\n    #159 buff_in = 8\'d9; \n    ^\n%Error: data/full_repos/permissive/459233267/cpu.v:184: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/459233267/cpu.v:185: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,tb);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module cpu(
    input clk, rst,
    inout [7:0] data_bus,
    output [4:0] adr_bus,
    input [7:0] buff_in,
    output reg [7:0] buff_out,
    output reg wr,rd
);

localparam s1 = 3'd0;
localparam s2 = 3'd1;
localparam s3 = 3'd2;
localparam s4 = 3'd3;
localparam s5 = 3'd4;
localparam s6 = 3'd5;
localparam s7 = 3'd6;
localparam s8 = 3'd7;

reg [7:0] acc;
reg [7:0] dr;
reg [4:0] ar;
reg [3:0] pc;
reg [1:0] ir;

assign adr_bus = ar;
assign data_bus = (wr & !rd) ? dr : 'hz;

reg [2:0] st;
reg [2:0] st_nxt;

always @(st) begin
    case(st)
        s1:
            begin
                ar[3:0] <= pc;
                ar[4] <= 1'b1;
                wr <= 1'b0;
            end
        s2:
            begin
                rd <= 1'b1;
                pc <= pc + 1;
            end
        s3:
            begin
                dr <= data_bus;
            end
        s4:
            begin
                rd <= 1'b0;
                ir <= dr[7:6];
            end
        s5:
            begin
                if(ir == 2'b00)
                    acc <= buff_in;
                else if(ir == 2'b01)
                    buff_out <= acc;
                else
                    begin
                        ar[4] <= 1'b0;
                        ar[3:0] <= dr[5:2];
                    end
            end
        s6:
            begin
                if(ir == 2'b10)
                    dr <= acc;
                else if(ir == 2'b11)
                    rd <= 1'b1;
            end
        s7:
            begin
                if(ir == 2'b10)
                    wr <= 1'b1;
                else if(ir == 2'b11)
                    dr <= data_bus;
            end
        s8:
            begin
                if(ir == 2'b11)
                    acc <= dr;
            end
    endcase    
end

always @* begin
    if(st != s8)
        st_nxt = st + 1;
    else
        st_nxt = s1;
end

always @(posedge clk or posedge rst) begin
    if(rst)
        begin
            st <= s1;
            pc <= 4'd0;
            ir <= 2'd0;
            ar <= 5'd0;
            dr <= 8'd0;
            rd <= 1'd0;
        end
    else
        st <= st_nxt;
end

endmodule
module cpu(
    input clk, rst,
    inout [7:0] data_bus,
    output [4:0] adr_bus,
    input [7:0] buff_in,
    output reg [7:0] buff_out,
    output reg wr,rd
);


localparam s1 = 3'd0;
localparam s2 = 3'd1;
localparam s3 = 3'd2;
localparam s4 = 3'd3;
localparam s5 = 3'd4;
localparam s6 = 3'd5;
localparam s7 = 3'd6;
localparam s8 = 3'd7;

reg [7:0] acc;
reg [7:0] dr;
reg [4:0] ar;
reg [3:0] pc;
reg [1:0] ir;

assign adr_bus = ar;
assign data_bus = (wr & !rd) ? dr : 'hz;

reg [2:0] st;
reg [2:0] st_nxt;

always @(st) begin
    case(st)
        s1:
            begin
                ar[3:0] <= pc;
                ar[4] <= 1'b1;
                wr <= 1'b0;
            end
        s2:
            begin
                rd <= 1'b1;
                pc <= pc + 1;
            end
        s3:
            begin
                dr <= data_bus;
            end
        s4:
            begin
                rd <= 1'b0;
                ir <= dr[7:6];
            end
        s5:
            begin
                if(ir == 2'b00)
                    acc <= buff_in;
                else if(ir == 2'b01)
                    buff_out <= acc;
                else
                    begin
                        ar[4] <= 1'b0;
                        ar[3:0] <= dr[5:2];
                    end
            end
        s6:
            begin
                if(ir == 2'b10)
                    dr <= acc;
                else if(ir == 2'b11)
                    rd <= 1'b1;
            end
        s7:
            begin
                if(ir == 2'b10)
                    wr <= 1'b1;
                else if(ir == 2'b11)
                    dr <= data_bus;
            end
        s8:
            begin
                if(ir == 2'b11)
                    acc <= dr;
            end
    endcase    
end

always @* begin
    if(st != s8)
        st_nxt = st + 1;
    else
        st_nxt = s1;
end

always @(posedge clk or posedge rst) begin
    if(rst)
        begin
            st <= s1;
            pc <= 4'd0;
            ir <= 2'd0;
            ar <= 5'd0;
            dr <= 8'd0;
            rd <= 1'd0;
        end
    else
        st <= st_nxt;
end

endmodule