data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v
1: b'%Error: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:20: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,tb_CONTROL_RW_FLOW);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:21: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("my.vcd");\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #4\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_CONTROL_RW_FLOW.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_CONTROL_RW_FLOW;

	reg valid_cmd;
	reg rw;
	reg active;
	reg mode;
	reg tx_done;
	reg reset;
	reg clk;
	wire ac_mem;
	wire rw_mem;
	wire p_load;
	wire tx_dat;
	wire busy;

	CONTROL_RW_FLOW DUT (valid_cmd, rw, active, mode, tx_done, reset, clk, ac_mem, rw_mem, p_load, tx_dat, busy);

	initial begin

		$dumpvars(0,tb_CONTROL_RW_FLOW);
    	$dumpfile("my.vcd");

		clk = 0;
		forever
			#5 clk = ~clk;

	end

	initial begin
		
		#5

		reset = 1;
		#5
		display;

		reset = 0;
		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#4
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 1;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 1;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;



		#300
		$finish;


	end

	task display;
		$display("r=%0b, clk=%0b, valid=%0b, rw=%0b, active=%0b, mode=%0b, tx_done=%0b, ac_mem=%0b, rw_mem=%0b, p_load=%0b, tx_dat=%0b, busy=%0b",
             reset, clk, valid_cmd, rw, active, mode, tx_done, ac_mem, rw_mem, p_load, tx_dat, busy);
  	endtask

endmodule
module tb_CONTROL_RW_FLOW;


	reg valid_cmd;
	reg rw;
	reg active;
	reg mode;
	reg tx_done;
	reg reset;
	reg clk;
	wire ac_mem;
	wire rw_mem;
	wire p_load;
	wire tx_dat;
	wire busy;

	CONTROL_RW_FLOW DUT (valid_cmd, rw, active, mode, tx_done, reset, clk, ac_mem, rw_mem, p_load, tx_dat, busy);

	initial begin

		$dumpvars(0,tb_CONTROL_RW_FLOW);
    	$dumpfile("my.vcd");

		clk = 0;
		forever
			#5 clk = ~clk;

	end

	initial begin
		
		#5

		reset = 1;
		#5
		display;

		reset = 0;
		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#4
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 0;
		#5
		display;

		valid_cmd = 1;
		rw = 0;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 1;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;

		valid_cmd = 1;
		rw = 1;
		active = 1;
		mode = 1;
		tx_done = 1;
		#5
		display;



		#300
		$finish;


	end

	task display;
		$display("r=%0b, clk=%0b, valid=%0b, rw=%0b, active=%0b, mode=%0b, tx_done=%0b, ac_mem=%0b, rw_mem=%0b, p_load=%0b, tx_dat=%0b, busy=%0b",
             reset, clk, valid_cmd, rw, active, mode, tx_done, ac_mem, rw_mem, p_load, tx_dat, busy);
  	endtask

endmodule