data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v
1: b'%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:1: Cannot find include file: ./global.vh\n`include "./global.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.sv\n             ./global.vh\n             ./global.vh.v\n             ./global.vh.sv\n             obj_dir/./global.vh\n             obj_dir/./global.vh.v\n             obj_dir/./global.vh.sv\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:38: Define or directive not defined: \'`OPEN_TIME\'\n    counter c_door(clk1hz, cd_start, `OPEN_TIME, cd_done);\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:39: Define or directive not defined: \'`MOVE_TIME\'\n    counter c_elev(clk1hz, ce_start, `MOVE_TIME, ce_done);\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:49: Define or directive not defined: \'`F_N\'\n                    curr_pos <= curr_pos == `F_N - 1 ? `F_N - 1 : curr_pos + 1\'b1;   \n                                            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:49: Define or directive not defined: \'`F_N\'\n                    curr_pos <= curr_pos == `F_N - 1 ? `F_N - 1 : curr_pos + 1\'b1;   \n                                                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:119: Define or directive not defined: \'`RS_UP\'\n                {`RS_UP, `DS_CLOSE};\n                 ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:119: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_UP, `DS_CLOSE};\n                       ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:119: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_UP, `DS_CLOSE};\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:122: Define or directive not defined: \'`RS_UP\'\n                {`RS_UP, `DS_OPEN};\n                 ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:122: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_UP, `DS_OPEN};\n                       ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:122: Define or directive not defined: \'`DS_OPEN\'\n                {`RS_UP, `DS_OPEN};\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:125: Define or directive not defined: \'`RS_UP\'\n                {`RS_UP, `DS_CLOSE};\n                 ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:125: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_UP, `DS_CLOSE};\n                       ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:125: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_UP, `DS_CLOSE};\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:128: Define or directive not defined: \'`RS_UP\'\n                {`RS_UP, `DS_CLOSE};\n                 ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:128: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_UP, `DS_CLOSE};\n                       ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:128: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_UP, `DS_CLOSE};\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:131: Define or directive not defined: \'`RS_DOWN\'\n                {`RS_DOWN, `DS_OPEN};\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:131: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_DOWN, `DS_OPEN};\n                         ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:131: Define or directive not defined: \'`DS_OPEN\'\n                {`RS_DOWN, `DS_OPEN};\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:134: Define or directive not defined: \'`RS_DOWN\'\n                {`RS_DOWN, `DS_CLOSE};\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:134: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_DOWN, `DS_CLOSE};\n                         ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:134: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_DOWN, `DS_CLOSE};\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:137: Define or directive not defined: \'`RS_DOWN\'\n                {`RS_DOWN, `DS_CLOSE};\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:137: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_DOWN, `DS_CLOSE};\n                         ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:137: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_DOWN, `DS_CLOSE};\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:140: Define or directive not defined: \'`RS_UP\'\n                {`RS_UP, `DS_CLOSE};\n                 ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:140: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                {`RS_UP, `DS_CLOSE};\n                       ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/control.v:140: Define or directive not defined: \'`DS_CLOSE\'\n                {`RS_UP, `DS_CLOSE};\n                         ^~~~~~~~~\n%Error: Exiting due to 29 error(s)\n'
module control (
    input clk380hz,
    input clk10hz,
    input clk1hz,
    input rst,
    input      [2:0] req,
    output     [7:0] curr_floor,
    output reg [3:0] running_state,
    output reg [3:0] door_state,
    output     [3:0] state
);


    parameter INIT       = 4'd0,
              UP         = 4'd1,
              DOWN       = 4'd2,
              UP_OPEN    = 4'd3,
              UP_CLOSE   = 4'd4,
              DOWN_OPEN  = 4'd5,
              DOWN_CLOSE = 4'd6;

    reg [3:0] curr = INIT, next;
    reg [7:0] curr_pos = 0;
    assign curr_floor = curr_pos;
    assign state = curr;


    wire go_up = req[2];
    wire go_down = req[1];
    wire open_door = req[0];


    reg cd_start = 0;
    wire cd_done;
    reg ce_start = 0;
    wire ce_done;
    counter c_door(clk1hz, cd_start, `OPEN_TIME, cd_done);
    counter c_elev(clk1hz, ce_start, `MOVE_TIME, ce_done);


    always @(posedge clk10hz or posedge rst) begin
        if(rst == 1) begin
            {ce_start, cd_start, curr_pos} <= 0;
        end
        else case (curr)
            UP: begin
                if(ce_done == 1) begin
                    curr_pos <= curr_pos == `F_N - 1 ? `F_N - 1 : curr_pos + 1'b1;
                    ce_start <= 0;
                end
                else ce_start <= 1;
            end
            DOWN: begin
                if(ce_done == 1) begin
                    curr_pos <= curr_pos == 0 ? 0 : curr_pos - 1'b1;
                    ce_start <= 0;
                end
                else ce_start <= 1;
            end
            UP_OPEN: begin
                cd_start <= ~cd_done;
            end
            DOWN_OPEN: begin
                cd_start <= ~cd_done;
            end
            default: begin
                ce_start <= 0;
                cd_start <= 0;
            end
        endcase     
    end



    always @(posedge clk10hz or posedge rst) begin
        curr <= rst == 1 ? INIT : next;
    end


    always @(*) begin
        case (curr)
            INIT: begin
                next = req > 0 ? UP_CLOSE : INIT;
            end
            UP_OPEN: begin
                next = cd_done == 1 ? UP_CLOSE : UP_OPEN;
            end
            UP_CLOSE: begin
                if(open_door == 1)      next = UP_OPEN;
                else if(go_up == 1)     next = UP;
                else if(go_down == 1)   next = DOWN;
                else                    next = UP_CLOSE;
            end
            UP: begin
                next = ce_done == 1 ? UP_CLOSE : UP;
            end
            DOWN_OPEN: begin
                next = cd_done == 1 ? DOWN_CLOSE : DOWN_OPEN;
            end
            DOWN_CLOSE: begin
                if(open_door == 1)      next = DOWN_OPEN;
                else if(go_down == 1)   next = DOWN;
                else if(go_up == 1)     next = UP;
                else                    next = DOWN_CLOSE;
            end
            DOWN: begin
                next = ce_done == 1 ? DOWN_CLOSE : DOWN;
            end
            default: next = INIT;
        endcase
    end


    always @(*) begin
        case(curr)
            INIT: 
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            UP_OPEN:
                {running_state, door_state} = 
                {`RS_UP, `DS_OPEN};
            UP_CLOSE:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            UP:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            DOWN_OPEN:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_OPEN};
            DOWN_CLOSE:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_CLOSE};
            DOWN:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_CLOSE};
            default:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
        endcase
    end

endmodule
module control (
    input clk380hz,
    input clk10hz,
    input clk1hz,
    input rst,
    input      [2:0] req,
    output     [7:0] curr_floor,
    output reg [3:0] running_state,
    output reg [3:0] door_state,
    output     [3:0] state
);



    parameter INIT       = 4'd0,
              UP         = 4'd1,
              DOWN       = 4'd2,
              UP_OPEN    = 4'd3,
              UP_CLOSE   = 4'd4,
              DOWN_OPEN  = 4'd5,
              DOWN_CLOSE = 4'd6;

    reg [3:0] curr = INIT, next;
    reg [7:0] curr_pos = 0;
    assign curr_floor = curr_pos;
    assign state = curr;


    wire go_up = req[2];
    wire go_down = req[1];
    wire open_door = req[0];


    reg cd_start = 0;
    wire cd_done;
    reg ce_start = 0;
    wire ce_done;
    counter c_door(clk1hz, cd_start, `OPEN_TIME, cd_done);
    counter c_elev(clk1hz, ce_start, `MOVE_TIME, ce_done);


    always @(posedge clk10hz or posedge rst) begin
        if(rst == 1) begin
            {ce_start, cd_start, curr_pos} <= 0;
        end
        else case (curr)
            UP: begin
                if(ce_done == 1) begin
                    curr_pos <= curr_pos == `F_N - 1 ? `F_N - 1 : curr_pos + 1'b1;
                    ce_start <= 0;
                end
                else ce_start <= 1;
            end
            DOWN: begin
                if(ce_done == 1) begin
                    curr_pos <= curr_pos == 0 ? 0 : curr_pos - 1'b1;
                    ce_start <= 0;
                end
                else ce_start <= 1;
            end
            UP_OPEN: begin
                cd_start <= ~cd_done;
            end
            DOWN_OPEN: begin
                cd_start <= ~cd_done;
            end
            default: begin
                ce_start <= 0;
                cd_start <= 0;
            end
        endcase     
    end



    always @(posedge clk10hz or posedge rst) begin
        curr <= rst == 1 ? INIT : next;
    end


    always @(*) begin
        case (curr)
            INIT: begin
                next = req > 0 ? UP_CLOSE : INIT;
            end
            UP_OPEN: begin
                next = cd_done == 1 ? UP_CLOSE : UP_OPEN;
            end
            UP_CLOSE: begin
                if(open_door == 1)      next = UP_OPEN;
                else if(go_up == 1)     next = UP;
                else if(go_down == 1)   next = DOWN;
                else                    next = UP_CLOSE;
            end
            UP: begin
                next = ce_done == 1 ? UP_CLOSE : UP;
            end
            DOWN_OPEN: begin
                next = cd_done == 1 ? DOWN_CLOSE : DOWN_OPEN;
            end
            DOWN_CLOSE: begin
                if(open_door == 1)      next = DOWN_OPEN;
                else if(go_down == 1)   next = DOWN;
                else if(go_up == 1)     next = UP;
                else                    next = DOWN_CLOSE;
            end
            DOWN: begin
                next = ce_done == 1 ? DOWN_CLOSE : DOWN;
            end
            default: next = INIT;
        endcase
    end


    always @(*) begin
        case(curr)
            INIT: 
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            UP_OPEN:
                {running_state, door_state} = 
                {`RS_UP, `DS_OPEN};
            UP_CLOSE:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            UP:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
            DOWN_OPEN:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_OPEN};
            DOWN_CLOSE:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_CLOSE};
            DOWN:
                {running_state, door_state} = 
                {`RS_DOWN, `DS_CLOSE};
            default:
                {running_state, door_state} = 
                {`RS_UP, `DS_CLOSE};
        endcase
    end

endmodule