data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v
1: b"%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:139: syntax error, unexpected '@'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:141: syntax error, unexpected '@'\n    repeat(3) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:143: syntax error, unexpected '@'\n    repeat(5) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:151: syntax error, unexpected '@'\n    @(negedge sw_rst);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:153: syntax error, unexpected '@'\n    repeat(5) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:165: Unsupported or unknown PLI call: $urandom_range\n    send_data($urandom_range(0,255),\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:166: Unsupported or unknown PLI call: $urandom_range\n              $urandom_range(0,255),\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:167: Unsupported or unknown PLI call: $urandom_range\n              $urandom_range(0,255),\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:168: Unsupported or unknown PLI call: $urandom_range\n              $urandom_range(0,255),\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:169: Unsupported or unknown PLI call: $urandom_range\n              $urandom_range(0,10));  \n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:192: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:194: syntax error, unexpected '@'\n    while(~op_rdy) @(posedge clk);  \n                   ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:198: syntax error, unexpected '@'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:200: syntax error, unexpected '@'\n    repeat(break_time) @(posedge clk);  \n                       ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_test.v:253: Unsupported or unknown PLI call: $urandom\n           rand_nr <= $urandom ;\n                      ^~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module comp_mult_test;

localparam PERIOD  = 5;
localparam DWIDTH  = 8;

wire                         clk          ;
wire                         rst_n        ;
reg                          sw_rst       ;
reg                          op_val       ;
wire                         op_rdy       ;
reg  [      2*2*DWIDTH -1:0] op_data      ;





wire                         res_val_1    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_1   ;

wire                         res_val_2    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_2   ;

wire                         res_val_4    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_4   ;

wire                         res_rdy_all;
                                        
reg    [            32 -1:0] rand_nr      ;
wire                         rand_f       ;
                                          
integer                      idx          ; 


wire test_rdy = 0;


clk_rst_tb #(
.PERIOD (PERIOD)
) i_clk_rst_tb (
.clk   (clk  ),
.rst_n (rst_n)
);


assign res_rdy_all = res_val_1 & res_val_2 & res_val_4;


comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (4       )
) DUT_comp_mult_wrapper_4 (
.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_4  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_4 )
); 

comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (2       )
) DUT_comp_mult_wrapper_2 (

.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_2  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_2 )
); 

comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (1       )
) DUT_comp_mult_wrapper_1 (

.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_1  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_1 )
); 


comp_mult_data_checker #(
.DWIDTH (DWIDTH)
) i_comp_mult_data_checker (                     
.clk         (clk        ),
.rst_n       (rst_n      ),
.sw_rst      (sw_rst     ),
.op_val      (op_val     ),
.op_rdy      (op_rdy     ),
.op_data     (op_data    ),
.sample      (res_rdy_all),
.res_data_4  (res_data_4 ),
.res_data_2  (res_data_2 ),
.res_data_1  (res_data_1 )
); 














initial begin 
    idx = 0;
    sw_rst = 1'b0;
    @(posedge rst_n);
    @(posedge clk);
    repeat(3) @(posedge clk);
    sw_rst = 1'b1; 
    repeat(5) @(posedge clk);
    sw_rst = 1'b0;
end 

initial begin 
    op_val  = 1'b0;
    op_data =  'b0;

    @(negedge sw_rst);
    
    repeat(5) @(posedge clk);
    send_data(8'd2,8'd3,8'd4,8'd2,1);
    send_data(8'd3,8'd3,8'd4,8'd2,0);
    send_data(8'd0,8'd0,8'd0,8'd0,0);
    
    send_data(8'd255,8'd255,8'd255,8'd255,0);
    send_data(8'd127,8'd127,8'd127,8'd127,0);
    send_data(8'd129,8'd129,8'd129,8'd129,0);
    send_data(8'd100,8'd100,8'd100,8'd100,0);
    send_data(8'd100,8'd101,8'd102,8'd103,0);
    
    repeat(1000)
    send_data($urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,10));  
     
    send_data(8'd128,8'd128,8'd128,8'd128,0);

    $display("DONE");
    $stop;
      
end 



task send_data;

input [8 -1:0] t_x1      ;  
input [8 -1:0] t_y1      ;
input [8 -1:0] t_x2      ;
input [8 -1:0] t_y2      ;
input [8 -1:0] break_time;

begin 

    op_val = 1'b1;
    op_data = {t_x1, t_y1, t_x2, t_y2};
    @(posedge clk);
    
    while(~op_rdy) @(posedge clk);
    if(break_time > 0) begin  
        op_val = 1'b0;
        op_data = 'bx;
        @(posedge clk);
    end 
    repeat(break_time) @(posedge clk);

end 
endtask



vld_rdy_checker #(
.DATA_WIDTH       (2*2*DWIDTH)
) i_vld_rdy_checker_in (     
.clk              (clk       ),
.rst_n            (rst_n     ),
.valid            (op_val    ),               
.ready            (op_rdy    ),               
.data             (op_data   )
);



vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_4 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_4   ),               
.ready            (res_rdy_all ),               
.data             (res_data_4  )
);


vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_2 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_2   ),               
.ready            (res_rdy_all ),               
.data             (res_data_2  )
);


vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_1 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_1   ),               
.ready            (res_rdy_all ),               
.data             (res_data_1  )
);

always @(posedge clk)
if(~rst_n) rand_nr <= 32'd0    ; else 
           rand_nr <= $urandom ;

assign rand_f = &rand_nr[1:0];


endmodule
module comp_mult_test;


localparam PERIOD  = 5;
localparam DWIDTH  = 8;

wire                         clk          ;
wire                         rst_n        ;
reg                          sw_rst       ;
reg                          op_val       ;
wire                         op_rdy       ;
reg  [      2*2*DWIDTH -1:0] op_data      ;





wire                         res_val_1    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_1   ;

wire                         res_val_2    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_2   ;

wire                         res_val_4    ;

wire [2*2*(DWIDTH + 1) -1:0] res_data_4   ;

wire                         res_rdy_all;
                                        
reg    [            32 -1:0] rand_nr      ;
wire                         rand_f       ;
                                          
integer                      idx          ; 


wire test_rdy = 0;


clk_rst_tb #(
.PERIOD (PERIOD)
) i_clk_rst_tb (
.clk   (clk  ),
.rst_n (rst_n)
);


assign res_rdy_all = res_val_1 & res_val_2 & res_val_4;


comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (4       )
) DUT_comp_mult_wrapper_4 (
.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_4  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_4 )
); 

comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (2       )
) DUT_comp_mult_wrapper_2 (

.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_2  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_2 )
); 

comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (1       )
) DUT_comp_mult_wrapper_1 (

.clk      (clk        ),
.rst_n    (rst_n      ),
.sw_rst   (sw_rst     ),
.op_val   (op_val     ),
.op_rdy   (op_rdy     ),
.op_data  (op_data    ),
.res_val  (res_val_1  ),
.res_rdy  (res_rdy_all),
.res_data (res_data_1 )
); 


comp_mult_data_checker #(
.DWIDTH (DWIDTH)
) i_comp_mult_data_checker (                     
.clk         (clk        ),
.rst_n       (rst_n      ),
.sw_rst      (sw_rst     ),
.op_val      (op_val     ),
.op_rdy      (op_rdy     ),
.op_data     (op_data    ),
.sample      (res_rdy_all),
.res_data_4  (res_data_4 ),
.res_data_2  (res_data_2 ),
.res_data_1  (res_data_1 )
); 














initial begin 
    idx = 0;
    sw_rst = 1'b0;
    @(posedge rst_n);
    @(posedge clk);
    repeat(3) @(posedge clk);
    sw_rst = 1'b1; 
    repeat(5) @(posedge clk);
    sw_rst = 1'b0;
end 

initial begin 
    op_val  = 1'b0;
    op_data =  'b0;

    @(negedge sw_rst);
    
    repeat(5) @(posedge clk);
    send_data(8'd2,8'd3,8'd4,8'd2,1);
    send_data(8'd3,8'd3,8'd4,8'd2,0);
    send_data(8'd0,8'd0,8'd0,8'd0,0);
    
    send_data(8'd255,8'd255,8'd255,8'd255,0);
    send_data(8'd127,8'd127,8'd127,8'd127,0);
    send_data(8'd129,8'd129,8'd129,8'd129,0);
    send_data(8'd100,8'd100,8'd100,8'd100,0);
    send_data(8'd100,8'd101,8'd102,8'd103,0);
    
    repeat(1000)
    send_data($urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,255),
              $urandom_range(0,10));  
     
    send_data(8'd128,8'd128,8'd128,8'd128,0);

    $display("DONE");
    $stop;
      
end 



task send_data;

input [8 -1:0] t_x1      ;  
input [8 -1:0] t_y1      ;
input [8 -1:0] t_x2      ;
input [8 -1:0] t_y2      ;
input [8 -1:0] break_time;

begin 

    op_val = 1'b1;
    op_data = {t_x1, t_y1, t_x2, t_y2};
    @(posedge clk);
    
    while(~op_rdy) @(posedge clk);
    if(break_time > 0) begin  
        op_val = 1'b0;
        op_data = 'bx;
        @(posedge clk);
    end 
    repeat(break_time) @(posedge clk);

end 
endtask



vld_rdy_checker #(
.DATA_WIDTH       (2*2*DWIDTH)
) i_vld_rdy_checker_in (     
.clk              (clk       ),
.rst_n            (rst_n     ),
.valid            (op_val    ),               
.ready            (op_rdy    ),               
.data             (op_data   )
);



vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_4 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_4   ),               
.ready            (res_rdy_all ),               
.data             (res_data_4  )
);


vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_2 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_2   ),               
.ready            (res_rdy_all ),               
.data             (res_data_2  )
);


vld_rdy_checker #(
.DATA_WIDTH       (2*2*(DWIDTH + 1))
) i_vld_rdy_checker_out_1 (     
.clk              (clk         ),
.rst_n            (rst_n       ),
.valid            (res_val_1   ),               
.ready            (res_rdy_all ),               
.data             (res_data_1  )
);

always @(posedge clk)
if(~rst_n) rand_nr <= 32'd0    ; else 
           rand_nr <= $urandom ;

assign rand_f = &rand_nr[1:0];


endmodule