data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/PCBranch.v
data/verilator_xmls/18611244-d5cc-49b4-95c9-def909942758.xml
module PCBranch(
    input [31:0] SImm,
    input [31:0] PCp1,
    output reg [31:0] BranchOut
    );
    always @(SImm or PCp1) begin
        BranchOut <= SImm + PCp1;
    end
endmodule
module PCBranch(
    input [31:0] SImm,
    input [31:0] PCp1,
    output reg [31:0] BranchOut
    );

    always @(SImm or PCp1) begin
        BranchOut <= SImm + PCp1;
    end
endmodule