data/full_repos/permissive/43974493/src/snes_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43974493/src/snes_controller.v:48: Operator EQ expects 32 or 27 bits on the RHS, but RHS\'s VARREF \'counter_60hz\' generates 21 bits.\n                                                                            : ... In instance snes_controller\n      if (COUNTER_60HZ_MAX - 1 == counter_60hz) begin\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module snes_controller
  (
   input                              clk,
   input                              serial_in,
   output reg                         data_clk,
   output reg                         data_latch, 
   output reg [SNES_BUTTON_COUNT-1:0] button_state
   );

   initial begin
      data_clk = 0;
      data_latch = 0;
      button_state = 0;
   end

   localparam SNES_BUTTON_COUNT = 12;

   localparam COUNTER_60HZ_MAX = 100000000 / 60;
   localparam COUNTER_12US_MAX = 1200;

   localparam STATE_WAIT = 0;
   localparam STATE_LATCH = 1;
   localparam STATE_DATA = 2;

   reg [1:0]                           state = STATE_WAIT;
   reg [$clog2(COUNTER_60HZ_MAX)-1:0]  counter_60hz = 0;
   reg [$clog2(COUNTER_12US_MAX)-1:0]  counter_12us = 0;
   reg [3:0]                           data_counter = 0;
   reg [SNES_BUTTON_COUNT-1:0]         buf_button_state = 0;

   always @ (posedge clk) begin

      data_clk <= counter_12us < 600;
      data_latch <= 0;

      if (COUNTER_60HZ_MAX - 1 == counter_60hz) begin
         counter_60hz <= 0;
      end else begin
         counter_60hz <= counter_60hz + 1;
      end

      if (COUNTER_12US_MAX - 1 == counter_12us) begin
         counter_12us <= 0;
      end else begin
         counter_12us <= counter_12us + 1;
      end

      case (state)

        STATE_WAIT: begin
           data_clk <= 1;
           if (0 == counter_60hz) begin
              counter_12us <= 0;
              state <= STATE_LATCH;
           end
        end


        STATE_LATCH: begin
           data_clk <= 1;
           data_latch <= 1;
           if (COUNTER_12US_MAX - 1 == counter_12us) begin
              state <= STATE_DATA;
           end
        end


        STATE_DATA: begin
           if ((COUNTER_12US_MAX / 2) - 1 == counter_12us) begin
              if (data_counter < 12) begin
                 buf_button_state <= { ~serial_in, buf_button_state[11:1] };
              end else if (~serial_in) begin



                 buf_button_state <= 0;
              end
              if (15 == data_counter) begin
                 data_counter <= 0;
                 button_state <= buf_button_state;
                 state <= STATE_WAIT;
              end else begin
                 data_counter <= data_counter + 1;
              end
           end
        end
      endcase
   end

endmodule
module snes_controller
  (
   input                              clk,
   input                              serial_in,
   output reg                         data_clk,
   output reg                         data_latch, 
   output reg [SNES_BUTTON_COUNT-1:0] button_state
   );


   initial begin
      data_clk = 0;
      data_latch = 0;
      button_state = 0;
   end

   localparam SNES_BUTTON_COUNT = 12;

   localparam COUNTER_60HZ_MAX = 100000000 / 60;
   localparam COUNTER_12US_MAX = 1200;

   localparam STATE_WAIT = 0;
   localparam STATE_LATCH = 1;
   localparam STATE_DATA = 2;

   reg [1:0]                           state = STATE_WAIT;
   reg [$clog2(COUNTER_60HZ_MAX)-1:0]  counter_60hz = 0;
   reg [$clog2(COUNTER_12US_MAX)-1:0]  counter_12us = 0;
   reg [3:0]                           data_counter = 0;
   reg [SNES_BUTTON_COUNT-1:0]         buf_button_state = 0;

   always @ (posedge clk) begin

      data_clk <= counter_12us < 600;
      data_latch <= 0;

      if (COUNTER_60HZ_MAX - 1 == counter_60hz) begin
         counter_60hz <= 0;
      end else begin
         counter_60hz <= counter_60hz + 1;
      end

      if (COUNTER_12US_MAX - 1 == counter_12us) begin
         counter_12us <= 0;
      end else begin
         counter_12us <= counter_12us + 1;
      end

      case (state)

        STATE_WAIT: begin
           data_clk <= 1;
           if (0 == counter_60hz) begin
              counter_12us <= 0;
              state <= STATE_LATCH;
           end
        end


        STATE_LATCH: begin
           data_clk <= 1;
           data_latch <= 1;
           if (COUNTER_12US_MAX - 1 == counter_12us) begin
              state <= STATE_DATA;
           end
        end


        STATE_DATA: begin
           if ((COUNTER_12US_MAX / 2) - 1 == counter_12us) begin
              if (data_counter < 12) begin
                 buf_button_state <= { ~serial_in, buf_button_state[11:1] };
              end else if (~serial_in) begin



                 buf_button_state <= 0;
              end
              if (15 == data_counter) begin
                 data_counter <= 0;
                 button_state <= buf_button_state;
                 state <= STATE_WAIT;
              end else begin
                 data_counter <= data_counter + 1;
              end
           end
        end
      endcase
   end

endmodule