data/full_repos/permissive/509809169/Circuits/Building Larger Circuits/FSM_ Sequence 1101 recognizer.v
1: b'%Error: Cannot find file containing module: Larger\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Building/Larger\n             data/full_repos/permissive/509809169/Circuits/Building/Larger.v\n             data/full_repos/permissive/509809169/Circuits/Building/Larger.sv\n             Larger\n             Larger.v\n             Larger.sv\n             obj_dir/Larger\n             obj_dir/Larger.v\n             obj_dir/Larger.sv\n%Error: Cannot find file containing module: Circuits,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Building\n%Error: Cannot find file containing module: Circuits/FSM_\n%Error: Cannot find file containing module: Sequence\n%Error: Cannot find file containing module: 1101\n%Error: Cannot find file containing module: recognizer.v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input reset,
    input data,
    output start_shifting);

    parameter A=0,B=1,C=2,D=3,E=4;
    reg [3:0] state,next;
    always @(*) begin
        case(state)
            A: next = data? B:A;
            B: next = data? C:A;
            C: next = data? C:D;
            D: next = data? E:A;
            E: next = E;
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)state<=A;
        else state<=next;
    end
    
    assign start_shifting = (state==E);
        
endmodule
module top_module (
    input clk,
    input reset,
    input data,
    output start_shifting);


    parameter A=0,B=1,C=2,D=3,E=4;
    reg [3:0] state,next;
    always @(*) begin
        case(state)
            A: next = data? B:A;
            B: next = data? C:A;
            C: next = data? C:D;
            D: next = data? E:A;
            E: next = E;
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)state<=A;
        else state<=next;
    end
    
    assign start_shifting = (state==E);
        
endmodule