data/full_repos/permissive/429737743/sources_1/new/ALU.v
1: b'%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:21: Cannot find include file: cpu_constant.v\n`include "cpu_constant.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.sv\n             cpu_constant.v\n             cpu_constant.v.v\n             cpu_constant.v.sv\n             obj_dir/cpu_constant.v\n             obj_dir/cpu_constant.v.v\n             obj_dir/cpu_constant.v.sv\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:32: Define or directive not defined: \'`ADD\'\n            `ADD : Ans = a + b;\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:32: syntax error, unexpected \':\', expecting endcase\n            `ADD : Ans = a + b;\n                 ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:33: Define or directive not defined: \'`SUB\'\n            `SUB : Ans = a - b;\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:34: Define or directive not defined: \'`XOR\'\n            `XOR : Ans = a ^ b;\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:35: Define or directive not defined: \'`OR\'\n            `OR  : Ans = a | b;\n            ^~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:36: Define or directive not defined: \'`AND\'\n            `AND : Ans = a & b;\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:37: Define or directive not defined: \'`SLL\'\n            `SLL : Ans = a << b[4 : 0];\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:38: Define or directive not defined: \'`SRL\'\n            `SRL : Ans = a >> b[4 : 0];\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:39: Define or directive not defined: \'`SRA\'\n            `SRA : Ans = ($signed(a)) >>> {b[0], b[1], b[2], b[3], b[4]};\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:40: Define or directive not defined: \'`SLT\'\n            `SLT : Ans = ($signed(a) < $signed(b)) ? 1 : 0;\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/ALU.v:41: Define or directive not defined: \'`SLTU\'\n            `SLTU : Ans = (a < b) ? 1 : 0;\n            ^~~~~\n%Error: Cannot continue\n'
module ALU(Ans, op, enable, a, b);
output [31 : 0] Ans;
reg [31 : 0] Ans;
input [31 : 0] a, b;
input [3 : 0] op;
input enable;
always @(*) begin
    if (enable) begin
        case (op)
            `ADD : Ans = a + b;
            `SUB : Ans = a - b;
            `XOR : Ans = a ^ b;
            `OR  : Ans = a | b;
            `AND : Ans = a & b;
            `SLL : Ans = a << b[4 : 0];
            `SRL : Ans = a >> b[4 : 0];
            `SRA : Ans = ($signed(a)) >>> {b[0], b[1], b[2], b[3], b[4]};
            `SLT : Ans = ($signed(a) < $signed(b)) ? 1 : 0;
            `SLTU : Ans = (a < b) ? 1 : 0;
            default : Ans = -1;
        endcase
    end
end
endmodule
module ALU(Ans, op, enable, a, b);

output [31 : 0] Ans;
reg [31 : 0] Ans;
input [31 : 0] a, b;
input [3 : 0] op;
input enable;
always @(*) begin
    if (enable) begin
        case (op)
            `ADD : Ans = a + b;
            `SUB : Ans = a - b;
            `XOR : Ans = a ^ b;
            `OR  : Ans = a | b;
            `AND : Ans = a & b;
            `SLL : Ans = a << b[4 : 0];
            `SRL : Ans = a >> b[4 : 0];
            `SRA : Ans = ($signed(a)) >>> {b[0], b[1], b[2], b[3], b[4]};
            `SLT : Ans = ($signed(a) < $signed(b)) ? 1 : 0;
            `SLTU : Ans = (a < b) ? 1 : 0;
            default : Ans = -1;
        endcase
    end
end
endmodule