data/full_repos/permissive/471941633/adder_multiplier/Reg2.v
data/verilator_xmls/5f3e98c5-6d27-4646-b7e0-21c45bf0e044.xml
module Reg2(input clk,load_P,clear_p,
	    input[15:0]data_P,output reg[15:0]Y
    );
always @(posedge clk)
	begin
		if(clear_p)
		Y <= 16'h0000;
		else if(load_P)
		Y <= data_P;
	end
endmodule
module Reg2(input clk,load_P,clear_p,
	    input[15:0]data_P,output reg[15:0]Y
    );

always @(posedge clk)
	begin
		if(clear_p)
		Y <= 16'h0000;
		else if(load_P)
		Y <= data_P;
	end
endmodule