data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz.v
data/verilator_xmls/f260c190-f5ee-4d12-b30b-384b5b6633fa.xml
module div_freq_100hz(input wire CLK_IN, output wire CLK_OUT);
    reg [6:0] counter = 0;
    reg out_1hz = 0;

    assign CLK_OUT = out_1hz;

    always @(posedge CLK_IN) begin
        counter <= counter + 1;

        if (counter == 7'd99) begin
            out_1hz <= 1;
            counter <= 0;
        end
        else
            out_1hz <= 0;
    end

endmodule
module div_freq_100hz(input wire CLK_IN, output wire CLK_OUT);

    reg [6:0] counter = 0;
    reg out_1hz = 0;

    assign CLK_OUT = out_1hz;

    always @(posedge CLK_IN) begin
        counter <= counter + 1;

        if (counter == 7'd99) begin
            out_1hz <= 1;
            counter <= 0;
        end
        else
            out_1hz <= 0;
    end

endmodule