data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v
1: b'%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:58: Define or directive not defined: \'`clk\'\nalways @(posedge `clk or negedge `rst_b)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:58: syntax error, unexpected or, expecting TYPE-IDENTIFIER\nalways @(posedge `clk or negedge `rst_b)\n                      ^~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:58: Define or directive not defined: \'`rst_b\'\nalways @(posedge `clk or negedge `rst_b)\n                                 ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:60: Define or directive not defined: \'`rst_b\'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:66: Define or directive not defined: \'`clk\'\nalways @(posedge `clk)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:72: Define or directive not defined: \'`clk\'\nalways @(posedge `clk or negedge `rst_b)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:72: Define or directive not defined: \'`rst_b\'\nalways @(posedge `clk or negedge `rst_b)\n                                 ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:74: Define or directive not defined: \'`rst_b\'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:80: Define or directive not defined: \'`clk\'\nalways @(posedge `clk)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:102: Define or directive not defined: \'`clk\'\nalways @(posedge `clk or negedge `rst_b)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:102: syntax error, unexpected or, expecting TYPE-IDENTIFIER\nalways @(posedge `clk or negedge `rst_b)\n                      ^~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:102: Define or directive not defined: \'`rst_b\'\nalways @(posedge `clk or negedge `rst_b)\n                                 ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:104: Define or directive not defined: \'`rst_b\'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:125: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  GPR_FH = $fopen("GPR.log");\n           ^~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:139: Define or directive not defined: \'`clk\'\nalways @(posedge `clk)\n                 ^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:139: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nalways @(posedge `clk)\n                     ^\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:149: syntax error, unexpected $fwrite\n              $fwrite(GPR_FH, "gr%2d:%8h |",i,wb_gpr_data_latch[31:0]);\n              ^~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:153: syntax error, unexpected $fwrite\n              $fwrite(GPR_FH, "gr%2d:%8h |",i,GPR[i]);\n              ^~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:157: syntax error, unexpected $fwrite\n              $fwrite(GPR_FH, "\\n");\n              ^~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/tb/mnt.v:160: syntax error, unexpected $fwrite\n      $fwrite(GPR_FH, "\\n");\n      ^~~~~~~\n%Error: Cannot continue\n'
module mnt();



reg             retire_latch;
reg     [31:0]  retire_pc_latch;



reg             wb_gpr_en_delay1;
reg     [ 4:0]  wb_gpr_index_delay1;
reg     [31:0]  wb_gpr_data_delay1;


reg     [31:0]  GPR [31:0];




wire            wb_gpr_en_latch;
wire    [ 4:0]  wb_gpr_index_latch;
wire    [31:0]  wb_gpr_data_latch;




always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    retire_latch     <=  1'b0;
  else
    retire_latch     <=  `retire;
end

always @(posedge `clk)
begin
  retire_pc_latch[31:0] <=  `retire_pc[31:0];
end


always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    wb_gpr_en_delay1  <= 1'b0;
  else
    wb_gpr_en_delay1  <= `wb_gpr_en;
end

always @(posedge `clk)
begin
  wb_gpr_index_delay1[4:0]  <= `wb_gpr_index[4:0];
  wb_gpr_data_delay1[31:0]  <= `wb_gpr_data[31:0];
end



assign wb_gpr_en_latch          = `wb_gpr_en;
assign wb_gpr_index_latch[4:0]  = `wb_gpr_index[4:0];
assign wb_gpr_data_latch[31:0]  = `wb_gpr_data[31:0];





wire   gpr_we;

assign gpr_we   =   wb_gpr_en_latch;
  
integer i;

always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    begin
      for(i = 0; i < 32; i = i+1)
        begin
          GPR[i] <= 32'b0;
        end
    end
  else if(gpr_we)
    begin
      GPR[wb_gpr_index_latch]  <= wb_gpr_data_latch;
    end
end





integer GPR_FH;

initial
begin
  GPR_FH = $fopen("GPR.log");
  if(GPR_FH == 0)
    begin
      $display("can't open log file GPR.log in mnt.v!");
      $finish;
    end
end




wire   retire_pc_print;
assign retire_pc_print   = retire_latch;

always @(posedge `clk)
begin
  if(retire_pc_print)      
    begin
      $fwrite(GPR_FH, "PC : %8h |", retire_pc_latch[31:0]);
      $fwrite(GPR_FH, "PSR: %8h\n", `psr);
      for(i = 0; i < 32; i = i+1)
        begin
          if(wb_gpr_en_latch && (i == wb_gpr_index_latch[4:0]))
            begin     
              $fwrite(GPR_FH, "gr%2d:%8h |",i,wb_gpr_data_latch[31:0]);
           end
          else
            begin
              $fwrite(GPR_FH, "gr%2d:%8h |",i,GPR[i]);
            end
          if(i % 4 == 3)
            begin
              $fwrite(GPR_FH, "\n");
            end
        end
      $fwrite(GPR_FH, "\n");
    end
end

endmodule
module mnt();




reg             retire_latch;
reg     [31:0]  retire_pc_latch;



reg             wb_gpr_en_delay1;
reg     [ 4:0]  wb_gpr_index_delay1;
reg     [31:0]  wb_gpr_data_delay1;


reg     [31:0]  GPR [31:0];




wire            wb_gpr_en_latch;
wire    [ 4:0]  wb_gpr_index_latch;
wire    [31:0]  wb_gpr_data_latch;




always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    retire_latch     <=  1'b0;
  else
    retire_latch     <=  `retire;
end

always @(posedge `clk)
begin
  retire_pc_latch[31:0] <=  `retire_pc[31:0];
end


always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    wb_gpr_en_delay1  <= 1'b0;
  else
    wb_gpr_en_delay1  <= `wb_gpr_en;
end

always @(posedge `clk)
begin
  wb_gpr_index_delay1[4:0]  <= `wb_gpr_index[4:0];
  wb_gpr_data_delay1[31:0]  <= `wb_gpr_data[31:0];
end



assign wb_gpr_en_latch          = `wb_gpr_en;
assign wb_gpr_index_latch[4:0]  = `wb_gpr_index[4:0];
assign wb_gpr_data_latch[31:0]  = `wb_gpr_data[31:0];





wire   gpr_we;

assign gpr_we   =   wb_gpr_en_latch;
  
integer i;

always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
    begin
      for(i = 0; i < 32; i = i+1)
        begin
          GPR[i] <= 32'b0;
        end
    end
  else if(gpr_we)
    begin
      GPR[wb_gpr_index_latch]  <= wb_gpr_data_latch;
    end
end





integer GPR_FH;

initial
begin
  GPR_FH = $fopen("GPR.log");
  if(GPR_FH == 0)
    begin
      $display("can't open log file GPR.log in mnt.v!");
      $finish;
    end
end




wire   retire_pc_print;
assign retire_pc_print   = retire_latch;

always @(posedge `clk)
begin
  if(retire_pc_print)      
    begin
      $fwrite(GPR_FH, "PC : %8h |", retire_pc_latch[31:0]);
      $fwrite(GPR_FH, "PSR: %8h\n", `psr);
      for(i = 0; i < 32; i = i+1)
        begin
          if(wb_gpr_en_latch && (i == wb_gpr_index_latch[4:0]))
            begin     
              $fwrite(GPR_FH, "gr%2d:%8h |",i,wb_gpr_data_latch[31:0]);
           end
          else
            begin
              $fwrite(GPR_FH, "gr%2d:%8h |",i,GPR[i]);
            end
          if(i % 4 == 3)
            begin
              $fwrite(GPR_FH, "\n");
            end
        end
      $fwrite(GPR_FH, "\n");
    end
end

endmodule