data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/testbench_phy_tx.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/testbench_phy_tx.v:2: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx,data/full_repos/permissive/425529933/cmos_cells.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx,data/full_repos/permissive/425529933/cmos_cells.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx,data/full_repos/permissive/425529933/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/testbench_phy_tx.v:3: Cannot find include file: probador_phy_tx.v\n`include "probador_phy_tx.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/testbench_phy_tx.v:4: Cannot find include file: phy_tx_c.v\n`include "phy_tx_c.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/testbench_phy_tx.v:5: Cannot find include file: phy_tx_e.v\n`include "phy_tx_e.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench_phy_tx (
);
	wire clk_32f;
	wire clk_2f;
	wire clk_4f;
	wire reset;
	wire valid_in;
	wire [31:0] Data_in;
	wire [7:0] Data_out_0_c;
	wire [7:0] Data_out_1_c;
	wire [7:0] Data_out_1_e;
	wire [7:0] Data_out_0_e;

	probador_phy_tx probador_phy_tx1 (
										.clk_32f(clk_32f),
										.clk_2f(clk_2f),
										.clk_4f(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.Data_out_1bit_0_c(Data_out_1bit_0_c),
										.Data_out_1bit_1_c(Data_out_1bit_1_c),
										.Data_out_1bit_0_e(Data_out_1bit_0_e),
										.Data_out_1bit_1_e(Data_out_1bit_1_e)
	);

	phy_tx_c phy_tx_c1 (
                        .clk_32f(clk_32f),
	                    .clk_2f_c(clk_2f),
	                    .clk_4f_c(clk_4f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
	                    .Data_out_1bit_0_c(Data_out_1bit_0_c),
	                    .Data_out_1bit_1_c(Data_out_1bit_1_c)
                        );

    phy_tx_e phy_tx_e1 (
                        .clk_32f(clk_32f),
	                    .clk_2f_e(clk_2f),
	                    .clk_4f_e(clk_4f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
	                    .Data_out_1bit_0_e(Data_out_1bit_0_e),
	                    .Data_out_1bit_1_e(Data_out_1bit_1_e)

	);

endmodule
module testbench_phy_tx (
);

	wire clk_32f;
	wire clk_2f;
	wire clk_4f;
	wire reset;
	wire valid_in;
	wire [31:0] Data_in;
	wire [7:0] Data_out_0_c;
	wire [7:0] Data_out_1_c;
	wire [7:0] Data_out_1_e;
	wire [7:0] Data_out_0_e;

	probador_phy_tx probador_phy_tx1 (
										.clk_32f(clk_32f),
										.clk_2f(clk_2f),
										.clk_4f(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.Data_out_1bit_0_c(Data_out_1bit_0_c),
										.Data_out_1bit_1_c(Data_out_1bit_1_c),
										.Data_out_1bit_0_e(Data_out_1bit_0_e),
										.Data_out_1bit_1_e(Data_out_1bit_1_e)
	);

	phy_tx_c phy_tx_c1 (
                        .clk_32f(clk_32f),
	                    .clk_2f_c(clk_2f),
	                    .clk_4f_c(clk_4f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
	                    .Data_out_1bit_0_c(Data_out_1bit_0_c),
	                    .Data_out_1bit_1_c(Data_out_1bit_1_c)
                        );

    phy_tx_e phy_tx_e1 (
                        .clk_32f(clk_32f),
	                    .clk_2f_e(clk_2f),
	                    .clk_4f_e(clk_4f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
	                    .Data_out_1bit_0_e(Data_out_1bit_0_e),
	                    .Data_out_1bit_1_e(Data_out_1bit_1_e)

	);

endmodule