data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/sbt/RealAdder.lo.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/sbt/RealAdder.lo.v:15: Cannot find file containing module: 'BBFAdd'\n  BBFAdd BBFAdd (  \n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/sbt,data/full_repos/permissive/493019833/BBFAdd\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/sbt,data/full_repos/permissive/493019833/BBFAdd.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/sbt,data/full_repos/permissive/493019833/BBFAdd.sv\n             BBFAdd\n             BBFAdd.v\n             BBFAdd.sv\n             obj_dir/BBFAdd\n             obj_dir/BBFAdd.v\n             obj_dir/BBFAdd.sv\n%Error: Exiting due to 1 error(s)\n"
module RealAdder(
  input         clock,
  input         reset,
  input  [63:0] io_a1_node,
  input  [63:0] io_a2_node,
  output [63:0] io_c_node
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif
  wire [63:0] BBFAdd_out;
  wire [63:0] BBFAdd_in2;
  wire [63:0] BBFAdd_in1;
  reg [63:0] register1_node;
  BBFAdd BBFAdd (
    .out(BBFAdd_out),
    .in2(BBFAdd_in2),
    .in1(BBFAdd_in1)
  );
  assign io_c_node = register1_node;
  assign BBFAdd_in2 = io_a2_node;
  assign BBFAdd_in1 = io_a1_node;
  always @(posedge clock) begin
    register1_node <= BBFAdd_out;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  register1_node = _RAND_0[63:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module RealAdder(
  input         clock,
  input         reset,
  input  [63:0] io_a1_node,
  input  [63:0] io_a2_node,
  output [63:0] io_c_node
);

`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif
  wire [63:0] BBFAdd_out;
  wire [63:0] BBFAdd_in2;
  wire [63:0] BBFAdd_in1;
  reg [63:0] register1_node;
  BBFAdd BBFAdd (
    .out(BBFAdd_out),
    .in2(BBFAdd_in2),
    .in1(BBFAdd_in1)
  );
  assign io_c_node = register1_node;
  assign BBFAdd_in2 = io_a2_node;
  assign BBFAdd_in1 = io_a1_node;
  always @(posedge clock) begin
    register1_node <= BBFAdd_out;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  register1_node = _RAND_0[63:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule