data/full_repos/permissive/433367655/Source/microarchitecture_tb.v
1: b'%Error: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:2: Cannot find include file: microarchitecture.v\n`include "microarchitecture.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/microarchitecture.v\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/microarchitecture.v.v\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/microarchitecture.v.sv\n             microarchitecture.v\n             microarchitecture.v.v\n             microarchitecture.v.sv\n             obj_dir/microarchitecture.v\n             obj_dir/microarchitecture.v.v\n             obj_dir/microarchitecture.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("RESULT.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/433367655/Source/microarchitecture_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #4000\n        ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module microarchitecture_tb();

    reg [31:0] sw = 32'd5;

    reg clk = 1'b1;
    always #1 clk = !clk;

    reg rst = 1'b1;
    
    wire [31:0] out;

    microarchitecture microarchitecture(clk, rst, sw, out);

    initial begin
        rst = 1'b1;
        #10
        rst = 1'b0;
        $dumpfile("RESULT.vcd");
        $dumpvars;
        #4000
        $display("Result: ", out);
        $finish;
    end
endmodule
module microarchitecture_tb();


    reg [31:0] sw = 32'd5;

    reg clk = 1'b1;
    always #1 clk = !clk;

    reg rst = 1'b1;
    
    wire [31:0] out;

    microarchitecture microarchitecture(clk, rst, sw, out);

    initial begin
        rst = 1'b1;
        #10
        rst = 1'b0;
        $dumpfile("RESULT.vcd");
        $dumpvars;
        #4000
        $display("Result: ", out);
        $finish;
    end
endmodule