data/full_repos/permissive/440575220/data_memory.v
data/verilator_xmls/42fd735d-3e83-4b2b-9990-2727f06b60b1.xml
module data_memory(
                   input clk,
                   input WE,
                   input [3:0] I,
                   input [31:0] A,
                   input [31:0] WD,
                   output [31:0] RD
                   );
   reg [31:0]                    RAM[0:63];
   assign RD = (WE == 0) ? RAM[A] : 32'b0;

   always @(posedge clk) if (WE) RAM[A] <= WD;

endmodule
module data_memory(
                   input clk,
                   input WE,
                   input [3:0] I,
                   input [31:0] A,
                   input [31:0] WD,
                   output [31:0] RD
                   );

   reg [31:0]                    RAM[0:63];
   assign RD = (WE == 0) ? RAM[A] : 32'b0;

   always @(posedge clk) if (WE) RAM[A] <= WD;

endmodule