data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb/Special_Adder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb/Special_Adder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #20 Data1 = 5\'b00010;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb/Special_Adder_tb.v:6: Cannot find file containing module: \'spec_adder\'\n spec_adder u1 (.Data1(Data1), .Data2(Data2), .Data3(Data3), .Out_Data(Out_Data));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb,data/full_repos/permissive/518325211/spec_adder\n             data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb,data/full_repos/permissive/518325211/spec_adder.v\n             data/full_repos/permissive/518325211/pll/DSM_lib/verilog-rtl_tb,data/full_repos/permissive/518325211/spec_adder.sv\n             spec_adder\n             spec_adder.v\n             spec_adder.sv\n             obj_dir/spec_adder\n             obj_dir/spec_adder.v\n             obj_dir/spec_adder.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spec_adder_tb;

	reg [4:0] Data1, Data2, Data3;
	wire [4:0] Out_Data;

	spec_adder u1 (.Data1(Data1), .Data2(Data2), .Data3(Data3), .Out_Data(Out_Data));

	initial begin
		Data1 = 5'b00001;
		Data2 = 5'b00001;
		Data3 = 5'b00001;

	#20	Data1 = 5'b00010;
		Data2 = 5'b00001;
		Data3 = 5'b00001;


	end
endmodule
module spec_adder_tb;


	reg [4:0] Data1, Data2, Data3;
	wire [4:0] Out_Data;

	spec_adder u1 (.Data1(Data1), .Data2(Data2), .Data3(Data3), .Out_Data(Out_Data));

	initial begin
		Data1 = 5'b00001;
		Data2 = 5'b00001;
		Data3 = 5'b00001;

	#20	Data1 = 5'b00010;
		Data2 = 5'b00001;
		Data3 = 5'b00001;


	end
endmodule