data/full_repos/permissive/423547971/FPGA Projects/VGA Projects/VGA Full Screen Text Editor/debounce.v
1: b'%Error: Cannot find file containing module: Projects/VGA\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.v\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.sv\n             Projects/VGA\n             Projects/VGA.v\n             Projects/VGA.sv\n             obj_dir/Projects/VGA\n             obj_dir/Projects/VGA.v\n             obj_dir/Projects/VGA.sv\n%Error: Cannot find file containing module: Full\n%Error: Cannot find file containing module: Screen\n%Error: Cannot find file containing module: Text\n%Error: Cannot find file containing module: Editor,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Editor/debounce.v\n%Error: Exiting due to 7 error(s)\n'
module debounce_chu(
	input clk,
	input reset,
	input sw,
	output reg db_level, db_tick
	);
	

	parameter [1:0] 
				zero  = 2'b00,
				wait0 = 2'b01,
				one   = 2'b10,
				wait1 = 2'b11;
				

	parameter N = 21;
	

	reg [N-1:0] q_reg, q_next;
	reg [1:0] state_reg, state_next;
	


	always @(posedge clk or posedge reset)
		if(reset)
			begin
				state_reg <= zero;
				q_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				q_reg <= q_next;
			end
	

	always @*
	begin
		state_next = state_reg;
		q_next = q_reg;
		db_tick = 1'b0;
		case(state_reg)
			
			zero : 
				begin
					db_level = 1'b0;
					if(sw)
						begin
							state_next = wait1;
							q_next = {N{1'b1}};
						end
				end
			
			wait1 :
				begin
					db_level = 1'b0;
					if(sw)
						begin
							
							q_next = q_reg - 1;
							if(q_next == 0)
								begin
									state_next = one;
									db_tick = 1'b1;
								end
						end
					else
						state_next = zero;
				end
			
			one :
				begin
					db_level = 1'b1;
					if(~sw)
						begin
							state_next = wait0;
							q_next = {N{1'b1}};
						end
				end		
	
			wait0 :
				begin
					db_level = 1'b1;
					if(~sw)
						begin
							q_next = q_reg - 1;
							if(q_next == 0)
								state_next = zero;
						end
					else
						state_next = one;
				end
				
			default : state_next = zero;
		endcase
	end
endmodule
module debounce_chu(
	input clk,
	input reset,
	input sw,
	output reg db_level, db_tick
	);

	

	parameter [1:0] 
				zero  = 2'b00,
				wait0 = 2'b01,
				one   = 2'b10,
				wait1 = 2'b11;
				

	parameter N = 21;
	

	reg [N-1:0] q_reg, q_next;
	reg [1:0] state_reg, state_next;
	


	always @(posedge clk or posedge reset)
		if(reset)
			begin
				state_reg <= zero;
				q_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				q_reg <= q_next;
			end
	

	always @*
	begin
		state_next = state_reg;
		q_next = q_reg;
		db_tick = 1'b0;
		case(state_reg)
			
			zero : 
				begin
					db_level = 1'b0;
					if(sw)
						begin
							state_next = wait1;
							q_next = {N{1'b1}};
						end
				end
			
			wait1 :
				begin
					db_level = 1'b0;
					if(sw)
						begin
							
							q_next = q_reg - 1;
							if(q_next == 0)
								begin
									state_next = one;
									db_tick = 1'b1;
								end
						end
					else
						state_next = zero;
				end
			
			one :
				begin
					db_level = 1'b1;
					if(~sw)
						begin
							state_next = wait0;
							q_next = {N{1'b1}};
						end
				end		
	
			wait0 :
				begin
					db_level = 1'b1;
					if(~sw)
						begin
							q_next = q_reg - 1;
							if(q_next == 0)
								state_next = zero;
						end
					else
						state_next = one;
				end
				
			default : state_next = zero;
		endcase
	end
endmodule