data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/cachelib/v_rtl/dut_Add_7U_4_4.v
data/verilator_xmls/ca99de68-900a-4699-b7e8-8e563d2d80fc.xml
module dut_Add_7U_4_4 (
	in2,
	in1,
	out1
	);
input [6:0] in2,
	in1;
output [6:0] out1;
wire [6:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_7U_4_4 (
	in2,
	in1,
	out1
	);

input [6:0] in2,
	in1;
output [6:0] out1;
wire [6:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule