data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_jtag_clk_sel_0_0_ff (

sel_clk, 

test_mode_pin, trst, pll_bypass_pin, sel_ff
);

input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;

wire   tmp0, tmp1;

bw_u1_oai21_4x u_oai21 (.z(tmp0), .a(test_mode_pin), .b1(trst), .b2(pll_bypass_pin));
bw_u1_nand2_4x u_nand2 (.z(tmp1), .a(tmp0), .b(sel_ff));
bw_u1_inv_8x   u_inv   (.z(sel_clk), .a(tmp1) );

endmodule
module ctu_jtag_clk_sel_0_0_ff (

sel_clk, 

test_mode_pin, trst, pll_bypass_pin, sel_ff
);


input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;

wire   tmp0, tmp1;

bw_u1_oai21_4x u_oai21 (.z(tmp0), .a(test_mode_pin), .b1(trst), .b2(pll_bypass_pin));
bw_u1_nand2_4x u_nand2 (.z(tmp1), .a(tmp0), .b(sel_ff));
bw_u1_inv_8x   u_inv   (.z(sel_clk), .a(tmp1) );

endmodule