data/full_repos/permissive/520428138/verilog/rtl/user_module_341174563322724948.v
data/verilator_xmls/972546a4-8a5b-4efa-a228-1cdb77963d39.xml
module encoder_8to3_341174563322724948(
    input [7:0] in,
    output [2:0] out
);

assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
module encoder_8to3_341174563322724948(
    input [7:0] in,
    output [2:0] out
);


assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule