data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD*DUTY_CYCLE);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n #OFFSET\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #(3*PERIOD) miso = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #(3*PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:85: Unsupported: Ignoring delay on this delayed statement.\n #OFFSET\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:104: syntax error, unexpected \'@\'\n  @(*)begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/spi_master/spi_master_testbench.v:111: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_master_testbench;


	reg clk;
	reg rst;
	reg sssd_in;
	reg start;
	reg miso;
	reg [7:0] data_in;


	wire mosi;
	wire sck;
	wire ss;
	wire sssd_out;
	wire [7:0] data_out;
	wire busy;
	wire new_data;
	

	parameter PERIOD          = 10;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;


	spi_master uut (
		.clk(clk), 
		.rst(rst), 
		.sssd_in(sssd_in),
		.start(start), 
		.miso(miso), 
		.data_in(data_in), 
		.mosi(mosi), 
		.sck(sck), 
		.ss(ss), 
		.ss(sssd_out),
		.data_out(data_out), 
		.busy(busy), 
		.new_data(new_data)
	);

	initial begin

		clk = 0;
		rst = 1;
		sssd_in = 1;
		start = 0;
		miso = 0;
		data_in = 0;
			
	#OFFSET
     forever
			begin
				clk = 1'b1;
				#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
				#(PERIOD*DUTY_CYCLE);
			end	
	end
	
	initial begin
	#OFFSET
		forever
			begin
				miso = 1'b1;
				#(3*PERIOD) miso = 1'b0;
				#(3*PERIOD);
			end
	end
	
	initial begin
	

		#10;
			rst=0;
			start=1;
			sssd_in=0;
			data_in=01011100;
		#10
			start=0;
		@(*)begin
			if (new_data)begin
				#20
					rst=1;
				#10
					rst=0;
			end
		end
	end
      
endmodule
module spi_master_testbench;



	reg clk;
	reg rst;
	reg sssd_in;
	reg start;
	reg miso;
	reg [7:0] data_in;


	wire mosi;
	wire sck;
	wire ss;
	wire sssd_out;
	wire [7:0] data_out;
	wire busy;
	wire new_data;
	

	parameter PERIOD          = 10;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;


	spi_master uut (
		.clk(clk), 
		.rst(rst), 
		.sssd_in(sssd_in),
		.start(start), 
		.miso(miso), 
		.data_in(data_in), 
		.mosi(mosi), 
		.sck(sck), 
		.ss(ss), 
		.ss(sssd_out),
		.data_out(data_out), 
		.busy(busy), 
		.new_data(new_data)
	);

	initial begin

		clk = 0;
		rst = 1;
		sssd_in = 1;
		start = 0;
		miso = 0;
		data_in = 0;
			
	#OFFSET
     forever
			begin
				clk = 1'b1;
				#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
				#(PERIOD*DUTY_CYCLE);
			end	
	end
	
	initial begin
	#OFFSET
		forever
			begin
				miso = 1'b1;
				#(3*PERIOD) miso = 1'b0;
				#(3*PERIOD);
			end
	end
	
	initial begin
	

		#10;
			rst=0;
			start=1;
			sssd_in=0;
			data_in=01011100;
		#10
			start=0;
		@(*)begin
			if (new_data)begin
				#20
					rst=1;
				#10
					rst=0;
			end
		end
	end
      
endmodule