data/full_repos/permissive/524532083/verilog/rtl/async_reg.v
data/verilator_xmls/745254b9-2ced-4240-b645-4b1b508b1f51.xml
module async_reg(
  input wire clock_async,
  input wire clock_sync,
  input wire data_async,
  output reg data_sync
);

  reg A,B;
  always@(posedge clock_async)
  begin
    A <= data_async;
  end

  always@(posedge clock_sync)
  begin
    B <= A;
    data_sync <= A;
  end

endmodule
module async_reg(
  input wire clock_async,
  input wire clock_sync,
  input wire data_async,
  output reg data_sync
);


  reg A,B;
  always@(posedge clock_async)
  begin
    A <= data_async;
  end

  always@(posedge clock_sync)
  begin
    B <= A;
    data_sync <= A;
  end

endmodule