data/full_repos/permissive/445379100/a3/mux.v
data/verilator_xmls/d3b6e7c2-3960-4f54-a3f0-c83cc1817ed1.xml
module mux (
    input [31:0] input0 ,
    input [31:0] input1 ,
    input mux_sel ,
    output reg [31:0] mux_output 
);

    always @(*) begin
        if ( mux_sel == 0 )    mux_output = input0 ;
        else                   mux_output = input1 ;
    end
    
endmodule
module mux (
    input [31:0] input0 ,
    input [31:0] input1 ,
    input mux_sel ,
    output reg [31:0] mux_output 
);


    always @(*) begin
        if ( mux_sel == 0 )    mux_output = input0 ;
        else                   mux_output = input1 ;
    end
    
endmodule