data/full_repos/permissive/420611307/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:20: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance cpu.ALU\n  4\'b0110: begin F = A < B; end\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420611307/cpu.v:79: Cannot find file containing module: \'instruction_memory\'\n instruction_memory ins_mem (\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory.v\n             data/full_repos/permissive/420611307,data/full_repos/permissive/420611307/instruction_memory.sv\n             instruction_memory\n             instruction_memory.v\n             instruction_memory.sv\n             obj_dir/instruction_memory\n             obj_dir/instruction_memory.v\n             obj_dir/instruction_memory.sv\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:160: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b100011: begin w_r_s = 2\'b01; imm_s = 1; rt_imm_s = 1; wr_data_s = 2\'b01; ALU_OP=3\'b100; end   \n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:161: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b101011: begin imm_s = 1; rt_imm_s = 1; ALU_OP = 3\'b100; Write_Reg = 0; Mem_Write = 1; end   \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:162: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b000100: begin ALU_OP = 3\'b101; PC_s = (ZF)?2\'b10:2\'b00; Write_Reg = 1\'b0; end   \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:163: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                              : ... In instance cpu\n   6\'b000101: begin ALU_OP = 3\'b101; PC_s = (ZF)?2\'b00:2\'b10; Write_Reg = 1\'b0; end   \n                           ^\n%Error: data/full_repos/permissive/420611307/cpu.v:203: Cannot find file containing module: \'data_memory\'\n data_memory data_mem (\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/420611307/cpu.v:215: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                              : ... In instance cpu\n  4\'b0100: begin f = {ZF, OF}; end\n                   ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module alu(A, B, ALU_OP, F, ZF, OF);
	input [31:0] A;
	input [31:0] B;
	input [3:0] ALU_OP;
	output reg [31:0] F;
	output reg ZF, OF;
	reg C;
	always@(*)
	begin
		C = 0; OF = 0; ZF = 0;
		case(ALU_OP)
		4'b0000: begin F = A & B; end
		4'b0001: begin F = A | B; end
		4'b0010: begin F = A ^ B; end
		4'b0011: begin F = ~(A | B); end 
		4'b0100: begin {C, F} = A + B; OF = A[31] ^ B[31] ^ F[31] ^ C; end 
		4'b0101: begin {C, F} = A - B; OF = A[31] ^ B[31] ^ F[31] ^ C; end 
		4'b0110: begin F = A < B; end
		4'b0111: begin F = B << A; end
		endcase
		ZF = F==0;
		end
endmodule
module alu(A, B, ALU_OP, F, ZF, OF);

	input [31:0] A;
	input [31:0] B;
	input [3:0] ALU_OP;
	output reg [31:0] F;
	output reg ZF, OF;
	reg C;
	always@(*)
	begin
		C = 0; OF = 0; ZF = 0;
		case(ALU_OP)
		4'b0000: begin F = A & B; end
		4'b0001: begin F = A | B; end
		4'b0010: begin F = A ^ B; end
		4'b0011: begin F = ~(A | B); end 
		4'b0100: begin {C, F} = A + B; OF = A[31] ^ B[31] ^ F[31] ^ C; end 
		4'b0101: begin {C, F} = A - B; OF = A[31] ^ B[31] ^ F[31] ^ C; end 
		4'b0110: begin F = A < B; end
		4'b0111: begin F = B << A; end
		endcase
		ZF = F==0;
		end
endmodule