data/full_repos/permissive/444277419/Verilog/carry_select.v
1: b"%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:15: Cannot find file containing module: 'com_32'\ncom_32 com_01(.a(A[0]),.b(B[0]),.c(1'b0),.co(CI_0[0]),.sum(S_0[0]));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444277419/Verilog,data/full_repos/permissive/444277419/com_32\n             data/full_repos/permissive/444277419/Verilog,data/full_repos/permissive/444277419/com_32.v\n             data/full_repos/permissive/444277419/Verilog,data/full_repos/permissive/444277419/com_32.sv\n             com_32\n             com_32.v\n             com_32.sv\n             obj_dir/com_32\n             obj_dir/com_32.v\n             obj_dir/com_32.sv\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:16: Cannot find file containing module: 'com_32'\ncom_32 com_02(.a(A[1]),.b(B[1]),.c(CI_0[0]),.co(CI_0[1]),.sum(S_0[1]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:17: Cannot find file containing module: 'com_32'\ncom_32 com_03(.a(A[2]),.b(B[2]),.c(CI_0[1]),.co(CI_0[2]),.sum(S_0[2]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:18: Cannot find file containing module: 'com_32'\ncom_32 com_04(.a(A[3]),.b(B[3]),.c(CI_0[2]),.co(CI_0[3]),.sum(S_0[3]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:21: Cannot find file containing module: 'com_32'\ncom_32 com_11(.a(A[0]),.b(B[0]),.c(1'b1),.co(CI_1[0]),.sum(S_1[0]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:22: Cannot find file containing module: 'com_32'\ncom_32 com_12(.a(A[1]),.b(B[1]),.c(CI_1[0]),.co(CI_1[1]),.sum(S_1[1]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:23: Cannot find file containing module: 'com_32'\ncom_32 com_13(.a(A[2]),.b(B[2]),.c(CI_1[1]),.co(CI_1[2]),.sum(S_1[2]));\n^~~~~~\n%Error: data/full_repos/permissive/444277419/Verilog/carry_select.v:24: Cannot find file containing module: 'com_32'\ncom_32 com_14(.a(A[3]),.b(B[3]),.c(CI_1[2]),.co(CI_1[3]),.sum(S_1[3]));\n^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module carry_select(
 A,
 B,
 Ci,
 CO,
 SUM);
input [3:0] A,B;
input Ci;
output reg CO;
output reg [3:0] SUM;

wire CI_0[3:0],S_0[3:0];
wire CI_1[3:0],S_1[3:0];

com_32 com_01(.a(A[0]),.b(B[0]),.c(1'b0),.co(CI_0[0]),.sum(S_0[0]));
com_32 com_02(.a(A[1]),.b(B[1]),.c(CI_0[0]),.co(CI_0[1]),.sum(S_0[1]));
com_32 com_03(.a(A[2]),.b(B[2]),.c(CI_0[1]),.co(CI_0[2]),.sum(S_0[2]));
com_32 com_04(.a(A[3]),.b(B[3]),.c(CI_0[2]),.co(CI_0[3]),.sum(S_0[3]));


com_32 com_11(.a(A[0]),.b(B[0]),.c(1'b1),.co(CI_1[0]),.sum(S_1[0]));
com_32 com_12(.a(A[1]),.b(B[1]),.c(CI_1[0]),.co(CI_1[1]),.sum(S_1[1]));
com_32 com_13(.a(A[2]),.b(B[2]),.c(CI_1[1]),.co(CI_1[2]),.sum(S_1[2]));
com_32 com_14(.a(A[3]),.b(B[3]),.c(CI_1[2]),.co(CI_1[3]),.sum(S_1[3]));


always@(*)begin
if(Ci)begin
CO=CI_1[3];
end else
CO=CI_0[3];
end


always@(*)begin
if(Ci)begin
SUM[0]=S_1[0];
SUM[1]=S_1[1];
SUM[2]=S_1[2];
SUM[3]=S_1[3];
end else
SUM[0]=S_0[0];
SUM[1]=S_0[1];
SUM[2]=S_0[2];
SUM[3]=S_0[3];
end
endmodule
module carry_select(
 A,
 B,
 Ci,
 CO,
 SUM);

input [3:0] A,B;
input Ci;
output reg CO;
output reg [3:0] SUM;

wire CI_0[3:0],S_0[3:0];
wire CI_1[3:0],S_1[3:0];

com_32 com_01(.a(A[0]),.b(B[0]),.c(1'b0),.co(CI_0[0]),.sum(S_0[0]));
com_32 com_02(.a(A[1]),.b(B[1]),.c(CI_0[0]),.co(CI_0[1]),.sum(S_0[1]));
com_32 com_03(.a(A[2]),.b(B[2]),.c(CI_0[1]),.co(CI_0[2]),.sum(S_0[2]));
com_32 com_04(.a(A[3]),.b(B[3]),.c(CI_0[2]),.co(CI_0[3]),.sum(S_0[3]));


com_32 com_11(.a(A[0]),.b(B[0]),.c(1'b1),.co(CI_1[0]),.sum(S_1[0]));
com_32 com_12(.a(A[1]),.b(B[1]),.c(CI_1[0]),.co(CI_1[1]),.sum(S_1[1]));
com_32 com_13(.a(A[2]),.b(B[2]),.c(CI_1[1]),.co(CI_1[2]),.sum(S_1[2]));
com_32 com_14(.a(A[3]),.b(B[3]),.c(CI_1[2]),.co(CI_1[3]),.sum(S_1[3]));


always@(*)begin
if(Ci)begin
CO=CI_1[3];
end else
CO=CI_0[3];
end


always@(*)begin
if(Ci)begin
SUM[0]=S_1[0];
SUM[1]=S_1[1];
SUM[2]=S_1[2];
SUM[3]=S_1[3];
end else
SUM[0]=S_0[0];
SUM[1]=S_0[1];
SUM[2]=S_0[2];
SUM[3]=S_0[3];
end
endmodule