data/full_repos/permissive/422421961/lib/tb/tb_clock_div.v
data/verilator_xmls/dd6c7820-a7da-4cc5-b866-dd6cb06e6d92.xml
module tb_clock_div (clk_in, rst, clk_out); 
  parameter cfactor= 2;
  input clk_in;
  input rst;
  output clk_out;
	reg clk_loc=0; 

	reg [10:0] cnt;
  

  
  assign clk_out = (cfactor==1)? clk_in : clk_loc;
  
  always@(posedge clk_in)
  begin: cdiv
      if(rst==1)
        begin
          cnt <= 'd0;
          clk_loc = 1;
        end
      else
        begin
          cnt <= cnt + 1'b1;
          if(cnt==cfactor/2-1) 
            clk_loc = 0;
          else if(cnt==cfactor-1) 
            begin
              cnt <= 'd0;
              clk_loc = 1;
            end
        end
  end
endmodule
module tb_clock_div (clk_in, rst, clk_out);
 
  parameter cfactor= 2;
  input clk_in;
  input rst;
  output clk_out;
	reg clk_loc=0; 

	reg [10:0] cnt;
  

  
  assign clk_out = (cfactor==1)? clk_in : clk_loc;
  
  always@(posedge clk_in)
  begin: cdiv
      if(rst==1)
        begin
          cnt <= 'd0;
          clk_loc = 1;
        end
      else
        begin
          cnt <= cnt + 1'b1;
          if(cnt==cfactor/2-1) 
            clk_loc = 0;
          else if(cnt==cfactor-1) 
            begin
              cnt <= 'd0;
              clk_loc = 1;
            end
        end
  end
endmodule