data/full_repos/permissive/439087417/rgst.v
data/verilator_xmls/d2c516f6-4b26-4d95-be0b-708365567ef5.xml
module rgst #(parameter dw = 'h10, clr_val = {dw{1'b0}})
(  input ld,
	input [dw-1:0] d,
	input clr,
	input clk,
	output reg [dw-1:0] q
    );

always @(posedge clk) begin
	if(clr) q <= clr_val;
	if(ld) q <= d;
end
endmodule
module rgst #(parameter dw = 'h10, clr_val = {dw{1'b0}})
(  input ld,
	input [dw-1:0] d,
	input clr,
	input clk,
	output reg [dw-1:0] q
    );


always @(posedge clk) begin
	if(clr) q <= clr_val;
	if(ld) q <= d;
end
endmodule