data/full_repos/permissive/486598419/6.7/Counter8.v
data/verilator_xmls/e27f036a-a689-40d8-a165-0360f7dcfb52.xml
module Counter8(
    input CLK,
    input rst_n,
    output reg [2:0] oQ,
    output [6:0] oDisplay
    );
    wire [2:0] tmp;
    wire y;
    wire z;
and(y,tmp[0],tmp[1]);
Divider D1(CLK,~rst_n,z);
JK_FF F0(z,1,1,rst_n,tmp[0]);
JK_FF F1(z,tmp[0],tmp[0],rst_n,tmp[1]);
JK_FF F2(z,y,y,rst_n,tmp[2]);
display7 d1(oQ,oDisplay);

always @(*)
    oQ<=tmp;

endmodule
module Counter8(
    input CLK,
    input rst_n,
    output reg [2:0] oQ,
    output [6:0] oDisplay
    );

    wire [2:0] tmp;
    wire y;
    wire z;
and(y,tmp[0],tmp[1]);
Divider D1(CLK,~rst_n,z);
JK_FF F0(z,1,1,rst_n,tmp[0]);
JK_FF F1(z,tmp[0],tmp[0],rst_n,tmp[1]);
JK_FF F2(z,y,y,rst_n,tmp[2]);
display7 d1(oQ,oDisplay);

always @(*)
    oQ<=tmp;

endmodule