data/full_repos/permissive/412297935/hdl/xio_bus.v
1: b'%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:46: Define or directive not defined: \'`XIO_STATE_IDLE\'\n                    xioState    <= `XIO_STATE_IDLE;  \n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    xioState    <= `XIO_STATE_IDLE;  \n                                                  ^\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:56: Define or directive not defined: \'`XIO_STATE_WRTS\'\n                        xioState    <= `XIO_STATE_WRTS;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                        xioState    <= `XIO_STATE_WRTS;\n                                                      ^\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:61: Define or directive not defined: \'`XIO_STATE_IDLE\'\n                    `XIO_STATE_IDLE:\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:61: syntax error, unexpected \':\', expecting endcase\n                    `XIO_STATE_IDLE:\n                                   ^\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:63: Define or directive not defined: \'`XIO_STATE_IDLE\'\n                            xioState        <= `XIO_STATE_IDLE;\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:66: Define or directive not defined: \'`XIO_STATE_WRTS\'\n                    `XIO_STATE_WRTS:\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:67: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                        begin\n                        ^~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:69: Define or directive not defined: \'`XIO_STATE_WCTS\'\n                            xioState        <= `XIO_STATE_WCTS;\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                            xioState        <= `XIO_STATE_WCTS;\n                                                              ^\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:72: Define or directive not defined: \'`XIO_STATE_WCTS\'\n                    `XIO_STATE_WCTS:\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:73: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                        begin\n                        ^~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:76: Define or directive not defined: \'`XIO_STATE_CMD\'\n                                    xioState    <= `XIO_STATE_CMD;\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:79: syntax error, unexpected end\n                        end\n                        ^~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:81: Define or directive not defined: \'`XIO_STATE_CMD\'\n                    `XIO_STATE_CMD:\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:85: Define or directive not defined: \'`XIO_STATE_CLK\'\n                            xioState        <= `XIO_STATE_CLK;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:87: Define or directive not defined: \'`XIO_CMD_SDRAM_READ\'\n                                `XIO_CMD_SDRAM_READ:    xioNext     <= `XIO_STATE_B3;\n                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:87: syntax error, unexpected \':\', expecting endcase\n                                `XIO_CMD_SDRAM_READ:    xioNext     <= `XIO_STATE_B3;\n                                                   ^\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:87: Define or directive not defined: \'`XIO_STATE_B3\'\n                                `XIO_CMD_SDRAM_READ:    xioNext     <= `XIO_STATE_B3;\n                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:88: Define or directive not defined: \'`XIO_STATE_DONE\'\n                                default            :    xioNext     <= `XIO_STATE_DONE;\n                                                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:92: Define or directive not defined: \'`XIO_STATE_CLK\'\n                    `XIO_STATE_CLK:\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:98: Define or directive not defined: \'`XIO_STATE_B3\'\n                    `XIO_STATE_B3:\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:102: Define or directive not defined: \'`XIO_STATE_B2\'\n                            xioNext         <= `XIO_STATE_B2;\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:103: Define or directive not defined: \'`XIO_STATE_CLK\'\n                            xioState        <= `XIO_STATE_CLK;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:106: Define or directive not defined: \'`XIO_STATE_B2\'\n                    `XIO_STATE_B2:\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:110: Define or directive not defined: \'`XIO_STATE_B1\'\n                            xioNext         <= `XIO_STATE_B1;\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:111: Define or directive not defined: \'`XIO_STATE_CLK\'\n                            xioState        <= `XIO_STATE_CLK;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:114: Define or directive not defined: \'`XIO_STATE_B1\'\n                    `XIO_STATE_B1:\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:118: Define or directive not defined: \'`XIO_STATE_B0\'\n                            xioNext         <= `XIO_STATE_B0;\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:119: Define or directive not defined: \'`XIO_STATE_CLK\'\n                            xioState        <= `XIO_STATE_CLK;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:122: Define or directive not defined: \'`XIO_STATE_B0\'\n                    `XIO_STATE_B0:\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:126: Define or directive not defined: \'`XIO_STATE_DONE\'\n                            xioNext         <= `XIO_STATE_DONE;\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:127: Define or directive not defined: \'`XIO_STATE_CLK\'\n                            xioState        <= `XIO_STATE_CLK;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:130: Define or directive not defined: \'`XIO_STATE_DONE\'\n                    `XIO_STATE_DONE:\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xio_bus.v:134: Define or directive not defined: \'`XIO_STATE_IDLE\'\n                            xioState        <= `XIO_STATE_IDLE;\n                                               ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module xio_bus 
	(
    input   wire            clk,
    input   wire            rst_n,
    
  	input   wire 	[7:0] 	rData,
    input   wire            rRts,
    input   wire            rClk,
    output  reg             rCts,
    
  	output  reg 	[7:0] 	wData,
    output  reg     [7:0]   wEn,
    output  reg             wRts,
    output  reg             wClk,
    input   wire            wCts,
    
    input   wire    [31:0]  data,
    input   wire    [3:0]   cmd,
    input   wire            cmdValid
  	);

    reg [3:0]   xioState;
    reg [3:0]   xioNext;
    reg [31:0]  xioData;
    reg [3:0]   xioCmd;
    
    
    always @ (posedge clk)
        begin
            if (rst_n == 1'b0)
                begin
                    rCts        <= 1'b0;
                    wData       <= 8'b0;
                    wEn         <= 8'b0;
                    wRts        <= 1'b0;
                    wClk        <= 1'b0;
                    xioState    <= `XIO_STATE_IDLE;
                    xioData     <= 32'b0;
                    xioCmd      <= 4'b0;
                end
            
            else
                if (cmdValid)
                    begin
                        xioData     <= data;
                        xioCmd      <= cmd;
                        xioState    <= `XIO_STATE_WRTS;
                    end
              
            else 
                case (xioState)
                    `XIO_STATE_IDLE:
                        begin
                            xioState        <= `XIO_STATE_IDLE;
                        end
                    
                    `XIO_STATE_WRTS:
                        begin
                            wRts            <= 1'b1;
                            xioState        <= `XIO_STATE_WCTS;
                        end
                    
                    `XIO_STATE_WCTS:
                        begin
                            if (wCts == 1'b1)
                                begin
                                    xioState    <= `XIO_STATE_CMD;
                                    wEn         <= 8'hff;
                                end
                        end
                 
                    `XIO_STATE_CMD:
                        begin
                            wData           <= {4'b0,cmd};
                            wClk            <= 1'b1;
                            xioState        <= `XIO_STATE_CLK;
                            case (cmd)
                                `XIO_CMD_SDRAM_READ:    xioNext     <= `XIO_STATE_B3;
                                default            :    xioNext     <= `XIO_STATE_DONE;
                            endcase;
                        end
                   
                    `XIO_STATE_CLK:
                        begin   
                            wClk            <= 1'b0;
                            xioState        <= xioNext;
                        end
                   
                    `XIO_STATE_B3:
                        begin   
                            wData           <= xioData[31:24];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B2;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B2:
                        begin   
                            wData           <= xioData[23:16];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B1;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B1:
                        begin   
                            wData           <= xioData[15:8];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B0;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B0:
                        begin   
                            wData           <= xioData[7:0];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_DONE;
                            xioState        <= `XIO_STATE_CLK;
                        end
                     
                    `XIO_STATE_DONE:
                        begin
                            wEn             <= 8'h0;
                            wRts            <= 1'b0;
                            xioState        <= `XIO_STATE_IDLE;
                        end
                      
                endcase
        end
        
endmodule
module xio_bus 
	(
    input   wire            clk,
    input   wire            rst_n,
    
  	input   wire 	[7:0] 	rData,
    input   wire            rRts,
    input   wire            rClk,
    output  reg             rCts,
    
  	output  reg 	[7:0] 	wData,
    output  reg     [7:0]   wEn,
    output  reg             wRts,
    output  reg             wClk,
    input   wire            wCts,
    
    input   wire    [31:0]  data,
    input   wire    [3:0]   cmd,
    input   wire            cmdValid
  	);


    reg [3:0]   xioState;
    reg [3:0]   xioNext;
    reg [31:0]  xioData;
    reg [3:0]   xioCmd;
    
    
    always @ (posedge clk)
        begin
            if (rst_n == 1'b0)
                begin
                    rCts        <= 1'b0;
                    wData       <= 8'b0;
                    wEn         <= 8'b0;
                    wRts        <= 1'b0;
                    wClk        <= 1'b0;
                    xioState    <= `XIO_STATE_IDLE;
                    xioData     <= 32'b0;
                    xioCmd      <= 4'b0;
                end
            
            else
                if (cmdValid)
                    begin
                        xioData     <= data;
                        xioCmd      <= cmd;
                        xioState    <= `XIO_STATE_WRTS;
                    end
              
            else 
                case (xioState)
                    `XIO_STATE_IDLE:
                        begin
                            xioState        <= `XIO_STATE_IDLE;
                        end
                    
                    `XIO_STATE_WRTS:
                        begin
                            wRts            <= 1'b1;
                            xioState        <= `XIO_STATE_WCTS;
                        end
                    
                    `XIO_STATE_WCTS:
                        begin
                            if (wCts == 1'b1)
                                begin
                                    xioState    <= `XIO_STATE_CMD;
                                    wEn         <= 8'hff;
                                end
                        end
                 
                    `XIO_STATE_CMD:
                        begin
                            wData           <= {4'b0,cmd};
                            wClk            <= 1'b1;
                            xioState        <= `XIO_STATE_CLK;
                            case (cmd)
                                `XIO_CMD_SDRAM_READ:    xioNext     <= `XIO_STATE_B3;
                                default            :    xioNext     <= `XIO_STATE_DONE;
                            endcase;
                        end
                   
                    `XIO_STATE_CLK:
                        begin   
                            wClk            <= 1'b0;
                            xioState        <= xioNext;
                        end
                   
                    `XIO_STATE_B3:
                        begin   
                            wData           <= xioData[31:24];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B2;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B2:
                        begin   
                            wData           <= xioData[23:16];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B1;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B1:
                        begin   
                            wData           <= xioData[15:8];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_B0;
                            xioState        <= `XIO_STATE_CLK;
                        end
                   
                    `XIO_STATE_B0:
                        begin   
                            wData           <= xioData[7:0];
                            wClk            <= 1'b1;
                            xioNext         <= `XIO_STATE_DONE;
                            xioState        <= `XIO_STATE_CLK;
                        end
                     
                    `XIO_STATE_DONE:
                        begin
                            wEn             <= 8'h0;
                            wRts            <= 1'b0;
                            xioState        <= `XIO_STATE_IDLE;
                        end
                      
                endcase
        end
        
endmodule