data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/imemrwpx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/imemrwpx.v:32: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/imemrwpx.v:56: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/imemrwpx.v:125: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    .q(do));\n       ^~\n%Error: Exiting due to 3 error(s)\n"
module imemrwpx
    (
     wrst,
     wrclk,
     wa,
     we,
     di,

     rrst,
     rdclk,
     ra,
     re,
     do,
     
     test,
     mask
     );

parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";
parameter NUMCLK= 1;

input               wrst;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst;
input               rdclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

(* KEEP = "true" *) reg [ADDRBIT-1:0]   iwa = {ADDRBIT{1'b0}};
(* KEEP = "true" *) reg                 iwe = 1'b0;
(* KEEP = "true" *) reg [WIDTH-1:0]     idi = {WIDTH{1'b0}};

(* KEEP = "true" *) reg [ADDRBIT-1:0]   ira = {ADDRBIT{1'b0}};

(* KEEP = "true" *) reg [ADDRBIT-1:0]   cnt = {ADDRBIT{1'b0}};



generate
if (MEM_RESET == "ON")
    begin: on_reset
always @ (posedge wrclk)
    if (wrst)
        begin
        cnt <= cnt + 1'b1;      
        iwa <= cnt;
        iwe <= 1'b1;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        cnt <= {ADDRBIT{1'b0}};
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end
    end
else
    begin: off_reset
always @ (posedge wrclk)
        begin
        iwe <= we;
        iwa <= wa;
        idi <= di;
        end
    end
endgenerate


always @ (posedge rdclk) ira <= ra;


`ifdef  RTL_SIMULATION
reg                 ire = {1{1'b0}};
wire [WIDTH-1:0]    ido;
reg [WIDTH-1:0]     do = {WIDTH{1'b0}};
always @ (posedge rdclk)  
    begin
    ire <= re;
    do <= ido;
    end
iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ire,ido,test,mask);

`else
alsyncram112x #(ADDRBIT,DEPTH,WIDTH,TYPE, MAXDEPTH) ram
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ira),
    .wrclock(wrclk),
    .rdclock(rdclk),
    .q(do));
`endif

endmodule
module imemrwpx
    (
     wrst,
     wrclk,
     wa,
     we,
     di,

     rrst,
     rdclk,
     ra,
     re,
     do,
     
     test,
     mask
     );


parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";
parameter NUMCLK= 1;

input               wrst;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst;
input               rdclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

(* KEEP = "true" *) reg [ADDRBIT-1:0]   iwa = {ADDRBIT{1'b0}};
(* KEEP = "true" *) reg                 iwe = 1'b0;
(* KEEP = "true" *) reg [WIDTH-1:0]     idi = {WIDTH{1'b0}};

(* KEEP = "true" *) reg [ADDRBIT-1:0]   ira = {ADDRBIT{1'b0}};

(* KEEP = "true" *) reg [ADDRBIT-1:0]   cnt = {ADDRBIT{1'b0}};



generate
if (MEM_RESET == "ON")
    begin: on_reset
always @ (posedge wrclk)
    if (wrst)
        begin
        cnt <= cnt + 1'b1;      
        iwa <= cnt;
        iwe <= 1'b1;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        cnt <= {ADDRBIT{1'b0}};
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end
    end
else
    begin: off_reset
always @ (posedge wrclk)
        begin
        iwe <= we;
        iwa <= wa;
        idi <= di;
        end
    end
endgenerate


always @ (posedge rdclk) ira <= ra;


`ifdef  RTL_SIMULATION
reg                 ire = {1{1'b0}};
wire [WIDTH-1:0]    ido;
reg [WIDTH-1:0]     do = {WIDTH{1'b0}};
always @ (posedge rdclk)  
    begin
    ire <= re;
    do <= ido;
    end
iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ire,ido,test,mask);

`else
alsyncram112x #(ADDRBIT,DEPTH,WIDTH,TYPE, MAXDEPTH) ram
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ira),
    .wrclock(wrclk),
    .rdclock(rdclk),
    .q(do));
`endif

endmodule