data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/DataMemoryMapper.v
1: b"%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/DataMemoryMapper.v:34: Cannot find file containing module: 'OnChipDataMemory'\n    OnChipDataMemory onChipDataMemory(\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess,data/full_repos/permissive/423012938/OnChipDataMemory\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess,data/full_repos/permissive/423012938/OnChipDataMemory.v\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess,data/full_repos/permissive/423012938/OnChipDataMemory.sv\n             OnChipDataMemory\n             OnChipDataMemory.v\n             OnChipDataMemory.sv\n             obj_dir/OnChipDataMemory\n             obj_dir/OnChipDataMemory.v\n             obj_dir/OnChipDataMemory.sv\n%Error: Exiting due to 1 error(s)\n"
module DataMemoryMapper (
    input [63:0] mr,
    input [63:0] mqb,
    input mwmem,
    input [2:0] mfunc3,
    input clk,

    output reg [63:0] md
);




    wire [63:0] onChipDataMemoryOut;
    wire onChipDataMemoryEnable = (~|mr[63:12]) & mr[11];
    wire onChipDataMemoryWriteEnable = onChipDataMemoryEnable & mwmem;
    OnChipDataMemory onChipDataMemory(
        mr[10:0],
        mqb,
        mfunc3[2],
        mfunc3[1:0],
        onChipDataMemoryWriteEnable,
        clk,
        onChipDataMemoryOut
    );



    always @(*) begin
        if (onChipDataMemoryEnable) begin
            md = onChipDataMemoryOut;
        end else begin
            md = 64'hx;
        end
    end

endmodule
module DataMemoryMapper (
    input [63:0] mr,
    input [63:0] mqb,
    input mwmem,
    input [2:0] mfunc3,
    input clk,

    output reg [63:0] md
);





    wire [63:0] onChipDataMemoryOut;
    wire onChipDataMemoryEnable = (~|mr[63:12]) & mr[11];
    wire onChipDataMemoryWriteEnable = onChipDataMemoryEnable & mwmem;
    OnChipDataMemory onChipDataMemory(
        mr[10:0],
        mqb,
        mfunc3[2],
        mfunc3[1:0],
        onChipDataMemoryWriteEnable,
        clk,
        onChipDataMemoryOut
    );



    always @(*) begin
        if (onChipDataMemoryEnable) begin
            md = onChipDataMemoryOut;
        end else begin
            md = 64'hx;
        end
    end

endmodule