data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/regrt_multiplexer.v
data/verilator_xmls/1927329b-4153-42d0-9ff0-4ced6f5898af.xml
module regrt_multiplexer(
    input [4:0] rt,
    input [4:0] rd,
    input regrt,
    output reg [4:0] dest_reg
    );
    always @(*) begin
        if (regrt == 0) begin
            dest_reg <= rd;
        end
        if (regrt == 1) begin
            dest_reg <= rt;
        end
    end
endmodule
module regrt_multiplexer(
    input [4:0] rt,
    input [4:0] rd,
    input regrt,
    output reg [4:0] dest_reg
    );

    always @(*) begin
        if (regrt == 0) begin
            dest_reg <= rd;
        end
        if (regrt == 1) begin
            dest_reg <= rt;
        end
    end
endmodule