data/full_repos/permissive/518791335/iiitb_pipo_tb.v
1: b'%Error: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("tb_out.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0, iiitb_pipo_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n#5 clear=1\'b1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5 clear=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b1001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b1010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b1011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b1110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b1111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#10 pi=4\'b0000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/518791335/iiitb_pipo_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\ninitial #150 $stop;\n        ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_pipo_tb;

reg clk;

reg clear;

reg [3:0] pi;

wire [3:0] po;

iiitb_pipo uut (.clk(clk),.clear(clear),.pi(pi),.po(po) );



initial begin

clk = 0;

clear = 0;

pi = 0;
$dumpfile("tb_out.vcd");
$dumpvars(0, iiitb_pipo_tb);

#5 clear=1'b1;

#5 clear=1'b0;

#10 pi=4'b1001;

#10 pi=4'b1010;

#10 pi=4'b1011;

#10 pi=4'b1110;

#10 pi=4'b1111;

#10 pi=4'b0000;

end

always #5 clk = ~clk;

initial #150 $stop;

endmodule
module iiitb_pipo_tb;


reg clk;

reg clear;

reg [3:0] pi;

wire [3:0] po;

iiitb_pipo uut (.clk(clk),.clear(clear),.pi(pi),.po(po) );



initial begin

clk = 0;

clear = 0;

pi = 0;
$dumpfile("tb_out.vcd");
$dumpvars(0, iiitb_pipo_tb);

#5 clear=1'b1;

#5 clear=1'b0;

#10 pi=4'b1001;

#10 pi=4'b1010;

#10 pi=4'b1011;

#10 pi=4'b1110;

#10 pi=4'b1111;

#10 pi=4'b0000;

end

always #5 clk = ~clk;

initial #150 $stop;

endmodule