data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/ewrapper_link_transmitter.v
1: b"%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/ewrapper_link_transmitter.v:114: Cannot find file containing module: 'synchronizer'\n   synchronizer #(.DW(2)) synchronizer(.out (txi_wait_sync[1:0]),\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/synchronizer\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/synchronizer.v\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/ewrapper_link_transmitter.v:123: Cannot find file containing module: 'ewrapper_link_txo'\n   ewrapper_link_txo txo( \n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/ewrapper_link_transmitter.v:192: Cannot find file containing module: 'fifo'\n   fifo #(.DW(104), .AW(2)) wrfifo_txo( \n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/ewrapper_link_transmitter.v:216: Cannot find file containing module: 'fifo'\n   fifo #(.DW(104), .AW(2)) rdfifo_txo( \n   ^~~~\n%Error: Exiting due to 4 error(s)\n"
module ewrapper_link_transmitter(

   emesh_wr_wait_inb, emesh_rd_wait_inb, tx_in,

   reset, txo_lclk, emesh_clk_inb, emesh_access_outb,
   emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
   emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
   txi_wr_wait, txi_rd_wait, burst_en
   );





   input          reset;
   input 	  txo_lclk;

   input 	  emesh_clk_inb;


   input 	  emesh_access_outb;
   input 	  emesh_write_outb;
   input [1:0] 	  emesh_datamode_outb;
   input [3:0] 	  emesh_ctrlmode_outb;
   input [31:0]   emesh_dstaddr_outb;
   input [31:0]   emesh_srcaddr_outb;
   input [31:0]   emesh_data_outb;   


   input 	  txi_wr_wait;
   input 	  txi_rd_wait;

   input 	  burst_en;





   output 	  emesh_wr_wait_inb;
   output 	  emesh_rd_wait_inb;


   output [71:0]  tx_in;







   reg 		  wrfifo_rd_en;
   



   wire [1:0] 	  txi_wait;
   wire [1:0] 	  txi_wait_sync;
   wire 	  txi_wr_wait_sync;
   wire 	  txi_rd_wait_sync;
   wire [103:0]   fifo_in;
   wire [103:0]   fifo_out;
   wire [107:0]   wrfifo_out;
   wire [107:0]   rdfifo_out;
   wire 	  wrfifo_wait;
   wire 	  rdfifo_wait;
   wire 	  wrfifo_rd_int;
   wire 	  rdfifo_rd_int;
   wire 	  wrfifo_rd;
   wire 	  rdfifo_rd;
   wire 	  wrfifo_wr;
   wire 	  rdfifo_wr;
   wire 	  rdfifo_empty;		
   wire 	  wrfifo_empty;	
   wire 	  txo_emesh_wait;	
   wire 	  txo_emesh_access;
   wire 	  txo_emesh_write;
   wire [1:0] 	  txo_emesh_datamode;
   wire [3:0] 	  txo_emesh_ctrlmode;
   wire [31:0] 	  txo_emesh_dstaddr;
   wire [31:0] 	  txo_emesh_srcaddr;
   wire [31:0] 	  txo_emesh_data;   






   assign txi_wait[1:0] = {txi_rd_wait,txi_wr_wait};
   assign txi_wr_wait_sync = txi_wait_sync[0];
   assign txi_rd_wait_sync = txi_wait_sync[1];

   synchronizer #(.DW(2)) synchronizer(.out	(txi_wait_sync[1:0]),
			               .in	(txi_wait[1:0]),
				       .clk	(txo_lclk),
				       .reset	(reset));





   ewrapper_link_txo txo(

			 .txo_emesh_wait	(txo_emesh_wait),
			 .tx_in			(tx_in[71:0]),

			 .reset			(reset),
			 .txo_lclk		(txo_lclk),
			 .txo_emesh_access	(txo_emesh_access),
			 .txo_emesh_write	(txo_emesh_write),
			 .txo_emesh_datamode	(txo_emesh_datamode[1:0]),
			 .txo_emesh_ctrlmode	(txo_emesh_ctrlmode[3:0]),
			 .txo_emesh_dstaddr	(txo_emesh_dstaddr[31:0]),
			 .txo_emesh_srcaddr	(txo_emesh_srcaddr[31:0]),
			 .txo_emesh_data	(txo_emesh_data[31:0]),
			 .burst_en		(burst_en));






   assign wrfifo_wr = emesh_access_outb & emesh_write_outb & ~emesh_wr_wait_inb;
   assign rdfifo_wr = emesh_access_outb &~emesh_write_outb & ~emesh_rd_wait_inb;


   assign wrfifo_rd_int = ~(wrfifo_empty | txi_wr_wait_sync | txo_emesh_wait);
   assign rdfifo_rd_int = ~(rdfifo_empty | txi_rd_wait_sync | txo_emesh_wait);


   always @ (posedge txo_lclk or posedge reset)
     if(reset)
       wrfifo_rd_en <= 1'b0;
     else
       wrfifo_rd_en <= ~wrfifo_rd_en;
   
   assign wrfifo_rd     = wrfifo_rd_int & ( wrfifo_rd_en | ~rdfifo_rd_int);
   assign rdfifo_rd     = rdfifo_rd_int & (~wrfifo_rd_en | ~wrfifo_rd_int);


   assign fifo_in[103:0] = {emesh_srcaddr_outb[31:0],
                            emesh_data_outb[31:0],
                            emesh_dstaddr_outb[31:0],
                            emesh_ctrlmode_outb[3:0],
                            emesh_datamode_outb[1:0],
                            emesh_write_outb,
                            emesh_access_outb};


   assign fifo_out[103:0] = wrfifo_rd ? wrfifo_out[103:0] : rdfifo_out[103:0];

   assign txo_emesh_access        = wrfifo_rd | rdfifo_rd;
   assign txo_emesh_write         = fifo_out[1];
   assign txo_emesh_datamode[1:0] = fifo_out[3:2];
   assign txo_emesh_ctrlmode[3:0] = fifo_out[7:4];
   assign txo_emesh_dstaddr[31:0] = fifo_out[39:8];
   assign txo_emesh_data[31:0]    = fifo_out[71:40];   
   assign txo_emesh_srcaddr[31:0] = fifo_out[103:72];



   fifo #(.DW(104), .AW(2)) wrfifo_txo(

				       .rd_data		(wrfifo_out[103:0]),
				       .rd_fifo_empty	(wrfifo_empty),
				       .wr_fifo_full	(emesh_wr_wait_inb),

				       .reset		(reset),
				       .wr_clk		(emesh_clk_inb),
				       .rd_clk		(txo_lclk),
				       .wr_write	(wrfifo_wr),
				       .wr_data		(fifo_in[103:0]),
				       .rd_read		(wrfifo_rd));



   fifo #(.DW(104), .AW(2)) rdfifo_txo(

				       .rd_data		(rdfifo_out[103:0]),
				       .rd_fifo_empty	(rdfifo_empty),
				       .wr_fifo_full	(emesh_rd_wait_inb),

				       .reset		(reset),
				       .wr_clk		(emesh_clk_inb),
				       .rd_clk		(txo_lclk),
				       .wr_write	(rdfifo_wr),
				       .wr_data		(fifo_in[103:0]),
				       .rd_read		(rdfifo_rd));




endmodule
module ewrapper_link_transmitter(

   emesh_wr_wait_inb, emesh_rd_wait_inb, tx_in,

   reset, txo_lclk, emesh_clk_inb, emesh_access_outb,
   emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
   emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
   txi_wr_wait, txi_rd_wait, burst_en
   );






   input          reset;
   input 	  txo_lclk;

   input 	  emesh_clk_inb;


   input 	  emesh_access_outb;
   input 	  emesh_write_outb;
   input [1:0] 	  emesh_datamode_outb;
   input [3:0] 	  emesh_ctrlmode_outb;
   input [31:0]   emesh_dstaddr_outb;
   input [31:0]   emesh_srcaddr_outb;
   input [31:0]   emesh_data_outb;   


   input 	  txi_wr_wait;
   input 	  txi_rd_wait;

   input 	  burst_en;





   output 	  emesh_wr_wait_inb;
   output 	  emesh_rd_wait_inb;


   output [71:0]  tx_in;







   reg 		  wrfifo_rd_en;
   



   wire [1:0] 	  txi_wait;
   wire [1:0] 	  txi_wait_sync;
   wire 	  txi_wr_wait_sync;
   wire 	  txi_rd_wait_sync;
   wire [103:0]   fifo_in;
   wire [103:0]   fifo_out;
   wire [107:0]   wrfifo_out;
   wire [107:0]   rdfifo_out;
   wire 	  wrfifo_wait;
   wire 	  rdfifo_wait;
   wire 	  wrfifo_rd_int;
   wire 	  rdfifo_rd_int;
   wire 	  wrfifo_rd;
   wire 	  rdfifo_rd;
   wire 	  wrfifo_wr;
   wire 	  rdfifo_wr;
   wire 	  rdfifo_empty;		
   wire 	  wrfifo_empty;	
   wire 	  txo_emesh_wait;	
   wire 	  txo_emesh_access;
   wire 	  txo_emesh_write;
   wire [1:0] 	  txo_emesh_datamode;
   wire [3:0] 	  txo_emesh_ctrlmode;
   wire [31:0] 	  txo_emesh_dstaddr;
   wire [31:0] 	  txo_emesh_srcaddr;
   wire [31:0] 	  txo_emesh_data;   






   assign txi_wait[1:0] = {txi_rd_wait,txi_wr_wait};
   assign txi_wr_wait_sync = txi_wait_sync[0];
   assign txi_rd_wait_sync = txi_wait_sync[1];

   synchronizer #(.DW(2)) synchronizer(.out	(txi_wait_sync[1:0]),
			               .in	(txi_wait[1:0]),
				       .clk	(txo_lclk),
				       .reset	(reset));





   ewrapper_link_txo txo(

			 .txo_emesh_wait	(txo_emesh_wait),
			 .tx_in			(tx_in[71:0]),

			 .reset			(reset),
			 .txo_lclk		(txo_lclk),
			 .txo_emesh_access	(txo_emesh_access),
			 .txo_emesh_write	(txo_emesh_write),
			 .txo_emesh_datamode	(txo_emesh_datamode[1:0]),
			 .txo_emesh_ctrlmode	(txo_emesh_ctrlmode[3:0]),
			 .txo_emesh_dstaddr	(txo_emesh_dstaddr[31:0]),
			 .txo_emesh_srcaddr	(txo_emesh_srcaddr[31:0]),
			 .txo_emesh_data	(txo_emesh_data[31:0]),
			 .burst_en		(burst_en));






   assign wrfifo_wr = emesh_access_outb & emesh_write_outb & ~emesh_wr_wait_inb;
   assign rdfifo_wr = emesh_access_outb &~emesh_write_outb & ~emesh_rd_wait_inb;


   assign wrfifo_rd_int = ~(wrfifo_empty | txi_wr_wait_sync | txo_emesh_wait);
   assign rdfifo_rd_int = ~(rdfifo_empty | txi_rd_wait_sync | txo_emesh_wait);


   always @ (posedge txo_lclk or posedge reset)
     if(reset)
       wrfifo_rd_en <= 1'b0;
     else
       wrfifo_rd_en <= ~wrfifo_rd_en;
   
   assign wrfifo_rd     = wrfifo_rd_int & ( wrfifo_rd_en | ~rdfifo_rd_int);
   assign rdfifo_rd     = rdfifo_rd_int & (~wrfifo_rd_en | ~wrfifo_rd_int);


   assign fifo_in[103:0] = {emesh_srcaddr_outb[31:0],
                            emesh_data_outb[31:0],
                            emesh_dstaddr_outb[31:0],
                            emesh_ctrlmode_outb[3:0],
                            emesh_datamode_outb[1:0],
                            emesh_write_outb,
                            emesh_access_outb};


   assign fifo_out[103:0] = wrfifo_rd ? wrfifo_out[103:0] : rdfifo_out[103:0];

   assign txo_emesh_access        = wrfifo_rd | rdfifo_rd;
   assign txo_emesh_write         = fifo_out[1];
   assign txo_emesh_datamode[1:0] = fifo_out[3:2];
   assign txo_emesh_ctrlmode[3:0] = fifo_out[7:4];
   assign txo_emesh_dstaddr[31:0] = fifo_out[39:8];
   assign txo_emesh_data[31:0]    = fifo_out[71:40];   
   assign txo_emesh_srcaddr[31:0] = fifo_out[103:72];



   fifo #(.DW(104), .AW(2)) wrfifo_txo(

				       .rd_data		(wrfifo_out[103:0]),
				       .rd_fifo_empty	(wrfifo_empty),
				       .wr_fifo_full	(emesh_wr_wait_inb),

				       .reset		(reset),
				       .wr_clk		(emesh_clk_inb),
				       .rd_clk		(txo_lclk),
				       .wr_write	(wrfifo_wr),
				       .wr_data		(fifo_in[103:0]),
				       .rd_read		(wrfifo_rd));



   fifo #(.DW(104), .AW(2)) rdfifo_txo(

				       .rd_data		(rdfifo_out[103:0]),
				       .rd_fifo_empty	(rdfifo_empty),
				       .wr_fifo_full	(emesh_rd_wait_inb),

				       .reset		(reset),
				       .wr_clk		(emesh_clk_inb),
				       .rd_clk		(txo_lclk),
				       .wr_write	(rdfifo_wr),
				       .wr_data		(fifo_in[103:0]),
				       .rd_read		(rdfifo_rd));




endmodule