data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlint115wrp.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlint115wrp.v:150: Cannot find file containing module: \'fflopx\'\nfflopx #(2+2*CHAW+2*CHDW) ppchram (iclk,rst,{chwe,chwa,chwrd,chre,chra,ichrdd},{ochwe,ochwa,ochwrd,ochre,ochra,chrdd});\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlint115wrp.v:168: Cannot find file containing module: \'fflopx\'\nfflopx #(3) alrmrestpli\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlint115wrp.v:198: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                                                       : ... In instance at6rtlint115wrp\n                alrmrestcnt     <= {SEGB{1\'b0}};\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlint115wrp.v:284: Cannot find file containing module: \'at6rtlint113\'\nat6rtlint113  #(STYW,STAW,STCHEW,SEGB,BITB,BITNUM,SEGNUM,UPW) at6rtlintxi    \n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module at6rtlint115wrp
    (
     iclk,
     rst,
     ipactive,

     ialrmrest,

     iupen,
     iupa,
     iupws,
     iuprs,
     iupdi,
     ouprdy,
     oupdo,
     oupint,

     idtvl,
     isegid,
     ibitid,
     
     istyreq,
     ista,
     ista_msk,
     ista_chgen,
     iinttypeen,
     

     ochwe,
     ochwa,     
     ochwrd,    
     ochre,
     ochra,
     ichrdd,


     osegwe,
     osegwa,
     osegwrd,
     osegre,
     osegra,
     isegrdd
     );




parameter   STYW        = 5;
parameter   STAW        = 5;
parameter   STCHEW      = 5;

parameter   SEGB        = 4;
parameter   BITB        = 5;

parameter   BITNUM      = 32;
parameter   SEGNUM      = 12;

parameter   UPW         = 32;

parameter   UPA         = SEGB + BITB + 2;

parameter   CHAW        = SEGB + BITB;
parameter   CHDW        = 2*STYW + STAW;

parameter   SEGAW       = SEGB;
parameter   SEGDW       = BITNUM;



input               iclk;
input               rst;
input               ipactive;

input               ialrmrest;

input               iupen;
input [UPA-1:0]     iupa;
input               iupws;
input               iuprs;
input [UPW-1:0]     iupdi;
output              ouprdy;
output [UPW-1:0]    oupdo;
output              oupint;

input               idtvl;
input [SEGB-1:0]    isegid;
input [BITB-1:0]    ibitid;
input [STYW-1:0]    istyreq;
input [STAW-1:0]    ista;


input [STAW-1:0]    ista_msk;
input [STCHEW-1:0]  ista_chgen;

input [STYW-1:0]    iinttypeen;








output              ochwe;
output [CHAW-1:0]   ochwa;
output [CHDW-1:0]   ochwrd;
output              ochre;
output [CHAW-1:0]   ochra;
input [CHDW-1:0]    ichrdd;






output              osegwe;
output [SEGAW-1:0]  osegwa;
output [SEGDW-1:0]  osegwrd;
output              osegre;
output [SEGAW-1:0]  osegra;
input [SEGDW-1:0]   isegrdd;









wire                chwe;
wire   [CHAW-1:0]   chwa;
wire   [CHDW-1:0]   chwrd;
wire                chre;
wire   [CHAW-1:0]   chra;
wire  [CHDW-1:0]    chrdd;
fflopx #(2+2*CHAW+2*CHDW) ppchram (iclk,rst,{chwe,chwa,chwrd,chre,chra,ichrdd},{ochwe,ochwa,ochwrd,ochre,ochra,chrdd});



parameter   IDLE        = 4'd0;
parameter   PREREAD     = 4'd1;
parameter   WAIT1       = 4'd2;
parameter   WAIT2       = 4'd3;
parameter   WAIT3       = 4'd4;
parameter   WAIT4       = 4'd5;
parameter   WAIT5       = 4'd6;
parameter   CLEARSTA    = 4'd7;
parameter   SETSTK      = 4'd8;

parameter   CNTB        = BITB + SEGB;

wire [2:0]         alrmrestpl;

fflopx #(3) alrmrestpli
    (iclk,rst,{alrmrestpl[1:0],ialrmrest},alrmrestpl);

wire                alrmrestpos  = alrmrestpl[1] & (!alrmrestpl[2]);

reg [CNTB-1:0]      alrmrestcnt = 0;
reg                 dtvli;
reg [SEGB-1:0]      segidi;
reg [BITB-1:0]      bitidi;

reg [STYW-1:0]      styreqi;
reg [STAW-1:0]      stai;
reg [STAW-1:0]      stalat;
reg [STAW-1:0]      sta_mski;
reg [STCHEW-1:0]    sta_chgeni;
reg [STYW-1:0]      inttypeen;

reg [3:0]           alrmreststate = 4'd0;

wire               alrmregvl    = |{alrmrestcnt,alrmrestpos};



always @(posedge iclk)
    begin

        case(alrmreststate)
            IDLE:
                begin
                alrmreststate   <= alrmrestpos ? PREREAD : IDLE;
                alrmrestcnt     <= {SEGB{1'b0}};
                dtvli       <= idtvl;
                segidi      <= isegid;
                bitidi      <= ibitid;
                styreqi     <= istyreq;
                stai        <= ista;
                sta_mski    <= ista_msk;
                sta_chgeni  <= ista_chgen;
                inttypeen   <= iinttypeen;              
                end
            PREREAD:
                begin
                dtvli       <= 1'b1;
                segidi      <= alrmrestcnt[CNTB-1:BITB];
                bitidi      <= alrmrestcnt[BITB-1:0];
                styreqi     <= {STYW{1'b0}};
                stai        <= {STAW{1'b0}};
                sta_mski    <= {STAW{1'b0}};
                sta_chgeni  <= {STCHEW{1'b1}};
                inttypeen   <= {STYW{1'b1}};                
                
                alrmreststate   <= WAIT1;
                end
            WAIT1:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT2;
                end
            WAIT2:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT3;
                end
            WAIT3:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT4;
                end
            WAIT4:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT5;
                end
            WAIT5:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= CLEARSTA;
                end
            CLEARSTA:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt[CNTB-1:BITB];
                bitidi          <= alrmrestcnt[BITB-1:0];
                styreqi         <= {STYW{1'b0}};
                stai            <= {STAW{1'b0}};
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                stalat          <= chrdd[STYW+STAW-1:STYW];
                alrmreststate   <= SETSTK;
                end
            SETSTK:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt[CNTB-1:BITB];
                bitidi          <= alrmrestcnt[BITB-1:0];
                styreqi         <= {STYW{1'b0}};
                stai            <= stalat;
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                alrmreststate   <= &alrmrestcnt ? IDLE: PREREAD;
                
                alrmrestcnt     <= alrmrestcnt + 1'b1;
                end
            default:
                begin
                alrmreststate   <= IDLE;
                dtvli           <= 1'b0;
                end
        endcase
        
    end

at6rtlint113  #(STYW,STAW,STCHEW,SEGB,BITB,BITNUM,SEGNUM,UPW) at6rtlintxi    
    (
     .iclk      (iclk),
     .rst       (rst),
     .ipactive  (ipactive),

     .iupen     (iupen),
     .iupa      (iupa),
     .iupws     (iupws),
     .iuprs     (iuprs),
     .iupdi     (iupdi),
     .ouprdy    (ouprdy),
     .oupdo     (oupdo),
     .oupint    (oupint),

     .idtvl     (dtvli),
     .isegid    (segidi),
     .ibitid    (bitidi),
    
     .istyreq   (styreqi),
     .ista      (stai),
     .ista_msk  (sta_mski),
     .ista_chgen(sta_chgeni),
     .iinttypeen(inttypeen),


     .ochwe     (chwe),
     .ochwa     (chwa),     
     .ochwrd    (chwrd),    
     .ochre     (chre),
     .ochra     (chra),
     .ichrdd    (chrdd),


     .osegwe    (osegwe),
     .osegwa    (osegwa),
     .osegwrd   (osegwrd),
     .osegre    (osegre),
     .osegra    (osegra),
     .isegrdd   (isegrdd)
     );


endmodule
module at6rtlint115wrp
    (
     iclk,
     rst,
     ipactive,

     ialrmrest,

     iupen,
     iupa,
     iupws,
     iuprs,
     iupdi,
     ouprdy,
     oupdo,
     oupint,

     idtvl,
     isegid,
     ibitid,
     
     istyreq,
     ista,
     ista_msk,
     ista_chgen,
     iinttypeen,
     

     ochwe,
     ochwa,     
     ochwrd,    
     ochre,
     ochra,
     ichrdd,


     osegwe,
     osegwa,
     osegwrd,
     osegre,
     osegra,
     isegrdd
     );





parameter   STYW        = 5;
parameter   STAW        = 5;
parameter   STCHEW      = 5;

parameter   SEGB        = 4;
parameter   BITB        = 5;

parameter   BITNUM      = 32;
parameter   SEGNUM      = 12;

parameter   UPW         = 32;

parameter   UPA         = SEGB + BITB + 2;

parameter   CHAW        = SEGB + BITB;
parameter   CHDW        = 2*STYW + STAW;

parameter   SEGAW       = SEGB;
parameter   SEGDW       = BITNUM;



input               iclk;
input               rst;
input               ipactive;

input               ialrmrest;

input               iupen;
input [UPA-1:0]     iupa;
input               iupws;
input               iuprs;
input [UPW-1:0]     iupdi;
output              ouprdy;
output [UPW-1:0]    oupdo;
output              oupint;

input               idtvl;
input [SEGB-1:0]    isegid;
input [BITB-1:0]    ibitid;
input [STYW-1:0]    istyreq;
input [STAW-1:0]    ista;


input [STAW-1:0]    ista_msk;
input [STCHEW-1:0]  ista_chgen;

input [STYW-1:0]    iinttypeen;








output              ochwe;
output [CHAW-1:0]   ochwa;
output [CHDW-1:0]   ochwrd;
output              ochre;
output [CHAW-1:0]   ochra;
input [CHDW-1:0]    ichrdd;






output              osegwe;
output [SEGAW-1:0]  osegwa;
output [SEGDW-1:0]  osegwrd;
output              osegre;
output [SEGAW-1:0]  osegra;
input [SEGDW-1:0]   isegrdd;









wire                chwe;
wire   [CHAW-1:0]   chwa;
wire   [CHDW-1:0]   chwrd;
wire                chre;
wire   [CHAW-1:0]   chra;
wire  [CHDW-1:0]    chrdd;
fflopx #(2+2*CHAW+2*CHDW) ppchram (iclk,rst,{chwe,chwa,chwrd,chre,chra,ichrdd},{ochwe,ochwa,ochwrd,ochre,ochra,chrdd});



parameter   IDLE        = 4'd0;
parameter   PREREAD     = 4'd1;
parameter   WAIT1       = 4'd2;
parameter   WAIT2       = 4'd3;
parameter   WAIT3       = 4'd4;
parameter   WAIT4       = 4'd5;
parameter   WAIT5       = 4'd6;
parameter   CLEARSTA    = 4'd7;
parameter   SETSTK      = 4'd8;

parameter   CNTB        = BITB + SEGB;

wire [2:0]         alrmrestpl;

fflopx #(3) alrmrestpli
    (iclk,rst,{alrmrestpl[1:0],ialrmrest},alrmrestpl);

wire                alrmrestpos  = alrmrestpl[1] & (!alrmrestpl[2]);

reg [CNTB-1:0]      alrmrestcnt = 0;
reg                 dtvli;
reg [SEGB-1:0]      segidi;
reg [BITB-1:0]      bitidi;

reg [STYW-1:0]      styreqi;
reg [STAW-1:0]      stai;
reg [STAW-1:0]      stalat;
reg [STAW-1:0]      sta_mski;
reg [STCHEW-1:0]    sta_chgeni;
reg [STYW-1:0]      inttypeen;

reg [3:0]           alrmreststate = 4'd0;

wire               alrmregvl    = |{alrmrestcnt,alrmrestpos};



always @(posedge iclk)
    begin

        case(alrmreststate)
            IDLE:
                begin
                alrmreststate   <= alrmrestpos ? PREREAD : IDLE;
                alrmrestcnt     <= {SEGB{1'b0}};
                dtvli       <= idtvl;
                segidi      <= isegid;
                bitidi      <= ibitid;
                styreqi     <= istyreq;
                stai        <= ista;
                sta_mski    <= ista_msk;
                sta_chgeni  <= ista_chgen;
                inttypeen   <= iinttypeen;              
                end
            PREREAD:
                begin
                dtvli       <= 1'b1;
                segidi      <= alrmrestcnt[CNTB-1:BITB];
                bitidi      <= alrmrestcnt[BITB-1:0];
                styreqi     <= {STYW{1'b0}};
                stai        <= {STAW{1'b0}};
                sta_mski    <= {STAW{1'b0}};
                sta_chgeni  <= {STCHEW{1'b1}};
                inttypeen   <= {STYW{1'b1}};                
                
                alrmreststate   <= WAIT1;
                end
            WAIT1:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT2;
                end
            WAIT2:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT3;
                end
            WAIT3:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT4;
                end
            WAIT4:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT5;
                end
            WAIT5:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= CLEARSTA;
                end
            CLEARSTA:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt[CNTB-1:BITB];
                bitidi          <= alrmrestcnt[BITB-1:0];
                styreqi         <= {STYW{1'b0}};
                stai            <= {STAW{1'b0}};
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                stalat          <= chrdd[STYW+STAW-1:STYW];
                alrmreststate   <= SETSTK;
                end
            SETSTK:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt[CNTB-1:BITB];
                bitidi          <= alrmrestcnt[BITB-1:0];
                styreqi         <= {STYW{1'b0}};
                stai            <= stalat;
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                alrmreststate   <= &alrmrestcnt ? IDLE: PREREAD;
                
                alrmrestcnt     <= alrmrestcnt + 1'b1;
                end
            default:
                begin
                alrmreststate   <= IDLE;
                dtvli           <= 1'b0;
                end
        endcase
        
    end

at6rtlint113  #(STYW,STAW,STCHEW,SEGB,BITB,BITNUM,SEGNUM,UPW) at6rtlintxi    
    (
     .iclk      (iclk),
     .rst       (rst),
     .ipactive  (ipactive),

     .iupen     (iupen),
     .iupa      (iupa),
     .iupws     (iupws),
     .iuprs     (iuprs),
     .iupdi     (iupdi),
     .ouprdy    (ouprdy),
     .oupdo     (oupdo),
     .oupint    (oupint),

     .idtvl     (dtvli),
     .isegid    (segidi),
     .ibitid    (bitidi),
    
     .istyreq   (styreqi),
     .ista      (stai),
     .ista_msk  (sta_mski),
     .ista_chgen(sta_chgeni),
     .iinttypeen(inttypeen),


     .ochwe     (chwe),
     .ochwa     (chwa),     
     .ochwrd    (chwrd),    
     .ochre     (chre),
     .ochra     (chra),
     .ichrdd    (chrdd),


     .osegwe    (osegwe),
     .osegwa    (osegwa),
     .osegwrd   (osegwrd),
     .osegre    (osegre),
     .osegra    (osegra),
     .isegrdd   (isegrdd)
     );


endmodule