data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:22: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_hundreds = val_p / 12\'d100;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:23: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_tens = (val_p / 12\'d10) % 12\'d10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:24: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_ones = val_p % 12\'d10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:28: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_hundreds = val_i / 12\'d100;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_tens = (val_i / 12\'d10) % 12\'d10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:30: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_ones = val_i % 12\'d10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:34: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_hundreds = val_d / 12\'d100;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:35: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_tens = (val_d / 12\'d10) % 12\'d10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:36: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 12 bits.\n                                                                                       : ... In instance seg7_act_val\n   res_ones = val_d % 12\'d10;  \n            ^\n%Error: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:44: Cannot find file containing module: \'seven_segment\'\nseven_segment hundreds(res_hundreds, seg7_hundreds);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment.v\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment.sv\n             seven_segment\n             seven_segment.v\n             seven_segment.sv\n             obj_dir/seven_segment\n             obj_dir/seven_segment.v\n             obj_dir/seven_segment.sv\n%Error: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:45: Cannot find file containing module: \'seven_segment\'\nseven_segment tens(res_tens, seg7_tens);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/three_decimal_vals_w_neg.v:46: Cannot find file containing module: \'seven_segment\'\nseven_segment ones(res_ones, seg7_ones);\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module seg7_act_val (
input [11:0]val_p,
input [11:0]val_i,
input [11:0]val_d,
input [2:0]switch_k,
output [6:0]seg7_hundreds,
output [6:0]seg7_tens,
output [6:0]seg7_ones
);

reg [3:0]res_hundreds;
reg [3:0]res_tens;
reg [3:0]res_ones;


always @(*)
begin

	case (switch_k)
	3'b100:
		begin
			res_hundreds = val_p / 12'd100;
			res_tens = (val_p / 12'd10) % 12'd10;
			res_ones = val_p % 12'd10;
		end
	3'b010:
		begin
			res_hundreds = val_i / 12'd100;
			res_tens = (val_i / 12'd10) % 12'd10;
			res_ones = val_i % 12'd10;
		end
	3'b001:
		begin
			res_hundreds = val_d / 12'd100;
			res_tens = (val_d / 12'd10) % 12'd10;
			res_ones = val_d % 12'd10;		
		end
		
	endcase

end


seven_segment hundreds(res_hundreds, seg7_hundreds);
seven_segment tens(res_tens, seg7_tens);
seven_segment ones(res_ones, seg7_ones);

endmodule
module seg7_act_val (
input [11:0]val_p,
input [11:0]val_i,
input [11:0]val_d,
input [2:0]switch_k,
output [6:0]seg7_hundreds,
output [6:0]seg7_tens,
output [6:0]seg7_ones
);


reg [3:0]res_hundreds;
reg [3:0]res_tens;
reg [3:0]res_ones;


always @(*)
begin

	case (switch_k)
	3'b100:
		begin
			res_hundreds = val_p / 12'd100;
			res_tens = (val_p / 12'd10) % 12'd10;
			res_ones = val_p % 12'd10;
		end
	3'b010:
		begin
			res_hundreds = val_i / 12'd100;
			res_tens = (val_i / 12'd10) % 12'd10;
			res_ones = val_i % 12'd10;
		end
	3'b001:
		begin
			res_hundreds = val_d / 12'd100;
			res_tens = (val_d / 12'd10) % 12'd10;
			res_ones = val_d % 12'd10;		
		end
		
	endcase

end


seven_segment hundreds(res_hundreds, seg7_hundreds);
seven_segment tens(res_tens, seg7_tens);
seven_segment ones(res_ones, seg7_ones);

endmodule