data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module entropy_RO #(parameter nRO = 40 )(
    input clk_dff,
    output o_RO_out,
    output o_xor_out_ROs_sampled,
    output o_xor_out_ROs_analog    
    );
    
    wire [nRO:1] ro_out;
    wire [nRO:1] ro_out_sampled;
    wire xor_out_sampled;  
    wire xor_out_analog;

    assign o_RO_out = ro_out[1];
    assign o_xor_out_ROs_sampled = xor_out_sampled;
    assign o_xor_out_ROs_analog = xor_out_analog;

    genvar i;
    generate
    for (i=nRO; i>=1; i=i-1)begin
        ring_osc RO_gen(.osc_out(ro_out[i]));
        mydff dff_gen(.clk(clk_dff), .D(ro_out[i]), .Q(ro_out_sampled[i]));
    end
    endgenerate

    multi_xor #(
    .length(nRO)
    )xor_stage(
    .ros_i(ro_out_sampled),
    .rosx(xor_out_sampled)
    ); 
    
    multi_xor #(
    .length(nRO)
    )xor_stage_analog(
    .ros_i(ro_out),
    .rosx(xor_out_analog)
    );
endmodule
module entropy_RO #(parameter nRO = 40 )(
    input clk_dff,
    output o_RO_out,
    output o_xor_out_ROs_sampled,
    output o_xor_out_ROs_analog    
    );

    
    wire [nRO:1] ro_out;
    wire [nRO:1] ro_out_sampled;
    wire xor_out_sampled;  
    wire xor_out_analog;

    assign o_RO_out = ro_out[1];
    assign o_xor_out_ROs_sampled = xor_out_sampled;
    assign o_xor_out_ROs_analog = xor_out_analog;

    genvar i;
    generate
    for (i=nRO; i>=1; i=i-1)begin
        ring_osc RO_gen(.osc_out(ro_out[i]));
        mydff dff_gen(.clk(clk_dff), .D(ro_out[i]), .Q(ro_out_sampled[i]));
    end
    endgenerate

    multi_xor #(
    .length(nRO)
    )xor_stage(
    .ros_i(ro_out_sampled),
    .rosx(xor_out_sampled)
    ); 
    
    multi_xor #(
    .length(nRO)
    )xor_stage_analog(
    .ros_i(ro_out),
    .rosx(xor_out_analog)
    );
endmodule