data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds4Tester/sbt/SmallOdds4Tester.v
data/verilator_xmls/3969c62e-f779-4158-84d0-b8802f2d9927.xml
module SmallOdds4Tester(
  input   clock,
  input   reset
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  device_under_test_clock;
  wire  device_under_test_reset;
  wire  device_under_test_io_in_ready;
  wire  device_under_test_io_in_valid;
  wire [31:0] device_under_test_io_in_bits;
  wire  device_under_test_io_out_ready;
  wire  device_under_test_io_out_valid;
  wire [31:0] device_under_test_io_out_bits;
  reg [6:0] _T_4;
  reg  _T_7;
  reg [4:0] _T_10;
  reg  _T_13;
  wire  _T_14 = _T_7 & _T_13;
  wire  _T_16 = ~reset;
  reg [11:0] _T_21;
  wire [11:0] _T_24 = _T_21 + 12'h1;
  wire  _T_26 = _T_21 > 12'hfa0;
  reg [4:0] value;
  wire [4:0] _GEN_1 = 5'h1 == value ? 5'h8 : 5'h3;
  wire [4:0] _GEN_2 = 5'h2 == value ? 5'h4 : _GEN_1;
  wire [4:0] _GEN_3 = 5'h3 == value ? 5'h7 : _GEN_2;
  wire [4:0] _GEN_4 = 5'h4 == value ? 5'hc : _GEN_3;
  wire [4:0] _GEN_5 = 5'h5 == value ? 5'h0 : _GEN_4;
  wire [4:0] _GEN_6 = 5'h6 == value ? 5'h3 : _GEN_5;
  wire [4:0] _GEN_7 = 5'h7 == value ? 5'h2 : _GEN_6;
  wire [4:0] _GEN_8 = 5'h8 == value ? 5'hc : _GEN_7;
  wire [4:0] _GEN_9 = 5'h9 == value ? 5'h3 : _GEN_8;
  wire [4:0] _GEN_10 = 5'ha == value ? 5'h5 : _GEN_9;
  wire [4:0] _GEN_11 = 5'hb == value ? 5'h5 : _GEN_10;
  wire [4:0] _GEN_12 = 5'hc == value ? 5'h11 : _GEN_11;
  wire [4:0] _GEN_13 = 5'hd == value ? 5'h7 : _GEN_12;
  wire [4:0] _GEN_14 = 5'he == value ? 5'h2 : _GEN_13;
  wire [4:0] _GEN_15 = 5'hf == value ? 5'h2 : _GEN_14;
  wire [4:0] _GEN_16 = 5'h10 == value ? 5'h5 : _GEN_15;
  wire [4:0] _GEN_17 = 5'h11 == value ? 5'hd : _GEN_16;
  wire [4:0] _GEN_18 = 5'h12 == value ? 5'h12 : _GEN_17;
  wire [4:0] _GEN_19 = 5'h13 == value ? 5'hf : _GEN_18;
  wire [4:0] _GEN_20 = 5'h14 == value ? 5'h0 : _GEN_19;
  wire [4:0] _GEN_21 = 5'h15 == value ? 5'hf : _GEN_20;
  wire [4:0] _GEN_22 = 5'h16 == value ? 5'hf : _GEN_21;
  wire [4:0] _GEN_23 = 5'h17 == value ? 5'ha : _GEN_22;
  wire [4:0] _GEN_24 = 5'h18 == value ? 5'h12 : _GEN_23;
  wire [4:0] _GEN_25 = 5'h19 == value ? 5'hb : _GEN_24;
  wire [4:0] _GEN_26 = 5'h1a == value ? 5'he : _GEN_25;
  wire [4:0] _GEN_27 = 5'h1b == value ? 5'h10 : _GEN_26;
  wire [4:0] _GEN_28 = 5'h1c == value ? 5'hc : _GEN_27;
  wire [4:0] _GEN_29 = 5'h1d == value ? 5'h2 : _GEN_28;
  wire [4:0] _GEN_30 = 5'h1e == value ? 5'h13 : _GEN_29;
  wire [4:0] _GEN_31 = 5'h1f == value ? 5'h0 : _GEN_30;
  wire  _T_177 = value == 5'h1e;
  wire [4:0] _T_180 = value + 5'h1;
  wire  _GEN_65 = _T_4 == 7'h1e | _T_7;
  wire [6:0] _T_189 = _T_4 + 7'h1;
  reg [2:0] value_1;
  wire  _GEN_79 = 5'h8 == _T_10 ? 1'h0 : 1'h1;
  wire  _GEN_80 = 5'h9 == _T_10 ? 1'h0 : _GEN_79;
  wire  _GEN_81 = 5'ha == _T_10 ? 1'h0 : _GEN_80;
  wire  _GEN_82 = 5'hb == _T_10 ? 1'h0 : _GEN_81;
  wire  _GEN_83 = 5'hc == _T_10 ? 1'h0 : _GEN_82;
  wire  _GEN_84 = 5'hd == _T_10 ? 1'h0 : _GEN_83;
  wire  _GEN_85 = 5'he == _T_10 ? 1'h0 : _GEN_84;
  wire  _GEN_86 = 5'hf == _T_10 ? 1'h0 : _GEN_85;
  wire  _GEN_87 = 5'h10 == _T_10 ? 1'h0 : _GEN_86;
  wire  _GEN_88 = 5'h11 == _T_10 ? 1'h0 : _GEN_87;
  wire  _GEN_89 = 5'h12 == _T_10 ? 1'h0 : _GEN_88;
  wire  _GEN_90 = 5'h13 == _T_10 ? 1'h0 : _GEN_89;
  wire  _GEN_91 = 5'h14 == _T_10 ? 1'h0 : _GEN_90;
  wire  _GEN_92 = 5'h15 == _T_10 ? 1'h0 : _GEN_91;
  wire  _GEN_93 = 5'h16 == _T_10 ? 1'h0 : _GEN_92;
  wire  _GEN_94 = 5'h17 == _T_10 ? 1'h0 : _GEN_93;
  wire  _GEN_95 = 5'h18 == _T_10 ? 1'h0 : _GEN_94;
  wire  _GEN_96 = 5'h19 == _T_10 ? 1'h0 : _GEN_95;
  wire  _GEN_97 = 5'h1a == _T_10 ? 1'h0 : _GEN_96;
  wire  _GEN_98 = 5'h1b == _T_10 ? 1'h0 : _GEN_97;
  wire  _GEN_99 = 5'h1c == _T_10 ? 1'h0 : _GEN_98;
  wire  _GEN_100 = 5'h1d == _T_10 ? 1'h0 : _GEN_99;
  wire  _GEN_101 = 5'h1e == _T_10 ? 1'h0 : _GEN_100;
  wire  _T_285 = device_under_test_io_out_ready & device_under_test_io_out_valid;
  wire [2:0] _GEN_104 = 3'h1 == value_1 ? 3'h7 : 3'h3;
  wire [2:0] _GEN_105 = 3'h2 == value_1 ? 3'h3 : _GEN_104;
  wire [2:0] _GEN_106 = 3'h3 == value_1 ? 3'h3 : _GEN_105;
  wire [2:0] _GEN_107 = 3'h4 == value_1 ? 3'h5 : _GEN_106;
  wire [2:0] _GEN_108 = 3'h5 == value_1 ? 3'h5 : _GEN_107;
  wire [2:0] _GEN_109 = 3'h6 == value_1 ? 3'h7 : _GEN_108;
  wire [2:0] _GEN_110 = 3'h7 == value_1 ? 3'h5 : _GEN_109;
  wire [3:0] _GEN_118 = {{1'd0}, value_1};
  wire [2:0] _GEN_111 = 4'h8 == _GEN_118 ? 3'h0 : _GEN_110;
  wire [31:0] _GEN_119 = {{29'd0}, _GEN_111};
  wire  _T_290 = device_under_test_io_out_bits != _GEN_119;
  wire [2:0] _T_304 = value_1 + 3'h1;
  wire  _GEN_112 = _T_10 == 5'h7 | _T_13;
  wire [4:0] _T_312 = _T_10 + 5'h1;
  wire  _GEN_121 = _T_285 & _T_290;
  SmallOdds4 device_under_test (
    .clock(device_under_test_clock),
    .reset(device_under_test_reset),
    .io_in_ready(device_under_test_io_in_ready),
    .io_in_valid(device_under_test_io_in_valid),
    .io_in_bits(device_under_test_io_in_bits),
    .io_out_ready(device_under_test_io_out_ready),
    .io_out_valid(device_under_test_io_out_valid),
    .io_out_bits(device_under_test_io_out_bits)
  );
  assign device_under_test_clock = clock;
  assign device_under_test_reset = reset;
  assign device_under_test_io_in_valid = 5'h1f == _T_4[4:0] ? 1'h0 : 1'h1;
  assign device_under_test_io_in_bits = {{27'd0}, _GEN_31};
  assign device_under_test_io_out_ready = 5'h1f == _T_10 ? 1'h0 : _GEN_101;
  always @(posedge clock) begin
    if (reset) begin
      _T_4 <= 7'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (~_T_7) begin
        _T_4 <= _T_189;
      end
    end
    if (reset) begin
      _T_7 <= 1'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (~_T_7) begin
        _T_7 <= _GEN_65;
      end
    end
    if (reset) begin
      _T_10 <= 5'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      if (~_T_13) begin
        _T_10 <= _T_312;
      end
    end
    if (reset) begin
      _T_13 <= 1'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      if (~_T_13) begin
        _T_13 <= _GEN_112;
      end
    end
    if (reset) begin
      _T_21 <= 12'h0;
    end else begin
      _T_21 <= _T_24;
    end
    if (reset) begin
      value <= 5'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (_T_177) begin
        value <= 5'h0;
      end else begin
        value <= _T_180;
      end
    end
    if (reset) begin
      value_1 <= 3'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      value_1 <= _T_304;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~reset) begin
          $fwrite(32'h80000002,"All input and output events completed\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_14 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_26 & _T_16) begin
          $fwrite(32'h80000002,
            "Exceeded maximum allowed %d ticks in OrderedDecoupledHWIOTester, If you think code is correct use:\nDecoupleTester.max_tick_count = <some-higher-value>\nin the OrderedDecoupledHWIOTester subclass\n"
            ,12'hfa0);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_26 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_285 & _T_16) begin
          $fwrite(32'h80000002,"output test event %d testing out.bits = %d, should be %d\n",_T_10,
            device_under_test_io_out_bits,4'h8 == _GEN_118 ? 3'h0 : _GEN_110);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_285 & _T_290 & _T_16) begin
          $fwrite(32'h80000002,"Error: event %d out.bits was %d should be %d\n",_T_10,device_under_test_io_out_bits,
            _GEN_111);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $fwrite(32'h80000002,"Assertion failed\n    at OrderedDecoupledHWIOTester.scala:324 assert(false.B)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  _T_4 = _RAND_0[6:0];
  _RAND_1 = {1{`RANDOM}};
  _T_7 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  _T_10 = _RAND_2[4:0];
  _RAND_3 = {1{`RANDOM}};
  _T_13 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  _T_21 = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  value = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  value_1 = _RAND_6[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module SmallOdds4Tester(
  input   clock,
  input   reset
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  device_under_test_clock;
  wire  device_under_test_reset;
  wire  device_under_test_io_in_ready;
  wire  device_under_test_io_in_valid;
  wire [31:0] device_under_test_io_in_bits;
  wire  device_under_test_io_out_ready;
  wire  device_under_test_io_out_valid;
  wire [31:0] device_under_test_io_out_bits;
  reg [6:0] _T_4;
  reg  _T_7;
  reg [4:0] _T_10;
  reg  _T_13;
  wire  _T_14 = _T_7 & _T_13;
  wire  _T_16 = ~reset;
  reg [11:0] _T_21;
  wire [11:0] _T_24 = _T_21 + 12'h1;
  wire  _T_26 = _T_21 > 12'hfa0;
  reg [4:0] value;
  wire [4:0] _GEN_1 = 5'h1 == value ? 5'h8 : 5'h3;
  wire [4:0] _GEN_2 = 5'h2 == value ? 5'h4 : _GEN_1;
  wire [4:0] _GEN_3 = 5'h3 == value ? 5'h7 : _GEN_2;
  wire [4:0] _GEN_4 = 5'h4 == value ? 5'hc : _GEN_3;
  wire [4:0] _GEN_5 = 5'h5 == value ? 5'h0 : _GEN_4;
  wire [4:0] _GEN_6 = 5'h6 == value ? 5'h3 : _GEN_5;
  wire [4:0] _GEN_7 = 5'h7 == value ? 5'h2 : _GEN_6;
  wire [4:0] _GEN_8 = 5'h8 == value ? 5'hc : _GEN_7;
  wire [4:0] _GEN_9 = 5'h9 == value ? 5'h3 : _GEN_8;
  wire [4:0] _GEN_10 = 5'ha == value ? 5'h5 : _GEN_9;
  wire [4:0] _GEN_11 = 5'hb == value ? 5'h5 : _GEN_10;
  wire [4:0] _GEN_12 = 5'hc == value ? 5'h11 : _GEN_11;
  wire [4:0] _GEN_13 = 5'hd == value ? 5'h7 : _GEN_12;
  wire [4:0] _GEN_14 = 5'he == value ? 5'h2 : _GEN_13;
  wire [4:0] _GEN_15 = 5'hf == value ? 5'h2 : _GEN_14;
  wire [4:0] _GEN_16 = 5'h10 == value ? 5'h5 : _GEN_15;
  wire [4:0] _GEN_17 = 5'h11 == value ? 5'hd : _GEN_16;
  wire [4:0] _GEN_18 = 5'h12 == value ? 5'h12 : _GEN_17;
  wire [4:0] _GEN_19 = 5'h13 == value ? 5'hf : _GEN_18;
  wire [4:0] _GEN_20 = 5'h14 == value ? 5'h0 : _GEN_19;
  wire [4:0] _GEN_21 = 5'h15 == value ? 5'hf : _GEN_20;
  wire [4:0] _GEN_22 = 5'h16 == value ? 5'hf : _GEN_21;
  wire [4:0] _GEN_23 = 5'h17 == value ? 5'ha : _GEN_22;
  wire [4:0] _GEN_24 = 5'h18 == value ? 5'h12 : _GEN_23;
  wire [4:0] _GEN_25 = 5'h19 == value ? 5'hb : _GEN_24;
  wire [4:0] _GEN_26 = 5'h1a == value ? 5'he : _GEN_25;
  wire [4:0] _GEN_27 = 5'h1b == value ? 5'h10 : _GEN_26;
  wire [4:0] _GEN_28 = 5'h1c == value ? 5'hc : _GEN_27;
  wire [4:0] _GEN_29 = 5'h1d == value ? 5'h2 : _GEN_28;
  wire [4:0] _GEN_30 = 5'h1e == value ? 5'h13 : _GEN_29;
  wire [4:0] _GEN_31 = 5'h1f == value ? 5'h0 : _GEN_30;
  wire  _T_177 = value == 5'h1e;
  wire [4:0] _T_180 = value + 5'h1;
  wire  _GEN_65 = _T_4 == 7'h1e | _T_7;
  wire [6:0] _T_189 = _T_4 + 7'h1;
  reg [2:0] value_1;
  wire  _GEN_79 = 5'h8 == _T_10 ? 1'h0 : 1'h1;
  wire  _GEN_80 = 5'h9 == _T_10 ? 1'h0 : _GEN_79;
  wire  _GEN_81 = 5'ha == _T_10 ? 1'h0 : _GEN_80;
  wire  _GEN_82 = 5'hb == _T_10 ? 1'h0 : _GEN_81;
  wire  _GEN_83 = 5'hc == _T_10 ? 1'h0 : _GEN_82;
  wire  _GEN_84 = 5'hd == _T_10 ? 1'h0 : _GEN_83;
  wire  _GEN_85 = 5'he == _T_10 ? 1'h0 : _GEN_84;
  wire  _GEN_86 = 5'hf == _T_10 ? 1'h0 : _GEN_85;
  wire  _GEN_87 = 5'h10 == _T_10 ? 1'h0 : _GEN_86;
  wire  _GEN_88 = 5'h11 == _T_10 ? 1'h0 : _GEN_87;
  wire  _GEN_89 = 5'h12 == _T_10 ? 1'h0 : _GEN_88;
  wire  _GEN_90 = 5'h13 == _T_10 ? 1'h0 : _GEN_89;
  wire  _GEN_91 = 5'h14 == _T_10 ? 1'h0 : _GEN_90;
  wire  _GEN_92 = 5'h15 == _T_10 ? 1'h0 : _GEN_91;
  wire  _GEN_93 = 5'h16 == _T_10 ? 1'h0 : _GEN_92;
  wire  _GEN_94 = 5'h17 == _T_10 ? 1'h0 : _GEN_93;
  wire  _GEN_95 = 5'h18 == _T_10 ? 1'h0 : _GEN_94;
  wire  _GEN_96 = 5'h19 == _T_10 ? 1'h0 : _GEN_95;
  wire  _GEN_97 = 5'h1a == _T_10 ? 1'h0 : _GEN_96;
  wire  _GEN_98 = 5'h1b == _T_10 ? 1'h0 : _GEN_97;
  wire  _GEN_99 = 5'h1c == _T_10 ? 1'h0 : _GEN_98;
  wire  _GEN_100 = 5'h1d == _T_10 ? 1'h0 : _GEN_99;
  wire  _GEN_101 = 5'h1e == _T_10 ? 1'h0 : _GEN_100;
  wire  _T_285 = device_under_test_io_out_ready & device_under_test_io_out_valid;
  wire [2:0] _GEN_104 = 3'h1 == value_1 ? 3'h7 : 3'h3;
  wire [2:0] _GEN_105 = 3'h2 == value_1 ? 3'h3 : _GEN_104;
  wire [2:0] _GEN_106 = 3'h3 == value_1 ? 3'h3 : _GEN_105;
  wire [2:0] _GEN_107 = 3'h4 == value_1 ? 3'h5 : _GEN_106;
  wire [2:0] _GEN_108 = 3'h5 == value_1 ? 3'h5 : _GEN_107;
  wire [2:0] _GEN_109 = 3'h6 == value_1 ? 3'h7 : _GEN_108;
  wire [2:0] _GEN_110 = 3'h7 == value_1 ? 3'h5 : _GEN_109;
  wire [3:0] _GEN_118 = {{1'd0}, value_1};
  wire [2:0] _GEN_111 = 4'h8 == _GEN_118 ? 3'h0 : _GEN_110;
  wire [31:0] _GEN_119 = {{29'd0}, _GEN_111};
  wire  _T_290 = device_under_test_io_out_bits != _GEN_119;
  wire [2:0] _T_304 = value_1 + 3'h1;
  wire  _GEN_112 = _T_10 == 5'h7 | _T_13;
  wire [4:0] _T_312 = _T_10 + 5'h1;
  wire  _GEN_121 = _T_285 & _T_290;
  SmallOdds4 device_under_test (
    .clock(device_under_test_clock),
    .reset(device_under_test_reset),
    .io_in_ready(device_under_test_io_in_ready),
    .io_in_valid(device_under_test_io_in_valid),
    .io_in_bits(device_under_test_io_in_bits),
    .io_out_ready(device_under_test_io_out_ready),
    .io_out_valid(device_under_test_io_out_valid),
    .io_out_bits(device_under_test_io_out_bits)
  );
  assign device_under_test_clock = clock;
  assign device_under_test_reset = reset;
  assign device_under_test_io_in_valid = 5'h1f == _T_4[4:0] ? 1'h0 : 1'h1;
  assign device_under_test_io_in_bits = {{27'd0}, _GEN_31};
  assign device_under_test_io_out_ready = 5'h1f == _T_10 ? 1'h0 : _GEN_101;
  always @(posedge clock) begin
    if (reset) begin
      _T_4 <= 7'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (~_T_7) begin
        _T_4 <= _T_189;
      end
    end
    if (reset) begin
      _T_7 <= 1'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (~_T_7) begin
        _T_7 <= _GEN_65;
      end
    end
    if (reset) begin
      _T_10 <= 5'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      if (~_T_13) begin
        _T_10 <= _T_312;
      end
    end
    if (reset) begin
      _T_13 <= 1'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      if (~_T_13) begin
        _T_13 <= _GEN_112;
      end
    end
    if (reset) begin
      _T_21 <= 12'h0;
    end else begin
      _T_21 <= _T_24;
    end
    if (reset) begin
      value <= 5'h0;
    end else if (device_under_test_io_in_valid & device_under_test_io_in_ready) begin
      if (_T_177) begin
        value <= 5'h0;
      end else begin
        value <= _T_180;
      end
    end
    if (reset) begin
      value_1 <= 3'h0;
    end else if (device_under_test_io_out_ready & device_under_test_io_out_valid) begin
      value_1 <= _T_304;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_14 & ~reset) begin
          $fwrite(32'h80000002,"All input and output events completed\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_14 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_26 & _T_16) begin
          $fwrite(32'h80000002,
            "Exceeded maximum allowed %d ticks in OrderedDecoupledHWIOTester, If you think code is correct use:\nDecoupleTester.max_tick_count = <some-higher-value>\nin the OrderedDecoupledHWIOTester subclass\n"
            ,12'hfa0);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_26 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_285 & _T_16) begin
          $fwrite(32'h80000002,"output test event %d testing out.bits = %d, should be %d\n",_T_10,
            device_under_test_io_out_bits,4'h8 == _GEN_118 ? 3'h0 : _GEN_110);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_285 & _T_290 & _T_16) begin
          $fwrite(32'h80000002,"Error: event %d out.bits was %d should be %d\n",_T_10,device_under_test_io_out_bits,
            _GEN_111);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $fwrite(32'h80000002,"Assertion failed\n    at OrderedDecoupledHWIOTester.scala:324 assert(false.B)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_121 & _T_16) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  _T_4 = _RAND_0[6:0];
  _RAND_1 = {1{`RANDOM}};
  _T_7 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  _T_10 = _RAND_2[4:0];
  _RAND_3 = {1{`RANDOM}};
  _T_13 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  _T_21 = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  value = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  value_1 = _RAND_6[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule