data/full_repos/permissive/445488268/trivium-verilog/trivium_top.v
1: b"%Error: data/full_repos/permissive/445488268/trivium-verilog/trivium_top.v:61: Cannot find file containing module: 'cipher_engine'\ncipher_engine cphr(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/cipher_engine\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/cipher_engine.v\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/cipher_engine.sv\n             cipher_engine\n             cipher_engine.v\n             cipher_engine.sv\n             obj_dir/cipher_engine\n             obj_dir/cipher_engine.v\n             obj_dir/cipher_engine.sv\n%Error: Exiting due to 1 error(s)\n"
module trivium_top(

    input   wire            clk_i,
    input   wire            n_rst_i,
    input   wire    [31:0]  dat_i,
    input   wire    [31:0]  ld_dat_i,
    input   wire    [2:0]   ld_reg_a_i,
    input   wire    [2:0]   ld_reg_b_i,
    input   wire            init_i,
    input   wire            proc_i,


    output  reg     [31:0]  dat_o,
    output  wire            busy_o
);




reg     [2:0]   next_state_s;
reg     [2:0]   cur_state_r;
reg     [10:0]  cntr_r;
reg             cphr_en_r;
reg     [31:0]  dat_r;
wire            bit_out_s;
integer i;




parameter   IDLE_e = 0, 
            WARMUP_e = 1, 
            WAIT_PROC_e = 2, 
            PROC_e = 3;




cipher_engine cphr(
    .clk_i(clk_i),
    .n_rst_i(n_rst_i),
    .ce_i(cphr_en_r),
    .ld_dat_i(ld_dat_i),
    .ld_reg_a_i(ld_reg_a_i),
    .ld_reg_b_i(ld_reg_b_i),
    .dat_i(dat_r[0]),
    .dat_o(bit_out_s)
);




assign busy_o = cphr_en_r;
initial begin
    cur_state_r = IDLE_e;
    cntr_r = 0;
    cphr_en_r = 1'b0;
end




always @(*) begin
    case (cur_state_r)
        IDLE_e:

            if (init_i)
                next_state_s = WARMUP_e;
            else
                next_state_s = IDLE_e;
            
        WARMUP_e:

            if (cntr_r == 1151)
                next_state_s = WAIT_PROC_e;
            else
                next_state_s = WARMUP_e;
            
        WAIT_PROC_e:
            if (proc_i)
                next_state_s = PROC_e;
            else if (init_i)
                next_state_s = WARMUP_e;
            else
                next_state_s = WAIT_PROC_e;
            
        PROC_e:

            if (cntr_r == 31)
                next_state_s = WAIT_PROC_e;
            else
                next_state_s = PROC_e;
            
        default:
            next_state_s = cur_state_r;
    endcase
end




always @(posedge clk_i or negedge n_rst_i) begin
    if (!n_rst_i) begin

        cntr_r <= 0;
        cur_state_r <= IDLE_e;
        cphr_en_r <= 1'b0;
        dat_o <= 0;
        dat_r <= 0;
    end
    else begin

        cur_state_r <= next_state_s;
      

        case (cur_state_r)
            IDLE_e: begin
                if (next_state_s == WARMUP_e) begin

                    cphr_en_r <= 1'b1;
                end
            end
         
            WARMUP_e: begin
                if (next_state_s == WAIT_PROC_e) begin
                    cntr_r <= 0;
                    cphr_en_r <= 1'b0;
                end
                else begin

                    cntr_r <= cntr_r + 1;
                end
            end
         
            WAIT_PROC_e: begin

                if (next_state_s == PROC_e) begin
                    cphr_en_r <= 1'b1;
                    dat_r <= dat_i;
                end
                else if (next_state_s == WARMUP_e)
                    cphr_en_r <= 1'b1;
            end
         
            PROC_e: begin
                if (next_state_s == WAIT_PROC_e) begin
                    cphr_en_r <= 1'b0;
                    cntr_r <= 0;
                end
                else
                    cntr_r <= cntr_r + 1;
                    

                dat_r <= {1'b0, dat_r[31:1]};
            

                dat_o <= {bit_out_s, dat_o[31:1]};
            end
         
        endcase
    end
end

endmodule
module trivium_top(

    input   wire            clk_i,
    input   wire            n_rst_i,
    input   wire    [31:0]  dat_i,
    input   wire    [31:0]  ld_dat_i,
    input   wire    [2:0]   ld_reg_a_i,
    input   wire    [2:0]   ld_reg_b_i,
    input   wire            init_i,
    input   wire            proc_i,


    output  reg     [31:0]  dat_o,
    output  wire            busy_o
);





reg     [2:0]   next_state_s;
reg     [2:0]   cur_state_r;
reg     [10:0]  cntr_r;
reg             cphr_en_r;
reg     [31:0]  dat_r;
wire            bit_out_s;
integer i;




parameter   IDLE_e = 0, 
            WARMUP_e = 1, 
            WAIT_PROC_e = 2, 
            PROC_e = 3;




cipher_engine cphr(
    .clk_i(clk_i),
    .n_rst_i(n_rst_i),
    .ce_i(cphr_en_r),
    .ld_dat_i(ld_dat_i),
    .ld_reg_a_i(ld_reg_a_i),
    .ld_reg_b_i(ld_reg_b_i),
    .dat_i(dat_r[0]),
    .dat_o(bit_out_s)
);




assign busy_o = cphr_en_r;
initial begin
    cur_state_r = IDLE_e;
    cntr_r = 0;
    cphr_en_r = 1'b0;
end




always @(*) begin
    case (cur_state_r)
        IDLE_e:

            if (init_i)
                next_state_s = WARMUP_e;
            else
                next_state_s = IDLE_e;
            
        WARMUP_e:

            if (cntr_r == 1151)
                next_state_s = WAIT_PROC_e;
            else
                next_state_s = WARMUP_e;
            
        WAIT_PROC_e:
            if (proc_i)
                next_state_s = PROC_e;
            else if (init_i)
                next_state_s = WARMUP_e;
            else
                next_state_s = WAIT_PROC_e;
            
        PROC_e:

            if (cntr_r == 31)
                next_state_s = WAIT_PROC_e;
            else
                next_state_s = PROC_e;
            
        default:
            next_state_s = cur_state_r;
    endcase
end




always @(posedge clk_i or negedge n_rst_i) begin
    if (!n_rst_i) begin

        cntr_r <= 0;
        cur_state_r <= IDLE_e;
        cphr_en_r <= 1'b0;
        dat_o <= 0;
        dat_r <= 0;
    end
    else begin

        cur_state_r <= next_state_s;
      

        case (cur_state_r)
            IDLE_e: begin
                if (next_state_s == WARMUP_e) begin

                    cphr_en_r <= 1'b1;
                end
            end
         
            WARMUP_e: begin
                if (next_state_s == WAIT_PROC_e) begin
                    cntr_r <= 0;
                    cphr_en_r <= 1'b0;
                end
                else begin

                    cntr_r <= cntr_r + 1;
                end
            end
         
            WAIT_PROC_e: begin

                if (next_state_s == PROC_e) begin
                    cphr_en_r <= 1'b1;
                    dat_r <= dat_i;
                end
                else if (next_state_s == WARMUP_e)
                    cphr_en_r <= 1'b1;
            end
         
            PROC_e: begin
                if (next_state_s == WAIT_PROC_e) begin
                    cphr_en_r <= 1'b0;
                    cntr_r <= 0;
                end
                else
                    cntr_r <= cntr_r + 1;
                    

                dat_r <= {1'b0, dat_r[31:1]};
            

                dat_o <= {bit_out_s, dat_o[31:1]};
            end
         
        endcase
    end
end

endmodule