data/full_repos/permissive/445216371/stage6.v
data/verilator_xmls/6de3f098-a951-4550-a7e6-425bc1189ac7.xml
module s6_Forward (
    output reg [31:0] AluOuto,
    output reg [4:0] Rdo,
    output reg regesterWo,
    input [31:0] AluOut,
    input [4:0] Rd,
    input regesterW,
    input clk,rst,stall
);
    always @(posedge clk, negedge rst) begin
        if(!rst)begin
            AluOuto<=0;
            Rdo<=0;
            regesterWo<=0;
        end
        else begin
            if(stall) begin
                AluOuto<=AluOuto;
                Rdo<=Rdo;
                regesterWo<=regesterWo;
            end else begin
                AluOuto<=AluOut;
                Rdo<=Rd;
                regesterWo<=regesterW;
            end
        end
    end
endmodule
module s6_Forward (
    output reg [31:0] AluOuto,
    output reg [4:0] Rdo,
    output reg regesterWo,
    input [31:0] AluOut,
    input [4:0] Rd,
    input regesterW,
    input clk,rst,stall
);

    always @(posedge clk, negedge rst) begin
        if(!rst)begin
            AluOuto<=0;
            Rdo<=0;
            regesterWo<=0;
        end
        else begin
            if(stall) begin
                AluOuto<=AluOuto;
                Rdo<=Rdo;
                regesterWo<=regesterWo;
            end else begin
                AluOuto<=AluOut;
                Rdo<=Rd;
                regesterWo<=regesterW;
            end
        end
    end
endmodule