data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:518: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:518: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:519: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:519: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:520: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:520: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:360: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k0_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:360: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k0_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:361: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k1_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:361: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k1_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:362: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k0_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add1_k0_st2 <= sqr_k0_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:363: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k1_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add1_k1_st2 <= sqr_k1_d2_st1;\n                ^~\n%Error: Exiting due to 12 warning(s)\n'
module kmeans_input_data_block_3dim #
(
  parameter input_data_width = 8,
  parameter memory_depth_bits = 8,
  parameter mem_d0_init_file = "./db/d0.txt",
  parameter mem_d1_init_file = "./db/d1.txt",
  parameter mem_d2_init_file = "./db/d2.txt"
)
(
  input clk,
  input [memory_depth_bits-1:0] rd_address,
  output [input_data_width-1:0] output_data0,
  output [input_data_width-1:0] output_data1,
  output [input_data_width-1:0] output_data2
);


  RAM
  #(
    .read_f(1),
    .init_file(mem_d0_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_0
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data0),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


  RAM
  #(
    .read_f(1),
    .init_file(mem_d1_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_1
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data1),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


  RAM
  #(
    .read_f(1),
    .init_file(mem_d2_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_2
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data2),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


endmodule
module kmeans_input_data_block_3dim #
(
  parameter input_data_width = 8,
  parameter memory_depth_bits = 8,
  parameter mem_d0_init_file = "./db/d0.txt",
  parameter mem_d1_init_file = "./db/d1.txt",
  parameter mem_d2_init_file = "./db/d2.txt"
)
(
  input clk,
  input [memory_depth_bits-1:0] rd_address,
  output [input_data_width-1:0] output_data0,
  output [input_data_width-1:0] output_data1,
  output [input_data_width-1:0] output_data2
);



  RAM
  #(
    .read_f(1),
    .init_file(mem_d0_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_0
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data0),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


  RAM
  #(
    .read_f(1),
    .init_file(mem_d1_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_1
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data1),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


  RAM
  #(
    .read_f(1),
    .init_file(mem_d2_init_file),
    .write_f(0),
    .output_file("mem_out_file.txt"),
    .depth(memory_depth_bits),
    .width(input_data_width)
  )
  RAM_2
  (
    .clk(clk),
    .rd_addr(rd_address),
    .out(output_data2),
    .wr(1'd0),
    .wr_addr(8'd0),
    .wr_data(8'd0)
  );


endmodule