data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Conditional/top_module.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Conditional,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Conditional/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input  wire [7:0] a,
    input  wire [7:0] b,
    input  wire [7:0] c,
    input  wire [7:0] d,
    output wire [7:0] min
);





  reg [7:0] min_i;
  always @(*) begin
    min_i = a;
    if (b < min_i) min_i = b;
    if (c < min_i) min_i = c;
    if (d < min_i) min_i = d;
  end

  assign min = min_i;

endmodule
module top_module (
    input  wire [7:0] a,
    input  wire [7:0] b,
    input  wire [7:0] c,
    input  wire [7:0] d,
    output wire [7:0] min
);






  reg [7:0] min_i;
  always @(*) begin
    min_i = a;
    if (b < min_i) min_i = b;
    if (c < min_i) min_i = c;
    if (d < min_i) min_i = d;
  end

  assign min = min_i;

endmodule