data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_rng.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_rng.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #500000 rng_clk = ~rng_clk;   \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_rng.v:51: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n   rand_num = $random (seed) & rst_l;\n              ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_rng.v:51: ../V3Ast.cpp:358: Null item passed to setOp1p\n   rand_num = $random (seed) & rst_l;\n                             ^\n                        ... See the manual and https://verilator.org for more assistance.\n'
module bw_rng (

	rng_data, rng_clk, 

 	vsup_rng_hv18, sel_bg_l, vctrl, clk_jbus, rst_l 
   	);

 	input	vsup_rng_hv18;
	input	sel_bg_l;
	input [2:0] vctrl;
	input 	clk_jbus;
	input 	rst_l ;
   	output rng_data;
   	output rng_clk;


   	integer     	seed;
   	reg		rand_num;
   	reg		rng_clk;
   	reg		rng_data;
   
   	initial
   	begin
	  seed = 2;
      	  rng_clk = 1'b0;
   	end
   
   	always 
        begin
	  #500000 rng_clk = ~rng_clk;
	  rand_num = $random (seed) & rst_l;
	  rng_data = rand_num;
     	end


endmodule
module bw_rng (

	rng_data, rng_clk, 

 	vsup_rng_hv18, sel_bg_l, vctrl, clk_jbus, rst_l 
   	);


 	input	vsup_rng_hv18;
	input	sel_bg_l;
	input [2:0] vctrl;
	input 	clk_jbus;
	input 	rst_l ;
   	output rng_data;
   	output rng_clk;


   	integer     	seed;
   	reg		rand_num;
   	reg		rng_clk;
   	reg		rng_data;
   
   	initial
   	begin
	  seed = 2;
      	  rng_clk = 1'b0;
   	end
   
   	always 
        begin
	  #500000 rng_clk = ~rng_clk;
	  rand_num = $random (seed) & rst_l;
	  rng_data = rand_num;
     	end


endmodule