data/full_repos/permissive/452648646/test/ram.v
data/verilator_xmls/573a5832-f806-4eb0-abcc-e941f38cf18c.xml
module ram (
    input wire clk,
    output wire [31:0] memory_out,
    input wire [31:0] memory_in,
    input wire [11:2] address,
    input wire write_enable
);

reg [31:0] storage [1024];

assign memory_out = storage[address];

always @(posedge clk) begin
    if (write_enable) begin
        storage[address] <= memory_in;
    end
end

endmodule
module ram (
    input wire clk,
    output wire [31:0] memory_out,
    input wire [31:0] memory_in,
    input wire [11:2] address,
    input wire write_enable
);


reg [31:0] storage [1024];

assign memory_out = storage[address];

always @(posedge clk) begin
    if (write_enable) begin
        storage[address] <= memory_in;
    end
end

endmodule