data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v:83: Define or directive not defined: '`MPRJ_IO_PADS'\n assign io_oeb = {(`MPRJ_IO_PADS-1){vram_rst_o}};\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/user_proj_example.v:85: Define or directive not defined: '`MPRJ_IO_PADS'\n wire [`MPRJ_IO_PADS-1:0] unused_io_in = io_in;\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


	assign io_out[0] = vram_offset;
	assign io_out[1] = vram_write_pixel;
	assign io_out[2] = vram_clk_o;
	assign io_out[3] = vram_rst_o;
	assign io_out[4 +: 16] = vram_raster_color;
	assign io_out[20 +: 18] = vram_raster_address;
	assign io_oeb = {(`MPRJ_IO_PADS-1){vram_rst_o}};
  
	wire [`MPRJ_IO_PADS-1:0] unused_io_in = io_in;
	wire [127:0]             unused_la_data_in = la_data_in;
	wire [127:0]             unused_la_oenb = la_oenb;
	
  

    assign irq = 3'b000;


    assign la_data_out[37:0] = io_out[37:0];
	assign la_data_out[38] = wb_clk_i;
	assign la_data_out[39] = wb_rst_i;
	assign la_data_out[40] = wbs_stb_i;
	assign la_data_out[41] = wbs_we_i;
	assign la_data_out[42 +: 4] = wbs_sel_i;
	assign la_data_out[46 +: 32] = wbs_dat_i;
	assign la_data_out[78 +: 32] = wbs_adr_i;
	assign la_data_out[110] = wbs_ack_o;
	assign la_data_out[127:111] = wbs_dat_o[16:0];
	
	wire [17:0] vram_raster_address;
	wire [15:0] vram_raster_color;
	wire        vram_clk_o;
	wire        vram_rst_o;
	wire        vram_write_pixel;
	wire        vram_offset;
	

    gpu_wrapper gpu_instance(
      .wb_clk_i				(wb_clk_i),
      .wb_rst_i				(wb_rst_i),
      .wbs_stb_i				(wbs_stb_i),
      .wbs_cyc_i				(wbs_cyc_i),
      .wbs_we_i				(wbs_we_i),
      .wbs_sel_i				(wbs_sel_i),
      .wbs_dat_i				(wbs_dat_i),
      .wbs_adr_i				(wbs_adr_i),
      .wbs_ack_o				(wbs_ack_o),
      .wbs_dat_o				(wbs_dat_o),
      .vram_raster_address	(vram_raster_address),
      .vram_raster_color		(vram_raster_color),
      .vram_clk_o				(vram_clk_o),
      .vram_rst_o				(vram_rst_o),
      .vram_write_pixel		(vram_write_pixel),
      .vram_offset			(vram_offset)
    );

endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);



	assign io_out[0] = vram_offset;
	assign io_out[1] = vram_write_pixel;
	assign io_out[2] = vram_clk_o;
	assign io_out[3] = vram_rst_o;
	assign io_out[4 +: 16] = vram_raster_color;
	assign io_out[20 +: 18] = vram_raster_address;
	assign io_oeb = {(`MPRJ_IO_PADS-1){vram_rst_o}};
  
	wire [`MPRJ_IO_PADS-1:0] unused_io_in = io_in;
	wire [127:0]             unused_la_data_in = la_data_in;
	wire [127:0]             unused_la_oenb = la_oenb;
	
  

    assign irq = 3'b000;


    assign la_data_out[37:0] = io_out[37:0];
	assign la_data_out[38] = wb_clk_i;
	assign la_data_out[39] = wb_rst_i;
	assign la_data_out[40] = wbs_stb_i;
	assign la_data_out[41] = wbs_we_i;
	assign la_data_out[42 +: 4] = wbs_sel_i;
	assign la_data_out[46 +: 32] = wbs_dat_i;
	assign la_data_out[78 +: 32] = wbs_adr_i;
	assign la_data_out[110] = wbs_ack_o;
	assign la_data_out[127:111] = wbs_dat_o[16:0];
	
	wire [17:0] vram_raster_address;
	wire [15:0] vram_raster_color;
	wire        vram_clk_o;
	wire        vram_rst_o;
	wire        vram_write_pixel;
	wire        vram_offset;
	

    gpu_wrapper gpu_instance(
      .wb_clk_i				(wb_clk_i),
      .wb_rst_i				(wb_rst_i),
      .wbs_stb_i				(wbs_stb_i),
      .wbs_cyc_i				(wbs_cyc_i),
      .wbs_we_i				(wbs_we_i),
      .wbs_sel_i				(wbs_sel_i),
      .wbs_dat_i				(wbs_dat_i),
      .wbs_adr_i				(wbs_adr_i),
      .wbs_ack_o				(wbs_ack_o),
      .wbs_dat_o				(wbs_dat_o),
      .vram_raster_address	(vram_raster_address),
      .vram_raster_color		(vram_raster_color),
      .vram_clk_o				(vram_clk_o),
      .vram_rst_o				(vram_rst_o),
      .vram_write_pixel		(vram_write_pixel),
      .vram_offset			(vram_offset)
    );

endmodule