data/full_repos/permissive/505761772/code/InOutStuff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/InOutStuff.v:30: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'SPI\'\nmodule SPI( input       CLK,\n       ^~~\n                                                                            : ... Top module \'DAC\'\nmodule DAC( input               SCK,\n       ^~~\n                                                                            : ... Top module \'GAIN\'\nmodule GAIN(input       SCK,\n       ^~~~\n                                                                            : ... Top module \'ADC\'\nmodule ADC( input       SCK,\n       ^~~\n                                                                            : ... Top module \'SERIAL_TX\'\nmodule SERIAL_TX (input [7:0]  DATA,\n       ^~~~~~~~~\n                                                                            : ... Top module \'SERIAL_RX\'\nmodule SERIAL_RX (input         CLK,\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'gain\' generates 4 bits.\n                                                                         : ... In instance GAIN\nreg [7:0] data = gain;\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:58: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'AorB\' generates 1 bits.\n                                                                         : ... In instance DAC\n      dataReg <= {8\'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};\n                        ^\n%Error: Exiting due to 3 warning(s)\n'
module ADC( input       SCK,
            input       MISO,
            output reg  RUN,
            output reg [13:0] A,
            output reg [13:0] B);

reg [13:0] ShiftReg;
reg [5:0] stateReg;

initial begin
  RUN = 0;
  stateReg = 6'h20;
end

always @(negedge SCK) begin
  if(stateReg == 6'h2F) begin
    stateReg <= 6'h3D;
    A <= ShiftReg;
  end else begin
    if(stateReg == 6'h3D)
      RUN <= 1;
    else if(stateReg == 6'h3E) begin
      RUN <= 0;
    end else if(stateReg < 6'h0E)
      ShiftReg <= {ShiftReg[12:0] , MISO};
    else if(stateReg == 6'h0F)
      B <= ShiftReg;
    else if((stateReg >= 6'h10) && (stateReg < 6'h1E))
      ShiftReg <= {ShiftReg[12:0] , MISO};

    stateReg <= stateReg + 1;
  end
end

endmodule
module ADC( input       SCK,
            input       MISO,
            output reg  RUN,
            output reg [13:0] A,
            output reg [13:0] B);


reg [13:0] ShiftReg;
reg [5:0] stateReg;

initial begin
  RUN = 0;
  stateReg = 6'h20;
end

always @(negedge SCK) begin
  if(stateReg == 6'h2F) begin
    stateReg <= 6'h3D;
    A <= ShiftReg;
  end else begin
    if(stateReg == 6'h3D)
      RUN <= 1;
    else if(stateReg == 6'h3E) begin
      RUN <= 0;
    end else if(stateReg < 6'h0E)
      ShiftReg <= {ShiftReg[12:0] , MISO};
    else if(stateReg == 6'h0F)
      B <= ShiftReg;
    else if((stateReg >= 6'h10) && (stateReg < 6'h1E))
      ShiftReg <= {ShiftReg[12:0] , MISO};

    stateReg <= stateReg + 1;
  end
end

endmodule