data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rf/400m/adc_gearbox_8x4.v
data/verilator_xmls/269f3ed9-0795-4c6e-9c3c-0df958ba5b96.xml
module adc_gearbox_8x4 (
  input  wire         clk1x,
  input  wire         reset_n_1x,

  input  wire [127:0] adc_q_in_1x,
  input  wire [127:0] adc_i_in_1x,
  input  wire         valid_in_1x,

  input  wire         enable_1x,

  input  wire         clk2x,

  input  wire         swap_iq_2x,
  output wire [127:0] adc_out_2x,
  output wire         valid_out_2x
);



  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [127:0] data_out_2x = 128'b0, adc_q_data_in_2x = 128'b0, adc_i_data_in_2x = 128'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end










  always @(posedge clk2x) begin
    toggle_2x     <= toggle_1x;
    toggle_2x_dly <= toggle_2x;
    adc_q_data_in_2x <= adc_q_in_1x;
    adc_i_data_in_2x <= adc_i_in_1x;
    data_out_2x <= 128'b0;

    if (valid_2x) begin
      if (swap_iq_2x) begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x <= {adc_i_data_in_2x[63:48], adc_q_data_in_2x[63:48],
                          adc_i_data_in_2x[47:32], adc_q_data_in_2x[47:32],
                          adc_i_data_in_2x[31:16], adc_q_data_in_2x[31:16],
                          adc_i_data_in_2x[15: 0], adc_q_data_in_2x[15: 0]};
        end else begin
          data_out_2x <= {adc_i_data_in_2x[127:112], adc_q_data_in_2x[127:112],
                          adc_i_data_in_2x[111: 96], adc_q_data_in_2x[111: 96],
                          adc_i_data_in_2x[95 : 80], adc_q_data_in_2x[95 : 80],
                          adc_i_data_in_2x[79 : 64], adc_q_data_in_2x[79 : 64]};
        end
      end else begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x <= {adc_q_data_in_2x[63:48], adc_i_data_in_2x[63:48],
                          adc_q_data_in_2x[47:32], adc_i_data_in_2x[47:32],
                          adc_q_data_in_2x[31:16], adc_i_data_in_2x[31:16],
                          adc_q_data_in_2x[15: 0], adc_i_data_in_2x[15: 0]};
        end else begin
          data_out_2x <= {adc_q_data_in_2x[127:112], adc_i_data_in_2x[127:112],
                          adc_q_data_in_2x[111: 96], adc_i_data_in_2x[111: 96],
                          adc_q_data_in_2x[95 : 80], adc_i_data_in_2x[95 : 80],
                          adc_q_data_in_2x[79 : 64], adc_i_data_in_2x[79 : 64]};
        end
      end
    end


    valid_2x     <= valid_in_1x && enable_1x;
    valid_dly_2x <= valid_2x;
  end

  assign adc_out_2x   = data_out_2x;
  assign valid_out_2x = valid_dly_2x;

endmodule
module adc_gearbox_8x4 (
  input  wire         clk1x,
  input  wire         reset_n_1x,

  input  wire [127:0] adc_q_in_1x,
  input  wire [127:0] adc_i_in_1x,
  input  wire         valid_in_1x,

  input  wire         enable_1x,

  input  wire         clk2x,

  input  wire         swap_iq_2x,
  output wire [127:0] adc_out_2x,
  output wire         valid_out_2x
);




  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [127:0] data_out_2x = 128'b0, adc_q_data_in_2x = 128'b0, adc_i_data_in_2x = 128'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end










  always @(posedge clk2x) begin
    toggle_2x     <= toggle_1x;
    toggle_2x_dly <= toggle_2x;
    adc_q_data_in_2x <= adc_q_in_1x;
    adc_i_data_in_2x <= adc_i_in_1x;
    data_out_2x <= 128'b0;

    if (valid_2x) begin
      if (swap_iq_2x) begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x <= {adc_i_data_in_2x[63:48], adc_q_data_in_2x[63:48],
                          adc_i_data_in_2x[47:32], adc_q_data_in_2x[47:32],
                          adc_i_data_in_2x[31:16], adc_q_data_in_2x[31:16],
                          adc_i_data_in_2x[15: 0], adc_q_data_in_2x[15: 0]};
        end else begin
          data_out_2x <= {adc_i_data_in_2x[127:112], adc_q_data_in_2x[127:112],
                          adc_i_data_in_2x[111: 96], adc_q_data_in_2x[111: 96],
                          adc_i_data_in_2x[95 : 80], adc_q_data_in_2x[95 : 80],
                          adc_i_data_in_2x[79 : 64], adc_q_data_in_2x[79 : 64]};
        end
      end else begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x <= {adc_q_data_in_2x[63:48], adc_i_data_in_2x[63:48],
                          adc_q_data_in_2x[47:32], adc_i_data_in_2x[47:32],
                          adc_q_data_in_2x[31:16], adc_i_data_in_2x[31:16],
                          adc_q_data_in_2x[15: 0], adc_i_data_in_2x[15: 0]};
        end else begin
          data_out_2x <= {adc_q_data_in_2x[127:112], adc_i_data_in_2x[127:112],
                          adc_q_data_in_2x[111: 96], adc_i_data_in_2x[111: 96],
                          adc_q_data_in_2x[95 : 80], adc_i_data_in_2x[95 : 80],
                          adc_q_data_in_2x[79 : 64], adc_i_data_in_2x[79 : 64]};
        end
      end
    end


    valid_2x     <= valid_in_1x && enable_1x;
    valid_dly_2x <= valid_2x;
  end

  assign adc_out_2x   = data_out_2x;
  assign valid_out_2x = valid_dly_2x;

endmodule