data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_cbus.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_cbus.v:97: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_vfpu_inst_vld_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_cbus.v:141: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_vfpu_pipe6_data_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_cbus.v:200: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_vfpu_pipe7_data_gated_clk (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ct_vfpu_cbus(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  idu_vfpu_rf_pipe6_gateclk_sel,
  idu_vfpu_rf_pipe6_iid,
  idu_vfpu_rf_pipe6_sel,
  idu_vfpu_rf_pipe7_gateclk_sel,
  idu_vfpu_rf_pipe7_iid,
  idu_vfpu_rf_pipe7_sel,
  pad_yy_icg_scan_en,
  rtu_yy_xx_flush,
  vfpu_rtu_pipe6_cmplt,
  vfpu_rtu_pipe6_iid,
  vfpu_rtu_pipe7_cmplt,
  vfpu_rtu_pipe7_iid
);


input          cp0_vfpu_icg_en;              
input          cp0_yy_clk_en;                
input          cpurst_b;                     
input          forever_cpuclk;               
input          idu_vfpu_rf_pipe6_gateclk_sel; 
input   [6:0]  idu_vfpu_rf_pipe6_iid;        
input          idu_vfpu_rf_pipe6_sel;        
input          idu_vfpu_rf_pipe7_gateclk_sel; 
input   [6:0]  idu_vfpu_rf_pipe7_iid;        
input          idu_vfpu_rf_pipe7_sel;        
input          pad_yy_icg_scan_en;           
input          rtu_yy_xx_flush;              
output         vfpu_rtu_pipe6_cmplt;         
output  [6:0]  vfpu_rtu_pipe6_iid;           
output         vfpu_rtu_pipe7_cmplt;         
output  [6:0]  vfpu_rtu_pipe7_iid;           


reg     [6:0]  cbus_pipe6_iid;               
reg            cbus_pipe6_inst_vld;          
reg     [6:0]  cbus_pipe7_iid;               
reg            cbus_pipe7_inst_vld;          


wire           cbus_pipe6_cmplt;             
wire           cbus_pipe6_gateclk_cmplt;     
wire           cbus_pipe7_cmplt;             
wire           cbus_pipe7_gateclk_cmplt;     
wire           cp0_vfpu_icg_en;              
wire           cp0_yy_clk_en;                
wire           cpurst_b;                     
wire           forever_cpuclk;               
wire           idu_vfpu_rf_pipe6_gateclk_sel; 
wire    [6:0]  idu_vfpu_rf_pipe6_iid;        
wire           idu_vfpu_rf_pipe6_sel;        
wire           idu_vfpu_rf_pipe7_gateclk_sel; 
wire    [6:0]  idu_vfpu_rf_pipe7_iid;        
wire           idu_vfpu_rf_pipe7_sel;        
wire           pad_yy_icg_scan_en;           
wire           rtu_yy_xx_flush;              
wire           vfpu_inst_vld_clk;            
wire           vfpu_inst_vld_clk_en;         
wire           vfpu_pipe6_data_clk;          
wire           vfpu_pipe6_data_clk_en;       
wire           vfpu_pipe7_data_clk;          
wire           vfpu_pipe7_data_clk_en;       
wire           vfpu_rtu_pipe6_cmplt;         
wire    [6:0]  vfpu_rtu_pipe6_iid;           
wire           vfpu_rtu_pipe7_cmplt;         
wire    [6:0]  vfpu_rtu_pipe7_iid;           







assign vfpu_inst_vld_clk_en = cbus_pipe6_gateclk_cmplt
                           || cbus_pipe7_gateclk_cmplt
                           || cbus_pipe6_inst_vld
                           || cbus_pipe7_inst_vld;

gated_clk_cell  x_vfpu_inst_vld_gated_clk (
  .clk_in               (forever_cpuclk      ),
  .clk_out              (vfpu_inst_vld_clk   ),
  .external_en          (1'b0                ),
  .global_en            (cp0_yy_clk_en       ),
  .local_en             (vfpu_inst_vld_clk_en),
  .module_en            (cp0_vfpu_icg_en     ),
  .pad_yy_icg_scan_en   (pad_yy_icg_scan_en  )
);












assign cbus_pipe6_cmplt         = idu_vfpu_rf_pipe6_sel;
assign cbus_pipe6_gateclk_cmplt = idu_vfpu_rf_pipe6_gateclk_sel;
          



always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cbus_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    cbus_pipe6_inst_vld <= 1'b0;
  else
    cbus_pipe6_inst_vld <= cbus_pipe6_cmplt;
end

assign vfpu_rtu_pipe6_cmplt = cbus_pipe6_inst_vld;




assign vfpu_pipe6_data_clk_en = cbus_pipe6_gateclk_cmplt;

gated_clk_cell  x_vfpu_pipe6_data_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (vfpu_pipe6_data_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (vfpu_pipe6_data_clk_en),
  .module_en              (cp0_vfpu_icg_en       ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);











always @(posedge vfpu_pipe6_data_clk or negedge cpurst_b)
begin
  if(!cpurst_b) 
    cbus_pipe6_iid[6:0] <= 7'b0;
  else if(cbus_pipe6_cmplt)
    cbus_pipe6_iid[6:0] <= idu_vfpu_rf_pipe6_iid[6:0];
  else 
    cbus_pipe6_iid[6:0] <= cbus_pipe6_iid[6:0];
end


assign vfpu_rtu_pipe6_iid[6:0] = cbus_pipe6_iid[6:0];




assign cbus_pipe7_cmplt         = idu_vfpu_rf_pipe7_sel;
assign cbus_pipe7_gateclk_cmplt = idu_vfpu_rf_pipe7_gateclk_sel;
          



always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cbus_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    cbus_pipe7_inst_vld <= 1'b0;
  else
    cbus_pipe7_inst_vld <= cbus_pipe7_cmplt;
end

assign vfpu_rtu_pipe7_cmplt = cbus_pipe7_inst_vld;




assign vfpu_pipe7_data_clk_en = cbus_pipe7_gateclk_cmplt;

gated_clk_cell  x_vfpu_pipe7_data_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (vfpu_pipe7_data_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (vfpu_pipe7_data_clk_en),
  .module_en              (cp0_vfpu_icg_en       ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);











always @(posedge vfpu_pipe7_data_clk or negedge cpurst_b)
begin
  if(!cpurst_b) 
    cbus_pipe7_iid[6:0] <= 7'b0;
  else if(cbus_pipe7_cmplt)
    cbus_pipe7_iid[6:0] <= idu_vfpu_rf_pipe7_iid[6:0];
  else 
    cbus_pipe7_iid[6:0] <= cbus_pipe7_iid[6:0];
end


assign vfpu_rtu_pipe7_iid[6:0] = cbus_pipe7_iid[6:0];


endmodule
module ct_vfpu_cbus(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  idu_vfpu_rf_pipe6_gateclk_sel,
  idu_vfpu_rf_pipe6_iid,
  idu_vfpu_rf_pipe6_sel,
  idu_vfpu_rf_pipe7_gateclk_sel,
  idu_vfpu_rf_pipe7_iid,
  idu_vfpu_rf_pipe7_sel,
  pad_yy_icg_scan_en,
  rtu_yy_xx_flush,
  vfpu_rtu_pipe6_cmplt,
  vfpu_rtu_pipe6_iid,
  vfpu_rtu_pipe7_cmplt,
  vfpu_rtu_pipe7_iid
);



input          cp0_vfpu_icg_en;              
input          cp0_yy_clk_en;                
input          cpurst_b;                     
input          forever_cpuclk;               
input          idu_vfpu_rf_pipe6_gateclk_sel; 
input   [6:0]  idu_vfpu_rf_pipe6_iid;        
input          idu_vfpu_rf_pipe6_sel;        
input          idu_vfpu_rf_pipe7_gateclk_sel; 
input   [6:0]  idu_vfpu_rf_pipe7_iid;        
input          idu_vfpu_rf_pipe7_sel;        
input          pad_yy_icg_scan_en;           
input          rtu_yy_xx_flush;              
output         vfpu_rtu_pipe6_cmplt;         
output  [6:0]  vfpu_rtu_pipe6_iid;           
output         vfpu_rtu_pipe7_cmplt;         
output  [6:0]  vfpu_rtu_pipe7_iid;           


reg     [6:0]  cbus_pipe6_iid;               
reg            cbus_pipe6_inst_vld;          
reg     [6:0]  cbus_pipe7_iid;               
reg            cbus_pipe7_inst_vld;          


wire           cbus_pipe6_cmplt;             
wire           cbus_pipe6_gateclk_cmplt;     
wire           cbus_pipe7_cmplt;             
wire           cbus_pipe7_gateclk_cmplt;     
wire           cp0_vfpu_icg_en;              
wire           cp0_yy_clk_en;                
wire           cpurst_b;                     
wire           forever_cpuclk;               
wire           idu_vfpu_rf_pipe6_gateclk_sel; 
wire    [6:0]  idu_vfpu_rf_pipe6_iid;        
wire           idu_vfpu_rf_pipe6_sel;        
wire           idu_vfpu_rf_pipe7_gateclk_sel; 
wire    [6:0]  idu_vfpu_rf_pipe7_iid;        
wire           idu_vfpu_rf_pipe7_sel;        
wire           pad_yy_icg_scan_en;           
wire           rtu_yy_xx_flush;              
wire           vfpu_inst_vld_clk;            
wire           vfpu_inst_vld_clk_en;         
wire           vfpu_pipe6_data_clk;          
wire           vfpu_pipe6_data_clk_en;       
wire           vfpu_pipe7_data_clk;          
wire           vfpu_pipe7_data_clk_en;       
wire           vfpu_rtu_pipe6_cmplt;         
wire    [6:0]  vfpu_rtu_pipe6_iid;           
wire           vfpu_rtu_pipe7_cmplt;         
wire    [6:0]  vfpu_rtu_pipe7_iid;           







assign vfpu_inst_vld_clk_en = cbus_pipe6_gateclk_cmplt
                           || cbus_pipe7_gateclk_cmplt
                           || cbus_pipe6_inst_vld
                           || cbus_pipe7_inst_vld;

gated_clk_cell  x_vfpu_inst_vld_gated_clk (
  .clk_in               (forever_cpuclk      ),
  .clk_out              (vfpu_inst_vld_clk   ),
  .external_en          (1'b0                ),
  .global_en            (cp0_yy_clk_en       ),
  .local_en             (vfpu_inst_vld_clk_en),
  .module_en            (cp0_vfpu_icg_en     ),
  .pad_yy_icg_scan_en   (pad_yy_icg_scan_en  )
);












assign cbus_pipe6_cmplt         = idu_vfpu_rf_pipe6_sel;
assign cbus_pipe6_gateclk_cmplt = idu_vfpu_rf_pipe6_gateclk_sel;
          



always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cbus_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    cbus_pipe6_inst_vld <= 1'b0;
  else
    cbus_pipe6_inst_vld <= cbus_pipe6_cmplt;
end

assign vfpu_rtu_pipe6_cmplt = cbus_pipe6_inst_vld;




assign vfpu_pipe6_data_clk_en = cbus_pipe6_gateclk_cmplt;

gated_clk_cell  x_vfpu_pipe6_data_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (vfpu_pipe6_data_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (vfpu_pipe6_data_clk_en),
  .module_en              (cp0_vfpu_icg_en       ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);











always @(posedge vfpu_pipe6_data_clk or negedge cpurst_b)
begin
  if(!cpurst_b) 
    cbus_pipe6_iid[6:0] <= 7'b0;
  else if(cbus_pipe6_cmplt)
    cbus_pipe6_iid[6:0] <= idu_vfpu_rf_pipe6_iid[6:0];
  else 
    cbus_pipe6_iid[6:0] <= cbus_pipe6_iid[6:0];
end


assign vfpu_rtu_pipe6_iid[6:0] = cbus_pipe6_iid[6:0];




assign cbus_pipe7_cmplt         = idu_vfpu_rf_pipe7_sel;
assign cbus_pipe7_gateclk_cmplt = idu_vfpu_rf_pipe7_gateclk_sel;
          



always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cbus_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    cbus_pipe7_inst_vld <= 1'b0;
  else
    cbus_pipe7_inst_vld <= cbus_pipe7_cmplt;
end

assign vfpu_rtu_pipe7_cmplt = cbus_pipe7_inst_vld;




assign vfpu_pipe7_data_clk_en = cbus_pipe7_gateclk_cmplt;

gated_clk_cell  x_vfpu_pipe7_data_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (vfpu_pipe7_data_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (vfpu_pipe7_data_clk_en),
  .module_en              (cp0_vfpu_icg_en       ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);











always @(posedge vfpu_pipe7_data_clk or negedge cpurst_b)
begin
  if(!cpurst_b) 
    cbus_pipe7_iid[6:0] <= 7'b0;
  else if(cbus_pipe7_cmplt)
    cbus_pipe7_iid[6:0] <= idu_vfpu_rf_pipe7_iid[6:0];
  else 
    cbus_pipe7_iid[6:0] <= cbus_pipe7_iid[6:0];
end


assign vfpu_rtu_pipe7_iid[6:0] = cbus_pipe7_iid[6:0];


endmodule