data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v
1: b'%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:1: Cannot find include file: ./global.vh\n`include "./global.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.sv\n             ./global.vh\n             ./global.vh.v\n             ./global.vh.sv\n             obj_dir/./global.vh\n             obj_dir/./global.vh.v\n             obj_dir/./global.vh.sv\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:5: Define or directive not defined: \'`F_N\'\n    input  [2*`F_N - 1:0] external,    \n              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:6: Define or directive not defined: \'`F_N\'\n    input  [  `F_N - 1:0] internal,    \n              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:7: Define or directive not defined: \'`F_N\'\n    output [2*`F_N-1:0] LED,           \n              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:20: Define or directive not defined: \'`F_N\'\n        for(i = 0; i < `F_N; i = i + 1) begin : KEYLED\n                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for(i = 0; i < `F_N; i = i + 1) begin : KEYLED\n                           ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:30: Define or directive not defined: \'`F_N\'\n    wire [2*`F_N-1:0] demand_state;\n            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:42: Define or directive not defined: \'`F_N\'\n        .up_in(external[2*`F_N-1:`F_N]),\n                          ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:42: Define or directive not defined: \'`F_N\'\n        .up_in(external[2*`F_N-1:`F_N]),\n                                 ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        .up_in(external[2*`F_N-1:`F_N]),\n                                     ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:43: Define or directive not defined: \'`F_N\'\n        .down_in(external[`F_N-1:0]),\n                          ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:60: Define or directive not defined: \'`INVALID\'\n    assign signal_dataBus = {running_state[3:0], door_state[3:0], `INVALID, `INVALID};\n                                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:60: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    assign signal_dataBus = {running_state[3:0], door_state[3:0], `INVALID, `INVALID};\n                                                                          ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:60: Define or directive not defined: \'`INVALID\'\n    assign signal_dataBus = {running_state[3:0], door_state[3:0], `INVALID, `INVALID};\n                                                                            ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/top.v:64: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module top(
    input clk100mhz,
    input rst_in,
    input  [2*`F_N - 1:0] external,
    input  [  `F_N - 1:0] internal,
    output [2*`F_N-1:0] LED,
    output [3:0] posH,
    output [7:0] segH,
    output [3:0] posL,
    output [7:0] segL
);

    wire clk380hz, clk10hz, clk1hz;
    clkDiv cd(clk100mhz, clk380hz, clk10hz, clk1hz);

    wire [3:0] inter_keys;
    genvar i;
    generate
        for(i = 0; i < `F_N; i = i + 1) begin : KEYLED
            keyled led(clk100mhz, internal[i], inter_keys[i]);
        end
    endgenerate
    keyled rst_key(clk100mhz, rst_in, rst);

    wire [7:0] curr_floor;
    wire [3:0] running_state;
    wire [3:0] door_state;
    wire [2:0] req;
    wire [2*`F_N-1:0] demand_state;
    wire [3:0] state_dataBus;
    wire [15:0] number_dataBus;
    wire [15:0] signal_dataBus;

    request Request(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .floor_in(inter_keys),
        .up_in(external[2*`F_N-1:`F_N]),
        .down_in(external[`F_N-1:0]),
        .req(req),
        .demand_state(demand_state)     
    );

    control Control(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .req(req),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .state(state_dataBus)
    );

    assign LED = demand_state;
    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8'hff};
    assign signal_dataBus = {running_state[3:0], door_state[3:0], `INVALID, `INVALID};
    num_segMsg    numbers(clk380hz, number_dataBus, posL, segL);
    signal_segMsg signals(clk380hz, signal_dataBus, posH, segH);

endmodule
module top(
    input clk100mhz,
    input rst_in,
    input  [2*`F_N - 1:0] external,
    input  [  `F_N - 1:0] internal,
    output [2*`F_N-1:0] LED,
    output [3:0] posH,
    output [7:0] segH,
    output [3:0] posL,
    output [7:0] segL
);


    wire clk380hz, clk10hz, clk1hz;
    clkDiv cd(clk100mhz, clk380hz, clk10hz, clk1hz);

    wire [3:0] inter_keys;
    genvar i;
    generate
        for(i = 0; i < `F_N; i = i + 1) begin : KEYLED
            keyled led(clk100mhz, internal[i], inter_keys[i]);
        end
    endgenerate
    keyled rst_key(clk100mhz, rst_in, rst);

    wire [7:0] curr_floor;
    wire [3:0] running_state;
    wire [3:0] door_state;
    wire [2:0] req;
    wire [2*`F_N-1:0] demand_state;
    wire [3:0] state_dataBus;
    wire [15:0] number_dataBus;
    wire [15:0] signal_dataBus;

    request Request(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .floor_in(inter_keys),
        .up_in(external[2*`F_N-1:`F_N]),
        .down_in(external[`F_N-1:0]),
        .req(req),
        .demand_state(demand_state)     
    );

    control Control(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .req(req),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .state(state_dataBus)
    );

    assign LED = demand_state;
    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8'hff};
    assign signal_dataBus = {running_state[3:0], door_state[3:0], `INVALID, `INVALID};
    num_segMsg    numbers(clk380hz, number_dataBus, posL, segL);
    signal_segMsg signals(clk380hz, signal_dataBus, posH, segH);

endmodule