data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_jtag.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_jtag.v:52: Cannot find include file: ../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh.sv\n             ../../../lib/rfnoc/core/ctrlport.vh\n             ../../../lib/rfnoc/core/ctrlport.vh.v\n             ../../../lib/rfnoc/core/ctrlport.vh.sv\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh.v\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_jtag.v:53: Cannot find include file: ./regmap/jtag_regmap_utils.vh\n  `include "./regmap/jtag_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ctrlport_to_jtag #(
  parameter BASE_ADDRESS      = 0,
  parameter DEFAULT_PRESCALAR = 0
) (




  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  output reg         s_ctrlport_resp_ack,

  output reg  [ 1:0] s_ctrlport_resp_status = 0,
  output reg  [31:0] s_ctrlport_resp_data   = 0,





  output wire tck,
  output wire tdi,
  input  wire tdo,
  output wire tms
);

  `include "../../../lib/rfnoc/core/ctrlport.vh"
  `include "./regmap/jtag_regmap_utils.vh"





  reg [  TX_DATA_SIZE-1:0] tx_data_reg;
  reg [ STB_DATA_SIZE-1:0] stb_data_reg;
  reg [PRESCALAR_SIZE-1:0] prescalar_reg = DEFAULT_PRESCALAR;
  reg [   LENGTH_SIZE-1:0] length_reg;
  reg                      start_reg;
  reg                      soft_rst_stb_reg;





  wire [31:0] rd_data;
  wire        ready;





  localparam NUM_ADDRESSES = 32;
  wire address_in_range   = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                            (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
  wire soft_rst_requested = (s_ctrlport_req_addr == BASE_ADDRESS + CONTROL) &&
                            (s_ctrlport_req_data[RESET] == 1'b1);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      tx_data_reg         <= {TX_DATA_SIZE {1'b0}};
      stb_data_reg        <= {STB_DATA_SIZE {1'b0}};
      prescalar_reg       <= DEFAULT_PRESCALAR;
      length_reg          <= {LENGTH_SIZE {1'b0}};
      start_reg           <= 1'b0;
      soft_rst_stb_reg    <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;

    end else begin

      start_reg        <= 1'b0;
      soft_rst_stb_reg <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_data   <= {CTRLPORT_DATA_W{1'bx}};
        s_ctrlport_resp_status <= CTRL_STS_OKAY;






        if (soft_rst_requested) begin
          soft_rst_stb_reg <= 1'b1;

        end else if (ready) begin
          case (s_ctrlport_req_addr)
            BASE_ADDRESS + TX_DATA: begin
              tx_data_reg <= s_ctrlport_req_data;
            end

            BASE_ADDRESS + STB_DATA: begin
              stb_data_reg <= s_ctrlport_req_data;
            end

            BASE_ADDRESS + CONTROL: begin
              length_reg <= s_ctrlport_req_data[LENGTH_MSB:LENGTH];
              prescalar_reg <= s_ctrlport_req_data[PRESCALAR_MSB:PRESCALAR];




              start_reg <= (s_ctrlport_req_data[RESET] == 1'b0);
            end


            default: begin
              if (address_in_range) begin
                s_ctrlport_resp_status <= CTRL_STS_CMDERR;


              end else begin
                s_ctrlport_resp_ack <= 1'b0;
              end
            end
          endcase


        end else begin
          s_ctrlport_resp_status <= CTRL_STS_CMDERR;
        end


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RX_DATA: begin
            s_ctrlport_resp_data <= rd_data;
          end

          BASE_ADDRESS + CONTROL: begin
            s_ctrlport_resp_data                          <= {CTRLPORT_DATA_W {1'b0}};
            s_ctrlport_resp_data[LENGTH_MSB:LENGTH]       <= length_reg;
            s_ctrlport_resp_data[PRESCALAR_MSB:PRESCALAR] <= prescalar_reg;
            s_ctrlport_resp_data[READY]                   <= ready;
          end


          default: begin
            s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end







  wire bitq_resetn = ~(ctrlport_rst | soft_rst_stb_reg);

  bitq_fsm #(
    .IDLE_VALUE (1'b0)
  ) jtag_master (
    .clk       (ctrlport_clk),
    .rstn      (bitq_resetn),
    .prescalar (prescalar_reg),
    .bit_clk   (tck),
    .bit_in    (tdo),
    .bit_out   (tdi),
    .bit_stb   (tms),
    .start     (start_reg),
    .ready     (ready),
    .len       (length_reg),
    .wr_data   (tx_data_reg),
    .stb_data  (stb_data_reg),
    .rd_data   (rd_data)
  );

endmodule
module ctrlport_to_jtag #(
  parameter BASE_ADDRESS      = 0,
  parameter DEFAULT_PRESCALAR = 0
) (




  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  output reg         s_ctrlport_resp_ack,

  output reg  [ 1:0] s_ctrlport_resp_status = 0,
  output reg  [31:0] s_ctrlport_resp_data   = 0,





  output wire tck,
  output wire tdi,
  input  wire tdo,
  output wire tms
);


  `include "../../../lib/rfnoc/core/ctrlport.vh"
  `include "./regmap/jtag_regmap_utils.vh"





  reg [  TX_DATA_SIZE-1:0] tx_data_reg;
  reg [ STB_DATA_SIZE-1:0] stb_data_reg;
  reg [PRESCALAR_SIZE-1:0] prescalar_reg = DEFAULT_PRESCALAR;
  reg [   LENGTH_SIZE-1:0] length_reg;
  reg                      start_reg;
  reg                      soft_rst_stb_reg;





  wire [31:0] rd_data;
  wire        ready;





  localparam NUM_ADDRESSES = 32;
  wire address_in_range   = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                            (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
  wire soft_rst_requested = (s_ctrlport_req_addr == BASE_ADDRESS + CONTROL) &&
                            (s_ctrlport_req_data[RESET] == 1'b1);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      tx_data_reg         <= {TX_DATA_SIZE {1'b0}};
      stb_data_reg        <= {STB_DATA_SIZE {1'b0}};
      prescalar_reg       <= DEFAULT_PRESCALAR;
      length_reg          <= {LENGTH_SIZE {1'b0}};
      start_reg           <= 1'b0;
      soft_rst_stb_reg    <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;

    end else begin

      start_reg        <= 1'b0;
      soft_rst_stb_reg <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_data   <= {CTRLPORT_DATA_W{1'bx}};
        s_ctrlport_resp_status <= CTRL_STS_OKAY;






        if (soft_rst_requested) begin
          soft_rst_stb_reg <= 1'b1;

        end else if (ready) begin
          case (s_ctrlport_req_addr)
            BASE_ADDRESS + TX_DATA: begin
              tx_data_reg <= s_ctrlport_req_data;
            end

            BASE_ADDRESS + STB_DATA: begin
              stb_data_reg <= s_ctrlport_req_data;
            end

            BASE_ADDRESS + CONTROL: begin
              length_reg <= s_ctrlport_req_data[LENGTH_MSB:LENGTH];
              prescalar_reg <= s_ctrlport_req_data[PRESCALAR_MSB:PRESCALAR];




              start_reg <= (s_ctrlport_req_data[RESET] == 1'b0);
            end


            default: begin
              if (address_in_range) begin
                s_ctrlport_resp_status <= CTRL_STS_CMDERR;


              end else begin
                s_ctrlport_resp_ack <= 1'b0;
              end
            end
          endcase


        end else begin
          s_ctrlport_resp_status <= CTRL_STS_CMDERR;
        end


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RX_DATA: begin
            s_ctrlport_resp_data <= rd_data;
          end

          BASE_ADDRESS + CONTROL: begin
            s_ctrlport_resp_data                          <= {CTRLPORT_DATA_W {1'b0}};
            s_ctrlport_resp_data[LENGTH_MSB:LENGTH]       <= length_reg;
            s_ctrlport_resp_data[PRESCALAR_MSB:PRESCALAR] <= prescalar_reg;
            s_ctrlport_resp_data[READY]                   <= ready;
          end


          default: begin
            s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end







  wire bitq_resetn = ~(ctrlport_rst | soft_rst_stb_reg);

  bitq_fsm #(
    .IDLE_VALUE (1'b0)
  ) jtag_master (
    .clk       (ctrlport_clk),
    .rstn      (bitq_resetn),
    .prescalar (prescalar_reg),
    .bit_clk   (tck),
    .bit_in    (tdo),
    .bit_out   (tdi),
    .bit_stb   (tms),
    .start     (start_reg),
    .ready     (ready),
    .len       (length_reg),
    .wr_data   (tx_data_reg),
    .stb_data  (stb_data_reg),
    .rd_data   (rd_data)
  );

endmodule