data/full_repos/permissive/445455582/single/RiSC16_memory.v
1: b'%Error: data/full_repos/permissive/445455582/single/RiSC16_memory.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module RiSC16_memory #(
    parameter WORD_LENGTH = 16,
    parameter MEM_SIZE = 65536
) (
    dataOut, address, dataIn, clk, writeEn, rst
);

    input [WORD_LENGTH - 1 : 0] address;
    output reg [WORD_LENGTH - 1 : 0] dataOut;
    input writeEn;
    input [WORD_LENGTH - 1 : 0] dataIn;
    input clk;
    input rst;

    reg [WORD_LENGTH - 1 : 0] memoryArray [0 : MEM_SIZE - 1];

    integer i;
    
    always @(*) begin
        dataOut <= memoryArray[address];
    end

    always @(negedge clk) begin
        if(rst)
            for (i = 0; i < MEM_SIZE; i = i + 1) begin
                memoryArray[i] <= 0;
            end
        else if(writeEn)
            memoryArray[address] <= dataIn;
    end

endmodule
module RiSC16_memory #(
    parameter WORD_LENGTH = 16,
    parameter MEM_SIZE = 65536
) (
    dataOut, address, dataIn, clk, writeEn, rst
);


    input [WORD_LENGTH - 1 : 0] address;
    output reg [WORD_LENGTH - 1 : 0] dataOut;
    input writeEn;
    input [WORD_LENGTH - 1 : 0] dataIn;
    input clk;
    input rst;

    reg [WORD_LENGTH - 1 : 0] memoryArray [0 : MEM_SIZE - 1];

    integer i;
    
    always @(*) begin
        dataOut <= memoryArray[address];
    end

    always @(negedge clk) begin
        if(rst)
            for (i = 0; i < MEM_SIZE; i = i + 1) begin
                memoryArray[i] <= 0;
            end
        else if(writeEn)
            memoryArray[address] <= dataIn;
    end

endmodule