data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v
1: b"%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:46: Cannot find file containing module: 'display_clk'\n    display_clk C1(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/display_clk\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/display_clk.v\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/display_clk.sv\n             display_clk\n             display_clk.v\n             display_clk.sv\n             obj_dir/display_clk\n             obj_dir/display_clk.v\n             obj_dir/display_clk.sv\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:56: Cannot find file containing module: 'data_controller'\n    data_controller C0_X(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:66: Cannot find file containing module: 'data_controller'\n    data_controller C0_Y(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:76: Cannot find file containing module: 'data_controller'\n    data_controller C0_Z(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:86: Cannot find file containing module: 'data_controller'\n    data_controller C0_T(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_formatter.v:104: Cannot find file containing module: 'data_controller'\n    data_controller C0_X_ACC(\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module data_formatter
    (
        input wire GCLK,
        input wire RST,
        input wire dec,
        input wire [7:0] temp_data_in,
        input wire [15:0] x_axis_in,
        input wire [15:0] y_axis_in,
        input wire [15:0] z_axis_in,
        output wire [15:0] x_axis_out,
        output wire [15:0] y_axis_out,
        output wire [15:0] z_axis_out,
        output wire [15:0] temp_data_out,

        output wire [15:0] ang_x,
        output wire [15:0] ang_y,
        output wire [15:0] ang_z        
    );
    



    wire dclk;
    display_clk C1(
                .clk(GCLK),
                .RST(RST),
                .dclk(dclk)
    );
    




    data_controller C0_X(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b00),
                .data(x_axis_in),
                .frmt(x_axis_out)
    );
    
    data_controller C0_Y(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b01),
                .data(y_axis_in),
                .frmt(y_axis_out)
    );
    
    data_controller C0_Z(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b10),
                .data(z_axis_in),
                .frmt(z_axis_out)
    );
    
    data_controller C0_T(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b11),
                .data({8'd0, temp_data_in}),
                .frmt(temp_data_out)
    );
      
      
    reg [15:0] ax_acc = 0;
    reg [15:0] ay_acc = 0;
    reg [15:0] az_acc = 0;
    always @(ang_x) begin
        ax_acc <= RST ? 0 : ax_acc + ang_x;
    end
    
    data_controller C0_X_ACC(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b00),
                .data(ax_acc),
                .frmt(ang_x)
    );    
    
                
endmodule
module data_formatter
    (
        input wire GCLK,
        input wire RST,
        input wire dec,
        input wire [7:0] temp_data_in,
        input wire [15:0] x_axis_in,
        input wire [15:0] y_axis_in,
        input wire [15:0] z_axis_in,
        output wire [15:0] x_axis_out,
        output wire [15:0] y_axis_out,
        output wire [15:0] z_axis_out,
        output wire [15:0] temp_data_out,

        output wire [15:0] ang_x,
        output wire [15:0] ang_y,
        output wire [15:0] ang_z        
    );

    



    wire dclk;
    display_clk C1(
                .clk(GCLK),
                .RST(RST),
                .dclk(dclk)
    );
    




    data_controller C0_X(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b00),
                .data(x_axis_in),
                .frmt(x_axis_out)
    );
    
    data_controller C0_Y(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b01),
                .data(y_axis_in),
                .frmt(y_axis_out)
    );
    
    data_controller C0_Z(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b10),
                .data(z_axis_in),
                .frmt(z_axis_out)
    );
    
    data_controller C0_T(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b11),
                .data({8'd0, temp_data_in}),
                .frmt(temp_data_out)
    );
      
      
    reg [15:0] ax_acc = 0;
    reg [15:0] ay_acc = 0;
    reg [15:0] az_acc = 0;
    always @(ang_x) begin
        ax_acc <= RST ? 0 : ax_acc + ang_x;
    end
    
    data_controller C0_X_ACC(
                .clk(GCLK),
                .dclk(dclk),
                .rst(RST),
                .display_sel(dec),
                .sel(2'b00),
                .data(ax_acc),
                .frmt(ang_x)
    );    
    
                
endmodule