data/full_repos/permissive/406635962/src/rtl/exu_disp.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:7: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:20: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:21: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:22: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:23: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] disp_i_rs1,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:24: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] disp_i_rs2,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:25: Define or directive not defined: \'`DECINFO_WIDTH\'\n    input [`DECINFO_WIDTH-1:0] disp_i_info,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:26: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] disp_i_imm,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:27: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] disp_i_pc,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:36: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] disp_o_alu_rs1,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:37: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] disp_o_alu_rs2,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:39: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:40: Define or directive not defined: \'`DECINFO_WIDTH\'\n    output [`DECINFO_WIDTH-1:0] disp_o_alu_info,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:41: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] disp_o_alu_imm,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:42: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] disp_o_alu_pc,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:43: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] disp_o_alu_itag,  \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:50: Define or directive not defined: \'`ITAG_WIDTH\'\n    input [`ITAG_WIDTH-1:0] disp_oitf_ptr, \n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:59: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:60: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_disp.v:61: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] disp_oitf_rdidx\n            ^~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module exu_disp (
    input oitf_empty,
    input disp_i_valid,
    output disp_i_ready,
    



    input disp_i_rs1en,
    input disp_i_rs2en,
    input disp_i_rdwen,
    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,
    input [`XLEN-1:0] disp_i_rs1,
    input [`XLEN-1:0] disp_i_rs2,
    input [`DECINFO_WIDTH-1:0] disp_i_info,
    input [`XLEN-1:0] disp_i_imm,
    input [`PC_SIZE-1:0] disp_i_pc,
    input disp_ilegl,


    output disp_o_alu_valid,
    input disp_o_alu_ready,

    input disp_o_alu_longpipe,
    
    output [`XLEN-1:0] disp_o_alu_rs1,
    output [`XLEN-1:0] disp_o_alu_rs2,
    output disp_o_alu_rdwen,
    output [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx,
    output [`DECINFO_WIDTH-1:0] disp_o_alu_info,
    output [`XLEN-1:0] disp_o_alu_imm,
    output [`PC_SIZE-1:0] disp_o_alu_pc,
    output [`ITAG_WIDTH-1:0] disp_o_alu_itag,
    output disp_o_alu_ilegl,
    

    input oitfrd_match_disprs1,
    input oitfrd_match_disprs2,
    input oitfrd_match_disprd,
    input [`ITAG_WIDTH-1:0] disp_oitf_ptr, 

    output disp_oitf_ena,
    input disp_oitf_ready,
    
    output  disp_oitf_rs1en,
    output disp_oitf_rs2en,
    output disp_oitf_rdwen,

    output [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx,
    output [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx,
    output [`RFIDX_WIDTH-1:0] disp_oitf_rdidx
);








wire raw_dep = oitfrd_match_disprs1 | oitfrd_match_disprs2;
wire waw_dep = oitfrd_match_disprd;
wire dep = raw_dep | waw_dep;

wire disp_condition = (~dep)
                                    & (disp_o_alu_longpipe ? disp_oitf_ready: 1'b1);

wire disp_i_valid_pos = disp_condition & disp_i_valid;
assign disp_i_ready = disp_condition & disp_o_alu_ready;
assign disp_o_alu_valid = disp_i_valid_pos;


assign disp_o_alu_rs1 = disp_i_rs1;
assign disp_o_alu_rs2 = disp_i_rs2;
assign disp_o_alu_rdwen = disp_i_rdwen;
assign disp_o_alu_rdidx = disp_i_rdidx;
assign disp_o_alu_info = disp_i_info;

assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_o_alu_longpipe;

assign disp_o_alu_imm = disp_i_imm;
assign disp_o_alu_pc = disp_i_pc;
assign disp_o_alu_itag = disp_oitf_ptr;
assign disp_o_alu_ilegl = disp_ilegl;


assign disp_oitf_rs1en = disp_i_rs1en;
assign disp_oitf_rs2en = disp_i_rs2en;
assign disp_oitf_rdwen = disp_i_rdwen;
assign disp_oitf_rs1idx = disp_i_rs1idx;
assign disp_oitf_rs2idx = disp_i_rs2idx;
assign disp_oitf_rdidx = disp_i_rdidx;
endmodule
module exu_disp (
    input oitf_empty,
    input disp_i_valid,
    output disp_i_ready,
    



    input disp_i_rs1en,
    input disp_i_rs2en,
    input disp_i_rdwen,
    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,
    input [`XLEN-1:0] disp_i_rs1,
    input [`XLEN-1:0] disp_i_rs2,
    input [`DECINFO_WIDTH-1:0] disp_i_info,
    input [`XLEN-1:0] disp_i_imm,
    input [`PC_SIZE-1:0] disp_i_pc,
    input disp_ilegl,


    output disp_o_alu_valid,
    input disp_o_alu_ready,

    input disp_o_alu_longpipe,
    
    output [`XLEN-1:0] disp_o_alu_rs1,
    output [`XLEN-1:0] disp_o_alu_rs2,
    output disp_o_alu_rdwen,
    output [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx,
    output [`DECINFO_WIDTH-1:0] disp_o_alu_info,
    output [`XLEN-1:0] disp_o_alu_imm,
    output [`PC_SIZE-1:0] disp_o_alu_pc,
    output [`ITAG_WIDTH-1:0] disp_o_alu_itag,
    output disp_o_alu_ilegl,
    

    input oitfrd_match_disprs1,
    input oitfrd_match_disprs2,
    input oitfrd_match_disprd,
    input [`ITAG_WIDTH-1:0] disp_oitf_ptr, 

    output disp_oitf_ena,
    input disp_oitf_ready,
    
    output  disp_oitf_rs1en,
    output disp_oitf_rs2en,
    output disp_oitf_rdwen,

    output [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx,
    output [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx,
    output [`RFIDX_WIDTH-1:0] disp_oitf_rdidx
);









wire raw_dep = oitfrd_match_disprs1 | oitfrd_match_disprs2;
wire waw_dep = oitfrd_match_disprd;
wire dep = raw_dep | waw_dep;

wire disp_condition = (~dep)
                                    & (disp_o_alu_longpipe ? disp_oitf_ready: 1'b1);

wire disp_i_valid_pos = disp_condition & disp_i_valid;
assign disp_i_ready = disp_condition & disp_o_alu_ready;
assign disp_o_alu_valid = disp_i_valid_pos;


assign disp_o_alu_rs1 = disp_i_rs1;
assign disp_o_alu_rs2 = disp_i_rs2;
assign disp_o_alu_rdwen = disp_i_rdwen;
assign disp_o_alu_rdidx = disp_i_rdidx;
assign disp_o_alu_info = disp_i_info;

assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_o_alu_longpipe;

assign disp_o_alu_imm = disp_i_imm;
assign disp_o_alu_pc = disp_i_pc;
assign disp_o_alu_itag = disp_oitf_ptr;
assign disp_o_alu_ilegl = disp_ilegl;


assign disp_oitf_rs1en = disp_i_rs1en;
assign disp_oitf_rs2en = disp_i_rs2en;
assign disp_oitf_rdwen = disp_i_rdwen;
assign disp_oitf_rs1idx = disp_i_rs1idx;
assign disp_oitf_rs2idx = disp_i_rs2idx;
assign disp_oitf_rdidx = disp_i_rdidx;
endmodule