data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv
1: b"%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport mult_types::*;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:19: syntax error, unexpected '@', expecting ';'\ndefault clocking tb_clk @(negedge itf.clk); endclocking\n                        ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:29: syntax error, unexpected <=, expecting IDENTIFIER\n    itf.reset_n <= 1'b0;\n                ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:31: syntax error, unexpected <=, expecting IDENTIFIER\n    itf.reset_n <= 1'b1;\n                ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:36: syntax error, unexpected <=, expecting IDENTIFIER\n itf.start <= 1'b1;\n           ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:42: syntax error, unexpected '(', expecting IDENTIFIER\n  reset();\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:49: syntax error, unexpected int, expecting IDENTIFIER or genvar\n for(int i = 0; i < 256; ++i) begin\n     ^~~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:52: syntax error, unexpected <=, expecting IDENTIFIER\n   itf.multiplier <= j;\n                  ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:53: syntax error, unexpected <=, expecting IDENTIFIER\n   itf.start <= 1'b1;\n             ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hvl/testbench.sv:76: syntax error, unexpected '(', expecting IDENTIFIER\n    itf.tb_report_dut_error(error);\n                            ^~~~~\n%Error: Exiting due to 10 error(s)\n"
module testbench(multiplier_itf.testbench itf);

add_shift_multiplier dut (
    .clk_i          ( itf.clk          ),
    .reset_n_i      ( itf.reset_n      ),
    .multiplicand_i ( itf.multiplicand ),
    .multiplier_i   ( itf.multiplier   ),
    .start_i        ( itf.start        ),
    .ready_o        ( itf.rdy          ),
    .product_o      ( itf.product      ),
    .done_o         ( itf.done         )
);

assign itf.mult_op = dut.ms.op;
default clocking tb_clk @(negedge itf.clk); endclocking








task reset();
    itf.reset_n <= 1'b0;
    ##5;
    itf.reset_n <= 1'b1;
    ##1;
endtask : reset

task run_start();
	itf.start <= 1'b1;
	@(tb_clk iff(itf.mult_op == ADD));
endtask : run_start

task run_reset();
	if(itf.mult_op == ADD) begin
		reset();
	end
	@(tb_clk iff(itf.mult_op == SHIFT));
	reset();
endtask : run_reset

task combination();
	for(int i = 0; i < 256; ++i) begin
		for(int j = 0; j < 256; ++j) begin
			itf.multiplicand <= i;
			itf.multiplier <= j;
			itf.start <= 1'b1;
			@(tb_clk iff(itf.done));
			assert (itf.product == (i * j))
			  else begin
				 $error ("%0d: %0t: BAD_PRODUCT error detected", `__LINE__, $time);
				 report_error (BAD_PRODUCT);
			  end
			assert (itf.rdy == 1'b1)
				else begin
					$error ("%0d: %0t: NOT_READY error detected", `__LINE__, $time);
					report_error (NOT_READY);
				end
			@(tb_clk iff(itf.rdy));			 
		end
	end
	run_start();
	run_reset();
endtask : combination




function void report_error(error_e error);
    itf.tb_report_dut_error(error);
endfunction : report_error


initial itf.reset_n = 1'b0;
initial begin
    reset();

	 
	 assert (itf.rdy == 1'b1)
		else begin
			$error ("%0d: %0t: NOT_READY error detected", `__LINE__, $time);
			report_error (NOT_READY);
		end
	 
	 combination();
    

    itf.finish();

    $error("Improper Simulation Exit");
end


endmodule
module testbench(multiplier_itf.testbench itf);


add_shift_multiplier dut (
    .clk_i          ( itf.clk          ),
    .reset_n_i      ( itf.reset_n      ),
    .multiplicand_i ( itf.multiplicand ),
    .multiplier_i   ( itf.multiplier   ),
    .start_i        ( itf.start        ),
    .ready_o        ( itf.rdy          ),
    .product_o      ( itf.product      ),
    .done_o         ( itf.done         )
);

assign itf.mult_op = dut.ms.op;
default clocking tb_clk @(negedge itf.clk); endclocking








task reset();
    itf.reset_n <= 1'b0;
    ##5;
    itf.reset_n <= 1'b1;
    ##1;
endtask : reset

task run_start();
	itf.start <= 1'b1;
	@(tb_clk iff(itf.mult_op == ADD));
endtask : run_start

task run_reset();
	if(itf.mult_op == ADD) begin
		reset();
	end
	@(tb_clk iff(itf.mult_op == SHIFT));
	reset();
endtask : run_reset

task combination();
	for(int i = 0; i < 256; ++i) begin
		for(int j = 0; j < 256; ++j) begin
			itf.multiplicand <= i;
			itf.multiplier <= j;
			itf.start <= 1'b1;
			@(tb_clk iff(itf.done));
			assert (itf.product == (i * j))
			  else begin
				 $error ("%0d: %0t: BAD_PRODUCT error detected", `__LINE__, $time);
				 report_error (BAD_PRODUCT);
			  end
			assert (itf.rdy == 1'b1)
				else begin
					$error ("%0d: %0t: NOT_READY error detected", `__LINE__, $time);
					report_error (NOT_READY);
				end
			@(tb_clk iff(itf.rdy));			 
		end
	end
	run_start();
	run_reset();
endtask : combination




function void report_error(error_e error);
    itf.tb_report_dut_error(error);
endfunction : report_error


initial itf.reset_n = 1'b0;
initial begin
    reset();

	 
	 assert (itf.rdy == 1'b1)
		else begin
			$error ("%0d: %0t: NOT_READY error detected", `__LINE__, $time);
			report_error (NOT_READY);
		end
	 
	 combination();
    

    itf.finish();

    $error("Improper Simulation Exit");
end


endmodule