data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:30: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:68: Define or directive not defined: \'`T0H_CYC\'\n    if (cnt == `T0H_CYC) begin\n               ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:68: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (cnt == `T0H_CYC) begin\n                       ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:74: Define or directive not defined: \'`T1H_CYC\'\n    if (cnt == `T1H_CYC) begin\n               ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (cnt == `T1H_CYC) begin\n                       ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder.v:79: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module ws2811Encoder (input		dataIn,
								dataClk,
								masterClk,
					  output    reg dataOut=1'b0);


	reg[7:0] cnt;
	reg countEn;
	reg nextDataOut;




	reg prevDataClk;
	always @ (posedge masterClk) begin
		prevDataClk <= dataClk;
	end
	`define ENCODE_DATACLK_POSEDGE (dataClk && !prevDataClk)
	`define ENCODE_DATACLK_NEGEDGE (!dataClk && prevDataClk)





	always @ (posedge masterClk) begin
		prevDataClk <= dataClk;
		if (`ENCODE_DATACLK_POSEDGE) begin
			nextDataOut <= dataIn;
			dataOut <= 1;
			cnt <= 0;
			countEn <= 1;
		end
		else if (countEn) begin
			cnt <= cnt + 1'b1;
			if (!nextDataOut) begin
				if (cnt == `T0H_CYC) begin
					dataOut <= 0;
					countEn <= 0;
				end
			end
			else begin
				if (cnt == `T1H_CYC) begin
					dataOut <= 0;
					countEn <= 0;
				end
			end
		end
	end

endmodule
module ws2811Encoder (input		dataIn,
								dataClk,
								masterClk,
					  output    reg dataOut=1'b0);



	reg[7:0] cnt;
	reg countEn;
	reg nextDataOut;




	reg prevDataClk;
	always @ (posedge masterClk) begin
		prevDataClk <= dataClk;
	end
	`define ENCODE_DATACLK_POSEDGE (dataClk && !prevDataClk)
	`define ENCODE_DATACLK_NEGEDGE (!dataClk && prevDataClk)





	always @ (posedge masterClk) begin
		prevDataClk <= dataClk;
		if (`ENCODE_DATACLK_POSEDGE) begin
			nextDataOut <= dataIn;
			dataOut <= 1;
			cnt <= 0;
			countEn <= 1;
		end
		else if (countEn) begin
			cnt <= cnt + 1'b1;
			if (!nextDataOut) begin
				if (cnt == `T0H_CYC) begin
					dataOut <= 0;
					countEn <= 0;
				end
			end
			else begin
				if (cnt == `T1H_CYC) begin
					dataOut <= 0;
					countEn <= 0;
				end
			end
		end
	end

endmodule