data/full_repos/permissive/487568919/basic_verilog/reset_set.sv
data/verilator_xmls/7bc35e16-7b28-4146-8793-8f0f90c5880b.xml
module reset_set(
  input clk,
  input nrst,
  input s,
  input r,
  output logic q = 0,
  output nq
);

always_ff @(posedge clk) begin
  if( ~nrst ) begin
    q = 0;
  end else begin
    if( r ) q = 1'b0;
    if( s ) q = 1'b1;
  end
end

assign nq = ~q;

endmodule
module reset_set(
  input clk,
  input nrst,
  input s,
  input r,
  output logic q = 0,
  output nq
);


always_ff @(posedge clk) begin
  if( ~nrst ) begin
    q = 0;
  end else begin
    if( r ) q = 1'b0;
    if( s ) q = 1'b1;
  end
end

assign nq = ~q;

endmodule