data/full_repos/permissive/454159683/mul3bc/mul3bc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454159683/mul3bc/mul3bc.v:11: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 3 bits.\n                                                                       : ... In instance mul3bc\n  if (y[0]) r0 = x;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul3bc/mul3bc.v:14: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                       : ... In instance mul3bc\n  if (y[1])r1 = {x, 1\'b0};\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module mul3bc(input[2:0] x, y, output[5:0] out);
	reg[4:0] r0, r1, r2;	

	always @(x or y)
	begin
		if (y[0]) r0 = x;
		else r0 = 0;
		
		if (y[1])r1 = {x, 1'b0};
		else r1 = 0;
		
		if (y[2]) r2  = {x, 2'b00};
		else r2 = 0;
	end
	assign out = r0 + r1 + r2;
	





















endmodule
module mul3bc(input[2:0] x, y, output[5:0] out);

	reg[4:0] r0, r1, r2;	

	always @(x or y)
	begin
		if (y[0]) r0 = x;
		else r0 = 0;
		
		if (y[1])r1 = {x, 1'b0};
		else r1 = 0;
		
		if (y[2]) r2  = {x, 2'b00};
		else r2 = 0;
	end
	assign out = r0 + r1 + r2;
	





















endmodule