data/full_repos/permissive/502544928/unified_caches.v
1: b"%Error: data/full_repos/permissive/502544928/unified_caches.v:114: Cannot find file containing module: 'cache_wrapper'\ncache_wrapper #((2*CORE), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/cache_wrapper\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/cache_wrapper.v\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/cache_wrapper.sv\n             cache_wrapper\n             cache_wrapper.v\n             cache_wrapper.sv\n             obj_dir/cache_wrapper\n             obj_dir/cache_wrapper.v\n             obj_dir/cache_wrapper.sv\n%Error: data/full_repos/permissive/502544928/unified_caches.v:129: Cannot find file containing module: 'cache_wrapper'\ncache_wrapper #(((2*CORE+1)), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) \n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module unified_caches #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, 
                     OFFSET_BITS = 3, ADDRESS_BITS = 20, MSG_BITS = 4)(
                     clock, reset,
                     
				     read, write, address, in_data, 
				     out_address, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 

					 report
 ); 

input clock, reset; 

input [1:0] read, write;
input [(2*ADDRESS_BITS)-1:0] address;
input [(2*DATA_WIDTH)-1:0] in_data;

output [1:0] valid, ready;
output [(2*ADDRESS_BITS)-1:0] out_address;
output[(2*DATA_WIDTH)-1:0] out_data;

input [(MSG_BITS * 2)-1:0]     mem2cache_msg; 
input [(ADDRESS_BITS * 2)-1:0] mem2cache_address; 
input [(DATA_WIDTH * 2)-1:0]   mem2cache_data;

output [(MSG_BITS * 2)-1:0]      cache2mem_msg; 
output [(ADDRESS_BITS * 2)-1:0] cache2mem_address; 
output [(DATA_WIDTH * 2)-1:0]   cache2mem_data;
input  report;

wire [MSG_BITS-1:0]      i_mem2cache_msg; 
wire [ADDRESS_BITS-1:0]  i_mem2cache_address; 
wire [DATA_WIDTH-1:0]    i_mem2cache_data;
 				     
wire [MSG_BITS-1:0]     i_cache2mem_msg; 
wire [ADDRESS_BITS-1:0] i_cache2mem_address; 
wire [DATA_WIDTH-1:0]   i_cache2mem_data;

wire [MSG_BITS-1:0]      d_mem2cache_msg; 
wire [ADDRESS_BITS-1:0]  d_mem2cache_address; 
wire [DATA_WIDTH-1:0]    d_mem2cache_data;
 				     
wire [MSG_BITS-1:0]     d_cache2mem_msg; 
wire [ADDRESS_BITS-1:0] d_cache2mem_address; 
wire [DATA_WIDTH-1:0]   d_cache2mem_data;

wire [ADDRESS_BITS-1:0]  i_address;
wire [ADDRESS_BITS-1:0]  d_address;
wire [DATA_WIDTH-1:0]    i_in_data;
wire [DATA_WIDTH-1:0]    d_in_data;
wire [ADDRESS_BITS-1:0]  i_out_addr;
wire [ADDRESS_BITS-1:0]  d_out_addr;
wire [DATA_WIDTH-1:0]    i_out_data;
wire [DATA_WIDTH-1:0]    d_out_data;

assign i_mem2cache_msg     = mem2cache_msg[(MSG_BITS-1) -: MSG_BITS]; 
assign i_mem2cache_address = mem2cache_address[(ADDRESS_BITS-1) -: ADDRESS_BITS]; 
assign i_mem2cache_data    = mem2cache_data[(DATA_WIDTH-1) -: DATA_WIDTH];
      		
assign cache2mem_msg[(MSG_BITS-1) -: MSG_BITS]            = i_cache2mem_msg;
assign cache2mem_address[(ADDRESS_BITS-1) -: ADDRESS_BITS]= i_cache2mem_address;
assign cache2mem_data[(DATA_WIDTH-1) -: DATA_WIDTH]       = i_cache2mem_data;  
	    
assign d_mem2cache_msg     = mem2cache_msg[((2*MSG_BITS)-1) -: MSG_BITS]; 
assign d_mem2cache_address = mem2cache_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS]; 
assign d_mem2cache_data    = mem2cache_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH];
      		
assign cache2mem_msg[((2*MSG_BITS)-1) -: MSG_BITS]             = d_cache2mem_msg;
assign cache2mem_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS] = d_cache2mem_address;
assign cache2mem_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH]        = d_cache2mem_data;

assign i_address  = address[(ADDRESS_BITS-1) -: ADDRESS_BITS];
assign d_address  = address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS];
	
assign i_in_data  = in_data[(DATA_WIDTH-1) -: DATA_WIDTH];
assign d_in_data  = in_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH];

assign out_address[(ADDRESS_BITS-1) -: ADDRESS_BITS] = i_out_addr;
assign out_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS] = d_out_addr;

assign out_data[(DATA_WIDTH-1) -: DATA_WIDTH]     = i_out_data ;
assign out_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH] = d_out_data;

cache_wrapper #((2*CORE), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             ICache (
				     clock, reset,
				       
				     read[0], write[0], i_address, i_in_data, 
				     i_out_addr, i_out_data, valid[0], ready[0],
				     
				     i_mem2cache_msg, 
				     i_mem2cache_address, i_mem2cache_data, 
				     
				     i_cache2mem_msg, 
				     i_cache2mem_address, i_cache2mem_data, 
					 report
);

cache_wrapper #(((2*CORE+1)), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             DCache (
				     clock, reset,
				       
				     read[1], write[1], d_address, d_in_data, 
				     d_out_addr, d_out_data, valid[1], ready[1],
				     
				     d_mem2cache_msg, 
				     d_mem2cache_address, d_mem2cache_data, 
				     
				     d_cache2mem_msg, 
				     d_cache2mem_address, d_cache2mem_data, 
					 report
);

endmodule
module unified_caches #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, 
                     OFFSET_BITS = 3, ADDRESS_BITS = 20, MSG_BITS = 4)(
                     clock, reset,
                     
				     read, write, address, in_data, 
				     out_address, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 

					 report
 );
 

input clock, reset; 

input [1:0] read, write;
input [(2*ADDRESS_BITS)-1:0] address;
input [(2*DATA_WIDTH)-1:0] in_data;

output [1:0] valid, ready;
output [(2*ADDRESS_BITS)-1:0] out_address;
output[(2*DATA_WIDTH)-1:0] out_data;

input [(MSG_BITS * 2)-1:0]     mem2cache_msg; 
input [(ADDRESS_BITS * 2)-1:0] mem2cache_address; 
input [(DATA_WIDTH * 2)-1:0]   mem2cache_data;

output [(MSG_BITS * 2)-1:0]      cache2mem_msg; 
output [(ADDRESS_BITS * 2)-1:0] cache2mem_address; 
output [(DATA_WIDTH * 2)-1:0]   cache2mem_data;
input  report;

wire [MSG_BITS-1:0]      i_mem2cache_msg; 
wire [ADDRESS_BITS-1:0]  i_mem2cache_address; 
wire [DATA_WIDTH-1:0]    i_mem2cache_data;
 				     
wire [MSG_BITS-1:0]     i_cache2mem_msg; 
wire [ADDRESS_BITS-1:0] i_cache2mem_address; 
wire [DATA_WIDTH-1:0]   i_cache2mem_data;

wire [MSG_BITS-1:0]      d_mem2cache_msg; 
wire [ADDRESS_BITS-1:0]  d_mem2cache_address; 
wire [DATA_WIDTH-1:0]    d_mem2cache_data;
 				     
wire [MSG_BITS-1:0]     d_cache2mem_msg; 
wire [ADDRESS_BITS-1:0] d_cache2mem_address; 
wire [DATA_WIDTH-1:0]   d_cache2mem_data;

wire [ADDRESS_BITS-1:0]  i_address;
wire [ADDRESS_BITS-1:0]  d_address;
wire [DATA_WIDTH-1:0]    i_in_data;
wire [DATA_WIDTH-1:0]    d_in_data;
wire [ADDRESS_BITS-1:0]  i_out_addr;
wire [ADDRESS_BITS-1:0]  d_out_addr;
wire [DATA_WIDTH-1:0]    i_out_data;
wire [DATA_WIDTH-1:0]    d_out_data;

assign i_mem2cache_msg     = mem2cache_msg[(MSG_BITS-1) -: MSG_BITS]; 
assign i_mem2cache_address = mem2cache_address[(ADDRESS_BITS-1) -: ADDRESS_BITS]; 
assign i_mem2cache_data    = mem2cache_data[(DATA_WIDTH-1) -: DATA_WIDTH];
      		
assign cache2mem_msg[(MSG_BITS-1) -: MSG_BITS]            = i_cache2mem_msg;
assign cache2mem_address[(ADDRESS_BITS-1) -: ADDRESS_BITS]= i_cache2mem_address;
assign cache2mem_data[(DATA_WIDTH-1) -: DATA_WIDTH]       = i_cache2mem_data;  
	    
assign d_mem2cache_msg     = mem2cache_msg[((2*MSG_BITS)-1) -: MSG_BITS]; 
assign d_mem2cache_address = mem2cache_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS]; 
assign d_mem2cache_data    = mem2cache_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH];
      		
assign cache2mem_msg[((2*MSG_BITS)-1) -: MSG_BITS]             = d_cache2mem_msg;
assign cache2mem_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS] = d_cache2mem_address;
assign cache2mem_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH]        = d_cache2mem_data;

assign i_address  = address[(ADDRESS_BITS-1) -: ADDRESS_BITS];
assign d_address  = address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS];
	
assign i_in_data  = in_data[(DATA_WIDTH-1) -: DATA_WIDTH];
assign d_in_data  = in_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH];

assign out_address[(ADDRESS_BITS-1) -: ADDRESS_BITS] = i_out_addr;
assign out_address[((2*ADDRESS_BITS)-1) -: ADDRESS_BITS] = d_out_addr;

assign out_data[(DATA_WIDTH-1) -: DATA_WIDTH]     = i_out_data ;
assign out_data[((2*DATA_WIDTH)-1) -: DATA_WIDTH] = d_out_data;

cache_wrapper #((2*CORE), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             ICache (
				     clock, reset,
				       
				     read[0], write[0], i_address, i_in_data, 
				     i_out_addr, i_out_data, valid[0], ready[0],
				     
				     i_mem2cache_msg, 
				     i_mem2cache_address, i_mem2cache_data, 
				     
				     i_cache2mem_msg, 
				     i_cache2mem_address, i_cache2mem_data, 
					 report
);

cache_wrapper #(((2*CORE+1)), DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             DCache (
				     clock, reset,
				       
				     read[1], write[1], d_address, d_in_data, 
				     d_out_addr, d_out_data, valid[1], ready[1],
				     
				     d_mem2cache_msg, 
				     d_mem2cache_address, d_mem2cache_data, 
				     
				     d_cache2mem_msg, 
				     d_cache2mem_address, d_cache2mem_data, 
					 report
);

endmodule