data/full_repos/permissive/480681467/Source/TB/mod_exp_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/mod_exp_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/mod_exp_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/mod_exp_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/480681467/Source/TB/mod_exp_tb.v:13: Cannot find file containing module: \'mod_exp\'\n mod_exp uut(base,modulo,exponent,clk,reset,finish,result);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/mod_exp\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/mod_exp.v\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/mod_exp.sv\n             mod_exp\n             mod_exp.v\n             mod_exp.sv\n             obj_dir/mod_exp\n             obj_dir/mod_exp.v\n             obj_dir/mod_exp.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mod_exp;
    
    reg [`WIDTH*2-1:0] base;
	reg [`WIDTH*2-1:0] modulo;
	reg [`WIDTH*2-1:0] exponent;
	reg clk;
	reg reset;
	wire finish;
	wire [`WIDTH*2-1:0] result;
	
	mod_exp uut(base,modulo,exponent,clk,reset,finish,result);
	defparam uut.WIDTH = `WIDTH;
	
	initial begin
	   base = 5;
	   modulo = 13;
	   exponent =  567;
	   clk = 0;
	   reset = 0;
	   #10 reset = 1;
	   #10 reset = 0;
	end
	
	always #5 clk = ~clk;
endmodule
module tb_mod_exp;

    
    reg [`WIDTH*2-1:0] base;
	reg [`WIDTH*2-1:0] modulo;
	reg [`WIDTH*2-1:0] exponent;
	reg clk;
	reg reset;
	wire finish;
	wire [`WIDTH*2-1:0] result;
	
	mod_exp uut(base,modulo,exponent,clk,reset,finish,result);
	defparam uut.WIDTH = `WIDTH;
	
	initial begin
	   base = 5;
	   modulo = 13;
	   exponent =  567;
	   clk = 0;
	   reset = 0;
	   #10 reset = 1;
	   #10 reset = 0;
	end
	
	always #5 clk = ~clk;
endmodule