data/full_repos/permissive/525349297/lpc_host.v
1: b'%Error: data/full_repos/permissive/525349297/lpc_host.v:28: Cannot find include file: lpc_defines.v\n`include "lpc_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525349297,data/full_repos/permissive/525349297/lpc_defines.v\n             data/full_repos/permissive/525349297,data/full_repos/permissive/525349297/lpc_defines.v.v\n             data/full_repos/permissive/525349297,data/full_repos/permissive/525349297/lpc_defines.v.sv\n             lpc_defines.v\n             lpc_defines.v.v\n             lpc_defines.v.sv\n             obj_dir/lpc_defines.v\n             obj_dir/lpc_defines.v.v\n             obj_dir/lpc_defines.v.sv\n%Error: data/full_repos/permissive/525349297/lpc_host.v:75: Define or directive not defined: \'`LPC_ST_FORCE_RESET\'\n        if (fsm_host_state == `LPC_ST_FORCE_RESET) begin\n                              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (fsm_host_state == `LPC_ST_FORCE_RESET) begin\n                                                 ^\n%Error: data/full_repos/permissive/525349297/lpc_host.v:83: syntax error, unexpected else\n        else begin\n        ^~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:89: Define or directive not defined: \'`LPC_ST_IDLE\'\n            fsm_host_state = `LPC_ST_IDLE;\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:92: Define or directive not defined: \'`LPC_ST_IDLE\'\n        else if (fsm_host_state == `LPC_ST_IDLE) begin\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:98: Define or directive not defined: \'`LPC_ST_START\'\n            fsm_host_state = `LPC_ST_START;\n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:102: Define or directive not defined: \'`LPC_ST_START\'\n        else if (fsm_host_state == `LPC_ST_START) begin\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:107: Define or directive not defined: \'`LPC_ST_CYCTYPE_RD\'\n                    fsm_host_state = `LPC_ST_CYCTYPE_RD;\n                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:112: Define or directive not defined: \'`LPC_ST_CYCTYPE_WR\'\n                    fsm_host_state = `LPC_ST_CYCTYPE_WR;\n                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:118: Define or directive not defined: \'`LPC_ST_CYCTYPE_MEMORY_RD\'\n                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_RD;\n                                     ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:123: Define or directive not defined: \'`LPC_ST_CYCTYPE_MEMORY_WR\'\n                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_WR;\n                                     ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:127: Define or directive not defined: \'`LPC_ST_CYCTYPE_RD\'\n        else if ((fsm_host_state == `LPC_ST_CYCTYPE_RD) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_RD)) begin\n                                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:127: Define or directive not defined: \'`LPC_ST_CYCTYPE_MEMORY_RD\'\n        else if ((fsm_host_state == `LPC_ST_CYCTYPE_RD) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_RD)) begin\n                                                                              ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:129: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK1\'\n            fsm_host_state = `LPC_ST_ADDR_RD_CLK1;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:131: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK1\'\n        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK1) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:133: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK2\'\n            fsm_host_state = `LPC_ST_ADDR_RD_CLK2;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:135: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK2\'\n        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK2) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:137: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK3\'\n           fsm_host_state = `LPC_ST_ADDR_RD_CLK3;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:139: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK3\'\n        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK3) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:141: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK4\'\n            fsm_host_state = `LPC_ST_ADDR_RD_CLK4;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:143: Define or directive not defined: \'`LPC_ST_ADDR_RD_CLK4\'\n        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK4) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:145: Define or directive not defined: \'`LPC_ST_TAR_RD_CLK1\'\n            fsm_host_state = `LPC_ST_TAR_RD_CLK1;\n                             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:147: Define or directive not defined: \'`LPC_ST_TAR_RD_CLK1\'\n        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK1) begin\n                                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:149: Define or directive not defined: \'`LPC_ST_TAR_RD_CLK2\'\n            fsm_host_state = `LPC_ST_TAR_RD_CLK2;\n                             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:151: Define or directive not defined: \'`LPC_ST_TAR_RD_CLK2\'\n        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK2) begin\n                                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:152: Define or directive not defined: \'`LPC_ST_SYNC_RD\'\n            fsm_host_state = `LPC_ST_SYNC_RD;\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:154: Define or directive not defined: \'`LPC_ST_SYNC_RD\'\n        else if (fsm_host_state == `LPC_ST_SYNC_RD) begin\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:156: Define or directive not defined: \'`LPC_ST_DATA_RD_CLK1\'\n            fsm_host_state    = `LPC_ST_DATA_RD_CLK1;\n                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:157: syntax error, unexpected \'=\', expecting IDENTIFIER\n            if (lad_reg == 4\'b0000) fsm_host_state = `LPC_ST_DATA_RD_CLK1;\n                                                   ^\n%Error: data/full_repos/permissive/525349297/lpc_host.v:157: Define or directive not defined: \'`LPC_ST_DATA_RD_CLK1\'\n            if (lad_reg == 4\'b0000) fsm_host_state = `LPC_ST_DATA_RD_CLK1;\n                                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:159: syntax error, unexpected \'=\', expecting IDENTIFIER\n                LPC_LRESET = 0;\n                           ^\n%Error: data/full_repos/permissive/525349297/lpc_host.v:164: Define or directive not defined: \'`LPC_ST_FORCE_RESET\'\n                fsm_host_state = `LPC_ST_FORCE_RESET;\n                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:167: Define or directive not defined: \'`LPC_ST_DATA_RD_CLK1\'\n        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK1) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:169: Define or directive not defined: \'`LPC_ST_DATA_RD_CLK2\'\n            fsm_host_state = `LPC_ST_DATA_RD_CLK2;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:171: Define or directive not defined: \'`LPC_ST_DATA_RD_CLK2\'\n        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK2) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:172: Define or directive not defined: \'`LPC_ST_FINAL_TAR_CLK1\'\n            fsm_host_state = `LPC_ST_FINAL_TAR_CLK1;\n                             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:174: Define or directive not defined: \'`LPC_ST_CYCTYPE_WR\'\n        else if ((fsm_host_state == `LPC_ST_CYCTYPE_WR) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_WR)) begin\n                                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:174: Define or directive not defined: \'`LPC_ST_CYCTYPE_MEMORY_WR\'\n        else if ((fsm_host_state == `LPC_ST_CYCTYPE_WR) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_WR)) begin\n                                                                              ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:176: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK1\'\n            fsm_host_state = `LPC_ST_ADDR_WR_CLK1;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:178: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK1\'\n        else if (fsm_host_state ==  `LPC_ST_ADDR_WR_CLK1) begin\n                                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:180: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK2\'\n            fsm_host_state = `LPC_ST_ADDR_WR_CLK2;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:182: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK2\'\n        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK2) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:184: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK3\'\n            fsm_host_state = `LPC_ST_ADDR_WR_CLK3;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:186: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK3\'\n        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK3) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:188: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK4\'\n           fsm_host_state = `LPC_ST_ADDR_WR_CLK4;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:190: Define or directive not defined: \'`LPC_ST_ADDR_WR_CLK4\'\n        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK4) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:192: Define or directive not defined: \'`LPC_ST_DATA_WR_CLK1\'\n            fsm_host_state = `LPC_ST_DATA_WR_CLK1;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:194: Define or directive not defined: \'`LPC_ST_DATA_WR_CLK1\'\n        else if (fsm_host_state == `LPC_ST_DATA_WR_CLK1) begin\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_host.v:196: Define or directive not defined: \'`LPC_ST_DATA_WR_CLK2\'\n            fsm_host_state = `LPC_ST_DATA_WR_CLK2;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module lpc_host (clk_i, ctrl_addr_i, ctrl_data_i, ctrl_nrst_i, ctrl_lframe_i,
                 ctrl_rd_status_i, ctrl_wr_status_i, ctrl_memory_cycle_i,
                 ctrl_data_o, ctrl_ready_o, ctrl_host_state_o,
                 LPC_LAD, LPC_LCLK, LPC_LRESET, LPC_LFRAME
);

    input  wire        clk_i;



    input  wire [15:0] ctrl_addr_i;
    input  wire [ 7:0] ctrl_data_i;
    input  wire        ctrl_nrst_i;
    input  wire        ctrl_lframe_i;
    input  wire        ctrl_rd_status_i;
    input  wire        ctrl_wr_status_i;
    input  wire        ctrl_memory_cycle_i;


    output reg  [ 7:0] ctrl_data_o;
    output reg         ctrl_ready_o;
    output wire [ 4:0] ctrl_host_state_o;


    inout  wire [ 3:0] LPC_LAD;
    output wire        LPC_LCLK;
    output reg         LPC_LRESET;
    output reg         LPC_LFRAME;


    reg [4:0] fsm_host_state;


    reg       lad_en;
    reg [3:0] lad_out;
    reg [3:0] lad_reg;

    assign ctrl_host_state_o = fsm_host_state;

    assign LPC_LAD  = (lad_en) ? lad_out : 4'bZZZZ;
    assign LPC_LCLK = ~clk_i;


    always @ (posedge clk_i) begin
        lad_reg <= LPC_LAD;
        if (fsm_host_state == `LPC_ST_FORCE_RESET) begin
            if (~ctrl_nrst_i) begin
                LPC_LRESET  = 0;
                LPC_LFRAME  = 1;
                lad_en  = 0;
                lad_out = 4'b0000;
                ctrl_ready_o   = 0;
            end
        else begin
            LPC_LRESET  = 1;
            LPC_LFRAME  = 1;
            lad_en  = 0;
            lad_out = 4'b0000;
            ctrl_ready_o   = 0;
            fsm_host_state = `LPC_ST_IDLE;
        end
        end
        else if (fsm_host_state == `LPC_ST_IDLE) begin
            if (~ctrl_lframe_i) begin
            LPC_LFRAME  = 0;
            lad_en  = 1;
            lad_out = 4'b0000;
            ctrl_ready_o   = 0;
            fsm_host_state = `LPC_ST_START;
        end
        else LPC_LRESET = 1;
        end
        else if (fsm_host_state == `LPC_ST_START) begin
           if (~ctrl_memory_cycle_i) begin
                if (ctrl_lframe_i & ctrl_rd_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0000;
                    fsm_host_state = `LPC_ST_CYCTYPE_RD;
                end
                else if (ctrl_lframe_i & ctrl_wr_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0010;
                    fsm_host_state = `LPC_ST_CYCTYPE_WR;
                end
           end  if (ctrl_memory_cycle_i) begin
                if (ctrl_lframe_i & ctrl_rd_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0100;
                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_RD;
                end
                else if (ctrl_lframe_i & ctrl_wr_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0110;
                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_WR;
                end
           end
        end
        else if ((fsm_host_state == `LPC_ST_CYCTYPE_RD) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_RD)) begin
            lad_out = ctrl_addr_i[15:12];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK1) begin
            lad_out    = ctrl_addr_i[11: 8];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK2) begin
           lad_out    = ctrl_addr_i[ 7: 4];
           fsm_host_state = `LPC_ST_ADDR_RD_CLK3;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK3) begin
            lad_out    = ctrl_addr_i[ 3: 0];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK4;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK4) begin
            lad_out    = 4'b1111;
            fsm_host_state = `LPC_ST_TAR_RD_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK1) begin
            lad_en     = 0;
            fsm_host_state = `LPC_ST_TAR_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK2) begin
            fsm_host_state = `LPC_ST_SYNC_RD;
        end
        else if (fsm_host_state == `LPC_ST_SYNC_RD) begin
            ctrl_data_o[3:0] = LPC_LAD;
            fsm_host_state    = `LPC_ST_DATA_RD_CLK1;
            if (lad_reg == 4'b0000) fsm_host_state = `LPC_ST_DATA_RD_CLK1;
            else if ((lad_reg != 4'b0101) && (lad_reg != 4'b0110)) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
        end
        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK1) begin
            ctrl_data_o[7:4] = LPC_LAD;
            fsm_host_state = `LPC_ST_DATA_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK2) begin
            fsm_host_state = `LPC_ST_FINAL_TAR_CLK1;
        end
        else if ((fsm_host_state == `LPC_ST_CYCTYPE_WR) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_WR)) begin
            lad_out = ctrl_addr_i[15:12];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK1;
        end
        else if (fsm_host_state ==  `LPC_ST_ADDR_WR_CLK1) begin
            lad_out = ctrl_addr_i[11: 8];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK2) begin
            lad_out = ctrl_addr_i[ 7: 4];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK3;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK3) begin
           lad_out = ctrl_addr_i[ 3: 0];
           fsm_host_state = `LPC_ST_ADDR_WR_CLK4;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK4) begin
            lad_out = ctrl_data_i[3:0];
            fsm_host_state = `LPC_ST_DATA_WR_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_DATA_WR_CLK1) begin
            lad_out = ctrl_data_i[7:4];
            fsm_host_state = `LPC_ST_DATA_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_DATA_WR_CLK2) begin
            lad_out = 4'b1111;
            fsm_host_state = `LPC_ST_TAR_WR_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_TAR_WR_CLK1) begin
            lad_en = 0;
            fsm_host_state = `LPC_ST_TAR_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_TAR_WR_CLK2) begin
            fsm_host_state = `LPC_ST_SYNC_WR;
        end
        else if (fsm_host_state == `LPC_ST_SYNC_WR) begin
            if (lad_reg == 4'b0000) fsm_host_state = `LPC_ST_FINAL_TAR_CLK1;
            else if ((lad_reg != 4'b0101) && (lad_reg != 4'b0110)) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
        end
        else if (fsm_host_state == `LPC_ST_FINAL_TAR_CLK1) begin
            if (lad_reg != 4'b1111) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
            else begin
                ctrl_ready_o = 1;
                fsm_host_state = `LPC_ST_FINAL_TAR_CLK2;
            end
        end
        else if (fsm_host_state == `LPC_ST_FINAL_TAR_CLK2) begin
            fsm_host_state = `LPC_ST_IDLE;
        end
        else begin
            fsm_host_state = `LPC_ST_FORCE_RESET;
        end
    end
endmodule
module lpc_host (clk_i, ctrl_addr_i, ctrl_data_i, ctrl_nrst_i, ctrl_lframe_i,
                 ctrl_rd_status_i, ctrl_wr_status_i, ctrl_memory_cycle_i,
                 ctrl_data_o, ctrl_ready_o, ctrl_host_state_o,
                 LPC_LAD, LPC_LCLK, LPC_LRESET, LPC_LFRAME
);


    input  wire        clk_i;



    input  wire [15:0] ctrl_addr_i;
    input  wire [ 7:0] ctrl_data_i;
    input  wire        ctrl_nrst_i;
    input  wire        ctrl_lframe_i;
    input  wire        ctrl_rd_status_i;
    input  wire        ctrl_wr_status_i;
    input  wire        ctrl_memory_cycle_i;


    output reg  [ 7:0] ctrl_data_o;
    output reg         ctrl_ready_o;
    output wire [ 4:0] ctrl_host_state_o;


    inout  wire [ 3:0] LPC_LAD;
    output wire        LPC_LCLK;
    output reg         LPC_LRESET;
    output reg         LPC_LFRAME;


    reg [4:0] fsm_host_state;


    reg       lad_en;
    reg [3:0] lad_out;
    reg [3:0] lad_reg;

    assign ctrl_host_state_o = fsm_host_state;

    assign LPC_LAD  = (lad_en) ? lad_out : 4'bZZZZ;
    assign LPC_LCLK = ~clk_i;


    always @ (posedge clk_i) begin
        lad_reg <= LPC_LAD;
        if (fsm_host_state == `LPC_ST_FORCE_RESET) begin
            if (~ctrl_nrst_i) begin
                LPC_LRESET  = 0;
                LPC_LFRAME  = 1;
                lad_en  = 0;
                lad_out = 4'b0000;
                ctrl_ready_o   = 0;
            end
        else begin
            LPC_LRESET  = 1;
            LPC_LFRAME  = 1;
            lad_en  = 0;
            lad_out = 4'b0000;
            ctrl_ready_o   = 0;
            fsm_host_state = `LPC_ST_IDLE;
        end
        end
        else if (fsm_host_state == `LPC_ST_IDLE) begin
            if (~ctrl_lframe_i) begin
            LPC_LFRAME  = 0;
            lad_en  = 1;
            lad_out = 4'b0000;
            ctrl_ready_o   = 0;
            fsm_host_state = `LPC_ST_START;
        end
        else LPC_LRESET = 1;
        end
        else if (fsm_host_state == `LPC_ST_START) begin
           if (~ctrl_memory_cycle_i) begin
                if (ctrl_lframe_i & ctrl_rd_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0000;
                    fsm_host_state = `LPC_ST_CYCTYPE_RD;
                end
                else if (ctrl_lframe_i & ctrl_wr_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0010;
                    fsm_host_state = `LPC_ST_CYCTYPE_WR;
                end
           end  if (ctrl_memory_cycle_i) begin
                if (ctrl_lframe_i & ctrl_rd_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0100;
                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_RD;
                end
                else if (ctrl_lframe_i & ctrl_wr_status_i) begin
                    LPC_LFRAME  = 1;
                    lad_out = 4'b0110;
                    fsm_host_state = `LPC_ST_CYCTYPE_MEMORY_WR;
                end
           end
        end
        else if ((fsm_host_state == `LPC_ST_CYCTYPE_RD) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_RD)) begin
            lad_out = ctrl_addr_i[15:12];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK1) begin
            lad_out    = ctrl_addr_i[11: 8];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK2) begin
           lad_out    = ctrl_addr_i[ 7: 4];
           fsm_host_state = `LPC_ST_ADDR_RD_CLK3;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK3) begin
            lad_out    = ctrl_addr_i[ 3: 0];
            fsm_host_state = `LPC_ST_ADDR_RD_CLK4;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_RD_CLK4) begin
            lad_out    = 4'b1111;
            fsm_host_state = `LPC_ST_TAR_RD_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK1) begin
            lad_en     = 0;
            fsm_host_state = `LPC_ST_TAR_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_TAR_RD_CLK2) begin
            fsm_host_state = `LPC_ST_SYNC_RD;
        end
        else if (fsm_host_state == `LPC_ST_SYNC_RD) begin
            ctrl_data_o[3:0] = LPC_LAD;
            fsm_host_state    = `LPC_ST_DATA_RD_CLK1;
            if (lad_reg == 4'b0000) fsm_host_state = `LPC_ST_DATA_RD_CLK1;
            else if ((lad_reg != 4'b0101) && (lad_reg != 4'b0110)) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
        end
        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK1) begin
            ctrl_data_o[7:4] = LPC_LAD;
            fsm_host_state = `LPC_ST_DATA_RD_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_DATA_RD_CLK2) begin
            fsm_host_state = `LPC_ST_FINAL_TAR_CLK1;
        end
        else if ((fsm_host_state == `LPC_ST_CYCTYPE_WR) || (fsm_host_state == `LPC_ST_CYCTYPE_MEMORY_WR)) begin
            lad_out = ctrl_addr_i[15:12];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK1;
        end
        else if (fsm_host_state ==  `LPC_ST_ADDR_WR_CLK1) begin
            lad_out = ctrl_addr_i[11: 8];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK2) begin
            lad_out = ctrl_addr_i[ 7: 4];
            fsm_host_state = `LPC_ST_ADDR_WR_CLK3;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK3) begin
           lad_out = ctrl_addr_i[ 3: 0];
           fsm_host_state = `LPC_ST_ADDR_WR_CLK4;
        end
        else if (fsm_host_state == `LPC_ST_ADDR_WR_CLK4) begin
            lad_out = ctrl_data_i[3:0];
            fsm_host_state = `LPC_ST_DATA_WR_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_DATA_WR_CLK1) begin
            lad_out = ctrl_data_i[7:4];
            fsm_host_state = `LPC_ST_DATA_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_DATA_WR_CLK2) begin
            lad_out = 4'b1111;
            fsm_host_state = `LPC_ST_TAR_WR_CLK1;
        end
        else if (fsm_host_state == `LPC_ST_TAR_WR_CLK1) begin
            lad_en = 0;
            fsm_host_state = `LPC_ST_TAR_WR_CLK2;
        end
        else if (fsm_host_state == `LPC_ST_TAR_WR_CLK2) begin
            fsm_host_state = `LPC_ST_SYNC_WR;
        end
        else if (fsm_host_state == `LPC_ST_SYNC_WR) begin
            if (lad_reg == 4'b0000) fsm_host_state = `LPC_ST_FINAL_TAR_CLK1;
            else if ((lad_reg != 4'b0101) && (lad_reg != 4'b0110)) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
        end
        else if (fsm_host_state == `LPC_ST_FINAL_TAR_CLK1) begin
            if (lad_reg != 4'b1111) begin
                LPC_LRESET = 0;
                LPC_LFRAME = 1;
                lad_en = 0;
                lad_out = 4'b0000;
                ctrl_ready_o = 0;
                fsm_host_state = `LPC_ST_FORCE_RESET;
            end
            else begin
                ctrl_ready_o = 1;
                fsm_host_state = `LPC_ST_FINAL_TAR_CLK2;
            end
        end
        else if (fsm_host_state == `LPC_ST_FINAL_TAR_CLK2) begin
            fsm_host_state = `LPC_ST_IDLE;
        end
        else begin
            fsm_host_state = `LPC_ST_FORCE_RESET;
        end
    end
endmodule