data/full_repos/permissive/50612019/shift_register.sv
data/verilator_xmls/559e7ac5-1cc2-449a-a092-fafa3b6556c4.xml
module shift_register #(parameter width = 1) (
  input logic clock,
  input logic [0:width-1] in,
  output logic [0:width-1] out);

  always_ff @ (posedge clock)
  begin
    out <= in;
  end
endmodule
module shift_register #(parameter width = 1) (
  input logic clock,
  input logic [0:width-1] in,
  output logic [0:width-1] out);


  always_ff @ (posedge clock)
  begin
    out <= in;
  end
endmodule