data/full_repos/permissive/449071180/if_equals.v
data/verilator_xmls/c031861a-ec6a-47a9-9dc3-a3e53447cc15.xml
module if_equals(in1,in2,out);

output reg out;

input [2:0] in1;

input [2:0] in2;

always@(in1,in2) begin
if(in1 == in2) begin
out = 1;
end else begin
out = 0;
end
end

endmodule
module if_equals(in1,in2,out);


output reg out;

input [2:0] in1;

input [2:0] in2;

always@(in1,in2) begin
if(in1 == in2) begin
out = 1;
end else begin
out = 0;
end
end

endmodule