data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.v
data/verilator_xmls/616f5ee2-4ad0-471b-bbe2-9780d4ad1c7f.xml
module test (A, Y);
    input [6:0] A;
    output Y;
    assign Y = |A;
endmodule
module test (A, Y);

    input [6:0] A;
    output Y;
    assign Y = |A;
endmodule