data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/clk_generator.v
data/verilator_xmls/aea26e5e-b806-4b1a-843b-34e5d7646d0f.xml
module clk_generator(
    input clk,
    input en,
	 input rst,
    input [31:0] limit,
    input [31:0] count,
    output reg clk_0,
	 output reg done
    );

	 reg [31:0] ndCount;
	 
	 initial clk_0 = 1'b0;
	 initial ndCount = 32'h00000000;
	 
	 always@(negedge clk) begin
		if(en) begin
			if(count > ndCount) begin
			ndCount <= count + limit;
			clk_0 <= ~clk_0;
			end
			else begin
				ndCount <= ndCount;
				clk_0 <= clk_0;
			end
		end
		else begin
			ndCount <= count+limit;
			clk_0 <= 1'b0;
		end
	 end

endmodule
module clk_generator(
    input clk,
    input en,
	 input rst,
    input [31:0] limit,
    input [31:0] count,
    output reg clk_0,
	 output reg done
    );


	 reg [31:0] ndCount;
	 
	 initial clk_0 = 1'b0;
	 initial ndCount = 32'h00000000;
	 
	 always@(negedge clk) begin
		if(en) begin
			if(count > ndCount) begin
			ndCount <= count + limit;
			clk_0 <= ~clk_0;
			end
			else begin
				ndCount <= ndCount;
				clk_0 <= clk_0;
			end
		end
		else begin
			ndCount <= count+limit;
			clk_0 <= 1'b0;
		end
	 end

endmodule