data/full_repos/permissive/441359809/src/yosys/tests/sat/counters-repeat.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/sat/counters-repeat.v:18: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'counter1\'\nmodule counter1(clk, rst, ping);\n       ^~~~~~~~\n                                                                                                : ... Top module \'counter2\'\nmodule counter2(clk, rst, ping);\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module counter2(clk, rst, ping);
	input clk, rst;
	output ping;
	reg [31:0] count;

	integer i;
	reg carry;

	always @(posedge clk) begin
		carry = 1;
		i = 0;
		repeat (32) begin
			count[i] <= !rst & (count[i] ^ carry);
			carry = count[i] & carry;
			i = i+1;
		end
	end

	assign ping = &count;
endmodule
module counter2(clk, rst, ping);

	input clk, rst;
	output ping;
	reg [31:0] count;

	integer i;
	reg carry;

	always @(posedge clk) begin
		carry = 1;
		i = 0;
		repeat (32) begin
			count[i] <= !rst & (count[i] ^ carry);
			carry = count[i] & carry;
			i = i+1;
		end
	end

	assign ping = &count;
endmodule