data/full_repos/permissive/476810618/AD1_AD2/AD1/app_14_sub.v
data/verilator_xmls/8d6819f6-fffc-40f9-a07d-b48d5b071897.xml
module rout2 (
    output rout,
    input a,
    input b,
    input bin, qs
);
    wire diff;
    assign diff = a^b|bin;
    assign rout = qs ? a : diff;
endmodule
module rout2 (
    output rout,
    input a,
    input b,
    input bin, qs
);

    wire diff;
    assign diff = a^b|bin;
    assign rout = qs ? a : diff;
endmodule