data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:17: Cannot find include file: ../../../../lib/axi4_sv/axi.vh\n  `include "../../../../lib/axi4_sv/axi.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4_sv/axi.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4_sv/axi.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd,data/full_repos/permissive/447976230/../../../../lib/axi4_sv/axi.vh.sv\n             ../../../../lib/axi4_sv/axi.vh\n             ../../../../lib/axi4_sv/axi.vh.v\n             ../../../../lib/axi4_sv/axi.vh.sv\n             obj_dir/../../../../lib/axi4_sv/axi.vh\n             obj_dir/../../../../lib/axi4_sv/axi.vh.v\n             obj_dir/../../../../lib/axi4_sv/axi.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:24: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(m_axi_hp,          m_axi_hp_v) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:24: syntax error, unexpected \',\'\n  always_comb begin `AXI4_ASSIGN(m_axi_hp,          m_axi_hp_v) end\n                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:25: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:26: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:27: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:28: Define or directive not defined: \'`AXI4_ASSIGN\'\n  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:31: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(m_axi_hp,      m_axi_hp_v)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:32: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0])\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:33: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1])\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:34: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2])\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv:35: Define or directive not defined: \'`AXI4_PORT_ASSIGN_NR\'\n    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3])\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module axi_interconnect_dma (
  AxiIf.slave  s_axi_hp_dma [3:0],
  AxiIf.master m_axi_hp
);


  `include "../../../../lib/axi4_sv/axi.vh"
  AxiIf_v #(128,49)
    m_axi_hp_v(.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
  AxiIf_v #(128,49)
    s_axi_hp_dma_v[3:0](.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));


  always_comb begin `AXI4_ASSIGN(m_axi_hp,          m_axi_hp_v) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end

  axi_interconnect_dma_bd axi_interconnect_dma_bd_i (
    `AXI4_PORT_ASSIGN_NR(m_axi_hp,      m_axi_hp_v)
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3])
    .clk40      (m_axi_hp.clk),
    .clk40_rstn (!m_axi_hp.rst)
  );

endmodule
module axi_interconnect_dma (
  AxiIf.slave  s_axi_hp_dma [3:0],
  AxiIf.master m_axi_hp
);



  `include "../../../../lib/axi4_sv/axi.vh"
  AxiIf_v #(128,49)
    m_axi_hp_v(.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
  AxiIf_v #(128,49)
    s_axi_hp_dma_v[3:0](.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));


  always_comb begin `AXI4_ASSIGN(m_axi_hp,          m_axi_hp_v) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end
  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end

  axi_interconnect_dma_bd axi_interconnect_dma_bd_i (
    `AXI4_PORT_ASSIGN_NR(m_axi_hp,      m_axi_hp_v)
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2])
    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3])
    .clk40      (m_axi_hp.clk),
    .clk40_rstn (!m_axi_hp.rst)
  );

endmodule