data/full_repos/permissive/433122322/Course_Design.v
1: b"%Error: data/full_repos/permissive/433122322/Course_Design.v:31: Cannot find file containing module: 'original_wave'\noriginal_wave ow(         \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433122322,data/full_repos/permissive/433122322/original_wave\n             data/full_repos/permissive/433122322,data/full_repos/permissive/433122322/original_wave.v\n             data/full_repos/permissive/433122322,data/full_repos/permissive/433122322/original_wave.sv\n             original_wave\n             original_wave.v\n             original_wave.sv\n             obj_dir/original_wave\n             obj_dir/original_wave.v\n             obj_dir/original_wave.sv\n%Error: data/full_repos/permissive/433122322/Course_Design.v:44: Cannot find file containing module: 'UART'\nUART uart(         \n^~~~\n%Error: data/full_repos/permissive/433122322/Course_Design.v:54: Cannot find file containing module: 'changing_waves'\nchanging_waves u1(              \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433122322/Course_Design.v:65: Cannot find file containing module: 'segment'\nsegment seg(      \n^~~~~~~\n%Error: data/full_repos/permissive/433122322/Course_Design.v:76: Cannot find file containing module: 'DAC'\nDAC dac(                                   \n^~~\n%Error: Exiting due to 5 error(s)\n"
module Course_Design(
	input 		clk,
	input       rst_n,
	
	input    uart_rx,
	output [7:0]  rx_data,
	
	output [5:0] seg_sel,
   output [7:0] seg_data,
	output    uart_tx,
		
	output da1_clk,
	output da1_wrt,
   output [10:0] da1_data, dout9,
	
	output [7: 0] dout1, dout2, dout3, dout4,dout5, dout6, dout7, dout8
);

reg [2:0] s0;
reg [2:0] s1;
reg [1:0] s2;

always@(*)
begin
	s0 <=rx_data[7: 5];
	s1 <=rx_data[4: 2];
	s2 <=rx_data[1: 0];
end


original_wave ow(
	.clk(clk),
	.rst_n(rst_n),
	.d1(dout1),
	.d2(dout2),
	.d3(dout3),
	.d4(dout4),
	.d5(dout5),
	.d6(dout6),
	.d7(dout7),
	.d8(dout8)
);

UART uart(
	.clk(clk), 
	.rst_n(rst_n),
	.uart_rx(uart_rx),
	.rx_data(rx_data),
	.uart_tx(uart_tx),
);


wire [10: 0] dout;
changing_waves u1(
		.clk(clk),
		.rst_n(rst_n),
		.s0(s0),
		.s1(s1),
		.s2(s2),
		.dout(dout),
		.d1(dout9)
);


segment seg(
	.clk(clk),
	.rst_n(rst_n),
	.s0(s0),
	.s1(s1),
	.s2(s2),
	.seg_sel(seg_sel),
	.seg_data(seg_data)
);


DAC dac(
	.clk(clk),
	.da_clk(da1_clk),
	.da_wrt(da1_wrt)
);
assign da1_data = dout; 

endmodule
module Course_Design(
	input 		clk,
	input       rst_n,
	
	input    uart_rx,
	output [7:0]  rx_data,
	
	output [5:0] seg_sel,
   output [7:0] seg_data,
	output    uart_tx,
		
	output da1_clk,
	output da1_wrt,
   output [10:0] da1_data, dout9,
	
	output [7: 0] dout1, dout2, dout3, dout4,dout5, dout6, dout7, dout8
);


reg [2:0] s0;
reg [2:0] s1;
reg [1:0] s2;

always@(*)
begin
	s0 <=rx_data[7: 5];
	s1 <=rx_data[4: 2];
	s2 <=rx_data[1: 0];
end


original_wave ow(
	.clk(clk),
	.rst_n(rst_n),
	.d1(dout1),
	.d2(dout2),
	.d3(dout3),
	.d4(dout4),
	.d5(dout5),
	.d6(dout6),
	.d7(dout7),
	.d8(dout8)
);

UART uart(
	.clk(clk), 
	.rst_n(rst_n),
	.uart_rx(uart_rx),
	.rx_data(rx_data),
	.uart_tx(uart_tx),
);


wire [10: 0] dout;
changing_waves u1(
		.clk(clk),
		.rst_n(rst_n),
		.s0(s0),
		.s1(s1),
		.s2(s2),
		.dout(dout),
		.d1(dout9)
);


segment seg(
	.clk(clk),
	.rst_n(rst_n),
	.s0(s0),
	.s1(s1),
	.s2(s2),
	.seg_sel(seg_sel),
	.seg_data(seg_data)
);


DAC dac(
	.clk(clk),
	.da_clk(da1_clk),
	.da_wrt(da1_wrt)
);
assign da1_data = dout; 

endmodule