data/full_repos/permissive/439731184/parity_clock_tb.v
1: b'%Error: data/full_repos/permissive/439731184/parity_clock_tb.v:1: Cannot find include file: parity_clock.v\n`include "parity_clock.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/parity_clock.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/parity_clock.v.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/parity_clock.v.sv\n             parity_clock.v\n             parity_clock.v.v\n             parity_clock.v.sv\n             obj_dir/parity_clock.v\n             obj_dir/parity_clock.v.v\n             obj_dir/parity_clock.v.sv\n%Error: data/full_repos/permissive/439731184/parity_clock_tb.v:10: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g\\t%h\\t%b", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/parity_clock_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/439731184/parity_clock_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, clk, y);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/parity_clock_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #16 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/parity_clock_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk <= clk + 1;\n    ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module parity_clock_tb();

reg [3:0] clk;
wire y;

initial begin
    $display ("time\tclk\ty");
    $monitor ("%g\t%h\t%b", 
              $time, clk, y);
    $dumpfile("test.vcd");
    $dumpvars(0, clk, y);
    clk <= 4'b0;
    #16 $finish;
end

always begin
    #1 clk <= clk + 1;
end

parity_clock P (clk, y);

endmodule
module parity_clock_tb();


reg [3:0] clk;
wire y;

initial begin
    $display ("time\tclk\ty");
    $monitor ("%g\t%h\t%b", 
              $time, clk, y);
    $dumpfile("test.vcd");
    $dumpvars(0, clk, y);
    clk <= 4'b0;
    #16 $finish;
end

always begin
    #1 clk <= clk + 1;
end

parity_clock P (clk, y);

endmodule