data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:52: Cannot find include file: sine.txt\n`include "sine.txt" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/sine.txt\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/sine.txt.v\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/sine.txt.sv\n             sine.txt\n             sine.txt.v\n             sine.txt.sv\n             obj_dir/sine.txt\n             obj_dir/sine.txt.v\n             obj_dir/sine.txt.sv\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 1\'b0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk <= ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("cordic.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n  initial $dumpvars(0,cordic_tb);\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/cordic_tb.v:59: Unsupported or unknown PLI call: $monitor\n   initial $monitor("%d\\t%d\\t%d\\t%d\\t%d",$time,xiu,yiu,xou,you);\n           ^~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module cordic_tb();

   cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );

   reg reset;
   reg clk;
   reg enable;
   reg [15:0] xi, yi, zi;
   
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;

   initial clk = 1'b0;
   always #50 clk <= ~clk;
   
   initial enable = 1'b1;

   initial zi = 16'b0;

   always @(posedge clk)
     zi <= #1 zi + 16'd0;
   
   wire [15:0] xo,yo,zo;

   initial $dumpfile("cordic.vcd");
  initial $dumpvars(0,cordic_tb);
   initial
     begin
`include "sine.txt"
     end

	wire [15:0] xiu = {~xi[15],xi[14:0]};
	wire [15:0] yiu = {~yi[15],yi[14:0]};
	wire [15:0] xou = {~xo[15],xo[14:0]};
	wire [15:0] you = {~yo[15],yo[14:0]};
   initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);

endmodule
module cordic_tb();


   cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );

   reg reset;
   reg clk;
   reg enable;
   reg [15:0] xi, yi, zi;
   
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;

   initial clk = 1'b0;
   always #50 clk <= ~clk;
   
   initial enable = 1'b1;

   initial zi = 16'b0;

   always @(posedge clk)
     zi <= #1 zi + 16'd0;
   
   wire [15:0] xo,yo,zo;

   initial $dumpfile("cordic.vcd");
  initial $dumpvars(0,cordic_tb);
   initial
     begin
`include "sine.txt"
     end

	wire [15:0] xiu = {~xi[15],xi[14:0]};
	wire [15:0] yiu = {~yi[15],yi[14:0]};
	wire [15:0] xou = {~xo[15],xo[14:0]};
	wire [15:0] you = {~yo[15],yo[14:0]};
   initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);

endmodule