data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v:66: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 9 bits.\n                                                                                                          : ... In instance VcdAdder.do_add.s_pad_2\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module VcdAdder(
    input clock,
    input [7:0] io_a,
    input [7:0] io_b,
    output [9:0] io_c
);
    wire _do_add__clock;
    wire [7:0] _do_add__a;
    wire [7:0] _do_add__b;
    wire [9:0] _do_add__c;
    DoAdd do_add (
        .clock(_do_add__clock),
        .a(_do_add__a),
        .b(_do_add__b),
        .c(_do_add__c)
    );
    assign _do_add__a = io_a;
    assign _do_add__b = io_b;
    assign _do_add__clock = clock;
    assign io_c = _do_add__c;
endmodule
module VcdAdder(
    input clock,
    input [7:0] io_a,
    input [7:0] io_b,
    output [9:0] io_c
);

    wire _do_add__clock;
    wire [7:0] _do_add__a;
    wire [7:0] _do_add__b;
    wire [9:0] _do_add__c;
    DoAdd do_add (
        .clock(_do_add__clock),
        .a(_do_add__a),
        .b(_do_add__b),
        .c(_do_add__c)
    );
    assign _do_add__a = io_a;
    assign _do_add__b = io_b;
    assign _do_add__clock = clock;
    assign io_c = _do_add__c;
endmodule