data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:11: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("and_64bit.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:12: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, testbench);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:16: Unsupported or unknown PLI call: $monitor\n    $monitor("a = %b\\nb = %b\\nc = %b\\n\\n" , a, b, c);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 64\'d1134; b = 64\'d8238;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = -64\'d7478; b = -64\'d46474;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 64\'d1092835; b = -64\'d1020;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 64\'d7890678653; b = 64\'d4238598110567;\n    ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

reg signed [63:0] a, b;
wire signed [63:0] c;
integer i;

and_64bit dut(.a(a), .b(b), .c(c));

initial begin
    $dumpfile("and_64bit.vcd");
    $dumpvars(0, testbench);

    a = 64'b0; b = 64'b0;

    $monitor("a = %b\nb = %b\nc = %b\n\n" , a, b, c);

    #10
    a = 64'b1111111111111111111111111111111111111111111111111111111111111111;
    b = 64'b1111111111111111111111111111111111111111111111111111111111111111;

    #10 a = 64'd1134; b = 64'd8238;
    #10 a = -64'd7478; b = -64'd46474;
    #10 a = 64'd1092835; b = -64'd1020;
    #10 a = 64'd7890678653; b = 64'd4238598110567;

end
endmodule
module testbench;


reg signed [63:0] a, b;
wire signed [63:0] c;
integer i;

and_64bit dut(.a(a), .b(b), .c(c));

initial begin
    $dumpfile("and_64bit.vcd");
    $dumpvars(0, testbench);

    a = 64'b0; b = 64'b0;

    $monitor("a = %b\nb = %b\nc = %b\n\n" , a, b, c);

    #10
    a = 64'b1111111111111111111111111111111111111111111111111111111111111111;
    b = 64'b1111111111111111111111111111111111111111111111111111111111111111;

    #10 a = 64'd1134; b = 64'd8238;
    #10 a = -64'd7478; b = -64'd46474;
    #10 a = 64'd1092835; b = -64'd1020;
    #10 a = 64'd7890678653; b = 64'd4238598110567;

end
endmodule