data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module clockgen(input clk_in1, output clk, output clkX4, output ph0, output ph1, output ph2, output ph3);

	assign clk = clk_in1;
	reg r;
	assign clkX4=r;
	reg p0, p1, p2, p3;
	assign ph0=p0;
	assign ph1=p1;
	assign ph2=p2;
	assign ph3=p3;
	initial begin
		r=0;
		forever begin
			@(posedge clk_in1);
			r = 1;
			p0 <= 0;
			p1 <= 1;
			p2 <= 0;
			p3 <= 0;
			#1.25 r=0;

			#1.25 r=1;
			p0 <= 0;
			p1 <= 0;
			p2 <= 1;
			p3 <= 0;
			#1.25 r=0;

			#1.25 r=1;
			p0 <= 0;
			p1 <= 0;
			p2 <= 0;
			p3 <= 1;
			#1.25 r=0;
			#1.25 r=1;
			p0 <= 1;
			p1 <= 0;
			p2 <= 0;
			p3 <= 0;
			#1.25 r=0;
		end
	end
endmodule
module clockgen(input clk_in1, output clk, output clkX4, output ph0, output ph1, output ph2, output ph3);


	assign clk = clk_in1;
	reg r;
	assign clkX4=r;
	reg p0, p1, p2, p3;
	assign ph0=p0;
	assign ph1=p1;
	assign ph2=p2;
	assign ph3=p3;
	initial begin
		r=0;
		forever begin
			@(posedge clk_in1);
			r = 1;
			p0 <= 0;
			p1 <= 1;
			p2 <= 0;
			p3 <= 0;
			#1.25 r=0;

			#1.25 r=1;
			p0 <= 0;
			p1 <= 0;
			p2 <= 1;
			p3 <= 0;
			#1.25 r=0;

			#1.25 r=1;
			p0 <= 0;
			p1 <= 0;
			p2 <= 0;
			p3 <= 1;
			#1.25 r=0;
			#1.25 r=1;
			p0 <= 1;
			p1 <= 0;
			p2 <= 0;
			p3 <= 0;
			#1.25 r=0;
		end
	end
endmodule