data/full_repos/permissive/449142214/Project files/CLK_div.v
1: b'%Error: Cannot find file containing module: files,data/full_repos/permissive/449142214\n        ... Looked in:\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214.v\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214.sv\n             files,data/full_repos/permissive/449142214\n             files,data/full_repos/permissive/449142214.v\n             files,data/full_repos/permissive/449142214.sv\n             obj_dir/files,data/full_repos/permissive/449142214\n             obj_dir/files,data/full_repos/permissive/449142214.v\n             obj_dir/files,data/full_repos/permissive/449142214.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/449142214/Project\n%Error: Cannot find file containing module: files/CLK_div.v\n%Error: Exiting due to 3 error(s)\n'
module CLK_div(input CLK,input RESET,output CLK_div);
reg [18:0] count_div;
always @ (posedge CLK,posedge RESET)
begin
    if (RESET == 1)
        count_div <= 0;
    else
        count_div <= count_div + 1;
end
assign CLK_div = count_div[18];
endmodule
module CLK_div(input CLK,input RESET,output CLK_div);

reg [18:0] count_div;
always @ (posedge CLK,posedge RESET)
begin
    if (RESET == 1)
        count_div <= 0;
    else
        count_div <= count_div + 1;
end
assign CLK_div = count_div[18];
endmodule