data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v
1: b'%Error: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:74: Cannot find file containing module: \'xadc_wiz_2\'\nxadc_wiz_2  XLXI_7 (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.v\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.sv\n             xadc_wiz_2\n             xadc_wiz_2.v\n             xadc_wiz_2.sv\n             obj_dir/xadc_wiz_2\n             obj_dir/xadc_wiz_2.v\n             obj_dir/xadc_wiz_2.sv\n%Warning-WIDTH: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:109: Input port connection \'jxADC\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'JXADC\' generates 8 bits.\n                                                                                                : ... In instance main_driver\nadc_controller dut0(clk, JXADC, data);\n                         ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module main_driver (clk, JXADC, sw, JA, JC);
input clk;
input [7:0] JXADC;
input [15:0] sw;
input [7:0] JA;

output [7:0] JC;


reg [31:0] freq_counter = 0;
reg var_clk = 0;
wire [15:0] data;   
parameter min_count = 84996;


adc_controller dut0(clk, JXADC, data);

always @(posedge clk) begin
    freq_counter <= freq_counter +1;
    if (freq_counter >= (min_count + ((4096 - data[15:4]) ** 2))) begin 
        freq_counter <= 0;
        var_clk <= !var_clk;
    end
end

motor_signals dut1(var_clk, sw[0], sw[1], JC[0], JC[1], JC[2], JC[3], JC[4], JC[5], JA[2:0]);

endmodule
module main_driver (clk, JXADC, sw, JA, JC);

input clk;
input [7:0] JXADC;
input [15:0] sw;
input [7:0] JA;

output [7:0] JC;


reg [31:0] freq_counter = 0;
reg var_clk = 0;
wire [15:0] data;   
parameter min_count = 84996;


adc_controller dut0(clk, JXADC, data);

always @(posedge clk) begin
    freq_counter <= freq_counter +1;
    if (freq_counter >= (min_count + ((4096 - data[15:4]) ** 2))) begin 
        freq_counter <= 0;
        var_clk <= !var_clk;
    end
end

motor_signals dut1(var_clk, sw[0], sw[1], JC[0], JC[1], JC[2], JC[3], JC[4], JC[5], JA[2:0]);

endmodule