data/full_repos/permissive/499494419/bo618.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:50: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk =~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:55: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:57: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:59: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:61: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:63: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:65: Unsupported: Ignoring delay on this delayed statement.\n#10;datavalid=0; \n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:66: Unsupported: Ignoring delay on this delayed statement.\n#10;datavalid=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:67: Unsupported: Ignoring delay on this delayed statement.\n#10;datavalid=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:68: Unsupported: Ignoring delay on this delayed statement.\n#10;datavalid=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo618.v:69: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Error: data/full_repos/permissive/499494419/bo618.v:39: Cannot find file containing module: \'ma\'\n ma uut (\n ^~\n        ... Looked in:\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma.v\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma.sv\n             ma\n             ma.v\n             ma.sv\n             obj_dir/ma\n             obj_dir/ma.v\n             obj_dir/ma.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bo;


	reg clk;
	reg rst;
	reg datavalid;


	wire datadelay1;
	wire datadelay2;
	wire datadelay3;
	wire datadelay4;


	ma uut (
		.clk(clk), 
		.rst(rst), 
		.datavalid(datavalid), 
		.datadelay1(datadelay1), 
		.datadelay2(datadelay2), 
		.datadelay3(datadelay3),
		.datadelay4(datadelay4)
	);

	initial clk =0;
always #5 clk =~clk;
 
initial begin
rst = 1;
datavalid = 0;
#100
rst = 0;
#25
rst = 1;
#20
datavalid= 1;
#100
datavalid = 0;
#10;
datavalid=1;
#10;datavalid=0;
#10;datavalid=1;
#10;datavalid=0;
#10;datavalid=1;
#200
$stop;
 
end
 
endmodule
module bo;



	reg clk;
	reg rst;
	reg datavalid;


	wire datadelay1;
	wire datadelay2;
	wire datadelay3;
	wire datadelay4;


	ma uut (
		.clk(clk), 
		.rst(rst), 
		.datavalid(datavalid), 
		.datadelay1(datadelay1), 
		.datadelay2(datadelay2), 
		.datadelay3(datadelay3),
		.datadelay4(datadelay4)
	);

	initial clk =0;
always #5 clk =~clk;
 
initial begin
rst = 1;
datavalid = 0;
#100
rst = 0;
#25
rst = 1;
#20
datavalid= 1;
#100
datavalid = 0;
#10;
datavalid=1;
#10;datavalid=0;
#10;datavalid=1;
#10;datavalid=0;
#10;datavalid=1;
#200
$stop;
 
end
 
endmodule