data/full_repos/permissive/430434698/bits_encoder.v
1: b'%Error: data/full_repos/permissive/430434698/bits_encoder.v:39: Cannot find include file: clog2.vh\n    `include "clog2.vh" \n             ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/clog2.vh\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/clog2.vh.v\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/clog2.vh.sv\n             clog2.vh\n             clog2.vh.v\n             clog2.vh.sv\n             obj_dir/clog2.vh\n             obj_dir/clog2.vh.v\n             obj_dir/clog2.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module bits_encoder #(
        parameter BITS = 1,
        parameter INVALID_VALUE_CHECK = 1
    )(
        input [BITS - 1:0] din,
        output [$clog2(BITS) - 1:0] dout,
        output out_valid
    );

    `include "clog2.vh"

    localparam OUTPUT_WIDTH = clog2(BITS);

    wire [BITS - 1:0] valid;

    wire [BITS - 1:0] invalid;

    wire [OUTPUT_WIDTH - 1:0] result [BITS - 1:0];


    genvar i;

    assign valid[0] = din[0];
    assign invalid[0] = 1'b0;
    assign result[0] = 0;

    generate
        for(i = 1;i < BITS;i = i + 1) begin : encode_generate
            assign valid[i] = ((valid[i - 1] == 1'b1) || 
                              (din[i] == 1'b1)) ? 1'b1 : 1'b0;
            assign invalid[i] = INVALID_VALUE_CHECK ? ((((valid[i - 1] == 1'b1)
                                && (din[i] == 1'b1)) || 
                                (invalid[i - 1] == 1'b1)) ? 1'b1 : 1'b0) : 
                                1'b0;
            assign result[i] = valid[i - 1] ? result[i - 1] : 
                               i[OUTPUT_WIDTH - 1:0];
        end
    endgenerate

    assign out_valid = valid[BITS - 1] & (~invalid[BITS - 1]);
    assign dout = out_valid ? result[BITS - 1] : {OUTPUT_WIDTH{1'b0}};

endmodule
module bits_encoder #(
        parameter BITS = 1,
        parameter INVALID_VALUE_CHECK = 1
    )(
        input [BITS - 1:0] din,
        output [$clog2(BITS) - 1:0] dout,
        output out_valid
    );


    `include "clog2.vh"

    localparam OUTPUT_WIDTH = clog2(BITS);

    wire [BITS - 1:0] valid;

    wire [BITS - 1:0] invalid;

    wire [OUTPUT_WIDTH - 1:0] result [BITS - 1:0];


    genvar i;

    assign valid[0] = din[0];
    assign invalid[0] = 1'b0;
    assign result[0] = 0;

    generate
        for(i = 1;i < BITS;i = i + 1) begin : encode_generate
            assign valid[i] = ((valid[i - 1] == 1'b1) || 
                              (din[i] == 1'b1)) ? 1'b1 : 1'b0;
            assign invalid[i] = INVALID_VALUE_CHECK ? ((((valid[i - 1] == 1'b1)
                                && (din[i] == 1'b1)) || 
                                (invalid[i - 1] == 1'b1)) ? 1'b1 : 1'b0) : 
                                1'b0;
            assign result[i] = valid[i - 1] ? result[i - 1] : 
                               i[OUTPUT_WIDTH - 1:0];
        end
    endgenerate

    assign out_valid = valid[BITS - 1] & (~invalid[BITS - 1]);
    assign dout = out_valid ? result[BITS - 1] : {OUTPUT_WIDTH{1'b0}};

endmodule