data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_lfsr.v
data/verilator_xmls/b693e119-d1db-4e2d-a1d2-f42dafc3308c.xml
module lfsr    (
out             ,
enable          ,
clk             ,
reset
);


output [7:0] out;

input enable, clk, reset;

reg [7:0] out;
wire        linear_feedback;


assign linear_feedback = !(out[7] ^ out[3]);

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (enable) begin
  out <= {out[6],out[5],
          out[4],out[3],
          out[2],out[1],
          out[0], linear_feedback};
end 

endmodule
module lfsr    (
out             ,
enable          ,
clk             ,
reset
);



output [7:0] out;

input enable, clk, reset;

reg [7:0] out;
wire        linear_feedback;


assign linear_feedback = !(out[7] ^ out[3]);

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (enable) begin
  out <= {out[6],out[5],
          out[4],out[3],
          out[2],out[1],
          out[0], linear_feedback};
end 

endmodule