data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:37: Define or directive not defined: \'`MULT_NOTHING\'\n  `MULT_NOTHING:\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:37: syntax error, unexpected \':\', expecting endcase\n  `MULT_NOTHING:\n               ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:39: Define or directive not defined: \'`MULT_READ_LO\'\n  `MULT_READ_LO:      \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:41: Define or directive not defined: \'`MULT_READ_HI\'\n  `MULT_READ_HI:      \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:43: Define or directive not defined: \'`MULT_WRITE_LO\'\n  `MULT_WRITE_LO:     \n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:45: Define or directive not defined: \'`MULT_WRITE_HI\'\n  `MULT_WRITE_HI:     \n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:47: Define or directive not defined: \'`MULT_MULT\'\n  `MULT_MULT:         \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:49: Define or directive not defined: \'`MULT_SIGNED_MULT\'\n  `MULT_SIGNED_MULT:  \n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:51: Define or directive not defined: \'`MULT_DIVIDE\'\n  `MULT_DIVIDE:       \n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:53: Define or directive not defined: \'`MULT_SIGNED_DIVIDE\'\n  `MULT_SIGNED_DIVIDE:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:65: syntax error, unexpected else\n  else if(comm==0)\n  ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Mult.v:70: syntax error, unexpected <=, expecting IDENTIFIER\n    Hi<=a;\n      ^~\n%Error: Cannot continue\n'
module Mult 
(
	clk,
	rst,
	a,
	b,
	mult_func,
	c_mult
);
	input clk;
	input rst;
	input [31:0] a;
	input [31:0] b;
	input [3:0] mult_func;
	output reg [31:0] c_mult;
	
	reg[31:0] Hi,Lo;
	reg write_Lo,write_Hi;
	reg[2:0] comm;
	
	wire signed[31:0] a_s,b_s; 
	
	
	assign a_s=a;
	assign b_s=b;

	
	always@(*)
	begin
		c_mult<=0;
		write_Lo<=0;
		write_Hi<=0;
		comm<=0;
		case(mult_func)
		`MULT_NOTHING:
			c_mult<=0;
		`MULT_READ_LO:      
			c_mult<=Lo;
		`MULT_READ_HI:      
			c_mult<=Hi;
		`MULT_WRITE_LO:     
			write_Lo<=1;
		`MULT_WRITE_HI:     
			write_Hi<=1;
		`MULT_MULT:         
			comm<=1;
		`MULT_SIGNED_MULT:  
			comm<=2;
		`MULT_DIVIDE:       
			comm<=3;
		`MULT_SIGNED_DIVIDE:
			comm<=4;
		endcase
	end
	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			Hi<=0;
			Lo<=0;
		end
		else if(comm==0)
		begin
			if(write_Lo)
				Lo<=a;
			if(write_Hi)
				Hi<=a;
		end
		else if(comm==1)
			{Hi,Lo}<=a*b;
		else if(comm==2)
			{Hi,Lo}<=a_s*b_s;
		else if(comm==3)
		begin
			if(b!=32'b0)
			begin
				Lo<=32'b0;
				Hi<=32'b0;
			end
		end
		else if(comm==4)
		begin
			if(b_s!=32'b0)
			begin
				Lo<=32'b0;
				Hi<=32'b0;
			end
		end
	end
endmodule
module Mult 
(
	clk,
	rst,
	a,
	b,
	mult_func,
	c_mult
);

	input clk;
	input rst;
	input [31:0] a;
	input [31:0] b;
	input [3:0] mult_func;
	output reg [31:0] c_mult;
	
	reg[31:0] Hi,Lo;
	reg write_Lo,write_Hi;
	reg[2:0] comm;
	
	wire signed[31:0] a_s,b_s; 
	
	
	assign a_s=a;
	assign b_s=b;

	
	always@(*)
	begin
		c_mult<=0;
		write_Lo<=0;
		write_Hi<=0;
		comm<=0;
		case(mult_func)
		`MULT_NOTHING:
			c_mult<=0;
		`MULT_READ_LO:      
			c_mult<=Lo;
		`MULT_READ_HI:      
			c_mult<=Hi;
		`MULT_WRITE_LO:     
			write_Lo<=1;
		`MULT_WRITE_HI:     
			write_Hi<=1;
		`MULT_MULT:         
			comm<=1;
		`MULT_SIGNED_MULT:  
			comm<=2;
		`MULT_DIVIDE:       
			comm<=3;
		`MULT_SIGNED_DIVIDE:
			comm<=4;
		endcase
	end
	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			Hi<=0;
			Lo<=0;
		end
		else if(comm==0)
		begin
			if(write_Lo)
				Lo<=a;
			if(write_Hi)
				Hi<=a;
		end
		else if(comm==1)
			{Hi,Lo}<=a*b;
		else if(comm==2)
			{Hi,Lo}<=a_s*b_s;
		else if(comm==3)
		begin
			if(b!=32'b0)
			begin
				Lo<=32'b0;
				Hi<=32'b0;
			end
		end
		else if(comm==4)
		begin
			if(b_s!=32'b0)
			begin
				Lo<=32'b0;
				Hi<=32'b0;
			end
		end
	end
endmodule