data/full_repos/permissive/431474762/CTRL.v
1: b'%Error: data/full_repos/permissive/431474762/CTRL.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.v\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/431474762/CTRL.v:11: Define or directive not defined: \'`StallBus\'\n    output reg [`StallBus-1:0] stall\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/CTRL.v:15: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b0;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/CTRL.v:17: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b000111;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/CTRL.v:19: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b001111;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/CTRL.v:22: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b0;\n                    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module CTRL(
    input wire rst,





    input wire stall_for_id,
    input wire stall_for_ex,
    output reg [`StallBus-1:0] stall
);  
    always @ (*) begin
        if (rst) begin
            stall = `StallBus'b0;
        end else if(stall_for_id)begin
            stall = `StallBus'b000111;
        end else if(stall_for_ex)begin
            stall = `StallBus'b001111;
            end
        else begin
            stall = `StallBus'b0;
        end
    end

endmodule
module CTRL(
    input wire rst,





    input wire stall_for_id,
    input wire stall_for_ex,
    output reg [`StallBus-1:0] stall
);
  
    always @ (*) begin
        if (rst) begin
            stall = `StallBus'b0;
        end else if(stall_for_id)begin
            stall = `StallBus'b000111;
        end else if(stall_for_ex)begin
            stall = `StallBus'b001111;
            end
        else begin
            stall = `StallBus'b0;
        end
    end

endmodule