data/full_repos/permissive/459421171/Pipelined/F.v
data/verilator_xmls/369d8a99-8edd-4118-b3c0-40c4f11c5372.xml
module F(clk , pred_PC , F_predPC);
input clk;
input [63:0] pred_PC;
output reg[63:0] F_predPC;

always@(posedge clk)
begin
    F_predPC <= pred_PC;

end

endmodule
module F(clk , pred_PC , F_predPC);

input clk;
input [63:0] pred_PC;
output reg[63:0] F_predPC;

always@(posedge clk)
begin
    F_predPC <= pred_PC;

end

endmodule