data/full_repos/permissive/413230008/Seven-Segment Display Driver/Code/Sources/sseg_driver.v
1: b'%Error: Cannot find file containing module: Display\n        ... Looked in:\n             data/full_repos/permissive/413230008/Seven-Segment/Display\n             data/full_repos/permissive/413230008/Seven-Segment/Display.v\n             data/full_repos/permissive/413230008/Seven-Segment/Display.sv\n             Display\n             Display.v\n             Display.sv\n             obj_dir/Display\n             obj_dir/Display.v\n             obj_dir/Display.sv\n%Error: Cannot find file containing module: Driver/Code/Sources,data/full_repos/permissive/413230008\n%Error: Cannot find file containing module: data/full_repos/permissive/413230008/Seven-Segment\n%Error: Cannot find file containing module: Driver/Code/Sources/sseg_driver.v\n%Error: Exiting due to 4 error(s)\n'
module sseg_driver(
    input clk,
    input [5:0] in0,in1,in2,in3,in4,in5,in6,in7,
    output [6:0] sseg,
    output [7:0] AN
    );

    wire done;
    wire [2:0] NumOut;
    wire [5:0] mux;

    timer_input (
        .clk(clk),
        .reset_n(1'b1),
        .enable(1'b1),
        .FINAL_VALUE(),
        .done(done)
    );

    udl_counter #(.BITS(3)) (
        .clk(clk),
        .reset_n(1'b1),
        .enable(done),
        .up(1'b1),
        .load(1'b0),
        .D(3'b000),
        .Q(NumOut)
    );

    mux_8x1 #(.N(6))(
       .w0(in0),
       .w1(in1),
       .w2(in2),
       .w3(in3),
       .w4(in4),
       .w5(in5),
       .w6(in6),
       .w7(in7),
       .S(NumOut),
       .f(mux)
    );

     first_sseg_driver (
            .active_digit(mux[4:1]),
            .num(NumOut),
            .dp_ctrl(mux[5]),
            .sseg(sseg),
            .AN(AN),
            .DP(DP)
            );

endmodule
module sseg_driver(
    input clk,
    input [5:0] in0,in1,in2,in3,in4,in5,in6,in7,
    output [6:0] sseg,
    output [7:0] AN
    );


    wire done;
    wire [2:0] NumOut;
    wire [5:0] mux;

    timer_input (
        .clk(clk),
        .reset_n(1'b1),
        .enable(1'b1),
        .FINAL_VALUE(),
        .done(done)
    );

    udl_counter #(.BITS(3)) (
        .clk(clk),
        .reset_n(1'b1),
        .enable(done),
        .up(1'b1),
        .load(1'b0),
        .D(3'b000),
        .Q(NumOut)
    );

    mux_8x1 #(.N(6))(
       .w0(in0),
       .w1(in1),
       .w2(in2),
       .w3(in3),
       .w4(in4),
       .w5(in5),
       .w6(in6),
       .w7(in7),
       .S(NumOut),
       .f(mux)
    );

     first_sseg_driver (
            .active_digit(mux[4:1]),
            .num(NumOut),
            .dp_ctrl(mux[5]),
            .sseg(sseg),
            .AN(AN),
            .DP(DP)
            );

endmodule