data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/clock_divider.v
data/verilator_xmls/c653373c-803c-4f3f-829c-32dcf1eb7726.xml
module clock_divider(input i_clk, input[31:0] factor, output reg dependent_clock = 0);
    
    reg[31:0] counter = 0;
    
    always@(posedge i_clk) begin
        counter = counter + 1;
        if (counter >= factor) begin
            dependent_clock <= ~dependent_clock;
            counter = 0;
        end 
    end
endmodule
module clock_divider(input i_clk, input[31:0] factor, output reg dependent_clock = 0);

    
    reg[31:0] counter = 0;
    
    always@(posedge i_clk) begin
        counter = counter + 1;
        if (counter >= factor) begin
            dependent_clock <= ~dependent_clock;
            counter = 0;
        end 
    end
endmodule