data/full_repos/permissive/494148647/src/memory/sdram/sdram.v
1: b'%Error: data/full_repos/permissive/494148647/src/memory/sdram/sdram.v:20: Cannot find include file: sdram.vh\n`include "sdram.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src/memory/sdram,data/full_repos/permissive/494148647/sdram.vh\n             data/full_repos/permissive/494148647/src/memory/sdram,data/full_repos/permissive/494148647/sdram.vh.v\n             data/full_repos/permissive/494148647/src/memory/sdram,data/full_repos/permissive/494148647/sdram.vh.sv\n             sdram.vh\n             sdram.vh.v\n             sdram.vh.sv\n             obj_dir/sdram.vh\n             obj_dir/sdram.vh.v\n             obj_dir/sdram.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module sdram#(
        parameter CAS_LATENCY = 3'b011,
        parameter REF_COUNTER_BITS = 11,
        parameter REF_COUNT = 1000
        ) (
        input clk,
        input rst,


        output sdram_clk,
        output sdram_cle,
        output sdram_cs,
        output sdram_cas,
        output sdram_ras,
        output sdram_we,
        output sdram_dqm,
        output [1:0] sdram_ba,
        output [12:0] sdram_a,
        inout [7:0] sdram_dq,


        input [22:0] addr,
        input rw,
        input [31:0] data_in,
        output [31:0] data_out,
        output busy,
        input in_valid,
        output out_valid
    );


    localparam CMD_UNSELECTED    = 4'b1000;
    localparam CMD_NOP           = 4'b0111;
    localparam CMD_ACTIVE        = 4'b0011;
    localparam CMD_READ          = 4'b0101;
    localparam CMD_WRITE         = 4'b0100;
    localparam CMD_TERMINATE     = 4'b0110;
    localparam CMD_PRECHARGE     = 4'b0010;
    localparam CMD_REFRESH       = 4'b0001;
    localparam CMD_LOAD_MODE_REG = 4'b0000;

    localparam STATE_SIZE = 4;
    localparam INIT = 0,
               WAIT = 1,
               PRECHARGE_INIT = 2,
               REFRESH_INIT_1 = 3,
               REFRESH_INIT_2 = 4,
               LOAD_MODE_REG = 5,
               IDLE = 6,
               REFRESH = 7,
               ACTIVATE = 8,
               READ = 9,
               READ_RES = 10,
               WRITE = 11,
               PRECHARGE = 12;

    wire sdram_clk_ddr;


    ODDR2 #(
        .DDR_ALIGNMENT("NONE"),
        .INIT(1'b0),
        .SRTYPE("SYNC")
    ) ODDR2_inst (
        .Q(sdram_clk_ddr),
        .C0(clk),
        .C1(~clk),
        .CE(1'b1),
        .D0(`SDRAM_CLK_D0),
        .D1(`SDRAM_CLK_D1),
        .R(1'b0),
        .S(1'b0)
    );

    IODELAY2 #(
        .IDELAY_VALUE(0),
        .IDELAY_MODE("NORMAL"),
        .ODELAY_VALUE(`SDRAM_CLK_ODELAY),
        .IDELAY_TYPE("FIXED"),
        .DELAY_SRC("ODATAIN"),
        .DATA_RATE("SDR")
    ) IODELAY_inst (
        .IDATAIN(1'b0),
        .T(1'b0),
        .ODATAIN(sdram_clk_ddr),
        .CAL(1'b0),
        .IOCLK0(1'b0),
        .IOCLK1(1'b0),
        .CLK(1'b0),
        .INC(1'b0),
        .CE(1'b0),
        .RST(1'b0),
        .BUSY(),
        .DATAOUT(),
        .DATAOUT2(),
        .TOUT(),
        .DOUT(sdram_clk)
    );


    reg cle_d, dqm_d;
    reg [3:0] cmd_d;
    reg [1:0] ba_d;
    reg [12:0] a_d;
    reg [7:0] dq_d;
    reg [7:0] dqi_d;




    (* IOB = "TRUE" *)
    reg cle_q, dqm_q;
    (* IOB = "TRUE" *)
    reg [3:0] cmd_q;
    (* IOB = "TRUE" *)
    reg [1:0] ba_q;
    (* IOB = "TRUE" *)
    reg [12:0] a_q;
    (* IOB = "TRUE" *)
    reg [7:0] dq_q;
    (* IOB = "TRUE" *)
    reg [7:0] dqi_q;
    reg dq_en_d, dq_en_q;


    assign sdram_cle = cle_q;
    assign sdram_cs = cmd_q[3];
    assign sdram_ras = cmd_q[2];
    assign sdram_cas = cmd_q[1];
    assign sdram_we = cmd_q[0];
    assign sdram_dqm = dqm_q;
    assign sdram_ba = ba_q;
    assign sdram_a = a_q;
    assign sdram_dq = dq_en_q ? dq_q : 8'hZZ;

    reg [STATE_SIZE-1:0] state_d, state_q = INIT;
    reg [STATE_SIZE-1:0] next_state_d, next_state_q;

    reg [22:0] addr_d, addr_q;
    reg [31:0] data_d, data_q;
    reg out_valid_d, out_valid_q;

    assign data_out = data_q;
    assign busy = !ready_q;
    assign out_valid = out_valid_q;

    reg [15:0] delay_ctr_d, delay_ctr_q;
    reg [1:0] byte_ctr_d, byte_ctr_q;

    reg [REF_COUNTER_BITS-1:0] refresh_ctr_d, refresh_ctr_q;
    reg refresh_flag_d, refresh_flag_q;

    reg ready_d, ready_q;
    reg saved_rw_d, saved_rw_q;
    reg [22:0] saved_addr_d, saved_addr_q;
    reg [31:0] saved_data_d, saved_data_q;

    reg rw_op_d, rw_op_q;

    reg [3:0] row_open_d, row_open_q;
    reg [12:0] row_addr_d[3:0], row_addr_q[3:0];

    reg [2:0] precharge_bank_d, precharge_bank_q;
    integer i;

    always @* begin

        dq_d = dq_q;
        dqi_d = sdram_dq;
        dq_en_d = 1'b0;
        cle_d = cle_q;
        cmd_d = CMD_NOP;
        dqm_d = 1'b0;
        ba_d = 2'd0;
        a_d = 25'd0;
        state_d = state_q;
        next_state_d = next_state_q;
        delay_ctr_d = delay_ctr_q;
        addr_d = addr_q;
        data_d = data_q;
        out_valid_d = 1'b0;
        precharge_bank_d = precharge_bank_q;
        rw_op_d = rw_op_q;
        byte_ctr_d = 2'd0;

        row_open_d = row_open_q;


        for (i = 0; i < 4; i = i + 1)
            row_addr_d[i] = row_addr_q[i];



        refresh_flag_d = refresh_flag_q;
        refresh_ctr_d = refresh_ctr_q + 1'b1;
        if (refresh_ctr_q > REF_COUNT) begin
            refresh_ctr_d = {REF_COUNTER_BITS{1'b0}};
            refresh_flag_d = 1'b1;
        end

        saved_rw_d = saved_rw_q;
        saved_data_d = saved_data_q;
        saved_addr_d = saved_addr_q;
        ready_d = ready_q;




        if (ready_q && in_valid) begin
            saved_rw_d = rw;
            saved_data_d = data_in;
            saved_addr_d = addr;
            ready_d = 1'b0;
        end

        case (state_q)

            INIT: begin
                ready_d = 1'b0;
                row_open_d = 4'b0;
                out_valid_d = 1'b0;
                a_d = 13'b0;
                ba_d = 2'b0;
                cle_d = 1'b1;
                state_d = WAIT;
                delay_ctr_d = 16'd10100;
                next_state_d = PRECHARGE_INIT;
                dq_en_d = 1'b0;
            end
            WAIT: begin
                delay_ctr_d = delay_ctr_q - 1'b1;
                if (delay_ctr_q == 16'd0) begin
                    state_d = next_state_q;
                    if (next_state_q == WRITE) begin
                        dq_en_d = 1'b1;
                        dq_d = data_q[7:0];
                    end
                end
            end
            PRECHARGE_INIT: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = 1'b1;
                ba_d = 2'd0;
                state_d = WAIT;
                next_state_d = REFRESH_INIT_1;
                delay_ctr_d = 16'd0;
            end
            REFRESH_INIT_1: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd7;
                next_state_d = REFRESH_INIT_2;
            end
            REFRESH_INIT_2: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd7;
                next_state_d = LOAD_MODE_REG;
            end
            LOAD_MODE_REG: begin
                cmd_d = CMD_LOAD_MODE_REG;
                ba_d = 2'b0;

                a_d = {3'b000, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b010};
                state_d = WAIT;
                delay_ctr_d = 16'd2;
                next_state_d = IDLE;
                refresh_flag_d = 1'b0;
                refresh_ctr_d = {REF_COUNTER_BITS{1'b1}};
                ready_d = 1'b1;
            end


            IDLE: begin
                if (refresh_flag_q) begin
                    state_d = PRECHARGE;
                    next_state_d = REFRESH;
                    precharge_bank_d = 3'b100;
                    refresh_flag_d = 1'b0;
                end else if (!ready_q) begin
                    ready_d = 1'b1;
                    rw_op_d = saved_rw_q;
                    addr_d = saved_addr_q;

                    if (saved_rw_q)
                        data_d = saved_data_q;


                    if (row_open_q[saved_addr_q[9:8]]) begin
                        if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin

                            if (saved_rw_q)
                                state_d = WRITE;
                            else
                                state_d = READ;
                        end else begin

                            state_d = PRECHARGE;
                            precharge_bank_d = {1'b0, saved_addr_q[9:8]};
                            next_state_d = ACTIVATE;
                        end
                    end else begin

                        state_d = ACTIVATE;
                    end
                end
            end


            REFRESH: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd6;
                next_state_d = IDLE;
            end


            ACTIVATE: begin
                cmd_d = CMD_ACTIVE;
                a_d = addr_q[22:10];
                ba_d = addr_q[9:8];
                delay_ctr_d = 16'd0;
                state_d = WAIT;

                if (rw_op_q)
                    next_state_d = WRITE;
                else
                    next_state_d = READ;

                row_open_d[addr_q[9:8]] = 1'b1;
                row_addr_d[addr_q[9:8]] = addr_q[22:10];
            end


            READ: begin
                cmd_d = CMD_READ;
                a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
                ba_d = addr_q[9:8];
                state_d = WAIT;
                delay_ctr_d = `SDRAM_READ_DELAY_CLK;
                next_state_d = READ_RES;

            end
            READ_RES: begin
                byte_ctr_d = byte_ctr_q + 1'b1;
                data_d = {dqi_q, data_q[31:8]};
                if (byte_ctr_q == 2'd3) begin
                    out_valid_d = 1'b1;
                    state_d = IDLE;
                end
            end


            WRITE: begin
                byte_ctr_d = byte_ctr_q + 1'b1;

                if (byte_ctr_q == 2'd0)
                    cmd_d = CMD_WRITE;

                dq_d = data_q[7:0];
                data_d = {8'h00, data_q[31:8]};
                dq_en_d = 1'b1;
                a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
                ba_d = addr_q[9:8];

                if (byte_ctr_q == 2'd3) begin
                    state_d = IDLE;
                end
            end


            PRECHARGE: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = precharge_bank_q[2];
                ba_d = precharge_bank_q[1:0];
                state_d = WAIT;
                delay_ctr_d = 16'd1;

                if (precharge_bank_q[2]) begin
                    row_open_d = 4'b0000;
                end else begin
                    row_open_d[precharge_bank_q[1:0]] = 1'b0;
                end
            end

            default: state_d = INIT;
        endcase

    end

    always @(posedge clk) begin
        if(rst) begin
            cle_q <= #1 1'b0;
            dq_en_q <= #1 1'b0;
            state_q <= #1 INIT;
            ready_q <= #1 1'b0;
        end else begin
            cle_q <= #1 cle_d;
            dq_en_q <= #1 dq_en_d;
            state_q <= #1 state_d;
            ready_q <= #1 ready_d;
        end

        saved_rw_q <= #1 saved_rw_d;
        saved_data_q <= #1 saved_data_d;
        saved_addr_q <= #1 saved_addr_d;

        cmd_q <= #1 cmd_d;
        dqm_q <= #1 dqm_d;
        ba_q <= #1 ba_d;
        a_q <= #1 a_d;
        dq_q <= #1 dq_d;
        dqi_q <= #1 dqi_d;

        next_state_q <= #1 next_state_d;
        refresh_flag_q <= #1 refresh_flag_d;
        refresh_ctr_q <= #1 refresh_ctr_d;
        data_q <= #1 data_d;
        addr_q <= #1 addr_d;
        out_valid_q <= #1 out_valid_d;
        row_open_q <= #1 row_open_d;
        for (i = 0; i < 4; i = i + 1)
            row_addr_q[i] <= #1 row_addr_d[i];
        precharge_bank_q <= #1 precharge_bank_d;
        rw_op_q <= #1 rw_op_d;
        byte_ctr_q <= #1 byte_ctr_d;
        delay_ctr_q <= #1 delay_ctr_d;
    end
endmodule
module sdram#(
        parameter CAS_LATENCY = 3'b011,
        parameter REF_COUNTER_BITS = 11,
        parameter REF_COUNT = 1000
        ) (
        input clk,
        input rst,


        output sdram_clk,
        output sdram_cle,
        output sdram_cs,
        output sdram_cas,
        output sdram_ras,
        output sdram_we,
        output sdram_dqm,
        output [1:0] sdram_ba,
        output [12:0] sdram_a,
        inout [7:0] sdram_dq,


        input [22:0] addr,
        input rw,
        input [31:0] data_in,
        output [31:0] data_out,
        output busy,
        input in_valid,
        output out_valid
    );



    localparam CMD_UNSELECTED    = 4'b1000;
    localparam CMD_NOP           = 4'b0111;
    localparam CMD_ACTIVE        = 4'b0011;
    localparam CMD_READ          = 4'b0101;
    localparam CMD_WRITE         = 4'b0100;
    localparam CMD_TERMINATE     = 4'b0110;
    localparam CMD_PRECHARGE     = 4'b0010;
    localparam CMD_REFRESH       = 4'b0001;
    localparam CMD_LOAD_MODE_REG = 4'b0000;

    localparam STATE_SIZE = 4;
    localparam INIT = 0,
               WAIT = 1,
               PRECHARGE_INIT = 2,
               REFRESH_INIT_1 = 3,
               REFRESH_INIT_2 = 4,
               LOAD_MODE_REG = 5,
               IDLE = 6,
               REFRESH = 7,
               ACTIVATE = 8,
               READ = 9,
               READ_RES = 10,
               WRITE = 11,
               PRECHARGE = 12;

    wire sdram_clk_ddr;


    ODDR2 #(
        .DDR_ALIGNMENT("NONE"),
        .INIT(1'b0),
        .SRTYPE("SYNC")
    ) ODDR2_inst (
        .Q(sdram_clk_ddr),
        .C0(clk),
        .C1(~clk),
        .CE(1'b1),
        .D0(`SDRAM_CLK_D0),
        .D1(`SDRAM_CLK_D1),
        .R(1'b0),
        .S(1'b0)
    );

    IODELAY2 #(
        .IDELAY_VALUE(0),
        .IDELAY_MODE("NORMAL"),
        .ODELAY_VALUE(`SDRAM_CLK_ODELAY),
        .IDELAY_TYPE("FIXED"),
        .DELAY_SRC("ODATAIN"),
        .DATA_RATE("SDR")
    ) IODELAY_inst (
        .IDATAIN(1'b0),
        .T(1'b0),
        .ODATAIN(sdram_clk_ddr),
        .CAL(1'b0),
        .IOCLK0(1'b0),
        .IOCLK1(1'b0),
        .CLK(1'b0),
        .INC(1'b0),
        .CE(1'b0),
        .RST(1'b0),
        .BUSY(),
        .DATAOUT(),
        .DATAOUT2(),
        .TOUT(),
        .DOUT(sdram_clk)
    );


    reg cle_d, dqm_d;
    reg [3:0] cmd_d;
    reg [1:0] ba_d;
    reg [12:0] a_d;
    reg [7:0] dq_d;
    reg [7:0] dqi_d;




    (* IOB = "TRUE" *)
    reg cle_q, dqm_q;
    (* IOB = "TRUE" *)
    reg [3:0] cmd_q;
    (* IOB = "TRUE" *)
    reg [1:0] ba_q;
    (* IOB = "TRUE" *)
    reg [12:0] a_q;
    (* IOB = "TRUE" *)
    reg [7:0] dq_q;
    (* IOB = "TRUE" *)
    reg [7:0] dqi_q;
    reg dq_en_d, dq_en_q;


    assign sdram_cle = cle_q;
    assign sdram_cs = cmd_q[3];
    assign sdram_ras = cmd_q[2];
    assign sdram_cas = cmd_q[1];
    assign sdram_we = cmd_q[0];
    assign sdram_dqm = dqm_q;
    assign sdram_ba = ba_q;
    assign sdram_a = a_q;
    assign sdram_dq = dq_en_q ? dq_q : 8'hZZ;

    reg [STATE_SIZE-1:0] state_d, state_q = INIT;
    reg [STATE_SIZE-1:0] next_state_d, next_state_q;

    reg [22:0] addr_d, addr_q;
    reg [31:0] data_d, data_q;
    reg out_valid_d, out_valid_q;

    assign data_out = data_q;
    assign busy = !ready_q;
    assign out_valid = out_valid_q;

    reg [15:0] delay_ctr_d, delay_ctr_q;
    reg [1:0] byte_ctr_d, byte_ctr_q;

    reg [REF_COUNTER_BITS-1:0] refresh_ctr_d, refresh_ctr_q;
    reg refresh_flag_d, refresh_flag_q;

    reg ready_d, ready_q;
    reg saved_rw_d, saved_rw_q;
    reg [22:0] saved_addr_d, saved_addr_q;
    reg [31:0] saved_data_d, saved_data_q;

    reg rw_op_d, rw_op_q;

    reg [3:0] row_open_d, row_open_q;
    reg [12:0] row_addr_d[3:0], row_addr_q[3:0];

    reg [2:0] precharge_bank_d, precharge_bank_q;
    integer i;

    always @* begin

        dq_d = dq_q;
        dqi_d = sdram_dq;
        dq_en_d = 1'b0;
        cle_d = cle_q;
        cmd_d = CMD_NOP;
        dqm_d = 1'b0;
        ba_d = 2'd0;
        a_d = 25'd0;
        state_d = state_q;
        next_state_d = next_state_q;
        delay_ctr_d = delay_ctr_q;
        addr_d = addr_q;
        data_d = data_q;
        out_valid_d = 1'b0;
        precharge_bank_d = precharge_bank_q;
        rw_op_d = rw_op_q;
        byte_ctr_d = 2'd0;

        row_open_d = row_open_q;


        for (i = 0; i < 4; i = i + 1)
            row_addr_d[i] = row_addr_q[i];



        refresh_flag_d = refresh_flag_q;
        refresh_ctr_d = refresh_ctr_q + 1'b1;
        if (refresh_ctr_q > REF_COUNT) begin
            refresh_ctr_d = {REF_COUNTER_BITS{1'b0}};
            refresh_flag_d = 1'b1;
        end

        saved_rw_d = saved_rw_q;
        saved_data_d = saved_data_q;
        saved_addr_d = saved_addr_q;
        ready_d = ready_q;




        if (ready_q && in_valid) begin
            saved_rw_d = rw;
            saved_data_d = data_in;
            saved_addr_d = addr;
            ready_d = 1'b0;
        end

        case (state_q)

            INIT: begin
                ready_d = 1'b0;
                row_open_d = 4'b0;
                out_valid_d = 1'b0;
                a_d = 13'b0;
                ba_d = 2'b0;
                cle_d = 1'b1;
                state_d = WAIT;
                delay_ctr_d = 16'd10100;
                next_state_d = PRECHARGE_INIT;
                dq_en_d = 1'b0;
            end
            WAIT: begin
                delay_ctr_d = delay_ctr_q - 1'b1;
                if (delay_ctr_q == 16'd0) begin
                    state_d = next_state_q;
                    if (next_state_q == WRITE) begin
                        dq_en_d = 1'b1;
                        dq_d = data_q[7:0];
                    end
                end
            end
            PRECHARGE_INIT: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = 1'b1;
                ba_d = 2'd0;
                state_d = WAIT;
                next_state_d = REFRESH_INIT_1;
                delay_ctr_d = 16'd0;
            end
            REFRESH_INIT_1: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd7;
                next_state_d = REFRESH_INIT_2;
            end
            REFRESH_INIT_2: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd7;
                next_state_d = LOAD_MODE_REG;
            end
            LOAD_MODE_REG: begin
                cmd_d = CMD_LOAD_MODE_REG;
                ba_d = 2'b0;

                a_d = {3'b000, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b010};
                state_d = WAIT;
                delay_ctr_d = 16'd2;
                next_state_d = IDLE;
                refresh_flag_d = 1'b0;
                refresh_ctr_d = {REF_COUNTER_BITS{1'b1}};
                ready_d = 1'b1;
            end


            IDLE: begin
                if (refresh_flag_q) begin
                    state_d = PRECHARGE;
                    next_state_d = REFRESH;
                    precharge_bank_d = 3'b100;
                    refresh_flag_d = 1'b0;
                end else if (!ready_q) begin
                    ready_d = 1'b1;
                    rw_op_d = saved_rw_q;
                    addr_d = saved_addr_q;

                    if (saved_rw_q)
                        data_d = saved_data_q;


                    if (row_open_q[saved_addr_q[9:8]]) begin
                        if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin

                            if (saved_rw_q)
                                state_d = WRITE;
                            else
                                state_d = READ;
                        end else begin

                            state_d = PRECHARGE;
                            precharge_bank_d = {1'b0, saved_addr_q[9:8]};
                            next_state_d = ACTIVATE;
                        end
                    end else begin

                        state_d = ACTIVATE;
                    end
                end
            end


            REFRESH: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 16'd6;
                next_state_d = IDLE;
            end


            ACTIVATE: begin
                cmd_d = CMD_ACTIVE;
                a_d = addr_q[22:10];
                ba_d = addr_q[9:8];
                delay_ctr_d = 16'd0;
                state_d = WAIT;

                if (rw_op_q)
                    next_state_d = WRITE;
                else
                    next_state_d = READ;

                row_open_d[addr_q[9:8]] = 1'b1;
                row_addr_d[addr_q[9:8]] = addr_q[22:10];
            end


            READ: begin
                cmd_d = CMD_READ;
                a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
                ba_d = addr_q[9:8];
                state_d = WAIT;
                delay_ctr_d = `SDRAM_READ_DELAY_CLK;
                next_state_d = READ_RES;

            end
            READ_RES: begin
                byte_ctr_d = byte_ctr_q + 1'b1;
                data_d = {dqi_q, data_q[31:8]};
                if (byte_ctr_q == 2'd3) begin
                    out_valid_d = 1'b1;
                    state_d = IDLE;
                end
            end


            WRITE: begin
                byte_ctr_d = byte_ctr_q + 1'b1;

                if (byte_ctr_q == 2'd0)
                    cmd_d = CMD_WRITE;

                dq_d = data_q[7:0];
                data_d = {8'h00, data_q[31:8]};
                dq_en_d = 1'b1;
                a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
                ba_d = addr_q[9:8];

                if (byte_ctr_q == 2'd3) begin
                    state_d = IDLE;
                end
            end


            PRECHARGE: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = precharge_bank_q[2];
                ba_d = precharge_bank_q[1:0];
                state_d = WAIT;
                delay_ctr_d = 16'd1;

                if (precharge_bank_q[2]) begin
                    row_open_d = 4'b0000;
                end else begin
                    row_open_d[precharge_bank_q[1:0]] = 1'b0;
                end
            end

            default: state_d = INIT;
        endcase

    end

    always @(posedge clk) begin
        if(rst) begin
            cle_q <= #1 1'b0;
            dq_en_q <= #1 1'b0;
            state_q <= #1 INIT;
            ready_q <= #1 1'b0;
        end else begin
            cle_q <= #1 cle_d;
            dq_en_q <= #1 dq_en_d;
            state_q <= #1 state_d;
            ready_q <= #1 ready_d;
        end

        saved_rw_q <= #1 saved_rw_d;
        saved_data_q <= #1 saved_data_d;
        saved_addr_q <= #1 saved_addr_d;

        cmd_q <= #1 cmd_d;
        dqm_q <= #1 dqm_d;
        ba_q <= #1 ba_d;
        a_q <= #1 a_d;
        dq_q <= #1 dq_d;
        dqi_q <= #1 dqi_d;

        next_state_q <= #1 next_state_d;
        refresh_flag_q <= #1 refresh_flag_d;
        refresh_ctr_q <= #1 refresh_ctr_d;
        data_q <= #1 data_d;
        addr_q <= #1 addr_d;
        out_valid_q <= #1 out_valid_d;
        row_open_q <= #1 row_open_d;
        for (i = 0; i < 4; i = i + 1)
            row_addr_q[i] <= #1 row_addr_d[i];
        precharge_bank_q <= #1 precharge_bank_d;
        rw_op_q <= #1 rw_op_d;
        byte_ctr_q <= #1 byte_ctr_d;
        delay_ctr_q <= #1 delay_ctr_d;
    end
endmodule