data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:7: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    m0_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`MemAddrBus]    m0_axi_awaddr , \n                           ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m0_axi_awvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m0_axi_awready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:12: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemBus]        m0_axi_wdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:12: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus]        m0_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m0_axi_wvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m0_axi_wready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [1:0]            m0_axi_bresp  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:18: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  m0_axi_bvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:19: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  m0_axi_bready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`MemAddrBus]    m0_axi_araddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:21: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    m0_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m0_axi_arvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m0_axi_arready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemBus]        m0_axi_rdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:26: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        m0_axi_rdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  m0_axi_rvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:29: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  m0_axi_rready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`MemAddrBus]    m1_axi_awaddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:32: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    m1_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m1_axi_awvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m1_axi_awready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:37: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemBus]        m1_axi_wdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:37: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus]        m1_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m1_axi_wvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:40: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m1_axi_wready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [1:0]            m1_axi_bresp  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  m1_axi_bvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:44: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  m1_axi_bready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:46: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`MemAddrBus]    m1_axi_araddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:46: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    m1_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  m1_axi_arvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  m1_axi_arready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:51: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemBus]        m1_axi_rdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:51: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        m1_axi_rdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:53: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  m1_axi_rvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:54: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  m1_axi_rready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:58: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [`MemAddrBus]    s0_axi_awaddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:58: Define or directive not defined: \'`MemAddrBus\'\n    output reg [`MemAddrBus]    s0_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:60: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  s0_axi_awready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:62: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [`MemBus]        s0_axi_wdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:62: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        s0_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:64: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  s0_axi_wvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:65: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  s0_axi_wready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:67: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [`MemAddrBus]    s0_axi_araddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:67: Define or directive not defined: \'`MemAddrBus\'\n    output reg [`MemAddrBus]    s0_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:69: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  s0_axi_arready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/axi4lite_2mt16s.v:71: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`MemBus]        s0_axi_rdata  , \n    ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module axi4lite_2mt16s (
	input clk,
	input rst_n,


    input wire [`MemAddrBus]    m0_axi_awaddr ,
    input wire [2:0]            m0_axi_awprot ,
    input wire                  m0_axi_awvalid,
    output reg                  m0_axi_awready,

    input wire [`MemBus]        m0_axi_wdata  ,
    input wire [3:0]            m0_axi_wstrb  ,
    input wire                  m0_axi_wvalid ,
    output reg                  m0_axi_wready ,

    output reg [1:0]            m0_axi_bresp  ,
    output reg                  m0_axi_bvalid ,
    input wire                  m0_axi_bready ,

    input wire [`MemAddrBus]    m0_axi_araddr ,
    input wire [2:0]            m0_axi_arprot ,
    input wire                  m0_axi_arvalid,
    output reg                  m0_axi_arready,

    output reg [`MemBus]        m0_axi_rdata  ,
    output reg [1:0]            m0_axi_rresp  ,
    output reg                  m0_axi_rvalid ,
    input wire                  m0_axi_rready ,


    input wire [`MemAddrBus]    m1_axi_awaddr ,
    input wire [2:0]            m1_axi_awprot ,
    input wire                  m1_axi_awvalid,
    output reg                  m1_axi_awready,

    input wire [`MemBus]        m1_axi_wdata  ,
    input wire [3:0]            m1_axi_wstrb  ,
    input wire                  m1_axi_wvalid ,
    output reg                  m1_axi_wready ,

    output reg [1:0]            m1_axi_bresp  ,
    output reg                  m1_axi_bvalid ,
    input wire                  m1_axi_bready ,

    input wire [`MemAddrBus]    m1_axi_araddr ,
    input wire [2:0]            m1_axi_arprot ,
    input wire                  m1_axi_arvalid,
    output reg                  m1_axi_arready,

    output reg [`MemBus]        m1_axi_rdata  ,
    output reg [1:0]            m1_axi_rresp  ,
    output reg                  m1_axi_rvalid ,
    input wire                  m1_axi_rready ,



    output reg [`MemAddrBus]    s0_axi_awaddr ,
    output reg                  s0_axi_awvalid,
    input wire                  s0_axi_awready,

    output reg [`MemBus]        s0_axi_wdata  ,
    output reg [3:0]            s0_axi_wstrb  ,
    output reg                  s0_axi_wvalid ,
    input wire                  s0_axi_wready ,

    output reg [`MemAddrBus]    s0_axi_araddr ,
    output reg                  s0_axi_arvalid,
    input wire                  s0_axi_arready,

    input wire [`MemBus]        s0_axi_rdata  ,
    input wire                  s0_axi_rvalid ,
    output reg                  s0_axi_rready ,


    output reg [`MemAddrBus]    s1_axi_awaddr ,
    output reg                  s1_axi_awvalid,
    input wire                  s1_axi_awready,

    output reg [`MemBus]        s1_axi_wdata  ,
    output reg [3:0]            s1_axi_wstrb  ,
    output reg                  s1_axi_wvalid ,
    input wire                  s1_axi_wready ,

    output reg [`MemAddrBus]    s1_axi_araddr ,
    output reg                  s1_axi_arvalid,
    input wire                  s1_axi_arready,

    input wire [`MemBus]        s1_axi_rdata  ,
    input wire                  s1_axi_rvalid ,
    output reg                  s1_axi_rready ,


    output reg [`MemAddrBus]    s2_axi_awaddr ,
    output reg                  s2_axi_awvalid,
    input wire                  s2_axi_awready,

    output reg [`MemBus]        s2_axi_wdata  ,
    output reg [3:0]            s2_axi_wstrb  ,
    output reg                  s2_axi_wvalid ,
    input wire                  s2_axi_wready ,

    output reg [`MemAddrBus]    s2_axi_araddr ,
    output reg                  s2_axi_arvalid,
    input wire                  s2_axi_arready,

    input wire [`MemBus]        s2_axi_rdata  ,
    input wire                  s2_axi_rvalid ,
    output reg                  s2_axi_rready ,


    output reg [`MemAddrBus]    s3_axi_awaddr ,
    output reg                  s3_axi_awvalid,
    input wire                  s3_axi_awready,

    output reg [`MemBus]        s3_axi_wdata  ,
    output reg [3:0]            s3_axi_wstrb  ,
    output reg                  s3_axi_wvalid ,
    input wire                  s3_axi_wready ,

    output reg [`MemAddrBus]    s3_axi_araddr ,
    output reg                  s3_axi_arvalid,
    input wire                  s3_axi_arready,

    input wire [`MemBus]        s3_axi_rdata  ,
    input wire                  s3_axi_rvalid ,
    output reg                  s3_axi_rready ,


    output reg [`MemAddrBus]    s4_axi_awaddr ,
    output reg                  s4_axi_awvalid,
    input wire                  s4_axi_awready,

    output reg [`MemBus]        s4_axi_wdata  ,
    output reg [3:0]            s4_axi_wstrb  ,
    output reg                  s4_axi_wvalid ,
    input wire                  s4_axi_wready ,

    output reg [`MemAddrBus]    s4_axi_araddr ,
    output reg                  s4_axi_arvalid,
    input wire                  s4_axi_arready,

    input wire [`MemBus]        s4_axi_rdata  ,
    input wire                  s4_axi_rvalid ,
    output reg                  s4_axi_rready ,


    output reg [`MemAddrBus]    s5_axi_awaddr ,
    output reg                  s5_axi_awvalid,
    input wire                  s5_axi_awready,

    output reg [`MemBus]        s5_axi_wdata  ,
    output reg [3:0]            s5_axi_wstrb  ,
    output reg                  s5_axi_wvalid ,
    input wire                  s5_axi_wready ,

    output reg [`MemAddrBus]    s5_axi_araddr ,
    output reg                  s5_axi_arvalid,
    input wire                  s5_axi_arready,

    input wire [`MemBus]        s5_axi_rdata  ,
    input wire                  s5_axi_rvalid ,
    output reg                  s5_axi_rready ,


    output reg [`MemAddrBus]    s6_axi_awaddr ,
    output reg                  s6_axi_awvalid,
    input wire                  s6_axi_awready,

    output reg [`MemBus]        s6_axi_wdata  ,
    output reg [3:0]            s6_axi_wstrb  ,
    output reg                  s6_axi_wvalid ,
    input wire                  s6_axi_wready ,

    output reg [`MemAddrBus]    s6_axi_araddr ,
    output reg                  s6_axi_arvalid,
    input wire                  s6_axi_arready,

    input wire [`MemBus]        s6_axi_rdata  ,
    input wire                  s6_axi_rvalid ,
    output reg                  s6_axi_rready ,


    output reg [`MemAddrBus]    s7_axi_awaddr ,
    output reg                  s7_axi_awvalid,
    input wire                  s7_axi_awready,

    output reg [`MemBus]        s7_axi_wdata  ,
    output reg [3:0]            s7_axi_wstrb  ,
    output reg                  s7_axi_wvalid ,
    input wire                  s7_axi_wready ,

    output reg [`MemAddrBus]    s7_axi_araddr ,
    output reg                  s7_axi_arvalid,
    input wire                  s7_axi_arready,

    input wire [`MemBus]        s7_axi_rdata  ,
    input wire                  s7_axi_rvalid ,
    output reg                  s7_axi_rready ,


    output reg [`MemAddrBus]    s8_axi_awaddr ,
    output reg                  s8_axi_awvalid,
    input wire                  s8_axi_awready,

    output reg [`MemBus]        s8_axi_wdata  ,
    output reg [3:0]            s8_axi_wstrb  ,
    output reg                  s8_axi_wvalid ,
    input wire                  s8_axi_wready ,

    output reg [`MemAddrBus]    s8_axi_araddr ,
    output reg                  s8_axi_arvalid,
    input wire                  s8_axi_arready,

    input wire [`MemBus]        s8_axi_rdata  ,
    input wire                  s8_axi_rvalid ,
    output reg                  s8_axi_rready ,


    output reg [`MemAddrBus]    s9_axi_awaddr ,
    output reg                  s9_axi_awvalid,
    input wire                  s9_axi_awready,

    output reg [`MemBus]        s9_axi_wdata  ,
    output reg [3:0]            s9_axi_wstrb  ,
    output reg                  s9_axi_wvalid ,
    input wire                  s9_axi_wready ,

    output reg [`MemAddrBus]    s9_axi_araddr ,
    output reg                  s9_axi_arvalid,
    input wire                  s9_axi_arready,

    input wire [`MemBus]        s9_axi_rdata  ,
    input wire                  s9_axi_rvalid ,
    output reg                  s9_axi_rready ,


    output reg [`MemAddrBus]    s10_axi_awaddr ,
    output reg                  s10_axi_awvalid,
    input wire                  s10_axi_awready,

    output reg [`MemBus]        s10_axi_wdata  ,
    output reg [3:0]            s10_axi_wstrb  ,
    output reg                  s10_axi_wvalid ,
    input wire                  s10_axi_wready ,

    output reg [`MemAddrBus]    s10_axi_araddr ,
    output reg                  s10_axi_arvalid,
    input wire                  s10_axi_arready,

    input wire [`MemBus]        s10_axi_rdata  ,
    input wire                  s10_axi_rvalid ,
    output reg                  s10_axi_rready ,


    output reg [`MemAddrBus]    s11_axi_awaddr ,
    output reg                  s11_axi_awvalid,
    input wire                  s11_axi_awready,

    output reg [`MemBus]        s11_axi_wdata  ,
    output reg [3:0]            s11_axi_wstrb  ,
    output reg                  s11_axi_wvalid ,
    input wire                  s11_axi_wready ,

    output reg [`MemAddrBus]    s11_axi_araddr ,
    output reg                  s11_axi_arvalid,
    input wire                  s11_axi_arready,

    input wire [`MemBus]        s11_axi_rdata  ,
    input wire                  s11_axi_rvalid ,
    output reg                  s11_axi_rready ,


    output reg [`MemAddrBus]    s12_axi_awaddr ,
    output reg                  s12_axi_awvalid,
    input wire                  s12_axi_awready,

    output reg [`MemBus]        s12_axi_wdata  ,
    output reg [3:0]            s12_axi_wstrb  ,
    output reg                  s12_axi_wvalid ,
    input wire                  s12_axi_wready ,

    output reg [`MemAddrBus]    s12_axi_araddr ,
    output reg                  s12_axi_arvalid,
    input wire                  s12_axi_arready,

    input wire [`MemBus]        s12_axi_rdata  ,
    input wire                  s12_axi_rvalid ,
    output reg                  s12_axi_rready ,


    output reg [`MemAddrBus]    s13_axi_awaddr ,
    output reg                  s13_axi_awvalid,
    input wire                  s13_axi_awready,

    output reg [`MemBus]        s13_axi_wdata  ,
    output reg [3:0]            s13_axi_wstrb  ,
    output reg                  s13_axi_wvalid ,
    input wire                  s13_axi_wready ,

    output reg [`MemAddrBus]    s13_axi_araddr ,
    output reg                  s13_axi_arvalid,
    input wire                  s13_axi_arready,

    input wire [`MemBus]        s13_axi_rdata  ,
    input wire                  s13_axi_rvalid ,
    output reg                  s13_axi_rready ,


    output reg [`MemAddrBus]    s14_axi_awaddr ,
    output reg                  s14_axi_awvalid,
    input wire                  s14_axi_awready,

    output reg [`MemBus]        s14_axi_wdata  ,
    output reg [3:0]            s14_axi_wstrb  ,
    output reg                  s14_axi_wvalid ,
    input wire                  s14_axi_wready ,

    output reg [`MemAddrBus]    s14_axi_araddr ,
    output reg                  s14_axi_arvalid,
    input wire                  s14_axi_arready,

    input wire [`MemBus]        s14_axi_rdata  ,
    input wire                  s14_axi_rvalid ,
    output reg                  s14_axi_rready ,


    output reg [`MemAddrBus]    s15_axi_awaddr ,
    output reg                  s15_axi_awvalid,
    input wire                  s15_axi_awready,

    output reg [`MemBus]        s15_axi_wdata  ,
    output reg [3:0]            s15_axi_wstrb  ,
    output reg                  s15_axi_wvalid ,
    input wire                  s15_axi_wready ,

    output reg [`MemAddrBus]    s15_axi_araddr ,
    output reg                  s15_axi_arvalid,
    input wire                  s15_axi_arready,

    input wire [`MemBus]        s15_axi_rdata  ,
    input wire                  s15_axi_rvalid ,
    output reg                  s15_axi_rready

);


wire m0_wbus_en = m0_axi_awvalid & m0_axi_wvalid;
wire m1_wbus_en = m1_axi_awvalid & m1_axi_wvalid & ~m0_wbus_en;

wire m0_abus_en = m0_axi_arvalid;
wire m1_abus_en = m1_axi_arvalid & ~m0_abus_en;


reg m0_rbus_en;
reg m1_rbus_en;


wire [`MemAddrBus]    master_axi_awaddr ;
wire                  master_axi_awvalid;
wire                  master_axi_awready;
wire [`MemBus]        master_axi_wdata  ;
wire [3:0]            master_axi_wstrb  ;
wire                  master_axi_wvalid ;
wire                  master_axi_wready ;
wire [`MemAddrBus]    master_axi_araddr ;
wire                  master_axi_arvalid;
wire                  master_axi_arready;
reg  [`MemBus]        master_axi_rdata  ;
wire                  master_axi_rvalid ;
wire                  master_axi_rready ;

assign master_axi_awaddr  = m0_wbus_en ? m0_axi_awaddr : m1_axi_awaddr;
assign master_axi_awvalid = ({1{m0_wbus_en}} & m0_axi_awvalid)
                            | ({1{m1_wbus_en}} & m1_axi_awvalid);
assign master_axi_wdata   = m0_wbus_en ? m0_axi_wdata : m1_axi_wdata;
assign master_axi_wstrb   = m0_wbus_en ? m0_axi_wstrb : m1_axi_wstrb;
assign master_axi_wvalid  = ({1{m0_wbus_en}} & m0_axi_wvalid)
                            | ({1{m1_wbus_en}} & m1_axi_wvalid);
assign master_axi_araddr  = m0_abus_en ? m0_axi_araddr : m1_axi_araddr;
assign master_axi_arvalid = ({1{m0_abus_en}} & m0_axi_arvalid)
                            | ({1{m1_abus_en}} & m1_axi_arvalid);
assign master_axi_rready  = ({1{m0_rbus_en}} & m0_axi_rready)
                            | ({1{m1_rbus_en}} & m1_axi_rready);

always @(*) begin
    m0_axi_awready = {1 {m0_wbus_en}} & master_axi_awready;
    m0_axi_wready  = {1 {m0_wbus_en}} & master_axi_wready ;
    m0_axi_arready = {1 {m0_abus_en}} & master_axi_arready;
    m0_axi_rdata   = master_axi_rdata  ;
    m0_axi_rvalid  = {1 {m0_rbus_en}} & master_axi_rvalid ;
    m1_axi_awready = {1 {m1_wbus_en}} & master_axi_awready;
    m1_axi_wready  = {1 {m1_wbus_en}} & master_axi_wready ;
    m1_axi_arready = {1 {m1_abus_en}} & master_axi_arready;
    m1_axi_rdata   = master_axi_rdata  ;
    m1_axi_rvalid  = {1 {m1_rbus_en}} & master_axi_rvalid ;
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        m0_rbus_en <= 0;
        m1_rbus_en <= 0;
    end
    else begin
        if (m0_axi_arvalid & m0_axi_arready)
            m0_rbus_en <=1'b1;
        else if (m0_rbus_en & m0_axi_rvalid & m0_axi_rready)
            m0_rbus_en <=1'b0;
        else
            m0_rbus_en <= m0_rbus_en;
        if (m1_axi_arvalid & m1_axi_arready)
            m1_rbus_en <=1'b1;
        else if (m1_rbus_en & m1_axi_rvalid & m1_axi_rready)
            m1_rbus_en <=1'b0;
        else
            m1_rbus_en <= m1_rbus_en;
    end
end



wire [3:0] wbus_mux;
wire [15:0] wbus_sel;
wire [3:0] abus_mux;
wire [15:0] abus_sel;
reg [3:0] rbus_mux;
reg [15:0] rbus_sel;


assign wbus_mux = master_axi_awaddr [31:28];
assign wbus_sel[0 ] = wbus_mux == 4'd0  ? 1'b1 : 1'b0;
assign wbus_sel[1 ] = wbus_mux == 4'd1  ? 1'b1 : 1'b0;
assign wbus_sel[2 ] = wbus_mux == 4'd2  ? 1'b1 : 1'b0;
assign wbus_sel[3 ] = wbus_mux == 4'd3  ? 1'b1 : 1'b0;
assign wbus_sel[4 ] = wbus_mux == 4'd4  ? 1'b1 : 1'b0;
assign wbus_sel[5 ] = wbus_mux == 4'd5  ? 1'b1 : 1'b0;
assign wbus_sel[6 ] = wbus_mux == 4'd6  ? 1'b1 : 1'b0;
assign wbus_sel[7 ] = wbus_mux == 4'd7  ? 1'b1 : 1'b0;
assign wbus_sel[8 ] = wbus_mux == 4'd8  ? 1'b1 : 1'b0;
assign wbus_sel[9 ] = wbus_mux == 4'd9  ? 1'b1 : 1'b0;
assign wbus_sel[10] = wbus_mux == 4'd10 ? 1'b1 : 1'b0;
assign wbus_sel[11] = wbus_mux == 4'd11 ? 1'b1 : 1'b0;
assign wbus_sel[12] = wbus_mux == 4'd12 ? 1'b1 : 1'b0;
assign wbus_sel[13] = wbus_mux == 4'd13 ? 1'b1 : 1'b0;
assign wbus_sel[14] = wbus_mux == 4'd14 ? 1'b1 : 1'b0;
assign wbus_sel[15] = wbus_mux == 4'd15 ? 1'b1 : 1'b0;

always @(*) begin
    s0_axi_awaddr  = wbus_mux == 4'd0  ? master_axi_awaddr : 32'b0;
    s1_axi_awaddr  = wbus_mux == 4'd1  ? master_axi_awaddr : 32'b0;
    s2_axi_awaddr  = wbus_mux == 4'd2  ? master_axi_awaddr : 32'b0;
    s3_axi_awaddr  = wbus_mux == 4'd3  ? master_axi_awaddr : 32'b0;
    s4_axi_awaddr  = wbus_mux == 4'd4  ? master_axi_awaddr : 32'b0;
    s5_axi_awaddr  = wbus_mux == 4'd5  ? master_axi_awaddr : 32'b0;
    s6_axi_awaddr  = wbus_mux == 4'd6  ? master_axi_awaddr : 32'b0;
    s7_axi_awaddr  = wbus_mux == 4'd7  ? master_axi_awaddr : 32'b0;
    s8_axi_awaddr  = wbus_mux == 4'd8  ? master_axi_awaddr : 32'b0;
    s9_axi_awaddr  = wbus_mux == 4'd9  ? master_axi_awaddr : 32'b0;
    s10_axi_awaddr = wbus_mux == 4'd10 ? master_axi_awaddr : 32'b0;
    s11_axi_awaddr = wbus_mux == 4'd11 ? master_axi_awaddr : 32'b0;
    s12_axi_awaddr = wbus_mux == 4'd12 ? master_axi_awaddr : 32'b0;
    s13_axi_awaddr = wbus_mux == 4'd13 ? master_axi_awaddr : 32'b0;
    s14_axi_awaddr = wbus_mux == 4'd14 ? master_axi_awaddr : 32'b0;
    s15_axi_awaddr = wbus_mux == 4'd15 ? master_axi_awaddr : 32'b0;

    s0_axi_awvalid  =  {1{wbus_sel[0]}} & master_axi_awvalid;
    s1_axi_awvalid  =  {1{wbus_sel[1]}} & master_axi_awvalid;
    s2_axi_awvalid  =  {1{wbus_sel[2]}} & master_axi_awvalid;
    s3_axi_awvalid  =  {1{wbus_sel[3]}} & master_axi_awvalid;
    s4_axi_awvalid  =  {1{wbus_sel[4]}} & master_axi_awvalid;
    s5_axi_awvalid  =  {1{wbus_sel[5]}} & master_axi_awvalid;
    s6_axi_awvalid  =  {1{wbus_sel[6]}} & master_axi_awvalid;
    s7_axi_awvalid  =  {1{wbus_sel[7]}} & master_axi_awvalid;
    s8_axi_awvalid  =  {1{wbus_sel[8]}} & master_axi_awvalid;
    s9_axi_awvalid  =  {1{wbus_sel[9]}} & master_axi_awvalid;
    s10_axi_awvalid = {1{wbus_sel[10]}} & master_axi_awvalid;
    s11_axi_awvalid = {1{wbus_sel[11]}} & master_axi_awvalid;
    s12_axi_awvalid = {1{wbus_sel[12]}} & master_axi_awvalid;
    s13_axi_awvalid = {1{wbus_sel[13]}} & master_axi_awvalid;
    s14_axi_awvalid = {1{wbus_sel[14]}} & master_axi_awvalid;
    s15_axi_awvalid = {1{wbus_sel[15]}} & master_axi_awvalid;


    s0_axi_wdata   = master_axi_wdata  ;
    s1_axi_wdata   = master_axi_wdata  ;
    s2_axi_wdata   = master_axi_wdata  ;
    s3_axi_wdata   = master_axi_wdata  ;
    s4_axi_wdata   = master_axi_wdata  ;
    s5_axi_wdata   = master_axi_wdata  ;
    s6_axi_wdata   = master_axi_wdata  ;
    s7_axi_wdata   = master_axi_wdata  ;
    s8_axi_wdata   = master_axi_wdata  ;
    s9_axi_wdata   = master_axi_wdata  ;
    s10_axi_wdata  = master_axi_wdata  ;
    s11_axi_wdata  = master_axi_wdata  ;
    s12_axi_wdata  = master_axi_wdata  ;
    s13_axi_wdata  = master_axi_wdata  ;
    s14_axi_wdata  = master_axi_wdata  ;
    s15_axi_wdata  = master_axi_wdata  ;

    s0_axi_wstrb  = master_axi_wstrb ;
    s1_axi_wstrb  = master_axi_wstrb ;
    s2_axi_wstrb  = master_axi_wstrb ;
    s3_axi_wstrb  = master_axi_wstrb ;
    s4_axi_wstrb  = master_axi_wstrb ;
    s5_axi_wstrb  = master_axi_wstrb ;
    s6_axi_wstrb  = master_axi_wstrb ;
    s7_axi_wstrb  = master_axi_wstrb ;
    s8_axi_wstrb  = master_axi_wstrb ;
    s9_axi_wstrb  = master_axi_wstrb ;
    s10_axi_wstrb = master_axi_wstrb ;
    s11_axi_wstrb = master_axi_wstrb ;
    s12_axi_wstrb = master_axi_wstrb ;
    s13_axi_wstrb = master_axi_wstrb ;
    s14_axi_wstrb = master_axi_wstrb ;
    s15_axi_wstrb = master_axi_wstrb ;

    s0_axi_wvalid =  {1{wbus_sel[0]}} & master_axi_wvalid ;
    s1_axi_wvalid =  {1{wbus_sel[1]}} & master_axi_wvalid ;
    s2_axi_wvalid =  {1{wbus_sel[2]}} & master_axi_wvalid ;
    s3_axi_wvalid =  {1{wbus_sel[3]}} & master_axi_wvalid ;
    s4_axi_wvalid =  {1{wbus_sel[4]}} & master_axi_wvalid ;
    s5_axi_wvalid =  {1{wbus_sel[5]}} & master_axi_wvalid ;
    s6_axi_wvalid =  {1{wbus_sel[6]}} & master_axi_wvalid ;
    s7_axi_wvalid =  {1{wbus_sel[7]}} & master_axi_wvalid ;
    s8_axi_wvalid =  {1{wbus_sel[8]}} & master_axi_wvalid ;
    s9_axi_wvalid =  {1{wbus_sel[9]}} & master_axi_wvalid ;
    s10_axi_wvalid = {1{wbus_sel[10]}} & master_axi_wvalid ;
    s11_axi_wvalid = {1{wbus_sel[11]}} & master_axi_wvalid ;
    s12_axi_wvalid = {1{wbus_sel[12]}} & master_axi_wvalid ;
    s13_axi_wvalid = {1{wbus_sel[13]}} & master_axi_wvalid ;
    s14_axi_wvalid = {1{wbus_sel[14]}} & master_axi_wvalid ;
    s15_axi_wvalid = {1{wbus_sel[15]}} & master_axi_wvalid ;
end

assign master_axi_awready = wbus_sel[0] & s0_axi_awready
        | wbus_sel[1]  & s1_axi_awready
        | wbus_sel[2]  & s2_axi_awready
        | wbus_sel[3]  & s3_axi_awready
        | wbus_sel[4]  & s4_axi_awready
        | wbus_sel[5]  & s5_axi_awready
        | wbus_sel[6]  & s6_axi_awready
        | wbus_sel[7]  & s7_axi_awready
        | wbus_sel[8]  & s8_axi_awready
        | wbus_sel[9]  & s9_axi_awready
        | wbus_sel[10] & s10_axi_awready
        | wbus_sel[11] & s11_axi_awready
        | wbus_sel[12] & s12_axi_awready
        | wbus_sel[13] & s13_axi_awready
        | wbus_sel[14] & s14_axi_awready
        | wbus_sel[15] & s15_axi_awready;
assign master_axi_wready  = wbus_sel[0] & s0_axi_wready
        | wbus_sel[1]  & s1_axi_wready
        | wbus_sel[2]  & s2_axi_wready
        | wbus_sel[3]  & s3_axi_wready
        | wbus_sel[4]  & s4_axi_wready
        | wbus_sel[5]  & s5_axi_wready
        | wbus_sel[6]  & s6_axi_wready
        | wbus_sel[7]  & s7_axi_wready
        | wbus_sel[8]  & s8_axi_wready
        | wbus_sel[9]  & s9_axi_wready
        | wbus_sel[10] & s10_axi_wready
        | wbus_sel[11] & s11_axi_wready
        | wbus_sel[12] & s12_axi_wready
        | wbus_sel[13] & s13_axi_wready
        | wbus_sel[14] & s14_axi_wready
        | wbus_sel[15] & s15_axi_wready;


assign abus_mux = master_axi_araddr [31:28];
assign abus_sel[0 ] = abus_mux == 4'd0  ? 1'b1 : 1'b0;
assign abus_sel[1 ] = abus_mux == 4'd1  ? 1'b1 : 1'b0;
assign abus_sel[2 ] = abus_mux == 4'd2  ? 1'b1 : 1'b0;
assign abus_sel[3 ] = abus_mux == 4'd3  ? 1'b1 : 1'b0;
assign abus_sel[4 ] = abus_mux == 4'd4  ? 1'b1 : 1'b0;
assign abus_sel[5 ] = abus_mux == 4'd5  ? 1'b1 : 1'b0;
assign abus_sel[6 ] = abus_mux == 4'd6  ? 1'b1 : 1'b0;
assign abus_sel[7 ] = abus_mux == 4'd7  ? 1'b1 : 1'b0;
assign abus_sel[8 ] = abus_mux == 4'd8  ? 1'b1 : 1'b0;
assign abus_sel[9 ] = abus_mux == 4'd9  ? 1'b1 : 1'b0;
assign abus_sel[10] = abus_mux == 4'd10 ? 1'b1 : 1'b0;
assign abus_sel[11] = abus_mux == 4'd11 ? 1'b1 : 1'b0;
assign abus_sel[12] = abus_mux == 4'd12 ? 1'b1 : 1'b0;
assign abus_sel[13] = abus_mux == 4'd13 ? 1'b1 : 1'b0;
assign abus_sel[14] = abus_mux == 4'd14 ? 1'b1 : 1'b0;
assign abus_sel[15] = abus_mux == 4'd15 ? 1'b1 : 1'b0;

always @(*) begin
    s0_axi_araddr  = abus_mux == 4'd0  ? master_axi_araddr : 32'b0;
    s1_axi_araddr  = abus_mux == 4'd1  ? master_axi_araddr : 32'b0;
    s2_axi_araddr  = abus_mux == 4'd2  ? master_axi_araddr : 32'b0;
    s3_axi_araddr  = abus_mux == 4'd3  ? master_axi_araddr : 32'b0;
    s4_axi_araddr  = abus_mux == 4'd4  ? master_axi_araddr : 32'b0;
    s5_axi_araddr  = abus_mux == 4'd5  ? master_axi_araddr : 32'b0;
    s6_axi_araddr  = abus_mux == 4'd6  ? master_axi_araddr : 32'b0;
    s7_axi_araddr  = abus_mux == 4'd7  ? master_axi_araddr : 32'b0;
    s8_axi_araddr  = abus_mux == 4'd8  ? master_axi_araddr : 32'b0;
    s9_axi_araddr  = abus_mux == 4'd9  ? master_axi_araddr : 32'b0;
    s10_axi_araddr = abus_mux == 4'd10 ? master_axi_araddr : 32'b0;
    s11_axi_araddr = abus_mux == 4'd11 ? master_axi_araddr : 32'b0;
    s12_axi_araddr = abus_mux == 4'd12 ? master_axi_araddr : 32'b0;
    s13_axi_araddr = abus_mux == 4'd13 ? master_axi_araddr : 32'b0;
    s14_axi_araddr = abus_mux == 4'd14 ? master_axi_araddr : 32'b0;
    s15_axi_araddr = abus_mux == 4'd15 ? master_axi_araddr : 32'b0;

    s0_axi_arvalid  =  {1{abus_sel[0]}} & master_axi_arvalid ;
    s1_axi_arvalid  =  {1{abus_sel[1]}} & master_axi_arvalid ;
    s2_axi_arvalid  =  {1{abus_sel[2]}} & master_axi_arvalid ;
    s3_axi_arvalid  =  {1{abus_sel[3]}} & master_axi_arvalid ;
    s4_axi_arvalid  =  {1{abus_sel[4]}} & master_axi_arvalid ;
    s5_axi_arvalid  =  {1{abus_sel[5]}} & master_axi_arvalid ;
    s6_axi_arvalid  =  {1{abus_sel[6]}} & master_axi_arvalid ;
    s7_axi_arvalid  =  {1{abus_sel[7]}} & master_axi_arvalid ;
    s8_axi_arvalid  =  {1{abus_sel[8]}} & master_axi_arvalid ;
    s9_axi_arvalid  =  {1{abus_sel[9]}} & master_axi_arvalid ;
    s10_axi_arvalid = {1{abus_sel[10]}} & master_axi_arvalid ;
    s11_axi_arvalid = {1{abus_sel[11]}} & master_axi_arvalid ;
    s12_axi_arvalid = {1{abus_sel[12]}} & master_axi_arvalid ;
    s13_axi_arvalid = {1{abus_sel[13]}} & master_axi_arvalid ;
    s14_axi_arvalid = {1{abus_sel[14]}} & master_axi_arvalid ;
    s15_axi_arvalid = {1{abus_sel[15]}} & master_axi_arvalid ;
end

assign master_axi_arready = abus_sel[0] & s0_axi_arready
    | abus_sel[1]  & s1_axi_arready
    | abus_sel[2]  & s2_axi_arready
    | abus_sel[3]  & s3_axi_arready
    | abus_sel[4]  & s4_axi_arready
    | abus_sel[5]  & s5_axi_arready
    | abus_sel[6]  & s6_axi_arready
    | abus_sel[7]  & s7_axi_arready
    | abus_sel[8]  & s8_axi_arready
    | abus_sel[9]  & s9_axi_arready
    | abus_sel[10] & s10_axi_arready
    | abus_sel[11] & s11_axi_arready
    | abus_sel[12] & s12_axi_arready
    | abus_sel[13] & s13_axi_arready
    | abus_sel[14] & s14_axi_arready
    | abus_sel[15] & s15_axi_arready;



always @(posedge clk) begin
    if(master_axi_arvalid & master_axi_arready) begin
        rbus_sel <= abus_sel;
        rbus_mux <= abus_mux;
    end
    else begin end
end

always @(*) begin
    s0_axi_rready  = {1{rbus_sel[ 0]}} & master_axi_rready ;
    s1_axi_rready  = {1{rbus_sel[ 1]}} & master_axi_rready ;
    s2_axi_rready  = {1{rbus_sel[ 2]}} & master_axi_rready ;
    s3_axi_rready  = {1{rbus_sel[ 3]}} & master_axi_rready ;
    s4_axi_rready  = {1{rbus_sel[ 4]}} & master_axi_rready ;
    s5_axi_rready  = {1{rbus_sel[ 5]}} & master_axi_rready ;
    s6_axi_rready  = {1{rbus_sel[ 6]}} & master_axi_rready ;
    s7_axi_rready  = {1{rbus_sel[ 7]}} & master_axi_rready ;
    s8_axi_rready  = {1{rbus_sel[ 8]}} & master_axi_rready ;
    s9_axi_rready  = {1{rbus_sel[ 9]}} & master_axi_rready ;
    s10_axi_rready = {1{rbus_sel[10]}} & master_axi_rready ;
    s11_axi_rready = {1{rbus_sel[11]}} & master_axi_rready ;
    s12_axi_rready = {1{rbus_sel[12]}} & master_axi_rready ;
    s13_axi_rready = {1{rbus_sel[13]}} & master_axi_rready ;
    s14_axi_rready = {1{rbus_sel[14]}} & master_axi_rready ;
    s15_axi_rready = {1{rbus_sel[15]}} & master_axi_rready ;
end

always @(*) begin
    case (rbus_mux)
         0: master_axi_rdata = s0_axi_rdata;
         1: master_axi_rdata = s1_axi_rdata;
         2: master_axi_rdata = s2_axi_rdata;
         3: master_axi_rdata = s3_axi_rdata;
         4: master_axi_rdata = s4_axi_rdata;
         5: master_axi_rdata = s5_axi_rdata;
         6: master_axi_rdata = s6_axi_rdata;
         7: master_axi_rdata = s7_axi_rdata;
         8: master_axi_rdata = s8_axi_rdata;
         9: master_axi_rdata = s9_axi_rdata;
        10: master_axi_rdata = s10_axi_rdata;
        11: master_axi_rdata = s11_axi_rdata;
        12: master_axi_rdata = s12_axi_rdata;
        13: master_axi_rdata = s13_axi_rdata;
        14: master_axi_rdata = s14_axi_rdata;
        15: master_axi_rdata = s15_axi_rdata;
    endcase
end

assign master_axi_rvalid = rbus_sel[0] & s0_axi_rvalid
    | rbus_sel[ 1] & s1_axi_rvalid
    | rbus_sel[ 2] & s2_axi_rvalid
    | rbus_sel[ 3] & s3_axi_rvalid
    | rbus_sel[ 4] & s4_axi_rvalid
    | rbus_sel[ 5] & s5_axi_rvalid
    | rbus_sel[ 6] & s6_axi_rvalid
    | rbus_sel[ 7] & s7_axi_rvalid
    | rbus_sel[ 8] & s8_axi_rvalid
    | rbus_sel[ 9] & s9_axi_rvalid
    | rbus_sel[10] & s10_axi_rvalid
    | rbus_sel[11] & s11_axi_rvalid
    | rbus_sel[12] & s12_axi_rvalid
    | rbus_sel[13] & s13_axi_rvalid
    | rbus_sel[14] & s14_axi_rvalid
    | rbus_sel[15] & s15_axi_rvalid;



wire valid = 1'b1;
always @(*) begin
    m0_axi_bresp  = 2'b00;
    m0_axi_bvalid = valid;
    m0_axi_rresp  = 2'b00;
    m1_axi_bresp  = 2'b00;
    m1_axi_bvalid = valid;
    m1_axi_rresp  = 2'b00;
end
endmodule
module axi4lite_2mt16s (
	input clk,
	input rst_n,


    input wire [`MemAddrBus]    m0_axi_awaddr ,
    input wire [2:0]            m0_axi_awprot ,
    input wire                  m0_axi_awvalid,
    output reg                  m0_axi_awready,

    input wire [`MemBus]        m0_axi_wdata  ,
    input wire [3:0]            m0_axi_wstrb  ,
    input wire                  m0_axi_wvalid ,
    output reg                  m0_axi_wready ,

    output reg [1:0]            m0_axi_bresp  ,
    output reg                  m0_axi_bvalid ,
    input wire                  m0_axi_bready ,

    input wire [`MemAddrBus]    m0_axi_araddr ,
    input wire [2:0]            m0_axi_arprot ,
    input wire                  m0_axi_arvalid,
    output reg                  m0_axi_arready,

    output reg [`MemBus]        m0_axi_rdata  ,
    output reg [1:0]            m0_axi_rresp  ,
    output reg                  m0_axi_rvalid ,
    input wire                  m0_axi_rready ,


    input wire [`MemAddrBus]    m1_axi_awaddr ,
    input wire [2:0]            m1_axi_awprot ,
    input wire                  m1_axi_awvalid,
    output reg                  m1_axi_awready,

    input wire [`MemBus]        m1_axi_wdata  ,
    input wire [3:0]            m1_axi_wstrb  ,
    input wire                  m1_axi_wvalid ,
    output reg                  m1_axi_wready ,

    output reg [1:0]            m1_axi_bresp  ,
    output reg                  m1_axi_bvalid ,
    input wire                  m1_axi_bready ,

    input wire [`MemAddrBus]    m1_axi_araddr ,
    input wire [2:0]            m1_axi_arprot ,
    input wire                  m1_axi_arvalid,
    output reg                  m1_axi_arready,

    output reg [`MemBus]        m1_axi_rdata  ,
    output reg [1:0]            m1_axi_rresp  ,
    output reg                  m1_axi_rvalid ,
    input wire                  m1_axi_rready ,



    output reg [`MemAddrBus]    s0_axi_awaddr ,
    output reg                  s0_axi_awvalid,
    input wire                  s0_axi_awready,

    output reg [`MemBus]        s0_axi_wdata  ,
    output reg [3:0]            s0_axi_wstrb  ,
    output reg                  s0_axi_wvalid ,
    input wire                  s0_axi_wready ,

    output reg [`MemAddrBus]    s0_axi_araddr ,
    output reg                  s0_axi_arvalid,
    input wire                  s0_axi_arready,

    input wire [`MemBus]        s0_axi_rdata  ,
    input wire                  s0_axi_rvalid ,
    output reg                  s0_axi_rready ,


    output reg [`MemAddrBus]    s1_axi_awaddr ,
    output reg                  s1_axi_awvalid,
    input wire                  s1_axi_awready,

    output reg [`MemBus]        s1_axi_wdata  ,
    output reg [3:0]            s1_axi_wstrb  ,
    output reg                  s1_axi_wvalid ,
    input wire                  s1_axi_wready ,

    output reg [`MemAddrBus]    s1_axi_araddr ,
    output reg                  s1_axi_arvalid,
    input wire                  s1_axi_arready,

    input wire [`MemBus]        s1_axi_rdata  ,
    input wire                  s1_axi_rvalid ,
    output reg                  s1_axi_rready ,


    output reg [`MemAddrBus]    s2_axi_awaddr ,
    output reg                  s2_axi_awvalid,
    input wire                  s2_axi_awready,

    output reg [`MemBus]        s2_axi_wdata  ,
    output reg [3:0]            s2_axi_wstrb  ,
    output reg                  s2_axi_wvalid ,
    input wire                  s2_axi_wready ,

    output reg [`MemAddrBus]    s2_axi_araddr ,
    output reg                  s2_axi_arvalid,
    input wire                  s2_axi_arready,

    input wire [`MemBus]        s2_axi_rdata  ,
    input wire                  s2_axi_rvalid ,
    output reg                  s2_axi_rready ,


    output reg [`MemAddrBus]    s3_axi_awaddr ,
    output reg                  s3_axi_awvalid,
    input wire                  s3_axi_awready,

    output reg [`MemBus]        s3_axi_wdata  ,
    output reg [3:0]            s3_axi_wstrb  ,
    output reg                  s3_axi_wvalid ,
    input wire                  s3_axi_wready ,

    output reg [`MemAddrBus]    s3_axi_araddr ,
    output reg                  s3_axi_arvalid,
    input wire                  s3_axi_arready,

    input wire [`MemBus]        s3_axi_rdata  ,
    input wire                  s3_axi_rvalid ,
    output reg                  s3_axi_rready ,


    output reg [`MemAddrBus]    s4_axi_awaddr ,
    output reg                  s4_axi_awvalid,
    input wire                  s4_axi_awready,

    output reg [`MemBus]        s4_axi_wdata  ,
    output reg [3:0]            s4_axi_wstrb  ,
    output reg                  s4_axi_wvalid ,
    input wire                  s4_axi_wready ,

    output reg [`MemAddrBus]    s4_axi_araddr ,
    output reg                  s4_axi_arvalid,
    input wire                  s4_axi_arready,

    input wire [`MemBus]        s4_axi_rdata  ,
    input wire                  s4_axi_rvalid ,
    output reg                  s4_axi_rready ,


    output reg [`MemAddrBus]    s5_axi_awaddr ,
    output reg                  s5_axi_awvalid,
    input wire                  s5_axi_awready,

    output reg [`MemBus]        s5_axi_wdata  ,
    output reg [3:0]            s5_axi_wstrb  ,
    output reg                  s5_axi_wvalid ,
    input wire                  s5_axi_wready ,

    output reg [`MemAddrBus]    s5_axi_araddr ,
    output reg                  s5_axi_arvalid,
    input wire                  s5_axi_arready,

    input wire [`MemBus]        s5_axi_rdata  ,
    input wire                  s5_axi_rvalid ,
    output reg                  s5_axi_rready ,


    output reg [`MemAddrBus]    s6_axi_awaddr ,
    output reg                  s6_axi_awvalid,
    input wire                  s6_axi_awready,

    output reg [`MemBus]        s6_axi_wdata  ,
    output reg [3:0]            s6_axi_wstrb  ,
    output reg                  s6_axi_wvalid ,
    input wire                  s6_axi_wready ,

    output reg [`MemAddrBus]    s6_axi_araddr ,
    output reg                  s6_axi_arvalid,
    input wire                  s6_axi_arready,

    input wire [`MemBus]        s6_axi_rdata  ,
    input wire                  s6_axi_rvalid ,
    output reg                  s6_axi_rready ,


    output reg [`MemAddrBus]    s7_axi_awaddr ,
    output reg                  s7_axi_awvalid,
    input wire                  s7_axi_awready,

    output reg [`MemBus]        s7_axi_wdata  ,
    output reg [3:0]            s7_axi_wstrb  ,
    output reg                  s7_axi_wvalid ,
    input wire                  s7_axi_wready ,

    output reg [`MemAddrBus]    s7_axi_araddr ,
    output reg                  s7_axi_arvalid,
    input wire                  s7_axi_arready,

    input wire [`MemBus]        s7_axi_rdata  ,
    input wire                  s7_axi_rvalid ,
    output reg                  s7_axi_rready ,


    output reg [`MemAddrBus]    s8_axi_awaddr ,
    output reg                  s8_axi_awvalid,
    input wire                  s8_axi_awready,

    output reg [`MemBus]        s8_axi_wdata  ,
    output reg [3:0]            s8_axi_wstrb  ,
    output reg                  s8_axi_wvalid ,
    input wire                  s8_axi_wready ,

    output reg [`MemAddrBus]    s8_axi_araddr ,
    output reg                  s8_axi_arvalid,
    input wire                  s8_axi_arready,

    input wire [`MemBus]        s8_axi_rdata  ,
    input wire                  s8_axi_rvalid ,
    output reg                  s8_axi_rready ,


    output reg [`MemAddrBus]    s9_axi_awaddr ,
    output reg                  s9_axi_awvalid,
    input wire                  s9_axi_awready,

    output reg [`MemBus]        s9_axi_wdata  ,
    output reg [3:0]            s9_axi_wstrb  ,
    output reg                  s9_axi_wvalid ,
    input wire                  s9_axi_wready ,

    output reg [`MemAddrBus]    s9_axi_araddr ,
    output reg                  s9_axi_arvalid,
    input wire                  s9_axi_arready,

    input wire [`MemBus]        s9_axi_rdata  ,
    input wire                  s9_axi_rvalid ,
    output reg                  s9_axi_rready ,


    output reg [`MemAddrBus]    s10_axi_awaddr ,
    output reg                  s10_axi_awvalid,
    input wire                  s10_axi_awready,

    output reg [`MemBus]        s10_axi_wdata  ,
    output reg [3:0]            s10_axi_wstrb  ,
    output reg                  s10_axi_wvalid ,
    input wire                  s10_axi_wready ,

    output reg [`MemAddrBus]    s10_axi_araddr ,
    output reg                  s10_axi_arvalid,
    input wire                  s10_axi_arready,

    input wire [`MemBus]        s10_axi_rdata  ,
    input wire                  s10_axi_rvalid ,
    output reg                  s10_axi_rready ,


    output reg [`MemAddrBus]    s11_axi_awaddr ,
    output reg                  s11_axi_awvalid,
    input wire                  s11_axi_awready,

    output reg [`MemBus]        s11_axi_wdata  ,
    output reg [3:0]            s11_axi_wstrb  ,
    output reg                  s11_axi_wvalid ,
    input wire                  s11_axi_wready ,

    output reg [`MemAddrBus]    s11_axi_araddr ,
    output reg                  s11_axi_arvalid,
    input wire                  s11_axi_arready,

    input wire [`MemBus]        s11_axi_rdata  ,
    input wire                  s11_axi_rvalid ,
    output reg                  s11_axi_rready ,


    output reg [`MemAddrBus]    s12_axi_awaddr ,
    output reg                  s12_axi_awvalid,
    input wire                  s12_axi_awready,

    output reg [`MemBus]        s12_axi_wdata  ,
    output reg [3:0]            s12_axi_wstrb  ,
    output reg                  s12_axi_wvalid ,
    input wire                  s12_axi_wready ,

    output reg [`MemAddrBus]    s12_axi_araddr ,
    output reg                  s12_axi_arvalid,
    input wire                  s12_axi_arready,

    input wire [`MemBus]        s12_axi_rdata  ,
    input wire                  s12_axi_rvalid ,
    output reg                  s12_axi_rready ,


    output reg [`MemAddrBus]    s13_axi_awaddr ,
    output reg                  s13_axi_awvalid,
    input wire                  s13_axi_awready,

    output reg [`MemBus]        s13_axi_wdata  ,
    output reg [3:0]            s13_axi_wstrb  ,
    output reg                  s13_axi_wvalid ,
    input wire                  s13_axi_wready ,

    output reg [`MemAddrBus]    s13_axi_araddr ,
    output reg                  s13_axi_arvalid,
    input wire                  s13_axi_arready,

    input wire [`MemBus]        s13_axi_rdata  ,
    input wire                  s13_axi_rvalid ,
    output reg                  s13_axi_rready ,


    output reg [`MemAddrBus]    s14_axi_awaddr ,
    output reg                  s14_axi_awvalid,
    input wire                  s14_axi_awready,

    output reg [`MemBus]        s14_axi_wdata  ,
    output reg [3:0]            s14_axi_wstrb  ,
    output reg                  s14_axi_wvalid ,
    input wire                  s14_axi_wready ,

    output reg [`MemAddrBus]    s14_axi_araddr ,
    output reg                  s14_axi_arvalid,
    input wire                  s14_axi_arready,

    input wire [`MemBus]        s14_axi_rdata  ,
    input wire                  s14_axi_rvalid ,
    output reg                  s14_axi_rready ,


    output reg [`MemAddrBus]    s15_axi_awaddr ,
    output reg                  s15_axi_awvalid,
    input wire                  s15_axi_awready,

    output reg [`MemBus]        s15_axi_wdata  ,
    output reg [3:0]            s15_axi_wstrb  ,
    output reg                  s15_axi_wvalid ,
    input wire                  s15_axi_wready ,

    output reg [`MemAddrBus]    s15_axi_araddr ,
    output reg                  s15_axi_arvalid,
    input wire                  s15_axi_arready,

    input wire [`MemBus]        s15_axi_rdata  ,
    input wire                  s15_axi_rvalid ,
    output reg                  s15_axi_rready

);



wire m0_wbus_en = m0_axi_awvalid & m0_axi_wvalid;
wire m1_wbus_en = m1_axi_awvalid & m1_axi_wvalid & ~m0_wbus_en;

wire m0_abus_en = m0_axi_arvalid;
wire m1_abus_en = m1_axi_arvalid & ~m0_abus_en;


reg m0_rbus_en;
reg m1_rbus_en;


wire [`MemAddrBus]    master_axi_awaddr ;
wire                  master_axi_awvalid;
wire                  master_axi_awready;
wire [`MemBus]        master_axi_wdata  ;
wire [3:0]            master_axi_wstrb  ;
wire                  master_axi_wvalid ;
wire                  master_axi_wready ;
wire [`MemAddrBus]    master_axi_araddr ;
wire                  master_axi_arvalid;
wire                  master_axi_arready;
reg  [`MemBus]        master_axi_rdata  ;
wire                  master_axi_rvalid ;
wire                  master_axi_rready ;

assign master_axi_awaddr  = m0_wbus_en ? m0_axi_awaddr : m1_axi_awaddr;
assign master_axi_awvalid = ({1{m0_wbus_en}} & m0_axi_awvalid)
                            | ({1{m1_wbus_en}} & m1_axi_awvalid);
assign master_axi_wdata   = m0_wbus_en ? m0_axi_wdata : m1_axi_wdata;
assign master_axi_wstrb   = m0_wbus_en ? m0_axi_wstrb : m1_axi_wstrb;
assign master_axi_wvalid  = ({1{m0_wbus_en}} & m0_axi_wvalid)
                            | ({1{m1_wbus_en}} & m1_axi_wvalid);
assign master_axi_araddr  = m0_abus_en ? m0_axi_araddr : m1_axi_araddr;
assign master_axi_arvalid = ({1{m0_abus_en}} & m0_axi_arvalid)
                            | ({1{m1_abus_en}} & m1_axi_arvalid);
assign master_axi_rready  = ({1{m0_rbus_en}} & m0_axi_rready)
                            | ({1{m1_rbus_en}} & m1_axi_rready);

always @(*) begin
    m0_axi_awready = {1 {m0_wbus_en}} & master_axi_awready;
    m0_axi_wready  = {1 {m0_wbus_en}} & master_axi_wready ;
    m0_axi_arready = {1 {m0_abus_en}} & master_axi_arready;
    m0_axi_rdata   = master_axi_rdata  ;
    m0_axi_rvalid  = {1 {m0_rbus_en}} & master_axi_rvalid ;
    m1_axi_awready = {1 {m1_wbus_en}} & master_axi_awready;
    m1_axi_wready  = {1 {m1_wbus_en}} & master_axi_wready ;
    m1_axi_arready = {1 {m1_abus_en}} & master_axi_arready;
    m1_axi_rdata   = master_axi_rdata  ;
    m1_axi_rvalid  = {1 {m1_rbus_en}} & master_axi_rvalid ;
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        m0_rbus_en <= 0;
        m1_rbus_en <= 0;
    end
    else begin
        if (m0_axi_arvalid & m0_axi_arready)
            m0_rbus_en <=1'b1;
        else if (m0_rbus_en & m0_axi_rvalid & m0_axi_rready)
            m0_rbus_en <=1'b0;
        else
            m0_rbus_en <= m0_rbus_en;
        if (m1_axi_arvalid & m1_axi_arready)
            m1_rbus_en <=1'b1;
        else if (m1_rbus_en & m1_axi_rvalid & m1_axi_rready)
            m1_rbus_en <=1'b0;
        else
            m1_rbus_en <= m1_rbus_en;
    end
end



wire [3:0] wbus_mux;
wire [15:0] wbus_sel;
wire [3:0] abus_mux;
wire [15:0] abus_sel;
reg [3:0] rbus_mux;
reg [15:0] rbus_sel;


assign wbus_mux = master_axi_awaddr [31:28];
assign wbus_sel[0 ] = wbus_mux == 4'd0  ? 1'b1 : 1'b0;
assign wbus_sel[1 ] = wbus_mux == 4'd1  ? 1'b1 : 1'b0;
assign wbus_sel[2 ] = wbus_mux == 4'd2  ? 1'b1 : 1'b0;
assign wbus_sel[3 ] = wbus_mux == 4'd3  ? 1'b1 : 1'b0;
assign wbus_sel[4 ] = wbus_mux == 4'd4  ? 1'b1 : 1'b0;
assign wbus_sel[5 ] = wbus_mux == 4'd5  ? 1'b1 : 1'b0;
assign wbus_sel[6 ] = wbus_mux == 4'd6  ? 1'b1 : 1'b0;
assign wbus_sel[7 ] = wbus_mux == 4'd7  ? 1'b1 : 1'b0;
assign wbus_sel[8 ] = wbus_mux == 4'd8  ? 1'b1 : 1'b0;
assign wbus_sel[9 ] = wbus_mux == 4'd9  ? 1'b1 : 1'b0;
assign wbus_sel[10] = wbus_mux == 4'd10 ? 1'b1 : 1'b0;
assign wbus_sel[11] = wbus_mux == 4'd11 ? 1'b1 : 1'b0;
assign wbus_sel[12] = wbus_mux == 4'd12 ? 1'b1 : 1'b0;
assign wbus_sel[13] = wbus_mux == 4'd13 ? 1'b1 : 1'b0;
assign wbus_sel[14] = wbus_mux == 4'd14 ? 1'b1 : 1'b0;
assign wbus_sel[15] = wbus_mux == 4'd15 ? 1'b1 : 1'b0;

always @(*) begin
    s0_axi_awaddr  = wbus_mux == 4'd0  ? master_axi_awaddr : 32'b0;
    s1_axi_awaddr  = wbus_mux == 4'd1  ? master_axi_awaddr : 32'b0;
    s2_axi_awaddr  = wbus_mux == 4'd2  ? master_axi_awaddr : 32'b0;
    s3_axi_awaddr  = wbus_mux == 4'd3  ? master_axi_awaddr : 32'b0;
    s4_axi_awaddr  = wbus_mux == 4'd4  ? master_axi_awaddr : 32'b0;
    s5_axi_awaddr  = wbus_mux == 4'd5  ? master_axi_awaddr : 32'b0;
    s6_axi_awaddr  = wbus_mux == 4'd6  ? master_axi_awaddr : 32'b0;
    s7_axi_awaddr  = wbus_mux == 4'd7  ? master_axi_awaddr : 32'b0;
    s8_axi_awaddr  = wbus_mux == 4'd8  ? master_axi_awaddr : 32'b0;
    s9_axi_awaddr  = wbus_mux == 4'd9  ? master_axi_awaddr : 32'b0;
    s10_axi_awaddr = wbus_mux == 4'd10 ? master_axi_awaddr : 32'b0;
    s11_axi_awaddr = wbus_mux == 4'd11 ? master_axi_awaddr : 32'b0;
    s12_axi_awaddr = wbus_mux == 4'd12 ? master_axi_awaddr : 32'b0;
    s13_axi_awaddr = wbus_mux == 4'd13 ? master_axi_awaddr : 32'b0;
    s14_axi_awaddr = wbus_mux == 4'd14 ? master_axi_awaddr : 32'b0;
    s15_axi_awaddr = wbus_mux == 4'd15 ? master_axi_awaddr : 32'b0;

    s0_axi_awvalid  =  {1{wbus_sel[0]}} & master_axi_awvalid;
    s1_axi_awvalid  =  {1{wbus_sel[1]}} & master_axi_awvalid;
    s2_axi_awvalid  =  {1{wbus_sel[2]}} & master_axi_awvalid;
    s3_axi_awvalid  =  {1{wbus_sel[3]}} & master_axi_awvalid;
    s4_axi_awvalid  =  {1{wbus_sel[4]}} & master_axi_awvalid;
    s5_axi_awvalid  =  {1{wbus_sel[5]}} & master_axi_awvalid;
    s6_axi_awvalid  =  {1{wbus_sel[6]}} & master_axi_awvalid;
    s7_axi_awvalid  =  {1{wbus_sel[7]}} & master_axi_awvalid;
    s8_axi_awvalid  =  {1{wbus_sel[8]}} & master_axi_awvalid;
    s9_axi_awvalid  =  {1{wbus_sel[9]}} & master_axi_awvalid;
    s10_axi_awvalid = {1{wbus_sel[10]}} & master_axi_awvalid;
    s11_axi_awvalid = {1{wbus_sel[11]}} & master_axi_awvalid;
    s12_axi_awvalid = {1{wbus_sel[12]}} & master_axi_awvalid;
    s13_axi_awvalid = {1{wbus_sel[13]}} & master_axi_awvalid;
    s14_axi_awvalid = {1{wbus_sel[14]}} & master_axi_awvalid;
    s15_axi_awvalid = {1{wbus_sel[15]}} & master_axi_awvalid;


    s0_axi_wdata   = master_axi_wdata  ;
    s1_axi_wdata   = master_axi_wdata  ;
    s2_axi_wdata   = master_axi_wdata  ;
    s3_axi_wdata   = master_axi_wdata  ;
    s4_axi_wdata   = master_axi_wdata  ;
    s5_axi_wdata   = master_axi_wdata  ;
    s6_axi_wdata   = master_axi_wdata  ;
    s7_axi_wdata   = master_axi_wdata  ;
    s8_axi_wdata   = master_axi_wdata  ;
    s9_axi_wdata   = master_axi_wdata  ;
    s10_axi_wdata  = master_axi_wdata  ;
    s11_axi_wdata  = master_axi_wdata  ;
    s12_axi_wdata  = master_axi_wdata  ;
    s13_axi_wdata  = master_axi_wdata  ;
    s14_axi_wdata  = master_axi_wdata  ;
    s15_axi_wdata  = master_axi_wdata  ;

    s0_axi_wstrb  = master_axi_wstrb ;
    s1_axi_wstrb  = master_axi_wstrb ;
    s2_axi_wstrb  = master_axi_wstrb ;
    s3_axi_wstrb  = master_axi_wstrb ;
    s4_axi_wstrb  = master_axi_wstrb ;
    s5_axi_wstrb  = master_axi_wstrb ;
    s6_axi_wstrb  = master_axi_wstrb ;
    s7_axi_wstrb  = master_axi_wstrb ;
    s8_axi_wstrb  = master_axi_wstrb ;
    s9_axi_wstrb  = master_axi_wstrb ;
    s10_axi_wstrb = master_axi_wstrb ;
    s11_axi_wstrb = master_axi_wstrb ;
    s12_axi_wstrb = master_axi_wstrb ;
    s13_axi_wstrb = master_axi_wstrb ;
    s14_axi_wstrb = master_axi_wstrb ;
    s15_axi_wstrb = master_axi_wstrb ;

    s0_axi_wvalid =  {1{wbus_sel[0]}} & master_axi_wvalid ;
    s1_axi_wvalid =  {1{wbus_sel[1]}} & master_axi_wvalid ;
    s2_axi_wvalid =  {1{wbus_sel[2]}} & master_axi_wvalid ;
    s3_axi_wvalid =  {1{wbus_sel[3]}} & master_axi_wvalid ;
    s4_axi_wvalid =  {1{wbus_sel[4]}} & master_axi_wvalid ;
    s5_axi_wvalid =  {1{wbus_sel[5]}} & master_axi_wvalid ;
    s6_axi_wvalid =  {1{wbus_sel[6]}} & master_axi_wvalid ;
    s7_axi_wvalid =  {1{wbus_sel[7]}} & master_axi_wvalid ;
    s8_axi_wvalid =  {1{wbus_sel[8]}} & master_axi_wvalid ;
    s9_axi_wvalid =  {1{wbus_sel[9]}} & master_axi_wvalid ;
    s10_axi_wvalid = {1{wbus_sel[10]}} & master_axi_wvalid ;
    s11_axi_wvalid = {1{wbus_sel[11]}} & master_axi_wvalid ;
    s12_axi_wvalid = {1{wbus_sel[12]}} & master_axi_wvalid ;
    s13_axi_wvalid = {1{wbus_sel[13]}} & master_axi_wvalid ;
    s14_axi_wvalid = {1{wbus_sel[14]}} & master_axi_wvalid ;
    s15_axi_wvalid = {1{wbus_sel[15]}} & master_axi_wvalid ;
end

assign master_axi_awready = wbus_sel[0] & s0_axi_awready
        | wbus_sel[1]  & s1_axi_awready
        | wbus_sel[2]  & s2_axi_awready
        | wbus_sel[3]  & s3_axi_awready
        | wbus_sel[4]  & s4_axi_awready
        | wbus_sel[5]  & s5_axi_awready
        | wbus_sel[6]  & s6_axi_awready
        | wbus_sel[7]  & s7_axi_awready
        | wbus_sel[8]  & s8_axi_awready
        | wbus_sel[9]  & s9_axi_awready
        | wbus_sel[10] & s10_axi_awready
        | wbus_sel[11] & s11_axi_awready
        | wbus_sel[12] & s12_axi_awready
        | wbus_sel[13] & s13_axi_awready
        | wbus_sel[14] & s14_axi_awready
        | wbus_sel[15] & s15_axi_awready;
assign master_axi_wready  = wbus_sel[0] & s0_axi_wready
        | wbus_sel[1]  & s1_axi_wready
        | wbus_sel[2]  & s2_axi_wready
        | wbus_sel[3]  & s3_axi_wready
        | wbus_sel[4]  & s4_axi_wready
        | wbus_sel[5]  & s5_axi_wready
        | wbus_sel[6]  & s6_axi_wready
        | wbus_sel[7]  & s7_axi_wready
        | wbus_sel[8]  & s8_axi_wready
        | wbus_sel[9]  & s9_axi_wready
        | wbus_sel[10] & s10_axi_wready
        | wbus_sel[11] & s11_axi_wready
        | wbus_sel[12] & s12_axi_wready
        | wbus_sel[13] & s13_axi_wready
        | wbus_sel[14] & s14_axi_wready
        | wbus_sel[15] & s15_axi_wready;


assign abus_mux = master_axi_araddr [31:28];
assign abus_sel[0 ] = abus_mux == 4'd0  ? 1'b1 : 1'b0;
assign abus_sel[1 ] = abus_mux == 4'd1  ? 1'b1 : 1'b0;
assign abus_sel[2 ] = abus_mux == 4'd2  ? 1'b1 : 1'b0;
assign abus_sel[3 ] = abus_mux == 4'd3  ? 1'b1 : 1'b0;
assign abus_sel[4 ] = abus_mux == 4'd4  ? 1'b1 : 1'b0;
assign abus_sel[5 ] = abus_mux == 4'd5  ? 1'b1 : 1'b0;
assign abus_sel[6 ] = abus_mux == 4'd6  ? 1'b1 : 1'b0;
assign abus_sel[7 ] = abus_mux == 4'd7  ? 1'b1 : 1'b0;
assign abus_sel[8 ] = abus_mux == 4'd8  ? 1'b1 : 1'b0;
assign abus_sel[9 ] = abus_mux == 4'd9  ? 1'b1 : 1'b0;
assign abus_sel[10] = abus_mux == 4'd10 ? 1'b1 : 1'b0;
assign abus_sel[11] = abus_mux == 4'd11 ? 1'b1 : 1'b0;
assign abus_sel[12] = abus_mux == 4'd12 ? 1'b1 : 1'b0;
assign abus_sel[13] = abus_mux == 4'd13 ? 1'b1 : 1'b0;
assign abus_sel[14] = abus_mux == 4'd14 ? 1'b1 : 1'b0;
assign abus_sel[15] = abus_mux == 4'd15 ? 1'b1 : 1'b0;

always @(*) begin
    s0_axi_araddr  = abus_mux == 4'd0  ? master_axi_araddr : 32'b0;
    s1_axi_araddr  = abus_mux == 4'd1  ? master_axi_araddr : 32'b0;
    s2_axi_araddr  = abus_mux == 4'd2  ? master_axi_araddr : 32'b0;
    s3_axi_araddr  = abus_mux == 4'd3  ? master_axi_araddr : 32'b0;
    s4_axi_araddr  = abus_mux == 4'd4  ? master_axi_araddr : 32'b0;
    s5_axi_araddr  = abus_mux == 4'd5  ? master_axi_araddr : 32'b0;
    s6_axi_araddr  = abus_mux == 4'd6  ? master_axi_araddr : 32'b0;
    s7_axi_araddr  = abus_mux == 4'd7  ? master_axi_araddr : 32'b0;
    s8_axi_araddr  = abus_mux == 4'd8  ? master_axi_araddr : 32'b0;
    s9_axi_araddr  = abus_mux == 4'd9  ? master_axi_araddr : 32'b0;
    s10_axi_araddr = abus_mux == 4'd10 ? master_axi_araddr : 32'b0;
    s11_axi_araddr = abus_mux == 4'd11 ? master_axi_araddr : 32'b0;
    s12_axi_araddr = abus_mux == 4'd12 ? master_axi_araddr : 32'b0;
    s13_axi_araddr = abus_mux == 4'd13 ? master_axi_araddr : 32'b0;
    s14_axi_araddr = abus_mux == 4'd14 ? master_axi_araddr : 32'b0;
    s15_axi_araddr = abus_mux == 4'd15 ? master_axi_araddr : 32'b0;

    s0_axi_arvalid  =  {1{abus_sel[0]}} & master_axi_arvalid ;
    s1_axi_arvalid  =  {1{abus_sel[1]}} & master_axi_arvalid ;
    s2_axi_arvalid  =  {1{abus_sel[2]}} & master_axi_arvalid ;
    s3_axi_arvalid  =  {1{abus_sel[3]}} & master_axi_arvalid ;
    s4_axi_arvalid  =  {1{abus_sel[4]}} & master_axi_arvalid ;
    s5_axi_arvalid  =  {1{abus_sel[5]}} & master_axi_arvalid ;
    s6_axi_arvalid  =  {1{abus_sel[6]}} & master_axi_arvalid ;
    s7_axi_arvalid  =  {1{abus_sel[7]}} & master_axi_arvalid ;
    s8_axi_arvalid  =  {1{abus_sel[8]}} & master_axi_arvalid ;
    s9_axi_arvalid  =  {1{abus_sel[9]}} & master_axi_arvalid ;
    s10_axi_arvalid = {1{abus_sel[10]}} & master_axi_arvalid ;
    s11_axi_arvalid = {1{abus_sel[11]}} & master_axi_arvalid ;
    s12_axi_arvalid = {1{abus_sel[12]}} & master_axi_arvalid ;
    s13_axi_arvalid = {1{abus_sel[13]}} & master_axi_arvalid ;
    s14_axi_arvalid = {1{abus_sel[14]}} & master_axi_arvalid ;
    s15_axi_arvalid = {1{abus_sel[15]}} & master_axi_arvalid ;
end

assign master_axi_arready = abus_sel[0] & s0_axi_arready
    | abus_sel[1]  & s1_axi_arready
    | abus_sel[2]  & s2_axi_arready
    | abus_sel[3]  & s3_axi_arready
    | abus_sel[4]  & s4_axi_arready
    | abus_sel[5]  & s5_axi_arready
    | abus_sel[6]  & s6_axi_arready
    | abus_sel[7]  & s7_axi_arready
    | abus_sel[8]  & s8_axi_arready
    | abus_sel[9]  & s9_axi_arready
    | abus_sel[10] & s10_axi_arready
    | abus_sel[11] & s11_axi_arready
    | abus_sel[12] & s12_axi_arready
    | abus_sel[13] & s13_axi_arready
    | abus_sel[14] & s14_axi_arready
    | abus_sel[15] & s15_axi_arready;



always @(posedge clk) begin
    if(master_axi_arvalid & master_axi_arready) begin
        rbus_sel <= abus_sel;
        rbus_mux <= abus_mux;
    end
    else begin end
end

always @(*) begin
    s0_axi_rready  = {1{rbus_sel[ 0]}} & master_axi_rready ;
    s1_axi_rready  = {1{rbus_sel[ 1]}} & master_axi_rready ;
    s2_axi_rready  = {1{rbus_sel[ 2]}} & master_axi_rready ;
    s3_axi_rready  = {1{rbus_sel[ 3]}} & master_axi_rready ;
    s4_axi_rready  = {1{rbus_sel[ 4]}} & master_axi_rready ;
    s5_axi_rready  = {1{rbus_sel[ 5]}} & master_axi_rready ;
    s6_axi_rready  = {1{rbus_sel[ 6]}} & master_axi_rready ;
    s7_axi_rready  = {1{rbus_sel[ 7]}} & master_axi_rready ;
    s8_axi_rready  = {1{rbus_sel[ 8]}} & master_axi_rready ;
    s9_axi_rready  = {1{rbus_sel[ 9]}} & master_axi_rready ;
    s10_axi_rready = {1{rbus_sel[10]}} & master_axi_rready ;
    s11_axi_rready = {1{rbus_sel[11]}} & master_axi_rready ;
    s12_axi_rready = {1{rbus_sel[12]}} & master_axi_rready ;
    s13_axi_rready = {1{rbus_sel[13]}} & master_axi_rready ;
    s14_axi_rready = {1{rbus_sel[14]}} & master_axi_rready ;
    s15_axi_rready = {1{rbus_sel[15]}} & master_axi_rready ;
end

always @(*) begin
    case (rbus_mux)
         0: master_axi_rdata = s0_axi_rdata;
         1: master_axi_rdata = s1_axi_rdata;
         2: master_axi_rdata = s2_axi_rdata;
         3: master_axi_rdata = s3_axi_rdata;
         4: master_axi_rdata = s4_axi_rdata;
         5: master_axi_rdata = s5_axi_rdata;
         6: master_axi_rdata = s6_axi_rdata;
         7: master_axi_rdata = s7_axi_rdata;
         8: master_axi_rdata = s8_axi_rdata;
         9: master_axi_rdata = s9_axi_rdata;
        10: master_axi_rdata = s10_axi_rdata;
        11: master_axi_rdata = s11_axi_rdata;
        12: master_axi_rdata = s12_axi_rdata;
        13: master_axi_rdata = s13_axi_rdata;
        14: master_axi_rdata = s14_axi_rdata;
        15: master_axi_rdata = s15_axi_rdata;
    endcase
end

assign master_axi_rvalid = rbus_sel[0] & s0_axi_rvalid
    | rbus_sel[ 1] & s1_axi_rvalid
    | rbus_sel[ 2] & s2_axi_rvalid
    | rbus_sel[ 3] & s3_axi_rvalid
    | rbus_sel[ 4] & s4_axi_rvalid
    | rbus_sel[ 5] & s5_axi_rvalid
    | rbus_sel[ 6] & s6_axi_rvalid
    | rbus_sel[ 7] & s7_axi_rvalid
    | rbus_sel[ 8] & s8_axi_rvalid
    | rbus_sel[ 9] & s9_axi_rvalid
    | rbus_sel[10] & s10_axi_rvalid
    | rbus_sel[11] & s11_axi_rvalid
    | rbus_sel[12] & s12_axi_rvalid
    | rbus_sel[13] & s13_axi_rvalid
    | rbus_sel[14] & s14_axi_rvalid
    | rbus_sel[15] & s15_axi_rvalid;



wire valid = 1'b1;
always @(*) begin
    m0_axi_bresp  = 2'b00;
    m0_axi_bvalid = valid;
    m0_axi_rresp  = 2'b00;
    m1_axi_bresp  = 2'b00;
    m1_axi_bvalid = valid;
    m1_axi_rresp  = 2'b00;
end
endmodule