data/full_repos/permissive/42149584/Lab2-Part2-Controller7SegmentDisplayKeypadScanner/DelayLoop.v
data/verilator_xmls/b884e16d-f282-4bfc-9e6d-be76fba5d8c3.xml
module DelayLoop(MR,Timeout,Clock) ;
parameter	Divider = 500000;
parameter 	NumberOfBits = 19;
input			MR, Clock;
output reg	Timeout;
reg 	[NumberOfBits-1:0]	count;
	
always @ (count)
	if(count==Divider) Timeout<=1;
	else Timeout<=0;
	
always @ (posedge Clock)
	if(MR==1)		begin count <= 0; end
	else if (count>=Divider)	count<=0;
		else count <= count+1'b1;
endmodule
module DelayLoop(MR,Timeout,Clock) ;

parameter	Divider = 500000;
parameter 	NumberOfBits = 19;
input			MR, Clock;
output reg	Timeout;
reg 	[NumberOfBits-1:0]	count;
	
always @ (count)
	if(count==Divider) Timeout<=1;
	else Timeout<=0;
	
always @ (posedge Clock)
	if(MR==1)		begin count <= 0; end
	else if (count>=Divider)	count<=0;
		else count <= count+1'b1;
endmodule