data/full_repos/permissive/432661124/HW/seg_map_512KB.v
1: b'%Error: data/full_repos/permissive/432661124/HW/seg_map_512KB.v:13: Unsupported: Replication to form \'logic[3:0]$[0:15]\' data type\n                                                                  : ... In instance seg_map_512KB\n reg [3:0]map[0:15] = {4\'h0, 4\'h1, 4\'h2, 4\'h3, 4\'h4, 4\'h5, 4\'h6, 4\'h7, 4\'h8, 4\'h9,\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/432661124/HW/seg_map_512KB.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                          : ... In instance seg_map_512KB\n reg [3:0]map[0:15] = {4\'h0, 4\'h1, 4\'h2, 4\'h3, 4\'h4, 4\'h5, 4\'h6, 4\'h7, 4\'h8, 4\'h9,\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module seg_map_512KB(
	 input CLK,
	 input [3:0]cpuaddr,
	 output [3:0]cpurdata,
	 input [3:0]cpuwdata,
	 input [4:0]memaddr,
	 output [3:0]memdata,
	 input WE,
	 output f_map_to_f
    );

	reg [3:0]map[0:15] = {4'h0, 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7, 4'h8, 4'h9,
								 4'ha, 4'hb,
								 4'hc, 4'hd, 4'he, 4'hf};
	assign memdata = map[memaddr[3:0]];
	assign cpurdata = map[cpuaddr];
	assign f_map_to_f = (map[15] == 4'hf);
	
	always @(posedge CLK) 
		if(WE) map[cpuaddr] <= cpuwdata;

endmodule
module seg_map_512KB(
	 input CLK,
	 input [3:0]cpuaddr,
	 output [3:0]cpurdata,
	 input [3:0]cpuwdata,
	 input [4:0]memaddr,
	 output [3:0]memdata,
	 input WE,
	 output f_map_to_f
    );


	reg [3:0]map[0:15] = {4'h0, 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7, 4'h8, 4'h9,
								 4'ha, 4'hb,
								 4'hc, 4'hd, 4'he, 4'hf};
	assign memdata = map[memaddr[3:0]];
	assign cpurdata = map[cpuaddr];
	assign f_map_to_f = (map[15] == 4'hf);
	
	always @(posedge CLK) 
		if(WE) map[cpuaddr] <= cpuwdata;

endmodule