data/full_repos/permissive/454430637/project_files/MUX_ACC.v
data/verilator_xmls/decdc329-f74e-4609-883f-22913b903a90.xml
module MUX_ACC(
in_1 , in_2 , out_M , sel_M );

input [`WIDTH_4-1:0] in_1 , in_2 ;
input sel_M ;
output [`WIDTH_4-1:0] out_M ;


assign out_M = sel_M ? in_2 :in_1 ;

endmodule
module MUX_ACC(
in_1 , in_2 , out_M , sel_M );


input [`WIDTH_4-1:0] in_1 , in_2 ;
input sel_M ;
output [`WIDTH_4-1:0] out_M ;


assign out_M = sel_M ? in_2 :in_1 ;

endmodule