data/full_repos/permissive/507506290/RTL_Files/TOP_DESIGN.v
1: b"%Error: data/full_repos/permissive/507506290/RTL_Files/TOP_DESIGN.v:68: Cannot find file containing module: 'instr_mem'\ninstr_mem PROGRAM_MEMORY(.pc_addr(pc_out), .o_instr(o_instr)); \n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/instr_mem\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/instr_mem.v\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/instr_mem.sv\n             instr_mem\n             instr_mem.v\n             instr_mem.sv\n             obj_dir/instr_mem\n             obj_dir/instr_mem.v\n             obj_dir/instr_mem.sv\n%Error: data/full_repos/permissive/507506290/RTL_Files/TOP_DESIGN.v:70: Cannot find file containing module: 'Control_UNIT'\nControl_UNIT CU(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507506290/RTL_Files/TOP_DESIGN.v:85: Cannot find file containing module: 'DATA_PATH'\nDATA_PATH DU(\n^~~~~~~~~\n%Error: data/full_repos/permissive/507506290/RTL_Files/TOP_DESIGN.v:103: Cannot find file containing module: 'DATA_MEM'\nDATA_MEM MEMORY(\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module TOP_DESIGN
(
 input i_clk , 
 input rst_n ,
 input enable ,
 output zero 
  );
wire [`INSTR_WIDTH-1:0] o_instr ;
wire [`ALU_CONTROL-1:0] o_alu_control   ;
wire [`OPCODE_WIDTH-1:0] i_OPCODE     ;
wire RegDst  ;
wire o_branch ;
wire MemReg   ;
wire MemWr ;
wire MemRd    ;
wire ALUSrc   ;
wire RegWr    ;
wire i_jump ;
wire [`DATA_WID-1:0] pc_out ;
wire [`DATA_WID-1:0] ALU_OUT;
wire [`DATA_WID-1:0] o_Write_mem ;
wire [`DATA_WID-1:0] pc_instr ;
wire [`DATA_WID-1:0] rd_data_mem;


instr_mem PROGRAM_MEMORY(.pc_addr(pc_out), .o_instr(o_instr)); 

Control_UNIT CU(
.i_funct(o_instr[5:0]), 
.i_OPCODE(o_instr[31:26]) ,
.o_alu_control(o_alu_control),
.RegDst(RegDst) , 
.ALUSrc(ALUSrc), 
.MemReg(MemReg) , 
.RegWr(RegWr), 
.MemRd(MemRd), 
.MemWr(MemWr),
.o_branch(o_branch), 
.i_jump(i_jump)
);


DATA_PATH DU(
 .i_clk(i_clk) , 
 .rst_n(rst_n) ,
 .rd_data(rd_data_mem) ,
 .inst(o_instr),
 .RegDst(RegDst),
 .o_branch(o_branch) ,                    
 .MemReg(MemReg) ,
 .ALUSrc(ALUSrc) , 
 .RegWr(RegWr) , 
 .i_jump(i_jump),
 .o_alu_control(o_alu_control) ,
 .pc_out(pc_out) ,
 .WR_mem(o_Write_mem) ,
 .ALU_OUT(ALU_OUT) ,
 .zero(zero) 
);

DATA_MEM MEMORY(
 .i_clk(i_clk) ,
 .i_addr(ALU_OUT) , 
 .i_write(MemWr), 
 .i_data(o_Write_mem) , 
 .i_read(MemRd), 
 .o_data(rd_data_mem));

endmodule
module TOP_DESIGN
(
 input i_clk , 
 input rst_n ,
 input enable ,
 output zero 
  );

wire [`INSTR_WIDTH-1:0] o_instr ;
wire [`ALU_CONTROL-1:0] o_alu_control   ;
wire [`OPCODE_WIDTH-1:0] i_OPCODE     ;
wire RegDst  ;
wire o_branch ;
wire MemReg   ;
wire MemWr ;
wire MemRd    ;
wire ALUSrc   ;
wire RegWr    ;
wire i_jump ;
wire [`DATA_WID-1:0] pc_out ;
wire [`DATA_WID-1:0] ALU_OUT;
wire [`DATA_WID-1:0] o_Write_mem ;
wire [`DATA_WID-1:0] pc_instr ;
wire [`DATA_WID-1:0] rd_data_mem;


instr_mem PROGRAM_MEMORY(.pc_addr(pc_out), .o_instr(o_instr)); 

Control_UNIT CU(
.i_funct(o_instr[5:0]), 
.i_OPCODE(o_instr[31:26]) ,
.o_alu_control(o_alu_control),
.RegDst(RegDst) , 
.ALUSrc(ALUSrc), 
.MemReg(MemReg) , 
.RegWr(RegWr), 
.MemRd(MemRd), 
.MemWr(MemWr),
.o_branch(o_branch), 
.i_jump(i_jump)
);


DATA_PATH DU(
 .i_clk(i_clk) , 
 .rst_n(rst_n) ,
 .rd_data(rd_data_mem) ,
 .inst(o_instr),
 .RegDst(RegDst),
 .o_branch(o_branch) ,                    
 .MemReg(MemReg) ,
 .ALUSrc(ALUSrc) , 
 .RegWr(RegWr) , 
 .i_jump(i_jump),
 .o_alu_control(o_alu_control) ,
 .pc_out(pc_out) ,
 .WR_mem(o_Write_mem) ,
 .ALU_OUT(ALU_OUT) ,
 .zero(zero) 
);

DATA_MEM MEMORY(
 .i_clk(i_clk) ,
 .i_addr(ALU_OUT) , 
 .i_write(MemWr), 
 .i_data(o_Write_mem) , 
 .i_read(MemRd), 
 .o_data(rd_data_mem));

endmodule