data/full_repos/permissive/430026064/imm_generator.v
1: b'%Error: data/full_repos/permissive/430026064/imm_generator.v:1: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/430026064/imm_generator.v:13: Define or directive not defined: \'`L_type\'\n   `L_type: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:13: syntax error, unexpected \':\', expecting endcase\n   `L_type: begin\n          ^\n%Error: data/full_repos/permissive/430026064/imm_generator.v:17: Define or directive not defined: \'`S_type\'\n   `S_type: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:17: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `S_type: begin\n            ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:22: Define or directive not defined: \'`CB_type\'\n   `CB_type: begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:22: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `CB_type: begin\n             ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:27: Define or directive not defined: \'`LUI_type\'\n           `LUI_type: begin \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:27: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `LUI_type: begin \n                      ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:31: Define or directive not defined: \'`AUIPC_type\'\n           `AUIPC_type: begin \n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:31: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `AUIPC_type: begin \n                        ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:35: Define or directive not defined: \'`JAL_type\'\n           `JAL_type: begin\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:35: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `JAL_type: begin\n                      ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:43: Define or directive not defined: \'`JALR_type\'\n           `JALR_type: begin\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:43: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `JALR_type: begin\n                       ^~~~~\n%Error: data/full_repos/permissive/430026064/imm_generator.v:47: syntax error, unexpected \':\', expecting clocking\n           default: begin\n                  ^\n%Error: Cannot continue\n'
module imm_generator(clk, in_data, out_data);
  	input clk;
	input wire [31:0] in_data;
	output reg [31:0] out_data;
  
 	wire [6:0] opcode;
  	assign opcode = in_data[6:0];
  
  	always@(*) begin
		case(opcode)
			`L_type: begin
              out_data[11:0]  = in_data[31:20];
              out_data[31:12] = {20{in_data[31]}};
			end
			`S_type: begin
              out_data[4:0]   = in_data[11:7];
              out_data[11:5]  = in_data[31:25];
              out_data[31:12] = {20{in_data[31]}};
			end			
			`CB_type: begin
              out_data[4:0]   = in_data[11:7];
              out_data[11:5]  = in_data[31:25];
              out_data[31:12] = {20{in_data[31]}};
			end
          	`LUI_type: begin 
              out_data[31:12] = in_data[31:12];
              out_data[11:0]  = 0;
            end
          	`AUIPC_type: begin 
              out_data[31:12] = in_data[31:12];
              out_data[11:0]  = 0;
            end
          	`JAL_type: begin
              out_data[0]  	  = 0;
              out_data[10:1]  = in_data[30:21];
              out_data[11]    = in_data[20];
              out_data[19:12] = in_data[19:12];
              out_data[20] 	  = in_data[31];
              out_data[31:21] = {11{in_data[31]}};
			end
          	`JALR_type: begin
              out_data[11:0]  = in_data[31:20];
              out_data[31:12] = {20{in_data[31]}};
            end
          	default: begin

            end
		endcase

	end
endmodule
module imm_generator(clk, in_data, out_data);

  	input clk;
	input wire [31:0] in_data;
	output reg [31:0] out_data;
  
 	wire [6:0] opcode;
  	assign opcode = in_data[6:0];
  
  	always@(*) begin
		case(opcode)
			`L_type: begin
              out_data[11:0]  = in_data[31:20];
              out_data[31:12] = {20{in_data[31]}};
			end
			`S_type: begin
              out_data[4:0]   = in_data[11:7];
              out_data[11:5]  = in_data[31:25];
              out_data[31:12] = {20{in_data[31]}};
			end			
			`CB_type: begin
              out_data[4:0]   = in_data[11:7];
              out_data[11:5]  = in_data[31:25];
              out_data[31:12] = {20{in_data[31]}};
			end
          	`LUI_type: begin 
              out_data[31:12] = in_data[31:12];
              out_data[11:0]  = 0;
            end
          	`AUIPC_type: begin 
              out_data[31:12] = in_data[31:12];
              out_data[11:0]  = 0;
            end
          	`JAL_type: begin
              out_data[0]  	  = 0;
              out_data[10:1]  = in_data[30:21];
              out_data[11]    = in_data[20];
              out_data[19:12] = in_data[19:12];
              out_data[20] 	  = in_data[31];
              out_data[31:21] = {11{in_data[31]}};
			end
          	`JALR_type: begin
              out_data[11:0]  = in_data[31:20];
              out_data[31:12] = {20{in_data[31]}};
            end
          	default: begin

            end
		endcase

	end
endmodule