data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ioslave_dl.v
data/verilator_xmls/5ef33905-73ff-4930-a09e-577a65139436.xml
module bw_ioslave_dl(

	dqs_in,
	lpf_out,
	se,
	si,
	strobe,

	dqs_out,
	so          );

	input		dqs_in;
	input [4:0]	lpf_out;
	input		se;
	input		si;
	input		strobe;

	output		dqs_out;
	output		so;

       parameter DELAY = 1250;

        reg             dqs_out;


        always @(dqs_in)
          begin
            dqs_out <= #DELAY dqs_in;
          end


endmodule
module bw_ioslave_dl(

	dqs_in,
	lpf_out,
	se,
	si,
	strobe,

	dqs_out,
	so          );


	input		dqs_in;
	input [4:0]	lpf_out;
	input		se;
	input		si;
	input		strobe;

	output		dqs_out;
	output		so;

       parameter DELAY = 1250;

        reg             dqs_out;


        always @(dqs_in)
          begin
            dqs_out <= #DELAY dqs_in;
          end


endmodule