data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:36: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [PRIORITY_BITWIDTH-1:0]  left_priority_i,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:37: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [PRIORITY_BITWIDTH-1:0]  right_priority_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:38: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [ID_BITWIDTH-1:0      ]  left_identifier_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:39: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [ID_BITWIDTH-1:0      ]  right_identifier_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:40: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [PRIORITY_BITWIDTH-1:0]  larger_priority_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/plic_comparator.sv:41: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic[ ID_BITWIDTH-1:0      ]  identifier_of_larger_o\n                ^\n%Error: Exiting due to 6 warning(s)\n'
module plic_comparator #(
    parameter int ID_BITWIDTH       = -1,
    parameter int PRIORITY_BITWIDTH = -1
)(
    input  logic [PRIORITY_BITWIDTH-1:0]  left_priority_i,
    input  logic [PRIORITY_BITWIDTH-1:0]  right_priority_i,
    input  logic [ID_BITWIDTH-1:0      ]  left_identifier_i,
    input  logic [ID_BITWIDTH-1:0      ]  right_identifier_i,
    output logic [PRIORITY_BITWIDTH-1:0]  larger_priority_o,
    output logic[ ID_BITWIDTH-1:0      ]  identifier_of_larger_o
);

    always_comb begin : proc_compare
        if (left_priority_i >= right_priority_i) begin
            larger_priority_o      = left_priority_i;
            identifier_of_larger_o = left_identifier_i;
        end else begin
            larger_priority_o      = right_priority_i;
            identifier_of_larger_o = right_identifier_i;
        end
    end


    `ifndef VERILATOR
    initial begin
        assert(ID_BITWIDTH       > 0)   else $error("ID_BITWIDTH has to be larger than 0");
        assert(PRIORITY_BITWIDTH > 0)   else $error("PRIORITY_BITWIDTH has to be larger than 0");
    end
    `endif


endmodule
module plic_comparator #(
    parameter int ID_BITWIDTH       = -1,
    parameter int PRIORITY_BITWIDTH = -1
)(
    input  logic [PRIORITY_BITWIDTH-1:0]  left_priority_i,
    input  logic [PRIORITY_BITWIDTH-1:0]  right_priority_i,
    input  logic [ID_BITWIDTH-1:0      ]  left_identifier_i,
    input  logic [ID_BITWIDTH-1:0      ]  right_identifier_i,
    output logic [PRIORITY_BITWIDTH-1:0]  larger_priority_o,
    output logic[ ID_BITWIDTH-1:0      ]  identifier_of_larger_o
);


    always_comb begin : proc_compare
        if (left_priority_i >= right_priority_i) begin
            larger_priority_o      = left_priority_i;
            identifier_of_larger_o = left_identifier_i;
        end else begin
            larger_priority_o      = right_priority_i;
            identifier_of_larger_o = right_identifier_i;
        end
    end


    `ifndef VERILATOR
    initial begin
        assert(ID_BITWIDTH       > 0)   else $error("ID_BITWIDTH has to be larger than 0");
        assert(PRIORITY_BITWIDTH > 0)   else $error("PRIORITY_BITWIDTH has to be larger than 0");
    end
    `endif


endmodule