data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Multiple top level modules\n                                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                  : ... Top module \'axi_arbiter\'\nmodule axi_arbiter #(\n       ^~~~~~~~~~~\n                                                                                                                                  : ... Top module \'AXI_ARBITRATION\'\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Unsupported: Interfaced port on top level module\n  AXI_ARBITRATION.arb arb\n                      ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Cannot find file containing interface: \'AXI_ARBITRATION\'\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: ../V3LinkDot.cpp:2055: Unlinked interface\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n'
module axi_arbiter #(

  parameter int NUM_REQ = -1
)(
  input logic clk_i       ,
  input logic rst_ni      ,
  AXI_ARBITRATION.arb arb
);

  `ifndef SYNTHESIS
  initial begin
    assert(NUM_REQ >= 0);
    assert(arb.NUM_REQ == NUM_REQ);
  end
  `endif

  logic [$clog2(NUM_REQ)-1:0] count_d, count_q;

  axi_arbiter_tree #(
    .NUM_REQ  ( NUM_REQ ),
    .ID_WIDTH ( 0       )
  ) i_tree (
    .in_req_i  ( arb.in_req  ),
    .in_ack_o  ( arb.in_ack  ),
    .in_id_i   ( '0          ),
    .out_req_o ( arb.out_req ),
    .out_ack_i ( arb.out_ack ),
    .out_id_o  ( arb.out_sel ),
    .shift_i   ( count_q     )
  );

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      count_q <= '0;
    end else if (arb.out_req && arb.out_ack) begin
      count_q <= (count_d == NUM_REQ ? '0 : count_d);
    end
  end

  assign count_d = count_q + 1;

endmodule
module axi_arbiter #(

  parameter int NUM_REQ = -1
)(
  input logic clk_i       ,
  input logic rst_ni      ,
  AXI_ARBITRATION.arb arb
);


  `ifndef SYNTHESIS
  initial begin
    assert(NUM_REQ >= 0);
    assert(arb.NUM_REQ == NUM_REQ);
  end
  `endif

  logic [$clog2(NUM_REQ)-1:0] count_d, count_q;

  axi_arbiter_tree #(
    .NUM_REQ  ( NUM_REQ ),
    .ID_WIDTH ( 0       )
  ) i_tree (
    .in_req_i  ( arb.in_req  ),
    .in_ack_o  ( arb.in_ack  ),
    .in_id_i   ( '0          ),
    .out_req_o ( arb.out_req ),
    .out_ack_i ( arb.out_ack ),
    .out_id_o  ( arb.out_sel ),
    .shift_i   ( count_q     )
  );

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      count_q <= '0;
    end else if (arb.out_req && arb.out_ack) begin
      count_q <= (count_d == NUM_REQ ? '0 : count_d);
    end
  end

  assign count_d = count_q + 1;

endmodule