data/full_repos/permissive/418749135/tff.v
data/verilator_xmls/f0ccbade-9381-44d4-951a-bd00305088d6.xml
module tff ( input clk, input rstn, input t, output reg q);  
  
  always @ (posedge clk) begin  
    if (!rstn)  
      q <= 0;  
    else  
        if (t)  
            q <= ~q;  
        else  
            q <= q;  
  end  
endmodule
module tff ( input clk, input rstn, input t, output reg q);
  
  
  always @ (posedge clk) begin  
    if (!rstn)  
      q <= 0;  
    else  
        if (t)  
            q <= ~q;  
        else  
            q <= q;  
  end  
endmodule