data/full_repos/permissive/4847981/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/4847981/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/4847981/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/4847981/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/4847981/test.v:40: Cannot find file containing module: \'td4\'\n td4 uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/4847981,data/full_repos/permissive/4847981/td4\n             data/full_repos/permissive/4847981,data/full_repos/permissive/4847981/td4.v\n             data/full_repos/permissive/4847981,data/full_repos/permissive/4847981/td4.sv\n             td4\n             td4.v\n             td4.sv\n             obj_dir/td4\n             obj_dir/td4.v\n             obj_dir/td4.sv\n%Error: data/full_repos/permissive/4847981/test.v:48: Cannot find file containing module: \'mem\'\n mem memory (MEM_ADDR, MEM_DATA);\n ^~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg [3:0] IN;
	reg CLK;


	wire [3:0] OUT;
	wire [3:0] MEM_ADDR;
	
	wire [7:0] MEM_DATA;
	
	integer count;


	td4 uut (
		.IN(IN), 
		.OUT(OUT), 
		.MEM_DATA(MEM_DATA), 
		.MEM_ADDR(MEM_ADDR), 
		.CLK(CLK)
	);
	
	mem memory (MEM_ADDR, MEM_DATA);

	initial begin

		IN = 0;
		CLK = 0;


		
		for (count = 0; count < 200; count = count + 1) begin
			#1;
			CLK=1;
			#1;
			CLK=0;
		end
        
		#10 $finish;
	end
      
endmodule
module test;



	reg [3:0] IN;
	reg CLK;


	wire [3:0] OUT;
	wire [3:0] MEM_ADDR;
	
	wire [7:0] MEM_DATA;
	
	integer count;


	td4 uut (
		.IN(IN), 
		.OUT(OUT), 
		.MEM_DATA(MEM_DATA), 
		.MEM_ADDR(MEM_ADDR), 
		.CLK(CLK)
	);
	
	mem memory (MEM_ADDR, MEM_DATA);

	initial begin

		IN = 0;
		CLK = 0;


		
		for (count = 0; count < 200; count = count + 1) begin
			#1;
			CLK=1;
			#1;
			CLK=0;
		end
        
		#10 $finish;
	end
      
endmodule