data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v
1: b'%Error: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:18: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n    f = $fopen("data_1d_out.txt");\n        ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #(10);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #110\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #11\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #(10);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #9\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #90\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/508935683/Verilog/tb_dct_1d.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dct_1d();

reg clk, rst, enb;
reg [7:0] data_in;
reg [7:0] data_65536 [0:65536];
reg [7:0] data_out_reg;
wire [9:0] data_out;
wire tp_enb;

dct_1d dctTEST(data_out, tp_enb, data_in, clk, rst, enb);

integer i, j, k;
integer f;

initial begin
    f = $fopen("data_1d_out.txt");
    #110
    for (j=0;j<65536;j=j+1) begin

        $fwrite(f, "%10b\n", data_out);
        k = j / 8;
        #(10);
    end
    $fclose(f);
end

initial begin
    rst <= 1;
    clk <= 1;
    enb <= 0;
    $readmemb("./data1.txt", data_65536);
    #11
    rst <= 0;
    enb <= 1;
    #9
    for (i=0;i<65536;i=i+1) begin
        data_in <= data_65536[i];
        #(10);
    end
    #90
    $finish;
end

always #5 clk <= ~clk;

endmodule
module tb_dct_1d();


reg clk, rst, enb;
reg [7:0] data_in;
reg [7:0] data_65536 [0:65536];
reg [7:0] data_out_reg;
wire [9:0] data_out;
wire tp_enb;

dct_1d dctTEST(data_out, tp_enb, data_in, clk, rst, enb);

integer i, j, k;
integer f;

initial begin
    f = $fopen("data_1d_out.txt");
    #110
    for (j=0;j<65536;j=j+1) begin

        $fwrite(f, "%10b\n", data_out);
        k = j / 8;
        #(10);
    end
    $fclose(f);
end

initial begin
    rst <= 1;
    clk <= 1;
    enb <= 0;
    $readmemb("./data1.txt", data_65536);
    #11
    rst <= 0;
    enb <= 1;
    #9
    for (i=0;i<65536;i=i+1) begin
        data_in <= data_65536[i];
        #(10);
    end
    #90
    $finish;
end

always #5 clk <= ~clk;

endmodule