data/full_repos/permissive/466874195/verilog/rtl/find.v
1: b"%Error: data/full_repos/permissive/466874195/verilog/rtl/find.v:32: Cannot find file containing module: 'gen_mask'\ngen_mask # (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/gen_mask\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/gen_mask.v\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/gen_mask.sv\n             gen_mask\n             gen_mask.v\n             gen_mask.sv\n             obj_dir/gen_mask\n             obj_dir/gen_mask.v\n             obj_dir/gen_mask.sv\n%Error: data/full_repos/permissive/466874195/verilog/rtl/find.v:42: Cannot find file containing module: 'sequence_generator'\nsequence_generator # (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466874195/verilog/rtl/find.v:59: Cannot find file containing module: 'calc_e_pl'\ncalc_e_pl # (\n^~~~~~~~~\n%Error: data/full_repos/permissive/466874195/verilog/rtl/find.v:79: Cannot find file containing module: 'optimum_sequence'\noptimum_sequence # (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module find #
(
    parameter SEQ_WIDTH = 8,
    parameter FIX_WIDTH = 2,
    parameter FIX_SEQ = 0,
    parameter STAGE_WIDTH = 20,
    parameter E_WIDTH = 20
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [6:0]               i_offset,

    output wire [SEQ_WIDTH-1:0]     o_seq,
    output wire [E_WIDTH-1:0]       o_e,
    output reg                      o_done
);

wire [SEQ_WIDTH-1:0] seq, seq2;
wire [SEQ_WIDTH-1:0] mask;
wire [E_WIDTH-1:0] e;
wire seq_valid, e_valid;
wire seq_done;
wire i_ready, o_ready;

assign i_ready = 1'b1;

gen_mask # (
    .SEQ_WIDTH(SEQ_WIDTH)
) inst_gen_mask (
    .clk(clk),
    .rst(rst),

    .i_offset(i_offset),
    .o_mask(mask)
);

sequence_generator # (
    .SEQ_WIDTH(SEQ_WIDTH), 
    .FIX_WIDTH(FIX_WIDTH), 
    .FIX_SEQ(FIX_SEQ)
) gen (
    .clk(clk),
    .rst(rst),

    .i_ready(o_ready),
    .i_offset(i_offset),

    .o_seq(seq),
    .o_valid(seq_valid),
    .o_done(seq_done)
);


calc_e_pl # (
    .SEQ_WIDTH(SEQ_WIDTH),
    .E_WIDTH(E_WIDTH),
    .STAGE_WIDTH(STAGE_WIDTH)
) calc (
    .clk(clk),
    .rst(rst),

    .i_offset(i_offset),
    .i_mask(mask),
    .i_seq(seq),
    .i_valid(seq_valid),
    .i_ready(i_ready),

    .o_seq(seq2),
    .o_e(e),
    .o_valid(e_valid),
    .o_ready(o_ready)
);

optimum_sequence # (
    .SEQ_WIDTH(SEQ_WIDTH), 
    .E_WIDTH(E_WIDTH)
) opt (
    .clk(clk),
    .rst(rst),
    
    .i_seq(seq2),
    .i_e(e),
    .i_valid(e_valid),
    .o_seq(o_seq), 
    .o_e(o_e)
);

always @(posedge clk)
    o_done <= seq_done & ~e_valid & ~rst;

endmodule
module find #
(
    parameter SEQ_WIDTH = 8,
    parameter FIX_WIDTH = 2,
    parameter FIX_SEQ = 0,
    parameter STAGE_WIDTH = 20,
    parameter E_WIDTH = 20
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [6:0]               i_offset,

    output wire [SEQ_WIDTH-1:0]     o_seq,
    output wire [E_WIDTH-1:0]       o_e,
    output reg                      o_done
);


wire [SEQ_WIDTH-1:0] seq, seq2;
wire [SEQ_WIDTH-1:0] mask;
wire [E_WIDTH-1:0] e;
wire seq_valid, e_valid;
wire seq_done;
wire i_ready, o_ready;

assign i_ready = 1'b1;

gen_mask # (
    .SEQ_WIDTH(SEQ_WIDTH)
) inst_gen_mask (
    .clk(clk),
    .rst(rst),

    .i_offset(i_offset),
    .o_mask(mask)
);

sequence_generator # (
    .SEQ_WIDTH(SEQ_WIDTH), 
    .FIX_WIDTH(FIX_WIDTH), 
    .FIX_SEQ(FIX_SEQ)
) gen (
    .clk(clk),
    .rst(rst),

    .i_ready(o_ready),
    .i_offset(i_offset),

    .o_seq(seq),
    .o_valid(seq_valid),
    .o_done(seq_done)
);


calc_e_pl # (
    .SEQ_WIDTH(SEQ_WIDTH),
    .E_WIDTH(E_WIDTH),
    .STAGE_WIDTH(STAGE_WIDTH)
) calc (
    .clk(clk),
    .rst(rst),

    .i_offset(i_offset),
    .i_mask(mask),
    .i_seq(seq),
    .i_valid(seq_valid),
    .i_ready(i_ready),

    .o_seq(seq2),
    .o_e(e),
    .o_valid(e_valid),
    .o_ready(o_ready)
);

optimum_sequence # (
    .SEQ_WIDTH(SEQ_WIDTH), 
    .E_WIDTH(E_WIDTH)
) opt (
    .clk(clk),
    .rst(rst),
    
    .i_seq(seq2),
    .i_e(e),
    .i_valid(e_valid),
    .o_seq(o_seq), 
    .o_e(o_e)
);

always @(posedge clk)
    o_done <= seq_done & ~e_valid & ~rst;

endmodule