data/full_repos/permissive/485085993/verilog/rtl/gpio.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/gpio.v:25: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'GPIO\'\nmodule GPIO (\n       ^~~~\n                                                                             : ... Top module \'GPIN\'\nmodule GPIN (\n       ^~~~\n                                                                             : ... Top module \'GPOUT\'\nmodule GPOUT (\n       ^~~~~\n                                                                             : ... Top module \'EMBEDDED_IO\'\nmodule EMBEDDED_IO (\n       ^~~~~~~~~~~\n                                                                             : ... Top module \'EMBEDDED_IO_ISOLN\'\nmodule EMBEDDED_IO_ISOLN (\n       ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module EMBEDDED_IO (
  input SOC_IN,
  output SOC_OUT,
  output SOC_DIR,
  output FPGA_IN,
  input FPGA_OUT,
  input FPGA_DIR
);

  assign FPGA_IN = SOC_IN;
  assign SOC_OUT = FPGA_OUT;
  assign SOC_DIR = FPGA_DIR;
endmodule
module EMBEDDED_IO (
  input SOC_IN,
  output SOC_OUT,
  output SOC_DIR,
  output FPGA_IN,
  input FPGA_OUT,
  input FPGA_DIR
);


  assign FPGA_IN = SOC_IN;
  assign SOC_OUT = FPGA_OUT;
  assign SOC_DIR = FPGA_DIR;
endmodule