data/full_repos/permissive/52900389/Comp_16bits_tb.v
1: b'%Error: data/full_repos/permissive/52900389/Comp_16bits_tb.v:30: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n reg [15:0] ref;\n            ^~~\n%Error: data/full_repos/permissive/52900389/Comp_16bits_tb.v:40: syntax error, unexpected ref\n  .ref(ref)\n   ^~~\n%Error: data/full_repos/permissive/52900389/Comp_16bits_tb.v:47: syntax error, unexpected ref\n  ref = 0;\n  ^~~\n%Warning-STMTDLY: data/full_repos/permissive/52900389/Comp_16bits_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Comp_16bits_tb;


	reg [15:0] in;
	reg rst;
	reg [15:0] ref;


	wire out;


	Comp_16bits uut (
		.in(in), 
		.out(out), 
		.rst(rst), 
		.ref(ref)
	);

	initial begin

		in = 0;
		rst = 0;
		ref = 0;


		#100;
        

		
		

	end
      
endmodule
module Comp_16bits_tb;



	reg [15:0] in;
	reg rst;
	reg [15:0] ref;


	wire out;


	Comp_16bits uut (
		.in(in), 
		.out(out), 
		.rst(rst), 
		.ref(ref)
	);

	initial begin

		in = 0;
		rst = 0;
		ref = 0;


		#100;
        

		
		

	end
      
endmodule