data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v
1: b'%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:4: Cannot find include file: noc_parameter.vh\n    `include  "noc_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:5: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:6: Cannot find include file: chip_ids.vh\n    ,`include "chip_ids.vh" \n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:5: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:8: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter HOST_PORT = 16\'d1800,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FPGA_PORT = 16\'d1800\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:10: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          config_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          trigger_system_reset_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          eth_system_reset_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [15:0] eth_status_vector_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                   [31:0] eth_config_vector_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          eth_an_complete_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [1:0] eth_pll_lock_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] udp_status_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] rx_udp_error_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] mac_status_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] fpga_ip_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                   [15:0] fpga_port_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [47:0] fpga_mac_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          set_host_ip_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] host_ip_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                   [31:0] host_ip_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                   [15:0] host_port_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:40: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_CHIPID_SIZE-1:0] host_chipid_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:41: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_regfile.v:101: syntax error, unexpected always\n    always @(posedge clk_i or negedge reset_n_i) begin\n    ^~~~~~\n%Error: Exiting due to 32 error(s)\n'
module ethernet_regfile #(
    `include  "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,`include "chip_ids.vh"
    ,parameter HOST_IP  = {8'd192, 8'd168, 8'd42, 8'd25},
    parameter HOST_PORT = 16'd1800,
    parameter FPGA_PORT = 16'd1800
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                          config_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    input  wire                          trigger_system_reset_i,
    output wire                          eth_system_reset_o,
    input  wire                   [15:0] eth_status_vector_i,
    output wire                   [31:0] eth_config_vector_o,
    input  wire                          eth_an_complete_i,
    input  wire                    [1:0] eth_pll_lock_i,
    input  wire                   [31:0] udp_status_i,
    input  wire                   [31:0] rx_udp_error_i,
    input  wire                   [31:0] mac_status_i,
    input  wire                   [31:0] fpga_ip_addr_i,
    output wire                   [15:0] fpga_port_o,
    input  wire                   [47:0] fpga_mac_addr_i,
    input  wire                          set_host_ip_i,
    input  wire                   [31:0] host_ip_addr_i,
    output wire                   [31:0] host_ip_addr_o,
    output wire                   [15:0] host_port_o,
    output wire    [NOC_CHIPID_SIZE-1:0] host_chipid_o
);

    integer i;



    localparam REG_ETH_SYSTEM_RESET  = 32'h00000000;
    localparam REG_ETH_STATUS_VECTOR = 32'h00000008;
    localparam REG_ETH_UDP_STATUS    = 32'h00000010;
    localparam REG_ETH_RX_UDP_ERROR  = 32'h00000018;
    localparam REG_ETH_MAC_STATUS    = 32'h00000020;
    localparam REG_ETH_FPGA_IP       = 32'h00000028;
    localparam REG_ETH_FPGA_PORT     = 32'h00000030;
    localparam REG_ETH_FPGA_MAC      = 32'h00000038;
    localparam REG_ETH_HOST_IP       = 32'h00000040;
    localparam REG_ETH_HOST_PORT     = 32'h00000048;
    localparam REG_ETH_HOST_CHIPID   = 32'h00000050;
    localparam REG_ETH_CONFIG_VECTOR = 32'h00000058;
    localparam REG_ETH_AN_COMPLETE   = 32'h00000060;
    localparam REG_ETH_PLL_LOCK      = 32'h00000068;

    localparam [4:0] PCSPMA_CONFIG_VECTOR = {
        1'b1,
        1'b0,
        1'b0,
        1'b0,
        1'b0
    };

    localparam [15:0] PCSPMA_AN_CONFIG_VECTOR = {
        1'b1,
        1'b1,
        2'b01,
        2'b10,
        1'b0,
        2'b00,
        1'b0,
        1'b0,
        4'b0000,
        1'b1
    };




    reg                       r_eth_system_reset, rin_eth_system_reset;
    reg                [21:0] r_eth_config_vector, rin_eth_config_vector;
    reg                [15:0] r_eth_fpga_port, rin_eth_fpga_port;
    reg                [31:0] r_eth_host_ip, rin_eth_host_ip;
    reg                [15:0] r_eth_host_port, rin_eth_host_port;
    reg [NOC_CHIPID_SIZE-1:0] r_eth_host_chipid, rin_eth_host_chipid;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_eth_system_reset <= 1'b0;
            r_eth_config_vector <= {1'b0, PCSPMA_CONFIG_VECTOR, PCSPMA_AN_CONFIG_VECTOR};
            r_eth_fpga_port <= FPGA_PORT;
            r_eth_host_ip <= HOST_IP;
            r_eth_host_port <= HOST_PORT;
            r_eth_host_chipid <= CHIPID_HOST;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_eth_system_reset <= rin_eth_system_reset;
            r_eth_config_vector <= rin_eth_config_vector;
            r_eth_fpga_port <= rin_eth_fpga_port;
            r_eth_host_ip <= rin_eth_host_ip;
            r_eth_host_port <= rin_eth_host_port;
            r_eth_host_chipid <= rin_eth_host_chipid;

            r_config_rdata <= rin_config_rdata;
        end
    end




    always @* begin
        rin_eth_system_reset = r_eth_system_reset || trigger_system_reset_i;
        rin_eth_config_vector = r_eth_config_vector;
        rin_eth_fpga_port = r_eth_fpga_port;
        rin_eth_host_ip = set_host_ip_i ? host_ip_addr_i : r_eth_host_ip;
        rin_eth_host_port = r_eth_host_port;
        rin_eth_host_chipid = r_eth_host_chipid;

        rin_config_rdata = r_config_rdata;




        if (reg_w_en) begin
            case (config_addr_i)
                REG_ETH_SYSTEM_RESET: begin
                    if (config_wben_i == {TCU_REG_BSEL_SIZE{1'b1}}) begin
                        rin_eth_system_reset = 1'b1;
                    end
                end

                REG_ETH_FPGA_PORT: begin
                    for (i=0; i<2; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_fpga_port[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_IP: begin
                    for (i=0; i<4; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_host_ip[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_PORT: begin
                    for (i=0; i<2; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_host_port[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_CHIPID: begin
                    if (config_wben_i[0]) begin
                        rin_eth_host_chipid = config_wdata_i[NOC_CHIPID_SIZE-1:0];
                    end
                end

                REG_ETH_CONFIG_VECTOR: begin
                    if (config_wben_i[0]) begin
                        rin_eth_config_vector[7:0] = config_wdata_i[7:0];
                    end
                    if (config_wben_i[1]) begin
                        rin_eth_config_vector[15:8] = config_wdata_i[15:8];
                    end
                    if (config_wben_i[2]) begin
                        rin_eth_config_vector[21:16] = config_wdata_i[21:16];
                    end
                end
            endcase
        end



        else if (reg_r_en) begin
            case (config_addr_i)
                REG_ETH_STATUS_VECTOR: begin
                    rin_config_rdata = eth_status_vector_i;
                end

                REG_ETH_UDP_STATUS: begin
                    rin_config_rdata = udp_status_i;
                end

                REG_ETH_RX_UDP_ERROR: begin
                    rin_config_rdata = rx_udp_error_i;
                end

                REG_ETH_MAC_STATUS: begin
                    rin_config_rdata = mac_status_i;
                end

                REG_ETH_FPGA_IP: begin
                    rin_config_rdata = fpga_ip_addr_i;
                end

                REG_ETH_FPGA_PORT: begin
                    rin_config_rdata = r_eth_fpga_port;
                end

                REG_ETH_FPGA_MAC: begin
                    rin_config_rdata = fpga_mac_addr_i;
                end

                REG_ETH_HOST_IP: begin
                    rin_config_rdata = r_eth_host_ip;
                end

                REG_ETH_HOST_PORT: begin
                    rin_config_rdata = r_eth_host_port;
                end

                REG_ETH_HOST_CHIPID: begin
                    rin_config_rdata = r_eth_host_chipid;
                end

                REG_ETH_CONFIG_VECTOR: begin
                    rin_config_rdata = r_eth_config_vector;
                end

                REG_ETH_AN_COMPLETE: begin
                    rin_config_rdata = eth_an_complete_i;
                end

                REG_ETH_PLL_LOCK: begin
                    rin_config_rdata = eth_pll_lock_i;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;

    assign eth_system_reset_o = r_eth_system_reset;
    assign eth_config_vector_o = {10'h0, r_eth_config_vector};
    assign fpga_port_o = r_eth_fpga_port;
    assign host_ip_addr_o = r_eth_host_ip;
    assign host_port_o = r_eth_host_port;
    assign host_chipid_o = r_eth_host_chipid;


endmodule
module ethernet_regfile #(
    `include  "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,`include "chip_ids.vh"
    ,parameter HOST_IP  = {8'd192, 8'd168, 8'd42, 8'd25},
    parameter HOST_PORT = 16'd1800,
    parameter FPGA_PORT = 16'd1800
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                          config_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    input  wire                          trigger_system_reset_i,
    output wire                          eth_system_reset_o,
    input  wire                   [15:0] eth_status_vector_i,
    output wire                   [31:0] eth_config_vector_o,
    input  wire                          eth_an_complete_i,
    input  wire                    [1:0] eth_pll_lock_i,
    input  wire                   [31:0] udp_status_i,
    input  wire                   [31:0] rx_udp_error_i,
    input  wire                   [31:0] mac_status_i,
    input  wire                   [31:0] fpga_ip_addr_i,
    output wire                   [15:0] fpga_port_o,
    input  wire                   [47:0] fpga_mac_addr_i,
    input  wire                          set_host_ip_i,
    input  wire                   [31:0] host_ip_addr_i,
    output wire                   [31:0] host_ip_addr_o,
    output wire                   [15:0] host_port_o,
    output wire    [NOC_CHIPID_SIZE-1:0] host_chipid_o
);


    integer i;



    localparam REG_ETH_SYSTEM_RESET  = 32'h00000000;
    localparam REG_ETH_STATUS_VECTOR = 32'h00000008;
    localparam REG_ETH_UDP_STATUS    = 32'h00000010;
    localparam REG_ETH_RX_UDP_ERROR  = 32'h00000018;
    localparam REG_ETH_MAC_STATUS    = 32'h00000020;
    localparam REG_ETH_FPGA_IP       = 32'h00000028;
    localparam REG_ETH_FPGA_PORT     = 32'h00000030;
    localparam REG_ETH_FPGA_MAC      = 32'h00000038;
    localparam REG_ETH_HOST_IP       = 32'h00000040;
    localparam REG_ETH_HOST_PORT     = 32'h00000048;
    localparam REG_ETH_HOST_CHIPID   = 32'h00000050;
    localparam REG_ETH_CONFIG_VECTOR = 32'h00000058;
    localparam REG_ETH_AN_COMPLETE   = 32'h00000060;
    localparam REG_ETH_PLL_LOCK      = 32'h00000068;

    localparam [4:0] PCSPMA_CONFIG_VECTOR = {
        1'b1,
        1'b0,
        1'b0,
        1'b0,
        1'b0
    };

    localparam [15:0] PCSPMA_AN_CONFIG_VECTOR = {
        1'b1,
        1'b1,
        2'b01,
        2'b10,
        1'b0,
        2'b00,
        1'b0,
        1'b0,
        4'b0000,
        1'b1
    };




    reg                       r_eth_system_reset, rin_eth_system_reset;
    reg                [21:0] r_eth_config_vector, rin_eth_config_vector;
    reg                [15:0] r_eth_fpga_port, rin_eth_fpga_port;
    reg                [31:0] r_eth_host_ip, rin_eth_host_ip;
    reg                [15:0] r_eth_host_port, rin_eth_host_port;
    reg [NOC_CHIPID_SIZE-1:0] r_eth_host_chipid, rin_eth_host_chipid;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_eth_system_reset <= 1'b0;
            r_eth_config_vector <= {1'b0, PCSPMA_CONFIG_VECTOR, PCSPMA_AN_CONFIG_VECTOR};
            r_eth_fpga_port <= FPGA_PORT;
            r_eth_host_ip <= HOST_IP;
            r_eth_host_port <= HOST_PORT;
            r_eth_host_chipid <= CHIPID_HOST;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_eth_system_reset <= rin_eth_system_reset;
            r_eth_config_vector <= rin_eth_config_vector;
            r_eth_fpga_port <= rin_eth_fpga_port;
            r_eth_host_ip <= rin_eth_host_ip;
            r_eth_host_port <= rin_eth_host_port;
            r_eth_host_chipid <= rin_eth_host_chipid;

            r_config_rdata <= rin_config_rdata;
        end
    end




    always @* begin
        rin_eth_system_reset = r_eth_system_reset || trigger_system_reset_i;
        rin_eth_config_vector = r_eth_config_vector;
        rin_eth_fpga_port = r_eth_fpga_port;
        rin_eth_host_ip = set_host_ip_i ? host_ip_addr_i : r_eth_host_ip;
        rin_eth_host_port = r_eth_host_port;
        rin_eth_host_chipid = r_eth_host_chipid;

        rin_config_rdata = r_config_rdata;




        if (reg_w_en) begin
            case (config_addr_i)
                REG_ETH_SYSTEM_RESET: begin
                    if (config_wben_i == {TCU_REG_BSEL_SIZE{1'b1}}) begin
                        rin_eth_system_reset = 1'b1;
                    end
                end

                REG_ETH_FPGA_PORT: begin
                    for (i=0; i<2; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_fpga_port[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_IP: begin
                    for (i=0; i<4; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_host_ip[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_PORT: begin
                    for (i=0; i<2; i=i+1) begin
                        if (config_wben_i[i]) begin
                            rin_eth_host_port[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = config_wdata_i[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE];
                        end
                    end
                end

                REG_ETH_HOST_CHIPID: begin
                    if (config_wben_i[0]) begin
                        rin_eth_host_chipid = config_wdata_i[NOC_CHIPID_SIZE-1:0];
                    end
                end

                REG_ETH_CONFIG_VECTOR: begin
                    if (config_wben_i[0]) begin
                        rin_eth_config_vector[7:0] = config_wdata_i[7:0];
                    end
                    if (config_wben_i[1]) begin
                        rin_eth_config_vector[15:8] = config_wdata_i[15:8];
                    end
                    if (config_wben_i[2]) begin
                        rin_eth_config_vector[21:16] = config_wdata_i[21:16];
                    end
                end
            endcase
        end



        else if (reg_r_en) begin
            case (config_addr_i)
                REG_ETH_STATUS_VECTOR: begin
                    rin_config_rdata = eth_status_vector_i;
                end

                REG_ETH_UDP_STATUS: begin
                    rin_config_rdata = udp_status_i;
                end

                REG_ETH_RX_UDP_ERROR: begin
                    rin_config_rdata = rx_udp_error_i;
                end

                REG_ETH_MAC_STATUS: begin
                    rin_config_rdata = mac_status_i;
                end

                REG_ETH_FPGA_IP: begin
                    rin_config_rdata = fpga_ip_addr_i;
                end

                REG_ETH_FPGA_PORT: begin
                    rin_config_rdata = r_eth_fpga_port;
                end

                REG_ETH_FPGA_MAC: begin
                    rin_config_rdata = fpga_mac_addr_i;
                end

                REG_ETH_HOST_IP: begin
                    rin_config_rdata = r_eth_host_ip;
                end

                REG_ETH_HOST_PORT: begin
                    rin_config_rdata = r_eth_host_port;
                end

                REG_ETH_HOST_CHIPID: begin
                    rin_config_rdata = r_eth_host_chipid;
                end

                REG_ETH_CONFIG_VECTOR: begin
                    rin_config_rdata = r_eth_config_vector;
                end

                REG_ETH_AN_COMPLETE: begin
                    rin_config_rdata = eth_an_complete_i;
                end

                REG_ETH_PLL_LOCK: begin
                    rin_config_rdata = eth_pll_lock_i;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;

    assign eth_system_reset_o = r_eth_system_reset;
    assign eth_config_vector_o = {10'h0, r_eth_config_vector};
    assign fpga_port_o = r_eth_fpga_port;
    assign host_ip_addr_o = r_eth_host_ip;
    assign host_port_o = r_eth_host_port;
    assign host_chipid_o = r_eth_host_chipid;


endmodule