data/full_repos/permissive/517239653/pulse_gen.v
data/verilator_xmls/3a55eb6d-c9f2-4b79-a524-6cf10b9bd83b.xml
module pulse_gen(pulse, clk, trigger);

parameter PULSE_WIDTH = 128;
output pulse;
input clk;
input trigger;

reg pulse_state = 0;
reg last_trigger = 0;
reg [31:0] pulse_counter = 0;

assign pulse = pulse_state;

always @(posedge clk) begin
    pulse_counter = pulse_counter + 1;
    

    if(trigger && !last_trigger) begin
        pulse_counter = 0;
    end


    if(pulse_counter > PULSE_WIDTH) begin
        pulse_counter = PULSE_WIDTH;
    end 


    pulse_state = (pulse_counter < PULSE_WIDTH);

    last_trigger = trigger;
end

endmodule
module pulse_gen(pulse, clk, trigger);


parameter PULSE_WIDTH = 128;
output pulse;
input clk;
input trigger;

reg pulse_state = 0;
reg last_trigger = 0;
reg [31:0] pulse_counter = 0;

assign pulse = pulse_state;

always @(posedge clk) begin
    pulse_counter = pulse_counter + 1;
    

    if(trigger && !last_trigger) begin
        pulse_counter = 0;
    end


    if(pulse_counter > PULSE_WIDTH) begin
        pulse_counter = PULSE_WIDTH;
    end 


    pulse_state = (pulse_counter < PULSE_WIDTH);

    last_trigger = trigger;
end

endmodule