data/full_repos/permissive/520038878/rtl/dBounce.v
1: b'%Warning-WIDTH: data/full_repos/permissive/520038878/rtl/dBounce.v:67: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                     : ... In instance xBitDebounce.HiThere[2].dbgen\n reg [NUMBITS:0] count = { NUMBITS{DEFAULT_STATE} };   \n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module xBitDebounce (
		input wire clock,
		input wire [NUMBITS-1:0] i_db,
		output wire [NUMBITS-1:0] o_db
	);
	parameter NUMBITS = 3;
	
	genvar i;
	generate
		for (i=0; i<NUMBITS; i=i+1) begin : HiThere
			dBounce #(.NUMCYCLES (500_000)) dbgen (
				.i_clk (clock),
				.i_db  (i_db[i]),
				.o_db  (o_db[i])
			);
		end
	endgenerate
endmodule
module xBitDebounce (
		input wire clock,
		input wire [NUMBITS-1:0] i_db,
		output wire [NUMBITS-1:0] o_db
	);

	parameter NUMBITS = 3;
	
	genvar i;
	generate
		for (i=0; i<NUMBITS; i=i+1) begin : HiThere
			dBounce #(.NUMCYCLES (500_000)) dbgen (
				.i_clk (clock),
				.i_db  (i_db[i]),
				.o_db  (o_db[i])
			);
		end
	endgenerate
endmodule