data/full_repos/permissive/431487364/src/perips/biu.v
1: b'%Error: data/full_repos/permissive/431487364/src/perips/biu.v:9: Cannot find include file: ../headers/buceros_header.v\n`include "../headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v.sv\n             ../headers/buceros_header.v\n             ../headers/buceros_header.v.v\n             ../headers/buceros_header.v.sv\n             obj_dir/../headers/buceros_header.v\n             obj_dir/../headers/buceros_header.v.v\n             obj_dir/../headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:11: Define or directive not defined: \'`MemAddrBus\'\n    input  wire [`MemAddrBus] mem_addr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire [`MemAddrBus] mem_addr_i,\n                            ^\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:12: Define or directive not defined: \'`WordBus\'\n    input  wire [   `WordBus] wmem_data_i,\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:13: Define or directive not defined: \'`MemDataBus\'\n    input  wire [`MemDataBus] ram_data_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:14: Define or directive not defined: \'`MemDataBus\'\n    input  wire [`MemDataBus] gpio_data_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire               gpio_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemDataBus] rmem_data_o\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:18: Define or directive not defined: \'`MemDataBus\'\n    output wire [`MemDataBus] rmem_data_o\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:24: Define or directive not defined: \'`MEM_DATA_W\'\n    assign rmem_data_o = {`MEM_DATA_W{ram_en_o }} & ram_data_i |\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/biu.v:25: Define or directive not defined: \'`MEM_DATA_W\'\n                         {`MEM_DATA_W{gpio_en_o}} & gpio_data_i;\n                          ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module biu (
    input  wire [`MemAddrBus] mem_addr_i,
    input  wire [   `WordBus] wmem_data_i,
    input  wire [`MemDataBus] ram_data_i,
    input  wire [`MemDataBus] gpio_data_i,

    output wire               ram_en_o,
    output wire               gpio_en_o,
    output wire [`MemDataBus] rmem_data_o
);

    assign ram_en_o  = mem_addr_i[31:29] == 3'b001;
    assign gpio_en_o = mem_addr_i[31:29] == 3'b010;

    assign rmem_data_o = {`MEM_DATA_W{ram_en_o }} & ram_data_i |
                         {`MEM_DATA_W{gpio_en_o}} & gpio_data_i;

    assign wmem_data_o = wmem_data_i;

endmodule
module biu (
    input  wire [`MemAddrBus] mem_addr_i,
    input  wire [   `WordBus] wmem_data_i,
    input  wire [`MemDataBus] ram_data_i,
    input  wire [`MemDataBus] gpio_data_i,

    output wire               ram_en_o,
    output wire               gpio_en_o,
    output wire [`MemDataBus] rmem_data_o
);


    assign ram_en_o  = mem_addr_i[31:29] == 3'b001;
    assign gpio_en_o = mem_addr_i[31:29] == 3'b010;

    assign rmem_data_o = {`MEM_DATA_W{ram_en_o }} & ram_data_i |
                         {`MEM_DATA_W{gpio_en_o}} & gpio_data_i;

    assign wmem_data_o = wmem_data_i;

endmodule