data/full_repos/permissive/510695465/Processor.v
1: b"%Error: data/full_repos/permissive/510695465/Processor.v:40: Cannot find file containing module: 'InstructionFetch'\nInstructionFetch IF(Clk,Reset,PCout,PC,Instruction_Code);\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/510695465,data/full_repos/permissive/510695465/InstructionFetch\n             data/full_repos/permissive/510695465,data/full_repos/permissive/510695465/InstructionFetch.v\n             data/full_repos/permissive/510695465,data/full_repos/permissive/510695465/InstructionFetch.sv\n             InstructionFetch\n             InstructionFetch.v\n             InstructionFetch.sv\n             obj_dir/InstructionFetch\n             obj_dir/InstructionFetch.v\n             obj_dir/InstructionFetch.sv\n%Error: data/full_repos/permissive/510695465/Processor.v:43: Cannot find file containing module: 'Add8bit'\nAdd8bit ADD1(PC,8'b0000_0001,PCplus1);\n^~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:44: Cannot find file containing module: 'Add8bit'\nAdd8bit ADD2(PC_IF_ID,extended,PCpluslabel);\n^~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:45: Cannot find file containing module: 'Mux'\nMux M1(PCplus1,PCpluslabel,jump,PCout);\n^~~\n%Error: data/full_repos/permissive/510695465/Processor.v:51: Cannot find file containing module: 'IF_ID_reg'\nIF_ID_reg pipreg1(Clk,Reset,flush,Instruction_Code,PC,instrCode_IF_ID,PC_IF_ID);\n^~~~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:61: Cannot find file containing module: 'RegisterFile'\nRegisterFile RF(Rs1,Rs2,Rd_EX_WB,ALUresult_EX_WB,\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:65: Cannot find file containing module: 'ControlUnit'\nControlUnit CU(opcode,ALUctrl,ALUsrc,RegWrite,jump,ImmSel);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:68: Cannot find file containing module: 'ID_EX_reg'\nID_EX_reg pipreg2(Clk,Reset,Read_Data_1,Read_Data_2,extended,Rd,Rs1,\n^~~~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:75: Cannot find file containing module: 'ForwardingUnit'\nForwardingUnit FU(Rs1_ID_EX,Rd_EX_WB,RegWrite_EX_WB,Forward);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:77: Cannot find file containing module: 'Mux'\nMux M2(Data2_ID_EX,extended_ID_EX,ALUsrc_ID_EX,Data_2);  \n^~~\n%Error: data/full_repos/permissive/510695465/Processor.v:78: Cannot find file containing module: 'Mux'\nMux M3(Data1_ID_EX,ALUresult_EX_WB,Forward,Data_1);  \n^~~\n%Error: data/full_repos/permissive/510695465/Processor.v:81: Cannot find file containing module: 'ALU'\nALU ALU1(Data_1,Data_2,ALUctrl_ID_EX,ALU_result,Zero);\n^~~\n%Error: data/full_repos/permissive/510695465/Processor.v:84: Cannot find file containing module: 'ImmGen'\nImmGen IG(instrCode_IF_ID,ImmSel,extended);\n^~~~~~\n%Error: data/full_repos/permissive/510695465/Processor.v:87: Cannot find file containing module: 'EX_WB_reg'\nEX_WB_reg pipreg3(Clk,Reset,RegWrite_ID_EX,ALU_result,Rd_ID_EX,\n^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module Processor(input Clk, input Reset);

wire [7:0] Instruction_Code,ALU_result,Read_Data_1,Read_Data_2;
wire [7:0] PC,PCout,PCplus1,PCpluslabel;
wire [7:0] extended,Data_1,Data_2;
wire ALUctrl,jump,ImmSel,ALUsrc,RegWrite,Zero;

wire [7:0] instrCode_IF_ID,PC_IF_ID;

wire [2:0] Rd_ID_EX,Rs1_ID_EX;
wire RegWrite_ID_EX,ALUctrl_ID_EX,ALUsrc_ID_EX,jump_ID_EX;
wire [7:0] PC_ID_EX,Data1_ID_EX,Data2_ID_EX,extended_ID_EX;

wire [2:0] Rd_EX_WB;
wire RegWrite_EX_WB;
wire [7:0] PCpluslabel_EX_WB,ALUresult_EX_WB;

InstructionFetch IF(Clk,Reset,PCout,PC,Instruction_Code);


Add8bit ADD1(PC,8'b0000_0001,PCplus1);
Add8bit ADD2(PC_IF_ID,extended,PCpluslabel);
Mux M1(PCplus1,PCpluslabel,jump,PCout);


wire flush;
assign flush = jump;

IF_ID_reg pipreg1(Clk,Reset,flush,Instruction_Code,PC,instrCode_IF_ID,PC_IF_ID);

wire [2:0]Rd,Rs1,Rs2;
wire [1:0]opcode;
assign Rs1 = instrCode_IF_ID[5:3];
assign Rs2 = instrCode_IF_ID[5:3];
assign Rd = instrCode_IF_ID[5:3];
assign opcode = instrCode_IF_ID[7:6];


RegisterFile RF(Rs1,Rs2,Rd_EX_WB,ALUresult_EX_WB,
                Read_Data_1,Read_Data_2,RegWrite_EX_WB,Clk,Reset);


ControlUnit CU(opcode,ALUctrl,ALUsrc,RegWrite,jump,ImmSel);


ID_EX_reg pipreg2(Clk,Reset,Read_Data_1,Read_Data_2,extended,Rd,Rs1,
            RegWrite,ALUctrl,ALUsrc,jump,
            Data1_ID_EX,Data2_ID_EX,extended_ID_EX,Rd_ID_EX,Rs1_ID_EX,
            RegWrite_ID_EX,ALUctrl_ID_EX,ALUsrc_ID_EX,jump_ID_EX);


wire Forward;
ForwardingUnit FU(Rs1_ID_EX,Rd_EX_WB,RegWrite_EX_WB,Forward);

Mux M2(Data2_ID_EX,extended_ID_EX,ALUsrc_ID_EX,Data_2);
Mux M3(Data1_ID_EX,ALUresult_EX_WB,Forward,Data_1);


ALU ALU1(Data_1,Data_2,ALUctrl_ID_EX,ALU_result,Zero);


ImmGen IG(instrCode_IF_ID,ImmSel,extended);


EX_WB_reg pipreg3(Clk,Reset,RegWrite_ID_EX,ALU_result,Rd_ID_EX,
                    RegWrite_EX_WB,ALUresult_EX_WB,Rd_EX_WB);
endmodule
module Processor(input Clk, input Reset);


wire [7:0] Instruction_Code,ALU_result,Read_Data_1,Read_Data_2;
wire [7:0] PC,PCout,PCplus1,PCpluslabel;
wire [7:0] extended,Data_1,Data_2;
wire ALUctrl,jump,ImmSel,ALUsrc,RegWrite,Zero;

wire [7:0] instrCode_IF_ID,PC_IF_ID;

wire [2:0] Rd_ID_EX,Rs1_ID_EX;
wire RegWrite_ID_EX,ALUctrl_ID_EX,ALUsrc_ID_EX,jump_ID_EX;
wire [7:0] PC_ID_EX,Data1_ID_EX,Data2_ID_EX,extended_ID_EX;

wire [2:0] Rd_EX_WB;
wire RegWrite_EX_WB;
wire [7:0] PCpluslabel_EX_WB,ALUresult_EX_WB;

InstructionFetch IF(Clk,Reset,PCout,PC,Instruction_Code);


Add8bit ADD1(PC,8'b0000_0001,PCplus1);
Add8bit ADD2(PC_IF_ID,extended,PCpluslabel);
Mux M1(PCplus1,PCpluslabel,jump,PCout);


wire flush;
assign flush = jump;

IF_ID_reg pipreg1(Clk,Reset,flush,Instruction_Code,PC,instrCode_IF_ID,PC_IF_ID);

wire [2:0]Rd,Rs1,Rs2;
wire [1:0]opcode;
assign Rs1 = instrCode_IF_ID[5:3];
assign Rs2 = instrCode_IF_ID[5:3];
assign Rd = instrCode_IF_ID[5:3];
assign opcode = instrCode_IF_ID[7:6];


RegisterFile RF(Rs1,Rs2,Rd_EX_WB,ALUresult_EX_WB,
                Read_Data_1,Read_Data_2,RegWrite_EX_WB,Clk,Reset);


ControlUnit CU(opcode,ALUctrl,ALUsrc,RegWrite,jump,ImmSel);


ID_EX_reg pipreg2(Clk,Reset,Read_Data_1,Read_Data_2,extended,Rd,Rs1,
            RegWrite,ALUctrl,ALUsrc,jump,
            Data1_ID_EX,Data2_ID_EX,extended_ID_EX,Rd_ID_EX,Rs1_ID_EX,
            RegWrite_ID_EX,ALUctrl_ID_EX,ALUsrc_ID_EX,jump_ID_EX);


wire Forward;
ForwardingUnit FU(Rs1_ID_EX,Rd_EX_WB,RegWrite_EX_WB,Forward);

Mux M2(Data2_ID_EX,extended_ID_EX,ALUsrc_ID_EX,Data_2);
Mux M3(Data1_ID_EX,ALUresult_EX_WB,Forward,Data_1);


ALU ALU1(Data_1,Data_2,ALUctrl_ID_EX,ALU_result,Zero);


ImmGen IG(instrCode_IF_ID,ImmSel,extended);


EX_WB_reg pipreg3(Clk,Reset,RegWrite_ID_EX,ALU_result,Rd_ID_EX,
                    RegWrite_EX_WB,ALUresult_EX_WB,Rd_EX_WB);
endmodule