data/full_repos/permissive/41404488/verilog/snes_bus_sync.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:111: Unsupported: Ignoring delay on this delayed statement.\nalways #14.3 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:112: Unsupported: Ignoring delay on this delayed statement.\nalways #139.6 cycle_clk = ~cycle_clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:113: Unsupported: Ignoring delay on this delayed statement.\ninitial #1000 rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:118: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:119: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:120: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:121: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:122: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:125: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:126: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:127: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:128: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:129: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:116: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n if (PARD_n) PARD_n = $random % 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:118: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:119: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:120: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:121: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:122: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:125: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:126: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:127: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:128: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:129: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Error: Exiting due to 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module snes_bus_sync (
	input        clk,
	input        rst_n,
	input  [7:0] PA,
	output       event_latch
);

	parameter OUT_OF_SYNC = 1'b1;
	parameter IN_SYNC     = 1'b0;

	reg [7:0]  PA_store [0:1];
	reg        sync_state = IN_SYNC;

	reg bus_latch = 0;


	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			PA_store[0] <= 8'b0;
			PA_store[1] <= 8'b0;
			bus_latch   <= 1'b0;
			sync_state  <= IN_SYNC;
		end
		else begin
			PA_store[0] <= PA;
			PA_store[1] <= PA_store[0];
			if (sync_state == IN_SYNC) begin


				if (((PA != PA_store[0]) || (PA_store[1] != PA_store[0]))) begin
					sync_state <= OUT_OF_SYNC;
					bus_latch <= 0;
				end
			end else if (sync_state == OUT_OF_SYNC) begin
				bus_latch  <= 0;

				if ((PA == PA_store[0]) && (PA_store[1] == PA_store[0])) begin
					bus_latch <= 1;
					sync_state <= IN_SYNC;
				end
			end
		end
	end
	

	assign event_latch    = bus_latch;

endmodule
module snes_bus_sync (
	input        clk,
	input        rst_n,
	input  [7:0] PA,
	output       event_latch
);


	parameter OUT_OF_SYNC = 1'b1;
	parameter IN_SYNC     = 1'b0;

	reg [7:0]  PA_store [0:1];
	reg        sync_state = IN_SYNC;

	reg bus_latch = 0;


	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			PA_store[0] <= 8'b0;
			PA_store[1] <= 8'b0;
			bus_latch   <= 1'b0;
			sync_state  <= IN_SYNC;
		end
		else begin
			PA_store[0] <= PA;
			PA_store[1] <= PA_store[0];
			if (sync_state == IN_SYNC) begin


				if (((PA != PA_store[0]) || (PA_store[1] != PA_store[0]))) begin
					sync_state <= OUT_OF_SYNC;
					bus_latch <= 0;
				end
			end else if (sync_state == OUT_OF_SYNC) begin
				bus_latch  <= 0;

				if ((PA == PA_store[0]) && (PA_store[1] == PA_store[0])) begin
					bus_latch <= 1;
					sync_state <= IN_SYNC;
				end
			end
		end
	end
	

	assign event_latch    = bus_latch;

endmodule