data/full_repos/permissive/451970862/rtl/bus/sb_2m1s.v
data/verilator_xmls/c23d9b3c-8c77-45cf-a38d-181562ff6d13.xml
module sb_2m1s (
input           clk,
input           rst_n,




input           sb_arvalid_m0,
output          sb_arready_m0,
input   [31:0]  sb_araddr_m0,

output          sb_rvalid_m0,
input           sb_rready_m0,
output   [31:0] sb_rdata_m0,

input           sb_wvalid_m0,
output          sb_wready_m0,
input   [31:0]  sb_waddr_m0,
input   [31:0]  sb_wdata_m0,
input   [3:0]   sb_wstrb_m0,

output          sb_bvalid_m0,
input           sb_bready_m0,
output          sb_bresp_m0,




input           sb_arvalid_m1,
output          sb_arready_m1,
input   [31:0]  sb_araddr_m1,

output          sb_rvalid_m1,
input           sb_rready_m1,
output   [31:0] sb_rdata_m1,

input           sb_wvalid_m1,
output          sb_wready_m1,
input   [31:0]  sb_waddr_m1,
input   [31:0]  sb_wdata_m1,
input   [3:0]   sb_wstrb_m1,

output          sb_bvalid_m1,
input           sb_bready_m1,
output          sb_bresp_m1,




output          sb_arvalid_s0,
input           sb_arready_s0,
output  [31:0]  sb_araddr_s0,

input           sb_rvalid_s0,
output          sb_rready_s0,
input   [31:0]  sb_rdata_s0,

output          sb_wvalid_s0,
input           sb_wready_s0,
output  [31:0]  sb_waddr_s0,
output  [31:0]  sb_wdata_s0,
output  [3:0]   sb_wstrb_s0,

input           sb_bvalid_s0,
output          sb_bready_s0,
input           sb_bresp_s0

);

reg       arflag;
reg       armst;
wire      ar_ok;
wire      r_ok;

assign    ar_ok = sb_arvalid_s0 & sb_arready_s0;
assign    r_ok  = sb_rvalid_s0  & sb_rready_s0;

always @ (posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    arflag  <=  1'b0;
    armst   <=  1'b0;
  end





  else if(~arflag & ar_ok & ~r_ok) begin

    arflag  <=  1'b1;
    armst   <=  sb_arvalid_m1;
  end















  else if(arflag & ~ar_ok & r_ok) begin

    arflag  <=  1'b0;

  end





  else if(arflag & ar_ok & r_ok) begin


    armst   <=  sb_arvalid_m1;
  end
end

assign    sb_arvalid_s0   = (arflag & ~r_ok) ? 1'b0 : sb_arvalid_m1 ? sb_arvalid_m1 : sb_arvalid_m0;
assign    sb_araddr_s0    = sb_arvalid_m1 ? sb_araddr_m1  : sb_araddr_m0;
assign    sb_arready_m0   = (arflag & ~r_ok) ? 1'b0 : sb_arvalid_m1 ? 1'b0 : sb_arready_s0;
assign    sb_arready_m1   = (arflag & ~r_ok) ? 1'b0 : sb_arready_s0;

assign    sb_rvalid_m0       = armst ? 1'b0          : sb_rvalid_s0;
assign    sb_rvalid_m1       = armst ? sb_rvalid_s0  : 1'b0;
assign    sb_rready_s0       = armst ? sb_rready_m1  : sb_rready_m0;
assign    sb_rdata_m0        = sb_rdata_s0;
assign    sb_rdata_m1        = sb_rdata_s0;



reg       wflag;
reg       wmst;
wire      w_ok;
wire      b_ok;

assign    w_ok  = sb_wvalid_s0 & sb_wready_s0;
assign    b_ok  = sb_bvalid_s0 & sb_bready_s0;

always @ (posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    wflag  <=  1'b0;
    wmst   <=  1'b0;
  end





  else if(~wflag & w_ok & ~b_ok) begin

    wflag  <=  1'b1;
    wmst   <=  sb_wvalid_m1;
  end















  else if(wflag & ~w_ok & b_ok) begin

    wflag  <=  1'b0;

  end





  else if(wflag & w_ok & b_ok) begin


    wmst   <=  sb_wvalid_m1;
  end
end

assign    sb_wvalid_s0   = (wflag & ~b_ok) ? 1'b0 : sb_wvalid_m1 ? sb_wvalid_m1 : sb_wvalid_m0;
assign    sb_waddr_s0    = sb_wvalid_m1 ? sb_waddr_m1  : sb_waddr_m0;
assign    sb_wdata_s0    = sb_wvalid_m1 ? sb_wdata_m1  : sb_wdata_m0;
assign    sb_wstrb_s0    = sb_wvalid_m1 ? sb_wstrb_m1  : sb_wstrb_m0;
assign    sb_wready_m0   = (wflag & ~b_ok) ? 1'b0 : sb_wvalid_m1 ? 1'b0 : sb_wready_s0;
assign    sb_wready_m1   = (wflag & ~b_ok) ? 1'b0 : sb_wready_s0;

assign    sb_bvalid_m0       = wmst ? 1'b0          : sb_bvalid_s0;
assign    sb_bvalid_m1       = wmst ? sb_bvalid_s0  : 1'b0;
assign    sb_bready_s0       = wmst ? sb_bready_m1  : sb_bready_m0;
assign    sb_bresp_m0        = sb_bresp_s0;
assign    sb_bresp_m1        = sb_bresp_s0;

endmodule
module sb_2m1s (
input           clk,
input           rst_n,




input           sb_arvalid_m0,
output          sb_arready_m0,
input   [31:0]  sb_araddr_m0,

output          sb_rvalid_m0,
input           sb_rready_m0,
output   [31:0] sb_rdata_m0,

input           sb_wvalid_m0,
output          sb_wready_m0,
input   [31:0]  sb_waddr_m0,
input   [31:0]  sb_wdata_m0,
input   [3:0]   sb_wstrb_m0,

output          sb_bvalid_m0,
input           sb_bready_m0,
output          sb_bresp_m0,




input           sb_arvalid_m1,
output          sb_arready_m1,
input   [31:0]  sb_araddr_m1,

output          sb_rvalid_m1,
input           sb_rready_m1,
output   [31:0] sb_rdata_m1,

input           sb_wvalid_m1,
output          sb_wready_m1,
input   [31:0]  sb_waddr_m1,
input   [31:0]  sb_wdata_m1,
input   [3:0]   sb_wstrb_m1,

output          sb_bvalid_m1,
input           sb_bready_m1,
output          sb_bresp_m1,




output          sb_arvalid_s0,
input           sb_arready_s0,
output  [31:0]  sb_araddr_s0,

input           sb_rvalid_s0,
output          sb_rready_s0,
input   [31:0]  sb_rdata_s0,

output          sb_wvalid_s0,
input           sb_wready_s0,
output  [31:0]  sb_waddr_s0,
output  [31:0]  sb_wdata_s0,
output  [3:0]   sb_wstrb_s0,

input           sb_bvalid_s0,
output          sb_bready_s0,
input           sb_bresp_s0

);


reg       arflag;
reg       armst;
wire      ar_ok;
wire      r_ok;

assign    ar_ok = sb_arvalid_s0 & sb_arready_s0;
assign    r_ok  = sb_rvalid_s0  & sb_rready_s0;

always @ (posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    arflag  <=  1'b0;
    armst   <=  1'b0;
  end





  else if(~arflag & ar_ok & ~r_ok) begin

    arflag  <=  1'b1;
    armst   <=  sb_arvalid_m1;
  end















  else if(arflag & ~ar_ok & r_ok) begin

    arflag  <=  1'b0;

  end





  else if(arflag & ar_ok & r_ok) begin


    armst   <=  sb_arvalid_m1;
  end
end

assign    sb_arvalid_s0   = (arflag & ~r_ok) ? 1'b0 : sb_arvalid_m1 ? sb_arvalid_m1 : sb_arvalid_m0;
assign    sb_araddr_s0    = sb_arvalid_m1 ? sb_araddr_m1  : sb_araddr_m0;
assign    sb_arready_m0   = (arflag & ~r_ok) ? 1'b0 : sb_arvalid_m1 ? 1'b0 : sb_arready_s0;
assign    sb_arready_m1   = (arflag & ~r_ok) ? 1'b0 : sb_arready_s0;

assign    sb_rvalid_m0       = armst ? 1'b0          : sb_rvalid_s0;
assign    sb_rvalid_m1       = armst ? sb_rvalid_s0  : 1'b0;
assign    sb_rready_s0       = armst ? sb_rready_m1  : sb_rready_m0;
assign    sb_rdata_m0        = sb_rdata_s0;
assign    sb_rdata_m1        = sb_rdata_s0;



reg       wflag;
reg       wmst;
wire      w_ok;
wire      b_ok;

assign    w_ok  = sb_wvalid_s0 & sb_wready_s0;
assign    b_ok  = sb_bvalid_s0 & sb_bready_s0;

always @ (posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    wflag  <=  1'b0;
    wmst   <=  1'b0;
  end





  else if(~wflag & w_ok & ~b_ok) begin

    wflag  <=  1'b1;
    wmst   <=  sb_wvalid_m1;
  end















  else if(wflag & ~w_ok & b_ok) begin

    wflag  <=  1'b0;

  end





  else if(wflag & w_ok & b_ok) begin


    wmst   <=  sb_wvalid_m1;
  end
end

assign    sb_wvalid_s0   = (wflag & ~b_ok) ? 1'b0 : sb_wvalid_m1 ? sb_wvalid_m1 : sb_wvalid_m0;
assign    sb_waddr_s0    = sb_wvalid_m1 ? sb_waddr_m1  : sb_waddr_m0;
assign    sb_wdata_s0    = sb_wvalid_m1 ? sb_wdata_m1  : sb_wdata_m0;
assign    sb_wstrb_s0    = sb_wvalid_m1 ? sb_wstrb_m1  : sb_wstrb_m0;
assign    sb_wready_m0   = (wflag & ~b_ok) ? 1'b0 : sb_wvalid_m1 ? 1'b0 : sb_wready_s0;
assign    sb_wready_m1   = (wflag & ~b_ok) ? 1'b0 : sb_wready_s0;

assign    sb_bvalid_m0       = wmst ? 1'b0          : sb_bvalid_s0;
assign    sb_bvalid_m1       = wmst ? sb_bvalid_s0  : 1'b0;
assign    sb_bready_s0       = wmst ? sb_bready_m1  : sb_bready_m0;
assign    sb_bresp_m0        = sb_bresp_s0;
assign    sb_bresp_m1        = sb_bresp_s0;

endmodule