data/full_repos/permissive/447283927/adress_generator.v
data/verilator_xmls/e1aed882-34de-4183-90e1-b0559f964349.xml
module address_generator (output reg [31:0] pc, input beq, input zero_flag, input [31:0] branch_pc, input clk, input rst, input Stall, input addressSrc, input [31:0] isrAddress);	
    initial
    begin
        pc = 0;
    end
    always @(posedge clk)
    begin
        if (rst)
        begin
            pc <= 0;
        end
        else 
        begin
        if (Stall)
        begin
        end
        else
        begin
                if (addressSrc)
                begin
                    pc <= isrAddress;
                end
                else if (beq && zero_flag)
                begin
                    pc <= branch_pc;
                end
                else
                begin
                    pc <= pc+4;
                end
        end
        end
    end 
endmodule
module address_generator (output reg [31:0] pc, input beq, input zero_flag, input [31:0] branch_pc, input clk, input rst, input Stall, input addressSrc, input [31:0] isrAddress);
	
    initial
    begin
        pc = 0;
    end
    always @(posedge clk)
    begin
        if (rst)
        begin
            pc <= 0;
        end
        else 
        begin
        if (Stall)
        begin
        end
        else
        begin
                if (addressSrc)
                begin
                    pc <= isrAddress;
                end
                else if (beq && zero_flag)
                begin
                    pc <= branch_pc;
                end
                else
                begin
                    pc <= pc+4;
                end
        end
        end
    end 
endmodule