data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v
1: b'%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:18: Cannot find include file: mikroislem.vh\n`include "mikroislem.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh.v\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/mikroislem.vh.sv\n             mikroislem.vh\n             mikroislem.vh.v\n             mikroislem.vh.sv\n             obj_dir/mikroislem.vh\n             obj_dir/mikroislem.vh.v\n             obj_dir/mikroislem.vh.sv\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:37: Define or directive not defined: \'`JAL\'\n            `JAL: begin\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:37: syntax error, unexpected \':\', expecting endcase\n            `JAL: begin\n                ^\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:41: Define or directive not defined: \'`JALR\'\n            `JALR: begin\n            ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:41: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `JALR: begin\n                   ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:48: Define or directive not defined: \'`BEQ\'\n            `BEQ: begin\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:48: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BEQ: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:52: Define or directive not defined: \'`BNE\'\n            `BNE: begin\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:52: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BNE: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:56: Define or directive not defined: \'`BLT\'\n            `BLT: begin\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:56: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BLT: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:60: Define or directive not defined: \'`BLTU\'\n            `BLTU: begin\n            ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:60: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BLTU: begin\n                   ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:64: Define or directive not defined: \'`BGE\'\n            `BGE: begin\n            ^~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:64: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BGE: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:68: Define or directive not defined: \'`BGEU\'\n            `BGEU: begin\n            ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:68: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BGEU: begin\n                   ^~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/dallanma_birimi.v:72: syntax error, unexpected endcase\n        endcase\n        ^~~~~~~\n%Error: Cannot continue\n'
module dallanma_birimi(
    input         [7:0]     islev_kodu_g                                   ,
    input         [31:0]    ps_g                                           ,
    input         [31:0]    islec1_g                                       ,
    input         [31:0]    islec2_g                                       ,
    input         [31:0]    anlik_g                                        ,
    output reg    [31:0]    jal_sonuc_c                                    ,
    output reg              dallanma_sonuc_c                               ,
    output reg    [31:0]    ps_c
    );
    
    always@* begin
        ps_c              = 0        ;
        dallanma_sonuc_c  = 0        ;
        jal_sonuc_c       = 0        ;
        case(islev_kodu_g)
            `JAL: begin
                jal_sonuc_c = ps_g + 3'b100                                ;
                ps_c        = ps_g + $signed(islec2_g)                     ; 
            end
            `JALR: begin


                jal_sonuc_c      = ps_g + 3'b100; 

                ps_c             =  ($signed(islec1_g) +  $signed(islec2_g)) & -2 ;
            end
            `BEQ: begin
                dallanma_sonuc_c =  $signed(islec1_g) ==  $signed(islec2_g);
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BNE: begin
                dallanma_sonuc_c =  $signed(islec1_g) != $signed(islec2_g) ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BLT: begin
                dallanma_sonuc_c = ($signed(islec1_g) < $signed(islec2_g)) ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BLTU: begin
                dallanma_sonuc_c =  islec1_g < islec2_g                    ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BGE: begin
                dallanma_sonuc_c = ($signed(islec1_g) >= $signed(islec2_g)); 
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BGEU: begin
                dallanma_sonuc_c =  islec1_g >= islec2_g                   ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
        endcase

    end
endmodule
module dallanma_birimi(
    input         [7:0]     islev_kodu_g                                   ,
    input         [31:0]    ps_g                                           ,
    input         [31:0]    islec1_g                                       ,
    input         [31:0]    islec2_g                                       ,
    input         [31:0]    anlik_g                                        ,
    output reg    [31:0]    jal_sonuc_c                                    ,
    output reg              dallanma_sonuc_c                               ,
    output reg    [31:0]    ps_c
    );

    
    always@* begin
        ps_c              = 0        ;
        dallanma_sonuc_c  = 0        ;
        jal_sonuc_c       = 0        ;
        case(islev_kodu_g)
            `JAL: begin
                jal_sonuc_c = ps_g + 3'b100                                ;
                ps_c        = ps_g + $signed(islec2_g)                     ; 
            end
            `JALR: begin


                jal_sonuc_c      = ps_g + 3'b100; 

                ps_c             =  ($signed(islec1_g) +  $signed(islec2_g)) & -2 ;
            end
            `BEQ: begin
                dallanma_sonuc_c =  $signed(islec1_g) ==  $signed(islec2_g);
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BNE: begin
                dallanma_sonuc_c =  $signed(islec1_g) != $signed(islec2_g) ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BLT: begin
                dallanma_sonuc_c = ($signed(islec1_g) < $signed(islec2_g)) ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BLTU: begin
                dallanma_sonuc_c =  islec1_g < islec2_g                    ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BGE: begin
                dallanma_sonuc_c = ($signed(islec1_g) >= $signed(islec2_g)); 
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
            `BGEU: begin
                dallanma_sonuc_c =  islec1_g >= islec2_g                   ;
                ps_c             = ps_g +  $signed(anlik_g)                ;
            end 
        endcase

    end
endmodule