data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_table_double.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_table_double.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_table_double.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module tcam_table_double
#(
   parameter   C_S_AXI_DATA_WIDTH   = 32,
   parameter   TCAM_ADDR_WIDTH      = 4,
   parameter   TCAM_DATA_WIDTH      = 32,

   parameter   TCAM_DUMMY_ENTRY     = 32'hace0_face
)
(
   input                                     axi_aclk,
   input                                     axi_resetn,


   input                                     tcam_entry_en,

   input          [TCAM_DATA_WIDTH-1:0]      tcam_entry,
   
   input                                     tcam_sel,
   input                                     flow_buffer_sel,


   input          [1:0]                      tcam_wr_ctrl,
   output                                    tcam_status,

   input          [TCAM_ADDR_WIDTH-1:0]      tcam_addr_wr,
   input                                     tcam_wren,
   input          [TCAM_DATA_WIDTH-1:0]      tcam_din,
   input          [TCAM_DATA_WIDTH-1:0]      tcam_din_mask,
   output                                    tcam_busy,

   output                                    tcam_hit,
   output                                    tcam_miss,
   output         [TCAM_ADDR_WIDTH-1:0]      tcam_match_result,
   output                                    tcam_match_en,

   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_hit_total,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_miss_total,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_total,

   input                                     tcam_flow_stat_clr,

   input          [TCAM_ADDR_WIDTH-1:0]      tcam_stat_addr_rd,
   input                                     tcam_stat_rden,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_stat_data_rd,

   input                                     tcam_stat_clr
);

wire  tcam_wren_0, tcam_busy_0, tcam_match_0;
wire  [TCAM_ADDR_WIDTH-1:0]   tcam_wr_addr_0, tcam_result_0;
wire  [TCAM_DATA_WIDTH-1:0]   tcam_wr_din_0, tcam_wr_din_mask_0, tcam_cmp_0;

wire  tcam_wren_1, tcam_busy_1, tcam_match_1;
wire  [TCAM_ADDR_WIDTH-1:0]   tcam_wr_addr_1, tcam_result_1;
wire  [TCAM_DATA_WIDTH-1:0]   tcam_wr_din_1, tcam_wr_din_mask_1, tcam_cmp_1;

assign tcam_busy = tcam_busy_0 | tcam_busy_1;

reg   r_tcam_sel;
always @(posedge axi_aclk)
   if (~axi_resetn)
      r_tcam_sel <= 0;
   else if (tcam_entry_en)
      r_tcam_sel <= tcam_sel;

wire  w_tcam_sel = (tcam_entry_en) ? tcam_sel : r_tcam_sel;


assign tcam_status = (tcam_wr_ctrl == 1) ? 0 :
                     (tcam_wr_ctrl == 2) ? 1 : flow_buffer_sel;


reg   [2:0] r_tcam_entry_en;
always @(posedge  axi_aclk)
   if (~axi_resetn) begin
      r_tcam_entry_en   <= 0;
   end
   else begin
      r_tcam_entry_en   <= {r_tcam_entry_en[1:0], tcam_entry_en};
   end

reg   [2:0] r_tcam_sel_d;
always @(posedge  axi_aclk)
   if (~axi_resetn) begin
      r_tcam_sel_d   <= 0;
   end
   else begin
      r_tcam_sel_d   <= {r_tcam_sel_d[1:0], w_tcam_sel};
   end


assign tcam_wren_0 = (tcam_wr_ctrl != 0) ? tcam_wr_ctrl[0] & tcam_wren :
                     (flow_buffer_sel == 1)   ? tcam_wren : 0;
assign tcam_wr_addr_0 = (tcam_wr_ctrl == 1 || flow_buffer_sel == 1) ? tcam_addr_wr : 0;
assign tcam_wr_din_0 = (tcam_wr_ctrl == 1 || flow_buffer_sel == 1) ? tcam_din : 0;

assign tcam_cmp_0 = (tcam_entry_en & tcam_wr_ctrl == 1) ? tcam_entry : 
                    (tcam_entry_en & tcam_wr_ctrl == 2) ? TCAM_DUMMY_ENTRY : 
                    (tcam_entry_en & w_tcam_sel == 0)   ? tcam_entry : TCAM_DUMMY_ENTRY;

`ifdef TCAM_MULTI
tcam_multi_wrapper
`else
tcam_module
`endif
#(
   .TCAM_ADDR_WIDTH  (  TCAM_ADDR_WIDTH         ),
   .TCAM_DATA_WIDTH  (  TCAM_DATA_WIDTH         )
)
tcam_table_0 (
   .CLK              (  axi_aclk                ),
   .RSTN             (  axi_resetn              ),
   .WR               (  tcam_wren_0             ), 
   .ADDR_WR          (  tcam_wr_addr_0          ),
   .DIN              (  tcam_wr_din_0           ), 
   .DIN_MASK         (  {TCAM_DATA_WIDTH{1'b0}} ), 
   .BUSY             (  tcam_busy_0          ), 
`ifdef EN_TCAM_RD
   .RD               (                          ),  
   .ADDR_RD          (  0                       ),
   .DOUT             (                          ),
`endif
   .CAM_DIN          (  tcam_cmp_0              ),
   .CAM_DATA_MASK    (  {TCAM_DATA_WIDTH{1'b0}} ),
   .MATCH            (  tcam_match_0            ),
   .MATCH_ADDR       (  tcam_result_0           )
);


assign tcam_wren_1 = (tcam_wr_ctrl != 0) ? tcam_wr_ctrl[1] & tcam_wren :
                     (flow_buffer_sel == 0) ? tcam_wren : 0;
assign tcam_wr_addr_1 = (tcam_wr_ctrl == 2 || flow_buffer_sel == 0) ? tcam_addr_wr : 0;
assign tcam_wr_din_1 = (tcam_wr_ctrl == 2 || flow_buffer_sel == 0) ? tcam_din : 0;

assign tcam_cmp_1 = (tcam_entry_en & tcam_wr_ctrl == 2) ? tcam_entry :
                    (tcam_entry_en & tcam_wr_ctrl == 1) ? TCAM_DUMMY_ENTRY :
                    (tcam_entry_en & w_tcam_sel == 1)   ? tcam_entry : TCAM_DUMMY_ENTRY;

`ifdef TCAM_MULTI
tcam_multi_wrapper
`else
tcam_module
`endif
#(
   .TCAM_ADDR_WIDTH  (  TCAM_ADDR_WIDTH         ),
   .TCAM_DATA_WIDTH  (  TCAM_DATA_WIDTH         )
)
tcam_table_1 (
   .CLK              (  axi_aclk                ),
   .RSTN             (  axi_resetn              ),
   .WR               (  tcam_wren_1             ), 
   .ADDR_WR          (  tcam_wr_addr_1          ),
   .DIN              (  tcam_wr_din_1           ), 
   .DIN_MASK         (  {TCAM_DATA_WIDTH{1'b0}} ), 
   .BUSY             (  tcam_busy_1          ), 
`ifdef EN_TCAM_RD
   .RD               (                          ),  
   .ADDR_RD          (  0                       ),
   .DOUT             (                          ),
`endif
   .CAM_DIN          (  tcam_cmp_1              ),
   .CAM_DATA_MASK    (  {TCAM_DATA_WIDTH{1'b0}} ),
   .MATCH            (  tcam_match_1            ),
   .MATCH_ADDR       (  tcam_result_1           )
);


assign tcam_hit = (r_tcam_entry_en[2]) ? (tcam_wr_ctrl == 1)    ? tcam_match_0 :
                                         (tcam_wr_ctrl == 2)    ? tcam_match_1 :
                                         (r_tcam_sel_d[2] == 0) ? tcam_match_0 : tcam_match_1 :
                                         0;
assign tcam_miss = (r_tcam_entry_en[2]) ? (tcam_wr_ctrl == 1)    ? ~tcam_match_0 :
                                          (tcam_wr_ctrl == 2)    ? ~tcam_match_1 :
                                          (r_tcam_sel_d[2] == 0) ? ~tcam_match_0 : ~tcam_match_1 :
                                          0;
assign tcam_match_result = (r_tcam_entry_en[2] & (tcam_match_0 | tcam_match_1)) ? (tcam_wr_ctrl == 1) ? tcam_result_0 :
                                                                                  (tcam_wr_ctrl == 2) ? tcam_result_1 :
                                                                                  (r_tcam_sel_d[2] == 0) ? tcam_result_0 : tcam_result_1 :
                                                                                  0;
assign tcam_match_en = r_tcam_entry_en[2];


always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_hit_total    <= 0;
      tcam_miss_total   <= 0;
      tcam_total        <= 0;
   end
   else if (tcam_flow_stat_clr) begin
      tcam_hit_total    <= 0;
      tcam_miss_total   <= 0;
      tcam_total        <= 0;
   end
   else if (r_tcam_entry_en[2]) begin
      tcam_hit_total    <= (tcam_hit) ? tcam_hit_total + 1 : tcam_hit_total;
      tcam_miss_total   <= (tcam_miss) ? tcam_miss_total + 1 : tcam_miss_total;
      tcam_total        <= tcam_total + 1;
   end



reg   [TCAM_ADDR_WIDTH-1:0]   stat_mem_clr_addr;
reg   stat_mem_clr_wr;

always @(posedge axi_aclk)
   if (~axi_resetn) begin
      stat_mem_clr_addr  <= 0;
      stat_mem_clr_wr    <= 0;
   end
   else if (stat_mem_clr_addr > 0) begin
      stat_mem_clr_addr  <= (stat_mem_clr_addr == (2**TCAM_ADDR_WIDTH-1)) ? 0 : stat_mem_clr_addr + 1;
      stat_mem_clr_wr    <= (stat_mem_clr_addr == (2**TCAM_ADDR_WIDTH-1)) ? 0 : 1;
   end
   else if (tcam_stat_clr) begin
      stat_mem_clr_addr  <= 1;
      stat_mem_clr_wr    <= 1;
   end

wire  [TCAM_ADDR_WIDTH-1:0]   tcam_stat_addr_wr_0, tcam_stat_addr_rd_0, tcam_stat_addr_rd_1;
wire  tcam_stat_wr_0, tcam_stat_rd_0;
wire  [C_S_AXI_DATA_WIDTH-1:0]   tcam_stat_data_wr_0, tcam_stat_data_rd_0, tcam_stat_data_rd_1;

assign tcam_stat_addr_rd_0 = tcam_match_result;
assign tcam_stat_rd_0 = tcam_hit;

assign tcam_stat_addr_rd_1 = tcam_stat_addr_rd;
assign tcam_stat_rd_1 = tcam_stat_rden;

reg   [TCAM_ADDR_WIDTH-1:0]  tcam_stat_addr_rd_0_d1, tcam_stat_addr_rd_0_d2;
reg   tcam_stat_rd_1_d, tcam_stat_wr_0_d1, tcam_stat_wr_0_d2;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_stat_addr_rd_0_d1  <= 0;
      tcam_stat_addr_rd_0_d2  <= 0;
      tcam_stat_wr_0_d1       <= 0;
      tcam_stat_wr_0_d2       <= 0;
      tcam_stat_rd_1_d        <= 0;
   end
   else begin
      tcam_stat_addr_rd_0_d1  <= tcam_stat_addr_rd_0;
      tcam_stat_addr_rd_0_d2  <= tcam_stat_addr_rd_0_d1;
      tcam_stat_wr_0_d1       <= tcam_hit;
      tcam_stat_wr_0_d2       <= tcam_stat_wr_0_d1;
      tcam_stat_rd_1_d        <= tcam_stat_rden;
   end

reg   [TCAM_DATA_WIDTH-1:0]   tcam_stat_data_rd_0_d;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_stat_data_rd_0_d <= 0;
   end
   else if (tcam_stat_wr_0_d1) begin
      tcam_stat_data_rd_0_d <= tcam_stat_data_rd_0;
   end      

assign tcam_stat_addr_wr_0 = (stat_mem_clr_wr) ? stat_mem_clr_addr : tcam_stat_addr_rd_0_d2;
assign tcam_stat_wr_0 = (stat_mem_clr_wr) ? 1 : tcam_stat_wr_0_d2;
assign tcam_stat_data_wr_0 = (stat_mem_clr_wr) ? 0 : tcam_stat_data_rd_0_d + 1;


always @(posedge axi_aclk)
   if (~axi_resetn)
      tcam_stat_data_rd <= 0;
   else if (tcam_stat_rd_1_d)
      tcam_stat_data_rd <= tcam_stat_data_rd_1;

bram_mem_true_dual
#(
   .ADDR_WIDTH    (  TCAM_ADDR_WIDTH         ),
   .DATA_WIDTH    (  C_S_AXI_DATA_WIDTH      )
)
entry_stats_match_mem
(
   .CLK_0         (  axi_aclk                ),
   .WR_0          (  tcam_stat_wr_0          ),
   .ADDR_WR_0     (  tcam_stat_addr_wr_0     ),
   .DIN_0         (  tcam_stat_data_wr_0     ),
   .RD_0          (  tcam_stat_rd_0          ),
   .ADDR_RD_0     (  tcam_stat_addr_rd_0     ),
   .DOUT_0        (  tcam_stat_data_rd_0     ),
   

   .CLK_1         (  axi_aclk                ),
   .WR_1          (0),
   .ADDR_WR_1     (0),
   .DIN_1         (0),
   .RD_1          (  tcam_stat_rd_1          ),
   .ADDR_RD_1     (  tcam_stat_addr_rd_1     ),
   .DOUT_1        (  tcam_stat_data_rd_1     )
);


endmodule
module tcam_table_double
#(
   parameter   C_S_AXI_DATA_WIDTH   = 32,
   parameter   TCAM_ADDR_WIDTH      = 4,
   parameter   TCAM_DATA_WIDTH      = 32,

   parameter   TCAM_DUMMY_ENTRY     = 32'hace0_face
)
(
   input                                     axi_aclk,
   input                                     axi_resetn,


   input                                     tcam_entry_en,

   input          [TCAM_DATA_WIDTH-1:0]      tcam_entry,
   
   input                                     tcam_sel,
   input                                     flow_buffer_sel,


   input          [1:0]                      tcam_wr_ctrl,
   output                                    tcam_status,

   input          [TCAM_ADDR_WIDTH-1:0]      tcam_addr_wr,
   input                                     tcam_wren,
   input          [TCAM_DATA_WIDTH-1:0]      tcam_din,
   input          [TCAM_DATA_WIDTH-1:0]      tcam_din_mask,
   output                                    tcam_busy,

   output                                    tcam_hit,
   output                                    tcam_miss,
   output         [TCAM_ADDR_WIDTH-1:0]      tcam_match_result,
   output                                    tcam_match_en,

   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_hit_total,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_miss_total,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_total,

   input                                     tcam_flow_stat_clr,

   input          [TCAM_ADDR_WIDTH-1:0]      tcam_stat_addr_rd,
   input                                     tcam_stat_rden,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]   tcam_stat_data_rd,

   input                                     tcam_stat_clr
);


wire  tcam_wren_0, tcam_busy_0, tcam_match_0;
wire  [TCAM_ADDR_WIDTH-1:0]   tcam_wr_addr_0, tcam_result_0;
wire  [TCAM_DATA_WIDTH-1:0]   tcam_wr_din_0, tcam_wr_din_mask_0, tcam_cmp_0;

wire  tcam_wren_1, tcam_busy_1, tcam_match_1;
wire  [TCAM_ADDR_WIDTH-1:0]   tcam_wr_addr_1, tcam_result_1;
wire  [TCAM_DATA_WIDTH-1:0]   tcam_wr_din_1, tcam_wr_din_mask_1, tcam_cmp_1;

assign tcam_busy = tcam_busy_0 | tcam_busy_1;

reg   r_tcam_sel;
always @(posedge axi_aclk)
   if (~axi_resetn)
      r_tcam_sel <= 0;
   else if (tcam_entry_en)
      r_tcam_sel <= tcam_sel;

wire  w_tcam_sel = (tcam_entry_en) ? tcam_sel : r_tcam_sel;


assign tcam_status = (tcam_wr_ctrl == 1) ? 0 :
                     (tcam_wr_ctrl == 2) ? 1 : flow_buffer_sel;


reg   [2:0] r_tcam_entry_en;
always @(posedge  axi_aclk)
   if (~axi_resetn) begin
      r_tcam_entry_en   <= 0;
   end
   else begin
      r_tcam_entry_en   <= {r_tcam_entry_en[1:0], tcam_entry_en};
   end

reg   [2:0] r_tcam_sel_d;
always @(posedge  axi_aclk)
   if (~axi_resetn) begin
      r_tcam_sel_d   <= 0;
   end
   else begin
      r_tcam_sel_d   <= {r_tcam_sel_d[1:0], w_tcam_sel};
   end


assign tcam_wren_0 = (tcam_wr_ctrl != 0) ? tcam_wr_ctrl[0] & tcam_wren :
                     (flow_buffer_sel == 1)   ? tcam_wren : 0;
assign tcam_wr_addr_0 = (tcam_wr_ctrl == 1 || flow_buffer_sel == 1) ? tcam_addr_wr : 0;
assign tcam_wr_din_0 = (tcam_wr_ctrl == 1 || flow_buffer_sel == 1) ? tcam_din : 0;

assign tcam_cmp_0 = (tcam_entry_en & tcam_wr_ctrl == 1) ? tcam_entry : 
                    (tcam_entry_en & tcam_wr_ctrl == 2) ? TCAM_DUMMY_ENTRY : 
                    (tcam_entry_en & w_tcam_sel == 0)   ? tcam_entry : TCAM_DUMMY_ENTRY;

`ifdef TCAM_MULTI
tcam_multi_wrapper
`else
tcam_module
`endif
#(
   .TCAM_ADDR_WIDTH  (  TCAM_ADDR_WIDTH         ),
   .TCAM_DATA_WIDTH  (  TCAM_DATA_WIDTH         )
)
tcam_table_0 (
   .CLK              (  axi_aclk                ),
   .RSTN             (  axi_resetn              ),
   .WR               (  tcam_wren_0             ), 
   .ADDR_WR          (  tcam_wr_addr_0          ),
   .DIN              (  tcam_wr_din_0           ), 
   .DIN_MASK         (  {TCAM_DATA_WIDTH{1'b0}} ), 
   .BUSY             (  tcam_busy_0          ), 
`ifdef EN_TCAM_RD
   .RD               (                          ),  
   .ADDR_RD          (  0                       ),
   .DOUT             (                          ),
`endif
   .CAM_DIN          (  tcam_cmp_0              ),
   .CAM_DATA_MASK    (  {TCAM_DATA_WIDTH{1'b0}} ),
   .MATCH            (  tcam_match_0            ),
   .MATCH_ADDR       (  tcam_result_0           )
);


assign tcam_wren_1 = (tcam_wr_ctrl != 0) ? tcam_wr_ctrl[1] & tcam_wren :
                     (flow_buffer_sel == 0) ? tcam_wren : 0;
assign tcam_wr_addr_1 = (tcam_wr_ctrl == 2 || flow_buffer_sel == 0) ? tcam_addr_wr : 0;
assign tcam_wr_din_1 = (tcam_wr_ctrl == 2 || flow_buffer_sel == 0) ? tcam_din : 0;

assign tcam_cmp_1 = (tcam_entry_en & tcam_wr_ctrl == 2) ? tcam_entry :
                    (tcam_entry_en & tcam_wr_ctrl == 1) ? TCAM_DUMMY_ENTRY :
                    (tcam_entry_en & w_tcam_sel == 1)   ? tcam_entry : TCAM_DUMMY_ENTRY;

`ifdef TCAM_MULTI
tcam_multi_wrapper
`else
tcam_module
`endif
#(
   .TCAM_ADDR_WIDTH  (  TCAM_ADDR_WIDTH         ),
   .TCAM_DATA_WIDTH  (  TCAM_DATA_WIDTH         )
)
tcam_table_1 (
   .CLK              (  axi_aclk                ),
   .RSTN             (  axi_resetn              ),
   .WR               (  tcam_wren_1             ), 
   .ADDR_WR          (  tcam_wr_addr_1          ),
   .DIN              (  tcam_wr_din_1           ), 
   .DIN_MASK         (  {TCAM_DATA_WIDTH{1'b0}} ), 
   .BUSY             (  tcam_busy_1          ), 
`ifdef EN_TCAM_RD
   .RD               (                          ),  
   .ADDR_RD          (  0                       ),
   .DOUT             (                          ),
`endif
   .CAM_DIN          (  tcam_cmp_1              ),
   .CAM_DATA_MASK    (  {TCAM_DATA_WIDTH{1'b0}} ),
   .MATCH            (  tcam_match_1            ),
   .MATCH_ADDR       (  tcam_result_1           )
);


assign tcam_hit = (r_tcam_entry_en[2]) ? (tcam_wr_ctrl == 1)    ? tcam_match_0 :
                                         (tcam_wr_ctrl == 2)    ? tcam_match_1 :
                                         (r_tcam_sel_d[2] == 0) ? tcam_match_0 : tcam_match_1 :
                                         0;
assign tcam_miss = (r_tcam_entry_en[2]) ? (tcam_wr_ctrl == 1)    ? ~tcam_match_0 :
                                          (tcam_wr_ctrl == 2)    ? ~tcam_match_1 :
                                          (r_tcam_sel_d[2] == 0) ? ~tcam_match_0 : ~tcam_match_1 :
                                          0;
assign tcam_match_result = (r_tcam_entry_en[2] & (tcam_match_0 | tcam_match_1)) ? (tcam_wr_ctrl == 1) ? tcam_result_0 :
                                                                                  (tcam_wr_ctrl == 2) ? tcam_result_1 :
                                                                                  (r_tcam_sel_d[2] == 0) ? tcam_result_0 : tcam_result_1 :
                                                                                  0;
assign tcam_match_en = r_tcam_entry_en[2];


always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_hit_total    <= 0;
      tcam_miss_total   <= 0;
      tcam_total        <= 0;
   end
   else if (tcam_flow_stat_clr) begin
      tcam_hit_total    <= 0;
      tcam_miss_total   <= 0;
      tcam_total        <= 0;
   end
   else if (r_tcam_entry_en[2]) begin
      tcam_hit_total    <= (tcam_hit) ? tcam_hit_total + 1 : tcam_hit_total;
      tcam_miss_total   <= (tcam_miss) ? tcam_miss_total + 1 : tcam_miss_total;
      tcam_total        <= tcam_total + 1;
   end



reg   [TCAM_ADDR_WIDTH-1:0]   stat_mem_clr_addr;
reg   stat_mem_clr_wr;

always @(posedge axi_aclk)
   if (~axi_resetn) begin
      stat_mem_clr_addr  <= 0;
      stat_mem_clr_wr    <= 0;
   end
   else if (stat_mem_clr_addr > 0) begin
      stat_mem_clr_addr  <= (stat_mem_clr_addr == (2**TCAM_ADDR_WIDTH-1)) ? 0 : stat_mem_clr_addr + 1;
      stat_mem_clr_wr    <= (stat_mem_clr_addr == (2**TCAM_ADDR_WIDTH-1)) ? 0 : 1;
   end
   else if (tcam_stat_clr) begin
      stat_mem_clr_addr  <= 1;
      stat_mem_clr_wr    <= 1;
   end

wire  [TCAM_ADDR_WIDTH-1:0]   tcam_stat_addr_wr_0, tcam_stat_addr_rd_0, tcam_stat_addr_rd_1;
wire  tcam_stat_wr_0, tcam_stat_rd_0;
wire  [C_S_AXI_DATA_WIDTH-1:0]   tcam_stat_data_wr_0, tcam_stat_data_rd_0, tcam_stat_data_rd_1;

assign tcam_stat_addr_rd_0 = tcam_match_result;
assign tcam_stat_rd_0 = tcam_hit;

assign tcam_stat_addr_rd_1 = tcam_stat_addr_rd;
assign tcam_stat_rd_1 = tcam_stat_rden;

reg   [TCAM_ADDR_WIDTH-1:0]  tcam_stat_addr_rd_0_d1, tcam_stat_addr_rd_0_d2;
reg   tcam_stat_rd_1_d, tcam_stat_wr_0_d1, tcam_stat_wr_0_d2;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_stat_addr_rd_0_d1  <= 0;
      tcam_stat_addr_rd_0_d2  <= 0;
      tcam_stat_wr_0_d1       <= 0;
      tcam_stat_wr_0_d2       <= 0;
      tcam_stat_rd_1_d        <= 0;
   end
   else begin
      tcam_stat_addr_rd_0_d1  <= tcam_stat_addr_rd_0;
      tcam_stat_addr_rd_0_d2  <= tcam_stat_addr_rd_0_d1;
      tcam_stat_wr_0_d1       <= tcam_hit;
      tcam_stat_wr_0_d2       <= tcam_stat_wr_0_d1;
      tcam_stat_rd_1_d        <= tcam_stat_rden;
   end

reg   [TCAM_DATA_WIDTH-1:0]   tcam_stat_data_rd_0_d;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      tcam_stat_data_rd_0_d <= 0;
   end
   else if (tcam_stat_wr_0_d1) begin
      tcam_stat_data_rd_0_d <= tcam_stat_data_rd_0;
   end      

assign tcam_stat_addr_wr_0 = (stat_mem_clr_wr) ? stat_mem_clr_addr : tcam_stat_addr_rd_0_d2;
assign tcam_stat_wr_0 = (stat_mem_clr_wr) ? 1 : tcam_stat_wr_0_d2;
assign tcam_stat_data_wr_0 = (stat_mem_clr_wr) ? 0 : tcam_stat_data_rd_0_d + 1;


always @(posedge axi_aclk)
   if (~axi_resetn)
      tcam_stat_data_rd <= 0;
   else if (tcam_stat_rd_1_d)
      tcam_stat_data_rd <= tcam_stat_data_rd_1;

bram_mem_true_dual
#(
   .ADDR_WIDTH    (  TCAM_ADDR_WIDTH         ),
   .DATA_WIDTH    (  C_S_AXI_DATA_WIDTH      )
)
entry_stats_match_mem
(
   .CLK_0         (  axi_aclk                ),
   .WR_0          (  tcam_stat_wr_0          ),
   .ADDR_WR_0     (  tcam_stat_addr_wr_0     ),
   .DIN_0         (  tcam_stat_data_wr_0     ),
   .RD_0          (  tcam_stat_rd_0          ),
   .ADDR_RD_0     (  tcam_stat_addr_rd_0     ),
   .DOUT_0        (  tcam_stat_data_rd_0     ),
   

   .CLK_1         (  axi_aclk                ),
   .WR_1          (0),
   .ADDR_WR_1     (0),
   .DIN_1         (0),
   .RD_1          (  tcam_stat_rd_1          ),
   .ADDR_RD_1     (  tcam_stat_addr_rd_1     ),
   .DOUT_1        (  tcam_stat_data_rd_1     )
);


endmodule