data/full_repos/permissive/443556793/lab_4/rtl/controller.v
1: b"%Error: data/full_repos/permissive/443556793/lab_4/rtl/controller.v:66: Duplicate declaration of signal: 'memwriteD'\n                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire[3:0] memwriteD;\n          ^~~~~~~~~\n        data/full_repos/permissive/443556793/lab_4/rtl/controller.v:32: ... Location of original declaration\n           output wire[3:0] memwriteD,\n                            ^~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module controller(
           input wire clk,rst,

           input wire[5:0] opD,functD,
           input wire[4:0] rtD,

           output wire branchD,

           output wire jumpD,
           output wire[3:0] memwriteD,
           output wire jrD,
           output wire jalD,
           output wire pceightD,
           output wire signD,
           output wire hilowriteD,
           output wire hilotoregD,
           output wire hiloaluD,
           output wire hiloreadD,


           input wire flushE,
           output wire memtoregE,alusrcE,
           output wire regdstE,regwriteE,
           output wire[7:0] alucontrolE,
           input wire stallE,


           output wire memtoregM,
           output wire regwriteM,
           output wire[2:0] lshbM,

           output wire memtoregW,regwriteW,
           output wire[2:0] lshbW

       );





wire memtoregD,alusrcD,regdstD,regwriteD;
wire[7:0] alucontrolD;
wire[2:0] lshbD;
wire[3:0] memwriteD;



wire[2:0] lshbE;

maindec md(
            opD,
            functD,
            rtD,
            memtoregD,memwriteD,
            branchD,alusrcD,
            regdstD,regwriteD,
            jumpD,
            lshbD,
            jrD,
            jalD,
            pceightD,
            signD,
            hilowriteD,
            hilotoregD,
            hiloaluD,
            hiloreadD
        );
aludec ad(functD,opD,alucontrolD);




flopenrc #(15) regE(
           clk,
           rst,
           ~stallE,
           flushE,
           {memwriteD,alusrcD,regdstD,regwriteD,alucontrolD},
           {memwriteE,alusrcE,regdstE,regwriteE,alucontrolE}
       );
flopenrc #(3) regE2(
           clk,
           rst,
           ~stallE,
           flushE,
           lshbD,
           lshbE
       );
flopenrc #(1) regE3(
           clk,
           rst,
           ~stallE,
           flushE,
           memtoregD,
           memtoregE
       );
flopr #(8) regM(
          clk,rst,
          {memtoregE,memwriteE,regwriteE},
          {memtoregM,memwriteM,regwriteM}
      );
flopr #(3) regM2(
          clk,rst,
          lshbE,
          lshbM
      );
flopr #(8) regW(
          clk,rst,
          {memtoregM,regwriteM},
          {memtoregW,regwriteW}
      );
flopr #(3) regW2(
          clk,rst,
          lshbM,
          lshbW
      );
endmodule
module controller(
           input wire clk,rst,

           input wire[5:0] opD,functD,
           input wire[4:0] rtD,

           output wire branchD,

           output wire jumpD,
           output wire[3:0] memwriteD,
           output wire jrD,
           output wire jalD,
           output wire pceightD,
           output wire signD,
           output wire hilowriteD,
           output wire hilotoregD,
           output wire hiloaluD,
           output wire hiloreadD,


           input wire flushE,
           output wire memtoregE,alusrcE,
           output wire regdstE,regwriteE,
           output wire[7:0] alucontrolE,
           input wire stallE,


           output wire memtoregM,
           output wire regwriteM,
           output wire[2:0] lshbM,

           output wire memtoregW,regwriteW,
           output wire[2:0] lshbW

       );






wire memtoregD,alusrcD,regdstD,regwriteD;
wire[7:0] alucontrolD;
wire[2:0] lshbD;
wire[3:0] memwriteD;



wire[2:0] lshbE;

maindec md(
            opD,
            functD,
            rtD,
            memtoregD,memwriteD,
            branchD,alusrcD,
            regdstD,regwriteD,
            jumpD,
            lshbD,
            jrD,
            jalD,
            pceightD,
            signD,
            hilowriteD,
            hilotoregD,
            hiloaluD,
            hiloreadD
        );
aludec ad(functD,opD,alucontrolD);




flopenrc #(15) regE(
           clk,
           rst,
           ~stallE,
           flushE,
           {memwriteD,alusrcD,regdstD,regwriteD,alucontrolD},
           {memwriteE,alusrcE,regdstE,regwriteE,alucontrolE}
       );
flopenrc #(3) regE2(
           clk,
           rst,
           ~stallE,
           flushE,
           lshbD,
           lshbE
       );
flopenrc #(1) regE3(
           clk,
           rst,
           ~stallE,
           flushE,
           memtoregD,
           memtoregE
       );
flopr #(8) regM(
          clk,rst,
          {memtoregE,memwriteE,regwriteE},
          {memtoregM,memwriteM,regwriteM}
      );
flopr #(3) regM2(
          clk,rst,
          lshbE,
          lshbM
      );
flopr #(8) regW(
          clk,rst,
          {memtoregM,regwriteM},
          {memtoregW,regwriteW}
      );
flopr #(3) regW2(
          clk,rst,
          lshbM,
          lshbW
      );
endmodule