data/full_repos/permissive/472385934/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472385934/alu.v:15: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SUB generates 32 bits.\n                                                             : ... In instance alu\n        3\'b110 : aluout = (in1-in2)?0:1; \n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu(
input [31:0] in1,
input [31:0] in2,
input [3:0] func,
output reg[31:0] aluout);

always @(*) begin
    case (func[2:0]) 
        3'b000 : aluout = in1+in2;
        3'b001 : aluout = in1-in2;
        3'b010 : aluout = in1|in2;
        3'b011 : aluout = in1&in2;
        3'b100 : aluout = in1^in2;
        3'b101 : aluout = ~(in1^in2);
        3'b110 : aluout = (in1-in2)?0:1;
        3'b111 : aluout = {in2[15:0],16'b0};
        default : aluout = 32'b0;
    endcase
end
endmodule
module alu(
input [31:0] in1,
input [31:0] in2,
input [3:0] func,
output reg[31:0] aluout);


always @(*) begin
    case (func[2:0]) 
        3'b000 : aluout = in1+in2;
        3'b001 : aluout = in1-in2;
        3'b010 : aluout = in1|in2;
        3'b011 : aluout = in1&in2;
        3'b100 : aluout = in1^in2;
        3'b101 : aluout = ~(in1^in2);
        3'b110 : aluout = (in1-in2)?0:1;
        3'b111 : aluout = {in2[15:0],16'b0};
        default : aluout = 32'b0;
    endcase
end
endmodule