data/full_repos/permissive/515245706/milestone1/gridDrawer/gridDrawer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/gridDrawer/gridDrawer.v:108: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1d\' generates 5 bits.\n                                                                                           : ... In instance gridDrawer.d1\n     x <= x + 5\'d29;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/gridDrawer/gridDrawer.v:105: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h74\' generates 7 bits.\n                                                                                           : ... In instance gridDrawer.d1\n    if (x == 7\'d116)\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/gridDrawer/gridDrawer.v:71: Operator ADD expects 7 bits on the RHS, but RHS\'s CONST \'5\'h1d\' generates 5 bits.\n                                                                                          : ... In instance gridDrawer.d0\n     y <= y + 5\'d29;\n            ^\n%Error: Exiting due to 3 warning(s)\n'
module linePixelCounter(clk, enable, resetn, load, out);
	input clk, enable, resetn;
	input [6: 0] load;
	reg [6: 0] cnt;
	output [6: 0] out;
	
	always @(posedge clk)
	begin 
		if (resetn == 0 || cnt >= load) 
			cnt <= 0;
		else if (enable == 1'b1)
			cnt <= cnt + 1;
	end
	assign out = cnt;
endmodule
module linePixelCounter(clk, enable, resetn, load, out);

	input clk, enable, resetn;
	input [6: 0] load;
	reg [6: 0] cnt;
	output [6: 0] out;
	
	always @(posedge clk)
	begin 
		if (resetn == 0 || cnt >= load) 
			cnt <= 0;
		else if (enable == 1'b1)
			cnt <= cnt + 1;
	end
	assign out = cnt;
endmodule