data/full_repos/permissive/531248401/module2_blink/2.3-oops_all_gates/oops_all_gates.v
1: b"%Error: data/full_repos/permissive/531248401/module2_blink/2.3-oops_all_gates/oops_all_gates.v:27: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/531248401/module2_blink/2.3-oops_all_gates/oops_all_gates.v:34: syntax error, unexpected and\nand(LEDG_N, sw[0], sw[1]);       \n^~~\n%Error: Exiting due to 2 error(s)\n"
module top(
    input  CLK,


    input P1A1,
    input P1A2,
    input P1A3,
    input P1A4,
    input P1A7,
    input P1A8,
    input P1A9,
    input P1A10,

    output LEDG_N,
	output LEDR_N,
);


wire [7:0] sw = ~{P1A10, P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1};



and(LEDG_N, sw[0], sw[1]);
and(x, sw[2], sw[3], sw[4]);
or(LEDR_N, sw[5], x);





endmodule
module top(
    input  CLK,


    input P1A1,
    input P1A2,
    input P1A3,
    input P1A4,
    input P1A7,
    input P1A8,
    input P1A9,
    input P1A10,

    output LEDG_N,
	output LEDR_N,
);



wire [7:0] sw = ~{P1A10, P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1};



and(LEDG_N, sw[0], sw[1]);
and(x, sw[2], sw[3], sw[4]);
or(LEDR_N, sw[5], x);





endmodule