data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design.v
data/verilator_xmls/aa7c472d-f63b-46c6-a2e1-32e19f0690d6.xml
module synchronous_scanned_d_ff(input d_in_0,d_in_1,sel,rst,clk,output reg d_out);

reg d;

always@(d_in_0,d_in_1,sel)
begin
d = (!sel ? d_in_0 : d_in_1);
end

always@(posedge clk)
begin
if(rst)d_out <= 1'b0;
else d_out <= d;
end

endmodule
module synchronous_scanned_d_ff(input d_in_0,d_in_1,sel,rst,clk,output reg d_out);


reg d;

always@(d_in_0,d_in_1,sel)
begin
d = (!sel ? d_in_0 : d_in_1);
end

always@(posedge clk)
begin
if(rst)d_out <= 1'b0;
else d_out <= d;
end

endmodule