data/full_repos/permissive/43264243/channel.v
1: b'%Error: data/full_repos/permissive/43264243/channel.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/channel.v:124: Define or directive not defined: \'`FIFO_DEPTH\'\n wire [`FIFO_DEPTH-1:0] itemsinfifo;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: Define or directive not defined: \'`FIFO_DEPTH\'\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                                   ^\n%Error: Exiting due to 4 error(s)\n'
module channel(clk, rstn, datain, unload, counterin, byteaddr, clearoverrun, overrun, attention, dataout, testouta, testoutb);
	input clk;
	input rstn;
	input datain;
	input unload;
	input [62:0] counterin;
	input [2:0] byteaddr;
	input clearoverrun;
	output overrun;
	output attention;
	output[7:0] dataout;
	output testouta;
	output testoutb;

	
	wire empty;
	wire full;
	wire datain_filt;
	wire [`FIFO_DEPTH-1:0] itemsinfifo;
	wire [63:0] fifooutputword;
	wire [63:0] fifoinputword;
	wire loaden;
	wire attention_int;
	
	reg overrun_int;
	reg attention_delayed;
	

	digitalfilter df0(
		.clk(clk),
		.rstn(rstn),
		.in(datain),
		.out(datain_filt)
	);
		


	edgedet ed0(
		.clk(clk),
		.rstn(rstn),
		.datain(datain_filt),
		.edgeseen(loaden)
	);
	
	

	ptrfifo fifo0(
	.clk(clk),
	.rstn(rstn),
	.loaden(loaden),
	.unloaden(unload),
	.datain(fifoinputword),
	.dataout(fifooutputword),
	.empty(empty),
	.full(full),
	.itemsinfifo(itemsinfifo)
	);
	
	defparam fifo0.WIDTH = 64;
	defparam fifo0.DEPTH = `FIFO_DEPTH;
	

	mux64to8 mux0(
		.sel(byteaddr),
		.inword(fifooutputword),
		.outbyte(dataout)
	);
	


	assign fifoinputword = {counterin, datain_filt};
	

	assign attention_int = ~empty | overrun_int;

	assign attention = attention_delayed;

	assign overrun = overrun_int;
	

	assign testouta = loaden;
	

	assign testoutb = unload;
	




	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			overrun_int = 0;
			attention_delayed = 0;
		end else begin

			attention_delayed = attention_int;

			if(clearoverrun == 1)
				overrun_int = 0;
			else if(full & loaden)

				overrun_int = 1;
		end
	end
			
endmodule
module channel(clk, rstn, datain, unload, counterin, byteaddr, clearoverrun, overrun, attention, dataout, testouta, testoutb);

	input clk;
	input rstn;
	input datain;
	input unload;
	input [62:0] counterin;
	input [2:0] byteaddr;
	input clearoverrun;
	output overrun;
	output attention;
	output[7:0] dataout;
	output testouta;
	output testoutb;

	
	wire empty;
	wire full;
	wire datain_filt;
	wire [`FIFO_DEPTH-1:0] itemsinfifo;
	wire [63:0] fifooutputword;
	wire [63:0] fifoinputword;
	wire loaden;
	wire attention_int;
	
	reg overrun_int;
	reg attention_delayed;
	

	digitalfilter df0(
		.clk(clk),
		.rstn(rstn),
		.in(datain),
		.out(datain_filt)
	);
		


	edgedet ed0(
		.clk(clk),
		.rstn(rstn),
		.datain(datain_filt),
		.edgeseen(loaden)
	);
	
	

	ptrfifo fifo0(
	.clk(clk),
	.rstn(rstn),
	.loaden(loaden),
	.unloaden(unload),
	.datain(fifoinputword),
	.dataout(fifooutputword),
	.empty(empty),
	.full(full),
	.itemsinfifo(itemsinfifo)
	);
	
	defparam fifo0.WIDTH = 64;
	defparam fifo0.DEPTH = `FIFO_DEPTH;
	

	mux64to8 mux0(
		.sel(byteaddr),
		.inword(fifooutputword),
		.outbyte(dataout)
	);
	


	assign fifoinputword = {counterin, datain_filt};
	

	assign attention_int = ~empty | overrun_int;

	assign attention = attention_delayed;

	assign overrun = overrun_int;
	

	assign testouta = loaden;
	

	assign testoutb = unload;
	




	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			overrun_int = 0;
			attention_delayed = 0;
		end else begin

			attention_delayed = attention_int;

			if(clearoverrun == 1)
				overrun_int = 0;
			else if(full & loaden)

				overrun_int = 1;
		end
	end
			
endmodule