data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("round_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,round_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module round_tb();

   localparam IW=8;
   localparam OW=4;
   localparam EW=IW-OW+1;
   
   reg signed [IW-1:0] in;
   wire signed [OW-1:0] out;
   wire signed [EW-1:0] err;

   round #(.bits_in(IW),
	   .bits_out(OW),
	   .round_to_zero(0),
	   .round_to_nearest(1),
	   .trunc(0))
   round (.in(in),.out(out),.err(err));

   initial $dumpfile("round_tb.vcd");
   initial $dumpvars(0,round_tb);

   wire signed [IW-1:0] out_round = {out,{IW-OW{1'b0}}};
   
   initial
     begin
	in <= -129;
	#1;
	repeat (260)
	  begin
	     in <= in + 1;
	     #1;
	     $display("In %d, out %d, out_rnd %d, err %d, real err %d",in,out,out_round,-err,out_round-in);
	     #1;
	  end
	$finish;
     end
     
endmodule
module round_tb();


   localparam IW=8;
   localparam OW=4;
   localparam EW=IW-OW+1;
   
   reg signed [IW-1:0] in;
   wire signed [OW-1:0] out;
   wire signed [EW-1:0] err;

   round #(.bits_in(IW),
	   .bits_out(OW),
	   .round_to_zero(0),
	   .round_to_nearest(1),
	   .trunc(0))
   round (.in(in),.out(out),.err(err));

   initial $dumpfile("round_tb.vcd");
   initial $dumpvars(0,round_tb);

   wire signed [IW-1:0] out_round = {out,{IW-OW{1'b0}}};
   
   initial
     begin
	in <= -129;
	#1;
	repeat (260)
	  begin
	     in <= in + 1;
	     #1;
	     $display("In %d, out %d, out_rnd %d, err %d, real err %d",in,out,out_round,-err,out_round-in);
	     #1;
	  end
	$finish;
     end
     
endmodule