data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:24: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.sv\n             ./const/parameters_cla.v\n             ./const/parameters_cla.v.v\n             ./const/parameters_cla.v.sv\n             obj_dir/./const/parameters_cla.v\n             obj_dir/./const/parameters_cla.v.v\n             obj_dir/./const/parameters_cla.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:55: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:76: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:106: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:125: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:146: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:172: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:200: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module CLA_16 ( OPA, OPB, CIN, PHI, SUM_FINAL, COUT_FINAL, CLK );
`include "./const/parameters_cla.v"

input  [N_16-1:0] OPA;
input  [N_16-1:0] OPB;
input  CIN;
input  PHI;
input  CLK;
output [N_16-1:0] SUM_FINAL;
output COUT_FINAL;

   wire [N_16-1:0] INTPROP;
   wire [N_16:0] INTGEN;
   wire [0:0] PBIT;
   wire [N_16:0] CARRY;
   wire [N_16-1:0] SUM;
   wire COUT;
	
   PRESTAGE_16 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
   DBLCTREE_16 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
   XORSTAGE_16 U3 (OPA[N_16-1:0] , OPB[N_16-1:0] , PBIT , PHI , CARRY[N_16:0] , SUM , COUT );
   
   always@(posedge CLK) begin
	SUM_FINAL <= SUM;
	COUT_FINAL <= COUT;
	end
   
   
endmodule
module CLA_16 ( OPA, OPB, CIN, PHI, SUM_FINAL, COUT_FINAL, CLK );

`include "./const/parameters_cla.v"

input  [N_16-1:0] OPA;
input  [N_16-1:0] OPB;
input  CIN;
input  PHI;
input  CLK;
output [N_16-1:0] SUM_FINAL;
output COUT_FINAL;

   wire [N_16-1:0] INTPROP;
   wire [N_16:0] INTGEN;
   wire [0:0] PBIT;
   wire [N_16:0] CARRY;
   wire [N_16-1:0] SUM;
   wire COUT;
	
   PRESTAGE_16 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
   DBLCTREE_16 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
   XORSTAGE_16 U3 (OPA[N_16-1:0] , OPB[N_16-1:0] , PBIT , PHI , CARRY[N_16:0] , SUM , COUT );
   
   always@(posedge CLK) begin
	SUM_FINAL <= SUM;
	COUT_FINAL <= COUT;
	end
   
   
endmodule