data/full_repos/permissive/52703097/alu.v
1: b'%Error: data/full_repos/permissive/52703097/alu.v:4: Cannot find include file: adder.v\n`include "adder.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v.sv\n             adder.v\n             adder.v.v\n             adder.v.sv\n             obj_dir/adder.v\n             obj_dir/adder.v.v\n             obj_dir/adder.v.sv\n%Error: data/full_repos/permissive/52703097/alu.v:5: Cannot find include file: multiplier.v\n`include "multiplier.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:6: Cannot find include file: divider.v\n`include "divider.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:7: Cannot find include file: shifter.v\n`include "shifter.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:71: Define or directive not defined: \'`WIDTH\'\nwire[`WIDTH + `WIDTH - 1:0] multiplier_result;\n     ^~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:71: Define or directive not defined: \'`WIDTH\'\nwire[`WIDTH + `WIDTH - 1:0] multiplier_result;\n              ^~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:84: Define or directive not defined: \'`WIDTH\'\nwire[`WIDTH-1:0] divider_quotient, divider_remainder;\n     ^~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:97: Define or directive not defined: \'`OPS\'\n                                                    : ... Suggested alternative: \'`OP_SUB\'\nreg[`OPS-1:0] shifter_ops;\n    ^~~~\n%Error: data/full_repos/permissive/52703097/alu.v:98: Define or directive not defined: \'`WIDTH\'\nwire[`WIDTH-1:0] shifter_result;\n     ^~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:103: Define or directive not defined: \'`SHIFT_WIDTH\'\n    .i_shift(i_b[`SHIFT_WIDTH-1:0]),\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:109: syntax error, unexpected \'!\', expecting TYPE-IDENTIFIER\nalways @(posedge clk && !reset) begin\n                        ^\n%Error: data/full_repos/permissive/52703097/alu.v:116: syntax error, unexpected \'=\', expecting IDENTIFIER\n            adder_cin = 1\'b0;\n                      ^\n%Error: data/full_repos/permissive/52703097/alu.v:121: syntax error, unexpected \'=\', expecting IDENTIFIER\n            subtractor_cin = 1\'b1;\n                           ^\n%Error: data/full_repos/permissive/52703097/alu.v:126: syntax error, unexpected \'=\', expecting IDENTIFIER\n            multiplier_start = 1\'b1;\n                             ^\n%Error: data/full_repos/permissive/52703097/alu.v:127: Define or directive not defined: \'`WIDTH\'\n            reg_result = multiplier_result[`WIDTH-1:0];\n                                           ^~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:131: syntax error, unexpected \'=\', expecting IDENTIFIER\n            divider_start = 1\'b1;\n                          ^\n%Error: data/full_repos/permissive/52703097/alu.v:136: syntax error, unexpected \'=\', expecting IDENTIFIER\n            shifter_ops = `LEFT_SHIFTL;\n                        ^\n%Error: data/full_repos/permissive/52703097/alu.v:136: Define or directive not defined: \'`LEFT_SHIFTL\'\n                                                     : ... Suggested alternative: \'`OP_LEFT_SHIFTL\'\n            shifter_ops = `LEFT_SHIFTL;\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:142: syntax error, unexpected \'=\', expecting IDENTIFIER\n            shifter_ops = `LEFT_SHIFTA;\n                        ^\n%Error: data/full_repos/permissive/52703097/alu.v:142: Define or directive not defined: \'`LEFT_SHIFTA\'\n                                                     : ... Suggested alternative: \'`OP_LEFT_SHIFTA\'\n            shifter_ops = `LEFT_SHIFTA;\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:148: syntax error, unexpected \'=\', expecting IDENTIFIER\n            shifter_ops = `RIGHT_SHIFTL;\n                        ^\n%Error: data/full_repos/permissive/52703097/alu.v:148: Define or directive not defined: \'`RIGHT_SHIFTL\'\n                                                     : ... Suggested alternative: \'`OP_RIGHT_SHIFTL\'\n            shifter_ops = `RIGHT_SHIFTL;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:154: syntax error, unexpected \'=\', expecting IDENTIFIER\n            shifter_ops = `RIGHT_SHIFTA;\n                        ^\n%Error: data/full_repos/permissive/52703097/alu.v:154: Define or directive not defined: \'`RIGHT_SHIFTA\'\n                                                     : ... Suggested alternative: \'`OP_RIGHT_SHIFTA\'\n            shifter_ops = `RIGHT_SHIFTA;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.v:159: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/52703097/alu.v:168: syntax error, unexpected \'=\', expecting IDENTIFIER\n        divider_start = 1\'b0;\n                      ^\n%Error: data/full_repos/permissive/52703097/alu.v:171: syntax error, unexpected \'=\', expecting IDENTIFIER\n        multiplier_start = 1\'b0;\n                         ^\n%Error: Cannot continue\n'
module alu(
  input clk,
  input reset,
  
  input [31:0] i_a,
  input [31:0] i_b,
  input  [3:0] i_cmd,

  output [31:0] o_result,
  output        o_valid,

  output        o_ready
);

reg [31:0] reg_result;
reg        reg_valid = 1'b0;


`define ST_RESET  2'h0
`define ST_READY  2'h1
`define ST_BUSY   2'h2


reg [1:0] reg_status = `ST_RESET;


always @(posedge clk && reset) begin
  reg_status <= `ST_READY;
end


assign o_ready = ((reg_status == `ST_READY) && !reset);
assign o_valid = (reg_valid && (reg_status == `ST_READY));
assign o_result = reg_result;




reg adder_cin;
wire adder_cout;
wire[31:0] adder_result;
adder alu_adder(.i_a(i_a), .i_b(i_b), .i_cin(adder_cin), .o_result(adder_result), .o_cout(adder_cout));


reg subtractor_cin;
wire subtractor_cout;
wire[31:0] subtractor_result;
adder alu_subtractor(.i_a(i_a), .i_b(~i_b), .i_cin(subtractor_cin), .o_result(subtractor_result), .o_cout(subtractor_cout));


reg multiplier_start = 1'b0;
wire[`WIDTH + `WIDTH - 1:0] multiplier_result;
wire multiplier_ready;

multiplier mul(
    .start(multiplier_start),
    .clk(clk),
    .multiplier(i_a),
    .multiplicand(i_b),
    .product(multiplier_result),
    .ready(multiplier_ready));


reg divider_start = 1'b0;
wire[`WIDTH-1:0] divider_quotient, divider_remainder;
wire divider_ready;

divider div(
    .start(divider_start),
    .clk(clk),
    .dividend(i_b),
    .divisor(i_a),
    .quotient(divider_quotient),
    .remainder(divider_remainder),
    .ready(divider_ready));


reg[`OPS-1:0] shifter_ops;
wire[`WIDTH-1:0] shifter_result;
reg shifter_start = 1'b0;

shifter shift(
    .i_data(i_a),
    .i_shift(i_b[`SHIFT_WIDTH-1:0]),
    .i_op(shifter_ops),
    .i_start(shifter_start),
    .o_result(shifter_result));


always @(posedge clk && !reset) begin

  case (reg_status)
  `ST_READY: begin
    reg_status <= `ST_BUSY;
    case (i_cmd)
        `OP_ADD: begin
            adder_cin = 1'b0;
            reg_result = adder_result;
        end

        `OP_SUB: begin
            subtractor_cin = 1'b1;
            reg_result = subtractor_result;
        end

        `OP_MUL: begin
            multiplier_start = 1'b1;
            reg_result = multiplier_result[`WIDTH-1:0];
        end

        `OP_DIV: begin
            divider_start = 1'b1;
            reg_result = divider_quotient;
        end

        `OP_LEFT_SHIFTL: begin
            shifter_ops = `LEFT_SHIFTL;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_LEFT_SHIFTA: begin
            shifter_ops = `LEFT_SHIFTA;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_RIGHT_SHIFTL: begin
            shifter_ops = `RIGHT_SHIFTL;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_RIGHT_SHIFTA: begin
            shifter_ops = `RIGHT_SHIFTA;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end
    endcase
  end
  `ST_BUSY: begin
    if (divider_ready == 1'b1 && multiplier_ready == 1'b1) begin
        reg_valid <= 1'b1;
        reg_status <= `ST_READY;
    end

    shifter_start = 1'b0;
    if (divider_ready == 1'b0)
        divider_start = 1'b0;
    
    if (multiplier_ready == 1'b0)
        multiplier_start = 1'b0;
  end
  default: begin
    $display("should not happen");
    $finish;
  end
  endcase

end

endmodule
module alu(
  input clk,
  input reset,
  
  input [31:0] i_a,
  input [31:0] i_b,
  input  [3:0] i_cmd,

  output [31:0] o_result,
  output        o_valid,

  output        o_ready
);


reg [31:0] reg_result;
reg        reg_valid = 1'b0;


`define ST_RESET  2'h0
`define ST_READY  2'h1
`define ST_BUSY   2'h2


reg [1:0] reg_status = `ST_RESET;


always @(posedge clk && reset) begin
  reg_status <= `ST_READY;
end


assign o_ready = ((reg_status == `ST_READY) && !reset);
assign o_valid = (reg_valid && (reg_status == `ST_READY));
assign o_result = reg_result;




reg adder_cin;
wire adder_cout;
wire[31:0] adder_result;
adder alu_adder(.i_a(i_a), .i_b(i_b), .i_cin(adder_cin), .o_result(adder_result), .o_cout(adder_cout));


reg subtractor_cin;
wire subtractor_cout;
wire[31:0] subtractor_result;
adder alu_subtractor(.i_a(i_a), .i_b(~i_b), .i_cin(subtractor_cin), .o_result(subtractor_result), .o_cout(subtractor_cout));


reg multiplier_start = 1'b0;
wire[`WIDTH + `WIDTH - 1:0] multiplier_result;
wire multiplier_ready;

multiplier mul(
    .start(multiplier_start),
    .clk(clk),
    .multiplier(i_a),
    .multiplicand(i_b),
    .product(multiplier_result),
    .ready(multiplier_ready));


reg divider_start = 1'b0;
wire[`WIDTH-1:0] divider_quotient, divider_remainder;
wire divider_ready;

divider div(
    .start(divider_start),
    .clk(clk),
    .dividend(i_b),
    .divisor(i_a),
    .quotient(divider_quotient),
    .remainder(divider_remainder),
    .ready(divider_ready));


reg[`OPS-1:0] shifter_ops;
wire[`WIDTH-1:0] shifter_result;
reg shifter_start = 1'b0;

shifter shift(
    .i_data(i_a),
    .i_shift(i_b[`SHIFT_WIDTH-1:0]),
    .i_op(shifter_ops),
    .i_start(shifter_start),
    .o_result(shifter_result));


always @(posedge clk && !reset) begin

  case (reg_status)
  `ST_READY: begin
    reg_status <= `ST_BUSY;
    case (i_cmd)
        `OP_ADD: begin
            adder_cin = 1'b0;
            reg_result = adder_result;
        end

        `OP_SUB: begin
            subtractor_cin = 1'b1;
            reg_result = subtractor_result;
        end

        `OP_MUL: begin
            multiplier_start = 1'b1;
            reg_result = multiplier_result[`WIDTH-1:0];
        end

        `OP_DIV: begin
            divider_start = 1'b1;
            reg_result = divider_quotient;
        end

        `OP_LEFT_SHIFTL: begin
            shifter_ops = `LEFT_SHIFTL;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_LEFT_SHIFTA: begin
            shifter_ops = `LEFT_SHIFTA;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_RIGHT_SHIFTL: begin
            shifter_ops = `RIGHT_SHIFTL;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end

        `OP_RIGHT_SHIFTA: begin
            shifter_ops = `RIGHT_SHIFTA;
            shifter_start = 1'b1;
            reg_result = shifter_result;
        end
    endcase
  end
  `ST_BUSY: begin
    if (divider_ready == 1'b1 && multiplier_ready == 1'b1) begin
        reg_valid <= 1'b1;
        reg_status <= `ST_READY;
    end

    shifter_start = 1'b0;
    if (divider_ready == 1'b0)
        divider_start = 1'b0;
    
    if (multiplier_ready == 1'b0)
        multiplier_start = 1'b0;
  end
  default: begin
    $display("should not happen");
    $finish;
  end
  endcase

end

endmodule