data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:62: Unsupported: Ignoring delay on this delayed statement.\n    #(T / 2);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:64: Unsupported: Ignoring delay on this delayed statement.\n    #(T / 2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:71: Unsupported: Ignoring delay on this delayed statement.\n    #(T/2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:89: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:94: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:96: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:98: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:102: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:105: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:107: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:110: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:112: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:114: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:121: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:123: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:125: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:129: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:132: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:134: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:137: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:139: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:141: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:145: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:20: Cannot find file containing module: \'ra_2r1w_32x32_sdr\'\n  ra_2r1w_32x32_sdr dut (\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/ra_2r1w_32x32_sdr\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/ra_2r1w_32x32_sdr.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/ra_2r1w_32x32_sdr.sv\n             ra_2r1w_32x32_sdr\n             ra_2r1w_32x32_sdr.v\n             ra_2r1w_32x32_sdr.sv\n             obj_dir/ra_2r1w_32x32_sdr\n             obj_dir/ra_2r1w_32x32_sdr.v\n             obj_dir/ra_2r1w_32x32_sdr.sv\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:93: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                                                 : ... In instance tb\n    wr_adr_0 = 32\'h0001;      \n             ^\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:104: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'haaaa\' generates 32 bits.\n                                                                                                  : ... In instance tb\n    rd_adr_0 = 32\'hAAAA;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:111: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'haaaa\' generates 32 bits.\n                                                                                                  : ... In instance tb\n    rd_adr_1 = 32\'hAAAA;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:120: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8\' generates 32 bits.\n                                                                                                  : ... In instance tb\n    wr_adr_0 = 32\'h0008;      \n             ^\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:131: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8\' generates 32 bits.\n                                                                                                  : ... In instance tb\n    rd_adr_0 = 32\'h0008;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/425063934/custom_layout/sim/ra_2r1w_32x32_sdr_tb.sv:138: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8\' generates 32 bits.\n                                                                                                  : ... In instance tb\n    rd_adr_1 = 32\'h0008;\n             ^\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();


  localparam T = 20;

  logic         clk, reset, strobe;
  logic         rd_enb_0;
  logic [4:0]   rd_adr_0;
  logic [31:0]  rd_dat_0;
  logic         rd_enb_1;
  logic [4:0]   rd_adr_1;
  logic [31:0]  rd_dat_1;
  logic         wr_enb_0;
  logic [4:0]   wr_adr_0;
  logic [31:0]  wr_dat_0;


  ra_2r1w_32x32_sdr dut (
                         .clk(clk),
                         .reset(reset),
                         .strobe(strobe),
                         .rd_enb_0(rd_enb_0),
                         .rd_adr_0(rd_adr_0),
                         .rd_dat_0(rd_dat_0),
                         .rd_enb_1(rd_enb_1),
                         .rd_adr_1(rd_adr_1),
                         .rd_dat_1(rd_dat_1),
                         .wr_enb_0(wr_enb_0),
                         .wr_adr_0(wr_adr_0),
                         .wr_dat_0(wr_dat_0)
                         );

























  always
  begin
    clk = 1'b0;
    #(T / 2);
    clk = 1'b1;
    #(T / 2);
  end


  initial
  begin
    reset = 1;
    #(T/2);
    reset = 0;
  end

  initial
  begin

    strobe = 0;
               
    rd_enb_0 = 0;
    rd_adr_0 = 0;

    rd_enb_1 = 0;
    rd_adr_1 = 0;      

    wr_enb_0 = 0;      
    wr_adr_0 = 0;      
    wr_dat_0 = 0;      
    #10
    


    wr_adr_0 = 32'h0001;      
    #1
    wr_dat_0 = 32'hAAAA;
    #1
    wr_enb_0 = 1'b1;      
    #5
    wr_enb_0 = 1'b0;      

    
    #10

    rd_adr_0 = 32'hAAAA;
    #1
    rd_enb_0 = 1'b1;
    #5
    rd_enb_0 = 1'b0;

    #10
    rd_adr_1 = 32'hAAAA;
    #1
    rd_enb_1 = 1'b1;
    #5
    rd_enb_1 = 1'b0;




    wr_adr_0 = 32'h0008;      
    #1
    wr_dat_0 = 32'h0008;
    #1
    wr_enb_0 = 1'b1;      
    #5
    wr_enb_0 = 1'b0;      

    
    #10

    rd_adr_0 = 32'h0008;
    #1
    rd_enb_0 = 1'b1;
    #5
    rd_enb_0 = 1'b0;

    #10
    rd_adr_1 = 32'h0008;
    #1
    rd_enb_1 = 1'b1;
    #5
    rd_enb_1 = 1'b0;


    #100

    $stop;
  end

endmodule
module tb();



  localparam T = 20;

  logic         clk, reset, strobe;
  logic         rd_enb_0;
  logic [4:0]   rd_adr_0;
  logic [31:0]  rd_dat_0;
  logic         rd_enb_1;
  logic [4:0]   rd_adr_1;
  logic [31:0]  rd_dat_1;
  logic         wr_enb_0;
  logic [4:0]   wr_adr_0;
  logic [31:0]  wr_dat_0;


  ra_2r1w_32x32_sdr dut (
                         .clk(clk),
                         .reset(reset),
                         .strobe(strobe),
                         .rd_enb_0(rd_enb_0),
                         .rd_adr_0(rd_adr_0),
                         .rd_dat_0(rd_dat_0),
                         .rd_enb_1(rd_enb_1),
                         .rd_adr_1(rd_adr_1),
                         .rd_dat_1(rd_dat_1),
                         .wr_enb_0(wr_enb_0),
                         .wr_adr_0(wr_adr_0),
                         .wr_dat_0(wr_dat_0)
                         );

























  always
  begin
    clk = 1'b0;
    #(T / 2);
    clk = 1'b1;
    #(T / 2);
  end


  initial
  begin
    reset = 1;
    #(T/2);
    reset = 0;
  end

  initial
  begin

    strobe = 0;
               
    rd_enb_0 = 0;
    rd_adr_0 = 0;

    rd_enb_1 = 0;
    rd_adr_1 = 0;      

    wr_enb_0 = 0;      
    wr_adr_0 = 0;      
    wr_dat_0 = 0;      
    #10
    


    wr_adr_0 = 32'h0001;      
    #1
    wr_dat_0 = 32'hAAAA;
    #1
    wr_enb_0 = 1'b1;      
    #5
    wr_enb_0 = 1'b0;      

    
    #10

    rd_adr_0 = 32'hAAAA;
    #1
    rd_enb_0 = 1'b1;
    #5
    rd_enb_0 = 1'b0;

    #10
    rd_adr_1 = 32'hAAAA;
    #1
    rd_enb_1 = 1'b1;
    #5
    rd_enb_1 = 1'b0;




    wr_adr_0 = 32'h0008;      
    #1
    wr_dat_0 = 32'h0008;
    #1
    wr_enb_0 = 1'b1;      
    #5
    wr_enb_0 = 1'b0;      

    
    #10

    rd_adr_0 = 32'h0008;
    #1
    rd_enb_0 = 1'b1;
    #5
    rd_enb_0 = 1'b0;

    #10
    rd_adr_1 = 32'h0008;
    #1
    rd_enb_1 = 1'b1;
    #5
    rd_enb_1 = 1'b0;


    #100

    $stop;
  end

endmodule