data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v
1: b'%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:18: Cannot find include file: comparator.v\n`include "comparator.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498994766/verilog/rtl,data/full_repos/permissive/498994766/comparator.v\n             data/full_repos/permissive/498994766/verilog/rtl,data/full_repos/permissive/498994766/comparator.v.v\n             data/full_repos/permissive/498994766/verilog/rtl,data/full_repos/permissive/498994766/comparator.v.sv\n             comparator.v\n             comparator.v.v\n             comparator.v.sv\n             obj_dir/comparator.v\n             obj_dir/comparator.v.v\n             obj_dir/comparator.v.sv\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:112: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:112: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:113: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:113: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:114: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:114: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:115: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:115: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:118: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:118: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:119: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:119: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:122: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`ANALOG_PADS-1:0] io_analog,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:132: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:132: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:133: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:133: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:134: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:134: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:135: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:135: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:136: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`ANALOG_PADS-1:0] io_analog;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498994766/verilog/rtl/user_analog_proj_example.v:148: syntax error, unexpected \';\', expecting IDENTIFIER or do or final\n    wire analog0, analog2, analog3, ;\n                                    ^\n%Error: Exiting due to 24 error(s)\n'
module user_analog_proj_example (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,
    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] irq
);
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
    wire [`ANALOG_PADS-1:0] io_analog;






          `ifdef USE_POWER_PINS
	
    	assign io_clamp_high[2:1] = vccd1;
    	assign io_clamp_low[2:1] = vssa1;
    `endif
    wire analog0, analog2, analog3, ;

















    assign io_analog[2] = analog2;
    assign io_analog[3] = analog3;
    assign io_analog[5] = analog5;
    assign io_analog[6] = analog6;
    assign io_analog[1] = analog1;
    assign io_analog[8] = analog8;


    comparator comp1 (
	`ifdef USE_POWER_PINS
	    .VDD(vccd1),
	    .GND(vssa1),
	`endif
	.Vp(analog5),
	.Vn(analog6),
	.CLK(analog8),
	
	.Outn(analog3),
	.Outp(analog2)
    );


endmodule
module user_analog_proj_example (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,
    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] irq
);

    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
    wire [`ANALOG_PADS-1:0] io_analog;






          `ifdef USE_POWER_PINS
	
    	assign io_clamp_high[2:1] = vccd1;
    	assign io_clamp_low[2:1] = vssa1;
    `endif
    wire analog0, analog2, analog3, ;

















    assign io_analog[2] = analog2;
    assign io_analog[3] = analog3;
    assign io_analog[5] = analog5;
    assign io_analog[6] = analog6;
    assign io_analog[1] = analog1;
    assign io_analog[8] = analog8;


    comparator comp1 (
	`ifdef USE_POWER_PINS
	    .VDD(vccd1),
	    .GND(vssa1),
	`endif
	.Vp(analog5),
	.Vn(analog6),
	.CLK(analog8),
	
	.Outn(analog3),
	.Outp(analog2)
    );


endmodule