data/full_repos/permissive/529457593/Sprint10/RegisterFile.v
1: b"%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:11: Cannot find file containing module: 'decoder_octo'\n decoder_octo dcd (.data_in(wa3), .out_port(decod_out));\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/529457593/Sprint10,data/full_repos/permissive/529457593/decoder_octo\n             data/full_repos/permissive/529457593/Sprint10,data/full_repos/permissive/529457593/decoder_octo.v\n             data/full_repos/permissive/529457593/Sprint10,data/full_repos/permissive/529457593/decoder_octo.sv\n             decoder_octo\n             decoder_octo.v\n             decoder_octo.sv\n             obj_dir/decoder_octo\n             obj_dir/decoder_octo.v\n             obj_dir/decoder_octo.sv\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:13: Cannot find file containing module: 'register'\n register rg1 (.d_in(8'b0), .d_out(reg_out[7:0]),   .enable(we3 & decod_out[0]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:14: Cannot find file containing module: 'register'\n register rg2 (.d_in(wd3),  .d_out(reg_out[15:8]),  .enable(we3 & decod_out[1]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:15: Cannot find file containing module: 'register'\n register rg3 (.d_in(wd3),  .d_out(reg_out[23:16]), .enable(we3 & decod_out[2]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:16: Cannot find file containing module: 'register'\n register rg4 (.d_in(wd3),  .d_out(reg_out[31:24]), .enable(we3 & decod_out[3]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:17: Cannot find file containing module: 'register'\n register rg5 (.d_in(wd3),  .d_out(reg_out[39:32]), .enable(we3 & decod_out[4]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:18: Cannot find file containing module: 'register'\n register rg6 (.d_in(wd3),  .d_out(reg_out[47:40]), .enable(we3 & decod_out[5]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:19: Cannot find file containing module: 'register'\n register rg7 (.d_in(wd3),  .d_out(reg_out[55:48]), .enable(we3 & decod_out[6]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:20: Cannot find file containing module: 'register'\n register rg8 (.d_in(wd3),  .d_out(reg_out[63:56]), .enable(we3 & decod_out[7]), .clk(CLK));   \n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:22: Cannot find file containing module: 'register'\n register ra (.d_in(wd3), .d_out(reg_out[71:64]),   .enable(we3 & wa3 == 4'h8), .clk(CLK));\n ^~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:24: Cannot find file containing module: 'demux8_8b'\n demux8_8b demux1 (.data_in(reg_out), .sel(ra1), .data_out(rd1));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/529457593/Sprint10/RegisterFile.v:25: Cannot find file containing module: 'demux8_8b'\n demux8_8b demux2 (.data_in(reg_out), .sel(ra2), .data_out(rd2));\n ^~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module RegisterFile (input [7:0] wd3, input [3:0] wa3,
							 input we3, CLK,
							 input [3:0] ra1, ra2,
                             output [7:0] rd1, rd2,
                             output [71:0] LCD_exit
                     );           
							 
	wire [7:0] decod_out;
	wire [71:0] reg_out;
							 
	decoder_octo dcd (.data_in(wa3), .out_port(decod_out));

	register rg1 (.d_in(8'b0), .d_out(reg_out[7:0]),   .enable(we3 & decod_out[0]), .clk(CLK));
	register rg2 (.d_in(wd3),  .d_out(reg_out[15:8]),  .enable(we3 & decod_out[1]), .clk(CLK));
	register rg3 (.d_in(wd3),  .d_out(reg_out[23:16]), .enable(we3 & decod_out[2]), .clk(CLK));
	register rg4 (.d_in(wd3),  .d_out(reg_out[31:24]), .enable(we3 & decod_out[3]), .clk(CLK));
	register rg5 (.d_in(wd3),  .d_out(reg_out[39:32]), .enable(we3 & decod_out[4]), .clk(CLK));
	register rg6 (.d_in(wd3),  .d_out(reg_out[47:40]), .enable(we3 & decod_out[5]), .clk(CLK));
	register rg7 (.d_in(wd3),  .d_out(reg_out[55:48]), .enable(we3 & decod_out[6]), .clk(CLK));
	register rg8 (.d_in(wd3),  .d_out(reg_out[63:56]), .enable(we3 & decod_out[7]), .clk(CLK));
	
	register ra (.d_in(wd3), .d_out(reg_out[71:64]),   .enable(we3 & wa3 == 4'h8), .clk(CLK));
	
	demux8_8b demux1 (.data_in(reg_out), .sel(ra1), .data_out(rd1));
	demux8_8b demux2 (.data_in(reg_out), .sel(ra2), .data_out(rd2));
  
   assign LCD_exit = reg_out[71:0];
							 
endmodule
module RegisterFile (input [7:0] wd3, input [3:0] wa3,
							 input we3, CLK,
							 input [3:0] ra1, ra2,
                             output [7:0] rd1, rd2,
                             output [71:0] LCD_exit
                     );
           
							 
	wire [7:0] decod_out;
	wire [71:0] reg_out;
							 
	decoder_octo dcd (.data_in(wa3), .out_port(decod_out));

	register rg1 (.d_in(8'b0), .d_out(reg_out[7:0]),   .enable(we3 & decod_out[0]), .clk(CLK));
	register rg2 (.d_in(wd3),  .d_out(reg_out[15:8]),  .enable(we3 & decod_out[1]), .clk(CLK));
	register rg3 (.d_in(wd3),  .d_out(reg_out[23:16]), .enable(we3 & decod_out[2]), .clk(CLK));
	register rg4 (.d_in(wd3),  .d_out(reg_out[31:24]), .enable(we3 & decod_out[3]), .clk(CLK));
	register rg5 (.d_in(wd3),  .d_out(reg_out[39:32]), .enable(we3 & decod_out[4]), .clk(CLK));
	register rg6 (.d_in(wd3),  .d_out(reg_out[47:40]), .enable(we3 & decod_out[5]), .clk(CLK));
	register rg7 (.d_in(wd3),  .d_out(reg_out[55:48]), .enable(we3 & decod_out[6]), .clk(CLK));
	register rg8 (.d_in(wd3),  .d_out(reg_out[63:56]), .enable(we3 & decod_out[7]), .clk(CLK));
	
	register ra (.d_in(wd3), .d_out(reg_out[71:64]),   .enable(we3 & wa3 == 4'h8), .clk(CLK));
	
	demux8_8b demux1 (.data_in(reg_out), .sel(ra1), .data_out(rd1));
	demux8_8b demux2 (.data_in(reg_out), .sel(ra2), .data_out(rd2));
  
   assign LCD_exit = reg_out[71:0];
							 
endmodule