data/full_repos/permissive/495276914/Insmem.v
data/verilator_xmls/62b49f4d-5ab4-444c-a9b8-924d2ae10d7a.xml
module Insmem(clk,PC,ins);
    input clk;
    input[31:0] PC;
    output reg[31:0] ins;
   
   reg[31:0] mem[0:50];
   
   wire[31:0] nop;
   assign nop = 32'h00000033;
   
   initial
    begin
        ins=0;
        $readmemh("D:/arpRISC/dock/code/RISCV-RV32I-Assembler/src/outfile.txt", mem);        
    end
    
    always @(negedge clk)begin       
          ins = mem[{2'b0,PC[31:2]}];    
    end  
      
endmodule
module Insmem(clk,PC,ins);

    input clk;
    input[31:0] PC;
    output reg[31:0] ins;
   
   reg[31:0] mem[0:50];
   
   wire[31:0] nop;
   assign nop = 32'h00000033;
   
   initial
    begin
        ins=0;
        $readmemh("D:/arpRISC/dock/code/RISCV-RV32I-Assembler/src/outfile.txt", mem);        
    end
    
    always @(negedge clk)begin       
          ins = mem[{2'b0,PC[31:2]}];    
    end  
      
endmodule