data/full_repos/permissive/496266817/rtl/endianCvt.v
1: b"%Error: data/full_repos/permissive/496266817/rtl/endianCvt.v:9: Cannot find file containing module: 'endianCvt32'\n endianCvt32 en(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/rtl,data/full_repos/permissive/496266817/endianCvt32\n             data/full_repos/permissive/496266817/rtl,data/full_repos/permissive/496266817/endianCvt32.v\n             data/full_repos/permissive/496266817/rtl,data/full_repos/permissive/496266817/endianCvt32.sv\n             endianCvt32\n             endianCvt32.v\n             endianCvt32.sv\n             obj_dir/endianCvt32\n             obj_dir/endianCvt32.v\n             obj_dir/endianCvt32.sv\n%Error: Exiting due to 1 error(s)\n"
module endianCvt(in, out);
	input	wire	[1023:0]in;
	output	wire	[1023:0]out;

genvar i;
generate for (i = 0 ; i < 32 ; i = i + 1) begin: GEN_ENDIAN
	endianCvt32 en(
				in [((i+1)*(32)-1):((i)*(32))],
				out[((i+1)*(32)-1):((i)*(32))]
				);
	end
endgenerate

endmodule
module endianCvt(in, out);

	input	wire	[1023:0]in;
	output	wire	[1023:0]out;

genvar i;
generate for (i = 0 ; i < 32 ; i = i + 1) begin: GEN_ENDIAN
	endianCvt32 en(
				in [((i+1)*(32)-1):((i)*(32))],
				out[((i+1)*(32)-1):((i)*(32))]
				);
	end
endgenerate

endmodule