data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/pulse_button.v
data/verilator_xmls/73a8f735-4471-4ae9-a313-727534f83501.xml
module pulse_button(
	input clk,
	input reset,
	input button,
	output pulse);

wire currentValue_q;
wire currentValue_not_q;
wire previousValue_q;
wire previousValue_not_q;

biestable_d currentValue(
	.clk(clk),
	.reset(reset),
	.d(button),
	.q(currentValue_q),
	.not_q(currentValue_not_q)
);

biestable_d previousValue(
	.clk(clk),
	.reset(reset),
	.d(currentValue_q),
	.q(previousValue_q),
	.not_q(previousValue_not_q)
);

and_gate and1(
	.a(currentValue_q),
	.b(previousValue_not_q),
	.c(pulse)
);

endmodule
module pulse_button(
	input clk,
	input reset,
	input button,
	output pulse);


wire currentValue_q;
wire currentValue_not_q;
wire previousValue_q;
wire previousValue_not_q;

biestable_d currentValue(
	.clk(clk),
	.reset(reset),
	.d(button),
	.q(currentValue_q),
	.not_q(currentValue_not_q)
);

biestable_d previousValue(
	.clk(clk),
	.reset(reset),
	.d(currentValue_q),
	.q(previousValue_q),
	.not_q(previousValue_not_q)
);

and_gate and1(
	.a(currentValue_q),
	.b(previousValue_not_q),
	.c(pulse)
);

endmodule