data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare/less_than_unsign_Nb.v
data/verilator_xmls/a01059aa-2426-406e-98dc-2ae1f6b22d0e.xml
module less_than_unsign_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output [N-1:0] r
);

wire [N-1:0] w0 = ~( a ^ b );
wire [N-1:0] w1 =  ( ~a & b );
wire [N-1:0] w2;

assign w2[0] = w1[0];
assign r = { {N-1{1'b0}} , w2[N-1]};

genvar i;
generate 
	for (i = 1; i < N; i = i + 1) begin
        assign w2[i] = w1[i] | ( w0[i] & w2[i-1] );
    end
endgenerate

endmodule
module less_than_unsign_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output [N-1:0] r
);


wire [N-1:0] w0 = ~( a ^ b );
wire [N-1:0] w1 =  ( ~a & b );
wire [N-1:0] w2;

assign w2[0] = w1[0];
assign r = { {N-1{1'b0}} , w2[N-1]};

genvar i;
generate 
	for (i = 1; i < N; i = i + 1) begin
        assign w2[i] = w1[i] | ( w0[i] & w2[i-1] );
    end
endgenerate

endmodule