data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:51: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:57: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,  \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:58: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:59: Define or directive not defined: \'`REG_WS_WIDTH\'\n    input wire [`REG_WS_WIDTH-1:0] ws,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:60: Define or directive not defined: \'`ENV_WIDTH\'\n    input wire [`ENV_WIDTH-1:0] env,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:62: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    input wire [`OP_OUT_WIDTH-1:0] modulation,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:64: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    output reg signed [`OP_OUT_WIDTH-1:0] out\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:72: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [0:`NUM_OPERATORS_PER_BANK-1];\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:72: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [0:`NUM_OPERATORS_PER_BANK-1];\n                                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:73: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-1:0] final_phase [0:`NUM_OPERATORS_PER_BANK-1];\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:73: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [`PHASE_ACC_WIDTH-1:0] final_phase [0:`NUM_OPERATORS_PER_BANK-1];\n                                              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:74: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:78: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire [`OP_OUT_WIDTH-1:0] tmp_out0;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:79: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:80: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:81: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:165: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n        3: tmp_out2 = final_phase[op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;\n                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:173: Define or directive not defined: \'`OP_NORMAL\'\n            `OP_NORMAL:    out <= tmp_out2;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:173: syntax error, unexpected \':\', expecting endcase\n            `OP_NORMAL:    out <= tmp_out2;\n                      ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/phase_generator.v:174: Define or directive not defined: \'`OP_BASS_DRUM\'\n            `OP_BASS_DRUM: out <= tmp_out2;\n            ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module phase_generator (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,  
    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire [`ENV_WIDTH-1:0] env,
    input wire key_on_pulse,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire [2:0] op_type,    
    output reg signed [`OP_OUT_WIDTH-1:0] out
);	
    localparam LOG_SIN_OUT_WIDTH = 12;
    localparam EXP_OUT_WIDTH = 10;
    localparam LOG_SIN_PLUS_GAIN_WIDTH = 13;
    localparam PIPELINE_DELAY = 2;     
    
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed;
    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [0:`NUM_OPERATORS_PER_BANK-1];
    reg [`PHASE_ACC_WIDTH-1:0] final_phase [0:`NUM_OPERATORS_PER_BANK-1];
    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;
    wire [LOG_SIN_OUT_WIDTH-1:0] log_sin_out; 
    wire [LOG_SIN_PLUS_GAIN_WIDTH-1:0] log_sin_plus_gain;     
    wire [EXP_OUT_WIDTH-1:0] exp_out;
    wire [`OP_OUT_WIDTH-1:0] tmp_out0;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;
    

    always @(posedge clk) begin
        if (reset)
            sample_clk_en_delayed <= 0;
        else begin
            sample_clk_en_delayed <= sample_clk_en_delayed << 1;
            sample_clk_en_delayed[0] <= sample_clk_en;
        end
    end
    

    calc_rhythm_phase calc_rhythm_phase (
        .clk(clk),
        .reset(reset),
        .sample_clk_en(sample_clk_en),
        .op_num(op_num),
        .phase_acc(phase_acc[op_num]),
        .phase_acc_17(phase_acc[17]),
        .phase_acc_13(phase_acc[13]),
        .op_type(op_type),    
        .rhythm_phase(rhythm_phase)
    );


    always @(posedge clk)
        if (reset) begin
            phase_acc[op_num] <= 0;
            final_phase[op_num] <= 0;
        end else if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (key_on_pulse) begin
                phase_acc[op_num] <= 0;
                final_phase[op_num] <= 0;
            end else begin
                phase_acc[op_num] <= phase_acc[op_num] + phase_inc;
                final_phase[op_num] <= rhythm_phase + phase_inc
                 + (modulation << 10);
            end
        
    assign tmp_ws2 = tmp_out1 < 0 ? ~tmp_out1 : tmp_out1;
                
    opl3_log_sine_lut log_sine_lut_inst (
        .theta(final_phase[op_num][18] ? ~final_phase[op_num][17:10]
         : final_phase[op_num][17:10]),
        .out(log_sin_out),
        .clk(clk),
        .reset(reset)
    );      
    
    assign log_sin_plus_gain = (log_sin_out) + (env << 3);
        
    opl3_exp_lut exp_lut_inst (
        .in(~log_sin_plus_gain[7:0]),
        .out(exp_out),
        .clk(clk),
        .reset(reset)
    );
    
    assign tmp_out0 = (2**10 + exp_out) << 1;
        
    always @ *
        if (final_phase[op_num][19])
            tmp_out1 = ~(tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]);
        else
            tmp_out1 = tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]; 
        

    always @ *
        case (ws)
        0: tmp_out2 = tmp_out1;
        1: tmp_out2 = tmp_out1 < 0 ? 0 : tmp_out1;
        2: tmp_out2 = tmp_ws2;
        3: tmp_out2 = final_phase[op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;
        endcase 
            
    always @(posedge clk)
        if (reset)
            out <= 0;
        else
            case (op_type)
            `OP_NORMAL:    out <= tmp_out2;
            `OP_BASS_DRUM: out <= tmp_out2;
            default:      out <= tmp_out2 << 1;
            endcase      
endmodule
module phase_generator (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,  
    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire [`ENV_WIDTH-1:0] env,
    input wire key_on_pulse,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire [2:0] op_type,    
    output reg signed [`OP_OUT_WIDTH-1:0] out
);
	
    localparam LOG_SIN_OUT_WIDTH = 12;
    localparam EXP_OUT_WIDTH = 10;
    localparam LOG_SIN_PLUS_GAIN_WIDTH = 13;
    localparam PIPELINE_DELAY = 2;     
    
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed;
    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [0:`NUM_OPERATORS_PER_BANK-1];
    reg [`PHASE_ACC_WIDTH-1:0] final_phase [0:`NUM_OPERATORS_PER_BANK-1];
    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;
    wire [LOG_SIN_OUT_WIDTH-1:0] log_sin_out; 
    wire [LOG_SIN_PLUS_GAIN_WIDTH-1:0] log_sin_plus_gain;     
    wire [EXP_OUT_WIDTH-1:0] exp_out;
    wire [`OP_OUT_WIDTH-1:0] tmp_out0;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;
    

    always @(posedge clk) begin
        if (reset)
            sample_clk_en_delayed <= 0;
        else begin
            sample_clk_en_delayed <= sample_clk_en_delayed << 1;
            sample_clk_en_delayed[0] <= sample_clk_en;
        end
    end
    

    calc_rhythm_phase calc_rhythm_phase (
        .clk(clk),
        .reset(reset),
        .sample_clk_en(sample_clk_en),
        .op_num(op_num),
        .phase_acc(phase_acc[op_num]),
        .phase_acc_17(phase_acc[17]),
        .phase_acc_13(phase_acc[13]),
        .op_type(op_type),    
        .rhythm_phase(rhythm_phase)
    );


    always @(posedge clk)
        if (reset) begin
            phase_acc[op_num] <= 0;
            final_phase[op_num] <= 0;
        end else if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (key_on_pulse) begin
                phase_acc[op_num] <= 0;
                final_phase[op_num] <= 0;
            end else begin
                phase_acc[op_num] <= phase_acc[op_num] + phase_inc;
                final_phase[op_num] <= rhythm_phase + phase_inc
                 + (modulation << 10);
            end
        
    assign tmp_ws2 = tmp_out1 < 0 ? ~tmp_out1 : tmp_out1;
                
    opl3_log_sine_lut log_sine_lut_inst (
        .theta(final_phase[op_num][18] ? ~final_phase[op_num][17:10]
         : final_phase[op_num][17:10]),
        .out(log_sin_out),
        .clk(clk),
        .reset(reset)
    );      
    
    assign log_sin_plus_gain = (log_sin_out) + (env << 3);
        
    opl3_exp_lut exp_lut_inst (
        .in(~log_sin_plus_gain[7:0]),
        .out(exp_out),
        .clk(clk),
        .reset(reset)
    );
    
    assign tmp_out0 = (2**10 + exp_out) << 1;
        
    always @ *
        if (final_phase[op_num][19])
            tmp_out1 = ~(tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]);
        else
            tmp_out1 = tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]; 
        

    always @ *
        case (ws)
        0: tmp_out2 = tmp_out1;
        1: tmp_out2 = tmp_out1 < 0 ? 0 : tmp_out1;
        2: tmp_out2 = tmp_ws2;
        3: tmp_out2 = final_phase[op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;
        endcase 
            
    always @(posedge clk)
        if (reset)
            out <= 0;
        else
            case (op_type)
            `OP_NORMAL:    out <= tmp_out2;
            `OP_BASS_DRUM: out <= tmp_out2;
            default:      out <= tmp_out2 << 1;
            endcase      
endmodule