data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100 clr_n = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #50 clr_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #100 up_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20 up_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20 clock_50 = ~clock_50;\n  ^\n%Error: data/full_repos/permissive/42499175/SourceFiles/TB_dimmer.v:13: Cannot find file containing module: \'dimmer\'\n dimmer U1(clock_50, clr_n, up_n, down_n, test, mode, leds, stepcounter, cyclecounter);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42499175/SourceFiles,data/full_repos/permissive/42499175/dimmer\n             data/full_repos/permissive/42499175/SourceFiles,data/full_repos/permissive/42499175/dimmer.v\n             data/full_repos/permissive/42499175/SourceFiles,data/full_repos/permissive/42499175/dimmer.sv\n             dimmer\n             dimmer.v\n             dimmer.sv\n             obj_dir/dimmer\n             obj_dir/dimmer.v\n             obj_dir/dimmer.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_dimmer();
	reg clock_50;
	reg up_n;
	reg down_n;
	reg test;
	reg mode;
	reg clr_n;
	wire [9:0] leds;
	wire [3:0] stepcounter;
	wire [17:0] cyclecounter;

	dimmer U1(clock_50, clr_n, up_n, down_n, test, mode, leds, stepcounter, cyclecounter);

	initial begin
		clock_50 = 0;
		clr_n = 1;
		up_n = 1;
		down_n = 1;
		test = 0;
		mode = 0;
		#100 clr_n = 0;
		#50 clr_n = 1;
		#100 up_n = 0;
		#20 up_n = 1;
	end

	always begin
		#20 clock_50 = ~clock_50;
	end
endmodule
module TB_dimmer();

	reg clock_50;
	reg up_n;
	reg down_n;
	reg test;
	reg mode;
	reg clr_n;
	wire [9:0] leds;
	wire [3:0] stepcounter;
	wire [17:0] cyclecounter;

	dimmer U1(clock_50, clr_n, up_n, down_n, test, mode, leds, stepcounter, cyclecounter);

	initial begin
		clock_50 = 0;
		clr_n = 1;
		up_n = 1;
		down_n = 1;
		test = 0;
		mode = 0;
		#100 clr_n = 0;
		#50 clr_n = 1;
		#100 up_n = 0;
		#20 up_n = 1;
	end

	always begin
		#20 clock_50 = ~clock_50;
	end
endmodule