data/full_repos/permissive/466926510/Project_files/SUB_AB.v
data/verilator_xmls/a103be74-388c-46a3-af3a-7c35de2fe306.xml
module SUB_AB
#(parameter WIDTH3 = 8)
(A , B , OUT );
    
    input [WIDTH3-1:0] A, B ;
    output [WIDTH3-1:0] OUT ;
    
    assign OUT = A-B ;
endmodule
module SUB_AB
#(parameter WIDTH3 = 8)
(A , B , OUT );

    
    input [WIDTH3-1:0] A, B ;
    output [WIDTH3-1:0] OUT ;
    
    assign OUT = A-B ;
endmodule