data/full_repos/permissive/494696040/Adder_with_shift_left.v
data/verilator_xmls/7bf383e1-e048-4798-a3de-6dee05f6c3da.xml
module Adder_with_left_shift(
    input wire [31:0] A,
    input wire [31:0] B,
    output wire [31:0] out
    );

   assign out = A + (B << 2);

endmodule
module Adder_with_left_shift(
    input wire [31:0] A,
    input wire [31:0] B,
    output wire [31:0] out
    );


   assign out = A + (B << 2);

endmodule