data/full_repos/permissive/443770883/lab8/rough/mproc.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/443770883/lab8/rough/mproc.v:52: Signal definition not found, creating implicitly: \'load_ir\'\n  ir ir_0 (clk, reset, load_ir, ins, cur_ins);\n                       ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/443770883/lab8/rough/mproc.v:53: Signal definition not found, creating implicitly: \'wr_reg\'\n  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);\n                                                                                                          ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:39: Cannot find file containing module: \'or3\'\n or3 o1(cur_ins[11],cur_ins[12],cur_ins[13],t1);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab8/rough,data/full_repos/permissive/443770883/or3\n             data/full_repos/permissive/443770883/lab8/rough,data/full_repos/permissive/443770883/or3.v\n             data/full_repos/permissive/443770883/lab8/rough,data/full_repos/permissive/443770883/or3.sv\n             or3\n             or3.v\n             or3.sv\n             obj_dir/or3\n             obj_dir/or3.v\n             obj_dir/or3.sv\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:40: Cannot find file containing module: \'or3\'\n or3 o2(cur_ins[14],cur_ins[15],t1,t2);\n ^~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:41: Cannot find file containing module: \'invert\'\n invert o3(t2,t3);\n ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:42: Cannot find file containing module: \'dfsl\'\n dfsl g1(clk,reset,1\'b1,pc_inc,load_ir);\n ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:43: Cannot find file containing module: \'dfrl\'\n dfrl g2(clk,reset,1\'b1,load_ir,pc_inc);\n ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:44: Cannot find file containing module: \'and2\'\n and2 o4(pc_inc, t3,wr_reg);\n ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:2: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_0 (clk, reset, load, din[\'h0], dout[\'h0]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:3: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_1 (clk, reset, load, din[\'h1], dout[\'h1]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:4: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_2 (clk, reset, load, din[\'h2], dout[\'h2]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:5: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_3 (clk, reset, load, din[\'h3], dout[\'h3]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:6: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_4 (clk, reset, load, din[\'h4], dout[\'h4]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:7: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_5 (clk, reset, load, din[\'h5], dout[\'h5]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:8: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_6 (clk, reset, load, din[\'h6], dout[\'h6]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:9: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_7 (clk, reset, load, din[\'h7], dout[\'h7]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:10: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_8 (clk, reset, load, din[\'h8], dout[\'h8]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:11: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_9 (clk, reset, load, din[\'h9], dout[\'h9]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:12: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_a (clk, reset, load, din[\'ha], dout[\'ha]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:13: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_b (clk, reset, load, din[\'hb], dout[\'hb]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:14: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_c (clk, reset, load, din[\'hc], dout[\'hc]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:15: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_d (clk, reset, load, din[\'hd], dout[\'hd]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:16: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_e (clk, reset, load, din[\'he], dout[\'he]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:17: Cannot find file containing module: \'dfrl\'\n  dfrl dfrl_f (clk, reset, load, din[\'hf], dout[\'hf]);\n  ^~~~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:51: Cannot find file containing module: \'pc\'\n  pc pc_0 (clk, reset, pc_inc, 1\'b0, 1\'b0, 16\'b0, addr);\n  ^~\n%Error: data/full_repos/permissive/443770883/lab8/rough/mproc.v:54: Cannot find file containing module: \'reg_alu\'\n  reg_alu reg_alu_0 (clk, reset, 1\'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16\'b0, d_out_a, d_out_b, cout);\n  ^~~~~~~\n%Error: Exiting due to 24 error(s), 2 warning(s)\n'
module mproc (input wire clk, reset, input wire [15:0] ins, output wire [15:0] addr);
  wire pc_inc, cout; wire [2:0] rd_addr_a, rd_addr_b, wr_addr; wire [1:0] op; wire [15:0] cur_ins, d_out_a, d_out_b;

  pc pc_0 (clk, reset, pc_inc, 1'b0, 1'b0, 16'b0, addr);
  ir ir_0 (clk, reset, load_ir, ins, cur_ins);
  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);
  reg_alu reg_alu_0 (clk, reset, 1'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16'b0, d_out_a, d_out_b, cout);
endmodule
module mproc (input wire clk, reset, input wire [15:0] ins, output wire [15:0] addr);

  wire pc_inc, cout; wire [2:0] rd_addr_a, rd_addr_b, wr_addr; wire [1:0] op; wire [15:0] cur_ins, d_out_a, d_out_b;

  pc pc_0 (clk, reset, pc_inc, 1'b0, 1'b0, 16'b0, addr);
  ir ir_0 (clk, reset, load_ir, ins, cur_ins);
  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);
  reg_alu reg_alu_0 (clk, reset, 1'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16'b0, d_out_a, d_out_b, cout);
endmodule