data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                             : ... In instance axi_address_decoder_BR\n  req_mask = 1\'sb0;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_address_decoder_BR.v:33: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                             : ... In instance axi_address_decoder_BR\n   rvalid_o = 1\'sb0;\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module axi_address_decoder_BR 
#(
   parameter N_TARG_PORT     = 8,
   parameter AXI_ID_IN       = 16,
   parameter AXI_ID_OUT      = AXI_ID_IN+$clog2(N_TARG_PORT)
)
(
	rid_i,
	rvalid_i,
	rready_o,
	rvalid_o,
	rready_i
);



	input wire [AXI_ID_OUT - 1:0] rid_i;
	input wire rvalid_i;
	output reg rready_o;
	output reg [N_TARG_PORT - 1:0] rvalid_o;
	input wire [N_TARG_PORT - 1:0] rready_i;
	reg [N_TARG_PORT - 1:0] req_mask;
	wire [$clog2(N_TARG_PORT) - 1:0] ROUTING;
	assign ROUTING = rid_i[(AXI_ID_IN + $clog2(N_TARG_PORT)) - 1:AXI_ID_IN];
	always @(*) begin
		req_mask = 1'sb0;
		req_mask[ROUTING] = 1'b1;
	end
	always @(*) begin
		if (rvalid_i)
			rvalid_o = {N_TARG_PORT {rvalid_i}} & req_mask;
		else
			rvalid_o = 1'sb0;
		rready_o = |(rready_i & req_mask);
	end
endmodule
module axi_address_decoder_BR 
#(
   parameter N_TARG_PORT     = 8,
   parameter AXI_ID_IN       = 16,
   parameter AXI_ID_OUT      = AXI_ID_IN+$clog2(N_TARG_PORT)
)
(
	rid_i,
	rvalid_i,
	rready_o,
	rvalid_o,
	rready_i
);




	input wire [AXI_ID_OUT - 1:0] rid_i;
	input wire rvalid_i;
	output reg rready_o;
	output reg [N_TARG_PORT - 1:0] rvalid_o;
	input wire [N_TARG_PORT - 1:0] rready_i;
	reg [N_TARG_PORT - 1:0] req_mask;
	wire [$clog2(N_TARG_PORT) - 1:0] ROUTING;
	assign ROUTING = rid_i[(AXI_ID_IN + $clog2(N_TARG_PORT)) - 1:AXI_ID_IN];
	always @(*) begin
		req_mask = 1'sb0;
		req_mask[ROUTING] = 1'b1;
	end
	always @(*) begin
		if (rvalid_i)
			rvalid_o = {N_TARG_PORT {rvalid_i}} & req_mask;
		else
			rvalid_o = 1'sb0;
		rready_o = |(rready_i & req_mask);
	end
endmodule