data/full_repos/permissive/462122681/conFF.v
1: b'%Error: data/full_repos/permissive/462122681/conFF.v:11: Cannot find file containing module: \'decoder_2_4\'\n decoder_2_4 decoder(c2,decoder_out);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_2_4\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_2_4.v\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_2_4.sv\n             decoder_2_4\n             decoder_2_4.v\n             decoder_2_4.sv\n             obj_dir/decoder_2_4\n             obj_dir/decoder_2_4.v\n             obj_dir/decoder_2_4.sv\n%Warning-WIDTH: data/full_repos/permissive/462122681/conFF.v:13: Operator NOT expects 32 bits on the LHS, but LHS\'s REDXOR generates 1 bits.\n                                                               : ... In instance conFF\n assign busa = ~(^bus_in);\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/462122681/conFF.v:15: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                               : ... In instance conFF\n assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/conFF.v:15: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                               : ... In instance conFF\n assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/conFF.v:15: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                               : ... In instance conFF\n assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);\n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/conFF.v:15: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                               : ... In instance conFF\n assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);\n                                                                                                                        ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module conFF(
	input [1:0] c2,
	input [31:0] bus_in,
	input conin,
	output [31:0]con_out

);
	wire [3:0] decoder_out;
	wire[31:0] busa;
	
	decoder_2_4 decoder(c2,decoder_out);
		
	assign busa = ~(^bus_in);

	assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);
	
endmodule
module conFF(
	input [1:0] c2,
	input [31:0] bus_in,
	input conin,
	output [31:0]con_out

);

	wire [3:0] decoder_out;
	wire[31:0] busa;
	
	decoder_2_4 decoder(c2,decoder_out);
		
	assign busa = ~(^bus_in);

	assign con_out = (decoder_out[0] & busa) | (decoder_out[1] & (~busa)) | (decoder_out[2] & (~bus_in)) | (decoder_out[3] & bus_in);
	
endmodule