data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit unsigned multiplier using wallace tree/multi_8bit_unsigned.v
1: b'%Error: Cannot find file containing module: unsigned\n        ... Looked in:\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned.v\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned.sv\n             unsigned\n             unsigned.v\n             unsigned.sv\n             obj_dir/unsigned\n             obj_dir/unsigned.v\n             obj_dir/unsigned.sv\n%Error: Cannot find file containing module: multiplier\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: wallace\n%Error: Cannot find file containing module: tree,data/full_repos/permissive/405799749\n%Error: Cannot find file containing module: data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit\n%Error: Cannot find file containing module: tree/multi_8bit_unsigned.v\n%Error: Exiting due to 7 error(s)\n'
module multi_8bit_unsigned(prod,a,b,clk,rst,load);
	output [15:0] prod;
	input [7:0] a,b;
	input clk,rst,load;
	wire [2:0] xi;
	wire [1:0] mr_sel;
	wire cla_sub; 
	wire [10:0] md;
	wire [9:0] ad,bd;
	assign ad = {2'd0,a};
	assign bd = {2'd0,b};
	piso_2bit p2b1(.sout(xi),.pin(bd),.load(load),.clk(clk),.rst(rst));
	reco_unit ru(.op(mr_sel),.sign(cla_sub),.xi(xi));
	mux_4x1 m41(.dout(md),.d0(11'd0),.d1({ad[9],ad}),.d2({ad,1'b0}),.d3(11'd0),.sel(mr_sel));
	accumulator a1(.res(prod),.md(md),.cla_sub(cla_sub),.load(load),.clk(clk),.rst(rst));
endmodule
module multi_8bit_unsigned(prod,a,b,clk,rst,load);

	output [15:0] prod;
	input [7:0] a,b;
	input clk,rst,load;
	wire [2:0] xi;
	wire [1:0] mr_sel;
	wire cla_sub; 
	wire [10:0] md;
	wire [9:0] ad,bd;
	assign ad = {2'd0,a};
	assign bd = {2'd0,b};
	piso_2bit p2b1(.sout(xi),.pin(bd),.load(load),.clk(clk),.rst(rst));
	reco_unit ru(.op(mr_sel),.sign(cla_sub),.xi(xi));
	mux_4x1 m41(.dout(md),.d0(11'd0),.d1({ad[9],ad}),.d2({ad,1'b0}),.d3(11'd0),.sel(mr_sel));
	accumulator a1(.res(prod),.md(md),.cla_sub(cla_sub),.load(load),.clk(clk),.rst(rst));
endmodule