data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/Dualedge/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/Dualedge,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Dualedge/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire d,
    output wire q
);

  reg qp = 1'b0;
  reg qn = 1'b0;

  always @(posedge clk) begin
    qp <= d ^ qn;
  end

  always @(negedge clk) begin
    qn <= d ^ qp;
  end

  assign q = qp ^ qn;

endmodule
module top_module (
    input  wire clk,
    input  wire d,
    output wire q
);


  reg qp = 1'b0;
  reg qn = 1'b0;

  always @(posedge clk) begin
    qp <= d ^ qn;
  end

  always @(negedge clk) begin
    qn <= d ^ qp;
  end

  assign q = qp ^ qn;

endmodule