data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_03.v
data/verilator_xmls/3a3d9a7e-cac9-4b7d-8613-0b2f0de8c848.xml
module test(input  [3:0] A, B,
            output [3:0] Y, Z);
assign Y = A + B, Z = B + A;
endmodule
module test(input  [3:0] A, B,
            output [3:0] Y, Z);

assign Y = A + B, Z = B + A;
endmodule