data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src/uart2wb.sv
1: b"%Error: data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src/uart2wb.sv:131: Cannot find file containing module: 'async_reg_bus'\nasync_reg_bus #(.AW(32), .DW(32),.BEW(4))\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src,data/full_repos/permissive/432384243/async_reg_bus\n             data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src,data/full_repos/permissive/432384243/async_reg_bus.v\n             data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src,data/full_repos/permissive/432384243/async_reg_bus.sv\n             async_reg_bus\n             async_reg_bus.v\n             async_reg_bus.sv\n             obj_dir/async_reg_bus\n             obj_dir/async_reg_bus.v\n             obj_dir/async_reg_bus.sv\n%Error: data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src/uart2wb.sv:166: Cannot find file containing module: 'uart2_core'\nuart2_core u_core (  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/rtl/uart2wb/src/uart2wb.sv:203: Cannot find file containing module: 'uart_msg_handler'\nuart_msg_handler u_msg (  \n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart2wb (  
        input wire                  arst_n          ,
        input wire                  app_clk         ,


       input wire                  cfg_tx_enable    ,
       input wire                  cfg_rx_enable    ,
       input wire                  cfg_stop_bit     ,
       input wire [1:0]            cfg_pri_mod      ,
       input wire [11:0]	    cfg_baud_16x     ,


       output   wire                wbm_cyc_o        ,
       output   wire                wbm_stb_o        ,
       output   wire [31:0]         wbm_adr_o        ,
       output   wire                wbm_we_o         ,
       output   wire [31:0]         wbm_dat_o        ,
       output   wire [3:0]          wbm_sel_o        ,
       input    wire [31:0]         wbm_dat_i        ,
       input    wire                wbm_ack_i        ,
       input    wire                wbm_err_i        ,


       output   wire               frm_error        ,
       output   wire       	    par_error        ,

       output   wire               baud_clk_16x     ,


       input    wire              rxd               ,
       output   wire              txd

     );











wire  [31:0]       reg_addr        ;
wire  [31:0]       reg_wdata       ;
wire               reg_req         ;
wire               reg_wr          ;
wire               reg_ack         ;
wire   [31:0]      reg_rdata       ;



wire              tx_data_avail    ;
wire [7:0]        tx_data          ;
wire              tx_rd            ;





wire         rx_ready              ;
wire [7:0]  rx_data                ;
wire        rx_wr                  ;

wire        line_reset_n           ;

assign wbm_cyc_o  = wbm_stb_o;




async_reg_bus #(.AW(32), .DW(32),.BEW(4))
          u_async_reg_bus (

          .in_clk                    (baud_clk_16x),
          .in_reset_n                (line_reset_n),


          .in_reg_rdata               (reg_rdata),
          .in_reg_ack                 (reg_ack),
          .in_reg_timeout             (),


          .in_reg_cs                  (reg_req),
          .in_reg_addr                (reg_addr),
          .in_reg_wdata               (reg_wdata),
          .in_reg_wr                  (reg_wr),
          .in_reg_be                  (4'hF),


          .out_clk                    (app_clk),
          .out_reset_n                (arst_n),


          .out_reg_cs                 (wbm_stb_o),
          .out_reg_addr               (wbm_adr_o),
          .out_reg_wdata              (wbm_dat_o),
          .out_reg_wr                 (wbm_we_o),
          .out_reg_be                 (wbm_sel_o),


          .out_reg_rdata              (wbm_dat_i),
          .out_reg_ack                (wbm_ack_i)
   );


uart2_core u_core (  
          .arst_n            (arst_n) ,
          .app_clk           (app_clk) ,


          .cfg_tx_enable      (cfg_tx_enable) , 
          .cfg_rx_enable      (cfg_rx_enable) , 
          .cfg_stop_bit       (cfg_stop_bit)  , 
          .cfg_pri_mod        (cfg_pri_mod)   , 
	  .cfg_baud_16x       (cfg_baud_16x)  ,


          .tx_data_avail      (tx_data_avail) ,
          .tx_rd              (tx_rd)         ,
          .tx_data            (tx_data)       ,
         


          .rx_ready           (rx_ready)      ,
          .rx_wr              (rx_wr)         ,
          .rx_data            (rx_data)       ,


          .frm_error          (frm_error) ,
	  .par_error          (par_error) ,

	  .baud_clk_16x       (baud_clk_16x) ,
	  .line_reset_n       (line_reset_n),


          .rxd                (rxd) ,
          .txd                (txd) 

     );



uart_msg_handler u_msg (  
          .reset_n            (arst_n ) ,
          .sys_clk            (baud_clk_16x ) ,



          .tx_data_avail      (tx_data_avail) ,
          .tx_rd              (tx_rd) ,
          .tx_data            (tx_data) ,
         


          .rx_ready           (rx_ready) ,
          .rx_wr              (rx_wr) ,
          .rx_data            (rx_data) ,


          .reg_addr          (reg_addr),
          .reg_wr            (reg_wr),
          .reg_wdata         (reg_wdata),
          .reg_req           (reg_req),
          .reg_ack           (reg_ack),
	  .reg_rdata         (reg_rdata) 

     );

endmodule
module uart2wb (  
        input wire                  arst_n          ,
        input wire                  app_clk         ,


       input wire                  cfg_tx_enable    ,
       input wire                  cfg_rx_enable    ,
       input wire                  cfg_stop_bit     ,
       input wire [1:0]            cfg_pri_mod      ,
       input wire [11:0]	    cfg_baud_16x     ,


       output   wire                wbm_cyc_o        ,
       output   wire                wbm_stb_o        ,
       output   wire [31:0]         wbm_adr_o        ,
       output   wire                wbm_we_o         ,
       output   wire [31:0]         wbm_dat_o        ,
       output   wire [3:0]          wbm_sel_o        ,
       input    wire [31:0]         wbm_dat_i        ,
       input    wire                wbm_ack_i        ,
       input    wire                wbm_err_i        ,


       output   wire               frm_error        ,
       output   wire       	    par_error        ,

       output   wire               baud_clk_16x     ,


       input    wire              rxd               ,
       output   wire              txd

     );












wire  [31:0]       reg_addr        ;
wire  [31:0]       reg_wdata       ;
wire               reg_req         ;
wire               reg_wr          ;
wire               reg_ack         ;
wire   [31:0]      reg_rdata       ;



wire              tx_data_avail    ;
wire [7:0]        tx_data          ;
wire              tx_rd            ;





wire         rx_ready              ;
wire [7:0]  rx_data                ;
wire        rx_wr                  ;

wire        line_reset_n           ;

assign wbm_cyc_o  = wbm_stb_o;




async_reg_bus #(.AW(32), .DW(32),.BEW(4))
          u_async_reg_bus (

          .in_clk                    (baud_clk_16x),
          .in_reset_n                (line_reset_n),


          .in_reg_rdata               (reg_rdata),
          .in_reg_ack                 (reg_ack),
          .in_reg_timeout             (),


          .in_reg_cs                  (reg_req),
          .in_reg_addr                (reg_addr),
          .in_reg_wdata               (reg_wdata),
          .in_reg_wr                  (reg_wr),
          .in_reg_be                  (4'hF),


          .out_clk                    (app_clk),
          .out_reset_n                (arst_n),


          .out_reg_cs                 (wbm_stb_o),
          .out_reg_addr               (wbm_adr_o),
          .out_reg_wdata              (wbm_dat_o),
          .out_reg_wr                 (wbm_we_o),
          .out_reg_be                 (wbm_sel_o),


          .out_reg_rdata              (wbm_dat_i),
          .out_reg_ack                (wbm_ack_i)
   );


uart2_core u_core (  
          .arst_n            (arst_n) ,
          .app_clk           (app_clk) ,


          .cfg_tx_enable      (cfg_tx_enable) , 
          .cfg_rx_enable      (cfg_rx_enable) , 
          .cfg_stop_bit       (cfg_stop_bit)  , 
          .cfg_pri_mod        (cfg_pri_mod)   , 
	  .cfg_baud_16x       (cfg_baud_16x)  ,


          .tx_data_avail      (tx_data_avail) ,
          .tx_rd              (tx_rd)         ,
          .tx_data            (tx_data)       ,
         


          .rx_ready           (rx_ready)      ,
          .rx_wr              (rx_wr)         ,
          .rx_data            (rx_data)       ,


          .frm_error          (frm_error) ,
	  .par_error          (par_error) ,

	  .baud_clk_16x       (baud_clk_16x) ,
	  .line_reset_n       (line_reset_n),


          .rxd                (rxd) ,
          .txd                (txd) 

     );



uart_msg_handler u_msg (  
          .reset_n            (arst_n ) ,
          .sys_clk            (baud_clk_16x ) ,



          .tx_data_avail      (tx_data_avail) ,
          .tx_rd              (tx_rd) ,
          .tx_data            (tx_data) ,
         


          .rx_ready           (rx_ready) ,
          .rx_wr              (rx_wr) ,
          .rx_data            (rx_data) ,


          .reg_addr          (reg_addr),
          .reg_wr            (reg_wr),
          .reg_wdata         (reg_wdata),
          .reg_req           (reg_req),
          .reg_ack           (reg_ack),
	  .reg_rdata         (reg_rdata) 

     );

endmodule