data/full_repos/permissive/414867793/Universal_Gates/Or_Gate/OR_G.v
data/verilator_xmls/0f8c4c94-27fa-4664-bec0-960a950c7978.xml
module OR_G(A,B,C);
input A,B;
output C;
assign C=A|B;


endmodule
module OR_G(A,B,C);

input A,B;
output C;
assign C=A|B;


endmodule