data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:11: Unsupported or unknown PLI call: $monitor\n  $monitor("rst %b en %b updown %b cnt %b overflow %b",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20 up_down = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #30 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
 reg clk;
 reg reset;
 reg enable;
 reg up_down;

 wire [7 : 0] count;
 wire overflow;

initial begin
  $monitor("rst %b en %b updown %b cnt %b overflow %b",
     reset,enable,up_down,count, overflow);
  clk = 0;
  reset = 1;
  enable = 0;
  up_down = 0;
  #10 reset = 0;
  #1 enable = 1;
  #20 up_down = 1;
  #30 $finish;
end

always #1 clk = ~clk;

lfsr_updown U(
.clk      ( clk      ),
.reset    ( reset    ),
.enable   ( enable   ),
.up_down  ( up_down  ),
.count    ( count    ),
.overflow ( overflow )
);

endmodule
module tb();

 reg clk;
 reg reset;
 reg enable;
 reg up_down;

 wire [7 : 0] count;
 wire overflow;

initial begin
  $monitor("rst %b en %b updown %b cnt %b overflow %b",
     reset,enable,up_down,count, overflow);
  clk = 0;
  reset = 1;
  enable = 0;
  up_down = 0;
  #10 reset = 0;
  #1 enable = 1;
  #20 up_down = 1;
  #30 $finish;
end

always #1 clk = ~clk;

lfsr_updown U(
.clk      ( clk      ),
.reset    ( reset    ),
.enable   ( enable   ),
.up_down  ( up_down  ),
.count    ( count    ),
.overflow ( overflow )
);

endmodule