data/full_repos/permissive/514775464/inputCapture.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514775464/inputCapture.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                      : ... In instance input_capture\n       val<=4\'b0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module input_capture(sig,clk,val,rst,rstVal,intFlag,rstIntFlag);
  input clk,rst,sig,rstVal,rstIntFlag;
  output reg [7:0] val;
  output reg intFlag;
  
  wire [7:0] tempCount;
  counter ct(.clk(clk),.count(tempCount),.reset(rst));
  initial intFlag=1'b0;
  
  always@(posedge sig or posedge rstVal or posedge rstIntFlag) begin
    if(rstVal)
      	val<=4'b0;
    else begin
    	val<=tempCount;
      	intFlag<=1'b1;
    end
    if(rstIntFlag)
      intFlag<=1'b0;
    
  end
endmodule
module input_capture(sig,clk,val,rst,rstVal,intFlag,rstIntFlag);

  input clk,rst,sig,rstVal,rstIntFlag;
  output reg [7:0] val;
  output reg intFlag;
  
  wire [7:0] tempCount;
  counter ct(.clk(clk),.count(tempCount),.reset(rst));
  initial intFlag=1'b0;
  
  always@(posedge sig or posedge rstVal or posedge rstIntFlag) begin
    if(rstVal)
      	val<=4'b0;
    else begin
    	val<=tempCount;
      	intFlag<=1'b1;
    end
    if(rstIntFlag)
      intFlag<=1'b0;
    
  end
endmodule