data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #40 iA=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #40 iA=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #40 iA=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #40 iA=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #40 iB=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #40 iB=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #40 iB=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #40 iB=0;\n    ^\n%Error: data/full_repos/permissive/486598419/6.1/logic_gates_1_tb.v:46: Cannot find file containing module: \'logic_gates_1\'\n  logic_gates_1\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/logic_gates_1\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/logic_gates_1.v\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/logic_gates_1.sv\n             logic_gates_1\n             logic_gates_1.v\n             logic_gates_1.sv\n             obj_dir/logic_gates_1\n             obj_dir/logic_gates_1.v\n             obj_dir/logic_gates_1.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module logic_gates_1_tb;
  reg iA;
  reg iB;
  wire oAnd;
  wire oOr;
  wire oNot;
  
  initial
  begin
    iA=0;
    #40 iA=1;
    #40 iA=0;
    #40 iA=1;
    #40 iA=0;
  end
  initial
  begin
    iB=0;
    #40 iB=0;
    #40 iB=1;
    #40 iB=1;
    #40 iB=0;
  end
  logic_gates_1
  logic_gates_inst(
     .iA(iA),
     .iB(iB),
     .oAnd(oAnd),
     .oOr(oOr),
     .oNot(oNot)
     ); 
endmodule
module logic_gates_1_tb;

  reg iA;
  reg iB;
  wire oAnd;
  wire oOr;
  wire oNot;
  
  initial
  begin
    iA=0;
    #40 iA=1;
    #40 iA=0;
    #40 iA=1;
    #40 iA=0;
  end
  initial
  begin
    iB=0;
    #40 iB=0;
    #40 iB=1;
    #40 iB=1;
    #40 iB=0;
  end
  logic_gates_1
  logic_gates_inst(
     .iA(iA),
     .iB(iB),
     .oAnd(oAnd),
     .oOr(oOr),
     .oNot(oNot)
     ); 
endmodule