data/full_repos/permissive/441359809/src/yosys/tests/simple/constpower.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/constpower.v:10: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s POWSS generates 32 bits.\n                                                                                           : ... In instance constpower\n  assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4);\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/constpower.v:11: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s POW generates 32 bits.\n                                                                                           : ... In instance constpower\n  assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j);\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module constpower(ys, yu);

output [8*8*8-1:0] ys, yu;

genvar i, j;

generate
	for (i = 0; i < 8; i = i+1)
	for (j = 0; j < 8; j = j+1) begin:V
		assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4);
		assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j);
	end
endgenerate

endmodule
module constpower(ys, yu);


output [8*8*8-1:0] ys, yu;

genvar i, j;

generate
	for (i = 0; i < 8; i = i+1)
	for (j = 0; j < 8; j = j+1) begin:V
		assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4);
		assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j);
	end
endgenerate

endmodule