data/full_repos/permissive/491371210/sources/synthesis/top.v
data/verilator_xmls/88f41cad-9394-4a6f-9d9e-0227b08a69eb.xml
module top # () (
        

        input sysRstb,
        input sysClk,
                

        input [3:0] sw,
        input [3:0] btn,
        

        output [3:0] led,
        output [11:0] ledRGB
    );
    




    





    


    reg [23:0] rCount = 0;
        
    



    

    assign led[1] = btn[1];
    assign led[2] = btn[2];
    assign led[3] = btn[3];
    

    assign ledRGB[0] = sw[0];
    assign ledRGB[1] = sw[1];
    assign ledRGB[2] = sw[2];
    

    assign led[0] = rCount[23];
    
    
    



    

    always @ (posedge(sysClk)) begin
        rCount <= rCount + 1;
    end

endmodule
module top # () (
        

        input sysRstb,
        input sysClk,
                

        input [3:0] sw,
        input [3:0] btn,
        

        output [3:0] led,
        output [11:0] ledRGB
    );

    




    





    


    reg [23:0] rCount = 0;
        
    



    

    assign led[1] = btn[1];
    assign led[2] = btn[2];
    assign led[3] = btn[3];
    

    assign ledRGB[0] = sw[0];
    assign ledRGB[1] = sw[1];
    assign ledRGB[2] = sw[2];
    

    assign led[0] = rCount[23];
    
    
    



    

    always @ (posedge(sysClk)) begin
        rCount <= rCount + 1;
    end

endmodule