data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module SignExtend(immIn, immOut);
    input [15:0] immIn;
    output reg [31:0] immOut;

    always @(immIn) begin
        immOut <= {{16{immIn[15]}},immIn[15:0]};
    end
endmodule
module SignExtend(immIn, immOut);

    input [15:0] immIn;
    output reg [31:0] immOut;

    always @(immIn) begin
        immOut <= {{16{immIn[15]}},immIn[15:0]};
    end
endmodule