data/full_repos/permissive/431605717/Code/RV32IM/MEM_WB.v
data/verilator_xmls/83d27521-957f-4dec-8069-e991464889fa.xml
module memwbreg(clk,clrn,pc_i,inst_i,mem_out_i,alu_out_i,wreg_i,wr_i,memtoreg_i,pc_o,inst_o,mem_out_o,alu_out_o,wreg_o,wr_o,memtoreg_o);
    input             clk, clrn;
    input      [31:0] pc_i;
    input      [31:0] inst_i;
    input      [31:0] mem_out_i;
    input      [31:0] alu_out_i;
    input             wreg_i;
    input       [4:0] wr_i;
    input             memtoreg_i;


    output reg [31:0] pc_o;
    output reg [31:0] inst_o;
    output reg [31:0] mem_out_o;
    output reg [31:0] alu_out_o;
    output reg        wreg_o;
    output reg  [4:0] wr_o;
    output reg        memtoreg_o;
    
    
    always @ (posedge clk) begin
        if (clrn) begin
            pc_o       <= pc_i;
            inst_o     <= inst_i;
            mem_out_o  <= mem_out_i;
            alu_out_o  <= alu_out_i;
            wreg_o     <= wreg_i;
            wr_o       <= wr_i;
            memtoreg_o <= memtoreg_i;
        end
        else begin
            pc_o       <= 0;
            inst_o     <= 0;
            mem_out_o  <= 0;
            alu_out_o  <= 0;
            wreg_o     <= 0;
            wr_o       <= 0;
            memtoreg_o <= 0;
        end
    end
    
endmodule
module memwbreg(clk,clrn,pc_i,inst_i,mem_out_i,alu_out_i,wreg_i,wr_i,memtoreg_i,pc_o,inst_o,mem_out_o,alu_out_o,wreg_o,wr_o,memtoreg_o);

    input             clk, clrn;
    input      [31:0] pc_i;
    input      [31:0] inst_i;
    input      [31:0] mem_out_i;
    input      [31:0] alu_out_i;
    input             wreg_i;
    input       [4:0] wr_i;
    input             memtoreg_i;


    output reg [31:0] pc_o;
    output reg [31:0] inst_o;
    output reg [31:0] mem_out_o;
    output reg [31:0] alu_out_o;
    output reg        wreg_o;
    output reg  [4:0] wr_o;
    output reg        memtoreg_o;
    
    
    always @ (posedge clk) begin
        if (clrn) begin
            pc_o       <= pc_i;
            inst_o     <= inst_i;
            mem_out_o  <= mem_out_i;
            alu_out_o  <= alu_out_i;
            wreg_o     <= wreg_i;
            wr_o       <= wr_i;
            memtoreg_o <= memtoreg_i;
        end
        else begin
            pc_o       <= 0;
            inst_o     <= 0;
            mem_out_o  <= 0;
            alu_out_o  <= 0;
            wreg_o     <= 0;
            wr_o       <= 0;
            memtoreg_o <= 0;
        end
    end
    
endmodule