data/full_repos/permissive/486812922/src/dm.v
data/verilator_xmls/65f5c639-ba7b-494f-886b-2a0286be3fed.xml
module dm_4k( addr, din, DMWr, clk, dout );
input [11: 2] addr;
input [31: 0] din;
input DMWr;
input clk;
output [31: 0] dout;

reg [31: 0] mem[1023: 0];
integer i;

assign dout = mem[addr];

initial begin
    for (i = 0; i < 1024; i = i + 1) begin
        mem[i] <= 0;
    end
end

always @(negedge clk) begin
    if (DMWr == 1) begin
        mem[addr] <= din;
    end
end

endmodule
module dm_4k( addr, din, DMWr, clk, dout );

input [11: 2] addr;
input [31: 0] din;
input DMWr;
input clk;
output [31: 0] dout;

reg [31: 0] mem[1023: 0];
integer i;

assign dout = mem[addr];

initial begin
    for (i = 0; i < 1024; i = i + 1) begin
        mem[i] <= 0;
    end
end

always @(negedge clk) begin
    if (DMWr == 1) begin
        mem[addr] <= din;
    end
end

endmodule