data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/ece241_2013_q4/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/ece241_2013_q4,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/ece241_2013_q4/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  wire fr3;
  wire fr2;
  wire fr1;
  wire dfr;

  reg clk = 1'd1;
  reg reset = 1'd0;
  reg [3:1] s = 1'd1;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 s = 3'b000;
    #10 s = 3'b001;
    #10 s = 3'b011;
    #10 s = 3'b111;
    #10;
    #10 s = 3'b011;
    #10 s = 3'b001;
    #10 s = 3'b000;
    #50;
  end

  initial begin
    #300 reset = 1'b1;
    #10 reset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .s(s),
      .fr3(fr3),
      .fr2(fr2),
      .fr1(fr1),
      .dfr(dfr)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire fr3;
  wire fr2;
  wire fr1;
  wire dfr;

  reg clk = 1'd1;
  reg reset = 1'd0;
  reg [3:1] s = 1'd1;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 s = 3'b000;
    #10 s = 3'b001;
    #10 s = 3'b011;
    #10 s = 3'b111;
    #10;
    #10 s = 3'b011;
    #10 s = 3'b001;
    #10 s = 3'b000;
    #50;
  end

  initial begin
    #300 reset = 1'b1;
    #10 reset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .s(s),
      .fr3(fr3),
      .fr2(fr2),
      .fr1(fr1),
      .dfr(dfr)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule