data/full_repos/permissive/499494419/ma.v
data/verilator_xmls/df830673-0bda-488f-bde6-1fe79a74365c.xml
module ma(A,wa,ka,re) ;
    
    input A;
   
    output ka;
	 output wa;
	 output re;
	 
	 assign #10 ka=A;
	 assign #10 wa=A;
	 assign #10 re=wa;
	 


endmodule
module ma(A,wa,ka,re) ;

    
    input A;
   
    output ka;
	 output wa;
	 output re;
	 
	 assign #10 ka=A;
	 assign #10 wa=A;
	 assign #10 re=wa;
	 


endmodule