data/full_repos/permissive/479997390/src/EX.v
1: b"%Error: data/full_repos/permissive/479997390/src/EX.v:75: Cannot find file containing module: 'mux2'\n  mux2 #(.WIDTH(32)) U_ALUSRC (\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux2\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux2.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux2.sv\n             mux2\n             mux2.v\n             mux2.sv\n             obj_dir/mux2\n             obj_dir/mux2.v\n             obj_dir/mux2.sv\n%Error: data/full_repos/permissive/479997390/src/EX.v:82: Cannot find file containing module: 'mux4'\n  mux4 #(.WIDTH(32)) U_FORWARD1 (\n  ^~~~\n%Error: data/full_repos/permissive/479997390/src/EX.v:91: Cannot find file containing module: 'mux4'\n  mux4 #(.WIDTH(32)) U_FORWARD2 (\n  ^~~~\n%Error: data/full_repos/permissive/479997390/src/EX.v:100: Cannot find file containing module: 'ALUControl'\n  ALUControl U_ALUCONTROL (\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/EX.v:106: Cannot find file containing module: 'ALU_UsingAdder'\n  ALU_UsingAdder U_ALU (\n  ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module EX (

  RegData1,
  RegData2In,
  Imm32,
  Funct,


  Shamt,

  DataFromMEM,
  DataFromWB,

  ALUSrc,
  ALUOp,

  WriteRegAddrIn,


  MemReadIn,
  MemWriteIn,
  MemToRegIn,
  RegWriteIn,
  Forward1,
  Forward2,
  
  ALUOut,

  RegData2Out,
  WriteRegAddrOut,


  MemReadOut,
  MemWriteOut,
  MemToRegOut,
  RegWriteOut
);

  input [31:0]RegData1, RegData2In, Imm32, DataFromMEM, DataFromWB;
  input [5:0] Funct;

  input [4:0] Shamt;

  input ALUSrc;

  input [4:0] ALUOp, WriteRegAddrIn;
  inputMemReadIn, MemWriteIn;
  input MemToRegIn, RegWriteIn;
  input [1:0] Forward1, Forward2;
  output [31:0] ALUOut,RegData2Out;
  output [4:0] WriteRegAddrOut;
  outputMemReadOut, MemWriteOut;
  output MemToRegOut, RegWriteOut;

  wire Zero;
  wire [4:0] ALUCtrl;
  wire [31:0] ALUIn2, PCNewFromReg, ForwardedRegData1, ForwardedRegData2;

  assign WriteRegAddrOut = WriteRegAddrIn;

  assign MemReadOut = MemReadIn;
  assign MemWriteOut = MemWriteIn;
  assign MemToRegOut = MemToRegIn;
  assign RegData2Out = ForwardedRegData2;
  assign PCNewFromReg = ForwardedRegData1;
  assign RegWriteOut = RegWriteIn;








  mux2 #(.WIDTH(32)) U_ALUSRC (
    .d0(ForwardedRegData2),
    .d1(Imm32),
    .s(ALUSrc),
    .y(ALUIn2)
  );

  mux4 #(.WIDTH(32)) U_FORWARD1 (
    .d0(RegData1),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(32'h0),
    .s(Forward1),
    .y(ForwardedRegData1)
  );

  mux4 #(.WIDTH(32)) U_FORWARD2 (
    .d0(RegData2In),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(32'h0),
    .s(Forward2),
    .y(ForwardedRegData2)
  );

  ALUControl U_ALUCONTROL (
    .ALUOp(ALUOp),
    .Funct(Funct),
    .ALUCtrl(ALUCtrl)
  );

  ALU_UsingAdder U_ALU (
    .ALUIn1(ForwardedRegData1),
    .ALUIn2(ALUIn2),
    .ALUInShamt(Shamt),
    .ALUCtrl(ALUCtrl),
    .Zero(Zero),
    .ALUOut(ALUOut)
  );











































  
endmodule
module EX (

  RegData1,
  RegData2In,
  Imm32,
  Funct,


  Shamt,

  DataFromMEM,
  DataFromWB,

  ALUSrc,
  ALUOp,

  WriteRegAddrIn,


  MemReadIn,
  MemWriteIn,
  MemToRegIn,
  RegWriteIn,
  Forward1,
  Forward2,
  
  ALUOut,

  RegData2Out,
  WriteRegAddrOut,


  MemReadOut,
  MemWriteOut,
  MemToRegOut,
  RegWriteOut
);


  input [31:0]RegData1, RegData2In, Imm32, DataFromMEM, DataFromWB;
  input [5:0] Funct;

  input [4:0] Shamt;

  input ALUSrc;

  input [4:0] ALUOp, WriteRegAddrIn;
  inputMemReadIn, MemWriteIn;
  input MemToRegIn, RegWriteIn;
  input [1:0] Forward1, Forward2;
  output [31:0] ALUOut,RegData2Out;
  output [4:0] WriteRegAddrOut;
  outputMemReadOut, MemWriteOut;
  output MemToRegOut, RegWriteOut;

  wire Zero;
  wire [4:0] ALUCtrl;
  wire [31:0] ALUIn2, PCNewFromReg, ForwardedRegData1, ForwardedRegData2;

  assign WriteRegAddrOut = WriteRegAddrIn;

  assign MemReadOut = MemReadIn;
  assign MemWriteOut = MemWriteIn;
  assign MemToRegOut = MemToRegIn;
  assign RegData2Out = ForwardedRegData2;
  assign PCNewFromReg = ForwardedRegData1;
  assign RegWriteOut = RegWriteIn;








  mux2 #(.WIDTH(32)) U_ALUSRC (
    .d0(ForwardedRegData2),
    .d1(Imm32),
    .s(ALUSrc),
    .y(ALUIn2)
  );

  mux4 #(.WIDTH(32)) U_FORWARD1 (
    .d0(RegData1),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(32'h0),
    .s(Forward1),
    .y(ForwardedRegData1)
  );

  mux4 #(.WIDTH(32)) U_FORWARD2 (
    .d0(RegData2In),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(32'h0),
    .s(Forward2),
    .y(ForwardedRegData2)
  );

  ALUControl U_ALUCONTROL (
    .ALUOp(ALUOp),
    .Funct(Funct),
    .ALUCtrl(ALUCtrl)
  );

  ALU_UsingAdder U_ALU (
    .ALUIn1(ForwardedRegData1),
    .ALUIn2(ALUIn2),
    .ALUInShamt(Shamt),
    .ALUCtrl(ALUCtrl),
    .Zero(Zero),
    .ALUOut(ALUOut)
  );











































  
endmodule