data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module MERGE_NETWORK #(parameter                       E_LOG = 2,
                       parameter                       FLOAT  = "no",
                       parameter                       SIGNED = "no",
                       parameter                       DATW  = 64,
                       parameter                       KEYW  = 32)
                      (input  wire                     CLK,
                       input  wire                     RST,
                       input  wire [(DATW<<E_LOG)-1:0] DIN_A,
                       input  wire                     SEL_A,
                       input  wire [(DATW<<E_LOG)-1:0] DIN_B,
                       input  wire                     SEL_B,
                       output wire [(DATW<<E_LOG)-1:0] DOT,
                       output wire                     DOTEN);

  localparam PAYW = DATW - KEYW;

  wire [(DATW<<E_LOG)-1:0] init_dummy_data;

  genvar i;
  generate
    for (i=0; i<(1<<E_LOG); i=i+1) begin: setdata
      if (FLOAT == "yes" || SIGNED == "yes") begin
        localparam [KEYW-1:0] MIN_KEY = {1'b1, {(KEYW-1){1'b0}}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end else begin
        localparam [KEYW-1:0] MIN_KEY = {(KEYW){1'b0}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end
    end
  endgenerate

  function [(DATW<<E_LOG)-1:0] mux;
    input [(DATW<<E_LOG)-1:0] in0;
    input [(DATW<<E_LOG)-1:0] in1;
    input                     sel;
    begin
      case (sel)
        1'b0: mux = in0;
        1'b1: mux = in1;
      endcase
    end
  endfunction



  reg [(DATW<<E_LOG)-1:0] din_a;
  reg [(DATW<<E_LOG)-1:0] din_b;
  always @(posedge CLK) begin
    din_a <= DIN_A;
    din_b <= DIN_B;
  end

  reg sel_a;
  reg sel_b;
  always @(posedge CLK) begin
    if (RST) begin
      sel_a <= 0;
      sel_b <= 0;
    end else begin
      sel_a <= SEL_A;
      sel_b <= SEL_B;
    end
  end

  reg dinen;
  always @(posedge CLK) begin
    dinen <= (RST) ? 0 : |{SEL_B,SEL_A};
  end



  wire [(DATW<<E_LOG)-1:0] c_2 = mux(din_b, din_a, sel_a);

  reg a_selected;
  always @(posedge CLK) begin
    if (dinen) a_selected <= sel_a;
  end

  wire update_r_1 = &{dinen,^{a_selected,sel_a}};

  reg [(DATW<<E_LOG)-1:0] r_1;
  reg [(DATW<<E_LOG)-1:0] r_2;
  always @(posedge CLK) begin
    if      (RST)   r_2 <= init_dummy_data;
    else if (dinen) r_2 <= c_2;
  end
  always @(posedge CLK) begin
    if      (RST)        r_1 <= init_dummy_data;
    else if (update_r_1) r_1 <= r_2;
  end

  wire [(DATW<<(E_LOG+1))-1:0] m_l_din = {r_2, r_1};
  wire [(DATW<<(E_LOG+1))-1:0] m_l_dot;
  BOEM #(E_LOG+1, FLOAT, SIGNED, DATW, KEYW)
  M_L(CLK, m_l_din, m_l_dot);


  integer p; reg [(DATW<<E_LOG)-1:0] sbuf [((E_LOG+1)<<1)-1:0];
  always @(posedge CLK) begin
    sbuf[0] <= c_2;
    for (p=1; p<((E_LOG+1)<<1); p=p+1) sbuf[p] <= sbuf[p-1];
  end

  wire [(DATW<<(E_LOG+1))-1:0] m_s_din = {sbuf[((E_LOG+1)<<1)-1], m_l_dot[(DATW<<(E_LOG+1))-1:(DATW<<E_LOG)]};
  wire [(DATW<<(E_LOG+1))-1:0] m_s_dot;
  BOEM #(E_LOG+1, FLOAT, SIGNED, DATW, KEYW)
  M_S(CLK, m_s_din, m_s_dot);

  reg init_record_ejected;
  always @(posedge CLK) begin
    if      (RST)   init_record_ejected <= 0;
    else if (dinen) init_record_ejected <= 1;
  end

  reg [(((E_LOG+1)<<1)<<1)-1:0] pc;
  always @(posedge CLK) begin
    if (RST) begin
      pc <= 0;
    end else begin
      pc[0] <= &{dinen, init_record_ejected};
      for (p=1; p<(((E_LOG+1)<<1)<<1); p=p+1) pc[p] <= pc[p-1];
    end
  end



  assign DOT   = m_s_dot[(DATW<<E_LOG)-1:0];
  assign DOTEN = pc[(((E_LOG+1)<<1)<<1)-1];

endmodule
module MERGE_NETWORK #(parameter                       E_LOG = 2,
                       parameter                       FLOAT  = "no",
                       parameter                       SIGNED = "no",
                       parameter                       DATW  = 64,
                       parameter                       KEYW  = 32)
                      (input  wire                     CLK,
                       input  wire                     RST,
                       input  wire [(DATW<<E_LOG)-1:0] DIN_A,
                       input  wire                     SEL_A,
                       input  wire [(DATW<<E_LOG)-1:0] DIN_B,
                       input  wire                     SEL_B,
                       output wire [(DATW<<E_LOG)-1:0] DOT,
                       output wire                     DOTEN);


  localparam PAYW = DATW - KEYW;

  wire [(DATW<<E_LOG)-1:0] init_dummy_data;

  genvar i;
  generate
    for (i=0; i<(1<<E_LOG); i=i+1) begin: setdata
      if (FLOAT == "yes" || SIGNED == "yes") begin
        localparam [KEYW-1:0] MIN_KEY = {1'b1, {(KEYW-1){1'b0}}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end else begin
        localparam [KEYW-1:0] MIN_KEY = {(KEYW){1'b0}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end
    end
  endgenerate

  function [(DATW<<E_LOG)-1:0] mux;
    input [(DATW<<E_LOG)-1:0] in0;
    input [(DATW<<E_LOG)-1:0] in1;
    input                     sel;
    begin
      case (sel)
        1'b0: mux = in0;
        1'b1: mux = in1;
      endcase
    end
  endfunction



  reg [(DATW<<E_LOG)-1:0] din_a;
  reg [(DATW<<E_LOG)-1:0] din_b;
  always @(posedge CLK) begin
    din_a <= DIN_A;
    din_b <= DIN_B;
  end

  reg sel_a;
  reg sel_b;
  always @(posedge CLK) begin
    if (RST) begin
      sel_a <= 0;
      sel_b <= 0;
    end else begin
      sel_a <= SEL_A;
      sel_b <= SEL_B;
    end
  end

  reg dinen;
  always @(posedge CLK) begin
    dinen <= (RST) ? 0 : |{SEL_B,SEL_A};
  end



  wire [(DATW<<E_LOG)-1:0] c_2 = mux(din_b, din_a, sel_a);

  reg a_selected;
  always @(posedge CLK) begin
    if (dinen) a_selected <= sel_a;
  end

  wire update_r_1 = &{dinen,^{a_selected,sel_a}};

  reg [(DATW<<E_LOG)-1:0] r_1;
  reg [(DATW<<E_LOG)-1:0] r_2;
  always @(posedge CLK) begin
    if      (RST)   r_2 <= init_dummy_data;
    else if (dinen) r_2 <= c_2;
  end
  always @(posedge CLK) begin
    if      (RST)        r_1 <= init_dummy_data;
    else if (update_r_1) r_1 <= r_2;
  end

  wire [(DATW<<(E_LOG+1))-1:0] m_l_din = {r_2, r_1};
  wire [(DATW<<(E_LOG+1))-1:0] m_l_dot;
  BOEM #(E_LOG+1, FLOAT, SIGNED, DATW, KEYW)
  M_L(CLK, m_l_din, m_l_dot);


  integer p; reg [(DATW<<E_LOG)-1:0] sbuf [((E_LOG+1)<<1)-1:0];
  always @(posedge CLK) begin
    sbuf[0] <= c_2;
    for (p=1; p<((E_LOG+1)<<1); p=p+1) sbuf[p] <= sbuf[p-1];
  end

  wire [(DATW<<(E_LOG+1))-1:0] m_s_din = {sbuf[((E_LOG+1)<<1)-1], m_l_dot[(DATW<<(E_LOG+1))-1:(DATW<<E_LOG)]};
  wire [(DATW<<(E_LOG+1))-1:0] m_s_dot;
  BOEM #(E_LOG+1, FLOAT, SIGNED, DATW, KEYW)
  M_S(CLK, m_s_din, m_s_dot);

  reg init_record_ejected;
  always @(posedge CLK) begin
    if      (RST)   init_record_ejected <= 0;
    else if (dinen) init_record_ejected <= 1;
  end

  reg [(((E_LOG+1)<<1)<<1)-1:0] pc;
  always @(posedge CLK) begin
    if (RST) begin
      pc <= 0;
    end else begin
      pc[0] <= &{dinen, init_record_ejected};
      for (p=1; p<(((E_LOG+1)<<1)<<1); p=p+1) pc[p] <= pc[p-1];
    end
  end



  assign DOT   = m_s_dot[(DATW<<E_LOG)-1:0];
  assign DOTEN = pc[(((E_LOG+1)<<1)<<1)-1];

endmodule