data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:69: Signal definition not found, creating implicitly: \'enable_q\'\nassign clk_sel = (enable_q | ~testmode_l) ? clk : to_core;\n                  ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:78: Signal definition not found, creating implicitly: \'drive_dqs_q\'\nassign to_pad = clk & drive_dqs_q & ~ch_disabled;\n                      ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:78: Signal definition not found, creating implicitly: \'ch_disabled\'\nassign to_pad = clk & drive_dqs_q & ~ch_disabled;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:59: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_enable(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.sv\n             dff_s\n             dff_s.v\n             dff_s.sv\n             obj_dir/dff_s\n             obj_dir/dff_s.v\n             obj_dir/dff_s.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:64: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_ch_enable(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dqs_edgelogic.v:73: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_drive_dqs(\n^~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module dram_dqs_edgelogic(

   clk_sel, dqs_pad_clk_so, to_pad, oe, 

   clk, dqs_pad_clk_se, dqs_pad_clk_si, 
   dram_io_drive_enable, dram_io_drive_data, 
   dram_io_channel_disabled, to_core, testmode_l
   );




input			clk;
input			testmode_l;
input			dqs_pad_clk_se;
input			dqs_pad_clk_si;
input			dram_io_drive_enable;
input			dram_io_drive_data;
input			dram_io_channel_disabled;
input			to_core;




output			clk_sel;
output			dqs_pad_clk_so;
output			to_pad;
output			oe;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)	flop_enable(
		.din(dram_io_drive_enable),
		.q(enable_q),
		.clk(clk), .si(dqs_pad_clk_si), .so(dqs_pad_clk_si1), .se(dqs_pad_clk_se));

dff_s #(1)	flop_ch_enable(
		.din(dram_io_channel_disabled),
		.q(ch_disabled),
		.clk(clk), .si(dqs_pad_clk_si1), .so(dqs_pad_clk_si2), .se(dqs_pad_clk_se));

assign clk_sel = (enable_q | ~testmode_l) ? clk : to_core;

assign oe = enable_q;

dff_s #(1)	flop_drive_dqs(
		.din(dram_io_drive_data),
		.q(drive_dqs_q),
		.clk(tclk), .si(dqs_pad_clk_si2), .so(dqs_pad_clk_so), .se(dqs_pad_clk_se));

assign to_pad = clk & drive_dqs_q & ~ch_disabled;

endmodule
module dram_dqs_edgelogic(

   clk_sel, dqs_pad_clk_so, to_pad, oe, 

   clk, dqs_pad_clk_se, dqs_pad_clk_si, 
   dram_io_drive_enable, dram_io_drive_data, 
   dram_io_channel_disabled, to_core, testmode_l
   );





input			clk;
input			testmode_l;
input			dqs_pad_clk_se;
input			dqs_pad_clk_si;
input			dram_io_drive_enable;
input			dram_io_drive_data;
input			dram_io_channel_disabled;
input			to_core;




output			clk_sel;
output			dqs_pad_clk_so;
output			to_pad;
output			oe;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)	flop_enable(
		.din(dram_io_drive_enable),
		.q(enable_q),
		.clk(clk), .si(dqs_pad_clk_si), .so(dqs_pad_clk_si1), .se(dqs_pad_clk_se));

dff_s #(1)	flop_ch_enable(
		.din(dram_io_channel_disabled),
		.q(ch_disabled),
		.clk(clk), .si(dqs_pad_clk_si1), .so(dqs_pad_clk_si2), .se(dqs_pad_clk_se));

assign clk_sel = (enable_q | ~testmode_l) ? clk : to_core;

assign oe = enable_q;

dff_s #(1)	flop_drive_dqs(
		.din(dram_io_drive_data),
		.q(drive_dqs_q),
		.clk(tclk), .si(dqs_pad_clk_si2), .so(dqs_pad_clk_so), .se(dqs_pad_clk_se));

assign to_pad = clk & drive_dqs_q & ~ch_disabled;

endmodule