data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_Mul_33Ux32U_64U_4.v
data/verilator_xmls/37a02cb2-cef9-48f7-9ae2-b4547290b365.xml
module dut_Mul_33Ux32U_64U_4 (
	in2,
	in1,
	out1
	);
input [32:0] in2;
input [31:0] in1;
output [63:0] out1;
wire [63:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule
module dut_Mul_33Ux32U_64U_4 (
	in2,
	in1,
	out1
	);

input [32:0] in2;
input [31:0] in1;
output [63:0] out1;
wire [63:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule