data/full_repos/permissive/521337848/Hardware/GRAPHICS/UI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/UI.v:21: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n                                                                              : ... In instance uiController\n  memory[n] = 0;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/UI.v:31: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 2 bits.\n                                                                              : ... In instance uiController\n tex <= memory[{CounterX[9:4],CounterY[8:4]}];\n     ^~\n%Error: Exiting due to 2 warning(s)\n'
module uiController(
	input clk,
	
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	input we,
	input[10:0] addr,
	input[1:0] din,
	
	output reg[4:0] tex
);


reg[1:0] memory[2047:0];

reg[11:0] n;

initial begin
	for(n=0;n<2048;n = n + 1) begin
		memory[n] = 0;
		end
end


always@(posedge clk)begin
	
	if(we)
		memory[addr] <= din;
		
	tex <= memory[{CounterX[9:4],CounterY[8:4]}];
	end

endmodule
module uiController(
	input clk,
	
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	input we,
	input[10:0] addr,
	input[1:0] din,
	
	output reg[4:0] tex
);



reg[1:0] memory[2047:0];

reg[11:0] n;

initial begin
	for(n=0;n<2048;n = n + 1) begin
		memory[n] = 0;
		end
end


always@(posedge clk)begin
	
	if(we)
		memory[addr] <= din;
		
	tex <= memory[{CounterX[9:4],CounterY[8:4]}];
	end

endmodule