data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v
1: b'%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:13: syntax error, unexpected IDENTIFIER, expecting \',\' or \';\'\n pulse_FSM FSM0 (\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/pulse_FSM_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module pulse_FSM_tb;
	localparam TRIG_H_period=50;
	localparam ADC_H_period=2;

	wire P;
	reg ADC_CLK = 1'b0;
	reg TRIG_CLK = 1'b0;
	reg PULSE_RST = 1'b0;
	reg PULSE_COUNT = 32'h0000_0000;
	reg PULSE_COUNT_NEXT = 32'h0000_0000;
	wire DONE

	pulse_FSM FSM0 (
		.s(TRIG_CLK),
		.clk(ADC_CLK),
		.rst(PULSE_RST),
		.P(P),
		.L(),
		.A(),
		.B()
	);

	pulse_counter #(
		.DATA_WIDTH(32)
	) PULSE_COUNT0 (
		.clk(ADC_CLK),
		.en(!P),
		wait_val(PULSE_COUNTER),
		.f(DONE)
	);

	always
	begin
		ADC_CLK = 1'b0;
		#ADC_H_period;
		ADC_CLK = 1'b1;
		#ADC_H_period;
	end

	always
	begin
		TRIG_CLK = 1'b0;
		#TRIG_H_period;
		TRIG_CLK = 1'b1;
		#TRIG_H_period;
	end

	initial
	begin
		PULSE_RST = 1'b0;
		#ADC_H_period;
		PULSE_RST = 1'b1;
	end
endmodule
module pulse_FSM_tb;

	localparam TRIG_H_period=50;
	localparam ADC_H_period=2;

	wire P;
	reg ADC_CLK = 1'b0;
	reg TRIG_CLK = 1'b0;
	reg PULSE_RST = 1'b0;
	reg PULSE_COUNT = 32'h0000_0000;
	reg PULSE_COUNT_NEXT = 32'h0000_0000;
	wire DONE

	pulse_FSM FSM0 (
		.s(TRIG_CLK),
		.clk(ADC_CLK),
		.rst(PULSE_RST),
		.P(P),
		.L(),
		.A(),
		.B()
	);

	pulse_counter #(
		.DATA_WIDTH(32)
	) PULSE_COUNT0 (
		.clk(ADC_CLK),
		.en(!P),
		wait_val(PULSE_COUNTER),
		.f(DONE)
	);

	always
	begin
		ADC_CLK = 1'b0;
		#ADC_H_period;
		ADC_CLK = 1'b1;
		#ADC_H_period;
	end

	always
	begin
		TRIG_CLK = 1'b0;
		#TRIG_H_period;
		TRIG_CLK = 1'b1;
		#TRIG_H_period;
	end

	initial
	begin
		PULSE_RST = 1'b0;
		#ADC_H_period;
		PULSE_RST = 1'b1;
	end
endmodule