data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:97: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\n      state <= `BLOCK_DECODE_IDLE;\n               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      state <= `BLOCK_DECODE_IDLE;\n                                 ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:107: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\n         `BLOCK_DECODE_IDLE : begin\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:107: syntax error, unexpected \':\', expecting endcase\n         `BLOCK_DECODE_IDLE : begin\n                            ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:112: Define or directive not defined: \'`BLOCK_DECODE_DC_SIZE\'\n                        state <= `BLOCK_DECODE_DC_SIZE;\n                                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                        state <= `BLOCK_DECODE_DC_SIZE;\n                                                      ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:113: Define or directive not defined: \'`BLOCK_DECODE_FIRST_COEFF_0\'\n                     end else state <= `BLOCK_DECODE_FIRST_COEFF_0;\n                                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:115: Define or directive not defined: \'`BLOCK_DECODE_EMPTY_BLOCK\'\n                   state <= `BLOCK_DECODE_EMPTY_BLOCK;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:121: Define or directive not defined: \'`BLOCK_DECODE_EMPTY_BLOCK\'\n         `BLOCK_DECODE_EMPTY_BLOCK : begin   \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:123: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\n           state <= `BLOCK_DECODE_IDLE;\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:125: Define or directive not defined: \'`BLOCK_DECODE_DC_SIZE\'\n         `BLOCK_DECODE_DC_SIZE : begin\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:129: syntax error, unexpected <=, expecting IDENTIFIER\n                     Escape_Symbol <= {6\'h00,DC_predict_I};\n                                   ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:131: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n                     state <= `BLOCK_DECODE_SUBSEQ_COEFFS;\n                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:133: syntax error, unexpected <=, expecting IDENTIFIER\n                     Escape_Symbol <= {DC_Symbol,14\'h0000};\n                                   ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:135: Define or directive not defined: \'`BLOCK_DECODE_DC_DIFF\'\n                     state <= `BLOCK_DECODE_DC_DIFF;\n                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:138: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:139: Define or directive not defined: \'`BLOCK_DECODE_DC_DIFF\'\n         `BLOCK_DECODE_DC_DIFF : begin\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:142: syntax error, unexpected <=, expecting IDENTIFIER\n                  Escape_Symbol <= {6\'h00,New_DC_predict_O};\n                                ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:144: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;\n                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:146: syntax error, unexpected <=, expecting IDENTIFIER\n                  bit_counter <= bit_counter - 1;\n                              ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:147: syntax error, unexpected <=, expecting IDENTIFIER\n                  if (bit_counter[3:0] == Escape_Symbol[17:14]) DC_half_range_bit <= Data_In_I;\n                                                                                  ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:150: Define or directive not defined: \'`BLOCK_DECODE_FIRST_COEFF_0\'\n         `BLOCK_DECODE_FIRST_COEFF_0 : begin\n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:151: Define or directive not defined: \'`BLOCK_DECODE_FIRST_COEFF_1\'\n           if (Data_In_I) state <= `BLOCK_DECODE_FIRST_COEFF_1;\n                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:152: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n           else state <= `BLOCK_DECODE_SUBSEQ_COEFFS;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:154: Define or directive not defined: \'`BLOCK_DECODE_FIRST_COEFF_1\'\n         `BLOCK_DECODE_FIRST_COEFF_1 : begin\n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:158: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n               state <= `BLOCK_DECODE_SUBSEQ_COEFFS;\n                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:160: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n         `BLOCK_DECODE_SUBSEQ_COEFFS : begin\n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:164: Define or directive not defined: \'`DCT_ESCAPE\'\n                  if (Subseq_Symbol != `DCT_ESCAPE) begin\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:164: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  if (Subseq_Symbol != `DCT_ESCAPE) begin\n                                                  ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:165: Define or directive not defined: \'`DCT_END_OF_BLOCK\'\n                     Escape_Symbol <= (Subseq_Symbol == `DCT_END_OF_BLOCK) ? 18\'h00000 : \n                                                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:167: syntax error, unexpected <=, expecting IDENTIFIER\n                     if (Subseq_state_delay) Write_En_reg <= 1\'b1;\n                                                          ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:170: Define or directive not defined: \'`DCT_END_OF_BLOCK\'\n                  if ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)) begin\n                                                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:170: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  if ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)) begin\n                                                                                ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:172: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\n                     state <= `BLOCK_DECODE_IDLE;\n                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:173: Define or directive not defined: \'`DCT_ESCAPE\'\n                  end else if (Subseq_Symbol == `DCT_ESCAPE) begin\n                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:175: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_ESCAPE\'\n                     state <= `BLOCK_DECODE_SUBSEQ_ESCAPE;\n                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:179: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_ESCAPE\'\n         `BLOCK_DECODE_SUBSEQ_ESCAPE : begin           \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:182: syntax error, unexpected <=, expecting IDENTIFIER\n                  Write_En_reg <= 1\'b1;\n                               ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:183: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;\n                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:184: syntax error, unexpected <=, expecting IDENTIFIER\n               end else bit_counter <= bit_counter - 1;\n                                    ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:191: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\n (state == `BLOCK_DECODE_IDLE) ? \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:192: Define or directive not defined: \'`INFO_BLOCK_CODE_EOB\'\n  `INFO_BLOCK_CODE_EOB : `INFO_BLOCK_CODE,\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:192: Define or directive not defined: \'`INFO_BLOCK_CODE\'\n  `INFO_BLOCK_CODE_EOB : `INFO_BLOCK_CODE,\n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:196: Define or directive not defined: \'`BLOCK_DECODE_IDLE\'\nassign Done_Block_Decode_O = (state == `BLOCK_DECODE_IDLE);\n                                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:196: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign Done_Block_Decode_O = (state == `BLOCK_DECODE_IDLE);\n                                                         ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:199: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_ESCAPE\'\n   (((state == `BLOCK_DECODE_SUBSEQ_ESCAPE) & (bit_counter == 5\'h00)) | \n               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:199: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   (((state == `BLOCK_DECODE_SUBSEQ_ESCAPE) & (bit_counter == 5\'h00)) | \n                                          ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:200: Define or directive not defined: \'`BLOCK_DECODE_SUBSEQ_COEFFS\'\n   ((state == `BLOCK_DECODE_SUBSEQ_COEFFS) & \n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Slice_Decode/Block_Decode.v:201: Define or directive not defined: \'`DCT_ESCAPE\'\n      ~((Subseq_Symbol == `DCT_ESCAPE) | ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)))));\n                          ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Block_Decode(
   resetn,
   clock,

   Start_Block_Decode_I,
   Done_Block_Decode_O,

   Data_In_I,
   Shift_En_O,

   Pattern_Code_I,
   Macroblock_Intra_I,
   Luma_Chroma_Sel_I,
   Intra_VLC_Format_I,   
   
   DC_predict_I,
   New_DC_predict_O,
   Update_DC_predict_O,
   
   Buffer_Value_O,
   Buffer_Write_En_O,

   DC_Coeff_En_O,
   DC_Coeff_Data_I,
   DC_Coeff_Addr_O,
   
   AC_Coeff_En_O,
   AC_Coeff_Data_I,
   AC_Coeff_Addr_O
);

input                resetn;
input                clock;

input                Start_Block_Decode_I;
output               Done_Block_Decode_O;

input                Data_In_I;
output               Shift_En_O;

input                Pattern_Code_I;
input                Macroblock_Intra_I;
input                Luma_Chroma_Sel_I;
input                Intra_VLC_Format_I;

input    [11:0]      DC_predict_I;
output   [11:0]      New_DC_predict_O;
output               Update_DC_predict_O;

output   [31:0]      Buffer_Value_O;
output               Buffer_Write_En_O;

output               DC_Coeff_En_O, AC_Coeff_En_O;  
input    [15:0]      DC_Coeff_Data_I, AC_Coeff_Data_I;
output   [9:0]       DC_Coeff_Addr_O, AC_Coeff_Addr_O;

reg      [2:0]       state;
reg      [17:0]      Escape_Symbol;
reg      [4:0]       bit_counter;
reg                  Subseq_state_delay;
reg                  Write_En_reg;

wire                 Subseq_Start;
wire                 Subseq_Done;
wire                 Subseq_Shift_En;
wire     [15:0]      Subseq_Symbol;
wire     [8:0]       Subseq_Symbol_signed;

reg                  DC_Start;
wire                 DC_Shift_En;
wire                 DC_Done;
wire     [3:0]       DC_Symbol;
reg                  DC_half_range_bit;
wire     [12:0]      DC_prediction_partial;
wire     [12:0]      DC_predict_adjust;
wire     [12:0]      DC_predict_full;

always @(posedge clock or negedge resetn) begin
   if (~resetn) begin
      state <= `BLOCK_DECODE_IDLE;
      bit_counter <= 5'h00;
      Escape_Symbol <= 18'h00000;
      Subseq_state_delay <= 1'b0;
      Write_En_reg <= 1'b0;
      DC_Start <= 1'b0;
      DC_half_range_bit <= 1'b0;
   end else begin
      Write_En_reg <= 1'b0;
      case (state)
         `BLOCK_DECODE_IDLE : begin
               if (Start_Block_Decode_I) begin
                  if (Pattern_Code_I) begin
                     if (Macroblock_Intra_I) begin
                        DC_Start <= 1'b1;
                        state <= `BLOCK_DECODE_DC_SIZE;
                     end else state <= `BLOCK_DECODE_FIRST_COEFF_0;
                  end else begin
                  	state <= `BLOCK_DECODE_EMPTY_BLOCK;
                  	Escape_Symbol <= 18'h00000;
                  	Write_En_reg <= 1'b1;
                  end
               end
            end
         `BLOCK_DECODE_EMPTY_BLOCK : begin   
         		Write_En_reg <= 1'b1;
         		state <= `BLOCK_DECODE_IDLE;
         	end
         `BLOCK_DECODE_DC_SIZE : begin
               DC_Start <= 1'b0;
               if (DC_Done & ~DC_Start) begin
                  if (DC_Symbol == 4'h0) begin
                     Escape_Symbol <= {6'h00,DC_predict_I};
                     Write_En_reg <= 1'b1;
                     state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
                  end else begin
                     Escape_Symbol <= {DC_Symbol,14'h0000};
                     bit_counter <= {1'b0,DC_Symbol};
                     state <= `BLOCK_DECODE_DC_DIFF;
                  end
               end
            end
         `BLOCK_DECODE_DC_DIFF : begin
               Escape_Symbol <= {Escape_Symbol[17:14],Escape_Symbol[12:0],Data_In_I};
               if (bit_counter == 5'h00) begin
                  Escape_Symbol <= {6'h00,New_DC_predict_O};
                  Write_En_reg <= 1'b1;
                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
               end else begin
                  bit_counter <= bit_counter - 1;
                  if (bit_counter[3:0] == Escape_Symbol[17:14]) DC_half_range_bit <= Data_In_I;
               end
            end
         `BLOCK_DECODE_FIRST_COEFF_0 : begin
         		if (Data_In_I) state <= `BLOCK_DECODE_FIRST_COEFF_1;
         		else state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
            end
         `BLOCK_DECODE_FIRST_COEFF_1 : begin
               Escape_Symbol <= (Data_In_I) ?
               	{6'h00,12'hFFF} : {6'h00,12'h001};
               Write_En_reg <= 1'b1;
               state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
            end
         `BLOCK_DECODE_SUBSEQ_COEFFS : begin
               Subseq_state_delay <= 1'b1;
               if (Subseq_Done) begin

                  if (Subseq_Symbol != `DCT_ESCAPE) begin
                     Escape_Symbol <= (Subseq_Symbol == `DCT_END_OF_BLOCK) ? 18'h00000 : 
                        {Subseq_Symbol[13:8],{3{Subseq_Symbol_signed[8]}}, Subseq_Symbol_signed[8:0]};
                     if (Subseq_state_delay) Write_En_reg <= 1'b1;
                  end

                  if ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)) begin
                     Subseq_state_delay <= 1'b0;
                     state <= `BLOCK_DECODE_IDLE;
                  end else if (Subseq_Symbol == `DCT_ESCAPE) begin
                     bit_counter <= 5'd17;
                     state <= `BLOCK_DECODE_SUBSEQ_ESCAPE;
                  end
               end
            end
         `BLOCK_DECODE_SUBSEQ_ESCAPE : begin           
               Escape_Symbol <= {Escape_Symbol[16:0],Data_In_I};
               if (bit_counter == 5'h00) begin
                  Write_En_reg <= 1'b1;
                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
               end else bit_counter <= bit_counter - 1;
            end
      endcase
   end
end

assign Buffer_Value_O = {
	(state == `BLOCK_DECODE_IDLE) ? 
		`INFO_BLOCK_CODE_EOB : `INFO_BLOCK_CODE,
	Escape_Symbol };
assign Buffer_Write_En_O = Write_En_reg;

assign Done_Block_Decode_O = (state == `BLOCK_DECODE_IDLE);

assign Subseq_Start = Subseq_Done & 
   (((state == `BLOCK_DECODE_SUBSEQ_ESCAPE) & (bit_counter == 5'h00)) | 
   ((state == `BLOCK_DECODE_SUBSEQ_COEFFS) & 
      ~((Subseq_Symbol == `DCT_ESCAPE) | ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)))));

assign Shift_En_O = DC_Shift_En | ((state == `BLOCK_DECODE_DC_DIFF) & (bit_counter != 5'h00)) |
   Subseq_Shift_En | (state == `BLOCK_DECODE_SUBSEQ_ESCAPE) |
      (Subseq_state_delay & ~(
         (state == `BLOCK_DECODE_SUBSEQ_COEFFS) &  
            ((Subseq_Symbol == `DCT_ESCAPE) | (Subseq_Symbol == `DCT_END_OF_BLOCK)))) | 
   ((state == `BLOCK_DECODE_FIRST_COEFF_0) & Data_In_I) | 
   (state == `BLOCK_DECODE_FIRST_COEFF_1);

assign Subseq_Symbol_signed = (Data_In_I) ? -Subseq_Symbol[7:0] : Subseq_Symbol[7:0];

assign DC_prediction_partial = DC_predict_I + Escape_Symbol[11:0];
assign DC_predict_adjust = (~DC_half_range_bit) ? 
   ((1 << Escape_Symbol[17:14]) - 1) : 13'h0000;
assign DC_predict_full = DC_prediction_partial - DC_predict_adjust;
assign New_DC_predict_O = DC_predict_full[11:0];

assign Update_DC_predict_O = ((state == `BLOCK_DECODE_DC_DIFF) & (bit_counter == 1'b0));

Block_Decode_DC_Coeff DC_Coeff_Decoder(
   .resetn(resetn),
   .clock(clock),
   .Start_I(DC_Start),
   .Luma_Chroma_Sel_I(Luma_Chroma_Sel_I),
   .Data_In_I(Data_In_I),
   .Shift_En_O(DC_Shift_En),
   .Valid_Code_O(DC_Done),
   .Symbol_O(DC_Symbol),
   .Coeff_Table_En_O(DC_Coeff_En_O),
   .Coeff_Table_Addr_O(DC_Coeff_Addr_O),
   .Coeff_Table_Data_I(DC_Coeff_Data_I)
);

wire                 Table_Sel;
assign Table_Sel = Macroblock_Intra_I & Intra_VLC_Format_I;

Block_Decode_Coeffs Coeff_Decoder(
   .resetn(resetn),
   .clock(clock),
   .Start_I(Subseq_Start),
   .Table_Sel_I(Table_Sel),
   .Data_In_I(Data_In_I),
   .Shift_En_O(Subseq_Shift_En),
   .Valid_Code_O(Subseq_Done),
   .Symbol_O(Subseq_Symbol),
   .Coeff_Table_En_O(AC_Coeff_En_O),
   .Coeff_Table_Addr_O(AC_Coeff_Addr_O),
   .Coeff_Table_Data_I(AC_Coeff_Data_I)
);

endmodule
module Block_Decode(
   resetn,
   clock,

   Start_Block_Decode_I,
   Done_Block_Decode_O,

   Data_In_I,
   Shift_En_O,

   Pattern_Code_I,
   Macroblock_Intra_I,
   Luma_Chroma_Sel_I,
   Intra_VLC_Format_I,   
   
   DC_predict_I,
   New_DC_predict_O,
   Update_DC_predict_O,
   
   Buffer_Value_O,
   Buffer_Write_En_O,

   DC_Coeff_En_O,
   DC_Coeff_Data_I,
   DC_Coeff_Addr_O,
   
   AC_Coeff_En_O,
   AC_Coeff_Data_I,
   AC_Coeff_Addr_O
);


input                resetn;
input                clock;

input                Start_Block_Decode_I;
output               Done_Block_Decode_O;

input                Data_In_I;
output               Shift_En_O;

input                Pattern_Code_I;
input                Macroblock_Intra_I;
input                Luma_Chroma_Sel_I;
input                Intra_VLC_Format_I;

input    [11:0]      DC_predict_I;
output   [11:0]      New_DC_predict_O;
output               Update_DC_predict_O;

output   [31:0]      Buffer_Value_O;
output               Buffer_Write_En_O;

output               DC_Coeff_En_O, AC_Coeff_En_O;  
input    [15:0]      DC_Coeff_Data_I, AC_Coeff_Data_I;
output   [9:0]       DC_Coeff_Addr_O, AC_Coeff_Addr_O;

reg      [2:0]       state;
reg      [17:0]      Escape_Symbol;
reg      [4:0]       bit_counter;
reg                  Subseq_state_delay;
reg                  Write_En_reg;

wire                 Subseq_Start;
wire                 Subseq_Done;
wire                 Subseq_Shift_En;
wire     [15:0]      Subseq_Symbol;
wire     [8:0]       Subseq_Symbol_signed;

reg                  DC_Start;
wire                 DC_Shift_En;
wire                 DC_Done;
wire     [3:0]       DC_Symbol;
reg                  DC_half_range_bit;
wire     [12:0]      DC_prediction_partial;
wire     [12:0]      DC_predict_adjust;
wire     [12:0]      DC_predict_full;

always @(posedge clock or negedge resetn) begin
   if (~resetn) begin
      state <= `BLOCK_DECODE_IDLE;
      bit_counter <= 5'h00;
      Escape_Symbol <= 18'h00000;
      Subseq_state_delay <= 1'b0;
      Write_En_reg <= 1'b0;
      DC_Start <= 1'b0;
      DC_half_range_bit <= 1'b0;
   end else begin
      Write_En_reg <= 1'b0;
      case (state)
         `BLOCK_DECODE_IDLE : begin
               if (Start_Block_Decode_I) begin
                  if (Pattern_Code_I) begin
                     if (Macroblock_Intra_I) begin
                        DC_Start <= 1'b1;
                        state <= `BLOCK_DECODE_DC_SIZE;
                     end else state <= `BLOCK_DECODE_FIRST_COEFF_0;
                  end else begin
                  	state <= `BLOCK_DECODE_EMPTY_BLOCK;
                  	Escape_Symbol <= 18'h00000;
                  	Write_En_reg <= 1'b1;
                  end
               end
            end
         `BLOCK_DECODE_EMPTY_BLOCK : begin   
         		Write_En_reg <= 1'b1;
         		state <= `BLOCK_DECODE_IDLE;
         	end
         `BLOCK_DECODE_DC_SIZE : begin
               DC_Start <= 1'b0;
               if (DC_Done & ~DC_Start) begin
                  if (DC_Symbol == 4'h0) begin
                     Escape_Symbol <= {6'h00,DC_predict_I};
                     Write_En_reg <= 1'b1;
                     state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
                  end else begin
                     Escape_Symbol <= {DC_Symbol,14'h0000};
                     bit_counter <= {1'b0,DC_Symbol};
                     state <= `BLOCK_DECODE_DC_DIFF;
                  end
               end
            end
         `BLOCK_DECODE_DC_DIFF : begin
               Escape_Symbol <= {Escape_Symbol[17:14],Escape_Symbol[12:0],Data_In_I};
               if (bit_counter == 5'h00) begin
                  Escape_Symbol <= {6'h00,New_DC_predict_O};
                  Write_En_reg <= 1'b1;
                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
               end else begin
                  bit_counter <= bit_counter - 1;
                  if (bit_counter[3:0] == Escape_Symbol[17:14]) DC_half_range_bit <= Data_In_I;
               end
            end
         `BLOCK_DECODE_FIRST_COEFF_0 : begin
         		if (Data_In_I) state <= `BLOCK_DECODE_FIRST_COEFF_1;
         		else state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
            end
         `BLOCK_DECODE_FIRST_COEFF_1 : begin
               Escape_Symbol <= (Data_In_I) ?
               	{6'h00,12'hFFF} : {6'h00,12'h001};
               Write_En_reg <= 1'b1;
               state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
            end
         `BLOCK_DECODE_SUBSEQ_COEFFS : begin
               Subseq_state_delay <= 1'b1;
               if (Subseq_Done) begin

                  if (Subseq_Symbol != `DCT_ESCAPE) begin
                     Escape_Symbol <= (Subseq_Symbol == `DCT_END_OF_BLOCK) ? 18'h00000 : 
                        {Subseq_Symbol[13:8],{3{Subseq_Symbol_signed[8]}}, Subseq_Symbol_signed[8:0]};
                     if (Subseq_state_delay) Write_En_reg <= 1'b1;
                  end

                  if ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)) begin
                     Subseq_state_delay <= 1'b0;
                     state <= `BLOCK_DECODE_IDLE;
                  end else if (Subseq_Symbol == `DCT_ESCAPE) begin
                     bit_counter <= 5'd17;
                     state <= `BLOCK_DECODE_SUBSEQ_ESCAPE;
                  end
               end
            end
         `BLOCK_DECODE_SUBSEQ_ESCAPE : begin           
               Escape_Symbol <= {Escape_Symbol[16:0],Data_In_I};
               if (bit_counter == 5'h00) begin
                  Write_En_reg <= 1'b1;
                  state <= `BLOCK_DECODE_SUBSEQ_COEFFS;
               end else bit_counter <= bit_counter - 1;
            end
      endcase
   end
end

assign Buffer_Value_O = {
	(state == `BLOCK_DECODE_IDLE) ? 
		`INFO_BLOCK_CODE_EOB : `INFO_BLOCK_CODE,
	Escape_Symbol };
assign Buffer_Write_En_O = Write_En_reg;

assign Done_Block_Decode_O = (state == `BLOCK_DECODE_IDLE);

assign Subseq_Start = Subseq_Done & 
   (((state == `BLOCK_DECODE_SUBSEQ_ESCAPE) & (bit_counter == 5'h00)) | 
   ((state == `BLOCK_DECODE_SUBSEQ_COEFFS) & 
      ~((Subseq_Symbol == `DCT_ESCAPE) | ((Subseq_state_delay) & (Subseq_Symbol == `DCT_END_OF_BLOCK)))));

assign Shift_En_O = DC_Shift_En | ((state == `BLOCK_DECODE_DC_DIFF) & (bit_counter != 5'h00)) |
   Subseq_Shift_En | (state == `BLOCK_DECODE_SUBSEQ_ESCAPE) |
      (Subseq_state_delay & ~(
         (state == `BLOCK_DECODE_SUBSEQ_COEFFS) &  
            ((Subseq_Symbol == `DCT_ESCAPE) | (Subseq_Symbol == `DCT_END_OF_BLOCK)))) | 
   ((state == `BLOCK_DECODE_FIRST_COEFF_0) & Data_In_I) | 
   (state == `BLOCK_DECODE_FIRST_COEFF_1);

assign Subseq_Symbol_signed = (Data_In_I) ? -Subseq_Symbol[7:0] : Subseq_Symbol[7:0];

assign DC_prediction_partial = DC_predict_I + Escape_Symbol[11:0];
assign DC_predict_adjust = (~DC_half_range_bit) ? 
   ((1 << Escape_Symbol[17:14]) - 1) : 13'h0000;
assign DC_predict_full = DC_prediction_partial - DC_predict_adjust;
assign New_DC_predict_O = DC_predict_full[11:0];

assign Update_DC_predict_O = ((state == `BLOCK_DECODE_DC_DIFF) & (bit_counter == 1'b0));

Block_Decode_DC_Coeff DC_Coeff_Decoder(
   .resetn(resetn),
   .clock(clock),
   .Start_I(DC_Start),
   .Luma_Chroma_Sel_I(Luma_Chroma_Sel_I),
   .Data_In_I(Data_In_I),
   .Shift_En_O(DC_Shift_En),
   .Valid_Code_O(DC_Done),
   .Symbol_O(DC_Symbol),
   .Coeff_Table_En_O(DC_Coeff_En_O),
   .Coeff_Table_Addr_O(DC_Coeff_Addr_O),
   .Coeff_Table_Data_I(DC_Coeff_Data_I)
);

wire                 Table_Sel;
assign Table_Sel = Macroblock_Intra_I & Intra_VLC_Format_I;

Block_Decode_Coeffs Coeff_Decoder(
   .resetn(resetn),
   .clock(clock),
   .Start_I(Subseq_Start),
   .Table_Sel_I(Table_Sel),
   .Data_In_I(Data_In_I),
   .Shift_En_O(Subseq_Shift_En),
   .Valid_Code_O(Subseq_Done),
   .Symbol_O(Subseq_Symbol),
   .Coeff_Table_En_O(AC_Coeff_En_O),
   .Coeff_Table_Addr_O(AC_Coeff_Addr_O),
   .Coeff_Table_Data_I(AC_Coeff_Data_I)
);

endmodule