data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:487: Bit extraction of var[79:0] requires 7 bit index, not 1 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T43 = io_chanxy_config[2\'h3 :1\'h0 ];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:489: Bit extraction of var[195:0] requires 8 bit index, not 1 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T45 = io_chanxy_in[4\'h9 :1\'h0 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:495: Bit extraction of var[79:0] requires 7 bit index, not 3 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T51 = io_chanxy_config[3\'h7 :3\'h4 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:497: Bit extraction of var[195:0] requires 8 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T53 = io_chanxy_in[5\'h13 :4\'ha ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:503: Bit extraction of var[79:0] requires 7 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T59 = io_chanxy_config[4\'hb :4\'h8 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:505: Bit extraction of var[195:0] requires 8 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T61 = io_chanxy_in[5\'h1d :5\'h14 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:511: Bit extraction of var[79:0] requires 7 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T67 = io_chanxy_config[4\'hf :4\'hc ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:513: Bit extraction of var[195:0] requires 8 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T69 = io_chanxy_in[6\'h27 :5\'h1e ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:519: Bit extraction of var[79:0] requires 7 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T75 = io_chanxy_config[5\'h13 :5\'h10 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:521: Bit extraction of var[195:0] requires 8 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T77 = io_chanxy_in[6\'h30 :6\'h28 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:527: Bit extraction of var[79:0] requires 7 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T83 = io_chanxy_config[5\'h17 :5\'h14 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:529: Bit extraction of var[195:0] requires 8 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T85 = io_chanxy_in[6\'h3a :6\'h31 ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:535: Bit extraction of var[79:0] requires 7 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T91 = io_chanxy_config[5\'h1b :5\'h18 ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:537: Bit extraction of var[195:0] requires 8 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T93 = io_chanxy_in[7\'h44 :6\'h3b ];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:543: Bit extraction of var[79:0] requires 7 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T99 = io_chanxy_config[5\'h1f :5\'h1c ];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:545: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T101 = io_chanxy_in[7\'h4e :7\'h45 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:551: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T107 = io_chanxy_config[6\'h23 :6\'h20 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:553: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T109 = io_chanxy_in[7\'h58 :7\'h4f ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:559: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T115 = io_chanxy_config[6\'h27 :6\'h24 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:561: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T117 = io_chanxy_in[7\'h61 :7\'h59 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:567: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T123 = io_chanxy_config[6\'h2b :6\'h28 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:569: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T125 = io_chanxy_in[7\'h6b :7\'h62 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:575: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T131 = io_chanxy_config[6\'h2f :6\'h2c ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:577: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T133 = io_chanxy_in[7\'h75 :7\'h6c ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:583: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T139 = io_chanxy_config[6\'h33 :6\'h30 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:585: Bit extraction of var[195:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T141 = io_chanxy_in[7\'h7f :7\'h76 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:591: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T147 = io_chanxy_config[6\'h37 :6\'h34 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:599: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T155 = io_chanxy_config[6\'h3b :6\'h38 ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:607: Bit extraction of var[79:0] requires 7 bit index, not 6 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T163 = io_chanxy_config[6\'h3f :6\'h3c ];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:668: Bit extraction of var[21:0] requires 5 bit index, not 1 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T223 = io_ipin_config[1\'h1 :1\'h0 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:670: Bit extraction of var[43:0] requires 6 bit index, not 1 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T225 = io_ipin_in[2\'h3 :1\'h0 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:676: Bit extraction of var[21:0] requires 5 bit index, not 2 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T231 = io_ipin_config[2\'h3 :2\'h2 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:678: Bit extraction of var[43:0] requires 6 bit index, not 3 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T233 = io_ipin_in[3\'h7 :3\'h4 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:684: Bit extraction of var[21:0] requires 5 bit index, not 3 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T239 = io_ipin_config[3\'h5 :3\'h4 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:686: Bit extraction of var[43:0] requires 6 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T241 = io_ipin_in[4\'hb :4\'h8 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:692: Bit extraction of var[21:0] requires 5 bit index, not 3 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T247 = io_ipin_config[3\'h7 :3\'h6 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:694: Bit extraction of var[43:0] requires 6 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T249 = io_ipin_in[4\'hf :4\'hc ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:700: Bit extraction of var[21:0] requires 5 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T255 = io_ipin_config[4\'h9 :4\'h8 ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:702: Bit extraction of var[43:0] requires 6 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T257 = io_ipin_in[5\'h13 :5\'h10 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:708: Bit extraction of var[21:0] requires 5 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T263 = io_ipin_config[4\'hb :4\'ha ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:710: Bit extraction of var[43:0] requires 6 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T265 = io_ipin_in[5\'h17 :5\'h14 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:716: Bit extraction of var[21:0] requires 5 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T271 = io_ipin_config[4\'hd :4\'hc ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:718: Bit extraction of var[43:0] requires 6 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T273 = io_ipin_in[5\'h1b :5\'h18 ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:724: Bit extraction of var[21:0] requires 5 bit index, not 4 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T279 = io_ipin_config[4\'hf :4\'he ];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:726: Bit extraction of var[43:0] requires 6 bit index, not 5 bits.\n                                                                                             : ... In instance lut_tile.this_sbcb\n  assign T281 = io_ipin_in[5\'h1f :5\'h1c ];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:79: Bit extraction of var[3:0] requires 2 bit index, not 1 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T6 = io_mux_configs[1\'h1 :1\'h1 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:80: Bit extraction of var[63:0] requires 6 bit index, not 5 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T7 = io_lut_configs[5\'h1f :5\'h10 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:81: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T8 = io_clb_in[3\'h7 :3\'h4 ];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:82: Bit extraction of var[3:0] requires 2 bit index, not 1 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T9 = io_mux_configs[1\'h0 :1\'h0 ];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:83: Bit extraction of var[63:0] requires 6 bit index, not 1 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T10 = io_lut_configs[4\'hf :1\'h0 ];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:84: Bit extraction of var[15:0] requires 4 bit index, not 1 bits.\n                                                                                            : ... In instance lut_tile.this_clb\n  assign T11 = io_clb_in[2\'h3 :1\'h0 ];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:776: Bit extraction of var[255:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile\n  assign T2 = this_config_io_configs_out[8\'h83 :7\'h44 ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:778: Bit extraction of var[255:0] requires 8 bit index, not 7 bits.\n                                                                                             : ... In instance lut_tile\n  assign T4 = this_config_io_configs_out[7\'h43 :7\'h40 ];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:779: Bit extraction of var[255:0] requires 8 bit index, not 1 bits.\n                                                                                             : ... In instance lut_tile\n  assign T5 = this_config_io_configs_out[6\'h3f :1\'h0 ];\n                                        ^\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:788: Cannot find file containing module: \'xbar\'\n  xbar this_xbar(.clk(clk), .reset(reset),\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/full-fpga-testing/tiny/src,data/full_repos/permissive/49670587/xbar\n             data/full_repos/permissive/49670587/full-fpga-testing/tiny/src,data/full_repos/permissive/49670587/xbar.v\n             data/full_repos/permissive/49670587/full-fpga-testing/tiny/src,data/full_repos/permissive/49670587/xbar.sv\n             xbar\n             xbar.v\n             xbar.sv\n             obj_dir/xbar\n             obj_dir/xbar.v\n             obj_dir/xbar.sv\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/tiny/src/lut_tile.v:792: Cannot find file containing module: \'configs_latches_8\'\n    configs_latches_8 this_config(.clk(clk), .reset(reset),\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 54 warning(s)\n'
module lut_tile(input clk, input reset,
    input  io_ff_en,
    input [31:0] io_configs_in,
    input [7:0] io_configs_en,
    input [43:0] io_ipin_in,
    input [195:0] io_chanxy_in,
    output[19:0] io_chanxy_out,
    output[3:0] io_opin_out);

  wire[79:0] T0;
  wire[255:0] this_config_io_configs_out;
  wire[21:0] T1;
  wire[63:0] T2;
  wire[14:0] T3;
  wire[10:0] this_sbcb_io_ipin_out;
  wire[3:0] this_clb_io_clb_out;
  wire[3:0] T4;
  wire[63:0] T5;
  wire[15:0] this_xbar_io_xbar_out;
  wire[19:0] this_sbcb_io_chanxy_out;

  assign T0 = this_config_io_configs_out[8'he9:8'h9a];
  assign T1 = this_config_io_configs_out[8'h99:8'h84];
  assign T2 = this_config_io_configs_out[8'h83:7'h44];
  assign T3 = {this_clb_io_clb_out, this_sbcb_io_ipin_out};
  assign T4 = this_config_io_configs_out[7'h43:7'h40];
  assign T5 = this_config_io_configs_out[6'h3f:1'h0];
  assign io_opin_out = this_clb_io_clb_out;
  assign io_chanxy_out = this_sbcb_io_chanxy_out;
  clb this_clb(.clk(clk), .reset(reset),
       .io_clb_in( this_xbar_io_xbar_out ),
       .io_clb_out( this_clb_io_clb_out ),
       .io_lut_configs( T5 ),
       .io_mux_configs( T4 ),
       .io_ff_en( io_ff_en ));
  xbar this_xbar(.clk(clk), .reset(reset),
       .io_xbar_in( T3 ),
       .io_xbar_out( this_xbar_io_xbar_out ),
       .io_mux_configs( T2 ));
    configs_latches_8 this_config(.clk(clk), .reset(reset),
       .io_d_in( io_configs_in ),
       .io_configs_out( this_config_io_configs_out ),
       .io_configs_en( io_configs_en ));
  sbcb this_sbcb(
       .io_ipin_in( io_ipin_in ),
       .io_ipin_config( T1 ),
       .io_chanxy_in( io_chanxy_in ),
       .io_chanxy_config( T0 ),
       .io_ipin_out( this_sbcb_io_ipin_out ),
       .io_chanxy_out( this_sbcb_io_chanxy_out ));
endmodule
module lut_tile(input clk, input reset,
    input  io_ff_en,
    input [31:0] io_configs_in,
    input [7:0] io_configs_en,
    input [43:0] io_ipin_in,
    input [195:0] io_chanxy_in,
    output[19:0] io_chanxy_out,
    output[3:0] io_opin_out);


  wire[79:0] T0;
  wire[255:0] this_config_io_configs_out;
  wire[21:0] T1;
  wire[63:0] T2;
  wire[14:0] T3;
  wire[10:0] this_sbcb_io_ipin_out;
  wire[3:0] this_clb_io_clb_out;
  wire[3:0] T4;
  wire[63:0] T5;
  wire[15:0] this_xbar_io_xbar_out;
  wire[19:0] this_sbcb_io_chanxy_out;

  assign T0 = this_config_io_configs_out[8'he9:8'h9a];
  assign T1 = this_config_io_configs_out[8'h99:8'h84];
  assign T2 = this_config_io_configs_out[8'h83:7'h44];
  assign T3 = {this_clb_io_clb_out, this_sbcb_io_ipin_out};
  assign T4 = this_config_io_configs_out[7'h43:7'h40];
  assign T5 = this_config_io_configs_out[6'h3f:1'h0];
  assign io_opin_out = this_clb_io_clb_out;
  assign io_chanxy_out = this_sbcb_io_chanxy_out;
  clb this_clb(.clk(clk), .reset(reset),
       .io_clb_in( this_xbar_io_xbar_out ),
       .io_clb_out( this_clb_io_clb_out ),
       .io_lut_configs( T5 ),
       .io_mux_configs( T4 ),
       .io_ff_en( io_ff_en ));
  xbar this_xbar(.clk(clk), .reset(reset),
       .io_xbar_in( T3 ),
       .io_xbar_out( this_xbar_io_xbar_out ),
       .io_mux_configs( T2 ));
    configs_latches_8 this_config(.clk(clk), .reset(reset),
       .io_d_in( io_configs_in ),
       .io_configs_out( this_config_io_configs_out ),
       .io_configs_en( io_configs_en ));
  sbcb this_sbcb(
       .io_ipin_in( io_ipin_in ),
       .io_ipin_config( T1 ),
       .io_chanxy_in( io_chanxy_in ),
       .io_chanxy_config( T0 ),
       .io_ipin_out( this_sbcb_io_ipin_out ),
       .io_chanxy_out( this_sbcb_io_chanxy_out ));
endmodule