data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:36: Cannot find file containing module: \'setting_reg\'\n   setting_reg #(.my_addr(BASE),.width(1)) sr_16to8\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.sv\n             setting_reg\n             setting_reg.v\n             setting_reg.sv\n             obj_dir/setting_reg\n             obj_dir/setting_reg.v\n             obj_dir/setting_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_streamid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_classid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_classid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_secs\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_tics\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:58: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_tics\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:71: Operator SUB expects 32 or 9 bits on the RHS, but RHS\'s VARREF \'has_trailer_reg\' generates 1 bits.\n                                                                                            : ... In instance dspengine_16to8\n   wire        last = (read_adr + 1) == (access_len - has_trailer_reg);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:98: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'access_len\' generates 9 bits.\n                                                                                            : ... In instance dspengine_16to8\n       new_header[15:0] <= access_len;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:99: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'access_len\' generates 9 bits.\n                                                                                            : ... In instance dspengine_16to8\n       length <= access_len;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:102: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'hdr_length\' generates 4 bits.\n                                                                                             : ... In instance dspengine_16to8\n     read_adr <= hdr_length;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:103: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'hdr_length\' generates 4 bits.\n                                                                                             : ... In instance dspengine_16to8\n     write_adr <= hdr_length;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:159: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'write_adr\' generates 9 bits.\n                                                                                             : ... In instance dspengine_16to8\n       new_header[15:0] <= write_adr + 1;\n                                     ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:194: Cannot find file containing module: \'pipectrl\'\n   pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl\n   ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:205: Cannot find file containing module: \'clip_reg\'\n   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i\n   ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_16to8.v:208: Cannot find file containing module: \'clip_reg\'\n   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q\n   ^~~~~~~~\n%Error: Exiting due to 4 error(s), 12 warning(s)\n'
module dspengine_16to8
  #(parameter BASE = 0,
    parameter BUF_SIZE = 9)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,

    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
    );

   wire convert;
   setting_reg #(.my_addr(BASE),.width(1)) sr_16to8
     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(convert),.changed());

   reg [2:0] 	 dsp_state;
   localparam DSP_IDLE = 0;
   localparam DSP_PARSE_HEADER = 1;
   localparam DSP_CONVERT = 2;
   localparam DSP_CONVERT_DRAIN_PIPE = 3;
   localparam DSP_READ_TRAILER = 4;
   localparam DSP_WRITE_TRAILER = 5;
   localparam DSP_WRITE_HEADER = 6;
   localparam DSP_DONE = 7;


   wire 	 is_if_data = (access_dat_i[31:29] == 3'b000);
   wire 	 has_streamid = access_dat_i[28];
   wire 	 has_classid = access_dat_i[27];
   wire 	 has_trailer = access_dat_i[26];

   wire 	 has_secs = |access_dat_i[23:22];
   wire 	 has_tics = |access_dat_i[21:20];
   wire [3:0] 	 hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;
   
   wire [35:0] 	 prod_i, prod_q;
   wire [15:0] 	 scaled_i, scaled_q;
   wire [7:0] 	 i8, q8;
   reg [7:0] 	 i8_reg, q8_reg;
   wire 	 stb_read, stb_clip, val_read, val_clip;
   wire 	 stb_out, stb_reg;
   reg 		 even;
   
   reg [BUF_SIZE-1:0] read_adr, write_adr;
   reg 		      has_trailer_reg;
   
   wire 	      last = (read_adr + 1) == (access_len - has_trailer_reg);
   wire 	      last_o, even_o;

   wire 	      stb_write = stb_out & (even_o | last_o);
   wire 	      send_to_pipe = ~stb_write & (dsp_state == DSP_CONVERT);
   reg [31:0] 	      new_header, new_trailer, trailer_mask;
   reg [15:0] 	      length;
   reg 		      wait_for_trailer;
   
   always @(posedge clk)
     if(reset | clear)
       dsp_state <= DSP_IDLE;
     else
       case(dsp_state)
	 DSP_IDLE :
	   begin
	      read_adr <= 0;
	      write_adr <= 0;
	      even <= 0;
	      if(access_ok)
		dsp_state <= DSP_PARSE_HEADER;
	   end
	 
	 DSP_PARSE_HEADER :
	   begin
	      has_trailer_reg <= has_trailer;
	      new_header[31:16] <= access_dat_i[31:16];
	      new_header[15:0] <= access_len;
	      length <= access_len;
	      if(is_if_data & convert)
		begin
		   read_adr <= hdr_length;
		   write_adr <= hdr_length;
		   dsp_state <= DSP_CONVERT;
		end
	      else
		dsp_state <= DSP_WRITE_HEADER;
	   end
	 
	 DSP_CONVERT:
	   begin
	      new_header[26] <= 1'b1;
	      if(stb_write)
		write_adr <= write_adr + 1;
	      else if(stb_read)
		begin
		   read_adr <= read_adr + 1;
		   even <= ~even;
		   if(last)
		     begin
			dsp_state <= DSP_CONVERT_DRAIN_PIPE;
			if(~even)
			  trailer_mask <= 32'h00400400;
			else
			  trailer_mask <= 32'h00400000;
		     end
		end
	   end
	 
	 DSP_CONVERT_DRAIN_PIPE :
	   if(stb_write)
	     begin
		write_adr <= write_adr + 1;
		if(last_o)
		  if(has_trailer_reg)
		    begin
		       dsp_state <= DSP_READ_TRAILER;
		       wait_for_trailer <= 0;
		    end
		  else
		    begin
		       dsp_state <= DSP_WRITE_TRAILER;
		       new_trailer <= trailer_mask;
		    end
	     end

	 DSP_READ_TRAILER :
	   begin
	      wait_for_trailer <= 1;
	      if(wait_for_trailer)
		dsp_state <= DSP_WRITE_TRAILER;
	      new_trailer <= access_dat_i[31:0] | trailer_mask;
	   end

	 DSP_WRITE_TRAILER :
	   begin
	      dsp_state <= DSP_WRITE_HEADER;
	      write_adr <= 0;
	      new_header[15:0] <= write_adr + 1;
	   end

	 DSP_WRITE_HEADER :
	   dsp_state <= DSP_DONE;

	 DSP_DONE :
	   begin
	      read_adr <= 0;
	      write_adr <= 0;
	      dsp_state <= DSP_IDLE;
	   end
       endcase

   assign access_skip_read = 0;
   assign access_done = (dsp_state == DSP_DONE);

   assign access_stb = 1;

   assign access_we = (dsp_state == DSP_WRITE_HEADER) | 
		      (dsp_state == DSP_WRITE_TRAILER) |
		      stb_write;

   assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } :
			 (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
			 (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } :
			 {4'h0, i8_reg, q8_reg, i8, q8 };
   
   assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr;
      

   
   wire [15:0] i16 = access_dat_i[31:16];
   wire [15:0] q16 = access_dat_i[15:0];

   pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl
     (.clk(clk), .reset(reset),
      .src_rdy_i(send_to_pipe), .dst_rdy_o(),
      .src_rdy_o(stb_out), .dst_rdy_i(1),
      .strobes({stb_clip,stb_read}), .valids({val_clip,val_read}),
      .tag_i({last,even}), .tag_o({last_o,even_o}));

   always @(posedge clk)
     if(stb_out & ~even_o)
       {i8_reg,q8_reg} <= {i8,q8};

   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i
     (.clk(clk), .in(i16), .out(i8), .strobe_in(stb_clip), .strobe_out());

   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q
     (.clk(clk), .in(q16), .out(q8), .strobe_in(stb_clip), .strobe_out());

endmodule
module dspengine_16to8
  #(parameter BASE = 0,
    parameter BUF_SIZE = 9)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,

    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
    );


   wire convert;
   setting_reg #(.my_addr(BASE),.width(1)) sr_16to8
     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(convert),.changed());

   reg [2:0] 	 dsp_state;
   localparam DSP_IDLE = 0;
   localparam DSP_PARSE_HEADER = 1;
   localparam DSP_CONVERT = 2;
   localparam DSP_CONVERT_DRAIN_PIPE = 3;
   localparam DSP_READ_TRAILER = 4;
   localparam DSP_WRITE_TRAILER = 5;
   localparam DSP_WRITE_HEADER = 6;
   localparam DSP_DONE = 7;


   wire 	 is_if_data = (access_dat_i[31:29] == 3'b000);
   wire 	 has_streamid = access_dat_i[28];
   wire 	 has_classid = access_dat_i[27];
   wire 	 has_trailer = access_dat_i[26];

   wire 	 has_secs = |access_dat_i[23:22];
   wire 	 has_tics = |access_dat_i[21:20];
   wire [3:0] 	 hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;
   
   wire [35:0] 	 prod_i, prod_q;
   wire [15:0] 	 scaled_i, scaled_q;
   wire [7:0] 	 i8, q8;
   reg [7:0] 	 i8_reg, q8_reg;
   wire 	 stb_read, stb_clip, val_read, val_clip;
   wire 	 stb_out, stb_reg;
   reg 		 even;
   
   reg [BUF_SIZE-1:0] read_adr, write_adr;
   reg 		      has_trailer_reg;
   
   wire 	      last = (read_adr + 1) == (access_len - has_trailer_reg);
   wire 	      last_o, even_o;

   wire 	      stb_write = stb_out & (even_o | last_o);
   wire 	      send_to_pipe = ~stb_write & (dsp_state == DSP_CONVERT);
   reg [31:0] 	      new_header, new_trailer, trailer_mask;
   reg [15:0] 	      length;
   reg 		      wait_for_trailer;
   
   always @(posedge clk)
     if(reset | clear)
       dsp_state <= DSP_IDLE;
     else
       case(dsp_state)
	 DSP_IDLE :
	   begin
	      read_adr <= 0;
	      write_adr <= 0;
	      even <= 0;
	      if(access_ok)
		dsp_state <= DSP_PARSE_HEADER;
	   end
	 
	 DSP_PARSE_HEADER :
	   begin
	      has_trailer_reg <= has_trailer;
	      new_header[31:16] <= access_dat_i[31:16];
	      new_header[15:0] <= access_len;
	      length <= access_len;
	      if(is_if_data & convert)
		begin
		   read_adr <= hdr_length;
		   write_adr <= hdr_length;
		   dsp_state <= DSP_CONVERT;
		end
	      else
		dsp_state <= DSP_WRITE_HEADER;
	   end
	 
	 DSP_CONVERT:
	   begin
	      new_header[26] <= 1'b1;
	      if(stb_write)
		write_adr <= write_adr + 1;
	      else if(stb_read)
		begin
		   read_adr <= read_adr + 1;
		   even <= ~even;
		   if(last)
		     begin
			dsp_state <= DSP_CONVERT_DRAIN_PIPE;
			if(~even)
			  trailer_mask <= 32'h00400400;
			else
			  trailer_mask <= 32'h00400000;
		     end
		end
	   end
	 
	 DSP_CONVERT_DRAIN_PIPE :
	   if(stb_write)
	     begin
		write_adr <= write_adr + 1;
		if(last_o)
		  if(has_trailer_reg)
		    begin
		       dsp_state <= DSP_READ_TRAILER;
		       wait_for_trailer <= 0;
		    end
		  else
		    begin
		       dsp_state <= DSP_WRITE_TRAILER;
		       new_trailer <= trailer_mask;
		    end
	     end

	 DSP_READ_TRAILER :
	   begin
	      wait_for_trailer <= 1;
	      if(wait_for_trailer)
		dsp_state <= DSP_WRITE_TRAILER;
	      new_trailer <= access_dat_i[31:0] | trailer_mask;
	   end

	 DSP_WRITE_TRAILER :
	   begin
	      dsp_state <= DSP_WRITE_HEADER;
	      write_adr <= 0;
	      new_header[15:0] <= write_adr + 1;
	   end

	 DSP_WRITE_HEADER :
	   dsp_state <= DSP_DONE;

	 DSP_DONE :
	   begin
	      read_adr <= 0;
	      write_adr <= 0;
	      dsp_state <= DSP_IDLE;
	   end
       endcase

   assign access_skip_read = 0;
   assign access_done = (dsp_state == DSP_DONE);

   assign access_stb = 1;

   assign access_we = (dsp_state == DSP_WRITE_HEADER) | 
		      (dsp_state == DSP_WRITE_TRAILER) |
		      stb_write;

   assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } :
			 (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
			 (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } :
			 {4'h0, i8_reg, q8_reg, i8, q8 };
   
   assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr;
      

   
   wire [15:0] i16 = access_dat_i[31:16];
   wire [15:0] q16 = access_dat_i[15:0];

   pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl
     (.clk(clk), .reset(reset),
      .src_rdy_i(send_to_pipe), .dst_rdy_o(),
      .src_rdy_o(stb_out), .dst_rdy_i(1),
      .strobes({stb_clip,stb_read}), .valids({val_clip,val_read}),
      .tag_i({last,even}), .tag_o({last_o,even_o}));

   always @(posedge clk)
     if(stb_out & ~even_o)
       {i8_reg,q8_reg} <= {i8,q8};

   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i
     (.clk(clk), .in(i16), .out(i8), .strobe_in(stb_clip), .strobe_out());

   clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q
     (.clk(clk), .in(q16), .out(q8), .strobe_in(stb_clip), .strobe_out());

endmodule