data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Mux32B8to1.v
data/verilator_xmls/05de083a-bc53-4c09-b2a5-b54baf40286d.xml
module Mux32B8to1(
    input [31:0] dIn0,
    input [31:0] dIn1,
    input [31:0] dIn2,
    input [31:0] dIn3,
    input [31:0] dIn4,
    input [31:0] dIn5,
    input [31:0] dIn6,
    input [31:0] dIn7,
    input [2:0] sel,
    output reg [31:0] dOut = 32'h00000000
    );
    
    always @ (*) begin
    case(sel)
      3'b000: dOut[31:0] <= dIn0[31:0];
      3'b001: dOut[31:0] <= dIn1[31:0];
      3'b010: dOut[31:0] <= dIn2[31:0];
      3'b011: dOut[31:0] <= dIn3[31:0];
      3'b100: dOut[31:0] <= dIn4[31:0];
      3'b101: dOut[31:0] <= dIn5[31:0];
      3'b110: dOut[31:0] <= dIn6[31:0];
      3'b111: dOut[31:0] <= dIn7[31:0];
    endcase
  end
endmodule
module Mux32B8to1(
    input [31:0] dIn0,
    input [31:0] dIn1,
    input [31:0] dIn2,
    input [31:0] dIn3,
    input [31:0] dIn4,
    input [31:0] dIn5,
    input [31:0] dIn6,
    input [31:0] dIn7,
    input [2:0] sel,
    output reg [31:0] dOut = 32'h00000000
    );

    
    always @ (*) begin
    case(sel)
      3'b000: dOut[31:0] <= dIn0[31:0];
      3'b001: dOut[31:0] <= dIn1[31:0];
      3'b010: dOut[31:0] <= dIn2[31:0];
      3'b011: dOut[31:0] <= dIn3[31:0];
      3'b100: dOut[31:0] <= dIn4[31:0];
      3'b101: dOut[31:0] <= dIn5[31:0];
      3'b110: dOut[31:0] <= dIn6[31:0];
      3'b111: dOut[31:0] <= dIn7[31:0];
    endcase
  end
endmodule