data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #(PERIOD/2)  clk380hz=~clk380hz;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #(5*PERIOD)  clk10hz=~clk10hz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1000 up_in[2] = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1000 down_in[1] = 1;\n    ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/request_tb.v:33: Cannot find file containing module: \'request\'\nrequest  u_request (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request.sv\n             request\n             request.v\n             request.sv\n             obj_dir/request\n             obj_dir/request.v\n             obj_dir/request.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_request;     


parameter PERIOD  = 10;



reg   clk380hz                             = 0 ;
reg   clk10hz                              = 0 ;
reg   rst                                  = 0 ;
reg   [7:0]  curr_floor                    = 0 ;
reg   [3:0]  running_state                 = 0 ;
reg   [3:0]  door_state                    = 4'b0100 ;
reg   [`F_N-1:0]  floor_in                 = 0 ;
reg   [`F_N-1:0]  up_in                    = 0 ;
reg   [`F_N-1:0]  down_in                  = 0 ;


wire  [2:0]  req                           ;
wire  [7:0]  demand_state                  ;

always #(PERIOD/2)  clk380hz=~clk380hz;
always #(5*PERIOD)  clk10hz=~clk10hz;






request  u_request (
    .clk380hz                ( clk380hz                  ),
    .clk10hz                 ( clk10hz                   ),
    .clk1hz                  ( clk1hz                    ),
    .rst                     ( rst                       ),
    .curr_floor              ( curr_floor     [7:0]      ),
    .running_state           ( running_state  [3:0]      ),
    .door_state              ( door_state     [3:0]      ),
    .floor_in                ( floor_in       [`F_N-1:0] ),
    .up_in                   ( up_in          [`F_N-1:0] ),
    .down_in                 ( down_in        [`F_N-1:0] ),

    .req                     ( req            [2:0]      ),
    .demand_state            ( demand_state   [7:0]      )
);

initial
begin
    #1000 up_in[2] = 1;
    #1000 down_in[1] = 1;
end

endmodule
module tb_request;
     


parameter PERIOD  = 10;



reg   clk380hz                             = 0 ;
reg   clk10hz                              = 0 ;
reg   rst                                  = 0 ;
reg   [7:0]  curr_floor                    = 0 ;
reg   [3:0]  running_state                 = 0 ;
reg   [3:0]  door_state                    = 4'b0100 ;
reg   [`F_N-1:0]  floor_in                 = 0 ;
reg   [`F_N-1:0]  up_in                    = 0 ;
reg   [`F_N-1:0]  down_in                  = 0 ;


wire  [2:0]  req                           ;
wire  [7:0]  demand_state                  ;

always #(PERIOD/2)  clk380hz=~clk380hz;
always #(5*PERIOD)  clk10hz=~clk10hz;






request  u_request (
    .clk380hz                ( clk380hz                  ),
    .clk10hz                 ( clk10hz                   ),
    .clk1hz                  ( clk1hz                    ),
    .rst                     ( rst                       ),
    .curr_floor              ( curr_floor     [7:0]      ),
    .running_state           ( running_state  [3:0]      ),
    .door_state              ( door_state     [3:0]      ),
    .floor_in                ( floor_in       [`F_N-1:0] ),
    .up_in                   ( up_in          [`F_N-1:0] ),
    .down_in                 ( down_in        [`F_N-1:0] ),

    .req                     ( req            [2:0]      ),
    .demand_state            ( demand_state   [7:0]      )
);

initial
begin
    #1000 up_in[2] = 1;
    #1000 down_in[1] = 1;
end

endmodule