data/full_repos/permissive/501791642/sim/rom_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLK = ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #30 phase = 127;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #30 PROGRAM = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #30 phase = 127;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #30 PROGRAM = 2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/rom_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #30 phase = 127;\n    ^\n%Error: data/full_repos/permissive/501791642/sim/rom_tb.v:15: Cannot find file containing module: \'step_size_rom\'\nstep_size_rom rom1(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/step_size_rom\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/step_size_rom.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/step_size_rom.sv\n             step_size_rom\n             step_size_rom.v\n             step_size_rom.sv\n             obj_dir/step_size_rom\n             obj_dir/step_size_rom.v\n             obj_dir/step_size_rom.sv\n%Error: data/full_repos/permissive/501791642/sim/rom_tb.v:22: Cannot find file containing module: \'sample_rom\'\nsample_rom rom2(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_tb;

reg CLK;
reg CE;
reg [6:0] NOTE_NUM;
reg [6:0] phase;
reg [6:0] PROGRAM;


wire [15:0] step;
wire [7:0] SAMPLE_OUT;

step_size_rom rom1(
    .CLK(CLK),
    .CE(CE),
    .A(NOTE_NUM),
    .D(step)
);

sample_rom rom2(
    .CLK(CLK),
    .CE(CE),
    .A0(phase),
    .A1(PROGRAM),
    .D(SAMPLE_OUT)
);



initial begin
    CE = 1;
    CLK = 0;
    NOTE_NUM = 0;
    phase = 0;
    PROGRAM = 0;
end

always #5 CLK = ~CLK;

initial begin




    
    #30 phase = 127;
    #30 PROGRAM = 1;
    phase = 0;
    #30 phase = 127;
    #30 PROGRAM = 2;
    phase = 0;
    #30 phase = 127;

    
end

endmodule
module rom_tb;


reg CLK;
reg CE;
reg [6:0] NOTE_NUM;
reg [6:0] phase;
reg [6:0] PROGRAM;


wire [15:0] step;
wire [7:0] SAMPLE_OUT;

step_size_rom rom1(
    .CLK(CLK),
    .CE(CE),
    .A(NOTE_NUM),
    .D(step)
);

sample_rom rom2(
    .CLK(CLK),
    .CE(CE),
    .A0(phase),
    .A1(PROGRAM),
    .D(SAMPLE_OUT)
);



initial begin
    CE = 1;
    CLK = 0;
    NOTE_NUM = 0;
    phase = 0;
    PROGRAM = 0;
end

always #5 CLK = ~CLK;

initial begin




    
    #30 phase = 127;
    #30 PROGRAM = 1;
    phase = 0;
    #30 phase = 127;
    #30 PROGRAM = 2;
    phase = 0;
    #30 phase = 127;

    
end

endmodule