data/full_repos/permissive/44647742/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #15\n ^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/counter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1 clk=~clk;\n ^\n%Error: data/full_repos/permissive/44647742/counter_tb.v:53: Cannot find file containing module: \'counter\'\n counter the_counter(rst_n,inc,dec,clk,counter_result);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/counter\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/counter.v\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb(
    );
	reg clk;
	reg rst_n;
	wire [3:0]counter_result;
	reg inc;
	reg dec;
	
	initial begin
	clk = 0;
	rst_n = 0;
	inc = 1;
	dec = 0;
	#2
	inc = 0;
	#3
	rst_n = 1;
	#5
	inc = 1;
	#10
	inc = 0;
	dec = 1;
	#15
	dec = 0;
	#20
	$finish;
	end
	
	always begin
	#1 clk=~clk;
	end
	
	counter the_counter(rst_n,inc,dec,clk,counter_result);

endmodule
module counter_tb(
    );

	reg clk;
	reg rst_n;
	wire [3:0]counter_result;
	reg inc;
	reg dec;
	
	initial begin
	clk = 0;
	rst_n = 0;
	inc = 1;
	dec = 0;
	#2
	inc = 0;
	#3
	rst_n = 1;
	#5
	inc = 1;
	#10
	inc = 0;
	dec = 1;
	#15
	dec = 0;
	#20
	$finish;
	end
	
	always begin
	#1 clk=~clk;
	end
	
	counter the_counter(rst_n,inc,dec,clk,counter_result);

endmodule