data/full_repos/permissive/493019833/test/testcase/firrtl/Complex2R2WCMem.lo/reference/Complex2R2WCMem.lo.v
data/verilator_xmls/c981a854-060e-4ebd-8318-3d4658714ca0.xml
module MUX_UNSIGNED(y, sel, a, b);
    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = sel ? a : b;
endmodule
module MUX_UNSIGNED(y, sel, a, b);

    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = sel ? a : b;
endmodule