data/full_repos/permissive/513806017/generated/Leros.v
data/verilator_xmls/89e8d668-0412-4ac1-97d0-bdf2db6b5e63.xml
module Alu(
  input         clock,
  input         reset,
  input  [2:0]  io_op,
  input  [31:0] io_din,
  input         io_ena,
  output [31:0] io_accu
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  reg [31:0] a;
  wire [31:0] _res_T_1 = a + io_din;
  wire [31:0] _res_T_3 = a - io_din;
  wire [31:0] _res_T_4 = a & io_din;
  wire [31:0] _res_T_5 = a | io_din;
  wire [31:0] _res_T_6 = a ^ io_din;
  wire [31:0] _GEN_0 = 3'h6 == io_op ? io_din : a;
  wire [31:0] _GEN_1 = 3'h7 == io_op ? {{1'd0}, a[31:1]} : _GEN_0;
  wire [31:0] _GEN_2 = 3'h5 == io_op ? _res_T_6 : _GEN_1;
  wire [31:0] _GEN_3 = 3'h4 == io_op ? _res_T_5 : _GEN_2;
  wire [31:0] _GEN_4 = 3'h3 == io_op ? _res_T_4 : _GEN_3;
  wire [31:0] _GEN_5 = 3'h2 == io_op ? _res_T_3 : _GEN_4;
  assign io_accu = a;
  always @(posedge clock) begin
    if (reset) begin
      a <= 32'h0;
    end else if (io_ena) begin
      if (!(3'h0 == io_op)) begin
        if (3'h1 == io_op) begin
          a <= _res_T_1;
        end else begin
          a <= _GEN_5;
        end
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a = _RAND_0[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Alu(
  input         clock,
  input         reset,
  input  [2:0]  io_op,
  input  [31:0] io_din,
  input         io_ena,
  output [31:0] io_accu
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  reg [31:0] a;
  wire [31:0] _res_T_1 = a + io_din;
  wire [31:0] _res_T_3 = a - io_din;
  wire [31:0] _res_T_4 = a & io_din;
  wire [31:0] _res_T_5 = a | io_din;
  wire [31:0] _res_T_6 = a ^ io_din;
  wire [31:0] _GEN_0 = 3'h6 == io_op ? io_din : a;
  wire [31:0] _GEN_1 = 3'h7 == io_op ? {{1'd0}, a[31:1]} : _GEN_0;
  wire [31:0] _GEN_2 = 3'h5 == io_op ? _res_T_6 : _GEN_1;
  wire [31:0] _GEN_3 = 3'h4 == io_op ? _res_T_5 : _GEN_2;
  wire [31:0] _GEN_4 = 3'h3 == io_op ? _res_T_4 : _GEN_3;
  wire [31:0] _GEN_5 = 3'h2 == io_op ? _res_T_3 : _GEN_4;
  assign io_accu = a;
  always @(posedge clock) begin
    if (reset) begin
      a <= 32'h0;
    end else if (io_ena) begin
      if (!(3'h0 == io_op)) begin
        if (3'h1 == io_op) begin
          a <= _res_T_1;
        end else begin
          a <= _GEN_5;
        end
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a = _RAND_0[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule