data/full_repos/permissive/499944578/rtl/test/top/top_Test.v
1: b'%Error: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:144: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("top_Test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:145: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,top_Test);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:148: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:151: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:153: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:155: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:1246: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:1249: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:1256: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:1258: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/top/top_Test.v:1298: Unsupported: Ignoring delay on this delayed statement.\n            #TIMEOUT;\n            ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module frag_ram_dual_clock_32_32(
    input      [31:0] data,
    input      [31:0] read_addr,
    input      [31:0] write_addr,
    input                       we,
    input                       read_clk,
    input                       write_clk,
    input                       re,
    output reg [31:0] q
);
    
    reg [(2**16 - 1):0][31:0] ram; 

    initial begin
        ram = 'b0;
        q = 'b0;
    end

    always @(posedge write_clk) begin: WRITE
        if (we) begin 
            ram[write_addr] <= data;
            $display("{\"time\":\"%0t\",\"label\":\"[frag_mem_write]\", \"data\":[\"0x%0h\",\"0x%0h\"]},", $time,write_addr,data);

        end
    end

    always @(posedge read_clk) begin: READ
        if (re) begin
            q <= ram[read_addr];
        end
    end
    
endmodule
module frag_ram_dual_clock_32_32(
    input      [31:0] data,
    input      [31:0] read_addr,
    input      [31:0] write_addr,
    input                       we,
    input                       read_clk,
    input                       write_clk,
    input                       re,
    output reg [31:0] q
);

    
    reg [(2**16 - 1):0][31:0] ram; 

    initial begin
        ram = 'b0;
        q = 'b0;
    end

    always @(posedge write_clk) begin: WRITE
        if (we) begin 
            ram[write_addr] <= data;
            $display("{\"time\":\"%0t\",\"label\":\"[frag_mem_write]\", \"data\":[\"0x%0h\",\"0x%0h\"]},", $time,write_addr,data);

        end
    end

    always @(posedge read_clk) begin: READ
        if (re) begin
            q <= ram[read_addr];
        end
    end
    
endmodule