data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:37: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:44: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:22: Cannot find file containing module: \'binary_to_gray\'\n    binary_to_gray #(N) dut_ab (a,b);\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/binary_to_gray\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/binary_to_gray.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test,data/full_repos/permissive/473423187/binary_to_gray.sv\n             binary_to_gray\n             binary_to_gray.v\n             binary_to_gray.sv\n             obj_dir/binary_to_gray\n             obj_dir/binary_to_gray.v\n             obj_dir/binary_to_gray.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:23: Cannot find file containing module: \'gray_to_binary\'\n    gray_to_binary #(N) dut_bc (b,c);\n    ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:36: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 10 bits.\n                                                                                                                  : ... In instance graycode_tb\n            a = i;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:43: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'i\' generates 10 bits.\n                                                                                                                  : ... In instance graycode_tb\n            a = N-i-1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/graycode_tb.sv:43: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                                  : ... In instance graycode_tb\n            a = N-i-1;\n              ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module graycode_tb #(
    parameter int N = 9
);

    logic [N-1:0] a, b, c, bp = '0;

    binary_to_gray #(N) dut_ab (a,b);
    gray_to_binary #(N) dut_bc (b,c);

    task check;
        assert(a == c);
        assert($signed($countones(b) - $countones(bp)) inside {-1,0,1});
        bp = b;
    endtask

    initial begin : p_stim
        logic [N:0] i;


        repeat(2) for (i = 0; i < 2**N; i++) begin
            a = i;
            #1;
            check();
        end


        for (i = 0; i < 2**N; i++) begin
            a = N-i-1;
            #1;
            check();
        end
    end

endmodule
module graycode_tb #(
    parameter int N = 9
);


    logic [N-1:0] a, b, c, bp = '0;

    binary_to_gray #(N) dut_ab (a,b);
    gray_to_binary #(N) dut_bc (b,c);

    task check;
        assert(a == c);
        assert($signed($countones(b) - $countones(bp)) inside {-1,0,1});
        bp = b;
    endtask

    initial begin : p_stim
        logic [N:0] i;


        repeat(2) for (i = 0; i < 2**N; i++) begin
            a = i;
            #1;
            check();
        end


        for (i = 0; i < 2**N; i++) begin
            a = N-i-1;
            #1;
            check();
        end
    end

endmodule