data/full_repos/permissive/491135068/opcode_decoder.v
1: b"%Error: data/full_repos/permissive/491135068/opcode_decoder.v:32: syntax error, unexpected ||, expecting ')' or ',' or or\n    always@(ibus_opcode || funct) begin\n                        ^~\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:44: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b010; \n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:50: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b011;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:56: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b000;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:62: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b110;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:68: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b100;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:74: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b011;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:82: syntax error, unexpected '=', expecting IDENTIFIER\n                        S = 3'b011;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:93: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b010; \n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:99: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b011;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:105: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b000;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:111: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b110;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:117: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b100;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:123: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b010;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:130: syntax error, unexpected '=', expecting IDENTIFIER\n                    S = 3'b010;\n                      ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:137: syntax error, unexpected '=', expecting IDENTIFIER\n                    store = 1'b1;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:143: syntax error, unexpected '=', expecting IDENTIFIER\n                    store = 1'b1;\n                          ^\n%Error: data/full_repos/permissive/491135068/opcode_decoder.v:148: syntax error, unexpected end\n    end\n    ^~~\n%Error: Cannot continue\n"
module opcode_decoder(
    input [5:0] ibus_opcode, funct,
    output reg imm, Cin, store, load, set, eq, eqType,
    output reg [2:0] S,
    output reg [1:0] setType
    );

    
    
    always@(ibus_opcode || funct) begin
        store = 1'b0;
        load  = 1'b0;
        set   = 1'b0;
        eq    = 1'b0;
        setType = 2'bx;
        case(ibus_opcode)
            6'b000000:
            begin
                case(funct)
                6'b000011:
                    begin
                    S = 3'b010; 
                    Cin = 0; 
                    imm = 1'b0;
                end
                6'b000010:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                    end
                6'b000001:
                    begin
                        S = 3'b000;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b000111:
                    begin
                        S = 3'b110;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b000100:
                    begin
                        S = 3'b100;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b110110:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                        set = 1'b1;
                        setType = 2'b00;
                    end
                6'b110111:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                        set = 1'b1;
                        setType = 2'b10;
                    end
                endcase
                
            end
            6'b000011:
                begin
                    S = 3'b010; 
                    Cin = 0; 
                    imm = 1'b1;
                end
            6'b000010:
                begin
                    S = 3'b011;
                    Cin = 1;
                    imm = 1'b1;
                end
            6'b000001:
                begin
                    S = 3'b000;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b001111:
                begin
                    S = 3'b110;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b001100:
                begin
                    S = 3'b100;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b011110:
                begin
                    S = 3'b010;
                    Cin = 0;
                    imm = 1'b1;
                    load = 1'b1;
                end
            6'b011111:
                begin
                    S = 3'b010;
                    Cin = 0;
                    imm = 1'b1;
                    store = 1'b1;
                end
            6'b110000:
                begin
                    store = 1'b1;
                    eq = 1'b1;
                    eqType = 1'b0;
                end
            6'b110001:
                begin
                    store = 1'b1;
                    eq = 1'b1;
                    eqType = 1'b1;
                end
        endcase
    end
endmodule
module opcode_decoder(
    input [5:0] ibus_opcode, funct,
    output reg imm, Cin, store, load, set, eq, eqType,
    output reg [2:0] S,
    output reg [1:0] setType
    );


    
    
    always@(ibus_opcode || funct) begin
        store = 1'b0;
        load  = 1'b0;
        set   = 1'b0;
        eq    = 1'b0;
        setType = 2'bx;
        case(ibus_opcode)
            6'b000000:
            begin
                case(funct)
                6'b000011:
                    begin
                    S = 3'b010; 
                    Cin = 0; 
                    imm = 1'b0;
                end
                6'b000010:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                    end
                6'b000001:
                    begin
                        S = 3'b000;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b000111:
                    begin
                        S = 3'b110;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b000100:
                    begin
                        S = 3'b100;
                        Cin = 0;
                        imm = 1'b0;
                    end
                6'b110110:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                        set = 1'b1;
                        setType = 2'b00;
                    end
                6'b110111:
                    begin
                        S = 3'b011;
                        Cin = 1;
                        imm = 1'b0;
                        set = 1'b1;
                        setType = 2'b10;
                    end
                endcase
                
            end
            6'b000011:
                begin
                    S = 3'b010; 
                    Cin = 0; 
                    imm = 1'b1;
                end
            6'b000010:
                begin
                    S = 3'b011;
                    Cin = 1;
                    imm = 1'b1;
                end
            6'b000001:
                begin
                    S = 3'b000;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b001111:
                begin
                    S = 3'b110;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b001100:
                begin
                    S = 3'b100;
                    Cin = 0;
                    imm = 1'b1;
                end
            6'b011110:
                begin
                    S = 3'b010;
                    Cin = 0;
                    imm = 1'b1;
                    load = 1'b1;
                end
            6'b011111:
                begin
                    S = 3'b010;
                    Cin = 0;
                    imm = 1'b1;
                    store = 1'b1;
                end
            6'b110000:
                begin
                    store = 1'b1;
                    eq = 1'b1;
                    eqType = 1'b0;
                end
            6'b110001:
                begin
                    store = 1'b1;
                    eq = 1'b1;
                    eqType = 1'b1;
                end
        endcase
    end
endmodule