data/full_repos/permissive/517427004/CA4 - Multi-Cycle/Verilog/MCProcessorTB.v
1: b'%Error: Invalid Option: -\n'
module MCProcessorTB ();
    reg clk = 1'b0, rst = 1'b0;

    MCProcessor processor(clk, rst);

    always #5 clk = ~clk;

    initial begin
        #1 rst = 1'b1;
        #3 rst = 1'b0;
        #7000 $finish;
    end
endmodule
module MCProcessorTB ();

    reg clk = 1'b0, rst = 1'b0;

    MCProcessor processor(clk, rst);

    always #5 clk = ~clk;

    initial begin
        #1 rst = 1'b1;
        #3 rst = 1'b0;
        #7000 $finish;
    end
endmodule