data/full_repos/permissive/451961217/morse_decoder.v
data/verilator_xmls/3f3bffb6-24f8-4fb7-b4d4-ceb50a066a63.xml
module shift_reg(clock, reset_n, ParallelLoadn, Enable, Data_IN, Q);
	input clock;
	input reset_n;
	input ParallelLoadn;
	input [11:0]Data_IN;
	input Enable;
	output reg Q;
	reg [11:0]bits;
	always@(posedge clock or negedge reset_n)
		if (reset_n==1'b0)
		begin
			bits <= 12'b000000000000;
			Q<=1'b0;
		end
		else if (ParallelLoadn==1'b1)
		begin
			bits<=Data_IN;
			Q<=1'b1;
		end
		else if (Enable==1'b1)
		begin
			Q<=bits[11];
			bits <= {bits[10:0],bits[11]};
		end
endmodule
module shift_reg(clock, reset_n, ParallelLoadn, Enable, Data_IN, Q);

	input clock;
	input reset_n;
	input ParallelLoadn;
	input [11:0]Data_IN;
	input Enable;
	output reg Q;
	reg [11:0]bits;
	always@(posedge clock or negedge reset_n)
		if (reset_n==1'b0)
		begin
			bits <= 12'b000000000000;
			Q<=1'b0;
		end
		else if (ParallelLoadn==1'b1)
		begin
			bits<=Data_IN;
			Q<=1'b1;
		end
		else if (Enable==1'b1)
		begin
			Q<=bits[11];
			bits <= {bits[10:0],bits[11]};
		end
endmodule