data/full_repos/permissive/517918128/dualport_sram_test.v
1: b'%Error: data/full_repos/permissive/517918128/dualport_sram_test.v:1: Cannot find include file: dualport_sram.v\n`include "dualport_sram.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517918128,data/full_repos/permissive/517918128/dualport_sram.v\n             data/full_repos/permissive/517918128,data/full_repos/permissive/517918128/dualport_sram.v.v\n             data/full_repos/permissive/517918128,data/full_repos/permissive/517918128/dualport_sram.v.sv\n             dualport_sram.v\n             dualport_sram.v.v\n             dualport_sram.v.sv\n             obj_dir/dualport_sram.v\n             obj_dir/dualport_sram.v.v\n             obj_dir/dualport_sram.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517918128/dualport_sram_test.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dualport_sram_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/517918128/dualport_sram_test.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dualport_sram_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100;wr=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517918128/dualport_sram_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module dualport_sram_test;

reg clk,wr,rd;
reg [31:0] din;
reg [2:0] addr;


wire [31:0] dout;


dualport_sram uut(
    .clk(clk),
    .wr(wr),
    .rd(rd),
    .din(din),
    .addr(addr),
    .dout(dout)
);
always #50 clk=~clk;
initial begin
    $dumpfile("dualport_sram_test.vcd");
    $dumpvars(0,dualport_sram_test);

    clk=1;
    wr=1;
    rd=0;
    din=32'h000000ff;
    addr=00;


    #100;wr=1;
    rd=0;
    din=32'h0011ffff;
    addr=01;

    #100;wr=1;
    rd=0;
    din=32'h0011abcd;
    addr=10;

    #100;wr=1;
    rd=0;
    din=32'h00110000;
    addr=11;

    #100;wr=0;
    rd=1;
    addr=01;

    #100;wr=0;
    rd=1;
    addr=11;

    #100;wr=0;
    rd=1;
    addr=10; 

    #100;
    $finish;

end

endmodule
module dualport_sram_test;


reg clk,wr,rd;
reg [31:0] din;
reg [2:0] addr;


wire [31:0] dout;


dualport_sram uut(
    .clk(clk),
    .wr(wr),
    .rd(rd),
    .din(din),
    .addr(addr),
    .dout(dout)
);
always #50 clk=~clk;
initial begin
    $dumpfile("dualport_sram_test.vcd");
    $dumpvars(0,dualport_sram_test);

    clk=1;
    wr=1;
    rd=0;
    din=32'h000000ff;
    addr=00;


    #100;wr=1;
    rd=0;
    din=32'h0011ffff;
    addr=01;

    #100;wr=1;
    rd=0;
    din=32'h0011abcd;
    addr=10;

    #100;wr=1;
    rd=0;
    din=32'h00110000;
    addr=11;

    #100;wr=0;
    rd=1;
    addr=01;

    #100;wr=0;
    rd=1;
    addr=11;

    #100;wr=0;
    rd=1;
    addr=10; 

    #100;
    $finish;

end

endmodule