data/full_repos/permissive/519759804/test_nodelayslot/RegTemp.v
data/verilator_xmls/e99cc167-f53d-4f59-9d3e-46e23b37d4ad.xml
module RegTemp
#(parameter SIZE = 32)
(reset, clk, choice, Data_i, Data_o);
    input reset;
    input clk;
	input [1:0] choice;
    input [SIZE-1:0] Data_i;
    output [SIZE-1:0] Data_o;
	
	(* max_fanout="68" *)reg [SIZE-1:0] Data_o;
    
    always@(posedge reset or posedge clk) begin
        if (reset) begin
            Data_o <= 0;
        end else begin
			if(choice==2'b00) begin
				Data_o <= 0;
			end
			else if(choice==2'b01) begin
				Data_o <= Data_i;
			end
			else begin
				Data_o <= Data_o;
			end
        end
    end
endmodule
module RegTemp
#(parameter SIZE = 32)
(reset, clk, choice, Data_i, Data_o);

    input reset;
    input clk;
	input [1:0] choice;
    input [SIZE-1:0] Data_i;
    output [SIZE-1:0] Data_o;
	
	(* max_fanout="68" *)reg [SIZE-1:0] Data_o;
    
    always@(posedge reset or posedge clk) begin
        if (reset) begin
            Data_o <= 0;
        end else begin
			if(choice==2'b00) begin
				Data_o <= 0;
			end
			else if(choice==2'b01) begin
				Data_o <= Data_i;
			end
			else begin
				Data_o <= Data_o;
			end
        end
    end
endmodule