data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v
1: b'%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background\n%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v\n%Error: Exiting due to 3 error(s)\n'
module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z);

    parameter integer rscid   = 1;
    parameter integer width   = 8;
    parameter         ph_clk  =  1'b1;
    parameter         ph_en   =  1'b1;
    parameter         ph_arst =  1'b1;
    parameter         ph_srst =  1'b1;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ld;
    output             vd;
    input  [width-1:0] d;
    output             lz;
    input              vz;
    output [width-1:0] z;

    wire               filled;
    wire               filled_next;
    wire   [width-1:0] abuf;
    wire               lbuf;


    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));

    assign lbuf = ld & ~(filled ^ vz);

    assign vd = vz | ~filled;

    assign lz = ld | filled;

    assign z = (filled) ? abuf : d;

    wire dummy;
    wire dummy_bufreg_lz;


    mgc_out_reg
    #(
        .rscid   (rscid),
        .width   (1'b1),
        .ph_clk  (ph_clk),
        .ph_en   (ph_en),
        .ph_arst (ph_arst),
        .ph_srst (ph_srst)
    )
    STATREG
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (filled_next),
        .d       (1'b0),
        .lz      (filled),
        .z       (dummy)
    );

    mgc_out_reg
    #(
        .rscid   (rscid),
        .width   (width),
        .ph_clk  (ph_clk),
        .ph_en   (ph_en),
        .ph_arst (ph_arst),
        .ph_srst (ph_srst)
    )
    BUFREG
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (lbuf),
        .d       (d),
        .lz      (dummy_bufreg_lz),
        .z       (abuf)
    );

endmodule
module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z);


    parameter integer rscid   = 1;
    parameter integer width   = 8;
    parameter         ph_clk  =  1'b1;
    parameter         ph_en   =  1'b1;
    parameter         ph_arst =  1'b1;
    parameter         ph_srst =  1'b1;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ld;
    output             vd;
    input  [width-1:0] d;
    output             lz;
    input              vz;
    output [width-1:0] z;

    wire               filled;
    wire               filled_next;
    wire   [width-1:0] abuf;
    wire               lbuf;


    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));

    assign lbuf = ld & ~(filled ^ vz);

    assign vd = vz | ~filled;

    assign lz = ld | filled;

    assign z = (filled) ? abuf : d;

    wire dummy;
    wire dummy_bufreg_lz;


    mgc_out_reg
    #(
        .rscid   (rscid),
        .width   (1'b1),
        .ph_clk  (ph_clk),
        .ph_en   (ph_en),
        .ph_arst (ph_arst),
        .ph_srst (ph_srst)
    )
    STATREG
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (filled_next),
        .d       (1'b0),
        .lz      (filled),
        .z       (dummy)
    );

    mgc_out_reg
    #(
        .rscid   (rscid),
        .width   (width),
        .ph_clk  (ph_clk),
        .ph_en   (ph_en),
        .ph_arst (ph_arst),
        .ph_srst (ph_srst)
    )
    BUFREG
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (lbuf),
        .d       (d),
        .lz      (dummy_bufreg_lz),
        .z       (abuf)
    );

endmodule