data/full_repos/permissive/449807379/CPU_design/alu_decoder_rotate.v
data/verilator_xmls/ceb909c7-6660-4276-8fb5-8558b684a1f1.xml
module alu_decoder_4out(op_code,out);

input [1:0] op_code;
output reg [3:0] out;





always @(*)
begin
case (op_code)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase


end
endmodule
module alu_decoder_4out(op_code,out);


input [1:0] op_code;
output reg [3:0] out;





always @(*)
begin
case (op_code)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase


end
endmodule