data/full_repos/permissive/490316079/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/490316079/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10 clk=~clk;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:8: Little bit endian vector: MSB < LSB of bit range: 0:22\nreg signed [0:WEIGHT_WIDTH+PART_NO_WIDTH-1]weight_bus;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:9: Little bit endian vector: MSB < LSB of bit range: 0:3\nwire [0:3]max;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:13: Little bit endian vector: MSB < LSB of bit range: 0:64\nreg [0:64]count;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:14: Little bit endian vector: MSB < LSB of bit range: 0:64\nreg [0:64]count2;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:16: Little bit endian vector: MSB < LSB of bit range: 0:22\nreg [0:WEIGHT_WIDTH+PART_NO_WIDTH-1] weight_bus_memory[0:Depth-1];\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/490316079/testbench.v:18: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg [0:1]state;\n    ^\n%Error: data/full_repos/permissive/490316079/testbench.v:21: Cannot find file containing module: \'control_FNN\'\ncontrol_FNN DUT(start_FNN ,restart, clk,weight_bus, load_weights ,weight_valid, ready_in ,input_image,max, finish_FNN,FNN_ready,FNN_ready_to_accept );\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490316079,data/full_repos/permissive/490316079/control_FNN\n             data/full_repos/permissive/490316079,data/full_repos/permissive/490316079/control_FNN.v\n             data/full_repos/permissive/490316079,data/full_repos/permissive/490316079/control_FNN.sv\n             control_FNN\n             control_FNN.v\n             control_FNN.sv\n             obj_dir/control_FNN\n             obj_dir/control_FNN.v\n             obj_dir/control_FNN.sv\n%Warning-WIDTH: data/full_repos/permissive/490316079/testbench.v:78: Bit extraction of array[32029:0] requires 15 bit index, not 65 bits.\n                                                                   : ... In instance testbench\n    weight_bus=weight_bus_memory[count2];\n                                ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
parameter WEIGHT_WIDTH=16, PART_NO_WIDTH=7, NN1=40, NN2=10, NN3=10, NN4=10, NO_OF_INPUTS=784, INDATA_WIDTH=16;
parameter Depth=NO_OF_INPUTS*NN1+NN1+NN1*NN2+NN2 +NN2*NN3+NN3+NN3* NN4+NN4;
parameter S0=0, S1=1,S2=2,S3=3;
reg start_FNN, restart, clk, load_weights, ready_in,weight_valid;
reg signed [0:WEIGHT_WIDTH+PART_NO_WIDTH-1]weight_bus;
wire [0:3]max;
wire finish_FNN,FNN_ready;
reg x,y;
integer i=0;
reg [0:64]count;
reg [0:64]count2;
reg [INDATA_WIDTH-1:0]input_image;
reg [0:WEIGHT_WIDTH+PART_NO_WIDTH-1] weight_bus_memory[0:Depth-1];
reg [INDATA_WIDTH-1:0]indata_mem[0:NO_OF_INPUTS-1];
reg [0:1]state;
reg loaded_in_memory;
wire FNN_ready_to_accept;
control_FNN DUT(start_FNN ,restart, clk,weight_bus, load_weights ,weight_valid, ready_in ,input_image,max, finish_FNN,FNN_ready,FNN_ready_to_accept );
initial
begin
clk=0;
count=0;
count2=0;
end


always 
#10 clk=~clk;

 initial
 begin
	 $readmemb("weights_and_biases.mif", weight_bus_memory);
	 $readmemb("input_data_2.mif", indata_mem);
	 loaded_in_memory=1;
 end
	    
always @(negedge clk)
begin
case(state)
S0: begin
    if(loaded_in_memory && x==0)
    state<=S1;
    end
S1: begin
    if(FNN_ready )
    state<=S2;
    end
S2: begin
    if(y==0 && i==NO_OF_INPUTS)
    state<=S3;
    end
S3: begin
    if(finish_FNN && y==1)
    state<=S2;
    end
default state<=S0;
endcase
end

always @(negedge clk)
begin
case(state)
S0: begin
    restart=0;
    x=0;
    end
S1: begin
    if(count==3)
    load_weights=1;
    if(x==0)
    begin
    if(count>3)
    begin
    weight_valid=1;
    weight_bus=weight_bus_memory[count2];
    count2=count2+1;
    end
    count=count+1;
    end
    end
    
S2: begin
    start_FNN=1;
    x=1;
    weight_valid=0;
    load_weights=0;
    y=0;
    ready_in=1;
    
    if(FNN_ready_to_accept)
    begin
    if(i<NO_OF_INPUTS)
    begin
    input_image=indata_mem[i] ;
    i=i+1;
    end
    end
    end
S3: begin
    restart=1;
    y=1;
    i=0;
    end
endcase
end
endmodule
module testbench();

parameter WEIGHT_WIDTH=16, PART_NO_WIDTH=7, NN1=40, NN2=10, NN3=10, NN4=10, NO_OF_INPUTS=784, INDATA_WIDTH=16;
parameter Depth=NO_OF_INPUTS*NN1+NN1+NN1*NN2+NN2 +NN2*NN3+NN3+NN3* NN4+NN4;
parameter S0=0, S1=1,S2=2,S3=3;
reg start_FNN, restart, clk, load_weights, ready_in,weight_valid;
reg signed [0:WEIGHT_WIDTH+PART_NO_WIDTH-1]weight_bus;
wire [0:3]max;
wire finish_FNN,FNN_ready;
reg x,y;
integer i=0;
reg [0:64]count;
reg [0:64]count2;
reg [INDATA_WIDTH-1:0]input_image;
reg [0:WEIGHT_WIDTH+PART_NO_WIDTH-1] weight_bus_memory[0:Depth-1];
reg [INDATA_WIDTH-1:0]indata_mem[0:NO_OF_INPUTS-1];
reg [0:1]state;
reg loaded_in_memory;
wire FNN_ready_to_accept;
control_FNN DUT(start_FNN ,restart, clk,weight_bus, load_weights ,weight_valid, ready_in ,input_image,max, finish_FNN,FNN_ready,FNN_ready_to_accept );
initial
begin
clk=0;
count=0;
count2=0;
end


always 
#10 clk=~clk;

 initial
 begin
	 $readmemb("weights_and_biases.mif", weight_bus_memory);
	 $readmemb("input_data_2.mif", indata_mem);
	 loaded_in_memory=1;
 end
	    
always @(negedge clk)
begin
case(state)
S0: begin
    if(loaded_in_memory && x==0)
    state<=S1;
    end
S1: begin
    if(FNN_ready )
    state<=S2;
    end
S2: begin
    if(y==0 && i==NO_OF_INPUTS)
    state<=S3;
    end
S3: begin
    if(finish_FNN && y==1)
    state<=S2;
    end
default state<=S0;
endcase
end

always @(negedge clk)
begin
case(state)
S0: begin
    restart=0;
    x=0;
    end
S1: begin
    if(count==3)
    load_weights=1;
    if(x==0)
    begin
    if(count>3)
    begin
    weight_valid=1;
    weight_bus=weight_bus_memory[count2];
    count2=count2+1;
    end
    count=count+1;
    end
    end
    
S2: begin
    start_FNN=1;
    x=1;
    weight_valid=0;
    load_weights=0;
    y=0;
    ready_in=1;
    
    if(FNN_ready_to_accept)
    begin
    if(i<NO_OF_INPUTS)
    begin
    input_image=indata_mem[i] ;
    i=i+1;
    end
    end
    end
S3: begin
    restart=1;
    y=1;
    i=0;
    end
endcase
end
endmodule