data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v
1: b"%Error: data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v:45: Cannot find file containing module: 'el_adder'\nel_adder #\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_adder\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_adder.v\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_adder.sv\n             el_adder\n             el_adder.v\n             el_adder.sv\n             obj_dir/el_adder\n             obj_dir/el_adder.v\n             obj_dir/el_adder.sv\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v:76: Cannot find file containing module: 'el_link'\nel_link#\n^~~~~~~\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v:92: Cannot find file containing module: 'el_link'\nel_link#\n^~~~~~~\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v:110: Cannot find file containing module: 'c_elem'\nc_elem#\n^~~~~~\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_adder_linked.v:122: Cannot find file containing module: 'c_elem'\nc_elem#\n^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module el_adder_linked#(
	parameter						WIDTH = 32,
	
	parameter						RAIL_NUM = 2,
	parameter						IN_NUM = 3,
	parameter						OUT_NUM = 2
)
(

	input							rst,

	output							ack_a_o,
	input	[RAIL_NUM*WIDTH-1 : 0]	in_a,

	output							ack_b_o,
	input	[RAIL_NUM*WIDTH-1 : 0]	in_b,

	output							ack_c_o,
	input	[RAIL_NUM-1 : 0]		in_c,

	output	[RAIL_NUM*WIDTH-1 : 0]	out_s,

	output	[RAIL_NUM-1 : 0]		out_c,

	input							ack_i
);


wire [WIDTH : 0] ack_i_link;
assign ack_i_link = {(WIDTH + 1){ack_i}};

wire [WIDTH-1 : 0] ack_add_s;
assign ack_add_s = {WIDTH{ack_add}};

wire ack_add;

wire [WIDTH-1 : 0] ack_a;
wire [WIDTH-1 : 0] ack_b;

wire [RAIL_NUM*WIDTH-1 : 0] out_s_add;
wire [RAIL_NUM-1 : 0] out_c_add;

el_adder #
(
	.WIDTH(WIDTH)
)
adder
(

	.rst(rst),

	.ack_a_o(ack_a),
	.in_a(in_a),

	.ack_b_o(ack_b),
	.in_b(in_b),

	.ack_c_o(ack_c_o),
	.in_c(in_c),

	.ack_s_i(ack_add_s),
	.out_s(out_s_add),

	.ack_c_i(ack_add),
	.out_c(out_c_add)

);


wire ack_l;
wire [RAIL_NUM*(WIDTH + 1)-1 : 0] dat_l;


el_link#
(
	.LINK_WIDTH(WIDTH + 1),
	.RAIL_NUM(RAIL_NUM)
)
link_1
(
	.rst(rst),
	
	.ack_o(ack_add),
	.in({out_c_add,out_s_add}),
	
	.ack_i(ack_l),
	.out(dat_l)
);

el_link#
(
	.LINK_WIDTH(WIDTH + 1),
	.RAIL_NUM(RAIL_NUM)
)
link_2
(
	.rst(rst),
	
	.ack_o(ack_l),
	.in(dat_l),
	
	.ack_i(ack_i),
	.out({out_c,out_s})
);



c_elem#
(
	.IN_NUM(WIDTH)
)
c_join_a
(
	.rst(rst),
	
	.in(ack_a),
	.out(ack_a_o)
);

c_elem#
(
	.IN_NUM(WIDTH)
)
c_join_b
(
	.rst(rst),
	
	.in(ack_b),
	.out(ack_b_o)
);



endmodule
module el_adder_linked#(
	parameter						WIDTH = 32,
	
	parameter						RAIL_NUM = 2,
	parameter						IN_NUM = 3,
	parameter						OUT_NUM = 2
)
(

	input							rst,

	output							ack_a_o,
	input	[RAIL_NUM*WIDTH-1 : 0]	in_a,

	output							ack_b_o,
	input	[RAIL_NUM*WIDTH-1 : 0]	in_b,

	output							ack_c_o,
	input	[RAIL_NUM-1 : 0]		in_c,

	output	[RAIL_NUM*WIDTH-1 : 0]	out_s,

	output	[RAIL_NUM-1 : 0]		out_c,

	input							ack_i
);



wire [WIDTH : 0] ack_i_link;
assign ack_i_link = {(WIDTH + 1){ack_i}};

wire [WIDTH-1 : 0] ack_add_s;
assign ack_add_s = {WIDTH{ack_add}};

wire ack_add;

wire [WIDTH-1 : 0] ack_a;
wire [WIDTH-1 : 0] ack_b;

wire [RAIL_NUM*WIDTH-1 : 0] out_s_add;
wire [RAIL_NUM-1 : 0] out_c_add;

el_adder #
(
	.WIDTH(WIDTH)
)
adder
(

	.rst(rst),

	.ack_a_o(ack_a),
	.in_a(in_a),

	.ack_b_o(ack_b),
	.in_b(in_b),

	.ack_c_o(ack_c_o),
	.in_c(in_c),

	.ack_s_i(ack_add_s),
	.out_s(out_s_add),

	.ack_c_i(ack_add),
	.out_c(out_c_add)

);


wire ack_l;
wire [RAIL_NUM*(WIDTH + 1)-1 : 0] dat_l;


el_link#
(
	.LINK_WIDTH(WIDTH + 1),
	.RAIL_NUM(RAIL_NUM)
)
link_1
(
	.rst(rst),
	
	.ack_o(ack_add),
	.in({out_c_add,out_s_add}),
	
	.ack_i(ack_l),
	.out(dat_l)
);

el_link#
(
	.LINK_WIDTH(WIDTH + 1),
	.RAIL_NUM(RAIL_NUM)
)
link_2
(
	.rst(rst),
	
	.ack_o(ack_l),
	.in(dat_l),
	
	.ack_i(ack_i),
	.out({out_c,out_s})
);



c_elem#
(
	.IN_NUM(WIDTH)
)
c_join_a
(
	.rst(rst),
	
	.in(ack_a),
	.out(ack_a_o)
);

c_elem#
(
	.IN_NUM(WIDTH)
)
c_join_b
(
	.rst(rst),
	
	.in(ack_b),
	.out(ack_b_o)
);



endmodule