data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v:49: Little bit endian vector: MSB < LSB of bit range: 0:31\n   parameter [0:in_width-1] mask = {in_width{1\'b1}};\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n   function automatic integer pop_count(input [0:in_width-1] argument);\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v:44: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance c_gather\n    pop_count = pop_count + argument[i];\n                          ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v:55: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:in_width-1] data_in;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_gather.v:58: Little bit endian vector: MSB < LSB of bit range: 0:31\n   output [0:out_width-1] data_out;\n          ^\n%Error: Exiting due to 5 warning(s)\n'
function automatic integer pop_count(input [0:in_width-1] argument);
      integer i;
      begin
	 pop_count = 0;
	 for(i = 0; i < in_width; i = i + 1)
	   pop_count = pop_count + argument[i];
      end
   endfunction
function automatic integer pop_count(input [0:in_width-1] argument);

      integer i;
      begin
	 pop_count = 0;
	 for(i = 0; i < in_width; i = i + 1)
	   pop_count = pop_count + argument[i];
      end
   endfunction