data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:141: Cannot find file containing module: 'MEM4X1'\n    MEM4X1 _TECHMAP_REPLACE_ (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1.v\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1.sv\n             MEM4X1\n             MEM4X1.v\n             MEM4X1.sv\n             obj_dir/MEM4X1\n             obj_dir/MEM4X1.v\n             obj_dir/MEM4X1.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:66: Unsupported: MSB < LSB of bit extract: -1<0\n                                                                                            : ... In instance __024mem\n   if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=\n                              ^\n%Error: Internal Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:67: ../V3Width.cpp:3809: Under node SEL has no expected width?? Missing Visitor func?\n                                                                                                            : ... In instance __024mem\n     _TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])\n                            ^\n"
module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
	parameter ABITS = 4;
	parameter SIZE = 16;

	input CLK, WR_DATA, WR_EN;
	input [ABITS-1:0] RD_ADDR, WR_ADDR;
	output RD_DATA;

	wire [1023:0] _TECHMAP_DO_ = "proc; clean";

	generate
	  if (ABITS > 4) begin
	  	wire high_rd_data, low_rd_data;
	  	if (SIZE > 2**(ABITS-1)) begin
			\$__mem_4x1_generator #(
				.ABITS(ABITS-1),
				.SIZE(SIZE - 2**(ABITS-1))
			) part_high (
				.CLK(CLK),
				.RD_ADDR(RD_ADDR[ABITS-2:0]),
				.RD_DATA(high_rd_data),
				.WR_ADDR(WR_ADDR[ABITS-2:0]),
				.WR_DATA(WR_DATA),
				.WR_EN(WR_EN && WR_ADDR[ABITS-1])
			);
		end else begin
			assign high_rd_data = 1'bx;
		end
		\$__mem_4x1_generator #(
			.ABITS(ABITS-1),
			.SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE)
		) part_low (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR[ABITS-2:0]),
			.RD_DATA(low_rd_data),
			.WR_ADDR(WR_ADDR[ABITS-2:0]),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN && !WR_ADDR[ABITS-1])
		);
		reg delayed_abit;
		always @(posedge CLK)
			delayed_abit <= RD_ADDR[ABITS-1];
		assign RD_DATA = delayed_abit ? high_rd_data : low_rd_data;
	  end else begin
	  	MEM4X1 _TECHMAP_REPLACE_ (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR),
			.RD_DATA(RD_DATA),
			.WR_ADDR(WR_ADDR),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN)
		);
	  end
	endgenerate
endmodule
module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);

	parameter ABITS = 4;
	parameter SIZE = 16;

	input CLK, WR_DATA, WR_EN;
	input [ABITS-1:0] RD_ADDR, WR_ADDR;
	output RD_DATA;

	wire [1023:0] _TECHMAP_DO_ = "proc; clean";

	generate
	  if (ABITS > 4) begin
	  	wire high_rd_data, low_rd_data;
	  	if (SIZE > 2**(ABITS-1)) begin
			\$__mem_4x1_generator #(
				.ABITS(ABITS-1),
				.SIZE(SIZE - 2**(ABITS-1))
			) part_high (
				.CLK(CLK),
				.RD_ADDR(RD_ADDR[ABITS-2:0]),
				.RD_DATA(high_rd_data),
				.WR_ADDR(WR_ADDR[ABITS-2:0]),
				.WR_DATA(WR_DATA),
				.WR_EN(WR_EN && WR_ADDR[ABITS-1])
			);
		end else begin
			assign high_rd_data = 1'bx;
		end
		\$__mem_4x1_generator #(
			.ABITS(ABITS-1),
			.SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE)
		) part_low (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR[ABITS-2:0]),
			.RD_DATA(low_rd_data),
			.WR_ADDR(WR_ADDR[ABITS-2:0]),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN && !WR_ADDR[ABITS-1])
		);
		reg delayed_abit;
		always @(posedge CLK)
			delayed_abit <= RD_ADDR[ABITS-1];
		assign RD_DATA = delayed_abit ? high_rd_data : low_rd_data;
	  end else begin
	  	MEM4X1 _TECHMAP_REPLACE_ (
			.CLK(CLK),
			.RD_ADDR(RD_ADDR),
			.RD_DATA(RD_DATA),
			.WR_ADDR(WR_ADDR),
			.WR_DATA(WR_DATA),
			.WR_EN(WR_EN)
		);
	  end
	endgenerate
endmodule