data/full_repos/permissive/441359809/src/yosys/tests/arch/common/counter.v
data/verilator_xmls/a8a4aed9-e224-4c82-8322-ae5e8c54e7df.xml
module top ( out, clk, reset );
    output [7:0] out;
    input clk, reset;
    reg [7:0] out;

    always @(posedge clk, posedge reset)
      if (reset)
          out <= 8'b0;
      else
          out <= out + 1;
endmodule
module top ( out, clk, reset );

    output [7:0] out;
    input clk, reset;
    reg [7:0] out;

    always @(posedge clk, posedge reset)
      if (reset)
          out <= 8'b0;
      else
          out <= out + 1;
endmodule