data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Conditional/top_module_tb.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Conditional,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Conditional/top_module_tb.v\n%Error: Exiting due to 4 error(s)\n'
module top_module_tb ();

  wire [7:0] min;

  reg [7:0] a = 8'd0;
  reg [7:0] b = 8'd0;
  reg [7:0] c = 8'd0;
  reg [7:0] d = 8'd0;

  localparam ITERATIONS = 60;

  always begin
    #1 a = $random;
    b = $random;
    c = $random;
    d = $random;
  end

  top_module uut (
      .a(a),
      .b(b),
      .c(c),
      .d(d),
      .min(min)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  wire [7:0] min;

  reg [7:0] a = 8'd0;
  reg [7:0] b = 8'd0;
  reg [7:0] c = 8'd0;
  reg [7:0] d = 8'd0;

  localparam ITERATIONS = 60;

  always begin
    #1 a = $random;
    b = $random;
    c = $random;
    d = $random;
  end

  top_module uut (
      .a(a),
      .b(b),
      .c(c),
      .d(d),
      .min(min)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule