data/full_repos/permissive/524509242/BCD Counter/prog_counter1.v
1: b'%Error: Cannot find file containing module: Counter,data/full_repos/permissive/524509242\n        ... Looked in:\n             data/full_repos/permissive/524509242/BCD/Counter,data/full_repos/permissive/524509242\n             data/full_repos/permissive/524509242/BCD/Counter,data/full_repos/permissive/524509242.v\n             data/full_repos/permissive/524509242/BCD/Counter,data/full_repos/permissive/524509242.sv\n             Counter,data/full_repos/permissive/524509242\n             Counter,data/full_repos/permissive/524509242.v\n             Counter,data/full_repos/permissive/524509242.sv\n             obj_dir/Counter,data/full_repos/permissive/524509242\n             obj_dir/Counter,data/full_repos/permissive/524509242.v\n             obj_dir/Counter,data/full_repos/permissive/524509242.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/524509242/BCD\n%Error: Cannot find file containing module: Counter/prog_counter1.v\n%Error: Exiting due to 3 error(s)\n'
module prog_count_7(max_count, run, CLK, count_out);

input [6:0] max_count;
input run, CLK;
output [6:0] count_out;

reg clk;





count_7 counter_1(.run(run),
		  .CLK(clk),
		  .count_out(count_out));

	
   
	always @ ( CLK or max_count or run or count_out) begin
		if(run==0)begin 
			clk=CLK;
			
		end 
		else begin
			if (count_out==max_count ||  count_out==99 ) begin
				clk=0;
			end
			else if (count_out>max_count ) begin
				clk=0;
			end
			else begin 
				clk=CLK;
			end 
		end
	end
	

endmodule
module prog_count_7(max_count, run, CLK, count_out);


input [6:0] max_count;
input run, CLK;
output [6:0] count_out;

reg clk;





count_7 counter_1(.run(run),
		  .CLK(clk),
		  .count_out(count_out));

	
   
	always @ ( CLK or max_count or run or count_out) begin
		if(run==0)begin 
			clk=CLK;
			
		end 
		else begin
			if (count_out==max_count ||  count_out==99 ) begin
				clk=0;
			end
			else if (count_out>max_count ) begin
				clk=0;
			end
			else begin 
				clk=CLK;
			end 
		end
	end
	

endmodule