data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/axi_master.v
1: b"%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/axi_master.v:223: Cannot find file containing module: 'axi_master_wr'\n   axi_master_wr axi_master_wr( \n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/axi_master_wr\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/axi_master_wr.v\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/axi_master_wr.sv\n             axi_master_wr\n             axi_master_wr.v\n             axi_master_wr.sv\n             obj_dir/axi_master_wr\n             obj_dir/axi_master_wr.v\n             obj_dir/axi_master_wr.sv\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/axi_master.v:262: Cannot find file containing module: 'axi_master_rd'\n   axi_master_rd axi_master_rd( \n   ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module axi_master (

   awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
   awvalid, wid, wdata, wstrb, wlast, wvalid, bready, arid, araddr,
   arlen, arsize, arburst, arlock, arcache, arprot, arvalid, rready,
   emesh_access_inb, emesh_write_inb, emesh_datamode_inb,
   emesh_ctrlmode_inb, emesh_dstaddr_inb, emesh_srcaddr_inb,
   emesh_data_inb, emesh_wr_wait_inb, emesh_rd_wait_inb, awqos, arqos,

   aclk, eclk, reset, awready, wready, bid, bresp, bvalid, arready,
   rid, rdata, rresp, rlast, rvalid, emesh_access_outb,
   emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
   emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
   emesh_wr_wait_outb
   );

   parameter MIDW = 6;
   parameter MAW  = 32;
   parameter MDW  = 64;
   parameter STW = 8;
      





   input aclk;
   input eclk;
   input reset;




   input            awready;
   



   input 	    wready;




   input [MIDW-1:0]  bid;
   input [1:0] 	    bresp;
   input 	    bvalid;
      



   input 	    arready;
   



   input [MIDW-1:0]  rid;
   input [MDW-1:0]   rdata;
   input [1:0] 	    rresp;
   input 	    rlast;
   input 	    rvalid;




   input 	    emesh_access_outb;
   input 	    emesh_write_outb;
   input [1:0] 	    emesh_datamode_outb;
   input [3:0] 	    emesh_ctrlmode_outb;
   input [31:0]     emesh_dstaddr_outb;
   input [31:0]     emesh_srcaddr_outb;
   input [31:0]     emesh_data_outb;   
   input 	    emesh_wr_wait_outb; 
      







   output [MIDW-1:0] awid;
   output [MAW-1:0]  awaddr;
   output [3:0]     awlen;
   output [2:0]     awsize;
   output [1:0]     awburst;
   output [1:0]     awlock;
   output [3:0]     awcache;
   output [2:0]     awprot;
   output 	    awvalid;
      



   output [MIDW-1:0] wid;
   output [MDW-1:0]  wdata;
   output [STW-1:0] wstrb;
   output 	    wlast;
   output 	    wvalid;
   



   output 	    bready;
   



   output [MIDW-1:0] arid;
   output [MAW-1:0]  araddr;
   output [3:0]     arlen;
   output [2:0]     arsize;
   output [1:0]     arburst;
   output [1:0]     arlock;
   output [3:0]     arcache;
   output [2:0]     arprot;
   output 	    arvalid;
      



   output 	    rready;




   output 	    emesh_access_inb;
   output 	    emesh_write_inb;
   output [1:0]     emesh_datamode_inb;
   output [3:0]     emesh_ctrlmode_inb;
   output [31:0]    emesh_dstaddr_inb;
   output [31:0]    emesh_srcaddr_inb;
   output [31:0]    emesh_data_inb;  
   output 	    emesh_wr_wait_inb;  
   output 	    emesh_rd_wait_inb; 
   






   output [3:0]     awqos;



   output [3:0]     arqos;









   wire [MIDW-1:0]  awid;
   wire [MAW-1:0]   awaddr;
   wire [3:0] 	    awlen;
   wire [2:0] 	    awsize;
   wire [1:0] 	    awburst;
   wire [1:0] 	    awlock;
   wire [3:0] 	    awcache;
   wire [2:0] 	    awprot;
   wire 	    awvalid;
   wire [MIDW-1:0]  wid;
   wire [MDW-1:0]   wdata;
   wire [STW-1:0]   wstrb;
   wire 	    wlast;
   wire 	    wvalid;
   wire 	    bready;
   wire [MIDW-1:0]  arid;
   wire [MAW-1:0]   araddr;
   wire [3:0] 	    arlen;
   wire [2:0] 	    arsize;
   wire [1:0] 	    arburst;
   wire [1:0] 	    arlock;
   wire [3:0] 	    arcache;
   wire [2:0] 	    arprot;
   wire 	    arvalid;
   wire 	    rready;
   wire 	    emesh_access_inb;
   wire 	    emesh_write_inb;
   wire [1:0] 	    emesh_datamode_inb;
   wire [3:0] 	    emesh_ctrlmode_inb;
   wire [31:0] 	    emesh_dstaddr_inb;
   wire [31:0] 	    emesh_srcaddr_inb;
   wire [31:0] 	    emesh_data_inb;  
   wire 	    emesh_wr_wait_inb;  
   wire 	    emesh_rd_wait_inb; 
   



   assign awqos[3:0] = 4'b0000;
   assign arqos[3:0] = 4'b0000;
   



   
   axi_master_wr axi_master_wr(

			       .awid		(awid[MIDW-1:0]),
			       .awaddr		(awaddr[MAW-1:0]),
			       .awlen		(awlen[3:0]),
			       .awsize		(awsize[2:0]),
			       .awburst		(awburst[1:0]),
			       .awlock		(awlock[1:0]),
			       .awcache		(awcache[3:0]),
			       .awprot		(awprot[2:0]),
			       .awvalid		(awvalid),
			       .wid		(wid[MIDW-1:0]),
			       .wdata		(wdata[MDW-1:0]),
			       .wstrb		(wstrb[STW-1:0]),
			       .wlast		(wlast),
			       .wvalid		(wvalid),
			       .bready		(bready),
			       .emesh_wr_wait_inb(emesh_wr_wait_inb),

			       .aclk		(aclk),
			       .eclk		(eclk),
			       .reset		(reset),
			       .awready		(awready),
			       .wready		(wready),
			       .bid		(bid[MIDW-1:0]),
			       .bresp		(bresp[1:0]),
			       .bvalid		(bvalid),
			       .emesh_access_outb(emesh_access_outb),
			       .emesh_write_outb(emesh_write_outb),
			       .emesh_datamode_outb(emesh_datamode_outb[1:0]),
			       .emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
			       .emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
			       .emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
			       .emesh_data_outb	(emesh_data_outb[31:0]));
   



   
   axi_master_rd axi_master_rd(

			       .arid		(arid[MIDW-1:0]),
			       .araddr		(araddr[MAW-1:0]),
			       .arlen		(arlen[3:0]),
			       .arsize		(arsize[2:0]),
			       .arburst		(arburst[1:0]),
			       .arlock		(arlock[1:0]),
			       .arcache		(arcache[3:0]),
			       .arprot		(arprot[2:0]),
			       .arvalid		(arvalid),
			       .rready		(rready),
			       .emesh_access_inb(emesh_access_inb),
			       .emesh_write_inb	(emesh_write_inb),
			       .emesh_datamode_inb(emesh_datamode_inb[1:0]),
			       .emesh_ctrlmode_inb(emesh_ctrlmode_inb[3:0]),
			       .emesh_dstaddr_inb(emesh_dstaddr_inb[31:0]),
			       .emesh_srcaddr_inb(emesh_srcaddr_inb[31:0]),
			       .emesh_data_inb	(emesh_data_inb[31:0]),
			       .emesh_rd_wait_inb(emesh_rd_wait_inb),

			       .aclk		(aclk),
			       .eclk		(eclk),
			       .reset		(reset),
			       .arready		(arready),
			       .rid		(rid[MIDW-1:0]),
			       .rdata		(rdata[MDW-1:0]),
			       .rresp		(rresp[1:0]),
			       .rlast		(rlast),
			       .rvalid		(rvalid),
			       .emesh_access_outb(emesh_access_outb),
			       .emesh_write_outb(emesh_write_outb),
			       .emesh_datamode_outb(emesh_datamode_outb[1:0]),
			       .emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
			       .emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
			       .emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
			       .emesh_data_outb	(emesh_data_outb[31:0]),
			       .emesh_wr_wait_outb(emesh_wr_wait_outb));
   

endmodule
module axi_master (

   awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
   awvalid, wid, wdata, wstrb, wlast, wvalid, bready, arid, araddr,
   arlen, arsize, arburst, arlock, arcache, arprot, arvalid, rready,
   emesh_access_inb, emesh_write_inb, emesh_datamode_inb,
   emesh_ctrlmode_inb, emesh_dstaddr_inb, emesh_srcaddr_inb,
   emesh_data_inb, emesh_wr_wait_inb, emesh_rd_wait_inb, awqos, arqos,

   aclk, eclk, reset, awready, wready, bid, bresp, bvalid, arready,
   rid, rdata, rresp, rlast, rvalid, emesh_access_outb,
   emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
   emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
   emesh_wr_wait_outb
   );


   parameter MIDW = 6;
   parameter MAW  = 32;
   parameter MDW  = 64;
   parameter STW = 8;
      





   input aclk;
   input eclk;
   input reset;




   input            awready;
   



   input 	    wready;




   input [MIDW-1:0]  bid;
   input [1:0] 	    bresp;
   input 	    bvalid;
      



   input 	    arready;
   



   input [MIDW-1:0]  rid;
   input [MDW-1:0]   rdata;
   input [1:0] 	    rresp;
   input 	    rlast;
   input 	    rvalid;




   input 	    emesh_access_outb;
   input 	    emesh_write_outb;
   input [1:0] 	    emesh_datamode_outb;
   input [3:0] 	    emesh_ctrlmode_outb;
   input [31:0]     emesh_dstaddr_outb;
   input [31:0]     emesh_srcaddr_outb;
   input [31:0]     emesh_data_outb;   
   input 	    emesh_wr_wait_outb; 
      







   output [MIDW-1:0] awid;
   output [MAW-1:0]  awaddr;
   output [3:0]     awlen;
   output [2:0]     awsize;
   output [1:0]     awburst;
   output [1:0]     awlock;
   output [3:0]     awcache;
   output [2:0]     awprot;
   output 	    awvalid;
      



   output [MIDW-1:0] wid;
   output [MDW-1:0]  wdata;
   output [STW-1:0] wstrb;
   output 	    wlast;
   output 	    wvalid;
   



   output 	    bready;
   



   output [MIDW-1:0] arid;
   output [MAW-1:0]  araddr;
   output [3:0]     arlen;
   output [2:0]     arsize;
   output [1:0]     arburst;
   output [1:0]     arlock;
   output [3:0]     arcache;
   output [2:0]     arprot;
   output 	    arvalid;
      



   output 	    rready;




   output 	    emesh_access_inb;
   output 	    emesh_write_inb;
   output [1:0]     emesh_datamode_inb;
   output [3:0]     emesh_ctrlmode_inb;
   output [31:0]    emesh_dstaddr_inb;
   output [31:0]    emesh_srcaddr_inb;
   output [31:0]    emesh_data_inb;  
   output 	    emesh_wr_wait_inb;  
   output 	    emesh_rd_wait_inb; 
   






   output [3:0]     awqos;



   output [3:0]     arqos;









   wire [MIDW-1:0]  awid;
   wire [MAW-1:0]   awaddr;
   wire [3:0] 	    awlen;
   wire [2:0] 	    awsize;
   wire [1:0] 	    awburst;
   wire [1:0] 	    awlock;
   wire [3:0] 	    awcache;
   wire [2:0] 	    awprot;
   wire 	    awvalid;
   wire [MIDW-1:0]  wid;
   wire [MDW-1:0]   wdata;
   wire [STW-1:0]   wstrb;
   wire 	    wlast;
   wire 	    wvalid;
   wire 	    bready;
   wire [MIDW-1:0]  arid;
   wire [MAW-1:0]   araddr;
   wire [3:0] 	    arlen;
   wire [2:0] 	    arsize;
   wire [1:0] 	    arburst;
   wire [1:0] 	    arlock;
   wire [3:0] 	    arcache;
   wire [2:0] 	    arprot;
   wire 	    arvalid;
   wire 	    rready;
   wire 	    emesh_access_inb;
   wire 	    emesh_write_inb;
   wire [1:0] 	    emesh_datamode_inb;
   wire [3:0] 	    emesh_ctrlmode_inb;
   wire [31:0] 	    emesh_dstaddr_inb;
   wire [31:0] 	    emesh_srcaddr_inb;
   wire [31:0] 	    emesh_data_inb;  
   wire 	    emesh_wr_wait_inb;  
   wire 	    emesh_rd_wait_inb; 
   



   assign awqos[3:0] = 4'b0000;
   assign arqos[3:0] = 4'b0000;
   



   
   axi_master_wr axi_master_wr(

			       .awid		(awid[MIDW-1:0]),
			       .awaddr		(awaddr[MAW-1:0]),
			       .awlen		(awlen[3:0]),
			       .awsize		(awsize[2:0]),
			       .awburst		(awburst[1:0]),
			       .awlock		(awlock[1:0]),
			       .awcache		(awcache[3:0]),
			       .awprot		(awprot[2:0]),
			       .awvalid		(awvalid),
			       .wid		(wid[MIDW-1:0]),
			       .wdata		(wdata[MDW-1:0]),
			       .wstrb		(wstrb[STW-1:0]),
			       .wlast		(wlast),
			       .wvalid		(wvalid),
			       .bready		(bready),
			       .emesh_wr_wait_inb(emesh_wr_wait_inb),

			       .aclk		(aclk),
			       .eclk		(eclk),
			       .reset		(reset),
			       .awready		(awready),
			       .wready		(wready),
			       .bid		(bid[MIDW-1:0]),
			       .bresp		(bresp[1:0]),
			       .bvalid		(bvalid),
			       .emesh_access_outb(emesh_access_outb),
			       .emesh_write_outb(emesh_write_outb),
			       .emesh_datamode_outb(emesh_datamode_outb[1:0]),
			       .emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
			       .emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
			       .emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
			       .emesh_data_outb	(emesh_data_outb[31:0]));
   



   
   axi_master_rd axi_master_rd(

			       .arid		(arid[MIDW-1:0]),
			       .araddr		(araddr[MAW-1:0]),
			       .arlen		(arlen[3:0]),
			       .arsize		(arsize[2:0]),
			       .arburst		(arburst[1:0]),
			       .arlock		(arlock[1:0]),
			       .arcache		(arcache[3:0]),
			       .arprot		(arprot[2:0]),
			       .arvalid		(arvalid),
			       .rready		(rready),
			       .emesh_access_inb(emesh_access_inb),
			       .emesh_write_inb	(emesh_write_inb),
			       .emesh_datamode_inb(emesh_datamode_inb[1:0]),
			       .emesh_ctrlmode_inb(emesh_ctrlmode_inb[3:0]),
			       .emesh_dstaddr_inb(emesh_dstaddr_inb[31:0]),
			       .emesh_srcaddr_inb(emesh_srcaddr_inb[31:0]),
			       .emesh_data_inb	(emesh_data_inb[31:0]),
			       .emesh_rd_wait_inb(emesh_rd_wait_inb),

			       .aclk		(aclk),
			       .eclk		(eclk),
			       .reset		(reset),
			       .arready		(arready),
			       .rid		(rid[MIDW-1:0]),
			       .rdata		(rdata[MDW-1:0]),
			       .rresp		(rresp[1:0]),
			       .rlast		(rlast),
			       .rvalid		(rvalid),
			       .emesh_access_outb(emesh_access_outb),
			       .emesh_write_outb(emesh_write_outb),
			       .emesh_datamode_outb(emesh_datamode_outb[1:0]),
			       .emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
			       .emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
			       .emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
			       .emesh_data_outb	(emesh_data_outb[31:0]),
			       .emesh_wr_wait_outb(emesh_wr_wait_outb));
   

endmodule