data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_zckgatedcap_h.v
data/verilator_xmls/27edb2a2-8d98-4b30-b3ae-88c185e3cca2.xml
module bw_zckgatedcap_h (

   ld
   );



   inout               ld;

endmodule
module bw_zckgatedcap_h (

   ld
   );




   inout               ld;

endmodule