data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/setting_reg_masked.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/setting_reg_masked.v:20: Operator NOT expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                               : ... In instance setting_reg_masked\n     out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/setting_reg_masked.v:20: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                               : ... In instance setting_reg_masked\n     out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/setting_reg_masked.v:20: Operator AND expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                               : ... In instance setting_reg_masked\n     out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );\n                                              ^\n%Error: Exiting due to 3 warning(s)\n'
module setting_reg_masked
  ( input clock, input reset, input strobe, input wire [6:0] addr,
    input wire [31:0] in, output reg [31:0] out, output reg changed);


   parameter my_addr = 0;
   
   always @(posedge clock)
     if(reset)
       begin
	  out <= #1 32'd0;
	  changed <= #1 1'b0;
       end
     else
       if(strobe & (my_addr==addr))
	 begin
	    out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
	    changed <= #1 1'b1;
	 end
       else
	 changed <= #1 1'b0;
   
endmodule
module setting_reg_masked
  ( input clock, input reset, input strobe, input wire [6:0] addr,
    input wire [31:0] in, output reg [31:0] out, output reg changed);



   parameter my_addr = 0;
   
   always @(posedge clock)
     if(reset)
       begin
	  out <= #1 32'd0;
	  changed <= #1 1'b0;
       end
     else
       if(strobe & (my_addr==addr))
	 begin
	    out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
	    changed <= #1 1'b1;
	 end
       else
	 changed <= #1 1'b0;
   
endmodule