data/full_repos/permissive/441359809/src/yosys/examples/smtbmc/demo4.v
data/verilator_xmls/6006afb9-6d03-4b65-97ae-21006df414dc.xml
module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);
	always @(posedge clk) begin
		if (rst) begin
			r1 <= in;
			r2 <= -in;
		end else begin
			r1 <= r1 + in;
			r2 <= inv2 ? -(r2 - in) : (r2 - in);
		end
	end
endmodule
module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);

	always @(posedge clk) begin
		if (rst) begin
			r1 <= in;
			r2 <= -in;
		end else begin
			r1 <= r1 + in;
			r2 <= inv2 ? -(r2 - in) : (r2 - in);
		end
	end
endmodule