data/full_repos/permissive/439345921/ALU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:269: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:278: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:286: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:303: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:312: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:320: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:329: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:337: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:345: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:356: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:364: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:381: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:398: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:407: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:432: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:449: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:458: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:475: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:483: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:500: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:509: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:517: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:526: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:534: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:543: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:551: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:560: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:568: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:577: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:585: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:594: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:602: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:611: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:619: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:628: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:636: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:645: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/ALU_tb.v:653: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/439345921/ALU_tb.v:15: Cannot find file containing module: \'ALU\'\n ALU ALU_inst(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ALU\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ALU.v\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 73 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();
	reg [15:0] x;
	reg [15:0] y;
	reg zx;
	reg nx;
	reg zy;
	reg ny;
	reg f;
	reg no;
	wire [15:0] out;
	wire zr;
	wire ng;
	
	ALU ALU_inst(
		.x(x),
		.y(y),
		.zx(zx),
		.nx(nx),
		.zy(zy),
		.ny(ny),
		.f(f),
		.no(no),
		.out(out),
		.zr(zr),
		.ng(ng)
	);
	
	initial begin
		x = 16'h0000;
		y = 16'hffff;
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 0;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#100
		x = 16'b000000000010001;
		y = 16'b000000000000011;
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;


		#10
		zx = 1;
		nx = 0;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
	end
endmodule
module ALU_tb();

	reg [15:0] x;
	reg [15:0] y;
	reg zx;
	reg nx;
	reg zy;
	reg ny;
	reg f;
	reg no;
	wire [15:0] out;
	wire zr;
	wire ng;
	
	ALU ALU_inst(
		.x(x),
		.y(y),
		.zx(zx),
		.nx(nx),
		.zy(zy),
		.ny(ny),
		.f(f),
		.no(no),
		.out(out),
		.zr(zr),
		.ng(ng)
	);
	
	initial begin
		x = 16'h0000;
		y = 16'hffff;
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 0;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#100
		x = 16'b000000000010001;
		y = 16'b000000000000011;
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;


		#10
		zx = 1;
		nx = 0;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 1;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 1;
		ny = 1;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 1;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 0;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 1;
		f  = 1;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
		

		#10
		zx = 0;
		nx = 1;
		zy = 0;
		ny = 1;
		f  = 0;
		no = 1;
		
		#10
		zx = 0;
		nx = 0;
		zy = 0;
		ny = 0;
		f  = 0;
		no = 0;
	end
endmodule