data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/atmux1.v
data/verilator_xmls/c76c8c03-ea5f-47ba-94b5-f6e75b146505.xml
module atmux1 (a, b, sela, o);

input   a,
        b,
        sela;

output  o;



reg     o;
always @(sela or a or b)
    begin
    case (sela)
        1'b0: o = b;
        1'b1: o = a;
    endcase
    end

endmodule
module atmux1 (a, b, sela, o);


input   a,
        b,
        sela;

output  o;



reg     o;
always @(sela or a or b)
    begin
    case (sela)
        1'b0: o = b;
        1'b1: o = a;
    endcase
    end

endmodule