data/full_repos/permissive/434187796/src/TIMER.v
1: b"%Error: data/full_repos/permissive/434187796/src/TIMER.v:3: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'cycle'\n                                                          : ... In instance TIMER\n                parameter [31:0] cycle,          \n                                 ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module TIMER
        #(
                parameter [31:0] cycle,
                parameter [31:0] rel = 32'd0
        )
        (
                input clk,
                input rst,
                output reg cy
        );
        reg [31:0] timer;

        initial begin
                timer <= rel;
                cy <= 1'b0;
        end

        always @(posedge clk or negedge rst) begin
                if (rst == 1'b0) begin
                        timer <= rel;
                        cy <= 1'b0;
                end else begin
                        if (timer == (cycle - 32'd1)) begin
                                timer <= 32'b0;
                                cy <= 1'b1;
                        end else begin
                                timer <= timer + 32'd1;
                                cy <= 1'b0;
                        end
                end
        end
endmodule
module TIMER
        #(
                parameter [31:0] cycle,
                parameter [31:0] rel = 32'd0
        )
        (
                input clk,
                input rst,
                output reg cy
        );

        reg [31:0] timer;

        initial begin
                timer <= rel;
                cy <= 1'b0;
        end

        always @(posedge clk or negedge rst) begin
                if (rst == 1'b0) begin
                        timer <= rel;
                        cy <= 1'b0;
                end else begin
                        if (timer == (cycle - 32'd1)) begin
                                timer <= 32'b0;
                                cy <= 1'b1;
                        end else begin
                                timer <= timer + 32'd1;
                                cy <= 1'b0;
                        end
                end
        end
endmodule