data/full_repos/permissive/500128826/HDLBits/Vectors/Vector5/top_module.v
data/verilator_xmls/a6085083-5d2c-43e2-bacc-c452fc209380.xml
module top_module (
    input wire a,
    input wire b,
    input wire c,
    input wire d,
    input wire e,
    output wire [24:0] out
);

  wire [24:0] signals_a = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
  wire [24:0] signals_b = {5{a, b, c, d, e}};
  assign out = signals_a ~^ signals_b;

endmodule
module top_module (
    input wire a,
    input wire b,
    input wire c,
    input wire d,
    input wire e,
    output wire [24:0] out
);


  wire [24:0] signals_a = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
  wire [24:0] signals_b = {5{a, b, c, d, e}};
  assign out = signals_a ~^ signals_b;

endmodule