data/full_repos/permissive/47737018/TB/source_fix4.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/47737018/TB/source_fix4.sv:27: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'mux\'\nmodule mux #(parameter int wl=36)\n       ^~~\n                                                                           : ... Top module \'rdy_en\'\nmodule rdy_en (\n       ^~~~~~\n                                                                           : ... Top module \'crossbar\'\nmodule crossbar #(parameter int wL=36,parameter int lhsCount=5,parameter int rhsCount=5)\n       ^~~~~~~~\n                                                                           : ... Top module \'FIFO\'\nmodule FIFO #(parameter int wL=36,parameter int d=8)\n       ^~~~\n                                                                           : ... Top module \'matrix\'\nmodule matrix #(parameter int WIDTH=36)\n       ^~~~~~\n                                                                           : ... Top module \'findblock\'\nmodule findblock (\n       ^~~~~~~~~\n                                                                           : ... Top module \'priority_encoder\'\nmodule priority_encoder (\n       ^~~~~~~~~~~~~~~~\n                                                                           : ... Top module \'decoder\'\n module decoder(\n        ^~~~~~~\n                                                                           : ... Top module \'decoder_2\'\nmodule decoder_2(\n       ^~~~~~~~~\n                                                                           : ... Top module \'dffr\'\nmodule dffr #(parameter int size = 36 )\n       ^~~~\n                                                                           : ... Top module \'dffr1\'\nmodule dffr1 #(parameter int size = 1 )\n       ^~~~~\n                                                                           : ... Top module \'dffr2\'\nmodule dffr2 #(parameter int size = 5 )\n       ^~~~~\n                                                                           : ... Top module \'dffr3\'\nmodule dffr3 #(parameter int size = 3 )\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:370: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block0\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[0]=(temp_block0)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:371: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block1\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[1]=(temp_block1)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:372: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block2\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[2]=(temp_block2)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:373: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block3\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[3]=(temp_block3)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:374: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block4\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[4]=(temp_block4)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:285: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'counter_pre\' generates 3 bits.\n                                                                         : ... In instance FIFO\nunique case (counter_pre)\n       ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module FIFO #(parameter int wL=36,parameter int d=8)
(
input logic push, 
input logic pop, 
output logic almost_full, 
output logic empty,
output logic almost_empty, 
input logic rst,
input logic clk,
input logic [wL-1:0] rst_val,

input logic full_pre,
output logic full,
input logic [2:0] counter_pre,
output logic [2:0] counter,
input logic [2:0] wrtPtr_next_pre,
output logic [2:0] wrtPtr_next,
input logic [2:0] rdPtr_next_pre,
output logic [2:0] rdPtr_next,

input logic [wL-1:0] data_push,
output logic [wL-1:0] data_pop_next,
output logic [wL-1:0] data_pop
);



logic [wL-1:0] mem[d-1:0];
logic [2:0] wrtPtr;
logic [2:0] rdPtr;





always_comb
begin

if(~rst)
begin
	
	wrtPtr=0;  
	rdPtr=0; 




	counter=0;
	
	mem[0]=rst_val; mem[4]=rst_val; 
	mem[1]=rst_val; mem[6]=rst_val; 
	mem[2]=rst_val; mem[5]=rst_val; 
	mem[3]=rst_val; mem[7]=rst_val; 

	
end
else 
begin
	
	
	begin
	if(push && ~full_pre && ~pop )
	begin
			counter=counter_pre+1;
			wrtPtr=wrtPtr_next_pre;
			mem[wrtPtr]=data_push;
	end
	
		
	if(pop && (~push ||~full_pre))
	begin
	counter=counter_pre-1;
	rdPtr=rdPtr_next_pre;
	end
	
	
	if(pop && push && ~full)
	begin
	  counter=counter_pre;
		wrtPtr=wrtPtr_next_pre;
		mem[wrtPtr]=data_push;
		rdPtr=rdPtr_next_pre;
	end
	




	
end
end
end

always_comb 
begin

if(~rst) begin
    data_pop = rst_val;
    data_pop_next = rst_val;
  end else begin
    data_pop = mem[(rdPtr+3'b001)];
    data_pop_next = mem[(rdPtr+3'b010)];
  end
end

always_comb
begin
wrtPtr_next=wrtPtr+1;
rdPtr_next=rdPtr+1;

unique case (counter_pre)
	4'b000:begin empty=1;almost_empty=1;almost_full=0;full=0;end
	4'b001:begin empty=0;almost_empty=1;almost_full=0;full=0;end
	4'b110:begin empty=0;almost_empty=0;almost_full=1;full=0;end
	4'b111:begin empty=0;almost_empty=0;almost_full=1;full=1;end
	default:begin empty=0;almost_empty=0;almost_full=0;full=0;end
endcase
end

endmodule
module FIFO #(parameter int wL=36,parameter int d=8)
(
input logic push, 
input logic pop, 
output logic almost_full, 
output logic empty,
output logic almost_empty, 
input logic rst,
input logic clk,
input logic [wL-1:0] rst_val,

input logic full_pre,
output logic full,
input logic [2:0] counter_pre,
output logic [2:0] counter,
input logic [2:0] wrtPtr_next_pre,
output logic [2:0] wrtPtr_next,
input logic [2:0] rdPtr_next_pre,
output logic [2:0] rdPtr_next,

input logic [wL-1:0] data_push,
output logic [wL-1:0] data_pop_next,
output logic [wL-1:0] data_pop
);




logic [wL-1:0] mem[d-1:0];
logic [2:0] wrtPtr;
logic [2:0] rdPtr;





always_comb
begin

if(~rst)
begin
	
	wrtPtr=0;  
	rdPtr=0; 




	counter=0;
	
	mem[0]=rst_val; mem[4]=rst_val; 
	mem[1]=rst_val; mem[6]=rst_val; 
	mem[2]=rst_val; mem[5]=rst_val; 
	mem[3]=rst_val; mem[7]=rst_val; 

	
end
else 
begin
	
	
	begin
	if(push && ~full_pre && ~pop )
	begin
			counter=counter_pre+1;
			wrtPtr=wrtPtr_next_pre;
			mem[wrtPtr]=data_push;
	end
	
		
	if(pop && (~push ||~full_pre))
	begin
	counter=counter_pre-1;
	rdPtr=rdPtr_next_pre;
	end
	
	
	if(pop && push && ~full)
	begin
	  counter=counter_pre;
		wrtPtr=wrtPtr_next_pre;
		mem[wrtPtr]=data_push;
		rdPtr=rdPtr_next_pre;
	end
	




	
end
end
end

always_comb 
begin

if(~rst) begin
    data_pop = rst_val;
    data_pop_next = rst_val;
  end else begin
    data_pop = mem[(rdPtr+3'b001)];
    data_pop_next = mem[(rdPtr+3'b010)];
  end
end

always_comb
begin
wrtPtr_next=wrtPtr+1;
rdPtr_next=rdPtr+1;

unique case (counter_pre)
	4'b000:begin empty=1;almost_empty=1;almost_full=0;full=0;end
	4'b001:begin empty=0;almost_empty=1;almost_full=0;full=0;end
	4'b110:begin empty=0;almost_empty=0;almost_full=1;full=0;end
	4'b111:begin empty=0;almost_empty=0;almost_full=1;full=1;end
	default:begin empty=0;almost_empty=0;almost_full=0;full=0;end
endcase
end

endmodule