data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn.v:27: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn.v:28: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn.v:29: Cannot find include file: ctu.h\n`include "ctu.h" \n         ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module ctu_clsp_clkgn(

jbus_mult_rst_l, jbus_gclk_dup_out, dram_gclk_out, 
de_grst_jsync_edge, de_grst_dsync_edge_dl, de_dbginit_jsync_edge, 
de_dbginit_dsync_edge_dl, ctu_jbus_tx_sync_cl, ctu_jbus_rx_sync_cl, 
ctu_jbi_ssiclk, ctu_dram_tx_sync_cl, ctu_dram_rx_sync_cl, coin_edge, 
cmp_grst_cl_l, cmp_gclk_out, cmp_dbginit_cl_l, a_grst_dl, 
a_dbginit_dl, jbus_gclk_out, shadreg_div_dmult, shadreg_div_jmult, 

update_shadow_cl, testmode_l, stretch_cnt_vec, start_clk_early_jl, 
start_clk_cl, start_2clk_early_jl, ssiclk_enable, se, reg_jdiv_vec, 
reg_jdiv_0, reg_div_jmult, reg_div_dmult, reg_div_cmult, 
reg_ddiv_vec, reg_ddiv_0, reg_cdiv_vec, reg_cdiv_0, 
pll_reset_ref_dly1_l, pll_raw_clk_out, pll_clk_out_pre_l, 
pll_clk_out_pre, pll_clk_out_l, pll_clk_out, jtag_nstep_vld, 
jtag_nstep_domain, jtag_nstep_count, jtag_clsp_sel_tck2, 
jtag_clsp_sel_jbus, jtag_clsp_sel_dram, jtag_clsp_sel_cpu, 
jtag_clsp_force_cken_jbus, jtag_clsp_force_cken_dram, 
jtag_clsp_force_cken_cmp, jtag_clock_dr, jsync_reg_tx2, 
jsync_reg_tx1, jsync_reg_tx0, jsync_reg_rx2, jsync_reg_rx1, 
jsync_reg_rx0, jsync_reg_period, jsync_reg_init, jbus_tx_sync, 
jbus_clk, io_tck2, io_pwron_rst_l, dsync_reg_tx2, dsync_reg_tx1, 
dsync_reg_tx0, dsync_reg_rx2, dsync_reg_rx1, dsync_reg_rx0, 
dsync_reg_period, dsync_reg_init, dram_a_grst_cl, 
dft_clsp_nstep_capture_l, de_grst_cl, de_dbginit_cl, 
ctu_dram_tx_sync_early, cmp_clk, clk_stretch_trig, 
clk_stretch_cnt_val_odd, clk_stretch_cnt_val_6, a_grst_cl, 
a_dbginit_cl
);

   output jbus_gclk_out;
   


   input		a_dbginit_cl;
   input		a_grst_cl;
   input		clk_stretch_cnt_val_6;
   input		clk_stretch_cnt_val_odd;
   input		clk_stretch_trig;
   input		cmp_clk;
   input		ctu_dram_tx_sync_early;
   input		de_dbginit_cl;
   input		de_grst_cl;
   input		dft_clsp_nstep_capture_l;
   input		dram_a_grst_cl;
   input [4:0]		dsync_reg_init;
   input [4:0]		dsync_reg_period;
   input [1:0]		dsync_reg_rx0;
   input [1:0]		dsync_reg_rx1;
   input [1:0]		dsync_reg_rx2;
   input [4:0]		dsync_reg_tx0;
   input [4:0]		dsync_reg_tx1;
   input [4:0]		dsync_reg_tx2;
   input		io_pwron_rst_l;
   input		io_tck2;
   input		jbus_clk;
   input		jbus_tx_sync;
   input [4:0]		jsync_reg_init;
   input [4:0]		jsync_reg_period;
   input [1:0]		jsync_reg_rx0;
   input [1:0]		jsync_reg_rx1;
   input [1:0]		jsync_reg_rx2;
   input [4:0]		jsync_reg_tx0;
   input [4:0]		jsync_reg_tx1;
   input [4:0]		jsync_reg_tx2;
   input		jtag_clock_dr;
   input		jtag_clsp_force_cken_cmp;
   input		jtag_clsp_force_cken_dram;
   input		jtag_clsp_force_cken_jbus;
   input [2:0]		jtag_clsp_sel_cpu;
   input [2:0]		jtag_clsp_sel_dram;
   input [2:0]		jtag_clsp_sel_jbus;
   input		jtag_clsp_sel_tck2;
   input [3:0]		jtag_nstep_count;
   input [2:0]		jtag_nstep_domain;
   input		jtag_nstep_vld;
   input		pll_clk_out;
   input		pll_clk_out_l;
   input		pll_clk_out_pre;
   input		pll_clk_out_pre_l;
   input		pll_raw_clk_out;
   input		pll_reset_ref_dly1_l;
   input		reg_cdiv_0;
   input [14:0]		reg_cdiv_vec;
   input		reg_ddiv_0;
   input [14:0]		reg_ddiv_vec;
   input [13:0]		reg_div_cmult;
   input [9:0]		reg_div_dmult;
   input [9:0]		reg_div_jmult;
   input		reg_jdiv_0;
   input [14:0]		reg_jdiv_vec;
   input		se;
   input		ssiclk_enable;
   input		start_2clk_early_jl;
   input		start_clk_cl;
   input		start_clk_early_jl;
   input [14:0]		stretch_cnt_vec;
   input		testmode_l;
   input		update_shadow_cl;


   output [9:0]		shadreg_div_dmult;
   output [9:0]		shadreg_div_jmult;


   output		a_dbginit_dl;
   output		a_grst_dl;
   output		cmp_dbginit_cl_l;
   output		cmp_gclk_out;
   output		cmp_grst_cl_l;
   output		coin_edge;
   output		ctu_dram_rx_sync_cl;
   output		ctu_dram_tx_sync_cl;
   output		ctu_jbi_ssiclk;
   output		ctu_jbus_rx_sync_cl;
   output		ctu_jbus_tx_sync_cl;
   output		de_dbginit_dsync_edge_dl;
   output		de_dbginit_jsync_edge;
   output		de_grst_dsync_edge_dl;
   output		de_grst_jsync_edge;
   output		dram_gclk_out;
   output		jbus_gclk_dup_out;
   output		jbus_mult_rst_l;



   wire			cmp_clk_sel;
   wire			cmp_div0;
   wire			cmp_div1;
   wire			cmp_div_bypass;
   wire			cmp_gclk_byp;
   wire			cmp_gclk_byp_int;
   wire			cmp_gclk_byp_inv;
   wire			cmp_gclk_byp_pre;
   wire			cmp_nstep_sel;
   wire			cmp_tst_clk;
   wire			coin_cnt_en;
   wire			coin_cnt_ld;
   wire			dram_clk_sel;
   wire			dram_div0;
   wire			dram_div1;
   wire			dram_gclk_byp;
   wire			dram_gclk_byp_int;
   wire			dram_gclk_byp_inv;
   wire			dram_gclk_byp_pre;
   wire			dram_nstep_sel;
   wire			dram_tst_clk;
   wire [4:0]		dsync_shadreg_init;
   wire [4:0]		dsync_shadreg_period;
   wire [1:0]		dsync_shadreg_rx0;
   wire [1:0]		dsync_shadreg_rx1;
   wire [1:0]		dsync_shadreg_rx2;
   wire [4:0]		dsync_shadreg_tx0;
   wire [4:0]		dsync_shadreg_tx1;
   wire [4:0]		dsync_shadreg_tx2;
   wire			jbus_alt_bypsel_l;
   wire			jbus_clk_sel;
   wire			jbus_div0;
   wire			jbus_div1;
   wire			jbus_div_bypass;
   wire			jbus_dup_div0;
   wire			jbus_gclk_byp;
   wire			jbus_gclk_byp_int;
   wire			jbus_gclk_byp_inv;
   wire			jbus_gclk_byp_pre;
   wire			jbus_nstep_sel;
   wire			jbus_tst_clk;
   wire [4:0]		jsync_shadreg_init;
   wire [4:0]		jsync_shadreg_period;
   wire [1:0]		jsync_shadreg_rx0;
   wire [1:0]		jsync_shadreg_rx1;
   wire [1:0]		jsync_shadreg_rx2;
   wire [4:0]		jsync_shadreg_tx0;
   wire [4:0]		jsync_shadreg_tx1;
   wire [4:0]		jsync_shadreg_tx2;
   wire			jtag_clock_dr_cmp;
   wire			jtag_clock_dr_dram;
   wire			jtag_clock_dr_jbus;
   wire			shadreg_cdiv_0;
   wire [14:0]		shadreg_cdiv_vec;
   wire			shadreg_ddiv_0;
   wire [14:0]		shadreg_ddiv_vec;
   wire [13:0]		shadreg_div_cmult;
   wire			shadreg_jdiv_0;
   wire [14:0]		shadreg_jdiv_vec;




     ctu_clsp_clkgn_fstlog  u_ctu_clsp_clkgn_fstlog (

						     .cmp_div0(cmp_div0),
						     .cmp_div1(cmp_div1),
						     .dram_div0(dram_div0),
						     .dram_div1(dram_div1),
						     .jbus_div0(jbus_div0),
						     .jbus_div1(jbus_div1),
						     .jbus_dup_div0(jbus_dup_div0),
						     .cmp_div_bypass(cmp_div_bypass),
						     .jbus_div_bypass(jbus_div_bypass),
						     .so(),
						     .jbus_mult_rst_l(jbus_mult_rst_l),
						     .jbus_alt_bypsel_l(jbus_alt_bypsel_l),

						     .clsp_fstlog_corepll_j_0(shadreg_jdiv_0),
						     .clsp_fstlog_corepll_d_0(shadreg_ddiv_0),
						     .clsp_fstlog_corepll_c_0(shadreg_cdiv_0),
						     .cdiv_vec(shadreg_cdiv_vec[14:0]),
						     .ddiv_vec(shadreg_ddiv_vec[14:0]),
						     .jdiv_vec(shadreg_jdiv_vec[14:0]),
						     .stretch_cnt_vec(stretch_cnt_vec[14:0]),
						     .bypclksel(jtag_clsp_sel_jbus[2]),
						     .se(se),
						     .si(1'b0),
						     .pll_reset_ref_l(pll_reset_ref_dly1_l),
						     .start_clk_jl(start_2clk_early_jl),
						     .clk_stretch_cnt_val_6(clk_stretch_cnt_val_6),
						     .clk_stretch_cnt_val_odd(clk_stretch_cnt_val_odd),
						     .clk_stretch_trig(clk_stretch_trig),
						     .pll_clk_out(pll_clk_out),
						     .pll_clk_out_l(pll_clk_out_l));


     ctu_clsp_clkgn_syncp u_ctu_clsp_clkgn_jsyncp(

						  .tx_sync(ctu_jbus_tx_sync_cl),
						  .rx_sync(ctu_jbus_rx_sync_cl),

						  .cmp_clk(cmp_clk),
						  .start_clk_early_jl(start_clk_early_jl),
						  .coin_cnt_en(coin_cnt_en),
						  .coin_cnt_ld(coin_cnt_ld),
						  .clsp_sync_tx0(jsync_shadreg_tx0[4:0]),
						  .clsp_sync_tx1(jsync_shadreg_tx1[4:0]),
						  .clsp_sync_tx2(jsync_shadreg_tx2[4:0]),
						  .clsp_sync_rx0(jsync_shadreg_rx0[1:0]),
						  .clsp_sync_rx1(jsync_shadreg_rx1[1:0]),
						  .clsp_sync_rx2(jsync_shadreg_rx2[1:0]),
						  .clsp_sync_init(jsync_shadreg_init[4:0]),
						  .clsp_sync_period(jsync_shadreg_period[4:0]));



     ctu_clsp_clkgn_syncp u_ctu_clsp_clkgn_dsyncp(

						  .tx_sync(ctu_dram_tx_sync_cl),
						  .rx_sync(ctu_dram_rx_sync_cl),

						  .cmp_clk(cmp_clk),
						  .start_clk_early_jl(start_clk_early_jl),
						  .coin_cnt_en(coin_cnt_en),
						  .coin_cnt_ld(coin_cnt_ld),
						  .clsp_sync_tx0(dsync_shadreg_tx0[4:0]),
						  .clsp_sync_tx1(dsync_shadreg_tx1[4:0]),
						  .clsp_sync_tx2(dsync_shadreg_tx2[4:0]),
						  .clsp_sync_rx0(dsync_shadreg_rx0[1:0]),
						  .clsp_sync_rx1(dsync_shadreg_rx1[1:0]),
						  .clsp_sync_rx2(dsync_shadreg_rx2[1:0]),
						  .clsp_sync_init(dsync_shadreg_init[4:0]),
						  .clsp_sync_period(dsync_shadreg_period[4:0]));


     ctu_clsp_clkgn_ssiclk u_ctu_clsp_clkgn_ssiclk (

						    .ctu_jbi_ssiclk(ctu_jbi_ssiclk),

						    .io_pwron_rst_l(io_pwron_rst_l),
						    .jbus_clk(jbus_clk),
						    .ssiclk_enable(ssiclk_enable));

  




    ctu_mux21 u_ctu_clsp_clkgn_clksw_cmp_tck_mux (

						  .z( jtag_clock_dr_cmp),

						  .d0( jtag_clock_dr),
						  .d1( io_tck2),
						  .s( jtag_clsp_sel_tck2 ));



    ctu_mux21 u_ctu_clsp_clkgn_clksw_jbus_tck_mux (

						   .z( jtag_clock_dr_jbus),

						   .d0( jtag_clock_dr),
						   .d1( pll_raw_clk_out),
						   .s( jtag_clsp_sel_tck2 ));


    ctu_mux21 u_ctu_clsp_clkgn_clksw_dram_tck_mux (

						   .z( jtag_clock_dr_dram),

						   .d0(jtag_clock_dr),
						   .d1(pll_raw_clk_out),
						   .s( jtag_clsp_sel_tck2 ));





    ctu_clsp_clkgn_nstep u_ctu_clsp_clkgn_nstep(

						.cmp_nstep_sel(cmp_nstep_sel),
						.jbus_nstep_sel(jbus_nstep_sel),
						.dram_nstep_sel(dram_nstep_sel),

						.io_pwron_rst_l(io_pwron_rst_l),
						.jtag_clock_dr_cmp(jtag_clock_dr_cmp),
						.jtag_clock_dr_dram(jtag_clock_dr_dram),
						.jtag_clock_dr_jbus(jtag_clock_dr_jbus),
						.jtag_clsp_force_cken_jbus(jtag_clsp_force_cken_jbus),
						.jtag_clsp_force_cken_dram(jtag_clsp_force_cken_dram),
						.jtag_clsp_force_cken_cmp(jtag_clsp_force_cken_cmp),
						.jtag_nstep_count(jtag_nstep_count[3:0]),
						.jtag_nstep_domain(jtag_nstep_domain[2:0]),
						.jtag_nstep_vld(jtag_nstep_vld),
						.cmp_gclk_bypass(cmp_gclk_byp_int),
						.dram_gclk_bypass(dram_gclk_byp_int),
						.jbus_gclk_bypass(jbus_gclk_byp_int),
						.capture_l(dft_clsp_nstep_capture_l),
						.start_clk_early_jl(start_clk_early_jl),
						.testmode_l(testmode_l),
						.shadreg_div_cmult(shadreg_div_cmult[13:0]),
						.shadreg_div_jmult(shadreg_div_jmult[9:0]),
						.shadreg_div_dmult(shadreg_div_dmult[9:0]));




     ctu_clsp_clkgn_clksw u_ctu_clsp_clkgn_clksw(

						 .cmp_tst_clk(cmp_tst_clk),
						 .cmp_clk_sel(cmp_clk_sel),
						 .dram_tst_clk(dram_tst_clk),
						 .dram_clk_sel(dram_clk_sel),
						 .jbus_tst_clk(jbus_tst_clk),
						 .jbus_clk_sel(jbus_clk_sel),

						 .io_pwron_rst_l(io_pwron_rst_l),
						 .jtag_clock_dr_cmp(jtag_clock_dr_cmp),
						 .jtag_clock_dr_jbus(jtag_clock_dr_jbus),
						 .jtag_clock_dr_dram(jtag_clock_dr_dram),
						 .capture_l(dft_clsp_nstep_capture_l),
						 .jtag_clsp_sel_cpu(jtag_clsp_sel_cpu[2:0]),
						 .jtag_clsp_sel_dram(jtag_clsp_sel_dram[2:0]),
						 .jtag_clsp_sel_jbus(jtag_clsp_sel_jbus[2:0]),
						 .jbus_alt_bypsel_l(jbus_alt_bypsel_l),
						 .cmp_div_bypass(cmp_div_bypass),
						 .cmp_gclk_bypass(cmp_gclk_byp),
						 .jbus_div_bypass(jbus_div_bypass),
						 .jbus_gclk_bypass(jbus_gclk_byp),
						 .dram_gclk_bypass(dram_gclk_byp),
						 .testmode_l(testmode_l),
						 .cmp_nstep_sel(cmp_nstep_sel),
						 .jbus_nstep_sel(jbus_nstep_sel),
						 .dram_nstep_sel(dram_nstep_sel));


     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_dram0_gated (

						    .z(dram_gclk_byp),

						    .a(dram_gclk_byp_inv));


     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_dram1_gated (

						    .z(dram_gclk_byp_pre),

						    .a(dram_gclk_byp_inv));



     bw_u1_ckbuf_30x u_ctu_clsp_clkgn_mux_dram2_gated (

						       .clk(dram_gclk_byp_int),

						       .rclk(dram_gclk_byp_pre));




     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_jbus0_gated (

						    .z(jbus_gclk_byp),

						    .a(jbus_gclk_byp_inv));


     bw_u1_inv_5x  u_ctu_clsp_clkgn_mux_jbus1_gated (

						     .z(jbus_gclk_byp_pre),

						     .a(jbus_gclk_byp_inv));


     bw_u1_ckbuf_30x u_ctu_clsp_clkgn_mux_jbus2_gated (

						       .clk(jbus_gclk_byp_int),

						       .rclk(jbus_gclk_byp_pre));




     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_cmp0_gated (

						   .z(cmp_gclk_byp),

						   .a(cmp_gclk_byp_inv));


     bw_u1_inv_5x  u_ctu_clsp_clkgn_mux_cmp1_gated (

						    .z(cmp_gclk_byp_pre),

						    .a(cmp_gclk_byp_inv));


     bw_clk_cl_ctu_2xcmp u_ctu_clsp_clkgn_mux_cmp2_gated (

							  .bw_pll_2x_clk_local(cmp_gclk_byp_int),

							  .bw_pll_2xclk(cmp_gclk_byp_pre));



  

     bw_ctu_clk_sync_mux u_ctu_clsp_clkgn_mux(

					      .cmp_gclk_byp(cmp_gclk_byp_inv),
					      .dram_gclk_byp(dram_gclk_byp_inv),
					      .jbus_gclk_byp(jbus_gclk_byp_inv),
					      .cmp_gclk_out(cmp_gclk_out),
					      .dram_gclk_out(dram_gclk_out),
					      .jbus_gclk_out(jbus_gclk_out),
					      .jbus_gclk_dup_byp(),
					      .jbus_gclk_dup_out(jbus_gclk_dup_out),

					      .tcu_sel_jbus(jbus_clk_sel),
					      .tcu_sel_dram(dram_clk_sel),
					      .tcu_sel_cpu(cmp_clk_sel),
					      .tcu_sel_jbus_dup(1'b1),
					      .jbus_div0(jbus_div0),
					      .jbus_clk_mux_0(jbus_tst_clk),
					      .jbus_div1(jbus_div1),
					      .dram_clk_mux_0(dram_tst_clk),
					      .dram_div0(dram_div0),
					      .dram_div1(dram_div1),
					      .pll_clk_out(pll_clk_out_pre),
					      .cmp_div1(cmp_div1),
					      .cmp_div0(cmp_div0),
					      .cmp_clk_mux_0(cmp_tst_clk),
					      .pll_clk_out_l(pll_clk_out_pre_l),
					      .jbus_gclk_dupl_mux_0(1'b0),
					      .jbus_dup_div0(jbus_dup_div0),
					      .jbus_dup_div1(1'b0));




     ctu_clsp_clkgn_shadreg u_ctu_clsp_clkgn_shadreg(

						     .jsync_shadreg_rx2(jsync_shadreg_rx2[1:0]),
						     .jsync_shadreg_rx1(jsync_shadreg_rx1[1:0]),
						     .jsync_shadreg_rx0(jsync_shadreg_rx0[1:0]),
						     .jsync_shadreg_tx2(jsync_shadreg_tx2[4:0]),
						     .jsync_shadreg_tx1(jsync_shadreg_tx1[4:0]),
						     .jsync_shadreg_tx0(jsync_shadreg_tx0[4:0]),
						     .jsync_shadreg_period(jsync_shadreg_period[4:0]),
						     .jsync_shadreg_init(jsync_shadreg_init[4:0]),
						     .dsync_shadreg_rx2(dsync_shadreg_rx2[1:0]),
						     .dsync_shadreg_rx1(dsync_shadreg_rx1[1:0]),
						     .dsync_shadreg_rx0(dsync_shadreg_rx0[1:0]),
						     .dsync_shadreg_tx2(dsync_shadreg_tx2[4:0]),
						     .dsync_shadreg_tx1(dsync_shadreg_tx1[4:0]),
						     .dsync_shadreg_tx0(dsync_shadreg_tx0[4:0]),
						     .dsync_shadreg_period(dsync_shadreg_period[4:0]),
						     .dsync_shadreg_init(dsync_shadreg_init[4:0]),
						     .shadreg_cdiv_vec(shadreg_cdiv_vec[14:0]),
						     .shadreg_cdiv_0(shadreg_cdiv_0),
						     .shadreg_ddiv_vec(shadreg_ddiv_vec[14:0]),
						     .shadreg_ddiv_0(shadreg_ddiv_0),
						     .shadreg_jdiv_vec(shadreg_jdiv_vec[14:0]),
						     .shadreg_jdiv_0(shadreg_jdiv_0),
						     .cmp_grst_cl_l(cmp_grst_cl_l),
						     .cmp_dbginit_cl_l(cmp_dbginit_cl_l),
						     .a_grst_dl(a_grst_dl),
						     .a_dbginit_dl(a_dbginit_dl),
						     .de_grst_dsync_edge_dl(de_grst_dsync_edge_dl),
						     .de_grst_jsync_edge(de_grst_jsync_edge),
						     .de_dbginit_dsync_edge_dl(de_dbginit_dsync_edge_dl),
						     .de_dbginit_jsync_edge(de_dbginit_jsync_edge),
						     .coin_cnt_en(coin_cnt_en),
						     .coin_cnt_ld(coin_cnt_ld),
						     .coin_edge(coin_edge),
						     .shadreg_div_jmult(shadreg_div_jmult[9:0]),
						     .shadreg_div_dmult(shadreg_div_dmult[9:0]),
						     .shadreg_div_cmult(shadreg_div_cmult[13:0]),

						     .io_pwron_rst_l(io_pwron_rst_l),
						     .se(se),
						     .start_clk_early_jl(start_clk_early_jl),
						     .start_clk_cl(start_clk_cl),
						     .cmp_clk(cmp_clk),
						     .jbus_tx_sync(jbus_tx_sync),
						     .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
						     .a_dbginit_cl(a_dbginit_cl),
						     .de_dbginit_cl(de_dbginit_cl),
						     .de_grst_cl(de_grst_cl),
						     .a_grst_cl(a_grst_cl),
						     .dram_a_grst_cl(dram_a_grst_cl),
						     .update_shadow_cl(update_shadow_cl),
						     .jtag_ctu_bypass_mode(jtag_clsp_sel_jbus[2]),
						     .jsync_reg_rx2(jsync_reg_rx2[1:0]),
						     .jsync_reg_rx1(jsync_reg_rx1[1:0]),
						     .jsync_reg_rx0(jsync_reg_rx0[1:0]),
						     .jsync_reg_tx2(jsync_reg_tx2[4:0]),
						     .jsync_reg_tx1(jsync_reg_tx1[4:0]),
						     .jsync_reg_tx0(jsync_reg_tx0[4:0]),
						     .jsync_reg_period(jsync_reg_period[4:0]),
						     .jsync_reg_init(jsync_reg_init[4:0]),
						     .dsync_reg_rx2(dsync_reg_rx2[1:0]),
						     .dsync_reg_rx1(dsync_reg_rx1[1:0]),
						     .dsync_reg_rx0(dsync_reg_rx0[1:0]),
						     .dsync_reg_tx2(dsync_reg_tx2[4:0]),
						     .dsync_reg_tx1(dsync_reg_tx1[4:0]),
						     .dsync_reg_tx0(dsync_reg_tx0[4:0]),
						     .dsync_reg_period(dsync_reg_period[4:0]),
						     .dsync_reg_init(dsync_reg_init[4:0]),
						     .reg_div_cmult(reg_div_cmult[13:0]),
						     .reg_div_jmult(reg_div_jmult[9:0]),
						     .reg_div_dmult(reg_div_dmult[9:0]),
						     .reg_cdiv_0(reg_cdiv_0),
						     .reg_cdiv_vec(reg_cdiv_vec[14:0]),
						     .reg_ddiv_0(reg_ddiv_0),
						     .reg_ddiv_vec(reg_ddiv_vec[14:0]),
						     .reg_jdiv_0(reg_jdiv_0),
						     .reg_jdiv_vec(reg_jdiv_vec[14:0]));





endmodule
module ctu_clsp_clkgn(

jbus_mult_rst_l, jbus_gclk_dup_out, dram_gclk_out, 
de_grst_jsync_edge, de_grst_dsync_edge_dl, de_dbginit_jsync_edge, 
de_dbginit_dsync_edge_dl, ctu_jbus_tx_sync_cl, ctu_jbus_rx_sync_cl, 
ctu_jbi_ssiclk, ctu_dram_tx_sync_cl, ctu_dram_rx_sync_cl, coin_edge, 
cmp_grst_cl_l, cmp_gclk_out, cmp_dbginit_cl_l, a_grst_dl, 
a_dbginit_dl, jbus_gclk_out, shadreg_div_dmult, shadreg_div_jmult, 

update_shadow_cl, testmode_l, stretch_cnt_vec, start_clk_early_jl, 
start_clk_cl, start_2clk_early_jl, ssiclk_enable, se, reg_jdiv_vec, 
reg_jdiv_0, reg_div_jmult, reg_div_dmult, reg_div_cmult, 
reg_ddiv_vec, reg_ddiv_0, reg_cdiv_vec, reg_cdiv_0, 
pll_reset_ref_dly1_l, pll_raw_clk_out, pll_clk_out_pre_l, 
pll_clk_out_pre, pll_clk_out_l, pll_clk_out, jtag_nstep_vld, 
jtag_nstep_domain, jtag_nstep_count, jtag_clsp_sel_tck2, 
jtag_clsp_sel_jbus, jtag_clsp_sel_dram, jtag_clsp_sel_cpu, 
jtag_clsp_force_cken_jbus, jtag_clsp_force_cken_dram, 
jtag_clsp_force_cken_cmp, jtag_clock_dr, jsync_reg_tx2, 
jsync_reg_tx1, jsync_reg_tx0, jsync_reg_rx2, jsync_reg_rx1, 
jsync_reg_rx0, jsync_reg_period, jsync_reg_init, jbus_tx_sync, 
jbus_clk, io_tck2, io_pwron_rst_l, dsync_reg_tx2, dsync_reg_tx1, 
dsync_reg_tx0, dsync_reg_rx2, dsync_reg_rx1, dsync_reg_rx0, 
dsync_reg_period, dsync_reg_init, dram_a_grst_cl, 
dft_clsp_nstep_capture_l, de_grst_cl, de_dbginit_cl, 
ctu_dram_tx_sync_early, cmp_clk, clk_stretch_trig, 
clk_stretch_cnt_val_odd, clk_stretch_cnt_val_6, a_grst_cl, 
a_dbginit_cl
);


   output jbus_gclk_out;
   


   input		a_dbginit_cl;
   input		a_grst_cl;
   input		clk_stretch_cnt_val_6;
   input		clk_stretch_cnt_val_odd;
   input		clk_stretch_trig;
   input		cmp_clk;
   input		ctu_dram_tx_sync_early;
   input		de_dbginit_cl;
   input		de_grst_cl;
   input		dft_clsp_nstep_capture_l;
   input		dram_a_grst_cl;
   input [4:0]		dsync_reg_init;
   input [4:0]		dsync_reg_period;
   input [1:0]		dsync_reg_rx0;
   input [1:0]		dsync_reg_rx1;
   input [1:0]		dsync_reg_rx2;
   input [4:0]		dsync_reg_tx0;
   input [4:0]		dsync_reg_tx1;
   input [4:0]		dsync_reg_tx2;
   input		io_pwron_rst_l;
   input		io_tck2;
   input		jbus_clk;
   input		jbus_tx_sync;
   input [4:0]		jsync_reg_init;
   input [4:0]		jsync_reg_period;
   input [1:0]		jsync_reg_rx0;
   input [1:0]		jsync_reg_rx1;
   input [1:0]		jsync_reg_rx2;
   input [4:0]		jsync_reg_tx0;
   input [4:0]		jsync_reg_tx1;
   input [4:0]		jsync_reg_tx2;
   input		jtag_clock_dr;
   input		jtag_clsp_force_cken_cmp;
   input		jtag_clsp_force_cken_dram;
   input		jtag_clsp_force_cken_jbus;
   input [2:0]		jtag_clsp_sel_cpu;
   input [2:0]		jtag_clsp_sel_dram;
   input [2:0]		jtag_clsp_sel_jbus;
   input		jtag_clsp_sel_tck2;
   input [3:0]		jtag_nstep_count;
   input [2:0]		jtag_nstep_domain;
   input		jtag_nstep_vld;
   input		pll_clk_out;
   input		pll_clk_out_l;
   input		pll_clk_out_pre;
   input		pll_clk_out_pre_l;
   input		pll_raw_clk_out;
   input		pll_reset_ref_dly1_l;
   input		reg_cdiv_0;
   input [14:0]		reg_cdiv_vec;
   input		reg_ddiv_0;
   input [14:0]		reg_ddiv_vec;
   input [13:0]		reg_div_cmult;
   input [9:0]		reg_div_dmult;
   input [9:0]		reg_div_jmult;
   input		reg_jdiv_0;
   input [14:0]		reg_jdiv_vec;
   input		se;
   input		ssiclk_enable;
   input		start_2clk_early_jl;
   input		start_clk_cl;
   input		start_clk_early_jl;
   input [14:0]		stretch_cnt_vec;
   input		testmode_l;
   input		update_shadow_cl;


   output [9:0]		shadreg_div_dmult;
   output [9:0]		shadreg_div_jmult;


   output		a_dbginit_dl;
   output		a_grst_dl;
   output		cmp_dbginit_cl_l;
   output		cmp_gclk_out;
   output		cmp_grst_cl_l;
   output		coin_edge;
   output		ctu_dram_rx_sync_cl;
   output		ctu_dram_tx_sync_cl;
   output		ctu_jbi_ssiclk;
   output		ctu_jbus_rx_sync_cl;
   output		ctu_jbus_tx_sync_cl;
   output		de_dbginit_dsync_edge_dl;
   output		de_dbginit_jsync_edge;
   output		de_grst_dsync_edge_dl;
   output		de_grst_jsync_edge;
   output		dram_gclk_out;
   output		jbus_gclk_dup_out;
   output		jbus_mult_rst_l;



   wire			cmp_clk_sel;
   wire			cmp_div0;
   wire			cmp_div1;
   wire			cmp_div_bypass;
   wire			cmp_gclk_byp;
   wire			cmp_gclk_byp_int;
   wire			cmp_gclk_byp_inv;
   wire			cmp_gclk_byp_pre;
   wire			cmp_nstep_sel;
   wire			cmp_tst_clk;
   wire			coin_cnt_en;
   wire			coin_cnt_ld;
   wire			dram_clk_sel;
   wire			dram_div0;
   wire			dram_div1;
   wire			dram_gclk_byp;
   wire			dram_gclk_byp_int;
   wire			dram_gclk_byp_inv;
   wire			dram_gclk_byp_pre;
   wire			dram_nstep_sel;
   wire			dram_tst_clk;
   wire [4:0]		dsync_shadreg_init;
   wire [4:0]		dsync_shadreg_period;
   wire [1:0]		dsync_shadreg_rx0;
   wire [1:0]		dsync_shadreg_rx1;
   wire [1:0]		dsync_shadreg_rx2;
   wire [4:0]		dsync_shadreg_tx0;
   wire [4:0]		dsync_shadreg_tx1;
   wire [4:0]		dsync_shadreg_tx2;
   wire			jbus_alt_bypsel_l;
   wire			jbus_clk_sel;
   wire			jbus_div0;
   wire			jbus_div1;
   wire			jbus_div_bypass;
   wire			jbus_dup_div0;
   wire			jbus_gclk_byp;
   wire			jbus_gclk_byp_int;
   wire			jbus_gclk_byp_inv;
   wire			jbus_gclk_byp_pre;
   wire			jbus_nstep_sel;
   wire			jbus_tst_clk;
   wire [4:0]		jsync_shadreg_init;
   wire [4:0]		jsync_shadreg_period;
   wire [1:0]		jsync_shadreg_rx0;
   wire [1:0]		jsync_shadreg_rx1;
   wire [1:0]		jsync_shadreg_rx2;
   wire [4:0]		jsync_shadreg_tx0;
   wire [4:0]		jsync_shadreg_tx1;
   wire [4:0]		jsync_shadreg_tx2;
   wire			jtag_clock_dr_cmp;
   wire			jtag_clock_dr_dram;
   wire			jtag_clock_dr_jbus;
   wire			shadreg_cdiv_0;
   wire [14:0]		shadreg_cdiv_vec;
   wire			shadreg_ddiv_0;
   wire [14:0]		shadreg_ddiv_vec;
   wire [13:0]		shadreg_div_cmult;
   wire			shadreg_jdiv_0;
   wire [14:0]		shadreg_jdiv_vec;




     ctu_clsp_clkgn_fstlog  u_ctu_clsp_clkgn_fstlog (

						     .cmp_div0(cmp_div0),
						     .cmp_div1(cmp_div1),
						     .dram_div0(dram_div0),
						     .dram_div1(dram_div1),
						     .jbus_div0(jbus_div0),
						     .jbus_div1(jbus_div1),
						     .jbus_dup_div0(jbus_dup_div0),
						     .cmp_div_bypass(cmp_div_bypass),
						     .jbus_div_bypass(jbus_div_bypass),
						     .so(),
						     .jbus_mult_rst_l(jbus_mult_rst_l),
						     .jbus_alt_bypsel_l(jbus_alt_bypsel_l),

						     .clsp_fstlog_corepll_j_0(shadreg_jdiv_0),
						     .clsp_fstlog_corepll_d_0(shadreg_ddiv_0),
						     .clsp_fstlog_corepll_c_0(shadreg_cdiv_0),
						     .cdiv_vec(shadreg_cdiv_vec[14:0]),
						     .ddiv_vec(shadreg_ddiv_vec[14:0]),
						     .jdiv_vec(shadreg_jdiv_vec[14:0]),
						     .stretch_cnt_vec(stretch_cnt_vec[14:0]),
						     .bypclksel(jtag_clsp_sel_jbus[2]),
						     .se(se),
						     .si(1'b0),
						     .pll_reset_ref_l(pll_reset_ref_dly1_l),
						     .start_clk_jl(start_2clk_early_jl),
						     .clk_stretch_cnt_val_6(clk_stretch_cnt_val_6),
						     .clk_stretch_cnt_val_odd(clk_stretch_cnt_val_odd),
						     .clk_stretch_trig(clk_stretch_trig),
						     .pll_clk_out(pll_clk_out),
						     .pll_clk_out_l(pll_clk_out_l));


     ctu_clsp_clkgn_syncp u_ctu_clsp_clkgn_jsyncp(

						  .tx_sync(ctu_jbus_tx_sync_cl),
						  .rx_sync(ctu_jbus_rx_sync_cl),

						  .cmp_clk(cmp_clk),
						  .start_clk_early_jl(start_clk_early_jl),
						  .coin_cnt_en(coin_cnt_en),
						  .coin_cnt_ld(coin_cnt_ld),
						  .clsp_sync_tx0(jsync_shadreg_tx0[4:0]),
						  .clsp_sync_tx1(jsync_shadreg_tx1[4:0]),
						  .clsp_sync_tx2(jsync_shadreg_tx2[4:0]),
						  .clsp_sync_rx0(jsync_shadreg_rx0[1:0]),
						  .clsp_sync_rx1(jsync_shadreg_rx1[1:0]),
						  .clsp_sync_rx2(jsync_shadreg_rx2[1:0]),
						  .clsp_sync_init(jsync_shadreg_init[4:0]),
						  .clsp_sync_period(jsync_shadreg_period[4:0]));



     ctu_clsp_clkgn_syncp u_ctu_clsp_clkgn_dsyncp(

						  .tx_sync(ctu_dram_tx_sync_cl),
						  .rx_sync(ctu_dram_rx_sync_cl),

						  .cmp_clk(cmp_clk),
						  .start_clk_early_jl(start_clk_early_jl),
						  .coin_cnt_en(coin_cnt_en),
						  .coin_cnt_ld(coin_cnt_ld),
						  .clsp_sync_tx0(dsync_shadreg_tx0[4:0]),
						  .clsp_sync_tx1(dsync_shadreg_tx1[4:0]),
						  .clsp_sync_tx2(dsync_shadreg_tx2[4:0]),
						  .clsp_sync_rx0(dsync_shadreg_rx0[1:0]),
						  .clsp_sync_rx1(dsync_shadreg_rx1[1:0]),
						  .clsp_sync_rx2(dsync_shadreg_rx2[1:0]),
						  .clsp_sync_init(dsync_shadreg_init[4:0]),
						  .clsp_sync_period(dsync_shadreg_period[4:0]));


     ctu_clsp_clkgn_ssiclk u_ctu_clsp_clkgn_ssiclk (

						    .ctu_jbi_ssiclk(ctu_jbi_ssiclk),

						    .io_pwron_rst_l(io_pwron_rst_l),
						    .jbus_clk(jbus_clk),
						    .ssiclk_enable(ssiclk_enable));

  




    ctu_mux21 u_ctu_clsp_clkgn_clksw_cmp_tck_mux (

						  .z( jtag_clock_dr_cmp),

						  .d0( jtag_clock_dr),
						  .d1( io_tck2),
						  .s( jtag_clsp_sel_tck2 ));



    ctu_mux21 u_ctu_clsp_clkgn_clksw_jbus_tck_mux (

						   .z( jtag_clock_dr_jbus),

						   .d0( jtag_clock_dr),
						   .d1( pll_raw_clk_out),
						   .s( jtag_clsp_sel_tck2 ));


    ctu_mux21 u_ctu_clsp_clkgn_clksw_dram_tck_mux (

						   .z( jtag_clock_dr_dram),

						   .d0(jtag_clock_dr),
						   .d1(pll_raw_clk_out),
						   .s( jtag_clsp_sel_tck2 ));





    ctu_clsp_clkgn_nstep u_ctu_clsp_clkgn_nstep(

						.cmp_nstep_sel(cmp_nstep_sel),
						.jbus_nstep_sel(jbus_nstep_sel),
						.dram_nstep_sel(dram_nstep_sel),

						.io_pwron_rst_l(io_pwron_rst_l),
						.jtag_clock_dr_cmp(jtag_clock_dr_cmp),
						.jtag_clock_dr_dram(jtag_clock_dr_dram),
						.jtag_clock_dr_jbus(jtag_clock_dr_jbus),
						.jtag_clsp_force_cken_jbus(jtag_clsp_force_cken_jbus),
						.jtag_clsp_force_cken_dram(jtag_clsp_force_cken_dram),
						.jtag_clsp_force_cken_cmp(jtag_clsp_force_cken_cmp),
						.jtag_nstep_count(jtag_nstep_count[3:0]),
						.jtag_nstep_domain(jtag_nstep_domain[2:0]),
						.jtag_nstep_vld(jtag_nstep_vld),
						.cmp_gclk_bypass(cmp_gclk_byp_int),
						.dram_gclk_bypass(dram_gclk_byp_int),
						.jbus_gclk_bypass(jbus_gclk_byp_int),
						.capture_l(dft_clsp_nstep_capture_l),
						.start_clk_early_jl(start_clk_early_jl),
						.testmode_l(testmode_l),
						.shadreg_div_cmult(shadreg_div_cmult[13:0]),
						.shadreg_div_jmult(shadreg_div_jmult[9:0]),
						.shadreg_div_dmult(shadreg_div_dmult[9:0]));




     ctu_clsp_clkgn_clksw u_ctu_clsp_clkgn_clksw(

						 .cmp_tst_clk(cmp_tst_clk),
						 .cmp_clk_sel(cmp_clk_sel),
						 .dram_tst_clk(dram_tst_clk),
						 .dram_clk_sel(dram_clk_sel),
						 .jbus_tst_clk(jbus_tst_clk),
						 .jbus_clk_sel(jbus_clk_sel),

						 .io_pwron_rst_l(io_pwron_rst_l),
						 .jtag_clock_dr_cmp(jtag_clock_dr_cmp),
						 .jtag_clock_dr_jbus(jtag_clock_dr_jbus),
						 .jtag_clock_dr_dram(jtag_clock_dr_dram),
						 .capture_l(dft_clsp_nstep_capture_l),
						 .jtag_clsp_sel_cpu(jtag_clsp_sel_cpu[2:0]),
						 .jtag_clsp_sel_dram(jtag_clsp_sel_dram[2:0]),
						 .jtag_clsp_sel_jbus(jtag_clsp_sel_jbus[2:0]),
						 .jbus_alt_bypsel_l(jbus_alt_bypsel_l),
						 .cmp_div_bypass(cmp_div_bypass),
						 .cmp_gclk_bypass(cmp_gclk_byp),
						 .jbus_div_bypass(jbus_div_bypass),
						 .jbus_gclk_bypass(jbus_gclk_byp),
						 .dram_gclk_bypass(dram_gclk_byp),
						 .testmode_l(testmode_l),
						 .cmp_nstep_sel(cmp_nstep_sel),
						 .jbus_nstep_sel(jbus_nstep_sel),
						 .dram_nstep_sel(dram_nstep_sel));


     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_dram0_gated (

						    .z(dram_gclk_byp),

						    .a(dram_gclk_byp_inv));


     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_dram1_gated (

						    .z(dram_gclk_byp_pre),

						    .a(dram_gclk_byp_inv));



     bw_u1_ckbuf_30x u_ctu_clsp_clkgn_mux_dram2_gated (

						       .clk(dram_gclk_byp_int),

						       .rclk(dram_gclk_byp_pre));




     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_jbus0_gated (

						    .z(jbus_gclk_byp),

						    .a(jbus_gclk_byp_inv));


     bw_u1_inv_5x  u_ctu_clsp_clkgn_mux_jbus1_gated (

						     .z(jbus_gclk_byp_pre),

						     .a(jbus_gclk_byp_inv));


     bw_u1_ckbuf_30x u_ctu_clsp_clkgn_mux_jbus2_gated (

						       .clk(jbus_gclk_byp_int),

						       .rclk(jbus_gclk_byp_pre));




     bw_u1_inv_5x u_ctu_clsp_clkgn_mux_cmp0_gated (

						   .z(cmp_gclk_byp),

						   .a(cmp_gclk_byp_inv));


     bw_u1_inv_5x  u_ctu_clsp_clkgn_mux_cmp1_gated (

						    .z(cmp_gclk_byp_pre),

						    .a(cmp_gclk_byp_inv));


     bw_clk_cl_ctu_2xcmp u_ctu_clsp_clkgn_mux_cmp2_gated (

							  .bw_pll_2x_clk_local(cmp_gclk_byp_int),

							  .bw_pll_2xclk(cmp_gclk_byp_pre));



  

     bw_ctu_clk_sync_mux u_ctu_clsp_clkgn_mux(

					      .cmp_gclk_byp(cmp_gclk_byp_inv),
					      .dram_gclk_byp(dram_gclk_byp_inv),
					      .jbus_gclk_byp(jbus_gclk_byp_inv),
					      .cmp_gclk_out(cmp_gclk_out),
					      .dram_gclk_out(dram_gclk_out),
					      .jbus_gclk_out(jbus_gclk_out),
					      .jbus_gclk_dup_byp(),
					      .jbus_gclk_dup_out(jbus_gclk_dup_out),

					      .tcu_sel_jbus(jbus_clk_sel),
					      .tcu_sel_dram(dram_clk_sel),
					      .tcu_sel_cpu(cmp_clk_sel),
					      .tcu_sel_jbus_dup(1'b1),
					      .jbus_div0(jbus_div0),
					      .jbus_clk_mux_0(jbus_tst_clk),
					      .jbus_div1(jbus_div1),
					      .dram_clk_mux_0(dram_tst_clk),
					      .dram_div0(dram_div0),
					      .dram_div1(dram_div1),
					      .pll_clk_out(pll_clk_out_pre),
					      .cmp_div1(cmp_div1),
					      .cmp_div0(cmp_div0),
					      .cmp_clk_mux_0(cmp_tst_clk),
					      .pll_clk_out_l(pll_clk_out_pre_l),
					      .jbus_gclk_dupl_mux_0(1'b0),
					      .jbus_dup_div0(jbus_dup_div0),
					      .jbus_dup_div1(1'b0));




     ctu_clsp_clkgn_shadreg u_ctu_clsp_clkgn_shadreg(

						     .jsync_shadreg_rx2(jsync_shadreg_rx2[1:0]),
						     .jsync_shadreg_rx1(jsync_shadreg_rx1[1:0]),
						     .jsync_shadreg_rx0(jsync_shadreg_rx0[1:0]),
						     .jsync_shadreg_tx2(jsync_shadreg_tx2[4:0]),
						     .jsync_shadreg_tx1(jsync_shadreg_tx1[4:0]),
						     .jsync_shadreg_tx0(jsync_shadreg_tx0[4:0]),
						     .jsync_shadreg_period(jsync_shadreg_period[4:0]),
						     .jsync_shadreg_init(jsync_shadreg_init[4:0]),
						     .dsync_shadreg_rx2(dsync_shadreg_rx2[1:0]),
						     .dsync_shadreg_rx1(dsync_shadreg_rx1[1:0]),
						     .dsync_shadreg_rx0(dsync_shadreg_rx0[1:0]),
						     .dsync_shadreg_tx2(dsync_shadreg_tx2[4:0]),
						     .dsync_shadreg_tx1(dsync_shadreg_tx1[4:0]),
						     .dsync_shadreg_tx0(dsync_shadreg_tx0[4:0]),
						     .dsync_shadreg_period(dsync_shadreg_period[4:0]),
						     .dsync_shadreg_init(dsync_shadreg_init[4:0]),
						     .shadreg_cdiv_vec(shadreg_cdiv_vec[14:0]),
						     .shadreg_cdiv_0(shadreg_cdiv_0),
						     .shadreg_ddiv_vec(shadreg_ddiv_vec[14:0]),
						     .shadreg_ddiv_0(shadreg_ddiv_0),
						     .shadreg_jdiv_vec(shadreg_jdiv_vec[14:0]),
						     .shadreg_jdiv_0(shadreg_jdiv_0),
						     .cmp_grst_cl_l(cmp_grst_cl_l),
						     .cmp_dbginit_cl_l(cmp_dbginit_cl_l),
						     .a_grst_dl(a_grst_dl),
						     .a_dbginit_dl(a_dbginit_dl),
						     .de_grst_dsync_edge_dl(de_grst_dsync_edge_dl),
						     .de_grst_jsync_edge(de_grst_jsync_edge),
						     .de_dbginit_dsync_edge_dl(de_dbginit_dsync_edge_dl),
						     .de_dbginit_jsync_edge(de_dbginit_jsync_edge),
						     .coin_cnt_en(coin_cnt_en),
						     .coin_cnt_ld(coin_cnt_ld),
						     .coin_edge(coin_edge),
						     .shadreg_div_jmult(shadreg_div_jmult[9:0]),
						     .shadreg_div_dmult(shadreg_div_dmult[9:0]),
						     .shadreg_div_cmult(shadreg_div_cmult[13:0]),

						     .io_pwron_rst_l(io_pwron_rst_l),
						     .se(se),
						     .start_clk_early_jl(start_clk_early_jl),
						     .start_clk_cl(start_clk_cl),
						     .cmp_clk(cmp_clk),
						     .jbus_tx_sync(jbus_tx_sync),
						     .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
						     .a_dbginit_cl(a_dbginit_cl),
						     .de_dbginit_cl(de_dbginit_cl),
						     .de_grst_cl(de_grst_cl),
						     .a_grst_cl(a_grst_cl),
						     .dram_a_grst_cl(dram_a_grst_cl),
						     .update_shadow_cl(update_shadow_cl),
						     .jtag_ctu_bypass_mode(jtag_clsp_sel_jbus[2]),
						     .jsync_reg_rx2(jsync_reg_rx2[1:0]),
						     .jsync_reg_rx1(jsync_reg_rx1[1:0]),
						     .jsync_reg_rx0(jsync_reg_rx0[1:0]),
						     .jsync_reg_tx2(jsync_reg_tx2[4:0]),
						     .jsync_reg_tx1(jsync_reg_tx1[4:0]),
						     .jsync_reg_tx0(jsync_reg_tx0[4:0]),
						     .jsync_reg_period(jsync_reg_period[4:0]),
						     .jsync_reg_init(jsync_reg_init[4:0]),
						     .dsync_reg_rx2(dsync_reg_rx2[1:0]),
						     .dsync_reg_rx1(dsync_reg_rx1[1:0]),
						     .dsync_reg_rx0(dsync_reg_rx0[1:0]),
						     .dsync_reg_tx2(dsync_reg_tx2[4:0]),
						     .dsync_reg_tx1(dsync_reg_tx1[4:0]),
						     .dsync_reg_tx0(dsync_reg_tx0[4:0]),
						     .dsync_reg_period(dsync_reg_period[4:0]),
						     .dsync_reg_init(dsync_reg_init[4:0]),
						     .reg_div_cmult(reg_div_cmult[13:0]),
						     .reg_div_jmult(reg_div_jmult[9:0]),
						     .reg_div_dmult(reg_div_dmult[9:0]),
						     .reg_cdiv_0(reg_cdiv_0),
						     .reg_cdiv_vec(reg_cdiv_vec[14:0]),
						     .reg_ddiv_0(reg_ddiv_0),
						     .reg_ddiv_vec(reg_ddiv_vec[14:0]),
						     .reg_jdiv_0(reg_jdiv_0),
						     .reg_jdiv_vec(reg_jdiv_vec[14:0]));





endmodule