data/full_repos/permissive/450915285/Random.v
1: b'%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:10: Operator ADD expects 6 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                : ... In instance Random\n        pX <= pX + 3\'b011;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:18: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                : ... In instance Random\n                rX <= 5\'b10100;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:17: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                : ... In instance Random\n            else if (pX<2\'b10)\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:27: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                : ... In instance Random\n                rY <= 5\'b10100;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:26: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                : ... In instance Random\n           else if (pY<2\'b10)\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/Random.v:24: Operator GT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'pY\' generates 6 bits.\n                                                                : ... In instance Random\n           if(pY>469) \n                ^\n%Error: Exiting due to 6 warning(s)\n'
module Random(VGAclk,rX,rY);
  input VGAclk;
  output [9:0] rX;
  output [9:0] rY;
  reg [9:0] rX;
  reg [9:0] rY;
  reg [5:0] pX, pY = 10;
  
    always @(posedge VGAclk)
        pX <= pX + 3'b011;
    always @(posedge VGAclk)
        pY <= pY + 1'b1;
    always @(posedge VGAclk)
        begin
            if(pX> 6'b111110)
                rX <= 620;
            else if (pX<2'b10)
                rX <= 5'b10100;
            else 
                rX <= (pX * 4'b1010);
            end
    always @(posedge VGAclk)
        begin 
           if(pY>469)
                rY <= 460;
           else if (pY<2'b10)
                rY <= 5'b10100;
           else 
               rY <= (pY * 4'b1010);
           end
endmodule
module Random(VGAclk,rX,rY);

  input VGAclk;
  output [9:0] rX;
  output [9:0] rY;
  reg [9:0] rX;
  reg [9:0] rY;
  reg [5:0] pX, pY = 10;
  
    always @(posedge VGAclk)
        pX <= pX + 3'b011;
    always @(posedge VGAclk)
        pY <= pY + 1'b1;
    always @(posedge VGAclk)
        begin
            if(pX> 6'b111110)
                rX <= 620;
            else if (pX<2'b10)
                rX <= 5'b10100;
            else 
                rX <= (pX * 4'b1010);
            end
    always @(posedge VGAclk)
        begin 
           if(pY>469)
                rY <= 460;
           else if (pY<2'b10)
                rY <= 5'b10100;
           else 
               rY <= (pY * 4'b1010);
           end
endmodule