data/full_repos/permissive/452305748/L4/m_gen/m_gen.v
data/verilator_xmls/72bb5fcd-13b0-4be6-95c4-3d20c41e7a25.xml
module m_gen (clk,
              res,
              y);
    
    input clk;
    input res;
    output y;
    
    reg [3:0] d;
    assign y = d[0];
    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            d <= 4'b1111;
        end
        else begin
            d[2:0] <= d[3:1];
            d[3] = d[3] +d[0];
        end
    end
    
endmodule
module m_gen (clk,
              res,
              y);

    
    input clk;
    input res;
    output y;
    
    reg [3:0] d;
    assign y = d[0];
    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            d <= 4'b1111;
        end
        else begin
            d[2:0] <= d[3:1];
            d[3] = d[3] +d[0];
        end
    end
    
endmodule