data/full_repos/permissive/480861037/verilog/rtl/m_Top_Module_User.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480861037/verilog/rtl/m_Top_Module_User.v:52: Operator ASSIGNW expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 37 bits.\n                                                                                       : ... In instance m_Top_Module_User\n    assign io_oeb = {(MPRJ_IO_PADS-1){rst}};   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480861037/verilog/rtl/m_Top_Module_User.v:58: Operator ASSIGNW expects 128 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 133 bits.\n                                                                                       : ... In instance m_Top_Module_User\n    assign la_data_out = {{(127-BITS){1\'b0}}, io_out};  \n                       ^\n%Error: data/full_repos/permissive/480861037/verilog/rtl/m_Top_Module_User.v:65: Cannot find file containing module: \'counter\'\n    counter #(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480861037/verilog/rtl,data/full_repos/permissive/480861037/counter\n             data/full_repos/permissive/480861037/verilog/rtl,data/full_repos/permissive/480861037/counter.v\n             data/full_repos/permissive/480861037/verilog/rtl,data/full_repos/permissive/480861037/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module m_Top_Module_User
#(
    parameter BITS = 32,
	 parameter MPRJ_IO_PADS = 38
)
(

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wire wb_clk_i,
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,


    input  wire [127:0] la_data_in,
    output wire [127:0] la_data_out,
    input  wire [127:0] la_oenb,


    input wire [MPRJ_IO_PADS-1:0] io_in,
    output wire [MPRJ_IO_PADS-1:0] io_out,
    output wire [MPRJ_IO_PADS-1:0] io_oeb,


    output wire [2:0] irq
);
    wire clk;
    wire rst;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i;
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};


    assign io_oeb = {(MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, io_out};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;

    counter #(
        .BITS(BITS)
    ) counter(
        .clk(clk),
        .reset(rst),
		  .clk_enb(la_oenb[66]),
        .ready(wbs_ack_o),
        .valid(valid),
        .rdata(wbs_dat_o),
        .wdata(wbs_dat_i),
        .wstrb(wstrb),
        .la_write(la_write),
        .la_input(la_data_in[63:32]),
        .count(io_out)
    );

endmodule
module m_Top_Module_User
#(
    parameter BITS = 32,
	 parameter MPRJ_IO_PADS = 38
)
(

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wire wb_clk_i,
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,


    input  wire [127:0] la_data_in,
    output wire [127:0] la_data_out,
    input  wire [127:0] la_oenb,


    input wire [MPRJ_IO_PADS-1:0] io_in,
    output wire [MPRJ_IO_PADS-1:0] io_out,
    output wire [MPRJ_IO_PADS-1:0] io_oeb,


    output wire [2:0] irq
);

    wire clk;
    wire rst;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i;
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};


    assign io_oeb = {(MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, io_out};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;

    counter #(
        .BITS(BITS)
    ) counter(
        .clk(clk),
        .reset(rst),
		  .clk_enb(la_oenb[66]),
        .ready(wbs_ack_o),
        .valid(valid),
        .rdata(wbs_dat_o),
        .wdata(wbs_dat_i),
        .wstrb(wstrb),
        .la_write(la_write),
        .la_input(la_data_in[63:32]),
        .count(io_out)
    );

endmodule