data/full_repos/permissive/437303189/src/sar_and_tmu/timing_management_unit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/437303189/src/sar_and_tmu/timing_management_unit.v:18: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'counter_in\' generates 13 bits.\n                                                                                                : ... In instance timing_management_unit\n        if (rst || !counter_in)\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437303189/src/sar_and_tmu/timing_management_unit.v:25: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'counter_in\' generates 13 bits.\n                                                                                                : ... In instance timing_management_unit\n        if (rst || !counter_in || counter_in < 1 << LOW_COUNT)\n                   ^\n%Error: Exiting due to 2 warning(s)\n'
module timing_management_unit #(
    parameter HIGH_COUNT = 1,
    parameter LOW_COUNT = 12
) (
    input rst,
    input clk_in,
    output reg clk_out
);

    parameter COUNTER_LAST_BIT_INDEX = HIGH_COUNT + LOW_COUNT - 1;
    
    reg [COUNTER_LAST_BIT_INDEX : 0] reg_counter;

    wire [COUNTER_LAST_BIT_INDEX : 0] counter_in = reg_counter << 1;

    always @(posedge clk_in) begin
        if (rst || !counter_in)
            reg_counter <= 1;
        else 
            reg_counter <= counter_in;
    end

    always @(posedge clk_in) begin
        if (rst || !counter_in || counter_in < 1 << LOW_COUNT)
            clk_out <= 0;
        else
            clk_out <= 1;
    end
    
endmodule
module timing_management_unit #(
    parameter HIGH_COUNT = 1,
    parameter LOW_COUNT = 12
) (
    input rst,
    input clk_in,
    output reg clk_out
);


    parameter COUNTER_LAST_BIT_INDEX = HIGH_COUNT + LOW_COUNT - 1;
    
    reg [COUNTER_LAST_BIT_INDEX : 0] reg_counter;

    wire [COUNTER_LAST_BIT_INDEX : 0] counter_in = reg_counter << 1;

    always @(posedge clk_in) begin
        if (rst || !counter_in)
            reg_counter <= 1;
        else 
            reg_counter <= counter_in;
    end

    always @(posedge clk_in) begin
        if (rst || !counter_in || counter_in < 1 << LOW_COUNT)
            clk_out <= 0;
        else
            clk_out <= 1;
    end
    
endmodule