data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_DECODE_16U_3_4.v
data/verilator_xmls/f55a4487-7d65-4af8-b803-2aca5bf5c9ee.xml
module dut_DECODE_16U_3_4 (
	in1,
	out1
	);
input [3:0] in1;
output [15:0] out1;
wire [15:0] asc001;

assign asc001 = 16'B0000000000000001 << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_16U_3_4 (
	in1,
	out1
	);

input [3:0] in1;
output [15:0] out1;
wire [15:0] asc001;

assign asc001 = 16'B0000000000000001 << in1;

assign out1 = asc001;
endmodule