data/full_repos/permissive/463439324/decap/encode_rp.v
1: b'%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:31: Cannot find include file: params.v\n`include "params.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/params.v\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/params.v.v\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/params.v.sv\n             params.v\n             params.v.v\n             params.v.sv\n             obj_dir/params.v\n             obj_dir/params.v.v\n             obj_dir/params.v.sv\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:47: Define or directive not defined: \'`RP_DEPTH\'\n    output      [`RP_DEPTH-1:0]     rp_rd_addr;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:48: Define or directive not defined: \'`RP_D_SIZE\'\n    input       [`RP_D_SIZE-1:0]    rp_rd_data;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:49: Define or directive not defined: \'`OUT_DEPTH\'\n    output reg  [`OUT_DEPTH-1:0]    cd_wr_addr;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:50: Define or directive not defined: \'`OUT_D_SIZE\'\n    output      [`OUT_D_SIZE-1:0]   cd_wr_data;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:55: Define or directive not defined: \'`RP_DEPTH\'\n    input       [`RP_DEPTH-1:0]     param_r_max;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:56: Define or directive not defined: \'`RP_D_SIZE\'\n    input       [`RP_D_SIZE-1:0]    param_m0;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:62: Define or directive not defined: \'`RP_DEPTH\'\n    reg         [`RP_DEPTH-2:0]     rb_wr_addr;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:63: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    rb_wr_data;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:64: Define or directive not defined: \'`RP_DEPTH\'\n    wire        [`RP_DEPTH-2:0]     rb_rd_addr;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:65: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    rb_rd_data;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:73: Define or directive not defined: \'`RP_D_SIZE\'\n    reg         [`RP_D_SIZE-1:0]    r0[2:0];\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:74: Define or directive not defined: \'`RP_D_SIZE\'\n    reg         [`RP_D_SIZE-1:0]    r1[1:0];\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:76: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    r0_l;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:77: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    r1_l;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:78: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    r0_s;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:79: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    r1_s;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:84: Define or directive not defined: \'`RP_D_SIZE2\'\n    wire        [`RP_D_SIZE2-1:0]   r1m0_r0;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:85: Define or directive not defined: \'`RP_D_SIZE2\'\n    reg         [`RP_D_SIZE2-1:0]   r_next;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:95: Define or directive not defined: \'`RP_DEPTH\'\n    reg         [`RP_DEPTH-1:0]     r_rd_addr;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:96: Define or directive not defined: \'`RP_DEPTH\'\n    wire        [`RP_DEPTH-1:0]     r_rd_diff;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:98: Define or directive not defined: \'`RP_D_SIZE\'\n    wire        [`RP_D_SIZE-1:0]    r_data;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:99: Define or directive not defined: \'`OUT_DEPTH\'\n    reg         [`OUT_DEPTH-1:0]    o_addr;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:100: Define or directive not defined: \'`OUT_D_SIZE\'\n    wire        [`OUT_D_SIZE-1:0]   o_data;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:102: Define or directive not defined: \'`RP_D_SIZE\'\n    bram_n # ( .D_SIZE(`RP_D_SIZE), .Q_DEPTH(`RP_DEPTH-1) ) r_buffer (\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:102: Define or directive not defined: \'`RP_DEPTH\'\n    bram_n # ( .D_SIZE(`RP_D_SIZE), .Q_DEPTH(`RP_DEPTH-1) ) r_buffer (\n                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:164: Define or directive not defined: \'`RP_DEPTH_2\'\n    assign rb_rd_addr = r_rd_addr[0 +: `RP_DEPTH_2];\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:164: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rb_rd_addr = r_rd_addr[0 +: `RP_DEPTH_2];\n                                                  ^\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:173: Define or directive not defined: \'`RP_DEPTH\'\n            r_rd_addr <= { `RP_DEPTH {1\'b0} };\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:177: Define or directive not defined: \'`RP_DEPTH\'\n                    r_rd_addr <= { `RP_DEPTH {1\'b0} };\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:181: Define or directive not defined: \'`RP_DEPTH_2\'\n                    r_rd_addr <= r_rd_addr + { { `RP_DEPTH_2 {1\'b0} }, 1\'b1 };\n                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:189: Define or directive not defined: \'`RP_D_SIZE\'\n            r0[2] <= { `RP_D_SIZE {1\'b0} };\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:190: Define or directive not defined: \'`RP_D_SIZE\'\n            r0[1] <= { `RP_D_SIZE {1\'b0} };\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:191: Define or directive not defined: \'`RP_D_SIZE\'\n            r0[0] <= { `RP_D_SIZE {1\'b0} };\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:192: Define or directive not defined: \'`RP_D_SIZE\'\n            r1[1] <= { `RP_D_SIZE {1\'b0} };\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:193: Define or directive not defined: \'`RP_D_SIZE\'\n            r1[0] <= { `RP_D_SIZE {1\'b0} };\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:201: Define or directive not defined: \'`RP_D_SIZE\'\n                r1[1] <= (~r_rd_end || ~param_r_max[0]) ? r_data : { `RP_D_SIZE {1\'b0} };\n                                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:215: Define or directive not defined: \'`RP_D_SIZE2\'\n            r_next <= { `RP_D_SIZE2 {1\'b0} };\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:220: Define or directive not defined: \'`RP_D_SIZE2\'\n                r_next <= { 8\'b0, r_next[8 +: (`RP_D_SIZE2 - 8)] };\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:225: Define or directive not defined: \'`RP_DEPTH\'\n    assign r_m0m1_next = param_r_max[0] ? ~|r_rd_diff[1 +: (`RP_DEPTH-1)] : (~|r_rd_diff[2 +: (`RP_DEPTH-2)] && ~&r_rd_diff[1:0]) ;\n                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:225: Define or directive not defined: \'`RP_DEPTH\'\n    assign r_m0m1_next = param_r_max[0] ? ~|r_rd_diff[1 +: (`RP_DEPTH-1)] : (~|r_rd_diff[2 +: (`RP_DEPTH-2)] && ~&r_rd_diff[1:0]) ;\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:260: Define or directive not defined: \'`OUT_DEPTH\'\n            cd_wr_addr <= { `OUT_DEPTH { 1\'b0 } };\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:263: Define or directive not defined: \'`OUT_DEPTH\'\n                cd_wr_addr <= cd_wr_addr + { { (`OUT_DEPTH - 1) {1\'b0} }, 1\'b1 };\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:273: Define or directive not defined: \'`RP_DEPTH\'\n            rb_wr_addr <= { (`RP_DEPTH-1) { 1\'b0 } };\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:277: Define or directive not defined: \'`RP_DEPTH\'\n                    rb_wr_addr <= { (`RP_DEPTH-1) { 1\'b0 } };\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/encode_rp.v:279: Define or directive not defined: \'`RP_DEPTH\'\n                    rb_wr_addr <= rb_wr_addr + { { (`RP_DEPTH - 2) {1\'b0} }, 1\'b1 };\n                                                    ^~~~~~~~~\n%Error: Exiting due to 46 error(s)\n'
module encode_rp ( clk, start, done, state_l, state_s,
    rp_rd_addr, rp_rd_data,
    cd_wr_addr, cd_wr_data, cd_wr_en,
    state_max,
    param_r_max, param_m0, param_1st_round,
    param_outs1, param_outsl
) ; 

    input                           clk;
    input                           start;
    output                          done;
    output      [4:0]               state_l;
    output      [4:0]               state_s;

    output      [`RP_DEPTH-1:0]     rp_rd_addr;
    input       [`RP_D_SIZE-1:0]    rp_rd_data;
    output reg  [`OUT_DEPTH-1:0]    cd_wr_addr;
    output      [`OUT_D_SIZE-1:0]   cd_wr_data;
    output                          cd_wr_en;

    input       [4:0]               state_max;

    input       [`RP_DEPTH-1:0]     param_r_max;
    input       [`RP_D_SIZE-1:0]    param_m0;
    input                           param_1st_round;
    input       [2:0]               param_outs1;
    input       [2:0]               param_outsl;

    wire                            rb_wr_en;
    reg         [`RP_DEPTH-2:0]     rb_wr_addr;
    wire        [`RP_D_SIZE-1:0]    rb_wr_data;
    wire        [`RP_DEPTH-2:0]     rb_rd_addr;
    wire        [`RP_D_SIZE-1:0]    rb_rd_data;

    reg         [4:0]               state[4:0];
    wire        [4:0]               state_l1;
    wire        [4:0]               state_s1;
    reg         [4:0]               state_next;
    reg         [1:0]               state_counter[3:0];

    reg         [`RP_D_SIZE-1:0]    r0[2:0];
    reg         [`RP_D_SIZE-1:0]    r1[1:0];

    wire        [`RP_D_SIZE-1:0]    r0_l;
    wire        [`RP_D_SIZE-1:0]    r1_l;
    wire        [`RP_D_SIZE-1:0]    r0_s;
    wire        [`RP_D_SIZE-1:0]    r1_s;
    wire        [1:0]               sc_l;
    wire        [1:0]               sc_s;


    wire        [`RP_D_SIZE2-1:0]   r1m0_r0;
    reg         [`RP_D_SIZE2-1:0]   r_next;

    reg         [2:0]               starts;

    reg         [2:0]               out_counter;

    wire                            r_m0m1_next;
    reg         [3:0]               r_m0m1;
    wire                            rl_s;

    reg         [`RP_DEPTH-1:0]     r_rd_addr;
    wire        [`RP_DEPTH-1:0]     r_rd_diff;
    wire                            r_rd_end;
    wire        [`RP_D_SIZE-1:0]    r_data;
    reg         [`OUT_DEPTH-1:0]    o_addr;
    wire        [`OUT_D_SIZE-1:0]   o_data;

    bram_n # ( .D_SIZE(`RP_D_SIZE), .Q_DEPTH(`RP_DEPTH-1) ) r_buffer (
        .clk(clk),
        .wr_en(rb_wr_en),
        .wr_addr(rb_wr_addr),
        .wr_din(rb_wr_data),
        .rd_addr(rb_rd_addr),
        .rd_dout(rb_rd_data)
    ) ;

    always @ ( posedge clk ) begin
        if(start) begin
            state[4] <= 5'd0;
            state[3] <= 5'd0;
            state[2] <= 5'd0;
            state[1] <= 5'd0;
            state[0] <= 5'd0;
        end else begin
            state[4] <= state_next;
            state[3] <= state[4];
            state[2] <= state[3];
            state[1] <= state[2];
            state[0] <= state[1];
        end
    end
    assign state_l = state[4];
    assign state_l1 = state[3];
    assign state_s = state[1];
    assign state_s1 = state[0];

    assign done = (state_l == 5'd31);

    always @ (*) begin
        if( r_rd_end && ~|sc_l ) begin
            if(state_l == state_max || done) begin
                state_next = 5'd31;
            end else begin
                state_next = state_l + 5'd1;
            end
        end else begin
            state_next = state_l;
        end
    end

    always @ ( posedge clk ) begin
        if(start || ~|(state_counter[3])) begin
            state_counter[3] <= 2'd2;
        end else begin
            state_counter[3] <= state_counter[3] - 2'd1;
        end
        if(start) begin
            state_counter[2] <= 2'd2;
            state_counter[1] <= 2'd2;
            state_counter[0] <= 2'd2;
        end else begin
            state_counter[2] <= state_counter[3];
            state_counter[1] <= state_counter[2];
            state_counter[0] <= state_counter[1];
        end
    end
    assign sc_l = state_counter[3];
    assign sc_s = state_counter[0];

    assign rb_rd_addr = r_rd_addr[0 +: `RP_DEPTH_2];
    assign rp_rd_addr = r_rd_addr;
    assign r_data = param_1st_round ? rp_rd_data : rb_rd_data; 

    assign r_rd_diff = param_r_max - r_rd_addr;
    assign r_rd_end = ~|r_rd_diff;

    always @ ( posedge clk ) begin
        if(start) begin
            r_rd_addr <= { `RP_DEPTH {1'b0} };
        end else begin
            if(r_rd_end) begin
                if(~|sc_l) begin
                    r_rd_addr <= { `RP_DEPTH {1'b0} };
                end
            end else begin
                if(|sc_l) begin
                    r_rd_addr <= r_rd_addr + { { `RP_DEPTH_2 {1'b0} }, 1'b1 };
                end
            end
        end
    end

    always @ ( posedge clk ) begin
        if(start) begin
            r0[2] <= { `RP_D_SIZE {1'b0} };
            r0[1] <= { `RP_D_SIZE {1'b0} };
            r0[0] <= { `RP_D_SIZE {1'b0} };
            r1[1] <= { `RP_D_SIZE {1'b0} };
            r1[0] <= { `RP_D_SIZE {1'b0} };
        end else begin
            if(sc_l == 2'd2 && ~&state_s) begin
                r0[2] <= r_data;
            end
            r0[1] <= r0[2];
            r0[0] <= r0[1];
            if(sc_l == 2'd1) begin
                r1[1] <= (~r_rd_end || ~param_r_max[0]) ? r_data : { `RP_D_SIZE {1'b0} };
            end
            r1[0] <= r1[1];
        end
    end
    assign r0_l = r0[2];
    assign r0_s = r0[0];
    assign r1_l = r1[1];
    assign r1_s = r1[0];

    assign r1m0_r0 = r1_s * param_m0 + r0_s;

    always @ ( posedge clk ) begin
        if(start) begin
            r_next <= { `RP_D_SIZE2 {1'b0} };
        end else begin
            if(sc_s == 2'd2 && ~&state_s) begin
                r_next <= r1m0_r0;
            end else begin
                r_next <= { 8'b0, r_next[8 +: (`RP_D_SIZE2 - 8)] };
            end
        end
    end

    assign r_m0m1_next = param_r_max[0] ? ~|r_rd_diff[1 +: (`RP_DEPTH-1)] : (~|r_rd_diff[2 +: (`RP_DEPTH-2)] && ~&r_rd_diff[1:0]) ;

    always @ ( posedge clk ) begin
        if(start) begin
            r_m0m1 <= 4'b0;
        end else begin
            r_m0m1[2] <= r_m0m1_next;
            r_m0m1[1] <= r_m0m1[2];
            r_m0m1[0] <= r_m0m1[1];
        end
    end
    assign rl_s = r_m0m1[0];

    always @ ( posedge clk ) begin
        starts <= { start, starts[2:1] };
    end

    always @ ( posedge clk ) begin
        if(starts[0]) begin
            out_counter <= 3'd6;
        end else begin
            if(sc_s == 2'd2 && ~&state_s) begin
                out_counter <= rl_s ? param_outsl : param_outs1;
            end else begin
                if(~out_counter[2] || &out_counter) begin
                    out_counter <= out_counter - 3'd1;
                end
            end
        end
    end

    assign cd_wr_en = ~out_counter[2];
    assign cd_wr_data = r_next[7:0];
    always @ ( posedge clk ) begin
        if(start) begin
            cd_wr_addr <= { `OUT_DEPTH { 1'b0 } };
        end else begin
            if(cd_wr_en) begin
                cd_wr_addr <= cd_wr_addr + { { (`OUT_DEPTH - 1) {1'b0} }, 1'b1 };
            end
        end
    end

    assign rb_wr_en = &out_counter;
    assign rb_wr_data = r_next[13:0];

    always @ ( posedge clk ) begin
        if(start) begin
            rb_wr_addr <= { (`RP_DEPTH-1) { 1'b0 } };
        end else begin
            if(rb_wr_en) begin
                if(state_l1 != state_s1) begin
                    rb_wr_addr <= { (`RP_DEPTH-1) { 1'b0 } };
                end else begin 
                    rb_wr_addr <= rb_wr_addr + { { (`RP_DEPTH - 2) {1'b0} }, 1'b1 };
                end
            end
        end
    end

endmodule
module encode_rp ( clk, start, done, state_l, state_s,
    rp_rd_addr, rp_rd_data,
    cd_wr_addr, cd_wr_data, cd_wr_en,
    state_max,
    param_r_max, param_m0, param_1st_round,
    param_outs1, param_outsl
) ;
 

    input                           clk;
    input                           start;
    output                          done;
    output      [4:0]               state_l;
    output      [4:0]               state_s;

    output      [`RP_DEPTH-1:0]     rp_rd_addr;
    input       [`RP_D_SIZE-1:0]    rp_rd_data;
    output reg  [`OUT_DEPTH-1:0]    cd_wr_addr;
    output      [`OUT_D_SIZE-1:0]   cd_wr_data;
    output                          cd_wr_en;

    input       [4:0]               state_max;

    input       [`RP_DEPTH-1:0]     param_r_max;
    input       [`RP_D_SIZE-1:0]    param_m0;
    input                           param_1st_round;
    input       [2:0]               param_outs1;
    input       [2:0]               param_outsl;

    wire                            rb_wr_en;
    reg         [`RP_DEPTH-2:0]     rb_wr_addr;
    wire        [`RP_D_SIZE-1:0]    rb_wr_data;
    wire        [`RP_DEPTH-2:0]     rb_rd_addr;
    wire        [`RP_D_SIZE-1:0]    rb_rd_data;

    reg         [4:0]               state[4:0];
    wire        [4:0]               state_l1;
    wire        [4:0]               state_s1;
    reg         [4:0]               state_next;
    reg         [1:0]               state_counter[3:0];

    reg         [`RP_D_SIZE-1:0]    r0[2:0];
    reg         [`RP_D_SIZE-1:0]    r1[1:0];

    wire        [`RP_D_SIZE-1:0]    r0_l;
    wire        [`RP_D_SIZE-1:0]    r1_l;
    wire        [`RP_D_SIZE-1:0]    r0_s;
    wire        [`RP_D_SIZE-1:0]    r1_s;
    wire        [1:0]               sc_l;
    wire        [1:0]               sc_s;


    wire        [`RP_D_SIZE2-1:0]   r1m0_r0;
    reg         [`RP_D_SIZE2-1:0]   r_next;

    reg         [2:0]               starts;

    reg         [2:0]               out_counter;

    wire                            r_m0m1_next;
    reg         [3:0]               r_m0m1;
    wire                            rl_s;

    reg         [`RP_DEPTH-1:0]     r_rd_addr;
    wire        [`RP_DEPTH-1:0]     r_rd_diff;
    wire                            r_rd_end;
    wire        [`RP_D_SIZE-1:0]    r_data;
    reg         [`OUT_DEPTH-1:0]    o_addr;
    wire        [`OUT_D_SIZE-1:0]   o_data;

    bram_n # ( .D_SIZE(`RP_D_SIZE), .Q_DEPTH(`RP_DEPTH-1) ) r_buffer (
        .clk(clk),
        .wr_en(rb_wr_en),
        .wr_addr(rb_wr_addr),
        .wr_din(rb_wr_data),
        .rd_addr(rb_rd_addr),
        .rd_dout(rb_rd_data)
    ) ;

    always @ ( posedge clk ) begin
        if(start) begin
            state[4] <= 5'd0;
            state[3] <= 5'd0;
            state[2] <= 5'd0;
            state[1] <= 5'd0;
            state[0] <= 5'd0;
        end else begin
            state[4] <= state_next;
            state[3] <= state[4];
            state[2] <= state[3];
            state[1] <= state[2];
            state[0] <= state[1];
        end
    end
    assign state_l = state[4];
    assign state_l1 = state[3];
    assign state_s = state[1];
    assign state_s1 = state[0];

    assign done = (state_l == 5'd31);

    always @ (*) begin
        if( r_rd_end && ~|sc_l ) begin
            if(state_l == state_max || done) begin
                state_next = 5'd31;
            end else begin
                state_next = state_l + 5'd1;
            end
        end else begin
            state_next = state_l;
        end
    end

    always @ ( posedge clk ) begin
        if(start || ~|(state_counter[3])) begin
            state_counter[3] <= 2'd2;
        end else begin
            state_counter[3] <= state_counter[3] - 2'd1;
        end
        if(start) begin
            state_counter[2] <= 2'd2;
            state_counter[1] <= 2'd2;
            state_counter[0] <= 2'd2;
        end else begin
            state_counter[2] <= state_counter[3];
            state_counter[1] <= state_counter[2];
            state_counter[0] <= state_counter[1];
        end
    end
    assign sc_l = state_counter[3];
    assign sc_s = state_counter[0];

    assign rb_rd_addr = r_rd_addr[0 +: `RP_DEPTH_2];
    assign rp_rd_addr = r_rd_addr;
    assign r_data = param_1st_round ? rp_rd_data : rb_rd_data; 

    assign r_rd_diff = param_r_max - r_rd_addr;
    assign r_rd_end = ~|r_rd_diff;

    always @ ( posedge clk ) begin
        if(start) begin
            r_rd_addr <= { `RP_DEPTH {1'b0} };
        end else begin
            if(r_rd_end) begin
                if(~|sc_l) begin
                    r_rd_addr <= { `RP_DEPTH {1'b0} };
                end
            end else begin
                if(|sc_l) begin
                    r_rd_addr <= r_rd_addr + { { `RP_DEPTH_2 {1'b0} }, 1'b1 };
                end
            end
        end
    end

    always @ ( posedge clk ) begin
        if(start) begin
            r0[2] <= { `RP_D_SIZE {1'b0} };
            r0[1] <= { `RP_D_SIZE {1'b0} };
            r0[0] <= { `RP_D_SIZE {1'b0} };
            r1[1] <= { `RP_D_SIZE {1'b0} };
            r1[0] <= { `RP_D_SIZE {1'b0} };
        end else begin
            if(sc_l == 2'd2 && ~&state_s) begin
                r0[2] <= r_data;
            end
            r0[1] <= r0[2];
            r0[0] <= r0[1];
            if(sc_l == 2'd1) begin
                r1[1] <= (~r_rd_end || ~param_r_max[0]) ? r_data : { `RP_D_SIZE {1'b0} };
            end
            r1[0] <= r1[1];
        end
    end
    assign r0_l = r0[2];
    assign r0_s = r0[0];
    assign r1_l = r1[1];
    assign r1_s = r1[0];

    assign r1m0_r0 = r1_s * param_m0 + r0_s;

    always @ ( posedge clk ) begin
        if(start) begin
            r_next <= { `RP_D_SIZE2 {1'b0} };
        end else begin
            if(sc_s == 2'd2 && ~&state_s) begin
                r_next <= r1m0_r0;
            end else begin
                r_next <= { 8'b0, r_next[8 +: (`RP_D_SIZE2 - 8)] };
            end
        end
    end

    assign r_m0m1_next = param_r_max[0] ? ~|r_rd_diff[1 +: (`RP_DEPTH-1)] : (~|r_rd_diff[2 +: (`RP_DEPTH-2)] && ~&r_rd_diff[1:0]) ;

    always @ ( posedge clk ) begin
        if(start) begin
            r_m0m1 <= 4'b0;
        end else begin
            r_m0m1[2] <= r_m0m1_next;
            r_m0m1[1] <= r_m0m1[2];
            r_m0m1[0] <= r_m0m1[1];
        end
    end
    assign rl_s = r_m0m1[0];

    always @ ( posedge clk ) begin
        starts <= { start, starts[2:1] };
    end

    always @ ( posedge clk ) begin
        if(starts[0]) begin
            out_counter <= 3'd6;
        end else begin
            if(sc_s == 2'd2 && ~&state_s) begin
                out_counter <= rl_s ? param_outsl : param_outs1;
            end else begin
                if(~out_counter[2] || &out_counter) begin
                    out_counter <= out_counter - 3'd1;
                end
            end
        end
    end

    assign cd_wr_en = ~out_counter[2];
    assign cd_wr_data = r_next[7:0];
    always @ ( posedge clk ) begin
        if(start) begin
            cd_wr_addr <= { `OUT_DEPTH { 1'b0 } };
        end else begin
            if(cd_wr_en) begin
                cd_wr_addr <= cd_wr_addr + { { (`OUT_DEPTH - 1) {1'b0} }, 1'b1 };
            end
        end
    end

    assign rb_wr_en = &out_counter;
    assign rb_wr_data = r_next[13:0];

    always @ ( posedge clk ) begin
        if(start) begin
            rb_wr_addr <= { (`RP_DEPTH-1) { 1'b0 } };
        end else begin
            if(rb_wr_en) begin
                if(state_l1 != state_s1) begin
                    rb_wr_addr <= { (`RP_DEPTH-1) { 1'b0 } };
                end else begin 
                    rb_wr_addr <= rb_wr_addr + { { (`RP_DEPTH - 2) {1'b0} }, 1'b1 };
                end
            end
        end
    end

endmodule