data/full_repos/permissive/460600765/rtl/fifo.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:55: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_empty_o     <= (tail == ADDR_LEN\'(head + 1));\n                                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:56: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 2)) || (tail == ADDR_LEN\'(head + 1));\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:56: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 2)) || (tail == ADDR_LEN\'(head + 1));\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:59: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 1)) || (tail == head);\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:65: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_full_o     <= (head == ADDR_LEN\'(tail + 2));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:66: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 3)) || (head == ADDR_LEN\'(tail + 2));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:66: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 3)) || (head == ADDR_LEN\'(tail + 2));\n                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:68: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_full_o     <= (head == ADDR_LEN\'(tail + 1));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:69: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 2)) || (head == ADDR_LEN\'(tail + 1));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:69: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 2)) || (head == ADDR_LEN\'(tail + 1));\n                                                                                          ^\n%Error: Exiting due to 10 warning(s)\n'
module bram2 #(
    parameter W_A = 10,
    parameter W_D = 32
) (
    input  wire logic clk,


    input  wire logic [W_A-1:0] addr0_i,
    input  wire logic [W_D-1:0] d0_i,
    input  wire logic           we0_i,
    output      logic [W_D-1:0] q0_o,


    input  wire logic [W_A-1:0] addr1_i,
    input  wire logic [W_D-1:0] d1_i,
    input  wire logic           we1_i,
    output      logic [W_D-1:0] q1_o
);
    localparam LEN = 2 ** W_A;

    logic [W_A-1:0] d_addr0;
    logic [W_A-1:0] d_addr1;
    logic [W_D-1:0] mem[0:LEN-1];

    always_ff @(posedge clk) begin
        if (we0_i)
            mem[addr0_i] <= d0_i;
        d_addr0 <= addr0_i;
    end

    always_ff @(posedge clk) begin
        if (we1_i)
            mem[addr1_i] <= d1_i;
        d_addr1 <= addr1_i;
    end

    assign q0_o = mem[d_addr0];
    assign q1_o = mem[d_addr1];

endmodule
module bram2 #(
    parameter W_A = 10,
    parameter W_D = 32
) (
    input  wire logic clk,


    input  wire logic [W_A-1:0] addr0_i,
    input  wire logic [W_D-1:0] d0_i,
    input  wire logic           we0_i,
    output      logic [W_D-1:0] q0_o,


    input  wire logic [W_A-1:0] addr1_i,
    input  wire logic [W_D-1:0] d1_i,
    input  wire logic           we1_i,
    output      logic [W_D-1:0] q1_o
);

    localparam LEN = 2 ** W_A;

    logic [W_A-1:0] d_addr0;
    logic [W_A-1:0] d_addr1;
    logic [W_D-1:0] mem[0:LEN-1];

    always_ff @(posedge clk) begin
        if (we0_i)
            mem[addr0_i] <= d0_i;
        d_addr0 <= addr0_i;
    end

    always_ff @(posedge clk) begin
        if (we1_i)
            mem[addr1_i] <= d1_i;
        d_addr1 <= addr1_i;
    end

    assign q0_o = mem[d_addr0];
    assign q1_o = mem[d_addr1];

endmodule