data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/microprogrammed_controller_46.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/microprogrammed_controller_46.v:163: Little bit endian vector: MSB < LSB of bit range: 1:62\n    output [1:62]   tp_state,        \n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/microprogrammed_controller_46.v:255: Little bit endian vector: MSB < LSB of bit range: 1:62\n    reg [1:62]  state, next;\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module microprogrammed_controller_46 #(
    parameter   UseASM = 1
)
(

    output reg      JSB,
    output reg      BRH,
    output reg      PTONLY,
    output reg      UP2PT,
    output reg      ARITHW,
    output reg      ISTW,
    output reg      STDECN,
    output reg      SST,
    output reg      RST,
    output reg      IST,
    output reg      SPT,
    output reg      IPTR,
    output reg      IPTS,
    output reg      PTD,
    output reg      PTI,
    output reg      TKR,
    output reg      RET,
    output [1:62]   tp_state,

    input           PHI2,

    input           pwor,
    input           IS,
    input           b5,
    input           b14,
    input           b26,
    input           b45,
    input           b55,




    always @ (posedge PHI2 or posedge pwor) begin : proc_state_reg
        if (pwor) begin
            state           <= 'b0;
            state[sIdle]    <= 1'b1;
        end
        else state <= next;
    end


    always @* begin : proc_next_comb
        next    = 'b0;
        JSB     = 1'b0;
        BRH     = 1'b0;
        PTONLY  = 1'b0;
        UP2PT   = 1'b0;
        ARITHW  = 1'b0;
        STDECN  = 1'b0;
        SST     = 1'b0;
        RST     = 1'b0;
        ISTW    = 1'b0;
        IST     = 1'b0;
        SPT     = 1'b0;
        IPTR    = 1'b0;
        IPTS    = 1'b0;
        PTD     = 1'b0;
        PTI     = 1'b0;
        TKR     = 1'b0;
        RET     = 1'b0;

        case (1'b1)

            state[sIdle]        :   if (b45)
                                        if (IS)             next[s1x]           = 1'b1; 
                                        else                next[s0x]           = 1'b1;
                                    else                    next[sIdle]         = 1'b1;
            state[s0x]          :   if (IS)                 next[s01x]          = 1'b1;
                                    else                    next[s00x]          = 1'b1;
            state[s00x]         :   if (IS)                 next[s001x]         = 1'b1;
                                    else                    next[s000x]         = 1'b1;
            state[s001x]        :   if (IS)                 next[s0011x]        = 1'b1;
                                    else                    next[s0010x]        = 1'b1;
            state[s000x]        :   if (IS)                 next[s0001x]        = 1'b1;
                                    else                    next[s0000x]        = 1'b1;
            state[s0000x]       :   if (IS)                 next[sType6]        = 1'b1;
                                    else                    next[sNop]          = 1'b1;
            state[sNop]         :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sNop]          = 1'b1;
            state[sAddrOut]     :   if (b26)                next[sIdle]         = 1'b1;
                                    else                    next[sAddrOut]      = 1'b1;

            state[s1x]          :   if (IS)                 next[sBrhWait]      = 1'b1;
                                    else                    next[sJsb]          = 1'b1;
            state[sJsb]         :   begin
                                        JSB = 1'b1;         
                                        if (b54)            next[sJsbWait]      = 1'b1;
                                        else                next[sJsb]          = 1'b1;
                                    end                     
            state[sJsbWait]     :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sJsbWait]      = 1'b1;
            state[sBrhWait]     :   if (b18)
                                        if (CARRY_FF)       next[sAddrOut]      = 1'b1;
                                        else                next[sBrhOut]       = 1'b1;
                                    else                    next[sBrhWait]      = 1'b1;
            state[sBrhOut]      :   begin
                                        BRH = 1'b1;         
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sBrhOut]       = 1'b1;
                                    end

            state[s01x]         :   if (IS)                 next[sArithWait]    = 1'b1;
                                    else                    next[s010x]         = 1'b1;
            state[s010x]        :   if (IS)                 next[sArithWait]    = 1'b1;
                                    else                    next[s0100x]        = 1'b1;
            state[s0100x]       :   if (IS)                 next[sArithWP]      = 1'b1;
                                    else                    next[sArithP]       = 1'b1;      
            state[sArithP]      :   begin
                                        PTONLY = 1'b1;      
                                        if (b54)            next[sArithWait]    = 1'b1;   
                                        else                next[sArithP]       = 1'b1;
                                    end                     
            state[sArithWP]     :   begin
                                        UP2PT = 1'b1;       
                                        if (b54)            next[sArithWait]    = 1'b1;   
                                        else                next[sArithWP]      = 1'b1;
                                    end                     
            state[sArithWait]   :   begin
                                        ARITHW = 1'b1;      
                                        if (b18)            next[sAddrOut]      = 1'b1;
                                        else                next[sArithWait]    = 1'b1;
                                    end                     

            state[s0010x]       :   if (IS)                 next[s00101x]       = 1'b1;
                                    else                    next[s00100x]       = 1'b1;
            state[s00100x]      :   if (IS)                 next[sRst]          = 1'b1;
                                    else                    next[sSst]          = 1'b1;
            state[sSst]         :   if (b5)                 next[sSstDecr]      = 1'b1;
                                    else                    next[sSst]          = 1'b1;
            state[sSstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sSstThis]      = 1'b1;     
                                        else                next[sSstDecr]      = 1'b1;
                                    end                     
            state[sSstThis]     :   begin
                                        SST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     

            state[sRst]         :   if (b5)                 next[sRstDecr]      = 1'b1;
                                    else                    next[sRst]          = 1'b1;
            state[sRstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sRstThis]      = 1'b1;     
                                        else                next[sRstDecr]      = 1'b1;
                                    end                     
            state[sRstThis]     :   begin
                                        RST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     

            state[s00101x]      :   if (IS)                 next[sCst]          = 1'b1;
                                    else                    next[sIst]          = 1'b1;
            state[sIst]         :   begin
                                        ISTW = 1'b1;
                                        if (b5)             next[sIstDecr]      = 1'b1;
                                        else                next[sIst]          = 1'b1;
                                    end
            state[sIstDecr]     :   begin
                                        STDECN = 1'b1;
                                        if (stqzero)        next[sIstThis]      = 1'b1;     
                                        else                next[sIstDecr]      = 1'b1;
                                    end                     
            state[sIstThis]     :   begin
                                        IST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     
            state[sStDone]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sStDone]       = 1'b1;

            state[sCst]         :   if (b5)                 next[sCstDecr]      = 1'b1;
                                    else                    next[sCst]          = 1'b1;
            state[sCstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sCstThis]      = 1'b1;     
                                        else                next[sCstDecr]      = 1'b1;
                                    end                     
            state[sCstThis]     :   begin
                                        RST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sCstThis]      = 1'b1;
                                    end

            state[s0011x]       :   if (IS)                 next[s00111x]       = 1'b1;
                                    else                    next[s00110x]       = 1'b1;
            state[s00110x]      :   if (IS)                 next[sIpt]          = 1'b1;
                                    else                    next[sSpt]          = 1'b1;
            state[sSpt]         :   begin
                                        SPT = 1'b1;         
                                        if (b54)            next[sSptDone]      = 1'b1;         
                                        else                next[sSpt]          = 1'b1;
                                    end
            state[sSptDone]     :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sSptDone]      = 1'b1;

            state[sIpt]         :   if (is_eq_ptr)
                                        if (b54)            next[sIptSetC]      = 1'b1;
                                        else                next[sIpt]          = 1'b1;
                                    else                    next[sIptRstC]      = 1'b1;
            state[sIptSetC]       :   begin
                                        IPTS = 1'b1;
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sIptSetC]      = 1'b1;
                                    end
            state[sIptRstC]      :   begin
                                        IPTR = 1'b1;
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sIptRstC]      = 1'b1;
                                    end

            state[s00111x]      :   if (IS)                 next[sPti]          = 1'b1;
                                    else                    next[sPtd]          = 1'b1;
            state[sPtd]         :   if (b14)                next[sPtdNow]       = 1'b1;
                                    else                    next[sPtd]          = 1'b1;
            state[sPtdNow]      :   begin
                                        PTD = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;         
                                        else                next[sPtdNow]       = 1'b1;
                                    end

            state[sPti]         :   if (b14)                next[sPtiNow]       = 1'b1;
                                    else                    next[sPti]          = 1'b1;
            state[sPtiNow]      :   begin
                                        PTI = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;         
                                        else                next[sPtiNow]       = 1'b1;
                                    end

            state[s0001x]       :   if (IS)                 next[s00011x]       = 1'b1;
                                    else                    next[sType5Wait]    = 1'b1;
            state[s00011x]      :   if (IS)                 next[sType5Wait]    = 1'b1;
                                    else                    next[sLdc]          = 1'b1;
            state[sLdc]         :   begin
                                        PTONLY = 1'b1;         
                                        if (b54)            next[sPtd]          = 1'b1;
                                        else                next[sLdc]          = 1'b1;
                                    end
            state[sType5Wait]   :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sType5Wait]    = 1'b1;

            state[sType6]       :   if (IS)                 next[s000011x]      = 1'b1;
                                    else                    next[s000010x]      = 1'b1;
            state[s000010x]     :   if (IS)                 next[s0000101x]     = 1'b1;
                                    else                    next[sRomSel]       = 1'b1;
            state[sRomSel]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sRomSel]        = 1'b1;
            state[s0000101x]    :   if (IS)                 next[sKey]          = 1'b1;
                                    else                    next[sExtKey]       = 1'b1;
            state[sExtKey]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sExtKey]       = 1'b1;
            state[sKey]         :   if (b18)                next[sKeyOut]       = 1'b1;
                                    else                    next[sKey]          = 1'b1;
            state[sKeyOut]      :   begin
                                        TKR = 1'b1;                             
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sKeyOut]       = 1'b1;
                                    end
            state[s000011x]     :   if (IS)                 next[sDataStore]    = 1'b1;
                                    else                    next[sRet]          = 1'b1;
            state[sRet]         :   if (b18)                next[sRetOut]       = 1'b1;
                                    else                    next[sRet]          = 1'b1;
            state[sRetOut]      :   begin
                                        RET = 1'b1;                             
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sRetOut]       = 1'b1;
                                    end
            state[sDataStore]   :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sDataStore]    = 1'b1;
        endcase
    end
endmodule
module microprogrammed_controller_46 #(
    parameter   UseASM = 1
)
(

    output reg      JSB,
    output reg      BRH,
    output reg      PTONLY,
    output reg      UP2PT,
    output reg      ARITHW,
    output reg      ISTW,
    output reg      STDECN,
    output reg      SST,
    output reg      RST,
    output reg      IST,
    output reg      SPT,
    output reg      IPTR,
    output reg      IPTS,
    output reg      PTD,
    output reg      PTI,
    output reg      TKR,
    output reg      RET,
    output [1:62]   tp_state,

    input           PHI2,

    input           pwor,
    input           IS,
    input           b5,
    input           b14,
    input           b26,
    input           b45,
    input           b55,




    always @ (posedge PHI2 or posedge pwor) begin : proc_state_reg
        if (pwor) begin
            state           <= 'b0;

            state[sIdle]    <= 1'b1;
        end
        else state <= next;
    end


    always @* begin : proc_next_comb
        next    = 'b0;
        JSB     = 1'b0;
        BRH     = 1'b0;
        PTONLY  = 1'b0;
        UP2PT   = 1'b0;
        ARITHW  = 1'b0;
        STDECN  = 1'b0;
        SST     = 1'b0;
        RST     = 1'b0;
        ISTW    = 1'b0;
        IST     = 1'b0;
        SPT     = 1'b0;
        IPTR    = 1'b0;
        IPTS    = 1'b0;
        PTD     = 1'b0;
        PTI     = 1'b0;
        TKR     = 1'b0;
        RET     = 1'b0;

        case (1'b1)

            state[sIdle]        :   if (b45)
                                        if (IS)             next[s1x]           = 1'b1; 
                                        else                next[s0x]           = 1'b1;
                                    else                    next[sIdle]         = 1'b1;
            state[s0x]          :   if (IS)                 next[s01x]          = 1'b1;
                                    else                    next[s00x]          = 1'b1;
            state[s00x]         :   if (IS)                 next[s001x]         = 1'b1;
                                    else                    next[s000x]         = 1'b1;
            state[s001x]        :   if (IS)                 next[s0011x]        = 1'b1;
                                    else                    next[s0010x]        = 1'b1;
            state[s000x]        :   if (IS)                 next[s0001x]        = 1'b1;
                                    else                    next[s0000x]        = 1'b1;
            state[s0000x]       :   if (IS)                 next[sType6]        = 1'b1;
                                    else                    next[sNop]          = 1'b1;
            state[sNop]         :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sNop]          = 1'b1;
            state[sAddrOut]     :   if (b26)                next[sIdle]         = 1'b1;
                                    else                    next[sAddrOut]      = 1'b1;

            state[s1x]          :   if (IS)                 next[sBrhWait]      = 1'b1;
                                    else                    next[sJsb]          = 1'b1;
            state[sJsb]         :   begin
                                        JSB = 1'b1;         
                                        if (b54)            next[sJsbWait]      = 1'b1;
                                        else                next[sJsb]          = 1'b1;
                                    end                     
            state[sJsbWait]     :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sJsbWait]      = 1'b1;
            state[sBrhWait]     :   if (b18)
                                        if (CARRY_FF)       next[sAddrOut]      = 1'b1;
                                        else                next[sBrhOut]       = 1'b1;
                                    else                    next[sBrhWait]      = 1'b1;
            state[sBrhOut]      :   begin
                                        BRH = 1'b1;         
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sBrhOut]       = 1'b1;
                                    end

            state[s01x]         :   if (IS)                 next[sArithWait]    = 1'b1;
                                    else                    next[s010x]         = 1'b1;
            state[s010x]        :   if (IS)                 next[sArithWait]    = 1'b1;
                                    else                    next[s0100x]        = 1'b1;
            state[s0100x]       :   if (IS)                 next[sArithWP]      = 1'b1;
                                    else                    next[sArithP]       = 1'b1;      
            state[sArithP]      :   begin
                                        PTONLY = 1'b1;      
                                        if (b54)            next[sArithWait]    = 1'b1;   
                                        else                next[sArithP]       = 1'b1;
                                    end                     
            state[sArithWP]     :   begin
                                        UP2PT = 1'b1;       
                                        if (b54)            next[sArithWait]    = 1'b1;   
                                        else                next[sArithWP]      = 1'b1;
                                    end                     
            state[sArithWait]   :   begin
                                        ARITHW = 1'b1;      
                                        if (b18)            next[sAddrOut]      = 1'b1;
                                        else                next[sArithWait]    = 1'b1;
                                    end                     

            state[s0010x]       :   if (IS)                 next[s00101x]       = 1'b1;
                                    else                    next[s00100x]       = 1'b1;
            state[s00100x]      :   if (IS)                 next[sRst]          = 1'b1;
                                    else                    next[sSst]          = 1'b1;
            state[sSst]         :   if (b5)                 next[sSstDecr]      = 1'b1;
                                    else                    next[sSst]          = 1'b1;
            state[sSstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sSstThis]      = 1'b1;     
                                        else                next[sSstDecr]      = 1'b1;
                                    end                     
            state[sSstThis]     :   begin
                                        SST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     

            state[sRst]         :   if (b5)                 next[sRstDecr]      = 1'b1;
                                    else                    next[sRst]          = 1'b1;
            state[sRstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sRstThis]      = 1'b1;     
                                        else                next[sRstDecr]      = 1'b1;
                                    end                     
            state[sRstThis]     :   begin
                                        RST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     

            state[s00101x]      :   if (IS)                 next[sCst]          = 1'b1;
                                    else                    next[sIst]          = 1'b1;
            state[sIst]         :   begin
                                        ISTW = 1'b1;
                                        if (b5)             next[sIstDecr]      = 1'b1;
                                        else                next[sIst]          = 1'b1;
                                    end
            state[sIstDecr]     :   begin
                                        STDECN = 1'b1;
                                        if (stqzero)        next[sIstThis]      = 1'b1;     
                                        else                next[sIstDecr]      = 1'b1;
                                    end                     
            state[sIstThis]     :   begin
                                        IST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sStDone]       = 1'b1;
                                    end                     
            state[sStDone]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sStDone]       = 1'b1;

            state[sCst]         :   if (b5)                 next[sCstDecr]      = 1'b1;
                                    else                    next[sCst]          = 1'b1;
            state[sCstDecr]     :   begin
                                        STDECN = 1'b1;      
                                        if (stqzero)        next[sCstThis]      = 1'b1;     
                                        else                next[sCstDecr]      = 1'b1;
                                    end                     
            state[sCstThis]     :   begin
                                        RST = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sCstThis]      = 1'b1;
                                    end

            state[s0011x]       :   if (IS)                 next[s00111x]       = 1'b1;
                                    else                    next[s00110x]       = 1'b1;
            state[s00110x]      :   if (IS)                 next[sIpt]          = 1'b1;
                                    else                    next[sSpt]          = 1'b1;
            state[sSpt]         :   begin
                                        SPT = 1'b1;         
                                        if (b54)            next[sSptDone]      = 1'b1;         
                                        else                next[sSpt]          = 1'b1;
                                    end
            state[sSptDone]     :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sSptDone]      = 1'b1;

            state[sIpt]         :   if (is_eq_ptr)
                                        if (b54)            next[sIptSetC]      = 1'b1;
                                        else                next[sIpt]          = 1'b1;
                                    else                    next[sIptRstC]      = 1'b1;
            state[sIptSetC]       :   begin
                                        IPTS = 1'b1;
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sIptSetC]      = 1'b1;
                                    end
            state[sIptRstC]      :   begin
                                        IPTR = 1'b1;
                                        if (b18)            next[sAddrOut]      = 1'b1;     
                                        else                next[sIptRstC]      = 1'b1;
                                    end

            state[s00111x]      :   if (IS)                 next[sPti]          = 1'b1;
                                    else                    next[sPtd]          = 1'b1;
            state[sPtd]         :   if (b14)                next[sPtdNow]       = 1'b1;
                                    else                    next[sPtd]          = 1'b1;
            state[sPtdNow]      :   begin
                                        PTD = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;         
                                        else                next[sPtdNow]       = 1'b1;
                                    end

            state[sPti]         :   if (b14)                next[sPtiNow]       = 1'b1;
                                    else                    next[sPti]          = 1'b1;
            state[sPtiNow]      :   begin
                                        PTI = 1'b1;         
                                        if (b18)            next[sAddrOut]      = 1'b1;         
                                        else                next[sPtiNow]       = 1'b1;
                                    end

            state[s0001x]       :   if (IS)                 next[s00011x]       = 1'b1;
                                    else                    next[sType5Wait]    = 1'b1;
            state[s00011x]      :   if (IS)                 next[sType5Wait]    = 1'b1;
                                    else                    next[sLdc]          = 1'b1;
            state[sLdc]         :   begin
                                        PTONLY = 1'b1;         
                                        if (b54)            next[sPtd]          = 1'b1;
                                        else                next[sLdc]          = 1'b1;
                                    end
            state[sType5Wait]   :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sType5Wait]    = 1'b1;

            state[sType6]       :   if (IS)                 next[s000011x]      = 1'b1;
                                    else                    next[s000010x]      = 1'b1;
            state[s000010x]     :   if (IS)                 next[s0000101x]     = 1'b1;
                                    else                    next[sRomSel]       = 1'b1;
            state[sRomSel]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sRomSel]        = 1'b1;
            state[s0000101x]    :   if (IS)                 next[sKey]          = 1'b1;
                                    else                    next[sExtKey]       = 1'b1;
            state[sExtKey]      :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sExtKey]       = 1'b1;
            state[sKey]         :   if (b18)                next[sKeyOut]       = 1'b1;
                                    else                    next[sKey]          = 1'b1;
            state[sKeyOut]      :   begin
                                        TKR = 1'b1;                             
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sKeyOut]       = 1'b1;
                                    end
            state[s000011x]     :   if (IS)                 next[sDataStore]    = 1'b1;
                                    else                    next[sRet]          = 1'b1;
            state[sRet]         :   if (b18)                next[sRetOut]       = 1'b1;
                                    else                    next[sRet]          = 1'b1;
            state[sRetOut]      :   begin
                                        RET = 1'b1;                             
                                        if (b26)            next[sIdle]         = 1'b1;
                                        else                next[sRetOut]       = 1'b1;
                                    end
            state[sDataStore]   :   if (b18)                next[sAddrOut]      = 1'b1;
                                    else                    next[sDataStore]    = 1'b1;
        endcase
    end
endmodule