data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:12: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'ha5; b = 8\'hbd;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:13: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'h18; b = 8\'h66;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'h35; b = 8\'h57;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'hb7; b = 8\'hc0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'h15; b = 8\'h11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'h07; b = 8\'h55;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:22: Unsupported: Ignoring delay on this delayed statement.\n #50 sel = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:23: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 1\'b0;\n ^\n%Error: data/full_repos/permissive/468612001/Week03/mux8b_2to1/tb_mux8b_2to1.v:6: Cannot find file containing module: \'mux8b_2to1_case\'\n mux8b_2to1_case U0 (a, b, sel, out);\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week03/mux8b_2to1,data/full_repos/permissive/468612001/mux8b_2to1_case\n             data/full_repos/permissive/468612001/Week03/mux8b_2to1,data/full_repos/permissive/468612001/mux8b_2to1_case.v\n             data/full_repos/permissive/468612001/Week03/mux8b_2to1,data/full_repos/permissive/468612001/mux8b_2to1_case.sv\n             mux8b_2to1_case\n             mux8b_2to1_case.v\n             mux8b_2to1_case.sv\n             obj_dir/mux8b_2to1_case\n             obj_dir/mux8b_2to1_case.v\n             obj_dir/mux8b_2to1_case.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mux8b_2to1();
	reg [7:0] a, b;
	reg		 sel;
	wire [7:0] out;
	
	mux8b_2to1_case U0 (a, b, sel, out);


	
	initial begin
			a = 8'h42;	b = 8'h71;
	#20	a = 8'ha5;	b = 8'hbd;
	#20	a = 8'h18;	b = 8'h66;
	#20	a = 8'h35;	b = 8'h57;
	#20	a = 8'hb7;	b = 8'hc0;
	#20	a = 8'h15;	b = 8'h11;
	#20	a = 8'h07;	b = 8'h55;
	end
	
	initial begin
			sel = 1'b0;
	#50	sel = 1'b1;
	#40	sel = 1'b0;
	end
endmodule
module tb_mux8b_2to1();

	reg [7:0] a, b;
	reg		 sel;
	wire [7:0] out;
	
	mux8b_2to1_case U0 (a, b, sel, out);


	
	initial begin
			a = 8'h42;	b = 8'h71;
	#20	a = 8'ha5;	b = 8'hbd;
	#20	a = 8'h18;	b = 8'h66;
	#20	a = 8'h35;	b = 8'h57;
	#20	a = 8'hb7;	b = 8'hc0;
	#20	a = 8'h15;	b = 8'h11;
	#20	a = 8'h07;	b = 8'h55;
	end
	
	initial begin
			sel = 1'b0;
	#50	sel = 1'b1;
	#40	sel = 1'b0;
	end
endmodule