data/full_repos/permissive/524509242/FSM GCD/DFLIPFLOP.v
1: b'%Error: Cannot find file containing module: GCD,data/full_repos/permissive/524509242\n        ... Looked in:\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.v\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.sv\n             GCD,data/full_repos/permissive/524509242\n             GCD,data/full_repos/permissive/524509242.v\n             GCD,data/full_repos/permissive/524509242.sv\n             obj_dir/GCD,data/full_repos/permissive/524509242\n             obj_dir/GCD,data/full_repos/permissive/524509242.v\n             obj_dir/GCD,data/full_repos/permissive/524509242.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/524509242/FSM\n%Error: Cannot find file containing module: GCD/DFLIPFLOP.v\n%Error: Exiting due to 3 error(s)\n'
module DFLIPFLOP (d_out,d_in, ld, clk, reset);

	input [3:0] d_in;
	input ld,clk, reset;
	output reg [3:0] d_out = 4'd0;
	
	
	always @(posedge clk) begin
		if (reset && !ld) begin
			d_out = 0; end
		else if(ld && !reset) begin
			d_out=d_in; end
		else begin d_out = d_out; end
	end
endmodule
module DFLIPFLOP (d_out,d_in, ld, clk, reset);


	input [3:0] d_in;
	input ld,clk, reset;
	output reg [3:0] d_out = 4'd0;
	
	
	always @(posedge clk) begin
		if (reset && !ld) begin
			d_out = 0; end
		else if(ld && !reset) begin
			d_out=d_in; end
		else begin d_out = d_out; end
	end
endmodule