data/full_repos/permissive/531341619/rtl/bfp_converter_align_mantissa.v
data/verilator_xmls/a47c80b9-dbb2-4d42-8537-bb30d4da8b2b.xml
module bfp_converter_align_mantissa
#(
  QUNATIZED_MANTISSA_WIDTH = 6,
  EXPONENT_WIDTH = 8
) (
  input  wire clk,
  input  wire [EXPONENT_WIDTH-1:0] exponent_diff,
  input  wire signed [QUNATIZED_MANTISSA_WIDTH-1:0] mantissa_data_in,
  output reg  signed [QUNATIZED_MANTISSA_WIDTH-1:0] mantissa_alligned
);
  always @(posedge clk)
  begin
    mantissa_alligned <= mantissa_data_in >>> exponent_diff;
  end
endmodule
module bfp_converter_align_mantissa
#(
  QUNATIZED_MANTISSA_WIDTH = 6,
  EXPONENT_WIDTH = 8
) (
  input  wire clk,
  input  wire [EXPONENT_WIDTH-1:0] exponent_diff,
  input  wire signed [QUNATIZED_MANTISSA_WIDTH-1:0] mantissa_data_in,
  output reg  signed [QUNATIZED_MANTISSA_WIDTH-1:0] mantissa_alligned
);

  always @(posedge clk)
  begin
    mantissa_alligned <= mantissa_data_in >>> exponent_diff;
  end
endmodule