data/full_repos/permissive/463439324/decap/dsptest0.v
data/verilator_xmls/77508a48-bb12-4ca6-bc52-92c31441ffc1.xml
module dsptest0(
    input clk,
    input signed    [24:0]  data_A,
    input signed    [17:0]  data_B,
    input signed    [47:0]  data_C,
    input signed    [24:0]  data_D,
    input                   data_crin,

    input                   DAaddsubctrl,

    output signed   [47:0]  data_P,
    output          [3:0]   data_crout
);

    wire signed     [29:0]  dsp0_A;
    wire signed     [17:0]  dsp0_B;
    wire signed     [47:0]  dsp0_C;
    wire signed     [24:0]  dsp0_D;
    wire                    dsp0_crin;
    wire signed     [47:0]  dsp0_P;
    wire            [3:0]   dsp0_crout;

    wire            [3:0]   dsp0_alumode;
    wire            [2:0]   dsp0_carryinsel;
    wire            [4:0]   dsp0_inmode;
    wire            [6:0]   dsp0_opmode;

    assign dsp0_A = { 5'b0, data_A };
    assign dsp0_B = data_B;
    assign dsp0_C = data_C;
    assign dsp0_D = data_D;
    assign dsp0_crin = data_crin;
    assign data_P = dsp0_P;
    assign data_crout = dsp0_crout;

    assign dsp0_alumode = 4'b0000;
    assign dsp0_carryinsel = 3'b000;
    assign dsp0_inmode = { 1'b0, DAaddsubctrl, 3'b100 } ;
    assign dsp0_opmode = 7'b0110101;

`ifdef GENERAL_VERSION

    wire signed [24:0] DandA;
    wire signed [49:0] DAtimesB;

    assign DandA = data_D + ( DAaddsubctrl ? ~data_A : data_A ) + { 24'b0, DAaddsubctrl };
    assign DAtimesB = DandA * data_B;

    assign data_P = DAtimesB[47:0] + data_C;

`endif

`ifdef XILINX_ZEDBOARD

    DSP48E1 #(

        .A_INPUT("DIRECT"),
        .B_INPUT("DIRECT"),
        .USE_DPORT("TRUE"),
        .USE_MULT("MULTIPLY"),
        .USE_SIMD("ONE48"),

        .AUTORESET_PATDET("NO_RESET"),
        .MASK(48'h3fffffffffff),
        .PATTERN(48'h000000000000),
        .SEL_MASK("MASK"),
        .SEL_PATTERN("PATTERN"),
        .USE_PATTERN_DETECT("NO_PATDET"),

        .ACASCREG(0),
        .ADREG(0),
        .ALUMODEREG(0),
        .AREG(0),
        .BCASCREG(0),
        .BREG(0),
        .CARRYINREG(0),
        .CARRYINSELREG(0),
        .CREG(0),
        .DREG(0),
        .INMODEREG(0),
        .MREG(0),
        .OPMODEREG(0),
        .PREG(0)
    ) dsp_inst0 (












        .CARRYOUT(dsp0_crout),
        .P(dsp0_P),







        .ALUMODE(dsp0_alumode),
        .CARRYINSEL(dsp0_carryinsel),
        .CLK(clk),
        .INMODE(dsp0_inmode),
        .OPMODE(dsp0_opmode),

        .A(dsp0_A),
        .B(dsp0_B),
        .C(dsp0_C),
        .CARRYIN(dsp0_crin),
        .D(dsp0_D)
























    );

`endif

endmodule
module dsptest0(
    input clk,
    input signed    [24:0]  data_A,
    input signed    [17:0]  data_B,
    input signed    [47:0]  data_C,
    input signed    [24:0]  data_D,
    input                   data_crin,

    input                   DAaddsubctrl,

    output signed   [47:0]  data_P,
    output          [3:0]   data_crout
);


    wire signed     [29:0]  dsp0_A;
    wire signed     [17:0]  dsp0_B;
    wire signed     [47:0]  dsp0_C;
    wire signed     [24:0]  dsp0_D;
    wire                    dsp0_crin;
    wire signed     [47:0]  dsp0_P;
    wire            [3:0]   dsp0_crout;

    wire            [3:0]   dsp0_alumode;
    wire            [2:0]   dsp0_carryinsel;
    wire            [4:0]   dsp0_inmode;
    wire            [6:0]   dsp0_opmode;

    assign dsp0_A = { 5'b0, data_A };
    assign dsp0_B = data_B;
    assign dsp0_C = data_C;
    assign dsp0_D = data_D;
    assign dsp0_crin = data_crin;
    assign data_P = dsp0_P;
    assign data_crout = dsp0_crout;

    assign dsp0_alumode = 4'b0000;
    assign dsp0_carryinsel = 3'b000;
    assign dsp0_inmode = { 1'b0, DAaddsubctrl, 3'b100 } ;
    assign dsp0_opmode = 7'b0110101;

`ifdef GENERAL_VERSION

    wire signed [24:0] DandA;
    wire signed [49:0] DAtimesB;

    assign DandA = data_D + ( DAaddsubctrl ? ~data_A : data_A ) + { 24'b0, DAaddsubctrl };
    assign DAtimesB = DandA * data_B;

    assign data_P = DAtimesB[47:0] + data_C;

`endif

`ifdef XILINX_ZEDBOARD

    DSP48E1 #(

        .A_INPUT("DIRECT"),
        .B_INPUT("DIRECT"),
        .USE_DPORT("TRUE"),
        .USE_MULT("MULTIPLY"),
        .USE_SIMD("ONE48"),

        .AUTORESET_PATDET("NO_RESET"),
        .MASK(48'h3fffffffffff),
        .PATTERN(48'h000000000000),
        .SEL_MASK("MASK"),
        .SEL_PATTERN("PATTERN"),
        .USE_PATTERN_DETECT("NO_PATDET"),

        .ACASCREG(0),
        .ADREG(0),
        .ALUMODEREG(0),
        .AREG(0),
        .BCASCREG(0),
        .BREG(0),
        .CARRYINREG(0),
        .CARRYINSELREG(0),
        .CREG(0),
        .DREG(0),
        .INMODEREG(0),
        .MREG(0),
        .OPMODEREG(0),
        .PREG(0)
    ) dsp_inst0 (












        .CARRYOUT(dsp0_crout),
        .P(dsp0_P),







        .ALUMODE(dsp0_alumode),
        .CARRYINSEL(dsp0_carryinsel),
        .CLK(clk),
        .INMODE(dsp0_inmode),
        .OPMODE(dsp0_opmode),

        .A(dsp0_A),
        .B(dsp0_B),
        .C(dsp0_C),
        .CARRYIN(dsp0_crin),
        .D(dsp0_D)
























    );

`endif

endmodule