data/full_repos/permissive/423014416/MA7_Clock.srcs/sources_1/new/ClockStateStorage.v
data/verilator_xmls/2a113727-d37f-41b7-8eea-33ecf24cd15d.xml
module ClockStateStorage(

    input clk,



    input up, down, left, right, reset,
    

    output [5:0] second, minute, hour,

    output reg blink,

    output reg cursorPos
);

    reg [25:0] secondIncrementCounter;
    
    reg [5:0] trueHour; 
    reg [5:0] trueMinute;
    reg [5:0] trueSecond;


    assign hour = trueHour;
    assign minute = trueMinute;
    assign second = trueSecond;

    initial begin
        trueSecond = 0;
        trueMinute = 0;
        trueHour = 0;
        secondIncrementCounter = 0;
        blink = 1;
        cursorPos = 0;
    end

    always @(posedge clk) begin

        if (reset) begin
            trueSecond <= 0;
            trueMinute <= 0;
            trueHour <= 0;
        end
        if (left)
            trueSecond <= 0;
        if (right)
            cursorPos <= ~cursorPos;
        if (up) begin
            case (cursorPos)
                1'b0 : trueMinute <= trueMinute < 59 ? trueMinute + 1 : 0;
                1'b1 : trueHour <= trueHour < 23 ? trueHour + 1 : 0;
            endcase
        end
        if (down) begin
            case (cursorPos)
                1'b0 : trueMinute <= trueMinute > 0 ? trueMinute - 1 : 59;
                1'b1 : trueHour <= trueHour > 0 ? trueHour - 1 : 23;
            endcase
        end



        secondIncrementCounter <= secondIncrementCounter + 1;
        if (secondIncrementCounter == 26'd50000000) begin
            secondIncrementCounter <= 1;
            blink <= ~blink;
            if (blink == 0)
            begin
                trueSecond <= trueSecond + 1;

                if (trueSecond == 6'd59) begin
                    trueSecond <= 0;
                    trueMinute <= trueMinute + 1;

                    if (trueMinute == 6'd59) begin
                        trueMinute <= 0;
                        trueHour <= trueHour + 1;

                        if (trueHour == 6'd23) begin
                            trueHour <= 0;
                        end
                    end
                end
            end
        end
    end


endmodule
module ClockStateStorage(

    input clk,



    input up, down, left, right, reset,
    

    output [5:0] second, minute, hour,

    output reg blink,

    output reg cursorPos
);


    reg [25:0] secondIncrementCounter;
    
    reg [5:0] trueHour; 
    reg [5:0] trueMinute;
    reg [5:0] trueSecond;


    assign hour = trueHour;
    assign minute = trueMinute;
    assign second = trueSecond;

    initial begin
        trueSecond = 0;
        trueMinute = 0;
        trueHour = 0;
        secondIncrementCounter = 0;
        blink = 1;
        cursorPos = 0;
    end

    always @(posedge clk) begin

        if (reset) begin
            trueSecond <= 0;
            trueMinute <= 0;
            trueHour <= 0;
        end
        if (left)
            trueSecond <= 0;
        if (right)
            cursorPos <= ~cursorPos;
        if (up) begin
            case (cursorPos)
                1'b0 : trueMinute <= trueMinute < 59 ? trueMinute + 1 : 0;
                1'b1 : trueHour <= trueHour < 23 ? trueHour + 1 : 0;
            endcase
        end
        if (down) begin
            case (cursorPos)
                1'b0 : trueMinute <= trueMinute > 0 ? trueMinute - 1 : 59;
                1'b1 : trueHour <= trueHour > 0 ? trueHour - 1 : 23;
            endcase
        end



        secondIncrementCounter <= secondIncrementCounter + 1;
        if (secondIncrementCounter == 26'd50000000) begin
            secondIncrementCounter <= 1;
            blink <= ~blink;
            if (blink == 0)
            begin
                trueSecond <= trueSecond + 1;

                if (trueSecond == 6'd59) begin
                    trueSecond <= 0;
                    trueMinute <= trueMinute + 1;

                    if (trueMinute == 6'd59) begin
                        trueMinute <= 0;
                        trueHour <= trueHour + 1;

                        if (trueHour == 6'd23) begin
                            trueHour <= 0;
                        end
                    end
                end
            end
        end
    end


endmodule