data/full_repos/permissive/450962776/processor/src/and_ori_type.v
data/verilator_xmls/44f57cea-670e-4ca6-acdc-385a6c9c4cce.xml
module and_ori_type(op,F);
input [3:0] op;
output F;
wire a,b;

not(a,op[3]);
not(b,op[2]);

and(F,a,b,op[0],op[1]);
endmodule
module and_ori_type(op,F);

input [3:0] op;
output F;
wire a,b;

not(a,op[3]);
not(b,op[2]);

and(F,a,b,op[0],op[1]);
endmodule