data/full_repos/permissive/43974493/src/divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43974493/src/divider.v:50: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'div_counter\' generates 4 bits.\n                                                                    : ... In instance divider\n           if (div_counter == BITS - 1) begin\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/divider.v:62: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                    : ... In instance divider\n              quotient <= (quotient << 1) | 1\'b1;\n                                          ^\n%Error: Exiting due to 2 warning(s)\n'
module divider
  (
   input                 clk,
   input                 en,
   input [BITS-1:0]      dividend,
   input [BITS-1:0]      divisor,
   output reg [BITS-1:0] quotient,
   output [BITS-1:0]     remainder,
   output                done
   );

   initial begin
      quotient = 0;
   end

   parameter BITS = 16;

   localparam STATE_IDLE   = 0;
   localparam STATE_DIVIDE = 1;

   reg                    state = STATE_IDLE;
   reg [$clog2(BITS)-1:0] div_counter = 0;
   reg [(BITS-1)*2:0]     dividend_reg = 0;
   reg [(BITS-1)*2:0]     divisor_reg = 0;        

   assign done = (STATE_IDLE == state) && !en;
   assign remainder = dividend_reg[BITS-1:0];

   always @ (posedge clk) begin
      case (state)
        STATE_IDLE: begin
           if (en) begin
              div_counter <= 0;
              dividend_reg <= { {BITS-1{1'b0}}, dividend };
              divisor_reg <= { divisor, {BITS-1{1'b0}} };
              quotient <= 0;
              state <= STATE_DIVIDE;
           end
        end
        STATE_DIVIDE: begin


           if (div_counter == BITS - 1) begin
              state <= STATE_IDLE;
           end else begin
              div_counter <= div_counter + 1;
           end



           divisor_reg <= divisor_reg >> 1;
           if (dividend_reg < divisor_reg) begin
              quotient <= quotient << 1;
           end else begin
              quotient <= (quotient << 1) | 1'b1;
              dividend_reg <= dividend_reg - divisor_reg;
           end
        end
      endcase
   end

endmodule
module divider
  (
   input                 clk,
   input                 en,
   input [BITS-1:0]      dividend,
   input [BITS-1:0]      divisor,
   output reg [BITS-1:0] quotient,
   output [BITS-1:0]     remainder,
   output                done
   );


   initial begin
      quotient = 0;
   end

   parameter BITS = 16;

   localparam STATE_IDLE   = 0;
   localparam STATE_DIVIDE = 1;

   reg                    state = STATE_IDLE;
   reg [$clog2(BITS)-1:0] div_counter = 0;
   reg [(BITS-1)*2:0]     dividend_reg = 0;
   reg [(BITS-1)*2:0]     divisor_reg = 0;        

   assign done = (STATE_IDLE == state) && !en;
   assign remainder = dividend_reg[BITS-1:0];

   always @ (posedge clk) begin
      case (state)
        STATE_IDLE: begin
           if (en) begin
              div_counter <= 0;
              dividend_reg <= { {BITS-1{1'b0}}, dividend };
              divisor_reg <= { divisor, {BITS-1{1'b0}} };
              quotient <= 0;
              state <= STATE_DIVIDE;
           end
        end
        STATE_DIVIDE: begin


           if (div_counter == BITS - 1) begin
              state <= STATE_IDLE;
           end else begin
              div_counter <= div_counter + 1;
           end



           divisor_reg <= divisor_reg >> 1;
           if (dividend_reg < divisor_reg) begin
              quotient <= quotient << 1;
           end else begin
              quotient <= (quotient << 1) | 1'b1;
              dividend_reg <= dividend_reg - divisor_reg;
           end
        end
      endcase
   end

endmodule