data/full_repos/permissive/464389943/verilog/rtl/pwm_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/464389943/verilog/rtl/pwm_top.v:99: Operator ASSIGNW expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 37 bits.\n                                                                             : ... In instance pwm_top\n    assign io_oeb                     = {(38-1){1\'b1}};\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/464389943/verilog/rtl/pwm_top.v:120: Cannot find file containing module: \'pwm\'\n        pwm #(\n        ^~~\n        ... Looked in:\n             data/full_repos/permissive/464389943/verilog/rtl,data/full_repos/permissive/464389943/pwm\n             data/full_repos/permissive/464389943/verilog/rtl,data/full_repos/permissive/464389943/pwm.v\n             data/full_repos/permissive/464389943/verilog/rtl,data/full_repos/permissive/464389943/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module 
pwm_top #(
    parameter BITS   = 32,
    parameter NumPWM = 4
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input          wb_clk_i,
    input          wb_rst_i,
    input          wbs_stb_i,
    input          wbs_cyc_i,
    input          wbs_we_i,
    input [3:0]    wbs_sel_i,
    input [31:0]   wbs_dat_i,
    input [31:0]   wbs_adr_i,
    output         wbs_ack_o,
    output [31:0]  wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire [31:0]               rdata [NumPWM-1:0]; 
    wire [31:0]               wdata;
    wire [NumPWM-1:0]         cio_pwm;
    wire [NumPWM-1:0]         ready;
    wire [$clog2(NumPWM)-1:0] pwm_select;
    wire [NumPWM-1:0]         valid_select;

    wire valid;
    wire [31:0] la_write;

    wire clk;
    wire rst;



    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wbs_dat_o = rdata[pwm_select];
    assign wdata = wbs_dat_i;


    assign io_out[`MPRJ_IO_PADS-1:22] = 0;
    assign io_out[21:20]              = pwm_select;
    assign io_out[19:16]              = cio_pwm;
    assign io_out[15:0]               = 0;
    assign io_oeb                     = {(`MPRJ_IO_PADS-1){1'b1}};


    assign irq = 3'b000;


    assign la_data_out = {{(128-NumPWM){1'b0}}, cio_pwm};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
    
    assign wbs_ack_o = | ready;
    assign pwm_select = (wbs_adr_i[7:6] === 2'bX) ? 2'b0 : wbs_adr_i[7:6];

    assign valid_select = (pwm_select == 0) ? 4'b0001 :
                          ((pwm_select == 1) ? 4'b0010 :
                          ((pwm_select == 2) ? 4'b0100 :
                          ((pwm_select == 3) ? 4'b1000 : 4'b0000)));
     
    genvar i;
    for (i = 0; i < NumPWM; i = i+1) begin
        pwm #(
            .BITS      (BITS)
        ) pwm_insts (
            .clk_i     (clk),
            .rst_ni    (!rst),
            .ready_o   (ready[i]),
            .valid_i   (valid && valid_select[i]),
            .rdata_o   (rdata[i]),
            .wdata_i   (wbs_dat_i),
            .we_i      (wbs_we_i),
            .addr_i    (wbs_adr_i),



            .cio_pwm_o (cio_pwm[i])
        );
    end
    

endmodule
module 
pwm_top #(
    parameter BITS   = 32,
    parameter NumPWM = 4
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input          wb_clk_i,
    input          wb_rst_i,
    input          wbs_stb_i,
    input          wbs_cyc_i,
    input          wbs_we_i,
    input [3:0]    wbs_sel_i,
    input [31:0]   wbs_dat_i,
    input [31:0]   wbs_adr_i,
    output         wbs_ack_o,
    output [31:0]  wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


    wire [31:0]               rdata [NumPWM-1:0]; 
    wire [31:0]               wdata;
    wire [NumPWM-1:0]         cio_pwm;
    wire [NumPWM-1:0]         ready;
    wire [$clog2(NumPWM)-1:0] pwm_select;
    wire [NumPWM-1:0]         valid_select;

    wire valid;
    wire [31:0] la_write;

    wire clk;
    wire rst;



    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wbs_dat_o = rdata[pwm_select];
    assign wdata = wbs_dat_i;


    assign io_out[`MPRJ_IO_PADS-1:22] = 0;
    assign io_out[21:20]              = pwm_select;
    assign io_out[19:16]              = cio_pwm;
    assign io_out[15:0]               = 0;
    assign io_oeb                     = {(`MPRJ_IO_PADS-1){1'b1}};


    assign irq = 3'b000;


    assign la_data_out = {{(128-NumPWM){1'b0}}, cio_pwm};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
    
    assign wbs_ack_o = | ready;
    assign pwm_select = (wbs_adr_i[7:6] === 2'bX) ? 2'b0 : wbs_adr_i[7:6];

    assign valid_select = (pwm_select == 0) ? 4'b0001 :
                          ((pwm_select == 1) ? 4'b0010 :
                          ((pwm_select == 2) ? 4'b0100 :
                          ((pwm_select == 3) ? 4'b1000 : 4'b0000)));
     
    genvar i;
    for (i = 0; i < NumPWM; i = i+1) begin
        pwm #(
            .BITS      (BITS)
        ) pwm_insts (
            .clk_i     (clk),
            .rst_ni    (!rst),
            .ready_o   (ready[i]),
            .valid_i   (valid && valid_select[i]),
            .rdata_o   (rdata[i]),
            .wdata_i   (wbs_dat_i),
            .we_i      (wbs_we_i),
            .addr_i    (wbs_adr_i),



            .cio_pwm_o (cio_pwm[i])
        );
    end
    

endmodule