data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/d177eba9-38a0-4cdc-80cc-15dec18c8af5.xml
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data_a,
       din_data_b,
       din_data_c,
       din_data_d,
       din_data_e,
       din_data_f,
       din_data_g,
       din_data_h,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";
    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data_a;
	input [7:0] din_data_b;
	input [7:0] din_data_c;
	input [7:0] din_data_d;
	input [7:0] din_data_e;
	input [7:0] din_data_f;
	input [7:0] din_data_g;
	input [7:0] din_data_h;
	input dout_busy;
	output dout_vld;
	output [31:0] dout_data;


endmodule
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data_a,
       din_data_b,
       din_data_c,
       din_data_d,
       din_data_e,
       din_data_f,
       din_data_g,
       din_data_h,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";

    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data_a;
	input [7:0] din_data_b;
	input [7:0] din_data_c;
	input [7:0] din_data_d;
	input [7:0] din_data_e;
	input [7:0] din_data_f;
	input [7:0] din_data_g;
	input [7:0] din_data_h;
	input dout_busy;
	output dout_vld;
	output [31:0] dout_data;


endmodule