data/full_repos/permissive/471533249/comp_unit_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n  clk = 0; #20; clk = 1; #20;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n  clk = 0; #20; clk = 1; #20;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:37: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:55: Unsupported: Ignoring delay on this delayed statement.\n  #280;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:64: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:73: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:82: Unsupported: Ignoring delay on this delayed statement.\n  #280;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/comp_unit_tb.sv:91: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Error: data/full_repos/permissive/471533249/comp_unit_tb.sv:21: Cannot find file containing module: \'comp_unit\'\n comp_unit comp(clk, reset,  mult_en, add_en, out_en, Ain, Bin, Cout, Aout, Bout, overflow);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/comp_unit\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/comp_unit.v\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/comp_unit.sv\n             comp_unit\n             comp_unit.v\n             comp_unit.sv\n             obj_dir/comp_unit\n             obj_dir/comp_unit.v\n             obj_dir/comp_unit.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comp_unit_tb();

	logic clk, reset,  mult_en, add_en, out_en;
	logic [31:0] Ain, Bin; 
	

	logic[31:0] Cout, Aout, Bout;
	logic overflow;
	
	logic [5:0] testnum, errors;
	
	comp_unit comp(clk, reset,  mult_en, add_en, out_en, Ain, Bin, Cout, Aout, Bout, overflow);
	
	always 
	begin
		clk = 0; #20; clk = 1; #20;
	end
	
	always
	begin
		reset = 1'b1;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
			
		#40;
		
		reset = 1'b0;
		mult_en = 1'b1;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#200;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b1;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#280;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b1;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#40;
		
		reset = 1'b0;
		mult_en = 1'b1;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#200;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b1;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#280;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b1;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#40;
	end
	
endmodule
module comp_unit_tb();


	logic clk, reset,  mult_en, add_en, out_en;
	logic [31:0] Ain, Bin; 
	

	logic[31:0] Cout, Aout, Bout;
	logic overflow;
	
	logic [5:0] testnum, errors;
	
	comp_unit comp(clk, reset,  mult_en, add_en, out_en, Ain, Bin, Cout, Aout, Bout, overflow);
	
	always 
	begin
		clk = 0; #20; clk = 1; #20;
	end
	
	always
	begin
		reset = 1'b1;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
			
		#40;
		
		reset = 1'b0;
		mult_en = 1'b1;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#200;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b1;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#280;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b1;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#40;
		
		reset = 1'b0;
		mult_en = 1'b1;
		add_en = 1'b0;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#200;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b1;
		out_en = 1'b0;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#280;
		
		reset = 1'b0;
		mult_en = 1'b0;
		add_en = 1'b0;
		out_en = 1'b1;
		Ain = 32'h400ccccd;
		Bin = 32'h40533333;
		
		#40;
	end
	
endmodule