data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_zcmp64.v
data/verilator_xmls/0775290b-c7e0-4a43-9cc1-a6d3e525b4af.xml
module sparc_tlu_zcmp64(

   zero, 

   in
   );

   input [63:0] in;

   output      zero;

   reg 	       zero;

   always @ (in)
     begin
	if (in == 64'b0)
	  zero = 1'b1;
	else
	  zero = 1'b0;
     end
   

endmodule
module sparc_tlu_zcmp64(

   zero, 

   in
   );


   input [63:0] in;

   output      zero;

   reg 	       zero;

   always @ (in)
     begin
	if (in == 64'b0)
	  zero = 1'b1;
	else
	  zero = 1'b0;
     end
   

endmodule