data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv:43: Unsupported or unknown PLI call: $$display\n    $$display("INITIALIZED.");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv:45: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv:55: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_arr_tb.sv:61: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pe_arr_tb();

parameter COL = 8;
parameter ROW = 8;
parameter SIMCYCLES = 10;

reg clk;
reg rstn;
reg fire;
reg [7:0] in_w [0 : COL-1];
reg [7:0] in_a [0 : ROW-1];
wire [31:0] outs [0 : (ROW*COL)-1];
wire outvalids [0 : (ROW*COL)-1];

integer i,j;

PE_ARR #(.ROWS(ROW), .COLS(COL)) 
	dut (.clk(clk), .rstn(rstn), 
        .fire(fire), 
        .in_w(in_w), 
        .in_a(in_a), 
        .outs(outs),
        .outvalids(outvalids));

initial forever 
begin
    `HALF_CLOCK clk = ~clk;
end

initial
begin
    clk <= 1;
    rstn <= 0;
    for(i=0; i<COL; i=i+1) begin
        in_w[i] <= 1;
        in_a[i] <= 0;
    end

    $$display("INITIALIZED.");
    
    @(posedge clk);
    
    fire <= 1;
    rstn <= 1;

    $display("STARTING SIMULATION");
    for (i=0; i<SIMCYCLES; i=i+1) begin
        for (j=0; j<COL; j=j+1) begin
            in_a[j] <= in_a[j] + 1;
        end
        @(posedge clk);
    end

    fire <= 0;

    for(i=0; i<ROW*2; i=i+1) begin
        @(posedge clk);
    end

    $display("SIMULATION ENDED.");
    $finish;
end

endmodule
module pe_arr_tb();


parameter COL = 8;
parameter ROW = 8;
parameter SIMCYCLES = 10;

reg clk;
reg rstn;
reg fire;
reg [7:0] in_w [0 : COL-1];
reg [7:0] in_a [0 : ROW-1];
wire [31:0] outs [0 : (ROW*COL)-1];
wire outvalids [0 : (ROW*COL)-1];

integer i,j;

PE_ARR #(.ROWS(ROW), .COLS(COL)) 
	dut (.clk(clk), .rstn(rstn), 
        .fire(fire), 
        .in_w(in_w), 
        .in_a(in_a), 
        .outs(outs),
        .outvalids(outvalids));

initial forever 
begin
    `HALF_CLOCK clk = ~clk;
end

initial
begin
    clk <= 1;
    rstn <= 0;
    for(i=0; i<COL; i=i+1) begin
        in_w[i] <= 1;
        in_a[i] <= 0;
    end

    $$display("INITIALIZED.");
    
    @(posedge clk);
    
    fire <= 1;
    rstn <= 1;

    $display("STARTING SIMULATION");
    for (i=0; i<SIMCYCLES; i=i+1) begin
        for (j=0; j<COL; j=j+1) begin
            in_a[j] <= in_a[j] + 1;
        end
        @(posedge clk);
    end

    fire <= 0;

    for(i=0; i<ROW*2; i=i+1) begin
        @(posedge clk);
    end

    $display("SIMULATION ENDED.");
    $finish;
end

endmodule