data/full_repos/permissive/529394000/src/top_tb.v
1: b'%Error: data/full_repos/permissive/529394000/src/top_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n             $dumpfile("wave.vcd");\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/529394000/src/top_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n             $dumpvars(0, top_tb);\n             ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529394000/src/top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20000\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529394000/src/top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/529394000/src/top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #60000000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/529394000/src/top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n         #20000  clk = ~clk;\n         ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;




	reg clk, rst;
	wire led;

	top dut
		(
		.rst(rst),
		.clk(clk),
		.led(led)
		);





    	initial
        	begin
            	$dumpfile("wave.vcd");
            	$dumpvars(0, top_tb);
                
            	clk 		= 1'b0;
				rst		= 1'b0;
				dut.counter	<= 0;
				dut.led		<= 0;

		#20000
			rst		= 1'b1;
		#10000
			rst		= 1'b0;

		
		#60000000
			$stop;
		end




    always 
	    begin
        	#20000		clk = ~clk;
	    end
 endmodule
module top_tb;





	reg clk, rst;
	wire led;

	top dut
		(
		.rst(rst),
		.clk(clk),
		.led(led)
		);





    	initial
        	begin
            	$dumpfile("wave.vcd");
            	$dumpvars(0, top_tb);
                
            	clk 		= 1'b0;
				rst		= 1'b0;
				dut.counter	<= 0;
				dut.led		<= 0;

		#20000
			rst		= 1'b1;
		#10000
			rst		= 1'b0;

		
		#60000000
			$stop;
		end




    always 
	    begin
        	#20000		clk = ~clk;
	    end
 endmodule