data/full_repos/permissive/42434302/ivltests/pr3064375.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3064375.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #5 CLK = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3064375.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5 CLK = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3064375.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3064375.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #101;\n  ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr3064375.v:40: Unsupported or unknown PLI call: $monitor\n  $monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2);\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pr3064375;

reg		CLK;
reg		RST;

reg		Reg1;
reg		Reg2;

initial begin
  CLK = 0;
  forever begin
    #5 CLK = 1;
    #5 CLK = 0;
  end
end

initial begin
  RST = 1;
  #20;
  RST = 0;
  #101;
  $finish;
end

always @(posedge CLK or posedge RST) begin
  if (RST)
    Reg1 <= 0;
  else
    Reg1 <= !Reg1;
end

always @(negedge CLK or posedge RST) begin
  if (RST)
    Reg2 <= 0;
  else
    Reg2 <= Reg1;
end

initial begin
  $monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2);
end

endmodule
module pr3064375;


reg		CLK;
reg		RST;

reg		Reg1;
reg		Reg2;

initial begin
  CLK = 0;
  forever begin
    #5 CLK = 1;
    #5 CLK = 0;
  end
end

initial begin
  RST = 1;
  #20;
  RST = 0;
  #101;
  $finish;
end

always @(posedge CLK or posedge RST) begin
  if (RST)
    Reg1 <= 0;
  else
    Reg1 <= !Reg1;
end

always @(negedge CLK or posedge RST) begin
  if (RST)
    Reg2 <= 0;
  else
    Reg2 <= Reg1;
end

initial begin
  $monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2);
end

endmodule