data/full_repos/permissive/466874195/verilog/rtl/gen_mask.v
1: b'%Warning-WIDTH: data/full_repos/permissive/466874195/verilog/rtl/gen_mask.v:25: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'i_offset\' generates 7 bits.\n                                                                              : ... In instance gen_mask\n            o_mask[idx] <= !(i_offset > ii);\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module gen_mask #
(
    parameter SEQ_WIDTH = 40
)
(
    input  wire                     clk,
    input  wire                     rst,
    
    input  wire [6:0]               i_offset,
    output reg  [SEQ_WIDTH-1:0]     o_mask    
);

integer ii;
integer idx;

always @(posedge clk) begin
    if (rst) begin
        o_mask <= {(SEQ_WIDTH){1'b0}};
    end else begin
        for (ii = 0; ii < SEQ_WIDTH; ii++) begin
            idx = SEQ_WIDTH - 1 - ii;
            o_mask[idx] <= !(i_offset > ii);
        end
    end
end

endmodule
module gen_mask #
(
    parameter SEQ_WIDTH = 40
)
(
    input  wire                     clk,
    input  wire                     rst,
    
    input  wire [6:0]               i_offset,
    output reg  [SEQ_WIDTH-1:0]     o_mask    
);


integer ii;
integer idx;

always @(posedge clk) begin
    if (rst) begin
        o_mask <= {(SEQ_WIDTH){1'b0}};
    end else begin
        for (ii = 0; ii < SEQ_WIDTH; ii++) begin
            idx = SEQ_WIDTH - 1 - ii;
            o_mask[idx] <= !(i_offset > ii);
        end
    end
end

endmodule