data/full_repos/permissive/522534105/RTL_files/Controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522534105/RTL_files/Controller.v:112: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                               : ... In instance Controller\n                        else if  (({Q, Q_n} == 2\'b00 || 2\'b11) )\n                                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Controller(
input i_clk , 
input start  , 
input i_rst_n ,
input Q  , 
input Q_n, 
input o_assert_done  , 
output  load_Acc , 
output load_Q , 
output load_M , 
output add_sub_en ,
output sel_Mux  , 
output c_enable  , 
output i_clr_q 
);

reg [3:0] p_STATE ;
reg [3:0] n_STATE ;
reg [6:0] CV ;
assign load_Acc    = CV[0];  
assign load_Q      = CV[1]; 
assign load_M      = CV[2];
assign add_sub_en  = CV[3];
assign sel_Mux     = CV[4];
assign c_enable    = CV[5] ;
assign i_clr_q     = CV[6];

always @(posedge i_clk)
   begin
    if (~i_rst_n)
       p_STATE <= `IDLE;
         else
         p_STATE <= n_STATE ;
    end

    always @(*)
       begin
          case (p_STATE)
           `IDLE : begin 
                     if (start==1'b1)
                         n_STATE = `S1 ;
                         else
                         n_STATE = `IDLE;
                  end  
         `S1 , `S2, `S3, `S4, `S5, `S6  : begin
                        if (o_assert_done == 1'b1)
                             n_STATE = `IDLE ;
                              else
                            n_STATE = n_STATE + 1'b1 ;
                              end
            default : begin
                            n_STATE = `IDLE  ;
                        end
        endcase      
    end                                
                                                           
                                          
                      
always @(*)
   begin
      case (p_STATE )
      `IDLE : begin 
                  if (start==1'b1)
                      begin
                       CV = 7'b000_0111;
                       end 
                   else
                       begin
                        CV = 7'b0000_000;
                        end 
             end    
       `S1 , `S2, `S3, `S4, `S5, `S6 :  begin
                   if (o_assert_done==1'b1)
                          CV = 7'b1001001 ;
             else              
                   if (({Q, Q_n} == 2'b01) )
                        begin
                         CV = 7'b0010_001;
                          end
                       else if (({Q, Q_n} == 2'b10))
                         begin
                         CV = 7'b0111_001 ;
                           end 
                        else if  (({Q, Q_n} == 2'b00 || 2'b11) )
                           begin
                            CV = 7'b000_0000 ;
                          end 
                            else
                               begin
                                  CV = 7'bxxxx_xxx ;
                             end 
                  end 
            default : begin
                           CV = 7'b0000_111;
                            end
                    endcase
        end                                                                                                                                           
endmodule
module Controller(
input i_clk , 
input start  , 
input i_rst_n ,
input Q  , 
input Q_n, 
input o_assert_done  , 
output  load_Acc , 
output load_Q , 
output load_M , 
output add_sub_en ,
output sel_Mux  , 
output c_enable  , 
output i_clr_q 
);


reg [3:0] p_STATE ;
reg [3:0] n_STATE ;
reg [6:0] CV ;
assign load_Acc    = CV[0];  
assign load_Q      = CV[1]; 
assign load_M      = CV[2];
assign add_sub_en  = CV[3];
assign sel_Mux     = CV[4];
assign c_enable    = CV[5] ;
assign i_clr_q     = CV[6];

always @(posedge i_clk)
   begin
    if (~i_rst_n)
       p_STATE <= `IDLE;
         else
         p_STATE <= n_STATE ;
    end

    always @(*)
       begin
          case (p_STATE)
           `IDLE : begin 
                     if (start==1'b1)
                         n_STATE = `S1 ;
                         else
                         n_STATE = `IDLE;
                  end  
         `S1 , `S2, `S3, `S4, `S5, `S6  : begin
                        if (o_assert_done == 1'b1)
                             n_STATE = `IDLE ;
                              else
                            n_STATE = n_STATE + 1'b1 ;
                              end
            default : begin
                            n_STATE = `IDLE  ;
                        end
        endcase      
    end                                
                                                           
                                          
                      
always @(*)
   begin
      case (p_STATE )
      `IDLE : begin 
                  if (start==1'b1)
                      begin
                       CV = 7'b000_0111;
                       end 
                   else
                       begin
                        CV = 7'b0000_000;
                        end 
             end    
       `S1 , `S2, `S3, `S4, `S5, `S6 :  begin
                   if (o_assert_done==1'b1)
                          CV = 7'b1001001 ;
             else              
                   if (({Q, Q_n} == 2'b01) )
                        begin
                         CV = 7'b0010_001;
                          end
                       else if (({Q, Q_n} == 2'b10))
                         begin
                         CV = 7'b0111_001 ;
                           end 
                        else if  (({Q, Q_n} == 2'b00 || 2'b11) )
                           begin
                            CV = 7'b000_0000 ;
                          end 
                            else
                               begin
                                  CV = 7'bxxxx_xxx ;
                             end 
                  end 
            default : begin
                           CV = 7'b0000_111;
                            end
                    endcase
        end                                                                                                                                           
endmodule