data/full_repos/permissive/458841681/Basic_examples/03-toggling-LED/leds.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458841681/Basic_examples/03-toggling-LED/leds.v:26: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh80\' generates 32 or 8 bits.\n                                                                                             : ... In instance top\n     led_reg[6:0] = 128;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top( input clk,
            output wire LED0,
            output wire LED1,
            output wire LED2,
            output wire LED3,
            output wire LED4,
            output wire LED5,
            output wire LED6,
            output wire LED7 );

   reg [7:0] led_reg;
   reg [24:0] counter;

   assign LED0 = ~led_reg[0];
   assign LED1 = ~led_reg[1];
   assign LED2 = ~led_reg[2];
   assign LED3 = ~led_reg[3];
   assign LED4 = ~led_reg[4];
   assign LED5 = ~led_reg[5];
   assign LED6 = ~led_reg[6];
   assign LED7 = 1'b0;

   initial begin
     led_reg[6:0] = 128;
     counter = 0;
   end

   always @(posedge clk)
   begin
      counter <= counter + 1;
      if (counter == 12000000) begin
        led_reg[7:0] <= ~led_reg[7:0];
        counter <= 0;
      end
   end

endmodule
module top( input clk,
            output wire LED0,
            output wire LED1,
            output wire LED2,
            output wire LED3,
            output wire LED4,
            output wire LED5,
            output wire LED6,
            output wire LED7 );


   reg [7:0] led_reg;
   reg [24:0] counter;

   assign LED0 = ~led_reg[0];
   assign LED1 = ~led_reg[1];
   assign LED2 = ~led_reg[2];
   assign LED3 = ~led_reg[3];
   assign LED4 = ~led_reg[4];
   assign LED5 = ~led_reg[5];
   assign LED6 = ~led_reg[6];
   assign LED7 = 1'b0;

   initial begin
     led_reg[6:0] = 128;
     counter = 0;
   end

   always @(posedge clk)
   begin
      counter <= counter + 1;
      if (counter == 12000000) begin
        led_reg[7:0] <= ~led_reg[7:0];
        counter <= 0;
      end
   end

endmodule