data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1 (1)/PRJ0_EJEMPLO_1/rtl/SC_upCOUNTER.v
1: b'%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n        ... Looked in:\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1\n%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl/SC_upCOUNTER.v\n%Error: Exiting due to 3 error(s)\n'
module SC_upCOUNTER #(parameter upCOUNTER_DATAWIDTH=8)(

	SC_upCOUNTER_data_OutBUS,

	SC_upCOUNTER_CLOCK_50,
	SC_upCOUNTER_RESET_InHigh,
	SC_upCOUNTER_upcount_InLow
);







output		[upCOUNTER_DATAWIDTH-1:0]	SC_upCOUNTER_data_OutBUS;
input		SC_upCOUNTER_CLOCK_50;
input		SC_upCOUNTER_RESET_InHigh;
input		SC_upCOUNTER_upcount_InLow;	




reg [upCOUNTER_DATAWIDTH-1:0] upCOUNTER_Register;
reg [upCOUNTER_DATAWIDTH-1:0] upCOUNTER_Signal;




always @(*)
begin
	if (SC_upCOUNTER_upcount_InLow == 1'b0)
		upCOUNTER_Signal = upCOUNTER_Register + 1'b1;
	else
		upCOUNTER_Signal = upCOUNTER_Register;
	end	

always @(posedge SC_upCOUNTER_CLOCK_50, posedge SC_upCOUNTER_RESET_InHigh)
begin
	if (SC_upCOUNTER_RESET_InHigh == 1'b1)
		upCOUNTER_Register <= 0;
	else
		upCOUNTER_Register <= upCOUNTER_Signal;
end




assign SC_upCOUNTER_data_OutBUS = upCOUNTER_Register;

endmodule
module SC_upCOUNTER #(parameter upCOUNTER_DATAWIDTH=8)(

	SC_upCOUNTER_data_OutBUS,

	SC_upCOUNTER_CLOCK_50,
	SC_upCOUNTER_RESET_InHigh,
	SC_upCOUNTER_upcount_InLow
);








output		[upCOUNTER_DATAWIDTH-1:0]	SC_upCOUNTER_data_OutBUS;
input		SC_upCOUNTER_CLOCK_50;
input		SC_upCOUNTER_RESET_InHigh;
input		SC_upCOUNTER_upcount_InLow;	




reg [upCOUNTER_DATAWIDTH-1:0] upCOUNTER_Register;
reg [upCOUNTER_DATAWIDTH-1:0] upCOUNTER_Signal;




always @(*)
begin
	if (SC_upCOUNTER_upcount_InLow == 1'b0)
		upCOUNTER_Signal = upCOUNTER_Register + 1'b1;
	else
		upCOUNTER_Signal = upCOUNTER_Register;
	end	

always @(posedge SC_upCOUNTER_CLOCK_50, posedge SC_upCOUNTER_RESET_InHigh)
begin
	if (SC_upCOUNTER_RESET_InHigh == 1'b1)
		upCOUNTER_Register <= 0;
	else
		upCOUNTER_Register <= upCOUNTER_Signal;
end




assign SC_upCOUNTER_data_OutBUS = upCOUNTER_Register;

endmodule