data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:45: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:46: Cannot find include file: tlp.vh\n`include "tlp.vh" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:63: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:65: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:66: Define or directive not defined: \'`SIG_BARDECODE_W\'\n     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:77: Define or directive not defined: \'`SIG_LBE_W\'\n     output [`SIG_LBE_W-1:0]                              RXC_META_LDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:78: Define or directive not defined: \'`SIG_FBE_W\'\n     output [`SIG_FBE_W-1:0]                              RXC_META_FDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:79: Define or directive not defined: \'`SIG_TAG_W\'\n     output [`SIG_TAG_W-1:0]                              RXC_META_TAG,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:80: Define or directive not defined: \'`SIG_LOWADDR_W\'\n     output [`SIG_LOWADDR_W-1:0]                          RXC_META_ADDR,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:81: Define or directive not defined: \'`SIG_TYPE_W\'\n     output [`SIG_TYPE_W-1:0]                             RXC_META_TYPE,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:82: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]                              RXC_META_LENGTH,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:83: Define or directive not defined: \'`SIG_BYTECNT_W\'\n     output [`SIG_BYTECNT_W-1:0]                          RXC_META_BYTES_REMAINING,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:84: Define or directive not defined: \'`SIG_CPLID_W\'\n     output [`SIG_CPLID_W-1:0]                            RXC_META_COMPLETER_ID,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:90: Define or directive not defined: \'`SIG_OFFSET_W\'\n     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:100: Define or directive not defined: \'`SIG_FBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:100: Define or directive not defined: \'`SIG_LBE_W\'\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:100: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);\n                                                 ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:111: Define or directive not defined: \'`TLP_CPLMETADW2_I\'\n    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH);\n                                                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:111: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH);\n                                                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:115: Define or directive not defined: \'`TLP_CPLMETADW0_I\'\n    localparam C_RX_METADW0_CYCLE = (`TLP_CPLMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:115: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW0_CYCLE = (`TLP_CPLMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:116: Define or directive not defined: \'`TLP_CPLMETADW1_I\'\n    localparam C_RX_METADW1_CYCLE = (`TLP_CPLMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:116: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW1_CYCLE = (`TLP_CPLMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:117: Define or directive not defined: \'`TLP_CPLMETADW2_I\'\n    localparam C_RX_METADW2_CYCLE = (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:117: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW2_CYCLE = (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:119: Define or directive not defined: \'`TLP_CPLMETADW0_I\'\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW0_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:119: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW0_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:120: Define or directive not defined: \'`TLP_CPLMETADW1_I\'\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW1_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:120: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW1_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:121: Define or directive not defined: \'`TLP_CPLMETADW2_I\'\n    localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW2_I%C_PCI_DATA_WIDTH);\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:121: syntax error, unexpected \'%\', expecting TYPE-IDENTIFIER\n    localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW2_I%C_PCI_DATA_WIDTH);\n                                                                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:125: Define or directive not defined: \'`TLP_MAXHDR_W\'\n    localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:128: Define or directive not defined: \'`TLP_CPLADDR_W\'\n    wire [`TLP_CPLADDR_W-1:0]                             wAddr;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:129: Define or directive not defined: \'`TLP_CPLHDR_W\'\n    wire [`TLP_CPLHDR_W-1:0]                              wMetadata;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:130: Define or directive not defined: \'`TLP_TYPE_W\'\n    wire [`TLP_TYPE_W-1:0]                                wType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:131: Define or directive not defined: \'`TLP_LEN_W\'\n    wire [`TLP_LEN_W-1:0]                                 wLength;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:176: Define or directive not defined: \'`TLP_LEN_R\'\n    assign RXC_META_LENGTH = wRxcMetadata[`TLP_LEN_R];\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:176: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_LENGTH = wRxcMetadata[`TLP_LEN_R];\n                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:179: Define or directive not defined: \'`TLP_FMT_R\'\n    assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:179: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});\n                                                                       ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:179: Define or directive not defined: \'`TLP_TYPE_R\'\n    assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});\n                                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:180: Define or directive not defined: \'`TLP_CPLADDR_R\'\n    assign RXC_META_ADDR = wRxcMetadata[`TLP_CPLADDR_R];\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:180: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_ADDR = wRxcMetadata[`TLP_CPLADDR_R];\n                                                      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:181: Define or directive not defined: \'`TLP_CPLCPLID_R\'\n    assign RXC_META_COMPLETER_ID = wRxcMetadata[`TLP_CPLCPLID_R];\n                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:181: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_COMPLETER_ID = wRxcMetadata[`TLP_CPLCPLID_R];\n                                                               ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:182: Define or directive not defined: \'`TLP_CPLBYTECNT_R\'\n    assign RXC_META_BYTES_REMAINING = wRxcMetadata[`TLP_CPLBYTECNT_R];\n                                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:182: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_BYTES_REMAINING = wRxcMetadata[`TLP_CPLBYTECNT_R];\n                                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:183: Define or directive not defined: \'`TLP_CPLTAG_R\'\n    assign RXC_META_TAG = wRxcMetadata[`TLP_CPLTAG_R];\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:183: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign RXC_META_TAG = wRxcMetadata[`TLP_CPLTAG_R];\n                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/rxc_engine_classic.v:184: Define or directive not defined: \'`TLP_EP_R\'\n    assign RXC_META_EP = wRxcMetadata[`TLP_EP_R];\n                                      ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rxc_engine_128
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                                CLK,


     input                                                RST_IN,


     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
     input                                                RX_TLP_VALID,
     input                                                RX_TLP_START_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
     input                                                RX_TLP_END_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,


     output [C_PCI_DATA_WIDTH-1:0]                        RXC_DATA,
     output                                               RXC_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXC_DATA_WORD_ENABLE,
     output                                               RXC_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_START_OFFSET,
     output                                               RXC_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_END_OFFSET,

     output [`SIG_LBE_W-1:0]                              RXC_META_LDWBE,
     output [`SIG_FBE_W-1:0]                              RXC_META_FDWBE,
     output [`SIG_TAG_W-1:0]                              RXC_META_TAG,
     output [`SIG_LOWADDR_W-1:0]                          RXC_META_ADDR,
     output [`SIG_TYPE_W-1:0]                             RXC_META_TYPE,
     output [`SIG_LEN_W-1:0]                              RXC_META_LENGTH,
     output [`SIG_BYTECNT_W-1:0]                          RXC_META_BYTES_REMAINING,
     output [`SIG_CPLID_W-1:0]                            RXC_META_COMPLETER_ID,
     output                                               RXC_META_EP,


     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_START_OFFSET,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
     );



    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
    localparam C_RX_INPUT_STAGES = 1;
    localparam C_RX_OUTPUT_STAGES = 1;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_RX_HDR_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;

    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
    localparam C_STRADDLE_W = 64;
    localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
    localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;


    wire [`SIG_OFFSET_W-1:0]                              __wRxcStartOffset; 
    wire [`SIG_OFFSET_W-1:0]                              __wRxcStraddledStartOffset; 
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdr;
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrStraddled;
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrNotStraddled;
    wire                                                  __wRxcHdrStraddle;
    wire                                                  __wRxcHdrValid;
    wire                                                  __wRxcHdrSOP;
    wire                                                  __wRxcHdrSOPStraddle;


    wire                                                  _wRxcHdrValid;
    wire                                                  _wRxcHdrStraddle;
    wire                                                  _wRxcHdrSOPStraddle;
    wire                                                  _wRxcHdrSOP;
    wire [`TLP_MAXHDR_W-1:0]                              _wRxcHdr;

    wire                                                  _wRxcHdrSF;
    wire [2:0]                                            _wRxcHdrDataSoff;
    wire                                                  _wRxcHdrEF;
    wire [1:0]                                            _wRxcHdrDataEoff;
    wire                                                  _wRxcHdrSCP;
    wire                                                  _wRxcHdrMCP;
    wire                                                  _wRxcHdrRegSF;
    wire                                                  _wRxcHdrRegValid;
    wire                                                  _wRxcHdrStartFlag;
    wire                                                  _wRxcHdr3DWHSF;
    wire [3:0]                                            _wRxcHdrStartMask;
    wire [3:0]                                            _wRxcHdrEndMask;
    

    wire [`TLP_MAXHDR_W-1:0]                              wRxcHdr;
    wire                                                  wRxcHdrSF;
    wire                                                  wRxcHdrEF;    
    wire                                                  wRxcHdrValid;
    wire [63:0]                                           wRxcMetadata;
    wire [`TLP_TYPE_W-1:0]                                wRxcType;
    wire [`TLP_LEN_W-1:0]                                 wRxcLength;
    wire [2:0]                                            wRxcHdrLength;
    wire [`SIG_OFFSET_W-1:0]                              wRxcHdrStartOffset;
    wire                                                  wRxcHdrSCP;
    wire                                                  wRxcHdrMCP;
    wire [1:0]                                            wRxcHdrDataSoff;
    wire [3:0]                                            wRxcHdrStartMask;
    wire [3:0]                                            wRxcHdrEndMask;


    wire [C_PCI_DATA_WIDTH-1:0]                           wRxcData;
    wire                                                  wRxcDataValid;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxcDataWordEnable;
    wire                                                  wRxcDataStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataStartOffset;
    wire                                                  wRxcDataEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataEndOffset;
    wire [`SIG_TAG_W-1:0]                                 wRxcMetaTag;
    wire [`SIG_TYPE_W-1:0]                                wRxcMetaType;
    wire [`SIG_LOWADDR_W-1:0]                             wRxcMetaAddr;
    wire [`SIG_REQID_W-1:0]                               wRxcMetaCompleterId;
    wire [`SIG_LEN_W-1:0]                                 wRxcMetaLength;
    wire                                                  wRxcMetaEP;
    wire [`SIG_BYTECNT_W-1:0]                             wRxcMetaBytesRemaining;

    reg                                                   rStraddledSOP;
    reg                                                   rStraddledSOPSplit;    


    assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
    assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];

    assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
    assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
                                 RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
    assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
    assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
    assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);

    assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
    assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
    assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
    assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;

    assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
    assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
    assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];

    assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
    assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) | 
                         (wRxcHdrMCP & ~wRxcHdrEF);

    assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);

    assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
    assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
    assign wRxcDataStartFlag = wRxcHdrSF;
    assign wRxcDataEndFlag = wRxcHdrEF;
    assign wRxcDataStartOffset = wRxcHdrDataSoff;
    assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
    assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
    assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
    assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
    assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
    assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
    assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});

    assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
    assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
    
    always @(posedge CLK) begin
        rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];




        if(__wRxcHdrSOP | RST_IN) begin
            rStraddledSOPSplit <=0;
        end else begin
            rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
        end
        
    end
    
    mux
        #(

          .C_NUM_INPUTS                 (2),
          .C_CLOG_NUM_INPUTS            (1),
          .C_WIDTH                      (`TLP_MAXHDR_W),
          .C_MUX_TYPE                   ("SELECT")
)
    hdr_mux
        (

         .MUX_OUTPUT                    (__wRxcHdr[`TLP_MAXHDR_W-1:0]),

         .MUX_INPUTS                    ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
                                          __wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
         .MUX_SELECT                    (rStraddledSOP | rStraddledSOPSplit)
);
    
    register
        #(

          .C_WIDTH                      (64 + 1),
          .C_VALUE                      (0)
)
    hdr_register_63_0
        (

         .RD_DATA                       ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),

         .WR_DATA                       ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (64),
          .C_VALUE                      (0)
)
    hdr_register_127_64
        (

         .RD_DATA                       (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),

         .WR_DATA                       (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (2),
          .C_VALUE                      (0)
)
    sf4dwh
        (

         .RD_DATA                       ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),

         .WR_DATA                       ({rStraddledSOP,__wRxcHdrSOP}),
         .WR_EN                         (1),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));


    register
        #(

          .C_WIDTH              (128 + 4),
          .C_VALUE              (0)
)
    metadata 
        (
         .RD_DATA               ({wRxcHdr,
                                  wRxcHdrSF, wRxcHdrDataSoff,
                                  wRxcHdrEF}),

         .RST_IN                (0),
         .WR_DATA               ({_wRxcHdr,
                                  _wRxcHdrSF, _wRxcHdrDataSoff[1:0],
                                  _wRxcHdrEF}),
         .WR_EN                 (1),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH              (3+8),
          .C_VALUE              (0)
)
    metadata_valid
        (
         .RD_DATA               ({wRxcHdrValid, 
                                  wRxcHdrSCP, wRxcHdrMCP,
                                  wRxcHdrEndMask, wRxcHdrStartMask}),

         .RST_IN                (RST_IN),
         .WR_DATA               ({_wRxcHdrValid, 
                                  _wRxcHdrSCP, _wRxcHdrMCP,
                                  _wRxcHdrEndMask, _wRxcHdrStartMask}),
         .WR_EN                 (1),


         .CLK                           (CLK));

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (4)
)
    o2m_ef
        (

         .MASK                          (_wRxcHdrEndMask),

         .OFFSET_ENABLE                 (_wRxcHdrEF),
         .OFFSET                        (_wRxcHdrDataEoff)
);

    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (C_OUTPUT_STAGE_WIDTH),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
                                          RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE, 
                                          RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING, 
                                          RXC_META_LENGTH, RXC_META_EP}),
         .RD_DATA_VALID                 (RXC_DATA_VALID),

         .WR_DATA                       ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
                                          wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType, 
                                          wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
                                          wRxcMetaLength, wRxcMetaEP}),
         .WR_DATA_VALID                 (wRxcDataValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule
module rxc_engine_128
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_RX_PIPELINE_DEPTH=10
      )
    (

     input                                                CLK,


     input                                                RST_IN,


     input [C_PCI_DATA_WIDTH-1:0]                         RX_TLP,
     input                                                RX_TLP_VALID,
     input                                                RX_TLP_START_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_START_OFFSET,
     input                                                RX_TLP_END_FLAG,
     input [`SIG_OFFSET_W-1:0]                            RX_TLP_END_OFFSET,
     input [`SIG_BARDECODE_W-1:0]                         RX_TLP_BAR_DECODE,


     output [C_PCI_DATA_WIDTH-1:0]                        RXC_DATA,
     output                                               RXC_DATA_VALID,
     output [(C_PCI_DATA_WIDTH/32)-1:0]                   RXC_DATA_WORD_ENABLE,
     output                                               RXC_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_START_OFFSET,
     output                                               RXC_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]             RXC_DATA_END_OFFSET,

     output [`SIG_LBE_W-1:0]                              RXC_META_LDWBE,
     output [`SIG_FBE_W-1:0]                              RXC_META_FDWBE,
     output [`SIG_TAG_W-1:0]                              RXC_META_TAG,
     output [`SIG_LOWADDR_W-1:0]                          RXC_META_ADDR,
     output [`SIG_TYPE_W-1:0]                             RXC_META_TYPE,
     output [`SIG_LEN_W-1:0]                              RXC_META_LENGTH,
     output [`SIG_BYTECNT_W-1:0]                          RXC_META_BYTES_REMAINING,
     output [`SIG_CPLID_W-1:0]                            RXC_META_COMPLETER_ID,
     output                                               RXC_META_EP,


     input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_EOP,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_END_OFFSET,
     input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0]    RX_SR_START_OFFSET,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_SOP,
     input [C_RX_PIPELINE_DEPTH:0]                        RX_SR_VALID
     );




    localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
    localparam C_RX_INPUT_STAGES = 1;
    localparam C_RX_OUTPUT_STAGES = 1;
    localparam C_RX_COMPUTATION_STAGES = 1;
    localparam C_RX_HDR_STAGES = 1;
    localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;

    localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
    localparam C_STRADDLE_W = 64;
    localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
    localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;


    wire [`SIG_OFFSET_W-1:0]                              __wRxcStartOffset; 
    wire [`SIG_OFFSET_W-1:0]                              __wRxcStraddledStartOffset; 
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdr;
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrStraddled;
    wire [`TLP_MAXHDR_W-1:0]                              __wRxcHdrNotStraddled;
    wire                                                  __wRxcHdrStraddle;
    wire                                                  __wRxcHdrValid;
    wire                                                  __wRxcHdrSOP;
    wire                                                  __wRxcHdrSOPStraddle;


    wire                                                  _wRxcHdrValid;
    wire                                                  _wRxcHdrStraddle;
    wire                                                  _wRxcHdrSOPStraddle;
    wire                                                  _wRxcHdrSOP;
    wire [`TLP_MAXHDR_W-1:0]                              _wRxcHdr;

    wire                                                  _wRxcHdrSF;
    wire [2:0]                                            _wRxcHdrDataSoff;
    wire                                                  _wRxcHdrEF;
    wire [1:0]                                            _wRxcHdrDataEoff;
    wire                                                  _wRxcHdrSCP;
    wire                                                  _wRxcHdrMCP;
    wire                                                  _wRxcHdrRegSF;
    wire                                                  _wRxcHdrRegValid;
    wire                                                  _wRxcHdrStartFlag;
    wire                                                  _wRxcHdr3DWHSF;
    wire [3:0]                                            _wRxcHdrStartMask;
    wire [3:0]                                            _wRxcHdrEndMask;
    

    wire [`TLP_MAXHDR_W-1:0]                              wRxcHdr;
    wire                                                  wRxcHdrSF;
    wire                                                  wRxcHdrEF;    
    wire                                                  wRxcHdrValid;
    wire [63:0]                                           wRxcMetadata;
    wire [`TLP_TYPE_W-1:0]                                wRxcType;
    wire [`TLP_LEN_W-1:0]                                 wRxcLength;
    wire [2:0]                                            wRxcHdrLength;
    wire [`SIG_OFFSET_W-1:0]                              wRxcHdrStartOffset;
    wire                                                  wRxcHdrSCP;
    wire                                                  wRxcHdrMCP;
    wire [1:0]                                            wRxcHdrDataSoff;
    wire [3:0]                                            wRxcHdrStartMask;
    wire [3:0]                                            wRxcHdrEndMask;


    wire [C_PCI_DATA_WIDTH-1:0]                           wRxcData;
    wire                                                  wRxcDataValid;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]                      wRxcDataWordEnable;
    wire                                                  wRxcDataStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataStartOffset;
    wire                                                  wRxcDataEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]                wRxcDataEndOffset;
    wire [`SIG_TAG_W-1:0]                                 wRxcMetaTag;
    wire [`SIG_TYPE_W-1:0]                                wRxcMetaType;
    wire [`SIG_LOWADDR_W-1:0]                             wRxcMetaAddr;
    wire [`SIG_REQID_W-1:0]                               wRxcMetaCompleterId;
    wire [`SIG_LEN_W-1:0]                                 wRxcMetaLength;
    wire                                                  wRxcMetaEP;
    wire [`SIG_BYTECNT_W-1:0]                             wRxcMetaBytesRemaining;

    reg                                                   rStraddledSOP;
    reg                                                   rStraddledSOPSplit;    


    assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
    assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];

    assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
    assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
                                 RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
    assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
    assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
    assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);

    assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
    assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
    assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
    assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;

    assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
    assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
    assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];

    assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
    assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) | 
                         (wRxcHdrMCP & ~wRxcHdrEF);

    assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);

    assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
    assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
    assign wRxcDataStartFlag = wRxcHdrSF;
    assign wRxcDataEndFlag = wRxcHdrEF;
    assign wRxcDataStartOffset = wRxcHdrDataSoff;
    assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
    assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
    assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
    assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
    assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
    assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
    assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});

    assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
    assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
    
    always @(posedge CLK) begin
        rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];




        if(__wRxcHdrSOP | RST_IN) begin
            rStraddledSOPSplit <=0;
        end else begin
            rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
        end
        
    end
    
    mux
        #(

          .C_NUM_INPUTS                 (2),
          .C_CLOG_NUM_INPUTS            (1),
          .C_WIDTH                      (`TLP_MAXHDR_W),
          .C_MUX_TYPE                   ("SELECT")
)
    hdr_mux
        (

         .MUX_OUTPUT                    (__wRxcHdr[`TLP_MAXHDR_W-1:0]),

         .MUX_INPUTS                    ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
                                          __wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
         .MUX_SELECT                    (rStraddledSOP | rStraddledSOPSplit)
);
    
    register
        #(

          .C_WIDTH                      (64 + 1),
          .C_VALUE                      (0)
)
    hdr_register_63_0
        (

         .RD_DATA                       ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),

         .WR_DATA                       ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (64),
          .C_VALUE                      (0)
)
    hdr_register_127_64
        (

         .RD_DATA                       (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),

         .WR_DATA                       (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
         .WR_EN                         (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH                      (2),
          .C_VALUE                      (0)
)
    sf4dwh
        (

         .RD_DATA                       ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),

         .WR_DATA                       ({rStraddledSOP,__wRxcHdrSOP}),
         .WR_EN                         (1),
         .RST_IN                        (RST_IN),


         .CLK                           (CLK));


    register
        #(

          .C_WIDTH              (128 + 4),
          .C_VALUE              (0)
)
    metadata 
        (
         .RD_DATA               ({wRxcHdr,
                                  wRxcHdrSF, wRxcHdrDataSoff,
                                  wRxcHdrEF}),

         .RST_IN                (0),
         .WR_DATA               ({_wRxcHdr,
                                  _wRxcHdrSF, _wRxcHdrDataSoff[1:0],
                                  _wRxcHdrEF}),
         .WR_EN                 (1),


         .CLK                           (CLK));

    register
        #(

          .C_WIDTH              (3+8),
          .C_VALUE              (0)
)
    metadata_valid
        (
         .RD_DATA               ({wRxcHdrValid, 
                                  wRxcHdrSCP, wRxcHdrMCP,
                                  wRxcHdrEndMask, wRxcHdrStartMask}),

         .RST_IN                (RST_IN),
         .WR_DATA               ({_wRxcHdrValid, 
                                  _wRxcHdrSCP, _wRxcHdrMCP,
                                  _wRxcHdrEndMask, _wRxcHdrStartMask}),
         .WR_EN                 (1),


         .CLK                           (CLK));

    offset_to_mask
        #(
          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (4)
)
    o2m_ef
        (

         .MASK                          (_wRxcHdrEndMask),

         .OFFSET_ENABLE                 (_wRxcHdrEF),
         .OFFSET                        (_wRxcHdrDataEoff)
);

    pipeline
        #(

          .C_DEPTH                      (C_RX_OUTPUT_STAGES),
          .C_WIDTH                      (C_OUTPUT_STAGE_WIDTH),
          .C_USE_MEMORY                 (0)
)
    output_pipeline
        (

         .WR_DATA_READY                 (),
         .RD_DATA                       ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
                                          RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE, 
                                          RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING, 
                                          RXC_META_LENGTH, RXC_META_EP}),
         .RD_DATA_VALID                 (RXC_DATA_VALID),

         .WR_DATA                       ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
                                          wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType, 
                                          wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
                                          wRxcMetaLength, wRxcMetaEP}),
         .WR_DATA_VALID                 (wRxcDataValid),
         .RD_DATA_READY                 (1'b1),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule