data/full_repos/permissive/439731184/multiplexer_from_gates.v
1: b'%Error: data/full_repos/permissive/439731184/multiplexer_from_gates.v:32: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t", c0, c1, c2, c3, a, b, y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #1 c0 = ~c0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #2 c1 = ~c1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:48: Unsupported: Ignoring delay on this delayed statement.\nalways #3 c2 = ~c2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:49: Unsupported: Ignoring delay on this delayed statement.\nalways #4 c3 = ~c3;\n       ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_from_gates_tb();

reg c0, c1, c2, c3, a, b;
wire y;

mux_from_gates M (y, c0, c1, c2, c3, a, b);

initial begin
    $display("c0\tc1\tc2\tc3\ta\tb\ty");
    $monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b\t", c0, c1, c2, c3, a, b, y);
    c0 = 0;
    c1 = 0;
    c2 = 0;
    c3 = 0;
    a = 0;
    b = 0;
    #10 b = 1;
    #10 b = 0;
    a = 1;
    #10 b = 1;
    #10 $finish;
end

always #1 c0 = ~c0;
always #2 c1 = ~c1;
always #3 c2 = ~c2;
always #4 c3 = ~c3;

endmodule
module mux_from_gates_tb();


reg c0, c1, c2, c3, a, b;
wire y;

mux_from_gates M (y, c0, c1, c2, c3, a, b);

initial begin
    $display("c0\tc1\tc2\tc3\ta\tb\ty");
    $monitor("%b\t%b\t%b\t%b\t%b\t%b\t%b\t", c0, c1, c2, c3, a, b, y);
    c0 = 0;
    c1 = 0;
    c2 = 0;
    c3 = 0;
    a = 0;
    b = 0;
    #10 b = 1;
    #10 b = 0;
    a = 1;
    #10 b = 1;
    #10 $finish;
end

always #1 c0 = ~c0;
always #2 c1 = ~c1;
always #3 c2 = ~c2;
always #4 c3 = ~c3;

endmodule