data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:157: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    cfg_is_wg_d1 <= \'bx;   \n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:220: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_dat_en_1 <= \'bx;   \n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:281: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_dat_en_2 <= \'bx;   \n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:342: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_dat_en_3 <= \'bx;   \n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:460: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_pd_d1 <= \'bx;   \n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:470: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data0_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:482: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data0_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:492: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data0_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:502: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data0_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:513: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data1_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:525: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data1_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:535: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data1_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:545: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data1_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:556: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data2_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:568: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data2_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:578: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data2_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:588: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data2_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:599: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data3_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:611: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data3_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:621: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data3_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:631: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data3_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:642: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data4_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:654: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data4_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:664: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data4_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:674: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data4_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:685: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data5_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:697: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data5_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:707: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data5_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:717: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data5_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:728: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data6_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:740: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data6_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:750: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data6_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:760: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data6_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:771: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data7_d1[43:0] <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:783: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data7_d1[87:44] <= \'bx;   \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:793: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data7_d1[131:88] <= \'bx;   \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:803: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    out_rt_data7_d1[175:132] <= \'bx;   \n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v:885: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                           : ... In instance NV_NVDLA_CMAC_CORE_rt_out\n    mac2accu_mode <= \'bx;   \n                  ^~\n%Error: Exiting due to 38 warning(s)\n'
module NV_NVDLA_CMAC_CORE_rt_out (
   nvdla_core_clk
  ,nvdla_wg_clk
  ,nvdla_core_rstn
  ,cfg_is_wg
  ,cfg_reg_en
  ,out_data0
  ,out_data1
  ,out_data2
  ,out_data3
  ,out_data4
  ,out_data5
  ,out_data6
  ,out_data7
  ,out_mask
  ,out_pd
  ,out_pvld
  ,dp2reg_done
  ,mac2accu_data0
  ,mac2accu_data1
  ,mac2accu_data2
  ,mac2accu_data3
  ,mac2accu_data4
  ,mac2accu_data5
  ,mac2accu_data6
  ,mac2accu_data7
  ,mac2accu_mask
  ,mac2accu_mode
  ,mac2accu_pd
  ,mac2accu_pvld
  );

input          nvdla_core_clk;
input          nvdla_wg_clk;
input          nvdla_core_rstn;
input          cfg_is_wg;
input          cfg_reg_en;
input  [175:0] out_data0;
input  [175:0] out_data1;
input  [175:0] out_data2;
input  [175:0] out_data3;
input  [175:0] out_data4;
input  [175:0] out_data5;
input  [175:0] out_data6;
input  [175:0] out_data7;
input    [7:0] out_mask;
input    [8:0] out_pd;
input          out_pvld;
output         dp2reg_done;
output [175:0] mac2accu_data0;
output [175:0] mac2accu_data1;
output [175:0] mac2accu_data2;
output [175:0] mac2accu_data3;
output [175:0] mac2accu_data4;
output [175:0] mac2accu_data5;
output [175:0] mac2accu_data6;
output [175:0] mac2accu_data7;
output   [7:0] mac2accu_mask;
output   [7:0] mac2accu_mode;
output   [8:0] mac2accu_pd;
output         mac2accu_pvld;
wire     [7:0] out_dat_en_0;
wire           out_rt_done_d0;
reg            cfg_is_wg_d1;
reg            cfg_reg_en_d1;
reg    [175:0] mac2accu_data0;
reg    [175:0] mac2accu_data1;
reg    [175:0] mac2accu_data2;
reg    [175:0] mac2accu_data3;
reg    [175:0] mac2accu_data4;
reg    [175:0] mac2accu_data5;
reg    [175:0] mac2accu_data6;
reg    [175:0] mac2accu_data7;
reg      [7:0] mac2accu_mask;
reg      [7:0] mac2accu_mode;
reg      [8:0] mac2accu_pd;
reg            mac2accu_pvld;
reg      [7:0] out_dat_en_1;
reg      [7:0] out_dat_en_2;
reg      [7:0] out_dat_en_3;
reg            out_layer_done;
reg    [175:0] out_rt_data0_d0;
reg    [175:0] out_rt_data0_d1;
reg    [175:0] out_rt_data1_d0;
reg    [175:0] out_rt_data1_d1;
reg    [175:0] out_rt_data2_d0;
reg    [175:0] out_rt_data2_d1;
reg    [175:0] out_rt_data3_d0;
reg    [175:0] out_rt_data3_d1;
reg    [175:0] out_rt_data4_d0;
reg    [175:0] out_rt_data4_d1;
reg    [175:0] out_rt_data5_d0;
reg    [175:0] out_rt_data5_d1;
reg    [175:0] out_rt_data6_d0;
reg    [175:0] out_rt_data6_d1;
reg    [175:0] out_rt_data7_d0;
reg    [175:0] out_rt_data7_d1;
reg            out_rt_done_d1;
reg            out_rt_done_d2;
reg            out_rt_done_d3;
reg            out_rt_done_d4;
reg      [7:0] out_rt_mask_d0;
reg      [7:0] out_rt_mask_d1;
reg      [8:0] out_rt_pd_d0;
reg      [8:0] out_rt_pd_d1;
reg            out_rt_pvld_d0;
reg            out_rt_pvld_d1;

















    





always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_reg_en_d1 <= 1'b0;
  end else begin
  cfg_reg_en_d1 <= cfg_reg_en;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_is_wg_d1 <= 1'b0;
  end else begin
  if ((cfg_reg_en) == 1'b1) begin
    cfg_is_wg_d1 <= cfg_is_wg;

  end else if ((cfg_reg_en) == 1'b0) begin
  end else begin
    cfg_is_wg_d1 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif

assign out_dat_en_0 = {16 /2 {1'b1}};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_1 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_1 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_1 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_2 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_2 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_2 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_3 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_3 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_3 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif





always @(
  out_pd
  or out_pvld
  ) begin
    out_layer_done = out_pd[8:8] &
                     out_pd[6:6] &
                     out_pvld;
end

always @(
  out_pvld
  or out_mask
  or out_pd
  ) begin
    out_rt_pvld_d0 = out_pvld;
    out_rt_mask_d0 = out_mask;
    out_rt_pd_d0   = out_pd;
end


always @(
  out_data0
  or out_data1
  or out_data2
  or out_data3
  or out_data4
  or out_data5
  or out_data6
  or out_data7
  ) begin
    out_rt_data0_d0 =  out_data0;
    out_rt_data1_d0 =  out_data1;
    out_rt_data2_d0 =  out_data2;
    out_rt_data3_d0 =  out_data3;
    out_rt_data4_d0 =  out_data4;
    out_rt_data5_d0 =  out_data5;
    out_rt_data6_d0 =  out_data6;
    out_rt_data7_d0 =  out_data7;
end


always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_pvld_d1 <= 1'b0;
  end else begin
  out_rt_pvld_d1 <= out_rt_pvld_d0;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_mask_d1 <= {8{1'b0}};
  end else begin
  out_rt_mask_d1 <= out_rt_mask_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((out_rt_pvld_d0) == 1'b1) begin
    out_rt_pd_d1 <= out_rt_pd_d0;

  end else if ((out_rt_pvld_d0) == 1'b0) begin
  end else begin
    out_rt_pd_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_0[0]) == 1'b1) begin
    out_rt_data0_d1[43:0] <= out_rt_data0_d0[43:0];

  end else if ((out_rt_mask_d0[0] & out_dat_en_0[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_1[0]) == 1'b1) begin
    out_rt_data0_d1[87:44] <= out_rt_data0_d0[87:44];

  end else if ((out_rt_mask_d0[0] & out_dat_en_1[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_2[0]) == 1'b1) begin
    out_rt_data0_d1[131:88] <= out_rt_data0_d0[131:88];

  end else if ((out_rt_mask_d0[0] & out_dat_en_2[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_3[0]) == 1'b1) begin
    out_rt_data0_d1[175:132] <= out_rt_data0_d0[175:132];

  end else if ((out_rt_mask_d0[0] & out_dat_en_3[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_0[1]) == 1'b1) begin
    out_rt_data1_d1[43:0] <= out_rt_data1_d0[43:0];

  end else if ((out_rt_mask_d0[1] & out_dat_en_0[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_1[1]) == 1'b1) begin
    out_rt_data1_d1[87:44] <= out_rt_data1_d0[87:44];

  end else if ((out_rt_mask_d0[1] & out_dat_en_1[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_2[1]) == 1'b1) begin
    out_rt_data1_d1[131:88] <= out_rt_data1_d0[131:88];

  end else if ((out_rt_mask_d0[1] & out_dat_en_2[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_3[1]) == 1'b1) begin
    out_rt_data1_d1[175:132] <= out_rt_data1_d0[175:132];

  end else if ((out_rt_mask_d0[1] & out_dat_en_3[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_0[2]) == 1'b1) begin
    out_rt_data2_d1[43:0] <= out_rt_data2_d0[43:0];

  end else if ((out_rt_mask_d0[2] & out_dat_en_0[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_1[2]) == 1'b1) begin
    out_rt_data2_d1[87:44] <= out_rt_data2_d0[87:44];

  end else if ((out_rt_mask_d0[2] & out_dat_en_1[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_2[2]) == 1'b1) begin
    out_rt_data2_d1[131:88] <= out_rt_data2_d0[131:88];

  end else if ((out_rt_mask_d0[2] & out_dat_en_2[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_3[2]) == 1'b1) begin
    out_rt_data2_d1[175:132] <= out_rt_data2_d0[175:132];

  end else if ((out_rt_mask_d0[2] & out_dat_en_3[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_0[3]) == 1'b1) begin
    out_rt_data3_d1[43:0] <= out_rt_data3_d0[43:0];

  end else if ((out_rt_mask_d0[3] & out_dat_en_0[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_1[3]) == 1'b1) begin
    out_rt_data3_d1[87:44] <= out_rt_data3_d0[87:44];

  end else if ((out_rt_mask_d0[3] & out_dat_en_1[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_2[3]) == 1'b1) begin
    out_rt_data3_d1[131:88] <= out_rt_data3_d0[131:88];

  end else if ((out_rt_mask_d0[3] & out_dat_en_2[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_3[3]) == 1'b1) begin
    out_rt_data3_d1[175:132] <= out_rt_data3_d0[175:132];

  end else if ((out_rt_mask_d0[3] & out_dat_en_3[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_0[4]) == 1'b1) begin
    out_rt_data4_d1[43:0] <= out_rt_data4_d0[43:0];

  end else if ((out_rt_mask_d0[4] & out_dat_en_0[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_1[4]) == 1'b1) begin
    out_rt_data4_d1[87:44] <= out_rt_data4_d0[87:44];

  end else if ((out_rt_mask_d0[4] & out_dat_en_1[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_2[4]) == 1'b1) begin
    out_rt_data4_d1[131:88] <= out_rt_data4_d0[131:88];

  end else if ((out_rt_mask_d0[4] & out_dat_en_2[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_3[4]) == 1'b1) begin
    out_rt_data4_d1[175:132] <= out_rt_data4_d0[175:132];

  end else if ((out_rt_mask_d0[4] & out_dat_en_3[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_0[5]) == 1'b1) begin
    out_rt_data5_d1[43:0] <= out_rt_data5_d0[43:0];

  end else if ((out_rt_mask_d0[5] & out_dat_en_0[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_1[5]) == 1'b1) begin
    out_rt_data5_d1[87:44] <= out_rt_data5_d0[87:44];

  end else if ((out_rt_mask_d0[5] & out_dat_en_1[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_2[5]) == 1'b1) begin
    out_rt_data5_d1[131:88] <= out_rt_data5_d0[131:88];

  end else if ((out_rt_mask_d0[5] & out_dat_en_2[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_3[5]) == 1'b1) begin
    out_rt_data5_d1[175:132] <= out_rt_data5_d0[175:132];

  end else if ((out_rt_mask_d0[5] & out_dat_en_3[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_0[6]) == 1'b1) begin
    out_rt_data6_d1[43:0] <= out_rt_data6_d0[43:0];

  end else if ((out_rt_mask_d0[6] & out_dat_en_0[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_1[6]) == 1'b1) begin
    out_rt_data6_d1[87:44] <= out_rt_data6_d0[87:44];

  end else if ((out_rt_mask_d0[6] & out_dat_en_1[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_2[6]) == 1'b1) begin
    out_rt_data6_d1[131:88] <= out_rt_data6_d0[131:88];

  end else if ((out_rt_mask_d0[6] & out_dat_en_2[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_3[6]) == 1'b1) begin
    out_rt_data6_d1[175:132] <= out_rt_data6_d0[175:132];

  end else if ((out_rt_mask_d0[6] & out_dat_en_3[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_0[7]) == 1'b1) begin
    out_rt_data7_d1[43:0] <= out_rt_data7_d0[43:0];

  end else if ((out_rt_mask_d0[7] & out_dat_en_0[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_1[7]) == 1'b1) begin
    out_rt_data7_d1[87:44] <= out_rt_data7_d0[87:44];

  end else if ((out_rt_mask_d0[7] & out_dat_en_1[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_2[7]) == 1'b1) begin
    out_rt_data7_d1[131:88] <= out_rt_data7_d0[131:88];

  end else if ((out_rt_mask_d0[7] & out_dat_en_2[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_3[7]) == 1'b1) begin
    out_rt_data7_d1[175:132] <= out_rt_data7_d0[175:132];

  end else if ((out_rt_mask_d0[7] & out_dat_en_3[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[175:132] <= 'bx;

  end
end



always @(
  out_rt_pvld_d1
  or out_rt_mask_d1
  or out_rt_pd_d1
  ) begin
    mac2accu_pvld = out_rt_pvld_d1;
    mac2accu_mask = out_rt_mask_d1;
    mac2accu_pd = out_rt_pd_d1;
end


always @(
  out_rt_data0_d1
  or out_rt_data1_d1
  or out_rt_data2_d1
  or out_rt_data3_d1
  or out_rt_data4_d1
  or out_rt_data5_d1
  or out_rt_data6_d1
  or out_rt_data7_d1
  ) begin
    mac2accu_data0 = out_rt_data0_d1;
    mac2accu_data1 = out_rt_data1_d1;
    mac2accu_data2 = out_rt_data2_d1;
    mac2accu_data3 = out_rt_data3_d1;
    mac2accu_data4 = out_rt_data4_d1;
    mac2accu_data5 = out_rt_data5_d1;
    mac2accu_data6 = out_rt_data6_d1;
    mac2accu_data7 = out_rt_data7_d1;
end



assign out_rt_done_d0 = out_layer_done;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d1 <= 1'b0;
  end else begin
  out_rt_done_d1 <= out_rt_done_d0;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d2 <= 1'b0;
  end else begin
  out_rt_done_d2 <= out_rt_done_d1;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d3 <= 1'b0;
  end else begin
  out_rt_done_d3 <= out_rt_done_d2;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d4 <= 1'b0;
  end else begin
  out_rt_done_d4 <= out_rt_done_d3;
  end
end


assign dp2reg_done = out_rt_done_d4;

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mode <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    mac2accu_mode <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    mac2accu_mode <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif







endmodule
module NV_NVDLA_CMAC_CORE_rt_out (
   nvdla_core_clk
  ,nvdla_wg_clk
  ,nvdla_core_rstn
  ,cfg_is_wg
  ,cfg_reg_en
  ,out_data0
  ,out_data1
  ,out_data2
  ,out_data3
  ,out_data4
  ,out_data5
  ,out_data6
  ,out_data7
  ,out_mask
  ,out_pd
  ,out_pvld
  ,dp2reg_done
  ,mac2accu_data0
  ,mac2accu_data1
  ,mac2accu_data2
  ,mac2accu_data3
  ,mac2accu_data4
  ,mac2accu_data5
  ,mac2accu_data6
  ,mac2accu_data7
  ,mac2accu_mask
  ,mac2accu_mode
  ,mac2accu_pd
  ,mac2accu_pvld
  );


input          nvdla_core_clk;
input          nvdla_wg_clk;
input          nvdla_core_rstn;
input          cfg_is_wg;
input          cfg_reg_en;
input  [175:0] out_data0;
input  [175:0] out_data1;
input  [175:0] out_data2;
input  [175:0] out_data3;
input  [175:0] out_data4;
input  [175:0] out_data5;
input  [175:0] out_data6;
input  [175:0] out_data7;
input    [7:0] out_mask;
input    [8:0] out_pd;
input          out_pvld;
output         dp2reg_done;
output [175:0] mac2accu_data0;
output [175:0] mac2accu_data1;
output [175:0] mac2accu_data2;
output [175:0] mac2accu_data3;
output [175:0] mac2accu_data4;
output [175:0] mac2accu_data5;
output [175:0] mac2accu_data6;
output [175:0] mac2accu_data7;
output   [7:0] mac2accu_mask;
output   [7:0] mac2accu_mode;
output   [8:0] mac2accu_pd;
output         mac2accu_pvld;
wire     [7:0] out_dat_en_0;
wire           out_rt_done_d0;
reg            cfg_is_wg_d1;
reg            cfg_reg_en_d1;
reg    [175:0] mac2accu_data0;
reg    [175:0] mac2accu_data1;
reg    [175:0] mac2accu_data2;
reg    [175:0] mac2accu_data3;
reg    [175:0] mac2accu_data4;
reg    [175:0] mac2accu_data5;
reg    [175:0] mac2accu_data6;
reg    [175:0] mac2accu_data7;
reg      [7:0] mac2accu_mask;
reg      [7:0] mac2accu_mode;
reg      [8:0] mac2accu_pd;
reg            mac2accu_pvld;
reg      [7:0] out_dat_en_1;
reg      [7:0] out_dat_en_2;
reg      [7:0] out_dat_en_3;
reg            out_layer_done;
reg    [175:0] out_rt_data0_d0;
reg    [175:0] out_rt_data0_d1;
reg    [175:0] out_rt_data1_d0;
reg    [175:0] out_rt_data1_d1;
reg    [175:0] out_rt_data2_d0;
reg    [175:0] out_rt_data2_d1;
reg    [175:0] out_rt_data3_d0;
reg    [175:0] out_rt_data3_d1;
reg    [175:0] out_rt_data4_d0;
reg    [175:0] out_rt_data4_d1;
reg    [175:0] out_rt_data5_d0;
reg    [175:0] out_rt_data5_d1;
reg    [175:0] out_rt_data6_d0;
reg    [175:0] out_rt_data6_d1;
reg    [175:0] out_rt_data7_d0;
reg    [175:0] out_rt_data7_d1;
reg            out_rt_done_d1;
reg            out_rt_done_d2;
reg            out_rt_done_d3;
reg            out_rt_done_d4;
reg      [7:0] out_rt_mask_d0;
reg      [7:0] out_rt_mask_d1;
reg      [8:0] out_rt_pd_d0;
reg      [8:0] out_rt_pd_d1;
reg            out_rt_pvld_d0;
reg            out_rt_pvld_d1;

















    





always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_reg_en_d1 <= 1'b0;
  end else begin
  cfg_reg_en_d1 <= cfg_reg_en;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_is_wg_d1 <= 1'b0;
  end else begin
  if ((cfg_reg_en) == 1'b1) begin
    cfg_is_wg_d1 <= cfg_is_wg;

  end else if ((cfg_reg_en) == 1'b0) begin
  end else begin
    cfg_is_wg_d1 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif

assign out_dat_en_0 = {16 /2 {1'b1}};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_1 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_1 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_1 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_2 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_2 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_2 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_dat_en_3 <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    out_dat_en_3 <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    out_dat_en_3 <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif





always @(
  out_pd
  or out_pvld
  ) begin
    out_layer_done = out_pd[8:8] &
                     out_pd[6:6] &
                     out_pvld;
end

always @(
  out_pvld
  or out_mask
  or out_pd
  ) begin
    out_rt_pvld_d0 = out_pvld;
    out_rt_mask_d0 = out_mask;
    out_rt_pd_d0   = out_pd;
end


always @(
  out_data0
  or out_data1
  or out_data2
  or out_data3
  or out_data4
  or out_data5
  or out_data6
  or out_data7
  ) begin
    out_rt_data0_d0 =  out_data0;
    out_rt_data1_d0 =  out_data1;
    out_rt_data2_d0 =  out_data2;
    out_rt_data3_d0 =  out_data3;
    out_rt_data4_d0 =  out_data4;
    out_rt_data5_d0 =  out_data5;
    out_rt_data6_d0 =  out_data6;
    out_rt_data7_d0 =  out_data7;
end


always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_pvld_d1 <= 1'b0;
  end else begin
  out_rt_pvld_d1 <= out_rt_pvld_d0;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_mask_d1 <= {8{1'b0}};
  end else begin
  out_rt_mask_d1 <= out_rt_mask_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((out_rt_pvld_d0) == 1'b1) begin
    out_rt_pd_d1 <= out_rt_pd_d0;

  end else if ((out_rt_pvld_d0) == 1'b0) begin
  end else begin
    out_rt_pd_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_0[0]) == 1'b1) begin
    out_rt_data0_d1[43:0] <= out_rt_data0_d0[43:0];

  end else if ((out_rt_mask_d0[0] & out_dat_en_0[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_1[0]) == 1'b1) begin
    out_rt_data0_d1[87:44] <= out_rt_data0_d0[87:44];

  end else if ((out_rt_mask_d0[0] & out_dat_en_1[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_2[0]) == 1'b1) begin
    out_rt_data0_d1[131:88] <= out_rt_data0_d0[131:88];

  end else if ((out_rt_mask_d0[0] & out_dat_en_2[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[0] & out_dat_en_3[0]) == 1'b1) begin
    out_rt_data0_d1[175:132] <= out_rt_data0_d0[175:132];

  end else if ((out_rt_mask_d0[0] & out_dat_en_3[0]) == 1'b0) begin
  end else begin
    out_rt_data0_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_0[1]) == 1'b1) begin
    out_rt_data1_d1[43:0] <= out_rt_data1_d0[43:0];

  end else if ((out_rt_mask_d0[1] & out_dat_en_0[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_1[1]) == 1'b1) begin
    out_rt_data1_d1[87:44] <= out_rt_data1_d0[87:44];

  end else if ((out_rt_mask_d0[1] & out_dat_en_1[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_2[1]) == 1'b1) begin
    out_rt_data1_d1[131:88] <= out_rt_data1_d0[131:88];

  end else if ((out_rt_mask_d0[1] & out_dat_en_2[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[1] & out_dat_en_3[1]) == 1'b1) begin
    out_rt_data1_d1[175:132] <= out_rt_data1_d0[175:132];

  end else if ((out_rt_mask_d0[1] & out_dat_en_3[1]) == 1'b0) begin
  end else begin
    out_rt_data1_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_0[2]) == 1'b1) begin
    out_rt_data2_d1[43:0] <= out_rt_data2_d0[43:0];

  end else if ((out_rt_mask_d0[2] & out_dat_en_0[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_1[2]) == 1'b1) begin
    out_rt_data2_d1[87:44] <= out_rt_data2_d0[87:44];

  end else if ((out_rt_mask_d0[2] & out_dat_en_1[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_2[2]) == 1'b1) begin
    out_rt_data2_d1[131:88] <= out_rt_data2_d0[131:88];

  end else if ((out_rt_mask_d0[2] & out_dat_en_2[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[2] & out_dat_en_3[2]) == 1'b1) begin
    out_rt_data2_d1[175:132] <= out_rt_data2_d0[175:132];

  end else if ((out_rt_mask_d0[2] & out_dat_en_3[2]) == 1'b0) begin
  end else begin
    out_rt_data2_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_0[3]) == 1'b1) begin
    out_rt_data3_d1[43:0] <= out_rt_data3_d0[43:0];

  end else if ((out_rt_mask_d0[3] & out_dat_en_0[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_1[3]) == 1'b1) begin
    out_rt_data3_d1[87:44] <= out_rt_data3_d0[87:44];

  end else if ((out_rt_mask_d0[3] & out_dat_en_1[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_2[3]) == 1'b1) begin
    out_rt_data3_d1[131:88] <= out_rt_data3_d0[131:88];

  end else if ((out_rt_mask_d0[3] & out_dat_en_2[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[3] & out_dat_en_3[3]) == 1'b1) begin
    out_rt_data3_d1[175:132] <= out_rt_data3_d0[175:132];

  end else if ((out_rt_mask_d0[3] & out_dat_en_3[3]) == 1'b0) begin
  end else begin
    out_rt_data3_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_0[4]) == 1'b1) begin
    out_rt_data4_d1[43:0] <= out_rt_data4_d0[43:0];

  end else if ((out_rt_mask_d0[4] & out_dat_en_0[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_1[4]) == 1'b1) begin
    out_rt_data4_d1[87:44] <= out_rt_data4_d0[87:44];

  end else if ((out_rt_mask_d0[4] & out_dat_en_1[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_2[4]) == 1'b1) begin
    out_rt_data4_d1[131:88] <= out_rt_data4_d0[131:88];

  end else if ((out_rt_mask_d0[4] & out_dat_en_2[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[4] & out_dat_en_3[4]) == 1'b1) begin
    out_rt_data4_d1[175:132] <= out_rt_data4_d0[175:132];

  end else if ((out_rt_mask_d0[4] & out_dat_en_3[4]) == 1'b0) begin
  end else begin
    out_rt_data4_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_0[5]) == 1'b1) begin
    out_rt_data5_d1[43:0] <= out_rt_data5_d0[43:0];

  end else if ((out_rt_mask_d0[5] & out_dat_en_0[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_1[5]) == 1'b1) begin
    out_rt_data5_d1[87:44] <= out_rt_data5_d0[87:44];

  end else if ((out_rt_mask_d0[5] & out_dat_en_1[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_2[5]) == 1'b1) begin
    out_rt_data5_d1[131:88] <= out_rt_data5_d0[131:88];

  end else if ((out_rt_mask_d0[5] & out_dat_en_2[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[5] & out_dat_en_3[5]) == 1'b1) begin
    out_rt_data5_d1[175:132] <= out_rt_data5_d0[175:132];

  end else if ((out_rt_mask_d0[5] & out_dat_en_3[5]) == 1'b0) begin
  end else begin
    out_rt_data5_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_0[6]) == 1'b1) begin
    out_rt_data6_d1[43:0] <= out_rt_data6_d0[43:0];

  end else if ((out_rt_mask_d0[6] & out_dat_en_0[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_1[6]) == 1'b1) begin
    out_rt_data6_d1[87:44] <= out_rt_data6_d0[87:44];

  end else if ((out_rt_mask_d0[6] & out_dat_en_1[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_2[6]) == 1'b1) begin
    out_rt_data6_d1[131:88] <= out_rt_data6_d0[131:88];

  end else if ((out_rt_mask_d0[6] & out_dat_en_2[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[6] & out_dat_en_3[6]) == 1'b1) begin
    out_rt_data6_d1[175:132] <= out_rt_data6_d0[175:132];

  end else if ((out_rt_mask_d0[6] & out_dat_en_3[6]) == 1'b0) begin
  end else begin
    out_rt_data6_d1[175:132] <= 'bx;

  end
end

always @(posedge nvdla_core_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_0[7]) == 1'b1) begin
    out_rt_data7_d1[43:0] <= out_rt_data7_d0[43:0];

  end else if ((out_rt_mask_d0[7] & out_dat_en_0[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[43:0] <= 'bx;

  end
end


always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_1[7]) == 1'b1) begin
    out_rt_data7_d1[87:44] <= out_rt_data7_d0[87:44];

  end else if ((out_rt_mask_d0[7] & out_dat_en_1[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[87:44] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_2[7]) == 1'b1) begin
    out_rt_data7_d1[131:88] <= out_rt_data7_d0[131:88];

  end else if ((out_rt_mask_d0[7] & out_dat_en_2[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[131:88] <= 'bx;

  end
end
always @(posedge nvdla_wg_clk) begin
  if ((out_rt_mask_d0[7] & out_dat_en_3[7]) == 1'b1) begin
    out_rt_data7_d1[175:132] <= out_rt_data7_d0[175:132];

  end else if ((out_rt_mask_d0[7] & out_dat_en_3[7]) == 1'b0) begin
  end else begin
    out_rt_data7_d1[175:132] <= 'bx;

  end
end



always @(
  out_rt_pvld_d1
  or out_rt_mask_d1
  or out_rt_pd_d1
  ) begin
    mac2accu_pvld = out_rt_pvld_d1;
    mac2accu_mask = out_rt_mask_d1;
    mac2accu_pd = out_rt_pd_d1;
end


always @(
  out_rt_data0_d1
  or out_rt_data1_d1
  or out_rt_data2_d1
  or out_rt_data3_d1
  or out_rt_data4_d1
  or out_rt_data5_d1
  or out_rt_data6_d1
  or out_rt_data7_d1
  ) begin
    mac2accu_data0 = out_rt_data0_d1;
    mac2accu_data1 = out_rt_data1_d1;
    mac2accu_data2 = out_rt_data2_d1;
    mac2accu_data3 = out_rt_data3_d1;
    mac2accu_data4 = out_rt_data4_d1;
    mac2accu_data5 = out_rt_data5_d1;
    mac2accu_data6 = out_rt_data6_d1;
    mac2accu_data7 = out_rt_data7_d1;
end



assign out_rt_done_d0 = out_layer_done;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d1 <= 1'b0;
  end else begin
  out_rt_done_d1 <= out_rt_done_d0;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d2 <= 1'b0;
  end else begin
  out_rt_done_d2 <= out_rt_done_d1;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d3 <= 1'b0;
  end else begin
  out_rt_done_d3 <= out_rt_done_d2;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_rt_done_d4 <= 1'b0;
  end else begin
  out_rt_done_d4 <= out_rt_done_d3;
  end
end


assign dp2reg_done = out_rt_done_d4;

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mode <= {8{1'b0}};
  end else begin
  if ((cfg_reg_en_d1) == 1'b1) begin
    mac2accu_mode <= {8{cfg_is_wg_d1}};

  end else if ((cfg_reg_en_d1) == 1'b0) begin
  end else begin
    mac2accu_mode <= 'bx;

  end
  end
end
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1,  (^(cfg_reg_en_d1)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif







endmodule