data/full_repos/permissive/502544928/cache_wrapper.v
1: b"%Error: data/full_repos/permissive/502544928/cache_wrapper.v:58: Cannot find file containing module: 'direct_mapped_cache'\ndirect_mapped_cache #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) CACHE (\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/direct_mapped_cache\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/direct_mapped_cache.v\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/direct_mapped_cache.sv\n             direct_mapped_cache\n             direct_mapped_cache.v\n             direct_mapped_cache.sv\n             obj_dir/direct_mapped_cache\n             obj_dir/direct_mapped_cache.v\n             obj_dir/direct_mapped_cache.sv\n%Error: Exiting due to 1 error(s)\n"
module cache_wrapper #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, 
                     OFFSET_BITS = 3, ADDRESS_BITS = 20, MSG_BITS = 4) (
				     clock, reset,  

				     read, write, address, in_data, 
				     out_addr, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
);

input clock, reset; 

input read, write;
input [ADDRESS_BITS-1:0] address;
input [DATA_WIDTH-1:0] in_data;
output valid, ready;
output[ADDRESS_BITS-1:0] out_addr;
output[DATA_WIDTH-1:0] out_data;


input [MSG_BITS-1:0]      mem2cache_msg; 
input [ADDRESS_BITS-1:0]  mem2cache_address; 
input [DATA_WIDTH-1:0]    mem2cache_data;
 				     
output [MSG_BITS-1:0]     cache2mem_msg; 
output [ADDRESS_BITS-1:0] cache2mem_address; 
output [DATA_WIDTH-1:0]   cache2mem_data; 

input  report;

direct_mapped_cache #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) CACHE (
				     clock, reset,  

				     read, write, address, in_data, 
				     out_addr, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
);

endmodule
module cache_wrapper #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6, 
                     OFFSET_BITS = 3, ADDRESS_BITS = 20, MSG_BITS = 4) (
				     clock, reset,  

				     read, write, address, in_data, 
				     out_addr, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
);


input clock, reset; 

input read, write;
input [ADDRESS_BITS-1:0] address;
input [DATA_WIDTH-1:0] in_data;
output valid, ready;
output[ADDRESS_BITS-1:0] out_addr;
output[DATA_WIDTH-1:0] out_data;


input [MSG_BITS-1:0]      mem2cache_msg; 
input [ADDRESS_BITS-1:0]  mem2cache_address; 
input [DATA_WIDTH-1:0]    mem2cache_data;
 				     
output [MSG_BITS-1:0]     cache2mem_msg; 
output [ADDRESS_BITS-1:0] cache2mem_address; 
output [DATA_WIDTH-1:0]   cache2mem_data; 

input  report;

direct_mapped_cache #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) CACHE (
				     clock, reset,  

				     read, write, address, in_data, 
				     out_addr, out_data, valid, ready,
				     

				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
);

endmodule