data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_csc_1.v
1: b"%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_csc_1.v:93: Cannot find file containing module: 'ad_csc_1_mul'\n  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_csc_1_mul\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_csc_1_mul.v\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_csc_1_mul.sv\n             ad_csc_1_mul\n             ad_csc_1_mul.v\n             ad_csc_1_mul.sv\n             obj_dir/ad_csc_1_mul\n             obj_dir/ad_csc_1_mul.v\n             obj_dir/ad_csc_1_mul.sv\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_csc_1.v:103: Cannot find file containing module: 'ad_csc_1_mul'\n  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_csc_1.v:113: Cannot find file containing module: 'ad_csc_1_mul'\n  ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_csc_1.v:123: Cannot find file containing module: 'ad_csc_1_add'\n  ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (\n  ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ad_csc_1 (



  clk,
  sync,
  data,



  C1,
  C2,
  C3,
  C4,



  csc_sync_1,
  csc_data_1);



  parameter   DELAY_DATA_WIDTH = 16;
  localparam  DW = DELAY_DATA_WIDTH - 1;



  input           clk;
  input   [DW:0]  sync;
  input   [23:0]  data;



  input   [16:0]  C1;
  input   [16:0]  C2;
  input   [16:0]  C3;
  input   [24:0]  C4;



  output  [DW:0]  csc_sync_1;
  output  [ 7:0]  csc_data_1;



  wire    [24:0]  data_1_m_s;
  wire    [24:0]  data_2_m_s;
  wire    [24:0]  data_3_m_s;
  wire    [DW:0]  sync_3_m_s;



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
    .clk (clk),
    .data_a (C1),
    .data_b (data[23:16]),
    .data_p (data_1_m_s),
    .ddata_in (1'd0),
    .ddata_out ());



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
    .clk (clk),
    .data_a (C2),
    .data_b (data[15:8]),
    .data_p (data_2_m_s),
    .ddata_in (1'd0),
    .ddata_out ());



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
    .clk (clk),
    .data_a (C3),
    .data_b (data[7:0]),
    .data_p (data_3_m_s),
    .ddata_in (sync),
    .ddata_out (sync_3_m_s));



  ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
    .clk (clk),
    .data_1 (data_1_m_s),
    .data_2 (data_2_m_s),
    .data_3 (data_3_m_s),
    .data_4 (C4),
    .data_p (csc_data_1),
    .ddata_in (sync_3_m_s),
    .ddata_out (csc_sync_1));

endmodule
module ad_csc_1 (



  clk,
  sync,
  data,



  C1,
  C2,
  C3,
  C4,



  csc_sync_1,
  csc_data_1);




  parameter   DELAY_DATA_WIDTH = 16;
  localparam  DW = DELAY_DATA_WIDTH - 1;



  input           clk;
  input   [DW:0]  sync;
  input   [23:0]  data;



  input   [16:0]  C1;
  input   [16:0]  C2;
  input   [16:0]  C3;
  input   [24:0]  C4;



  output  [DW:0]  csc_sync_1;
  output  [ 7:0]  csc_data_1;



  wire    [24:0]  data_1_m_s;
  wire    [24:0]  data_2_m_s;
  wire    [24:0]  data_3_m_s;
  wire    [DW:0]  sync_3_m_s;



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
    .clk (clk),
    .data_a (C1),
    .data_b (data[23:16]),
    .data_p (data_1_m_s),
    .ddata_in (1'd0),
    .ddata_out ());



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
    .clk (clk),
    .data_a (C2),
    .data_b (data[15:8]),
    .data_p (data_2_m_s),
    .ddata_in (1'd0),
    .ddata_out ());



  ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
    .clk (clk),
    .data_a (C3),
    .data_b (data[7:0]),
    .data_p (data_3_m_s),
    .ddata_in (sync),
    .ddata_out (sync_3_m_s));



  ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
    .clk (clk),
    .data_1 (data_1_m_s),
    .data_2 (data_2_m_s),
    .data_3 (data_3_m_s),
    .data_4 (C4),
    .data_p (csc_data_1),
    .ddata_in (sync_3_m_s),
    .ddata_out (csc_sync_1));

endmodule