data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/phasedet_ck1x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/phasedet_ck1x.v:59: Cannot find file containing module: 'atmux1'\natmux1 scmux\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro,data/full_repos/permissive/530013823/atmux1\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro,data/full_repos/permissive/530013823/atmux1.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro,data/full_repos/permissive/530013823/atmux1.sv\n             atmux1\n             atmux1.v\n             atmux1.sv\n             obj_dir/atmux1\n             obj_dir/atmux1.v\n             obj_dir/atmux1.sv\n%Error: Exiting due to 1 error(s)\n"
module phasedet_ck1x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     phaseout
     );



input   rst1x_,
        rst2x_,
        clk2x,
        clk1x;

input   scanmode;

output  phaseout;



















`ifndef RTL_FPGA_STYLE
reg     phaseout;
wire    rstq1x_;

atmux1 scmux
    (
     .a     (rst1x_),
     .b     ((!phaseout) & rst1x_),
     .sela  (scanmode),
     .o     (rstq1x_)
     );

reg     q1x;
always @(posedge clk1x or negedge rstq1x_)
    if(!rstq1x_)    q1x <= 1'b0;
    else            q1x <= 1'b1;


always @(posedge clk2x or negedge rst2x_)
    if(!rst2x_) phaseout    <= 1'b0;
    else        phaseout    <= q1x;



`else
reg                 phaseout;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if (!rst2x_)    phaseout <= 1'b0;
    else            phaseout <= clk1x;
    end

`endif
endmodule
module phasedet_ck1x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     phaseout
     );




input   rst1x_,
        rst2x_,
        clk2x,
        clk1x;

input   scanmode;

output  phaseout;



















`ifndef RTL_FPGA_STYLE
reg     phaseout;
wire    rstq1x_;

atmux1 scmux
    (
     .a     (rst1x_),
     .b     ((!phaseout) & rst1x_),
     .sela  (scanmode),
     .o     (rstq1x_)
     );

reg     q1x;
always @(posedge clk1x or negedge rstq1x_)
    if(!rstq1x_)    q1x <= 1'b0;
    else            q1x <= 1'b1;


always @(posedge clk2x or negedge rst2x_)
    if(!rst2x_) phaseout    <= 1'b0;
    else        phaseout    <= q1x;



`else
reg                 phaseout;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if (!rst2x_)    phaseout <= 1'b0;
    else            phaseout <= clk1x;
    end

`endif
endmodule