data/full_repos/permissive/448780010/code/tools.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/448780010/code/tools.v:14: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'decoder_2_4\'\nmodule decoder_2_4(\n       ^~~~~~~~~~~\n                                                                       : ... Top module \'decoder_4_16\'\nmodule decoder_4_16(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'decoder_5_32\'\nmodule decoder_5_32(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'decoder_6_64\'\nmodule decoder_6_64(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_r\'\nmodule fifo_buffer_r #(\n       ^~~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_w\'\nmodule fifo_buffer_w #(\n       ^~~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_data\'\nmodule fifo_buffer_data #(\n       ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/448780010/code/tools.v:265: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'related_valid\' generates 5 bits.\n                                                                     : ... In instance fifo_buffer_data\n        assign related_valid[i] = valid[i] && (related_valid == buff[i][RELA_WIDTH - 1:0]);\n                                                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module fifo_buffer_r #(
    parameter DATA_WIDTH = 32,
    parameter BUFF_DEPTH = 5,
    parameter ADDR_WIDTH = 3
)(
    input                     clk,
    input                     resetn,
    input                     wen,
    input                     ren,
    output                    empty,
    output                    full,
    input  [DATA_WIDTH - 1:0] input_data,
    output [DATA_WIDTH - 1:0] output_data
);
    
    reg [DATA_WIDTH - 1:0] buff [BUFF_DEPTH - 1:0];
    reg [ADDR_WIDTH - 1:0] head;
    reg [ADDR_WIDTH - 1:0] tail;
    reg [ADDR_WIDTH - 1:0] count;

    wire do_read;
    wire do_write;

    assign do_read  = ren && !empty;
    assign do_write = wen && !full;

    assign empty       = count == 0;
    assign full        = count == (BUFF_DEPTH - 1);
    assign output_data = buff[tail];

    always @(posedge clk ) begin
        if(!resetn) begin
            count <= 0;
        end
        else if(do_read && !do_write) begin
            count <= count - 1;
        end
        else if(!do_read && do_write) begin
            count <= count + 1;
        end
    end

    always @(posedge clk ) begin
        if(!resetn) begin
            head <= 0;
        end
        else if(do_write) begin
            if(head == (BUFF_DEPTH - 1)) begin
                head <= 0;
            end
            else begin
                head <= head + 1;
            end
        end
    end

    always @(posedge clk ) begin
        if(!resetn) begin
            tail <= 0;
        end
        else if(do_read) begin
            if(tail == (BUFF_DEPTH - 1)) begin
                tail <= 0;
            end
            else begin
                tail <= tail + 1;
            end
        end
    end

    genvar i;
    generate for (i = 0; i < BUFF_DEPTH; i = i + 1) begin:gen_buff
        always @ (posedge clk) begin
            if (!resetn) begin
                buff[i] <= 0;
            end else if (do_read && tail == i) begin
                buff[i] <= 0;
            end else if (do_write && head == i) begin
                buff[i] <= input_data;
            end
        end
    end endgenerate

endmodule
module fifo_buffer_r #(
    parameter DATA_WIDTH = 32,
    parameter BUFF_DEPTH = 5,
    parameter ADDR_WIDTH = 3
)(
    input                     clk,
    input                     resetn,
    input                     wen,
    input                     ren,
    output                    empty,
    output                    full,
    input  [DATA_WIDTH - 1:0] input_data,
    output [DATA_WIDTH - 1:0] output_data
);

    
    reg [DATA_WIDTH - 1:0] buff [BUFF_DEPTH - 1:0];
    reg [ADDR_WIDTH - 1:0] head;
    reg [ADDR_WIDTH - 1:0] tail;
    reg [ADDR_WIDTH - 1:0] count;

    wire do_read;
    wire do_write;

    assign do_read  = ren && !empty;
    assign do_write = wen && !full;

    assign empty       = count == 0;
    assign full        = count == (BUFF_DEPTH - 1);
    assign output_data = buff[tail];

    always @(posedge clk ) begin
        if(!resetn) begin
            count <= 0;
        end
        else if(do_read && !do_write) begin
            count <= count - 1;
        end
        else if(!do_read && do_write) begin
            count <= count + 1;
        end
    end

    always @(posedge clk ) begin
        if(!resetn) begin
            head <= 0;
        end
        else if(do_write) begin
            if(head == (BUFF_DEPTH - 1)) begin
                head <= 0;
            end
            else begin
                head <= head + 1;
            end
        end
    end

    always @(posedge clk ) begin
        if(!resetn) begin
            tail <= 0;
        end
        else if(do_read) begin
            if(tail == (BUFF_DEPTH - 1)) begin
                tail <= 0;
            end
            else begin
                tail <= tail + 1;
            end
        end
    end

    genvar i;
    generate for (i = 0; i < BUFF_DEPTH; i = i + 1) begin:gen_buff
        always @ (posedge clk) begin
            if (!resetn) begin
                buff[i] <= 0;
            end else if (do_read && tail == i) begin
                buff[i] <= 0;
            end else if (do_write && head == i) begin
                buff[i] <= input_data;
            end
        end
    end endgenerate

endmodule