data/full_repos/permissive/413345709/Project/top.v
1: b"%Error: data/full_repos/permissive/413345709/Project/top.v:11: Cannot find file containing module: 'clock_divider'\nclock_divider cl25(reset, clk, clk25);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413345709/Project,data/full_repos/permissive/413345709/clock_divider\n             data/full_repos/permissive/413345709/Project,data/full_repos/permissive/413345709/clock_divider.v\n             data/full_repos/permissive/413345709/Project,data/full_repos/permissive/413345709/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/413345709/Project/top.v:12: Cannot find file containing module: 'HorizontalCnt'\nHorizontalCnt hcnt(clk25, reset, Hcount, Venable);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413345709/Project/top.v:13: Cannot find file containing module: 'VerticalCnt'\nVerticalCnt vcnt(clk25, reset, Venable, Vcount);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/413345709/Project/top.v:14: Cannot find file containing module: 'kbd_protocol'\nkbd_protocol kbdp (reset, clk25, ps2clk, ps2data, scancode, found);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413345709/Project/top.v:15: Cannot find file containing module: 'vgasync'\nvgasync vga(reset, clk25, Hcount, Vcount, hsync, vsync, red, green, blue, scancode, found);\n^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module top(reset, clk, ps2clk, ps2data, hsync, vsync, red, green, blue);
input reset, clk;
input ps2clk, ps2data;
output hsync, vsync;
output [2:0] red, green, blue;
wire [9:0] Hcount;
wire [8:0] Vcount;
wire clk25;
wire found;
wire [7:0]scancode;
clock_divider cl25(reset, clk, clk25);
HorizontalCnt hcnt(clk25, reset, Hcount, Venable);
VerticalCnt vcnt(clk25, reset, Venable, Vcount);
kbd_protocol kbdp (reset, clk25, ps2clk, ps2data, scancode, found);
vgasync vga(reset, clk25, Hcount, Vcount, hsync, vsync, red, green, blue, scancode, found);
endmodule
module top(reset, clk, ps2clk, ps2data, hsync, vsync, red, green, blue);

input reset, clk;
input ps2clk, ps2data;
output hsync, vsync;
output [2:0] red, green, blue;
wire [9:0] Hcount;
wire [8:0] Vcount;
wire clk25;
wire found;
wire [7:0]scancode;
clock_divider cl25(reset, clk, clk25);
HorizontalCnt hcnt(clk25, reset, Hcount, Venable);
VerticalCnt vcnt(clk25, reset, Venable, Vcount);
kbd_protocol kbdp (reset, clk25, ps2clk, ps2data, scancode, found);
vgasync vga(reset, clk25, Hcount, Vcount, hsync, vsync, red, green, blue, scancode, found);
endmodule