data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/PE.v
1: b"%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/PE.v:59: Cannot find file containing module: 'OUT_REG'\nOUT_REG #(.REG_DATA_WIDTH(DATA_OUT_WIDTH)) Out_Reg(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/OUT_REG.sv\n             OUT_REG\n             OUT_REG.v\n             OUT_REG.sv\n             obj_dir/OUT_REG\n             obj_dir/OUT_REG.v\n             obj_dir/OUT_REG.sv\n%Error: Exiting due to 1 error(s)\n"
module PE #( parameter PX_WIDTH=16, parameter W_WIDTH=16, parameter DATA_OUT_WIDTH=16)
(

PE_Clk,
PE_Out_Reg_Set,
PE_Reset,
PE_Fifo_Set,
PE_Is,
PE_If_Px,
PE_w,

PE_Out
);




input PE_Clk;
input PE_Out_Reg_Set;
input PE_Reset;
input PE_Fifo_Set;
input [DATA_OUT_WIDTH-1:0] PE_Is;
input signed [PX_WIDTH-1:0] PE_If_Px;
input signed [W_WIDTH-1:0] PE_w;
output signed [DATA_OUT_WIDTH-1:0] PE_Out;




reg signed [DATA_OUT_WIDTH-1:0] Sum_Reg;
wire signed [DATA_OUT_WIDTH-1:0] Sum_Reg_Output_Wire;
wire signed [DATA_OUT_WIDTH-1:0] Out_Reg_Output_Wire;





OUT_REG #(.REG_DATA_WIDTH(DATA_OUT_WIDTH)) Out_Reg(

.OUT_REG_Clk(PE_Clk),
.OUT_REG_Reset(PE_Reset),
.OUT_REG_Set(PE_Out_Reg_Set),
.OUT_REG_Input_Data(Sum_Reg_Output_Wire),
.OUT_REG_Output_Data(Out_Reg_Output_Wire)
);




always@(PE_If_Px,PE_w,PE_Is)
begin
	Sum_Reg= (PE_If_Px*PE_w) + PE_Is;
end




assign Sum_Reg_Output_Wire=Sum_Reg;
assign PE_Out= PE_Fifo_Set==1'b0 ? Out_Reg_Output_Wire : Sum_Reg_Output_Wire;


endmodule
module PE #( parameter PX_WIDTH=16, parameter W_WIDTH=16, parameter DATA_OUT_WIDTH=16)
(

PE_Clk,
PE_Out_Reg_Set,
PE_Reset,
PE_Fifo_Set,
PE_Is,
PE_If_Px,
PE_w,

PE_Out
);





input PE_Clk;
input PE_Out_Reg_Set;
input PE_Reset;
input PE_Fifo_Set;
input [DATA_OUT_WIDTH-1:0] PE_Is;
input signed [PX_WIDTH-1:0] PE_If_Px;
input signed [W_WIDTH-1:0] PE_w;
output signed [DATA_OUT_WIDTH-1:0] PE_Out;




reg signed [DATA_OUT_WIDTH-1:0] Sum_Reg;
wire signed [DATA_OUT_WIDTH-1:0] Sum_Reg_Output_Wire;
wire signed [DATA_OUT_WIDTH-1:0] Out_Reg_Output_Wire;





OUT_REG #(.REG_DATA_WIDTH(DATA_OUT_WIDTH)) Out_Reg(

.OUT_REG_Clk(PE_Clk),
.OUT_REG_Reset(PE_Reset),
.OUT_REG_Set(PE_Out_Reg_Set),
.OUT_REG_Input_Data(Sum_Reg_Output_Wire),
.OUT_REG_Output_Data(Out_Reg_Output_Wire)
);




always@(PE_If_Px,PE_w,PE_Is)
begin
	Sum_Reg= (PE_If_Px*PE_w) + PE_Is;
end




assign Sum_Reg_Output_Wire=Sum_Reg;
assign PE_Out= PE_Fifo_Set==1'b0 ? Out_Reg_Output_Wire : Sum_Reg_Output_Wire;


endmodule