data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:294: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'counter\'\nmodule counter(\n       ^~~~~~~\n                                                                                           : ... Top module \'buf1clear\'\nmodule buf1clear(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:468: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_addr\' generates 15 bits.\n                                                                                        : ... In instance counter.sA\n      toSave = s_addr;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:476: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      1: i_addr = 16\'d2;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:477: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      2: i_addr = 16\'d3;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:478: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      3: i_addr = 16\'d4;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:479: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      4: i_addr = 16\'d5;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:480: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      5: i_addr = 16\'d6;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:481: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      6: i_addr = 16\'d7;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:482: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      7: i_addr = 16\'d8;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:486: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n     if(exp) i_addr = 16\'d8;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:499: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n    JMP: if(dataAddr == 0) i_addr = num;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:518: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n        if(dataAddr == 0) i_addr = num;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:546: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh2\' generates 32 or 2 bits.\n                                                                                        : ... In instance counter.sA\n         n_int = 2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:531: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'toCont\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = toCont;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:536: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = num;\n                 ^\n%Error: Exiting due to 15 warning(s)\n'
module counter(
	input clk,
	input rst,
	
	input prst,
	
	input irq1,
	input irq2,
	input irq3,
	
	input hlt,
	
	input[7:0] offset,
	
	input[15:0] sreg1,
	input[15:0] sreg2,
	input[15:0] sreg3,
	input[15:0] sreg4,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	input[3:0] mOper,
	input[14:0] data,
	
	input s,
	input aeq,
	
	input lt,
	input gt,
	input eq,
	
	input exp,
	
	output[14:0] addr,
	
	output eirq,
	
	output inter,
	
	input cmpStart,
	
	input read,
	input save,
	
	output[15:0] stackaddr
);

wire[15:0] toSave;
wire push;
wire pop;

wire[15:0] toCont;

stackAddr sAddrA(.clk(clk),
					  .rst(rst),
	
					  .toSave(toSave),
					  .push(push),
	
					  .pop(pop),
					  .out(toCont)
	
);

wire rexp;
wire iexp;

wire[14:0] s_addr;
wire[14:0] i_addr;


wire[7:0] s_stackAddr;


wire[7:0] i_stackAddr;

wire[7:0] i_irq;
wire[7:0] s_irq;

wire oirq1;
wire oirq2;
wire oirq3;

wire rem;

wire ieirq;

wire[15:0] num;

numcountsel ncs(
	.clk(clk),
	.rst(rst),
	
	.reg1(reg1),
	.sreg1(sreg1),
	.sreg2(sreg2),
	.sreg3(sreg3),
	.sreg4(sreg4),
	
	.num1(num)
);

przebuffer pba1(.rst(rst),
					 .clk(clk),
					 
					 .feirq(ieirq),
					 .eirq(eirq),
	
					 .irq1(irq1),
					 .irq2(irq2),
					 .irq3(irq3),
					 
					 .rem(rem),
	
						.oirq1(oirq1),
						.oirq2(oirq2),
						.oirq3(oirq3)
);

addrBus aB(.clk(clk),
			  .rst(rst),
	
			  .iaddr(i_addr),
	
			  .addr(s_addr)
);


stackBus sB(.clk(clk),
				.rst(rst),
				
				.s_stackAddr(s_stackAddr),
		
				.i_stackAddr(i_stackAddr),
				
				.i_irq(i_irq),
				.s_irq(s_irq)
);

saveAddr sA(.s(s),
				.clk(clk),
				.offset(offset),
				.rst(rst),
				
				.prst(prst),
				
				.gt(gt),
				.lt(lt),
				.eq(eq),
			
				.num(num),
				
				.irq1(oirq1),
				.irq2(oirq2),
				.irq3(oirq3),
				
				.exp(0),
				
				.rem(rem),
				
				.hlt(hlt),
				.aeq(aeq),
				
				.inter(inter),
				
			
				.i_stackAddr(i_stackAddr),
				
				
				.s_stackAddr(s_stackAddr),
				
				.toSave(toSave),
				.push(push),
	
				.pop(pop),
				.toCont(toCont),
					  
				.mOper(mOper),
				.dataAddr(data),
	
				.s_addr(s_addr),
				.i_addr(i_addr),
				
				.eirq(ieirq),
				
				.i_irq(i_irq),
				.s_irq(s_irq),
				
				.cmpStart(cmpStart),
				
				.read(read),
				.save(save)
);

assign addr = s_addr;
assign stackaddr = toCont;
endmodule
module counter(
	input clk,
	input rst,
	
	input prst,
	
	input irq1,
	input irq2,
	input irq3,
	
	input hlt,
	
	input[7:0] offset,
	
	input[15:0] sreg1,
	input[15:0] sreg2,
	input[15:0] sreg3,
	input[15:0] sreg4,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	input[3:0] mOper,
	input[14:0] data,
	
	input s,
	input aeq,
	
	input lt,
	input gt,
	input eq,
	
	input exp,
	
	output[14:0] addr,
	
	output eirq,
	
	output inter,
	
	input cmpStart,
	
	input read,
	input save,
	
	output[15:0] stackaddr
);


wire[15:0] toSave;
wire push;
wire pop;

wire[15:0] toCont;

stackAddr sAddrA(.clk(clk),
					  .rst(rst),
	
					  .toSave(toSave),
					  .push(push),
	
					  .pop(pop),
					  .out(toCont)
	
);

wire rexp;
wire iexp;

wire[14:0] s_addr;
wire[14:0] i_addr;


wire[7:0] s_stackAddr;


wire[7:0] i_stackAddr;

wire[7:0] i_irq;
wire[7:0] s_irq;

wire oirq1;
wire oirq2;
wire oirq3;

wire rem;

wire ieirq;

wire[15:0] num;

numcountsel ncs(
	.clk(clk),
	.rst(rst),
	
	.reg1(reg1),
	.sreg1(sreg1),
	.sreg2(sreg2),
	.sreg3(sreg3),
	.sreg4(sreg4),
	
	.num1(num)
);

przebuffer pba1(.rst(rst),
					 .clk(clk),
					 
					 .feirq(ieirq),
					 .eirq(eirq),
	
					 .irq1(irq1),
					 .irq2(irq2),
					 .irq3(irq3),
					 
					 .rem(rem),
	
						.oirq1(oirq1),
						.oirq2(oirq2),
						.oirq3(oirq3)
);

addrBus aB(.clk(clk),
			  .rst(rst),
	
			  .iaddr(i_addr),
	
			  .addr(s_addr)
);


stackBus sB(.clk(clk),
				.rst(rst),
				
				.s_stackAddr(s_stackAddr),
		
				.i_stackAddr(i_stackAddr),
				
				.i_irq(i_irq),
				.s_irq(s_irq)
);

saveAddr sA(.s(s),
				.clk(clk),
				.offset(offset),
				.rst(rst),
				
				.prst(prst),
				
				.gt(gt),
				.lt(lt),
				.eq(eq),
			
				.num(num),
				
				.irq1(oirq1),
				.irq2(oirq2),
				.irq3(oirq3),
				
				.exp(0),
				
				.rem(rem),
				
				.hlt(hlt),
				.aeq(aeq),
				
				.inter(inter),
				
			
				.i_stackAddr(i_stackAddr),
				
				
				.s_stackAddr(s_stackAddr),
				
				.toSave(toSave),
				.push(push),
	
				.pop(pop),
				.toCont(toCont),
					  
				.mOper(mOper),
				.dataAddr(data),
	
				.s_addr(s_addr),
				.i_addr(i_addr),
				
				.eirq(ieirq),
				
				.i_irq(i_irq),
				.s_irq(s_irq),
				
				.cmpStart(cmpStart),
				
				.read(read),
				.save(save)
);

assign addr = s_addr;
assign stackaddr = toCont;
endmodule