data/full_repos/permissive/500326609/a3/dummydecoder.v
data/verilator_xmls/78936f37-ee82-484b-b509-e94577e23399.xml
module dummydecoder(
    input [31:0] instr,
    output [5:0] op,
    output [4:0] rs1,
    output [4:0] rs2,
    output [4:0] rd,
    input  [31:0] r_rv2,
    output [31:0] rv2,
    output we
);

    assign op = {1'b0,instr[5],instr[14:12],instr[30]};
    assign rs1 = instr[19:15];
    assign rs2 = instr[24:20];
    assign rd = instr[11:7];
    assign we = 1;

    assign rv2 = (instr[5]) ? r_rv2 : {{20{1'b0}},instr[31:20]};

endmodule
module dummydecoder(
    input [31:0] instr,
    output [5:0] op,
    output [4:0] rs1,
    output [4:0] rs2,
    output [4:0] rd,
    input  [31:0] r_rv2,
    output [31:0] rv2,
    output we
);


    assign op = {1'b0,instr[5],instr[14:12],instr[30]};
    assign rs1 = instr[19:15];
    assign rs2 = instr[24:20];
    assign rd = instr[11:7];
    assign we = 1;

    assign rv2 = (instr[5]) ? r_rv2 : {{20{1'b0}},instr[31:20]};

endmodule