data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module complemento2(a,s);
	input[5:0] a;
	output s;
	reg[5:0] s;
	wire[5:0] c1,soma;
	wire vaium;
	soma = 5'b0001;
	complemento1 COMPLEMENTO1(a,c1);
	fulladder5bits SOMA(a,b,s,vaium);
endmodule
module complemento2(a,s);

	input[5:0] a;
	output s;
	reg[5:0] s;
	wire[5:0] c1,soma;
	wire vaium;
	soma = 5'b0001;
	complemento1 COMPLEMENTO1(a,c1);
	fulladder5bits SOMA(a,b,s,vaium);
endmodule