data/full_repos/permissive/508331744/verilog/rtl/HA.v
data/verilator_xmls/8720dc23-0980-45c7-ba3e-453b221e8b16.xml
module HA(
    input x,y,
    output cout,sum
    );
    (* dont_touch="true" *)
    
    assign cout = x & y;
    assign sum = x ^ y;
       
endmodule
module HA(
    input x,y,
    output cout,sum
    );

    (* dont_touch="true" *)
    
    assign cout = x & y;
    assign sum = x ^ y;
       
endmodule