data/full_repos/permissive/470158975/rtl/misc/fwft_fifo.v
1: b"%Error: data/full_repos/permissive/470158975/rtl/misc/fwft_fifo.v:24: Cannot find file containing module: 'FIFO_SYNC_MACRO'\n   FIFO_SYNC_MACRO  #(\n   ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470158975/rtl/misc,data/full_repos/permissive/470158975/FIFO_SYNC_MACRO\n             data/full_repos/permissive/470158975/rtl/misc,data/full_repos/permissive/470158975/FIFO_SYNC_MACRO.v\n             data/full_repos/permissive/470158975/rtl/misc,data/full_repos/permissive/470158975/FIFO_SYNC_MACRO.sv\n             FIFO_SYNC_MACRO\n             FIFO_SYNC_MACRO.v\n             FIFO_SYNC_MACRO.sv\n             obj_dir/FIFO_SYNC_MACRO\n             obj_dir/FIFO_SYNC_MACRO.v\n             obj_dir/FIFO_SYNC_MACRO.sv\n%Error: Exiting due to 1 error(s)\n"
module fwft_fifo #(
   parameter DATA_WIDTH = 64

    ) (
    input wire RST,
    input wire CLK,
    output wire [DATA_WIDTH-1:0] DO,
    output wire EMPTY,
    output wire FULL,
    input wire [DATA_WIDTH-1:0] DI,
    input wire RDEN,
    input wire WREN
    );


   localparam FIFO_SIZE = (DATA_WIDTH > 36) ? "36Kb" : "18Kb";

   wire empty_int;
   wire rd_en_int;
   reg dout_valid =0;
    
   FIFO_SYNC_MACRO  #(
      .DEVICE("7SERIES"),
      .ALMOST_EMPTY_OFFSET(9'h080),
      .ALMOST_FULL_OFFSET(9'h080),
      .DATA_WIDTH(DATA_WIDTH),
      .DO_REG(0),
      .FIFO_SIZE (FIFO_SIZE)
   ) FIFO_SYNC_MACRO_inst (   
      .ALMOSTEMPTY(),
      .ALMOSTFULL(),
      .DO(DO),
      .EMPTY(empty_int),
      .FULL(FULL),
      .RDCOUNT(),
      .RDERR(),
      .WRCOUNT(),
      .WRERR(),
      .CLK(CLK),
      .DI(DI),
      .RDEN(rd_en_int),
      .RST(RST),
      .WREN(WREN)
   );

   assign rd_en_int = !empty_int && (!dout_valid || RDEN);
   assign EMPTY = !dout_valid;

   always @(posedge CLK) begin
      if (RST)
         dout_valid <= 0;
      else
         begin
            if (rd_en_int)
               dout_valid <= 1;
            else if (RDEN)
               dout_valid <= 0;
         end 
   end

endmodule
module fwft_fifo #(
   parameter DATA_WIDTH = 64

    ) (
    input wire RST,
    input wire CLK,
    output wire [DATA_WIDTH-1:0] DO,
    output wire EMPTY,
    output wire FULL,
    input wire [DATA_WIDTH-1:0] DI,
    input wire RDEN,
    input wire WREN
    );



   localparam FIFO_SIZE = (DATA_WIDTH > 36) ? "36Kb" : "18Kb";

   wire empty_int;
   wire rd_en_int;
   reg dout_valid =0;
    
   FIFO_SYNC_MACRO  #(
      .DEVICE("7SERIES"),
      .ALMOST_EMPTY_OFFSET(9'h080),
      .ALMOST_FULL_OFFSET(9'h080),
      .DATA_WIDTH(DATA_WIDTH),
      .DO_REG(0),
      .FIFO_SIZE (FIFO_SIZE)
   ) FIFO_SYNC_MACRO_inst (   
      .ALMOSTEMPTY(),
      .ALMOSTFULL(),
      .DO(DO),
      .EMPTY(empty_int),
      .FULL(FULL),
      .RDCOUNT(),
      .RDERR(),
      .WRCOUNT(),
      .WRERR(),
      .CLK(CLK),
      .DI(DI),
      .RDEN(rd_en_int),
      .RST(RST),
      .WREN(WREN)
   );

   assign rd_en_int = !empty_int && (!dout_valid || RDEN);
   assign EMPTY = !dout_valid;

   always @(posedge CLK) begin
      if (RST)
         dout_valid <= 0;
      else
         begin
            if (rd_en_int)
               dout_valid <= 1;
            else if (RDEN)
               dout_valid <= 0;
         end 
   end

endmodule