data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5 \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialHandler_tb.v:51: Cannot find file containing module: \'SerialHandler\'\nSerialHandler U0(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialHandler\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialHandler.v\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialHandler.sv\n             SerialHandler\n             SerialHandler.v\n             SerialHandler.sv\n             obj_dir/SerialHandler\n             obj_dir/SerialHandler.v\n             obj_dir/SerialHandler.sv\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SerialHandler_tb;

parameter POSITION_WIDTH = 11;

reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [POSITION_WIDTH-1:0] position_output;

reg [7:0] data_in [1:0];

SerialHandler U0(
    .clk100MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .ser_pos(position_output)
);

integer i = 0;
integer state = 0;
initial
begin
    ext_clk = 0;
    rst = 1;
    ext_flush = 0;
    serial = 0;

    data_in[0] = 8'b11111_111;
    data_in[1] = 8'b1111_1111;
    #5 
    ext_flush = 1;
    rst = 0;
    #5
    ext_flush = 0;
    state = 1;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[0][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    
    state = 2;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    state = 3;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    #5
    ext_flush = 1;
    #5
    ext_flush = 0;
    #50
    #10 $stop;   
    #5 $finish;
end

endmodule
module SerialHandler_tb;


parameter POSITION_WIDTH = 11;

reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [POSITION_WIDTH-1:0] position_output;

reg [7:0] data_in [1:0];

SerialHandler U0(
    .clk100MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .ser_pos(position_output)
);

integer i = 0;
integer state = 0;
initial
begin
    ext_clk = 0;
    rst = 1;
    ext_flush = 0;
    serial = 0;

    data_in[0] = 8'b11111_111;
    data_in[1] = 8'b1111_1111;
    #5 
    ext_flush = 1;
    rst = 0;
    #5
    ext_flush = 0;
    state = 1;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[0][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    
    state = 2;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    state = 3;
    for(i = 0; i < 7; i=i+1) begin
        #5
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
        #1
        clk = 0;
    end
    #5
    ext_flush = 1;
    #5
    ext_flush = 0;
    #50
    #10 $stop;   
    #5 $finish;
end

endmodule