data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/new/audio_sampling.v
data/verilator_xmls/16aba177-d714-4b9f-b66f-f0099a6b3270.xml
module min_max(clk, samples, max, min);

input clk;
output reg [15:0] samples;
output reg [15:0] min, max;

parameter SIZE = 1024;    
reg [15:0] rom_memory [SIZE-1:0];
integer i;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    max=rom_memory[0];
    min=rom_memory[0];
end
  


always@(posedge clk) begin
    samples = rom_memory[i];
    if(i == SIZE)
        i = 0;
    if (min>rom_memory[i])
        min=rom_memory[i];
    if (max<=rom_memory[i])
        max=rom_memory[i];
    i = i+ 1;
end
endmodule
module min_max(clk, samples, max, min);


input clk;
output reg [15:0] samples;
output reg [15:0] min, max;

parameter SIZE = 1024;    
reg [15:0] rom_memory [SIZE-1:0];
integer i;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    max=rom_memory[0];
    min=rom_memory[0];
end
  


always@(posedge clk) begin
    samples = rom_memory[i];
    if(i == SIZE)
        i = 0;
    if (min>rom_memory[i])
        min=rom_memory[i];
    if (max<=rom_memory[i])
        max=rom_memory[i];
    i = i+ 1;
end
endmodule