data/full_repos/permissive/454263844/Project_files/Shift_reg_a.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454263844/Project_files/Shift_reg_a.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                   : ... In instance Shift_Reg_a\n      A_o <= {A_in, A_o[7:1]} ;       \n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Shift_Reg_a( A_in , A_o , i_clk , ld_A , shift_A  );
parameter N = 8;
input i_clk ;
input [N-1:0] A_in ;
input ld_A ;
input shift_A ;
output reg [N-1:0] A_o ;

always @ (posedge i_clk )
begin
 if (ld_A)
  begin
   A_o <= A_in ;
   end
          else if (shift_A)
     begin
      A_o <= {A_in, A_o[7:1]} ;
       end
       else
         begin
       A_o <= 8'b0000_0000;
       end
       end
   
endmodule
module Shift_Reg_a( A_in , A_o , i_clk , ld_A , shift_A  );

parameter N = 8;
input i_clk ;
input [N-1:0] A_in ;
input ld_A ;
input shift_A ;
output reg [N-1:0] A_o ;

always @ (posedge i_clk )
begin
 if (ld_A)
  begin
   A_o <= A_in ;
   end
          else if (shift_A)
     begin
      A_o <= {A_in, A_o[7:1]} ;
       end
       else
         begin
       A_o <= 8'b0000_0000;
       end
       end
   
endmodule