data/full_repos/permissive/43856783/j1_soc/hdl/Position/counter_div.v
data/verilator_xmls/38f8875c-9dca-405b-a917-91a44b566e83.xml
module counter_div (clk , rst, DEC, z);

  input clk;
  input rst;
  input DEC;
  output reg z;

  reg [6:0] cont=64;


always @(negedge clk) begin


  if (rst) 
   cont = 7'b1000000;
  else
     begin
      if (DEC) cont=cont-1;
      else cont=cont;
     end

 z = (cont==0) ? 1 : 0 ;


end

endmodule
module counter_div (clk , rst, DEC, z);


  input clk;
  input rst;
  input DEC;
  output reg z;

  reg [6:0] cont=64;


always @(negedge clk) begin


  if (rst) 
   cont = 7'b1000000;
  else
     begin
      if (DEC) cont=cont-1;
      else cont=cont;
     end

 z = (cont==0) ? 1 : 0 ;


end

endmodule