data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/testbench_phy.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/testbench_phy.v:2: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/cmos_cells.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/cmos_cells.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/testbench_phy.v:3: Cannot find include file: phy_c.v\n`include "phy_c.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/testbench_phy.v:4: Cannot find include file: phy_e.v\n`include "phy_e.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/testbench_phy.v:5: Cannot find include file: probador_phy.v\n`include "probador_phy.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench_phy ();

    wire clk_32f;
    wire [31:0] Data_in;
    wire valid_in;
    wire [31:0] Data_out_c;
    wire valid_out_c;
    wire [31:0] Data_out_e;
    wire valid_out_e;
    


    probador_phy  probador_phy (
										.clk_32f(clk_32f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
                                        .valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c),
                                        .valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
	);

    phy_c phy_c1 (
                        .clk_32f(clk_32f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
                        .valid_out_c(valid_out_c),
	                    .Data_out_c(Data_out_c)
                        );

    phy_e phy_e1 (
                        .clk_32f(clk_32f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
                        .valid_out_e(valid_out_e),
						.Data_out_e(Data_out_e)
    
    );

endmodule
module testbench_phy ();


    wire clk_32f;
    wire [31:0] Data_in;
    wire valid_in;
    wire [31:0] Data_out_c;
    wire valid_out_c;
    wire [31:0] Data_out_e;
    wire valid_out_e;
    


    probador_phy  probador_phy (
										.clk_32f(clk_32f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
                                        .valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c),
                                        .valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
	);

    phy_c phy_c1 (
                        .clk_32f(clk_32f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
                        .valid_out_c(valid_out_c),
	                    .Data_out_c(Data_out_c)
                        );

    phy_e phy_e1 (
                        .clk_32f(clk_32f),
	                    .reset(reset),
	                    .valid_in(valid_in),
	                    .Data_in(Data_in),
                        .valid_out_e(valid_out_e),
						.Data_out_e(Data_out_e)
    
    );

endmodule