data/full_repos/permissive/417261953/src/pwm_gen.v
data/verilator_xmls/469a3a17-9afe-4518-8c67-4639c38e5c45.xml
module pwm_gen (
	input    	clk, 
	input [2:0]	duty_cycle, 
	output reg	pwm
);

reg [2:0]	count;

initial 
begin
	count=3'b000;
	pwm=1'b0;
end

always @(posedge clk)
begin
	count = count + 1'b1;
	if (count < duty_cycle) 
		begin 
			pwm = 1'b1;
		end
	else if (count >= duty_cycle)
		begin
			pwm = 1'b0;
		end
end

endmodule
module pwm_gen (
	input    	clk, 
	input [2:0]	duty_cycle, 
	output reg	pwm
);


reg [2:0]	count;

initial 
begin
	count=3'b000;
	pwm=1'b0;
end

always @(posedge clk)
begin
	count = count + 1'b1;
	if (count < duty_cycle) 
		begin 
			pwm = 1'b1;
		end
	else if (count >= duty_cycle)
		begin
			pwm = 1'b0;
		end
end

endmodule