data/full_repos/permissive/470158975/rtl/payload_crc_acc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:32: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n            sum_a <= udp_data[15:0] + udp_data[31:16] + sum_a;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:32: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n            sum_a <= udp_data[15:0] + udp_data[31:16] + sum_a;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:33: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n            sum_b <= udp_data[47:32] + udp_data[63:48] + sum_b;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:33: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n            sum_b <= udp_data[47:32] + udp_data[63:48] + sum_b;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:36: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                             : ... In instance payload_crc_acc\n            udp_crc <= (result[15:0] + result[17:16]);\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:47: Operator ADD expects 18 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:47: Operator ADD expects 18 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                             : ... In instance payload_crc_acc\n   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:47: Operator ADD expects 18 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                             : ... In instance payload_crc_acc\n   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/payload_crc_acc.v:47: Operator ADD expects 18 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                             : ... In instance payload_crc_acc\n   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];\n                                                                  ^\n%Error: Exiting due to 9 warning(s)\n'
module payload_crc_acc(

   input    wire        clk,
   input    wire        rst,
   input    wire [63:0] udp_data,
   input    wire        udp_data_valid,
   input    wire        last_data,
   output   reg[15:0]   udp_crc,
   output   reg         udp_crc_valid

);

   reg  [31:0] sum_a;
   reg  [31:0] sum_b;
   wire [16:0] result_a;
   wire [16:0] result_b;
   wire [17:0] result;
   reg         last_reg;
   reg         last_detect;

   always @(posedge clk) begin
      if (rst) begin
         sum_a    <= 0;
         sum_b    <= 0;
         udp_crc <= 0;
         udp_crc_valid <= 0;
      end
      else begin
         if (udp_data_valid) begin
            sum_a <= udp_data[15:0] + udp_data[31:16] + sum_a;
            sum_b <= udp_data[47:32] + udp_data[63:48] + sum_b;
         end
         if (last_detect) begin
            udp_crc <= (result[15:0] + result[17:16]);
            udp_crc_valid <= 1;
            sum_a <=0;
            sum_b <=0;
         end
         else udp_crc_valid <= 0;
      end
   end
   
   assign result_a = (sum_a[15:0] + sum_a[31:16]);
   assign result_b = (sum_b[15:0] + sum_b[31:16]);
   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];
   
   always @(posedge clk) begin 
       if (rst) begin
           last_reg <= 0;
           last_detect <= 0;
       end else begin
         last_reg <= last_data;
         last_detect <= last_data & !last_reg;
      end
   end
   
   
endmodule
module payload_crc_acc(

   input    wire        clk,
   input    wire        rst,
   input    wire [63:0] udp_data,
   input    wire        udp_data_valid,
   input    wire        last_data,
   output   reg[15:0]   udp_crc,
   output   reg         udp_crc_valid

);


   reg  [31:0] sum_a;
   reg  [31:0] sum_b;
   wire [16:0] result_a;
   wire [16:0] result_b;
   wire [17:0] result;
   reg         last_reg;
   reg         last_detect;

   always @(posedge clk) begin
      if (rst) begin
         sum_a    <= 0;
         sum_b    <= 0;
         udp_crc <= 0;
         udp_crc_valid <= 0;
      end
      else begin
         if (udp_data_valid) begin
            sum_a <= udp_data[15:0] + udp_data[31:16] + sum_a;
            sum_b <= udp_data[47:32] + udp_data[63:48] + sum_b;
         end
         if (last_detect) begin
            udp_crc <= (result[15:0] + result[17:16]);
            udp_crc_valid <= 1;
            sum_a <=0;
            sum_b <=0;
         end
         else udp_crc_valid <= 0;
      end
   end
   
   assign result_a = (sum_a[15:0] + sum_a[31:16]);
   assign result_b = (sum_b[15:0] + sum_b[31:16]);
   assign result = result_a[15:0] + result_b[15:0] + result_a[16] + result_b[16];
   
   always @(posedge clk) begin 
       if (rst) begin
           last_reg <= 0;
           last_detect <= 0;
       end else begin
         last_reg <= last_data;
         last_detect <= last_data & !last_reg;
      end
   end
   
   
endmodule