data/full_repos/permissive/435516446/MIPS/Adder.v
data/verilator_xmls/4adfe6ca-de91-4038-8095-cb21d663c84e.xml
module Adder(
	 input clock,
    input [31:0] input1,
    input [31:0] input2,
    output reg [31:0] result
    );
always @ (negedge clock)
 result = input1 + input2;

endmodule
module Adder(
	 input clock,
    input [31:0] input1,
    input [31:0] input2,
    output reg [31:0] result
    );

always @ (negedge clock)
 result = input1 + input2;

endmodule