data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n always #1 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:41: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:55: Unsupported: wait statements\n  wait(mprj_io[37:32] == 6\'h18);\n  ^~~~\n%Error: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:58: Unsupported: wait statements\n  wait(mprj_io[37:32] == 6\'h19 || mprj_io[37:32] == 6\'h1a);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484005552/cpu/tests/0_addi/test_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: Exiting due to 5 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_tb;
	reg clock;
	reg RSTB;
	reg CSB;

	reg power1, power2;

	wire gpio;
	wire [37:0] mprj_io;

	always #1 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, test_tb);

		repeat (1000) begin
			repeat (1000) @(posedge clock);
		end

		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		wait(mprj_io[37:32] == 6'h18);
		$display("Monitor: Test Started");

		wait(mprj_io[37:32] == 6'h19 || mprj_io[37:32] == 6'h1a);
		$display("Monitor: Test Done");
		
		if(mprj_io[37:32] == 6'h19) begin
			$display("Monitor: completed and all assertions passed - pc == 0x%0h", mprj_io[31:0]);
		end
		else begin
			$display("Monitor: assertion failed - pc == 0x%0h", mprj_io[31:0]);
		end
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		#1000;
		RSTB <= 1'b1;
		#2000;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
	wire VDD3V3;
	wire VSS;
    
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	assign mprj_io[3] = 1;
	assign mprj_io[0] = 0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module test_tb;

	reg clock;
	reg RSTB;
	reg CSB;

	reg power1, power2;

	wire gpio;
	wire [37:0] mprj_io;

	always #1 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, test_tb);

		repeat (1000) begin
			repeat (1000) @(posedge clock);
		end

		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		wait(mprj_io[37:32] == 6'h18);
		$display("Monitor: Test Started");

		wait(mprj_io[37:32] == 6'h19 || mprj_io[37:32] == 6'h1a);
		$display("Monitor: Test Done");
		
		if(mprj_io[37:32] == 6'h19) begin
			$display("Monitor: completed and all assertions passed - pc == 0x%0h", mprj_io[31:0]);
		end
		else begin
			$display("Monitor: assertion failed - pc == 0x%0h", mprj_io[31:0]);
		end
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		#1000;
		RSTB <= 1'b1;
		#2000;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
	wire VDD3V3;
	wire VSS;
    
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	assign mprj_io[3] = 1;
	assign mprj_io[0] = 0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule