data/full_repos/permissive/472385934/hazard_handle.v
data/verilator_xmls/d0294ac7-00d0-4a08-9de2-80249e79c559.xml
module hazard_handle(
input [4:0] rsE,rtE,
input [4:0] rtD,
input [4:0] rsD,
input [4:0] writeregM,writeregW,
input regwriteM,regwriteW,
input memtoregE,
input [4:0] writeregE,
input pcsrcD,memtoregM,regwriteE,
input jump,
output [1:0]forwardAE,forwardBE,
output forwardAD,forwardBD,
output flushD,
output stallF,stallD,flushE);

reg lwstall;
wire bstall;
wire bstall_temp1,bstall_temp2;

forward_unit forward_RAW(writeregM,writeregW,rsE,rtE,regwriteM,regwriteW,forwardAE,forwardBE);

always@(*) begin
    if(((rtD==rsE)||(rtD==rtE))&memtoregE&(rtD!=0))
        lwstall = 1;
    else lwstall = 0;
end


assign flushD = pcsrcD | jump;
wire [1:0]forwardAD_temp,forwardBD_temp;
forward_unit forward_control(writeregM,0,rsE,rtE,regwriteM,0,forwardAD_temp,forwardBD_temp);
assign forwardAD = forwardAD_temp[0];
assign forwardBD = forwardBD_temp[0];
assign bstall_temp1 = pcsrcD&&(regwriteE&&((writeregE==rsD)||(writeregE==rtD)));
assign bstall_temp2 = pcsrcD&&(memtoregM&&((writeregM==rsD)||(writeregM==rtD)));
assign bstall = bstall_temp1 | bstall_temp2;
assign stallD = lwstall | bstall;
assign stallF = lwstall | bstall;
assign flushE = lwstall | bstall;
endmodule
module hazard_handle(
input [4:0] rsE,rtE,
input [4:0] rtD,
input [4:0] rsD,
input [4:0] writeregM,writeregW,
input regwriteM,regwriteW,
input memtoregE,
input [4:0] writeregE,
input pcsrcD,memtoregM,regwriteE,
input jump,
output [1:0]forwardAE,forwardBE,
output forwardAD,forwardBD,
output flushD,
output stallF,stallD,flushE);


reg lwstall;
wire bstall;
wire bstall_temp1,bstall_temp2;

forward_unit forward_RAW(writeregM,writeregW,rsE,rtE,regwriteM,regwriteW,forwardAE,forwardBE);

always@(*) begin
    if(((rtD==rsE)||(rtD==rtE))&memtoregE&(rtD!=0))
        lwstall = 1;
    else lwstall = 0;
end


assign flushD = pcsrcD | jump;
wire [1:0]forwardAD_temp,forwardBD_temp;
forward_unit forward_control(writeregM,0,rsE,rtE,regwriteM,0,forwardAD_temp,forwardBD_temp);
assign forwardAD = forwardAD_temp[0];
assign forwardBD = forwardBD_temp[0];
assign bstall_temp1 = pcsrcD&&(regwriteE&&((writeregE==rsD)||(writeregE==rtD)));
assign bstall_temp2 = pcsrcD&&(memtoregM&&((writeregM==rsD)||(writeregM==rtD)));
assign bstall = bstall_temp1 | bstall_temp2;
assign stallD = lwstall | bstall;
assign stallF = lwstall | bstall;
assign flushE = lwstall | bstall;
endmodule