data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:56: Signal definition not found, creating implicitly: \'InteEn\'\nassign InteEn = C0State[0];\n       ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:57: Signal definition not found, creating implicitly: \'INTE\'\nassign INTE = C0State[1];\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:62: Signal definition not found, creating implicitly: \'R\'\n                                                                                        : ... Suggested alternative: \'RS\'\nassign R           =(opcode==6\'h00);\n       ^\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:63: Signal definition not found, creating implicitly: \'SLL_SRL_SRA\'\nassign SLL_SRL_SRA =(opcode==6\'h00 && func[5:2]==4\'h0);\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:64: Signal definition not found, creating implicitly: \'JR\'\n                                                                                        : ... Suggested alternative: \'R\'\nassign JR          =(opcode==6\'h00 && func==6\'h8);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:65: Signal definition not found, creating implicitly: \'JALR\'\n                                                                                        : ... Suggested alternative: \'JR\'\nassign JALR        =(opcode==6\'h00 && func==6\'h9);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:66: Signal definition not found, creating implicitly: \'SYSCALL\'\nassign SYSCALL     = (opcode==6\'h00 && func==6\'hC);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:67: Signal definition not found, creating implicitly: \'J\'\n                                                                                        : ... Suggested alternative: \'JR\'\nassign J           =(opcode==6\'h02);\n       ^\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:68: Signal definition not found, creating implicitly: \'JAL\'\n                                                                                        : ... Suggested alternative: \'JALR\'\nassign JAL         =(opcode==6\'h03);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:69: Signal definition not found, creating implicitly: \'BEQ\'\nassign BEQ         =(opcode==6\'h04);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:70: Signal definition not found, creating implicitly: \'BNE\'\nassign BNE         =(opcode==6\'h05);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:72: Signal definition not found, creating implicitly: \'ADDI\'\nassign ADDI        =(opcode==6\'h08);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:73: Signal definition not found, creating implicitly: \'ADDIU\'\n                                                                                        : ... Suggested alternative: \'ADDI\'\nassign ADDIU       =(opcode==6\'h09);\n       ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:74: Signal definition not found, creating implicitly: \'SLTI\'\nassign SLTI        =(opcode==6\'h0A);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:75: Signal definition not found, creating implicitly: \'SLTIU\'\n                                                                                        : ... Suggested alternative: \'SLTI\'\nassign SLTIU       =(opcode==6\'h0B);\n       ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:77: Signal definition not found, creating implicitly: \'ANDI\'\n                                                                                        : ... Suggested alternative: \'ADDI\'\nassign ANDI        =(opcode==6\'h0C);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:78: Signal definition not found, creating implicitly: \'ORI\'\nassign ORI         =(opcode==6\'h0D);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:79: Signal definition not found, creating implicitly: \'XORI\'\n                                                                                        : ... Suggested alternative: \'ORI\'\nassign XORI        =(opcode==6\'h0E);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:81: Signal definition not found, creating implicitly: \'LUI\'\nassign LUI         =(opcode==6\'h0F);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:82: Signal definition not found, creating implicitly: \'MFC0\'\nassign MFC0        =(opcode==6\'h10 && RS==5\'h0);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:83: Signal definition not found, creating implicitly: \'MTC0\'\n                                                                                        : ... Suggested alternative: \'MFC0\'\nassign MTC0        =(opcode==6\'h10 && RS==5\'h4);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:84: Signal definition not found, creating implicitly: \'ERET\'\nassign ERET        =(opcode==6\'h10 && RS==5\'h10 && func==6\'h18);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:85: Signal definition not found, creating implicitly: \'MUL\'\nassign MUL         =(opcode==6\'h1c);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:86: Signal definition not found, creating implicitly: \'LH\'\nassign LH          =(opcode==6\'h21);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:87: Signal definition not found, creating implicitly: \'LW\'\n                                                                                        : ... Suggested alternative: \'LH\'\nassign LW          =(opcode==6\'h23);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:88: Signal definition not found, creating implicitly: \'SH\'\n                                                                                        : ... Suggested alternative: \'LH\'\nassign SH          =(opcode==6\'h29);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:89: Signal definition not found, creating implicitly: \'SW\'\n                                                                                        : ... Suggested alternative: \'LW\'\nassign SW          =(opcode==6\'h2B);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:291: Signal definition not found, creating implicitly: \'state0\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state0 = (state == 0);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:292: Signal definition not found, creating implicitly: \'state1\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state1 = (state == 1);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:293: Signal definition not found, creating implicitly: \'state2\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state2 = (state == 2);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:294: Signal definition not found, creating implicitly: \'state3\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state3 = (state == 3);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:295: Signal definition not found, creating implicitly: \'state4\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state4 = (state == 4);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:296: Signal definition not found, creating implicitly: \'state5\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state5 = (state == 5);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:297: Signal definition not found, creating implicitly: \'state6\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state6 = (state == 6);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:298: Signal definition not found, creating implicitly: \'state7\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state7 = (state == 7);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:299: Signal definition not found, creating implicitly: \'state8\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state8 = (state == 8);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:300: Signal definition not found, creating implicitly: \'state9\'\n                                                                                         : ... Suggested alternative: \'state\'\nassign state9 = (state == 9);\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:301: Signal definition not found, creating implicitly: \'state10\'\n                                                                                         : ... Suggested alternative: \'state0\'\nassign state10 = (state == 10);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:302: Signal definition not found, creating implicitly: \'state11\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state11 = (state == 11);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:303: Signal definition not found, creating implicitly: \'state13\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state13 = (state == 13);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:304: Signal definition not found, creating implicitly: \'state14\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state14 = (state == 14);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:305: Signal definition not found, creating implicitly: \'state15\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state15 = (state == 15);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:306: Signal definition not found, creating implicitly: \'state16\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state16 = (state == 16);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:307: Signal definition not found, creating implicitly: \'state17\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state17 = (state == 17);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:308: Signal definition not found, creating implicitly: \'state18\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state18 = (state == 18);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:309: Signal definition not found, creating implicitly: \'state19\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state19 = (state == 19);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:310: Signal definition not found, creating implicitly: \'state20\'\n                                                                                         : ... Suggested alternative: \'state0\'\nassign state20 = (state == 20);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:311: Signal definition not found, creating implicitly: \'state21\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state21 = (state == 21);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:312: Signal definition not found, creating implicitly: \'state22\'\n                                                                                         : ... Suggested alternative: \'state2\'\nassign state22 = (state == 22);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:313: Signal definition not found, creating implicitly: \'state23\'\n                                                                                         : ... Suggested alternative: \'state13\'\nassign state23 = (state == 23);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:314: Signal definition not found, creating implicitly: \'state24\'\n                                                                                         : ... Suggested alternative: \'state14\'\nassign state24 = (state == 24);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:315: Signal definition not found, creating implicitly: \'state25\'\n                                                                                         : ... Suggested alternative: \'state15\'\nassign state25 = (state == 25);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:316: Signal definition not found, creating implicitly: \'state26\'\n                                                                                         : ... Suggested alternative: \'state16\'\nassign state26 = (state == 26);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:317: Signal definition not found, creating implicitly: \'state27\'\n                                                                                         : ... Suggested alternative: \'state17\'\nassign state27 = (state == 27);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:318: Signal definition not found, creating implicitly: \'state28\'\n                                                                                         : ... Suggested alternative: \'state18\'\nassign state28 = (state == 28);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:319: Signal definition not found, creating implicitly: \'state29\'\n                                                                                         : ... Suggested alternative: \'state19\'\nassign state29 = (state == 29);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:320: Signal definition not found, creating implicitly: \'state30\'\n                                                                                         : ... Suggested alternative: \'state0\'\nassign state30 = (state == 30);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:321: Signal definition not found, creating implicitly: \'state31\'\n                                                                                         : ... Suggested alternative: \'state1\'\nassign state31 = (state == 31);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:322: Signal definition not found, creating implicitly: \'state32\'\n                                                                                         : ... Suggested alternative: \'state2\'\nassign state32 = (state == 32);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:323: Signal definition not found, creating implicitly: \'state33\'\n                                                                                         : ... Suggested alternative: \'state13\'\nassign state33 = (state == 33);\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ControlUnit.v:324: Signal definition not found, creating implicitly: \'state34\'\n                                                                                         : ... Suggested alternative: \'state14\'\nassign state34 = (state == 34);\n       ^~~~~~~\n%Error: Exiting due to 61 warning(s)\n'
module ControlUnit(
input clk,
input[5:0] opcode,
input[5:0] func,
input[4:0] RS,
input  MemOK,
input[31:0] C0State,

output MemRead,
output PCWrite,
output PCWriteCond,
output IorD,
output MemWrite,
output[2:0] WriteData,
output IRWrite,
output[1:0] ALUSrcA,
output RegWrite,
output[1:0] RegDst,
output SaveHalf,
output LoadHalf,
output[1:0] ALUop, 
output[2:0] ALUSrcB, 
output[2:0] PCSource,
output[5:0] CUState,
output[5:0] ALUFunc,
output C0Write,
output[1:0] C0Dst,
output[2:0] C0Src,
output CauseSource,
output SyscallInte,
output IsBne
    );
	 
reg [5:0] state;
assign CUState = state;
assign InteEn = C0State[0];
assign INTE = C0State[1];
initial begin
	state <= 0;
end

assign R           =(opcode==6'h00);
assign SLL_SRL_SRA =(opcode==6'h00 && func[5:2]==4'h0);
assign JR          =(opcode==6'h00 && func==6'h8);
assign JALR        =(opcode==6'h00 && func==6'h9);
assign SYSCALL     = (opcode==6'h00 && func==6'hC);
assign J           =(opcode==6'h02);
assign JAL         =(opcode==6'h03);
assign BEQ         =(opcode==6'h04);
assign BNE         =(opcode==6'h05);

assign ADDI        =(opcode==6'h08);
assign ADDIU       =(opcode==6'h09);
assign SLTI        =(opcode==6'h0A);
assign SLTIU       =(opcode==6'h0B);

assign ANDI        =(opcode==6'h0C);
assign ORI 	       =(opcode==6'h0D);
assign XORI        =(opcode==6'h0E);

assign LUI         =(opcode==6'h0F);
assign MFC0        =(opcode==6'h10 && RS==5'h0);
assign MTC0        =(opcode==6'h10 && RS==5'h4);
assign ERET        =(opcode==6'h10 && RS==5'h10 && func==6'h18);
assign MUL         =(opcode==6'h1c);
assign LH          =(opcode==6'h21);
assign LW          =(opcode==6'h23);
assign SH          =(opcode==6'h29);
assign SW          =(opcode==6'h2B);


always @(posedge clk) begin
	case(state)
		0: begin 
			if(INTE && InteEn) begin
				state <= 25;
			end
			else begin
				state <= 23;
			end
		end
		1: begin 
			if(LW | SW | LH | SH) begin
				state <= 2;
			end
			
			else if (R)begin
				if(JR) begin
					state <= 14;
				end
				else if(JALR) begin
					state <= 15;
				end
				else if(SLL_SRL_SRA) begin
					state <= 19;
				end
				else if(SYSCALL) begin
					state <= 29;
				end
				else begin
					state <= 6;
				end
			end
			
			else if (BEQ) begin
				state <= 8;
			end
			
			else if (J) begin
				state <= 9;
			end 
			
			else if(JAL) begin
				state <= 13;
			end
			
			else if(MFC0) begin
				state <= 16;
			end
			
			else if(MTC0) begin
				state <= 17;
			end
			
			else if(LUI) begin
				state <= 18;
			end 
			
			else if(ADDI | SLTI) begin
				state <= 20;
			end
			
			else if(ANDI | ORI |XORI | ADDIU | SLTIU) begin
				state <= 21;
			end
			
			else if(MUL) begin
				state <= 22;
			end
			
			else if(ERET) begin
				state <= 32;
			end
			
			else if(BNE) begin
				state <= 34;
			end
		end
		2: begin 
			if (LW)begin
				state <= 3;
			end
			else if (SW)begin
				state <= 5;
			end
			else if (SH)begin
				state <= 11;
			end
			else if (LH)begin
				state <= 10;
			end
		end
		3: begin
			state <= 4;
		end
		4: begin 
			if(MemOK) begin
				state <= 0;
			end
		end
		5: begin 
			state <= 33;
		end
		6: begin 
			state <= 7;
		end
		7: begin 
			state <= 0;
		end
		8: begin 
			state <= 0;
		end
		9: begin 
			state <= 0;
		end
		10: begin 
			state <= 4;
		end
		11: begin 
			state <= 33;
		end
		12: begin 
			state <= 0;
		end
		13: begin
			state <=0;
		end
		14: begin
			state <= 0;
		end
		15: begin
			state <= 0;
		end
		16: begin
			state <= 0;
		end
		17: begin
			state <= 0;
		end
		18: begin
			state <= 0;
		end
		19: begin
			state <= 7;
		end
		20: begin
			state <= 24;
		end
		21: begin
			state <= 24;
		end
		22: begin
			state <= 7;
		end
		23: begin
			if(MemOK) begin
				state <= 1;
			end
		end
		24: begin
			state <= 0;
		end
		25: begin
			state <= 26;
		end
		26: begin
			state <= 27;
		end
		27: begin
			state <= 0;
		end
		28: begin
			state <= 31;
		end
		29: begin
			state <= 30;
		end
		30: begin
			state <= 0;
		end
		31: begin
			state <= 0;
		end
		32: begin
			state <= 28;
		end
		33: begin
			if(MemOK) begin
				state <= 0;
			end
		end
		34: begin
			state <= 0;
		end
		default: begin
			state <= 0;
		end
	endcase
end

assign state0 = (state == 0);
assign state1 = (state == 1);
assign state2 = (state == 2);
assign state3 = (state == 3);
assign state4 = (state == 4);
assign state5 = (state == 5);
assign state6 = (state == 6);
assign state7 = (state == 7);
assign state8 = (state == 8);
assign state9 = (state == 9);
assign state10 = (state == 10);
assign state11 = (state == 11);
assign state13 = (state == 13);
assign state14 = (state == 14);
assign state15 = (state == 15);
assign state16 = (state == 16);
assign state17 = (state == 17);
assign state18 = (state == 18);
assign state19 = (state == 19);
assign state20 = (state == 20);
assign state21 = (state == 21);
assign state22 = (state == 22);
assign state23 = (state == 23);
assign state24 = (state == 24);
assign state25 = (state == 25);
assign state26 = (state == 26);
assign state27 = (state == 27);
assign state28 = (state == 28);
assign state29 = (state == 29);
assign state30 = (state == 30);
assign state31 = (state == 31);
assign state32 = (state == 32);
assign state33 = (state == 33);
assign state34 = (state == 34);

assign PCWrite = state9 | state13 | state14 | state15 | (state23 & MemOK)|state27 | state28;
assign PCWriteCond = state8 | state34;
assign IorD = state3 | state5 | state10 | state11;
assign MemRead = state0 | state3 | state10;
assign MemWrite = state5 | state11;
assign WriteData[2] = state18;
assign WriteData[1] = state13 | state15 | state16;
assign WriteData[0] = state4 | state16;
assign IRWrite = state23 & MemOK;
assign ALUop[1] = state6 | state19 | state20 | state21 | state22;
assign ALUop[0] = state8 | state34;
assign ALUSrcA[1] = state19;
assign ALUSrcA[0] = state2 | state6 | state8 | state20 | state21 | state22 | state34;
assign ALUSrcB[2] = state21;
assign ALUSrcB[1] = state1 | state2 | state20;
assign ALUSrcB[0] = state1 | state23;
assign RegWrite = (state4 & MemOK) | state7 | state13 | state15 | state16 | state18 | state24;
assign RegDst[1] = state13;
assign RegDst[0] = state7 | state15;
assign SaveHalf = state11;
assign LoadHalf = state10;
assign PCSource[2] = state27 | state28;
assign PCSource[1] = state9 | state13 | state14 | state15;
assign PCSource[0] = state8 | state14 | state15 | state27 | state34;
assign IsBne = state34;
assign ALUFunc = 
	{6{R}} & func |
	{6{ADDI}}  & 6'h20 |
	{6{ADDIU}} & 6'h21 |
	{6{SLTI}}  & 6'h2A |
	{6{SLTIU}} & 6'h2B |
	{6{ANDI}}  & 6'h24 |
	{6{ORI}}   & 6'h25 |
	{6{XORI}}  & 6'h26 |
	{6{MUL}}   & 6'h3f;
assign C0Write = state17 | state25 | state26 | state29 | state31;
assign C0Dst[1]= state0 | state25 | state29 | state28 | state31;
assign C0Dst[0]= state26 | state29 | state32;
assign C0Src[2]= state31;
assign C0Src[1]= state25 | state29;
assign C0Src[0]= state26 | state29;
assign CauseSource = state30;
assign SyscallInte = state30;
endmodule
module ControlUnit(
input clk,
input[5:0] opcode,
input[5:0] func,
input[4:0] RS,
input  MemOK,
input[31:0] C0State,

output MemRead,
output PCWrite,
output PCWriteCond,
output IorD,
output MemWrite,
output[2:0] WriteData,
output IRWrite,
output[1:0] ALUSrcA,
output RegWrite,
output[1:0] RegDst,
output SaveHalf,
output LoadHalf,
output[1:0] ALUop, 
output[2:0] ALUSrcB, 
output[2:0] PCSource,
output[5:0] CUState,
output[5:0] ALUFunc,
output C0Write,
output[1:0] C0Dst,
output[2:0] C0Src,
output CauseSource,
output SyscallInte,
output IsBne
    );

	 
reg [5:0] state;
assign CUState = state;
assign InteEn = C0State[0];
assign INTE = C0State[1];
initial begin
	state <= 0;
end

assign R           =(opcode==6'h00);
assign SLL_SRL_SRA =(opcode==6'h00 && func[5:2]==4'h0);
assign JR          =(opcode==6'h00 && func==6'h8);
assign JALR        =(opcode==6'h00 && func==6'h9);
assign SYSCALL     = (opcode==6'h00 && func==6'hC);
assign J           =(opcode==6'h02);
assign JAL         =(opcode==6'h03);
assign BEQ         =(opcode==6'h04);
assign BNE         =(opcode==6'h05);

assign ADDI        =(opcode==6'h08);
assign ADDIU       =(opcode==6'h09);
assign SLTI        =(opcode==6'h0A);
assign SLTIU       =(opcode==6'h0B);

assign ANDI        =(opcode==6'h0C);
assign ORI 	       =(opcode==6'h0D);
assign XORI        =(opcode==6'h0E);

assign LUI         =(opcode==6'h0F);
assign MFC0        =(opcode==6'h10 && RS==5'h0);
assign MTC0        =(opcode==6'h10 && RS==5'h4);
assign ERET        =(opcode==6'h10 && RS==5'h10 && func==6'h18);
assign MUL         =(opcode==6'h1c);
assign LH          =(opcode==6'h21);
assign LW          =(opcode==6'h23);
assign SH          =(opcode==6'h29);
assign SW          =(opcode==6'h2B);


always @(posedge clk) begin
	case(state)
		0: begin 
			if(INTE && InteEn) begin
				state <= 25;
			end
			else begin
				state <= 23;
			end
		end
		1: begin 
			if(LW | SW | LH | SH) begin
				state <= 2;
			end
			
			else if (R)begin
				if(JR) begin
					state <= 14;
				end
				else if(JALR) begin
					state <= 15;
				end
				else if(SLL_SRL_SRA) begin
					state <= 19;
				end
				else if(SYSCALL) begin
					state <= 29;
				end
				else begin
					state <= 6;
				end
			end
			
			else if (BEQ) begin
				state <= 8;
			end
			
			else if (J) begin
				state <= 9;
			end 
			
			else if(JAL) begin
				state <= 13;
			end
			
			else if(MFC0) begin
				state <= 16;
			end
			
			else if(MTC0) begin
				state <= 17;
			end
			
			else if(LUI) begin
				state <= 18;
			end 
			
			else if(ADDI | SLTI) begin
				state <= 20;
			end
			
			else if(ANDI | ORI |XORI | ADDIU | SLTIU) begin
				state <= 21;
			end
			
			else if(MUL) begin
				state <= 22;
			end
			
			else if(ERET) begin
				state <= 32;
			end
			
			else if(BNE) begin
				state <= 34;
			end
		end
		2: begin 
			if (LW)begin
				state <= 3;
			end
			else if (SW)begin
				state <= 5;
			end
			else if (SH)begin
				state <= 11;
			end
			else if (LH)begin
				state <= 10;
			end
		end
		3: begin
			state <= 4;
		end
		4: begin 
			if(MemOK) begin
				state <= 0;
			end
		end
		5: begin 
			state <= 33;
		end
		6: begin 
			state <= 7;
		end
		7: begin 
			state <= 0;
		end
		8: begin 
			state <= 0;
		end
		9: begin 
			state <= 0;
		end
		10: begin 
			state <= 4;
		end
		11: begin 
			state <= 33;
		end
		12: begin 
			state <= 0;
		end
		13: begin
			state <=0;
		end
		14: begin
			state <= 0;
		end
		15: begin
			state <= 0;
		end
		16: begin
			state <= 0;
		end
		17: begin
			state <= 0;
		end
		18: begin
			state <= 0;
		end
		19: begin
			state <= 7;
		end
		20: begin
			state <= 24;
		end
		21: begin
			state <= 24;
		end
		22: begin
			state <= 7;
		end
		23: begin
			if(MemOK) begin
				state <= 1;
			end
		end
		24: begin
			state <= 0;
		end
		25: begin
			state <= 26;
		end
		26: begin
			state <= 27;
		end
		27: begin
			state <= 0;
		end
		28: begin
			state <= 31;
		end
		29: begin
			state <= 30;
		end
		30: begin
			state <= 0;
		end
		31: begin
			state <= 0;
		end
		32: begin
			state <= 28;
		end
		33: begin
			if(MemOK) begin
				state <= 0;
			end
		end
		34: begin
			state <= 0;
		end
		default: begin
			state <= 0;
		end
	endcase
end

assign state0 = (state == 0);
assign state1 = (state == 1);
assign state2 = (state == 2);
assign state3 = (state == 3);
assign state4 = (state == 4);
assign state5 = (state == 5);
assign state6 = (state == 6);
assign state7 = (state == 7);
assign state8 = (state == 8);
assign state9 = (state == 9);
assign state10 = (state == 10);
assign state11 = (state == 11);
assign state13 = (state == 13);
assign state14 = (state == 14);
assign state15 = (state == 15);
assign state16 = (state == 16);
assign state17 = (state == 17);
assign state18 = (state == 18);
assign state19 = (state == 19);
assign state20 = (state == 20);
assign state21 = (state == 21);
assign state22 = (state == 22);
assign state23 = (state == 23);
assign state24 = (state == 24);
assign state25 = (state == 25);
assign state26 = (state == 26);
assign state27 = (state == 27);
assign state28 = (state == 28);
assign state29 = (state == 29);
assign state30 = (state == 30);
assign state31 = (state == 31);
assign state32 = (state == 32);
assign state33 = (state == 33);
assign state34 = (state == 34);

assign PCWrite = state9 | state13 | state14 | state15 | (state23 & MemOK)|state27 | state28;
assign PCWriteCond = state8 | state34;
assign IorD = state3 | state5 | state10 | state11;
assign MemRead = state0 | state3 | state10;
assign MemWrite = state5 | state11;
assign WriteData[2] = state18;
assign WriteData[1] = state13 | state15 | state16;
assign WriteData[0] = state4 | state16;
assign IRWrite = state23 & MemOK;
assign ALUop[1] = state6 | state19 | state20 | state21 | state22;
assign ALUop[0] = state8 | state34;
assign ALUSrcA[1] = state19;
assign ALUSrcA[0] = state2 | state6 | state8 | state20 | state21 | state22 | state34;
assign ALUSrcB[2] = state21;
assign ALUSrcB[1] = state1 | state2 | state20;
assign ALUSrcB[0] = state1 | state23;
assign RegWrite = (state4 & MemOK) | state7 | state13 | state15 | state16 | state18 | state24;
assign RegDst[1] = state13;
assign RegDst[0] = state7 | state15;
assign SaveHalf = state11;
assign LoadHalf = state10;
assign PCSource[2] = state27 | state28;
assign PCSource[1] = state9 | state13 | state14 | state15;
assign PCSource[0] = state8 | state14 | state15 | state27 | state34;
assign IsBne = state34;
assign ALUFunc = 
	{6{R}} & func |
	{6{ADDI}}  & 6'h20 |
	{6{ADDIU}} & 6'h21 |
	{6{SLTI}}  & 6'h2A |
	{6{SLTIU}} & 6'h2B |
	{6{ANDI}}  & 6'h24 |
	{6{ORI}}   & 6'h25 |
	{6{XORI}}  & 6'h26 |
	{6{MUL}}   & 6'h3f;
assign C0Write = state17 | state25 | state26 | state29 | state31;
assign C0Dst[1]= state0 | state25 | state29 | state28 | state31;
assign C0Dst[0]= state26 | state29 | state32;
assign C0Src[2]= state31;
assign C0Src[1]= state25 | state29;
assign C0Src[0]= state26 | state29;
assign CauseSource = state30;
assign SyscallInte = state30;
endmodule