data/full_repos/permissive/501880753/memory_interface_FSM.v
data/verilator_xmls/efb0a883-1fb5-4dcb-a283-229d440a36f4.xml
module memory_interface_FSM (
	input clk, reset, rdy, rw,
	output reg oe, we,
	output reg [1:0] present_state
);

	reg [1:0] NS, PS;
	

	localparam IDLE = 2'b00,
					CHKRW = 2'b01,
					READ = 2'b10,
					WRITE = 2'b11;

	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			PS <= IDLE;
		else
			PS <= NS;
	end

	always @ (*)
	begin
	
		NS = PS;
		
		case(PS)
		
			IDLE:
				begin
					NS = (rdy == 1) ? CHKRW : IDLE;
					oe = 0;
					we = 0;
				end
			
			CHKRW:
				begin
					if (rw == 1)
					begin
						oe = rw;
						NS = READ;
					end
					else
					begin
						we = ~rw;
						NS = WRITE;
					end
				end
			
			READ:
				NS = (rdy == 1) ? READ : IDLE;
			
			WRITE:
				NS = (rdy == 1) ? WRITE : IDLE;
			
			default:
				NS = PS;
				
		endcase
		
		present_state = PS;
		
	end
endmodule
module memory_interface_FSM (
	input clk, reset, rdy, rw,
	output reg oe, we,
	output reg [1:0] present_state
);


	reg [1:0] NS, PS;
	

	localparam IDLE = 2'b00,
					CHKRW = 2'b01,
					READ = 2'b10,
					WRITE = 2'b11;

	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			PS <= IDLE;
		else
			PS <= NS;
	end

	always @ (*)
	begin
	
		NS = PS;
		
		case(PS)
		
			IDLE:
				begin
					NS = (rdy == 1) ? CHKRW : IDLE;
					oe = 0;
					we = 0;
				end
			
			CHKRW:
				begin
					if (rw == 1)
					begin
						oe = rw;
						NS = READ;
					end
					else
					begin
						we = ~rw;
						NS = WRITE;
					end
				end
			
			READ:
				NS = (rdy == 1) ? READ : IDLE;
			
			WRITE:
				NS = (rdy == 1) ? WRITE : IDLE;
			
			default:
				NS = PS;
				
		endcase
		
		present_state = PS;
		
	end
endmodule