data/full_repos/permissive/443867168/Verilog/CLA_clked.v
1: b"%Error: data/full_repos/permissive/443867168/Verilog/CLA_clked.v:29: Cannot find file containing module: 'CLA'\n    CLA abc(.a(Q_a),.b(Q_b),.Cin(Cin),.sum(D_sum),.Cout(D_Cout));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/443867168/Verilog,data/full_repos/permissive/443867168/CLA\n             data/full_repos/permissive/443867168/Verilog,data/full_repos/permissive/443867168/CLA.v\n             data/full_repos/permissive/443867168/Verilog,data/full_repos/permissive/443867168/CLA.sv\n             CLA\n             CLA.v\n             CLA.sv\n             obj_dir/CLA\n             obj_dir/CLA.v\n             obj_dir/CLA.sv\n%Error: Exiting due to 1 error(s)\n"
module CLA_clked (

    input CLK,
    input [3:0] a,
    input [3:0] b,
    input Cin,


    output reg [3:0] sum,
    output reg Cout

    );


    reg [3:0] Q_a;
    reg [3:0] Q_b;
    wire [3:0] D_sum;
    wire D_Cout;

    always @(posedge CLK)
    begin

        Q_a = a;
        Q_b = b;
    end


    CLA abc(.a(Q_a),.b(Q_b),.Cin(Cin),.sum(D_sum),.Cout(D_Cout));

    always @(posedge CLK)
    begin

        sum = D_sum;
        Cout = D_Cout;
    end
endmodule
module CLA_clked (

    input CLK,
    input [3:0] a,
    input [3:0] b,
    input Cin,


    output reg [3:0] sum,
    output reg Cout

    );



    reg [3:0] Q_a;
    reg [3:0] Q_b;
    wire [3:0] D_sum;
    wire D_Cout;

    always @(posedge CLK)
    begin

        Q_a = a;
        Q_b = b;
    end


    CLA abc(.a(Q_a),.b(Q_b),.Cin(Cin),.sum(D_sum),.Cout(D_Cout));

    always @(posedge CLK)
    begin

        sum = D_sum;
        Cout = D_Cout;
    end
endmodule