data/full_repos/permissive/447976230/fpga/usrp1/megacells/bustri_bb.v
data/verilator_xmls/e1f8cce5-9eff-404f-ba98-87b6372834fe.xml
module bustri (
	data,
	enabledt,
	tridata);

	input	[15:0]  data;
	input	  enabledt;
	inout	[15:0]  tridata;

endmodule
module bustri (
	data,
	enabledt,
	tridata);


	input	[15:0]  data;
	input	  enabledt;
	inout	[15:0]  tridata;

endmodule