data/full_repos/permissive/458935738/common/minmax.v
data/verilator_xmls/a68231ec-d3e1-4b49-bbf7-f2b2d08cf73a.xml
module minmax4 (
    data0, data1, data2, data3,
    min, max
);
    parameter BIT_WIDTH = 16;

    input [BIT_WIDTH-1:0] data0, data1, data2, data3;
    output wire [BIT_WIDTH-1:0] min, max;

    wire [BIT_WIDTH-1:0] min01, min23, max01, max23;
    
    assign min01 = data0 < data1 ? data0 : data1;
    assign max01 = data0 < data1 ? data1 : data0;
    assign min23 = data2 < data3 ? data2 : data3;
    assign max23 = data2 < data3 ? data3 : data2;

    assign min = min01 < min23 ? min01 : min23;
    assign max = max01 > max23 ? max01 : max23;

endmodule
module minmax4 (
    data0, data1, data2, data3,
    min, max
);

    parameter BIT_WIDTH = 16;

    input [BIT_WIDTH-1:0] data0, data1, data2, data3;
    output wire [BIT_WIDTH-1:0] min, max;

    wire [BIT_WIDTH-1:0] min01, min23, max01, max23;
    
    assign min01 = data0 < data1 ? data0 : data1;
    assign max01 = data0 < data1 ? data1 : data0;
    assign min23 = data2 < data3 ? data2 : data3;
    assign max23 = data2 < data3 ? data3 : data2;

    assign min = min01 < min23 ? min01 : min23;
    assign max = max01 > max23 ? max01 : max23;

endmodule