data/full_repos/permissive/528831163/src/dec_round_permutation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528831163/src/dec_round_permutation.v:2: Operator VAR \'shift\' expects 6 bits on the Initial value, but Initial value\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                  : ... In instance dec_round_permutation\n    parameter [5:0] shift = 5\'b0000,\n                    ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/528831163/src/dec_round_permutation.v:9: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'shift\' generates 6 bits.\n                                                                                  : ... In instance dec_round_permutation\n    assign o_rp = (i_rp >> shift) | (i_rp << (data_length - shift));\n                                                          ^\n%Error: Exiting due to 2 warning(s)\n'
module dec_round_permutation #(
    parameter [5:0] shift = 5'b0000,
    parameter [7:0] data_length = 8'd16
)(
    input [data_length - 1:0] i_rp,  output [data_length - 1:0] o_rp
); 
    

    assign o_rp = (i_rp >> shift) | (i_rp << (data_length - shift));
endmodule
module dec_round_permutation #(
    parameter [5:0] shift = 5'b0000,
    parameter [7:0] data_length = 8'd16
)(
    input [data_length - 1:0] i_rp,  output [data_length - 1:0] o_rp
);
 
    

    assign o_rp = (i_rp >> shift) | (i_rp << (data_length - shift));
endmodule