data/full_repos/permissive/509990356/PS2 mouse protocol parser with data path.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/509990356/PS2\n        ... Looked in:\n             data/full_repos/permissive/509990356,data/full_repos/permissive/509990356/data/full_repos/permissive/509990356/PS2\n             data/full_repos/permissive/509990356,data/full_repos/permissive/509990356/data/full_repos/permissive/509990356/PS2.v\n             data/full_repos/permissive/509990356,data/full_repos/permissive/509990356/data/full_repos/permissive/509990356/PS2.sv\n             data/full_repos/permissive/509990356/PS2\n             data/full_repos/permissive/509990356/PS2.v\n             data/full_repos/permissive/509990356/PS2.sv\n             obj_dir/data/full_repos/permissive/509990356/PS2\n             obj_dir/data/full_repos/permissive/509990356/PS2.v\n             obj_dir/data/full_repos/permissive/509990356/PS2.sv\n%Error: Cannot find file containing module: mouse\n%Error: Cannot find file containing module: protocol\n%Error: Cannot find file containing module: parser\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: data\n%Error: Cannot find file containing module: path.v\n%Error: Exiting due to 7 error(s)\n'
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output [23:0] out_bytes,
    output done);
    

    reg [2:0] state,next_state;
    reg [23:0] temp;
    parameter BYTE1=0,BYTE2=1,BYTE3=2,DONE=4;
    

   always@(*)begin
        case(state)
            BYTE1: next_state=(in[3])? BYTE2: BYTE1;
            BYTE2: next_state= BYTE3;
            BYTE3: next_state= DONE;
            DONE:  next_state= (in[3])? BYTE2: BYTE1;
        endcase
    end         
    

    always@(posedge clk)begin
        if(reset)
            state<=BYTE1;
        else
            state<=next_state;
    end
    
    always@(posedge clk)begin
        case(state)
            BYTE1: temp[23:16]=in;
            BYTE2: temp[15:8]=in;
            BYTE3: temp[7:0]=in;
            DONE : temp[23:16]=in;
        endcase
    end
    

    assign done =(state==DONE);
    

    assign out_bytes= temp & {24{done}};

endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output [23:0] out_bytes,
    output done);

    

    reg [2:0] state,next_state;
    reg [23:0] temp;
    parameter BYTE1=0,BYTE2=1,BYTE3=2,DONE=4;
    

   always@(*)begin
        case(state)
            BYTE1: next_state=(in[3])? BYTE2: BYTE1;
            BYTE2: next_state= BYTE3;
            BYTE3: next_state= DONE;
            DONE:  next_state= (in[3])? BYTE2: BYTE1;
        endcase
    end         
    

    always@(posedge clk)begin
        if(reset)
            state<=BYTE1;
        else
            state<=next_state;
    end
    
    always@(posedge clk)begin
        case(state)
            BYTE1: temp[23:16]=in;
            BYTE2: temp[15:8]=in;
            BYTE3: temp[7:0]=in;
            DONE : temp[23:16]=in;
        endcase
    end
    

    assign done =(state==DONE);
    

    assign out_bytes= temp & {24{done}};

endmodule