data/full_repos/permissive/42434302/ivltests/pr2976242.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr2976242.v:4: syntax error, unexpected var, expecting IDENTIFIER or do or final\n  wire [3:0] var;\n             ^~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2976242.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1 rvar = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2976242.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 rvar = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2976242.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 rvar = 2\'b11;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2976242.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (pass) $display("PASSED");\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2976242.v:22: syntax error, unexpected var, expecting \')\'\n  bit_to_real u6(var[0]);\n                 ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2976242.v:23: syntax error, unexpected var, expecting \')\'\n  vec_to_real u7(var);\n                 ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2976242.v:24: syntax error, unexpected var, expecting \')\'\n  vec_to_real u8[1:0](var);\n                      ^~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module vec_to_real (input wire real in);
  always @(in) if (in != $stime) begin
    $display("Failed vec_to_real %m at %1d, got %0d, expected %0d",
             $stime, in, $stime);
    top.pass = 1'b0;
  end
endmodule
module vec_to_real (input wire real in);

  always @(in) if (in != $stime) begin
    $display("Failed vec_to_real %m at %1d, got %0d, expected %0d",
             $stime, in, $stime);
    top.pass = 1'b0;
  end
endmodule