data/full_repos/permissive/522122051/src/iiitb_pwm_gen.v
data/verilator_xmls/929ef1e9-ad3a-4099-a83a-cdc96922902b.xml
module iiitb_pwm_gen
 (
 clk,
 increase_duty,
 decrease_duty,
 reset, 
 PWM_OUT
    );
 
 input clk,reset;
 input increase_duty;
 input decrease_duty;
 output PWM_OUT ;
 wire slow_clk_enable;
 reg[27:0] counter_debounce;
 reg tmp1,tmp2;
 reg tmp3,tmp4;
 wire duty_inc, duty_dec;
 reg[3:0] counter_PWM;
 reg[3:0] DUTY_CYCLE; 


  
 always @(posedge clk or posedge reset)
 begin
 if(reset) begin
 counter_debounce<=28'd0;
  counter_PWM<=4'd0;
  DUTY_CYCLE<=4'd5;
  tmp1 <= 0;
  tmp2 <= 0;
  tmp3<=0;
  tmp4<=0;
  end
 else begin
 	counter_debounce <= counter_debounce>=28'd1 ? 28'd0 : counter_debounce + 28'd1;
 	if(duty_inc==1 && DUTY_CYCLE <= 9) begin
        DUTY_CYCLE <= DUTY_CYCLE + 4'd1;
        end
        else if(duty_dec==1 && DUTY_CYCLE>=1) begin

        DUTY_CYCLE <= DUTY_CYCLE - 4'd1;
        end
        counter_PWM <= counter_PWM + 4'd1;
        if(counter_PWM>=9) begin
        counter_PWM <= 0;
        end
        if(slow_clk_enable==1) begin
  	tmp1 <= increase_duty;
  	tmp2 <= tmp1;
  	tmp3 <= decrease_duty;
  	tmp4 <= tmp3;
  	end
    end
 end
 
 assign slow_clk_enable = counter_debounce == 1 ?1:0;
  
 assign duty_inc =  tmp1 & (~ tmp2) & slow_clk_enable;
  
 assign duty_dec =  tmp3 & (~ tmp4) & slow_clk_enable;
 
 assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
 
endmodule
module iiitb_pwm_gen
 (
 clk,
 increase_duty,
 decrease_duty,
 reset, 
 PWM_OUT
    );

 
 input clk,reset;
 input increase_duty;
 input decrease_duty;
 output PWM_OUT ;
 wire slow_clk_enable;
 reg[27:0] counter_debounce;
 reg tmp1,tmp2;
 reg tmp3,tmp4;
 wire duty_inc, duty_dec;
 reg[3:0] counter_PWM;
 reg[3:0] DUTY_CYCLE; 


  
 always @(posedge clk or posedge reset)
 begin
 if(reset) begin
 counter_debounce<=28'd0;
  counter_PWM<=4'd0;
  DUTY_CYCLE<=4'd5;
  tmp1 <= 0;
  tmp2 <= 0;
  tmp3<=0;
  tmp4<=0;
  end
 else begin
 	counter_debounce <= counter_debounce>=28'd1 ? 28'd0 : counter_debounce + 28'd1;
 	if(duty_inc==1 && DUTY_CYCLE <= 9) begin
        DUTY_CYCLE <= DUTY_CYCLE + 4'd1;
        end
        else if(duty_dec==1 && DUTY_CYCLE>=1) begin

        DUTY_CYCLE <= DUTY_CYCLE - 4'd1;
        end
        counter_PWM <= counter_PWM + 4'd1;
        if(counter_PWM>=9) begin
        counter_PWM <= 0;
        end
        if(slow_clk_enable==1) begin
  	tmp1 <= increase_duty;
  	tmp2 <= tmp1;
  	tmp3 <= decrease_duty;
  	tmp4 <= tmp3;
  	end
    end
 end
 
 assign slow_clk_enable = counter_debounce == 1 ?1:0;
  
 assign duty_inc =  tmp1 & (~ tmp2) & slow_clk_enable;
  
 assign duty_dec =  tmp3 & (~ tmp4) & slow_clk_enable;
 
 assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
 
endmodule