data/full_repos/permissive/515648441/true_dpram_dclk_tb.v
1: b'%Error: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:1: Cannot find include file: true_dpram_dclk.v\n`include "true_dpram_dclk.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515648441,data/full_repos/permissive/515648441/true_dpram_dclk.v\n             data/full_repos/permissive/515648441,data/full_repos/permissive/515648441/true_dpram_dclk.v.v\n             data/full_repos/permissive/515648441,data/full_repos/permissive/515648441/true_dpram_dclk.v.sv\n             true_dpram_dclk.v\n             true_dpram_dclk.v.v\n             true_dpram_dclk.v.sv\n             obj_dir/true_dpram_dclk.v\n             obj_dir/true_dpram_dclk.v.v\n             obj_dir/true_dpram_dclk.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #50 clk_A = ~clk_A;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  forever #60 clk_B = ~clk_B;\n          ^\n%Error: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:32: Unsupported or unknown PLI call: $monitor\n  $monitor("TIME = %0t,\\nAddress @ A = %0h , Data @ A = %0h,\\nAddress @ B = %0h, Data @ B = %0h", $time, addr_A, data_in_A, addr_B, data_in_B);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("true_dpram_dclk_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, true_dpram_dclk_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515648441/true_dpram_dclk_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module true_dpram_dclk_tb();
	reg wr_en_A, wr_en_B, clk_A, clk_B;
	reg [WIDTH - 1:0] data_in_A, data_in_B;
	reg [ADDRESS - 1:0] addr_A, addr_B;
	wire [WIDTH - 1:0] data_out_A, data_out_B;

	true_dpram_dclk dut(
		.data_in_A(data_in_A),
		.data_in_B(data_in_B),
		.addr_A(addr_A),
		.addr_B(addr_B),
		.wr_en_A(wr_en_A),
		.wr_en_B(wr_en_B),
		.clk_A(clk_A),
		.clk_B(clk_B),
		.data_out_A(data_out_A),
		.data_out_B(data_out_B) );

	initial begin
		clk_A = 1'b1;
		forever #50 clk_A = ~clk_A;
	end

	initial begin
		clk_B = 1'b1;
		forever #60 clk_B = ~clk_B;
	end

	initial begin
		$monitor("TIME = %0t,\nAddress @ A = %0h , Data @ A = %0h,\nAddress @ B = %0h, Data @ B = %0h", $time, addr_A, data_in_A, addr_B, data_in_B);
		$dumpfile("true_dpram_dclk_tb.vcd");
		$dumpvars(0, true_dpram_dclk_tb);
		
		wr_en_A = 1'b0; wr_en_B = 1'b0;
		#100;
		
		addr_A = 6'h28; data_in_A = 8'hB5;
		addr_B = 6'h3D; data_in_B = 8'h6F;
		wr_en_A = 1'b1; wr_en_B = 1'b1;
		#100;
		
		#1000 $finish;
	end
endmodule
module true_dpram_dclk_tb();

	reg wr_en_A, wr_en_B, clk_A, clk_B;
	reg [WIDTH - 1:0] data_in_A, data_in_B;
	reg [ADDRESS - 1:0] addr_A, addr_B;
	wire [WIDTH - 1:0] data_out_A, data_out_B;

	true_dpram_dclk dut(
		.data_in_A(data_in_A),
		.data_in_B(data_in_B),
		.addr_A(addr_A),
		.addr_B(addr_B),
		.wr_en_A(wr_en_A),
		.wr_en_B(wr_en_B),
		.clk_A(clk_A),
		.clk_B(clk_B),
		.data_out_A(data_out_A),
		.data_out_B(data_out_B) );

	initial begin
		clk_A = 1'b1;
		forever #50 clk_A = ~clk_A;
	end

	initial begin
		clk_B = 1'b1;
		forever #60 clk_B = ~clk_B;
	end

	initial begin
		$monitor("TIME = %0t,\nAddress @ A = %0h , Data @ A = %0h,\nAddress @ B = %0h, Data @ B = %0h", $time, addr_A, data_in_A, addr_B, data_in_B);
		$dumpfile("true_dpram_dclk_tb.vcd");
		$dumpvars(0, true_dpram_dclk_tb);
		
		wr_en_A = 1'b0; wr_en_B = 1'b0;
		#100;
		
		addr_A = 6'h28; data_in_A = 8'hB5;
		addr_B = 6'h3D; data_in_B = 8'h6F;
		wr_en_A = 1'b1; wr_en_B = 1'b1;
		#100;
		
		#1000 $finish;
	end
endmodule