data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:588: Operator MODDIV expects 3 bits on the RHS, but RHS\'s VARREF \'den\' generates 2 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_rem_45\n    assign y = num % den;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:588: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 3 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_rem_45\n    assign y = num % den;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_11\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_18\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_21\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 7 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_32\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_46\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockMemTest/reference/MultiClockMemTest.v:517: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 9 bits.\n                                                                                                                             : ... In instance MultiClockMemTest.u_pad_48\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 8 warning(s)\n'
module DFF_POSCLK(q, d, clk);
    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule
module DFF_POSCLK(q, d, clk);

    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule