data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_dff_sync_reset.v
data/verilator_xmls/04c2dab3-b93b-40cd-b457-185f380fede1.xml
module dff_sync_reset (
data   ,
clk    ,
reset  ,
q
);

input data, clk, reset ; 


output q;


reg q;


always @ ( posedge clk)
if (~reset) begin
  q <= 1'b0;
end  else begin
  q <= data;
end

endmodule
module dff_sync_reset (
data   ,
clk    ,
reset  ,
q
);


input data, clk, reset ; 


output q;


reg q;


always @ ( posedge clk)
if (~reset) begin
  q <= 1'b0;
end  else begin
  q <= data;
end

endmodule