data/full_repos/permissive/513199821/regfile.v
1: b'%Error: data/full_repos/permissive/513199821/regfile.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: data/full_repos/permissive/513199821/regfile.v:31: Define or directive not defined: \'`R_ZERO\'\n    rfile[`R_ZERO] <= 0;  \n          ^~~~~~~\n%Error: data/full_repos/permissive/513199821/regfile.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    rfile[`R_ZERO] <= 0;  \n                 ^\n%Error: data/full_repos/permissive/513199821/regfile.v:42: Define or directive not defined: \'`R_ZERO\'\n    if (rd != `R_ZERO) begin\n              ^~~~~~~\n%Error: data/full_repos/permissive/513199821/regfile.v:42: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (rd != `R_ZERO) begin\n                     ^\n%Error: data/full_repos/permissive/513199821/regfile.v:49: syntax error, unexpected end\nend\n^~~\n%Error: Cannot continue\n'
module regfile
  #(
     parameter WIDTH = 16
  ) (
    input  clk,
    input  rst,
    input  [4:0] r0,
    input  [4:0] r1,
    input  [4:0] rd,
    input  [WIDTH - 1:0] data,

    output [WIDTH - 1:0] v0,
    output [WIDTH - 1:0] v1
);


reg [WIDTH - 1:0] rfile [0:31];


assign v0 = rfile[r0];
assign v1 = rfile[r1];


integer i;

always @ (posedge clk)
begin
  if (rst) begin
    rfile[`R_ZERO] <= 0;
`ifdef TEST
    rfile[19] <= 0;
    for (i = 0; i < 16; i++)
      rfile[i] <= i;
`endif
  end else begin
`ifdef TEST
    rfile[19] <= rfile[19] + 1'b1;
`endif

    if (rd != `R_ZERO) begin
      rfile[rd] <= data;
`ifdef TEST_OFF
      $display ("WRITE\t%x rd=%x result=%x", rfile[19], rd, data);
`endif
     end
  end
end

endmodule
module regfile
  #(
     parameter WIDTH = 16
  ) (
    input  clk,
    input  rst,
    input  [4:0] r0,
    input  [4:0] r1,
    input  [4:0] rd,
    input  [WIDTH - 1:0] data,

    output [WIDTH - 1:0] v0,
    output [WIDTH - 1:0] v1
);



reg [WIDTH - 1:0] rfile [0:31];


assign v0 = rfile[r0];
assign v1 = rfile[r1];


integer i;

always @ (posedge clk)
begin
  if (rst) begin
    rfile[`R_ZERO] <= 0;
`ifdef TEST
    rfile[19] <= 0;
    for (i = 0; i < 16; i++)
      rfile[i] <= i;
`endif
  end else begin
`ifdef TEST
    rfile[19] <= rfile[19] + 1'b1;
`endif

    if (rd != `R_ZERO) begin
      rfile[rd] <= data;
`ifdef TEST_OFF
      $display ("WRITE\t%x rd=%x result=%x", rfile[19], rd, data);
`endif
     end
  end
end

endmodule