data/full_repos/permissive/451577625/system/reducer_64.v
1: b'%Error: data/full_repos/permissive/451577625/system/reducer_64.v:14: Cannot find file containing module: \'reducer_4_to_2\'\n    reducer_4_to_2 reducer(.in_w (in_w[i]),\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2.sv\n             reducer_4_to_2\n             reducer_4_to_2.v\n             reducer_4_to_2.sv\n             obj_dir/reducer_4_to_2\n             obj_dir/reducer_4_to_2.v\n             obj_dir/reducer_4_to_2.sv\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3b9aca00\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3b9aca00\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h4c4b40\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h4c4b40\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                                                        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module reducer_64 (input [63:0] in_w, input [63:0] in_x, input [63:0] in_y, input [63:0] in_z, input in_cin, output [63:0] out_sum, output [63:0] out_carry, output out_cout);

		wire [64:0] w_carries;
		wire [63:0] w_out_carry_pre_shift;
		
		assign w_carries[0] = in_cin;
		assign out_cout = w_carries[64];
		assign out_carry = {w_out_carry_pre_shift[62:0], 1'b0};

		genvar i;
		
		generate
			for(i = 0; i < 64; i = i + 1) begin : gen_reducer_4_to_2
				reducer_4_to_2 reducer(.in_w (in_w[i]),
					.in_x (in_x[i]),
					.in_y (in_y[i]),
					.in_z (in_z[i]),
					.in_cin (w_carries[i]),
					.out_sum (out_sum[i]),
					.out_carry (w_out_carry_pre_shift[i]),
					.out_cout (w_carries[i+1]));
			end
		endgenerate

endmodule
module reducer_64 (input [63:0] in_w, input [63:0] in_x, input [63:0] in_y, input [63:0] in_z, input in_cin, output [63:0] out_sum, output [63:0] out_carry, output out_cout);


		wire [64:0] w_carries;
		wire [63:0] w_out_carry_pre_shift;
		
		assign w_carries[0] = in_cin;
		assign out_cout = w_carries[64];
		assign out_carry = {w_out_carry_pre_shift[62:0], 1'b0};

		genvar i;
		
		generate
			for(i = 0; i < 64; i = i + 1) begin : gen_reducer_4_to_2
				reducer_4_to_2 reducer(.in_w (in_w[i]),
					.in_x (in_x[i]),
					.in_y (in_y[i]),
					.in_z (in_z[i]),
					.in_cin (w_carries[i]),
					.out_sum (out_sum[i]),
					.out_carry (w_out_carry_pre_shift[i]),
					.out_cout (w_carries[i+1]));
			end
		endgenerate

endmodule