data/full_repos/permissive/445455582/single/RiSC16_control.v
1: b"%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:57: Define or directive not defined: '`ALU_FUNCT_LEN'\n    output reg [`ALU_FUNCT_LEN - 1 : 0] aluFunct = `ALU_ADD;\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:57: Define or directive not defined: '`ALU_ADD'\n    output reg [`ALU_FUNCT_LEN - 1 : 0] aluFunct = `ALU_ADD;\n                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:57: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n    output reg [`ALU_FUNCT_LEN - 1 : 0] aluFunct = `ALU_ADD;\n                                                           ^\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:69: Define or directive not defined: '`ALU_ADD'\n            aluFunct    <= `ALU_ADD;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:69: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n            aluFunct    <= `ALU_ADD;\n                                   ^\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:79: Define or directive not defined: '`OP_ADD'\n                `OP_ADD:    begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:79: syntax error, unexpected ':', expecting endcase\n                `OP_ADD:    begin\n                       ^\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:80: Define or directive not defined: '`ALU_ADD'\n                    aluFunct    <= `ALU_ADD;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:90: Define or directive not defined: '`OP_ADDI'\n                `OP_ADDI:   begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:90: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_ADDI:   begin\n                            ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:91: Define or directive not defined: '`ALU_ADD'\n                    aluFunct    <= `ALU_ADD;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:101: Define or directive not defined: '`OP_NAND'\n                `OP_NAND:   begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:101: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_NAND:   begin\n                            ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:102: Define or directive not defined: '`ALU_NAND'\n                    aluFunct    <= `ALU_NAND;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:112: Define or directive not defined: '`OP_LUI'\n                `OP_LUI:    begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:112: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_LUI:    begin\n                            ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:113: Define or directive not defined: '`ALU_PASSA'\n                    aluFunct    <= `ALU_PASSA;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:123: Define or directive not defined: '`OP_SW'\n                `OP_SW:     begin\n                ^~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:123: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_SW:     begin\n                            ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:124: Define or directive not defined: '`ALU_ADD'\n                    aluFunct    <= `ALU_ADD;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:134: Define or directive not defined: '`OP_LW'\n                `OP_LW:     begin\n                ^~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:134: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_LW:     begin\n                            ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:135: Define or directive not defined: '`ALU_ADD'\n                    aluFunct    <= `ALU_ADD;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:145: Define or directive not defined: '`OP_BEQ'\n                `OP_BEQ:     begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:145: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_BEQ:     begin\n                             ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:146: Define or directive not defined: '`ALU_SUB'\n                    aluFunct    <= `ALU_SUB;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:159: Define or directive not defined: '`OP_JALR'\n                `OP_JALR:     begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:159: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `OP_JALR:     begin\n                              ^~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:160: Define or directive not defined: '`ALU_PASSA'\n                    aluFunct    <= `ALU_PASSA;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_control.v:170: syntax error, unexpected endcase\n            endcase\n            ^~~~~~~\n%Error: Cannot continue\n"
module RiSC16_control #(
    parameter OP_LEN = 3
) (
    op, state, pen, 
    aluFunct, muxSrc1, muxSrc2, 
    d_wen, reg_wen, muxTrgt, muxAddr2, muxPc 
);

    input [OP_LEN - 1 : 0] op;
    input state;
    input pen;

    output reg [`ALU_FUNCT_LEN - 1 : 0] aluFunct = `ALU_ADD;
    output reg muxSrc1 = 0;
    output reg muxSrc2 = 0;
    output reg d_wen = 0;
    output reg reg_wen = 0;
    output reg [1:0] muxTrgt = 0;
    output reg muxAddr2 = 0;
    output reg [1:0] muxPc = 0;

    always @(*) begin
        
        if(pen) begin
            aluFunct    <= `ALU_ADD;
            muxSrc1     <=  0;
            muxSrc2     <=  0;
            d_wen       <=  0;
            reg_wen     <=  0;
            muxTrgt     <=  2'b00;
            muxAddr2    <=  0;
            muxPc       <=  2'b00;
        end else begin
            case (op)
                `OP_ADD:    begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_ADDI:   begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_NAND:   begin
                    aluFunct    <= `ALU_NAND;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_LUI:    begin
                    aluFunct    <= `ALU_PASSA;
                    muxSrc1     <= 1;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_SW:     begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 1;
                    reg_wen     <= 0;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 1;
                    muxPc       <= 2'b00;
                end

                `OP_LW:     begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_BEQ:     begin
                    aluFunct    <= `ALU_SUB;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 0;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 1;
                    if(state)
                        muxPc   <= 2'b10;
                    else
                        muxPc   <= 2'b00;
                end
                
                `OP_JALR:     begin
                    aluFunct    <= `ALU_PASSA;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b10;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b11;
                end

            endcase
        end

    end
    
endmodule
module RiSC16_control #(
    parameter OP_LEN = 3
) (
    op, state, pen, 
    aluFunct, muxSrc1, muxSrc2, 
    d_wen, reg_wen, muxTrgt, muxAddr2, muxPc 
);


    input [OP_LEN - 1 : 0] op;
    input state;
    input pen;

    output reg [`ALU_FUNCT_LEN - 1 : 0] aluFunct = `ALU_ADD;
    output reg muxSrc1 = 0;
    output reg muxSrc2 = 0;
    output reg d_wen = 0;
    output reg reg_wen = 0;
    output reg [1:0] muxTrgt = 0;
    output reg muxAddr2 = 0;
    output reg [1:0] muxPc = 0;

    always @(*) begin
        
        if(pen) begin
            aluFunct    <= `ALU_ADD;
            muxSrc1     <=  0;
            muxSrc2     <=  0;
            d_wen       <=  0;
            reg_wen     <=  0;
            muxTrgt     <=  2'b00;
            muxAddr2    <=  0;
            muxPc       <=  2'b00;
        end else begin
            case (op)
                `OP_ADD:    begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_ADDI:   begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_NAND:   begin
                    aluFunct    <= `ALU_NAND;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_LUI:    begin
                    aluFunct    <= `ALU_PASSA;
                    muxSrc1     <= 1;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b01;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_SW:     begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 1;
                    reg_wen     <= 0;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 1;
                    muxPc       <= 2'b00;
                end

                `OP_LW:     begin
                    aluFunct    <= `ALU_ADD;
                    muxSrc1     <= 0;
                    muxSrc2     <= 1;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b00;
                end

                `OP_BEQ:     begin
                    aluFunct    <= `ALU_SUB;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 0;
                    muxTrgt     <= 2'b00;
                    muxAddr2    <= 1;
                    if(state)
                        muxPc   <= 2'b10;
                    else
                        muxPc   <= 2'b00;
                end
                
                `OP_JALR:     begin
                    aluFunct    <= `ALU_PASSA;
                    muxSrc1     <= 0;
                    muxSrc2     <= 0;
                    d_wen       <= 0;
                    reg_wen     <= 1;
                    muxTrgt     <= 2'b10;
                    muxAddr2    <= 0;
                    muxPc       <= 2'b11;
                end

            endcase
        end

    end
    
endmodule