data/full_repos/permissive/487568919/basic_verilog/debounce.v
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/debounce.v:56: Cannot find file containing module: 'SetReset'\nSetReset SR (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/SetReset\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/SetReset.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/SetReset.sv\n             SetReset\n             SetReset.v\n             SetReset.sv\n             obj_dir/SetReset\n             obj_dir/SetReset.v\n             obj_dir/SetReset.sv\n%Error: Exiting due to 1 error(s)\n"
module debounce(clk,nrst,en,in,out);

input wire clk;
input wire nrst;
input wire en;

input wire [(WIDTH-1):0] in;
output wire [(WIDTH-1):0] out;

parameter WIDTH = 1;

reg [(WIDTH-1):0] d1 = 0;
reg [(WIDTH-1):0] d2 = 0;

always @ (posedge clk) begin
	if (~nrst) begin
		d1[(WIDTH-1):0] <= 0;
		d2[(WIDTH-1):0] <= 0;
	end
	else begin
		if (en) begin
			d1[(WIDTH-1):0] <= d2[(WIDTH-1):0];
			d2[(WIDTH-1):0] <= in[(WIDTH-1):0];
		end;
	end
end

wire [(WIDTH-1):0] switch_hi = (d2[(WIDTH-1):0] & d1[(WIDTH-1):0]);
wire [(WIDTH-1):0] n_switch_lo = (d2[(WIDTH-1):0] | d1[(WIDTH-1):0]);

SetReset SR (
	.clk(clk),
	.nrst(nrst),
	.s(switch_hi[(WIDTH-1):0]),
	.r(~n_switch_lo[(WIDTH-1):0]),
	.q(out[(WIDTH-1):0]),
	.nq()
	);
defparam SR.WIDTH = WIDTH;

endmodule
module debounce(clk,nrst,en,in,out);


input wire clk;
input wire nrst;
input wire en;

input wire [(WIDTH-1):0] in;
output wire [(WIDTH-1):0] out;

parameter WIDTH = 1;

reg [(WIDTH-1):0] d1 = 0;
reg [(WIDTH-1):0] d2 = 0;

always @ (posedge clk) begin
	if (~nrst) begin
		d1[(WIDTH-1):0] <= 0;
		d2[(WIDTH-1):0] <= 0;
	end
	else begin
		if (en) begin
			d1[(WIDTH-1):0] <= d2[(WIDTH-1):0];
			d2[(WIDTH-1):0] <= in[(WIDTH-1):0];
		end;
	end
end

wire [(WIDTH-1):0] switch_hi = (d2[(WIDTH-1):0] & d1[(WIDTH-1):0]);
wire [(WIDTH-1):0] n_switch_lo = (d2[(WIDTH-1):0] | d1[(WIDTH-1):0]);

SetReset SR (
	.clk(clk),
	.nrst(nrst),
	.s(switch_hi[(WIDTH-1):0]),
	.r(~n_switch_lo[(WIDTH-1):0]),
	.q(out[(WIDTH-1):0]),
	.nq()
	);
defparam SR.WIDTH = WIDTH;

endmodule