data/full_repos/permissive/443770883/lab5/Lab5-Student copy/reg_file.v
1: b'%Error: Cannot find file containing module: copy,data/full_repos/permissive/443770883\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab5/Lab5-Student/copy,data/full_repos/permissive/443770883\n             data/full_repos/permissive/443770883/lab5/Lab5-Student/copy,data/full_repos/permissive/443770883.v\n             data/full_repos/permissive/443770883/lab5/Lab5-Student/copy,data/full_repos/permissive/443770883.sv\n             copy,data/full_repos/permissive/443770883\n             copy,data/full_repos/permissive/443770883.v\n             copy,data/full_repos/permissive/443770883.sv\n             obj_dir/copy,data/full_repos/permissive/443770883\n             obj_dir/copy,data/full_repos/permissive/443770883.v\n             obj_dir/copy,data/full_repos/permissive/443770883.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/443770883/lab5/Lab5-Student\n%Error: Cannot find file containing module: copy/reg_file.v\n%Error: Exiting due to 3 error(s)\n'
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);


wire [0:7] load;
wire [0:15] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7;


demux8 dm0(wr, wr_addr[2],wr_addr[1],wr_addr[0],load);
dfrl16 f0(clk,reset,load[0],d_in,dout0);
dfrl16 f1(clk,reset,load[1],d_in,dout1);
dfrl16 f2(clk,reset,load[2],d_in,dout2);
dfrl16 f3(clk,reset,load[3],d_in,dout3);
dfrl16 f4(clk,reset,load[4],d_in,dout4);
dfrl16 f5(clk,reset,load[5],d_in,dout5);
dfrl16 f6(clk,reset,load[6],d_in,dout6);
dfrl16 f7(clk,reset,load[7],d_in,dout7);
mux8_16 m0(dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7, rd_addr_a, d_out_a);
mux8_16 m1(dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7, rd_addr_b, d_out_b);

endmodule
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);



wire [0:7] load;
wire [0:15] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7;


demux8 dm0(wr, wr_addr[2],wr_addr[1],wr_addr[0],load);
dfrl16 f0(clk,reset,load[0],d_in,dout0);
dfrl16 f1(clk,reset,load[1],d_in,dout1);
dfrl16 f2(clk,reset,load[2],d_in,dout2);
dfrl16 f3(clk,reset,load[3],d_in,dout3);
dfrl16 f4(clk,reset,load[4],d_in,dout4);
dfrl16 f5(clk,reset,load[5],d_in,dout5);
dfrl16 f6(clk,reset,load[6],d_in,dout6);
dfrl16 f7(clk,reset,load[7],d_in,dout7);
mux8_16 m0(dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7, rd_addr_a, d_out_a);
mux8_16 m1(dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7, rd_addr_b, d_out_b);

endmodule