data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalTester/reference/IntervalTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalTester/reference/IntervalTester.v:264: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                                       : ... In instance IntervalTester.s_pad_16\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalTester/reference/IntervalTester.v:264: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                       : ... In instance IntervalTester.s_pad_25\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalTester/reference/IntervalTester.v:264: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 7 bits.\n                                                                                                                       : ... In instance IntervalTester.s_pad_27\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalTester/reference/IntervalTester.v:193: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                       : ... In instance IntervalTester.u_pad_3\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 4 warning(s)\n'
module IntervalTester(
    input clock,
    input reset
);
    wire [3:0] _cycle__q;
    wire [3:0] _cycle__d;
    DFF_POSCLK #(.width(4)) cycle (
        .q(_cycle__q),
        .d(_cycle__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(4)) u_mux_1 (
        .y(_cycle__d),
        .sel(reset),
        .a(4'h0),
        .b(_WTEMP_0)
    );
    wire done;
    wire wrap_wrap;
    EQ_UNSIGNED #(.width(4)) u_eq_2 (
        .y(wrap_wrap),
        .a(_cycle__q),
        .b(4'hA)
    );
    wire [4:0] _wrap_value_T;
    wire [3:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_3 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_4 (
        .y(_wrap_value_T),
        .a(_cycle__q),
        .b(_WTEMP_1)
    );
    wire [3:0] _wrap_value_T_1;
    TAIL #(.width(5), .n(1)) tail_5 (
        .y(_wrap_value_T_1),
        .in(_wrap_value_T)
    );
    wire [3:0] _node_0;
    wire [3:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_6 (
        .y(_WTEMP_2),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_7 (
        .y(_node_0),
        .sel(wrap_wrap),
        .a(_WTEMP_2),
        .b(_wrap_value_T_1)
    );
    wire _T;
    BITS #(.width(1), .high(0), .low(0)) bits_8 (
        .y(_T),
        .in(reset)
    );
    wire _T_1;
    EQ_UNSIGNED #(.width(1)) u_eq_9 (
        .y(_T_1),
        .a(_T),
        .b(1'h0)
    );
    wire _dut__clock;
    wire _dut__reset;
    wire [4:0] _dut__io_in1;
    wire [7:0] _dut__io_in2;
    wire [8:0] _dut__io_out;
    IntervalTest1 dut (
        .clock(_dut__clock),
        .reset(_dut__reset),
        .io_in1(_dut__io_in1),
        .io_in2(_dut__io_in2),
        .io_out(_dut__io_out)
    );
    wire [3:0] _node_2;
    ASSINT #(.width(4)) assint_12 (
        .y(_node_2),
        .in(4'h4)
    );
    wire [6:0] _node_3;
    SHL_SIGNED #(.width(4), .n(3)) s_shl_13 (
        .y(_node_3),
        .in(_node_2)
    );
    wire [4:0] _node_4;
    ASSINT #(.width(5)) assint_14 (
        .y(_node_4),
        .in(5'h8)
    );
    wire [7:0] _node_5;
    SHL_SIGNED #(.width(5), .n(3)) s_shl_15 (
        .y(_node_5),
        .in(_node_4)
    );
    wire _T_2;
    wire [8:0] _WTEMP_3;
    PAD_SIGNED #(.width(8), .n(9)) s_pad_16 (
        .y(_WTEMP_3),
        .in(_node_5)
    );
    EQ_SIGNED #(.width(9)) s_eq_17 (
        .y(_T_2),
        .a(_dut__io_out),
        .b(_WTEMP_3)
    );
    wire _T_3;
    BITS #(.width(1), .high(0), .low(0)) bits_18 (
        .y(_T_3),
        .in(reset)
    );
    wire _T_4;
    BITWISEOR #(.width(1)) bitwiseor_19 (
        .y(_T_4),
        .a(_T_2),
        .b(_T_3)
    );
    wire _T_5;
    EQ_UNSIGNED #(.width(1)) u_eq_20 (
        .y(_T_5),
        .a(_T_4),
        .b(1'h0)
    );
    wire _T_6;
    BITS #(.width(1), .high(0), .low(0)) bits_21 (
        .y(_T_6),
        .in(reset)
    );
    wire _T_7;
    EQ_UNSIGNED #(.width(1)) u_eq_22 (
        .y(_T_7),
        .a(_T_6),
        .b(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_23 (
        .y(_WTEMP_0),
        .sel(1'h1),
        .a(_node_0),
        .b(_cycle__q)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_24 (
        .y(done),
        .sel(1'h1),
        .a(wrap_wrap),
        .b(1'h0)
    );
    assign _dut__clock = clock;
    wire [3:0] _WTEMP_4;
    PAD_SIGNED #(.width(4), .n(5)) s_pad_25 (
        .y(_dut__io_in1),
        .in(_WTEMP_4)
    );
    ASSINT #(.width(4)) assint_26 (
        .y(_WTEMP_4),
        .in(4'h4)
    );
    PAD_SIGNED #(.width(7), .n(8)) s_pad_27 (
        .y(_dut__io_in2),
        .in(_node_3)
    );
    assign _dut__reset = reset;
endmodule
module IntervalTester(
    input clock,
    input reset
);

    wire [3:0] _cycle__q;
    wire [3:0] _cycle__d;
    DFF_POSCLK #(.width(4)) cycle (
        .q(_cycle__q),
        .d(_cycle__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(4)) u_mux_1 (
        .y(_cycle__d),
        .sel(reset),
        .a(4'h0),
        .b(_WTEMP_0)
    );
    wire done;
    wire wrap_wrap;
    EQ_UNSIGNED #(.width(4)) u_eq_2 (
        .y(wrap_wrap),
        .a(_cycle__q),
        .b(4'hA)
    );
    wire [4:0] _wrap_value_T;
    wire [3:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_3 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_4 (
        .y(_wrap_value_T),
        .a(_cycle__q),
        .b(_WTEMP_1)
    );
    wire [3:0] _wrap_value_T_1;
    TAIL #(.width(5), .n(1)) tail_5 (
        .y(_wrap_value_T_1),
        .in(_wrap_value_T)
    );
    wire [3:0] _node_0;
    wire [3:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_6 (
        .y(_WTEMP_2),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_7 (
        .y(_node_0),
        .sel(wrap_wrap),
        .a(_WTEMP_2),
        .b(_wrap_value_T_1)
    );
    wire _T;
    BITS #(.width(1), .high(0), .low(0)) bits_8 (
        .y(_T),
        .in(reset)
    );
    wire _T_1;
    EQ_UNSIGNED #(.width(1)) u_eq_9 (
        .y(_T_1),
        .a(_T),
        .b(1'h0)
    );
    wire _dut__clock;
    wire _dut__reset;
    wire [4:0] _dut__io_in1;
    wire [7:0] _dut__io_in2;
    wire [8:0] _dut__io_out;
    IntervalTest1 dut (
        .clock(_dut__clock),
        .reset(_dut__reset),
        .io_in1(_dut__io_in1),
        .io_in2(_dut__io_in2),
        .io_out(_dut__io_out)
    );
    wire [3:0] _node_2;
    ASSINT #(.width(4)) assint_12 (
        .y(_node_2),
        .in(4'h4)
    );
    wire [6:0] _node_3;
    SHL_SIGNED #(.width(4), .n(3)) s_shl_13 (
        .y(_node_3),
        .in(_node_2)
    );
    wire [4:0] _node_4;
    ASSINT #(.width(5)) assint_14 (
        .y(_node_4),
        .in(5'h8)
    );
    wire [7:0] _node_5;
    SHL_SIGNED #(.width(5), .n(3)) s_shl_15 (
        .y(_node_5),
        .in(_node_4)
    );
    wire _T_2;
    wire [8:0] _WTEMP_3;
    PAD_SIGNED #(.width(8), .n(9)) s_pad_16 (
        .y(_WTEMP_3),
        .in(_node_5)
    );
    EQ_SIGNED #(.width(9)) s_eq_17 (
        .y(_T_2),
        .a(_dut__io_out),
        .b(_WTEMP_3)
    );
    wire _T_3;
    BITS #(.width(1), .high(0), .low(0)) bits_18 (
        .y(_T_3),
        .in(reset)
    );
    wire _T_4;
    BITWISEOR #(.width(1)) bitwiseor_19 (
        .y(_T_4),
        .a(_T_2),
        .b(_T_3)
    );
    wire _T_5;
    EQ_UNSIGNED #(.width(1)) u_eq_20 (
        .y(_T_5),
        .a(_T_4),
        .b(1'h0)
    );
    wire _T_6;
    BITS #(.width(1), .high(0), .low(0)) bits_21 (
        .y(_T_6),
        .in(reset)
    );
    wire _T_7;
    EQ_UNSIGNED #(.width(1)) u_eq_22 (
        .y(_T_7),
        .a(_T_6),
        .b(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_23 (
        .y(_WTEMP_0),
        .sel(1'h1),
        .a(_node_0),
        .b(_cycle__q)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_24 (
        .y(done),
        .sel(1'h1),
        .a(wrap_wrap),
        .b(1'h0)
    );
    assign _dut__clock = clock;
    wire [3:0] _WTEMP_4;
    PAD_SIGNED #(.width(4), .n(5)) s_pad_25 (
        .y(_dut__io_in1),
        .in(_WTEMP_4)
    );
    ASSINT #(.width(4)) assint_26 (
        .y(_WTEMP_4),
        .in(4'h4)
    );
    PAD_SIGNED #(.width(7), .n(8)) s_pad_27 (
        .y(_dut__io_in2),
        .in(_node_3)
    );
    assign _dut__reset = reset;
endmodule