data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/BASIC/v_rtl/dut_Add_16Ux16U_17U_4.v
data/verilator_xmls/e70dbb52-3883-40fb-8d8c-958f6165b6a5.xml
module dut_Add_16Ux16U_17U_4 (
	in2,
	in1,
	out1
	);
input [15:0] in2,
	in1;
output [16:0] out1;
wire [16:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_16Ux16U_17U_4 (
	in2,
	in1,
	out1
	);

input [15:0] in2,
	in1;
output [16:0] out1;
wire [16:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule