data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:137: syntax error, unexpected \'@\'\n Done_Picture_Decode_O = 1\'b0; @(posedge clock);\n                               ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:139: syntax error, unexpected \'@\'\n while (~Slice_Start_Code_I) @(posedge clock);\n                             ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:140: syntax error, unexpected \'@\'\n Shift_8_En_O = 1\'b0; @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:143: syntax error, unexpected \'@\'\n  Shift_8_En_O = 1\'b1; @(posedge clock); \n                       ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:144: syntax error, unexpected \'@\'\n  Shift_8_En_O = 1\'b0; shift_1_reg = 1\'b1; @(posedge clock); \n                                           ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:148: syntax error, unexpected \'@\'\n   @(posedge clock);\n   ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:152: syntax error, unexpected \'@\'\n   @(posedge clock);\n   ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_Picture_Decode_fill.v:155: syntax error, unexpected \'@\'\n Done_Picture_Decode_O = 1\'b1; @(posedge clock);\n                               ^\n%Error: Exiting due to 9 error(s)\n'
module Picture_Decode (
   resetn,
   clock,

   Start_Picture_Decode_I,
   Done_Picture_Decode_O,

   Data_In_I,
   Shift_1_En_O,
   Shift_8_En_O,
	Shift_Busy_I,
	Byte_Allign_I,
   Start_Code_I,
   Slice_Start_Code_I,
   Start_Code_Upcoming_I,

   Picture_Type_I,
 	Picture_Structure_I,
	Intra_VLC_Format_I,
	Frame_Pred_Frame_DCT_I,
	Concealment_Vectors_I,
	F_Codes_I,
	Intra_DC_Precision_I,
	Quant_Scale_Type_I,
	Alternate_Scan_I,
	Image_Horizontal_I,  
	Image_Vertical_I,
	Load_Seq_Intra_Quant_I,
	Load_Seq_NIntra_Quant_I,
	
   YUV_Data_O,
   YUV_Write_En_O,
   YUV_Start_O,

	Forward_Framestore_Address_O,
	Forward_Framestore_Data_I,
	Forward_Framestore_Busy_I,
	Forward_Framestore_Busy_O,
	Backward_Framestore_Address_O,
	Backward_Framestore_Data_I,
	Backward_Framestore_Busy_I,
	Backward_Framestore_Busy_O

,debug    

);

input [16:0] debug;

input                resetn;
input                clock;

input                Start_Picture_Decode_I;
output reg           Done_Picture_Decode_O;

input    [1:0]       Data_In_I;
output            	Shift_1_En_O;
output reg           Shift_8_En_O;
input						Shift_Busy_I;
input						Byte_Allign_I;
input                Start_Code_I;
input                Slice_Start_Code_I;
input                Start_Code_Upcoming_I;

input 	[1:0]		   Picture_Type_I;
input 	[1:0]		 	Picture_Structure_I;
input 					Intra_VLC_Format_I;
input 					Frame_Pred_Frame_DCT_I;
input 					Concealment_Vectors_I;
input 	[15:0]		F_Codes_I;
input 	[1:0]			Intra_DC_Precision_I;
input 					Quant_Scale_Type_I;
input 					Alternate_Scan_I;
input 	[11:0]		Image_Horizontal_I;  
input 	[11:0]		Image_Vertical_I;
input 					Load_Seq_Intra_Quant_I;
input 					Load_Seq_NIntra_Quant_I;

output   [7:0]       YUV_Data_O;
output               YUV_Write_En_O;
output 					YUV_Start_O;

output	[18:0]		Forward_Framestore_Address_O, Backward_Framestore_Address_O;
input 	[31:0]		Forward_Framestore_Data_I, Backward_Framestore_Data_I;
input 					Forward_Framestore_Busy_I, Backward_Framestore_Busy_I;
output 					Forward_Framestore_Busy_O, Backward_Framestore_Busy_O;

assign YUV_Data_O = 8'h00;
assign YUV_Write_En_O = 1'b0;
assign YUV_Start_O = 1'b0;

assign Forward_Framestore_Address_O = 19'd0;
assign Backward_Framestore_Address_O = 19'd0;

assign Forward_Framestore_Busy_O = 1'b0;
assign Backward_Framestore_Busy_O = 1'b0;

reg active;
always @(posedge clock or negedge resetn) begin
	if (~resetn) active <= 1'b0;
	else if (Start_Picture_Decode_I) active <= 1'b1;
	else active <= 1'b0;
end


`define COUNTER_LIMIT 48500
integer counter;
integer check1;
reg shift_1_reg;

initial begin
	active = 1'b0;
	counter = 0;
	Done_Picture_Decode_O = 1'b1;
	Shift_8_En_O = 1'b0;
	shift_1_reg = 1'b0;
end

always @(posedge active) begin
	Done_Picture_Decode_O = 1'b0; @(posedge clock);
	Shift_8_En_O = 1'b1;
	while (~Slice_Start_Code_I) @(posedge clock);
	Shift_8_En_O = 1'b0; @(posedge clock);
	while (Slice_Start_Code_I) begin
		counter = 0;
		Shift_8_En_O = 1'b1; @(posedge clock); 
		Shift_8_En_O = 1'b0; shift_1_reg = 1'b1; @(posedge clock); 
		while (~Start_Code_I) begin
			counter = counter + 1;
			if (Start_Code_I) shift_1_reg = 1'b0;
			@(posedge clock);
		end
		while (counter < `COUNTER_LIMIT) begin
			counter = counter + 1;
			@(posedge clock);
		end
	end	
	Done_Picture_Decode_O = 1'b1; @(posedge clock);
end

assign Shift_1_En_O = shift_1_reg & ~Start_Code_I;

endmodule
module Picture_Decode (
   resetn,
   clock,

   Start_Picture_Decode_I,
   Done_Picture_Decode_O,

   Data_In_I,
   Shift_1_En_O,
   Shift_8_En_O,
	Shift_Busy_I,
	Byte_Allign_I,
   Start_Code_I,
   Slice_Start_Code_I,
   Start_Code_Upcoming_I,

   Picture_Type_I,
 	Picture_Structure_I,
	Intra_VLC_Format_I,
	Frame_Pred_Frame_DCT_I,
	Concealment_Vectors_I,
	F_Codes_I,
	Intra_DC_Precision_I,
	Quant_Scale_Type_I,
	Alternate_Scan_I,
	Image_Horizontal_I,  
	Image_Vertical_I,
	Load_Seq_Intra_Quant_I,
	Load_Seq_NIntra_Quant_I,
	
   YUV_Data_O,
   YUV_Write_En_O,
   YUV_Start_O,

	Forward_Framestore_Address_O,
	Forward_Framestore_Data_I,
	Forward_Framestore_Busy_I,
	Forward_Framestore_Busy_O,
	Backward_Framestore_Address_O,
	Backward_Framestore_Data_I,
	Backward_Framestore_Busy_I,
	Backward_Framestore_Busy_O

,debug    

);


input [16:0] debug;

input                resetn;
input                clock;

input                Start_Picture_Decode_I;
output reg           Done_Picture_Decode_O;

input    [1:0]       Data_In_I;
output            	Shift_1_En_O;
output reg           Shift_8_En_O;
input						Shift_Busy_I;
input						Byte_Allign_I;
input                Start_Code_I;
input                Slice_Start_Code_I;
input                Start_Code_Upcoming_I;

input 	[1:0]		   Picture_Type_I;
input 	[1:0]		 	Picture_Structure_I;
input 					Intra_VLC_Format_I;
input 					Frame_Pred_Frame_DCT_I;
input 					Concealment_Vectors_I;
input 	[15:0]		F_Codes_I;
input 	[1:0]			Intra_DC_Precision_I;
input 					Quant_Scale_Type_I;
input 					Alternate_Scan_I;
input 	[11:0]		Image_Horizontal_I;  
input 	[11:0]		Image_Vertical_I;
input 					Load_Seq_Intra_Quant_I;
input 					Load_Seq_NIntra_Quant_I;

output   [7:0]       YUV_Data_O;
output               YUV_Write_En_O;
output 					YUV_Start_O;

output	[18:0]		Forward_Framestore_Address_O, Backward_Framestore_Address_O;
input 	[31:0]		Forward_Framestore_Data_I, Backward_Framestore_Data_I;
input 					Forward_Framestore_Busy_I, Backward_Framestore_Busy_I;
output 					Forward_Framestore_Busy_O, Backward_Framestore_Busy_O;

assign YUV_Data_O = 8'h00;
assign YUV_Write_En_O = 1'b0;
assign YUV_Start_O = 1'b0;

assign Forward_Framestore_Address_O = 19'd0;
assign Backward_Framestore_Address_O = 19'd0;

assign Forward_Framestore_Busy_O = 1'b0;
assign Backward_Framestore_Busy_O = 1'b0;

reg active;
always @(posedge clock or negedge resetn) begin
	if (~resetn) active <= 1'b0;
	else if (Start_Picture_Decode_I) active <= 1'b1;
	else active <= 1'b0;
end


`define COUNTER_LIMIT 48500
integer counter;
integer check1;
reg shift_1_reg;

initial begin
	active = 1'b0;
	counter = 0;
	Done_Picture_Decode_O = 1'b1;
	Shift_8_En_O = 1'b0;
	shift_1_reg = 1'b0;
end

always @(posedge active) begin
	Done_Picture_Decode_O = 1'b0; @(posedge clock);
	Shift_8_En_O = 1'b1;
	while (~Slice_Start_Code_I) @(posedge clock);
	Shift_8_En_O = 1'b0; @(posedge clock);
	while (Slice_Start_Code_I) begin
		counter = 0;
		Shift_8_En_O = 1'b1; @(posedge clock); 
		Shift_8_En_O = 1'b0; shift_1_reg = 1'b1; @(posedge clock); 
		while (~Start_Code_I) begin
			counter = counter + 1;
			if (Start_Code_I) shift_1_reg = 1'b0;
			@(posedge clock);
		end
		while (counter < `COUNTER_LIMIT) begin
			counter = counter + 1;
			@(posedge clock);
		end
	end	
	Done_Picture_Decode_O = 1'b1; @(posedge clock);
end

assign Shift_1_En_O = shift_1_reg & ~Start_Code_I;

endmodule