data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 a[0] = !a[0];\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 a[1] = !a[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:25: Unsupported: Ignoring delay on this delayed statement.\n #4 a[2] = !a[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:28: Unsupported: Ignoring delay on this delayed statement.\n #8 a[3] = !a[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:31: Unsupported: Ignoring delay on this delayed statement.\n #16 a[4] = !a[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:34: Unsupported: Ignoring delay on this delayed statement.\n #32 a[5] = !a[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:37: Unsupported: Ignoring delay on this delayed statement.\n #64 a[6] = !a[6];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:40: Unsupported: Ignoring delay on this delayed statement.\n #128 a[7] = !a[7];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:43: Unsupported: Ignoring delay on this delayed statement.\n #256 rr = !rr;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #520;\n  ^\n%Error: data/full_repos/permissive/472097485/Chu03/Barrel_01/TestRorL.v:16: Cannot find file containing module: \'RorL\'\n RorL uut ( a, rr, r );\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu03/Barrel_01,data/full_repos/permissive/472097485/RorL\n             data/full_repos/permissive/472097485/Chu03/Barrel_01,data/full_repos/permissive/472097485/RorL.v\n             data/full_repos/permissive/472097485/Chu03/Barrel_01,data/full_repos/permissive/472097485/RorL.sv\n             RorL\n             RorL.v\n             RorL.sv\n             obj_dir/RorL\n             obj_dir/RorL.v\n             obj_dir/RorL.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestRorL;


	reg [7:0] a;
	reg rr;


	wire [7:0] r;


	RorL uut ( a, rr, r );

	always begin
	#1 a[0] = !a[0];
	end
	always begin
	#2 a[1] = !a[1];
	end
	always begin
	#4 a[2] = !a[2];
	end
	always begin
	#8 a[3] = !a[3];
	end
	always begin
	#16 a[4] = !a[4];
	end
	always begin
	#32 a[5] = !a[5];
	end
	always begin
	#64 a[6] = !a[6];
	end
	always begin
	#128 a[7] = !a[7];
	end
	always begin
	#256 rr = !rr;
	end

	initial begin

		a = 8'b0;
		rr = 0;


		#520;
        

		$stop;
	end
      
endmodule
module TestRorL;



	reg [7:0] a;
	reg rr;


	wire [7:0] r;


	RorL uut ( a, rr, r );

	always begin
	#1 a[0] = !a[0];
	end
	always begin
	#2 a[1] = !a[1];
	end
	always begin
	#4 a[2] = !a[2];
	end
	always begin
	#8 a[3] = !a[3];
	end
	always begin
	#16 a[4] = !a[4];
	end
	always begin
	#32 a[5] = !a[5];
	end
	always begin
	#64 a[6] = !a[6];
	end
	always begin
	#128 a[7] = !a[7];
	end
	always begin
	#256 rr = !rr;
	end

	initial begin

		a = 8'b0;
		rr = 0;


		#520;
        

		$stop;
	end
      
endmodule