data/full_repos/permissive/485839274/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #100;        \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:59: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/485839274/test.v:91: Unsupported: Ignoring delay on this delayed statement.\n   always #10 CLK = ~CLK;    \n          ^\n%Error: data/full_repos/permissive/485839274/test.v:18: Cannot find file containing module: \'FIFO\'\nFIFO uut(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/485839274,data/full_repos/permissive/485839274/FIFO\n             data/full_repos/permissive/485839274,data/full_repos/permissive/485839274/FIFO.v\n             data/full_repos/permissive/485839274,data/full_repos/permissive/485839274/FIFO.sv\n             FIFO\n             FIFO.v\n             FIFO.sv\n             obj_dir/FIFO\n             obj_dir/FIFO.v\n             obj_dir/FIFO.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;



 reg CLK;
 reg RST;
 reg [7:0]DATA_INPUT;
 reg BTN_WRITE;
 reg BTN_READ;
 wire [7:0]DATA_OUT;
 wire EMPTY;
 wire FULL;



FIFO uut(
.CLK(CLK),
.RST(RST),
.DATA_INPUT(DATA_INPUT),
.BTN_WRITE(BTN_WRITE),
.BTN_READ(BTN_READ),
.DATA_OUT(DATA_OUT),
.EMPTY(EMPTY),
.FULL(FULL)
);

 initial begin



  CLK  = 1'b0;
  DATA_INPUT  = 8'b00000000;
  BTN_READ  = 1'b0;
  BTN_WRITE  = 1'b0;
  RST  = 1'b1;



  #100;        


  RST  = 1'b1;

  #20;
  RST  = 1'b0;
  BTN_WRITE  = 1'b1;
  DATA_INPUT  = 8'b00000001;

  #20;
   BTN_WRITE = 1'b0;
	#20;
 
  DATA_INPUT  = 8'b00000010;
  BTN_WRITE = 1'b1;
   #20;
  BTN_WRITE = 1'b0;
	#20;
  DATA_INPUT  = 8'b00000100;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  DATA_INPUT  = 8'b00001000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  BTN_READ = 1'b1;
  #20;
  BTN_READ = 1'b0;
  #20;
  BTN_READ = 1'b1;
  #20;
  BTN_READ = 1'b0;
  #20;
  DATA_INPUT  = 8'b00010000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  DATA_INPUT  = 8'b00100000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  $stop;
 end 

   always #10 CLK = ~CLK;    

endmodule
module test;




 reg CLK;
 reg RST;
 reg [7:0]DATA_INPUT;
 reg BTN_WRITE;
 reg BTN_READ;
 wire [7:0]DATA_OUT;
 wire EMPTY;
 wire FULL;



FIFO uut(
.CLK(CLK),
.RST(RST),
.DATA_INPUT(DATA_INPUT),
.BTN_WRITE(BTN_WRITE),
.BTN_READ(BTN_READ),
.DATA_OUT(DATA_OUT),
.EMPTY(EMPTY),
.FULL(FULL)
);

 initial begin



  CLK  = 1'b0;
  DATA_INPUT  = 8'b00000000;
  BTN_READ  = 1'b0;
  BTN_WRITE  = 1'b0;
  RST  = 1'b1;



  #100;        


  RST  = 1'b1;

  #20;
  RST  = 1'b0;
  BTN_WRITE  = 1'b1;
  DATA_INPUT  = 8'b00000001;

  #20;
   BTN_WRITE = 1'b0;
	#20;
 
  DATA_INPUT  = 8'b00000010;
  BTN_WRITE = 1'b1;
   #20;
  BTN_WRITE = 1'b0;
	#20;
  DATA_INPUT  = 8'b00000100;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  DATA_INPUT  = 8'b00001000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  BTN_READ = 1'b1;
  #20;
  BTN_READ = 1'b0;
  #20;
  BTN_READ = 1'b1;
  #20;
  BTN_READ = 1'b0;
  #20;
  DATA_INPUT  = 8'b00010000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  DATA_INPUT  = 8'b00100000;
  BTN_WRITE = 1'b1;
  #20;
  BTN_WRITE = 1'b0;
  #20;
  $stop;
 end 

   always #10 CLK = ~CLK;    

endmodule