data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv
1: b"%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:17: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport ariane_pkg::*;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:32: syntax error, unexpected ::, expecting ')' or ','\n    output riscv::pte_t             lu_content_o,\n                ^~\n                                                                                : ... Perhaps 'riscv' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:34: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                    lu_is_1G_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:35: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                    lu_hit_o\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:49: syntax error, unexpected IDENTIFIER\n    riscv::pte_t [TLB_ENTRIES-1:0] content_q, content_n;\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:56: syntax error, unexpected always_comb\n    always_comb begin : translation\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:68: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:99: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:129: syntax error, unexpected always_comb\n    always_comb begin : plru_replacement\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:154: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:157: syntax error, unexpected if\n            if (lu_hit[i] & lu_access_i) begin\n            ^~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:159: syntax error, unexpected IDENTIFIER\n                for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin\n                                           ^~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:183: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i += 1) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:186: syntax error, unexpected IDENTIFIER\n            en = 1'b1;\n            ^~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/tlb.sv:187: syntax error, unexpected IDENTIFIER\n            for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin\n                                       ^~~\n%Error: Exiting due to 15 error(s)\n"
function int countSetBits(logic[TLB_ENTRIES-1:0] vector);
      automatic int count = 0;
      foreach (vector[idx]) begin
        count += vector[idx];
      end
      return count;
    endfunction
function int countSetBits(logic[TLB_ENTRIES-1:0] vector);

      automatic int count = 0;
      foreach (vector[idx]) begin
        count += vector[idx];
      end
      return count;
    endfunction