data/full_repos/permissive/458113953/LAB 7&8_2019A8PS0621H/Simulation and Constraints/Digital_Lock_Test.v
1: b'%Error: Cannot find file containing module: 7&8_2019A8PS0621H/Simulation\n        ... Looked in:\n             data/full_repos/permissive/458113953/LAB/7&8_2019A8PS0621H/Simulation\n             data/full_repos/permissive/458113953/LAB/7&8_2019A8PS0621H/Simulation.v\n             data/full_repos/permissive/458113953/LAB/7&8_2019A8PS0621H/Simulation.sv\n             7&8_2019A8PS0621H/Simulation\n             7&8_2019A8PS0621H/Simulation.v\n             7&8_2019A8PS0621H/Simulation.sv\n             obj_dir/7&8_2019A8PS0621H/Simulation\n             obj_dir/7&8_2019A8PS0621H/Simulation.v\n             obj_dir/7&8_2019A8PS0621H/Simulation.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Constraints,data/full_repos/permissive/458113953\n%Error: Cannot find file containing module: data/full_repos/permissive/458113953/LAB\n%Error: Cannot find file containing module: Constraints/Digital_Lock_Test.v\n%Error: Exiting due to 5 error(s)\n'
module Digital_Lock_Test(

    );
    reg mClk,Reset,B0,B1;
    wire correct,incorrect;
    digital_lock t1(mClk, Reset,B0,B1, correct, incorrect);
    initial begin
    Reset=1'b1;
    #9
    Reset=1'b0;
    end
    initial begin
    mClk=1'b0;
    repeat(32)
    #5
    mClk=~mClk;
    $finish;
    end
    initial begin
    #40
    B0=0;
    B1=1;
    #30
    B0=1;
    B1=0;
    end
endmodule
module Digital_Lock_Test(

    );

    reg mClk,Reset,B0,B1;
    wire correct,incorrect;
    digital_lock t1(mClk, Reset,B0,B1, correct, incorrect);
    initial begin
    Reset=1'b1;
    #9
    Reset=1'b0;
    end
    initial begin
    mClk=1'b0;
    repeat(32)
    #5
    mClk=~mClk;
    $finish;
    end
    initial begin
    #40
    B0=0;
    B1=1;
    #30
    B0=1;
    B1=0;
    end
endmodule