data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv
1: b"%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv:125: syntax error, unexpected ::, expecting ';'\n    localparam dm::hartinfo_t DebugHartInfo = '{\n                 ^~\n                                                                                        : ... Perhaps 'dm' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv:151: syntax error, unexpected ::, expecting ';'\n    localparam logic [63:0] SMODE_STATUS_READ_MASK = riscv::SSTATUS_UIE\n                                                          ^~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv:164: syntax error, unexpected ::, expecting ';'\n    localparam logic [63:0] SMODE_STATUS_WRITE_MASK = riscv::SSTATUS_SIE\n                                                           ^~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv:523: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n        riscv::pte_t           content;\n        ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/ariane_pkg.sv:711: syntax error, unexpected endpackage\nendpackage\n^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
function automatic logic [1:0] extract_transfer_size(fu_op op);
        case (op)
            LD, SD, FLD, FSD,
            AMO_LRD,   AMO_SCD,
            AMO_SWAPD, AMO_ADDD,
            AMO_ANDD,  AMO_ORD,
            AMO_XORD,  AMO_MAXD,
            AMO_MAXDU, AMO_MIND,
            AMO_MINDU: begin
                return 2'b11;
            end
            LW, LWU, SW, FLW, FSW,
            AMO_LRW,   AMO_SCW,
            AMO_SWAPW, AMO_ADDW,
            AMO_ANDW,  AMO_ORW,
            AMO_XORW,  AMO_MAXW,
            AMO_MAXWU, AMO_MINW,
            AMO_MINWU: begin
                return 2'b10;
            end
            LH, LHU, SH, FLH, FSH: return 2'b01;
            LB, LBU, SB, FLB, FSB: return 2'b00;
            default:     return 2'b11;
        endcase
    endfunction
function automatic logic [1:0] extract_transfer_size(fu_op op);

        case (op)
            LD, SD, FLD, FSD,
            AMO_LRD,   AMO_SCD,
            AMO_SWAPD, AMO_ADDD,
            AMO_ANDD,  AMO_ORD,
            AMO_XORD,  AMO_MAXD,
            AMO_MAXDU, AMO_MIND,
            AMO_MINDU: begin
                return 2'b11;
            end
            LW, LWU, SW, FLW, FSW,
            AMO_LRW,   AMO_SCW,
            AMO_SWAPW, AMO_ADDW,
            AMO_ANDW,  AMO_ORW,
            AMO_XORW,  AMO_MAXW,
            AMO_MAXWU, AMO_MINW,
            AMO_MINWU: begin
                return 2'b10;
            end
            LH, LHU, SH, FLH, FSH: return 2'b01;
            LB, LBU, SB, FLB, FSB: return 2'b00;
            default:     return 2'b11;
        endcase
    endfunction