data/full_repos/permissive/447283927/main_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447283927/main_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #1 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447283927/main_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #170\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447283927/main_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447283927/main_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/447283927/main_test.v:14: Cannot find file containing module: \'main\'\nmain UUT(rst, clk, alu_z, Anode_Activate, LED_out, BTN_in, interrupt);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/main\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/main.v\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;

reg rst, clk;
wire alu_z;
wire [7:0] Anode_Activate;	
wire  [6:0] LED_out;	
reg [15:0] BTN_in;
reg interrupt;



main UUT(rst, clk, alu_z, Anode_Activate, LED_out, BTN_in, interrupt);

    always begin
        clk = 0;
        forever #1 clk = ~clk;
    end
    
    initial begin
        rst = 0;
        interrupt = 0;
        BTN_in[7:0] = 25;
        BTN_in[15:8] = 10;
        #170
        interrupt = 1;
        #2
        interrupt = 0;
        #10
        
    
    $finish;  
    end

endmodule
module main_test;


reg rst, clk;
wire alu_z;
wire [7:0] Anode_Activate;	
wire  [6:0] LED_out;	
reg [15:0] BTN_in;
reg interrupt;



main UUT(rst, clk, alu_z, Anode_Activate, LED_out, BTN_in, interrupt);

    always begin
        clk = 0;
        forever #1 clk = ~clk;
    end
    
    initial begin
        rst = 0;
        interrupt = 0;
        BTN_in[7:0] = 25;
        BTN_in[15:8] = 10;
        #170
        interrupt = 1;
        #2
        interrupt = 0;
        #10
        
    
    $finish;  
    end

endmodule