data/full_repos/permissive/469804105/RTL/Project_files/down_Counter.v
data/verilator_xmls/392b4f92-f4ab-411d-b23f-524006eff6af.xml
module down_Counter(
i_clk , clr_n , ld_cnt , counter 
    );
input i_clk ;
input clr_n ;
input ld_cnt ;
output  [2:0] counter ;

reg[2:0] count_out ;


always@(posedge i_clk)
 begin
  if(clr_n == 1'b1)
      count_out <= count_out;
      else if(ld_cnt==1'b1)
       count_out <= count_out-1'b1; 
       else
       count_out <= 3'b100;
       end    
   assign counter = count_out ;    
endmodule
module down_Counter(
i_clk , clr_n , ld_cnt , counter 
    );

input i_clk ;
input clr_n ;
input ld_cnt ;
output  [2:0] counter ;

reg[2:0] count_out ;


always@(posedge i_clk)
 begin
  if(clr_n == 1'b1)
      count_out <= count_out;
      else if(ld_cnt==1'b1)
       count_out <= count_out-1'b1; 
       else
       count_out <= 3'b100;
       end    
   assign counter = count_out ;    
endmodule