data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_bht_pre_array.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_bht_pre_array.v:64: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_bht_pre_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_bht_pre_array.v:86: Cannot find file containing module: 'ct_spsram_1024x64'\nct_spsram_1024x64  x_ct_spsram_1024x64 (\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ct_ifu_bht_pre_array(
  bht_pre_array_clk_en,
  bht_pre_data_out,
  bht_pred_array_cen_b,
  bht_pred_array_din,
  bht_pred_array_gwen,
  bht_pred_array_index,
  bht_pred_bwen,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);


input           bht_pre_array_clk_en; 
input           bht_pred_array_cen_b; 
input   [63:0]  bht_pred_array_din;  
input           bht_pred_array_gwen; 
input   [9 :0]  bht_pred_array_index; 
input   [63:0]  bht_pred_bwen;       
input           cp0_ifu_icg_en;      
input           cp0_yy_clk_en;       
input           forever_cpuclk;      
input           pad_yy_icg_scan_en;  
output  [63:0]  bht_pre_data_out;    




wire            bht_pre_array_clk_en; 
wire            bht_pre_clk;         
wire    [63:0]  bht_pre_data_out;    
wire            bht_pre_en;          
wire            bht_pred_array_cen_b; 
wire    [63:0]  bht_pred_array_din;  
wire            bht_pred_array_gwen; 
wire    [9 :0]  bht_pred_array_index; 
wire    [63:0]  bht_pred_bwen;       
wire            cp0_ifu_icg_en;      
wire            cp0_yy_clk_en;       
wire            forever_cpuclk;      
wire            pad_yy_icg_scan_en;  




gated_clk_cell  x_bht_pre_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (bht_pre_clk       ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (bht_pre_en        ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









assign bht_pre_en = bht_pre_array_clk_en;



ct_spsram_1024x64  x_ct_spsram_1024x64 (
  .A                    (bht_pred_array_index),
  .CEN                  (bht_pred_array_cen_b),
  .CLK                  (bht_pre_clk         ),
  .D                    (bht_pred_array_din  ),
  .GWEN                 (bht_pred_array_gwen ),
  .Q                    (bht_pre_data_out    ),
  .WEN                  (bht_pred_bwen       )
);












endmodule
module ct_ifu_bht_pre_array(
  bht_pre_array_clk_en,
  bht_pre_data_out,
  bht_pred_array_cen_b,
  bht_pred_array_din,
  bht_pred_array_gwen,
  bht_pred_array_index,
  bht_pred_bwen,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);



input           bht_pre_array_clk_en; 
input           bht_pred_array_cen_b; 
input   [63:0]  bht_pred_array_din;  
input           bht_pred_array_gwen; 
input   [9 :0]  bht_pred_array_index; 
input   [63:0]  bht_pred_bwen;       
input           cp0_ifu_icg_en;      
input           cp0_yy_clk_en;       
input           forever_cpuclk;      
input           pad_yy_icg_scan_en;  
output  [63:0]  bht_pre_data_out;    




wire            bht_pre_array_clk_en; 
wire            bht_pre_clk;         
wire    [63:0]  bht_pre_data_out;    
wire            bht_pre_en;          
wire            bht_pred_array_cen_b; 
wire    [63:0]  bht_pred_array_din;  
wire            bht_pred_array_gwen; 
wire    [9 :0]  bht_pred_array_index; 
wire    [63:0]  bht_pred_bwen;       
wire            cp0_ifu_icg_en;      
wire            cp0_yy_clk_en;       
wire            forever_cpuclk;      
wire            pad_yy_icg_scan_en;  




gated_clk_cell  x_bht_pre_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (bht_pre_clk       ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (bht_pre_en        ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









assign bht_pre_en = bht_pre_array_clk_en;



ct_spsram_1024x64  x_ct_spsram_1024x64 (
  .A                    (bht_pred_array_index),
  .CEN                  (bht_pred_array_cen_b),
  .CLK                  (bht_pre_clk         ),
  .D                    (bht_pred_array_din  ),
  .GWEN                 (bht_pred_array_gwen ),
  .Q                    (bht_pre_data_out    ),
  .WEN                  (bht_pred_bwen       )
);












endmodule