data/full_repos/permissive/42434302/ivltests/pr2305307b.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:2: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n  reg passed, in, expect;\n                  ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:2: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n  reg passed, in, expect;\n                        ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:5: syntax error, unexpected rand, expecting IDENTIFIER or do or final\n  wire rand = &in;\n       ^~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n        0: {in,expect} = 2\'b00;\n               ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:17: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        0: {in,expect} = 2\'b00;\n                     ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n        1: {in,expect} = 2\'b11;\n               ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:18: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        1: {in,expect} = 2\'b11;\n                     ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:19: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n        2: {in,expect} = 2\'bzx;\n               ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:19: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        2: {in,expect} = 2\'bzx;\n                     ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n        3: {in,expect} = 2\'bxx;\n               ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:20: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        3: {in,expect} = 2\'bxx;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:26: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\n      if (rand !== expect) begin\n          ^~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (rand !== expect) begin\n                   ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:28: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, expect, rand);\n                     ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (ror !== expect) begin\n                  ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (ror !== expect) begin\n                        ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, expect, ror);\n                     ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (rxor !== expect) begin\n                   ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:38: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (rxor !== expect) begin\n                         ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, expect, rxor);\n                     ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:45: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (rnand !== ~expect) begin\n                     ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:47: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, ~expect, rnand);\n                      ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:51: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (rnor !== ~expect) begin\n                    ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:53: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, ~expect, rnor);\n                      ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n      if (rxnor !== ~expect) begin\n                     ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2305307b.v:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                 in, ~expect, rxnor);\n                      ^~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed, in, expect;
  integer lp;

  wire rand = &in;
  wire ror = |in;
  wire rxor = ^in;
  wire rnand = ~&in;
  wire rnor = ~|in;
  wire rxnor = ~^in;

  initial begin
    passed = 1'b1;

    for (lp=0; lp < 3 ; lp = lp + 1) begin
      case (lp)
        0: {in,expect} = 2'b00;
        1: {in,expect} = 2'b11;
        2: {in,expect} = 2'bzx;
        3: {in,expect} = 2'bxx;
      endcase

      #1;


      if (rand !== expect) begin
        $display("FAILED CA reduction & with input %b, expected %b, got %b",
                 in, expect, rand);
        passed = 1'b0;
      end

      if (ror !== expect) begin
        $display("FAILED CA reduction | with input %b, expected %b, got %b",
                 in, expect, ror);
        passed = 1'b0;
      end

      if (rxor !== expect) begin
        $display("FAILED CA reduction ^ with input %b, expected %b, got %b",
                 in, expect, rxor);
        passed = 1'b0;
      end


      if (rnand !== ~expect) begin
        $display("FAILED CA reduction ~& with input %b, expected %b, got %b",
                 in, ~expect, rnand);
        passed = 1'b0;
      end

      if (rnor !== ~expect) begin
        $display("FAILED CA reduction ~| with input %b, expected %b, got %b",
                 in, ~expect, rnor);
        passed = 1'b0;
      end

      if (rxnor !== ~expect) begin
        $display("FAILED CA reduction ~^ with input %b, expected %b, got %b",
                 in, ~expect, rxnor);
        passed = 1'b0;
      end
    end

    if (passed) $display("PASSED");
  end
endmodule
module top;

  reg passed, in, expect;
  integer lp;

  wire rand = &in;
  wire ror = |in;
  wire rxor = ^in;
  wire rnand = ~&in;
  wire rnor = ~|in;
  wire rxnor = ~^in;

  initial begin
    passed = 1'b1;

    for (lp=0; lp < 3 ; lp = lp + 1) begin
      case (lp)
        0: {in,expect} = 2'b00;
        1: {in,expect} = 2'b11;
        2: {in,expect} = 2'bzx;
        3: {in,expect} = 2'bxx;
      endcase

      #1;


      if (rand !== expect) begin
        $display("FAILED CA reduction & with input %b, expected %b, got %b",
                 in, expect, rand);
        passed = 1'b0;
      end

      if (ror !== expect) begin
        $display("FAILED CA reduction | with input %b, expected %b, got %b",
                 in, expect, ror);
        passed = 1'b0;
      end

      if (rxor !== expect) begin
        $display("FAILED CA reduction ^ with input %b, expected %b, got %b",
                 in, expect, rxor);
        passed = 1'b0;
      end


      if (rnand !== ~expect) begin
        $display("FAILED CA reduction ~& with input %b, expected %b, got %b",
                 in, ~expect, rnand);
        passed = 1'b0;
      end

      if (rnor !== ~expect) begin
        $display("FAILED CA reduction ~| with input %b, expected %b, got %b",
                 in, ~expect, rnor);
        passed = 1'b0;
      end

      if (rxnor !== ~expect) begin
        $display("FAILED CA reduction ~^ with input %b, expected %b, got %b",
                 in, ~expect, rxnor);
        passed = 1'b0;
      end
    end

    if (passed) $display("PASSED");
  end
endmodule