data/full_repos/permissive/468612001/Week02/multiplexer3/multiplexer3.v
data/verilator_xmls/277b2ca6-8a2c-4258-920d-c16fcb5cca5f.xml
module multiplexer3(a, b, sel, out);
	input a, b, sel;
	output out;
	wire out1, out2, nsel;
	
	and g1(out1, a, nsel), g2(out2, b, sel);
	or  g3(out, out1, out2);
	not g4(nsel, sel);
	
endmodule
module multiplexer3(a, b, sel, out);

	input a, b, sel;
	output out;
	wire out1, out2, nsel;
	
	and g1(out1, a, nsel), g2(out2, b, sel);
	or  g3(out, out1, out2);
	not g4(nsel, sel);
	
endmodule