data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:47: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign {CA, CB, CC, CD, CE, CF, CG, DP} = { SSD_CATHODES, 1\'b1};\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:63: Cannot find file containing module: \'m_port_ultra\'\n m_port_ultra portableUltrasoundFSM (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/45440421/Implementation/Modelsim,data/full_repos/permissive/45440421/m_port_ultra\n             data/full_repos/permissive/45440421/Implementation/Modelsim,data/full_repos/permissive/45440421/m_port_ultra.v\n             data/full_repos/permissive/45440421/Implementation/Modelsim,data/full_repos/permissive/45440421/m_port_ultra.sv\n             m_port_ultra\n             m_port_ultra.v\n             m_port_ultra.sv\n             obj_dir/m_port_ultra\n             obj_dir/m_port_ultra.v\n             obj_dir/m_port_ultra.sv\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:77: Operator DIV expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'convexSetSize\' generates 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD4 = (convexSetSize / 10000);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:77: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD4 = (convexSetSize / 10000);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:78: Operator MODDIV expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'convexSetSize\' generates 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:78: Operator MODDIV expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'convexSetSize\' generates 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:78: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:79: Operator MODDIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'convexSetSize\' generates 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:79: Operator MODDIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'convexSetSize\' generates 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:79: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 10 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:80: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD1 = (((convexSetSize % 100) - (convexSetSize % 10)) / 10);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:81: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                                 : ... In instance m_port_ultra_top\n assign BCD0 = (((convexSetSize % 10) - (convexSetSize % 1)) / 1);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:119: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD0\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b000: SSD = SSD0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:120: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD1\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b001: SSD = SSD1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:121: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD2\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b010: SSD = SSD2;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:122: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD3\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b011: SSD = SSD3;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:123: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD4\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b100: SSD = SSD4;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:124: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD5\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b101: SSD = SSD5;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:125: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD6\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b110: SSD = SSD6;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:126: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'SSD7\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n            3\'b111: SSD = SSD7;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:132: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h8\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1010: SSD_CATHODES = 7\'b0001000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:133: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h60\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1011: SSD_CATHODES = 7\'b1100000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h31\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1100: SSD_CATHODES = 7\'b0110001 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:135: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h42\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1101: SSD_CATHODES = 7\'b1000010 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:136: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h30\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1110: SSD_CATHODES = 7\'b0110000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:137: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h38\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1111: SSD_CATHODES = 7\'b0111000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:138: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h1\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0000: SSD_CATHODES = 7\'b0000001 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:139: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4f\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0001: SSD_CATHODES = 7\'b1001111 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:140: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h12\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0010: SSD_CATHODES = 7\'b0010010 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:141: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0011: SSD_CATHODES = 7\'b0000110 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:142: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4c\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0100: SSD_CATHODES = 7\'b1001100 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:143: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h24\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0101: SSD_CATHODES = 7\'b0100100 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:144: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h20\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0110: SSD_CATHODES = 7\'b0100000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:145: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'hf\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b0111: SSD_CATHODES = 7\'b0001111 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:146: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1000: SSD_CATHODES = 7\'b0000000 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:147: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'hc\' generates 7 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n   4\'b1001: SSD_CATHODES = 7\'b0001100 ;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Modelsim/m_port_ultra_top.v:131: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                                  : ... In instance m_port_ultra_top\n  case (SSD)\n  ^~~~\n%Error: Exiting due to 1 error(s), 51 warning(s)\n'
module m_port_ultra_top (
	input CLK100MHZ,
	input [15:0] SW,
	input BTNC, BTNU, BTND, BTNL, BTNR,
	input CPU_RESETN,
	output [15:0] LED,
	output CA, output CB, output CC, output CD, output CE, output CF, output CG, output DP,
	output [7:0] AN
);


	wire [4095:0] convexPoints;
	wire [7:0] convexSetSize;
	

	reg [4:0] SSD;
	reg [7:0] SSD_CATHODES;
	reg [3:0] count;
	wire [31:0] outputResult;
	reg scan_ca;
	
	assign AN[0] = scan_ca;


	assign {CA, CB, CC, CD, CE, CF, CG, DP} = { SSD_CATHODES, 1'b1};
	

	reg [26:0] DIV_CLK;

	always @(posedge CLK100MHZ, negedge CPU_RESETN) begin							
		if (!CPU_RESETN) begin
			DIV_CLK <= 0;
		end
		
		else begin
			DIV_CLK <= DIV_CLK + 1'b1;
		end
	end
	

	m_port_ultra portableUltrasoundFSM (
		.clk (CLK100MHZ),
		.slowClk (DIV_CLK[25:24]),
		.reset_n (CPU_RESETN),
		.ack (BTNC),
		.shiftRight (BTNR),
		.shiftLeft (BTNL),
		.convexPoints (convexPoints),
		.convexSetSize (convexSetSize)
	);
	

	wire [3:0] BCD0, BCD1, BCD2, BCD3, BCD4;
	
	assign BCD4 = (convexSetSize / 10000);
	assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);
	assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);
	assign BCD1 = (((convexSetSize % 100) - (convexSetSize % 10)) / 10);
	assign BCD0 = (((convexSetSize % 10) - (convexSetSize % 1)) / 1);


	assign outputResult [31:28] = 4'b0000;
	assign outputResult [27:24] = 4'b0000;
	assign outputResult [23:20] = 4'b0000;
	assign outputResult [19:16] = BCD4;
	assign outputResult [15:12] = BCD3;
	assign outputResult [11:8] = BCD2;
	assign outputResult [7:4] = BCD1;
	assign outputResult [3:0] = BCD0;
	

	wire[2:0] ssdscan_clk;
	assign ssdscan_clk = DIV_CLK[19:17];
	assign AN[0] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[1] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[2] = !( (~(ssdscan_clk[2])) &&  (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[3] = !( (~(ssdscan_clk[2])) &&  (ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[4] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[5] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[6] = !( ( (ssdscan_clk[2])) &&  (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[7] = !( ( (ssdscan_clk[2])) &&  (ssdscan_clk[1]) &&  (ssdscan_clk[0]) );

    wire[3:0] SSD7, SSD6, SSD5, SSD4, SSD3, SSD2, SSD1, SSD0;
    
	assign SSD7 = outputResult[31:28];
	assign SSD6 = outputResult[27:24];
	assign SSD5 = outputResult[23:20];
	assign SSD4 = outputResult[19:16];
	assign SSD3 = outputResult[15:12];
	assign SSD2 = outputResult[11:8];
	assign SSD1 = outputResult[7:4];
	assign SSD0 = outputResult[3:0];
	
	always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3, SSD4, SSD5, SSD6, SSD7)
	begin : SSD_SCAN_OUT
		case (ssdscan_clk) 
            3'b000: SSD = SSD0;
            3'b001: SSD = SSD1;
            3'b010: SSD = SSD2;
            3'b011: SSD = SSD3;
            3'b100: SSD = SSD4;
            3'b101: SSD = SSD5;
            3'b110: SSD = SSD6;
            3'b111: SSD = SSD7;
		endcase 
	end

	always @ (SSD) begin
		case (SSD)
			4'b1010: SSD_CATHODES = 7'b0001000 ;
			4'b1011: SSD_CATHODES = 7'b1100000 ;
			4'b1100: SSD_CATHODES = 7'b0110001 ;
			4'b1101: SSD_CATHODES = 7'b1000010 ;
			4'b1110: SSD_CATHODES = 7'b0110000 ;
			4'b1111: SSD_CATHODES = 7'b0111000 ;
			4'b0000: SSD_CATHODES = 7'b0000001 ;
			4'b0001: SSD_CATHODES = 7'b1001111 ;
			4'b0010: SSD_CATHODES = 7'b0010010 ;
			4'b0011: SSD_CATHODES = 7'b0000110 ;
			4'b0100: SSD_CATHODES = 7'b1001100 ;
			4'b0101: SSD_CATHODES = 7'b0100100 ;
			4'b0110: SSD_CATHODES = 7'b0100000 ;
			4'b0111: SSD_CATHODES = 7'b0001111 ;
			4'b1000: SSD_CATHODES = 7'b0000000 ;
			4'b1001: SSD_CATHODES = 7'b0001100 ;
		endcase
	end	
	
endmodule
module m_port_ultra_top (
	input CLK100MHZ,
	input [15:0] SW,
	input BTNC, BTNU, BTND, BTNL, BTNR,
	input CPU_RESETN,
	output [15:0] LED,
	output CA, output CB, output CC, output CD, output CE, output CF, output CG, output DP,
	output [7:0] AN
);



	wire [4095:0] convexPoints;
	wire [7:0] convexSetSize;
	

	reg [4:0] SSD;
	reg [7:0] SSD_CATHODES;
	reg [3:0] count;
	wire [31:0] outputResult;
	reg scan_ca;
	
	assign AN[0] = scan_ca;


	assign {CA, CB, CC, CD, CE, CF, CG, DP} = { SSD_CATHODES, 1'b1};
	

	reg [26:0] DIV_CLK;

	always @(posedge CLK100MHZ, negedge CPU_RESETN) begin							
		if (!CPU_RESETN) begin
			DIV_CLK <= 0;
		end
		
		else begin
			DIV_CLK <= DIV_CLK + 1'b1;
		end
	end
	

	m_port_ultra portableUltrasoundFSM (
		.clk (CLK100MHZ),
		.slowClk (DIV_CLK[25:24]),
		.reset_n (CPU_RESETN),
		.ack (BTNC),
		.shiftRight (BTNR),
		.shiftLeft (BTNL),
		.convexPoints (convexPoints),
		.convexSetSize (convexSetSize)
	);
	

	wire [3:0] BCD0, BCD1, BCD2, BCD3, BCD4;
	
	assign BCD4 = (convexSetSize / 10000);
	assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);
	assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);
	assign BCD1 = (((convexSetSize % 100) - (convexSetSize % 10)) / 10);
	assign BCD0 = (((convexSetSize % 10) - (convexSetSize % 1)) / 1);


	assign outputResult [31:28] = 4'b0000;
	assign outputResult [27:24] = 4'b0000;
	assign outputResult [23:20] = 4'b0000;
	assign outputResult [19:16] = BCD4;
	assign outputResult [15:12] = BCD3;
	assign outputResult [11:8] = BCD2;
	assign outputResult [7:4] = BCD1;
	assign outputResult [3:0] = BCD0;
	

	wire[2:0] ssdscan_clk;
	assign ssdscan_clk = DIV_CLK[19:17];
	assign AN[0] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[1] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[2] = !( (~(ssdscan_clk[2])) &&  (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[3] = !( (~(ssdscan_clk[2])) &&  (ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[4] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[5] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) &&  (ssdscan_clk[0]) );
	assign AN[6] = !( ( (ssdscan_clk[2])) &&  (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
	assign AN[7] = !( ( (ssdscan_clk[2])) &&  (ssdscan_clk[1]) &&  (ssdscan_clk[0]) );

    wire[3:0] SSD7, SSD6, SSD5, SSD4, SSD3, SSD2, SSD1, SSD0;
    
	assign SSD7 = outputResult[31:28];
	assign SSD6 = outputResult[27:24];
	assign SSD5 = outputResult[23:20];
	assign SSD4 = outputResult[19:16];
	assign SSD3 = outputResult[15:12];
	assign SSD2 = outputResult[11:8];
	assign SSD1 = outputResult[7:4];
	assign SSD0 = outputResult[3:0];
	
	always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3, SSD4, SSD5, SSD6, SSD7)
	begin : SSD_SCAN_OUT
		case (ssdscan_clk) 
            3'b000: SSD = SSD0;
            3'b001: SSD = SSD1;
            3'b010: SSD = SSD2;
            3'b011: SSD = SSD3;
            3'b100: SSD = SSD4;
            3'b101: SSD = SSD5;
            3'b110: SSD = SSD6;
            3'b111: SSD = SSD7;
		endcase 
	end

	always @ (SSD) begin
		case (SSD)
			4'b1010: SSD_CATHODES = 7'b0001000 ;
			4'b1011: SSD_CATHODES = 7'b1100000 ;
			4'b1100: SSD_CATHODES = 7'b0110001 ;
			4'b1101: SSD_CATHODES = 7'b1000010 ;
			4'b1110: SSD_CATHODES = 7'b0110000 ;
			4'b1111: SSD_CATHODES = 7'b0111000 ;
			4'b0000: SSD_CATHODES = 7'b0000001 ;
			4'b0001: SSD_CATHODES = 7'b1001111 ;
			4'b0010: SSD_CATHODES = 7'b0010010 ;
			4'b0011: SSD_CATHODES = 7'b0000110 ;
			4'b0100: SSD_CATHODES = 7'b1001100 ;
			4'b0101: SSD_CATHODES = 7'b0100100 ;
			4'b0110: SSD_CATHODES = 7'b0100000 ;
			4'b0111: SSD_CATHODES = 7'b0001111 ;
			4'b1000: SSD_CATHODES = 7'b0000000 ;
			4'b1001: SSD_CATHODES = 7'b0001100 ;
		endcase
	end	
	
endmodule