data/full_repos/permissive/455657973/logicalAnd.v
data/verilator_xmls/102b4312-aa18-4001-82ab-188bf7deb8d8.xml
module logicalAnd(input [31:0] in2, in1, output [31:0]out);

assign out = in1 & in2;

endmodule
module logicalAnd(input [31:0] in2, in1, output [31:0]out);


assign out = in1 & in2;

endmodule