data/full_repos/permissive/493019833/test/testcase/firrtl/TrimTypeCircuit/sbt/TrimTypeCircuit.v
data/verilator_xmls/548d1c7b-a0a2-4980-a84c-81621fea7781.xml
module TrimTypeCircuit(
  input         clock,
  input         reset,
  input  [3:0]  io_a,
  input  [3:0]  io_b,
  output [9:0]  io_multiplyRoundHalfUp,
  output [19:0] io_multiplyNoTrim
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg [7:0] regMultiplyRoundHalfUp;
  reg [7:0] regMultiplyNoTrim;
  wire [8:0] _GEN_0 = {$signed(regMultiplyRoundHalfUp), 1'h0};
  wire [10:0] _GEN_1 = {$signed(regMultiplyNoTrim), 3'h0};
  assign io_multiplyRoundHalfUp = {{1{_GEN_0[8]}},_GEN_0};
  assign io_multiplyNoTrim = {{9{_GEN_1[10]}},_GEN_1};
  always @(posedge clock) begin
    regMultiplyRoundHalfUp <= $signed(io_a) * $signed(io_b);
    regMultiplyNoTrim <= $signed(io_a) * $signed(io_b);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regMultiplyRoundHalfUp = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  regMultiplyNoTrim = _RAND_1[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module TrimTypeCircuit(
  input         clock,
  input         reset,
  input  [3:0]  io_a,
  input  [3:0]  io_b,
  output [9:0]  io_multiplyRoundHalfUp,
  output [19:0] io_multiplyNoTrim
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg [7:0] regMultiplyRoundHalfUp;
  reg [7:0] regMultiplyNoTrim;
  wire [8:0] _GEN_0 = {$signed(regMultiplyRoundHalfUp), 1'h0};
  wire [10:0] _GEN_1 = {$signed(regMultiplyNoTrim), 3'h0};
  assign io_multiplyRoundHalfUp = {{1{_GEN_0[8]}},_GEN_0};
  assign io_multiplyNoTrim = {{9{_GEN_1[10]}},_GEN_1};
  always @(posedge clock) begin
    regMultiplyRoundHalfUp <= $signed(io_a) * $signed(io_b);
    regMultiplyNoTrim <= $signed(io_a) * $signed(io_b);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regMultiplyRoundHalfUp = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  regMultiplyNoTrim = _RAND_1[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule