data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("power_trig_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,power_trig_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n   initial #100 rst <= 0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n     #100000 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2000 run <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/custom/power_trig_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #30000 run <= 0;\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module power_trig_tb();
   initial $dumpfile("power_trig_tb.vcd");
   initial $dumpvars(0,power_trig_tb);

   reg clk = 0;
   always #10 clk <= ~clk;
   reg rst = 1;
   initial #100 rst <= 0;

   initial
     begin
	set_stb <= 0;
	#1000;
	set_stb <= 1;
     end
   
   reg [31:0] sample_in;
   reg 	      strobe_in;
   wire [31:0] sample_out;
   wire        strobe_out;
   reg 	       set_stb, run;
   
   power_trig #(.BASE(0)) power_trig
     (.clk(clk), .reset(rst), .enable(1),
      .set_stb(set_stb), .set_addr(0), .set_data(32'h000B_B000),
      .run(run),

      .ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in),
      .bb_sample(sample_out), .bb_strobe(strobe_out));

   initial sample_in <= 32'h0100_0300;
   
   always @(posedge clk)
     if(~strobe_in)
       sample_in <= sample_in + 32'h0001_0001;

   initial
     #100000 $finish;

   initial 
     begin
	run <= 0;
	#2000 run <= 1;
	#30000 run <= 0;
     end

   always @(posedge clk)
     if(rst | ~run)
       strobe_in <= 0;
     else
       strobe_in <= ~strobe_in;
   
endmodule
module power_trig_tb();

   initial $dumpfile("power_trig_tb.vcd");
   initial $dumpvars(0,power_trig_tb);

   reg clk = 0;
   always #10 clk <= ~clk;
   reg rst = 1;
   initial #100 rst <= 0;

   initial
     begin
	set_stb <= 0;
	#1000;
	set_stb <= 1;
     end
   
   reg [31:0] sample_in;
   reg 	      strobe_in;
   wire [31:0] sample_out;
   wire        strobe_out;
   reg 	       set_stb, run;
   
   power_trig #(.BASE(0)) power_trig
     (.clk(clk), .reset(rst), .enable(1),
      .set_stb(set_stb), .set_addr(0), .set_data(32'h000B_B000),
      .run(run),

      .ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in),
      .bb_sample(sample_out), .bb_strobe(strobe_out));

   initial sample_in <= 32'h0100_0300;
   
   always @(posedge clk)
     if(~strobe_in)
       sample_in <= sample_in + 32'h0001_0001;

   initial
     #100000 $finish;

   initial 
     begin
	run <= 0;
	#2000 run <= 1;
	#30000 run <= 0;
     end

   always @(posedge clk)
     if(rst | ~run)
       strobe_in <= 0;
     else
       strobe_in <= ~strobe_in;
   
endmodule