data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/2014_q3c/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/2014_q3c,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/2014_q3c/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire clk,
    input wire [2:0] y,
    input wire x,
    output wire Y0,
    output reg z
);

  parameter STATE_000 = 3'b000;
  parameter STATE_001 = 3'b001;
  parameter STATE_010 = 3'b010;
  parameter STATE_011 = 3'b011;
  parameter STATE_100 = 3'b100;

  wire [2:0] state;
  reg  [2:0] next_state;

  assign state = y;
  assign Y0 = next_state[0];


  always @(*) begin
    case ({
      x, state
    })
      {1'b0, STATE_000} : next_state = STATE_000;
      {1'b1, STATE_000} : next_state = STATE_001;
      {1'b0, STATE_001} : next_state = STATE_001;
      {1'b1, STATE_001} : next_state = STATE_100;
      {1'b0, STATE_010} : next_state = STATE_010;
      {1'b1, STATE_010} : next_state = STATE_001;
      {1'b0, STATE_011} : next_state = STATE_001;
      {1'b1, STATE_011} : next_state = STATE_010;
      {1'b0, STATE_100} : next_state = STATE_011;
      {1'b1, STATE_100} : next_state = STATE_100;
      default: next_state = STATE_000;
    endcase
  end


  always @(*) begin
    case (state)
      STATE_011, STATE_100: z = 1'b1;
      default: z = 1'b0;
    endcase
  end
endmodule
module top_module (
    input wire clk,
    input wire [2:0] y,
    input wire x,
    output wire Y0,
    output reg z
);


  parameter STATE_000 = 3'b000;
  parameter STATE_001 = 3'b001;
  parameter STATE_010 = 3'b010;
  parameter STATE_011 = 3'b011;
  parameter STATE_100 = 3'b100;

  wire [2:0] state;
  reg  [2:0] next_state;

  assign state = y;
  assign Y0 = next_state[0];


  always @(*) begin
    case ({
      x, state
    })
      {1'b0, STATE_000} : next_state = STATE_000;
      {1'b1, STATE_000} : next_state = STATE_001;
      {1'b0, STATE_001} : next_state = STATE_001;
      {1'b1, STATE_001} : next_state = STATE_100;
      {1'b0, STATE_010} : next_state = STATE_010;
      {1'b1, STATE_010} : next_state = STATE_001;
      {1'b0, STATE_011} : next_state = STATE_001;
      {1'b1, STATE_011} : next_state = STATE_010;
      {1'b0, STATE_100} : next_state = STATE_011;
      {1'b1, STATE_100} : next_state = STATE_100;
      default: next_state = STATE_000;
    endcase
  end


  always @(*) begin
    case (state)
      STATE_011, STATE_100: z = 1'b1;
      default: z = 1'b0;
    endcase
  end
endmodule