data/full_repos/permissive/418749135/halfadder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/halfadder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/halfadder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/halfadder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Error: data/full_repos/permissive/418749135/halfadder_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/halfadder_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module half_adder_verilog_tb();

reg a, b;
wire s, c;

half_adder dut (.a(a), .b(b), .s(s), .c(c));

initial
begin

a = 1'b0;
b = 1'b0;
#50;

a = 1'b0;
b = 1'b1;
#50;

a = 1'b1;
b = 1'b0;
#50;

a = 1'b1;
b = 1'b1;

end
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end

endmodule
module half_adder_verilog_tb();


reg a, b;
wire s, c;

half_adder dut (.a(a), .b(b), .s(s), .c(c));

initial
begin

a = 1'b0;
b = 1'b0;
#50;

a = 1'b0;
b = 1'b1;
#50;

a = 1'b1;
b = 1'b0;
#50;

a = 1'b1;
b = 1'b1;

end
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end

endmodule