data/full_repos/permissive/419273451/lab1/codes/Adder.v
data/verilator_xmls/d4ea7ab4-bbff-4503-b0d7-f6465bf1077a.xml
module Adder
(
    data1_i,
    data2_i,
    data_o
);


input   signed[31:0]      data1_i;
input   signed[31:0]      data2_i;
output  signed[31:0]      data_o;

assign data_o = data1_i + data2_i;

endmodule
module Adder
(
    data1_i,
    data2_i,
    data_o
);



input   signed[31:0]      data1_i;
input   signed[31:0]      data2_i;
output  signed[31:0]      data_o;

assign data_o = data1_i + data2_i;

endmodule