data/full_repos/permissive/480681467/Source/Main/mux.v
data/verilator_xmls/77534cc7-e32b-4739-8d96-be28fc9c1ee2.xml
module mux(
    output reg out,
    input sel,
    input a,
    input b
    );
    
    wire not_sel;
    always @(sel or not_sel)
        out = (sel&a)|(not_sel&b);
    
    assign not_sel = ~sel;
    
endmodule
module mux(
    output reg out,
    input sel,
    input a,
    input b
    );

    
    wire not_sel;
    always @(sel or not_sel)
        out = (sel&a)|(not_sel&b);
    
    assign not_sel = ~sel;
    
endmodule