data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v
1: b'%Error: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:74: Cannot find file containing module: \'xadc_wiz_2\'\nxadc_wiz_2  XLXI_7 (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.v\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.sv\n             xadc_wiz_2\n             xadc_wiz_2.v\n             xadc_wiz_2.sv\n             obj_dir/xadc_wiz_2\n             obj_dir/xadc_wiz_2.v\n             obj_dir/xadc_wiz_2.sv\n%Warning-WIDTH: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:109: Input port connection \'jxADC\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'JXADC\' generates 8 bits.\n                                                                                                : ... In instance main_driver\nadc_controller dut0(clk, JXADC, data);\n                         ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module motor_signals(clk, enable, fwd, Apos, Aneg, Bpos, Bneg, Cpos, Cneg, hall);
input clk, enable, fwd; 
input [2:0] hall;
output Apos, Aneg, Bpos, Bneg, Cpos, Cneg; 


parameter s0 = 6'b000000;
parameter s1 = 6'b100001;
parameter s2 = 6'b100100;   
parameter s3 = 6'b000110;   
parameter s4 = 6'b010010;
parameter s5 = 6'b011000;
parameter s6 = 6'b001001;

reg [5:0] state = s0;

assign {Apos, Aneg, Bpos, Bneg, Cpos, Cneg} = state;    

always @(posedge clk) begin  
    if (!enable) state <= s0;
    else case (state)
        s0: begin
            if (hall == 3'b001) state <= s1;
            else if (hall == 3'b000) state <= s2;
            else if (hall == 3'b100) state <= s3;
            else if (hall == 3'b110) state <= s4;
            else if (hall == 3'b111) state <= s5;
            else if (hall == 3'b011) state <= s6;
            else state <= s0;
        end
        s1: state <= enable ? (fwd ? s2 : s6) : s0;
        s2: state <= enable ? (fwd ? s3 : s1) : s0;
        s3: state <= enable ? (fwd ? s4 : s2) : s0;
        s4: state <= enable ? (fwd ? s5 : s3) : s0;
        s5: state <= enable ? (fwd ? s6 : s4) : s0;
        s6: state <= enable ? (fwd ? s1 : s5) : s0;
    endcase 
end
endmodule
module motor_signals(clk, enable, fwd, Apos, Aneg, Bpos, Bneg, Cpos, Cneg, hall);

input clk, enable, fwd; 
input [2:0] hall;
output Apos, Aneg, Bpos, Bneg, Cpos, Cneg; 


parameter s0 = 6'b000000;
parameter s1 = 6'b100001;
parameter s2 = 6'b100100;   
parameter s3 = 6'b000110;   
parameter s4 = 6'b010010;
parameter s5 = 6'b011000;
parameter s6 = 6'b001001;

reg [5:0] state = s0;

assign {Apos, Aneg, Bpos, Bneg, Cpos, Cneg} = state;    

always @(posedge clk) begin  
    if (!enable) state <= s0;
    else case (state)
        s0: begin
            if (hall == 3'b001) state <= s1;
            else if (hall == 3'b000) state <= s2;
            else if (hall == 3'b100) state <= s3;
            else if (hall == 3'b110) state <= s4;
            else if (hall == 3'b111) state <= s5;
            else if (hall == 3'b011) state <= s6;
            else state <= s0;
        end
        s1: state <= enable ? (fwd ? s2 : s6) : s0;
        s2: state <= enable ? (fwd ? s3 : s1) : s0;
        s3: state <= enable ? (fwd ? s4 : s2) : s0;
        s4: state <= enable ? (fwd ? s5 : s3) : s0;
        s5: state <= enable ? (fwd ? s6 : s4) : s0;
        s6: state <= enable ? (fwd ? s1 : s5) : s0;
    endcase 
end
endmodule