data/full_repos/permissive/468929885/verilog/rtl/el_ed.v
data/verilator_xmls/822d1f5b-ec1a-46df-adf1-cb47bc3ca92e.xml
module el_ed
(

	input							rst,

	input							en,
	input							fb,
	input							in,

	output							out

);

reg state_r = 0;

assign out = state_r ^ in;

always@(*)
begin
	if(rst)
	begin
		state_r = 0;
	end
	else
	begin
		if(en)
		begin
			state_r = in ^ fb;
		end
	end
end



endmodule
module el_ed
(

	input							rst,

	input							en,
	input							fb,
	input							in,

	output							out

);


reg state_r = 0;

assign out = state_r ^ in;

always@(*)
begin
	if(rst)
	begin
		state_r = 0;
	end
	else
	begin
		if(en)
		begin
			state_r = in ^ fb;
		end
	end
end



endmodule