data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:455: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n%Warning-PINMISSING: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:246: Cell has missing pin: \'io_enq_ready\'\n  Queue resDumpQueue(.clk(clk), .reset(reset),\n        ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    R1 = {1{$random}};\n       ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    R4 = {1{$random}};\n       ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:45: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                               : ... In instance SparseFrontierFrontend.resDump.resDumpQueue\n    maybe_full = {1{$random}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:179: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid3 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:180: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid2 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:181: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regValid1 = {1{$random}};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:182: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regReqCount = {1{$random}};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:183: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regState = {1{$random}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:185: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n    regReadAddr = {1{$random}};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:197: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T40 = T41[2\'h3:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:235: Bit extraction of var[24:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T47 = T31[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:236: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s VARREF \'T32\' generates 20 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T31 = T32 << 3\'h5;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:243: Bit extraction of var[24:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T49 = T36[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:244: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s VARREF \'regReadAddr\' generates 20 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend.resDump\n  assign T36 = regReadAddr << 3\'h5;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:457: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regState = {1{$random}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:458: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regResetAddr = {1{$random}};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:460: Operator ASSIGN expects 31 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regRowIndsLeftInCol = {1{$random}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:461: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regAligned = {1{$random}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:462: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n    regStartDump = {1{$random}};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:468: Bit extraction of var[31:0] requires 5 bit index, not 3 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T0 = regRowCount[5\'h15:3\'h6];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:483: Bit extraction of var[31:0] requires 5 bit index, not 2 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign enableBRAMReset = io_ctrl[2\'h2:2\'h2];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:485: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign startAccel = io_ctrl[1\'h0:1\'h0];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:488: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign enableBRAMDump = io_ctrl[1\'h1:1\'h1];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:523: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T46 = rowIndMetadata_TDATA[5\'h1e:1\'h0];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:558: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T95 = T74[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:569: Bit extraction of var[31:0] requires 5 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign T98 = T78[5\'h13:1\'h0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/506208052/src/hdl/SparseFrontierFrontend/SparseFrontierFrontend.v:572: Bit extraction of var[63:0] requires 6 bit index, not 1 bits.\n                                                                                                                : ... In instance SparseFrontierFrontend\n  assign rowIndLower = rowIndData_TDATA[5\'h1f:1\'h0];\n                                       ^\n%Error: Exiting due to 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Queue(input clk, input reset,
    output io_enq_ready,
    input  io_enq_valid,
    input [63:0] io_enq_bits,
    input  io_deq_ready,
    output io_deq_valid,
    output[63:0] io_deq_bits,
    output[4:0] io_count
);

  wire[4:0] T0;
  wire[3:0] ptr_diff;
  reg [3:0] R1;
  wire[3:0] T15;
  wire[3:0] T2;
  wire[3:0] T3;
  wire do_deq;
  reg [3:0] R4;
  wire[3:0] T16;
  wire[3:0] T5;
  wire[3:0] T6;
  wire do_enq;
  wire T7;
  wire ptr_match;
  reg  maybe_full;
  wire T17;
  wire T8;
  wire T9;
  wire[63:0] T10;
  reg [63:0] ram [15:0];
  wire[63:0] T11;
  wire T12;
  wire empty;
  wire T13;
  wire T14;
  wire full;

`ifndef SYNTHESIS

  integer initvar;
  initial begin
    #0.002;
    R1 = {1{$random}};
    R4 = {1{$random}};
    maybe_full = {1{$random}};
    for (initvar = 0; initvar < 16; initvar = initvar+1)
      ram[initvar] = {2{$random}};
  end

`endif

  assign io_count = T0;
  assign T0 = {T7, ptr_diff};
  assign ptr_diff = R4 - R1;
  assign T15 = reset ? 4'h0 : T2;
  assign T2 = do_deq ? T3 : R1;
  assign T3 = R1 + 4'h1;
  assign do_deq = io_deq_ready & io_deq_valid;
  assign T16 = reset ? 4'h0 : T5;
  assign T5 = do_enq ? T6 : R4;
  assign T6 = R4 + 4'h1;
  assign do_enq = io_enq_ready & io_enq_valid;
  assign T7 = maybe_full & ptr_match;
  assign ptr_match = R4 == R1;
  assign T17 = reset ? 1'h0 : T8;
  assign T8 = T9 ? do_enq : maybe_full;
  assign T9 = do_enq != do_deq;
  assign io_deq_bits = T10;
  assign T10 = ram[R1];
  assign io_deq_valid = T12;
  assign T12 = empty ^ 1'h1;
  assign empty = ptr_match & T13;
  assign T13 = maybe_full ^ 1'h1;
  assign io_enq_ready = T14;
  assign T14 = full ^ 1'h1;
  assign full = ptr_match & maybe_full;

  always @(posedge clk) begin
    if(reset) begin
      R1 <= 4'h0;
    end else if(do_deq) begin
      R1 <= T3;
    end
    if(reset) begin
      R4 <= 4'h0;
    end else if(do_enq) begin
      R4 <= T6;
    end
    if(reset) begin
      maybe_full <= 1'h0;
    end else if(T9) begin
      maybe_full <= do_enq;
    end
    if (do_enq)
      ram[R4] <= io_enq_bits;
  end
endmodule
module Queue(input clk, input reset,
    output io_enq_ready,
    input  io_enq_valid,
    input [63:0] io_enq_bits,
    input  io_deq_ready,
    output io_deq_valid,
    output[63:0] io_deq_bits,
    output[4:0] io_count
);


  wire[4:0] T0;
  wire[3:0] ptr_diff;
  reg [3:0] R1;
  wire[3:0] T15;
  wire[3:0] T2;
  wire[3:0] T3;
  wire do_deq;
  reg [3:0] R4;
  wire[3:0] T16;
  wire[3:0] T5;
  wire[3:0] T6;
  wire do_enq;
  wire T7;
  wire ptr_match;
  reg  maybe_full;
  wire T17;
  wire T8;
  wire T9;
  wire[63:0] T10;
  reg [63:0] ram [15:0];
  wire[63:0] T11;
  wire T12;
  wire empty;
  wire T13;
  wire T14;
  wire full;

`ifndef SYNTHESIS

  integer initvar;
  initial begin
    #0.002;
    R1 = {1{$random}};
    R4 = {1{$random}};
    maybe_full = {1{$random}};
    for (initvar = 0; initvar < 16; initvar = initvar+1)
      ram[initvar] = {2{$random}};
  end

`endif

  assign io_count = T0;
  assign T0 = {T7, ptr_diff};
  assign ptr_diff = R4 - R1;
  assign T15 = reset ? 4'h0 : T2;
  assign T2 = do_deq ? T3 : R1;
  assign T3 = R1 + 4'h1;
  assign do_deq = io_deq_ready & io_deq_valid;
  assign T16 = reset ? 4'h0 : T5;
  assign T5 = do_enq ? T6 : R4;
  assign T6 = R4 + 4'h1;
  assign do_enq = io_enq_ready & io_enq_valid;
  assign T7 = maybe_full & ptr_match;
  assign ptr_match = R4 == R1;
  assign T17 = reset ? 1'h0 : T8;
  assign T8 = T9 ? do_enq : maybe_full;
  assign T9 = do_enq != do_deq;
  assign io_deq_bits = T10;
  assign T10 = ram[R1];
  assign io_deq_valid = T12;
  assign T12 = empty ^ 1'h1;
  assign empty = ptr_match & T13;
  assign T13 = maybe_full ^ 1'h1;
  assign io_enq_ready = T14;
  assign T14 = full ^ 1'h1;
  assign full = ptr_match & maybe_full;

  always @(posedge clk) begin
    if(reset) begin
      R1 <= 4'h0;
    end else if(do_deq) begin
      R1 <= T3;
    end
    if(reset) begin
      R4 <= 4'h0;
    end else if(do_enq) begin
      R4 <= T6;
    end
    if(reset) begin
      maybe_full <= 1'h0;
    end else if(T9) begin
      maybe_full <= do_enq;
    end
    if (do_enq)
      ram[R4] <= io_enq_bits;
  end
endmodule