data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new/Debouncer.v
1: b"%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new/Debouncer.v:33: Cannot find file containing module: 'Counter'\n    Counter #(20) c(count, nreset, clock);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.v\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Error: Exiting due to 1 error(s)\n"
module Debouncer(
    output reg out,
    input in,
    input clock
);
    reg nreset;

    wire idle, max;
    wire [19:0] count;

    Counter #(20) c(count, nreset, clock);

    assign idle = (out == in);
    assign max = &count;

    initial
    begin
        out <= 0;
        nreset <= 0;
    end

    always @(posedge clock)
    begin
        if(idle) nreset <= 0;
        else
            begin
                nreset <= 1;
                if(max) out <= ~out;
            end
    end

endmodule
module Debouncer(
    output reg out,
    input in,
    input clock
);

    reg nreset;

    wire idle, max;
    wire [19:0] count;

    Counter #(20) c(count, nreset, clock);

    assign idle = (out == in);
    assign max = &count;

    initial
    begin
        out <= 0;
        nreset <= 0;
    end

    always @(posedge clock)
    begin
        if(idle) nreset <= 0;
        else
            begin
                nreset <= 1;
                if(max) out <= ~out;
            end
    end

endmodule