data/full_repos/permissive/463481430/simulation/tb1.v
1: b"%Error: data/full_repos/permissive/463481430/simulation/tb1.v:21: Cannot find file containing module: 'FPU32'\nFPU32 u_FPU32(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/FPU32\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/FPU32.v\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/FPU32.sv\n             FPU32\n             FPU32.v\n             FPU32.sv\n             obj_dir/FPU32\n             obj_dir/FPU32.v\n             obj_dir/FPU32.sv\n%Error: Exiting due to 1 error(s)\n"
module TEST_TOP1(
    input wire i_clk,
    input wire[31:0] a,
    input wire[31:0] b,
    output reg[31:0] c
);


reg[31:0] A,B;


wire[31:0] res1;
wire[31:0] res2;
wire[31:0] res3;
wire[31:0] res4;
FPU32 u_FPU32(
    .i_clk    (     ),
    .i_rsn    (     ),
    .i_op1    ( A    ),
    .i_op2    ( B    ),
    .o_addres ( res1 ),
    .o_subres ( res2 ),
    .o_mulres ( res3 ),
    .o_divres (    )
);


always @(posedge i_clk) begin
    A <= a;
    B <= b;
    c <= res2;
end




endmodule
module TEST_TOP1(
    input wire i_clk,
    input wire[31:0] a,
    input wire[31:0] b,
    output reg[31:0] c
);



reg[31:0] A,B;


wire[31:0] res1;
wire[31:0] res2;
wire[31:0] res3;
wire[31:0] res4;
FPU32 u_FPU32(
    .i_clk    (     ),
    .i_rsn    (     ),
    .i_op1    ( A    ),
    .i_op2    ( B    ),
    .o_addres ( res1 ),
    .o_subres ( res2 ),
    .o_mulres ( res3 ),
    .o_divres (    )
);


always @(posedge i_clk) begin
    A <= a;
    B <= b;
    c <= res2;
end




endmodule