data/full_repos/permissive/496508301/Lesson5/sec_counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #17     res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1000   $stop;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:60: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sec_counter_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:61: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module s_counter_tb();
reg         clk;
reg         res;
wire[3:0]   s_num;
s_counter s_counter(
    .clk(clk),
    .res(res),
    .s_num(s_num)
);
initial begin
            clk <= 0; res <= 0;
    #17     res <= 1;
    #1000   $stop;    
end
always #5 clk=~clk;

initial begin
    $dumpfile("sec_counter_tb.vcd");
    $dumpvars;
end
endmodule
module s_counter_tb();

reg         clk;
reg         res;
wire[3:0]   s_num;
s_counter s_counter(
    .clk(clk),
    .res(res),
    .s_num(s_num)
);
initial begin
            clk <= 0; res <= 0;
    #17     res <= 1;
    #1000   $stop;    
end
always #5 clk=~clk;

initial begin
    $dumpfile("sec_counter_tb.vcd");
    $dumpvars;
end
endmodule