data/full_repos/permissive/507312280/rtl/perips/sram.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/perips,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:8: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    sram_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`MemAddrBus]    sram_axi_awaddr , \n                           ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sram_axi_awready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:12: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemBus]        sram_axi_wdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:12: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus]        sram_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  sram_axi_wvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sram_axi_wready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemAddrBus]    sram_axi_araddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:17: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    sram_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sram_axi_arready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemBus]        sram_axi_rdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:21: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        sram_axi_rdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:23: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  sram_axi_rready  \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:29: Define or directive not defined: \'`SRamSize\'\nreg [clogb2(`SRamSize-1)-1:0]addr;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:32: Define or directive not defined: \'`MemBus\'\nreg [`MemBus]dout;\n     ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`MemBus]dout;\n            ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:33: Define or directive not defined: \'`MemBus\'\nreg [`MemBus]din;\n     ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`MemBus]din;\n            ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:39: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) \n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:57: Define or directive not defined: \'`SRamSize\'\n        addr = sram_axi_awaddr[clogb2(`SRamSize-1)+1:2];\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:62: Define or directive not defined: \'`SRamSize\'\n            addr = sram_axi_araddr[clogb2(`SRamSize-1)+1:2];\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:75: Define or directive not defined: \'`SRamSize\'\nlocalparam RAM_DEPTH = `SRamSize; \n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nlocalparam RAM_DEPTH = `SRamSize; \n                                ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:80: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sram.v:104: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module sram (
	input clk,
	input rst_n,



    input wire [`MemAddrBus]    sram_axi_awaddr ,
    input wire                  sram_axi_awvalid,
    output reg                  sram_axi_awready,

    input wire [`MemBus]        sram_axi_wdata  ,
    input wire [3:0]            sram_axi_wstrb  ,
    input wire                  sram_axi_wvalid ,
    output reg                  sram_axi_wready ,

    input wire [`MemAddrBus]    sram_axi_araddr ,
    input wire                  sram_axi_arvalid,
    output reg                  sram_axi_arready,

    output reg [`MemBus]        sram_axi_rdata  ,
    output reg                  sram_axi_rvalid ,
    input wire                  sram_axi_rready
	
);



reg [clogb2(`SRamSize-1)-1:0]addr;
reg we,en;
reg [3:0] wem;
reg [`MemBus]dout;
reg [`MemBus]din;
wire axi_whsk = sram_axi_awvalid & sram_axi_wvalid;
wire axi_rhsk = sram_axi_arvalid & (~sram_axi_rvalid | (sram_axi_rvalid & sram_axi_rready)) & ~axi_whsk;



always @(posedge clk or negedge rst_n)
if (~rst_n)
    sram_axi_rvalid <=1'b0;
else begin
    if (axi_rhsk)
        sram_axi_rvalid <=1'b1;
    else if (sram_axi_rvalid & sram_axi_rready)
        sram_axi_rvalid <=1'b0;
    else
        sram_axi_rvalid <= sram_axi_rvalid;
end

always @(*) begin
    sram_axi_awready = axi_whsk;
    sram_axi_wready = axi_whsk;
    sram_axi_rdata = dout;
    sram_axi_arready = axi_rhsk;
    if(axi_whsk) begin
        addr = sram_axi_awaddr[clogb2(`SRamSize-1)+1:2];
        we = 1;
    end
    else begin
        if (axi_rhsk) begin
            addr = sram_axi_araddr[clogb2(`SRamSize-1)+1:2];
            we = 0;
        end
        else begin
            addr = 0;
            we = 0;
        end
    end
    din = sram_axi_wdata;
    en = axi_whsk | axi_rhsk;
    wem = sram_axi_wstrb;
end

localparam RAM_DEPTH = `SRamSize;
localparam RAM_WIDTH = 32;

reg [RAM_WIDTH-1:0] BRAM [0:RAM_DEPTH-1];

always @(posedge clk)
    if (en) begin
        if (we) begin
            if(wem[0])
                BRAM[addr][7:0] <= din[7:0];
            if(wem[1])
                BRAM[addr][15:8] <= din[15:8];
            if(wem[2])
                BRAM[addr][23:16] <= din[23:16];
            if(wem[3])
                BRAM[addr][31:24] <= din[31:24];
        end
        else begin
            dout <= BRAM[addr];
        end
    end


function integer clogb2;
    input integer depth;
        for (clogb2=0; depth>0; clogb2=clogb2+1)
            depth = depth >> 1;
endfunction

endmodule
module sram (
	input clk,
	input rst_n,



    input wire [`MemAddrBus]    sram_axi_awaddr ,
    input wire                  sram_axi_awvalid,
    output reg                  sram_axi_awready,

    input wire [`MemBus]        sram_axi_wdata  ,
    input wire [3:0]            sram_axi_wstrb  ,
    input wire                  sram_axi_wvalid ,
    output reg                  sram_axi_wready ,

    input wire [`MemAddrBus]    sram_axi_araddr ,
    input wire                  sram_axi_arvalid,
    output reg                  sram_axi_arready,

    output reg [`MemBus]        sram_axi_rdata  ,
    output reg                  sram_axi_rvalid ,
    input wire                  sram_axi_rready
	
);




reg [clogb2(`SRamSize-1)-1:0]addr;
reg we,en;
reg [3:0] wem;
reg [`MemBus]dout;
reg [`MemBus]din;
wire axi_whsk = sram_axi_awvalid & sram_axi_wvalid;
wire axi_rhsk = sram_axi_arvalid & (~sram_axi_rvalid | (sram_axi_rvalid & sram_axi_rready)) & ~axi_whsk;



always @(posedge clk or negedge rst_n)
if (~rst_n)
    sram_axi_rvalid <=1'b0;
else begin
    if (axi_rhsk)
        sram_axi_rvalid <=1'b1;
    else if (sram_axi_rvalid & sram_axi_rready)
        sram_axi_rvalid <=1'b0;
    else
        sram_axi_rvalid <= sram_axi_rvalid;
end

always @(*) begin
    sram_axi_awready = axi_whsk;
    sram_axi_wready = axi_whsk;
    sram_axi_rdata = dout;
    sram_axi_arready = axi_rhsk;
    if(axi_whsk) begin
        addr = sram_axi_awaddr[clogb2(`SRamSize-1)+1:2];
        we = 1;
    end
    else begin
        if (axi_rhsk) begin
            addr = sram_axi_araddr[clogb2(`SRamSize-1)+1:2];
            we = 0;
        end
        else begin
            addr = 0;
            we = 0;
        end
    end
    din = sram_axi_wdata;
    en = axi_whsk | axi_rhsk;
    wem = sram_axi_wstrb;
end

localparam RAM_DEPTH = `SRamSize;
localparam RAM_WIDTH = 32;

reg [RAM_WIDTH-1:0] BRAM [0:RAM_DEPTH-1];

always @(posedge clk)
    if (en) begin
        if (we) begin
            if(wem[0])
                BRAM[addr][7:0] <= din[7:0];
            if(wem[1])
                BRAM[addr][15:8] <= din[15:8];
            if(wem[2])
                BRAM[addr][23:16] <= din[23:16];
            if(wem[3])
                BRAM[addr][31:24] <= din[31:24];
        end
        else begin
            dout <= BRAM[addr];
        end
    end


function integer clogb2;
    input integer depth;
        for (clogb2=0; depth>0; clogb2=clogb2+1)
            depth = depth >> 1;
endfunction

endmodule