data/full_repos/permissive/489075769/write_data_ms.v
data/verilator_xmls/daa01da0-7d13-45a7-a7a5-0a520c37d808.xml
module write_data_slave (ACLK, ARESETn,WVALID, o_WREADY, i_WREADY, i_WDATA, o_WDATA, i_WSTRB, o_WSTRB);
input ACLK;
input ARESETn;
input WVALID;
input i_WREADY;
input [31:0] i_WDATA;
input [3:0] i_WSTRB;  
output reg o_WREADY;
output reg [31:0] o_WDATA;       
output reg [3:0] o_WSTRB;

	
	
always @(posedge ACLK) begin 
o_WREADY <= i_WREADY;  
o_WSTRB <= i_WSTRB;

if (ARESETn) begin
o_WDATA <= 0;
o_WREADY <= 0;
o_WSTRB <= 0;
end

if (o_WREADY && WVALID) o_WDATA <= i_WDATA;
else o_WDATA <= 0;


end
     

	
endmodule
module write_data_slave (ACLK, ARESETn,WVALID, o_WREADY, i_WREADY, i_WDATA, o_WDATA, i_WSTRB, o_WSTRB);

input ACLK;
input ARESETn;
input WVALID;
input i_WREADY;
input [31:0] i_WDATA;
input [3:0] i_WSTRB;  
output reg o_WREADY;
output reg [31:0] o_WDATA;       
output reg [3:0] o_WSTRB;

	
	
always @(posedge ACLK) begin 
o_WREADY <= i_WREADY;  
o_WSTRB <= i_WSTRB;

if (ARESETn) begin
o_WDATA <= 0;
o_WREADY <= 0;
o_WSTRB <= 0;
end

if (o_WREADY && WVALID) o_WDATA <= i_WDATA;
else o_WDATA <= 0;


end
     

	
endmodule