data/full_repos/permissive/525452387/testbench/ex_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ex_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Error: data/full_repos/permissive/525452387/testbench/ex_tb.v:156: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("ex.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/ex_tb.v:157: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ex_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ex_test_bench;
    reg[31:0] ex_1_inst_i;
    reg[4:0] ex_1_reg_waddr_i;

    reg[31:0] ex_1_op1_i;
    reg[31:0] ex_1_op2_i;

    wire[31:0] ex_1_reg_wdata_o;
    wire[4:0] ex_1_reg_waddr_o;

    ex ex_1 (
        .inst_i(ex_1_inst_i),
        .reg_waddr_i(ex_1_reg_waddr_i),
        .op1_i(ex_1_op1_i),
        .op2_i(ex_1_op2_i),

        .reg_wdata_o(ex_1_reg_wdata_o),
        .reg_waddr_o(ex_1_reg_waddr_o)
    );

    initial begin
        #1 begin
            ex_1_inst_i = 32'hfff08013;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'hab && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0021a113;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h1 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'hffd2b213;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h1 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0043c313;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h2b && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'hffb4e413;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h6b && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0065f513;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h40 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h00769613;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h2100 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0017d713;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h21 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h4018d813;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h21 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    initial begin
        $dumpfile("ex.vcd");
        $dumpvars(0, ex_1);
    end

endmodule
module ex_test_bench;

    reg[31:0] ex_1_inst_i;
    reg[4:0] ex_1_reg_waddr_i;

    reg[31:0] ex_1_op1_i;
    reg[31:0] ex_1_op2_i;

    wire[31:0] ex_1_reg_wdata_o;
    wire[4:0] ex_1_reg_waddr_o;

    ex ex_1 (
        .inst_i(ex_1_inst_i),
        .reg_waddr_i(ex_1_reg_waddr_i),
        .op1_i(ex_1_op1_i),
        .op2_i(ex_1_op2_i),

        .reg_wdata_o(ex_1_reg_wdata_o),
        .reg_waddr_o(ex_1_reg_waddr_o)
    );

    initial begin
        #1 begin
            ex_1_inst_i = 32'hfff08013;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'hab && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0021a113;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h1 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'hffd2b213;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h1 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0043c313;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h2b && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'hffb4e413;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h6b && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0065f513;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h40 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h00769613;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h2100 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h0017d713;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h21 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            ex_1_inst_i = 32'h4018d813;
            ex_1_reg_waddr_i = 5'h3;
            ex_1_op1_i = 32'h42;
            ex_1_op2_i = 32'h69;
        end
        #1 begin
            if (ex_1_reg_wdata_o == 32'h21 && ex_1_reg_waddr_o == 5'h3) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    initial begin
        $dumpfile("ex.vcd");
        $dumpvars(0, ex_1);
    end

endmodule