data/full_repos/permissive/46376317/src/rtl/sha3.v
1: b'%Error: data/full_repos/permissive/46376317/src/rtl/sha3.v:152: Cannot find file containing module: \'sha3_core\'\n  sha3_core core(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46376317/src/rtl,data/full_repos/permissive/46376317/sha3_core\n             data/full_repos/permissive/46376317/src/rtl,data/full_repos/permissive/46376317/sha3_core.v\n             data/full_repos/permissive/46376317/src/rtl,data/full_repos/permissive/46376317/sha3_core.sv\n             sha3_core\n             sha3_core.v\n             sha3_core.sv\n             obj_dir/sha3_core\n             obj_dir/sha3_core.v\n             obj_dir/sha3_core.sv\n%Warning-WIDTH: data/full_repos/permissive/46376317/src/rtl/sha3.v:224: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                      : ... In instance sha3\n      block_addr    = address - ADDR_BLOCK00;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module sha3(

            input wire           clk,
            input wire           reset_n,


            input wire           cs,
            input wire           we,


            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
            output wire [31 : 0] read_data
           );





  localparam ADDR_NAME0       = 8'h00;
  localparam ADDR_NAME1       = 8'h01;
  localparam ADDR_VERSION     = 8'h02;

  localparam ADDR_CTRL        = 8'h08;
  localparam CTRL_INIT_BIT    = 0;
  localparam CTRL_NEXT_BIT    = 1;

  localparam ADDR_STATUS      = 8'h09;
  localparam STATUS_READY_BIT = 0;
  localparam STATUS_VALID_BIT = 1;
  localparam STATUS_ERROR_BIT = 2;

  localparam ADDR_BLOCK00     = 8'h10;
  localparam ADDR_BLOCK31     = 8'h2f;

  localparam ADDR_DIGEST00    = 8'h40;
  localparam ADDR_DIGEST15    = 8'h4f;

  localparam CORE_NAME0       = 32'h7368612d;
  localparam CORE_NAME1       = 32'h33202020;
  localparam CORE_VERSION     = 32'h302e3130;

  localparam MODE_SHA3_224    = 2'h0;
  localparam MODE_SHA3_256    = 2'h1;
  localparam MODE_SHA3_384    = 2'h2;
  localparam MODE_SHA3_512    = 2'h3;





  reg init_reg;
  reg init_new;

  reg next_reg;
  reg next_new;

  reg [1 : 0] mode_reg;
  reg [1 : 0] mode_new;
  reg         mode_we;

  reg ready_reg;

  reg [31 : 0] block_reg [0 : 31];
  reg [4 : 0]  block_addr;
  reg          block_we;

  reg [511 : 0] digest_reg;
  reg [7 : 0]   digest_addr;
  reg           digest_valid_reg;





  wire            core_init;
  wire            core_next;
  wire [1 : 0]    core_mode;
  wire            core_work_factor;
  wire [31 : 0]   core_work_factor_num;
  wire            core_ready;
  wire [1023 : 0] core_block;
  wire [511 : 0]  core_digest;
  wire            core_digest_valid;

  reg [31 : 0]    tmp_read_data;





  assign core_init = init_reg;

  assign core_next = next_reg;

  assign core_mode = mode_reg;

  assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
                       block_reg[04], block_reg[04], block_reg[05], block_reg[07],
                       block_reg[08], block_reg[09], block_reg[10], block_reg[11],
                       block_reg[12], block_reg[13], block_reg[14], block_reg[15],
                       block_reg[16], block_reg[17], block_reg[18], block_reg[19],
                       block_reg[20], block_reg[21], block_reg[22], block_reg[23],
                       block_reg[24], block_reg[24], block_reg[25], block_reg[27],
                       block_reg[28], block_reg[29], block_reg[30], block_reg[31]};

  assign read_data = tmp_read_data;





  sha3_core core(
                 .clk(clk),
                 .reset_n(reset_n),

                 .init(core_init),
                 .next(core_next),
                 .mode(core_mode),

                 .block(core_block),

                 .ready(core_ready),

                 .digest(core_digest),
                 .digest_valid(core_digest_valid)
                );









  always @ (posedge clk)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          init_reg         <= 0;
          next_reg         <= 0;
          mode_reg         <= MODE_SHA3_256;
          ready_reg        <= 0;
          digest_reg       <= 512'h0;
          digest_valid_reg <= 0;
          for (i = 0 ; i < 32 ; i = i + 1)
            block_reg[i] = 32'h0;
        end
      else
        begin
          ready_reg        <= core_ready;
          digest_valid_reg <= core_digest_valid;
          init_reg         <= init_new;
          next_reg         <= next_new;

          if (mode_we)
            mode_reg <= write_data[3 : 2];

          if (core_digest_valid)
            digest_reg <= core_digest;

          if (block_we)
            block_reg[block_addr] <= write_data;
        end
    end








  always @*
    begin : api_logic
      init_new      = 0;
      next_new      = 0;
      mode_we       = 0;
      block_we      = 0;
      tmp_read_data = 32'h0;

      block_addr    = address - ADDR_BLOCK00;
      digest_addr   = 8'h10 - (address - ADDR_DIGEST00);

      if (cs)
        begin
          if (we)
            begin
              if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
                block_we = 1;

              case (address)

                ADDR_CTRL:
                  begin
                    init_new = write_data[CTRL_INIT_BIT];
                    next_new = write_data[CTRL_NEXT_BIT];
                    mode_we  = 1;
                  end

                default:
                  begin
                  end
              endcase
            end

          else
            begin
              if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
                tmp_read_data = block_reg[block_addr];


              if ((address >= ADDR_DIGEST00) && (address <= ADDR_DIGEST15))
                tmp_read_data = digest_reg[32 * digest_addr -: 32];

              case (address)

                ADDR_NAME0:
                  tmp_read_data = CORE_NAME0;

                ADDR_NAME1:
                  tmp_read_data = CORE_NAME1;

                ADDR_VERSION:
                  tmp_read_data = CORE_VERSION;

                ADDR_CTRL:
                  tmp_read_data = {28'h0, mode_reg, next_reg, init_reg};

                ADDR_STATUS:
                    tmp_read_data = {30'h0, digest_valid_reg, ready_reg};

                default:
                  begin
                  end
              endcase
            end
        end
    end
endmodule
module sha3(

            input wire           clk,
            input wire           reset_n,


            input wire           cs,
            input wire           we,


            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
            output wire [31 : 0] read_data
           );






  localparam ADDR_NAME0       = 8'h00;
  localparam ADDR_NAME1       = 8'h01;
  localparam ADDR_VERSION     = 8'h02;

  localparam ADDR_CTRL        = 8'h08;
  localparam CTRL_INIT_BIT    = 0;
  localparam CTRL_NEXT_BIT    = 1;

  localparam ADDR_STATUS      = 8'h09;
  localparam STATUS_READY_BIT = 0;
  localparam STATUS_VALID_BIT = 1;
  localparam STATUS_ERROR_BIT = 2;

  localparam ADDR_BLOCK00     = 8'h10;
  localparam ADDR_BLOCK31     = 8'h2f;

  localparam ADDR_DIGEST00    = 8'h40;
  localparam ADDR_DIGEST15    = 8'h4f;

  localparam CORE_NAME0       = 32'h7368612d;
  localparam CORE_NAME1       = 32'h33202020;
  localparam CORE_VERSION     = 32'h302e3130;

  localparam MODE_SHA3_224    = 2'h0;
  localparam MODE_SHA3_256    = 2'h1;
  localparam MODE_SHA3_384    = 2'h2;
  localparam MODE_SHA3_512    = 2'h3;





  reg init_reg;
  reg init_new;

  reg next_reg;
  reg next_new;

  reg [1 : 0] mode_reg;
  reg [1 : 0] mode_new;
  reg         mode_we;

  reg ready_reg;

  reg [31 : 0] block_reg [0 : 31];
  reg [4 : 0]  block_addr;
  reg          block_we;

  reg [511 : 0] digest_reg;
  reg [7 : 0]   digest_addr;
  reg           digest_valid_reg;





  wire            core_init;
  wire            core_next;
  wire [1 : 0]    core_mode;
  wire            core_work_factor;
  wire [31 : 0]   core_work_factor_num;
  wire            core_ready;
  wire [1023 : 0] core_block;
  wire [511 : 0]  core_digest;
  wire            core_digest_valid;

  reg [31 : 0]    tmp_read_data;





  assign core_init = init_reg;

  assign core_next = next_reg;

  assign core_mode = mode_reg;

  assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
                       block_reg[04], block_reg[04], block_reg[05], block_reg[07],
                       block_reg[08], block_reg[09], block_reg[10], block_reg[11],
                       block_reg[12], block_reg[13], block_reg[14], block_reg[15],
                       block_reg[16], block_reg[17], block_reg[18], block_reg[19],
                       block_reg[20], block_reg[21], block_reg[22], block_reg[23],
                       block_reg[24], block_reg[24], block_reg[25], block_reg[27],
                       block_reg[28], block_reg[29], block_reg[30], block_reg[31]};

  assign read_data = tmp_read_data;





  sha3_core core(
                 .clk(clk),
                 .reset_n(reset_n),

                 .init(core_init),
                 .next(core_next),
                 .mode(core_mode),

                 .block(core_block),

                 .ready(core_ready),

                 .digest(core_digest),
                 .digest_valid(core_digest_valid)
                );









  always @ (posedge clk)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          init_reg         <= 0;
          next_reg         <= 0;
          mode_reg         <= MODE_SHA3_256;
          ready_reg        <= 0;
          digest_reg       <= 512'h0;
          digest_valid_reg <= 0;
          for (i = 0 ; i < 32 ; i = i + 1)
            block_reg[i] = 32'h0;
        end
      else
        begin
          ready_reg        <= core_ready;
          digest_valid_reg <= core_digest_valid;
          init_reg         <= init_new;
          next_reg         <= next_new;

          if (mode_we)
            mode_reg <= write_data[3 : 2];

          if (core_digest_valid)
            digest_reg <= core_digest;

          if (block_we)
            block_reg[block_addr] <= write_data;
        end
    end








  always @*
    begin : api_logic
      init_new      = 0;
      next_new      = 0;
      mode_we       = 0;
      block_we      = 0;
      tmp_read_data = 32'h0;

      block_addr    = address - ADDR_BLOCK00;
      digest_addr   = 8'h10 - (address - ADDR_DIGEST00);

      if (cs)
        begin
          if (we)
            begin
              if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
                block_we = 1;

              case (address)

                ADDR_CTRL:
                  begin
                    init_new = write_data[CTRL_INIT_BIT];
                    next_new = write_data[CTRL_NEXT_BIT];
                    mode_we  = 1;
                  end

                default:
                  begin
                  end
              endcase
            end

          else
            begin
              if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
                tmp_read_data = block_reg[block_addr];


              if ((address >= ADDR_DIGEST00) && (address <= ADDR_DIGEST15))
                tmp_read_data = digest_reg[32 * digest_addr -: 32];

              case (address)

                ADDR_NAME0:
                  tmp_read_data = CORE_NAME0;

                ADDR_NAME1:
                  tmp_read_data = CORE_NAME1;

                ADDR_VERSION:
                  tmp_read_data = CORE_VERSION;

                ADDR_CTRL:
                  tmp_read_data = {28'h0, mode_reg, next_reg, init_reg};

                ADDR_STATUS:
                    tmp_read_data = {30'h0, digest_valid_reg, ready_reg};

                default:
                  begin
                  end
              endcase
            end
        end
    end
endmodule