data/full_repos/permissive/42178149/Test_FSM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42178149/Test_FSM.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42178149/Test_FSM.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42178149/Test_FSM.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n%Error: data/full_repos/permissive/42178149/Test_FSM.v:46: Cannot find file containing module: \'Gato_FSM\'\n Gato_FSM uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Gato_FSM\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Gato_FSM.v\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Gato_FSM.sv\n             Gato_FSM\n             Gato_FSM.v\n             Gato_FSM.sv\n             obj_dir/Gato_FSM\n             obj_dir/Gato_FSM.v\n             obj_dir/Gato_FSM.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_FSM;


	reg clk;
	reg reset;
	reg p1_mm;
	reg p2_mm;
	reg p1_tie;
	reg p1_loss;
	reg p1_win;
	reg p2_tie;
	reg p2_loss;
	reg p2_win;


	wire [2:0] state;
	wire verifica_status;
	wire turno_p1;
	wire turno_p2;


	Gato_FSM uut (
		.clk(clk), 
		.reset(reset), 
		.state(state), 
		.p1_mm(p1_mm), 
		.p2_mm(p2_mm), 
		.p1_tie(p1_tie), 
		.p1_loss(p1_loss), 
		.p1_win(p1_win), 
		.p2_tie(p2_tie), 
		.p2_loss(p2_loss), 
		.p2_win(p2_win), 
		.verifica_status(verifica_status), 
		.turno_p1(turno_p1), 
		.turno_p2(turno_p2)
	);
	
	always 
		#5 clk = ~clk;

	initial begin

		clk = 1;
		reset = 0;
		p1_mm = 0;
		p2_mm = 0;
		p1_tie = 0;
		p1_loss = 0;
		p1_win = 0;
		p2_tie = 0;
		p2_loss = 0;
		p2_win = 0;


		#10;
		p1_mm = 1'b1;
		
		#30;
		p2_mm = 1'b1;
		

        


	end
      
endmodule
module Test_FSM;



	reg clk;
	reg reset;
	reg p1_mm;
	reg p2_mm;
	reg p1_tie;
	reg p1_loss;
	reg p1_win;
	reg p2_tie;
	reg p2_loss;
	reg p2_win;


	wire [2:0] state;
	wire verifica_status;
	wire turno_p1;
	wire turno_p2;


	Gato_FSM uut (
		.clk(clk), 
		.reset(reset), 
		.state(state), 
		.p1_mm(p1_mm), 
		.p2_mm(p2_mm), 
		.p1_tie(p1_tie), 
		.p1_loss(p1_loss), 
		.p1_win(p1_win), 
		.p2_tie(p2_tie), 
		.p2_loss(p2_loss), 
		.p2_win(p2_win), 
		.verifica_status(verifica_status), 
		.turno_p1(turno_p1), 
		.turno_p2(turno_p2)
	);
	
	always 
		#5 clk = ~clk;

	initial begin

		clk = 1;
		reset = 0;
		p1_mm = 0;
		p2_mm = 0;
		p1_tie = 0;
		p1_loss = 0;
		p1_win = 0;
		p2_tie = 0;
		p2_loss = 0;
		p2_win = 0;


		#10;
		p1_mm = 1'b1;
		
		#30;
		p2_mm = 1'b1;
		

        


	end
      
endmodule