data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd/top_module.v
1: b"%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd/top_module.v:17: Cannot find file containing module: 'add16'\n  add16 a1 (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd,data/full_repos/permissive/500128826/add16\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd,data/full_repos/permissive/500128826/add16.v\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd,data/full_repos/permissive/500128826/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd/top_module.v:26: Cannot find file containing module: 'add16'\n  add16 a2a (\n  ^~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_cseladd/top_module.v:34: Cannot find file containing module: 'add16'\n  add16 a2b (\n  ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module (
    input  wire [31:0] a,
    input  wire [31:0] b,
    output wire [31:0] sum
);

  wire carry;
  add16 a1 (
      a[15:0],
      b[15:0],
      1'b0,
      sum[15:0],
      carry
  );

  wire [31:16] sum2a;
  add16 a2a (
      a[31:16],
      b[31:16],
      1'b0,
      sum2a,
  );

  wire [31:16] sum2b;
  add16 a2b (
      a[31:16],
      b[31:16],
      1'b1,
      sum2b,
  );

  assign sum[31:16] = (carry) ? sum2b : sum2a;

endmodule
module top_module (
    input  wire [31:0] a,
    input  wire [31:0] b,
    output wire [31:0] sum
);


  wire carry;
  add16 a1 (
      a[15:0],
      b[15:0],
      1'b0,
      sum[15:0],
      carry
  );

  wire [31:16] sum2a;
  add16 a2a (
      a[31:16],
      b[31:16],
      1'b0,
      sum2a,
  );

  wire [31:16] sum2b;
  add16 a2b (
      a[31:16],
      b[31:16],
      1'b1,
      sum2b,
  );

  assign sum[31:16] = (carry) ? sum2b : sum2a;

endmodule