data/full_repos/permissive/512700783/PC.v
data/verilator_xmls/83481fc0-56f2-44d5-aa02-ee8229962e66.xml
module PC(In, Out, Clk);
    	input [31:0] In;
    	input Clk;
    	output reg[31:0] Out;
		reg [31:0] PC = 0;
    	reg count = 0;
	always @(posedge Clk)
	begin
    		PC = In;
    		if (count == 0)	begin
        		Out = 0;
        		count = 1;
    		end
    		else begin
    			Out = PC;        
    		end
	end    
endmodule
module PC(In, Out, Clk);

    	input [31:0] In;
    	input Clk;
    	output reg[31:0] Out;
		reg [31:0] PC = 0;
    	reg count = 0;
	always @(posedge Clk)
	begin
    		PC = In;
    		if (count == 0)	begin
        		Out = 0;
        		count = 1;
    		end
    		else begin
    			Out = PC;        
    		end
	end    
endmodule