data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:187: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'CPU\'\nmodule CPU(\n       ^~~\n                                                                                    : ... Top module \'toRAMCollect\'\nmodule toRAMCollect(\n       ^~~~~~~~~~~~\n                                                                                    : ... Top module \'toMem\'\nmodule toMem(\n       ^~~~~\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:104: Cannot find file containing module: \'core\'\ncore QDP(.clk(clk),\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.v\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:147: Cannot find file containing module: \'memCont\'\nmemCont mCa(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:249: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance toMem\n if(status == 0) addrROM <= addrMemory[10:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:257: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                 : ... In instance toMem\n  if(addrMemory[12:11] == 2\'b10) addrRAM8 <= {1\'b1,addrMemory[10:0]};\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:258: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                 : ... In instance toMem\n  else addrRAM8 <= {addrMemory[10:0]};\n                ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module CPU(
	input clk,
	input clk_tim,
	input rst,
	
	input saverdy,
	input readrdy,
	
	output readstart,
	
	input irq1,
	input irq2,
	input irq3,
	input irq4,
	input irq5,
	input irq6,
	input irq7,
	
	input[15:0] in1,
	input[15:0] in2,

	
	output status,
	

	
	
	output[15:0] out1,
	output[15:0] out2,

	output workx,
	
	output prst,
	
	
	input[31:0] toCPU,
		
	output[14:0] addrCPU,
	output[31:0] fromCPU,
	output wCPU,
	
	output oover,
	
	output[1:0] outsel
);

wire brk;

wire[15:0] RAMaddr;
wire[15:0] toRAM;

wire w;
wire[15:0] fromRAM;

wire work;
	
wire[14:0] addr;
	
wire[24:0] dataProg;
	
wire cbrk;

wire prsts;

wire eirq;
wire irqx1;
wire irqx2;
wire irqx3;

wire[2:0] irq;
wire exception;

reg pexp;

always@(posedge clk)
	pexp <= 0;
	
irqcollector iCola(.clk(clk),
						 .rst(rst),
	
						.irq1(irq1),
						.irq2(irq2),
						.irq3(irq3),
						.irq4(irq4),
						.irq5(irq5),
						.irq6(irq6),
						.irq7(irq7),
						
						.irq(irq)
	
);

interCont iCo(.clk(clk),
				  .rst(rst),
	
				  .eirq(eirq),
				  .irq(irq),
	
					.irq1(irqx1),
					.irq2(irqx2),
					.irq3(irqx3)
);

core QDP(.clk(clk),
		   .clk_tim(clk_tim),
			.rst(rst),
			
			.eirq(eirq),
			
			.irq1(irqx1),
			.irq2(irqx2),
			.irq3(irqx3),
			
			.brk(brk),
			
			
			.in1(in1),
			.in2(in2),
			
			.exception(exception),
			.fromRAM(fromRAM),
			
			.exe(dataProg[24:20]),
			.ereg1(dataProg[19:18]),
			.ereg2(dataProg[17:16]),
			.edata(dataProg[15:0]),
			
			.out1(out1),
			.out2(out2),

			
			.addr(addr),
			
			.toRAM(toRAM),
			.RAMaddr(RAMaddr),
			.w(w),
			.status(status),
			
			.work(work),
			
			.outsel(outsel)
			
			
);

	
memCont mCa(
	.clk(clk),
	.rst(rst),
	.brk(brk),
	

	.toCPU(toCPU),
	
	.addr(addrCPU),
	.fromCPU(fromCPU),
	.wRAM(wCPU),
	

	
	.RAMaddr({RAMaddr}),
	.toRAM(toRAM),
	.w(w),
	
	.fromRAM(fromRAM),
	
	

	
	.addrPro(addr),
	.dataProg(dataProg),
	

	
	
	.readrdy(readrdy),
	.saverdy(saverdy),
	.readstart(readstart),
			
	.work(work)
);

assign workx = work;
assign prst = prsts;
endmodule
module CPU(
	input clk,
	input clk_tim,
	input rst,
	
	input saverdy,
	input readrdy,
	
	output readstart,
	
	input irq1,
	input irq2,
	input irq3,
	input irq4,
	input irq5,
	input irq6,
	input irq7,
	
	input[15:0] in1,
	input[15:0] in2,

	
	output status,
	

	
	
	output[15:0] out1,
	output[15:0] out2,

	output workx,
	
	output prst,
	
	
	input[31:0] toCPU,
		
	output[14:0] addrCPU,
	output[31:0] fromCPU,
	output wCPU,
	
	output oover,
	
	output[1:0] outsel
);


wire brk;

wire[15:0] RAMaddr;
wire[15:0] toRAM;

wire w;
wire[15:0] fromRAM;

wire work;
	
wire[14:0] addr;
	
wire[24:0] dataProg;
	
wire cbrk;

wire prsts;

wire eirq;
wire irqx1;
wire irqx2;
wire irqx3;

wire[2:0] irq;
wire exception;

reg pexp;

always@(posedge clk)
	pexp <= 0;
	
irqcollector iCola(.clk(clk),
						 .rst(rst),
	
						.irq1(irq1),
						.irq2(irq2),
						.irq3(irq3),
						.irq4(irq4),
						.irq5(irq5),
						.irq6(irq6),
						.irq7(irq7),
						
						.irq(irq)
	
);

interCont iCo(.clk(clk),
				  .rst(rst),
	
				  .eirq(eirq),
				  .irq(irq),
	
					.irq1(irqx1),
					.irq2(irqx2),
					.irq3(irqx3)
);

core QDP(.clk(clk),
		   .clk_tim(clk_tim),
			.rst(rst),
			
			.eirq(eirq),
			
			.irq1(irqx1),
			.irq2(irqx2),
			.irq3(irqx3),
			
			.brk(brk),
			
			
			.in1(in1),
			.in2(in2),
			
			.exception(exception),
			.fromRAM(fromRAM),
			
			.exe(dataProg[24:20]),
			.ereg1(dataProg[19:18]),
			.ereg2(dataProg[17:16]),
			.edata(dataProg[15:0]),
			
			.out1(out1),
			.out2(out2),

			
			.addr(addr),
			
			.toRAM(toRAM),
			.RAMaddr(RAMaddr),
			.w(w),
			.status(status),
			
			.work(work),
			
			.outsel(outsel)
			
			
);

	
memCont mCa(
	.clk(clk),
	.rst(rst),
	.brk(brk),
	

	.toCPU(toCPU),
	
	.addr(addrCPU),
	.fromCPU(fromCPU),
	.wRAM(wCPU),
	

	
	.RAMaddr({RAMaddr}),
	.toRAM(toRAM),
	.w(w),
	
	.fromRAM(fromRAM),
	
	

	
	.addrPro(addr),
	.dataProg(dataProg),
	

	
	
	.readrdy(readrdy),
	.saverdy(saverdy),
	.readstart(readstart),
			
	.work(work)
);

assign workx = work;
assign prst = prsts;
endmodule