data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/my_dff8.v
data/verilator_xmls/44df70b0-37d7-445c-8b69-6517e0c7c3ae.xml
module my_dff8 (
    input wire clk,
    input wire [7:0] d,
    output reg [7:0] q
);

  always @(posedge clk) begin
    q <= d;
  end

endmodule
module my_dff8 (
    input wire clk,
    input wire [7:0] d,
    output reg [7:0] q
);


  always @(posedge clk) begin
    q <= d;
  end

endmodule