data/full_repos/permissive/481044442/BDCDrv/upload_data.v
1: b"%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:48: Too many digits for 8 bit number: 8'h0x55\n    8'd100: begin tx_pulse<=1'b1; up_bytes<=8'h0x55; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:49: Too many digits for 8 bit number: 8'h0xaa\n    8'd120: begin tx_pulse<=1'b1; up_bytes<=8'h0xaa; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:50: Too many digits for 8 bit number: 8'h0x01\n    8'd140: begin tx_pulse<=1'b1; up_bytes<=8'h0x01; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:51: Too many digits for 8 bit number: 8'h0x02\n    8'd160: begin tx_pulse<=1'b1; up_bytes<=8'h0x02; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:52: Too many digits for 8 bit number: 8'h0x03\n    8'd180: begin tx_pulse<=1'b1; up_bytes<=8'h0x03; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:53: Too many digits for 8 bit number: 8'h0xff\n    8'd200: begin tx_pulse<=1'b1; up_bytes<=8'h0xff; end\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/upload_data.v:54: Too many digits for 8 bit number: 8'h0x00\n    default: begin tx_pulse<=1'b0; up_bytes<=8'h0x00; end\n                                             ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module upload_data(clk,reset,tx_pulse,up_bytes);
input clk;
input reset;

output reg tx_pulse;
output reg [7:0] up_bytes;



















reg [7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				counter<=8'd0;
			  end
	else begin
			if(counter==8'd220)
				counter<=8'd0;
			else
				counter<=counter+1'b1;
		 end
end

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				tx_pulse<=1'b0;
				up_bytes<=8'd0;
			  end
	else begin
			case(counter)
				8'd100: begin tx_pulse<=1'b1; up_bytes<=8'h0x55; end
				8'd120: begin tx_pulse<=1'b1; up_bytes<=8'h0xaa; end
				8'd140: begin tx_pulse<=1'b1; up_bytes<=8'h0x01; end
				8'd160: begin tx_pulse<=1'b1; up_bytes<=8'h0x02; end
				8'd180: begin tx_pulse<=1'b1; up_bytes<=8'h0x03; end
				8'd200: begin tx_pulse<=1'b1; up_bytes<=8'h0xff; end
				default: begin tx_pulse<=1'b0; up_bytes<=8'h0x00; end
			endcase
		 end
end
endmodule
module upload_data(clk,reset,tx_pulse,up_bytes);

input clk;
input reset;

output reg tx_pulse;
output reg [7:0] up_bytes;



















reg [7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				counter<=8'd0;
			  end
	else begin
			if(counter==8'd220)
				counter<=8'd0;
			else
				counter<=counter+1'b1;
		 end
end

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				tx_pulse<=1'b0;
				up_bytes<=8'd0;
			  end
	else begin
			case(counter)
				8'd100: begin tx_pulse<=1'b1; up_bytes<=8'h0x55; end
				8'd120: begin tx_pulse<=1'b1; up_bytes<=8'h0xaa; end
				8'd140: begin tx_pulse<=1'b1; up_bytes<=8'h0x01; end
				8'd160: begin tx_pulse<=1'b1; up_bytes<=8'h0x02; end
				8'd180: begin tx_pulse<=1'b1; up_bytes<=8'h0x03; end
				8'd200: begin tx_pulse<=1'b1; up_bytes<=8'h0xff; end
				default: begin tx_pulse<=1'b0; up_bytes<=8'h0x00; end
			endcase
		 end
end
endmodule