data/full_repos/permissive/445929378/decrypting_entity_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/decrypting_entity_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/decrypting_entity_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/decrypting_entity_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Error: data/full_repos/permissive/445929378/decrypting_entity_tb.v:32: Cannot find file containing module: \'decrypting_entity\'\n   decrypting_entity uut(\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/decrypting_entity\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/decrypting_entity.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/decrypting_entity.sv\n             decrypting_entity\n             decrypting_entity.v\n             decrypting_entity.sv\n             obj_dir/decrypting_entity\n             obj_dir/decrypting_entity.v\n             obj_dir/decrypting_entity.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decrypting_entity_tb #(parameter SIZE = 64);


   reg clk;
   reg rst;
   reg switch;
   reg [SIZE-1 : 0] p;
   reg 		    p_tvalid;
   reg [SIZE-1 : 0] alpha;
   reg 		    alpha_tvalid;


   wire [SIZE-1 : 0] p_out_tdata;
   wire 	     p_out_tvalid;
   reg 		     p_out_tready;
   
   wire [SIZE-1 : 0] alpha_out_tdata;
   wire 	     alpha_out_tvalid;   
   reg 		     alpha_out_tready;
   
   wire [SIZE-1 : 0] public_key;
   wire 	     public_key_tvalid;
   reg 		     public_key_tready;
   
   wire 	     output_tready;

   assign output_tready = p_out_tready & alpha_out_tready & public_key_tready;


   decrypting_entity uut(
			 .clk(clk), 
			 .rst(rst),
			 .switch(switch),
			 .input_first_tdata(p), 
			 .input_first_tvalid(p_tvalid), 

			 .input_second_tdata(alpha), 
			 .input_second_tvalid(alpha_tvalid), 

			 .output_a_tdata(p_out_tdata), 
			 .output_a_tvalid(p_out_tvalid), 
			 .output_a_tready(output_tready), 
			 .output_b_tdata(alpha_out_tdata), 
			 .output_b_tvalid(alpha_out_tvalid), 
			 .output_b_tready(output_tready),
			 .output_c_tdata(public_key), 
			 .output_c_tvalid(public_key_tvalid), 
			 .output_c_tready(output_tready)
			 );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;
      switch = 0;
      
      p = 64'd18446744073709551337;
      p_tvalid = 1;
      alpha = 64'd9223372036854775433;
      alpha_tvalid = 1;

      
      p_out_tready = 0;
      alpha_out_tready = 0;
      public_key_tready = 0;
      #5;
      p_out_tready = 1;
      alpha_out_tready = 1;
      public_key_tready = 1;
      
      

      #200;

      if(output_tready) begin
	 p = 64'd10794478246981970827;
	 p_tvalid = 1;
	 alpha = 64'd2422059422088052805;
	 alpha_tvalid = 1;
	 switch = 1;
      end
      


   end
   
endmodule
module decrypting_entity_tb #(parameter SIZE = 64);



   reg clk;
   reg rst;
   reg switch;
   reg [SIZE-1 : 0] p;
   reg 		    p_tvalid;
   reg [SIZE-1 : 0] alpha;
   reg 		    alpha_tvalid;


   wire [SIZE-1 : 0] p_out_tdata;
   wire 	     p_out_tvalid;
   reg 		     p_out_tready;
   
   wire [SIZE-1 : 0] alpha_out_tdata;
   wire 	     alpha_out_tvalid;   
   reg 		     alpha_out_tready;
   
   wire [SIZE-1 : 0] public_key;
   wire 	     public_key_tvalid;
   reg 		     public_key_tready;
   
   wire 	     output_tready;

   assign output_tready = p_out_tready & alpha_out_tready & public_key_tready;


   decrypting_entity uut(
			 .clk(clk), 
			 .rst(rst),
			 .switch(switch),
			 .input_first_tdata(p), 
			 .input_first_tvalid(p_tvalid), 

			 .input_second_tdata(alpha), 
			 .input_second_tvalid(alpha_tvalid), 

			 .output_a_tdata(p_out_tdata), 
			 .output_a_tvalid(p_out_tvalid), 
			 .output_a_tready(output_tready), 
			 .output_b_tdata(alpha_out_tdata), 
			 .output_b_tvalid(alpha_out_tvalid), 
			 .output_b_tready(output_tready),
			 .output_c_tdata(public_key), 
			 .output_c_tvalid(public_key_tvalid), 
			 .output_c_tready(output_tready)
			 );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;
      switch = 0;
      
      p = 64'd18446744073709551337;
      p_tvalid = 1;
      alpha = 64'd9223372036854775433;
      alpha_tvalid = 1;

      
      p_out_tready = 0;
      alpha_out_tready = 0;
      public_key_tready = 0;
      #5;
      p_out_tready = 1;
      alpha_out_tready = 1;
      public_key_tready = 1;
      
      

      #200;

      if(output_tready) begin
	 p = 64'd10794478246981970827;
	 p_tvalid = 1;
	 alpha = 64'd2422059422088052805;
	 alpha_tvalid = 1;
	 switch = 1;
      end
      


   end
   
endmodule