data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [DATA_WIDTH-1:0]  din,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output [DATA_WIDTH-1:0] dout,\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [DATA_WIDTH-1:0]    fifo_dout;\n        ^\n%Error: data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v:19: Cannot find file containing module: \'fifo\'\n   fifo\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/504677412/src/fifo,data/full_repos/permissive/504677412/fifo\n             data/full_repos/permissive/504677412/src/fifo,data/full_repos/permissive/504677412/fifo.v\n             data/full_repos/permissive/504677412/src/fifo,data/full_repos/permissive/504677412/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: data/full_repos/permissive/504677412/src/fifo/fifo_fwft.v:33: Cannot find file containing module: \'fifo_fwft_adapter\'\n   fifo_fwft_adapter\n   ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module fifo_fwft
  #(parameter DATA_WIDTH = 0,
    parameter DEPTH_WIDTH = 0)
   (
    input                   clk,
    input                   rst,
    input [DATA_WIDTH-1:0]  din,
    input                   wr_en,
    output                  full,
    output [DATA_WIDTH-1:0] dout,
    input                   rd_en,
    output                  empty);

   wire [DATA_WIDTH-1:0]    fifo_dout;
   wire                     fifo_empty;
   wire                     fifo_rd_en;


   fifo
     #(.DEPTH_WIDTH (DEPTH_WIDTH),
       .DATA_WIDTH  (DATA_WIDTH))
   fifo0
     (
      .clk       (clk),
      .rst       (rst),
      .rd_en_i   (fifo_rd_en),
      .rd_data_o (fifo_dout),
      .empty_o   (fifo_empty),
      .wr_en_i   (wr_en),
      .wr_data_i (din),
      .full_o    (full));

   fifo_fwft_adapter
     #(.DATA_WIDTH (DATA_WIDTH))
   fwft_adapter
     (.clk          (clk),
      .rst          (rst),
      .rd_en_i      (rd_en),
      .fifo_empty_i (fifo_empty),
      .fifo_rd_en_o (fifo_rd_en),
      .fifo_dout_i  (fifo_dout),
      .dout_o       (dout),
      .empty_o      (empty));

endmodule
module fifo_fwft
  #(parameter DATA_WIDTH = 0,
    parameter DEPTH_WIDTH = 0)
   (
    input                   clk,
    input                   rst,
    input [DATA_WIDTH-1:0]  din,
    input                   wr_en,
    output                  full,
    output [DATA_WIDTH-1:0] dout,
    input                   rd_en,
    output                  empty);


   wire [DATA_WIDTH-1:0]    fifo_dout;
   wire                     fifo_empty;
   wire                     fifo_rd_en;


   fifo
     #(.DEPTH_WIDTH (DEPTH_WIDTH),
       .DATA_WIDTH  (DATA_WIDTH))
   fifo0
     (
      .clk       (clk),
      .rst       (rst),
      .rd_en_i   (fifo_rd_en),
      .rd_data_o (fifo_dout),
      .empty_o   (fifo_empty),
      .wr_en_i   (wr_en),
      .wr_data_i (din),
      .full_o    (full));

   fifo_fwft_adapter
     #(.DATA_WIDTH (DATA_WIDTH))
   fwft_adapter
     (.clk          (clk),
      .rst          (rst),
      .rd_en_i      (rd_en),
      .fifo_empty_i (fifo_empty),
      .fifo_rd_en_o (fifo_rd_en),
      .fifo_dout_i  (fifo_dout),
      .dout_o       (dout),
      .empty_o      (empty));

endmodule