data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:77: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_gpio,data/full_repos/permissive/504248338/uprj_netlists.v\n             data/full_repos/permissive/504248338/verilog/dv/user_gpio,data/full_repos/permissive/504248338/uprj_netlists.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_gpio,data/full_repos/permissive/504248338/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:78: Cannot find include file: is62wvs1288.v\n`include "is62wvs1288.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:79: Cannot find include file: user_reg_map.v\n`include "user_reg_map.v" \n         ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:143: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:146: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:152: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:158: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_CFG0,\'h01F);\n                                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:158: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_CFG0,\'h01F);\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:161: Define or directive not defined: \'`PINMUX_GBL_CFG1\'\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_CFG1,39);\n                                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:161: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_CFG1,39);\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:164: Define or directive not defined: \'`PINMUX_GBL_INTR_MSK\'\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_INTR_MSK,\'h8000);\n                                                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:164: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(32\'h3002_0000+`PINMUX_GBL_INTR_MSK,\'h8000);\n                                                                     ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:167: syntax error, unexpected \'@\'\n         repeat (200) @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:170: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clock);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:281: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:282: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:289: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:290: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:291: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:299: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:308: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:316: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:317: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:319: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:320: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:328: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:338: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:339: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:346: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:347: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:349: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:350: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_gpio/user_gpio_tb.v:363: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 28 error(s), 10 warning(s)\n'
module user_gpio_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
        integer    test_step;
        wire       clock_mon;






	always #12.5 clock <= (clock === 1'b0);


	initial begin
		OneUsPeriod = 1;
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, `TB_GLBL);
	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write('h3080_0000,'h1);

	        repeat (2) @(posedge clock);
		#1;
                wb_user_core_write('h3080_0004,'h10);



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h8000);

		test_fail = 0;
	        repeat (200) @(posedge clock);


		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: GPIO Mode (GL) Passed");
		   `else
		       $display("Monitor: GPIO Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: GPIO Mode (GL) Failed");
		    `else
		        $display("Monitor: GPIO Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    





   wire flash_io1;
   wire flash_clk = io_out[16];
   wire spiram_csb = io_out[13];
   tri  #1 flash_io0 = io_out[15];
   assign io_in[14] = flash_io1;

   tri  #1 flash_io2 = 1'b1;
   tri  #1 flash_io3 = 1'b1;


   is62wvs1288 #(.mem_file_name("flash1.hex"))
	u_sfram (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );





task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     `TB_GLBL.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask



























task gen_gpio_out;
input  [31:0] datain;
output [7:0] port_a_out;
output [7:0] port_b_out;
output [7:0] port_c_out;
output [7:0] port_d_out;

reg [7:0] port_a_out;
reg [7:0] port_b_out;
reg [7:0] port_c_out;
reg [7:0] port_d_out;
begin
    port_a_out ='h0;
    port_b_out ='h0;
    port_c_out ='h0;
    port_d_out ='h0;

    port_c_out[6] =  datain[0];
    port_d_out[0] =  datain[1];
    port_d_out[1] =  datain[2];
    port_d_out[2] =  datain[3];
    port_d_out[3] =  datain[4];
    port_d_out[4] =  datain[5];
    port_b_out[6] =  datain[6];
    port_b_out[7] =  datain[7];
    port_d_out[5] =  datain[8];
    port_d_out[6] =  datain[9];
    port_d_out[7] =  datain[10];
    port_b_out[0] =  datain[11];
    port_b_out[1] =  datain[12];
    port_b_out[2] =  datain[13];
    port_b_out[3] =  datain[14];
    port_b_out[4] =  datain[15];
    port_b_out[5] =  datain[16];
    port_c_out[0] =  datain[18];
    port_c_out[1] =  datain[19];
    port_c_out[2] =  datain[20];
    port_c_out[3] =  datain[21];
    port_c_out[4] =  datain[22];
    port_c_out[5] =  datain[23];
end
endtask


task exp_gpio_in;
output [7:0] port_a_in;
output [7:0] port_b_in;
output [7:0] port_c_in;
output [7:0] port_d_in;
reg [7:0] port_a_in;
reg [7:0] port_b_in;
reg [7:0] port_c_in;
reg [7:0] port_d_in;
begin
    port_a_in ='h0;
    port_b_in ='h0;
    port_c_in ='h0;
    port_d_in ='h0;
    
    port_c_in[6] =  io_out[0];
    port_d_in[0] =  io_out[1];
    port_d_in[1] =  io_out[2];
    port_d_in[2] =  io_out[3];
    port_d_in[3] =  io_out[4];
    port_d_in[4] =  io_out[5];
    port_b_in[6] =  io_out[6];
    port_b_in[7] =  io_out[7];
    port_d_in[5] =  io_out[8];
    port_d_in[6] =  io_out[9];
    port_d_in[7] =  io_out[10];
    port_b_in[0] =  io_out[11];
    port_b_in[1] =  io_out[12];
    port_b_in[2] =  io_out[13];
    port_b_in[3] =  io_out[14];
    port_b_in[4] =  io_out[15];
    port_b_in[5] =  io_out[16];
    port_c_in[0] =  io_out[18];
    port_c_in[1] =  io_out[19];
    port_c_in[2] =  io_out[20];
    port_c_in[3] =  io_out[21];
    port_c_in[4] =  io_out[22];
    port_c_in[5] =  io_out[23];
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif



endmodule
module user_gpio_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
        integer    test_step;
        wire       clock_mon;






	always #12.5 clock <= (clock === 1'b0);


	initial begin
		OneUsPeriod = 1;
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, `TB_GLBL);
	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write('h3080_0000,'h1);

	        repeat (2) @(posedge clock);
		#1;
                wb_user_core_write('h3080_0004,'h10);



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h8000);

		test_fail = 0;
	        repeat (200) @(posedge clock);


		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: GPIO Mode (GL) Passed");
		   `else
		       $display("Monitor: GPIO Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: GPIO Mode (GL) Failed");
		    `else
		        $display("Monitor: GPIO Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    





   wire flash_io1;
   wire flash_clk = io_out[16];
   wire spiram_csb = io_out[13];
   tri  #1 flash_io0 = io_out[15];
   assign io_in[14] = flash_io1;

   tri  #1 flash_io2 = 1'b1;
   tri  #1 flash_io3 = 1'b1;


   is62wvs1288 #(.mem_file_name("flash1.hex"))
	u_sfram (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );





task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     `TB_GLBL.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask



























task gen_gpio_out;
input  [31:0] datain;
output [7:0] port_a_out;
output [7:0] port_b_out;
output [7:0] port_c_out;
output [7:0] port_d_out;

reg [7:0] port_a_out;
reg [7:0] port_b_out;
reg [7:0] port_c_out;
reg [7:0] port_d_out;
begin
    port_a_out ='h0;
    port_b_out ='h0;
    port_c_out ='h0;
    port_d_out ='h0;

    port_c_out[6] =  datain[0];
    port_d_out[0] =  datain[1];
    port_d_out[1] =  datain[2];
    port_d_out[2] =  datain[3];
    port_d_out[3] =  datain[4];
    port_d_out[4] =  datain[5];
    port_b_out[6] =  datain[6];
    port_b_out[7] =  datain[7];
    port_d_out[5] =  datain[8];
    port_d_out[6] =  datain[9];
    port_d_out[7] =  datain[10];
    port_b_out[0] =  datain[11];
    port_b_out[1] =  datain[12];
    port_b_out[2] =  datain[13];
    port_b_out[3] =  datain[14];
    port_b_out[4] =  datain[15];
    port_b_out[5] =  datain[16];
    port_c_out[0] =  datain[18];
    port_c_out[1] =  datain[19];
    port_c_out[2] =  datain[20];
    port_c_out[3] =  datain[21];
    port_c_out[4] =  datain[22];
    port_c_out[5] =  datain[23];
end
endtask


task exp_gpio_in;
output [7:0] port_a_in;
output [7:0] port_b_in;
output [7:0] port_c_in;
output [7:0] port_d_in;
reg [7:0] port_a_in;
reg [7:0] port_b_in;
reg [7:0] port_c_in;
reg [7:0] port_d_in;
begin
    port_a_in ='h0;
    port_b_in ='h0;
    port_c_in ='h0;
    port_d_in ='h0;
    
    port_c_in[6] =  io_out[0];
    port_d_in[0] =  io_out[1];
    port_d_in[1] =  io_out[2];
    port_d_in[2] =  io_out[3];
    port_d_in[3] =  io_out[4];
    port_d_in[4] =  io_out[5];
    port_b_in[6] =  io_out[6];
    port_b_in[7] =  io_out[7];
    port_d_in[5] =  io_out[8];
    port_d_in[6] =  io_out[9];
    port_d_in[7] =  io_out[10];
    port_b_in[0] =  io_out[11];
    port_b_in[1] =  io_out[12];
    port_b_in[2] =  io_out[13];
    port_b_in[3] =  io_out[14];
    port_b_in[4] =  io_out[15];
    port_b_in[5] =  io_out[16];
    port_c_in[0] =  io_out[18];
    port_c_in[1] =  io_out[19];
    port_c_in[2] =  io_out[20];
    port_c_in[3] =  io_out[21];
    port_c_in[4] =  io_out[22];
    port_c_in[5] =  io_out[23];
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif



endmodule