data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:59: Define or directive not defined: '`MPRJ_IO_PADS'\n  input  [`MPRJ_IO_PADS-1:0] io_in      ,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:60: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_out     ,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:61: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_oeb     ,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:98: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_in ;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:99: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_out;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:100: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_oeb;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:149: Unsupported: SystemVerilog 2012 reserved word not implemented: 'interconnect'\n  wb_interconnect interconnect (\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:154: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk_i      (wb_clk_i   ),\n    ^\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:247: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign io_oeb = {(`MPRJ_IO_PADS){1'b0}};\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472671476/verilog/rtl/user_proj_example.v:247: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n  assign io_oeb = {(`MPRJ_IO_PADS){1'b0}};\n                                 ^\n%Error: Exiting due to 10 error(s)\n"
module user_proj_example #(parameter BITS = 32) (
`ifdef USE_POWER_PINS
  inout                      vccd1      ,
  inout                      vssd1      ,
`endif

  input                      wb_clk_i   ,
  input                      wb_rst_i   ,
  input                      wbs_stb_i  ,
  input                      wbs_cyc_i  ,
  input                      wbs_we_i   ,
  input  [              3:0] wbs_sel_i  ,
  input  [             31:0] wbs_dat_i  ,
  input  [             31:0] wbs_adr_i  ,
  output                     wbs_ack_o  ,
  output [             31:0] wbs_dat_o  ,

  input  [            127:0] la_data_in ,
  output [            127:0] la_data_out,
  input  [            127:0] la_oenb    ,

  input  [`MPRJ_IO_PADS-1:0] io_in      ,
  output [`MPRJ_IO_PADS-1:0] io_out     ,
  output [`MPRJ_IO_PADS-1:0] io_oeb     ,

  output [              2:0] irq        ,

  output                     sram_csb_a ,
  output [              8:0] sram_addr_a,
  input  [             31:0] sram_dout_a,

  output                     sram_csb_b ,
  output                     sram_web_b ,
  output [              3:0] sram_mask_b,
  output [              8:0] sram_addr_b,
  output [             31:0] sram_din_b,

  output        trng_wb_cyc_o, 
  output        trng_wb_stb_o,
  output [8:0]  trng_wb_adr_o,
  output        trng_wb_we_o ,
  input  [31:0] trng_wb_dat_i,
  output [31:0] trng_wb_dat_o,
  input         trng_wb_ack_i,
  input  [31:0] trng_buffer_i

);




  localparam WB_WIDTH     = 32;
  localparam SRAM_ADDR_WD = 9 ;
  localparam SRAM_DATA_WD = 32;
  localparam UART_ADDR_WD = 2 ;
  localparam UART_DATA_WD = 32;




  wire [`MPRJ_IO_PADS-1:0] io_in ;
  wire [`MPRJ_IO_PADS-1:0] io_out;
  wire [`MPRJ_IO_PADS-1:0] io_oeb;




  wire                      s0_wb_cyc_i;
  wire                      s0_wb_stb_i;
  wire [  SRAM_ADDR_WD-1:0] s0_wb_adr_i;
  wire                      s0_wb_we_i ;
  wire [  SRAM_DATA_WD-1:0] s0_wb_dat_i;
  wire [SRAM_DATA_WD/8-1:0] s0_wb_sel_i;
  wire [  SRAM_DATA_WD-1:0] s0_wb_dat_o;
  wire                      s0_wb_ack_o;





  wire                      s1_wb_cyc_i;
  wire                      s1_wb_stb_i;
  wire [               8:0] s1_wb_adr_o;
  wire                      s1_wb_we_i ;
  wire [WB_WIDTH-1:0] s1_wb_dat_i;
  wire [WB_WIDTH/8-1:0] s1_wb_sel_i;
  wire [WB_WIDTH-1:0] s1_wb_dat_o;
  wire                      s1_wb_ack_o;




  wire                s3_wb_cyc_i;
  wire                s3_wb_stb_i;
  wire [         8:0] s3_wb_adr_o;
  wire                s3_wb_we_i ;
  wire [WB_WIDTH-1:0] s3_wb_dat_i;

  wire [WB_WIDTH-1:0] s3_wb_dat_o;
  wire                s3_wb_ack_o;


  wire alarm;
  wire alarm_set;
  wire master_key_ready;
  wire [31:0] o_LFSR_Data;

  wire [31:0] trng_i = 32'd0;



  wb_interconnect interconnect (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .clk_i      (wb_clk_i   ),
    .rst        (wb_rst_i   ),
    

    .m0_wb_dat_i(wbs_dat_i  ),
    .m0_wb_adr_i(wbs_adr_i  ),
    .m0_wb_sel_i(wbs_sel_i  ),
    .m0_wb_we_i (wbs_we_i   ),
    .m0_wb_cyc_i(wbs_cyc_i  ),
    .m0_wb_stb_i(wbs_stb_i  ),
    .m0_wb_dat_o(wbs_dat_o  ),
    .m0_wb_ack_o(wbs_ack_o  ),
    

    .s0_wb_dat_i(s0_wb_dat_o),
    .s0_wb_ack_i(s0_wb_ack_o),
    .s0_wb_dat_o(s0_wb_dat_i),
    .s0_wb_adr_o(s0_wb_adr_i),
    .s0_wb_sel_o(s0_wb_sel_i),
    .s0_wb_we_o (s0_wb_we_i ),
    .s0_wb_cyc_o(s0_wb_cyc_i),
    .s0_wb_stb_o(s0_wb_stb_i),
    

    .s1_wb_dat_i(s1_wb_dat_o),
    .s1_wb_ack_i(s1_wb_ack_o),
    .s1_wb_dat_o(s1_wb_dat_i),
    .s1_wb_adr_o(s1_wb_adr_o),
    .s1_wb_sel_o(s1_wb_sel_i),
    .s1_wb_we_o (s1_wb_we_i ),
    .s1_wb_cyc_o(s1_wb_cyc_i),
    .s1_wb_stb_o(s1_wb_stb_i),
    

    .s2_wb_dat_i(trng_wb_dat_i),
    .s2_wb_ack_i(trng_wb_ack_i),
    .s2_wb_dat_o(trng_wb_dat_o),
    .s2_wb_adr_o(trng_wb_adr_o),
    .s2_wb_sel_o(),
    .s2_wb_we_o (trng_wb_we_o),
    .s2_wb_cyc_o(trng_wb_cyc_o),
    .s2_wb_stb_o(trng_wb_stb_o),
    

    .s3_wb_dat_i(s3_wb_dat_o),
    .s3_wb_ack_i(s3_wb_ack_o),
    .s3_wb_dat_o(s3_wb_dat_i),
    .s3_wb_adr_o(s3_wb_adr_o),
    .s3_wb_sel_o(),
    .s3_wb_we_o (s3_wb_we_i ),
    .s3_wb_cyc_o(s3_wb_cyc_i),
    .s3_wb_stb_o(s3_wb_stb_i)
  );


  sram_wb_wrapper #(
    `ifndef SYNTHESIS
    .SRAM_ADDR_WD(SRAM_ADDR_WD),
    .SRAM_DATA_WD(SRAM_DATA_WD)
    `endif
  ) wb_wrapper0 (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .rst        (wb_rst_i   ),

    .wb_clk_i   (wb_clk_i   ),
    .wb_cyc_i   (s0_wb_cyc_i),
    .wb_stb_i   (s0_wb_stb_i),
    .wb_adr_i   (s0_wb_adr_i),
    .wb_we_i    (s0_wb_we_i ),
    .wb_dat_i   (s0_wb_dat_i),
    .wb_sel_i   (s0_wb_sel_i),
    .wb_dat_o   (s0_wb_dat_o),
    .wb_ack_o   (s0_wb_ack_o),


    .sram_csb_a (sram_csb_a ),
    .sram_addr_a(sram_addr_a),
    .sram_dout_a (sram_dout_a),

    .sram_csb_b (sram_csb_b ),
    .sram_web_b (sram_web_b ),
    .sram_mask_b(sram_mask_b),
    .sram_addr_b(sram_addr_b),
    .sram_din_b (sram_din_b ),
    .trng_i(trng_buffer_i),
    .alarm(alarm),
    .master_key_ready(master_key_ready),
    .alarm_set(alarm_set)
  );

  assign io_oeb = {(`MPRJ_IO_PADS){1'b0}};

  

  simpleuartA_wb   
  simpleuartA_wb_dut (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .wb_clk_i (wb_clk_i ),
    .wb_rst_i (wb_rst_i ),
    .wb_adr_i (s1_wb_adr_o[1:0]),
    .wb_dat_i (s1_wb_dat_i ),
    .wb_sel_i (s1_wb_sel_i ),
    .wb_we_i  (s1_wb_we_i ),
    .wb_cyc_i (s1_wb_cyc_i ),
    .wb_stb_i (s1_wb_stb_i ),
    .wb_ack_o (s1_wb_ack_o ),
    .wb_dat_o (s1_wb_dat_o ),
    .uart_enabled ( ),
    .ser_tx (io_out[16] ),
    .ser_rx  (io_in[15])
  );


  assign io_out[18] = o_LFSR_Data[0];

  LFSR 
  #(
    .NUM_BITS (32)
  )
  LFSR_dut (
    .i_Clk (wb_clk_i ),
    .i_Enable (1'b1 ),
    .i_alarm_set (alarm_set),
    .i_Seed_DV (trng_wb_cyc_o),
    .i_Seed_Data (trng_buffer_i ),
    .o_LFSR_Data (o_LFSR_Data ),
    .o_LFSR_Done  (),
    .i_LFSR ( io_in[17]),
    .master_key_ready(master_key_ready),
    .i_rst(wb_rst_i),
    .o_alarm(alarm)
  );




  tiny_spi #(
    .BAUD_WIDTH(0),
    .BAUD_DIV  (8),
    .SPI_MODE  (0),
    .BC_WIDTH  (3),
    .DIV_WIDTH (2),
    .IDLE      (0)
  ) tiny_spi_inst (
    `ifdef USE_POWER_PINS
    .vccd1(vccd1           ),
    .vssd1(vssd1           ),
    `endif
    .rst_i(wb_rst_i        ),
    .clk_i(wb_clk_i        ),
    .stb_i(s3_wb_stb_i     ),
    .we_i (s3_wb_we_i      ),
    .dat_o(s3_wb_dat_o     ),
    .dat_i(s3_wb_dat_i     ),
    .int_o(                ),
    .adr_i(s3_wb_adr_o[2:0]),
    .cyc_i(s3_wb_cyc_i     ),
    .ack_o(s3_wb_ack_o     ),
    .MOSI (io_out[12]      ),
    .SCLK (io_out[13]      ),
    .MISO (io_in[14]       )
  );


endmodule
module user_proj_example #(parameter BITS = 32) (
`ifdef USE_POWER_PINS
  inout                      vccd1      ,
  inout                      vssd1      ,
`endif

  input                      wb_clk_i   ,
  input                      wb_rst_i   ,
  input                      wbs_stb_i  ,
  input                      wbs_cyc_i  ,
  input                      wbs_we_i   ,
  input  [              3:0] wbs_sel_i  ,
  input  [             31:0] wbs_dat_i  ,
  input  [             31:0] wbs_adr_i  ,
  output                     wbs_ack_o  ,
  output [             31:0] wbs_dat_o  ,

  input  [            127:0] la_data_in ,
  output [            127:0] la_data_out,
  input  [            127:0] la_oenb    ,

  input  [`MPRJ_IO_PADS-1:0] io_in      ,
  output [`MPRJ_IO_PADS-1:0] io_out     ,
  output [`MPRJ_IO_PADS-1:0] io_oeb     ,

  output [              2:0] irq        ,

  output                     sram_csb_a ,
  output [              8:0] sram_addr_a,
  input  [             31:0] sram_dout_a,

  output                     sram_csb_b ,
  output                     sram_web_b ,
  output [              3:0] sram_mask_b,
  output [              8:0] sram_addr_b,
  output [             31:0] sram_din_b,

  output        trng_wb_cyc_o, 
  output        trng_wb_stb_o,
  output [8:0]  trng_wb_adr_o,
  output        trng_wb_we_o ,
  input  [31:0] trng_wb_dat_i,
  output [31:0] trng_wb_dat_o,
  input         trng_wb_ack_i,
  input  [31:0] trng_buffer_i

);





  localparam WB_WIDTH     = 32;
  localparam SRAM_ADDR_WD = 9 ;
  localparam SRAM_DATA_WD = 32;
  localparam UART_ADDR_WD = 2 ;
  localparam UART_DATA_WD = 32;




  wire [`MPRJ_IO_PADS-1:0] io_in ;
  wire [`MPRJ_IO_PADS-1:0] io_out;
  wire [`MPRJ_IO_PADS-1:0] io_oeb;




  wire                      s0_wb_cyc_i;
  wire                      s0_wb_stb_i;
  wire [  SRAM_ADDR_WD-1:0] s0_wb_adr_i;
  wire                      s0_wb_we_i ;
  wire [  SRAM_DATA_WD-1:0] s0_wb_dat_i;
  wire [SRAM_DATA_WD/8-1:0] s0_wb_sel_i;
  wire [  SRAM_DATA_WD-1:0] s0_wb_dat_o;
  wire                      s0_wb_ack_o;





  wire                      s1_wb_cyc_i;
  wire                      s1_wb_stb_i;
  wire [               8:0] s1_wb_adr_o;
  wire                      s1_wb_we_i ;
  wire [WB_WIDTH-1:0] s1_wb_dat_i;
  wire [WB_WIDTH/8-1:0] s1_wb_sel_i;
  wire [WB_WIDTH-1:0] s1_wb_dat_o;
  wire                      s1_wb_ack_o;




  wire                s3_wb_cyc_i;
  wire                s3_wb_stb_i;
  wire [         8:0] s3_wb_adr_o;
  wire                s3_wb_we_i ;
  wire [WB_WIDTH-1:0] s3_wb_dat_i;

  wire [WB_WIDTH-1:0] s3_wb_dat_o;
  wire                s3_wb_ack_o;


  wire alarm;
  wire alarm_set;
  wire master_key_ready;
  wire [31:0] o_LFSR_Data;

  wire [31:0] trng_i = 32'd0;



  wb_interconnect interconnect (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .clk_i      (wb_clk_i   ),
    .rst        (wb_rst_i   ),
    

    .m0_wb_dat_i(wbs_dat_i  ),
    .m0_wb_adr_i(wbs_adr_i  ),
    .m0_wb_sel_i(wbs_sel_i  ),
    .m0_wb_we_i (wbs_we_i   ),
    .m0_wb_cyc_i(wbs_cyc_i  ),
    .m0_wb_stb_i(wbs_stb_i  ),
    .m0_wb_dat_o(wbs_dat_o  ),
    .m0_wb_ack_o(wbs_ack_o  ),
    

    .s0_wb_dat_i(s0_wb_dat_o),
    .s0_wb_ack_i(s0_wb_ack_o),
    .s0_wb_dat_o(s0_wb_dat_i),
    .s0_wb_adr_o(s0_wb_adr_i),
    .s0_wb_sel_o(s0_wb_sel_i),
    .s0_wb_we_o (s0_wb_we_i ),
    .s0_wb_cyc_o(s0_wb_cyc_i),
    .s0_wb_stb_o(s0_wb_stb_i),
    

    .s1_wb_dat_i(s1_wb_dat_o),
    .s1_wb_ack_i(s1_wb_ack_o),
    .s1_wb_dat_o(s1_wb_dat_i),
    .s1_wb_adr_o(s1_wb_adr_o),
    .s1_wb_sel_o(s1_wb_sel_i),
    .s1_wb_we_o (s1_wb_we_i ),
    .s1_wb_cyc_o(s1_wb_cyc_i),
    .s1_wb_stb_o(s1_wb_stb_i),
    

    .s2_wb_dat_i(trng_wb_dat_i),
    .s2_wb_ack_i(trng_wb_ack_i),
    .s2_wb_dat_o(trng_wb_dat_o),
    .s2_wb_adr_o(trng_wb_adr_o),
    .s2_wb_sel_o(),
    .s2_wb_we_o (trng_wb_we_o),
    .s2_wb_cyc_o(trng_wb_cyc_o),
    .s2_wb_stb_o(trng_wb_stb_o),
    

    .s3_wb_dat_i(s3_wb_dat_o),
    .s3_wb_ack_i(s3_wb_ack_o),
    .s3_wb_dat_o(s3_wb_dat_i),
    .s3_wb_adr_o(s3_wb_adr_o),
    .s3_wb_sel_o(),
    .s3_wb_we_o (s3_wb_we_i ),
    .s3_wb_cyc_o(s3_wb_cyc_i),
    .s3_wb_stb_o(s3_wb_stb_i)
  );


  sram_wb_wrapper #(
    `ifndef SYNTHESIS
    .SRAM_ADDR_WD(SRAM_ADDR_WD),
    .SRAM_DATA_WD(SRAM_DATA_WD)
    `endif
  ) wb_wrapper0 (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .rst        (wb_rst_i   ),

    .wb_clk_i   (wb_clk_i   ),
    .wb_cyc_i   (s0_wb_cyc_i),
    .wb_stb_i   (s0_wb_stb_i),
    .wb_adr_i   (s0_wb_adr_i),
    .wb_we_i    (s0_wb_we_i ),
    .wb_dat_i   (s0_wb_dat_i),
    .wb_sel_i   (s0_wb_sel_i),
    .wb_dat_o   (s0_wb_dat_o),
    .wb_ack_o   (s0_wb_ack_o),


    .sram_csb_a (sram_csb_a ),
    .sram_addr_a(sram_addr_a),
    .sram_dout_a (sram_dout_a),

    .sram_csb_b (sram_csb_b ),
    .sram_web_b (sram_web_b ),
    .sram_mask_b(sram_mask_b),
    .sram_addr_b(sram_addr_b),
    .sram_din_b (sram_din_b ),
    .trng_i(trng_buffer_i),
    .alarm(alarm),
    .master_key_ready(master_key_ready),
    .alarm_set(alarm_set)
  );

  assign io_oeb = {(`MPRJ_IO_PADS){1'b0}};

  

  simpleuartA_wb   
  simpleuartA_wb_dut (
    `ifdef USE_POWER_PINS
    .vccd1      (vccd1      ),
    .vssd1      (vssd1      ),
    `endif
    .wb_clk_i (wb_clk_i ),
    .wb_rst_i (wb_rst_i ),
    .wb_adr_i (s1_wb_adr_o[1:0]),
    .wb_dat_i (s1_wb_dat_i ),
    .wb_sel_i (s1_wb_sel_i ),
    .wb_we_i  (s1_wb_we_i ),
    .wb_cyc_i (s1_wb_cyc_i ),
    .wb_stb_i (s1_wb_stb_i ),
    .wb_ack_o (s1_wb_ack_o ),
    .wb_dat_o (s1_wb_dat_o ),
    .uart_enabled ( ),
    .ser_tx (io_out[16] ),
    .ser_rx  (io_in[15])
  );


  assign io_out[18] = o_LFSR_Data[0];

  LFSR 
  #(
    .NUM_BITS (32)
  )
  LFSR_dut (
    .i_Clk (wb_clk_i ),
    .i_Enable (1'b1 ),
    .i_alarm_set (alarm_set),
    .i_Seed_DV (trng_wb_cyc_o),
    .i_Seed_Data (trng_buffer_i ),
    .o_LFSR_Data (o_LFSR_Data ),
    .o_LFSR_Done  (),
    .i_LFSR ( io_in[17]),
    .master_key_ready(master_key_ready),
    .i_rst(wb_rst_i),
    .o_alarm(alarm)
  );




  tiny_spi #(
    .BAUD_WIDTH(0),
    .BAUD_DIV  (8),
    .SPI_MODE  (0),
    .BC_WIDTH  (3),
    .DIV_WIDTH (2),
    .IDLE      (0)
  ) tiny_spi_inst (
    `ifdef USE_POWER_PINS
    .vccd1(vccd1           ),
    .vssd1(vssd1           ),
    `endif
    .rst_i(wb_rst_i        ),
    .clk_i(wb_clk_i        ),
    .stb_i(s3_wb_stb_i     ),
    .we_i (s3_wb_we_i      ),
    .dat_o(s3_wb_dat_o     ),
    .dat_i(s3_wb_dat_i     ),
    .int_o(                ),
    .adr_i(s3_wb_adr_o[2:0]),
    .cyc_i(s3_wb_cyc_i     ),
    .ack_o(s3_wb_ack_o     ),
    .MOSI (io_out[12]      ),
    .SCLK (io_out[13]      ),
    .MISO (io_in[14]       )
  );


endmodule