data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/SPGD/LFSR.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/SPGD/LFSR.v:12: syntax error, unexpected rand, expecting IDENTIFIER or '=' or do or final\nreg [REG_WIDTH - 1:0] rand = SEED;\n                      ^~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/SPGD/LFSR.v:15: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\nassign feedback = !(rand[3] ^ rand[0]);\n                    ^~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/SPGD/LFSR.v:19: syntax error, unexpected rand\n  rand <= SEED;\n  ^~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/SPGD/LFSR.v:23: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\nassign random = rand[OUT_WIDTH - 1:0];\n                ^~~~\n%Error: Exiting due to 4 error(s)\n"
module LFSR
#(
	parameter REG_WIDTH = 31,
	parameter OUT_WIDTH = 11,
	parameter SEED = 24218329
)
(
	input wire clk,
	input wire rst,
	output wire [OUT_WIDTH - 1:0] random
);
reg [REG_WIDTH - 1:0] rand = SEED;
wire feedback;

assign feedback = !(rand[3] ^ rand[0]);

always @(posedge clk)
	if (rst)
		rand <= SEED;
	else
		rand <= {feedback, rand[REG_WIDTH - 1:1]};

assign random = rand[OUT_WIDTH - 1:0];
endmodule
module LFSR
#(
	parameter REG_WIDTH = 31,
	parameter OUT_WIDTH = 11,
	parameter SEED = 24218329
)
(
	input wire clk,
	input wire rst,
	output wire [OUT_WIDTH - 1:0] random
);

reg [REG_WIDTH - 1:0] rand = SEED;
wire feedback;

assign feedback = !(rand[3] ^ rand[0]);

always @(posedge clk)
	if (rst)
		rand <= SEED;
	else
		rand <= {feedback, rand[REG_WIDTH - 1:1]};

assign random = rand[OUT_WIDTH - 1:0];
endmodule