data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder 2.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n%Error: Cannot find file containing module: 2.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    reg cin, cout;

    add16 add16_inst1 (a[15:0 ], b[15:0 ], 1'b0, sum[15:0 ], cin);
    add16 add16_inst2 (a[31:16], b[31:16], cin , sum[31:16], cout);

endmodule
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    reg cin, cout;

    add16 add16_inst1 (a[15:0 ], b[15:0 ], 1'b0, sum[15:0 ], cin);
    add16 add16_inst2 (a[31:16], b[31:16], cin , sum[31:16], cout);

endmodule