data/full_repos/permissive/417347157/tb/fir_filter_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/417347157/tb/fir_filter_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/417347157/tb/fir_filter_tb.sv:48: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/417347157/tb/fir_filter_tb.sv:51: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/417347157/tb/fir_filter_tb.sv:57: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fir_filter_tb(

    );
    
    
    reg clk = 0;
    reg rst = 0;    
    wire signed [15:0] sine_wave;
    reg [31:0] phase_step = 16'd50;
    wire signed [15:0] filtered_sine_wave;

        

    always begin
        #10
        clk = ~clk;
    end
    
    integer i;

    
    initial begin
    
        rst = 1;
        @(posedge clk);
        @(posedge clk);
        rst = 0;
        @(posedge clk);
        

        for(i=32'h000FFFFF; i<32'hFFFFFFFF; i=i+32'h00100000)begin
            phase_step = i;
            repeat (500)begin
                @(posedge clk);
            end 
        end
        $stop;

    end
    
    

    sine_wave_gen_quarter sine_wave_gen_quarter_inst(
        .i_clk(clk),
        .i_rst(rst),
        .i_phase_step(phase_step),
        .o_gen_out(sine_wave)
    );
    
    
    
    fir_filter fir_filter_inst(
         .i_clk(clk)
        ,.i_rst(rst)
        ,.i_data(sine_wave)
        ,.o_data(filtered_sine_wave)
    );
    
    

endmodule
module fir_filter_tb(

    );

    
    
    reg clk = 0;
    reg rst = 0;    
    wire signed [15:0] sine_wave;
    reg [31:0] phase_step = 16'd50;
    wire signed [15:0] filtered_sine_wave;

        

    always begin
        #10
        clk = ~clk;
    end
    
    integer i;

    
    initial begin
    
        rst = 1;
        @(posedge clk);
        @(posedge clk);
        rst = 0;
        @(posedge clk);
        

        for(i=32'h000FFFFF; i<32'hFFFFFFFF; i=i+32'h00100000)begin
            phase_step = i;
            repeat (500)begin
                @(posedge clk);
            end 
        end
        $stop;

    end
    
    

    sine_wave_gen_quarter sine_wave_gen_quarter_inst(
        .i_clk(clk),
        .i_rst(rst),
        .i_phase_step(phase_step),
        .o_gen_out(sine_wave)
    );
    
    
    
    fir_filter fir_filter_inst(
         .i_clk(clk)
        ,.i_rst(rst)
        ,.i_data(sine_wave)
        ,.o_data(filtered_sine_wave)
    );
    
    

endmodule