data/full_repos/permissive/482006041/6-4/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:8: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("wave.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:9: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0, tb);\n       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n       #10000 $finish;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #20 reset <= ~reset;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #20 reset <= ~reset;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #30 reset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n            #30 reset = 1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-4/user/sim/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #20 in <= {$random}%5;\n        ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (

);

    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #10000 $finish;
    end

    wire 	open;
    wire 	error;

    reg clk = 0, reset = 1;
    always 
        #10 clk <= ~clk;

    initial begin
        #20 reset <= ~reset;
        #20 reset <= ~reset;
    end

    always @(*) begin
        if (open || error) begin
            #30 reset = 1'b0;
            #30 reset = 1'b1;
        end 
    end

    reg [2:0] in;
    wire b1, b2, b3, b4;

    always 
        #20 in <= {$random}%5;

    assign b1 = (in == 3'd1) ? 1'b1 : 1'b0;
    assign b2 = (in == 3'd2) ? 1'b1 : 1'b0;
    assign b3 = (in == 3'd3) ? 1'b1 : 1'b0;
    assign b4 = (in == 3'd4) ? 1'b1 : 1'b0;

    lock #(
        .IDLE  		( 3'd0 		),
        .S1    		( 3'd1 		),
        .S2    		( 3'd2 		),
        .S3    		( 3'd3 		),
        .S4    		( 3'd4 		),
        .OPEN  		( 3'd5 		),
        .ERROR 		( 3'd6 		))
    u_lock(

        .clk   		( clk   		),
        .reset 		( reset 		),
        .b1    		( b1    		),
        .b2    		( b2    		),
        .b3    		( b3    		),
        .b4    		( b4    		),
        .open  		( open  		),
        .error 		( error 		)
    );

endmodule
module tb (

);


    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #10000 $finish;
    end

    wire 	open;
    wire 	error;

    reg clk = 0, reset = 1;
    always 
        #10 clk <= ~clk;

    initial begin
        #20 reset <= ~reset;
        #20 reset <= ~reset;
    end

    always @(*) begin
        if (open || error) begin
            #30 reset = 1'b0;
            #30 reset = 1'b1;
        end 
    end

    reg [2:0] in;
    wire b1, b2, b3, b4;

    always 
        #20 in <= {$random}%5;

    assign b1 = (in == 3'd1) ? 1'b1 : 1'b0;
    assign b2 = (in == 3'd2) ? 1'b1 : 1'b0;
    assign b3 = (in == 3'd3) ? 1'b1 : 1'b0;
    assign b4 = (in == 3'd4) ? 1'b1 : 1'b0;

    lock #(
        .IDLE  		( 3'd0 		),
        .S1    		( 3'd1 		),
        .S2    		( 3'd2 		),
        .S3    		( 3'd3 		),
        .S4    		( 3'd4 		),
        .OPEN  		( 3'd5 		),
        .ERROR 		( 3'd6 		))
    u_lock(

        .clk   		( clk   		),
        .reset 		( reset 		),
        .b1    		( b1    		),
        .b2    		( b2    		),
        .b3    		( b3    		),
        .b4    		( b4    		),
        .open  		( open  		),
        .error 		( error 		)
    );

endmodule