data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module Register #(parameter addr_width = 8, data_width = 32)(
    input [addr_width-1:0] Raddr1,
    input [addr_width-1:0] Raddr2, 
    input [addr_width-1:0] Waddr,
    input [data_width-1:0] Wdata,
    input clk,
    input RegWrite,
    output reg [data_width-1:0] Rdata1,
    output reg [data_width-1:0] Rdata2
);
    localparam regNum = 1 << addr_width;
    reg [data_width-1:0] register [regNum-1:0];
    integer i;
    initial begin for(i=0;i<regNum;i=i+1) register[i] = 0; end

    always @(posedge clk) begin 
        if (RegWrite == 1'b1 & Waddr != 0) register[Waddr] <= Wdata; 
    end
    always @(negedge clk) begin
        Rdata1 = (RegWrite == 1 & Waddr == Raddr1)? Wdata:register[Raddr1]; 
        Rdata2 = (RegWrite == 1 & Waddr == Raddr2)? Wdata:register[Raddr2];
    end
endmodule
module Register #(parameter addr_width = 8, data_width = 32)(
    input [addr_width-1:0] Raddr1,
    input [addr_width-1:0] Raddr2, 
    input [addr_width-1:0] Waddr,
    input [data_width-1:0] Wdata,
    input clk,
    input RegWrite,
    output reg [data_width-1:0] Rdata1,
    output reg [data_width-1:0] Rdata2
);

    localparam regNum = 1 << addr_width;
    reg [data_width-1:0] register [regNum-1:0];
    integer i;
    initial begin for(i=0;i<regNum;i=i+1) register[i] = 0; end

    always @(posedge clk) begin 
        if (RegWrite == 1'b1 & Waddr != 0) register[Waddr] <= Wdata; 
    end
    always @(negedge clk) begin
        Rdata1 = (RegWrite == 1 & Waddr == Raddr1)? Wdata:register[Raddr1]; 
        Rdata2 = (RegWrite == 1 & Waddr == Raddr2)? Wdata:register[Raddr2];
    end
endmodule