data/full_repos/permissive/486367830/debug/top_debug/deb_src/clk_rst_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486367830/debug/top_debug/deb_src/clk_rst_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD clk <= ~clk; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/clk_rst_tb.v:17: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/clk_rst_tb.v:19: syntax error, unexpected \'@\'\n        repeat(3) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/clk_rst_tb.v:21: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_rst_tb#(
parameter PERIOD = 5
)(
output reg clk  ,
output reg rst_n
);

initial begin 
    clk = 0;
    forever begin 
    #PERIOD clk <= ~clk; 
    end 
end 

initial begin 
        rst_n <= 1'b1;
        @(posedge clk);
        rst_n <= 1'b0;
        repeat(3) @(posedge clk);
        rst_n <= 1'b1;
        @(posedge clk);
end 

endmodule
module clk_rst_tb#(
parameter PERIOD = 5
)(
output reg clk  ,
output reg rst_n
);


initial begin 
    clk = 0;
    forever begin 
    #PERIOD clk <= ~clk; 
    end 
end 

initial begin 
        rst_n <= 1'b1;
        @(posedge clk);
        rst_n <= 1'b0;
        repeat(3) @(posedge clk);
        rst_n <= 1'b1;
        @(posedge clk);
end 

endmodule