data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v:23: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                      : ... In instance axi_RR_Flag_Req\n   RR_FLAG_o <= 1\'sb0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v:28: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                      : ... In instance axi_RR_Flag_Req\n    RR_FLAG_o <= 1\'sb0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_node/axi_RR_Flag_Req.v:25: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'RR_FLAG_o\' generates 3 bits.\n                                                                                                      : ... In instance axi_RR_Flag_Req\n   if (RR_FLAG_o < (MAX_COUNT - 1))\n                 ^\n%Error: Exiting due to 3 warning(s)\n'
module axi_RR_Flag_Req 
#(

    parameter MAX_COUNT   = 8,
    parameter WIDTH       = $clog2(MAX_COUNT)
)
(
	clk,
	rst_n,
	RR_FLAG_o,
	data_req_i,
	data_gnt_i
);


	input wire clk;
	input wire rst_n;
	output reg [WIDTH - 1:0] RR_FLAG_o;
	input wire data_req_i;
	input wire data_gnt_i;
	always @(posedge clk or negedge rst_n) begin : RR_Flag_Req_SEQ
		if (rst_n == 1'b0)
			RR_FLAG_o <= 1'sb0;
		else if (data_req_i & data_gnt_i)
			if (RR_FLAG_o < (MAX_COUNT - 1))
				RR_FLAG_o <= RR_FLAG_o + 1'b1;
			else
				RR_FLAG_o <= 1'sb0;
	end
endmodule
module axi_RR_Flag_Req 
#(

    parameter MAX_COUNT   = 8,
    parameter WIDTH       = $clog2(MAX_COUNT)
)
(
	clk,
	rst_n,
	RR_FLAG_o,
	data_req_i,
	data_gnt_i
);



	input wire clk;
	input wire rst_n;
	output reg [WIDTH - 1:0] RR_FLAG_o;
	input wire data_req_i;
	input wire data_gnt_i;
	always @(posedge clk or negedge rst_n) begin : RR_Flag_Req_SEQ
		if (rst_n == 1'b0)
			RR_FLAG_o <= 1'sb0;
		else if (data_req_i & data_gnt_i)
			if (RR_FLAG_o < (MAX_COUNT - 1))
				RR_FLAG_o <= RR_FLAG_o + 1'b1;
			else
				RR_FLAG_o <= 1'sb0;
	end
endmodule