data/full_repos/permissive/490716708/Verilog/iCE40.v
1: b'%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:2: Cannot find include file: CPU6.v\n`include "CPU6.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.sv\n             CPU6.v\n             CPU6.v.v\n             CPU6.v.sv\n             obj_dir/CPU6.v\n             obj_dir/CPU6.v.v\n             obj_dir/CPU6.v.sv\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:3: Cannot find include file: LEDPanel.v\n`include "LEDPanel.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:4: Cannot find include file: PLL.v\n`include "PLL.v" \n         ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module iCE40(input clock_100MHz, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7, output LED8);
    initial begin
        reset = 1;
    end

    assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = leds;
    
    reg reset;

    wire writeEnBus;
    wire [7:0] data_c2r, data_r2c;
    wire [18:0] addressBus;
    wire [7:0] leds;
    wire clock20MHz, locked, clock;

	PLL pll(clock_100MHz, clock20MHz, locked);
    Divide4 div(clock20MHz, clock);
    BlockRAM ram(clock, addressBus, writeEnBus, data_c2r, data_r2c);
    LEDPanel panel(clock, addressBus, writeEnBus, data_c2r, data_r2c, leds);
    CPU6 cpu (reset, clock, data_r2c, writeEnBus, addressBus, data_c2r);

	always @ (posedge clock) begin
		if (reset == 1 && locked == 1) begin
			reset <= 0;
		end
    end
endmodule
module iCE40(input clock_100MHz, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7, output LED8);

    initial begin
        reset = 1;
    end

    assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = leds;
    
    reg reset;

    wire writeEnBus;
    wire [7:0] data_c2r, data_r2c;
    wire [18:0] addressBus;
    wire [7:0] leds;
    wire clock20MHz, locked, clock;

	PLL pll(clock_100MHz, clock20MHz, locked);
    Divide4 div(clock20MHz, clock);
    BlockRAM ram(clock, addressBus, writeEnBus, data_c2r, data_r2c);
    LEDPanel panel(clock, addressBus, writeEnBus, data_c2r, data_r2c, leds);
    CPU6 cpu (reset, clock, data_r2c, writeEnBus, addressBus, data_c2r);

	always @ (posedge clock) begin
		if (reset == 1 && locked == 1) begin
			reset <= 0;
		end
    end
endmodule