data/full_repos/permissive/507564148/code/expand/fsm.v
data/verilator_xmls/9d64ebb1-1b4f-4a4c-82f7-1e84918f98e1.xml
module fsm (
    input [3:0] option,
    input [15:0] act_time,
    input clk,
    input mode,
    input finish_test,
    input rst_n,
    output reg [2:0] state,
    output reg [15:0]max_result
);







parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b111, S5 = 3'b110;

always @(posedge clk) begin
if(rst_n == 1'b0) begin
    state <= S0;
    max_result <= 16'b1111111111111111;
end
else begin
    case(state)
    S0:
    begin
        if(option[3]) begin
            state <= S1;
        end
        else begin
            state <= state;
        end
    end
    S1:
    begin
        if(option[1]) begin
        state <= S3;
        end
        else if(option[2]) begin
        state <= S2;
        end
        else begin
        state <= state;
        end
    end
    S3:
    begin

        if(((option[2] == 1'b1) && (act_time > 16'd256)) && (option[0] == 1'b0)) begin
            state <= S4;
        end

        else if(((option[2] == 1'b1) && (act_time < 16'd256)) || (option[0] == 1'b1)) begin
            state <= S2;
        end
        else begin
            state <= state;
        end
    end
    S4:
    begin
        if((mode == 1'b1) && (act_time < max_result)) begin
            max_result <= act_time;
        end
        else begin
            max_result <= max_result;
        end
        
        if(mode && (finish_test == 1'b1)) begin
            state <= S5;
        end
        else if(mode && (finish_test == 1'b0) && (option[3] == 1'b1)) begin
            state <= S1;
        end
        else begin
            state <= state;
        end
    end
    default: 
    begin
        state <= state;
    end
    endcase
end
end
endmodule
module fsm (
    input [3:0] option,
    input [15:0] act_time,
    input clk,
    input mode,
    input finish_test,
    input rst_n,
    output reg [2:0] state,
    output reg [15:0]max_result
);








parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b111, S5 = 3'b110;

always @(posedge clk) begin
if(rst_n == 1'b0) begin
    state <= S0;
    max_result <= 16'b1111111111111111;
end
else begin
    case(state)
    S0:
    begin
        if(option[3]) begin
            state <= S1;
        end
        else begin
            state <= state;
        end
    end
    S1:
    begin
        if(option[1]) begin
        state <= S3;
        end
        else if(option[2]) begin
        state <= S2;
        end
        else begin
        state <= state;
        end
    end
    S3:
    begin

        if(((option[2] == 1'b1) && (act_time > 16'd256)) && (option[0] == 1'b0)) begin
            state <= S4;
        end

        else if(((option[2] == 1'b1) && (act_time < 16'd256)) || (option[0] == 1'b1)) begin
            state <= S2;
        end
        else begin
            state <= state;
        end
    end
    S4:
    begin
        if((mode == 1'b1) && (act_time < max_result)) begin
            max_result <= act_time;
        end
        else begin
            max_result <= max_result;
        end
        
        if(mode && (finish_test == 1'b1)) begin
            state <= S5;
        end
        else if(mode && (finish_test == 1'b0) && (option[3] == 1'b1)) begin
            state <= S1;
        end
        else begin
            state <= state;
        end
    end
    default: 
    begin
        state <= state;
    end
    endcase
end
end
endmodule