data/full_repos/permissive/449521261/parallel_to_UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:216: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            end else if(clock_divider == max_counter) begin\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:214: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            if(clock_divider == max_counter/2) begin\n                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module clock_divider(
    input reset,
    input input_clock,
    output reg output_clock
    );




    parameter max_counter = 0;


    reg [$clog2(max_counter):0] clock_divider;




    always @ (posedge input_clock or posedge reset) begin
        if(reset == 'b1) begin
            clock_divider <= 'b0;
            output_clock <= 'b0;
        end else begin
            clock_divider <= clock_divider + 'b1;
            if(clock_divider == max_counter/2) begin
                output_clock <= 'b1;
            end else if(clock_divider == max_counter) begin
                output_clock <= 'b0;
                clock_divider <= 'b0;
            end
        end
    end
endmodule
module clock_divider(
    input reset,
    input input_clock,
    output reg output_clock
    );





    parameter max_counter = 0;


    reg [$clog2(max_counter):0] clock_divider;




    always @ (posedge input_clock or posedge reset) begin
        if(reset == 'b1) begin
            clock_divider <= 'b0;
            output_clock <= 'b0;
        end else begin
            clock_divider <= clock_divider + 'b1;
            if(clock_divider == max_counter/2) begin
                output_clock <= 'b1;
            end else if(clock_divider == max_counter) begin
                output_clock <= 'b0;
                clock_divider <= 'b0;
            end
        end
    end
endmodule