data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:140: Signal definition not found, creating implicitly: \'clk2\'\n                                                                                                  : ... Suggested alternative: \'clk\'\n assign clkOut = clk2;\n                 ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:273: Signal definition not found, creating implicitly: \'refclk1\'\n                                                                                                  : ... Suggested alternative: \'refclk\'\nalways @ (posedge refclk1) begin\n                  ^~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:111: Cannot find file containing module: \'LBUS_IF\'\n   LBUS_IF lbus_if\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464094143/sasebo_giii_aes,data/full_repos/permissive/464094143/LBUS_IF\n             data/full_repos/permissive/464094143/sasebo_giii_aes,data/full_repos/permissive/464094143/LBUS_IF.v\n             data/full_repos/permissive/464094143/sasebo_giii_aes,data/full_repos/permissive/464094143/LBUS_IF.sv\n             LBUS_IF\n             LBUS_IF.v\n             LBUS_IF.sv\n             obj_dir/LBUS_IF\n             obj_dir/LBUS_IF.v\n             obj_dir/LBUS_IF.sv\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:181: Cannot find file containing module: \'IDELAYE2\'\nIDELAYE2 #(\n^~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:208: Cannot find file containing module: \'IDELAYE2\'\nIDELAYE2 #(\n^~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:235: Cannot find file containing module: \'IDELAYE2\'\nIDELAYE2 #(\n^~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:318: Cannot find file containing module: \'IDELAYCTRL\'\nIDELAYCTRL IDELAYCTRL_inst (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:324: Cannot find file containing module: \'BUFG\'\n BUFG u50 (.I(clk0), .O(refclk1)); \n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:325: Cannot find file containing module: \'BUFG\'\n BUFG u51 (.I(clkA), .O(clk)); \n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:326: Cannot find file containing module: \'BUFG\'\n BUFG u52 (.I(clk2t), .O(clk2)); \n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:327: Cannot find file containing module: \'BUFG\'\n BUFG u53 (.I(clk5t), .O(clk5)); \n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:331: Cannot find file containing module: \'BUFG\'\n BUFG  u25 (.I(CLKFBOUT1),   .O(CLKFBIN1));\n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:332: Cannot find file containing module: \'BUFG\'\n BUFG  u26 (.I(clk3),   .O(clk21));\n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:334: Cannot find file containing module: \'MMCME2_ADV\'\nMMCME2_ADV #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:408: Cannot find file containing module: \'aes_tiny\'\n aes_tiny aes_tiny( .clk(clk),  .rst(dvld),  .din(blk_din), .key(blk_kin), .dout(blk_dout),  .done(blk_dvld) );\n ^~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:459: Cannot find file containing module: \'uart_tx\'\nuart_tx  uartOut(.i_Clock(clk1), .i_Tx_DV(transmitReg), .i_Tx_Byte(TXdata), .o_Tx_Active(TXactive), .o_Tx_Serial(tx), .o_Tx_Done(TXDone) );  \n^~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:460: Cannot find file containing module: \'tdc_top\'\ntdc_top tp (clk1, out);\n^~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:461: Cannot find file containing module: \'tdc_decode\'\ntdc_decode tdc_decode(.clk(clk1), .rst(lbus_rstn), .chainvalue_i(outReg), .coded_o(processedOut)); \n^~~~~~~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:532: Cannot find file containing module: \'IBUFG\'\n   IBUFG u10 (.I(lbus_clkn), .O(refclk)); \n   ^~~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:538: Cannot find file containing module: \'BUFG\'\n BUFG  u15 (.I(CLKFBOUT),   .O(CLKFBIN));\n ^~~~\n%Error: data/full_repos/permissive/464094143/sasebo_giii_aes/chip_sasebo_giii_aes.v:542: Cannot find file containing module: \'MMCME2_ADV\'\n MMCME2_ADV #(\n ^~~~~~~~~~\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module CHIP_SASEBO_GIII_AES
  (
   lbus_di_a, lbus_do, lbus_wrn, lbus_rdn,
   lbus_clkn, lbus_rstn,


   gpio_startn, gpio_endn, gpio_exec, led,


   osc_en_b,
	tx,
	clkOut);
   


   input [15:0]  lbus_di_a;
   output [15:0] lbus_do;
   input         lbus_wrn, lbus_rdn;
   input         lbus_clkn, lbus_rstn;


   output        gpio_startn, gpio_endn, gpio_exec;
   output [9:0]  led;


   output        osc_en_b;
	

	output tx;

	
	output clkOut;
	



   wire         clk, rst;


	

   reg [15:0]   lbus_a, lbus_di;
   

   wire [127:0] blk_kin, blk_din, blk_dout;
   wire         blk_krdy, blk_kvld, blk_drdy, blk_dvld;
   wire         blk_encdec, blk_en, blk_rstn, blk_busy;
   reg          blk_drdy_delay;
  
   wire clk0, clk1, clk3;
	reg startTx;

	wire busyTX, Tx, doneTx;
   
	
	


  

  

   assign led[0] = rst;
   assign led[1] = lbus_rstn;
   assign led[2] = 1'b0;
   assign led[3] = blk_rstn;
   assign led[4] = blk_encdec;
   assign led[5] = blk_krdy;
   assign led[6] = blk_kvld;
   assign led[7] = 1'b0;
   assign led[8] = blk_dvld;
   assign led[9] = blk_busy;
   assign osc_en_b = 1'b1;

   always @(posedge clk) if (lbus_wrn)  lbus_a  <= lbus_di_a;
   always @(posedge clk) if (~lbus_wrn) lbus_di <= lbus_di_a;

   LBUS_IF lbus_if
     (.lbus_a(lbus_a), .lbus_di(lbus_di), .lbus_do(lbus_do),
      .lbus_wr(lbus_wrn), .lbus_rd(lbus_rdn),
      .blk_kin(blk_kin), .blk_din(blk_din), .blk_dout(blk_dout),
      .blk_krdy(blk_krdy), .blk_drdy(blk_drdy), 
      .blk_kvld(blk_kvld), .blk_dvld(blk_dvld),
      .blk_encdec(blk_encdec), .blk_en(blk_en), .blk_rstn(blk_rstn),
      .clk(clk), .rst(rst));


   assign gpio_startn = ~blk_drdy;
   assign gpio_endn   = 1'b0;
   assign gpio_exec   = 1'b0;












   MK_CLKRST mk_clkrst (.clkin(clk), .rstnin(lbus_rstn),
                        .clk(), .rst(rst),.clk00(), .clk11(), .clk22());
	wire clkO;	
   wire   refclk, clkA, clkAA, clkAAA, clk5, clk5t, clk2t;
	assign clkOut = clk2;





























reg [127:0] rnd1;
reg [127:0] rnd2;
reg [127:0] rnd3;
reg [127:0] rnd4;
reg [4:0] r1;
reg [4:0] r2;
reg [4:0] r3;	

	

(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst0 (
.CNTVALUEOUT(),
.DATAOUT(clkAA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[4:0]),
.DATAIN(refclk1),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);


(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst1 (
.CNTVALUEOUT(),
.DATAOUT(clkAAA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[36:32]),
.DATAIN(clkAA),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);


(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("TRUE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst2 (
.CNTVALUEOUT(),
.DATAOUT(clkA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[68:64]),
.DATAIN(clkAAA),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);




reg i;
reg [31:0] m1;
reg [31:0] d1;



parameter a=6;
parameter b=4;
parameter k=4;

always @ (posedge refclk1) begin

	if(lbus_rstn==0) begin

	m1 <= 16;
	rnd1<=128'hab65272819bac345;

	end
	else begin
		rnd1 <=  {rnd1[126:0],rnd1[127]^~rnd1[125]^~rnd1[100]^~rnd1[98]}; 

		end

end






























(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYCTRL IDELAYCTRL_inst (
.RDY(),
.REFCLK(clk2),
.RST(~lbus_rstn)
);

	BUFG u50 (.I(clk0), .O(refclk1)); 
	BUFG u51 (.I(clkA), .O(clk)); 
	BUFG u52 (.I(clk2t), .O(clk2)); 
	BUFG u53 (.I(clk5t), .O(clk5)); 

wire CLKFBOUT1, CLKFBIN1,Cout;

 BUFG  u25 (.I(CLKFBOUT1),   .O(CLKFBIN1));
 BUFG  u26 (.I(clk3),   .O(clk21));

MMCME2_ADV #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(5.0),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(5.208),

		.CLKOUT1_DIVIDE(40),
		.CLKOUT2_DIVIDE(1),
		.CLKOUT3_DIVIDE(1),
		.CLKOUT4_DIVIDE(1),
		.CLKOUT5_DIVIDE(1),
		.CLKOUT6_DIVIDE(1),
		.CLKOUT0_DIVIDE_F(5.0),

		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DUTY_CYCLE(0.5),
		.CLKOUT2_DUTY_CYCLE(0.5),
		.CLKOUT3_DUTY_CYCLE(0.5),
		.CLKOUT4_DUTY_CYCLE(0.5),
		.CLKOUT5_DUTY_CYCLE(0.5),
		.CLKOUT6_DUTY_CYCLE(0.5),

		.CLKOUT0_PHASE(0.0),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT3_PHASE(0.0),
		.CLKOUT4_PHASE(0.0),
		.CLKOUT5_PHASE(0.0),
		.CLKOUT6_PHASE(0.0),
		.CLKOUT4_CASCADE("FALSE"),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	MMCME2_BASE_inst1 (

		.CLKOUT0(clk2t),
		.CLKOUT1(clk5t),
		.CLKOUT2(),





		.CLKFBOUT(CLKFBOUT1),


		.LOCKED(),

		.CLKIN1(clk21),

		.PWRDWN(),
		.RST(~lbus_rstn),

		.CLKINSEL(1'b1),
		.CLKFBIN(CLKFBIN1)
		
	);













reg kvld, dvld, endvld, busy;


 aes_tiny aes_tiny( .clk(clk),  .rst(dvld),  .din(blk_din), .key(blk_kin), .dout(blk_dout),  .done(blk_dvld) );
		
	assign blk_kvld = kvld;
	assign blk_busy = busy;
	
	always @(posedge clk) begin
   if(lbus_rstn==0) begin
		dvld <=0;
		kvld <=0;
		busy  <=0;
	end
	else begin
		if(blk_krdy==1)
			kvld  <=1;
		else if(blk_krdy==0)
			kvld <=0;
			
		if(blk_drdy==1 && endvld==1) begin
			dvld <= 1;
			endvld <=0;
			busy  <=1;
		end
		else if(dvld==1)
			dvld<=0;
		else if(blk_dvld==1) begin
			endvld <=1;
			busy  <=0;			
		end
	end
	end






   reg enTX;
   wire TXdone,TXactive; 
	wire clkin1;						
	reg [7:0] data      [1023:0]; 							
   reg [9:0] addr;
   reg [31:0]count;
	reg [7:0] TXdata;
	wire[7:0] processedOut;
	reg en, transmit, transmitReg, counten;
	reg [2:0] bbyte;
	
wire [255:0] out;		
reg [255:0] outReg;		
parameter regsize =511;
	
uart_tx  uartOut(.i_Clock(clk1), .i_Tx_DV(transmitReg), .i_Tx_Byte(TXdata), .o_Tx_Active(TXactive), .o_Tx_Serial(tx), .o_Tx_Done(TXDone) );		
tdc_top tp (clk1, out);
tdc_decode tdc_decode(.clk(clk1), .rst(lbus_rstn), .chainvalue_i(outReg), .coded_o(processedOut)); 

integer index;
  always @(posedge clk1) begin
		if(lbus_rstn==0) begin
			addr <=0;
			transmit <=0;
			transmitReg <=0;
			counten <=0;
			bbyte <=0;
			for (index=0; index<1024; index=index+1) begin
         data[index] <= 0;
			en <=0;
         end
		end
		else if (dvld==1 && en==0 ) begin
			addr <=0;
			en   <=1;
			transmit <=0;
			transmitReg <=0;
			outReg <= out;
			
		end
		else if (en==1 && addr!=regsize && transmit ==0)  begin
         addr <= addr+1;

			outReg <= out;
			data[addr] <= processedOut;
			transmit <=0;
			transmitReg <=0;
		end
		else if(en ==1 && addr==regsize && transmit ==0) begin
			en <=0;

			counten <=1;
			count  <=0;

			addr <=0;

			bbyte <= 0;
		end
		else if(counten==1) begin
			if(count==1024*1024*1) begin
				transmit <=1;
				transmitReg <=1;
				TXdata <= data[addr];
				
				counten <=0;
			end
			else
				count <= count +1;
		end		
		else if( transmit ==1) begin
				if(addr==regsize) begin
					transmit <=0;
					transmitReg <=0;
					addr <=0;
				end
				else if (transmitReg ==1) begin
						transmitReg <=0;
					end
				else if(TXactive==0) begin
					transmitReg <=1;
					TXdata <= data[addr];
					addr <= addr+1;
				end
				
		end 
	
  end

   IBUFG u10 (.I(lbus_clkn), .O(refclk)); 




 wire CLKFBOUT, CLKFBIN;
 BUFG  u15 (.I(CLKFBOUT),   .O(CLKFBIN));
 
							
								
	MMCME2_ADV #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(40.0),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(41),

		.CLKOUT1_DIVIDE(10),
		.CLKOUT2_DIVIDE(5),
		.CLKOUT3_DIVIDE(1),
		.CLKOUT4_DIVIDE(1),
		.CLKOUT5_DIVIDE(1),
		.CLKOUT6_DIVIDE(1),
		.CLKOUT0_DIVIDE_F(40.0),

		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DUTY_CYCLE(0.5),
		.CLKOUT2_DUTY_CYCLE(0.5),
		.CLKOUT3_DUTY_CYCLE(0.5),
		.CLKOUT4_DUTY_CYCLE(0.5),
		.CLKOUT5_DUTY_CYCLE(0.5),
		.CLKOUT6_DUTY_CYCLE(0.5),

		.CLKOUT0_PHASE(0.0),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT3_PHASE(0.0),
		.CLKOUT4_PHASE(0.0),
		.CLKOUT5_PHASE(0.0),
		.CLKOUT6_PHASE(0.0),
		.CLKOUT4_CASCADE("FALSE"),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	MMCME2_BASE_inst (

		.CLKOUT0(clk0),
		.CLKOUT1(clk1),
		.CLKOUT2(clk3),





		.CLKFBOUT(CLKFBOUT),


		.LOCKED(LOCKED),

		.CLKIN1(refclk),

		.PWRDWN(PWRDWN),
		.RST(~lbus_rstn),
		.CLKINSEL(1'b1),

		.CLKFBIN(CLKFBIN)
	);

			
								
endmodule
module CHIP_SASEBO_GIII_AES
  (
   lbus_di_a, lbus_do, lbus_wrn, lbus_rdn,
   lbus_clkn, lbus_rstn,


   gpio_startn, gpio_endn, gpio_exec, led,


   osc_en_b,
	tx,
	clkOut);

   


   input [15:0]  lbus_di_a;
   output [15:0] lbus_do;
   input         lbus_wrn, lbus_rdn;
   input         lbus_clkn, lbus_rstn;


   output        gpio_startn, gpio_endn, gpio_exec;
   output [9:0]  led;


   output        osc_en_b;
	

	output tx;

	
	output clkOut;
	



   wire         clk, rst;


	

   reg [15:0]   lbus_a, lbus_di;
   

   wire [127:0] blk_kin, blk_din, blk_dout;
   wire         blk_krdy, blk_kvld, blk_drdy, blk_dvld;
   wire         blk_encdec, blk_en, blk_rstn, blk_busy;
   reg          blk_drdy_delay;
  
   wire clk0, clk1, clk3;
	reg startTx;

	wire busyTX, Tx, doneTx;
   
	
	


  

  

   assign led[0] = rst;
   assign led[1] = lbus_rstn;
   assign led[2] = 1'b0;
   assign led[3] = blk_rstn;
   assign led[4] = blk_encdec;
   assign led[5] = blk_krdy;
   assign led[6] = blk_kvld;
   assign led[7] = 1'b0;
   assign led[8] = blk_dvld;
   assign led[9] = blk_busy;
   assign osc_en_b = 1'b1;

   always @(posedge clk) if (lbus_wrn)  lbus_a  <= lbus_di_a;
   always @(posedge clk) if (~lbus_wrn) lbus_di <= lbus_di_a;

   LBUS_IF lbus_if
     (.lbus_a(lbus_a), .lbus_di(lbus_di), .lbus_do(lbus_do),
      .lbus_wr(lbus_wrn), .lbus_rd(lbus_rdn),
      .blk_kin(blk_kin), .blk_din(blk_din), .blk_dout(blk_dout),
      .blk_krdy(blk_krdy), .blk_drdy(blk_drdy), 
      .blk_kvld(blk_kvld), .blk_dvld(blk_dvld),
      .blk_encdec(blk_encdec), .blk_en(blk_en), .blk_rstn(blk_rstn),
      .clk(clk), .rst(rst));


   assign gpio_startn = ~blk_drdy;
   assign gpio_endn   = 1'b0;
   assign gpio_exec   = 1'b0;












   MK_CLKRST mk_clkrst (.clkin(clk), .rstnin(lbus_rstn),
                        .clk(), .rst(rst),.clk00(), .clk11(), .clk22());
	wire clkO;	
   wire   refclk, clkA, clkAA, clkAAA, clk5, clk5t, clk2t;
	assign clkOut = clk2;





























reg [127:0] rnd1;
reg [127:0] rnd2;
reg [127:0] rnd3;
reg [127:0] rnd4;
reg [4:0] r1;
reg [4:0] r2;
reg [4:0] r3;	

	

(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst0 (
.CNTVALUEOUT(),
.DATAOUT(clkAA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[4:0]),
.DATAIN(refclk1),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);


(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst1 (
.CNTVALUEOUT(),
.DATAOUT(clkAAA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[36:32]),
.DATAIN(clkAA),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);


(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYE2 #(
.CINVCTRL_SEL("TRUE"),
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(0),
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(192.0),
.SIGNAL_PATTERN("CLOCK")
)
IDELAYE2_inst2 (
.CNTVALUEOUT(),
.DATAOUT(clkA),
.C(refclk1),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(rnd1[68:64]),
.DATAIN(clkAAA),
.IDATAIN(),
.INC(1'b0),
.LD(1'b1),
.LDPIPEEN(1'b1),
.REGRST(~lbus_rstn)
);




reg i;
reg [31:0] m1;
reg [31:0] d1;



parameter a=6;
parameter b=4;
parameter k=4;

always @ (posedge refclk1) begin

	if(lbus_rstn==0) begin

	m1 <= 16;
	rnd1<=128'hab65272819bac345;

	end
	else begin
		rnd1 <=  {rnd1[126:0],rnd1[127]^~rnd1[125]^~rnd1[100]^~rnd1[98]}; 

		end

end






























(* IODELAY_GROUP = "Group_ADS1" *)
IDELAYCTRL IDELAYCTRL_inst (
.RDY(),
.REFCLK(clk2),
.RST(~lbus_rstn)
);

	BUFG u50 (.I(clk0), .O(refclk1)); 
	BUFG u51 (.I(clkA), .O(clk)); 
	BUFG u52 (.I(clk2t), .O(clk2)); 
	BUFG u53 (.I(clk5t), .O(clk5)); 

wire CLKFBOUT1, CLKFBIN1,Cout;

 BUFG  u25 (.I(CLKFBOUT1),   .O(CLKFBIN1));
 BUFG  u26 (.I(clk3),   .O(clk21));

MMCME2_ADV #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(5.0),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(5.208),

		.CLKOUT1_DIVIDE(40),
		.CLKOUT2_DIVIDE(1),
		.CLKOUT3_DIVIDE(1),
		.CLKOUT4_DIVIDE(1),
		.CLKOUT5_DIVIDE(1),
		.CLKOUT6_DIVIDE(1),
		.CLKOUT0_DIVIDE_F(5.0),

		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DUTY_CYCLE(0.5),
		.CLKOUT2_DUTY_CYCLE(0.5),
		.CLKOUT3_DUTY_CYCLE(0.5),
		.CLKOUT4_DUTY_CYCLE(0.5),
		.CLKOUT5_DUTY_CYCLE(0.5),
		.CLKOUT6_DUTY_CYCLE(0.5),

		.CLKOUT0_PHASE(0.0),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT3_PHASE(0.0),
		.CLKOUT4_PHASE(0.0),
		.CLKOUT5_PHASE(0.0),
		.CLKOUT6_PHASE(0.0),
		.CLKOUT4_CASCADE("FALSE"),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	MMCME2_BASE_inst1 (

		.CLKOUT0(clk2t),
		.CLKOUT1(clk5t),
		.CLKOUT2(),





		.CLKFBOUT(CLKFBOUT1),


		.LOCKED(),

		.CLKIN1(clk21),

		.PWRDWN(),
		.RST(~lbus_rstn),

		.CLKINSEL(1'b1),
		.CLKFBIN(CLKFBIN1)
		
	);













reg kvld, dvld, endvld, busy;


 aes_tiny aes_tiny( .clk(clk),  .rst(dvld),  .din(blk_din), .key(blk_kin), .dout(blk_dout),  .done(blk_dvld) );
		
	assign blk_kvld = kvld;
	assign blk_busy = busy;
	
	always @(posedge clk) begin
   if(lbus_rstn==0) begin
		dvld <=0;
		kvld <=0;
		busy  <=0;
	end
	else begin
		if(blk_krdy==1)
			kvld  <=1;
		else if(blk_krdy==0)
			kvld <=0;
			
		if(blk_drdy==1 && endvld==1) begin
			dvld <= 1;
			endvld <=0;
			busy  <=1;
		end
		else if(dvld==1)
			dvld<=0;
		else if(blk_dvld==1) begin
			endvld <=1;
			busy  <=0;			
		end
	end
	end






   reg enTX;
   wire TXdone,TXactive; 
	wire clkin1;						
	reg [7:0] data      [1023:0]; 							
   reg [9:0] addr;
   reg [31:0]count;
	reg [7:0] TXdata;
	wire[7:0] processedOut;
	reg en, transmit, transmitReg, counten;
	reg [2:0] bbyte;
	
wire [255:0] out;		
reg [255:0] outReg;		
parameter regsize =511;
	
uart_tx  uartOut(.i_Clock(clk1), .i_Tx_DV(transmitReg), .i_Tx_Byte(TXdata), .o_Tx_Active(TXactive), .o_Tx_Serial(tx), .o_Tx_Done(TXDone) );		
tdc_top tp (clk1, out);
tdc_decode tdc_decode(.clk(clk1), .rst(lbus_rstn), .chainvalue_i(outReg), .coded_o(processedOut)); 

integer index;
  always @(posedge clk1) begin
		if(lbus_rstn==0) begin
			addr <=0;
			transmit <=0;
			transmitReg <=0;
			counten <=0;
			bbyte <=0;
			for (index=0; index<1024; index=index+1) begin
         data[index] <= 0;
			en <=0;
         end
		end
		else if (dvld==1 && en==0 ) begin
			addr <=0;
			en   <=1;
			transmit <=0;
			transmitReg <=0;
			outReg <= out;
			
		end
		else if (en==1 && addr!=regsize && transmit ==0)  begin
         addr <= addr+1;

			outReg <= out;
			data[addr] <= processedOut;
			transmit <=0;
			transmitReg <=0;
		end
		else if(en ==1 && addr==regsize && transmit ==0) begin
			en <=0;

			counten <=1;
			count  <=0;

			addr <=0;

			bbyte <= 0;
		end
		else if(counten==1) begin
			if(count==1024*1024*1) begin
				transmit <=1;
				transmitReg <=1;
				TXdata <= data[addr];
				
				counten <=0;
			end
			else
				count <= count +1;
		end		
		else if( transmit ==1) begin
				if(addr==regsize) begin
					transmit <=0;
					transmitReg <=0;
					addr <=0;
				end
				else if (transmitReg ==1) begin
						transmitReg <=0;
					end
				else if(TXactive==0) begin
					transmitReg <=1;
					TXdata <= data[addr];
					addr <= addr+1;
				end
				
		end 
	
  end

   IBUFG u10 (.I(lbus_clkn), .O(refclk)); 




 wire CLKFBOUT, CLKFBIN;
 BUFG  u15 (.I(CLKFBOUT),   .O(CLKFBIN));
 
							
								
	MMCME2_ADV #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(40.0),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(41),

		.CLKOUT1_DIVIDE(10),
		.CLKOUT2_DIVIDE(5),
		.CLKOUT3_DIVIDE(1),
		.CLKOUT4_DIVIDE(1),
		.CLKOUT5_DIVIDE(1),
		.CLKOUT6_DIVIDE(1),
		.CLKOUT0_DIVIDE_F(40.0),

		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DUTY_CYCLE(0.5),
		.CLKOUT2_DUTY_CYCLE(0.5),
		.CLKOUT3_DUTY_CYCLE(0.5),
		.CLKOUT4_DUTY_CYCLE(0.5),
		.CLKOUT5_DUTY_CYCLE(0.5),
		.CLKOUT6_DUTY_CYCLE(0.5),

		.CLKOUT0_PHASE(0.0),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT3_PHASE(0.0),
		.CLKOUT4_PHASE(0.0),
		.CLKOUT5_PHASE(0.0),
		.CLKOUT6_PHASE(0.0),
		.CLKOUT4_CASCADE("FALSE"),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	MMCME2_BASE_inst (

		.CLKOUT0(clk0),
		.CLKOUT1(clk1),
		.CLKOUT2(clk3),





		.CLKFBOUT(CLKFBOUT),


		.LOCKED(LOCKED),

		.CLKIN1(refclk),

		.PWRDWN(PWRDWN),
		.RST(~lbus_rstn),
		.CLKINSEL(1'b1),

		.CLKFBIN(CLKFBIN)
	);

			
								
endmodule