data/full_repos/permissive/408955603/Sesion9/biestableTHold.v
data/verilator_xmls/e9703a80-c3af-438f-a45c-76497bae6a7d.xml
module T(output reg Q, output wire nQ, input wire T, input wire nPRESET, input wire nCLEAR);
	initial Q = 0;
	not(nQ, Q);

	always @(negedge T)
		if (nPRESET && nCLEAR) Q = ~Q;

	always @(nPRESET, nCLEAR)
		case({nPRESET, nCLEAR})
			2'b01: Q = 1;
			2'b10: Q = 0;
		endcase
endmodule
module T(output reg Q, output wire nQ, input wire T, input wire nPRESET, input wire nCLEAR);

	initial Q = 0;
	not(nQ, Q);

	always @(negedge T)
		if (nPRESET && nCLEAR) Q = ~Q;

	always @(nPRESET, nCLEAR)
		case({nPRESET, nCLEAR})
			2'b01: Q = 1;
			2'b10: Q = 0;
		endcase
endmodule