data/full_repos/permissive/481069643/Day01/adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481069643/Day01/adder.v:17: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'in_cin\' generates 1 bits.\n                                                                     : ... In instance adder\nassign {out_carry,out_sum} = in_a+in_b+in_cin;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module adder(in_a,in_b,in_cin,out_sum,out_carry);

input [3:0]in_a,in_b;
input in_cin;
output [3:0]out_sum;
output out_carry;

assign {out_carry,out_sum} = in_a+in_b+in_cin;

endmodule
module adder(in_a,in_b,in_cin,out_sum,out_carry);


input [3:0]in_a,in_b;
input in_cin;
output [3:0]out_sum;
output out_carry;

assign {out_carry,out_sum} = in_a+in_b+in_cin;

endmodule