data/full_repos/permissive/46343463/src/GeneralControl.v
1: b'%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:1: Cannot find include file: LookupTable.v\n`include "LookupTable.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v.sv\n             LookupTable.v\n             LookupTable.v.v\n             LookupTable.v.sv\n             obj_dir/LookupTable.v\n             obj_dir/LookupTable.v.v\n             obj_dir/LookupTable.v.sv\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: Define or directive not defined: \'`ADD_op\'\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n   ^~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: syntax error, unexpected \',\', expecting endcase\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n          ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: Define or directive not defined: \'`SUB_op\'\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n            ^~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: Define or directive not defined: \'`MUL_op\'\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n                     ^~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: Define or directive not defined: \'`AND_op\'\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n                              ^~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:37: Define or directive not defined: \'`OR_op\'\n   `ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :\n                                       ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:40: Define or directive not defined: \'`ADD_func\'\n    `ADD_func:\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:43: Define or directive not defined: \'`ADD_alu\'\n     EX_ctrl_o <= { `ADD_alu, 1\'b0, 1\'b1 };\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:43: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     EX_ctrl_o <= { `ADD_alu, 1\'b0, 1\'b1 };\n                            ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:48: Define or directive not defined: \'`SUB_func\'\n    `SUB_func :\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:49: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:51: Define or directive not defined: \'`SUB_alu\'\n     EX_ctrl_o <= { `SUB_alu, 1\'b0, 1\'b1 };\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:51: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     EX_ctrl_o <= { `SUB_alu, 1\'b0, 1\'b1 };\n                            ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:56: Define or directive not defined: \'`MUL_func\'\n    `MUL_func : \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:57: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:59: Define or directive not defined: \'`MUL_alu\'\n     EX_ctrl_o <= { `MUL_alu, 1\'b0, 1\'b1 };\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:59: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     EX_ctrl_o <= { `MUL_alu, 1\'b0, 1\'b1 };\n                            ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:64: Define or directive not defined: \'`AND_func\'\n    `AND_func : \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:65: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:67: Define or directive not defined: \'`AND_alu\'\n     EX_ctrl_o <= { `AND_alu, 1\'b0, 1\'b1 };\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:67: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     EX_ctrl_o <= { `AND_alu, 1\'b0, 1\'b1 };\n                            ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:72: Define or directive not defined: \'`OR_func\'\n    `OR_func :\n    ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:73: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:75: Define or directive not defined: \'`OR_alu\'\n     EX_ctrl_o <= { `OR_alu, 1\'b0, 1\'b1 };\n                    ^~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:75: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     EX_ctrl_o <= { `OR_alu, 1\'b0, 1\'b1 };\n                           ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:80: syntax error, unexpected \':\', expecting clocking\n    default  :\n             ^\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:90: Define or directive not defined: \'`ADDI_op\'\n   `ADDI_op :\n   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:93: Define or directive not defined: \'`ADD_alu\'\n    EX_ctrl_o <= { `ADD_alu, 1\'b1, 1\'b0 };\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:98: Define or directive not defined: \'`LW_op\'\n   `LW_op :\n   ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:101: Define or directive not defined: \'`ADD_alu\'\n    EX_ctrl_o <= { `ADD_alu, 1\'b1, 1\'b0 };\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:106: Define or directive not defined: \'`SW_op\'\n   `SW_op :\n   ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:109: Define or directive not defined: \'`ADD_alu\'\n    EX_ctrl_o <= { `ADD_alu, 1\'b1, 1\'b0 };\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:114: Define or directive not defined: \'`J_op\'\n   `J_op :\n   ^~~~~\n%Error: data/full_repos/permissive/46343463/src/GeneralControl.v:122: Define or directive not defined: \'`BEQ_op\'\n   `BEQ_op :\n   ^~~~~~~\n%Error: Cannot continue\n'
module GeneralControl (
	input			[5:0]	op_i,
	input			[5:0]	func_i,
	input					is_equal_i,
	output reg		[1:0]	PC_ctrl_o,
	output reg		[4:0]	EX_ctrl_o,	
	output reg		[1:0]	MEM_ctrl_o,
	output reg		[1:0]	WB_ctrl_o
);
	








	always @ (*)
	begin
		case (op_i)

			`ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op	:
			begin
			case (func_i)
				`ADD_func:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `ADD_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end
		
				`SUB_func	:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `SUB_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				`MUL_func	:	
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `MUL_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				`AND_func	:	
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `AND_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end
		
				`OR_func	:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `OR_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				default		:
				begin
					PC_ctrl_o	<= 2'b0;
					EX_ctrl_o	<= 5'b0;
					MEM_ctrl_o	<= 2'b0;
					WB_ctrl_o	<= 2'b0;
				end
			endcase
			end

			`ADDI_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b0, 1'b0 };
				WB_ctrl_o	<= { 1'b1, 1'b1 };
			end

			`LW_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b1, 1'b0 };
				WB_ctrl_o	<= { 1'b0, 1'b1 };
			end

			`SW_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b1, 1'b1 };
				WB_ctrl_o	<= { 1'b1, 1'b0 };
			end

			`J_op	:
			begin
				PC_ctrl_o	<= { 1'b1, 1'b0 };
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end

			`BEQ_op	:
			begin

				if(is_equal_i)
					PC_ctrl_o	<= { 1'b1, 1'b1 };
				else
					PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end

			default:
			begin
				PC_ctrl_o	<= 2'b0;
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end
		endcase
	end

endmodule
module GeneralControl (
	input			[5:0]	op_i,
	input			[5:0]	func_i,
	input					is_equal_i,
	output reg		[1:0]	PC_ctrl_o,
	output reg		[4:0]	EX_ctrl_o,	
	output reg		[1:0]	MEM_ctrl_o,
	output reg		[1:0]	WB_ctrl_o
);

	








	always @ (*)
	begin
		case (op_i)

			`ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op	:
			begin
			case (func_i)
				`ADD_func:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `ADD_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end
		
				`SUB_func	:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `SUB_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				`MUL_func	:	
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `MUL_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				`AND_func	:	
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `AND_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end
		
				`OR_func	:
				begin
					PC_ctrl_o	<= { 1'b0, 1'b0 };
					EX_ctrl_o	<= { `OR_alu, 1'b0, 1'b1 };
					MEM_ctrl_o	<= { 1'b0, 1'b0 };
					WB_ctrl_o	<= { 1'b1, 1'b1 };
				end

				default		:
				begin
					PC_ctrl_o	<= 2'b0;
					EX_ctrl_o	<= 5'b0;
					MEM_ctrl_o	<= 2'b0;
					WB_ctrl_o	<= 2'b0;
				end
			endcase
			end

			`ADDI_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b0, 1'b0 };
				WB_ctrl_o	<= { 1'b1, 1'b1 };
			end

			`LW_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b1, 1'b0 };
				WB_ctrl_o	<= { 1'b0, 1'b1 };
			end

			`SW_op	:
			begin
				PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= { `ADD_alu, 1'b1, 1'b0 };
				MEM_ctrl_o	<= { 1'b1, 1'b1 };
				WB_ctrl_o	<= { 1'b1, 1'b0 };
			end

			`J_op	:
			begin
				PC_ctrl_o	<= { 1'b1, 1'b0 };
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end

			`BEQ_op	:
			begin

				if(is_equal_i)
					PC_ctrl_o	<= { 1'b1, 1'b1 };
				else
					PC_ctrl_o	<= { 1'b0, 1'b0 };
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end

			default:
			begin
				PC_ctrl_o	<= 2'b0;
				EX_ctrl_o	<= 5'b0;
				MEM_ctrl_o	<= 2'b0;
				WB_ctrl_o	<= 2'b0;
			end
		endcase
	end

endmodule