data/full_repos/permissive/445357518/regfile.v
data/verilator_xmls/552fc6b0-b9bc-4c4f-a7cc-ce192500d309.xml
module regfile(data_in,writenum,write,readnum,clk,data_out);

	input [15:0] data_in;
	input [2:0] writenum, readnum;
	input write, clk;
	output [15:0] data_out;
	reg [15:0] data_out;
	wire [7:0] writeValue;
	wire R0_in, R1_in, R2_in, R3_in, R4_in, R5_in, R6_in, R7_in;
	wire [15:0] R0;
	wire [15:0] R1;
	wire [15:0] R2;
	wire [15:0] R3;
	wire [15:0] R4;
	wire [15:0] R5;
	wire [15:0] R6;
	wire [15:0] R7;
	wire [7:0] select;


	Dec dec38(writenum, writeValue);
	

	assign R0_in = writeValue[0] & write;
	assign R1_in = writeValue[1] & write;
	assign R2_in = writeValue[2] & write;
	assign R3_in = writeValue[3] & write;
	assign R4_in = writeValue[4] & write;
	assign R5_in = writeValue[5] & write;
	assign R6_in = writeValue[6] & write;
	assign R7_in = writeValue[7] & write;
	

	vDFF1 R0_dff(clk, data_in, R0_in, R0); 
	vDFF1 R1_dff(clk, data_in, R1_in, R1);
	vDFF1 R2_dff(clk, data_in, R2_in, R2);
	vDFF1 R3_dff(clk, data_in, R3_in, R3);
	vDFF1 R4_dff(clk, data_in, R4_in, R4);
	vDFF1 R5_dff(clk, data_in, R5_in, R5);
	vDFF1 R6_dff(clk, data_in, R6_in, R6);
	vDFF1 R7_dff(clk, data_in, R7_in, R7);




	Dec dec38read(readnum, select);

	always @* begin
		case (select)
			8'b00000001: data_out = R0;
			8'b00000010: data_out = R1;
			8'b00000100: data_out = R2;
			8'b00001000: data_out = R3;
			8'b00010000: data_out = R4;
			8'b00100000: data_out = R5;
			8'b01000000: data_out = R6;
			8'b10000000: data_out = R7;
			default: data_out = 16'bxxxxxxxxxxxxxxxx;
		endcase
	end
	
endmodule
module regfile(data_in,writenum,write,readnum,clk,data_out);


	input [15:0] data_in;
	input [2:0] writenum, readnum;
	input write, clk;
	output [15:0] data_out;
	reg [15:0] data_out;
	wire [7:0] writeValue;
	wire R0_in, R1_in, R2_in, R3_in, R4_in, R5_in, R6_in, R7_in;
	wire [15:0] R0;
	wire [15:0] R1;
	wire [15:0] R2;
	wire [15:0] R3;
	wire [15:0] R4;
	wire [15:0] R5;
	wire [15:0] R6;
	wire [15:0] R7;
	wire [7:0] select;


	Dec dec38(writenum, writeValue);
	

	assign R0_in = writeValue[0] & write;
	assign R1_in = writeValue[1] & write;
	assign R2_in = writeValue[2] & write;
	assign R3_in = writeValue[3] & write;
	assign R4_in = writeValue[4] & write;
	assign R5_in = writeValue[5] & write;
	assign R6_in = writeValue[6] & write;
	assign R7_in = writeValue[7] & write;
	

	vDFF1 R0_dff(clk, data_in, R0_in, R0); 
	vDFF1 R1_dff(clk, data_in, R1_in, R1);
	vDFF1 R2_dff(clk, data_in, R2_in, R2);
	vDFF1 R3_dff(clk, data_in, R3_in, R3);
	vDFF1 R4_dff(clk, data_in, R4_in, R4);
	vDFF1 R5_dff(clk, data_in, R5_in, R5);
	vDFF1 R6_dff(clk, data_in, R6_in, R6);
	vDFF1 R7_dff(clk, data_in, R7_in, R7);




	Dec dec38read(readnum, select);

	always @* begin
		case (select)
			8'b00000001: data_out = R0;
			8'b00000010: data_out = R1;
			8'b00000100: data_out = R2;
			8'b00001000: data_out = R3;
			8'b00010000: data_out = R4;
			8'b00100000: data_out = R5;
			8'b01000000: data_out = R6;
			8'b10000000: data_out = R7;
			default: data_out = 16'bxxxxxxxxxxxxxxxx;
		endcase
	end
	
endmodule