data/full_repos/permissive/512700783/main.v
1: b'%Error: data/full_repos/permissive/512700783/main.v:2: Cannot find include file: Mips.v\n`include "Mips.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/Mips.v\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/Mips.v.v\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/Mips.v.sv\n             Mips.v\n             Mips.v.v\n             Mips.v.sv\n             obj_dir/Mips.v\n             obj_dir/Mips.v.v\n             obj_dir/Mips.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/512700783/main.v:15: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~ clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/512700783/main.v:17: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Mips.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/512700783/main.v:18: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,main);\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module main(clk);
	output reg clk = 0;
	Mips uut (
    		.clk(clk)
	);

	always #5 clk = ~ clk;
	initial begin 
		$dumpfile("Mips.vcd");
		$dumpvars(0,main);
	end    
endmodule
module main(clk);

	output reg clk = 0;
	Mips uut (
    		.clk(clk)
	);

	always #5 clk = ~ clk;
	initial begin 
		$dumpfile("Mips.vcd");
		$dumpvars(0,main);
	end    
endmodule