data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/lv_rd256wrap.v
data/verilator_xmls/a7af1a81-e5ee-4790-94be-ef9f16673577.xml
module lv_rd256wrap
    (
     clk,
     rst,
     randvl
     );



parameter WID = 256;
parameter SEED = 256'd134799733323198995502561713907086292154532538166959272814710328655875;




input     clk;
input    rst;
output [WID-1:0] randvl;




reg [WID-1:0]    randreg;

always@(posedge clk)
    begin
    if(rst)
        begin
        randreg <= SEED;
        end
    else
        begin
        randreg[255] <= randreg[0];
        randreg[254] <= randreg[255];
        randreg[253] <= randreg[254] ^ randreg[0];
        randreg[252] <= randreg[253];
        randreg[251] <= randreg[252];
        randreg[250] <= randreg[251] ^ randreg[0];
        randreg[249] <= randreg[250];
        randreg[248] <= randreg[249];
        randreg[247] <= randreg[248];
        randreg[246] <= randreg[247];
        randreg[245] <= randreg[246] ^ randreg[0];
        randreg[244:0] <= randreg[245:1];
        end
    end
assign randvl = randreg;
endmodule
module lv_rd256wrap
    (
     clk,
     rst,
     randvl
     );




parameter WID = 256;
parameter SEED = 256'd134799733323198995502561713907086292154532538166959272814710328655875;




input     clk;
input    rst;
output [WID-1:0] randvl;




reg [WID-1:0]    randreg;

always@(posedge clk)
    begin
    if(rst)
        begin
        randreg <= SEED;
        end
    else
        begin
        randreg[255] <= randreg[0];
        randreg[254] <= randreg[255];
        randreg[253] <= randreg[254] ^ randreg[0];
        randreg[252] <= randreg[253];
        randreg[251] <= randreg[252];
        randreg[250] <= randreg[251] ^ randreg[0];
        randreg[249] <= randreg[250];
        randreg[248] <= randreg[249];
        randreg[247] <= randreg[248];
        randreg[246] <= randreg[247];
        randreg[245] <= randreg[246] ^ randreg[0];
        randreg[244:0] <= randreg[245:1];
        end
    end
assign randvl = randreg;
endmodule