data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  always #50 clock    <= (clock === 1\'b0);\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n  always #500 spi_clock <= ~spi_clock;\n         ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:104: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:232: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:272: syntax error, unexpected \'@\'\n      @(negedge spi_clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:276: syntax error, unexpected \'@\'\n      @(posedge spi_clock)\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:281: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:361: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:367: syntax error, unexpected \'@\'\n      @(posedge update_cycle_complete);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:377: syntax error, unexpected \'@\'\n      @(posedge update_cycle_complete);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:401: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:403: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:405: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:425: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:437: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:439: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:452: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:454: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:456: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:486: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:535: syntax error, unexpected \'@\'\n          @(posedge clock);\n          ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:544: syntax error, unexpected \'@\'\n          @(posedge clock);\n          ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:564: syntax error, unexpected \'@\'\n          @(posedge clock);\n          ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:596: syntax error, unexpected \'@\'\n    @(posedge power2)\n    ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:612: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: data/full_repos/permissive/524532083/verilog/vcs/user_wrapper_test.v:619: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: Exiting due to 24 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module HBCell(
input wire p_in,
input wire n_in,
output wire line
);

wire common;
wire temp1;
wire temp2;

nmos n1Mos (common,1'b0,n_in);
pmos p1Mos (common,1'b1,p_in);

assign line = common;

endmodule
module HBCell(
input wire p_in,
input wire n_in,
output wire line
);


wire common;
wire temp1;
wire temp2;

nmos n1Mos (common,1'b0,n_in);
pmos p1Mos (common,1'b1,p_in);

assign line = common;

endmodule