data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:13: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:25: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("lin_gen_tb.vcd");\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:44: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:50: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:55: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:59: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, PE_TB);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:60: Unsupported or unknown PLI call: $dumpall\n        $dumpall;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/tb/lin_gen_tb.sv:61: Unsupported or unknown PLI call: $dumpflush\n        $dumpflush;\n        ^~~~~~~~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE_TB;
    reg clk, rstn, fire;
    reg [7:0] w [0:3];
    wire [11:0] o [0:3];
    reg [7:0] a [0:3];
    reg [7:0] cnt;

    integer i;

    always begin
        #10;
        clk = ~clk;
    end

    always_ff @ (posedge clk) begin
        cnt <= cnt + 1'b1;
    end

    PE_Lin_gen dut(.clk(clk), .rstn(rstn), .fire(fire), 
        .in_w(w), .in_a(a[0]), .outs(o));

    initial begin
        $dumpfile("lin_gen_tb.vcd");
        clk <= 0;
        rstn <= 0;
        a[0] <= 1;
        fire <= 1;



        w[0] <= 0;
        w[1] <= 1;
        w[2] <= 2;
        w[3] <= 3;

        $display("Initialized");

        #25;
        rstn <= 1;

        for (i=0; i<8; i=i+1) begin
            @(posedge clk);
            $display("i=%d\tout=%d,%d,%d,%d",i,o[0],o[1],o[2],o[3]);

            a[0] <= a[0] + 1;
        end
        
        #5;
        a[0] <= 0;
        fire <= 0;

        for (i=0; i<8; i=i+1) begin
            @(posedge clk);
            $display("i=%d\tout=%d,%d,%d,%d",i,o[0],o[1],o[2],o[3]);
        end

        $dumpvars(0, PE_TB);
        $dumpall;
        $dumpflush;
        $finish;
    end
endmodule
module PE_TB;

    reg clk, rstn, fire;
    reg [7:0] w [0:3];
    wire [11:0] o [0:3];
    reg [7:0] a [0:3];
    reg [7:0] cnt;

    integer i;

    always begin
        #10;
        clk = ~clk;
    end

    always_ff @ (posedge clk) begin
        cnt <= cnt + 1'b1;
    end

    PE_Lin_gen dut(.clk(clk), .rstn(rstn), .fire(fire), 
        .in_w(w), .in_a(a[0]), .outs(o));

    initial begin
        $dumpfile("lin_gen_tb.vcd");
        clk <= 0;
        rstn <= 0;
        a[0] <= 1;
        fire <= 1;



        w[0] <= 0;
        w[1] <= 1;
        w[2] <= 2;
        w[3] <= 3;

        $display("Initialized");

        #25;
        rstn <= 1;

        for (i=0; i<8; i=i+1) begin
            @(posedge clk);
            $display("i=%d\tout=%d,%d,%d,%d",i,o[0],o[1],o[2],o[3]);

            a[0] <= a[0] + 1;
        end
        
        #5;
        a[0] <= 0;
        fire <= 0;

        for (i=0; i<8; i=i+1) begin
            @(posedge clk);
            $display("i=%d\tout=%d,%d,%d,%d",i,o[0],o[1],o[2],o[3]);
        end

        $dumpvars(0, PE_TB);
        $dumpall;
        $dumpflush;
        $finish;
    end
endmodule