data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack3.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack3.v:2: syntax error, unexpected '.', expecting '['\nmodule top(...);\n           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack3.v:14: syntax error, unexpected output\n output u = !(w&v);\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top(...);
	input a,b,c,d,e,f,g,h,i,j;
	wire x = !(a&b);
	wire y = !(c|d);
	wire z = !(e|f);
	wire n0 = !(g&h);
	wire n1 = !(i|j);
	wire w = !(x&y);
	wire n2 = !(z&n0);
	wire n3 = !(n0|n1);
	wire n4 = !(n2|n3);
	wire v = !(w|n5);
	output u = !(w&v);
endmodule
module top(...);

	input a,b,c,d,e,f,g,h,i,j;
	wire x = !(a&b);
	wire y = !(c|d);
	wire z = !(e|f);
	wire n0 = !(g&h);
	wire n1 = !(i|j);
	wire w = !(x&y);
	wire n2 = !(z&n0);
	wire n3 = !(n0|n1);
	wire n4 = !(n2|n3);
	wire v = !(w|n5);
	output u = !(w&v);
endmodule