data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v
1: b'%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:22: Operator ADD expects 20 bits on the LHS, but LHS\'s VARREF \'counter\' generates 10 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            counter <= counter + 20\'d1;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:22: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 20 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            counter <= counter + 20\'d1;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:24: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            counter <= 20\'d0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:25: Operator LT expects 10 bits on the RHS, but RHS\'s VARREF \'half_divisor\' generates 6 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            clock_out <= (counter < half_divisor)?1\'b1:1\'b0;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:29: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            counter <= 20\'d0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:30: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h1\' generates 20 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n            half_divisor <= 20\'d1;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/adjustable_frequency_divider_clk_en.v:40: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h1\' generates 20 bits.\n                                                                                                                              : ... In instance adjustable_frequency_divider\n                half_divisor <= 20\'d1;\n                             ^~\n%Error: Exiting due to 7 warning(s)\n'
module adjustable_frequency_divider(
    input wire clock_in,
    input wire nreset,
    input wire step_divisor,
    output reg clock_out
    );


    parameter COUNTER_RANGE = 10;
    parameter MAX_DIVISION = 10;
    parameter DIVISOR_RANGE = 6;
    reg[COUNTER_RANGE-1:0] counter;
    reg[DIVISOR_RANGE-1:0] half_divisor;





    always @(posedge clock_in)
    begin 
        if ( nreset ) begin
            counter <= counter + 20'd1;
            if(counter>=( half_divisor*2 -1))
            counter <= 20'd0;
            clock_out <= (counter < half_divisor)?1'b1:1'b0;
        end
        else
        begin
            counter <= 20'd0;
            half_divisor <= 20'd1;
        end
    end

    always @(posedge step_divisor) begin
        if ( nreset )
        begin
            if (half_divisor*2 < MAX_DIVISION) begin
                half_divisor <= half_divisor + 1'b1;
            end else begin
                half_divisor <= 20'd1;
            end
        end
    end

endmodule
module adjustable_frequency_divider(
    input wire clock_in,
    input wire nreset,
    input wire step_divisor,
    output reg clock_out
    );



    parameter COUNTER_RANGE = 10;
    parameter MAX_DIVISION = 10;
    parameter DIVISOR_RANGE = 6;
    reg[COUNTER_RANGE-1:0] counter;
    reg[DIVISOR_RANGE-1:0] half_divisor;





    always @(posedge clock_in)
    begin 
        if ( nreset ) begin
            counter <= counter + 20'd1;
            if(counter>=( half_divisor*2 -1))
            counter <= 20'd0;
            clock_out <= (counter < half_divisor)?1'b1:1'b0;
        end
        else
        begin
            counter <= 20'd0;
            half_divisor <= 20'd1;
        end
    end

    always @(posedge step_divisor) begin
        if ( nreset )
        begin
            if (half_divisor*2 < MAX_DIVISION) begin
                half_divisor <= half_divisor + 1'b1;
            end else begin
                half_divisor <= 20'd1;
            end
        end
    end

endmodule