data/full_repos/permissive/488739248/rtl/ttl/ttl_74373.sv
data/verilator_xmls/e9da5f67-30a6-48b1-ae8f-b29470302336.xml
module ttl_74373 #(parameter DLY=12)
(
  input  wire OCn,
  input  wire C,
  input  wire [7:0] D,
  output wire [7:0] Q
);
    reg [7:0] Q_current;
    
    always_latch begin
        if (C && !OCn)
            Q_current = D;
    end

    assign #DLY Q = (OCn) ? 8'hzz : Q_current;
endmodule
module ttl_74373 #(parameter DLY=12)
(
  input  wire OCn,
  input  wire C,
  input  wire [7:0] D,
  output wire [7:0] Q
);

    reg [7:0] Q_current;
    
    always_latch begin
        if (C && !OCn)
            Q_current = D;
    end

    assign #DLY Q = (OCn) ? 8'hzz : Q_current;
endmodule