data/full_repos/permissive/47037127/cache/instructionhasher.v
1: b'%Warning-WIDTH: data/full_repos/permissive/47037127/cache/instructionhasher.v:12: Operator ASSIGNW expects 29 bits on the Assign RHS, but Assign RHS\'s SEL generates 30 bits.\n                                                                                : ... In instance instructionhasher\nassign adjustedAddr=addr[31:2];\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/47037127/cache/instructionhasher.v:14: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 29 bits.\n                                                                                : ... In instance instructionhasher\nassign OUT=adjustedAddr%64;  \n          ^\n%Error: Exiting due to 2 warning(s)\n'
module instructionhasher(
	addr,
	OUT
	);

input [31:0] addr;
output [5:0] OUT;

wire [28:0] adjustedAddr;
assign adjustedAddr=addr[31:2];

assign OUT=adjustedAddr%64;

endmodule
module instructionhasher(
	addr,
	OUT
	);


input [31:0] addr;
output [5:0] OUT;

wire [28:0] adjustedAddr;
assign adjustedAddr=addr[31:2];

assign OUT=adjustedAddr%64;

endmodule