data/full_repos/permissive/423547971/FPGA Projects/VGA Projects/VGA Clock and Calendar/new_binary_clock.v
1: b'%Error: Cannot find file containing module: Projects/VGA\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.v\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.sv\n             Projects/VGA\n             Projects/VGA.v\n             Projects/VGA.sv\n             obj_dir/Projects/VGA\n             obj_dir/Projects/VGA.v\n             obj_dir/Projects/VGA.sv\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Calendar,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Calendar/new_binary_clock.v\n%Error: Exiting due to 6 error(s)\n'
module new_binary_clock(
    input clk_100MHz,
    input reset,
    input tick_hr,
    input tick_min,
    input set_am_pm,
    output tick_1Hz,
    output am_pm,
    output end_of_day,
    output [3:0] sec_1s, sec_10s,
    output [3:0] min_1s, min_10s,
    output [3:0] hr_1s, hr_10s
    );
    

	reg a, b, c, d, e, f, g, h, i;
	wire db_hr, db_min, db_am_pm;
	

	always @(posedge clk_100MHz) begin
		a <= tick_hr;
		b <= a;
		c <= b;
	end
	assign db_hr = c;
	

	always @(posedge clk_100MHz) begin
		d <= tick_min;
		e <= d;
		f <= e;
	end
	assign db_min = f;
	

	always @(posedge clk_100MHz) begin
	   g <= set_am_pm;
	   h <= g;
	   i <= h;
	end
	assign db_am_pm = i;
	


    reg [31:0] ctr_1Hz = 32'h0;
    reg r_1Hz = 1'b0;
    
    always @(posedge clk_100MHz or posedge reset)
        if(reset)
            ctr_1Hz <= 32'h0;
        else
            if(ctr_1Hz == 49_999_999) begin
                ctr_1Hz <= 32'h0;
                r_1Hz <= ~r_1Hz;
            end
            else
                ctr_1Hz <= ctr_1Hz + 1;
     


    reg [5:0] seconds_ctr = 6'b0;
    reg [5:0] minutes_ctr = 6'b0;
    reg [3:0] hours_ctr = 4'hc;
    reg am_pm_reg = 1'b0;
    

    wire switch_am_pm = ((hours_ctr == 11) && (minutes_ctr == 59) && (seconds_ctr == 59)) ? 1 : 0;        
	

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            seconds_ctr <= 6'b0;
        else
            if(seconds_ctr == 59)
                seconds_ctr <= 6'b0;
            else
                seconds_ctr <= seconds_ctr + 1;
            

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            minutes_ctr <= 6'b0;
        else 

            if(db_min | (seconds_ctr == 59))
                if(minutes_ctr == 59)
                    minutes_ctr <= 6'b0;
                else
                    minutes_ctr <= minutes_ctr + 1;
                    

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            hours_ctr <= 4'hc;
        else 

            if(db_hr | (minutes_ctr == 59 && seconds_ctr == 59))
                if(hours_ctr == 12)
                    hours_ctr <= 4'h1;
                else
                    hours_ctr <= hours_ctr + 1;
       

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            am_pm_reg = 0;
        else

            if(db_am_pm | switch_am_pm)
                am_pm_reg <= ~am_pm_reg;   
                    


    assign sec_10s = seconds_ctr / 10;
    assign sec_1s  = seconds_ctr % 10;
    assign min_10s = minutes_ctr / 10;
    assign min_1s  = minutes_ctr % 10;
    assign hr_10s  = hours_ctr   / 10;
    assign hr_1s   = hours_ctr   % 10; 
        


    assign tick_1Hz = r_1Hz; 
    

    assign end_of_day = ((hours_ctr == 11) && (minutes_ctr == 59) && (seconds_ctr == 59) && (am_pm_reg == 1)) ? 1 : 0;
         

    assign am_pm = am_pm_reg;        
endmodule
module new_binary_clock(
    input clk_100MHz,
    input reset,
    input tick_hr,
    input tick_min,
    input set_am_pm,
    output tick_1Hz,
    output am_pm,
    output end_of_day,
    output [3:0] sec_1s, sec_10s,
    output [3:0] min_1s, min_10s,
    output [3:0] hr_1s, hr_10s
    );

    

	reg a, b, c, d, e, f, g, h, i;
	wire db_hr, db_min, db_am_pm;
	

	always @(posedge clk_100MHz) begin
		a <= tick_hr;
		b <= a;
		c <= b;
	end
	assign db_hr = c;
	

	always @(posedge clk_100MHz) begin
		d <= tick_min;
		e <= d;
		f <= e;
	end
	assign db_min = f;
	

	always @(posedge clk_100MHz) begin
	   g <= set_am_pm;
	   h <= g;
	   i <= h;
	end
	assign db_am_pm = i;
	


    reg [31:0] ctr_1Hz = 32'h0;
    reg r_1Hz = 1'b0;
    
    always @(posedge clk_100MHz or posedge reset)
        if(reset)
            ctr_1Hz <= 32'h0;
        else
            if(ctr_1Hz == 49_999_999) begin
                ctr_1Hz <= 32'h0;
                r_1Hz <= ~r_1Hz;
            end
            else
                ctr_1Hz <= ctr_1Hz + 1;
     


    reg [5:0] seconds_ctr = 6'b0;
    reg [5:0] minutes_ctr = 6'b0;
    reg [3:0] hours_ctr = 4'hc;
    reg am_pm_reg = 1'b0;
    

    wire switch_am_pm = ((hours_ctr == 11) && (minutes_ctr == 59) && (seconds_ctr == 59)) ? 1 : 0;        
	

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            seconds_ctr <= 6'b0;
        else
            if(seconds_ctr == 59)
                seconds_ctr <= 6'b0;
            else
                seconds_ctr <= seconds_ctr + 1;
            

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            minutes_ctr <= 6'b0;
        else 

            if(db_min | (seconds_ctr == 59))
                if(minutes_ctr == 59)
                    minutes_ctr <= 6'b0;
                else
                    minutes_ctr <= minutes_ctr + 1;
                    

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            hours_ctr <= 4'hc;
        else 

            if(db_hr | (minutes_ctr == 59 && seconds_ctr == 59))
                if(hours_ctr == 12)
                    hours_ctr <= 4'h1;
                else
                    hours_ctr <= hours_ctr + 1;
       

    always @(posedge tick_1Hz or posedge reset)
        if(reset)
            am_pm_reg = 0;
        else

            if(db_am_pm | switch_am_pm)
                am_pm_reg <= ~am_pm_reg;   
                    


    assign sec_10s = seconds_ctr / 10;
    assign sec_1s  = seconds_ctr % 10;
    assign min_10s = minutes_ctr / 10;
    assign min_1s  = minutes_ctr % 10;
    assign hr_10s  = hours_ctr   / 10;
    assign hr_1s   = hours_ctr   % 10; 
        


    assign tick_1Hz = r_1Hz; 
    

    assign end_of_day = ((hours_ctr == 11) && (minutes_ctr == 59) && (seconds_ctr == 59) && (am_pm_reg == 1)) ? 1 : 0;
         

    assign am_pm = am_pm_reg;        
endmodule