data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_non_pipelined_de.v
data/verilator_xmls/374ee147-69cb-46a3-b8c3-8d85b10055ca.xml
module dom1_sbox8_cfn_fr_ne (

			     f,

			     x, y, z, r, clk
			  ) ;

   output [1:0]        f;

   input [1:0] 	       x, y, z;

   input               r, clk;


   (*equivalent_register_removal = "no" *)reg [1:0]    g, t;

      always @ (negedge clk) begin
	 g[1] <= (~x[1]) & (~y[1]) ^ z[1];

	 g[0] <=   x[0]  &   y[0]  ^ z[0];


	 t[1] <= ((~x[1]) &  y[0] ) ^ r;

	 t[0] <= ((~y[1]) &  x[0] ) ^ r;

      end

   assign f[0] = t[0] ^ g[0];

   assign f[1] = t[1] ^ g[1];


   endmodule
module dom1_sbox8_cfn_fr_ne (

			     f,

			     x, y, z, r, clk
			  ) ;


   output [1:0]        f;

   input [1:0] 	       x, y, z;

   input               r, clk;


   (*equivalent_register_removal = "no" *)reg [1:0]    g, t;

      always @ (negedge clk) begin
	 g[1] <= (~x[1]) & (~y[1]) ^ z[1];

	 g[0] <=   x[0]  &   y[0]  ^ z[0];


	 t[1] <= ((~x[1]) &  y[0] ) ^ r;

	 t[0] <= ((~y[1]) &  x[0] ) ^ r;

      end

   assign f[0] = t[0] ^ g[0];

   assign f[1] = t[1] ^ g[1];


   endmodule