data/full_repos/permissive/42149584/Lab6-Part2/OneTemperatureConverter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part2/OneTemperatureConverter.v:14: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                           : ... In instance OneTemperatureConverter\n assign First1 = (Temp*18/10+32)/10;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part2/OneTemperatureConverter.v:15: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                           : ... In instance OneTemperatureConverter\n assign First0 = (Temp*18/10+32)%10;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part2/OneTemperatureConverter.v:17: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                           : ... In instance OneTemperatureConverter\n assign Second1 = Temp/10;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab6-Part2/OneTemperatureConverter.v:18: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                           : ... In instance OneTemperatureConverter\n assign Second0 = Temp%10;\n                ^\n%Error: Exiting due to 4 warning(s)\n'
module OneTemperatureConverter(Temp,First1,First0,Second1,Second0);
	input [7:0] Temp;
	output [3:0] First1, First0, Second1, Second0;
	
	assign First1 = (Temp*18/10+32)/10;
	assign First0 = (Temp*18/10+32)%10;
	
	assign Second1 = Temp/10;
	assign Second0 = Temp%10;
endmodule
module OneTemperatureConverter(Temp,First1,First0,Second1,Second0);

	input [7:0] Temp;
	output [3:0] First1, First0, Second1, Second0;
	
	assign First1 = (Temp*18/10+32)/10;
	assign First0 = (Temp*18/10+32)%10;
	
	assign Second1 = Temp/10;
	assign Second0 = Temp%10;
endmodule