data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v
1: b'%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:26: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:30: Define or directive not defined: \'`E203_PC_SIZE\'\n  input  [`E203_PC_SIZE-1:0] pc,   \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:36: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] dec_bjp_imm,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:37: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  input  [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,  \n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:48: Define or directive not defined: \'`E203_PC_SIZE\'\n  output [`E203_PC_SIZE-1:0] prdt_pc_add_op1,    \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:49: Define or directive not defined: \'`E203_PC_SIZE\'\n  output [`E203_PC_SIZE-1:0] prdt_pc_add_op2,    \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:56: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] rf2bpu_x1,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:57: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] rf2bpu_rs1,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:84: Define or directive not defined: \'`E203_XLEN\'\n  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`E203_XLEN-1]));   \n                                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:87: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH\'d0);    \n                                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:88: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH\'d1);    \n                                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:109: Define or directive not defined: \'`E203_PC_SIZE\'\n  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`E203_PC_SIZE-1:0]\n                                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:110: Define or directive not defined: \'`E203_PC_SIZE\'\n                         : (dec_jalr & dec_jalr_rs1x0) ? `E203_PC_SIZE\'b0\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:111: Define or directive not defined: \'`E203_PC_SIZE\'\n                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`E203_PC_SIZE-1:0]\n                                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:112: Define or directive not defined: \'`E203_PC_SIZE\'\n                         : rf2bpu_rs1[`E203_PC_SIZE-1:0];  \n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_ifu_litebpu.v:114: Define or directive not defined: \'`E203_PC_SIZE\'\n  assign prdt_pc_add_op2 = dec_bjp_imm[`E203_PC_SIZE-1:0];  \n                                       ^~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module e203_ifu_litebpu(

  input  [`E203_PC_SIZE-1:0] pc,


  input  dec_jal,
  input  dec_jalr,
  input  dec_bxx,
  input  [`E203_XLEN-1:0] dec_bjp_imm,
  input  [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,


  input  oitf_empty,
  input  ir_empty,
  input  ir_rs1en,
  input  jalr_rs1idx_cam_irrdidx,
  

  output bpu_wait,
  output prdt_taken,
  output [`E203_PC_SIZE-1:0] prdt_pc_add_op1,
  output [`E203_PC_SIZE-1:0] prdt_pc_add_op2,

  input  dec_i_valid,


  output bpu2rf_rs1_ena,
  input  ir_valid_clr,
  input  [`E203_XLEN-1:0] rf2bpu_x1,
  input  [`E203_XLEN-1:0] rf2bpu_rs1,

  input  clk,
  input  rst_n
  );






















  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`E203_XLEN-1]));
  

  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd0);
  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd1);
  wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);

  wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_cam_irrdidx));
  wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_empty));



  wire jalr_rs1xn_dep_ir_clr = (jalr_rs1xn_dep & oitf_empty & (~ir_empty)) & (ir_valid_clr | (~ir_rs1en));
  wire rs1xn_rdrf_r;
  wire rs1xn_rdrf_set = (~rs1xn_rdrf_r) & dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~jalr_rs1xn_dep) | jalr_rs1xn_dep_ir_clr);
  wire rs1xn_rdrf_clr = rs1xn_rdrf_r;
  wire rs1xn_rdrf_ena = rs1xn_rdrf_set |   rs1xn_rdrf_clr;
  wire rs1xn_rdrf_nxt = rs1xn_rdrf_set | (~rs1xn_rdrf_clr);

  sirv_gnrl_dfflr #(1) rs1xn_rdrf_dfflrs(rs1xn_rdrf_ena, rs1xn_rdrf_nxt, rs1xn_rdrf_r, clk, rst_n);

  assign bpu2rf_rs1_ena = rs1xn_rdrf_set;

  assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep | rs1xn_rdrf_set;

  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`E203_PC_SIZE-1:0]
                         : (dec_jalr & dec_jalr_rs1x0) ? `E203_PC_SIZE'b0
                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`E203_PC_SIZE-1:0]
                         : rf2bpu_rs1[`E203_PC_SIZE-1:0];  

  assign prdt_pc_add_op2 = dec_bjp_imm[`E203_PC_SIZE-1:0];  

endmodule
module e203_ifu_litebpu(

  input  [`E203_PC_SIZE-1:0] pc,


  input  dec_jal,
  input  dec_jalr,
  input  dec_bxx,
  input  [`E203_XLEN-1:0] dec_bjp_imm,
  input  [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,


  input  oitf_empty,
  input  ir_empty,
  input  ir_rs1en,
  input  jalr_rs1idx_cam_irrdidx,
  

  output bpu_wait,
  output prdt_taken,
  output [`E203_PC_SIZE-1:0] prdt_pc_add_op1,
  output [`E203_PC_SIZE-1:0] prdt_pc_add_op2,

  input  dec_i_valid,


  output bpu2rf_rs1_ena,
  input  ir_valid_clr,
  input  [`E203_XLEN-1:0] rf2bpu_x1,
  input  [`E203_XLEN-1:0] rf2bpu_rs1,

  input  clk,
  input  rst_n
  );























  assign prdt_taken   = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`E203_XLEN-1]));
  

  wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd0);
  wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd1);
  wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);

  wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_cam_irrdidx));
  wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_empty));



  wire jalr_rs1xn_dep_ir_clr = (jalr_rs1xn_dep & oitf_empty & (~ir_empty)) & (ir_valid_clr | (~ir_rs1en));
  wire rs1xn_rdrf_r;
  wire rs1xn_rdrf_set = (~rs1xn_rdrf_r) & dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~jalr_rs1xn_dep) | jalr_rs1xn_dep_ir_clr);
  wire rs1xn_rdrf_clr = rs1xn_rdrf_r;
  wire rs1xn_rdrf_ena = rs1xn_rdrf_set |   rs1xn_rdrf_clr;
  wire rs1xn_rdrf_nxt = rs1xn_rdrf_set | (~rs1xn_rdrf_clr);

  sirv_gnrl_dfflr #(1) rs1xn_rdrf_dfflrs(rs1xn_rdrf_ena, rs1xn_rdrf_nxt, rs1xn_rdrf_r, clk, rst_n);

  assign bpu2rf_rs1_ena = rs1xn_rdrf_set;

  assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep | rs1xn_rdrf_set;

  assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`E203_PC_SIZE-1:0]
                         : (dec_jalr & dec_jalr_rs1x0) ? `E203_PC_SIZE'b0
                         : (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`E203_PC_SIZE-1:0]
                         : rf2bpu_rs1[`E203_PC_SIZE-1:0];  

  assign prdt_pc_add_op2 = dec_bjp_imm[`E203_PC_SIZE-1:0];  

endmodule