data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_mux.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_mux.sv:20: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  DATA_T [N_INP-1:0]     inp_data_i,\n                ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_mux.sv:21: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic  [N_INP-1:0]     inp_valid_i,\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_mux.sv:22: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output logic  [N_INP-1:0]     inp_ready_o,\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_mux.sv:24: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic  [LOG_N_INP-1:0] inp_sel_i,\n                ^\n%Error: Exiting due to 4 warning(s)\n'
module stream_mux #(
  parameter type DATA_T = logic,
  parameter integer N_INP = 0,

  localparam integer LOG_N_INP = $clog2(N_INP)
) (
  input  DATA_T [N_INP-1:0]     inp_data_i,
  input  logic  [N_INP-1:0]     inp_valid_i,
  output logic  [N_INP-1:0]     inp_ready_o,

  input  logic  [LOG_N_INP-1:0] inp_sel_i,

  output DATA_T                 oup_data_o,
  output logic                  oup_valid_o,
  input  logic                  oup_ready_i
);

  always_comb begin
    inp_ready_o = '0;
    inp_ready_o[inp_sel_i] = oup_ready_i;
  end
  assign oup_data_o   = inp_data_i[inp_sel_i];
  assign oup_valid_o  = inp_valid_i[inp_sel_i];


`ifndef VERILATOR
  initial begin: p_assertions
    assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!");
  end
`endif


endmodule
module stream_mux #(
  parameter type DATA_T = logic,
  parameter integer N_INP = 0,

  localparam integer LOG_N_INP = $clog2(N_INP)
) (
  input  DATA_T [N_INP-1:0]     inp_data_i,
  input  logic  [N_INP-1:0]     inp_valid_i,
  output logic  [N_INP-1:0]     inp_ready_o,

  input  logic  [LOG_N_INP-1:0] inp_sel_i,

  output DATA_T                 oup_data_o,
  output logic                  oup_valid_o,
  input  logic                  oup_ready_i
);


  always_comb begin
    inp_ready_o = '0;
    inp_ready_o[inp_sel_i] = oup_ready_i;
  end
  assign oup_data_o   = inp_data_i[inp_sel_i];
  assign oup_valid_o  = inp_valid_i[inp_sel_i];


`ifndef VERILATOR
  initial begin: p_assertions
    assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!");
  end
`endif


endmodule