data/full_repos/permissive/469080355/sad_processor.v
data/verilator_xmls/e7ee1516-e2f9-4feb-96c5-c871b4b8dbaf.xml
module sad_processor (
        input wire [255:0] sad_results,
        input wire block_done,

        output wire [15:0] block_me
    );

    reg [15:0] last_min_sad;

endmodule
module sad_processor (
        input wire [255:0] sad_results,
        input wire block_done,

        output wire [15:0] block_me
    );


    reg [15:0] last_min_sad;

endmodule