data/full_repos/permissive/430422543/uart/src/uart_rx.v
1: b'%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:1: Cannot find include file: uart_states.vh\n`include "uart_states.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh.v\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh.sv\n             uart_states.vh\n             uart_states.vh.v\n             uart_states.vh.sv\n             obj_dir/uart_states.vh\n             obj_dir/uart_states.vh.v\n             obj_dir/uart_states.vh.sv\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:33: Define or directive not defined: \'`RESET\'\n      state = `RESET;\n              ^~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      state = `RESET;\n                    ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:37: Define or directive not defined: \'`RESET\'\n      `RESET: begin\n      ^~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:37: syntax error, unexpected \':\', expecting endcase\n      `RESET: begin\n            ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:46: Define or directive not defined: \'`IDLE\'\n          state <= `IDLE;\n                   ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          state <= `IDLE;\n                        ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:50: Define or directive not defined: \'`IDLE\'\n      `IDLE: begin\n      ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:50: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `IDLE: begin\n             ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:53: Define or directive not defined: \'`DATA_BIT\'\n          state <= `DATA_BIT;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          state <= `DATA_BIT;\n                            ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:63: Define or directive not defined: \'`RESET\'\n            state <= `RESET;\n                     ^~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            state <= `RESET;\n                           ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:69: Define or directive not defined: \'`DATA_BIT\'\n      `DATA_BIT: begin\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `DATA_BIT: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:75: Define or directive not defined: \'`STOP_BIT\'\n            state <= `STOP_BIT;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            state <= `STOP_BIT;\n                              ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:79: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:84: Define or directive not defined: \'`STOP_BIT\'\n      `STOP_BIT: begin\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:86: Define or directive not defined: \'`IDLE\'\n          state <= `IDLE;\n                   ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:94: syntax error, unexpected <=, expecting IDENTIFIER\n            error <= 1\'b1;\n                  ^~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:95: Define or directive not defined: \'`RESET\'\n            state <= `RESET;\n                     ^~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_rx.v:100: Define or directive not defined: \'`IDLE\'\n      default: state <= `IDLE;\n                        ^~~~~\n%Error: Cannot continue\n'
module uart_rx #(
  parameter PAYLOAD_SIZE = 8
)(
    input  wire       clk,  
    input  wire       enable,
    input  wire       in,   
    output reg  [PAYLOAD_SIZE-1:0] out,  
    output reg        done,
    output reg        busy, 
    output reg        error   
);
  parameter BIT_WIDTH = $clog2(PAYLOAD_SIZE);

  reg [2:0] state;
  reg [BIT_WIDTH-1:0] bit_index = 0; 
  reg [1:0] input_sw = 2'b0; 
  reg [3:0] clock_count = 4'b0;
  reg [PAYLOAD_SIZE-1:0] received_data = 0;

  initial begin
    out <= 0;
    error <= 1'b0;
    done <= 1'b0;
    busy <= 1'b0;
  end

  always @(posedge clk) begin
    input_sw = { input_sw[0], in };

    if (!enable) begin
      state = `RESET;
    end

    case (state)
      `RESET: begin
        out <= 0;
        error <= 1'b0;
        done <= 1'b0;
        busy <= 1'b0;
        bit_index <= 0;
        clock_count <= 4'b0;
        received_data <= 8'b0;
        if (enable) begin
          state <= `IDLE;
        end
      end

      `IDLE: begin
        done <= 1'b0;
        if (&clock_count) begin
          state <= `DATA_BIT;
          out <= 0;
          bit_index <= 0;
          clock_count <= 4'b0;
          received_data <= 8'b0;
          busy <= 1'b1;
          error <= 1'b0;
        end else if (!(&input_sw) || |clock_count) begin
          if (&input_sw) begin
            error <= 1'b1;
            state <= `RESET;
          end
          clock_count <= clock_count + 4'b1;
        end
      end

      `DATA_BIT: begin
        if (&clock_count) begin 
          clock_count <= 4'b0;
          received_data[bit_index] <= input_sw[0];
          if (&bit_index) begin
            bit_index <= 0;
            state <= `STOP_BIT;
          end else begin
            bit_index <= bit_index + 1;
          end
        end else begin
          clock_count <= clock_count + 4'b1;
        end
      end

      `STOP_BIT: begin
        if (&clock_count || (clock_count >= 4'h8 && !(|input_sw))) begin
          state <= `IDLE;
          done <= 1'b1;
          busy <= 1'b0;
          out <= received_data;
          clock_count <= 4'b0;
        end else begin
          clock_count <= clock_count + 1;
          if (!(|input_sw)) begin
            error <= 1'b1;
            state <= `RESET;
          end
        end
      end

      default: state <= `IDLE;
    endcase
  end
endmodule
module uart_rx #(
  parameter PAYLOAD_SIZE = 8
)(
    input  wire       clk,  
    input  wire       enable,
    input  wire       in,   
    output reg  [PAYLOAD_SIZE-1:0] out,  
    output reg        done,
    output reg        busy, 
    output reg        error   
);

  parameter BIT_WIDTH = $clog2(PAYLOAD_SIZE);

  reg [2:0] state;
  reg [BIT_WIDTH-1:0] bit_index = 0; 
  reg [1:0] input_sw = 2'b0; 
  reg [3:0] clock_count = 4'b0;
  reg [PAYLOAD_SIZE-1:0] received_data = 0;

  initial begin
    out <= 0;
    error <= 1'b0;
    done <= 1'b0;
    busy <= 1'b0;
  end

  always @(posedge clk) begin
    input_sw = { input_sw[0], in };

    if (!enable) begin
      state = `RESET;
    end

    case (state)
      `RESET: begin
        out <= 0;
        error <= 1'b0;
        done <= 1'b0;
        busy <= 1'b0;
        bit_index <= 0;
        clock_count <= 4'b0;
        received_data <= 8'b0;
        if (enable) begin
          state <= `IDLE;
        end
      end

      `IDLE: begin
        done <= 1'b0;
        if (&clock_count) begin
          state <= `DATA_BIT;
          out <= 0;
          bit_index <= 0;
          clock_count <= 4'b0;
          received_data <= 8'b0;
          busy <= 1'b1;
          error <= 1'b0;
        end else if (!(&input_sw) || |clock_count) begin
          if (&input_sw) begin
            error <= 1'b1;
            state <= `RESET;
          end
          clock_count <= clock_count + 4'b1;
        end
      end

      `DATA_BIT: begin
        if (&clock_count) begin 
          clock_count <= 4'b0;
          received_data[bit_index] <= input_sw[0];
          if (&bit_index) begin
            bit_index <= 0;
            state <= `STOP_BIT;
          end else begin
            bit_index <= bit_index + 1;
          end
        end else begin
          clock_count <= clock_count + 4'b1;
        end
      end

      `STOP_BIT: begin
        if (&clock_count || (clock_count >= 4'h8 && !(|input_sw))) begin
          state <= `IDLE;
          done <= 1'b1;
          busy <= 1'b0;
          out <= received_data;
          clock_count <= 4'b0;
        end else begin
          clock_count <= clock_count + 1;
          if (!(|input_sw)) begin
            error <= 1'b1;
            state <= `RESET;
          end
        end
      end

      default: state <= `IDLE;
    endcase
  end
endmodule