data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:65: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                            : ... In instance MemTester.u_pad_2\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:65: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                            : ... In instance MemTester.rwMod.u_pad_20\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:65: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 5 bits.\n                                                                                                            : ... In instance MemTester.rwMod.u_pad_25\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:65: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 32 bits.\n                                                                                                            : ... In instance MemTester.rwMod.u_pad_28\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:89: Input port connection \'a\' expects 32 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                            : ... In instance MemTester.rwMod\n        .a(1\'d0),\n         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:117: Input port connection \'a\' expects 5 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                             : ... In instance MemTester.rwMod\n        .a(1\'d0),\n         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MemTester/reference/MemTester.v:16: Input port connection \'a\' expects 32 bits on the pin connection, but pin connection\'s CONST \'7\'h64\' generates 7 bits.\n                                                                                                            : ... In instance MemTester\n        .a(7\'d100),\n         ^\n%Error: Exiting due to 7 warning(s)\n'
module MemTester(
    input clock,
    input reset
);
    wire [31:0] _count__q;
    wire [31:0] _count__d;
    DFF_POSCLK #(.width(32)) count (
        .q(_count__q),
        .d(_count__d),
        .clk(clock)
    );
    wire [31:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(32)) u_mux_1 (
        .y(_count__d),
        .sel(reset),
        .a(7'd100),
        .b(_WTEMP_0)
    );
    wire [32:0] _node_0;
    wire [31:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_2 (
        .y(_WTEMP_1),
        .in(1'd1)
    );
    SUB_UNSIGNED #(.width(32)) u_sub_3 (
        .y(_node_0),
        .a(_count__q),
        .b(_WTEMP_1)
    );
    wire _rwMod__clock;
    wire _rwMod__reset;
    ReadWrite rwMod (
        .clock(_rwMod__clock),
        .reset(_rwMod__reset)
    );
    TAIL #(.width(33), .n(1)) tail_32 (
        .y(_WTEMP_0),
        .in(_node_0)
    );
    assign _rwMod__clock = clock;
    assign _rwMod__reset = reset;
endmodule
module MemTester(
    input clock,
    input reset
);

    wire [31:0] _count__q;
    wire [31:0] _count__d;
    DFF_POSCLK #(.width(32)) count (
        .q(_count__q),
        .d(_count__d),
        .clk(clock)
    );
    wire [31:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(32)) u_mux_1 (
        .y(_count__d),
        .sel(reset),
        .a(7'd100),
        .b(_WTEMP_0)
    );
    wire [32:0] _node_0;
    wire [31:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_2 (
        .y(_WTEMP_1),
        .in(1'd1)
    );
    SUB_UNSIGNED #(.width(32)) u_sub_3 (
        .y(_node_0),
        .a(_count__q),
        .b(_WTEMP_1)
    );
    wire _rwMod__clock;
    wire _rwMod__reset;
    ReadWrite rwMod (
        .clock(_rwMod__clock),
        .reset(_rwMod__reset)
    );
    TAIL #(.width(33), .n(1)) tail_32 (
        .y(_WTEMP_0),
        .in(_node_0)
    );
    assign _rwMod__clock = clock;
    assign _rwMod__reset = reset;
endmodule