data/full_repos/permissive/456771003/common.v
data/verilator_xmls/33025a73-a56d-41c8-936e-a7c70b74376f.xml
module ff_ar
#(
    parameter W=1,
    parameter RESET_VAL=0
)
(
    input wire clk,
    input wire rst,
    input wire [W-1:0] d,
    output reg [W-1:0] q
);

    always @(posedge clk, posedge rst) begin
        if (rst) begin
            q <= RESET_VAL;
        end else begin
            q <= d;
        end
    end

endmodule
module ff_ar
#(
    parameter W=1,
    parameter RESET_VAL=0
)
(
    input wire clk,
    input wire rst,
    input wire [W-1:0] d,
    output reg [W-1:0] q
);


    always @(posedge clk, posedge rst) begin
        if (rst) begin
            q <= RESET_VAL;
        end else begin
            q <= d;
        end
    end

endmodule