data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:num_ports-1] mask;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:42: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:num_ports-1] req;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:45: Little bit endian vector: MSB < LSB of bit range: 0:31\n   output [0:num_ports-1] gnt;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:48: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   req_qual;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:51: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   gnt_qual;\n        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:52: Cannot find file containing module: \'c_lod\'\n   c_lod\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_lod\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_lod.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_lod.sv\n             c_lod\n             c_lod.v\n             c_lod.sv\n             obj_dir/c_lod\n             obj_dir/c_lod.v\n             obj_dir/c_lod.sv\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:58: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   req_unqual;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:61: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   gnt_unqual;\n        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter_base.v:62: Cannot find file containing module: \'c_lod\'\n   c_lod\n   ^~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module c_rr_arbiter_base
  (mask, req, gnt);
   

   parameter num_ports = 32;
   

   input [0:num_ports-1] mask;
   

   input [0:num_ports-1] req;
   

   output [0:num_ports-1] gnt;
   wire [0:num_ports-1]   gnt;
   
   wire [0:num_ports-1]   req_qual;
   assign req_qual = req & mask;
   
   wire [0:num_ports-1]   gnt_qual;
   c_lod
     #(.width(num_ports))
   gnt_qual_lod
     (.data_in(req_qual),
      .data_out(gnt_qual));
   
   wire [0:num_ports-1]   req_unqual;
   assign req_unqual = req;
   
   wire [0:num_ports-1]   gnt_unqual;
   c_lod
     #(.width(num_ports))
   gnt_unqual_lod
     (.data_in(req_unqual),
      .data_out(gnt_unqual));
   
   assign gnt = (|req_qual) ? gnt_qual : gnt_unqual;
   
endmodule
module c_rr_arbiter_base
  (mask, req, gnt);

   

   parameter num_ports = 32;
   

   input [0:num_ports-1] mask;
   

   input [0:num_ports-1] req;
   

   output [0:num_ports-1] gnt;
   wire [0:num_ports-1]   gnt;
   
   wire [0:num_ports-1]   req_qual;
   assign req_qual = req & mask;
   
   wire [0:num_ports-1]   gnt_qual;
   c_lod
     #(.width(num_ports))
   gnt_qual_lod
     (.data_in(req_qual),
      .data_out(gnt_qual));
   
   wire [0:num_ports-1]   req_unqual;
   assign req_unqual = req;
   
   wire [0:num_ports-1]   gnt_unqual;
   c_lod
     #(.width(num_ports))
   gnt_unqual_lod
     (.data_in(req_unqual),
      .data_out(gnt_unqual));
   
   assign gnt = (|req_qual) ? gnt_qual : gnt_unqual;
   
endmodule