data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v
1: b"%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:325: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;\n                                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:392: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin\n                                       ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module GameData (input clk, input reset,
    output reg [7:0] odata, output reg odata_clk
    );


    reg [7:0] INES[32*1024-1:0];
    reg [21:0] INES_SIZE = 24719; 
    initial $readmemh("BattleCity.nes.hex", INES);

    reg [1:0] state = 0;
    reg [21:0] addr = 0;
    reg out_clk = 0;

    always @(posedge clk) begin
        if (reset) begin
            state <= 1;
            addr <= 0;
            odata_clk <= 0;
        end else if (state==1) begin
            if (addr == INES_SIZE) begin

                state <= 2;
                odata_clk <= 0;
            end else begin

                odata <= INES[addr];
                odata_clk <= 1;
                addr <= addr + 1;
            end
        end
    end
endmodule
module GameData (input clk, input reset,
    output reg [7:0] odata, output reg odata_clk
    );



    reg [7:0] INES[32*1024-1:0];
    reg [21:0] INES_SIZE = 24719; 
    initial $readmemh("BattleCity.nes.hex", INES);

    reg [1:0] state = 0;
    reg [21:0] addr = 0;
    reg out_clk = 0;

    always @(posedge clk) begin
        if (reset) begin
            state <= 1;
            addr <= 0;
            odata_clk <= 0;
        end else if (state==1) begin
            if (addr == INES_SIZE) begin

                state <= 2;
                odata_clk <= 0;
            end else begin

                odata <= INES[addr];
                odata_clk <= 1;
                addr <= addr + 1;
            end
        end
    end
endmodule