data/full_repos/permissive/434840709/USTB_verilog_elevator/src/key_input.v
data/verilator_xmls/a2d78b58-c35b-4fa3-8a66-7a9598ef9225.xml
module key_input #(parameter W = 8) (
    input clk,
    input [W - 1:0] keys,
    output reg [W - 1: 0] key_press = 0
);

reg [W - 1: 0] prev = 0;

always @(posedge clk) begin
    key_press <= prev ^ keys;
    prev <= keys;
end

endmodule
module key_input #(parameter W = 8) (
    input clk,
    input [W - 1:0] keys,
    output reg [W - 1: 0] key_press = 0
);


reg [W - 1: 0] prev = 0;

always @(posedge clk) begin
    key_press <= prev ^ keys;
    prev <= keys;
end

endmodule