data/full_repos/permissive/473722449/JKFF.v
data/verilator_xmls/094f1d80-609e-4711-808f-e5f0b8d6ec00.xml
module JKFF(
    input j,
    input k,
    output reg q,
    input clk
    );
    always@(posedge clk)
    begin
       case({j,k})
       2'b00:q=q;
       2'b01:q=0; 
       2'b10:q=1;
       2'b11:q=~q;
       endcase
    end
endmodule
module JKFF(
    input j,
    input k,
    output reg q,
    input clk
    );

    always@(posedge clk)
    begin
       case({j,k})
       2'b00:q=q;
       2'b01:q=0; 
       2'b10:q=1;
       2'b11:q=~q;
       endcase
    end
endmodule