data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module hazard_unit #(parameter addr_width = 8)(
    input clk,
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] EX_rd,
    input EX_MemRead,
    output reg PCWrite,
    output reg IF_ID_Write,
    output reg hazard
);
    initial begin PCWrite = 1; IF_ID_Write = 1; hazard = 0; end
    always @(negedge clk) begin
        if (EX_MemRead == 1 & EX_rd != 0 & (rs1 == EX_rd | rs2 == EX_rd)) begin
            {PCWrite, IF_ID_Write, hazard} <= 3'b001;
        end
        else begin {PCWrite, IF_ID_Write, hazard} <= 3'b110; end
    end
endmodule
module hazard_unit #(parameter addr_width = 8)(
    input clk,
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] EX_rd,
    input EX_MemRead,
    output reg PCWrite,
    output reg IF_ID_Write,
    output reg hazard
);

    initial begin PCWrite = 1; IF_ID_Write = 1; hazard = 0; end
    always @(negedge clk) begin
        if (EX_MemRead == 1 & EX_rd != 0 & (rs1 == EX_rd | rs2 == EX_rd)) begin
            {PCWrite, IF_ID_Write, hazard} <= 3'b001;
        end
        else begin {PCWrite, IF_ID_Write, hazard} <= 3'b110; end
    end
endmodule