data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:186: Cannot find file containing module: \'pconfigx\'\npconfigx #(16,16\'b0000_0001_0100_0000) mg_reg0   \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core,data/full_repos/permissive/530013823/pconfigx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core,data/full_repos/permissive/530013823/pconfigx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core,data/full_repos/permissive/530013823/pconfigx.sv\n             pconfigx\n             pconfigx.v\n             pconfigx.sv\n             obj_dir/pconfigx\n             obj_dir/pconfigx.v\n             obj_dir/pconfigx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:221: Cannot find file containing module: \'pconfigx\'\npconfigx #(16,16\'b1000_0000_0010_0000) mg_reg4  \n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:290: Cannot find file containing module: \'fflopx\'\nfflopx #(16)plcfout4 (clk, rst_, cfout4[15:0], adv_abi[16:1]);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:301: Cannot find file containing module: \'fflopx\'\nfflopx #(1) plpact (clk, rst_,upactive, spact);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:325: Cannot find file containing module: \'fflopx\'\nfflopx #(1) planen(clk, rst_,an_enable, san_enable); \n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:330: Cannot find file containing module: \'fflopx\'\nfflopx #(1) planrst (clk, rst_,an_rest, san_rest); \n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:336: Cannot find file containing module: \'pconfigx\'\npconfigx #(1,1\'b1) ignore_link  \n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:522: Cannot find file containing module: \'fflopx\'\nfflopx #(16) plnp_tx_dat (clk, rst_,np_tx_dat,snp_tx_dat);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:528: Cannot find file containing module: \'pconfigx\'\npconfigx #(16,16\'b0) mg_reg7   \n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_autoneg.v:617: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                                                                     : ... In instance ippcsge_autoneg\n        if (rudi != RUDI_I)         idle_cnt <= 2\'b0;\n                                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module ippcsge_autoneg
    (
     clk,
     clk19m,
     rst_,
     sync,
     rudi,
     rx_cfdata,
     tx_cfdata,
     xmit,
     an_state,
     an_complete,

     upa,
     upen,
     upactive,
     uprs,
     upws,
     updi,
     updo,
     uprdy

     );



input           clk, rst_, sync;
input           clk19m;

input [1:0]     rudi;

input [15:0]    rx_cfdata;
output [15:0]   tx_cfdata;
output [1:0]    xmit;
output [3:0]    an_state;
output          an_complete;


input [4:0]     upa;
input           upen;
input           upactive;
input           uprs,upws;
input [15:0]    updi;
output [15:0]   updo;
output          uprdy;







parameter       XMIT_IDL = 2'd0;
parameter       XMIT_CFG = 2'd1;
parameter       XMIT_DAT = 2'd2;

parameter       AN_ENABLE       = 4'd0;
parameter       AN_RESTART      = 4'd1;
parameter       AN_DIS_LINK_OK  = 4'd2;
parameter       ABILITY_DET     = 4'd3;
parameter       ACK_DET         = 4'd4;
parameter       NEXT_PAGE_WAIT  = 4'd5;
parameter       COMPLETE_ACK    = 4'd6;
parameter       IDLE_DET        = 4'd7;
parameter       LINK_OK         = 4'd8;

parameter       RUDI_INVLD  = 2'b11;
parameter       RUDI_I      = 2'b10;
parameter       RUDI_C      = 2'b01;

parameter       TIMER_DONE_VAL = 21'd1250000;

parameter       ADV_ABILITY = 16'b0000_00000_0010_0000;



wire [16:1]     adv_abi;
wire [16:1]     np_tx;
wire            np_ena;




wire [16:1]     lp_adv_abi;
wire [16:1]     lp_np_rx;


wire            abi_match;
wire            ack_match;
wire            consist_match;
wire            txcf_NP;

wire            idle_match;


reg             page_rx;
reg             bp_rx;

reg             an_complete;
reg [3:0]       an_state;

reg [15:0]      tx_cfdata;
reg [1:0]       xmit;
reg             np_loaded;
reg             np_rx;
reg             toggle_rx;
reg             toggle_tx;
reg [15:0]      lrx_cfdata;





wire [15:0]     lpen;




assign          lpen[0] = upen & (upa == 5'd0);




assign          lpen[1] = upen & (upa == 5'd1);

assign          lpen[2] = upen & (upa == 5'd2);
assign          lpen[3] = upen & (upa == 5'd3);






assign          lpen[4] = upen & (upa == 5'd4);


assign          lpen[5] = upen & (upa == 5'd5);





assign          lpen[6] = upen & (upa == 5'd6);






assign          lpen[7]  = upen & (upa == 5'd7);


assign          lpen[8]  = upen & (upa == 5'd8);


assign          lpen[9]  = upen & (upa == 5'd9);

assign          lpen[10] = upen & (upa == 5'd10);
assign          lpen[11] = upen & (upa == 5'd11);
assign          lpen[12] = upen & (upa == 5'd12);
assign          lpen[13] = upen & (upa == 5'd13);
assign          lpen[14] = upen & (upa == 5'd14);
assign          lpen[15] = upen & (upa == 5'd15);

wire [15:0]     pdo0, pdo1, pdo2, pdo3, pdo4, pdo5, pdo6, 
                pdo7, pdo8, pdo9, pdo10, pdo11, pdo12, pdo13, pdo14, pdo15;

wire [15:0]     cfout0, cfout4;

wire [15:0]     reg0,reg4;


pconfigx #(16,16'b0000_0001_0100_0000) mg_reg0
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[0]),
     .upws(upws),
     .updi(updi),
     .out(cfout0),
     .updo(reg0)
     );

assign          pdo0 = lpen[0]? reg0 : 16'b0;

reg [1:0]       reg1;

always @(posedge clk or negedge rst_)
    if(!rst_) reg1 <= 2'b0;
    else if(!upactive) 
        reg1 <= lpen[1]& upws? {updi[5],updi[2]}: reg1;
    else
        reg1 <= {an_complete,(xmit == XMIT_DAT)};

assign          pdo1 = lpen[1]? {10'b0,reg1[1],2'b00,reg1[0],2'b0} : 16'b0;

pconfigx #(16,16'b1000_0000_0010_0000) mg_reg4  
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[4]),
     .upws(upws),
     .updi(updi),
     .out(cfout4),
     .updo(reg4)
     );

assign          pdo4 = lpen[4]? reg4 : 16'b0;



reg [15:0]      slp_np_rx,slp_adv_abi;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        slp_adv_abi  <= 16'b0;
        slp_np_rx    <= 16'b0;
        end
    else
        if(!upactive)
            begin
            slp_np_rx   <= lpen[8] &upws? updi[15:0] : slp_np_rx;
            slp_adv_abi <= lpen[5] &upws? updi[15:0] : slp_adv_abi;
            end 
        else 
            begin
            slp_np_rx    <= lp_np_rx;
            slp_adv_abi  <= lp_adv_abi;
            end
    end



wire    state_cmpack;
assign  state_cmpack = (an_state == COMPLETE_ACK);

assign  lp_adv_abi  =   (state_cmpack& bp_rx)? lrx_cfdata: slp_adv_abi;
assign  lp_np_rx    =   (state_cmpack& np_rx)? lrx_cfdata: slp_np_rx;



assign          pdo5  = lpen[5]? slp_adv_abi : 16'b0;
assign          pdo8  = lpen[8]? slp_np_rx   : 16'b0;

reg [1:0]       reg6;
assign          np_ena = adv_abi[16]& np_tx[16];

always @(posedge clk or negedge rst_)
    if(!rst_) reg6 <= 2'b0;
    else if(!upactive) reg6 <= lpen[6]& upws? {updi[2],updi[1]} : reg6;
    else               reg6 <= {np_ena, page_rx};

assign          pdo6 = lpen[6]? {13'b0, reg6[1:0], 1'b0} : 16'b0;


fflopx #(16)plcfout4 (clk, rst_, cfout4[15:0], adv_abi[16:1]);

reg [20:0]      link_timer;


wire            start_link_timer;

wire            link_timer_done;
assign          link_timer_done = (link_timer == TIMER_DONE_VAL);

wire            spact;
fflopx #(1) plpact (clk, rst_,upactive, spact);

assign          start_link_timer = (an_state == AN_RESTART)|(an_state == COMPLETE_ACK)|(an_state == IDLE_DET);

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)                  link_timer <= 21'b0;
    else
        begin
        if(spact)
            if (!start_link_timer) link_timer <= 21'b0;
            else                   link_timer <= link_timer_done       ? 
                                                 (an_state == IDLE_DET)? 21'b0: link_timer: link_timer + 1'b1;
        end
    end



wire            an_rest;
wire            an_enable;

assign          an_enable   = cfout0[12];

wire            san_enable;
fflopx #(1) planen(clk, rst_,an_enable, san_enable);

assign          an_rest     = cfout0[9];

wire            san_rest;
fflopx #(1) planrst (clk, rst_,an_rest, san_rest);


wire            cfout9;
wire            reg9;

pconfigx #(1,1'b1) ignore_link  
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[9]),
     .upws(upws),
     .updi(updi[0]),
     .out(cfout9),
     .updo(reg9)
     );

reg [20:0]      sync_timer;

wire            sync_timer_done;
assign          sync_timer_done = (sync_timer == 21'd1500000);


always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)        sync_timer <= 21'b0;
    else
        begin
        if(spact)
            if (sync)  sync_timer <= 21'b0;
            else       sync_timer <= sync_timer_done? sync_timer: sync_timer + 1'b1;
        end
    end

wire            sync_fail;
assign          sync_fail = (!sync)& sync_timer_done;

wire            rudi_fail;
assign          rudi_fail = (rudi == RUDI_INVLD);

wire            link_err;
assign          link_err  = (!cfout9& (sync_fail| rudi_fail) );

assign          pdo9 = lpen[9]? {15'd0,reg9}: 16'b0;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)  an_state <= AN_ENABLE;
    else if (san_rest | link_err|(!spact))
        begin
        an_state <= AN_ENABLE;
        end
    else
        case (an_state)
            AN_ENABLE:
                begin
                if (san_enable)  an_state <= AN_RESTART;
                else             an_state <= AN_DIS_LINK_OK;
                end
            AN_RESTART:
                begin
                if (link_timer_done)    an_state <= ABILITY_DET;
                end
            ABILITY_DET:
                begin
                if (abi_match & (|lrx_cfdata))   an_state <= ACK_DET;
                end
            ACK_DET:
                begin
                if (ack_match & consist_match)                                           an_state <= COMPLETE_ACK;
                else if ((ack_match & ~consist_match) | (abi_match & ~(|lrx_cfdata)))    an_state <= AN_ENABLE;
                end
            COMPLETE_ACK:
                begin
                if (abi_match & ~(|lrx_cfdata))                                          an_state <= AN_ENABLE;
                else if (link_timer_done & adv_abi[16] & lp_adv_abi[16] & np_loaded &
                         (txcf_NP | np_rx) & (~abi_match | (|lrx_cfdata)))               an_state <= NEXT_PAGE_WAIT;
                else if (((link_timer_done & (~adv_abi[16] | ~lp_adv_abi[16])) |
                         (link_timer_done & adv_abi[16] & lp_adv_abi[16] & ~txcf_NP & ~np_rx)) &
                         (~abi_match | (|lrx_cfdata)))                                   an_state <= IDLE_DET;               
                end
            NEXT_PAGE_WAIT:
                begin
                if (abi_match & (toggle_rx ^ lrx_cfdata[11]) & (|lrx_cfdata))            an_state <= ACK_DET;
                else if (abi_match & ~(|lrx_cfdata))                                     an_state <= AN_ENABLE;
                end
            IDLE_DET:
                begin
                if (abi_match & ~(|lrx_cfdata))          an_state <= AN_ENABLE;
                else if (link_timer_done & idle_match)   an_state <= LINK_OK;
                end
            LINK_OK:
                begin
                if (abi_match)      an_state <= AN_ENABLE;
                else                an_state <= LINK_OK;
                end
            default:                an_state <= AN_DIS_LINK_OK;
        endcase
    end



always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        page_rx         <= 1'b0;
        an_complete     <= 1'b0;
        tx_cfdata       <= 16'b0;
        xmit            <= XMIT_IDL;
        np_rx           <= 1'b0;
        bp_rx           <= 1'b0;
        toggle_rx       <= 1'b0;
        toggle_tx       <= 1'b0;
        end 
    else
        case (an_state)
            AN_ENABLE:
                begin
                page_rx     <= 1'b0;
                an_complete <= 1'b0;
                if (san_enable)
                    begin
                    tx_cfdata   <= 16'b0;
                    xmit        <= XMIT_CFG;
                    end
                else    xmit    <= XMIT_IDL;
                end
            AN_RESTART:
                begin
                tx_cfdata       <= 16'b0;
                xmit            <= XMIT_CFG;  
                bp_rx           <= 1'b1;
                np_rx           <= 1'b0;
                end
            AN_DIS_LINK_OK:
                begin
                xmit <= XMIT_DAT;
                end
            ABILITY_DET:
                begin
                toggle_tx       <= adv_abi[12];
                tx_cfdata       <= {adv_abi[16],1'b0,adv_abi[14:1]};
                end
            ACK_DET:
                begin
                tx_cfdata[14] <= 1'b1;              
                end
            COMPLETE_ACK:
                begin
                toggle_tx   <= !tx_cfdata[11];
                toggle_rx   <= page_rx? toggle_rx: lrx_cfdata[11];
                np_rx       <= page_rx? np_rx    : lrx_cfdata[15];
                page_rx     <= 1'b1;
                end
            NEXT_PAGE_WAIT:
                begin
                tx_cfdata   <= {np_tx[16],1'b0,np_tx[14:13],toggle_tx,np_tx[11:1]};
                page_rx     <= 1'b0;
                bp_rx       <= 1'b0;
                end
            IDLE_DET:
                begin
                xmit            <= XMIT_IDL;
                end
            LINK_OK:
                begin
                xmit            <= XMIT_DAT;
                an_complete     <= 1'b1;
                end
        endcase
    end
 






wire   np_tx_ind;
assign np_tx_ind =  lpen[7]& upws;

reg    snp_tx_ind;
always @(posedge clk or negedge rst_)
    if(!rst_)
        snp_tx_ind <= 1'b0;
    else
        snp_tx_ind <= np_tx_ind;


wire [15:0] np_tx_dat;
wire [15:0]  snp_tx_dat;
fflopx #(16) plnp_tx_dat (clk, rst_,np_tx_dat,snp_tx_dat);

assign      np_tx[16:1] = snp_tx_dat;

wire [15:0] reg7;

pconfigx #(16,16'b0) mg_reg7
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[7]),
     .upws(upws),
     .updi(updi),
     .out(np_tx_dat),
     .updo(reg7)
     );

assign      pdo7 = lpen[7]? reg7 : 16'b0;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        np_loaded   <= 1'b0;
        end
    else if ((an_state == AN_RESTART) | (an_state == NEXT_PAGE_WAIT))
        begin
        np_loaded   <= 1'b0;
        end
    else if(snp_tx_ind)
        begin
        np_loaded   <= 1'b1;
        end
    else if(!txcf_NP)  np_loaded <= np_rx;
    
    end


assign txcf_NP = tx_cfdata[15];




always @(posedge clk or negedge rst_)
    if(!rst_)
        lrx_cfdata <= 16'b0;
    else
        lrx_cfdata <= rx_cfdata;

wire    pre_abi_match;
assign  pre_abi_match = ({rx_cfdata[15],rx_cfdata[13:0]} == {lrx_cfdata[15],lrx_cfdata[13:0]});


reg [3:0] abi_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          abi_cnt <= 4'b0;
    else if ((rudi == RUDI_INVLD) | (rudi == RUDI_I))    abi_cnt <= 4'b0;
    else if (~pre_abi_match)           abi_cnt <= 4'b0;    
    else if (pre_abi_match )           abi_cnt <= abi_match? abi_cnt : abi_cnt + 1'b1;
    end

assign abi_match = (abi_cnt == 4'd11);

reg [15:0] labi_match;

always @(posedge clk or negedge rst_)
    if(!rst_)
        labi_match <= 16'b0;
    else 
        if(abi_match) labi_match <= lrx_cfdata;


wire       pre_ack_match;
assign     pre_ack_match = pre_abi_match & rx_cfdata[14]& lrx_cfdata[14];

reg [3:0]  ack_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          ack_cnt <= 4'b0;
    else if ((rudi == RUDI_INVLD) | (rudi == RUDI_I))   ack_cnt <= 4'b0;
    else if (~pre_ack_match)                            ack_cnt <= 4'b0;    
    else if (pre_ack_match )                            ack_cnt <= ack_match? ack_cnt : ack_cnt + 1'b1;
    end

assign ack_match = (ack_cnt == 4'd11);

assign consist_match = ack_match& (lrx_cfdata == labi_match);
       
reg [2:0] idle_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          idle_cnt <= 3'b0;
    else 
        begin
        if (rudi != RUDI_I)         idle_cnt <= 2'b0;
        else if (idle_cnt < 3'd5)   idle_cnt <= idle_cnt + 1'b1;
        end
    end

assign     idle_match = (idle_cnt == 3'd5);



assign updo  = pdo0| pdo1| pdo4| pdo5| pdo6| pdo7| pdo8| pdo9;

assign uprdy = (|lpen) & (upws| uprs);

endmodule
module ippcsge_autoneg
    (
     clk,
     clk19m,
     rst_,
     sync,
     rudi,
     rx_cfdata,
     tx_cfdata,
     xmit,
     an_state,
     an_complete,

     upa,
     upen,
     upactive,
     uprs,
     upws,
     updi,
     updo,
     uprdy

     );




input           clk, rst_, sync;
input           clk19m;

input [1:0]     rudi;

input [15:0]    rx_cfdata;
output [15:0]   tx_cfdata;
output [1:0]    xmit;
output [3:0]    an_state;
output          an_complete;


input [4:0]     upa;
input           upen;
input           upactive;
input           uprs,upws;
input [15:0]    updi;
output [15:0]   updo;
output          uprdy;







parameter       XMIT_IDL = 2'd0;
parameter       XMIT_CFG = 2'd1;
parameter       XMIT_DAT = 2'd2;

parameter       AN_ENABLE       = 4'd0;
parameter       AN_RESTART      = 4'd1;
parameter       AN_DIS_LINK_OK  = 4'd2;
parameter       ABILITY_DET     = 4'd3;
parameter       ACK_DET         = 4'd4;
parameter       NEXT_PAGE_WAIT  = 4'd5;
parameter       COMPLETE_ACK    = 4'd6;
parameter       IDLE_DET        = 4'd7;
parameter       LINK_OK         = 4'd8;

parameter       RUDI_INVLD  = 2'b11;
parameter       RUDI_I      = 2'b10;
parameter       RUDI_C      = 2'b01;

parameter       TIMER_DONE_VAL = 21'd1250000;

parameter       ADV_ABILITY = 16'b0000_00000_0010_0000;



wire [16:1]     adv_abi;
wire [16:1]     np_tx;
wire            np_ena;




wire [16:1]     lp_adv_abi;
wire [16:1]     lp_np_rx;


wire            abi_match;
wire            ack_match;
wire            consist_match;
wire            txcf_NP;

wire            idle_match;


reg             page_rx;
reg             bp_rx;

reg             an_complete;
reg [3:0]       an_state;

reg [15:0]      tx_cfdata;
reg [1:0]       xmit;
reg             np_loaded;
reg             np_rx;
reg             toggle_rx;
reg             toggle_tx;
reg [15:0]      lrx_cfdata;





wire [15:0]     lpen;




assign          lpen[0] = upen & (upa == 5'd0);




assign          lpen[1] = upen & (upa == 5'd1);

assign          lpen[2] = upen & (upa == 5'd2);
assign          lpen[3] = upen & (upa == 5'd3);






assign          lpen[4] = upen & (upa == 5'd4);


assign          lpen[5] = upen & (upa == 5'd5);





assign          lpen[6] = upen & (upa == 5'd6);






assign          lpen[7]  = upen & (upa == 5'd7);


assign          lpen[8]  = upen & (upa == 5'd8);


assign          lpen[9]  = upen & (upa == 5'd9);

assign          lpen[10] = upen & (upa == 5'd10);
assign          lpen[11] = upen & (upa == 5'd11);
assign          lpen[12] = upen & (upa == 5'd12);
assign          lpen[13] = upen & (upa == 5'd13);
assign          lpen[14] = upen & (upa == 5'd14);
assign          lpen[15] = upen & (upa == 5'd15);

wire [15:0]     pdo0, pdo1, pdo2, pdo3, pdo4, pdo5, pdo6, 
                pdo7, pdo8, pdo9, pdo10, pdo11, pdo12, pdo13, pdo14, pdo15;

wire [15:0]     cfout0, cfout4;

wire [15:0]     reg0,reg4;


pconfigx #(16,16'b0000_0001_0100_0000) mg_reg0
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[0]),
     .upws(upws),
     .updi(updi),
     .out(cfout0),
     .updo(reg0)
     );

assign          pdo0 = lpen[0]? reg0 : 16'b0;

reg [1:0]       reg1;

always @(posedge clk or negedge rst_)
    if(!rst_) reg1 <= 2'b0;
    else if(!upactive) 
        reg1 <= lpen[1]& upws? {updi[5],updi[2]}: reg1;
    else
        reg1 <= {an_complete,(xmit == XMIT_DAT)};

assign          pdo1 = lpen[1]? {10'b0,reg1[1],2'b00,reg1[0],2'b0} : 16'b0;

pconfigx #(16,16'b1000_0000_0010_0000) mg_reg4  
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[4]),
     .upws(upws),
     .updi(updi),
     .out(cfout4),
     .updo(reg4)
     );

assign          pdo4 = lpen[4]? reg4 : 16'b0;



reg [15:0]      slp_np_rx,slp_adv_abi;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        slp_adv_abi  <= 16'b0;
        slp_np_rx    <= 16'b0;
        end
    else
        if(!upactive)
            begin
            slp_np_rx   <= lpen[8] &upws? updi[15:0] : slp_np_rx;
            slp_adv_abi <= lpen[5] &upws? updi[15:0] : slp_adv_abi;
            end 
        else 
            begin
            slp_np_rx    <= lp_np_rx;
            slp_adv_abi  <= lp_adv_abi;
            end
    end



wire    state_cmpack;
assign  state_cmpack = (an_state == COMPLETE_ACK);

assign  lp_adv_abi  =   (state_cmpack& bp_rx)? lrx_cfdata: slp_adv_abi;
assign  lp_np_rx    =   (state_cmpack& np_rx)? lrx_cfdata: slp_np_rx;



assign          pdo5  = lpen[5]? slp_adv_abi : 16'b0;
assign          pdo8  = lpen[8]? slp_np_rx   : 16'b0;

reg [1:0]       reg6;
assign          np_ena = adv_abi[16]& np_tx[16];

always @(posedge clk or negedge rst_)
    if(!rst_) reg6 <= 2'b0;
    else if(!upactive) reg6 <= lpen[6]& upws? {updi[2],updi[1]} : reg6;
    else               reg6 <= {np_ena, page_rx};

assign          pdo6 = lpen[6]? {13'b0, reg6[1:0], 1'b0} : 16'b0;


fflopx #(16)plcfout4 (clk, rst_, cfout4[15:0], adv_abi[16:1]);

reg [20:0]      link_timer;


wire            start_link_timer;

wire            link_timer_done;
assign          link_timer_done = (link_timer == TIMER_DONE_VAL);

wire            spact;
fflopx #(1) plpact (clk, rst_,upactive, spact);

assign          start_link_timer = (an_state == AN_RESTART)|(an_state == COMPLETE_ACK)|(an_state == IDLE_DET);

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)                  link_timer <= 21'b0;
    else
        begin
        if(spact)
            if (!start_link_timer) link_timer <= 21'b0;
            else                   link_timer <= link_timer_done       ? 
                                                 (an_state == IDLE_DET)? 21'b0: link_timer: link_timer + 1'b1;
        end
    end



wire            an_rest;
wire            an_enable;

assign          an_enable   = cfout0[12];

wire            san_enable;
fflopx #(1) planen(clk, rst_,an_enable, san_enable);

assign          an_rest     = cfout0[9];

wire            san_rest;
fflopx #(1) planrst (clk, rst_,an_rest, san_rest);


wire            cfout9;
wire            reg9;

pconfigx #(1,1'b1) ignore_link  
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[9]),
     .upws(upws),
     .updi(updi[0]),
     .out(cfout9),
     .updo(reg9)
     );

reg [20:0]      sync_timer;

wire            sync_timer_done;
assign          sync_timer_done = (sync_timer == 21'd1500000);


always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)        sync_timer <= 21'b0;
    else
        begin
        if(spact)
            if (sync)  sync_timer <= 21'b0;
            else       sync_timer <= sync_timer_done? sync_timer: sync_timer + 1'b1;
        end
    end

wire            sync_fail;
assign          sync_fail = (!sync)& sync_timer_done;

wire            rudi_fail;
assign          rudi_fail = (rudi == RUDI_INVLD);

wire            link_err;
assign          link_err  = (!cfout9& (sync_fail| rudi_fail) );

assign          pdo9 = lpen[9]? {15'd0,reg9}: 16'b0;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)  an_state <= AN_ENABLE;
    else if (san_rest | link_err|(!spact))
        begin
        an_state <= AN_ENABLE;
        end
    else
        case (an_state)
            AN_ENABLE:
                begin
                if (san_enable)  an_state <= AN_RESTART;
                else             an_state <= AN_DIS_LINK_OK;
                end
            AN_RESTART:
                begin
                if (link_timer_done)    an_state <= ABILITY_DET;
                end
            ABILITY_DET:
                begin
                if (abi_match & (|lrx_cfdata))   an_state <= ACK_DET;
                end
            ACK_DET:
                begin
                if (ack_match & consist_match)                                           an_state <= COMPLETE_ACK;
                else if ((ack_match & ~consist_match) | (abi_match & ~(|lrx_cfdata)))    an_state <= AN_ENABLE;
                end
            COMPLETE_ACK:
                begin
                if (abi_match & ~(|lrx_cfdata))                                          an_state <= AN_ENABLE;
                else if (link_timer_done & adv_abi[16] & lp_adv_abi[16] & np_loaded &
                         (txcf_NP | np_rx) & (~abi_match | (|lrx_cfdata)))               an_state <= NEXT_PAGE_WAIT;
                else if (((link_timer_done & (~adv_abi[16] | ~lp_adv_abi[16])) |
                         (link_timer_done & adv_abi[16] & lp_adv_abi[16] & ~txcf_NP & ~np_rx)) &
                         (~abi_match | (|lrx_cfdata)))                                   an_state <= IDLE_DET;               
                end
            NEXT_PAGE_WAIT:
                begin
                if (abi_match & (toggle_rx ^ lrx_cfdata[11]) & (|lrx_cfdata))            an_state <= ACK_DET;
                else if (abi_match & ~(|lrx_cfdata))                                     an_state <= AN_ENABLE;
                end
            IDLE_DET:
                begin
                if (abi_match & ~(|lrx_cfdata))          an_state <= AN_ENABLE;
                else if (link_timer_done & idle_match)   an_state <= LINK_OK;
                end
            LINK_OK:
                begin
                if (abi_match)      an_state <= AN_ENABLE;
                else                an_state <= LINK_OK;
                end
            default:                an_state <= AN_DIS_LINK_OK;
        endcase
    end



always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        page_rx         <= 1'b0;
        an_complete     <= 1'b0;
        tx_cfdata       <= 16'b0;
        xmit            <= XMIT_IDL;
        np_rx           <= 1'b0;
        bp_rx           <= 1'b0;
        toggle_rx       <= 1'b0;
        toggle_tx       <= 1'b0;
        end 
    else
        case (an_state)
            AN_ENABLE:
                begin
                page_rx     <= 1'b0;
                an_complete <= 1'b0;
                if (san_enable)
                    begin
                    tx_cfdata   <= 16'b0;
                    xmit        <= XMIT_CFG;
                    end
                else    xmit    <= XMIT_IDL;
                end
            AN_RESTART:
                begin
                tx_cfdata       <= 16'b0;
                xmit            <= XMIT_CFG;  
                bp_rx           <= 1'b1;
                np_rx           <= 1'b0;
                end
            AN_DIS_LINK_OK:
                begin
                xmit <= XMIT_DAT;
                end
            ABILITY_DET:
                begin
                toggle_tx       <= adv_abi[12];
                tx_cfdata       <= {adv_abi[16],1'b0,adv_abi[14:1]};
                end
            ACK_DET:
                begin
                tx_cfdata[14] <= 1'b1;              
                end
            COMPLETE_ACK:
                begin
                toggle_tx   <= !tx_cfdata[11];
                toggle_rx   <= page_rx? toggle_rx: lrx_cfdata[11];
                np_rx       <= page_rx? np_rx    : lrx_cfdata[15];
                page_rx     <= 1'b1;
                end
            NEXT_PAGE_WAIT:
                begin
                tx_cfdata   <= {np_tx[16],1'b0,np_tx[14:13],toggle_tx,np_tx[11:1]};
                page_rx     <= 1'b0;
                bp_rx       <= 1'b0;
                end
            IDLE_DET:
                begin
                xmit            <= XMIT_IDL;
                end
            LINK_OK:
                begin
                xmit            <= XMIT_DAT;
                an_complete     <= 1'b1;
                end
        endcase
    end
 






wire   np_tx_ind;
assign np_tx_ind =  lpen[7]& upws;

reg    snp_tx_ind;
always @(posedge clk or negedge rst_)
    if(!rst_)
        snp_tx_ind <= 1'b0;
    else
        snp_tx_ind <= np_tx_ind;


wire [15:0] np_tx_dat;
wire [15:0]  snp_tx_dat;
fflopx #(16) plnp_tx_dat (clk, rst_,np_tx_dat,snp_tx_dat);

assign      np_tx[16:1] = snp_tx_dat;

wire [15:0] reg7;

pconfigx #(16,16'b0) mg_reg7
    (
     .clk(clk),
     .rst_(rst_),
     .upen(lpen[7]),
     .upws(upws),
     .updi(updi),
     .out(np_tx_dat),
     .updo(reg7)
     );

assign      pdo7 = lpen[7]? reg7 : 16'b0;

always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)
        begin
        np_loaded   <= 1'b0;
        end
    else if ((an_state == AN_RESTART) | (an_state == NEXT_PAGE_WAIT))
        begin
        np_loaded   <= 1'b0;
        end
    else if(snp_tx_ind)
        begin
        np_loaded   <= 1'b1;
        end
    else if(!txcf_NP)  np_loaded <= np_rx;
    
    end


assign txcf_NP = tx_cfdata[15];




always @(posedge clk or negedge rst_)
    if(!rst_)
        lrx_cfdata <= 16'b0;
    else
        lrx_cfdata <= rx_cfdata;

wire    pre_abi_match;
assign  pre_abi_match = ({rx_cfdata[15],rx_cfdata[13:0]} == {lrx_cfdata[15],lrx_cfdata[13:0]});


reg [3:0] abi_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          abi_cnt <= 4'b0;
    else if ((rudi == RUDI_INVLD) | (rudi == RUDI_I))    abi_cnt <= 4'b0;
    else if (~pre_abi_match)           abi_cnt <= 4'b0;    
    else if (pre_abi_match )           abi_cnt <= abi_match? abi_cnt : abi_cnt + 1'b1;
    end

assign abi_match = (abi_cnt == 4'd11);

reg [15:0] labi_match;

always @(posedge clk or negedge rst_)
    if(!rst_)
        labi_match <= 16'b0;
    else 
        if(abi_match) labi_match <= lrx_cfdata;


wire       pre_ack_match;
assign     pre_ack_match = pre_abi_match & rx_cfdata[14]& lrx_cfdata[14];

reg [3:0]  ack_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          ack_cnt <= 4'b0;
    else if ((rudi == RUDI_INVLD) | (rudi == RUDI_I))   ack_cnt <= 4'b0;
    else if (~pre_ack_match)                            ack_cnt <= 4'b0;    
    else if (pre_ack_match )                            ack_cnt <= ack_match? ack_cnt : ack_cnt + 1'b1;
    end

assign ack_match = (ack_cnt == 4'd11);

assign consist_match = ack_match& (lrx_cfdata == labi_match);
       
reg [2:0] idle_cnt;
always @ (posedge clk or negedge rst_)
    begin
    if (~rst_)          idle_cnt <= 3'b0;
    else 
        begin
        if (rudi != RUDI_I)         idle_cnt <= 2'b0;
        else if (idle_cnt < 3'd5)   idle_cnt <= idle_cnt + 1'b1;
        end
    end

assign     idle_match = (idle_cnt == 3'd5);



assign updo  = pdo0| pdo1| pdo4| pdo5| pdo6| pdo7| pdo8| pdo9;

assign uprdy = (|lpen) & (upws| uprs);

endmodule