data/full_repos/permissive/517427004/CA2 - MIPS Single-Cycle/Verilog/MIPS_TB.v
1: b'%Error: Invalid Option: -\n'
module MIPS_TB ();
    reg clk = 1'b0, rst = 1'b0;

    MIPS mips(clk, rst);

    always #10 clk = ~clk;

    initial begin
        #2 rst = 1'b1;
        #5 rst = 1'b0;
        #3500 $stop;
    end
endmodule
module MIPS_TB ();

    reg clk = 1'b0, rst = 1'b0;

    MIPS mips(clk, rst);

    always #10 clk = ~clk;

    initial begin
        #2 rst = 1'b1;
        #5 rst = 1'b0;
        #3500 $stop;
    end
endmodule