data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:228: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:234: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:242: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:248: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:262: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:268: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:282: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:289: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:295: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:301: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/OFMI_tb.v:306: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OFMI_tb();



parameter IFPATH = "../files/IF/vin/test-vin.txt";
parameter IF_SIZE=192;
parameter W_SIZE=27;
parameter W_COXRW=9;
parameter OF_SIZE=108;
parameter ADDR_OFFSET=0;
parameter MAXIMSIZE=10800;
parameter MAXWSIZE=507;
parameter W_ADDR_WIDTH=9;
parameter IF_ADDR_WIDTH=22;
parameter MEM_ADDR_WIDTH=22;
parameter W_DATA_WIDTH=8;
parameter IF_DATA_WIDTH=9;
parameter MEM_DATA_WIDTH=32;
localparam MAXMEMSIZE=MAXIMSIZE+MAXWSIZE;
parameter CLK_PERIOD=20;
integer i;


reg tb_clk;
reg [IF_ADDR_WIDTH-1:0] tb_if_Size;
reg [IF_ADDR_WIDTH-1:0] tb_of_size;
reg [W_ADDR_WIDTH-1:0] tb_w_size;
reg [W_ADDR_WIDTH-1:0] tb_w_coxrw;
reg tb_loading_weights_already_ok;


reg tb_reset_Ofmi;
reg [MEM_ADDR_WIDTH-1:0] tb_Ofmi_addr_offset;
reg tb_Ofmi_start_loading_weights;
reg tb_Ofmi_start_feeding_datapath;
reg tb_Ofmi_stop_feeding_datapath;
reg tb_Ofmi_feeding_datapath_finished_ok;
reg tb_Ofmi_start_writing_data;
reg tb_Ofmi_writing_data_already_ok;


reg tb_reset_Owmc;
reg tb_Owmc_start_loading_weights;
reg tb_Owmc_start_loading_regs;
reg tb_Owmc_loading_regs_already_ok;



reg [MEM_DATA_WIDTH-1:0] tb_OffchipRam_data_in;



wire tb_Ofmi_loading_weights_already;
wire tb_Ofmi_feeding_datapath_finished;
wire tb_Ofmi_writing_data_already;
wire tb_Ofmi_Offmem_We;
wire tb_Ofmi_Offmem_Re;
wire [MEM_ADDR_WIDTH-1:0]  tb_Ofmi_Offmem_Addr;
wire tb_Ofmi_Mux_Sel;
wire tb_Ofmi_Mux_En;



wire tb_Owmc_loading_weights_already;
wire tb_Owmc_loading_regs_already;
wire [W_DATA_WIDTH-1:0] tb_Owmc_output_data;
wire tb_Owmc_muxes_en;
wire [W_ADDR_WIDTH-1:0] tb_Owmc_muxes_sel;



wire [MEM_DATA_WIDTH-1:0] tb_OffchipRam_Data_Out;


wire [MEM_DATA_WIDTH-1:0] Demux_out0;
wire [MEM_DATA_WIDTH-1:0] Demux_out1;




OFMI #(.W_ADDR_WIDTH(W_ADDR_WIDTH),.IF_BITWIDTH_MAXSIZE(IF_ADDR_WIDTH),.OFFMEN_ADDR_WIDTH(MEM_ADDR_WIDTH)) Ofmi
(


.OFMI_Clk(tb_clk),
.OFMI_Reset(tb_reset_Ofmi),
.OFMI_If_Size(tb_if_Size),
.OFMI_Of_Size(tb_of_size),
.OFMI_W_Size(tb_w_size), 
.OFMI_Addr_Offset(tb_Ofmi_addr_offset),
.OFMI_Mst_Start_Loading_Weights(tb_Ofmi_start_loading_weights),
.OFMI_Mst_Loading_Weights_Already_Ok(tb_loading_weights_already_ok),
.OFMI_Owmc_Loading_Weights_Already(tb_Owmc_loading_weights_already),
.OFMI_Mst_Start_Feeding_Datapath(tb_Ofmi_start_feeding_datapath),
.OFMI_Mst_Stop_Feeding_Datapath(tb_Ofmi_stop_feeding_datapath),
.OFMI_Feeding_Datapath_finished_OK(tb_Ofmi_feeding_datapath_finished_ok),
.OFMI_Mst_Start_Writing_Data(tb_Ofmi_start_writing_data),
.OFMI_Mst_Writing_Data_Already_Ok(tb_Ofmi_writing_data_already_ok),



.OFMI_Mst_Loading_Weights_Already(tb_Ofmi_loading_weights_already),
.OFMI_Mst_Feeding_Datapath_finished(tb_Ofmi_feeding_datapath_finished),
.OFMI_Mst_Writing_Data_Already(tb_Ofmi_writing_data_already),
.OFMI_Offmem_We(tb_Ofmi_Offmem_We),
.OFMI_Offmem_Re(tb_Ofmi_Offmem_Re),
.OFMI_Offmem_Addr(tb_Ofmi_Offmem_Addr),
.OFMI_Mux_Sel(tb_Ofmi_Mux_Sel),
.OFMI_Mux_En(tb_Ofmi_Mux_En)

);

RAM_SIM #(
.DATA_WIDTH(MEM_DATA_WIDTH),
.MEM_SIZE(MAXMEMSIZE),
.ADDR_WIDTH(MEM_ADDR_WIDTH),
.IFPATH(IFPATH)) OffchipRam

(


.RAM_SIM_Clk(tb_clk),
.RAM_SIM_We(tb_Ofmi_Offmem_We),
.RAM_SIM_Oe(tb_Ofmi_Offmem_Re),
.RAM_SIM_Address(tb_Ofmi_Offmem_Addr),
.RAM_SIM_Data_In(tb_OffchipRam_data_in),


.RAM_SIM_Data_Out(tb_OffchipRam_Data_Out)

);


OWMC #(.W_DATA_WIDTH(W_DATA_WIDTH),.W_MEM_SIZE(MAXWSIZE),.W_ADDR_WIDTH(W_ADDR_WIDTH)) Owmc
(


.OWMC_Clk(tb_clk),
.OWMC_Reset(tb_reset_Owmc),
.OWMC_W_Size(tb_w_size),
.OWMC_W_COXRW(tb_w_coxrw),
.OWMC_Input_Data(Demux_out0),
.OWMC_Start_Loading_Weights(tb_Owmc_start_loading_weights),
.OWMC_Start_Loading_Regs(tb_Owmc_start_loading_regs),
.OWMC_Loading_Weights_Already_Ok(tb_loading_weights_already_ok),
.OWMC_Loading_Regs_Already_Ok(tb_Owmc_loading_regs_already_ok),


.OWMC_Loading_Weights_Already(tb_Owmc_loading_weights_already),
.OWMC_Loading_Regs_Already(tb_Owmc_loading_regs_already),
.OWMC_Output_Data(tb_Owmc_output_data),
.OWMC_Muxes_En(tb_Owmc_muxes_en),
.OWMC_Muxes_Sel(tb_Owmc_muxes_sel)

);


DEMUX_1_2 #(.INPUT_DATA_WIDTH(MEM_DATA_WIDTH)) Demux
(


.DEMUX_Data_in(tb_OffchipRam_Data_Out),
.DEMUX_selector(tb_Ofmi_Mux_Sel),
.DEMUX_En(tb_Ofmi_Mux_En),

.DEMUX_out0(Demux_out0),
.DEMUX_out1(Demux_out1)

);


always
begin
		tb_clk=1'b1;
		#(CLK_PERIOD/2);
		tb_clk=1'b0;
		#(CLK_PERIOD/2);
end



initial 
begin
	
	tb_if_Size<=IF_SIZE-1;
	tb_of_size<=OF_SIZE-1;
	tb_w_size<=W_SIZE-1;
	tb_w_coxrw<=W_COXRW-1;
	tb_loading_weights_already_ok<=0;
	tb_reset_Ofmi<=0;
	tb_Ofmi_addr_offset<=ADDR_OFFSET;
	tb_Ofmi_start_loading_weights<=0;
	tb_Ofmi_start_feeding_datapath<=0;
	tb_Ofmi_stop_feeding_datapath<=0;
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	tb_Ofmi_start_writing_data<=0;
	tb_Ofmi_writing_data_already_ok<=0;
	tb_reset_Owmc<=0;
	tb_Owmc_start_loading_weights<=0;
	tb_Owmc_start_loading_regs<=0;
	tb_Owmc_loading_regs_already_ok<=0;
	tb_OffchipRam_data_in<=0;

	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_loading_weights<=1;
	tb_Owmc_start_loading_weights<=0;
	tb_reset_Ofmi<=1;
	tb_reset_Owmc<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_loading_weights<=0;
	tb_Owmc_start_loading_weights<=1;
	
	
	for(i=0;tb_Owmc_loading_weights_already==1'b0;i=i+1)begin
		
		@(negedge tb_clk)
		@(posedge tb_clk);
		tb_Owmc_start_loading_weights<=0;
		
	end
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_loading_weights_already_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_loading_weights_already_ok<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;
	
	for(i=0;tb_Ofmi_feeding_datapath_finished==1'b0;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
		
	end
	
	tb_Ofmi_feeding_datapath_finished_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	
	

	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;
	
	for(i=0;i<20;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
		
	end
	tb_Ofmi_stop_feeding_datapath<=1;
	
	for(i=0;i<3;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk)
		tb_Ofmi_stop_feeding_datapath<=0;
	end
	
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;

	
	for(i=0;tb_Ofmi_feeding_datapath_finished==1'b0;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
	end
	
	tb_Ofmi_feeding_datapath_finished_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk);
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	
	$stop;
	
end
	
	
endmodule
module OFMI_tb();




parameter IFPATH = "../files/IF/vin/test-vin.txt";
parameter IF_SIZE=192;
parameter W_SIZE=27;
parameter W_COXRW=9;
parameter OF_SIZE=108;
parameter ADDR_OFFSET=0;
parameter MAXIMSIZE=10800;
parameter MAXWSIZE=507;
parameter W_ADDR_WIDTH=9;
parameter IF_ADDR_WIDTH=22;
parameter MEM_ADDR_WIDTH=22;
parameter W_DATA_WIDTH=8;
parameter IF_DATA_WIDTH=9;
parameter MEM_DATA_WIDTH=32;
localparam MAXMEMSIZE=MAXIMSIZE+MAXWSIZE;
parameter CLK_PERIOD=20;
integer i;


reg tb_clk;
reg [IF_ADDR_WIDTH-1:0] tb_if_Size;
reg [IF_ADDR_WIDTH-1:0] tb_of_size;
reg [W_ADDR_WIDTH-1:0] tb_w_size;
reg [W_ADDR_WIDTH-1:0] tb_w_coxrw;
reg tb_loading_weights_already_ok;


reg tb_reset_Ofmi;
reg [MEM_ADDR_WIDTH-1:0] tb_Ofmi_addr_offset;
reg tb_Ofmi_start_loading_weights;
reg tb_Ofmi_start_feeding_datapath;
reg tb_Ofmi_stop_feeding_datapath;
reg tb_Ofmi_feeding_datapath_finished_ok;
reg tb_Ofmi_start_writing_data;
reg tb_Ofmi_writing_data_already_ok;


reg tb_reset_Owmc;
reg tb_Owmc_start_loading_weights;
reg tb_Owmc_start_loading_regs;
reg tb_Owmc_loading_regs_already_ok;



reg [MEM_DATA_WIDTH-1:0] tb_OffchipRam_data_in;



wire tb_Ofmi_loading_weights_already;
wire tb_Ofmi_feeding_datapath_finished;
wire tb_Ofmi_writing_data_already;
wire tb_Ofmi_Offmem_We;
wire tb_Ofmi_Offmem_Re;
wire [MEM_ADDR_WIDTH-1:0]  tb_Ofmi_Offmem_Addr;
wire tb_Ofmi_Mux_Sel;
wire tb_Ofmi_Mux_En;



wire tb_Owmc_loading_weights_already;
wire tb_Owmc_loading_regs_already;
wire [W_DATA_WIDTH-1:0] tb_Owmc_output_data;
wire tb_Owmc_muxes_en;
wire [W_ADDR_WIDTH-1:0] tb_Owmc_muxes_sel;



wire [MEM_DATA_WIDTH-1:0] tb_OffchipRam_Data_Out;


wire [MEM_DATA_WIDTH-1:0] Demux_out0;
wire [MEM_DATA_WIDTH-1:0] Demux_out1;




OFMI #(.W_ADDR_WIDTH(W_ADDR_WIDTH),.IF_BITWIDTH_MAXSIZE(IF_ADDR_WIDTH),.OFFMEN_ADDR_WIDTH(MEM_ADDR_WIDTH)) Ofmi
(


.OFMI_Clk(tb_clk),
.OFMI_Reset(tb_reset_Ofmi),
.OFMI_If_Size(tb_if_Size),
.OFMI_Of_Size(tb_of_size),
.OFMI_W_Size(tb_w_size), 
.OFMI_Addr_Offset(tb_Ofmi_addr_offset),
.OFMI_Mst_Start_Loading_Weights(tb_Ofmi_start_loading_weights),
.OFMI_Mst_Loading_Weights_Already_Ok(tb_loading_weights_already_ok),
.OFMI_Owmc_Loading_Weights_Already(tb_Owmc_loading_weights_already),
.OFMI_Mst_Start_Feeding_Datapath(tb_Ofmi_start_feeding_datapath),
.OFMI_Mst_Stop_Feeding_Datapath(tb_Ofmi_stop_feeding_datapath),
.OFMI_Feeding_Datapath_finished_OK(tb_Ofmi_feeding_datapath_finished_ok),
.OFMI_Mst_Start_Writing_Data(tb_Ofmi_start_writing_data),
.OFMI_Mst_Writing_Data_Already_Ok(tb_Ofmi_writing_data_already_ok),



.OFMI_Mst_Loading_Weights_Already(tb_Ofmi_loading_weights_already),
.OFMI_Mst_Feeding_Datapath_finished(tb_Ofmi_feeding_datapath_finished),
.OFMI_Mst_Writing_Data_Already(tb_Ofmi_writing_data_already),
.OFMI_Offmem_We(tb_Ofmi_Offmem_We),
.OFMI_Offmem_Re(tb_Ofmi_Offmem_Re),
.OFMI_Offmem_Addr(tb_Ofmi_Offmem_Addr),
.OFMI_Mux_Sel(tb_Ofmi_Mux_Sel),
.OFMI_Mux_En(tb_Ofmi_Mux_En)

);

RAM_SIM #(
.DATA_WIDTH(MEM_DATA_WIDTH),
.MEM_SIZE(MAXMEMSIZE),
.ADDR_WIDTH(MEM_ADDR_WIDTH),
.IFPATH(IFPATH)) OffchipRam

(


.RAM_SIM_Clk(tb_clk),
.RAM_SIM_We(tb_Ofmi_Offmem_We),
.RAM_SIM_Oe(tb_Ofmi_Offmem_Re),
.RAM_SIM_Address(tb_Ofmi_Offmem_Addr),
.RAM_SIM_Data_In(tb_OffchipRam_data_in),


.RAM_SIM_Data_Out(tb_OffchipRam_Data_Out)

);


OWMC #(.W_DATA_WIDTH(W_DATA_WIDTH),.W_MEM_SIZE(MAXWSIZE),.W_ADDR_WIDTH(W_ADDR_WIDTH)) Owmc
(


.OWMC_Clk(tb_clk),
.OWMC_Reset(tb_reset_Owmc),
.OWMC_W_Size(tb_w_size),
.OWMC_W_COXRW(tb_w_coxrw),
.OWMC_Input_Data(Demux_out0),
.OWMC_Start_Loading_Weights(tb_Owmc_start_loading_weights),
.OWMC_Start_Loading_Regs(tb_Owmc_start_loading_regs),
.OWMC_Loading_Weights_Already_Ok(tb_loading_weights_already_ok),
.OWMC_Loading_Regs_Already_Ok(tb_Owmc_loading_regs_already_ok),


.OWMC_Loading_Weights_Already(tb_Owmc_loading_weights_already),
.OWMC_Loading_Regs_Already(tb_Owmc_loading_regs_already),
.OWMC_Output_Data(tb_Owmc_output_data),
.OWMC_Muxes_En(tb_Owmc_muxes_en),
.OWMC_Muxes_Sel(tb_Owmc_muxes_sel)

);


DEMUX_1_2 #(.INPUT_DATA_WIDTH(MEM_DATA_WIDTH)) Demux
(


.DEMUX_Data_in(tb_OffchipRam_Data_Out),
.DEMUX_selector(tb_Ofmi_Mux_Sel),
.DEMUX_En(tb_Ofmi_Mux_En),

.DEMUX_out0(Demux_out0),
.DEMUX_out1(Demux_out1)

);


always
begin
		tb_clk=1'b1;
		#(CLK_PERIOD/2);
		tb_clk=1'b0;
		#(CLK_PERIOD/2);
end



initial 
begin
	
	tb_if_Size<=IF_SIZE-1;
	tb_of_size<=OF_SIZE-1;
	tb_w_size<=W_SIZE-1;
	tb_w_coxrw<=W_COXRW-1;
	tb_loading_weights_already_ok<=0;
	tb_reset_Ofmi<=0;
	tb_Ofmi_addr_offset<=ADDR_OFFSET;
	tb_Ofmi_start_loading_weights<=0;
	tb_Ofmi_start_feeding_datapath<=0;
	tb_Ofmi_stop_feeding_datapath<=0;
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	tb_Ofmi_start_writing_data<=0;
	tb_Ofmi_writing_data_already_ok<=0;
	tb_reset_Owmc<=0;
	tb_Owmc_start_loading_weights<=0;
	tb_Owmc_start_loading_regs<=0;
	tb_Owmc_loading_regs_already_ok<=0;
	tb_OffchipRam_data_in<=0;

	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_loading_weights<=1;
	tb_Owmc_start_loading_weights<=0;
	tb_reset_Ofmi<=1;
	tb_reset_Owmc<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_loading_weights<=0;
	tb_Owmc_start_loading_weights<=1;
	
	
	for(i=0;tb_Owmc_loading_weights_already==1'b0;i=i+1)begin
		
		@(negedge tb_clk)
		@(posedge tb_clk);
		tb_Owmc_start_loading_weights<=0;
		
	end
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_loading_weights_already_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_loading_weights_already_ok<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;
	
	for(i=0;tb_Ofmi_feeding_datapath_finished==1'b0;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
		
	end
	
	tb_Ofmi_feeding_datapath_finished_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	
	

	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;
	
	for(i=0;i<20;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
		
	end
	tb_Ofmi_stop_feeding_datapath<=1;
	
	for(i=0;i<3;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk)
		tb_Ofmi_stop_feeding_datapath<=0;
	end
	
	tb_Ofmi_start_feeding_datapath<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_Ofmi_start_feeding_datapath<=0;

	
	for(i=0;tb_Ofmi_feeding_datapath_finished==1'b0;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
	end
	
	tb_Ofmi_feeding_datapath_finished_ok<=1;
	@(negedge tb_clk)
	@(posedge tb_clk);
	tb_Ofmi_feeding_datapath_finished_ok<=0;
	
	$stop;
	
end
	
	
endmodule