data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #3000   $stop;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #10 aa <= aa+1;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:34: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("comp_conv_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:35: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comp_conv(
            a,
            a_comp
);
input[7:0]  a;
output[7:0] a_comp;

wire[6:0]   tmp;
wire[7:0]   y;

assign      tmp = ~a[6:0];
assign      y[6:0] = tmp+1;
assign      y[7] = a[7];

assign      a_comp = a[7]?y:a;
endmodule
module comp_conv(
            a,
            a_comp
);

input[7:0]  a;
output[7:0] a_comp;

wire[6:0]   tmp;
wire[7:0]   y;

assign      tmp = ~a[6:0];
assign      y[6:0] = tmp+1;
assign      y[7] = a[7];

assign      a_comp = a[7]?y:a;
endmodule