data/full_repos/permissive/411457613/Pyverilog/verilogcode/instance_array.v
data/verilator_xmls/8c937d3f-0ad5-4f56-9187-47490be25353.xml
module SUB #
  (
   parameter MODE = 0
   )
  (
   input VAL,
   output LED
   );
  assign LED = ~VAL & MODE;
endmodule
module SUB #
  (
   parameter MODE = 0
   )
  (
   input VAL,
   output LED
   );

  assign LED = ~VAL & MODE;
endmodule