data/full_repos/permissive/428601773/tb/tb_core.v
1: b'%Error: data/full_repos/permissive/428601773/tb/tb_core.v:2: Cannot find include file: CoreRiscV.v\n`include "CoreRiscV.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/CoreRiscV.v\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/CoreRiscV.v.v\n             data/full_repos/permissive/428601773/tb,data/full_repos/permissive/428601773/CoreRiscV.v.sv\n             CoreRiscV.v\n             CoreRiscV.v.v\n             CoreRiscV.v.sv\n             obj_dir/CoreRiscV.v\n             obj_dir/CoreRiscV.v.v\n             obj_dir/CoreRiscV.v.sv\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, tb_core);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_core.v:23: Unsupported: Ignoring delay on this delayed statement.\n    # RST_WAIT;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/428601773/tb/tb_core.v:27: Unsupported: Ignoring delay on this delayed statement.\n      # HF_CYCLE;\n      ^\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:30: Define or directive not defined: \'`OPCODE_SYSTEM\'\n      if (tb_core.core.opcode == `OPCODE_SYSTEM) begin\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:30: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (tb_core.core.opcode == `OPCODE_SYSTEM) begin\n                                               ^\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:38: Define or directive not defined: \'`OPCODE_OPERATION_REG\'\n          `OPCODE_OPERATION_REG : $display("\\t OPERATION_REG");\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:38: syntax error, unexpected \':\', expecting endcase\n          `OPCODE_OPERATION_REG : $display("\\t OPERATION_REG");\n                                ^\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:39: Define or directive not defined: \'`OPCODE_OPERATION_IMM\'\n          `OPCODE_OPERATION_IMM : $display("\\t OPERATION_IMM");\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:40: Define or directive not defined: \'`OPCODE_IMM_U_LOAD\'\n          `OPCODE_IMM_U_LOAD : $display("\\t IMM_U_LOAD");\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:41: Define or directive not defined: \'`OPCODE_IMM_U_PC\'\n          `OPCODE_IMM_U_PC  : $display("\\t IMM_U_PC ");\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:42: Define or directive not defined: \'`OPCODE_STORE\'\n          `OPCODE_STORE   : $display("\\t STORE");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:43: Define or directive not defined: \'`OPCODE_LOAD\'\n          `OPCODE_LOAD    : $display("\\t LOAD");\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:44: Define or directive not defined: \'`OPCODE_BRANCH\'\n          `OPCODE_BRANCH  : $display("\\t BRANCH");\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:45: Define or directive not defined: \'`OPCODE_JUMP_LINK_REG\'\n          `OPCODE_JUMP_LINK_REG : $display("\\t JUMP_LINK_REG");\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:46: Define or directive not defined: \'`OPCODE_JUMP_LINK_IMM\'\n          `OPCODE_JUMP_LINK_IMM : $display("\\t JUMP_LINK_IMM");\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:47: Define or directive not defined: \'`OPCODE_MISC_MEM\'\n          `OPCODE_MISC_MEM  : $display("\\t MISC_MEM");\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:48: Define or directive not defined: \'`OPCODE_SYSTEM\'\n          `OPCODE_SYSTEM  : $display("\\t SYSTEM");\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/tb/tb_core.v:54: syntax error, unexpected endcase\n        endcase\n        ^~~~~~~\n%Error: Cannot continue\n'
module tb_core();

  parameter     HF_CYCLE = 2.5;
  parameter     RST_WAIT = 10;
  parameter     RAM_SIZE = 512;


  reg clk;
  reg rst_n;

  CoreRiscV core(clk);
  
  integer i = 0;
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, tb_core);
    
    clk   = 1'b0;
    rst_n = 1'b0;
    # RST_WAIT;
    rst_n = 1'b1;
    
    while (1) begin
      # HF_CYCLE;
      clk = ~clk;
      i = i + 1;
      if (tb_core.core.opcode == `OPCODE_SYSTEM) begin
        $display("RESULT FOUNDED:%10d", tb_core.core.RF_connection.RAM[10]);
        break;
      end
      
      if (clk == 1'b1) begin
        $display("Takt=%3d :: PC=%2d :: Instr=%8h", i / 2 + 1, tb_core.core.pc , tb_core.core.instr);
        case(tb_core.core.opcode)
          `OPCODE_OPERATION_REG : $display("\t OPERATION_REG");
          `OPCODE_OPERATION_IMM : $display("\t OPERATION_IMM");
          `OPCODE_IMM_U_LOAD	: $display("\t IMM_U_LOAD");
          `OPCODE_IMM_U_PC		: $display("\t IMM_U_PC	");
          `OPCODE_STORE			: $display("\t STORE");
          `OPCODE_LOAD 			: $display("\t LOAD");
          `OPCODE_BRANCH		: $display("\t BRANCH");
          `OPCODE_JUMP_LINK_REG : $display("\t JUMP_LINK_REG");
          `OPCODE_JUMP_LINK_IMM : $display("\t JUMP_LINK_IMM");
          `OPCODE_MISC_MEM		: $display("\t MISC_MEM");
          `OPCODE_SYSTEM		: $display("\t SYSTEM");
          default: begin
            $display("\n!!!OPCODE: UNKNOWN!!!");
            break;
          end

        endcase
        if (tb_core.core.jal_signal)
          $display("\tJUMP TO %10d", tb_core.core.pc + tb_core.core.imm_J);
        else if (tb_core.core.jalr_signal)
          $display("\tJUMP TO %10d", tb_core.core.rd1 + tb_core.core.imm_I);
        else if (tb_core.core.branch_signal)
          $display("\tTRY JUMP TO %10d", tb_core.core.pc + tb_core.core.imm_B);
        else if (tb_core.core.memory_write_enable_signal)
          $display("\tMem[%10d] = %10d", tb_core.core.alu_result, tb_core.core.imm_S);
        else if (tb_core.core.memory_require_signal)
          $display("\tx%2d = Mem[%10d] = %10d", tb_core.core.rd3, tb_core.core.alu_result, tb_core.core.readed_data);
        else
          $display("\t%5b(%10d, %10d) = %10d", tb_core.core.alu_operation_signal,  tb_core.core.rd1, tb_core.core.rd2, tb_core.core.wd3);
      end
    end
    $finish;
  end

endmodule
module tb_core();


  parameter     HF_CYCLE = 2.5;
  parameter     RST_WAIT = 10;
  parameter     RAM_SIZE = 512;


  reg clk;
  reg rst_n;

  CoreRiscV core(clk);
  
  integer i = 0;
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, tb_core);
    
    clk   = 1'b0;
    rst_n = 1'b0;
    # RST_WAIT;
    rst_n = 1'b1;
    
    while (1) begin
      # HF_CYCLE;
      clk = ~clk;
      i = i + 1;
      if (tb_core.core.opcode == `OPCODE_SYSTEM) begin
        $display("RESULT FOUNDED:%10d", tb_core.core.RF_connection.RAM[10]);
        break;
      end
      
      if (clk == 1'b1) begin
        $display("Takt=%3d :: PC=%2d :: Instr=%8h", i / 2 + 1, tb_core.core.pc , tb_core.core.instr);
        case(tb_core.core.opcode)
          `OPCODE_OPERATION_REG : $display("\t OPERATION_REG");
          `OPCODE_OPERATION_IMM : $display("\t OPERATION_IMM");
          `OPCODE_IMM_U_LOAD	: $display("\t IMM_U_LOAD");
          `OPCODE_IMM_U_PC		: $display("\t IMM_U_PC	");
          `OPCODE_STORE			: $display("\t STORE");
          `OPCODE_LOAD 			: $display("\t LOAD");
          `OPCODE_BRANCH		: $display("\t BRANCH");
          `OPCODE_JUMP_LINK_REG : $display("\t JUMP_LINK_REG");
          `OPCODE_JUMP_LINK_IMM : $display("\t JUMP_LINK_IMM");
          `OPCODE_MISC_MEM		: $display("\t MISC_MEM");
          `OPCODE_SYSTEM		: $display("\t SYSTEM");
          default: begin
            $display("\n!!!OPCODE: UNKNOWN!!!");
            break;
          end

        endcase
        if (tb_core.core.jal_signal)
          $display("\tJUMP TO %10d", tb_core.core.pc + tb_core.core.imm_J);
        else if (tb_core.core.jalr_signal)
          $display("\tJUMP TO %10d", tb_core.core.rd1 + tb_core.core.imm_I);
        else if (tb_core.core.branch_signal)
          $display("\tTRY JUMP TO %10d", tb_core.core.pc + tb_core.core.imm_B);
        else if (tb_core.core.memory_write_enable_signal)
          $display("\tMem[%10d] = %10d", tb_core.core.alu_result, tb_core.core.imm_S);
        else if (tb_core.core.memory_require_signal)
          $display("\tx%2d = Mem[%10d] = %10d", tb_core.core.rd3, tb_core.core.alu_result, tb_core.core.readed_data);
        else
          $display("\t%5b(%10d, %10d) = %10d", tb_core.core.alu_operation_signal,  tb_core.core.rd1, tb_core.core.rd2, tb_core.core.wd3);
      end
    end
    $finish;
  end

endmodule