data/full_repos/permissive/493019833/test/testcase/firrtl/SIntTester/reference/SIntTester.v
data/verilator_xmls/fe853b3f-e54d-42a9-8b44-b0145c8ba08f.xml
module BITS(y, in);
    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule
module BITS(y, in);

    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule