data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_speedctrl.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_speedctrl.v:91: Cannot find file containing module: 'fflopxe'\nfflopxe #(8)    ffrcvcap (rxclk, rxrst_, iifovld, iifodat, rcvdat);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_speedctrl.v:131: Cannot find file containing module: 'fflopx'\nfflopx #(1) ffostable (txclk, txrst_, pstable, ostable);\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ipsmacge_speedctrl
    (

     rxrst_,
     rxclk,
     iifovld,
     iifodat,

     txclk,
     txrst_,
     oselclk,

     ostable,
     omodspd,

     stacapdat,
     stamodspd,
     staselclk,

     pautodis,
     pmodspd,
     pstable,
     pmodgmii
     );





















input           rxrst_;
input           rxclk;

input           iifovld;
input [7:0]     iifodat;

input           txclk;
input           txrst_;
output [1:0]    oselclk;

output          ostable;
output [1:0]    omodspd;

output [7:0]    stacapdat;
output [1:0]    stamodspd;
output [1:0]	staselclk;

input           pstable;
input           pautodis;
input [1:0]     pmodspd;
input           pmodgmii;







reg [1:0]       omodspd;
assign          stamodspd = omodspd;

wire [7:0]      rcvdat;
fflopxe #(8)    ffrcvcap (rxclk, rxrst_, iifovld, iifodat, rcvdat);

assign          stacapdat = rcvdat;

wire [1:0]      rcvspeed;
assign          rcvspeed = rcvdat [2:1];

always @(pautodis or pmodspd or rcvspeed)
    begin
    case (pautodis)
        1'b1:   omodspd <= pmodspd;
        1'b0:   omodspd <= rcvspeed;
    endcase
    end

reg [1:0]       oselclk;
assign 			staselclk = oselclk;

always @(pmodgmii or pautodis or rcvspeed or pmodspd)
    begin
    case (pautodis)
        1'b1:   
            begin
            case (pmodspd)
                2'b00:  oselclk <= pmodgmii ? 2'b00 : 2'b01;
                2'b01:  oselclk <= pmodgmii ? 2'b00 : 2'b11;
                default:oselclk <= pmodgmii ? 2'b10 : 2'b10;
            endcase
            end
        1'b0:
            begin
            case (rcvspeed)
                2'b00:  oselclk <= pmodgmii ? 2'b00 : 2'b01;
                2'b01:  oselclk <= pmodgmii ? 2'b00 : 2'b11;
                default:oselclk <= pmodgmii ? 2'b10 : 2'b10;
            endcase
            end
    endcase
    end

fflopx #(1) ffostable (txclk, txrst_, pstable, ostable);

endmodule
module ipsmacge_speedctrl
    (

     rxrst_,
     rxclk,
     iifovld,
     iifodat,

     txclk,
     txrst_,
     oselclk,

     ostable,
     omodspd,

     stacapdat,
     stamodspd,
     staselclk,

     pautodis,
     pmodspd,
     pstable,
     pmodgmii
     );






















input           rxrst_;
input           rxclk;

input           iifovld;
input [7:0]     iifodat;

input           txclk;
input           txrst_;
output [1:0]    oselclk;

output          ostable;
output [1:0]    omodspd;

output [7:0]    stacapdat;
output [1:0]    stamodspd;
output [1:0]	staselclk;

input           pstable;
input           pautodis;
input [1:0]     pmodspd;
input           pmodgmii;







reg [1:0]       omodspd;
assign          stamodspd = omodspd;

wire [7:0]      rcvdat;
fflopxe #(8)    ffrcvcap (rxclk, rxrst_, iifovld, iifodat, rcvdat);

assign          stacapdat = rcvdat;

wire [1:0]      rcvspeed;
assign          rcvspeed = rcvdat [2:1];

always @(pautodis or pmodspd or rcvspeed)
    begin
    case (pautodis)
        1'b1:   omodspd <= pmodspd;
        1'b0:   omodspd <= rcvspeed;
    endcase
    end

reg [1:0]       oselclk;
assign 			staselclk = oselclk;

always @(pmodgmii or pautodis or rcvspeed or pmodspd)
    begin
    case (pautodis)
        1'b1:   
            begin
            case (pmodspd)
                2'b00:  oselclk <= pmodgmii ? 2'b00 : 2'b01;
                2'b01:  oselclk <= pmodgmii ? 2'b00 : 2'b11;
                default:oselclk <= pmodgmii ? 2'b10 : 2'b10;
            endcase
            end
        1'b0:
            begin
            case (rcvspeed)
                2'b00:  oselclk <= pmodgmii ? 2'b00 : 2'b01;
                2'b01:  oselclk <= pmodgmii ? 2'b00 : 2'b11;
                default:oselclk <= pmodgmii ? 2'b10 : 2'b10;
            endcase
            end
    endcase
    end

fflopx #(1) ffostable (txclk, txrst_, pstable, ostable);

endmodule