data/full_repos/permissive/529706848/verilog/tb_decoder_3to8.v
1: b'%Error: data/full_repos/permissive/529706848/verilog/tb_decoder_3to8.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_decoder_3to8.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_decoder_3to8.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_decoder_3to8.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_decoder_3to8();

reg [2:0] in;
wire [7:0] out;

decoder_3to8_PROJECT_ID decoder(
    .in(in),
    .out(out)
);

integer i;
initial begin
    $dumpvars;
    #10;
    for (i = 0; i < 8; i = i + 1) begin
        in = i;
        #10;
        $display("in 0b%b -> out 0b%b", in, out);
        #10;
    end
end

endmodule
module tb_decoder_3to8();


reg [2:0] in;
wire [7:0] out;

decoder_3to8_PROJECT_ID decoder(
    .in(in),
    .out(out)
);

integer i;
initial begin
    $dumpvars;
    #10;
    for (i = 0; i < 8; i = i + 1) begin
        in = i;
        #10;
        $display("in 0b%b -> out 0b%b", in, out);
        #10;
    end
end

endmodule