data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_decoder.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: breadboard),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: breadboard)/seg_decoder.v\n%Error: Exiting due to 9 error(s)\n'
module seg_decoder(
    input [3:0] count_in,
    output [6:0] decode_out
    );
    
    reg [6:0] decoder = 7'b000_0000;
    
    always @(*) begin
        case(count_in)
            4'b0000 : decoder = 7'b111_1110;
            4'b0001 : decoder = 7'b001_1000;
            4'b0010 : decoder = 7'b110_1101;
            4'b0011 : decoder = 7'b011_1101;
            4'b0100 : decoder = 7'b001_1011;
            4'b0101 : decoder = 7'b011_0111;
            4'b0110 : decoder = 7'b111_0111;
            4'b0111 : decoder = 7'b001_1100;
            4'b1000 : decoder = 7'b111_1111;
            4'b1001 : decoder = 7'b001_1111;
            default : decoder = 7'b111_1001;
        endcase
    end
    
    assign decode_out = decoder;
    
endmodule
module seg_decoder(
    input [3:0] count_in,
    output [6:0] decode_out
    );

    
    reg [6:0] decoder = 7'b000_0000;
    
    always @(*) begin
        case(count_in)
            4'b0000 : decoder = 7'b111_1110;
            4'b0001 : decoder = 7'b001_1000;
            4'b0010 : decoder = 7'b110_1101;
            4'b0011 : decoder = 7'b011_1101;
            4'b0100 : decoder = 7'b001_1011;
            4'b0101 : decoder = 7'b011_0111;
            4'b0110 : decoder = 7'b111_0111;
            4'b0111 : decoder = 7'b001_1100;
            4'b1000 : decoder = 7'b111_1111;
            4'b1001 : decoder = 7'b001_1111;
            default : decoder = 7'b111_1001;
        endcase
    end
    
    assign decode_out = decoder;
    
endmodule