data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v
1: b'%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:23: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/uart,data/full_repos/permissive/482719158/uprj_netlists.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/uart,data/full_repos/permissive/482719158/uprj_netlists.v.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/uart,data/full_repos/permissive/482719158/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:24: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:25: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n always #(1000000000/baud_rate/10) clk <= (clk === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= (clock === 1\'b0);\n        ^\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:132: syntax error, unexpected \'@\'\n  repeat (1500000) @(posedge clock);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:163: Unsupported: wait statements\n  wait(checkbits == 16\'h0ffe)\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/uart/uart_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #8680\n  ^\n%Error: Exiting due to 5 error(s), 16 warning(s)\n'
module uart_tb;
	reg clock;
	reg RSTB;
	reg microwatt_reset;
	reg power1, power2;
	reg power3, power4;
	reg uart_rx;

	wire gpio;
	wire [37:0] mprj_io;
	wire [15:0] checkbits;
	wire user_flash_csb;
	wire user_flash_clk;
	inout user_flash_io0;
	inout user_flash_io1;
	wire uart_tx;

	assign mprj_io[7] = microwatt_reset;

	assign mprj_io[35] = 1'b1;

	assign user_flash_csb = mprj_io[8];
	assign user_flash_clk = mprj_io[9];
	assign user_flash_io0 = mprj_io[10];
	assign mprj_io[11] = user_flash_io1;

	assign checkbits = mprj_io[31:16];

	assign uart_tx = mprj_io[6];
	assign mprj_io[5] = uart_rx;

	assign mprj_io[3] = 1'b1;


	always #5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin



		$display("Microwatt UART rx -> tx test");

		repeat (1500000) @(posedge clock);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		microwatt_reset <= 1'b1;
		#1000;
		microwatt_reset <= 1'b0;


	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	initial begin
		uart_rx <= 1'b1;

		wait(checkbits == 16'h0ffe)
		$display("Microwatt alive!");


		$display("Writing 7 to Microwatt uart");
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b0;
		#8680
		$display("Done. Waiting for Microwatt to send 7 back");
		uart_rx <= 1'b1;
	end

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("microwatt.hex")
	) spiflash_microwatt (
		.csb(user_flash_csb),
		.clk(user_flash_clk),
		.io0(user_flash_io0),
		.io1(user_flash_io1)
	);

	tbuart_expect_seven #(
		.baud_rate(115200)
	) tbuart (
		.ser_rx(uart_tx)
	);

endmodule
module uart_tb;

	reg clock;
	reg RSTB;
	reg microwatt_reset;
	reg power1, power2;
	reg power3, power4;
	reg uart_rx;

	wire gpio;
	wire [37:0] mprj_io;
	wire [15:0] checkbits;
	wire user_flash_csb;
	wire user_flash_clk;
	inout user_flash_io0;
	inout user_flash_io1;
	wire uart_tx;

	assign mprj_io[7] = microwatt_reset;

	assign mprj_io[35] = 1'b1;

	assign user_flash_csb = mprj_io[8];
	assign user_flash_clk = mprj_io[9];
	assign user_flash_io0 = mprj_io[10];
	assign mprj_io[11] = user_flash_io1;

	assign checkbits = mprj_io[31:16];

	assign uart_tx = mprj_io[6];
	assign mprj_io[5] = uart_rx;

	assign mprj_io[3] = 1'b1;


	always #5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin



		$display("Microwatt UART rx -> tx test");

		repeat (1500000) @(posedge clock);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		microwatt_reset <= 1'b1;
		#1000;
		microwatt_reset <= 1'b0;


	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	initial begin
		uart_rx <= 1'b1;

		wait(checkbits == 16'h0ffe)
		$display("Microwatt alive!");


		$display("Writing 7 to Microwatt uart");
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b1;
		#8680
		uart_rx <= 1'b0;
		#8680
		uart_rx <= 1'b0;
		#8680
		$display("Done. Waiting for Microwatt to send 7 back");
		uart_rx <= 1'b1;
	end

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("microwatt.hex")
	) spiflash_microwatt (
		.csb(user_flash_csb),
		.clk(user_flash_clk),
		.io0(user_flash_io0),
		.io1(user_flash_io1)
	);

	tbuart_expect_seven #(
		.baud_rate(115200)
	) tbuart (
		.ser_rx(uart_tx)
	);

endmodule