data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKBUF.v
data/verilator_xmls/ba5d7734-2434-4e02-a519-0686e180d50d.xml
module ATCKBUF
    (
     A,
     Y
     );
input A;
output Y;
reg    Y;
always @(A)
    begin

    Y = A;
    end
endmodule
module ATCKBUF
    (
     A,
     Y
     );

input A;
output Y;
reg    Y;
always @(A)
    begin

    Y = A;
    end
endmodule