data/full_repos/permissive/505514178/source_code/ALU_cntrl.v
data/verilator_xmls/371feecc-89ff-42b0-a0c5-33f3e534f209.xml
module ALU_cntrl(
	input [1:0] ALUop,
	input [2:0] func3,
	input func7,
	input opbit,
	output reg [3:0] control
    );



always @(*)
begin
case(ALUop)
2'b00:
begin
control = 4'b0010;
end
2'b01:
begin
control = 4'b1111;
end
2'b10:
begin
case(func3)
3'b000:
begin
if(func7==1 && opbit==1)
control = 4'b0011;
else
control = 4'b0010;
end
3'b001:
control = 4'b0100;
3'b010:
control = 4'b1000;
3'b011:
control = 4'b1001;
3'b100:
control = 4'b0111;
3'b101:
begin
if(func7==0)
control = 4'b0101;
else
control = 4'b0110;
end
3'b110:
control = 4'b0001;
3'b111:
control = 4'b0000;
endcase
end
2'b11:
control = 4'b0010;
endcase
end

endmodule
module ALU_cntrl(
	input [1:0] ALUop,
	input [2:0] func3,
	input func7,
	input opbit,
	output reg [3:0] control
    );




always @(*)
begin
case(ALUop)
2'b00:
begin
control = 4'b0010;
end
2'b01:
begin
control = 4'b1111;
end
2'b10:
begin
case(func3)
3'b000:
begin
if(func7==1 && opbit==1)
control = 4'b0011;
else
control = 4'b0010;
end
3'b001:
control = 4'b0100;
3'b010:
control = 4'b1000;
3'b011:
control = 4'b1001;
3'b100:
control = 4'b0111;
3'b101:
begin
if(func7==0)
control = 4'b0101;
else
control = 4'b0110;
end
3'b110:
control = 4'b0001;
3'b111:
control = 4'b0000;
endcase
end
2'b11:
control = 4'b0010;
endcase
end

endmodule