data/full_repos/permissive/426072575/labs/lab15_Mole state machine sequence detector/codes/xiaodou.v
1: b'%Error: Cannot find file containing module: state\n        ... Looked in:\n             data/full_repos/permissive/426072575/labs/lab15_Mole/state\n             data/full_repos/permissive/426072575/labs/lab15_Mole/state.v\n             data/full_repos/permissive/426072575/labs/lab15_Mole/state.sv\n             state\n             state.v\n             state.sv\n             obj_dir/state\n             obj_dir/state.v\n             obj_dir/state.sv\n%Error: Cannot find file containing module: machine\n%Error: Cannot find file containing module: sequence\n%Error: Cannot find file containing module: detector/codes,data/full_repos/permissive/426072575\n%Error: Cannot find file containing module: data/full_repos/permissive/426072575/labs/lab15_Mole\n%Error: Cannot find file containing module: detector/codes/xiaodou.v\n%Error: Exiting due to 6 error(s)\n'
module xiaodou(
    input clk,
    input reset,
    input load_in,
    input clock_in,
    output load_out,
    output clock_out
    );
    reg key_rrr,key_rr,key_r;
    reg load_rrr,load_rr,load_r;
    always @(posedge clk or negedge reset)
       if(!reset) 
          begin
             key_rrr <=0;
             key_rr <=0;
             key_r <=0;
             load_rrr <=0;
             load_rr <=0;
             load_r <=0;
          end
        else
          begin
              key_rrr <= key_rr;
              key_rr <= key_r;
              key_r <= clock_in;
              load_rrr <= load_rr;
              load_rr <= load_r;
              load_r <= load_in;
          end 
    assign clock_out = key_rrr & key_rr & key_r;
    assign load_out = load_rrr & load_rr & load_r;
endmodule
module xiaodou(
    input clk,
    input reset,
    input load_in,
    input clock_in,
    output load_out,
    output clock_out
    );

    reg key_rrr,key_rr,key_r;
    reg load_rrr,load_rr,load_r;
    always @(posedge clk or negedge reset)
       if(!reset) 
          begin
             key_rrr <=0;
             key_rr <=0;
             key_r <=0;
             load_rrr <=0;
             load_rr <=0;
             load_r <=0;
          end
        else
          begin
              key_rrr <= key_rr;
              key_rr <= key_r;
              key_r <= clock_in;
              load_rrr <= load_rr;
              load_rr <= load_r;
              load_r <= load_in;
          end 
    assign clock_out = key_rrr & key_rr & key_r;
    assign load_out = load_rrr & load_rr & load_r;
endmodule