data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/COUNTER_CH.v
data/verilator_xmls/30034229-4e9d-493d-876a-bb48caeacca3.xml
module COUNTER_CH #(parameter BITWIDTH=2)(


COUNTER_Clk,
COUNTER_Clr,
COUNTER_En,


COUNTER_Out


);





input COUNTER_Clk;
input COUNTER_Clr;
input COUNTER_En;
output [BITWIDTH-1:0] COUNTER_Out;




reg [BITWIDTH-1:0] counter;






always@(posedge COUNTER_Clk or negedge COUNTER_Clr)
begin
		if(!COUNTER_Clr)
			counter<=0;
		else if(COUNTER_En)
			counter<=counter +1'b1;
end

assign COUNTER_Out=counter;


endmodule
module COUNTER_CH #(parameter BITWIDTH=2)(


COUNTER_Clk,
COUNTER_Clr,
COUNTER_En,


COUNTER_Out


);






input COUNTER_Clk;
input COUNTER_Clr;
input COUNTER_En;
output [BITWIDTH-1:0] COUNTER_Out;




reg [BITWIDTH-1:0] counter;






always@(posedge COUNTER_Clk or negedge COUNTER_Clr)
begin
		if(!COUNTER_Clr)
			counter<=0;
		else if(COUNTER_En)
			counter<=counter +1'b1;
end

assign COUNTER_Out=counter;


endmodule