data/full_repos/permissive/459421171/Pipelined/decode.v
data/verilator_xmls/0ad94ac4-996c-4ad2-b6b1-683ed00ad990.xml
module decode(clk,iCode,rA,rB,reg_stackA,reg_stackB,reg_stack4,valA,valB);

input clk;
input[3:0] iCode , rA , rB;
input[63:0]reg_stackA , reg_stackB , reg_stack4 ;

output reg[63:0] valA , valB;

always@(posedge clk)
begin
if(iCode==4'b0010)
begin
valA <= reg_stackA;
end

if(iCode==4'b0100)
    begin
      valA<=reg_stackA;
      valB<=reg_stackB;
    end
    if(iCode==4'b0101)
    begin
      valB=reg_stackB;
    end
    if(iCode==4'b0110)
    begin
      valA<=reg_stackA;
      valB<=reg_stackB;
    end



    if(iCode==4'b1000)
    begin
      valB<=reg_stack4;
    end
    if(iCode==4'b1001)
    begin
      valA<=reg_stack4;
      valB<=reg_stack4;
    end
    if(iCode==4'b1010)
    begin
      valA<=reg_stackA;
      valB<=reg_stack4;
    end
    if(iCode==4'b1011)
    begin
      valA<=reg_stack4;
      valB<=reg_stack4;
    end
  end

endmodule
module decode(clk,iCode,rA,rB,reg_stackA,reg_stackB,reg_stack4,valA,valB);


input clk;
input[3:0] iCode , rA , rB;
input[63:0]reg_stackA , reg_stackB , reg_stack4 ;

output reg[63:0] valA , valB;

always@(posedge clk)
begin
if(iCode==4'b0010)
begin
valA <= reg_stackA;
end

if(iCode==4'b0100)
    begin
      valA<=reg_stackA;
      valB<=reg_stackB;
    end
    if(iCode==4'b0101)
    begin
      valB=reg_stackB;
    end
    if(iCode==4'b0110)
    begin
      valA<=reg_stackA;
      valB<=reg_stackB;
    end



    if(iCode==4'b1000)
    begin
      valB<=reg_stack4;
    end
    if(iCode==4'b1001)
    begin
      valA<=reg_stack4;
      valB<=reg_stack4;
    end
    if(iCode==4'b1010)
    begin
      valA<=reg_stackA;
      valB<=reg_stack4;
    end
    if(iCode==4'b1011)
    begin
      valA<=reg_stack4;
      valB<=reg_stack4;
    end
  end

endmodule