data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   # 100 CLK = ~CLK;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/486598419/6.6/Asynchronous_D_FF_tb.v:30: Cannot find file containing module: \'Asynchronous_D_FF\'\nAsynchronous_D_FF uut(CLK,D,RST_n,Q1,Q2);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/Asynchronous_D_FF\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/Asynchronous_D_FF.v\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/Asynchronous_D_FF.sv\n             Asynchronous_D_FF\n             Asynchronous_D_FF.v\n             Asynchronous_D_FF.sv\n             obj_dir/Asynchronous_D_FF\n             obj_dir/Asynchronous_D_FF.v\n             obj_dir/Asynchronous_D_FF.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Asynchronous_D_FF_tb();
   reg CLK;
   reg D;
   reg RST_n;
   wire Q1;
   wire Q2;

Asynchronous_D_FF uut(CLK,D,RST_n,Q1,Q2);
always
begin
   # 100 CLK = ~CLK;
end

initial
   begin
   CLK=1;
   D=1;
   RST_n=1;
   #100;
   
   D=0;
   RST_n=0;
   #100;
   
   D=1;
   RST_n=1;
   #100;
   
   D=1;
   RST_n=1;
   #100;
   end

endmodule
module Asynchronous_D_FF_tb();

   reg CLK;
   reg D;
   reg RST_n;
   wire Q1;
   wire Q2;

Asynchronous_D_FF uut(CLK,D,RST_n,Q1,Q2);
always
begin
   # 100 CLK = ~CLK;
end

initial
   begin
   CLK=1;
   D=1;
   RST_n=1;
   #100;
   
   D=0;
   RST_n=0;
   #100;
   
   D=1;
   RST_n=1;
   #100;
   
   D=1;
   RST_n=1;
   #100;
   end

endmodule