data/full_repos/permissive/447976230/fpga/usrp3/top/x300/capture_ddrlvds.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/capture_ddrlvds.v:50: Cannot find file containing module: 'IBUFGDS'\n  IBUFGDS ss_clk_ibufgds_i (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/IBUFGDS\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/IBUFGDS.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/capture_ddrlvds.v:55: Cannot find file containing module: 'BUFG'\n  BUFG ss_clk_bufg_i (\n  ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/capture_ddrlvds.v:71: Cannot find file containing module: 'IBUFDS'\n    IBUFDS ibufds_i (\n    ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/capture_ddrlvds.v:116: Cannot find file containing module: 'IDDR'\n    IDDR #(\n    ^~~~\n%Error: Exiting due to 4 error(s)\n"
module capture_ddrlvds #(
  parameter WIDTH            = 14,
  parameter PATT_CHECKER     = "FALSE",
  parameter DATA_IDELAY_MODE = "BYPASSED",
  parameter DATA_IDELAY_VAL  = 16,
  parameter DATA_IDELAY_FREF = 200.0
) (

  input             adc_clk_p,
  input             adc_clk_n,
  input [WIDTH-1:0] adc_data_p,
  input [WIDTH-1:0] adc_data_n,
  

  input             radio_clk,
  

  input             data_delay_stb,
  input [4:0]       data_delay_val,


  output            adc_cap_clk,
  output [(2*WIDTH)-1:0] data_out,
  

  input             checker_en,
  output [3:0]      checker_locked,
  output [3:0]      checker_failed
);



  
  wire adc_buf_clk;
  



  IBUFGDS ss_clk_ibufgds_i (
    .I(adc_clk_p), .IB(adc_clk_n),
    .O(adc_buf_clk)
  );

  BUFG ss_clk_bufg_i (
    .I(adc_buf_clk),
    .O(adc_cap_clk)
  );




  wire [WIDTH-1:0]     adc_data_buf, adc_data_del;
  wire [(2*WIDTH)-1:0] adc_data_aclk;
  reg  [(2*WIDTH)-1:0] adc_data_rclk, adc_data_rclk_sync;

  genvar i;
  generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins


    IBUFDS ibufds_i (
      .I(adc_data_p[i]), .IB(adc_data_n[i]),
      .O(adc_data_buf[i])
    );




    if (DATA_IDELAY_MODE != "BYPASSED") begin

      reg       data_delay_stb_reg;
      reg [4:0] data_delay_val_reg;
      always @(posedge radio_clk)
        {data_delay_stb_reg, data_delay_val_reg} <= {data_delay_stb, data_delay_val};
      
      IDELAYE2 #(
        .DELAY_SRC("IDATAIN"),
        .IDELAY_TYPE(DATA_IDELAY_MODE=="FIXED"?"FIXED":"VAR_LOAD"),
        .SIGNAL_PATTERN("DATA"),
        .HIGH_PERFORMANCE_MODE("TRUE"),
        .PIPE_SEL("FALSE"),
        .CINVCTRL_SEL("FALSE"),
        .IDELAY_VALUE(DATA_IDELAY_VAL),
        .REFCLK_FREQUENCY(DATA_IDELAY_FREF)
      ) idelay_i (
        .DATAIN(1'b0),
        .IDATAIN(adc_data_buf[i]),
        .DATAOUT(adc_data_del[i]),
        .C(radio_clk),
        .LD(data_delay_stb_reg),
        .CE(1'b0),
        .INC(1'b0),
        .CINVCTRL(1'b0),
        .CNTVALUEIN(data_delay_val_reg),
        .CNTVALUEOUT(),
        .LDPIPEEN(1'b0),
        .REGRST(1'b0)
      );
    end else begin
      assign adc_data_del[i] = adc_data_buf[i];
    end




    IDDR #(
      .DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
    ) iddr_i (
      .C(adc_cap_clk), .CE(1'b1),
      .D(adc_data_del[i]), .R(1'b0), .S(1'b0),
      .Q1(adc_data_aclk[2*i]), .Q2(adc_data_aclk[(2*i)+1])
    );
  end endgenerate











  always @(posedge radio_clk)
    {adc_data_rclk_sync, adc_data_rclk} <= {adc_data_rclk, adc_data_aclk};


  assign data_out = adc_data_rclk_sync;




  generate if (PATT_CHECKER == "TRUE") begin
    wire        checker_en_aclk;
    wire [1:0]  checker_locked_aclk, checker_failed_aclk;

    synchronizer #(.INITIAL_VAL(1'b0)) checker_en_aclk_sync_i (
      .clk(adc_cap_clk), .rst(1'b0), .in(checker_en), .out(checker_en_aclk));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_0_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[0]), .out(checker_locked[0]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_1_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[1]), .out(checker_locked[1]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_0_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[0]), .out(checker_failed[0]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_1_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[1]), .out(checker_failed[1]));

    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) aclk_q_checker_i (
      .clk(adc_cap_clk), .rst(~checker_en_aclk),
      .valid(1'b1), .data(~adc_data_aclk[WIDTH-1:0]),
      .count(), .errors(),
      .locked(checker_locked_aclk[0]), .failed(checker_failed_aclk[0])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) aclk_i_checker_i (
      .clk(adc_cap_clk), .rst(~checker_en_aclk),
      .valid(1'b1), .data(~adc_data_aclk[(2*WIDTH)-1:WIDTH]),
      .count(), .errors(),
      .locked(checker_locked_aclk[1]), .failed(checker_failed_aclk[1])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) rclk_q_checker_i (
      .clk(radio_clk), .rst(~checker_en),
      .valid(1'b1), .data(~adc_data_rclk_sync[WIDTH-1:0]),
      .count(), .errors(),
      .locked(checker_locked[2]), .failed(checker_failed[2])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) rclk_i_checker_i (
      .clk(radio_clk), .rst(~checker_en),
      .valid(1'b1), .data(~adc_data_rclk_sync[(2*WIDTH)-1:WIDTH]),
      .count(), .errors(),
      .locked(checker_locked[3]), .failed(checker_failed[3])
    );
  end endgenerate

endmodule
module capture_ddrlvds #(
  parameter WIDTH            = 14,
  parameter PATT_CHECKER     = "FALSE",
  parameter DATA_IDELAY_MODE = "BYPASSED",
  parameter DATA_IDELAY_VAL  = 16,
  parameter DATA_IDELAY_FREF = 200.0
) (

  input             adc_clk_p,
  input             adc_clk_n,
  input [WIDTH-1:0] adc_data_p,
  input [WIDTH-1:0] adc_data_n,
  

  input             radio_clk,
  

  input             data_delay_stb,
  input [4:0]       data_delay_val,


  output            adc_cap_clk,
  output [(2*WIDTH)-1:0] data_out,
  

  input             checker_en,
  output [3:0]      checker_locked,
  output [3:0]      checker_failed
);




  
  wire adc_buf_clk;
  



  IBUFGDS ss_clk_ibufgds_i (
    .I(adc_clk_p), .IB(adc_clk_n),
    .O(adc_buf_clk)
  );

  BUFG ss_clk_bufg_i (
    .I(adc_buf_clk),
    .O(adc_cap_clk)
  );




  wire [WIDTH-1:0]     adc_data_buf, adc_data_del;
  wire [(2*WIDTH)-1:0] adc_data_aclk;
  reg  [(2*WIDTH)-1:0] adc_data_rclk, adc_data_rclk_sync;

  genvar i;
  generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins


    IBUFDS ibufds_i (
      .I(adc_data_p[i]), .IB(adc_data_n[i]),
      .O(adc_data_buf[i])
    );




    if (DATA_IDELAY_MODE != "BYPASSED") begin

      reg       data_delay_stb_reg;
      reg [4:0] data_delay_val_reg;
      always @(posedge radio_clk)
        {data_delay_stb_reg, data_delay_val_reg} <= {data_delay_stb, data_delay_val};
      
      IDELAYE2 #(
        .DELAY_SRC("IDATAIN"),
        .IDELAY_TYPE(DATA_IDELAY_MODE=="FIXED"?"FIXED":"VAR_LOAD"),
        .SIGNAL_PATTERN("DATA"),
        .HIGH_PERFORMANCE_MODE("TRUE"),
        .PIPE_SEL("FALSE"),
        .CINVCTRL_SEL("FALSE"),
        .IDELAY_VALUE(DATA_IDELAY_VAL),
        .REFCLK_FREQUENCY(DATA_IDELAY_FREF)
      ) idelay_i (
        .DATAIN(1'b0),
        .IDATAIN(adc_data_buf[i]),
        .DATAOUT(adc_data_del[i]),
        .C(radio_clk),
        .LD(data_delay_stb_reg),
        .CE(1'b0),
        .INC(1'b0),
        .CINVCTRL(1'b0),
        .CNTVALUEIN(data_delay_val_reg),
        .CNTVALUEOUT(),
        .LDPIPEEN(1'b0),
        .REGRST(1'b0)
      );
    end else begin
      assign adc_data_del[i] = adc_data_buf[i];
    end




    IDDR #(
      .DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
    ) iddr_i (
      .C(adc_cap_clk), .CE(1'b1),
      .D(adc_data_del[i]), .R(1'b0), .S(1'b0),
      .Q1(adc_data_aclk[2*i]), .Q2(adc_data_aclk[(2*i)+1])
    );
  end endgenerate











  always @(posedge radio_clk)
    {adc_data_rclk_sync, adc_data_rclk} <= {adc_data_rclk, adc_data_aclk};


  assign data_out = adc_data_rclk_sync;




  generate if (PATT_CHECKER == "TRUE") begin
    wire        checker_en_aclk;
    wire [1:0]  checker_locked_aclk, checker_failed_aclk;

    synchronizer #(.INITIAL_VAL(1'b0)) checker_en_aclk_sync_i (
      .clk(adc_cap_clk), .rst(1'b0), .in(checker_en), .out(checker_en_aclk));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_0_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[0]), .out(checker_locked[0]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_1_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[1]), .out(checker_locked[1]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_0_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[0]), .out(checker_failed[0]));
    synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_1_sync_i (
      .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[1]), .out(checker_failed[1]));

    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) aclk_q_checker_i (
      .clk(adc_cap_clk), .rst(~checker_en_aclk),
      .valid(1'b1), .data(~adc_data_aclk[WIDTH-1:0]),
      .count(), .errors(),
      .locked(checker_locked_aclk[0]), .failed(checker_failed_aclk[0])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) aclk_i_checker_i (
      .clk(adc_cap_clk), .rst(~checker_en_aclk),
      .valid(1'b1), .data(~adc_data_aclk[(2*WIDTH)-1:WIDTH]),
      .count(), .errors(),
      .locked(checker_locked_aclk[1]), .failed(checker_failed_aclk[1])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) rclk_q_checker_i (
      .clk(radio_clk), .rst(~checker_en),
      .valid(1'b1), .data(~adc_data_rclk_sync[WIDTH-1:0]),
      .count(), .errors(),
      .locked(checker_locked[2]), .failed(checker_failed[2])
    );
  
    cap_pattern_verifier #(
      .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1),
      .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1)
    ) rclk_i_checker_i (
      .clk(radio_clk), .rst(~checker_en),
      .valid(1'b1), .data(~adc_data_rclk_sync[(2*WIDTH)-1:WIDTH]),
      .count(), .errors(),
      .locked(checker_locked[3]), .failed(checker_failed[3])
    );
  end endgenerate

endmodule