data/full_repos/permissive/46804359/0_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/46804359/0_cpu.v:63: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                              : ... In instance processor\nassign readReg1 = instr[25-21];\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/46804359/0_cpu.v:64: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                              : ... In instance processor\nassign readReg2 = instr[20-16];\n                ^\n%Error: data/full_repos/permissive/46804359/0_cpu.v:75: Cannot find file containing module: \'pc\'\npc pc0(\n^~\n        ... Looked in:\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc.v\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: data/full_repos/permissive/46804359/0_cpu.v:85: Cannot find file containing module: \'Control\'\nControl ctrl0(\n^~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:100: Cannot find file containing module: \'Adder_32b\'\nAdder_32b pc_adder(\n^~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:108: Cannot find file containing module: \'Adder_32b\'\nAdder_32b adder1(\n^~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:115: Cannot find file containing module: \'reg_file\'\nreg_file registers(\n^~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:126: Cannot find file containing module: \'sign_extender\'\nsign_extender signext0(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:132: Cannot find file containing module: \'Shift_left2_26b\'\nShift_left2_26b sl26(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:138: Cannot find file containing module: \'Shift_left2_32b\'\nShift_left2_32b sl32(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:145: Cannot find file containing module: \'Mux2x1_5b\'\nMux2x1_5b Mux_RegDst(\n^~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:153: Cannot find file containing module: \'Mux2x1_32b\'\nMux2x1_32b Mux_ALUsrc(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:161: Cannot find file containing module: \'Mux2x1_32b\'\nMux2x1_32b Mux_MemtoReg(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:169: Cannot find file containing module: \'Mux2x1_32b\'\nMux2x1_32b Mux_Branch(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:177: Cannot find file containing module: \'Mux2x1_32b\'\nMux2x1_32b Mux_Jump(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:185: Cannot find file containing module: \'alu_control\'\nalu_control aluctrl(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/46804359/0_cpu.v:192: Cannot find file containing module: \'ALU\'\nALU alu0(\n^~~\n%Error: Exiting due to 15 error(s), 2 warning(s)\n'
module processor(
    input clk,
    input pc_reset,
    input pc_enable,
    input [31:0] instr,
    input [31:0] data_out,
    output wire[31:0] data_in,
    output wire[31:0] inst_addr,
    output wire[31:0] data_addr,
    output wire mem_read_ctrlsig,
    output wire mem_write_ctrlsig
    );


wire [31:0] pc_in;
wire [31:0] pc_out;

wire [31:0] readData1;
wire [31:0] readData2;
wire [31:0] sign_ext_out;

wire [4:0] reg_dst_out;
wire [31:0] alu_src_out;
wire [31:0] mem_to_reg_out;
wire [31:0] branch_out;

wire [31:0] add0_in1;
wire [31:0] pc_plus_four;
wire [31:0] adder_result;

wire [31:0] alu_data_output;

wire [31:0] sl32_out;
wire [31:0] jump_addr;

wire [25:0] sl26_in;
wire [27:0] sl26_out;

wire [15:0] sign_ext_in;

wire [5:0] opcode;
wire [5:0] aluctrl_func_op;

wire [4:0]reg_dst_input0;
wire [4:0]reg_dst_input1;

wire [4:0] readReg1;
wire [4:0] readReg2;
wire [4:0] writeReg;

wire [3:0] alu_ctrl;

wire [1:0] alu_op;

wire reg_dst, jump, branch, mem_to_reg, alu_src, reg_write, mux3_sel, zero, ctrl_mem_read, ctrl_mem_write;

assign add0_in1 = 32'd4;
assign jump_addr = {pc_plus_four[31:28], sl26_out[27:0]};
assign aluctrl_func_op = instr[5:0];
assign mux3_sel =  branch & zero;
assign readReg1 = instr[25-21];
assign readReg2 = instr[20-16];
assign inst_addr = pc_out;
assign data_in = readData2;
assign data_addr = alu_data_output;
assign writeReg = reg_dst_out;
assign opcode = instr[31:26];
assign sign_ext_in = instr[15:0];
assign sl26_in = instr[25:0];
assign reg_dst_input0 = instr[20:16];
assign reg_dst_input1 = instr[15:11];

pc pc0(
	.in(pc_in),
	.clk,
	.rst(pc_reset),
	.en(pc_enable),
	.out(pc_out)
	);



Control ctrl0(
	.clk,
	.opcode(opcode),
	.reg_dst(reg_dst),
	.jump(jump),
	.branch(branch),
	.ctrl_mem_read(mem_read_ctrlsig),
	.mem_to_reg(mem_to_reg),
	.ctrl_mem_write(mem_write_ctrlsig),
	.alu_src(alu_src),
	.reg_write(reg_write),
	.alu_op(alu_op)
	);


Adder_32b pc_adder(
	.clk,
	.input0(pc_out),
	.input1(add0_in1),
	.out(pc_plus_four)
	);


Adder_32b adder1(
	.clk,
	.input0(pc_plus_four),
	.input1(sl32_out),
	.out(adder_result)
	);

reg_file registers(
  .clk,
	.regWrite(reg_write),
	.readReg1(readReg1),
	.readReg2(readReg2),
	.writeReg(writeReg),
	.writeData(mem_to_reg_out),
	.readData1(readData1),
	.readData2(readData2)
	);

sign_extender signext0(
	.clk,
	.in(sign_ext_in),
	.out(sign_ext_out)
	);

Shift_left2_26b sl26(
	.clk,
	.in(sl26_in),
	.out(sl26_out)
	);

Shift_left2_32b sl32(
	.clk,
	.in(sign_ext_out),
	.out(sl32_out)
	);


Mux2x1_5b Mux_RegDst(
	.clk,
	.input0(reg_dst_input0),
	.input1(reg_dst_input1),
	.select(reg_dst),
	.out(reg_dst_out)
	);

Mux2x1_32b Mux_ALUsrc(
	.clk,
	.input0(readData2),
	.input1(sign_ext_out),
	.select(alu_src),
	.out(alu_src_out)
	);

Mux2x1_32b Mux_MemtoReg(
	.clk,
	.input0(alu_data_output),
	.input1(data_out),
	.select(mem_to_reg),
	.out(mem_to_reg_out)
	);

Mux2x1_32b Mux_Branch(
	.clk,
	.input0(pc_plus_four),
	.input1(adder_result),
	.select(mux3_sel),
	.out(branch_out)
	);

Mux2x1_32b Mux_Jump(
	.clk,
	.input0(branch_out),
	.input1(jump_addr),
	.select(jump),
	.out(pc_in)
	);

alu_control aluctrl(
	.clk,
	.alu_op,
	.func_op(aluctrl_func_op),
	.alu_control_sig(alu_ctrl)
	);

ALU alu0(
	.clk,
	.control(alu_ctrl),
	.data_input1(readData1),
	.data_input2(alu_src_out),
	.data_output(alu_data_output),
	.zero
	);

endmodule
module processor(
    input clk,
    input pc_reset,
    input pc_enable,
    input [31:0] instr,
    input [31:0] data_out,
    output wire[31:0] data_in,
    output wire[31:0] inst_addr,
    output wire[31:0] data_addr,
    output wire mem_read_ctrlsig,
    output wire mem_write_ctrlsig
    );



wire [31:0] pc_in;
wire [31:0] pc_out;

wire [31:0] readData1;
wire [31:0] readData2;
wire [31:0] sign_ext_out;

wire [4:0] reg_dst_out;
wire [31:0] alu_src_out;
wire [31:0] mem_to_reg_out;
wire [31:0] branch_out;

wire [31:0] add0_in1;
wire [31:0] pc_plus_four;
wire [31:0] adder_result;

wire [31:0] alu_data_output;

wire [31:0] sl32_out;
wire [31:0] jump_addr;

wire [25:0] sl26_in;
wire [27:0] sl26_out;

wire [15:0] sign_ext_in;

wire [5:0] opcode;
wire [5:0] aluctrl_func_op;

wire [4:0]reg_dst_input0;
wire [4:0]reg_dst_input1;

wire [4:0] readReg1;
wire [4:0] readReg2;
wire [4:0] writeReg;

wire [3:0] alu_ctrl;

wire [1:0] alu_op;

wire reg_dst, jump, branch, mem_to_reg, alu_src, reg_write, mux3_sel, zero, ctrl_mem_read, ctrl_mem_write;

assign add0_in1 = 32'd4;
assign jump_addr = {pc_plus_four[31:28], sl26_out[27:0]};
assign aluctrl_func_op = instr[5:0];
assign mux3_sel =  branch & zero;
assign readReg1 = instr[25-21];
assign readReg2 = instr[20-16];
assign inst_addr = pc_out;
assign data_in = readData2;
assign data_addr = alu_data_output;
assign writeReg = reg_dst_out;
assign opcode = instr[31:26];
assign sign_ext_in = instr[15:0];
assign sl26_in = instr[25:0];
assign reg_dst_input0 = instr[20:16];
assign reg_dst_input1 = instr[15:11];

pc pc0(
	.in(pc_in),
	.clk,
	.rst(pc_reset),
	.en(pc_enable),
	.out(pc_out)
	);



Control ctrl0(
	.clk,
	.opcode(opcode),
	.reg_dst(reg_dst),
	.jump(jump),
	.branch(branch),
	.ctrl_mem_read(mem_read_ctrlsig),
	.mem_to_reg(mem_to_reg),
	.ctrl_mem_write(mem_write_ctrlsig),
	.alu_src(alu_src),
	.reg_write(reg_write),
	.alu_op(alu_op)
	);


Adder_32b pc_adder(
	.clk,
	.input0(pc_out),
	.input1(add0_in1),
	.out(pc_plus_four)
	);


Adder_32b adder1(
	.clk,
	.input0(pc_plus_four),
	.input1(sl32_out),
	.out(adder_result)
	);

reg_file registers(
  .clk,
	.regWrite(reg_write),
	.readReg1(readReg1),
	.readReg2(readReg2),
	.writeReg(writeReg),
	.writeData(mem_to_reg_out),
	.readData1(readData1),
	.readData2(readData2)
	);

sign_extender signext0(
	.clk,
	.in(sign_ext_in),
	.out(sign_ext_out)
	);

Shift_left2_26b sl26(
	.clk,
	.in(sl26_in),
	.out(sl26_out)
	);

Shift_left2_32b sl32(
	.clk,
	.in(sign_ext_out),
	.out(sl32_out)
	);


Mux2x1_5b Mux_RegDst(
	.clk,
	.input0(reg_dst_input0),
	.input1(reg_dst_input1),
	.select(reg_dst),
	.out(reg_dst_out)
	);

Mux2x1_32b Mux_ALUsrc(
	.clk,
	.input0(readData2),
	.input1(sign_ext_out),
	.select(alu_src),
	.out(alu_src_out)
	);

Mux2x1_32b Mux_MemtoReg(
	.clk,
	.input0(alu_data_output),
	.input1(data_out),
	.select(mem_to_reg),
	.out(mem_to_reg_out)
	);

Mux2x1_32b Mux_Branch(
	.clk,
	.input0(pc_plus_four),
	.input1(adder_result),
	.select(mux3_sel),
	.out(branch_out)
	);

Mux2x1_32b Mux_Jump(
	.clk,
	.input0(branch_out),
	.input1(jump_addr),
	.select(jump),
	.out(pc_in)
	);

alu_control aluctrl(
	.clk,
	.alu_op,
	.func_op(aluctrl_func_op),
	.alu_control_sig(alu_ctrl)
	);

ALU alu0(
	.clk,
	.control(alu_ctrl),
	.data_input1(readData1),
	.data_input2(alu_src_out),
	.data_output(alu_data_output),
	.zero
	);

endmodule