data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_synch_cl_cg (

syncdata, 

cmp_clk, start_clk_cl, arst_l, force_cken, presyncdata
);

parameter SIZE = 1;

input  cmp_clk;
input  start_clk_cl;
input  arst_l;
input  force_cken;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire   [SIZE-1:0]  presyncdata_muxed; 


   assign presyncdata_muxed =  force_cken? { SIZE {1'b1}} :  {SIZE {start_clk_cl}}  & presyncdata;

   dffrl_async_ns  #(SIZE)  u_synch_jl_cl_ff1_nsr(
                   .din (presyncdata_muxed[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (syncdata[SIZE-1:0]));
endmodule
module ctu_synch_cl_cg (

syncdata, 

cmp_clk, start_clk_cl, arst_l, force_cken, presyncdata
);


parameter SIZE = 1;

input  cmp_clk;
input  start_clk_cl;
input  arst_l;
input  force_cken;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire   [SIZE-1:0]  presyncdata_muxed; 


   assign presyncdata_muxed =  force_cken? { SIZE {1'b1}} :  {SIZE {start_clk_cl}}  & presyncdata;

   dffrl_async_ns  #(SIZE)  u_synch_jl_cl_ff1_nsr(
                   .din (presyncdata_muxed[SIZE-1:0]),
                   .clk (cmp_clk),
                   .rst_l(arst_l),
                   .q (syncdata[SIZE-1:0]));
endmodule