data/full_repos/permissive/434840709/week13/1.v
data/verilator_xmls/053c212c-0be5-4e5d-aa5d-afbe4b38d41b.xml
module top_module (
    input clk,
    input reset,
    output [3:0] q
);
    reg [3:0] count;

    always @(posedge clk )
            if (reset)
                count <= 4'd1; 
            else if (count==4'd10) 
                count <= 4'd0;
            else 
                count <= count + 4'd1;

    assign q = count;  

endmodule
module top_module (
    input clk,
    input reset,
    output [3:0] q
);

    reg [3:0] count;

    always @(posedge clk )
            if (reset)
                count <= 4'd1; 
            else if (count==4'd10) 
                count <= 4'd0;
            else 
                count <= count + 4'd1;

    assign q = count;  

endmodule