data/full_repos/permissive/469312749/alu/work/verilog/shift_16_9.v
data/verilator_xmls/beaf9dae-f2a9-4edf-ba43-813af6a0376f.xml
module shift_16_9 (
    input [15:0] x,
    input [15:0] y,
    input [1:0] shiftAlufn,
    output reg [15:0] shiftOut
  );
  
  
  
  reg [15:0] temp;
  
  always @* begin
    
    case (shiftAlufn)
      2'h0: begin
        temp = x << y[0+3-:4];
      end
      2'h1: begin
        temp = x >> y[0+3-:4];
      end
      2'h2: begin
        temp = $signed(x) <<< y[0+3-:4];
      end
      2'h3: begin
        temp = $signed(x) >>> y[0+3-:4];
      end
      default: begin
        temp = 16'h0000;
      end
    endcase
    shiftOut = temp;
  end
endmodule
module shift_16_9 (
    input [15:0] x,
    input [15:0] y,
    input [1:0] shiftAlufn,
    output reg [15:0] shiftOut
  );

  
  
  
  reg [15:0] temp;
  
  always @* begin
    
    case (shiftAlufn)
      2'h0: begin
        temp = x << y[0+3-:4];
      end
      2'h1: begin
        temp = x >> y[0+3-:4];
      end
      2'h2: begin
        temp = $signed(x) <<< y[0+3-:4];
      end
      2'h3: begin
        temp = $signed(x) >>> y[0+3-:4];
      end
      default: begin
        temp = 16'h0000;
      end
    endcase
    shiftOut = temp;
  end
endmodule