data/full_repos/permissive/43856783/j1_soc/hdl/Position/lsr_div.v
data/verilator_xmls/d71ea3fd-0e08-4706-a221-62c0a2533280.xml
module lsr_div (clk , rst, DV_in, Result, INIT, SH, LDA, A);
  
  input clk;
  input rst;
  input [63:0] DV_in;
  input [63:0] Result;
  input INIT;
  input SH;
  input LDA;
  output reg [63:0] A;

reg [63:0] DV;

always @(negedge clk)
  
  if(INIT || rst) begin
	A=0;
	DV= DV_in;
  end
  else begin

	  if(SH) begin
		{A,DV}={A,DV}<<1;
	  end
	  else begin
	  	if(LDA)
			A=Result;
 	 	else
			A=A;
	  end
  end
endmodule
module lsr_div (clk , rst, DV_in, Result, INIT, SH, LDA, A);

  
  input clk;
  input rst;
  input [63:0] DV_in;
  input [63:0] Result;
  input INIT;
  input SH;
  input LDA;
  output reg [63:0] A;

reg [63:0] DV;

always @(negedge clk)
  
  if(INIT || rst) begin
	A=0;
	DV= DV_in;
  end
  else begin

	  if(SH) begin
		{A,DV}={A,DV}<<1;
	  end
	  else begin
	  	if(LDA)
			A=Result;
 	 	else
			A=A;
	  end
  end
endmodule