data/full_repos/permissive/506984841/fib_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #2 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1  data_reg = 16\'b0000111111111111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0000000000000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0001011111111110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0000000000000001;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0001011111111101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0000000000001010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1000100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0010100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1011100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1110000000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1101100000111111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b1001100000000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_reg = 16\'b0001111111110000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #6 b_control = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/fib_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = 0;\n  ^\n%Error: data/full_repos/permissive/506984841/fib_tb.v:19: Cannot find file containing module: \'core\'\n core uut (mem_addr,mem_write,mem_data,clk,rst);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/core\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/core.v\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/506984841/fib_tb.v:20: Cannot find file containing module: \'buffer\'\n buffer uub (mem_data,data_reg,b_control);\n ^~~~~~\n%Error: Exiting due to 2 error(s), 84 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fib_tb;


	reg clk;
	reg rst;
	reg b_control;
	reg [15:0] data_reg;


	wire [10:0] mem_addr;
	wire mem_write;


	wire [15:0] mem_data;


	core uut (mem_addr,mem_write,mem_data,clk,rst);
	buffer uub (mem_data,data_reg,b_control);

	initial begin
		clk = 0;
		rst = 0;
		b_control = 0;
		data_reg = 16'b0000000000000000;

		#2 rst = 1;
		#1 rst = 0;
		b_control = 1;
		#1  data_reg = 16'b0000111111111111;
		#10 data_reg = 16'b0000000000000000;
		#10 data_reg = 16'b0001011111111110;
		#10 data_reg = 16'b0000000000000001;		
		#10 data_reg = 16'b0001011111111101;
		#10 data_reg = 16'b0000000000001010;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1001100000000000;
		#10 data_reg = 16'b0001111111110000;
		#6 b_control = 0;
	end
	
	always begin
		#5 clk = 1;
		#5 clk = 0;
	end
      
endmodule
module fib_tb;



	reg clk;
	reg rst;
	reg b_control;
	reg [15:0] data_reg;


	wire [10:0] mem_addr;
	wire mem_write;


	wire [15:0] mem_data;


	core uut (mem_addr,mem_write,mem_data,clk,rst);
	buffer uub (mem_data,data_reg,b_control);

	initial begin
		clk = 0;
		rst = 0;
		b_control = 0;
		data_reg = 16'b0000000000000000;

		#2 rst = 1;
		#1 rst = 0;
		b_control = 1;
		#1  data_reg = 16'b0000111111111111;
		#10 data_reg = 16'b0000000000000000;
		#10 data_reg = 16'b0001011111111110;
		#10 data_reg = 16'b0000000000000001;		
		#10 data_reg = 16'b0001011111111101;
		#10 data_reg = 16'b0000000000001010;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1010100000000000;
		#10 data_reg = 16'b1000100000000000;
		#10 data_reg = 16'b1001000000000000;
		#10 data_reg = 16'b0010100000000000;
		#10 data_reg = 16'b1011100000000000;
		#10 data_reg = 16'b1110000000000000;
		#10 data_reg = 16'b1101100000111111;
		#10 data_reg = 16'b1001100000000000;
		#10 data_reg = 16'b0001111111110000;
		#6 b_control = 0;
	end
	
	always begin
		#5 clk = 1;
		#5 clk = 0;
	end
      
endmodule