data/full_repos/permissive/455874613/Projects/Module05/DFlop.v
data/verilator_xmls/415738da-4dcf-4c9d-a416-af64ef49ffd3.xml
module DFlop (
	input  arst  ,
	input  clk   ,
	input  din   ,
	input  load,
	input load_data,
	output reg dout
);

	always@(posedge clk or negedge arst) begin
		 if(~arst)
			dout <= 1'b0;
		 else if(~load)
			dout <= din;
			else
			 dout<=load_data;
	end

endmodule
module DFlop (
	input  arst  ,
	input  clk   ,
	input  din   ,
	input  load,
	input load_data,
	output reg dout
);


	always@(posedge clk or negedge arst) begin
		 if(~arst)
			dout <= 1'b0;
		 else if(~load)
			dout <= din;
			else
			 dout<=load_data;
	end

endmodule