data/full_repos/permissive/47037127/programcounter.v
data/verilator_xmls/d940e827-841d-436e-ad6d-74fb28fb0c2b.xml
module programcounter(
	CLK,
	INCREMENT,
	NEWV,
	WRITE,
	out
	);

input CLK;
input INCREMENT;
input [31:0] NEWV;
input WRITE;
output [31:0] out;

reg [31:0] val;
assign out=val;



always@(negedge CLK) begin
	if(~WRITE&&INCREMENT) begin
		val<=val+1;
	end
	else if(WRITE) begin
		val<=NEWV;
	end
end

initial begin
	val=0;
end
endmodule
module programcounter(
	CLK,
	INCREMENT,
	NEWV,
	WRITE,
	out
	);


input CLK;
input INCREMENT;
input [31:0] NEWV;
input WRITE;
output [31:0] out;

reg [31:0] val;
assign out=val;



always@(negedge CLK) begin
	if(~WRITE&&INCREMENT) begin
		val<=val+1;
	end
	else if(WRITE) begin
		val<=NEWV;
	end
end

initial begin
	val=0;
end
endmodule