data/full_repos/permissive/430179659/LAB4/tb/top.sv
1: b'%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:2: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430179659/LAB4/tb,data/full_repos/permissive/430179659/uvm_macros.svh\n             data/full_repos/permissive/430179659/LAB4/tb,data/full_repos/permissive/430179659/uvm_macros.svh.v\n             data/full_repos/permissive/430179659/LAB4/tb,data/full_repos/permissive/430179659/uvm_macros.svh.sv\n             uvm_macros.svh\n             uvm_macros.svh.v\n             uvm_macros.svh.sv\n             obj_dir/uvm_macros.svh\n             obj_dir/uvm_macros.svh.v\n             obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:3: Cannot find include file: ../src/dut_if.sv\n`include "../src/dut_if.sv" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:4: Cannot find include file: ../src/DUT.sv\n`include "../src/DUT.sv" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:5: Cannot find include file: ../tb/packet_in.sv\n`include "../tb/packet_in.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:6: Cannot find include file: ../tb/packet_out.sv\n`include "../tb/packet_out.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:7: Cannot find include file: ../tb/sequence_in.sv\n`include "../tb/sequence_in.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:8: Cannot find include file: ../tb/sequencer.sv\n`include "../tb/sequencer.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:9: Cannot find include file: ../tb/driver.sv\n`include "../tb/driver.sv" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:10: Cannot find include file: ../tb/driver_out.sv\n`include "../tb/driver_out.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:11: Cannot find include file: ../tb/monitor.sv\n`include "../tb/monitor.sv" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:12: Cannot find include file: ../tb/monitor_out.sv\n`include "../tb/monitor_out.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:13: Cannot find include file: ../tb/agent.sv\n`include "../tb/agent.sv" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:14: Cannot find include file: ../tb/agent_out.sv\n`include "../tb/agent_out.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:15: Cannot find include file: ../tb/refmod.sv\n`include "../tb/refmod.sv" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:16: Cannot find include file: ../tb/comparator.sv\n`include "../tb/comparator.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:17: Cannot find include file: ../tb/env.sv\n`include "../tb/env.sv" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:18: Cannot find include file: ../tb/simple_test.sv\n`include "../tb/simple_test.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n       ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/430179659/LAB4/tb/top.sv:28: Unsupported: Ignoring delay on this delayed statement.\n    #22 rst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/430179659/LAB4/tb/top.sv:32: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n%Error: data/full_repos/permissive/430179659/LAB4/tb/top.sv:53: syntax error, unexpected \'#\'\n    uvm_config_db#(input_vif)::set(uvm_root::get(), "*.env_h.mst.*", "vif", in);\n                 ^\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module top;
  logic clk;
  logic rst;
  
  initial begin
    clk = 0;
    rst = 1;
    #22 rst = 0;
    
  end
  
  always #5 clk = !clk;
  
  logic [1:0] state;
  
  dut_if in(clk, rst);
  dut_if out(clk, rst);
  
  DUT mul(in, out, state);

  initial begin
    `ifdef INCA
      $recordvars();
    `endif
    `ifdef VCS
      $vcdpluson;
    `endif
    `ifdef QUESTA
      $wlfdumpvars();
      set_config_int("*", "recording_detail", 1);
    `endif
    
    uvm_config_db#(input_vif)::set(uvm_root::get(), "*.env_h.mst.*", "vif", in);
    uvm_config_db#(output_vif)::set(uvm_root::get(), "*.env_h.slv.*",  "vif", out);
    
    run_test("simple_test");
  end
endmodule
module top;

  logic clk;
  logic rst;
  
  initial begin
    clk = 0;
    rst = 1;
    #22 rst = 0;
    
  end
  
  always #5 clk = !clk;
  
  logic [1:0] state;
  
  dut_if in(clk, rst);
  dut_if out(clk, rst);
  
  DUT mul(in, out, state);

  initial begin
    `ifdef INCA
      $recordvars();
    `endif
    `ifdef VCS
      $vcdpluson;
    `endif
    `ifdef QUESTA
      $wlfdumpvars();
      set_config_int("*", "recording_detail", 1);
    `endif
    
    uvm_config_db#(input_vif)::set(uvm_root::get(), "*.env_h.mst.*", "vif", in);
    uvm_config_db#(output_vif)::set(uvm_root::get(), "*.env_h.slv.*",  "vif", out);
    
    run_test("simple_test");
  end
endmodule