data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_half_adder_gates.v
data/verilator_xmls/3fd2b51a-ce63-4381-8748-082524bb12c9.xml
module half_adder_gates(x,y,sum,carry);
input x,y;
output sum,carry;

and U_carry (carry,x,y);
xor U_sum (sum,x,y);

endmodule
module half_adder_gates(x,y,sum,carry);

input x,y;
output sum,carry;

and U_carry (carry,x,y);
xor U_sum (sum,x,y);

endmodule