data/full_repos/permissive/435885222/sources/mem_wb.v
data/verilator_xmls/3c35720a-6cb7-4e5a-ae05-4d935d42709f.xml
module mem_wb(
    input clk,
    input rst,
    input [4:0] mem_wd,
    input mem_wreg,
    input [31:0] mem_wdata,
    output reg[4:0] wb_wd,
    output reg wb_wreg,
    output reg[31:0] wb_wdata
    );
    always @(posedge clk)begin
        if(rst==1'b1)begin
            wb_wd<=5'b00000;
            wb_wreg<=1'b0;
          wb_wdata<=32'h00000000;
        end else begin
            wb_wd<=mem_wd;
            wb_wreg<=mem_wreg;
            wb_wdata<=mem_wdata;
        end
    end
endmodule
module mem_wb(
    input clk,
    input rst,
    input [4:0] mem_wd,
    input mem_wreg,
    input [31:0] mem_wdata,
    output reg[4:0] wb_wd,
    output reg wb_wreg,
    output reg[31:0] wb_wdata
    );

    always @(posedge clk)begin
        if(rst==1'b1)begin
            wb_wd<=5'b00000;
            wb_wreg<=1'b0;
          wb_wdata<=32'h00000000;
        end else begin
            wb_wd<=mem_wd;
            wb_wreg<=mem_wreg;
            wb_wdata<=mem_wdata;
        end
    end
endmodule