data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:90: syntax error, unexpected class\nDeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));\n                  ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:98: syntax error, unexpected class, expecting '['\noutput class,\n       ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:202: syntax error, unexpected IDENTIFIER\ncomplement_rejfdb CP_L1_x1 (x1, x1c);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:545: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:553: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:752: syntax error, unexpected class, expecting '['\nmodule convert16_to_1(sig_out, class);\n                               ^~~~~\n%Error: Exiting due to 6 error(s)\n"
module shiftback2bit( 
dout,
din, 
clk,
rst
);
output reg [15:0] dout;
input [15:0] din; 
input  clk, rst;
always @(posedge clk)
begin
if (rst == 1'b1) dout <= 16'b0000000000000000;
else if (clk == 1'b1) dout[13:0] <= din[15:2];
dout [15:14] <= 2'b00;
end 

endmodule
module shiftback2bit( 
dout,
din, 
clk,
rst
);

output reg [15:0] dout;
input [15:0] din; 
input  clk, rst;
always @(posedge clk)
begin
if (rst == 1'b1) dout <= 16'b0000000000000000;
else if (clk == 1'b1) dout[13:0] <= din[15:2];
dout [15:14] <= 2'b00;
end 

endmodule