data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:10: Define or directive not defined: \'`outfile\'\n  file = $fopen(`outfile);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:10: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  file = $fopen(`outfile);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_0 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_0 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_1 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_1 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_2 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_2 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_3 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_3 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #2 clock = ~clock;\n   ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n'
module testbench();
reg clock = 0 , reset ;
reg req_0 , req_1 ,  req_2 , req_3; 
wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
integer file;

initial begin


  file = $fopen(`outfile);
  $fdisplay(file, "Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
  clock = 0;
  reset = 1;
  req_0 = 0;
  req_1 = 0;
  req_2 = 0;
  req_3 = 0;
  #10 reset = 1;
  #10 reset = 0;
  #10 req_0 = 1;
  #20 req_0 = 0;
  #10 req_1 = 1;
  #20 req_1 = 0;
  #10 req_2 = 1;
  #20 req_2 = 0;
  #10 req_3 = 1;
  #20 req_3 = 0;
  #10 $finish;
end

always @(negedge clock)
  $fdisplay(file, "%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);

initial begin
 #1;
 forever
   #2 clock = ~clock;
end

fsm_full U_fsm_full(
clock ,
reset ,
req_0 ,
req_1 ,
req_2 ,
req_3 ,
gnt_0 ,
gnt_1 ,
gnt_2 ,
gnt_3
);

endmodule
module testbench();

reg clock = 0 , reset ;
reg req_0 , req_1 ,  req_2 , req_3; 
wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
integer file;

initial begin


  file = $fopen(`outfile);
  $fdisplay(file, "Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
  clock = 0;
  reset = 1;
  req_0 = 0;
  req_1 = 0;
  req_2 = 0;
  req_3 = 0;
  #10 reset = 1;
  #10 reset = 0;
  #10 req_0 = 1;
  #20 req_0 = 0;
  #10 req_1 = 1;
  #20 req_1 = 0;
  #10 req_2 = 1;
  #20 req_2 = 0;
  #10 req_3 = 1;
  #20 req_3 = 0;
  #10 $finish;
end

always @(negedge clock)
  $fdisplay(file, "%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);

initial begin
 #1;
 forever
   #2 clock = ~clock;
end

fsm_full U_fsm_full(
clock ,
reset ,
req_0 ,
req_1 ,
req_2 ,
req_3 ,
gnt_0 ,
gnt_1 ,
gnt_2 ,
gnt_3
);

endmodule