data/full_repos/permissive/48602886/src/memory_if/memory_if.sv
1: b'%Error: data/full_repos/permissive/48602886/src/memory_if/memory_if.sv:51: Cannot find file containing module: \'memory_if_sync_fifo\'\n memory_if_sync_fifo\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48602886/src/memory_if,data/full_repos/permissive/48602886/memory_if_sync_fifo\n             data/full_repos/permissive/48602886/src/memory_if,data/full_repos/permissive/48602886/memory_if_sync_fifo.v\n             data/full_repos/permissive/48602886/src/memory_if,data/full_repos/permissive/48602886/memory_if_sync_fifo.sv\n             memory_if_sync_fifo\n             memory_if_sync_fifo.v\n             memory_if_sync_fifo.sv\n             obj_dir/memory_if_sync_fifo\n             obj_dir/memory_if_sync_fifo.v\n             obj_dir/memory_if_sync_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/memory_if/memory_if.sv:78: Operator OR expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance memory_if\n assign oMEM_BYTEENA = {8{!req_fifo_rd_rw}} | (req_fifo_rd_addr[0])? {~req_fifo_rd_mask, 4\'h0} : {4\'h0, ~req_fifo_rd_mask};\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/memory_if/memory_if.sv:78: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                 : ... In instance memory_if\n assign oMEM_BYTEENA = {8{!req_fifo_rd_rw}} | (req_fifo_rd_addr[0])? {~req_fifo_rd_mask, 4\'h0} : {4\'h0, ~req_fifo_rd_mask};\n                                                                   ^\n%Error: data/full_repos/permissive/48602886/src/memory_if/memory_if.sv:112: Cannot find file containing module: \'memory_if_sync_fifo\'\n memory_if_sync_fifo\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module memory_if(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,


		input wire iCPU_REQ,
		output wire oCPU_BUSY,
		input wire [3:0] iCPU_MASK,
		input wire iCPU_RW,
		input wire [31:0] iCPU_ADDR,

		input wire [31:0] iCPU_DATA,

		output wire oCPU_VALID,
		input wire iCPU_BUSY,
		output wire [63:0] oCPU_DATA,

		output wire oMEM_WR,
		output wire [7:0] oMEM_BYTEENA,
		output wire [31:0] oMEM_ADDR,
		output wire [63:0] oMEM_DATA,
		input wire [63:0] iMEM_DATA
	);



	wire get_fifo_wr_stop;


	wire req_fifo_wr_almost_full;
	wire req_fifo_rd_empty;

	wire [3:0] req_fifo_rd_mask;
	wire req_fifo_rd_rw;
	wire [31:0] req_fifo_rd_addr;
	wire [31:0] req_fifo_rd_data;

	memory_if_sync_fifo
	#(
		.N(4+1+32+32),
		.DEPTH(8),
		.D_N(3)
	)REQ_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),

		.oCOUNT(),

		.iWR_EN(iCPU_REQ && !req_fifo_wr_almost_full),
		.iWR_DATA({iCPU_MASK, iCPU_RW, iCPU_ADDR, iCPU_DATA}),
		.oWR_FULL(),
		.oWR_ALMOST_FULL(req_fifo_wr_almost_full),

		.iRD_EN(!get_fifo_wr_stop && !req_fifo_rd_empty),
		.oRD_DATA({req_fifo_rd_mask, req_fifo_rd_rw, req_fifo_rd_addr, req_fifo_rd_data}),
		.oRD_EMPTY(req_fifo_rd_empty),
		.oRD_ALMOST_EMPTY()
	);

	assign oCPU_BUSY = req_fifo_wr_almost_full;

	assign oMEM_WR = !req_fifo_rd_empty && req_fifo_rd_rw;
	assign oMEM_BYTEENA = {8{!req_fifo_rd_rw}} | (req_fifo_rd_addr[0])? {~req_fifo_rd_mask, 4'h0} : {4'h0, ~req_fifo_rd_mask};
	assign oMEM_ADDR = {1'b0, req_fifo_rd_addr[31:1]};
	assign oMEM_DATA = {req_fifo_rd_data, req_fifo_rd_data};



	reg request_rd_delay0;
	reg request_rd_delay1;

	always_ff@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			request_rd_delay0 <= 1'b0;
			request_rd_delay1 <= 1'b0;
		end
		else if(iRESET_SYNC)begin
			request_rd_delay0 <= 1'b0;
			request_rd_delay1 <= 1'b0;
		end
		else begin
			request_rd_delay0 <= !get_fifo_wr_stop && !req_fifo_rd_empty && !req_fifo_rd_rw;
			request_rd_delay1 <= request_rd_delay0;
		end
	end


	wire [3:0] get_fifo_count;
	assign get_fifo_wr_stop = !(get_fifo_count < 4'hb);

	wire get_fifo_rd_empty;

	memory_if_sync_fifo
	#(
		.N(64),
		.DEPTH(16),
		.D_N(4)
	)GET_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),

		.oCOUNT(get_fifo_count),

		.iWR_EN(request_rd_delay1),
		.iWR_DATA(iMEM_DATA),
		.oWR_FULL(),
		.oWR_ALMOST_FULL(),

		.iRD_EN(!iCPU_BUSY && !get_fifo_rd_empty),
		.oRD_DATA(oCPU_DATA),
		.oRD_EMPTY(get_fifo_rd_empty),
		.oRD_ALMOST_EMPTY()
	);

	assign oCPU_VALID = !get_fifo_rd_empty;


endmodule
module memory_if(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,


		input wire iCPU_REQ,
		output wire oCPU_BUSY,
		input wire [3:0] iCPU_MASK,
		input wire iCPU_RW,
		input wire [31:0] iCPU_ADDR,

		input wire [31:0] iCPU_DATA,

		output wire oCPU_VALID,
		input wire iCPU_BUSY,
		output wire [63:0] oCPU_DATA,

		output wire oMEM_WR,
		output wire [7:0] oMEM_BYTEENA,
		output wire [31:0] oMEM_ADDR,
		output wire [63:0] oMEM_DATA,
		input wire [63:0] iMEM_DATA
	);




	wire get_fifo_wr_stop;


	wire req_fifo_wr_almost_full;
	wire req_fifo_rd_empty;

	wire [3:0] req_fifo_rd_mask;
	wire req_fifo_rd_rw;
	wire [31:0] req_fifo_rd_addr;
	wire [31:0] req_fifo_rd_data;

	memory_if_sync_fifo
	#(
		.N(4+1+32+32),
		.DEPTH(8),
		.D_N(3)
	)REQ_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),

		.oCOUNT(),

		.iWR_EN(iCPU_REQ && !req_fifo_wr_almost_full),
		.iWR_DATA({iCPU_MASK, iCPU_RW, iCPU_ADDR, iCPU_DATA}),
		.oWR_FULL(),
		.oWR_ALMOST_FULL(req_fifo_wr_almost_full),

		.iRD_EN(!get_fifo_wr_stop && !req_fifo_rd_empty),
		.oRD_DATA({req_fifo_rd_mask, req_fifo_rd_rw, req_fifo_rd_addr, req_fifo_rd_data}),
		.oRD_EMPTY(req_fifo_rd_empty),
		.oRD_ALMOST_EMPTY()
	);

	assign oCPU_BUSY = req_fifo_wr_almost_full;

	assign oMEM_WR = !req_fifo_rd_empty && req_fifo_rd_rw;
	assign oMEM_BYTEENA = {8{!req_fifo_rd_rw}} | (req_fifo_rd_addr[0])? {~req_fifo_rd_mask, 4'h0} : {4'h0, ~req_fifo_rd_mask};
	assign oMEM_ADDR = {1'b0, req_fifo_rd_addr[31:1]};
	assign oMEM_DATA = {req_fifo_rd_data, req_fifo_rd_data};



	reg request_rd_delay0;
	reg request_rd_delay1;

	always_ff@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			request_rd_delay0 <= 1'b0;
			request_rd_delay1 <= 1'b0;
		end
		else if(iRESET_SYNC)begin
			request_rd_delay0 <= 1'b0;
			request_rd_delay1 <= 1'b0;
		end
		else begin
			request_rd_delay0 <= !get_fifo_wr_stop && !req_fifo_rd_empty && !req_fifo_rd_rw;
			request_rd_delay1 <= request_rd_delay0;
		end
	end


	wire [3:0] get_fifo_count;
	assign get_fifo_wr_stop = !(get_fifo_count < 4'hb);

	wire get_fifo_rd_empty;

	memory_if_sync_fifo
	#(
		.N(64),
		.DEPTH(16),
		.D_N(4)
	)GET_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),

		.oCOUNT(get_fifo_count),

		.iWR_EN(request_rd_delay1),
		.iWR_DATA(iMEM_DATA),
		.oWR_FULL(),
		.oWR_ALMOST_FULL(),

		.iRD_EN(!iCPU_BUSY && !get_fifo_rd_empty),
		.oRD_DATA(oCPU_DATA),
		.oRD_EMPTY(get_fifo_rd_empty),
		.oRD_ALMOST_EMPTY()
	);

	assign oCPU_VALID = !get_fifo_rd_empty;


endmodule