data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/mux2_1_1bit.v
data/verilator_xmls/412f18f2-5cb3-476c-892f-a856d3d14d9e.xml
module mux2_1_1bit(
input a,b,s,
output y
    );
assign y=a&~s|b&s;

endmodule
module mux2_1_1bit(
input a,b,s,
output y
    );

assign y=a&~s|b&s;

endmodule