data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/clock_divider.v
1: b"%Error: data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/clock_divider.v:11: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/531248401/module2_blink/2.2-blink_clock_divider/clock_divider.v:16: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module clock_divider(
    input clk,
    input [23:0] div,
    output slow_clk,
);

reg [23:0] counter;
reg slow_clk;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter >= div) begin
        counter <= 0;
        slow_clk = ~slow_clk;
    end
end

endmodule
module clock_divider(
    input clk,
    input [23:0] div,
    output slow_clk,
);


reg [23:0] counter;
reg slow_clk;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter >= div) begin
        counter <= 0;
        slow_clk = ~slow_clk;
    end
end

endmodule