data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v
1: b"%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:52: Define or directive not defined: '`MPRJ_IO_PADS'\n  input  [`MPRJ_IO_PADS-1:0] io_in,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:53: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_out,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:54: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_oeb,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:62: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_in;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:63: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_out;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n  wire [`MPRJ_IO_PADS-1:0] io_oeb;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:98: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/466022941/verilog/rtl/btc_miner_top_old.v:116: syntax error, unexpected ||, expecting ')' or ',' or or\n  always @(la_data_in || la_oenb || la_sel || o_nonce || o_block_header || o_target) begin\n                      ^~\n%Error: Exiting due to 8 error(s)\n"
module miner_ctrl #(
  parameter BITS = 32
)(
  input clk,
  input rst,
  input valid,
  input wb_we,
  input [BITS-1:0] wdata,
  input [BITS-1:0] la_write0,
  input [BITS-1:0] la_write3,
  input [BITS-1:0] la_input0,
  input [BITS-1:0] la_input3,
  output ready,
  output [BITS-1:0] rdata,
  output [639:0] block_header,
  output [255:0] target,
  output [BITS-1:0] nonce,
  output idle
);



  localparam WAIT_IN=0, READ_IN=1, COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4;

  reg [2:0] state;

  reg ready;
  reg [BITS-1:0] rdata;
  reg [BITS-1:0] wb_data_reg;
  reg [BITS-1:0] nonce;
  reg [BITS-1:0] encoded_target;
  reg [255:0] target;
  reg miner_rst;

  reg [639:0] block_header;
  reg [255:0] o_hash_val;
  reg o_done_hash;

  wire idle;
  wire start_ctrl;

  assign idle = (state == WAIT_IN) ? 1'b1 : 1'b0;
  assign start_ctrl = la_write3[12] ? la_input3[12] : 1'b0;


  integer unsigned count;

  always @(posedge clk) begin
    if (rst) begin
      ready <= 0;
      rdata <= 0;
      wb_data_reg <= 0;
      nonce <= 0;
      encoded_target <= 0;
      target <= 0;
      count <= 0;
      miner_rst <= 1;
      block_header <= 0;

      state <= WAIT_IN;
    end else begin
      ready <= 1'b0;


      case (state)
        WAIT_IN: begin

          miner_rst <= 1;
          if (start_ctrl == 1) begin
            state <= READ_IN;
          end
        end

        READ_IN: begin

          miner_rst <= 1;

          if (valid && !ready) begin
            ready <= 1'b1;

            if (wb_we) begin

              if (count == 0) begin
                block_header[BITS-1:0] <= wdata;
                count <= count + 1;
              end else if (count == 1) begin
                block_header[BITS*2-1:BITS] <= wdata;
                count <= count + 1;
              end else if (count == 2) begin
                block_header[BITS*3-1:BITS*2] <= wdata;
                count <= count + 1;
              end else if (count == 3) begin
                block_header[BITS*4-1:BITS*3] <= wdata;
                count <= count + 1;
              end else if (count == 4) begin
                block_header[BITS*5-1:BITS*4] <= wdata;
                count <= count + 1;
              end else if (count == 5) begin
                block_header[BITS*6-1:BITS*5] <= wdata;
                count <= count + 1;
              end else if (count == 6) begin
                block_header[BITS*7-1:BITS*6] <= wdata;
                count <= count + 1;
              end else if (count == 7) begin
                block_header[BITS*8-1:BITS*7] <= wdata;
                count <= count + 1;
              end else if (count == 8) begin
                block_header[BITS*9-1:BITS*8] <= wdata;
                count <= count + 1;
              end else if (count == 9) begin
                block_header[BITS*10-1:BITS*9] <= wdata;
                count <= count + 1;
              end

              if (count == 18) begin

                encoded_target <= wdata;
                target <= {{(255-BITS){1'b0}}, wdata};
                count <= count + 1;
              end else if (count >= 19) begin
                block_header[639:608] <= nonce;
                count <= 0;
                nonce <= nonce + 1;
                miner_rst <= 0;
                state <= COMPUTE;
              end else begin
                count <= count + 1;
              end
            end
          end
        end

        COMPUTE: begin

          if (o_done_hash) begin

            if (o_hash_val < target) begin
              state <= WRITE_OUT;
            end else begin
              miner_rst <= 1;
              block_header[639:608] <= nonce;
              state <= INCR_NONCE;
            end
          end else begin
            miner_rst <= 0;
          end
        end

        INCR_NONCE: begin

          miner_rst <= 0;
          nonce <= nonce + 1;
          state <= COMPUTE;
        end
          
        WRITE_OUT: begin

          if (valid && !ready) begin
            ready <= 1'b1;

            if (wb_we) begin

            end else begin

              rdata <= o_hash_val[BITS*count +:BITS];
              if (count >= 7) begin
                count <= 0;
                state <= WAIT_IN;
              end else begin
                count <= count + 1;
              end
            end
          end
        end

      endcase
    end
  end

  miner double_sha256_miner(
    .block(block_header),
    .clk(clk),
    .rst(rst),
    .hashed(o_hash_val),
    .done(o_done_hash)
  );
endmodule
module miner_ctrl #(
  parameter BITS = 32
)(
  input clk,
  input rst,
  input valid,
  input wb_we,
  input [BITS-1:0] wdata,
  input [BITS-1:0] la_write0,
  input [BITS-1:0] la_write3,
  input [BITS-1:0] la_input0,
  input [BITS-1:0] la_input3,
  output ready,
  output [BITS-1:0] rdata,
  output [639:0] block_header,
  output [255:0] target,
  output [BITS-1:0] nonce,
  output idle
);




  localparam WAIT_IN=0, READ_IN=1, COMPUTE=2, INCR_NONCE=3, WRITE_OUT=4;

  reg [2:0] state;

  reg ready;
  reg [BITS-1:0] rdata;
  reg [BITS-1:0] wb_data_reg;
  reg [BITS-1:0] nonce;
  reg [BITS-1:0] encoded_target;
  reg [255:0] target;
  reg miner_rst;

  reg [639:0] block_header;
  reg [255:0] o_hash_val;
  reg o_done_hash;

  wire idle;
  wire start_ctrl;

  assign idle = (state == WAIT_IN) ? 1'b1 : 1'b0;
  assign start_ctrl = la_write3[12] ? la_input3[12] : 1'b0;


  integer unsigned count;

  always @(posedge clk) begin
    if (rst) begin
      ready <= 0;
      rdata <= 0;
      wb_data_reg <= 0;
      nonce <= 0;
      encoded_target <= 0;
      target <= 0;
      count <= 0;
      miner_rst <= 1;
      block_header <= 0;

      state <= WAIT_IN;
    end else begin
      ready <= 1'b0;


      case (state)
        WAIT_IN: begin

          miner_rst <= 1;
          if (start_ctrl == 1) begin
            state <= READ_IN;
          end
        end

        READ_IN: begin

          miner_rst <= 1;

          if (valid && !ready) begin
            ready <= 1'b1;

            if (wb_we) begin

              if (count == 0) begin
                block_header[BITS-1:0] <= wdata;
                count <= count + 1;
              end else if (count == 1) begin
                block_header[BITS*2-1:BITS] <= wdata;
                count <= count + 1;
              end else if (count == 2) begin
                block_header[BITS*3-1:BITS*2] <= wdata;
                count <= count + 1;
              end else if (count == 3) begin
                block_header[BITS*4-1:BITS*3] <= wdata;
                count <= count + 1;
              end else if (count == 4) begin
                block_header[BITS*5-1:BITS*4] <= wdata;
                count <= count + 1;
              end else if (count == 5) begin
                block_header[BITS*6-1:BITS*5] <= wdata;
                count <= count + 1;
              end else if (count == 6) begin
                block_header[BITS*7-1:BITS*6] <= wdata;
                count <= count + 1;
              end else if (count == 7) begin
                block_header[BITS*8-1:BITS*7] <= wdata;
                count <= count + 1;
              end else if (count == 8) begin
                block_header[BITS*9-1:BITS*8] <= wdata;
                count <= count + 1;
              end else if (count == 9) begin
                block_header[BITS*10-1:BITS*9] <= wdata;
                count <= count + 1;
              end

              if (count == 18) begin

                encoded_target <= wdata;
                target <= {{(255-BITS){1'b0}}, wdata};
                count <= count + 1;
              end else if (count >= 19) begin
                block_header[639:608] <= nonce;
                count <= 0;
                nonce <= nonce + 1;
                miner_rst <= 0;
                state <= COMPUTE;
              end else begin
                count <= count + 1;
              end
            end
          end
        end

        COMPUTE: begin

          if (o_done_hash) begin

            if (o_hash_val < target) begin
              state <= WRITE_OUT;
            end else begin
              miner_rst <= 1;
              block_header[639:608] <= nonce;
              state <= INCR_NONCE;
            end
          end else begin
            miner_rst <= 0;
          end
        end

        INCR_NONCE: begin

          miner_rst <= 0;
          nonce <= nonce + 1;
          state <= COMPUTE;
        end
          
        WRITE_OUT: begin

          if (valid && !ready) begin
            ready <= 1'b1;

            if (wb_we) begin

            end else begin

              rdata <= o_hash_val[BITS*count +:BITS];
              if (count >= 7) begin
                count <= 0;
                state <= WAIT_IN;
              end else begin
                count <= count + 1;
              end
            end
          end
        end

      endcase
    end
  end

  miner double_sha256_miner(
    .block(block_header),
    .clk(clk),
    .rst(rst),
    .hashed(o_hash_val),
    .done(o_done_hash)
  );
endmodule