data/full_repos/permissive/445357518/regfile.v
data/verilator_xmls/552fc6b0-b9bc-4c4f-a7cc-ce192500d309.xml
module Dec(a, b);
	parameter n = 3;
	parameter m = 8;

	input[n-1:0] a;
	output[m-1:0] b;

	assign b = 1<<a;
endmodule
module Dec(a, b);

	parameter n = 3;
	parameter m = 8;

	input[n-1:0] a;
	output[m-1:0] b;

	assign b = 1<<a;
endmodule