data/full_repos/permissive/493514142/verilog/rtl/FPU/LZD_comb.v
data/verilator_xmls/5ff5d6c8-88e4-403c-9d29-6ee57a0ba6e8.xml
module FPU_LZD_comb (in_bits, out_pos, out_val);

input [1:0]in_bits;

output out_pos;
output out_val;

assign out_pos = !in_bits[1];
assign out_val = |in_bits;

endmodule
module FPU_LZD_comb (in_bits, out_pos, out_val);


input [1:0]in_bits;

output out_pos;
output out_val;

assign out_pos = !in_bits[1];
assign out_val = |in_bits;

endmodule