data/full_repos/permissive/431605717/Code/RV32IM/register.v
data/verilator_xmls/14beb590-1822-40e7-809b-fe576da10d9d.xml
module risc_v_32_regfile(clk,clrn,rd1,rd2,wr,wd,wreg,read_data1,read_data2);
    input         clk, clrn;
    input  [4:0]  rd1;
    input  [4:0]  rd2;
    input  [4:0]  wr;
    input  [31:0] wd;
    input         wreg;
    output [31:0] read_data1;
    output [31:0] read_data2;
    
    reg  [31:0] regfile [1:31];
    
    
    wire [31:0]   read_data1 = (rd1==0) ? 0 : regfile[rd1];
    wire [31:0]   read_data2 = (rd2==0) ? 0 : regfile[rd2];
    
    always @ (negedge clk) begin
        if (wreg && (wr != 0)) begin
            regfile[wr] <= wd;
        end
    end
    
endmodule
module risc_v_32_regfile(clk,clrn,rd1,rd2,wr,wd,wreg,read_data1,read_data2);

    input         clk, clrn;
    input  [4:0]  rd1;
    input  [4:0]  rd2;
    input  [4:0]  wr;
    input  [31:0] wd;
    input         wreg;
    output [31:0] read_data1;
    output [31:0] read_data2;
    
    reg  [31:0] regfile [1:31];
    
    
    wire [31:0]   read_data1 = (rd1==0) ? 0 : regfile[rd1];
    wire [31:0]   read_data2 = (rd2==0) ? 0 : regfile[rd2];
    
    always @ (negedge clk) begin
        if (wreg && (wr != 0)) begin
            regfile[wr] <= wd;
        end
    end
    
endmodule