data/full_repos/permissive/517239653/wave_gen.v
1: b"%Error: data/full_repos/permissive/517239653/wave_gen.v:11: Cannot find file containing module: 'divider'\ndivider CLOCK_DIV(slow_clk, clk, clk_div);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.v\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Error: Exiting due to 1 error(s)\n"
module wave_gen(word_out, clk, clk_div, lut);

parameter LUT_SIZE = 4096;
output [7:0] word_out;
input clk;
input [31:0] clk_div;
input [LUT_SIZE-1:0] lut;


wire slow_clk;
divider CLOCK_DIV(slow_clk, clk, clk_div);
reg [31:0] wave_ind = 0;
reg [7:0] word_reg = 0;

assign word_out = word_reg;

always @(posedge slow_clk) begin
    word_reg <= lut[(((wave_ind + 1)<<3)-1)-:8];
    if(wave_ind >= (LUT_SIZE >> 3)) begin
        wave_ind <= 0;
    end else begin
        wave_ind <= wave_ind + 1;
    end
end

endmodule
module wave_gen(word_out, clk, clk_div, lut);


parameter LUT_SIZE = 4096;
output [7:0] word_out;
input clk;
input [31:0] clk_div;
input [LUT_SIZE-1:0] lut;


wire slow_clk;
divider CLOCK_DIV(slow_clk, clk, clk_div);
reg [31:0] wave_ind = 0;
reg [7:0] word_reg = 0;

assign word_out = word_reg;

always @(posedge slow_clk) begin
    word_reg <= lut[(((wave_ind + 1)<<3)-1)-:8];
    if(wave_ind >= (LUT_SIZE >> 3)) begin
        wave_ind <= 0;
    end else begin
        wave_ind <= wave_ind + 1;
    end
end

endmodule