data/full_repos/permissive/427221126/src/BasicArith.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/BasicArith.v:89: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'MAC\'\nmodule MAC\n       ^~~\n                                                                           : ... Top module \'ComplexMult\'\nmodule ComplexMult \n       ^~~~~~~~~~~\n                                                                           : ... Top module \'FMA\'\nmodule FMA\n       ^~~\n                                                                           : ... Top module \'Acc\'\nmodule Acc\n       ^~~\n                                                                           : ... Top module \'FMApFRound\'\nmodule FMApFRound\n       ^~~~~~~~~~\n                                                                           : ... Top module \'Max4\'\nmodule Max4\n       ^~~~\n                                                                           : ... Top module \'Add3\'\nmodule Add3(clk, reset, en, a, d, c, y);\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 24 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the LHS, but LHS\'s VARREF \'ain\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'din\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 96 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the LHS, but LHS\'s VARREF \'ain\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the RHS, but RHS\'s VARREF \'din\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:555: Output port connection \'Y\' expects 97 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 50 bits.\n                                                                         : ... In instance Add3\n  .Y(y)\n   ^\n%Error: data/full_repos/permissive/427221126/src/BasicArith.v:408: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.sv\n             FRound\n             FRound.v\n             FRound.sv\n             obj_dir/FRound\n             obj_dir/FRound.v\n             obj_dir/FRound.sv\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:291: Operator ASSIGNDLY expects 47 bits on the Assign RHS, but Assign RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= din_reg;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:293: Operator ADD expects 47 bits on the RHS, but RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= sum + din_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:225: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 29 bits.\n                                                                         : ... In instance FMA\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:76: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= mult;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:78: Operator ADD expects 42 bits on the RHS, but RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= sum + mult;\n                   ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module ComplexMult 
  #( 
    parameter INWIDTH = 16 
  )
  (
    input clk, reset, en,
    input signed [INWIDTH-1:0]    ar, ai, br, bi,
    output signed [2*INWIDTH:0]   pr, pi
  );

  reg signed [INWIDTH-1:0] ar_d, ar_d2, ar_d3, ar_d4;
  reg signed [INWIDTH-1:0] ai_d, ai_d2, ai_d3, ai_d4;
  reg signed [INWIDTH-1:0] br_d, br_d2, br_d3, br_d4;
  reg signed [INWIDTH-1:0] bi_d, bi_d2, bi_d3, bi_d4;
  reg signed [INWIDTH:0]   common_add;
  reg signed [2*INWIDTH:0] common_mult, common, common_d_1, common_d_2;
  reg signed [INWIDTH:0] pr_add, pi_add;
  reg signed [2*INWIDTH:0] pr_mult, pi_mult, pr_ppln, pi_ppln;

  always @(posedge clk)
    if (reset) begin
      ar_d  <= 0;
      ar_d2 <= 0;
      ar_d3 <= 0;
      ar_d4 <= 0;
      ai_d  <= 0;
      ai_d2 <= 0;
      ai_d3 <= 0;
      ai_d4 <= 0;
      br_d  <= 0;
      br_d2 <= 0;
      br_d3 <= 0;
      br_d4 <= 0;
      bi_d  <= 0;
      bi_d2 <= 0;
      bi_d3 <= 0;
      bi_d4 <= 0;
    end else if (en) begin
      ar_d  <= ar;
      ar_d2 <= ar_d;
      ar_d3 <= ar_d2;
      ar_d4 <= ar_d3;
      ai_d  <= ai;
      ai_d2 <= ai_d;
      ai_d3 <= ai_d2;
      ai_d4 <= ai_d3;
      br_d  <= br;
      br_d2 <= br_d;
      br_d3 <= br_d2;
      br_d4 <= br_d3;
      bi_d  <= bi;
      bi_d2 <= bi_d;
      bi_d3 <= bi_d2;
      bi_d4 <= bi_d3;
    end



  always @(posedge clk)
    if (reset) begin
      common_add <= 0;
      common_mult <= 0;
      common <= 0;
    end else if (en) begin
      common_add <= ar_d - ai_d;
      common_mult <= common_add * bi_d2;
      common <= common_mult;
    end


  always @(posedge clk)
    if (reset) begin
      pr_add <= 0;
      pr_mult <= 0;
      pr_ppln <= 0;
      common_d_1 <= 0;
    end else if (en) begin
      pr_add <= br_d3 - bi_d3;
      pr_mult <= pr_add * ar_d4;
      common_d_1 <= common;
      pr_ppln <= pr_mult + common_d_1;
    end


  always @(posedge clk)
    if (reset) begin
      pi_add <= 0;
      pi_mult <= 0;
      pi_ppln <= 0;
      common_d_2 <= 0;
    end else if (en) begin
      pi_add <= br_d3 + bi_d3;
      pi_mult <= pi_add * ai_d4;
      common_d_2 <= common;
      pi_ppln <= pi_mult + common_d_2;
    end

  assign pr = pr_ppln;
  assign pi = pi_ppln;
endmodule
module ComplexMult 
  #( 
    parameter INWIDTH = 16 
  )
  (
    input clk, reset, en,
    input signed [INWIDTH-1:0]    ar, ai, br, bi,
    output signed [2*INWIDTH:0]   pr, pi
  );


  reg signed [INWIDTH-1:0] ar_d, ar_d2, ar_d3, ar_d4;
  reg signed [INWIDTH-1:0] ai_d, ai_d2, ai_d3, ai_d4;
  reg signed [INWIDTH-1:0] br_d, br_d2, br_d3, br_d4;
  reg signed [INWIDTH-1:0] bi_d, bi_d2, bi_d3, bi_d4;
  reg signed [INWIDTH:0]   common_add;
  reg signed [2*INWIDTH:0] common_mult, common, common_d_1, common_d_2;
  reg signed [INWIDTH:0] pr_add, pi_add;
  reg signed [2*INWIDTH:0] pr_mult, pi_mult, pr_ppln, pi_ppln;

  always @(posedge clk)
    if (reset) begin
      ar_d  <= 0;
      ar_d2 <= 0;
      ar_d3 <= 0;
      ar_d4 <= 0;
      ai_d  <= 0;
      ai_d2 <= 0;
      ai_d3 <= 0;
      ai_d4 <= 0;
      br_d  <= 0;
      br_d2 <= 0;
      br_d3 <= 0;
      br_d4 <= 0;
      bi_d  <= 0;
      bi_d2 <= 0;
      bi_d3 <= 0;
      bi_d4 <= 0;
    end else if (en) begin
      ar_d  <= ar;
      ar_d2 <= ar_d;
      ar_d3 <= ar_d2;
      ar_d4 <= ar_d3;
      ai_d  <= ai;
      ai_d2 <= ai_d;
      ai_d3 <= ai_d2;
      ai_d4 <= ai_d3;
      br_d  <= br;
      br_d2 <= br_d;
      br_d3 <= br_d2;
      br_d4 <= br_d3;
      bi_d  <= bi;
      bi_d2 <= bi_d;
      bi_d3 <= bi_d2;
      bi_d4 <= bi_d3;
    end



  always @(posedge clk)
    if (reset) begin
      common_add <= 0;
      common_mult <= 0;
      common <= 0;
    end else if (en) begin
      common_add <= ar_d - ai_d;
      common_mult <= common_add * bi_d2;
      common <= common_mult;
    end


  always @(posedge clk)
    if (reset) begin
      pr_add <= 0;
      pr_mult <= 0;
      pr_ppln <= 0;
      common_d_1 <= 0;
    end else if (en) begin
      pr_add <= br_d3 - bi_d3;
      pr_mult <= pr_add * ar_d4;
      common_d_1 <= common;
      pr_ppln <= pr_mult + common_d_1;
    end


  always @(posedge clk)
    if (reset) begin
      pi_add <= 0;
      pi_mult <= 0;
      pi_ppln <= 0;
      common_d_2 <= 0;
    end else if (en) begin
      pi_add <= br_d3 + bi_d3;
      pi_mult <= pi_add * ai_d4;
      common_d_2 <= common;
      pi_ppln <= pi_mult + common_d_2;
    end

  assign pr = pr_ppln;
  assign pi = pi_ppln;
endmodule