data/full_repos/permissive/436253691/hardware/rtl/RAM_SIM.sv
1: b"%Error: data/full_repos/permissive/436253691/hardware/rtl/RAM_SIM.sv:23: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'IFPATH'\n                                                                       : ... In instance RAM_SIM\nmodule RAM_SIM #(parameter DATA_WIDTH = 32, MEM_SIZE=1024  ,ADDR_WIDTH = 10, string IFPATH [0:100], string OFPATH [0:100])\n                                                                                    ^~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/rtl/RAM_SIM.sv:23: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'OFPATH'\n                                                                       : ... In instance RAM_SIM\nmodule RAM_SIM #(parameter DATA_WIDTH = 32, MEM_SIZE=1024  ,ADDR_WIDTH = 10, string IFPATH [0:100], string OFPATH [0:100])\n                                                                                                           ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module RAM_SIM #(parameter DATA_WIDTH = 32, MEM_SIZE=1024  ,ADDR_WIDTH = 10, string IFPATH [0:100], string OFPATH [0:100])
(

RAM_SIM_Clk,
RAM_SIM_We,
RAM_SIM_Oe,
RAM_SIM_Save,
RAM_SIM_Final_Addr,
RAM_SIM_Load,
RAM_SIM_Counter,
RAM_SIM_Address, 
RAM_SIM_Data_In,

RAM_SIM_Data_Out
);






input RAM_SIM_Clk;
input RAM_SIM_We;
input RAM_SIM_Oe;
input RAM_SIM_Save;
input [31:0] RAM_SIM_Final_Addr;
input RAM_SIM_Load;
input [7:0] RAM_SIM_Counter;
input [ADDR_WIDTH-1:0] RAM_SIM_Address;
input [DATA_WIDTH-1:0] RAM_SIM_Data_In;
output [DATA_WIDTH-1:0] RAM_SIM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [DATA_WIDTH-1:0] Q_temp;




always@(RAM_SIM_Save,RAM_SIM_Load)
begin

	if(RAM_SIM_Load)
		begin
			$readmemh(IFPATH[RAM_SIM_Counter],Ram_Array);
		end
	
	else if(RAM_SIM_Save)
		begin
			$writememh(OFPATH[RAM_SIM_Counter],Ram_Array,9,RAM_SIM_Final_Addr);
		end
end






always@(posedge RAM_SIM_Clk)
begin
	
	if(RAM_SIM_We) begin
		Ram_Array[RAM_SIM_Address]<=RAM_SIM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_SIM_Address];
	
end





assign RAM_SIM_Data_Out = RAM_SIM_Oe == 1'b1 ? Q_temp : 'hz;



endmodule
module RAM_SIM #(parameter DATA_WIDTH = 32, MEM_SIZE=1024  ,ADDR_WIDTH = 10, string IFPATH [0:100], string OFPATH [0:100])
(

RAM_SIM_Clk,
RAM_SIM_We,
RAM_SIM_Oe,
RAM_SIM_Save,
RAM_SIM_Final_Addr,
RAM_SIM_Load,
RAM_SIM_Counter,
RAM_SIM_Address, 
RAM_SIM_Data_In,

RAM_SIM_Data_Out
);







input RAM_SIM_Clk;
input RAM_SIM_We;
input RAM_SIM_Oe;
input RAM_SIM_Save;
input [31:0] RAM_SIM_Final_Addr;
input RAM_SIM_Load;
input [7:0] RAM_SIM_Counter;
input [ADDR_WIDTH-1:0] RAM_SIM_Address;
input [DATA_WIDTH-1:0] RAM_SIM_Data_In;
output [DATA_WIDTH-1:0] RAM_SIM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [DATA_WIDTH-1:0] Q_temp;




always@(RAM_SIM_Save,RAM_SIM_Load)
begin

	if(RAM_SIM_Load)
		begin
			$readmemh(IFPATH[RAM_SIM_Counter],Ram_Array);
		end
	
	else if(RAM_SIM_Save)
		begin
			$writememh(OFPATH[RAM_SIM_Counter],Ram_Array,9,RAM_SIM_Final_Addr);
		end
end






always@(posedge RAM_SIM_Clk)
begin
	
	if(RAM_SIM_We) begin
		Ram_Array[RAM_SIM_Address]<=RAM_SIM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_SIM_Address];
	
end





assign RAM_SIM_Data_Out = RAM_SIM_Oe == 1'b1 ? Q_temp : 'hz;



endmodule