data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src/andgate4.v
data/verilator_xmls/c5ed203f-a618-466e-8795-22d1ea2e29d4.xml
module andgate4 
        (
    input in0,
    input in1,
    input in2,
    input in3,
    output out1
    );

    assign out1 = in0 & in1 & in2 & in3;
endmodule
module andgate4 
        (
    input in0,
    input in1,
    input in2,
    input in3,
    output out1
    );


    assign out1 = in0 & in1 & in2 & in3;
endmodule