data/full_repos/permissive/427221126/src/ConvLayer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ConvLayer.v:459: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ConvLayer\'\nmodule ConvLayer\n       ^~~~~~~~~\n                                                                           : ... Top module \'ConvCore_nC\'\nmodule ConvCore_nC\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:129: Operator ASSIGNDLY expects 41 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n      psum[0] <= mul[0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:140: Operator ADD expects 41 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n          psum[ii] <= mul[ii] + psum[ii-1];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:423: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g] ;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:425: Operator ADD expects 48 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g]  + psum[g-1];\n                                          ^\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:243: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.sv\n             ShiftRegSIPOnB\n             ShiftRegSIPOnB.v\n             ShiftRegSIPOnB.sv\n             obj_dir/ShiftRegSIPOnB\n             obj_dir/ShiftRegSIPOnB.v\n             obj_dir/ShiftRegSIPOnB.sv\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:255: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:290: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:623: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:639: Cannot find file containing module: \'FIFOsync\'\n  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:651: Cannot find file containing module: \'FIFOpi\'\n  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (\n  ^~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module ConvCore_nC
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10,
              NUM_CHANNELS = 20
  )
  (
    input                         clk       ,
    input                         reset     ,
    input                         en        ,
    input   signed [INWIDTH-1:0]  din0      ,
    input                         din0_valid,
    input   signed [INWIDTH-1:0]  din1      ,
    input                         din1_valid,
    input                         sum_en    ,
    output  signed [INWIDTH-1:0]  dout      ,
    output                        dout_valid 
  );
  wire  signed  [47:0]  cas_dout;
  wire                  cas_ready;
  wire                  cas_dout_vld;
  genvar g;
  
  wire         [NUM_CHANNELS-1:0] vd_din1_valid;
  wire signed       [INWIDTH-1:0] vd9_dout_wire   [0:NUM_CHANNELS-1];
  reg  signed       [INWIDTH-1:0] vd9_dout_buffer [0:NUM_CHANNELS-1];
  wire [INWIDTH*NUM_CHANNELS-1:0] vd_dout;
  wire         [NUM_CHANNELS-1:0] vd_dout_vld_wire;
  reg          [NUM_CHANNELS-1:0] vd9_dout_vld;
  wire [INWIDTH*NUM_CHANNELS-1:0] vd9_dout_wire_flat;
  
  wire signed [INWIDTH-1:0] round_dout;
  wire        [INWIDTH-1:0] fifo_cas_dout;
  wire        [INWIDTH-1:0] fifopi_dout;
  wire  fifo_cas_write;
  wire  fifo_cas_read ;
  wire  fifo_cas_empty;
  wire  fifo_cas_full ;

  wire fifopi_writing ;
  wire fifopi_read    ;
  wire fifopi_empty   ;
  wire fifopi_full    ;

  reg  [$clog2(NUM_CHANNELS)-1:0] vd9_counter, cas_counter;
  reg  [3:0]                      din1_counter;
  wire d1c_wrap, vd9c_wrap, vd9_counter_pulse;
  wire cas_counter_pulse;
  wire cas_counter_wrap;
  wire cas_idle;
  reg  [3:1] cas_dout_vld_d;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      din1_counter <= 0;
    end
    else if (en) begin
      if (din1_valid) begin
        if (!d1c_wrap)  din1_counter <= din1_counter + 1;
        else            din1_counter <= 0;
      end
    end
  end

  assign d1c_wrap = (din1_counter == 4'd8);
  assign vd9_counter_pulse = d1c_wrap && din1_valid;
  assign vd9c_wrap = (vd9_counter == (NUM_CHANNELS-1));

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      vd9_counter <= 0;
    end
    else if (en) begin
      if (vd9_counter_pulse) begin
        if (!vd9c_wrap) vd9_counter <= vd9_counter + 1;
        else            vd9_counter <= 0;
      end
    end
  end

  assign cas_counter_pulse = !cas_idle || vd9_dout_vld[NUM_CHANNELS-1];

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      cas_counter <= 0;
    end
    else if (en && sum_en) begin
      if (cas_counter_pulse) begin
        if (!cas_counter_wrap)  cas_counter <= cas_counter + 1;
        else                    cas_counter <= 0;
      end
    end
  end
  assign cas_counter_wrap = (cas_counter == (NUM_CHANNELS-1));
  assign cas_idle = (sum_en == 1'b1) ? (cas_counter == 0) : 1'b1;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      vd9_dout_vld <= 0;
    end
    else if (en) begin
      vd9_dout_vld <= vd_dout_vld_wire;
    end
  end

  assign fifo_cas_write = cas_dout_vld_d[3];
  assign fifo_cas_read = 1'b1;
  assign fifopi_read = 1'b1;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      cas_dout_vld_d <= 0;
    end
    else if (en && sum_en) begin
      cas_dout_vld_d <= {cas_dout_vld_d[3-1:1], cas_dout_vld};
    end
  end

  assign dout_valid = (sum_en == 1'b1) ? !fifo_cas_empty : !fifopi_empty;
  assign dout = $signed((sum_en == 1'b1) ? fifo_cas_dout : fifopi_dout);

  generate
    for (g = 0; g < NUM_CHANNELS; g = g + 1) begin : vecdots
      assign vd_din1_valid[g] = (vd9_counter  == g) && din1_valid;

      Vecdot9 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_vd9 (
        .clk(clk), .reset(reset), .en(en),
        .xin       ( din0                 ),
        .xin_valid ( din0_valid           ),
        .hin       ( din1                 ),
        .hin_valid ( vd_din1_valid[g]     ),
        .dout      ( vd9_dout_wire[g]     ),
        .dout_valid( vd_dout_vld_wire[g]  ) 
      );

      always @(posedge clk) begin
        if (reset == 1'b1) begin
          vd9_dout_buffer[g] <= 0;
        end
        else if (en) begin
          if (vd_dout_vld_wire[g] && cas_idle) begin
            vd9_dout_buffer[g] <= vd9_dout_wire[g];
          end
        end
      end

      assign vd_dout[(g+1)*INWIDTH-1:g*INWIDTH] = vd9_dout_buffer[g];
      assign vd9_dout_wire_flat[(g+1)*INWIDTH-1:g*INWIDTH] = vd9_dout_wire[g];
    end
  endgenerate

  CasAdder #(.INWIDTH(INWIDTH), .CHAIN_LEN(NUM_CHANNELS)) U_casadd (
    .clk       ( clk                          ),
    .reset     ( reset                        ),
    .en        ( en && sum_en                 ),
    .din       ( vd_dout                      ),
    .din_ready ( cas_ready                    ),
    .din_valid ( vd9_dout_vld[NUM_CHANNELS-1] ),
    .scale     ( 16'sh0001                    ),
    .scl_valid ( 1'b1                         ),
    .dout      ( cas_dout                     ),
    .dout_valid( cas_dout_vld                 ) 
  );

  FRound #(
    .INWIDTH ( 48     +1  ),
    .IN_FRAC ( IN_FRAC+1  ),
    .OUTWIDTH( INWIDTH    ),
    .OUT_FRAC( IN_FRAC    ) 
  ) U_round (
    .CLK  ( clk               ),
    .RESET( reset             ),
    .EN   ( en && sum_en      ),
    .DIN  ( {cas_dout, 1'b0}  ),
    .DOUT ( round_dout        ),
    .SATUR(                   ),
    .OVFL (                   ),
    .UDFL (                   ) 
  );

  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (
    .CLK  ( clk             ),
    .RESET( reset           ),
    .EN   ( en && sum_en    ),
    .DI   ( round_dout      ),
    .WRITE( fifo_cas_write  ),
    .DO   ( fifo_cas_dout   ),
    .READ ( fifo_cas_read   ),
    .FULL ( fifo_cas_full   ),
    .EMPTY( fifo_cas_empty  )
  );

  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (
    .CLK    ( clk                               ),
    .RESET  ( reset                             ),
    .EN     ( en && !sum_en                     ),
    .DI     ( vd9_dout_wire_flat                ),
    .WRITE  ( vd_dout_vld_wire[NUM_CHANNELS-1]  ),
    .WRITING( fifopi_writing                    ),
    .DO     ( fifopi_dout                       ),
    .READ   ( fifopi_read                       ),
    .EMPTY  ( fifopi_empty                      ),
    .FULL   ( fifopi_full                       ) 
  );
endmodule
module ConvCore_nC
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10,
              NUM_CHANNELS = 20
  )
  (
    input                         clk       ,
    input                         reset     ,
    input                         en        ,
    input   signed [INWIDTH-1:0]  din0      ,
    input                         din0_valid,
    input   signed [INWIDTH-1:0]  din1      ,
    input                         din1_valid,
    input                         sum_en    ,
    output  signed [INWIDTH-1:0]  dout      ,
    output                        dout_valid 
  );

  wire  signed  [47:0]  cas_dout;
  wire                  cas_ready;
  wire                  cas_dout_vld;
  genvar g;
  
  wire         [NUM_CHANNELS-1:0] vd_din1_valid;
  wire signed       [INWIDTH-1:0] vd9_dout_wire   [0:NUM_CHANNELS-1];
  reg  signed       [INWIDTH-1:0] vd9_dout_buffer [0:NUM_CHANNELS-1];
  wire [INWIDTH*NUM_CHANNELS-1:0] vd_dout;
  wire         [NUM_CHANNELS-1:0] vd_dout_vld_wire;
  reg          [NUM_CHANNELS-1:0] vd9_dout_vld;
  wire [INWIDTH*NUM_CHANNELS-1:0] vd9_dout_wire_flat;
  
  wire signed [INWIDTH-1:0] round_dout;
  wire        [INWIDTH-1:0] fifo_cas_dout;
  wire        [INWIDTH-1:0] fifopi_dout;
  wire  fifo_cas_write;
  wire  fifo_cas_read ;
  wire  fifo_cas_empty;
  wire  fifo_cas_full ;

  wire fifopi_writing ;
  wire fifopi_read    ;
  wire fifopi_empty   ;
  wire fifopi_full    ;

  reg  [$clog2(NUM_CHANNELS)-1:0] vd9_counter, cas_counter;
  reg  [3:0]                      din1_counter;
  wire d1c_wrap, vd9c_wrap, vd9_counter_pulse;
  wire cas_counter_pulse;
  wire cas_counter_wrap;
  wire cas_idle;
  reg  [3:1] cas_dout_vld_d;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      din1_counter <= 0;
    end
    else if (en) begin
      if (din1_valid) begin
        if (!d1c_wrap)  din1_counter <= din1_counter + 1;
        else            din1_counter <= 0;
      end
    end
  end

  assign d1c_wrap = (din1_counter == 4'd8);
  assign vd9_counter_pulse = d1c_wrap && din1_valid;
  assign vd9c_wrap = (vd9_counter == (NUM_CHANNELS-1));

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      vd9_counter <= 0;
    end
    else if (en) begin
      if (vd9_counter_pulse) begin
        if (!vd9c_wrap) vd9_counter <= vd9_counter + 1;
        else            vd9_counter <= 0;
      end
    end
  end

  assign cas_counter_pulse = !cas_idle || vd9_dout_vld[NUM_CHANNELS-1];

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      cas_counter <= 0;
    end
    else if (en && sum_en) begin
      if (cas_counter_pulse) begin
        if (!cas_counter_wrap)  cas_counter <= cas_counter + 1;
        else                    cas_counter <= 0;
      end
    end
  end
  assign cas_counter_wrap = (cas_counter == (NUM_CHANNELS-1));
  assign cas_idle = (sum_en == 1'b1) ? (cas_counter == 0) : 1'b1;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      vd9_dout_vld <= 0;
    end
    else if (en) begin
      vd9_dout_vld <= vd_dout_vld_wire;
    end
  end

  assign fifo_cas_write = cas_dout_vld_d[3];
  assign fifo_cas_read = 1'b1;
  assign fifopi_read = 1'b1;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      cas_dout_vld_d <= 0;
    end
    else if (en && sum_en) begin
      cas_dout_vld_d <= {cas_dout_vld_d[3-1:1], cas_dout_vld};
    end
  end

  assign dout_valid = (sum_en == 1'b1) ? !fifo_cas_empty : !fifopi_empty;
  assign dout = $signed((sum_en == 1'b1) ? fifo_cas_dout : fifopi_dout);

  generate
    for (g = 0; g < NUM_CHANNELS; g = g + 1) begin : vecdots
      assign vd_din1_valid[g] = (vd9_counter  == g) && din1_valid;

      Vecdot9 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_vd9 (
        .clk(clk), .reset(reset), .en(en),
        .xin       ( din0                 ),
        .xin_valid ( din0_valid           ),
        .hin       ( din1                 ),
        .hin_valid ( vd_din1_valid[g]     ),
        .dout      ( vd9_dout_wire[g]     ),
        .dout_valid( vd_dout_vld_wire[g]  ) 
      );

      always @(posedge clk) begin
        if (reset == 1'b1) begin
          vd9_dout_buffer[g] <= 0;
        end
        else if (en) begin
          if (vd_dout_vld_wire[g] && cas_idle) begin
            vd9_dout_buffer[g] <= vd9_dout_wire[g];
          end
        end
      end

      assign vd_dout[(g+1)*INWIDTH-1:g*INWIDTH] = vd9_dout_buffer[g];
      assign vd9_dout_wire_flat[(g+1)*INWIDTH-1:g*INWIDTH] = vd9_dout_wire[g];
    end
  endgenerate

  CasAdder #(.INWIDTH(INWIDTH), .CHAIN_LEN(NUM_CHANNELS)) U_casadd (
    .clk       ( clk                          ),
    .reset     ( reset                        ),
    .en        ( en && sum_en                 ),
    .din       ( vd_dout                      ),
    .din_ready ( cas_ready                    ),
    .din_valid ( vd9_dout_vld[NUM_CHANNELS-1] ),
    .scale     ( 16'sh0001                    ),
    .scl_valid ( 1'b1                         ),
    .dout      ( cas_dout                     ),
    .dout_valid( cas_dout_vld                 ) 
  );

  FRound #(
    .INWIDTH ( 48     +1  ),
    .IN_FRAC ( IN_FRAC+1  ),
    .OUTWIDTH( INWIDTH    ),
    .OUT_FRAC( IN_FRAC    ) 
  ) U_round (
    .CLK  ( clk               ),
    .RESET( reset             ),
    .EN   ( en && sum_en      ),
    .DIN  ( {cas_dout, 1'b0}  ),
    .DOUT ( round_dout        ),
    .SATUR(                   ),
    .OVFL (                   ),
    .UDFL (                   ) 
  );

  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (
    .CLK  ( clk             ),
    .RESET( reset           ),
    .EN   ( en && sum_en    ),
    .DI   ( round_dout      ),
    .WRITE( fifo_cas_write  ),
    .DO   ( fifo_cas_dout   ),
    .READ ( fifo_cas_read   ),
    .FULL ( fifo_cas_full   ),
    .EMPTY( fifo_cas_empty  )
  );

  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (
    .CLK    ( clk                               ),
    .RESET  ( reset                             ),
    .EN     ( en && !sum_en                     ),
    .DI     ( vd9_dout_wire_flat                ),
    .WRITE  ( vd_dout_vld_wire[NUM_CHANNELS-1]  ),
    .WRITING( fifopi_writing                    ),
    .DO     ( fifopi_dout                       ),
    .READ   ( fifopi_read                       ),
    .EMPTY  ( fifopi_empty                      ),
    .FULL   ( fifopi_full                       ) 
  );
endmodule