data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v
1: b'%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Redefining existing define: \'M_W\', with different value: 8\n                     ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.\n%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Previous definition is here, with value: 4\n%Warning-PINMISSING: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:379: Cell has missing pin: \'RST\'\nmb24 b_mult(\n     ^~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:499: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.sv\n             HALF_ADDER\n             HALF_ADDER.v\n             HALF_ADDER.sv\n             obj_dir/HALF_ADDER\n             obj_dir/HALF_ADDER.v\n             obj_dir/HALF_ADDER.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:500: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:501: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:505: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:509: Cannot find file containing module: \'FULL_ADDER\'\n                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n                 ^~\n%Warning-LITENDIAN: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:43: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg [0:HPE-1]D_SHIFTEN;\n    ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module sa_booth3_encoder (x, single, double, triple, quad, neg);

input [3:0]x;

output single;

output  double;

output triple;

output  quad;

output neg;

wire w0;

wire w1;

wire w2;

wire w3;

wire w4;

wire w5;

assign neg=x[3];

assign w0=x[0]^x[1];

assign w1=x[1]^x[2];

assign w2=x[2]^x[3];

assign single=~((~w0)|w2);

assign double=~((~w1)|w0);

assign triple=~((~w2)|(~w0));

assign quad=~((~w2)|(w0|w1));

endmodule
module sa_booth3_encoder (x, single, double, triple, quad, neg);


input [3:0]x;

output single;

output  double;

output triple;

output  quad;

output neg;

wire w0;

wire w1;

wire w2;

wire w3;

wire w4;

wire w5;

assign neg=x[3];

assign w0=x[0]^x[1];

assign w1=x[1]^x[2];

assign w2=x[2]^x[3];

assign single=~((~w0)|w2);

assign double=~((~w1)|w0);

assign triple=~((~w2)|(~w0));

assign quad=~((~w2)|(w0|w1));

endmodule