data/full_repos/permissive/443520440/code/seg7_driver.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/443520440/code/seg7_driver.v:65: Cell has missing pin: \'rst\'\n    Divider display_div(.I_CLK(clk), .O_CLK(display_clk));\n            ^~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module trans7(
    input [3:0] 	iData	,
    output [7:0] 	oData
    );
    wire [15:0] 	num		;
	wire a,b,c,d,e,f,g,dp;
    assign num[0] = (~iData[3] & ~iData[2] & ~iData[1] & ~iData[0]);
    assign num[1] = (~iData[3] & ~iData[2] & ~iData[1] & iData[0]);
    assign num[2] = (~iData[3] & ~iData[2] & iData[1] & ~iData[0]);
    assign num[3] = (~iData[3] & ~iData[2] & iData[1] & iData[0]);
    assign num[4] = (~iData[3] & iData[2] & ~iData[1] & ~iData[0]);
    assign num[5] = (~iData[3] & iData[2] & ~iData[1] & iData[0]);
    assign num[6] = (~iData[3] & iData[2] & iData[1] & ~iData[0]);
    assign num[7] = (~iData[3] & iData[2] & iData[1] & iData[0]);
    assign num[8] = (iData[3] & ~iData[2] & ~iData[1] & ~iData[0]);
    assign num[9] = (iData[3] & ~iData[2] & ~iData[1] & iData[0]);
	assign num[10] = (iData[3] & ~iData[2] & iData[1] & ~iData[0]);
	assign num[11] = (iData[3] & ~iData[2] & iData[1] & iData[0]);
	assign num[12] = (iData[3] & iData[2] & ~iData[1] & ~iData[0]);
	assign num[13] = (iData[3] & iData[2] & ~iData[1] & iData[0]);
	assign num[14] = (iData[3] & iData[2] & iData[1] & ~iData[0]);
	assign num[15] = (iData[3] & iData[2] & iData[1] & iData[0]);
    assign a = num[1] | num[4] | num[11] | num[13];
    assign b = num[5] | num[6] | num[11] | num[12] | num[14] | num[15];
    assign c = num[2] | num[12] | num[14] | num[15];
    assign d = num[1] | num[4] | num[7] | num[10] | num[15];
    assign e = num[1] | num[3] | num[4] | num[5] | num[7] | num[9];
    assign f = num[1] | num[2] | num[3] | num[7] | num[13];
    assign g = num[0] | num[1] | num[7] | num[12];
	assign dp = num[0] | num[1]| num[2]| num[3]| num[4]| num[5]| num[6]| num[7]| num[8]| num[9];
    assign oData = {dp,g,f,e,d,c,b,a};
endmodule
module trans7(
    input [3:0] 	iData	,
    output [7:0] 	oData
    );

    wire [15:0] 	num		;
	wire a,b,c,d,e,f,g,dp;
    assign num[0] = (~iData[3] & ~iData[2] & ~iData[1] & ~iData[0]);
    assign num[1] = (~iData[3] & ~iData[2] & ~iData[1] & iData[0]);
    assign num[2] = (~iData[3] & ~iData[2] & iData[1] & ~iData[0]);
    assign num[3] = (~iData[3] & ~iData[2] & iData[1] & iData[0]);
    assign num[4] = (~iData[3] & iData[2] & ~iData[1] & ~iData[0]);
    assign num[5] = (~iData[3] & iData[2] & ~iData[1] & iData[0]);
    assign num[6] = (~iData[3] & iData[2] & iData[1] & ~iData[0]);
    assign num[7] = (~iData[3] & iData[2] & iData[1] & iData[0]);
    assign num[8] = (iData[3] & ~iData[2] & ~iData[1] & ~iData[0]);
    assign num[9] = (iData[3] & ~iData[2] & ~iData[1] & iData[0]);
	assign num[10] = (iData[3] & ~iData[2] & iData[1] & ~iData[0]);
	assign num[11] = (iData[3] & ~iData[2] & iData[1] & iData[0]);
	assign num[12] = (iData[3] & iData[2] & ~iData[1] & ~iData[0]);
	assign num[13] = (iData[3] & iData[2] & ~iData[1] & iData[0]);
	assign num[14] = (iData[3] & iData[2] & iData[1] & ~iData[0]);
	assign num[15] = (iData[3] & iData[2] & iData[1] & iData[0]);
    assign a = num[1] | num[4] | num[11] | num[13];
    assign b = num[5] | num[6] | num[11] | num[12] | num[14] | num[15];
    assign c = num[2] | num[12] | num[14] | num[15];
    assign d = num[1] | num[4] | num[7] | num[10] | num[15];
    assign e = num[1] | num[3] | num[4] | num[5] | num[7] | num[9];
    assign f = num[1] | num[2] | num[3] | num[7] | num[13];
    assign g = num[0] | num[1] | num[7] | num[12];
	assign dp = num[0] | num[1]| num[2]| num[3]| num[4]| num[5]| num[6]| num[7]| num[8]| num[9];
    assign oData = {dp,g,f,e,d,c,b,a};
endmodule