data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/program_counter.v
data/verilator_xmls/9e57c7d2-f01e-448e-a4ae-d12b576eae42.xml
module program_counter(
    input clk,
    input [31:0] nextPc,
    output reg [31:0] pc
    ); 

    always @(posedge clk) begin
        pc <= nextPc;
    end
endmodule
module program_counter(
    input clk,
    input [31:0] nextPc,
    output reg [31:0] pc
    );
 

    always @(posedge clk) begin
        pc <= nextPc;
    end
endmodule