data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v
1: b'%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:43: Cannot find include file: ../../lib/n64adv_vparams.vh\n`include "../../lib/n64adv_vparams.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423107324/rtl/ppu,data/full_repos/permissive/423107324/../../lib/n64adv_vparams.vh\n             data/full_repos/permissive/423107324/rtl/ppu,data/full_repos/permissive/423107324/../../lib/n64adv_vparams.vh.v\n             data/full_repos/permissive/423107324/rtl/ppu,data/full_repos/permissive/423107324/../../lib/n64adv_vparams.vh.sv\n             ../../lib/n64adv_vparams.vh\n             ../../lib/n64adv_vparams.vh.v\n             ../../lib/n64adv_vparams.vh.sv\n             obj_dir/../../lib/n64adv_vparams.vh\n             obj_dir/../../lib/n64adv_vparams.vh.v\n             obj_dir/../../lib/n64adv_vparams.vh.sv\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:44: Cannot find include file: ../../lib/n64adv_ppuconfig.vh\n`include "../../lib/n64adv_ppuconfig.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:52: Define or directive not defined: \'`VDATA_I_FU_SLICE\'\ninput [`VDATA_I_FU_SLICE] vdata_i;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\ninput [`VDATA_I_FU_SLICE] vdata_i;\n                        ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:54: Define or directive not defined: \'`VDATA_I_FU_SLICE\'\noutput reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1\'b0}};\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\noutput reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1\'b0}};\n                             ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:58: Define or directive not defined: \'`GAMMA_TABLE_OFF\'\nwire       en_gamma_boost     = ~(gammaparams_i == `GAMMA_TABLE_OFF);\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire       en_gamma_boost     = ~(gammaparams_i == `GAMMA_TABLE_OFF);\n                                                                   ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:59: Define or directive not defined: \'`GAMMA_TABLE_OFF\'\nwire [3:0] gamma_rom_page_tmp =  (gammaparams_i < `GAMMA_TABLE_OFF) ? gammaparams_i       :\n                                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire [3:0] gamma_rom_page_tmp =  (gammaparams_i < `GAMMA_TABLE_OFF) ? gammaparams_i       :\n                                                                  ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:65: Define or directive not defined: \'`VDATA_I_CO_SLICE\'\nwire [`VDATA_I_CO_SLICE] gamma_vdata_out;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`VDATA_I_CO_SLICE] gamma_vdata_out;\n                       ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:78: Define or directive not defined: \'`VDATA_I_RE_SLICE\'\n      gamma_vdata_i <= vdata_i[`VDATA_I_RE_SLICE];\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      gamma_vdata_i <= vdata_i[`VDATA_I_RE_SLICE];\n                                                ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:81: Define or directive not defined: \'`VDATA_I_GR_SLICE\'\n        gamma_vdata_i <= vdata_i[`VDATA_I_GR_SLICE];\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:81: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        gamma_vdata_i <= vdata_i[`VDATA_I_GR_SLICE];\n                                                  ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:83: Define or directive not defined: \'`VDATA_I_BL_SLICE\'\n        gamma_vdata_i <= vdata_i[`VDATA_I_BL_SLICE];\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        gamma_vdata_i <= vdata_i[`VDATA_I_BL_SLICE];\n                                                  ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:121: Define or directive not defined: \'`VDATA_I_SY_SLICE\'\n    vdata_sync_L[0] <= vdata_i[`VDATA_I_SY_SLICE];\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    vdata_sync_L[0] <= vdata_i[`VDATA_I_SY_SLICE];\n                                                ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:126: Define or directive not defined: \'`VDATA_I_FU_SLICE\'\nreg [`VDATA_I_FU_SLICE] vdata_o_pre = {vdata_width_i{1\'b0}};\n     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`VDATA_I_FU_SLICE] vdata_o_pre = {vdata_width_i{1\'b0}};\n                      ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:135: Define or directive not defined: \'`VDATA_I_SY_SLICE\'\n      vdata_o_pre[`VDATA_I_SY_SLICE] <= vdata_sync_L[2];\n                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:135: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      vdata_o_pre[`VDATA_I_SY_SLICE] <= vdata_sync_L[2];\n                                   ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:136: Define or directive not defined: \'`VDATA_I_RE_SLICE\'\n      vdata_o_pre[`VDATA_I_RE_SLICE] <= gamma_vdata_o;\n                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:136: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      vdata_o_pre[`VDATA_I_RE_SLICE] <= gamma_vdata_o;\n                                   ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:139: Define or directive not defined: \'`VDATA_I_GR_SLICE\'\n        vdata_o_pre[`VDATA_I_GR_SLICE] <= gamma_vdata_o;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:139: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        vdata_o_pre[`VDATA_I_GR_SLICE] <= gamma_vdata_o;\n                                     ^\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:141: Define or directive not defined: \'`VDATA_I_BL_SLICE\'\n        vdata_o_pre[`VDATA_I_BL_SLICE] <= gamma_vdata_o;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423107324/rtl/ppu/gamma_module.v:141: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        vdata_o_pre[`VDATA_I_BL_SLICE] <= gamma_vdata_o;\n                                     ^\n%Error: Exiting due to 30 error(s)\n'
module gamma_module(
  VCLK,
  nRST,
  gammaparams_i,
  vdata_valid_i,
  vdata_i,
  vdata_valid_o,
  vdata_o
);

`include "../../lib/n64adv_vparams.vh"
`include "../../lib/n64adv_ppuconfig.vh"

input VCLK;
input nRST;

input [ 3:0] gammaparams_i;

input vdata_valid_i;
input [`VDATA_I_FU_SLICE] vdata_i;
output reg vdata_valid_o;
output reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1'b0}};



wire       en_gamma_boost     = ~(gammaparams_i == `GAMMA_TABLE_OFF);
wire [3:0] gamma_rom_page_tmp =  (gammaparams_i < `GAMMA_TABLE_OFF) ? gammaparams_i       :
                                                                      gammaparams_i - 1'b1;
wire [2:0] gamma_rom_page = gamma_rom_page_tmp[2:0];



wire [`VDATA_I_CO_SLICE] gamma_vdata_out;

reg [1:0] vdata_i_cnt = 2'b00;
reg [color_width_i-1:0] gamma_vdata_i = {color_width_i{1'b0}};
wire [color_width_i-1:0] gamma_vdata_o;

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_i_cnt <= 2'b00;
    gamma_vdata_i <= {color_width_i{1'b0}};
  end else begin
    if (vdata_valid_i) begin
      vdata_i_cnt <= 2'b01;
      gamma_vdata_i <= vdata_i[`VDATA_I_RE_SLICE];
    end else begin
      if (vdata_i_cnt == 2'b01)
        gamma_vdata_i <= vdata_i[`VDATA_I_GR_SLICE];
      if (vdata_i_cnt == 2'b10)
        gamma_vdata_i <= vdata_i[`VDATA_I_BL_SLICE];
      vdata_i_cnt <= vdata_i_cnt + 2'b01;
    end
  end

gamma_table gamma_table_re_u(
  .VCLK(VCLK),
  .nRST(nRST),
  .gamma_val(gamma_rom_page),
  .vdata_in(gamma_vdata_i),
  .nbypass(en_gamma_boost),
  .vdata_out(gamma_vdata_o)
);



reg vdata_valid_L[0:2];
reg [3:0] vdata_sync_L[0:2];
integer int_idx;
initial begin
  for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
    vdata_valid_L[int_idx] = 1'b0;
    vdata_sync_L[int_idx] = 4'h0;
  end
end

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
      vdata_valid_L[int_idx] <= 1'b0;
      vdata_sync_L[int_idx] <= 4'h0;
    end
  end else begin
    vdata_valid_L[2] <= vdata_valid_L[1];
    vdata_valid_L[1] <= vdata_valid_L[0];
    vdata_valid_L[0] <= vdata_valid_i;
    vdata_sync_L[2] <= vdata_sync_L[1];
    vdata_sync_L[1] <= vdata_sync_L[0];
    vdata_sync_L[0] <= vdata_i[`VDATA_I_SY_SLICE];
  end


reg [1:0] vdata_o_cnt = 2'b00;
reg [`VDATA_I_FU_SLICE] vdata_o_pre = {vdata_width_i{1'b0}};

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_o_cnt <= 2'b00;
    vdata_o_pre <= {vdata_width_i{1'b0}};
  end else begin
    if (vdata_valid_L[2]) begin
      vdata_o_cnt <= 2'b01;
      vdata_o_pre[`VDATA_I_SY_SLICE] <= vdata_sync_L[2];
      vdata_o_pre[`VDATA_I_RE_SLICE] <= gamma_vdata_o;
    end else begin
      if (vdata_o_cnt == 2'b01)
        vdata_o_pre[`VDATA_I_GR_SLICE] <= gamma_vdata_o;
      if (vdata_o_cnt == 2'b10)
        vdata_o_pre[`VDATA_I_BL_SLICE] <= gamma_vdata_o;
      vdata_o_cnt <= vdata_o_cnt + 2'b01;
    end
  end


always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_o <= {vdata_width_i{1'b0}};
  end else begin
    vdata_valid_o <= vdata_valid_L[2];
    if (vdata_valid_L[2])
      vdata_o <= vdata_o_pre;
  end

endmodule
module gamma_module(
  VCLK,
  nRST,
  gammaparams_i,
  vdata_valid_i,
  vdata_i,
  vdata_valid_o,
  vdata_o
);


`include "../../lib/n64adv_vparams.vh"
`include "../../lib/n64adv_ppuconfig.vh"

input VCLK;
input nRST;

input [ 3:0] gammaparams_i;

input vdata_valid_i;
input [`VDATA_I_FU_SLICE] vdata_i;
output reg vdata_valid_o;
output reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1'b0}};



wire       en_gamma_boost     = ~(gammaparams_i == `GAMMA_TABLE_OFF);
wire [3:0] gamma_rom_page_tmp =  (gammaparams_i < `GAMMA_TABLE_OFF) ? gammaparams_i       :
                                                                      gammaparams_i - 1'b1;
wire [2:0] gamma_rom_page = gamma_rom_page_tmp[2:0];



wire [`VDATA_I_CO_SLICE] gamma_vdata_out;

reg [1:0] vdata_i_cnt = 2'b00;
reg [color_width_i-1:0] gamma_vdata_i = {color_width_i{1'b0}};
wire [color_width_i-1:0] gamma_vdata_o;

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_i_cnt <= 2'b00;
    gamma_vdata_i <= {color_width_i{1'b0}};
  end else begin
    if (vdata_valid_i) begin
      vdata_i_cnt <= 2'b01;
      gamma_vdata_i <= vdata_i[`VDATA_I_RE_SLICE];
    end else begin
      if (vdata_i_cnt == 2'b01)
        gamma_vdata_i <= vdata_i[`VDATA_I_GR_SLICE];
      if (vdata_i_cnt == 2'b10)
        gamma_vdata_i <= vdata_i[`VDATA_I_BL_SLICE];
      vdata_i_cnt <= vdata_i_cnt + 2'b01;
    end
  end

gamma_table gamma_table_re_u(
  .VCLK(VCLK),
  .nRST(nRST),
  .gamma_val(gamma_rom_page),
  .vdata_in(gamma_vdata_i),
  .nbypass(en_gamma_boost),
  .vdata_out(gamma_vdata_o)
);



reg vdata_valid_L[0:2];
reg [3:0] vdata_sync_L[0:2];
integer int_idx;
initial begin
  for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
    vdata_valid_L[int_idx] = 1'b0;
    vdata_sync_L[int_idx] = 4'h0;
  end
end

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
      vdata_valid_L[int_idx] <= 1'b0;
      vdata_sync_L[int_idx] <= 4'h0;
    end
  end else begin
    vdata_valid_L[2] <= vdata_valid_L[1];
    vdata_valid_L[1] <= vdata_valid_L[0];
    vdata_valid_L[0] <= vdata_valid_i;
    vdata_sync_L[2] <= vdata_sync_L[1];
    vdata_sync_L[1] <= vdata_sync_L[0];
    vdata_sync_L[0] <= vdata_i[`VDATA_I_SY_SLICE];
  end


reg [1:0] vdata_o_cnt = 2'b00;
reg [`VDATA_I_FU_SLICE] vdata_o_pre = {vdata_width_i{1'b0}};

always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_o_cnt <= 2'b00;
    vdata_o_pre <= {vdata_width_i{1'b0}};
  end else begin
    if (vdata_valid_L[2]) begin
      vdata_o_cnt <= 2'b01;
      vdata_o_pre[`VDATA_I_SY_SLICE] <= vdata_sync_L[2];
      vdata_o_pre[`VDATA_I_RE_SLICE] <= gamma_vdata_o;
    end else begin
      if (vdata_o_cnt == 2'b01)
        vdata_o_pre[`VDATA_I_GR_SLICE] <= gamma_vdata_o;
      if (vdata_o_cnt == 2'b10)
        vdata_o_pre[`VDATA_I_BL_SLICE] <= gamma_vdata_o;
      vdata_o_cnt <= vdata_o_cnt + 2'b01;
    end
  end


always @(posedge VCLK or negedge nRST)
  if (!nRST) begin
    vdata_o <= {vdata_width_i{1'b0}};
  end else begin
    vdata_valid_o <= vdata_valid_L[2];
    if (vdata_valid_L[2])
      vdata_o <= vdata_o_pre;
  end

endmodule