data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Bcdadd100/bcd_fadd.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Bcdadd100,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Bcdadd100/bcd_fadd.v\n%Error: Exiting due to 4 error(s)\n'
module bcd_fadd (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire       cin,
    output wire       cout,
    output wire [3:0] sum
);

  reg [4:0] large_sum;
  assign {cout, sum} = large_sum;

  always @(*) begin
    large_sum = cin + a + b;
    if (large_sum > 9) large_sum = large_sum + 6;
  end

endmodule
module bcd_fadd (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire       cin,
    output wire       cout,
    output wire [3:0] sum
);


  reg [4:0] large_sum;
  assign {cout, sum} = large_sum;

  always @(*) begin
    large_sum = cin + a + b;
    if (large_sum > 9) large_sum = large_sum + 6;
  end

endmodule