data/full_repos/permissive/441248555/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/441248555/verilog/rtl/user_proj_example.v:69: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/441248555/verilog/rtl/user_proj_example.v:72: syntax error, unexpected always\n always @(posedge wb_clk_i or posedge wb_rst_i)\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,	
  `endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
 

    output [31:0] wbs_dat_o,



);
    reg [3:0] count1;
    reg [31:0] wbs_dat_o;
 always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
count1<=0;
else begin
if(wb_stb_i)
count1<=count1+1;
else
count1<=count1-1;
end
end

always @(count1)
begin
case(count1)
    4'b0000:wbs_dat_o = 32'b0000001;
	 4'b0001:wbs_dat_o = 32'b1001111;
	 4'b0010:wbs_dat_o = 32'b0010010;
	 4'b0011:wbs_dat_o = 32'b0000110;
	 4'b0100:wbs_dat_o = 32'b1001100;
	 4'b0101:wbs_dat_o = 32'b0100100;
	 4'b0110:wbs_dat_o = 32'b0100000;
	 4'b0111:wbs_dat_o = 32'b0001111;
	 4'b1000:wbs_dat_o = 32'b0000000;
	 4'b1001:wbs_dat_o = 32'b0000100;
	 4'b1010:wbs_dat_o = 32'b0001001;
	 4'b1011:wbs_dat_o = 32'b1100000;
	 4'b1100:wbs_dat_o = 32'b0110001;
	 4'b1101:wbs_dat_o = 32'b0000001;
	 4'b1110:wbs_dat_o = 32'b0110000;
	 4'b1111:wbs_dat_o = 32'b0111000;
	 default:wbs_dat_o = 32'b1111111;
	 endcase
end
endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,	
  `endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
 

    output [31:0] wbs_dat_o,



);

    reg [3:0] count1;
    reg [31:0] wbs_dat_o;
 always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
count1<=0;
else begin
if(wb_stb_i)
count1<=count1+1;
else
count1<=count1-1;
end
end

always @(count1)
begin
case(count1)
    4'b0000:wbs_dat_o = 32'b0000001;
	 4'b0001:wbs_dat_o = 32'b1001111;
	 4'b0010:wbs_dat_o = 32'b0010010;
	 4'b0011:wbs_dat_o = 32'b0000110;
	 4'b0100:wbs_dat_o = 32'b1001100;
	 4'b0101:wbs_dat_o = 32'b0100100;
	 4'b0110:wbs_dat_o = 32'b0100000;
	 4'b0111:wbs_dat_o = 32'b0001111;
	 4'b1000:wbs_dat_o = 32'b0000000;
	 4'b1001:wbs_dat_o = 32'b0000100;
	 4'b1010:wbs_dat_o = 32'b0001001;
	 4'b1011:wbs_dat_o = 32'b1100000;
	 4'b1100:wbs_dat_o = 32'b0110001;
	 4'b1101:wbs_dat_o = 32'b0000001;
	 4'b1110:wbs_dat_o = 32'b0110000;
	 4'b1111:wbs_dat_o = 32'b0111000;
	 default:wbs_dat_o = 32'b1111111;
	 endcase
end
endmodule