data/full_repos/permissive/43858668/final_verilog/src/clib/c_prio_sel.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prio_sel.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module c_prio_sel
  (priorities, enable, select);
   
`include "c_functions.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 16;
   

   localparam prio_width = clogb(num_priorities);
   

   input [0:num_ports*prio_width-1] priorities;
   

   input [0:num_ports-1] 	    enable;
   

   output [0:num_ports-1] 	    select;
   wire [0:num_ports-1] 	    select;
   

   wire [0:prio_width*num_ports-1]  prio_ports;
   c_interleave
     #(.width(num_ports*prio_width),
       .num_blocks(num_ports))
   prio_ports_intl
     (.data_in(priorities),
      .data_out(prio_ports));
   
   wire [0:(prio_width+1)*num_ports-1]  mask;
   
   assign mask[0:num_ports-1] = enable;
   
   generate
      
      genvar 				i;
      
      for(i = 0; i < prio_width; i = i + 1)
	begin:is
	   
	   wire [0:num_ports-1] mask_in;
	   assign mask_in = mask[i*num_ports:(i+1)*num_ports-1];
	   
	   wire [0:num_ports-1] prio;
	   assign prio = prio_ports[i*num_ports:(i+1)*num_ports-1];
	   
	   wire [0:num_ports-1] mask_out;
	   assign mask_out = mask_in & (prio | {num_ports{~|(mask_in & prio)}});
	   
	   assign mask[(i+1)*num_ports:(i+2)*num_ports-1] = mask_out;
	   
	end
      
   endgenerate
   
   assign select = mask[prio_width*num_ports:(prio_width+1)*num_ports-1];
   
endmodule
module c_prio_sel
  (priorities, enable, select);

   
`include "c_functions.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 16;
   

   localparam prio_width = clogb(num_priorities);
   

   input [0:num_ports*prio_width-1] priorities;
   

   input [0:num_ports-1] 	    enable;
   

   output [0:num_ports-1] 	    select;
   wire [0:num_ports-1] 	    select;
   

   wire [0:prio_width*num_ports-1]  prio_ports;
   c_interleave
     #(.width(num_ports*prio_width),
       .num_blocks(num_ports))
   prio_ports_intl
     (.data_in(priorities),
      .data_out(prio_ports));
   
   wire [0:(prio_width+1)*num_ports-1]  mask;
   
   assign mask[0:num_ports-1] = enable;
   
   generate
      
      genvar 				i;
      
      for(i = 0; i < prio_width; i = i + 1)
	begin:is
	   
	   wire [0:num_ports-1] mask_in;
	   assign mask_in = mask[i*num_ports:(i+1)*num_ports-1];
	   
	   wire [0:num_ports-1] prio;
	   assign prio = prio_ports[i*num_ports:(i+1)*num_ports-1];
	   
	   wire [0:num_ports-1] mask_out;
	   assign mask_out = mask_in & (prio | {num_ports{~|(mask_in & prio)}});
	   
	   assign mask[(i+1)*num_ports:(i+2)*num_ports-1] = mask_out;
	   
	end
      
   endgenerate
   
   assign select = mask[prio_width*num_ports:(prio_width+1)*num_ports-1];
   
endmodule