data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pad_functional.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pad_functional.sv:45: Unsupported: Verilog 1995 gate primitive: pmos\n  rpmos  (PAD, PAD_wi, 1'b0);\n         ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pad_functional.sv:82: Unsupported: Verilog 1995 gate primitive: pmos\n  rpmos  (PAD, PAD_wi, 1'b0);\n         ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module pad_functional_pu
(
   input  logic             OEN,
   input  logic             I,
   output logic             O,
   input  logic             PEN,
   inout  logic             PAD
);





  wire   PAD_wi;

  bufif0 (PAD, I, OEN);
  buf    (O, PAD);
  bufif0 (PAD_wi, 1'b1, PEN);
  rpmos  (PAD, PAD_wi, 1'b0);

endmodule
module pad_functional_pu
(
   input  logic             OEN,
   input  logic             I,
   output logic             O,
   input  logic             PEN,
   inout  logic             PAD
);






  wire   PAD_wi;

  bufif0 (PAD, I, OEN);
  buf    (O, PAD);
  bufif0 (PAD_wi, 1'b1, PEN);
  rpmos  (PAD, PAD_wi, 1'b0);

endmodule