data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb_data_array.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb_data_array.v:65: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_btb_data_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb_data_array.v:116: Cannot find file containing module: 'ct_spsram_512x44'\nct_spsram_512x44  x_ct_spsram_512x44_bank0 (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb_data_array.v:137: Cannot find file containing module: 'ct_spsram_512x44'\nct_spsram_512x44  x_ct_spsram_512x44_bank1 (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ct_ifu_btb_data_array(
  btb_data_cen_b,
  btb_data_clk_en,
  btb_data_din,
  btb_data_dout,
  btb_data_wen,
  btb_index,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);


input           btb_data_cen_b;     
input           btb_data_clk_en;    
input   [43:0]  btb_data_din;       
input   [3 :0]  btb_data_wen;       
input   [9 :0]  btb_index;          
input           cp0_ifu_icg_en;     
input           cp0_yy_clk_en;      
input           forever_cpuclk;     
input           pad_yy_icg_scan_en; 
output  [87:0]  btb_data_dout;      




wire    [43:0]  btb_data_bwen_bank0; 
wire    [43:0]  btb_data_bwen_bank1; 
wire            btb_data_cen_b;     
wire            btb_data_clk;       
wire            btb_data_clk_en;    
wire    [43:0]  btb_data_din;       
wire    [87:0]  btb_data_dout;      
wire            btb_data_en;        
wire            btb_data_gwen_bank0; 
wire            btb_data_gwen_bank1; 
wire    [3 :0]  btb_data_wen;       
wire    [9 :0]  btb_index;          
wire            cp0_ifu_icg_en;     
wire            cp0_yy_clk_en;      
wire            forever_cpuclk;     
wire            pad_yy_icg_scan_en; 




gated_clk_cell  x_btb_data_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (btb_data_clk      ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (btb_data_en       ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









assign btb_data_en = btb_data_clk_en;




assign btb_data_bwen_bank0[43:0] = {{22{btb_data_wen[1]}}, {22{btb_data_wen[0]}}};
assign btb_data_gwen_bank0       = btb_data_wen[1] && btb_data_wen[0];
assign btb_data_bwen_bank1[43:0] = {{22{btb_data_wen[3]}}, {22{btb_data_wen[2]}}};
assign btb_data_gwen_bank1       = btb_data_wen[3] && btb_data_wen[2];
























ct_spsram_512x44  x_ct_spsram_512x44_bank0 (
  .A                   (btb_index[8:0]     ),
  .CEN                 (btb_data_cen_b     ),
  .CLK                 (btb_data_clk       ),
  .D                   (btb_data_din       ),
  .GWEN                (btb_data_gwen_bank0),
  .Q                   (btb_data_dout[43:0]),
  .WEN                 (btb_data_bwen_bank0)
);












ct_spsram_512x44  x_ct_spsram_512x44_bank1 (
  .A                    (btb_index[8:0]      ),
  .CEN                  (btb_data_cen_b      ),
  .CLK                  (btb_data_clk        ),
  .D                    (btb_data_din        ),
  .GWEN                 (btb_data_gwen_bank1 ),
  .Q                    (btb_data_dout[87:44]),
  .WEN                  (btb_data_bwen_bank1 )
);














endmodule
module ct_ifu_btb_data_array(
  btb_data_cen_b,
  btb_data_clk_en,
  btb_data_din,
  btb_data_dout,
  btb_data_wen,
  btb_index,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);



input           btb_data_cen_b;     
input           btb_data_clk_en;    
input   [43:0]  btb_data_din;       
input   [3 :0]  btb_data_wen;       
input   [9 :0]  btb_index;          
input           cp0_ifu_icg_en;     
input           cp0_yy_clk_en;      
input           forever_cpuclk;     
input           pad_yy_icg_scan_en; 
output  [87:0]  btb_data_dout;      




wire    [43:0]  btb_data_bwen_bank0; 
wire    [43:0]  btb_data_bwen_bank1; 
wire            btb_data_cen_b;     
wire            btb_data_clk;       
wire            btb_data_clk_en;    
wire    [43:0]  btb_data_din;       
wire    [87:0]  btb_data_dout;      
wire            btb_data_en;        
wire            btb_data_gwen_bank0; 
wire            btb_data_gwen_bank1; 
wire    [3 :0]  btb_data_wen;       
wire    [9 :0]  btb_index;          
wire            cp0_ifu_icg_en;     
wire            cp0_yy_clk_en;      
wire            forever_cpuclk;     
wire            pad_yy_icg_scan_en; 




gated_clk_cell  x_btb_data_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (btb_data_clk      ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (btb_data_en       ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);









assign btb_data_en = btb_data_clk_en;




assign btb_data_bwen_bank0[43:0] = {{22{btb_data_wen[1]}}, {22{btb_data_wen[0]}}};
assign btb_data_gwen_bank0       = btb_data_wen[1] && btb_data_wen[0];
assign btb_data_bwen_bank1[43:0] = {{22{btb_data_wen[3]}}, {22{btb_data_wen[2]}}};
assign btb_data_gwen_bank1       = btb_data_wen[3] && btb_data_wen[2];
























ct_spsram_512x44  x_ct_spsram_512x44_bank0 (
  .A                   (btb_index[8:0]     ),
  .CEN                 (btb_data_cen_b     ),
  .CLK                 (btb_data_clk       ),
  .D                   (btb_data_din       ),
  .GWEN                (btb_data_gwen_bank0),
  .Q                   (btb_data_dout[43:0]),
  .WEN                 (btb_data_bwen_bank0)
);












ct_spsram_512x44  x_ct_spsram_512x44_bank1 (
  .A                    (btb_index[8:0]      ),
  .CEN                  (btb_data_cen_b      ),
  .CLK                  (btb_data_clk        ),
  .D                    (btb_data_din        ),
  .GWEN                 (btb_data_gwen_bank1 ),
  .Q                    (btb_data_dout[87:44]),
  .WEN                  (btb_data_bwen_bank1 )
);














endmodule