data/full_repos/permissive/522240207/iiitb_bc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522240207/iiitb_bc_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    always #5 Clk = ~Clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/522240207/iiitb_bc_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("iiitb_bc_out.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522240207/iiitb_bc_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,iiitb_bc_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/522240207/iiitb_bc_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/522240207/iiitb_bc_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #30;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/522240207/iiitb_bc_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/522240207/iiitb_bc_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_bc_tb;


    reg Clk;
    reg reset;
    reg UpOrDown;


    wire [3:0] Count;


    iiitb_bc uut (
        .Clk(Clk), 
        .reset(reset), 
        .UpOrDown(UpOrDown), 
        .Count(Count)
    );


    initial Clk = 0;
    always #5 Clk = ~Clk;
    
    initial begin

	$dumpfile("iiitb_bc_out.vcd");
	$dumpvars(0,iiitb_bc_tb);
        reset = 0;
        UpOrDown = 0;
        #30;
        UpOrDown = 1;
      #30;
        reset = 1;
        UpOrDown = 0;
        #100;
        reset = 0;  
	#10000 $finish;
    end
      
endmodule
module iiitb_bc_tb;



    reg Clk;
    reg reset;
    reg UpOrDown;


    wire [3:0] Count;


    iiitb_bc uut (
        .Clk(Clk), 
        .reset(reset), 
        .UpOrDown(UpOrDown), 
        .Count(Count)
    );


    initial Clk = 0;
    always #5 Clk = ~Clk;
    
    initial begin

	$dumpfile("iiitb_bc_out.vcd");
	$dumpvars(0,iiitb_bc_tb);
        reset = 0;
        UpOrDown = 0;
        #30;
        UpOrDown = 1;
      #30;
        reset = 1;
        UpOrDown = 0;
        #100;
        reset = 0;  
	#10000 $finish;
    end
      
endmodule