data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/testbench_bits8_32word.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/testbench_bits8_32word.v:2: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word,data/full_repos/permissive/425529933/cmos_cells.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word,data/full_repos/permissive/425529933/cmos_cells.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word,data/full_repos/permissive/425529933/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/testbench_bits8_32word.v:3: Cannot find include file: bits8_32word_c.v\n`include "bits8_32word_c.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/testbench_bits8_32word.v:4: Cannot find include file: bits8_32word_e.v\n`include "bits8_32word_e.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/testbench_bits8_32word.v:5: Cannot find include file: probador_bits8_32word.v\n`include "probador_bits8_32word.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench_bits8_32word ();
	wire clk_4f;
	wire reset;
	wire valid_in;
	wire [7:0] Data_in;
	wire valid_out_c;
	wire [31:0] Data_out_c;
	wire valid_out_e;
	wire [31:0] Data_out_e;

	bits8_32word_c		bits8_32word_1(	.clk_4f_c(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c)
									);

	bits8_32word_e		bits8_32word_2(	.clk_4f_e(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
									);
	

	probador_bits8_32word	probador_1(	.clk_4f(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c),
										.valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
									);
endmodule
module testbench_bits8_32word ();

	wire clk_4f;
	wire reset;
	wire valid_in;
	wire [7:0] Data_in;
	wire valid_out_c;
	wire [31:0] Data_out_c;
	wire valid_out_e;
	wire [31:0] Data_out_e;

	bits8_32word_c		bits8_32word_1(	.clk_4f_c(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c)
									);

	bits8_32word_e		bits8_32word_2(	.clk_4f_e(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
									);
	

	probador_bits8_32word	probador_1(	.clk_4f(clk_4f),
										.reset(reset),
										.valid_in(valid_in),
										.Data_in(Data_in),
										.valid_out_c(valid_out_c),
										.Data_out_c(Data_out_c),
										.valid_out_e(valid_out_e),
										.Data_out_e(Data_out_e)
									);
endmodule