data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v
1: b'%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:40: Cannot find include file: openGFX430_defines.v\n`include "openGFX430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.sv\n             openGFX430_defines.v\n             openGFX430_defines.v.v\n             openGFX430_defines.v.sv\n             obj_dir/openGFX430_defines.v\n             obj_dir/openGFX430_defines.v.v\n             obj_dir/openGFX430_defines.v.sv\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:441: Cannot find include file: openGFX430_undefines.v\n`include "openGFX430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:97: Define or directive not defined: \'`APIX_MSB\'\noutput [`APIX_MSB:0] vid_ram_addr_nxt_o;        \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:97: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput [`APIX_MSB:0] vid_ram_addr_nxt_o;        \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:113: Define or directive not defined: \'`LPIX_MSB\'\ninput  [`LPIX_MSB:0] display_width_i;           \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:113: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput  [`LPIX_MSB:0] display_width_i;           \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:121: Define or directive not defined: \'`APIX_MSB\'\ninput  [`APIX_MSB:0] vid_ram_base_addr_i;       \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:121: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput  [`APIX_MSB:0] vid_ram_base_addr_i;       \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:180: Define or directive not defined: \'`LPIX_MSB\'\nreg  [`LPIX_MSB:0] vid_ram_width;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:180: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg  [`LPIX_MSB:0] vid_ram_width;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:186: Define or directive not defined: \'`LPIX_MSB\'\n  if (puc_rst)                 vid_ram_width   <=  {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:189: Define or directive not defined: \'`LPIX_MSB\'\nwire [16:0] vid_ram_width_tmp = {{16-`LPIX_MSB{1\'b0}}, vid_ram_width};\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:196: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] vid_ram_addr;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:196: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] vid_ram_addr;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:197: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] vid_ram_addr_inc;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:197: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] vid_ram_addr_inc;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:216: Define or directive not defined: \'`APIX_LO_MSB\'\nreg [`APIX_LO_MSB:0] vid_ram_addr_lo;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:216: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`APIX_LO_MSB:0] vid_ram_addr_lo;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:219: Define or directive not defined: \'`APIX_LO_MSB\'\n  if (puc_rst)                   vid_ram_addr_lo <=  {`APIX_LO_MSB+1{1\'b0}};\n                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:220: Define or directive not defined: \'`APIX_LO_MSB\'\n  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];\n                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:220: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];\n                                                                           ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:221: Define or directive not defined: \'`APIX_LO_MSB\'\n  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];\n                                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:221: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];\n                                                                                  ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:227: Define or directive not defined: \'`APIX_LO_MSB\'\nassign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};\n                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:227: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};\n                                                               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:228: Define or directive not defined: \'`APIX_LO_MSB\'\nwire [16:0] vid_ram_addr_lo_tmp = {{16-`APIX_LO_MSB{1\'b0}},vid_ram_addr_lo};\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: Define or directive not defined: \'`APIX_LO_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n                                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:393: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:393: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n                                          ^~~~~~~~~\n%Error: Exiting due to 39 error(s)\n'
function [15:0] one_hot16;
   input  [3:0] binary;
   begin
      one_hot16         = 16'h0000;
      one_hot16[binary] =  1'b1;
   end
endfunction
function [15:0] one_hot16;

   input  [3:0] binary;
   begin
      one_hot16         = 16'h0000;
      one_hot16[binary] =  1'b1;
   end
endfunction