data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #105;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:119: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:137: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;      \n       ^\n%Error: data/full_repos/permissive/494117590/hdl_src/tb/tb_btfly.v:30: Cannot find file containing module: \'btfly_op\'\nbtfly_op btfly(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/btfly_op\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/btfly_op.v\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/btfly_op.sv\n             btfly_op\n             btfly_op.v\n             btfly_op.sv\n             obj_dir/btfly_op\n             obj_dir/btfly_op.v\n             obj_dir/btfly_op.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_BTFLY_18x18S;


reg signed [17:0] i_s18_V0_R;
reg signed [17:0] i_s18_V0_I;
reg signed [17:0] i_s18_V1_R;
reg signed [17:0] i_s18_V1_I;
reg signed [17:0] i_s18_T0_R;
reg signed [17:0] i_s18_T0_I;
reg signed [17:0] i_s18_T1_R;
reg signed [17:0] i_s18_T1_I;


wire signed [17:0] o_s18_O0_R;
wire signed [17:0] o_s18_O0_I;
wire signed [17:0] o_s18_O1_R;
wire signed [17:0] o_s18_O1_I;

reg i_u1_valid_in;

reg clk;
reg rst_n;


wire o_u1_valid_out;


btfly_op btfly(
  .clk(clk) ,
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(o_u1_valid_out),
  .i_s18_V0_R(i_s18_V0_R),  
  .i_s18_V0_I(i_s18_V0_I),
  .i_s18_V1_R(i_s18_V1_R), 
  .i_s18_V1_I(i_s18_V1_I),
  .i_s18_T0_R(i_s18_T0_R),  
  .i_s18_T0_I(i_s18_T0_I), 
  .i_s18_T1_R(i_s18_T1_R), 
  .i_s18_T1_I(i_s18_T1_I),
  .o_s18_O0_R(o_s18_O0_R), 
  .o_s18_O0_I(o_s18_O0_I),
  .o_s18_O1_R(o_s18_O1_R), 
  .o_s18_O1_I(o_s18_O1_I)
);

initial begin





    i_s18_V0_R = -4981  ;
    i_s18_V0_I = 19661  ;
    i_s18_V1_R = -3277  ;
    i_s18_V1_I = 4443   ;
    i_s18_T0_R = -655   ;
    i_s18_T0_I = -50463 ;
    i_s18_T1_R = 33423  ;
    i_s18_T1_I = 262    ;


    i_u1_valid_in = 0;
    clk = 0;
    rst_n = 0;


    #105;
    #10 rst_n = 1;
    #50
    i_u1_valid_in = 1;

    #300






    i_s18_V0_R = 0 ;
    i_s18_V0_I = 0 ;
    i_s18_V1_R = 0 ;
    i_s18_V1_I = 0 ;
    i_s18_T0_R = 0 ;
    i_s18_T0_I = 0 ;
    i_s18_T1_R = 0 ;
    i_s18_T1_I = 0 ;


    #20;




    

    i_s18_V0_R = -9830 ;
    i_s18_V0_I = 51118 ;
    i_s18_V1_R = -51511;
    i_s18_V1_I = 3696  ;
    i_s18_T0_R = -655  ;
    i_s18_T0_I = -50463;
    i_s18_T1_R = 33423 ;
    i_s18_T1_I = 262   ;

    #20

    i_s18_V0_R = 0 ;
    i_s18_V0_I = 0 ;
    i_s18_V1_R = 0 ;
    i_s18_V1_I = 0 ;
    i_s18_T0_R = 0 ;
    i_s18_T0_I = 0 ;
    i_s18_T1_R = 0 ;
    i_s18_T1_I = 0 ;

    #20




    i_s18_V0_R = -4981  ;
    i_s18_V0_I = 19661  ;
    i_s18_V1_R = -3277  ;
    i_s18_V1_I = 4443   ;
    i_s18_T0_R = -655   ;
    i_s18_T0_I = -50463 ;
    i_s18_T1_R = 33423  ;
    i_s18_T1_I = 262    ;


    #100;

end
always #5 clk=~clk;      
endmodule
module Test_BTFLY_18x18S;



reg signed [17:0] i_s18_V0_R;
reg signed [17:0] i_s18_V0_I;
reg signed [17:0] i_s18_V1_R;
reg signed [17:0] i_s18_V1_I;
reg signed [17:0] i_s18_T0_R;
reg signed [17:0] i_s18_T0_I;
reg signed [17:0] i_s18_T1_R;
reg signed [17:0] i_s18_T1_I;


wire signed [17:0] o_s18_O0_R;
wire signed [17:0] o_s18_O0_I;
wire signed [17:0] o_s18_O1_R;
wire signed [17:0] o_s18_O1_I;

reg i_u1_valid_in;

reg clk;
reg rst_n;


wire o_u1_valid_out;


btfly_op btfly(
  .clk(clk) ,
  .rst_n(rst_n),
  .i_u1_valid_in(i_u1_valid_in),
  .o_u1_valid_out(o_u1_valid_out),
  .i_s18_V0_R(i_s18_V0_R),  
  .i_s18_V0_I(i_s18_V0_I),
  .i_s18_V1_R(i_s18_V1_R), 
  .i_s18_V1_I(i_s18_V1_I),
  .i_s18_T0_R(i_s18_T0_R),  
  .i_s18_T0_I(i_s18_T0_I), 
  .i_s18_T1_R(i_s18_T1_R), 
  .i_s18_T1_I(i_s18_T1_I),
  .o_s18_O0_R(o_s18_O0_R), 
  .o_s18_O0_I(o_s18_O0_I),
  .o_s18_O1_R(o_s18_O1_R), 
  .o_s18_O1_I(o_s18_O1_I)
);

initial begin





    i_s18_V0_R = -4981  ;
    i_s18_V0_I = 19661  ;
    i_s18_V1_R = -3277  ;
    i_s18_V1_I = 4443   ;
    i_s18_T0_R = -655   ;
    i_s18_T0_I = -50463 ;
    i_s18_T1_R = 33423  ;
    i_s18_T1_I = 262    ;


    i_u1_valid_in = 0;
    clk = 0;
    rst_n = 0;


    #105;
    #10 rst_n = 1;
    #50
    i_u1_valid_in = 1;

    #300






    i_s18_V0_R = 0 ;
    i_s18_V0_I = 0 ;
    i_s18_V1_R = 0 ;
    i_s18_V1_I = 0 ;
    i_s18_T0_R = 0 ;
    i_s18_T0_I = 0 ;
    i_s18_T1_R = 0 ;
    i_s18_T1_I = 0 ;


    #20;




    

    i_s18_V0_R = -9830 ;
    i_s18_V0_I = 51118 ;
    i_s18_V1_R = -51511;
    i_s18_V1_I = 3696  ;
    i_s18_T0_R = -655  ;
    i_s18_T0_I = -50463;
    i_s18_T1_R = 33423 ;
    i_s18_T1_I = 262   ;

    #20

    i_s18_V0_R = 0 ;
    i_s18_V0_I = 0 ;
    i_s18_V1_R = 0 ;
    i_s18_V1_I = 0 ;
    i_s18_T0_R = 0 ;
    i_s18_T0_I = 0 ;
    i_s18_T1_R = 0 ;
    i_s18_T1_I = 0 ;

    #20




    i_s18_V0_R = -4981  ;
    i_s18_V0_I = 19661  ;
    i_s18_V1_R = -3277  ;
    i_s18_V1_I = 4443   ;
    i_s18_T0_R = -655   ;
    i_s18_T0_I = -50463 ;
    i_s18_T1_R = 33423  ;
    i_s18_T1_I = 262    ;


    #100;

end
always #5 clk=~clk;      
endmodule