data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv
1: b'%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:138: Cannot find file containing module: \'IkariWarriorsCoreClocks_Cen\'\n    IkariWarriorsCoreClocks_Cen IK_clk_cen(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520811519/rtl,data/full_repos/permissive/520811519/IkariWarriorsCoreClocks_Cen\n             data/full_repos/permissive/520811519/rtl,data/full_repos/permissive/520811519/IkariWarriorsCoreClocks_Cen.v\n             data/full_repos/permissive/520811519/rtl,data/full_repos/permissive/520811519/IkariWarriorsCoreClocks_Cen.sv\n             IkariWarriorsCoreClocks_Cen\n             IkariWarriorsCoreClocks_Cen.v\n             IkariWarriorsCoreClocks_Cen.sv\n             obj_dir/IkariWarriorsCoreClocks_Cen\n             obj_dir/IkariWarriorsCoreClocks_Cen.v\n             obj_dir/IkariWarriorsCoreClocks_Cen.sv\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:155: Cannot find file containing module: \'IkariWarriorsCore_Clocks\'\nIkariWarriorsCore_Clocks IK_clocks(\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:226: Cannot find file containing module: \'IkariWarriorsCore_CPU_A_B\'\n    IkariWarriorsCore_CPU_A_B IK_cpuA_B\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:302: Cannot find file containing module: \'Dual_YM3526_Sound\'\n    Dual_YM3526_Sound IK_snd\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:333: Cannot find file containing module: \'IkariWarriorsCore_Registers\'\n    IkariWarriorsCore_Registers IK_registers(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:372: Cannot find file containing module: \'IkariWarriorsCore_Side\'\n    IkariWarriorsCore_Side IK_side(\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:418: Cannot find file containing module: \'IkariWarriorsCore_Back1\'\n    IkariWarriorsCore_Back1 IK_back1(\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:486: Cannot find file containing module: \'IkariWarriorsCore_Front1\'\n    IkariWarriorsCore_Front1 IK_front1(\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:530: Cannot find file containing module: \'IkariWarriorsCore_Front2\'\n    IkariWarriorsCore_Front2 IK_front2(\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:572: Cannot find file containing module: \'IkariWarriorsCore_LineBuffer\'\n    IkariWarriorsCore_LineBuffer IK_linebuf1(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:598: Cannot find file containing module: \'IkariWarriorsCore_LineBuffer\'\n    IkariWarriorsCore_LineBuffer IK_linebuf2(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:622: Cannot find file containing module: \'IkariWarriorsCore_FrontTurbo\'\n    IkariWarriorsCore_FrontTurbo IK_FrontTurbo(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:651: Cannot find file containing module: \'IkariWarriorsCore_FinalVideo\'\n    IkariWarriorsCore_FinalVideo IK_video_mixer(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/520811519/rtl/IkariWarriorsCore.sv:681: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n                                                                                 : ... In instance IkariWarriorsCore\n    assign SCR_X = X;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 13 error(s), 1 warning(s)\n'
module IkariWarriorsCore
(
    input wire RESETn,
    input wire VIDEO_RSTn,
    input wire pause_cpu,
    input wire i_clk,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
    input wire [7:0] GAME,
    input wire [15:0] DSW,
    output wire player_ctrl_clk,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,


	output        [23:0] rom_addr,
	input         [15:0] rom_data,
	output logic         rom_req,
	input                rom_ack,


    input wire [3:0] layer_ena_dbg,
    input wire [3:0] dbg_B1Voffset,
    input wire swap_px,    

    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B,
	output logic HBLANK,
	output logic VBLANK,
	output logic HSYNC,
	output logic VSYNC,
    output logic [8:0] SCR_Y,
    output logic [8:0] SCR_X,
    output logic VBL,
    output logic SYNC,
    output logic VS,
    output logic HS,
    output logic DISP,
    output logic PIX_CLK,
	output logic CE_PIXEL,


    output wire signed [15:0] snd1,
    output wire signed [15:0] snd2,
    output wire sample
);
    logic VRD, AE, BE;
    
    logic CK0, CK0n, CK1, CK1n, LDn;
    logic HLDn;
     logic [8:0] H;
     logic [2:0] Hn;
    logic [8:0] FH;
    logic F1CK;
    logic F2CK;
    logic [7:0] Y;
    logic [7:0] X;
    logic [8:0] F1V;
    logic [8:0] F2V;
    logic VCKn;
    logic LT;
    logic VLK;
    logic VFLGn;
    logic VDG, V_C;
    logic VWE, VOE;
    logic BWA, A_B, RLA, RLB, WBA, WBB;
    logic LA, LC, LD, HD8;
    logic WR0, WR1;


    logic  [7:0] AD;
    

    logic [7:0] VD_out, VD_in;
    logic [11:0] VA;


    logic FRONT1_VIDEO_CSn;
    logic FRONT2_VIDEO_CSn;
    logic BACK1_VRAM_CSn;
    logic SIDE_VRAM_CSn;
    logic DISC;
    logic F1SX;
    logic F1SY;
    logic F2SX;
    logic F2SY;
    logic B1SX;
    logic B1SY;
    logic SSET;
    logic BSET;
    logic XSET;
    logic YSET;
    logic MSET;
    logic F2INS;
    logic [5:0] FN;
    logic REG0n;
    logic REG1n;


    logic INV;
    logic INVn;
    logic B1X8;
    logic B1Y8;
    logic F1X8;
    logic F1Y8;
	logic F2X8;
    logic F2Y8;
    

    logic COIN;
    logic P1;
    logic P2;
    logic P1_P2;
    logic MCODE;
    logic DIP1;
    logic DIP2;

     logic clk_13p4_cen;
     logic clk_13p4;
     logic clk_13p4b_cen;
     logic clk_13p4b;
     logic clk_6p7_cen;
     logic clk_6p7b_cen;
     logic clk_3p35_cen;
     logic clk_3p35b_cen;
     logic clk_4_cen;
     logic clk_4b_cen;

    IkariWarriorsCoreClocks_Cen IK_clk_cen(
        .i_clk(i_clk),
        .clk_13p4_cen(clk_13p4_cen),
        .clk_13p4(clk_13p4),
        .clk_13p4b_cen(clk_13p4b_cen),
        .clk_13p4b(clk_13p4b),
        .clk_6p7_cen(clk_6p7_cen),
        .clk_6p7b_cen(clk_6p7b_cen),
        .clk_3p35_cen(clk_3p35_cen),
        .clk_3p35b_cen(clk_3p35b_cen),
        .clk_4_cen(clk_4_cen),
        .clk_4b_cen(clk_4b_cen)
    );
    
    assign player_ctrl_clk = clk_3p35_cen;
	assign CE_PIXEL = clk_6p7_cen; 

IkariWarriorsCore_Clocks IK_clocks(
    .clk(i_clk),
    .clk_13p4_cen(clk_13p4_cen),
    .clk_13p4(clk_13p4),
    .clk_13p4b_cen(clk_13p4b_cen),
    .clk_13p4b(clk_13p4b),
    .clk_6p7_cen(clk_6p7_cen),
    .clk_6p7b_cen(clk_6p7b_cen),
    .reset(VIDEO_RSTn),
    .VIDEO_RSTn(VIDEO_RSTn),
    .INVn(INVn), 
    .F1SX(F1SX),
    .F1X8(F1X8),
    .F2SX(F2SX),
    .F2X8(F2X8),
    .VD_in(VD_in),
    .VRD(VRD),
    .AE(AE),
    .BE(BE),

    .CK0(CK0),
    .CK0n(CK0n),
    .HLDn(HLDn),
    .CK1(CK1),
    .CK1n(CK1n),
    .H(H),
    .Hn(Hn),
    .FH(FH),
    .F1CK(F1CK),
    .F2CK(F2CK),
    .Y(Y),
    .X(X),
    .F1V(F1V),
    .F2V(F2V),
    .VCKn(VCKn),
    .VBL(VBL),
    .DISP(DISP),
    .SYNC(SYNC),
	.HBLANK(HBLANK),
	.VBLANK(VBLANK),
    .HSYNC(HSYNC),
    .VSYNC(VSYNC),
    .LT(LT),

    .VWE(VWE),
    .VOE(VOE),
    .BWA(BWA),
    .A_B(A_B),
    .RLA(RLA),
    .RLB(RLB),
    .WBA(WBA),
    .WBB(WBB),
    .VDG(VDG),
    .VLK(VLK),
    .V_C(V_C),
    .VFLGn(VFLGn),
    .HD8(HD8),
    .LC(LC),
    .LD(LD),
    .LA(LA),
    .WR0(WR0),
    .WR1(WR1)
	);

    logic SND_BUSY;
    logic CPUA_WR;
    logic CPUA_RD;
    logic [7:0] CPUAD;



    IkariWarriorsCore_CPU_A_B IK_cpuA_B
    (

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .H0(H[0]),
        .Cen_p(clk_3p35_cen),
        .Cen_n(clk_3p35b_cen),
        .RESETn(VIDEO_RSTn),
        .PLAYER1(PLAYER1),
        .PLAYER2(PLAYER2),
        .DSW(DSW),
        .VBL(VBL),
        .BWA(BWA),
        .A_B(A_B),
        .RLA(RLA),
        .RLB(RLB),
        .WBA(WBA),
        .WBB(WBB),
        .VDG(VDG),

        .VRDn(VRD),
        .AE(AE),
        .BE(BE),
        

        .CPUAD(CPUAD),
        .CPUA_RD(CPUA_RD),
        .CPUA_WR(CPUA_WR),


        .VA(VA),

        .V_out(VD_in),
        .V_in(VD_out),
        

        .GAME(GAME),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        

        .SND_BUSY(SND_BUSY),
        .COIN(COIN),
        .P1(P1),
        .P2(P2),
        .P1_P2(P1_P2),
        .MCODE(MCODE),
        .DIP1(DIP1),
        .DIP2(DIP2),


        .FRONT1_VIDEO_CSn(FRONT1_VIDEO_CSn),
        .FRONT2_VIDEO_CSn(FRONT2_VIDEO_CSn),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .SSET(SSET),
        .BSET(BSET),
        .F1SX(F1SX),
        .F1SY(F1SY),
        .F2SX(F2SX),
        .F2SY(F2SY),
        .B1SX(B1SX),
        .B1SY(B1SY),
        .XSET(XSET),
        .YSET(YSET),
        .MSET(MSET),
        .F2INS(F2INS),
        .REG0(REG0n),
        .REG1(REG1n)
    );

    Dual_YM3526_Sound IK_snd
    (
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .CEN_p(clk_4_cen),
        .CEN_n(clk_4b_cen),
        .RESETn(VIDEO_RSTn),
        .data_in(CPUAD),
        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        .MCODE(MCODE),
        .MS(SND_BUSY),
        .snd1(snd1),
        .snd2(snd2),
        .sample(sample)
    );








    logic [7:0] F1Y;
    logic [7:0] F2Y;
    logic [1:0] SBK;
    logic [2:0] SD_COLOR_BANK;

    IkariWarriorsCore_Registers IK_registers(
        .VIDEO_RSTn(VIDEO_RSTn),
        .reset(VIDEO_RSTn),
        .clk(i_clk),
        .VD_in(VD_in),


        .BSET(BSET),
        .INV(INV),
        .INVn(INVn),
        .B1X8(B1X8),
        .B1Y8(B1Y8),


        .SSET(SSET),
        .SBK(SBK),
        .SD_COLOR_BANK(SD_COLOR_BANK),


        .MSET(MSET),
        .F2Y8(F2Y8),
        .F2X8(F2X8),
        .F1Y8(F1Y8),
        .F1X8(F1X8),


        .F1SY(F1SY),
        .F1Y(F1Y),


        .F2SY(F2SY),
        .F2Y(F2Y)
    );


    logic [6:0] SD;
    assign SD[6:4] = SD_COLOR_BANK;
    logic [7:0] side_vout;

    IkariWarriorsCore_Side IK_side(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .INV(INV),
        .INVn(INVn),


        .VD_in(VD_in),
        .VD_out(side_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .VA(VA[10:0]),

        .VFLGn(VFLGn),
        .H8(H[8]),
        .Y(Y[7:3]),
        .X(X), 


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .VLK(VLK),
        .H2n(Hn[2]),
        .H1n(Hn[1]),
        .H0n(Hn[0]),


        .SBK(SBK),
        .SD(SD[3:0])
    );

    logic [7:0] B1D;

    logic [7:0] back1_vout;
    IkariWarriorsCore_Back1 IK_back1(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),
        .RESET(VIDEO_RSTn),

        .INV(INV),
        .INVn(INVn),

        .VD_in(VD_in),
        .VD_out(back1_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .dbg_B1Voffset(dbg_B1Voffset),
        .swap_px(swap_px),
        

        .rom_addr(rom_addr),
	     .rom_data(rom_data),
	     .rom_req(rom_req),
	     .rom_ack(rom_ack),

        .B1SY(B1SY),
        .B1SX(B1SX),

        .B1Y8(B1Y8),
        .B1X8(B1X8),

        .V_C(V_C),

        .H8(H[8]),
        .Y(Y[7:4]),
        .H3(H[3]),
        .H2(H[2]),
        .H1(H[1]),
        .H0(H[0]),
        .X(X), 
        .VA(VA[10:0]),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        

        .VFLGn(VFLGn),


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .CK1n(CK1n),
        .LA(LA),
        .VLK(VLK),


        .B1D(B1D[7:0])
    );
    
    logic [7:0] F1D;
    logic [8:0] FL_1Y;
    logic [8:0] SPR_1Y;
    logic [8:0] SPR_1X;
    logic [7:0] front1_vout;

    IkariWarriorsCore_Front1 IK_front1(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .VD_in(VD_in),
        .VD_out(front1_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .FRONT1_VIDEO_CSn(FRONT1_VIDEO_CSn),
        .VA(VA[11:0]),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .F1V(F1V),
        .FN(FN[5:0]),
        .LC(LC),
        .VLK(VLK),
        .F1CK(F1CK),
        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .F1D(F1D),
        .SPR_1Y(SPR_1Y),
        .SPR_1X(SPR_1X),
        .FL_1Y(FL_1Y)
    );

    logic [7:0] F2D;
    logic [8:0] SPR_2Y;
    logic [7:0] front2_vout;

    IkariWarriorsCore_Front2 IK_front2(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .V_C(V_C),

        .FRONT2_VIDEO_CSn(FRONT2_VIDEO_CSn),
        .VA(VA[10:0]), 
        .VD_in(VD_in),
        .VD_out(front2_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .F2V(F2V),
        .LC(LC),
        .VLK(VLK),

        .F1CK(F1CK),
        .F2CK(F2CK),
        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .F2D(F2D),
        .SPR_2Y(SPR_2Y)
    );


    logic [7:0] L1D_BUF;
    logic FYocho1;
    assign FYocho1 = F1Y8;
    IkariWarriorsCore_LineBuffer IK_linebuf1(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(F1D),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK_LDn(~(F1CK & ~LD)),
        .FLY(FL_1Y),
        .HLD(HLDn),
        .FY8(FYocho1),
        .FY(F1Y),
        .INVn(INVn),

        .LD_BUF(L1D_BUF)
    );


    logic [7:0] L2D_BUF;
    logic FYocho2;
    assign FYocho2 = F2Y8;
    IkariWarriorsCore_LineBuffer IK_linebuf2(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(F2D),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK_LDn(~(F2CK & F1CK & ~LD)),
        .FLY(SPR_2Y),
        .HLD(HLDn),
        .FY8(FYocho2),
        .FY(F2Y),
        .INVn(INVn),

        .LD_BUF(L2D_BUF)
    );

    logic [7:0] FT_VD_out;

    IkariWarriorsCore_FrontTurbo IK_FrontTurbo(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .H2n(Hn[2]),
        .H6(H[6]),
        .H7(H[7]),
        .XSET(XSET),
        .YSET(YSET),
        .F2INS(F2INS),
        .VD_in(VD_in),
        .VD_out(FT_VD_out),
        .SPR_1Y(SPR_1Y),
        .SPR_1X(SPR_1X),
        .VA(VA[6:5]),
        .WR0(WR0),
        .WR1(WR1),
        .REG0n(REG0n),
        .REG1n(REG1n),
        .FN(FN[5:0])
    );
    

        assign VD_out = ( (!VDG && !SIDE_VRAM_CSn)     ? side_vout   : (
                          (!VDG && !BACK1_VRAM_CSn)    ? back1_vout  : (
                          (!VDG && !FRONT1_VIDEO_CSn)  ? front1_vout : (  
                          (!VDG && !FRONT2_VIDEO_CSn)  ? front2_vout : ( 
                          ((!REG0n || !REG1n)) ? FT_VD_out   : 8'hff )))));

    IkariWarriorsCore_FinalVideo IK_video_mixer(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .HD8(HD8),
        .H1(H[1]),
        .CK1(CK1),
        .CK1n(CK1n),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .layer_ena_dbg(layer_ena_dbg),

        .L1D(L1D_BUF),
        .L2D(L2D_BUF[6:0]),
        .SD(SD),
        .B1D(B1D),



        .DISP(DISP),

        .R(R),
        .G(G),
        .B(B)
    );

    assign SCR_X = X;
    assign SCR_Y = {H[8],Y[7:3],H[2:0]};
    assign PIX_CLK = CK1;
endmodule
module IkariWarriorsCore
(
    input wire RESETn,
    input wire VIDEO_RSTn,
    input wire pause_cpu,
    input wire i_clk,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
    input wire [7:0] GAME,
    input wire [15:0] DSW,
    output wire player_ctrl_clk,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,


	output        [23:0] rom_addr,
	input         [15:0] rom_data,
	output logic         rom_req,
	input                rom_ack,


    input wire [3:0] layer_ena_dbg,
    input wire [3:0] dbg_B1Voffset,
    input wire swap_px,    

    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B,
	output logic HBLANK,
	output logic VBLANK,
	output logic HSYNC,
	output logic VSYNC,
    output logic [8:0] SCR_Y,
    output logic [8:0] SCR_X,
    output logic VBL,
    output logic SYNC,
    output logic VS,
    output logic HS,
    output logic DISP,
    output logic PIX_CLK,
	output logic CE_PIXEL,


    output wire signed [15:0] snd1,
    output wire signed [15:0] snd2,
    output wire sample
);

    logic VRD, AE, BE;
    
    logic CK0, CK0n, CK1, CK1n, LDn;
    logic HLDn;
     logic [8:0] H;
     logic [2:0] Hn;
    logic [8:0] FH;
    logic F1CK;
    logic F2CK;
    logic [7:0] Y;
    logic [7:0] X;
    logic [8:0] F1V;
    logic [8:0] F2V;
    logic VCKn;
    logic LT;
    logic VLK;
    logic VFLGn;
    logic VDG, V_C;
    logic VWE, VOE;
    logic BWA, A_B, RLA, RLB, WBA, WBB;
    logic LA, LC, LD, HD8;
    logic WR0, WR1;


    logic  [7:0] AD;
    

    logic [7:0] VD_out, VD_in;
    logic [11:0] VA;


    logic FRONT1_VIDEO_CSn;
    logic FRONT2_VIDEO_CSn;
    logic BACK1_VRAM_CSn;
    logic SIDE_VRAM_CSn;
    logic DISC;
    logic F1SX;
    logic F1SY;
    logic F2SX;
    logic F2SY;
    logic B1SX;
    logic B1SY;
    logic SSET;
    logic BSET;
    logic XSET;
    logic YSET;
    logic MSET;
    logic F2INS;
    logic [5:0] FN;
    logic REG0n;
    logic REG1n;


    logic INV;
    logic INVn;
    logic B1X8;
    logic B1Y8;
    logic F1X8;
    logic F1Y8;
	logic F2X8;
    logic F2Y8;
    

    logic COIN;
    logic P1;
    logic P2;
    logic P1_P2;
    logic MCODE;
    logic DIP1;
    logic DIP2;

     logic clk_13p4_cen;
     logic clk_13p4;
     logic clk_13p4b_cen;
     logic clk_13p4b;
     logic clk_6p7_cen;
     logic clk_6p7b_cen;
     logic clk_3p35_cen;
     logic clk_3p35b_cen;
     logic clk_4_cen;
     logic clk_4b_cen;

    IkariWarriorsCoreClocks_Cen IK_clk_cen(
        .i_clk(i_clk),
        .clk_13p4_cen(clk_13p4_cen),
        .clk_13p4(clk_13p4),
        .clk_13p4b_cen(clk_13p4b_cen),
        .clk_13p4b(clk_13p4b),
        .clk_6p7_cen(clk_6p7_cen),
        .clk_6p7b_cen(clk_6p7b_cen),
        .clk_3p35_cen(clk_3p35_cen),
        .clk_3p35b_cen(clk_3p35b_cen),
        .clk_4_cen(clk_4_cen),
        .clk_4b_cen(clk_4b_cen)
    );
    
    assign player_ctrl_clk = clk_3p35_cen;
	assign CE_PIXEL = clk_6p7_cen; 

IkariWarriorsCore_Clocks IK_clocks(
    .clk(i_clk),
    .clk_13p4_cen(clk_13p4_cen),
    .clk_13p4(clk_13p4),
    .clk_13p4b_cen(clk_13p4b_cen),
    .clk_13p4b(clk_13p4b),
    .clk_6p7_cen(clk_6p7_cen),
    .clk_6p7b_cen(clk_6p7b_cen),
    .reset(VIDEO_RSTn),
    .VIDEO_RSTn(VIDEO_RSTn),
    .INVn(INVn), 
    .F1SX(F1SX),
    .F1X8(F1X8),
    .F2SX(F2SX),
    .F2X8(F2X8),
    .VD_in(VD_in),
    .VRD(VRD),
    .AE(AE),
    .BE(BE),

    .CK0(CK0),
    .CK0n(CK0n),
    .HLDn(HLDn),
    .CK1(CK1),
    .CK1n(CK1n),
    .H(H),
    .Hn(Hn),
    .FH(FH),
    .F1CK(F1CK),
    .F2CK(F2CK),
    .Y(Y),
    .X(X),
    .F1V(F1V),
    .F2V(F2V),
    .VCKn(VCKn),
    .VBL(VBL),
    .DISP(DISP),
    .SYNC(SYNC),
	.HBLANK(HBLANK),
	.VBLANK(VBLANK),
    .HSYNC(HSYNC),
    .VSYNC(VSYNC),
    .LT(LT),

    .VWE(VWE),
    .VOE(VOE),
    .BWA(BWA),
    .A_B(A_B),
    .RLA(RLA),
    .RLB(RLB),
    .WBA(WBA),
    .WBB(WBB),
    .VDG(VDG),
    .VLK(VLK),
    .V_C(V_C),
    .VFLGn(VFLGn),
    .HD8(HD8),
    .LC(LC),
    .LD(LD),
    .LA(LA),
    .WR0(WR0),
    .WR1(WR1)
	);

    logic SND_BUSY;
    logic CPUA_WR;
    logic CPUA_RD;
    logic [7:0] CPUAD;



    IkariWarriorsCore_CPU_A_B IK_cpuA_B
    (

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .H0(H[0]),
        .Cen_p(clk_3p35_cen),
        .Cen_n(clk_3p35b_cen),
        .RESETn(VIDEO_RSTn),
        .PLAYER1(PLAYER1),
        .PLAYER2(PLAYER2),
        .DSW(DSW),
        .VBL(VBL),
        .BWA(BWA),
        .A_B(A_B),
        .RLA(RLA),
        .RLB(RLB),
        .WBA(WBA),
        .WBB(WBB),
        .VDG(VDG),

        .VRDn(VRD),
        .AE(AE),
        .BE(BE),
        

        .CPUAD(CPUAD),
        .CPUA_RD(CPUA_RD),
        .CPUA_WR(CPUA_WR),


        .VA(VA),

        .V_out(VD_in),
        .V_in(VD_out),
        

        .GAME(GAME),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        

        .SND_BUSY(SND_BUSY),
        .COIN(COIN),
        .P1(P1),
        .P2(P2),
        .P1_P2(P1_P2),
        .MCODE(MCODE),
        .DIP1(DIP1),
        .DIP2(DIP2),


        .FRONT1_VIDEO_CSn(FRONT1_VIDEO_CSn),
        .FRONT2_VIDEO_CSn(FRONT2_VIDEO_CSn),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .SSET(SSET),
        .BSET(BSET),
        .F1SX(F1SX),
        .F1SY(F1SY),
        .F2SX(F2SX),
        .F2SY(F2SY),
        .B1SX(B1SX),
        .B1SY(B1SY),
        .XSET(XSET),
        .YSET(YSET),
        .MSET(MSET),
        .F2INS(F2INS),
        .REG0(REG0n),
        .REG1(REG1n)
    );

    Dual_YM3526_Sound IK_snd
    (
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .CEN_p(clk_4_cen),
        .CEN_n(clk_4b_cen),
        .RESETn(VIDEO_RSTn),
        .data_in(CPUAD),
        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        .MCODE(MCODE),
        .MS(SND_BUSY),
        .snd1(snd1),
        .snd2(snd2),
        .sample(sample)
    );








    logic [7:0] F1Y;
    logic [7:0] F2Y;
    logic [1:0] SBK;
    logic [2:0] SD_COLOR_BANK;

    IkariWarriorsCore_Registers IK_registers(
        .VIDEO_RSTn(VIDEO_RSTn),
        .reset(VIDEO_RSTn),
        .clk(i_clk),
        .VD_in(VD_in),


        .BSET(BSET),
        .INV(INV),
        .INVn(INVn),
        .B1X8(B1X8),
        .B1Y8(B1Y8),


        .SSET(SSET),
        .SBK(SBK),
        .SD_COLOR_BANK(SD_COLOR_BANK),


        .MSET(MSET),
        .F2Y8(F2Y8),
        .F2X8(F2X8),
        .F1Y8(F1Y8),
        .F1X8(F1X8),


        .F1SY(F1SY),
        .F1Y(F1Y),


        .F2SY(F2SY),
        .F2Y(F2Y)
    );


    logic [6:0] SD;
    assign SD[6:4] = SD_COLOR_BANK;
    logic [7:0] side_vout;

    IkariWarriorsCore_Side IK_side(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .INV(INV),
        .INVn(INVn),


        .VD_in(VD_in),
        .VD_out(side_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .VA(VA[10:0]),

        .VFLGn(VFLGn),
        .H8(H[8]),
        .Y(Y[7:3]),
        .X(X), 


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .VLK(VLK),
        .H2n(Hn[2]),
        .H1n(Hn[1]),
        .H0n(Hn[0]),


        .SBK(SBK),
        .SD(SD[3:0])
    );

    logic [7:0] B1D;

    logic [7:0] back1_vout;
    IkariWarriorsCore_Back1 IK_back1(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),
        .RESET(VIDEO_RSTn),

        .INV(INV),
        .INVn(INVn),

        .VD_in(VD_in),
        .VD_out(back1_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .dbg_B1Voffset(dbg_B1Voffset),
        .swap_px(swap_px),
        

        .rom_addr(rom_addr),
	     .rom_data(rom_data),
	     .rom_req(rom_req),
	     .rom_ack(rom_ack),

        .B1SY(B1SY),
        .B1SX(B1SX),

        .B1Y8(B1Y8),
        .B1X8(B1X8),

        .V_C(V_C),

        .H8(H[8]),
        .Y(Y[7:4]),
        .H3(H[3]),
        .H2(H[2]),
        .H1(H[1]),
        .H0(H[0]),
        .X(X), 
        .VA(VA[10:0]),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        

        .VFLGn(VFLGn),


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .CK1n(CK1n),
        .LA(LA),
        .VLK(VLK),


        .B1D(B1D[7:0])
    );
    
    logic [7:0] F1D;
    logic [8:0] FL_1Y;
    logic [8:0] SPR_1Y;
    logic [8:0] SPR_1X;
    logic [7:0] front1_vout;

    IkariWarriorsCore_Front1 IK_front1(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .VD_in(VD_in),
        .VD_out(front1_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .FRONT1_VIDEO_CSn(FRONT1_VIDEO_CSn),
        .VA(VA[11:0]),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .F1V(F1V),
        .FN(FN[5:0]),
        .LC(LC),
        .VLK(VLK),
        .F1CK(F1CK),
        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .F1D(F1D),
        .SPR_1Y(SPR_1Y),
        .SPR_1X(SPR_1X),
        .FL_1Y(FL_1Y)
    );

    logic [7:0] F2D;
    logic [8:0] SPR_2Y;
    logic [7:0] front2_vout;

    IkariWarriorsCore_Front2 IK_front2(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .V_C(V_C),

        .FRONT2_VIDEO_CSn(FRONT2_VIDEO_CSn),
        .VA(VA[10:0]), 
        .VD_in(VD_in),
        .VD_out(front2_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .F2V(F2V),
        .LC(LC),
        .VLK(VLK),

        .F1CK(F1CK),
        .F2CK(F2CK),
        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .F2D(F2D),
        .SPR_2Y(SPR_2Y)
    );


    logic [7:0] L1D_BUF;
    logic FYocho1;
    assign FYocho1 = F1Y8;
    IkariWarriorsCore_LineBuffer IK_linebuf1(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(F1D),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK_LDn(~(F1CK & ~LD)),
        .FLY(FL_1Y),
        .HLD(HLDn),
        .FY8(FYocho1),
        .FY(F1Y),
        .INVn(INVn),

        .LD_BUF(L1D_BUF)
    );


    logic [7:0] L2D_BUF;
    logic FYocho2;
    assign FYocho2 = F2Y8;
    IkariWarriorsCore_LineBuffer IK_linebuf2(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(F2D),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK_LDn(~(F2CK & F1CK & ~LD)),
        .FLY(SPR_2Y),
        .HLD(HLDn),
        .FY8(FYocho2),
        .FY(F2Y),
        .INVn(INVn),

        .LD_BUF(L2D_BUF)
    );

    logic [7:0] FT_VD_out;

    IkariWarriorsCore_FrontTurbo IK_FrontTurbo(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .H2n(Hn[2]),
        .H6(H[6]),
        .H7(H[7]),
        .XSET(XSET),
        .YSET(YSET),
        .F2INS(F2INS),
        .VD_in(VD_in),
        .VD_out(FT_VD_out),
        .SPR_1Y(SPR_1Y),
        .SPR_1X(SPR_1X),
        .VA(VA[6:5]),
        .WR0(WR0),
        .WR1(WR1),
        .REG0n(REG0n),
        .REG1n(REG1n),
        .FN(FN[5:0])
    );
    

        assign VD_out = ( (!VDG && !SIDE_VRAM_CSn)     ? side_vout   : (
                          (!VDG && !BACK1_VRAM_CSn)    ? back1_vout  : (
                          (!VDG && !FRONT1_VIDEO_CSn)  ? front1_vout : (  
                          (!VDG && !FRONT2_VIDEO_CSn)  ? front2_vout : ( 
                          ((!REG0n || !REG1n)) ? FT_VD_out   : 8'hff )))));

    IkariWarriorsCore_FinalVideo IK_video_mixer(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .HD8(HD8),
        .H1(H[1]),
        .CK1(CK1),
        .CK1n(CK1n),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .layer_ena_dbg(layer_ena_dbg),

        .L1D(L1D_BUF),
        .L2D(L2D_BUF[6:0]),
        .SD(SD),
        .B1D(B1D),



        .DISP(DISP),

        .R(R),
        .G(G),
        .B(B)
    );

    assign SCR_X = X;
    assign SCR_Y = {H[8],Y[7:3],H[2:0]};
    assign PIX_CLK = CK1;
endmodule