data/full_repos/permissive/458134463/Modules/DataMemory_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/DataMemory_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n forever #2 clock = ~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/DataMemory_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10 MemWrite = 1\'b0; MemRead = 1\'b1;  \n^\n%Error: data/full_repos/permissive/458134463/Modules/DataMemory_tb.v:34: Unsupported or unknown PLI call: $monitor\n$monitor("Time: %3d | Clock: %1d | MemWrite: %1b | MemRead: %1b\\nAddress   : %32b\\nWrite Data: %32b\\nRead Data : %32b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DataMemory_tb();

reg MemWrite, MemRead;
reg clock;
reg [31:0] address;
reg [31:0] write_data;

wire [31:0] read_data;


DataMemory dm(MemWrite, MemRead, address, write_data, read_data, clock);

initial begin
	clock = 1'b0;
	forever #2 clock = ~clock;
end



initial begin

address    = 32'b00000000000000000000000000000001;
write_data = 32'hFFFFFFF1;

        MemWrite = 1'b1; MemRead = 1'b0;
#`DELAY MemWrite = 1'b0; MemRead = 1'b1;

end


initial begin
$monitor("Time: %3d | Clock: %1d | MemWrite: %1b | MemRead: %1b\nAddress   : %32b\nWrite Data: %32b\nRead Data : %32b", 
			$time, clock, MemWrite, MemRead, 
			address, write_data, read_data);
end

endmodule
module DataMemory_tb();


reg MemWrite, MemRead;
reg clock;
reg [31:0] address;
reg [31:0] write_data;

wire [31:0] read_data;


DataMemory dm(MemWrite, MemRead, address, write_data, read_data, clock);

initial begin
	clock = 1'b0;
	forever #2 clock = ~clock;
end



initial begin

address    = 32'b00000000000000000000000000000001;
write_data = 32'hFFFFFFF1;

        MemWrite = 1'b1; MemRead = 1'b0;
#`DELAY MemWrite = 1'b0; MemRead = 1'b1;

end


initial begin
$monitor("Time: %3d | Clock: %1d | MemWrite: %1b | MemRead: %1b\nAddress   : %32b\nWrite Data: %32b\nRead Data : %32b", 
			$time, clock, MemWrite, MemRead, 
			address, write_data, read_data);
end

endmodule