data/full_repos/permissive/529457593/Sprint10/countM10.v
data/verilator_xmls/ae17f6f0-d767-47d4-a491-e4ac652352ad.xml
module countM10 (input clock, reset, output reg [3:0] number);

	reg[3:0] count = 4'd0;

	always @ (posedge clock) begin
	
		count <= count + 4'd1;		
		if(count >= 4'd9 || reset == 0)
			count <= 4'd0;
			
		number = count;	
	end

endmodule
module countM10 (input clock, reset, output reg [3:0] number);


	reg[3:0] count = 4'd0;

	always @ (posedge clock) begin
	
		count <= count + 4'd1;		
		if(count >= 4'd9 || reset == 0)
			count <= 4'd0;
			
		number = count;	
	end

endmodule