data/full_repos/permissive/489075769/master_slave.v
1: b"%Error: data/full_repos/permissive/489075769/master_slave.v:22: Cannot find file containing module: 'master'\nmaster mt(ACLK, ARESETn,ARREADY,RVALID, ARVALID,RREADY,ARADDR,RDATA,o_RDATA,o_RRESP,ARPROT, read, data,\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/master\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/master.v\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/master.sv\n             master\n             master.v\n             master.sv\n             obj_dir/master\n             obj_dir/master.v\n             obj_dir/master.sv\n%Error: data/full_repos/permissive/489075769/master_slave.v:25: Cannot find file containing module: 'slave1'\nslave1 st(ACLK, ARESETn,ARVALID,RREADY,ARREADY,ARADDR,RVALID,RDATA,o_RRESP,read,\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module master_slave(ACLK,ARESETn,write,read,data,o_RDATA);

input ACLK;
input ARESETn;
input write;
input read;
input [31:0] data;
output[31:0] o_RDATA;
wire [31:0] RDATA;
wire [31:0]WDATA;
wire [31:0]AWADDR;
wire [31:0]ARADDR;
wire[3:0] WSTRB;
wire [2:0] AWPROT;
wire [2:0] ARPROT;
wire [1:0]o_RRESP;
wire [1:0] BRESP;
wire [1:0] o_BRESP;
wire ARREADY,RVALID, ARVALID,RREADY,
AWREADY,WREADY,BVALID,AWVALID,WVALID,BREADY;

master mt(ACLK, ARESETn,ARREADY,RVALID, ARVALID,RREADY,ARADDR,RDATA,o_RDATA,o_RRESP,ARPROT, read, data,
AWREADY,WREADY,BVALID,write,AWVALID,AWADDR,WVALID,WDATA,WSTRB,AWPROT,BREADY,BRESP);

slave1 st(ACLK, ARESETn,ARVALID,RREADY,ARREADY,ARADDR,RVALID,RDATA,o_RRESP,read,
write,AWVALID,WVALID,BREADY,AWADDR,WDATA,WSTRB,BRESP,AWREADY,WREADY,BVALID,o_BRESP);

endmodule
module master_slave(ACLK,ARESETn,write,read,data,o_RDATA);


input ACLK;
input ARESETn;
input write;
input read;
input [31:0] data;
output[31:0] o_RDATA;
wire [31:0] RDATA;
wire [31:0]WDATA;
wire [31:0]AWADDR;
wire [31:0]ARADDR;
wire[3:0] WSTRB;
wire [2:0] AWPROT;
wire [2:0] ARPROT;
wire [1:0]o_RRESP;
wire [1:0] BRESP;
wire [1:0] o_BRESP;
wire ARREADY,RVALID, ARVALID,RREADY,
AWREADY,WREADY,BVALID,AWVALID,WVALID,BREADY;

master mt(ACLK, ARESETn,ARREADY,RVALID, ARVALID,RREADY,ARADDR,RDATA,o_RDATA,o_RRESP,ARPROT, read, data,
AWREADY,WREADY,BVALID,write,AWVALID,AWADDR,WVALID,WDATA,WSTRB,AWPROT,BREADY,BRESP);

slave1 st(ACLK, ARESETn,ARVALID,RREADY,ARREADY,ARADDR,RVALID,RDATA,o_RRESP,read,
write,AWVALID,WVALID,BREADY,AWADDR,WDATA,WSTRB,BRESP,AWREADY,WREADY,BVALID,o_BRESP);

endmodule