data/full_repos/permissive/485129576/mem16.v
data/verilator_xmls/66c26981-8c89-49e4-8fe1-388449e95b25.xml
module MEM16 (
    input [7:0] A,
    output wire [15:0] instruc
);
    reg [15:0] ram [0:255];

    initial $readmemb("instruc.txt", ram, 0);

    assign instruc = ram[A];
    
endmodule
module MEM16 (
    input [7:0] A,
    output wire [15:0] instruc
);

    reg [15:0] ram [0:255];

    initial $readmemb("instruc.txt", ram, 0);

    assign instruc = ram[A];
    
endmodule