data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioout.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioout.v:48: Cannot find file containing module: 'fflopx'\nfflopx #(DW) ffodath (txclk, txrst_, idat_h, odat_h);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioout.v:49: Cannot find file containing module: 'fflopx'\nfflopx #(DW) ffodatl (txclk, txrst_, idat_l, odat_l);\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ipsmacge_ifddioout
    (
     txclk,
     txrst_,
     idat_h,
     idat_l,
     odat_h,
     odat_l
     );



parameter DW = 4;



input             txrst_;
input             txclk;


input [DW-1: 0]   idat_h;
input [DW-1: 0]   idat_l;

output [DW-1: 0]  odat_h;
output [DW-1: 0]  odat_l;



wire [DW-1:0]     odat_h;
wire [DW-1:0]     odat_l;




fflopx #(DW) ffodath (txclk, txrst_, idat_h, odat_h);
fflopx #(DW) ffodatl (txclk, txrst_, idat_l, odat_l);

endmodule
module ipsmacge_ifddioout
    (
     txclk,
     txrst_,
     idat_h,
     idat_l,
     odat_h,
     odat_l
     );




parameter DW = 4;



input             txrst_;
input             txclk;


input [DW-1: 0]   idat_h;
input [DW-1: 0]   idat_l;

output [DW-1: 0]  odat_h;
output [DW-1: 0]  odat_l;



wire [DW-1:0]     odat_h;
wire [DW-1:0]     odat_l;




fflopx #(DW) ffodath (txclk, txrst_, idat_h, odat_h);
fflopx #(DW) ffodatl (txclk, txrst_, idat_l, odat_l);

endmodule