data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v
1: b'%Error: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:270: Cannot find file containing module: \'fifo_video\'\n fifo_video thingera (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519183085/src/core/PDP-1,data/full_repos/permissive/519183085/fifo_video\n             data/full_repos/permissive/519183085/src/core/PDP-1,data/full_repos/permissive/519183085/fifo_video.v\n             data/full_repos/permissive/519183085/src/core/PDP-1,data/full_repos/permissive/519183085/fifo_video.sv\n             fifo_video\n             fifo_video.v\n             fifo_video.sv\n             obj_dir/fifo_video\n             obj_dir/fifo_video.v\n             obj_dir/fifo_video.sv\n%Error: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:330: Cannot find file containing module: \'rendram\'\n   rendram rr_gen (\n   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:466: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n        foundit[j] <= 1\'b0;            \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:467: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n        minbrite[j] <= 10\'h3ff;           \n                ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:489: Operator EQ expects 12 bits on the LHS, but LHS\'s VARREF \'vertical_counter\' generates 11 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n          (vertical_counter == dimline), (fifovalid & ({fifo_y, fifo_x} == pa_out[j][19:0])),\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:489: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n          (vertical_counter == dimline), (fifovalid & ({fifo_y, fifo_x} == pa_out[j][19:0])),\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:490: Operator EQ expects 7 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n          ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & (j == bufcount)), pa_out[j][31:29]\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:490: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'bufcount\' generates 4 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n          ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & (j == bufcount)), pa_out[j][31:29]\n                                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:490: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n          ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & (j == bufcount)), pa_out[j][31:29]\n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:495: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {2\'b11, phos_full, fifo_y, fifo_x};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:496: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_wren[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:497: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             foundit[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:502: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {1\'b0, pa_out[j][30:0]};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:502: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {1\'b0, pa_out[j][30:0]};\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:503: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_wren[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:509: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j][31:30] <= {1\'b0, pa_out[j][30]};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:509: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j][31:30] <= {1\'b0, pa_out[j][30]};\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:510: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j][19:0] <= pa_out[j][19:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:510: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j][19:0] <= pa_out[j][19:0];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:511: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             casex({&pa_out[j][29:20], 1\'b0, pa_out[j][29:20]} - {1\'b0, phos_dim})\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:511: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             casex({&pa_out[j][29:20], 1\'b0, pa_out[j][29:20]} - {1\'b0, phos_dim})\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:512: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             12\'b1xxx_xxxx_xxxx : pb_in[j][29:20] <= 10\'h3fe;         \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:513: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             12\'b00xx_xxxx_xxxx : pb_in[j][29:20] <= (pa_out[j][29:20] - phos_dim);  \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:513: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             12\'b00xx_xxxx_xxxx : pb_in[j][29:20] <= (pa_out[j][29:20] - phos_dim);  \n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:514: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             12\'b01xx_xxxx_xxxx : pb_in[j][29:20] <= 10\'h0;          \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:516: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_wren[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:521: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {12\'h0, 20\'h0};   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:522: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_wren[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:527: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {1\'b0, pa_out[j][30:0]};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:527: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_in[j] <= {1\'b0, pa_out[j][30:0]};\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:528: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n             pb_wren[j] <= 1\'b1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:533: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n            pb_wren[j] <= 1\'b0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:540: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n        minbrite[j] <= pa_out[j][29:20];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:540: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n        minbrite[j] <= pa_out[j][29:20];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:541: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n        mb_add[j] <= ramcnta_d;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:538: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n       if ((pa_out[j][29:20] < minbrite[j]) & ~pipehold)\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:538: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n       if ((pa_out[j][29:20] < minbrite[j]) & ~pipehold)\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:553: Operator EQ expects 7 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n      if ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & pa_out[bufcount][29]) pixwrite <= ~pixwrite;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:567: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n       pb_wren[j] <= 1\'b0;    \n              ^\n%Warning-WIDTH: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:571: Operator EQ expects 12 bits on the LHS, but LHS\'s VARREF \'vertical_counter\' generates 11 bits.\n                                                                                      : ... In instance pdp1_vga_crt\n      casex({(vertical_counter == dimline), |foundit | ~fifovalid})\n                               ^~\n%Error: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:660: Cannot find file containing module: \'linebuf\'\n linebuf thingerb ( .clock(clk),\n ^~~~~~~\n%Error: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:672: Cannot find file containing module: \'linebuf\'\n linebuf thingerc ( .clock(clk),\n ^~~~~~~\n%Error: data/full_repos/permissive/519183085/src/core/PDP-1/pdp1_vga_crt.v:687: Cannot find file containing module: \'color_lut\'\n color_lut thingerd (\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 38 warning(s)\n'
module pdp1_vga_crt (
	input 				reset_n,
	input 				clk,
	input 				CLK_50M,
	input [10:0] 		horizontal_counter,              
	input [10:0] 		vertical_counter,   
	output reg [7:0] 	red_out,                         
	output reg [7:0] 	green_out,
	output reg [7:0] 	blue_out,             
   input 				frame_odd,
	input					cpu_stall,
	output reg			cpu_vga_run,
  
	input  [9:0] 		pixel_x_i,
	input  [9:0] 		pixel_y_i,                       
	input  [2:0] 		pixel_brightness,                
	input 				variable_brightness,       
	input  				pixel_available,
	input  [1:0]		pixel_type,
	
	input 				mag_ships,
	input [2:0] 		trail_len,
	input 				blur_on,
	
	input 				clk_74a,
	input	[31:0]		bridge_addr,
	input					bridge_wr,
	input	[31:0]		bridge_wr_data
	
	
);
             
	
	wire use_debugs = 1'b0;
	



	wire [9:0] xcoord = xprod[15:6];
	wire [9:0] ycoord = yprod[15:6];
	

	wire [9:0] xmula = pixel_y;
	wire [5:0] xmulb = 6'd48;	
	wire [15:0] xprod = xmula * xmulb;
	

	wire [9:0] ymula = ~pixel_x;
	wire [5:0] ymulb = 6'd45;
	wire [15:0] yprod = ymula * ymulb;
	
	reg [1:0] pa_del;
	reg [2:0] frame_odd_d;
	reg [1:0] cpu_stall_d;
	
	
	reg [9:0] pixel_x;
	reg [9:0] pixel_y;
	reg write_fifo;
	reg [3:0] stuffstate;
	reg [3:0] ss_wait;
	reg [9:0] pixtest;
	
	reg [7:0] needlecnt;
	reg [7:0] wedgecnt;
	
	reg [39:0] w_coord;
	reg [39:0] n_coord;
	
	

	always @ (posedge CLK_50M)
	begin
	
	
		
		pa_del <= {pa_del[0], pixel_available};
		frame_odd_d <= {frame_odd_d[1:0], frame_odd};
		cpu_vga_run <= (frame_odd_d[2:1] == 2'b01);
		
		
		if (frame_odd_d[2:1] == 2'b01)
		begin
			needlecnt <= 8'h0;
			wedgecnt <= 8'h0;
		end
		else if (write_fifo)
		case (pixel_type)
		2'h1 :	begin
						needlecnt <= needlecnt + 1'b1;
						if (needlecnt == 8'h14) n_coord <= {~pixel_x, pixel_y, ycoord, xcoord};
					end
		2'h2 :	begin
						wedgecnt <= wedgecnt + 1'b1;
						if (wedgecnt == 8'h24) w_coord <= {~pixel_x, pixel_y, ycoord, xcoord};
					end
		endcase			
					
		


		if (cpu_stall_d == 2'b01)
		begin
			stuffstate <= (use_debugs ? 4'h1 : 4'h6);
			write_fifo <= 1'b0;
		end
		else if (|ss_wait)
		begin
			ss_wait <= ss_wait - 1'b1;
			write_fifo <= 1'b0;
		end
		else
		case(stuffstate)

		4'h1 :	begin
						pixel_x <= 10'h0;
						pixel_y <= 10'h0;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h2;
					end
		
		4'h2 :	begin
						pixel_x <= 10'h3ff;
						pixel_y <= 10'h0;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h3;
					end

		4'h3 :	begin
						pixel_x <= 10'h0;
						pixel_y <= 10'h3ff;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h4;
					end

		4'h4 :	begin
						pixel_x <= 10'h3ff;
						pixel_y <= 10'h3ff;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h5;
					end
					
		4'h5 :	begin
						pixel_x <= 10'h100;
						pixel_y <= pixtest;
						pixtest <= pixtest + 1'b1;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h6;
					end
		
		4'h6 :	begin
						pixel_x <= pixel_x_i;
						pixel_y <= pixel_y_i;
						write_fifo <= (pa_del == 2'b01);
					end
		
		endcase
					

		
	end	
		
	
	wire [9:0] curr_x;
	wire [9:0] curr_y;
	wire [1:0] curr_type;
	
	reg rdreq;
	wire rdempty;
	wire wr_full;
	
	
	wire magpix = (^pixel_type) & mag_ships;
	
	fifo_video thingera (
									.wrclk	(CLK_50M),
									.data		({pixel_type & {2{mag_ships}}, (magpix ? {~pixel_x, pixel_y} : {ycoord, xcoord})}),
									.wrreq	(write_fifo & ~wr_full),
									.wrfull  (wr_full),
									
									.rdclk	(clk),
									.rdreq	(rdreq),
									.rdempty	(rdempty),
									.q			({curr_type, curr_y, curr_x})
							  );


	
	
	
	localparam numbuffs = 8'd16;
	reg [3:0] ob_buf;
	reg [3:0] ob_count;
	reg [3:0] bufcount;
	wire bufbit = vertical_counter[4];
	localparam dimline = 12'd737;
	localparam startline = 12'd12;
	localparam cv_lowbit = 'd4;
	

	reg [9:0] phos_dim;
	always
	case(trail_len[2:0])
	3'h0 : phos_dim <= 10'h3fe;
	3'h1 : phos_dim <= 10'd64;
	3'h2 : phos_dim <= 10'd32;
	3'h3 : phos_dim <= 10'd16;
	3'h4 : phos_dim <= 10'd8;
	3'h5 : phos_dim <= 10'd4;
	3'h6 : phos_dim <= 10'd2;
	3'h7 : phos_dim <= 10'd1;
	endcase
		
	localparam phos_full = 10'h3ff;
	
	wire [31:0] pa_out [numbuffs-1:0];
	wire [31:0] pb_out [numbuffs-1:0];
	reg [9:0] ramcnta;
	reg [9:0] ramcntb;
	reg pb_wren [numbuffs-1:0];
	reg [31:0] pb_in [numbuffs-1:0];
		







	
	genvar i;
	generate
		for (i = 0; i < numbuffs; i=i+1)
		begin : ramgen
			rendram rr_gen (
			.clock(clk),
			.data_a(32'h0000_0000), .address_a(ramcnta), .wren_a(1'b0), .q_a(pa_out[i]),
			.data_b(pb_in[i]), .address_b(ramcntb), .wren_b(pb_wren[i]), .q_b(pb_out[i])
			);
		end
	endgenerate
	
	
	reg [numbuffs-1:0] foundit;
	reg [9:0] minbrite [numbuffs-1:0];
	reg [9:0] mb_add [numbuffs-1:0];
	reg [3:0] state;
	reg [7:0] j;
	reg [9:0] oldestbrite;
	reg [9:0] ob_add;
	reg [9:0] ramcnta_d;
	reg pipehold;
	
	reg fifovalid;
	reg [9:0] fifo_x;
	reg [9:0] fifo_y;

	reg whichbuf;
	reg [7:0] pixout;
	reg [9:0] out_x;
	reg [9:0] out_y;
	reg pixwrite, pixwrite_d;

	reg [39:0] w_coord_d;
	reg [39:0] n_coord_d;
	
	












	
	
	

	

	wire [9:0] w_ya = (curr_y - w_coord_d[39:30]);
	wire [10:0] w_yb = ({w_ya[9], w_ya} + {1'b0, w_coord_d[19:10]});
	

	reg [9:0] w_y_fix;
	always
	case({(w_yb > 11'd719), w_yb[10]})
	2'b10 	: w_y_fix <= (w_yb[9:0] + 10'd304);
	2'b11 	: w_y_fix <= (w_yb[9:0] + 10'd720);
	default	: w_y_fix <= w_yb[9:0];
	endcase
	

	wire [9:0] w_xa = (curr_x - w_coord_d[29:20]);
	wire [10:0] w_xb = ({w_xa[9], w_xa} + {1'b0, w_coord_d[ 9: 0]});
	

	reg [9:0] w_x_fix;
	always
	case({(w_xb > 11'd767), w_xb[10]})
	2'b10 	: w_x_fix <= (w_xb[9:0] + 10'd256);
	2'b11 	: w_x_fix <= (w_xb[9:0] + 10'd768);
	default	: w_x_fix <= w_xb[9:0];
	endcase


	wire [9:0] n_ya = (curr_y - n_coord_d[39:30]);
	wire [10:0] n_yb = ({n_ya[9], n_ya} + {1'b0, n_coord_d[19:10]});
	

	reg [9:0] n_y_fix;
	always
	case({(n_yb > 11'd719), n_yb[10]})
	2'b10 	: n_y_fix <= (n_yb[9:0] + 10'd304);
	2'b11 	: n_y_fix <= (n_yb[9:0] + 10'd720);
	default	: n_y_fix <= n_yb[9:0];
	endcase
	

	wire [9:0] n_xa = (curr_x - n_coord_d[29:20]);
	wire [10:0] n_xb = ({n_xa[9], n_xa} + {1'b0, n_coord_d[ 9: 0]});
	

	reg [9:0] n_x_fix;
	always
	case({(n_xb > 11'd767), n_xb[10]})
	2'b10 	: n_x_fix <= (n_xb[9:0] + 10'd256);
	2'b11 	: n_x_fix <= (n_xb[9:0] + 10'd768);
	default	: n_x_fix <= n_xb[9:0];
	endcase
	
	always @ (posedge clk)
	begin
	
		w_coord_d <= w_coord;
		n_coord_d <= n_coord;
		
		cpu_stall_d <= {cpu_stall_d[0], cpu_stall};
		
		if (~|vertical_counter)
		begin
			state <= 4'h1;
			bufcount <= 0;
		end
		else
		case (state)

		4'h1 :	begin
						
						if (horizontal_counter == 1)
						begin
							
							whichbuf <= bufbit;
							ramcnta <= 0;
							
							fifovalid <= ~rdempty & cpu_stall_d[1];
							case(curr_type)
							2'h1 		: {fifo_y, fifo_x} <= {n_y_fix, n_x_fix};
							2'h2 		: {fifo_y, fifo_x} <= {w_y_fix, w_x_fix};
							default	: {fifo_y, fifo_x} <= {curr_y, curr_x};
							endcase
							rdreq <= ~rdempty & cpu_stall_d[1];
							
							for (j = 0; j < numbuffs; j = j + 1)
							begin
								foundit[j] <= 1'b0;
								minbrite[j] <= 10'h3ff;
							end
							
							pipehold <= 1'b1;
							state <= 4'h2;
						 
						 end
						 
					end
		


		4'h2 :	begin
						rdreq <= 1'b0;

						ramcnta_d <= ramcnta;
						ramcntb <= ramcnta_d;

						if (~pipehold)
						for (j = 0; j < numbuffs; j = j + 1)
						begin
							casex({
										(vertical_counter == dimline), (fifovalid & ({fifo_y, fifo_x} == pa_out[j][19:0])),
										((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & (j == bufcount)), pa_out[j][31:29]
									})
							

							6'b01x_x1x :	begin
													pb_in[j] <= {2'b11, phos_full, fifo_y, fifo_x};
													pb_wren[j] <= 1'b1;
													foundit[j] <= 1'b1;
												end
											

							6'b001_1xx :	begin
													pb_in[j] <= {1'b0, pa_out[j][30:0]};
													pb_wren[j] <= 1'b1;
												end
												


							6'b1xx_0x1 :	begin
													pb_in[j][31:30] <= {1'b0, pa_out[j][30]};
													pb_in[j][19:0] <= pa_out[j][19:0];
													casex({&pa_out[j][29:20], 1'b0, pa_out[j][29:20]} - {1'b0, phos_dim})
													12'b1xxx_xxxx_xxxx : pb_in[j][29:20] <= 10'h3fe;
													12'b00xx_xxxx_xxxx : pb_in[j][29:20] <= (pa_out[j][29:20] - phos_dim);
													12'b01xx_xxxx_xxxx : pb_in[j][29:20] <= 10'h0;
													endcase
													pb_wren[j] <= 1'b1;
												end
							

							6'b1xx_0x0 :	begin
													pb_in[j] <= {12'h0, 20'h0};
													pb_wren[j] <= 1'b1;
												end
							

							6'b1xx_1xx :	begin
													pb_in[j] <= {1'b0, pa_out[j][30:0]};
													pb_wren[j] <= 1'b1;
												end
							

							default :	begin
												pb_wren[j] <= 1'b0;
											end
							endcase
							

							if ((pa_out[j][29:20] < minbrite[j]) & ~pipehold)
							begin
								minbrite[j] <= pa_out[j][29:20];
								mb_add[j] <= ramcnta_d;
							end
						
						end


						pipehold <= 1'b0;
						

						{pixout, out_y, out_x} <= {pa_out[bufcount][28:21], pa_out[bufcount][19:0]};
						

						if ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & pa_out[bufcount][29]) pixwrite <= ~pixwrite;


						ramcnta <= ramcnta + 1'b1;
						if (~|ramcnta & ~pipehold) state <= 4'h3;
					
					end
		

		4'h3 :	begin
						
						for (j = 0; j < numbuffs; j = j + 1)
						begin
							
							pb_wren[j] <= 1'b0;
						
						end
						
						casex({(vertical_counter == dimline), |foundit | ~fifovalid})
						2'b1x : state <= 4'h0;
						2'b01 : state <= 4'h1;
						2'b00 : state <= 4'h4;
						endcase
						
						oldestbrite <= 10'h3ff;
						ob_count <= 0;
						
						bufcount <= bufcount + 1'b1;
						
					end
		
		

		4'h4 :	begin
						if (minbrite[ob_count] < oldestbrite)
						begin
							oldestbrite <= minbrite[ob_count];
							ob_add <= mb_add[ob_count];
							ob_buf <= ob_count;
						end
						ob_count <= ob_count + 1'b1;
						if (&ob_count) state <= 4'h5;						
					end
		

		4'h5 :	begin
						pb_in[ob_buf] <= {2'b11, phos_full, fifo_y, fifo_x};
						ramcntb <= ob_add;
						pb_wren[ob_buf] <= 1'b1;
						state <= 4'h6;
					end


		4'h6 :	begin
						pb_wren[ob_buf] <= 1'b0;
						state <= 4'h1;
					end
		
		
		endcase

		
		
		pixwrite_d <= pixwrite;
		
		if (~whichbuf)
		begin

			buf_a_wr <= (pixwrite ^ pixwrite_d);
			buf_a_dat <= pixout;
			buf_a_add <= {out_y[cv_lowbit-1:0], out_x};

			buf_b_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd8)};
			buf_out <= buf_b_out;
		end
		else
		begin

			buf_b_wr <= (pixwrite ^ pixwrite_d);
			buf_b_dat <= pixout;
			buf_b_add <= {out_y[cv_lowbit-1:0], out_x};

			buf_a_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd8)};
			buf_out <= buf_a_out;
		end
		

		buf_c_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd16)};
		buf_c_wr <= (horizontal_counter >= 11'd16);
		
	
	end
	
	

	
	reg [7:0] buf_out;
	reg [13:0] buf_c_add;
	reg buf_c_wr;
	
	reg [7:0] buf_a_dat;
	reg [13:0] buf_a_add;
	reg buf_a_wr;
	wire [7:0] buf_a_out;
	wire [7:0] buf_a_outb;
	
		
	linebuf thingerb (	.clock(clk),
								.data_a(buf_a_dat), .address_a(buf_a_add), .wren_a(buf_a_wr), .q_a(buf_a_out),
								.data_b(8'h0), .address_b(buf_c_add), .wren_b(buf_c_wr & whichbuf), .q_b(buf_a_outb)
							);
							
	reg [7:0] buf_b_dat;
	reg [13:0] buf_b_add;
	reg buf_b_wr;
	wire [7:0] buf_b_out;
	wire [7:0] buf_b_outb;
	
		
	linebuf thingerc (	.clock(clk),
								.data_a(buf_b_dat), .address_a(buf_b_add), .wren_a(buf_b_wr), .q_a(buf_b_out),
								.data_b(8'h0), .address_b(buf_c_add), .wren_b(buf_c_wr & ~whichbuf), .q_b(buf_b_outb)
							);
							
							
	

	
	wire [23:0] output_color;
	


	wire write_clut_en = bridge_wr && (bridge_addr[31:16] == 16'h1000); 

	color_lut thingerd (
		.write_clk		(clk_74a),
		.write_address	(bridge_addr[9:2]),
		.write_data		(bridge_wr_data),
		.write_enable	(write_clut_en),
		.read_clk		(clk),
		.input_index	(buf_out),
		.output_color	(output_color)
	);
							

							



	
	reg [23:0] linebufa [1023:0];
	reg [23:0] linebufb [1023:0];
	reg [23:0] linebufc [1023:0];
	
	reg [23:0] pix [8:0];
	
	wire [9:0] writeline = (horizontal_counter[9:0] - 10'd3);

	reg [11:0] gauss_ra, gauss_rb, gauss_rc, gauss_r;
	reg [11:0] gauss_ga, gauss_gb, gauss_gc, gauss_g;
	reg [11:0] gauss_ba, gauss_bb, gauss_bc, gauss_b;
	
	
	
	always @ (posedge clk)
	begin	
	




		
		
		pix[2] <= pix[1];
		pix[1] <= pix[0];
		pix[0] <= linebufa[horizontal_counter[9:0]];
		
		pix[5] <= pix[4];
		pix[4] <= pix[3];
		pix[3] <= linebufb[horizontal_counter[9:0]];
		
		pix[8] <= pix[7];
		pix[7] <= pix[6];
		pix[6] <= linebufc[horizontal_counter[9:0]];
							
		if (~horizontal_counter[10])
		begin
			
			linebufa[writeline] <= ((output_color[23] | ~blur_on) ? output_color : {1'b0, output_color[23:17], 1'b0, output_color[15:9], 1'b0, output_color[7:1]});
			linebufb[writeline] <= pix[2];
			linebufc[writeline] <= pix[5];
			
		end

		gauss_ra <= {4'h0, pix[0][7:0]      } + {3'h0, pix[1][7:0], 1'b0} + {4'h0, pix[2][7:0]      };
		gauss_rb <= {3'h0, pix[3][7:0], 1'b0} + {2'h0, pix[4][7:0], 2'b0} + {3'h0, pix[5][7:0], 1'b0};
		gauss_rc <= {4'h0, pix[6][7:0]      } + {3'h0, pix[7][7:0], 1'b0} + {4'h0, pix[8][7:0]      };
		
		gauss_r <= gauss_ra + gauss_rb + gauss_rc;
		

		gauss_ga <= {4'h0, pix[0][15:8]      } + {3'h0, pix[1][15:8], 1'b0} + {4'h0, pix[2][15:8]      };
		gauss_gb <= {3'h0, pix[3][15:8], 1'b0} + {2'h0, pix[4][15:8], 2'b0} + {3'h0, pix[5][15:8], 1'b0};
		gauss_gc <= {4'h0, pix[6][15:8]      } + {3'h0, pix[7][15:8], 1'b0} + {4'h0, pix[8][15:8]      };
		
		gauss_g <= gauss_ga + gauss_gb + gauss_gc;


		gauss_ba <= {4'h0, pix[0][23:16]      } + {3'h0, pix[1][23:16], 1'b0} + {4'h0, pix[2][23:16]      };
		gauss_bb <= {3'h0, pix[3][23:16], 1'b0} + {2'h0, pix[4][23:16], 2'b0} + {3'h0, pix[5][23:16], 1'b0};
		gauss_bc <= {4'h0, pix[6][23:16]      } + {3'h0, pix[7][23:16], 1'b0} + {4'h0, pix[8][23:16]      };
		
		gauss_b <= gauss_ba + gauss_bb + gauss_bc;
		
		

		case(blur_on)
		1'b0 : {blue_out, green_out, red_out} <= pix[4];
		1'b1 : {blue_out, green_out, red_out} <= {(gauss_b[11] ? 8'hff : gauss_b[10:3]), (gauss_g[11] ? 8'hff : gauss_g[10:3]), (gauss_r[11] ? 8'hff : gauss_r[10:3])};
		endcase

		
	end


							
endmodule
module pdp1_vga_crt (
	input 				reset_n,
	input 				clk,
	input 				CLK_50M,
	input [10:0] 		horizontal_counter,              
	input [10:0] 		vertical_counter,   
	output reg [7:0] 	red_out,                         
	output reg [7:0] 	green_out,
	output reg [7:0] 	blue_out,             
   input 				frame_odd,
	input					cpu_stall,
	output reg			cpu_vga_run,
  
	input  [9:0] 		pixel_x_i,
	input  [9:0] 		pixel_y_i,                       
	input  [2:0] 		pixel_brightness,                
	input 				variable_brightness,       
	input  				pixel_available,
	input  [1:0]		pixel_type,
	
	input 				mag_ships,
	input [2:0] 		trail_len,
	input 				blur_on,
	
	input 				clk_74a,
	input	[31:0]		bridge_addr,
	input					bridge_wr,
	input	[31:0]		bridge_wr_data
	
	
);

             
	
	wire use_debugs = 1'b0;
	



	wire [9:0] xcoord = xprod[15:6];
	wire [9:0] ycoord = yprod[15:6];
	

	wire [9:0] xmula = pixel_y;
	wire [5:0] xmulb = 6'd48;	
	wire [15:0] xprod = xmula * xmulb;
	

	wire [9:0] ymula = ~pixel_x;
	wire [5:0] ymulb = 6'd45;
	wire [15:0] yprod = ymula * ymulb;
	
	reg [1:0] pa_del;
	reg [2:0] frame_odd_d;
	reg [1:0] cpu_stall_d;
	
	
	reg [9:0] pixel_x;
	reg [9:0] pixel_y;
	reg write_fifo;
	reg [3:0] stuffstate;
	reg [3:0] ss_wait;
	reg [9:0] pixtest;
	
	reg [7:0] needlecnt;
	reg [7:0] wedgecnt;
	
	reg [39:0] w_coord;
	reg [39:0] n_coord;
	
	

	always @ (posedge CLK_50M)
	begin
	
	
		
		pa_del <= {pa_del[0], pixel_available};
		frame_odd_d <= {frame_odd_d[1:0], frame_odd};
		cpu_vga_run <= (frame_odd_d[2:1] == 2'b01);
		
		
		if (frame_odd_d[2:1] == 2'b01)
		begin
			needlecnt <= 8'h0;
			wedgecnt <= 8'h0;
		end
		else if (write_fifo)
		case (pixel_type)
		2'h1 :	begin
						needlecnt <= needlecnt + 1'b1;
						if (needlecnt == 8'h14) n_coord <= {~pixel_x, pixel_y, ycoord, xcoord};
					end
		2'h2 :	begin
						wedgecnt <= wedgecnt + 1'b1;
						if (wedgecnt == 8'h24) w_coord <= {~pixel_x, pixel_y, ycoord, xcoord};
					end
		endcase			
					
		


		if (cpu_stall_d == 2'b01)
		begin
			stuffstate <= (use_debugs ? 4'h1 : 4'h6);
			write_fifo <= 1'b0;
		end
		else if (|ss_wait)
		begin
			ss_wait <= ss_wait - 1'b1;
			write_fifo <= 1'b0;
		end
		else
		case(stuffstate)

		4'h1 :	begin
						pixel_x <= 10'h0;
						pixel_y <= 10'h0;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h2;
					end
		
		4'h2 :	begin
						pixel_x <= 10'h3ff;
						pixel_y <= 10'h0;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h3;
					end

		4'h3 :	begin
						pixel_x <= 10'h0;
						pixel_y <= 10'h3ff;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h4;
					end

		4'h4 :	begin
						pixel_x <= 10'h3ff;
						pixel_y <= 10'h3ff;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h5;
					end
					
		4'h5 :	begin
						pixel_x <= 10'h100;
						pixel_y <= pixtest;
						pixtest <= pixtest + 1'b1;
						write_fifo <= 1'b1;
						ss_wait <= 4'hf;
						stuffstate <= 4'h6;
					end
		
		4'h6 :	begin
						pixel_x <= pixel_x_i;
						pixel_y <= pixel_y_i;
						write_fifo <= (pa_del == 2'b01);
					end
		
		endcase
					

		
	end	
		
	
	wire [9:0] curr_x;
	wire [9:0] curr_y;
	wire [1:0] curr_type;
	
	reg rdreq;
	wire rdempty;
	wire wr_full;
	
	
	wire magpix = (^pixel_type) & mag_ships;
	
	fifo_video thingera (
									.wrclk	(CLK_50M),
									.data		({pixel_type & {2{mag_ships}}, (magpix ? {~pixel_x, pixel_y} : {ycoord, xcoord})}),
									.wrreq	(write_fifo & ~wr_full),
									.wrfull  (wr_full),
									
									.rdclk	(clk),
									.rdreq	(rdreq),
									.rdempty	(rdempty),
									.q			({curr_type, curr_y, curr_x})
							  );


	
	
	
	localparam numbuffs = 8'd16;
	reg [3:0] ob_buf;
	reg [3:0] ob_count;
	reg [3:0] bufcount;
	wire bufbit = vertical_counter[4];
	localparam dimline = 12'd737;
	localparam startline = 12'd12;
	localparam cv_lowbit = 'd4;
	

	reg [9:0] phos_dim;
	always
	case(trail_len[2:0])
	3'h0 : phos_dim <= 10'h3fe;
	3'h1 : phos_dim <= 10'd64;
	3'h2 : phos_dim <= 10'd32;
	3'h3 : phos_dim <= 10'd16;
	3'h4 : phos_dim <= 10'd8;
	3'h5 : phos_dim <= 10'd4;
	3'h6 : phos_dim <= 10'd2;
	3'h7 : phos_dim <= 10'd1;
	endcase
		
	localparam phos_full = 10'h3ff;
	
	wire [31:0] pa_out [numbuffs-1:0];
	wire [31:0] pb_out [numbuffs-1:0];
	reg [9:0] ramcnta;
	reg [9:0] ramcntb;
	reg pb_wren [numbuffs-1:0];
	reg [31:0] pb_in [numbuffs-1:0];
		







	
	genvar i;
	generate
		for (i = 0; i < numbuffs; i=i+1)
		begin : ramgen
			rendram rr_gen (
			.clock(clk),
			.data_a(32'h0000_0000), .address_a(ramcnta), .wren_a(1'b0), .q_a(pa_out[i]),
			.data_b(pb_in[i]), .address_b(ramcntb), .wren_b(pb_wren[i]), .q_b(pb_out[i])
			);
		end
	endgenerate
	
	
	reg [numbuffs-1:0] foundit;
	reg [9:0] minbrite [numbuffs-1:0];
	reg [9:0] mb_add [numbuffs-1:0];
	reg [3:0] state;
	reg [7:0] j;
	reg [9:0] oldestbrite;
	reg [9:0] ob_add;
	reg [9:0] ramcnta_d;
	reg pipehold;
	
	reg fifovalid;
	reg [9:0] fifo_x;
	reg [9:0] fifo_y;

	reg whichbuf;
	reg [7:0] pixout;
	reg [9:0] out_x;
	reg [9:0] out_y;
	reg pixwrite, pixwrite_d;

	reg [39:0] w_coord_d;
	reg [39:0] n_coord_d;
	
	












	
	
	

	

	wire [9:0] w_ya = (curr_y - w_coord_d[39:30]);
	wire [10:0] w_yb = ({w_ya[9], w_ya} + {1'b0, w_coord_d[19:10]});
	

	reg [9:0] w_y_fix;
	always
	case({(w_yb > 11'd719), w_yb[10]})
	2'b10 	: w_y_fix <= (w_yb[9:0] + 10'd304);
	2'b11 	: w_y_fix <= (w_yb[9:0] + 10'd720);
	default	: w_y_fix <= w_yb[9:0];
	endcase
	

	wire [9:0] w_xa = (curr_x - w_coord_d[29:20]);
	wire [10:0] w_xb = ({w_xa[9], w_xa} + {1'b0, w_coord_d[ 9: 0]});
	

	reg [9:0] w_x_fix;
	always
	case({(w_xb > 11'd767), w_xb[10]})
	2'b10 	: w_x_fix <= (w_xb[9:0] + 10'd256);
	2'b11 	: w_x_fix <= (w_xb[9:0] + 10'd768);
	default	: w_x_fix <= w_xb[9:0];
	endcase


	wire [9:0] n_ya = (curr_y - n_coord_d[39:30]);
	wire [10:0] n_yb = ({n_ya[9], n_ya} + {1'b0, n_coord_d[19:10]});
	

	reg [9:0] n_y_fix;
	always
	case({(n_yb > 11'd719), n_yb[10]})
	2'b10 	: n_y_fix <= (n_yb[9:0] + 10'd304);
	2'b11 	: n_y_fix <= (n_yb[9:0] + 10'd720);
	default	: n_y_fix <= n_yb[9:0];
	endcase
	

	wire [9:0] n_xa = (curr_x - n_coord_d[29:20]);
	wire [10:0] n_xb = ({n_xa[9], n_xa} + {1'b0, n_coord_d[ 9: 0]});
	

	reg [9:0] n_x_fix;
	always
	case({(n_xb > 11'd767), n_xb[10]})
	2'b10 	: n_x_fix <= (n_xb[9:0] + 10'd256);
	2'b11 	: n_x_fix <= (n_xb[9:0] + 10'd768);
	default	: n_x_fix <= n_xb[9:0];
	endcase
	
	always @ (posedge clk)
	begin
	
		w_coord_d <= w_coord;
		n_coord_d <= n_coord;
		
		cpu_stall_d <= {cpu_stall_d[0], cpu_stall};
		
		if (~|vertical_counter)
		begin
			state <= 4'h1;
			bufcount <= 0;
		end
		else
		case (state)

		4'h1 :	begin
						
						if (horizontal_counter == 1)
						begin
							
							whichbuf <= bufbit;
							ramcnta <= 0;
							
							fifovalid <= ~rdempty & cpu_stall_d[1];
							case(curr_type)
							2'h1 		: {fifo_y, fifo_x} <= {n_y_fix, n_x_fix};
							2'h2 		: {fifo_y, fifo_x} <= {w_y_fix, w_x_fix};
							default	: {fifo_y, fifo_x} <= {curr_y, curr_x};
							endcase
							rdreq <= ~rdempty & cpu_stall_d[1];
							
							for (j = 0; j < numbuffs; j = j + 1)
							begin
								foundit[j] <= 1'b0;
								minbrite[j] <= 10'h3ff;
							end
							
							pipehold <= 1'b1;
							state <= 4'h2;
						 
						 end
						 
					end
		


		4'h2 :	begin
						rdreq <= 1'b0;

						ramcnta_d <= ramcnta;
						ramcntb <= ramcnta_d;

						if (~pipehold)
						for (j = 0; j < numbuffs; j = j + 1)
						begin
							casex({
										(vertical_counter == dimline), (fifovalid & ({fifo_y, fifo_x} == pa_out[j][19:0])),
										((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & (j == bufcount)), pa_out[j][31:29]
									})
							

							6'b01x_x1x :	begin
													pb_in[j] <= {2'b11, phos_full, fifo_y, fifo_x};
													pb_wren[j] <= 1'b1;
													foundit[j] <= 1'b1;
												end
											

							6'b001_1xx :	begin
													pb_in[j] <= {1'b0, pa_out[j][30:0]};
													pb_wren[j] <= 1'b1;
												end
												


							6'b1xx_0x1 :	begin
													pb_in[j][31:30] <= {1'b0, pa_out[j][30]};
													pb_in[j][19:0] <= pa_out[j][19:0];
													casex({&pa_out[j][29:20], 1'b0, pa_out[j][29:20]} - {1'b0, phos_dim})
													12'b1xxx_xxxx_xxxx : pb_in[j][29:20] <= 10'h3fe;
													12'b00xx_xxxx_xxxx : pb_in[j][29:20] <= (pa_out[j][29:20] - phos_dim);
													12'b01xx_xxxx_xxxx : pb_in[j][29:20] <= 10'h0;
													endcase
													pb_wren[j] <= 1'b1;
												end
							

							6'b1xx_0x0 :	begin
													pb_in[j] <= {12'h0, 20'h0};
													pb_wren[j] <= 1'b1;
												end
							

							6'b1xx_1xx :	begin
													pb_in[j] <= {1'b0, pa_out[j][30:0]};
													pb_wren[j] <= 1'b1;
												end
							

							default :	begin
												pb_wren[j] <= 1'b0;
											end
							endcase
							

							if ((pa_out[j][29:20] < minbrite[j]) & ~pipehold)
							begin
								minbrite[j] <= pa_out[j][29:20];
								mb_add[j] <= ramcnta_d;
							end
						
						end


						pipehold <= 1'b0;
						

						{pixout, out_y, out_x} <= {pa_out[bufcount][28:21], pa_out[bufcount][19:0]};
						

						if ((vertical_counter[10:cv_lowbit] == pa_out[bufcount][19:10+cv_lowbit]) & pa_out[bufcount][29]) pixwrite <= ~pixwrite;


						ramcnta <= ramcnta + 1'b1;
						if (~|ramcnta & ~pipehold) state <= 4'h3;
					
					end
		

		4'h3 :	begin
						
						for (j = 0; j < numbuffs; j = j + 1)
						begin
							
							pb_wren[j] <= 1'b0;
						
						end
						
						casex({(vertical_counter == dimline), |foundit | ~fifovalid})
						2'b1x : state <= 4'h0;
						2'b01 : state <= 4'h1;
						2'b00 : state <= 4'h4;
						endcase
						
						oldestbrite <= 10'h3ff;
						ob_count <= 0;
						
						bufcount <= bufcount + 1'b1;
						
					end
		
		

		4'h4 :	begin
						if (minbrite[ob_count] < oldestbrite)
						begin
							oldestbrite <= minbrite[ob_count];
							ob_add <= mb_add[ob_count];
							ob_buf <= ob_count;
						end
						ob_count <= ob_count + 1'b1;
						if (&ob_count) state <= 4'h5;						
					end
		

		4'h5 :	begin
						pb_in[ob_buf] <= {2'b11, phos_full, fifo_y, fifo_x};
						ramcntb <= ob_add;
						pb_wren[ob_buf] <= 1'b1;
						state <= 4'h6;
					end


		4'h6 :	begin
						pb_wren[ob_buf] <= 1'b0;
						state <= 4'h1;
					end
		
		
		endcase

		
		
		pixwrite_d <= pixwrite;
		
		if (~whichbuf)
		begin

			buf_a_wr <= (pixwrite ^ pixwrite_d);
			buf_a_dat <= pixout;
			buf_a_add <= {out_y[cv_lowbit-1:0], out_x};

			buf_b_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd8)};
			buf_out <= buf_b_out;
		end
		else
		begin

			buf_b_wr <= (pixwrite ^ pixwrite_d);
			buf_b_dat <= pixout;
			buf_b_add <= {out_y[cv_lowbit-1:0], out_x};

			buf_a_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd8)};
			buf_out <= buf_a_out;
		end
		

		buf_c_add <= {vertical_counter[cv_lowbit-1:0], (horizontal_counter[9:0] - 10'd16)};
		buf_c_wr <= (horizontal_counter >= 11'd16);
		
	
	end
	
	

	
	reg [7:0] buf_out;
	reg [13:0] buf_c_add;
	reg buf_c_wr;
	
	reg [7:0] buf_a_dat;
	reg [13:0] buf_a_add;
	reg buf_a_wr;
	wire [7:0] buf_a_out;
	wire [7:0] buf_a_outb;
	
		
	linebuf thingerb (	.clock(clk),
								.data_a(buf_a_dat), .address_a(buf_a_add), .wren_a(buf_a_wr), .q_a(buf_a_out),
								.data_b(8'h0), .address_b(buf_c_add), .wren_b(buf_c_wr & whichbuf), .q_b(buf_a_outb)
							);
							
	reg [7:0] buf_b_dat;
	reg [13:0] buf_b_add;
	reg buf_b_wr;
	wire [7:0] buf_b_out;
	wire [7:0] buf_b_outb;
	
		
	linebuf thingerc (	.clock(clk),
								.data_a(buf_b_dat), .address_a(buf_b_add), .wren_a(buf_b_wr), .q_a(buf_b_out),
								.data_b(8'h0), .address_b(buf_c_add), .wren_b(buf_c_wr & ~whichbuf), .q_b(buf_b_outb)
							);
							
							
	

	
	wire [23:0] output_color;
	


	wire write_clut_en = bridge_wr && (bridge_addr[31:16] == 16'h1000); 

	color_lut thingerd (
		.write_clk		(clk_74a),
		.write_address	(bridge_addr[9:2]),
		.write_data		(bridge_wr_data),
		.write_enable	(write_clut_en),
		.read_clk		(clk),
		.input_index	(buf_out),
		.output_color	(output_color)
	);
							

							



	
	reg [23:0] linebufa [1023:0];
	reg [23:0] linebufb [1023:0];
	reg [23:0] linebufc [1023:0];
	
	reg [23:0] pix [8:0];
	
	wire [9:0] writeline = (horizontal_counter[9:0] - 10'd3);

	reg [11:0] gauss_ra, gauss_rb, gauss_rc, gauss_r;
	reg [11:0] gauss_ga, gauss_gb, gauss_gc, gauss_g;
	reg [11:0] gauss_ba, gauss_bb, gauss_bc, gauss_b;
	
	
	
	always @ (posedge clk)
	begin	
	




		
		
		pix[2] <= pix[1];
		pix[1] <= pix[0];
		pix[0] <= linebufa[horizontal_counter[9:0]];
		
		pix[5] <= pix[4];
		pix[4] <= pix[3];
		pix[3] <= linebufb[horizontal_counter[9:0]];
		
		pix[8] <= pix[7];
		pix[7] <= pix[6];
		pix[6] <= linebufc[horizontal_counter[9:0]];
							
		if (~horizontal_counter[10])
		begin
			
			linebufa[writeline] <= ((output_color[23] | ~blur_on) ? output_color : {1'b0, output_color[23:17], 1'b0, output_color[15:9], 1'b0, output_color[7:1]});
			linebufb[writeline] <= pix[2];
			linebufc[writeline] <= pix[5];
			
		end

		gauss_ra <= {4'h0, pix[0][7:0]      } + {3'h0, pix[1][7:0], 1'b0} + {4'h0, pix[2][7:0]      };
		gauss_rb <= {3'h0, pix[3][7:0], 1'b0} + {2'h0, pix[4][7:0], 2'b0} + {3'h0, pix[5][7:0], 1'b0};
		gauss_rc <= {4'h0, pix[6][7:0]      } + {3'h0, pix[7][7:0], 1'b0} + {4'h0, pix[8][7:0]      };
		
		gauss_r <= gauss_ra + gauss_rb + gauss_rc;
		

		gauss_ga <= {4'h0, pix[0][15:8]      } + {3'h0, pix[1][15:8], 1'b0} + {4'h0, pix[2][15:8]      };
		gauss_gb <= {3'h0, pix[3][15:8], 1'b0} + {2'h0, pix[4][15:8], 2'b0} + {3'h0, pix[5][15:8], 1'b0};
		gauss_gc <= {4'h0, pix[6][15:8]      } + {3'h0, pix[7][15:8], 1'b0} + {4'h0, pix[8][15:8]      };
		
		gauss_g <= gauss_ga + gauss_gb + gauss_gc;


		gauss_ba <= {4'h0, pix[0][23:16]      } + {3'h0, pix[1][23:16], 1'b0} + {4'h0, pix[2][23:16]      };
		gauss_bb <= {3'h0, pix[3][23:16], 1'b0} + {2'h0, pix[4][23:16], 2'b0} + {3'h0, pix[5][23:16], 1'b0};
		gauss_bc <= {4'h0, pix[6][23:16]      } + {3'h0, pix[7][23:16], 1'b0} + {4'h0, pix[8][23:16]      };
		
		gauss_b <= gauss_ba + gauss_bb + gauss_bc;
		
		

		case(blur_on)
		1'b0 : {blue_out, green_out, red_out} <= pix[4];
		1'b1 : {blue_out, green_out, red_out} <= {(gauss_b[11] ? 8'hff : gauss_b[10:3]), (gauss_g[11] ? 8'hff : gauss_g[10:3]), (gauss_r[11] ? 8'hff : gauss_r[10:3])};
		endcase

		
	end


							
endmodule