data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:17: syntax error, unexpected rand, expecting IDENTIFIER or do or final\n    wire [31:0] rand;\n                ^~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:27: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\n        .num(rand)\n             ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:41: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("prng_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:42: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, prng_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:46: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:51: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:52: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\n            $display("0x%h", rand);\n                             ^~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_tb.v:54: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n'
module prng_tb#(
    parameter PRNG_SEED = 32'hdeadbeef,
    parameter RAND_COUNT = 100000
    ) ();

    reg clk, rst, next;
    reg [31:0] seed;
    wire [31:0] rand;

    integer i;


    prng DUT (
        .clk(clk),
        .rst(rst),
        .next(next),
        .seed(seed),
        .num(rand)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("prng_tb.vcd");
        $dumpvars(0, prng_tb);

        seed = PRNG_SEED;
        next = 1'b0;
        @(negedge rst);
        @(posedge clk);

        for (i = 0; i < RAND_COUNT; i = i+1) begin
            next = 1'b1;
            @(posedge clk);
            $display("0x%h", rand);
            next = 1'b0;
            @(posedge clk);
        end

        $finish;
    end
endmodule
module prng_tb#(
    parameter PRNG_SEED = 32'hdeadbeef,
    parameter RAND_COUNT = 100000
    ) ();


    reg clk, rst, next;
    reg [31:0] seed;
    wire [31:0] rand;

    integer i;


    prng DUT (
        .clk(clk),
        .rst(rst),
        .next(next),
        .seed(seed),
        .num(rand)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("prng_tb.vcd");
        $dumpvars(0, prng_tb);

        seed = PRNG_SEED;
        next = 1'b0;
        @(negedge rst);
        @(posedge clk);

        for (i = 0; i < RAND_COUNT; i = i+1) begin
            next = 1'b1;
            @(posedge clk);
            $display("0x%h", rand);
            next = 1'b0;
            @(posedge clk);
        end

        $finish;
    end
endmodule