data/full_repos/permissive/418819021/lab-06/test_sbi.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:12: Define or directive not defined: \'`STAGE_IF\'\n            `STAGE_IF :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:12: syntax error, unexpected \':\', expecting endcase\n            `STAGE_IF :\n                      ^\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:14: Define or directive not defined: \'`STAGE_ID\'\n            `STAGE_ID :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:15: Define or directive not defined: \'`TYPE_SBI\'\n            if (!(uut.control.opcode_type === `TYPE_SBI)) begin\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:21: Define or directive not defined: \'`TYPE_SBI\'\n                    `TYPE_SBI,\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:21: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                    `TYPE_SBI,\n                             ^\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:31: syntax error, unexpected end\n            end else if (!(uut.control.opcode_imd === io_addr)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:39: syntax error, unexpected end\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:39: Define or directive not defined: \'`GROUP_IO_READ\'\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:45: syntax error, unexpected end\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:45: Define or directive not defined: \'`GROUP_IO_READ\'\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:52: syntax error, unexpected end\n            end else if(!(uut.control.opcode_group[`GROUP_ALU_AUX])) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:52: Define or directive not defined: \'`GROUP_ALU_AUX\'\n            end else if(!(uut.control.opcode_group[`GROUP_ALU_AUX])) begin\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:57: syntax error, unexpected end\n            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:65: syntax error, unexpected end\n            end else if (!(uut.control.alu_rr == uut.control.bus_data)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:71: syntax error, unexpected end\n            end else begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:74: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:75: Define or directive not defined: \'`STAGE_EX\'\n            `STAGE_EX :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:76: Define or directive not defined: \'`CONTROL_IO_WRITE\'\n            if (!uut.control.signals[`CONTROL_IO_WRITE]) begin\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:82: syntax error, unexpected end\n            end else if (!uut.control.alu_enable) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:88: syntax error, unexpected end\n            end else if (!(uut.control.alu_rd == (1 << bit_val))) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:94: syntax error, unexpected end\n            end else begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:97: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:98: Define or directive not defined: \'`STAGE_MEM\'\n            `STAGE_MEM : TEST_SBI = 1\'b1;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_sbi.vh:99: Define or directive not defined: \'`STAGE_WB\'\n            `STAGE_WB  : TEST_SBI = 1\'b1;\n            ^~~~~~~~~\n%Error: Cannot continue\n'
function TEST_SBI;
    input integer io_addr;
    input integer bit_val;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF :
            TEST_SBI = 1'b1;
            `STAGE_ID :
            if (!(uut.control.opcode_type === `TYPE_SBI)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_type: %d vs %d",

                    io_addr,
                    bit_val,
                    `TYPE_SBI,
                    uut.control.opcode_type);
            end else if (!(uut.control.opcode_bit === bit_val)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_bit: %d vs %d",

                    io_addr,
                    bit_val,
                    bit_val,
                    uut.control.opcode_bit);
            end else if (!(uut.control.opcode_imd === io_addr)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_imd: %d vs %d",

                    io_addr,
                    bit_val,
                    io_addr,
                    uut.control.opcode_imd);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_IO_READ",

                    io_addr,
                    bit_val);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_IO_READ",

                    io_addr,
                    bit_val);

            end else if(!(uut.control.opcode_group[`GROUP_ALU_AUX])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_ALU_AUX",
                    io_addr,
                    bit_val);
            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED, check bus_addr in bus_interface_unit.v: %d vs %d",

                    io_addr,
                    bit_val,
                    io_addr,
                    uut.control.bus_int.bus_addr);
            end else if (!(uut.control.alu_rr == uut.control.bus_data)) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_rr should have other value for SBI instruction",

                    io_addr,
                    bit_val);
            end else begin
                TEST_SBI = 1'b1;
                $display("SBI R%2d, %d - ID: OK", io_addr, bit_val);
            end
            `STAGE_EX :
            if (!uut.control.signals[`CONTROL_IO_WRITE]) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal CONTROL_IO_WRITE should be active for SBI instruction",

                    io_addr,
                    bit_val);
            end else if (!uut.control.alu_enable) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_enable should be active for SBI instruction",

                    io_addr,
                    bit_val);
            end else if (!(uut.control.alu_rd == (1 << bit_val))) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_rd should have other value for SBI instruction",

                    io_addr,
                    bit_val);
            end else begin
                TEST_SBI = 1'b1;
                $display("SBI R%2d, %d - EX: OK", io_addr, bit_val);
            end
            `STAGE_MEM : TEST_SBI = 1'b1;
            `STAGE_WB  : TEST_SBI = 1'b1;

        endcase
    end

endfunction
function TEST_SBI;

    input integer io_addr;
    input integer bit_val;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF :
            TEST_SBI = 1'b1;
            `STAGE_ID :
            if (!(uut.control.opcode_type === `TYPE_SBI)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_type: %d vs %d",

                    io_addr,
                    bit_val,
                    `TYPE_SBI,
                    uut.control.opcode_type);
            end else if (!(uut.control.opcode_bit === bit_val)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_bit: %d vs %d",

                    io_addr,
                    bit_val,
                    bit_val,
                    uut.control.opcode_bit);
            end else if (!(uut.control.opcode_imd === io_addr)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d - ID: FAILED, check opcode_imd: %d vs %d",

                    io_addr,
                    bit_val,
                    io_addr,
                    uut.control.opcode_imd);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_IO_READ",

                    io_addr,
                    bit_val);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_IO_READ",

                    io_addr,
                    bit_val);

            end else if(!(uut.control.opcode_group[`GROUP_ALU_AUX])) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED - SBI instruction should be in GROUP_ALU_AUX",
                    io_addr,
                    bit_val);
            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin
                TEST_SBI = 1'bx;
                $display("SBI %d,R%2d, - ID: FAILED, check bus_addr in bus_interface_unit.v: %d vs %d",

                    io_addr,
                    bit_val,
                    io_addr,
                    uut.control.bus_int.bus_addr);
            end else if (!(uut.control.alu_rr == uut.control.bus_data)) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_rr should have other value for SBI instruction",

                    io_addr,
                    bit_val);
            end else begin
                TEST_SBI = 1'b1;
                $display("SBI R%2d, %d - ID: OK", io_addr, bit_val);
            end
            `STAGE_EX :
            if (!uut.control.signals[`CONTROL_IO_WRITE]) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal CONTROL_IO_WRITE should be active for SBI instruction",

                    io_addr,
                    bit_val);
            end else if (!uut.control.alu_enable) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_enable should be active for SBI instruction",

                    io_addr,
                    bit_val);
            end else if (!(uut.control.alu_rd == (1 << bit_val))) begin
                TEST_SBI = 1'bx;
                $display("SBI R%2d, %d - ID: FAILED, signal alu_rd should have other value for SBI instruction",

                    io_addr,
                    bit_val);
            end else begin
                TEST_SBI = 1'b1;
                $display("SBI R%2d, %d - EX: OK", io_addr, bit_val);
            end
            `STAGE_MEM : TEST_SBI = 1'b1;
            `STAGE_WB  : TEST_SBI = 1'b1;

        endcase
    end

endfunction