data/full_repos/permissive/461141714/src/Single Cycle CPU/Controll.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/Controll.v\n%Error: Exiting due to 4 error(s)\n'
module ControlUnit(
    input [3:0] opcode,
    input [5:0] func,
    output reg isR,
    output reg [5:0] aluFunc,
    output reg isADI,
    output reg isLHI,
    output reg isJMP,
    output reg isOUT,
    output reg regWrite
    );
    
    always @(*) begin

        isR = 0;
        aluFunc = 6'b0;
        isADI = 0;
        isLHI = 0;
        isJMP = 0;
        isOUT = 0;
        regWrite = 0;
        

        if(opcode == `OPCODE_R && func != `FUNC_WWD) begin
            isR = 1'b1;
            aluFunc = func[3:0];
            regWrite = 1;
        end
        else if (opcode == `OPCODE_ADI) begin
            aluFunc = `FUNC_ADD;
            isADI = 1;
            regWrite = 1;
        end
        else if (opcode == `OPCODE_LHI) begin
            isLHI = 1;
            regWrite = 1;
        end
        else if (opcode == `OPCODE_JMP) begin
            isJMP = 1;
        end
        else if (opcode == `OPCODE_R && func == `FUNC_WWD) begin
            isOUT = 1;
        end
    end
    
    
endmodule
module ControlUnit(
    input [3:0] opcode,
    input [5:0] func,
    output reg isR,
    output reg [5:0] aluFunc,
    output reg isADI,
    output reg isLHI,
    output reg isJMP,
    output reg isOUT,
    output reg regWrite
    );

    
    always @(*) begin

        isR = 0;
        aluFunc = 6'b0;
        isADI = 0;
        isLHI = 0;
        isJMP = 0;
        isOUT = 0;
        regWrite = 0;
        

        if(opcode == `OPCODE_R && func != `FUNC_WWD) begin
            isR = 1'b1;
            aluFunc = func[3:0];
            regWrite = 1;
        end
        else if (opcode == `OPCODE_ADI) begin
            aluFunc = `FUNC_ADD;
            isADI = 1;
            regWrite = 1;
        end
        else if (opcode == `OPCODE_LHI) begin
            isLHI = 1;
            regWrite = 1;
        end
        else if (opcode == `OPCODE_JMP) begin
            isJMP = 1;
        end
        else if (opcode == `OPCODE_R && func == `FUNC_WWD) begin
            isOUT = 1;
        end
    end
    
    
endmodule