data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:63: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                              : ... In instance uart_rx\n            if (cycle_cnt == CYCLE - 1)  \n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:68: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                              : ... In instance uart_rx\n            if (cycle_cnt == CYCLE - 1 && bit_cnt == 3\'d7)   \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:73: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                              : ... In instance uart_rx\n            if (cycle_cnt == CYCLE / 2 - 1)  \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:108: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                               : ... In instance uart_rx\n        if (cycle_cnt == CYCLE - 1)\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:120: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                               : ... In instance uart_rx\n    else if ((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/514467334/project/ConvKing/source/Uart/uart_rx.v:129: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cycle_cnt\' generates 16 bits.\n                                                                                               : ... In instance uart_rx\n    else if (state == S_REC_BYTE && cycle_cnt == CYCLE / 2 - 1)\n                                              ^~\n%Error: Exiting due to 6 warning(s)\n'
module uart_rx
       #(
           parameter CLK_FRE = 50,
           parameter BAUD_RATE = 115200
       )
       (
           input clk,
           input rst_n,
           output reg[7: 0] rx_data,
           output reg rx_data_valid,
           input rx_data_ready,
           input rx_pin
       );

localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;

localparam S_IDLE = 1;
localparam S_START = 2;
localparam S_REC_BYTE = 3;
localparam S_STOP = 4;
localparam S_DATA = 5;

reg[2: 0] state;
reg[2: 0] next_state;
reg rx_d0;
reg rx_d1;
wire rx_negedge;
reg[7: 0] rx_bits;
reg[15: 0] cycle_cnt;
reg[2: 0] bit_cnt;

assign rx_negedge = rx_d1 && ~rx_d0;

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        rx_d0 <= 1'b0;
        rx_d1 <= 1'b0;
    end
    else begin
        rx_d0 <= rx_pin;
        rx_d1 <= rx_d0;
    end
end


always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        state <= S_IDLE;
    else
        state <= next_state;
end

always@( * ) begin
    case (state)
        S_IDLE:
            if (rx_negedge)
                next_state <= S_START;
            else
                next_state <= S_IDLE;
        S_START:
            if (cycle_cnt == CYCLE - 1)
                next_state <= S_REC_BYTE;
            else
                next_state <= S_START;
        S_REC_BYTE:
            if (cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
                next_state <= S_STOP;
            else
                next_state <= S_REC_BYTE;
        S_STOP:
            if (cycle_cnt == CYCLE / 2 - 1)
                next_state <= S_DATA;
            else
                next_state <= S_STOP;
        S_DATA:
            if (rx_data_ready)
                next_state <= S_IDLE;
            else
                next_state <= S_DATA;
        default:
            next_state <= S_IDLE;
    endcase
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_data_valid <= 1'b0;
    else if (state == S_STOP && next_state != state)
        rx_data_valid <= 1'b1;
    else if (state == S_DATA && rx_data_ready)
        rx_data_valid <= 1'b0;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_data <= 8'd0;
    else if (state == S_STOP && next_state != state)
        rx_data <= rx_bits;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        bit_cnt <= 3'd0;
    end
    else if (state == S_REC_BYTE)
        if (cycle_cnt == CYCLE - 1)
            bit_cnt <= bit_cnt + 3'd1;
        else
            bit_cnt <= bit_cnt;
    else
        bit_cnt <= 3'd0;
end


always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        cycle_cnt <= 16'd0;
    else if ((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
        cycle_cnt <= 16'd0;
    else
        cycle_cnt <= cycle_cnt + 16'd1;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_bits <= 8'd0;
    else if (state == S_REC_BYTE && cycle_cnt == CYCLE / 2 - 1)
        rx_bits[bit_cnt] <= rx_pin;
    else
        rx_bits <= rx_bits;
end
endmodule
module uart_rx
       #(
           parameter CLK_FRE = 50,
           parameter BAUD_RATE = 115200
       )
       (
           input clk,
           input rst_n,
           output reg[7: 0] rx_data,
           output reg rx_data_valid,
           input rx_data_ready,
           input rx_pin
       );


localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;

localparam S_IDLE = 1;
localparam S_START = 2;
localparam S_REC_BYTE = 3;
localparam S_STOP = 4;
localparam S_DATA = 5;

reg[2: 0] state;
reg[2: 0] next_state;
reg rx_d0;
reg rx_d1;
wire rx_negedge;
reg[7: 0] rx_bits;
reg[15: 0] cycle_cnt;
reg[2: 0] bit_cnt;

assign rx_negedge = rx_d1 && ~rx_d0;

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        rx_d0 <= 1'b0;
        rx_d1 <= 1'b0;
    end
    else begin
        rx_d0 <= rx_pin;
        rx_d1 <= rx_d0;
    end
end


always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        state <= S_IDLE;
    else
        state <= next_state;
end

always@( * ) begin
    case (state)
        S_IDLE:
            if (rx_negedge)
                next_state <= S_START;
            else
                next_state <= S_IDLE;
        S_START:
            if (cycle_cnt == CYCLE - 1)
                next_state <= S_REC_BYTE;
            else
                next_state <= S_START;
        S_REC_BYTE:
            if (cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
                next_state <= S_STOP;
            else
                next_state <= S_REC_BYTE;
        S_STOP:
            if (cycle_cnt == CYCLE / 2 - 1)
                next_state <= S_DATA;
            else
                next_state <= S_STOP;
        S_DATA:
            if (rx_data_ready)
                next_state <= S_IDLE;
            else
                next_state <= S_DATA;
        default:
            next_state <= S_IDLE;
    endcase
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_data_valid <= 1'b0;
    else if (state == S_STOP && next_state != state)
        rx_data_valid <= 1'b1;
    else if (state == S_DATA && rx_data_ready)
        rx_data_valid <= 1'b0;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_data <= 8'd0;
    else if (state == S_STOP && next_state != state)
        rx_data <= rx_bits;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        bit_cnt <= 3'd0;
    end
    else if (state == S_REC_BYTE)
        if (cycle_cnt == CYCLE - 1)
            bit_cnt <= bit_cnt + 3'd1;
        else
            bit_cnt <= bit_cnt;
    else
        bit_cnt <= 3'd0;
end


always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        cycle_cnt <= 16'd0;
    else if ((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
        cycle_cnt <= 16'd0;
    else
        cycle_cnt <= cycle_cnt + 16'd1;
end

always@(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0)
        rx_bits <= 8'd0;
    else if (state == S_REC_BYTE && cycle_cnt == CYCLE / 2 - 1)
        rx_bits[bit_cnt] <= rx_pin;
    else
        rx_bits <= rx_bits;
end
endmodule