data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/timestamp_pad_proc.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/timestamp_pad_proc.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/timestamp_pad_proc.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module timestamp_pad_proc
#(
   parameter   TS_POSITION_WIDTH       = 8,
   parameter   C_M_AXIS_TDATA_WIDTH    = 256,
   parameter   C_S_AXIS_TDATA_WIDTH    = 256
)
(
   input                                              axi_aclk,
   input                                              axi_resetn,

   input       [63:0]                                 ref_counter,
   input                                              ts_valid,
   input       [TS_POSITION_WIDTH-1:0]                slave_ts_position,
   input       [TS_POSITION_WIDTH-1:0]                master_ts_position,

   input       [C_S_AXIS_TDATA_WIDTH-1:0]             s_axis_tdata,
   input                                              s_axis_tvalid,
   input                                              s_axis_tready,
   input                                              s_axis_tlast,

   output      [C_S_AXIS_TDATA_WIDTH-1:0]             s_axis_tdata_ts_pad,

   input       [C_M_AXIS_TDATA_WIDTH-1:0]             m_axis_tdata,
   input                                              m_axis_tvalid,
   input                                              m_axis_tready,
   input                                              m_axis_tlast,

   output      [C_M_AXIS_TDATA_WIDTH-1:0]             m_axis_tdata_ts_pad
);


reg   [7:0] slave_pkt_word_cnt, master_pkt_word_cnt;

always @(posedge axi_aclk)
 if (~axi_resetn)
    slave_pkt_word_cnt  <= 0;
 else if (s_axis_tlast & s_axis_tvalid & s_axis_tready)
    slave_pkt_word_cnt  <= 0;
 else if (s_axis_tvalid & s_axis_tready)
    slave_pkt_word_cnt  <= slave_pkt_word_cnt + 1;

assign s_axis_tdata_ts_pad = (ts_valid && (slave_ts_position[7:0] == slave_pkt_word_cnt)) ? ref_counter : s_axis_tdata;


always @(posedge axi_aclk)
 if (~axi_resetn)
    master_pkt_word_cnt <= 0;
 else if (m_axis_tlast & m_axis_tvalid & m_axis_tready)
    master_pkt_word_cnt <= 0;
 else if (m_axis_tvalid & m_axis_tready)
    master_pkt_word_cnt <= master_pkt_word_cnt + 1;

assign m_axis_tdata_ts_pad = (ts_valid && (master_ts_position[7:0] == master_pkt_word_cnt)) ? ref_counter : m_axis_tdata;

endmodule
module timestamp_pad_proc
#(
   parameter   TS_POSITION_WIDTH       = 8,
   parameter   C_M_AXIS_TDATA_WIDTH    = 256,
   parameter   C_S_AXIS_TDATA_WIDTH    = 256
)
(
   input                                              axi_aclk,
   input                                              axi_resetn,

   input       [63:0]                                 ref_counter,
   input                                              ts_valid,
   input       [TS_POSITION_WIDTH-1:0]                slave_ts_position,
   input       [TS_POSITION_WIDTH-1:0]                master_ts_position,

   input       [C_S_AXIS_TDATA_WIDTH-1:0]             s_axis_tdata,
   input                                              s_axis_tvalid,
   input                                              s_axis_tready,
   input                                              s_axis_tlast,

   output      [C_S_AXIS_TDATA_WIDTH-1:0]             s_axis_tdata_ts_pad,

   input       [C_M_AXIS_TDATA_WIDTH-1:0]             m_axis_tdata,
   input                                              m_axis_tvalid,
   input                                              m_axis_tready,
   input                                              m_axis_tlast,

   output      [C_M_AXIS_TDATA_WIDTH-1:0]             m_axis_tdata_ts_pad
);



reg   [7:0] slave_pkt_word_cnt, master_pkt_word_cnt;

always @(posedge axi_aclk)
 if (~axi_resetn)
    slave_pkt_word_cnt  <= 0;
 else if (s_axis_tlast & s_axis_tvalid & s_axis_tready)
    slave_pkt_word_cnt  <= 0;
 else if (s_axis_tvalid & s_axis_tready)
    slave_pkt_word_cnt  <= slave_pkt_word_cnt + 1;

assign s_axis_tdata_ts_pad = (ts_valid && (slave_ts_position[7:0] == slave_pkt_word_cnt)) ? ref_counter : s_axis_tdata;


always @(posedge axi_aclk)
 if (~axi_resetn)
    master_pkt_word_cnt <= 0;
 else if (m_axis_tlast & m_axis_tvalid & m_axis_tready)
    master_pkt_word_cnt <= 0;
 else if (m_axis_tvalid & m_axis_tready)
    master_pkt_word_cnt <= master_pkt_word_cnt + 1;

assign m_axis_tdata_ts_pad = (ts_valid && (master_ts_position[7:0] == master_pkt_word_cnt)) ? ref_counter : m_axis_tdata;

endmodule