data/full_repos/permissive/41404488/verilog/snes_hook.v
1: b'%Error: data/full_repos/permissive/41404488/verilog/snes_hook.v:84: Cannot find file containing module: \'snes_bus_sync\'\n snes_bus_sync bus_sync (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/41404488/verilog,data/full_repos/permissive/41404488/snes_bus_sync\n             data/full_repos/permissive/41404488/verilog,data/full_repos/permissive/41404488/snes_bus_sync.v\n             data/full_repos/permissive/41404488/verilog,data/full_repos/permissive/41404488/snes_bus_sync.sv\n             snes_bus_sync\n             snes_bus_sync.v\n             snes_bus_sync.sv\n             obj_dir/snes_bus_sync\n             obj_dir/snes_bus_sync.v\n             obj_dir/snes_bus_sync.sv\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_hook.v:103: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                           : ... In instance snes_hook\n   delay_write  <= 3\'b111;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module snes_hook (
	input                clk,
	input                rst_n,
	input [7:0]          addr,
	inout [7:0]          data,
	input                PARD_n,
	input                PAWR_n,
	input                USB_RXFn,
	input                USB_TXEn,
	output reg           USB_RDn,
	output reg           USB_WRn,
	input                USB_BIT0,
	input                USB_BIT1,
	output reg           ROM_oe_n,
	output               ROM_wr_n,	
	output reg [3:0]     glitch_force
);

   
	

	reg       data_enable;
	wire      bus_latch;
	reg       bus_latch_r1;
	reg [7:0] data_out;
	reg [7:0] hist;
	reg punch;
	reg [3:0] delay_write;
	wire usb_active;
	

	reg [2:0] HOOK_STATE;
	parameter ST_INIT                 = 3'h0;
	parameter ST_RST_FOUND            = 3'h1;
	parameter ST_SCAN_1               = 3'h2;
	parameter ST_SCAN_2               = 3'h3;
	parameter ST_SCAN_3               = 3'h4;
	parameter ST_IRQ_1                = 3'h5;
	parameter ST_IRQ_2                = 3'h6;


   assign ROM_wr_n = 1;
	assign data = (punch) ? data_out : 8'hZZ;
	assign usb_active = (~USB_BIT0 & USB_BIT1) ? 1'b1 : 1'b0;
	
	snes_bus_sync bus_sync (
		.clk(clk),
		.rst_n(rst_n),
		.PA(addr),
		.event_latch(bus_latch)
	);









	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			HOOK_STATE   <= ST_INIT;
			bus_latch_r1 <= 1'b0;
			delay_write  <= 3'b111;
		end else begin
		   bus_latch_r1 <= bus_latch;
			
			delay_write[3]   <= (PARD_n && (HOOK_STATE != ST_INIT) && (HOOK_STATE != ST_RST_FOUND)) ? PAWR_n : 1'b1;
			delay_write[2:0] <= delay_write[3:1];
		
			if (bus_latch_r1 == 0 && bus_latch == 1) begin
				hist <= addr;
				case (HOOK_STATE)


					ST_INIT: begin
						if (addr == 8'hFC) begin
							if (usb_active) HOOK_STATE <= ST_RST_FOUND;
							else HOOK_STATE <= ST_SCAN_1;
						end
					end				
					ST_RST_FOUND: begin
						if (~punch) begin
							HOOK_STATE <= ST_SCAN_1;
						end
					end				
					ST_SCAN_1: begin

						HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_SCAN_2: begin
						if (addr == (hist-1)) HOOK_STATE <= ST_SCAN_3;
						else HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_SCAN_3: begin
						if (addr == (hist-1)) HOOK_STATE <= ST_IRQ_1;
						else HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_IRQ_1: begin
						HOOK_STATE <= ST_IRQ_2;
						if (~punch) HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_IRQ_2: begin
						if (~punch) HOOK_STATE <= ST_SCAN_1;
					end
				endcase
			end

			
		end 
	end
	
	
	
	always @(*) begin
		USB_RDn = 1;
		USB_WRn = 1;
		ROM_oe_n = 1;
		data_out = 0;
		punch = 0;
		glitch_force = 4'bZZZZ;
		if ((HOOK_STATE == ST_INIT || HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFC)) begin
			punch = 1;
			data_out = 8'h84;
			glitch_force[2] = 1'b1;
			glitch_force[0] = 1'b1;
		end
		if ((HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFD)) begin
		   punch = 1;
			data_out = 8'h21;
			glitch_force[3] = 1'b1;
			glitch_force[1] = 1'b1;
		end
		if ((HOOK_STATE == ST_IRQ_2 || HOOK_STATE == ST_IRQ_1) && (addr == 8'hEA)) begin
			punch = 1;
			data_out = 8'h84;
			glitch_force[2] = 1'b1;
			glitch_force[0] = 1'b1;
		end
		if ((HOOK_STATE == ST_IRQ_2) && (addr == 8'hEB)) begin
			punch = 1;
			data_out = 8'h21;
			glitch_force[3] = 1'b1;
			glitch_force[1] = 1'b1;
		end
		
		if (addr == 8'hFE && ~PARD_n) begin
			punch = 1;
			if (usb_active) data_out = {~USB_RXFn,~USB_TXEn,1'b1,5'b00000};
			else data_out = 8'b00000000;
		end
		else if (addr == 8'hFF && ~PARD_n) begin
			USB_RDn = 0;
		end
		else if (addr == 8'hFF && ~PAWR_n) begin
			USB_WRn = |delay_write[1:0];
		end
		else if (addr[7] && |addr[6:2] && ~PARD_n) begin
			ROM_oe_n = 0;
		end
	end

	

endmodule
module snes_hook (
	input                clk,
	input                rst_n,
	input [7:0]          addr,
	inout [7:0]          data,
	input                PARD_n,
	input                PAWR_n,
	input                USB_RXFn,
	input                USB_TXEn,
	output reg           USB_RDn,
	output reg           USB_WRn,
	input                USB_BIT0,
	input                USB_BIT1,
	output reg           ROM_oe_n,
	output               ROM_wr_n,	
	output reg [3:0]     glitch_force
);


   
	

	reg       data_enable;
	wire      bus_latch;
	reg       bus_latch_r1;
	reg [7:0] data_out;
	reg [7:0] hist;
	reg punch;
	reg [3:0] delay_write;
	wire usb_active;
	

	reg [2:0] HOOK_STATE;
	parameter ST_INIT                 = 3'h0;
	parameter ST_RST_FOUND            = 3'h1;
	parameter ST_SCAN_1               = 3'h2;
	parameter ST_SCAN_2               = 3'h3;
	parameter ST_SCAN_3               = 3'h4;
	parameter ST_IRQ_1                = 3'h5;
	parameter ST_IRQ_2                = 3'h6;


   assign ROM_wr_n = 1;
	assign data = (punch) ? data_out : 8'hZZ;
	assign usb_active = (~USB_BIT0 & USB_BIT1) ? 1'b1 : 1'b0;
	
	snes_bus_sync bus_sync (
		.clk(clk),
		.rst_n(rst_n),
		.PA(addr),
		.event_latch(bus_latch)
	);









	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			HOOK_STATE   <= ST_INIT;
			bus_latch_r1 <= 1'b0;
			delay_write  <= 3'b111;
		end else begin
		   bus_latch_r1 <= bus_latch;
			
			delay_write[3]   <= (PARD_n && (HOOK_STATE != ST_INIT) && (HOOK_STATE != ST_RST_FOUND)) ? PAWR_n : 1'b1;
			delay_write[2:0] <= delay_write[3:1];
		
			if (bus_latch_r1 == 0 && bus_latch == 1) begin
				hist <= addr;
				case (HOOK_STATE)


					ST_INIT: begin
						if (addr == 8'hFC) begin
							if (usb_active) HOOK_STATE <= ST_RST_FOUND;
							else HOOK_STATE <= ST_SCAN_1;
						end
					end				
					ST_RST_FOUND: begin
						if (~punch) begin
							HOOK_STATE <= ST_SCAN_1;
						end
					end				
					ST_SCAN_1: begin

						HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_SCAN_2: begin
						if (addr == (hist-1)) HOOK_STATE <= ST_SCAN_3;
						else HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_SCAN_3: begin
						if (addr == (hist-1)) HOOK_STATE <= ST_IRQ_1;
						else HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_IRQ_1: begin
						HOOK_STATE <= ST_IRQ_2;
						if (~punch) HOOK_STATE <= ST_SCAN_1;
					end
					
					ST_IRQ_2: begin
						if (~punch) HOOK_STATE <= ST_SCAN_1;
					end
				endcase
			end

			
		end 
	end
	
	
	
	always @(*) begin
		USB_RDn = 1;
		USB_WRn = 1;
		ROM_oe_n = 1;
		data_out = 0;
		punch = 0;
		glitch_force = 4'bZZZZ;
		if ((HOOK_STATE == ST_INIT || HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFC)) begin
			punch = 1;
			data_out = 8'h84;
			glitch_force[2] = 1'b1;
			glitch_force[0] = 1'b1;
		end
		if ((HOOK_STATE == ST_RST_FOUND) && (addr == 8'hFD)) begin
		   punch = 1;
			data_out = 8'h21;
			glitch_force[3] = 1'b1;
			glitch_force[1] = 1'b1;
		end
		if ((HOOK_STATE == ST_IRQ_2 || HOOK_STATE == ST_IRQ_1) && (addr == 8'hEA)) begin
			punch = 1;
			data_out = 8'h84;
			glitch_force[2] = 1'b1;
			glitch_force[0] = 1'b1;
		end
		if ((HOOK_STATE == ST_IRQ_2) && (addr == 8'hEB)) begin
			punch = 1;
			data_out = 8'h21;
			glitch_force[3] = 1'b1;
			glitch_force[1] = 1'b1;
		end
		
		if (addr == 8'hFE && ~PARD_n) begin
			punch = 1;
			if (usb_active) data_out = {~USB_RXFn,~USB_TXEn,1'b1,5'b00000};
			else data_out = 8'b00000000;
		end
		else if (addr == 8'hFF && ~PARD_n) begin
			USB_RDn = 0;
		end
		else if (addr == 8'hFF && ~PAWR_n) begin
			USB_WRn = |delay_write[1:0];
		end
		else if (addr[7] && |addr[6:2] && ~PARD_n) begin
			ROM_oe_n = 0;
		end
	end

	

endmodule