data/full_repos/permissive/467394306/rtl/esp/BRAM_2048x8.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/esp/BRAM_2048x8.sv:29: Unsupported: Ignoring delay on this delayed statement.\n        #5 A0_tmp = A0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/rtl/esp/BRAM_2048x8.sv:42: Cannot find file containing module: \'RAMB16_S9_S9\'\n    RAMB16_S9_S9 bram (\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/467394306/rtl/esp,data/full_repos/permissive/467394306/RAMB16_S9_S9\n             data/full_repos/permissive/467394306/rtl/esp,data/full_repos/permissive/467394306/RAMB16_S9_S9.v\n             data/full_repos/permissive/467394306/rtl/esp,data/full_repos/permissive/467394306/RAMB16_S9_S9.sv\n             RAMB16_S9_S9\n             RAMB16_S9_S9.v\n             RAMB16_S9_S9.sv\n             obj_dir/RAMB16_S9_S9\n             obj_dir/RAMB16_S9_S9.v\n             obj_dir/RAMB16_S9_S9.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BRAM_2048x8( CLK, A0, D0, Q0, WE0, WEM0, CE0, A1, D1, Q1, WE1, WEM1, CE1 );
    input CLK;
    input [10:0] A0;
    input [7:0] D0;
    output [7:0] Q0;
    input WE0;
    input [7:0] WEM0;
    input CE0;
    input [10:0] A1;
    input [7:0] D1;
    output [7:0] Q1;
    input WE1;
    input [7:0] WEM1;
    input CE1;

    reg 	    CE0_tmp;
    reg 	    CE1_tmp;
    reg [10:0]  A0_tmp;
    reg [10:0]  A1_tmp;
    reg 	    WE0_tmp;
    reg 	    WE1_tmp;
    reg [7:0]   D0_tmp;
    reg [7:0]   D1_tmp;

    always @(*)
    begin
        #5 A0_tmp = A0;
        A1_tmp = A1;
        CE0_tmp = CE0;
        CE1_tmp = CE1;
        WE0_tmp = WE0;
        WE1_tmp = WE1;
        D0_tmp = D0;
        D1_tmp = D1;
    end
    
    wire DOPA_float;
    wire DOPB_float;

    RAMB16_S9_S9 bram (
        .DOA(Q0),
        .DOB(Q1),
        .DOPA(DOPA_float),
        .DOPB(DOPB_float),
        .ADDRA(A0_tmp),
        .ADDRB(A1_tmp),
        .CLKA(CLK),
        .CLKB(CLK),
        .DIA(D0_tmp),
        .DIB(D1_tmp),
        .DIPA(1'b0),
        .DIPB(1'b0),
        .ENA(CE0_tmp),
        .ENB(CE1_tmp),
        .SSRA(1'b0),
        .SSRB(1'b0),
        .WEA(WE0_tmp),
        .WEB(WE1_tmp));
endmodule
module BRAM_2048x8( CLK, A0, D0, Q0, WE0, WEM0, CE0, A1, D1, Q1, WE1, WEM1, CE1 );

    input CLK;
    input [10:0] A0;
    input [7:0] D0;
    output [7:0] Q0;
    input WE0;
    input [7:0] WEM0;
    input CE0;
    input [10:0] A1;
    input [7:0] D1;
    output [7:0] Q1;
    input WE1;
    input [7:0] WEM1;
    input CE1;

    reg 	    CE0_tmp;
    reg 	    CE1_tmp;
    reg [10:0]  A0_tmp;
    reg [10:0]  A1_tmp;
    reg 	    WE0_tmp;
    reg 	    WE1_tmp;
    reg [7:0]   D0_tmp;
    reg [7:0]   D1_tmp;

    always @(*)
    begin
        #5 A0_tmp = A0;
        A1_tmp = A1;
        CE0_tmp = CE0;
        CE1_tmp = CE1;
        WE0_tmp = WE0;
        WE1_tmp = WE1;
        D0_tmp = D0;
        D1_tmp = D1;
    end
    
    wire DOPA_float;
    wire DOPB_float;

    RAMB16_S9_S9 bram (
        .DOA(Q0),
        .DOB(Q1),
        .DOPA(DOPA_float),
        .DOPB(DOPB_float),
        .ADDRA(A0_tmp),
        .ADDRB(A1_tmp),
        .CLKA(CLK),
        .CLKB(CLK),
        .DIA(D0_tmp),
        .DIB(D1_tmp),
        .DIPA(1'b0),
        .DIPB(1'b0),
        .ENA(CE0_tmp),
        .ENB(CE1_tmp),
        .SSRA(1'b0),
        .SSRB(1'b0),
        .WEA(WE0_tmp),
        .WEB(WE1_tmp));
endmodule