data/full_repos/permissive/479997390/src/FullAdder32Bits.v
data/verilator_xmls/2371e7e6-6257-4ed9-bbf6-096a2072327e.xml
module oneBitALUForMSB (
    a, b, carryIn, Operation, Ainvert, Binvert, Less, Result, Set, Overflow
);
    input a, b, carryIn, Less, Ainvert, Binvert;
    input [1:0] Operation;
    output Result, Set, Overflow;
    reg Result;
    wire tempA, tempB, Set, tempResultForAdder, rresult, carryOut;

    assign tempA = (Ainvert == 1) ? ~a : a;
    assign tempB = (Binvert == 1) ? ~b : b;
    assign Overflow = carryIn ^ carryOut;
    assign Set = tempResultForAdder;

    always @(tempA, tempB, tempResultForAdder, Less, Operation) begin
        case (Operation)
            2'b00: Result = tempA & tempB;
            2'b01: Result = tempA | tempB;
            2'b10: Result = tempResultForAdder;
            2'b11: Result = Less;
            default: Result = 1'bz;
        endcase
    end
    oneBitAdder adder (
        .a (tempA),
        .b (tempB),
        .carryIn (carryIn),
        .carryOut (carryOut),
        .sum (tempResultForAdder)
    );
endmodule
module oneBitALUForMSB (
    a, b, carryIn, Operation, Ainvert, Binvert, Less, Result, Set, Overflow
);

    input a, b, carryIn, Less, Ainvert, Binvert;
    input [1:0] Operation;
    output Result, Set, Overflow;
    reg Result;
    wire tempA, tempB, Set, tempResultForAdder, rresult, carryOut;

    assign tempA = (Ainvert == 1) ? ~a : a;
    assign tempB = (Binvert == 1) ? ~b : b;
    assign Overflow = carryIn ^ carryOut;
    assign Set = tempResultForAdder;

    always @(tempA, tempB, tempResultForAdder, Less, Operation) begin
        case (Operation)
            2'b00: Result = tempA & tempB;
            2'b01: Result = tempA | tempB;
            2'b10: Result = tempResultForAdder;
            2'b11: Result = Less;
            default: Result = 1'bz;
        endcase
    end
    oneBitAdder adder (
        .a (tempA),
        .b (tempB),
        .carryIn (carryIn),
        .carryOut (carryOut),
        .sum (tempResultForAdder)
    );
endmodule