data/full_repos/permissive/469312749/alu/work/verilog/comp_16_10.v
data/verilator_xmls/605067c3-ba1c-4e4d-95a6-57ef1be1727f.xml
module comp_16_10 (
    input z,
    input v,
    input n,
    input [1:0] compAlufn,
    output reg [15:0] compOut
  );
  
  
  
  reg temp;
  
  always @* begin
    
    case (compAlufn)
      2'h1: begin
        temp = z;
      end
      2'h2: begin
        temp = n ^ v;
      end
      2'h3: begin
        temp = (n ^ v) | z;
      end
      default: begin
        temp = 1'h0;
      end
    endcase
    compOut[1+14-:15] = 15'h0000;
    compOut[0+0-:1] = temp;
  end
endmodule
module comp_16_10 (
    input z,
    input v,
    input n,
    input [1:0] compAlufn,
    output reg [15:0] compOut
  );

  
  
  
  reg temp;
  
  always @* begin
    
    case (compAlufn)
      2'h1: begin
        temp = z;
      end
      2'h2: begin
        temp = n ^ v;
      end
      2'h3: begin
        temp = (n ^ v) | z;
      end
      default: begin
        temp = 1'h0;
      end
    endcase
    compOut[1+14-:15] = 15'h0000;
    compOut[0+0-:1] = temp;
  end
endmodule