data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic_high.v
data/verilator_xmls/d4447223-3d46-44a8-8634-394431cc99d6.xml
module bw_io_ddr_vref_logic_high(in,vrefcode,vdd18);
input vdd18;
input [7:1] in;
output [7:0] vrefcode;

assign vrefcode[7:0] = {in[7:1],1'b0};
endmodule
module bw_io_ddr_vref_logic_high(in,vrefcode,vdd18);

input vdd18;
input [7:1] in;
output [7:0] vrefcode;

assign vrefcode[7:0] = {in[7:1],1'b0};
endmodule