data/full_repos/permissive/43264243/root_xilinx.v
1: b"%Error: data/full_repos/permissive/43264243/root_xilinx.v:60: Cannot find file containing module: 'system'\n system sys0(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/system\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/system.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/system.sv\n             system\n             system.v\n             system.sv\n             obj_dir/system\n             obj_dir/system.v\n             obj_dir/system.sv\n%Error: data/full_repos/permissive/43264243/root_xilinx.v:76: Cannot find file containing module: 'PLL_BASE'\n PLL_BASE #(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module root(clk, rstn, datain_ch0, datain_ch1, datain_ch2, datain_ch3, serialout, clk20, locked, testout0, testout1, testout2, testout3);
	input clk;
	input rstn;
	input datain_ch0;
	input datain_ch1;
	input datain_ch2;
	input datain_ch3;
	output clk20;
	output locked;
	output serialout;
	output testout0;
	output testout1;
	output testout2;
	output testout3;
	wire fbouttofbin;
	wire clk100;
	wire rstn_int;
	wire locked_int;
	wire CLKOUT2;
	wire CLKOUT3;
	wire CLKOUT4;
	wire CLKOUT5;
					
	system sys0(
		.clk(clk100),
		.rstn(rstn_int),
		.datain_ch0(datain_ch0),
		.datain_ch1(datain_ch1),
		.datain_ch2(datain_ch2),
		.datain_ch3(datain_ch3),
		.serialout(serialout),
		.testout0(testout0),
		.testout1(testout1),
		.testout2(testout2),
		.testout3(testout3)
	
	);
	
	
	PLL_BASE #(
	.BANDWIDTH("OPTIMIZED"),
	.CLKFBOUT_MULT(12),
	.CLKFBOUT_PHASE(0.0),
	.CLKIN_PERIOD(20.000),
	.CLKOUT0_DIVIDE(6),
	.CLKOUT0_DUTY_CYCLE(0.5),
	.CLKOUT0_PHASE(0.0),
	.CLKOUT1_DIVIDE(30),
	.CLKOUT1_DUTY_CYCLE(0.5),
	.CLKOUT1_PHASE(0.0),
	.CLKOUT2_DIVIDE(1),
	.CLKOUT2_DUTY_CYCLE(0.5),
	.CLKOUT2_PHASE(0.0),
	.CLKOUT3_DIVIDE(1),
	.CLKOUT3_DUTY_CYCLE(0.5),
	.CLKOUT3_PHASE(0.0),
	.CLKOUT4_DIVIDE(1),
	.CLKOUT4_DUTY_CYCLE(0.5),
	.CLKOUT4_PHASE(0.0),
	.CLKOUT5_DIVIDE(1),
	.CLKOUT5_DUTY_CYCLE(0.5),
	.CLKOUT5_PHASE(0.0),
	.COMPENSATION("SYSTEM_SYNCHRONOUS"),


	.DIVCLK_DIVIDE(1),
	.REF_JITTER(0.100)
	) PLL_BASE_inst (
		.CLKFBOUT(fbouttofbin),
		.CLKOUT0(clk100),
		.CLKOUT1(clk20),
		.CLKOUT2(CLKOUT2),
		.CLKOUT3(CLKOUT3),
		.CLKOUT4(CLKOUT4),
		.CLKOUT5(CLKOUT5),
		.LOCKED(locked_int),
		.CLKFBIN(fbouttofbin),
		.CLKIN(clk),
		.RST(~rstn)
	);
	
	assign locked = locked_int;
	assign rstn_int = rstn & locked_int;

endmodule
module root(clk, rstn, datain_ch0, datain_ch1, datain_ch2, datain_ch3, serialout, clk20, locked, testout0, testout1, testout2, testout3);

	input clk;
	input rstn;
	input datain_ch0;
	input datain_ch1;
	input datain_ch2;
	input datain_ch3;
	output clk20;
	output locked;
	output serialout;
	output testout0;
	output testout1;
	output testout2;
	output testout3;
	wire fbouttofbin;
	wire clk100;
	wire rstn_int;
	wire locked_int;
	wire CLKOUT2;
	wire CLKOUT3;
	wire CLKOUT4;
	wire CLKOUT5;
					
	system sys0(
		.clk(clk100),
		.rstn(rstn_int),
		.datain_ch0(datain_ch0),
		.datain_ch1(datain_ch1),
		.datain_ch2(datain_ch2),
		.datain_ch3(datain_ch3),
		.serialout(serialout),
		.testout0(testout0),
		.testout1(testout1),
		.testout2(testout2),
		.testout3(testout3)
	
	);
	
	
	PLL_BASE #(
	.BANDWIDTH("OPTIMIZED"),
	.CLKFBOUT_MULT(12),
	.CLKFBOUT_PHASE(0.0),
	.CLKIN_PERIOD(20.000),
	.CLKOUT0_DIVIDE(6),
	.CLKOUT0_DUTY_CYCLE(0.5),
	.CLKOUT0_PHASE(0.0),
	.CLKOUT1_DIVIDE(30),
	.CLKOUT1_DUTY_CYCLE(0.5),
	.CLKOUT1_PHASE(0.0),
	.CLKOUT2_DIVIDE(1),
	.CLKOUT2_DUTY_CYCLE(0.5),
	.CLKOUT2_PHASE(0.0),
	.CLKOUT3_DIVIDE(1),
	.CLKOUT3_DUTY_CYCLE(0.5),
	.CLKOUT3_PHASE(0.0),
	.CLKOUT4_DIVIDE(1),
	.CLKOUT4_DUTY_CYCLE(0.5),
	.CLKOUT4_PHASE(0.0),
	.CLKOUT5_DIVIDE(1),
	.CLKOUT5_DUTY_CYCLE(0.5),
	.CLKOUT5_PHASE(0.0),
	.COMPENSATION("SYSTEM_SYNCHRONOUS"),


	.DIVCLK_DIVIDE(1),
	.REF_JITTER(0.100)
	) PLL_BASE_inst (
		.CLKFBOUT(fbouttofbin),
		.CLKOUT0(clk100),
		.CLKOUT1(clk20),
		.CLKOUT2(CLKOUT2),
		.CLKOUT3(CLKOUT3),
		.CLKOUT4(CLKOUT4),
		.CLKOUT5(CLKOUT5),
		.LOCKED(locked_int),
		.CLKFBIN(fbouttofbin),
		.CLKIN(clk),
		.RST(~rstn)
	);
	
	assign locked = locked_int;
	assign rstn_int = rstn & locked_int;

endmodule