data/full_repos/permissive/426864978/lab3/task4/seg7.sv
data/verilator_xmls/c2d5d0ef-1041-47da-a8fe-7363bdf92395.xml
module seg7(input [3:0] hex, input done, input found, output [6:0] HEX0);
    reg [6:0] led;

    assign HEX0 = led;

    always @(*) begin
        if (done == 1'b1) begin
            if (found == 1'b1)
                case (hex)
                    4'b0000: led = `ZERO;
                    4'b0001: led = `ONE;
                    4'b0010: led = `TWO;
                    4'b0011: led = `THREE;
                    4'b0100: led = `FOUR;
                    4'b0101: led = `FIVE;
                    4'b0110: led = `SIX;
                    4'b0111: led = `SEVEN;
                    4'b1000: led = `EIGHT;
                    4'b1001: led = `NINE;
                    4'b1010: led = `A;
                    4'b1011: led = `B;
                    4'b1100: led = `C;
                    4'b1101: led = `D;
                    4'b1110: led = `E;
                    4'b1111: led = `F;
                    default: led = `NONE;
                endcase
            else
                led = `DASH;
        end else
            led = `NONE;
    end
    
endmodule
module seg7(input [3:0] hex, input done, input found, output [6:0] HEX0);

    reg [6:0] led;

    assign HEX0 = led;

    always @(*) begin
        if (done == 1'b1) begin
            if (found == 1'b1)
                case (hex)
                    4'b0000: led = `ZERO;
                    4'b0001: led = `ONE;
                    4'b0010: led = `TWO;
                    4'b0011: led = `THREE;
                    4'b0100: led = `FOUR;
                    4'b0101: led = `FIVE;
                    4'b0110: led = `SIX;
                    4'b0111: led = `SEVEN;
                    4'b1000: led = `EIGHT;
                    4'b1001: led = `NINE;
                    4'b1010: led = `A;
                    4'b1011: led = `B;
                    4'b1100: led = `C;
                    4'b1101: led = `D;
                    4'b1110: led = `E;
                    4'b1111: led = `F;
                    default: led = `NONE;
                endcase
            else
                led = `DASH;
        end else
            led = `NONE;
    end
    
endmodule