data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/Bitstream_Buffer.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/Bitstream_Buffer.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/Bitstream_Buffer.v:29: Define or directive not defined: \'`BITSTR_BUFFER_ADDR_WIDTH\'\ninput [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_A_I;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/Bitstream_Buffer.v:33: Define or directive not defined: \'`BITSTR_BUFFER_ADDR_WIDTH\'\ninput [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_B_I;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module Bitstream_Buffer(
   clock,
   Address_A_I,
   Write_Enable_A_I,
   Data_A_I,
   Enable_B_I,
   Address_B_I,
   Data_B_O
);

input             clock;
input [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_A_I;
input             Write_Enable_A_I;
input    [31:0]   Data_A_I;
input             Enable_B_I;
input [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_B_I;
output   [31:0]   Data_B_O;

wire     [31:0]   Data_B;

assign Data_B_O = Data_B;

RAMB16_S36_S36 Bitstream_Buffer_RAM (
   .DOA(),
   .DOB(Data_B),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I),
   .ADDRB(Address_B_I),
   .CLKA(clock),
   .CLKB(clock),
   .DIA(Data_A_I),
   .DIB(32'h0000),
   .DIPA(4'b00),
   .DIPB(4'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

endmodule
module Bitstream_Buffer(
   clock,
   Address_A_I,
   Write_Enable_A_I,
   Data_A_I,
   Enable_B_I,
   Address_B_I,
   Data_B_O
);


input             clock;
input [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_A_I;
input             Write_Enable_A_I;
input    [31:0]   Data_A_I;
input             Enable_B_I;
input [`BITSTR_BUFFER_ADDR_WIDTH-1:0] Address_B_I;
output   [31:0]   Data_B_O;

wire     [31:0]   Data_B;

assign Data_B_O = Data_B;

RAMB16_S36_S36 Bitstream_Buffer_RAM (
   .DOA(),
   .DOB(Data_B),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I),
   .ADDRB(Address_B_I),
   .CLKA(clock),
   .CLKB(clock),
   .DIA(Data_A_I),
   .DIB(32'h0000),
   .DIPA(4'b00),
   .DIPB(4'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

endmodule