data/full_repos/permissive/517031174/Template/clk_div.v
1: b'%Warning-WIDTH: data/full_repos/permissive/517031174/Template/clk_div.v:20: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                          : ... In instance clk_div\n  div_cnt <= 16\'d0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/clk_div.v:23: Operator ADD expects 49 bits on the LHS, but LHS\'s VARREF \'div_cnt\' generates 32 bits.\n                                                                          : ... In instance clk_div\n  div_cnt <= div_cnt + freq_word;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/clk_div.v:23: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 49 bits.\n                                                                          : ... In instance clk_div\n  div_cnt <= div_cnt + freq_word;\n          ^~\n%Error: Exiting due to 3 warning(s)\n'
module clk_div #(
	parameter CLKREF = 32'd256_000_000
)(
    input clk,
    input rst_n, 
	input [31:0]freq_set,
	output reg clk_div
);

reg [31:0]div_cnt;
reg [48:0]freq_word;

always@(*)
begin
	freq_word <= (freq_set*32'd1099512)>>5'd16;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		div_cnt <= 16'd0;
	end
	else begin
		div_cnt <= div_cnt + freq_word;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		clk_div <= 1'b0;
	end
	else begin
		if(div_cnt < 32'h7fff_ffff) begin
			clk_div <= 1'b0;
		end
		else begin
			clk_div <= 1'b1;
		end
	end
end

endmodule
module clk_div #(
	parameter CLKREF = 32'd256_000_000
)(
    input clk,
    input rst_n, 
	input [31:0]freq_set,
	output reg clk_div
);


reg [31:0]div_cnt;
reg [48:0]freq_word;

always@(*)
begin
	freq_word <= (freq_set*32'd1099512)>>5'd16;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		div_cnt <= 16'd0;
	end
	else begin
		div_cnt <= div_cnt + freq_word;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		clk_div <= 1'b0;
	end
	else begin
		if(div_cnt < 32'h7fff_ffff) begin
			clk_div <= 1'b0;
		end
		else begin
			clk_div <= 1'b1;
		end
	end
end

endmodule