data/full_repos/permissive/478243883/Top.v
1: b"%Error: data/full_repos/permissive/478243883/Top.v:47: Cannot find file containing module: 'clk_wiz_0'\nclk_wiz_0 inst(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/478243883,data/full_repos/permissive/478243883/clk_wiz_0\n             data/full_repos/permissive/478243883,data/full_repos/permissive/478243883/clk_wiz_0.v\n             data/full_repos/permissive/478243883,data/full_repos/permissive/478243883/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/478243883/Top.v:66: Cannot find file containing module: 'UART_RX'\nUART_RX Receiver_inst(\n^~~~~~~\n%Error: data/full_repos/permissive/478243883/Top.v:98: Cannot find file containing module: 'UART_TX'\nUART_TX Transmitter_inst(\n^~~~~~~\n%Error: data/full_repos/permissive/478243883/Top.v:127: Cannot find file containing module: 'Bitcoin_Wrapper'\nBitcoin_Wrapper Miner_inst(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module Top(
    sys_clk_p,
    sys_clk_n,
    RX_In,
    TX_Out
);








input sys_clk_p;
input sys_clk_n;


wire clk;


clk_wiz_0 inst(

    .clk_out1(clk),

    .clk_in1_p(sys_clk_p),
    .clk_in1_n(sys_clk_n)
);







input RX_In;
wire [7:0] RX_Out;
wire RX_Valid;


UART_RX Receiver_inst(
    .clk(clk),
    .RX_In(RX_In),
    .RX_Valid(RX_Valid),
    .RX_Out(RX_Out)
);


reg [10:0] Byte_Counter;
reg [639:0] RX_data;
reg Block_Header_Valid;


parameter [31:0] Training_Sequence = 32'b01100001011000100110001101100100;
parameter TS_BYTE_SIZE = 4;
reg [3:0] RX_State;
reg [6:0] TS_Index;








reg TX_Enable;
reg [7:0] TX_In_Reg;
wire [7:0] TX_In;
wire TX_Valid;
output wire TX_Out;


UART_TX Transmitter_inst(
    .clk(clk),
    .TX_In(TX_In),
    .TX_Enable(TX_Enable),
    .TX_Out(TX_Out),
    .TX_Valid(TX_Valid)
);


assign TX_In = TX_In_Reg;


reg [255:0] TX_Data;
reg [6:0] TX_Index;
wire Transmit_Enable;
reg TX_State;

wire [255:0] Golden_Hash;


parameter BYTES_TO_SEND     = 32;
parameter BYTES_TO_RECEIVE  = 80;







Bitcoin_Wrapper Miner_inst(
    .clk(clk),
    .Block_Header(RX_data),
    .Block_Header_Valid(Block_Header_Valid),

    .Golden_Hash(Golden_Hash),
    .Hash_Valid(Transmit_Enable)
);  









always @ (posedge clk)
begin
case (TX_State)

    1'b0:
        begin
        TX_Enable <= 0;

        if (Transmit_Enable)
            begin
            TX_Data <= Golden_Hash;
            TX_Index <= BYTES_TO_SEND - 1; 
            TX_State <= 1;
            end

        else 
            begin
            TX_State <= 0;
            end
        end 

    1'b1:
        begin
        TX_Enable <= 1;
        TX_In_Reg <= TX_Data[((TX_Index)*8) +: 8];

        if (TX_Valid == 1)
            begin                           

            if (TX_Index == 0)
                begin
                TX_State <= 0;
                end

            else
                begin
                TX_Index <= TX_Index - 1; 
                TX_State <= 1;
                end
            end

        else
            begin
            TX_State <= 1;
            end
        end 
    default: TX_State <= 0;
endcase
end







always @ (posedge clk)
begin

if (RX_Valid == 1)
    begin        
    case(RX_State)


    4'd0: 
        begin
        Block_Header_Valid <= 0;
        Byte_Counter <= BYTES_TO_RECEIVE-1;

        if (RX_Out == Training_Sequence[((TS_Index)*8) +: 8])
            begin

            if (TS_Index == 0)
                begin                
                RX_State <= 1;
                RX_data <= 0;
                end

            else
                begin
                TS_Index <= TS_Index - 1;
                RX_State <= 0;
                end        
            end

        else
            begin
            TS_Index <= TS_BYTE_SIZE-1;
            RX_State <= 0;
            end
        end


    4'd1: 
        begin  
        TS_Index <= TS_BYTE_SIZE-1;
        RX_data[((Byte_Counter)*8) +: 8] <= RX_Out;            
        if (Byte_Counter == 0)
            begin
            Byte_Counter <= BYTES_TO_RECEIVE-1;
            Block_Header_Valid <= 1;
            RX_State <= 0;
            end
        else
            begin             
            Byte_Counter <= Byte_Counter - 1;
            Block_Header_Valid <= 0;
            RX_State <= 1;
            end
        end 

    default: RX_State <= 0;
    endcase
    end
else 
    begin
    Block_Header_Valid <= 0;
    end
end



endmodule
module Top(
    sys_clk_p,
    sys_clk_n,
    RX_In,
    TX_Out
);









input sys_clk_p;
input sys_clk_n;


wire clk;


clk_wiz_0 inst(

    .clk_out1(clk),

    .clk_in1_p(sys_clk_p),
    .clk_in1_n(sys_clk_n)
);







input RX_In;
wire [7:0] RX_Out;
wire RX_Valid;


UART_RX Receiver_inst(
    .clk(clk),
    .RX_In(RX_In),
    .RX_Valid(RX_Valid),
    .RX_Out(RX_Out)
);


reg [10:0] Byte_Counter;
reg [639:0] RX_data;
reg Block_Header_Valid;


parameter [31:0] Training_Sequence = 32'b01100001011000100110001101100100;
parameter TS_BYTE_SIZE = 4;
reg [3:0] RX_State;
reg [6:0] TS_Index;








reg TX_Enable;
reg [7:0] TX_In_Reg;
wire [7:0] TX_In;
wire TX_Valid;
output wire TX_Out;


UART_TX Transmitter_inst(
    .clk(clk),
    .TX_In(TX_In),
    .TX_Enable(TX_Enable),
    .TX_Out(TX_Out),
    .TX_Valid(TX_Valid)
);


assign TX_In = TX_In_Reg;


reg [255:0] TX_Data;
reg [6:0] TX_Index;
wire Transmit_Enable;
reg TX_State;

wire [255:0] Golden_Hash;


parameter BYTES_TO_SEND     = 32;
parameter BYTES_TO_RECEIVE  = 80;







Bitcoin_Wrapper Miner_inst(
    .clk(clk),
    .Block_Header(RX_data),
    .Block_Header_Valid(Block_Header_Valid),

    .Golden_Hash(Golden_Hash),
    .Hash_Valid(Transmit_Enable)
);  









always @ (posedge clk)
begin
case (TX_State)

    1'b0:
        begin
        TX_Enable <= 0;

        if (Transmit_Enable)
            begin
            TX_Data <= Golden_Hash;
            TX_Index <= BYTES_TO_SEND - 1; 
            TX_State <= 1;
            end

        else 
            begin
            TX_State <= 0;
            end
        end 

    1'b1:
        begin
        TX_Enable <= 1;
        TX_In_Reg <= TX_Data[((TX_Index)*8) +: 8];

        if (TX_Valid == 1)
            begin                           

            if (TX_Index == 0)
                begin
                TX_State <= 0;
                end

            else
                begin
                TX_Index <= TX_Index - 1; 
                TX_State <= 1;
                end
            end

        else
            begin
            TX_State <= 1;
            end
        end 
    default: TX_State <= 0;
endcase
end







always @ (posedge clk)
begin

if (RX_Valid == 1)
    begin        
    case(RX_State)


    4'd0: 
        begin
        Block_Header_Valid <= 0;
        Byte_Counter <= BYTES_TO_RECEIVE-1;

        if (RX_Out == Training_Sequence[((TS_Index)*8) +: 8])
            begin

            if (TS_Index == 0)
                begin                
                RX_State <= 1;
                RX_data <= 0;
                end

            else
                begin
                TS_Index <= TS_Index - 1;
                RX_State <= 0;
                end        
            end

        else
            begin
            TS_Index <= TS_BYTE_SIZE-1;
            RX_State <= 0;
            end
        end


    4'd1: 
        begin  
        TS_Index <= TS_BYTE_SIZE-1;
        RX_data[((Byte_Counter)*8) +: 8] <= RX_Out;            
        if (Byte_Counter == 0)
            begin
            Byte_Counter <= BYTES_TO_RECEIVE-1;
            Block_Header_Valid <= 1;
            RX_State <= 0;
            end
        else
            begin             
            Byte_Counter <= Byte_Counter - 1;
            Block_Header_Valid <= 0;
            RX_State <= 1;
            end
        end 

    default: RX_State <= 0;
    endcase
    end
else 
    begin
    Block_Header_Valid <= 0;
    end
end



endmodule