data/full_repos/permissive/454159683/mul4bj/mul4bj.v
1: b'%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:11: Cannot find file containing module: \'mul1b\'\n mul1b u0(x[0], y[0], 0, 0, cx[0], sx[0]);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/454159683/mul4bj,data/full_repos/permissive/454159683/mul1b\n             data/full_repos/permissive/454159683/mul4bj,data/full_repos/permissive/454159683/mul1b.v\n             data/full_repos/permissive/454159683/mul4bj,data/full_repos/permissive/454159683/mul1b.sv\n             mul1b\n             mul1b.v\n             mul1b.sv\n             obj_dir/mul1b\n             obj_dir/mul1b.v\n             obj_dir/mul1b.sv\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:12: Cannot find file containing module: \'mul1b\'\n mul1b u1(x[1], y[0], 0, cx[0], cx[1], sx[1]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:13: Cannot find file containing module: \'mul1b\'\n mul1b u2(x[2], y[0], 0, cx[1], cx[2], sx[2]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:14: Cannot find file containing module: \'mul1b\'\n mul1b u3(x[3], y[0], 0, cx[2], cx[3], sx[3]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:17: Cannot find file containing module: \'mul1b\'\n mul1b u4(x[0], y[1], sx[1], 0, cx[4], sx[4]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:18: Cannot find file containing module: \'mul1b\'\n mul1b u5(x[1], y[1], sx[2], cx[4], cx[5], sx[5]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:19: Cannot find file containing module: \'mul1b\'\n mul1b u6(x[2], y[1], sx[3], cx[5], cx[6], sx[6]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:20: Cannot find file containing module: \'mul1b\'\n mul1b u7(x[3], y[1], cx[3], cx[6], cx[7], sx[7]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:23: Cannot find file containing module: \'mul1b\'\n mul1b u8(x[0], y[2], sx[5], 0, cx[8], sx[8]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:24: Cannot find file containing module: \'mul1b\'\n mul1b u9(x[1], y[2], sx[6], cx[8], cx[9], sx[9]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:25: Cannot find file containing module: \'mul1b\'\n mul1b u10(x[2], y[2], sx[7], cx[9], cx[10], sx[10]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:26: Cannot find file containing module: \'mul1b\'\n mul1b u11(x[3], y[2], cx[7], cx[10], cx[11], sx[11]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:29: Cannot find file containing module: \'mul1b\'\n mul1b u12(x[0], y[3], sx[9], 0, cx[12], sx[12]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:30: Cannot find file containing module: \'mul1b\'\n mul1b u13(x[1], y[3], sx[10], cx[12], cx[13], sx[13]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:31: Cannot find file containing module: \'mul1b\'\n mul1b u14(x[2], y[3], sx[11], cx[13], cx[14], sx[14]);\n ^~~~~\n%Error: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:32: Cannot find file containing module: \'mul1b\'\n mul1b u15(x[3], y[3], cx[11], cx[14], cx[15], sx[15]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:35: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[0] = sx[0];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:36: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[1] = sx[4];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:37: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[2] = sx[8];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:38: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[3] = sx[12];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:39: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[4] = sx[13];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:40: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[5] = sx[14];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bj/mul4bj.v:41: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                       : ... In instance mul4bj\n assign z[6] = sx[15];\n             ^\n%Error: Exiting due to 16 error(s), 7 warning(s)\n'
module mul4bj(input [3:0]x, y, output [7:0]z);
	wire [15:0]cx, sx[15:0];



	mul1b u0(x[0], y[0], 0, 0, cx[0], sx[0]);
	mul1b u1(x[1], y[0], 0, cx[0], cx[1], sx[1]);
	mul1b u2(x[2], y[0], 0, cx[1], cx[2], sx[2]);
	mul1b u3(x[3], y[0], 0, cx[2], cx[3], sx[3]);
	

	mul1b u4(x[0], y[1], sx[1], 0, cx[4], sx[4]);
	mul1b u5(x[1], y[1], sx[2], cx[4], cx[5], sx[5]);
	mul1b u6(x[2], y[1], sx[3], cx[5], cx[6], sx[6]);
	mul1b u7(x[3], y[1], cx[3], cx[6], cx[7], sx[7]);
	

	mul1b u8(x[0], y[2], sx[5], 0, cx[8], sx[8]);
	mul1b u9(x[1], y[2], sx[6], cx[8], cx[9], sx[9]);
	mul1b u10(x[2], y[2], sx[7], cx[9], cx[10], sx[10]);
	mul1b u11(x[3], y[2], cx[7], cx[10], cx[11], sx[11]);
	

	mul1b u12(x[0], y[3], sx[9], 0, cx[12], sx[12]);
	mul1b u13(x[1], y[3], sx[10], cx[12], cx[13], sx[13]);
	mul1b u14(x[2], y[3], sx[11], cx[13], cx[14], sx[14]);
	mul1b u15(x[3], y[3], cx[11], cx[14], cx[15], sx[15]);
	
	
	assign z[0] = sx[0];
	assign z[1] = sx[4];
	assign z[2] = sx[8];
	assign z[3] = sx[12];
	assign z[4] = sx[13];
	assign z[5] = sx[14];
	assign z[6] = sx[15];
	assign z[7] = cx[15];

endmodule
module mul4bj(input [3:0]x, y, output [7:0]z);

	wire [15:0]cx, sx[15:0];



	mul1b u0(x[0], y[0], 0, 0, cx[0], sx[0]);
	mul1b u1(x[1], y[0], 0, cx[0], cx[1], sx[1]);
	mul1b u2(x[2], y[0], 0, cx[1], cx[2], sx[2]);
	mul1b u3(x[3], y[0], 0, cx[2], cx[3], sx[3]);
	

	mul1b u4(x[0], y[1], sx[1], 0, cx[4], sx[4]);
	mul1b u5(x[1], y[1], sx[2], cx[4], cx[5], sx[5]);
	mul1b u6(x[2], y[1], sx[3], cx[5], cx[6], sx[6]);
	mul1b u7(x[3], y[1], cx[3], cx[6], cx[7], sx[7]);
	

	mul1b u8(x[0], y[2], sx[5], 0, cx[8], sx[8]);
	mul1b u9(x[1], y[2], sx[6], cx[8], cx[9], sx[9]);
	mul1b u10(x[2], y[2], sx[7], cx[9], cx[10], sx[10]);
	mul1b u11(x[3], y[2], cx[7], cx[10], cx[11], sx[11]);
	

	mul1b u12(x[0], y[3], sx[9], 0, cx[12], sx[12]);
	mul1b u13(x[1], y[3], sx[10], cx[12], cx[13], sx[13]);
	mul1b u14(x[2], y[3], sx[11], cx[13], cx[14], sx[14]);
	mul1b u15(x[3], y[3], cx[11], cx[14], cx[15], sx[15]);
	
	
	assign z[0] = sx[0];
	assign z[1] = sx[4];
	assign z[2] = sx[8];
	assign z[3] = sx[12];
	assign z[4] = sx[13];
	assign z[5] = sx[14];
	assign z[6] = sx[15];
	assign z[7] = cx[15];

endmodule