data/full_repos/permissive/48330045/test/tb_shift_register.v
1: b'%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:1: Cannot find include file: ../rtl/shift_register.v\n`include "../rtl/shift_register.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/shift_register.v\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/shift_register.v.v\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/shift_register.v.sv\n             ../rtl/shift_register.v\n             ../rtl/shift_register.v.v\n             ../rtl/shift_register.v.sv\n             obj_dir/../rtl/shift_register.v\n             obj_dir/../rtl/shift_register.v.v\n             obj_dir/../rtl/shift_register.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_shift_register.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tb_shift_register.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb_shift_register);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_shift_register.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst_n<=1\'bx;clk<=1\'bx;en<=1\'bx;d<={WIDTH{1\'bx}};\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_shift_register.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD) rst_n<=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_shift_register.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD*3) rst_n<=0;clk<=0;en<=0;d<=0;\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:38: syntax error, unexpected \'@\'\n  repeat(5) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:40: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:42: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:44: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:46: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:48: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:50: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:52: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:56: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:60: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:64: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:68: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/48330045/test/tb_shift_register.v:71: syntax error, unexpected \'@\'\n  repeat(5) @(posedge clk);\n            ^\n%Error: Exiting due to 16 error(s), 4 warning(s)\n'
module tb_shift_register;

parameter DEPTH = 4;
parameter WIDTH = 4;

reg  clk;
reg  rst_n;
reg  en;
reg [WIDTH-1:0] d;
wire [WIDTH-1:0] q;

shift_register
#(
  .DEPTH(DEPTH),
  .WIDTH(WIDTH)
) _shift_register
(
  .clk   ( clk   ) ,
  .rst_n ( rst_n ) ,
  .en    ( en    ) ,
  .d     ( d     ) ,
  .q     ( q     )
);

parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;

initial begin
  $dumpfile("tb_shift_register.vcd");
  $dumpvars(0, tb_shift_register);
  #1 rst_n<=1'bx;clk<=1'bx;en<=1'bx;d<={WIDTH{1'bx}};
  #(CLK_PERIOD) rst_n<=1;
  #(CLK_PERIOD*3) rst_n<=0;clk<=0;en<=0;d<=0;
  repeat(5) @(posedge clk);
  rst_n<=1;
  @(posedge clk);
  d<=1;
  @(posedge clk);
  en<=1;
  @(posedge clk);
  d<=2;
  @(posedge clk);
  d<=3;
  @(posedge clk);
  d<=4;
  @(posedge clk);
  d<=5;
  @(posedge clk);
  if(q !== 1)
    $display("result == ", 1, " expected but ", q);
  d<=6;
  @(posedge clk);
  if(q !== 2)
    $display("result == ", 2, " expected but ", q);
  d<=7;
  @(posedge clk);
  if(q !== 3)
    $display("result == ", 3, " expected but ", q);
  d<=8;
  @(posedge clk);
  if(q !== 4)
    $display("result == ", 4, " expected but ", q);
  en<=0;
  @(posedge clk);
  if(q !== 5)
    $display("result == ", 5, " expected but ", q);
  repeat(5) @(posedge clk);
  $finish(2);
end

endmodule
module tb_shift_register;


parameter DEPTH = 4;
parameter WIDTH = 4;

reg  clk;
reg  rst_n;
reg  en;
reg [WIDTH-1:0] d;
wire [WIDTH-1:0] q;

shift_register
#(
  .DEPTH(DEPTH),
  .WIDTH(WIDTH)
) _shift_register
(
  .clk   ( clk   ) ,
  .rst_n ( rst_n ) ,
  .en    ( en    ) ,
  .d     ( d     ) ,
  .q     ( q     )
);

parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;

initial begin
  $dumpfile("tb_shift_register.vcd");
  $dumpvars(0, tb_shift_register);
  #1 rst_n<=1'bx;clk<=1'bx;en<=1'bx;d<={WIDTH{1'bx}};
  #(CLK_PERIOD) rst_n<=1;
  #(CLK_PERIOD*3) rst_n<=0;clk<=0;en<=0;d<=0;
  repeat(5) @(posedge clk);
  rst_n<=1;
  @(posedge clk);
  d<=1;
  @(posedge clk);
  en<=1;
  @(posedge clk);
  d<=2;
  @(posedge clk);
  d<=3;
  @(posedge clk);
  d<=4;
  @(posedge clk);
  d<=5;
  @(posedge clk);
  if(q !== 1)
    $display("result == ", 1, " expected but ", q);
  d<=6;
  @(posedge clk);
  if(q !== 2)
    $display("result == ", 2, " expected but ", q);
  d<=7;
  @(posedge clk);
  if(q !== 3)
    $display("result == ", 3, " expected but ", q);
  d<=8;
  @(posedge clk);
  if(q !== 4)
    $display("result == ", 4, " expected but ", q);
  en<=0;
  @(posedge clk);
  if(q !== 5)
    $display("result == ", 5, " expected but ", q);
  repeat(5) @(posedge clk);
  $finish(2);
end

endmodule