data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/my_mult_DAC_tb.v:20: Cannot find file containing module: \'my_mult\'\nmy_mult #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/my_mult\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/my_mult.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/my_mult.sv\n             my_mult\n             my_mult.v\n             my_mult.sv\n             obj_dir/my_mult\n             obj_dir/my_mult.v\n             obj_dir/my_mult.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module my_mult_DAC_tb;
localparam NUM_SAMPS = 3;
localparam F_period=4;
localparam H_period=F_period/2;
localparam DATA_WIDTH = 64;
localparam DAC_WIDTH = 14;
localparam INT_WIDTH = 16;
localparam BIT_SHIFT = 0;
localparam DEC_FORMAT = DATA_WIDTH-INT_WIDTH;
localparam INT_FORMAT = 2;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg  [DATA_WIDTH - 1	: 0] NUM_SAMPS_COUNT = {DATA_WIDTH{1'b0}};
reg	 [DATA_WIDTH - 1	: 0] A = {DATA_WIDTH{1'b0}};
reg  [DATA_WIDTH - 1	: 0] B = {DATA_WIDTH{1'b0}};
wire [DAC_WIDTH - 1    : 0] PRODUCT;

my_mult #(
	.DATA_WIDTH(DATA_WIDTH),
    .OUT_WIDTH(DAC_WIDTH),
	.INT_WIDTH(INT_WIDTH),
	.BIT_SHIFT(BIT_SHIFT),
	.INT_FORMAT(INT_FORMAT),
	.DEC_FORMAT(DEC_FORMAT)
) MUL0 (
	.a(A),
	.b(B),
	.p(PRODUCT)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        NUM_SAMPS_COUNT = NUM_SAMPS_COUNT + 1;
        #F_period;
        A = {{16'h0001}, {DATA_WIDTH-INT_WIDTH{1'b0}}};
        #F_period;
        B = {{16'h800A}, {DATA_WIDTH-INT_WIDTH{1'b0}}};
    end
    $finish;
end
endmodule
module my_mult_DAC_tb;

localparam NUM_SAMPS = 3;
localparam F_period=4;
localparam H_period=F_period/2;
localparam DATA_WIDTH = 64;
localparam DAC_WIDTH = 14;
localparam INT_WIDTH = 16;
localparam BIT_SHIFT = 0;
localparam DEC_FORMAT = DATA_WIDTH-INT_WIDTH;
localparam INT_FORMAT = 2;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg  [DATA_WIDTH - 1	: 0] NUM_SAMPS_COUNT = {DATA_WIDTH{1'b0}};
reg	 [DATA_WIDTH - 1	: 0] A = {DATA_WIDTH{1'b0}};
reg  [DATA_WIDTH - 1	: 0] B = {DATA_WIDTH{1'b0}};
wire [DAC_WIDTH - 1    : 0] PRODUCT;

my_mult #(
	.DATA_WIDTH(DATA_WIDTH),
    .OUT_WIDTH(DAC_WIDTH),
	.INT_WIDTH(INT_WIDTH),
	.BIT_SHIFT(BIT_SHIFT),
	.INT_FORMAT(INT_FORMAT),
	.DEC_FORMAT(DEC_FORMAT)
) MUL0 (
	.a(A),
	.b(B),
	.p(PRODUCT)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        NUM_SAMPS_COUNT = NUM_SAMPS_COUNT + 1;
        #F_period;
        A = {{16'h0001}, {DATA_WIDTH-INT_WIDTH{1'b0}}};
        #F_period;
        B = {{16'h800A}, {DATA_WIDTH-INT_WIDTH{1'b0}}};
    end
    $finish;
end
endmodule