data/full_repos/permissive/494305189/pow/pow.v
1: b'%Warning-WIDTH: data/full_repos/permissive/494305189/pow/pow.v:18: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 7 bits.\n                                                                 : ... In instance pow\n    result <= a;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/494305189/pow/pow.v:21: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 7 bits.\n                                                                 : ... In instance pow\n     result <= a;\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module pow(input clk, rst, input[6:0] a, b, output reg[13:0] result);
	reg[6:0] count;
	reg finish;
	always @(posedge clk) begin
		if (rst) begin
			finish <= 0;
			result <= 0;
			count <= 0;
		end
		else if (finish == 0) begin
			if (b == 0)
				result <= 1;
			else if (b == 1)
				result <= a;
			else if (count < b) begin
				if (count == 0) begin
					result <= a;
					count <= count + 1;
				end
				else begin
					result <= result * a;
					count <= count + 1;
				end
			end
			else
				finish <= 1;
		end
	end
endmodule
module pow(input clk, rst, input[6:0] a, b, output reg[13:0] result);

	reg[6:0] count;
	reg finish;
	always @(posedge clk) begin
		if (rst) begin
			finish <= 0;
			result <= 0;
			count <= 0;
		end
		else if (finish == 0) begin
			if (b == 0)
				result <= 1;
			else if (b == 1)
				result <= a;
			else if (count < b) begin
				if (count == 0) begin
					result <= a;
					count <= count + 1;
				end
				else begin
					result <= result * a;
					count <= count + 1;
				end
			end
			else
				finish <= 1;
		end
	end
endmodule