data/full_repos/permissive/496508301/Lesson2/fn_sw.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=0;bb<=0;ss<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=0;bb<=1;ss<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=0;bb<=1;ss<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=1;bb<=0;ss<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=1;bb<=0;ss<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 aa<=1;bb<=1;ss<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Error: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:49: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("fn_sw_tb.vcd");  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson2/fn_sw.v:50: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;  \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fn_sw_tb;
reg     aa,bb,ss;
wire    yy;
fn_sw fn_sw(
        .a(aa),
        .b(bb),
        .sel(ss),
        .y(yy)
);

initial begin
        aa<=0;bb<=0;ss<=0;
    #10 aa<=0;bb<=0;ss<=1;
    #10 aa<=0;bb<=1;ss<=0;
    #10 aa<=0;bb<=1;ss<=1;
    #10 aa<=1;bb<=0;ss<=0;
    #10 aa<=1;bb<=0;ss<=1;
    #10 aa<=1;bb<=1;ss<=1;
    #10 $stop;
end

initial begin
    $dumpfile("fn_sw_tb.vcd");
    $dumpvars;
end
endmodule
module fn_sw_tb;

reg     aa,bb,ss;
wire    yy;
fn_sw fn_sw(
        .a(aa),
        .b(bb),
        .sel(ss),
        .y(yy)
);

initial begin
        aa<=0;bb<=0;ss<=0;
    #10 aa<=0;bb<=0;ss<=1;
    #10 aa<=0;bb<=1;ss<=0;
    #10 aa<=0;bb<=1;ss<=1;
    #10 aa<=1;bb<=0;ss<=0;
    #10 aa<=1;bb<=0;ss<=1;
    #10 aa<=1;bb<=1;ss<=1;
    #10 $stop;
end

initial begin
    $dumpfile("fn_sw_tb.vcd");
    $dumpvars;
end
endmodule