data/full_repos/permissive/42149584/Pong/Phase1/pong.v
1: b"%Error: data/full_repos/permissive/42149584/Pong/Phase1/pong.v:33: Cannot find file containing module: 'Clock50MHz'\n Clock50MHz ClockUnit(InputClock, clk50);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42149584/Pong/Phase1,data/full_repos/permissive/42149584/Clock50MHz\n             data/full_repos/permissive/42149584/Pong/Phase1,data/full_repos/permissive/42149584/Clock50MHz.v\n             data/full_repos/permissive/42149584/Pong/Phase1,data/full_repos/permissive/42149584/Clock50MHz.sv\n             Clock50MHz\n             Clock50MHz.v\n             Clock50MHz.sv\n             obj_dir/Clock50MHz\n             obj_dir/Clock50MHz.v\n             obj_dir/Clock50MHz.sv\n%Error: data/full_repos/permissive/42149584/Pong/Phase1/pong.v:39: Cannot find file containing module: 'BUFG'\n BUFG bufg_inst(clk25, clk25_int);\n ^~~~\n%Error: data/full_repos/permissive/42149584/Pong/Phase1/pong.v:44: Cannot find file containing module: 'video_timer'\n video_timer video_timer_inst(clk25, hsync, vsync, xpos, ypos);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/42149584/Pong/Phase1/pong.v:45: Cannot find file containing module: 'game'\n game game_inst(clk25, xpos, ypos, rota, rotb, red, green, blue);\n ^~~~\n%Error: Exiting due to 4 error(s)\n"
module PongNexys3(
    input InputClock,
    input rota,
    input rotb,
    output [2:0] red,
    output [2:0] green,
    output [1:0] blue,
    output hsync,
    output vsync
    );








	
	
	wire clk50;
	Clock50MHz ClockUnit(InputClock, clk50);
	reg clk25_int;
	always @(posedge clk50) begin
		clk25_int <= ~clk25_int;
	end
	wire clk25;
	BUFG bufg_inst(clk25, clk25_int);

	wire [9:0] xpos;
	wire [9:0] ypos;

	video_timer video_timer_inst(clk25, hsync, vsync, xpos, ypos);
	game game_inst(clk25, xpos, ypos, rota, rotb, red, green, blue);
					
endmodule
module PongNexys3(
    input InputClock,
    input rota,
    input rotb,
    output [2:0] red,
    output [2:0] green,
    output [1:0] blue,
    output hsync,
    output vsync
    );









	
	
	wire clk50;
	Clock50MHz ClockUnit(InputClock, clk50);
	reg clk25_int;
	always @(posedge clk50) begin
		clk25_int <= ~clk25_int;
	end
	wire clk25;
	BUFG bufg_inst(clk25, clk25_int);

	wire [9:0] xpos;
	wire [9:0] ypos;

	video_timer video_timer_inst(clk25, hsync, vsync, xpos, ypos);
	game game_inst(clk25, xpos, ypos, rota, rotb, red, green, blue);
					
endmodule