data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff.v
data/verilator_xmls/051d9c30-2111-43c3-a04a-af7d84b54187.xml
module ff(CLK, D, Q, Qb);
input   CLK, D;
output  Q, Qb;

reg Q;
assign Qb = ~Q;


always @ ( posedge CLK)  
        Q <= D;



endmodule
module ff(CLK, D, Q, Qb);

input   CLK, D;
output  Q, Qb;

reg Q;
assign Qb = ~Q;


always @ ( posedge CLK)  
        Q <= D;



endmodule