data/full_repos/permissive/515624136/testbench/WSIGNAL_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515624136/testbench/WSIGNAL_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515624136/testbench/WSIGNAL_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/515624136/testbench/WSIGNAL_tb.v:55: syntax error, unexpected \'@\'\n @(posedge tb_clk_50)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module WSIGNAL_tb();



reg tb_clk_50;
reg tb_en;

wire Wsignal_Write;


WSIGNAL Wsignal(


.WSIGNAL_Clk(tb_clk_50),
.WSIGNAL_En(tb_en),

.WSIGNAL_RegFile_Write(Wsignal_Write)

);



always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end

initial
begin
	tb_en<=1'b0;
	@(posedge tb_clk_50)
	@(negedge tb_clk_50)
	tb_en<=1'b1;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_en<=1'b0;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	
		
	$stop;
	
end


endmodule
module WSIGNAL_tb();




reg tb_clk_50;
reg tb_en;

wire Wsignal_Write;


WSIGNAL Wsignal(


.WSIGNAL_Clk(tb_clk_50),
.WSIGNAL_En(tb_en),

.WSIGNAL_RegFile_Write(Wsignal_Write)

);



always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end

initial
begin
	tb_en<=1'b0;
	@(posedge tb_clk_50)
	@(negedge tb_clk_50)
	tb_en<=1'b1;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_en<=1'b0;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	
		
	$stop;
	
end


endmodule