data/full_repos/permissive/451577625/system/alu_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hF0F0F0F0; in_b = 32\'hABCDABCD; opcode = 4\'b1011;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h00000001; in_b = 32\'h1; opcode = 4\'b1010;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hFFFFFFFF; in_b = 32\'h0F0F0F0F; opcode = 4\'b0110;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hF0F0F0F0; in_b = 32\'h0F0F0F0F; opcode = 4\'b0111;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0000FFFF; in_b = 32\'h00000001; opcode = 4\'b0000;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0000FFFF; in_b = 32\'h000000FF; opcode = 4\'b0001;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'h0; in_b = 32\'h0; opcode = 4\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/alu_32.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_a = 32\'hFFFFFFF3; in_b = 32\'hB; opcode = 4\'b1000;   \n  ^\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/alu_32.v:114: Cell has missing pin: \'clk\'\n alu_32 DUT(.in_a (in_a),\n        ^~~\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/alu_32.v:114: Cell has missing pin: \'in_div_reset\'\n alu_32 DUT(.in_a (in_a),\n        ^~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:37: Cannot find file containing module: \'adder_32\'\n adder_32 adder(.in_x (r_a_pre_process),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:43: Cannot find file containing module: \'shift_rot_32\'\n shift_rot_32 shifter (.in_x (in_a),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:49: Cannot find file containing module: \'multiplier_32\'\n multiplier_32 multiplier (.in_x (in_a),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/alu_32.v:53: Cannot find file containing module: \'divider_32\'\n divider_32 divider (.clk (clk),\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:90: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_adder_sum_out\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b1011 : out_result = w_adder_sum_out;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:94: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_shift_rot_out\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0101 : out_result = w_shift_rot_out;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:95: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_and_32\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0110 : out_result = w_and_32;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/alu_32.v:96: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'w_or_32\' generates 32 bits.\n                                                                       : ... In instance alu_32_tb.DUT\n   4\'b0111 : out_result = w_or_32;   \n                        ^\n%Error: Exiting due to 4 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_32(input clk, input in_div_reset, input [31:0] in_a, input [31:0] in_b, input [3:0] in_opcode, output reg [63:0] out_result);




	wire [31:0] w_and_32;
	wire [31:0] w_or_32;
	wire [31:0] w_not_32;
	wire [31:0] w_adder_sum_out;
	wire [31:0] w_shift_rot_out;
	wire [63:0] w_multi_product_out;
	wire [63:0] w_div_out;
	wire w_adder_carry_out;
	
	reg [31:0] r_a_pre_process;
	reg [31:0] r_b_pre_process;
	reg [31:0] r_b_inverted;
	reg r_adder_carry_in;
	
	assign w_and_32 = in_a & in_b;
	assign w_or_32 = in_a | in_b;
	assign w_not_32 = ~r_b_pre_process;
	
	adder_32 adder(.in_x (r_a_pre_process),
		.in_y (r_b_inverted),
		.in_carry (r_adder_carry_in),
		.out_sum (w_adder_sum_out),
		.out_carry (w_adder_carry_out));
	
	shift_rot_32 shifter (.in_x (in_a),
		.in_y (in_b),
		.in_left (in_opcode[0]),
		.in_rot (in_opcode[1]),
		.out (w_shift_rot_out));
	
	multiplier_32 multiplier (.in_x (in_a),
		.in_y (in_b),
		.out_product (w_multi_product_out));
		
	divider_32 divider (.clk (clk),
		.in_reset (in_div_reset),
		.in_dividend (in_a),
		.in_divisor (in_b),
		.out_quotient (w_div_out[31:0]),
		.out_remainder (w_div_out[63:32]));

	always @(*) begin
		case(in_opcode)
			4'b1010,
			4'b1011 : begin
				r_b_pre_process = in_b;
				r_a_pre_process = 0;
			end
			default : begin
				r_a_pre_process = in_a;
				r_b_pre_process = in_b;
			end
		endcase
		
		case(in_opcode)
			4'b0001,
			4'b1010,
			4'b1011 : r_b_inverted = w_not_32;
			default : r_b_inverted = r_b_pre_process;
		endcase
		
		case(in_opcode)
			4'b0001,
			4'b1010 : r_adder_carry_in = 1;
			default : r_adder_carry_in = 0;
		endcase
		
		case(in_opcode)
			4'b0000,
			4'b0001,
			4'b1010,
			4'b1011 : out_result = w_adder_sum_out;
			4'b0010,
			4'b0011,
			4'b0100,
			4'b0101 : out_result = w_shift_rot_out;
			4'b0110 : out_result = w_and_32;
			4'b0111 : out_result = w_or_32;
			4'b1000 : out_result = w_multi_product_out;
			4'b1001 : out_result = w_div_out;
			default : out_result = 0;
		endcase
	end
	
endmodule
module alu_32(input clk, input in_div_reset, input [31:0] in_a, input [31:0] in_b, input [3:0] in_opcode, output reg [63:0] out_result);





	wire [31:0] w_and_32;
	wire [31:0] w_or_32;
	wire [31:0] w_not_32;
	wire [31:0] w_adder_sum_out;
	wire [31:0] w_shift_rot_out;
	wire [63:0] w_multi_product_out;
	wire [63:0] w_div_out;
	wire w_adder_carry_out;
	
	reg [31:0] r_a_pre_process;
	reg [31:0] r_b_pre_process;
	reg [31:0] r_b_inverted;
	reg r_adder_carry_in;
	
	assign w_and_32 = in_a & in_b;
	assign w_or_32 = in_a | in_b;
	assign w_not_32 = ~r_b_pre_process;
	
	adder_32 adder(.in_x (r_a_pre_process),
		.in_y (r_b_inverted),
		.in_carry (r_adder_carry_in),
		.out_sum (w_adder_sum_out),
		.out_carry (w_adder_carry_out));
	
	shift_rot_32 shifter (.in_x (in_a),
		.in_y (in_b),
		.in_left (in_opcode[0]),
		.in_rot (in_opcode[1]),
		.out (w_shift_rot_out));
	
	multiplier_32 multiplier (.in_x (in_a),
		.in_y (in_b),
		.out_product (w_multi_product_out));
		
	divider_32 divider (.clk (clk),
		.in_reset (in_div_reset),
		.in_dividend (in_a),
		.in_divisor (in_b),
		.out_quotient (w_div_out[31:0]),
		.out_remainder (w_div_out[63:32]));

	always @(*) begin
		case(in_opcode)
			4'b1010,
			4'b1011 : begin
				r_b_pre_process = in_b;
				r_a_pre_process = 0;
			end
			default : begin
				r_a_pre_process = in_a;
				r_b_pre_process = in_b;
			end
		endcase
		
		case(in_opcode)
			4'b0001,
			4'b1010,
			4'b1011 : r_b_inverted = w_not_32;
			default : r_b_inverted = r_b_pre_process;
		endcase
		
		case(in_opcode)
			4'b0001,
			4'b1010 : r_adder_carry_in = 1;
			default : r_adder_carry_in = 0;
		endcase
		
		case(in_opcode)
			4'b0000,
			4'b0001,
			4'b1010,
			4'b1011 : out_result = w_adder_sum_out;
			4'b0010,
			4'b0011,
			4'b0100,
			4'b0101 : out_result = w_shift_rot_out;
			4'b0110 : out_result = w_and_32;
			4'b0111 : out_result = w_or_32;
			4'b1000 : out_result = w_multi_product_out;
			4'b1001 : out_result = w_div_out;
			default : out_result = 0;
		endcase
	end
	
endmodule