data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_swpla.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_swpla.v:103: Cannot find file containing module: 'sink'\n   sink #(32) s0(.in (in));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sink\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sink.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sink.sv\n             sink\n             sink.v\n             sink.sv\n             obj_dir/sink\n             obj_dir/sink.v\n             obj_dir/sink.sv\n%Error: Exiting due to 1 error(s)\n"
module sparc_ifu_swpla(

   out, 

   in
   );

   input [31:0]  in;
   output 	 out;

   wire [31:0] 	 in;
   reg 		 out;
   

   always @ (in)
     begin
	      if (in[31:30] == 2'b01)
	        out = 1'b1;
	      else if (in[31:30] == 2'b00)
	        begin
	           if (in[24:22] == 3'b100)
	             out = 1'b0;
	           else
	             out = 1'b1;
	        end
	      else if (in[31:30] == 2'b10)
	        begin
	           if (in[24:23] == 2'b11)
	             out = 1'b1;
	           else if (in[24] == 1'b0)
	             begin
		              if (in[22] == 1'b0)
		                out = 1'b0;
		              else if ((in[22] == 1'b1) && (in[20:19] == 2'b00))

		                out = 1'b0;
		              else
		                out = 1'b1;
	             end
	           else
	             begin
		              if (in[22:19] == 4'h4)
		                out = 1'b1;
		              else if (in[22] == 1'b0)
		                out = 1'b0;
		              else if  ((in[22:19] == 4'hc) ||  (in[22:19] == 4'hf))
		                out = 1'b0;


		              else
		                out = 1'b1;
	             end
	        end
	      else
	        begin


             if (in[24] | in[23] | ~in[21])
	             out = 1'b1;




	           else if ((~in[23]) && (in[22:19] == 4'he))
	             out = 1'b0;
	           else if (in[22:21] == 2'b01)
	             out = 1'b0;
	           else
	             out = 1'b1;
	        end
     end

   sink #(32) s0(.in (in));
   
endmodule
module sparc_ifu_swpla(

   out, 

   in
   );


   input [31:0]  in;
   output 	 out;

   wire [31:0] 	 in;
   reg 		 out;
   

   always @ (in)
     begin
	      if (in[31:30] == 2'b01)
	        out = 1'b1;
	      else if (in[31:30] == 2'b00)
	        begin
	           if (in[24:22] == 3'b100)
	             out = 1'b0;
	           else
	             out = 1'b1;
	        end
	      else if (in[31:30] == 2'b10)
	        begin
	           if (in[24:23] == 2'b11)
	             out = 1'b1;
	           else if (in[24] == 1'b0)
	             begin
		              if (in[22] == 1'b0)
		                out = 1'b0;
		              else if ((in[22] == 1'b1) && (in[20:19] == 2'b00))

		                out = 1'b0;
		              else
		                out = 1'b1;
	             end
	           else
	             begin
		              if (in[22:19] == 4'h4)
		                out = 1'b1;
		              else if (in[22] == 1'b0)
		                out = 1'b0;
		              else if  ((in[22:19] == 4'hc) ||  (in[22:19] == 4'hf))
		                out = 1'b0;


		              else
		                out = 1'b1;
	             end
	        end
	      else
	        begin


             if (in[24] | in[23] | ~in[21])
	             out = 1'b1;




	           else if ((~in[23]) && (in[22:19] == 4'he))
	             out = 1'b0;
	           else if (in[22:21] == 2'b01)
	             out = 1'b0;
	           else
	             out = 1'b1;
	        end
     end

   sink #(32) s0(.in (in));
   
endmodule