data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:11: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb,data/full_repos/permissive/447976230/sim_clks_rsts.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb,data/full_repos/permissive/447976230/sim_clks_rsts.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb,data/full_repos/permissive/447976230/sim_clks_rsts.vh.sv\n             sim_clks_rsts.vh\n             sim_clks_rsts.vh.v\n             sim_clks_rsts.vh.sv\n             obj_dir/sim_clks_rsts.vh\n             obj_dir/sim_clks_rsts.vh.v\n             obj_dir/sim_clks_rsts.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:12: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:15: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("e310_io_tb",6,1)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:15: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("e310_io_tb",6,1)\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:18: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(rx_clk, 16.27, 50)  \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:19: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(areset, 0, 100)   \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:65: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:65: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for reset");\n                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:66: syntax error, unexpected \'@\'\n    while (areset) @(posedge radio_clk);\n                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:67: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE((~areset));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:67: syntax error, unexpected \';\'\n    `TEST_CASE_DONE((~areset));\n                              ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:69: syntax error, unexpected \'@\'\n    repeat (10) @(posedge radio_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:71: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Test RX channel 0,1");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:71: syntax error, unexpected \';\'\n    `TEST_CASE_START("Test RX channel 0,1");\n                                           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:74: syntax error, unexpected \'@\'\n    repeat (10) @(posedge radio_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:75: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:78: syntax error, unexpected \'@\'\n          @(posedge radio_clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:81: syntax error, unexpected \'@\'\n          @(negedge radio_clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:87: syntax error, unexpected \'@\'\n        while ({rx_i0, rx_q0} == 24\'d0) @(posedge radio_clk);\n                                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:90: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:90: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:91: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:91: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:92: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_i1 == i,   "RX1 I incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:92: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_i1 == i,   "RX1 I incorrect!");\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:93: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:93: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:98: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:98: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:100: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                 : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:100: syntax error, unexpected \';\'\n    `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");\n                                                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:104: syntax error, unexpected \'@\'\n    repeat (10) @(posedge radio_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:105: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:108: syntax error, unexpected \'@\'\n          @(posedge radio_clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:111: syntax error, unexpected \'@\'\n          @(negedge radio_clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:116: syntax error, unexpected \'@\'\n        while ({rx_i0, rx_q0} == 24\'d0) @(posedge radio_clk);\n                                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:119: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:119: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:120: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:120: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:122: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:122: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:123: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:123: syntax error, unexpected \',\'\n          `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:128: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:128: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:130: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                 : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Test TX channel 0");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:130: syntax error, unexpected \';\'\n    `TEST_CASE_START("Test TX channel 0");\n                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:136: syntax error, unexpected \'@\'\n    repeat (10) @(posedge radio_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv:138: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module e310_io_tb();
  `TEST_BENCH_INIT("e310_io_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(rx_clk, 16.27, 50)
  `DEFINE_RESET(areset, 0, 100)

  reg mimo;
  wire radio_clk, radio_rst;
  wire [11:0] rx_i0, rx_i1, rx_q0, rx_q1;
  wire rx_stb;
  reg [11:0] tx_i0, tx_i1, tx_q0, tx_q1;
  wire tx_stb;
  reg rx_frame;
  reg [11:0] rx_data;
  wire tx_clk;
  wire tx_frame;
  wire [11:0] tx_data;
  e310_io e310_io (
    .areset(areset),
    .mimo(mimo),
    .radio_clk(radio_clk),
    .radio_rst(radio_rst),
    .rx_i0(rx_i0),
    .rx_q0(rx_q0),
    .rx_i1(rx_i1),
    .rx_q1(rx_q1),
    .rx_stb(rx_stb),
    .tx_i0(tx_i0),
    .tx_q0(tx_q0),
    .tx_i1(tx_i1),
    .tx_q1(tx_q1),
    .tx_stb(tx_stb),
    .rx_clk(rx_clk),
    .rx_frame(rx_frame),
    .rx_data(rx_data),
    .tx_clk(tx_clk),
    .tx_frame(tx_frame),
    .tx_data(tx_data));


  initial begin : tb_main
    mimo     <= 1'b0;
    tx_i0    <= 'd0;
    tx_q0    <= 'd0;
    tx_i1    <= 'd0;
    tx_q1    <= 'd0;
    rx_data  <= 'd0;
    rx_frame <= 1'b0;
    `TEST_CASE_START("Wait for reset");
    while (areset) @(posedge radio_clk);
    `TEST_CASE_DONE((~areset));

    repeat (10) @(posedge radio_clk);

    `TEST_CASE_START("Test RX channel 0,1");
    mimo      <= 1'b0;
    rx_data   <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          @(posedge radio_clk);
          rx_frame  <= 1'b1;
          rx_data   <= i;
          @(negedge radio_clk);
          rx_frame  <= 1'b0;
          rx_data   <= i+1;
        end
      end
      begin
        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
        for (int i = 1; i < 64; i = i + 2) begin

          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
          `ASSERT_ERROR(rx_i1 == i,   "RX1 I incorrect!");
          `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");
          @(posedge radio_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");
    mimo      <= 1'b1;
    rx_frame  <= 1'b0;
    rx_data   <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          @(posedge radio_clk);
          rx_frame  <= ~rx_frame;
          rx_data   <= i;
          @(negedge radio_clk);
          rx_data   <= i+1;
        end
      end
      begin
        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
        for (int i = 1; i < 32; i = i + 4) begin

          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
          @(posedge radio_clk);
          `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");
          `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");
          @(posedge radio_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 0");
    mimo  <= 1'b0;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);

    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          tx_i0 <= i;
          tx_q0 <= i+1;
          @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 64; i = i + 2) begin

          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 1");
    mimo  <= 1'b0;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          tx_i1 <= i;
          tx_q1 <= i+1;
          @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 64; i = i + 2) begin
          `ASSERT_ERROR(tx_data  == i, "TX1 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX1 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 0 & 1 (MIMO)");
    mimo  <= 1'b1;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 32; i = i + 4) begin
          tx_i0 <= i;
          tx_q0 <= i+1;
          tx_i1 <= i+2;
          tx_q1 <= i+3;
          @(posedge radio_clk);
          while (tx_stb) @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 32; i = i + 4) begin
          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(posedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+2, "TX1 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+3, "TX1 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);
    `TEST_BENCH_DONE;
  end

endmodule
module e310_io_tb();

  `TEST_BENCH_INIT("e310_io_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(rx_clk, 16.27, 50)
  `DEFINE_RESET(areset, 0, 100)

  reg mimo;
  wire radio_clk, radio_rst;
  wire [11:0] rx_i0, rx_i1, rx_q0, rx_q1;
  wire rx_stb;
  reg [11:0] tx_i0, tx_i1, tx_q0, tx_q1;
  wire tx_stb;
  reg rx_frame;
  reg [11:0] rx_data;
  wire tx_clk;
  wire tx_frame;
  wire [11:0] tx_data;
  e310_io e310_io (
    .areset(areset),
    .mimo(mimo),
    .radio_clk(radio_clk),
    .radio_rst(radio_rst),
    .rx_i0(rx_i0),
    .rx_q0(rx_q0),
    .rx_i1(rx_i1),
    .rx_q1(rx_q1),
    .rx_stb(rx_stb),
    .tx_i0(tx_i0),
    .tx_q0(tx_q0),
    .tx_i1(tx_i1),
    .tx_q1(tx_q1),
    .tx_stb(tx_stb),
    .rx_clk(rx_clk),
    .rx_frame(rx_frame),
    .rx_data(rx_data),
    .tx_clk(tx_clk),
    .tx_frame(tx_frame),
    .tx_data(tx_data));


  initial begin : tb_main
    mimo     <= 1'b0;
    tx_i0    <= 'd0;
    tx_q0    <= 'd0;
    tx_i1    <= 'd0;
    tx_q1    <= 'd0;
    rx_data  <= 'd0;
    rx_frame <= 1'b0;
    `TEST_CASE_START("Wait for reset");
    while (areset) @(posedge radio_clk);
    `TEST_CASE_DONE((~areset));

    repeat (10) @(posedge radio_clk);

    `TEST_CASE_START("Test RX channel 0,1");
    mimo      <= 1'b0;
    rx_data   <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          @(posedge radio_clk);
          rx_frame  <= 1'b1;
          rx_data   <= i;
          @(negedge radio_clk);
          rx_frame  <= 1'b0;
          rx_data   <= i+1;
        end
      end
      begin
        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
        for (int i = 1; i < 64; i = i + 2) begin

          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
          `ASSERT_ERROR(rx_i1 == i,   "RX1 I incorrect!");
          `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");
          @(posedge radio_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");
    mimo      <= 1'b1;
    rx_frame  <= 1'b0;
    rx_data   <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          @(posedge radio_clk);
          rx_frame  <= ~rx_frame;
          rx_data   <= i;
          @(negedge radio_clk);
          rx_data   <= i+1;
        end
      end
      begin
        while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
        for (int i = 1; i < 32; i = i + 4) begin

          `ASSERT_ERROR(rx_i0 == i,   "RX0 I incorrect!");
          `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
          @(posedge radio_clk);
          `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");
          `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");
          @(posedge radio_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 0");
    mimo  <= 1'b0;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);

    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          tx_i0 <= i;
          tx_q0 <= i+1;
          @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 64; i = i + 2) begin

          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 1");
    mimo  <= 1'b0;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 64; i = i + 2) begin
          tx_i1 <= i;
          tx_q1 <= i+1;
          @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 64; i = i + 2) begin
          `ASSERT_ERROR(tx_data  == i, "TX1 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX1 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Test TX channel 0 & 1 (MIMO)");
    mimo  <= 1'b1;
    tx_i0 <= 'd0;
    tx_q0 <= 'd0;
    tx_i1 <= 'd0;
    tx_q1 <= 'd0;
    repeat (10) @(posedge radio_clk);
    fork
      begin
        for (int i = 1; i < 32; i = i + 4) begin
          tx_i0 <= i;
          tx_q0 <= i+1;
          tx_i1 <= i+2;
          tx_q1 <= i+3;
          @(posedge radio_clk);
          while (tx_stb) @(posedge radio_clk);
        end
      end
      begin
        while (tx_data == 12'd0) @(posedge tx_clk);
        for (int i = 1; i < 32; i = i + 4) begin
          `ASSERT_ERROR(tx_data  == i, "TX0 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+1, "TX0 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
          @(posedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+2, "TX1 I data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(negedge tx_clk);
          `ASSERT_ERROR(tx_data  == i+3, "TX1 Q data incorrect!");
          `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
          @(posedge tx_clk);
        end
      end
    join
    `TEST_CASE_DONE(1);
    `TEST_BENCH_DONE;
  end

endmodule