data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:81: Signal definition not found, creating implicitly: \'dram_io_clk_inv_d1\'\nwire dram_cnt_enable = rst_l & (dram_io_clk_inv_d1 ? dram_io_pad_enable_d1 : dram_io_pad_enable);\n                                ^~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:81: Signal definition not found, creating implicitly: \'dram_io_pad_enable_d1\'\n                                                                                                    : ... Suggested alternative: \'dram_io_pad_enable\'\nwire dram_cnt_enable = rst_l & (dram_io_clk_inv_d1 ? dram_io_pad_enable_d1 : dram_io_pad_enable);\n                                                     ^~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:100: Signal definition not found, creating implicitly: \'dram_cnt_enable_d1\'\n                                                                                                     : ... Suggested alternative: \'dram_cnt_enable\'\n    dram_cnt_enable_d1 | pad_data_valid_in ? pad_pos_cnt[1:0] + 2\'h1 : pad_pos_cnt[1:0]) :\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:67: Cannot find file containing module: \'dffrl_s\'\ndffrl_s #(1) ff_clk_inv(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s.sv\n             dffrl_s\n             dffrl_s.v\n             dffrl_s.sv\n             obj_dir/dffrl_s\n             obj_dir/dffrl_s.v\n             obj_dir/dffrl_s.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:75: Cannot find file containing module: \'dffrl_s\'\ndffrl_s #(1) ff_cnt_en(\n^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:83: Cannot find file containing module: \'dffrl_async\'\ndffrl_async #(1) ff_cnt_en_d2(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:92: Cannot find file containing module: \'dff_s\'\ndff_s #(1) ff_data_vld(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:103: Cannot find file containing module: \'dffrl_async\'\ndffrl_async #(1)       ff_pos_cnt0(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:111: Cannot find file containing module: \'dffrl_async\'\ndffrl_async #(1)       ff_pos_cnt1(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:122: Cannot find file containing module: \'dff_s\'\ndff_s #(1)        ff_neg_cnt0(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pad_logic.v:129: Cannot find file containing module: \'dff_s\'\ndff_s #(1)        ff_neg_cnt1(\n^~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module dram_pad_logic(

   pad_logic_clk_so, 
   io_dram_data_valid, pad_pos_cnt, 
   pad_neg_cnt, 

   rst_l, arst_l, clk, pad_logic_clk_si, pad_logic_clk_se, testmode_l,
   dram_io_pad_clk_inv, dram_io_pad_enable, burst_length_four
   );




input			rst_l;
input			arst_l;
input			clk;
input			testmode_l;
input			pad_logic_clk_si;
input			pad_logic_clk_se;
input		 	dram_io_pad_clk_inv;
input			dram_io_pad_enable;
input			burst_length_four;




output			pad_logic_clk_so;
output			io_dram_data_valid;
output [1:0]		pad_pos_cnt;
output [1:0]		pad_neg_cnt;


wire			cnt_clk;
wire			pad_data_valid_in;
wire			pad_data_valid;
wire [1:0]		pad_pos_cnt_in;






wire tclk = testmode_l ? ~clk : clk;



dffrl_s #(1) ff_clk_inv(
        .din(dram_io_pad_clk_inv),
        .q(dram_io_clk_inv_d1),
	.rst_l(rst_l),
        .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si), .so(pad_logic_clk_si1));



dffrl_s #(1) ff_cnt_en(
        .din(dram_io_pad_enable),
        .q(dram_io_pad_enable_d1),
	.rst_l(rst_l),
        .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si1), .so(pad_logic_clk_si2));

wire dram_cnt_enable = rst_l & (dram_io_clk_inv_d1 ? dram_io_pad_enable_d1 : dram_io_pad_enable);

dffrl_async #(1) ff_cnt_en_d2(
        .din(dram_cnt_enable),
        .q(dram_cnt_enable_d1),
	.rst_l(arst_l),
        .clk(tclk), .se(pad_logic_clk_se), .si(pad_logic_clk_si5), .so(pad_logic_clk_si6));


assign pad_data_valid_in = (pad_pos_cnt[1:0] == 1) | (pad_pos_cnt[1:0] == 3) ;

dff_s #(1) ff_data_vld(
                .din(pad_data_valid_in),
                .q(io_dram_data_valid),
                .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si2), 
			.so(pad_logic_clk_si3));


assign pad_pos_cnt_in[1:0] = {rst_l, rst_l} & (burst_length_four ? (
				dram_cnt_enable_d1 | pad_data_valid_in ? pad_pos_cnt[1:0] + 2'h1 : pad_pos_cnt[1:0]) :
				pad_pos_cnt[1:0] + 1'b1);

dffrl_async #(1)       ff_pos_cnt0(
                .din(pad_pos_cnt_in[0]),
                .q(pad_pos_cnt[0]),
                .rst_l(arst_l),
                .clk(clk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si3), 
			.so(pad_logic_clk_si4));

dffrl_async #(1)       ff_pos_cnt1(
                .din(pad_pos_cnt_in[1]),
                .q(pad_pos_cnt[1]),
                .rst_l(arst_l),
                .clk(clk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si4), 
			.so(pad_logic_clk_si5));


wire [1:0]      pad_neg_cnt;

dff_s #(1)        ff_neg_cnt0(
                .din(pad_pos_cnt[0]),
                .q(pad_neg_cnt[0]),
                .clk(tclk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si6), 
			.so(pad_logic_clk_si7));

dff_s #(1)        ff_neg_cnt1(
                .din(pad_pos_cnt[1]),
                .q(pad_neg_cnt[1]),
                .clk(tclk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si7), 
			.so(pad_logic_clk_so));

endmodule
module dram_pad_logic(

   pad_logic_clk_so, 
   io_dram_data_valid, pad_pos_cnt, 
   pad_neg_cnt, 

   rst_l, arst_l, clk, pad_logic_clk_si, pad_logic_clk_se, testmode_l,
   dram_io_pad_clk_inv, dram_io_pad_enable, burst_length_four
   );





input			rst_l;
input			arst_l;
input			clk;
input			testmode_l;
input			pad_logic_clk_si;
input			pad_logic_clk_se;
input		 	dram_io_pad_clk_inv;
input			dram_io_pad_enable;
input			burst_length_four;




output			pad_logic_clk_so;
output			io_dram_data_valid;
output [1:0]		pad_pos_cnt;
output [1:0]		pad_neg_cnt;


wire			cnt_clk;
wire			pad_data_valid_in;
wire			pad_data_valid;
wire [1:0]		pad_pos_cnt_in;






wire tclk = testmode_l ? ~clk : clk;



dffrl_s #(1) ff_clk_inv(
        .din(dram_io_pad_clk_inv),
        .q(dram_io_clk_inv_d1),
	.rst_l(rst_l),
        .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si), .so(pad_logic_clk_si1));



dffrl_s #(1) ff_cnt_en(
        .din(dram_io_pad_enable),
        .q(dram_io_pad_enable_d1),
	.rst_l(rst_l),
        .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si1), .so(pad_logic_clk_si2));

wire dram_cnt_enable = rst_l & (dram_io_clk_inv_d1 ? dram_io_pad_enable_d1 : dram_io_pad_enable);

dffrl_async #(1) ff_cnt_en_d2(
        .din(dram_cnt_enable),
        .q(dram_cnt_enable_d1),
	.rst_l(arst_l),
        .clk(tclk), .se(pad_logic_clk_se), .si(pad_logic_clk_si5), .so(pad_logic_clk_si6));


assign pad_data_valid_in = (pad_pos_cnt[1:0] == 1) | (pad_pos_cnt[1:0] == 3) ;

dff_s #(1) ff_data_vld(
                .din(pad_data_valid_in),
                .q(io_dram_data_valid),
                .clk(clk), .se(pad_logic_clk_se), .si(pad_logic_clk_si2), 
			.so(pad_logic_clk_si3));


assign pad_pos_cnt_in[1:0] = {rst_l, rst_l} & (burst_length_four ? (
				dram_cnt_enable_d1 | pad_data_valid_in ? pad_pos_cnt[1:0] + 2'h1 : pad_pos_cnt[1:0]) :
				pad_pos_cnt[1:0] + 1'b1);

dffrl_async #(1)       ff_pos_cnt0(
                .din(pad_pos_cnt_in[0]),
                .q(pad_pos_cnt[0]),
                .rst_l(arst_l),
                .clk(clk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si3), 
			.so(pad_logic_clk_si4));

dffrl_async #(1)       ff_pos_cnt1(
                .din(pad_pos_cnt_in[1]),
                .q(pad_pos_cnt[1]),
                .rst_l(arst_l),
                .clk(clk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si4), 
			.so(pad_logic_clk_si5));


wire [1:0]      pad_neg_cnt;

dff_s #(1)        ff_neg_cnt0(
                .din(pad_pos_cnt[0]),
                .q(pad_neg_cnt[0]),
                .clk(tclk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si6), 
			.so(pad_logic_clk_si7));

dff_s #(1)        ff_neg_cnt1(
                .din(pad_pos_cnt[1]),
                .q(pad_neg_cnt[1]),
                .clk(tclk), 
		.se(pad_logic_clk_se), .si(pad_logic_clk_si7), 
			.so(pad_logic_clk_so));

endmodule