data/full_repos/permissive/446312960/Verilog_Simulation/01_hello/tb_testbench.v
1: b'%Error: data/full_repos/permissive/446312960/Verilog_Simulation/01_hello/tb_testbench.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/01_hello/tb_testbench.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);               \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire n1,n2,n3;
or_test tester(n1,n2,n3);


or_gate dut   (n1,n2,n3);

always @( n1, n2, n3 )
begin
    $display("%b %b %b",n1,n2,n3);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire n1,n2,n3;
or_test tester(n1,n2,n3);


or_gate dut   (n1,n2,n3);

always @( n1, n2, n3 )
begin
    $display("%b %b %b",n1,n2,n3);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule