data/full_repos/permissive/500341183/verilog/gl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/500341183/verilog/gl/user_project_wrapper.v:57: Cannot find file containing module: 'user_proj_example'\n user_proj_example mprj (.iClk(wb_clk_i),\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500341183/verilog/gl,data/full_repos/permissive/500341183/user_proj_example\n             data/full_repos/permissive/500341183/verilog/gl,data/full_repos/permissive/500341183/user_proj_example.v\n             data/full_repos/permissive/500341183/verilog/gl,data/full_repos/permissive/500341183/user_proj_example.sv\n             user_proj_example\n             user_proj_example.v\n             user_proj_example.sv\n             obj_dir/user_proj_example\n             obj_dir/user_proj_example.v\n             obj_dir/user_proj_example.sv\n%Error: Exiting due to 1 error(s)\n"
module user_project_wrapper (user_clock2,
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_cyc_i,
    wbs_stb_i,
    wbs_we_i,
    analog_io,
    io_in,
    io_oeb,
    io_out,
    la_data_in,
    la_data_out,
    la_oenb,
    user_irq,
    wbs_adr_i,
    wbs_dat_i,
    wbs_dat_o,
    wbs_sel_i);
 input user_clock2;
 input vccd1;
 input vccd2;
 input vdda1;
 input vdda2;
 input vssa1;
 input vssa2;
 input vssd1;
 input vssd2;
 input wb_clk_i;
 input wb_rst_i;
 output wbs_ack_o;
 input wbs_cyc_i;
 input wbs_stb_i;
 input wbs_we_i;
 inout [28:0] analog_io;
 input [37:0] io_in;
 output [37:0] io_oeb;
 output [37:0] io_out;
 input [127:0] la_data_in;
 output [127:0] la_data_out;
 input [127:0] la_oenb;
 output [2:0] user_irq;
 input [31:0] wbs_adr_i;
 input [31:0] wbs_dat_i;
 output [31:0] wbs_dat_o;
 input [3:0] wbs_sel_i;


 user_proj_example mprj (.iClk(wb_clk_i),
    .iRst_n(wb_rst_i),
    .iSDAT(la_data_in[1]),
    .iSVAL(la_data_in[0]),
    .iValid(wbs_we_i),
    .oSDAT(la_data_out[1]),
    .oSVAL(la_data_out[0]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .iSize({wbs_sel_i[2],
    wbs_sel_i[1],
    wbs_sel_i[0]}));
endmodule
module user_project_wrapper (user_clock2,
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_cyc_i,
    wbs_stb_i,
    wbs_we_i,
    analog_io,
    io_in,
    io_oeb,
    io_out,
    la_data_in,
    la_data_out,
    la_oenb,
    user_irq,
    wbs_adr_i,
    wbs_dat_i,
    wbs_dat_o,
    wbs_sel_i);

 input user_clock2;
 input vccd1;
 input vccd2;
 input vdda1;
 input vdda2;
 input vssa1;
 input vssa2;
 input vssd1;
 input vssd2;
 input wb_clk_i;
 input wb_rst_i;
 output wbs_ack_o;
 input wbs_cyc_i;
 input wbs_stb_i;
 input wbs_we_i;
 inout [28:0] analog_io;
 input [37:0] io_in;
 output [37:0] io_oeb;
 output [37:0] io_out;
 input [127:0] la_data_in;
 output [127:0] la_data_out;
 input [127:0] la_oenb;
 output [2:0] user_irq;
 input [31:0] wbs_adr_i;
 input [31:0] wbs_dat_i;
 output [31:0] wbs_dat_o;
 input [3:0] wbs_sel_i;


 user_proj_example mprj (.iClk(wb_clk_i),
    .iRst_n(wb_rst_i),
    .iSDAT(la_data_in[1]),
    .iSVAL(la_data_in[0]),
    .iValid(wbs_we_i),
    .oSDAT(la_data_out[1]),
    .oSVAL(la_data_out[0]),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .iSize({wbs_sel_i[2],
    wbs_sel_i[1],
    wbs_sel_i[0]}));
endmodule