data/full_repos/permissive/42434302/ivltests/size_cast2.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/size_cast2.v:23: syntax error, unexpected logic, expecting IDENTIFIER or \'=\' or do or final\n  reg logic[6:0] a;\n      ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/size_cast2.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module resize_test();
  logic [4:0] result;
  resize dut(result);

  initial begin
    #1;

    if(result !== 5'd9) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
  end
endmodule
module resize_test();

  logic [4:0] result;
  resize dut(result);

  initial begin
    #1;

    if(result !== 5'd9) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
  end
endmodule