data/full_repos/permissive/523744529/Verilog/SpiSlave.v
1: b'%Error: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:21: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                  : ... In instance SPI_Slave\n   MISO          <= {MISO[6:0], MOSI};\n                         ^\n%Error: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:21: Extracting 7 bits from only 1 bit number\n                                                                  : ... In instance SPI_Slave\n   MISO          <= {MISO[6:0], MOSI};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:21: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                          : ... In instance SPI_Slave\n   MISO          <= {MISO[6:0], MOSI};\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:30: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_BYTE\' generates 8 bits.\n                                                                          : ... In instance SPI_Slave\n   MISO <= TX_BYTE;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:35: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'rx_bits_count\' generates 3 bits.\n                                                                          : ... In instance SPI_Slave\n assign RX_DONE = (rx_bits_count == 8) ? 1\'b1 : 1\'b0;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/523744529/Verilog/SpiSlave.v:36: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'MISO\' generates 1 bits.\n                                                                          : ... In instance SPI_Slave\n assign RX_BYTE = MISO;\n                ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module SPI_Slave (

	input  wire CLK,
	input  wire CS,
	input  wire MOSI,
	output reg  MISO,
	

	output wire [7:0] RX_BYTE,
	output wire       RX_DONE,
	input  wire [7:0] TX_BYTE,
	input  wire       WE,
	input  wire       INNER_CLK
);
	reg [2:0] rx_bits_count;

	always @(posedge CLK)
	begin
		if (CS)
		begin
			MISO          <= {MISO[6:0], MOSI};
			rx_bits_count <= rx_bits_count + 1;
		end
	end

	always @(posedge INNER_CLK)
	begin
		if (WE)
		begin
			MISO <= TX_BYTE;
			rx_bits_count <= 0;
		end
	end

	assign RX_DONE = (rx_bits_count == 8) ? 1'b1 : 1'b0;
	assign RX_BYTE = MISO;
endmodule
module SPI_Slave (

	input  wire CLK,
	input  wire CS,
	input  wire MOSI,
	output reg  MISO,
	

	output wire [7:0] RX_BYTE,
	output wire       RX_DONE,
	input  wire [7:0] TX_BYTE,
	input  wire       WE,
	input  wire       INNER_CLK
);

	reg [2:0] rx_bits_count;

	always @(posedge CLK)
	begin
		if (CS)
		begin
			MISO          <= {MISO[6:0], MOSI};
			rx_bits_count <= rx_bits_count + 1;
		end
	end

	always @(posedge INNER_CLK)
	begin
		if (WE)
		begin
			MISO <= TX_BYTE;
			rx_bits_count <= 0;
		end
	end

	assign RX_DONE = (rx_bits_count == 8) ? 1'b1 : 1'b0;
	assign RX_BYTE = MISO;
endmodule