data/full_repos/permissive/516759878/RTL/Mux_seven_seg.v
1: b"%Error: data/full_repos/permissive/516759878/RTL/Mux_seven_seg.v:37: Cannot find file containing module: 'count_2bit'\n count_2bit COUNTER(.i_clk(i_clk), .count_out(o_cnt));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/count_2bit\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/count_2bit.v\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/count_2bit.sv\n             count_2bit\n             count_2bit.v\n             count_2bit.sv\n             obj_dir/count_2bit\n             obj_dir/count_2bit.v\n             obj_dir/count_2bit.sv\n%Error: Exiting due to 1 error(s)\n"
module Mux_seven_seg(
input i_clk ,  

input [`WIDTH_SEG-1:0]o_seg1 ,
input [`WIDTH_SEG-1:0]o_seg2 ,
input [`WIDTH_SEG-1:0] o_seg3 ,
input [`WIDTH_SEG-1:0] o_seg4 , 
output reg [`WIDTH_EN-1:0] o_en  , 
output reg [`WIDTH_SEG-1:0] o_seg
 );
 wire[1:0] o_cnt;
 count_2bit COUNTER(.i_clk(i_clk), .count_out(o_cnt));
    
 
 always @(*)
    begin
          case (o_cnt)
          2'b00: begin
                    o_seg = o_seg1 ;
                    o_en = 4'b1110;
                     end 
         2'b01: begin
                    o_seg = o_seg2 ;
                    o_en = 4'b1101;
                     end  
         2'b10: begin
                    o_seg = o_seg3 ;
                    o_en = 4'b1011;
                     end                 
         default : begin 
                        o_seg = o_seg4;
                        o_en  = 4'b0111;
                        end
              endcase
          end               

                   
endmodule
module Mux_seven_seg(
input i_clk ,  

input [`WIDTH_SEG-1:0]o_seg1 ,
input [`WIDTH_SEG-1:0]o_seg2 ,
input [`WIDTH_SEG-1:0] o_seg3 ,
input [`WIDTH_SEG-1:0] o_seg4 , 
output reg [`WIDTH_EN-1:0] o_en  , 
output reg [`WIDTH_SEG-1:0] o_seg
 );

 wire[1:0] o_cnt;
 count_2bit COUNTER(.i_clk(i_clk), .count_out(o_cnt));
    
 
 always @(*)
    begin
          case (o_cnt)
          2'b00: begin
                    o_seg = o_seg1 ;
                    o_en = 4'b1110;
                     end 
         2'b01: begin
                    o_seg = o_seg2 ;
                    o_en = 4'b1101;
                     end  
         2'b10: begin
                    o_seg = o_seg3 ;
                    o_en = 4'b1011;
                     end                 
         default : begin 
                        o_seg = o_seg4;
                        o_en  = 4'b0111;
                        end
              endcase
          end               

                   
endmodule