data/full_repos/permissive/43264243/utx.v
1: b'%Error: data/full_repos/permissive/43264243/utx.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/utx.v:45: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/43264243/utx.v:52: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module baudcounter(clk, rstn, arm, baudce);
	input clk;
	input rstn;
	input arm;
	output reg baudce;

	reg [10:0] baudcntr;
	
	always @(*)
		baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1'b1 : 1'b0;
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0)
			baudcntr <= 0;
		else begin
			if(arm) begin
				if(baudcntr == `BAUDRATE_DIVISOR)
					baudcntr <= 0;
				else	
					baudcntr <= baudcntr + 1'b1;
			end else
				baudcntr <= 0;
		end
	end
endmodule
module baudcounter(clk, rstn, arm, baudce);

	input clk;
	input rstn;
	input arm;
	output reg baudce;

	reg [10:0] baudcntr;
	
	always @(*)
		baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1'b1 : 1'b0;
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0)
			baudcntr <= 0;
		else begin
			if(arm) begin
				if(baudcntr == `BAUDRATE_DIVISOR)
					baudcntr <= 0;
				else	
					baudcntr <= baudcntr + 1'b1;
			end else
				baudcntr <= 0;
		end
	end
endmodule