data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v
1: b"%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:21: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(23)(clk, reset, clk_cnt);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:22: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(15)(clk, reset, clk_sel);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:24: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select#(4)(clk_sel, reset, seg7_sel);\n                ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:36: syntax error, unexpected '(', expecting IDENTIFIER\nryg_ctl (clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);\n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module bcd_to_seg7(bcd_in,seg7);

input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule
module bcd_to_seg7(bcd_in,seg7);


input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule