data/full_repos/permissive/516818930/controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:40: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                    : ... In instance controller\ninitial main_road_light<=3\'b001;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance controller\ninitial side_road_light<=3\'b100;  \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:50: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                    : ... In instance controller\n               main_road_light<=3\'b001;  \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:51: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance controller\n               side_road_light<=3\'b100;  \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:59: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                    : ... In instance controller\n                main_road_light<=3\'b010;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:60: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance controller\n                side_road_light<=3\'b100;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:66: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance controller\n                main_road_light<=3\'b100;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:67: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                    : ... In instance controller\n                side_road_light<=3\'b001;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:74: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance controller\n                main_road_light<=3\'b100;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/516818930/controller.v:75: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                    : ... In instance controller\n                side_road_light<=3\'b010;   \n                               ^~\n%Error: Exiting due to 10 warning(s)\n'
module controller(main_road_light,side_road_light,SENSOR,clk,second);
parameter MG_SR=2'b00,
        MY_SR=2'b01,
        MR_SG=2'b10,
        MR_SY=2'b11;
    
input SENSOR,
    clk;
output reg[3:0] main_road_light,
                side_road_light;
reg[1:0] state,next_state;
output reg[7:0] second=-1;


initial state<=2'b00;
initial main_road_light<=3'b001;
initial side_road_light<=3'b100;

always@(posedge clk)begin 
    state<=next_state;
end
always @(*) begin
    case(state) 
        MG_SR:
            begin
               main_road_light<=3'b001;
               side_road_light<=3'b100;
               
               if((SENSOR==1))begin 
                       next_state<=MY_SR;end
               
            end
        MY_SR:
            begin
                main_road_light<=3'b010;
                side_road_light<=3'b100;
                    if(second==9)begin
                    next_state<=MR_SG;end
            end
        MR_SG:
            begin
                main_road_light<=3'b100;
                side_road_light<=3'b001;
                    if(second==19)begin
                                                                           
                    next_state<=MR_SY;end
            end
        MR_SY:
            begin
                main_road_light<=3'b100;
                side_road_light<=3'b010;
                if(SENSOR==0) begin       
                    next_state<=MG_SR;end
            end
        default state<=MG_SR;
        endcase
 end
 
 always@(posedge clk)begin
    if(state!=next_state)begin
        state<=next_state;
        second<=0;end
     else begin
        second<=second+1;end
 end
    
 endmodule
module controller(main_road_light,side_road_light,SENSOR,clk,second);

parameter MG_SR=2'b00,
        MY_SR=2'b01,
        MR_SG=2'b10,
        MR_SY=2'b11;
    
input SENSOR,
    clk;
output reg[3:0] main_road_light,
                side_road_light;
reg[1:0] state,next_state;
output reg[7:0] second=-1;


initial state<=2'b00;
initial main_road_light<=3'b001;
initial side_road_light<=3'b100;

always@(posedge clk)begin 
    state<=next_state;
end
always @(*) begin
    case(state) 
        MG_SR:
            begin
               main_road_light<=3'b001;
               side_road_light<=3'b100;
               
               if((SENSOR==1))begin 
                       next_state<=MY_SR;end
               
            end
        MY_SR:
            begin
                main_road_light<=3'b010;
                side_road_light<=3'b100;
                    if(second==9)begin
                    next_state<=MR_SG;end
            end
        MR_SG:
            begin
                main_road_light<=3'b100;
                side_road_light<=3'b001;
                    if(second==19)begin
                                                                           
                    next_state<=MR_SY;end
            end
        MR_SY:
            begin
                main_road_light<=3'b100;
                side_road_light<=3'b010;
                if(SENSOR==0) begin       
                    next_state<=MG_SR;end
            end
        default state<=MG_SR;
        endcase
 end
 
 always@(posedge clk)begin
    if(state!=next_state)begin
        state<=next_state;
        second<=0;end
     else begin
        second<=second+1;end
 end
    
 endmodule