data/full_repos/permissive/423547971/College Coursework/Advanced Computer Architecture Final Project/verilog CPU/shifter.v
1: b'%Error: Cannot find file containing module: Coursework/Advanced\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Advanced\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.v\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.sv\n             Coursework/Advanced\n             Coursework/Advanced.v\n             Coursework/Advanced.sv\n             obj_dir/Coursework/Advanced\n             obj_dir/Coursework/Advanced.v\n             obj_dir/Coursework/Advanced.sv\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Architecture\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project/verilog\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: CPU/shifter.v\n%Error: Exiting due to 8 error(s)\n'
module shifter( shifter_select, shifter_enable, x_input, y_input, shifter_output );
  input     [2:0]  	shifter_select;
  input            	shifter_enable;
  input     [15:0] 	x_input;
  input     [3:0]  	y_input;
  output    [15:0] 	shifter_output;


always @*
begin
  if( shifter_enable )
    begin
      case( shifter_select )
      3'b000:  shifter_output = x_input >> y_input;
      3'b001:  shifter_output = x_input << y_input;
      3'b010:  shifter_output = {15, x_input[15:1]};
      3'b011:  shifter_output = {x_input[14:0], x_input[15]};
      3'b100:  shifter_output = {x_input[0], x_input[15:1]};
      endcase
    end
end

endmodule
module shifter( shifter_select, shifter_enable, x_input, y_input, shifter_output );

  input     [2:0]  	shifter_select;
  input            	shifter_enable;
  input     [15:0] 	x_input;
  input     [3:0]  	y_input;
  output    [15:0] 	shifter_output;


always @*
begin
  if( shifter_enable )
    begin
      case( shifter_select )
      3'b000:  shifter_output = x_input >> y_input;
      3'b001:  shifter_output = x_input << y_input;
      3'b010:  shifter_output = {15, x_input[15:1]};
      3'b011:  shifter_output = {x_input[14:0], x_input[15]};
      3'b100:  shifter_output = {x_input[0], x_input[15:1]};
      endcase
    end
end

endmodule