data/full_repos/permissive/492140037/OJ/control32.v
data/verilator_xmls/b378dd62-8823-46cc-b114-0d537634bd54.xml
module control32(Opcode, Function_opcode, Jr, RegDST, ALUSrc, MemtoReg, RegWrite, MemWrite, Branch, nBranch, Jmp, Jal, I_format, Sftmd, ALUOp);
    input[5:0]   Opcode;
    input[5:0]   Function_opcode;
    output       Jr;
    output       RegDST;
    output       ALUSrc;
    output       MemtoReg;
    output       RegWrite;
    output       MemWrite;
    output       Branch;
    output       nBranch;
    output       Jmp;
    output       Jal;
    output       I_format;
    output       Sftmd;
    output[1:0]  ALUOp;

    wire R_format, Lw, Sw, Beq, Bne;

    assign R_format = Opcode == 6'b000000;
    assign I_format = Opcode[5:3] == 3'b001;

    assign Beq = Opcode == 6'b000100;
    assign Bne = Opcode == 6'b000101;

    assign Lw = Opcode == 6'b100011;
    assign Sw = Opcode == 6'b101011;

    assign Jr = Opcode == 6'b000000 && Function_opcode == 6'b001000;
    assign Jal = Opcode == 6'b000011;

    assign RegDST = R_format;
    assign ALUSrc = I_format || Lw || Sw;

    assign MemtoReg = Lw;
    assign RegWrite = (R_format || Lw || Jal || I_format) && (!Jr);
    assign MemWrite = Sw;

    assign Branch = Beq;
    assign nBranch = Bne;

    assign Jmp = Opcode == 6'b000010;

    assign Sftmd = R_format && Function_opcode[5:3] == 3'b000;

    assign ALUOp = {R_format || I_format, Branch || nBranch};

endmodule
module control32(Opcode, Function_opcode, Jr, RegDST, ALUSrc, MemtoReg, RegWrite, MemWrite, Branch, nBranch, Jmp, Jal, I_format, Sftmd, ALUOp);

    input[5:0]   Opcode;
    input[5:0]   Function_opcode;
    output       Jr;
    output       RegDST;
    output       ALUSrc;
    output       MemtoReg;
    output       RegWrite;
    output       MemWrite;
    output       Branch;
    output       nBranch;
    output       Jmp;
    output       Jal;
    output       I_format;
    output       Sftmd;
    output[1:0]  ALUOp;

    wire R_format, Lw, Sw, Beq, Bne;

    assign R_format = Opcode == 6'b000000;
    assign I_format = Opcode[5:3] == 3'b001;

    assign Beq = Opcode == 6'b000100;
    assign Bne = Opcode == 6'b000101;

    assign Lw = Opcode == 6'b100011;
    assign Sw = Opcode == 6'b101011;

    assign Jr = Opcode == 6'b000000 && Function_opcode == 6'b001000;
    assign Jal = Opcode == 6'b000011;

    assign RegDST = R_format;
    assign ALUSrc = I_format || Lw || Sw;

    assign MemtoReg = Lw;
    assign RegWrite = (R_format || Lw || Jal || I_format) && (!Jr);
    assign MemWrite = Sw;

    assign Branch = Beq;
    assign nBranch = Bne;

    assign Jmp = Opcode == 6'b000010;

    assign Sftmd = R_format && Function_opcode[5:3] == 3'b000;

    assign ALUOp = {R_format || I_format, Branch || nBranch};

endmodule