data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sr_test(t1, t2, p);

input  p;
output t1, t2;

reg t1, t2;

initial begin
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;

   #100;
   t1 <= 1'b1;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   $finish;
end

endmodule
module sr_test(t1, t2, p);


input  p;
output t1, t2;

reg t1, t2;

initial begin
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;

   #100;
   t1 <= 1'b1;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b0;

   #100;
   $finish;
end

endmodule