data/full_repos/permissive/407433468/2010-PRJ0_BASE_1/rtl/shift_reg_start_done.v
data/verilator_xmls/8ebb638e-8c6e-4f7b-82e5-b7699c00621a.xml
module shift_reg_start_done
   #(parameter N=8)
   (
    input wire clk, reset,
	 input wire Trigger,
    input wire [1:0] ctrl,
    input wire [N-1:0] d,
    output wire q, last_tick
   );
localparam NOP 		=2'b00;
localparam SHIFT_L 	=2'b01;
localparam SHIFT_R 	=2'b10;
localparam LOAD 	=2'b11;

   reg [N-1:0] r_reg, r_next;
   reg [N-1:0] cnt_reg, cnt_next;


   always @(posedge clk, posedge reset)

	begin
      if (reset== 1'b1)
      begin
        r_reg <= 0;
        cnt_reg <= 0;
      end
      else if (Trigger == 1'b1)
      begin
        r_reg <= r_next;
		cnt_reg <= cnt_next;
      end
    end

   always @*
   begin
   cnt_next	= (cnt_reg == N-1) ? 0 : cnt_reg + 1;
   r_next = r_reg;
     case(ctrl)
       NOP: r_next = r_reg;
       SHIFT_L: r_next = {r_reg[N-2:0], 1'b0};
       SHIFT_R: r_next = {1'b0, r_reg[N-1:1]};
       LOAD:begin
			r_next = d;
			cnt_next = 0;
		end
     endcase
   end

   assign q = r_reg[N-1];
   assign last_tick	= (cnt_reg == N-1);
endmodule
module shift_reg_start_done
   #(parameter N=8)
   (
    input wire clk, reset,
	 input wire Trigger,
    input wire [1:0] ctrl,
    input wire [N-1:0] d,
    output wire q, last_tick
   );

localparam NOP 		=2'b00;
localparam SHIFT_L 	=2'b01;
localparam SHIFT_R 	=2'b10;
localparam LOAD 	=2'b11;

   reg [N-1:0] r_reg, r_next;
   reg [N-1:0] cnt_reg, cnt_next;


   always @(posedge clk, posedge reset)

	begin
      if (reset== 1'b1)
      begin
        r_reg <= 0;
        cnt_reg <= 0;
      end
      else if (Trigger == 1'b1)
      begin
        r_reg <= r_next;
		cnt_reg <= cnt_next;
      end
    end

   always @*
   begin
   cnt_next	= (cnt_reg == N-1) ? 0 : cnt_reg + 1;
   r_next = r_reg;
     case(ctrl)
       NOP: r_next = r_reg;
       SHIFT_L: r_next = {r_reg[N-2:0], 1'b0};
       SHIFT_R: r_next = {1'b0, r_reg[N-1:1]};
       LOAD:begin
			r_next = d;
			cnt_next = 0;
		end
     endcase
   end

   assign q = r_reg[N-1];
   assign last_tick	= (cnt_reg == N-1);
endmodule