data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v
1: b'%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:761: Operator ADD expects 34 bits on the LHS, but LHS\'s REPLICATE generates 24 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12.m24_5\n tmp11_10 <= {tmp11,7\'b0} + {1\'b0,tmp10};\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:769: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12.m24_5\n c <= {tmp11_10_r[33:30] + P[47], P[46:0]};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:769: Operator ASSIGNDLY expects 50 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 51 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12.m24_5\n c <= {tmp11_10_r[33:30] + P[47], P[46:0]};\n   ^~\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:196: Operator NEGATE expects 7 bits on the LHS, but LHS\'s VARREF \'regime1_r9\' generates 5 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [Bs+1:0] r1 = rc1_r9 ? {2\'b0,regime1_r9} : -regime1_r9;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:197: Operator NEGATE expects 7 bits on the LHS, but LHS\'s VARREF \'regime2_r9\' generates 5 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [Bs+1:0] r2 = rc2_r9 ? {2\'b0,regime2_r9} : -regime2_r9;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:200: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s VARREF \'mant2_zero\' generates 1 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [Bs+es+1:0] div_e = {r1, e1_r9} - {r2, e2_r9} - 1 + mant2_zero + div_m_udf;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:200: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s VARREF \'div_m_udf\' generates 1 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [Bs+es+1:0] div_e = {r1, e1_r9} - {r2, e2_r9} - 1 + mant2_zero + div_m_udf;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:201: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s COND generates 13 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [es+Bs:0] div_eN = div_e[es+Bs+1] ? -div_e : div_e;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:203: Operator ADD expects 6 bits on the LHS, but LHS\'s LOGOR generates 1 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nwire [Bs:0] r_o = (~div_e[es+Bs+1] || (|div_e[es-1:0])) + div_eN[es+Bs:es];\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/407682224/simple_unit/rtl/div_N32_ES6_PIPE12.v:221: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                                             : ... In instance div_N32_ES6_PIPE12\nDSR_right_64_lat1 #(.N(3*N+3)) dsr2 (.clk(clk), .a({tmp_o,{N{1\'b0}}}), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n                                                                                  ^\n%Error: Exiting due to 10 warning(s)\n'
module LOD16_4(in, out, out_v);
input [15:0] in;
output [3:0] out;
output out_v;
wire [2:0] out_l, out_h;
wire out_vl, out_vh;
LOD8_3 pl(.in(in[7:0]), .out(out_l), .out_v(out_vl));
LOD8_3 ph(.in(in[15:8]), .out(out_h), .out_v(out_vh));
assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
assign out_v = out_vl | out_vh;
endmodule
module LOD16_4(in, out, out_v);

input [15:0] in;
output [3:0] out;
output out_v;
wire [2:0] out_l, out_h;
wire out_vl, out_vh;
LOD8_3 pl(.in(in[7:0]), .out(out_l), .out_v(out_vl));
LOD8_3 ph(.in(in[15:8]), .out(out_h), .out_v(out_vh));
assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
assign out_v = out_vl | out_vh;
endmodule