data/full_repos/permissive/516759878/RTL/Counter.v
data/verilator_xmls/5f4c454b-332b-4ee5-8f4d-b0ac61f47f7a.xml
module Counter(i_clk , i_rst_n , ld_in , i_en_cnt , out_cnt );
input i_clk ;
input i_rst_n ;
input ld_in ;
input i_en_cnt ;
output [`WIDTH_CNT-1:0] out_cnt ;

reg [`WIDTH_CNT-1:0] Q_cnt ;

always @(posedge i_clk)
      begin
    if (~i_rst_n)
       begin
         Q_cnt <= 4'b0000;
         end
     else if (ld_in ==1'b1)
         begin
            if (i_en_cnt ==1'b1)
                begin
          Q_cnt <= Q_cnt + 1'b1 ;
                end
          else
                begin
           Q_cnt <= Q_cnt - 1'b1 ;
                end 
       end
   else
        begin
             Q_cnt <= 4'b0000;
          end
     end
                 
                      
endmodule
module Counter(i_clk , i_rst_n , ld_in , i_en_cnt , out_cnt );

input i_clk ;
input i_rst_n ;
input ld_in ;
input i_en_cnt ;
output [`WIDTH_CNT-1:0] out_cnt ;

reg [`WIDTH_CNT-1:0] Q_cnt ;

always @(posedge i_clk)
      begin
    if (~i_rst_n)
       begin
         Q_cnt <= 4'b0000;
         end
     else if (ld_in ==1'b1)
         begin
            if (i_en_cnt ==1'b1)
                begin
          Q_cnt <= Q_cnt + 1'b1 ;
                end
          else
                begin
           Q_cnt <= Q_cnt - 1'b1 ;
                end 
       end
   else
        begin
             Q_cnt <= 4'b0000;
          end
     end
                 
                      
endmodule