data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G.v
data/verilator_xmls/fb30b87c-1dcf-4a91-9648-28b045bb89fd.xml
module NAND_G(A,B,C);

input A,B;
output C;
assign C = (~(A&B));


endmodule
module NAND_G(A,B,C);


input A,B;
output C;
assign C = (~(A&B));


endmodule