data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v
1: b'%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:9: Cannot find include file: attributes.v\n`include "attributes.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46989236/instruction_decoder,data/full_repos/permissive/46989236/attributes.v\n             data/full_repos/permissive/46989236/instruction_decoder,data/full_repos/permissive/46989236/attributes.v.v\n             data/full_repos/permissive/46989236/instruction_decoder,data/full_repos/permissive/46989236/attributes.v.sv\n             attributes.v\n             attributes.v.v\n             attributes.v.sv\n             obj_dir/attributes.v\n             obj_dir/attributes.v.v\n             obj_dir/attributes.v.sv\n%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:4: Define or directive not defined: \'`REG_WIDTH\'\nwire [`REG_WIDTH-1:0]b,c;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:5: Define or directive not defined: \'`OP_WIDTH\'\nwire [`OP_WIDTH-1:0]opcode;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:6: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1:0]instr;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:11: Unsupported or unknown PLI call: $monitor\n$monitor ("%d\\ttriggered=%b,busy=%b,chkbsy=%b,trigger=%b",$time,triggered,indicate_busy,check_busy,trigger);\n^~~~~~~~\n%Error: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("plot.vcd");\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#5 triggered = 1\'b1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5 check_busy = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5 check_busy = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 instr = 12\'d1656;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5 check_busy = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 triggered = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/instruction_decoder/instr_dec_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#5 instr = instr + 12\'d1;\n^\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module instr_dec_tb;
reg triggered,check_busy;
wire trigger,indicate_busy;
wire [`REG_WIDTH-1:0]b,c;
wire [`OP_WIDTH-1:0]opcode;
reg [`INSTR_WIDTH-1:0]instr;
initial
begin
`include "attributes.v"
instr = 12'd0;
$monitor ("%d\ttriggered=%b,busy=%b,chkbsy=%b,trigger=%b",$time,triggered,indicate_busy,check_busy,trigger);
$dumpfile("plot.vcd");
instr = 12'd2048;
#5 triggered = 1'b1;
#5 check_busy = 1'b1;
#5 check_busy = 1'b0;
#5 instr = 12'd1656;
#5 check_busy = 1'b1;
#5 triggered = 1'b1;
$finish;
end

always begin 
#5 instr = instr + 12'd1;
if (instr == 12'd1024)
$finish;
end

instr_dec dec(
.instr (instr),
.triggered (triggered),
.opcode (opcode),
.b (b),
.c (c),
.trigger (trigger),
.indicate_busy (indicate_busy),
.check_busy (check_busy)
);
endmodule
module instr_dec_tb;

reg triggered,check_busy;
wire trigger,indicate_busy;
wire [`REG_WIDTH-1:0]b,c;
wire [`OP_WIDTH-1:0]opcode;
reg [`INSTR_WIDTH-1:0]instr;
initial
begin
`include "attributes.v"
instr = 12'd0;
$monitor ("%d\ttriggered=%b,busy=%b,chkbsy=%b,trigger=%b",$time,triggered,indicate_busy,check_busy,trigger);
$dumpfile("plot.vcd");
instr = 12'd2048;
#5 triggered = 1'b1;
#5 check_busy = 1'b1;
#5 check_busy = 1'b0;
#5 instr = 12'd1656;
#5 check_busy = 1'b1;
#5 triggered = 1'b1;
$finish;
end

always begin 
#5 instr = instr + 12'd1;
if (instr == 12'd1024)
$finish;
end

instr_dec dec(
.instr (instr),
.triggered (triggered),
.opcode (opcode),
.b (b),
.c (c),
.trigger (trigger),
.indicate_busy (indicate_busy),
.check_busy (check_busy)
);
endmodule