data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #1.3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #77.5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #254;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:95: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:97: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/models/gpmc_model_sync.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100000;\n ^\n%Error: Exiting due to 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gpmc_model_sync
  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
   output reg EM_NWE, output reg EM_NOE );

   reg [15:0] EM_D_int;
   assign EM_D = EM_D_int;

   initial
     begin
	EM_CLK <= 0;
	EM_A <= 10'bz;
	EM_NBE <= 2'b11;
	EM_NWE <= 1;
	EM_NOE <= 1;
	EM_NCS4 <= 1;
	EM_NCS6 <= 1;
	EM_D_int <= 16'bz;
 	EM_WAIT0 <= 0;
     end
   
   task GPMC_Write;
      input ctrl;
      input [10:0] addr;
      input [15:0] data;
      begin
	 EM_CLK <= 1;
	 #10;
	 EM_CLK <= 0;
	 EM_NWE <= 0;
	 if(ctrl)
	   EM_NCS6 <= 0;
	 else
	   EM_NCS4 <= 0;
	 EM_A <= addr[10:1];
	 EM_D_int <= data;
	 #10;
	 EM_CLK <= 1;
	 #10;
	 EM_CLK <= 0;
	 EM_NWE <= 1;
	 EM_NCS4 <= 1;
	 EM_NCS6 <= 1;
	 EM_A <= 10'bz;
	 EM_D_int <= 16'bz;
	 #100;
      end
   endtask

   task GPMC_Read;
      input ctrl;
      input [10:0] addr;
      begin
	 #1.3;
	 EM_A <= addr[10:1];
	 #3;
	 if(ctrl)
	   EM_NCS6 <= 0;
	 else
	   EM_NCS4 <= 0;
	 #14;
	 EM_NOE <= 0;
	 #77.5;
	 EM_NCS4 <= 1;
	 EM_NCS6 <= 1;

	 $display("Data Read from GPMC: %X",EM_D);
	 EM_NOE <= 1;
	 #254;
	 EM_A <= 10'bz;
      end
   endtask
   
   initial
     begin
	#1000;
	GPMC_Write(1,36,16'hF00D);
	#1000;
	GPMC_Read(1,36);
	#1000;
	GPMC_Write(0,36,16'h1234);
	GPMC_Write(0,38,16'h5678);
	GPMC_Write(0,40,16'h9abc);
	GPMC_Write(0,11'h2F4,16'hF00D);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	#100000;
	$finish;
     end
   
endmodule
module gpmc_model_sync
  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
   output reg EM_NWE, output reg EM_NOE );


   reg [15:0] EM_D_int;
   assign EM_D = EM_D_int;

   initial
     begin
	EM_CLK <= 0;
	EM_A <= 10'bz;
	EM_NBE <= 2'b11;
	EM_NWE <= 1;
	EM_NOE <= 1;
	EM_NCS4 <= 1;
	EM_NCS6 <= 1;
	EM_D_int <= 16'bz;
 	EM_WAIT0 <= 0;
     end
   
   task GPMC_Write;
      input ctrl;
      input [10:0] addr;
      input [15:0] data;
      begin
	 EM_CLK <= 1;
	 #10;
	 EM_CLK <= 0;
	 EM_NWE <= 0;
	 if(ctrl)
	   EM_NCS6 <= 0;
	 else
	   EM_NCS4 <= 0;
	 EM_A <= addr[10:1];
	 EM_D_int <= data;
	 #10;
	 EM_CLK <= 1;
	 #10;
	 EM_CLK <= 0;
	 EM_NWE <= 1;
	 EM_NCS4 <= 1;
	 EM_NCS6 <= 1;
	 EM_A <= 10'bz;
	 EM_D_int <= 16'bz;
	 #100;
      end
   endtask

   task GPMC_Read;
      input ctrl;
      input [10:0] addr;
      begin
	 #1.3;
	 EM_A <= addr[10:1];
	 #3;
	 if(ctrl)
	   EM_NCS6 <= 0;
	 else
	   EM_NCS4 <= 0;
	 #14;
	 EM_NOE <= 0;
	 #77.5;
	 EM_NCS4 <= 1;
	 EM_NCS6 <= 1;

	 $display("Data Read from GPMC: %X",EM_D);
	 EM_NOE <= 1;
	 #254;
	 EM_A <= 10'bz;
      end
   endtask
   
   initial
     begin
	#1000;
	GPMC_Write(1,36,16'hF00D);
	#1000;
	GPMC_Read(1,36);
	#1000;
	GPMC_Write(0,36,16'h1234);
	GPMC_Write(0,38,16'h5678);
	GPMC_Write(0,40,16'h9abc);
	GPMC_Write(0,11'h2F4,16'hF00D);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	GPMC_Write(0,11'h7FE,16'hDEAD);
	#100000;
	$finish;
     end
   
endmodule