data/full_repos/permissive/516809949/digital/rtl/puf.v
1: b'%Warning-WIDTH: data/full_repos/permissive/516809949/digital/rtl/puf.v:47: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                         : ... In instance puf\n    wire [ 7:0] scc_cnter_plus1 = scc_cnter + 1\'b1;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/516809949/digital/rtl/puf.v:83: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'q_last\' generates 1 bits.\n                                                                         : ... In instance puf\n                stat <= stat + q_last;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/516809949/digital/rtl/puf.v:105: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'scc_cnter_plus1\' generates 8 bits.\n                                                                          : ... In instance puf\n                        scc_cnter <= scc_cnter_plus1;\n                                  ^~\n%Error: data/full_repos/permissive/516809949/digital/rtl/puf.v:140: Cannot find file containing module: \'smp_core\'\n    smp_core U_SMP_CORE (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/smp_core\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/smp_core.v\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/smp_core.sv\n             smp_core\n             smp_core.v\n             smp_core.sv\n             obj_dir/smp_core\n             obj_dir/smp_core.v\n             obj_dir/smp_core.sv\n%Error: data/full_repos/permissive/516809949/digital/rtl/puf.v:153: Cannot find file containing module: \'ncm_core\'\n    ncm_core U_NCM_CORE (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/puf.v:171: Cannot find file containing module: \'msk_core\'\n    msk_core U_MSK_CORE (\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module puf(
    input  wire         clk,
    input  wire         rst_n,
    input  wire         i_go,
    input  wire [ 55:0] i_chl_seed,
    input  wire [ 55:0] i_key1,
    input  wire [ 55:0] i_key2,
    input  wire [ 55:0] i_erchl,
    input  wire [ 55:0] i_seed56,
    input  wire [  7:0] i_seed8,
    input  wire [ 10:0] i_seed11,
    input  wire [ 15:0] i_scc_end,
    input  wire [ 15:0] i_scc_begin,
    input  wire [ 15:0] i_evx,
    input  wire [  7:0] i_chx,
    input  wire [  7:0] i_grd,
    input  wire [  3:0] i_rpt,
    input  wire         i_use_seed,
    input  wire         i_use_clkrnd,
    input  wire [  1:0] i_arc,
    input  wire         i_clk_smp,
    input  wire         i_clk_ncm,
    input  wire         i_clk_msk,
    output wire [ 55:0] o_state1,
    output wire [ 55:0] o_state2,
    output wire [ 15:0] o_stat,
    output wire [127:0] o_auth,
    output reg          o_save,
    output reg          o_done);

    reg [3:0] state;

    reg [127:0] auth;
    reg [ 15:0] stat;

    reg [1:0] valid_trans;
    reg       q_last;

    reg [15:0] evx_cnter;
    reg [15:0] scc_cnter;

    wire [ 3:0] state_plus1 = state + 1'b1;

    wire [15:0] evx_cnter_plus1 = evx_cnter + 1'b1;
    wire [ 7:0] scc_cnter_plus1 = scc_cnter + 1'b1;

    reg  go    [0:2];
    wire q     [0:2];
    wire valid [0:2];
    wire done  [0:2];

    wire [55:0] state1 [0:2];
    wire [55:0] state2;

    reg [1:0] i_go_meta; 
    wire      i_go_sync = i_go_meta[1];

    always @(posedge clk or negedge rst_n)
        if (!rst_n) i_go_meta <= 2'b0;
        else        i_go_meta <= {i_go_meta[0], i_go};

    always @(posedge clk or negedge rst_n)
        if (!rst_n) begin
            state <= 0;
            auth <= 128'b0;
            stat <= 0;
            evx_cnter <= 0;
            scc_cnter <= 0;
            valid_trans <= 0;
            q_last <= 0;
            go[0] <= 0; 
            go[1] <= 0;
            go[2] <= 0;
            o_save <= 0;
            o_done <= 0;
        end
        else begin
            valid_trans <= {valid_trans[0], valid[i_arc]};
            q_last <= q[i_arc];
            if (valid_trans == 2'b01) begin
                stat <= stat + q_last;
                auth <= {auth[126:0], q_last};
            end
            case (state)
                'd0: begin
                    if (i_go_sync) begin
                        state <= state_plus1;
                        stat <= 0;
                        auth <= 128'b0;
                        evx_cnter <= 0;
                    end
                end
                'd1: begin
                    state <= state_plus1;
                    evx_cnter <= evx_cnter_plus1;
                    scc_cnter <= 0;
                    go[i_arc] <= 1;
                end
                'd2: begin
                    if (scc_cnter == i_scc_end)
                        o_save <= 0;
                    else begin
                        scc_cnter <= scc_cnter_plus1;
                        if (scc_cnter == i_scc_begin)
                            o_save <= 1;
                    end

                    if (done[i_arc]) begin
                        state <= state_plus1;
                        go[i_arc] <= 0;
                    end
                end
                'd3: begin
                    if (!done[i_arc]) begin
                        if (evx_cnter == i_evx)
                            state <= state_plus1;
                        else
                            state <= 'd1;
                    end
                end
                'd4: begin
                    state <= state_plus1;
                    o_done <= 1;
                    o_save <= 0;
                end
                'd5: begin
                    if (!i_go_sync) begin
                        state <= 0;
                        o_done <= 0;
                    end
                end
                default: begin
                    state <= state_plus1;
                end
            endcase
        end

    smp_core U_SMP_CORE (
        .clk          ( i_clk_smp    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[0]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_chx        ( i_chx        ) ,
        .i_rpt        ( i_rpt        ) ,
        .o_state1     ( state1[0]    ) ,
        .o_q          ( q[0]         ) ,
        .o_valid      ( valid[0]     ) ,
        .o_done       ( done[0]      ) );

    ncm_core U_NCM_CORE (
        .clk          ( i_clk_ncm    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[1]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_erchl      ( i_erchl      ) ,
        .i_seed8      ( i_seed8      ) ,
        .i_chx        ( i_chx        ) ,
        .i_grd        ( i_grd        ) ,
        .i_rpt        ( i_rpt        ) ,
        .i_use_seed   ( i_use_seed   ) ,
        .i_use_clkrnd ( i_use_clkrnd ) ,
        .o_state1     ( state1[1]    ) ,
        .o_q          ( q[1]         ) ,
        .o_valid      ( valid[1]     ) ,
        .o_done       ( done[1]      ) );

    msk_core U_MSK_CORE (
        .clk          ( i_clk_msk    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[2]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_key2       ( i_key2       ) ,
        .i_erchl      ( i_erchl      ) ,
        .i_seed56     ( i_seed56     ) ,
        .i_seed8      ( i_seed8      ) ,
        .i_seed11     ( i_seed11     ) ,
        .i_chx        ( i_chx        ) ,
        .i_grd        ( i_grd        ) ,
        .i_rpt        ( i_rpt        ) ,
        .i_use_seed   ( i_use_seed   ) ,
        .i_use_clkrnd ( i_use_clkrnd ) ,
        .o_state1     ( state1[2]    ) ,
        .o_state2     ( state2       ) ,
        .o_q          ( q[2]         ) ,
        .o_valid      ( valid[2]     ) ,
        .o_done       ( done[2]      ) );

    assign o_state1 = state1[i_arc];
    assign o_state2 = state2;
    assign o_auth = auth;
    assign o_stat = stat;

endmodule
module puf(
    input  wire         clk,
    input  wire         rst_n,
    input  wire         i_go,
    input  wire [ 55:0] i_chl_seed,
    input  wire [ 55:0] i_key1,
    input  wire [ 55:0] i_key2,
    input  wire [ 55:0] i_erchl,
    input  wire [ 55:0] i_seed56,
    input  wire [  7:0] i_seed8,
    input  wire [ 10:0] i_seed11,
    input  wire [ 15:0] i_scc_end,
    input  wire [ 15:0] i_scc_begin,
    input  wire [ 15:0] i_evx,
    input  wire [  7:0] i_chx,
    input  wire [  7:0] i_grd,
    input  wire [  3:0] i_rpt,
    input  wire         i_use_seed,
    input  wire         i_use_clkrnd,
    input  wire [  1:0] i_arc,
    input  wire         i_clk_smp,
    input  wire         i_clk_ncm,
    input  wire         i_clk_msk,
    output wire [ 55:0] o_state1,
    output wire [ 55:0] o_state2,
    output wire [ 15:0] o_stat,
    output wire [127:0] o_auth,
    output reg          o_save,
    output reg          o_done);


    reg [3:0] state;

    reg [127:0] auth;
    reg [ 15:0] stat;

    reg [1:0] valid_trans;
    reg       q_last;

    reg [15:0] evx_cnter;
    reg [15:0] scc_cnter;

    wire [ 3:0] state_plus1 = state + 1'b1;

    wire [15:0] evx_cnter_plus1 = evx_cnter + 1'b1;
    wire [ 7:0] scc_cnter_plus1 = scc_cnter + 1'b1;

    reg  go    [0:2];
    wire q     [0:2];
    wire valid [0:2];
    wire done  [0:2];

    wire [55:0] state1 [0:2];
    wire [55:0] state2;

    reg [1:0] i_go_meta; 
    wire      i_go_sync = i_go_meta[1];

    always @(posedge clk or negedge rst_n)
        if (!rst_n) i_go_meta <= 2'b0;
        else        i_go_meta <= {i_go_meta[0], i_go};

    always @(posedge clk or negedge rst_n)
        if (!rst_n) begin
            state <= 0;
            auth <= 128'b0;
            stat <= 0;
            evx_cnter <= 0;
            scc_cnter <= 0;
            valid_trans <= 0;
            q_last <= 0;
            go[0] <= 0; 
            go[1] <= 0;
            go[2] <= 0;
            o_save <= 0;
            o_done <= 0;
        end
        else begin
            valid_trans <= {valid_trans[0], valid[i_arc]};
            q_last <= q[i_arc];
            if (valid_trans == 2'b01) begin
                stat <= stat + q_last;
                auth <= {auth[126:0], q_last};
            end
            case (state)
                'd0: begin
                    if (i_go_sync) begin
                        state <= state_plus1;
                        stat <= 0;
                        auth <= 128'b0;
                        evx_cnter <= 0;
                    end
                end
                'd1: begin
                    state <= state_plus1;
                    evx_cnter <= evx_cnter_plus1;
                    scc_cnter <= 0;
                    go[i_arc] <= 1;
                end
                'd2: begin
                    if (scc_cnter == i_scc_end)
                        o_save <= 0;
                    else begin
                        scc_cnter <= scc_cnter_plus1;
                        if (scc_cnter == i_scc_begin)
                            o_save <= 1;
                    end

                    if (done[i_arc]) begin
                        state <= state_plus1;
                        go[i_arc] <= 0;
                    end
                end
                'd3: begin
                    if (!done[i_arc]) begin
                        if (evx_cnter == i_evx)
                            state <= state_plus1;
                        else
                            state <= 'd1;
                    end
                end
                'd4: begin
                    state <= state_plus1;
                    o_done <= 1;
                    o_save <= 0;
                end
                'd5: begin
                    if (!i_go_sync) begin
                        state <= 0;
                        o_done <= 0;
                    end
                end
                default: begin
                    state <= state_plus1;
                end
            endcase
        end

    smp_core U_SMP_CORE (
        .clk          ( i_clk_smp    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[0]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_chx        ( i_chx        ) ,
        .i_rpt        ( i_rpt        ) ,
        .o_state1     ( state1[0]    ) ,
        .o_q          ( q[0]         ) ,
        .o_valid      ( valid[0]     ) ,
        .o_done       ( done[0]      ) );

    ncm_core U_NCM_CORE (
        .clk          ( i_clk_ncm    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[1]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_erchl      ( i_erchl      ) ,
        .i_seed8      ( i_seed8      ) ,
        .i_chx        ( i_chx        ) ,
        .i_grd        ( i_grd        ) ,
        .i_rpt        ( i_rpt        ) ,
        .i_use_seed   ( i_use_seed   ) ,
        .i_use_clkrnd ( i_use_clkrnd ) ,
        .o_state1     ( state1[1]    ) ,
        .o_q          ( q[1]         ) ,
        .o_valid      ( valid[1]     ) ,
        .o_done       ( done[1]      ) );

    msk_core U_MSK_CORE (
        .clk          ( i_clk_msk    ) ,
        .rst_n        ( rst_n        ) ,
        .i_go         ( go[2]        ) ,
        .i_chl_seed   ( i_chl_seed   ) ,
        .i_key1       ( i_key1       ) ,
        .i_key2       ( i_key2       ) ,
        .i_erchl      ( i_erchl      ) ,
        .i_seed56     ( i_seed56     ) ,
        .i_seed8      ( i_seed8      ) ,
        .i_seed11     ( i_seed11     ) ,
        .i_chx        ( i_chx        ) ,
        .i_grd        ( i_grd        ) ,
        .i_rpt        ( i_rpt        ) ,
        .i_use_seed   ( i_use_seed   ) ,
        .i_use_clkrnd ( i_use_clkrnd ) ,
        .o_state1     ( state1[2]    ) ,
        .o_state2     ( state2       ) ,
        .o_q          ( q[2]         ) ,
        .o_valid      ( valid[2]     ) ,
        .o_done       ( done[2]      ) );

    assign o_state1 = state1[i_arc];
    assign o_state2 = state2;
    assign o_auth = auth;
    assign o_stat = stat;

endmodule