data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall.v
1: b"%Error: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall.v:29: Cannot find file containing module: 'ControllerI2C'\n ControllerI2C ControlUnit(ClockOut,SCL,Go,Reset,ControllerBaudEnable,ControllerReadOrWrite,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42149584/Lab6-Part1,data/full_repos/permissive/42149584/ControllerI2C\n             data/full_repos/permissive/42149584/Lab6-Part1,data/full_repos/permissive/42149584/ControllerI2C.v\n             data/full_repos/permissive/42149584/Lab6-Part1,data/full_repos/permissive/42149584/ControllerI2C.sv\n             ControllerI2C\n             ControllerI2C.v\n             ControllerI2C.sv\n             obj_dir/ControllerI2C\n             obj_dir/ControllerI2C.v\n             obj_dir/ControllerI2C.sv\n%Error: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall.v:30: Cannot find file containing module: 'MasterDataUnitI2C'\n MasterDataUnitI2C DataUnit(BaudRate,ClockFrequency,FirstByte,ControllerBaudEnable,ClockOut,ControllerReadOrWrite,Reset,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad,DataUnitReceivedData,SCL,SDA);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall.v:31: Cannot find file containing module: 'Clock65MHz'\n Clock65MHz SystemClock(Clock,ClockOut,ClockLocked);\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module lab6phase1I2C2015fall(Clock,Go,Reset,ClockLocked,SCL,SDA);
	input Clock, Go, Reset;
	output ClockLocked, SCL, SDA;
	
	wire ClockOut;
	wire ControllerBaudEnable;
	wire ControllerReadOrWrite;
	wire ControllerSelect;
	wire ControllerShiftOrHold;
	wire ControllerStartStopAck;
	wire ControllerWriteLoad;

	parameter BaudRate = 20'd40000;
	parameter ClockFrequency = 30'd65000000;
	parameter FirstByte = 8'b10101101;
	

	wire [7:0] DataUnitReceivedData;

	ControllerI2C ControlUnit(ClockOut,SCL,Go,Reset,ControllerBaudEnable,ControllerReadOrWrite,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad);
	MasterDataUnitI2C DataUnit(BaudRate,ClockFrequency,FirstByte,ControllerBaudEnable,ClockOut,ControllerReadOrWrite,Reset,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad,DataUnitReceivedData,SCL,SDA);
	Clock65MHz SystemClock(Clock,ClockOut,ClockLocked);
endmodule
module lab6phase1I2C2015fall(Clock,Go,Reset,ClockLocked,SCL,SDA);

	input Clock, Go, Reset;
	output ClockLocked, SCL, SDA;
	
	wire ClockOut;
	wire ControllerBaudEnable;
	wire ControllerReadOrWrite;
	wire ControllerSelect;
	wire ControllerShiftOrHold;
	wire ControllerStartStopAck;
	wire ControllerWriteLoad;

	parameter BaudRate = 20'd40000;
	parameter ClockFrequency = 30'd65000000;
	parameter FirstByte = 8'b10101101;
	

	wire [7:0] DataUnitReceivedData;

	ControllerI2C ControlUnit(ClockOut,SCL,Go,Reset,ControllerBaudEnable,ControllerReadOrWrite,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad);
	MasterDataUnitI2C DataUnit(BaudRate,ClockFrequency,FirstByte,ControllerBaudEnable,ClockOut,ControllerReadOrWrite,Reset,ControllerSelect,ControllerShiftOrHold,ControllerStartStopAck,ControllerWriteLoad,DataUnitReceivedData,SCL,SDA);
	Clock65MHz SystemClock(Clock,ClockOut,ClockLocked);
endmodule