data/full_repos/permissive/506562943/DigitalCircuits/3-8-1-data-selector/rtl/case_data_selector.v
data/verilator_xmls/460b308d-1614-4b0b-90b1-3b7f2df0a7e8.xml
module case_data_selector (
	input [7:0] dat,
	input [2:0] addr,
	
	output reg out
);


always @(*) begin
	case(addr)
		3'd0: out = dat[0];
		3'd1: out = dat[1];
		3'd2: out = dat[2];
		3'd3: out = dat[3];
		3'd4: out = dat[4];
		3'd5: out = dat[5];
		3'd6: out = dat[6];
		3'd7: out = dat[7];
		default: out = dat[0];
	endcase
end

endmodule
module case_data_selector (
	input [7:0] dat,
	input [2:0] addr,
	
	output reg out
);



always @(*) begin
	case(addr)
		3'd0: out = dat[0];
		3'd1: out = dat[1];
		3'd2: out = dat[2];
		3'd3: out = dat[3];
		3'd4: out = dat[4];
		3'd5: out = dat[5];
		3'd6: out = dat[6];
		3'd7: out = dat[7];
		default: out = dat[0];
	endcase
end

endmodule