data/full_repos/permissive/485129576/buffer8.v
data/verilator_xmls/cfce7647-0c10-4804-a109-bef3388a471e.xml
module BUF8 (
    input [7:0] in,
    input enable,
    output reg [7:0] out
);
    always@(*) begin
        case(enable)
            1'b0 : out = 8'bzzzzzzzz;
            1'b1 : out = in;
        endcase
    end
    
endmodule
module BUF8 (
    input [7:0] in,
    input enable,
    output reg [7:0] out
);

    always@(*) begin
        case(enable)
            1'b0 : out = 8'bzzzzzzzz;
            1'b1 : out = in;
        endcase
    end
    
endmodule