data/full_repos/permissive/501138203/verilog/rtl/puf.v
1: b"%Error: data/full_repos/permissive/501138203/verilog/rtl/puf.v:43: Cannot find file containing module: 'BR32'\n  BR32 BR32_inst (\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/BR32\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/BR32.v\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/BR32.sv\n             BR32\n             BR32.v\n             BR32.sv\n             obj_dir/BR32\n             obj_dir/BR32.v\n             obj_dir/BR32.sv\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf.v:49: Cannot find file containing module: 'BR64'\n  BR64 BR64_inst (\n  ^~~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf.v:55: Cannot find file containing module: 'BR128'\n  BR128 BR128_inst (\n  ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module puf 
(
    input wire reset,
    input wire [1:0] length,
    input wire [127:0] c,
    output reg out
);




  reg [3:0] reset_in;
  wire out_32;
  wire out_64;
  wire out_128;


  always @ (*) begin
    case(length)
      2'b00: begin 
               reset_in <= {3'b111, reset};
               out <= out_32;
             end
      2'b01: begin
               reset_in <= {2'b11, reset, 1'b1};
               out <= out_64; 
             end  
      2'b10: begin
               reset_in <= {1'b1, reset, 2'b11};
               out <= out_128;
             end  
      2'b11: begin
               reset_in <= {1'b1, reset, 2'b11};
               out <= out_128;
             end
    endcase
  end


  BR32 BR32_inst (
    .RESET(reset_in[0]),
    .C(c[31:0]),
    .OUT(out_32)
  );

  BR64 BR64_inst (
    .RESET(reset_in[1]),
    .C(c[63:0]),
    .OUT(out_64)
  );

  BR128 BR128_inst (
    .RESET(reset_in[2]),
    .C(c[127:0]),
    .OUT(out_128)
  );

endmodule
module puf 
(
    input wire reset,
    input wire [1:0] length,
    input wire [127:0] c,
    output reg out
);





  reg [3:0] reset_in;
  wire out_32;
  wire out_64;
  wire out_128;


  always @ (*) begin
    case(length)
      2'b00: begin 
               reset_in <= {3'b111, reset};
               out <= out_32;
             end
      2'b01: begin
               reset_in <= {2'b11, reset, 1'b1};
               out <= out_64; 
             end  
      2'b10: begin
               reset_in <= {1'b1, reset, 2'b11};
               out <= out_128;
             end  
      2'b11: begin
               reset_in <= {1'b1, reset, 2'b11};
               out <= out_128;
             end
    endcase
  end


  BR32 BR32_inst (
    .RESET(reset_in[0]),
    .C(c[31:0]),
    .OUT(out_32)
  );

  BR64 BR64_inst (
    .RESET(reset_in[1]),
    .C(c[63:0]),
    .OUT(out_64)
  );

  BR128 BR128_inst (
    .RESET(reset_in[2]),
    .C(c[127:0]),
    .OUT(out_128)
  );

endmodule