data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo_ctrl.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo_ctrl.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo_ctrl.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo_ctrl.v:63: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo_ctrl.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 4 error(s)\n'
module c_fifo_ctrl
  (clk, reset, push_active, pop_active, push, pop, push_addr, pop_addr, 
   almost_empty, empty, full, errors);
   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 8;
   

   parameter extra_addr_width = 0;
   

   localparam addr_width = clogb(depth) + extra_addr_width;
   

   parameter offset = 0;
   

   localparam [0:addr_width-1] min_value = offset;
   

   localparam [0:addr_width-1] max_value = offset + depth - 1;
   

   parameter fast_almost_empty = 0;
   

   parameter enable_bypass = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input push_active;
   input pop_active;
   

   input push;
   

   input pop;
   

   output [0:addr_width-1] push_addr;
   wire [0:addr_width-1]   push_addr;
   

   output [0:addr_width-1] pop_addr;
   wire [0:addr_width-1]   pop_addr;
   

   output 		   almost_empty;
   wire 		   almost_empty;
   

   output 		   empty;
   wire 		   empty;
   

   output 		   full;
   wire 		   full;
   

   output [0:1] 	   errors;
   wire [0:1] 		   errors;
   
   wire 		   active;
   assign active = push_active | pop_active;
   
   generate
      
      if(depth == 1)
	begin
	   
	   assign push_addr = min_value;
	   assign pop_addr = min_value;
	   
	   wire empty_s, empty_q;
	   assign empty_s = (empty_q & ~push) | pop;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign almost_empty = ~empty_q;
	   assign empty = empty_q;
	   assign full = ~empty_q;
	   
	end
      else if(depth > 1)
	begin
	   
	   wire [0:addr_width-1] push_addr_q;
	   
	   wire [0:addr_width-1] push_addr_next;
	   c_incr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   push_addr_incr
	     (.data_in(push_addr_q),
	      .data_out(push_addr_next));
	   
	   wire [0:addr_width-1] push_addr_prev;
	   c_decr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   push_addr_decr
	     (.data_in(push_addr_q),
	      .data_out(push_addr_prev));
	   
	   wire [0:addr_width-1] push_addr_s;
	   assign push_addr_s = push ? push_addr_next : push_addr_q;
	   c_dff
	     #(.width(addr_width),
	       .reset_value(min_value),
	       .reset_type(reset_type))
	   push_addrq
	     (.clk(clk),
	      .reset(reset),
	      .active(push_active),
	      .d(push_addr_s),
	      .q(push_addr_q));
	   
	   assign push_addr = push_addr_q;
	   
	   wire [0:addr_width-1] pop_addr_q;
	   
	   wire [0:addr_width-1] pop_addr_next;
	   c_incr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   pop_addr_incr
	     (.data_in(pop_addr_q),
	      .data_out(pop_addr_next));
	   
	   wire [0:addr_width-1] pop_addr_prev;
	   c_decr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   pop_addr_decr
	     (.data_in(pop_addr_q),
	      .data_out(pop_addr_prev));
	   
	   wire [0:addr_width-1] pop_addr_s;
	   assign pop_addr_s = pop ? pop_addr_next : pop_addr_q;
	   c_dff
	     #(.width(addr_width),
	       .reset_value(min_value),
	       .reset_type(reset_type))
	   pop_addrq
	     (.clk(clk),
	      .reset(reset),
	      .active(pop_active),
	      .d(pop_addr_s),
	      .q(pop_addr_q));
	   
	   assign pop_addr = pop_addr_q;

	   if(fast_almost_empty)
	     begin
		
		wire equal;
		assign equal = (push_addr_q == pop_addr_q);
		
		wire next_almost_empty;
		assign next_almost_empty = (push_addr_prev == pop_addr_next);
		
		wire almost_empty_s, almost_empty_q;
		if(enable_bypass)
		  assign almost_empty_s = (almost_empty & ~(push ^ pop)) | 
					  (next_almost_empty & (~push & pop)) |
					  (equal & (push & ~pop));
		else
		  assign almost_empty_s = (almost_empty & ~(push ^ pop)) | 
					  (next_almost_empty & (~push & pop)) |
					  (equal & push);
		c_dff
		  #(.width(1),
		    .reset_type(reset_type))
		almost_emptyq
		  (.clk(clk),
		   .reset(reset),
		   .active(active),
		   .d(almost_empty_s),
		   .q(almost_empty_q));
		
		assign almost_empty = almost_empty_q;
		
	     end
	   else
	     assign almost_empty = (push_addr_prev == pop_addr_q);
	   
	   wire 		 next_empty;
	   assign next_empty = (push_addr_q == pop_addr_next);
	   
	   wire 		 empty_s, empty_q;
	   if(enable_bypass)
	     assign empty_s = (empty & ~(push & ~pop)) | 
			      (next_empty & (~push & pop));
	   else
	     assign empty_s = (empty | (next_empty & pop)) & ~push;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign empty = empty_q;
	   
	   wire 		 next_full;
	   assign next_full = (push_addr_next == pop_addr_q);
	   
	   wire 		 full_s, full_q;
	   assign full_s = (full | (next_full & push)) & ~pop;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   fullq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(full_s),
	      .q(full_q));
	   
	   assign full = full_q;
	   
	end
      

      
      else
	begin
	   initial
	   begin
	      $display({"ERROR: FIFO controller module %m requires a depth ", 
			"of at least one entry."});
	      $stop;
	   end
	end
      

      
   endgenerate
   
   wire 			 error_underflow;
   
   generate
      
      if(enable_bypass)
	assign error_underflow = empty & ~push & pop;
      else
	assign error_underflow = empty & pop;
      
   endgenerate
   
   wire 			 error_overflow;
   assign error_overflow = full & push;
   

   
   always @(posedge clk)
     begin
	
	if(error_underflow)
	  $display("ERROR: FIFO underflow in module %m.");
	
	if(error_overflow)
	  $display("ERROR: FIFO overflow in module %m.");
	
     end
   

   
   assign errors[0] = error_underflow;
   assign errors[1] = error_overflow;
   
endmodule
module c_fifo_ctrl
  (clk, reset, push_active, pop_active, push, pop, push_addr, pop_addr, 
   almost_empty, empty, full, errors);

   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 8;
   

   parameter extra_addr_width = 0;
   

   localparam addr_width = clogb(depth) + extra_addr_width;
   

   parameter offset = 0;
   

   localparam [0:addr_width-1] min_value = offset;
   

   localparam [0:addr_width-1] max_value = offset + depth - 1;
   

   parameter fast_almost_empty = 0;
   

   parameter enable_bypass = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input push_active;
   input pop_active;
   

   input push;
   

   input pop;
   

   output [0:addr_width-1] push_addr;
   wire [0:addr_width-1]   push_addr;
   

   output [0:addr_width-1] pop_addr;
   wire [0:addr_width-1]   pop_addr;
   

   output 		   almost_empty;
   wire 		   almost_empty;
   

   output 		   empty;
   wire 		   empty;
   

   output 		   full;
   wire 		   full;
   

   output [0:1] 	   errors;
   wire [0:1] 		   errors;
   
   wire 		   active;
   assign active = push_active | pop_active;
   
   generate
      
      if(depth == 1)
	begin
	   
	   assign push_addr = min_value;
	   assign pop_addr = min_value;
	   
	   wire empty_s, empty_q;
	   assign empty_s = (empty_q & ~push) | pop;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign almost_empty = ~empty_q;
	   assign empty = empty_q;
	   assign full = ~empty_q;
	   
	end
      else if(depth > 1)
	begin
	   
	   wire [0:addr_width-1] push_addr_q;
	   
	   wire [0:addr_width-1] push_addr_next;
	   c_incr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   push_addr_incr
	     (.data_in(push_addr_q),
	      .data_out(push_addr_next));
	   
	   wire [0:addr_width-1] push_addr_prev;
	   c_decr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   push_addr_decr
	     (.data_in(push_addr_q),
	      .data_out(push_addr_prev));
	   
	   wire [0:addr_width-1] push_addr_s;
	   assign push_addr_s = push ? push_addr_next : push_addr_q;
	   c_dff
	     #(.width(addr_width),
	       .reset_value(min_value),
	       .reset_type(reset_type))
	   push_addrq
	     (.clk(clk),
	      .reset(reset),
	      .active(push_active),
	      .d(push_addr_s),
	      .q(push_addr_q));
	   
	   assign push_addr = push_addr_q;
	   
	   wire [0:addr_width-1] pop_addr_q;
	   
	   wire [0:addr_width-1] pop_addr_next;
	   c_incr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   pop_addr_incr
	     (.data_in(pop_addr_q),
	      .data_out(pop_addr_next));
	   
	   wire [0:addr_width-1] pop_addr_prev;
	   c_decr
	     #(.width(addr_width),
	       .min_value(min_value),
	       .max_value(max_value))
	   pop_addr_decr
	     (.data_in(pop_addr_q),
	      .data_out(pop_addr_prev));
	   
	   wire [0:addr_width-1] pop_addr_s;
	   assign pop_addr_s = pop ? pop_addr_next : pop_addr_q;
	   c_dff
	     #(.width(addr_width),
	       .reset_value(min_value),
	       .reset_type(reset_type))
	   pop_addrq
	     (.clk(clk),
	      .reset(reset),
	      .active(pop_active),
	      .d(pop_addr_s),
	      .q(pop_addr_q));
	   
	   assign pop_addr = pop_addr_q;

	   if(fast_almost_empty)
	     begin
		
		wire equal;
		assign equal = (push_addr_q == pop_addr_q);
		
		wire next_almost_empty;
		assign next_almost_empty = (push_addr_prev == pop_addr_next);
		
		wire almost_empty_s, almost_empty_q;
		if(enable_bypass)
		  assign almost_empty_s = (almost_empty & ~(push ^ pop)) | 
					  (next_almost_empty & (~push & pop)) |
					  (equal & (push & ~pop));
		else
		  assign almost_empty_s = (almost_empty & ~(push ^ pop)) | 
					  (next_almost_empty & (~push & pop)) |
					  (equal & push);
		c_dff
		  #(.width(1),
		    .reset_type(reset_type))
		almost_emptyq
		  (.clk(clk),
		   .reset(reset),
		   .active(active),
		   .d(almost_empty_s),
		   .q(almost_empty_q));
		
		assign almost_empty = almost_empty_q;
		
	     end
	   else
	     assign almost_empty = (push_addr_prev == pop_addr_q);
	   
	   wire 		 next_empty;
	   assign next_empty = (push_addr_q == pop_addr_next);
	   
	   wire 		 empty_s, empty_q;
	   if(enable_bypass)
	     assign empty_s = (empty & ~(push & ~pop)) | 
			      (next_empty & (~push & pop));
	   else
	     assign empty_s = (empty | (next_empty & pop)) & ~push;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign empty = empty_q;
	   
	   wire 		 next_full;
	   assign next_full = (push_addr_next == pop_addr_q);
	   
	   wire 		 full_s, full_q;
	   assign full_s = (full | (next_full & push)) & ~pop;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   fullq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(full_s),
	      .q(full_q));
	   
	   assign full = full_q;
	   
	end
      

      
      else
	begin
	   initial
	   begin
	      $display({"ERROR: FIFO controller module %m requires a depth ", 
			"of at least one entry."});
	      $stop;
	   end
	end
      

      
   endgenerate
   
   wire 			 error_underflow;
   
   generate
      
      if(enable_bypass)
	assign error_underflow = empty & ~push & pop;
      else
	assign error_underflow = empty & pop;
      
   endgenerate
   
   wire 			 error_overflow;
   assign error_overflow = full & push;
   

   
   always @(posedge clk)
     begin
	
	if(error_underflow)
	  $display("ERROR: FIFO underflow in module %m.");
	
	if(error_overflow)
	  $display("ERROR: FIFO overflow in module %m.");
	
     end
   

   
   assign errors[0] = error_underflow;
   assign errors[1] = error_overflow;
   
endmodule