data/full_repos/permissive/528252229/ex_mem.v
1: b'%Error: data/full_repos/permissive/528252229/ex_mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/ex_mem.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]        ex_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus]        ex_wd,\n                       ^\n%Error: data/full_repos/permissive/528252229/ex_mem.v:10: Define or directive not defined: \'`WriteBus\'\n input wire[`WriteBus]           ex_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    ex_wdata,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]   ex_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    ex_mem_addr,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    ex_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:16: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]  ex_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:17: Define or directive not defined: \'`StopBus\'\n input wire[`StopBus]            stall,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:20: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]       mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:21: Define or directive not defined: \'`WriteBus\'\n output reg[`WriteBus]           mem_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:22: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:24: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]   mem_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:25: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    mem_mem_addr,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    mem_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:27: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus]  mem_pc\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:34: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:35: Define or directive not defined: \'`ZeroRegAddr\'\n            mem_wd       <= `ZeroRegAddr;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:36: Define or directive not defined: \'`WriteDisable\'\n            mem_wreg     <= `WriteDisable;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:37: Define or directive not defined: \'`ZeroWord\'\n            mem_wdata    <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:38: Define or directive not defined: \'`ALU_OP_NOP\'\n   mem_aluop  <= `ALU_OP_NOP;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:39: Define or directive not defined: \'`ZeroWord\'\n   mem_mem_addr <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:40: Define or directive not defined: \'`ZeroWord\'\n   mem_reg2  <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:41: Define or directive not defined: \'`InitialPc\'\n            mem_pc       <= `InitialPc;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:43: Define or directive not defined: \'`Stop\'\n        else if(stall[3] == `Stop && stall[4] == `NoStop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:43: Define or directive not defined: \'`NoStop\'\n        else if(stall[3] == `Stop && stall[4] == `NoStop) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:44: Define or directive not defined: \'`ZeroRegAddr\'\n            mem_wd       <= `ZeroRegAddr;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:45: Define or directive not defined: \'`WriteDisable\'\n            mem_wreg     <= `WriteDisable;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:46: Define or directive not defined: \'`ZeroWord\'\n            mem_wdata    <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:47: Define or directive not defined: \'`ALU_OP_NOP\'\n   mem_aluop  <= `ALU_OP_NOP;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:48: Define or directive not defined: \'`ZeroWord\'\n   mem_mem_addr <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:49: Define or directive not defined: \'`ZeroWord\'\n   mem_reg2  <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:50: Define or directive not defined: \'`InitialPc\'\n            mem_pc       <= `InitialPc;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex_mem.v:52: Define or directive not defined: \'`NoStop\'\n        else if(stall[3] == `NoStop) begin\n                            ^~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module ex_mem(

	input wire						clk,
	input wire						rst,
	
	
	input wire[`RegAddrBus]       	ex_wd,
	input wire[`WriteBus]           ex_wreg,
	input wire[`RegBus]				ex_wdata, 	

	input wire[`AluOpBus]			ex_aluop,
	input wire[`RegBus]				ex_mem_addr,
	input wire[`RegBus]				ex_reg2,
	input wire[`InstAddrBus]		ex_pc,
	input wire[`StopBus]            stall,


	output reg[`RegAddrBus]      	mem_wd,
	output reg[`WriteBus]           mem_wreg,
	output reg[`RegBus]				mem_wdata,

	output reg[`AluOpBus]			mem_aluop,
	output reg[`RegBus]				mem_mem_addr,
	output reg[`RegBus]				mem_reg2,
	output reg[`InstAddrBus]		mem_pc
	
);



    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            mem_wd       <= `ZeroRegAddr;
            mem_wreg     <= `WriteDisable;
            mem_wdata    <= `ZeroWord;
			mem_aluop	 <= `ALU_OP_NOP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2	 <= `ZeroWord;
            mem_pc       <= `InitialPc;
        end 
        else if(stall[3] == `Stop && stall[4] == `NoStop) begin
            mem_wd       <= `ZeroRegAddr;
            mem_wreg     <= `WriteDisable;
            mem_wdata    <= `ZeroWord;
			mem_aluop	 <= `ALU_OP_NOP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2	 <= `ZeroWord;
            mem_pc       <= `InitialPc;
        end 
        else if(stall[3] == `NoStop) begin
            mem_wd       <= ex_wd;
            mem_wreg     <= ex_wreg;
            mem_wdata    <= ex_wdata;
			mem_aluop	 <= ex_aluop;
			mem_mem_addr <= ex_mem_addr;
			mem_reg2	 <= ex_reg2;
            mem_pc       <= ex_pc;
        end
    end

	

endmodule
module ex_mem(

	input wire						clk,
	input wire						rst,
	
	
	input wire[`RegAddrBus]       	ex_wd,
	input wire[`WriteBus]           ex_wreg,
	input wire[`RegBus]				ex_wdata, 	

	input wire[`AluOpBus]			ex_aluop,
	input wire[`RegBus]				ex_mem_addr,
	input wire[`RegBus]				ex_reg2,
	input wire[`InstAddrBus]		ex_pc,
	input wire[`StopBus]            stall,


	output reg[`RegAddrBus]      	mem_wd,
	output reg[`WriteBus]           mem_wreg,
	output reg[`RegBus]				mem_wdata,

	output reg[`AluOpBus]			mem_aluop,
	output reg[`RegBus]				mem_mem_addr,
	output reg[`RegBus]				mem_reg2,
	output reg[`InstAddrBus]		mem_pc
	
);




    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            mem_wd       <= `ZeroRegAddr;
            mem_wreg     <= `WriteDisable;
            mem_wdata    <= `ZeroWord;
			mem_aluop	 <= `ALU_OP_NOP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2	 <= `ZeroWord;
            mem_pc       <= `InitialPc;
        end 
        else if(stall[3] == `Stop && stall[4] == `NoStop) begin
            mem_wd       <= `ZeroRegAddr;
            mem_wreg     <= `WriteDisable;
            mem_wdata    <= `ZeroWord;
			mem_aluop	 <= `ALU_OP_NOP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2	 <= `ZeroWord;
            mem_pc       <= `InitialPc;
        end 
        else if(stall[3] == `NoStop) begin
            mem_wd       <= ex_wd;
            mem_wreg     <= ex_wreg;
            mem_wdata    <= ex_wdata;
			mem_aluop	 <= ex_aluop;
			mem_mem_addr <= ex_mem_addr;
			mem_reg2	 <= ex_reg2;
            mem_pc       <= ex_pc;
        end
    end

	

endmodule