data/full_repos/permissive/509809169/Circuits/Sequential Logic/Counters/Slow decade counter.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169.sv\n             Logic/Counters,data/full_repos/permissive/509809169\n             Logic/Counters,data/full_repos/permissive/509809169.v\n             Logic/Counters,data/full_repos/permissive/509809169.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Slow\n%Error: Cannot find file containing module: decade\n%Error: Cannot find file containing module: counter.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always @(posedge clk) begin
        if(reset)	q<=0;
        else begin
            if(q<9) begin
            	if(slowena==1)
                    q<=q+1;
                else q<=q;
            end
            else 
                if(slowena==1) q<=0;
        end
    end
                
endmodule
module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    always @(posedge clk) begin
        if(reset)	q<=0;
        else begin
            if(q<9) begin
            	if(slowena==1)
                    q<=q+1;
                else q<=q;
            end
            else 
                if(slowena==1) q<=0;
        end
    end
                
endmodule