data/full_repos/permissive/515477729/source/pipo.v
data/verilator_xmls/986f0674-bad5-47c4-8e35-32540ceb4df2.xml
module pipo (output reg [15:0] data_out, input [15:0] data_in, input clk, load);

    always @(posedge clk) begin
        if (load) data_out <= data_in;
    end
endmodule
module pipo (output reg [15:0] data_out, input [15:0] data_in, input clk, load);


    always @(posedge clk) begin
        if (load) data_out <= data_in;
    end
endmodule