data/full_repos/permissive/431687600/Proc_SRC/control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/431687600/Proc_SRC/control.v:87: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                          : ... In instance control\n     o_branch      <= i_instruction[2:0];            \n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module control(
	input clk,reset,i_checkbranch,
	input [12:0] i_instruction, 
	output reg [3:0] o_opcode,                      
	output reg [2:0] o_destination,o_addr1,o_addr2,     
	output reg [8:0] o_branch, 
	output reg [12:0] o_PC,                     
	output reg o_memWrite,o_memRead,o_PCop);         

	localparam RESET_STATE = 0;
	localparam FETCH = 1;
	localparam DECODE = 2;
	localparam MATH_EXECUTE = 3;
	localparam BRANCH_EXECUTE = 4;

	reg [2:0] state;

	always@(posedge clk) begin
		if(reset == 1'b1) state <= 0;
		case(state)
			RESET_STATE: begin 
				o_PCop <= 0;
				o_PC <= 0;
				o_memWrite    <= 0;
				o_memRead     <= 0;
				state <= FETCH;
				end                                     
			FETCH: begin                    
				o_opcode      <= i_instruction[12:9];
				o_addr1       <= 0;
				o_addr2       <= 0;
				o_destination <= 0;
				o_branch      <= 0;
				o_memWrite    <= 0;
				o_memRead     <= 0;
				o_PCop      <= 0;
				state         <= DECODE;
			end
			DECODE: begin                    
				if(i_instruction[12:9] == 4'b1000) begin
					o_opcode      <= i_instruction[12:9];          
					o_addr1       <= 0;           
					o_addr2       <= 0;            
					o_branch      <= i_instruction[8:0];            
					o_destination <= 0;                    
					o_memRead     <= 1;
					o_PC 	      <= 0;
					state         <= BRANCH_EXECUTE;           
				end
				else if(i_instruction[12:11] == 2'b11) begin
					o_opcode      <= i_instruction[12:9];          
					o_addr1       <= i_instruction[8:6];           
					o_addr2       <= i_instruction[5:3];            
					o_branch      <= i_instruction[2:0];            
					o_destination <= 0;                    
					o_memRead     <= 1;
					state         <= BRANCH_EXECUTE;           
				end
				else begin
					o_opcode      <= i_instruction[12:9];          
					o_destination <= i_instruction[8:6];           				
					o_addr1       <= i_instruction[5:3];            
					o_addr2       <= i_instruction[2:0];            
					o_memRead     <= 1;
					o_branch      <= 0; 
					state 		<= MATH_EXECUTE;                    
				end
			end



			MATH_EXECUTE: begin 
				o_opcode      <= i_instruction[12:9];               
				o_memWrite    <= 1;                      
				o_memRead     <= 0;
				o_PCop      <= 0; 
				o_destination <= i_instruction[8:6];
				o_addr1       <= i_instruction[5:3];            
				o_addr2       <= i_instruction[2:0];  
				state         <= FETCH;                     
			end
			BRANCH_EXECUTE: begin  
				o_opcode      <= i_instruction[12:9];              
				o_memRead     <= 0; 
				o_PCop      <= i_checkbranch;               
				state         <= FETCH;         
			end
			default: state <= 0;
		endcase
	end
endmodule
module control(
	input clk,reset,i_checkbranch,
	input [12:0] i_instruction, 
	output reg [3:0] o_opcode,                      
	output reg [2:0] o_destination,o_addr1,o_addr2,     
	output reg [8:0] o_branch, 
	output reg [12:0] o_PC,                     
	output reg o_memWrite,o_memRead,o_PCop);
         

	localparam RESET_STATE = 0;
	localparam FETCH = 1;
	localparam DECODE = 2;
	localparam MATH_EXECUTE = 3;
	localparam BRANCH_EXECUTE = 4;

	reg [2:0] state;

	always@(posedge clk) begin
		if(reset == 1'b1) state <= 0;
		case(state)
			RESET_STATE: begin 
				o_PCop <= 0;
				o_PC <= 0;
				o_memWrite    <= 0;
				o_memRead     <= 0;
				state <= FETCH;
				end                                     
			FETCH: begin                    
				o_opcode      <= i_instruction[12:9];
				o_addr1       <= 0;
				o_addr2       <= 0;
				o_destination <= 0;
				o_branch      <= 0;
				o_memWrite    <= 0;
				o_memRead     <= 0;
				o_PCop      <= 0;
				state         <= DECODE;
			end
			DECODE: begin                    
				if(i_instruction[12:9] == 4'b1000) begin
					o_opcode      <= i_instruction[12:9];          
					o_addr1       <= 0;           
					o_addr2       <= 0;            
					o_branch      <= i_instruction[8:0];            
					o_destination <= 0;                    
					o_memRead     <= 1;
					o_PC 	      <= 0;
					state         <= BRANCH_EXECUTE;           
				end
				else if(i_instruction[12:11] == 2'b11) begin
					o_opcode      <= i_instruction[12:9];          
					o_addr1       <= i_instruction[8:6];           
					o_addr2       <= i_instruction[5:3];            
					o_branch      <= i_instruction[2:0];            
					o_destination <= 0;                    
					o_memRead     <= 1;
					state         <= BRANCH_EXECUTE;           
				end
				else begin
					o_opcode      <= i_instruction[12:9];          
					o_destination <= i_instruction[8:6];           				
					o_addr1       <= i_instruction[5:3];            
					o_addr2       <= i_instruction[2:0];            
					o_memRead     <= 1;
					o_branch      <= 0; 
					state 		<= MATH_EXECUTE;                    
				end
			end



			MATH_EXECUTE: begin 
				o_opcode      <= i_instruction[12:9];               
				o_memWrite    <= 1;                      
				o_memRead     <= 0;
				o_PCop      <= 0; 
				o_destination <= i_instruction[8:6];
				o_addr1       <= i_instruction[5:3];            
				o_addr2       <= i_instruction[2:0];  
				state         <= FETCH;                     
			end
			BRANCH_EXECUTE: begin  
				o_opcode      <= i_instruction[12:9];              
				o_memRead     <= 0; 
				o_PCop      <= i_checkbranch;               
				state         <= FETCH;         
			end
			default: state <= 0;
		endcase
	end
endmodule