data/full_repos/permissive/513199821/balu.v
1: b'%Error: data/full_repos/permissive/513199821/balu.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: data/full_repos/permissive/513199821/balu.v:24: Define or directive not defined: \'`BALU_EQ\'\n    `BALU_EQ: balu = vl === vr;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/balu.v:24: syntax error, unexpected \':\', expecting endcase\n    `BALU_EQ: balu = vl === vr;\n            ^\n%Error: data/full_repos/permissive/513199821/balu.v:25: Define or directive not defined: \'`BALU_NE\'\n    `BALU_NE: balu = ~(vl === vr);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/balu.v:26: Define or directive not defined: \'`BALU_LT\'\n    `BALU_LT: balu = vl < vr;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/balu.v:46: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module balu #(
     parameter WIDTH = 32,
     parameter RSBIT = 3
  ) (
    input		clk,
    input		rst,
    input [RSBIT - 1:0] rs_i,
    input [WIDTH - 1:0] vl,
    input [WIDTH - 1:0] vr,
    input [2:0] 	op,

    output reg [RSBIT - 1:0] rs,
    output reg		     taken
);

function [0:0] balu (input [2:0] op, input [WIDTH - 1:0] vl, input [WIDTH - 1:0] vr);
  case (op)
    `BALU_EQ: balu = vl === vr;
    `BALU_NE: balu = ~(vl === vr);
    `BALU_LT: balu = vl < vr;
    default : balu = 1'b0;
  endcase
endfunction

wire acc = balu (op, vl, vr);

always @ (posedge clk)
begin
  if (rst) begin
    rs <= 0;
  end else begin
    rs <= 0;
    if (|rs_i) begin
      taken <= acc;
      rs    <= rs_i;
`ifdef BALU_TEST
      $display ("BALU\t%x @%x op=%x vl=%x vr=%x =%x", coreZ0.cycle, rs_i, op, vl, vr, acc);
`endif
    end
  end
end

endmodule
module balu #(
     parameter WIDTH = 32,
     parameter RSBIT = 3
  ) (
    input		clk,
    input		rst,
    input [RSBIT - 1:0] rs_i,
    input [WIDTH - 1:0] vl,
    input [WIDTH - 1:0] vr,
    input [2:0] 	op,

    output reg [RSBIT - 1:0] rs,
    output reg		     taken
);


function [0:0] balu (input [2:0] op, input [WIDTH - 1:0] vl, input [WIDTH - 1:0] vr);
  case (op)
    `BALU_EQ: balu = vl === vr;
    `BALU_NE: balu = ~(vl === vr);
    `BALU_LT: balu = vl < vr;
    default : balu = 1'b0;
  endcase
endfunction

wire acc = balu (op, vl, vr);

always @ (posedge clk)
begin
  if (rst) begin
    rs <= 0;
  end else begin
    rs <= 0;
    if (|rs_i) begin
      taken <= acc;
      rs    <= rs_i;
`ifdef BALU_TEST
      $display ("BALU\t%x @%x op=%x vl=%x vr=%x =%x", coreZ0.cycle, rs_i, op, vl, vr, acc);
`endif
    end
  end
end

endmodule