data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:11: syntax error, unexpected ::, expecting \')\' or \',\'\n    parameter type req_t                      = snitch_pkg::dreq_t,\n                                                          ^~\n                                                                                                : ... Perhaps \'snitch_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:12: syntax error, unexpected ::, expecting \';\'\n    parameter type resp_t                     = snitch_pkg::dresp_t,\n                                                          ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter bit [NrPorts-1:0] RegisterReq   = \'0,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:15: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter              Arbiter            = "rr"     \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:16: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:18: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic   rst_ni,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:20: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  req_t  [NrPorts-1:0] req_payload_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:21: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic  [NrPorts-1:0] req_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output logic  [NrPorts-1:0] req_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output resp_t [NrPorts-1:0] resp_payload_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output logic  [NrPorts-1:0] resp_last_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output logic  [NrPorts-1:0] resp_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:27: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic  [NrPorts-1:0] resp_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output req_t  req_payload_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output logic  req_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:31: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic  req_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:33: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  resp_t resp_payload_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:34: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic  resp_last_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:35: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  logic  resp_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:36: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output logic  resp_ready_o\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_demux.sv:51: syntax error, unexpected for\n  for (genvar i = 0; i < NrPorts; i++) begin : gen_spill_regs\n  ^~~\n%Error: Exiting due to 21 error(s)\n'
module snitch_demux #(
    parameter int unsigned NrPorts            = 4,
    parameter type req_t                      = snitch_pkg::dreq_t,
    parameter type resp_t                     = snitch_pkg::dresp_t,
    parameter int unsigned RespDepth          = 8,
    parameter bit [NrPorts-1:0] RegisterReq   = '0,
    parameter              Arbiter            = "rr"
) (
    input  logic   clk_i,
    input  logic   rst_ni,

    input  req_t  [NrPorts-1:0] req_payload_i,
    input  logic  [NrPorts-1:0] req_valid_i,
    output logic  [NrPorts-1:0] req_ready_o,

    output resp_t [NrPorts-1:0] resp_payload_o,
    output logic  [NrPorts-1:0] resp_last_o,
    output logic  [NrPorts-1:0] resp_valid_o,
    input  logic  [NrPorts-1:0] resp_ready_i,

    output req_t  req_payload_o,
    output logic  req_valid_o,
    input  logic  req_ready_i,

    input  resp_t resp_payload_i,
    input  logic  resp_last_i,
    input  logic  resp_valid_i,
    output logic  resp_ready_o
);

  localparam LogNrPorts = (NrPorts > 1) ? $clog2(NrPorts) : 1;

  logic [NrPorts-1:0] req_valid_masked;
  logic [NrPorts-1:0] req_ready_masked;
  logic [LogNrPorts-1:0] idx, idx_rsp;
  logic full;

  req_t  [NrPorts-1:0] req_payload_q;
  logic  [NrPorts-1:0] req_valid_q;
  logic  [NrPorts-1:0] req_ready_q;


  for (genvar i = 0; i < NrPorts; i++) begin : gen_spill_regs
      spill_register  #(
        .T      ( req_t          ),
        .Bypass ( !RegisterReq[i] )
      ) i_spill_register_tcdm_req (
        .clk_i,
        .rst_ni,
        .valid_i ( req_valid_i      [i] ),
        .ready_o ( req_ready_o      [i] ),
        .data_i  ( req_payload_i    [i] ),
        .valid_o ( req_valid_q      [i] ),
        .ready_i ( req_ready_masked [i] ),
        .data_o  ( req_payload_q    [i] )
      );
  end

  for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked
    assign req_valid_masked[i] = req_valid_q[i] & ~full;
    assign req_ready_masked[i] = req_ready_q[i] & ~full;
  end


  stream_arbiter #(
    .DATA_T  ( req_t   ),
    .N_INP   ( NrPorts ),
    .ARBITER ( Arbiter )
  ) i_stream_arbiter_req (
    .clk_i,
    .rst_ni,
    .inp_data_i   ( req_payload_q    ),
    .inp_valid_i  ( req_valid_masked ),
    .inp_ready_o  ( req_ready_q      ),
    .oup_data_o   ( req_payload_o    ),
    .oup_valid_o  ( req_valid_o      ),
    .oup_ready_i  ( req_ready_i      )
  );

  if (NrPorts == 1) begin
    assign idx_rsp = 0;
    assign full = 1'b0;
  end else begin
    onehot_to_bin #(
      .ONEHOT_WIDTH ( NrPorts )
    ) i_onehot_to_bin (
      .onehot ( req_valid_q & req_ready_q ),
      .bin    ( idx                       )
    );

    fifo_v3 #(
       .DATA_WIDTH ( LogNrPorts                                       ),
       .DEPTH      ( RespDepth                                        )
     ) i_resp_fifo (
       .clk_i,
       .rst_ni,
       .flush_i    ( 1'b0                                             ),
       .testmode_i ( 1'b0                                             ),
       .full_o     ( full                                             ),
       .empty_o    (                                                  ),
       .usage_o    (                                                  ),
       .data_i     ( idx                                              ),

       .push_i     ( req_valid_o & req_ready_i & ~req_payload_o.write ),
       .data_o     ( idx_rsp                                          ),
       .pop_i      ( resp_ready_o & resp_valid_i & resp_last_i        )
     );
   end

  stream_demux #(
    .N_OUP       ( NrPorts    )
  ) i_stream_demux_resp (
    .inp_valid_i ( resp_valid_i ),
    .inp_ready_o ( resp_ready_o ),
    .oup_sel_i   ( idx_rsp      ),
    .oup_valid_o ( resp_valid_o ),
    .oup_ready_i ( resp_ready_i )
  );

  for (genvar i = 0; i < NrPorts; i++) begin
    assign resp_payload_o[i] = resp_payload_i;
    assign resp_last_o[i] = resp_last_i;
  end

endmodule
module snitch_demux #(
    parameter int unsigned NrPorts            = 4,
    parameter type req_t                      = snitch_pkg::dreq_t,
    parameter type resp_t                     = snitch_pkg::dresp_t,
    parameter int unsigned RespDepth          = 8,
    parameter bit [NrPorts-1:0] RegisterReq   = '0,
    parameter              Arbiter            = "rr"
) (
    input  logic   clk_i,
    input  logic   rst_ni,

    input  req_t  [NrPorts-1:0] req_payload_i,
    input  logic  [NrPorts-1:0] req_valid_i,
    output logic  [NrPorts-1:0] req_ready_o,

    output resp_t [NrPorts-1:0] resp_payload_o,
    output logic  [NrPorts-1:0] resp_last_o,
    output logic  [NrPorts-1:0] resp_valid_o,
    input  logic  [NrPorts-1:0] resp_ready_i,

    output req_t  req_payload_o,
    output logic  req_valid_o,
    input  logic  req_ready_i,

    input  resp_t resp_payload_i,
    input  logic  resp_last_i,
    input  logic  resp_valid_i,
    output logic  resp_ready_o
);


  localparam LogNrPorts = (NrPorts > 1) ? $clog2(NrPorts) : 1;

  logic [NrPorts-1:0] req_valid_masked;
  logic [NrPorts-1:0] req_ready_masked;
  logic [LogNrPorts-1:0] idx, idx_rsp;
  logic full;

  req_t  [NrPorts-1:0] req_payload_q;
  logic  [NrPorts-1:0] req_valid_q;
  logic  [NrPorts-1:0] req_ready_q;


  for (genvar i = 0; i < NrPorts; i++) begin : gen_spill_regs
      spill_register  #(
        .T      ( req_t          ),
        .Bypass ( !RegisterReq[i] )
      ) i_spill_register_tcdm_req (
        .clk_i,
        .rst_ni,
        .valid_i ( req_valid_i      [i] ),
        .ready_o ( req_ready_o      [i] ),
        .data_i  ( req_payload_i    [i] ),
        .valid_o ( req_valid_q      [i] ),
        .ready_i ( req_ready_masked [i] ),
        .data_o  ( req_payload_q    [i] )
      );
  end

  for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked
    assign req_valid_masked[i] = req_valid_q[i] & ~full;
    assign req_ready_masked[i] = req_ready_q[i] & ~full;
  end


  stream_arbiter #(
    .DATA_T  ( req_t   ),
    .N_INP   ( NrPorts ),
    .ARBITER ( Arbiter )
  ) i_stream_arbiter_req (
    .clk_i,
    .rst_ni,
    .inp_data_i   ( req_payload_q    ),
    .inp_valid_i  ( req_valid_masked ),
    .inp_ready_o  ( req_ready_q      ),
    .oup_data_o   ( req_payload_o    ),
    .oup_valid_o  ( req_valid_o      ),
    .oup_ready_i  ( req_ready_i      )
  );

  if (NrPorts == 1) begin
    assign idx_rsp = 0;
    assign full = 1'b0;
  end else begin
    onehot_to_bin #(
      .ONEHOT_WIDTH ( NrPorts )
    ) i_onehot_to_bin (
      .onehot ( req_valid_q & req_ready_q ),
      .bin    ( idx                       )
    );

    fifo_v3 #(
       .DATA_WIDTH ( LogNrPorts                                       ),
       .DEPTH      ( RespDepth                                        )
     ) i_resp_fifo (
       .clk_i,
       .rst_ni,
       .flush_i    ( 1'b0                                             ),
       .testmode_i ( 1'b0                                             ),
       .full_o     ( full                                             ),
       .empty_o    (                                                  ),
       .usage_o    (                                                  ),
       .data_i     ( idx                                              ),

       .push_i     ( req_valid_o & req_ready_i & ~req_payload_o.write ),
       .data_o     ( idx_rsp                                          ),
       .pop_i      ( resp_ready_o & resp_valid_i & resp_last_i        )
     );
   end

  stream_demux #(
    .N_OUP       ( NrPorts    )
  ) i_stream_demux_resp (
    .inp_valid_i ( resp_valid_i ),
    .inp_ready_o ( resp_ready_o ),
    .oup_sel_i   ( idx_rsp      ),
    .oup_valid_o ( resp_valid_o ),
    .oup_ready_i ( resp_ready_i )
  );

  for (genvar i = 0; i < NrPorts; i++) begin
    assign resp_payload_o[i] = resp_payload_i;
    assign resp_last_o[i] = resp_last_i;
  end

endmodule