data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_buf.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_buf.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_buf.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module c2i_buf (

   ucb_buf_acpt, iob_ucb_vld, iob_ucb_data, 

   rst_l, clk, c2i_packet_vld, ucb_sel, c2i_packet, ucb_iob_stall
   );


   
   parameter REG_WIDTH = 64;
   parameter IOB_UCB_WIDTH = 32;
   
   




   input                      rst_l;
   input 		      clk;



   input 		      c2i_packet_vld;
   input 		      ucb_sel;
   output 		      ucb_buf_acpt;

   

   input [REG_WIDTH+63:0]     c2i_packet;
   
   

   output                     iob_ucb_vld;
   output [IOB_UCB_WIDTH-1:0] iob_ucb_data;
   input 	              ucb_iob_stall;
   
   

   wire 		      dbl_buf_wr;
   wire 		      dbl_buf_rd;
   wire 		      dbl_buf_vld;
   wire 		      dbl_buf_full;
   
   wire 		      outdata_buf_wr;
   wire [REG_WIDTH+63:0]      outdata_buf_in;
   wire [(REG_WIDTH+64)/IOB_UCB_WIDTH-1:0] outdata_vec_in;
   wire 		      outdata_buf_busy;

   




   assign 	 dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
   assign 	 ucb_buf_acpt = dbl_buf_wr;
   assign 	 dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
   assign 	 outdata_buf_wr = dbl_buf_rd;
   assign 	 outdata_vec_in = {(REG_WIDTH+64)/IOB_UCB_WIDTH{1'b1}};
   

   dbl_buf #(REG_WIDTH+64) dbl_buf (.rst_l(rst_l),
				    .clk(clk),
				    .wr(dbl_buf_wr),
				    .din(c2i_packet),
				    .rd(dbl_buf_rd),
				    .dout(outdata_buf_in),
				    .vld(dbl_buf_vld),
				    .full(dbl_buf_full));
   
   ucb_bus_out #(IOB_UCB_WIDTH,REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
                                                       .clk(clk),
                                                       .outdata_buf_wr(outdata_buf_wr),
                                                       .outdata_buf_in(outdata_buf_in),
                                                       .outdata_vec_in(outdata_vec_in),
                                                       .outdata_buf_busy(outdata_buf_busy),
                                                       .vld(iob_ucb_vld),
                                                       .data(iob_ucb_data),
                                                       .stall(ucb_iob_stall));


endmodule
module c2i_buf (

   ucb_buf_acpt, iob_ucb_vld, iob_ucb_data, 

   rst_l, clk, c2i_packet_vld, ucb_sel, c2i_packet, ucb_iob_stall
   );



   
   parameter REG_WIDTH = 64;
   parameter IOB_UCB_WIDTH = 32;
   
   




   input                      rst_l;
   input 		      clk;



   input 		      c2i_packet_vld;
   input 		      ucb_sel;
   output 		      ucb_buf_acpt;

   

   input [REG_WIDTH+63:0]     c2i_packet;
   
   

   output                     iob_ucb_vld;
   output [IOB_UCB_WIDTH-1:0] iob_ucb_data;
   input 	              ucb_iob_stall;
   
   

   wire 		      dbl_buf_wr;
   wire 		      dbl_buf_rd;
   wire 		      dbl_buf_vld;
   wire 		      dbl_buf_full;
   
   wire 		      outdata_buf_wr;
   wire [REG_WIDTH+63:0]      outdata_buf_in;
   wire [(REG_WIDTH+64)/IOB_UCB_WIDTH-1:0] outdata_vec_in;
   wire 		      outdata_buf_busy;

   




   assign 	 dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
   assign 	 ucb_buf_acpt = dbl_buf_wr;
   assign 	 dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
   assign 	 outdata_buf_wr = dbl_buf_rd;
   assign 	 outdata_vec_in = {(REG_WIDTH+64)/IOB_UCB_WIDTH{1'b1}};
   

   dbl_buf #(REG_WIDTH+64) dbl_buf (.rst_l(rst_l),
				    .clk(clk),
				    .wr(dbl_buf_wr),
				    .din(c2i_packet),
				    .rd(dbl_buf_rd),
				    .dout(outdata_buf_in),
				    .vld(dbl_buf_vld),
				    .full(dbl_buf_full));
   
   ucb_bus_out #(IOB_UCB_WIDTH,REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
                                                       .clk(clk),
                                                       .outdata_buf_wr(outdata_buf_wr),
                                                       .outdata_buf_in(outdata_buf_in),
                                                       .outdata_vec_in(outdata_vec_in),
                                                       .outdata_buf_busy(outdata_buf_busy),
                                                       .vld(iob_ucb_vld),
                                                       .data(iob_ucb_data),
                                                       .stall(ucb_iob_stall));


endmodule