data/full_repos/permissive/52682338/Cartridge/aes_cha.v
1: b"%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:50: Cannot find file containing module: 'rom_c1'\n rom_c1 C1(C_ADDR[17:0], C1DATA);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_c1\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_c1.v\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_c1.sv\n             rom_c1\n             rom_c1.v\n             rom_c1.sv\n             obj_dir/rom_c1\n             obj_dir/rom_c1.v\n             obj_dir/rom_c1.sv\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:51: Cannot find file containing module: 'rom_c2'\n rom_c2 C2(C_ADDR[17:0], C2DATA);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:52: Cannot find file containing module: 'rom_s1'\n rom_s1 S1(S_ADDR[16:0], FIXD);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:54: Cannot find file containing module: 'rom_m1'\n rom_m1 M1(SDA, SDD, nSDROM, nSDMRD);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:56: Cannot find file containing module: 'neo_zmc2'\n neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, DOTA, DOTB);\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_cha.v:62: Cannot find file containing module: 'neo_273'\n neo_273 N273(PBUS[19:0], PCK1B, PCK2B, C_LATCH, S_LATCH);\n ^~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module aes_cha(
	input CLK_24M,
	input nSDROM, nSDMRD,
	input [15:0] SDA,
	input SDRD1, SDRD0, 
	input [23:0] PBUS,
	input CA4, LOAD, H, EVEN, S2H1,
	input CLK_12M,
	input PCK2B, PCK1B,
	output [7:0] FIXD,
	output DOTA, DOTB,
	output [3:0] GAD,
	output [3:0] GBD,
	inout [7:0] SDD,
	input CLK_8M
);

	wire [19:0] C_LATCH;
	wire [15:0] S_LATCH;
	wire [20:0] C_ADDR;
	wire [16:0] S_ADDR;
	wire [15:0] C1DATA;
	wire [15:0] C2DATA;
	wire [21:11] MA;
	wire [31:0] CR;
	
	assign C_ADDR = {C_LATCH[19:4], CA4, C_LATCH[3:0]};
	assign S_ADDR = {S_LATCH[15:3], S2H1, S_LATCH[2:0]};
	
	assign CR = {C1DATA, C2DATA};
	
	rom_c1 C1(C_ADDR[17:0], C1DATA);
	rom_c2 C2(C_ADDR[17:0], C2DATA);
	rom_s1 S1(S_ADDR[16:0], FIXD);
	
	rom_m1 M1(SDA, SDD, nSDROM, nSDMRD);
	
	neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, DOTA, DOTB);
	



	
	neo_273 N273(PBUS[19:0], PCK1B, PCK2B, C_LATCH, S_LATCH);

endmodule
module aes_cha(
	input CLK_24M,
	input nSDROM, nSDMRD,
	input [15:0] SDA,
	input SDRD1, SDRD0, 
	input [23:0] PBUS,
	input CA4, LOAD, H, EVEN, S2H1,
	input CLK_12M,
	input PCK2B, PCK1B,
	output [7:0] FIXD,
	output DOTA, DOTB,
	output [3:0] GAD,
	output [3:0] GBD,
	inout [7:0] SDD,
	input CLK_8M
);


	wire [19:0] C_LATCH;
	wire [15:0] S_LATCH;
	wire [20:0] C_ADDR;
	wire [16:0] S_ADDR;
	wire [15:0] C1DATA;
	wire [15:0] C2DATA;
	wire [21:11] MA;
	wire [31:0] CR;
	
	assign C_ADDR = {C_LATCH[19:4], CA4, C_LATCH[3:0]};
	assign S_ADDR = {S_LATCH[15:3], S2H1, S_LATCH[2:0]};
	
	assign CR = {C1DATA, C2DATA};
	
	rom_c1 C1(C_ADDR[17:0], C1DATA);
	rom_c2 C2(C_ADDR[17:0], C2DATA);
	rom_s1 S1(S_ADDR[16:0], FIXD);
	
	rom_m1 M1(SDA, SDD, nSDROM, nSDMRD);
	
	neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, DOTA, DOTB);
	



	
	neo_273 N273(PBUS[19:0], PCK1B, PCK2B, C_LATCH, S_LATCH);

endmodule