data/full_repos/permissive/500711628/phase_counter/phase_counter.v
data/verilator_xmls/32750317-56c9-4f55-bf50-df8a981bd96e.xml
module phase_counter
(
	input clock,
	input reset,
	input exec,

	output reg phase1,
	output reg phase2,
	output reg phase3
);
	
	reg [1:0] count = 2'b00;

	

	always @(posedge clock) begin
		if(reset) begin 
			count <= 2'b00;
		end 

		else begin

				if(count == 2'b00) begin
					phase1 <= 1'b1;
					phase2 <= 1'b0;
					phase3 <= 1'b0;
					count <= 2'b01;
				end 
				else begin
					phase1 <= 1'b0;
					phase2 <= 1'b1;
					phase3 <= 1'b0;
					count <= 2'b00;
				end


		end
	end
	
endmodule
module phase_counter
(
	input clock,
	input reset,
	input exec,

	output reg phase1,
	output reg phase2,
	output reg phase3
);

	
	reg [1:0] count = 2'b00;

	

	always @(posedge clock) begin
		if(reset) begin 
			count <= 2'b00;
		end 

		else begin

				if(count == 2'b00) begin
					phase1 <= 1'b1;
					phase2 <= 1'b0;
					phase3 <= 1'b0;
					count <= 2'b01;
				end 
				else begin
					phase1 <= 1'b0;
					phase2 <= 1'b1;
					phase3 <= 1'b0;
					count <= 2'b00;
				end


		end
	end
	
endmodule