data/full_repos/permissive/423852699/verilog/IMEM.v
data/verilator_xmls/651338c9-45c1-4220-8135-91268b937e5f.xml
module IMEM (
    input wire[31:0] a,

    output wire[31:0] spo
);

    reg[31:0] inst_array[0:255];

    assign spo = inst_array[a[7:0]];
    
endmodule
module IMEM (
    input wire[31:0] a,

    output wire[31:0] spo
);


    reg[31:0] inst_array[0:255];

    assign spo = inst_array[a[7:0]];
    
endmodule