data/full_repos/permissive/487568919/generic_systemverilog_designs_library/binary_to_gray/binary_to_gray.sv
data/verilator_xmls/b26a81ca-2b59-4697-9bad-b1c6f767d2e8.xml
module binary_to_gray
  #(parameter WIDTH=4)
  (input  logic [WIDTH-1:0] b_in,
   output logic [WIDTH-1:0] g_out);
  
  always_comb begin
    g_out[WIDTH-1] = b_in[WIDTH-1];
    foreach (g_out[i]) 
      g_out[i-1] = b_in[i]^b_in[i-1]; 
  end
  
endmodule
module binary_to_gray
  #(parameter WIDTH=4)
  (input  logic [WIDTH-1:0] b_in,
   output logic [WIDTH-1:0] g_out);

  
  always_comb begin
    g_out[WIDTH-1] = b_in[WIDTH-1];
    foreach (g_out[i]) 
      g_out[i-1] = b_in[i]^b_in[i-1]; 
  end
  
endmodule