data/full_repos/permissive/504762811/regfile.v
1: b'%Error: data/full_repos/permissive/504762811/regfile.v:1: Cannot find include file: minicpu.h\n`include "minicpu.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.v\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.sv\n             minicpu.h\n             minicpu.h.v\n             minicpu.h.sv\n             obj_dir/minicpu.h\n             obj_dir/minicpu.h.v\n             obj_dir/minicpu.h.sv\n%Error: data/full_repos/permissive/504762811/regfile.v:9: Define or directive not defined: \'`DataBus\'\n output reg [`DataBus] valA,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output reg [`DataBus] valA,\n                     ^\n%Error: data/full_repos/permissive/504762811/regfile.v:10: Define or directive not defined: \'`DataBus\'\n output reg [`DataBus] valB,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [2:0] dstE,\n ^~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`DataBus] valM,\n ^~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:13: Define or directive not defined: \'`DataBus\'\n input wire [`DataBus] valM,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:14: Define or directive not defined: \'`DataBus\'\n input wire [`DataBus] valE,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire we_  \n ^~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:18: Define or directive not defined: \'`DataBus\'\n reg [`DataBus] rf [7:1];  \n      ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/regfile.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`DataBus] rf [7:1];  \n              ^\n%Error: data/full_repos/permissive/504762811/regfile.v:33: Define or directive not defined: \'`ENABLE_\'\n  if(we_==`ENABLE_) begin\n          ^~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module regfile (
	input wire [2:0] srcA,
	input wire [2:0] srcB,
	output reg [`DataBus] valA,
	output reg [`DataBus] valB,
	input wire [2:0] dstM,
	input wire [2:0] dstE,
	input wire [`DataBus] valM,
	input wire [`DataBus] valE,
	input wire clk,
	input wire we_
);
	reg [`DataBus] rf [7:1];
	



	always @(*) begin
		valA = (srcA)? rf[srcA]: 0;
		valB = (srcB)? rf[srcB]: 0;
		$write("%-5d: !!DecodePhase: \n", $time);
		$write("       !!valAFetching: regNum:%o  content:%x  result:valA=%x \n", srcA, rf[srcA], valA);
		$write("      !!valBFetching: regNum:%o  content:%x  result:valB=%x \n", srcB, rf[srcB], valB);
		end
		

	always @(posedge clk)
		if(we_==`ENABLE_) begin


			if(dstM) begin 
				rf[dstM] <= valM;
				$write("%-5d: !!!!MemoryAccessResult: ",$time);	
				$write("       !!!!regNum:%o  ", dstM);
				$write("       !!!!valM: %x(x),%d(d) ", valM,valM);
				$write("\n");
			end
			if(dstE && dstE!=dstM) begin 
				rf[dstE] <= valE;
				$write("%-5d: !!!!ExecutionResult: ",$time);	
				$write("       !!!!regNum:%o  ", dstE);
				$write("       !!!!valE: %x(x),%d(d) ", valE,valE);
				$write("\n");
			end
		end
endmodule
module regfile (
	input wire [2:0] srcA,
	input wire [2:0] srcB,
	output reg [`DataBus] valA,
	output reg [`DataBus] valB,
	input wire [2:0] dstM,
	input wire [2:0] dstE,
	input wire [`DataBus] valM,
	input wire [`DataBus] valE,
	input wire clk,
	input wire we_
);

	reg [`DataBus] rf [7:1];
	



	always @(*) begin
		valA = (srcA)? rf[srcA]: 0;
		valB = (srcB)? rf[srcB]: 0;
		$write("%-5d: !!DecodePhase: \n", $time);
		$write("       !!valAFetching: regNum:%o  content:%x  result:valA=%x \n", srcA, rf[srcA], valA);
		$write("      !!valBFetching: regNum:%o  content:%x  result:valB=%x \n", srcB, rf[srcB], valB);
		end
		

	always @(posedge clk)
		if(we_==`ENABLE_) begin


			if(dstM) begin 
				rf[dstM] <= valM;
				$write("%-5d: !!!!MemoryAccessResult: ",$time);	
				$write("       !!!!regNum:%o  ", dstM);
				$write("       !!!!valM: %x(x),%d(d) ", valM,valM);
				$write("\n");
			end
			if(dstE && dstE!=dstM) begin 
				rf[dstE] <= valE;
				$write("%-5d: !!!!ExecutionResult: ",$time);	
				$write("       !!!!regNum:%o  ", dstE);
				$write("       !!!!valE: %x(x),%d(d) ", valE,valE);
				$write("\n");
			end
		end
endmodule