data/full_repos/permissive/434840709/week11/7.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/week11/7.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/434840709/week11/7.v:11: Cannot find file containing module: \'dut\'\ndut d_instance( .clk(clk)) ;\n^~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/week11,data/full_repos/permissive/434840709/dut\n             data/full_repos/permissive/434840709/week11,data/full_repos/permissive/434840709/dut.v\n             data/full_repos/permissive/434840709/week11,data/full_repos/permissive/434840709/dut.sv\n             dut\n             dut.v\n             dut.sv\n             obj_dir/dut\n             obj_dir/dut.v\n             obj_dir/dut.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module ( );

reg clk;

initial begin
    clk = 1'b0;
end

    always #5 clk = ~clk;
dut d_instance( .clk(clk)) ;
endmodule
module top_module ( );


reg clk;

initial begin
    clk = 1'b0;
end

    always #5 clk = ~clk;
dut d_instance( .clk(clk)) ;
endmodule