data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:6: Signal definition not found, creating implicitly: \'d\'\n    assign d = 65 - 1;\n           ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:8: Signal definition not found, creating implicitly: \'Z\'\n    assign Z = 32\'b0010101;\n           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:10: Can\'t find definition of variable: \'b\'\n    assign a = !b;\n                ^\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:10: Signal definition not found, creating implicitly: \'a\'\n    assign a = !b;\n           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:12: Can\'t find definition of variable: \'op_d\'\n    assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] |\n                          ^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:12: Can\'t find definition of variable: \'op3_d\'\n                                                                                              : ... Suggested alternative: \'op_d\'\n    assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] |\n                                               ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:17: Can\'t find definition of variable: \'dtu_dcl_opf2_d\'\n                 dtu_dcl_opf2_d);                           \n                 ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/expression_tostring.v:12: Signal definition not found, creating implicitly: \'cc_mvbr_d\'\n    assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] |\n           ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module dummy();
    
    assign d = `NUMBER - 1;

    assign Z = 32'b0010101;
    
    assign a = !b;

    assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] |
 			             op_d[1] & ~op_d[0] & op3_d[5] & ~op3_d[4] &
 			            op3_d[3] & op3_d[2] & op3_d[1] & op3_d[0] | 
 			             op_d[1] & ~op_d[0] & op3_d[5] & op3_d[4] &
 			           ~op3_d[3] & op3_d[2] & ~op3_d[1] & op3_d[0] &
 			             dtu_dcl_opf2_d);                           
    

endmodule
module dummy();

    
    assign d = `NUMBER - 1;

    assign Z = 32'b0010101;
    
    assign a = !b;

    assign cc_mvbr_d = ~(~op_d[1] & ~op_d[0] & op3_d[4] & op3_d[3] |
 			             op_d[1] & ~op_d[0] & op3_d[5] & ~op3_d[4] &
 			            op3_d[3] & op3_d[2] & op3_d[1] & op3_d[0] | 
 			             op_d[1] & ~op_d[0] & op3_d[5] & op3_d[4] &
 			           ~op3_d[3] & op3_d[2] & ~op3_d[1] & op3_d[0] &
 			             dtu_dcl_opf2_d);                           
    

endmodule