data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/VcdAdder/reference/VcdAdder.v:66: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 9 bits.\n                                                                                                          : ... In instance VcdAdder.do_add.s_pad_2\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ADD_SIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule
module ADD_SIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule