data/full_repos/permissive/427221126/workspace/PE.sv
1: b'%Error: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsupported: Replication to form \'logic[15:0]$[0:6]\' data type\n                                                               : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                    ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                     ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:66: Unsized numbers/parameters not allowed in replications.\n                                                                             : ... In instance PE\n        data_in <= {0,0,0,0,0,0,0};\n                               ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:67: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        filter  <= {0,0,0};\n                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:67: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        filter  <= {0,0,0};\n                    ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:67: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        filter  <= {0,0,0};\n                     ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:67: Unsized numbers/parameters not allowed in replications.\n                                                                             : ... In instance PE\n        filter  <= {0,0,0};\n                       ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:86: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n    if(rst) data = {0,0,0};\n                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:86: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n    if(rst) data = {0,0,0};\n                    ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:86: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n    if(rst) data = {0,0,0};\n                     ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:86: Unsized numbers/parameters not allowed in replications.\n                                                                             : ... In instance PE\n    if(rst) data = {0,0,0};\n                       ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:89: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        0: data = {data_in[0],data_in[1],data_in[2]} ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/workspace/PE.sv:89: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance PE\n        0: data = {data_in[0],data_in[1],data_in[2]} ;\n                ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:90: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        1: data = {data_in[1],data_in[2],data_in[3]} ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/workspace/PE.sv:90: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance PE\n        1: data = {data_in[1],data_in[2],data_in[3]} ;\n                ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:91: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        2: data = {data_in[2],data_in[3],data_in[4]} ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/workspace/PE.sv:91: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance PE\n        2: data = {data_in[2],data_in[3],data_in[4]} ;\n                ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:92: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        3: data = {data_in[3],data_in[4],data_in[5]} ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/workspace/PE.sv:92: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance PE\n        3: data = {data_in[3],data_in[4],data_in[5]} ;\n                ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:93: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        4: data = {data_in[4],data_in[5],data_in[6]} ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/workspace/PE.sv:93: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance PE\n        4: data = {data_in[4],data_in[5],data_in[6]} ;\n                ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:94: Unsupported: Replication to form \'logic[15:0]$[0:2]\' data type\n                                                               : ... In instance PE\n        default: data = {0,0,0};\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:94: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        default: data = {0,0,0};\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:94: Unsized numbers/parameters not allowed in concatenations.\n                                                                             : ... In instance PE\n        default: data = {0,0,0};\n                          ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:94: Unsized numbers/parameters not allowed in replications.\n                                                                             : ... In instance PE\n        default: data = {0,0,0};\n                            ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsupported: Replication to form \'logic[15:0]$[0:4]\' data type\n                                                                : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                    ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                     ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                          ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:100: Unsized numbers/parameters not allowed in replications.\n                                                                              : ... In instance PE\n    if(rst) psum <= {0,0,0,0,0};\n                            ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsupported: Replication to form \'logic[15:0]$[0:4]\' data type\n                                                                : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                          ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsized numbers/parameters not allowed in concatenations.\n                                                                              : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/PE.sv:109: Unsized numbers/parameters not allowed in replications.\n                                                                              : ... In instance PE\n        default: psum <= {0,0,0,0,0};\n                                 ^\n%Error: data/full_repos/permissive/427221126/workspace/PE.sv:113: Cannot find file containing module: \'vector_mult\'\nvector_mult m1(.A(filter),.B(data),.RES(res));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/vector_mult\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/vector_mult.v\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/vector_mult.sv\n             vector_mult\n             vector_mult.v\n             vector_mult.sv\n             obj_dir/vector_mult\n             obj_dir/vector_mult.v\n             obj_dir/vector_mult.sv\n%Error: Exiting due to 12 error(s), 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE

(
    input clk,rst,en,

    input   [15:0] FILTER_IN   [0:2],
    input   [15:0] DATA_IN     [0:6],
    input   [15:0] PSUM_IN     [0:4],

    output  [15:0] FILTER_OUT  [0:2],
    output  [15:0] DATA_OUT    [0:6],
    output  [15:0] PSUM_OUT    [0:4],
    output         DONE
);


reg  [15:0]data_in     [0:6];
reg  [15:0]filter   [0:2]; 
reg  [15:0]psum     [0:4];

reg [15:0] data [0:2];

wire [15:0]res;
reg done;
reg [1:0] state,state_next;

parameter [1:0] IDLE = 2'd0,
                INPT = 2'd1,
                COMP = 2'd2,
                OUPT = 2'd3;
reg [2:0]counter;

reg flag;
always @(posedge clk) begin
    if(rst) flag <= 0;
    else if(en) flag <= 1;
    else if(done) flag <= 0;
end

always @(posedge clk) begin
    if(rst||en) begin
        state <= IDLE;
    end
    else begin
        state <= state_next;
    end
end

always @(*) begin
    if(rst) state_next = IDLE;
    else begin
    case (state) 
         IDLE: if(en) state_next = INPT ;
         INPT: if(flag) state_next = COMP;    
         COMP: if(counter == 4) state_next = OUPT;
         OUPT: state_next = IDLE;
        default: state_next = IDLE;
    endcase  
    end  
end


always @(posedge clk) begin
    if(rst) begin
        data_in <= {0,0,0,0,0,0,0};
        filter  <= {0,0,0};
    end
    else if(state_next == INPT) begin
        data_in <= DATA_IN;
        filter <= FILTER_IN;
    end
end


always @(posedge clk) begin
    if(rst||en) begin
        counter <= 0;
    end
    else if((state_next ==  COMP) && flag) begin
        counter <= counter + 1;
    end
end

always @(*) begin 
    if(rst) data = {0,0,0};
    else begin
    case (counter)
        0: data = {data_in[0],data_in[1],data_in[2]} ;
        1: data = {data_in[1],data_in[2],data_in[3]} ;
        2: data = {data_in[2],data_in[3],data_in[4]} ;
        3: data = {data_in[3],data_in[4],data_in[5]} ;
        4: data = {data_in[4],data_in[5],data_in[6]} ;
        default: data = {0,0,0};
    endcase
    end
end

always @(posedge clk) begin
    if(rst) psum <= {0,0,0,0,0};
    else if(state_next == INPT) psum <= PSUM_IN;
    else
    case(counter)
        0: if(state_next == COMP)psum[0] <= psum[0] + res;
        1: psum[1] <= psum[1] + res;
        2: psum[2] <= psum[2] + res;
        3: psum[3] <= psum[3] + res;
        4: if(state_next == OUPT) psum[4] <= psum[4] + res; 
        default: psum <= {0,0,0,0,0};
    endcase
end

vector_mult m1(.A(filter),.B(data),.RES(res));


always @(posedge clk) begin
    if(rst) done <= 0;
    else  if(state_next == OUPT)
        done <= 1;
    else    
        done <= 0;

end


assign  DATA_OUT = data_in;
assign  PSUM_OUT = psum;
assign  FILTER_OUT = filter;
assign  DONE = done;

endmodule
module PE

(
    input clk,rst,en,

    input   [15:0] FILTER_IN   [0:2],
    input   [15:0] DATA_IN     [0:6],
    input   [15:0] PSUM_IN     [0:4],

    output  [15:0] FILTER_OUT  [0:2],
    output  [15:0] DATA_OUT    [0:6],
    output  [15:0] PSUM_OUT    [0:4],
    output         DONE
);



reg  [15:0]data_in     [0:6];
reg  [15:0]filter   [0:2]; 
reg  [15:0]psum     [0:4];

reg [15:0] data [0:2];

wire [15:0]res;
reg done;
reg [1:0] state,state_next;

parameter [1:0] IDLE = 2'd0,
                INPT = 2'd1,
                COMP = 2'd2,
                OUPT = 2'd3;
reg [2:0]counter;

reg flag;
always @(posedge clk) begin
    if(rst) flag <= 0;
    else if(en) flag <= 1;
    else if(done) flag <= 0;
end

always @(posedge clk) begin
    if(rst||en) begin
        state <= IDLE;
    end
    else begin
        state <= state_next;
    end
end

always @(*) begin
    if(rst) state_next = IDLE;
    else begin
    case (state) 
         IDLE: if(en) state_next = INPT ;
         INPT: if(flag) state_next = COMP;    
         COMP: if(counter == 4) state_next = OUPT;
         OUPT: state_next = IDLE;
        default: state_next = IDLE;
    endcase  
    end  
end


always @(posedge clk) begin
    if(rst) begin
        data_in <= {0,0,0,0,0,0,0};
        filter  <= {0,0,0};
    end
    else if(state_next == INPT) begin
        data_in <= DATA_IN;
        filter <= FILTER_IN;
    end
end


always @(posedge clk) begin
    if(rst||en) begin
        counter <= 0;
    end
    else if((state_next ==  COMP) && flag) begin
        counter <= counter + 1;
    end
end

always @(*) begin 
    if(rst) data = {0,0,0};
    else begin
    case (counter)
        0: data = {data_in[0],data_in[1],data_in[2]} ;
        1: data = {data_in[1],data_in[2],data_in[3]} ;
        2: data = {data_in[2],data_in[3],data_in[4]} ;
        3: data = {data_in[3],data_in[4],data_in[5]} ;
        4: data = {data_in[4],data_in[5],data_in[6]} ;
        default: data = {0,0,0};
    endcase
    end
end

always @(posedge clk) begin
    if(rst) psum <= {0,0,0,0,0};
    else if(state_next == INPT) psum <= PSUM_IN;
    else
    case(counter)
        0: if(state_next == COMP)psum[0] <= psum[0] + res;
        1: psum[1] <= psum[1] + res;
        2: psum[2] <= psum[2] + res;
        3: psum[3] <= psum[3] + res;
        4: if(state_next == OUPT) psum[4] <= psum[4] + res; 
        default: psum <= {0,0,0,0,0};
    endcase
end

vector_mult m1(.A(filter),.B(data),.RES(res));


always @(posedge clk) begin
    if(rst) done <= 0;
    else  if(state_next == OUPT)
        done <= 1;
    else    
        done <= 0;

end


assign  DATA_OUT = data_in;
assign  PSUM_OUT = psum;
assign  FILTER_OUT = filter;
assign  DONE = done;

endmodule