data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v
1: b'%Error: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:1: Cannot find include file: controller.v\n`include "controller.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491934675/ECE251/controller,data/full_repos/permissive/491934675/controller.v\n             data/full_repos/permissive/491934675/ECE251/controller,data/full_repos/permissive/491934675/controller.v.v\n             data/full_repos/permissive/491934675/ECE251/controller,data/full_repos/permissive/491934675/controller.v.sv\n             controller.v\n             controller.v.v\n             controller.v.sv\n             obj_dir/controller.v\n             obj_dir/controller.v.v\n             obj_dir/controller.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #90;\n    ^\n%Error: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("controller_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/controller/controller_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, pc, clk, instruction, flags, be, rw, mmuxsel, je, re0, memwrite);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module controller_tb();

reg clk;
wire [7:0] pc;
wire be, rw, mmuxsel, je, re0, memwrite;

reg [15:0] instruction;
reg [1:0] flags;


controller test(clk, instruction, flags, pc, be, rw, mmuxsel, je, re0, memwrite);




initial begin
    clk = 0;
    for(integer i = 0; i<10; i=i+1) begin
        #10;
        clk = ~clk;
    end
end

initial begin
    instruction = 16'b1111111111111111;
    #10;
    instruction = 16'b1010101010101010;
    #90;
    instruction = 16'b0000000000000000;
    flags = 2'd0;
end

initial begin
    $dumpfile("controller_tb.vcd");
    $dumpvars(0, pc, clk, instruction, flags, be, rw, mmuxsel, je, re0, memwrite);

end

endmodule
module controller_tb();


reg clk;
wire [7:0] pc;
wire be, rw, mmuxsel, je, re0, memwrite;

reg [15:0] instruction;
reg [1:0] flags;


controller test(clk, instruction, flags, pc, be, rw, mmuxsel, je, re0, memwrite);




initial begin
    clk = 0;
    for(integer i = 0; i<10; i=i+1) begin
        #10;
        clk = ~clk;
    end
end

initial begin
    instruction = 16'b1111111111111111;
    #10;
    instruction = 16'b1010101010101010;
    #90;
    instruction = 16'b0000000000000000;
    flags = 2'd0;
end

initial begin
    $dumpfile("controller_tb.vcd");
    $dumpvars(0, pc, clk, instruction, flags, be, rw, mmuxsel, je, re0, memwrite);

end

endmodule