data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/HILO.v
data/verilator_xmls/39b8d247-62ce-4f25-a43e-ea706a492f0c.xml
module HILO(
    input clk,
    input rst,
    input wire I_FromMEMWB_wreg,
    input wire [31:0] I_FromMEMWB_hi,
    input wire [31:0] I_FromMEMWB_lo,
    output reg [31:0] O_ToEX_hi,
    output reg [31:0] O_ToEX_lo
);

always @(posedge clk) begin
    if(rst == 1'b0) begin
        O_ToEX_hi<=32'b0;
        O_ToEX_lo<=32'b0;
    end else if (I_FromMEMWB_wreg==1'b1) begin
        O_ToEX_hi<=I_FromMEMWB_hi;
        O_ToEX_lo<=I_FromMEMWB_lo;
    end
end
    
endmodule
module HILO(
    input clk,
    input rst,
    input wire I_FromMEMWB_wreg,
    input wire [31:0] I_FromMEMWB_hi,
    input wire [31:0] I_FromMEMWB_lo,
    output reg [31:0] O_ToEX_hi,
    output reg [31:0] O_ToEX_lo
);


always @(posedge clk) begin
    if(rst == 1'b0) begin
        O_ToEX_hi<=32'b0;
        O_ToEX_lo<=32'b0;
    end else if (I_FromMEMWB_wreg==1'b1) begin
        O_ToEX_hi<=I_FromMEMWB_hi;
        O_ToEX_lo<=I_FromMEMWB_lo;
    end
end
    
endmodule