data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:21: Cannot find include file: common_cells/registers.svh\n`include "common_cells/registers.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh.sv\n             common_cells/registers.svh\n             common_cells/registers.svh.v\n             common_cells/registers.svh.sv\n             obj_dir/common_cells/registers.svh\n             obj_dir/common_cells/registers.svh.v\n             obj_dir/common_cells/registers.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:390: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:391: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:184: Define or directive not defined: \'`FFLARN\'\n    `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, \'0, clk_i, rst_ni)\n    ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:184: syntax error, unexpected \'(\'\n    `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, \'0, clk_i, rst_ni)\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:420: Define or directive not defined: \'`AXI_LITE_TYPEDEF_AW_CHAN_T\'\n  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:420: syntax error, unexpected \'(\'\n  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:421: Define or directive not defined: \'`AXI_LITE_TYPEDEF_W_CHAN_T\'\n  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:422: Define or directive not defined: \'`AXI_LITE_TYPEDEF_B_CHAN_T\'\n  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:423: Define or directive not defined: \'`AXI_LITE_TYPEDEF_AR_CHAN_T\'\n  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:424: Define or directive not defined: \'`AXI_LITE_TYPEDEF_R_CHAN_T\'\n  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:425: Define or directive not defined: \'`AXI_LITE_TYPEDEF_REQ_T\'\n  `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:426: Define or directive not defined: \'`AXI_LITE_TYPEDEF_RESP_T\'\n  `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:434: Define or directive not defined: \'`AXI_LITE_ASSIGN_TO_REQ\'\n    `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:434: syntax error, unexpected \'(\'\n    `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:435: Define or directive not defined: \'`AXI_LITE_ASSIGN_FROM_RESP\'\n    `AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:438: Define or directive not defined: \'`AXI_LITE_ASSIGN_FROM_REQ\'\n  `AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_lite_mux.sv:439: Define or directive not defined: \'`AXI_LITE_ASSIGN_TO_RESP\'\n  `AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst)\n  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module axi_lite_mux_intf #(
  parameter int unsigned AxiAddrWidth  = 32'd0,
  parameter int unsigned AxiDataWidth  = 32'd0,
  parameter int unsigned NoSlvPorts    = 32'd0,

  parameter int unsigned MaxTrans      = 32'd0,

  parameter bit          FallThrough   = 1'b0,

  parameter bit          SpillAw       = 1'b1,
  parameter bit          SpillW        = 1'b0,
  parameter bit          SpillB        = 1'b0,

  parameter bit          SpillAr       = 1'b1,
  parameter bit          SpillR        = 1'b0
) (
  input  logic   clk_i,
  input  logic   rst_ni,
  input  logic   test_i,
  AXI_BUS.Slave  slv [NoSlvPorts-1:0],
  AXI_BUS.Master mst
);

  typedef logic [AxiAddrWidth-1:0]   addr_t;
  typedef logic [AxiDataWidth-1:0]   data_t;
  typedef logic [AxiDataWidth/8-1:0] strb_t;

  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
  `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t     [NoSlvPorts-1:0] slv_reqs;
  resp_t    [NoSlvPorts-1:0] slv_resps;
  req_t                      mst_req;
  resp_t                     mst_resp;

  for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports
    `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
    `AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
  end

  `AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req)
  `AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst)

  axi_lite_mux #(
    .aw_chan_t     ( aw_chan_t     ),
    .w_chan_t      (  w_chan_t     ),
    .b_chan_t      (  b_chan_t     ),
    .ar_chan_t     ( ar_chan_t     ),
    .r_chan_t      (  r_chan_t     ),
    .NoSlvPorts    ( NoSlvPorts    ),
    .MaxTrans      ( MaxTrans      ),
    .FallThrough   ( FallThrough   ),
    .SpillAw       ( SpillAw       ),
    .SpillW        ( SpillW        ),
    .SpillB        ( SpillB        ),
    .SpillAr       ( SpillAr       ),
    .SpillR        ( SpillR        )
  ) i_axi_mux (
    .clk_i,
    .rst_ni,
    .test_i,
    .slv_reqs_i  ( slv_reqs  ),
    .slv_resps_o ( slv_resps ),
    .mst_req_o   ( mst_req   ),
    .mst_resp_i  ( mst_resp  )
  );


  `ifndef VERILATOR
    initial begin: p_assertions
      AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parameter has to be > 0!");
      DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parameter has to be > 0!");
    end
  `endif

endmodule
module axi_lite_mux_intf #(
  parameter int unsigned AxiAddrWidth  = 32'd0,
  parameter int unsigned AxiDataWidth  = 32'd0,
  parameter int unsigned NoSlvPorts    = 32'd0,

  parameter int unsigned MaxTrans      = 32'd0,

  parameter bit          FallThrough   = 1'b0,

  parameter bit          SpillAw       = 1'b1,
  parameter bit          SpillW        = 1'b0,
  parameter bit          SpillB        = 1'b0,

  parameter bit          SpillAr       = 1'b1,
  parameter bit          SpillR        = 1'b0
) (
  input  logic   clk_i,
  input  logic   rst_ni,
  input  logic   test_i,
  AXI_BUS.Slave  slv [NoSlvPorts-1:0],
  AXI_BUS.Master mst
);


  typedef logic [AxiAddrWidth-1:0]   addr_t;
  typedef logic [AxiDataWidth-1:0]   data_t;
  typedef logic [AxiDataWidth/8-1:0] strb_t;

  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
  `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t     [NoSlvPorts-1:0] slv_reqs;
  resp_t    [NoSlvPorts-1:0] slv_resps;
  req_t                      mst_req;
  resp_t                     mst_resp;

  for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports
    `AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
    `AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
  end

  `AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req)
  `AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst)

  axi_lite_mux #(
    .aw_chan_t     ( aw_chan_t     ),
    .w_chan_t      (  w_chan_t     ),
    .b_chan_t      (  b_chan_t     ),
    .ar_chan_t     ( ar_chan_t     ),
    .r_chan_t      (  r_chan_t     ),
    .NoSlvPorts    ( NoSlvPorts    ),
    .MaxTrans      ( MaxTrans      ),
    .FallThrough   ( FallThrough   ),
    .SpillAw       ( SpillAw       ),
    .SpillW        ( SpillW        ),
    .SpillB        ( SpillB        ),
    .SpillAr       ( SpillAr       ),
    .SpillR        ( SpillR        )
  ) i_axi_mux (
    .clk_i,
    .rst_ni,
    .test_i,
    .slv_reqs_i  ( slv_reqs  ),
    .slv_resps_o ( slv_resps ),
    .mst_req_o   ( mst_req   ),
    .mst_resp_i  ( mst_resp  )
  );


  `ifndef VERILATOR
    initial begin: p_assertions
      AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parameter has to be > 0!");
      DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parameter has to be > 0!");
    end
  `endif

endmodule