data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:27: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'f1_test\'\nmodule f1_test(in, out, clk, reset);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f2_demultiplexer1_to_4\'\nmodule f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                                       : ... Top module \'f3_test\'\nmodule f3_test(in, out);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f4_test\'\nmodule f4_test;\n       ^~~~~~~\n                                                                                                       : ... Top module \'f5_test\'\nmodule f5_test(in, out);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f6_test\'\nmodule f6_test(in, out);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f7_test\'\nmodule f7_test(in, out, io);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f8_test\'\nmodule f8_test(in1, in2, out1, out2, io1, io2);\n       ^~~~~~~\n                                                                                                       : ... Top module \'f9_test\'\nmodule f9_test(q, d, clk, reset);\n       ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:100: Little bit endian vector: MSB < LSB of bit range: 0:1\ninout [0:1] io2;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:102: Little bit endian vector: MSB < LSB of bit range: 0:1\noutput [0:1] out2;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:104: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] in2;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:86: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 32 or 4 bits.\n                                                                                                    : ... In instance f6_test\nassign out = p;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:74: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'p1\' generates 32 or 4 bits.\n                                                                                                    : ... In instance f5_test\nassign out = +p1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s NEGATE generates 32 or 3 bits.\n                                                                                                    : ... In instance f5_test\nassign out = -p2;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:76: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 4 bits.\n                                                                                                    : ... In instance f5_test\nassign out = p1 + p2;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:77: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                                    : ... In instance f5_test\nassign out = p1 - p2;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:60: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4a\' generates 32 or 7 bits.\n                                                                                                    : ... In instance f3_test\nassign out = 74;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:38: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                    : ... In instance f2_demultiplexer1_to_4\n        4\'b11xx: state = 4;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:17: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                                                    : ... In instance f1_test\n    d = a + b + c;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:17: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                                                                    : ... In instance f1_test\n    d = a + b + c;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:17: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                                                    : ... In instance f1_test\n    d = a + b + c;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parse2synthtrans.v:19: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'b\' generates 4 bits.\n                                                                                                    : ... In instance f1_test\n    if(b)\n    ^~\n%Error: Exiting due to 15 warning(s)\n'
module f4_test;
endmodule
module f4_test;

endmodule