data/full_repos/permissive/528147991/scr/sign_ext_16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528147991/scr/sign_ext_16.v:10: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                         : ... In instance sign_ext_16\n out32 <= $signed(in16);\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sign_ext_16(in16, out32);

	input [15:0] in16;
	
	output reg [31:0] out32;
	
	always @(in16)
	begin
	
	out32 <= $signed(in16);
	
	end
endmodule
module sign_ext_16(in16, out32);


	input [15:0] in16;
	
	output reg [31:0] out32;
	
	always @(in16)
	begin
	
	out32 <= $signed(in16);
	
	end
endmodule