data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v
1: b'%Error: data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v:26: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("MIPS_wave.vcd");         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v:27: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, tb_MIPS_Pipeline);     \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425175279/MIPS_Pipeline/tb_MIPS_Pipeline.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_MIPS_Pipeline();

reg clk,rst_n;
reg [31:0] cnt;

initial
begin            
    $dumpfile("MIPS_wave.vcd");
    $dumpvars(0, tb_MIPS_Pipeline);
end

initial begin
    clk <= 1'b0;
    rst_n <= 1'b0;
    cnt <= 32'b0;

    #10
    clk <= 1'b1;

    #10
    clk <= 1'b0;
    rst_n <= 1'b1;

    forever begin
        #10 clk <= ~clk;
    end

end

always @(negedge clk) begin
    cnt <= cnt + 1'b1;
    if (cnt >= 25) begin
        $stop;
    end
end


MIPS_Pipeline u_MIPS_Pipeline(
    .clk(clk),
    .rst_n(rst_n)
);

endmodule
module tb_MIPS_Pipeline();


reg clk,rst_n;
reg [31:0] cnt;

initial
begin            
    $dumpfile("MIPS_wave.vcd");
    $dumpvars(0, tb_MIPS_Pipeline);
end

initial begin
    clk <= 1'b0;
    rst_n <= 1'b0;
    cnt <= 32'b0;

    #10
    clk <= 1'b1;

    #10
    clk <= 1'b0;
    rst_n <= 1'b1;

    forever begin
        #10 clk <= ~clk;
    end

end

always @(negedge clk) begin
    cnt <= cnt + 1'b1;
    if (cnt >= 25) begin
        $stop;
    end
end


MIPS_Pipeline u_MIPS_Pipeline(
    .clk(clk),
    .rst_n(rst_n)
);

endmodule