data/full_repos/permissive/501138203/verilog/rtl/BR128.v
1: b'%Error: data/full_repos/permissive/501138203/verilog/rtl/BR128.v:5: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module BR128 
(
  input wire RESET,
  input wire [127:0] C,
  output wire OUT
);
  supply1 VDD;
  supply0 VSS;


  
endmodule
module BR128 
(
  input wire RESET,
  input wire [127:0] C,
  output wire OUT
);

  supply1 VDD;
  supply0 VSS;


  
endmodule