data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:48: Cannot find file containing module: 'bw_u1_soff_4x'\nbw_u1_soff_4x I257 (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x.sv\n             bw_u1_soff_4x\n             bw_u1_soff_4x.v\n             bw_u1_soff_4x.sv\n             obj_dir/bw_u1_soff_4x\n             obj_dir/bw_u1_soff_4x.v\n             obj_dir/bw_u1_soff_4x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:55: Cannot find file containing module: 'bw_u1_soffr_4x'\nbw_u1_soffr_4x I260 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:63: Cannot find file containing module: 'bw_u1_soffr_4x'\nbw_u1_soffr_4x I263 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:71: Cannot find file containing module: 'bw_u1_inv_4x'\nbw_u1_inv_4x I268 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:74: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I269 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:78: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I270 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:82: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I271 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:86: Cannot find file containing module: 'bw_io_ddr_pad_txrx_zctl'\nbw_io_ddr_pad_txrx_zctl I304 (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_dnrcn.v:96: Cannot find file containing module: 'bw_io_ddr_rptr_vddcom'\nbw_io_ddr_rptr_vddcom I319 (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module bw_io_impctl_ddr_dnrcn(si ,vdd18 ,cbd ,so ,pad ,sclk ,oe ,above ,
     clk ,se ,global_reset_n );
input [8:1]	cbd ;
output		so ;
output		pad ;
output		above ;
input		si ;
input		vdd18 ;
input		sclk ;
input		oe ;
input		clk ;
input		se ;
input		global_reset_n ;
supply0		vss ;
 
wire		net093 ;
wire		sclk1 ;
wire		sclk2 ;
wire		scan1 ;
wire		net051 ;
wire		net056 ;
wire		net059 ;
wire		vf ;
wire		net062 ;
wire		abvref ;
 
 
bw_u1_soff_4x I257 (
     .q               (sclk1 ),
     .so              (net093 ),
     .ck              (clk ),
     .d               (sclk ),
     .se              (se ),
     .sd              (si ) );
bw_u1_soffr_4x I260 (
     .q               (sclk2 ),
     .so              (scan1 ),
     .ck              (clk ),
     .d               (sclk1 ),
     .se              (se ),
     .sd              (net093 ),
     .r_l             (global_reset_n ) );
bw_u1_soffr_4x I263 (
     .q               (above ),
     .so              (so ),
     .ck              (clk ),
     .d               (net062 ),
     .se              (se ),
     .sd              (scan1 ),
     .r_l             (global_reset_n ) );
bw_u1_inv_4x I268 (
     .z               (net051 ),
     .a               (sclk2 ) );
bw_u1_nand2_4x I269 (
     .z               (net062 ),
     .a               (net056 ),
     .b               (net059 ) );
bw_u1_nand2_4x I270 (
     .z               (net059 ),
     .a               (net051 ),
     .b               (above ) );
bw_u1_nand2_4x I271 (
     .z               (net056 ),
     .a               (abvref ),
     .b               (sclk2 ) );
bw_io_ddr_pad_txrx_zctl I304 (
     .vrefcode        ({{4 {vf }} ,vss ,vss ,vss ,vss } ),
     .cbu             ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
     .cbd             ({cbd } ),
     .out             (abvref ),
     .pad             (pad ),
     .vdd_h           (vdd18 ),
     .data            (vss ),
     .oe              (oe ),
     .odt_enable      (vss ) );
bw_io_ddr_rptr_vddcom I319 (
     .vdd18           (vdd18 ),
     .vdd_com         (vf ) );
endmodule
module bw_io_impctl_ddr_dnrcn(si ,vdd18 ,cbd ,so ,pad ,sclk ,oe ,above ,
     clk ,se ,global_reset_n );

input [8:1]	cbd ;
output		so ;
output		pad ;
output		above ;
input		si ;
input		vdd18 ;
input		sclk ;
input		oe ;
input		clk ;
input		se ;
input		global_reset_n ;
supply0		vss ;
 
wire		net093 ;
wire		sclk1 ;
wire		sclk2 ;
wire		scan1 ;
wire		net051 ;
wire		net056 ;
wire		net059 ;
wire		vf ;
wire		net062 ;
wire		abvref ;
 
 
bw_u1_soff_4x I257 (
     .q               (sclk1 ),
     .so              (net093 ),
     .ck              (clk ),
     .d               (sclk ),
     .se              (se ),
     .sd              (si ) );
bw_u1_soffr_4x I260 (
     .q               (sclk2 ),
     .so              (scan1 ),
     .ck              (clk ),
     .d               (sclk1 ),
     .se              (se ),
     .sd              (net093 ),
     .r_l             (global_reset_n ) );
bw_u1_soffr_4x I263 (
     .q               (above ),
     .so              (so ),
     .ck              (clk ),
     .d               (net062 ),
     .se              (se ),
     .sd              (scan1 ),
     .r_l             (global_reset_n ) );
bw_u1_inv_4x I268 (
     .z               (net051 ),
     .a               (sclk2 ) );
bw_u1_nand2_4x I269 (
     .z               (net062 ),
     .a               (net056 ),
     .b               (net059 ) );
bw_u1_nand2_4x I270 (
     .z               (net059 ),
     .a               (net051 ),
     .b               (above ) );
bw_u1_nand2_4x I271 (
     .z               (net056 ),
     .a               (abvref ),
     .b               (sclk2 ) );
bw_io_ddr_pad_txrx_zctl I304 (
     .vrefcode        ({{4 {vf }} ,vss ,vss ,vss ,vss } ),
     .cbu             ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
     .cbd             ({cbd } ),
     .out             (abvref ),
     .pad             (pad ),
     .vdd_h           (vdd18 ),
     .data            (vss ),
     .oe              (oe ),
     .odt_enable      (vss ) );
bw_io_ddr_rptr_vddcom I319 (
     .vdd18           (vdd18 ),
     .vdd_com         (vf ) );
endmodule