data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:69: Define or directive not defined: \'`ALU_NOTHING\'\n  alu_func<=`ALU_NOTHING;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  alu_func<=`ALU_NOTHING;\n                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:70: Define or directive not defined: \'`SHIFT_NOTHING\'\n  shift_func<=`SHIFT_NOTHING;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  shift_func<=`SHIFT_NOTHING;\n                            ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:71: Define or directive not defined: \'`MULT_NOTHING\'\n  mult_func<=`MULT_NOTHING;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  mult_func<=`MULT_NOTHING;\n                          ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:72: Define or directive not defined: \'`BRANCH_NO\'\n  branch_func<=`BRANCH_NO;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  branch_func<=`BRANCH_NO;\n                         ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:73: Define or directive not defined: \'`A_FROM_REG_SOURCE\'\n  a_source_out<=`A_FROM_REG_SOURCE;\n                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_source_out<=`A_FROM_REG_SOURCE;\n                                  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:74: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n  b_source_out<=`B_FROM_REG_TARGET;\n                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:74: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  b_source_out<=`B_FROM_REG_TARGET;\n                                  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:75: Define or directive not defined: \'`C_FROM_ALU\'\n  c_source_out<=`C_FROM_ALU; \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_source_out<=`C_FROM_ALU; \n                           ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:76: Define or directive not defined: \'`FROM_INC4\'\n  pc_source_out<=`FROM_INC4;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pc_source_out<=`FROM_INC4;\n                           ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:77: Define or directive not defined: \'`MEM_FETCH\'\n  mem_source_out<=`MEM_FETCH;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  mem_source_out<=`MEM_FETCH;\n                            ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:95: Define or directive not defined: \'`SHIFT_LEFT_UNSIGNED\'\n        shift_func<=`SHIFT_LEFT_UNSIGNED;\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        shift_func<=`SHIFT_LEFT_UNSIGNED;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:96: Define or directive not defined: \'`A_FROM_IMM10_6\'\n        a_source_out<=`A_FROM_IMM10_6; \n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        a_source_out<=`A_FROM_IMM10_6; \n                                     ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:97: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n        b_source_out<=`B_FROM_REG_TARGET;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        b_source_out<=`B_FROM_REG_TARGET;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:106: Define or directive not defined: \'`SHIFT_RIGHT_UNSIGNED\'\n        shift_func<=`SHIFT_RIGHT_UNSIGNED;\n                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        shift_func<=`SHIFT_RIGHT_UNSIGNED;\n                                         ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:107: Define or directive not defined: \'`A_FROM_IMM10_6\'\n        a_source_out<=`A_FROM_IMM10_6; \n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        a_source_out<=`A_FROM_IMM10_6; \n                                     ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:108: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n        b_source_out<=`B_FROM_REG_TARGET;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        b_source_out<=`B_FROM_REG_TARGET;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:115: Define or directive not defined: \'`SHIFT_RIGHT_SIGNED\'\n        shift_func<=`SHIFT_RIGHT_SIGNED;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:115: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        shift_func<=`SHIFT_RIGHT_SIGNED;\n                                       ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:116: Define or directive not defined: \'`A_FROM_IMM10_6\'\n        a_source_out<=`A_FROM_IMM10_6; \n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        a_source_out<=`A_FROM_IMM10_6; \n                                     ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:117: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n        b_source_out<=`B_FROM_REG_TARGET;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        b_source_out<=`B_FROM_REG_TARGET;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:124: Define or directive not defined: \'`SHIFT_LEFT_UNSIGNED\'\n        shift_func<=`SHIFT_LEFT_UNSIGNED;\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        shift_func<=`SHIFT_LEFT_UNSIGNED;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:125: Define or directive not defined: \'`A_FROM_REG_SOURCE\'\n        a_source_out<=`A_FROM_REG_SOURCE;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:125: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        a_source_out<=`A_FROM_REG_SOURCE;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:126: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n        b_source_out<=`B_FROM_REG_TARGET;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        b_source_out<=`B_FROM_REG_TARGET;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:136: Define or directive not defined: \'`SHIFT_RIGHT_UNSIGNED\'\n        shift_func<=`SHIFT_RIGHT_UNSIGNED;\n                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:136: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        shift_func<=`SHIFT_RIGHT_UNSIGNED;\n                                         ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:137: Define or directive not defined: \'`A_FROM_REG_SOURCE\'\n        a_source_out<=`A_FROM_REG_SOURCE;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:137: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        a_source_out<=`A_FROM_REG_SOURCE;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:138: Define or directive not defined: \'`B_FROM_REG_TARGET\'\n        b_source_out<=`B_FROM_REG_TARGET;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:138: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        b_source_out<=`B_FROM_REG_TARGET;\n                                        ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Control.v:146: Define or directive not defined: \'`SHIFT_RIGHT_SIGNED\'\n        shift_func<=`SHIFT_RIGHT_SIGNED;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Control 
( 
	opcode,
	rs_index,
	rt_index,
	rd_index,
	imm_out,
	alu_func,
	shift_func,
	mult_func,
	branch_func,
	a_source_out,
	b_source_out,
	c_source_out,
	pc_source_out,
	mem_source_out
);

	input 	[31:0]	opcode;
	output	[4:0]	rs_index;
	output	[4:0]	rt_index;
	output	[4:0]	rd_index;
	output	[15:0]	imm_out;
	output	[3:0]	alu_func;
	output	[1:0]	shift_func;
	output	[3:0]	mult_func;
	output	[2:0]	branch_func;
	output	[1:0]	a_source_out;
	output	[1:0]	b_source_out;
	output	[2:0]	c_source_out;
	output	[1:0]	pc_source_out;
	output	[3:0]	mem_source_out;


	reg	[4:0]	rs_index;
	reg	[4:0]	rt_index;
	reg	[4:0]	rd_index;
	reg	[3:0]	alu_func;
	reg	[1:0]	shift_func;
	reg	[3:0]	mult_func;
	reg	[2:0]	branch_func;
	reg	[1:0]	a_source_out;
	reg	[1:0]	b_source_out;
	reg	[2:0]	c_source_out;
	reg	[1:0]	pc_source_out;
	reg	[3:0]	mem_source_out;

	
	wire	[5:0]	op,func;
	wire	[4:0]	r1,r2,r3,sham;
	
	
	assign op=opcode[31:26];
	assign func=opcode[5:0];
	assign r1=opcode[25:21];
	assign r2=opcode[20:16];
	assign r3=opcode[15:11];
	assign sham=opcode[10:6];

	assign imm_out=opcode[15:0];
	
	always@(*)
	begin
		rs_index<=r1;
		rt_index<=r2;
		rd_index<=5'b0;
		alu_func<=`ALU_NOTHING;
		shift_func<=`SHIFT_NOTHING;
		mult_func<=`MULT_NOTHING;
		branch_func<=`BRANCH_NO;
		a_source_out<=`A_FROM_REG_SOURCE;
		b_source_out<=`B_FROM_REG_TARGET;
		c_source_out<=`C_FROM_ALU;
		pc_source_out<=`FROM_INC4;
		mem_source_out<=`MEM_FETCH;

		case(opcode[31:29])
		3'b000:
			case(opcode[28:26])
			3'b000:
				begin
					rs_index<=r1;
					rt_index<=r2;
					case(func[5:3])
					3'b000:
						case(func[2:0])
						3'b000:
							begin
								if(r2==0 && r3==0)
									$display("NOP");
								else
									$display("SLL");
								shift_func<=`SHIFT_LEFT_UNSIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b001:
							;
						3'b010:
							begin
								$display("SLR");
								shift_func<=`SHIFT_RIGHT_UNSIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b011:
							begin
								$display("SRA");
								shift_func<=`SHIFT_RIGHT_SIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b100:
							begin
								$display("SLLV");
								shift_func<=`SHIFT_LEFT_UNSIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b101:
							;
						3'b110:
							begin
								$display("SRLV");
								shift_func<=`SHIFT_RIGHT_UNSIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b111:
							begin
								$display("SRAV");
								shift_func<=`SHIFT_RIGHT_SIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						endcase
					3'b001:
						case(func[2:0])
						3'b000:
							begin
								$display("JR");
								rs_index<=r1;
								rt_index<=0;
								rd_index<=0;
								branch_func<=`BRANCH_YES;
								pc_source_out<=`FROM_LBRANCH;
								alu_func<=`ALU_OR;
							end
						3'b001:
							begin
								$display("JALR");
								rs_index<=r1;
								rt_index<=0;
								rd_index<=r3;
								branch_func<=`BRANCH_YES;
								pc_source_out<=`FROM_LBRANCH;
								c_source_out<=`C_FROM_PC_PLUS4;
								alu_func<=`ALU_OR;
							end
						3'b010:
							;
						3'b011:
							;
						3'b100:
						begin
							$display("SYSCALL");
							rs_index<=63;
							rt_index<=0;
							rd_index<=46;
							branch_func<=`BRANCH_YES;
							pc_source_out<=`FROM_LBRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
							alu_func<=`ALU_OR;
						end
						3'b101:
						begin
							$display("BREAK");
							rs_index<=63;
							rt_index<=0;
							rd_index<=46;
							branch_func<=`BRANCH_YES;
							pc_source_out<=`FROM_LBRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
							alu_func<=`ALU_OR;
						end
						3'b110:
							;
						3'b111:
							$display("SYNC");
						endcase
					3'b010:
						case(func[2:0])
						3'b000:
						begin
							$display("MFHI");
							mult_func<=`MULT_READ_HI;
							rd_index<=r3;
						end
						3'b001:
						begin
							$display("MTHI");
							mult_func<=`MULT_WRITE_HI;
						end
						3'b010:
						begin
							$display("MFLO");
							mult_func<=`MULT_READ_LO;
							rd_index<=r3;
						end
						3'b011:
						begin
							$display("MTLO");
							mult_func<=`MULT_WRITE_LO;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b011:
						case(func[2:0])
						3'b000:
						begin
							$display("MULT");
							mult_func<=`MULT_SIGNED_MULT;
						end
						3'b001:
						begin
							$display("MULTU");
							mult_func<=`MULT_MULT;
						end
						3'b010:
						begin
							$display("DIV");
							mult_func<=`MULT_SIGNED_DIVIDE;
						end
						3'b011:
						begin
							$display("DIVU");
							mult_func<=`MULT_DIVIDE;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b100:
					begin
						rd_index<=r3;
						case(func[2:0])
						3'b000:
						begin
							$display("ADD");
							alu_func<=`ALU_ADD;
						end
						3'b001:
						begin
							$display("ADDU");
							alu_func<=`ALU_ADD;
						end
						3'b010:
						begin
							$display("SUB");
							alu_func<=`ALU_SUBTRACT;
						end
						3'b011:
						begin
							$display("SUBU");
							alu_func<=`ALU_SUBTRACT;
						end
						3'b100:
						begin
							$display("AND");
							alu_func<=`ALU_AND;
						end
						3'b101:
						begin
							$display("OR");
							alu_func<=`ALU_OR;
						end
						3'b110:
						begin
							$display("XOR");
							alu_func<=`ALU_XOR;
						end
						3'b111:
						begin
							$display("NOR");
							alu_func<=`ALU_NOR;
						end
						endcase
					end
					3'b101:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
						begin
							$display("SLT");
							rd_index<=r3;
							alu_func<=`ALU_LESS_THAN_SIGNED;
						end
						3'b011:
						begin
							$display("SLTU");
							rd_index<=r3;
							alu_func<=`ALU_LESS_THAN;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b110:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b111:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					endcase
				end
			3'b001:
				begin
					case(opcode[20:19])
					2'b00:
						case(opcode[18:16])
						3'b000:
						begin	
							$display("BLTZ");
							rs_index<=r1;
							rt_index<=0;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_LTZ;
							pc_source_out<=`FROM_BRANCH;
						end
						3'b001:
						begin	
							$display("BGEZ");
							rs_index<=r1;
							rt_index<=0;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_GEZ;
							pc_source_out<=`FROM_BRANCH;
						end
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b01:
						case(opcode[18:16])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b10:
						case(opcode[18:16])
						3'b000:
						begin	
							$display("BLTZAL");
							rs_index<=r1;
							rt_index<=0;
							rd_index<=31;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_LTZ;
							pc_source_out<=`FROM_BRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
						end
						3'b001:
						begin	
							$display("BGEZAL");
							rs_index<=r1;
							rt_index<=0;
							rd_index<=31;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_GEZ;
							pc_source_out<=`FROM_BRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
						end
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b11:
						case(opcode[18:16])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					endcase
				end
			3'b010:
			begin
				$display("J");
				branch_func<=`BRANCH_YES;
				pc_source_out<=`FROM_OPCODE25_0;
			end
			3'b011:
			begin
				$display("JAL");
				rd_index<=31;
				c_source_out<=`C_FROM_PC_PLUS4;
				branch_func<=`BRANCH_YES;
				pc_source_out<=`FROM_OPCODE25_0;
			end
			3'b100:
			begin
				$display("BEQ");
				rs_index<=r1;
				rt_index<=r2;
				alu_func<=`ALU_XOR;
				branch_func<=`BRANCH_EQ;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b101:
			begin
				$display("BNE");
				rs_index<=r1;
				rt_index<=r2;
				alu_func<=`ALU_XOR;
				branch_func<=`BRANCH_NE;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b110:
			begin
				$display("BLEZ");
				rs_index<=r1;
				rt_index<=0;
				alu_func<=`ALU_OR;
				branch_func<=`BRANCH_LEZ;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b111:
			begin
				$display("BGTZ");
				rs_index<=r1;
				rt_index<=0;
				alu_func<=`ALU_OR;
				branch_func<=`BRANCH_GTZ;
				pc_source_out<=`FROM_BRANCH;
			end
			endcase
		3'b001:
			case(opcode[28:26])
			3'b000:
			begin
				$display("ADDI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
			end
			3'b001:
			begin
				$display("ADDIU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
			end
			3'b010:
			begin
				$display("SLTI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_LESS_THAN_SIGNED;
			end
			3'b011:
			begin
				$display("SLTIU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_LESS_THAN;
			end
			3'b100:
			begin
				$display("ANDI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_AND;
			end
			3'b101:
			begin
				$display("ORI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_OR;
			end
			3'b110:
			begin
				$display("XORI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_XOR;
			end
			3'b111:
			begin
				$display("LUI");
				rd_index<=r2;
				c_source_out<=`C_FROM_IMM_SHIFT16;
			end
			endcase
		3'b010:
			case(opcode[28:26])
			3'b000:
			begin
				case(opcode[25:21])
				5'b00000:
				begin
					$display("MFC0");
					rs_index<={1'b1,r3};
					rt_index<=6'b0;
					rd_index<=r2;
					alu_func<=`ALU_OR;
				end
				5'b00100:
				begin
					$display("MTC0");
					rs_index<=r2;
					rt_index<=6'b0;
					rd_index<={1'b1,r3};
					alu_func<=`ALU_OR;
				end
				default:
					;
				endcase
			end
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b011:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b100:
			case(opcode[28:26])
			3'b000:
			begin
				$display("LB");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ8S;
			end
			3'b001:
			begin
				$display("LH");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ16S;
			end
			3'b010:
			begin
				$display("LWL");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b011:
			begin
				$display("LW");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b100:
			begin
				$display("LBU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ8;
			end
			3'b101:
			begin
				$display("LHU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ16;
			end
			3'b110:
			begin
				$display("LWR");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b111:
				;
			endcase
		3'b101:
			case(opcode[28:26])
			3'b000:
			begin
				$display("SB");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE8;
			end
			3'b001:
			begin
				$display("SH");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE16;
			end
			3'b010:
			begin
				$display("SWL");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE32;
			end
			3'b011:
			begin
				$display("SW");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE32;
			end
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b110:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b111:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		endcase
	end
endmodule
module Control 
( 
	opcode,
	rs_index,
	rt_index,
	rd_index,
	imm_out,
	alu_func,
	shift_func,
	mult_func,
	branch_func,
	a_source_out,
	b_source_out,
	c_source_out,
	pc_source_out,
	mem_source_out
);


	input 	[31:0]	opcode;
	output	[4:0]	rs_index;
	output	[4:0]	rt_index;
	output	[4:0]	rd_index;
	output	[15:0]	imm_out;
	output	[3:0]	alu_func;
	output	[1:0]	shift_func;
	output	[3:0]	mult_func;
	output	[2:0]	branch_func;
	output	[1:0]	a_source_out;
	output	[1:0]	b_source_out;
	output	[2:0]	c_source_out;
	output	[1:0]	pc_source_out;
	output	[3:0]	mem_source_out;


	reg	[4:0]	rs_index;
	reg	[4:0]	rt_index;
	reg	[4:0]	rd_index;
	reg	[3:0]	alu_func;
	reg	[1:0]	shift_func;
	reg	[3:0]	mult_func;
	reg	[2:0]	branch_func;
	reg	[1:0]	a_source_out;
	reg	[1:0]	b_source_out;
	reg	[2:0]	c_source_out;
	reg	[1:0]	pc_source_out;
	reg	[3:0]	mem_source_out;

	
	wire	[5:0]	op,func;
	wire	[4:0]	r1,r2,r3,sham;
	
	
	assign op=opcode[31:26];
	assign func=opcode[5:0];
	assign r1=opcode[25:21];
	assign r2=opcode[20:16];
	assign r3=opcode[15:11];
	assign sham=opcode[10:6];

	assign imm_out=opcode[15:0];
	
	always@(*)
	begin
		rs_index<=r1;
		rt_index<=r2;
		rd_index<=5'b0;
		alu_func<=`ALU_NOTHING;
		shift_func<=`SHIFT_NOTHING;
		mult_func<=`MULT_NOTHING;
		branch_func<=`BRANCH_NO;
		a_source_out<=`A_FROM_REG_SOURCE;
		b_source_out<=`B_FROM_REG_TARGET;
		c_source_out<=`C_FROM_ALU;
		pc_source_out<=`FROM_INC4;
		mem_source_out<=`MEM_FETCH;

		case(opcode[31:29])
		3'b000:
			case(opcode[28:26])
			3'b000:
				begin
					rs_index<=r1;
					rt_index<=r2;
					case(func[5:3])
					3'b000:
						case(func[2:0])
						3'b000:
							begin
								if(r2==0 && r3==0)
									$display("NOP");
								else
									$display("SLL");
								shift_func<=`SHIFT_LEFT_UNSIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b001:
							;
						3'b010:
							begin
								$display("SLR");
								shift_func<=`SHIFT_RIGHT_UNSIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b011:
							begin
								$display("SRA");
								shift_func<=`SHIFT_RIGHT_SIGNED;
								a_source_out<=`A_FROM_IMM10_6;
								b_source_out<=`B_FROM_REG_TARGET;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b100:
							begin
								$display("SLLV");
								shift_func<=`SHIFT_LEFT_UNSIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b101:
							;
						3'b110:
							begin
								$display("SRLV");
								shift_func<=`SHIFT_RIGHT_UNSIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						3'b111:
							begin
								$display("SRAV");
								shift_func<=`SHIFT_RIGHT_SIGNED;
								a_source_out<=`A_FROM_REG_SOURCE;
								b_source_out<=`B_FROM_REG_TARGET;
								rs_index<=r1;
								rt_index<=r2;
								rd_index<=r3;
							end
						endcase
					3'b001:
						case(func[2:0])
						3'b000:
							begin
								$display("JR");
								rs_index<=r1;
								rt_index<=0;
								rd_index<=0;
								branch_func<=`BRANCH_YES;
								pc_source_out<=`FROM_LBRANCH;
								alu_func<=`ALU_OR;
							end
						3'b001:
							begin
								$display("JALR");
								rs_index<=r1;
								rt_index<=0;
								rd_index<=r3;
								branch_func<=`BRANCH_YES;
								pc_source_out<=`FROM_LBRANCH;
								c_source_out<=`C_FROM_PC_PLUS4;
								alu_func<=`ALU_OR;
							end
						3'b010:
							;
						3'b011:
							;
						3'b100:
						begin
							$display("SYSCALL");
							rs_index<=63;
							rt_index<=0;
							rd_index<=46;
							branch_func<=`BRANCH_YES;
							pc_source_out<=`FROM_LBRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
							alu_func<=`ALU_OR;
						end
						3'b101:
						begin
							$display("BREAK");
							rs_index<=63;
							rt_index<=0;
							rd_index<=46;
							branch_func<=`BRANCH_YES;
							pc_source_out<=`FROM_LBRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
							alu_func<=`ALU_OR;
						end
						3'b110:
							;
						3'b111:
							$display("SYNC");
						endcase
					3'b010:
						case(func[2:0])
						3'b000:
						begin
							$display("MFHI");
							mult_func<=`MULT_READ_HI;
							rd_index<=r3;
						end
						3'b001:
						begin
							$display("MTHI");
							mult_func<=`MULT_WRITE_HI;
						end
						3'b010:
						begin
							$display("MFLO");
							mult_func<=`MULT_READ_LO;
							rd_index<=r3;
						end
						3'b011:
						begin
							$display("MTLO");
							mult_func<=`MULT_WRITE_LO;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b011:
						case(func[2:0])
						3'b000:
						begin
							$display("MULT");
							mult_func<=`MULT_SIGNED_MULT;
						end
						3'b001:
						begin
							$display("MULTU");
							mult_func<=`MULT_MULT;
						end
						3'b010:
						begin
							$display("DIV");
							mult_func<=`MULT_SIGNED_DIVIDE;
						end
						3'b011:
						begin
							$display("DIVU");
							mult_func<=`MULT_DIVIDE;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b100:
					begin
						rd_index<=r3;
						case(func[2:0])
						3'b000:
						begin
							$display("ADD");
							alu_func<=`ALU_ADD;
						end
						3'b001:
						begin
							$display("ADDU");
							alu_func<=`ALU_ADD;
						end
						3'b010:
						begin
							$display("SUB");
							alu_func<=`ALU_SUBTRACT;
						end
						3'b011:
						begin
							$display("SUBU");
							alu_func<=`ALU_SUBTRACT;
						end
						3'b100:
						begin
							$display("AND");
							alu_func<=`ALU_AND;
						end
						3'b101:
						begin
							$display("OR");
							alu_func<=`ALU_OR;
						end
						3'b110:
						begin
							$display("XOR");
							alu_func<=`ALU_XOR;
						end
						3'b111:
						begin
							$display("NOR");
							alu_func<=`ALU_NOR;
						end
						endcase
					end
					3'b101:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
						begin
							$display("SLT");
							rd_index<=r3;
							alu_func<=`ALU_LESS_THAN_SIGNED;
						end
						3'b011:
						begin
							$display("SLTU");
							rd_index<=r3;
							alu_func<=`ALU_LESS_THAN;
						end
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b110:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					3'b111:
						case(func[2:0])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					endcase
				end
			3'b001:
				begin
					case(opcode[20:19])
					2'b00:
						case(opcode[18:16])
						3'b000:
						begin	
							$display("BLTZ");
							rs_index<=r1;
							rt_index<=0;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_LTZ;
							pc_source_out<=`FROM_BRANCH;
						end
						3'b001:
						begin	
							$display("BGEZ");
							rs_index<=r1;
							rt_index<=0;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_GEZ;
							pc_source_out<=`FROM_BRANCH;
						end
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b01:
						case(opcode[18:16])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b10:
						case(opcode[18:16])
						3'b000:
						begin	
							$display("BLTZAL");
							rs_index<=r1;
							rt_index<=0;
							rd_index<=31;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_LTZ;
							pc_source_out<=`FROM_BRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
						end
						3'b001:
						begin	
							$display("BGEZAL");
							rs_index<=r1;
							rt_index<=0;
							rd_index<=31;
							alu_func<=`ALU_OR;
							branch_func<=`BRANCH_GEZ;
							pc_source_out<=`FROM_BRANCH;
							c_source_out<=`C_FROM_PC_PLUS4;
						end
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					2'b11:
						case(opcode[18:16])
						3'b000:
							;
						3'b001:
							;
						3'b010:
							;
						3'b011:
							;
						3'b100:
							;
						3'b101:
							;
						3'b110:
							;
						3'b111:
							;
						endcase
					endcase
				end
			3'b010:
			begin
				$display("J");
				branch_func<=`BRANCH_YES;
				pc_source_out<=`FROM_OPCODE25_0;
			end
			3'b011:
			begin
				$display("JAL");
				rd_index<=31;
				c_source_out<=`C_FROM_PC_PLUS4;
				branch_func<=`BRANCH_YES;
				pc_source_out<=`FROM_OPCODE25_0;
			end
			3'b100:
			begin
				$display("BEQ");
				rs_index<=r1;
				rt_index<=r2;
				alu_func<=`ALU_XOR;
				branch_func<=`BRANCH_EQ;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b101:
			begin
				$display("BNE");
				rs_index<=r1;
				rt_index<=r2;
				alu_func<=`ALU_XOR;
				branch_func<=`BRANCH_NE;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b110:
			begin
				$display("BLEZ");
				rs_index<=r1;
				rt_index<=0;
				alu_func<=`ALU_OR;
				branch_func<=`BRANCH_LEZ;
				pc_source_out<=`FROM_BRANCH;
			end
			3'b111:
			begin
				$display("BGTZ");
				rs_index<=r1;
				rt_index<=0;
				alu_func<=`ALU_OR;
				branch_func<=`BRANCH_GTZ;
				pc_source_out<=`FROM_BRANCH;
			end
			endcase
		3'b001:
			case(opcode[28:26])
			3'b000:
			begin
				$display("ADDI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
			end
			3'b001:
			begin
				$display("ADDIU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
			end
			3'b010:
			begin
				$display("SLTI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_LESS_THAN_SIGNED;
			end
			3'b011:
			begin
				$display("SLTIU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_LESS_THAN;
			end
			3'b100:
			begin
				$display("ANDI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_AND;
			end
			3'b101:
			begin
				$display("ORI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_OR;
			end
			3'b110:
			begin
				$display("XORI");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_IMM;
				alu_func<=`ALU_XOR;
			end
			3'b111:
			begin
				$display("LUI");
				rd_index<=r2;
				c_source_out<=`C_FROM_IMM_SHIFT16;
			end
			endcase
		3'b010:
			case(opcode[28:26])
			3'b000:
			begin
				case(opcode[25:21])
				5'b00000:
				begin
					$display("MFC0");
					rs_index<={1'b1,r3};
					rt_index<=6'b0;
					rd_index<=r2;
					alu_func<=`ALU_OR;
				end
				5'b00100:
				begin
					$display("MTC0");
					rs_index<=r2;
					rt_index<=6'b0;
					rd_index<={1'b1,r3};
					alu_func<=`ALU_OR;
				end
				default:
					;
				endcase
			end
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b011:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b100:
			case(opcode[28:26])
			3'b000:
			begin
				$display("LB");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ8S;
			end
			3'b001:
			begin
				$display("LH");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ16S;
			end
			3'b010:
			begin
				$display("LWL");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b011:
			begin
				$display("LW");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b100:
			begin
				$display("LBU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ8;
			end
			3'b101:
			begin
				$display("LHU");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ16;
			end
			3'b110:
			begin
				$display("LWR");
				rs_index<=r1;
				rd_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				c_source_out<=`C_FROM_MEMORY;
				mem_source_out<=`MEM_READ32;
			end
			3'b111:
				;
			endcase
		3'b101:
			case(opcode[28:26])
			3'b000:
			begin
				$display("SB");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE8;
			end
			3'b001:
			begin
				$display("SH");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE16;
			end
			3'b010:
			begin
				$display("SWL");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE32;
			end
			3'b011:
			begin
				$display("SW");
				rs_index<=r1;
				rt_index<=r2;
				b_source_out<=`B_FROM_SIGNED_IMM;
				alu_func<=`ALU_ADD;
				mem_source_out<=`MEM_WRITE32;
			end
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b110:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		3'b111:
			case(opcode[28:26])
			3'b000:
				;
			3'b001:
				;
			3'b010:
				;
			3'b011:
				;
			3'b100:
				;
			3'b101:
				;
			3'b110:
				;
			3'b111:
				;
			endcase
		endcase
	end
endmodule