data/full_repos/permissive/420117502/Basic/1_Half_Adder/Half_Adder.v
data/verilator_xmls/da6254de-46d6-4193-b37a-02bec0235359.xml
module Half_Adder (
    input wire a,
    input wire b,
    output wire sum,
    output wire carry
);
    assign sum = a^b;
    assign carry = a&b;
endmodule
module Half_Adder (
    input wire a,
    input wire b,
    output wire sum,
    output wire carry
);

    assign sum = a^b;
    assign carry = a&b;
endmodule