data/full_repos/permissive/469979476/language/7.v
data/verilator_xmls/72cadc8e-ed90-4708-b36c-26dcf59bc6e3.xml
module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a|b);
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

    
    assign out = ~(a|b);
endmodule