data/full_repos/permissive/509809169/Circuits/Sequential Logic/Latches and Flip Flops/MUX and DFF(!).v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: Flops,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Flops/MUX\n%Error: Cannot find file containing module: DFF(!).v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    always @(posedge clk) begin
        case({E,L})
            2'b00: Q<=Q;
            2'b01: Q<=R;
            2'b10: Q<=w;
            2'b11: Q<=R;
        endcase
    end
endmodule
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);

    always @(posedge clk) begin
        case({E,L})
            2'b00: Q<=Q;
            2'b01: Q<=R;
            2'b10: Q<=w;
            2'b11: Q<=R;
        endcase
    end
endmodule