data/full_repos/permissive/425573648/fpga/seg7_act_val.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:55: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n                                                                           : ... In instance seg7_act_val\n     res_thousands = val_c / 1000;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:56: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n                                                                           : ... In instance seg7_act_val\n     res_hundreds = (val_c / 100) % 10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n                                                                           : ... In instance seg7_act_val\n     res_tens = (val_c / 10) % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:58: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n                                                                           : ... In instance seg7_act_val\n     res_ones = val_c % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:69: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_hundreds = val_p / 100;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:70: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_tens = (val_p / 10) % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:71: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_ones = val_p % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:80: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_hundreds = val_i / 100;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:81: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_tens = (val_i / 10) % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:82: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_ones = val_i % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:91: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_hundreds = val_d / 100;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:92: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_tens = (val_d / 10) % 10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:93: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 12 bits.\n                                                                           : ... In instance seg7_act_val\n     res_ones = val_d % 10;\n              ^\n%Error: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:114: Cannot find file containing module: \'seven_segment\'\nseven_segment thousands(disp_vals, res_thousands, seg7_thousands);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment.v\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/seven_segment.sv\n             seven_segment\n             seven_segment.v\n             seven_segment.sv\n             obj_dir/seven_segment\n             obj_dir/seven_segment.v\n             obj_dir/seven_segment.sv\n%Error: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:115: Cannot find file containing module: \'seven_segment\'\nseven_segment hundreds(disp_vals, res_hundreds, seg7_hundreds);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:116: Cannot find file containing module: \'seven_segment\'\nseven_segment tens(disp_vals, res_tens, seg7_tens);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/seg7_act_val.v:117: Cannot find file containing module: \'seven_segment\'\nseven_segment ones(disp_vals, res_ones, seg7_ones);\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 13 warning(s)\n'
module seg7_act_val (
	input [11:0]val_p,
	input [11:0]val_i,
	input [11:0]val_d,
	input [15:0]val_c,
	input [3:0]ui_select,
	output reg [6:0]k_active,
	output reg [6:0]k_equals,
	output [6:0]seg7_thousands,
	output [6:0]seg7_hundreds,
	output [6:0]seg7_tens,
	output [6:0]seg7_ones
);


reg [3:0]res_thousands;
reg [3:0]res_hundreds;
reg [3:0]res_tens;
reg [3:0]res_ones;


reg disp_vals;

always @(*)
	begin
		case (ui_select)
		
			4'b1000:
				begin

					res_thousands = val_c / 1000;
					res_hundreds = (val_c / 100) % 10;
					res_tens = (val_c / 10) % 10;
					res_ones = val_c % 10;
					k_active = 7'b0110001;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
					
			
			4'b0100:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_p / 100;
					res_tens = (val_p / 10) % 10;
					res_ones = val_p % 10;
					k_active = 7'b0011000;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			4'b0010:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_i / 100;
					res_tens = (val_i / 10) % 10;
					res_ones = val_i % 10;
					k_active = 7'b1111001;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			4'b0001:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_d / 100;
					res_tens = (val_d / 10) % 10;
					res_ones = val_d % 10;
					k_active = 7'b1000010;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			default:
				begin

					res_thousands = 4'd0;
					res_hundreds = 4'd0;
					res_tens = 4'd0;
					res_ones = 4'd0;
					k_active = 7'b1111111;
					k_equals = 7'b1111111;
					disp_vals = 1'b0;
				end
		endcase

	end


seven_segment thousands(disp_vals, res_thousands, seg7_thousands);
seven_segment hundreds(disp_vals, res_hundreds, seg7_hundreds);
seven_segment tens(disp_vals, res_tens, seg7_tens);
seven_segment ones(disp_vals, res_ones, seg7_ones);

endmodule
module seg7_act_val (
	input [11:0]val_p,
	input [11:0]val_i,
	input [11:0]val_d,
	input [15:0]val_c,
	input [3:0]ui_select,
	output reg [6:0]k_active,
	output reg [6:0]k_equals,
	output [6:0]seg7_thousands,
	output [6:0]seg7_hundreds,
	output [6:0]seg7_tens,
	output [6:0]seg7_ones
);



reg [3:0]res_thousands;
reg [3:0]res_hundreds;
reg [3:0]res_tens;
reg [3:0]res_ones;


reg disp_vals;

always @(*)
	begin
		case (ui_select)
		
			4'b1000:
				begin

					res_thousands = val_c / 1000;
					res_hundreds = (val_c / 100) % 10;
					res_tens = (val_c / 10) % 10;
					res_ones = val_c % 10;
					k_active = 7'b0110001;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
					
			
			4'b0100:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_p / 100;
					res_tens = (val_p / 10) % 10;
					res_ones = val_p % 10;
					k_active = 7'b0011000;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			4'b0010:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_i / 100;
					res_tens = (val_i / 10) % 10;
					res_ones = val_i % 10;
					k_active = 7'b1111001;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			4'b0001:
				begin

					res_thousands = 4'd0;
					res_hundreds = val_d / 100;
					res_tens = (val_d / 10) % 10;
					res_ones = val_d % 10;
					k_active = 7'b1000010;
					k_equals = 7'b1110110;
					disp_vals = 1'b1;
				end
			default:
				begin

					res_thousands = 4'd0;
					res_hundreds = 4'd0;
					res_tens = 4'd0;
					res_ones = 4'd0;
					k_active = 7'b1111111;
					k_equals = 7'b1111111;
					disp_vals = 1'b0;
				end
		endcase

	end


seven_segment thousands(disp_vals, res_thousands, seg7_thousands);
seven_segment hundreds(disp_vals, res_hundreds, seg7_hundreds);
seven_segment tens(disp_vals, res_tens, seg7_tens);
seven_segment ones(disp_vals, res_ones, seg7_ones);

endmodule