data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv
1: b'%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:3: Cannot find include file: bli201v32i_tl_defines.vh\n`include "bli201v32i_tl_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh.v\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh.sv\n             bli201v32i_tl_defines.vh\n             bli201v32i_tl_defines.vh.v\n             bli201v32i_tl_defines.vh.sv\n             obj_dir/bli201v32i_tl_defines.vh\n             obj_dir/bli201v32i_tl_defines.vh.v\n             obj_dir/bli201v32i_tl_defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:13: Unsupported: Ignoring delay on this delayed statement.\n    #(CLOCK_PERIOD/2) clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:41: Unsupported: Ignoring delay on this delayed statement.\n      #0;\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:44: syntax error, unexpected \'@\'\n      repeat(2) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:62: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:64: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:66: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:68: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:70: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:72: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:74: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:76: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:78: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:80: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:86: syntax error, unexpected \'@\'\n      @(negedge dut_uart_tx);       \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:88: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:89: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:91: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:93: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:95: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:97: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:99: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:101: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:103: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:105: Unsupported: Ignoring delay on this delayed statement.\n      #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:110: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:125: Define or directive not defined: \'`TL_A_MSG_PUTFULLDATA_OPCODE\'\n      tl_a_opcode = `TL_A_MSG_PUTFULLDATA_OPCODE;    \n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:125: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_opcode = `TL_A_MSG_PUTFULLDATA_OPCODE;    \n                                                ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:126: Define or directive not defined: \'`TL_A_MSG_PUTFULLDATA_PARAM\'\n      tl_a_param = `TL_A_MSG_PUTFULLDATA_PARAM;      \n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_param = `TL_A_MSG_PUTFULLDATA_PARAM;      \n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:136: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:140: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:147: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:155: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:158: Define or directive not defined: \'`TL_D_MSG_ACCESSACKDATA_OPCODE\'\n      if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE) $display("%d [TL PutFullData]: ERROR: response type mismatch!", $time);\n                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:158: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE) $display("%d [TL PutFullData]: ERROR: response type mismatch!", $time);\n                                                        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:175: Define or directive not defined: \'`TL_A_MSG_GET_OPCODE\'\n      tl_a_opcode = `TL_A_MSG_GET_OPCODE;    \n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:175: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_opcode = `TL_A_MSG_GET_OPCODE;    \n                                        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:176: Define or directive not defined: \'`TL_A_MSG_GET_PARAM\'\n      tl_a_param = `TL_A_MSG_GET_PARAM;      \n                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:176: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_param = `TL_A_MSG_GET_PARAM;      \n                                      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:186: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:192: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:198: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:201: Define or directive not defined: \'`TL_D_MSG_ACCESSACK_OPCODE\'\n      if (tl_d_opcode != `TL_D_MSG_ACCESSACK_OPCODE) $display("%d [TL Get]: ERROR: response type mismatch!", $time);\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:201: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (tl_d_opcode != `TL_D_MSG_ACCESSACK_OPCODE) $display("%d [TL Get]: ERROR: response type mismatch!", $time);\n                                                   ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:209: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:265: syntax error, unexpected \'@\'\n    repeat(8) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:269: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:278: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_uart.sv:279: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 25 error(s), 25 warning(s)\n'
module tb_uart();
  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;


  reg [2:0] tl_a_opcode;   initial tl_a_opcode  = 'b0;
  reg [2:0] tl_a_param;    initial tl_a_param   = 'b0;
  reg [3:0] tl_a_size;     initial tl_a_size    = 'b0;
  reg [0:0] tl_a_source;   initial tl_a_source  = 'b0;
  reg [24:0] tl_a_address; initial tl_a_address = 'b0;
  reg [3:0] tl_a_mask;     initial tl_a_mask    = 'b0;
  reg [31:0] tl_a_data;    initial tl_a_data    = 'b0;
  reg tl_a_corrupt;        initial tl_a_corrupt = 'b0;
  reg tl_a_valid;          initial tl_a_valid   = 'b0;
  wire tl_a_ready;
    
  wire [2:0] tl_d_opcode;
  wire [1:0] tl_d_param;
  wire [3:0] tl_d_size;
  wire [0:0] tl_d_source;
  wire [0:0] tl_d_sink;
  wire tl_d_denied;
  wire [31:0] tl_d_data;
  wire tl_d_corrupt;
  wire tl_d_valid;
  reg tl_d_ready;          initial tl_d_ready   = 'b0;


  task reset;
    begin
      #0;
      rst = 0;
      $display("[TEST]\tRESET pulled LOW.");
      repeat(2) @(posedge clk);
      @(negedge clk);
      rst = 1;
      $display("[TEST]\tRESET pulled HIGH.");
    end
  endtask



  reg dut_uart_rx;
  wire dut_uart_tx;
  reg [7:0] dut_uart_tx_char;
  initial dut_uart_rx = 'b1; 
  
  task UART_Transmit;
    input [7:0] char;
    begin
      dut_uart_rx = 'b0;
      #80;
      dut_uart_rx = char[0];
      #80;
      dut_uart_rx = char[1];
      #80;
      dut_uart_rx = char[2];
      #80;
      dut_uart_rx = char[3];
      #80;
      dut_uart_rx = char[4];
      #80;
      dut_uart_rx = char[5];
      #80;
      dut_uart_rx = char[6];
      #80;
      dut_uart_rx = char[7];
      #80;
      dut_uart_rx = 'b1;
      #80;
    end
  endtask
  
  task UART_Receive;
    begin
      @(negedge dut_uart_tx);

      #40;
      #80;
      dut_uart_tx_char[0] = dut_uart_tx;
      #80;
      dut_uart_tx_char[1] = dut_uart_tx;
      #80;
      dut_uart_tx_char[2] = dut_uart_tx;
      #80;
      dut_uart_tx_char[3] = dut_uart_tx;
      #80;
      dut_uart_tx_char[4] = dut_uart_tx;
      #80;
      dut_uart_tx_char[5] = dut_uart_tx;
      #80;
      dut_uart_tx_char[6] = dut_uart_tx;
      #80;
      dut_uart_tx_char[7] = dut_uart_tx;
      #80;
      if (dut_uart_tx !== 'b1) begin
        $display("%t [TEST]\tDUT TX Frame ERROR.", $time);
      end
      ;
      #40;
      $display("%t [TEST]\tReceived DUT TX %d / 0x%h.", $time, dut_uart_tx_char, dut_uart_tx_char);
    end
  endtask
  
  
  task TL_PutFullData;
    input [7:0] size;
    input [0:0] source;
    input [31:0] address;
    input [31:0] mask;
    input [255:0] data;
      
    begin
      integer i;
      tl_a_opcode = `TL_A_MSG_PUTFULLDATA_OPCODE;
      tl_a_param = `TL_A_MSG_PUTFULLDATA_PARAM;
      tl_a_size =  $clog2(size);
      tl_a_source = source;
      tl_a_address = address;
      tl_a_mask = mask;
      tl_a_corrupt = 1'b0;
      tl_a_data = data;
      
      
      tl_a_valid = 'b1;
      #1;
      
      $display("%d [TL PutFullData]: waiting slave device READY...", $time);
      while (tl_a_ready !== 'b1) begin
        @(posedge clk);
      end
      
      for (i=0; i<size/4; i+=1) begin
        tl_a_data = data[31:0];
        data = {32'h0, data[255-32:32]};
        $display("%d [TL PutFullData]: sending PUTFULLDATA <addr: %h, size: %d, data: %h>", $time, tl_a_address, 1<<tl_a_size, tl_a_data);
        @(posedge clk);
      end
      @(posedge clk);
      tl_a_valid = 'b0;
      tl_d_ready = 'b1;
      
      $display("%d [TL PutFullData]: waiting response...", $time);
      while (tl_d_valid !== 'b1) begin
        @(posedge clk);
      end
      
      if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE) $display("%d [TL PutFullData]: ERROR: response type mismatch!", $time);
      if (tl_d_size !== tl_a_size) $display("%d [TL PutFullData]: ERROR: response size mismatch!", $time); 
      if (tl_d_denied !== 'b0) $display("%d [TL PutFullData]: ERROR: response denied!", $time);
      
      $display("%d [TL PutFullData]: get response.", $time);
    end
  endtask
  
  task TL_Get;
    input [2:0] size;
    input [0:0] source;
    input [31:0] address;
    input [31:0] mask;
    output [255:0] data;
    
    begin
      integer i;
      tl_a_opcode = `TL_A_MSG_GET_OPCODE;
      tl_a_param = `TL_A_MSG_GET_PARAM;
      tl_a_size =  $clog2(size);
      tl_a_source = source;
      tl_a_address = address;
      tl_a_mask = mask;
      tl_a_corrupt = 1'b0;
      tl_a_data = 'hCCCCCCCC;
      
      $display("%d [TL Get]: waiting slave device READY...", $time);
      while (tl_a_ready != 'b1) begin
        @(posedge clk);
      end
      tl_a_valid = 'b1;
      
      $display("%d [TL Get]: sending GET <addr: %h, size: %d>", $time, tl_a_address, 1<<tl_a_size);
      tl_a_valid = 'b1;
      @(posedge clk);
      tl_a_valid = 'b0;
      tl_d_ready = 'b1;
      
      $display("%d [TL Get]: waiting response...", $time);
      while (tl_d_valid !== 'b1) begin
        @(posedge clk);
      end
      
      if (tl_d_opcode != `TL_D_MSG_ACCESSACK_OPCODE) $display("%d [TL Get]: ERROR: response type mismatch!", $time);
      if (tl_d_size != tl_a_size) $display("%d [TL Get]: ERROR: response size mismatch!", $time); 
      if (tl_d_denied != 'b0) $display("%d [TL Get]: ERROR: response denied!", $time);
      
      data = 'h0;
      for (i=0; i<size/4; i+=1) begin
        $display("%d [TL Get]: get response %h", $time, tl_d_data);      
        data = data | (tl_d_data << (i*32));
        @(posedge clk);
      end
      $display("%d [TL Get]: get final response %h", $time, data);      
    end
  endtask


  uart #(
  ) DUT (
    .clk(clk),
    .rst(rst),

    .uart_i_itim_tl_a_opcode(tl_a_opcode),
    .uart_i_itim_tl_a_param(tl_a_param),
    .uart_i_itim_tl_a_size(tl_a_size),
    .uart_i_itim_tl_a_source(tl_a_source),
    .uart_i_itim_tl_a_address(tl_a_address),
    .uart_i_itim_tl_a_mask(tl_a_mask),
    .uart_i_itim_tl_a_data(tl_a_data),
    .uart_i_itim_tl_a_corrupt(tl_a_corrupt),
    .uart_i_itim_tl_a_valid(tl_a_valid),
    .uart_o_itim_tl_a_ready(tl_a_ready),
    
    .uart_o_itim_tl_d_opcode(tl_d_opcode),
    .uart_o_itim_tl_d_param(tl_d_param),
    .uart_o_itim_tl_d_size(tl_d_size),
    .uart_o_itim_tl_d_source(tl_d_source),
    .uart_o_itim_tl_d_sink(tl_d_sink),
    .uart_o_itim_tl_d_denied(tl_d_denied),
    .uart_o_itim_tl_d_data(tl_d_data),
    .uart_o_itim_tl_d_corrupt(tl_d_corrupt),
    .uart_o_itim_tl_d_valid(tl_d_valid),
    .uart_i_itim_tl_d_ready(tl_d_ready),


    .uart_i_rx(dut_uart_rx),
    .uart_o_tx(dut_uart_tx),


    .uart_o_tx_busy(),
    .uart_o_rx_busy(),
    .uart_o_rx_overrun_error(),
    .uart_o_rx_frame_error()
  );



  reg [31:0] tl_data_output;

  initial begin
    reset();
    
    repeat(8) @(posedge clk);
    
    tl_d_ready = 'b1;
    
    fork
      begin
        TL_PutFullData('d4, 'h0, 'h0000_0010, 'b0001, 'h0000_0040);
      end
      begin    
        UART_Receive();
      end
    join
    
    repeat(100) @(posedge clk);
    #100;
    $finish();


  end 

endmodule
module tb_uart();

  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;


  reg [2:0] tl_a_opcode;   initial tl_a_opcode  = 'b0;
  reg [2:0] tl_a_param;    initial tl_a_param   = 'b0;
  reg [3:0] tl_a_size;     initial tl_a_size    = 'b0;
  reg [0:0] tl_a_source;   initial tl_a_source  = 'b0;
  reg [24:0] tl_a_address; initial tl_a_address = 'b0;
  reg [3:0] tl_a_mask;     initial tl_a_mask    = 'b0;
  reg [31:0] tl_a_data;    initial tl_a_data    = 'b0;
  reg tl_a_corrupt;        initial tl_a_corrupt = 'b0;
  reg tl_a_valid;          initial tl_a_valid   = 'b0;
  wire tl_a_ready;
    
  wire [2:0] tl_d_opcode;
  wire [1:0] tl_d_param;
  wire [3:0] tl_d_size;
  wire [0:0] tl_d_source;
  wire [0:0] tl_d_sink;
  wire tl_d_denied;
  wire [31:0] tl_d_data;
  wire tl_d_corrupt;
  wire tl_d_valid;
  reg tl_d_ready;          initial tl_d_ready   = 'b0;


  task reset;
    begin
      #0;
      rst = 0;
      $display("[TEST]\tRESET pulled LOW.");
      repeat(2) @(posedge clk);
      @(negedge clk);
      rst = 1;
      $display("[TEST]\tRESET pulled HIGH.");
    end
  endtask



  reg dut_uart_rx;
  wire dut_uart_tx;
  reg [7:0] dut_uart_tx_char;
  initial dut_uart_rx = 'b1; 
  
  task UART_Transmit;
    input [7:0] char;
    begin
      dut_uart_rx = 'b0;
      #80;
      dut_uart_rx = char[0];
      #80;
      dut_uart_rx = char[1];
      #80;
      dut_uart_rx = char[2];
      #80;
      dut_uart_rx = char[3];
      #80;
      dut_uart_rx = char[4];
      #80;
      dut_uart_rx = char[5];
      #80;
      dut_uart_rx = char[6];
      #80;
      dut_uart_rx = char[7];
      #80;
      dut_uart_rx = 'b1;
      #80;
    end
  endtask
  
  task UART_Receive;
    begin
      @(negedge dut_uart_tx);

      #40;
      #80;
      dut_uart_tx_char[0] = dut_uart_tx;
      #80;
      dut_uart_tx_char[1] = dut_uart_tx;
      #80;
      dut_uart_tx_char[2] = dut_uart_tx;
      #80;
      dut_uart_tx_char[3] = dut_uart_tx;
      #80;
      dut_uart_tx_char[4] = dut_uart_tx;
      #80;
      dut_uart_tx_char[5] = dut_uart_tx;
      #80;
      dut_uart_tx_char[6] = dut_uart_tx;
      #80;
      dut_uart_tx_char[7] = dut_uart_tx;
      #80;
      if (dut_uart_tx !== 'b1) begin
        $display("%t [TEST]\tDUT TX Frame ERROR.", $time);
      end
      ;
      #40;
      $display("%t [TEST]\tReceived DUT TX %d / 0x%h.", $time, dut_uart_tx_char, dut_uart_tx_char);
    end
  endtask
  
  
  task TL_PutFullData;
    input [7:0] size;
    input [0:0] source;
    input [31:0] address;
    input [31:0] mask;
    input [255:0] data;
      
    begin
      integer i;
      tl_a_opcode = `TL_A_MSG_PUTFULLDATA_OPCODE;
      tl_a_param = `TL_A_MSG_PUTFULLDATA_PARAM;
      tl_a_size =  $clog2(size);
      tl_a_source = source;
      tl_a_address = address;
      tl_a_mask = mask;
      tl_a_corrupt = 1'b0;
      tl_a_data = data;
      
      
      tl_a_valid = 'b1;
      #1;
      
      $display("%d [TL PutFullData]: waiting slave device READY...", $time);
      while (tl_a_ready !== 'b1) begin
        @(posedge clk);
      end
      
      for (i=0; i<size/4; i+=1) begin
        tl_a_data = data[31:0];
        data = {32'h0, data[255-32:32]};
        $display("%d [TL PutFullData]: sending PUTFULLDATA <addr: %h, size: %d, data: %h>", $time, tl_a_address, 1<<tl_a_size, tl_a_data);
        @(posedge clk);
      end
      @(posedge clk);
      tl_a_valid = 'b0;
      tl_d_ready = 'b1;
      
      $display("%d [TL PutFullData]: waiting response...", $time);
      while (tl_d_valid !== 'b1) begin
        @(posedge clk);
      end
      
      if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE) $display("%d [TL PutFullData]: ERROR: response type mismatch!", $time);
      if (tl_d_size !== tl_a_size) $display("%d [TL PutFullData]: ERROR: response size mismatch!", $time); 
      if (tl_d_denied !== 'b0) $display("%d [TL PutFullData]: ERROR: response denied!", $time);
      
      $display("%d [TL PutFullData]: get response.", $time);
    end
  endtask
  
  task TL_Get;
    input [2:0] size;
    input [0:0] source;
    input [31:0] address;
    input [31:0] mask;
    output [255:0] data;
    
    begin
      integer i;
      tl_a_opcode = `TL_A_MSG_GET_OPCODE;
      tl_a_param = `TL_A_MSG_GET_PARAM;
      tl_a_size =  $clog2(size);
      tl_a_source = source;
      tl_a_address = address;
      tl_a_mask = mask;
      tl_a_corrupt = 1'b0;
      tl_a_data = 'hCCCCCCCC;
      
      $display("%d [TL Get]: waiting slave device READY...", $time);
      while (tl_a_ready != 'b1) begin
        @(posedge clk);
      end
      tl_a_valid = 'b1;
      
      $display("%d [TL Get]: sending GET <addr: %h, size: %d>", $time, tl_a_address, 1<<tl_a_size);
      tl_a_valid = 'b1;
      @(posedge clk);
      tl_a_valid = 'b0;
      tl_d_ready = 'b1;
      
      $display("%d [TL Get]: waiting response...", $time);
      while (tl_d_valid !== 'b1) begin
        @(posedge clk);
      end
      
      if (tl_d_opcode != `TL_D_MSG_ACCESSACK_OPCODE) $display("%d [TL Get]: ERROR: response type mismatch!", $time);
      if (tl_d_size != tl_a_size) $display("%d [TL Get]: ERROR: response size mismatch!", $time); 
      if (tl_d_denied != 'b0) $display("%d [TL Get]: ERROR: response denied!", $time);
      
      data = 'h0;
      for (i=0; i<size/4; i+=1) begin
        $display("%d [TL Get]: get response %h", $time, tl_d_data);      
        data = data | (tl_d_data << (i*32));
        @(posedge clk);
      end
      $display("%d [TL Get]: get final response %h", $time, data);      
    end
  endtask


  uart #(
  ) DUT (
    .clk(clk),
    .rst(rst),

    .uart_i_itim_tl_a_opcode(tl_a_opcode),
    .uart_i_itim_tl_a_param(tl_a_param),
    .uart_i_itim_tl_a_size(tl_a_size),
    .uart_i_itim_tl_a_source(tl_a_source),
    .uart_i_itim_tl_a_address(tl_a_address),
    .uart_i_itim_tl_a_mask(tl_a_mask),
    .uart_i_itim_tl_a_data(tl_a_data),
    .uart_i_itim_tl_a_corrupt(tl_a_corrupt),
    .uart_i_itim_tl_a_valid(tl_a_valid),
    .uart_o_itim_tl_a_ready(tl_a_ready),
    
    .uart_o_itim_tl_d_opcode(tl_d_opcode),
    .uart_o_itim_tl_d_param(tl_d_param),
    .uart_o_itim_tl_d_size(tl_d_size),
    .uart_o_itim_tl_d_source(tl_d_source),
    .uart_o_itim_tl_d_sink(tl_d_sink),
    .uart_o_itim_tl_d_denied(tl_d_denied),
    .uart_o_itim_tl_d_data(tl_d_data),
    .uart_o_itim_tl_d_corrupt(tl_d_corrupt),
    .uart_o_itim_tl_d_valid(tl_d_valid),
    .uart_i_itim_tl_d_ready(tl_d_ready),


    .uart_i_rx(dut_uart_rx),
    .uart_o_tx(dut_uart_tx),


    .uart_o_tx_busy(),
    .uart_o_rx_busy(),
    .uart_o_rx_overrun_error(),
    .uart_o_rx_frame_error()
  );



  reg [31:0] tl_data_output;

  initial begin
    reset();
    
    repeat(8) @(posedge clk);
    
    tl_d_ready = 'b1;
    
    fork
      begin
        TL_PutFullData('d4, 'h0, 'h0000_0010, 'b0001, 'h0000_0040);
      end
      begin    
        UART_Receive();
      end
    join
    
    repeat(100) @(posedge clk);
    #100;
    $finish();


  end 

endmodule