data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/AND_3.v
data/verilator_xmls/ca9e1408-8e25-43ed-861c-bc11a4a4ae6a.xml
module AND_3(out, A, B, C);
	
	input A, B, C;
	output out;
	wire and1_out;
	
	and and1(and1_out, A, B);
	and and2(out, and1_out, C);	

endmodule
module AND_3(out, A, B, C);

	
	input A, B, C;
	output out;
	wire and1_out;
	
	and and1(and1_out, A, B);
	and and2(out, and1_out, C);	

endmodule