data/full_repos/permissive/503973366/SIM/tb_result_writer5.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100    reset_n = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10     reset_n = 1;\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:35: syntax error, unexpected \'@\'\n        #10     @(posedge clk); #3\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10     @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10     @(posedge clk); #3\n                                ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:40: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:40: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:42: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:45: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:48: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:48: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:50: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:53: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:56: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:56: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:58: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:61: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:64: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:64: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:66: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:69: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:72: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:72: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:74: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:77: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:80: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:80: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:82: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:85: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:88: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:88: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:90: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:93: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:96: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:96: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:98: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:101: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:104: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:104: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:106: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:109: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:112: syntax error, unexpected \'@\'\n        @(posedge clk); #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:112: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:114: syntax error, unexpected \'@\'\n        @(posedge clk); \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/tb_result_writer5.v:117: Unsupported: Ignoring delay on this delayed statement.\n        @(posedge clk); #3\n                        ^\n%Error: Exiting due to 21 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_result_writer5();
    reg                             clk, reset_n;
    reg                             done_o;
    reg [`IN_DATA_WIDTH - 1 : 0]    result_o;
    reg [`DATA_WIDTH - 1 : 0]       q_b;

    wire [`ADDR_WIDTH - 1 : 0]      addr_b;
    wire                            ce_b;
    wire                            we_b;
    wire [`DATA_WIDTH - 1 : 0]      d_b;

    always begin
        #5 clk = ~clk;
    end

    initial begin

        reset_n     = 1;
        clk         = 0;
        done_o      = 0;
        result_o    = {(`IN_DATA_WIDTH){1'b0}};
        q_b         = {(`DATA_WIDTH){1'b0}};


        $display("Reset. [%0d]", $time);
        #100    reset_n = 0;
        #10     reset_n = 1;
        #10     @(posedge clk); #3


        $display("test pattern start. [%0d]", $time);
        done_o = 1'b1; result_o = 31;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 179;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 125;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 11;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 1;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 3;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 69;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 101;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 225;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 131;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3
        
        #100
        $display("Simulation Finish,");
        $finish;
    end


    result_writer5
    # (
        .DWIDTH(`DATA_WIDTH),
        .AWIDTH(`ADDR_WIDTH),
        .MEM_SIZE(`MEM_DEPTH)
    ) result_writer5_inst (
        .clk(clk),
        .reset_n(reset_n),

        .calc_done_i(done_o),
        .calc_result_i(result_o),

        .q_b_i(q_b),
        .addr_b_o(addr_b),
        .ce_b_o(ce_b),
        .we_b_o(we_b),
        .d_b_o(d_b)
    );


endmodule
module tb_result_writer5();

    reg                             clk, reset_n;
    reg                             done_o;
    reg [`IN_DATA_WIDTH - 1 : 0]    result_o;
    reg [`DATA_WIDTH - 1 : 0]       q_b;

    wire [`ADDR_WIDTH - 1 : 0]      addr_b;
    wire                            ce_b;
    wire                            we_b;
    wire [`DATA_WIDTH - 1 : 0]      d_b;

    always begin
        #5 clk = ~clk;
    end

    initial begin

        reset_n     = 1;
        clk         = 0;
        done_o      = 0;
        result_o    = {(`IN_DATA_WIDTH){1'b0}};
        q_b         = {(`DATA_WIDTH){1'b0}};


        $display("Reset. [%0d]", $time);
        #100    reset_n = 0;
        #10     reset_n = 1;
        #10     @(posedge clk); #3


        $display("test pattern start. [%0d]", $time);
        done_o = 1'b1; result_o = 31;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 179;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 125;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 11;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 1;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 3;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 69;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 101;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 225;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3

        done_o = 1'b1; result_o = 131;
        @(posedge clk); #3
        done_o = 1'b0; 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); 
        @(posedge clk); #3
        
        #100
        $display("Simulation Finish,");
        $finish;
    end


    result_writer5
    # (
        .DWIDTH(`DATA_WIDTH),
        .AWIDTH(`ADDR_WIDTH),
        .MEM_SIZE(`MEM_DEPTH)
    ) result_writer5_inst (
        .clk(clk),
        .reset_n(reset_n),

        .calc_done_i(done_o),
        .calc_result_i(result_o),

        .q_b_i(q_b),
        .addr_b_o(addr_b),
        .ce_b_o(ce_b),
        .we_b_o(we_b),
        .d_b_o(d_b)
    );


endmodule