data/full_repos/permissive/447976230/fpga/usrp1/megacells/mylpm_addsub_bb.v
data/verilator_xmls/f4f5ed6d-6533-4208-9acc-21f1456705a3.xml
module mylpm_addsub (
	add_sub,
	dataa,
	datab,
	clock,
	result);

	input	  add_sub;
	input	[15:0]  dataa;
	input	[15:0]  datab;
	input	  clock;
	output	[15:0]  result;

endmodule
module mylpm_addsub (
	add_sub,
	dataa,
	datab,
	clock,
	result);


	input	  add_sub;
	input	[15:0]  dataa;
	input	[15:0]  datab;
	input	  clock;
	output	[15:0]  result;

endmodule