data/full_repos/permissive/520452389/source_codes/Execution.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/520452389/source_codes/Execution.v:22: Signal definition not found, creating implicitly: \'zero\'\n                                                                                   : ... Suggested alternative: \'zero_s3\'\n        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);\n                                                                                                              ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:18: Cannot find file containing module: \'ksa_add\'\nksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.v\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.sv\n             ksa_add\n             ksa_add.v\n             ksa_add.sv\n             obj_dir/ksa_add\n             obj_dir/ksa_add.v\n             obj_dir/ksa_add.sv\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:20: Cannot find file containing module: \'ALU\'\nALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);\n^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module forward(input [4:0]source_s2,input [4:0]dest_for_I_s2,input reset,input [4:0]write_reg_s3,input RegWrite_s3,output reg [1:0]fwda,output reg [1:0]fwdb,input [4:0]write_reg_s4,input RegWrite_s4);

always @(write_reg_s3,source_s2,dest_for_I_s2) begin 

fwda = 0;
fwdb = 0;

if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == source_s2) )begin 
    fwda = 2'b10;
end 
else if((RegWrite_s4 ==1) && (write_reg_s4 !=0) &&(write_reg_s4 == source_s2) && !((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == source_s2) ))begin 
    fwda = 2'b01;
end 
if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == dest_for_I_s2) )begin 
    fwdb = 2'b10;
end 
else if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s4 == dest_for_I_s2) && !((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == dest_for_I_s2) ) )begin 
    fwdb = 2'b01;
end 

end
endmodule
module forward(input [4:0]source_s2,input [4:0]dest_for_I_s2,input reset,input [4:0]write_reg_s3,input RegWrite_s3,output reg [1:0]fwda,output reg [1:0]fwdb,input [4:0]write_reg_s4,input RegWrite_s4);


always @(write_reg_s3,source_s2,dest_for_I_s2) begin 

fwda = 0;
fwdb = 0;

if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == source_s2) )begin 
    fwda = 2'b10;
end 
else if((RegWrite_s4 ==1) && (write_reg_s4 !=0) &&(write_reg_s4 == source_s2) && !((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == source_s2) ))begin 
    fwda = 2'b01;
end 
if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == dest_for_I_s2) )begin 
    fwdb = 2'b10;
end 
else if((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s4 == dest_for_I_s2) && !((RegWrite_s3 ==1) && (write_reg_s3 !=0) &&(write_reg_s3 == dest_for_I_s2) ) )begin 
    fwdb = 2'b01;
end 

end
endmodule