data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference/ExampleTopModuleWithBB.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference/ExampleTopModuleWithBB.v:89: Operator COND expects 15 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                      : ... In instance ExampleTopModuleWithBB.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference/ExampleTopModuleWithBB.v:89: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 15 bits.\n                                                                                                                                      : ... In instance ExampleTopModuleWithBB.u_pad_11\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference/ExampleTopModuleWithBB.v:18: Cannot find file containing module: \'BB\'\n    BB bb (\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference,data/full_repos/permissive/493019833/BB\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference,data/full_repos/permissive/493019833/BB.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/reference,data/full_repos/permissive/493019833/BB.sv\n             BB\n             BB.v\n             BB.sv\n             obj_dir/BB\n             obj_dir/BB.v\n             obj_dir/BB.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module ExampleTopModuleWithBB(
    input clock,
    input reset,
    input [14:0] io_a,
    input [14:0] io_b,
    input [13:0] io_c,
    output [15:0] io_x,
    output [15:0] io_y,
    output [15:0] io_z,
    inout [2:0] io_analog1,
    inout [2:0] io_analog2,
    output [4:0] io_v_0,
    output [4:0] io_v_1,
    output [4:0] io_v_2
);
    wire [15:0] _bb__z;
    wire [13:0] _bb__c;
    BB bb (
        .analog2(io_analog2),
        .analog1(io_analog1),
        .z(_bb__z),
        .c(_bb__c)
    );
    wire [15:0] _T_24;
    wire [14:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(15)) u_pad_1 (
        .y(_WTEMP_0),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(15)) u_add_2 (
        .y(_T_24),
        .a(io_a),
        .b(_WTEMP_0)
    );
    wire [14:0] _T_25;
    TAIL #(.width(16), .n(1)) tail_3 (
        .y(_T_25),
        .in(_T_24)
    );
    wire [15:0] _T_27;
    wire [14:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(15)) u_pad_4 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    SUB_UNSIGNED #(.width(15)) u_sub_5 (
        .y(_T_27),
        .a(io_b),
        .b(_WTEMP_1)
    );
    wire [15:0] _T_28;
    ASUINT #(.width(16)) asuint_6 (
        .y(_T_28),
        .in(_T_27)
    );
    wire [14:0] _T_29;
    TAIL #(.width(16), .n(1)) tail_7 (
        .y(_T_29),
        .in(_T_28)
    );
    assign _bb__c = io_c;
    BITS #(.width(15), .high(4), .low(0)) bits_8 (
        .y(io_v_0),
        .in(io_a)
    );
    BITS #(.width(15), .high(4), .low(0)) bits_9 (
        .y(io_v_1),
        .in(io_a)
    );
    BITS #(.width(15), .high(4), .low(0)) bits_10 (
        .y(io_v_2),
        .in(io_a)
    );
    PAD_UNSIGNED #(.width(15), .n(16)) u_pad_11 (
        .y(io_x),
        .in(_T_25)
    );
    PAD_UNSIGNED #(.width(15), .n(16)) u_pad_12 (
        .y(io_y),
        .in(_T_29)
    );
    assign io_z = _bb__z;
endmodule
module ExampleTopModuleWithBB(
    input clock,
    input reset,
    input [14:0] io_a,
    input [14:0] io_b,
    input [13:0] io_c,
    output [15:0] io_x,
    output [15:0] io_y,
    output [15:0] io_z,
    inout [2:0] io_analog1,
    inout [2:0] io_analog2,
    output [4:0] io_v_0,
    output [4:0] io_v_1,
    output [4:0] io_v_2
);

    wire [15:0] _bb__z;
    wire [13:0] _bb__c;
    BB bb (
        .analog2(io_analog2),
        .analog1(io_analog1),
        .z(_bb__z),
        .c(_bb__c)
    );
    wire [15:0] _T_24;
    wire [14:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(15)) u_pad_1 (
        .y(_WTEMP_0),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(15)) u_add_2 (
        .y(_T_24),
        .a(io_a),
        .b(_WTEMP_0)
    );
    wire [14:0] _T_25;
    TAIL #(.width(16), .n(1)) tail_3 (
        .y(_T_25),
        .in(_T_24)
    );
    wire [15:0] _T_27;
    wire [14:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(15)) u_pad_4 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    SUB_UNSIGNED #(.width(15)) u_sub_5 (
        .y(_T_27),
        .a(io_b),
        .b(_WTEMP_1)
    );
    wire [15:0] _T_28;
    ASUINT #(.width(16)) asuint_6 (
        .y(_T_28),
        .in(_T_27)
    );
    wire [14:0] _T_29;
    TAIL #(.width(16), .n(1)) tail_7 (
        .y(_T_29),
        .in(_T_28)
    );
    assign _bb__c = io_c;
    BITS #(.width(15), .high(4), .low(0)) bits_8 (
        .y(io_v_0),
        .in(io_a)
    );
    BITS #(.width(15), .high(4), .low(0)) bits_9 (
        .y(io_v_1),
        .in(io_a)
    );
    BITS #(.width(15), .high(4), .low(0)) bits_10 (
        .y(io_v_2),
        .in(io_a)
    );
    PAD_UNSIGNED #(.width(15), .n(16)) u_pad_11 (
        .y(io_x),
        .in(_T_25)
    );
    PAD_UNSIGNED #(.width(15), .n(16)) u_pad_12 (
        .y(io_y),
        .in(_T_29)
    );
    assign io_z = _bb__z;
endmodule