data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v
1: b"%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v:97: Can't find definition of variable: 'TCU_OPCODE_SIZE'\n    input [TCU_OPCODE_SIZE-1:0] cmd;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v:99: Can't find definition of variable: 'TCU_OPCODE_WRITE'\n                                                                                            : ... Suggested alternative: 'TCU_OPCODE_SIZE'\n        if ((cmd == TCU_OPCODE_WRITE) ||\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v:100: Can't find definition of variable: 'TCU_OPCODE_SEND'\n                                                                                             : ... Suggested alternative: 'TCU_OPCODE_SIZE'\n            (cmd == TCU_OPCODE_SEND) ||\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v:101: Can't find definition of variable: 'TCU_OPCODE_REPLY'\n                                                                                             : ... Suggested alternative: 'TCU_OPCODE_SEND'\n            (cmd == TCU_OPCODE_REPLY)) begin\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_functions.v:104: Can't find definition of variable: 'TCU_OPCODE_READ'\n                                                                                             : ... Suggested alternative: 'TCU_OPCODE_SEND'\n        else if (cmd == TCU_OPCODE_READ) begin\n                        ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
function automatic [7:0] set_bsel8;
    input [2:0] addr;
    input [3:0] size;
    reg [7:0] tmp;
    begin
        case(size)
            4'd1: tmp = 8'b0000_0001;
            4'd2: tmp = 8'b0000_0011;
            4'd3: tmp = 8'b0000_0111;
            4'd4: tmp = 8'b0000_1111;
            4'd5: tmp = 8'b0001_1111;
            4'd6: tmp = 8'b0011_1111;
            4'd7: tmp = 8'b0111_1111;
            4'd8: tmp = 8'b1111_1111;
            default: tmp = 8'b0000_0000;
        endcase
        set_bsel8 = tmp << addr;
    end
endfunction
function automatic [7:0] set_bsel8;

    input [2:0] addr;
    input [3:0] size;
    reg [7:0] tmp;
    begin
        case(size)
            4'd1: tmp = 8'b0000_0001;
            4'd2: tmp = 8'b0000_0011;
            4'd3: tmp = 8'b0000_0111;
            4'd4: tmp = 8'b0000_1111;
            4'd5: tmp = 8'b0001_1111;
            4'd6: tmp = 8'b0011_1111;
            4'd7: tmp = 8'b0111_1111;
            4'd8: tmp = 8'b1111_1111;
            default: tmp = 8'b0000_0000;
        endcase
        set_bsel8 = tmp << addr;
    end
endfunction