data/full_repos/permissive/443520440/code/sd_photo_rw.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/443520440/code/sd_photo_rw.v:108: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'sd_read_photo\'\nmodule sd_read_photo(\n       ^~~~~~~~~~~~~\n                                                                              : ... Top module \'sd_write_photo\'\nmodule sd_write_photo(\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module sd_write_photo(
    input                clk                ,  
    input       [3:0]    select_photo_no    ,
    input                caught_photo_mode  ,
    input                wr_req             ,
    input                wr_busy            ,
    output reg           wr_start_en        ,
    output reg  [31:0]   wr_sec_addr        ,
    output      [18:0]   sd_wr_ram_addr
    );


    parameter READ_TIME = 1200;
    parameter DIVIDED_CLK = 50000;


    reg [18:0]          sd_wr_ram_addr_t;
    reg                 send_clk;
    initial             wr_sec_addr <= 0;
    integer             cnt = 0;
    

    always @(posedge clk) begin
        cnt <= cnt + 1;
        if(cnt == DIVIDED_CLK) begin
            cnt <= 0;
            send_clk <= 1;
        end
        else
            send_clk <= 0;
    end
    

    reg caught_photo_mode_0, caught_photo_mode_1;
    wire caught_photo_mode_ena;
    assign caught_photo_mode_ena = caught_photo_mode_0 & ~caught_photo_mode_1;
    always @(posedge clk) begin
        caught_photo_mode_0 <= caught_photo_mode;
        caught_photo_mode_1 <= caught_photo_mode_0;
    end


    reg [10:0] start_cnt;
    initial start_cnt <= 0;
    always @(posedge clk) begin
        if(caught_photo_mode_ena) begin
            start_cnt <= 1;
            case (select_photo_no)
                4'h0: wr_sec_addr <= 32'd73743;
                4'h1: wr_sec_addr <= 32'd74943;
                4'h2: wr_sec_addr <= 32'd76143;
                4'h3: wr_sec_addr <= 32'd77343;
                4'h4: wr_sec_addr <= 32'd78543;
                4'h5: wr_sec_addr <= 32'd79743;
                4'h6: wr_sec_addr <= 32'd80943;
                4'h7: wr_sec_addr <= 32'd82143;
                4'h8: wr_sec_addr <= 32'd83343;
                4'h9: wr_sec_addr <= 32'd84543;
                4'ha: wr_sec_addr <= 32'd85743;
                4'hb: wr_sec_addr <= 32'd86943;
                4'hc: wr_sec_addr <= 32'd88143;
                4'hd: wr_sec_addr <= 32'd89343;
                4'he: wr_sec_addr <= 32'd90543;
                4'hf: wr_sec_addr <= 32'd91743;
                default: wr_sec_addr <= 32'd73743;
            endcase
        end
        wr_start_en <= 0;
        if(send_clk && ~wr_busy && start_cnt > 0) begin
            wr_start_en <= 1;
            wr_sec_addr <= wr_sec_addr + 1;
            start_cnt <= start_cnt + 1;
            if(start_cnt == READ_TIME) begin
                start_cnt <= 0;
            end
        end
    end
    

    assign sd_wr_ram_addr = (sd_wr_ram_addr_t[18] & sd_wr_ram_addr_t[17]) ? (19'b0) : sd_wr_ram_addr_t;
    always@(posedge clk) begin
        if(!caught_photo_mode) begin
            sd_wr_ram_addr_t <= 19'b0;
        end else if(wr_start_en) begin
            sd_wr_ram_addr_t <= sd_wr_ram_addr_t - 19'b1;
        end else if(wr_req) begin
            if(sd_wr_ram_addr_t < 19'd307219) begin
                sd_wr_ram_addr_t <= sd_wr_ram_addr_t +19'd1;
            end
            else begin
                sd_wr_ram_addr_t <= 19'd0;
            end
        end
    end
endmodule
module sd_write_photo(
    input                clk                ,  
    input       [3:0]    select_photo_no    ,
    input                caught_photo_mode  ,
    input                wr_req             ,
    input                wr_busy            ,
    output reg           wr_start_en        ,
    output reg  [31:0]   wr_sec_addr        ,
    output      [18:0]   sd_wr_ram_addr
    );



    parameter READ_TIME = 1200;
    parameter DIVIDED_CLK = 50000;


    reg [18:0]          sd_wr_ram_addr_t;
    reg                 send_clk;
    initial             wr_sec_addr <= 0;
    integer             cnt = 0;
    

    always @(posedge clk) begin
        cnt <= cnt + 1;
        if(cnt == DIVIDED_CLK) begin
            cnt <= 0;
            send_clk <= 1;
        end
        else
            send_clk <= 0;
    end
    

    reg caught_photo_mode_0, caught_photo_mode_1;
    wire caught_photo_mode_ena;
    assign caught_photo_mode_ena = caught_photo_mode_0 & ~caught_photo_mode_1;
    always @(posedge clk) begin
        caught_photo_mode_0 <= caught_photo_mode;
        caught_photo_mode_1 <= caught_photo_mode_0;
    end


    reg [10:0] start_cnt;
    initial start_cnt <= 0;
    always @(posedge clk) begin
        if(caught_photo_mode_ena) begin
            start_cnt <= 1;
            case (select_photo_no)
                4'h0: wr_sec_addr <= 32'd73743;
                4'h1: wr_sec_addr <= 32'd74943;
                4'h2: wr_sec_addr <= 32'd76143;
                4'h3: wr_sec_addr <= 32'd77343;
                4'h4: wr_sec_addr <= 32'd78543;
                4'h5: wr_sec_addr <= 32'd79743;
                4'h6: wr_sec_addr <= 32'd80943;
                4'h7: wr_sec_addr <= 32'd82143;
                4'h8: wr_sec_addr <= 32'd83343;
                4'h9: wr_sec_addr <= 32'd84543;
                4'ha: wr_sec_addr <= 32'd85743;
                4'hb: wr_sec_addr <= 32'd86943;
                4'hc: wr_sec_addr <= 32'd88143;
                4'hd: wr_sec_addr <= 32'd89343;
                4'he: wr_sec_addr <= 32'd90543;
                4'hf: wr_sec_addr <= 32'd91743;
                default: wr_sec_addr <= 32'd73743;
            endcase
        end
        wr_start_en <= 0;
        if(send_clk && ~wr_busy && start_cnt > 0) begin
            wr_start_en <= 1;
            wr_sec_addr <= wr_sec_addr + 1;
            start_cnt <= start_cnt + 1;
            if(start_cnt == READ_TIME) begin
                start_cnt <= 0;
            end
        end
    end
    

    assign sd_wr_ram_addr = (sd_wr_ram_addr_t[18] & sd_wr_ram_addr_t[17]) ? (19'b0) : sd_wr_ram_addr_t;
    always@(posedge clk) begin
        if(!caught_photo_mode) begin
            sd_wr_ram_addr_t <= 19'b0;
        end else if(wr_start_en) begin
            sd_wr_ram_addr_t <= sd_wr_ram_addr_t - 19'b1;
        end else if(wr_req) begin
            if(sd_wr_ram_addr_t < 19'd307219) begin
                sd_wr_ram_addr_t <= sd_wr_ram_addr_t +19'd1;
            end
            else begin
                sd_wr_ram_addr_t <= 19'd0;
            end
        end
    end
endmodule