data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module ALUcontrol #(parameter len = 4)(
    input [1:0] ALUOp,
    input [len-1:0] inst,
    output reg [len-1:0] ctrl
);
    always @(ALUOp, inst) begin
        ctrl <= 0;
        case(ALUOp)
            2'b00: ctrl <= 4'h2;
            2'b01: begin
                case(inst[len-2:0])
                    3'b000: ctrl <= 4'h3;
                    3'b001: ctrl <= 4'h4;
                    3'b100: ctrl <= 4'h8;
                    3'b101: ctrl <= 4'h9;
                endcase
            end
            2'b10: begin
                case(inst[2:0])
                    3'b000: ctrl <= (inst[3])? 4'h3 : 4'h2;
                    3'b111: ctrl <= 4'h0;
                    3'b110: ctrl <= 4'h1;
                    3'b001: ctrl <= 4'h5;
                    3'b101: ctrl <= (inst[3])? 4'h7 : 4'h6;
                endcase
            end
            2'b11: begin
                case (inst[2:0])
                    3'b000: ctrl <= 4'h2;
                    3'b111: ctrl <= 4'h0;
                    3'b001: ctrl <= 4'h5;
                    3'b101: ctrl <= (inst[3])? 4'h7 : 4'h6;
                endcase
            end
        endcase
    end
endmodule
module ALUcontrol #(parameter len = 4)(
    input [1:0] ALUOp,
    input [len-1:0] inst,
    output reg [len-1:0] ctrl
);

    always @(ALUOp, inst) begin
        ctrl <= 0;
        case(ALUOp)
            2'b00: ctrl <= 4'h2;
            2'b01: begin
                case(inst[len-2:0])
                    3'b000: ctrl <= 4'h3;
                    3'b001: ctrl <= 4'h4;
                    3'b100: ctrl <= 4'h8;
                    3'b101: ctrl <= 4'h9;
                endcase
            end
            2'b10: begin
                case(inst[2:0])
                    3'b000: ctrl <= (inst[3])? 4'h3 : 4'h2;
                    3'b111: ctrl <= 4'h0;
                    3'b110: ctrl <= 4'h1;
                    3'b001: ctrl <= 4'h5;
                    3'b101: ctrl <= (inst[3])? 4'h7 : 4'h6;
                endcase
            end
            2'b11: begin
                case (inst[2:0])
                    3'b000: ctrl <= 4'h2;
                    3'b111: ctrl <= 4'h0;
                    3'b001: ctrl <= 4'h5;
                    3'b101: ctrl <= (inst[3])? 4'h7 : 4'h6;
                endcase
            end
        endcase
    end
endmodule