data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:265: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  {`PA_WIDTH{1'b0}};\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:265: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  {`PA_WIDTH{1'b0}};\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:267: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_inst_new_va[`PA_WIDTH-1:0];\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:267: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_inst_new_va[`PA_WIDTH-1:0];\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:269: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0];\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:269: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0];\n                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:271: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_vpn[`PA_WIDTH-13:0] = entry_l1_pf_va[`PA_WIDTH-1:12];\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:271: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_vpn[`PA_WIDTH-13:0] = entry_l1_pf_va[`PA_WIDTH-1:12];\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:280: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  {`PA_WIDTH-12{1'b0}};\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:280: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  {`PA_WIDTH-12{1'b0}};\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:286: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  ld_da_ppn_ff[`PA_WIDTH-13:0];\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:286: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  ld_da_ppn_ff[`PA_WIDTH-13:0];\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:292: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  pfu_get_ppn[`PA_WIDTH-13:0];\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:292: Define or directive not defined: '`PA_WIDTH'\n    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  pfu_get_ppn[`PA_WIDTH-13:0];\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:413: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0]  = entry_l1_pf_va[`PA_WIDTH-1:0]\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:413: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0]  = entry_l1_pf_va[`PA_WIDTH-1:0]\n                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:414: Define or directive not defined: '`PA_WIDTH'\n                                                    + entry_strideh[`PA_WIDTH-1:0];\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:436: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_addr[`PA_WIDTH-1:0]  = {entry_l1_pf_ppn[`PA_WIDTH-13:0],\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:436: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_addr[`PA_WIDTH-1:0]  = {entry_l1_pf_ppn[`PA_WIDTH-13:0],\n                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:461: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]  =\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:462: Define or directive not defined: '`PA_WIDTH'\n                entry_l1_pf_va[`PA_WIDTH-1:0]\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:463: Define or directive not defined: '`PA_WIDTH'\n                - entry_inst_new_va[`PA_WIDTH-1:0];\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:465: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1:0] =\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:466: Define or directive not defined: '`PA_WIDTH'\n                entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:467: Define or directive not defined: '`PA_WIDTH'\n                - entry_l1_dist_strideh[`PA_WIDTH-1:0];\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:469: Define or directive not defined: '`PA_WIDTH'\nassign entry_l1_pf_va_eq_inst_new_va = !(|entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]);\n                                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:471: Define or directive not defined: '`PA_WIDTH'\nassign entry_inst_new_va_surpass_l1_pf_va_set = (entry_stride_neg ^ entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1])\n                                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pfb_l1sm.v:474: Define or directive not defined: '`PA_WIDTH'\nassign entry_in_l1_pf_region_set  = entry_stride_neg ^ entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1];\n                                                                                        ^~~~~~~~~\n%Error: Exiting due to 28 error(s)\n"
module ct_lsu_pfu_pfb_l1sm(
  cp0_lsu_icg_en,
  cp0_lsu_pfu_mmu_dis,
  cp0_yy_clk_en,
  cpurst_b,
  entry_biu_pe_req,
  entry_biu_pe_req_grnt,
  entry_biu_pe_req_src,
  entry_clk,
  entry_create_dp_vld,
  entry_inst_new_va,
  entry_l1_biu_pe_req_set,
  entry_l1_cmp_va_vld,
  entry_l1_dist_strideh,
  entry_l1_mmu_pe_req_set,
  entry_l1_page_sec,
  entry_l1_page_share,
  entry_l1_pf_addr,
  entry_l1_pf_va,
  entry_l1_pf_va_sub_inst_new_va,
  entry_l1_vpn,
  entry_l1sm_reinit_req,
  entry_l1sm_va_can_cmp,
  entry_mmu_pe_req,
  entry_mmu_pe_req_grnt,
  entry_mmu_pe_req_src,
  entry_pf_inst_vld,
  entry_pop_vld,
  entry_reinit_vld,
  entry_stride_neg,
  entry_strideh,
  entry_tsm_is_judge,
  forever_cpuclk,
  ld_da_page_sec_ff,
  ld_da_page_share_ff,
  ld_da_ppn_ff,
  pad_yy_icg_scan_en,
  pfu_biu_pe_req_sel_l1,
  pfu_dcache_pref_en,
  pfu_get_page_sec,
  pfu_get_page_share,
  pfu_get_ppn,
  pfu_get_ppn_err,
  pfu_get_ppn_vld,
  pfu_mmu_pe_req_sel_l1
);


input           cp0_lsu_icg_en;                        
input           cp0_lsu_pfu_mmu_dis;                   
input           cp0_yy_clk_en;                         
input           cpurst_b;                              
input           entry_biu_pe_req;                      
input           entry_biu_pe_req_grnt;                 
input   [1 :0]  entry_biu_pe_req_src;                  
input           entry_clk;                             
input           entry_create_dp_vld;                   
input   [39:0]  entry_inst_new_va;                     
input   [39:0]  entry_l1_dist_strideh;                 
input           entry_mmu_pe_req;                      
input           entry_mmu_pe_req_grnt;                 
input   [1 :0]  entry_mmu_pe_req_src;                  
input           entry_pf_inst_vld;                     
input           entry_pop_vld;                         
input           entry_reinit_vld;                      
input           entry_stride_neg;                      
input   [39:0]  entry_strideh;                         
input           entry_tsm_is_judge;                    
input           forever_cpuclk;                        
input           ld_da_page_sec_ff;                     
input           ld_da_page_share_ff;                   
input   [27:0]  ld_da_ppn_ff;                          
input           pad_yy_icg_scan_en;                    
input           pfu_biu_pe_req_sel_l1;                 
input           pfu_dcache_pref_en;                    
input           pfu_get_page_sec;                      
input           pfu_get_page_share;                    
input   [27:0]  pfu_get_ppn;                           
input           pfu_get_ppn_err;                       
input           pfu_get_ppn_vld;                       
input           pfu_mmu_pe_req_sel_l1;                 
output          entry_l1_biu_pe_req_set;               
output          entry_l1_cmp_va_vld;                   
output          entry_l1_mmu_pe_req_set;               
output          entry_l1_page_sec;                     
output          entry_l1_page_share;                   
output  [39:0]  entry_l1_pf_addr;                      
output  [39:0]  entry_l1_pf_va;                        
output  [39:0]  entry_l1_pf_va_sub_inst_new_va;        
output  [27:0]  entry_l1_vpn;                          
output          entry_l1sm_reinit_req;                 
output          entry_l1sm_va_can_cmp;                 


reg             entry_in_l1_pf_region;                 
reg             entry_inst_new_va_surpass_l1_pf_va;    
reg             entry_l1_cmp_va_vld;                   
reg     [2 :0]  entry_l1_next_state;                   
reg             entry_l1_page_sec;                     
reg             entry_l1_page_share;                   
reg     [27:0]  entry_l1_pf_ppn;                       
reg     [39:0]  entry_l1_pf_va;                        
reg     [2 :0]  entry_l1_state;                        


wire            cp0_lsu_icg_en;                        
wire            cp0_lsu_pfu_mmu_dis;                   
wire            cp0_yy_clk_en;                         
wire            cpurst_b;                              
wire            entry_biu_pe_req;                      
wire            entry_biu_pe_req_grnt;                 
wire    [1 :0]  entry_biu_pe_req_src;                  
wire            entry_clk;                             
wire            entry_create_dp_vld;                   
wire            entry_in_l1_pf_region_set;             
wire    [39:0]  entry_inst_new_va;                     
wire            entry_inst_new_va_surpass_l1_pf_va_set; 
wire            entry_l1_biu_pe_req;                   
wire            entry_l1_biu_pe_req_grnt;              
wire            entry_l1_biu_pe_req_set;               
wire    [39:0]  entry_l1_dist_strideh;                 
wire            entry_l1_mmu_pe_req;                   
wire            entry_l1_mmu_pe_req_grnt;              
wire            entry_l1_mmu_pe_req_set;               
wire    [39:0]  entry_l1_pf_addr;                      
wire            entry_l1_pf_addr_init_vld;             
wire            entry_l1_pf_ppn_clk;                   
wire            entry_l1_pf_ppn_clk_en;                
wire            entry_l1_pf_ppn_up_vld;                
wire            entry_l1_pf_va_add_gateclk_en;         
wire    [39:0]  entry_l1_pf_va_add_strideh;            
wire            entry_l1_pf_va_add_vld;                
wire            entry_l1_pf_va_clk;                    
wire            entry_l1_pf_va_clk_en;                 
wire            entry_l1_pf_va_cross_4k;               
wire            entry_l1_pf_va_eq_inst_new_va;         
wire    [39:0]  entry_l1_pf_va_sub_inst_new_va;        
wire    [12:0]  entry_l1_pf_va_sum_4k;                 
wire    [27:0]  entry_l1_vpn;                          
wire    [39:0]  entry_l1sm_diff_sub_dist_strideh;      
wire            entry_l1sm_is_add_pf_va;               
wire            entry_l1sm_is_init_pf_addr;            
wire            entry_l1sm_is_req_mmu;                 
wire            entry_l1sm_is_req_pf;                  
wire            entry_l1sm_is_wait_ppn;                
wire            entry_l1sm_reinit_req;                 
wire            entry_l1sm_va_can_cmp;                 
wire            entry_mmu_pe_req;                      
wire            entry_mmu_pe_req_grnt;                 
wire    [1 :0]  entry_mmu_pe_req_src;                  
wire            entry_pf_inst_vld;                     
wire            entry_pop_vld;                         
wire            entry_reinit_vld;                      
wire            entry_stride_neg;                      
wire    [39:0]  entry_strideh;                         
wire            entry_tsm_is_judge;                    
wire            forever_cpuclk;                        
wire            ld_da_page_sec_ff;                     
wire            ld_da_page_share_ff;                   
wire    [27:0]  ld_da_ppn_ff;                          
wire            pad_yy_icg_scan_en;                    
wire            pfu_biu_pe_req_sel_l1;                 
wire            pfu_dcache_pref_en;                    
wire            pfu_get_page_sec;                      
wire            pfu_get_page_share;                    
wire    [27:0]  pfu_get_ppn;                           
wire            pfu_get_ppn_err;                       
wire            pfu_get_ppn_vld;                       
wire            pfu_mmu_pe_req_sel_l1;                 


parameter L1_INIT_PF_ADDR = 3'b000,
          L1_ADD_PF_VA    = 3'b001,
          L1_REQ_PF       = 3'b100,
          L1_REQ_MMU      = 3'b101,
          L1_WAIT_PPN     = 3'b110,
          L1_DEAD         = 3'b111;





assign entry_l1_pf_va_clk_en  = entry_l1_pf_addr_init_vld
                                ||  entry_l1_pf_va_add_gateclk_en;

gated_clk_cell  x_lsu_pfu_pfb_l1sm_pf_va_gated_clk (
  .clk_in                (forever_cpuclk       ),
  .clk_out               (entry_l1_pf_va_clk   ),
  .external_en           (1'b0                 ),
  .global_en             (cp0_yy_clk_en        ),
  .local_en              (entry_l1_pf_va_clk_en),
  .module_en             (cp0_lsu_icg_en       ),
  .pad_yy_icg_scan_en    (pad_yy_icg_scan_en   )
);









assign entry_l1_pf_ppn_clk_en = entry_l1_pf_addr_init_vld
                                    &&  pfu_dcache_pref_en
                                ||  entry_l1_pf_ppn_up_vld;

gated_clk_cell  x_lsu_pfu_pfb_l1sm_pf_ppn_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (entry_l1_pf_ppn_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (entry_l1_pf_ppn_clk_en),
  .module_en              (cp0_lsu_icg_en        ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);















always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_state[2:0]  <=  L1_INIT_PF_ADDR;
  else if(entry_pop_vld ||  entry_reinit_vld || !pfu_dcache_pref_en)
    entry_l1_state[2:0]  <=  L1_INIT_PF_ADDR;
  else
    entry_l1_state[2:0]  <=  entry_l1_next_state[2:0];
end





always @(posedge entry_l1_pf_va_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  {`PA_WIDTH{1'b0}};
  else if(entry_l1_pf_addr_init_vld)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_inst_new_va[`PA_WIDTH-1:0];
  else if(entry_l1_pf_va_add_vld)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0];
end
assign entry_l1_vpn[`PA_WIDTH-13:0] = entry_l1_pf_va[`PA_WIDTH-1:12];




always @(posedge entry_l1_pf_ppn_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  {`PA_WIDTH-12{1'b0}};
    entry_l1_page_sec               <=  1'b0;
    entry_l1_page_share             <=  1'b0;
  end
  else if(entry_l1_pf_addr_init_vld &&  pfu_dcache_pref_en)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  ld_da_ppn_ff[`PA_WIDTH-13:0];
    entry_l1_page_sec               <=  ld_da_page_sec_ff;
    entry_l1_page_share             <=  ld_da_page_share_ff;
  end
  else if(entry_l1_pf_ppn_up_vld)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  pfu_get_ppn[`PA_WIDTH-13:0];
    entry_l1_page_sec               <=  pfu_get_page_sec;
    entry_l1_page_share             <=  pfu_get_page_share;
  end
end





always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_cmp_va_vld   <=  1'b0;
  else if(entry_create_dp_vld ||  entry_reinit_vld)
    entry_l1_cmp_va_vld   <=  1'b0;
  else if(entry_l1_pf_va_add_vld  ||  entry_pf_inst_vld &&  entry_l1sm_va_can_cmp)
    entry_l1_cmp_va_vld   <=  1'b1;
  else
    entry_l1_cmp_va_vld   <=  1'b0;
end




always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  1'b0;
    entry_in_l1_pf_region               <=  1'b1;
  end
  else if(entry_create_dp_vld ||  entry_reinit_vld)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  1'b0;
    entry_in_l1_pf_region               <=  1'b1;
  end
  else if(entry_l1_cmp_va_vld &&  entry_l1sm_va_can_cmp)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  entry_inst_new_va_surpass_l1_pf_va_set;
    entry_in_l1_pf_region               <=  entry_in_l1_pf_region_set;
  end
end





always @( pfu_dcache_pref_en
       or pfu_get_ppn_vld
       or entry_l1_state[2:0]
       or cp0_lsu_pfu_mmu_dis
       or entry_l1_pf_va_add_vld
       or entry_l1_mmu_pe_req_grnt
       or entry_reinit_vld
       or pfu_get_ppn_err
       or entry_l1_pf_va_cross_4k
       or entry_l1_pf_addr_init_vld)
begin
entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
case(entry_l1_state[2:0])
  L1_INIT_PF_ADDR:
    if(entry_l1_pf_addr_init_vld  &&  pfu_dcache_pref_en)
      entry_l1_next_state[2:0] = L1_ADD_PF_VA;
    else
      entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
  L1_ADD_PF_VA:
      entry_l1_next_state[2:0] = L1_REQ_PF;
  L1_REQ_PF:
    if(entry_l1_pf_va_add_vld &&  entry_l1_pf_va_cross_4k && cp0_lsu_pfu_mmu_dis)
      entry_l1_next_state[2:0] = L1_DEAD;
    else if(entry_l1_pf_va_add_vld &&  entry_l1_pf_va_cross_4k)
      entry_l1_next_state[2:0] = L1_REQ_MMU;
    else
      entry_l1_next_state[2:0] = L1_REQ_PF;
  L1_REQ_MMU:
    if(entry_l1_mmu_pe_req_grnt)
      entry_l1_next_state[2:0] = L1_WAIT_PPN;
    else
      entry_l1_next_state[2:0] = L1_REQ_MMU;
  L1_WAIT_PPN:
    if(pfu_get_ppn_vld  &&  !pfu_get_ppn_err)
      entry_l1_next_state[2:0] = L1_REQ_PF;
    else if(pfu_get_ppn_vld  &&  pfu_get_ppn_err)
      entry_l1_next_state[2:0] = L1_DEAD;
    else
      entry_l1_next_state[2:0] = L1_WAIT_PPN;
  L1_DEAD:
    if(entry_reinit_vld)
      entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
    else
      entry_l1_next_state[2:0] = L1_DEAD;
  default:entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
endcase

end

assign entry_l1sm_is_init_pf_addr = entry_l1_state[2:0] ==  L1_INIT_PF_ADDR;
assign entry_l1sm_is_add_pf_va    = entry_l1_state[2:0] ==  L1_ADD_PF_VA;
assign entry_l1sm_is_req_pf       = entry_l1_state[2:0] ==  L1_REQ_PF;
assign entry_l1sm_is_req_mmu      = entry_l1_state[2:0] ==  L1_REQ_MMU;
assign entry_l1sm_is_wait_ppn     = entry_l1_state[2:0] ==  L1_WAIT_PPN;

assign entry_l1sm_va_can_cmp      = entry_l1_state[2];




assign entry_l1_pf_addr_init_vld  = entry_l1sm_is_init_pf_addr
                                    &&  entry_tsm_is_judge;





assign entry_l1_pf_va_add_vld   = entry_l1sm_is_add_pf_va
                                  ||  entry_l1_biu_pe_req_grnt;

assign entry_l1_pf_va_add_gateclk_en  = entry_l1sm_is_add_pf_va
                                        ||  entry_biu_pe_req_grnt;

assign entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0]  = entry_l1_pf_va[`PA_WIDTH-1:0]
                                                    + entry_strideh[`PA_WIDTH-1:0];

assign entry_l1_pf_va_sum_4k[12:0]  = {1'b0,entry_l1_pf_va[11:0]}
                                      + entry_strideh[12:0];

assign entry_l1_pf_va_cross_4k      = entry_l1_pf_va_sum_4k[12];






assign entry_l1_biu_pe_req      = entry_biu_pe_req
                                  &&  entry_biu_pe_req_src[0];

assign entry_l1_biu_pe_req_set  = entry_l1sm_is_req_pf
                                  &&  entry_in_l1_pf_region
                                  &&  !entry_l1_biu_pe_req;

assign entry_l1_biu_pe_req_grnt = pfu_biu_pe_req_sel_l1
                                  &&  entry_biu_pe_req_grnt;

assign entry_l1_pf_addr[`PA_WIDTH-1:0]  = {entry_l1_pf_ppn[`PA_WIDTH-13:0],
                                          entry_l1_pf_va[11:0]};




assign entry_l1_mmu_pe_req      = entry_mmu_pe_req
                                  &&  entry_mmu_pe_req_src[0];

assign entry_l1_mmu_pe_req_set  = entry_l1sm_is_req_mmu
                                  &&  !entry_l1_mmu_pe_req;

assign entry_l1_mmu_pe_req_grnt = entry_mmu_pe_req_grnt
                                  &&  pfu_mmu_pe_req_sel_l1;




assign entry_l1_pf_ppn_up_vld   = entry_l1sm_is_wait_ppn
                                  &&  pfu_get_ppn_vld;





assign entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]  =
                entry_l1_pf_va[`PA_WIDTH-1:0]
                - entry_inst_new_va[`PA_WIDTH-1:0];

assign entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1:0] =
                entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]
                - entry_l1_dist_strideh[`PA_WIDTH-1:0];

assign entry_l1_pf_va_eq_inst_new_va = !(|entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]);

assign entry_inst_new_va_surpass_l1_pf_va_set = (entry_stride_neg ^ entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1])
                                                && !entry_l1_pf_va_eq_inst_new_va;

assign entry_in_l1_pf_region_set  = entry_stride_neg ^ entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1];




assign entry_l1sm_reinit_req  = entry_l1sm_va_can_cmp
                                &&  entry_inst_new_va_surpass_l1_pf_va;


endmodule
module ct_lsu_pfu_pfb_l1sm(
  cp0_lsu_icg_en,
  cp0_lsu_pfu_mmu_dis,
  cp0_yy_clk_en,
  cpurst_b,
  entry_biu_pe_req,
  entry_biu_pe_req_grnt,
  entry_biu_pe_req_src,
  entry_clk,
  entry_create_dp_vld,
  entry_inst_new_va,
  entry_l1_biu_pe_req_set,
  entry_l1_cmp_va_vld,
  entry_l1_dist_strideh,
  entry_l1_mmu_pe_req_set,
  entry_l1_page_sec,
  entry_l1_page_share,
  entry_l1_pf_addr,
  entry_l1_pf_va,
  entry_l1_pf_va_sub_inst_new_va,
  entry_l1_vpn,
  entry_l1sm_reinit_req,
  entry_l1sm_va_can_cmp,
  entry_mmu_pe_req,
  entry_mmu_pe_req_grnt,
  entry_mmu_pe_req_src,
  entry_pf_inst_vld,
  entry_pop_vld,
  entry_reinit_vld,
  entry_stride_neg,
  entry_strideh,
  entry_tsm_is_judge,
  forever_cpuclk,
  ld_da_page_sec_ff,
  ld_da_page_share_ff,
  ld_da_ppn_ff,
  pad_yy_icg_scan_en,
  pfu_biu_pe_req_sel_l1,
  pfu_dcache_pref_en,
  pfu_get_page_sec,
  pfu_get_page_share,
  pfu_get_ppn,
  pfu_get_ppn_err,
  pfu_get_ppn_vld,
  pfu_mmu_pe_req_sel_l1
);



input           cp0_lsu_icg_en;                        
input           cp0_lsu_pfu_mmu_dis;                   
input           cp0_yy_clk_en;                         
input           cpurst_b;                              
input           entry_biu_pe_req;                      
input           entry_biu_pe_req_grnt;                 
input   [1 :0]  entry_biu_pe_req_src;                  
input           entry_clk;                             
input           entry_create_dp_vld;                   
input   [39:0]  entry_inst_new_va;                     
input   [39:0]  entry_l1_dist_strideh;                 
input           entry_mmu_pe_req;                      
input           entry_mmu_pe_req_grnt;                 
input   [1 :0]  entry_mmu_pe_req_src;                  
input           entry_pf_inst_vld;                     
input           entry_pop_vld;                         
input           entry_reinit_vld;                      
input           entry_stride_neg;                      
input   [39:0]  entry_strideh;                         
input           entry_tsm_is_judge;                    
input           forever_cpuclk;                        
input           ld_da_page_sec_ff;                     
input           ld_da_page_share_ff;                   
input   [27:0]  ld_da_ppn_ff;                          
input           pad_yy_icg_scan_en;                    
input           pfu_biu_pe_req_sel_l1;                 
input           pfu_dcache_pref_en;                    
input           pfu_get_page_sec;                      
input           pfu_get_page_share;                    
input   [27:0]  pfu_get_ppn;                           
input           pfu_get_ppn_err;                       
input           pfu_get_ppn_vld;                       
input           pfu_mmu_pe_req_sel_l1;                 
output          entry_l1_biu_pe_req_set;               
output          entry_l1_cmp_va_vld;                   
output          entry_l1_mmu_pe_req_set;               
output          entry_l1_page_sec;                     
output          entry_l1_page_share;                   
output  [39:0]  entry_l1_pf_addr;                      
output  [39:0]  entry_l1_pf_va;                        
output  [39:0]  entry_l1_pf_va_sub_inst_new_va;        
output  [27:0]  entry_l1_vpn;                          
output          entry_l1sm_reinit_req;                 
output          entry_l1sm_va_can_cmp;                 


reg             entry_in_l1_pf_region;                 
reg             entry_inst_new_va_surpass_l1_pf_va;    
reg             entry_l1_cmp_va_vld;                   
reg     [2 :0]  entry_l1_next_state;                   
reg             entry_l1_page_sec;                     
reg             entry_l1_page_share;                   
reg     [27:0]  entry_l1_pf_ppn;                       
reg     [39:0]  entry_l1_pf_va;                        
reg     [2 :0]  entry_l1_state;                        


wire            cp0_lsu_icg_en;                        
wire            cp0_lsu_pfu_mmu_dis;                   
wire            cp0_yy_clk_en;                         
wire            cpurst_b;                              
wire            entry_biu_pe_req;                      
wire            entry_biu_pe_req_grnt;                 
wire    [1 :0]  entry_biu_pe_req_src;                  
wire            entry_clk;                             
wire            entry_create_dp_vld;                   
wire            entry_in_l1_pf_region_set;             
wire    [39:0]  entry_inst_new_va;                     
wire            entry_inst_new_va_surpass_l1_pf_va_set; 
wire            entry_l1_biu_pe_req;                   
wire            entry_l1_biu_pe_req_grnt;              
wire            entry_l1_biu_pe_req_set;               
wire    [39:0]  entry_l1_dist_strideh;                 
wire            entry_l1_mmu_pe_req;                   
wire            entry_l1_mmu_pe_req_grnt;              
wire            entry_l1_mmu_pe_req_set;               
wire    [39:0]  entry_l1_pf_addr;                      
wire            entry_l1_pf_addr_init_vld;             
wire            entry_l1_pf_ppn_clk;                   
wire            entry_l1_pf_ppn_clk_en;                
wire            entry_l1_pf_ppn_up_vld;                
wire            entry_l1_pf_va_add_gateclk_en;         
wire    [39:0]  entry_l1_pf_va_add_strideh;            
wire            entry_l1_pf_va_add_vld;                
wire            entry_l1_pf_va_clk;                    
wire            entry_l1_pf_va_clk_en;                 
wire            entry_l1_pf_va_cross_4k;               
wire            entry_l1_pf_va_eq_inst_new_va;         
wire    [39:0]  entry_l1_pf_va_sub_inst_new_va;        
wire    [12:0]  entry_l1_pf_va_sum_4k;                 
wire    [27:0]  entry_l1_vpn;                          
wire    [39:0]  entry_l1sm_diff_sub_dist_strideh;      
wire            entry_l1sm_is_add_pf_va;               
wire            entry_l1sm_is_init_pf_addr;            
wire            entry_l1sm_is_req_mmu;                 
wire            entry_l1sm_is_req_pf;                  
wire            entry_l1sm_is_wait_ppn;                
wire            entry_l1sm_reinit_req;                 
wire            entry_l1sm_va_can_cmp;                 
wire            entry_mmu_pe_req;                      
wire            entry_mmu_pe_req_grnt;                 
wire    [1 :0]  entry_mmu_pe_req_src;                  
wire            entry_pf_inst_vld;                     
wire            entry_pop_vld;                         
wire            entry_reinit_vld;                      
wire            entry_stride_neg;                      
wire    [39:0]  entry_strideh;                         
wire            entry_tsm_is_judge;                    
wire            forever_cpuclk;                        
wire            ld_da_page_sec_ff;                     
wire            ld_da_page_share_ff;                   
wire    [27:0]  ld_da_ppn_ff;                          
wire            pad_yy_icg_scan_en;                    
wire            pfu_biu_pe_req_sel_l1;                 
wire            pfu_dcache_pref_en;                    
wire            pfu_get_page_sec;                      
wire            pfu_get_page_share;                    
wire    [27:0]  pfu_get_ppn;                           
wire            pfu_get_ppn_err;                       
wire            pfu_get_ppn_vld;                       
wire            pfu_mmu_pe_req_sel_l1;                 


parameter L1_INIT_PF_ADDR = 3'b000,
          L1_ADD_PF_VA    = 3'b001,
          L1_REQ_PF       = 3'b100,
          L1_REQ_MMU      = 3'b101,
          L1_WAIT_PPN     = 3'b110,
          L1_DEAD         = 3'b111;





assign entry_l1_pf_va_clk_en  = entry_l1_pf_addr_init_vld
                                ||  entry_l1_pf_va_add_gateclk_en;

gated_clk_cell  x_lsu_pfu_pfb_l1sm_pf_va_gated_clk (
  .clk_in                (forever_cpuclk       ),
  .clk_out               (entry_l1_pf_va_clk   ),
  .external_en           (1'b0                 ),
  .global_en             (cp0_yy_clk_en        ),
  .local_en              (entry_l1_pf_va_clk_en),
  .module_en             (cp0_lsu_icg_en       ),
  .pad_yy_icg_scan_en    (pad_yy_icg_scan_en   )
);









assign entry_l1_pf_ppn_clk_en = entry_l1_pf_addr_init_vld
                                    &&  pfu_dcache_pref_en
                                ||  entry_l1_pf_ppn_up_vld;

gated_clk_cell  x_lsu_pfu_pfb_l1sm_pf_ppn_gated_clk (
  .clk_in                 (forever_cpuclk        ),
  .clk_out                (entry_l1_pf_ppn_clk   ),
  .external_en            (1'b0                  ),
  .global_en              (cp0_yy_clk_en         ),
  .local_en               (entry_l1_pf_ppn_clk_en),
  .module_en              (cp0_lsu_icg_en        ),
  .pad_yy_icg_scan_en     (pad_yy_icg_scan_en    )
);















always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_state[2:0]  <=  L1_INIT_PF_ADDR;
  else if(entry_pop_vld ||  entry_reinit_vld || !pfu_dcache_pref_en)
    entry_l1_state[2:0]  <=  L1_INIT_PF_ADDR;
  else
    entry_l1_state[2:0]  <=  entry_l1_next_state[2:0];
end





always @(posedge entry_l1_pf_va_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  {`PA_WIDTH{1'b0}};
  else if(entry_l1_pf_addr_init_vld)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_inst_new_va[`PA_WIDTH-1:0];
  else if(entry_l1_pf_va_add_vld)
    entry_l1_pf_va[`PA_WIDTH-1:0] <=  entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0];
end
assign entry_l1_vpn[`PA_WIDTH-13:0] = entry_l1_pf_va[`PA_WIDTH-1:12];




always @(posedge entry_l1_pf_ppn_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  {`PA_WIDTH-12{1'b0}};
    entry_l1_page_sec               <=  1'b0;
    entry_l1_page_share             <=  1'b0;
  end
  else if(entry_l1_pf_addr_init_vld &&  pfu_dcache_pref_en)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  ld_da_ppn_ff[`PA_WIDTH-13:0];
    entry_l1_page_sec               <=  ld_da_page_sec_ff;
    entry_l1_page_share             <=  ld_da_page_share_ff;
  end
  else if(entry_l1_pf_ppn_up_vld)
  begin
    entry_l1_pf_ppn[`PA_WIDTH-13:0] <=  pfu_get_ppn[`PA_WIDTH-13:0];
    entry_l1_page_sec               <=  pfu_get_page_sec;
    entry_l1_page_share             <=  pfu_get_page_share;
  end
end





always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    entry_l1_cmp_va_vld   <=  1'b0;
  else if(entry_create_dp_vld ||  entry_reinit_vld)
    entry_l1_cmp_va_vld   <=  1'b0;
  else if(entry_l1_pf_va_add_vld  ||  entry_pf_inst_vld &&  entry_l1sm_va_can_cmp)
    entry_l1_cmp_va_vld   <=  1'b1;
  else
    entry_l1_cmp_va_vld   <=  1'b0;
end




always @(posedge entry_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  1'b0;
    entry_in_l1_pf_region               <=  1'b1;
  end
  else if(entry_create_dp_vld ||  entry_reinit_vld)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  1'b0;
    entry_in_l1_pf_region               <=  1'b1;
  end
  else if(entry_l1_cmp_va_vld &&  entry_l1sm_va_can_cmp)
  begin
    entry_inst_new_va_surpass_l1_pf_va  <=  entry_inst_new_va_surpass_l1_pf_va_set;
    entry_in_l1_pf_region               <=  entry_in_l1_pf_region_set;
  end
end





always @( pfu_dcache_pref_en
       or pfu_get_ppn_vld
       or entry_l1_state[2:0]
       or cp0_lsu_pfu_mmu_dis
       or entry_l1_pf_va_add_vld
       or entry_l1_mmu_pe_req_grnt
       or entry_reinit_vld
       or pfu_get_ppn_err
       or entry_l1_pf_va_cross_4k
       or entry_l1_pf_addr_init_vld)
begin
entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
case(entry_l1_state[2:0])
  L1_INIT_PF_ADDR:
    if(entry_l1_pf_addr_init_vld  &&  pfu_dcache_pref_en)
      entry_l1_next_state[2:0] = L1_ADD_PF_VA;
    else
      entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
  L1_ADD_PF_VA:
      entry_l1_next_state[2:0] = L1_REQ_PF;
  L1_REQ_PF:
    if(entry_l1_pf_va_add_vld &&  entry_l1_pf_va_cross_4k && cp0_lsu_pfu_mmu_dis)
      entry_l1_next_state[2:0] = L1_DEAD;
    else if(entry_l1_pf_va_add_vld &&  entry_l1_pf_va_cross_4k)
      entry_l1_next_state[2:0] = L1_REQ_MMU;
    else
      entry_l1_next_state[2:0] = L1_REQ_PF;
  L1_REQ_MMU:
    if(entry_l1_mmu_pe_req_grnt)
      entry_l1_next_state[2:0] = L1_WAIT_PPN;
    else
      entry_l1_next_state[2:0] = L1_REQ_MMU;
  L1_WAIT_PPN:
    if(pfu_get_ppn_vld  &&  !pfu_get_ppn_err)
      entry_l1_next_state[2:0] = L1_REQ_PF;
    else if(pfu_get_ppn_vld  &&  pfu_get_ppn_err)
      entry_l1_next_state[2:0] = L1_DEAD;
    else
      entry_l1_next_state[2:0] = L1_WAIT_PPN;
  L1_DEAD:
    if(entry_reinit_vld)
      entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
    else
      entry_l1_next_state[2:0] = L1_DEAD;
  default:entry_l1_next_state[2:0] = L1_INIT_PF_ADDR;
endcase

end

assign entry_l1sm_is_init_pf_addr = entry_l1_state[2:0] ==  L1_INIT_PF_ADDR;
assign entry_l1sm_is_add_pf_va    = entry_l1_state[2:0] ==  L1_ADD_PF_VA;
assign entry_l1sm_is_req_pf       = entry_l1_state[2:0] ==  L1_REQ_PF;
assign entry_l1sm_is_req_mmu      = entry_l1_state[2:0] ==  L1_REQ_MMU;
assign entry_l1sm_is_wait_ppn     = entry_l1_state[2:0] ==  L1_WAIT_PPN;

assign entry_l1sm_va_can_cmp      = entry_l1_state[2];




assign entry_l1_pf_addr_init_vld  = entry_l1sm_is_init_pf_addr
                                    &&  entry_tsm_is_judge;





assign entry_l1_pf_va_add_vld   = entry_l1sm_is_add_pf_va
                                  ||  entry_l1_biu_pe_req_grnt;

assign entry_l1_pf_va_add_gateclk_en  = entry_l1sm_is_add_pf_va
                                        ||  entry_biu_pe_req_grnt;

assign entry_l1_pf_va_add_strideh[`PA_WIDTH-1:0]  = entry_l1_pf_va[`PA_WIDTH-1:0]
                                                    + entry_strideh[`PA_WIDTH-1:0];

assign entry_l1_pf_va_sum_4k[12:0]  = {1'b0,entry_l1_pf_va[11:0]}
                                      + entry_strideh[12:0];

assign entry_l1_pf_va_cross_4k      = entry_l1_pf_va_sum_4k[12];






assign entry_l1_biu_pe_req      = entry_biu_pe_req
                                  &&  entry_biu_pe_req_src[0];

assign entry_l1_biu_pe_req_set  = entry_l1sm_is_req_pf
                                  &&  entry_in_l1_pf_region
                                  &&  !entry_l1_biu_pe_req;

assign entry_l1_biu_pe_req_grnt = pfu_biu_pe_req_sel_l1
                                  &&  entry_biu_pe_req_grnt;

assign entry_l1_pf_addr[`PA_WIDTH-1:0]  = {entry_l1_pf_ppn[`PA_WIDTH-13:0],
                                          entry_l1_pf_va[11:0]};




assign entry_l1_mmu_pe_req      = entry_mmu_pe_req
                                  &&  entry_mmu_pe_req_src[0];

assign entry_l1_mmu_pe_req_set  = entry_l1sm_is_req_mmu
                                  &&  !entry_l1_mmu_pe_req;

assign entry_l1_mmu_pe_req_grnt = entry_mmu_pe_req_grnt
                                  &&  pfu_mmu_pe_req_sel_l1;




assign entry_l1_pf_ppn_up_vld   = entry_l1sm_is_wait_ppn
                                  &&  pfu_get_ppn_vld;





assign entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]  =
                entry_l1_pf_va[`PA_WIDTH-1:0]
                - entry_inst_new_va[`PA_WIDTH-1:0];

assign entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1:0] =
                entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]
                - entry_l1_dist_strideh[`PA_WIDTH-1:0];

assign entry_l1_pf_va_eq_inst_new_va = !(|entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1:0]);

assign entry_inst_new_va_surpass_l1_pf_va_set = (entry_stride_neg ^ entry_l1_pf_va_sub_inst_new_va[`PA_WIDTH-1])
                                                && !entry_l1_pf_va_eq_inst_new_va;

assign entry_in_l1_pf_region_set  = entry_stride_neg ^ entry_l1sm_diff_sub_dist_strideh[`PA_WIDTH-1];




assign entry_l1sm_reinit_req  = entry_l1sm_va_can_cmp
                                &&  entry_inst_new_va_surpass_l1_pf_va;


endmodule