data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:11: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 clock=~clock;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:14: Unsupported: fork statements\n    initial fork \n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:15: Unsupported: Ignoring delay on this delayed statement.\n            #0 reset =1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #10 reset =1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:17: Unsupported: Ignoring delay on this delayed statement.\n            #25 x=1\'b1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #125 x=1\'b0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:19: Unsupported: Ignoring delay on this delayed statement.\n            #525 x=1\'b1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #625 x=1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #700 reset =1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #710 reset =1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #825  x=1\'b1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #1025 x=1\'b0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:26: Unsupported: Ignoring delay on this delayed statement.\n            #1425 x=1\'b1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #1525 x=1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:28: Unsupported: Ignoring delay on this delayed statement.\n            #1725 x=1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:31: Unsupported: Ignoring delay on this delayed statement.\n    initial #2000 $finish;\n            ^\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:34: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("bcd.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_BCD_OPG_Copy.v:35: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Lab3_BCD_OPG_Copy();
    wire z0,z1;
    reg x,clock,reset;
    
    Lab3_BCD_OPG_state_diagram M0(z0, x, clock, reset);
    Lab3_BCD_OPG_structure M1(z1, x, clock, reset);

    initial begin
        clock=1'b0;
        forever #50 clock=~clock;
    end

    initial fork 
            #0 reset =1'b0;
            #10 reset =1'b1;
            #25 x=1'b1; 
            #125 x=1'b0; 
            #525 x=1'b1; 
            #625 x=1'b0;
            
            #700 reset =1'b0;
            #710 reset =1'b1;
            #825  x=1'b1; 
            #1025 x=1'b0; 
            #1425 x=1'b1; 
            #1525 x=1'b0;
            #1725 x=1'b1;
    join

    initial #2000 $finish;

    initial begin
        $dumpfile("bcd.vcd");
        $dumpvars;   
    end

endmodule
module t_Lab3_BCD_OPG_Copy();

    wire z0,z1;
    reg x,clock,reset;
    
    Lab3_BCD_OPG_state_diagram M0(z0, x, clock, reset);
    Lab3_BCD_OPG_structure M1(z1, x, clock, reset);

    initial begin
        clock=1'b0;
        forever #50 clock=~clock;
    end

    initial fork 
            #0 reset =1'b0;
            #10 reset =1'b1;
            #25 x=1'b1; 
            #125 x=1'b0; 
            #525 x=1'b1; 
            #625 x=1'b0;
            
            #700 reset =1'b0;
            #710 reset =1'b1;
            #825  x=1'b1; 
            #1025 x=1'b0; 
            #1425 x=1'b1; 
            #1525 x=1'b0;
            #1725 x=1'b1;
    join

    initial #2000 $finish;

    initial begin
        $dumpfile("bcd.vcd");
        $dumpvars;   
    end

endmodule