data/full_repos/permissive/461249624/sample_project/src/design.v
data/verilator_xmls/93e49d0f-4434-48dd-a839-c2202ab8312e.xml
module mux4a1Bus(
    input [3:0] D0, D1, D2, D3,
    input [1:0] S,
    output reg [3:0] Q);

always @ (*) begin
    case(S)
        2'b00: Q = D0;
        2'b01: Q = D1;
        2'b10: Q = D2;
        2'b11: Q = D3;
    endcase
end

endmodule
module mux4a1Bus(
    input [3:0] D0, D1, D2, D3,
    input [1:0] S,
    output reg [3:0] Q);


always @ (*) begin
    case(S)
        2'b00: Q = D0;
        2'b01: Q = D1;
        2'b10: Q = D2;
        2'b11: Q = D3;
    endcase
end

endmodule