data/full_repos/permissive/41342062/Divisor_Frecuencia.v
1: b"%Error: data/full_repos/permissive/41342062/Divisor_Frecuencia.v:57: Duplicate declaration of signal: 'C_1Hz'\n                                                                   : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg C_1Hz=0;\n     ^~~~~\n        data/full_repos/permissive/41342062/Divisor_Frecuencia.v:53: ... Location of original declaration\n  output  C_1Hz\n          ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module Divisor_Frecuencia (
		input  C_100Mhz,
		output  C_1Hz
	);

	reg[31:0] contador = 0;
	reg C_1Hz=0;
	 
	always @(posedge C_100Mhz)
		begin
				if (contador == 50000000-1)
					begin
					C_1Hz <= ~C_1Hz;
					contador <=0;
					end

				else
					begin
					contador <= contador + 1;
				   end
	  end
endmodule
module Divisor_Frecuencia (
		input  C_100Mhz,
		output  C_1Hz
	);


	reg[31:0] contador = 0;
	reg C_1Hz=0;
	 
	always @(posedge C_100Mhz)
		begin
				if (contador == 50000000-1)
					begin
					C_1Hz <= ~C_1Hz;
					contador <=0;
					end

				else
					begin
					contador <= contador + 1;
				   end
	  end
endmodule