data/full_repos/permissive/513398397/verilog/tb_riscV.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/513398397/verilog/tb_riscV.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #11\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513398397/verilog/tb_riscV.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513398397/verilog/tb_riscV.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #3569\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513398397/verilog/tb_riscV.v:33: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/513398397/verilog/tb_riscV.v:21: Can\'t find definition of \'IMEM\' in dotted scope/variable: \'TEST.IMEM\'\n    $readmemh("../machine code/code2.txt", TEST.IMEM.inst_reg);\n                                                ^~~~\n        ... Known scopes under \'TEST\': <no cells found>\n%Error: data/full_repos/permissive/513398397/verilog/tb_riscV.v:23: Can\'t find definition of \'DATAMEM\' in dotted scope/variable: \'TEST.DATAMEM\'\n    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});\n                           ^~~~~~~\n        ... Known scopes under \'TEST\': <no cells found>\n%Error: data/full_repos/permissive/513398397/verilog/tb_riscV.v:23: Can\'t find definition of \'DATAMEM\' in dotted scope/variable: \'TEST.DATAMEM\'\n    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});\n                                                      ^~~~~~~\n        ... Known scopes under \'TEST\': <no cells found>\n%Error: data/full_repos/permissive/513398397/verilog/tb_riscV.v:23: Can\'t find definition of \'DATAMEM\' in dotted scope/variable: \'TEST.DATAMEM\'\n    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});\n                                                                                 ^~~~~~~\n        ... Known scopes under \'TEST\': <no cells found>\n%Error: data/full_repos/permissive/513398397/verilog/tb_riscV.v:23: Can\'t find definition of \'DATAMEM\' in dotted scope/variable: \'TEST.DATAMEM\'\n    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});\n                                                                                                            ^~~~~~~\n        ... Known scopes under \'TEST\': <no cells found>\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_riscV();

reg clk, rst, inst_wen, enb;
reg [31:0] inst_data;
reg [6:0] inst_addr;
wire [31:0] WB_o;

initial begin
    rst = 1;
    clk = 1;
    enb = 0;
    inst_wen = 0;
    inst_addr = 0;
    inst_data = 0;
    #11
    rst = 0;
    #10
    enb = 1;
    $readmemh("../machine code/code2.txt", TEST.IMEM.inst_reg);
    #3569
    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});



end

riscV32I TEST(
    WB_o, inst_data, inst_addr, clk, rst, inst_wen, enb
);

always #5 clk <= ~clk;

endmodule
module tb_riscV();


reg clk, rst, inst_wen, enb;
reg [31:0] inst_data;
reg [6:0] inst_addr;
wire [31:0] WB_o;

initial begin
    rst = 1;
    clk = 1;
    enb = 0;
    inst_wen = 0;
    inst_addr = 0;
    inst_data = 0;
    #11
    rst = 0;
    #10
    enb = 1;
    $readmemh("../machine code/code2.txt", TEST.IMEM.inst_reg);
    #3569
    $display("%32h", {TEST.DATAMEM.MEM_Data[87], TEST.DATAMEM.MEM_Data[86], TEST.DATAMEM.MEM_Data[85], TEST.DATAMEM.MEM_Data[84]});



end

riscV32I TEST(
    WB_o, inst_data, inst_addr, clk, rst, inst_wen, enb
);

always #5 clk <= ~clk;

endmodule