data/full_repos/permissive/486598419/6.5/Adder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.5/Adder_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.5/Adder_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.5/Adder_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.5/Adder_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.5/Adder_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/486598419/6.5/Adder_tb.v:30: Cannot find file containing module: \'Adder\'\nAdder uut(iData_a,iData_b,iC,oData,oData_C);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.5,data/full_repos/permissive/486598419/Adder\n             data/full_repos/permissive/486598419/6.5,data/full_repos/permissive/486598419/Adder.v\n             data/full_repos/permissive/486598419/6.5,data/full_repos/permissive/486598419/Adder.sv\n             Adder\n             Adder.v\n             Adder.sv\n             obj_dir/Adder\n             obj_dir/Adder.v\n             obj_dir/Adder.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Adder_tb();
    reg[7:0] iData_a;
    reg[7:0] iData_b;
    reg iC;
    wire[7:0] oData;
    wire oData_C;
    
Adder uut(iData_a,iData_b,iC,oData,oData_C);
initial
    begin
    iData_a=8'b00000000;
    iData_b=8'b00000001;
    iC=1;
    #100;
    
    iData_a=8'b11000000;
    iData_b=8'b11000001;
    iC=1;
    #100;
    
    iData_a=8'b11111111;
    iData_b=8'b11111111;
    iC=1;
    #100;
    
    iData_a=8'b11111100;
    iData_b=8'b11111100;
    iC=0;
    #100;
    
    iData_a=8'b01001111;
    iData_b=8'b11111010;
    iC=1;
    #100;
    end
    
endmodule
module Adder_tb();

    reg[7:0] iData_a;
    reg[7:0] iData_b;
    reg iC;
    wire[7:0] oData;
    wire oData_C;
    
Adder uut(iData_a,iData_b,iC,oData,oData_C);
initial
    begin
    iData_a=8'b00000000;
    iData_b=8'b00000001;
    iC=1;
    #100;
    
    iData_a=8'b11000000;
    iData_b=8'b11000001;
    iC=1;
    #100;
    
    iData_a=8'b11111111;
    iData_b=8'b11111111;
    iC=1;
    #100;
    
    iData_a=8'b11111100;
    iData_b=8'b11111100;
    iC=0;
    #100;
    
    iData_a=8'b01001111;
    iData_b=8'b11111010;
    iC=1;
    #100;
    end
    
endmodule