data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:265: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:274: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:278: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:264: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:290: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:299: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:303: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:289: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:322: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 8 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 16 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:326: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b010: mem_out6 = {16\'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:313: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n  if ((core_l15_rqtype == 4\'b0000) & (l15_core_val == 1)) begin\n                       ^~\n%Error: Exiting due to 15 warning(s)\n'
module mem_decode (
	input wire clk,
	input wire nrst,
	input wire [3:0] mem_op4,
	input wire [31:0] op_a4,
	input wire [31:0] op_b4,
	input wire [31:0] S_imm4,
	input wire stall_mem,
	input wire dmem_finished,
	output wire [31:0] addr6,
	output wire [31:0] data_in6,
	output wire [1:0] baddr6,
	output wire gwe6,
	output wire rd6,
	output wire bw06,
	output wire bw16,
	output wire bw26,
	output wire bw36,
	output wire m_op6,
	output wire addr_misaligned6,
	output wire ld_addr_misaligned6,
	output wire samo_addr_misaligned6,
	output wire [3:0] mem_op6
);
	
	reg [3:0] mem_opReg5;
	reg [31:0] op_aReg5;
	reg [31:0] op_bReg5;
	reg [31:0] S_immReg5;
	wire [3:0] mem_op5;
	wire [31:0] op_a5;
	wire [31:0] op_b5;
	wire [31:0] S_imm5;
	wire gwe5;
	wire rd5;
	wire m_op5;
	wire [31:0] addr5;
	reg [31:0] data_in5;
	wire [1:0] addr_mis5;
	wire addr_misaligned5;
	wire ld_addr_misaligned5;
	wire samo_addr_misaligned5;
	wire bw05;
	wire bw15;
	wire bw25;
	wire bw35;
	reg gweReg6;
	reg rdReg6;
	reg m_opReg6;
	reg [3:0] mem_opReg6;
	reg [31:0] addrReg6;
	reg [31:0] data_inReg6;
	reg addr_misalignedReg6;
	reg ld_addr_misalignedReg6;
	reg samo_addr_misalignedReg6;
	reg bw0Reg6;
	reg bw1Reg6;
	reg bw2Reg6;
	reg bw3Reg6;
	wire [31:0] data_out6;
	reg memstallReg;
	wire memstallwire;
	assign memstallwire = (dmem_finished && stall_mem ? 1'b0 : memstallReg);
	always @(posedge clk or negedge nrst)
		if (!nrst) begin
			mem_opReg5 <= 0;
			op_aReg5 <= 0;
			op_bReg5 <= 0;
			S_immReg5 <= 0;
			memstallReg <= 0;
		end
		else begin
			if (stall_mem && ~memstallwire) begin
				mem_opReg5 <= mem_op4;
				op_aReg5 <= op_a4;
				op_bReg5 <= op_b4;
				S_immReg5 <= S_imm4;
			end
			else if ((stall_mem && memstallwire) && memstallReg) begin
				mem_opReg5 <= mem_opReg5;
				op_aReg5 <= op_aReg5;
				op_bReg5 <= op_bReg5;
				S_immReg5 <= S_immReg5;
			end
			else begin
				mem_opReg5 <= mem_op4;
				op_aReg5 <= op_a4;
				op_bReg5 <= op_b4;
				S_immReg5 <= S_imm4;
			end
			if (stall_mem)
				memstallReg <= 1;
			if (dmem_finished)
				memstallReg <= 0;
		end
	always @(posedge clk or negedge nrst)
		if (!nrst) begin
			gweReg6 <= 0;
			rdReg6 <= 0;
			mem_opReg6 <= 0;
			addrReg6 <= 0;
			data_inReg6 <= 0;
			addr_misalignedReg6 <= 0;
			ld_addr_misalignedReg6 <= 0;
			samo_addr_misalignedReg6 <= 0;
			bw0Reg6 <= 0;
			bw1Reg6 <= 0;
			bw2Reg6 <= 0;
			bw3Reg6 <= 0;
			m_opReg6 <= 0;
		end
		else begin
			gweReg6 <= gwe5;
			rdReg6 <= rd5;
			mem_opReg6 <= mem_op5;
			addrReg6 <= addr5;
			data_inReg6 <= data_in5;
			addr_misalignedReg6 <= addr_misaligned5;
			ld_addr_misalignedReg6 <= ld_addr_misaligned5;
			samo_addr_misalignedReg6 <= samo_addr_misaligned5;
			bw0Reg6 <= bw05;
			bw1Reg6 <= bw15;
			bw2Reg6 <= bw25;
			bw3Reg6 <= bw35;
			m_opReg6 <= m_op5;
		end
	assign mem_op5 = mem_opReg5;
	assign op_a5 = op_aReg5;
	assign op_b5 = op_bReg5;
	assign S_imm5 = S_immReg5;
	assign addr5 = (mem_op5[3] ? S_imm5 + op_a5 : op_b5 + op_a5);
	assign m_op5 = |mem_op5;
	assign addr_mis5[0] = mem_op5[1] & addr5[0];
	assign addr_mis5[1] = (mem_op5[1] & mem_op5[2]) & addr5[1];
	assign addr_misaligned5 = addr_mis5[0] | addr_mis5[1];
	assign ld_addr_misaligned5 = addr_misaligned5 & ~mem_op5[3];
	assign samo_addr_misaligned5 = addr_misaligned5 & mem_op5[3];
	assign gwe5 = &mem_op5 & ~addr_misaligned5;
	assign rd5 = !mem_op5[3] & ~addr_misaligned5;
	assign bw05 = (((~addr5[1] & ~addr5[0]) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw25 = (((addr5[1] & ~addr5[0]) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw15 = (((~addr5[1] & ((addr5[0] & mem_op5[2]) | (~addr5[0] & mem_op5[1]))) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw35 = (((addr5[1] & ((addr5[0] & mem_op5[2]) | (~addr5[0] & mem_op5[1]))) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	always @(*)
		case (mem_op5[2:1])
			2'b11: data_in5 = op_b5;
			2'b01: data_in5 = {op_b5[15:0], op_b5[15:0]};
			2'b10: data_in5 = {op_b5[7:0], op_b5[7:0], op_b5[7:0], op_b5[7:0]};
			default: data_in5 = op_b5;
		endcase
	assign gwe6 = gweReg6;
	assign rd6 = rdReg6;
	assign mem_op6 = mem_opReg6;
	assign addr6 = addrReg6;
	assign data_in6 = data_inReg6;
	assign addr_misaligned6 = addr_misalignedReg6;
	assign ld_addr_misaligned6 = ld_addr_misalignedReg6;
	assign samo_addr_misaligned6 = samo_addr_misalignedReg6;
	assign bw06 = bw0Reg6;
	assign bw16 = bw1Reg6;
	assign bw26 = bw2Reg6;
	assign bw36 = bw3Reg6;
	assign m_op6 = m_opReg6;
endmodule
module mem_decode (
	input wire clk,
	input wire nrst,
	input wire [3:0] mem_op4,
	input wire [31:0] op_a4,
	input wire [31:0] op_b4,
	input wire [31:0] S_imm4,
	input wire stall_mem,
	input wire dmem_finished,
	output wire [31:0] addr6,
	output wire [31:0] data_in6,
	output wire [1:0] baddr6,
	output wire gwe6,
	output wire rd6,
	output wire bw06,
	output wire bw16,
	output wire bw26,
	output wire bw36,
	output wire m_op6,
	output wire addr_misaligned6,
	output wire ld_addr_misaligned6,
	output wire samo_addr_misaligned6,
	output wire [3:0] mem_op6
);

	
	reg [3:0] mem_opReg5;
	reg [31:0] op_aReg5;
	reg [31:0] op_bReg5;
	reg [31:0] S_immReg5;
	wire [3:0] mem_op5;
	wire [31:0] op_a5;
	wire [31:0] op_b5;
	wire [31:0] S_imm5;
	wire gwe5;
	wire rd5;
	wire m_op5;
	wire [31:0] addr5;
	reg [31:0] data_in5;
	wire [1:0] addr_mis5;
	wire addr_misaligned5;
	wire ld_addr_misaligned5;
	wire samo_addr_misaligned5;
	wire bw05;
	wire bw15;
	wire bw25;
	wire bw35;
	reg gweReg6;
	reg rdReg6;
	reg m_opReg6;
	reg [3:0] mem_opReg6;
	reg [31:0] addrReg6;
	reg [31:0] data_inReg6;
	reg addr_misalignedReg6;
	reg ld_addr_misalignedReg6;
	reg samo_addr_misalignedReg6;
	reg bw0Reg6;
	reg bw1Reg6;
	reg bw2Reg6;
	reg bw3Reg6;
	wire [31:0] data_out6;
	reg memstallReg;
	wire memstallwire;
	assign memstallwire = (dmem_finished && stall_mem ? 1'b0 : memstallReg);
	always @(posedge clk or negedge nrst)
		if (!nrst) begin
			mem_opReg5 <= 0;
			op_aReg5 <= 0;
			op_bReg5 <= 0;
			S_immReg5 <= 0;
			memstallReg <= 0;
		end
		else begin
			if (stall_mem && ~memstallwire) begin
				mem_opReg5 <= mem_op4;
				op_aReg5 <= op_a4;
				op_bReg5 <= op_b4;
				S_immReg5 <= S_imm4;
			end
			else if ((stall_mem && memstallwire) && memstallReg) begin
				mem_opReg5 <= mem_opReg5;
				op_aReg5 <= op_aReg5;
				op_bReg5 <= op_bReg5;
				S_immReg5 <= S_immReg5;
			end
			else begin
				mem_opReg5 <= mem_op4;
				op_aReg5 <= op_a4;
				op_bReg5 <= op_b4;
				S_immReg5 <= S_imm4;
			end
			if (stall_mem)
				memstallReg <= 1;
			if (dmem_finished)
				memstallReg <= 0;
		end
	always @(posedge clk or negedge nrst)
		if (!nrst) begin
			gweReg6 <= 0;
			rdReg6 <= 0;
			mem_opReg6 <= 0;
			addrReg6 <= 0;
			data_inReg6 <= 0;
			addr_misalignedReg6 <= 0;
			ld_addr_misalignedReg6 <= 0;
			samo_addr_misalignedReg6 <= 0;
			bw0Reg6 <= 0;
			bw1Reg6 <= 0;
			bw2Reg6 <= 0;
			bw3Reg6 <= 0;
			m_opReg6 <= 0;
		end
		else begin
			gweReg6 <= gwe5;
			rdReg6 <= rd5;
			mem_opReg6 <= mem_op5;
			addrReg6 <= addr5;
			data_inReg6 <= data_in5;
			addr_misalignedReg6 <= addr_misaligned5;
			ld_addr_misalignedReg6 <= ld_addr_misaligned5;
			samo_addr_misalignedReg6 <= samo_addr_misaligned5;
			bw0Reg6 <= bw05;
			bw1Reg6 <= bw15;
			bw2Reg6 <= bw25;
			bw3Reg6 <= bw35;
			m_opReg6 <= m_op5;
		end
	assign mem_op5 = mem_opReg5;
	assign op_a5 = op_aReg5;
	assign op_b5 = op_bReg5;
	assign S_imm5 = S_immReg5;
	assign addr5 = (mem_op5[3] ? S_imm5 + op_a5 : op_b5 + op_a5);
	assign m_op5 = |mem_op5;
	assign addr_mis5[0] = mem_op5[1] & addr5[0];
	assign addr_mis5[1] = (mem_op5[1] & mem_op5[2]) & addr5[1];
	assign addr_misaligned5 = addr_mis5[0] | addr_mis5[1];
	assign ld_addr_misaligned5 = addr_misaligned5 & ~mem_op5[3];
	assign samo_addr_misaligned5 = addr_misaligned5 & mem_op5[3];
	assign gwe5 = &mem_op5 & ~addr_misaligned5;
	assign rd5 = !mem_op5[3] & ~addr_misaligned5;
	assign bw05 = (((~addr5[1] & ~addr5[0]) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw25 = (((addr5[1] & ~addr5[0]) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw15 = (((~addr5[1] & ((addr5[0] & mem_op5[2]) | (~addr5[0] & mem_op5[1]))) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	assign bw35 = (((addr5[1] & ((addr5[0] & mem_op5[2]) | (~addr5[0] & mem_op5[1]))) & mem_op5[3]) & ~addr_misaligned5) | gwe5;
	always @(*)
		case (mem_op5[2:1])
			2'b11: data_in5 = op_b5;
			2'b01: data_in5 = {op_b5[15:0], op_b5[15:0]};
			2'b10: data_in5 = {op_b5[7:0], op_b5[7:0], op_b5[7:0], op_b5[7:0]};
			default: data_in5 = op_b5;
		endcase
	assign gwe6 = gweReg6;
	assign rd6 = rdReg6;
	assign mem_op6 = mem_opReg6;
	assign addr6 = addrReg6;
	assign data_in6 = data_inReg6;
	assign addr_misaligned6 = addr_misalignedReg6;
	assign ld_addr_misaligned6 = ld_addr_misalignedReg6;
	assign samo_addr_misaligned6 = samo_addr_misalignedReg6;
	assign bw06 = bw0Reg6;
	assign bw16 = bw1Reg6;
	assign bw26 = bw2Reg6;
	assign bw36 = bw3Reg6;
	assign m_op6 = m_opReg6;
endmodule