data/full_repos/permissive/444327372/controller.v
1: b"%Error: data/full_repos/permissive/444327372/controller.v:72: Cannot find file containing module: 'maindec'\n maindec md(.instr(instrD),\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/maindec\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/maindec.v\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/maindec.sv\n             maindec\n             maindec.v\n             maindec.sv\n             obj_dir/maindec\n             obj_dir/maindec.v\n             obj_dir/maindec.sv\n%Error: data/full_repos/permissive/444327372/controller.v:96: Cannot find file containing module: 'aludec'\n aludec ad(.instr(instrD),\n ^~~~~~\n%Error: data/full_repos/permissive/444327372/controller.v:103: Cannot find file containing module: 'flopenrc'\n flopenrc #(21) regE(\n ^~~~~~~~\n%Error: data/full_repos/permissive/444327372/controller.v:123: Cannot find file containing module: 'flopr'\n flopr #(15) regM(\n ^~~~~\n%Error: data/full_repos/permissive/444327372/controller.v:133: Cannot find file containing module: 'flopr'\n flopr #(8) regW(\n ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module controller(
	input wire clk,rst,

	input wire[31:0] instrD,
	
	input wire stallD,
	input wire stallE,



	input wire[5:0] opD,functD,
	input wire equalD,
	output wire pcsrcD, 
	output wire branchD, jumpD, jalD, jrD, balD,
	

	input wire flushE,
	output wire memtoregE,alusrcE,
	output wire regdstE,regwriteE,	
	output wire[7:0] alucontrolE,
	output wire hi_weE,
	output wire lo_weE,
	output wire div_validE, signed_divE,
	output wire jalE, jrE, balE,


	output wire memtoregM,memwriteM,
				regwriteM,
	output wire [7:0]alucontrolM,
	output wire memenM,

	output wire memtoregW,regwriteW

    );
	

	wire memtoregD,memwriteD,alusrcD,
		regdstD,regwriteD;
	wire[7:0] alucontrolD;
	wire hi_weD;
	wire lo_weD;

	wire memenD;
	

	wire memwriteE;
	wire memenE;


	maindec md(.instr(instrD),
			   .stallD(stallD),
			   .memtoreg(memtoregD),
			   .memwrite(memwriteD),
			   .memen(memenD),
			   
			   .alusrc(alusrcD),
			   .regdst(regdstD),
			   .regwrite(regwriteD),
			   

			   .branch(branchD),
			   .jump(jumpD),
			   .jal(jalD),
			   .jr(jrD),
			   .bal(balD),
			   
			   .hi_we(hi_weD),
			   .lo_we(lo_weD),
			   
			   .div_valid(div_validD),
			   .signed_div(signed_divD)
			   );

	aludec ad(.instr(instrD),
			  .stallD(stallD),
			  .alucontrol(alucontrolD));

	assign pcsrcD = branchD & equalD;


	flopenrc #(21) regE(
		.clk(clk),
		.rst(rst),
		.en(~stallE),
		.clear(flushE),
		.d({memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD, 
			hi_weD, lo_weD,
			div_validD,signed_divD,
			jalD, jrD, balD,
			memenD
			}),
		.q({memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE, 
			hi_weE, lo_weE,
			div_validE, signed_divE,
			jalE, jrE, balE,
			memenE
			})
	);


	flopr #(15) regM(
		clk,rst,
		{memtoregE,memwriteE,regwriteE,
		 alucontrolE,
		 memenE},
		{memtoregM,memwriteM,regwriteM,
		 alucontrolM,
		 memenM}
		);

	flopr #(8) regW(
		clk,rst,
		{memtoregM,regwriteM},
		{memtoregW,regwriteW}
		);
endmodule
module controller(
	input wire clk,rst,

	input wire[31:0] instrD,
	
	input wire stallD,
	input wire stallE,



	input wire[5:0] opD,functD,
	input wire equalD,
	output wire pcsrcD, 
	output wire branchD, jumpD, jalD, jrD, balD,
	

	input wire flushE,
	output wire memtoregE,alusrcE,
	output wire regdstE,regwriteE,	
	output wire[7:0] alucontrolE,
	output wire hi_weE,
	output wire lo_weE,
	output wire div_validE, signed_divE,
	output wire jalE, jrE, balE,


	output wire memtoregM,memwriteM,
				regwriteM,
	output wire [7:0]alucontrolM,
	output wire memenM,

	output wire memtoregW,regwriteW

    );

	

	wire memtoregD,memwriteD,alusrcD,
		regdstD,regwriteD;
	wire[7:0] alucontrolD;
	wire hi_weD;
	wire lo_weD;

	wire memenD;
	

	wire memwriteE;
	wire memenE;


	maindec md(.instr(instrD),
			   .stallD(stallD),
			   .memtoreg(memtoregD),
			   .memwrite(memwriteD),
			   .memen(memenD),
			   
			   .alusrc(alusrcD),
			   .regdst(regdstD),
			   .regwrite(regwriteD),
			   

			   .branch(branchD),
			   .jump(jumpD),
			   .jal(jalD),
			   .jr(jrD),
			   .bal(balD),
			   
			   .hi_we(hi_weD),
			   .lo_we(lo_weD),
			   
			   .div_valid(div_validD),
			   .signed_div(signed_divD)
			   );

	aludec ad(.instr(instrD),
			  .stallD(stallD),
			  .alucontrol(alucontrolD));

	assign pcsrcD = branchD & equalD;


	flopenrc #(21) regE(
		.clk(clk),
		.rst(rst),
		.en(~stallE),
		.clear(flushE),
		.d({memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD, 
			hi_weD, lo_weD,
			div_validD,signed_divD,
			jalD, jrD, balD,
			memenD
			}),
		.q({memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE, 
			hi_weE, lo_weE,
			div_validE, signed_divE,
			jalE, jrE, balE,
			memenE
			})
	);


	flopr #(15) regM(
		clk,rst,
		{memtoregE,memwriteE,regwriteE,
		 alucontrolE,
		 memenE},
		{memtoregM,memwriteM,regwriteM,
		 alucontrolM,
		 memenM}
		);

	flopr #(8) regW(
		clk,rst,
		{memtoregM,regwriteM},
		{memtoregW,regwriteW}
		);
endmodule