data/full_repos/permissive/439731184/ft.v
1: b'%Error: data/full_repos/permissive/439731184/ft.v:196: Unsupported or unknown PLI call: $urandom\n    i1 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:197: Unsupported or unknown PLI call: $urandom\n    i2 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:198: Unsupported or unknown PLI call: $urandom\n    i3 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:199: Unsupported or unknown PLI call: $urandom\n    i4 = $urandom;\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:195: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/ft.v:204: Unsupported or unknown PLI call: $monitor\n    $monitor("(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ft4 #(parameter N_BITS = 4) (i1, i2, i3, i4, 
                                    o1, o2, o3, o4);

input [2*N_BITS-1:0] i1, i2, i3, i4;
output [2*N_BITS+3:0] o1, o2, o3, o4;


wire[N_BITS:0] t1;
wire[N_BITS:0] t2;
add #(N_BITS) A1 (i1[2*N_BITS-1:N_BITS], i3[2*N_BITS-1:N_BITS], t1);
add #(N_BITS) A2 (i2[2*N_BITS-1:N_BITS], i4[2*N_BITS-1:N_BITS], t2);
add #(N_BITS+1) A3 (t1, t2, o1[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t3;
wire[N_BITS:0] t4;
add #(N_BITS) A4 (i1[N_BITS-1:0], i3[N_BITS-1:0], t3);
add #(N_BITS) A5 (i2[N_BITS-1:0], i4[N_BITS-1:0], t4);
add #(N_BITS+1) A6 (t3, t4, o1[N_BITS+1:0]);


wire[N_BITS:0] t5;
wire[N_BITS:0] t6;
add #(N_BITS) A7 (i1[2*N_BITS-1:N_BITS], i3[2*N_BITS-1:N_BITS], t5);
add #(N_BITS) A8 (i2[2*N_BITS-1:N_BITS], i4[2*N_BITS-1:N_BITS], t6);
sub #(N_BITS+1) S1 (t5, t6, o3[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t7;
wire[N_BITS:0] t8;
add #(N_BITS) A9 (i1[N_BITS-1:0], i3[N_BITS-1:0], t7);
add #(N_BITS) A10 (i2[N_BITS-1:0], i4[N_BITS-1:0], t8);
sub #(N_BITS+1) S2 (t7, t8, o3[N_BITS+1:0]);


wire[N_BITS:0] t9;
wire[N_BITS:0] t10;
add #(N_BITS) A11 (i1[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], t9);
add #(N_BITS) A12 (i3[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], t10);
sub #(N_BITS+1) S3 (t9, t10, o2[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t11;
wire[N_BITS:0] t12;
add #(N_BITS) A13 (i1[N_BITS-1:0], i2[2*N_BITS-1:N_BITS], t11);
add #(N_BITS) A14 (i3[N_BITS-1:0], i4[2*N_BITS-1:N_BITS], t12);
sub #(N_BITS+1) S4 (t11, t12, o2[N_BITS+1:0]);


wire[N_BITS:0] t13;
wire[N_BITS:0] t14;
add #(N_BITS) A15 (i1[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], t13);
add #(N_BITS) A16 (i3[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], t14);
sub #(N_BITS+1) S5 (t13, t14, o4[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t15;
wire[N_BITS:0] t16;
add #(N_BITS) A17 (i1[N_BITS-1:0], i4[2*N_BITS-1:N_BITS], t15);
add #(N_BITS) A18 (i3[N_BITS-1:0], i2[2*N_BITS-1:N_BITS], t16);
sub #(N_BITS+1) S6 (t15, t16, o4[N_BITS+1:0]);

endmodule
module ft4 #(parameter N_BITS = 4) (i1, i2, i3, i4, 
                                    o1, o2, o3, o4);


input [2*N_BITS-1:0] i1, i2, i3, i4;
output [2*N_BITS+3:0] o1, o2, o3, o4;


wire[N_BITS:0] t1;
wire[N_BITS:0] t2;
add #(N_BITS) A1 (i1[2*N_BITS-1:N_BITS], i3[2*N_BITS-1:N_BITS], t1);
add #(N_BITS) A2 (i2[2*N_BITS-1:N_BITS], i4[2*N_BITS-1:N_BITS], t2);
add #(N_BITS+1) A3 (t1, t2, o1[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t3;
wire[N_BITS:0] t4;
add #(N_BITS) A4 (i1[N_BITS-1:0], i3[N_BITS-1:0], t3);
add #(N_BITS) A5 (i2[N_BITS-1:0], i4[N_BITS-1:0], t4);
add #(N_BITS+1) A6 (t3, t4, o1[N_BITS+1:0]);


wire[N_BITS:0] t5;
wire[N_BITS:0] t6;
add #(N_BITS) A7 (i1[2*N_BITS-1:N_BITS], i3[2*N_BITS-1:N_BITS], t5);
add #(N_BITS) A8 (i2[2*N_BITS-1:N_BITS], i4[2*N_BITS-1:N_BITS], t6);
sub #(N_BITS+1) S1 (t5, t6, o3[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t7;
wire[N_BITS:0] t8;
add #(N_BITS) A9 (i1[N_BITS-1:0], i3[N_BITS-1:0], t7);
add #(N_BITS) A10 (i2[N_BITS-1:0], i4[N_BITS-1:0], t8);
sub #(N_BITS+1) S2 (t7, t8, o3[N_BITS+1:0]);


wire[N_BITS:0] t9;
wire[N_BITS:0] t10;
add #(N_BITS) A11 (i1[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], t9);
add #(N_BITS) A12 (i3[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], t10);
sub #(N_BITS+1) S3 (t9, t10, o2[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t11;
wire[N_BITS:0] t12;
add #(N_BITS) A13 (i1[N_BITS-1:0], i2[2*N_BITS-1:N_BITS], t11);
add #(N_BITS) A14 (i3[N_BITS-1:0], i4[2*N_BITS-1:N_BITS], t12);
sub #(N_BITS+1) S4 (t11, t12, o2[N_BITS+1:0]);


wire[N_BITS:0] t13;
wire[N_BITS:0] t14;
add #(N_BITS) A15 (i1[2*N_BITS-1:N_BITS], i2[N_BITS-1:0], t13);
add #(N_BITS) A16 (i3[2*N_BITS-1:N_BITS], i4[N_BITS-1:0], t14);
sub #(N_BITS+1) S5 (t13, t14, o4[2*N_BITS+3:N_BITS+2]);


wire[N_BITS:0] t15;
wire[N_BITS:0] t16;
add #(N_BITS) A17 (i1[N_BITS-1:0], i4[2*N_BITS-1:N_BITS], t15);
add #(N_BITS) A18 (i3[N_BITS-1:0], i2[2*N_BITS-1:N_BITS], t16);
sub #(N_BITS+1) S6 (t15, t16, o4[N_BITS+1:0]);

endmodule