data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #2.5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:58: Unsupported: fork statements\n  fork begin\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #0 clk = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #1000 nrst <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #1000 start <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 start <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:78: Unsupported: Ignoring delay on this delayed statement.\n   #10 start <= 1\'b0;\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:80: syntax error, unexpected \'@\'\n   @(!busy)begin\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10 start <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #10 start <= 1\'b0;\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:94: syntax error, unexpected \'@\'\n   @(!busy)begin\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:104: syntax error, unexpected end, expecting join or join_any or join_none\n   end\n   ^~~\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_wr.v:118: syntax error, unexpected end, expecting join or join_any or join_none\n   end\n   ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_usb_pd_phy_wr;

	reg		clk;
	reg		nrst;
	reg		start;
	reg		hdr_sop_hrst;
	
	reg		[31 : 0]	tx_word;
	reg		[3 : 0]		tx_type;
	reg		[2 : 0]		tx_num;
	
	wire	dout;
	wire	busy;
	
	usb_pd_phy_wr#(
		.system_khz(200000)
	)DUT(
		.nrst		(nrst),
		.clock		(clk),
		
		.hdr_sop_hrst	(hdr_sop_hrst),
		.start			(start),
		.busy			(busy),
		
		.send_num	(tx_num),
		.send_type	(tx_type),
		
		.send_word0	(tx_word),
		.send_word1	(32'd0),
		.send_word2	(32'd0),
		.send_word3	(32'd0),
		.send_word4	(32'd0),
		.send_word5	(32'd0),
		.send_word6	(32'd0),
		
		.bmc_dout	(dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			start = 1'b0;
			hdr_sop_hrst = 1'b0;
			
			tx_word = 32'd0;
			tx_type = 4'hD;
			tx_num = 3'd0;
			
			#1000 nrst <= 1'b1;
			
			#1000 start <= 1'b0;
			hdr_sop_hrst = 1'b1;
			
			if(!busy)begin
				#10 start <= 1'b1;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'd0;
				tx_type = 4'hD;
				tx_num = 3'd0;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'd0;
				tx_type = 4'h1;
				tx_num = 3'd0;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'h3104_B12C;
				tx_type = 4'h2;
				tx_num = 3'd1;
			end
			
			#10 start <= 1'b0;
			
		end join
	end
	
endmodule
module tb_usb_pd_phy_wr;


	reg		clk;
	reg		nrst;
	reg		start;
	reg		hdr_sop_hrst;
	
	reg		[31 : 0]	tx_word;
	reg		[3 : 0]		tx_type;
	reg		[2 : 0]		tx_num;
	
	wire	dout;
	wire	busy;
	
	usb_pd_phy_wr#(
		.system_khz(200000)
	)DUT(
		.nrst		(nrst),
		.clock		(clk),
		
		.hdr_sop_hrst	(hdr_sop_hrst),
		.start			(start),
		.busy			(busy),
		
		.send_num	(tx_num),
		.send_type	(tx_type),
		
		.send_word0	(tx_word),
		.send_word1	(32'd0),
		.send_word2	(32'd0),
		.send_word3	(32'd0),
		.send_word4	(32'd0),
		.send_word5	(32'd0),
		.send_word6	(32'd0),
		
		.bmc_dout	(dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			start = 1'b0;
			hdr_sop_hrst = 1'b0;
			
			tx_word = 32'd0;
			tx_type = 4'hD;
			tx_num = 3'd0;
			
			#1000 nrst <= 1'b1;
			
			#1000 start <= 1'b0;
			hdr_sop_hrst = 1'b1;
			
			if(!busy)begin
				#10 start <= 1'b1;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'd0;
				tx_type = 4'hD;
				tx_num = 3'd0;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'd0;
				tx_type = 4'h1;
				tx_num = 3'd0;
			end
			
			#10 start <= 1'b0;
			
			@(!busy)begin
				#30000 start <= 1'b0;
			end
			
			if(!busy)begin
				#10 start <= 1'b1;
				hdr_sop_hrst <= 1'b0;
				tx_word = 32'h3104_B12C;
				tx_type = 4'h2;
				tx_num = 3'd1;
			end
			
			#10 start <= 1'b0;
			
		end join
	end
	
endmodule