data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/01_Latches_and_Flip-Flops/10_DFF+gate.v
data/verilator_xmls/75a76455-0d82-40c1-9812-94b4d9b0192d.xml
module top_module (
    input clk,
    input in, 
    output reg out
);
    
    always @(posedge clk) begin
        out <= in ^ out;
    end

endmodule
module top_module (
    input clk,
    input in, 
    output reg out
);

    
    always @(posedge clk) begin
        out <= in ^ out;
    end

endmodule