data/full_repos/permissive/42434302/ivltests/pr2202846c.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (result != 1) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (result != 1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (result != 2) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (result != 3) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (result != 4) begin\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:12: Extracting 6 bits from only 2 bit number\n                                                                    : ... In instance top\n     expr[11:6]           : result = 4;\n         ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2202846c.v:12: Selection index out of range: 10:5 outside 2:1\n                                                                               : ... In instance top\n     expr[11:6]           : result = 4;\n         ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg [5:0] cond;
  reg [2:1] expr;
  integer result;

  always @(cond or expr) begin
    casex (cond)
     6'b01_??10           : result = 1;
     {2'b10, 4'b??10}     : result = 2;
     {expr[1:0], 4'b??01} : result = 3;
     expr[11:6]           : result = 4;
     default              : result = 0;
   endcase
  end

  initial begin
    pass = 1'b1;

    expr = 2'b10;
    cond = 6'b01_xx10;
    #1 if (result != 1) begin
      $display("Failed case expr 1 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'bxx_xxxx;
    #1 if (result != 1) begin
      $display("Failed case expr 1a test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b10_zz10;
    #1 if (result != 2) begin
      $display("Failed case expr 2 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b0x_zz01;
    #1 if (result != 3) begin
      $display("Failed case expr 3 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b11_1111;
    #1 if (result != 4) begin
      $display("Failed case expr 1a test, got expr %0d", result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [5:0] cond;
  reg [2:1] expr;
  integer result;

  always @(cond or expr) begin
    casex (cond)
     6'b01_??10           : result = 1;
     {2'b10, 4'b??10}     : result = 2;
     {expr[1:0], 4'b??01} : result = 3;
     expr[11:6]           : result = 4;
     default              : result = 0;
   endcase
  end

  initial begin
    pass = 1'b1;

    expr = 2'b10;
    cond = 6'b01_xx10;
    #1 if (result != 1) begin
      $display("Failed case expr 1 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'bxx_xxxx;
    #1 if (result != 1) begin
      $display("Failed case expr 1a test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b10_zz10;
    #1 if (result != 2) begin
      $display("Failed case expr 2 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b0x_zz01;
    #1 if (result != 3) begin
      $display("Failed case expr 3 test, got expr %0d", result);
      pass = 1'b0;
    end

    cond = 6'b11_1111;
    #1 if (result != 4) begin
      $display("Failed case expr 1a test, got expr %0d", result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule