data/full_repos/permissive/481307378/source_files/FullAdder/fa.v
data/verilator_xmls/31b23203-ae57-408e-b59a-8b23a6e35bb3.xml
module fa(input a, input b, input c_in, output s, output c_out);

assign s = a ^ b ^ c_in;
assign c_out = ((a ^ b) & c_in) | (a & b);
endmodule
module fa(input a, input b, input c_in, output s, output c_out);


assign s = a ^ b ^ c_in;
assign c_out = ((a ^ b) & c_in) | (a & b);
endmodule