data/full_repos/permissive/463204869/units/util/source/rtl/verilog/util_clkgate.v
data/verilator_xmls/93cabd8f-95b8-48a1-9f7a-2e188e1b6b86.xml
module util_clkgate #(
    parameter DELAY = 0.1
)(
    input  wire clk_i,
    input  wire en_i,
    input  wire testmode_i,
    output wire clk_o
);

`ifdef XILINX

    BUFGCE clkgate_bufgce (
       .I  (clk_i),
       .CE (en_i | testmode_i),
       .O  (clk_o)
    );

`else

    reg  int_clk;
    wire int_en;

    assign

        #DELAY

        int_en = en_i | testmode_i;

    always @(clk_i or int_en) begin
        if (clk_i == 1'b0) begin
            int_clk <= int_en;
        end
    end

    assign clk_o = int_clk & clk_i;

`endif

endmodule
module util_clkgate #(
    parameter DELAY = 0.1
)(
    input  wire clk_i,
    input  wire en_i,
    input  wire testmode_i,
    output wire clk_o
);


`ifdef XILINX

    BUFGCE clkgate_bufgce (
       .I  (clk_i),
       .CE (en_i | testmode_i),
       .O  (clk_o)
    );

`else

    reg  int_clk;
    wire int_en;

    assign

        #DELAY

        int_en = en_i | testmode_i;

    always @(clk_i or int_en) begin
        if (clk_i == 1'b0) begin
            int_clk <= int_en;
        end
    end

    assign clk_o = int_clk & clk_i;

`endif

endmodule