data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:39: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("gpio.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:40: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(5, gpio_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:44: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:78: Unsupported: wait statements\n  wait(checkbits_hi == 8\'hA0);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:80: Unsupported: wait statements\n  wait(checkbits_hi == 8\'h0B);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:82: Unsupported: wait statements\n  wait(checkbits_hi == 8\'hAB);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:84: syntax error, unexpected \'@\'\n  repeat (3000) @(posedge clock);\n                ^\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:86: syntax error, unexpected \'@\'\n  repeat (3000) @(posedge clock);\n                ^\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:92: Unsupported: wait statements\n  wait(checkbits_hi == 8\'hA0);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:93: Unsupported: wait statements\n  wait(checkbits[7:0]  == 8\'hF0);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:94: Unsupported: wait statements\n  wait(checkbits_hi == 8\'h0B);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:95: Unsupported: wait statements\n  wait(checkbits[7:0]  == 8\'h0F);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:96: Unsupported: wait statements\n  wait(checkbits_hi == 8\'hAB);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:97: Unsupported: wait statements\n  wait(checkbits[7:0]  == 8\'h00);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:98: Unsupported: wait statements\n  wait(checkbits_hi == 8\'h01);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:99: Unsupported: wait statements\n  wait(checkbits[7:0]  == 8\'h01);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:100: Unsupported: wait statements\n  wait(checkbits_hi == 8\'h02);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:101: Unsupported: wait statements\n  wait(checkbits[7:0]  == 8\'h03);\n  ^~~~\n%Error: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:102: Unsupported: wait statements\n  wait(checkbits_hi == 8\'h04);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("GPIO state = %b (%d - %d)", checkbits,\n  ^\n%Error: Exiting due to 19 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gpio_tb;

	reg clock;
	reg power1;

	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock <= 0;
	end

	initial begin
		$dumpfile("gpio.vcd");
		$dumpvars(5, gpio_tb);


		repeat (50) begin
			repeat (1000) @(posedge clock);
			$display("+1000 cycles");
		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	wire [37:0] mprj_io;
	wire [15:0] checkbits;
	reg  [7:0] checkbits_lo;
	wire [7:0] checkbits_hi;

	assign mprj_io[23:16] = checkbits_lo;
	assign checkbits = mprj_io[31:16];
	assign checkbits_hi = checkbits[15:8];
	assign mprj_io[3] = 1'b1;

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire gpio;

	reg RSTB;


	initial begin
		checkbits_lo <= {8{1'bz}};
		wait(checkbits_hi == 8'hA0);
		checkbits_lo <= 8'hF0;
		wait(checkbits_hi == 8'h0B);
		checkbits_lo <= 8'h0F;
		wait(checkbits_hi == 8'hAB);
		checkbits_lo <= 8'h0;
		repeat (3000) @(posedge clock);
		checkbits_lo <= 8'h1;
		repeat (3000) @(posedge clock);
		checkbits_lo <= 8'h3;
	end


	initial begin
		wait(checkbits_hi == 8'hA0);
		wait(checkbits[7:0]  == 8'hF0);
		wait(checkbits_hi == 8'h0B);
		wait(checkbits[7:0]  == 8'h0F);
		wait(checkbits_hi == 8'hAB);
		wait(checkbits[7:0]  == 8'h00);
		wait(checkbits_hi == 8'h01);
		wait(checkbits[7:0]  == 8'h01);
		wait(checkbits_hi == 8'h02);
		wait(checkbits[7:0]  == 8'h03);
		wait(checkbits_hi == 8'h04);
		`ifdef GL
			$display("Monitor: Test GPIO (GL) Passed");
		`else
			$display("Monitor: Test GPIO (RTL) Passed");
		`endif
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		
		#1000;
		RSTB <= 1'b1;
		#2000;
	end

	initial begin
		power1 <= 1'b0;
		#200;
		power1 <= 1'b1;
	end
		

	always @(checkbits) begin
		#1 $display("GPIO state = %b (%d - %d)", checkbits,
				checkbits_hi, checkbits_lo);
	end

	wire VDD;
	wire VSS;

	assign VDD = power1;
	assign VSS = 1'b0;













	caravel uut (
		.VDD 	  (VDD),
		.VSS	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("gpio.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module gpio_tb;


	reg clock;
	reg power1;

	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock <= 0;
	end

	initial begin
		$dumpfile("gpio.vcd");
		$dumpvars(5, gpio_tb);


		repeat (50) begin
			repeat (1000) @(posedge clock);
			$display("+1000 cycles");
		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	wire [37:0] mprj_io;
	wire [15:0] checkbits;
	reg  [7:0] checkbits_lo;
	wire [7:0] checkbits_hi;

	assign mprj_io[23:16] = checkbits_lo;
	assign checkbits = mprj_io[31:16];
	assign checkbits_hi = checkbits[15:8];
	assign mprj_io[3] = 1'b1;

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire gpio;

	reg RSTB;


	initial begin
		checkbits_lo <= {8{1'bz}};
		wait(checkbits_hi == 8'hA0);
		checkbits_lo <= 8'hF0;
		wait(checkbits_hi == 8'h0B);
		checkbits_lo <= 8'h0F;
		wait(checkbits_hi == 8'hAB);
		checkbits_lo <= 8'h0;
		repeat (3000) @(posedge clock);
		checkbits_lo <= 8'h1;
		repeat (3000) @(posedge clock);
		checkbits_lo <= 8'h3;
	end


	initial begin
		wait(checkbits_hi == 8'hA0);
		wait(checkbits[7:0]  == 8'hF0);
		wait(checkbits_hi == 8'h0B);
		wait(checkbits[7:0]  == 8'h0F);
		wait(checkbits_hi == 8'hAB);
		wait(checkbits[7:0]  == 8'h00);
		wait(checkbits_hi == 8'h01);
		wait(checkbits[7:0]  == 8'h01);
		wait(checkbits_hi == 8'h02);
		wait(checkbits[7:0]  == 8'h03);
		wait(checkbits_hi == 8'h04);
		`ifdef GL
			$display("Monitor: Test GPIO (GL) Passed");
		`else
			$display("Monitor: Test GPIO (RTL) Passed");
		`endif
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		
		#1000;
		RSTB <= 1'b1;
		#2000;
	end

	initial begin
		power1 <= 1'b0;
		#200;
		power1 <= 1'b1;
	end
		

	always @(checkbits) begin
		#1 $display("GPIO state = %b (%d - %d)", checkbits,
				checkbits_hi, checkbits_lo);
	end

	wire VDD;
	wire VSS;

	assign VDD = power1;
	assign VSS = 1'b0;













	caravel uut (
		.VDD 	  (VDD),
		.VSS	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("gpio.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule