data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 clock=~clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #0 d=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #15 d=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #20 nreset=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #20 d=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #20 d=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #20 nreset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #20 nreset=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #40 nreset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;\n        ^\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new/testDFlipFlop.v:25: Cannot find file containing module: \'DFlipFlop\'\n    DFlipFlop D1(q,clock,nreset,d);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new,data/full_repos/permissive/423958267/DFlipFlop\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new,data/full_repos/permissive/423958267/DFlipFlop.v\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_3/new,data/full_repos/permissive/423958267/DFlipFlop.sv\n             DFlipFlop\n             DFlipFlop.v\n             DFlipFlop.sv\n             obj_dir/DFlipFlop\n             obj_dir/DFlipFlop.v\n             obj_dir/DFlipFlop.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testDFlipFlop();
    reg clock, nreset, d;
    DFlipFlop D1(q,clock,nreset,d);
    always
    #10 clock=~clock;
    initial
    begin


        #0 d=0;
        clock=0;
        nreset=0;
        #15 d=1;
        #20 nreset=1;
        #20 d=0;
        #20 d=1;
        #20 nreset=0;
        #20 nreset=1;
        #40 nreset=0;
        #20 $finish;
    end
endmodule
module testDFlipFlop();

    reg clock, nreset, d;
    DFlipFlop D1(q,clock,nreset,d);
    always
    #10 clock=~clock;
    initial
    begin


        #0 d=0;
        clock=0;
        nreset=0;
        #15 d=1;
        #20 nreset=1;
        #20 d=0;
        #20 d=1;
        #20 nreset=0;
        #20 nreset=1;
        #40 nreset=0;
        #20 $finish;
    end
endmodule