data/full_repos/permissive/455657973/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:27: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:32: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:38: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:44: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:50: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:56: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:62: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:68: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:74: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:80: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:86: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:91: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:97: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                             : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:106: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                              : ... In instance alu\n      aluPC <= PC_out;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:116: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                              : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:120: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                              : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/455657973/alu.v:125: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PC_out\' generates 64 bits.\n                                                              : ... In instance alu\n     aluPC <= PC_out;\n           ^~\n%Error: data/full_repos/permissive/455657973/alu.v:131: Cannot find file containing module: \'add\'\n add adder(.Ra(RA), .Rb(RB),.cin({1\'d0}),.sum(adder_sum),.cout(adder_cout));\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/add\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/add.v\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/add.sv\n             add\n             add.v\n             add.sv\n             obj_dir/add\n             obj_dir/add.v\n             obj_dir/add.sv\n%Error: data/full_repos/permissive/455657973/alu.v:132: Cannot find file containing module: \'logicalAnd\'\n logicalAnd land(RA,RB,land_out);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:133: Cannot find file containing module: \'logicalOr\'\n logicalOr lor(RA,RB,lor_out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:134: Cannot find file containing module: \'subtract\'\n subtract subtractor(RA, RB, sub_diff);\n ^~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:135: Cannot find file containing module: \'multiply\'\n multiply mul(RA,RB,mul_out);\n ^~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:136: Cannot find file containing module: \'logicalNot\'\n logicalNot not_module(RB,not_out);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:137: Cannot find file containing module: \'rotate_R\'\n rotate_R ror_op(RA,ror_out);\n ^~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:138: Cannot find file containing module: \'rotate_L\'\n rotate_L rol_op(RA ,rol_out);\n ^~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:139: Cannot find file containing module: \'shift_L\'\n shift_L shl(RA,shl_out);\n ^~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:140: Cannot find file containing module: \'shift_R\'\n shift_R shr(RA,shr_out);\n ^~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:141: Cannot find file containing module: \'negate\'\n negate neg(RA,neg_out);\n ^~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:142: Cannot find file containing module: \'divide_32\'\n divide_32 div(RA,RB, div_out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/455657973/alu.v:143: Cannot find file containing module: \'PCincrement\'\n PCincrement incPC(IncPC, RPC, PC_out);\n ^~~~~~~~~~~\n%Error: Exiting due to 13 error(s), 17 warning(s)\n'
module alu(
	input brn_flag, IncPC,
	input wire [31:0] RA,
	input wire [31:0] RB,
	input wire [31:0] RPC,
	input wire [4:0] opcode,
	
	output reg [63:0] RC, 
	output reg [31:0] aluPC
);

parameter Addition = 5'b00011, Subtraction = 5'b00100, Multiplication = 5'b01110, Division = 5'b01111, Shift_right = 5'b00101, Shift_left = 5'b00110, Rotate_right = 5'b00111, Rotate_left = 5'b01000, 
				  Logical_AND = 5'b01001, Logical_OR = 5'b01010, Negate = 5'b10000, Not = 5'b10001, addi = 5'b01011, andi = 5'b01100, ori = 5'b01101, ldw = 5'b00000, ldwi = 5'b00001, stw = 5'b00010,
				  branch = 5'b10010, jr = 5'b10011, jal = 5'b10100, mfhi = 5'b10111, mflo = 5'b11000, in = 5'b10101, out = 5'b10110, nop = 5'b11001, halt = 5'b11010;
	
	wire [31:0] shr_out, shl_out, lor_out, land_out, neg_out, not_out, adder_sum, adder_cout, sub_diff, sub_cout, rol_out, ror_out;
	wire [63:0] mul_out, div_out, PC_out;
	
	always @(*)
		begin
			case (opcode)
				Addition: begin
					RC[31:0] <= adder_sum[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				Subtraction: begin
					RC[31:0] <=  sub_diff[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Logical_OR, ori: begin
					RC[31:0] <= lor_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Logical_AND, andi: begin
					RC[31:0] <= land_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Negate: begin
					RC[31:0] <= neg_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Not: begin
					RC[31:0] <= not_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Shift_right: begin
					RC[31:0] <= shr_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Shift_left: begin
					RC[31:0] <= shl_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Rotate_right: begin
					RC[31:0] <= ror_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Rotate_left: begin
					RC[31:0] <= rol_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Multiplication: begin
					RC[63:32] <= ~mul_out[63:32];
					RC[31:0] <= mul_out[31:0];
					aluPC <= PC_out;
				end
				
				Division: begin
					RC[63:0] <= div_out[63:0];
					aluPC <= PC_out;
				end
				
				ldw, ldwi, stw, addi: begin
					RC[31:0] <= adder_sum[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				branch: begin
					if(brn_flag==1) begin
						aluPC <= adder_sum[31:0];
						RC <= 64'd0;
					end 
					else
						aluPC <= PC_out;
				end
				jr: begin
					aluPC <= adder_sum[31:0];
				end
				jal: begin
					RC[31:0] <= RPC[31:0] + 1;
					aluPC <= adder_sum[31:0];
				end
				halt: begin
					aluPC <= PC_out;
				end
				
				nop: begin
					aluPC <= PC_out;
				end
				
				default: begin
					RC[63:0] <= 64'd0;
					aluPC <= PC_out;
				end
			endcase
	end
	

	add adder(.Ra(RA), .Rb(RB),.cin({1'd0}),.sum(adder_sum),.cout(adder_cout));
	logicalAnd land(RA,RB,land_out);
	logicalOr lor(RA,RB,lor_out);
	subtract subtractor(RA, RB, sub_diff);
	multiply mul(RA,RB,mul_out);
	logicalNot not_module(RB,not_out);
	rotate_R ror_op(RA,ror_out);
	rotate_L rol_op(RA ,rol_out);
	shift_L shl(RA,shl_out);
	shift_R shr(RA,shr_out);
	negate neg(RA,neg_out);
	divide_32 div(RA,RB, div_out);
	PCincrement incPC(IncPC, RPC, PC_out);

endmodule
module alu(
	input brn_flag, IncPC,
	input wire [31:0] RA,
	input wire [31:0] RB,
	input wire [31:0] RPC,
	input wire [4:0] opcode,
	
	output reg [63:0] RC, 
	output reg [31:0] aluPC
);


parameter Addition = 5'b00011, Subtraction = 5'b00100, Multiplication = 5'b01110, Division = 5'b01111, Shift_right = 5'b00101, Shift_left = 5'b00110, Rotate_right = 5'b00111, Rotate_left = 5'b01000, 
				  Logical_AND = 5'b01001, Logical_OR = 5'b01010, Negate = 5'b10000, Not = 5'b10001, addi = 5'b01011, andi = 5'b01100, ori = 5'b01101, ldw = 5'b00000, ldwi = 5'b00001, stw = 5'b00010,
				  branch = 5'b10010, jr = 5'b10011, jal = 5'b10100, mfhi = 5'b10111, mflo = 5'b11000, in = 5'b10101, out = 5'b10110, nop = 5'b11001, halt = 5'b11010;
	
	wire [31:0] shr_out, shl_out, lor_out, land_out, neg_out, not_out, adder_sum, adder_cout, sub_diff, sub_cout, rol_out, ror_out;
	wire [63:0] mul_out, div_out, PC_out;
	
	always @(*)
		begin
			case (opcode)
				Addition: begin
					RC[31:0] <= adder_sum[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				Subtraction: begin
					RC[31:0] <=  sub_diff[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Logical_OR, ori: begin
					RC[31:0] <= lor_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Logical_AND, andi: begin
					RC[31:0] <= land_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Negate: begin
					RC[31:0] <= neg_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Not: begin
					RC[31:0] <= not_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Shift_right: begin
					RC[31:0] <= shr_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Shift_left: begin
					RC[31:0] <= shl_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Rotate_right: begin
					RC[31:0] <= ror_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Rotate_left: begin
					RC[31:0] <= rol_out[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				Multiplication: begin
					RC[63:32] <= ~mul_out[63:32];
					RC[31:0] <= mul_out[31:0];
					aluPC <= PC_out;
				end
				
				Division: begin
					RC[63:0] <= div_out[63:0];
					aluPC <= PC_out;
				end
				
				ldw, ldwi, stw, addi: begin
					RC[31:0] <= adder_sum[31:0];
					RC[63:32] <= 32'd0;
					aluPC <= PC_out;
				end
				
				branch: begin
					if(brn_flag==1) begin
						aluPC <= adder_sum[31:0];
						RC <= 64'd0;
					end 
					else
						aluPC <= PC_out;
				end
				jr: begin
					aluPC <= adder_sum[31:0];
				end
				jal: begin
					RC[31:0] <= RPC[31:0] + 1;
					aluPC <= adder_sum[31:0];
				end
				halt: begin
					aluPC <= PC_out;
				end
				
				nop: begin
					aluPC <= PC_out;
				end
				
				default: begin
					RC[63:0] <= 64'd0;
					aluPC <= PC_out;
				end
			endcase
	end
	

	add adder(.Ra(RA), .Rb(RB),.cin({1'd0}),.sum(adder_sum),.cout(adder_cout));
	logicalAnd land(RA,RB,land_out);
	logicalOr lor(RA,RB,lor_out);
	subtract subtractor(RA, RB, sub_diff);
	multiply mul(RA,RB,mul_out);
	logicalNot not_module(RB,not_out);
	rotate_R ror_op(RA,ror_out);
	rotate_L rol_op(RA ,rol_out);
	shift_L shl(RA,shl_out);
	shift_R shr(RA,shr_out);
	negate neg(RA,neg_out);
	divide_32 div(RA,RB, div_out);
	PCincrement incPC(IncPC, RPC, PC_out);

endmodule