data/full_repos/permissive/42434302/ivltests/pr596.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr596.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #15 reset = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr596.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #20 reset = 1;\n      ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr596.v:21: Unsupported or unknown PLI call: $monitor\n  $monitor("out=%b", out);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr596.v:28: Unsupported: Ignoring delay on this delayed statement.\n  initial #1000 $finish ;\n          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lfsr_test();
  parameter SIZE = 4;
  reg clk, reset, ena;
  wire [SIZE-1:0] out;

  initial
    begin
      clk = 0;
      reset = 0;
      ena = 1'bz;
      #15 reset = 0;
      #20 reset = 1;
    end

   initial
      begin


	 $monitor("out=%b", out);
      end

  always clk = #10 ~clk;

  lfsr_counter LF( clk, reset, out );

  initial #1000 $finish ;
endmodule
module lfsr_test();

  parameter SIZE = 4;
  reg clk, reset, ena;
  wire [SIZE-1:0] out;

  initial
    begin
      clk = 0;
      reset = 0;
      ena = 1'bz;
      #15 reset = 0;
      #20 reset = 1;
    end

   initial
      begin


	 $monitor("out=%b", out);
      end

  always clk = #10 ~clk;

  lfsr_counter LF( clk, reset, out );

  initial #1000 $finish ;
endmodule