data/full_repos/permissive/516818930/controller_tb.v
1: b'%Error: data/full_repos/permissive/516818930/controller_tb.v:1: syntax error, unexpected IDENTIFIER\ntimescale 1ms / 1ns\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516818930/controller_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n       clk=1; forever #500 clk=~clk;  \n                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516818930/controller_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        SENSOR=1; forever #40000 SENSOR=~SENSOR;    \n                          ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module controller_tb();
reg SENSOR,clk;
wire[2:0] main_road;
wire[2:0] side_road;
wire[7:0] count;

controller DUT(main_road,side_road,SENSOR,clk,count);

initial
    begin
       clk=1; forever #500 clk=~clk;
    end
initial 
    begin
        SENSOR=1; forever #40000 SENSOR=~SENSOR;
    end
endmodule
module controller_tb();

reg SENSOR,clk;
wire[2:0] main_road;
wire[2:0] side_road;
wire[7:0] count;

controller DUT(main_road,side_road,SENSOR,clk,count);

initial
    begin
       clk=1; forever #500 clk=~clk;
    end
initial 
    begin
        SENSOR=1; forever #40000 SENSOR=~SENSOR;
    end
endmodule