data/full_repos/permissive/42061259/LIFO_FIFO/Fifo_Lifo.v
1: b"%Error: data/full_repos/permissive/42061259/LIFO_FIFO/Fifo_Lifo.v:54: Cannot find file containing module: 'ram'\n ram #(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram.v\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n"
module Fifo_Lifo(
    input  Wrclk,
    input  Rdclk,
    input  Rst,
    input  Wren,
	input  Rden,
	input  [15:0] Datain ,
	output [15:0] Dataout,
	output Full,
	output Empty
    );


	parameter MODE  = 0                 ;
	parameter DEPTH = (1 << ADDR_WIDTH) ;
	parameter SIZE  = 8                 ;
	parameter ADDR_WIDTH = 3            ;
	

	reg  [ADDR_WIDTH-1:0] wr_pointer;
	reg  [ADDR_WIDTH-1:0] rd_pointer;
	reg  [ADDR_WIDTH  :0] status_cnt;
	
	reg  [SIZE-1:0] data_out ;
	wire [SIZE-1:0] data_ram ;
	



	



	ram #(
		.dat_width(SIZE),
		.adr_width(ADDR_WIDTH),
		.mem_size (DEPTH) 
	) XIFO_RAM(
			.dat_i(data_ram)       , 
			.dat_o(Dataout)        , 
			.adr_wr_i(wr_pointer)  , 
			.adr_rd_i(rd_pointer)  , 
			.we_i(Wren)            , 
			.rde_i(Rden)           , 
			.clk(Rdclk)
	);


endmodule
module Fifo_Lifo(
    input  Wrclk,
    input  Rdclk,
    input  Rst,
    input  Wren,
	input  Rden,
	input  [15:0] Datain ,
	output [15:0] Dataout,
	output Full,
	output Empty
    );



	parameter MODE  = 0                 ;
	parameter DEPTH = (1 << ADDR_WIDTH) ;
	parameter SIZE  = 8                 ;
	parameter ADDR_WIDTH = 3            ;
	

	reg  [ADDR_WIDTH-1:0] wr_pointer;
	reg  [ADDR_WIDTH-1:0] rd_pointer;
	reg  [ADDR_WIDTH  :0] status_cnt;
	
	reg  [SIZE-1:0] data_out ;
	wire [SIZE-1:0] data_ram ;
	



	



	ram #(
		.dat_width(SIZE),
		.adr_width(ADDR_WIDTH),
		.mem_size (DEPTH) 
	) XIFO_RAM(
			.dat_i(data_ram)       , 
			.dat_o(Dataout)        , 
			.adr_wr_i(wr_pointer)  , 
			.adr_rd_i(rd_pointer)  , 
			.we_i(Wren)            , 
			.rde_i(Rden)           , 
			.clk(Rdclk)
	);


endmodule