data/full_repos/permissive/486954482/netlists/2masked_sign64.v
data/verilator_xmls/cac77bf3-5a7e-4808-ac2f-1996895d6ffc.xml
module relu(
    input [127:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );
    wire [63:0] mask1;
    wire [63:0] mask2;
    wire [63:0] unmasked;
    assign mask1 = g_input[63:0];
    assign mask2= g_input[127:64];
    assign unmasked = e_input + mask1;
    assign o = (unmasked[63] == 0)? mask2 + 1 : mask2;
endmodule
module relu(
    input [127:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );

    wire [63:0] mask1;
    wire [63:0] mask2;
    wire [63:0] unmasked;
    assign mask1 = g_input[63:0];
    assign mask2= g_input[127:64];
    assign unmasked = e_input + mask1;
    assign o = (unmasked[63] == 0)? mask2 + 1 : mask2;
endmodule