data/full_repos/permissive/470803657/modules/top.v
1: b"%Error: data/full_repos/permissive/470803657/modules/top.v:18: Cannot find file containing module: 'program_counter'\nprogram_counter PC (.clock           (clock),\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/program_counter\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/program_counter.v\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/program_counter.sv\n             program_counter\n             program_counter.v\n             program_counter.sv\n             obj_dir/program_counter\n             obj_dir/program_counter.v\n             obj_dir/program_counter.sv\n%Error: data/full_repos/permissive/470803657/modules/top.v:23: Cannot find file containing module: 'register'\nregister       MAR (.clock           (clock),\n^~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:29: Cannot find file containing module: 'memory_16x8'\nmemory_16x8    MEM (.in_mem          (out_mar[3:0]), \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:32: Cannot find file containing module: 'register'\nregister        IR (.clock           (clock), \n^~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:38: Cannot find file containing module: 'control_unit'\ncontrol_unit    CU (.clock           (clock), \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:43: Cannot find file containing module: 'register'\nregister        AR (.clock           (clock), \n^~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:49: Cannot find file containing module: 'alu'\nalu            ALU (.in_a            (out_ar), \n^~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:54: Cannot find file containing module: 'register'\nregister        BR (.clock           (clock), \n^~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:60: Cannot find file containing module: 'register'\nregister        OR (.clock           (clock), \n^~~~~~~~\n%Error: data/full_repos/permissive/470803657/modules/top.v:66: Cannot find file containing module: 'bus_mux'\nbus_mux       BMUX (.in_pc           (out_pc[3:0]), \n^~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module top (input  wire       clock,
            input  wire       reset,
            output wire [7:0] out);

wire [11:0] control_word;
wire [7:0]  out_pc;
wire [7:0]  out_mar;
wire [7:0]  out_mem;
wire [7:0]  out_ir;
wire [7:0]  out_ar;
wire [7:0]  out_br;
wire [7:0]  out_alu;
wire [7:0]  out_bmux;

program_counter PC (.clock           (clock),
                    .reset           (reset),
                    .load_pc         (control_word[11]),
                    .out_pc          (out_pc));

register       MAR (.clock           (clock),
                    .reset           (reset),
                    .load            (control_word[9]), 
                    .in_reg          (out_bmux[3:0]), 
                    .out_reg         (out_mar));

memory_16x8    MEM (.in_mem          (out_mar[3:0]), 
                    .out_mem         (out_mem));

register        IR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[7]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out_ir));

control_unit    CU (.clock           (clock), 
                    .reset           (reset), 
                    .in_control_unit (out_ir[7:4]), 
                    .control_word    (control_word));

register        AR (.clock           (clock), 
                    .reset           (reset),
                    .load            (control_word[5]),
                    .in_reg          (out_bmux),
                    .out_reg         (out_ar));

alu            ALU (.in_a            (out_ar), 
                    .in_b            (out_br),
                    .add_sub         (control_word[3]),
                    .out_alu         (out_alu));

register        BR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[1]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out_br));

register        OR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[0]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out));

bus_mux       BMUX (.in_pc           (out_pc[3:0]), 
                    .in_mem          (out_mem), 
                    .in_ir           (out_ir[3:0]), 
                    .in_ar           (out_ar), 
                    .in_alu          (out_alu), 
                    .enable_pc       (control_word[10]), 
                    .enable_mem      (control_word[8]), 
                    .enable_ir       (control_word[6]), 
                    .enable_ar       (control_word[4]), 
                    .enable_alu      (control_word[2]), 
                    .out_bmux        (out_bmux));

endmodule
module top (input  wire       clock,
            input  wire       reset,
            output wire [7:0] out);


wire [11:0] control_word;
wire [7:0]  out_pc;
wire [7:0]  out_mar;
wire [7:0]  out_mem;
wire [7:0]  out_ir;
wire [7:0]  out_ar;
wire [7:0]  out_br;
wire [7:0]  out_alu;
wire [7:0]  out_bmux;

program_counter PC (.clock           (clock),
                    .reset           (reset),
                    .load_pc         (control_word[11]),
                    .out_pc          (out_pc));

register       MAR (.clock           (clock),
                    .reset           (reset),
                    .load            (control_word[9]), 
                    .in_reg          (out_bmux[3:0]), 
                    .out_reg         (out_mar));

memory_16x8    MEM (.in_mem          (out_mar[3:0]), 
                    .out_mem         (out_mem));

register        IR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[7]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out_ir));

control_unit    CU (.clock           (clock), 
                    .reset           (reset), 
                    .in_control_unit (out_ir[7:4]), 
                    .control_word    (control_word));

register        AR (.clock           (clock), 
                    .reset           (reset),
                    .load            (control_word[5]),
                    .in_reg          (out_bmux),
                    .out_reg         (out_ar));

alu            ALU (.in_a            (out_ar), 
                    .in_b            (out_br),
                    .add_sub         (control_word[3]),
                    .out_alu         (out_alu));

register        BR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[1]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out_br));

register        OR (.clock           (clock), 
                    .reset           (reset), 
                    .load            (control_word[0]), 
                    .in_reg          (out_bmux), 
                    .out_reg         (out));

bus_mux       BMUX (.in_pc           (out_pc[3:0]), 
                    .in_mem          (out_mem), 
                    .in_ir           (out_ir[3:0]), 
                    .in_ar           (out_ar), 
                    .in_alu          (out_alu), 
                    .enable_pc       (control_word[10]), 
                    .enable_mem      (control_word[8]), 
                    .enable_ir       (control_word[6]), 
                    .enable_ar       (control_word[4]), 
                    .enable_alu      (control_word[2]), 
                    .out_bmux        (out_bmux));

endmodule