data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_bin2gray.v
data/verilator_xmls/6e6f562a-a091-49b1-a119-14edab23229c.xml
module af4eos_agg_bin2gray
    (
     b,
     g
     );



parameter   WIDTH = 4;



input [WIDTH-1:0]   b;
output [WIDTH-1:0]  g;






wire [WIDTH-1:0]    b;
wire [WIDTH-1:0]    g;

assign              g[WIDTH-1]  = b[WIDTH-1];
assign              g[WIDTH-2:0]= b[WIDTH-1:1] ^ b[WIDTH-2:0];

endmodule
module af4eos_agg_bin2gray
    (
     b,
     g
     );




parameter   WIDTH = 4;



input [WIDTH-1:0]   b;
output [WIDTH-1:0]  g;






wire [WIDTH-1:0]    b;
wire [WIDTH-1:0]    g;

assign              g[WIDTH-1]  = b[WIDTH-1];
assign              g[WIDTH-2:0]= b[WIDTH-1:1] ^ b[WIDTH-2:0];

endmodule