data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/rtldbgsipo1.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/rtldbgsipo1.v:57: Cannot find file containing module: 'fflopknx'\nfflopknx #(ODAT_B) xflodat (clk,rst,edat,odat);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopknx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopknx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopknx.sv\n             fflopknx\n             fflopknx.v\n             fflopknx.sv\n             obj_dir/fflopknx\n             obj_dir/fflopknx.v\n             obj_dir/fflopknx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/rtldbgsipo1.v:64: Cannot find file containing module: 'fflopknx'\nfflopknx #(IDAT_B) xflidat_l (clk,rst,idat,idat_l);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/rtldbgsipo1.v:65: Cannot find file containing module: 'fflopknx'\nfflopknx #(OCNT_B) xflocnt_l (clk,rst,iena?1'b0:ocnt_l+1'b1,ocnt_l);\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module rtldbgsipo1
    (
     clk,
     rst,
     iena,
     idat,
     odat
     );



parameter ODAT_B = 10;
parameter IDAT_B = 1;
parameter OCNT_B = tflog2(ODAT_B);

function integer tflog2;
    input [31 : 0] value;
    integer        i;
    begin
        tflog2 = 0;
        for(i = 0;2 ** i < value;i = i + 1)
            begin
            tflog2 = i + 1;
            end
    end
endfunction





input     clk;
input     rst;
input [IDAT_B-1:0] idat;
input              iena;
output [ODAT_B-1:0] odat;




wire [ODAT_B-1:0]   odat;
reg [ODAT_B-1:0]    edat;

fflopknx #(ODAT_B) xflodat (clk,rst,edat,odat);




wire [IDAT_B-1:0]   idat_l;
wire [OCNT_B-1:0]   ocnt_l;
fflopknx #(IDAT_B) xflidat_l (clk,rst,idat,idat_l);
fflopknx #(OCNT_B) xflocnt_l (clk,rst,iena?1'b0:ocnt_l+1'b1,ocnt_l);

always @(posedge clk)
    if (rst) edat <= {ODAT_B{1'b0}};
    else edat [ocnt_l] <= idat_l;

endmodule
module rtldbgsipo1
    (
     clk,
     rst,
     iena,
     idat,
     odat
     );




parameter ODAT_B = 10;
parameter IDAT_B = 1;
parameter OCNT_B = tflog2(ODAT_B);

function integer tflog2;
    input [31 : 0] value;
    integer        i;
    begin
        tflog2 = 0;
        for(i = 0;2 ** i < value;i = i + 1)
            begin
            tflog2 = i + 1;
            end
    end
endfunction





input     clk;
input     rst;
input [IDAT_B-1:0] idat;
input              iena;
output [ODAT_B-1:0] odat;




wire [ODAT_B-1:0]   odat;
reg [ODAT_B-1:0]    edat;

fflopknx #(ODAT_B) xflodat (clk,rst,edat,odat);




wire [IDAT_B-1:0]   idat_l;
wire [OCNT_B-1:0]   ocnt_l;
fflopknx #(IDAT_B) xflidat_l (clk,rst,idat,idat_l);
fflopknx #(OCNT_B) xflocnt_l (clk,rst,iena?1'b0:ocnt_l+1'b1,ocnt_l);

always @(posedge clk)
    if (rst) edat <= {ODAT_B{1'b0}};
    else edat [ocnt_l] <= idat_l;

endmodule