data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:122: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_read_channel_ar_gated_cell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:141: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_read_channel_r_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:162: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_vict_aw_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:181: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_st_aw_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:200: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_vict_w_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:219: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_st_w_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:238: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_round_w_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:257: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_lsu_bus_arb_w_fifo_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:275: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_write_channel_b_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:296: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_snoop_channel_ac_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:315: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_snoop_channel_cr_gated_cell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v:334: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_snoop_channel_cd_gated_cell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module ct_biu_lowpower(
  accpuclk,
  arcpuclk,
  bcpuclk,
  biu_yy_xx_no_op,
  bus_arb_w_fifo_clk,
  bus_arb_w_fifo_clk_en,
  cdcpuclk,
  coreclk,
  cp0_biu_icg_en,
  crcpuclk,
  forever_coreclk,
  pad_yy_icg_scan_en,
  rcpuclk,
  read_ar_clk_en,
  read_busy,
  read_r_clk_en,
  round_w_clk_en,
  round_wcpuclk,
  snoop_ac_clk_en,
  snoop_cd_clk_en,
  snoop_cr_clk_en,
  st_aw_clk_en,
  st_awcpuclk,
  st_w_clk_en,
  st_wcpuclk,
  vict_aw_clk_en,
  vict_awcpuclk,
  vict_w_clk_en,
  vict_wcpuclk,
  write_b_clk_en,
  write_busy
);


input        bus_arb_w_fifo_clk_en; 
input        coreclk;              
input        cp0_biu_icg_en;       
input        forever_coreclk;      
input        pad_yy_icg_scan_en;   
input        read_ar_clk_en;       
input        read_busy;            
input        read_r_clk_en;        
input        round_w_clk_en;       
input        snoop_ac_clk_en;      
input        snoop_cd_clk_en;      
input        snoop_cr_clk_en;      
input        st_aw_clk_en;         
input        st_w_clk_en;          
input        vict_aw_clk_en;       
input        vict_w_clk_en;        
input        write_b_clk_en;       
input        write_busy;           
output       accpuclk;             
output       arcpuclk;             
output       bcpuclk;              
output       biu_yy_xx_no_op;      
output       bus_arb_w_fifo_clk;   
output       cdcpuclk;             
output       crcpuclk;             
output       rcpuclk;              
output       round_wcpuclk;        
output       st_awcpuclk;          
output       st_wcpuclk;           
output       vict_awcpuclk;        
output       vict_wcpuclk;         




wire         accpuclk;             
wire         arcpuclk;             
wire         bcpuclk;              
wire         biu_yy_xx_no_op;      
wire         bus_arb_w_fifo_clk;   
wire         bus_arb_w_fifo_clk_en; 
wire         cdcpuclk;             
wire         coreclk;              
wire         cp0_biu_icg_en;       
wire         crcpuclk;             
wire         forever_coreclk;      
wire         pad_yy_icg_scan_en;   
wire         rcpuclk;              
wire         read_ar_clk_en;       
wire         read_busy;            
wire         read_r_clk_en;        
wire         round_w_clk_en;       
wire         round_wcpuclk;        
wire         snoop_ac_clk_en;      
wire         snoop_cd_clk_en;      
wire         snoop_cr_clk_en;      
wire         st_aw_clk_en;         
wire         st_awcpuclk;          
wire         st_w_clk_en;          
wire         st_wcpuclk;           
wire         vict_aw_clk_en;       
wire         vict_awcpuclk;        
wire         vict_w_clk_en;        
wire         vict_wcpuclk;         
wire         write_b_clk_en;       
wire         write_busy;           






gated_clk_cell  x_read_channel_ar_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (arcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (read_ar_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_read_channel_r_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (rcpuclk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (read_r_clk_en     ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












gated_clk_cell  x_write_channel_vict_aw_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (vict_awcpuclk     ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (vict_aw_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_st_aw_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (st_awcpuclk       ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (st_aw_clk_en      ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_vict_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (vict_wcpuclk      ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (vict_w_clk_en     ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_st_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (st_wcpuclk        ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (st_w_clk_en       ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_round_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (round_wcpuclk     ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (round_w_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_lsu_bus_arb_w_fifo_gated_clk (
  .clk_in                (coreclk              ),
  .clk_out               (bus_arb_w_fifo_clk   ),
  .external_en           (1'b0                 ),
  .global_en             (1'b1                 ),
  .local_en              (bus_arb_w_fifo_clk_en),
  .module_en             (cp0_biu_icg_en       ),
  .pad_yy_icg_scan_en    (pad_yy_icg_scan_en   )
);









gated_clk_cell  x_write_channel_b_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (bcpuclk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (write_b_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












gated_clk_cell  x_snoop_channel_ac_gated_cell (
  .clk_in             (forever_coreclk   ),
  .clk_out            (accpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_ac_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_snoop_channel_cr_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (crcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_cr_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_snoop_channel_cd_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (cdcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_cd_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










assign biu_yy_xx_no_op = !read_busy && !write_busy;


endmodule
module ct_biu_lowpower(
  accpuclk,
  arcpuclk,
  bcpuclk,
  biu_yy_xx_no_op,
  bus_arb_w_fifo_clk,
  bus_arb_w_fifo_clk_en,
  cdcpuclk,
  coreclk,
  cp0_biu_icg_en,
  crcpuclk,
  forever_coreclk,
  pad_yy_icg_scan_en,
  rcpuclk,
  read_ar_clk_en,
  read_busy,
  read_r_clk_en,
  round_w_clk_en,
  round_wcpuclk,
  snoop_ac_clk_en,
  snoop_cd_clk_en,
  snoop_cr_clk_en,
  st_aw_clk_en,
  st_awcpuclk,
  st_w_clk_en,
  st_wcpuclk,
  vict_aw_clk_en,
  vict_awcpuclk,
  vict_w_clk_en,
  vict_wcpuclk,
  write_b_clk_en,
  write_busy
);



input        bus_arb_w_fifo_clk_en; 
input        coreclk;              
input        cp0_biu_icg_en;       
input        forever_coreclk;      
input        pad_yy_icg_scan_en;   
input        read_ar_clk_en;       
input        read_busy;            
input        read_r_clk_en;        
input        round_w_clk_en;       
input        snoop_ac_clk_en;      
input        snoop_cd_clk_en;      
input        snoop_cr_clk_en;      
input        st_aw_clk_en;         
input        st_w_clk_en;          
input        vict_aw_clk_en;       
input        vict_w_clk_en;        
input        write_b_clk_en;       
input        write_busy;           
output       accpuclk;             
output       arcpuclk;             
output       bcpuclk;              
output       biu_yy_xx_no_op;      
output       bus_arb_w_fifo_clk;   
output       cdcpuclk;             
output       crcpuclk;             
output       rcpuclk;              
output       round_wcpuclk;        
output       st_awcpuclk;          
output       st_wcpuclk;           
output       vict_awcpuclk;        
output       vict_wcpuclk;         




wire         accpuclk;             
wire         arcpuclk;             
wire         bcpuclk;              
wire         biu_yy_xx_no_op;      
wire         bus_arb_w_fifo_clk;   
wire         bus_arb_w_fifo_clk_en; 
wire         cdcpuclk;             
wire         coreclk;              
wire         cp0_biu_icg_en;       
wire         crcpuclk;             
wire         forever_coreclk;      
wire         pad_yy_icg_scan_en;   
wire         rcpuclk;              
wire         read_ar_clk_en;       
wire         read_busy;            
wire         read_r_clk_en;        
wire         round_w_clk_en;       
wire         round_wcpuclk;        
wire         snoop_ac_clk_en;      
wire         snoop_cd_clk_en;      
wire         snoop_cr_clk_en;      
wire         st_aw_clk_en;         
wire         st_awcpuclk;          
wire         st_w_clk_en;          
wire         st_wcpuclk;           
wire         vict_aw_clk_en;       
wire         vict_awcpuclk;        
wire         vict_w_clk_en;        
wire         vict_wcpuclk;         
wire         write_b_clk_en;       
wire         write_busy;           






gated_clk_cell  x_read_channel_ar_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (arcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (read_ar_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_read_channel_r_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (rcpuclk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (read_r_clk_en     ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












gated_clk_cell  x_write_channel_vict_aw_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (vict_awcpuclk     ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (vict_aw_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_st_aw_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (st_awcpuclk       ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (st_aw_clk_en      ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_vict_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (vict_wcpuclk      ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (vict_w_clk_en     ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_st_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (st_wcpuclk        ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (st_w_clk_en       ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_write_channel_round_w_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (round_wcpuclk     ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (round_w_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_lsu_bus_arb_w_fifo_gated_clk (
  .clk_in                (coreclk              ),
  .clk_out               (bus_arb_w_fifo_clk   ),
  .external_en           (1'b0                 ),
  .global_en             (1'b1                 ),
  .local_en              (bus_arb_w_fifo_clk_en),
  .module_en             (cp0_biu_icg_en       ),
  .pad_yy_icg_scan_en    (pad_yy_icg_scan_en   )
);









gated_clk_cell  x_write_channel_b_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (bcpuclk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (write_b_clk_en    ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












gated_clk_cell  x_snoop_channel_ac_gated_cell (
  .clk_in             (forever_coreclk   ),
  .clk_out            (accpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_ac_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_snoop_channel_cr_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (crcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_cr_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










gated_clk_cell  x_snoop_channel_cd_gated_cell (
  .clk_in             (coreclk           ),
  .clk_out            (cdcpuclk          ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (snoop_cd_clk_en   ),
  .module_en          (cp0_biu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










assign biu_yy_xx_no_op = !read_busy && !write_busy;


endmodule