data/full_repos/permissive/530250155/verilog/rtl/site/misc.v
1: b'%Error: data/full_repos/permissive/530250155/verilog/rtl/site/misc.v:22: Cannot find include file: ../toysram.vh\n`include "../toysram.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.v\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.sv\n             ../toysram.vh\n             ../toysram.vh.v\n             ../toysram.vh.sv\n             obj_dir/../toysram.vh\n             obj_dir/../toysram.vh.v\n             obj_dir/../toysram.vh.sv\n%Error: data/full_repos/permissive/530250155/verilog/rtl/site/misc.v:52: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-8:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module misc  #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif

    input            clk,
    input            reset,


    input  [127:0]   la_data_in,
    output [127:0]   la_data_out,
    input  [127:0]   la_oen,





    inout [`MPRJ_IO_PADS-8:0] analog_io,


    input            user_clock2
);

endmodule
module misc  #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif

    input            clk,
    input            reset,


    input  [127:0]   la_data_in,
    output [127:0]   la_data_out,
    input  [127:0]   la_oen,





    inout [`MPRJ_IO_PADS-8:0] analog_io,


    input            user_clock2
);


endmodule