data/full_repos/permissive/439087417/ctrl_u.v
1: b'%Warning-WIDTH: data/full_repos/permissive/439087417/ctrl_u.v:10: Operator NEQ expects 16 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                : ... In instance ctrl_u\nassign st_nxt[1] =(st[0] & bgn) | (st[1] & (itr !=4\'d15));\n                                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/439087417/ctrl_u.v:11: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                : ... In instance ctrl_u\nassign st_nxt[2] = st[1] & itr ==4\'d15;\n                               ^~\n%Error: Exiting due to 2 warning(s)\n'
module ctrl_u (
  input clk, rst_b, bgn,
  input [15:0] itr,
  output fin, ld, init
  );
  reg [2:0] st;
  wire [2:0] st_nxt;
  
assign st_nxt[0] = st[2] | (st[0] & (~bgn));
assign st_nxt[1] =(st[0] & bgn) | (st[1] & (itr !=4'd15));
assign st_nxt[2] = st[1] & itr ==4'd15;

assign ld = (st[0] & bgn) | st[1];
assign init = st[0] & bgn;
assign fin = st[2];

initial st <= 3'b001;
always @ (posedge clk, negedge rst_b) begin
  if (!rst_b)
    st <= 3'b001;
  else
  st <= st_nxt;
end 
endmodule
module ctrl_u (
  input clk, rst_b, bgn,
  input [15:0] itr,
  output fin, ld, init
  );

  reg [2:0] st;
  wire [2:0] st_nxt;
  
assign st_nxt[0] = st[2] | (st[0] & (~bgn));
assign st_nxt[1] =(st[0] & bgn) | (st[1] & (itr !=4'd15));
assign st_nxt[2] = st[1] & itr ==4'd15;

assign ld = (st[0] & bgn) | st[1];
assign init = st[0] & bgn;
assign fin = st[2];

initial st <= 3'b001;
always @ (posedge clk, negedge rst_b) begin
  if (!rst_b)
    st <= 3'b001;
  else
  st <= st_nxt;
end 
endmodule