data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v:8: Unsupported: Ignoring delay on this delayed statement.\n     #1 q <= 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #2 q <= ~q;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module T_FF (q, t, clk, reset, enable);
	output q;
	input t, clk, reset, enable;
	reg q;
	always @ (posedge reset or negedge clk)
	 if (reset)
	    #1 q <= 1'b0;
	 else if (t == 1 && enable) 
	    #2 q <= ~q;
endmodule
module T_FF (q, t, clk, reset, enable);

	output q;
	input t, clk, reset, enable;
	reg q;
	always @ (posedge reset or negedge clk)
	 if (reset)
	    #1 q <= 1'b0;
	 else if (t == 1 && enable) 
	    #2 q <= ~q;
endmodule