data/full_repos/permissive/421223411/verilog/rtl/accelerator/CoreTop.v
data/verilator_xmls/0e0a0b45-d48b-4011-aaf8-3dc66ac7878c.xml
module ControlPath(
  input        clock,
  input        reset,
  input        io_instr_has_jump,
  input        io_instr_has_stop,
  input        io_instr_has_branch,
  input        io_instr_has_mem,
  input        io_instr_has_wb,
  output       io_issue_if,
  input        io_if_done,
  output       io_issue_mem,
  output       io_mem_we,
  input        io_mem_done,
  output       io_waiting,
  output       io_halted,
  output [2:0] io_state,
  input        io_restart_core,
  output       io_restart
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg  restart_reg;
  wire  _io_restart_T = io_restart_core | restart_reg;
  reg [2:0] state;
  wire  is_store_instr = io_instr_has_mem & ~io_instr_has_wb;
  wire  _T_2 = 3'h0 == state;
  wire  _T_5 = 3'h1 == state;
  wire [1:0] _state_T = io_if_done ? 2'h2 : 2'h1;
  wire  _T_8 = 3'h2 == state;
  wire  _T_11 = 3'h3 == state;
  wire [2:0] _GEN_0 = io_instr_has_mem ? 3'h4 : 3'h6;
  wire [2:0] _GEN_1 = io_instr_has_jump | io_instr_has_branch ? 3'h0 : _GEN_0;
  wire [2:0] _GEN_2 = io_instr_has_stop ? 3'h7 : _GEN_1;
  wire  _T_15 = 3'h4 == state;
  wire  _T_18 = 3'h5 == state;
  wire [2:0] _state_T_1 = is_store_instr ? 3'h0 : 3'h6;
  wire [2:0] _state_T_2 = io_mem_done ? _state_T_1 : 3'h5;
  wire  _T_21 = 3'h6 == state;
  wire  _T_24 = 3'h7 == state;
  wire [2:0] _GEN_3 = _T_24 ? 3'h7 : state;
  wire [2:0] _GEN_4 = _T_21 ? 3'h0 : _GEN_3;
  wire [2:0] _GEN_5 = _T_18 ? _state_T_2 : _GEN_4;
  wire [2:0] _GEN_6 = _T_15 ? 3'h5 : _GEN_5;
  wire [2:0] _GEN_7 = _T_11 ? _GEN_2 : _GEN_6;
  wire [2:0] _GEN_8 = _T_8 ? 3'h3 : _GEN_7;
  assign io_issue_if = state == 3'h0;
  assign io_issue_mem = state == 3'h4;
  assign io_mem_we = io_instr_has_mem & ~io_instr_has_wb;
  assign io_waiting = state == 3'h1 | state == 3'h5;
  assign io_halted = state == 3'h7;
  assign io_state = state;
  assign io_restart = io_restart_core | restart_reg;
  always @(posedge clock) begin
    if (reset) begin
      restart_reg <= 1'h0;
    end else if (restart_reg & state != 3'h0 & state != 3'h1 & state != 3'h4 & state != 3'h5) begin
      restart_reg <= 1'h0;
    end else begin
      restart_reg <= _io_restart_T;
    end
    if (reset) begin
      state <= 3'h0;
    end else if (restart_reg & state != 3'h0 & state != 3'h1 & state != 3'h4 & state != 3'h5) begin
      state <= 3'h0;
    end else if (_T_2) begin
      state <= 3'h1;
    end else if (_T_5) begin
      state <= {{1'd0}, _state_T};
    end else begin
      state <= _GEN_8;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  restart_reg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  state = _RAND_1[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module ControlPath(
  input        clock,
  input        reset,
  input        io_instr_has_jump,
  input        io_instr_has_stop,
  input        io_instr_has_branch,
  input        io_instr_has_mem,
  input        io_instr_has_wb,
  output       io_issue_if,
  input        io_if_done,
  output       io_issue_mem,
  output       io_mem_we,
  input        io_mem_done,
  output       io_waiting,
  output       io_halted,
  output [2:0] io_state,
  input        io_restart_core,
  output       io_restart
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg  restart_reg;
  wire  _io_restart_T = io_restart_core | restart_reg;
  reg [2:0] state;
  wire  is_store_instr = io_instr_has_mem & ~io_instr_has_wb;
  wire  _T_2 = 3'h0 == state;
  wire  _T_5 = 3'h1 == state;
  wire [1:0] _state_T = io_if_done ? 2'h2 : 2'h1;
  wire  _T_8 = 3'h2 == state;
  wire  _T_11 = 3'h3 == state;
  wire [2:0] _GEN_0 = io_instr_has_mem ? 3'h4 : 3'h6;
  wire [2:0] _GEN_1 = io_instr_has_jump | io_instr_has_branch ? 3'h0 : _GEN_0;
  wire [2:0] _GEN_2 = io_instr_has_stop ? 3'h7 : _GEN_1;
  wire  _T_15 = 3'h4 == state;
  wire  _T_18 = 3'h5 == state;
  wire [2:0] _state_T_1 = is_store_instr ? 3'h0 : 3'h6;
  wire [2:0] _state_T_2 = io_mem_done ? _state_T_1 : 3'h5;
  wire  _T_21 = 3'h6 == state;
  wire  _T_24 = 3'h7 == state;
  wire [2:0] _GEN_3 = _T_24 ? 3'h7 : state;
  wire [2:0] _GEN_4 = _T_21 ? 3'h0 : _GEN_3;
  wire [2:0] _GEN_5 = _T_18 ? _state_T_2 : _GEN_4;
  wire [2:0] _GEN_6 = _T_15 ? 3'h5 : _GEN_5;
  wire [2:0] _GEN_7 = _T_11 ? _GEN_2 : _GEN_6;
  wire [2:0] _GEN_8 = _T_8 ? 3'h3 : _GEN_7;
  assign io_issue_if = state == 3'h0;
  assign io_issue_mem = state == 3'h4;
  assign io_mem_we = io_instr_has_mem & ~io_instr_has_wb;
  assign io_waiting = state == 3'h1 | state == 3'h5;
  assign io_halted = state == 3'h7;
  assign io_state = state;
  assign io_restart = io_restart_core | restart_reg;
  always @(posedge clock) begin
    if (reset) begin
      restart_reg <= 1'h0;
    end else if (restart_reg & state != 3'h0 & state != 3'h1 & state != 3'h4 & state != 3'h5) begin
      restart_reg <= 1'h0;
    end else begin
      restart_reg <= _io_restart_T;
    end
    if (reset) begin
      state <= 3'h0;
    end else if (restart_reg & state != 3'h0 & state != 3'h1 & state != 3'h4 & state != 3'h5) begin
      state <= 3'h0;
    end else if (_T_2) begin
      state <= 3'h1;
    end else if (_T_5) begin
      state <= {{1'd0}, _state_T};
    end else begin
      state <= _GEN_8;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  restart_reg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  state = _RAND_1[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule