data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v
1: b'%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:18: Cannot find include file: sabitler.vh\n`include "sabitler.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/sabitler.vh\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/sabitler.vh.v\n             data/full_repos/permissive/469669161/verilog/rtl,data/full_repos/permissive/469669161/sabitler.vh.sv\n             sabitler.vh\n             sabitler.vh.v\n             sabitler.vh.sv\n             obj_dir/sabitler.vh\n             obj_dir/sabitler.vh.v\n             obj_dir/sabitler.vh.sv\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:19: Cannot find include file: mikroislem.vh\n`include "mikroislem.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:29: Define or directive not defined: \'`BUYRUK_BIT\'\n    input        [`BUYRUK_BIT-1:0]      bb_buy_g                                                            ,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:30: Define or directive not defined: \'`BB_ADRES_BIT\'\n    input        [`BB_ADRES_BIT-1:0]    bb_buy_ps_g                                                         ,\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:36: Define or directive not defined: \'`UIS_BIT\'\n    output       [`UIS_BIT-1:0]         gc_uis_c                                                            ,  \n                  ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:40: Define or directive not defined: \'`BB_ADRES_BIT\'\n    output      [`BB_ADRES_BIT-1:0]     gc_odd_ps_c                                                                      \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:48: Define or directive not defined: \'`BUYRUK_BIT\'\n    wire         [`BUYRUK_BIT-1:0]       buyruk_w          = bb_buy_g                                       ;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:51: Define or directive not defined: \'`BUY_ISKODU_BIT\'\n    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:51: Define or directive not defined: \'`BUY_ISKODU\'\n    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:51: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;\n                                                                                  ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:51: Define or directive not defined: \'`BUY_ISKODU_BIT\'\n    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;\n                                                                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:52: Define or directive not defined: \'`BUY_HY_BIT\'\n    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:52: Define or directive not defined: \'`BUY_HY\'\n    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;\n                                                                      ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:52: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;\n                                                                              ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:52: Define or directive not defined: \'`BUY_HY_BIT\'\n    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;\n                                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:53: Define or directive not defined: \'`BUY_KY1_BIT\'\n    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:53: Define or directive not defined: \'`BUY_KY1\'\n    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;\n                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:53: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;\n                                                                               ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:53: Define or directive not defined: \'`BUY_KY1_BIT\'\n    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;\n                                                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:54: Define or directive not defined: \'`BUY_KY2_BIT\'\n    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:54: Define or directive not defined: \'`BUY_KY2\'\n    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;\n                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:54: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;\n                                                                               ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:54: Define or directive not defined: \'`BUY_KY2_BIT\'\n    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;\n                                                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:55: Define or directive not defined: \'`BUY_F7_BIT\'\n    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:55: Define or directive not defined: \'`BUY_F7\'\n    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;\n                                                                      ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:55: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;\n                                                                              ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:55: Define or directive not defined: \'`BUY_F7_BIT\'\n    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;\n                                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:56: Define or directive not defined: \'`BUY_F3_BIT\'\n    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:56: Define or directive not defined: \'`BUY_F3\'\n    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;\n                                                                      ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:56: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;\n                                                                              ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:56: Define or directive not defined: \'`BUY_F3_BIT\'\n    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;\n                                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:60: Define or directive not defined: \'`YURUT_KODU_BIT\'\n    reg          [`YURUT_KODU_BIT - 1: 0]    yurut_kodu_r                                                   ;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:61: Define or directive not defined: \'`ISLEV_KODU_BIT\'\n    reg          [`ISLEV_KODU_BIT - 1: 0]    islev_kodu_r                                                   ;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:62: Define or directive not defined: \'`IS1_SEC_BIT\'\n    reg          [`IS1_SEC_BIT - 1: 0]       is1_sec_r                                                      ;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:63: Define or directive not defined: \'`IS2_SEC_BIT\'\n    reg          [`IS2_SEC_BIT - 1: 0]       is2_sec_r                                                      ;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:64: Define or directive not defined: \'`ANLIK_DEGER_BIT\'\n    reg          [`ANLIK_DEGER_BIT - 1: 0]   anlik_deger_r                                                  ; \n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:72: Define or directive not defined: \'`PS_BIT\'\n    reg          [`PS_BIT - 1: 0]            ps_r                                                           ;\n                  ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:74: Define or directive not defined: \'`UIS_BIT\'\n    reg          [`UIS_BIT - 1: 0]           gc_uis_r                                                       ;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:75: Define or directive not defined: \'`UIS_BIT\'\n    reg          [`UIS_BIT - 1: 0]           yazmac_gc_uis_r                                                ;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:118: Define or directive not defined: \'`I_ANLIK_ISARET\'\n        i_anlik = buyruk_w[`I_ANLIK_ISARET] ? {{20{1\'b1}}, \n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        i_anlik = buyruk_w[`I_ANLIK_ISARET] ? {{20{1\'b1}}, \n                                          ^\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:119: Define or directive not defined: \'`I_ANLIK\'\n                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]} \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:119: Define or directive not defined: \'`I_ANLIK_BIT\'\n                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]} \n                                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:122: Define or directive not defined: \'`I_ANLIK\'\n                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]};\n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:122: Define or directive not defined: \'`I_ANLIK_BIT\'\n                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]};\n                                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:123: Define or directive not defined: \'`U_ANLIK\'\n        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:123: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];\n                                   ^~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:123: Define or directive not defined: \'`U_ANLIK_BIT\'\n        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:149: Define or directive not defined: \'`IS1_SEC_KY1\'\n            is1_sec_r = `IS1_SEC_KY1;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/getir_coz.v:149: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            is1_sec_r = `IS1_SEC_KY1;\n                                    ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module getir_coz
    (
    input                               clk_g                                                               ,
    input                               rst_g                                                               ,


    input                               bb_buy_gecerli_g                                                    ,
    input        [`BUYRUK_BIT-1:0]      bb_buy_g                                                            ,
    input        [`BB_ADRES_BIT-1:0]    bb_buy_ps_g                                                         ,
    output                              gc_hazir_c                                                          ,


    input                               gc_duraklat_g                                                       ,
    input                               gc_bosalt_g                                                         ,
    output       [`UIS_BIT-1:0]         gc_uis_c                                                            ,  


    output                              gc_odd_c                                                            ,
    output      [`BB_ADRES_BIT-1:0]     gc_odd_ps_c                                                                      
    );






    wire         [`BUYRUK_BIT-1:0]       buyruk_w          = bb_buy_g                                       ;


    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;
    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;
    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;
    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;
    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;
    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;


    wire                                     gecerli_w                                                      ;
    reg          [`YURUT_KODU_BIT - 1: 0]    yurut_kodu_r                                                   ;
    reg          [`ISLEV_KODU_BIT - 1: 0]    islev_kodu_r                                                   ;
    reg          [`IS1_SEC_BIT - 1: 0]       is1_sec_r                                                      ;
    reg          [`IS2_SEC_BIT - 1: 0]       is2_sec_r                                                      ;
    reg          [`ANLIK_DEGER_BIT - 1: 0]   anlik_deger_r                                                  ; 
    reg                                      yukle_buyrugu_r                                                ;
    reg                                      kaydet_buyrugu_r                                               ;
    reg                                      fence_buyrugu_r                                                ;
    reg                                      bellek_turu_w_r                                                ;
    reg                                      bellek_turu_hw_r                                               ;
    reg                                      bellek_isaretli_r                                              ;
    reg                                      bellek_turu_b_r                                                ;
    reg          [`PS_BIT - 1: 0]            ps_r                                                           ;

    reg          [`UIS_BIT - 1: 0]           gc_uis_r                                                       ;
    reg          [`UIS_BIT - 1: 0]           yazmac_gc_uis_r                                                ;


    reg          [31:0]                      i_anlik                                                        ;
    reg          [31:0]                      u_anlik                                                        ;
    reg          [31:0]                      j_anlik                                                        ;
    reg          [31:0]                      s_anlik                                                        ;
    reg          [31:0]                      b_anlik                                                        ;

    wire                                     yanlis_buyruk_w                                                ;


    assign                                  gecerli_w               =       bb_buy_gecerli_g && ~gc_bosalt_g;
    assign                                  yanlis_buyruk_w         =       islev_kodu_r == 0               ;
    assign                                  gc_hazir_c              =       !gc_duraklat_g;
    assign                                  gc_uis_c                =       yazmac_gc_uis_r                 ;    
    assign                                  gc_odd_c                =       gecerli_w && yanlis_buyruk_w    ;
    assign                                  gc_odd_ps_c             =       ps_r                            ;



    always @* begin
        gc_uis_r                        =               yazmac_gc_uis_r                                     ;


        yurut_kodu_r                    =               0                                                   ;
        islev_kodu_r                    =               0                                                   ;
        is1_sec_r                       =               0                                                   ;
        is2_sec_r                       =               0                                                   ;
        anlik_deger_r                   =               0                                                   ;
        yukle_buyrugu_r                 =               0                                                   ;
        kaydet_buyrugu_r                =               0                                                   ;
        fence_buyrugu_r                 =               0                                                   ;
        bellek_turu_w_r                 =               0                                                   ;
        bellek_turu_hw_r                =               0                                                   ;
        bellek_turu_b_r                 =               0                                                   ;
        bellek_isaretli_r               =               0                                                   ;
        ps_r                            =               bb_buy_ps_g                                         ;

        



        i_anlik = buyruk_w[`I_ANLIK_ISARET] ? {{20{1'b1}}, 
                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]} 
                                            : 
                                              {{20{1'b0}},
                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]};
        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];
        



        j_anlik = { (buyruk_w[19] ? {11{1'b1}} : {11{1'b0}}),
                    buyruk_w[19], 
                    buyruk_w[12+:8],
                    buyruk_w[20],
                    buyruk_w[21+:10],
                    1'b0
                  };
        s_anlik = { (buyruk_w[31] ? {20{1'b1}} : {20{1'b0}}),
                    buyruk_w[25+:7],
                    buyruk_w[7+:5]
                  };
        b_anlik = { (buyruk_w[31] ? {19{1'b1}} : {19{1'b0}}),
                    buyruk_w[31],
                    buyruk_w[7],
                    buyruk_w[25+:6],
                    buyruk_w[8+:4],
                    1'b0
                  };
        

        if (iskodu_w == 7'h3 || iskodu_w == 7'h67 || iskodu_w == 7'h13) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = i_anlik;
        end
        
        if (iskodu_w == 7'h37) begin
            is1_sec_r = `IS1_SEC_0;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = u_anlik;
        end
        
        if (iskodu_w == 7'h17) begin
            is1_sec_r = `IS1_SEC_PS;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = u_anlik;
        end

        if (iskodu_w == 7'h6f) begin
            is1_sec_r = `IS1_SEC_PS;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = j_anlik;
        end

        if (iskodu_w == 7'h63) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
            anlik_deger_r = b_anlik;
        end

        if (iskodu_w == 7'h23) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
            anlik_deger_r = s_anlik;
        end

        if (iskodu_w == 7'h33) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
        end
        
        if (iskodu_w == 7'h73) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_AD;
        end
        


        case (iskodu_w)
            7'h37: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                islev_kodu_r = `LUI;
            end 
            7'h17: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                islev_kodu_r = `AUIPC;            
            end
            7'h13: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                case (f3_w)
                3'h0: islev_kodu_r = `ADD; 
                3'h1: islev_kodu_r = `SLL;
                3'h2: islev_kodu_r = `SLT;
                3'h3: islev_kodu_r = `SLTU;
                3'h4: islev_kodu_r = `XOR;
                3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
                3'h6: islev_kodu_r = `OR;
                3'h7: islev_kodu_r = `AND;
                endcase
            end
            7'h33: begin
                if (f7_w[0]) begin
                    yurut_kodu_r = f3_w < 3'h4 ? `YURUT_KODU_TCB : `YURUT_KODU_TBB;
                    case (f3_w)
                    3'h0: islev_kodu_r = `MUL; 
                    3'h1: islev_kodu_r = `MULH;
                    3'h2: islev_kodu_r = `MULHSU;
                    3'h3: islev_kodu_r = `MULHU;
                    3'h4: islev_kodu_r = `DIV;
                    3'h5: islev_kodu_r = `DIVU; 
                    3'h6: islev_kodu_r = `REM;
                    3'h7: islev_kodu_r = `REMU;
                    endcase                
                end
                else begin
                    yurut_kodu_r = `YURUT_KODU_AMB;
                    case (f3_w)
                    3'h0: islev_kodu_r = f7_w[5] ? `SUB : `ADD; 
                    3'h1: islev_kodu_r = `SLL;
                    3'h2: islev_kodu_r = `SLT;
                    3'h3: islev_kodu_r = `SLTU;
                    3'h4: islev_kodu_r = `XOR;
                    3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
                    3'h6: islev_kodu_r = `OR;
                    3'h7: islev_kodu_r = `AND;
                    endcase                
                end
            end
            7'h6f: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                islev_kodu_r = `JAL;
            end
            7'h67: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                islev_kodu_r = `JALR;
            end
            7'h63: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                case (f3_w)
                3'h0: islev_kodu_r = `BEQ; 
                3'h1: islev_kodu_r = `BNE;
                3'h4: islev_kodu_r = `BLT;
                3'h5: islev_kodu_r = `BGE; 
                3'h6: islev_kodu_r = `BLTU;
                3'h7: islev_kodu_r = `BGEU;
                endcase
            end
            7'h03: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                yukle_buyrugu_r = 1'b1;
                case (f3_w)
                3'h0: begin
                islev_kodu_r = `LB;
                bellek_turu_b_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h1: begin
                islev_kodu_r = `LH;
                bellek_turu_hw_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h2: begin
                islev_kodu_r = `LW;
                bellek_turu_w_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h4: begin
                islev_kodu_r = `LBU;
                bellek_turu_b_r = 1'b1;
                end
                3'h5: begin
                islev_kodu_r = `LHU;
                bellek_turu_hw_r = 1'b1;
                end
                endcase           
            end
            7'h23: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                kaydet_buyrugu_r = 1'b1;
                case (f3_w)
                3'h0: begin
                islev_kodu_r = `SB;
                bellek_turu_b_r = 1'b1;
                end
                3'h1: begin
                islev_kodu_r = `SH;
                bellek_turu_hw_r = 1'b1;
                end
                3'h2: begin
                islev_kodu_r = `SW;
                bellek_turu_w_r = 1'b1;
                end
                endcase           
            end    
            7'h0f: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                fence_buyrugu_r = 1'b1;
                if (f3_w == 0) islev_kodu_r = `FENCE;
            end  
            7'h73: begin

                yurut_kodu_r = `YURUT_KODU_CSR;
                if (f3_w == 0) begin
                    yurut_kodu_r = `YURUT_KODU_SISTEM;
                    if (ky2_w == 'h1) islev_kodu_r = `EBREAK;
                    if (ky2_w == 'h0) islev_kodu_r = `ECALL;
                    if (ky2_w == 'h2) begin 
                        if (f7_w == 'h0) islev_kodu_r = `URET;
                        if (f7_w == 'h18) islev_kodu_r = `MRET;
                    end
                end
                if (f3_w == 'h1)  islev_kodu_r = `CSRRW;
                if (f3_w == 'h2)  islev_kodu_r = `CSRRS;
                if (f3_w == 'h3)  islev_kodu_r = `CSRRC;
                if (f3_w == 'h5)  islev_kodu_r = `CSRRWI;
                if (f3_w == 'h6)  islev_kodu_r = `CSRRSI;
                if (f3_w == 'h7)  islev_kodu_r = `CSRRCI;
            end        
        endcase




        
        
        
        gc_uis_r[`GECERLI]                              = gecerli_w  && ~yanlis_buyruk_w;

        if (gecerli_w) begin


            gc_uis_r[`YURUT_KODU+:`YURUT_KODU_BIT]      = yurut_kodu_r;
            gc_uis_r[`ISLEV_KODU+:`ISLEV_KODU_BIT]      = islev_kodu_r;
            gc_uis_r[`IS1_SEC+:`IS1_SEC_BIT]            = is1_sec_r;
            gc_uis_r[`IS2_SEC+:`IS2_SEC_BIT]            = is2_sec_r;
            gc_uis_r[`ANLIK_DEGER+:`ANLIK_DEGER_BIT]    = anlik_deger_r;
            gc_uis_r[`KY1+:`KY1_BIT]                    = ky1_w;
            gc_uis_r[`KY2+:`KY2_BIT]                    = ky2_w;
            gc_uis_r[`YUKLE_BUYRUGU]                    = yukle_buyrugu_r;
            gc_uis_r[`KAYDET_BUYRUGU]                   = kaydet_buyrugu_r;
            gc_uis_r[`FENCE_BUYRUGU]                    = fence_buyrugu_r;
            gc_uis_r[`BELLEK_TURU_W]                    = bellek_turu_w_r;
            gc_uis_r[`BELLEK_TURU_HW]                   = bellek_turu_hw_r;
            gc_uis_r[`BELLEK_TURU_B]                    = bellek_turu_b_r;
            gc_uis_r[`BELLEK_ISARETLI]                  = bellek_isaretli_r;
            gc_uis_r[`HY+:`HY_BIT]                      = hy_w;
            gc_uis_r[`PS+:`PS_BIT]                      = ps_r;
            gc_uis_r[`DDY_ADRES+:`DDY_ADRES_BIT]        = i_anlik;
            gc_uis_r[`DDY_ANLIK+:`DDY_ANLIK_BIT]        = ky1_w;
        end
    end

    always @(posedge clk_g) begin
        if (rst_g) begin

            yazmac_gc_uis_r <= 0;
        end
        else begin
            if (gc_duraklat_g) begin
                yazmac_gc_uis_r <= yazmac_gc_uis_r;
            end
            else begin
                yazmac_gc_uis_r <= gc_uis_r;
            end
        end
    end

endmodule
module getir_coz
    (
    input                               clk_g                                                               ,
    input                               rst_g                                                               ,


    input                               bb_buy_gecerli_g                                                    ,
    input        [`BUYRUK_BIT-1:0]      bb_buy_g                                                            ,
    input        [`BB_ADRES_BIT-1:0]    bb_buy_ps_g                                                         ,
    output                              gc_hazir_c                                                          ,


    input                               gc_duraklat_g                                                       ,
    input                               gc_bosalt_g                                                         ,
    output       [`UIS_BIT-1:0]         gc_uis_c                                                            ,  


    output                              gc_odd_c                                                            ,
    output      [`BB_ADRES_BIT-1:0]     gc_odd_ps_c                                                                      
    );







    wire         [`BUYRUK_BIT-1:0]       buyruk_w          = bb_buy_g                                       ;


    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;
    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;
    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;
    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;
    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;
    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;


    wire                                     gecerli_w                                                      ;
    reg          [`YURUT_KODU_BIT - 1: 0]    yurut_kodu_r                                                   ;
    reg          [`ISLEV_KODU_BIT - 1: 0]    islev_kodu_r                                                   ;
    reg          [`IS1_SEC_BIT - 1: 0]       is1_sec_r                                                      ;
    reg          [`IS2_SEC_BIT - 1: 0]       is2_sec_r                                                      ;
    reg          [`ANLIK_DEGER_BIT - 1: 0]   anlik_deger_r                                                  ; 
    reg                                      yukle_buyrugu_r                                                ;
    reg                                      kaydet_buyrugu_r                                               ;
    reg                                      fence_buyrugu_r                                                ;
    reg                                      bellek_turu_w_r                                                ;
    reg                                      bellek_turu_hw_r                                               ;
    reg                                      bellek_isaretli_r                                              ;
    reg                                      bellek_turu_b_r                                                ;
    reg          [`PS_BIT - 1: 0]            ps_r                                                           ;

    reg          [`UIS_BIT - 1: 0]           gc_uis_r                                                       ;
    reg          [`UIS_BIT - 1: 0]           yazmac_gc_uis_r                                                ;


    reg          [31:0]                      i_anlik                                                        ;
    reg          [31:0]                      u_anlik                                                        ;
    reg          [31:0]                      j_anlik                                                        ;
    reg          [31:0]                      s_anlik                                                        ;
    reg          [31:0]                      b_anlik                                                        ;

    wire                                     yanlis_buyruk_w                                                ;


    assign                                  gecerli_w               =       bb_buy_gecerli_g && ~gc_bosalt_g;
    assign                                  yanlis_buyruk_w         =       islev_kodu_r == 0               ;
    assign                                  gc_hazir_c              =       !gc_duraklat_g;
    assign                                  gc_uis_c                =       yazmac_gc_uis_r                 ;    
    assign                                  gc_odd_c                =       gecerli_w && yanlis_buyruk_w    ;
    assign                                  gc_odd_ps_c             =       ps_r                            ;



    always @* begin
        gc_uis_r                        =               yazmac_gc_uis_r                                     ;


        yurut_kodu_r                    =               0                                                   ;
        islev_kodu_r                    =               0                                                   ;
        is1_sec_r                       =               0                                                   ;
        is2_sec_r                       =               0                                                   ;
        anlik_deger_r                   =               0                                                   ;
        yukle_buyrugu_r                 =               0                                                   ;
        kaydet_buyrugu_r                =               0                                                   ;
        fence_buyrugu_r                 =               0                                                   ;
        bellek_turu_w_r                 =               0                                                   ;
        bellek_turu_hw_r                =               0                                                   ;
        bellek_turu_b_r                 =               0                                                   ;
        bellek_isaretli_r               =               0                                                   ;
        ps_r                            =               bb_buy_ps_g                                         ;

        



        i_anlik = buyruk_w[`I_ANLIK_ISARET] ? {{20{1'b1}}, 
                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]} 
                                            : 
                                              {{20{1'b0}},
                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]};
        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];
        



        j_anlik = { (buyruk_w[19] ? {11{1'b1}} : {11{1'b0}}),
                    buyruk_w[19], 
                    buyruk_w[12+:8],
                    buyruk_w[20],
                    buyruk_w[21+:10],
                    1'b0
                  };
        s_anlik = { (buyruk_w[31] ? {20{1'b1}} : {20{1'b0}}),
                    buyruk_w[25+:7],
                    buyruk_w[7+:5]
                  };
        b_anlik = { (buyruk_w[31] ? {19{1'b1}} : {19{1'b0}}),
                    buyruk_w[31],
                    buyruk_w[7],
                    buyruk_w[25+:6],
                    buyruk_w[8+:4],
                    1'b0
                  };
        

        if (iskodu_w == 7'h3 || iskodu_w == 7'h67 || iskodu_w == 7'h13) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = i_anlik;
        end
        
        if (iskodu_w == 7'h37) begin
            is1_sec_r = `IS1_SEC_0;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = u_anlik;
        end
        
        if (iskodu_w == 7'h17) begin
            is1_sec_r = `IS1_SEC_PS;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = u_anlik;
        end

        if (iskodu_w == 7'h6f) begin
            is1_sec_r = `IS1_SEC_PS;
            is2_sec_r = `IS2_SEC_AD;
            anlik_deger_r = j_anlik;
        end

        if (iskodu_w == 7'h63) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
            anlik_deger_r = b_anlik;
        end

        if (iskodu_w == 7'h23) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
            anlik_deger_r = s_anlik;
        end

        if (iskodu_w == 7'h33) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_KY2;
        end
        
        if (iskodu_w == 7'h73) begin
            is1_sec_r = `IS1_SEC_KY1;
            is2_sec_r = `IS2_SEC_AD;
        end
        


        case (iskodu_w)
            7'h37: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                islev_kodu_r = `LUI;
            end 
            7'h17: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                islev_kodu_r = `AUIPC;            
            end
            7'h13: begin
                yurut_kodu_r = `YURUT_KODU_AMB;
                case (f3_w)
                3'h0: islev_kodu_r = `ADD; 
                3'h1: islev_kodu_r = `SLL;
                3'h2: islev_kodu_r = `SLT;
                3'h3: islev_kodu_r = `SLTU;
                3'h4: islev_kodu_r = `XOR;
                3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
                3'h6: islev_kodu_r = `OR;
                3'h7: islev_kodu_r = `AND;
                endcase
            end
            7'h33: begin
                if (f7_w[0]) begin
                    yurut_kodu_r = f3_w < 3'h4 ? `YURUT_KODU_TCB : `YURUT_KODU_TBB;
                    case (f3_w)
                    3'h0: islev_kodu_r = `MUL; 
                    3'h1: islev_kodu_r = `MULH;
                    3'h2: islev_kodu_r = `MULHSU;
                    3'h3: islev_kodu_r = `MULHU;
                    3'h4: islev_kodu_r = `DIV;
                    3'h5: islev_kodu_r = `DIVU; 
                    3'h6: islev_kodu_r = `REM;
                    3'h7: islev_kodu_r = `REMU;
                    endcase                
                end
                else begin
                    yurut_kodu_r = `YURUT_KODU_AMB;
                    case (f3_w)
                    3'h0: islev_kodu_r = f7_w[5] ? `SUB : `ADD; 
                    3'h1: islev_kodu_r = `SLL;
                    3'h2: islev_kodu_r = `SLT;
                    3'h3: islev_kodu_r = `SLTU;
                    3'h4: islev_kodu_r = `XOR;
                    3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
                    3'h6: islev_kodu_r = `OR;
                    3'h7: islev_kodu_r = `AND;
                    endcase                
                end
            end
            7'h6f: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                islev_kodu_r = `JAL;
            end
            7'h67: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                islev_kodu_r = `JALR;
            end
            7'h63: begin
                yurut_kodu_r = `YURUT_KODU_DB;
                case (f3_w)
                3'h0: islev_kodu_r = `BEQ; 
                3'h1: islev_kodu_r = `BNE;
                3'h4: islev_kodu_r = `BLT;
                3'h5: islev_kodu_r = `BGE; 
                3'h6: islev_kodu_r = `BLTU;
                3'h7: islev_kodu_r = `BGEU;
                endcase
            end
            7'h03: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                yukle_buyrugu_r = 1'b1;
                case (f3_w)
                3'h0: begin
                islev_kodu_r = `LB;
                bellek_turu_b_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h1: begin
                islev_kodu_r = `LH;
                bellek_turu_hw_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h2: begin
                islev_kodu_r = `LW;
                bellek_turu_w_r = 1'b1;
                bellek_isaretli_r = 1'b1; 
                end
                3'h4: begin
                islev_kodu_r = `LBU;
                bellek_turu_b_r = 1'b1;
                end
                3'h5: begin
                islev_kodu_r = `LHU;
                bellek_turu_hw_r = 1'b1;
                end
                endcase           
            end
            7'h23: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                kaydet_buyrugu_r = 1'b1;
                case (f3_w)
                3'h0: begin
                islev_kodu_r = `SB;
                bellek_turu_b_r = 1'b1;
                end
                3'h1: begin
                islev_kodu_r = `SH;
                bellek_turu_hw_r = 1'b1;
                end
                3'h2: begin
                islev_kodu_r = `SW;
                bellek_turu_w_r = 1'b1;
                end
                endcase           
            end    
            7'h0f: begin
                yurut_kodu_r = `YURUT_KODU_BIB;
                fence_buyrugu_r = 1'b1;
                if (f3_w == 0) islev_kodu_r = `FENCE;
            end  
            7'h73: begin

                yurut_kodu_r = `YURUT_KODU_CSR;
                if (f3_w == 0) begin
                    yurut_kodu_r = `YURUT_KODU_SISTEM;
                    if (ky2_w == 'h1) islev_kodu_r = `EBREAK;
                    if (ky2_w == 'h0) islev_kodu_r = `ECALL;
                    if (ky2_w == 'h2) begin 
                        if (f7_w == 'h0) islev_kodu_r = `URET;
                        if (f7_w == 'h18) islev_kodu_r = `MRET;
                    end
                end
                if (f3_w == 'h1)  islev_kodu_r = `CSRRW;
                if (f3_w == 'h2)  islev_kodu_r = `CSRRS;
                if (f3_w == 'h3)  islev_kodu_r = `CSRRC;
                if (f3_w == 'h5)  islev_kodu_r = `CSRRWI;
                if (f3_w == 'h6)  islev_kodu_r = `CSRRSI;
                if (f3_w == 'h7)  islev_kodu_r = `CSRRCI;
            end        
        endcase




        
        
        
        gc_uis_r[`GECERLI]                              = gecerli_w  && ~yanlis_buyruk_w;

        if (gecerli_w) begin


            gc_uis_r[`YURUT_KODU+:`YURUT_KODU_BIT]      = yurut_kodu_r;
            gc_uis_r[`ISLEV_KODU+:`ISLEV_KODU_BIT]      = islev_kodu_r;
            gc_uis_r[`IS1_SEC+:`IS1_SEC_BIT]            = is1_sec_r;
            gc_uis_r[`IS2_SEC+:`IS2_SEC_BIT]            = is2_sec_r;
            gc_uis_r[`ANLIK_DEGER+:`ANLIK_DEGER_BIT]    = anlik_deger_r;
            gc_uis_r[`KY1+:`KY1_BIT]                    = ky1_w;
            gc_uis_r[`KY2+:`KY2_BIT]                    = ky2_w;
            gc_uis_r[`YUKLE_BUYRUGU]                    = yukle_buyrugu_r;
            gc_uis_r[`KAYDET_BUYRUGU]                   = kaydet_buyrugu_r;
            gc_uis_r[`FENCE_BUYRUGU]                    = fence_buyrugu_r;
            gc_uis_r[`BELLEK_TURU_W]                    = bellek_turu_w_r;
            gc_uis_r[`BELLEK_TURU_HW]                   = bellek_turu_hw_r;
            gc_uis_r[`BELLEK_TURU_B]                    = bellek_turu_b_r;
            gc_uis_r[`BELLEK_ISARETLI]                  = bellek_isaretli_r;
            gc_uis_r[`HY+:`HY_BIT]                      = hy_w;
            gc_uis_r[`PS+:`PS_BIT]                      = ps_r;
            gc_uis_r[`DDY_ADRES+:`DDY_ADRES_BIT]        = i_anlik;
            gc_uis_r[`DDY_ANLIK+:`DDY_ANLIK_BIT]        = ky1_w;
        end
    end

    always @(posedge clk_g) begin
        if (rst_g) begin

            yazmac_gc_uis_r <= 0;
        end
        else begin
            if (gc_duraklat_g) begin
                yazmac_gc_uis_r <= yazmac_gc_uis_r;
            end
            else begin
                yazmac_gc_uis_r <= gc_uis_r;
            end
        end
    end

endmodule