data/full_repos/permissive/508059792/pclogic.v
data/verilator_xmls/a9310245-5bdf-4a2f-827d-07777621fb1e.xml
module pclogic(clk, reset, ain, aout, pcsel);

input reset;
input clk;
input [31:0] ain;

input pcsel;

output reg [31:0] aout;

always @(posedge clk ) begin
	if (reset==1)
		aout<=32'b0;
	else
		if (pcsel==0) begin
			aout<=aout+1;
		end
		if (pcsel==1) begin
			aout<=ain+aout+1;
	end
end


endmodule
module pclogic(clk, reset, ain, aout, pcsel);


input reset;
input clk;
input [31:0] ain;

input pcsel;

output reg [31:0] aout;

always @(posedge clk ) begin
	if (reset==1)
		aout<=32'b0;
	else
		if (pcsel==0) begin
			aout<=aout+1;
		end
		if (pcsel==1) begin
			aout<=ain+aout+1;
	end
end


endmodule