data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:59: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:68: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:77: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:86: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:95: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:104: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:132: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:153: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:163: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:172: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:181: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:188: Unsupported: Verilog 1995 force\n        force tb_rtl_crack.dut.curr_key = 24\'hFFFFFF;\n        ^~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:192: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:197: Unsupported: wait statements\n        wait (tb_rtl_crack.dut.rdy == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_rtl_crack.sv:198: Unsupported: Verilog 1995 release\n        release tb_rtl_crack.dut.curr_key;\n        ^~~~~~~\n%Error: Exiting due to 14 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_crack();

    logic clk, rst_n, en, rdy, key_valid, fpt_wren, err;
    logic [23:0] key, start_key;
    logic [7:0] ct_addr, ct_rddata, fpt_addr, fpt_wrdata;


    logic [7:0] ciphertext [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] parent_pt [255:0];

    crack dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task state_checker;
        input [31:0] index;
        input [3:0] exp_state;
        begin
            if (tb_rtl_crack.dut.state !== exp_state) begin
                $display("ERROR %dA: Expected state is %d, actual state is %d", index, exp_state, tb_rtl_crack.dut.state);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE     4'b0000
    `define EN_A4    4'b0001
    `define DEN_A4   4'b0010
    `define CRACK    4'b0011
    `define VERIFY   4'b0100
    `define READ_PT  4'b0101
    `define CHECK    4'b0110
    `define COPY_PT  4'b0111
    `define CRACKED  4'b1000


    `define KEY_MAX     24'hFFFFFF

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        state_checker(1, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'bx) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'bx, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0;
        @(negedge clk);
        state_checker(2, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1; start_key = 24'h0;
        @(posedge clk);
        state_checker(3, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        @(posedge clk);
        state_checker(4, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b1) begin
            $display("ERROR 4A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        state_checker(5, `EN_A4);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 5A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        while (tb_rtl_crack.dut.state !== `COPY_PT) begin
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        end


        if (tb_rtl_crack.dut.key !== 24'h18) begin
            $display("ERROR 7B: Expected key is %h, actual key is %h", 24'h18, tb_rtl_crack.dut.key);
            err = 1'b1;
        end


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_rtl_crack.dut.pt.altsyncram_component.m_default.altsyncram_inst.mem_data[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_rtl_crack.dut.pt.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end

        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_rtl_crack.dut.pt_copy[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_rtl_crack.dut.pt_copy[i]);
                err = 1'b1;
            end
        end


        while (tb_rtl_crack.dut.state == `COPY_PT) begin
            parent_pt[tb_rtl_crack.dut.fpt_addr] = tb_rtl_crack.dut.fpt_wrdata;
            @(posedge clk);
        end
        state_checker(9, `CRACKED);

        if (tb_rtl_crack.dut.key_valid !== 1'b1) begin
            $display("ERROR 9: Expected key_valid is %d, actual key_valid is %d", 1'b1, tb_rtl_crack.dut.key_valid);
            err = 1'b1;
        end

        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== parent_pt[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], parent_pt[i]);
                err = 1'b1;
            end
        end





        rst_n = 1'b0; en = 1'b0;
        @(posedge clk);
        @(posedge clk);
        state_checker(10, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 10: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        state_checker(11, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 11: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        @(posedge clk);
        state_checker(12, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b1) begin
            $display("ERROR 12: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        state_checker(13, `EN_A4);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 13: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end

        force tb_rtl_crack.dut.curr_key = `KEY_MAX;


        while (tb_rtl_crack.dut.state !== `IDLE) begin
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        end


        wait (tb_rtl_crack.dut.rdy == 1'b1);
        release tb_rtl_crack.dut.curr_key;

        if (tb_rtl_crack.dut.key_valid !== 1'b0) begin
            $display("ERROR 15A: Expected key_valid is %d, actual key_valid is %d", 1'b0, tb_rtl_crack.dut.key_valid);
            err = 1'b1;
        end
        if (tb_rtl_crack.dut.key !== `KEY_MAX) begin
            $display("ERROR 15B: Expected key is %h, actual key is %h", `KEY_MAX, tb_rtl_crack.dut.key);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_rtl_crack();


    logic clk, rst_n, en, rdy, key_valid, fpt_wren, err;
    logic [23:0] key, start_key;
    logic [7:0] ct_addr, ct_rddata, fpt_addr, fpt_wrdata;


    logic [7:0] ciphertext [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] parent_pt [255:0];

    crack dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task state_checker;
        input [31:0] index;
        input [3:0] exp_state;
        begin
            if (tb_rtl_crack.dut.state !== exp_state) begin
                $display("ERROR %dA: Expected state is %d, actual state is %d", index, exp_state, tb_rtl_crack.dut.state);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE     4'b0000
    `define EN_A4    4'b0001
    `define DEN_A4   4'b0010
    `define CRACK    4'b0011
    `define VERIFY   4'b0100
    `define READ_PT  4'b0101
    `define CHECK    4'b0110
    `define COPY_PT  4'b0111
    `define CRACKED  4'b1000


    `define KEY_MAX     24'hFFFFFF

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        state_checker(1, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'bx) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'bx, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0;
        @(negedge clk);
        state_checker(2, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1; start_key = 24'h0;
        @(posedge clk);
        state_checker(3, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        @(posedge clk);
        state_checker(4, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b1) begin
            $display("ERROR 4A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        state_checker(5, `EN_A4);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 5A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        while (tb_rtl_crack.dut.state !== `COPY_PT) begin
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        end


        if (tb_rtl_crack.dut.key !== 24'h18) begin
            $display("ERROR 7B: Expected key is %h, actual key is %h", 24'h18, tb_rtl_crack.dut.key);
            err = 1'b1;
        end


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_rtl_crack.dut.pt.altsyncram_component.m_default.altsyncram_inst.mem_data[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_rtl_crack.dut.pt.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end

        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_rtl_crack.dut.pt_copy[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_rtl_crack.dut.pt_copy[i]);
                err = 1'b1;
            end
        end


        while (tb_rtl_crack.dut.state == `COPY_PT) begin
            parent_pt[tb_rtl_crack.dut.fpt_addr] = tb_rtl_crack.dut.fpt_wrdata;
            @(posedge clk);
        end
        state_checker(9, `CRACKED);

        if (tb_rtl_crack.dut.key_valid !== 1'b1) begin
            $display("ERROR 9: Expected key_valid is %d, actual key_valid is %d", 1'b1, tb_rtl_crack.dut.key_valid);
            err = 1'b1;
        end

        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== parent_pt[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], parent_pt[i]);
                err = 1'b1;
            end
        end





        rst_n = 1'b0; en = 1'b0;
        @(posedge clk);
        @(posedge clk);
        state_checker(10, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 10: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        state_checker(11, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 11: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        @(posedge clk);
        state_checker(12, `IDLE);
        if (tb_rtl_crack.dut.rdy !== 1'b1) begin
            $display("ERROR 12: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        state_checker(13, `EN_A4);
        if (tb_rtl_crack.dut.rdy !== 1'b0) begin
            $display("ERROR 13: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_crack.dut.rdy);
            err = 1'b1;
        end

        force tb_rtl_crack.dut.curr_key = `KEY_MAX;


        while (tb_rtl_crack.dut.state !== `IDLE) begin
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_crack.dut.ct_addr];
        end


        wait (tb_rtl_crack.dut.rdy == 1'b1);
        release tb_rtl_crack.dut.curr_key;

        if (tb_rtl_crack.dut.key_valid !== 1'b0) begin
            $display("ERROR 15A: Expected key_valid is %d, actual key_valid is %d", 1'b0, tb_rtl_crack.dut.key_valid);
            err = 1'b1;
        end
        if (tb_rtl_crack.dut.key !== `KEY_MAX) begin
            $display("ERROR 15B: Expected key is %h, actual key is %h", `KEY_MAX, tb_rtl_crack.dut.key);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule