data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:53: Unsupported: Ignoring delay on this delayed statement.\n#1000;  \n^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:86: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'A\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A & B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:86: Operator AND expects 5 bits on the RHS, but RHS\'s VARREF \'B\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A & B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:88: Operator OR expects 5 bits on the LHS, but LHS\'s VARREF \'A\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A | B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:88: Operator OR expects 5 bits on the RHS, but RHS\'s VARREF \'B\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A | B;\n               ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_xor_4(
`ifdef USE_POWER_PINS
        inout vccd1,
        inout vssd1,
`endif
input clk,
  input [3:0] A0,B0,A1,B1,
input [1:0] ALU_Sel1,ALU_Sel2,
  output [3:0] ALU_Out1,ALU_Out2,
output CarryOut1,CarryOut2,
  output [3:0] x,
output y,
input [1:0] active
);

alu_4 alu_4_1(
.A (A0),
.B (B0),
.ALU_Sel (ALU_Sel1),
.ALU_Out (ALU_Out1),
.CarryOut (CarryOut1)
);

alu_4 alu_4_2(
.A (A1),
.B (B1),
.ALU_Sel (ALU_Sel2),
.ALU_Out (ALU_Out2),
.CarryOut (CarryOut2)
);


  assign x[3:0] = ALU_Out1[3:0] ^ ALU_Out2[3:0];
assign y = CarryOut1 ^ CarryOut2;
  always @(*)
begin
  
  $display("A0", A0[3:0]);
  $display("B0", B0[3:0]);
  $display("A1", A1[3:0]);
  $display("B1", B1[3:0]);
  $display("ALU_Sel1", ALU_Sel1[1:0]);
  $display("ALU_Sel2", ALU_Sel2[1:0]);
  #1000;  
  $display("ALU_Out1", ALU_Out1[3:0]);
  $display("ALU_Out2", ALU_Out2[3:0]);
  $display("CarryOut1", CarryOut1);
  $display("CarryOut2", CarryOut2);
  $display("x", x[3:0]);
  $display("y", y);
  
#1000;  
if (x!=0)
$display ("Faulty ALU");
else
$display ("ALU is right");
if (y!=0)
$display ("Faulty Carry");
else
$display ("Carry is right");
end


endmodule
module alu_xor_4(
`ifdef USE_POWER_PINS
        inout vccd1,
        inout vssd1,
`endif
input clk,
  input [3:0] A0,B0,A1,B1,
input [1:0] ALU_Sel1,ALU_Sel2,
  output [3:0] ALU_Out1,ALU_Out2,
output CarryOut1,CarryOut2,
  output [3:0] x,
output y,
input [1:0] active
);


alu_4 alu_4_1(
.A (A0),
.B (B0),
.ALU_Sel (ALU_Sel1),
.ALU_Out (ALU_Out1),
.CarryOut (CarryOut1)
);

alu_4 alu_4_2(
.A (A1),
.B (B1),
.ALU_Sel (ALU_Sel2),
.ALU_Out (ALU_Out2),
.CarryOut (CarryOut2)
);


  assign x[3:0] = ALU_Out1[3:0] ^ ALU_Out2[3:0];
assign y = CarryOut1 ^ CarryOut2;
  always @(*)
begin
  
  $display("A0", A0[3:0]);
  $display("B0", B0[3:0]);
  $display("A1", A1[3:0]);
  $display("B1", B1[3:0]);
  $display("ALU_Sel1", ALU_Sel1[1:0]);
  $display("ALU_Sel2", ALU_Sel2[1:0]);
  #1000;  
  $display("ALU_Out1", ALU_Out1[3:0]);
  $display("ALU_Out2", ALU_Out2[3:0]);
  $display("CarryOut1", CarryOut1);
  $display("CarryOut2", CarryOut2);
  $display("x", x[3:0]);
  $display("y", y);
  
#1000;  
if (x!=0)
$display ("Faulty ALU");
else
$display ("ALU is right");
if (y!=0)
$display ("Faulty Carry");
else
$display ("Carry is right");
end


endmodule