data/full_repos/permissive/43858668/final_verilog/src/clib/c_lfsr.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_lfsr.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_lfsr.v:49: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_lfsr.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 3 error(s)\n'
module c_lfsr
  (clk, reset, active, load, run, feedback, complete, d, q);
   
`include "c_constants.v"
   

   parameter width = 32;
   

   parameter offset = 0;
   

   parameter [offset:(offset+width)-1] reset_value = {width{1'b1}};
   

   parameter iterations = 1;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input load;
   

   input run;
   

   input [0:width-1] feedback;
   

   input complete;
   

   input [offset:(offset+width)-1] d;
   

   output [offset:(offset+width)-1] q;
   wire [offset:(offset+width)-1] q;
   
   wire [offset:(offset+width)-1] state_q;
   
   wire [0:width-1] 		  feedback_sum;
   c_fbmult
     #(.width(width),
       .iterations(iterations))
   fbmult
     (.feedback(feedback),
      .complete(complete),
      .data_in(state_q),
      .data_out(feedback_sum));
   
   wire [offset:(offset+width)-1] feedback_value;
   assign feedback_value = {width{~load}} & feedback_sum;
   
   wire [offset:(offset+width)-1] toggle_value;
   assign toggle_value = feedback_value ^ d;
   
   wire [offset:(offset+width)-1] base_value;
   
   generate
      
      if(width == 1)
	begin
	   
	   assign base_value = 1'b0;
	   
	end
      else
	begin
	   
	   assign base_value
	     = {1'b0, {(width-1){~load}} & state_q[offset:(offset+width-1)-1]};
	   
	end
      
   endgenerate
   
   wire [offset:(offset+width)-1] state_s;
   assign state_s = (load | run) ? (base_value ^ toggle_value) : state_q;
   c_dff
     #(.width(width),
       .offset(offset),
       .reset_type(reset_type),
       .reset_value(reset_value))
   stateq
     (.clk(clk),
      .reset(reset),
      .active(active),
      .d(state_s),
      .q(state_q));
   
   assign q = state_q;
   
endmodule
module c_lfsr
  (clk, reset, active, load, run, feedback, complete, d, q);

   
`include "c_constants.v"
   

   parameter width = 32;
   

   parameter offset = 0;
   

   parameter [offset:(offset+width)-1] reset_value = {width{1'b1}};
   

   parameter iterations = 1;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input load;
   

   input run;
   

   input [0:width-1] feedback;
   

   input complete;
   

   input [offset:(offset+width)-1] d;
   

   output [offset:(offset+width)-1] q;
   wire [offset:(offset+width)-1] q;
   
   wire [offset:(offset+width)-1] state_q;
   
   wire [0:width-1] 		  feedback_sum;
   c_fbmult
     #(.width(width),
       .iterations(iterations))
   fbmult
     (.feedback(feedback),
      .complete(complete),
      .data_in(state_q),
      .data_out(feedback_sum));
   
   wire [offset:(offset+width)-1] feedback_value;
   assign feedback_value = {width{~load}} & feedback_sum;
   
   wire [offset:(offset+width)-1] toggle_value;
   assign toggle_value = feedback_value ^ d;
   
   wire [offset:(offset+width)-1] base_value;
   
   generate
      
      if(width == 1)
	begin
	   
	   assign base_value = 1'b0;
	   
	end
      else
	begin
	   
	   assign base_value
	     = {1'b0, {(width-1){~load}} & state_q[offset:(offset+width-1)-1]};
	   
	end
      
   endgenerate
   
   wire [offset:(offset+width)-1] state_s;
   assign state_s = (load | run) ? (base_value ^ toggle_value) : state_q;
   c_dff
     #(.width(width),
       .offset(offset),
       .reset_type(reset_type),
       .reset_value(reset_value))
   stateq
     (.clk(clk),
      .reset(reset),
      .active(active),
      .d(state_s),
      .q(state_q));
   
   assign q = state_q;
   
endmodule