data/full_repos/permissive/510695465/Mux.v
data/verilator_xmls/4f476cea-ee5b-4946-9604-08561132c8ec.xml
module Mux(A,B,S,Out);
input [7:0]A,B;
input S;
output [7:0]Out;

assign Out = (S == 1)? B : A;
endmodule
module Mux(A,B,S,Out);

input [7:0]A,B;
input S;
output [7:0]Out;

assign Out = (S == 1)? B : A;
endmodule