data/full_repos/permissive/418819021/lab-03/unitTest.v
1: b'%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:43: Define or directive not defined: \'`TEST_INSTR_WIDTH\'\n        .INSTR_WIDTH     (`TEST_INSTR_WIDTH),\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:44: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n        .DATA_WIDTH      (`TEST_DATA_WIDTH),\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:45: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:46: Define or directive not defined: \'`TEST_ADDR_WIDTH\'\n        .ADDR_WIDTH      (`TEST_ADDR_WIDTH),\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:47: Define or directive not defined: \'`TEST_D_ADDR_WIDTH\'\n        .D_ADDR_WIDTH    (`TEST_D_ADDR_WIDTH),\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:48: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n        .R_ADDR_WIDTH    (`TEST_R_ADDR_WIDTH),\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:80: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:80: syntax error, unexpected \':\', expecting endcase\n                    `STAGE_IF:  result = 1\'b1;\n                             ^\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:81: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:  \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:82: Define or directive not defined: \'`GROUP_REGISTER\'\n                        if (debug_opcode_group[`GROUP_REGISTER]\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:83: Define or directive not defined: \'`TYPE_LDI\'\n                            && debug_opcode_type == `TYPE_LDI \n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:88: Define or directive not defined: \'`STAGE_EX\'\n                    `STAGE_EX:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:89: Define or directive not defined: \'`STAGE_MEM\'\n                    `STAGE_MEM: result = 1\'b1;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:90: Define or directive not defined: \'`STAGE_WB\'\n                    `STAGE_WB: \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:92: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                            && debug_signals[`CONTROL_REG_RD_WRITE] \n                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:100: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:101: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:103: Define or directive not defined: \'`GROUP_STORE_DIRECT\'\n                        if (debug_opcode_group[`GROUP_STORE_DIRECT] \n                                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:104: Define or directive not defined: \'`TYPE_STS\'\n                            && debug_opcode_type == `TYPE_STS \n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:111: Define or directive not defined: \'`STAGE_EX\'\n                    `STAGE_EX:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:112: Define or directive not defined: \'`STAGE_MEM\'\n                    `STAGE_MEM: \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:118: Define or directive not defined: \'`STAGE_WB\'\n                    `STAGE_WB: result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:122: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:123: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:  \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:124: Define or directive not defined: \'`GROUP_REGISTER\'\n                        if (debug_opcode_group[`GROUP_REGISTER]\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:125: Define or directive not defined: \'`TYPE_LDI\'\n                            && debug_opcode_type == `TYPE_LDI\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:130: Define or directive not defined: \'`STAGE_EX\'\n                    `STAGE_EX:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:131: Define or directive not defined: \'`STAGE_MEM\'\n                    `STAGE_MEM: result = 1\'b1;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:132: Define or directive not defined: \'`STAGE_WB\'\n                    `STAGE_WB: \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:134: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                            && debug_signals[`CONTROL_REG_RD_WRITE] \n                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:142: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:143: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:  \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:144: Define or directive not defined: \'`GROUP_REGISTER\'\n                        if (debug_opcode_group[`GROUP_REGISTER]\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:145: Define or directive not defined: \'`TYPE_LDI\'\n                            && debug_opcode_type == `TYPE_LDI \n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:150: Define or directive not defined: \'`STAGE_EX\'\n                    `STAGE_EX:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:151: Define or directive not defined: \'`STAGE_MEM\'\n                    `STAGE_MEM: result = 1\'b1;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:152: Define or directive not defined: \'`STAGE_WB\'\n                    `STAGE_WB: \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:154: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                            && debug_signals[`CONTROL_REG_RD_WRITE] \n                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:162: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:163: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:  \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:164: Define or directive not defined: \'`GROUP_LOAD\'\n                        if (debug_opcode_group[`GROUP_LOAD]\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:165: Define or directive not defined: \'`TYPE_LD_Y\'\n                            && debug_opcode_type == `TYPE_LD_Y)\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:169: Define or directive not defined: \'`STAGE_EX\'\n                    `STAGE_EX:  \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:175: Define or directive not defined: \'`STAGE_MEM\'\n                    `STAGE_MEM:\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:180: Define or directive not defined: \'`STAGE_WB\'\n                    `STAGE_WB: \n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:182: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                            && debug_signals[`CONTROL_REG_RD_WRITE] \n                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:190: Define or directive not defined: \'`STAGE_IF\'\n                    `STAGE_IF:  result = 1\'b1;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:191: Define or directive not defined: \'`STAGE_ID\'\n                    `STAGE_ID:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/unitTest.v:193: Define or directive not defined: \'`GROUP_LOAD\'\n                        if (debug_opcode_group[`GROUP_LOAD] \n                                               ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module unitTest(
        input wire clk,
        input wire reset,
        output reg result
`ifdef DEBUG
        ,
        output wire [`TEST_I_ADDR_WIDTH-1:0] debug_program_counter
`endif
    );
     
`ifdef DEBUG

    wire [`STAGE_COUNT-1:0]     debug_pipeline_stage;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rr;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rd;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_out;
    
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rr_addr;
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rd_addr;
    wire [`FLAG_COUNT:0]          debug_flags_out;
    wire [`TEST_INSTR_WIDTH-1:0]  debug_bus_address;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_X;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Y;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Z;
    wire [`TEST_DATA_WIDTH-1:0]   debug_bus_data;
    wire [`TEST_IMD_WIDTH-1:0]    debug_opcode_imd;
    
    wire [`OPCODE_COUNT-1:0]    debug_opcode_type;
    wire [`GROUP_COUNT-1:0]     debug_opcode_group;
    wire [`TEST_DATA_WIDTH-1:0] debug_writeback_value;
    wire [`SIGNAL_COUNT-1:0]    debug_signals;

`endif



    cpu #(
        .INSTR_WIDTH     (`TEST_INSTR_WIDTH),
        .DATA_WIDTH      (`TEST_DATA_WIDTH),
        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),
        .ADDR_WIDTH      (`TEST_ADDR_WIDTH),
        .D_ADDR_WIDTH    (`TEST_D_ADDR_WIDTH),
        .R_ADDR_WIDTH    (`TEST_R_ADDR_WIDTH),
        .RST_ACTIVE_LEVEL(1)
        ) uut (
        .clk(clk), 
        .reset(reset)
`ifdef DEBUG
        ,
        .debug_pipeline_stage (debug_pipeline_stage),
        .debug_program_counter(debug_program_counter),
        .debug_alu_rr         (debug_alu_rr),
        .debug_alu_rd         (debug_alu_rd),
        .debug_alu_out        (debug_alu_out),
        .debug_flags_out      (debug_flags_out),
        .debug_bus_address    (debug_bus_address),
        .debug_register_X     (debug_register_X),
        .debug_register_Y     (debug_register_Y),
        .debug_register_Z     (debug_register_Z),
        .debug_bus_data       (debug_bus_data),
        .debug_opcode_type    (debug_opcode_type),
        .debug_opcode_group   (debug_opcode_group),
        .debug_opcode_imd     (debug_opcode_imd),
        .debug_writeback_value(debug_writeback_value),
        .debug_signals        (debug_signals),
        .debug_rd_addr        (debug_rd_addr),
        .debug_rr_addr        (debug_rr_addr)
`endif
    );
    always @(*) begin

        case(debug_program_counter)
            0:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI 
                            && debug_opcode_imd == 10)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10 
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            1:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_STORE_DIRECT] 
                            && debug_opcode_type == `TYPE_STS 

                            && debug_opcode_imd == (10 | 128)
                            && debug_rr_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: 

                        if (debug_bus_address == (64 | 10))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	result = 1'b1;
                endcase
            2:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI
                            && debug_opcode_imd == 0)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 0 
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            3:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI 
                            && debug_opcode_imd == 138)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 138
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 28)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            4:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_LOAD]
                            && debug_opcode_type == `TYPE_LD_Y)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  
                        if (debug_alu_rr == 0
                            && debug_alu_rd == 138)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_MEM:
                        if (debug_bus_address == (74))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 27)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            5:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_LOAD] 
                            && debug_opcode_type == `TYPE_LDS 

                            && debug_opcode_imd == (10 | 128))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: 

                        if (debug_bus_address == (64 | 10))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 28)
                            result = 1'b1;
                        else 
                            result = 1'bx;
                endcase
            6:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_REGISTER] 
                            && debug_opcode_type == `TYPE_MOV 
                            && debug_rr_addr == 28)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 27)
                            result = 1'b1;
                        else 
                            result = 1'bx;
                endcase
                
            default:
                result = 1'bz;
        endcase
    end
endmodule
module unitTest(
        input wire clk,
        input wire reset,
        output reg result
`ifdef DEBUG
        ,
        output wire [`TEST_I_ADDR_WIDTH-1:0] debug_program_counter
`endif
    );

     
`ifdef DEBUG

    wire [`STAGE_COUNT-1:0]     debug_pipeline_stage;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rr;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rd;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_out;
    
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rr_addr;
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rd_addr;
    wire [`FLAG_COUNT:0]          debug_flags_out;
    wire [`TEST_INSTR_WIDTH-1:0]  debug_bus_address;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_X;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Y;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Z;
    wire [`TEST_DATA_WIDTH-1:0]   debug_bus_data;
    wire [`TEST_IMD_WIDTH-1:0]    debug_opcode_imd;
    
    wire [`OPCODE_COUNT-1:0]    debug_opcode_type;
    wire [`GROUP_COUNT-1:0]     debug_opcode_group;
    wire [`TEST_DATA_WIDTH-1:0] debug_writeback_value;
    wire [`SIGNAL_COUNT-1:0]    debug_signals;

`endif



    cpu #(
        .INSTR_WIDTH     (`TEST_INSTR_WIDTH),
        .DATA_WIDTH      (`TEST_DATA_WIDTH),
        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),
        .ADDR_WIDTH      (`TEST_ADDR_WIDTH),
        .D_ADDR_WIDTH    (`TEST_D_ADDR_WIDTH),
        .R_ADDR_WIDTH    (`TEST_R_ADDR_WIDTH),
        .RST_ACTIVE_LEVEL(1)
        ) uut (
        .clk(clk), 
        .reset(reset)
`ifdef DEBUG
        ,
        .debug_pipeline_stage (debug_pipeline_stage),
        .debug_program_counter(debug_program_counter),
        .debug_alu_rr         (debug_alu_rr),
        .debug_alu_rd         (debug_alu_rd),
        .debug_alu_out        (debug_alu_out),
        .debug_flags_out      (debug_flags_out),
        .debug_bus_address    (debug_bus_address),
        .debug_register_X     (debug_register_X),
        .debug_register_Y     (debug_register_Y),
        .debug_register_Z     (debug_register_Z),
        .debug_bus_data       (debug_bus_data),
        .debug_opcode_type    (debug_opcode_type),
        .debug_opcode_group   (debug_opcode_group),
        .debug_opcode_imd     (debug_opcode_imd),
        .debug_writeback_value(debug_writeback_value),
        .debug_signals        (debug_signals),
        .debug_rd_addr        (debug_rd_addr),
        .debug_rr_addr        (debug_rr_addr)
`endif
    );
    always @(*) begin

        case(debug_program_counter)
            0:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI 
                            && debug_opcode_imd == 10)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10 
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            1:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_STORE_DIRECT] 
                            && debug_opcode_type == `TYPE_STS 

                            && debug_opcode_imd == (10 | 128)
                            && debug_rr_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: 

                        if (debug_bus_address == (64 | 10))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	result = 1'b1;
                endcase
            2:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI
                            && debug_opcode_imd == 0)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 0 
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 29)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            3:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_REGISTER]
                            && debug_opcode_type == `TYPE_LDI 
                            && debug_opcode_imd == 138)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 138
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 28)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            4:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:  
                        if (debug_opcode_group[`GROUP_LOAD]
                            && debug_opcode_type == `TYPE_LD_Y)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  
                        if (debug_alu_rr == 0
                            && debug_alu_rd == 138)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_MEM:
                        if (debug_bus_address == (74))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 27)
                            result = 1'b1;
                        else
                            result = 1'bx;
                endcase
            5:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_LOAD] 
                            && debug_opcode_type == `TYPE_LDS 

                            && debug_opcode_imd == (10 | 128))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: 

                        if (debug_bus_address == (64 | 10))
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 28)
                            result = 1'b1;
                        else 
                            result = 1'bx;
                endcase
            6:
                case (debug_pipeline_stage)
                    `STAGE_IF:  result = 1'b1;
                    `STAGE_ID:

                        if (debug_opcode_group[`GROUP_REGISTER] 
                            && debug_opcode_type == `TYPE_MOV 
                            && debug_rr_addr == 28)
                            result = 1'b1;
                        else
                            result = 1'bx;
                    `STAGE_EX:  result = 1'b1;
                    `STAGE_MEM: result = 1'b1;
                    `STAGE_WB:	
                        if (debug_writeback_value == 10
                            && debug_signals[`CONTROL_REG_RD_WRITE] 
                            && debug_rd_addr == 27)
                            result = 1'b1;
                        else 
                            result = 1'bx;
                endcase
                
            default:
                result = 1'bz;
        endcase
    end
endmodule