data/full_repos/permissive/523744529/Verilog/3MAC.v
1: b'%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:24: Cannot find file containing module: \'MUL\'\n MUL mul1(W1, I1, mul1out);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/523744529/Verilog,data/full_repos/permissive/523744529/MUL\n             data/full_repos/permissive/523744529/Verilog,data/full_repos/permissive/523744529/MUL.v\n             data/full_repos/permissive/523744529/Verilog,data/full_repos/permissive/523744529/MUL.sv\n             MUL\n             MUL.v\n             MUL.sv\n             obj_dir/MUL\n             obj_dir/MUL.v\n             obj_dir/MUL.sv\n%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:25: Cannot find file containing module: \'MUL\'\n MUL mul2(W2, I2, mul2out);\n ^~~\n%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:26: Cannot find file containing module: \'MUL\'\n MUL mul3(W3, I3, mul3out);\n ^~~\n%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:27: Cannot find file containing module: \'SUM\'\n SUM sum1(mul2out, mul1out, sum1out);\n ^~~\n%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:28: Cannot find file containing module: \'SUM\'\n SUM sum2(mul3out, OUTPUT,  sum2out);\n ^~~\n%Error: data/full_repos/permissive/523744529/Verilog/3MAC.v:29: Cannot find file containing module: \'SUm\'\n SUm sum3(sum1out, sum2out, sum3out);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/523744529/Verilog/3MAC.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'sum3out\' generates 1 bits.\n                                                                      : ... In instance MAC3\n   OUTPUT <= sum3out;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module MAC3 (

	input  wire [7:0] W1,
	input  wire [7:0] I1,
	input  wire [7:0] W2,
	input  wire [7:0] I2,
	input  wire [7:0] W3,
	input  wire [7:0] I3,
	output reg  [7:0] OUTPUT,


	input wire CLK,
	input wire EN,
	input wire RST
);

	wire mul1out;
	wire mul2out;
	wire mul3out;
	wire sum1out;
	wire sum2out;
	wire sum3out;

	MUL mul1(W1, I1, mul1out);
	MUL mul2(W2, I2, mul2out);
	MUL mul3(W3, I3, mul3out);
	SUM sum1(mul2out, mul1out, sum1out);
	SUM sum2(mul3out, OUTPUT,  sum2out);
	SUm sum3(sum1out, sum2out, sum3out);

	always @(posedge CLK)
	begin
		if (RST)
		begin
			OUTPUT <= 0;
		end
		else if (EN)
		begin
			OUTPUT <= sum3out;
		end
	end
endmodule
module MAC3 (

	input  wire [7:0] W1,
	input  wire [7:0] I1,
	input  wire [7:0] W2,
	input  wire [7:0] I2,
	input  wire [7:0] W3,
	input  wire [7:0] I3,
	output reg  [7:0] OUTPUT,


	input wire CLK,
	input wire EN,
	input wire RST
);


	wire mul1out;
	wire mul2out;
	wire mul3out;
	wire sum1out;
	wire sum2out;
	wire sum3out;

	MUL mul1(W1, I1, mul1out);
	MUL mul2(W2, I2, mul2out);
	MUL mul3(W3, I3, mul3out);
	SUM sum1(mul2out, mul1out, sum1out);
	SUM sum2(mul3out, OUTPUT,  sum2out);
	SUm sum3(sum1out, sum2out, sum3out);

	always @(posedge CLK)
	begin
		if (RST)
		begin
			OUTPUT <= 0;
		end
		else if (EN)
		begin
			OUTPUT <= sum3out;
		end
	end
endmodule