data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n       #1\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n       #1\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n            #10 $stop;   \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n            #5 $finish;\n            ^\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:35: Cannot find file containing module: \'clk_gen\'\nclk_gen U0 (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/clk_gen\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/clk_gen.v\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/clk_gen.sv\n             clk_gen\n             clk_gen.v\n             clk_gen.sv\n             obj_dir/clk_gen\n             obj_dir/clk_gen.v\n             obj_dir/clk_gen.sv\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:41: Cannot find file containing module: \'SweepPosition\'\nSweepPosition U1 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/pwm_tb.v:47: Cannot find file containing module: \'AngleToPWM\'\nAngleToPWM U2 (\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_tb;

reg clk1MHz, rst;
wire pwm; 


wire clk200Hz;


wire [9:0] pos;

clk_gen U0 (
   .clk1MHz(clk1MHz), 
   .rst(rst),
   .clk200Hz(clk200Hz)
);

SweepPosition U1 (
   .pos(pos),
   .clk200Hz(clk200Hz),
   .rst(rst)
);

AngleToPWM U2 (
     .pos(pos),
     .clk1MHz(clk1MHz),
     .rst(rst),
     .pwm(pwm)
);

integer i;
reg success_flag;

initial begin
    success_flag = 1;
    rst = 0;
    #5
    rst = 1;
    #5
    rst = 0;

   for(i = 0; i < 32'd30_000_000; i=i+1) 
   begin
       #1
       clk1MHz = 0;
       #1
       clk1MHz = 1;
   end










    


























    

	if (success_flag == 0) begin
		$display("*FAILED** TEST!");
	end 
	else begin
		$display("**PASSED** TEST!");
	end
            #10 $stop;   
            #5 $finish;
end

endmodule
module pwm_tb;


reg clk1MHz, rst;
wire pwm; 


wire clk200Hz;


wire [9:0] pos;

clk_gen U0 (
   .clk1MHz(clk1MHz), 
   .rst(rst),
   .clk200Hz(clk200Hz)
);

SweepPosition U1 (
   .pos(pos),
   .clk200Hz(clk200Hz),
   .rst(rst)
);

AngleToPWM U2 (
     .pos(pos),
     .clk1MHz(clk1MHz),
     .rst(rst),
     .pwm(pwm)
);

integer i;
reg success_flag;

initial begin
    success_flag = 1;
    rst = 0;
    #5
    rst = 1;
    #5
    rst = 0;

   for(i = 0; i < 32'd30_000_000; i=i+1) 
   begin
       #1
       clk1MHz = 0;
       #1
       clk1MHz = 1;
   end










    


























    

	if (success_flag == 0) begin
		$display("*FAILED** TEST!");
	end 
	else begin
		$display("**PASSED** TEST!");
	end
            #10 $stop;   
            #5 $finish;
end

endmodule