data/full_repos/permissive/46804359/pc.v
data/verilator_xmls/58b1c582-78e8-4489-960b-3c7a224e2ed1.xml
module pc(
    input [31:0] in,
    input clk,
    input rst,
    input en,
    output reg [31:0] out);

always@(posedge clk or posedge rst)
begin
    if(rst)
        out <= 32'h00003000;
    else if(en)
        out <= in;
end

endmodule
module pc(
    input [31:0] in,
    input clk,
    input rst,
    input en,
    output reg [31:0] out);


always@(posedge clk or posedge rst)
begin
    if(rst)
        out <= 32'h00003000;
    else if(en)
        out <= in;
end

endmodule