data/full_repos/permissive/51276512/sim.v
1: b'%Error: data/full_repos/permissive/51276512/sim.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/51276512/sim.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/51276512/sim.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset_reg <= 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51276512/sim.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51276512/sim.v:24: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk_reg <= ~clk_reg;\n         ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim#(parameter MAX_CYCLES=10000)(
  output clk,
  output reset
);

  reg reset_reg = 1'b1;
  assign reset = reset_reg;


  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    #10 reset_reg <= 1'b0;
    #1000 $finish;
  end

  reg clk_reg = 1'b0;
  assign clk = clk_reg;


  always #5 clk_reg <= ~clk_reg;

endmodule
module sim#(parameter MAX_CYCLES=10000)(
  output clk,
  output reset
);


  reg reset_reg = 1'b1;
  assign reset = reset_reg;


  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    #10 reset_reg <= 1'b0;
    #1000 $finish;
  end

  reg clk_reg = 1'b0;
  assign clk = clk_reg;


  always #5 clk_reg <= ~clk_reg;

endmodule