data/full_repos/permissive/456468799/Verilog/ColourMux.v
1: b"%Error: data/full_repos/permissive/456468799/Verilog/ColourMux.v:62: Cannot find file containing module: 'ColourMuxBit'\n  ColourMuxBit cb0(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[0], INK_SEL, ink_bits[0], CIDX, MODE_IS_0, MODE_IS_2, colour0);\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456468799/Verilog,data/full_repos/permissive/456468799/ColourMuxBit\n             data/full_repos/permissive/456468799/Verilog,data/full_repos/permissive/456468799/ColourMuxBit.v\n             data/full_repos/permissive/456468799/Verilog,data/full_repos/permissive/456468799/ColourMuxBit.sv\n             ColourMuxBit\n             ColourMuxBit.v\n             ColourMuxBit.sv\n             obj_dir/ColourMuxBit\n             obj_dir/ColourMuxBit.v\n             obj_dir/ColourMuxBit.sv\n%Error: data/full_repos/permissive/456468799/Verilog/ColourMux.v:63: Cannot find file containing module: 'ColourMuxBit'\n  ColourMuxBit cb1(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[1], INK_SEL, ink_bits[1], CIDX, MODE_IS_0, MODE_IS_2, colour1);\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456468799/Verilog/ColourMux.v:64: Cannot find file containing module: 'ColourMuxBit'\n  ColourMuxBit cb2(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[2], INK_SEL, ink_bits[2], CIDX, MODE_IS_0, MODE_IS_2, colour2);\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456468799/Verilog/ColourMux.v:65: Cannot find file containing module: 'ColourMuxBit'\n  ColourMuxBit cb3(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[3], INK_SEL, ink_bits[3], CIDX, MODE_IS_0, MODE_IS_2, colour3);\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456468799/Verilog/ColourMux.v:66: Cannot find file containing module: 'ColourMuxBit'\n  ColourMuxBit cb4(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[4], INK_SEL, ink_bits[4], CIDX, MODE_IS_0, MODE_IS_2, colour4);\n  ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ColourMux(input CLK_n,
                 input[4 : 0] BORDER,
                 input[15 : 0] INKR0,
                 input[15 : 0] INKR1,
                 input[15 : 0] INKR2,
                 input[15 : 0] INKR3,
                 input[15 : 0] INKR4,
                 input COLOUR_KEEP,
                 input INK_SEL,
                 input BORDER_SEL,
                 input MODE_IS_0,
                 input MODE_IS_2,
                 input[3 : 0] CIDX,
                 output[4 : 0] COLOUR);
  reg[15 : 0] ink_bits[5 : 0];
  integer i;
  always
    @(*)
      begin
        for (i = 0; i < 16; i = i + 1)
          begin
            ink_bits[0][i] = INKR0[i];
            ink_bits[1][i] = INKR1[i];
            ink_bits[2][i] = INKR2[i];
            ink_bits[3][i] = INKR3[i];
            ink_bits[4][i] = INKR4[i];
          end
      end
  wire colour0,
       colour1,
       colour2,
       colour3,
       colour4;
  ColourMuxBit cb0(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[0], INK_SEL, ink_bits[0], CIDX, MODE_IS_0, MODE_IS_2, colour0);
  ColourMuxBit cb1(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[1], INK_SEL, ink_bits[1], CIDX, MODE_IS_0, MODE_IS_2, colour1);
  ColourMuxBit cb2(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[2], INK_SEL, ink_bits[2], CIDX, MODE_IS_0, MODE_IS_2, colour2);
  ColourMuxBit cb3(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[3], INK_SEL, ink_bits[3], CIDX, MODE_IS_0, MODE_IS_2, colour3);
  ColourMuxBit cb4(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[4], INK_SEL, ink_bits[4], CIDX, MODE_IS_0, MODE_IS_2, colour4);
  assign COLOUR = { colour4, colour3, colour2, colour1, colour0 };
endmodule
module ColourMux(input CLK_n,
                 input[4 : 0] BORDER,
                 input[15 : 0] INKR0,
                 input[15 : 0] INKR1,
                 input[15 : 0] INKR2,
                 input[15 : 0] INKR3,
                 input[15 : 0] INKR4,
                 input COLOUR_KEEP,
                 input INK_SEL,
                 input BORDER_SEL,
                 input MODE_IS_0,
                 input MODE_IS_2,
                 input[3 : 0] CIDX,
                 output[4 : 0] COLOUR);

  reg[15 : 0] ink_bits[5 : 0];
  integer i;
  always
    @(*)
      begin
        for (i = 0; i < 16; i = i + 1)
          begin
            ink_bits[0][i] = INKR0[i];
            ink_bits[1][i] = INKR1[i];
            ink_bits[2][i] = INKR2[i];
            ink_bits[3][i] = INKR3[i];
            ink_bits[4][i] = INKR4[i];
          end
      end
  wire colour0,
       colour1,
       colour2,
       colour3,
       colour4;
  ColourMuxBit cb0(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[0], INK_SEL, ink_bits[0], CIDX, MODE_IS_0, MODE_IS_2, colour0);
  ColourMuxBit cb1(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[1], INK_SEL, ink_bits[1], CIDX, MODE_IS_0, MODE_IS_2, colour1);
  ColourMuxBit cb2(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[2], INK_SEL, ink_bits[2], CIDX, MODE_IS_0, MODE_IS_2, colour2);
  ColourMuxBit cb3(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[3], INK_SEL, ink_bits[3], CIDX, MODE_IS_0, MODE_IS_2, colour3);
  ColourMuxBit cb4(CLK_n, COLOUR_KEEP, BORDER_SEL, BORDER[4], INK_SEL, ink_bits[4], CIDX, MODE_IS_0, MODE_IS_2, colour4);
  assign COLOUR = { colour4, colour3, colour2, colour1, colour0 };
endmodule