data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_bs_fsdq_2x.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_bs_fsdq_2x.v:43: Cannot find file containing module: 'bw_u1_scanlg_2x'\n  bw_u1_scanlg_2x Iq0 (\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_scanlg_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_scanlg_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_scanlg_2x.sv\n             bw_u1_scanlg_2x\n             bw_u1_scanlg_2x.v\n             bw_u1_scanlg_2x.sv\n             obj_dir/bw_u1_scanlg_2x\n             obj_dir/bw_u1_scanlg_2x.v\n             obj_dir/bw_u1_scanlg_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_bs_fsdq_2x.v:50: Cannot find file containing module: 'bw_u1_scanlg_2x'\n  bw_u1_scanlg_2x Iq1 (\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_bs_fsdq_2x.v:57: Cannot find file containing module: 'bw_u1_scanlg_2x'\n  bw_u1_scanlg_2x Iq2 (\n  ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bw_io_bs_fsdq_2x (

  q, 

  d, up_dr
  );

  output [2:0]	q;
  input  [2:0]	d;
  input		up_dr;


  supply1	vdd;


  bw_u1_scanlg_2x Iq0 (
    .so              (q[0]),
    .sd              (d[0]),
    .ck              (up_dr),
    .se              (vdd)
    );

  bw_u1_scanlg_2x Iq1 (
    .so              (q[1]),
    .sd              (d[1]),
    .ck              (up_dr),
    .se              (vdd)
    );

  bw_u1_scanlg_2x Iq2 (
    .so              (q[2]),
    .sd              (d[2]),
    .ck              (up_dr),
    .se              (vdd)
    );

  endmodule
module bw_io_bs_fsdq_2x (

  q, 

  d, up_dr
  );


  output [2:0]	q;
  input  [2:0]	d;
  input		up_dr;


  supply1	vdd;


  bw_u1_scanlg_2x Iq0 (
    .so              (q[0]),
    .sd              (d[0]),
    .ck              (up_dr),
    .se              (vdd)
    );

  bw_u1_scanlg_2x Iq1 (
    .so              (q[1]),
    .sd              (d[1]),
    .ck              (up_dr),
    .se              (vdd)
    );

  bw_u1_scanlg_2x Iq2 (
    .so              (q[2]),
    .sd              (d[2]),
    .ck              (up_dr),
    .se              (vdd)
    );

  endmodule