data/full_repos/permissive/449370139/verilog_code/uart.v
1: b"%Error: data/full_repos/permissive/449370139/verilog_code/uart.v:79: Cannot find file containing module: 'uart_receiver'\nuart_receiver rx(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_receiver\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_receiver.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_receiver.sv\n             uart_receiver\n             uart_receiver.v\n             uart_receiver.sv\n             obj_dir/uart_receiver\n             obj_dir/uart_receiver.v\n             obj_dir/uart_receiver.sv\n%Error: data/full_repos/permissive/449370139/verilog_code/uart.v:84: Cannot find file containing module: 'uart_transmitter'\nuart_transmitter tx(\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart(
    input clk,
    input I_rst_n,
    input rdn,
    input wrn,
    input rxd,
    input [7:0]d_in,
    output[7:0]d_out,
    output r_ready,
    output t_empty,
    output txd
    );




parameter count=651;
reg [15:0] num;
reg [3:0] cnt;
reg clkin;
wire parity_error;
wire frame_error;




always@(posedge clk or negedge I_rst_n)
begin
    if(!I_rst_n)begin
        num<=16'b0000000000000000;
        clkin<=1'b0;
    end
    else begin
        num=num+16'b0000000000000001;
        if(num>=count/2) begin
            clkin=~clkin;     
            num<=16'b0000000000000000;
        end 
    end
end




always @(posedge clkin or negedge I_rst_n) begin
    if(!I_rst_n)begin
        cnt<=4'b0000;
    end
    else begin
        cnt <= cnt + 4'b0001;
    end
end





uart_receiver rx(
    .clk(clkin),.clrn(I_rst_n),.cnt(cnt),.rdn(rdn),.rxd(rxd),
    .d_out(d_out),.r_ready(r_ready),.parity_error(parity_error),.frame_error(frame_error)
);

uart_transmitter tx(
    .clk(clkin),.clrn(I_rst_n),.wrn(wrn),.d_in(d_in),.cnt(cnt),
    .t_empty(t_empty),.txd(txd)
);

endmodule
module uart(
    input clk,
    input I_rst_n,
    input rdn,
    input wrn,
    input rxd,
    input [7:0]d_in,
    output[7:0]d_out,
    output r_ready,
    output t_empty,
    output txd
    );





parameter count=651;
reg [15:0] num;
reg [3:0] cnt;
reg clkin;
wire parity_error;
wire frame_error;




always@(posedge clk or negedge I_rst_n)
begin
    if(!I_rst_n)begin
        num<=16'b0000000000000000;
        clkin<=1'b0;
    end
    else begin
        num=num+16'b0000000000000001;
        if(num>=count/2) begin
            clkin=~clkin;     
            num<=16'b0000000000000000;
        end 
    end
end




always @(posedge clkin or negedge I_rst_n) begin
    if(!I_rst_n)begin
        cnt<=4'b0000;
    end
    else begin
        cnt <= cnt + 4'b0001;
    end
end





uart_receiver rx(
    .clk(clkin),.clrn(I_rst_n),.cnt(cnt),.rdn(rdn),.rxd(rxd),
    .d_out(d_out),.r_ready(r_ready),.parity_error(parity_error),.frame_error(frame_error)
);

uart_transmitter tx(
    .clk(clkin),.clrn(I_rst_n),.wrn(wrn),.d_in(d_in),.cnt(cnt),
    .t_empty(t_empty),.txd(txd)
);

endmodule