data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/PCnt.v
data/verilator_xmls/9016d014-ef01-4a01-aeca-24cc61b4ef6b.xml
module PCnt(
    input wire clk,
    input wire rstn,
    input wire we,
    input wire [31:0] data_in,
    output wire [31:0] data_out
    );

    reg [31:0] current_pc;

    always@(posedge clk or negedge rstn)
    begin
        if (!rstn) begin 
            current_pc <= 32'h01000000;
        end 
        else if(we) begin
            current_pc <= data_in;
        end
    end
    
    assign data_out = current_pc;
    
endmodule
module PCnt(
    input wire clk,
    input wire rstn,
    input wire we,
    input wire [31:0] data_in,
    output wire [31:0] data_out
    );


    reg [31:0] current_pc;

    always@(posedge clk or negedge rstn)
    begin
        if (!rstn) begin 
            current_pc <= 32'h01000000;
        end 
        else if(we) begin
            current_pc <= data_in;
        end
    end
    
    assign data_out = current_pc;
    
endmodule