data/full_repos/permissive/514775464/inputCapture_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n initial begin reset=1\'b1;#20 reset=1\'b0;end\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n initial begin signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; end\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n initial begin signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; end\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n initial begin signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; end\n                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n initial begin signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; #30 signal=1\'b1; #20 signal=1\'b0; end\n                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  initial begin rstOutput=1\'b0; #120 rstOutput=1\'b1; end\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/514775464/inputCapture_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  initial begin rstIntFlag=1\'b0; #140 rstIntFlag=1\'b1; end\n                                 ^\n%Error: data/full_repos/permissive/514775464/inputCapture_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/514775464/inputCapture_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, ic1);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module inputCapture_tb;
  reg clk,reset;
  wire [7:0] count;
  reg signal;
  reg rstOutput;
  wire intFlag;
  reg rstIntFlag;

  input_capture ic1(.clk(clk),.val(count),.rst(reset),.sig(signal),.rstVal(rstOutput), .rstIntFlag(rstIntFlag), .intFlag(intFlag));

  initial begin 
    clk = 1'b0; 
    repeat(50) 
    #4
    clk= ~clk;
  end


 initial begin reset=1'b1;#20 reset=1'b0;end

 initial begin signal=1'b0; #30 signal=1'b1; #20 signal=1'b0; #30 signal=1'b1; #20 signal=1'b0; end

  initial begin rstOutput=1'b0; #120 rstOutput=1'b1; end

  initial begin rstIntFlag=1'b0; #140 rstIntFlag=1'b1; end
  initial begin
 	$dumpfile("dump.vcd"); 
    $dumpvars(0, ic1);
  end
    
endmodule
module inputCapture_tb;

  reg clk,reset;
  wire [7:0] count;
  reg signal;
  reg rstOutput;
  wire intFlag;
  reg rstIntFlag;

  input_capture ic1(.clk(clk),.val(count),.rst(reset),.sig(signal),.rstVal(rstOutput), .rstIntFlag(rstIntFlag), .intFlag(intFlag));

  initial begin 
    clk = 1'b0; 
    repeat(50) 
    #4
    clk= ~clk;
  end


 initial begin reset=1'b1;#20 reset=1'b0;end

 initial begin signal=1'b0; #30 signal=1'b1; #20 signal=1'b0; #30 signal=1'b1; #20 signal=1'b0; end

  initial begin rstOutput=1'b0; #120 rstOutput=1'b1; end

  initial begin rstIntFlag=1'b0; #140 rstIntFlag=1'b1; end
  initial begin
 	$dumpfile("dump.vcd"); 
    $dumpvars(0, ic1);
  end
    
endmodule