data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_data_checker.v
data/verilator_xmls/12c76534-5fd5-4ec6-a939-df94ed84cd79.xml
module comp_mult_data_checker #(
parameter DWIDTH = 8
)(

input                         clk          ,
input                         rst_n        ,
input                         sw_rst       ,
                                                 

input                         op_val       ,
input                         op_rdy       ,
input [      2*2*DWIDTH -1:0] op_data      ,
                                               

input                         sample       ,
                                           
input [2*2*(DWIDTH + 1) -1:0] res_data_4   ,
input [2*2*(DWIDTH + 1) -1:0] res_data_2   ,
input [2*2*(DWIDTH + 1) -1:0] res_data_1




); 

reg         [  2*2*DWIDTH -1:0] operands_fifo [64-1:0];
reg         [           6 -1:0] wr_ptr; 
reg         [           6 -1:0] rd_ptr;


wire signed [2*(DWIDTH+1) -1:0] dut_xr_4;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_4;

wire signed [2*(DWIDTH+1) -1:0] dut_xr_2;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_2;

wire signed [2*(DWIDTH+1) -1:0] dut_xr_1;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_1;
                    
reg signed  [      DWIDTH -1:0] l_x1, l_y1, l_x2, l_y2 ;
reg signed  [2*(DWIDTH+1) -1:0] l_xr;
reg signed  [2*(DWIDTH+1) -1:0] l_yr;

assign dut_xr_4 = res_data_4[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_4 = res_data_4[           0+:2*(DWIDTH+1)];

assign dut_xr_2 = res_data_2[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_2 = res_data_2[           0+:2*(DWIDTH+1)];

assign dut_xr_1 = res_data_1[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_1 = res_data_1[           0+:2*(DWIDTH+1)];


always @(posedge clk or negedge rst_n)
if(~rst_n) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end else 
if(sw_rst) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end 

always @(posedge clk)
if(op_val & op_rdy) begin 
    operands_fifo[wr_ptr] <= op_data;
    wr_ptr <= wr_ptr + 'd1;
end 

always @(posedge clk)
if(sample) begin 
    {l_x1, l_y1, l_x2, l_y2} = operands_fifo[rd_ptr];
    l_xr = l_x1 * l_x2 - l_y1 * l_y2;
    l_yr = l_x1 * l_y2 + l_y1 * l_x2;
    rd_ptr <= rd_ptr + 'd1;
    if ((dut_xr_4 !== l_xr) | (dut_yr_4 !== l_yr)) begin
        $display("%M %0t COMP_MULT_4 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_4, dut_yr_4, l_xr,l_yr);     
        $stop;
    end 
    else if ((dut_xr_2 !== l_xr) | (dut_yr_2 !== l_yr)) begin
        $display("%M %0t COMP_MULT_2 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_2, dut_yr_2, l_xr,l_yr);     
        $stop;
    end 
    else if ((dut_xr_1 !== l_xr) | (dut_yr_1 !== l_yr)) begin
        $display("%M %0t COMP_MULT_1 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_1, dut_yr_1, l_xr,l_yr);     
        $stop;
    end 
    else
        $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), same as expected (%0d + %0di)", $time,
         l_x1, l_y1, l_x2, l_y2, dut_xr_4, dut_yr_4, l_xr,l_yr);
end 




endmodule
module comp_mult_data_checker #(
parameter DWIDTH = 8
)(

input                         clk          ,
input                         rst_n        ,
input                         sw_rst       ,
                                                 

input                         op_val       ,
input                         op_rdy       ,
input [      2*2*DWIDTH -1:0] op_data      ,
                                               

input                         sample       ,
                                           
input [2*2*(DWIDTH + 1) -1:0] res_data_4   ,
input [2*2*(DWIDTH + 1) -1:0] res_data_2   ,
input [2*2*(DWIDTH + 1) -1:0] res_data_1




);
 

reg         [  2*2*DWIDTH -1:0] operands_fifo [64-1:0];
reg         [           6 -1:0] wr_ptr; 
reg         [           6 -1:0] rd_ptr;


wire signed [2*(DWIDTH+1) -1:0] dut_xr_4;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_4;

wire signed [2*(DWIDTH+1) -1:0] dut_xr_2;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_2;

wire signed [2*(DWIDTH+1) -1:0] dut_xr_1;
wire signed [2*(DWIDTH+1) -1:0] dut_yr_1;
                    
reg signed  [      DWIDTH -1:0] l_x1, l_y1, l_x2, l_y2 ;
reg signed  [2*(DWIDTH+1) -1:0] l_xr;
reg signed  [2*(DWIDTH+1) -1:0] l_yr;

assign dut_xr_4 = res_data_4[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_4 = res_data_4[           0+:2*(DWIDTH+1)];

assign dut_xr_2 = res_data_2[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_2 = res_data_2[           0+:2*(DWIDTH+1)];

assign dut_xr_1 = res_data_1[2*(DWIDTH+1)+:2*(DWIDTH+1)];
assign dut_yr_1 = res_data_1[           0+:2*(DWIDTH+1)];


always @(posedge clk or negedge rst_n)
if(~rst_n) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end else 
if(sw_rst) begin 
    wr_ptr <= 'd0;
    rd_ptr <= 'd0;
end 

always @(posedge clk)
if(op_val & op_rdy) begin 
    operands_fifo[wr_ptr] <= op_data;
    wr_ptr <= wr_ptr + 'd1;
end 

always @(posedge clk)
if(sample) begin 
    {l_x1, l_y1, l_x2, l_y2} = operands_fifo[rd_ptr];
    l_xr = l_x1 * l_x2 - l_y1 * l_y2;
    l_yr = l_x1 * l_y2 + l_y1 * l_x2;
    rd_ptr <= rd_ptr + 'd1;
    if ((dut_xr_4 !== l_xr) | (dut_yr_4 !== l_yr)) begin
        $display("%M %0t COMP_MULT_4 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_4, dut_yr_4, l_xr,l_yr);     
        $stop;
    end 
    else if ((dut_xr_2 !== l_xr) | (dut_yr_2 !== l_yr)) begin
        $display("%M %0t COMP_MULT_2 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_2, dut_yr_2, l_xr,l_yr);     
        $stop;
    end 
    else if ((dut_xr_1 !== l_xr) | (dut_yr_1 !== l_yr)) begin
        $display("%M %0t COMP_MULT_1 ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
        l_x1, l_y1, l_x2, l_y2, dut_xr_1, dut_yr_1, l_xr,l_yr);     
        $stop;
    end 
    else
        $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), same as expected (%0d + %0di)", $time,
         l_x1, l_y1, l_x2, l_y2, dut_xr_4, dut_yr_4, l_xr,l_yr);
end 




endmodule