data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_memory_2.sv
data/verilator_xmls/ab2d5b49-4941-4c87-bd67-62afaaa929a8.xml
module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
	typedef logic [3:0] nibble;

	nibble mem[0:15];

	always @(posedge clk) begin
		if (wen) mem[addr] <= wdata;
		rdata <= mem[addr];
	end
endmodule
module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);

	typedef logic [3:0] nibble;

	nibble mem[0:15];

	always @(posedge clk) begin
		if (wen) mem[addr] <= wdata;
		rdata <= mem[addr];
	end
endmodule