data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/HalfAdder.v
data/verilator_xmls/cd060b1e-d889-4c32-b66e-4501bac58b0b.xml
module HalfAdder(
    input aIn,
    input bIn,
    output sum,
    output carry
  );
  
  assign sum = aIn ^ bIn;
  assign carry = aIn & bIn;
  
endmodule
module HalfAdder(
    input aIn,
    input bIn,
    output sum,
    output carry
  );

  
  assign sum = aIn ^ bIn;
  assign carry = aIn & bIn;
  
endmodule