data/full_repos/permissive/50737157/src/testerCpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/50737157/src/testerCpu.v:14: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk=!clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/50737157/src/testerCpu.v:21: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dff.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/50737157/src/testerCpu.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/50737157/src/testerCpu.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 interrupts[7] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50737157/src/testerCpu.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 interrupts[7] = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50737157/src/testerCpu.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester();
    reg clk;
    reg reset;
    reg [7:0] interrupts;

    wire [15:0] address_bus;
    wire [15:0] data_bus;

    wire [15:0] led;

    wire read, write, halt;
    
    reg [1:0] counter;
    always #1 clk=!clk;

    initial begin
        clk = 0;
        reset = 1;
        counter = 0;
        interrupts = 0;
        $dumpfile("dff.vcd");
        $dumpvars;
        #10 interrupts[7] = 1;
        #1 interrupts[7] = 0;
        #300 $finish;
    end
    
    always @ (posedge clk) begin
        counter <= counter + 1;
        if (&counter)
            reset <= 0;
    end
    
    wire cs_diodes; assign cs_diodes = address_bus[15:12] == 4'b1001;
    Diodes diodes(data_bus, led, cs_diodes, write);

    wire cs_ram; assign cs_ram = !address_bus[15];
    Ram ram(
        .clk(clk),
        .data_bus(data_bus),
        .address_bus(address_bus[10:0]),
        .enable(cs_ram),
        .write(write),
        .read(read));
        
    Cpu cpu(
        .clk(clk),
        .reset(reset),
        .data_bus(data_bus),
        .address_bus(address_bus),
        .r(read),
        .w(write),
        .interrupts(interrupts),
        .halt(halt));
endmodule
module tester();

    reg clk;
    reg reset;
    reg [7:0] interrupts;

    wire [15:0] address_bus;
    wire [15:0] data_bus;

    wire [15:0] led;

    wire read, write, halt;
    
    reg [1:0] counter;
    always #1 clk=!clk;

    initial begin
        clk = 0;
        reset = 1;
        counter = 0;
        interrupts = 0;
        $dumpfile("dff.vcd");
        $dumpvars;
        #10 interrupts[7] = 1;
        #1 interrupts[7] = 0;
        #300 $finish;
    end
    
    always @ (posedge clk) begin
        counter <= counter + 1;
        if (&counter)
            reset <= 0;
    end
    
    wire cs_diodes; assign cs_diodes = address_bus[15:12] == 4'b1001;
    Diodes diodes(data_bus, led, cs_diodes, write);

    wire cs_ram; assign cs_ram = !address_bus[15];
    Ram ram(
        .clk(clk),
        .data_bus(data_bus),
        .address_bus(address_bus[10:0]),
        .enable(cs_ram),
        .write(write),
        .read(read));
        
    Cpu cpu(
        .clk(clk),
        .reset(reset),
        .data_bus(data_bus),
        .address_bus(address_bus),
        .r(read),
        .w(write),
        .interrupts(interrupts),
        .halt(halt));
endmodule