data/full_repos/permissive/520428138/verilog/rtl/user_module_341449297858921043.v
data/verilator_xmls/020d8554-5eeb-4e1c-bd26-5f3fc772a588.xml
module user_module_341449297858921043(
	input [7:0] io_in, 
	output [7:0] io_out
);

	wire [10:0] result;
	assign io_out = result[7:0];

  	anfsqrt_sqrt_341449297858921043 sqrt_core(
		.clk(io_in[0]),
		.query({io_in[7:1], 4'b0}),
		.result(result)
  	);

endmodule
module user_module_341449297858921043(
	input [7:0] io_in, 
	output [7:0] io_out
);


	wire [10:0] result;
	assign io_out = result[7:0];

  	anfsqrt_sqrt_341449297858921043 sqrt_core(
		.clk(io_in[0]),
		.query({io_in[7:1], 4'b0}),
		.result(result)
  	);

endmodule