data/full_repos/permissive/441359809/src/yosys/examples/smtbmc/demo1.v
data/verilator_xmls/5695c72b-2254-4292-8577-b22bd1432bea.xml
module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y);
	assign iseven = !a[0];
	assign y = a + (addtwo ? 2 : 1);
endmodule
module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y);

	assign iseven = !a[0];
	assign y = a + (addtwo ? 2 : 1);
endmodule