data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:447: Define or directive not defined: \'`CACHE_SIZE\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:447: syntax error, unexpected \'/\', expecting \')\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                                    ^\n%Error: Exiting due to 3 error(s)\n'
module DRAM_conX#(
              parameter APP_ADDR_WIDTH  = 28,
              parameter APP_CMD_WIDTH   = 3,
              parameter APP_DATA_WIDTH  = 128,
              parameter APP_MASK_WIDTH  = 16)
    (

     output wire [3:0] s_axi_awid,
     output wire [APP_ADDR_WIDTH-1:0] s_axi_awaddr,
     output wire [7:0] s_axi_awlen,
     output wire [2:0] s_axi_awsize,
     output wire [1:0] s_axi_awburst,
     output wire [0:0] s_axi_awlock,
     output wire [3:0] s_axi_awcache,
     output wire [2:0] s_axi_awprot,
     output wire [3:0] s_axi_awqos,
     output wire s_axi_awvalid,
     input wire s_axi_awready,

     output wire [APP_DATA_WIDTH-1:0] s_axi_wdata,
     output wire [APP_MASK_WIDTH-1:0] s_axi_wstrb,
     output wire s_axi_wlast,
     output wire s_axi_wvalid,
     input wire s_axi_wready,

     input wire [3:0] s_axi_bid,
     input wire [1:0] s_axi_bresp,
     input wire s_axi_bvalid,
     output wire s_axi_bready,

     output wire [3:0] s_axi_arid,
     output wire [APP_ADDR_WIDTH-1:0] s_axi_araddr,
     output wire [7:0] s_axi_arlen,
     output wire [2:0] s_axi_arsize,
     output wire [1:0] s_axi_arburst,
     output wire [0:0] s_axi_arlock,
     output wire [3:0] s_axi_arcache,
     output wire [2:0] s_axi_arprot,
     output wire [3:0] s_axi_arqos,
     output wire s_axi_arvalid,
     input wire s_axi_arready,

     input wire [3:0] s_axi_rid,
     input wire [APP_DATA_WIDTH-1:0] s_axi_rdata,
     input wire [1:0] s_axi_rresp,
     input wire s_axi_rlast,
     input wire s_axi_rvalid,
     output wire s_axi_rready,

     input wire mig_ui_clk,
     input wire mig_ui_rst_x,
     input wire dram_init_calib_complete,


     input wire                         i_clk,
     input wire                         i_rst_x,

     input  wire                         i_rd_en,
     input  wire                         i_wr_en,
     input  wire [31:0]                  i_addr,
     input  wire [31:0]                  i_data,
     input  wire                         i_init_calib_complete,
     output wire[127:0]                  o_data,
     output wire                         o_busy,
     input  wire [3:0]                   i_mask);





    wire        w_dram_stall;
    wire        w_dram_le;
    wire        w_dram_we;
    wire [31:0] w_dram_addr;
    wire [31:0] w_dram_idata;
    wire[127:0] w_dram_odata;


    wire        c_oe;
    wire        c_clr;
    wire        c_we;
    wire [31:0] c_addr;
    wire[127:0] c_idata;
    wire[127:0] c_odata;

    cach_controller cach_controller(
        .clk(i_clk),
        .rst_x(i_rst_x),
        .i_rd_en(i_rd_en),
        .i_wr_en(i_wr_en),
        .i_addr(i_addr),
        .i_data(i_data),
        .o_data(o_data),
        .o_busy(o_busy),
        .i_mask(i_mask),
        .cach_hit(c_oe),
        .cach_we(c_we),
        .cach_addr(c_addr),
        .cach_wdata(c_idata),
        .cach_rdata(c_odata),
        .dram_stall(w_dram_stall),
        .dram_le(w_dram_le),
        .dram_we(w_dram_we),
        .dram_rdata(w_dram_odata),
        .dram_wdata(w_dram_idata),
        .dram_addr(w_dram_addr)
        );

    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1'b1, 1'b0, c_clr, c_we,
                                c_addr[31:4], c_idata, c_odata, c_oe);

    DRAM_Wrapper2#(
                   .APP_ADDR_WIDTH(APP_ADDR_WIDTH),
                   .APP_CMD_WIDTH(APP_CMD_WIDTH),
                   .APP_DATA_WIDTH(APP_DATA_WIDTH),
                   .APP_MASK_WIDTH(APP_MASK_WIDTH))
    dram (

	       .s_axi_awid                     (s_axi_awid),
	       .s_axi_awaddr                   (s_axi_awaddr),
	       .s_axi_awlen                    (s_axi_awlen),
	       .s_axi_awsize                   (s_axi_awsize),
	       .s_axi_awburst                  (s_axi_awburst),
	       .s_axi_awlock                   (s_axi_awlock),
	       .s_axi_awcache                  (s_axi_awcache),
	       .s_axi_awprot                   (s_axi_awprot),
	       .s_axi_awqos                    (s_axi_awqos),
	       .s_axi_awvalid                  (s_axi_awvalid),
	       .s_axi_awready                  (s_axi_awready),

	       .s_axi_wdata                    (s_axi_wdata),
	       .s_axi_wstrb                    (s_axi_wstrb),
	       .s_axi_wlast                    (s_axi_wlast),
	       .s_axi_wvalid                   (s_axi_wvalid),
	       .s_axi_wready                   (s_axi_wready),

	       .s_axi_bid                      (s_axi_bid),
	       .s_axi_bresp                    (s_axi_bresp),
	       .s_axi_bvalid                   (s_axi_bvalid),
	       .s_axi_bready                   (s_axi_bready),

	       .s_axi_arid                     (s_axi_arid),
	       .s_axi_araddr                   (s_axi_araddr),
	       .s_axi_arlen                    (s_axi_arlen),
	       .s_axi_arsize                   (s_axi_arsize),
	       .s_axi_arburst                  (s_axi_arburst),
	       .s_axi_arlock                   (s_axi_arlock),
	       .s_axi_arcache                  (s_axi_arcache),
	       .s_axi_arprot                   (s_axi_arprot),
	       .s_axi_arqos                    (s_axi_arqos),
	       .s_axi_arvalid                  (s_axi_arvalid),
	       .s_axi_arready                  (s_axi_arready),

	       .s_axi_rid                      (s_axi_rid),
	       .s_axi_rdata                    (s_axi_rdata),
	       .s_axi_rresp                    (s_axi_rresp),
	       .s_axi_rlast                    (s_axi_rlast),
	       .s_axi_rvalid                   (s_axi_rvalid),
	       .s_axi_rready                   (s_axi_rready),
	       .mig_ui_clk(mig_ui_clk),
	       .mig_ui_rst_x(mig_ui_rst_x),
	       .dram_init_calib_complete(dram_init_calib_complete),


               .i_clk(i_clk),
               .i_rst_x(i_rst_x),

               .i_rd_en(w_dram_le),
               .i_wr_en(w_dram_we),
               .i_addr(w_dram_addr),
               .i_data(w_dram_idata),
               .i_init_calib_complete(i_init_calib_complete),
               .o_data(w_dram_odata),
               .o_busy(w_dram_stall),
               .i_mask(i_mask)
               );

endmodule
module DRAM_conX#(
              parameter APP_ADDR_WIDTH  = 28,
              parameter APP_CMD_WIDTH   = 3,
              parameter APP_DATA_WIDTH  = 128,
              parameter APP_MASK_WIDTH  = 16)
    (

     output wire [3:0] s_axi_awid,
     output wire [APP_ADDR_WIDTH-1:0] s_axi_awaddr,
     output wire [7:0] s_axi_awlen,
     output wire [2:0] s_axi_awsize,
     output wire [1:0] s_axi_awburst,
     output wire [0:0] s_axi_awlock,
     output wire [3:0] s_axi_awcache,
     output wire [2:0] s_axi_awprot,
     output wire [3:0] s_axi_awqos,
     output wire s_axi_awvalid,
     input wire s_axi_awready,

     output wire [APP_DATA_WIDTH-1:0] s_axi_wdata,
     output wire [APP_MASK_WIDTH-1:0] s_axi_wstrb,
     output wire s_axi_wlast,
     output wire s_axi_wvalid,
     input wire s_axi_wready,

     input wire [3:0] s_axi_bid,
     input wire [1:0] s_axi_bresp,
     input wire s_axi_bvalid,
     output wire s_axi_bready,

     output wire [3:0] s_axi_arid,
     output wire [APP_ADDR_WIDTH-1:0] s_axi_araddr,
     output wire [7:0] s_axi_arlen,
     output wire [2:0] s_axi_arsize,
     output wire [1:0] s_axi_arburst,
     output wire [0:0] s_axi_arlock,
     output wire [3:0] s_axi_arcache,
     output wire [2:0] s_axi_arprot,
     output wire [3:0] s_axi_arqos,
     output wire s_axi_arvalid,
     input wire s_axi_arready,

     input wire [3:0] s_axi_rid,
     input wire [APP_DATA_WIDTH-1:0] s_axi_rdata,
     input wire [1:0] s_axi_rresp,
     input wire s_axi_rlast,
     input wire s_axi_rvalid,
     output wire s_axi_rready,

     input wire mig_ui_clk,
     input wire mig_ui_rst_x,
     input wire dram_init_calib_complete,


     input wire                         i_clk,
     input wire                         i_rst_x,

     input  wire                         i_rd_en,
     input  wire                         i_wr_en,
     input  wire [31:0]                  i_addr,
     input  wire [31:0]                  i_data,
     input  wire                         i_init_calib_complete,
     output wire[127:0]                  o_data,
     output wire                         o_busy,
     input  wire [3:0]                   i_mask);






    wire        w_dram_stall;
    wire        w_dram_le;
    wire        w_dram_we;
    wire [31:0] w_dram_addr;
    wire [31:0] w_dram_idata;
    wire[127:0] w_dram_odata;


    wire        c_oe;
    wire        c_clr;
    wire        c_we;
    wire [31:0] c_addr;
    wire[127:0] c_idata;
    wire[127:0] c_odata;

    cach_controller cach_controller(
        .clk(i_clk),
        .rst_x(i_rst_x),
        .i_rd_en(i_rd_en),
        .i_wr_en(i_wr_en),
        .i_addr(i_addr),
        .i_data(i_data),
        .o_data(o_data),
        .o_busy(o_busy),
        .i_mask(i_mask),
        .cach_hit(c_oe),
        .cach_we(c_we),
        .cach_addr(c_addr),
        .cach_wdata(c_idata),
        .cach_rdata(c_odata),
        .dram_stall(w_dram_stall),
        .dram_le(w_dram_le),
        .dram_we(w_dram_we),
        .dram_rdata(w_dram_odata),
        .dram_wdata(w_dram_idata),
        .dram_addr(w_dram_addr)
        );

    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1'b1, 1'b0, c_clr, c_we,
                                c_addr[31:4], c_idata, c_odata, c_oe);

    DRAM_Wrapper2#(
                   .APP_ADDR_WIDTH(APP_ADDR_WIDTH),
                   .APP_CMD_WIDTH(APP_CMD_WIDTH),
                   .APP_DATA_WIDTH(APP_DATA_WIDTH),
                   .APP_MASK_WIDTH(APP_MASK_WIDTH))
    dram (

	       .s_axi_awid                     (s_axi_awid),
	       .s_axi_awaddr                   (s_axi_awaddr),
	       .s_axi_awlen                    (s_axi_awlen),
	       .s_axi_awsize                   (s_axi_awsize),
	       .s_axi_awburst                  (s_axi_awburst),
	       .s_axi_awlock                   (s_axi_awlock),
	       .s_axi_awcache                  (s_axi_awcache),
	       .s_axi_awprot                   (s_axi_awprot),
	       .s_axi_awqos                    (s_axi_awqos),
	       .s_axi_awvalid                  (s_axi_awvalid),
	       .s_axi_awready                  (s_axi_awready),

	       .s_axi_wdata                    (s_axi_wdata),
	       .s_axi_wstrb                    (s_axi_wstrb),
	       .s_axi_wlast                    (s_axi_wlast),
	       .s_axi_wvalid                   (s_axi_wvalid),
	       .s_axi_wready                   (s_axi_wready),

	       .s_axi_bid                      (s_axi_bid),
	       .s_axi_bresp                    (s_axi_bresp),
	       .s_axi_bvalid                   (s_axi_bvalid),
	       .s_axi_bready                   (s_axi_bready),

	       .s_axi_arid                     (s_axi_arid),
	       .s_axi_araddr                   (s_axi_araddr),
	       .s_axi_arlen                    (s_axi_arlen),
	       .s_axi_arsize                   (s_axi_arsize),
	       .s_axi_arburst                  (s_axi_arburst),
	       .s_axi_arlock                   (s_axi_arlock),
	       .s_axi_arcache                  (s_axi_arcache),
	       .s_axi_arprot                   (s_axi_arprot),
	       .s_axi_arqos                    (s_axi_arqos),
	       .s_axi_arvalid                  (s_axi_arvalid),
	       .s_axi_arready                  (s_axi_arready),

	       .s_axi_rid                      (s_axi_rid),
	       .s_axi_rdata                    (s_axi_rdata),
	       .s_axi_rresp                    (s_axi_rresp),
	       .s_axi_rlast                    (s_axi_rlast),
	       .s_axi_rvalid                   (s_axi_rvalid),
	       .s_axi_rready                   (s_axi_rready),
	       .mig_ui_clk(mig_ui_clk),
	       .mig_ui_rst_x(mig_ui_rst_x),
	       .dram_init_calib_complete(dram_init_calib_complete),


               .i_clk(i_clk),
               .i_rst_x(i_rst_x),

               .i_rd_en(w_dram_le),
               .i_wr_en(w_dram_we),
               .i_addr(w_dram_addr),
               .i_data(w_dram_idata),
               .i_init_calib_complete(i_init_calib_complete),
               .o_data(w_dram_odata),
               .o_busy(w_dram_stall),
               .i_mask(i_mask)
               );

endmodule