data/full_repos/permissive/454159683/mul4bc/mul4bc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bc/mul4bc.v:26: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 4 bits.\n                                                                       : ... In instance mul4bc\n  r0 = y[0] ? x : 0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bc/mul4bc.v:27: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                       : ... In instance mul4bc\n  r1 = y[1] ? {x, 1\'b0} : 0;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/mul4bc/mul4bc.v:28: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s REPLICATE generates 6 bits.\n                                                                       : ... In instance mul4bc\n  r2 = y[2] ? {x, 2\'b00} : 0;\n            ^\n%Error: Exiting due to 3 warning(s)\n'
module mul4bc(input[3:0] x, y, output[7:0] out);
	reg[6:0] r0, r1, r2, r3;	















	
	always @(x or y)
	begin
		r0 = y[0] ? x : 0;
		r1 = y[1] ? {x, 1'b0} : 0;
		r2 = y[2] ? {x, 2'b00} : 0;
		r3 = y[3] ? {x, 3'b000} : 0;
	end

















	assign out = r0 + r1 + r2 + r3;
endmodule
module mul4bc(input[3:0] x, y, output[7:0] out);

	reg[6:0] r0, r1, r2, r3;	















	
	always @(x or y)
	begin
		r0 = y[0] ? x : 0;
		r1 = y[1] ? {x, 1'b0} : 0;
		r2 = y[2] ? {x, 2'b00} : 0;
		r3 = y[3] ? {x, 3'b000} : 0;
	end

















	assign out = r0 + r1 + r2 + r3;
endmodule