data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v
1: b"%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:99: Cannot find file containing module: 'fpu_mul'\nfpu_mul x0_mul\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic,data/full_repos/permissive/49670587/fpu_mul\n             data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic,data/full_repos/permissive/49670587/fpu_mul.v\n             data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic,data/full_repos/permissive/49670587/fpu_mul.sv\n             fpu_mul\n             fpu_mul.v\n             fpu_mul.sv\n             obj_dir/fpu_mul\n             obj_dir/fpu_mul.v\n             obj_dir/fpu_mul.sv\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:110: Cannot find file containing module: 'fpu_mul'\nfpu_mul x1_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:122: Cannot find file containing module: 'fpu_mul'\nfpu_mul x2_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:133: Cannot find file containing module: 'fpu_add'\nfpu_add a0_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:145: Cannot find file containing module: 'fpu_add'\nfpu_add a1_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:156: Cannot find file containing module: 'fpu_add'\nfpu_add a2_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:167: Cannot find file containing module: 'fpu_mul'\nfpu_mul x3_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:179: Cannot find file containing module: 'fpu_mul'\nfpu_mul x4_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:191: Cannot find file containing module: 'fpu_mul'\nfpu_mul x5_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:202: Cannot find file containing module: 'fpu_mul'\nfpu_mul x6_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:213: Cannot find file containing module: 'fpu_mul'\nfpu_mul x7_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:224: Cannot find file containing module: 'fpu_mul'\nfpu_mul x8_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:235: Cannot find file containing module: 'fpu_add'\nfpu_add a3_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:246: Cannot find file containing module: 'fpu_add'\nfpu_add a4_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:258: Cannot find file containing module: 'fpu_add'\nfpu_add a5_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:269: Cannot find file containing module: 'fpu_add'\nfpu_add a6_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:282: Cannot find file containing module: 'fpu_mul'\nfpu_mul x9_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:293: Cannot find file containing module: 'fpu_add'\nfpu_add a7_add\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:309: Cannot find file containing module: 'fpu_mul'\nfpu_mul x10_mul\n^~~~~~~\n%Error: data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/fpu/hardlogic/bgm.v:320: Cannot find file containing module: 'fpu_add'\nfpu_add a8_add\n^~~~~~~\n%Error: Exiting due to 20 error(s)\n"
module delay5 (clock, d5_delay_in, d5_delay_out);
	input clock;
	input [`BITS-1:0] d5_delay_in;
	output [`BITS-1:0] d5_delay_out;


	reg [`BITS-1:0] d5_reg1;


	assign d5_delay_out = d5_reg1;

	always @(posedge clock)
	begin
		d5_reg1 <= d5_delay_in;

	end
endmodule
module delay5 (clock, d5_delay_in, d5_delay_out);

	input clock;
	input [`BITS-1:0] d5_delay_in;
	output [`BITS-1:0] d5_delay_out;


	reg [`BITS-1:0] d5_reg1;


	assign d5_delay_out = d5_reg1;

	always @(posedge clock)
	begin
		d5_reg1 <= d5_delay_in;

	end
endmodule