data/full_repos/permissive/415843050/cpu-src/control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:53: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                         : ... In instance Control\n    assign opcode = Instruction[31:26];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:54: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance Control\n    assign rs = Instruction[25:21];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:55: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance Control\n    assign rt = Instruction[20:16];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:56: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance Control\n    assign rd = Instruction[15:11];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:57: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance Control\n    assign shamt = Instruction[10:6];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:58: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                         : ... In instance Control\n    assign func = Instruction[5:0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:59: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                         : ... In instance Control\n    assign immediate = Instruction[15:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:64: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign r_format = (opcode == 6\'b000000 || opcode == 6\'b010000 ) ? 1\'b1 : 1\'b0;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:64: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign r_format = (opcode == 6\'b000000 || opcode == 6\'b010000 ) ? 1\'b1 : 1\'b0;\n                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:78: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jmp = (opcode == 6\'b000010) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:79: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h3\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jal = (opcode == 6\'b000011) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:80: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jr = (opcode == 6\'b000000 && func == 6\'b001000) ? 1\'b1 : 1\'b0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:80: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jr = (opcode == 6\'b000000 && func == 6\'b001000) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:81: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jalr = (opcode == 6\'b000000 && func == 6\'b001001) ? 1\'b1 : 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:81: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h9\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Jalr = (opcode == 6\'b000000 && func == 6\'b001001) ? 1\'b1 : 1\'b0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:84: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Beq = (opcode == 6\'b000100) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:85: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h5\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bne = (opcode == 6\'b000101) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:86: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bgez = (opcode == 6\'b000001 && rt == 5\'b00001) ? 1\'b1 : 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:86: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Bgez = (opcode == 6\'b000001 && rt == 5\'b00001) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:87: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h7\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bgtz = (opcode == 6\'b000111 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:87: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Bgtz = (opcode == 6\'b000111 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:88: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Blez = (opcode == 6\'b000110 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:88: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Blez = (opcode == 6\'b000110 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:89: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bltz = (opcode == 6\'b000001 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:89: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Bltz = (opcode == 6\'b000001 && rt == 5\'b00000) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:90: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bgezal = (opcode == 6\'b000001 && rt == 5\'b10001) ? 1\'b1 : 1\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:90: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h11\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Bgezal = (opcode == 6\'b000001 && rt == 5\'b10001) ? 1\'b1 : 1\'b0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:91: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Bltzal = (opcode == 6\'b000001 && rt == 5\'b10000) ? 1\'b1 : 1\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:91: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Bltzal = (opcode == 6\'b000001 && rt == 5\'b10000) ? 1\'b1 : 1\'b0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:94: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Mfhi = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:94: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mfhi = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:94: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mfhi = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:95: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010000) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:95: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                         : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010000) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:96: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Mflo = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:96: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mflo = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:96: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mflo = (opcode == 6\'b000000 && rs == 5\'b00000 && rt == 5\'b00000 &&\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:97: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010010) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:97: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n                                                                         : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010010) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:98: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                         : ... In instance Control\n    assign Mfc0 = (opcode == 6\'b010000 && rs == 5\'b00000 && shamt == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:98: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mfc0 = (opcode == 6\'b010000 && rs == 5\'b00000 && shamt == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:98: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance Control\n    assign Mfc0 = (opcode == 6\'b010000 && rs == 5\'b00000 && shamt == 5\'b00000 &&\n                                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:100: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Mthi = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:100: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mthi = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:100: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mthi = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:101: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010001) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:101: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h11\' generates 6 bits.\n                                                                          : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010001) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:102: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Mtlo = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:102: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mtlo = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:102: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mtlo = (opcode == 6\'b000000 && rt == 5\'b00000 && rd == 5\'b00000 &&\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:103: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010011) ? 1\'b1 : 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:103: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h13\' generates 6 bits.\n                                                                          : ... In instance Control\n                   shamt == 5\'b00000 && func == 6\'b010011) ? 1\'b1 : 1\'b0;\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:104: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Mtc0 = (opcode == 6\'b010000 && rs == 5\'b00100 && shamt == 5\'b00000 &&\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:104: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h4\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mtc0 = (opcode == 6\'b010000 && rs == 5\'b00100 && shamt == 5\'b00000 &&\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:104: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n    assign Mtc0 = (opcode == 6\'b010000 && rs == 5\'b00100 && shamt == 5\'b00000 &&\n                                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:123: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n                                                                          : ... In instance Control\n    assign Register_write_sel = Mfc0 ? rt : (r_format ? rd : rt);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:131: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Shift = (opcode == 6\'b000000 && func[5:3] == 3\'b000 && func[2:0] != 3\'b001)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:152: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Break = (opcode == 6\'b000000 && func == 6\'b001101) ? 1\'b1 : 1\'b0;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:152: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'hd\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Break = (opcode == 6\'b000000 && func == 6\'b001101) ? 1\'b1 : 1\'b0;\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:155: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Syscall = (opcode == 6\'b000000 && func == 6\'b001100) ? 1\'b1 : 1\'b0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:155: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n                                                                          : ... In instance Control\n    assign Syscall = (opcode == 6\'b000000 && func == 6\'b001100) ? 1\'b1 : 1\'b0;\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:164: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                          : ... In instance Control\n                    (opcode == 6\'b000000 &&\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:169: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                            (func[5:2] == 4\'b0110 && rd == 5\'b00000 && shamt == 5\'b00000) ||\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:169: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                            (func[5:2] == 4\'b0110 && rd == 5\'b00000 && shamt == 5\'b00000) ||\n                                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:173: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                            (func[5:1] == 5\'b10101 && shamt == 5\'b00000) ||\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:175: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                            (func[5:2] == 4\'b0000 && rs == 5\'b00000) ||\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/415843050/cpu-src/control.v:176: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                          : ... In instance Control\n                            (func[5:2] == 4\'b0001 && shamt == 5\'b00000)\n                                                           ^~\n%Error: Exiting due to 67 warning(s)\n'
module Control(
    Instruction,
    I_type,Jmp,Jr,Jal,Jalr,
    Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal,
    Register_write,Register_write_sel,
    Memory_or_IO,
    Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0,
    Shift,ALU_op,ALU_src,Memory_sign,Memory_data_width,
    Break,Syscall,Eret,
    Reserved_instruction,
    L_type,S_type
    );

    input[31:0] Instruction;
    
    output      I_type;
    output      Jmp,Jr,Jal,Jalr;
    output      Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    output      Register_write;
    output[4:0] Register_write_sel;
    output      Memory_or_IO;
    output      Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0;
    output      Shift;
    output[1:0] ALU_op;
    output      ALU_src;
    output      Memory_sign;
    output[1:0] Memory_data_width;
    output      Break,Syscall,Eret;
    output      Reserved_instruction;
    output      L_type,S_type;
    
    wire[6:0]   opcode,func;
    wire[5:0]   rs,rt, rd,shamt;
    wire[16:0]  immediate;
    
    wire r_format;
    wire i_type,l_type,s_type,b_type;
    wire Jmp,Jr,Jal,Jalr;
    wire Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    wire Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0;
    wire Shift;
    
    
    

    assign opcode = Instruction[31:26];
    assign rs = Instruction[25:21];
    assign rt = Instruction[20:16];
    assign rd = Instruction[15:11];
    assign shamt = Instruction[10:6];
    assign func = Instruction[5:0];
    assign immediate = Instruction[15:0];
    
    
    

    assign r_format = (opcode == 6'b000000 || opcode == 6'b010000) ? 1'b1 : 1'b0;
    





    assign i_type = opcode[5:3] == 3'b001 ? 1'b1 : 1'b0;
    assign l_type = opcode[5:3] == 3'b100 ? 1'b1 : 1'b0;
    assign s_type = opcode[5:3] == 3'b101 ? 1'b1 : 1'b0;
    assign b_type = opcode[5:3] == 3'b000 ? 1'b1 : 1'b0;
    assign I_type = i_type;
    

    assign Jmp = (opcode == 6'b000010) ? 1'b1 : 1'b0;
    assign Jal = (opcode == 6'b000011) ? 1'b1 : 1'b0;
    assign Jr = (opcode == 6'b000000 && func == 6'b001000) ? 1'b1 : 1'b0;
    assign Jalr = (opcode == 6'b000000 && func == 6'b001001) ? 1'b1 : 1'b0;
    

    assign Beq = (opcode == 6'b000100) ? 1'b1 : 1'b0;
    assign Bne = (opcode == 6'b000101) ? 1'b1 : 1'b0;
    assign Bgez = (opcode == 6'b000001 && rt == 5'b00001) ? 1'b1 : 1'b0;
    assign Bgtz = (opcode == 6'b000111 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Blez = (opcode == 6'b000110 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Bltz = (opcode == 6'b000001 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Bgezal = (opcode == 6'b000001 && rt == 5'b10001) ? 1'b1 : 1'b0;
    assign Bltzal = (opcode == 6'b000001 && rt == 5'b10000) ? 1'b1 : 1'b0;
    

    assign Mfhi = (opcode == 6'b000000 && rs == 5'b00000 && rt == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010000) ? 1'b1 : 1'b0;
    assign Mflo = (opcode == 6'b000000 && rs == 5'b00000 && rt == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010010) ? 1'b1 : 1'b0;
    assign Mfc0 = (opcode == 6'b010000 && rs == 5'b00000 && shamt == 5'b00000 &&
                   func[5:3] == 3'b000) ? 1'b1 : 1'b0;
    assign Mthi = (opcode == 6'b000000 && rt == 5'b00000 && rd == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010001) ? 1'b1 : 1'b0;
    assign Mtlo = (opcode == 6'b000000 && rt == 5'b00000 && rd == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010011) ? 1'b1 : 1'b0;
    assign Mtc0 = (opcode == 6'b010000 && rs == 5'b00100 && shamt == 5'b00000 &&
                   func[5:3] == 3'b000) ? 1'b1 : 1'b0;
    





    assign Register_write = r_format 
        ? (
            (func[5:3] == 3'b100 || Mfhi || Mflo || Mfc0 || Shift ||
             func[5:1] == 5'b10101 || Jalr) ? 1'b1 : 1'b0
          )
        : (
            (i_type || l_type || Bgezal || Bltzal || Jal) ? 1'b1 : 1'b0
          );
    


    assign Register_write_sel = Mfc0 ? rt : (r_format ? rd : rt);
    


    assign Memory_or_IO = l_type;
    


    assign Shift = (opcode == 6'b000000 && func[5:3] == 3'b000 && func[2:0] != 3'b001)
                   ? 1'b1 : 1'b0;
    


    assign ALU_op = {
                        (r_format || i_type),
                        (Beq || Bne || Bgez || Bgtz || Blez ||Bltz || Bgezal || Bltzal)
                    };
    


    assign ALU_src = i_type || l_type || s_type;
    

    assign Memory_sign = opcode[2];
    

    assign Memory_data_width = opcode[1:0];
    

    assign Break = (opcode == 6'b000000 && func == 6'b001101) ? 1'b1 : 1'b0;
    

    assign Syscall = (opcode == 6'b000000 && func == 6'b001100) ? 1'b1 : 1'b0;
    

    assign Eret = (Instruction == 32'b010000_1000_0000_0000_0000_0000_011000) ? 1'b1 : 1'b0;
    

    assign Reserved_instruction =
            (
                (r_format && 
                    (opcode == 6'b000000 &&
                        (

                            func[5:3] == 3'b100 ||

                            (func[5:2] == 4'b0110 && rd == 5'b00000 && shamt == 5'b00000) ||

                            Mfhi || Mflo || Mthi || Mtlo ||

                            (func[5:1] == 5'b10101 && shamt == 5'b00000) ||

                            (func[5:2] == 4'b0000 && rs == 5'b00000) ||
                            (func[5:2] == 4'b0001 && shamt == 5'b00000)
                        ) ||
                        Mfc0 || Mtc0 || Jr || Jalr || Break || Syscall || Eret
                    )
                ) ||
                (
                    i_type || l_type || s_type ||
                    Beq || Bne || Bgez || Bgtz || Blez || Bltz || Bgezal || Bltzal
                ) ||
                (
                    Jmp || Jal
                ) ||
                (
                    Instruction == 32'h00000000
                )
            )
            ? 1'b0 : 1'b1;
    
    assign L_type = l_type;
    assign S_type = s_type;
    
endmodule
module Control(
    Instruction,
    I_type,Jmp,Jr,Jal,Jalr,
    Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal,
    Register_write,Register_write_sel,
    Memory_or_IO,
    Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0,
    Shift,ALU_op,ALU_src,Memory_sign,Memory_data_width,
    Break,Syscall,Eret,
    Reserved_instruction,
    L_type,S_type
    );


    input[31:0] Instruction;
    
    output      I_type;
    output      Jmp,Jr,Jal,Jalr;
    output      Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    output      Register_write;
    output[4:0] Register_write_sel;
    output      Memory_or_IO;
    output      Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0;
    output      Shift;
    output[1:0] ALU_op;
    output      ALU_src;
    output      Memory_sign;
    output[1:0] Memory_data_width;
    output      Break,Syscall,Eret;
    output      Reserved_instruction;
    output      L_type,S_type;
    
    wire[6:0]   opcode,func;
    wire[5:0]   rs,rt, rd,shamt;
    wire[16:0]  immediate;
    
    wire r_format;
    wire i_type,l_type,s_type,b_type;
    wire Jmp,Jr,Jal,Jalr;
    wire Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    wire Mfhi,Mflo,Mfc0,Mthi,Mtlo,Mtc0;
    wire Shift;
    
    
    

    assign opcode = Instruction[31:26];
    assign rs = Instruction[25:21];
    assign rt = Instruction[20:16];
    assign rd = Instruction[15:11];
    assign shamt = Instruction[10:6];
    assign func = Instruction[5:0];
    assign immediate = Instruction[15:0];
    
    
    

    assign r_format = (opcode == 6'b000000 || opcode == 6'b010000) ? 1'b1 : 1'b0;
    





    assign i_type = opcode[5:3] == 3'b001 ? 1'b1 : 1'b0;
    assign l_type = opcode[5:3] == 3'b100 ? 1'b1 : 1'b0;
    assign s_type = opcode[5:3] == 3'b101 ? 1'b1 : 1'b0;
    assign b_type = opcode[5:3] == 3'b000 ? 1'b1 : 1'b0;
    assign I_type = i_type;
    

    assign Jmp = (opcode == 6'b000010) ? 1'b1 : 1'b0;
    assign Jal = (opcode == 6'b000011) ? 1'b1 : 1'b0;
    assign Jr = (opcode == 6'b000000 && func == 6'b001000) ? 1'b1 : 1'b0;
    assign Jalr = (opcode == 6'b000000 && func == 6'b001001) ? 1'b1 : 1'b0;
    

    assign Beq = (opcode == 6'b000100) ? 1'b1 : 1'b0;
    assign Bne = (opcode == 6'b000101) ? 1'b1 : 1'b0;
    assign Bgez = (opcode == 6'b000001 && rt == 5'b00001) ? 1'b1 : 1'b0;
    assign Bgtz = (opcode == 6'b000111 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Blez = (opcode == 6'b000110 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Bltz = (opcode == 6'b000001 && rt == 5'b00000) ? 1'b1 : 1'b0;
    assign Bgezal = (opcode == 6'b000001 && rt == 5'b10001) ? 1'b1 : 1'b0;
    assign Bltzal = (opcode == 6'b000001 && rt == 5'b10000) ? 1'b1 : 1'b0;
    

    assign Mfhi = (opcode == 6'b000000 && rs == 5'b00000 && rt == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010000) ? 1'b1 : 1'b0;
    assign Mflo = (opcode == 6'b000000 && rs == 5'b00000 && rt == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010010) ? 1'b1 : 1'b0;
    assign Mfc0 = (opcode == 6'b010000 && rs == 5'b00000 && shamt == 5'b00000 &&
                   func[5:3] == 3'b000) ? 1'b1 : 1'b0;
    assign Mthi = (opcode == 6'b000000 && rt == 5'b00000 && rd == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010001) ? 1'b1 : 1'b0;
    assign Mtlo = (opcode == 6'b000000 && rt == 5'b00000 && rd == 5'b00000 &&
                   shamt == 5'b00000 && func == 6'b010011) ? 1'b1 : 1'b0;
    assign Mtc0 = (opcode == 6'b010000 && rs == 5'b00100 && shamt == 5'b00000 &&
                   func[5:3] == 3'b000) ? 1'b1 : 1'b0;
    





    assign Register_write = r_format 
        ? (
            (func[5:3] == 3'b100 || Mfhi || Mflo || Mfc0 || Shift ||
             func[5:1] == 5'b10101 || Jalr) ? 1'b1 : 1'b0
          )
        : (
            (i_type || l_type || Bgezal || Bltzal || Jal) ? 1'b1 : 1'b0
          );
    


    assign Register_write_sel = Mfc0 ? rt : (r_format ? rd : rt);
    


    assign Memory_or_IO = l_type;
    


    assign Shift = (opcode == 6'b000000 && func[5:3] == 3'b000 && func[2:0] != 3'b001)
                   ? 1'b1 : 1'b0;
    


    assign ALU_op = {
                        (r_format || i_type),
                        (Beq || Bne || Bgez || Bgtz || Blez ||Bltz || Bgezal || Bltzal)
                    };
    


    assign ALU_src = i_type || l_type || s_type;
    

    assign Memory_sign = opcode[2];
    

    assign Memory_data_width = opcode[1:0];
    

    assign Break = (opcode == 6'b000000 && func == 6'b001101) ? 1'b1 : 1'b0;
    

    assign Syscall = (opcode == 6'b000000 && func == 6'b001100) ? 1'b1 : 1'b0;
    

    assign Eret = (Instruction == 32'b010000_1000_0000_0000_0000_0000_011000) ? 1'b1 : 1'b0;
    

    assign Reserved_instruction =
            (
                (r_format && 
                    (opcode == 6'b000000 &&
                        (

                            func[5:3] == 3'b100 ||

                            (func[5:2] == 4'b0110 && rd == 5'b00000 && shamt == 5'b00000) ||

                            Mfhi || Mflo || Mthi || Mtlo ||

                            (func[5:1] == 5'b10101 && shamt == 5'b00000) ||

                            (func[5:2] == 4'b0000 && rs == 5'b00000) ||
                            (func[5:2] == 4'b0001 && shamt == 5'b00000)
                        ) ||
                        Mfc0 || Mtc0 || Jr || Jalr || Break || Syscall || Eret
                    )
                ) ||
                (
                    i_type || l_type || s_type ||
                    Beq || Bne || Bgez || Bgtz || Blez || Bltz || Bgezal || Bltzal
                ) ||
                (
                    Jmp || Jal
                ) ||
                (
                    Instruction == 32'h00000000
                )
            )
            ? 1'b0 : 1'b1;
    
    assign L_type = l_type;
    assign S_type = s_type;
    
endmodule