data/full_repos/permissive/418819021/lab-05/state_machine.v
1: b'%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:8: Define or directive not defined: \'`STAGE_COUNT\'\n    output      reg [`STAGE_COUNT-1:0] pipeline_stage,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:12: Define or directive not defined: \'`GROUP_COUNT\'\n    input  wire     [`GROUP_COUNT-1:0] opcode_group\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:15: Define or directive not defined: \'`STAGE_COUNT\'\n    reg [`STAGE_COUNT-1:0] next_stage;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:22: Define or directive not defined: \'`STAGE_RESET\'\n            pipeline_stage <= `STAGE_RESET;\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            pipeline_stage <= `STAGE_RESET;\n                                          ^\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:38: Define or directive not defined: \'`STAGE_MEM\'\n        else if (pipeline_stage == `STAGE_MEM && opcode_group[`GROUP_TWO_CYCLE_MEM])\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:38: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        else if (pipeline_stage == `STAGE_MEM && opcode_group[`GROUP_TWO_CYCLE_MEM])\n                                              ^~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:38: Define or directive not defined: \'`GROUP_TWO_CYCLE_MEM\'\n        else if (pipeline_stage == `STAGE_MEM && opcode_group[`GROUP_TWO_CYCLE_MEM])\n                                                              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:45: Define or directive not defined: \'`STAGE_RESET\'\n            `STAGE_RESET:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:45: syntax error, unexpected \':\', expecting endcase\n            `STAGE_RESET:\n                        ^\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:46: Define or directive not defined: \'`STAGE_IF\'\n            next_stage = `STAGE_IF;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:47: Define or directive not defined: \'`STAGE_IF\'\n            `STAGE_IF:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:48: Define or directive not defined: \'`STAGE_ID\'\n            next_stage = `STAGE_ID;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:49: Define or directive not defined: \'`STAGE_ID\'\n            `STAGE_ID:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:50: Define or directive not defined: \'`STAGE_EX\'\n            next_stage = `STAGE_EX;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:51: Define or directive not defined: \'`STAGE_EX\'\n            `STAGE_EX:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:52: Define or directive not defined: \'`STAGE_MEM\'\n            next_stage = `STAGE_MEM;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:61: Define or directive not defined: \'`STAGE_MEM\'\n            `STAGE_MEM:\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:62: Define or directive not defined: \'`GROUP_TWO_CYCLE_MEM\'\n            if (opcode_group[`GROUP_TWO_CYCLE_MEM] && cycle_count == 0)\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:63: Define or directive not defined: \'`STAGE_MEM\'\n                next_stage = `STAGE_MEM;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:65: Define or directive not defined: \'`STAGE_WB\'\n                next_stage = `STAGE_WB;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:66: Define or directive not defined: \'`STAGE_WB\'\n            `STAGE_WB:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:67: Define or directive not defined: \'`STAGE_IF\'\n            next_stage = `STAGE_IF;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/state_machine.v:69: Define or directive not defined: \'`STAGE_RESET\'\n                next_stage = `STAGE_RESET;\n                             ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module state_machine (
    output      reg [`STAGE_COUNT-1:0] pipeline_stage,
    input  wire                        clk           ,
    input  wire                        reset         ,
    output      reg                    cycle_count   ,
    input  wire     [`GROUP_COUNT-1:0] opcode_group
);

    reg [`STAGE_COUNT-1:0] next_stage;


    always @(posedge clk, posedge reset)
        if (reset)
            pipeline_stage <= `STAGE_RESET;
        else
            pipeline_stage <= next_stage;


    always @(posedge clk, posedge reset) begin
        if (reset)
            cycle_count <= 0;

        else if (pipeline_stage == `STAGE_MEM && opcode_group[`GROUP_TWO_CYCLE_MEM])
            cycle_count <= ~cycle_count;
    end


    always @* begin
        case (pipeline_stage)
            `STAGE_RESET:
            next_stage = `STAGE_IF;
            `STAGE_IF:
            next_stage = `STAGE_ID;
            `STAGE_ID:
            next_stage = `STAGE_EX;
            `STAGE_EX:
            next_stage = `STAGE_MEM;

            `STAGE_MEM:
            if (opcode_group[`GROUP_TWO_CYCLE_MEM] && cycle_count == 0)
                next_stage = `STAGE_MEM;
            else
                next_stage = `STAGE_WB;
            `STAGE_WB:
            next_stage = `STAGE_IF;
            default:
                next_stage = `STAGE_RESET;
        endcase
    end

endmodule
module state_machine (
    output      reg [`STAGE_COUNT-1:0] pipeline_stage,
    input  wire                        clk           ,
    input  wire                        reset         ,
    output      reg                    cycle_count   ,
    input  wire     [`GROUP_COUNT-1:0] opcode_group
);


    reg [`STAGE_COUNT-1:0] next_stage;


    always @(posedge clk, posedge reset)
        if (reset)
            pipeline_stage <= `STAGE_RESET;
        else
            pipeline_stage <= next_stage;


    always @(posedge clk, posedge reset) begin
        if (reset)
            cycle_count <= 0;

        else if (pipeline_stage == `STAGE_MEM && opcode_group[`GROUP_TWO_CYCLE_MEM])
            cycle_count <= ~cycle_count;
    end


    always @* begin
        case (pipeline_stage)
            `STAGE_RESET:
            next_stage = `STAGE_IF;
            `STAGE_IF:
            next_stage = `STAGE_ID;
            `STAGE_ID:
            next_stage = `STAGE_EX;
            `STAGE_EX:
            next_stage = `STAGE_MEM;

            `STAGE_MEM:
            if (opcode_group[`GROUP_TWO_CYCLE_MEM] && cycle_count == 0)
                next_stage = `STAGE_MEM;
            else
                next_stage = `STAGE_WB;
            `STAGE_WB:
            next_stage = `STAGE_IF;
            default:
                next_stage = `STAGE_RESET;
        endcase
    end

endmodule