data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v
1: b'%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v:16: Cannot find include file: pa_chip_param.v\n`include "pa_chip_param.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/yuheng-riscv-env/tb,data/full_repos/permissive/485610894/pa_chip_param.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/tb,data/full_repos/permissive/485610894/pa_chip_param.v.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/tb,data/full_repos/permissive/485610894/pa_chip_param.v.sv\n             pa_chip_param.v\n             pa_chip_param.v.v\n             pa_chip_param.v.sv\n             obj_dir/pa_chip_param.v\n             obj_dir/pa_chip_param.v.v\n             obj_dir/pa_chip_param.v.sv\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v:56: syntax error, unexpected \'@\'\n    @ (posedge sys_clk) sys_rst_n = 0;\n    ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v:60: syntax error, unexpected \'@\'\n        @ (posedge sys_clk);\n        ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v:105: Define or directive not defined: \'`CPU_FREQ_HZ\'\nalways #((32\'d1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/tb/core_tb.v:105: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nalways #((32\'d1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;\n                                        ^\n%Error: Exiting due to 5 error(s)\n'
module core_tb(
    );

`include "pa_chip_param.v"

reg                             sys_clk;
reg                             sys_rst_n;

wire                            TXD;

initial begin
`ifdef DUMP_VCD
    $dumpfile("wave.vcd");
    $dumpvars(0, core_tb);
`endif
end

pa_chip_top u_pa_chip_top (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (),
    .txd                        (TXD)
);

core_uart_monitor_tb u_core_uart_monitor_tb (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (TXD),
    .txd                        ()
);

initial begin
    sys_clk = 1;
    sys_rst_n = 0;

`ifndef ROM_MODE_BRAM
    $readmemh("image.pat", u_pa_chip_top.u_pa_perips_rom._ram);
`endif
end

always begin
    @ (posedge sys_clk) sys_rst_n = 0;
    @ (posedge sys_clk) sys_rst_n = 1;

    while (1) begin
        @ (posedge sys_clk);
    end

    $stop();
end

`ifdef TEST_ISA

wire [`DATA_BUS_WIDTH-1:0]      x3  = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x3 ;
wire [`DATA_BUS_WIDTH-1:0]      x26 = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x26;
wire [`DATA_BUS_WIDTH-1:0]      x27 = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x27;

always begin
    wait (x26 == 32'b1);
    # (100);

    if (x27 == 32'b1) begin
        $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~ #####     ##     ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~ #    #   #  #   #       #      ~~~~~~~~~");
        $display("~~~~~~~~~ #    #  #    #   ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~ #####   ######       #       # ~~~~~~~~~");
        $display("~~~~~~~~~ #       #    #  #    #  #    # ~~~~~~~~~");
        $display("~~~~~~~~~ #       #    #   ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    end
    else begin
        $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~ ######   ##       #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #       #  #      #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #####  #    #     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      ######     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      #    #     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      #    #     #    ###### ~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("fail testnum = %2d", x3);
    end

    $stop();
end

`endif

always #((32'd1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;

endmodule
module core_tb(
    );


`include "pa_chip_param.v"

reg                             sys_clk;
reg                             sys_rst_n;

wire                            TXD;

initial begin
`ifdef DUMP_VCD
    $dumpfile("wave.vcd");
    $dumpvars(0, core_tb);
`endif
end

pa_chip_top u_pa_chip_top (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (),
    .txd                        (TXD)
);

core_uart_monitor_tb u_core_uart_monitor_tb (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (TXD),
    .txd                        ()
);

initial begin
    sys_clk = 1;
    sys_rst_n = 0;

`ifndef ROM_MODE_BRAM
    $readmemh("image.pat", u_pa_chip_top.u_pa_perips_rom._ram);
`endif
end

always begin
    @ (posedge sys_clk) sys_rst_n = 0;
    @ (posedge sys_clk) sys_rst_n = 1;

    while (1) begin
        @ (posedge sys_clk);
    end

    $stop();
end

`ifdef TEST_ISA

wire [`DATA_BUS_WIDTH-1:0]      x3  = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x3 ;
wire [`DATA_BUS_WIDTH-1:0]      x26 = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x26;
wire [`DATA_BUS_WIDTH-1:0]      x27 = u_pa_chip_top.u_pa_core_top.u_pa_core_rtu.u_pa_core_xreg._x27;

always begin
    wait (x26 == 32'b1);
    # (100);

    if (x27 == 32'b1) begin
        $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~ #####     ##     ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~ #    #   #  #   #       #      ~~~~~~~~~");
        $display("~~~~~~~~~ #    #  #    #   ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~ #####   ######       #       # ~~~~~~~~~");
        $display("~~~~~~~~~ #       #    #  #    #  #    # ~~~~~~~~~");
        $display("~~~~~~~~~ #       #    #   ####    ####  ~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
    end
    else begin
        $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("~~~~~~~~~~ ######   ##       #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #       #  #      #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #####  #    #     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      ######     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      #    #     #    #      ~~~~~~~~~");
        $display("~~~~~~~~~~ #      #    #     #    ###### ~~~~~~~~~");
        $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
        $display("fail testnum = %2d", x3);
    end

    $stop();
end

`endif

always #((32'd1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;

endmodule