data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleComplexAdder/reference/SimpleComplexAdder.v
data/verilator_xmls/534200d5-57af-4b87-8be8-729846d8a4c1.xml
module DFF_POSCLK(q, d, clk);
    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule
module DFF_POSCLK(q, d, clk);

    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule