data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:46: Define or directive not defined: \'`REGFILE_TYPE_FF_2D\'\n   parameter regfile_type = `REGFILE_TYPE_FF_2D;\n                            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter regfile_type = `REGFILE_TYPE_FF_2D;\n                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:51: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_fifo.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 6 error(s)\n'
module c_fifo
  (clk, reset, push_active, pop_active, push, pop, push_data, pop_data, 
   almost_empty, empty, full, errors);
   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 4;
   

   parameter width = 8;
   

   parameter regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter enable_bypass = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   

   localparam addr_width = clogb(depth);
   
   input clk;
   input reset;
   input push_active;
   input pop_active;
   

   input push;
   

   input pop;
   

   input [0:width-1] push_data;
   

   output [0:width-1] pop_data;
   wire [0:width-1]   pop_data;
   

   output 	      almost_empty;
   wire 	      almost_empty;
   

   output 	      empty;
   wire 	      empty;
   

   output 	      full;
   wire 	      full;
   

   output [0:1]       errors;
   wire [0:1] 	      errors;
   
   wire 	      error_underflow;
   wire 	      error_overflow;
   
   generate
      
      if(depth == 0)
	begin
	   
	   if(enable_bypass)
	     assign pop_data = push_data;
	   
	   assign almost_empty = 1'b0;
	   assign empty = 1'b1;
	   assign full = 1'b1;
	   
	   assign error_underflow = pop;
	   assign error_overflow = push;
	   
	   assign errors[0] = error_underflow;
	   assign errors[1] = error_overflow;
	   
	end
      else if(depth == 1)
	begin
	   
	   wire [0:width-1] data_s, data_q;
	   assign data_s = push ? push_data : data_q;
	   c_dff
	     #(.width(width),
	       .reset_type(reset_type))
	   dataq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(push_active),
	      .d(data_s),
	      .q(data_q));
	   
	   if(enable_bypass)
	     assign pop_data = empty ? push_data : data_q;
	   else
	     assign pop_data = data_q;
	   
	   wire 	    empty_active;
	   assign empty_active = push_active | pop_active;
	   
	   wire 	    empty_s, empty_q;
	   assign empty_s = (empty_q & ~push) | pop;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(empty_active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign almost_empty = ~empty_q;
	   assign empty = empty_q;
	   assign full = ~empty_q;
	   
	   wire 	    error_underflow;
	   if(enable_bypass)
	     assign error_underflow = empty_q & pop & ~push;
	   else
	     assign error_underflow = empty_q & pop;
	   
	   wire 	    error_overflow;
	   assign error_overflow = ~empty_q & push;
	   
	   assign errors[0] = error_underflow;
	   assign errors[1] = error_overflow;
	   
	end
      else if(depth > 1)
	begin
	   
	   wire [0:addr_width-1] push_addr;
	   wire [0:addr_width-1] pop_addr;
	   c_fifo_ctrl
	     #(.depth(depth),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   ctrl
	     (.clk(clk),
	      .reset(reset),
	      .push_active(push_active),
	      .pop_active(pop_active),
	      .push(push),
	      .pop(pop),
	      .push_addr(push_addr),
	      .pop_addr(pop_addr),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .full(full),
	      .errors(errors));
	   
	   assign error_underflow = errors[0];
	   assign error_overflow = errors[1];
	   
	   wire [0:width-1] 	 rf_data;
	   c_regfile
	     #(.depth(depth),
	       .width(width),
	       .regfile_type(regfile_type))
	   rf
	     (.clk(clk),
	      .write_active(push_active),
	      .write_enable(push),
	      .write_address(push_addr),
	      .write_data(push_data),
	      .read_address(pop_addr),
	      .read_data(rf_data));
	   
	   if(enable_bypass)
	     assign pop_data = empty ? push_data : rf_data;
	   else
	     assign pop_data = rf_data;
	   
	end
      
   endgenerate
   
endmodule
module c_fifo
  (clk, reset, push_active, pop_active, push, pop, push_data, pop_data, 
   almost_empty, empty, full, errors);

   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 4;
   

   parameter width = 8;
   

   parameter regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter enable_bypass = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   

   localparam addr_width = clogb(depth);
   
   input clk;
   input reset;
   input push_active;
   input pop_active;
   

   input push;
   

   input pop;
   

   input [0:width-1] push_data;
   

   output [0:width-1] pop_data;
   wire [0:width-1]   pop_data;
   

   output 	      almost_empty;
   wire 	      almost_empty;
   

   output 	      empty;
   wire 	      empty;
   

   output 	      full;
   wire 	      full;
   

   output [0:1]       errors;
   wire [0:1] 	      errors;
   
   wire 	      error_underflow;
   wire 	      error_overflow;
   
   generate
      
      if(depth == 0)
	begin
	   
	   if(enable_bypass)
	     assign pop_data = push_data;
	   
	   assign almost_empty = 1'b0;
	   assign empty = 1'b1;
	   assign full = 1'b1;
	   
	   assign error_underflow = pop;
	   assign error_overflow = push;
	   
	   assign errors[0] = error_underflow;
	   assign errors[1] = error_overflow;
	   
	end
      else if(depth == 1)
	begin
	   
	   wire [0:width-1] data_s, data_q;
	   assign data_s = push ? push_data : data_q;
	   c_dff
	     #(.width(width),
	       .reset_type(reset_type))
	   dataq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(push_active),
	      .d(data_s),
	      .q(data_q));
	   
	   if(enable_bypass)
	     assign pop_data = empty ? push_data : data_q;
	   else
	     assign pop_data = data_q;
	   
	   wire 	    empty_active;
	   assign empty_active = push_active | pop_active;
	   
	   wire 	    empty_s, empty_q;
	   assign empty_s = (empty_q & ~push) | pop;
	   c_dff
	     #(.width(1),
	       .reset_value(1'b1),
	       .reset_type(reset_type))
	   emptyq
	     (.clk(clk),
	      .reset(reset),
	      .active(empty_active),
	      .d(empty_s),
	      .q(empty_q));
	   
	   assign almost_empty = ~empty_q;
	   assign empty = empty_q;
	   assign full = ~empty_q;
	   
	   wire 	    error_underflow;
	   if(enable_bypass)
	     assign error_underflow = empty_q & pop & ~push;
	   else
	     assign error_underflow = empty_q & pop;
	   
	   wire 	    error_overflow;
	   assign error_overflow = ~empty_q & push;
	   
	   assign errors[0] = error_underflow;
	   assign errors[1] = error_overflow;
	   
	end
      else if(depth > 1)
	begin
	   
	   wire [0:addr_width-1] push_addr;
	   wire [0:addr_width-1] pop_addr;
	   c_fifo_ctrl
	     #(.depth(depth),
	       .enable_bypass(enable_bypass),
	       .reset_type(reset_type))
	   ctrl
	     (.clk(clk),
	      .reset(reset),
	      .push_active(push_active),
	      .pop_active(pop_active),
	      .push(push),
	      .pop(pop),
	      .push_addr(push_addr),
	      .pop_addr(pop_addr),
	      .almost_empty(almost_empty),
	      .empty(empty),
	      .full(full),
	      .errors(errors));
	   
	   assign error_underflow = errors[0];
	   assign error_overflow = errors[1];
	   
	   wire [0:width-1] 	 rf_data;
	   c_regfile
	     #(.depth(depth),
	       .width(width),
	       .regfile_type(regfile_type))
	   rf
	     (.clk(clk),
	      .write_active(push_active),
	      .write_enable(push),
	      .write_address(push_addr),
	      .write_data(push_data),
	      .read_address(pop_addr),
	      .read_data(rf_data));
	   
	   if(enable_bypass)
	     assign pop_data = empty ? push_data : rf_data;
	   else
	     assign pop_data = rf_data;
	   
	end
      
   endgenerate
   
endmodule