data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:12: Signal definition not found, creating implicitly: \'clk_idx\'\nfreq_div#(22) M1 (clk,reset,clk_idx);\n                            ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:13: Signal definition not found, creating implicitly: \'clk_row\'\nfreq_div#(12) M2 (clk,reset,clk_row);\n                            ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:163: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                             : ... In instance lab4_2.M4\n  idx_cnt =idx+cnt;    \n              ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:14: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nidx_gen M3 (clk_idx,reset,idx); \n                          ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                                     ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:16: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrom_char M5 (idx_cnt, column_out);\n             ^~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module lab4_2(clk, reset, row, sel, column_green, column_red);
input clk, reset;
input[1:0] sel;
output[7:0] row, column_green, column_red;
wire clk_shift, clk_scan;
wire[7:0] idx, idx_cnt;
wire[7:0] column_out;

assign column_green= (sel== 2'b01 || sel== 2'b11)? column_out: 8'b0;
assign column_red= (sel== 2'b10 || sel== 2'b11)? column_out: 8'b0;

freq_div#(22) M1 (clk,reset,clk_idx);
freq_div#(12) M2 (clk,reset,clk_row);
idx_gen M3 (clk_idx,reset,idx); 
row_gen M4 (clk_row,reset, idx, row, idx_cnt);
rom_char M5 (idx_cnt, column_out);
endmodule
module lab4_2(clk, reset, row, sel, column_green, column_red);

input clk, reset;
input[1:0] sel;
output[7:0] row, column_green, column_red;
wire clk_shift, clk_scan;
wire[7:0] idx, idx_cnt;
wire[7:0] column_out;

assign column_green= (sel== 2'b01 || sel== 2'b11)? column_out: 8'b0;
assign column_red= (sel== 2'b10 || sel== 2'b11)? column_out: 8'b0;

freq_div#(22) M1 (clk,reset,clk_idx);
freq_div#(12) M2 (clk,reset,clk_row);
idx_gen M3 (clk_idx,reset,idx); 
row_gen M4 (clk_row,reset, idx, row, idx_cnt);
rom_char M5 (idx_cnt, column_out);
endmodule