data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v
1: b"%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:10: Define or directive not defined: '`ADDRSIZE'\n   input [`ADDRSIZE-1:0] trig_x,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:11: Define or directive not defined: '`ADDRSIZE'\n   input [`ADDRSIZE-1:0] trig_y,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:12: Define or directive not defined: '`IOPAIRS'\n   input [`IOPAIRS-1:0] in_pins,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:13: Define or directive not defined: '`IOPAIRS'\n   output [`IOPAIRS-1:0] out_pins\n           ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:16: Define or directive not defined: '`HEIGHT'\nwire ic_u[`HEIGHT-1:0][`WIDTH-1:0];    \n          ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:16: Define or directive not defined: '`WIDTH'\nwire ic_u[`HEIGHT-1:0][`WIDTH-1:0];    \n                       ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:17: Define or directive not defined: '`HEIGHT'\nwire ic_d[`HEIGHT-1:0][`WIDTH-1:0];    \n          ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:17: Define or directive not defined: '`WIDTH'\nwire ic_d[`HEIGHT-1:0][`WIDTH-1:0];    \n                       ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:18: Define or directive not defined: '`HEIGHT'\nwire ic_r[`HEIGHT-1:0][`WIDTH-1:0];    \n          ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:18: Define or directive not defined: '`WIDTH'\nwire ic_r[`HEIGHT-1:0][`WIDTH-1:0];    \n                       ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:19: Define or directive not defined: '`HEIGHT'\nwire ic_l[`HEIGHT-1:0][`WIDTH-1:0];    \n          ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:19: Define or directive not defined: '`WIDTH'\nwire ic_l[`HEIGHT-1:0][`WIDTH-1:0];    \n                       ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:20: Define or directive not defined: '`HEIGHT'\nwire trig_h[`HEIGHT-1:0];             \n            ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:21: Define or directive not defined: '`WIDTH'\nwire trig_v[`WIDTH-1:0];              \n            ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:24: Define or directive not defined: '`HEIGHT'\nfor (y=0; y<`HEIGHT; y=y+1) begin:g_y\n            ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:24: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nfor (y=0; y<`HEIGHT; y=y+1) begin:g_y\n                   ^\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:25: Define or directive not defined: '`WIDTH'\n   for (x=0; x<`WIDTH; x=x+1) begin:g_x\n               ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`Y_FIRST'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n               ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                        ^~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`Y_FIRST'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`Y_STEP'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`IOPAIRS'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`Y_FIRST'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:31: Define or directive not defined: '`Y_STEP'\n      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin\n                                                                              ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:32: Define or directive not defined: '`X_IN'\n         if (x == `X_IN) begin\n                  ^~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:34: Define or directive not defined: '`Y_FIRST'\n            assign in_i = in_pins[(y-`Y_FIRST)/`Y_STEP];\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:34: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n            assign in_i = in_pins[(y-`Y_FIRST)/`Y_STEP];\n                                             ^\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:34: Define or directive not defined: '`Y_STEP'\n            assign in_i = in_pins[(y-`Y_FIRST)/`Y_STEP];\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:38: syntax error, unexpected end\n         end\n         ^~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:39: Define or directive not defined: '`X_OUT'\n         if (x == `X_OUT) begin\n                  ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:40: Define or directive not defined: '`Y_FIRST'\n            assign out_pins[(y-`Y_FIRST)/`Y_STEP] = out_o;\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:40: Define or directive not defined: '`Y_STEP'\n            assign out_pins[(y-`Y_FIRST)/`Y_STEP] = out_o;\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:45: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:52: Define or directive not defined: '`WIDTH'\n         .in_r(ic_l[y][(x+1)%`WIDTH]),\n                             ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:53: Define or directive not defined: '`HEIGHT'\n         .in_b(ic_u[(y+1)%`HEIGHT][x]),\n                          ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:58: Define or directive not defined: '`WIDTH'\n         .out_r(ic_r[y][(x+1)%`WIDTH]),\n                              ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:59: Define or directive not defined: '`HEIGHT'\n         .out_b(ic_d[(y+1)%`HEIGHT][x]),\n                           ^~~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:66: Define or directive not defined: '`WIDTH'\nfor (x=0; x<`WIDTH; x=x+1) begin:g_vt\n            ^~~~~~\n%Error: data/full_repos/permissive/428225746/verilog/rtl/logic_grid.v:70: Define or directive not defined: '`HEIGHT'\nfor (y=0; y<`HEIGHT; y=y+1) begin:g_ht\n            ^~~~~~~\n%Error: Cannot continue\n"
module logic_grid (
   input clk,
   input rst_n,
   input trig_en,
   input [`ADDRSIZE-1:0] trig_x,
   input [`ADDRSIZE-1:0] trig_y,
   input [`IOPAIRS-1:0] in_pins,
   output [`IOPAIRS-1:0] out_pins
);

wire ic_u[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_d[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_r[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_l[`HEIGHT-1:0][`WIDTH-1:0];
wire trig_h[`HEIGHT-1:0];
wire trig_v[`WIDTH-1:0];

generate genvar x, y;
for (y=0; y<`HEIGHT; y=y+1) begin:g_y
   for (x=0; x<`WIDTH; x=x+1) begin:g_x
      wire trig = trig_h[y] & trig_v[x];
      wire in_i;
      wire en_i;
      wire out_o;
      
      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin
         if (x == `X_IN) begin
            assign en_i = 1;
            assign in_i = in_pins[(y-`Y_FIRST)/`Y_STEP];
         end else begin
            assign en_i = 0;
            assign in_i = 0;
         end
         if (x == `X_OUT) begin
            assign out_pins[(y-`Y_FIRST)/`Y_STEP] = out_o;
         end
      end else begin
         assign en_i = 0;
         assign in_i = 0;
      end

      logic_cell lc (
         .clk(clk),
         .rst_n(rst_n),
         .trig(trig),
         .in_t(ic_d[y][x]),
         .in_r(ic_l[y][(x+1)%`WIDTH]),
         .in_b(ic_u[(y+1)%`HEIGHT][x]),
         .in_l(ic_r[y][x]),
         .in_i(in_i),
         .en_i(en_i),
         .out_t(ic_u[y][x]),
         .out_r(ic_r[y][(x+1)%`WIDTH]),
         .out_b(ic_d[(y+1)%`HEIGHT][x]),
         .out_l(ic_l[y][x]),
         .out_o(out_o)     
      );
   end
end

for (x=0; x<`WIDTH; x=x+1) begin:g_vt
   assign trig_v[x] = trig_en & (trig_x == x);
end

for (y=0; y<`HEIGHT; y=y+1) begin:g_ht
   assign trig_h[y] = trig_en & (trig_y == y);
end
endgenerate

endmodule
module logic_grid (
   input clk,
   input rst_n,
   input trig_en,
   input [`ADDRSIZE-1:0] trig_x,
   input [`ADDRSIZE-1:0] trig_y,
   input [`IOPAIRS-1:0] in_pins,
   output [`IOPAIRS-1:0] out_pins
);


wire ic_u[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_d[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_r[`HEIGHT-1:0][`WIDTH-1:0];
wire ic_l[`HEIGHT-1:0][`WIDTH-1:0];
wire trig_h[`HEIGHT-1:0];
wire trig_v[`WIDTH-1:0];

generate genvar x, y;
for (y=0; y<`HEIGHT; y=y+1) begin:g_y
   for (x=0; x<`WIDTH; x=x+1) begin:g_x
      wire trig = trig_h[y] & trig_v[x];
      wire in_i;
      wire en_i;
      wire out_o;
      
      if (y >= `Y_FIRST && y <= `Y_FIRST+`Y_STEP*(`IOPAIRS-1) && (y-`Y_FIRST)%`Y_STEP == 0) begin
         if (x == `X_IN) begin
            assign en_i = 1;
            assign in_i = in_pins[(y-`Y_FIRST)/`Y_STEP];
         end else begin
            assign en_i = 0;
            assign in_i = 0;
         end
         if (x == `X_OUT) begin
            assign out_pins[(y-`Y_FIRST)/`Y_STEP] = out_o;
         end
      end else begin
         assign en_i = 0;
         assign in_i = 0;
      end

      logic_cell lc (
         .clk(clk),
         .rst_n(rst_n),
         .trig(trig),
         .in_t(ic_d[y][x]),
         .in_r(ic_l[y][(x+1)%`WIDTH]),
         .in_b(ic_u[(y+1)%`HEIGHT][x]),
         .in_l(ic_r[y][x]),
         .in_i(in_i),
         .en_i(en_i),
         .out_t(ic_u[y][x]),
         .out_r(ic_r[y][(x+1)%`WIDTH]),
         .out_b(ic_d[(y+1)%`HEIGHT][x]),
         .out_l(ic_l[y][x]),
         .out_o(out_o)     
      );
   end
end

for (x=0; x<`WIDTH; x=x+1) begin:g_vt
   assign trig_v[x] = trig_en & (trig_x == x);
end

for (y=0; y<`HEIGHT; y=y+1) begin:g_ht
   assign trig_h[y] = trig_en & (trig_y == y);
end
endgenerate

endmodule