data/full_repos/permissive/506186384/project-files/lab5/Ctr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/506186384/project-files/lab5/Ctr.v:117: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                 : ... In instance Ctr\n                aluOp = 2\'b000;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Ctr(
    input [5:0] OpCode,
    output [1:0] RegDst,
    output [1:0] ALUSrc1,
    output [1:0] ALUSrc2,
    output MemToReg, 
    output RegWrite,
    output MemRead,
    output MemWrite,
    output Branch,
    output [2:0] ALUOp,
    output Jump
    );
    
    reg [1:0] regDst;
    reg [1:0] aluSrc1;
    reg [1:0] aluSrc2;
    reg memtoReg;
    reg regWrite;
    reg memRead;
    reg memWrite;
    reg branch;
    reg [2:0] aluOp;
    reg jump;
    
    always @ (OpCode)
    begin
        case(OpCode)
            6'b000000:
            begin
                regDst = 2'b01;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b010;
                jump = 0;
            end
            
            6'b100011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b101011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b000100:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 1;
                aluOp = 3'b001;
                jump = 0;
            end
            
            6'b000010:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 2'b000;
                jump = 1;
            end
            
            6'b001000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b001100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b011;
                jump = 0;
            end
            
            6'b001101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b100;
                jump = 0;
            end
            
            6'b000011:
            begin
                regDst = 2'b10;
                aluSrc1 = 2'b10;
                aluSrc2 = 2'b11;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 1;
            end
            
            default:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                jump = 0;
            end
        endcase
    end
   
   assign RegDst = regDst;
   assign ALUSrc1 = aluSrc1;
   assign ALUSrc2 = aluSrc2;
   assign MemToReg = memtoReg;
   assign RegWrite = regWrite;
   assign MemRead = memRead;
   assign MemWrite = memWrite;
   assign Branch = branch;
   assign ALUOp = aluOp;
   assign Jump = jump;
   
endmodule
module Ctr(
    input [5:0] OpCode,
    output [1:0] RegDst,
    output [1:0] ALUSrc1,
    output [1:0] ALUSrc2,
    output MemToReg, 
    output RegWrite,
    output MemRead,
    output MemWrite,
    output Branch,
    output [2:0] ALUOp,
    output Jump
    );

    
    reg [1:0] regDst;
    reg [1:0] aluSrc1;
    reg [1:0] aluSrc2;
    reg memtoReg;
    reg regWrite;
    reg memRead;
    reg memWrite;
    reg branch;
    reg [2:0] aluOp;
    reg jump;
    
    always @ (OpCode)
    begin
        case(OpCode)
            6'b000000:
            begin
                regDst = 2'b01;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b010;
                jump = 0;
            end
            
            6'b100011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b101011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b000100:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 1;
                aluOp = 3'b001;
                jump = 0;
            end
            
            6'b000010:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 2'b000;
                jump = 1;
            end
            
            6'b001000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 0;
            end
            
            6'b001100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b011;
                jump = 0;
            end
            
            6'b001101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b100;
                jump = 0;
            end
            
            6'b000011:
            begin
                regDst = 2'b10;
                aluSrc1 = 2'b10;
                aluSrc2 = 2'b11;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 3'b000;
                jump = 1;
            end
            
            default:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                jump = 0;
            end
        endcase
    end
   
   assign RegDst = regDst;
   assign ALUSrc1 = aluSrc1;
   assign ALUSrc2 = aluSrc2;
   assign MemToReg = memtoReg;
   assign RegWrite = regWrite;
   assign MemRead = memRead;
   assign MemWrite = memWrite;
   assign Branch = branch;
   assign ALUOp = aluOp;
   assign Jump = jump;
   
endmodule