data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:43: Cannot find file containing module: 'i33mult'\ni33mult i33mult1i\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i33mult\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i33mult.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i33mult.sv\n             i33mult\n             i33mult.v\n             i33mult.sv\n             obj_dir/i33mult\n             obj_dir/i33mult.v\n             obj_dir/i33mult.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:52: Cannot find file containing module: 'i33mult'\ni33mult i33mult2i\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:61: Cannot find file containing module: 'i33mult'\ni33mult i33mult3i\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:70: Cannot find file containing module: 'i33mult'\ni33mult i33mult4i\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:80: Cannot find file containing module: 'cla'\ncla #(6) i66cla1i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:91: Cannot find file containing module: 'cla'\ncla #(6) i66cla2i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i66vedic.v:105: Cannot find file containing module: 'cla'\ncla #(6) i66cla3i\n^~~\n%Error: Exiting due to 7 error(s)\n"
module i66vedic
    (
     a,
     b,
     rslt
     );




parameter WIDTH = 6;
parameter RSWID = 12;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w33rslt1;

i33mult i33mult1i
    (
     .a(a[2:0]),
     .b(b[2:0]),
     .prd(w33rslt1)
     );

wire [WIDTH-1:0]   w33rslt2;

i33mult i33mult2i
    (
     .a(a[2:0]),
     .b(b[5:3]),
     .prd(w33rslt2)
     );

wire [WIDTH-1:0]   w33rslt3;

i33mult i33mult3i
    (
     .a(a[5:3]),
     .b(b[2:0]),
     .prd(w33rslt3)
     );

wire [WIDTH-1:0]   w33rslt4;

i33mult i33mult4i
    (
     .a(a[5:3]),
     .b(b[5:3]),
     .prd(w33rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(6) i66cla1i
    (
     .a(w33rslt2),
     .b(w33rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(6) i66cla2i
    (
     .a({3'b000,w33rslt1[5:3]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(6) i66cla3i
    (
     .a(w33rslt4),
     .b({2'b00,cla3cin,cla2rslt[5:3]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[2:0],w33rslt1[2:0]};

endmodule
module i66vedic
    (
     a,
     b,
     rslt
     );





parameter WIDTH = 6;
parameter RSWID = 12;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w33rslt1;

i33mult i33mult1i
    (
     .a(a[2:0]),
     .b(b[2:0]),
     .prd(w33rslt1)
     );

wire [WIDTH-1:0]   w33rslt2;

i33mult i33mult2i
    (
     .a(a[2:0]),
     .b(b[5:3]),
     .prd(w33rslt2)
     );

wire [WIDTH-1:0]   w33rslt3;

i33mult i33mult3i
    (
     .a(a[5:3]),
     .b(b[2:0]),
     .prd(w33rslt3)
     );

wire [WIDTH-1:0]   w33rslt4;

i33mult i33mult4i
    (
     .a(a[5:3]),
     .b(b[5:3]),
     .prd(w33rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(6) i66cla1i
    (
     .a(w33rslt2),
     .b(w33rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(6) i66cla2i
    (
     .a({3'b000,w33rslt1[5:3]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(6) i66cla3i
    (
     .a(w33rslt4),
     .b({2'b00,cla3cin,cla2rslt[5:3]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[2:0],w33rslt1[2:0]};

endmodule