data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_decoder.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_decoder.v:19: Multiple top level modules\n                                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                         : ... Top module \'f1_test\'\nmodule f1_test (input [1:0] in, input enable, output reg  out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f2_test\'\nmodule f2_test (input [1:0] in, input enable, output reg [2:0] out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f3_test\'\nmodule f3_test (input [2:0] in, output reg [7:0] out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f4_test\'\nmodule f4_test (input [2:0] in, input enable, output reg [7:0] out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f5_test\'\nmodule f5_test (input [3:0] in, input enable, output reg [15:0] out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f6_test\'\nmodule f6_test (input [4:0] in, input enable, output reg [31:0] out);\n       ^~~~~~~\n                                                                                                         : ... Top module \'f7_test\'\nmodule f7_test (input [5:0] in, input enable, output reg [63:0] out);\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_decoder.v:7: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                     : ... In instance f1_test\n     out = 4\'b0000;\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module f2_test (input [1:0] in, input enable, output reg [2:0] out);

always @(in or enable)
    if(!enable)
	    out = 3'b000;
	else begin
	   case (in)
	       2'b00 : out = 3'b001 ;
	       2'b01 : out = 3'b010;
	       2'b10 : out = 3'b010;
	       2'b11 : out = 3'b100;
	    endcase
	end
endmodule
module f2_test (input [1:0] in, input enable, output reg [2:0] out);


always @(in or enable)
    if(!enable)
	    out = 3'b000;
	else begin
	   case (in)
	       2'b00 : out = 3'b001 ;
	       2'b01 : out = 3'b010;
	       2'b10 : out = 3'b010;
	       2'b11 : out = 3'b100;
	    endcase
	end
endmodule