data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldumpdbdat.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldumpdbdat.v:163: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do            (dbdat_do),\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldumpdbdat.v:163: syntax error, unexpected '(', expecting ')'\n     .do            (dbdat_do),\n                     ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module rtldumpdbdat
    (
     clk,
     rst,

     dbenb,
     vld,
     dat,

     wrpage,
     
     upact,
     upen,
     upa,
     upws,
     uprs,
     updi,
     updo,
     uprdy
     );



parameter           DBADD   = 11;
parameter           DBDAT   = 32;
parameter           DBLEN   = {1'b1,{DBADD{1'b0}}};



input               clk,
                    rst;

input               dbenb;
input               vld;
input [DBDAT-1:0]   dat;

output              wrpage;

input               upact;
input               upen;
input [DBADD-1:0]   upa;
input               upws;
input               uprs;
input [DBDAT-1:0]   updi;
output [DBDAT-1:0]  updo;
output              uprdy;








wire                dumpfull;
wire                dumpstr;
assign              dumpstr = dbenb;

reg                 dumpen;
always @ (posedge clk)
    begin
    if(rst) dumpen <= 1'b0;
    else if(dumpstr) dumpen <= 1'b1;
    else if(dumpfull) dumpen <= 1'b0;
    end


wire                rden;
wire [DBADD-1:0]    rdid;
assign              rden = 1'b0;
assign              rdid = {DBADD{1'b0}};
wire [DBDAT-1:0]    rddat;

wire                wren;
assign              wren = dumpen & vld;

reg [DBADD-1:0]     wrid;

always @ (posedge clk)
    begin
    if(rst)           wrid <= {DBADD{1'b0}};
    else if(dumpfull)   wrid <= {DBADD{1'b0}};
    else if(wren)       wrid <= wrid + 1;
    end

assign  wrpage  = wrid[DBADD-1];

assign              dumpfull = wren & (wrid == {DBADD{1'b1}});

wire [DBDAT-1:0]    wrdat;
assign              wrdat = dat;



wire                dbdat_pen;
wire [DBDAT-1:0]    dbdat_pdo;
wire                dbdat_prdy;
wire                dbdat_we;
wire [DBADD-1:0]    dbdat_wa;
wire [DBDAT-1:0]    dbdat_di;
wire                dbdat_re;
wire [DBADD-1:0]    dbdat_ra;
wire [DBDAT-1:0]    dbdat_do;

rtlrambuf112x #(DBADD,DBDAT) dbdatarb
    (

     .clk       (clk),
     .rst       (rst),     


     .eng_re    (rden),
     .eng_ra    (rdid),
     .eng_rdd   (rddat),
     .eng_we    (wren),
     .eng_wa    (wrid),
     .eng_wrd   (wrdat),
     

     .upen      (dbdat_pen),
     .upws      (upws),
     .uprs      (uprs),
     .upa       (upa[DBADD-1:0]),
     .updi      (updi[DBDAT-1:0]),
     .updo      (dbdat_pdo),
     .uprdy     (dbdat_prdy),
     .active    (upact),
     

     .memwe     (dbdat_we),
     .memwa     (dbdat_wa),
     .memwrd    (dbdat_di),
     .memre     (dbdat_re),
     .memra     (dbdat_ra),
     .memrdd    (dbdat_do)
     );

iarray112x #(DBADD,DBLEN,DBDAT) dbdat          
    (
     .wrst          (rst),
     .wclk          (clk),
     .wa            (dbdat_wa),
     .we            (dbdat_we),
     .di            (dbdat_di),

     .rrst          (rst),
     .rclk          (clk),
     .ra            (dbdat_ra),
     .re            (dbdat_re),
     .do            (dbdat_do),

     .test          (1'b0),
     .mask          (1'b0)
     );


assign              dbdat_pen = upen;

wire [DBDAT-1:0]    updo;
assign              updo =  dbdat_pdo;

wire                uprdy;
assign              uprdy = dbdat_prdy;

endmodule
module rtldumpdbdat
    (
     clk,
     rst,

     dbenb,
     vld,
     dat,

     wrpage,
     
     upact,
     upen,
     upa,
     upws,
     uprs,
     updi,
     updo,
     uprdy
     );




parameter           DBADD   = 11;
parameter           DBDAT   = 32;
parameter           DBLEN   = {1'b1,{DBADD{1'b0}}};



input               clk,
                    rst;

input               dbenb;
input               vld;
input [DBDAT-1:0]   dat;

output              wrpage;

input               upact;
input               upen;
input [DBADD-1:0]   upa;
input               upws;
input               uprs;
input [DBDAT-1:0]   updi;
output [DBDAT-1:0]  updo;
output              uprdy;








wire                dumpfull;
wire                dumpstr;
assign              dumpstr = dbenb;

reg                 dumpen;
always @ (posedge clk)
    begin
    if(rst) dumpen <= 1'b0;
    else if(dumpstr) dumpen <= 1'b1;
    else if(dumpfull) dumpen <= 1'b0;
    end


wire                rden;
wire [DBADD-1:0]    rdid;
assign              rden = 1'b0;
assign              rdid = {DBADD{1'b0}};
wire [DBDAT-1:0]    rddat;

wire                wren;
assign              wren = dumpen & vld;

reg [DBADD-1:0]     wrid;

always @ (posedge clk)
    begin
    if(rst)           wrid <= {DBADD{1'b0}};
    else if(dumpfull)   wrid <= {DBADD{1'b0}};
    else if(wren)       wrid <= wrid + 1;
    end

assign  wrpage  = wrid[DBADD-1];

assign              dumpfull = wren & (wrid == {DBADD{1'b1}});

wire [DBDAT-1:0]    wrdat;
assign              wrdat = dat;



wire                dbdat_pen;
wire [DBDAT-1:0]    dbdat_pdo;
wire                dbdat_prdy;
wire                dbdat_we;
wire [DBADD-1:0]    dbdat_wa;
wire [DBDAT-1:0]    dbdat_di;
wire                dbdat_re;
wire [DBADD-1:0]    dbdat_ra;
wire [DBDAT-1:0]    dbdat_do;

rtlrambuf112x #(DBADD,DBDAT) dbdatarb
    (

     .clk       (clk),
     .rst       (rst),     


     .eng_re    (rden),
     .eng_ra    (rdid),
     .eng_rdd   (rddat),
     .eng_we    (wren),
     .eng_wa    (wrid),
     .eng_wrd   (wrdat),
     

     .upen      (dbdat_pen),
     .upws      (upws),
     .uprs      (uprs),
     .upa       (upa[DBADD-1:0]),
     .updi      (updi[DBDAT-1:0]),
     .updo      (dbdat_pdo),
     .uprdy     (dbdat_prdy),
     .active    (upact),
     

     .memwe     (dbdat_we),
     .memwa     (dbdat_wa),
     .memwrd    (dbdat_di),
     .memre     (dbdat_re),
     .memra     (dbdat_ra),
     .memrdd    (dbdat_do)
     );

iarray112x #(DBADD,DBLEN,DBDAT) dbdat          
    (
     .wrst          (rst),
     .wclk          (clk),
     .wa            (dbdat_wa),
     .we            (dbdat_we),
     .di            (dbdat_di),

     .rrst          (rst),
     .rclk          (clk),
     .ra            (dbdat_ra),
     .re            (dbdat_re),
     .do            (dbdat_do),

     .test          (1'b0),
     .mask          (1'b0)
     );


assign              dbdat_pen = upen;

wire [DBDAT-1:0]    updo;
assign              updo =  dbdat_pdo;

wire                uprdy;
assign              uprdy = dbdat_prdy;

endmodule