data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom/inst_rom_display.v
1: b"%Error: data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom/inst_rom_display.v:31: Cannot find file containing module: 'inst_rom'\n    inst_rom inst_rom_module(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom,data/full_repos/permissive/482470328/inst_rom\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom,data/full_repos/permissive/482470328/inst_rom.v\n             data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom,data/full_repos/permissive/482470328/inst_rom.sv\n             inst_rom\n             inst_rom.v\n             inst_rom.sv\n             obj_dir/inst_rom\n             obj_dir/inst_rom.v\n             obj_dir/inst_rom.sv\n%Error: data/full_repos/permissive/482470328/lab5/labFiles/memory_sync/inst_rom/inst_rom_display.v:48: Cannot find file containing module: 'lcd_module'\n    lcd_module lcd_module(\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module inst_rom_display(

    input clk,
    input resetn,


    output lcd_rst,
    output lcd_cs,
    output lcd_rs,
    output lcd_wr,
    output lcd_rd,
    inout[15:0] lcd_data_io,
    output lcd_bl_ctr,
    inout ct_int,
    inout ct_sda,
    output ct_scl,
    output ct_rstn
    );


    reg  [31:0] addr;
    wire [31:0] inst;

    inst_rom inst_rom_module(
        .clka   (clk       ),
        .addra  (addr[9:2] ),
        .douta  (inst      )
    );





    reg         display_valid;
    reg  [39:0] display_name;
    reg  [31:0] display_value;
    wire [5 :0] display_number;
    wire        input_valid;
    wire [31:0] input_value;

    lcd_module lcd_module(
        .clk            (clk           ),
        .resetn         (resetn        ),


        .display_valid  (display_valid ),
        .display_name   (display_name  ),
        .display_value  (display_value ),
        .display_number (display_number),
        .input_valid    (input_valid   ),
        .input_value    (input_value   ),


        .lcd_rst        (lcd_rst       ),
        .lcd_cs         (lcd_cs        ),
        .lcd_rs         (lcd_rs        ),
        .lcd_wr         (lcd_wr        ),
        .lcd_rd         (lcd_rd        ),
        .lcd_data_io    (lcd_data_io   ),
        .lcd_bl_ctr     (lcd_bl_ctr    ),
        .ct_int         (ct_int        ),
        .ct_sda         (ct_sda        ),
        .ct_scl         (ct_scl        ),
        .ct_rstn        (ct_rstn       )
    ); 





    always @(posedge clk)
    begin
        if (!resetn)
        begin
            addr <= 32'd0;
        end
        else if (input_valid)
        begin
            addr[31:2] <= input_value[31:2];
        end
    end






    always @(posedge clk)
    begin
       case(display_number)
           6'd1:
           begin
               display_valid <= 1'b1;
               display_name  <= "ADDR ";
               display_value <= addr;
           end
           6'd2: 
           begin
               display_valid <= 1'b1;
               display_name  <= "INST ";
               display_value <= inst;
           end
           default :
           begin
               display_valid <= 1'b0;
               display_name  <= 40'd0;
               display_value <= 32'd0;
           end
       endcase
    end


endmodule
module inst_rom_display(

    input clk,
    input resetn,


    output lcd_rst,
    output lcd_cs,
    output lcd_rs,
    output lcd_wr,
    output lcd_rd,
    inout[15:0] lcd_data_io,
    output lcd_bl_ctr,
    inout ct_int,
    inout ct_sda,
    output ct_scl,
    output ct_rstn
    );



    reg  [31:0] addr;
    wire [31:0] inst;

    inst_rom inst_rom_module(
        .clka   (clk       ),
        .addra  (addr[9:2] ),
        .douta  (inst      )
    );





    reg         display_valid;
    reg  [39:0] display_name;
    reg  [31:0] display_value;
    wire [5 :0] display_number;
    wire        input_valid;
    wire [31:0] input_value;

    lcd_module lcd_module(
        .clk            (clk           ),
        .resetn         (resetn        ),


        .display_valid  (display_valid ),
        .display_name   (display_name  ),
        .display_value  (display_value ),
        .display_number (display_number),
        .input_valid    (input_valid   ),
        .input_value    (input_value   ),


        .lcd_rst        (lcd_rst       ),
        .lcd_cs         (lcd_cs        ),
        .lcd_rs         (lcd_rs        ),
        .lcd_wr         (lcd_wr        ),
        .lcd_rd         (lcd_rd        ),
        .lcd_data_io    (lcd_data_io   ),
        .lcd_bl_ctr     (lcd_bl_ctr    ),
        .ct_int         (ct_int        ),
        .ct_sda         (ct_sda        ),
        .ct_scl         (ct_scl        ),
        .ct_rstn        (ct_rstn       )
    ); 





    always @(posedge clk)
    begin
        if (!resetn)
        begin
            addr <= 32'd0;
        end
        else if (input_valid)
        begin
            addr[31:2] <= input_value[31:2];
        end
    end






    always @(posedge clk)
    begin
       case(display_number)
           6'd1:
           begin
               display_valid <= 1'b1;
               display_name  <= "ADDR ";
               display_value <= addr;
           end
           6'd2: 
           begin
               display_valid <= 1'b1;
               display_name  <= "INST ";
               display_value <= inst;
           end
           default :
           begin
               display_valid <= 1'b0;
               display_name  <= 40'd0;
               display_value <= 32'd0;
           end
       endcase
    end


endmodule