data/full_repos/permissive/418749135/d_ff_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/d_ff_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/d_ff_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n     #15 d <= 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/d_ff_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n     #10 rstn <= 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/d_ff_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #(delay) d <= i;\n      ^\n%Error: data/full_repos/permissive/418749135/d_ff_tb.v:30: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("dump.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/d_ff_tb.v:31: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars;\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dff;
	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;
    integer i;

    dff  dff0 ( .d(d),
                .rstn (rstn),
                .clk (clk),
                .q (q));


    always #10 clk = ~clk;


    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;

    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
initial begin
   $dumpfile("dump.vcd");
   $dumpvars;
   end
endmodule
module tb_dff;

	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;
    integer i;

    dff  dff0 ( .d(d),
                .rstn (rstn),
                .clk (clk),
                .q (q));


    always #10 clk = ~clk;


    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;

    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
initial begin
   $dumpfile("dump.vcd");
   $dumpvars;
   end
endmodule