data/full_repos/permissive/52633518/register.v
data/verilator_xmls/c8487189-304d-4478-a9e4-eb911db99936.xml
module register(

  input clk, rst, w_en,
  input [15:0] data_in,

  output reg [15:0] data_out
);

  always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
      data_out <= 16'd0;
    end else begin
      if(w_en == 1'b1) begin
        data_out <= data_in;
      end else begin
		  data_out <= data_out;
		end
    end
  end
 
endmodule
module register(

  input clk, rst, w_en,
  input [15:0] data_in,

  output reg [15:0] data_out
);


  always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
      data_out <= 16'd0;
    end else begin
      if(w_en == 1'b1) begin
        data_out <= data_in;
      end else begin
		  data_out <= data_out;
		end
    end
  end
 
endmodule