data/full_repos/permissive/458737381/src/verilog-parser/tests/dram.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram.v:22: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module dram (

   dram_io_addr0, dram_io_addr1, dram_io_bank0, dram_io_bank1, 
   dram_io_cas0_l, dram_io_cas1_l, dram_io_channel_disabled0, 
   dram_io_channel_disabled1, dram_io_cke0, dram_io_cke1, 
   dram_io_clk_enable0, dram_io_clk_enable1, dram_io_cs0_l, 
   dram_io_cs1_l, dram_io_data0_out, dram_io_data1_out, 
   dram_io_drive_data0, dram_io_drive_data1, dram_io_drive_enable0, 
   dram_io_drive_enable1, dram_io_pad_clk_inv0, dram_io_pad_clk_inv1, 
   dram_io_pad_enable0, dram_io_pad_enable1, dram_io_ptr_clk_inv0, 
   dram_io_ptr_clk_inv1, dram_io_ras0_l, dram_io_ras1_l, 
   dram_io_write_en0_l, dram_io_write_en1_l, dram_sctag0_data_vld_r0, 
   dram_sctag0_rd_ack, dram_sctag0_scb_mecc_err, 
   dram_sctag0_scb_secc_err, dram_sctag0_wr_ack, 
   dram_sctag1_data_vld_r0, dram_sctag1_rd_ack, 
   dram_sctag1_scb_mecc_err, dram_sctag1_scb_secc_err, 
   dram_sctag1_wr_ack, ucb_iob_data, ucb_iob_stall, ucb_iob_vld, 
   dram_sctag0_chunk_id_r0, dram_sctag0_mecc_err_r2, 
   dram_sctag0_rd_req_id_r0, dram_sctag0_secc_err_r2, 
   dram_sctag1_chunk_id_r0, dram_sctag1_mecc_err_r2, 
   dram_sctag1_rd_req_id_r0, dram_sctag1_secc_err_r2, 
   dram_scbuf0_data_r2, dram_scbuf0_ecc_r2, dram_scbuf1_data_r2, 
   dram_scbuf1_ecc_r2, dram_local_pt0_opened_bank, 
   dram_local_pt1_opened_bank, dram_pt_max_banks_open_valid, 
   dram_pt_max_time_valid, dram_pt_ucb_data, dram_clk_tr, dram_so, 

   dram_other_pt_max_banks_open_valid, dram_other_pt_max_time_valid, 
   dram_other_pt_ucb_data, dram_other_pt0_opened_bank, 
   dram_other_pt1_opened_bank, io_dram0_data_in, io_dram0_data_valid, 
   io_dram0_ecc_in, io_dram1_data_in, io_dram1_data_valid, 
   io_dram1_ecc_in, iob_ucb_data, iob_ucb_stall, iob_ucb_vld, 
   scbuf0_dram_data_mecc_r5, scbuf0_dram_data_vld_r5, 
   scbuf0_dram_wr_data_r5, scbuf1_dram_data_mecc_r5, 
   scbuf1_dram_data_vld_r5, scbuf1_dram_wr_data_r5, sctag0_dram_addr, 
   sctag0_dram_rd_dummy_req, sctag0_dram_rd_req, 
   sctag0_dram_rd_req_id, sctag0_dram_wr_req, sctag1_dram_addr, 
   sctag1_dram_rd_dummy_req, sctag1_dram_rd_req, 
   sctag1_dram_rd_req_id, sctag1_dram_wr_req, clspine_dram_rx_sync, 
   clspine_dram_tx_sync, clspine_jbus_rx_sync, clspine_jbus_tx_sync, 
   dram_gdbginit_l, clk_dram_jbus_cken, clk_dram_dram_cken, 
   clk_dram_cmp_cken, clspine_dram_selfrsh, global_shift_enable, 
   dram_si, jbus_gclk, dram_gclk, cmp_gclk, dram_adbginit_l, 
   dram_arst_l, jbus_grst_l, dram_grst_l, cmp_grst_l, 
   ctu_tst_scanmode, ctu_tst_pre_grst_l, ctu_tst_scan_disable, 
   ctu_tst_macrotest, ctu_tst_short_chain
   );






output [14:0]		dram_io_addr0;
output [14:0]		dram_io_addr1;
output [2:0]		dram_io_bank0;
output [2:0]		dram_io_bank1;
output			dram_io_cas0_l;
output			dram_io_cas1_l;
output			dram_io_channel_disabled0;
output			dram_io_channel_disabled1;
output			dram_io_cke0;
output			dram_io_cke1;
output			dram_io_clk_enable0;
output			dram_io_clk_enable1;
output [3:0]		dram_io_cs0_l;
output [3:0]		dram_io_cs1_l;
output [287:0]		dram_io_data0_out;
output [287:0]		dram_io_data1_out;
output			dram_io_drive_data0;
output			dram_io_drive_data1;
output			dram_io_drive_enable0;
output			dram_io_drive_enable1;
output 			dram_io_pad_clk_inv0;
output 			dram_io_pad_clk_inv1;
output			dram_io_pad_enable0;
output			dram_io_pad_enable1;
output [4:0]		dram_io_ptr_clk_inv0;
output [4:0]		dram_io_ptr_clk_inv1;
output			dram_io_ras0_l;
output			dram_io_ras1_l;
output			dram_io_write_en0_l;
output			dram_io_write_en1_l;
output			dram_sctag0_data_vld_r0;
output			dram_sctag0_rd_ack;
output			dram_sctag0_scb_mecc_err;
output			dram_sctag0_scb_secc_err;
output			dram_sctag0_wr_ack;
output			dram_sctag1_data_vld_r0;
output			dram_sctag1_rd_ack;
output			dram_sctag1_scb_mecc_err;
output			dram_sctag1_scb_secc_err;
output			dram_sctag1_wr_ack;
output [3:0]		ucb_iob_data;
output			ucb_iob_stall;
output			ucb_iob_vld;
output [1:0]		dram_sctag0_chunk_id_r0;
output			dram_sctag0_mecc_err_r2;
output [2:0]		dram_sctag0_rd_req_id_r0;
output			dram_sctag0_secc_err_r2;
output [1:0]		dram_sctag1_chunk_id_r0;
output			dram_sctag1_mecc_err_r2;
output [2:0]		dram_sctag1_rd_req_id_r0;
output			dram_sctag1_secc_err_r2;
output [127:0]		dram_scbuf0_data_r2;
output [27:0]		dram_scbuf0_ecc_r2;
output [127:0]		dram_scbuf1_data_r2;
output [27:0]		dram_scbuf1_ecc_r2;
output			dram_local_pt0_opened_bank;
output			dram_local_pt1_opened_bank;
output          	dram_pt_max_banks_open_valid;
output          	dram_pt_max_time_valid;
output [16:0]   	dram_pt_ucb_data;








input          		dram_other_pt_max_banks_open_valid;
input          		dram_other_pt_max_time_valid;
input [16:0]   		dram_other_pt_ucb_data;
input			dram_other_pt0_opened_bank;
input			dram_other_pt1_opened_bank;
input [255:0]		io_dram0_data_in;
input			io_dram0_data_valid;
input [31:0]		io_dram0_ecc_in;
input [255:0]		io_dram1_data_in;
input			io_dram1_data_valid;
input [31:0]		io_dram1_ecc_in;
input [3:0]		iob_ucb_data;
input			iob_ucb_stall;
input			iob_ucb_vld;
input			scbuf0_dram_data_mecc_r5;
input			scbuf0_dram_data_vld_r5;
input [63:0]		scbuf0_dram_wr_data_r5;
input			scbuf1_dram_data_mecc_r5;
input			scbuf1_dram_data_vld_r5;
input [63:0]		scbuf1_dram_wr_data_r5;
input [39:5]		sctag0_dram_addr;
input			sctag0_dram_rd_dummy_req;
input			sctag0_dram_rd_req;
input [2:0]		sctag0_dram_rd_req_id;
input			sctag0_dram_wr_req;
input [39:5]		sctag1_dram_addr;
input			sctag1_dram_rd_dummy_req;
input			sctag1_dram_rd_req;
input [2:0]		sctag1_dram_rd_req_id;
input			sctag1_dram_wr_req;





input			clspine_dram_rx_sync;
input			clspine_dram_tx_sync;
input			clspine_jbus_rx_sync;
input			clspine_jbus_tx_sync;
input			dram_gdbginit_l;
input           	clk_dram_jbus_cken;
input           	clk_dram_dram_cken;
input           	clk_dram_cmp_cken;
input           	clspine_dram_selfrsh;
input           	global_shift_enable;
output          	dram_clk_tr;

input			dram_si;
output			dram_so;

input           	jbus_gclk;
input           	dram_gclk;
input           	cmp_gclk;

input			dram_adbginit_l;
input			dram_arst_l;
input           	jbus_grst_l;
input           	dram_grst_l;
input           	cmp_grst_l;
                                        	
input			ctu_tst_scanmode;	
input			ctu_tst_pre_grst_l;	
input			ctu_tst_scan_disable;
input			ctu_tst_macrotest;
input			ctu_tst_short_chain;






wire [3:0]		ch0_dp_data_mecc0;
wire [3:0]		ch0_dp_data_mecc1;
wire [3:0]		ch0_dp_data_mecc2;
wire [3:0]		ch0_dp_data_mecc3;
wire [3:0]		ch0_dp_data_mecc4;
wire [3:0]		ch0_dp_data_mecc5;
wire [3:0]		ch0_dp_data_mecc6;
wire [3:0]		ch0_dp_data_mecc7;
wire			ch0_dp_data_valid_d1;
wire			ch0_dram_data_val_other_ch;
wire [35:0]		ch0_err_loc;
wire [15:0]		ch0_err_syn;
wire [35:0]		ch0_que_b0_addr_picked;
wire			ch0_que_b0_cmd_picked;
wire [5:0]		ch0_que_b0_data_addr;
wire [2:0]		ch0_que_b0_id_picked;
wire [2:0]		ch0_que_b0_index_picked;
wire [7:0]		ch0_que_cas_int_picked;
wire			ch0_que_channel_picked;
wire [6:0]		ch0_que_int_wr_que_inv_info;
wire [7:0]		ch0_que_l2req_valids;
wire [255:0]		ch0_que_mem_data;
wire			ch0_que_mux_write_en;
wire [4:0]		ch0_que_pos;
wire [7:0]		ch0_que_ras_int_picked;
wire			ch0_que_wr_cas_ch01_picked;
wire [3:0]		ch1_dp_data_mecc0;
wire [3:0]		ch1_dp_data_mecc1;
wire [3:0]		ch1_dp_data_mecc2;
wire [3:0]		ch1_dp_data_mecc3;
wire [3:0]		ch1_dp_data_mecc4;
wire [3:0]		ch1_dp_data_mecc5;
wire [3:0]		ch1_dp_data_mecc6;
wire [3:0]		ch1_dp_data_mecc7;
wire			ch1_dp_data_valid_d1;
wire			ch1_dram_data_val_other_ch;
wire [35:0]		ch1_err_loc;
wire [15:0]		ch1_err_syn;
wire [35:0]		ch1_que_b0_addr_picked;
wire			ch1_que_b0_cmd_picked;
wire [5:0]		ch1_que_b0_data_addr;
wire [2:0]		ch1_que_b0_id_picked;
wire [2:0]		ch1_que_b0_index_picked;
wire [7:0]		ch1_que_cas_int_picked;
wire			ch1_que_channel_picked;
wire [6:0]		ch1_que_int_wr_que_inv_info;
wire [7:0]		ch1_que_l2req_valids;
wire [255:0]		ch1_que_mem_data;
wire			ch1_que_mux_write_en;
wire [4:0]		ch1_que_pos;
wire [7:0]		ch1_que_ras_int_picked;
wire			ch1_que_wr_cas_ch01_picked;
wire			cmp_after_clk_rst_l;
wire			cmp_rclk;
wire			cpu_cluster_so;
wire			dbginit_l;
wire			dram_cluster_so;
wire			dram_dram_rx_sync;
wire			dram_dram_tx_sync;
wire			dram_jbus_rx_sync;
wire			dram_jbus_tx_sync;
wire			dram_rclk;
wire			dram_rst_l;
wire			dram_sctag0_pa_err_r2;
wire			dram_sctag1_pa_err_r2;
wire			dram_ucb_ack_vld0;
wire			dram_ucb_ack_vld1;
wire [63:0]		dram_ucb_data0;
wire [63:0]		dram_ucb_data1;
wire			dram_ucb_nack_vld0;
wire			dram_ucb_nack_vld1;
wire			jbus_cluster_so;
wire			jbus_rclk;
wire			jbus_rst_l;
wire			l2if0_channel_disabled;
wire			l2if1_channel_disabled;
wire			l2if_err_intr0;
wire			l2if_err_intr1;
wire			l2if_ucb_trig0;
wire			l2if_ucb_trig1;
wire [64:0]		listen_out0;
wire [64:0]		listen_out1;
wire			mem_bypass;
wire			pt_ch0_blk_new_openbank;
wire			pt_ch1_blk_new_openbank;
wire [16:0]		pt_max_banks_open;
wire [15:0]		pt_max_time;
wire			que0_channel_disabled;
wire			que1_channel_disabled;
wire [16:0]		que_max_banks_open0;
wire [16:0]		que_max_banks_open1;
wire			que_max_banks_open_valid0;
wire			que_max_banks_open_valid1;
wire			que_max_time_valid0;
wire			que_max_time_valid1;
wire			se;
wire			sehold;
wire			so_0;
wire			testmode_l;
wire [31:0]		ucb_dram_addr;
wire [63:0]		ucb_dram_data;
wire			ucb_dram_rd_req_vld0;
wire			ucb_dram_rd_req_vld1;
wire			ucb_dram_wr_req_vld0;
wire			ucb_dram_wr_req_vld1;
wire			ucb_l2if_selfrsh;


wire			cpu_cluster_si;
wire			dram_cluster_si;
wire			jbus_cluster_si;
wire			long_chain_so_0;
wire			short_chain_so_0;





bw_clk_cl_dram_ddr dram_cluster_header(

				       .cluster_grst_l(dram_rst_l),
				       .dbginit_l(dbginit_l),
				       .rclk(dram_rclk),
				       .so(dram_cluster_so),

				       .adbginit_l(dram_adbginit_l),
				       .arst_l(dram_arst_l),
				       .cluster_cken(clk_dram_dram_cken),
				       .gclk(dram_gclk),
				       .gdbginit_l(dram_gdbginit_l),
				       .grst_l(dram_grst_l),
				       .se(se),
				       .si(dram_cluster_si));


bw_clk_cl_dram_cmp cpu_cluster_header(

				      .cluster_grst_l(cmp_after_clk_rst_l),
				      .dbginit_l(),
				      .rclk(cmp_rclk),
				      .so(cpu_cluster_so),

				      .adbginit_l(1'b1),
				      .arst_l(dram_arst_l),
				      .cluster_cken(clk_dram_cmp_cken),
				      .gclk(cmp_gclk),
				      .gdbginit_l(1'b1),
				      .grst_l(cmp_grst_l),
				      .se(se),
				      .si(cpu_cluster_si));
dffrl_async_ns #(1) async_rst_flop(
                .din(cmp_after_clk_rst_l),
                .q(cmp_rst_l),
                .rst_l(dram_arst_l),
                .clk(cmp_rclk));



bw_clk_cl_dram_jbus jbus_cluster_header(

					.cluster_grst_l(jbus_rst_l),
					.dbginit_l(),
					.rclk(jbus_rclk),
					.so(jbus_cluster_so),

					.adbginit_l(1'b1),
					.arst_l(dram_arst_l),
					.cluster_cken(clk_dram_jbus_cken),
					.gclk(jbus_gclk),
					.gdbginit_l(1'b1),
					.grst_l(jbus_grst_l),
					.se(se),
					.si(jbus_cluster_si));




test_stub_scan       test_stub_scan(

				    .mux_drive_disable(),
				    .mem_write_disable(),
				    .sehold(sehold),
				    .se	(se),
				    .testmode_l(testmode_l),
				    .mem_bypass(mem_bypass),
				    .so_0(so_0),
				    .so_1(),
				    .so_2(),

				    .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
				    .arst_l(dram_arst_l),
				    .global_shift_enable(global_shift_enable),
				    .ctu_tst_scan_disable(ctu_tst_scan_disable),
				    .ctu_tst_scanmode(ctu_tst_scanmode),
				    .ctu_tst_macrotest(ctu_tst_macrotest),
				    .ctu_tst_short_chain(ctu_tst_short_chain),
				    .long_chain_so_0(long_chain_so_0),
				    .short_chain_so_0(short_chain_so_0),
				    .long_chain_so_1(),
				    .short_chain_so_1(),
				    .long_chain_so_2(),
				    .short_chain_so_2());




cluster_header_sync jbus_cluster_header_sync(

					     .dram_rx_sync_local(dram_dram_rx_sync),
					     .dram_tx_sync_local(dram_dram_tx_sync),
					     .jbus_rx_sync_local(dram_jbus_rx_sync),
					     .jbus_tx_sync_local(dram_jbus_tx_sync),
					     .so(),

					     .dram_rx_sync_global(clspine_dram_rx_sync),
					     .dram_tx_sync_global(clspine_dram_tx_sync),
					     .jbus_rx_sync_global(clspine_jbus_rx_sync),
					     .jbus_tx_sync_global(clspine_jbus_tx_sync),
					     .cmp_gclk(cmp_gclk),
					     .cmp_rclk(cmp_rclk),
					     .si(),
					     .se(se));







dramctl	dramctl0(

		 .l2if_ucb_trig		(l2if_ucb_trig0),
		 .dram_sctag_chunk_id	(dram_sctag0_chunk_id_r0[1:0]),
		 .dram_sctag_data_vld	(dram_sctag0_data_vld_r0),
		 .dram_sctag_rd_req_id	(dram_sctag0_rd_req_id_r0[2:0]),
		 .dram_sctag_data	(dram_scbuf0_data_r2[127:0]),
		 .dram_sctag_mecc_err	(dram_sctag0_mecc_err_r2),
		 .dram_sctag_pa_err	(dram_sctag0_pa_err_r2),
		 .dram_sctag_secc_err	(dram_sctag0_secc_err_r2),
		 .dram_sctag_ecc	(dram_scbuf0_ecc_r2[27:0]),
		 .dram_sctag_rd_ack	(dram_sctag0_rd_ack),
		 .dram_sctag_wr_ack	(dram_sctag0_wr_ack),
		 .dram_io_data_out	(dram_io_data0_out[287:0]),
		 .dram_io_addr		(dram_io_addr0[14:0]),
		 .dram_io_bank		(dram_io_bank0[2:0]),
		 .dram_io_cas_l		(dram_io_cas0_l),
		 .dram_io_cke		(dram_io_cke0),
		 .dram_io_cs_l		(dram_io_cs0_l[3:0]),
		 .dram_io_drive_data	(dram_io_drive_data0),
		 .dram_io_drive_enable	(dram_io_drive_enable0),
		 .dram_io_ras_l		(dram_io_ras0_l),
		 .dram_io_write_en_l	(dram_io_write_en0_l),
		 .dram_io_pad_enable	(dram_io_pad_enable0),
		 .dram_io_clk_enable	(dram_io_clk_enable0),
		 .dram_io_ptr_clk_inv	(dram_io_ptr_clk_inv0),
		 .dram_io_pad_clk_inv	(dram_io_pad_clk_inv0),
		 .dram_io_channel_disabled(dram_io_channel_disabled0),
		 .dram_ucb_ack_vld	(dram_ucb_ack_vld0),
		 .dram_ucb_nack_vld	(dram_ucb_nack_vld0),
		 .dram_ucb_data		(dram_ucb_data0[63:0]),
		 .l2if_err_intr		(l2if_err_intr0),
		 .dram_local_pt_opened_bank(dram_local_pt0_opened_bank),
		 .que_max_banks_open_valid(que_max_banks_open_valid0),
		 .que_max_banks_open	(que_max_banks_open0[16:0]),
		 .que_max_time_valid	(que_max_time_valid0),
		 .dram_sctag_scb_mecc_err(dram_sctag0_scb_mecc_err),
		 .dram_sctag_scb_secc_err(dram_sctag0_scb_secc_err),
		 .que_int_pos		(ch0_que_pos[4:0]),
		 .que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]),
		 .que_ras_int_picked	(ch0_que_ras_int_picked[7:0]),
		 .que_b0_data_addr	(ch0_que_b0_data_addr[5:0]),
		 .que_l2req_valids	(ch0_que_l2req_valids[7:0]),
		 .que_b0_addr_picked	(ch0_que_b0_addr_picked[35:0]),
		 .que_b0_id_picked	(ch0_que_b0_id_picked[2:0]),
		 .que_b0_index_picked	(ch0_que_b0_index_picked[2:0]),
		 .que_b0_cmd_picked	(ch0_que_b0_cmd_picked),
		 .que_channel_picked	(ch0_que_channel_picked),
		 .dp_data_valid_d1	(ch0_dp_data_valid_d1),
		 .dram_data_val_other_ch(ch0_dram_data_val_other_ch),
		 .que_mem_data		(ch0_que_mem_data[255:0]),
		 .dp_data_mecc0		(ch0_dp_data_mecc0[3:0]),
		 .dp_data_mecc1		(ch0_dp_data_mecc1[3:0]),
		 .dp_data_mecc2		(ch0_dp_data_mecc2[3:0]),
		 .dp_data_mecc3		(ch0_dp_data_mecc3[3:0]),
		 .dp_data_mecc4		(ch0_dp_data_mecc4[3:0]),
		 .dp_data_mecc5		(ch0_dp_data_mecc5[3:0]),
		 .dp_data_mecc6		(ch0_dp_data_mecc6[3:0]),
		 .dp_data_mecc7		(ch0_dp_data_mecc7[3:0]),
		 .err_syn		(ch0_err_syn[15:0]),
		 .err_loc		(ch0_err_loc[35:0]),
		 .que_channel_disabled	(que0_channel_disabled),
		 .l2if_channel_disabled	(l2if0_channel_disabled),
		 .listen_out		(listen_out0[64:0]),
		 .que_cas_int_picked	(ch0_que_cas_int_picked[7:0]),
		 .que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
		 .que_mux_write_en	(ch0_que_mux_write_en),

		 .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),
		 .dram_dbginit_l	(dbginit_l),
		 .sctag_dram_rd_req	(sctag0_dram_rd_req),
		 .sctag_dram_rd_dummy_req(sctag0_dram_rd_dummy_req),
		 .sctag_dram_data_vld	(scbuf0_dram_data_vld_r5),
		 .sctag_dram_rd_req_id	(sctag0_dram_rd_req_id[2:0]),
		 .sctag_dram_addr	(sctag0_dram_addr[39:5]),
		 .sctag_dram_wr_req	(sctag0_dram_wr_req),
		 .sctag_dram_wr_data	(scbuf0_dram_wr_data_r5[63:0]),
		 .sctag_dram_data_mecc	(scbuf0_dram_data_mecc_r5),
		 .cmp_clk		(cmp_rclk),
		 .dram_clk		(dram_rclk),
		 .cmp_rst_l		(cmp_rst_l),
		 .dram_rst_l		(dram_rst_l),
		 .dram_arst_l		(dram_arst_l),
		 .io_dram_data_valid	(io_dram0_data_valid),
		 .io_dram_data_in	(io_dram0_data_in[255:0]),
		 .io_dram_ecc_in	(io_dram0_ecc_in[31:0]),
		 .ucb_dram_rd_req_vld	(ucb_dram_rd_req_vld0),
		 .ucb_dram_wr_req_vld	(ucb_dram_wr_req_vld0),
		 .ucb_dram_addr		(ucb_dram_addr[31:0]),
		 .ucb_dram_data		(ucb_dram_data[63:0]),
		 .pt_ch_blk_new_openbank(pt_ch0_blk_new_openbank),
		 .pt_max_banks_open	(pt_max_banks_open[16:0]),
		 .pt_max_time		(pt_max_time[15:0]),
		 .dram_dram_rx_sync	(dram_dram_rx_sync),
		 .dram_dram_tx_sync	(dram_dram_tx_sync),
		 .dram_jbus_rx_sync	(dram_jbus_rx_sync),
		 .dram_jbus_tx_sync	(dram_jbus_tx_sync),
		 .ch0_que_ras_int_picked(ch1_que_ras_int_picked[7:0]),
		 .ch0_que_b0_data_addr	(ch1_que_b0_data_addr[5:0]),
		 .ch0_que_channel_picked(ch1_que_channel_picked),
		 .ch1_que_l2req_valids	(ch1_que_l2req_valids[7:0]),
		 .ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]),
		 .ch1_que_b0_id_picked	(ch1_que_b0_id_picked[2:0]),
		 .ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]),
		 .ch1_que_b0_cmd_picked	(ch1_que_b0_cmd_picked),
		 .ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]),
		 .other_que_pos		(ch1_que_pos[4:0]),
		 .ch0_dram_data_val_other_ch(ch1_dram_data_val_other_ch),
		 .ch0_dram_sctag_chunk_id(dram_sctag1_chunk_id_r0[1:0]),
		 .ch0_dram_sctag_rd_req_id(dram_sctag1_rd_req_id_r0[2:0]),
		 .ch0_dram_sctag_data	(dram_scbuf1_data_r2[127:0]),
		 .ch0_dram_sctag_ecc	(dram_scbuf1_ecc_r2[27:0]),
		 .ch0_dram_sctag_mecc_err(dram_sctag1_mecc_err_r2),
		 .ch0_dram_sctag_pa_err	(dram_sctag1_pa_err_r2),
		 .ch0_dram_sctag_secc_err(dram_sctag1_secc_err_r2),
		 .ch0_dp_data_valid_d1	(ch1_dp_data_valid_d1),
		 .ch0_err_syn		(ch1_err_syn[15:0]),
		 .ch0_err_loc		(ch1_err_loc[35:0]),
		 .ch1_que_mem_data	(ch1_que_mem_data[255:0]),
		 .ch1_dp_data_mecc0	(ch1_dp_data_mecc0[3:0]),
		 .ch1_dp_data_mecc1	(ch1_dp_data_mecc1[3:0]),
		 .ch1_dp_data_mecc2	(ch1_dp_data_mecc2[3:0]),
		 .ch1_dp_data_mecc3	(ch1_dp_data_mecc3[3:0]),
		 .ch1_dp_data_mecc4	(ch1_dp_data_mecc4[3:0]),
		 .ch1_dp_data_mecc5	(ch1_dp_data_mecc5[3:0]),
		 .ch1_dp_data_mecc6	(ch1_dp_data_mecc6[3:0]),
		 .ch1_dp_data_mecc7	(ch1_dp_data_mecc7[3:0]),
		 .other_channel_disabled(l2if1_channel_disabled),
		 .other_que_channel_disabled(que1_channel_disabled),
		 .sehold		(sehold),
		 .mem_bypass		(mem_bypass),
		 .ch0_que_cas_int_picked(ch1_que_cas_int_picked[7:0]),
		 .ch0_que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked),
		 .ch0_que_mux_write_en	(ch1_que_mux_write_en));


dramctl	dramctl1(

		 .l2if_ucb_trig		(l2if_ucb_trig1),
		 .dram_sctag_chunk_id	(dram_sctag1_chunk_id_r0[1:0]),
		 .dram_sctag_data_vld	(dram_sctag1_data_vld_r0),
		 .dram_sctag_rd_req_id	(dram_sctag1_rd_req_id_r0[2:0]),
		 .dram_sctag_data	(dram_scbuf1_data_r2[127:0]),
		 .dram_sctag_mecc_err	(dram_sctag1_mecc_err_r2),
		 .dram_sctag_pa_err	(dram_sctag1_pa_err_r2),
		 .dram_sctag_secc_err	(dram_sctag1_secc_err_r2),
		 .dram_sctag_ecc	(dram_scbuf1_ecc_r2[27:0]),
		 .dram_sctag_rd_ack	(dram_sctag1_rd_ack),
		 .dram_sctag_wr_ack	(dram_sctag1_wr_ack),
		 .dram_io_data_out	(dram_io_data1_out[287:0]),
		 .dram_io_addr		(dram_io_addr1[14:0]),
		 .dram_io_bank		(dram_io_bank1[2:0]),
		 .dram_io_cas_l		(dram_io_cas1_l),
		 .dram_io_cke		(dram_io_cke1),
		 .dram_io_cs_l		(dram_io_cs1_l[3:0]),
		 .dram_io_drive_data	(dram_io_drive_data1),
		 .dram_io_drive_enable	(dram_io_drive_enable1),
		 .dram_io_ras_l		(dram_io_ras1_l),
		 .dram_io_write_en_l	(dram_io_write_en1_l),
		 .dram_io_pad_enable	(dram_io_pad_enable1),
		 .dram_io_clk_enable	(dram_io_clk_enable1),
		 .dram_io_ptr_clk_inv	(dram_io_ptr_clk_inv1),
		 .dram_io_pad_clk_inv	(dram_io_pad_clk_inv1),
		 .dram_io_channel_disabled(dram_io_channel_disabled1),
		 .dram_ucb_ack_vld	(dram_ucb_ack_vld1),
		 .dram_ucb_nack_vld	(dram_ucb_nack_vld1),
		 .dram_ucb_data		(dram_ucb_data1[63:0]),
		 .l2if_err_intr		(l2if_err_intr1),
		 .dram_local_pt_opened_bank(dram_local_pt1_opened_bank),
		 .que_max_banks_open_valid(que_max_banks_open_valid1),
		 .que_max_banks_open	(que_max_banks_open1[16:0]),
		 .que_max_time_valid	(que_max_time_valid1),
		 .dram_sctag_scb_mecc_err(dram_sctag1_scb_mecc_err),
		 .dram_sctag_scb_secc_err(dram_sctag1_scb_secc_err),
		 .que_int_pos		(ch1_que_pos[4:0]),
		 .que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]),
		 .que_ras_int_picked	(ch1_que_ras_int_picked[7:0]),
		 .que_b0_data_addr	(ch1_que_b0_data_addr[5:0]),
		 .que_l2req_valids	(ch1_que_l2req_valids[7:0]),
		 .que_b0_addr_picked	(ch1_que_b0_addr_picked[35:0]),
		 .que_b0_id_picked	(ch1_que_b0_id_picked[2:0]),
		 .que_b0_index_picked	(ch1_que_b0_index_picked[2:0]),
		 .que_b0_cmd_picked	(ch1_que_b0_cmd_picked),
		 .que_channel_picked	(ch1_que_channel_picked),
		 .dp_data_valid_d1	(ch1_dp_data_valid_d1),
		 .dram_data_val_other_ch(ch1_dram_data_val_other_ch),
		 .que_mem_data		(ch1_que_mem_data[255:0]),
		 .dp_data_mecc0		(ch1_dp_data_mecc0[3:0]),
		 .dp_data_mecc1		(ch1_dp_data_mecc1[3:0]),
		 .dp_data_mecc2		(ch1_dp_data_mecc2[3:0]),
		 .dp_data_mecc3		(ch1_dp_data_mecc3[3:0]),
		 .dp_data_mecc4		(ch1_dp_data_mecc4[3:0]),
		 .dp_data_mecc5		(ch1_dp_data_mecc5[3:0]),
		 .dp_data_mecc6		(ch1_dp_data_mecc6[3:0]),
		 .dp_data_mecc7		(ch1_dp_data_mecc7[3:0]),
		 .err_syn		(ch1_err_syn[15:0]),
		 .err_loc		(ch1_err_loc[35:0]),
		 .que_channel_disabled	(que1_channel_disabled),
		 .l2if_channel_disabled	(l2if1_channel_disabled),
		 .listen_out		(listen_out1[64:0]),
		 .que_cas_int_picked	(ch1_que_cas_int_picked[7:0]),
		 .que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked),
		 .que_mux_write_en	(ch1_que_mux_write_en),

		 .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),
		 .dram_dbginit_l	(dbginit_l),
		 .sctag_dram_rd_req	(sctag1_dram_rd_req),
		 .sctag_dram_rd_dummy_req(sctag1_dram_rd_dummy_req),
		 .sctag_dram_data_vld	(scbuf1_dram_data_vld_r5),
		 .sctag_dram_rd_req_id	(sctag1_dram_rd_req_id[2:0]),
		 .sctag_dram_addr	(sctag1_dram_addr[39:5]),
		 .sctag_dram_wr_req	(sctag1_dram_wr_req),
		 .sctag_dram_wr_data	(scbuf1_dram_wr_data_r5[63:0]),
		 .sctag_dram_data_mecc	(scbuf1_dram_data_mecc_r5),
		 .cmp_clk		(cmp_rclk),
		 .dram_clk		(dram_rclk),
		 .cmp_rst_l		(cmp_rst_l),
		 .dram_rst_l		(dram_rst_l),
		 .dram_arst_l		(dram_arst_l),
		 .io_dram_data_valid	(io_dram1_data_valid),
		 .io_dram_data_in	(io_dram1_data_in[255:0]),
		 .io_dram_ecc_in	(io_dram1_ecc_in[31:0]),
		 .ucb_dram_rd_req_vld	(ucb_dram_rd_req_vld1),
		 .ucb_dram_wr_req_vld	(ucb_dram_wr_req_vld1),
		 .ucb_dram_addr		(ucb_dram_addr[31:0]),
		 .ucb_dram_data		(ucb_dram_data[63:0]),
		 .pt_ch_blk_new_openbank(pt_ch1_blk_new_openbank),
		 .pt_max_banks_open	(pt_max_banks_open[16:0]),
		 .pt_max_time		(pt_max_time[15:0]),
		 .dram_dram_rx_sync	(dram_dram_rx_sync),
		 .dram_dram_tx_sync	(dram_dram_tx_sync),
		 .dram_jbus_rx_sync	(dram_jbus_rx_sync),
		 .dram_jbus_tx_sync	(dram_jbus_tx_sync),
		 .ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]),
		 .ch0_que_b0_data_addr	(ch0_que_b0_data_addr[5:0]),
		 .ch0_que_channel_picked(ch0_que_channel_picked),
		 .ch1_que_l2req_valids	(ch0_que_l2req_valids[7:0]),
		 .ch1_que_b0_addr_picked(ch0_que_b0_addr_picked[35:0]),
		 .ch1_que_b0_id_picked	(ch0_que_b0_id_picked[2:0]),
		 .ch1_que_b0_index_picked(ch0_que_b0_index_picked[2:0]),
		 .ch1_que_b0_cmd_picked	(ch0_que_b0_cmd_picked),
		 .ch1_que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]),
		 .other_que_pos		(ch0_que_pos[4:0]),
		 .ch0_dram_data_val_other_ch(ch0_dram_data_val_other_ch),
		 .ch0_dram_sctag_chunk_id(dram_sctag0_chunk_id_r0[1:0]),
		 .ch0_dram_sctag_rd_req_id(dram_sctag0_rd_req_id_r0[2:0]),
		 .ch0_dram_sctag_data	(dram_scbuf0_data_r2[127:0]),
		 .ch0_dram_sctag_ecc	(dram_scbuf0_ecc_r2[27:0]),
		 .ch0_dram_sctag_mecc_err(dram_sctag0_mecc_err_r2),
		 .ch0_dram_sctag_pa_err	(dram_sctag0_pa_err_r2),
		 .ch0_dram_sctag_secc_err(dram_sctag0_secc_err_r2),
		 .ch0_dp_data_valid_d1	(ch0_dp_data_valid_d1),
		 .ch0_err_syn		(ch0_err_syn[15:0]),
		 .ch0_err_loc		(ch0_err_loc[35:0]),
		 .ch1_que_mem_data	(ch0_que_mem_data[255:0]),
		 .ch1_dp_data_mecc0	(ch0_dp_data_mecc0[3:0]),
		 .ch1_dp_data_mecc1	(ch0_dp_data_mecc1[3:0]),
		 .ch1_dp_data_mecc2	(ch0_dp_data_mecc2[3:0]),
		 .ch1_dp_data_mecc3	(ch0_dp_data_mecc3[3:0]),
		 .ch1_dp_data_mecc4	(ch0_dp_data_mecc4[3:0]),
		 .ch1_dp_data_mecc5	(ch0_dp_data_mecc5[3:0]),
		 .ch1_dp_data_mecc6	(ch0_dp_data_mecc6[3:0]),
		 .ch1_dp_data_mecc7	(ch0_dp_data_mecc7[3:0]),
		 .other_channel_disabled(l2if0_channel_disabled),
		 .other_que_channel_disabled(que0_channel_disabled),
		 .sehold		(sehold),
		 .mem_bypass		(mem_bypass),
		 .ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]),
		 .ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
		 .ch0_que_mux_write_en	(ch0_que_mux_write_en));




dram_pt dram_pt(

		.pt_ch0_blk_new_openbank(pt_ch0_blk_new_openbank),
		.pt_ch1_blk_new_openbank(pt_ch1_blk_new_openbank),
		.pt_max_banks_open	(pt_max_banks_open[16:0]),
		.pt_max_time		(pt_max_time[15:0]),
		.dram_pt_max_banks_open_valid(dram_pt_max_banks_open_valid),
		.dram_pt_max_time_valid	(dram_pt_max_time_valid),
		.dram_pt_ucb_data	(dram_pt_ucb_data[16:0]),

		.clk			(dram_rclk),
		.rst_l			(dram_rst_l),
		.arst_l			(dram_arst_l),
		.dram_local_pt0_opened_bank(dram_local_pt0_opened_bank),
		.dram_local_pt1_opened_bank(dram_local_pt1_opened_bank),
		.dram_other_pt0_opened_bank(dram_other_pt0_opened_bank),
		.dram_other_pt1_opened_bank(dram_other_pt1_opened_bank),
		.que_max_banks_open_valid0(que_max_banks_open_valid0),
		.que_max_banks_open_valid1(que_max_banks_open_valid1),
		.que_max_banks_open0	(que_max_banks_open0[16:0]),
		.que_max_banks_open1	(que_max_banks_open1[16:0]),
		.que_max_time_valid0	(que_max_time_valid0),
		.que_max_time_valid1	(que_max_time_valid1),
		.dram_other_pt_max_banks_open_valid(dram_other_pt_max_banks_open_valid),
		.dram_other_pt_max_time_valid(dram_other_pt_max_time_valid),
		.dram_other_pt_ucb_data	(dram_other_pt_ucb_data[16:0])); 





dram_ucb dram_ucb(

		  .ucb_dram_rd_req_vld0	(ucb_dram_rd_req_vld0),
		  .ucb_dram_rd_req_vld1	(ucb_dram_rd_req_vld1),
		  .ucb_dram_wr_req_vld0	(ucb_dram_wr_req_vld0),
		  .ucb_dram_wr_req_vld1	(ucb_dram_wr_req_vld1),
		  .ucb_dram_addr	(ucb_dram_addr[31:0]),
		  .ucb_dram_data	(ucb_dram_data[63:0]),
		  .ucb_iob_data		(ucb_iob_data[3:0]),
		  .ucb_iob_stall	(ucb_iob_stall),
		  .ucb_iob_vld		(ucb_iob_vld),
		  .ddr_clk_tr		(dram_clk_tr),
		  .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),

		  .clk			(jbus_rclk),
		  .rst_l		(jbus_rst_l),
		  .clspine_dram_selfrsh	(clspine_dram_selfrsh),
		  .iob_ucb_data		(iob_ucb_data[3:0]),
		  .iob_ucb_stall	(iob_ucb_stall),
		  .iob_ucb_vld		(iob_ucb_vld),
		  .dram_ucb_ack_vld0	(dram_ucb_ack_vld0),
		  .dram_ucb_ack_vld1	(dram_ucb_ack_vld1),
		  .dram_ucb_nack_vld0	(dram_ucb_nack_vld0),
		  .dram_ucb_nack_vld1	(dram_ucb_nack_vld1),
		  .dram_ucb_data0	(dram_ucb_data0[63:0]),
		  .dram_ucb_data1	(dram_ucb_data1[63:0]),
		  .l2if_err_intr0	(l2if_err_intr0),
		  .l2if_err_intr1	(l2if_err_intr1),
		  .l2if_ucb_trig0	(l2if_ucb_trig0),
		  .l2if_ucb_trig1	(l2if_ucb_trig1));

endmodule
module dram (

   dram_io_addr0, dram_io_addr1, dram_io_bank0, dram_io_bank1, 
   dram_io_cas0_l, dram_io_cas1_l, dram_io_channel_disabled0, 
   dram_io_channel_disabled1, dram_io_cke0, dram_io_cke1, 
   dram_io_clk_enable0, dram_io_clk_enable1, dram_io_cs0_l, 
   dram_io_cs1_l, dram_io_data0_out, dram_io_data1_out, 
   dram_io_drive_data0, dram_io_drive_data1, dram_io_drive_enable0, 
   dram_io_drive_enable1, dram_io_pad_clk_inv0, dram_io_pad_clk_inv1, 
   dram_io_pad_enable0, dram_io_pad_enable1, dram_io_ptr_clk_inv0, 
   dram_io_ptr_clk_inv1, dram_io_ras0_l, dram_io_ras1_l, 
   dram_io_write_en0_l, dram_io_write_en1_l, dram_sctag0_data_vld_r0, 
   dram_sctag0_rd_ack, dram_sctag0_scb_mecc_err, 
   dram_sctag0_scb_secc_err, dram_sctag0_wr_ack, 
   dram_sctag1_data_vld_r0, dram_sctag1_rd_ack, 
   dram_sctag1_scb_mecc_err, dram_sctag1_scb_secc_err, 
   dram_sctag1_wr_ack, ucb_iob_data, ucb_iob_stall, ucb_iob_vld, 
   dram_sctag0_chunk_id_r0, dram_sctag0_mecc_err_r2, 
   dram_sctag0_rd_req_id_r0, dram_sctag0_secc_err_r2, 
   dram_sctag1_chunk_id_r0, dram_sctag1_mecc_err_r2, 
   dram_sctag1_rd_req_id_r0, dram_sctag1_secc_err_r2, 
   dram_scbuf0_data_r2, dram_scbuf0_ecc_r2, dram_scbuf1_data_r2, 
   dram_scbuf1_ecc_r2, dram_local_pt0_opened_bank, 
   dram_local_pt1_opened_bank, dram_pt_max_banks_open_valid, 
   dram_pt_max_time_valid, dram_pt_ucb_data, dram_clk_tr, dram_so, 

   dram_other_pt_max_banks_open_valid, dram_other_pt_max_time_valid, 
   dram_other_pt_ucb_data, dram_other_pt0_opened_bank, 
   dram_other_pt1_opened_bank, io_dram0_data_in, io_dram0_data_valid, 
   io_dram0_ecc_in, io_dram1_data_in, io_dram1_data_valid, 
   io_dram1_ecc_in, iob_ucb_data, iob_ucb_stall, iob_ucb_vld, 
   scbuf0_dram_data_mecc_r5, scbuf0_dram_data_vld_r5, 
   scbuf0_dram_wr_data_r5, scbuf1_dram_data_mecc_r5, 
   scbuf1_dram_data_vld_r5, scbuf1_dram_wr_data_r5, sctag0_dram_addr, 
   sctag0_dram_rd_dummy_req, sctag0_dram_rd_req, 
   sctag0_dram_rd_req_id, sctag0_dram_wr_req, sctag1_dram_addr, 
   sctag1_dram_rd_dummy_req, sctag1_dram_rd_req, 
   sctag1_dram_rd_req_id, sctag1_dram_wr_req, clspine_dram_rx_sync, 
   clspine_dram_tx_sync, clspine_jbus_rx_sync, clspine_jbus_tx_sync, 
   dram_gdbginit_l, clk_dram_jbus_cken, clk_dram_dram_cken, 
   clk_dram_cmp_cken, clspine_dram_selfrsh, global_shift_enable, 
   dram_si, jbus_gclk, dram_gclk, cmp_gclk, dram_adbginit_l, 
   dram_arst_l, jbus_grst_l, dram_grst_l, cmp_grst_l, 
   ctu_tst_scanmode, ctu_tst_pre_grst_l, ctu_tst_scan_disable, 
   ctu_tst_macrotest, ctu_tst_short_chain
   );







output [14:0]		dram_io_addr0;
output [14:0]		dram_io_addr1;
output [2:0]		dram_io_bank0;
output [2:0]		dram_io_bank1;
output			dram_io_cas0_l;
output			dram_io_cas1_l;
output			dram_io_channel_disabled0;
output			dram_io_channel_disabled1;
output			dram_io_cke0;
output			dram_io_cke1;
output			dram_io_clk_enable0;
output			dram_io_clk_enable1;
output [3:0]		dram_io_cs0_l;
output [3:0]		dram_io_cs1_l;
output [287:0]		dram_io_data0_out;
output [287:0]		dram_io_data1_out;
output			dram_io_drive_data0;
output			dram_io_drive_data1;
output			dram_io_drive_enable0;
output			dram_io_drive_enable1;
output 			dram_io_pad_clk_inv0;
output 			dram_io_pad_clk_inv1;
output			dram_io_pad_enable0;
output			dram_io_pad_enable1;
output [4:0]		dram_io_ptr_clk_inv0;
output [4:0]		dram_io_ptr_clk_inv1;
output			dram_io_ras0_l;
output			dram_io_ras1_l;
output			dram_io_write_en0_l;
output			dram_io_write_en1_l;
output			dram_sctag0_data_vld_r0;
output			dram_sctag0_rd_ack;
output			dram_sctag0_scb_mecc_err;
output			dram_sctag0_scb_secc_err;
output			dram_sctag0_wr_ack;
output			dram_sctag1_data_vld_r0;
output			dram_sctag1_rd_ack;
output			dram_sctag1_scb_mecc_err;
output			dram_sctag1_scb_secc_err;
output			dram_sctag1_wr_ack;
output [3:0]		ucb_iob_data;
output			ucb_iob_stall;
output			ucb_iob_vld;
output [1:0]		dram_sctag0_chunk_id_r0;
output			dram_sctag0_mecc_err_r2;
output [2:0]		dram_sctag0_rd_req_id_r0;
output			dram_sctag0_secc_err_r2;
output [1:0]		dram_sctag1_chunk_id_r0;
output			dram_sctag1_mecc_err_r2;
output [2:0]		dram_sctag1_rd_req_id_r0;
output			dram_sctag1_secc_err_r2;
output [127:0]		dram_scbuf0_data_r2;
output [27:0]		dram_scbuf0_ecc_r2;
output [127:0]		dram_scbuf1_data_r2;
output [27:0]		dram_scbuf1_ecc_r2;
output			dram_local_pt0_opened_bank;
output			dram_local_pt1_opened_bank;
output          	dram_pt_max_banks_open_valid;
output          	dram_pt_max_time_valid;
output [16:0]   	dram_pt_ucb_data;








input          		dram_other_pt_max_banks_open_valid;
input          		dram_other_pt_max_time_valid;
input [16:0]   		dram_other_pt_ucb_data;
input			dram_other_pt0_opened_bank;
input			dram_other_pt1_opened_bank;
input [255:0]		io_dram0_data_in;
input			io_dram0_data_valid;
input [31:0]		io_dram0_ecc_in;
input [255:0]		io_dram1_data_in;
input			io_dram1_data_valid;
input [31:0]		io_dram1_ecc_in;
input [3:0]		iob_ucb_data;
input			iob_ucb_stall;
input			iob_ucb_vld;
input			scbuf0_dram_data_mecc_r5;
input			scbuf0_dram_data_vld_r5;
input [63:0]		scbuf0_dram_wr_data_r5;
input			scbuf1_dram_data_mecc_r5;
input			scbuf1_dram_data_vld_r5;
input [63:0]		scbuf1_dram_wr_data_r5;
input [39:5]		sctag0_dram_addr;
input			sctag0_dram_rd_dummy_req;
input			sctag0_dram_rd_req;
input [2:0]		sctag0_dram_rd_req_id;
input			sctag0_dram_wr_req;
input [39:5]		sctag1_dram_addr;
input			sctag1_dram_rd_dummy_req;
input			sctag1_dram_rd_req;
input [2:0]		sctag1_dram_rd_req_id;
input			sctag1_dram_wr_req;





input			clspine_dram_rx_sync;
input			clspine_dram_tx_sync;
input			clspine_jbus_rx_sync;
input			clspine_jbus_tx_sync;
input			dram_gdbginit_l;
input           	clk_dram_jbus_cken;
input           	clk_dram_dram_cken;
input           	clk_dram_cmp_cken;
input           	clspine_dram_selfrsh;
input           	global_shift_enable;
output          	dram_clk_tr;

input			dram_si;
output			dram_so;

input           	jbus_gclk;
input           	dram_gclk;
input           	cmp_gclk;

input			dram_adbginit_l;
input			dram_arst_l;
input           	jbus_grst_l;
input           	dram_grst_l;
input           	cmp_grst_l;
                                        	
input			ctu_tst_scanmode;	
input			ctu_tst_pre_grst_l;	
input			ctu_tst_scan_disable;
input			ctu_tst_macrotest;
input			ctu_tst_short_chain;






wire [3:0]		ch0_dp_data_mecc0;
wire [3:0]		ch0_dp_data_mecc1;
wire [3:0]		ch0_dp_data_mecc2;
wire [3:0]		ch0_dp_data_mecc3;
wire [3:0]		ch0_dp_data_mecc4;
wire [3:0]		ch0_dp_data_mecc5;
wire [3:0]		ch0_dp_data_mecc6;
wire [3:0]		ch0_dp_data_mecc7;
wire			ch0_dp_data_valid_d1;
wire			ch0_dram_data_val_other_ch;
wire [35:0]		ch0_err_loc;
wire [15:0]		ch0_err_syn;
wire [35:0]		ch0_que_b0_addr_picked;
wire			ch0_que_b0_cmd_picked;
wire [5:0]		ch0_que_b0_data_addr;
wire [2:0]		ch0_que_b0_id_picked;
wire [2:0]		ch0_que_b0_index_picked;
wire [7:0]		ch0_que_cas_int_picked;
wire			ch0_que_channel_picked;
wire [6:0]		ch0_que_int_wr_que_inv_info;
wire [7:0]		ch0_que_l2req_valids;
wire [255:0]		ch0_que_mem_data;
wire			ch0_que_mux_write_en;
wire [4:0]		ch0_que_pos;
wire [7:0]		ch0_que_ras_int_picked;
wire			ch0_que_wr_cas_ch01_picked;
wire [3:0]		ch1_dp_data_mecc0;
wire [3:0]		ch1_dp_data_mecc1;
wire [3:0]		ch1_dp_data_mecc2;
wire [3:0]		ch1_dp_data_mecc3;
wire [3:0]		ch1_dp_data_mecc4;
wire [3:0]		ch1_dp_data_mecc5;
wire [3:0]		ch1_dp_data_mecc6;
wire [3:0]		ch1_dp_data_mecc7;
wire			ch1_dp_data_valid_d1;
wire			ch1_dram_data_val_other_ch;
wire [35:0]		ch1_err_loc;
wire [15:0]		ch1_err_syn;
wire [35:0]		ch1_que_b0_addr_picked;
wire			ch1_que_b0_cmd_picked;
wire [5:0]		ch1_que_b0_data_addr;
wire [2:0]		ch1_que_b0_id_picked;
wire [2:0]		ch1_que_b0_index_picked;
wire [7:0]		ch1_que_cas_int_picked;
wire			ch1_que_channel_picked;
wire [6:0]		ch1_que_int_wr_que_inv_info;
wire [7:0]		ch1_que_l2req_valids;
wire [255:0]		ch1_que_mem_data;
wire			ch1_que_mux_write_en;
wire [4:0]		ch1_que_pos;
wire [7:0]		ch1_que_ras_int_picked;
wire			ch1_que_wr_cas_ch01_picked;
wire			cmp_after_clk_rst_l;
wire			cmp_rclk;
wire			cpu_cluster_so;
wire			dbginit_l;
wire			dram_cluster_so;
wire			dram_dram_rx_sync;
wire			dram_dram_tx_sync;
wire			dram_jbus_rx_sync;
wire			dram_jbus_tx_sync;
wire			dram_rclk;
wire			dram_rst_l;
wire			dram_sctag0_pa_err_r2;
wire			dram_sctag1_pa_err_r2;
wire			dram_ucb_ack_vld0;
wire			dram_ucb_ack_vld1;
wire [63:0]		dram_ucb_data0;
wire [63:0]		dram_ucb_data1;
wire			dram_ucb_nack_vld0;
wire			dram_ucb_nack_vld1;
wire			jbus_cluster_so;
wire			jbus_rclk;
wire			jbus_rst_l;
wire			l2if0_channel_disabled;
wire			l2if1_channel_disabled;
wire			l2if_err_intr0;
wire			l2if_err_intr1;
wire			l2if_ucb_trig0;
wire			l2if_ucb_trig1;
wire [64:0]		listen_out0;
wire [64:0]		listen_out1;
wire			mem_bypass;
wire			pt_ch0_blk_new_openbank;
wire			pt_ch1_blk_new_openbank;
wire [16:0]		pt_max_banks_open;
wire [15:0]		pt_max_time;
wire			que0_channel_disabled;
wire			que1_channel_disabled;
wire [16:0]		que_max_banks_open0;
wire [16:0]		que_max_banks_open1;
wire			que_max_banks_open_valid0;
wire			que_max_banks_open_valid1;
wire			que_max_time_valid0;
wire			que_max_time_valid1;
wire			se;
wire			sehold;
wire			so_0;
wire			testmode_l;
wire [31:0]		ucb_dram_addr;
wire [63:0]		ucb_dram_data;
wire			ucb_dram_rd_req_vld0;
wire			ucb_dram_rd_req_vld1;
wire			ucb_dram_wr_req_vld0;
wire			ucb_dram_wr_req_vld1;
wire			ucb_l2if_selfrsh;


wire			cpu_cluster_si;
wire			dram_cluster_si;
wire			jbus_cluster_si;
wire			long_chain_so_0;
wire			short_chain_so_0;





bw_clk_cl_dram_ddr dram_cluster_header(

				       .cluster_grst_l(dram_rst_l),
				       .dbginit_l(dbginit_l),
				       .rclk(dram_rclk),
				       .so(dram_cluster_so),

				       .adbginit_l(dram_adbginit_l),
				       .arst_l(dram_arst_l),
				       .cluster_cken(clk_dram_dram_cken),
				       .gclk(dram_gclk),
				       .gdbginit_l(dram_gdbginit_l),
				       .grst_l(dram_grst_l),
				       .se(se),
				       .si(dram_cluster_si));


bw_clk_cl_dram_cmp cpu_cluster_header(

				      .cluster_grst_l(cmp_after_clk_rst_l),
				      .dbginit_l(),
				      .rclk(cmp_rclk),
				      .so(cpu_cluster_so),

				      .adbginit_l(1'b1),
				      .arst_l(dram_arst_l),
				      .cluster_cken(clk_dram_cmp_cken),
				      .gclk(cmp_gclk),
				      .gdbginit_l(1'b1),
				      .grst_l(cmp_grst_l),
				      .se(se),
				      .si(cpu_cluster_si));
dffrl_async_ns #(1) async_rst_flop(
                .din(cmp_after_clk_rst_l),
                .q(cmp_rst_l),
                .rst_l(dram_arst_l),
                .clk(cmp_rclk));



bw_clk_cl_dram_jbus jbus_cluster_header(

					.cluster_grst_l(jbus_rst_l),
					.dbginit_l(),
					.rclk(jbus_rclk),
					.so(jbus_cluster_so),

					.adbginit_l(1'b1),
					.arst_l(dram_arst_l),
					.cluster_cken(clk_dram_jbus_cken),
					.gclk(jbus_gclk),
					.gdbginit_l(1'b1),
					.grst_l(jbus_grst_l),
					.se(se),
					.si(jbus_cluster_si));




test_stub_scan       test_stub_scan(

				    .mux_drive_disable(),
				    .mem_write_disable(),
				    .sehold(sehold),
				    .se	(se),
				    .testmode_l(testmode_l),
				    .mem_bypass(mem_bypass),
				    .so_0(so_0),
				    .so_1(),
				    .so_2(),

				    .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
				    .arst_l(dram_arst_l),
				    .global_shift_enable(global_shift_enable),
				    .ctu_tst_scan_disable(ctu_tst_scan_disable),
				    .ctu_tst_scanmode(ctu_tst_scanmode),
				    .ctu_tst_macrotest(ctu_tst_macrotest),
				    .ctu_tst_short_chain(ctu_tst_short_chain),
				    .long_chain_so_0(long_chain_so_0),
				    .short_chain_so_0(short_chain_so_0),
				    .long_chain_so_1(),
				    .short_chain_so_1(),
				    .long_chain_so_2(),
				    .short_chain_so_2());




cluster_header_sync jbus_cluster_header_sync(

					     .dram_rx_sync_local(dram_dram_rx_sync),
					     .dram_tx_sync_local(dram_dram_tx_sync),
					     .jbus_rx_sync_local(dram_jbus_rx_sync),
					     .jbus_tx_sync_local(dram_jbus_tx_sync),
					     .so(),

					     .dram_rx_sync_global(clspine_dram_rx_sync),
					     .dram_tx_sync_global(clspine_dram_tx_sync),
					     .jbus_rx_sync_global(clspine_jbus_rx_sync),
					     .jbus_tx_sync_global(clspine_jbus_tx_sync),
					     .cmp_gclk(cmp_gclk),
					     .cmp_rclk(cmp_rclk),
					     .si(),
					     .se(se));







dramctl	dramctl0(

		 .l2if_ucb_trig		(l2if_ucb_trig0),
		 .dram_sctag_chunk_id	(dram_sctag0_chunk_id_r0[1:0]),
		 .dram_sctag_data_vld	(dram_sctag0_data_vld_r0),
		 .dram_sctag_rd_req_id	(dram_sctag0_rd_req_id_r0[2:0]),
		 .dram_sctag_data	(dram_scbuf0_data_r2[127:0]),
		 .dram_sctag_mecc_err	(dram_sctag0_mecc_err_r2),
		 .dram_sctag_pa_err	(dram_sctag0_pa_err_r2),
		 .dram_sctag_secc_err	(dram_sctag0_secc_err_r2),
		 .dram_sctag_ecc	(dram_scbuf0_ecc_r2[27:0]),
		 .dram_sctag_rd_ack	(dram_sctag0_rd_ack),
		 .dram_sctag_wr_ack	(dram_sctag0_wr_ack),
		 .dram_io_data_out	(dram_io_data0_out[287:0]),
		 .dram_io_addr		(dram_io_addr0[14:0]),
		 .dram_io_bank		(dram_io_bank0[2:0]),
		 .dram_io_cas_l		(dram_io_cas0_l),
		 .dram_io_cke		(dram_io_cke0),
		 .dram_io_cs_l		(dram_io_cs0_l[3:0]),
		 .dram_io_drive_data	(dram_io_drive_data0),
		 .dram_io_drive_enable	(dram_io_drive_enable0),
		 .dram_io_ras_l		(dram_io_ras0_l),
		 .dram_io_write_en_l	(dram_io_write_en0_l),
		 .dram_io_pad_enable	(dram_io_pad_enable0),
		 .dram_io_clk_enable	(dram_io_clk_enable0),
		 .dram_io_ptr_clk_inv	(dram_io_ptr_clk_inv0),
		 .dram_io_pad_clk_inv	(dram_io_pad_clk_inv0),
		 .dram_io_channel_disabled(dram_io_channel_disabled0),
		 .dram_ucb_ack_vld	(dram_ucb_ack_vld0),
		 .dram_ucb_nack_vld	(dram_ucb_nack_vld0),
		 .dram_ucb_data		(dram_ucb_data0[63:0]),
		 .l2if_err_intr		(l2if_err_intr0),
		 .dram_local_pt_opened_bank(dram_local_pt0_opened_bank),
		 .que_max_banks_open_valid(que_max_banks_open_valid0),
		 .que_max_banks_open	(que_max_banks_open0[16:0]),
		 .que_max_time_valid	(que_max_time_valid0),
		 .dram_sctag_scb_mecc_err(dram_sctag0_scb_mecc_err),
		 .dram_sctag_scb_secc_err(dram_sctag0_scb_secc_err),
		 .que_int_pos		(ch0_que_pos[4:0]),
		 .que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]),
		 .que_ras_int_picked	(ch0_que_ras_int_picked[7:0]),
		 .que_b0_data_addr	(ch0_que_b0_data_addr[5:0]),
		 .que_l2req_valids	(ch0_que_l2req_valids[7:0]),
		 .que_b0_addr_picked	(ch0_que_b0_addr_picked[35:0]),
		 .que_b0_id_picked	(ch0_que_b0_id_picked[2:0]),
		 .que_b0_index_picked	(ch0_que_b0_index_picked[2:0]),
		 .que_b0_cmd_picked	(ch0_que_b0_cmd_picked),
		 .que_channel_picked	(ch0_que_channel_picked),
		 .dp_data_valid_d1	(ch0_dp_data_valid_d1),
		 .dram_data_val_other_ch(ch0_dram_data_val_other_ch),
		 .que_mem_data		(ch0_que_mem_data[255:0]),
		 .dp_data_mecc0		(ch0_dp_data_mecc0[3:0]),
		 .dp_data_mecc1		(ch0_dp_data_mecc1[3:0]),
		 .dp_data_mecc2		(ch0_dp_data_mecc2[3:0]),
		 .dp_data_mecc3		(ch0_dp_data_mecc3[3:0]),
		 .dp_data_mecc4		(ch0_dp_data_mecc4[3:0]),
		 .dp_data_mecc5		(ch0_dp_data_mecc5[3:0]),
		 .dp_data_mecc6		(ch0_dp_data_mecc6[3:0]),
		 .dp_data_mecc7		(ch0_dp_data_mecc7[3:0]),
		 .err_syn		(ch0_err_syn[15:0]),
		 .err_loc		(ch0_err_loc[35:0]),
		 .que_channel_disabled	(que0_channel_disabled),
		 .l2if_channel_disabled	(l2if0_channel_disabled),
		 .listen_out		(listen_out0[64:0]),
		 .que_cas_int_picked	(ch0_que_cas_int_picked[7:0]),
		 .que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
		 .que_mux_write_en	(ch0_que_mux_write_en),

		 .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),
		 .dram_dbginit_l	(dbginit_l),
		 .sctag_dram_rd_req	(sctag0_dram_rd_req),
		 .sctag_dram_rd_dummy_req(sctag0_dram_rd_dummy_req),
		 .sctag_dram_data_vld	(scbuf0_dram_data_vld_r5),
		 .sctag_dram_rd_req_id	(sctag0_dram_rd_req_id[2:0]),
		 .sctag_dram_addr	(sctag0_dram_addr[39:5]),
		 .sctag_dram_wr_req	(sctag0_dram_wr_req),
		 .sctag_dram_wr_data	(scbuf0_dram_wr_data_r5[63:0]),
		 .sctag_dram_data_mecc	(scbuf0_dram_data_mecc_r5),
		 .cmp_clk		(cmp_rclk),
		 .dram_clk		(dram_rclk),
		 .cmp_rst_l		(cmp_rst_l),
		 .dram_rst_l		(dram_rst_l),
		 .dram_arst_l		(dram_arst_l),
		 .io_dram_data_valid	(io_dram0_data_valid),
		 .io_dram_data_in	(io_dram0_data_in[255:0]),
		 .io_dram_ecc_in	(io_dram0_ecc_in[31:0]),
		 .ucb_dram_rd_req_vld	(ucb_dram_rd_req_vld0),
		 .ucb_dram_wr_req_vld	(ucb_dram_wr_req_vld0),
		 .ucb_dram_addr		(ucb_dram_addr[31:0]),
		 .ucb_dram_data		(ucb_dram_data[63:0]),
		 .pt_ch_blk_new_openbank(pt_ch0_blk_new_openbank),
		 .pt_max_banks_open	(pt_max_banks_open[16:0]),
		 .pt_max_time		(pt_max_time[15:0]),
		 .dram_dram_rx_sync	(dram_dram_rx_sync),
		 .dram_dram_tx_sync	(dram_dram_tx_sync),
		 .dram_jbus_rx_sync	(dram_jbus_rx_sync),
		 .dram_jbus_tx_sync	(dram_jbus_tx_sync),
		 .ch0_que_ras_int_picked(ch1_que_ras_int_picked[7:0]),
		 .ch0_que_b0_data_addr	(ch1_que_b0_data_addr[5:0]),
		 .ch0_que_channel_picked(ch1_que_channel_picked),
		 .ch1_que_l2req_valids	(ch1_que_l2req_valids[7:0]),
		 .ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]),
		 .ch1_que_b0_id_picked	(ch1_que_b0_id_picked[2:0]),
		 .ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]),
		 .ch1_que_b0_cmd_picked	(ch1_que_b0_cmd_picked),
		 .ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]),
		 .other_que_pos		(ch1_que_pos[4:0]),
		 .ch0_dram_data_val_other_ch(ch1_dram_data_val_other_ch),
		 .ch0_dram_sctag_chunk_id(dram_sctag1_chunk_id_r0[1:0]),
		 .ch0_dram_sctag_rd_req_id(dram_sctag1_rd_req_id_r0[2:0]),
		 .ch0_dram_sctag_data	(dram_scbuf1_data_r2[127:0]),
		 .ch0_dram_sctag_ecc	(dram_scbuf1_ecc_r2[27:0]),
		 .ch0_dram_sctag_mecc_err(dram_sctag1_mecc_err_r2),
		 .ch0_dram_sctag_pa_err	(dram_sctag1_pa_err_r2),
		 .ch0_dram_sctag_secc_err(dram_sctag1_secc_err_r2),
		 .ch0_dp_data_valid_d1	(ch1_dp_data_valid_d1),
		 .ch0_err_syn		(ch1_err_syn[15:0]),
		 .ch0_err_loc		(ch1_err_loc[35:0]),
		 .ch1_que_mem_data	(ch1_que_mem_data[255:0]),
		 .ch1_dp_data_mecc0	(ch1_dp_data_mecc0[3:0]),
		 .ch1_dp_data_mecc1	(ch1_dp_data_mecc1[3:0]),
		 .ch1_dp_data_mecc2	(ch1_dp_data_mecc2[3:0]),
		 .ch1_dp_data_mecc3	(ch1_dp_data_mecc3[3:0]),
		 .ch1_dp_data_mecc4	(ch1_dp_data_mecc4[3:0]),
		 .ch1_dp_data_mecc5	(ch1_dp_data_mecc5[3:0]),
		 .ch1_dp_data_mecc6	(ch1_dp_data_mecc6[3:0]),
		 .ch1_dp_data_mecc7	(ch1_dp_data_mecc7[3:0]),
		 .other_channel_disabled(l2if1_channel_disabled),
		 .other_que_channel_disabled(que1_channel_disabled),
		 .sehold		(sehold),
		 .mem_bypass		(mem_bypass),
		 .ch0_que_cas_int_picked(ch1_que_cas_int_picked[7:0]),
		 .ch0_que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked),
		 .ch0_que_mux_write_en	(ch1_que_mux_write_en));


dramctl	dramctl1(

		 .l2if_ucb_trig		(l2if_ucb_trig1),
		 .dram_sctag_chunk_id	(dram_sctag1_chunk_id_r0[1:0]),
		 .dram_sctag_data_vld	(dram_sctag1_data_vld_r0),
		 .dram_sctag_rd_req_id	(dram_sctag1_rd_req_id_r0[2:0]),
		 .dram_sctag_data	(dram_scbuf1_data_r2[127:0]),
		 .dram_sctag_mecc_err	(dram_sctag1_mecc_err_r2),
		 .dram_sctag_pa_err	(dram_sctag1_pa_err_r2),
		 .dram_sctag_secc_err	(dram_sctag1_secc_err_r2),
		 .dram_sctag_ecc	(dram_scbuf1_ecc_r2[27:0]),
		 .dram_sctag_rd_ack	(dram_sctag1_rd_ack),
		 .dram_sctag_wr_ack	(dram_sctag1_wr_ack),
		 .dram_io_data_out	(dram_io_data1_out[287:0]),
		 .dram_io_addr		(dram_io_addr1[14:0]),
		 .dram_io_bank		(dram_io_bank1[2:0]),
		 .dram_io_cas_l		(dram_io_cas1_l),
		 .dram_io_cke		(dram_io_cke1),
		 .dram_io_cs_l		(dram_io_cs1_l[3:0]),
		 .dram_io_drive_data	(dram_io_drive_data1),
		 .dram_io_drive_enable	(dram_io_drive_enable1),
		 .dram_io_ras_l		(dram_io_ras1_l),
		 .dram_io_write_en_l	(dram_io_write_en1_l),
		 .dram_io_pad_enable	(dram_io_pad_enable1),
		 .dram_io_clk_enable	(dram_io_clk_enable1),
		 .dram_io_ptr_clk_inv	(dram_io_ptr_clk_inv1),
		 .dram_io_pad_clk_inv	(dram_io_pad_clk_inv1),
		 .dram_io_channel_disabled(dram_io_channel_disabled1),
		 .dram_ucb_ack_vld	(dram_ucb_ack_vld1),
		 .dram_ucb_nack_vld	(dram_ucb_nack_vld1),
		 .dram_ucb_data		(dram_ucb_data1[63:0]),
		 .l2if_err_intr		(l2if_err_intr1),
		 .dram_local_pt_opened_bank(dram_local_pt1_opened_bank),
		 .que_max_banks_open_valid(que_max_banks_open_valid1),
		 .que_max_banks_open	(que_max_banks_open1[16:0]),
		 .que_max_time_valid	(que_max_time_valid1),
		 .dram_sctag_scb_mecc_err(dram_sctag1_scb_mecc_err),
		 .dram_sctag_scb_secc_err(dram_sctag1_scb_secc_err),
		 .que_int_pos		(ch1_que_pos[4:0]),
		 .que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]),
		 .que_ras_int_picked	(ch1_que_ras_int_picked[7:0]),
		 .que_b0_data_addr	(ch1_que_b0_data_addr[5:0]),
		 .que_l2req_valids	(ch1_que_l2req_valids[7:0]),
		 .que_b0_addr_picked	(ch1_que_b0_addr_picked[35:0]),
		 .que_b0_id_picked	(ch1_que_b0_id_picked[2:0]),
		 .que_b0_index_picked	(ch1_que_b0_index_picked[2:0]),
		 .que_b0_cmd_picked	(ch1_que_b0_cmd_picked),
		 .que_channel_picked	(ch1_que_channel_picked),
		 .dp_data_valid_d1	(ch1_dp_data_valid_d1),
		 .dram_data_val_other_ch(ch1_dram_data_val_other_ch),
		 .que_mem_data		(ch1_que_mem_data[255:0]),
		 .dp_data_mecc0		(ch1_dp_data_mecc0[3:0]),
		 .dp_data_mecc1		(ch1_dp_data_mecc1[3:0]),
		 .dp_data_mecc2		(ch1_dp_data_mecc2[3:0]),
		 .dp_data_mecc3		(ch1_dp_data_mecc3[3:0]),
		 .dp_data_mecc4		(ch1_dp_data_mecc4[3:0]),
		 .dp_data_mecc5		(ch1_dp_data_mecc5[3:0]),
		 .dp_data_mecc6		(ch1_dp_data_mecc6[3:0]),
		 .dp_data_mecc7		(ch1_dp_data_mecc7[3:0]),
		 .err_syn		(ch1_err_syn[15:0]),
		 .err_loc		(ch1_err_loc[35:0]),
		 .que_channel_disabled	(que1_channel_disabled),
		 .l2if_channel_disabled	(l2if1_channel_disabled),
		 .listen_out		(listen_out1[64:0]),
		 .que_cas_int_picked	(ch1_que_cas_int_picked[7:0]),
		 .que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked),
		 .que_mux_write_en	(ch1_que_mux_write_en),

		 .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),
		 .dram_dbginit_l	(dbginit_l),
		 .sctag_dram_rd_req	(sctag1_dram_rd_req),
		 .sctag_dram_rd_dummy_req(sctag1_dram_rd_dummy_req),
		 .sctag_dram_data_vld	(scbuf1_dram_data_vld_r5),
		 .sctag_dram_rd_req_id	(sctag1_dram_rd_req_id[2:0]),
		 .sctag_dram_addr	(sctag1_dram_addr[39:5]),
		 .sctag_dram_wr_req	(sctag1_dram_wr_req),
		 .sctag_dram_wr_data	(scbuf1_dram_wr_data_r5[63:0]),
		 .sctag_dram_data_mecc	(scbuf1_dram_data_mecc_r5),
		 .cmp_clk		(cmp_rclk),
		 .dram_clk		(dram_rclk),
		 .cmp_rst_l		(cmp_rst_l),
		 .dram_rst_l		(dram_rst_l),
		 .dram_arst_l		(dram_arst_l),
		 .io_dram_data_valid	(io_dram1_data_valid),
		 .io_dram_data_in	(io_dram1_data_in[255:0]),
		 .io_dram_ecc_in	(io_dram1_ecc_in[31:0]),
		 .ucb_dram_rd_req_vld	(ucb_dram_rd_req_vld1),
		 .ucb_dram_wr_req_vld	(ucb_dram_wr_req_vld1),
		 .ucb_dram_addr		(ucb_dram_addr[31:0]),
		 .ucb_dram_data		(ucb_dram_data[63:0]),
		 .pt_ch_blk_new_openbank(pt_ch1_blk_new_openbank),
		 .pt_max_banks_open	(pt_max_banks_open[16:0]),
		 .pt_max_time		(pt_max_time[15:0]),
		 .dram_dram_rx_sync	(dram_dram_rx_sync),
		 .dram_dram_tx_sync	(dram_dram_tx_sync),
		 .dram_jbus_rx_sync	(dram_jbus_rx_sync),
		 .dram_jbus_tx_sync	(dram_jbus_tx_sync),
		 .ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]),
		 .ch0_que_b0_data_addr	(ch0_que_b0_data_addr[5:0]),
		 .ch0_que_channel_picked(ch0_que_channel_picked),
		 .ch1_que_l2req_valids	(ch0_que_l2req_valids[7:0]),
		 .ch1_que_b0_addr_picked(ch0_que_b0_addr_picked[35:0]),
		 .ch1_que_b0_id_picked	(ch0_que_b0_id_picked[2:0]),
		 .ch1_que_b0_index_picked(ch0_que_b0_index_picked[2:0]),
		 .ch1_que_b0_cmd_picked	(ch0_que_b0_cmd_picked),
		 .ch1_que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]),
		 .other_que_pos		(ch0_que_pos[4:0]),
		 .ch0_dram_data_val_other_ch(ch0_dram_data_val_other_ch),
		 .ch0_dram_sctag_chunk_id(dram_sctag0_chunk_id_r0[1:0]),
		 .ch0_dram_sctag_rd_req_id(dram_sctag0_rd_req_id_r0[2:0]),
		 .ch0_dram_sctag_data	(dram_scbuf0_data_r2[127:0]),
		 .ch0_dram_sctag_ecc	(dram_scbuf0_ecc_r2[27:0]),
		 .ch0_dram_sctag_mecc_err(dram_sctag0_mecc_err_r2),
		 .ch0_dram_sctag_pa_err	(dram_sctag0_pa_err_r2),
		 .ch0_dram_sctag_secc_err(dram_sctag0_secc_err_r2),
		 .ch0_dp_data_valid_d1	(ch0_dp_data_valid_d1),
		 .ch0_err_syn		(ch0_err_syn[15:0]),
		 .ch0_err_loc		(ch0_err_loc[35:0]),
		 .ch1_que_mem_data	(ch0_que_mem_data[255:0]),
		 .ch1_dp_data_mecc0	(ch0_dp_data_mecc0[3:0]),
		 .ch1_dp_data_mecc1	(ch0_dp_data_mecc1[3:0]),
		 .ch1_dp_data_mecc2	(ch0_dp_data_mecc2[3:0]),
		 .ch1_dp_data_mecc3	(ch0_dp_data_mecc3[3:0]),
		 .ch1_dp_data_mecc4	(ch0_dp_data_mecc4[3:0]),
		 .ch1_dp_data_mecc5	(ch0_dp_data_mecc5[3:0]),
		 .ch1_dp_data_mecc6	(ch0_dp_data_mecc6[3:0]),
		 .ch1_dp_data_mecc7	(ch0_dp_data_mecc7[3:0]),
		 .other_channel_disabled(l2if0_channel_disabled),
		 .other_que_channel_disabled(que0_channel_disabled),
		 .sehold		(sehold),
		 .mem_bypass		(mem_bypass),
		 .ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]),
		 .ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
		 .ch0_que_mux_write_en	(ch0_que_mux_write_en));




dram_pt dram_pt(

		.pt_ch0_blk_new_openbank(pt_ch0_blk_new_openbank),
		.pt_ch1_blk_new_openbank(pt_ch1_blk_new_openbank),
		.pt_max_banks_open	(pt_max_banks_open[16:0]),
		.pt_max_time		(pt_max_time[15:0]),
		.dram_pt_max_banks_open_valid(dram_pt_max_banks_open_valid),
		.dram_pt_max_time_valid	(dram_pt_max_time_valid),
		.dram_pt_ucb_data	(dram_pt_ucb_data[16:0]),

		.clk			(dram_rclk),
		.rst_l			(dram_rst_l),
		.arst_l			(dram_arst_l),
		.dram_local_pt0_opened_bank(dram_local_pt0_opened_bank),
		.dram_local_pt1_opened_bank(dram_local_pt1_opened_bank),
		.dram_other_pt0_opened_bank(dram_other_pt0_opened_bank),
		.dram_other_pt1_opened_bank(dram_other_pt1_opened_bank),
		.que_max_banks_open_valid0(que_max_banks_open_valid0),
		.que_max_banks_open_valid1(que_max_banks_open_valid1),
		.que_max_banks_open0	(que_max_banks_open0[16:0]),
		.que_max_banks_open1	(que_max_banks_open1[16:0]),
		.que_max_time_valid0	(que_max_time_valid0),
		.que_max_time_valid1	(que_max_time_valid1),
		.dram_other_pt_max_banks_open_valid(dram_other_pt_max_banks_open_valid),
		.dram_other_pt_max_time_valid(dram_other_pt_max_time_valid),
		.dram_other_pt_ucb_data	(dram_other_pt_ucb_data[16:0])); 





dram_ucb dram_ucb(

		  .ucb_dram_rd_req_vld0	(ucb_dram_rd_req_vld0),
		  .ucb_dram_rd_req_vld1	(ucb_dram_rd_req_vld1),
		  .ucb_dram_wr_req_vld0	(ucb_dram_wr_req_vld0),
		  .ucb_dram_wr_req_vld1	(ucb_dram_wr_req_vld1),
		  .ucb_dram_addr	(ucb_dram_addr[31:0]),
		  .ucb_dram_data	(ucb_dram_data[63:0]),
		  .ucb_iob_data		(ucb_iob_data[3:0]),
		  .ucb_iob_stall	(ucb_iob_stall),
		  .ucb_iob_vld		(ucb_iob_vld),
		  .ddr_clk_tr		(dram_clk_tr),
		  .ucb_l2if_selfrsh	(ucb_l2if_selfrsh),

		  .clk			(jbus_rclk),
		  .rst_l		(jbus_rst_l),
		  .clspine_dram_selfrsh	(clspine_dram_selfrsh),
		  .iob_ucb_data		(iob_ucb_data[3:0]),
		  .iob_ucb_stall	(iob_ucb_stall),
		  .iob_ucb_vld		(iob_ucb_vld),
		  .dram_ucb_ack_vld0	(dram_ucb_ack_vld0),
		  .dram_ucb_ack_vld1	(dram_ucb_ack_vld1),
		  .dram_ucb_nack_vld0	(dram_ucb_nack_vld0),
		  .dram_ucb_nack_vld1	(dram_ucb_nack_vld1),
		  .dram_ucb_data0	(dram_ucb_data0[63:0]),
		  .dram_ucb_data1	(dram_ucb_data1[63:0]),
		  .l2if_err_intr0	(l2if_err_intr0),
		  .l2if_err_intr1	(l2if_err_intr1),
		  .l2if_ucb_trig0	(l2if_ucb_trig0),
		  .l2if_ucb_trig1	(l2if_ucb_trig1));

endmodule