data/full_repos/permissive/454159683/mux81c/mux81c.v
data/verilator_xmls/88171528-4277-49e2-8d7a-1d961c02fe64.xml
module mux81c(input in0, in1, in2, in3, in4, in5, in6, in7, input[2:0] sel, output reg out);
	always @(sel)
	begin
		if (sel == 0)
			out = in0;
		else if (sel == 1)
			out = in1;
		else if (sel == 2)
			out = in2;
		else if (sel == 3)
			out = in3;
		else if (sel == 4)
			out = in4;
		else if (sel == 5)
			out = in5;
		else if (sel == 6)
			out = in6;
		else
			out = in7;
	end














endmodule
module mux81c(input in0, in1, in2, in3, in4, in5, in6, in7, input[2:0] sel, output reg out);

	always @(sel)
	begin
		if (sel == 0)
			out = in0;
		else if (sel == 1)
			out = in1;
		else if (sel == 2)
			out = in2;
		else if (sel == 3)
			out = in3;
		else if (sel == 4)
			out = in4;
		else if (sel == 5)
			out = in5;
		else if (sel == 6)
			out = in6;
		else
			out = in7;
	end














endmodule