data/full_repos/permissive/473722449/reg_4bit_str.v
1: b"%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:24: Cannot find file containing module: 'mux2x1dataflow'\n    mux2x1dataflow m0 (load,q[o],d[0],w1[0]);\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux2x1dataflow\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux2x1dataflow.v\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux2x1dataflow.sv\n             mux2x1dataflow\n             mux2x1dataflow.v\n             mux2x1dataflow.sv\n             obj_dir/mux2x1dataflow\n             obj_dir/mux2x1dataflow.v\n             obj_dir/mux2x1dataflow.sv\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:25: Cannot find file containing module: 'mux2x1dataflow'\n    mux2x1dataflow m1 (load,q[1],d[1],w1[1]);\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:26: Cannot find file containing module: 'mux2x1dataflow'\n    mux2x1dataflow m2 (load,q[2],d[2],w1[2]);\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:27: Cannot find file containing module: 'mux2x1dataflow'\n    mux2x1dataflow m3 (load,q[3],d[3],w1[3]);\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:29: Cannot find file containing module: 'DFF'\n    DFF d0 (w1[0],clk,q[0]);\n    ^~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:30: Cannot find file containing module: 'DFF'\n    DFF d1 (w1[1],clk,q[1]);\n    ^~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:31: Cannot find file containing module: 'DFF'\n    DFF d2 (w1[2],clk,q[2]);\n    ^~~\n%Error: data/full_repos/permissive/473722449/reg_4bit_str.v:32: Cannot find file containing module: 'DFF'\n    DFF d3 (w1[3],clk,q[3]);\n    ^~~\n%Error: Exiting due to 8 error(s)\n"
module reg_4bit_str(
    input [3:0] d,
    input clk,
    input load,
    output wire [3:0] q
    );
    wire [3:0] w1; 
    mux2x1dataflow m0 (load,q[o],d[0],w1[0]);
    mux2x1dataflow m1 (load,q[1],d[1],w1[1]);
    mux2x1dataflow m2 (load,q[2],d[2],w1[2]);
    mux2x1dataflow m3 (load,q[3],d[3],w1[3]);
    
    DFF d0 (w1[0],clk,q[0]);
    DFF d1 (w1[1],clk,q[1]);
    DFF d2 (w1[2],clk,q[2]);
    DFF d3 (w1[3],clk,q[3]);
    
endmodule
module reg_4bit_str(
    input [3:0] d,
    input clk,
    input load,
    output wire [3:0] q
    );

    wire [3:0] w1; 
    mux2x1dataflow m0 (load,q[o],d[0],w1[0]);
    mux2x1dataflow m1 (load,q[1],d[1],w1[1]);
    mux2x1dataflow m2 (load,q[2],d[2],w1[2]);
    mux2x1dataflow m3 (load,q[3],d[3],w1[3]);
    
    DFF d0 (w1[0],clk,q[0]);
    DFF d1 (w1[1],clk,q[1]);
    DFF d2 (w1[2],clk,q[2]);
    DFF d3 (w1[3],clk,q[3]);
    
endmodule