data/full_repos/permissive/45365961/hello.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/45365961/hello.v:20: Little bit endian vector: MSB < LSB of bit range: 0:159\n   reg [0:20 * 8 - 1] message;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                              : ... In instance hello\n        state <= 3\'h0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:38: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                              : ... In instance hello\n               state <= 3\'h1;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:40: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                              : ... In instance hello\n              state <= 3\'h3;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:44: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                              : ... In instance hello\n               state <= 3\'h2;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:48: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                              : ... In instance hello\n              state <= 3\'h0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:49: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                              : ... In instance hello\n          default: state <= 3\'h3;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/45365961/hello.v:32: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                              : ... In instance hello\n        case (state)\n        ^~~~\n%Error: data/full_repos/permissive/45365961/hello.v:53: Cannot find file containing module: \'uart\'\n   uart yuart(\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/45365961,data/full_repos/permissive/45365961/uart\n             data/full_repos/permissive/45365961,data/full_repos/permissive/45365961/uart.v\n             data/full_repos/permissive/45365961,data/full_repos/permissive/45365961/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module hello(
             input  clk_50,
             input  reset_n,
             output tx);

   reg [7:0] data;
   reg       dataReady;

   wire      busy;

   reg [0:`MESSAGE_LEN_BITS - 1] message;

   reg [1:0] state;

   always @(posedge clk_50 or negedge reset_n)
     if (reset_n == 1'b0) begin
        data <= 0;
        dataReady <= 0;

        message <= `MESSAGE;
        state <= `STATE_BYTE_START;
     end else begin
        case (state)
          `STATE_BYTE_START:
            if (message[0:7] != 0) begin
               data <= message[0:7];
               message <= {message[8:`MESSAGE_LEN_BITS - 1], 8'd0};
               dataReady <= 1;
               state <= `STATE_BYTE_WAIT_FOR_BUSY;
            end else
              state <= `STATE_STOPPED;
          `STATE_BYTE_WAIT_FOR_BUSY:
            if (busy) begin
               dataReady <= 0;
               state <= `STATE_BYTE_WAIT_FOR_NOT_BUSY;
            end
          `STATE_BYTE_WAIT_FOR_NOT_BUSY:
            if (!busy)
              state <= `STATE_BYTE_START;
          default: state <= `STATE_STOPPED;
        endcase
     end

   uart yuart(
              .clk(clk_50),
              .reset(!reset_n),
              .data(data),
              .dataReady(dataReady),
              .busy(busy),
              .tx(tx)
              );
endmodule
module hello(
             input  clk_50,
             input  reset_n,
             output tx);


   reg [7:0] data;
   reg       dataReady;

   wire      busy;

   reg [0:`MESSAGE_LEN_BITS - 1] message;

   reg [1:0] state;

   always @(posedge clk_50 or negedge reset_n)
     if (reset_n == 1'b0) begin
        data <= 0;
        dataReady <= 0;

        message <= `MESSAGE;
        state <= `STATE_BYTE_START;
     end else begin
        case (state)
          `STATE_BYTE_START:
            if (message[0:7] != 0) begin
               data <= message[0:7];
               message <= {message[8:`MESSAGE_LEN_BITS - 1], 8'd0};
               dataReady <= 1;
               state <= `STATE_BYTE_WAIT_FOR_BUSY;
            end else
              state <= `STATE_STOPPED;
          `STATE_BYTE_WAIT_FOR_BUSY:
            if (busy) begin
               dataReady <= 0;
               state <= `STATE_BYTE_WAIT_FOR_NOT_BUSY;
            end
          `STATE_BYTE_WAIT_FOR_NOT_BUSY:
            if (!busy)
              state <= `STATE_BYTE_START;
          default: state <= `STATE_STOPPED;
        endcase
     end

   uart yuart(
              .clk(clk_50),
              .reset(!reset_n),
              .data(data),
              .dataReady(dataReady),
              .busy(busy),
              .tx(tx)
              );
endmodule