data/full_repos/permissive/422650017/verilog/rtl/elpis/forwardingunit.v
1: b'%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/forwardingunit.v:17: Cannot find include file: /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n    `include "/project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module forwardingunit(
	input[4:0] ex_reg_a_in,
	input[4:0] ex_reg_b_in,
	input[4:0] mem_reg_d_in,
	input[4:0] wb_reg_d_in,
	input mem_reg_we_in,
	input wb_reg_we_in,
	output reg[1:0] forward_x,
	output reg[1:0] forward_y
);

	always@(*) begin
		if (wb_reg_we_in & (wb_reg_d_in != 0) & 
			!(mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_a_in)) & 
			(wb_reg_d_in == ex_reg_a_in)) 
				forward_x <= 2'b01;
		else if (mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_a_in)) 
			forward_x <= 2'b10;
		else 
			forward_x <= 2'b00;
		
		if (wb_reg_we_in & (wb_reg_d_in != 0) & 
			!(mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_b_in)) & 
			(wb_reg_d_in == ex_reg_b_in) ) 
				forward_y <= 2'b01;
		else if (mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_b_in)) 
			forward_y <= 2'b10;
		else 
			forward_y <= 2'b00;
	end
	
endmodule
module forwardingunit(
	input[4:0] ex_reg_a_in,
	input[4:0] ex_reg_b_in,
	input[4:0] mem_reg_d_in,
	input[4:0] wb_reg_d_in,
	input mem_reg_we_in,
	input wb_reg_we_in,
	output reg[1:0] forward_x,
	output reg[1:0] forward_y
);


	always@(*) begin
		if (wb_reg_we_in & (wb_reg_d_in != 0) & 
			!(mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_a_in)) & 
			(wb_reg_d_in == ex_reg_a_in)) 
				forward_x <= 2'b01;
		else if (mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_a_in)) 
			forward_x <= 2'b10;
		else 
			forward_x <= 2'b00;
		
		if (wb_reg_we_in & (wb_reg_d_in != 0) & 
			!(mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_b_in)) & 
			(wb_reg_d_in == ex_reg_b_in) ) 
				forward_y <= 2'b01;
		else if (mem_reg_we_in & (mem_reg_d_in != 0) & (mem_reg_d_in == ex_reg_b_in)) 
			forward_y <= 2'b10;
		else 
			forward_y <= 2'b00;
	end
	
endmodule