data/full_repos/permissive/423852699/tb/DMEM_IO.v
1: b"%Error: data/full_repos/permissive/423852699/tb/DMEM_IO.v:29: Cannot find file containing module: 'bram'\n    bram bram_inst (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/423852699/tb,data/full_repos/permissive/423852699/bram\n             data/full_repos/permissive/423852699/tb,data/full_repos/permissive/423852699/bram.v\n             data/full_repos/permissive/423852699/tb,data/full_repos/permissive/423852699/bram.sv\n             bram\n             bram.v\n             bram.sv\n             obj_dir/bram\n             obj_dir/bram.v\n             obj_dir/bram.sv\n%Error: Exiting due to 1 error(s)\n"
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata,


    input wire[7:0] opr1,
    input wire[7:0] opr2,
    output wire[15:0] result
);
    wire[31:0] bram_result;
    wire bram_we = ~ask_addr[31] & we;

    reg[7:0] opr1_reg;
    reg[7:0] opr2_reg;

    assign rdata = fetch_addr[31] ? (fetch_addr[2] ? {24'h0, opr2_reg} : {24'h0, opr1_reg})
                    : bram_result;



    reg[15:0] display_result;
    assign result = display_result;

    bram bram_inst (
        .clka(clk),
        .ena(1'b1),
        .wea(bram_we),
        .addra(ask_addr[17:2]),
        .dina(wdata),
        .douta(bram_result)
    );

    always @(posedge clk) begin
        if (we) begin
            if (ask_addr[31] & ask_addr[3]) begin
                display_result <= wdata[15:0];
            end
        end

        opr1_reg <= opr1;
        opr2_reg <= opr2;
    end
endmodule
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata,


    input wire[7:0] opr1,
    input wire[7:0] opr2,
    output wire[15:0] result
);

    wire[31:0] bram_result;
    wire bram_we = ~ask_addr[31] & we;

    reg[7:0] opr1_reg;
    reg[7:0] opr2_reg;

    assign rdata = fetch_addr[31] ? (fetch_addr[2] ? {24'h0, opr2_reg} : {24'h0, opr1_reg})
                    : bram_result;



    reg[15:0] display_result;
    assign result = display_result;

    bram bram_inst (
        .clka(clk),
        .ena(1'b1),
        .wea(bram_we),
        .addra(ask_addr[17:2]),
        .dina(wdata),
        .douta(bram_result)
    );

    always @(posedge clk) begin
        if (we) begin
            if (ask_addr[31] & ask_addr[3]) begin
                display_result <= wdata[15:0];
            end
        end

        opr1_reg <= opr1;
        opr2_reg <= opr2;
    end
endmodule