data/full_repos/permissive/460663963/Randomizer.v
data/verilator_xmls/79d6d1c0-7ac2-4809-b4c1-eed8e728b94f.xml
module randomizer(
input wire I,
input wire clk,
input wire reset,
input wire load,
input wire en,
input wire [14:0] seed,
output reg O
);

reg [14:0] Initial;
reg temp;

assign Initial = 15'b011011100010101;

always @ (posedge clk) begin

if (reset == 1) begin
	Initial <= 0;
end

if (load == 1) begin
	Initial <= seed;
end

if (en == 1) begin
	temp = Initial[0] ^ Initial[1];
	Initial <= Initial >> 1;
	Initial[14] <= temp;
	O = temp ^ I;
end

end

endmodule
module randomizer(
input wire I,
input wire clk,
input wire reset,
input wire load,
input wire en,
input wire [14:0] seed,
output reg O
);


reg [14:0] Initial;
reg temp;

assign Initial = 15'b011011100010101;

always @ (posedge clk) begin

if (reset == 1) begin
	Initial <= 0;
end

if (load == 1) begin
	Initial <= seed;
end

if (en == 1) begin
	temp = Initial[0] ^ Initial[1];
	Initial <= Initial >> 1;
	Initial[14] <= temp;
	O = temp ^ I;
end

end

endmodule