data/full_repos/permissive/451577625/system/multiplier_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/multiplier_32.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 32\'ha; in_y = 32\'ha;   \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/multiplier_32.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 32\'h61; in_y = 32\'h56;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/multiplier_32.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 32\'hFFFFFFF3; in_y = 32\'hB;   \n  ^\n%Error: data/full_repos/permissive/451577625/system/multiplier_32.v:18: Cannot find file containing module: \'bit_pair_recoder_32\'\n   bit_pair_recoder_32 recoder(.in_multiplier (in_x),\n   ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/bit_pair_recoder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/bit_pair_recoder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/bit_pair_recoder_32.sv\n             bit_pair_recoder_32\n             bit_pair_recoder_32.v\n             bit_pair_recoder_32.sv\n             obj_dir/bit_pair_recoder_32\n             obj_dir/bit_pair_recoder_32.v\n             obj_dir/bit_pair_recoder_32.sv\n%Error: data/full_repos/permissive/451577625/system/multiplier_32.v:26: Cannot find file containing module: \'reducer_64\'\n   reducer_64 reducer(.in_w (w_partial_products_shift[4*i]),\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/multiplier_32.v:37: Cannot find file containing module: \'reducer_64\'\n   reducer_64 reducer(.in_w (w_reduce_16_to_8[4*i]),\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/multiplier_32.v:47: Cannot find file containing module: \'reducer_64\'\n  reducer_64 reducer(.in_w (w_reduce_8_to_4[0]),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/multiplier_32.v:56: Cannot find file containing module: \'cla_64\'\n  cla_64 adder(.in_x (w_reduce_4_to_2[0]),\n  ^~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier_32 (input [31:0] in_x, input [31:0] in_y, output [63:0] out_product);

	wire [63:0] w_partial_products [0:15];
	wire [63:0] w_partial_products_shift [0:15];
	wire [63:0] w_reduce_16_to_8 [0:7];
	wire [63:0] w_reduce_8_to_4 [0:3];
	wire [63:0] w_reduce_4_to_2 [0:1];
	wire [32:0] w_padded_multiplicand;
	
	assign w_padded_multiplicand = {in_y, 1'b0};
	
	genvar i;
	


	generate
		for(i = 0; i < 16; i = i + 1) begin : gen_partial_products
			bit_pair_recoder_32 recoder(.in_multiplier (in_x),
				.in_bit_pair (w_padded_multiplicand[(i*2)+2:(i*2)]),
				.out_recode (w_partial_products[i]));
				
			assign w_partial_products_shift[i] = {w_partial_products[i][63-(2*i):0], {(2*i){1'b0}}};
		end
				
		for(i = 0; i < 4; i = i + 1) begin : gen_reduce_16_to_8
			reducer_64 reducer(.in_w (w_partial_products_shift[4*i]),
				.in_x (w_partial_products_shift[(4*i)+1]),
				.in_y (w_partial_products_shift[(4*i)+2]),
				.in_z (w_partial_products_shift[(4*i)+3]),
				.in_cin (1'b0),
				.out_sum (w_reduce_16_to_8[2*i]),
				.out_carry (w_reduce_16_to_8[(2*i)+1]),
				.out_cout ());
		end
		
		for(i = 0; i < 2; i = i + 1) begin : gen_reduce_8_to_4
			reducer_64 reducer(.in_w (w_reduce_16_to_8[4*i]),
				.in_x (w_reduce_16_to_8[(4*i)+1]),
				.in_y (w_reduce_16_to_8[(4*i)+2]),
				.in_z (w_reduce_16_to_8[(4*i)+3]),
				.in_cin (1'b0),
				.out_sum (w_reduce_8_to_4[2*i]),
				.out_carry (w_reduce_8_to_4[(2*i)+1]),
				.out_cout ());  
		end
		
		reducer_64 reducer(.in_w (w_reduce_8_to_4[0]),
			.in_x (w_reduce_8_to_4[1]),
			.in_y (w_reduce_8_to_4[2]),
			.in_z (w_reduce_8_to_4[3]),
			.in_cin (1'b0),
			.out_sum (w_reduce_4_to_2[0]),
			.out_carry (w_reduce_4_to_2[1]),
			.out_cout ());
		
		cla_64 adder(.in_x (w_reduce_4_to_2[0]),
			.in_y (w_reduce_4_to_2[1]),
			.in_carry (1'b0),
			.out_sum (out_product),
			.out_carry (),
			.out_propogate (),
			.out_generate ());
			
	endgenerate

endmodule
module multiplier_32 (input [31:0] in_x, input [31:0] in_y, output [63:0] out_product);


	wire [63:0] w_partial_products [0:15];
	wire [63:0] w_partial_products_shift [0:15];
	wire [63:0] w_reduce_16_to_8 [0:7];
	wire [63:0] w_reduce_8_to_4 [0:3];
	wire [63:0] w_reduce_4_to_2 [0:1];
	wire [32:0] w_padded_multiplicand;
	
	assign w_padded_multiplicand = {in_y, 1'b0};
	
	genvar i;
	


	generate
		for(i = 0; i < 16; i = i + 1) begin : gen_partial_products
			bit_pair_recoder_32 recoder(.in_multiplier (in_x),
				.in_bit_pair (w_padded_multiplicand[(i*2)+2:(i*2)]),
				.out_recode (w_partial_products[i]));
				
			assign w_partial_products_shift[i] = {w_partial_products[i][63-(2*i):0], {(2*i){1'b0}}};
		end
				
		for(i = 0; i < 4; i = i + 1) begin : gen_reduce_16_to_8
			reducer_64 reducer(.in_w (w_partial_products_shift[4*i]),
				.in_x (w_partial_products_shift[(4*i)+1]),
				.in_y (w_partial_products_shift[(4*i)+2]),
				.in_z (w_partial_products_shift[(4*i)+3]),
				.in_cin (1'b0),
				.out_sum (w_reduce_16_to_8[2*i]),
				.out_carry (w_reduce_16_to_8[(2*i)+1]),
				.out_cout ());
		end
		
		for(i = 0; i < 2; i = i + 1) begin : gen_reduce_8_to_4
			reducer_64 reducer(.in_w (w_reduce_16_to_8[4*i]),
				.in_x (w_reduce_16_to_8[(4*i)+1]),
				.in_y (w_reduce_16_to_8[(4*i)+2]),
				.in_z (w_reduce_16_to_8[(4*i)+3]),
				.in_cin (1'b0),
				.out_sum (w_reduce_8_to_4[2*i]),
				.out_carry (w_reduce_8_to_4[(2*i)+1]),
				.out_cout ());  
		end
		
		reducer_64 reducer(.in_w (w_reduce_8_to_4[0]),
			.in_x (w_reduce_8_to_4[1]),
			.in_y (w_reduce_8_to_4[2]),
			.in_z (w_reduce_8_to_4[3]),
			.in_cin (1'b0),
			.out_sum (w_reduce_4_to_2[0]),
			.out_carry (w_reduce_4_to_2[1]),
			.out_cout ());
		
		cla_64 adder(.in_x (w_reduce_4_to_2[0]),
			.in_y (w_reduce_4_to_2[1]),
			.in_carry (1'b0),
			.out_sum (out_product),
			.out_carry (),
			.out_propogate (),
			.out_generate ());
			
	endgenerate

endmodule