data/full_repos/permissive/426864978/lab3/task2/task2.sv
1: b"%Error: data/full_repos/permissive/426864978/lab3/task2/task2.sv:27: Cannot find file containing module: 'init'\n    init i(.clk(CLOCK_50),\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/426864978/lab3/task2,data/full_repos/permissive/426864978/init\n             data/full_repos/permissive/426864978/lab3/task2,data/full_repos/permissive/426864978/init.v\n             data/full_repos/permissive/426864978/lab3/task2,data/full_repos/permissive/426864978/init.sv\n             init\n             init.v\n             init.sv\n             obj_dir/init\n             obj_dir/init.v\n             obj_dir/init.sv\n%Error: data/full_repos/permissive/426864978/lab3/task2/task2.sv:35: Cannot find file containing module: 'ksa'\n    ksa k(.clk(CLOCK_50),\n    ^~~\n%Error: data/full_repos/permissive/426864978/lab3/task2/task2.sv:45: Cannot find file containing module: 's_mem'\n    s_mem s(.address(addr),\n    ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module task2(input logic CLOCK_50, input logic [3:0] KEY, input logic [9:0] SW,
             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
             output logic [9:0] LEDR);

    logic rst_n, en_i, en_k, rdy_i, rdy_k, wren, wren_i, wren_k, enabled_i, enabled_k;
    logic [7:0] addr, addr_i, addr_k, wrdata, wrdata_i, wrdata_k, q;

    assign rst_n = KEY[3];
    assign en_i = rdy_i & ~enabled_i;
    assign en_k = rdy_k & ~enabled_k && rdy_i && enabled_i;

    assign { addr, wrdata, wren } = (en_k | enabled_k) ? { addr_k, wrdata_k, wren_k } : { addr_i, wrdata_i, wren_i };

    always @(posedge CLOCK_50) begin
       if (rst_n == 1'b0) begin
            enabled_i <= 1'b0;
            enabled_k <= 1'b0;
       end
       if (en_i == 1'b1)
            enabled_i <= 1'b1;

        if (en_k == 1'b1)
            enabled_k <= 1'b1;
    end

    init i(.clk(CLOCK_50),
           .rst_n(rst_n),
           .en(en_i),
           .rdy(rdy_i),
           .addr(addr_i),
           .wrdata(wrdata_i),
           .wren(wren_i));

    ksa k(.clk(CLOCK_50),
          .rst_n(rst_n),
          .en(en_k),
          .rdy(rdy_k),
          .key({14'b0, SW[9:0]}),
          .addr(addr_k),
          .rddata(q),
          .wrdata(wrdata_k),
          .wren(wren_k));

    s_mem s(.address(addr),
            .clock(CLOCK_50),
            .data(wrdata),
            .wren(wren),
            .q(q));

endmodule
module task2(input logic CLOCK_50, input logic [3:0] KEY, input logic [9:0] SW,
             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
             output logic [9:0] LEDR);


    logic rst_n, en_i, en_k, rdy_i, rdy_k, wren, wren_i, wren_k, enabled_i, enabled_k;
    logic [7:0] addr, addr_i, addr_k, wrdata, wrdata_i, wrdata_k, q;

    assign rst_n = KEY[3];
    assign en_i = rdy_i & ~enabled_i;
    assign en_k = rdy_k & ~enabled_k && rdy_i && enabled_i;

    assign { addr, wrdata, wren } = (en_k | enabled_k) ? { addr_k, wrdata_k, wren_k } : { addr_i, wrdata_i, wren_i };

    always @(posedge CLOCK_50) begin
       if (rst_n == 1'b0) begin
            enabled_i <= 1'b0;
            enabled_k <= 1'b0;
       end
       if (en_i == 1'b1)
            enabled_i <= 1'b1;

        if (en_k == 1'b1)
            enabled_k <= 1'b1;
    end

    init i(.clk(CLOCK_50),
           .rst_n(rst_n),
           .en(en_i),
           .rdy(rdy_i),
           .addr(addr_i),
           .wrdata(wrdata_i),
           .wren(wren_i));

    ksa k(.clk(CLOCK_50),
          .rst_n(rst_n),
          .en(en_k),
          .rdy(rdy_k),
          .key({14'b0, SW[9:0]}),
          .addr(addr_k),
          .rddata(q),
          .wrdata(wrdata_k),
          .wren(wren_k));

    s_mem s(.address(addr),
            .clock(CLOCK_50),
            .data(wrdata),
            .wren(wren),
            .q(q));

endmodule