data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit_test.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit_test.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("add_1bit_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit_test.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test_add_1bit);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit_test.v:16: Unsupported or unknown PLI call: $monitor\n        $monitor($time, ": a=%b, b=%b, c_in=%b, sum=%b, cout=%b\\n", a,b,c_in, sum, c_out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n                #5 {a,b,c_in} = i;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_add_1bit();

reg a,b,c_in;
wire signed sum;
wire c_out;
integer i;

add_1bit Adder(a,b,c_in,sum,c_out);

initial 
    begin
        $dumpfile("add_1bit_test.vcd");
        $dumpvars(0, test_add_1bit);
        {a,b,c_in} = 0;

        $monitor($time, ": a=%b, b=%b, c_in=%b, sum=%b, cout=%b\n", a,b,c_in, sum, c_out);
            for(i = 0; i < 8; i = i + 1) begin
                #5 {a,b,c_in} = i;
            end
    end
endmodule
module test_add_1bit();


reg a,b,c_in;
wire signed sum;
wire c_out;
integer i;

add_1bit Adder(a,b,c_in,sum,c_out);

initial 
    begin
        $dumpfile("add_1bit_test.vcd");
        $dumpvars(0, test_add_1bit);
        {a,b,c_in} = 0;

        $monitor($time, ": a=%b, b=%b, c_in=%b, sum=%b, cout=%b\n", a,b,c_in, sum, c_out);
            for(i = 0; i < 8; i = i + 1) begin
                #5 {a,b,c_in} = i;
            end
    end
endmodule