data/full_repos/permissive/505898990/verilog/rtl/examples/distance_display_mine_orginal.v
1: b"%Error: data/full_repos/permissive/505898990/verilog/rtl/examples/distance_display_mine_orginal.v:435: syntax error, unexpected ';', expecting ')' or ','\n    output reg [7:0] o_segments = 0;\n                                   ^\n%Error: Exiting due to 1 error(s)\n"
module seg8 (
    input wire [3:0] i_bcd_digit,
    output reg [7:0] o_segments = 0;
);

	always @(*) begin
        case(i_bcd_digit)

            0:  o_segments = 8'b00111111;
            1:  o_segments = 8'b00000110;
            2:  o_segments = 8'b01011011;
            3:  o_segments = 8'b01001111;
            4:  o_segments = 8'b01100110;
            5:  o_segments = 8'b01101101;
            6:  o_segments = 8'b01111100;
            7:  o_segments = 8'b00000111;
            8:  o_segments = 8'b01111111;
            9:  o_segments = 8'b01100111;
           16:  o_segments = 8'b01000000;
            default:    
                o_segments = 8'b00000000;
        endcase
    end

endmodule
module seg8 (
    input wire [3:0] i_bcd_digit,
    output reg [7:0] o_segments = 0;

);

	always @(*) begin
        case(i_bcd_digit)

            0:  o_segments = 8'b00111111;
            1:  o_segments = 8'b00000110;
            2:  o_segments = 8'b01011011;
            3:  o_segments = 8'b01001111;
            4:  o_segments = 8'b01100110;
            5:  o_segments = 8'b01101101;
            6:  o_segments = 8'b01111100;
            7:  o_segments = 8'b00000111;
            8:  o_segments = 8'b01111111;
            9:  o_segments = 8'b01100111;
           16:  o_segments = 8'b01000000;
            default:    
                o_segments = 8'b00000000;
        endcase
    end

endmodule