data/full_repos/permissive/441359809/src/yosys/tests/simple/hierarchy.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/hierarchy.v:19: Operator VAR \'d\' expects 8 bits on the Initial value, but Initial value\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                          : ... In instance top.foo\nparameter [7:0] d = 0;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/hierarchy.v:22: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 4 bits.\n                                                                                          : ... In instance top.foo\nassign y1 = a;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/hierarchy.v:23: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 4 bits.\n                                                                                          : ... In instance top.foo\nassign y2 = b;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/hierarchy.v:24: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'c\' generates 3 bits.\n                                                                                          : ... In instance top.foo\nassign y3 = c;\n          ^\n%Error: Exiting due to 4 warning(s)\n'
module top(a, b, y1, y2, y3, y4);
input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;





submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);

endmodule
module top(a, b, y1, y2, y3, y4);

input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;





submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);

endmodule