data/full_repos/permissive/455421905/src/even_odd.v
1: b"%Error: data/full_repos/permissive/455421905/src/even_odd.v:80: Cannot find file containing module: 'COMPARATOR'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: Exiting due to 1 error(s)\n"
module CAE #(parameter              FLOAT  = "no",
             parameter              SIGNED = "no",
             parameter              DATW = 64,
             parameter              KEYW = 32)
            (input  wire            CLK,
             input  wire [DATW-1:0] DIN0,
             input  wire [DATW-1:0] DIN1,
             output wire [DATW-1:0] DOT0,
             output wire [DATW-1:0] DOT1);

  function [DATW-1:0] mux;
    input [DATW-1:0] a;
    input [DATW-1:0] b;
    input            sel;
    begin
      case (sel)
        1'b0: mux = a;
        1'b1: mux = b;
      endcase
    end
  endfunction

  wire comparator_rslt;
  COMPARATOR #(FLOAT, SIGNED, KEYW)
  comparator(DIN0[KEYW-1:0], DIN1[KEYW-1:0], comparator_rslt);

  reg [DATW-1:0] din0;      always @(posedge CLK) din0      <= DIN0;
  reg [DATW-1:0] din1;      always @(posedge CLK) din1      <= DIN1;
  reg            comp_rslt; always @(posedge CLK) comp_rslt <= comparator_rslt;

  assign DOT0 = mux(din1, din0, comp_rslt);
  assign DOT1 = mux(din0, din1, comp_rslt);

endmodule
module CAE #(parameter              FLOAT  = "no",
             parameter              SIGNED = "no",
             parameter              DATW = 64,
             parameter              KEYW = 32)
            (input  wire            CLK,
             input  wire [DATW-1:0] DIN0,
             input  wire [DATW-1:0] DIN1,
             output wire [DATW-1:0] DOT0,
             output wire [DATW-1:0] DOT1);


  function [DATW-1:0] mux;
    input [DATW-1:0] a;
    input [DATW-1:0] b;
    input            sel;
    begin
      case (sel)
        1'b0: mux = a;
        1'b1: mux = b;
      endcase
    end
  endfunction

  wire comparator_rslt;
  COMPARATOR #(FLOAT, SIGNED, KEYW)
  comparator(DIN0[KEYW-1:0], DIN1[KEYW-1:0], comparator_rslt);

  reg [DATW-1:0] din0;      always @(posedge CLK) din0      <= DIN0;
  reg [DATW-1:0] din1;      always @(posedge CLK) din1      <= DIN1;
  reg            comp_rslt; always @(posedge CLK) comp_rslt <= comparator_rslt;

  assign DOT0 = mux(din1, din0, comp_rslt);
  assign DOT1 = mux(din0, din1, comp_rslt);

endmodule