data/full_repos/permissive/445918935/led_blink.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445918935/led_blink.v:11: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h5b8d80\' generates 32 bits.\n                                                                   : ... In instance led_blink\n    reg [32:0]tick_limit = 32\'d06_000_000;\n                           ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module led_blink(
    input sysclk,
    input [1:0]btn,
    output [1:0]led
);



    reg [32:0]tick_limit = 32'd06_000_000;
    reg [32:0]tick_count = 0;
    reg led_state = 0;

    always @ (posedge sysclk) begin
        if (btn[0]) begin
            tick_limit <= tick_limit - 1;
        end

        if (btn[1]) begin
            tick_limit <= tick_limit + 1;
        end

        tick_count <= tick_count + 1'b1;
        if (tick_count > tick_limit) begin
            tick_count <= 0;
            led_state <= ~led_state;
        end
    end

    assign led[0] = led_state;
endmodule
module led_blink(
    input sysclk,
    input [1:0]btn,
    output [1:0]led
);




    reg [32:0]tick_limit = 32'd06_000_000;
    reg [32:0]tick_count = 0;
    reg led_state = 0;

    always @ (posedge sysclk) begin
        if (btn[0]) begin
            tick_limit <= tick_limit - 1;
        end

        if (btn[1]) begin
            tick_limit <= tick_limit + 1;
        end

        tick_count <= tick_count + 1'b1;
        if (tick_count > tick_limit) begin
            tick_count <= 0;
            led_state <= ~led_state;
        end
    end

    assign led[0] = led_state;
endmodule