data/full_repos/permissive/512700783/Instruction_Memory.v
data/verilator_xmls/90be29be-098c-429c-8a4b-a25b50c2ccff.xml
module Instruction_Memory(A, RD);
	input [31:0] A;
	output reg [31:0] RD;
	reg [7:0] Memory[0:59];
	initial
		$readmemb("init.dat",Memory);
	
	always @(A)
	begin
		RD={Memory[A],Memory[A+1],Memory[A+2],Memory[A+3]};
	end
endmodule
module Instruction_Memory(A, RD);

	input [31:0] A;
	output reg [31:0] RD;
	reg [7:0] Memory[0:59];
	initial
		$readmemb("init.dat",Memory);
	
	always @(A)
	begin
		RD={Memory[A],Memory[A+1],Memory[A+2],Memory[A+3]};
	end
endmodule