data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:2: Cannot find include file: F_ADD.v\n`include "F_ADD.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v.sv\n             F_ADD.v\n             F_ADD.v.v\n             F_ADD.v.sv\n             obj_dir/F_ADD.v\n             obj_dir/F_ADD.v.v\n             obj_dir/F_ADD.v.sv\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("F_ADD_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(2,F_ADD_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module F_ADD_tb();
reg A,B,C;
wire S,O;
F_ADD uut(A,B,C,S,O);
initial begin
  $dumpfile("F_ADD_tb.vcd");
  $dumpvars(2,F_ADD_tb);

  A=0;
  B=0;
  C=0;
  #20
  A=0;
  B=0;
  C=1;
  #20
  A=0;
  B=1;
  C=0;
  #20
  A=0;
  B=1;
  C=1;
  #20
  A=1;
  B=0;
  C=0;
  #20
  A=1;
  B=0;
  C=1;
  #20
  A=1;
  B=1;
  C=0;
  #20
  A=1;
  B=1;
  C=1;
  #20
$display("test Done");
end

endmodule
module F_ADD_tb();

reg A,B,C;
wire S,O;
F_ADD uut(A,B,C,S,O);
initial begin
  $dumpfile("F_ADD_tb.vcd");
  $dumpvars(2,F_ADD_tb);

  A=0;
  B=0;
  C=0;
  #20
  A=0;
  B=0;
  C=1;
  #20
  A=0;
  B=1;
  C=0;
  #20
  A=0;
  B=1;
  C=1;
  #20
  A=1;
  B=0;
  C=0;
  #20
  A=1;
  B=0;
  C=1;
  #20
  A=1;
  B=1;
  C=0;
  #20
  A=1;
  B=1;
  C=1;
  #20
$display("test Done");
end

endmodule