data/full_repos/permissive/507889320/Single_Port_RAM_64x8bit.v
data/verilator_xmls/2141f822-8ba8-4865-889d-bd68b9febbb9.xml
module Single_Port_RAM_64x8bit(
    input [7:0] data,
    input [5:0] addr,
    input we,
    input clk,
    output [7:0] q
    );


	reg [7:0] ram [63:0];
	reg [5:0] addr_reg;
	
	always @(posedge clk) begin
	if(we)
		ram[addr] <= data;
	else
		addr_reg <= addr;
	end
	
	assign q = ram[addr_reg];
endmodule
module Single_Port_RAM_64x8bit(
    input [7:0] data,
    input [5:0] addr,
    input we,
    input clk,
    output [7:0] q
    );



	reg [7:0] ram [63:0];
	reg [5:0] addr_reg;
	
	always @(posedge clk) begin
	if(we)
		ram[addr] <= data;
	else
		addr_reg <= addr;
	end
	
	assign q = ram[addr_reg];
endmodule