data/full_repos/permissive/487478597/riscv_mem.v
1: b'%Error: data/full_repos/permissive/487478597/riscv_mem.v:66: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(status == 2\'b01) begin\n                    ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:71: syntax error, unexpected \'{\'\n                    {cache_reg[index][{addr[3:2], 2\'h3}], cache_reg[index][{addr[3:2], 2\'h2}], \n                    ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:74: syntax error, unexpected \'[\', expecting IDENTIFIER\n                else cache_reg[index][addr[3:0]] = Wdata;\n                              ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:79: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    Rdata = {cache_reg[index][{addr[3:2], 2\'h3}], \n                          ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};\n                           ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:95: syntax error, unexpected <=, expecting IDENTIFIER\n           mem_Wdata <= {cache_reg[index][{cnt, 2\'h3}], \n                     ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n            mem_Wdata <= 0;\n                      ^~\n%Warning-STMTDLY: data/full_repos/permissive/487478597/riscv_mem.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #1 request_num = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module main_mem #(parameter addr_sz = 10, mem_sz = 1024, data_sz = 32) (
    input [addr_sz-1:0] addr,
    input isWrite,
    input [data_sz-1:0] Wdata,
    output reg [data_sz-1:0] Rdata,
    output reg Done
);
    reg [7:0] mem_reg [0:mem_sz-1];
    integer i;
    initial begin 
        Done = 1;
        Rdata = 0;
        for(i=0;i<mem_sz;i=i+1) mem_reg[i] = 0;
        $readmemh("./bin.txt", mem_reg);
    end
    always @(*) begin
        Done = 0;
        if (isWrite) begin {mem_reg[addr+3], mem_reg[addr+2], mem_reg[addr+1], mem_reg[addr]} = Wdata; end
        else begin Rdata = {mem_reg[addr+3], mem_reg[addr+2], mem_reg[addr+1], mem_reg[addr]}; end

        Done <= 1;
    end
endmodule
module main_mem #(parameter addr_sz = 10, mem_sz = 1024, data_sz = 32) (
    input [addr_sz-1:0] addr,
    input isWrite,
    input [data_sz-1:0] Wdata,
    output reg [data_sz-1:0] Rdata,
    output reg Done
);

    reg [7:0] mem_reg [0:mem_sz-1];
    integer i;
    initial begin 
        Done = 1;
        Rdata = 0;
        for(i=0;i<mem_sz;i=i+1) mem_reg[i] = 0;
        $readmemh("./bin.txt", mem_reg);
    end
    always @(*) begin
        Done = 0;
        if (isWrite) begin {mem_reg[addr+3], mem_reg[addr+2], mem_reg[addr+1], mem_reg[addr]} = Wdata; end
        else begin Rdata = {mem_reg[addr+3], mem_reg[addr+2], mem_reg[addr+1], mem_reg[addr]}; end

        Done <= 1;
    end
endmodule