data/full_repos/permissive/433621701/generic_RB_array/generic_RB_array.v
data/verilator_xmls/f286a25c-41cd-4fb2-9dca-4e8b4365cf08.xml
module Full_Adder(input a, b, carry_in, output reg sum, carry_out);
    always @(a or b or carry_in)
    begin
        sum = a ^ b ^ carry_in;
        carry_out = a & b | (a^b) & carry_in;
    end
endmodule
module Full_Adder(input a, b, carry_in, output reg sum, carry_out);

    always @(a or b or carry_in)
    begin
        sum = a ^ b ^ carry_in;
        carry_out = a & b | (a^b) & carry_in;
    end
endmodule