data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Karnaugh_Map_to_Circuit/73_Kmap1.v
data/verilator_xmls/952d752f-054d-4c11-bf22-03009093738f.xml
module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    
    assign out = ~(~a & ~b & ~c);


endmodule
module top_module(
    input a,
    input b,
    input c,
    output out  );
 
    
    assign out = ~(~a & ~b & ~c);


endmodule