data/full_repos/permissive/465580112/GRU/mac.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:43: Operator ADD expects 6 bits on the LHS, but LHS\'s REPLICATE generates 4 bits.\n                                                                 : ... In instance mac2.mul.m13.m12.m8\n q[7:2]=({2\'b00,q0[3:2]}+q1[3:0])+({2\'b00,q2[3:0]}+{q3[3:0],2\'b00});\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:43: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance mac2.mul.m13.m12.m8\n q[7:2]=({2\'b00,q0[3:2]}+q1[3:0])+({2\'b00,q2[3:0]}+{q3[3:0],2\'b00});\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:72: Operator ADD expects 12 bits on the LHS, but LHS\'s REPLICATE generates 8 bits.\n                                                                 : ... In instance mac2.mul.m13.m12\nq[15:4]=({4\'b0000,q0[7:4]}+q1[7:0])+({4\'b0000,q2[7:0]}+{q3[7:0],4\'b0000});\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:72: Operator ADD expects 12 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                 : ... In instance mac2.mul.m13.m12\nq[15:4]=({4\'b0000,q0[7:4]}+q1[7:0])+({4\'b0000,q2[7:0]}+{q3[7:0],4\'b0000});\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:101: Operator ADD expects 24 bits on the LHS, but LHS\'s REPLICATE generates 16 bits.\n                                                                  : ... In instance mac2.mul.m13\n q[31:8]=({8\'b00000000,q0[15:8]}+q1[15:0])+({8\'b00000000,q2[15:0]}+{q3[15:0],8\'b00000000});\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:101: Operator ADD expects 24 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                  : ... In instance mac2.mul.m13\n q[31:8]=({8\'b00000000,q0[15:8]}+q1[15:0])+({8\'b00000000,q2[15:0]}+{q3[15:0],8\'b00000000});\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:118: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'p0\' generates 15 bits.\n                                                                  : ... In instance mac2.mul\n  mul16 m13(cs,p0,p1,q[31:0]);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:118: Input port connection \'b\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'p1\' generates 15 bits.\n                                                                  : ... In instance mac2.mul\n  mul16 m13(cs,p0,p1,q[31:0]);\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:126: Operator ASSIGN expects 28 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                  : ... In instance mac2.mul\nresult[27:0] = q[31:0];\n             ^\n%Error: Exiting due to 9 warning(s)\n'
module addq(
input en, 
input [15:0]x,y,
output reg [15:0] sum

);
reg [15:0] op1,op2;
reg cout;

always@(*)
begin

if(en)
begin
  
    sum=16'b0;
cout=0;
    op1=x;
    op2=y;
    	if(x[15]==1'b1)
      	op1={1'b1,~x[14:0]+1'b1};
	else
	op1=op1;
    	if(y[15]==1'b1)
      	op2={1'b1,~y[14:0]+1'b1};
	else
	op2=op2;

 {cout,sum}=op1+op2;
  	if(sum[15]==1'b1)
    	sum={1'b1,~sum[14:0]+1'b1};
	else
	sum=sum;
end
else;
end
endmodule
module addq(
input en, 
input [15:0]x,y,
output reg [15:0] sum

);

reg [15:0] op1,op2;
reg cout;

always@(*)
begin

if(en)
begin
  
    sum=16'b0;
cout=0;
    op1=x;
    op2=y;
    	if(x[15]==1'b1)
      	op1={1'b1,~x[14:0]+1'b1};
	else
	op1=op1;
    	if(y[15]==1'b1)
      	op2={1'b1,~y[14:0]+1'b1};
	else
	op2=op2;

 {cout,sum}=op1+op2;
  	if(sum[15]==1'b1)
    	sum={1'b1,~sum[14:0]+1'b1};
	else
	sum=sum;
end
else;
end
endmodule