data/full_repos/permissive/458870430/rtl/VTL_chip.v
1: b'%Error: data/full_repos/permissive/458870430/rtl/VTL_chip.v:130: Cannot find file containing module: \'rom_charset\'\nrom_charset rom_charset (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458870430/rtl,data/full_repos/permissive/458870430/rom_charset\n             data/full_repos/permissive/458870430/rtl,data/full_repos/permissive/458870430/rom_charset.v\n             data/full_repos/permissive/458870430/rtl,data/full_repos/permissive/458870430/rom_charset.sv\n             rom_charset\n             rom_charset.v\n             rom_charset.sv\n             obj_dir/rom_charset\n             obj_dir/rom_charset.v\n             obj_dir/rom_charset.sv\n%Error: data/full_repos/permissive/458870430/rtl/VTL_chip.v:136: Cannot find file containing module: \'rom_charset_alternate\'\nrom_charset_alternate rom_charset_alternate (\n^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:146: Operator LT expects 10 bits on the RHS, but RHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nassign hsync = (hcnt < hsw) ? 0 : 1;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:151: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nwire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:151: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nwire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:151: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nwire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:151: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nwire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:158: Operator SUB expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'hcnt\' generates 10 bits.\n                                                                       : ... In instance VTL_chip\nassign xcnt = hcnt - (hsw+hbp+LEFT_BORDER_WIDTH);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:158: Operator ADD expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nassign xcnt = hcnt - (hsw+hbp+LEFT_BORDER_WIDTH);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:158: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\nassign xcnt = hcnt - (hsw+hbp+LEFT_BORDER_WIDTH);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:197: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n  if(hcnt == hsw+hbp+H+hfp-1) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:197: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n  if(hcnt == hsw+hbp+H+hfp-1) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:197: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'hfp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n  if(hcnt == hsw+hbp+H+hfp-1) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:398: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n      (hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:398: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n      (hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:398: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'hsw\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n      (hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) \n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:398: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'hbp\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n      (hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) \n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:454: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'sdram_dout\' generates 8 bits.\n                                                                       : ... In instance VTL_chip\n    charsetAddress <= (sdram_dout << 3) | ycnt[2:0];  \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:454: Operator OR expects 13 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                       : ... In instance VTL_chip\n    charsetAddress <= (sdram_dout << 3) | ycnt[2:0];  \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:473: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt1\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n        if(vdc_graphic_mode_number == 5) ramAddress = ramAddress + (xcnt1 >> 3);   \n                                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:474: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt2\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n     else if(vdc_graphic_mode_number == 4) ramAddress = ramAddress + (xcnt2 >> 3);   \n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:475: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt1\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n     else if(vdc_graphic_mode_number == 3) ramAddress = ramAddress + (xcnt1 >> 3);   \n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:492: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt1\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n        if(vdc_graphic_mode_number == 2) ramAddress = ramAddress + (xcnt1 >> 4);   \n                                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:493: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt3\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n     else if(vdc_graphic_mode_number == 1) ramAddress = ramAddress + (xcnt3 >> 4);   \n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:509: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt1\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n     ramAddress = ramAddress + (xcnt1 >> 3); \n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:526: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt1\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n       if(vdc_text80_enabled) ramAddress = ramAddress + (xcnt1 >> 3);   \n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/458870430/rtl/VTL_chip.v:527: Operator SHIFTR expects 14 bits on the LHS, but LHS\'s VARREF \'xcnt2\' generates 13 bits.\n                                                                       : ... In instance VTL_chip\n    else                        ramAddress = ramAddress + (xcnt2 >> 3);\n                                                                 ^~\n%Error: Exiting due to 2 error(s), 25 warning(s)\n'
module VTL_chip 
(	
	input    F14M,
	input    RESET,
	input    BLANK,
		

   output           CPUCK,
	output reg       CPUENA,
	output           WAIT_n,
	input            MREQ_n,
	input            IORQ_n,
	input            RD_n,
	input            WR_n,
	input     [15:0] A,
	input      [7:0] DO,
	output reg [7:0] DI,
	

	input [ 6:0] KD,  
   input        CASIN,

   input [31:0] joystick_0,
	input [31:0] joystick_1,
	

	output reg [24:0] sdram_addr,
	input       [7:0] sdram_dout,
   output reg  [7:0] sdram_din,
	output reg        sdram_wr,
	output reg        sdram_rd,
	

	output hsync,
	output vsync,
	output [5:0] r,
	output [5:0] g,
	output [5:0] b,
	output display_enable,
	
	output reg BUZZER,
	output reg CASOUT,
	
	input  alt_font,
	output [2:0] cnt,
	
	input          img_mounted, 
   input   [31:0] img_size    
);

reg [7:0] hfp = 10;
reg [7:0] hsw = 66;
reg [7:0] hbp = 70;






parameter HEIGHT              = 192;
parameter TOP_BORDER_WIDTH    =  65;
parameter BOTTOM_BORDER_WIDTH =  55;
parameter V                   = 313;

parameter WIDTH               = 640;
parameter LEFT_BORDER_WIDTH   =  72;
parameter RIGHT_BORDER_WIDTH  =  86;
parameter H                   = 798;



reg[9:0]   hcnt;
reg[9:0]   vcnt;
wire[12:0] xcnt;
wire[12:0] xcnt1;
wire[12:0] xcnt2;
wire[12:0] xcnt3;
wire[9:0]  ycnt;

reg[7:0]  char;
reg[7:0]  fgbg;
reg[7:0]  ramData;
reg[7:0]  ramDataD;
reg[13:0] ramAddress;

reg[7:0]  ramQ;

reg [3:0] pixel;

reg [2:0] vdc_graphic_mode_number;
reg       vdc_text80_enabled     ;
reg [3:0] vdc_text80_foreground  ;
reg [3:0] vdc_text80_background  ;
reg [3:0] vdc_border_color       ;
reg       vdc_page_7             ;


reg caps_lock_bit           ;
reg vdc_graphic_mode_enabled;


parameter col0 = 12'h000;
parameter col1 = 12'h00f;
parameter col2 = 12'h080;
parameter col3 = 12'h08f;
parameter col4 = 12'ha00;
parameter col5 = 12'hf0f;
parameter col6 = 12'h780;
parameter col7 = 12'h999;
parameter col8 = 12'h555;
parameter col9 = 12'h88f;
parameter cola = 12'h0f0;
parameter colb = 12'h4ff;
parameter colc = 12'hf45;
parameter cold = 12'hf9f;
parameter cole = 12'hcf0;
parameter colf = 12'hfff;

reg[12:0] charsetAddress;

wire[7:0] charsetQ;
wire[7:0] charsetQ_alt;
wire[7:0] charsetQ_std; 

assign charsetQ = (!alt_font) ? charsetQ_std : charsetQ_alt;

rom_charset rom_charset (
	.address(charsetAddress),
	.clock(F14M),
	.q(charsetQ_std)
);							  						

rom_charset_alternate rom_charset_alternate (
	.address(charsetAddress),
	.clock(F14M),
	.q(charsetQ_alt)
);							  						

wire [3:0] fg;
wire [3:0] bg;


assign hsync = (hcnt < hsw) ? 0 : 1;
assign vsync = (vcnt <   2) ? 0 : 1;

assign display_enable = ~non_visible_area;

wire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;
						  

assign fg = (vdc_graphic_mode_enabled && (vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 2)) || (!vdc_graphic_mode_enabled && vdc_text80_enabled) ? vdc_text80_foreground : fgbg[7:4];
assign bg = (vdc_graphic_mode_enabled && (vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 2)) || (!vdc_graphic_mode_enabled && vdc_text80_enabled) ? vdc_text80_background : fgbg[3:0];


assign xcnt = hcnt - (hsw+hbp+LEFT_BORDER_WIDTH);

assign xcnt1 = xcnt + 8 +8;
assign xcnt2 = xcnt + 16+8;
assign xcnt3 = xcnt + 24+8;

assign ycnt = vcnt - TOP_BORDER_WIDTH;

wire [2:0] VDC_cnt = hcnt[2:0];
wire [1:0] CPU_cnt = hcnt[1:0];

assign cnt = VDC_cnt;

assign CPUCK  = VDC_cnt[1];



wire MREQ   = ~MREQ_n;
wire WR     = ~WR_n;
wire RD     = ~RD_n;
wire IORQ   = ~IORQ_n;



reg MREQ_old;
reg skip_beat;

always@(posedge F14M) begin
	if(RESET) begin
		hcnt <= 0;  
		vcnt <= 0;
		banks[0] <= 0;		
	end
	else begin		   
		

		if(hcnt == hsw+hbp+H+hfp-1) begin
			hcnt <= 10'd0;
			if(vcnt == V-1) begin
				vcnt <= 10'd0;				
			end
			else 
				vcnt <= vcnt + 10'd1;				
		end
		else hcnt <= hcnt + 10'd1;

		if(BLANK) begin
			if(non_visible_area) pixel <= 0;   
			else pixel <= vdc_border_color; 
		end
		else begin

				

				  if(VDC_cnt == 7) begin sdram_rd <= 1; sdram_addr <= videoAddress;       end
			else if(VDC_cnt == 0) begin                                                  end
			else if(VDC_cnt == 1) begin                                                  end
			else if(VDC_cnt == 2) begin                                                  end
			else if(VDC_cnt == 3) begin sdram_rd <= 0;                                   end
			else if(VDC_cnt == 4) begin sdram_rd <= 1;                                   end
			else if(VDC_cnt == 5) begin                                                  end
			else if(VDC_cnt == 6) begin                                                  end
			





										

			if(CPU_cnt == 3) begin
				MREQ_old <= MREQ;
				if(MREQ_old == 0 && MREQ == 1) begin
					skip_beat <= 1;					
				end
				else skip_beat <= 0;
			end
			

			if(CPU_cnt == 0) begin			
				CPUENA <= !skip_beat;			
			end			
			else
				CPUENA <= 0;
			

			if(CPU_cnt == 1) begin
				sdram_rd <= 1; 
				sdram_addr <= cpuReadAddress;
				if(MREQ && WR && !skip_beat)	begin				
					if(mapped_io) begin											
						caps_lock_bit            <= DO[6];
						vdc_graphic_mode_enabled <= DO[3];
						CASOUT                   <= DO[2];					
						BUZZER                   <= DO[0];
					end
					else begin
						sdram_wr <= bank_is_ram;
						sdram_din <= DO;  						
					end		   
				end
			end


			if(CPU_cnt == 2) begin
				if(MREQ && !skip_beat) begin
					if(RD) begin					
						if(mapped_io) begin											
							DI[7] <= CASIN;					
							DI[6:0] <= KD;						      
						end				
						else 
							DI <= sdram_dout;
					end			
					if(WR)	begin

						sdram_wr <= 0;  
					end					
				end
			end
					

			if(CPU_cnt == 2 && IORQ && !skip_beat) begin
				if(RD) begin				
					if(A[7:0] == 'h2b) begin


						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_0[4];					
						DI[3] <= ~joystick_0[0];
						DI[2] <= ~joystick_0[1];
						DI[1] <= ~joystick_0[2];
						DI[0] <= ~joystick_0[3];
					end
					else if(A[7:0] == 'h27) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_0[5];					
						DI[3] <= 1;
						DI[2] <= 1;
						DI[1] <= 1;
						DI[0] <= 1;
					end
					else if(A[7:0] == 'h2e) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_1[4];					
						DI[3] <= ~joystick_1[0];
						DI[2] <= ~joystick_1[1];
						DI[1] <= ~joystick_1[2];
						DI[0] <= ~joystick_1[3];
					end
					else if(A[7:0] == 'h2d) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_1[5];					
						DI[3] <= 1;
						DI[2] <= 1;
						DI[1] <= 1;
						DI[0] <= 1;
					end

					else if(A[7:0] == 'ha0) DI <= hsw;						
					else if(A[7:0] == 'ha1) DI <= hbp;						
					else if(A[7:0] == 'ha2) DI <= hfp;						
					else
						DI <= { DI[7:1], 1'b1 };
						







				end
				if(WR) begin
					case(A[7:0])
						'h40: banks[0] <= DO[3:0];
						'h41: banks[1] <= DO[3:0];
						'h42: banks[2] <= DO[3:0];
						'h43: banks[3] <= DO[3:0];
						'h44:
							begin	
								vdc_page_7         <= ~DO[3];
								vdc_text80_enabled <= DO[0]; 
								vdc_border_color   <= DO[7:4];
								
								if(DO[2:1] == 'b00)  vdc_graphic_mode_number <= 5;              											
								if(DO[2:0] == 'b010) vdc_graphic_mode_number <= 4;
								if(DO[2:0] == 'b011) vdc_graphic_mode_number <= 3;
								if(DO[2:0] == 'b110) vdc_graphic_mode_number <= 2;
								if(DO[2:0] == 'b111) vdc_graphic_mode_number <= 1;
								if(DO[2:1] == 'b10)  vdc_graphic_mode_number <= 0;                  
							end
						'h45:
							begin
								vdc_text80_foreground <= DO[7:4];
								vdc_text80_background <= DO[3:0];         
							end
						'h0d: ;

						'h0e: ;

						'h10: ;
						'h11: ;
						'h12: ;
						'h13: ;
						'h14: ;
					   'ha0: hsw <= DO;						
					   'ha1: hbp <= DO;						
					   'ha2: hfp <= DO;						
						


					endcase				
				end
			end		
								

			if(non_visible_area) 
				pixel <= 0;
			else if( (vcnt < TOP_BORDER_WIDTH || vcnt >= TOP_BORDER_WIDTH + HEIGHT) || 
						(hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) 
				pixel <= vdc_border_color; 				
			else 
			begin
				if(vdc_graphic_mode_enabled == 1) begin
					if(vdc_graphic_mode_number == 5) begin

						pixel <= char[0] == 1 ? fg : bg;
						char <= char >> 1;         
					end 
					else if(vdc_graphic_mode_number == 4) begin

						if(xcnt[0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end               
					end 
					else if(vdc_graphic_mode_number == 3 || vdc_graphic_mode_number == 0) begin

						if(xcnt[1:0] == 0) begin
							pixel = char[3:0];
							char = char >> 4;
						end               
					end 
					else if(vdc_graphic_mode_number == 2) begin

						if(xcnt[0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end
					end 
					else if(vdc_graphic_mode_number == 1) begin

						if(xcnt[1:0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end
					end
				end	
				else if(vdc_text80_enabled) begin

					pixel <= char[0] == 1 ? fg : bg;
					char <= char >> 1;         
				end
				else begin

					if(xcnt[0] == 0) begin
						pixel <= char[0] == 1 ? fg : bg;
						char <= char >> 1;
					end
				end	
			end


			if(xcnt[2:0] == 1) begin
				ramData <= sdram_dout;			
				charsetAddress <= (sdram_dout << 3) | ycnt[2:0];
			end		
			

			if(vdc_graphic_mode_enabled) begin					
				if(vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 4 || vdc_graphic_mode_number == 3) begin

					ramAddress[13]  = ycnt[2];
					ramAddress[12]  = ycnt[1];
					ramAddress[11]  = ycnt[0];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[7];
					ramAddress[ 6]  = ycnt[6];
					ramAddress[ 5]  = ycnt[7];
					ramAddress[ 4]  = ycnt[6];
					ramAddress[3:0] = 0;
					
						  if(vdc_graphic_mode_number == 5) ramAddress = ramAddress + (xcnt1 >> 3);   
					else if(vdc_graphic_mode_number == 4) ramAddress = ramAddress + (xcnt2 >> 3);   
					else if(vdc_graphic_mode_number == 3) ramAddress = ramAddress + (xcnt1 >> 3);   

				end else if(vdc_graphic_mode_number == 2 || vdc_graphic_mode_number == 1) begin

					ramAddress[13]  = 1;
					ramAddress[12]  = ycnt[2];
					ramAddress[11]  = ycnt[1];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[0];
					ramAddress[ 6]  = ycnt[7];
					ramAddress[ 5]  = ycnt[6];
					ramAddress[ 4]  = ycnt[7];
					ramAddress[ 3]  = ycnt[6];
					ramAddress[2:0] = 0;
					
						  if(vdc_graphic_mode_number == 2) ramAddress = ramAddress + (xcnt1 >> 4);   
					else if(vdc_graphic_mode_number == 1) ramAddress = ramAddress + (xcnt3 >> 4);   

				end else if(vdc_graphic_mode_number == 0) begin

					ramAddress[13]  = 1;
					ramAddress[12]  = ycnt[2];
					ramAddress[11]  = ycnt[1];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[7];
					ramAddress[ 6]  = ycnt[6];
					ramAddress[ 5]  = ycnt[7];
					ramAddress[ 4]  = ycnt[6];
					ramAddress[3:0] = 0;
					
					ramAddress = ramAddress + (xcnt1 >> 3); 
				end
			end
			else begin

				ramAddress[13]  = 1;
				ramAddress[12]  = 1;
				ramAddress[11]  = 1;         
				ramAddress[10]  = ycnt[5];
				ramAddress[ 9]  = ycnt[4];
				ramAddress[ 8]  = ycnt[3];
				ramAddress[ 7]  = ycnt[7];
				ramAddress[ 6]  = ycnt[6];
				ramAddress[ 5]  = ycnt[7];
				ramAddress[ 4]  = ycnt[6];
				ramAddress[3:0] = 0;
				
					  if(vdc_text80_enabled) ramAddress = ramAddress + (xcnt1 >> 3);   
				else                        ramAddress = ramAddress + (xcnt2 >> 3);
			end			
				

			if(vdc_graphic_mode_enabled) begin

				if(vdc_graphic_mode_number == 5) begin
					if(xcnt[2:0] == 7) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 4) begin

					if(xcnt[3:0] == 7) begin
						ramDataD <= ramData;             
					end   
					else if(xcnt[3:0] == 15) begin
						char <= ramDataD;
						fgbg <= ramData;             
					end   
				end else if(vdc_graphic_mode_number == 3 || vdc_graphic_mode_number == 0) begin

					if(xcnt[2:0] == 7) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 2) begin
					if(xcnt[3:0] == 15) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 1) begin
					if(xcnt[4:0] == 15) begin
						ramDataD <= ramData;             
					end   
					else if(xcnt[4:0] == 31) begin
						char <= ramDataD;
						fgbg <= ramData;             
					end   
				end            
			end
			else if(vdc_text80_enabled) begin

				if(xcnt[2:0] == 7) begin
					char <= charsetQ;
				end   
			end
			else begin

				if(xcnt[3:0] == 7) begin
					ramDataD <= charsetQ;
				end   
				else if(xcnt[3:0] == 15) begin
					char <= ramDataD;
					fgbg <= ramData;          
				end   
			end   
		end
	end
end 


assign r = 
	pixel == 4'h0 ? { col0[11:8], 2'b00 } : 
	pixel == 4'h1 ? { col1[11:8], 2'b00 } : 
	pixel == 4'h2 ? { col2[11:8], 2'b00 } : 
	pixel == 4'h3 ? { col3[11:8], 2'b00 } : 
	pixel == 4'h4 ? { col4[11:8], 2'b00 } : 
	pixel == 4'h5 ? { col5[11:8], 2'b00 } : 
	pixel == 4'h6 ? { col6[11:8], 2'b00 } : 
	pixel == 4'h7 ? { col7[11:8], 2'b00 } : 
	pixel == 4'h8 ? { col8[11:8], 2'b00 } : 
	pixel == 4'h9 ? { col9[11:8], 2'b00 } : 
	pixel == 4'ha ? { cola[11:8], 2'b00 } : 
	pixel == 4'hb ? { colb[11:8], 2'b00 } : 
	pixel == 4'hc ? { colc[11:8], 2'b00 } : 
	pixel == 4'hd ? { cold[11:8], 2'b00 } : 
	pixel == 4'he ? { cole[11:8], 2'b00 } : 
                   { colf[11:8], 2'b00 } ;

assign g = 
	pixel == 4'h0 ? { col0[7:4], 2'b00 } : 
	pixel == 4'h1 ? { col1[7:4], 2'b00 } : 
	pixel == 4'h2 ? { col2[7:4], 2'b00 } : 
	pixel == 4'h3 ? { col3[7:4], 2'b00 } : 
	pixel == 4'h4 ? { col4[7:4], 2'b00 } : 
	pixel == 4'h5 ? { col5[7:4], 2'b00 } : 
	pixel == 4'h6 ? { col6[7:4], 2'b00 } : 
	pixel == 4'h7 ? { col7[7:4], 2'b00 } : 
	pixel == 4'h8 ? { col8[7:4], 2'b00 } : 
	pixel == 4'h9 ? { col9[7:4], 2'b00 } : 
	pixel == 4'ha ? { cola[7:4], 2'b00 } : 
	pixel == 4'hb ? { colb[7:4], 2'b00 } : 
	pixel == 4'hc ? { colc[7:4], 2'b00 } : 
	pixel == 4'hd ? { cold[7:4], 2'b00 } : 
	pixel == 4'he ? { cole[7:4], 2'b00 } : 
						 { colf[7:4], 2'b00 } ;
					 									 
assign b = 
	pixel == 4'h0 ? { col0[3:0], 2'b00 } : 
	pixel == 4'h1 ? { col1[3:0], 2'b00 } : 
	pixel == 4'h2 ? { col2[3:0], 2'b00 } : 
	pixel == 4'h3 ? { col3[3:0], 2'b00 } : 
	pixel == 4'h4 ? { col4[3:0], 2'b00 } : 
	pixel == 4'h5 ? { col5[3:0], 2'b00 } : 
	pixel == 4'h6 ? { col6[3:0], 2'b00 } : 
	pixel == 4'h7 ? { col7[3:0], 2'b00 } : 
	pixel == 4'h8 ? { col8[3:0], 2'b00 } : 
	pixel == 4'h9 ? { col9[3:0], 2'b00 } : 
	pixel == 4'ha ? { cola[3:0], 2'b00 } : 
	pixel == 4'hb ? { colb[3:0], 2'b00 } : 
	pixel == 4'hc ? { colc[3:0], 2'b00 } : 
	pixel == 4'hd ? { cold[3:0], 2'b00 } : 
	pixel == 4'he ? { cole[3:0], 2'b00 } : 
						 { colf[3:0], 2'b00 } ;




	reg   [3:0] banks[3:0];
	wire  [3:0] bank          = banks[bank_bits];
	wire  [1:0] bank_bits     = A[15:14];  
	wire [13:0] base_addr     = A[13:0];	
	wire        bank_is_ram   = bank >= 4 && bank <=7;
	wire        mapped_io     = bank == 2 && (base_addr >= 14'h2800 && base_addr <= 14'h2FFF);
	
	wire [24:0] videoAddress   = (vdc_page_7 == 1) ? { 7'd0, 4'h7, ramAddress } : { 7'd0, 4'h3, ramAddress };
	wire [24:0] cpuReadAddress = { 7'd0, bank, base_addr };		
		
endmodule
module VTL_chip 
(	
	input    F14M,
	input    RESET,
	input    BLANK,
		

   output           CPUCK,
	output reg       CPUENA,
	output           WAIT_n,
	input            MREQ_n,
	input            IORQ_n,
	input            RD_n,
	input            WR_n,
	input     [15:0] A,
	input      [7:0] DO,
	output reg [7:0] DI,
	

	input [ 6:0] KD,  
   input        CASIN,

   input [31:0] joystick_0,
	input [31:0] joystick_1,
	

	output reg [24:0] sdram_addr,
	input       [7:0] sdram_dout,
   output reg  [7:0] sdram_din,
	output reg        sdram_wr,
	output reg        sdram_rd,
	

	output hsync,
	output vsync,
	output [5:0] r,
	output [5:0] g,
	output [5:0] b,
	output display_enable,
	
	output reg BUZZER,
	output reg CASOUT,
	
	input  alt_font,
	output [2:0] cnt,
	
	input          img_mounted, 
   input   [31:0] img_size    
);


reg [7:0] hfp = 10;
reg [7:0] hsw = 66;
reg [7:0] hbp = 70;






parameter HEIGHT              = 192;
parameter TOP_BORDER_WIDTH    =  65;
parameter BOTTOM_BORDER_WIDTH =  55;
parameter V                   = 313;

parameter WIDTH               = 640;
parameter LEFT_BORDER_WIDTH   =  72;
parameter RIGHT_BORDER_WIDTH  =  86;
parameter H                   = 798;



reg[9:0]   hcnt;
reg[9:0]   vcnt;
wire[12:0] xcnt;
wire[12:0] xcnt1;
wire[12:0] xcnt2;
wire[12:0] xcnt3;
wire[9:0]  ycnt;

reg[7:0]  char;
reg[7:0]  fgbg;
reg[7:0]  ramData;
reg[7:0]  ramDataD;
reg[13:0] ramAddress;

reg[7:0]  ramQ;

reg [3:0] pixel;

reg [2:0] vdc_graphic_mode_number;
reg       vdc_text80_enabled     ;
reg [3:0] vdc_text80_foreground  ;
reg [3:0] vdc_text80_background  ;
reg [3:0] vdc_border_color       ;
reg       vdc_page_7             ;


reg caps_lock_bit           ;
reg vdc_graphic_mode_enabled;


parameter col0 = 12'h000;
parameter col1 = 12'h00f;
parameter col2 = 12'h080;
parameter col3 = 12'h08f;
parameter col4 = 12'ha00;
parameter col5 = 12'hf0f;
parameter col6 = 12'h780;
parameter col7 = 12'h999;
parameter col8 = 12'h555;
parameter col9 = 12'h88f;
parameter cola = 12'h0f0;
parameter colb = 12'h4ff;
parameter colc = 12'hf45;
parameter cold = 12'hf9f;
parameter cole = 12'hcf0;
parameter colf = 12'hfff;

reg[12:0] charsetAddress;

wire[7:0] charsetQ;
wire[7:0] charsetQ_alt;
wire[7:0] charsetQ_std; 

assign charsetQ = (!alt_font) ? charsetQ_std : charsetQ_alt;

rom_charset rom_charset (
	.address(charsetAddress),
	.clock(F14M),
	.q(charsetQ_std)
);							  						

rom_charset_alternate rom_charset_alternate (
	.address(charsetAddress),
	.clock(F14M),
	.q(charsetQ_alt)
);							  						

wire [3:0] fg;
wire [3:0] bg;


assign hsync = (hcnt < hsw) ? 0 : 1;
assign vsync = (vcnt <   2) ? 0 : 1;

assign display_enable = ~non_visible_area;

wire non_visible_area = hcnt < hsw+hbp || vcnt < 4 || vcnt > (312-2) || hcnt >= hsw+hbp+H;
						  

assign fg = (vdc_graphic_mode_enabled && (vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 2)) || (!vdc_graphic_mode_enabled && vdc_text80_enabled) ? vdc_text80_foreground : fgbg[7:4];
assign bg = (vdc_graphic_mode_enabled && (vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 2)) || (!vdc_graphic_mode_enabled && vdc_text80_enabled) ? vdc_text80_background : fgbg[3:0];


assign xcnt = hcnt - (hsw+hbp+LEFT_BORDER_WIDTH);

assign xcnt1 = xcnt + 8 +8;
assign xcnt2 = xcnt + 16+8;
assign xcnt3 = xcnt + 24+8;

assign ycnt = vcnt - TOP_BORDER_WIDTH;

wire [2:0] VDC_cnt = hcnt[2:0];
wire [1:0] CPU_cnt = hcnt[1:0];

assign cnt = VDC_cnt;

assign CPUCK  = VDC_cnt[1];



wire MREQ   = ~MREQ_n;
wire WR     = ~WR_n;
wire RD     = ~RD_n;
wire IORQ   = ~IORQ_n;



reg MREQ_old;
reg skip_beat;

always@(posedge F14M) begin
	if(RESET) begin
		hcnt <= 0;  
		vcnt <= 0;
		banks[0] <= 0;		
	end
	else begin		   
		

		if(hcnt == hsw+hbp+H+hfp-1) begin
			hcnt <= 10'd0;
			if(vcnt == V-1) begin
				vcnt <= 10'd0;				
			end
			else 
				vcnt <= vcnt + 10'd1;				
		end
		else hcnt <= hcnt + 10'd1;

		if(BLANK) begin
			if(non_visible_area) pixel <= 0;   
			else pixel <= vdc_border_color; 
		end
		else begin

				

				  if(VDC_cnt == 7) begin sdram_rd <= 1; sdram_addr <= videoAddress;       end
			else if(VDC_cnt == 0) begin                                                  end
			else if(VDC_cnt == 1) begin                                                  end
			else if(VDC_cnt == 2) begin                                                  end
			else if(VDC_cnt == 3) begin sdram_rd <= 0;                                   end
			else if(VDC_cnt == 4) begin sdram_rd <= 1;                                   end
			else if(VDC_cnt == 5) begin                                                  end
			else if(VDC_cnt == 6) begin                                                  end
			





										

			if(CPU_cnt == 3) begin
				MREQ_old <= MREQ;
				if(MREQ_old == 0 && MREQ == 1) begin
					skip_beat <= 1;					
				end
				else skip_beat <= 0;
			end
			

			if(CPU_cnt == 0) begin			
				CPUENA <= !skip_beat;			
			end			
			else
				CPUENA <= 0;
			

			if(CPU_cnt == 1) begin
				sdram_rd <= 1; 
				sdram_addr <= cpuReadAddress;
				if(MREQ && WR && !skip_beat)	begin				
					if(mapped_io) begin											
						caps_lock_bit            <= DO[6];
						vdc_graphic_mode_enabled <= DO[3];
						CASOUT                   <= DO[2];					
						BUZZER                   <= DO[0];
					end
					else begin
						sdram_wr <= bank_is_ram;
						sdram_din <= DO;  						
					end		   
				end
			end


			if(CPU_cnt == 2) begin
				if(MREQ && !skip_beat) begin
					if(RD) begin					
						if(mapped_io) begin											
							DI[7] <= CASIN;					
							DI[6:0] <= KD;						      
						end				
						else 
							DI <= sdram_dout;
					end			
					if(WR)	begin

						sdram_wr <= 0;  
					end					
				end
			end
					

			if(CPU_cnt == 2 && IORQ && !skip_beat) begin
				if(RD) begin				
					if(A[7:0] == 'h2b) begin


						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_0[4];					
						DI[3] <= ~joystick_0[0];
						DI[2] <= ~joystick_0[1];
						DI[1] <= ~joystick_0[2];
						DI[0] <= ~joystick_0[3];
					end
					else if(A[7:0] == 'h27) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_0[5];					
						DI[3] <= 1;
						DI[2] <= 1;
						DI[1] <= 1;
						DI[0] <= 1;
					end
					else if(A[7:0] == 'h2e) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_1[4];					
						DI[3] <= ~joystick_1[0];
						DI[2] <= ~joystick_1[1];
						DI[1] <= ~joystick_1[2];
						DI[0] <= ~joystick_1[3];
					end
					else if(A[7:0] == 'h2d) begin

						DI[7] <= 1;					
						DI[6] <= 1;					
						DI[5] <= 1;					
						DI[4] <= ~joystick_1[5];					
						DI[3] <= 1;
						DI[2] <= 1;
						DI[1] <= 1;
						DI[0] <= 1;
					end

					else if(A[7:0] == 'ha0) DI <= hsw;						
					else if(A[7:0] == 'ha1) DI <= hbp;						
					else if(A[7:0] == 'ha2) DI <= hfp;						
					else
						DI <= { DI[7:1], 1'b1 };
						







				end
				if(WR) begin
					case(A[7:0])
						'h40: banks[0] <= DO[3:0];
						'h41: banks[1] <= DO[3:0];
						'h42: banks[2] <= DO[3:0];
						'h43: banks[3] <= DO[3:0];
						'h44:
							begin	
								vdc_page_7         <= ~DO[3];
								vdc_text80_enabled <= DO[0]; 
								vdc_border_color   <= DO[7:4];
								
								if(DO[2:1] == 'b00)  vdc_graphic_mode_number <= 5;              											
								if(DO[2:0] == 'b010) vdc_graphic_mode_number <= 4;
								if(DO[2:0] == 'b011) vdc_graphic_mode_number <= 3;
								if(DO[2:0] == 'b110) vdc_graphic_mode_number <= 2;
								if(DO[2:0] == 'b111) vdc_graphic_mode_number <= 1;
								if(DO[2:1] == 'b10)  vdc_graphic_mode_number <= 0;                  
							end
						'h45:
							begin
								vdc_text80_foreground <= DO[7:4];
								vdc_text80_background <= DO[3:0];         
							end
						'h0d: ;

						'h0e: ;

						'h10: ;
						'h11: ;
						'h12: ;
						'h13: ;
						'h14: ;
					   'ha0: hsw <= DO;						
					   'ha1: hbp <= DO;						
					   'ha2: hfp <= DO;						
						


					endcase				
				end
			end		
								

			if(non_visible_area) 
				pixel <= 0;
			else if( (vcnt < TOP_BORDER_WIDTH || vcnt >= TOP_BORDER_WIDTH + HEIGHT) || 
						(hcnt < hsw+hbp + LEFT_BORDER_WIDTH || hcnt >= hsw+hbp + LEFT_BORDER_WIDTH + WIDTH)) 
				pixel <= vdc_border_color; 				
			else 
			begin
				if(vdc_graphic_mode_enabled == 1) begin
					if(vdc_graphic_mode_number == 5) begin

						pixel <= char[0] == 1 ? fg : bg;
						char <= char >> 1;         
					end 
					else if(vdc_graphic_mode_number == 4) begin

						if(xcnt[0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end               
					end 
					else if(vdc_graphic_mode_number == 3 || vdc_graphic_mode_number == 0) begin

						if(xcnt[1:0] == 0) begin
							pixel = char[3:0];
							char = char >> 4;
						end               
					end 
					else if(vdc_graphic_mode_number == 2) begin

						if(xcnt[0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end
					end 
					else if(vdc_graphic_mode_number == 1) begin

						if(xcnt[1:0] == 0) begin
							pixel <= char[0] == 1 ? fg : bg;
							char <= char >> 1;
						end
					end
				end	
				else if(vdc_text80_enabled) begin

					pixel <= char[0] == 1 ? fg : bg;
					char <= char >> 1;         
				end
				else begin

					if(xcnt[0] == 0) begin
						pixel <= char[0] == 1 ? fg : bg;
						char <= char >> 1;
					end
				end	
			end


			if(xcnt[2:0] == 1) begin
				ramData <= sdram_dout;			
				charsetAddress <= (sdram_dout << 3) | ycnt[2:0];
			end		
			

			if(vdc_graphic_mode_enabled) begin					
				if(vdc_graphic_mode_number == 5 || vdc_graphic_mode_number == 4 || vdc_graphic_mode_number == 3) begin

					ramAddress[13]  = ycnt[2];
					ramAddress[12]  = ycnt[1];
					ramAddress[11]  = ycnt[0];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[7];
					ramAddress[ 6]  = ycnt[6];
					ramAddress[ 5]  = ycnt[7];
					ramAddress[ 4]  = ycnt[6];
					ramAddress[3:0] = 0;
					
						  if(vdc_graphic_mode_number == 5) ramAddress = ramAddress + (xcnt1 >> 3);   
					else if(vdc_graphic_mode_number == 4) ramAddress = ramAddress + (xcnt2 >> 3);   
					else if(vdc_graphic_mode_number == 3) ramAddress = ramAddress + (xcnt1 >> 3);   

				end else if(vdc_graphic_mode_number == 2 || vdc_graphic_mode_number == 1) begin

					ramAddress[13]  = 1;
					ramAddress[12]  = ycnt[2];
					ramAddress[11]  = ycnt[1];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[0];
					ramAddress[ 6]  = ycnt[7];
					ramAddress[ 5]  = ycnt[6];
					ramAddress[ 4]  = ycnt[7];
					ramAddress[ 3]  = ycnt[6];
					ramAddress[2:0] = 0;
					
						  if(vdc_graphic_mode_number == 2) ramAddress = ramAddress + (xcnt1 >> 4);   
					else if(vdc_graphic_mode_number == 1) ramAddress = ramAddress + (xcnt3 >> 4);   

				end else if(vdc_graphic_mode_number == 0) begin

					ramAddress[13]  = 1;
					ramAddress[12]  = ycnt[2];
					ramAddress[11]  = ycnt[1];
					ramAddress[10]  = ycnt[5];
					ramAddress[ 9]  = ycnt[4];
					ramAddress[ 8]  = ycnt[3];
					ramAddress[ 7]  = ycnt[7];
					ramAddress[ 6]  = ycnt[6];
					ramAddress[ 5]  = ycnt[7];
					ramAddress[ 4]  = ycnt[6];
					ramAddress[3:0] = 0;
					
					ramAddress = ramAddress + (xcnt1 >> 3); 
				end
			end
			else begin

				ramAddress[13]  = 1;
				ramAddress[12]  = 1;
				ramAddress[11]  = 1;         
				ramAddress[10]  = ycnt[5];
				ramAddress[ 9]  = ycnt[4];
				ramAddress[ 8]  = ycnt[3];
				ramAddress[ 7]  = ycnt[7];
				ramAddress[ 6]  = ycnt[6];
				ramAddress[ 5]  = ycnt[7];
				ramAddress[ 4]  = ycnt[6];
				ramAddress[3:0] = 0;
				
					  if(vdc_text80_enabled) ramAddress = ramAddress + (xcnt1 >> 3);   
				else                        ramAddress = ramAddress + (xcnt2 >> 3);
			end			
				

			if(vdc_graphic_mode_enabled) begin

				if(vdc_graphic_mode_number == 5) begin
					if(xcnt[2:0] == 7) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 4) begin

					if(xcnt[3:0] == 7) begin
						ramDataD <= ramData;             
					end   
					else if(xcnt[3:0] == 15) begin
						char <= ramDataD;
						fgbg <= ramData;             
					end   
				end else if(vdc_graphic_mode_number == 3 || vdc_graphic_mode_number == 0) begin

					if(xcnt[2:0] == 7) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 2) begin
					if(xcnt[3:0] == 15) begin
						char <= ramData;             
					end
				end else if(vdc_graphic_mode_number == 1) begin
					if(xcnt[4:0] == 15) begin
						ramDataD <= ramData;             
					end   
					else if(xcnt[4:0] == 31) begin
						char <= ramDataD;
						fgbg <= ramData;             
					end   
				end            
			end
			else if(vdc_text80_enabled) begin

				if(xcnt[2:0] == 7) begin
					char <= charsetQ;
				end   
			end
			else begin

				if(xcnt[3:0] == 7) begin
					ramDataD <= charsetQ;
				end   
				else if(xcnt[3:0] == 15) begin
					char <= ramDataD;
					fgbg <= ramData;          
				end   
			end   
		end
	end
end 


assign r = 
	pixel == 4'h0 ? { col0[11:8], 2'b00 } : 
	pixel == 4'h1 ? { col1[11:8], 2'b00 } : 
	pixel == 4'h2 ? { col2[11:8], 2'b00 } : 
	pixel == 4'h3 ? { col3[11:8], 2'b00 } : 
	pixel == 4'h4 ? { col4[11:8], 2'b00 } : 
	pixel == 4'h5 ? { col5[11:8], 2'b00 } : 
	pixel == 4'h6 ? { col6[11:8], 2'b00 } : 
	pixel == 4'h7 ? { col7[11:8], 2'b00 } : 
	pixel == 4'h8 ? { col8[11:8], 2'b00 } : 
	pixel == 4'h9 ? { col9[11:8], 2'b00 } : 
	pixel == 4'ha ? { cola[11:8], 2'b00 } : 
	pixel == 4'hb ? { colb[11:8], 2'b00 } : 
	pixel == 4'hc ? { colc[11:8], 2'b00 } : 
	pixel == 4'hd ? { cold[11:8], 2'b00 } : 
	pixel == 4'he ? { cole[11:8], 2'b00 } : 
                   { colf[11:8], 2'b00 } ;

assign g = 
	pixel == 4'h0 ? { col0[7:4], 2'b00 } : 
	pixel == 4'h1 ? { col1[7:4], 2'b00 } : 
	pixel == 4'h2 ? { col2[7:4], 2'b00 } : 
	pixel == 4'h3 ? { col3[7:4], 2'b00 } : 
	pixel == 4'h4 ? { col4[7:4], 2'b00 } : 
	pixel == 4'h5 ? { col5[7:4], 2'b00 } : 
	pixel == 4'h6 ? { col6[7:4], 2'b00 } : 
	pixel == 4'h7 ? { col7[7:4], 2'b00 } : 
	pixel == 4'h8 ? { col8[7:4], 2'b00 } : 
	pixel == 4'h9 ? { col9[7:4], 2'b00 } : 
	pixel == 4'ha ? { cola[7:4], 2'b00 } : 
	pixel == 4'hb ? { colb[7:4], 2'b00 } : 
	pixel == 4'hc ? { colc[7:4], 2'b00 } : 
	pixel == 4'hd ? { cold[7:4], 2'b00 } : 
	pixel == 4'he ? { cole[7:4], 2'b00 } : 
						 { colf[7:4], 2'b00 } ;
					 									 
assign b = 
	pixel == 4'h0 ? { col0[3:0], 2'b00 } : 
	pixel == 4'h1 ? { col1[3:0], 2'b00 } : 
	pixel == 4'h2 ? { col2[3:0], 2'b00 } : 
	pixel == 4'h3 ? { col3[3:0], 2'b00 } : 
	pixel == 4'h4 ? { col4[3:0], 2'b00 } : 
	pixel == 4'h5 ? { col5[3:0], 2'b00 } : 
	pixel == 4'h6 ? { col6[3:0], 2'b00 } : 
	pixel == 4'h7 ? { col7[3:0], 2'b00 } : 
	pixel == 4'h8 ? { col8[3:0], 2'b00 } : 
	pixel == 4'h9 ? { col9[3:0], 2'b00 } : 
	pixel == 4'ha ? { cola[3:0], 2'b00 } : 
	pixel == 4'hb ? { colb[3:0], 2'b00 } : 
	pixel == 4'hc ? { colc[3:0], 2'b00 } : 
	pixel == 4'hd ? { cold[3:0], 2'b00 } : 
	pixel == 4'he ? { cole[3:0], 2'b00 } : 
						 { colf[3:0], 2'b00 } ;




	reg   [3:0] banks[3:0];
	wire  [3:0] bank          = banks[bank_bits];
	wire  [1:0] bank_bits     = A[15:14];  
	wire [13:0] base_addr     = A[13:0];	
	wire        bank_is_ram   = bank >= 4 && bank <=7;
	wire        mapped_io     = bank == 2 && (base_addr >= 14'h2800 && base_addr <= 14'h2FFF);
	
	wire [24:0] videoAddress   = (vdc_page_7 == 1) ? { 7'd0, 4'h7, ramAddress } : { 7'd0, 4'h3, ramAddress };
	wire [24:0] cpuReadAddress = { 7'd0, bank, base_addr };		
		
endmodule