data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/double_arm_asyn.v
1: b'%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/double_arm_asyn.v:33: Bit extraction of array[79:0] requires 7 bit index, not 16 bits.\n                                                                                                     : ... In instance double_ram_asyn\n            mem[addr_a] <= din_a;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/double_arm_asyn.v:36: Bit extraction of array[79:0] requires 7 bit index, not 16 bits.\n                                                                                                     : ... In instance double_ram_asyn\n            mem[addr_b] <= din_b;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/double_arm_asyn.v:48: Bit extraction of array[79:0] requires 7 bit index, not 16 bits.\n                                                                                                     : ... In instance double_ram_asyn\n            dout_a <= mem[addr_a];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/double_arm_asyn.v:51: Bit extraction of array[79:0] requires 7 bit index, not 16 bits.\n                                                                                                     : ... In instance double_ram_asyn\n            dout_b <= mem[addr_b];\n                         ^\n%Error: Exiting due to 4 warning(s)\n'
module double_ram_asyn(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b
);

 
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = DATA_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din_a;
input [ADDR_WIDTH-1:0] addr_a;
input we_a, oe_a;
output reg [DATA_WIDTH-1:0] dout_a;


input [DATA_WIDTH-1:0] din_b;
input [ADDR_WIDTH-1:0] addr_b;
input we_b, oe_b;
output reg [DATA_WIDTH-1:0] dout_b;

integer i;

reg [DATA_WIDTH-1:0] mem[RAM_DEPTH-1:0]; 




always@(posedge clk or negedge rst) begin
    if(!rst) begin
        if(we_a) begin
            mem[addr_a] <= din_a;
        end
        if(we_b) begin
            mem[addr_b] <= din_b;
        end
    end
    else begin
        for(i = 0; i < RAM_DEPTH; i = i + 1)
            mem[i] <= 0;
    end 
    end
    

    always@(addr_a or addr_b or oe_a or oe_b) begin
        if(oe_a) begin
            dout_a <= mem[addr_a];
        end
        if(oe_b) begin
            dout_b <= mem[addr_b];
        end
    end


endmodule
module double_ram_asyn(
    clk, rst, cs,
    din_a, addr_a, dout_a, we_a, oe_a,
    din_b, addr_b, dout_b, we_b, oe_b
);


 
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = DATA_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din_a;
input [ADDR_WIDTH-1:0] addr_a;
input we_a, oe_a;
output reg [DATA_WIDTH-1:0] dout_a;


input [DATA_WIDTH-1:0] din_b;
input [ADDR_WIDTH-1:0] addr_b;
input we_b, oe_b;
output reg [DATA_WIDTH-1:0] dout_b;

integer i;

reg [DATA_WIDTH-1:0] mem[RAM_DEPTH-1:0]; 




always@(posedge clk or negedge rst) begin
    if(!rst) begin
        if(we_a) begin
            mem[addr_a] <= din_a;
        end
        if(we_b) begin
            mem[addr_b] <= din_b;
        end
    end
    else begin
        for(i = 0; i < RAM_DEPTH; i = i + 1)
            mem[i] <= 0;
    end 
    end
    

    always@(addr_a or addr_b or oe_a or oe_b) begin
        if(oe_a) begin
            dout_a <= mem[addr_a];
        end
        if(oe_b) begin
            dout_b <= mem[addr_b];
        end
    end


endmodule