data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v
1: b'%Error: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:20: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n    file_id = $fopen("F:/vivado_proj/FlowReshaper/srcs_rgb/test_output.txt");\n              ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:22: Unsupported: Ignoring delay on this delayed statement.\n    # 33 rstn = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:23: Unsupported: Ignoring delay on this delayed statement.\n    # 70 rstn = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:24: Unsupported: Ignoring delay on this delayed statement.\n    # 10 ena = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:25: Unsupported: Ignoring delay on this delayed statement.\n    # 30 ena = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #2000000 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/421488999/srcs_rgb/test_FlowReshaper.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk = ~clk;\n       ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_FlowReshaper();
reg ena,clk,rstn;
wire rd_en;
wire [19:0] ram_addr;
reg [15:0] ram_dout;
wire [7:0] wr_data;
integer file_id; 
reg wr_en_1;

(* ramstyle = "AUTO" *) reg [15:0] data_ram [0:76799]; 
always@(posedge clk or negedge rstn) begin
    if(~rstn) ram_dout <= 0;
    else ram_dout <= data_ram[ram_addr];
end

initial begin
    $readmemh("F:/vivado_proj/FlowReshaper/srcs_rgb/test.txt",data_ram);
    file_id = $fopen("F:/vivado_proj/FlowReshaper/srcs_rgb/test_output.txt");
    ena = 0;clk = 0;rstn = 1;
    # 33 rstn = 0;
    # 70 rstn = 1;
    # 10 ena = 1;
    # 30 ena = 0;
    #2000000 
    $fclose(file_id);
    $stop;
end

always #2.5 clk = ~clk;

always@(posedge clk)
begin
    wr_en_1 <= wr_en;
    if(wr_en_1)
        $fwrite(file_id, "%h\n", wr_data);
end

FlowReshaper reshaper(
    .clk                       (clk),
    .rstn                      (rstn),
    .rd_en                     (rd_en),
    .rd_addr                   (ram_addr),
    .rd_data                   (ram_dout),
    .wr_en                     (wr_en),
    .wr_addr                   (),
    .wr_data                   (wr_data),
    .ena                       (ena)
);


endmodule
module test_FlowReshaper();

reg ena,clk,rstn;
wire rd_en;
wire [19:0] ram_addr;
reg [15:0] ram_dout;
wire [7:0] wr_data;
integer file_id; 
reg wr_en_1;

(* ramstyle = "AUTO" *) reg [15:0] data_ram [0:76799]; 
always@(posedge clk or negedge rstn) begin
    if(~rstn) ram_dout <= 0;
    else ram_dout <= data_ram[ram_addr];
end

initial begin
    $readmemh("F:/vivado_proj/FlowReshaper/srcs_rgb/test.txt",data_ram);
    file_id = $fopen("F:/vivado_proj/FlowReshaper/srcs_rgb/test_output.txt");
    ena = 0;clk = 0;rstn = 1;
    # 33 rstn = 0;
    # 70 rstn = 1;
    # 10 ena = 1;
    # 30 ena = 0;
    #2000000 
    $fclose(file_id);
    $stop;
end

always #2.5 clk = ~clk;

always@(posedge clk)
begin
    wr_en_1 <= wr_en;
    if(wr_en_1)
        $fwrite(file_id, "%h\n", wr_data);
end

FlowReshaper reshaper(
    .clk                       (clk),
    .rstn                      (rstn),
    .rd_en                     (rd_en),
    .rd_addr                   (ram_addr),
    .rd_data                   (ram_dout),
    .wr_en                     (wr_en),
    .wr_addr                   (),
    .wr_data                   (wr_data),
    .ena                       (ena)
);


endmodule