data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n   forever #5 clk= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:76: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Error: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:38: Cannot find file containing module: \'Single_Port_RAM_64x8bit\'\n Single_Port_RAM_64x8bit uut (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507889320,data/full_repos/permissive/507889320/Single_Port_RAM_64x8bit\n             data/full_repos/permissive/507889320,data/full_repos/permissive/507889320/Single_Port_RAM_64x8bit.v\n             data/full_repos/permissive/507889320,data/full_repos/permissive/507889320/Single_Port_RAM_64x8bit.sv\n             Single_Port_RAM_64x8bit\n             Single_Port_RAM_64x8bit.v\n             Single_Port_RAM_64x8bit.sv\n             obj_dir/Single_Port_RAM_64x8bit\n             obj_dir/Single_Port_RAM_64x8bit.v\n             obj_dir/Single_Port_RAM_64x8bit.sv\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:56: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:61: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:65: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h4\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d4;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:68: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:72: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h4\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d4;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/507889320/Single_port_RAM64x8bit_test.v:75: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                     : ... In instance Single_port_RAM64x8bit_test\n   addr = 5\'d0;\n        ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Single_port_RAM64x8bit_test;


	reg [7:0] data;
	reg [5:0] addr;
	reg we;
	reg clk;


	wire [7:0] q;


	Single_Port_RAM_64x8bit uut (
		.data(data), 
		.addr(addr), 
		.we(we), 
		.clk(clk), 
		.q(q)
	);

	initial 
		begin
			clk = 1'b1;
			forever #5 clk= ~clk;
		end
	
	initial 
		begin

			data = 8'h01;
			addr = 5'd0;
			we = 1'b1;
			#10;
			
			data = 8'h02;
			addr = 5'd1;
			#10;
			
			data = 8'h03;
			addr = 5'd4;
			#10;
			
			addr = 5'd1;
			we = 1'b0;
			#10;
			
			addr = 5'd4;
			#10;

			addr = 5'd0;
			#10;

	end
      
endmodule
module Single_port_RAM64x8bit_test;



	reg [7:0] data;
	reg [5:0] addr;
	reg we;
	reg clk;


	wire [7:0] q;


	Single_Port_RAM_64x8bit uut (
		.data(data), 
		.addr(addr), 
		.we(we), 
		.clk(clk), 
		.q(q)
	);

	initial 
		begin
			clk = 1'b1;
			forever #5 clk= ~clk;
		end
	
	initial 
		begin

			data = 8'h01;
			addr = 5'd0;
			we = 1'b1;
			#10;
			
			data = 8'h02;
			addr = 5'd1;
			#10;
			
			data = 8'h03;
			addr = 5'd4;
			#10;
			
			addr = 5'd1;
			we = 1'b0;
			#10;
			
			addr = 5'd4;
			#10;

			addr = 5'd0;
			#10;

	end
      
endmodule