data/full_repos/permissive/423547971/FPGA Projects/How to Control PMOD KYPD Basys 3/top.v
1: b'%Error: Cannot find file containing module: Projects/How\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/How\n             data/full_repos/permissive/423547971/FPGA/Projects/How.v\n             data/full_repos/permissive/423547971/FPGA/Projects/How.sv\n             Projects/How\n             Projects/How.v\n             Projects/How.sv\n             obj_dir/Projects/How\n             obj_dir/Projects/How.v\n             obj_dir/Projects/How.sv\n%Error: Cannot find file containing module: to\n%Error: Cannot find file containing module: Control\n%Error: Cannot find file containing module: PMOD\n%Error: Cannot find file containing module: KYPD\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: 3/top.v\n%Error: Exiting due to 9 error(s)\n'
module top(
    input clk_100MHz,
    input [3:0] rows,
    output [3:0] cols,
    output [3:0] an,
    output [6:0] seg
    );

	wire [3:0] w_dec;

	decoder d(.clk_100MHz(clk_100MHz), .row(rows),
			.col(cols), .dec_out(w_dec));

	seg7_control s(.dec(w_dec), .an(an), .seg(seg));

endmodule
module top(
    input clk_100MHz,
    input [3:0] rows,
    output [3:0] cols,
    output [3:0] an,
    output [6:0] seg
    );


	wire [3:0] w_dec;

	decoder d(.clk_100MHz(clk_100MHz), .row(rows),
			.col(cols), .dec_out(w_dec));

	seg7_control s(.dec(w_dec), .an(an), .seg(seg));

endmodule