data/full_repos/permissive/436122533/Lab-1/HalfAdder.v
data/verilator_xmls/79c13bc6-728d-46db-9bf3-61ac5a9d85e5.xml
module HalfAdder(a,b,sum,cy);
input a,b;
output sum,cy;

xor xor1(sum,a,b);
and and1(cy,a,b);

endmodule
module HalfAdder(a,b,sum,cy);

input a,b;
output sum,cy;

xor xor1(sum,a,b);
and and1(cy,a,b);

endmodule