data/full_repos/permissive/420819839/Vectors/Vector3.v
data/verilator_xmls/381dfdb3-38c2-4532-b1e4-6eedb78d825b.xml
module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );

  assign {w,x,y,z} = { a, b, c, d, e, f,2'b11};

endmodule
module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );


  assign {w,x,y,z} = { a, b, c, d, e, f,2'b11};

endmodule