data/full_repos/permissive/497530416/sequential/pc_update.v
data/verilator_xmls/6f700df3-0659-4e5b-9da5-2cc9174f5ce4.xml
module pc_update(clk, icode, cnd, valC, valM, valP, PC_new);

input cnd;
input clk;
input [3:0] icode;
input [63:0] valC, valM, valP;

output reg [63:0] PC_new;

always@(*)
    begin
        case(icode)

        4'b0111:
        begin
            if(cnd)
                PC_new = valC;
            else
                PC_new = valP;
        end


        4'b1000:begin PC_new = valC; end
        

        4'b1001: begin PC_new = valM; end


        default: begin PC_new = valP; end
        endcase
    end

endmodule
module pc_update(clk, icode, cnd, valC, valM, valP, PC_new);


input cnd;
input clk;
input [3:0] icode;
input [63:0] valC, valM, valP;

output reg [63:0] PC_new;

always@(*)
    begin
        case(icode)

        4'b0111:
        begin
            if(cnd)
                PC_new = valC;
            else
                PC_new = valP;
        end


        4'b1000:begin PC_new = valC; end
        

        4'b1001: begin PC_new = valM; end


        default: begin PC_new = valP; end
        endcase
    end

endmodule