data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:10: Unsupported or unknown PLI call: $monitor\n  $monitor ("%g\\t %b      %b    %b",$time,enable,data,out);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 data = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 data = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 data = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 data = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/conditional_operator.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module conditional_operator();

wire out;
reg enable,data;

assign out = (enable) ? data : 1'bz;

initial begin
  $display ("time\t enable data out");
  $monitor ("%g\t %b      %b    %b",$time,enable,data,out);
  enable = 0;
  data = 0;
  #1 data = 1;
  #1 data = 0;
  #1 enable = 1;
  #1 data = 1;
  #1 data = 0;
  #1 enable = 0;
  #10 $finish;
end	

endmodule
module conditional_operator();


wire out;
reg enable,data;

assign out = (enable) ? data : 1'bz;

initial begin
  $display ("time\t enable data out");
  $monitor ("%g\t %b      %b    %b",$time,enable,data,out);
  enable = 0;
  data = 0;
  #1 data = 1;
  #1 data = 0;
  #1 enable = 1;
  #1 data = 1;
  #1 data = 0;
  #1 enable = 0;
  #10 $finish;
end	

endmodule