data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/to_send/tb_poly_mul256_andrea.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/to_send/tb_poly_mul256_andrea.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/to_send/tb_poly_mul256_andrea.v:77: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/to_send/tb_poly_mul256_andrea.v:83: syntax error, unexpected wait\n  wait(pol_mul_done);\n  ^~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_poly_mul256_andrea;


	reg clk;
	reg rst;
	reg acc_clear;
	reg pol_load_coeff4x;
	wire [63:0] pol_64bit_in;
	wire [63:0] s_vec_64;
	reg read;
	
	reg [8:0] i;
	reg [3327:0] pol_value; 


	wire [6:0] bram_address_relative;
	wire [7:0] s_address;
	wire [63:0] coeff4x_out;
	wire [63:0] polmul_result64_out;
	wire pol_mul_done;


	poly_mul256_parallel_in uut (
		.clk(clk), 
		.rst(rst), 
		.acc_clear(acc_clear), 
		.pol_load_coeff4x(pol_load_coeff4x), 
		.bram_address_relative(bram_address_relative), 
		.pol_64bit_in(pol_64bit_in), 
		.s_address(s_address), 
		.s_vec_64(s_vec_64),
		.read(read), 
		.coeff4x_out(coeff4x_out),
		.pol_mul_done(pol_mul_done)
	);

    s_rom rom(.clk(clk), .s_address(s_address), .s_vec_64(s_vec_64));
    pol_rom pr(.clk(clk), .bram_address_relative(bram_address_relative), .pol_64bit_in(pol_64bit_in));

	initial begin

		clk = 0;
		rst = 1;
		acc_clear = 1;
		pol_load_coeff4x = 0;
		read = 0;


		#100;
        


		@(posedge clk)
			begin
				acc_clear = 0;
				rst = 0;
			end
			
		wait(pol_mul_done);
		
		@(posedge clk)
			begin
				read = 1;
			end
			
			
			

	end
    
	always #5 clk = ~clk;
	
	

	   

        
        
endmodule
module tb_poly_mul256_andrea;



	reg clk;
	reg rst;
	reg acc_clear;
	reg pol_load_coeff4x;
	wire [63:0] pol_64bit_in;
	wire [63:0] s_vec_64;
	reg read;
	
	reg [8:0] i;
	reg [3327:0] pol_value; 


	wire [6:0] bram_address_relative;
	wire [7:0] s_address;
	wire [63:0] coeff4x_out;
	wire [63:0] polmul_result64_out;
	wire pol_mul_done;


	poly_mul256_parallel_in uut (
		.clk(clk), 
		.rst(rst), 
		.acc_clear(acc_clear), 
		.pol_load_coeff4x(pol_load_coeff4x), 
		.bram_address_relative(bram_address_relative), 
		.pol_64bit_in(pol_64bit_in), 
		.s_address(s_address), 
		.s_vec_64(s_vec_64),
		.read(read), 
		.coeff4x_out(coeff4x_out),
		.pol_mul_done(pol_mul_done)
	);

    s_rom rom(.clk(clk), .s_address(s_address), .s_vec_64(s_vec_64));
    pol_rom pr(.clk(clk), .bram_address_relative(bram_address_relative), .pol_64bit_in(pol_64bit_in));

	initial begin

		clk = 0;
		rst = 1;
		acc_clear = 1;
		pol_load_coeff4x = 0;
		read = 0;


		#100;
        


		@(posedge clk)
			begin
				acc_clear = 0;
				rst = 0;
			end
			
		wait(pol_mul_done);
		
		@(posedge clk)
			begin
				read = 1;
			end
			
			
			

	end
    
	always #5 clk = ~clk;
	
	

	   

        
        
endmodule