data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d0; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d2; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d3; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:20: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d4; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:21: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d5; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:22: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d6; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:23: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=1; Address=16\'d7; \n^\n%Error: data/full_repos/permissive/449807379/CPU_design/test_RAM_read.v:29: Unsupported or unknown PLI call: $monitor\n$monitor($time, "data at address %d is %h", Address, D_Out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_memory_read; 
    reg  enable,ReadWrite;
    reg [31:0] D_In;
    reg [15:0] Address;
    wire [31:0] D_Out;

RAM test_ram(enable,ReadWrite,Address,D_In,D_Out); 

initial  
begin

 $readmemh("RAM Write.txt", test_ram.RAM);

   enable =0;   ReadWrite=1;	Address=16'd0;	
#5 enable =1;   ReadWrite=1;	Address=16'd0;	
#5 enable =1;   ReadWrite=1;	Address=16'd1;	
#5 enable =1;   ReadWrite=1;	Address=16'd2;	
#5 enable =1;   ReadWrite=1;	Address=16'd3;	
#5 enable =1;   ReadWrite=1;	Address=16'd4;	
#5 enable =1;   ReadWrite=1;	Address=16'd5;	
#5 enable =1;   ReadWrite=1;	Address=16'd6;	
#5 enable =1;   ReadWrite=1;	Address=16'd7;	

end

initial
begin
$monitor($time, "data at address %d is %h", Address, D_Out);
end

endmodule
module test_memory_read;
 
    reg  enable,ReadWrite;
    reg [31:0] D_In;
    reg [15:0] Address;
    wire [31:0] D_Out;

RAM test_ram(enable,ReadWrite,Address,D_In,D_Out); 

initial  
begin

 $readmemh("RAM Write.txt", test_ram.RAM);

   enable =0;   ReadWrite=1;	Address=16'd0;	
#5 enable =1;   ReadWrite=1;	Address=16'd0;	
#5 enable =1;   ReadWrite=1;	Address=16'd1;	
#5 enable =1;   ReadWrite=1;	Address=16'd2;	
#5 enable =1;   ReadWrite=1;	Address=16'd3;	
#5 enable =1;   ReadWrite=1;	Address=16'd4;	
#5 enable =1;   ReadWrite=1;	Address=16'd5;	
#5 enable =1;   ReadWrite=1;	Address=16'd6;	
#5 enable =1;   ReadWrite=1;	Address=16'd7;	

end

initial
begin
$monitor($time, "data at address %d is %h", Address, D_Out);
end

endmodule