data/full_repos/permissive/478970138/4-1/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:8: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:9: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #6000 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 data = ~data;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20 val = ~val;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-1/user/sim/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #40 enable = ~enable;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (

);

    reg data, enable, val;

    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb);
        #6000 $finish;
    end

    initial begin
        data    = 0;
        enable  = 0;
        val     = 0;
    end

    always begin
        #10 data = ~data;
    end

    always begin
        #20 val = ~val;
    end

    always begin
        #40 enable = ~enable;
    end

    wire 	dout;

    top u_top(

        .data   		( data   		),
        .enable 		( enable 		),
        .val    		( val    		),
        .dout   		( dout   		)
    );


endmodule
module tb (

);


    reg data, enable, val;

    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb);
        #6000 $finish;
    end

    initial begin
        data    = 0;
        enable  = 0;
        val     = 0;
    end

    always begin
        #10 data = ~data;
    end

    always begin
        #20 val = ~val;
    end

    always begin
        #40 enable = ~enable;
    end

    wire 	dout;

    top u_top(

        .data   		( data   		),
        .enable 		( enable 		),
        .val    		( val    		),
        .dout   		( dout   		)
    );


endmodule