data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module MERGE_LOGIC #(parameter                       E_LOG      = 2,
                     parameter                       USE_IPCORE = "INTEL",
                     parameter                       FLOAT      = "no",
                     parameter                       SIGNED     = "no",
                     parameter                       DATW       = 64,
                     parameter                       KEYW       = 32)
                    (input  wire                     CLK,
                     input  wire                     RST,
                     input  wire                     IN_FULL,
                     input  wire                     ENQ_A,
                     input  wire [(DATW<<E_LOG)-1:0] DIN_A,
                     input  wire                     ENQ_B,
                     input  wire [(DATW<<E_LOG)-1:0] DIN_B,
                     output wire                     FUL_A,
                     output wire                     FUL_B,
                     output wire [(DATW<<E_LOG)-1:0] DOT,
                     output wire                     DOTEN);

  localparam PAYW = DATW - KEYW;

  wire [(DATW<<E_LOG)-1:0] init_dummy_data;

  genvar i;
  generate
    for (i=0; i<(1<<E_LOG); i=i+1) begin: setdata
      if (FLOAT == "yes" || SIGNED == "yes") begin
        localparam [KEYW-1:0] MIN_KEY = {1'b1, {(KEYW-1){1'b0}}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end else begin
        localparam [KEYW-1:0] MIN_KEY = {(KEYW){1'b0}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end
    end
  endgenerate


  reg stall;
  always @(posedge CLK) stall <= IN_FULL;

  function integer clog2;
    input integer value;
    begin
      value = value - 1;
      for (clog2=0; value>0; clog2=clog2+1)
        value = value >> 1;
    end
  endfunction

  function mux;
    input       a;
    input       b;
    input       c;
    input [1:0] sel;
    begin
      case (sel)
        2'b00: mux = a;
        2'b01: mux = b;
        2'b10: mux = b;
        2'b11: mux = c;
      endcase
    end
  endfunction

  localparam FIFO_SIZE = clog2(((((E_LOG+1)<<1)<<1)+2));

  wire                     fifo_A_enq, fifo_B_enq;
  wire                     fifo_A_deq, fifo_B_deq;
  wire [(DATW<<E_LOG)-1:0] fifo_A_din, fifo_B_din;
  wire [(DATW<<E_LOG)-1:0] fifo_A_dot, fifo_B_dot;
  wire                     fifo_A_emp, fifo_B_emp;
  wire                     fifo_A_ful, fifo_B_ful;
  wire [5:0]               fifo_A_cnt, fifo_B_cnt;

  reg  [(DATW<<E_LOG)-1:0] A [2:0];
  reg  [(DATW<<E_LOG)-1:0] B [2:0];

  reg  [2:0]               init_A;
  reg  [2:0]               init_B;

  reg  [1:0]               comp_history;

  assign fifo_A_enq = ENQ_A;
  assign fifo_A_deq = &{~stall, ~fifo_A_emp, comp_history[0]};
  assign fifo_A_din = DIN_A;

  assign fifo_B_enq = ENQ_B;
  assign fifo_B_deq = ~|{stall, fifo_B_emp, comp_history[0]};
  assign fifo_B_din = DIN_B;

  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)
  fifo_A(CLK, RST, fifo_A_enq, fifo_A_deq, fifo_A_din,
         fifo_A_dot, fifo_A_emp, fifo_A_ful, fifo_A_cnt);
  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)
  fifo_B(CLK, RST, fifo_B_enq, fifo_B_deq, fifo_B_din,
         fifo_B_dot, fifo_B_emp, fifo_B_ful, fifo_B_cnt);

  integer p;
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<3; p=p+1) begin
        A[p]      <= init_dummy_data;
        init_A[p] <= 0;
      end
    end else if (fifo_A_deq) begin
      A[0]      <= fifo_A_dot;
      init_A[0] <= 1;
      for (p=1; p<3; p=p+1) begin
        A[p]      <= A[p-1];
        init_A[p] <= init_A[p-1];
      end
    end
  end
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<3; p=p+1) begin
        B[p]      <= init_dummy_data;
        init_B[p] <= 0;
      end
    end else if (fifo_B_deq) begin
      B[0]      <= fifo_B_dot;
      init_B[0] <= 1;
      for (p=1; p<3; p=p+1) begin
        B[p]      <= B[p-1];
        init_B[p] <= init_B[p-1];
      end
    end
  end

  generate
    for (i=0; i<3; i=i+1) begin: comp
      wire comparator_rslt;
      COMPARATOR #(FLOAT, SIGNED, KEYW)
      comparator(A[i][KEYW-1:0], B[2-i][KEYW-1:0], comparator_rslt);
      reg rslt;
      always @(posedge CLK) begin
        if (RST) begin
          rslt <= 0;
        end else if (|{fifo_B_deq,fifo_A_deq}) begin
          rslt <= comparator_rslt;
        end
      end
    end
  endgenerate

  always @(posedge CLK) begin
    if (RST) begin
      comp_history <= 0;
    end else if (|{fifo_B_deq,fifo_A_deq}) begin
      comp_history[0] <= mux(comp[2].rslt, comp[1].rslt, comp[0].rslt, comp_history);
      comp_history[1] <= comp_history[0];
    end
  end

  reg [(DATW<<E_LOG)-1:0] mnet_din_a;
  reg [(DATW<<E_LOG)-1:0] mnet_din_b;
  always @(posedge CLK) begin
    mnet_din_a <= A[2];
    mnet_din_b <= B[2];
  end

  reg mnet_sel_a;
  reg mnet_sel_b;
  always @(posedge CLK) begin
    if (RST) begin
      mnet_sel_a <= 0;
      mnet_sel_b <= 0;
    end else begin
      mnet_sel_a <= &{init_A[2], fifo_A_deq};
      mnet_sel_b <= &{init_B[2], fifo_B_deq};
    end
  end

  wire [(DATW<<E_LOG)-1:0] mnet_dot;
  wire                     mnet_doten;
  MERGE_NETWORK #(E_LOG, FLOAT, SIGNED, DATW, KEYW)
  merge_network(CLK, RST, mnet_din_a, mnet_sel_a, mnet_din_b, mnet_sel_b,
                mnet_dot, mnet_doten);

  wire                     fifo_C_enq;
  wire                     fifo_C_deq;
  wire [(DATW<<E_LOG)-1:0] fifo_C_din;
  wire [(DATW<<E_LOG)-1:0] fifo_C_dot;
  wire                     fifo_C_emp;
  wire                     fifo_C_ful;
  wire [FIFO_SIZE:0]       fifo_C_cnt;

  wire                     obuf_enq;
  wire                     obuf_deq;
  wire [(DATW<<E_LOG)-1:0] obuf_din;
  wire [(DATW<<E_LOG)-1:0] obuf_dot;
  wire                     obuf_emp;
  wire                     obuf_ful;
  wire [1:0]               obuf_cnt;

  assign fifo_C_enq = mnet_doten;
  assign fifo_C_deq = ~|{stall, fifo_C_emp};
  assign fifo_C_din = mnet_dot;

  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)
  fifo_C(CLK, RST, fifo_C_enq, fifo_C_deq, fifo_C_din,
         fifo_C_dot, fifo_C_emp, fifo_C_ful, fifo_C_cnt);


  assign FUL_A = fifo_A_ful;
  assign FUL_B = fifo_B_ful;
  assign DOT   = fifo_C_dot;
  assign DOTEN = fifo_C_deq;

endmodule
module MERGE_LOGIC #(parameter                       E_LOG      = 2,
                     parameter                       USE_IPCORE = "INTEL",
                     parameter                       FLOAT      = "no",
                     parameter                       SIGNED     = "no",
                     parameter                       DATW       = 64,
                     parameter                       KEYW       = 32)
                    (input  wire                     CLK,
                     input  wire                     RST,
                     input  wire                     IN_FULL,
                     input  wire                     ENQ_A,
                     input  wire [(DATW<<E_LOG)-1:0] DIN_A,
                     input  wire                     ENQ_B,
                     input  wire [(DATW<<E_LOG)-1:0] DIN_B,
                     output wire                     FUL_A,
                     output wire                     FUL_B,
                     output wire [(DATW<<E_LOG)-1:0] DOT,
                     output wire                     DOTEN);


  localparam PAYW = DATW - KEYW;

  wire [(DATW<<E_LOG)-1:0] init_dummy_data;

  genvar i;
  generate
    for (i=0; i<(1<<E_LOG); i=i+1) begin: setdata
      if (FLOAT == "yes" || SIGNED == "yes") begin
        localparam [KEYW-1:0] MIN_KEY = {1'b1, {(KEYW-1){1'b0}}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end else begin
        localparam [KEYW-1:0] MIN_KEY = {(KEYW){1'b0}};
        if (PAYW == 0) begin
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = MIN_KEY;
        end else begin
          localparam [PAYW-1:0] DUMMY_PAYLOAD = {(PAYW){1'b1}};
          assign init_dummy_data[DATW*(i+1)-1:DATW*i] = {DUMMY_PAYLOAD, MIN_KEY};
        end
      end
    end
  endgenerate


  reg stall;
  always @(posedge CLK) stall <= IN_FULL;

  function integer clog2;
    input integer value;
    begin
      value = value - 1;
      for (clog2=0; value>0; clog2=clog2+1)
        value = value >> 1;
    end
  endfunction

  function mux;
    input       a;
    input       b;
    input       c;
    input [1:0] sel;
    begin
      case (sel)
        2'b00: mux = a;
        2'b01: mux = b;
        2'b10: mux = b;
        2'b11: mux = c;
      endcase
    end
  endfunction

  localparam FIFO_SIZE = clog2(((((E_LOG+1)<<1)<<1)+2));

  wire                     fifo_A_enq, fifo_B_enq;
  wire                     fifo_A_deq, fifo_B_deq;
  wire [(DATW<<E_LOG)-1:0] fifo_A_din, fifo_B_din;
  wire [(DATW<<E_LOG)-1:0] fifo_A_dot, fifo_B_dot;
  wire                     fifo_A_emp, fifo_B_emp;
  wire                     fifo_A_ful, fifo_B_ful;
  wire [5:0]               fifo_A_cnt, fifo_B_cnt;

  reg  [(DATW<<E_LOG)-1:0] A [2:0];
  reg  [(DATW<<E_LOG)-1:0] B [2:0];

  reg  [2:0]               init_A;
  reg  [2:0]               init_B;

  reg  [1:0]               comp_history;

  assign fifo_A_enq = ENQ_A;
  assign fifo_A_deq = &{~stall, ~fifo_A_emp, comp_history[0]};
  assign fifo_A_din = DIN_A;

  assign fifo_B_enq = ENQ_B;
  assign fifo_B_deq = ~|{stall, fifo_B_emp, comp_history[0]};
  assign fifo_B_din = DIN_B;

  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)
  fifo_A(CLK, RST, fifo_A_enq, fifo_A_deq, fifo_A_din,
         fifo_A_dot, fifo_A_emp, fifo_A_ful, fifo_A_cnt);
  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)
  fifo_B(CLK, RST, fifo_B_enq, fifo_B_deq, fifo_B_din,
         fifo_B_dot, fifo_B_emp, fifo_B_ful, fifo_B_cnt);

  integer p;
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<3; p=p+1) begin
        A[p]      <= init_dummy_data;
        init_A[p] <= 0;
      end
    end else if (fifo_A_deq) begin
      A[0]      <= fifo_A_dot;
      init_A[0] <= 1;
      for (p=1; p<3; p=p+1) begin
        A[p]      <= A[p-1];
        init_A[p] <= init_A[p-1];
      end
    end
  end
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<3; p=p+1) begin
        B[p]      <= init_dummy_data;
        init_B[p] <= 0;
      end
    end else if (fifo_B_deq) begin
      B[0]      <= fifo_B_dot;
      init_B[0] <= 1;
      for (p=1; p<3; p=p+1) begin
        B[p]      <= B[p-1];
        init_B[p] <= init_B[p-1];
      end
    end
  end

  generate
    for (i=0; i<3; i=i+1) begin: comp
      wire comparator_rslt;
      COMPARATOR #(FLOAT, SIGNED, KEYW)
      comparator(A[i][KEYW-1:0], B[2-i][KEYW-1:0], comparator_rslt);
      reg rslt;
      always @(posedge CLK) begin
        if (RST) begin
          rslt <= 0;
        end else if (|{fifo_B_deq,fifo_A_deq}) begin
          rslt <= comparator_rslt;
        end
      end
    end
  endgenerate

  always @(posedge CLK) begin
    if (RST) begin
      comp_history <= 0;
    end else if (|{fifo_B_deq,fifo_A_deq}) begin
      comp_history[0] <= mux(comp[2].rslt, comp[1].rslt, comp[0].rslt, comp_history);
      comp_history[1] <= comp_history[0];
    end
  end

  reg [(DATW<<E_LOG)-1:0] mnet_din_a;
  reg [(DATW<<E_LOG)-1:0] mnet_din_b;
  always @(posedge CLK) begin
    mnet_din_a <= A[2];
    mnet_din_b <= B[2];
  end

  reg mnet_sel_a;
  reg mnet_sel_b;
  always @(posedge CLK) begin
    if (RST) begin
      mnet_sel_a <= 0;
      mnet_sel_b <= 0;
    end else begin
      mnet_sel_a <= &{init_A[2], fifo_A_deq};
      mnet_sel_b <= &{init_B[2], fifo_B_deq};
    end
  end

  wire [(DATW<<E_LOG)-1:0] mnet_dot;
  wire                     mnet_doten;
  MERGE_NETWORK #(E_LOG, FLOAT, SIGNED, DATW, KEYW)
  merge_network(CLK, RST, mnet_din_a, mnet_sel_a, mnet_din_b, mnet_sel_b,
                mnet_dot, mnet_doten);

  wire                     fifo_C_enq;
  wire                     fifo_C_deq;
  wire [(DATW<<E_LOG)-1:0] fifo_C_din;
  wire [(DATW<<E_LOG)-1:0] fifo_C_dot;
  wire                     fifo_C_emp;
  wire                     fifo_C_ful;
  wire [FIFO_SIZE:0]       fifo_C_cnt;

  wire                     obuf_enq;
  wire                     obuf_deq;
  wire [(DATW<<E_LOG)-1:0] obuf_din;
  wire [(DATW<<E_LOG)-1:0] obuf_dot;
  wire                     obuf_emp;
  wire                     obuf_ful;
  wire [1:0]               obuf_cnt;

  assign fifo_C_enq = mnet_doten;
  assign fifo_C_deq = ~|{stall, fifo_C_emp};
  assign fifo_C_din = mnet_dot;

  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)
  fifo_C(CLK, RST, fifo_C_enq, fifo_C_deq, fifo_C_din,
         fifo_C_dot, fifo_C_emp, fifo_C_ful, fifo_C_cnt);


  assign FUL_A = fifo_A_ful;
  assign FUL_B = fifo_B_ful;
  assign DOT   = fifo_C_dot;
  assign DOTEN = fifo_C_deq;

endmodule