data/full_repos/permissive/453129229/SDCARD_TEST.srcs/sources_1/imports/SDCARD/sdcard_interface.v
1: b"%Error: data/full_repos/permissive/453129229/SDCARD_TEST.srcs/sources_1/imports/SDCARD/sdcard_interface.v:318: syntax error, unexpected '(', expecting IDENTIFIER\n  .clk(clk),\n  ^\n%Error: Exiting due to 1 error(s)\n"
module sdcard_interface(
    input wire clk,rst,
    input wire btn,
    output wire led0_r,led0_g,led0_b,

	input wire SD_MISO,
	output wire SD_MOSI,
	output wire SD_DCLK,SD_nCS,

	output wire uart_rx,uart_tx
    );

    localparam POWER_ON=0, 
               COMMANDS=1,
               SEND_COMMAND=2,
               RECEIVE_RESPONSE=3,
               END_CMD=4,
			   IDLE=5,
			   DELAY=6,
			   WRITE_1=7,
			   WRITE_2=8,
			   BUSY=9;

					 
    reg[3:0] state_q=0,state_d;
    reg[9:0] counter_q=0,counter_d;
	reg[3:0] cmd_counter_q=0,cmd_counter_d;
	reg[3:0] response_counter_q=0,response_counter_d;
    reg[55:0] wr_data_q=0,wr_data_d;
	reg[39:0] rd_data_q=0,rd_data_d;
    reg[2:0] led_q=0,led_d;
	reg stuck_q=0,stuck_d;
	reg[9:0] stuck_counter_q=0,stuck_counter_d;
	reg[15:0] addr_counter_q,addr_counter_d;
	wire key_tick;
	

    reg rd,wr,hold;
    reg[7:0] wr_data;
    reg clk_div_q=0,clk_div_d;
    wire[7:0] rd_data;
    wire done_tick,ready;
    wire clk_div,cs_n_1;
    

	 reg wr_uart,rd_uart;
	 reg[7:0] wr_data_uart;
	 wire[7:0] rd_data_uart;
	 wire rx_empty;
	 

	 localparam INIT_LAST_INDEX=6;
	 reg[55:0] cmd_list[10:0];
	 initial begin
		cmd_list[0]=48'h40_00_00_00_00_95;
		cmd_list[1]=48'h48_00_00_01_AA_87;
		cmd_list[2]=48'h7B_00_00_00_00_83;
		cmd_list[3]=48'h77_00_00_00_00_00;
		cmd_list[4]=48'h69_40_00_00_00_00;
		cmd_list[5]=48'h7A_00_00_00_00_00;
		cmd_list[6]=48'h50_00_00_02_00_00;
		cmd_list[7]=48'h58_00_00_00_00_00;
		cmd_list[8]=48'h4D_00_00_00_00_00;
	 end
	 				 
	 

    always @(posedge clk,posedge rst) begin
        if(rst) begin
            state_q<=0;
            counter_q<=0;
            wr_data_q<=0;
			rd_data_q<=0;
            led_q<=0;
			cmd_counter_q<=0;
			response_counter_q<=0;
			stuck_q<=0;
			stuck_counter_q<=0;
			clk_div_q<=0;
			addr_counter_q<=0;
        end
        else begin
            state_q<=state_d;
            counter_q<=counter_d;
            wr_data_q<=wr_data_d;
			rd_data_q<=rd_data_d;
            led_q<=led_d;
		    cmd_counter_q<=cmd_counter_d;
		    response_counter_q<=response_counter_d;
		    stuck_q<=stuck_d;
		    stuck_counter_q<=stuck_counter_d;
		    clk_div_q<=clk_div_d;
		    addr_counter_q<=addr_counter_d;
        end
    end
    

    always @* begin
        state_d=state_q;
        counter_d=counter_q;
        wr_data_d=wr_data_q;
		rd_data_d=rd_data_q;
        led_d=led_q;
		cmd_counter_d=cmd_counter_q;
	    response_counter_d=response_counter_q;	  
	    stuck_d=stuck_q;
	    stuck_counter_d=stuck_counter_q;
	    clk_div_d=clk_div_q;
	    addr_counter_d=addr_counter_q;
        rd=0;
        wr=0;
        hold=0;
		wr_data=8'hff;
		 
        case(state_q)

            POWER_ON: if(btn) begin
                        rd=1;
                        led_d=3'b100;
					    cmd_counter_d=0;
					    clk_div_d=0;
					    addr_counter_d=0;
                        if(done_tick) begin
                            counter_d=counter_q+1'b1;
                            if(counter_q==15) begin
                                rd=0;
                                state_d=COMMANDS;
                            end
                        end
                      end
            COMMANDS: if(ready) begin
                        wr_data_d=cmd_list[cmd_counter_q]; 
                        if(cmd_counter_q==7) wr_data_d[39:8]=2049+addr_counter_q;
                        state_d=SEND_COMMAND;
						response_counter_d=0;
						counter_d=0;
		                stuck_counter_d=0;
		                stuck_d=0;
                      end
        SEND_COMMAND: if(ready || done_tick) begin 
                        wr_data_d={wr_data_q[47:0],8'hff};
                        wr_data=wr_data_d[55:48];
                        wr=1;
                        counter_d=counter_q+1'b1;
                        if(counter_q==7) begin
							wr=0;
                            rd=1;
                            counter_d=0;
                            state_d=RECEIVE_RESPONSE;
                        end
                      end 
     RECEIVE_RESPONSE: if(done_tick) begin
                         response_counter_d=response_counter_q+1;

                         case(cmd_counter_q) 
                            0: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                           1: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    led_d=3'b001;
                                    if(response_counter_d==5) begin
                                        cmd_counter_d=(rd_data_d==40'h01_00_00_01_AA)? cmd_counter_q+1:cmd_counter_q;
                                        rd=0;
                                        state_d=END_CMD;
                                    end
                                end
                            2: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                            3: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                            4: begin
                                    stuck_counter_d=stuck_counter_q+1;
                                    if(stuck_counter_q==1000) stuck_d=1;
                                    cmd_counter_d=(rd_data==8'h00)? cmd_counter_q+1:cmd_counter_q-1;
                                    state_d=END_CMD;
                                end
                            5: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    if(response_counter_d==5) begin
                                            rd=0;
                                            cmd_counter_d=(rd_data_d==40'h00_C0_FF_80_00)? cmd_counter_q+1:cmd_counter_q;
                                            state_d=END_CMD;
                                    end
                                end  
                             6: begin
                                    cmd_counter_d=(rd_data==8'h00)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                             7: begin
                                    state_d=WRITE_1;

                                end
                             8: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    if(response_counter_d==2) begin
                                        cmd_counter_d=(rd_data_d==16'h0000)? cmd_counter_q+1:cmd_counter_q;
                                        rd=1;
                                        state_d=IDLE;
                                        led_d=3'b010;
                                    end
                                  end
                          endcase			
                         end
            	
				END_CMD:if(ready) begin
                                wr=1;
                                state_d=stuck_q? POWER_ON:COMMANDS;
                                if(cmd_counter_q==INIT_LAST_INDEX+1 || clk_div_q) state_d=DELAY;
                          end
                   DELAY: if(ready) begin
                            stuck_counter_d=stuck_counter_d+1;
                            clk_div_d=1;
                            if(stuck_counter_d==1000) begin 
                            led_d=3'b010;
                            state_d=IDLE;
                            end
                          end

   
   

					IDLE: if(key_tick) begin
					           cmd_counter_d=7;
					           state_d=COMMANDS;
					           addr_counter_d=addr_counter_q+1;
					           led_d=100; 
					      end
				 WRITE_1: if(ready || done_tick) begin 
                            if(counter_q==0 || counter_q==513 || counter_q==514) wr_data=8'b1111_1110;
                            else wr_data=8'h60 + addr_counter_q;
                            wr=1;
                            counter_d=counter_q+1'b1;
                            if(counter_q==515) begin
                                wr=0;
                                rd=1;
                                counter_d=0;
                                state_d=WRITE_2;
                            end
                          end 
                 WRITE_2: if(done_tick) begin
                              state_d=BUSY;
                           end
                    BUSY: begin
                            rd=1;
                            if(SD_MISO && done_tick) begin
                                cmd_counter_d=8;
                                state_d=COMMANDS;
                            end
                          end
             default: state_d=POWER_ON;
        endcase
    end
    
    assign SD_nCS=(state_q==POWER_ON || state_q==COMMANDS || (state_q==END_CMD && ready) || state_q==IDLE)? 1'b1:cs_n_1;

	assign led0_r=led_q[2]? clk:1'b1, 
	       led0_g=led_q[1]? clk:1'b1,
	       led0_b=led_q[0]? clk:1'b1;
    assign idle=state_q==IDLE;
	 

    spi #(.HI_FREQ_DIV(2), .LO_FREQ_DIV(30), .SPI_MODE(0)) m0
    ( 
        .clk(clk),
        .rst(rst),                                

        .clk_div(clk_div_q),
        .rd(rd),
        .wr(wr),
        .hold(hold),
        .wr_data(wr_data),
        .rd_data(rd_data),
        .done_tick(done_tick),
        .ready(ready),

        .miso(SD_MISO),
        .mosi(SD_MOSI),
        .sclk(SD_DCLK),
        .cs_n(cs_n_1)
	);
	
	 uart #(.DBIT(8),.SB_TICK(16),.DVSR(78),.DVSR_WIDTH(9),.FIFO_W(10)) m1
	(
		.clk(clk),
		.rst_n({!rst}),
		.rd_uart(rd_uart),
		.wr_uart(wr_uart),
		.wr_data(wr_data_uart),
		.rx(uart_rx),
		.tx(uart_tx),
		.rd_data(rd_data_uart),
		.rx_empty(rx_empty),
		.tx_full()
    );
    

    always @* begin
    wr_uart=0;
    rd_uart=0;
	wr_data_uart=0;
 		wr_uart= wr || (state_q==RECEIVE_RESPONSE && done_tick) || (state_q==WRITE_2 && done_tick);
		wr_data_uart=wr? wr_data:rd_data;
    end
	
	debounce_explicit
	(
		.clk(clk),
		.rst_n({!rst}),
		.sw(btn),
		.db_level(),
		.db_tick(key_tick)
    );
	
   
endmodule
module sdcard_interface(
    input wire clk,rst,
    input wire btn,
    output wire led0_r,led0_g,led0_b,

	input wire SD_MISO,
	output wire SD_MOSI,
	output wire SD_DCLK,SD_nCS,

	output wire uart_rx,uart_tx
    );


    localparam POWER_ON=0, 
               COMMANDS=1,
               SEND_COMMAND=2,
               RECEIVE_RESPONSE=3,
               END_CMD=4,
			   IDLE=5,
			   DELAY=6,
			   WRITE_1=7,
			   WRITE_2=8,
			   BUSY=9;

					 
    reg[3:0] state_q=0,state_d;
    reg[9:0] counter_q=0,counter_d;
	reg[3:0] cmd_counter_q=0,cmd_counter_d;
	reg[3:0] response_counter_q=0,response_counter_d;
    reg[55:0] wr_data_q=0,wr_data_d;
	reg[39:0] rd_data_q=0,rd_data_d;
    reg[2:0] led_q=0,led_d;
	reg stuck_q=0,stuck_d;
	reg[9:0] stuck_counter_q=0,stuck_counter_d;
	reg[15:0] addr_counter_q,addr_counter_d;
	wire key_tick;
	

    reg rd,wr,hold;
    reg[7:0] wr_data;
    reg clk_div_q=0,clk_div_d;
    wire[7:0] rd_data;
    wire done_tick,ready;
    wire clk_div,cs_n_1;
    

	 reg wr_uart,rd_uart;
	 reg[7:0] wr_data_uart;
	 wire[7:0] rd_data_uart;
	 wire rx_empty;
	 

	 localparam INIT_LAST_INDEX=6;
	 reg[55:0] cmd_list[10:0];
	 initial begin
		cmd_list[0]=48'h40_00_00_00_00_95;
		cmd_list[1]=48'h48_00_00_01_AA_87;
		cmd_list[2]=48'h7B_00_00_00_00_83;
		cmd_list[3]=48'h77_00_00_00_00_00;
		cmd_list[4]=48'h69_40_00_00_00_00;
		cmd_list[5]=48'h7A_00_00_00_00_00;
		cmd_list[6]=48'h50_00_00_02_00_00;
		cmd_list[7]=48'h58_00_00_00_00_00;
		cmd_list[8]=48'h4D_00_00_00_00_00;
	 end
	 				 
	 

    always @(posedge clk,posedge rst) begin
        if(rst) begin
            state_q<=0;
            counter_q<=0;
            wr_data_q<=0;
			rd_data_q<=0;
            led_q<=0;
			cmd_counter_q<=0;
			response_counter_q<=0;
			stuck_q<=0;
			stuck_counter_q<=0;
			clk_div_q<=0;
			addr_counter_q<=0;
        end
        else begin
            state_q<=state_d;
            counter_q<=counter_d;
            wr_data_q<=wr_data_d;
			rd_data_q<=rd_data_d;
            led_q<=led_d;
		    cmd_counter_q<=cmd_counter_d;
		    response_counter_q<=response_counter_d;
		    stuck_q<=stuck_d;
		    stuck_counter_q<=stuck_counter_d;
		    clk_div_q<=clk_div_d;
		    addr_counter_q<=addr_counter_d;
        end
    end
    

    always @* begin
        state_d=state_q;
        counter_d=counter_q;
        wr_data_d=wr_data_q;
		rd_data_d=rd_data_q;
        led_d=led_q;
		cmd_counter_d=cmd_counter_q;
	    response_counter_d=response_counter_q;	  
	    stuck_d=stuck_q;
	    stuck_counter_d=stuck_counter_q;
	    clk_div_d=clk_div_q;
	    addr_counter_d=addr_counter_q;
        rd=0;
        wr=0;
        hold=0;
		wr_data=8'hff;
		 
        case(state_q)

            POWER_ON: if(btn) begin
                        rd=1;
                        led_d=3'b100;
					    cmd_counter_d=0;
					    clk_div_d=0;
					    addr_counter_d=0;
                        if(done_tick) begin
                            counter_d=counter_q+1'b1;
                            if(counter_q==15) begin
                                rd=0;
                                state_d=COMMANDS;
                            end
                        end
                      end
            COMMANDS: if(ready) begin
                        wr_data_d=cmd_list[cmd_counter_q]; 
                        if(cmd_counter_q==7) wr_data_d[39:8]=2049+addr_counter_q;
                        state_d=SEND_COMMAND;
						response_counter_d=0;
						counter_d=0;
		                stuck_counter_d=0;
		                stuck_d=0;
                      end
        SEND_COMMAND: if(ready || done_tick) begin 
                        wr_data_d={wr_data_q[47:0],8'hff};
                        wr_data=wr_data_d[55:48];
                        wr=1;
                        counter_d=counter_q+1'b1;
                        if(counter_q==7) begin
							wr=0;
                            rd=1;
                            counter_d=0;
                            state_d=RECEIVE_RESPONSE;
                        end
                      end 
     RECEIVE_RESPONSE: if(done_tick) begin
                         response_counter_d=response_counter_q+1;

                         case(cmd_counter_q) 
                            0: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                           1: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    led_d=3'b001;
                                    if(response_counter_d==5) begin
                                        cmd_counter_d=(rd_data_d==40'h01_00_00_01_AA)? cmd_counter_q+1:cmd_counter_q;
                                        rd=0;
                                        state_d=END_CMD;
                                    end
                                end
                            2: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                            3: begin
                                    cmd_counter_d=(rd_data==8'h01)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                            4: begin
                                    stuck_counter_d=stuck_counter_q+1;
                                    if(stuck_counter_q==1000) stuck_d=1;
                                    cmd_counter_d=(rd_data==8'h00)? cmd_counter_q+1:cmd_counter_q-1;
                                    state_d=END_CMD;
                                end
                            5: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    if(response_counter_d==5) begin
                                            rd=0;
                                            cmd_counter_d=(rd_data_d==40'h00_C0_FF_80_00)? cmd_counter_q+1:cmd_counter_q;
                                            state_d=END_CMD;
                                    end
                                end  
                             6: begin
                                    cmd_counter_d=(rd_data==8'h00)? cmd_counter_q+1:cmd_counter_q;
                                    state_d=END_CMD;
                                end
                             7: begin
                                    state_d=WRITE_1;

                                end
                             8: begin
                                    rd_data_d={rd_data_q[31:0],rd_data};
                                    rd=1;
                                    if(response_counter_d==2) begin
                                        cmd_counter_d=(rd_data_d==16'h0000)? cmd_counter_q+1:cmd_counter_q;
                                        rd=1;
                                        state_d=IDLE;
                                        led_d=3'b010;
                                    end
                                  end
                          endcase			
                         end
            	
				END_CMD:if(ready) begin
                                wr=1;
                                state_d=stuck_q? POWER_ON:COMMANDS;
                                if(cmd_counter_q==INIT_LAST_INDEX+1 || clk_div_q) state_d=DELAY;
                          end
                   DELAY: if(ready) begin
                            stuck_counter_d=stuck_counter_d+1;
                            clk_div_d=1;
                            if(stuck_counter_d==1000) begin 
                            led_d=3'b010;
                            state_d=IDLE;
                            end
                          end

   
   

					IDLE: if(key_tick) begin
					           cmd_counter_d=7;
					           state_d=COMMANDS;
					           addr_counter_d=addr_counter_q+1;
					           led_d=100; 
					      end
				 WRITE_1: if(ready || done_tick) begin 
                            if(counter_q==0 || counter_q==513 || counter_q==514) wr_data=8'b1111_1110;
                            else wr_data=8'h60 + addr_counter_q;
                            wr=1;
                            counter_d=counter_q+1'b1;
                            if(counter_q==515) begin
                                wr=0;
                                rd=1;
                                counter_d=0;
                                state_d=WRITE_2;
                            end
                          end 
                 WRITE_2: if(done_tick) begin
                              state_d=BUSY;
                           end
                    BUSY: begin
                            rd=1;
                            if(SD_MISO && done_tick) begin
                                cmd_counter_d=8;
                                state_d=COMMANDS;
                            end
                          end
             default: state_d=POWER_ON;
        endcase
    end
    
    assign SD_nCS=(state_q==POWER_ON || state_q==COMMANDS || (state_q==END_CMD && ready) || state_q==IDLE)? 1'b1:cs_n_1;

	assign led0_r=led_q[2]? clk:1'b1, 
	       led0_g=led_q[1]? clk:1'b1,
	       led0_b=led_q[0]? clk:1'b1;
    assign idle=state_q==IDLE;
	 

    spi #(.HI_FREQ_DIV(2), .LO_FREQ_DIV(30), .SPI_MODE(0)) m0
    ( 
        .clk(clk),
        .rst(rst),                                

        .clk_div(clk_div_q),
        .rd(rd),
        .wr(wr),
        .hold(hold),
        .wr_data(wr_data),
        .rd_data(rd_data),
        .done_tick(done_tick),
        .ready(ready),

        .miso(SD_MISO),
        .mosi(SD_MOSI),
        .sclk(SD_DCLK),
        .cs_n(cs_n_1)
	);
	
	 uart #(.DBIT(8),.SB_TICK(16),.DVSR(78),.DVSR_WIDTH(9),.FIFO_W(10)) m1
	(
		.clk(clk),
		.rst_n({!rst}),
		.rd_uart(rd_uart),
		.wr_uart(wr_uart),
		.wr_data(wr_data_uart),
		.rx(uart_rx),
		.tx(uart_tx),
		.rd_data(rd_data_uart),
		.rx_empty(rx_empty),
		.tx_full()
    );
    

    always @* begin
    wr_uart=0;
    rd_uart=0;
	wr_data_uart=0;
 		wr_uart= wr || (state_q==RECEIVE_RESPONSE && done_tick) || (state_q==WRITE_2 && done_tick);
		wr_data_uart=wr? wr_data:rd_data;
    end
	
	debounce_explicit
	(
		.clk(clk),
		.rst_n({!rst}),
		.sw(btn),
		.db_level(),
		.db_tick(key_tick)
    );
	
   
endmodule