data/full_repos/permissive/468612001/Week03/mux8b_2to1/mux8b_2to1_assign.v
data/verilator_xmls/5d93acbb-5bb9-440c-abf8-367e0dbf216e.xml
module mux8b_2to1_assign(a, b, sel, out);
	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	
	assign out = sel ? b : a;
endmodule
module mux8b_2to1_assign(a, b, sel, out);

	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	
	assign out = sel ? b : a;
endmodule