data/full_repos/permissive/470401923/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/470401923/verilog/rtl/user_project_wrapper.v:69: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470401923/verilog/rtl/user_project_wrapper.v:70: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470401923/verilog/rtl/user_project_wrapper.v:71: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470401923/verilog/rtl/user_project_wrapper.v:77: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





  wire [31:0] ram_clk_delay_sel;




















  wire        tag_array_ext_ram_clk;
  wire        tag_array_ext_ram_csb;
  wire        tag_array_ext_ram_web;
  wire [7:0]  tag_array_ext_ram_addr;
  wire [63:0] tag_array_ext_ram_wdata;
  wire [1:0]  tag_array_ext_ram_wmask;
  wire [31:0] tag_array_ext_ram_rdata0;
  wire [31:0] tag_array_ext_ram_rdata1;
  wire        tag_array_ext_ram_csb1;
  wire [7:0]  tag_array_ext_ram_addr1;


  wire        data_arrays_0_0_ext_ram_clk0;
  wire        data_arrays_0_0_ext_ram_clk1;
  wire        data_arrays_0_0_ext_ram_clk2;
  wire        data_arrays_0_0_ext_ram_clk3;
  wire [3:0]  data_arrays_0_0_ext_ram_csb;
  wire        data_arrays_0_0_ext_ram_web0;
  wire        data_arrays_0_0_ext_ram_web1;
  wire        data_arrays_0_0_ext_ram_web2;
  wire        data_arrays_0_0_ext_ram_web3;
  wire [8:0]  data_arrays_0_0_ext_ram_addr00;
  wire [8:0]  data_arrays_0_0_ext_ram_addr01;
  wire [8:0]  data_arrays_0_0_ext_ram_addr02;
  wire [8:0]  data_arrays_0_0_ext_ram_addr03;
  wire [63:0] data_arrays_0_0_ext_ram_wdata0;
  wire [63:0] data_arrays_0_0_ext_ram_wdata1;
  wire [63:0] data_arrays_0_0_ext_ram_wdata2;
  wire [63:0] data_arrays_0_0_ext_ram_wdata3;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask0;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask1;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask2;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask3;
  wire [63:0] data_arrays_0_0_ext_ram_rdata0;
  wire [63:0] data_arrays_0_0_ext_ram_rdata1;
  wire [63:0] data_arrays_0_0_ext_ram_rdata2;
  wire [63:0] data_arrays_0_0_ext_ram_rdata3;
  wire [3:0]  data_arrays_0_0_ext_ram_csb1;
  wire [8:0]  data_arrays_0_0_ext_ram_addr10;
  wire [8:0]  data_arrays_0_0_ext_ram_addr11;
  wire [8:0]  data_arrays_0_0_ext_ram_addr12;
  wire [8:0]  data_arrays_0_0_ext_ram_addr13;

Marmot Marmot (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),


    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_dat_o(wbs_dat_o),


    .la_data_in(la_data_in),
    .la_data_out(la_data_out),
    .la_oenb (la_oenb),


    .io_in (io_in),
    .io_out(io_out),
    .io_oeb(io_oeb),


    .irq(user_irq),


    .ram_clk_delay_sel(ram_clk_delay_sel),




















    .tag_array_ext_ram_clk(),
    .tag_array_ext_ram_csb(tag_array_ext_ram_csb),
    .tag_array_ext_ram_web(tag_array_ext_ram_web),
    .tag_array_ext_ram_addr(tag_array_ext_ram_addr),
    .tag_array_ext_ram_wdata(tag_array_ext_ram_wdata),
    .tag_array_ext_ram_wmask(tag_array_ext_ram_wmask),
    .tag_array_ext_ram_rdata0(tag_array_ext_ram_rdata0),
    .tag_array_ext_ram_rdata1(tag_array_ext_ram_rdata1),
    .tag_array_ext_ram_csb1(tag_array_ext_ram_csb1),
    .tag_array_ext_ram_addr1(tag_array_ext_ram_addr1),


    .data_arrays_0_0_ext_ram_clk(),
    .data_arrays_0_0_ext_ram_csb(data_arrays_0_0_ext_ram_csb),
    .data_arrays_0_0_ext_ram_web0(data_arrays_0_0_ext_ram_web0),
    .data_arrays_0_0_ext_ram_web1(data_arrays_0_0_ext_ram_web1),
    .data_arrays_0_0_ext_ram_web2(data_arrays_0_0_ext_ram_web2),
    .data_arrays_0_0_ext_ram_web3(data_arrays_0_0_ext_ram_web3),
    .data_arrays_0_0_ext_ram_addr00(data_arrays_0_0_ext_ram_addr00),
    .data_arrays_0_0_ext_ram_addr01(data_arrays_0_0_ext_ram_addr01),
    .data_arrays_0_0_ext_ram_addr02(data_arrays_0_0_ext_ram_addr02),
    .data_arrays_0_0_ext_ram_addr03(data_arrays_0_0_ext_ram_addr03),
    .data_arrays_0_0_ext_ram_wdata0(data_arrays_0_0_ext_ram_wdata0),
    .data_arrays_0_0_ext_ram_wdata1(data_arrays_0_0_ext_ram_wdata1),
    .data_arrays_0_0_ext_ram_wdata2(data_arrays_0_0_ext_ram_wdata2),
    .data_arrays_0_0_ext_ram_wdata3(data_arrays_0_0_ext_ram_wdata3),
    .data_arrays_0_0_ext_ram_wmask0(data_arrays_0_0_ext_ram_wmask0),
    .data_arrays_0_0_ext_ram_wmask1(data_arrays_0_0_ext_ram_wmask1),
    .data_arrays_0_0_ext_ram_wmask2(data_arrays_0_0_ext_ram_wmask2),
    .data_arrays_0_0_ext_ram_wmask3(data_arrays_0_0_ext_ram_wmask3),
    .data_arrays_0_0_ext_ram_rdata0(data_arrays_0_0_ext_ram_rdata0),
    .data_arrays_0_0_ext_ram_rdata1(data_arrays_0_0_ext_ram_rdata1),
    .data_arrays_0_0_ext_ram_rdata2(data_arrays_0_0_ext_ram_rdata2),
    .data_arrays_0_0_ext_ram_rdata3(data_arrays_0_0_ext_ram_rdata3),
    .data_arrays_0_0_ext_ram_csb1(data_arrays_0_0_ext_ram_csb1),
    .data_arrays_0_0_ext_ram_addr10(data_arrays_0_0_ext_ram_addr10),
    .data_arrays_0_0_ext_ram_addr11(data_arrays_0_0_ext_ram_addr11),
    .data_arrays_0_0_ext_ram_addr12(data_arrays_0_0_ext_ram_addr12),
    .data_arrays_0_0_ext_ram_addr13(data_arrays_0_0_ext_ram_addr13)
);




`ifdef DO_NOT_DEFINE
  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram0 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata0),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram1 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata1),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram2 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata2),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram3 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata3),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram4 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[4]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata4),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[4]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram5 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[5]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata5),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[5]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram6 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[6]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata6),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[6]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram7 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[7]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata7),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[7]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );
`endif




  clk_skew_adjust u_clk_skew_adjust_0 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[4:0]),
      .clk_out(tag_array_ext_ram_clk)
  );

  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(`VERBOSE)) tag_array_ext_ram0h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (tag_array_ext_ram_clk),
    .csb0   (tag_array_ext_ram_csb),
    .web0   (tag_array_ext_ram_web),
    .wmask0 ({4{tag_array_ext_ram_wmask[1]}}),
    .addr0  (tag_array_ext_ram_addr),
    .din0   (tag_array_ext_ram_wdata[63:32]),
    .dout0  (tag_array_ext_ram_rdata1),
    .clk1   (tag_array_ext_ram_clk),
    .csb1   (tag_array_ext_ram_csb1),
    .addr1  (tag_array_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(`VERBOSE)) tag_array_ext_ram0l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (tag_array_ext_ram_clk),
    .csb0   (tag_array_ext_ram_csb),
    .web0   (tag_array_ext_ram_web),
    .wmask0 ({4{tag_array_ext_ram_wmask[0]}}),
    .addr0  (tag_array_ext_ram_addr),
    .din0   (tag_array_ext_ram_wdata[31:0]),
    .dout0  (tag_array_ext_ram_rdata0),
    .clk1   (tag_array_ext_ram_clk),
    .csb1   (tag_array_ext_ram_csb1),
    .addr1  (tag_array_ext_ram_addr1),
    .dout1  ()
  );




  clk_skew_adjust u_clk_skew_adjust_1 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[9:5]),
      .clk_out(data_arrays_0_0_ext_ram_clk0)
  );

  clk_skew_adjust u_clk_skew_adjust_2 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[14:10]),
      .clk_out(data_arrays_0_0_ext_ram_clk1)
  );

  clk_skew_adjust u_clk_skew_adjust_3 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[19:15]),
      .clk_out(data_arrays_0_0_ext_ram_clk2)
  );

  clk_skew_adjust u_clk_skew_adjust_4 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[24:20]),
      .clk_out(data_arrays_0_0_ext_ram_clk3)
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram0h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk0),
    .csb0   (data_arrays_0_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_0_ext_ram_web0),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask0[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr00),
    .din0   (data_arrays_0_0_ext_ram_wdata0[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata0[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk0),
    .csb1   (data_arrays_0_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_0_ext_ram_addr10),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram0l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk0),
    .csb0   (data_arrays_0_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_0_ext_ram_web0),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask0[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr00),
    .din0   (data_arrays_0_0_ext_ram_wdata0[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata0[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk0),
    .csb1   (data_arrays_0_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_0_ext_ram_addr10),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram1h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk1),
    .csb0   (data_arrays_0_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_0_ext_ram_web1),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask1[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr01),
    .din0   (data_arrays_0_0_ext_ram_wdata1[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata1[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk1),
    .csb1   (data_arrays_0_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_0_ext_ram_addr11),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram1l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk1),
    .csb0   (data_arrays_0_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_0_ext_ram_web1),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask1[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr01),
    .din0   (data_arrays_0_0_ext_ram_wdata1[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata1[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk1),
    .csb1   (data_arrays_0_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_0_ext_ram_addr11),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram2h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk2),
    .csb0   (data_arrays_0_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_0_ext_ram_web2),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask2[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr02),
    .din0   (data_arrays_0_0_ext_ram_wdata2[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata2[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk2),
    .csb1   (data_arrays_0_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_0_ext_ram_addr12),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram2l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk2),
    .csb0   (data_arrays_0_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_0_ext_ram_web2),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask2[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr02),
    .din0   (data_arrays_0_0_ext_ram_wdata2[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata2[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk2),
    .csb1   (data_arrays_0_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_0_ext_ram_addr12),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram3h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk3),
    .csb0   (data_arrays_0_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_0_ext_ram_web3),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask3[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr03),
    .din0   (data_arrays_0_0_ext_ram_wdata3[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata3[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk3),
    .csb1   (data_arrays_0_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_0_ext_ram_addr13),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram3l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk3),
    .csb0   (data_arrays_0_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_0_ext_ram_web3),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask3[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr03),
    .din0   (data_arrays_0_0_ext_ram_wdata3[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata3[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk3),
    .csb1   (data_arrays_0_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_0_ext_ram_addr13),
    .dout1  ()
  );

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);






  wire [31:0] ram_clk_delay_sel;




















  wire        tag_array_ext_ram_clk;
  wire        tag_array_ext_ram_csb;
  wire        tag_array_ext_ram_web;
  wire [7:0]  tag_array_ext_ram_addr;
  wire [63:0] tag_array_ext_ram_wdata;
  wire [1:0]  tag_array_ext_ram_wmask;
  wire [31:0] tag_array_ext_ram_rdata0;
  wire [31:0] tag_array_ext_ram_rdata1;
  wire        tag_array_ext_ram_csb1;
  wire [7:0]  tag_array_ext_ram_addr1;


  wire        data_arrays_0_0_ext_ram_clk0;
  wire        data_arrays_0_0_ext_ram_clk1;
  wire        data_arrays_0_0_ext_ram_clk2;
  wire        data_arrays_0_0_ext_ram_clk3;
  wire [3:0]  data_arrays_0_0_ext_ram_csb;
  wire        data_arrays_0_0_ext_ram_web0;
  wire        data_arrays_0_0_ext_ram_web1;
  wire        data_arrays_0_0_ext_ram_web2;
  wire        data_arrays_0_0_ext_ram_web3;
  wire [8:0]  data_arrays_0_0_ext_ram_addr00;
  wire [8:0]  data_arrays_0_0_ext_ram_addr01;
  wire [8:0]  data_arrays_0_0_ext_ram_addr02;
  wire [8:0]  data_arrays_0_0_ext_ram_addr03;
  wire [63:0] data_arrays_0_0_ext_ram_wdata0;
  wire [63:0] data_arrays_0_0_ext_ram_wdata1;
  wire [63:0] data_arrays_0_0_ext_ram_wdata2;
  wire [63:0] data_arrays_0_0_ext_ram_wdata3;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask0;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask1;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask2;
  wire [1:0]  data_arrays_0_0_ext_ram_wmask3;
  wire [63:0] data_arrays_0_0_ext_ram_rdata0;
  wire [63:0] data_arrays_0_0_ext_ram_rdata1;
  wire [63:0] data_arrays_0_0_ext_ram_rdata2;
  wire [63:0] data_arrays_0_0_ext_ram_rdata3;
  wire [3:0]  data_arrays_0_0_ext_ram_csb1;
  wire [8:0]  data_arrays_0_0_ext_ram_addr10;
  wire [8:0]  data_arrays_0_0_ext_ram_addr11;
  wire [8:0]  data_arrays_0_0_ext_ram_addr12;
  wire [8:0]  data_arrays_0_0_ext_ram_addr13;

Marmot Marmot (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),


    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_dat_o(wbs_dat_o),


    .la_data_in(la_data_in),
    .la_data_out(la_data_out),
    .la_oenb (la_oenb),


    .io_in (io_in),
    .io_out(io_out),
    .io_oeb(io_oeb),


    .irq(user_irq),


    .ram_clk_delay_sel(ram_clk_delay_sel),




















    .tag_array_ext_ram_clk(),
    .tag_array_ext_ram_csb(tag_array_ext_ram_csb),
    .tag_array_ext_ram_web(tag_array_ext_ram_web),
    .tag_array_ext_ram_addr(tag_array_ext_ram_addr),
    .tag_array_ext_ram_wdata(tag_array_ext_ram_wdata),
    .tag_array_ext_ram_wmask(tag_array_ext_ram_wmask),
    .tag_array_ext_ram_rdata0(tag_array_ext_ram_rdata0),
    .tag_array_ext_ram_rdata1(tag_array_ext_ram_rdata1),
    .tag_array_ext_ram_csb1(tag_array_ext_ram_csb1),
    .tag_array_ext_ram_addr1(tag_array_ext_ram_addr1),


    .data_arrays_0_0_ext_ram_clk(),
    .data_arrays_0_0_ext_ram_csb(data_arrays_0_0_ext_ram_csb),
    .data_arrays_0_0_ext_ram_web0(data_arrays_0_0_ext_ram_web0),
    .data_arrays_0_0_ext_ram_web1(data_arrays_0_0_ext_ram_web1),
    .data_arrays_0_0_ext_ram_web2(data_arrays_0_0_ext_ram_web2),
    .data_arrays_0_0_ext_ram_web3(data_arrays_0_0_ext_ram_web3),
    .data_arrays_0_0_ext_ram_addr00(data_arrays_0_0_ext_ram_addr00),
    .data_arrays_0_0_ext_ram_addr01(data_arrays_0_0_ext_ram_addr01),
    .data_arrays_0_0_ext_ram_addr02(data_arrays_0_0_ext_ram_addr02),
    .data_arrays_0_0_ext_ram_addr03(data_arrays_0_0_ext_ram_addr03),
    .data_arrays_0_0_ext_ram_wdata0(data_arrays_0_0_ext_ram_wdata0),
    .data_arrays_0_0_ext_ram_wdata1(data_arrays_0_0_ext_ram_wdata1),
    .data_arrays_0_0_ext_ram_wdata2(data_arrays_0_0_ext_ram_wdata2),
    .data_arrays_0_0_ext_ram_wdata3(data_arrays_0_0_ext_ram_wdata3),
    .data_arrays_0_0_ext_ram_wmask0(data_arrays_0_0_ext_ram_wmask0),
    .data_arrays_0_0_ext_ram_wmask1(data_arrays_0_0_ext_ram_wmask1),
    .data_arrays_0_0_ext_ram_wmask2(data_arrays_0_0_ext_ram_wmask2),
    .data_arrays_0_0_ext_ram_wmask3(data_arrays_0_0_ext_ram_wmask3),
    .data_arrays_0_0_ext_ram_rdata0(data_arrays_0_0_ext_ram_rdata0),
    .data_arrays_0_0_ext_ram_rdata1(data_arrays_0_0_ext_ram_rdata1),
    .data_arrays_0_0_ext_ram_rdata2(data_arrays_0_0_ext_ram_rdata2),
    .data_arrays_0_0_ext_ram_rdata3(data_arrays_0_0_ext_ram_rdata3),
    .data_arrays_0_0_ext_ram_csb1(data_arrays_0_0_ext_ram_csb1),
    .data_arrays_0_0_ext_ram_addr10(data_arrays_0_0_ext_ram_addr10),
    .data_arrays_0_0_ext_ram_addr11(data_arrays_0_0_ext_ram_addr11),
    .data_arrays_0_0_ext_ram_addr12(data_arrays_0_0_ext_ram_addr12),
    .data_arrays_0_0_ext_ram_addr13(data_arrays_0_0_ext_ram_addr13)
);




`ifdef DO_NOT_DEFINE
  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram0 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata0),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram1 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata1),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram2 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata2),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram3 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata3),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram4 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[4]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata4),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[4]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram5 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[5]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata5),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[5]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram6 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[6]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata6),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[6]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_ext_ram7 (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_ext_ram_clk),
    .csb0   (data_arrays_0_ext_ram_csb[7]),
    .web0   (data_arrays_0_ext_ram_web),
    .wmask0 (data_arrays_0_ext_ram_wmask),
    .addr0  (data_arrays_0_ext_ram_addr),
    .din0   (data_arrays_0_ext_ram_wdata),
    .dout0  (data_arrays_0_ext_ram_rdata7),
    .clk1   (data_arrays_0_ext_ram_clk),
    .csb1   (data_arrays_0_ext_ram_csb1[7]),
    .addr1  (data_arrays_0_ext_ram_addr1),
    .dout1  ()
  );
`endif




  clk_skew_adjust u_clk_skew_adjust_0 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[4:0]),
      .clk_out(tag_array_ext_ram_clk)
  );

  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(`VERBOSE)) tag_array_ext_ram0h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (tag_array_ext_ram_clk),
    .csb0   (tag_array_ext_ram_csb),
    .web0   (tag_array_ext_ram_web),
    .wmask0 ({4{tag_array_ext_ram_wmask[1]}}),
    .addr0  (tag_array_ext_ram_addr),
    .din0   (tag_array_ext_ram_wdata[63:32]),
    .dout0  (tag_array_ext_ram_rdata1),
    .clk1   (tag_array_ext_ram_clk),
    .csb1   (tag_array_ext_ram_csb1),
    .addr1  (tag_array_ext_ram_addr1),
    .dout1  ()
  );

  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(`VERBOSE)) tag_array_ext_ram0l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (tag_array_ext_ram_clk),
    .csb0   (tag_array_ext_ram_csb),
    .web0   (tag_array_ext_ram_web),
    .wmask0 ({4{tag_array_ext_ram_wmask[0]}}),
    .addr0  (tag_array_ext_ram_addr),
    .din0   (tag_array_ext_ram_wdata[31:0]),
    .dout0  (tag_array_ext_ram_rdata0),
    .clk1   (tag_array_ext_ram_clk),
    .csb1   (tag_array_ext_ram_csb1),
    .addr1  (tag_array_ext_ram_addr1),
    .dout1  ()
  );




  clk_skew_adjust u_clk_skew_adjust_1 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[9:5]),
      .clk_out(data_arrays_0_0_ext_ram_clk0)
  );

  clk_skew_adjust u_clk_skew_adjust_2 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[14:10]),
      .clk_out(data_arrays_0_0_ext_ram_clk1)
  );

  clk_skew_adjust u_clk_skew_adjust_3 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[19:15]),
      .clk_out(data_arrays_0_0_ext_ram_clk2)
  );

  clk_skew_adjust u_clk_skew_adjust_4 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
      .clk_in(wb_clk_i),
      .sel(ram_clk_delay_sel[24:20]),
      .clk_out(data_arrays_0_0_ext_ram_clk3)
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram0h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk0),
    .csb0   (data_arrays_0_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_0_ext_ram_web0),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask0[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr00),
    .din0   (data_arrays_0_0_ext_ram_wdata0[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata0[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk0),
    .csb1   (data_arrays_0_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_0_ext_ram_addr10),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram0l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk0),
    .csb0   (data_arrays_0_0_ext_ram_csb[0]),
    .web0   (data_arrays_0_0_ext_ram_web0),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask0[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr00),
    .din0   (data_arrays_0_0_ext_ram_wdata0[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata0[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk0),
    .csb1   (data_arrays_0_0_ext_ram_csb1[0]),
    .addr1  (data_arrays_0_0_ext_ram_addr10),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram1h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk1),
    .csb0   (data_arrays_0_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_0_ext_ram_web1),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask1[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr01),
    .din0   (data_arrays_0_0_ext_ram_wdata1[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata1[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk1),
    .csb1   (data_arrays_0_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_0_ext_ram_addr11),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram1l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk1),
    .csb0   (data_arrays_0_0_ext_ram_csb[1]),
    .web0   (data_arrays_0_0_ext_ram_web1),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask1[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr01),
    .din0   (data_arrays_0_0_ext_ram_wdata1[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata1[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk1),
    .csb1   (data_arrays_0_0_ext_ram_csb1[1]),
    .addr1  (data_arrays_0_0_ext_ram_addr11),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram2h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk2),
    .csb0   (data_arrays_0_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_0_ext_ram_web2),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask2[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr02),
    .din0   (data_arrays_0_0_ext_ram_wdata2[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata2[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk2),
    .csb1   (data_arrays_0_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_0_ext_ram_addr12),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram2l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk2),
    .csb0   (data_arrays_0_0_ext_ram_csb[2]),
    .web0   (data_arrays_0_0_ext_ram_web2),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask2[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr02),
    .din0   (data_arrays_0_0_ext_ram_wdata2[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata2[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk2),
    .csb1   (data_arrays_0_0_ext_ram_csb1[2]),
    .addr1  (data_arrays_0_0_ext_ram_addr12),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram3h (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk3),
    .csb0   (data_arrays_0_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_0_ext_ram_web3),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask3[1]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr03),
    .din0   (data_arrays_0_0_ext_ram_wdata3[63:32]),
    .dout0  (data_arrays_0_0_ext_ram_rdata3[63:32]),
    .clk1   (data_arrays_0_0_ext_ram_clk3),
    .csb1   (data_arrays_0_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_0_ext_ram_addr13),
    .dout1  ()
  );

  sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) data_arrays_0_0_ext_ram3l (
`ifdef USE_POWER_PINS
    .vccd1  (vccd1),
    .vssd1  (vssd1),
`endif
    .clk0   (data_arrays_0_0_ext_ram_clk3),
    .csb0   (data_arrays_0_0_ext_ram_csb[3]),
    .web0   (data_arrays_0_0_ext_ram_web3),
    .wmask0 ({4{data_arrays_0_0_ext_ram_wmask3[0]}}),
    .addr0  (data_arrays_0_0_ext_ram_addr03),
    .din0   (data_arrays_0_0_ext_ram_wdata3[31:0]),
    .dout0  (data_arrays_0_0_ext_ram_rdata3[31:0]),
    .clk1   (data_arrays_0_0_ext_ram_clk3),
    .csb1   (data_arrays_0_0_ext_ram_csb1[3]),
    .addr1  (data_arrays_0_0_ext_ram_addr13),
    .dout1  ()
  );

endmodule