data/full_repos/permissive/445455582/single/tb/system_tb.v
1: b'%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:23: Cannot find include file: RiSC16_system.v\n`include "RiSC16_system.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:50: Unsupported or unknown PLI call: $monitor\n        $monitor("%g: pc %h, IR %h", $time, system.PC, system.IR);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("system_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, system_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/system_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, system_tb.system.rf.dataRegister[2]);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #6      instr   <= 16\'b0110101000000000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #4     instr   <= 16\'b0110110100000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #4     instr   <= 16\'b0000100100000011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #4     pen     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #4     rst     <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #16     $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/system_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    always #2 clk <= ~clk;\n           ^\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module system_tb;

    reg clk = 0;
    reg pen = 1;
    reg rst = 1;
    reg [15:0] instr = 16'h0000;
    reg [15:0] addr = 16'h0000;


    RiSC16_system #(
        .WORD_LENGTH(16),
        .PROGRAM_SIZE(20),
        .DATA_SIZE(20)
    ) system (
        .clk(clk), 
        .addr(addr),
        .pen(pen), 
        .instr(instr), 
        .rst(rst)
    );


    initial begin
        

        $monitor("%g: pc %h, IR %h", $time, system.PC, system.IR);
        $dumpfile("system_tb.vcd");
        $dumpvars(0, system_tb);
        $dumpvars(0, system_tb.system.rf.dataRegister[2]);

        $display("System Purge");

        $display("System Programming");
        $display("b0110101000000000 lui 2, 0x200");
        #6      instr   <= 16'b0110101000000000;
                addr    <= 16'h0000;
                rst     <= 0;

        $display("b0110110100000000 lui 3, 0x100");
        #4     instr   <= 16'b0110110100000000;
                addr    <= 16'h0001;

        $display("b0000100100000011 add 2, 2, 3");
        #4     instr   <= 16'b0000100100000011;
               addr    <= 16'h0002;
        
        $display("Finish Programming to Reset");
        #4     pen     <= 0;
                rst     <= 1;

        #4     rst     <= 0;

        #16     $finish;

    end

    always #2 clk <= ~clk;

endmodule
module system_tb;


    reg clk = 0;
    reg pen = 1;
    reg rst = 1;
    reg [15:0] instr = 16'h0000;
    reg [15:0] addr = 16'h0000;


    RiSC16_system #(
        .WORD_LENGTH(16),
        .PROGRAM_SIZE(20),
        .DATA_SIZE(20)
    ) system (
        .clk(clk), 
        .addr(addr),
        .pen(pen), 
        .instr(instr), 
        .rst(rst)
    );


    initial begin
        

        $monitor("%g: pc %h, IR %h", $time, system.PC, system.IR);
        $dumpfile("system_tb.vcd");
        $dumpvars(0, system_tb);
        $dumpvars(0, system_tb.system.rf.dataRegister[2]);

        $display("System Purge");

        $display("System Programming");
        $display("b0110101000000000 lui 2, 0x200");
        #6      instr   <= 16'b0110101000000000;
                addr    <= 16'h0000;
                rst     <= 0;

        $display("b0110110100000000 lui 3, 0x100");
        #4     instr   <= 16'b0110110100000000;
                addr    <= 16'h0001;

        $display("b0000100100000011 add 2, 2, 3");
        #4     instr   <= 16'b0000100100000011;
               addr    <= 16'h0002;
        
        $display("Finish Programming to Reset");
        #4     pen     <= 0;
                rst     <= 1;

        #4     rst     <= 0;

        #16     $finish;

    end

    always #2 clk <= ~clk;

endmodule