data/full_repos/permissive/478970138/4-7/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/478970138/4-7/user/sim/tb.v:8: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("wave.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/478970138/4-7/user/sim/tb.v:9: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0, tb);\n       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-7/user/sim/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n       #6000 $finish;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-7/user/sim/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10 in = in + 1\'b1;\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (

);

    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg [4:0] in = 5'b0;

    always begin
        #10 in = in + 1'b1;
    end

    wire    a, b, c, d, e;
    assign {a, b, c, d, e} = in;
    wire 	result;

    Voter u_Voter(

        .a      		( a      		),
        .b      		( b      		),
        .c      		( c      		),
        .d      		( d      		),
        .e      		( e      		),
        .result 		( result 		)
    );


endmodule
module tb (

);


    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg [4:0] in = 5'b0;

    always begin
        #10 in = in + 1'b1;
    end

    wire    a, b, c, d, e;
    assign {a, b, c, d, e} = in;
    wire 	result;

    Voter u_Voter(

        .a      		( a      		),
        .b      		( b      		),
        .c      		( c      		),
        .d      		( d      		),
        .e      		( e      		),
        .result 		( result 		)
    );


endmodule