data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v
1: b'%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:24: Unsupported: event data types\n   event reset_trigger;\n   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #OFFSET;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1\'b1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n         #(PERIOD*DUTY_CYCLE);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:45: syntax error, unexpected \'@\'\n        @ (reset_trigger);\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:48: syntax error, unexpected \'@\'\n        @ (posedge clk);\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:52: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:60: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("div_16_TB.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:61: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(-1, uut);\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:63: syntax error, unexpected ->\n     #10 -> reset_trigger;\n         ^~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n     #10 -> reset_trigger;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/div_16_TB.v:64: Unsupported: Ignoring delay on this delayed statement.\n     #((PERIOD*DUTY_CYCLE)*120) $finish;\n     ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module div_16_TB;

   reg  clk;
   reg  rst;
   reg  reset;
   reg  start;
   reg  init_in;
   reg  [15:0]A;
   reg  [15:0]B;
   wire [15:0] Result;
   wire done;

   div_16 uut (.clk(clk) , .rst(rst) , .init_in(start) , .A(A) , .B(B) , .Result(Result) , .done(done));

   parameter PERIOD          = 20;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;
   reg [20:0] i;
   event reset_trigger;




   initial begin
      clk = 0; reset = 1; start = 0; A = 16'd35; B = 16'd5;
   end

   initial  begin
     #OFFSET;
     forever
       begin
         clk = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
         #(PERIOD*DUTY_CYCLE);
       end
   end

   initial begin
      forever begin 
        @ (reset_trigger);
        @ (posedge clk);
        start = 0;
        @ (posedge clk);
        start = 1;

       for(i=0; i<2; i=i+1) begin
         @ (posedge clk);
       end
          start = 0;
      end
   end
	 

   initial begin: TEST_CASE
     $dumpfile("div_16_TB.vcd");
     $dumpvars(-1, uut);
	
     #10 -> reset_trigger;
     #((PERIOD*DUTY_CYCLE)*120) $finish;
   end

endmodule
module div_16_TB;


   reg  clk;
   reg  rst;
   reg  reset;
   reg  start;
   reg  init_in;
   reg  [15:0]A;
   reg  [15:0]B;
   wire [15:0] Result;
   wire done;

   div_16 uut (.clk(clk) , .rst(rst) , .init_in(start) , .A(A) , .B(B) , .Result(Result) , .done(done));

   parameter PERIOD          = 20;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;
   reg [20:0] i;
   event reset_trigger;




   initial begin
      clk = 0; reset = 1; start = 0; A = 16'd35; B = 16'd5;
   end

   initial  begin
     #OFFSET;
     forever
       begin
         clk = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
         #(PERIOD*DUTY_CYCLE);
       end
   end

   initial begin
      forever begin 
        @ (reset_trigger);
        @ (posedge clk);
        start = 0;
        @ (posedge clk);
        start = 1;

       for(i=0; i<2; i=i+1) begin
         @ (posedge clk);
       end
          start = 0;
      end
   end
	 

   initial begin: TEST_CASE
     $dumpfile("div_16_TB.vcd");
     $dumpvars(-1, uut);
	
     #10 -> reset_trigger;
     #((PERIOD*DUTY_CYCLE)*120) $finish;
   end

endmodule