data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test folder/VGA_top.v
1: b'%Error: Cannot find file containing module: folder,data/full_repos/permissive/496231454\n        ... Looked in:\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454.v\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454.sv\n             folder,data/full_repos/permissive/496231454\n             folder,data/full_repos/permissive/496231454.v\n             folder,data/full_repos/permissive/496231454.sv\n             obj_dir/folder,data/full_repos/permissive/496231454\n             obj_dir/folder,data/full_repos/permissive/496231454.v\n             obj_dir/folder,data/full_repos/permissive/496231454.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test\n%Error: Cannot find file containing module: folder/VGA_top.v\n%Error: Exiting due to 3 error(s)\n'
module VGA_Test_Patterns_Top
  (input  clk,
   input  i_UART_RX,
   output o_UART_TX,
   input reset,

   output [0:6] LED_out,
   output [3:0] Anode_Activate,
     

   output o_VGA_HSync,
   output o_VGA_VSync,
   output o_VGA_Red_0,
   output o_VGA_Red_1,
   output o_VGA_Red_2,
   output o_VGA_Red_3,
   output o_VGA_Grn_0,
   output o_VGA_Grn_1,
   output o_VGA_Grn_2,
   output o_VGA_Grn_3,
   output o_VGA_Blu_0,
   output o_VGA_Blu_1,
   output o_VGA_Blu_2,
   output o_VGA_Blu_3    
   );
    

  parameter c_VIDEO_WIDTH = 4;
  parameter c_TOTAL_COLS  = 800;
  parameter c_TOTAL_ROWS  = 525;
  parameter c_ACTIVE_COLS = 640;
  parameter c_ACTIVE_ROWS = 480;
   
  wire w_RX_DV;
  wire [7:0] w_RX_Byte;
  wire w_TX_Active, w_TX_Serial;

  wire divided_clk;
   
  reg [3:0] r_TP_Index = 0;
 

  wire [c_VIDEO_WIDTH-1:0] w_Red_Video_TP, w_Red_Video_Porch;
  wire [c_VIDEO_WIDTH-1:0] w_Grn_Video_TP, w_Grn_Video_Porch;
  wire [c_VIDEO_WIDTH-1:0] w_Blu_Video_TP, w_Blu_Video_Porch;

  clock_divider clock_wrapper(
    .clk(clk),.divided_clk(divided_clk));
   

  UART_RX #(.CLKS_PER_BIT(217)) UART_RX_Inst
  (.clk(divided_clk),
   .i_RX_Serial(i_UART_RX),
   .o_RX_DV(w_RX_DV),
   .o_RX_Byte(w_RX_Byte));
    

  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (.clk(divided_clk),
   .i_TX_DV(w_RX_DV),
   .i_TX_Byte(w_RX_Byte),
   .o_TX_Active(w_TX_Active),
   .o_TX_Serial(w_TX_Serial),
   .o_TX_Done());
   

  assign o_UART_TX = w_TX_Active ? w_TX_Serial : 1'b1; 
   
   

  Seven_segment_LED_Display_Controller sven_seg_con
  (.clk(clk),
   .reset(reset),
   .digits(w_RX_Byte[7:0]),
   .Anode_Activate(Anode_Activate),
   .LED_out(LED_out));
    
   





  always @(posedge divided_clk)
  begin
    if (w_RX_DV == 1'b1)
      r_TP_Index <= w_RX_Byte[3:0];
  end
   

  VGA_Sync_Pulses #(.TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS)) VGA_Sync_Pulses_Inst 
  (.clk(divided_clk),
   .o_HSync(w_HSync_Start),
   .o_VSync(w_VSync_Start),
   .o_Col_Count(),
   .o_Row_Count()
  );
   
   

  Test_Pattern_Gen  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                      .TOTAL_COLS(c_TOTAL_COLS),
                      .TOTAL_ROWS(c_TOTAL_ROWS),
                      .ACTIVE_COLS(c_ACTIVE_COLS),
                      .ACTIVE_ROWS(c_ACTIVE_ROWS))
  Test_Pattern_Gen_Inst
   (.clk(divided_clk),
    .i_Pattern(r_TP_Index),
    .i_HSync(w_HSync_Start),
    .i_VSync(w_VSync_Start),
    .o_HSync(w_HSync_TP),
    .o_VSync(w_VSync_TP),
    .o_Red_Video(w_Red_Video_TP),
    .o_Grn_Video(w_Grn_Video_TP),
    .o_Blu_Video(w_Blu_Video_TP));
     
  VGA_Sync_Porch  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                    .TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS))
  VGA_Sync_Porch_Inst
   (.clk(divided_clk),
    .i_HSync(w_HSync_TP),
    .i_VSync(w_VSync_TP),
    .i_Red_Video(w_Red_Video_TP),
    .i_Grn_Video(w_Grn_Video_TP),
    .i_Blu_Video(w_Blu_Video_TP),
    .o_HSync(w_HSync_Porch),
    .o_VSync(w_VSync_Porch),
    .o_Red_Video(w_Red_Video_Porch),
    .o_Grn_Video(w_Grn_Video_Porch),
    .o_Blu_Video(w_Blu_Video_Porch));
       
  assign o_VGA_HSync = w_HSync_Porch;
  assign o_VGA_VSync = w_VSync_Porch;
       
  assign o_VGA_Red_0 = w_Red_Video_Porch[0];
  assign o_VGA_Red_1 = w_Red_Video_Porch[1];
  assign o_VGA_Red_2 = w_Red_Video_Porch[2];
  assign o_VGA_Red_3 = w_Red_Video_Porch[3];
   
  assign o_VGA_Grn_0 = w_Grn_Video_Porch[0];
  assign o_VGA_Grn_1 = w_Grn_Video_Porch[1];
  assign o_VGA_Grn_2 = w_Grn_Video_Porch[2];
  assign o_VGA_Grn_3 = w_Grn_Video_Porch[3];
 
  assign o_VGA_Blu_0 = w_Blu_Video_Porch[0];
  assign o_VGA_Blu_1 = w_Blu_Video_Porch[1];
  assign o_VGA_Blu_2 = w_Blu_Video_Porch[2];
  assign o_VGA_Blu_3 = w_Blu_Video_Porch[3];
   
endmodule
module VGA_Test_Patterns_Top
  (input  clk,
   input  i_UART_RX,
   output o_UART_TX,
   input reset,

   output [0:6] LED_out,
   output [3:0] Anode_Activate,
     

   output o_VGA_HSync,
   output o_VGA_VSync,
   output o_VGA_Red_0,
   output o_VGA_Red_1,
   output o_VGA_Red_2,
   output o_VGA_Red_3,
   output o_VGA_Grn_0,
   output o_VGA_Grn_1,
   output o_VGA_Grn_2,
   output o_VGA_Grn_3,
   output o_VGA_Blu_0,
   output o_VGA_Blu_1,
   output o_VGA_Blu_2,
   output o_VGA_Blu_3    
   );

    

  parameter c_VIDEO_WIDTH = 4;
  parameter c_TOTAL_COLS  = 800;
  parameter c_TOTAL_ROWS  = 525;
  parameter c_ACTIVE_COLS = 640;
  parameter c_ACTIVE_ROWS = 480;
   
  wire w_RX_DV;
  wire [7:0] w_RX_Byte;
  wire w_TX_Active, w_TX_Serial;

  wire divided_clk;
   
  reg [3:0] r_TP_Index = 0;
 

  wire [c_VIDEO_WIDTH-1:0] w_Red_Video_TP, w_Red_Video_Porch;
  wire [c_VIDEO_WIDTH-1:0] w_Grn_Video_TP, w_Grn_Video_Porch;
  wire [c_VIDEO_WIDTH-1:0] w_Blu_Video_TP, w_Blu_Video_Porch;

  clock_divider clock_wrapper(
    .clk(clk),.divided_clk(divided_clk));
   

  UART_RX #(.CLKS_PER_BIT(217)) UART_RX_Inst
  (.clk(divided_clk),
   .i_RX_Serial(i_UART_RX),
   .o_RX_DV(w_RX_DV),
   .o_RX_Byte(w_RX_Byte));
    

  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (.clk(divided_clk),
   .i_TX_DV(w_RX_DV),
   .i_TX_Byte(w_RX_Byte),
   .o_TX_Active(w_TX_Active),
   .o_TX_Serial(w_TX_Serial),
   .o_TX_Done());
   

  assign o_UART_TX = w_TX_Active ? w_TX_Serial : 1'b1; 
   
   

  Seven_segment_LED_Display_Controller sven_seg_con
  (.clk(clk),
   .reset(reset),
   .digits(w_RX_Byte[7:0]),
   .Anode_Activate(Anode_Activate),
   .LED_out(LED_out));
    
   





  always @(posedge divided_clk)
  begin
    if (w_RX_DV == 1'b1)
      r_TP_Index <= w_RX_Byte[3:0];
  end
   

  VGA_Sync_Pulses #(.TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS)) VGA_Sync_Pulses_Inst 
  (.clk(divided_clk),
   .o_HSync(w_HSync_Start),
   .o_VSync(w_VSync_Start),
   .o_Col_Count(),
   .o_Row_Count()
  );
   
   

  Test_Pattern_Gen  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                      .TOTAL_COLS(c_TOTAL_COLS),
                      .TOTAL_ROWS(c_TOTAL_ROWS),
                      .ACTIVE_COLS(c_ACTIVE_COLS),
                      .ACTIVE_ROWS(c_ACTIVE_ROWS))
  Test_Pattern_Gen_Inst
   (.clk(divided_clk),
    .i_Pattern(r_TP_Index),
    .i_HSync(w_HSync_Start),
    .i_VSync(w_VSync_Start),
    .o_HSync(w_HSync_TP),
    .o_VSync(w_VSync_TP),
    .o_Red_Video(w_Red_Video_TP),
    .o_Grn_Video(w_Grn_Video_TP),
    .o_Blu_Video(w_Blu_Video_TP));
     
  VGA_Sync_Porch  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                    .TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS))
  VGA_Sync_Porch_Inst
   (.clk(divided_clk),
    .i_HSync(w_HSync_TP),
    .i_VSync(w_VSync_TP),
    .i_Red_Video(w_Red_Video_TP),
    .i_Grn_Video(w_Grn_Video_TP),
    .i_Blu_Video(w_Blu_Video_TP),
    .o_HSync(w_HSync_Porch),
    .o_VSync(w_VSync_Porch),
    .o_Red_Video(w_Red_Video_Porch),
    .o_Grn_Video(w_Grn_Video_Porch),
    .o_Blu_Video(w_Blu_Video_Porch));
       
  assign o_VGA_HSync = w_HSync_Porch;
  assign o_VGA_VSync = w_VSync_Porch;
       
  assign o_VGA_Red_0 = w_Red_Video_Porch[0];
  assign o_VGA_Red_1 = w_Red_Video_Porch[1];
  assign o_VGA_Red_2 = w_Red_Video_Porch[2];
  assign o_VGA_Red_3 = w_Red_Video_Porch[3];
   
  assign o_VGA_Grn_0 = w_Grn_Video_Porch[0];
  assign o_VGA_Grn_1 = w_Grn_Video_Porch[1];
  assign o_VGA_Grn_2 = w_Grn_Video_Porch[2];
  assign o_VGA_Grn_3 = w_Grn_Video_Porch[3];
 
  assign o_VGA_Blu_0 = w_Blu_Video_Porch[0];
  assign o_VGA_Blu_1 = w_Blu_Video_Porch[1];
  assign o_VGA_Blu_2 = w_Blu_Video_Porch[2];
  assign o_VGA_Blu_3 = w_Blu_Video_Porch[3];
   
endmodule