data/full_repos/permissive/505451992/PWM_Generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_Generator.v:20: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                       : ... In instance PWM_Generator\n        counter<= 10\'d0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_Generator.v:31: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance PWM_Generator\n        pwm <= 2\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_Generator.v:35: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                       : ... In instance PWM_Generator\n        counter <= 10\'d0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_Generator.v:28: Operator LT expects 11 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                       : ... In instance PWM_Generator\n    else if(counter < 10\'d1023)  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/505451992/PWM_Generator.v:23: Operator LT expects 11 bits on the RHS, but RHS\'s VARREF \'P\' generates 10 bits.\n                                                                       : ... In instance PWM_Generator\n    else if(counter < P)  \n                    ^\n%Error: Exiting due to 5 warning(s)\n'
module PWM_Generator(
input reset,
input CLK,

input [9:0] Position,

output reg pwm
    );
    
  reg [10:0] counter;
  reg [9:0] P;
  
    
    
 always@(posedge CLK or posedge reset)    
    if(reset) begin
        counter<= 10'd0;
        P <= 10'd0;
      end
    else if(counter < P)
        begin
        counter <= counter + 10'd1;
        pwm <= 1;
        end
    else if(counter < 10'd1023)
        begin
        counter <= counter + 10'd1;
        pwm <= 2'b0;
        end
    else
        begin
        counter <= 10'd0;
        P <= Position;
        end
    
    
    
endmodule
module PWM_Generator(
input reset,
input CLK,

input [9:0] Position,

output reg pwm
    );

    
  reg [10:0] counter;
  reg [9:0] P;
  
    
    
 always@(posedge CLK or posedge reset)    
    if(reset) begin
        counter<= 10'd0;
        P <= 10'd0;
      end
    else if(counter < P)
        begin
        counter <= counter + 10'd1;
        pwm <= 1;
        end
    else if(counter < 10'd1023)
        begin
        counter <= counter + 10'd1;
        pwm <= 2'b0;
        end
    else
        begin
        counter <= 10'd0;
        P <= Position;
        end
    
    
    
endmodule