data/full_repos/permissive/515851157/verilog/rtl/simple.v
1: b"%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:76: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:77: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module mem_block #(
    parameter BITS =32
)(
    input clk,
    input [5:0] addr,
    input rd_en,
    input wr_en,



    input [7:0] wdata,



    output [7:0] rout_data

);


    reg [7:0] rout_data;
    
    reg [7:0] mem [64:0];

    always @(posedge clk) begin
        
        if(wr_en==1'b1 && rd_en==1'b0)
        begin
         mem[addr]=wdata;
        end
        else if (wr_en==1'b0 && rd_en==1'b1)
        begin
         rout_data=mem[addr];
        end
        
 end

endmodule
module mem_block #(
    parameter BITS =32
)(
    input clk,
    input [5:0] addr,
    input rd_en,
    input wr_en,



    input [7:0] wdata,



    output [7:0] rout_data

);



    reg [7:0] rout_data;
    
    reg [7:0] mem [64:0];

    always @(posedge clk) begin
        
        if(wr_en==1'b1 && rd_en==1'b0)
        begin
         mem[addr]=wdata;
        end
        else if (wr_en==1'b0 && rd_en==1'b1)
        begin
         rout_data=mem[addr];
        end
        
 end

endmodule