data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/genclock4d86.v
data/verilator_xmls/68ca890e-337a-4e86-877e-480ebb984545.xml
module genclock4d86
    (
     rst_,
     iclk19,
     frmsync,
     oclk4d86
     );




input           rst_;
input           iclk19;
input           frmsync;
output          oclk4d86;




reg             frmsync_rt;
always @(negedge iclk19 or negedge rst_)
    begin
    if (!rst_)  frmsync_rt  <= 1'b0;
    else if(frmsync_rt) frmsync_rt <= 1'b0;
    else        frmsync_rt  <= frmsync;
    end

reg [1:0] cntph;
always @(posedge iclk19 or negedge rst_)
    begin
    if (!rst_)              cntph <= 2'd0;
    else if (frmsync_rt)    cntph <= 2'd0;
    else                    cntph <= cntph + 1'b1;
    end

wire            oclk4d86;
assign oclk4d86 = cntph[1];

endmodule
module genclock4d86
    (
     rst_,
     iclk19,
     frmsync,
     oclk4d86
     );





input           rst_;
input           iclk19;
input           frmsync;
output          oclk4d86;




reg             frmsync_rt;
always @(negedge iclk19 or negedge rst_)
    begin
    if (!rst_)  frmsync_rt  <= 1'b0;
    else if(frmsync_rt) frmsync_rt <= 1'b0;
    else        frmsync_rt  <= frmsync;
    end

reg [1:0] cntph;
always @(posedge iclk19 or negedge rst_)
    begin
    if (!rst_)              cntph <= 2'd0;
    else if (frmsync_rt)    cntph <= 2'd0;
    else                    cntph <= cntph + 1'b1;
    end

wire            oclk4d86;
assign oclk4d86 = cntph[1];

endmodule