data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU.v:21: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                     : ... In instance ALU\n            ropc <=opa+opb;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU.v:21: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                     : ... In instance ALU\n            ropc <=opa+opb;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU.v:26: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                     : ... In instance ALU\n            ropc= opa-opb;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU.v:26: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                     : ... In instance ALU\n            ropc= opa-opb;\n                     ^\n%Error: Exiting due to 4 warning(s)\n'
module ALU(
    input [3:0] opa,
    input [3:0] opb,
    input [1:0] asm,
    output [7:0] opc
    );
    reg [7:0] ropc=0;
    always@(*)
    begin
    case(asm)
            2'b00: 
            begin
            ropc <= 0;
            end
            
            2'b01:
            begin
            ropc <=opa+opb;
            end 
            
            2'b10:
            begin
            ropc= opa-opb;
            end 
            
            2'b11:
            begin
             ropc = opa * opb;
            end 
           
        endcase
   end 
   assign opc = ropc;
endmodule
module ALU(
    input [3:0] opa,
    input [3:0] opb,
    input [1:0] asm,
    output [7:0] opc
    );

    reg [7:0] ropc=0;
    always@(*)
    begin
    case(asm)
            2'b00: 
            begin
            ropc <= 0;
            end
            
            2'b01:
            begin
            ropc <=opa+opb;
            end 
            
            2'b10:
            begin
            ropc= opa-opb;
            end 
            
            2'b11:
            begin
             ropc = opa * opb;
            end 
           
        endcase
   end 
   assign opc = ropc;
endmodule