data/full_repos/permissive/421030651/src/peri/dma.sv
1: b'%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:1: Cannot find include file: dma_mmap.h\n`include "dma_mmap.h" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/dma_mmap.h\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/dma_mmap.h.v\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/dma_mmap.h.sv\n             dma_mmap.h\n             dma_mmap.h.v\n             dma_mmap.h.sv\n             obj_dir/dma_mmap.h\n             obj_dir/dma_mmap.h.v\n             obj_dir/dma_mmap.h.sv\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:66: Define or directive not defined: \'`DMA_SRC\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_SRC) begin\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:66: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_SRC) begin\n                                                        ^\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:75: Define or directive not defined: \'`DMA_DEST\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_DEST) begin\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:84: Define or directive not defined: \'`DMA_LEN\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_LEN) begin\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:126: Define or directive not defined: \'`DMA_CON\'\n    else if (~dma_busy && apb_wr && s_apb_intf.paddr[7:0] == `DMA_CON) begin\n                                                             ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (~dma_busy && apb_wr && s_apb_intf.paddr[7:0] == `DMA_CON) begin\n                                                                     ^\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:135: syntax error, unexpected else\n    else if (dma_con_err || dma_done || ~wdt_rst_b) begin\n    ^~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:148: Define or directive not defined: \'`DMA_IE\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_IE) begin\n                                                ^~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:160: Define or directive not defined: \'`DMA_IC\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_IC) begin\n                                                ^~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:168: Define or directive not defined: \'`DMA_SRC\'\n        `DMA_SRC:     prdata_t = dma_src;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:168: syntax error, unexpected \':\', expecting endcase\n        `DMA_SRC:     prdata_t = dma_src;\n                ^\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:169: Define or directive not defined: \'`DMA_DEST\'\n        `DMA_DEST:    prdata_t = dma_dest;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:170: Define or directive not defined: \'`DMA_LEN\'\n        `DMA_LEN:     prdata_t = dma_len;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:171: Define or directive not defined: \'`DMA_CON\'\n        `DMA_CON:     prdata_t = dma_con;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:172: Define or directive not defined: \'`DMA_IE\'\n        `DMA_IE:      prdata_t = {31\'b0, dma_ie};\n        ^~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:173: Define or directive not defined: \'`DMA_IP\'\n        `DMA_IP:      prdata_t = {31\'b0, dma_ip};\n        ^~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:174: Define or directive not defined: \'`DMA_IC\'\n        `DMA_IC:      prdata_t = {31\'b0, dma_ip};\n        ^~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:175: Define or directive not defined: \'`DMA_WDT_CNT\'\n        `DMA_WDT_CNT: prdata_t = {wdt_timeout, wdt_cnt_config[30:0]};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:547: Define or directive not defined: \'`DMA_WDT_CNT\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_WDT_CNT) begin\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:547: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_WDT_CNT) begin\n                                                            ^\n%Error: data/full_repos/permissive/421030651/src/peri/dma.sv:559: Define or directive not defined: \'`DMA_WDT_CNT\'\n    else if (apb_wr && s_apb_intf.paddr[7:0] == `DMA_WDT_CNT) begin\n                                                ^~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module dma_fifo (
    input                            clk,
    input                            rstn,

    input                            push,
    input        [              1:0] wsize,
    input        [             31:0] wdata,
    output logic                     full,
    output logic [`DMA_FIFO_DEPTH:0] cnt,

    input                            pop,
    input        [              1:0] rsize,
    output logic [             31:0] rdata,
    output logic                     empty

);


logic [                7:0] buff [`DMA_FIFO_SIZE];
logic [`DMA_FIFO_DEPTH-1:0] rptr;
logic [`DMA_FIFO_DEPTH-1:0] wptr;

assign empty = cnt <= rsize;
assign full  = cnt >= (({{`DMA_FIFO_DEPTH{1'b0}}, 1'b1} << (`DMA_FIFO_DEPTH)) - wsize);
assign rdata = {{8{rsize >= 2'h3}} & buff[rptr + `DMA_FIFO_DEPTH'h3],
                {8{rsize >= 2'h2}} & buff[rptr + `DMA_FIFO_DEPTH'h2],
                {8{rsize >= 2'h1}} & buff[rptr + `DMA_FIFO_DEPTH'h1],
                {8{rsize >= 2'h0}} & buff[rptr + `DMA_FIFO_DEPTH'h0]};

always_ff @(posedge clk or negedge rstn) begin: reg_wptr
    if (~rstn) begin
        wptr <= `DMA_FIFO_DEPTH'b0;
    end
    else if (push && ~full) begin
        wptr <= wptr + {{`DMA_FIFO_DEPTH-2{1'b0}}, wsize} + `DMA_FIFO_DEPTH'b1;
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_rptr
    if (~rstn) begin
        rptr <= `DMA_FIFO_DEPTH'b0;
    end
    else if (pop && ~empty) begin
        rptr <= rptr + {{`DMA_FIFO_DEPTH-2{1'b0}}, rsize} + `DMA_FIFO_DEPTH'b1;
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_cnt
    if (~rstn) begin
        cnt  <= {`DMA_FIFO_DEPTH+1{1'b0}};
    end
    else begin
        cnt  <= cnt +
                ({`DMA_FIFO_DEPTH+1{push && ~full }} & ({{`DMA_FIFO_DEPTH-1{1'b0}}, wsize} + {`DMA_FIFO_DEPTH'b0, 1'b1})) -
                ({`DMA_FIFO_DEPTH+1{pop  && ~empty}} & ({{`DMA_FIFO_DEPTH-1{1'b0}}, rsize} + {`DMA_FIFO_DEPTH'b0, 1'b1}));
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_buff
    integer i;
    if (~rstn) begin
        for (i = 0; i < `DMA_FIFO_SIZE; i = i + 1) begin
            buff[i] <= 8'b0;
        end
    end
    else begin
        if (push && ~full) begin
            if (wsize >= 2'h0) buff[wptr            ] <= wdata[ 0+:8];
            if (wsize >= 2'h1) buff[wptr + `DMA_FIFO_DEPTH'h1] <= wdata[ 8+:8];
            if (wsize >= 2'h2) buff[wptr + `DMA_FIFO_DEPTH'h2] <= wdata[16+:8];
            if (wsize >= 2'h3) buff[wptr + `DMA_FIFO_DEPTH'h3] <= wdata[24+:8];
        end
    end
end

endmodule
module dma_fifo (
    input                            clk,
    input                            rstn,

    input                            push,
    input        [              1:0] wsize,
    input        [             31:0] wdata,
    output logic                     full,
    output logic [`DMA_FIFO_DEPTH:0] cnt,

    input                            pop,
    input        [              1:0] rsize,
    output logic [             31:0] rdata,
    output logic                     empty

);



logic [                7:0] buff [`DMA_FIFO_SIZE];
logic [`DMA_FIFO_DEPTH-1:0] rptr;
logic [`DMA_FIFO_DEPTH-1:0] wptr;

assign empty = cnt <= rsize;
assign full  = cnt >= (({{`DMA_FIFO_DEPTH{1'b0}}, 1'b1} << (`DMA_FIFO_DEPTH)) - wsize);
assign rdata = {{8{rsize >= 2'h3}} & buff[rptr + `DMA_FIFO_DEPTH'h3],
                {8{rsize >= 2'h2}} & buff[rptr + `DMA_FIFO_DEPTH'h2],
                {8{rsize >= 2'h1}} & buff[rptr + `DMA_FIFO_DEPTH'h1],
                {8{rsize >= 2'h0}} & buff[rptr + `DMA_FIFO_DEPTH'h0]};

always_ff @(posedge clk or negedge rstn) begin: reg_wptr
    if (~rstn) begin
        wptr <= `DMA_FIFO_DEPTH'b0;
    end
    else if (push && ~full) begin
        wptr <= wptr + {{`DMA_FIFO_DEPTH-2{1'b0}}, wsize} + `DMA_FIFO_DEPTH'b1;
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_rptr
    if (~rstn) begin
        rptr <= `DMA_FIFO_DEPTH'b0;
    end
    else if (pop && ~empty) begin
        rptr <= rptr + {{`DMA_FIFO_DEPTH-2{1'b0}}, rsize} + `DMA_FIFO_DEPTH'b1;
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_cnt
    if (~rstn) begin
        cnt  <= {`DMA_FIFO_DEPTH+1{1'b0}};
    end
    else begin
        cnt  <= cnt +
                ({`DMA_FIFO_DEPTH+1{push && ~full }} & ({{`DMA_FIFO_DEPTH-1{1'b0}}, wsize} + {`DMA_FIFO_DEPTH'b0, 1'b1})) -
                ({`DMA_FIFO_DEPTH+1{pop  && ~empty}} & ({{`DMA_FIFO_DEPTH-1{1'b0}}, rsize} + {`DMA_FIFO_DEPTH'b0, 1'b1}));
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_buff
    integer i;
    if (~rstn) begin
        for (i = 0; i < `DMA_FIFO_SIZE; i = i + 1) begin
            buff[i] <= 8'b0;
        end
    end
    else begin
        if (push && ~full) begin
            if (wsize >= 2'h0) buff[wptr            ] <= wdata[ 0+:8];
            if (wsize >= 2'h1) buff[wptr + `DMA_FIFO_DEPTH'h1] <= wdata[ 8+:8];
            if (wsize >= 2'h2) buff[wptr + `DMA_FIFO_DEPTH'h2] <= wdata[16+:8];
            if (wsize >= 2'h3) buff[wptr + `DMA_FIFO_DEPTH'h3] <= wdata[24+:8];
        end
    end
end

endmodule