data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:12: Operator VAR \'WR_FDMA_BURST_LEN\' expects 32 bits on the Initial value, but Initial value\'s CONST \'16\'h40\' generates 16 bits.\n                                                                                           : ... In instance dma_if\n    parameter  integer WR_FDMA_BURST_LEN     = 16\'d64,               \n                       ^~~~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:16: Operator VAR \'RD_FDMA_BURST_LEN\' expects 32 bits on the Initial value, but Initial value\'s CONST \'16\'h100\' generates 16 bits.\n                                                                                           : ... In instance dma_if\n    parameter  integer RD_FDMA_BURST_LEN     = 16\'d256,\n                       ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:76: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'wr_data_cnt_ddr\' generates 7 bits.\n                                                                                           : ... In instance dma_if\n        if (wr_data_cnt_ddr > WR_FDMA_BURST_LEN * 2 - 1) begin     \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:109: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'WR_FDMA_BURST_LEN\' generates 32 bits.\n                                                                                            : ... In instance dma_if\nassign fdma_wsize = WR_FDMA_BURST_LEN;             \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:110: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'RD_FDMA_BURST_LEN\' generates 32 bits.\n                                                                                            : ... In instance dma_if\nassign fdma_rsize = RD_FDMA_BURST_LEN;              \n                  ^\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma/dma_if.v:211: Cannot find file containing module: \'fifo2ddr\'\nfifo2ddr  u_fifo2ddr (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma,data/full_repos/permissive/507203156/fifo2ddr\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma,data/full_repos/permissive/507203156/fifo2ddr.v\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/dma,data/full_repos/permissive/507203156/fifo2ddr.sv\n             fifo2ddr\n             fifo2ddr.v\n             fifo2ddr.sv\n             obj_dir/fifo2ddr\n             obj_dir/fifo2ddr.v\n             obj_dir/fifo2ddr.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module dma_if#
(
    parameter  integer WR_MEM_SIZE  	   	 = 32'd512*512,
    parameter  integer WR_MEM_ADDR_OFFSET    = 32'h500000,
    parameter  integer WR_FDMA_BURST_LEN     = 16'd64,

    parameter  integer RD_MEM_SIZE           = 32'd512*512,
    parameter  integer RD_MEM_ADDR_OFFSET    = 32'h300000,  
    parameter  integer RD_FDMA_BURST_LEN     = 16'd256,
    parameter  integer M_AXI_ADDR_WIDTH      = 32,
    parameter  integer M_AXI_DATA_WIDTH      = 128
)
(
    input 	 wire   							fdma_clk			,
    input 	 wire   							fdma_rstn			,


    input    wire                               load_cmd              ,
    input    wire [63:0]                         din                 ,
    input    wire                                din_en              ,


    output   wire [M_AXI_ADDR_WIDTH-1 : 0]      fdma_waddr          ,
    output   reg                                fdma_wareq          ,
    output   wire [15 : 0]                      fdma_wsize          , 
    input                                       fdma_wbusy          ,
    output   wire [M_AXI_DATA_WIDTH-1 :0]       fdma_wdata			,
    input  	 wire                               fdma_wvalid         ,
    output	 wire                               fdma_wready			,

    output   wire [M_AXI_ADDR_WIDTH-1 : 0]      fdma_raddr          ,
    output   reg                                fdma_rareq          ,
    output   wire [15 : 0]                      fdma_rsize          ,                                     
    input                                       fdma_rbusy          ,

    input    wire [M_AXI_DATA_WIDTH-1 :0]       fdma_rdata			,
    input    wire                               fdma_rvalid         ,
    
    output	 wire                               fdma_rready			,

    output   wire  [2  :0] 						fdma_T_S			
);


wire [6:0]wr_data_cnt_ddr;
wire [5:0]rd_data_cnt_ddr;
wire empty_ddr;
wire full_ddr;





reg load_cmd_d = 1'b0;
always @(posedge fdma_clk) begin
    load_cmd_d <= load_cmd;
end

reg wr_cmd, wr_cmd_d;
always @(posedge fdma_clk or negedge fdma_rstn) begin
    if(~fdma_rstn) begin
        wr_cmd <= 1'b0;
        wr_cmd_d <= 1'b0;
    end
    else begin
        wr_cmd_d <= wr_cmd;


        if (wr_data_cnt_ddr > WR_FDMA_BURST_LEN * 2 - 1) begin     
            wr_cmd <= 1'b1;
        end
        else
            wr_cmd <= 1'b0;
    end
end

assign fdma_wready = 1'b1;
assign fdma_rready = 1'b1;




localparam RD_ADDR_INC = RD_FDMA_BURST_LEN * 16;
localparam WR_ADDR_INC = WR_FDMA_BURST_LEN * 16;

localparam IDLE   = 0;
localparam WRITE1 = 1;
localparam WRITE2 = 2;
localparam READ1  = 3;
localparam READ2  = 4;

reg [31: 0] fdma_waddr_r;
reg [31: 0] fdma_raddr_r;
reg [2  :0] T_S = IDLE;



assign fdma_T_S = T_S;
assign fdma_waddr = fdma_waddr_r + WR_MEM_ADDR_OFFSET;
assign fdma_raddr = fdma_raddr_r + RD_MEM_ADDR_OFFSET;

assign fdma_wsize = WR_FDMA_BURST_LEN;             
assign fdma_rsize = RD_FDMA_BURST_LEN;

  

reg [8:0] rst_cnt = 0;
always @(posedge fdma_clk)
	if(fdma_rstn==1'b0)
		rst_cnt <= 9'd0;
	else if(rst_cnt[8] == 1'b0 )
         rst_cnt <= rst_cnt + 1'b1;
     else 
         rst_cnt <= rst_cnt;




always @(posedge fdma_clk)begin
    if(rst_cnt[8] == 1'b0)begin
        T_S <= IDLE;
        fdma_wareq  <= 1'b0; 
        fdma_rareq  <= 1'b0; 
        fdma_waddr_r <= 'd0;    
        fdma_raddr_r <= 'd0;
    end 
    else begin
        case(T_S)    
        IDLE:begin
            if(wr_cmd & ~wr_cmd_d)
                T_S <= WRITE1;
            else if(load_cmd & ~load_cmd_d)
                T_S <= READ1;
            else
                T_S <= IDLE;
        end

        WRITE1:begin
            if(fdma_waddr_r >= WR_MEM_SIZE) begin
                fdma_waddr_r<=0;
                T_S <= IDLE;
            end
            else begin
                if(!fdma_wbusy)begin
                    fdma_wareq  <= 1'b1; 
                end

                if(fdma_wareq && fdma_wbusy)begin
                    fdma_wareq  <= 1'b0; 
                    T_S         <= WRITE2;
                end
            end
        end

        WRITE2:begin
            if(!fdma_wbusy) begin
                fdma_waddr_r  <= fdma_waddr_r + WR_ADDR_INC;
                T_S <= WRITE1;
            end 
            else if(fdma_wvalid) begin

            end
        end

        READ1:begin
            if(fdma_raddr_r >= RD_MEM_SIZE) begin
                fdma_raddr_r<=0;
                T_S <= IDLE;
            end
            else begin
                if(!fdma_rbusy)begin
                    fdma_rareq  <= 1'b1; 
                end
                if(fdma_rareq && fdma_rbusy)begin
                    fdma_rareq  <= 1'b0; 
                    T_S         <= READ2;
                end 
            end
        end
        
        READ2:begin
            if(!fdma_rbusy) begin
                T_S <= READ1;
                fdma_raddr_r  <= fdma_raddr_r + RD_ADDR_INC;
            end 
            else if(fdma_rvalid) begin

            end
        end   
        default:
            T_S <= IDLE;     
        endcase
    end
  end

wire fifo_rst;
assign fifo_rst = (T_S==IDLE)?1'b0:1'b1;



fifo2ddr  u_fifo2ddr (
    .clk                     ( fdma_clk                ),
    .rst_n                   ( fifo_rst                ),

    .wen                     ( din_en               ),
    .wdata                   ( din        [63:0]     ),

    .ren                     ( fdma_wvalid          ),
    .rdata                   ( fdma_wdata   [127:0] ),

    .wr_data_cnt             ( wr_data_cnt_ddr  [6:0]  ),
    .rd_data_cnt             ( rd_data_cnt_ddr  [5:0]  ),

    .rempty                  ( empty_ddr               ),
    .wfull                   ( full_ddr                )
);





endmodule
module dma_if#
(
    parameter  integer WR_MEM_SIZE  	   	 = 32'd512*512,
    parameter  integer WR_MEM_ADDR_OFFSET    = 32'h500000,
    parameter  integer WR_FDMA_BURST_LEN     = 16'd64,

    parameter  integer RD_MEM_SIZE           = 32'd512*512,
    parameter  integer RD_MEM_ADDR_OFFSET    = 32'h300000,  
    parameter  integer RD_FDMA_BURST_LEN     = 16'd256,
    parameter  integer M_AXI_ADDR_WIDTH      = 32,
    parameter  integer M_AXI_DATA_WIDTH      = 128
)
(
    input 	 wire   							fdma_clk			,
    input 	 wire   							fdma_rstn			,


    input    wire                               load_cmd              ,
    input    wire [63:0]                         din                 ,
    input    wire                                din_en              ,


    output   wire [M_AXI_ADDR_WIDTH-1 : 0]      fdma_waddr          ,
    output   reg                                fdma_wareq          ,
    output   wire [15 : 0]                      fdma_wsize          , 
    input                                       fdma_wbusy          ,
    output   wire [M_AXI_DATA_WIDTH-1 :0]       fdma_wdata			,
    input  	 wire                               fdma_wvalid         ,
    output	 wire                               fdma_wready			,

    output   wire [M_AXI_ADDR_WIDTH-1 : 0]      fdma_raddr          ,
    output   reg                                fdma_rareq          ,
    output   wire [15 : 0]                      fdma_rsize          ,                                     
    input                                       fdma_rbusy          ,

    input    wire [M_AXI_DATA_WIDTH-1 :0]       fdma_rdata			,
    input    wire                               fdma_rvalid         ,
    
    output	 wire                               fdma_rready			,

    output   wire  [2  :0] 						fdma_T_S			
);



wire [6:0]wr_data_cnt_ddr;
wire [5:0]rd_data_cnt_ddr;
wire empty_ddr;
wire full_ddr;





reg load_cmd_d = 1'b0;
always @(posedge fdma_clk) begin
    load_cmd_d <= load_cmd;
end

reg wr_cmd, wr_cmd_d;
always @(posedge fdma_clk or negedge fdma_rstn) begin
    if(~fdma_rstn) begin
        wr_cmd <= 1'b0;
        wr_cmd_d <= 1'b0;
    end
    else begin
        wr_cmd_d <= wr_cmd;


        if (wr_data_cnt_ddr > WR_FDMA_BURST_LEN * 2 - 1) begin     
            wr_cmd <= 1'b1;
        end
        else
            wr_cmd <= 1'b0;
    end
end

assign fdma_wready = 1'b1;
assign fdma_rready = 1'b1;




localparam RD_ADDR_INC = RD_FDMA_BURST_LEN * 16;
localparam WR_ADDR_INC = WR_FDMA_BURST_LEN * 16;

localparam IDLE   = 0;
localparam WRITE1 = 1;
localparam WRITE2 = 2;
localparam READ1  = 3;
localparam READ2  = 4;

reg [31: 0] fdma_waddr_r;
reg [31: 0] fdma_raddr_r;
reg [2  :0] T_S = IDLE;



assign fdma_T_S = T_S;
assign fdma_waddr = fdma_waddr_r + WR_MEM_ADDR_OFFSET;
assign fdma_raddr = fdma_raddr_r + RD_MEM_ADDR_OFFSET;

assign fdma_wsize = WR_FDMA_BURST_LEN;             
assign fdma_rsize = RD_FDMA_BURST_LEN;

  

reg [8:0] rst_cnt = 0;
always @(posedge fdma_clk)
	if(fdma_rstn==1'b0)
		rst_cnt <= 9'd0;
	else if(rst_cnt[8] == 1'b0 )
         rst_cnt <= rst_cnt + 1'b1;
     else 
         rst_cnt <= rst_cnt;




always @(posedge fdma_clk)begin
    if(rst_cnt[8] == 1'b0)begin
        T_S <= IDLE;
        fdma_wareq  <= 1'b0; 
        fdma_rareq  <= 1'b0; 
        fdma_waddr_r <= 'd0;    
        fdma_raddr_r <= 'd0;
    end 
    else begin
        case(T_S)    
        IDLE:begin
            if(wr_cmd & ~wr_cmd_d)
                T_S <= WRITE1;
            else if(load_cmd & ~load_cmd_d)
                T_S <= READ1;
            else
                T_S <= IDLE;
        end

        WRITE1:begin
            if(fdma_waddr_r >= WR_MEM_SIZE) begin
                fdma_waddr_r<=0;
                T_S <= IDLE;
            end
            else begin
                if(!fdma_wbusy)begin
                    fdma_wareq  <= 1'b1; 
                end

                if(fdma_wareq && fdma_wbusy)begin
                    fdma_wareq  <= 1'b0; 
                    T_S         <= WRITE2;
                end
            end
        end

        WRITE2:begin
            if(!fdma_wbusy) begin
                fdma_waddr_r  <= fdma_waddr_r + WR_ADDR_INC;
                T_S <= WRITE1;
            end 
            else if(fdma_wvalid) begin

            end
        end

        READ1:begin
            if(fdma_raddr_r >= RD_MEM_SIZE) begin
                fdma_raddr_r<=0;
                T_S <= IDLE;
            end
            else begin
                if(!fdma_rbusy)begin
                    fdma_rareq  <= 1'b1; 
                end
                if(fdma_rareq && fdma_rbusy)begin
                    fdma_rareq  <= 1'b0; 
                    T_S         <= READ2;
                end 
            end
        end
        
        READ2:begin
            if(!fdma_rbusy) begin
                T_S <= READ1;
                fdma_raddr_r  <= fdma_raddr_r + RD_ADDR_INC;
            end 
            else if(fdma_rvalid) begin

            end
        end   
        default:
            T_S <= IDLE;     
        endcase
    end
  end

wire fifo_rst;
assign fifo_rst = (T_S==IDLE)?1'b0:1'b1;



fifo2ddr  u_fifo2ddr (
    .clk                     ( fdma_clk                ),
    .rst_n                   ( fifo_rst                ),

    .wen                     ( din_en               ),
    .wdata                   ( din        [63:0]     ),

    .ren                     ( fdma_wvalid          ),
    .rdata                   ( fdma_wdata   [127:0] ),

    .wr_data_cnt             ( wr_data_cnt_ddr  [6:0]  ),
    .rd_data_cnt             ( rd_data_cnt_ddr  [5:0]  ),

    .rempty                  ( empty_ddr               ),
    .wfull                   ( full_ddr                )
);





endmodule