data/full_repos/permissive/481885440/design/digital_filter_3a/design/rtl/integrator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481885440/design/digital_filter_3a/design/rtl/integrator.v:17: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'data_in\' generates 9 bits.\n                                                                                                        : ... In instance integrator\n            data_out <= data_out + data_in;    \n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module integrator #(
    parameter WIDTH_IN = 9,
    parameter WIDTH_OUT = 18
)
(
    input wire clk,
    input wire rst_n,
    input wire unsigned [WIDTH_IN - 1 : 0] data_in,
    output reg unsigned [WIDTH_OUT - 1 : 0] data_out
);

    always @(posedge clk) begin
        if(!rst_n) begin
            data_out <= 0;
        end
        else begin
            data_out <= data_out + data_in;    
        end
    end

endmodule
module integrator #(
    parameter WIDTH_IN = 9,
    parameter WIDTH_OUT = 18
)
(
    input wire clk,
    input wire rst_n,
    input wire unsigned [WIDTH_IN - 1 : 0] data_in,
    output reg unsigned [WIDTH_OUT - 1 : 0] data_out
);


    always @(posedge clk) begin
        if(!rst_n) begin
            data_out <= 0;
        end
        else begin
            data_out <= data_out + data_in;    
        end
    end

endmodule