data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v
1: b"%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:22: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:23: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:24: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:30: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:31: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:32: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:45: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb[`MPRJ_IO_PADS-1:0] = {`MPRJ_IO_PADS{1'b0}};\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/teras_bridge_mpw5.v:45: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb[`MPRJ_IO_PADS-1:0] = {`MPRJ_IO_PADS{1'b0}};\n                                        ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module teras_bridge_mpw5 (


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb

);
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] matrix_c_out;

    wire valid;
    wire matrix_c_valid;


    assign valid = wbs_cyc_i && wbs_stb_i; 


    assign io_out[31:8] = matrix_c_out[23:0];
    assign io_out[32]   = matrix_c_valid;
    assign io_oeb[`MPRJ_IO_PADS-1:0] = {`MPRJ_IO_PADS{1'b0}};

    assign clk = wb_clk_i;
    assign rst = wb_rst_i;

    teras teras_inst (

        .clk    ( clk             ),
        .rst_n  ( ~rst            ),




        .rtr_o  ( wbs_ack_o      ),
        .rts_i  ( valid          ),

        .data_i ( wbs_dat_i      ),




        .rtr_i  ( 1'b1           ),
        .rts_o  ( matrix_c_valid ),

        .data_o ( matrix_c_out   )
    );

endmodule
module teras_bridge_mpw5 (


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb

);

    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] matrix_c_out;

    wire valid;
    wire matrix_c_valid;


    assign valid = wbs_cyc_i && wbs_stb_i; 


    assign io_out[31:8] = matrix_c_out[23:0];
    assign io_out[32]   = matrix_c_valid;
    assign io_oeb[`MPRJ_IO_PADS-1:0] = {`MPRJ_IO_PADS{1'b0}};

    assign clk = wb_clk_i;
    assign rst = wb_rst_i;

    teras teras_inst (

        .clk    ( clk             ),
        .rst_n  ( ~rst            ),




        .rtr_o  ( wbs_ack_o      ),
        .rts_i  ( valid          ),

        .data_i ( wbs_dat_i      ),




        .rtr_i  ( 1'b1           ),
        .rts_o  ( matrix_c_valid ),

        .data_o ( matrix_c_out   )
    );

endmodule