data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n            #10 $stop;   \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #5 $finish;\n            ^\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/bin_to_bcd_tb.v:32: Cannot find file containing module: \'bin_to_bcd\'\nbin_to_bcd U0(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/bin_to_bcd\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/bin_to_bcd.v\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/bin_to_bcd.sv\n             bin_to_bcd\n             bin_to_bcd.v\n             bin_to_bcd.sv\n             obj_dir/bin_to_bcd\n             obj_dir/bin_to_bcd.v\n             obj_dir/bin_to_bcd.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bin_to_bcd_tb;

reg [10:0] bin;
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire [3:0] thousands;

bin_to_bcd U0(
    .bin(bin),
    .ones(ones),
    .tens(tens),
    .hundreds(hundreds),
    .thousands(thousands)
);

integer i;
reg success_flag;

initial begin
    #10
	bin = 0;
	#10
	bin = 321;
	#10
	bin = 2020;
	#10
	bin = 1234;
	#10

	if (success_flag == 0) begin
		$display("*FAILED** TEST!");
	end 
	else begin
		$display("**PASSED** TEST!");
	end
            #10 $stop;   
            #5 $finish;
end

endmodule
module bin_to_bcd_tb;


reg [10:0] bin;
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire [3:0] thousands;

bin_to_bcd U0(
    .bin(bin),
    .ones(ones),
    .tens(tens),
    .hundreds(hundreds),
    .thousands(thousands)
);

integer i;
reg success_flag;

initial begin
    #10
	bin = 0;
	#10
	bin = 321;
	#10
	bin = 2020;
	#10
	bin = 1234;
	#10

	if (success_flag == 0) begin
		$display("*FAILED** TEST!");
	end 
	else begin
		$display("**PASSED** TEST!");
	end
            #10 $stop;   
            #5 $finish;
end

endmodule