data/full_repos/permissive/493019833/test/testcase/firrtl/EmptyChirrtlMem/sbt/EmptyChirrtlMem.v
data/verilator_xmls/7b38108e-222c-47ec-9532-1ab7cdac5b72.xml
module Queue(
  input   clock
);
endmodule
module Queue(
  input   clock
);

endmodule