data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv:44: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance multiplier\n        product <= 32\'d0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv:85: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance multiplier\n                next_product <= 32\'d0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv:90: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'repeated_add\' generates 32 bits.\n                                                                                         : ... In instance multiplier\n                    next_product = product + repeated_add;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv:97: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance multiplier\n                next_product <= 32\'d0;             \n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/multiplier.sv:103: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                          : ... In instance multiplier\n                    next_product <= 32\'d0;\n                                 ^~\n%Error: Exiting due to 5 warning(s)\n'
module multiplier
(
    input logic clk,
    input logic rst,
    input logic start,
    input logic [31:0] multiplicand,
    input logic [31:0] multiplier,
    output logic [63:0] product,
    output logic mul_resp
);


logic [31:0] repeated_add;
logic [31:0] iteration;
logic [31:0] next_iteration;
logic [63:0] next_product;
logic [31:0] stop_case;

always_comb begin
    if(multiplicand > multiplier) begin
        stop_case = multiplier - 32'd1;
        repeated_add = multiplicand;
    end
    else begin
        stop_case = multiplicand - 32'd1;
        repeated_add = multiplier;
    end

end


enum int unsigned {
    idle,
    add_shift,
    done
} state, next_state;


always_ff @(posedge clk)
begin : next_state_condition
    if(rst) begin
        state <= idle;
        iteration <= 32'd0;
        product <= 32'd0;
    end
    else begin
        state <= next_state;
        iteration <= next_iteration;
        product <= next_product;
    end
end

always_comb
begin : next_state_logic
    case(state)
        idle: begin
                if(start == 1'b1 && (multiplicand == 32'd0 || multiplier == 32'd0)) begin
                    next_state <= done;
                end
                else if(start == 1'b1)
                    next_state <= add_shift;
                else
                    next_state <= idle;
              end

        add_shift: begin
                    if(iteration == stop_case)
                        next_state <= done;
                    else
                        next_state <= add_shift;
                   end

        done: begin
                next_state <= idle;
              end
        default:;
    endcase
end

always_comb 
begin : state_output
    case(state)
        idle: begin
                next_iteration <= 32'd0;
                next_product <= 32'd0;
                mul_resp <= 1'b0;
              end
        
        add_shift: begin
                    next_product = product + repeated_add;
                    next_iteration = iteration + 32'd1;
                    mul_resp <= 1'd0;
                   end

        done: begin
                next_iteration <= 32'd0;
                next_product <= 32'd0;             
                mul_resp <= 1'b1;
              end
              
        default: begin
                    next_iteration <= 32'd0;
                    next_product <= 32'd0;
                    mul_resp <= 1'b0;
                 end
    endcase
end
endmodule
module multiplier
(
    input logic clk,
    input logic rst,
    input logic start,
    input logic [31:0] multiplicand,
    input logic [31:0] multiplier,
    output logic [63:0] product,
    output logic mul_resp
);



logic [31:0] repeated_add;
logic [31:0] iteration;
logic [31:0] next_iteration;
logic [63:0] next_product;
logic [31:0] stop_case;

always_comb begin
    if(multiplicand > multiplier) begin
        stop_case = multiplier - 32'd1;
        repeated_add = multiplicand;
    end
    else begin
        stop_case = multiplicand - 32'd1;
        repeated_add = multiplier;
    end

end


enum int unsigned {
    idle,
    add_shift,
    done
} state, next_state;


always_ff @(posedge clk)
begin : next_state_condition
    if(rst) begin
        state <= idle;
        iteration <= 32'd0;
        product <= 32'd0;
    end
    else begin
        state <= next_state;
        iteration <= next_iteration;
        product <= next_product;
    end
end

always_comb
begin : next_state_logic
    case(state)
        idle: begin
                if(start == 1'b1 && (multiplicand == 32'd0 || multiplier == 32'd0)) begin
                    next_state <= done;
                end
                else if(start == 1'b1)
                    next_state <= add_shift;
                else
                    next_state <= idle;
              end

        add_shift: begin
                    if(iteration == stop_case)
                        next_state <= done;
                    else
                        next_state <= add_shift;
                   end

        done: begin
                next_state <= idle;
              end
        default:;
    endcase
end

always_comb 
begin : state_output
    case(state)
        idle: begin
                next_iteration <= 32'd0;
                next_product <= 32'd0;
                mul_resp <= 1'b0;
              end
        
        add_shift: begin
                    next_product = product + repeated_add;
                    next_iteration = iteration + 32'd1;
                    mul_resp <= 1'd0;
                   end

        done: begin
                next_iteration <= 32'd0;
                next_product <= 32'd0;             
                mul_resp <= 1'b1;
              end
              
        default: begin
                    next_iteration <= 32'd0;
                    next_product <= 32'd0;
                    mul_resp <= 1'b0;
                 end
    endcase
end
endmodule