data/full_repos/permissive/514758517/arth_top.v
1: b'%Error: data/full_repos/permissive/514758517/arth_top.v:2: Cannot find include file: adder.v\n`include "adder.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/adder.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/adder.v.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/adder.v.sv\n             adder.v\n             adder.v.v\n             adder.v.sv\n             obj_dir/adder.v\n             obj_dir/adder.v.v\n             obj_dir/adder.v.sv\n%Error: data/full_repos/permissive/514758517/arth_top.v:3: Cannot find include file: subtractor.v\n`include "subtractor.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514758517/arth_top.v:4: Cannot find include file: product.v\n`include "product.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/514758517/arth_top.v:5: Cannot find include file: divider.v\n`include "divider.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module arth_top(in1 , in2 , opcode , out_arth);

  input signed [4:0]in1;
  input signed [4:0]in2;
  output reg signed [8:0]out_arth;
  input [2:0]opcode;
  wire [8:0]out_add , out_sub , out_prod , out_div;
  
  add      u0_add  (in1 , in2 , out_add);
  subtract u1_sub  (in1 , in2 , out_sub);
  product  u2_prod (in1 , in2 , out_prod);
  divide   u3_div  (in1 , in2 , out_div);
  
  always@(opcode , out_add , out_sub , out_prod , out_div)
    begin
		case(opcode[1:0])
			2'b00 : out_arth <= out_add;
			2'b01 : out_arth <= out_sub;
			2'b10 : out_arth <= out_prod;
			2'b11 : out_arth <= out_div;
		endcase
	end
endmodule
module arth_top(in1 , in2 , opcode , out_arth);


  input signed [4:0]in1;
  input signed [4:0]in2;
  output reg signed [8:0]out_arth;
  input [2:0]opcode;
  wire [8:0]out_add , out_sub , out_prod , out_div;
  
  add      u0_add  (in1 , in2 , out_add);
  subtract u1_sub  (in1 , in2 , out_sub);
  product  u2_prod (in1 , in2 , out_prod);
  divide   u3_div  (in1 , in2 , out_div);
  
  always@(opcode , out_add , out_sub , out_prod , out_div)
    begin
		case(opcode[1:0])
			2'b00 : out_arth <= out_add;
			2'b01 : out_arth <= out_sub;
			2'b10 : out_arth <= out_prod;
			2'b11 : out_arth <= out_div;
		endcase
	end
endmodule