data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Writeback/PipelineRegMEMWB.v
data/verilator_xmls/a4e160a1-7997-476a-9f63-34153b3d526f.xml
module PipelineRegMEMWB (
    input [4:0] mrd,
    input [63:0] mr,
    input [63:0] md,
    input mm2reg,
    input mwreg,
    input clk,

    output reg [4:0] wrd,
    output reg [63:0] wr,
    output reg [63:0] wd,
    output reg wm2reg,
    output reg wwreg
);

    always @(posedge clk) begin
        wrd <= mrd;
        wr <= mr;
        wd <= md;
        wm2reg <= mm2reg;
        wwreg <= mwreg;
    end

endmodule
module PipelineRegMEMWB (
    input [4:0] mrd,
    input [63:0] mr,
    input [63:0] md,
    input mm2reg,
    input mwreg,
    input clk,

    output reg [4:0] wrd,
    output reg [63:0] wr,
    output reg [63:0] wd,
    output reg wm2reg,
    output reg wwreg
);


    always @(posedge clk) begin
        wrd <= mrd;
        wr <= mr;
        wd <= md;
        wm2reg <= mm2reg;
        wwreg <= mwreg;
    end

endmodule