data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #0 clk=1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset=1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #400 $finish;\n    ^\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new/RISC_V_TB.v:15: Cannot find file containing module: \'RISC_V\'\n  RISC_V procesor(clk, reset,\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new,data/full_repos/permissive/465067219/RISC_V\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new,data/full_repos/permissive/465067219/RISC_V.v\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sim_1/new,data/full_repos/permissive/465067219/RISC_V.sv\n             RISC_V\n             RISC_V.v\n             RISC_V.sv\n             obj_dir/RISC_V\n             obj_dir/RISC_V.v\n             obj_dir/RISC_V.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISC_V_TB();
  reg clk, reset;
  wire [31:0] PC_EX;
  wire [31:0] ALU_OUT_EX;
  wire [31:0] PC_MEM;
  wire PCSrc;
  wire [31:0] DATA_MEMORY_MEM;
  wire [31:0] ALU_DATA_WB;
  wire [1:0] forwardA, forwardB;
  wire pipeline_stall;
  RISC_V procesor(clk, reset,
                  PC_EX,
                  ALU_OUT_EX,
                  PC_MEM,
                  PCSrc,
                  DATA_MEMORY_MEM,
                  ALU_DATA_WB,
                  forwardA, forwardB,
                  pipeline_stall);   
  
  always #5 clk=~clk;
  
  initial begin
    #0 clk=1'b0;
       reset=1'b1;
    #10 reset=1'b0;
    #400 $finish;
  end
endmodule
module RISC_V_TB();

  reg clk, reset;
  wire [31:0] PC_EX;
  wire [31:0] ALU_OUT_EX;
  wire [31:0] PC_MEM;
  wire PCSrc;
  wire [31:0] DATA_MEMORY_MEM;
  wire [31:0] ALU_DATA_WB;
  wire [1:0] forwardA, forwardB;
  wire pipeline_stall;
  RISC_V procesor(clk, reset,
                  PC_EX,
                  ALU_OUT_EX,
                  PC_MEM,
                  PCSrc,
                  DATA_MEMORY_MEM,
                  ALU_DATA_WB,
                  forwardA, forwardB,
                  pipeline_stall);   
  
  always #5 clk=~clk;
  
  initial begin
    #0 clk=1'b0;
       reset=1'b1;
    #10 reset=1'b0;
    #400 $finish;
  end
endmodule