data/full_repos/permissive/525349297/lpc_periph_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n            #20 clk_i = ~clk_i;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/525349297/lpc_periph_tb.v:76: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("lpc_periph_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525349297/lpc_periph_tb.v:77: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,lpc_periph_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #40 nrst_i = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #250 nrst_i = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #40  lframe_i = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #40  lframe_i = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #800 lframe_i = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #80  lframe_i = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #800 lframe_i = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #80  lframe_i = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #40 nrst_i = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #250 nrst_i = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n            #40  lframe_i  = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n            #40 lframe_i = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n            #400 lframe_i = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n            #800 lframe_i = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n            #80 lframe_i = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n            #250 nrst_i = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n            #400 lframe_i = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/525349297/lpc_periph_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #8000;\n        ^\n%Error: Exiting due to 2 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lpc_periph_tb();

    reg         addr_hit;
    reg         rd_flag;
    reg         wr_flag;
    reg         clk_i;
    reg         nrst_i;
    reg         lframe_i;
    reg  [15:0] host_addr_i = 16'h0000;
    reg  [ 7:0] host_wr_i = 7'h00;
    reg  [ 7:0] periph_data_i = 7'h00;

    wire [ 7:0] periph_wr_o;
    wire [15:0] periph_addr_o;
    wire  [7:0] host_data_o;
    wire  [3:0] periph_rd_out;
    wire        host_ready;

    wire        periph_rd_status;
    wire        periph_wr_status;
    wire  [4:0] current_periph_state;
    wire  [4:0] current_host_state;
    wire        periph_en;

    wire        LCLK;
    wire        LRESET;
    wire        LFRAME;
    wire  [3:0] LAD = 4'bZZZZ;

    wire [31:0] TDATABOu;
    reg         READYBOu;
    wire        READYNET;
    reg  [15:0] u_addr;
    reg   [7:0] u_data;
    integer i, j;
    reg memory_cycle_sig;

    initial
    begin
        clk_i = 1'b1;
        READYBOu = 1'b0;
        forever
            #20 clk_i = ~clk_i;
    end

    initial
    begin

        $dumpfile("lpc_periph_tb.vcd");
        $dumpvars(0,lpc_periph_tb);

        lframe_i = 1;
        addr_hit = 1;
        nrst_i = 1;
        rd_flag  = 0;
        wr_flag = 1;
        #40 nrst_i = 0;
        #250 nrst_i = 1;
        
        memory_cycle_sig = 0;


        #40  lframe_i = 0;
        host_addr_i = 16'hF0F0;
        host_wr_i = 8'h5A;
        #40  lframe_i = 1;


        #800 lframe_i = 0;
        periph_data_i = 8'hA5;
        rd_flag = 1;
        wr_flag = 0;
        #80  lframe_i = 1;


        #800 lframe_i = 0;
        periph_data_i = 8'h88;
        rd_flag = 1;
        wr_flag = 0;
        #80  lframe_i = 1;

        addr_hit = 0;
        nrst_i = 1;
        u_addr = 0;
        u_data = 0;

        lframe_i = 1;
        addr_hit = 1;
        nrst_i = 1;
        rd_flag = 0;
        wr_flag = 1;
        #40 nrst_i = 0;
        #250 nrst_i = 1;

        for (i = 0; i <= 128; i = i + 1) begin
          for(j = 0; j < 2; j = j + 1) begin
            memory_cycle_sig = j;

            #40  lframe_i  = 0;
            rd_flag = 0;
            wr_flag  = 1;
            host_addr_i = u_addr+i;
            host_wr_i  = u_data+i;
            #40 lframe_i = 1;
            #400 lframe_i = 0;


            #800 lframe_i = 0;
            periph_data_i = 8'hBB+i;
            rd_flag = 1;
            wr_flag = 0;
            #80 lframe_i = 1;

            #250 nrst_i = 1;
            #400 lframe_i = 1;
          end   
        end

        #8000;

        $stop;
        $finish;
    end


    lpc_host lpc_host_inst(
    .clk_i(clk_i),

    .ctrl_addr_i(host_addr_i),
    .ctrl_data_i(host_wr_i),
    .ctrl_nrst_i(nrst_i),
    .ctrl_lframe_i(lframe_i),
    .ctrl_rd_status_i(rd_flag),
    .ctrl_wr_status_i(wr_flag),
    .ctrl_memory_cycle_i(memory_cycle_sig),

    .ctrl_data_o(host_data_o),
    .ctrl_ready_o(host_ready),

    .LPC_LAD(LAD), .LPC_LCLK(LCLK), .LPC_LRESET(LRESET), .LPC_LFRAME(LFRAME),
    .ctrl_host_state_o(current_host_state)
    );


    lpc_periph lpc_periph_inst(

    .clk_i(LCLK),
    .nrst_i(LRESET),
    .lframe_i(LFRAME),
    .lad_bus(LAD),
    .addr_hit_i(addr_hit),
    .current_state_o(current_periph_state),
    .din_i(periph_data_i),
    .lpc_data_in_o(periph_wr_o),
    .lpc_data_out_o(periph_rd_out),
    .lpc_addr_o(periph_addr_o),
    .lpc_en_o(periph_en),
    .io_wren_sm_o(periph_wr_status),
    .io_rden_sm_o(periph_rd_status),

    .TDATA(TDATABOu),
    .READY(READYNET)
    );

endmodule
module lpc_periph_tb();


    reg         addr_hit;
    reg         rd_flag;
    reg         wr_flag;
    reg         clk_i;
    reg         nrst_i;
    reg         lframe_i;
    reg  [15:0] host_addr_i = 16'h0000;
    reg  [ 7:0] host_wr_i = 7'h00;
    reg  [ 7:0] periph_data_i = 7'h00;

    wire [ 7:0] periph_wr_o;
    wire [15:0] periph_addr_o;
    wire  [7:0] host_data_o;
    wire  [3:0] periph_rd_out;
    wire        host_ready;

    wire        periph_rd_status;
    wire        periph_wr_status;
    wire  [4:0] current_periph_state;
    wire  [4:0] current_host_state;
    wire        periph_en;

    wire        LCLK;
    wire        LRESET;
    wire        LFRAME;
    wire  [3:0] LAD = 4'bZZZZ;

    wire [31:0] TDATABOu;
    reg         READYBOu;
    wire        READYNET;
    reg  [15:0] u_addr;
    reg   [7:0] u_data;
    integer i, j;
    reg memory_cycle_sig;

    initial
    begin
        clk_i = 1'b1;
        READYBOu = 1'b0;
        forever
            #20 clk_i = ~clk_i;
    end

    initial
    begin

        $dumpfile("lpc_periph_tb.vcd");
        $dumpvars(0,lpc_periph_tb);

        lframe_i = 1;
        addr_hit = 1;
        nrst_i = 1;
        rd_flag  = 0;
        wr_flag = 1;
        #40 nrst_i = 0;
        #250 nrst_i = 1;
        
        memory_cycle_sig = 0;


        #40  lframe_i = 0;
        host_addr_i = 16'hF0F0;
        host_wr_i = 8'h5A;
        #40  lframe_i = 1;


        #800 lframe_i = 0;
        periph_data_i = 8'hA5;
        rd_flag = 1;
        wr_flag = 0;
        #80  lframe_i = 1;


        #800 lframe_i = 0;
        periph_data_i = 8'h88;
        rd_flag = 1;
        wr_flag = 0;
        #80  lframe_i = 1;

        addr_hit = 0;
        nrst_i = 1;
        u_addr = 0;
        u_data = 0;

        lframe_i = 1;
        addr_hit = 1;
        nrst_i = 1;
        rd_flag = 0;
        wr_flag = 1;
        #40 nrst_i = 0;
        #250 nrst_i = 1;

        for (i = 0; i <= 128; i = i + 1) begin
          for(j = 0; j < 2; j = j + 1) begin
            memory_cycle_sig = j;

            #40  lframe_i  = 0;
            rd_flag = 0;
            wr_flag  = 1;
            host_addr_i = u_addr+i;
            host_wr_i  = u_data+i;
            #40 lframe_i = 1;
            #400 lframe_i = 0;


            #800 lframe_i = 0;
            periph_data_i = 8'hBB+i;
            rd_flag = 1;
            wr_flag = 0;
            #80 lframe_i = 1;

            #250 nrst_i = 1;
            #400 lframe_i = 1;
          end   
        end

        #8000;

        $stop;
        $finish;
    end


    lpc_host lpc_host_inst(
    .clk_i(clk_i),

    .ctrl_addr_i(host_addr_i),
    .ctrl_data_i(host_wr_i),
    .ctrl_nrst_i(nrst_i),
    .ctrl_lframe_i(lframe_i),
    .ctrl_rd_status_i(rd_flag),
    .ctrl_wr_status_i(wr_flag),
    .ctrl_memory_cycle_i(memory_cycle_sig),

    .ctrl_data_o(host_data_o),
    .ctrl_ready_o(host_ready),

    .LPC_LAD(LAD), .LPC_LCLK(LCLK), .LPC_LRESET(LRESET), .LPC_LFRAME(LFRAME),
    .ctrl_host_state_o(current_host_state)
    );


    lpc_periph lpc_periph_inst(

    .clk_i(LCLK),
    .nrst_i(LRESET),
    .lframe_i(LFRAME),
    .lad_bus(LAD),
    .addr_hit_i(addr_hit),
    .current_state_o(current_periph_state),
    .din_i(periph_data_i),
    .lpc_data_in_o(periph_wr_o),
    .lpc_data_out_o(periph_rd_out),
    .lpc_addr_o(periph_addr_o),
    .lpc_en_o(periph_en),
    .io_wren_sm_o(periph_wr_status),
    .io_rden_sm_o(periph_rd_status),

    .TDATA(TDATABOu),
    .READY(READYNET)
    );

endmodule