data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float/fp_sqrt.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float/fp_sqrt.v:21: Cannot find file containing module: 'DW_fp_sqrt'\n  DW_fp_sqrt #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float,data/full_repos/permissive/486954482/DW_fp_sqrt\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float,data/full_repos/permissive/486954482/DW_fp_sqrt.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float,data/full_repos/permissive/486954482/DW_fp_sqrt.sv\n             DW_fp_sqrt\n             DW_fp_sqrt.v\n             DW_fp_sqrt.sv\n             obj_dir/DW_fp_sqrt\n             obj_dir/DW_fp_sqrt.v\n             obj_dir/DW_fp_sqrt.sv\n%Error: Exiting due to 1 error(s)\n"
module fp_sqrt(g_input, e_input, o); 



parameter inst_sig_width = 23;
parameter inst_exp_width = 8;
parameter inst_ieee_compliance = 0;


input [inst_sig_width+inst_exp_width + 3: 0] g_input;
input [inst_sig_width+inst_exp_width + 3: 0] e_input;

output [inst_sig_width+inst_exp_width : 0] o;

wire [inst_sig_width+inst_exp_width : 0] inst_a;
wire [2 : 0] inst_rnd;

assign inst_rnd = g_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1] ^ e_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1];
assign inst_a = g_input[inst_sig_width+inst_exp_width:0] ^ e_input[inst_sig_width+inst_exp_width:0];

  DW_fp_sqrt #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 (
                      .a(inst_a),
                      .rnd(inst_rnd),
                      .z(o),
                      .status() );

endmodule
module fp_sqrt(g_input, e_input, o);
 



parameter inst_sig_width = 23;
parameter inst_exp_width = 8;
parameter inst_ieee_compliance = 0;


input [inst_sig_width+inst_exp_width + 3: 0] g_input;
input [inst_sig_width+inst_exp_width + 3: 0] e_input;

output [inst_sig_width+inst_exp_width : 0] o;

wire [inst_sig_width+inst_exp_width : 0] inst_a;
wire [2 : 0] inst_rnd;

assign inst_rnd = g_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1] ^ e_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1];
assign inst_a = g_input[inst_sig_width+inst_exp_width:0] ^ e_input[inst_sig_width+inst_exp_width:0];

  DW_fp_sqrt #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 (
                      .a(inst_a),
                      .rnd(inst_rnd),
                      .z(o),
                      .status() );

endmodule