data/full_repos/permissive/43298951/src/rtl/gcm_core.v
1: b'%Error: data/full_repos/permissive/43298951/src/rtl/gcm_core.v:114: Cannot find file containing module: \'aes_core\'\n  aes_core aes(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43298951/src/rtl,data/full_repos/permissive/43298951/aes_core\n             data/full_repos/permissive/43298951/src/rtl,data/full_repos/permissive/43298951/aes_core.v\n             data/full_repos/permissive/43298951/src/rtl,data/full_repos/permissive/43298951/aes_core.sv\n             aes_core\n             aes_core.v\n             aes_core.sv\n             obj_dir/aes_core\n             obj_dir/aes_core.v\n             obj_dir/aes_core.sv\n%Error: data/full_repos/permissive/43298951/src/rtl/gcm_core.v:132: Cannot find file containing module: \'gcm_ghash\'\n  gcm_ghash ghash(\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/43298951/src/rtl/gcm_core.v:159: Operator ASSIGNDLY expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n                                                                          : ... In instance gcm_core\n          ctr_reg      <= 64\'h0;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module gcm_core(
                input wire            clk,
                input wire            reset_n,

                input wire            init,
                input wire            next,
                input wire            done,

                input wire            enc_dec,
                input wire            keylen,
                input wire [1 : 0]    taglen,

                output wire           ready,
                output wire           valid,
                output wire           tag_correct,

                input wire [255 : 0]  key,
                input wire [127 : 0]  nonce,
                input wire [127 : 0]  block_in,
                output wire [127 : 0] block_out,
                input wire [127 : 0]  tag_in,
                output wire [127 : 0] tag_out
               );




  localparam CTRL_IDLE = 3'h0;
  localparam CTRL_INIT = 3'h1;





  reg [127 : 0] ctr_reg;
  reg [127 : 0] ctr_new;
  reg           ctr_we;

  reg [2 : 0]   gcm_ctrl_reg;
  reg [2 : 0]   gcm_ctrl_new;
  reg           gcm_ctrl_we;





  reg            aes_init;
  reg            aes_next;
  wire           aes_encdec;
  wire           aes_ready;
  wire           aes_valid;

  reg            ctr_init;
  reg            ctr_next;

  reg            ghash_init;
  reg            ghash_next;
  wire           ghash_ready;
  reg [127 : 0]  ghash_h0;
  reg [127 : 0]  ghash_x;
  wire [127 : 0] ghash_y;








  assign aes_encdec = 1;





  aes_core aes(
               .clk(clk),
               .reset_n(reset_n),

               .encdec(aes_encdec),
               .init(aes_init),
               .next(aes_next),
               .ready(aes_ready),

               .key(key),
               .keylen(keylen),

               .block(block_in),
               .result(block_out),
               .result_valid(aes_valid)
              );


  gcm_ghash ghash(
                  .clk(clk),
                  .reset_n(reset_n),

                  .init(ghash_init),
                  .next(ghash_next),
                  .ready(ghash_ready),

                  .h0(ghash_h0),
                  .x(ghash_x),
                  .y(ghash_y)
                 );









  always @ (posedge clk)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          ctr_reg      <= 64'h0;
          gcm_ctrl_reg <= CTRL_IDLE;
        end
      else
        begin
          if (ctr_we)
            ctr_reg <= ctr_new;

          if (gcm_ctrl_we)
            gcm_ctrl_reg <= gcm_ctrl_new;

        end
    end





  always @*
    begin : ctr_logic
      ctr_new = 128'h0;
      ctr_we  = 0;

      if (ctr_init)
        begin
          ctr_new = nonce;
          ctr_we  = 1;
        end

      if (ctr_next)
        begin
          ctr_new = {ctr_reg[127 : 64], ctr_reg[63 : 0] + 1'b1};
          ctr_we  = 1;
        end
    end





  always @*
    begin : gcm_core_ctrl_fsm
      aes_init     = 0;
      aes_next     = 0;
      ctr_init     = 0;
      ctr_next     = 0;
      gcm_ctrl_new = CTRL_IDLE;
      gcm_ctrl_we  = 0;

      case (gcm_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                gcm_ctrl_new = CTRL_INIT;
                gcm_ctrl_we  = 1;
              end
          end

        CTRL_INIT:
          begin
            gcm_ctrl_new = CTRL_IDLE;
            gcm_ctrl_we  = 1;
          end

        default:
          begin
          end
      endcase
    end

endmodule
module gcm_core(
                input wire            clk,
                input wire            reset_n,

                input wire            init,
                input wire            next,
                input wire            done,

                input wire            enc_dec,
                input wire            keylen,
                input wire [1 : 0]    taglen,

                output wire           ready,
                output wire           valid,
                output wire           tag_correct,

                input wire [255 : 0]  key,
                input wire [127 : 0]  nonce,
                input wire [127 : 0]  block_in,
                output wire [127 : 0] block_out,
                input wire [127 : 0]  tag_in,
                output wire [127 : 0] tag_out
               );





  localparam CTRL_IDLE = 3'h0;
  localparam CTRL_INIT = 3'h1;





  reg [127 : 0] ctr_reg;
  reg [127 : 0] ctr_new;
  reg           ctr_we;

  reg [2 : 0]   gcm_ctrl_reg;
  reg [2 : 0]   gcm_ctrl_new;
  reg           gcm_ctrl_we;





  reg            aes_init;
  reg            aes_next;
  wire           aes_encdec;
  wire           aes_ready;
  wire           aes_valid;

  reg            ctr_init;
  reg            ctr_next;

  reg            ghash_init;
  reg            ghash_next;
  wire           ghash_ready;
  reg [127 : 0]  ghash_h0;
  reg [127 : 0]  ghash_x;
  wire [127 : 0] ghash_y;








  assign aes_encdec = 1;





  aes_core aes(
               .clk(clk),
               .reset_n(reset_n),

               .encdec(aes_encdec),
               .init(aes_init),
               .next(aes_next),
               .ready(aes_ready),

               .key(key),
               .keylen(keylen),

               .block(block_in),
               .result(block_out),
               .result_valid(aes_valid)
              );


  gcm_ghash ghash(
                  .clk(clk),
                  .reset_n(reset_n),

                  .init(ghash_init),
                  .next(ghash_next),
                  .ready(ghash_ready),

                  .h0(ghash_h0),
                  .x(ghash_x),
                  .y(ghash_y)
                 );









  always @ (posedge clk)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          ctr_reg      <= 64'h0;
          gcm_ctrl_reg <= CTRL_IDLE;
        end
      else
        begin
          if (ctr_we)
            ctr_reg <= ctr_new;

          if (gcm_ctrl_we)
            gcm_ctrl_reg <= gcm_ctrl_new;

        end
    end





  always @*
    begin : ctr_logic
      ctr_new = 128'h0;
      ctr_we  = 0;

      if (ctr_init)
        begin
          ctr_new = nonce;
          ctr_we  = 1;
        end

      if (ctr_next)
        begin
          ctr_new = {ctr_reg[127 : 64], ctr_reg[63 : 0] + 1'b1};
          ctr_we  = 1;
        end
    end





  always @*
    begin : gcm_core_ctrl_fsm
      aes_init     = 0;
      aes_next     = 0;
      ctr_init     = 0;
      ctr_next     = 0;
      gcm_ctrl_new = CTRL_IDLE;
      gcm_ctrl_we  = 0;

      case (gcm_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                gcm_ctrl_new = CTRL_INIT;
                gcm_ctrl_we  = 1;
              end
          end

        CTRL_INIT:
          begin
            gcm_ctrl_new = CTRL_IDLE;
            gcm_ctrl_we  = 1;
          end

        default:
          begin
          end
      endcase
    end

endmodule