data/full_repos/permissive/505451992/pwr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    reset = 1;#125 \n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    reset = 0;#125;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    reset = 0;#125;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #2000000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #4000000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n                #500\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n                  #500000\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n                        #500000\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n                          #500000\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n                          #500000\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n                          #500000\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n                          #1000000\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n                            #500000\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n                            #500000\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n                            #500000\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n                            #500000\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n                             #500000  \n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n                             #500000 \n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n                            #500000 \n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/pwr_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n                            #500000 \n                            ^\n%Error: data/full_repos/permissive/505451992/pwr_tb.v:22: Cannot find file containing module: \'OSCH\'\nOSCH OSCH_inst( .STDBY(1\'b0),  \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/OSCH\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/OSCH.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/OSCH.sv\n             OSCH\n             OSCH.v\n             OSCH.sv\n             obj_dir/OSCH\n             obj_dir/OSCH.v\n             obj_dir/OSCH.sv\n%Error: data/full_repos/permissive/505451992/pwr_tb.v:29: Cannot find file containing module: \'Rate_switch\'\n   Rate_switch rsh(.reset(reset),\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/pwr_tb.v:34: Cannot find file containing module: \'Clock\'\n      Clock cok(.reset(reset),\n      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/pwr_tb.v:55: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh6f\' generates 32 or 7 bits.\n                                                                : ... In instance pwr_tb\n    R = 111;\n      ^\n%Error: data/full_repos/permissive/505451992/pwr_tb.v:100: Cannot find file containing module: \'PWM_Generator\'\n    PWM_Generator pgc(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/pwr_tb.v:109: Cannot find file containing module: \'PWM_Receiver\'\n    PWM_Receiver  pmr(\n    ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwr_tb(

    );
    reg reset;
    wire clk;

    wire[9:0] Position;
    wire PWM_CD;


    reg[9:0] Position_CD;

  wire CLK_PWM;
    wire [23:0] Rate;
	reg [2:0]R;
 


defparam OSCH_inst.NOM_FREQ = "10.23";
OSCH OSCH_inst( .STDBY(1'b0),

.OSC(clk),
.SEDSTDBY());

        

   Rate_switch rsh(.reset(reset),
        .clk(clk),.R(R),.Rate_1(Rate));
          
 
 
      Clock cok(.reset(reset),
      .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
 
 
       
        
        initial begin



    reset = 1;#125 
    reset = 0;#125;
    reset = 0;#125;
    end
    

     initial begin
		 R = 3'b000;
		 #2000000
		  R = 3'b001;
		  #4000000
		  R = 111;
		 end
           

           initial begin
                #500
                 Position_CD = 1;
                  #500000
                Position_CD = 1022;
                        #500000
                Position_CD = 400;
                          #500000
                Position_CD = 100;
                          #500000
                Position_CD = 100;
                          #500000
                Position_CD = 1;
                          #1000000
                Position_CD = 1022;
                            #500000
                Position_CD = 2;
                            #500000
                Position_CD = 3;
                            #500000
                Position_CD = 0;
                            #500000
                Position_CD = 1000;
                             #500000  
                Position_CD = 1023;                               
                             #500000 
                 Position_CD = 1021; 
                            #500000 
                 Position_CD = 0; 
                            #500000 
                 Position_CD = 1021; 
                end
                
           
    
    
    
    
    
    
    
    PWM_Generator pgc(
    .reset(reset),
    .CLK(CLK_PWM),

    .Position(Position_CD),

    .pwm(PWM_CD)
        ); 
    
    PWM_Receiver  pmr(
    .reset(reset),
    .clk(CLK_PWM),
    .pwm(PWM_CD),
    .Position(Position)
    
        );
endmodule
module pwr_tb(

    );

    reg reset;
    wire clk;

    wire[9:0] Position;
    wire PWM_CD;


    reg[9:0] Position_CD;

  wire CLK_PWM;
    wire [23:0] Rate;
	reg [2:0]R;
 


defparam OSCH_inst.NOM_FREQ = "10.23";
OSCH OSCH_inst( .STDBY(1'b0),

.OSC(clk),
.SEDSTDBY());

        

   Rate_switch rsh(.reset(reset),
        .clk(clk),.R(R),.Rate_1(Rate));
          
 
 
      Clock cok(.reset(reset),
      .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
 
 
       
        
        initial begin



    reset = 1;#125 
    reset = 0;#125;
    reset = 0;#125;
    end
    

     initial begin
		 R = 3'b000;
		 #2000000
		  R = 3'b001;
		  #4000000
		  R = 111;
		 end
           

           initial begin
                #500
                 Position_CD = 1;
                  #500000
                Position_CD = 1022;
                        #500000
                Position_CD = 400;
                          #500000
                Position_CD = 100;
                          #500000
                Position_CD = 100;
                          #500000
                Position_CD = 1;
                          #1000000
                Position_CD = 1022;
                            #500000
                Position_CD = 2;
                            #500000
                Position_CD = 3;
                            #500000
                Position_CD = 0;
                            #500000
                Position_CD = 1000;
                             #500000  
                Position_CD = 1023;                               
                             #500000 
                 Position_CD = 1021; 
                            #500000 
                 Position_CD = 0; 
                            #500000 
                 Position_CD = 1021; 
                end
                
           
    
    
    
    
    
    
    
    PWM_Generator pgc(
    .reset(reset),
    .CLK(CLK_PWM),

    .Position(Position_CD),

    .pwm(PWM_CD)
        ); 
    
    PWM_Receiver  pmr(
    .reset(reset),
    .clk(CLK_PWM),
    .pwm(PWM_CD),
    .Position(Position)
    
        );
endmodule