data/full_repos/permissive/461620575/Simple DACs/Delta-Sigma/DAC.v
1: b'%Error: Cannot find file containing module: DACs/Delta-Sigma,data/full_repos/permissive/461620575\n        ... Looked in:\n             data/full_repos/permissive/461620575/Simple/DACs/Delta-Sigma,data/full_repos/permissive/461620575\n             data/full_repos/permissive/461620575/Simple/DACs/Delta-Sigma,data/full_repos/permissive/461620575.v\n             data/full_repos/permissive/461620575/Simple/DACs/Delta-Sigma,data/full_repos/permissive/461620575.sv\n             DACs/Delta-Sigma,data/full_repos/permissive/461620575\n             DACs/Delta-Sigma,data/full_repos/permissive/461620575.v\n             DACs/Delta-Sigma,data/full_repos/permissive/461620575.sv\n             obj_dir/DACs/Delta-Sigma,data/full_repos/permissive/461620575\n             obj_dir/DACs/Delta-Sigma,data/full_repos/permissive/461620575.v\n             obj_dir/DACs/Delta-Sigma,data/full_repos/permissive/461620575.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461620575/Simple\n%Error: Cannot find file containing module: DACs/Delta-Sigma/DAC.v\n%Error: Exiting due to 3 error(s)\n'
module DAC #(parameter WIDTH = 10) (
	input clk, 
	input rst, 
	input [WIDTH-1:0] DAC_in,
	
	output reg DAC_out
	);
		
	reg [(WIDTH-1)+2:0] sigma;

	always@(posedge clk) begin
	

		sigma   <= sigma + (sigma[(WIDTH-1)+2] ? 2'b11 << WIDTH : {((WIDTH-1)+2){1'b0}}) + DAC_in; 
		DAC_out <= sigma[(WIDTH-1)+2];
			
		if (rst) begin
			sigma   <= 1'b1 << WIDTH;
			DAC_out <= 1'b0;			      
		end
	end	
	
endmodule
module DAC #(parameter WIDTH = 10) (
	input clk, 
	input rst, 
	input [WIDTH-1:0] DAC_in,
	
	output reg DAC_out
	);

		
	reg [(WIDTH-1)+2:0] sigma;

	always@(posedge clk) begin
	

		sigma   <= sigma + (sigma[(WIDTH-1)+2] ? 2'b11 << WIDTH : {((WIDTH-1)+2){1'b0}}) + DAC_in; 
		DAC_out <= sigma[(WIDTH-1)+2];
			
		if (rst) begin
			sigma   <= 1'b1 << WIDTH;
			DAC_out <= 1'b0;			      
		end
	end	
	
endmodule