data/full_repos/permissive/482006041/6-1/user/src/top.v
1: b"%Error: data/full_repos/permissive/482006041/6-1/user/src/top.v:5: Cannot find file containing module: 'clk_div_even'\n    clk_div_even #(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482006041/6-1/user/src,data/full_repos/permissive/482006041/clk_div_even\n             data/full_repos/permissive/482006041/6-1/user/src,data/full_repos/permissive/482006041/clk_div_even.v\n             data/full_repos/permissive/482006041/6-1/user/src,data/full_repos/permissive/482006041/clk_div_even.sv\n             clk_div_even\n             clk_div_even.v\n             clk_div_even.sv\n             obj_dir/clk_div_even\n             obj_dir/clk_div_even.v\n             obj_dir/clk_div_even.sv\n%Error: data/full_repos/permissive/482006041/6-1/user/src/top.v:15: Cannot find file containing module: 'clk_div_odd'\n    clk_div_odd #(\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module clock_div(reset, clk_100MHz, clk_10MHz, clk_6667KHz);
    input reset, clk_100MHz;
    output clk_10MHz, clk_6667KHz;

    clk_div_even #(
        .DIV   		( 10     		),
        .DIV_W 		( 3     		))
    u_clk_div_even(

        .clk     		( clk_100MHz	),
        .rst_n   		( reset   		),
        .clk_div 		( clk_10MHz 	)
    );
    
    clk_div_odd #(
        .DIV   		( 15 		),
        .DIV_W 		( 4  		))
    u_clk_div_odd(

        .clk     		( clk_100MHz    ),
        .rst_n   		( reset   		),
        .clk_div 		( clk_6667KHz 	)
    );

endmodule
module clock_div(reset, clk_100MHz, clk_10MHz, clk_6667KHz);

    input reset, clk_100MHz;
    output clk_10MHz, clk_6667KHz;

    clk_div_even #(
        .DIV   		( 10     		),
        .DIV_W 		( 3     		))
    u_clk_div_even(

        .clk     		( clk_100MHz	),
        .rst_n   		( reset   		),
        .clk_div 		( clk_10MHz 	)
    );
    
    clk_div_odd #(
        .DIV   		( 15 		),
        .DIV_W 		( 4  		))
    u_clk_div_odd(

        .clk     		( clk_100MHz    ),
        .rst_n   		( reset   		),
        .clk_div 		( clk_6667KHz 	)
    );

endmodule