data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:17: Multiple top level modules\n                                                                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                    : ... Top module \'axi_lite_join\'\nmodule axi_lite_join (\n       ^~~~~~~~~~~~~\n                                                                                                                                    : ... Top module \'AXI_LITE\'\n    AXI_LITE.Slave  in,\n    ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:17: Unsupported: Interfaced port on top level module\n    AXI_LITE.Slave  in,\n                    ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:18: Unsupported: Interfaced port on top level module\n    AXI_LITE.Master out\n                    ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:17: Cannot find file containing interface: \'AXI_LITE\'\n    AXI_LITE.Slave  in,\n    ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:18: Cannot find file containing interface: \'AXI_LITE\'\n    AXI_LITE.Master out\n    ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_lite_join.sv:17: ../V3LinkDot.cpp:2055: Unlinked interface\n    AXI_LITE.Slave  in,\n    ^~~~~~~~\n'
module axi_lite_join (
    AXI_LITE.Slave  in,
    AXI_LITE.Master out
);

    `ifndef SYNTHESIS
    initial begin
        assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
        assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
    end
    `endif

    assign out.aw_addr   = in.aw_addr;
    assign out.aw_valid  = in.aw_valid;
    assign out.w_data    = in.w_data;
    assign out.w_strb    = in.w_strb;
    assign out.w_valid   = in.w_valid;
    assign out.b_ready   = in.b_ready;
    assign out.ar_addr   = in.ar_addr;
    assign out.ar_valid  = in.ar_valid;
    assign out.r_ready   = in.r_ready;

    assign in.aw_ready = out.aw_ready;
    assign in.w_ready  = out.w_ready;
    assign in.b_resp   = out.b_resp;
    assign in.b_valid  = out.b_valid;
    assign in.ar_ready = out.ar_ready;
    assign in.r_data   = out.r_data;
    assign in.r_resp   = out.r_resp;
    assign in.r_valid  = out.r_valid;

endmodule
module axi_lite_join (
    AXI_LITE.Slave  in,
    AXI_LITE.Master out
);


    `ifndef SYNTHESIS
    initial begin
        assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
        assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
    end
    `endif

    assign out.aw_addr   = in.aw_addr;
    assign out.aw_valid  = in.aw_valid;
    assign out.w_data    = in.w_data;
    assign out.w_strb    = in.w_strb;
    assign out.w_valid   = in.w_valid;
    assign out.b_ready   = in.b_ready;
    assign out.ar_addr   = in.ar_addr;
    assign out.ar_valid  = in.ar_valid;
    assign out.r_ready   = in.r_ready;

    assign in.aw_ready = out.aw_ready;
    assign in.w_ready  = out.w_ready;
    assign in.b_resp   = out.b_resp;
    assign in.b_valid  = out.b_valid;
    assign in.ar_ready = out.ar_ready;
    assign in.r_data   = out.r_data;
    assign in.r_resp   = out.r_resp;
    assign in.r_valid  = out.r_valid;

endmodule