data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/syn_lib/SHIFT_LEFT.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/syn_lib/SHIFT_LEFT.v:3: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/\n// synopsys_ template \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module SHIFT_LEFT
#(
  parameter N=16
)
(
  a,
  shift_amount,
  o
);

  localparam LOG_N = $clog2(N);

  input [N-1:0] a;
  input [LOG_N:0] shift_amount;
  output [N-1:0] o;


  wire [N-1:0] ai[LOG_N+1:0];

  assign ai[0] = a;

  genvar i;
  generate
    for (i = 0; i < LOG_N+1; i = i + 1) begin: ASSIGN
      assign ai[i+1] = (shift_amount[i])?(ai[i]>>2**i):(ai[i]);
    end
  endgenerate

  assign o = ai[LOG_N+1];

endmodule
module SHIFT_LEFT
#(
  parameter N=16
)
(
  a,
  shift_amount,
  o
);


  localparam LOG_N = $clog2(N);

  input [N-1:0] a;
  input [LOG_N:0] shift_amount;
  output [N-1:0] o;


  wire [N-1:0] ai[LOG_N+1:0];

  assign ai[0] = a;

  genvar i;
  generate
    for (i = 0; i < LOG_N+1; i = i + 1) begin: ASSIGN
      assign ai[i+1] = (shift_amount[i])?(ai[i]>>2**i):(ai[i]);
    end
  endgenerate

  assign o = ai[LOG_N+1];

endmodule