data/full_repos/permissive/479923049/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case expression, but Case expression\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case Item, but Case Item\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:77: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(16) instruction_register (clk, load_ir, read_data, ir_out);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.sv\n             vDFFE\n             vDFFE.v\n             vDFFE.sv\n             obj_dir/vDFFE\n             obj_dir/vDFFE.v\n             obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/479923049/cpu.v:91: Cannot find file containing module: \'datapath\'\n    datapath DP(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:99: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) program_counter (clk, load_pc, next_pc, PC);\n    ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:100: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) data_address (clk, load_addr, datapath_out[8:0], data_addr_out);\n    ^~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module InstructionDecoder(instruction, opcode, op, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum);
    input [15:0] instruction;
    input [2:0] nsel;

    output [1:0] op, ALUop, shift;
    output [15:0] sximm5, sximm8;
    output [2:0] opcode;
    output reg [2:0] readnum, writenum;

    assign ALUop = instruction[12:11];
    assign opcode = instruction[15:13];
    assign op = instruction[12:11];
    assign sximm5 = { {11{instruction[4]}} , instruction[4:0] };
    assign sximm8 = { {8{instruction[7]}} , instruction[7:0] };
    assign shift = instruction[4:3];
    
    always @(*) begin 
        case(nsel)
            3'b001: {readnum, writenum} = {2{instruction[2:0]}};
            3'b010: {readnum, writenum} = {2{instruction[7:5]}};
            3'b100: {readnum, writenum} = {2{instruction[10:8]}};
            default: {readnum, writenum} = {6{1'bx}};
        endcase
    end
endmodule
module InstructionDecoder(instruction, opcode, op, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum);

    input [15:0] instruction;
    input [2:0] nsel;

    output [1:0] op, ALUop, shift;
    output [15:0] sximm5, sximm8;
    output [2:0] opcode;
    output reg [2:0] readnum, writenum;

    assign ALUop = instruction[12:11];
    assign opcode = instruction[15:13];
    assign op = instruction[12:11];
    assign sximm5 = { {11{instruction[4]}} , instruction[4:0] };
    assign sximm8 = { {8{instruction[7]}} , instruction[7:0] };
    assign shift = instruction[4:3];
    
    always @(*) begin 
        case(nsel)
            3'b001: {readnum, writenum} = {2{instruction[2:0]}};
            3'b010: {readnum, writenum} = {2{instruction[7:5]}};
            3'b100: {readnum, writenum} = {2{instruction[10:8]}};
            default: {readnum, writenum} = {6{1'bx}};
        endcase
    end
endmodule