data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:77: Unsupported: Ignoring delay on this delayed statement.\n#5 din_a = 0; din_b = 0; we_a = 0; oe_b = 0; we_b = 1; oe_a = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:78: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 2; din_b = din_b + 1; addr_b = 2; #1 load = 1; #1 load =  0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:78: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 2; din_b = din_b + 1; addr_b = 2; #1 load = 1; #1 load =  0;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:78: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 2; din_b = din_b + 1; addr_b = 2; #1 load = 1; #1 load =  0;\n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:79: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 1; din_b = din_b + 1; addr_b = 1; #1 load = 1; #1 load = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:79: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 1; din_b = din_b + 1; addr_b = 1; #1 load = 1; #1 load = 0;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:79: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 1; din_b = din_b + 1; addr_b = 1; #1 load = 1; #1 load = 0;\n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:80: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 3; din_b = din_b + 2; addr_b = 3; #1 load = 1; #1 load = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:80: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 3; din_b = din_b + 2; addr_b = 3; #1 load = 1; #1 load = 0;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:80: Unsupported: Ignoring delay on this delayed statement.\n#5 addr_a = 3; din_b = din_b + 2; addr_b = 3; #1 load = 1; #1 load = 0;\n                                                           ^\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:137: syntax error, unexpected \'@\'\n#50 @(negedge clk) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_double_ram_sy.v:137: Unsupported: Ignoring delay on this delayed statement.\n#50 @(negedge clk) begin\n^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_double_ram_sy;
reg clk, cs, rst;
reg [2:0] din_a;
reg [2:0] addr_a;
reg we_a, oe_a;
wire [2:0] dout_a;

reg [2:0] din_b;
reg [2:0] addr_b;
reg we_b, oe_b;
wire [2:0] dout_b;
reg load;
reg rst_clk;
integer i = 1;
wire [2:0] memout;

always #5 clk = ~clk;
initial begin
    #50
    clk = 0;
    load = 0;
    cs = 1;
    rst = 1;
    din_a = 0;
    addr_a = 0;
    we_a = 0;
    oe_a = 0;
    rst_clk = 1;
    din_b = 0;
    addr_b = 0;
    we_b = 0;
    oe_b = 0;

























#5 din_a = 0; din_b = 0; we_a = 0; oe_b = 0; we_b = 1; oe_a = 1;
#5 addr_a = 2; din_b = din_b + 1; addr_b = 2; #1 load = 1; #1 load =  0;
#5 addr_a = 1; din_b = din_b + 1; addr_b = 1; #1 load = 1; #1 load = 0;
#5 addr_a = 3; din_b = din_b + 2; addr_b = 3; #1 load = 1; #1 load = 0;
























































#50 @(negedge clk) begin
    cs = 1;
end
end








double_ram_sy test(
clk, rst, cs, 
din_a, addr_a, dout_a, we_a, oe_a,
din_b, addr_b, dout_b, we_b, oe_b,
load
    );

endmodule
module sim_double_ram_sy;

reg clk, cs, rst;
reg [2:0] din_a;
reg [2:0] addr_a;
reg we_a, oe_a;
wire [2:0] dout_a;

reg [2:0] din_b;
reg [2:0] addr_b;
reg we_b, oe_b;
wire [2:0] dout_b;
reg load;
reg rst_clk;
integer i = 1;
wire [2:0] memout;

always #5 clk = ~clk;
initial begin
    #50
    clk = 0;
    load = 0;
    cs = 1;
    rst = 1;
    din_a = 0;
    addr_a = 0;
    we_a = 0;
    oe_a = 0;
    rst_clk = 1;
    din_b = 0;
    addr_b = 0;
    we_b = 0;
    oe_b = 0;

























#5 din_a = 0; din_b = 0; we_a = 0; oe_b = 0; we_b = 1; oe_a = 1;
#5 addr_a = 2; din_b = din_b + 1; addr_b = 2; #1 load = 1; #1 load =  0;
#5 addr_a = 1; din_b = din_b + 1; addr_b = 1; #1 load = 1; #1 load = 0;
#5 addr_a = 3; din_b = din_b + 2; addr_b = 3; #1 load = 1; #1 load = 0;
























































#50 @(negedge clk) begin
    cs = 1;
end
end








double_ram_sy test(
clk, rst, cs, 
din_a, addr_a, dout_a, we_a, oe_a,
din_b, addr_b, dout_b, we_b, oe_b,
load
    );

endmodule