data/full_repos/permissive/43974493/src/instr_cache.v
1: b'%Error: data/full_repos/permissive/43974493/src/instr_cache.v:8: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.v\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/43974493/src/instr_cache.v:15: Define or directive not defined: \'`ADDR_BITS\'\n   input [`ADDR_BITS-1:0]       instr_ptr,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/43974493/src/instr_cache.v:17: Define or directive not defined: \'`INSTR_BITS\'\n   output reg [`INSTR_BITS-1:0] instr,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43974493/src/instr_cache.v:52: Define or directive not defined: \'`MAIN_MEM_PREFIX\'\n   wire [29:0] prefixed_instr_ptr = { `MAIN_MEM_PREFIX, instr_ptr };\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43974493/src/instr_cache.v:52: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wire [29:0] prefixed_instr_ptr = { `MAIN_MEM_PREFIX, instr_ptr };\n                                                      ^\n%Error: Exiting due to 5 error(s)\n'
module instr_cache
  (
   input                        clk,
   input                        boot_done,

   input [`ADDR_BITS-1:0]       instr_ptr,
   output                       valid,
   output reg [`INSTR_BITS-1:0] instr,

   output reg                   mem_cmd_en,
   output [2:0]                 mem_cmd_instr,
   output [5:0]                 mem_cmd_bl,
   output reg [29:0]            mem_cmd_byte_addr,
   input                        mem_cmd_empty,
   input                        mem_cmd_full,
   output reg                   mem_rd_en,
   input [31:0]                 mem_rd_data,
   input                        mem_rd_full,
   input                        mem_rd_empty,
   input [6:0]                  mem_rd_count,
   input                        mem_rd_overflow,
   input                        mem_rd_error
   );

   initial begin
      instr = 0;
      mem_cmd_en = 0;
      mem_cmd_byte_addr = 0;
      mem_rd_en = 0;
   end


   assign mem_cmd_instr = 3'b001;

   assign mem_cmd_bl = 6'b000000;


   `define STATE_PRE_BOOT 0
   `define STATE_CMD      1
   `define STATE_WAIT     2
   `define STATE_READ     3
   reg [1:0]  state = `STATE_PRE_BOOT;
   wire [29:0] prefixed_instr_ptr = { `MAIN_MEM_PREFIX, instr_ptr };
   assign valid = (`STATE_CMD == state) && (mem_cmd_byte_addr == prefixed_instr_ptr);
   always @ (posedge clk) begin
      mem_cmd_en <= 0;
      mem_rd_en <= 0;
      case (state)
         `STATE_PRE_BOOT: begin
            if (boot_done) begin
               send_cmd();
            end
         end
         `STATE_CMD: begin
            if (mem_cmd_byte_addr != prefixed_instr_ptr) begin
               send_cmd();
            end
         end
         `STATE_WAIT: begin
            if (!mem_rd_empty) begin
               mem_rd_en <= 1;
               state <= `STATE_READ;
            end
         end
         `STATE_READ: begin
            instr <= mem_rd_data;
            state <= `STATE_CMD;
         end
      endcase
   end

   task send_cmd;
      begin
         mem_cmd_en <= 1;
         mem_cmd_byte_addr <= prefixed_instr_ptr;
         state <= `STATE_WAIT;
      end
   endtask

endmodule
module instr_cache
  (
   input                        clk,
   input                        boot_done,

   input [`ADDR_BITS-1:0]       instr_ptr,
   output                       valid,
   output reg [`INSTR_BITS-1:0] instr,

   output reg                   mem_cmd_en,
   output [2:0]                 mem_cmd_instr,
   output [5:0]                 mem_cmd_bl,
   output reg [29:0]            mem_cmd_byte_addr,
   input                        mem_cmd_empty,
   input                        mem_cmd_full,
   output reg                   mem_rd_en,
   input [31:0]                 mem_rd_data,
   input                        mem_rd_full,
   input                        mem_rd_empty,
   input [6:0]                  mem_rd_count,
   input                        mem_rd_overflow,
   input                        mem_rd_error
   );


   initial begin
      instr = 0;
      mem_cmd_en = 0;
      mem_cmd_byte_addr = 0;
      mem_rd_en = 0;
   end


   assign mem_cmd_instr = 3'b001;

   assign mem_cmd_bl = 6'b000000;


   `define STATE_PRE_BOOT 0
   `define STATE_CMD      1
   `define STATE_WAIT     2
   `define STATE_READ     3
   reg [1:0]  state = `STATE_PRE_BOOT;
   wire [29:0] prefixed_instr_ptr = { `MAIN_MEM_PREFIX, instr_ptr };
   assign valid = (`STATE_CMD == state) && (mem_cmd_byte_addr == prefixed_instr_ptr);
   always @ (posedge clk) begin
      mem_cmd_en <= 0;
      mem_rd_en <= 0;
      case (state)
         `STATE_PRE_BOOT: begin
            if (boot_done) begin
               send_cmd();
            end
         end
         `STATE_CMD: begin
            if (mem_cmd_byte_addr != prefixed_instr_ptr) begin
               send_cmd();
            end
         end
         `STATE_WAIT: begin
            if (!mem_rd_empty) begin
               mem_rd_en <= 1;
               state <= `STATE_READ;
            end
         end
         `STATE_READ: begin
            instr <= mem_rd_data;
            state <= `STATE_CMD;
         end
      endcase
   end

   task send_cmd;
      begin
         mem_cmd_en <= 1;
         mem_cmd_byte_addr <= prefixed_instr_ptr;
         state <= `STATE_WAIT;
      end
   endtask

endmodule