data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_top.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_top.v:10: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_top.v:11: Cannot find include file: UART_defines.v\n`include "UART_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_top.v:34: Define or directive not defined: \'`ADDR_WIDTH\'\ninput [`ADDR_WIDTH-1:0] wb_addr_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_top.v:57: Define or directive not defined: \'`ADDR_WIDTH\'\nwire [`ADDR_WIDTH-1:0] wb_addr_i;\n      ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module UART_top	(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	stx_o, srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);


input		clk;


input		wb_rst_i;
input	[`ADDR_WIDTH-1:0]	wb_addr_i;
input	[7:0]	wb_dat_i;
output	[7:0]	wb_dat_o;
input		wb_we_i;
input		wb_stb_i;
input		wb_cyc_i;
output		wb_ack_o;
output		int_o;


input		srx_i;
output		stx_o;
output		rts_o;
input		cts_i;
output		dtr_o;
input		dsr_i;
input		ri_i;
input		dcd_i;

wire		stx_o;
wire		rts_o;
wire		dtr_o;

wire	[`ADDR_WIDTH-1:0]	wb_addr_i;
wire	[7:0]	wb_dat_i;
wire	[7:0]	wb_dat_o;

wire		we_o;

wire	[3:0]	ier;
wire	[7:0]	iir;
wire	[3:0]	fcr;
wire	[4:0]	mcr;
wire	[7:0]	lcr;
wire	[7:0]	lsr;	
wire	[7:0]	msr;
wire	[31:0]	dl;

wire		enable;






UART_wb		wb_interface(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),


		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),

		.we_o(		we_o		)
		);


UART_regs	regs(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_addr_i(	wb_addr_i	),
		.wb_dat_i(	wb_dat_i	),
		.wb_dat_o(	wb_dat_o	),
		.wb_we_i(	we_o		),
		.ier(		ier		),
		.iir(		iir		),
		.fcr(		fcr		),
		.mcr(		mcr		),
		.lcr(		lcr		),
		.lsr(		lsr		),
		.msr(		msr		),
		.dl(		dl		),
		.modem_inputs(	{cts_i, dsr_i,
				 ri_i,  dcd_i}	),
		.stx_o(		stx_o		),
		.srx_i(		srx_i		),
		.enable(	enable		),
		.rts_o(		rts_o		),
		.dtr_o(		dtr_o		)
		);

endmodule
module UART_top	(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	stx_o, srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);



input		clk;


input		wb_rst_i;
input	[`ADDR_WIDTH-1:0]	wb_addr_i;
input	[7:0]	wb_dat_i;
output	[7:0]	wb_dat_o;
input		wb_we_i;
input		wb_stb_i;
input		wb_cyc_i;
output		wb_ack_o;
output		int_o;


input		srx_i;
output		stx_o;
output		rts_o;
input		cts_i;
output		dtr_o;
input		dsr_i;
input		ri_i;
input		dcd_i;

wire		stx_o;
wire		rts_o;
wire		dtr_o;

wire	[`ADDR_WIDTH-1:0]	wb_addr_i;
wire	[7:0]	wb_dat_i;
wire	[7:0]	wb_dat_o;

wire		we_o;

wire	[3:0]	ier;
wire	[7:0]	iir;
wire	[3:0]	fcr;
wire	[4:0]	mcr;
wire	[7:0]	lcr;
wire	[7:0]	lsr;	
wire	[7:0]	msr;
wire	[31:0]	dl;

wire		enable;






UART_wb		wb_interface(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),


		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),

		.we_o(		we_o		)
		);


UART_regs	regs(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_addr_i(	wb_addr_i	),
		.wb_dat_i(	wb_dat_i	),
		.wb_dat_o(	wb_dat_o	),
		.wb_we_i(	we_o		),
		.ier(		ier		),
		.iir(		iir		),
		.fcr(		fcr		),
		.mcr(		mcr		),
		.lcr(		lcr		),
		.lsr(		lsr		),
		.msr(		msr		),
		.dl(		dl		),
		.modem_inputs(	{cts_i, dsr_i,
				 ri_i,  dcd_i}	),
		.stx_o(		stx_o		),
		.srx_i(		srx_i		),
		.enable(	enable		),
		.rts_o(		rts_o		),
		.dtr_o(		dtr_o		)
		);

endmodule