data/full_repos/permissive/406635962/src/rtl/exu_regfile.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:9: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] read_src1_idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:10: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] read_src2_idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:11: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] read_src1_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:12: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] read_src2_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:14: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] wbck_dest_idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:15: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] wbck_dest_data,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:18: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] x1_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:24: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf_r[`RFREG_NUM-1:0];\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:24: Define or directive not defined: \'`RFREG_NUM\'\nwire [`XLEN-1:0] rf_r[`RFREG_NUM-1:0];\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:25: Define or directive not defined: \'`RFREG_NUM\'\nwire [`RFREG_NUM-1:0] rf_wen;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:29: Define or directive not defined: \'`RFREG_NUM\'\n    for(i=0; i<`RFREG_NUM; i=i+1) begin:regfile\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for(i=0; i<`RFREG_NUM; i=i+1) begin:regfile\n                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:32: Define or directive not defined: \'`XLEN\'\n            assign rf_r[i] = `XLEN\'b0;          \n                             ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:33: syntax error, unexpected end\n        end        \n        ^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:36: Define or directive not defined: \'`XLEN\'\n            gnrl_dfflr #(`XLEN) rf_dfflr(rf_wen[i], wbck_dest_data, rf_r[i], clk, rst_n);\n                         ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:37: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_regfile.v:43: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module exu_regfile (
    input [`RFIDX_WIDTH-1:0] read_src1_idx,
    input [`RFIDX_WIDTH-1:0] read_src2_idx,
    output [`XLEN-1:0] read_src1_data,
    output [`XLEN-1:0] read_src2_data,
    
    input [`RFIDX_WIDTH-1:0] wbck_dest_idx,
    input [`XLEN-1:0] wbck_dest_data,
    input wbck_dest_ena,

    output [`XLEN-1:0] x1_data,

    input clk,
    input rst_n
);

wire [`XLEN-1:0] rf_r[`RFREG_NUM-1:0];
wire [`RFREG_NUM-1:0] rf_wen;

genvar i;
generate
    for(i=0; i<`RFREG_NUM; i=i+1) begin:regfile
        if(i==0) begin:x0
            assign rf_wen[i] = 1'b0;
            assign rf_r[i] = `XLEN'b0;          
        end        
        else begin:not_x0
            assign rf_wen[i] = wbck_dest_ena & (wbck_dest_idx == i);
            gnrl_dfflr #(`XLEN) rf_dfflr(rf_wen[i], wbck_dest_data, rf_r[i], clk, rst_n);
        end
    end
endgenerate
assign read_src1_data = rf_r[read_src1_idx];
assign read_src2_data = rf_r[read_src2_idx];
assign x1_data = rf_r[1];
endmodule
module exu_regfile (
    input [`RFIDX_WIDTH-1:0] read_src1_idx,
    input [`RFIDX_WIDTH-1:0] read_src2_idx,
    output [`XLEN-1:0] read_src1_data,
    output [`XLEN-1:0] read_src2_data,
    
    input [`RFIDX_WIDTH-1:0] wbck_dest_idx,
    input [`XLEN-1:0] wbck_dest_data,
    input wbck_dest_ena,

    output [`XLEN-1:0] x1_data,

    input clk,
    input rst_n
);


wire [`XLEN-1:0] rf_r[`RFREG_NUM-1:0];
wire [`RFREG_NUM-1:0] rf_wen;

genvar i;
generate
    for(i=0; i<`RFREG_NUM; i=i+1) begin:regfile
        if(i==0) begin:x0
            assign rf_wen[i] = 1'b0;
            assign rf_r[i] = `XLEN'b0;          
        end        
        else begin:not_x0
            assign rf_wen[i] = wbck_dest_ena & (wbck_dest_idx == i);
            gnrl_dfflr #(`XLEN) rf_dfflr(rf_wen[i], wbck_dest_data, rf_r[i], clk, rst_n);
        end
    end
endgenerate
assign read_src1_data = rf_r[read_src1_idx];
assign read_src2_data = rf_r[read_src2_idx];
assign x1_data = rf_r[1];
endmodule