data/full_repos/permissive/454159683/comp4b/comp4b.v
data/verilator_xmls/343f1fc7-6fba-4314-a16d-99884a0df39e.xml
module comp4b(input [3:0] a, b, output reg [1:0] out);
	always @(a or b)
	begin
		if (a > b) 
			out = 1;
		else if (a < b)
			out = 2;
		else
			out = 0;
	end
endmodule
module comp4b(input [3:0] a, b, output reg [1:0] out);

	always @(a or b)
	begin
		if (a > b) 
			out = 1;
		else if (a < b)
			out = 2;
		else
			out = 0;
	end
endmodule