data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #331;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #331 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #331 clk = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #331 clk = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n   #331 clk = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #331 clk = 1;\n   ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FPALU_tb();
	reg [31:0] a;
	reg [31:0] b;


	real      result;
	reg       clk;
	reg       rst_n;
	reg [1:0] opcode;
  
	wire          din_uni_a_sgn    = a[28];
	wire [5:0]    din_uni_a_exp    = a[27:22];
	wire [21:0]   din_uni_a_man_dn = a[21:0];
	wire          din_uni_b_sgn    = b[28];
	wire [5:0]    din_uni_b_exp    = b[27:22];
	wire [21:0]   din_uni_b_man_dn = b[21:0];
	wire          dout_uni_y_sgn;
	wire [5:0]    dout_uni_y_exp; 
	wire [21:0]   dout_uni_y_man_dn;

	reg [8:0] daddr;
	reg [5:0] caddr;
	wire [15:0] cin;
	wire [15:0] din;
	data_cmem_fp16 u_cmem_src(
		.a(caddr),
		.q(cin)
	);

	data_dmem_fp16 u_dmem_src(
		.a(daddr),
		.q(din)
	);

	`define DEBUGINFO
	FPALU dut(
		.clk(clk), .opcode(opcode),
		.din_uni_a_sgn     (din_uni_a_sgn    ),
		.din_uni_a_exp     (din_uni_a_exp    ),
		.din_uni_a_man_dn  (din_uni_a_man_dn ),
		.din_uni_b_sgn     (din_uni_b_sgn    ),
		.din_uni_b_exp     (din_uni_b_exp    ),
		.din_uni_b_man_dn  (din_uni_b_man_dn ),
		.dout_uni_y_sgn    (dout_uni_y_sgn   ),
		.dout_uni_y_exp    (dout_uni_y_exp   ),
		.dout_uni_y_man_dn (dout_uni_y_man_dn)
	);
	
	integer i;
	real dout_real;
	initial begin
		a = {$random};
		b = {$random};
		clk    = 0;
		caddr  = 0;
		daddr  = 0;

		#331;
		
		$dumpfile("dump.vcd");
		$dumpvars;
		#331 clk = 1;


		opcode = 2'b10;
		for(i=0;i<200;i=i+1) begin
			#331 clk = 0;
			caddr = caddr + 1;
			daddr = daddr + 1;
			a = {din[15], 1'b0, din[14:10], 12'b0, din[9:0]};
			b = {cin[15], 1'b0, cin[14:10], 12'b0, cin[9:0]};
			#331 clk = 1;
			dout_real = (1.0-2.0*dout_uni_y_sgn) * dout_uni_y_man_dn * 2.0**(-21.0 + dout_uni_y_exp - 31.0);
		end


		opcode = 2'b11;
		for(i=0;i<200;i=i+1) begin
			#331 clk = 0;
			a = {$random};
			b = {$random};
			#331 clk = 1;
		end
		$finish;
	end
endmodule
module FPALU_tb();

	reg [31:0] a;
	reg [31:0] b;


	real      result;
	reg       clk;
	reg       rst_n;
	reg [1:0] opcode;
  
	wire          din_uni_a_sgn    = a[28];
	wire [5:0]    din_uni_a_exp    = a[27:22];
	wire [21:0]   din_uni_a_man_dn = a[21:0];
	wire          din_uni_b_sgn    = b[28];
	wire [5:0]    din_uni_b_exp    = b[27:22];
	wire [21:0]   din_uni_b_man_dn = b[21:0];
	wire          dout_uni_y_sgn;
	wire [5:0]    dout_uni_y_exp; 
	wire [21:0]   dout_uni_y_man_dn;

	reg [8:0] daddr;
	reg [5:0] caddr;
	wire [15:0] cin;
	wire [15:0] din;
	data_cmem_fp16 u_cmem_src(
		.a(caddr),
		.q(cin)
	);

	data_dmem_fp16 u_dmem_src(
		.a(daddr),
		.q(din)
	);

	`define DEBUGINFO
	FPALU dut(
		.clk(clk), .opcode(opcode),
		.din_uni_a_sgn     (din_uni_a_sgn    ),
		.din_uni_a_exp     (din_uni_a_exp    ),
		.din_uni_a_man_dn  (din_uni_a_man_dn ),
		.din_uni_b_sgn     (din_uni_b_sgn    ),
		.din_uni_b_exp     (din_uni_b_exp    ),
		.din_uni_b_man_dn  (din_uni_b_man_dn ),
		.dout_uni_y_sgn    (dout_uni_y_sgn   ),
		.dout_uni_y_exp    (dout_uni_y_exp   ),
		.dout_uni_y_man_dn (dout_uni_y_man_dn)
	);
	
	integer i;
	real dout_real;
	initial begin
		a = {$random};
		b = {$random};
		clk    = 0;
		caddr  = 0;
		daddr  = 0;

		#331;
		
		$dumpfile("dump.vcd");
		$dumpvars;
		#331 clk = 1;


		opcode = 2'b10;
		for(i=0;i<200;i=i+1) begin
			#331 clk = 0;
			caddr = caddr + 1;
			daddr = daddr + 1;
			a = {din[15], 1'b0, din[14:10], 12'b0, din[9:0]};
			b = {cin[15], 1'b0, cin[14:10], 12'b0, cin[9:0]};
			#331 clk = 1;
			dout_real = (1.0-2.0*dout_uni_y_sgn) * dout_uni_y_man_dn * 2.0**(-21.0 + dout_uni_y_exp - 31.0);
		end


		opcode = 2'b11;
		for(i=0;i<200;i=i+1) begin
			#331 clk = 0;
			a = {$random};
			b = {$random};
			#331 clk = 1;
		end
		$finish;
	end
endmodule