data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:910: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n                                                                                    : ... In instance shifter_32bit.u5\n xor(zero,dir,dir);\n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:911: Cannot find file containing module: \'Decoder_2To4\'\n Decoder_2To4 d(.a(dir), .y(f));\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/Decoder_2To4\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/Decoder_2To4.v\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/Decoder_2To4.sv\n             Decoder_2To4\n             Decoder_2To4.v\n             Decoder_2To4.sv\n             obj_dir/Decoder_2To4\n             obj_dir/Decoder_2To4.v\n             obj_dir/Decoder_2To4.sv\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:687: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n                                                                                    : ... In instance shifter_32bit.u4\n xor(zero,dir,dir);\n    ^\n%Error: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:688: Cannot find file containing module: \'Decoder_2To4\'\n Decoder_2To4 d(.a(dir), .y(f));\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:464: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n                                                                                    : ... In instance shifter_32bit.u3\n xor(zero,dir,dir);\n    ^\n%Error: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:465: Cannot find file containing module: \'Decoder_2To4\'\n Decoder_2To4 d(.a(dir), .y(f));\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:241: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n                                                                                    : ... In instance shifter_32bit.u2\n xor(zero,dir,dir);\n    ^\n%Error: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:242: Cannot find file containing module: \'Decoder_2To4\'\n Decoder_2To4 d(.a(dir), .y(f));\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:18: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n                                                                                   : ... In instance shifter_32bit.u1\n xor(zero,dir,dir);\n    ^\n%Error: data/full_repos/permissive/428158935/sources_1/new/ShiftModule.v:19: Cannot find file containing module: \'Decoder_2To4\'\n Decoder_2To4 d(.a(dir), .y(f));\n ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 5 warning(s)\n'
module shifter_32bit(
    input [31:0] In,
    input [1:0]dir,
    input [4:0] bite,
    output  [31:0] result
    );
    wire[31:0] temp[3:0];
    shifter_1bit u1(.In(In), .dir(dir), .enable(bite[0]), .result(temp[0]));
    shifter_2bit u2(.In(temp[0]), .dir(dir), .enable(bite[1]), .result(temp[1]));
    shifter_4bit u3(.In(temp[1]), .dir(dir), .enable(bite[2]), .result(temp[2]));
    shifter_8bit u4(.In(temp[2]), .dir(dir), .enable(bite[3]), .result(temp[3]));
    shifter_16bit u5(.In(temp[3]), .dir(dir), .enable(bite[4]), .result(result));
endmodule
module shifter_32bit(
    input [31:0] In,
    input [1:0]dir,
    input [4:0] bite,
    output  [31:0] result
    );

    wire[31:0] temp[3:0];
    shifter_1bit u1(.In(In), .dir(dir), .enable(bite[0]), .result(temp[0]));
    shifter_2bit u2(.In(temp[0]), .dir(dir), .enable(bite[1]), .result(temp[1]));
    shifter_4bit u3(.In(temp[1]), .dir(dir), .enable(bite[2]), .result(temp[2]));
    shifter_8bit u4(.In(temp[2]), .dir(dir), .enable(bite[3]), .result(temp[3]));
    shifter_16bit u5(.In(temp[3]), .dir(dir), .enable(bite[4]), .result(result));
endmodule