data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:36: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:49: Define or directive not defined: \'`ARBITER_TYPE_ROUND_ROBIN_BINARY\'\n   parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                                                            ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:51: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_alloc_mac.v:357: Define or directive not defined: \'`BINARY_OP_OR\'\n       .op(`BINARY_OP_OR))\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module whr_alloc_mac
  (clk, reset, route_ip_op, req_ip, req_head_ip, req_tail_ip, gnt_ip, 
   flit_valid_op, flit_head_op, flit_tail_op, xbr_ctrl_op_ip, elig_op, full_op);
   
`include "c_constants.v"
`include "c_functions.v"
   

   parameter num_ports = 5;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter precomp_ip_sel = 1;
   

   parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:num_ports*num_ports-1] route_ip_op;
   

   input [0:num_ports-1] 	   req_ip;
   

   input [0:num_ports-1] 	   req_head_ip;
   

   input [0:num_ports-1] 	   req_tail_ip;
   

   output [0:num_ports-1] 	   gnt_ip;
   wire [0:num_ports-1] 	   gnt_ip;
   

   output [0:num_ports-1] 	   flit_valid_op;
   wire [0:num_ports-1] 	   flit_valid_op;
   

   output [0:num_ports-1] 	   flit_head_op;
   wire [0:num_ports-1] 	   flit_head_op;
   

   output [0:num_ports-1] 	   flit_tail_op;
   wire [0:num_ports-1] 	   flit_tail_op;
   

   output [0:num_ports*num_ports-1] xbr_ctrl_op_ip;
   wire [0:num_ports*num_ports-1]   xbr_ctrl_op_ip;
   

   input [0:num_ports-1] 	    elig_op;
   

   input [0:num_ports-1] 	    full_op;
   
   



   
   wire [0:num_ports*num_ports-1]   route_op_ip;
   c_interleave
     #(.width(num_ports*num_ports),
       .num_blocks(num_ports))
   route_op_ip_intl
     (.data_in(route_ip_op),
      .data_out(route_op_ip));
   
   wire [0:num_ports*num_ports-1]   gnt_op_ip;
   
   genvar 			    op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   



	   
	   wire [0:num_ports-1] route_ip;
	   assign route_ip = route_op_ip[op*num_ports:(op+1)*num_ports-1];
	   
	   wire 		elig;
	   assign elig = elig_op[op];
	   
	   wire 		full;
	   assign full = full_op[op];
	   
	   wire [0:num_ports-1] gnt_ip;
	   assign gnt_op_ip[op*num_ports:(op+1)*num_ports-1] = gnt_ip;
	   
	   wire 		flit_valid;
	   assign flit_valid_op[op] = flit_valid;
	   
	   wire 		flit_head;
	   assign flit_head_op[op] = flit_head;
	   
	   wire 		flit_tail;
	   assign flit_tail_op[op] = flit_tail;
	   
	   wire [0:num_ports-1] xbr_ctrl_ip;
	   assign xbr_ctrl_op_ip[op*num_ports:(op+1)*num_ports-1] = xbr_ctrl_ip;
	   
	   



	   
	   wire [0:num_ports-1] arb_req_ip;
	   assign arb_req_ip = req_ip & route_ip;
	   
	   





	   
	   wire 		arb_active;
	   assign arb_active = |arb_req_ip;
	   
	   wire [0:num_ports-1] hold_gnt_ip;
	   assign hold_gnt_ip = arb_req_ip & ~req_head_ip;
	   
	   wire [0:num_ports-1] arb_gnt_ip;
	   
	   wire 		gnt;
	   
	   if(precomp_ip_sel)
	     begin
		
		wire [0:num_ports-1] prio_ip;
		
		wire [0:num_ports-1] mgnt_ip;
		c_prefix_arbiter_base
		  #(.num_ports(num_ports))
		opab
		  (.prio_port(prio_ip),
		   .req(arb_req_ip),
		   .gnt(mgnt_ip));
		
		wire 		     update;
		assign update
		  = (|(hold_gnt_ip & req_tail_ip) | (elig & |arb_req_ip)) & 
		    ~full;
		
		wire [0:port_idx_width-1] next_port;
		c_encode
		  #(.num_ports(num_ports))
		next_port_enc
		  (.data_in(mgnt_ip),
		   .data_out(next_port));
		
		wire [0:port_idx_width-1] presel_s, presel_q;
		assign presel_s = update ? next_port : presel_q;
		c_dff
		  #(.width(port_idx_width),
		    .reset_type(reset_type))
		preselq
		  (.clk(clk),
		   .reset(reset),
		   .active(arb_active),
		   .d(presel_s),
		   .q(presel_q));
		
		c_decode
		  #(.num_ports(num_ports),
		    .offset(num_ports-1))
		prio_ip_dec
		  (.data_in(presel_q),
		   .data_out(prio_ip));
		
		wire [0:num_ports-1] 	  presel_ip;
		c_decode
		  #(.num_ports(num_ports))
		presel_ip_dec
		  (.data_in(presel_q),
		   .data_out(presel_ip));
		
		wire [0:num_ports-1] 	  gnt_presel_ip;
		assign gnt_presel_ip = arb_req_ip & presel_ip;
		
		wire [0:num_ports-1] 	  gnt_onehot_ip;
		c_one_hot_filter
		  #(.width(num_ports))
		oohf
		  (.data_in(arb_req_ip),
		   .data_out(gnt_onehot_ip));
		





		
		assign arb_gnt_ip = gnt_presel_ip | gnt_onehot_ip;
		
		assign gnt
		  = ((elig & |arb_gnt_ip) | |(arb_req_ip & ~req_head_ip)) & 
		    ~full;
		
	     end
	   else
	     begin
		
		wire arb_update;
		assign arb_update = |arb_req_ip & elig & ~full;
		
		c_arbiter
		  #(.num_ports(num_ports),
		    .num_priorities(1),
		    .arbiter_type(arbiter_type),
		    .reset_type(reset_type))
		arb
		  (.clk(clk),
		   .reset(reset),
		   .active(arb_active),
		   .update(arb_update),
		   .req_pr(arb_req_ip),
		   .gnt_pr(arb_gnt_ip),
		   .gnt());
		
		assign gnt
		  = |(arb_req_ip & (~req_head_ip | {num_ports{elig}})) & ~full;
		
	     end
	   
	   wire [0:num_ports-1] raw_gnt_ip;
	   assign raw_gnt_ip = elig ? arb_gnt_ip : hold_gnt_ip;
	   
	   assign gnt_ip = raw_gnt_ip & {num_ports{~full}};
	   
	   wire 		gnt_head;
	   assign gnt_head = elig;
	   
	   wire 		gnt_tail;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   gnt_tail_sel
	     (.select(raw_gnt_ip),
	      .data_in(req_tail_ip),
	      .data_out(gnt_tail));
	   
	   wire 		xbr_ctrl_active;
	   assign xbr_ctrl_active = arb_active | (|xbr_ctrl_ip);
	   
	   wire [0:num_ports-1] xbr_ctrl_ip_s, xbr_ctrl_ip_q;
	   assign xbr_ctrl_ip_s = raw_gnt_ip;
	   c_dff
	     #(.width(num_ports),
	       .reset_type(reset_type))
	   xbr_ctrl_ipq
	     (.clk(clk),
	      .reset(reset),
	      .active(xbr_ctrl_active),
	      .d(xbr_ctrl_ip_s),
	      .q(xbr_ctrl_ip_q));
	   
	   assign xbr_ctrl_ip = xbr_ctrl_ip_q;
	   
	   wire 		flit_valid_s, flit_valid_q;
	   assign flit_valid_s = gnt;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_validq
	     (.clk(clk),
	      .reset(reset),
	      .active(xbr_ctrl_active),
	      .d(flit_valid_s),
	      .q(flit_valid_q));
	   
	   assign flit_valid = flit_valid_q;
	   
	   wire 		flit_head_s, flit_head_q;
	   assign flit_head_s = gnt_head;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_headq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(arb_active),
	      .d(flit_head_s),
	      .q(flit_head_q));
	   
	   assign flit_head = flit_head_q;
	   
	   wire 		flit_tail_s, flit_tail_q;
	   assign flit_tail_s = gnt_tail;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_tailq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(arb_active),
	      .d(flit_tail_s),
	      .q(flit_tail_q));
	   
	   assign flit_tail = flit_tail_q;
	   
	end
      
   endgenerate
   
   



   
   c_binary_op
     #(.num_ports(num_ports),
       .width(num_ports),
       .op(`BINARY_OP_OR))
   gnt_ip_or
     (.data_in(gnt_op_ip),
      .data_out(gnt_ip));
   
endmodule
module whr_alloc_mac
  (clk, reset, route_ip_op, req_ip, req_head_ip, req_tail_ip, gnt_ip, 
   flit_valid_op, flit_head_op, flit_tail_op, xbr_ctrl_op_ip, elig_op, full_op);

   
`include "c_constants.v"
`include "c_functions.v"
   

   parameter num_ports = 5;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter precomp_ip_sel = 1;
   

   parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:num_ports*num_ports-1] route_ip_op;
   

   input [0:num_ports-1] 	   req_ip;
   

   input [0:num_ports-1] 	   req_head_ip;
   

   input [0:num_ports-1] 	   req_tail_ip;
   

   output [0:num_ports-1] 	   gnt_ip;
   wire [0:num_ports-1] 	   gnt_ip;
   

   output [0:num_ports-1] 	   flit_valid_op;
   wire [0:num_ports-1] 	   flit_valid_op;
   

   output [0:num_ports-1] 	   flit_head_op;
   wire [0:num_ports-1] 	   flit_head_op;
   

   output [0:num_ports-1] 	   flit_tail_op;
   wire [0:num_ports-1] 	   flit_tail_op;
   

   output [0:num_ports*num_ports-1] xbr_ctrl_op_ip;
   wire [0:num_ports*num_ports-1]   xbr_ctrl_op_ip;
   

   input [0:num_ports-1] 	    elig_op;
   

   input [0:num_ports-1] 	    full_op;
   
   



   
   wire [0:num_ports*num_ports-1]   route_op_ip;
   c_interleave
     #(.width(num_ports*num_ports),
       .num_blocks(num_ports))
   route_op_ip_intl
     (.data_in(route_ip_op),
      .data_out(route_op_ip));
   
   wire [0:num_ports*num_ports-1]   gnt_op_ip;
   
   genvar 			    op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   



	   
	   wire [0:num_ports-1] route_ip;
	   assign route_ip = route_op_ip[op*num_ports:(op+1)*num_ports-1];
	   
	   wire 		elig;
	   assign elig = elig_op[op];
	   
	   wire 		full;
	   assign full = full_op[op];
	   
	   wire [0:num_ports-1] gnt_ip;
	   assign gnt_op_ip[op*num_ports:(op+1)*num_ports-1] = gnt_ip;
	   
	   wire 		flit_valid;
	   assign flit_valid_op[op] = flit_valid;
	   
	   wire 		flit_head;
	   assign flit_head_op[op] = flit_head;
	   
	   wire 		flit_tail;
	   assign flit_tail_op[op] = flit_tail;
	   
	   wire [0:num_ports-1] xbr_ctrl_ip;
	   assign xbr_ctrl_op_ip[op*num_ports:(op+1)*num_ports-1] = xbr_ctrl_ip;
	   
	   



	   
	   wire [0:num_ports-1] arb_req_ip;
	   assign arb_req_ip = req_ip & route_ip;
	   
	   





	   
	   wire 		arb_active;
	   assign arb_active = |arb_req_ip;
	   
	   wire [0:num_ports-1] hold_gnt_ip;
	   assign hold_gnt_ip = arb_req_ip & ~req_head_ip;
	   
	   wire [0:num_ports-1] arb_gnt_ip;
	   
	   wire 		gnt;
	   
	   if(precomp_ip_sel)
	     begin
		
		wire [0:num_ports-1] prio_ip;
		
		wire [0:num_ports-1] mgnt_ip;
		c_prefix_arbiter_base
		  #(.num_ports(num_ports))
		opab
		  (.prio_port(prio_ip),
		   .req(arb_req_ip),
		   .gnt(mgnt_ip));
		
		wire 		     update;
		assign update
		  = (|(hold_gnt_ip & req_tail_ip) | (elig & |arb_req_ip)) & 
		    ~full;
		
		wire [0:port_idx_width-1] next_port;
		c_encode
		  #(.num_ports(num_ports))
		next_port_enc
		  (.data_in(mgnt_ip),
		   .data_out(next_port));
		
		wire [0:port_idx_width-1] presel_s, presel_q;
		assign presel_s = update ? next_port : presel_q;
		c_dff
		  #(.width(port_idx_width),
		    .reset_type(reset_type))
		preselq
		  (.clk(clk),
		   .reset(reset),
		   .active(arb_active),
		   .d(presel_s),
		   .q(presel_q));
		
		c_decode
		  #(.num_ports(num_ports),
		    .offset(num_ports-1))
		prio_ip_dec
		  (.data_in(presel_q),
		   .data_out(prio_ip));
		
		wire [0:num_ports-1] 	  presel_ip;
		c_decode
		  #(.num_ports(num_ports))
		presel_ip_dec
		  (.data_in(presel_q),
		   .data_out(presel_ip));
		
		wire [0:num_ports-1] 	  gnt_presel_ip;
		assign gnt_presel_ip = arb_req_ip & presel_ip;
		
		wire [0:num_ports-1] 	  gnt_onehot_ip;
		c_one_hot_filter
		  #(.width(num_ports))
		oohf
		  (.data_in(arb_req_ip),
		   .data_out(gnt_onehot_ip));
		





		
		assign arb_gnt_ip = gnt_presel_ip | gnt_onehot_ip;
		
		assign gnt
		  = ((elig & |arb_gnt_ip) | |(arb_req_ip & ~req_head_ip)) & 
		    ~full;
		
	     end
	   else
	     begin
		
		wire arb_update;
		assign arb_update = |arb_req_ip & elig & ~full;
		
		c_arbiter
		  #(.num_ports(num_ports),
		    .num_priorities(1),
		    .arbiter_type(arbiter_type),
		    .reset_type(reset_type))
		arb
		  (.clk(clk),
		   .reset(reset),
		   .active(arb_active),
		   .update(arb_update),
		   .req_pr(arb_req_ip),
		   .gnt_pr(arb_gnt_ip),
		   .gnt());
		
		assign gnt
		  = |(arb_req_ip & (~req_head_ip | {num_ports{elig}})) & ~full;
		
	     end
	   
	   wire [0:num_ports-1] raw_gnt_ip;
	   assign raw_gnt_ip = elig ? arb_gnt_ip : hold_gnt_ip;
	   
	   assign gnt_ip = raw_gnt_ip & {num_ports{~full}};
	   
	   wire 		gnt_head;
	   assign gnt_head = elig;
	   
	   wire 		gnt_tail;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   gnt_tail_sel
	     (.select(raw_gnt_ip),
	      .data_in(req_tail_ip),
	      .data_out(gnt_tail));
	   
	   wire 		xbr_ctrl_active;
	   assign xbr_ctrl_active = arb_active | (|xbr_ctrl_ip);
	   
	   wire [0:num_ports-1] xbr_ctrl_ip_s, xbr_ctrl_ip_q;
	   assign xbr_ctrl_ip_s = raw_gnt_ip;
	   c_dff
	     #(.width(num_ports),
	       .reset_type(reset_type))
	   xbr_ctrl_ipq
	     (.clk(clk),
	      .reset(reset),
	      .active(xbr_ctrl_active),
	      .d(xbr_ctrl_ip_s),
	      .q(xbr_ctrl_ip_q));
	   
	   assign xbr_ctrl_ip = xbr_ctrl_ip_q;
	   
	   wire 		flit_valid_s, flit_valid_q;
	   assign flit_valid_s = gnt;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_validq
	     (.clk(clk),
	      .reset(reset),
	      .active(xbr_ctrl_active),
	      .d(flit_valid_s),
	      .q(flit_valid_q));
	   
	   assign flit_valid = flit_valid_q;
	   
	   wire 		flit_head_s, flit_head_q;
	   assign flit_head_s = gnt_head;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_headq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(arb_active),
	      .d(flit_head_s),
	      .q(flit_head_q));
	   
	   assign flit_head = flit_head_q;
	   
	   wire 		flit_tail_s, flit_tail_q;
	   assign flit_tail_s = gnt_tail;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   flit_tailq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(arb_active),
	      .d(flit_tail_s),
	      .q(flit_tail_q));
	   
	   assign flit_tail = flit_tail_q;
	   
	end
      
   endgenerate
   
   



   
   c_binary_op
     #(.num_ports(num_ports),
       .width(num_ports),
       .op(`BINARY_OP_OR))
   gnt_ip_or
     (.data_in(gnt_op_ip),
      .data_out(gnt_ip));
   
endmodule