data/full_repos/permissive/434840709/作业/3位计数器/cg.v
data/verilator_xmls/f42a3b7b-4a8a-4211-9184-abfdd11dc5e3.xml
module top_module( 

                input [2:0] in,

                output [1:0] out 

        );

assign out = in[0]+in[1]+in[2];

endmodule
module top_module( 

                input [2:0] in,

                output [1:0] out 

        );


assign out = in[0]+in[1]+in[2];

endmodule