data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v
1: b'%Error: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:17: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " reset=%b, rdy=%b, rw=%b, oe=%b, we=%b, present_state=%d", reset, rdy, rw, oe, we, present_state);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("memory_interface_FSM.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, memory_interface_FSM_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #0 clk=0; reset=1; rdy=0; rw=0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #50 clk=~clk; reset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 1 : 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #50 clk=~clk; rdy=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501880753/memory_interface_FSM_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 0 : 1;\n            ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_interface_FSM_tb ();

	reg clk, reset, rdy, rw;
	wire oe, we;
	wire [1:0] present_state;

memory_interface_FSM DUT (.clk(clk), .reset(reset), .rdy(rdy), .rw(rw), .oe(oe), .we(we), .present_state(present_state));

	initial
      begin
        $monitor($time, " reset=%b, rdy=%b, rw=%b, oe=%b, we=%b, present_state=%d", reset, rdy, rw, oe, we, present_state);
      end

  	integer i = 0;

	initial
      begin
        $dumpfile("memory_interface_FSM.vcd");
        $dumpvars(1, memory_interface_FSM_tb);

        #0 clk=0; reset=1; rdy=0; rw=0;
        #50 clk=~clk; reset=0;

        for (i=0; i<30; i=i+1)
          begin
            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 1 : 0;
          end

        #50 clk=~clk; rdy=0;

        for (i=0; i<50; i=i+1)
          begin
            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 0 : 1;
          end

      end

endmodule
module memory_interface_FSM_tb ();


	reg clk, reset, rdy, rw;
	wire oe, we;
	wire [1:0] present_state;

memory_interface_FSM DUT (.clk(clk), .reset(reset), .rdy(rdy), .rw(rw), .oe(oe), .we(we), .present_state(present_state));

	initial
      begin
        $monitor($time, " reset=%b, rdy=%b, rw=%b, oe=%b, we=%b, present_state=%d", reset, rdy, rw, oe, we, present_state);
      end

  	integer i = 0;

	initial
      begin
        $dumpfile("memory_interface_FSM.vcd");
        $dumpvars(1, memory_interface_FSM_tb);

        #0 clk=0; reset=1; rdy=0; rw=0;
        #50 clk=~clk; reset=0;

        for (i=0; i<30; i=i+1)
          begin
            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 1 : 0;
          end

        #50 clk=~clk; rdy=0;

        for (i=0; i<50; i=i+1)
          begin
            #50 clk=~clk; rdy = (i > 5 && i < 20) ? 1 : 0; rw = (i > 2) ? 0 : 1;
          end

      end

endmodule