data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/peripheral.v
1: b"%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/peripheral.v:45: Cannot find file containing module: 'ultrasonic'\n ultrasonic  ut ( .clk(clk), .rst_n(rst_n), .signal(signal) , .value(value) , .done(done) );\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic\n             data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic.sv\n             ultrasonic\n             ultrasonic.v\n             ultrasonic.sv\n             obj_dir/ultrasonic\n             obj_dir/ultrasonic.v\n             obj_dir/ultrasonic.sv\n%Error: Exiting due to 1 error(s)\n"
module peripheral_ult(
	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	input 			signal,
	
	output reg [15:0] d_out
	);
	


	reg [1:0] 		s;

	wire 			rst_n = ~rst ;
    wire [15:0] 	value ; 
    wire 			done ;



	always @(*) begin
		case (addr)
			4'h0:		s = (cs && rd) ? 2'b01 : 2'b00 ;
			4'h2:		s = (cs && rd) ? 2'b10 : 2'b00 ;
			default: 	s = 2'b00 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			2'b01:	 	d_out[0] 	= done ;
			2'b10: 		d_out    	= value[15:0] ;
			default:	d_out   	= 0 ;
		endcase
	end

	ultrasonic  ut ( .clk(clk), .rst_n(rst_n), .signal(signal) , .value(value) , .done(done) );

endmodule
module peripheral_ult(
	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	input 			signal,
	
	output reg [15:0] d_out
	);

	


	reg [1:0] 		s;

	wire 			rst_n = ~rst ;
    wire [15:0] 	value ; 
    wire 			done ;



	always @(*) begin
		case (addr)
			4'h0:		s = (cs && rd) ? 2'b01 : 2'b00 ;
			4'h2:		s = (cs && rd) ? 2'b10 : 2'b00 ;
			default: 	s = 2'b00 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			2'b01:	 	d_out[0] 	= done ;
			2'b10: 		d_out    	= value[15:0] ;
			default:	d_out   	= 0 ;
		endcase
	end

	ultrasonic  ut ( .clk(clk), .rst_n(rst_n), .signal(signal) , .value(value) , .done(done) );

endmodule