data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:62: syntax error, unexpected \'@\'\n     repeat(5)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:64: syntax error, unexpected \'@\'\n     repeat(1)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:67: syntax error, unexpected \'@\'\n  repeat(8050)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:72: syntax error, unexpected \'@\'\n  repeat(500000)@(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/41989639/american_put_cyclone/src/amer_put_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module amer_put_tb;


	reg clk;
	reg nrst;
	reg start_s1;
	reg start_s2;
	reg [63:0] plus;
	reg [63:0] minus;
	reg [63:0] K_over_S;
	reg [63:0] p_up;
	reg [63:0] p_down;
	

	wire [63:0] result;
	

	amer_put uut (
		.clk(clk),
		.nrst(nrst),
		.start_s1(start_s1),
		.start_s2(start_s2),
		.p_up(p_up),
		.p_down(p_down),
		.log_lambda_up(plus),
		.log_lambda_down(minus),
		.K_over_S(K_over_S),
		.result(result)
	);
	
	initial begin

		clk    = 0;
		nrst   = 0;
		start_s1  = 0;
		start_s2  = 0;

		K_over_S <= 64'h3ff0000000000000;
	    plus    <= 64'h3f8030dc4ea03a72;
	    minus   <= 64'hbf8030dc4ea03a72;
	    p_up    <= 64'h3fdfe9e61a77116f;
	    p_down  <= 64'h3fe00af7fa15cd9b;







		#100;
		nrst <= 1'b1;
		

	    repeat(5)@(posedge clk);
		start_s1 <= 1'b1;
	    repeat(1)@(posedge clk);
		start_s1 <= 1'b0;
	    
		repeat(8050)@(posedge clk);



	    
		repeat(500000)@(posedge clk);

		
       
	end
	

	initial begin
	#20
	forever clk = #20 ~clk; 		
	end

      
endmodule
module amer_put_tb;



	reg clk;
	reg nrst;
	reg start_s1;
	reg start_s2;
	reg [63:0] plus;
	reg [63:0] minus;
	reg [63:0] K_over_S;
	reg [63:0] p_up;
	reg [63:0] p_down;
	

	wire [63:0] result;
	

	amer_put uut (
		.clk(clk),
		.nrst(nrst),
		.start_s1(start_s1),
		.start_s2(start_s2),
		.p_up(p_up),
		.p_down(p_down),
		.log_lambda_up(plus),
		.log_lambda_down(minus),
		.K_over_S(K_over_S),
		.result(result)
	);
	
	initial begin

		clk    = 0;
		nrst   = 0;
		start_s1  = 0;
		start_s2  = 0;

		K_over_S <= 64'h3ff0000000000000;
	    plus    <= 64'h3f8030dc4ea03a72;
	    minus   <= 64'hbf8030dc4ea03a72;
	    p_up    <= 64'h3fdfe9e61a77116f;
	    p_down  <= 64'h3fe00af7fa15cd9b;







		#100;
		nrst <= 1'b1;
		

	    repeat(5)@(posedge clk);
		start_s1 <= 1'b1;
	    repeat(1)@(posedge clk);
		start_s1 <= 1'b0;
	    
		repeat(8050)@(posedge clk);



	    
		repeat(500000)@(posedge clk);

		
       
	end
	

	initial begin
	#20
	forever clk = #20 ~clk; 		
	end

      
endmodule