data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:27: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:29: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:31: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:35: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:38: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:40: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:43: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:46: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/489994352/Image-Part-v2/rtl/conv1_tb.v:48: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module conv1_tb();
parameter data_width = 16;
wire [9*data_width-1:0] data_out;
reg [data_width-1:0] data_outmem [0:9-1];
wire      full;
wire      empty;
reg [data_width-1:0]  data_in;
reg      clk;
reg      rst;
reg      wr_en;
reg      rd_en;
fifo_conv1 fifo_conv1 (data_out,full,empty,data_in,clk,rst,wr_en,rd_en);
integer i,j;
always @(*)
for (i=0; i<9; i=i+1) begin
    data_outmem[i]<=data_out[i*16+:16];
end


reg [15:0] inpimg [0:224*224*3-1];
initial begin
    $readmemh("../data/inpf.txt",inpimg);
end
always #5 clk = ~clk;
initial begin
    clk = 0;
    @(posedge clk);
    rst = 1;
    @(posedge clk);
    rst = 0;
    @(posedge clk);
    wr_en = 1;
    for (j=0; j<(224*2)+3;j=j+1) begin
        data_in = inpimg[j];
        @(posedge clk);
    end
    wr_en = 0;
    @(posedge clk);
    rd_en = 1;
    @(posedge clk);
    @(posedge clk);
    rd_en=0;
    @(posedge clk);
    wr_en = 1;
    data_in = inpimg[452];
    @(posedge clk);
    wr_en = 0;
    @(posedge clk);
    $stop;
end





endmodule
module conv1_tb();

parameter data_width = 16;
wire [9*data_width-1:0] data_out;
reg [data_width-1:0] data_outmem [0:9-1];
wire      full;
wire      empty;
reg [data_width-1:0]  data_in;
reg      clk;
reg      rst;
reg      wr_en;
reg      rd_en;
fifo_conv1 fifo_conv1 (data_out,full,empty,data_in,clk,rst,wr_en,rd_en);
integer i,j;
always @(*)
for (i=0; i<9; i=i+1) begin
    data_outmem[i]<=data_out[i*16+:16];
end


reg [15:0] inpimg [0:224*224*3-1];
initial begin
    $readmemh("../data/inpf.txt",inpimg);
end
always #5 clk = ~clk;
initial begin
    clk = 0;
    @(posedge clk);
    rst = 1;
    @(posedge clk);
    rst = 0;
    @(posedge clk);
    wr_en = 1;
    for (j=0; j<(224*2)+3;j=j+1) begin
        data_in = inpimg[j];
        @(posedge clk);
    end
    wr_en = 0;
    @(posedge clk);
    rd_en = 1;
    @(posedge clk);
    @(posedge clk);
    rd_en=0;
    @(posedge clk);
    wr_en = 1;
    data_in = inpimg[452];
    @(posedge clk);
    wr_en = 0;
    @(posedge clk);
    $stop;
end





endmodule