data/full_repos/permissive/506268796/main.v
1: b'%Error: data/full_repos/permissive/506268796/main.v:1: Cannot find include file: M.v\n`include "M.v" \n         ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/506268796,data/full_repos/permissive/506268796/M.v\n             data/full_repos/permissive/506268796,data/full_repos/permissive/506268796/M.v.v\n             data/full_repos/permissive/506268796,data/full_repos/permissive/506268796/M.v.sv\n             M.v\n             M.v.v\n             M.v.sv\n             obj_dir/M.v\n             obj_dir/M.v.v\n             obj_dir/M.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/506268796/main.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/506268796/main.v:46: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("log.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/506268796/main.v:47: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/506268796/main.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #300 rst <= 0; clk64 <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/506268796/main.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1300 b <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/506268796/main.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #200000 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module main();

    reg S, R, clk, rst, b;
    wire rst2;
    wire out, ready;
    wire pos, neg;
    wire Q, Q1;
    
    reg [3:0] dataCnt;
    reg [23:0] data [5:0];
    
    reg [5:0] clk64;
    
    wire [23:0] pixel;
    wire [4:0] address;
    wire transmitter_clk;
    wire out_clk;
    
    assign pixel = data[address];
    
    spiclkgen clk_gen(.clk(clk), .rst(rst), .clk_dvd(transmitter_clk), .shifted(out_clk), .mreset(rst2));    

    linespitransmitter lt(.clk(transmitter_clk), .rst(rst2), .pixel_count(4), .pixel({8'hFF, pixel}), .address(address), .out(out), .done(ready));
    
    always begin
        #10 clk <= ~clk;
    end
    
    always @(posedge ready) begin
        dataCnt <= dataCnt + 1;
    end
    
    always @(posedge clk) begin
        clk64 <= clk64 + 1;
    end
    
    initial begin
        data[0] <= 24'hAAAAAA;
        data[1] <= 24'hCCCCCC;
        data[2] <= 24'hAAAAAA;
        data[3] <= 24'h111111;
        data[4] <= 24'h222222;
        data[5] <= 24'h333333;
        $dumpfile("log.vcd");
        $dumpvars;
        dataCnt <= 0;
        clk64<= 0;
        b <= 1;
        clk <= 0;
        rst <= 1;
        #300 rst <= 0; clk64 <= 0;
        #1300 b <= 0;
        #200000 $finish;
    end
   
endmodule
module main();


    reg S, R, clk, rst, b;
    wire rst2;
    wire out, ready;
    wire pos, neg;
    wire Q, Q1;
    
    reg [3:0] dataCnt;
    reg [23:0] data [5:0];
    
    reg [5:0] clk64;
    
    wire [23:0] pixel;
    wire [4:0] address;
    wire transmitter_clk;
    wire out_clk;
    
    assign pixel = data[address];
    
    spiclkgen clk_gen(.clk(clk), .rst(rst), .clk_dvd(transmitter_clk), .shifted(out_clk), .mreset(rst2));    

    linespitransmitter lt(.clk(transmitter_clk), .rst(rst2), .pixel_count(4), .pixel({8'hFF, pixel}), .address(address), .out(out), .done(ready));
    
    always begin
        #10 clk <= ~clk;
    end
    
    always @(posedge ready) begin
        dataCnt <= dataCnt + 1;
    end
    
    always @(posedge clk) begin
        clk64 <= clk64 + 1;
    end
    
    initial begin
        data[0] <= 24'hAAAAAA;
        data[1] <= 24'hCCCCCC;
        data[2] <= 24'hAAAAAA;
        data[3] <= 24'h111111;
        data[4] <= 24'h222222;
        data[5] <= 24'h333333;
        $dumpfile("log.vcd");
        $dumpvars;
        dataCnt <= 0;
        clk64<= 0;
        b <= 1;
        clk <= 0;
        rst <= 1;
        #300 rst <= 0; clk64 <= 0;
        #1300 b <= 0;
        #200000 $finish;
    end
   
endmodule