data/full_repos/permissive/519309743/circuito-parte4.v
1: b"%Error: data/full_repos/permissive/519309743/circuito-parte4.v:1: syntax error, unexpected ';', expecting ')' or ','\nmodule controlador (clk,ch_vm,enb_3,Vint_z,qs,qes,qees,rstn,se,see,seee ;\n                                                                        ^\n%Error: data/full_repos/permissive/519309743/circuito-parte4.v:5: syntax error, unexpected output\n     output reg [3:0] se,see,seee;\n     ^~~~~~\n%Error: data/full_repos/permissive/519309743/circuito-parte4.v:12: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module controlador (clk,ch_vm,enb_3,Vint_z,qs,qes,qees,rstn,se,see,seee ;
	input clk,ch_vm,enb_3,Vint_z;
    	input [3:0] qs,qes,qees;
	output reg rstn;
   	 output reg [3:0] se,see,seee;
  	reg [1:0] state;
  	reg ch_ref,ch_zr;
	parameter a = 2'b00,
		      b = 2'b01,
		      c = 2'b10,
		      d = 2'b11;
	initial begin
      		rstn = 1'b1;
		state = a;
	end
	always@(negedge clk)begin
		case(state)
			a: begin
          				if(ch_vm == 1'b1)begin 

					ch_zr <= 1'b0;
					state <= b;
         			end
			else 
				state <=a;
			end
			b: begin
          				if(enb_3 == 1'b1)begin 

					state <= c;
				end
				else
					state <= b;
			end
			c: begin
         				if(Vint_z == 1'b1)begin 

					se <= qs;
					see <= qes;
					seee <= qees;
					ch_zr <= 1'b1;
					state <= d;
         				end	
				else
					state <= c;
			end
			d: begin
         				 if(ch_vm == 1'b1) 

					state <= a;
				else
					state <= d;
			end
		endcase
	end
	

always @(state) begin
		case(state)
          			b: begin
            				rstn =1'b0;
          			end
			c: begin 
				ch_ref = 1'b1;
			end
			d: begin
				rstn = 1'b1;
			end
		endcase
	end
endmodule
module controlador (clk,ch_vm,enb_3,Vint_z,qs,qes,qees,rstn,se,see,seee ;

	input clk,ch_vm,enb_3,Vint_z;
    	input [3:0] qs,qes,qees;
	output reg rstn;
   	 output reg [3:0] se,see,seee;
  	reg [1:0] state;
  	reg ch_ref,ch_zr;
	parameter a = 2'b00,
		      b = 2'b01,
		      c = 2'b10,
		      d = 2'b11;
	initial begin
      		rstn = 1'b1;
		state = a;
	end
	always@(negedge clk)begin
		case(state)
			a: begin
          				if(ch_vm == 1'b1)begin 

					ch_zr <= 1'b0;
					state <= b;
         			end
			else 
				state <=a;
			end
			b: begin
          				if(enb_3 == 1'b1)begin 

					state <= c;
				end
				else
					state <= b;
			end
			c: begin
         				if(Vint_z == 1'b1)begin 

					se <= qs;
					see <= qes;
					seee <= qees;
					ch_zr <= 1'b1;
					state <= d;
         				end	
				else
					state <= c;
			end
			d: begin
         				 if(ch_vm == 1'b1) 

					state <= a;
				else
					state <= d;
			end
		endcase
	end
	

always @(state) begin
		case(state)
          			b: begin
            				rstn =1'b0;
          			end
			c: begin 
				ch_ref = 1'b1;
			end
			d: begin
				rstn = 1'b1;
			end
		endcase
	end
endmodule