data/full_repos/permissive/48250786/test_aesmodule.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_aesmodule.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_aesmodule.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_aesmodule.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_aesmodule.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_aesmodule.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/48250786/test_aesmodule.v:38: Cannot find file containing module: \'aesmodule\'\n aesmodule uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/aesmodule\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/aesmodule.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/aesmodule.sv\n             aesmodule\n             aesmodule.v\n             aesmodule.sv\n             obj_dir/aesmodule\n             obj_dir/aesmodule.v\n             obj_dir/aesmodule.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_aesmodule;


	reg [127:0] in;
	reg decr;
	reg clk;
	reg reset;


	wire [127:0] out;
	wire ready;


	aesmodule uut (
		.out(out), 
		.ready(ready), 
		.in(in), 
		.decr(decr), 
		.clk(clk), 
		.reset(reset)
	);
	
	
	always begin
		clk = 0;
		#10; 
		clk = 1;
		#10;
	end

	initial begin

		decr = 0;
		reset = 0;
		in = 128'h3243f6a8_885a308d_313198a2_e0370734;

		
		#2;
		reset = 1;
		
		#3;
		
		reset = 0;
		
		#5;


	end
      
endmodule
module test_aesmodule;



	reg [127:0] in;
	reg decr;
	reg clk;
	reg reset;


	wire [127:0] out;
	wire ready;


	aesmodule uut (
		.out(out), 
		.ready(ready), 
		.in(in), 
		.decr(decr), 
		.clk(clk), 
		.reset(reset)
	);
	
	
	always begin
		clk = 0;
		#10; 
		clk = 1;
		#10;
	end

	initial begin

		decr = 0;
		reset = 0;
		in = 128'h3243f6a8_885a308d_313198a2_e0370734;

		
		#2;
		reset = 1;
		
		#3;
		
		reset = 0;
		
		#5;


	end
      
endmodule