data/full_repos/permissive/447223480/01_add/cpu.v
data/verilator_xmls/129a3714-4632-494b-881a-1dcf02d4c0b9.xml
module regs(clock, reset, select, in_data, out_data);
	input clock;
	input reset;
	input[4:0] select;
	input[31:0] in_data;
	output[31:0] out_data;

	reg [31:0] regs[0:31];

	assign out_data = select == 5'd0 ? 32'd0 : regs[select];

	integer i;
	always @(posedge clock) begin
		if (reset) begin
			for (i = 0; i < 32; i = i + 1) begin
				regs[i] <= 32'd0;
			end
		end else begin
			if (select != 5'd0) begin
				regs[select] <= in_data;
			end
		end
	end

endmodule
module regs(clock, reset, select, in_data, out_data);

	input clock;
	input reset;
	input[4:0] select;
	input[31:0] in_data;
	output[31:0] out_data;

	reg [31:0] regs[0:31];

	assign out_data = select == 5'd0 ? 32'd0 : regs[select];

	integer i;
	always @(posedge clock) begin
		if (reset) begin
			for (i = 0; i < 32; i = i + 1) begin
				regs[i] <= 32'd0;
			end
		end else begin
			if (select != 5'd0) begin
				regs[select] <= in_data;
			end
		end
	end

endmodule