data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/ABR.v
data/verilator_xmls/b44e49df-05d2-4275-b139-2d6d7324d8a9.xml
module ABR(
    input clk,
    input [31:0] AIn,
    input [31:0] BIn,
    output reg [31:0] AOut,
    output reg [31:0] BOut
    );
    
    always@(posedge clk)begin
        AOut <= AIn;
        BOut <= BIn;
    end
endmodule
module ABR(
    input clk,
    input [31:0] AIn,
    input [31:0] BIn,
    output reg [31:0] AOut,
    output reg [31:0] BOut
    );

    
    always@(posedge clk)begin
        AOut <= AIn;
        BOut <= BIn;
    end
endmodule