data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module Control(
    input [6:0] Ctrlin,
    input [2:0] funct3,
    output wire ALUSrc,
    output wire [1:0] ALUOp,
    output wire MemWrite,
    output wire MemRead,
    output wire RegWrite,
    output wire Branch,
    output wire MemtoReg,
    output wire WdataSrc,
    output wire RdataSrc,
    output wire storeType,
    output wire [1:0] loadType
);
    reg [12:0] bus = 0;
    assign {ALUSrc, ALUOp, MemWrite, MemRead, Branch, MemtoReg, RegWrite, WdataSrc, RdataSrc, storeType, loadType} = bus;
    always @(*) begin
        case(Ctrlin)
            7'b0110011: bus <= 13'b0100000100000;
            7'b0010011: bus <= 13'b1110000100000;
            7'b0000011: begin
                case (funct3)
                    3'b000: bus <= 13'b1000101100001;
                    3'b100: bus <= 13'b1000101100010;
                    default: bus <= 13'b1000101100000;
                endcase
            end
            7'b0100011: begin
                case (funct3)
                    3'b000: bus<= 13'b1001000000100;
                    default: bus <= 13'b1001000000000;
                endcase       
            end     
            7'b1100011: bus <= 13'b0010010000000;
            7'b1100111: bus <= 13'b0000010001000;
            7'b1101111: bus <= 13'b1000010110000;
            default: bus <= 0;
        endcase
    end
endmodule
module Control(
    input [6:0] Ctrlin,
    input [2:0] funct3,
    output wire ALUSrc,
    output wire [1:0] ALUOp,
    output wire MemWrite,
    output wire MemRead,
    output wire RegWrite,
    output wire Branch,
    output wire MemtoReg,
    output wire WdataSrc,
    output wire RdataSrc,
    output wire storeType,
    output wire [1:0] loadType
);

    reg [12:0] bus = 0;
    assign {ALUSrc, ALUOp, MemWrite, MemRead, Branch, MemtoReg, RegWrite, WdataSrc, RdataSrc, storeType, loadType} = bus;
    always @(*) begin
        case(Ctrlin)
            7'b0110011: bus <= 13'b0100000100000;
            7'b0010011: bus <= 13'b1110000100000;
            7'b0000011: begin
                case (funct3)
                    3'b000: bus <= 13'b1000101100001;
                    3'b100: bus <= 13'b1000101100010;
                    default: bus <= 13'b1000101100000;
                endcase
            end
            7'b0100011: begin
                case (funct3)
                    3'b000: bus<= 13'b1001000000100;
                    default: bus <= 13'b1001000000000;
                endcase       
            end     
            7'b1100011: bus <= 13'b0010010000000;
            7'b1100111: bus <= 13'b0000010001000;
            7'b1101111: bus <= 13'b1000010110000;
            default: bus <= 0;
        endcase
    end
endmodule