data/full_repos/permissive/439514885/verilog/bits_top.v
1: b"%Error: data/full_repos/permissive/439514885/verilog/bits_top.v:75: Cannot find file containing module: 'bits_regs'\nbits_regs bits_regs(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_regs\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_regs.v\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_regs.sv\n             bits_regs\n             bits_regs.v\n             bits_regs.sv\n             obj_dir/bits_regs\n             obj_dir/bits_regs.v\n             obj_dir/bits_regs.sv\n%Error: data/full_repos/permissive/439514885/verilog/bits_top.v:107: Cannot find file containing module: 'imem_controller'\nimem_controller imem_controller(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/439514885/verilog/bits_top.v:133: Cannot find file containing module: 'bits_core'\nbits_core bits_core(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bits_top(


   pready,
   prdata,
   pslverr,

   imem_ceb,
   imem_web,
   imem_addr,

   smem_ceb,
   smem_web,
   smem_addr,
   smem_wdata,



   clk,
   resetB,


   paddr,
   psel,
   penable,
   pwrite,
   pwdata,


  imem_rdata,


  smem_rdata

);

output       pready;
output[31:0] prdata;
output       pslverr;

output       imem_ceb;
output       imem_web;
output[9:0]  imem_addr;

output       smem_ceb;
output       smem_web;
output[13:0] smem_addr;
output[95:0] smem_wdata;

input        clk;
input        resetB;
input[7:2]   paddr;
input        psel;
input        penable;
input        pwrite;
input[31:0]  pwdata;

input[31:0]  imem_rdata;

input[95:0]  smem_rdata;

wire       start;
wire[15:0] expectedBytes;
wire done_reading_memory;
wire[127:0] instruction_word;
wire[15:0] instruction_valid_bytes;
wire done;
wire[63:0] bits_value;
wire[15:0] version_sum;
wire[15:0] bit_counter;

wire       mem_req_b;
wire       mem_ack_b;

bits_regs bits_regs(


    .pready (),
    .prdata (prdata),
    .pslverr(),


    .expected_bytes(expectedBytes),
    .start(start),



    .clk (clk),
    .resetB (resetB),


    .paddr (paddr[7:2]),
    .psel (psel),
    .penable (penable),
    .pwrite (pwrite),
    .pwdata (pwdata),


    .done (done),
    .bits_value (bits_value),
    .bits_enable (1'b0),
    .version_sum(version_sum),
    .bit_counter(bit_counter)
);


imem_controller imem_controller(


    .imem_ceb (imem_ceb),
    .imem_web (imem_web),
    .imem_addr (imem_addr),


    .done_reading_memory (done_reading_memory),
    .instruction_word (instruction_word),
    .instruction_valid_bytes(instruction_valid_bytes),
    .mem_ack_b (mem_ack_b),



    .clk (clk),
    .resetB (resetB),


    .imem_rdata (imem_rdata),
    .mem_req_b (mem_req_b),


    .expectedBytes (expectedBytes)
);

bits_core bits_core(


    .smem_ceb (smem_ceb),
    .smem_web (smem_web),
    .smem_addr (smem_addr),
    .smem_wdata (smem_wdata),
    .mem_req_b (mem_req_b),


    .done (done),
    .version_sum (version_sum),
    .bits_value (bits_value),
    .bit_counter(bit_counter),



    .clk (clk),
    .resetB (resetB),


    .smem_rdata (smem_rdata),


    .instruction_word (instruction_word),
    .instruction_byte_valid (instruction_valid_bytes),
    .done_reading_memory (done_reading_memory),
    .mem_ack_b (mem_ack_b),


    .start (start),
    .expectedBytes (expectedBytes)
);


endmodule
module bits_top(


   pready,
   prdata,
   pslverr,

   imem_ceb,
   imem_web,
   imem_addr,

   smem_ceb,
   smem_web,
   smem_addr,
   smem_wdata,



   clk,
   resetB,


   paddr,
   psel,
   penable,
   pwrite,
   pwdata,


  imem_rdata,


  smem_rdata

);


output       pready;
output[31:0] prdata;
output       pslverr;

output       imem_ceb;
output       imem_web;
output[9:0]  imem_addr;

output       smem_ceb;
output       smem_web;
output[13:0] smem_addr;
output[95:0] smem_wdata;

input        clk;
input        resetB;
input[7:2]   paddr;
input        psel;
input        penable;
input        pwrite;
input[31:0]  pwdata;

input[31:0]  imem_rdata;

input[95:0]  smem_rdata;

wire       start;
wire[15:0] expectedBytes;
wire done_reading_memory;
wire[127:0] instruction_word;
wire[15:0] instruction_valid_bytes;
wire done;
wire[63:0] bits_value;
wire[15:0] version_sum;
wire[15:0] bit_counter;

wire       mem_req_b;
wire       mem_ack_b;

bits_regs bits_regs(


    .pready (),
    .prdata (prdata),
    .pslverr(),


    .expected_bytes(expectedBytes),
    .start(start),



    .clk (clk),
    .resetB (resetB),


    .paddr (paddr[7:2]),
    .psel (psel),
    .penable (penable),
    .pwrite (pwrite),
    .pwdata (pwdata),


    .done (done),
    .bits_value (bits_value),
    .bits_enable (1'b0),
    .version_sum(version_sum),
    .bit_counter(bit_counter)
);


imem_controller imem_controller(


    .imem_ceb (imem_ceb),
    .imem_web (imem_web),
    .imem_addr (imem_addr),


    .done_reading_memory (done_reading_memory),
    .instruction_word (instruction_word),
    .instruction_valid_bytes(instruction_valid_bytes),
    .mem_ack_b (mem_ack_b),



    .clk (clk),
    .resetB (resetB),


    .imem_rdata (imem_rdata),
    .mem_req_b (mem_req_b),


    .expectedBytes (expectedBytes)
);

bits_core bits_core(


    .smem_ceb (smem_ceb),
    .smem_web (smem_web),
    .smem_addr (smem_addr),
    .smem_wdata (smem_wdata),
    .mem_req_b (mem_req_b),


    .done (done),
    .version_sum (version_sum),
    .bits_value (bits_value),
    .bit_counter(bit_counter),



    .clk (clk),
    .resetB (resetB),


    .smem_rdata (smem_rdata),


    .instruction_word (instruction_word),
    .instruction_byte_valid (instruction_valid_bytes),
    .done_reading_memory (done_reading_memory),
    .mem_ack_b (mem_ack_b),


    .start (start),
    .expectedBytes (expectedBytes)
);


endmodule