data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v
1: b"%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:123: Define or directive not defined: '`SEL_WIDTH'\n  decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:123: Define or directive not defined: '`SEL_WIDTH'\n  decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:124: Define or directive not defined: '`FUNC_WIDTH'\n  decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'b0}};\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:124: Define or directive not defined: '`FUNC_WIDTH'\n  decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'b0}};\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:133: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:133: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:133: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                           ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:134: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:134: Define or directive not defined: '`FUNC_ADD'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:134: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                            ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:139: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:139: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:139: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                           ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:140: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:140: Define or directive not defined: '`FUNC_ADD'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:140: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                            ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:145: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:145: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:145: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                           ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:146: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:146: Define or directive not defined: '`FUNC_ADD'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:146: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                            ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:151: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:151: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:151: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                           ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:152: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:152: Define or directive not defined: '`FUNC_ADD'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:152: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;\n                                            ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:157: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:157: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:157: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;\n                                           ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:158: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SUB;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:158: Define or directive not defined: '`FUNC_SUB'\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SUB;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:158: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SUB;\n                                            ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:163: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:163: Define or directive not defined: '`SEL_BJU'\n      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;\n                                                            ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:163: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;\n                                                                     ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:163: Define or directive not defined: '`SEL_ALU'\n      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:164: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:164: Define or directive not defined: '`FUNC_JALR'\n      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:164: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;\n                                                                       ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:164: Define or directive not defined: '`FUNC_ADD'\n      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;\n                                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:169: Define or directive not defined: '`SEL_WIDTH'\n      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:170: Define or directive not defined: '`SEL_CP0'\n                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;\n                                                            ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:170: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;\n                                                                     ^\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:170: Define or directive not defined: '`SEL_BJU'\n                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:170: Define or directive not defined: '`SEL_ALU'\n                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;\n                                                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:171: Define or directive not defined: '`FUNC_WIDTH'\n      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0  \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:172: Define or directive not defined: '`FUNC_EBREAK'\n                                ? decd_inst[11:7] == 5'b0 ? `FUNC_EBREAK : `FUNC_JALR : `FUNC_ADD;\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v:172: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n                                ? decd_inst[11:7] == 5'b0 ? `FUNC_EBREAK : `FUNC_JALR : `FUNC_ADD;\n                                                                         ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module pa_idu_decd_rv32c(
  decd_inst,
  decd_inst_32bit,
  decd_rv32c_func,
  decd_rv32c_ill_expt,
  decd_rv32c_imm1,
  decd_rv32c_imm1_vld,
  decd_rv32c_imm2,
  decd_rv32c_imm2_vld,
  decd_rv32c_op_vld,
  decd_rv32c_rd,
  decd_rv32c_rd_vld,
  decd_rv32c_rs1,
  decd_rv32c_rs1_vld,
  decd_rv32c_rs2,
  decd_rv32c_rs2_vld,
  decd_rv32c_sel
);


input   [31:0]  decd_inst;          
input           decd_inst_32bit;    
output  [19:0]  decd_rv32c_func;    
output          decd_rv32c_ill_expt; 
output  [31:0]  decd_rv32c_imm1;    
output          decd_rv32c_imm1_vld; 
output  [31:0]  decd_rv32c_imm2;    
output          decd_rv32c_imm2_vld; 
output          decd_rv32c_op_vld;  
output  [4 :0]  decd_rv32c_rd;      
output          decd_rv32c_rd_vld;  
output  [4 :0]  decd_rv32c_rs1;     
output          decd_rv32c_rs1_vld; 
output  [4 :0]  decd_rv32c_rs2;     
output          decd_rv32c_rs2_vld; 
output  [5 :0]  decd_rv32c_sel;     


reg     [19:0]  decd_func;          
reg             decd_ill_expt;      
reg     [4 :0]  decd_rd;            
reg             decd_rd_vld;        
reg     [4 :0]  decd_rs1;           
reg             decd_rs1_vld;       
reg     [4 :0]  decd_rs2;           
reg             decd_rs2_vld;       
reg     [5 :0]  decd_sel;           


wire    [31:0]  cbtype_imm;         
wire            cbtype_imm_vld;     
wire    [31:0]  ciatype_imm;        
wire            ciatype_imm_vld;    
wire    [31:0]  ciltype_imm;        
wire            ciltype_imm_vld;    
wire    [31:0]  cistype_imm;        
wire            cistype_imm_vld;    
wire    [31:0]  citype_imm;         
wire            citype_imm_vld;     
wire    [31:0]  ciwtype_imm;        
wire            ciwtype_imm_vld;    
wire    [31:0]  cjtype_imm;         
wire            cjtype_imm_vld;     
wire    [31:0]  cltype_imm;         
wire            cltype_imm_vld;     
wire    [31:0]  csstype_imm;        
wire            csstype_imm_vld;    
wire    [31:0]  decd_imm1;          
wire            decd_imm1_vld;      
wire    [31:0]  decd_imm2;          
wire            decd_imm2_vld;      
wire    [31:0]  decd_inst;          
wire            decd_inst_32bit;    
wire    [19:0]  decd_rv32c_func;    
wire            decd_rv32c_ill_expt; 
wire    [31:0]  decd_rv32c_imm1;    
wire            decd_rv32c_imm1_vld; 
wire    [31:0]  decd_rv32c_imm2;    
wire            decd_rv32c_imm2_vld; 
wire            decd_rv32c_op_vld;  
wire    [4 :0]  decd_rv32c_rd;      
wire            decd_rv32c_rd_vld;  
wire    [4 :0]  decd_rv32c_rs1;     
wire            decd_rv32c_rs1_vld; 
wire    [4 :0]  decd_rv32c_rs2;     
wire            decd_rv32c_rs2_vld; 
wire    [5 :0]  decd_rv32c_sel;     
















always @( decd_inst[15:0])
begin
  decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};
  decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'b0}};
  decd_rd_vld                = 1'b0;
  casez(decd_inst[15:0])




    16'b000_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b000_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b010_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b011_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_00???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SUB;
      decd_rd_vld                = 1'b1;
    end
    16'b100_0?????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;
      decd_rd_vld                = decd_inst[6:2] != 5'b0;
    end
    16'b100_1?????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0
                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0  
                                ? decd_inst[11:7] == 5'b0 ? `FUNC_EBREAK : `FUNC_JALR : `FUNC_ADD;
      decd_rd_vld                = decd_inst[11:2] != 10'b0;
    end


    16'b100_?00???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SRL;
      decd_rd_vld                = 1'b1;
    end
    16'b100_?01???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SRA;
      decd_rd_vld                = 1'b1;
    end
    16'b000_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SLL;
      decd_rd_vld                = 1'b1;
    end


    16'b100_?10???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_AND;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_01???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_XOR;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_10???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_OR;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_11???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_AND;
      decd_rd_vld                = 1'b1;
    end




    16'b001_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_JAL;
      decd_rd_vld                = 1'b1;
    end
    16'b101_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_JAL;
      decd_rd_vld                = 1'b0;
    end
    16'b110_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_BEQ;
      decd_rd_vld                = 1'b0;
    end
    16'b111_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_BNE;
      decd_rd_vld                = 1'b0;
    end




    16'b010_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
      decd_rd_vld                = 1'b1;
    end
    16'b110_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b010_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
      decd_rd_vld                = 1'b1;
    end
    16'b110_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b011_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
    end
    16'b111_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b011_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
    end
    16'b111_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b001_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FLD;
    end
    16'b101_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FSD;
    end
    16'b001_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FLD;
    end
    16'b101_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FSD;
    end

    default:
    begin
      decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};
      decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'bx}};
      decd_rd_vld                = 1'b0;
    end
  endcase

end





always @( decd_inst[15:7]
       or decd_inst[9:0])
begin
  decd_rs1_vld  = 1'b0;
  decd_rs1[4:0] = 5'h0;
  casez({decd_inst[15:13], decd_inst[1:0]})
    5'b01001:
    begin
      decd_rs1_vld  = 1'b1;
    end
    5'b01101:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = decd_inst[11:7] == 5'h2 ? 5'h2 : 5'h0;
    end
    5'b00000,
    5'b?1110,
    5'b?1010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = 5'h2;
    end
    5'b?1100,
    5'b?1000,
    5'b11?01,
    5'b10001:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = {2'b01, decd_inst[9:7]};
    end
    5'b00001,
    5'b00010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = decd_inst[11:7];
    end
    5'b10010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = (decd_inst[6:2] != 5'b0 & ~decd_inst[12]) ? 5'b0 : decd_inst[11:7];
    end
    default: 
    begin
      decd_rs1_vld  = 1'b0;
      decd_rs1[4:0] = 5'b0;
    end
  endcase

end


always @( decd_inst[15:13]
       or decd_inst[11:10]
       or decd_inst[6:0])
begin
  casez({decd_inst[15:13], decd_inst[1:0]})
    5'b11010,
    5'b10010:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = decd_inst[6:2];
    end
    5'b11000:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = {2'b01, decd_inst[4:2]};
    end
    5'b10001:
    begin
      decd_rs2_vld  = decd_inst[11:10] == 2'b11;
      decd_rs2[4:0] = {2'b01, decd_inst[4:2]};
    end
    5'b11?01:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = 5'b0;
    end
    default: 
    begin
      decd_rs2_vld  = 1'b0;

      decd_rs2[4:0] = 5'b0;
    end
  endcase

end


always @( decd_inst[15:13]
       or decd_inst[11:0])
begin
  case({decd_inst[15:13], decd_inst[1:0]})
    5'b01010,
    5'b01001,
    5'b01101,
    5'b00001,
    5'b00010:
      decd_rd[4:0] = decd_inst[11:7];
    5'b10010:
      decd_rd[4:0] = decd_inst[6:2] == 5'b0 ? 5'b1 : decd_inst[11:7];
    5'b00101:
      decd_rd[4:0] = 5'b1;
    5'b10001:
      decd_rd[4:0] = {2'b01, decd_inst[9:7]};
    5'b01000,
    5'b00000:
      decd_rd[4:0] = {2'b01, decd_inst[4:2]};
    default : 
      decd_rd[4:0] = decd_inst[11:7];
  endcase

end





assign citype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b01001
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b00001
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b00010
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b10001
                          & decd_inst[11:10] != 2'b11;
assign citype_imm[31:0]  = {{27{decd_inst[12]}}, decd_inst[6:2]};

assign cistype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01010;
assign cistype_imm[31:0] = {24'b0, decd_inst[3:2], decd_inst[12], decd_inst[6:4], 2'b0};

assign ciltype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101
                         &  decd_inst[11:7] != 5'b10;
assign ciltype_imm[31:0] = {{15{decd_inst[12]}}, decd_inst[6:2], 12'b0};

assign ciatype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101
                         &  decd_inst[11:7] == 5'b10;
assign ciatype_imm[31:0] = {{23{decd_inst[12]}}, decd_inst[4:3], decd_inst[5], 
                            decd_inst[2], decd_inst[6], 4'b0};

assign ciwtype_imm_vld   = ~decd_inst_32bit & {decd_inst[15:13], decd_inst[1:0]}
                           == 5'b00000;
assign ciwtype_imm[31:0] = {22'b0, decd_inst[10:7], decd_inst[12:11], decd_inst[5],
                            decd_inst[6], 2'b0};

assign cltype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b01000 
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b11000;
assign cltype_imm[31:0]  = {25'b0, decd_inst[5], decd_inst[12:10], decd_inst[6], 2'b0};

assign csstype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b11010;
assign csstype_imm[31:0] = {24'b0, decd_inst[8:7], decd_inst[12:9], 2'b0};

assign cbtype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b11001 
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b11101;
assign cbtype_imm[31:0]  = {{24{decd_inst[12]}}, decd_inst[6:5], decd_inst[2],
                               decd_inst[11:10], decd_inst[4:3], 1'b0}; 

assign cjtype_imm_vld    = {decd_inst[14:13], decd_inst[1:0]} == 4'b0101;
assign cjtype_imm[31:0]  = {{21{decd_inst[12]}}, decd_inst[8], decd_inst[10:9], 
                           decd_inst[6], decd_inst[7], decd_inst[2], decd_inst[11],
                           decd_inst[5:3], 1'b0};


assign decd_imm1_vld   = citype_imm_vld | ciltype_imm_vld | ciatype_imm_vld | ciwtype_imm_vld;
assign decd_imm1[31:0] = {32{citype_imm_vld}}  & citype_imm[31:0]
                       | {32{ciltype_imm_vld}} & ciltype_imm[31:0]
                       | {32{ciatype_imm_vld}} & ciatype_imm[31:0]
                       | {32{ciwtype_imm_vld}} & ciwtype_imm[31:0];


assign decd_imm2_vld   = cistype_imm_vld | cltype_imm_vld | csstype_imm_vld
                       | cbtype_imm_vld | cjtype_imm_vld;
assign decd_imm2[31:0] = {32{cistype_imm_vld}} & cistype_imm[31:0]
                       | {32{cltype_imm_vld}}  & cltype_imm[31:0]
                       | {32{csstype_imm_vld}} & csstype_imm[31:0]
                       | {32{cbtype_imm_vld}}  & cbtype_imm[31:0]
                       | {32{cjtype_imm_vld}}  & cjtype_imm[31:0];







always @( decd_inst[15:0]
       or decd_rd[4:0])
begin
  casez({decd_inst[12:10], decd_inst[15:13], decd_inst[1:0]})
    8'b???00000:
    begin
      decd_ill_expt = decd_inst[12:5] == 8'b0;
    end
    8'b???01101:
    begin
      decd_ill_expt = {decd_inst[12], decd_inst[6:2]} == 6'b0;
    end
    8'b?0?10001,
    8'b???00010:
    begin
      decd_ill_expt = decd_inst[12];
    end
    8'b???01010:
    begin
      decd_ill_expt = decd_rd[4:0] == 5'b0;
    end
    8'b0??10010:
    begin
      decd_ill_expt = decd_inst[11:2] == 10'b0;
    end
    8'b???01000,
    8'b???11000,
    8'b???00001,
    8'b???00101,
    8'b???01001,
    8'b?1010001,
    8'b?1110001,
    8'b???10101,
    8'b???11001,
    8'b???11101,
    8'b1??10010,
    8'b???11010:
    begin
      decd_ill_expt = 1'b0; 
    end
    default:
    begin          
      decd_ill_expt = 1'b1;
    end
  endcase

end




assign decd_rv32c_op_vld                = ~decd_inst_32bit;
assign decd_rv32c_sel[`SEL_WIDTH-1:0]   = decd_sel[`SEL_WIDTH-1:0];
assign decd_rv32c_func[`FUNC_WIDTH-1:0] = decd_func[`FUNC_WIDTH-1:0];

assign decd_rv32c_rs1_vld               = decd_rs1_vld;
assign decd_rv32c_rs1[4:0]              = decd_rs1[4:0];
assign decd_rv32c_rs2_vld               = decd_rs2_vld;
assign decd_rv32c_rs2[4:0]              = decd_rs2[4:0];
assign decd_rv32c_rd_vld                = decd_rd_vld;
assign decd_rv32c_rd[4:0]               = decd_rd[4:0];

assign decd_rv32c_imm1_vld              = decd_imm1_vld;
assign decd_rv32c_imm1[31:0]            = decd_imm1[31:0];
assign decd_rv32c_imm2_vld              = decd_imm2_vld;
assign decd_rv32c_imm2[31:0]            = decd_imm2[31:0];

assign decd_rv32c_ill_expt              = decd_ill_expt;


endmodule
module pa_idu_decd_rv32c(
  decd_inst,
  decd_inst_32bit,
  decd_rv32c_func,
  decd_rv32c_ill_expt,
  decd_rv32c_imm1,
  decd_rv32c_imm1_vld,
  decd_rv32c_imm2,
  decd_rv32c_imm2_vld,
  decd_rv32c_op_vld,
  decd_rv32c_rd,
  decd_rv32c_rd_vld,
  decd_rv32c_rs1,
  decd_rv32c_rs1_vld,
  decd_rv32c_rs2,
  decd_rv32c_rs2_vld,
  decd_rv32c_sel
);



input   [31:0]  decd_inst;          
input           decd_inst_32bit;    
output  [19:0]  decd_rv32c_func;    
output          decd_rv32c_ill_expt; 
output  [31:0]  decd_rv32c_imm1;    
output          decd_rv32c_imm1_vld; 
output  [31:0]  decd_rv32c_imm2;    
output          decd_rv32c_imm2_vld; 
output          decd_rv32c_op_vld;  
output  [4 :0]  decd_rv32c_rd;      
output          decd_rv32c_rd_vld;  
output  [4 :0]  decd_rv32c_rs1;     
output          decd_rv32c_rs1_vld; 
output  [4 :0]  decd_rv32c_rs2;     
output          decd_rv32c_rs2_vld; 
output  [5 :0]  decd_rv32c_sel;     


reg     [19:0]  decd_func;          
reg             decd_ill_expt;      
reg     [4 :0]  decd_rd;            
reg             decd_rd_vld;        
reg     [4 :0]  decd_rs1;           
reg             decd_rs1_vld;       
reg     [4 :0]  decd_rs2;           
reg             decd_rs2_vld;       
reg     [5 :0]  decd_sel;           


wire    [31:0]  cbtype_imm;         
wire            cbtype_imm_vld;     
wire    [31:0]  ciatype_imm;        
wire            ciatype_imm_vld;    
wire    [31:0]  ciltype_imm;        
wire            ciltype_imm_vld;    
wire    [31:0]  cistype_imm;        
wire            cistype_imm_vld;    
wire    [31:0]  citype_imm;         
wire            citype_imm_vld;     
wire    [31:0]  ciwtype_imm;        
wire            ciwtype_imm_vld;    
wire    [31:0]  cjtype_imm;         
wire            cjtype_imm_vld;     
wire    [31:0]  cltype_imm;         
wire            cltype_imm_vld;     
wire    [31:0]  csstype_imm;        
wire            csstype_imm_vld;    
wire    [31:0]  decd_imm1;          
wire            decd_imm1_vld;      
wire    [31:0]  decd_imm2;          
wire            decd_imm2_vld;      
wire    [31:0]  decd_inst;          
wire            decd_inst_32bit;    
wire    [19:0]  decd_rv32c_func;    
wire            decd_rv32c_ill_expt; 
wire    [31:0]  decd_rv32c_imm1;    
wire            decd_rv32c_imm1_vld; 
wire    [31:0]  decd_rv32c_imm2;    
wire            decd_rv32c_imm2_vld; 
wire            decd_rv32c_op_vld;  
wire    [4 :0]  decd_rv32c_rd;      
wire            decd_rv32c_rd_vld;  
wire    [4 :0]  decd_rv32c_rs1;     
wire            decd_rv32c_rs1_vld; 
wire    [4 :0]  decd_rv32c_rs2;     
wire            decd_rv32c_rs2_vld; 
wire    [5 :0]  decd_rv32c_sel;     
















always @( decd_inst[15:0])
begin
  decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};
  decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'b0}};
  decd_rd_vld                = 1'b0;
  casez(decd_inst[15:0])




    16'b000_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b000_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b010_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b011_??????_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_ADD;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_00???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SUB;
      decd_rd_vld                = 1'b1;
    end
    16'b100_0?????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0 ? `SEL_BJU : `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0 ? `FUNC_JALR : `FUNC_ADD;
      decd_rd_vld                = decd_inst[6:2] != 5'b0;
    end
    16'b100_1?????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = decd_inst[6:2] == 5'b0
                                ? decd_inst[11:7] == 5'b0 ? `SEL_CP0 : `SEL_BJU : `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = decd_inst[6:2] == 5'b0  
                                ? decd_inst[11:7] == 5'b0 ? `FUNC_EBREAK : `FUNC_JALR : `FUNC_ADD;
      decd_rd_vld                = decd_inst[11:2] != 10'b0;
    end


    16'b100_?00???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SRL;
      decd_rd_vld                = 1'b1;
    end
    16'b100_?01???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SRA;
      decd_rd_vld                = 1'b1;
    end
    16'b000_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SLL;
      decd_rd_vld                = 1'b1;
    end


    16'b100_?10???_?????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_AND;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_01???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_XOR;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_10???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_OR;
      decd_rd_vld                = 1'b1;
    end
    16'b100_011???_11???_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_ALU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_AND;
      decd_rd_vld                = 1'b1;
    end




    16'b001_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_JAL;
      decd_rd_vld                = 1'b1;
    end
    16'b101_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_JAL;
      decd_rd_vld                = 1'b0;
    end
    16'b110_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_BEQ;
      decd_rd_vld                = 1'b0;
    end
    16'b111_?????_??????_01:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_BJU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_BNE;
      decd_rd_vld                = 1'b0;
    end




    16'b010_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
      decd_rd_vld                = 1'b1;
    end
    16'b110_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b010_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
      decd_rd_vld                = 1'b1;
    end
    16'b110_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b011_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
    end
    16'b111_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b011_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_LW;
    end
    16'b111_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_SW;
    end
    16'b001_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FLD;
    end
    16'b101_??????_?????_00:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FSD;
    end
    16'b001_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FLD;
    end
    16'b101_??????_?????_10:
    begin  
      decd_sel[`SEL_WIDTH-1:0]   = `SEL_LSU;
      decd_func[`FUNC_WIDTH-1:0] = `FUNC_FSD;
    end

    default:
    begin
      decd_sel[`SEL_WIDTH-1:0]   = {`SEL_WIDTH{1'b0}};
      decd_func[`FUNC_WIDTH-1:0] = {`FUNC_WIDTH{1'bx}};
      decd_rd_vld                = 1'b0;
    end
  endcase

end





always @( decd_inst[15:7]
       or decd_inst[9:0])
begin
  decd_rs1_vld  = 1'b0;
  decd_rs1[4:0] = 5'h0;
  casez({decd_inst[15:13], decd_inst[1:0]})
    5'b01001:
    begin
      decd_rs1_vld  = 1'b1;
    end
    5'b01101:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = decd_inst[11:7] == 5'h2 ? 5'h2 : 5'h0;
    end
    5'b00000,
    5'b?1110,
    5'b?1010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = 5'h2;
    end
    5'b?1100,
    5'b?1000,
    5'b11?01,
    5'b10001:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = {2'b01, decd_inst[9:7]};
    end
    5'b00001,
    5'b00010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = decd_inst[11:7];
    end
    5'b10010:
    begin
      decd_rs1_vld  = 1'b1;
      decd_rs1[4:0] = (decd_inst[6:2] != 5'b0 & ~decd_inst[12]) ? 5'b0 : decd_inst[11:7];
    end
    default: 
    begin
      decd_rs1_vld  = 1'b0;
      decd_rs1[4:0] = 5'b0;
    end
  endcase

end


always @( decd_inst[15:13]
       or decd_inst[11:10]
       or decd_inst[6:0])
begin
  casez({decd_inst[15:13], decd_inst[1:0]})
    5'b11010,
    5'b10010:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = decd_inst[6:2];
    end
    5'b11000:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = {2'b01, decd_inst[4:2]};
    end
    5'b10001:
    begin
      decd_rs2_vld  = decd_inst[11:10] == 2'b11;
      decd_rs2[4:0] = {2'b01, decd_inst[4:2]};
    end
    5'b11?01:
    begin
      decd_rs2_vld  = 1'b1;
      decd_rs2[4:0] = 5'b0;
    end
    default: 
    begin
      decd_rs2_vld  = 1'b0;

      decd_rs2[4:0] = 5'b0;
    end
  endcase

end


always @( decd_inst[15:13]
       or decd_inst[11:0])
begin
  case({decd_inst[15:13], decd_inst[1:0]})
    5'b01010,
    5'b01001,
    5'b01101,
    5'b00001,
    5'b00010:
      decd_rd[4:0] = decd_inst[11:7];
    5'b10010:
      decd_rd[4:0] = decd_inst[6:2] == 5'b0 ? 5'b1 : decd_inst[11:7];
    5'b00101:
      decd_rd[4:0] = 5'b1;
    5'b10001:
      decd_rd[4:0] = {2'b01, decd_inst[9:7]};
    5'b01000,
    5'b00000:
      decd_rd[4:0] = {2'b01, decd_inst[4:2]};
    default : 
      decd_rd[4:0] = decd_inst[11:7];
  endcase

end





assign citype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b01001
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b00001
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b00010
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b10001
                          & decd_inst[11:10] != 2'b11;
assign citype_imm[31:0]  = {{27{decd_inst[12]}}, decd_inst[6:2]};

assign cistype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01010;
assign cistype_imm[31:0] = {24'b0, decd_inst[3:2], decd_inst[12], decd_inst[6:4], 2'b0};

assign ciltype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101
                         &  decd_inst[11:7] != 5'b10;
assign ciltype_imm[31:0] = {{15{decd_inst[12]}}, decd_inst[6:2], 12'b0};

assign ciatype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101
                         &  decd_inst[11:7] == 5'b10;
assign ciatype_imm[31:0] = {{23{decd_inst[12]}}, decd_inst[4:3], decd_inst[5], 
                            decd_inst[2], decd_inst[6], 4'b0};

assign ciwtype_imm_vld   = ~decd_inst_32bit & {decd_inst[15:13], decd_inst[1:0]}
                           == 5'b00000;
assign ciwtype_imm[31:0] = {22'b0, decd_inst[10:7], decd_inst[12:11], decd_inst[5],
                            decd_inst[6], 2'b0};

assign cltype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b01000 
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b11000;
assign cltype_imm[31:0]  = {25'b0, decd_inst[5], decd_inst[12:10], decd_inst[6], 2'b0};

assign csstype_imm_vld   = {decd_inst[15:13], decd_inst[1:0]} == 5'b11010;
assign csstype_imm[31:0] = {24'b0, decd_inst[8:7], decd_inst[12:9], 2'b0};

assign cbtype_imm_vld    = {decd_inst[15:13], decd_inst[1:0]} == 5'b11001 
                         | {decd_inst[15:13], decd_inst[1:0]} == 5'b11101;
assign cbtype_imm[31:0]  = {{24{decd_inst[12]}}, decd_inst[6:5], decd_inst[2],
                               decd_inst[11:10], decd_inst[4:3], 1'b0}; 

assign cjtype_imm_vld    = {decd_inst[14:13], decd_inst[1:0]} == 4'b0101;
assign cjtype_imm[31:0]  = {{21{decd_inst[12]}}, decd_inst[8], decd_inst[10:9], 
                           decd_inst[6], decd_inst[7], decd_inst[2], decd_inst[11],
                           decd_inst[5:3], 1'b0};


assign decd_imm1_vld   = citype_imm_vld | ciltype_imm_vld | ciatype_imm_vld | ciwtype_imm_vld;
assign decd_imm1[31:0] = {32{citype_imm_vld}}  & citype_imm[31:0]
                       | {32{ciltype_imm_vld}} & ciltype_imm[31:0]
                       | {32{ciatype_imm_vld}} & ciatype_imm[31:0]
                       | {32{ciwtype_imm_vld}} & ciwtype_imm[31:0];


assign decd_imm2_vld   = cistype_imm_vld | cltype_imm_vld | csstype_imm_vld
                       | cbtype_imm_vld | cjtype_imm_vld;
assign decd_imm2[31:0] = {32{cistype_imm_vld}} & cistype_imm[31:0]
                       | {32{cltype_imm_vld}}  & cltype_imm[31:0]
                       | {32{csstype_imm_vld}} & csstype_imm[31:0]
                       | {32{cbtype_imm_vld}}  & cbtype_imm[31:0]
                       | {32{cjtype_imm_vld}}  & cjtype_imm[31:0];







always @( decd_inst[15:0]
       or decd_rd[4:0])
begin
  casez({decd_inst[12:10], decd_inst[15:13], decd_inst[1:0]})
    8'b???00000:
    begin
      decd_ill_expt = decd_inst[12:5] == 8'b0;
    end
    8'b???01101:
    begin
      decd_ill_expt = {decd_inst[12], decd_inst[6:2]} == 6'b0;
    end
    8'b?0?10001,
    8'b???00010:
    begin
      decd_ill_expt = decd_inst[12];
    end
    8'b???01010:
    begin
      decd_ill_expt = decd_rd[4:0] == 5'b0;
    end
    8'b0??10010:
    begin
      decd_ill_expt = decd_inst[11:2] == 10'b0;
    end
    8'b???01000,
    8'b???11000,
    8'b???00001,
    8'b???00101,
    8'b???01001,
    8'b?1010001,
    8'b?1110001,
    8'b???10101,
    8'b???11001,
    8'b???11101,
    8'b1??10010,
    8'b???11010:
    begin
      decd_ill_expt = 1'b0; 
    end
    default:
    begin          
      decd_ill_expt = 1'b1;
    end
  endcase

end




assign decd_rv32c_op_vld                = ~decd_inst_32bit;
assign decd_rv32c_sel[`SEL_WIDTH-1:0]   = decd_sel[`SEL_WIDTH-1:0];
assign decd_rv32c_func[`FUNC_WIDTH-1:0] = decd_func[`FUNC_WIDTH-1:0];

assign decd_rv32c_rs1_vld               = decd_rs1_vld;
assign decd_rv32c_rs1[4:0]              = decd_rs1[4:0];
assign decd_rv32c_rs2_vld               = decd_rs2_vld;
assign decd_rv32c_rs2[4:0]              = decd_rs2[4:0];
assign decd_rv32c_rd_vld                = decd_rd_vld;
assign decd_rv32c_rd[4:0]               = decd_rd[4:0];

assign decd_rv32c_imm1_vld              = decd_imm1_vld;
assign decd_rv32c_imm1[31:0]            = decd_imm1[31:0];
assign decd_rv32c_imm2_vld              = decd_imm2_vld;
assign decd_rv32c_imm2[31:0]            = decd_imm2[31:0];

assign decd_rv32c_ill_expt              = decd_ill_expt;


endmodule