data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:52: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]    ucb_packet;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:58: Define or directive not defined: \'`UCB_ADDR_WIDTH\'\n   wire [`UCB_ADDR_WIDTH-1:0]         ucb_packet_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:64: Define or directive not defined: \'`UCB_ADDR_HI\'\n   assign   ucb_packet_addr = ucb_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];\n                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:64: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign   ucb_packet_addr = ucb_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];\n                                                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:64: Define or directive not defined: \'`UCB_ADDR_LO\'\n   assign   ucb_packet_addr = ucb_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];\n                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:89: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_L1ID}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:89: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n {`CPU_ASI,`IOB_ASI_L1ID}:begin\n          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:89: Define or directive not defined: \'`IOB_ASI_L1ID\'\n {`CPU_ASI,`IOB_ASI_L1ID}:begin\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:92: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_L1DD}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:92: Define or directive not defined: \'`IOB_ASI_L1DD\'\n {`CPU_ASI,`IOB_ASI_L1DD}:begin\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:95: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_BIST}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:95: Define or directive not defined: \'`IOB_ASI_BIST\'\n {`CPU_ASI,`IOB_ASI_BIST}:begin\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:98: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_MARGIN}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:98: Define or directive not defined: \'`IOB_ASI_MARGIN\'\n {`CPU_ASI,`IOB_ASI_MARGIN}:begin\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:101: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_DEFEATURE}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:101: Define or directive not defined: \'`IOB_ASI_DEFEATURE\'\n {`CPU_ASI,`IOB_ASI_DEFEATURE}:begin\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:104: Define or directive not defined: \'`CPU_ASI\'\n {`CPU_ASI,`IOB_ASI_PC}:begin\n  ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_asi_dec.v:104: Define or directive not defined: \'`IOB_ASI_PC\'\n {`CPU_ASI,`IOB_ASI_PC}:begin\n           ^~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module iobdg_asi_dec (

   asi_ctrl, asi_addr, 

   ucb_packet
   );

   



   input [`UCB_64PAY_PKT_WIDTH-1:0]    ucb_packet;
   output [31:0] 		       asi_ctrl;
   output [31:0] 		       asi_addr;
   
   reg [31:0] 			       asi_ctrl;
   
   wire [`UCB_ADDR_WIDTH-1:0] 	       ucb_packet_addr;
   
   



   assign 	 ucb_packet_addr = ucb_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];
   


















   


   always @(ucb_packet_addr) begin
      case (ucb_packet_addr[39:28])
	{`CPU_ASI,`IOB_ASI_L1ID}:begin
	   asi_ctrl = {30'b0100000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_L1DD}:begin
	   asi_ctrl = {30'b0010000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_BIST}:begin
	   asi_ctrl = {30'b0001000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_MARGIN}:begin
	   asi_ctrl = {30'b0000100,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_DEFEATURE}:begin
	   asi_ctrl = {30'b0000010,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_PC}:begin
	   asi_ctrl = {30'b0000001,ucb_packet_addr[24:23]};
	end
	default:begin
	   asi_ctrl = 32'b0;
	end
      endcase
   end
   
   assign        asi_addr = {9'b0,ucb_packet_addr[22:0]};


endmodule
module iobdg_asi_dec (

   asi_ctrl, asi_addr, 

   ucb_packet
   );


   



   input [`UCB_64PAY_PKT_WIDTH-1:0]    ucb_packet;
   output [31:0] 		       asi_ctrl;
   output [31:0] 		       asi_addr;
   
   reg [31:0] 			       asi_ctrl;
   
   wire [`UCB_ADDR_WIDTH-1:0] 	       ucb_packet_addr;
   
   



   assign 	 ucb_packet_addr = ucb_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];
   


















   


   always @(ucb_packet_addr) begin
      case (ucb_packet_addr[39:28])
	{`CPU_ASI,`IOB_ASI_L1ID}:begin
	   asi_ctrl = {30'b0100000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_L1DD}:begin
	   asi_ctrl = {30'b0010000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_BIST}:begin
	   asi_ctrl = {30'b0001000,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_MARGIN}:begin
	   asi_ctrl = {30'b0000100,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_DEFEATURE}:begin
	   asi_ctrl = {30'b0000010,ucb_packet_addr[24:23]};
	end
	{`CPU_ASI,`IOB_ASI_PC}:begin
	   asi_ctrl = {30'b0000001,ucb_packet_addr[24:23]};
	end
	default:begin
	   asi_ctrl = 32'b0;
	end
      endcase
   end
   
   assign        asi_addr = {9'b0,ucb_packet_addr[22:0]};


endmodule