data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new/tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new/tester.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new/tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #0 clock = 0; btnC = 0; btnU = 0; sw = 8\'b00000000; sw[0] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new/tester.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #100000 $finish;\n        ^\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new/tester.v:36: Cannot find file containing module: \'main\'\n    main m(seg,an,digit3,digit2,digit1,digit0,btnC,btnU,sw,clock);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new,data/full_repos/permissive/423958267/main\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new,data/full_repos/permissive/423958267/main.v\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_3/new,data/full_repos/permissive/423958267/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(

);
    reg clock;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [6:0] seg;
    wire [3:0] an;
    
    reg btnC, btnU;
    reg [7:0] sw;
    

    
    main m(seg,an,digit3,digit2,digit1,digit0,btnC,btnU,sw,clock);

    always #10 clock = ~clock;

    initial
    begin
        #0 clock = 0; btnC = 0; btnU = 0; sw = 8'b00000000; sw[0] = 1;
        #100000 $finish;
    end
endmodule
module tester(

);

    reg clock;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [6:0] seg;
    wire [3:0] an;
    
    reg btnC, btnU;
    reg [7:0] sw;
    

    
    main m(seg,an,digit3,digit2,digit1,digit0,btnC,btnU,sw,clock);

    always #10 clock = ~clock;

    initial
    begin
        #0 clock = 0; btnC = 0; btnU = 0; sw = 8'b00000000; sw[0] = 1;
        #100000 $finish;
    end
endmodule