data/full_repos/permissive/473363095/sensors_input.v
1: b'%Warning-WIDTH: data/full_repos/permissive/473363095/sensors_input.v:38: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                       : ... In instance sensors_input\n   rest = (sensor2 + sensor4) - cat * 2 ;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/473363095/sensors_input.v:48: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                       : ... In instance sensors_input\n   rest = (sensor1 + sensor3) - cat * 2 ;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/473363095/sensors_input.v:58: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                       : ... In instance sensors_input\n   rest = (sensor1 + sensor2 + sensor3 + sensor4) - cat * 4; \n        ^\n%Error: Exiting due to 3 warning(s)\n'
module sensors_input(
	output [7:0] height,
   input [7:0] sensor1,
   input [7:0] sensor2,
   input [7:0] sensor3,
   input [7:0] sensor4
	);

	reg [7:0] medie;
	reg [7:0] cat;
	reg [1:0] rest;
	
	always @(*) begin
		

		if (sensor1 == 8'b0 || sensor3 == 8'b0) begin
			cat = (sensor2 + sensor4) / 2;
			rest = (sensor2 + sensor4) - cat * 2 ;
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat + 1;
				default: medie = 0; 
			endcase
		

		end else if (sensor2 == 8'b0 || sensor4 == 8'b0) begin
			cat = (sensor1 + sensor3) / 2;
			rest = (sensor1 + sensor3) - cat * 2 ;
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat + 1;
				default: medie = 0; 
			endcase
		

		end else begin
			cat = (sensor1 + sensor2 + sensor3 + sensor4) / 4;
			rest = (sensor1 + sensor2 + sensor3 + sensor4) - cat * 4;	
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat;
				'b10: medie = cat + 1;
				'b11: medie = cat + 1;
				default: medie = 0; 
			endcase
		end
	end
	

	assign height = medie;

endmodule
module sensors_input(
	output [7:0] height,
   input [7:0] sensor1,
   input [7:0] sensor2,
   input [7:0] sensor3,
   input [7:0] sensor4
	);


	reg [7:0] medie;
	reg [7:0] cat;
	reg [1:0] rest;
	
	always @(*) begin
		

		if (sensor1 == 8'b0 || sensor3 == 8'b0) begin
			cat = (sensor2 + sensor4) / 2;
			rest = (sensor2 + sensor4) - cat * 2 ;
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat + 1;
				default: medie = 0; 
			endcase
		

		end else if (sensor2 == 8'b0 || sensor4 == 8'b0) begin
			cat = (sensor1 + sensor3) / 2;
			rest = (sensor1 + sensor3) - cat * 2 ;
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat + 1;
				default: medie = 0; 
			endcase
		

		end else begin
			cat = (sensor1 + sensor2 + sensor3 + sensor4) / 4;
			rest = (sensor1 + sensor2 + sensor3 + sensor4) - cat * 4;	
			case (rest)
				'b0: medie = cat;
				'b1: medie = cat;
				'b10: medie = cat + 1;
				'b11: medie = cat + 1;
				default: medie = 0; 
			endcase
		end
	end
	

	assign height = medie;

endmodule