data/full_repos/permissive/460663963/Randomizer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/460663963/Randomizer_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460663963/Randomizer_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/460663963/Randomizer_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/460663963/Randomizer_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/460663963/Randomizer_tb.v:41: syntax error, unexpected rand, expecting IDENTIFIER\nrandomizer rand (DataIn, clk, reset, load, en, seed, DataOut);\n           ^~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module randomizer_tb();

reg [95:0] I;
reg [95:0] O;
reg clk, reset, load, en;
reg [14:0] seed;
reg DataIn;
wire DataOut;

reg [95:0] Expected;

integer i;

assign O = 0;
assign Expected = 96'h558AC4A53A1724E163AC2BF9;

initial begin
I = 96'hACBCD2114DAE1577C6DBF4C9;
reset = 0;
load = 0;
seed = 0;
en = 1;
clk = 1;
for (i = 95; i >= 0; i = i - 1) begin
	DataIn = I[i];
	#5 clk = ~clk;
	#5 clk = ~clk;
	O[i] = DataOut;
end
if (O == Expected) begin
	$display("Success!");
	#10 $finish;
end
else begin
	$display("Failure!");
	#10 $finish;
end

end

randomizer rand (DataIn, clk, reset, load, en, seed, DataOut);

endmodule
module randomizer_tb();


reg [95:0] I;
reg [95:0] O;
reg clk, reset, load, en;
reg [14:0] seed;
reg DataIn;
wire DataOut;

reg [95:0] Expected;

integer i;

assign O = 0;
assign Expected = 96'h558AC4A53A1724E163AC2BF9;

initial begin
I = 96'hACBCD2114DAE1577C6DBF4C9;
reset = 0;
load = 0;
seed = 0;
en = 1;
clk = 1;
for (i = 95; i >= 0; i = i - 1) begin
	DataIn = I[i];
	#5 clk = ~clk;
	#5 clk = ~clk;
	O[i] = DataOut;
end
if (O == Expected) begin
	$display("Success!");
	#10 $finish;
end
else begin
	$display("Failure!");
	#10 $finish;
end

end

randomizer rand (DataIn, clk, reset, load, en, seed, DataOut);

endmodule