data/full_repos/permissive/42149584/Pong/Phase1/video_timer.v
data/verilator_xmls/e1699d8d-5795-4a0a-b149-e5f138d409d5.xml
module video_timer(input clk,
						 output hsyncOut,
						 output vsyncOut,
						 output [9:0] xposOut,
						 output [9:0] yposOut);

	reg [9:0] xpos;
	reg [9:0] ypos;

	wire endline = (xpos == 799);

	always @(posedge clk) begin
		if (endline)
		  xpos <= 0;
		else
		  xpos <= xpos + 10'd1;
	end

	always @(posedge clk) begin
		if (endline) begin
			if (ypos == 520)
				ypos <= 0;
			else
				ypos <= ypos + 10'd1;	
		end
	end
		 
	reg hsync, vsync;
	always @(posedge clk) begin
		hsync <= ~(xpos > 664 && xpos <= 759);
		vsync <= ~(ypos == 490 || ypos == 491);
	end

	assign hsyncOut = hsync;
	assign vsyncOut = vsync;
	assign xposOut = xpos;
	assign yposOut = ypos;

endmodule
module video_timer(input clk,
						 output hsyncOut,
						 output vsyncOut,
						 output [9:0] xposOut,
						 output [9:0] yposOut);


	reg [9:0] xpos;
	reg [9:0] ypos;

	wire endline = (xpos == 799);

	always @(posedge clk) begin
		if (endline)
		  xpos <= 0;
		else
		  xpos <= xpos + 10'd1;
	end

	always @(posedge clk) begin
		if (endline) begin
			if (ypos == 520)
				ypos <= 0;
			else
				ypos <= ypos + 10'd1;	
		end
	end
		 
	reg hsync, vsync;
	always @(posedge clk) begin
		hsync <= ~(xpos > 664 && xpos <= 759);
		vsync <= ~(ypos == 490 || ypos == 491);
	end

	assign hsyncOut = hsync;
	assign vsyncOut = vsync;
	assign xposOut = xpos;
	assign yposOut = ypos;

endmodule