data/full_repos/permissive/493847347/src/s44_soft.v
1: b"%Error: data/full_repos/permissive/493847347/src/s44_soft.v:35: Cannot find file containing module: 'lut'\nlut #(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/lut\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/lut.v\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/lut.sv\n             lut\n             lut.v\n             lut.sv\n             obj_dir/lut\n             obj_dir/lut.v\n             obj_dir/lut.sv\n%Error: data/full_repos/permissive/493847347/src/s44_soft.v:47: Cannot find file containing module: 'lut'\nlut #(\n^~~\n%Error: Exiting due to 2 error(s)\n"
module s44_soft #()(

  input wire clk,
  input wire sc_data,
  input wire sc_en,

  input wire [3:0] s0,
  input wire [3:0] s1,

  output wire sc_data_out,
  output wire z0,
  output wire z1
);

wire lut0_z;

reg fractured;

wire lut1_s_0;
wire lut1_sc_data;

assign lut1_s_0 = fractured ? s1[0] : lut0_z;

assign z0 = lut0_z;





lut #(
  .INPUTS(4),
  .CONFIG_WIDTH(1)
) lut0 (
  .config_clk(clk),
  .config_en(sc_en),
  .config_in(lut1_sc_data),
  .config_out(sc_data_out),
  .addr(s0),
  .out(lut0_z)
);

lut #(
  .INPUTS(4),
  .CONFIG_WIDTH(1)
) lut1 (
  .config_clk(clk),
  .config_en(sc_en),
  .config_in(fractured),
  .config_out(lut1_sc_data),
  .addr({s1[3:1],lut1_s_0}),
  .out(z1)
);

always @(posedge clk) begin
  fractured <= sc_data;
end

endmodule
module s44_soft #()(

  input wire clk,
  input wire sc_data,
  input wire sc_en,

  input wire [3:0] s0,
  input wire [3:0] s1,

  output wire sc_data_out,
  output wire z0,
  output wire z1
);


wire lut0_z;

reg fractured;

wire lut1_s_0;
wire lut1_sc_data;

assign lut1_s_0 = fractured ? s1[0] : lut0_z;

assign z0 = lut0_z;





lut #(
  .INPUTS(4),
  .CONFIG_WIDTH(1)
) lut0 (
  .config_clk(clk),
  .config_en(sc_en),
  .config_in(lut1_sc_data),
  .config_out(sc_data_out),
  .addr(s0),
  .out(lut0_z)
);

lut #(
  .INPUTS(4),
  .CONFIG_WIDTH(1)
) lut1 (
  .config_clk(clk),
  .config_en(sc_en),
  .config_in(fractured),
  .config_out(lut1_sc_data),
  .addr({s1[3:1],lut1_s_0}),
  .out(z1)
);

always @(posedge clk) begin
  fractured <= sc_data;
end

endmodule