data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v
1: b'%Error: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:13: Unsupported or unknown PLI call: $dumpfile\n               $dumpfile("tb_asmd_multiplier.vcd");\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:14: Unsupported or unknown PLI call: $dumpvars\n               $dumpvars(0, tb_asmd_multiplier);\n               ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:15: Unsupported: Ignoring delay on this delayed statement.\n               #500 $finish;\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:19: Unsupported: Ignoring delay on this delayed statement.\n                    forever #5 clk=~clk;\n                            ^\n%Error: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:21: Unsupported: fork statements\n                initial fork\n                        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:22: Unsupported: Ignoring delay on this delayed statement.\n                    #10 reset = 1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:23: Unsupported: Ignoring delay on this delayed statement.\n                    #20 reset = 0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/503137469/verilog/rtl/asmd_multiplier/test/tb_asmd_multiplier.v:24: Unsupported: Ignoring delay on this delayed statement.\n                    #30 word0= 4\'b1000; word1 =  4\'b1111; start =1;\n                    ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_asmd_multiplier;
        parameter word_length = 4;
        wire  [2*word_length-1:0] product;
        wire                      ready;
        reg   [word_length-1:0]   word0, word1;
        reg                       start, clk, reset;

        asmd_multiplier module1(.product(product), .ready(ready), .word0(word0), .word1(word1),
                                .start(start), .clk(clk), .reset(reset));

        initial begin
               $dumpfile("tb_asmd_multiplier.vcd");
               $dumpvars(0, tb_asmd_multiplier);
               #500 $finish;
        end
        initial begin
                    clk =1'b0;
                    forever #5 clk=~clk;
                end
                initial fork
                    #10 reset = 1;
                    #20 reset = 0;
                    #30 word0= 4'b1000; word1 =  4'b1111; start =1;
        join

endmodule
module tb_asmd_multiplier;

        parameter word_length = 4;
        wire  [2*word_length-1:0] product;
        wire                      ready;
        reg   [word_length-1:0]   word0, word1;
        reg                       start, clk, reset;

        asmd_multiplier module1(.product(product), .ready(ready), .word0(word0), .word1(word1),
                                .start(start), .clk(clk), .reset(reset));

        initial begin
               $dumpfile("tb_asmd_multiplier.vcd");
               $dumpvars(0, tb_asmd_multiplier);
               #500 $finish;
        end
        initial begin
                    clk =1'b0;
                    forever #5 clk=~clk;
                end
                initial fork
                    #10 reset = 1;
                    #20 reset = 0;
                    #30 word0= 4'b1000; word1 =  4'b1111; start =1;
        join

endmodule