data/full_repos/permissive/43264243/utx.v
1: b'%Error: data/full_repos/permissive/43264243/utx.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/utx.v:45: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/43264243/utx.v:52: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module utx(clk, rstn, load, inbyte, serialout, done);
	input clk;
	input rstn;
	input load;
	input [7:0] inbyte;
	output serialout;
	output done;	
	
	wire baudce;
	wire bitcounterce;
	wire [1:0] cur_utx_state;
	wire [1:0] next_utx_state;
	wire [3:0] bitcounter;
	wire busy_int;
	wire done_int;
	wire shiftregout;
	wire nextbit;
	
	

	
	baudcounter bc0(
		.clk(clk),
		.rstn(rstn),
		.arm(busy_int),
		.baudce(baudce)
	);
	

	
	bit_counter btc0(
		.clk(clk),
		.rstn(rstn),
		.ce(bitcounterce),
		.bitnum(bitcounter)
		);



	
	sr_lsb_first sr0(
		.clk(clk),
		.rstn(rstn),
		.load(load),
		.shift(nextbit),
		.parallelin(inbyte),
		.lsbout(shiftregout)
		);
		

	
	comb_utx_sm smc0(
		.load(load),
		.shiftregin(shiftregout),
		.baudce(baudce),
		.cur_utx_state(cur_utx_state),
		.bitcounter(bitcounter),
		.bitcounterce(bitcounterce),
		.busy(busy_int),
		.done_int(done_int),
		.serialout(serialout),
		.nextbit(nextbit),
		.next_utx_state(next_utx_state)
		);
		

	
	seq_utx_sm sms0(
		.rstn(rstn),
		.clk(clk),
		.done_int(done_int),
		.next_utx_state(next_utx_state),
		.done(done),
		.cur_utx_state(cur_utx_state)
		);
		
endmodule
module utx(clk, rstn, load, inbyte, serialout, done);

	input clk;
	input rstn;
	input load;
	input [7:0] inbyte;
	output serialout;
	output done;	
	
	wire baudce;
	wire bitcounterce;
	wire [1:0] cur_utx_state;
	wire [1:0] next_utx_state;
	wire [3:0] bitcounter;
	wire busy_int;
	wire done_int;
	wire shiftregout;
	wire nextbit;
	
	

	
	baudcounter bc0(
		.clk(clk),
		.rstn(rstn),
		.arm(busy_int),
		.baudce(baudce)
	);
	

	
	bit_counter btc0(
		.clk(clk),
		.rstn(rstn),
		.ce(bitcounterce),
		.bitnum(bitcounter)
		);



	
	sr_lsb_first sr0(
		.clk(clk),
		.rstn(rstn),
		.load(load),
		.shift(nextbit),
		.parallelin(inbyte),
		.lsbout(shiftregout)
		);
		

	
	comb_utx_sm smc0(
		.load(load),
		.shiftregin(shiftregout),
		.baudce(baudce),
		.cur_utx_state(cur_utx_state),
		.bitcounter(bitcounter),
		.bitcounterce(bitcounterce),
		.busy(busy_int),
		.done_int(done_int),
		.serialout(serialout),
		.nextbit(nextbit),
		.next_utx_state(next_utx_state)
		);
		

	
	seq_utx_sm sms0(
		.rstn(rstn),
		.clk(clk),
		.done_int(done_int),
		.next_utx_state(next_utx_state),
		.done(done),
		.cur_utx_state(cur_utx_state)
		);
		
endmodule