data/full_repos/permissive/511535464/src/CLK.v
data/verilator_xmls/fe6106b2-d85c-4664-bae0-614f9b70dc0f.xml
module CLK(
    input wire sysclk,
    input wire reset,
    output reg clk
);

reg [31:0] count;

initial begin
    count <= 0;
end

always@(posedge sysclk or posedge reset) begin
    if(reset) begin
        count <= 0;
        clk <= 0;
    end
    else if(count >= 2) begin
        clk <= ~clk;
        count <= 0;
    end
    else begin
        count <= count + 1;
    end
end

endmodule
module CLK(
    input wire sysclk,
    input wire reset,
    output reg clk
);


reg [31:0] count;

initial begin
    count <= 0;
end

always@(posedge sysclk or posedge reset) begin
    if(reset) begin
        count <= 0;
        clk <= 0;
    end
    else if(count >= 2) begin
        clk <= ~clk;
        count <= 0;
    end
    else begin
        count <= count + 1;
    end
end

endmodule