data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v
1: b"%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:13: Define or directive not defined: '`IO_PINS'\n   input [`IO_PINS-1:0] pin_dir,             \n          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:14: Define or directive not defined: '`IO_PINS'\n   input [`IO_PINS-1:0] pin_data_in,         \n          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:15: Define or directive not defined: '`IO_PINS'\n   output [`IO_PINS-1:0] pin_data_out,       \n           ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:16: Define or directive not defined: '`IO_PINS'\n   output [`IO_PINS+2-1:0] port_active_in,   \n           ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:17: Define or directive not defined: '`IO_PINS'\n   input [`IO_PINS+2-1:0] port_active_out,   \n          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:18: Define or directive not defined: '`IO_PINS'\n   output [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_in,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:18: Define or directive not defined: '`DATA_WIDTH'\n   output [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_in,\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:19: Define or directive not defined: '`IO_PINS'\n   input [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_out\n           ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:19: Define or directive not defined: '`DATA_WIDTH'\n   input [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_out\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:22: Define or directive not defined: '`IO_PINS'\nwire [`IO_PINS-1:0] pin_dir_rev;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:23: Define or directive not defined: '`IO_PINS'\nwire [`IO_PINS-1:0] pin_data_in_rev;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:24: Define or directive not defined: '`IO_PINS'\nwire [`IO_PINS-1:0] pin_data_out_rev;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:39: Define or directive not defined: '`IO_PINS'\n   for (pin=0; pin<`IO_PINS; pin=pin+1) begin:g_pin\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:39: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   for (pin=0; pin<`IO_PINS; pin=pin+1) begin:g_pin\n                           ^\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:40: Define or directive not defined: '`IO_PINS'\n      localparam rpin = `IO_PINS-1-pin;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/io_filter_rev.v:44: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n"
module io_filter_rev (
   input clk,
   input rst_n,
   input [`IO_PINS-1:0] pin_dir,
   input [`IO_PINS-1:0] pin_data_in,
   output [`IO_PINS-1:0] pin_data_out,
   output [`IO_PINS+2-1:0] port_active_in,
   input [`IO_PINS+2-1:0] port_active_out,
   output [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_in,
   input [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_out
);

wire [`IO_PINS-1:0] pin_dir_rev;
wire [`IO_PINS-1:0] pin_data_in_rev;
wire [`IO_PINS-1:0] pin_data_out_rev;

io_filter io_filter_inst (
   .clk(clk),
   .rst_n(rst_n),
   .pin_dir(pin_dir_rev),
   .pin_data_in(pin_data_in_rev),
   .pin_data_out(pin_data_out_rev),
   .port_active_in(port_active_in),
   .port_active_out(port_active_out),
   .port_data_in(port_data_in),
   .port_data_out(port_data_out)
);

generate genvar pin;
   for (pin=0; pin<`IO_PINS; pin=pin+1) begin:g_pin
      localparam rpin = `IO_PINS-1-pin;
      assign pin_dir_rev[pin] = pin_dir[rpin];
      assign pin_data_in_rev[pin] = pin_data_in[rpin];
      assign pin_data_out[pin] = pin_data_out_rev[rpin];
   end
endgenerate

endmodule
module io_filter_rev (
   input clk,
   input rst_n,
   input [`IO_PINS-1:0] pin_dir,
   input [`IO_PINS-1:0] pin_data_in,
   output [`IO_PINS-1:0] pin_data_out,
   output [`IO_PINS+2-1:0] port_active_in,
   input [`IO_PINS+2-1:0] port_active_out,
   output [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_in,
   input [(`IO_PINS+2)*`DATA_WIDTH-1:0] port_data_out
);


wire [`IO_PINS-1:0] pin_dir_rev;
wire [`IO_PINS-1:0] pin_data_in_rev;
wire [`IO_PINS-1:0] pin_data_out_rev;

io_filter io_filter_inst (
   .clk(clk),
   .rst_n(rst_n),
   .pin_dir(pin_dir_rev),
   .pin_data_in(pin_data_in_rev),
   .pin_data_out(pin_data_out_rev),
   .port_active_in(port_active_in),
   .port_active_out(port_active_out),
   .port_data_in(port_data_in),
   .port_data_out(port_data_out)
);

generate genvar pin;
   for (pin=0; pin<`IO_PINS; pin=pin+1) begin:g_pin
      localparam rpin = `IO_PINS-1-pin;
      assign pin_dir_rev[pin] = pin_dir[rpin];
      assign pin_data_in_rev[pin] = pin_data_in[rpin];
      assign pin_data_out[pin] = pin_data_out_rev[rpin];
   end
endgenerate

endmodule