data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:32: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chany_bottom_in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:34: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chany_top_in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:36: Little bit endian vector: MSB < LSB of bit range: 0:59\ninput [0:59] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:38: Little bit endian vector: MSB < LSB of bit range: 0:59\ninput [0:59] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:40: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chany_bottom_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:42: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chany_top_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:72: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:73: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:74: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:75: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:76: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:77: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:78: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:79: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_3_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:80: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_4_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:81: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_4_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:82: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_5_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:83: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_5_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:84: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_6_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:85: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_6_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:86: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_7_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:87: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_7_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:88: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_8_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:89: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_8_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:90: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_9_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:91: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_9_sram_inv;\n     ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:202: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_left_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6.sv\n             mux_2level_tapbuf_size6\n             mux_2level_tapbuf_size6.v\n             mux_2level_tapbuf_size6.sv\n             obj_dir/mux_2level_tapbuf_size6\n             obj_dir/mux_2level_tapbuf_size6.v\n             obj_dir/mux_2level_tapbuf_size6.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:208: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_left_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:214: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:220: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:226: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:232: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:238: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:244: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:250: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_6 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:256: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_right_ipin_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:262: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_left_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:268: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_left_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:274: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:280: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:286: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:292: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:298: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:304: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:310: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_6 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cby_0__1_.v:316: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_right_ipin_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s), 26 warning(s)\n'
module cby_0__1_(chany_bottom_in,
                 chany_top_in,
                 bl,
                 wl,
                 chany_bottom_out,
                 chany_top_out,
                 right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
                 right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
                 left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_);

input [0:12] chany_bottom_in;

input [0:12] chany_top_in;

input [0:59] bl;

input [0:59] wl;

output [0:12] chany_bottom_out;

output [0:12] chany_top_out;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;









wire [0:5] mux_2level_tapbuf_size6_0_sram;
wire [0:5] mux_2level_tapbuf_size6_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_1_sram;
wire [0:5] mux_2level_tapbuf_size6_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_2_sram;
wire [0:5] mux_2level_tapbuf_size6_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_3_sram;
wire [0:5] mux_2level_tapbuf_size6_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_4_sram;
wire [0:5] mux_2level_tapbuf_size6_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_5_sram;
wire [0:5] mux_2level_tapbuf_size6_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_6_sram;
wire [0:5] mux_2level_tapbuf_size6_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_7_sram;
wire [0:5] mux_2level_tapbuf_size6_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_8_sram;
wire [0:5] mux_2level_tapbuf_size6_8_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_9_sram;
wire [0:5] mux_2level_tapbuf_size6_9_sram_inv;





	assign chany_top_out[0] = chany_bottom_in[0];



	assign chany_top_out[1] = chany_bottom_in[1];



	assign chany_top_out[2] = chany_bottom_in[2];



	assign chany_top_out[3] = chany_bottom_in[3];



	assign chany_top_out[4] = chany_bottom_in[4];



	assign chany_top_out[5] = chany_bottom_in[5];



	assign chany_top_out[6] = chany_bottom_in[6];



	assign chany_top_out[7] = chany_bottom_in[7];



	assign chany_top_out[8] = chany_bottom_in[8];



	assign chany_top_out[9] = chany_bottom_in[9];



	assign chany_top_out[10] = chany_bottom_in[10];



	assign chany_top_out[11] = chany_bottom_in[11];



	assign chany_top_out[12] = chany_bottom_in[12];



	assign chany_bottom_out[0] = chany_top_in[0];



	assign chany_bottom_out[1] = chany_top_in[1];



	assign chany_bottom_out[2] = chany_top_in[2];



	assign chany_bottom_out[3] = chany_top_in[3];



	assign chany_bottom_out[4] = chany_top_in[4];



	assign chany_bottom_out[5] = chany_top_in[5];



	assign chany_bottom_out[6] = chany_top_in[6];



	assign chany_bottom_out[7] = chany_top_in[7];



	assign chany_bottom_out[8] = chany_top_in[8];



	assign chany_bottom_out[9] = chany_top_in[9];



	assign chany_bottom_out[10] = chany_top_in[10];



	assign chany_bottom_out[11] = chany_top_in[11];



	assign chany_bottom_out[12] = chany_top_in[12];




	mux_2level_tapbuf_size6 mux_left_ipin_0 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
		.sram(mux_2level_tapbuf_size6_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_0_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));

	mux_2level_tapbuf_size6 mux_left_ipin_1 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size6_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_1_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));

	mux_2level_tapbuf_size6 mux_right_ipin_0 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size6_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_2_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_1 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size6_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_3_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_2 (
		.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
		.sram(mux_2level_tapbuf_size6_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_4_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_3 (
		.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
		.sram(mux_2level_tapbuf_size6_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_5_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_4 (
		.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
		.sram(mux_2level_tapbuf_size6_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_6_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_5 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size6_7_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_7_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_6 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size6_8_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_8_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_7 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size6_9_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_9_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));

	mux_2level_tapbuf_size6_mem mem_left_ipin_0 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size6_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_0_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_left_ipin_1 (
		.bl(bl[6:11]),
		.wl(wl[6:11]),
		.mem_out(mux_2level_tapbuf_size6_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_1_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_0 (
		.bl(bl[12:17]),
		.wl(wl[12:17]),
		.mem_out(mux_2level_tapbuf_size6_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_2_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_1 (
		.bl(bl[18:23]),
		.wl(wl[18:23]),
		.mem_out(mux_2level_tapbuf_size6_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_3_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_2 (
		.bl(bl[24:29]),
		.wl(wl[24:29]),
		.mem_out(mux_2level_tapbuf_size6_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_4_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_3 (
		.bl(bl[30:35]),
		.wl(wl[30:35]),
		.mem_out(mux_2level_tapbuf_size6_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_5_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_4 (
		.bl(bl[36:41]),
		.wl(wl[36:41]),
		.mem_out(mux_2level_tapbuf_size6_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_6_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_5 (
		.bl(bl[42:47]),
		.wl(wl[42:47]),
		.mem_out(mux_2level_tapbuf_size6_7_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_7_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_6 (
		.bl(bl[48:53]),
		.wl(wl[48:53]),
		.mem_out(mux_2level_tapbuf_size6_8_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_8_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_7 (
		.bl(bl[54:59]),
		.wl(wl[54:59]),
		.mem_out(mux_2level_tapbuf_size6_9_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_9_sram_inv[0:5]));

endmodule
module cby_0__1_(chany_bottom_in,
                 chany_top_in,
                 bl,
                 wl,
                 chany_bottom_out,
                 chany_top_out,
                 right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
                 right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
                 left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
                 left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_);


input [0:12] chany_bottom_in;

input [0:12] chany_top_in;

input [0:59] bl;

input [0:59] wl;

output [0:12] chany_bottom_out;

output [0:12] chany_top_out;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;









wire [0:5] mux_2level_tapbuf_size6_0_sram;
wire [0:5] mux_2level_tapbuf_size6_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_1_sram;
wire [0:5] mux_2level_tapbuf_size6_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_2_sram;
wire [0:5] mux_2level_tapbuf_size6_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_3_sram;
wire [0:5] mux_2level_tapbuf_size6_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_4_sram;
wire [0:5] mux_2level_tapbuf_size6_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_5_sram;
wire [0:5] mux_2level_tapbuf_size6_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_6_sram;
wire [0:5] mux_2level_tapbuf_size6_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_7_sram;
wire [0:5] mux_2level_tapbuf_size6_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_8_sram;
wire [0:5] mux_2level_tapbuf_size6_8_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_9_sram;
wire [0:5] mux_2level_tapbuf_size6_9_sram_inv;





	assign chany_top_out[0] = chany_bottom_in[0];



	assign chany_top_out[1] = chany_bottom_in[1];



	assign chany_top_out[2] = chany_bottom_in[2];



	assign chany_top_out[3] = chany_bottom_in[3];



	assign chany_top_out[4] = chany_bottom_in[4];



	assign chany_top_out[5] = chany_bottom_in[5];



	assign chany_top_out[6] = chany_bottom_in[6];



	assign chany_top_out[7] = chany_bottom_in[7];



	assign chany_top_out[8] = chany_bottom_in[8];



	assign chany_top_out[9] = chany_bottom_in[9];



	assign chany_top_out[10] = chany_bottom_in[10];



	assign chany_top_out[11] = chany_bottom_in[11];



	assign chany_top_out[12] = chany_bottom_in[12];



	assign chany_bottom_out[0] = chany_top_in[0];



	assign chany_bottom_out[1] = chany_top_in[1];



	assign chany_bottom_out[2] = chany_top_in[2];



	assign chany_bottom_out[3] = chany_top_in[3];



	assign chany_bottom_out[4] = chany_top_in[4];



	assign chany_bottom_out[5] = chany_top_in[5];



	assign chany_bottom_out[6] = chany_top_in[6];



	assign chany_bottom_out[7] = chany_top_in[7];



	assign chany_bottom_out[8] = chany_top_in[8];



	assign chany_bottom_out[9] = chany_top_in[9];



	assign chany_bottom_out[10] = chany_top_in[10];



	assign chany_bottom_out[11] = chany_top_in[11];



	assign chany_bottom_out[12] = chany_top_in[12];




	mux_2level_tapbuf_size6 mux_left_ipin_0 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
		.sram(mux_2level_tapbuf_size6_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_0_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));

	mux_2level_tapbuf_size6 mux_left_ipin_1 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size6_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_1_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));

	mux_2level_tapbuf_size6 mux_right_ipin_0 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size6_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_2_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_1 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size6_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_3_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_2 (
		.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
		.sram(mux_2level_tapbuf_size6_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_4_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_3 (
		.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
		.sram(mux_2level_tapbuf_size6_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_5_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_4 (
		.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
		.sram(mux_2level_tapbuf_size6_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_6_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_5 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size6_7_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_7_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_6 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size6_8_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_8_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_right_ipin_7 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size6_9_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_9_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));

	mux_2level_tapbuf_size6_mem mem_left_ipin_0 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size6_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_0_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_left_ipin_1 (
		.bl(bl[6:11]),
		.wl(wl[6:11]),
		.mem_out(mux_2level_tapbuf_size6_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_1_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_0 (
		.bl(bl[12:17]),
		.wl(wl[12:17]),
		.mem_out(mux_2level_tapbuf_size6_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_2_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_1 (
		.bl(bl[18:23]),
		.wl(wl[18:23]),
		.mem_out(mux_2level_tapbuf_size6_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_3_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_2 (
		.bl(bl[24:29]),
		.wl(wl[24:29]),
		.mem_out(mux_2level_tapbuf_size6_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_4_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_3 (
		.bl(bl[30:35]),
		.wl(wl[30:35]),
		.mem_out(mux_2level_tapbuf_size6_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_5_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_4 (
		.bl(bl[36:41]),
		.wl(wl[36:41]),
		.mem_out(mux_2level_tapbuf_size6_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_6_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_5 (
		.bl(bl[42:47]),
		.wl(wl[42:47]),
		.mem_out(mux_2level_tapbuf_size6_7_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_7_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_6 (
		.bl(bl[48:53]),
		.wl(wl[48:53]),
		.mem_out(mux_2level_tapbuf_size6_8_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_8_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_right_ipin_7 (
		.bl(bl[54:59]),
		.wl(wl[54:59]),
		.mem_out(mux_2level_tapbuf_size6_9_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_9_sram_inv[0:5]));

endmodule