data/full_repos/permissive/496903659/139 exams#ece241_2013_q8.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/139\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/139\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/139.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/139.sv\n             data/full_repos/permissive/496903659/139\n             data/full_repos/permissive/496903659/139.v\n             data/full_repos/permissive/496903659/139.sv\n             obj_dir/data/full_repos/permissive/496903659/139\n             obj_dir/data/full_repos/permissive/496903659/139.v\n             obj_dir/data/full_repos/permissive/496903659/139.sv\n%Error: Cannot find file containing module: exams#ece241_2013_q8.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input clk,
    input aresetn,
    input x,
    output z ); 

    reg [2:0] state, next_state;
    
    always @(*) begin
        if (x)
            next_state <= state[0] << 1 | state[1] << 1 | state[2] << 1;
		else
            next_state <= state[0] << 0 | state[1] << 2 | state[2] << 0;
    end
        
    always @(posedge clk, negedge aresetn) begin
        if (~aresetn)
            state <= 1;
        else
            state <= next_state;
    end
    
    assign z = (state == (1 << 2)) && (x == 1);
endmodule
module top_module (
    input clk,
    input aresetn,
    input x,
    output z );
 

    reg [2:0] state, next_state;
    
    always @(*) begin
        if (x)
            next_state <= state[0] << 1 | state[1] << 1 | state[2] << 1;
		else
            next_state <= state[0] << 0 | state[1] << 2 | state[2] << 0;
    end
        
    always @(posedge clk, negedge aresetn) begin
        if (~aresetn)
            state <= 1;
        else
            state <= next_state;
    end
    
    assign z = (state == (1 << 2)) && (x == 1);
endmodule