data/full_repos/permissive/52703097/divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52703097/divider.v:20: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'bits\' generates 5 bits.\n                                                                : ... In instance divider\n    assign ready = !bits;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52703097/divider.v:29: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh20\' generates 32 or 6 bits.\n                                                                : ... In instance divider\n            bits = 32;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/52703097/divider.v:34: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bits\' generates 5 bits.\n                                                                : ... In instance divider\n        else if (bits) begin\n             ^~\n%Error: Exiting due to 3 warning(s)\n'
module divider(
    input start,
    input clk,
    input [`WIDTH-1:0] dividend,
    input [`WIDTH-1:0] divisor,
    output reg [`WIDTH-1:0] quotient,
    output [`WIDTH-1:0] remainder,
    output ready);

    reg [`WIDTH+`WIDTH-1:0] dividend_copy, divisor_copy, diff;
    assign remainder = dividend_copy[`WIDTH-1:0];
    reg [4:0] bits;
    assign ready = !bits;
    
    initial begin
        bits = 0;
    end


    always @ (posedge clk) begin
        if (ready & start) begin
            bits = `WIDTH;
            quotient = 0;
            dividend_copy = {`WIDTH'd0, dividend};
            divisor_copy = {1'b0, divisor, 31'd0};
        end
        else if (bits) begin
            diff = dividend_copy - divisor_copy;
            quotient = quotient << 1;

            if (!diff[`WIDTH+`WIDTH-1]) begin
                dividend_copy = diff;
                quotient[0] = 1'd1;
            end

            divisor_copy = divisor_copy >> 1;
            bits = bits - 1;
        end
    end

endmodule
module divider(
    input start,
    input clk,
    input [`WIDTH-1:0] dividend,
    input [`WIDTH-1:0] divisor,
    output reg [`WIDTH-1:0] quotient,
    output [`WIDTH-1:0] remainder,
    output ready);


    reg [`WIDTH+`WIDTH-1:0] dividend_copy, divisor_copy, diff;
    assign remainder = dividend_copy[`WIDTH-1:0];
    reg [4:0] bits;
    assign ready = !bits;
    
    initial begin
        bits = 0;
    end


    always @ (posedge clk) begin
        if (ready & start) begin
            bits = `WIDTH;
            quotient = 0;
            dividend_copy = {`WIDTH'd0, dividend};
            divisor_copy = {1'b0, divisor, 31'd0};
        end
        else if (bits) begin
            diff = dividend_copy - divisor_copy;
            quotient = quotient << 1;

            if (!diff[`WIDTH+`WIDTH-1]) begin
                dividend_copy = diff;
                quotient[0] = 1'd1;
            end

            divisor_copy = divisor_copy >> 1;
            bits = bits - 1;
        end
    end

endmodule