data/full_repos/permissive/434840709/week12/6.v
data/verilator_xmls/39fe9617-20ca-4d05-bc5b-92c35df070ed.xml
module top_module (
    input d, 
    input ena,
    output q
); 
    reg Q = 0;
    always@ (ena or d)begin
        if(ena)
           Q = d; 
    end 
    assign q = Q;
endmodule
module top_module (
    input d, 
    input ena,
    output q
);
 
    reg Q = 0;
    always@ (ena or d)begin
        if(ena)
           Q = d; 
    end 
    assign q = Q;
endmodule