data/full_repos/permissive/453464110/SRAM_V_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #5 i_clk = ~i_clk ;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 addr_in = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 d_in = 32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 rw = 1\'b0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 addr_in = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #2 rw = 1\'b1 ;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_in = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#10 d_in = 47;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#10 rw = 1\'b0;   \n^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 addr_in = 2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3 rw = 1\'b1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #40 addr_in = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 d_in = 14 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1 rw = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10 addr_in = 3 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #2 rw = 1\'b1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453464110/SRAM_V_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #550 $stop ;\n  ^\n%Error: data/full_repos/permissive/453464110/SRAM_V_tb.v:13: Cannot find file containing module: \'SRAM_V\'\nSRAM_V DUT  (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/453464110,data/full_repos/permissive/453464110/SRAM_V\n             data/full_repos/permissive/453464110,data/full_repos/permissive/453464110/SRAM_V.v\n             data/full_repos/permissive/453464110,data/full_repos/permissive/453464110/SRAM_V.sv\n             SRAM_V\n             SRAM_V.v\n             SRAM_V.sv\n             obj_dir/SRAM_V\n             obj_dir/SRAM_V.v\n             obj_dir/SRAM_V.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SRAM_V_tb ();
parameter n = 8 ;
parameter m = 10 ;
reg i_clk ;
reg [n-1:0] d_in ;
reg rw ;
reg [m-1:0] addr_in ;
wire [n-1:0] data_out ;


SRAM_V DUT  (
      d_in , 
		i_clk , 
		rw , 
		addr_in , 
	   data_out ) ;
		
	initial
    begin
	  i_clk = 1'b0 ;
   end
 

always #5 i_clk = ~i_clk ;



initial
   begin

 #10 addr_in = 0;
 #10 d_in = 32;
 #10 rw = 1'b0;
 #10 addr_in = 1;

  
  #2 rw = 1'b1 ;
 
  #10 addr_in = 0;
#10 d_in = 47;
#10 rw = 1'b0;
 #10 addr_in = 2;
 
 #3 rw = 1'b1 ;
 
 #40 addr_in = 0;
 #5 d_in = 14 ;
 #1 rw = 1'b0;
 #10 addr_in = 3 ;
 
 #2 rw = 1'b1 ;
 
  #550 $stop ;
  
 
		end
		endmodule
module SRAM_V_tb ();

parameter n = 8 ;
parameter m = 10 ;
reg i_clk ;
reg [n-1:0] d_in ;
reg rw ;
reg [m-1:0] addr_in ;
wire [n-1:0] data_out ;


SRAM_V DUT  (
      d_in , 
		i_clk , 
		rw , 
		addr_in , 
	   data_out ) ;
		
	initial
    begin
	  i_clk = 1'b0 ;
   end
 

always #5 i_clk = ~i_clk ;



initial
   begin

 #10 addr_in = 0;
 #10 d_in = 32;
 #10 rw = 1'b0;
 #10 addr_in = 1;

  
  #2 rw = 1'b1 ;
 
  #10 addr_in = 0;
#10 d_in = 47;
#10 rw = 1'b0;
 #10 addr_in = 2;
 
 #3 rw = 1'b1 ;
 
 #40 addr_in = 0;
 #5 d_in = 14 ;
 #1 rw = 1'b0;
 #10 addr_in = 3 ;
 
 #2 rw = 1'b1 ;
 
  #550 $stop ;
  
 
		end
		endmodule