data/full_repos/permissive/456468799/Verilog/ColourMuxBit.v
data/verilator_xmls/95f899a8-026d-46fc-ad95-3b08d1f1f4c6.xml
module ColourMuxBit(input CLK_n,
                    input COLOUR_KEEP,
                    input BORDER_SEL,
                    input BORDER,
                    input INK_SEL,
                    input[15 : 0] INKR,
                    input[3 : 0] CIDX,
                    input MODE_IS_0,
                    input MODE_IS_2,
                    output reg INK);

  wire u1701,
       u1702,
       u1703,
       u1718,
       u1719,
       u1720,
       u1721;
  wire [3 : 0] ink_0;
  wire [3 : 0] ink_1;
  wire [3 : 0] muxOutput;

  assign u1701 = CIDX[2] & MODE_IS_0;
  assign ink_0 = { (u1701 | INKR[1]) & (INKR[5] | ~u1701), (u1701 | INKR[3]) & (INKR[7] | ~u1701), (u1701 | INKR[0]) & (INKR[4] | ~u1701), (u1701 | INKR[2]) & (INKR[6] | ~u1701) };
  assign ink_1 = { (u1701 | INKR[9]) & (INKR[13] | ~u1701), (u1701 | INKR[11]) & (INKR[15] | ~u1701), (u1701 | INKR[8]) & (INKR[12] | ~u1701), (u1701 | INKR[10]) & (INKR[14] | ~u1701) };
  assign u1702 = CIDX[3] & MODE_IS_0;
  assign muxOutput = u1702 ? ink_1 : ink_0;
  assign u1703 = CIDX[1] & ~MODE_IS_2;
  assign u1718 = (u1703 | muxOutput[3]) & (~u1703 | muxOutput[2]);
  assign u1719 = (u1703 | muxOutput[1]) & (~u1703 | muxOutput[0]);
  assign u1720 = INK_SEL & CIDX[0] & u1718;
  assign u1721 = INK_SEL & ~CIDX[0] & u1719;

  always
    @(posedge CLK_n)
      INK = (INK & COLOUR_KEEP) | (BORDER_SEL & BORDER) | u1720 | u1721;
endmodule
module ColourMuxBit(input CLK_n,
                    input COLOUR_KEEP,
                    input BORDER_SEL,
                    input BORDER,
                    input INK_SEL,
                    input[15 : 0] INKR,
                    input[3 : 0] CIDX,
                    input MODE_IS_0,
                    input MODE_IS_2,
                    output reg INK);


  wire u1701,
       u1702,
       u1703,
       u1718,
       u1719,
       u1720,
       u1721;
  wire [3 : 0] ink_0;
  wire [3 : 0] ink_1;
  wire [3 : 0] muxOutput;

  assign u1701 = CIDX[2] & MODE_IS_0;
  assign ink_0 = { (u1701 | INKR[1]) & (INKR[5] | ~u1701), (u1701 | INKR[3]) & (INKR[7] | ~u1701), (u1701 | INKR[0]) & (INKR[4] | ~u1701), (u1701 | INKR[2]) & (INKR[6] | ~u1701) };
  assign ink_1 = { (u1701 | INKR[9]) & (INKR[13] | ~u1701), (u1701 | INKR[11]) & (INKR[15] | ~u1701), (u1701 | INKR[8]) & (INKR[12] | ~u1701), (u1701 | INKR[10]) & (INKR[14] | ~u1701) };
  assign u1702 = CIDX[3] & MODE_IS_0;
  assign muxOutput = u1702 ? ink_1 : ink_0;
  assign u1703 = CIDX[1] & ~MODE_IS_2;
  assign u1718 = (u1703 | muxOutput[3]) & (~u1703 | muxOutput[2]);
  assign u1719 = (u1703 | muxOutput[1]) & (~u1703 | muxOutput[0]);
  assign u1720 = INK_SEL & CIDX[0] & u1718;
  assign u1721 = INK_SEL & ~CIDX[0] & u1719;

  always
    @(posedge CLK_n)
      INK = (INK & COLOUR_KEEP) | (BORDER_SEL & BORDER) | u1720 | u1721;
endmodule