data/full_repos/permissive/43856783/j1_soc/hdl/divider/div_16/counter_div.v
data/verilator_xmls/a5bb63c2-9fe7-4dcb-8a92-019eeca1da55.xml
module counter_div (clk , rst, DEC, z);

  input clk;
  input rst;
  input DEC;
  output reg z;

  reg [4:0] cont=16;


always @(negedge clk) begin


  if (rst) 
   cont = 5'b10000;
  else
     begin
      if (DEC) cont=cont-1;
      else cont=cont;
     end

 z = (cont==0) ? 1 : 0 ;


end

endmodule
module counter_div (clk , rst, DEC, z);


  input clk;
  input rst;
  input DEC;
  output reg z;

  reg [4:0] cont=16;


always @(negedge clk) begin


  if (rst) 
   cont = 5'b10000;
  else
     begin
      if (DEC) cont=cont-1;
      else cont=cont;
     end

 z = (cont==0) ? 1 : 0 ;


end

endmodule