data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #period CLK  = ~ CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #(2*period);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #2 CLR = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 CLR = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #3 CE = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #400;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2CLR = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #400;\n ^\n%Error: data/full_repos/permissive/458313092/Prescaler/Prescaler_tb.v:11: Cannot find file containing module: \'Prescaler\'\nPrescaler #(.divide_factor(15)) presc_tb (.CLK(CLK),.CE(CE),.CLR(CLR), .CEO(CEO));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458313092/Prescaler,data/full_repos/permissive/458313092/Prescaler\n             data/full_repos/permissive/458313092/Prescaler,data/full_repos/permissive/458313092/Prescaler.v\n             data/full_repos/permissive/458313092/Prescaler,data/full_repos/permissive/458313092/Prescaler.sv\n             Prescaler\n             Prescaler.v\n             Prescaler.sv\n             obj_dir/Prescaler\n             obj_dir/Prescaler.v\n             obj_dir/Prescaler.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Prescaler_tb;
localparam period = 4;
reg CLK;
reg CE;
reg CLR;

wire CEO;

Prescaler #(.divide_factor(15)) presc_tb (.CLK(CLK),.CE(CE),.CLR(CLR), .CEO(CEO));

initial begin
    CLK = 1'b0;
    CE = 1'b0;
    CLR = 1'b0;


end

always begin
    #period CLK  = ~ CLK;
end

always begin
    #(2*period);
    #2 CLR = 1'b1;
    #1 CLR = 1'b0;
    #3 CE = 1'b1;

    #400;
	#2CLR = 1'b1;
	#400;
    $stop;


end
endmodule
module Prescaler_tb;

localparam period = 4;
reg CLK;
reg CE;
reg CLR;

wire CEO;

Prescaler #(.divide_factor(15)) presc_tb (.CLK(CLK),.CE(CE),.CLR(CLR), .CEO(CEO));

initial begin
    CLK = 1'b0;
    CE = 1'b0;
    CLR = 1'b0;


end

always begin
    #period CLK  = ~ CLK;
end

always begin
    #(2*period);
    #2 CLR = 1'b1;
    #1 CLR = 1'b0;
    #3 CE = 1'b1;

    #400;
	#2CLR = 1'b1;
	#400;
    $stop;


end
endmodule