data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n         #10     clock = ~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:60: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:67: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:73: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:77: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:83: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:87: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:93: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:97: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:107: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:114: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:120: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:124: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:130: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:134: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:140: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:144: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:154: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:161: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:169: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:175: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:186: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:193: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:203: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:210: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:218: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:224: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:233: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:239: syntax error, unexpected \'@\'\n                @(negedge clock);\n                ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:250: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:257: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:267: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:274: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:284: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:291: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:297: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:301: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:308: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:312: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:322: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:329: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:335: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:339: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:345: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:349: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:355: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:361: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:367: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:371: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:377: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: data/full_repos/permissive/499137621/CheckPoint1_32bit_ALU_project-main/alu_tb.v:381: syntax error, unexpected \'@\'\n            @(negedge clock);\n            ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();



    reg            clock;
    reg [31:0] data_operandA, data_operandB, data_expected;
    reg [4:0] ctrl_ALUopcode, ctrl_shiftamt;



    wire [31:0] data_result;
    wire isNotEqual, isLessThan, overflow;



    integer errors;
    integer index;



    alu alu_ut(data_operandA, data_operandB, ctrl_ALUopcode, ctrl_shiftamt,
        data_result, isNotEqual, isLessThan, overflow);

    initial

    begin
        $display($time, " << Starting the Simulation >>");
        clock = 1'b0;
        errors = 0;



        checkAdd();
        checkSub();





        checkOverflow();

        if(errors == 0) begin
            $display("The simulation completed without errors");
        end
        else begin
            $display("The simulation failed with %d errors", errors);
        end

        $stop;
    end


    always
         #10     clock = ~clock;

    task checkOr;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00011;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in OR (test 1); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 2); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 3); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 4); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkAnd;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00010;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 5); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 6); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 7); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in AND (test 8); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkAdd;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00000;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in ADD (test 9); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            for(index = 0; index < 31; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001 << index;
                assign data_operandB = 32'h00000001 << index;

                assign data_expected = 32'h00000001 << (index + 1);

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in ADD (test 17 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end
        end
    endtask

    task checkSub;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in SUB (test 10); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkSLL;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00100;
            assign data_operandB = 32'h00000000;

            assign data_operandA = 32'h00000001;
            assign ctrl_shiftamt = 5'b00000;

            @(negedge clock);
            if(data_result !== 32'h00000001) begin
                $display("**Error in SLL (test 11); expected: %h, actual: %h", 32'h00000001, data_result);
                errors = errors + 1;
            end

            for(index = 0; index < 5; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001;
                assign ctrl_shiftamt = 5'b00001 << index;

                assign data_expected = 32'h00000001 << (2**index);

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in SLL (test 18 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end

            for(index = 0; index < 4; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001;
                assign ctrl_shiftamt = 5'b00011 << index;

                assign data_expected = 32'h00000001 << ((2**index) + (2**(index + 1)));

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in SLL (test 19 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end
        end
    endtask

    task checkSRA;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00101;
            assign data_operandB = 32'h00000000;

            assign data_operandA = 32'h00000000;
            assign ctrl_shiftamt = 5'b00000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in SRA (test 12); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkNE;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(isNotEqual !== 1'b0) begin
                $display("**Error in isNotEqual (test 13); expected: %b, actual: %b", 1'b0, isNotEqual);
                errors = errors + 1;
            end
        end
    endtask

    task checkLT;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(isLessThan !== 1'b0) begin
                $display("**Error in isLessThan (test 14); expected: %b, actual: %b", 1'b0, isLessThan);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h0FFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(isLessThan !== 1'b0) begin
                $display("**Error in isLessThan (test 23); expected: %b, actual: %b", 1'b0, isLessThan);
                errors = errors + 1;
            end


            @(negedge clock);
            assign data_operandA = 32'h80000001;
            assign data_operandB = 32'h7FFFFFFF;

            @(negedge clock);
            if(isLessThan !== 1'b1) begin
                $display("**Error in isLessThan (test 24); expected: %b, actual: %b", 1'b1, isLessThan);
                errors = errors + 1;
            end
        end
    endtask

    task checkOverflow;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00000;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 15); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h80000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 20); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h40000000;
            assign data_operandB = 32'h40000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 21); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 16); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h80000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 22); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h0F000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 25); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end
        end
    endtask

endmodule
module alu_tb();




    reg            clock;
    reg [31:0] data_operandA, data_operandB, data_expected;
    reg [4:0] ctrl_ALUopcode, ctrl_shiftamt;



    wire [31:0] data_result;
    wire isNotEqual, isLessThan, overflow;



    integer errors;
    integer index;



    alu alu_ut(data_operandA, data_operandB, ctrl_ALUopcode, ctrl_shiftamt,
        data_result, isNotEqual, isLessThan, overflow);

    initial

    begin
        $display($time, " << Starting the Simulation >>");
        clock = 1'b0;
        errors = 0;



        checkAdd();
        checkSub();





        checkOverflow();

        if(errors == 0) begin
            $display("The simulation completed without errors");
        end
        else begin
            $display("The simulation failed with %d errors", errors);
        end

        $stop;
    end


    always
         #10     clock = ~clock;

    task checkOr;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00011;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in OR (test 1); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 2); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 3); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in OR (test 4); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkAnd;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00010;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 5); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 6); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in AND (test 7); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'hFFFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(data_result !== 32'hFFFFFFFF) begin
                $display("**Error in AND (test 8); expected: %h, actual: %h", 32'hFFFFFFFF, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkAdd;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00000;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in ADD (test 9); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end

            for(index = 0; index < 31; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001 << index;
                assign data_operandB = 32'h00000001 << index;

                assign data_expected = 32'h00000001 << (index + 1);

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in ADD (test 17 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end
        end
    endtask

    task checkSub;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in SUB (test 10); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkSLL;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00100;
            assign data_operandB = 32'h00000000;

            assign data_operandA = 32'h00000001;
            assign ctrl_shiftamt = 5'b00000;

            @(negedge clock);
            if(data_result !== 32'h00000001) begin
                $display("**Error in SLL (test 11); expected: %h, actual: %h", 32'h00000001, data_result);
                errors = errors + 1;
            end

            for(index = 0; index < 5; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001;
                assign ctrl_shiftamt = 5'b00001 << index;

                assign data_expected = 32'h00000001 << (2**index);

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in SLL (test 18 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end

            for(index = 0; index < 4; index = index + 1)
            begin
                @(negedge clock);
                assign data_operandA = 32'h00000001;
                assign ctrl_shiftamt = 5'b00011 << index;

                assign data_expected = 32'h00000001 << ((2**index) + (2**(index + 1)));

                @(negedge clock);
                if(data_result !== data_expected) begin
                    $display("**Error in SLL (test 19 part %d); expected: %h, actual: %h", index, data_expected, data_result);
                    errors = errors + 1;
                end
            end
        end
    endtask

    task checkSRA;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00101;
            assign data_operandB = 32'h00000000;

            assign data_operandA = 32'h00000000;
            assign ctrl_shiftamt = 5'b00000;

            @(negedge clock);
            if(data_result !== 32'h00000000) begin
                $display("**Error in SRA (test 12); expected: %h, actual: %h", 32'h00000000, data_result);
                errors = errors + 1;
            end
        end
    endtask

    task checkNE;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(isNotEqual !== 1'b0) begin
                $display("**Error in isNotEqual (test 13); expected: %b, actual: %b", 1'b0, isNotEqual);
                errors = errors + 1;
            end
        end
    endtask

    task checkLT;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(isLessThan !== 1'b0) begin
                $display("**Error in isLessThan (test 14); expected: %b, actual: %b", 1'b0, isLessThan);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h0FFFFFFF;
            assign data_operandB = 32'hFFFFFFFF;

            @(negedge clock);
            if(isLessThan !== 1'b0) begin
                $display("**Error in isLessThan (test 23); expected: %b, actual: %b", 1'b0, isLessThan);
                errors = errors + 1;
            end


            @(negedge clock);
            assign data_operandA = 32'h80000001;
            assign data_operandB = 32'h7FFFFFFF;

            @(negedge clock);
            if(isLessThan !== 1'b1) begin
                $display("**Error in isLessThan (test 24); expected: %b, actual: %b", 1'b1, isLessThan);
                errors = errors + 1;
            end
        end
    endtask

    task checkOverflow;
        begin
            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00000;
            assign ctrl_shiftamt = 5'b00000;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 15); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h80000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 20); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h40000000;
            assign data_operandB = 32'h40000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 21); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign ctrl_ALUopcode = 5'b00001;

            assign data_operandA = 32'h00000000;
            assign data_operandB = 32'h00000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 16); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h80000000;

            @(negedge clock);
            if(overflow !== 1'b0) begin
                $display("**Error in overflow (test 22); expected: %b, actual: %b", 1'b0, overflow);
                errors = errors + 1;
            end

            @(negedge clock);
            assign data_operandA = 32'h80000000;
            assign data_operandB = 32'h0F000000;

            @(negedge clock);
            if(overflow !== 1'b1) begin
                $display("**Error in overflow (test 25); expected: %b, actual: %b", 1'b1, overflow);
                errors = errors + 1;
            end
        end
    endtask

endmodule