data/full_repos/permissive/416058412/hw/rtl/ccip_std_afu.sv
1: b'%Error: data/full_repos/permissive/416058412/hw/rtl/ccip_std_afu.sv:41: Cannot find include file: ccip_async_shim.sv\n`include "ccip_async_shim.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/ccip_async_shim.sv\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/ccip_async_shim.sv.v\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/ccip_async_shim.sv.sv\n             ccip_async_shim.sv\n             ccip_async_shim.sv.v\n             ccip_async_shim.sv.sv\n             obj_dir/ccip_async_shim.sv\n             obj_dir/ccip_async_shim.sv.v\n             obj_dir/ccip_async_shim.sv.sv\n%Error: data/full_repos/permissive/416058412/hw/rtl/ccip_std_afu.sv:46: Cannot find include file: top_level_loopback.sv\n`include "top_level_loopback.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ccip_std_afu (

    input           logic             pClk,
    input           logic             pClkDiv2,
    input           logic             pClkDiv4,
    input           logic             uClk_usr,
    input           logic             uClk_usrDiv2,
    input           logic             pck_cp2af_softReset,
    input           logic [1:0]       pck_cp2af_pwrState,
    input           logic             pck_cp2af_error,


`ifdef PLATFORM_PAC_A10

    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx,


    pr_hssi_if.to_fiu   hssi
`else

    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx
`endif

    );


    `ifdef PHY_NETWORK
        `ifndef PLATFORM_PAC_A10
            $error("Physical networking is only supported when building for the PAC-A10 patform")
        `endif
    `endif


`ifdef SYS_CLOCK_200

    $info("Building system with medium frequencies");

    t_if_ccip_Tx afu_tx;
    t_if_ccip_Rx afu_rx;

    logic reset_pass;


    ccip_async_shim cross_clock (
        .bb_softreset(pck_cp2af_softReset),
        .bb_clk(pClk),
        .bb_tx(pck_af2cp_sTx),
        .bb_rx(pck_cp2af_sRx),

        .afu_softreset(reset_pass),
        .afu_clk(pClkDiv2),
        .afu_tx(afu_tx),
        .afu_rx(afu_rx)
    );


`ifdef PHY_NETWORK
    $info("Building system with physical networking support");

    top_level_network_module top_level (
        .pClk(pClkDiv2),
        .pClkDiv2(pClkDiv2),
        .pReset(reset_pass),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx),

        .hssi(hssi)
    );
`else
    $info("Building system with loopback networking support");

    top_level_loopback_module top_level (
        .pClk(pClkDiv2),
        .pClkDiv2(pClkDiv2),
        .pReset(reset_pass),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx)
    );
`endif

`elsif SYS_CLOCK_400

    $info("Building system with high frequencies");

`ifdef PHY_NETWORK
    $info("Building system with physical networking support");

    top_level_network_module top_level (
        .pClk(pClk),
        .pClkDiv2(pClkDiv2),
        .pReset(pck_cp2af_softReset),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx),

        .hssi(hssi)
    );
`else
    $info("Building system with loopback networking support");

    top_level_loopback_module top_level (
        .pClk(pClk),
        .pClkDiv2(pClkDiv2),
        .pReset(pck_cp2af_softReset),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx)
    );
`endif

`else
    $error("** Illegal Configuration ** the system clock is not defined");

`endif


endmodule
module ccip_std_afu (

    input           logic             pClk,
    input           logic             pClkDiv2,
    input           logic             pClkDiv4,
    input           logic             uClk_usr,
    input           logic             uClk_usrDiv2,
    input           logic             pck_cp2af_softReset,
    input           logic [1:0]       pck_cp2af_pwrState,
    input           logic             pck_cp2af_error,


`ifdef PLATFORM_PAC_A10

    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx,


    pr_hssi_if.to_fiu   hssi
`else

    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx
`endif

    );



    `ifdef PHY_NETWORK
        `ifndef PLATFORM_PAC_A10
            $error("Physical networking is only supported when building for the PAC-A10 patform")
        `endif
    `endif


`ifdef SYS_CLOCK_200

    $info("Building system with medium frequencies");

    t_if_ccip_Tx afu_tx;
    t_if_ccip_Rx afu_rx;

    logic reset_pass;


    ccip_async_shim cross_clock (
        .bb_softreset(pck_cp2af_softReset),
        .bb_clk(pClk),
        .bb_tx(pck_af2cp_sTx),
        .bb_rx(pck_cp2af_sRx),

        .afu_softreset(reset_pass),
        .afu_clk(pClkDiv2),
        .afu_tx(afu_tx),
        .afu_rx(afu_rx)
    );


`ifdef PHY_NETWORK
    $info("Building system with physical networking support");

    top_level_network_module top_level (
        .pClk(pClkDiv2),
        .pClkDiv2(pClkDiv2),
        .pReset(reset_pass),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx),

        .hssi(hssi)
    );
`else
    $info("Building system with loopback networking support");

    top_level_loopback_module top_level (
        .pClk(pClkDiv2),
        .pClkDiv2(pClkDiv2),
        .pReset(reset_pass),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx)
    );
`endif

`elsif SYS_CLOCK_400

    $info("Building system with high frequencies");

`ifdef PHY_NETWORK
    $info("Building system with physical networking support");

    top_level_network_module top_level (
        .pClk(pClk),
        .pClkDiv2(pClkDiv2),
        .pReset(pck_cp2af_softReset),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx),

        .hssi(hssi)
    );
`else
    $info("Building system with loopback networking support");

    top_level_loopback_module top_level (
        .pClk(pClk),
        .pClkDiv2(pClkDiv2),
        .pReset(pck_cp2af_softReset),

        .pck_cp2af_sRx(afu_rx),
        .pck_af2cp_sTx(afu_tx)
    );
`endif

`else
    $error("** Illegal Configuration ** the system clock is not defined");

`endif


endmodule