data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_ps2/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_ps2,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_ps2/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire clk,
    input wire [7:0] in,
    input wire reset,
    output reg done
);

  parameter STATE_BYTE1 = 2'b00;
  parameter STATE_BYTE2 = 2'b01;
  parameter STATE_BYTE3 = 2'b10;
  parameter STATE_DONE = 2'b11;

  reg [1:0] state, next_state = STATE_BYTE1;


  always @(*) begin
    casez ({
      in[3], state
    })
      {1'b0, STATE_BYTE1} : next_state = STATE_BYTE1;
      {1'b1, STATE_BYTE1} : next_state = STATE_BYTE2;
      {1'bz, STATE_BYTE2} : next_state = STATE_BYTE3;
      {1'bz, STATE_BYTE3} : next_state = STATE_DONE;
      {1'b0, STATE_DONE} : next_state = STATE_BYTE1;
      {1'b1, STATE_DONE} : next_state = STATE_BYTE2;
      default: next_state = state;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_BYTE1;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      STATE_DONE: done = 1'b1;
      default: done = 1'b0;
    endcase
  end
endmodule
module top_module (
    input wire clk,
    input wire [7:0] in,
    input wire reset,
    output reg done
);


  parameter STATE_BYTE1 = 2'b00;
  parameter STATE_BYTE2 = 2'b01;
  parameter STATE_BYTE3 = 2'b10;
  parameter STATE_DONE = 2'b11;

  reg [1:0] state, next_state = STATE_BYTE1;


  always @(*) begin
    casez ({
      in[3], state
    })
      {1'b0, STATE_BYTE1} : next_state = STATE_BYTE1;
      {1'b1, STATE_BYTE1} : next_state = STATE_BYTE2;
      {1'bz, STATE_BYTE2} : next_state = STATE_BYTE3;
      {1'bz, STATE_BYTE3} : next_state = STATE_DONE;
      {1'b0, STATE_DONE} : next_state = STATE_BYTE1;
      {1'b1, STATE_DONE} : next_state = STATE_BYTE2;
      default: next_state = state;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_BYTE1;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      STATE_DONE: done = 1'b1;
      default: done = 1'b0;
    endcase
  end
endmodule