data/full_repos/permissive/444327372/mycpu_top.v
1: b"%Error: data/full_repos/permissive/444327372/mycpu_top.v:4: syntax error, unexpected int, expecting IDENTIFIER or '[' or do or final\n input wire[5:0] int,  \n                 ^~~\n%Error: data/full_repos/permissive/444327372/mycpu_top.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [3 :0] debug_wb_rf_wen,\n ^~~~~~\n%Error: data/full_repos/permissive/444327372/mycpu_top.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [4 :0] debug_wb_rf_wnum,\n ^~~~~~\n%Error: data/full_repos/permissive/444327372/mycpu_top.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [31:0] debug_wb_rf_wdata\n ^~~~~~\n%Error: data/full_repos/permissive/444327372/mycpu_top.v:26: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/444327372/mycpu_top.v:37: syntax error, unexpected IDENTIFIER\n    mips mips(\n    ^~~~\n%Error: Exiting due to 6 error(s)\n"
module mycpu_top(    
    input clk,
    input resetn,
	input wire[5:0] int,


    output        inst_sram_en   ,
    output [3 :0] inst_sram_wen  ,
    output [31:0] inst_sram_addr ,
    output [31:0] inst_sram_wdata,
    input  [31:0] inst_sram_rdata,
    

    output        data_sram_en   ,
    output [3 :0] data_sram_wen  ,
    output [31:0] data_sram_addr ,
    output [31:0] data_sram_wdata,

    input  [31:0] data_sram_rdata,


	output wire [31:0] debug_wb_pc,
	output wire [3 :0] debug_wb_rf_wen,
	output wire [4 :0] debug_wb_rf_wnum,
	output wire [31:0] debug_wb_rf_wdata
);


	wire [31:0] pc;
	wire [31:0] instr;
    wire memenM;
	wire memwrite;
	wire [31:0] aluout, writedata, readdata;
    wire [3:0] selM;
    wire [1:0] sizeM;
    
    mips mips(
        .clk(~clk),
        .rst(~resetn),
        


        .pcF(pc),
        .instrF(instr),
    


        .memenM(memenM),
        .memwriteM(memwrite),
        .aluoutM(aluout),
        .writedataM(writedata),
        .readdataM(readdata),
        
        .selM(selM),


        .debug_wb_pc(debug_wb_pc),
	    .debug_wb_rf_wen(debug_wb_rf_wen),
	    .debug_wb_rf_wnum(debug_wb_rf_wnum),
	    .debug_wb_rf_wdata(debug_wb_rf_wdata)
    );

    assign inst_sram_en = 1'b1;
    assign inst_sram_wen = 4'b0;

    assign inst_sram_wdata = 32'b0;
    assign instr = inst_sram_rdata;


    assign data_sram_en = 1'b1;


    assign data_sram_wen = selM;

    assign data_sram_wdata = writedata;
    assign readdata = data_sram_rdata;








    mmu mmu(
        .inst_vaddr(pc),
        .inst_paddr(inst_sram_addr),
        .data_vaddr(aluout),
        .data_paddr(data_sram_addr)

    );
endmodule
module mycpu_top(    
    input clk,
    input resetn,
	input wire[5:0] int,


    output        inst_sram_en   ,
    output [3 :0] inst_sram_wen  ,
    output [31:0] inst_sram_addr ,
    output [31:0] inst_sram_wdata,
    input  [31:0] inst_sram_rdata,
    

    output        data_sram_en   ,
    output [3 :0] data_sram_wen  ,
    output [31:0] data_sram_addr ,
    output [31:0] data_sram_wdata,

    input  [31:0] data_sram_rdata,


	output wire [31:0] debug_wb_pc,
	output wire [3 :0] debug_wb_rf_wen,
	output wire [4 :0] debug_wb_rf_wnum,
	output wire [31:0] debug_wb_rf_wdata
);



	wire [31:0] pc;
	wire [31:0] instr;
    wire memenM;
	wire memwrite;
	wire [31:0] aluout, writedata, readdata;
    wire [3:0] selM;
    wire [1:0] sizeM;
    
    mips mips(
        .clk(~clk),
        .rst(~resetn),
        


        .pcF(pc),
        .instrF(instr),
    


        .memenM(memenM),
        .memwriteM(memwrite),
        .aluoutM(aluout),
        .writedataM(writedata),
        .readdataM(readdata),
        
        .selM(selM),


        .debug_wb_pc(debug_wb_pc),
	    .debug_wb_rf_wen(debug_wb_rf_wen),
	    .debug_wb_rf_wnum(debug_wb_rf_wnum),
	    .debug_wb_rf_wdata(debug_wb_rf_wdata)
    );

    assign inst_sram_en = 1'b1;
    assign inst_sram_wen = 4'b0;

    assign inst_sram_wdata = 32'b0;
    assign instr = inst_sram_rdata;


    assign data_sram_en = 1'b1;


    assign data_sram_wen = selM;

    assign data_sram_wdata = writedata;
    assign readdata = data_sram_rdata;








    mmu mmu(
        .inst_vaddr(pc),
        .inst_paddr(inst_sram_addr),
        .data_vaddr(aluout),
        .data_paddr(data_sram_addr)

    );
endmodule