data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:27: Signal definition not found, creating implicitly: \'signc1\'\n                                                                                       : ... Suggested alternative: \'signa\'\n    assign seg7Digit[27:24] = signc1 + 14;\n                              ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:24: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'signb\' generates 1 bits.\n                                                                                    : ... In instance top\n    assign seg7Digit[7:4] = signb + 14; \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:26: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'signa\' generates 1 bits.\n                                                                                    : ... In instance top\n    assign seg7Digit[15:12] = signa + 14;  \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:27: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'signc1\' generates 1 bits.\n                                                                                    : ... In instance top\n    assign seg7Digit[27:24] = signc1 + 14;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:28: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'asm\' generates 2 bits.\n                                                                                    : ... In instance top\n    assign seg7Digit[31:28] = asm;\n                            ^\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:32: Cannot find file containing module: \'ALU\'\n    ALU alu_wrapper(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/ALU\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/ALU.v\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:43: Cannot find file containing module: \'bin2bcd\'\n    bin2bcd b2bwrap(\n    ^~~~~~~\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top.v:48: Cannot find file containing module: \'SEGDRIVE\'\n    SEGDRIVE seg7driver_wrapper(\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module top(

    input [3:0] opa,
    input [3:0] opb,
    input signa,
    input signb,
    input [1:0] asm,




    input clkt, 
    output [6:0] Cnode1,
    output [7:0] AN1,
    output seg
    );

    wire [31:0] seg7Digit; 

    assign seg7Digit[3:0] = opb; 
    assign seg7Digit[7:4] = signb + 14; 
    assign seg7Digit[11:8] = opa; 
    assign seg7Digit[15:12] = signa + 14;  
    assign seg7Digit[27:24] = signc1 + 14;
    assign seg7Digit[31:28] = asm;
    
    wire [7:0] opc;
    
    ALU alu_wrapper(
     .opa(opa),
     .opb(opb),
     .signa(signa),
     .signb(signb),
     .asm(asm),
     .opc(opc),
     .signc1(signc1)
    );
    
    
    bin2bcd b2bwrap(
    .bin(opc),
    .bcd(seg7Digit[23:16])
   );

    SEGDRIVE seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(seg7Digit),
         .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
    
    
    
    
endmodule
module top(

    input [3:0] opa,
    input [3:0] opb,
    input signa,
    input signb,
    input [1:0] asm,




    input clkt, 
    output [6:0] Cnode1,
    output [7:0] AN1,
    output seg
    );


    wire [31:0] seg7Digit; 

    assign seg7Digit[3:0] = opb; 
    assign seg7Digit[7:4] = signb + 14; 
    assign seg7Digit[11:8] = opa; 
    assign seg7Digit[15:12] = signa + 14;  
    assign seg7Digit[27:24] = signc1 + 14;
    assign seg7Digit[31:28] = asm;
    
    wire [7:0] opc;
    
    ALU alu_wrapper(
     .opa(opa),
     .opb(opb),
     .signa(signa),
     .signb(signb),
     .asm(asm),
     .opc(opc),
     .signc1(signc1)
    );
    
    
    bin2bcd b2bwrap(
    .bin(opc),
    .bcd(seg7Digit[23:16])
   );

    SEGDRIVE seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(seg7Digit),
         .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
    
    
    
    
endmodule