data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test folder/clk.v
1: b'%Error: Cannot find file containing module: folder,data/full_repos/permissive/496231454\n        ... Looked in:\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454.v\n             data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test/folder,data/full_repos/permissive/496231454.sv\n             folder,data/full_repos/permissive/496231454\n             folder,data/full_repos/permissive/496231454.v\n             folder,data/full_repos/permissive/496231454.sv\n             obj_dir/folder,data/full_repos/permissive/496231454\n             obj_dir/folder,data/full_repos/permissive/496231454.v\n             obj_dir/folder,data/full_repos/permissive/496231454.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/496231454/VGA_Controller.srcs/sources_1/imports/test\n%Error: Cannot find file containing module: folder/clk.v\n%Error: Exiting due to 3 error(s)\n'
module clock_divider(
 input wire clk,
 output reg divided_clk = 0
);
 localparam divided_value = 1;
 integer counter_value = 0;
 
always@ (posedge clk)
begin
  if (counter_value == divided_value)
     counter_value <= 0;
     else
     counter_value <= counter_value+1;
   end
   
always@ (posedge clk)
begin
  if (counter_value == divided_value)
    divided_clk <= ~divided_clk;
    else
    divided_clk <= divided_clk;
  end
endmodule
module clock_divider(
 input wire clk,
 output reg divided_clk = 0
);

 localparam divided_value = 1;
 integer counter_value = 0;
 
always@ (posedge clk)
begin
  if (counter_value == divided_value)
     counter_value <= 0;
     else
     counter_value <= counter_value+1;
   end
   
always@ (posedge clk)
begin
  if (counter_value == divided_value)
    divided_clk <= ~divided_clk;
    else
    divided_clk <= divided_clk;
  end
endmodule