data/full_repos/permissive/492581806/ins_Cache.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #0.9 hit=1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #0.9 hit=1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:108: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:240: Unsupported: Ignoring delay on this delayed statement.\n                 #1;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/ins_Cache.v:265: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/492581806/ins_Cache.v:268: Operator ASSIGN expects 132 bits on the Assign RHS, but Assign RHS\'s CONST \'131\'h0\' generates 131 bits.\n                                                                    : ... In instance ins_cache\n            iCache[j] = 131\'b0;\n                      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ins_cache (clock,PC,reset,c_instruction,c_busywait,mem_instruction,imem_read,imem_address,imem_busywait);

    input  clock, reset,imem_busywait;
    input [31:0] PC;
    input [127:0] mem_instruction;
    
    output reg imem_read,c_busywait;
    output reg [5:0] imem_address;
    output reg [31:0] c_instruction;
    
    reg [31:0] instruction;

   reg [1:0]  offset;
   reg [2:0]  index;
   reg [2:0]  PCaddress_tag,tag;
   reg [131:0] iCache [7:0];
   reg [127:0] BLOCK;
   reg hit;
   reg validbit;
  


always @(*)begin
		
		

		#1;



            offset         =  PC[3:2];
			index          =  PC[6:4];
            PCaddress_tag  =  PC[9:7]; 
             
    



			BLOCK    =  iCache[index][127:0];
			tag      =  iCache[index][130:128];
			validbit =  iCache[index][131];
			
			
		
		
	
end




always @(PCaddress_tag,tag,validbit)
begin

if(tag==PCaddress_tag && validbit)

begin


  #0.9 hit=1'b1;

end  


else
begin


  #0.9 hit=1'b0;

end 

end










   always@(BLOCK[31:0],BLOCK[63:32],BLOCK[95:64],BLOCK[127:96],offset) 

   begin



  
   #1;
   case(offset)
         2'b00 :instruction=BLOCK[31:0]; 
         2'b01 :instruction=BLOCK[63:32];
         2'b10 :instruction=BLOCK[95:64];
         2'b11 :instruction=BLOCK[127:96];
   
  endcase
 
  end
    



   
    


always @(posedge clock)begin

if(!hit) begin


c_busywait = 1'b1;

end

else


c_busywait=1'b0;

end


/

    parameter IDLE = 2'b00, IMEM_READ = 2'b01,IC_WRITE=2'b10;
    reg [1:0] state, nextstate;


    always @(*)
    begin
        case (state)

            IDLE:
            begin

            if(!hit)
              nextstate=IMEM_READ;
            else
              nextstate=IDLE; 
            
            end


           IMEM_READ:

           begin

            if(!imem_busywait)
               nextstate=IC_WRITE;
            else
                nextstate=IMEM_READ;

            end
           
           IC_WRITE:
             
               nextstate=IDLE; 
            
           
               
        endcase

    end


    always @(*)
    begin
        case(state)
            IDLE:
            begin
               imem_read = 0;
               imem_address = 6'dx;
               
            end
         
            IMEM_READ: 
            begin
                imem_read = 1;
                imem_address ={tag,index};
                c_busywait=1;
                
            end


          
	        IC_WRITE:
            begin
                imem_read = 1'd0;
                imem_address = 6'dx;
                


                 #1;
				iCache[index][127:0]   = mem_instruction;
				iCache[index][130:128] = PCaddress_tag;
			    iCache[index][131]   = 1'd1;

			
            end
            
            
            
            
        endcase
    end



    integer j;
   
    always @(posedge clock, reset)
    
    begin
        if(reset)
        begin
            state = IDLE;
            c_busywait=1'b0;
             #1;
             for( j=0;j<8;j=j+1)
            begin
            iCache[j] = 131'b0;
            end
        end
        
        else begin
            state = nextstate;
         end
    end


endmodule
module ins_cache (clock,PC,reset,c_instruction,c_busywait,mem_instruction,imem_read,imem_address,imem_busywait);


    input  clock, reset,imem_busywait;
    input [31:0] PC;
    input [127:0] mem_instruction;
    
    output reg imem_read,c_busywait;
    output reg [5:0] imem_address;
    output reg [31:0] c_instruction;
    
    reg [31:0] instruction;

   reg [1:0]  offset;
   reg [2:0]  index;
   reg [2:0]  PCaddress_tag,tag;
   reg [131:0] iCache [7:0];
   reg [127:0] BLOCK;
   reg hit;
   reg validbit;
  


always @(*)begin
		
		

		#1;



            offset         =  PC[3:2];
			index          =  PC[6:4];
            PCaddress_tag  =  PC[9:7]; 
             
    



			BLOCK    =  iCache[index][127:0];
			tag      =  iCache[index][130:128];
			validbit =  iCache[index][131];
			
			
		
		
	
end




always @(PCaddress_tag,tag,validbit)
begin

if(tag==PCaddress_tag && validbit)

begin


  #0.9 hit=1'b1;

end  


else
begin


  #0.9 hit=1'b0;

end 

end










   always@(BLOCK[31:0],BLOCK[63:32],BLOCK[95:64],BLOCK[127:96],offset) 

   begin



  
   #1;
   case(offset)
         2'b00 :instruction=BLOCK[31:0]; 
         2'b01 :instruction=BLOCK[63:32];
         2'b10 :instruction=BLOCK[95:64];
         2'b11 :instruction=BLOCK[127:96];
   
  endcase
 
  end
    



   
    


always @(posedge clock)begin

if(!hit) begin


c_busywait = 1'b1;

end

else


c_busywait=1'b0;

end


/

    parameter IDLE = 2'b00, IMEM_READ = 2'b01,IC_WRITE=2'b10;
    reg [1:0] state, nextstate;


    always @(*)
    begin
        case (state)

            IDLE:
            begin

            if(!hit)
              nextstate=IMEM_READ;
            else
              nextstate=IDLE; 
            
            end


           IMEM_READ:

           begin

            if(!imem_busywait)
               nextstate=IC_WRITE;
            else
                nextstate=IMEM_READ;

            end
           
           IC_WRITE:
             
               nextstate=IDLE; 
            
           
               
        endcase

    end


    always @(*)
    begin
        case(state)
            IDLE:
            begin
               imem_read = 0;
               imem_address = 6'dx;
               
            end
         
            IMEM_READ: 
            begin
                imem_read = 1;
                imem_address ={tag,index};
                c_busywait=1;
                
            end


          
	        IC_WRITE:
            begin
                imem_read = 1'd0;
                imem_address = 6'dx;
                


                 #1;
				iCache[index][127:0]   = mem_instruction;
				iCache[index][130:128] = PCaddress_tag;
			    iCache[index][131]   = 1'd1;

			
            end
            
            
            
            
        endcase
    end



    integer j;
   
    always @(posedge clock, reset)
    
    begin
        if(reset)
        begin
            state = IDLE;
            c_busywait=1'b0;
             #1;
             for( j=0;j<8;j=j+1)
            begin
            iCache[j] = 131'b0;
            end
        end
        
        else begin
            state = nextstate;
         end
    end


endmodule