data/full_repos/permissive/48250786/regparam.v
data/verilator_xmls/25fcd244-8155-4538-be0c-dfd728571426.xml
module regparam 
	# (parameter SIZE = 16)
	(output reg [SIZE-1:0] Q,
    input [SIZE-1:0] D,
    input clk,
    input rst,
    input clken
    );
	 
	 always @(posedge clk, posedge rst)
	 begin
		if(rst)
			Q <= 0;
		else if(clken)
			Q <= D;
	 end

endmodule
module regparam 
	# (parameter SIZE = 16)
	(output reg [SIZE-1:0] Q,
    input [SIZE-1:0] D,
    input clk,
    input rst,
    input clken
    );

	 
	 always @(posedge clk, posedge rst)
	 begin
		if(rst)
			Q <= 0;
		else if(clken)
			Q <= D;
	 end

endmodule