data/full_repos/permissive/516084506/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.functional.v
1: b"%Error: data/full_repos/permissive/516084506/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.functional.v:23: syntax error, unexpected '(', expecting IDENTIFIER\n UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );\n                                                                     ^~~\n%Error: Exiting due to 1 error(s)\n"
module gf180mcu_fd_sc_mcu9t5v0__icgtp_2( TE, E, CLK, Q, notifier );
input CLK, E, TE, notifier;
output Q;

	not MGM_BG_0( MGM_EN0, CLK );

	or MGM_BG_1( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );

	and MGM_BG_2( Q, CLK, IQ2 );

endmodule
module gf180mcu_fd_sc_mcu9t5v0__icgtp_2( TE, E, CLK, Q, notifier );

input CLK, E, TE, notifier;
output Q;

	not MGM_BG_0( MGM_EN0, CLK );

	or MGM_BG_1( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );

	and MGM_BG_2( Q, CLK, IQ2 );

endmodule