data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_synch_jldl.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_synch_jldl.v:26: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_clsp_synch_jldl(

ctu_dram13_dram_cken_dl, ctu_dram02_dram_cken_dl, ctu_dll3_byp_val, 
ctu_dll3_byp_l, ctu_dll2_byp_val, ctu_dll2_byp_l, ctu_dll1_byp_val, 
ctu_dll1_byp_l, ctu_dll0_byp_val, ctu_dll0_byp_l, 
ctu_ddr3_dram_cken_dl, ctu_ddr3_dll_delayctr, ctu_ddr2_dram_cken_dl, 
ctu_ddr2_dll_delayctr, ctu_ddr1_dram_cken_dl, ctu_ddr1_dll_delayctr, 
ctu_ddr0_dram_cken_dl, ctu_ddr0_dll_delayctr, ctu_ddr0_iodll_rst_l, 
ctu_ddr1_iodll_rst_l, ctu_ddr2_iodll_rst_l, ctu_ddr3_iodll_rst_l, 
start_clk_dl, 

ctu_dram13_cken_cl, ctu_dram02_cken_cl, ctu_dll3_byp_val_jl, 
ctu_dll3_byp_l_jl, ctu_dll2_byp_val_jl, ctu_dll2_byp_l_jl, 
ctu_dll1_byp_val_jl, ctu_dll1_byp_l_jl, ctu_dll0_byp_val_jl, 
ctu_dll0_byp_l_jl, ctu_ddr3_iodll_rst_jl_l, ctu_ddr3_dll_delayctr_jl, 
ctu_ddr3_cken_cl, ctu_ddr2_iodll_rst_jl_l, ctu_ddr2_dll_delayctr_jl, 
ctu_ddr2_cken_cl, ctu_ddr1_iodll_rst_jl_l, ctu_ddr1_dll_delayctr_jl, 
ctu_ddr1_cken_cl, ctu_ddr0_iodll_rst_jl_l, ctu_ddr0_dll_delayctr_jl, 
ctu_ddr0_cken_cl, coin_edge, cmp_clk, jbus_rx_sync, start_clk_cl, 
io_pwron_rst_l, ctu_dram_tx_sync_early
);



input			cmp_clk;
input			coin_edge;
input			ctu_ddr0_cken_cl;
input [2:0]		ctu_ddr0_dll_delayctr_jl;
input			ctu_ddr0_iodll_rst_jl_l;
input			ctu_ddr1_cken_cl;
input [2:0]		ctu_ddr1_dll_delayctr_jl;
input			ctu_ddr1_iodll_rst_jl_l;
input			ctu_ddr2_cken_cl;
input [2:0]		ctu_ddr2_dll_delayctr_jl;
input			ctu_ddr2_iodll_rst_jl_l;
input			ctu_ddr3_cken_cl;
input [2:0]		ctu_ddr3_dll_delayctr_jl;
input			ctu_ddr3_iodll_rst_jl_l;
input			ctu_dll0_byp_l_jl;
input [4:0]		ctu_dll0_byp_val_jl;
input			ctu_dll1_byp_l_jl;
input [4:0]		ctu_dll1_byp_val_jl;
input			ctu_dll2_byp_l_jl;
input [4:0]		ctu_dll2_byp_val_jl;
input			ctu_dll3_byp_l_jl;
input [4:0]		ctu_dll3_byp_val_jl;
input			ctu_dram02_cken_cl;
input			ctu_dram13_cken_cl;

input			jbus_rx_sync;
input                   start_clk_cl;
input                   io_pwron_rst_l;
input			ctu_dram_tx_sync_early;


output [2:0]		ctu_ddr0_dll_delayctr;
output			ctu_ddr0_dram_cken_dl;
output [2:0]		ctu_ddr1_dll_delayctr;
output			ctu_ddr1_dram_cken_dl;
output [2:0]		ctu_ddr2_dll_delayctr;
output			ctu_ddr2_dram_cken_dl;
output [2:0]		ctu_ddr3_dll_delayctr;
output			ctu_ddr3_dram_cken_dl;
output			ctu_dll0_byp_l;
output [4:0]		ctu_dll0_byp_val;
output			ctu_dll1_byp_l;
output [4:0]		ctu_dll1_byp_val;
output			ctu_dll2_byp_l;
output [4:0]		ctu_dll2_byp_val;
output			ctu_dll3_byp_l;
output [4:0]		ctu_dll3_byp_val;
output			ctu_dram02_dram_cken_dl;
output			ctu_dram13_dram_cken_dl;

output                  ctu_ddr0_iodll_rst_l;
output                  ctu_ddr1_iodll_rst_l;
output                  ctu_ddr2_iodll_rst_l;
output                  ctu_ddr3_iodll_rst_l;
output                  start_clk_dl;



wire           jbus_rx_sync_gated;


    assign  jbus_rx_sync_gated = jbus_rx_sync & start_clk_cl;



    dffrle_ns u_start_clk_dl (
       .din (start_clk_cl),
       .q(start_clk_dl),
       .en (ctu_dram_tx_sync_early ),
       .rst_l(start_clk_cl), 
       .clk (cmp_clk)
    );



    ctu_synch_cl_dl u_ctu_dram02_dram_cken (

					    .syncdata(ctu_dram02_dram_cken_dl),

					    .cmp_clk(cmp_clk),
					    .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					    .presyncdata(ctu_dram02_cken_cl));
    ctu_synch_cl_dl u_ctu_dram13_dram_cken (

					    .syncdata(ctu_dram13_dram_cken_dl),

					    .cmp_clk(cmp_clk),
					    .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					    .presyncdata(ctu_dram13_cken_cl));



    

    ctu_synch_jl_dl #(3) u_ctu_ddr0_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr0_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr0_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr1_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr1_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr1_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr2_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr2_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr2_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr3_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr3_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr3_dll_delayctr_jl[2:0]));



    ctu_synch_jl_dl u_ctu_dll0_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll0_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll0_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll1_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll1_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll1_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll2_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll2_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll2_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll3_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll3_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll3_byp_l_jl));



    ctu_synch_jl_dl #(5) u_ctu_dll0_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll0_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll0_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll1_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll1_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll1_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll2_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll2_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll2_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll3_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll3_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll3_byp_val_jl[4:0]));


    ctu_synch_cl_dl u_ctu_ddr0_dram_cken (

					  .syncdata(ctu_ddr0_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr0_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr1_dram_cken (

					  .syncdata(ctu_ddr1_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr1_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr2_dram_cken (

					  .syncdata(ctu_ddr2_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr2_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr3_dram_cken (

					  .syncdata(ctu_ddr3_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr3_cken_cl));




      ctu_synch_jl_dl u_ctu_ddr0_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr0_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr0_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr1_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr1_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr1_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr2_iodll_rst_dl_l(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr2_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr2_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr3_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr3_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr3_iodll_rst_jl_l));





endmodule
module ctu_clsp_synch_jldl(

ctu_dram13_dram_cken_dl, ctu_dram02_dram_cken_dl, ctu_dll3_byp_val, 
ctu_dll3_byp_l, ctu_dll2_byp_val, ctu_dll2_byp_l, ctu_dll1_byp_val, 
ctu_dll1_byp_l, ctu_dll0_byp_val, ctu_dll0_byp_l, 
ctu_ddr3_dram_cken_dl, ctu_ddr3_dll_delayctr, ctu_ddr2_dram_cken_dl, 
ctu_ddr2_dll_delayctr, ctu_ddr1_dram_cken_dl, ctu_ddr1_dll_delayctr, 
ctu_ddr0_dram_cken_dl, ctu_ddr0_dll_delayctr, ctu_ddr0_iodll_rst_l, 
ctu_ddr1_iodll_rst_l, ctu_ddr2_iodll_rst_l, ctu_ddr3_iodll_rst_l, 
start_clk_dl, 

ctu_dram13_cken_cl, ctu_dram02_cken_cl, ctu_dll3_byp_val_jl, 
ctu_dll3_byp_l_jl, ctu_dll2_byp_val_jl, ctu_dll2_byp_l_jl, 
ctu_dll1_byp_val_jl, ctu_dll1_byp_l_jl, ctu_dll0_byp_val_jl, 
ctu_dll0_byp_l_jl, ctu_ddr3_iodll_rst_jl_l, ctu_ddr3_dll_delayctr_jl, 
ctu_ddr3_cken_cl, ctu_ddr2_iodll_rst_jl_l, ctu_ddr2_dll_delayctr_jl, 
ctu_ddr2_cken_cl, ctu_ddr1_iodll_rst_jl_l, ctu_ddr1_dll_delayctr_jl, 
ctu_ddr1_cken_cl, ctu_ddr0_iodll_rst_jl_l, ctu_ddr0_dll_delayctr_jl, 
ctu_ddr0_cken_cl, coin_edge, cmp_clk, jbus_rx_sync, start_clk_cl, 
io_pwron_rst_l, ctu_dram_tx_sync_early
);




input			cmp_clk;
input			coin_edge;
input			ctu_ddr0_cken_cl;
input [2:0]		ctu_ddr0_dll_delayctr_jl;
input			ctu_ddr0_iodll_rst_jl_l;
input			ctu_ddr1_cken_cl;
input [2:0]		ctu_ddr1_dll_delayctr_jl;
input			ctu_ddr1_iodll_rst_jl_l;
input			ctu_ddr2_cken_cl;
input [2:0]		ctu_ddr2_dll_delayctr_jl;
input			ctu_ddr2_iodll_rst_jl_l;
input			ctu_ddr3_cken_cl;
input [2:0]		ctu_ddr3_dll_delayctr_jl;
input			ctu_ddr3_iodll_rst_jl_l;
input			ctu_dll0_byp_l_jl;
input [4:0]		ctu_dll0_byp_val_jl;
input			ctu_dll1_byp_l_jl;
input [4:0]		ctu_dll1_byp_val_jl;
input			ctu_dll2_byp_l_jl;
input [4:0]		ctu_dll2_byp_val_jl;
input			ctu_dll3_byp_l_jl;
input [4:0]		ctu_dll3_byp_val_jl;
input			ctu_dram02_cken_cl;
input			ctu_dram13_cken_cl;

input			jbus_rx_sync;
input                   start_clk_cl;
input                   io_pwron_rst_l;
input			ctu_dram_tx_sync_early;


output [2:0]		ctu_ddr0_dll_delayctr;
output			ctu_ddr0_dram_cken_dl;
output [2:0]		ctu_ddr1_dll_delayctr;
output			ctu_ddr1_dram_cken_dl;
output [2:0]		ctu_ddr2_dll_delayctr;
output			ctu_ddr2_dram_cken_dl;
output [2:0]		ctu_ddr3_dll_delayctr;
output			ctu_ddr3_dram_cken_dl;
output			ctu_dll0_byp_l;
output [4:0]		ctu_dll0_byp_val;
output			ctu_dll1_byp_l;
output [4:0]		ctu_dll1_byp_val;
output			ctu_dll2_byp_l;
output [4:0]		ctu_dll2_byp_val;
output			ctu_dll3_byp_l;
output [4:0]		ctu_dll3_byp_val;
output			ctu_dram02_dram_cken_dl;
output			ctu_dram13_dram_cken_dl;

output                  ctu_ddr0_iodll_rst_l;
output                  ctu_ddr1_iodll_rst_l;
output                  ctu_ddr2_iodll_rst_l;
output                  ctu_ddr3_iodll_rst_l;
output                  start_clk_dl;



wire           jbus_rx_sync_gated;


    assign  jbus_rx_sync_gated = jbus_rx_sync & start_clk_cl;



    dffrle_ns u_start_clk_dl (
       .din (start_clk_cl),
       .q(start_clk_dl),
       .en (ctu_dram_tx_sync_early ),
       .rst_l(start_clk_cl), 
       .clk (cmp_clk)
    );



    ctu_synch_cl_dl u_ctu_dram02_dram_cken (

					    .syncdata(ctu_dram02_dram_cken_dl),

					    .cmp_clk(cmp_clk),
					    .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					    .presyncdata(ctu_dram02_cken_cl));
    ctu_synch_cl_dl u_ctu_dram13_dram_cken (

					    .syncdata(ctu_dram13_dram_cken_dl),

					    .cmp_clk(cmp_clk),
					    .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					    .presyncdata(ctu_dram13_cken_cl));



    

    ctu_synch_jl_dl #(3) u_ctu_ddr0_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr0_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr0_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr1_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr1_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr1_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr2_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr2_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr2_dll_delayctr_jl[2:0]));
    ctu_synch_jl_dl #(3) u_ctu_ddr3_dll_delayctr(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						 .syncdata(ctu_ddr3_dll_delayctr[2:0]),

						 .cmp_clk(cmp_clk),
						 .coin_edge(coin_edge),
						 .arst_l(io_pwron_rst_l),
						 .presyncdata(ctu_ddr3_dll_delayctr_jl[2:0]));



    ctu_synch_jl_dl u_ctu_dll0_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll0_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll0_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll1_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll1_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll1_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll2_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll2_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll2_byp_l_jl));
    ctu_synch_jl_dl u_ctu_dll3_byp_l(
				     .jbus_rx_sync(jbus_rx_sync_gated), 


				     .syncdata(ctu_dll3_byp_l),

				     .cmp_clk(cmp_clk),
				     .coin_edge(coin_edge),
				     .arst_l(io_pwron_rst_l),
				     .presyncdata(ctu_dll3_byp_l_jl));



    ctu_synch_jl_dl #(5) u_ctu_dll0_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll0_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll0_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll1_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll1_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll1_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll2_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll2_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll2_byp_val_jl[4:0]));
    ctu_synch_jl_dl #(5) u_ctu_dll3_byp_val(
				            .jbus_rx_sync(jbus_rx_sync_gated), 


					    .syncdata(ctu_dll3_byp_val[4:0]),

					    .cmp_clk(cmp_clk),
					    .coin_edge(coin_edge),
					    .arst_l(io_pwron_rst_l),
					    .presyncdata(ctu_dll3_byp_val_jl[4:0]));


    ctu_synch_cl_dl u_ctu_ddr0_dram_cken (

					  .syncdata(ctu_ddr0_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr0_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr1_dram_cken (

					  .syncdata(ctu_ddr1_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr1_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr2_dram_cken (

					  .syncdata(ctu_ddr2_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr2_cken_cl));
    ctu_synch_cl_dl u_ctu_ddr3_dram_cken (

					  .syncdata(ctu_ddr3_dram_cken_dl),

					  .cmp_clk(cmp_clk),
					  .ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
					  .presyncdata(ctu_ddr3_cken_cl));




      ctu_synch_jl_dl u_ctu_ddr0_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr0_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr0_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr1_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr1_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr1_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr2_iodll_rst_dl_l(
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr2_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr2_iodll_rst_jl_l));
      ctu_synch_jl_dl u_ctu_ddr3_iodll_rst_dl_l( 
						 .jbus_rx_sync(jbus_rx_sync_gated),


						.syncdata(ctu_ddr3_iodll_rst_l),

						.cmp_clk(cmp_clk),
						.coin_edge(coin_edge),
						.arst_l(io_pwron_rst_l),
						.presyncdata(ctu_ddr3_iodll_rst_jl_l));





endmodule