data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/shftl2.v
data/verilator_xmls/4fe40428-e188-4259-b2c1-37c343d768ea.xml
module shftl2 (
  input       [31:0] a,
  output wire [31:0] y
);



assign y = {a[29:0], 2'b00};

endmodule
module shftl2 (
  input       [31:0] a,
  output wire [31:0] y
);




assign y = {a[29:0], 2'b00};

endmodule