data/full_repos/permissive/50192283/endian_swap.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/50192283/endian_swap.sv:3: Little bit endian vector: MSB < LSB of bit range: 0:63\n  input [0:63] in,\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/endian_swap.sv:4: Little bit endian vector: MSB < LSB of bit range: 0:63\n  output reg [0:63] out);\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module endian_swap (
  input clock,
  input [0:63] in,
  output reg [0:63] out);

  always @ (posedge clock)
    out <= {in[56:63], in[48:55], in[40:47], in[32:39],
            in[24:31], in[16:23], in[8:15],  in[0:7]};
endmodule
module endian_swap (
  input clock,
  input [0:63] in,
  output reg [0:63] out);


  always @ (posedge clock)
    out <= {in[56:63], in[48:55], in[40:47], in[32:39],
            in[24:31], in[16:23], in[8:15],  in[0:7]};
endmodule