data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:12: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;\n                                                                                                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                                                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;\n                                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                                                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;\n                                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                                                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;\n                                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0   ; #5 RSLCT[7:4] = 0  ; #5 RSLCT[11:8] = 0  ; #5 RSLCT[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;\n                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:26: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0   ; #6 RSLCT[7:4] = 0  ; #6 RSLCT[11:8] = 0  ; #6 RSLCT[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;\n                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n #7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0   ; #7 RSLCT[7:4] = 0  ; #7 RSLCT[11:8] = 0  ; #7 RSLCT[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;\n                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0   ; #8 RSLCT[7:4] = 0  ; #8 RSLCT[11:8] = 0  ; #8 RSLCT[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;\n                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n #9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0   ; #9 RSLCT[7:4] = 0  ; #9 RSLCT[11:8] = 0  ; #9 RSLCT[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;\n                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0   ; #10 RSLCT[7:4] = 0  ; #10 RSLCT[11:8] = 0  ; #10 RSLCT[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;\n                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n #11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0   ; #11 RSLCT[7:4] = 0  ; #11 RSLCT[11:8] = 0  ; #11 RSLCT[15:12] = 0  ; #11 RSLCT[19:16] = 0   ;\n                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:38: Unsupported: Ignoring delay on this delayed statement.\n #12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0   ; #12 RSLCT[7:4] = 0  ; #12 RSLCT[11:8] = 0  ; #12 RSLCT[15:12] = 0  ; #12 RSLCT[19:16] = 0   ;\n                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:44: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:47: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("RegisterFileTestBench4.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:48: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,RegisterFileTestBench4);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench4.v:50: Unsupported or unknown PLI call: $monitor\n $monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 123 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFileTestBench4;

parameter sim_time = 750*2;

reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;

RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork

	Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ;

	#1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0; #1 RSLCT[7:4] = 0; #1 RSLCT[11:8] = 0; #1 RSLCT[15:12] = 0; #1 RSLCT[19:16] = 0;

	#2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0; #2 RSLCT[7:4] = 0; #2 RSLCT[11:8] = 0; #2 RSLCT[15:12] = 0; #2 RSLCT[19:16] = 0;

	#3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0; #3 RSLCT[7:4] = 0; #3 RSLCT[11:8] = 0; #3 RSLCT[15:12] = 0; #3 RSLCT[19:16] = 0;

	#4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0; #4 RSLCT[7:4] = 0; #4 RSLCT[11:8] = 0; #4 RSLCT[15:12] = 0; #4 RSLCT[19:16] = 0;

	#5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0; #5 RSLCT[7:4] = 0; #5 RSLCT[11:8] = 0; #5 RSLCT[15:12] = 0; #5 RSLCT[19:16] = 0;

	#6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0; #6 RSLCT[7:4] = 0; #6 RSLCT[11:8] = 0; #6 RSLCT[15:12] = 0; #6 RSLCT[19:16] = 0;

	#7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0; #7 RSLCT[7:4] = 0; #7 RSLCT[11:8] = 0; #7 RSLCT[15:12] = 0; #7 RSLCT[19:16] = 0;

	#8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0; #8 RSLCT[7:4] = 0; #8 RSLCT[11:8] = 0; #8 RSLCT[15:12] = 0; #8 RSLCT[19:16] = 0;

	#9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0; #9 RSLCT[7:4] = 0; #9 RSLCT[11:8] = 0; #9 RSLCT[15:12] = 0; #9 RSLCT[19:16] = 0;

	#10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0; #10 RSLCT[7:4] = 0; #10 RSLCT[11:8] = 0; #10 RSLCT[15:12] = 0; #10 RSLCT[19:16] = 0;

	#11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0; #11 RSLCT[7:4] = 0; #11 RSLCT[11:8] = 0; #11 RSLCT[15:12] = 0; #11 RSLCT[19:16] = 0;

	#12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0; #12 RSLCT[7:4] = 0; #12 RSLCT[11:8] = 0; #12 RSLCT[15:12] = 0; #12 RSLCT[19:16] = 0;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("RegisterFileTestBench4.vcd");
	$dumpvars(0,RegisterFileTestBench4);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end

endmodule
module RegisterFileTestBench4;


parameter sim_time = 750*2;

reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;

RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork

	Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ;

	#1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0; #1 RSLCT[7:4] = 0; #1 RSLCT[11:8] = 0; #1 RSLCT[15:12] = 0; #1 RSLCT[19:16] = 0;

	#2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0; #2 RSLCT[7:4] = 0; #2 RSLCT[11:8] = 0; #2 RSLCT[15:12] = 0; #2 RSLCT[19:16] = 0;

	#3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0; #3 RSLCT[7:4] = 0; #3 RSLCT[11:8] = 0; #3 RSLCT[15:12] = 0; #3 RSLCT[19:16] = 0;

	#4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0; #4 RSLCT[7:4] = 0; #4 RSLCT[11:8] = 0; #4 RSLCT[15:12] = 0; #4 RSLCT[19:16] = 0;

	#5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0; #5 RSLCT[7:4] = 0; #5 RSLCT[11:8] = 0; #5 RSLCT[15:12] = 0; #5 RSLCT[19:16] = 0;

	#6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0; #6 RSLCT[7:4] = 0; #6 RSLCT[11:8] = 0; #6 RSLCT[15:12] = 0; #6 RSLCT[19:16] = 0;

	#7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0; #7 RSLCT[7:4] = 0; #7 RSLCT[11:8] = 0; #7 RSLCT[15:12] = 0; #7 RSLCT[19:16] = 0;

	#8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0; #8 RSLCT[7:4] = 0; #8 RSLCT[11:8] = 0; #8 RSLCT[15:12] = 0; #8 RSLCT[19:16] = 0;

	#9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0; #9 RSLCT[7:4] = 0; #9 RSLCT[11:8] = 0; #9 RSLCT[15:12] = 0; #9 RSLCT[19:16] = 0;

	#10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0; #10 RSLCT[7:4] = 0; #10 RSLCT[11:8] = 0; #10 RSLCT[15:12] = 0; #10 RSLCT[19:16] = 0;

	#11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0; #11 RSLCT[7:4] = 0; #11 RSLCT[11:8] = 0; #11 RSLCT[15:12] = 0; #11 RSLCT[19:16] = 0;

	#12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0; #12 RSLCT[7:4] = 0; #12 RSLCT[11:8] = 0; #12 RSLCT[15:12] = 0; #12 RSLCT[19:16] = 0;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("RegisterFileTestBench4.vcd");
	$dumpvars(0,RegisterFileTestBench4);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end

endmodule