data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pwr_supply_clk_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pwr_supply_clk_gen.v:63: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'counter\' generates 9 bits.\n                                                                                                     : ... In instance pwr_supply_clk_gen\n    if (counter == MAX_COUNT-1) begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwr_supply_clk_gen#(
  parameter SOURCE_CLK_FREQ = 100_000_000,
  parameter TARGET_CLK_FREQ =     100_000
) (

  input wire clk,
  input wire rst,


  output reg pwr_supply_clk
);








localparam MAX_COUNT = SOURCE_CLK_FREQ / TARGET_CLK_FREQ / 2;
localparam COUNTER_W = $clog2(MAX_COUNT);
reg [COUNTER_W-1:0] counter = 0;









always @(posedge clk) begin
  if (rst) begin
    counter <= 0;
    pwr_supply_clk <= 1'b0;
  end
  else begin

    counter <= counter + 1'b1;



    if (counter == MAX_COUNT-1) begin
      counter <= 0;
      pwr_supply_clk <= ~pwr_supply_clk;
    end
  end
end

endmodule
module pwr_supply_clk_gen#(
  parameter SOURCE_CLK_FREQ = 100_000_000,
  parameter TARGET_CLK_FREQ =     100_000
) (

  input wire clk,
  input wire rst,


  output reg pwr_supply_clk
);









localparam MAX_COUNT = SOURCE_CLK_FREQ / TARGET_CLK_FREQ / 2;
localparam COUNTER_W = $clog2(MAX_COUNT);
reg [COUNTER_W-1:0] counter = 0;









always @(posedge clk) begin
  if (rst) begin
    counter <= 0;
    pwr_supply_clk <= 1'b0;
  end
  else begin

    counter <= counter + 1'b1;



    if (counter == MAX_COUNT-1) begin
      counter <= 0;
      pwr_supply_clk <= ~pwr_supply_clk;
    end
  end
end

endmodule