data/full_repos/permissive/493514142/verilog/rtl/FPU/LZD_mux.v
data/verilator_xmls/5b56b7de-a7d2-4d8c-a928-ff25c92d3699.xml
module FPU_LZD_mux  (in_pos_1, in_val_1, in_pos_2, in_val_2, out_pos, out_val);




parameter layer = 1;

input [layer-1 : 0] in_pos_1, in_pos_2;
input in_val_1, in_val_2;

output [layer : 0]out_pos;
output out_val;

assign out_val = in_val_1 | in_val_2;
assign out_pos = in_val_2 ? {!in_val_2, in_pos_2} : {!in_val_2, in_pos_1} ; 

endmodule
module FPU_LZD_mux  (in_pos_1, in_val_1, in_pos_2, in_val_2, out_pos, out_val);





parameter layer = 1;

input [layer-1 : 0] in_pos_1, in_pos_2;
input in_val_1, in_val_2;

output [layer : 0]out_pos;
output out_val;

assign out_val = in_val_1 | in_val_2;
assign out_pos = in_val_2 ? {!in_val_2, in_pos_2} : {!in_val_2, in_pos_1} ; 

endmodule