data/full_repos/permissive/426823752/hex_converter.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426823752/hex_converter.sv:69: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance hex_converter\n  case(in[15:11])\n  ^~~~\n%Error: Exiting due to 16 warning(s)\n'
module hex_converter(input [15:0] in,
							output logic [7:0] out_th, out_hu, out_te, out_on
							);

	logic [31:00] temp;
	always_comb
	begin
		temp = 32'h0;
		case(in[3:0])
			4'h0 : temp[7:0] = 8'h30;
			4'h1 : temp[7:0] = 8'h31;
			4'h2 : temp[7:0] = 8'h32;
			4'h3 : temp[7:0] = 8'h33;
			4'h4 : temp[7:0] = 8'h34;
			4'h5 : temp[7:0] = 8'h35;
			4'h6 : temp[7:0] = 8'h36;
			4'h7 : temp[7:0] = 8'h37;
			4'h8 : temp[7:0] = 8'h38;
			4'h9 : temp[7:0] = 8'h39;
			4'ha : temp[7:0] = 8'h41;
			4'hb : temp[7:0] = 8'h42;
			4'hc : temp[7:0] = 8'h43;
			4'hd : temp[7:0] = 8'h44;
			4'he : temp[7:0] = 8'h45;
			4'hf : temp[7:0] = 8'h46;
			default: ;
		endcase

		case(in[7:4])
			4'h0 : temp[15:8] = 8'h30;
			4'h1 : temp[15:8] = 8'h31;
			4'h2 : temp[15:8] = 8'h32;
			4'h3 : temp[15:8] = 8'h33;
			4'h4 : temp[15:8] = 8'h34;
			4'h5 : temp[15:8] = 8'h35;
			4'h6 : temp[15:8] = 8'h36;
			4'h7 : temp[15:8] = 8'h37;
			4'h8 : temp[15:8] = 8'h38;
			4'h9 : temp[15:8] = 8'h39;
			4'ha : temp[15:8] = 8'h41;
			4'hb : temp[15:8] = 8'h42;
			4'hc : temp[15:8] = 8'h43;
			4'hd : temp[15:8] = 8'h44;
			4'he : temp[15:8] = 8'h45;
			4'hf : temp[15:8] = 8'h46;
			default: ;
		endcase

		case(in[11:8])
			4'h0 : temp[23:16] = 8'h30;
			4'h1 : temp[23:16] = 8'h31;
			4'h2 : temp[23:16] = 8'h32;
			4'h3 : temp[23:16] = 8'h33;
			4'h4 : temp[23:16] = 8'h34;
			4'h5 : temp[23:16] = 8'h35;
			4'h6 : temp[23:16] = 8'h36;
			4'h7 : temp[23:16] = 8'h37;
			4'h8 : temp[23:16] = 8'h38;
			4'h9 : temp[23:16] = 8'h39;
			4'ha : temp[23:16] = 8'h41;
			4'hb : temp[23:16] = 8'h42;
			4'hc : temp[23:16] = 8'h43;
			4'hd : temp[23:16] = 8'h44;
			4'he : temp[23:16] = 8'h45;
			4'hf : temp[23:16] = 8'h46;
			default: ;
		endcase

		case(in[15:11])
			4'h0 : temp[31:24] = 8'h30;
			4'h1 : temp[31:24] = 8'h31;
			4'h2 : temp[31:24] = 8'h32;
			4'h3 : temp[31:24] = 8'h33;
			4'h4 : temp[31:24] = 8'h34;
			4'h5 : temp[31:24] = 8'h35;
			4'h6 : temp[31:24] = 8'h36;
			4'h7 : temp[31:24] = 8'h37;
			4'h8 : temp[31:24] = 8'h38;
			4'h9 : temp[31:24] = 8'h39;
			4'ha : temp[31:24] = 8'h41;
			4'hb : temp[31:24] = 8'h42;
			4'hc : temp[31:24] = 8'h43;
			4'hd : temp[31:24] = 8'h44;
			4'he : temp[31:24] = 8'h45;
			4'hf : temp[31:24] = 8'h46;
			default: ;
		endcase

	end

	assign out_th = temp[31:24];
	assign out_hu = temp[23:16];
	assign out_te = temp[15:08];
	assign out_on = temp[07:00];

endmodule
module hex_converter(input [15:0] in,
							output logic [7:0] out_th, out_hu, out_te, out_on
							);


	logic [31:00] temp;
	always_comb
	begin
		temp = 32'h0;
		case(in[3:0])
			4'h0 : temp[7:0] = 8'h30;
			4'h1 : temp[7:0] = 8'h31;
			4'h2 : temp[7:0] = 8'h32;
			4'h3 : temp[7:0] = 8'h33;
			4'h4 : temp[7:0] = 8'h34;
			4'h5 : temp[7:0] = 8'h35;
			4'h6 : temp[7:0] = 8'h36;
			4'h7 : temp[7:0] = 8'h37;
			4'h8 : temp[7:0] = 8'h38;
			4'h9 : temp[7:0] = 8'h39;
			4'ha : temp[7:0] = 8'h41;
			4'hb : temp[7:0] = 8'h42;
			4'hc : temp[7:0] = 8'h43;
			4'hd : temp[7:0] = 8'h44;
			4'he : temp[7:0] = 8'h45;
			4'hf : temp[7:0] = 8'h46;
			default: ;
		endcase

		case(in[7:4])
			4'h0 : temp[15:8] = 8'h30;
			4'h1 : temp[15:8] = 8'h31;
			4'h2 : temp[15:8] = 8'h32;
			4'h3 : temp[15:8] = 8'h33;
			4'h4 : temp[15:8] = 8'h34;
			4'h5 : temp[15:8] = 8'h35;
			4'h6 : temp[15:8] = 8'h36;
			4'h7 : temp[15:8] = 8'h37;
			4'h8 : temp[15:8] = 8'h38;
			4'h9 : temp[15:8] = 8'h39;
			4'ha : temp[15:8] = 8'h41;
			4'hb : temp[15:8] = 8'h42;
			4'hc : temp[15:8] = 8'h43;
			4'hd : temp[15:8] = 8'h44;
			4'he : temp[15:8] = 8'h45;
			4'hf : temp[15:8] = 8'h46;
			default: ;
		endcase

		case(in[11:8])
			4'h0 : temp[23:16] = 8'h30;
			4'h1 : temp[23:16] = 8'h31;
			4'h2 : temp[23:16] = 8'h32;
			4'h3 : temp[23:16] = 8'h33;
			4'h4 : temp[23:16] = 8'h34;
			4'h5 : temp[23:16] = 8'h35;
			4'h6 : temp[23:16] = 8'h36;
			4'h7 : temp[23:16] = 8'h37;
			4'h8 : temp[23:16] = 8'h38;
			4'h9 : temp[23:16] = 8'h39;
			4'ha : temp[23:16] = 8'h41;
			4'hb : temp[23:16] = 8'h42;
			4'hc : temp[23:16] = 8'h43;
			4'hd : temp[23:16] = 8'h44;
			4'he : temp[23:16] = 8'h45;
			4'hf : temp[23:16] = 8'h46;
			default: ;
		endcase

		case(in[15:11])
			4'h0 : temp[31:24] = 8'h30;
			4'h1 : temp[31:24] = 8'h31;
			4'h2 : temp[31:24] = 8'h32;
			4'h3 : temp[31:24] = 8'h33;
			4'h4 : temp[31:24] = 8'h34;
			4'h5 : temp[31:24] = 8'h35;
			4'h6 : temp[31:24] = 8'h36;
			4'h7 : temp[31:24] = 8'h37;
			4'h8 : temp[31:24] = 8'h38;
			4'h9 : temp[31:24] = 8'h39;
			4'ha : temp[31:24] = 8'h41;
			4'hb : temp[31:24] = 8'h42;
			4'hc : temp[31:24] = 8'h43;
			4'hd : temp[31:24] = 8'h44;
			4'he : temp[31:24] = 8'h45;
			4'hf : temp[31:24] = 8'h46;
			default: ;
		endcase

	end

	assign out_th = temp[31:24];
	assign out_hu = temp[23:16];
	assign out_te = temp[15:08];
	assign out_on = temp[07:00];

endmodule