data/full_repos/permissive/449071180/tb_random_number_generator.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_random_number_generator.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_random_number_generator.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_random_number_generator.v:21: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_random_number_generator.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_random_number_generator.v:28: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_random_number_generator.v:7: Cannot find file containing module: \'random_number_generator\'\nrandom_number_generator port_map(\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/random_number_generator\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/random_number_generator.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/random_number_generator.sv\n             random_number_generator\n             random_number_generator.v\n             random_number_generator.sv\n             obj_dir/random_number_generator\n             obj_dir/random_number_generator.v\n             obj_dir/random_number_generator.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_random_number_generator();

reg clk_test,reset_test;

wire[2:0] y_output_test,x_output_test;

random_number_generator port_map(
.clk(clk_test),
.reset(reset_test),
.y_output(y_output_test),
.x_output(x_output_test)
);

initial begin
clk_test = 0;
reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;
end

always begin
clk_test = 1;
#5;
clk_test = 0;
#5;
$display("%b",y_output_test);
$display("%b",x_output_test);
end

endmodule
module tb_random_number_generator();


reg clk_test,reset_test;

wire[2:0] y_output_test,x_output_test;

random_number_generator port_map(
.clk(clk_test),
.reset(reset_test),
.y_output(y_output_test),
.x_output(x_output_test)
);

initial begin
clk_test = 0;
reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;
end

always begin
clk_test = 1;
#5;
clk_test = 0;
#5;
$display("%b",y_output_test);
$display("%b",x_output_test);
end

endmodule