data/full_repos/permissive/507312280/rtl/core/core.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/core/core.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:17: Define or directive not defined: \'`MemAddrBus\'\n    output wire [`MemAddrBus]   core_axi_awaddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output wire [`MemAddrBus]   core_axi_awaddr , \n                            ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 core_axi_awvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 core_axi_awready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemBus]       core_axi_wdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:22: Define or directive not defined: \'`MemBus\'\n    output wire [`MemBus]       core_axi_wdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 core_axi_wvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 core_axi_wready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [1:0]           core_axi_bresp  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 core_axi_bvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 core_axi_bready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemAddrBus]   core_axi_araddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:31: Define or directive not defined: \'`MemAddrBus\'\n    output wire [`MemAddrBus]   core_axi_araddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 core_axi_arvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 core_axi_arready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemBus]       core_axi_rdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:36: Define or directive not defined: \'`MemBus\'\n    input  wire [`MemBus]       core_axi_rdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 core_axi_rvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 core_axi_rready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemAddrBus]   iram_axi_awaddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:42: Define or directive not defined: \'`MemAddrBus\'\n    input  wire [`MemAddrBus]   iram_axi_awaddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 iram_axi_awvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 iram_axi_awready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:46: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemBus]       iram_axi_wdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:46: Define or directive not defined: \'`MemBus\'\n    input  wire [`MemBus]       iram_axi_wdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 iram_axi_wvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 iram_axi_wready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:50: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [1:0]           iram_axi_bresp  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:51: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 iram_axi_bvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:52: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 iram_axi_bready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:53: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemAddrBus]   iram_axi_araddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:53: Define or directive not defined: \'`MemAddrBus\'\n    input  wire [`MemAddrBus]   iram_axi_araddr , \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 iram_axi_arvalid, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:56: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 iram_axi_arready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:57: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemBus]       iram_axi_rdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:57: Define or directive not defined: \'`MemBus\'\n    output wire [`MemBus]       iram_axi_rdata  , \n                 ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:59: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 iram_axi_rvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:60: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                 iram_axi_rready  \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:64: Define or directive not defined: \'`MemBus\'\nwire [`MemBus] mem_wdata; \n      ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`MemBus] mem_wdata; \n             ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:65: Define or directive not defined: \'`MemBus\'\nwire [`MemBus] mem_rdata; \n      ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`MemBus] mem_rdata; \n             ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:66: Define or directive not defined: \'`MemAddrBus\'\nwire [`MemAddrBus] mem_addr; \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`MemAddrBus] mem_addr; \n                 ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:69: Define or directive not defined: \'`RegAddrBus\'\nwire [`RegAddrBus] reg_raddr1; \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegAddrBus] reg_raddr1; \n                 ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:70: Define or directive not defined: \'`RegAddrBus\'\nwire [`RegAddrBus] reg_raddr2; \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegAddrBus] reg_raddr2; \n                 ^\n%Error: data/full_repos/permissive/507312280/rtl/core/core.v:71: Define or directive not defined: \'`RegBus\'\nwire [`RegBus] reg_rdata1; \n      ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module core (
    input  wire clk,
    input  wire rst_n,


    input  wire halt_req_i,

    output wire soft_rst,


    input  wire core_ex_trap_valid,
    output wire core_ex_trap_ready,



    output wire [`MemAddrBus]   core_axi_awaddr ,
    output wire [2:0]           core_axi_awprot ,
    output wire                 core_axi_awvalid,
    input  wire                 core_axi_awready,

    output wire [`MemBus]       core_axi_wdata  ,
    output wire [3:0]           core_axi_wstrb  ,
    output wire                 core_axi_wvalid ,
    input  wire                 core_axi_wready ,

    input  wire [1:0]           core_axi_bresp  ,
    input  wire                 core_axi_bvalid ,
    output wire                 core_axi_bready ,

    output wire [`MemAddrBus]   core_axi_araddr ,
    output wire [2:0]           core_axi_arprot ,
    output wire                 core_axi_arvalid,
    input  wire                 core_axi_arready,

    input  wire [`MemBus]       core_axi_rdata  ,
    input  wire [1:0]           core_axi_rresp  ,
    input  wire                 core_axi_rvalid ,
    output wire                 core_axi_rready ,


    input  wire [`MemAddrBus]   iram_axi_awaddr ,
    input  wire [2:0]           iram_axi_awprot ,
    input  wire                 iram_axi_awvalid,
    output wire                 iram_axi_awready,
    input  wire [`MemBus]       iram_axi_wdata  ,
    input  wire [3:0]           iram_axi_wstrb  ,
    input  wire                 iram_axi_wvalid ,
    output wire                 iram_axi_wready ,
    output wire [1:0]           iram_axi_bresp  ,
    output wire                 iram_axi_bvalid ,
    input  wire                 iram_axi_bready ,
    input  wire [`MemAddrBus]   iram_axi_araddr ,
    input  wire [2:0]           iram_axi_arprot ,
    input  wire                 iram_axi_arvalid,
    output wire                 iram_axi_arready,
    output wire [`MemBus]       iram_axi_rdata  ,
    output wire [1:0]           iram_axi_rresp  ,
    output wire                 iram_axi_rvalid ,
    input  wire                 iram_axi_rready
);


wire [`MemBus] mem_wdata;
wire [`MemBus] mem_rdata;
wire [`MemAddrBus] mem_addr;
wire [3:0] mem_wem;

wire [`RegAddrBus] reg_raddr1;
wire [`RegAddrBus] reg_raddr2;
wire [`RegBus] reg_rdata1;
wire [`RegBus] reg_rdata2;
wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;
wire [`InstAddrBus] idex_pc_n;
wire [`InstAddrBus] trap_pc_n;
wire [`InstAddrBus] pc;
wire [`InstBus] inst;
wire [`CsrAddrBus] idex_csr_addr;
wire [`RegBus] idex_csr_wdata;
wire [`RegBus] idex_csr_rdata;
wire [`CsrAddrBus] trap_csr_addr;
wire [`RegBus] trap_csr_wdata;
wire [`RegBus] trap_csr_rdata;
wire [`RegBus] div_dividend;
wire [`RegBus] div_divisor;
wire [2:0] div_op;
wire [`RegBus] div_result;
wire [`InstAddrBus] mepc;

sctr inst_sctr
(
    .clk              (clk),
    .rst_n            (rst_n),
    .reg_we_i         (reg_we_idex),
    .csr_we_i         (csr_we_idex),
    .mem_wdata_i      (mem_wdata),
    .mem_addr_i       (mem_addr),
    .mem_we_i         (mem_we),
    .mem_wem_i        (mem_wem),
    .mem_en_i         (mem_en),
    .mem_rdata_o      (mem_rdata),
    .reg_we_o         (reg_we_sctr),
    .csr_we_o         (csr_we_sctr),
    .iram_rd_o        (iram_rd),
    .div_start_i      (div_start),
    .div_ready_i      (div_ready),
    .mult_inst_i      (mult_inst),
    .iram_rstn_i      (iram_rstn),
    .halt_req_i       (halt_req_i),
    .trap_in_i        (trap_in),
    .trap_jump_i      (trap_jump),
    .idex_mret_i      (idex_mret),
    .trap_stat_o      (),
    .sctr_axi_awaddr  (core_axi_awaddr ),
    .sctr_axi_awprot  (core_axi_awprot ),
    .sctr_axi_awvalid (core_axi_awvalid),
    .sctr_axi_awready (core_axi_awready),
    .sctr_axi_wdata   (core_axi_wdata  ),
    .sctr_axi_wstrb   (core_axi_wstrb  ),
    .sctr_axi_wvalid  (core_axi_wvalid ),
    .sctr_axi_wready  (core_axi_wready ),
    .sctr_axi_bresp   (core_axi_bresp  ),
    .sctr_axi_bvalid  (core_axi_bvalid ),
    .sctr_axi_bready  (core_axi_bready ),
    .sctr_axi_araddr  (core_axi_araddr ),
    .sctr_axi_arprot  (core_axi_arprot ),
    .sctr_axi_arvalid (core_axi_arvalid),
    .sctr_axi_arready (core_axi_arready),
    .sctr_axi_rdata   (core_axi_rdata  ),
    .sctr_axi_rresp   (core_axi_rresp  ),
    .sctr_axi_rvalid  (core_axi_rvalid ),
    .sctr_axi_rready  (core_axi_rready ),
    .hx_valid         (hx_valid)
);

regs inst_regs
(
    .clk         (clk),
    .rst_n       (rst_n),
    .raddr1_i    (reg_raddr1),
    .raddr2_i    (reg_raddr2),
    .rdata1_o    (reg_rdata1),
    .rdata2_o    (reg_rdata2),
    .we_i        (reg_we_sctr),
    .waddr_i     (reg_waddr),
    .wdata_i     (reg_wdata),
    .bus_raddr_i (5'b0),
    .bus_data_o  ()
);

iram inst_iram
(
    .clk              (clk),
    .rst_n            (rst_n),
    .pc_n_i           (trap_pc_n),
    .iram_rd_i        (iram_rd),
    .pc_o             (pc),
    .inst_o           (inst),
    .iram_rstn_o      (iram_rstn),
    .insts_sel_i      (insts_sel),
    .iram_axi_awaddr  (iram_axi_awaddr ),
    .iram_axi_awprot  (iram_axi_awprot ),
    .iram_axi_awvalid (iram_axi_awvalid),
    .iram_axi_awready (iram_axi_awready),
    .iram_axi_wdata   (iram_axi_wdata  ),
    .iram_axi_wstrb   (iram_axi_wstrb  ),
    .iram_axi_wvalid  (iram_axi_wvalid ),
    .iram_axi_wready  (iram_axi_wready ),
    .iram_axi_bresp   (iram_axi_bresp  ),
    .iram_axi_bvalid  (iram_axi_bvalid ),
    .iram_axi_bready  (iram_axi_bready ),
    .iram_axi_araddr  (iram_axi_araddr ),
    .iram_axi_arprot  (iram_axi_arprot ),
    .iram_axi_arvalid (iram_axi_arvalid),
    .iram_axi_arready (iram_axi_arready),
    .iram_axi_rdata   (iram_axi_rdata  ),
    .iram_axi_rresp   (iram_axi_rresp  ),
    .iram_axi_rvalid  (iram_axi_rvalid ),
    .iram_axi_rready  (iram_axi_rready )
);


idex inst_idex
(
    .clk          (clk),
    .inst_i       (inst),
    .pc_i         (pc),
    .reg_rdata1_i (reg_rdata1),
    .reg_rdata2_i (reg_rdata2),
    .csr_rdata_i  (idex_csr_rdata),
    .mem_rdata_i  (mem_rdata),
    .dividend_o   (div_dividend),
    .divisor_o    (div_divisor),
    .div_op_o     (div_op),
    .div_start_o  (div_start),
    .div_result_i (div_result),
    .mult_inst_o  (mult_inst),
    .reg_raddr1_o (reg_raddr1),
    .reg_raddr2_o (reg_raddr2),
    .reg_wdata_o  (reg_wdata),
    .reg_we_o     (reg_we_idex),
    .reg_waddr_o  (reg_waddr),
    .csr_wdata_o  (idex_csr_wdata),
    .csr_we_o     (csr_we_idex),
    .csr_addr_o   (idex_csr_addr),
    .mem_wdata_o  (mem_wdata),
    .mem_addr_o   (mem_addr),
    .mem_we_o     (mem_we),
    .mem_wem_o    (mem_wem),
    .mem_en_o     (mem_en),
    .pc_n_o       (idex_pc_n),
    .ecall_o      (ecall_trap),
    .ebreak_o     (ebreak_trap),
    .wfi_o        (wfi_trap),
    .inst_err_o   (inst_err_trap),
    .idex_mret_o  (idex_mret),
    .mepc         (mepc)
);


div inst_div
(
    .clk         (clk),
    .rst_n       (rst_n),
    .dividend_i  (div_dividend),
    .divisor_i   (div_divisor),
    .start_i     (div_start & (~trap_in)),
    .op_i        (div_op),
    .reg_waddr_i (5'b0),
    .result_o    (div_result),
    .ready_o     (div_ready),
    .busy_o      (),
    .reg_waddr_o ()
);

csr inst_csr
(
    .clk              (clk),
    .rst_n            (rst_n),
    .idex_csr_we_i    (csr_we_sctr),
    .idex_csr_addr_i  (idex_csr_addr),
    .idex_csr_wdata_i (idex_csr_wdata),
    .idex_csr_rdata_o (idex_csr_rdata),
    .trap_csr_we_i    (trap_csr_we),
    .trap_csr_addr_i  (trap_csr_addr),
    .trap_csr_wdata_i (trap_csr_wdata),
    .trap_csr_rdata_o (trap_csr_rdata),
    .mepc             (mepc),
    .soft_rst         (soft_rst),
    .insts_sel_o      (insts_sel),
    .ex_trap_valid_i  (core_ex_trap_valid),
    .ex_trap_valid_o  (ex_trap_valid),
    .tcmp_trap_valid_o(tcmp_trap_valid),
    .soft_trap_valid_o(soft_trap_valid),
    .mstatus_MIE3     (mstatus_MIE3),

    .hx_valid         (hx_valid)
);

trap inst_trap
(
    .clk                (clk),
    .rst_n              (rst_n),
    .csr_rdata_i        (trap_csr_rdata),
    .csr_wdata_o        (trap_csr_wdata),
    .csr_we_o           (trap_csr_we),
    .csr_addr_o         (trap_csr_addr),
    .ex_trap_ready_o    (core_ex_trap_ready),
    .ecall_i            (ecall_trap),
    .ebreak_i           (ebreak_trap),
    .wfi_i              (wfi_trap),
    .inst_err_i         (inst_err_trap),
    .mem_err_i          (1'b0),
    .ex_trap_valid_i    (ex_trap_valid),
    .tcmp_trap_valid_i  (tcmp_trap_valid),
    .soft_trap_valid_i  (soft_trap_valid),
    .mstatus_MIE3       (mstatus_MIE3),
    .pc_i               (pc),
    .inst_i             (inst),
    .mem_addr_i         (mem_addr),
    .pc_n_i             (idex_pc_n),
    .pc_n_o             (trap_pc_n),
    .trap_jump_o        (trap_jump),
    .trap_in_o          (trap_in)
);

endmodule
module core (
    input  wire clk,
    input  wire rst_n,


    input  wire halt_req_i,

    output wire soft_rst,


    input  wire core_ex_trap_valid,
    output wire core_ex_trap_ready,



    output wire [`MemAddrBus]   core_axi_awaddr ,
    output wire [2:0]           core_axi_awprot ,
    output wire                 core_axi_awvalid,
    input  wire                 core_axi_awready,

    output wire [`MemBus]       core_axi_wdata  ,
    output wire [3:0]           core_axi_wstrb  ,
    output wire                 core_axi_wvalid ,
    input  wire                 core_axi_wready ,

    input  wire [1:0]           core_axi_bresp  ,
    input  wire                 core_axi_bvalid ,
    output wire                 core_axi_bready ,

    output wire [`MemAddrBus]   core_axi_araddr ,
    output wire [2:0]           core_axi_arprot ,
    output wire                 core_axi_arvalid,
    input  wire                 core_axi_arready,

    input  wire [`MemBus]       core_axi_rdata  ,
    input  wire [1:0]           core_axi_rresp  ,
    input  wire                 core_axi_rvalid ,
    output wire                 core_axi_rready ,


    input  wire [`MemAddrBus]   iram_axi_awaddr ,
    input  wire [2:0]           iram_axi_awprot ,
    input  wire                 iram_axi_awvalid,
    output wire                 iram_axi_awready,
    input  wire [`MemBus]       iram_axi_wdata  ,
    input  wire [3:0]           iram_axi_wstrb  ,
    input  wire                 iram_axi_wvalid ,
    output wire                 iram_axi_wready ,
    output wire [1:0]           iram_axi_bresp  ,
    output wire                 iram_axi_bvalid ,
    input  wire                 iram_axi_bready ,
    input  wire [`MemAddrBus]   iram_axi_araddr ,
    input  wire [2:0]           iram_axi_arprot ,
    input  wire                 iram_axi_arvalid,
    output wire                 iram_axi_arready,
    output wire [`MemBus]       iram_axi_rdata  ,
    output wire [1:0]           iram_axi_rresp  ,
    output wire                 iram_axi_rvalid ,
    input  wire                 iram_axi_rready
);



wire [`MemBus] mem_wdata;
wire [`MemBus] mem_rdata;
wire [`MemAddrBus] mem_addr;
wire [3:0] mem_wem;

wire [`RegAddrBus] reg_raddr1;
wire [`RegAddrBus] reg_raddr2;
wire [`RegBus] reg_rdata1;
wire [`RegBus] reg_rdata2;
wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;
wire [`InstAddrBus] idex_pc_n;
wire [`InstAddrBus] trap_pc_n;
wire [`InstAddrBus] pc;
wire [`InstBus] inst;
wire [`CsrAddrBus] idex_csr_addr;
wire [`RegBus] idex_csr_wdata;
wire [`RegBus] idex_csr_rdata;
wire [`CsrAddrBus] trap_csr_addr;
wire [`RegBus] trap_csr_wdata;
wire [`RegBus] trap_csr_rdata;
wire [`RegBus] div_dividend;
wire [`RegBus] div_divisor;
wire [2:0] div_op;
wire [`RegBus] div_result;
wire [`InstAddrBus] mepc;

sctr inst_sctr
(
    .clk              (clk),
    .rst_n            (rst_n),
    .reg_we_i         (reg_we_idex),
    .csr_we_i         (csr_we_idex),
    .mem_wdata_i      (mem_wdata),
    .mem_addr_i       (mem_addr),
    .mem_we_i         (mem_we),
    .mem_wem_i        (mem_wem),
    .mem_en_i         (mem_en),
    .mem_rdata_o      (mem_rdata),
    .reg_we_o         (reg_we_sctr),
    .csr_we_o         (csr_we_sctr),
    .iram_rd_o        (iram_rd),
    .div_start_i      (div_start),
    .div_ready_i      (div_ready),
    .mult_inst_i      (mult_inst),
    .iram_rstn_i      (iram_rstn),
    .halt_req_i       (halt_req_i),
    .trap_in_i        (trap_in),
    .trap_jump_i      (trap_jump),
    .idex_mret_i      (idex_mret),
    .trap_stat_o      (),
    .sctr_axi_awaddr  (core_axi_awaddr ),
    .sctr_axi_awprot  (core_axi_awprot ),
    .sctr_axi_awvalid (core_axi_awvalid),
    .sctr_axi_awready (core_axi_awready),
    .sctr_axi_wdata   (core_axi_wdata  ),
    .sctr_axi_wstrb   (core_axi_wstrb  ),
    .sctr_axi_wvalid  (core_axi_wvalid ),
    .sctr_axi_wready  (core_axi_wready ),
    .sctr_axi_bresp   (core_axi_bresp  ),
    .sctr_axi_bvalid  (core_axi_bvalid ),
    .sctr_axi_bready  (core_axi_bready ),
    .sctr_axi_araddr  (core_axi_araddr ),
    .sctr_axi_arprot  (core_axi_arprot ),
    .sctr_axi_arvalid (core_axi_arvalid),
    .sctr_axi_arready (core_axi_arready),
    .sctr_axi_rdata   (core_axi_rdata  ),
    .sctr_axi_rresp   (core_axi_rresp  ),
    .sctr_axi_rvalid  (core_axi_rvalid ),
    .sctr_axi_rready  (core_axi_rready ),
    .hx_valid         (hx_valid)
);

regs inst_regs
(
    .clk         (clk),
    .rst_n       (rst_n),
    .raddr1_i    (reg_raddr1),
    .raddr2_i    (reg_raddr2),
    .rdata1_o    (reg_rdata1),
    .rdata2_o    (reg_rdata2),
    .we_i        (reg_we_sctr),
    .waddr_i     (reg_waddr),
    .wdata_i     (reg_wdata),
    .bus_raddr_i (5'b0),
    .bus_data_o  ()
);

iram inst_iram
(
    .clk              (clk),
    .rst_n            (rst_n),
    .pc_n_i           (trap_pc_n),
    .iram_rd_i        (iram_rd),
    .pc_o             (pc),
    .inst_o           (inst),
    .iram_rstn_o      (iram_rstn),
    .insts_sel_i      (insts_sel),
    .iram_axi_awaddr  (iram_axi_awaddr ),
    .iram_axi_awprot  (iram_axi_awprot ),
    .iram_axi_awvalid (iram_axi_awvalid),
    .iram_axi_awready (iram_axi_awready),
    .iram_axi_wdata   (iram_axi_wdata  ),
    .iram_axi_wstrb   (iram_axi_wstrb  ),
    .iram_axi_wvalid  (iram_axi_wvalid ),
    .iram_axi_wready  (iram_axi_wready ),
    .iram_axi_bresp   (iram_axi_bresp  ),
    .iram_axi_bvalid  (iram_axi_bvalid ),
    .iram_axi_bready  (iram_axi_bready ),
    .iram_axi_araddr  (iram_axi_araddr ),
    .iram_axi_arprot  (iram_axi_arprot ),
    .iram_axi_arvalid (iram_axi_arvalid),
    .iram_axi_arready (iram_axi_arready),
    .iram_axi_rdata   (iram_axi_rdata  ),
    .iram_axi_rresp   (iram_axi_rresp  ),
    .iram_axi_rvalid  (iram_axi_rvalid ),
    .iram_axi_rready  (iram_axi_rready )
);


idex inst_idex
(
    .clk          (clk),
    .inst_i       (inst),
    .pc_i         (pc),
    .reg_rdata1_i (reg_rdata1),
    .reg_rdata2_i (reg_rdata2),
    .csr_rdata_i  (idex_csr_rdata),
    .mem_rdata_i  (mem_rdata),
    .dividend_o   (div_dividend),
    .divisor_o    (div_divisor),
    .div_op_o     (div_op),
    .div_start_o  (div_start),
    .div_result_i (div_result),
    .mult_inst_o  (mult_inst),
    .reg_raddr1_o (reg_raddr1),
    .reg_raddr2_o (reg_raddr2),
    .reg_wdata_o  (reg_wdata),
    .reg_we_o     (reg_we_idex),
    .reg_waddr_o  (reg_waddr),
    .csr_wdata_o  (idex_csr_wdata),
    .csr_we_o     (csr_we_idex),
    .csr_addr_o   (idex_csr_addr),
    .mem_wdata_o  (mem_wdata),
    .mem_addr_o   (mem_addr),
    .mem_we_o     (mem_we),
    .mem_wem_o    (mem_wem),
    .mem_en_o     (mem_en),
    .pc_n_o       (idex_pc_n),
    .ecall_o      (ecall_trap),
    .ebreak_o     (ebreak_trap),
    .wfi_o        (wfi_trap),
    .inst_err_o   (inst_err_trap),
    .idex_mret_o  (idex_mret),
    .mepc         (mepc)
);


div inst_div
(
    .clk         (clk),
    .rst_n       (rst_n),
    .dividend_i  (div_dividend),
    .divisor_i   (div_divisor),
    .start_i     (div_start & (~trap_in)),
    .op_i        (div_op),
    .reg_waddr_i (5'b0),
    .result_o    (div_result),
    .ready_o     (div_ready),
    .busy_o      (),
    .reg_waddr_o ()
);

csr inst_csr
(
    .clk              (clk),
    .rst_n            (rst_n),
    .idex_csr_we_i    (csr_we_sctr),
    .idex_csr_addr_i  (idex_csr_addr),
    .idex_csr_wdata_i (idex_csr_wdata),
    .idex_csr_rdata_o (idex_csr_rdata),
    .trap_csr_we_i    (trap_csr_we),
    .trap_csr_addr_i  (trap_csr_addr),
    .trap_csr_wdata_i (trap_csr_wdata),
    .trap_csr_rdata_o (trap_csr_rdata),
    .mepc             (mepc),
    .soft_rst         (soft_rst),
    .insts_sel_o      (insts_sel),
    .ex_trap_valid_i  (core_ex_trap_valid),
    .ex_trap_valid_o  (ex_trap_valid),
    .tcmp_trap_valid_o(tcmp_trap_valid),
    .soft_trap_valid_o(soft_trap_valid),
    .mstatus_MIE3     (mstatus_MIE3),

    .hx_valid         (hx_valid)
);

trap inst_trap
(
    .clk                (clk),
    .rst_n              (rst_n),
    .csr_rdata_i        (trap_csr_rdata),
    .csr_wdata_o        (trap_csr_wdata),
    .csr_we_o           (trap_csr_we),
    .csr_addr_o         (trap_csr_addr),
    .ex_trap_ready_o    (core_ex_trap_ready),
    .ecall_i            (ecall_trap),
    .ebreak_i           (ebreak_trap),
    .wfi_i              (wfi_trap),
    .inst_err_i         (inst_err_trap),
    .mem_err_i          (1'b0),
    .ex_trap_valid_i    (ex_trap_valid),
    .tcmp_trap_valid_i  (tcmp_trap_valid),
    .soft_trap_valid_i  (soft_trap_valid),
    .mstatus_MIE3       (mstatus_MIE3),
    .pc_i               (pc),
    .inst_i             (inst),
    .mem_addr_i         (mem_addr),
    .pc_n_i             (idex_pc_n),
    .pc_n_o             (trap_pc_n),
    .trap_jump_o        (trap_jump),
    .trap_in_o          (trap_in)
);

endmodule