data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_04.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_04.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q1'\n                                                                                                       : ... In instance test\n  Q1 <= 42;\n  ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_04.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q2'\n                                                                                                        : ... In instance test\n  Q2 <= 42;\n  ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_04.v:14: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q2'\n                                                                                                        : ... In instance test\n  Q2 <= 23;\n  ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/opt_04.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q3'\n                                                                                                        : ... In instance test\n Q3 <= 42;\n ^~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module test(input CLK, ARST,
            output [7:0] Q1, Q2, Q3);

wire NO_CLK = 0;

always @(posedge CLK, posedge ARST)
	if (ARST)
		Q1 <= 42;

always @(posedge NO_CLK, posedge ARST)
	if (ARST)
		Q2 <= 42;
	else
		Q2 <= 23;

always @(posedge CLK)
	Q3 <= 42;

endmodule
module test(input CLK, ARST,
            output [7:0] Q1, Q2, Q3);


wire NO_CLK = 0;

always @(posedge CLK, posedge ARST)
	if (ARST)
		Q1 <= 42;

always @(posedge NO_CLK, posedge ARST)
	if (ARST)
		Q2 <= 42;
	else
		Q2 <= 23;

always @(posedge CLK)
	Q3 <= 42;

endmodule