data/full_repos/permissive/419538859/lab3/lab3_1/sim/lab3_1.v
data/verilator_xmls/d89cb592-853a-462b-ac31-75bbc05039e0.xml
module 	count_00_59_bcd(clk,reset,enable,count1,count0,carry);

input 	clk,reset,enable;
output	[3:0]count1,count0;
wire	[3:0]count1,count0;
reg		[3:0]count1reg,count0reg;
reg		carryreg;
output 	carry;

assign 	count1=count1reg;
assign	count0=count0reg;
assign	carry=carryreg;

always@ (posedge clk or posedge reset)
begin
	if(reset) 
		begin
		carryreg<=1'd0;
		count1reg<=4'd0;
		count0reg<=4'd0;
		end
	else 	
		if(enable == 1'b1)begin
				if(((count1reg==4'd5)&&(count0reg!=4'd9))|
						((count1reg!=4'd5)&&(count0reg!=4'd9)))begin
						count0reg<=count0reg+4'd1;
						carryreg<=1'd0;
						end
				else
					if((count1reg==4'd5)&&(count0reg==4'd9))begin
						count1reg<=4'd0;
						count0reg<=4'd0;
						carryreg<=1'b1;
						end
					else begin
						count0reg<=4'd0;
						count1reg<=count1reg+4'd1;
						carryreg<=1'd0;
						end
				end
		
end
endmodule
module 	count_00_59_bcd(clk,reset,enable,count1,count0,carry);


input 	clk,reset,enable;
output	[3:0]count1,count0;
wire	[3:0]count1,count0;
reg		[3:0]count1reg,count0reg;
reg		carryreg;
output 	carry;

assign 	count1=count1reg;
assign	count0=count0reg;
assign	carry=carryreg;

always@ (posedge clk or posedge reset)
begin
	if(reset) 
		begin
		carryreg<=1'd0;
		count1reg<=4'd0;
		count0reg<=4'd0;
		end
	else 	
		if(enable == 1'b1)begin
				if(((count1reg==4'd5)&&(count0reg!=4'd9))|
						((count1reg!=4'd5)&&(count0reg!=4'd9)))begin
						count0reg<=count0reg+4'd1;
						carryreg<=1'd0;
						end
				else
					if((count1reg==4'd5)&&(count0reg==4'd9))begin
						count1reg<=4'd0;
						count0reg<=4'd0;
						carryreg<=1'b1;
						end
					else begin
						count0reg<=4'd0;
						count1reg<=count1reg+4'd1;
						carryreg<=1'd0;
						end
				end
		
end
endmodule