data/full_repos/permissive/41334298/tests/elementary/t1.v
data/verilator_xmls/b429c190-540f-4763-98d5-4fc58c333b8a.xml
module top (a, b, c, y);
input a, b, c;
output y;


and (y, a, b, c);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;


and (y, a, b, c);

endmodule