data/full_repos/permissive/492581806/regmod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492581806/regmod.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492581806/regmod.v:19: Unsupported or unknown PLI call: $monitor\n$monitor($time, "\\t%d\\t%d\\t%d\\t%d\\t%d\\t%d\\t%d\\t%d",store[0],store[1],store[2],store[3],store[4],store[5],store[6],store[7]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/492581806/regmod.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #0.9  store[INADDRESS] = IN;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/regmod.v:28: Unsupported: Ignoring delay on this delayed statement.\n # 0.1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/regmod.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg_file (IN, OUT1 , OUT2, INADDRESS, OUT1ADDRESS , OUT2ADDRESS , WRITE , CLK , RESET,BUSYWAIT,INSBUSYWAIT);

input [7:0] IN ;
output [7:0] OUT1,OUT2;
input  [2:0] INADDRESS,OUT1ADDRESS,OUT2ADDRESS ;
input WRITE,CLK,RESET;

reg [7:0] store [7:0] ;  
input BUSYWAIT,INSBUSYWAIT;

initial
begin
#5;
$display("\n\t\t\t---------------------------------------------------------------\n");
$display("\t\ttime\treg0\treg1\treg2\treg3\treg4\treg5\treg6\treg7\n");
$display("\n\t\t\t---------------------------------------------------------------\n");
$monitor($time, "\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",store[0],store[1],store[2],store[3],store[4],store[5],store[6],store[7]);
end


assign #2 OUT1= store[OUT1ADDRESS];
assign #2 OUT2= store[OUT2ADDRESS];

always @ (posedge  CLK )
 begin
 # 0.1
 if (WRITE && !BUSYWAIT && !INSBUSYWAIT)
 	begin
	       #0.9  store[INADDRESS] = IN;
	end
end


always @ (posedge  CLK )
 begin
if(RESET)
	begin 
	#1;
	      store[0]=    8'b00000000;
	      store[1]=    8'b00000000;
	      store[2]=    8'b00000000;
              store[3]=    8'b00000000;
	      store[4]=    8'b00000000;
	      store[5]=    8'b00000000;
	      store[6]=    8'b00000000;
	      store[7]=    8'b00000000;
	end
end
endmodule
module reg_file (IN, OUT1 , OUT2, INADDRESS, OUT1ADDRESS , OUT2ADDRESS , WRITE , CLK , RESET,BUSYWAIT,INSBUSYWAIT);


input [7:0] IN ;
output [7:0] OUT1,OUT2;
input  [2:0] INADDRESS,OUT1ADDRESS,OUT2ADDRESS ;
input WRITE,CLK,RESET;

reg [7:0] store [7:0] ;  
input BUSYWAIT,INSBUSYWAIT;

initial
begin
#5;
$display("\n\t\t\t---------------------------------------------------------------\n");
$display("\t\ttime\treg0\treg1\treg2\treg3\treg4\treg5\treg6\treg7\n");
$display("\n\t\t\t---------------------------------------------------------------\n");
$monitor($time, "\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",store[0],store[1],store[2],store[3],store[4],store[5],store[6],store[7]);
end


assign #2 OUT1= store[OUT1ADDRESS];
assign #2 OUT2= store[OUT2ADDRESS];

always @ (posedge  CLK )
 begin
 # 0.1
 if (WRITE && !BUSYWAIT && !INSBUSYWAIT)
 	begin
	       #0.9  store[INADDRESS] = IN;
	end
end


always @ (posedge  CLK )
 begin
if(RESET)
	begin 
	#1;
	      store[0]=    8'b00000000;
	      store[1]=    8'b00000000;
	      store[2]=    8'b00000000;
              store[3]=    8'b00000000;
	      store[4]=    8'b00000000;
	      store[5]=    8'b00000000;
	      store[6]=    8'b00000000;
	      store[7]=    8'b00000000;
	end
end
endmodule