data/full_repos/permissive/469586427/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/469586427/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469586427/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469586427/verilog/rtl/user_project_wrapper.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469586427/verilog/rtl/user_project_wrapper.v:73: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);




  wire  core_clock;
  wire  core_reset;
  wire  core_io_irq_uart_irq;
  wire  core_io_irq_spi_irq;
  wire  core_io_irq_m1_irq;
  wire  core_io_irq_m2_irq;
  wire  core_io_irq_m3_irq;
  wire [31:0] core_io_ibus_addr;
  wire [31:0] core_io_ibus_inst;
  wire  core_io_ibus_valid;
  wire [31:0] core_io_dbus_addr;
  wire [31:0] core_io_dbus_wdata;
  wire [31:0] core_io_dbus_rdata;
  wire  core_io_dbus_rd_en;
  wire  core_io_dbus_wr_en;
  wire [1:0] core_io_dbus_st_type;
  wire [2:0] core_io_dbus_ld_type;
  wire  core_io_dbus_valid;
  wire  wb_inter_connect_clock;
  wire  wb_inter_connect_reset;
  wire [31:0] wb_inter_connect_io_dbus_addr;
  wire [31:0] wb_inter_connect_io_dbus_wdata;
  wire [31:0] wb_inter_connect_io_dbus_rdata;
  wire  wb_inter_connect_io_dbus_rd_en;
  wire  wb_inter_connect_io_dbus_wr_en;
  wire [1:0] wb_inter_connect_io_dbus_st_type;
  wire [2:0] wb_inter_connect_io_dbus_ld_type;
  wire  wb_inter_connect_io_dbus_valid;
  wire [31:0] wb_inter_connect_io_ibus_addr;
  wire [31:0] wb_inter_connect_io_ibus_inst;
  wire  wb_inter_connect_io_ibus_valid;
  wire [8:0] wb_inter_connect_io_imem_io_addr;
  wire [31:0] wb_inter_connect_io_imem_io_rdata;
  wire [31:0] wb_inter_connect_io_imem_io_wdata;
  wire  wb_inter_connect_io_imem_io_wr_en;
  wire  wb_inter_connect_io_imem_io_cs;
  wire [3:0] wb_inter_connect_io_imem_io_st_type;
  wire [8:0] wb_inter_connect_io_dmem_io_addr;
  wire [31:0] wb_inter_connect_io_dmem_io_wdata;
  wire [31:0] wb_inter_connect_io_dmem_io_rdata;
  wire  wb_inter_connect_io_dmem_io_cs;
  wire  wb_inter_connect_io_dmem_io_wr_en;
  wire [3:0] wb_inter_connect_io_dmem_io_st_type;
  wire [15:0] wb_inter_connect_io_wbm_m2s_addr;
  wire [31:0] wb_inter_connect_io_wbm_m2s_data;
  wire  wb_inter_connect_io_wbm_m2s_we;
  wire [3:0] wb_inter_connect_io_wbm_m2s_sel;
  wire  wb_inter_connect_io_wbm_m2s_stb;
  wire  wb_inter_connect_io_uart_tx;
  wire  wb_inter_connect_io_uart_tx_en;
  wire  wb_inter_connect_io_uart_rx;
  wire  wb_inter_connect_io_uart_irq;
  wire  wb_inter_connect_io_spi_cs;
  wire  wb_inter_connect_io_spi_clk;
  wire  wb_inter_connect_io_spi_mosi;
  wire  wb_inter_connect_io_spi_miso;
  wire  wb_inter_connect_io_spi_irq;
  wire  wb_inter_connect_io_spi_cs_en;
  wire  wb_inter_connect_io_spi_clk_en;
  wire  wb_inter_connect_io_spi_mosi_en;
  wire  wb_inter_connect_io_m1_ack_i;
  wire [31:0] wb_inter_connect_io_m1_data_i;
  wire  wb_inter_connect_io_m1_addr_sel;
  wire  wb_inter_connect_io_m2_ack_i;
  wire [31:0] wb_inter_connect_io_m2_data_i;
  wire  wb_inter_connect_io_m2_addr_sel;
  wire  wb_inter_connect_io_m3_ack_i;
  wire [31:0] wb_inter_connect_io_m3_data_i;
  wire  wb_inter_connect_io_m3_addr_sel;
  wire  m1_clock;
  wire  m1_reset;
  wire [15:0] m1_io_wbs_m2s_addr;
  wire [31:0] m1_io_wbs_m2s_data;
  wire  m1_io_wbs_m2s_we;
  wire [3:0] m1_io_wbs_m2s_sel;
  wire  m1_io_wbs_m2s_stb;
  wire  m1_io_wbs_ack_o;
  wire [31:0] m1_io_wbs_data_o;
  wire  m1_io_motor_gpio_qei_ch_a;
  wire  m1_io_motor_gpio_qei_ch_b;
  wire  m1_io_motor_gpio_pwm_high;
  wire  m1_io_motor_gpio_pwm_low;
  wire  m1_io_motor_gpio_pwm_high_en;
  wire  m1_io_motor_gpio_pwm_low_en;
  wire  m1_io_ba_match;
  wire  m1_io_motor_irq;
  wire  m2_clock;
  wire  m2_reset;
  wire [15:0] m2_io_wbs_m2s_addr;
  wire [31:0] m2_io_wbs_m2s_data;
  wire  m2_io_wbs_m2s_we;
  wire [3:0] m2_io_wbs_m2s_sel;
  wire  m2_io_wbs_m2s_stb;
  wire  m2_io_wbs_ack_o;
  wire [31:0] m2_io_wbs_data_o;
  wire  m2_io_motor_gpio_qei_ch_a;
  wire  m2_io_motor_gpio_qei_ch_b;
  wire  m2_io_motor_gpio_pwm_high;
  wire  m2_io_motor_gpio_pwm_low;
  wire  m2_io_motor_gpio_pwm_high_en;
  wire  m2_io_motor_gpio_pwm_low_en;
  wire  m2_io_ba_match;
  wire  m2_io_motor_irq;
  wire  m3_clock;
  wire  m3_reset;
  wire [15:0] m3_io_wbs_m2s_addr;
  wire [31:0] m3_io_wbs_m2s_data;
  wire  m3_io_wbs_m2s_we;
  wire [3:0] m3_io_wbs_m2s_sel;
  wire  m3_io_wbs_m2s_stb;
  wire  m3_io_wbs_ack_o;
  wire [31:0] m3_io_wbs_data_o;
  wire  m3_io_motor_gpio_qei_ch_a;
  wire  m3_io_motor_gpio_qei_ch_b;
  wire  m3_io_motor_gpio_pwm_high;
  wire  m3_io_motor_gpio_pwm_low;
  wire  m3_io_motor_gpio_pwm_high_en;
  wire  m3_io_motor_gpio_pwm_low_en;
  wire  m3_io_ba_match;
  wire  m3_io_motor_irq;
  wire  imem_clock;
  wire [8:0] imem_io_addr;
  wire [31:0] imem_io_rdata;
  wire [31:0] imem_io_wdata;
  wire  imem_io_cs;
  wire  imem_io_wr_en;
  wire [3:0] imem_io_st_type;
  wire  dmem_clock;
  wire [8:0] dmem_io_addr;
  wire [31:0] dmem_io_wdata;
  wire [31:0] dmem_io_rdata;
  wire  dmem_io_cs;
  wire  dmem_io_wr_en;
  wire [3:0] dmem_io_st_type;
  Core core (
    .clock(core_clock),
    .reset(core_reset),
    .io_irq_uart_irq(core_io_irq_uart_irq),
    .io_irq_spi_irq(core_io_irq_spi_irq),
    .io_irq_m1_irq(core_io_irq_m1_irq),
    .io_irq_m2_irq(core_io_irq_m2_irq),
    .io_irq_m3_irq(core_io_irq_m3_irq),
    .io_ibus_addr(core_io_ibus_addr),
    .io_ibus_inst(core_io_ibus_inst),
    .io_ibus_valid(core_io_ibus_valid),
    .io_dbus_addr(core_io_dbus_addr),
    .io_dbus_wdata(core_io_dbus_wdata),
    .io_dbus_rdata(core_io_dbus_rdata),
    .io_dbus_rd_en(core_io_dbus_rd_en),
    .io_dbus_wr_en(core_io_dbus_wr_en),
    .io_dbus_st_type(core_io_dbus_st_type),
    .io_dbus_ld_type(core_io_dbus_ld_type),
    .io_dbus_valid(core_io_dbus_valid)
  );
  WB_InterConnect wb_inter_connect (
    .clock(wb_inter_connect_clock),
    .reset(wb_inter_connect_reset),
    .io_dbus_addr(wb_inter_connect_io_dbus_addr),
    .io_dbus_wdata(wb_inter_connect_io_dbus_wdata),
    .io_dbus_rdata(wb_inter_connect_io_dbus_rdata),
    .io_dbus_rd_en(wb_inter_connect_io_dbus_rd_en),
    .io_dbus_wr_en(wb_inter_connect_io_dbus_wr_en),
    .io_dbus_st_type(wb_inter_connect_io_dbus_st_type),
    .io_dbus_ld_type(wb_inter_connect_io_dbus_ld_type),
    .io_dbus_valid(wb_inter_connect_io_dbus_valid),
    .io_ibus_addr(wb_inter_connect_io_ibus_addr),
    .io_ibus_inst(wb_inter_connect_io_ibus_inst),
    .io_ibus_valid(wb_inter_connect_io_ibus_valid),
    .io_imem_io_addr(wb_inter_connect_io_imem_io_addr),
    .io_imem_io_rdata(wb_inter_connect_io_imem_io_rdata),
    .io_imem_io_wdata(wb_inter_connect_io_imem_io_wdata),
    .io_imem_io_wr_en(wb_inter_connect_io_imem_io_wr_en),
    .io_imem_io_cs(wb_inter_connect_io_imem_io_cs),
    .io_imem_io_st_type(wb_inter_connect_io_imem_io_st_type),
    .io_dmem_io_addr(wb_inter_connect_io_dmem_io_addr),
    .io_dmem_io_wdata(wb_inter_connect_io_dmem_io_wdata),
    .io_dmem_io_rdata(wb_inter_connect_io_dmem_io_rdata),
    .io_dmem_io_cs(wb_inter_connect_io_dmem_io_cs),
    .io_dmem_io_wr_en(wb_inter_connect_io_dmem_io_wr_en),
    .io_dmem_io_st_type(wb_inter_connect_io_dmem_io_st_type),
    .io_wbm_m2s_addr(wb_inter_connect_io_wbm_m2s_addr),
    .io_wbm_m2s_data(wb_inter_connect_io_wbm_m2s_data),
    .io_wbm_m2s_we(wb_inter_connect_io_wbm_m2s_we),
    .io_wbm_m2s_sel(wb_inter_connect_io_wbm_m2s_sel),
    .io_wbm_m2s_stb(wb_inter_connect_io_wbm_m2s_stb),
    .io_uart_tx(wb_inter_connect_io_uart_tx),
    .io_uart_tx_en(wb_inter_connect_io_uart_tx_en),
    .io_uart_rx(wb_inter_connect_io_uart_rx),
    .io_uart_irq(wb_inter_connect_io_uart_irq),
    .io_spi_cs(wb_inter_connect_io_spi_cs),
    .io_spi_clk(wb_inter_connect_io_spi_clk),
    .io_spi_mosi(wb_inter_connect_io_spi_mosi),
    .io_spi_miso(wb_inter_connect_io_spi_miso),
    .io_spi_irq(wb_inter_connect_io_spi_irq),
    .io_spi_cs_en(wb_inter_connect_io_spi_cs_en),
    .io_spi_clk_en(wb_inter_connect_io_spi_clk_en),
    .io_spi_mosi_en(wb_inter_connect_io_spi_mosi_en),
    .io_m1_ack_i(wb_inter_connect_io_m1_ack_i),
    .io_m1_data_i(wb_inter_connect_io_m1_data_i),
    .io_m1_addr_sel(wb_inter_connect_io_m1_addr_sel),
    .io_m2_ack_i(wb_inter_connect_io_m2_ack_i),
    .io_m2_data_i(wb_inter_connect_io_m2_data_i),
    .io_m2_addr_sel(wb_inter_connect_io_m2_addr_sel),
    .io_m3_ack_i(wb_inter_connect_io_m3_ack_i),
    .io_m3_data_i(wb_inter_connect_io_m3_data_i),
    .io_m3_addr_sel(wb_inter_connect_io_m3_addr_sel)
  );
  Motor_Top m1 (
    .clock(m1_clock),
    .reset(m1_reset),
    .io_wbs_m2s_addr(m1_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m1_io_wbs_m2s_data),
    .io_wbs_m2s_we(m1_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m1_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m1_io_wbs_m2s_stb),
    .io_wbs_ack_o(m1_io_wbs_ack_o),
    .io_wbs_data_o(m1_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m1_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m1_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m1_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m1_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m1_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m1_io_motor_gpio_pwm_low_en),
    .io_ba_match(m1_io_ba_match),
    .io_motor_irq(m1_io_motor_irq)
  );
  Motor_Top m2 (
    .clock(m2_clock),
    .reset(m2_reset),
    .io_wbs_m2s_addr(m2_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m2_io_wbs_m2s_data),
    .io_wbs_m2s_we(m2_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m2_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m2_io_wbs_m2s_stb),
    .io_wbs_ack_o(m2_io_wbs_ack_o),
    .io_wbs_data_o(m2_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m2_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m2_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m2_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m2_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m2_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m2_io_motor_gpio_pwm_low_en),
    .io_ba_match(m2_io_ba_match),
    .io_motor_irq(m2_io_motor_irq)
  );
  Motor_Top m3 (
    .clock(m3_clock),
    .reset(m3_reset),
    .io_wbs_m2s_addr(m3_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m3_io_wbs_m2s_data),
    .io_wbs_m2s_we(m3_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m3_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m3_io_wbs_m2s_stb),
    .io_wbs_ack_o(m3_io_wbs_ack_o),
    .io_wbs_data_o(m3_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m3_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m3_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m3_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m3_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m3_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m3_io_motor_gpio_pwm_low_en),
    .io_ba_match(m3_io_ba_match),
    .io_motor_irq(m3_io_motor_irq)
  );
  sky130_sram_2kbyte_1rw1r_32x512_8 dmem (
  `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
  `endif

  .clk0(dmem_clock),
  .csb0(dmem_io_cs),
  .web0(dmem_io_wr_en),
  .wmask0(dmem_io_st_type),
  .addr0(dmem_io_addr),
  .din0(dmem_io_wdata),
  .dout0(dmem_io_rdata)
  ); 

  sky130_sram_2kbyte_1rw1r_32x512_8 imem (
  `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
  `endif

  .clk0(imem_clock),
  .csb0(imem_io_cs),
  .web0(imem_io_wr_en),
  .wmask0(dmem_io_st_type),
  .addr0(imem_io_addr),
  .din0(imem_io_wdata),
  .dout0(imem_io_rdata)
  ); 
  assign io_uart_tx = wb_inter_connect_io_uart_tx;
  assign io_uart_tx_en = wb_inter_connect_io_uart_tx_en;
  assign io_spi_cs = wb_inter_connect_io_spi_cs;
  assign io_spi_clk = wb_inter_connect_io_spi_clk;
  assign io_spi_mosi = wb_inter_connect_io_spi_mosi;
  assign io_spi_cs_en = wb_inter_connect_io_spi_cs_en;
  assign io_spi_clk_en = wb_inter_connect_io_spi_clk_en;
  assign io_spi_mosi_en = wb_inter_connect_io_spi_mosi_en;
  assign io_m1_io_pwm_high = m1_io_motor_gpio_pwm_high;
  assign io_m1_io_pwm_low = m1_io_motor_gpio_pwm_low;
  assign io_m1_io_pwm_high_en = m1_io_motor_gpio_pwm_high_en;
  assign io_m1_io_pwm_low_en = m1_io_motor_gpio_pwm_low_en;
  assign io_m2_io_pwm_high = m2_io_motor_gpio_pwm_high;
  assign io_m2_io_pwm_low = m2_io_motor_gpio_pwm_low;
  assign io_m2_io_pwm_high_en = m2_io_motor_gpio_pwm_high_en;
  assign io_m2_io_pwm_low_en = m2_io_motor_gpio_pwm_low_en;
  assign io_m3_io_pwm_high = m3_io_motor_gpio_pwm_high;
  assign io_m3_io_pwm_low = m3_io_motor_gpio_pwm_low;
  assign io_m3_io_pwm_high_en = m3_io_motor_gpio_pwm_high_en;
  assign io_m3_io_pwm_low_en = m3_io_motor_gpio_pwm_low_en;
  assign core_clock = clock;
  assign core_reset = reset;
  assign core_io_irq_uart_irq = wb_inter_connect_io_uart_irq;
  assign core_io_irq_spi_irq = wb_inter_connect_io_spi_irq;
  assign core_io_irq_m1_irq = m1_io_motor_irq;
  assign core_io_irq_m2_irq = m2_io_motor_irq;
  assign core_io_irq_m3_irq = m3_io_motor_irq;
  assign core_io_ibus_inst = wb_inter_connect_io_ibus_inst;
  assign core_io_ibus_valid = wb_inter_connect_io_ibus_valid;
  assign core_io_dbus_rdata = wb_inter_connect_io_dbus_rdata;
  assign core_io_dbus_valid = wb_inter_connect_io_dbus_valid;
  assign wb_inter_connect_clock = clock;
  assign wb_inter_connect_reset = reset;
  assign wb_inter_connect_io_dbus_addr = core_io_dbus_addr;
  assign wb_inter_connect_io_dbus_wdata = core_io_dbus_wdata;
  assign wb_inter_connect_io_dbus_rd_en = core_io_dbus_rd_en;
  assign wb_inter_connect_io_dbus_wr_en = core_io_dbus_wr_en;
  assign wb_inter_connect_io_dbus_st_type = core_io_dbus_st_type;
  assign wb_inter_connect_io_dbus_ld_type = core_io_dbus_ld_type;
  assign wb_inter_connect_io_ibus_addr = core_io_ibus_addr;
  assign wb_inter_connect_io_imem_io_rdata = imem_io_rdata;
  assign wb_inter_connect_io_dmem_io_rdata = dmem_io_rdata;
  assign wb_inter_connect_io_uart_rx = io_uart_rx;
  assign wb_inter_connect_io_spi_miso = io_spi_miso;
  assign wb_inter_connect_io_m1_ack_i = m1_io_wbs_ack_o;
  assign wb_inter_connect_io_m1_data_i = m1_io_wbs_data_o;
  assign wb_inter_connect_io_m2_ack_i = m2_io_wbs_ack_o;
  assign wb_inter_connect_io_m2_data_i = m2_io_wbs_data_o;
  assign wb_inter_connect_io_m3_ack_i = m3_io_wbs_ack_o;
  assign wb_inter_connect_io_m3_data_i = m3_io_wbs_data_o;
  assign m1_clock = clock;
  assign m1_reset = reset;
  assign m1_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m1_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m1_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m1_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m1_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m1_io_motor_gpio_qei_ch_a = io_m1_io_qei_ch_a;
  assign m1_io_motor_gpio_qei_ch_b = io_m1_io_qei_ch_b;
  assign m1_io_ba_match = wb_inter_connect_io_m1_addr_sel;
  assign m2_clock = clock;
  assign m2_reset = reset;
  assign m2_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m2_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m2_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m2_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m2_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m2_io_motor_gpio_qei_ch_a = io_m2_io_qei_ch_a;
  assign m2_io_motor_gpio_qei_ch_b = io_m2_io_qei_ch_b;
  assign m2_io_ba_match = wb_inter_connect_io_m2_addr_sel;
  assign m3_clock = clock;
  assign m3_reset = reset;
  assign m3_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m3_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m3_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m3_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m3_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m3_io_motor_gpio_qei_ch_a = io_m3_io_qei_ch_a;
  assign m3_io_motor_gpio_qei_ch_b = io_m3_io_qei_ch_b;
  assign m3_io_ba_match = wb_inter_connect_io_m3_addr_sel;
  assign imem_clock = clock;
  assign imem_io_addr = wb_inter_connect_io_imem_io_addr;
  assign imem_io_wdata = wb_inter_connect_io_imem_io_wdata;
  assign imem_io_cs = wb_inter_connect_io_imem_io_cs;
  assign imem_io_wr_en = wb_inter_connect_io_imem_io_wr_en;
  assign imem_io_st_type = wb_inter_connect_io_imem_io_st_type;
  assign dmem_clock = clock;
  assign dmem_io_addr = wb_inter_connect_io_dmem_io_addr;
  assign dmem_io_wdata = wb_inter_connect_io_dmem_io_wdata;
  assign dmem_io_cs = wb_inter_connect_io_dmem_io_cs;
  assign dmem_io_wr_en = wb_inter_connect_io_dmem_io_wr_en;
  assign dmem_io_st_type = wb_inter_connect_io_dmem_io_st_type;
  
  assign  clock = wb_clk_i; 
  assign  reset = wb_rst_i;
  assign  io_out[0] =  io_uart_tx;
  assign  io_oeb[0] =  io_uart_txen;
  assign  io_uart_rx = io_in[0];
  assign  io_out[1] = io_spi_cs; 
  assign  io_out[2] = io_spi_clk;
  assign  io_out[3] = io_spi_mosi;
  assign  io_oeb[1] = io_spi_cs_en; 
  assign  io_oeb[2] = io_spi_clk_en;
  assign  io_oeb[3] = io_spi_mosi_en;
  assign  io_spi_miso = io_in[1];

  assign   io_m1_io_qei_ch_a = io_in[2];
  assign   io_m1_io_qei_ch_b = io_in[3];
  assign   io_out[4] = io_m1_io_pwm_high;
  assign   io_out[5] = io_m1_io_pwm_low;
  assign   io_oeb[4] = io_m1_io_pwm_high_en;
  assign   io_oeb[5] = io_m1_io_pwm_low_en;

  assign   io_m2_io_qei_ch_a = io_in[4];
  assign   io_m2_io_qei_ch_b = io_in[5];
  assign   io_out[6] = io_m2_io_pwm_high;
  assign   io_out[7] = io_m2_io_pwm_low;
  assign   io_oeb[6] = io_m2_io_pwm_high_en;
  assign   io_oeb[7] = io_m2_io_pwm_low_en;

  assign   io_m3_io_qei_ch_a = io_in[6];
  assign   io_m3_io_qei_ch_b = io_in[7];
  assign   io_out[8] = io_m3_io_pwm_high;
  assign   io_out[9] = io_m3_io_pwm_low;
  assign   io_oeb[8] = io_m3_io_pwm_high_en;
  assign   io_oeb[9] = io_m3_io_pwm_low_en;
endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





  wire  core_clock;
  wire  core_reset;
  wire  core_io_irq_uart_irq;
  wire  core_io_irq_spi_irq;
  wire  core_io_irq_m1_irq;
  wire  core_io_irq_m2_irq;
  wire  core_io_irq_m3_irq;
  wire [31:0] core_io_ibus_addr;
  wire [31:0] core_io_ibus_inst;
  wire  core_io_ibus_valid;
  wire [31:0] core_io_dbus_addr;
  wire [31:0] core_io_dbus_wdata;
  wire [31:0] core_io_dbus_rdata;
  wire  core_io_dbus_rd_en;
  wire  core_io_dbus_wr_en;
  wire [1:0] core_io_dbus_st_type;
  wire [2:0] core_io_dbus_ld_type;
  wire  core_io_dbus_valid;
  wire  wb_inter_connect_clock;
  wire  wb_inter_connect_reset;
  wire [31:0] wb_inter_connect_io_dbus_addr;
  wire [31:0] wb_inter_connect_io_dbus_wdata;
  wire [31:0] wb_inter_connect_io_dbus_rdata;
  wire  wb_inter_connect_io_dbus_rd_en;
  wire  wb_inter_connect_io_dbus_wr_en;
  wire [1:0] wb_inter_connect_io_dbus_st_type;
  wire [2:0] wb_inter_connect_io_dbus_ld_type;
  wire  wb_inter_connect_io_dbus_valid;
  wire [31:0] wb_inter_connect_io_ibus_addr;
  wire [31:0] wb_inter_connect_io_ibus_inst;
  wire  wb_inter_connect_io_ibus_valid;
  wire [8:0] wb_inter_connect_io_imem_io_addr;
  wire [31:0] wb_inter_connect_io_imem_io_rdata;
  wire [31:0] wb_inter_connect_io_imem_io_wdata;
  wire  wb_inter_connect_io_imem_io_wr_en;
  wire  wb_inter_connect_io_imem_io_cs;
  wire [3:0] wb_inter_connect_io_imem_io_st_type;
  wire [8:0] wb_inter_connect_io_dmem_io_addr;
  wire [31:0] wb_inter_connect_io_dmem_io_wdata;
  wire [31:0] wb_inter_connect_io_dmem_io_rdata;
  wire  wb_inter_connect_io_dmem_io_cs;
  wire  wb_inter_connect_io_dmem_io_wr_en;
  wire [3:0] wb_inter_connect_io_dmem_io_st_type;
  wire [15:0] wb_inter_connect_io_wbm_m2s_addr;
  wire [31:0] wb_inter_connect_io_wbm_m2s_data;
  wire  wb_inter_connect_io_wbm_m2s_we;
  wire [3:0] wb_inter_connect_io_wbm_m2s_sel;
  wire  wb_inter_connect_io_wbm_m2s_stb;
  wire  wb_inter_connect_io_uart_tx;
  wire  wb_inter_connect_io_uart_tx_en;
  wire  wb_inter_connect_io_uart_rx;
  wire  wb_inter_connect_io_uart_irq;
  wire  wb_inter_connect_io_spi_cs;
  wire  wb_inter_connect_io_spi_clk;
  wire  wb_inter_connect_io_spi_mosi;
  wire  wb_inter_connect_io_spi_miso;
  wire  wb_inter_connect_io_spi_irq;
  wire  wb_inter_connect_io_spi_cs_en;
  wire  wb_inter_connect_io_spi_clk_en;
  wire  wb_inter_connect_io_spi_mosi_en;
  wire  wb_inter_connect_io_m1_ack_i;
  wire [31:0] wb_inter_connect_io_m1_data_i;
  wire  wb_inter_connect_io_m1_addr_sel;
  wire  wb_inter_connect_io_m2_ack_i;
  wire [31:0] wb_inter_connect_io_m2_data_i;
  wire  wb_inter_connect_io_m2_addr_sel;
  wire  wb_inter_connect_io_m3_ack_i;
  wire [31:0] wb_inter_connect_io_m3_data_i;
  wire  wb_inter_connect_io_m3_addr_sel;
  wire  m1_clock;
  wire  m1_reset;
  wire [15:0] m1_io_wbs_m2s_addr;
  wire [31:0] m1_io_wbs_m2s_data;
  wire  m1_io_wbs_m2s_we;
  wire [3:0] m1_io_wbs_m2s_sel;
  wire  m1_io_wbs_m2s_stb;
  wire  m1_io_wbs_ack_o;
  wire [31:0] m1_io_wbs_data_o;
  wire  m1_io_motor_gpio_qei_ch_a;
  wire  m1_io_motor_gpio_qei_ch_b;
  wire  m1_io_motor_gpio_pwm_high;
  wire  m1_io_motor_gpio_pwm_low;
  wire  m1_io_motor_gpio_pwm_high_en;
  wire  m1_io_motor_gpio_pwm_low_en;
  wire  m1_io_ba_match;
  wire  m1_io_motor_irq;
  wire  m2_clock;
  wire  m2_reset;
  wire [15:0] m2_io_wbs_m2s_addr;
  wire [31:0] m2_io_wbs_m2s_data;
  wire  m2_io_wbs_m2s_we;
  wire [3:0] m2_io_wbs_m2s_sel;
  wire  m2_io_wbs_m2s_stb;
  wire  m2_io_wbs_ack_o;
  wire [31:0] m2_io_wbs_data_o;
  wire  m2_io_motor_gpio_qei_ch_a;
  wire  m2_io_motor_gpio_qei_ch_b;
  wire  m2_io_motor_gpio_pwm_high;
  wire  m2_io_motor_gpio_pwm_low;
  wire  m2_io_motor_gpio_pwm_high_en;
  wire  m2_io_motor_gpio_pwm_low_en;
  wire  m2_io_ba_match;
  wire  m2_io_motor_irq;
  wire  m3_clock;
  wire  m3_reset;
  wire [15:0] m3_io_wbs_m2s_addr;
  wire [31:0] m3_io_wbs_m2s_data;
  wire  m3_io_wbs_m2s_we;
  wire [3:0] m3_io_wbs_m2s_sel;
  wire  m3_io_wbs_m2s_stb;
  wire  m3_io_wbs_ack_o;
  wire [31:0] m3_io_wbs_data_o;
  wire  m3_io_motor_gpio_qei_ch_a;
  wire  m3_io_motor_gpio_qei_ch_b;
  wire  m3_io_motor_gpio_pwm_high;
  wire  m3_io_motor_gpio_pwm_low;
  wire  m3_io_motor_gpio_pwm_high_en;
  wire  m3_io_motor_gpio_pwm_low_en;
  wire  m3_io_ba_match;
  wire  m3_io_motor_irq;
  wire  imem_clock;
  wire [8:0] imem_io_addr;
  wire [31:0] imem_io_rdata;
  wire [31:0] imem_io_wdata;
  wire  imem_io_cs;
  wire  imem_io_wr_en;
  wire [3:0] imem_io_st_type;
  wire  dmem_clock;
  wire [8:0] dmem_io_addr;
  wire [31:0] dmem_io_wdata;
  wire [31:0] dmem_io_rdata;
  wire  dmem_io_cs;
  wire  dmem_io_wr_en;
  wire [3:0] dmem_io_st_type;
  Core core (
    .clock(core_clock),
    .reset(core_reset),
    .io_irq_uart_irq(core_io_irq_uart_irq),
    .io_irq_spi_irq(core_io_irq_spi_irq),
    .io_irq_m1_irq(core_io_irq_m1_irq),
    .io_irq_m2_irq(core_io_irq_m2_irq),
    .io_irq_m3_irq(core_io_irq_m3_irq),
    .io_ibus_addr(core_io_ibus_addr),
    .io_ibus_inst(core_io_ibus_inst),
    .io_ibus_valid(core_io_ibus_valid),
    .io_dbus_addr(core_io_dbus_addr),
    .io_dbus_wdata(core_io_dbus_wdata),
    .io_dbus_rdata(core_io_dbus_rdata),
    .io_dbus_rd_en(core_io_dbus_rd_en),
    .io_dbus_wr_en(core_io_dbus_wr_en),
    .io_dbus_st_type(core_io_dbus_st_type),
    .io_dbus_ld_type(core_io_dbus_ld_type),
    .io_dbus_valid(core_io_dbus_valid)
  );
  WB_InterConnect wb_inter_connect (
    .clock(wb_inter_connect_clock),
    .reset(wb_inter_connect_reset),
    .io_dbus_addr(wb_inter_connect_io_dbus_addr),
    .io_dbus_wdata(wb_inter_connect_io_dbus_wdata),
    .io_dbus_rdata(wb_inter_connect_io_dbus_rdata),
    .io_dbus_rd_en(wb_inter_connect_io_dbus_rd_en),
    .io_dbus_wr_en(wb_inter_connect_io_dbus_wr_en),
    .io_dbus_st_type(wb_inter_connect_io_dbus_st_type),
    .io_dbus_ld_type(wb_inter_connect_io_dbus_ld_type),
    .io_dbus_valid(wb_inter_connect_io_dbus_valid),
    .io_ibus_addr(wb_inter_connect_io_ibus_addr),
    .io_ibus_inst(wb_inter_connect_io_ibus_inst),
    .io_ibus_valid(wb_inter_connect_io_ibus_valid),
    .io_imem_io_addr(wb_inter_connect_io_imem_io_addr),
    .io_imem_io_rdata(wb_inter_connect_io_imem_io_rdata),
    .io_imem_io_wdata(wb_inter_connect_io_imem_io_wdata),
    .io_imem_io_wr_en(wb_inter_connect_io_imem_io_wr_en),
    .io_imem_io_cs(wb_inter_connect_io_imem_io_cs),
    .io_imem_io_st_type(wb_inter_connect_io_imem_io_st_type),
    .io_dmem_io_addr(wb_inter_connect_io_dmem_io_addr),
    .io_dmem_io_wdata(wb_inter_connect_io_dmem_io_wdata),
    .io_dmem_io_rdata(wb_inter_connect_io_dmem_io_rdata),
    .io_dmem_io_cs(wb_inter_connect_io_dmem_io_cs),
    .io_dmem_io_wr_en(wb_inter_connect_io_dmem_io_wr_en),
    .io_dmem_io_st_type(wb_inter_connect_io_dmem_io_st_type),
    .io_wbm_m2s_addr(wb_inter_connect_io_wbm_m2s_addr),
    .io_wbm_m2s_data(wb_inter_connect_io_wbm_m2s_data),
    .io_wbm_m2s_we(wb_inter_connect_io_wbm_m2s_we),
    .io_wbm_m2s_sel(wb_inter_connect_io_wbm_m2s_sel),
    .io_wbm_m2s_stb(wb_inter_connect_io_wbm_m2s_stb),
    .io_uart_tx(wb_inter_connect_io_uart_tx),
    .io_uart_tx_en(wb_inter_connect_io_uart_tx_en),
    .io_uart_rx(wb_inter_connect_io_uart_rx),
    .io_uart_irq(wb_inter_connect_io_uart_irq),
    .io_spi_cs(wb_inter_connect_io_spi_cs),
    .io_spi_clk(wb_inter_connect_io_spi_clk),
    .io_spi_mosi(wb_inter_connect_io_spi_mosi),
    .io_spi_miso(wb_inter_connect_io_spi_miso),
    .io_spi_irq(wb_inter_connect_io_spi_irq),
    .io_spi_cs_en(wb_inter_connect_io_spi_cs_en),
    .io_spi_clk_en(wb_inter_connect_io_spi_clk_en),
    .io_spi_mosi_en(wb_inter_connect_io_spi_mosi_en),
    .io_m1_ack_i(wb_inter_connect_io_m1_ack_i),
    .io_m1_data_i(wb_inter_connect_io_m1_data_i),
    .io_m1_addr_sel(wb_inter_connect_io_m1_addr_sel),
    .io_m2_ack_i(wb_inter_connect_io_m2_ack_i),
    .io_m2_data_i(wb_inter_connect_io_m2_data_i),
    .io_m2_addr_sel(wb_inter_connect_io_m2_addr_sel),
    .io_m3_ack_i(wb_inter_connect_io_m3_ack_i),
    .io_m3_data_i(wb_inter_connect_io_m3_data_i),
    .io_m3_addr_sel(wb_inter_connect_io_m3_addr_sel)
  );
  Motor_Top m1 (
    .clock(m1_clock),
    .reset(m1_reset),
    .io_wbs_m2s_addr(m1_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m1_io_wbs_m2s_data),
    .io_wbs_m2s_we(m1_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m1_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m1_io_wbs_m2s_stb),
    .io_wbs_ack_o(m1_io_wbs_ack_o),
    .io_wbs_data_o(m1_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m1_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m1_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m1_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m1_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m1_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m1_io_motor_gpio_pwm_low_en),
    .io_ba_match(m1_io_ba_match),
    .io_motor_irq(m1_io_motor_irq)
  );
  Motor_Top m2 (
    .clock(m2_clock),
    .reset(m2_reset),
    .io_wbs_m2s_addr(m2_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m2_io_wbs_m2s_data),
    .io_wbs_m2s_we(m2_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m2_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m2_io_wbs_m2s_stb),
    .io_wbs_ack_o(m2_io_wbs_ack_o),
    .io_wbs_data_o(m2_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m2_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m2_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m2_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m2_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m2_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m2_io_motor_gpio_pwm_low_en),
    .io_ba_match(m2_io_ba_match),
    .io_motor_irq(m2_io_motor_irq)
  );
  Motor_Top m3 (
    .clock(m3_clock),
    .reset(m3_reset),
    .io_wbs_m2s_addr(m3_io_wbs_m2s_addr),
    .io_wbs_m2s_data(m3_io_wbs_m2s_data),
    .io_wbs_m2s_we(m3_io_wbs_m2s_we),
    .io_wbs_m2s_sel(m3_io_wbs_m2s_sel),
    .io_wbs_m2s_stb(m3_io_wbs_m2s_stb),
    .io_wbs_ack_o(m3_io_wbs_ack_o),
    .io_wbs_data_o(m3_io_wbs_data_o),
    .io_motor_gpio_qei_ch_a(m3_io_motor_gpio_qei_ch_a),
    .io_motor_gpio_qei_ch_b(m3_io_motor_gpio_qei_ch_b),
    .io_motor_gpio_pwm_high(m3_io_motor_gpio_pwm_high),
    .io_motor_gpio_pwm_low(m3_io_motor_gpio_pwm_low),
    .io_motor_gpio_pwm_high_en(m3_io_motor_gpio_pwm_high_en),
    .io_motor_gpio_pwm_low_en(m3_io_motor_gpio_pwm_low_en),
    .io_ba_match(m3_io_ba_match),
    .io_motor_irq(m3_io_motor_irq)
  );
  sky130_sram_2kbyte_1rw1r_32x512_8 dmem (
  `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
  `endif

  .clk0(dmem_clock),
  .csb0(dmem_io_cs),
  .web0(dmem_io_wr_en),
  .wmask0(dmem_io_st_type),
  .addr0(dmem_io_addr),
  .din0(dmem_io_wdata),
  .dout0(dmem_io_rdata)
  ); 

  sky130_sram_2kbyte_1rw1r_32x512_8 imem (
  `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
  `endif

  .clk0(imem_clock),
  .csb0(imem_io_cs),
  .web0(imem_io_wr_en),
  .wmask0(dmem_io_st_type),
  .addr0(imem_io_addr),
  .din0(imem_io_wdata),
  .dout0(imem_io_rdata)
  ); 
  assign io_uart_tx = wb_inter_connect_io_uart_tx;
  assign io_uart_tx_en = wb_inter_connect_io_uart_tx_en;
  assign io_spi_cs = wb_inter_connect_io_spi_cs;
  assign io_spi_clk = wb_inter_connect_io_spi_clk;
  assign io_spi_mosi = wb_inter_connect_io_spi_mosi;
  assign io_spi_cs_en = wb_inter_connect_io_spi_cs_en;
  assign io_spi_clk_en = wb_inter_connect_io_spi_clk_en;
  assign io_spi_mosi_en = wb_inter_connect_io_spi_mosi_en;
  assign io_m1_io_pwm_high = m1_io_motor_gpio_pwm_high;
  assign io_m1_io_pwm_low = m1_io_motor_gpio_pwm_low;
  assign io_m1_io_pwm_high_en = m1_io_motor_gpio_pwm_high_en;
  assign io_m1_io_pwm_low_en = m1_io_motor_gpio_pwm_low_en;
  assign io_m2_io_pwm_high = m2_io_motor_gpio_pwm_high;
  assign io_m2_io_pwm_low = m2_io_motor_gpio_pwm_low;
  assign io_m2_io_pwm_high_en = m2_io_motor_gpio_pwm_high_en;
  assign io_m2_io_pwm_low_en = m2_io_motor_gpio_pwm_low_en;
  assign io_m3_io_pwm_high = m3_io_motor_gpio_pwm_high;
  assign io_m3_io_pwm_low = m3_io_motor_gpio_pwm_low;
  assign io_m3_io_pwm_high_en = m3_io_motor_gpio_pwm_high_en;
  assign io_m3_io_pwm_low_en = m3_io_motor_gpio_pwm_low_en;
  assign core_clock = clock;
  assign core_reset = reset;
  assign core_io_irq_uart_irq = wb_inter_connect_io_uart_irq;
  assign core_io_irq_spi_irq = wb_inter_connect_io_spi_irq;
  assign core_io_irq_m1_irq = m1_io_motor_irq;
  assign core_io_irq_m2_irq = m2_io_motor_irq;
  assign core_io_irq_m3_irq = m3_io_motor_irq;
  assign core_io_ibus_inst = wb_inter_connect_io_ibus_inst;
  assign core_io_ibus_valid = wb_inter_connect_io_ibus_valid;
  assign core_io_dbus_rdata = wb_inter_connect_io_dbus_rdata;
  assign core_io_dbus_valid = wb_inter_connect_io_dbus_valid;
  assign wb_inter_connect_clock = clock;
  assign wb_inter_connect_reset = reset;
  assign wb_inter_connect_io_dbus_addr = core_io_dbus_addr;
  assign wb_inter_connect_io_dbus_wdata = core_io_dbus_wdata;
  assign wb_inter_connect_io_dbus_rd_en = core_io_dbus_rd_en;
  assign wb_inter_connect_io_dbus_wr_en = core_io_dbus_wr_en;
  assign wb_inter_connect_io_dbus_st_type = core_io_dbus_st_type;
  assign wb_inter_connect_io_dbus_ld_type = core_io_dbus_ld_type;
  assign wb_inter_connect_io_ibus_addr = core_io_ibus_addr;
  assign wb_inter_connect_io_imem_io_rdata = imem_io_rdata;
  assign wb_inter_connect_io_dmem_io_rdata = dmem_io_rdata;
  assign wb_inter_connect_io_uart_rx = io_uart_rx;
  assign wb_inter_connect_io_spi_miso = io_spi_miso;
  assign wb_inter_connect_io_m1_ack_i = m1_io_wbs_ack_o;
  assign wb_inter_connect_io_m1_data_i = m1_io_wbs_data_o;
  assign wb_inter_connect_io_m2_ack_i = m2_io_wbs_ack_o;
  assign wb_inter_connect_io_m2_data_i = m2_io_wbs_data_o;
  assign wb_inter_connect_io_m3_ack_i = m3_io_wbs_ack_o;
  assign wb_inter_connect_io_m3_data_i = m3_io_wbs_data_o;
  assign m1_clock = clock;
  assign m1_reset = reset;
  assign m1_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m1_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m1_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m1_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m1_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m1_io_motor_gpio_qei_ch_a = io_m1_io_qei_ch_a;
  assign m1_io_motor_gpio_qei_ch_b = io_m1_io_qei_ch_b;
  assign m1_io_ba_match = wb_inter_connect_io_m1_addr_sel;
  assign m2_clock = clock;
  assign m2_reset = reset;
  assign m2_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m2_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m2_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m2_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m2_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m2_io_motor_gpio_qei_ch_a = io_m2_io_qei_ch_a;
  assign m2_io_motor_gpio_qei_ch_b = io_m2_io_qei_ch_b;
  assign m2_io_ba_match = wb_inter_connect_io_m2_addr_sel;
  assign m3_clock = clock;
  assign m3_reset = reset;
  assign m3_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr;
  assign m3_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data;
  assign m3_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we;
  assign m3_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel;
  assign m3_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb;
  assign m3_io_motor_gpio_qei_ch_a = io_m3_io_qei_ch_a;
  assign m3_io_motor_gpio_qei_ch_b = io_m3_io_qei_ch_b;
  assign m3_io_ba_match = wb_inter_connect_io_m3_addr_sel;
  assign imem_clock = clock;
  assign imem_io_addr = wb_inter_connect_io_imem_io_addr;
  assign imem_io_wdata = wb_inter_connect_io_imem_io_wdata;
  assign imem_io_cs = wb_inter_connect_io_imem_io_cs;
  assign imem_io_wr_en = wb_inter_connect_io_imem_io_wr_en;
  assign imem_io_st_type = wb_inter_connect_io_imem_io_st_type;
  assign dmem_clock = clock;
  assign dmem_io_addr = wb_inter_connect_io_dmem_io_addr;
  assign dmem_io_wdata = wb_inter_connect_io_dmem_io_wdata;
  assign dmem_io_cs = wb_inter_connect_io_dmem_io_cs;
  assign dmem_io_wr_en = wb_inter_connect_io_dmem_io_wr_en;
  assign dmem_io_st_type = wb_inter_connect_io_dmem_io_st_type;
  
  assign  clock = wb_clk_i; 
  assign  reset = wb_rst_i;
  assign  io_out[0] =  io_uart_tx;
  assign  io_oeb[0] =  io_uart_txen;
  assign  io_uart_rx = io_in[0];
  assign  io_out[1] = io_spi_cs; 
  assign  io_out[2] = io_spi_clk;
  assign  io_out[3] = io_spi_mosi;
  assign  io_oeb[1] = io_spi_cs_en; 
  assign  io_oeb[2] = io_spi_clk_en;
  assign  io_oeb[3] = io_spi_mosi_en;
  assign  io_spi_miso = io_in[1];

  assign   io_m1_io_qei_ch_a = io_in[2];
  assign   io_m1_io_qei_ch_b = io_in[3];
  assign   io_out[4] = io_m1_io_pwm_high;
  assign   io_out[5] = io_m1_io_pwm_low;
  assign   io_oeb[4] = io_m1_io_pwm_high_en;
  assign   io_oeb[5] = io_m1_io_pwm_low_en;

  assign   io_m2_io_qei_ch_a = io_in[4];
  assign   io_m2_io_qei_ch_b = io_in[5];
  assign   io_out[6] = io_m2_io_pwm_high;
  assign   io_out[7] = io_m2_io_pwm_low;
  assign   io_oeb[6] = io_m2_io_pwm_high_en;
  assign   io_oeb[7] = io_m2_io_pwm_low_en;

  assign   io_m3_io_qei_ch_a = io_in[6];
  assign   io_m3_io_qei_ch_b = io_in[7];
  assign   io_out[8] = io_m3_io_pwm_high;
  assign   io_out[9] = io_m3_io_pwm_low;
  assign   io_oeb[8] = io_m3_io_pwm_high_en;
  assign   io_oeb[9] = io_m3_io_pwm_low_en;
endmodule