data/full_repos/permissive/458208177/test/8_bit_shift_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #2;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:22: Cannot find file containing module: \'shift_8_bit\'\nshift_8_bit M1(S, bb_right, bb_left, D, shift_in_right, shift_in_left, select);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/shift_8_bit\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/shift_8_bit.v\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/shift_8_bit.sv\n             shift_8_bit\n             shift_8_bit.v\n             shift_8_bit.sv\n             obj_dir/shift_8_bit\n             obj_dir/shift_8_bit.v\n             obj_dir/shift_8_bit.sv\n%Warning-WIDTH: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:33: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n                                                                             : ... In instance t_shift_8_bit\n    D = (i << 1) >> 2;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:34: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n                                                                             : ... In instance t_shift_8_bit\n    shift_in_left = (i >> 9);\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n                                                                             : ... In instance t_shift_8_bit\n    shift_in_right = (i << 9) >> 9;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/458208177/test/8_bit_shift_tb.v:38: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 32 bits.\n                                                                             : ... In instance t_shift_8_bit\n      select = k;\n             ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_shift_8_bit;

reg  [9:0] check;

wire [7:0]  S;
wire        bb_right, bb_left;

reg [7:0]  D;
reg        shift_in_right, shift_in_left;
reg        select;

reg[9:0] i;

integer k;

integer num_correct;
integer num_wrong;


shift_8_bit M1(S, bb_right, bb_left, D, shift_in_right, shift_in_left, select);


initial begin
  $display("Running testbench, this may take a minute or two...");


  num_correct = 0; num_wrong = 0;


  for (i = 0; i <= 254; i = i + 1) begin
    D = (i << 1) >> 2;
    shift_in_left = (i >> 9);
    shift_in_right = (i << 9) >> 9;

    for (k = 0; k < 2; k = k + 1) begin
      select = k;



      if (k == 0) begin
        check = i << 1;
      end else begin
        check = i >> 1;
      end



      #2;
      if ({bb_left, S, bb_right} == check) begin
        num_correct = num_correct + 1;
      end else begin
        num_wrong = num_wrong + 1;

        $display($time, " ASSERTION ERROR: input = %b, check = %b, actual = %b, shift_in_left = %b, shift_in_right = %b, D = %b", i, check, {bb_left, S, bb_right}, shift_in_left, shift_in_right, D);
      end

    end
  end

  $display("num_correct = %d, num_wrong = %d", num_correct, num_wrong);


  $finish;
end

endmodule
module t_shift_8_bit;


reg  [9:0] check;

wire [7:0]  S;
wire        bb_right, bb_left;

reg [7:0]  D;
reg        shift_in_right, shift_in_left;
reg        select;

reg[9:0] i;

integer k;

integer num_correct;
integer num_wrong;


shift_8_bit M1(S, bb_right, bb_left, D, shift_in_right, shift_in_left, select);


initial begin
  $display("Running testbench, this may take a minute or two...");


  num_correct = 0; num_wrong = 0;


  for (i = 0; i <= 254; i = i + 1) begin
    D = (i << 1) >> 2;
    shift_in_left = (i >> 9);
    shift_in_right = (i << 9) >> 9;

    for (k = 0; k < 2; k = k + 1) begin
      select = k;



      if (k == 0) begin
        check = i << 1;
      end else begin
        check = i >> 1;
      end



      #2;
      if ({bb_left, S, bb_right} == check) begin
        num_correct = num_correct + 1;
      end else begin
        num_wrong = num_wrong + 1;

        $display($time, " ASSERTION ERROR: input = %b, check = %b, actual = %b, shift_in_left = %b, shift_in_right = %b, D = %b", i, check, {bb_left, S, bb_right}, shift_in_left, shift_in_right, D);
      end

    end
  end

  $display("num_correct = %d, num_wrong = %d", num_correct, num_wrong);


  $finish;
end

endmodule