data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:15: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'forloops01\'\nmodule forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);\n       ^~~~~~~~~~\n                                                                                            : ... Top module \'forloops02\'\nmodule forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:19: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 4 bits.\n                                                                                         : ... In instance forloops02\n   q[k] = {~a, ~b, a, b} >> k[1:0];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:22: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                         : ... In instance forloops02\n  x = k + {a, b};\n        ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:22: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                         : ... In instance forloops02\n  x = k + {a, b};\n    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:24: Operator SUB expects 32 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                         : ... In instance forloops02\n assign y = k - {a, b};\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:24: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                         : ... In instance forloops02\n assign y = k - {a, b};\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:5: Operator XOR expects 64 bits on the LHS, but LHS\'s REPLICATE generates 2 bits.\n                                                                                        : ... In instance forloops01\n   p[2*k +: 2] = {a, b} ^ {2{k}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:5: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s XOR generates 64 bits.\n                                                                                        : ... In instance forloops01\n   p[2*k +: 2] = {a, b} ^ {2{k}};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:6: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                        : ... In instance forloops01\n  x <= k + {a, b};\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:6: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                        : ... In instance forloops01\n  x <= k + {a, b};\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:10: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 4 bits.\n                                                                                         : ... In instance forloops01\n   q[k] = {~a, ~b, a, b} >> k[1:0];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:11: Operator SUB expects 32 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                         : ... In instance forloops01\n  y = k - {a, b};\n        ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/forloops.v:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                         : ... In instance forloops01\n  y = k - {a, b};\n    ^\n%Error: Exiting due to 13 warning(s)\n'
module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
	integer k;
	always @(posedge clk) begin
		for (k=0; k<2; k=k+1)
			p[2*k +: 2] = {a, b} ^ {2{k}};
		x <= k + {a, b};
	end
	always @* begin
		for (k=0; k<4; k=k+1)
			q[k] = {~a, ~b, a, b} >> k[1:0];
		y = k - {a, b};
	end
endmodule
module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);

	integer k;
	always @(posedge clk) begin
		for (k=0; k<2; k=k+1)
			p[2*k +: 2] = {a, b} ^ {2{k}};
		x <= k + {a, b};
	end
	always @* begin
		for (k=0; k<4; k=k+1)
			q[k] = {~a, ~b, a, b} >> k[1:0];
		y = k - {a, b};
	end
endmodule