data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlreqack.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlreqack.v:72: Cannot find file containing module: 'rtlfifordy2ck'\nrtlfifordy2ck ififo\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/rtlfifordy2ck\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/rtlfifordy2ck.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/rtlfifordy2ck.sv\n             rtlfifordy2ck\n             rtlfifordy2ck.v\n             rtlfifordy2ck.sv\n             obj_dir/rtlfifordy2ck\n             obj_dir/rtlfifordy2ck.v\n             obj_dir/rtlfifordy2ck.sv\n%Error: Exiting due to 1 error(s)\n"
module rtlreqack
    (
     clk,
     rst,


     req,
     reqinfo,
     ack,
     vld,


     fifowr,
     fifodi,


     flush,
     reqen,
     fifowrerr,
     fiforderr,
     fifofull,
     fifowa,
     fifolen
     );



parameter           ADD = 8;
parameter           LEN = 256;
parameter           WIDTH = 128;
parameter           TYPE = "AUTO";



input               clk,
                    rst;

output              req;
output [WIDTH-1:0]  reqinfo;
input               ack;
output              vld;
input               flush;
input               reqen;         
input               fifowr;
input [WIDTH-1:0]   fifodi;

output              fifowrerr;
output              fiforderr;
output              fifofull;
output [ADD-1:0]    fifowa;
output [ADD:0]      fifolen;







rtlfifordy2ck ififo
    (
     .wrclk         (clk),
     .wrrst        (rst),
     .rdclk         (clk),
     .rdrst        (rst),
     

     .fifordy       (req),
     .fifodout      (reqinfo),
     .fifoget       (ack),
     .fifovld       (vld),
     

     .fifowr        (fifowr),
     .fifodi        (fifodi),
     

     .flush         (flush),
     .reqen         (reqen),
     .fifowrerr     (fifowrerr),
     .fiforderr     (fiforderr),
     .fifofull      (fifofull),
     .fifolen       (fifolen),
     .fifowa        (fifowa)
     );
defparam
        ififo.ADD = ADD,
        ififo.LEN = LEN,
        ififo.WIDTH = WIDTH,
        ififo.TYPE = TYPE,
        ififo.DUAL_CLK = "OFF";

endmodule
module rtlreqack
    (
     clk,
     rst,


     req,
     reqinfo,
     ack,
     vld,


     fifowr,
     fifodi,


     flush,
     reqen,
     fifowrerr,
     fiforderr,
     fifofull,
     fifowa,
     fifolen
     );




parameter           ADD = 8;
parameter           LEN = 256;
parameter           WIDTH = 128;
parameter           TYPE = "AUTO";



input               clk,
                    rst;

output              req;
output [WIDTH-1:0]  reqinfo;
input               ack;
output              vld;
input               flush;
input               reqen;         
input               fifowr;
input [WIDTH-1:0]   fifodi;

output              fifowrerr;
output              fiforderr;
output              fifofull;
output [ADD-1:0]    fifowa;
output [ADD:0]      fifolen;







rtlfifordy2ck ififo
    (
     .wrclk         (clk),
     .wrrst        (rst),
     .rdclk         (clk),
     .rdrst        (rst),
     

     .fifordy       (req),
     .fifodout      (reqinfo),
     .fifoget       (ack),
     .fifovld       (vld),
     

     .fifowr        (fifowr),
     .fifodi        (fifodi),
     

     .flush         (flush),
     .reqen         (reqen),
     .fifowrerr     (fifowrerr),
     .fiforderr     (fiforderr),
     .fifofull      (fifofull),
     .fifolen       (fifolen),
     .fifowa        (fifowa)
     );
defparam
        ififo.ADD = ADD,
        ififo.LEN = LEN,
        ififo.WIDTH = WIDTH,
        ififo.TYPE = TYPE,
        ififo.DUAL_CLK = "OFF";

endmodule