data/full_repos/permissive/463395574/control.v
1: b'%Error: data/full_repos/permissive/463395574/control.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/control.v:6: Define or directive not defined: \'`INSTR_SIZE\'\n    input [`INSTR_SIZE-1:0] instr,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:29: Define or directive not defined: \'`OP_AUIPC\'\n    assign ALUSrcA = (opcode == `OP_AUIPC);\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign ALUSrcA = (opcode == `OP_AUIPC);\n                                         ^\n%Error: data/full_repos/permissive/463395574/control.v:30: Define or directive not defined: \'`OP_I_TYPE\'\n    assign ALUSrcB = (opcode == `OP_I_TYPE\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:31: Define or directive not defined: \'`OP_LUI\'\n                     | opcode == `OP_LUI\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:32: Define or directive not defined: \'`OP_AUIPC\'\n                     | opcode == `OP_AUIPC\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:33: Define or directive not defined: \'`OP_LOAD\'\n                     | opcode == `OP_LOAD\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:34: Define or directive not defined: \'`OP_STORE\'\n                     | opcode == `OP_STORE);\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                     | opcode == `OP_STORE);\n                                          ^\n%Error: data/full_repos/permissive/463395574/control.v:35: Define or directive not defined: \'`OP_BRANCH\'\n    assign branch = (opcode == `OP_BRANCH);\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:35: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign branch = (opcode == `OP_BRANCH);\n                                         ^\n%Error: data/full_repos/permissive/463395574/control.v:36: Define or directive not defined: \'`OP_LOAD\'\n    assign memRead = (opcode == `OP_LOAD);\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign memRead = (opcode == `OP_LOAD);\n                                        ^\n%Error: data/full_repos/permissive/463395574/control.v:37: Define or directive not defined: \'`OP_STORE\'\n    assign memWrite = (opcode == `OP_STORE);\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign memWrite = (opcode == `OP_STORE);\n                                          ^\n%Error: data/full_repos/permissive/463395574/control.v:38: Define or directive not defined: \'`OP_R_TYPE\'\n    assign regWrite = (opcode == `OP_R_TYPE\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:39: Define or directive not defined: \'`OP_I_TYPE\'\n                      | opcode == `OP_I_TYPE\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:40: Define or directive not defined: \'`OP_JAL\'\n                      | opcode == `OP_JAL\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:41: Define or directive not defined: \'`OP_JALR\'\n                      | opcode == `OP_JALR\n                                  ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:42: Define or directive not defined: \'`OP_LUI\'\n                      | opcode == `OP_LUI\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:43: Define or directive not defined: \'`OP_AUIPC\'\n                      | opcode == `OP_AUIPC\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:44: Define or directive not defined: \'`OP_LOAD\'\n                      | opcode == `OP_LOAD\n                                  ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                      ) & (rd != `REG_IDX_WIDTH\'b0);\n                      ^\n%Error: data/full_repos/permissive/463395574/control.v:45: Define or directive not defined: \'`REG_IDX_WIDTH\'\n                      ) & (rd != `REG_IDX_WIDTH\'b0);\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:48: Define or directive not defined: \'`OP_JAL\'\n    if (opcode == `OP_JAL | opcode == `OP_JALR)\n                  ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:48: Define or directive not defined: \'`OP_JALR\'\n    if (opcode == `OP_JAL | opcode == `OP_JALR)\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (opcode == `OP_JAL | opcode == `OP_JALR)\n                                              ^\n%Error: data/full_repos/permissive/463395574/control.v:50: Define or directive not defined: \'`OP_JAL\'\n            jumpType <= opcode == `OP_JAL ? `JUMP_TYPE_JAL : `JUMP_TYPE_JALR;\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:50: Define or directive not defined: \'`JUMP_TYPE_JAL\'\n            jumpType <= opcode == `OP_JAL ? `JUMP_TYPE_JAL : `JUMP_TYPE_JALR;\n                                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:50: Define or directive not defined: \'`JUMP_TYPE_JALR\'\n            jumpType <= opcode == `OP_JAL ? `JUMP_TYPE_JAL : `JUMP_TYPE_JALR;\n                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:53: Define or directive not defined: \'`OP_LOAD\'\n    else if (opcode == `OP_LOAD)\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:55: Define or directive not defined: \'`JUMP_TYPE_NONE\'\n            jumpType <= `JUMP_TYPE_NONE;\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:60: Define or directive not defined: \'`JUMP_TYPE_NONE\'\n            jumpType <= `JUMP_TYPE_NONE;\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:67: Define or directive not defined: \'`OP_LUI\'\n        `OP_LUI:\n        ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:69: Define or directive not defined: \'`IMM_CTRL_UTYPE\'\n                immCtrl <= `IMM_CTRL_UTYPE;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:70: Define or directive not defined: \'`ALU_CTRL_LUI\'\n                ALUCtrl <= `ALU_CTRL_LUI;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:72: Define or directive not defined: \'`OP_AUIPC\'\n        `OP_AUIPC:\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:74: Define or directive not defined: \'`IMM_CTRL_UTYPE\'\n                immCtrl <= `IMM_CTRL_UTYPE;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:75: Define or directive not defined: \'`ALU_CTRL_AUIPC\'\n                ALUCtrl <= `ALU_CTRL_AUIPC;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:77: Define or directive not defined: \'`OP_JAL\'\n        `OP_JAL:\n        ^~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:79: Define or directive not defined: \'`IMM_CTRL_JTYPE\'\n                immCtrl <= `IMM_CTRL_JTYPE;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:80: Define or directive not defined: \'`ALU_CTRL_ZERO\'\n                ALUCtrl <= `ALU_CTRL_ZERO;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:82: Define or directive not defined: \'`OP_JALR\'\n        `OP_JALR:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:84: Define or directive not defined: \'`IMM_CTRL_ITYPE\'\n                immCtrl <= `IMM_CTRL_ITYPE;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:85: Define or directive not defined: \'`ALU_CTRL_ZERO\'\n                ALUCtrl <= `ALU_CTRL_ZERO;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:87: Define or directive not defined: \'`OP_BRANCH\'\n        `OP_BRANCH:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:89: Define or directive not defined: \'`IMM_CTRL_BTYPE\'\n                immCtrl <= `IMM_CTRL_BTYPE;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:90: Define or directive not defined: \'`ALU_CTRL_ZERO\'\n                ALUCtrl <= `ALU_CTRL_ZERO;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/control.v:92: Define or directive not defined: \'`OP_LOAD\'\n        `OP_LOAD:\n        ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ControlUnit (
    input [`INSTR_SIZE-1:0] instr,

    output reg [4:0] immCtrl,
    output reg [3:0] ALUCtrl,
    output           ALUSrcA,
    output           ALUSrcB,
    output           branch,
    output     [2:0] funct3,
    output reg [1:0] jumpType,
    output           memRead,
    output           memWrite,
    output reg [1:0] memtoReg,
    output           regWrite
);

    wire [6:0] opcode = instr[6:0];
    assign funct3 = instr[14:12];
    wire [6:0] funct7 = instr[31:25];
    wire [4:0] rs1 = instr[19:15];
    wire [4:0] rs2 = instr[24:20];
    wire [4:0] rd = instr[11:7];


    assign ALUSrcA = (opcode == `OP_AUIPC);
    assign ALUSrcB = (opcode == `OP_I_TYPE
                     | opcode == `OP_LUI
                     | opcode == `OP_AUIPC
                     | opcode == `OP_LOAD
                     | opcode == `OP_STORE);
    assign branch = (opcode == `OP_BRANCH);
    assign memRead = (opcode == `OP_LOAD);
    assign memWrite = (opcode == `OP_STORE);
    assign regWrite = (opcode == `OP_R_TYPE
                      | opcode == `OP_I_TYPE
                      | opcode == `OP_JAL
                      | opcode == `OP_JALR
                      | opcode == `OP_LUI
                      | opcode == `OP_AUIPC
                      | opcode == `OP_LOAD
                      ) & (rd != `REG_IDX_WIDTH'b0);

    always @(*)
    if (opcode == `OP_JAL | opcode == `OP_JALR)
        begin
            jumpType <= opcode == `OP_JAL ? `JUMP_TYPE_JAL : `JUMP_TYPE_JALR;
            memtoReg <= 2'b10;
        end
    else if (opcode == `OP_LOAD)
        begin
            jumpType <= `JUMP_TYPE_NONE;
            memtoReg <= 2'b01;
        end
    else
        begin
            jumpType <= `JUMP_TYPE_NONE;
            memtoReg <= 2'b00;
        end


    always @(*)
    case(opcode)
        `OP_LUI:
            begin
                immCtrl <= `IMM_CTRL_UTYPE;
                ALUCtrl <= `ALU_CTRL_LUI;
            end
        `OP_AUIPC:
            begin
                immCtrl <= `IMM_CTRL_UTYPE;
                ALUCtrl <= `ALU_CTRL_AUIPC;
            end
        `OP_JAL:
            begin
                immCtrl <= `IMM_CTRL_JTYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_JALR:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_BRANCH:
            begin
                immCtrl <= `IMM_CTRL_BTYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_LOAD:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                ALUCtrl <= `ALU_CTRL_ADD;
            end
        `OP_STORE:
            begin
                immCtrl <= `IMM_CTRL_STYPE;
                ALUCtrl <= `ALU_CTRL_ADD;
            end
        `OP_I_TYPE:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                case (funct3)
                    `FUNCT3_ADDI:
                        ALUCtrl <= `ALU_CTRL_ADD;
                    `FUNCT3_SLTI:
                        ALUCtrl <= `ALU_CTRL_SLT;
                    `FUNCT3_SLTIU:
                        ALUCtrl <= `ALU_CTRL_SLTU;
                    `FUNCT3_XORI:
                        ALUCtrl <= `ALU_CTRL_XOR;
                    `FUNCT3_ORI:
                        ALUCtrl <= `ALU_CTRL_OR;
                    `FUNCT3_ANDI:
                        ALUCtrl <= `ALU_CTRL_AND;
                    `FUNCT3_SLL:
                        ALUCtrl <= `ALU_CTRL_SLL;
                    `FUNCT3_SR:
                        case (funct7)
                            `FUNCT7_SRL:
                                ALUCtrl <= `ALU_CTRL_SRL;
                            `FUNCT7_SRA:
                                ALUCtrl <= `ALU_CTRL_SRA;
                            default:
                                ALUCtrl <= `ALU_CTRL_ZERO;
                        endcase
                    default:
                        ALUCtrl <= `ALU_CTRL_ZERO;
                endcase
            end
        `OP_R_TYPE:
            case (funct3)
                `FUNCT3_ADD:
                    case (funct7)
                        `FUNCT7_ADD:
                            ALUCtrl <= `ALU_CTRL_ADD;
                        `FUNCT7_SUB:
                            ALUCtrl <= `ALU_CTRL_SUB;
                        default:
                            ALUCtrl <= `ALU_CTRL_ZERO;
                    endcase
                `FUNCT3_SL:
                    ALUCtrl <= `ALU_CTRL_SLL;
                `FUNCT3_SLT:
                    ALUCtrl <= `ALU_CTRL_SLT;
                `FUNCT3_SLTU:
                    ALUCtrl <= `ALU_CTRL_SLTU;
                `FUNCT3_XOR:
                    ALUCtrl <= `ALU_CTRL_XOR;
                `FUNCT3_SR:
                    case (funct7)
                        `FUNCT7_SRL:
                            ALUCtrl <= `ALU_CTRL_SRL;
                        `FUNCT7_SRA:
                            ALUCtrl <= `ALU_CTRL_SRA;
                        default:
                            ALUCtrl <= `ALU_CTRL_ZERO;
                    endcase
                `FUNCT3_OR:
                    ALUCtrl <= `ALU_CTRL_OR;
                `FUNCT3_AND:
                    ALUCtrl <= `ALU_CTRL_AND;
            endcase
        default:    ALUCtrl <= `ALU_CTRL_ZERO;
	endcase
endmodule
module ControlUnit (
    input [`INSTR_SIZE-1:0] instr,

    output reg [4:0] immCtrl,
    output reg [3:0] ALUCtrl,
    output           ALUSrcA,
    output           ALUSrcB,
    output           branch,
    output     [2:0] funct3,
    output reg [1:0] jumpType,
    output           memRead,
    output           memWrite,
    output reg [1:0] memtoReg,
    output           regWrite
);


    wire [6:0] opcode = instr[6:0];
    assign funct3 = instr[14:12];
    wire [6:0] funct7 = instr[31:25];
    wire [4:0] rs1 = instr[19:15];
    wire [4:0] rs2 = instr[24:20];
    wire [4:0] rd = instr[11:7];


    assign ALUSrcA = (opcode == `OP_AUIPC);
    assign ALUSrcB = (opcode == `OP_I_TYPE
                     | opcode == `OP_LUI
                     | opcode == `OP_AUIPC
                     | opcode == `OP_LOAD
                     | opcode == `OP_STORE);
    assign branch = (opcode == `OP_BRANCH);
    assign memRead = (opcode == `OP_LOAD);
    assign memWrite = (opcode == `OP_STORE);
    assign regWrite = (opcode == `OP_R_TYPE
                      | opcode == `OP_I_TYPE
                      | opcode == `OP_JAL
                      | opcode == `OP_JALR
                      | opcode == `OP_LUI
                      | opcode == `OP_AUIPC
                      | opcode == `OP_LOAD
                      ) & (rd != `REG_IDX_WIDTH'b0);

    always @(*)
    if (opcode == `OP_JAL | opcode == `OP_JALR)
        begin
            jumpType <= opcode == `OP_JAL ? `JUMP_TYPE_JAL : `JUMP_TYPE_JALR;
            memtoReg <= 2'b10;
        end
    else if (opcode == `OP_LOAD)
        begin
            jumpType <= `JUMP_TYPE_NONE;
            memtoReg <= 2'b01;
        end
    else
        begin
            jumpType <= `JUMP_TYPE_NONE;
            memtoReg <= 2'b00;
        end


    always @(*)
    case(opcode)
        `OP_LUI:
            begin
                immCtrl <= `IMM_CTRL_UTYPE;
                ALUCtrl <= `ALU_CTRL_LUI;
            end
        `OP_AUIPC:
            begin
                immCtrl <= `IMM_CTRL_UTYPE;
                ALUCtrl <= `ALU_CTRL_AUIPC;
            end
        `OP_JAL:
            begin
                immCtrl <= `IMM_CTRL_JTYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_JALR:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_BRANCH:
            begin
                immCtrl <= `IMM_CTRL_BTYPE;
                ALUCtrl <= `ALU_CTRL_ZERO;
            end
        `OP_LOAD:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                ALUCtrl <= `ALU_CTRL_ADD;
            end
        `OP_STORE:
            begin
                immCtrl <= `IMM_CTRL_STYPE;
                ALUCtrl <= `ALU_CTRL_ADD;
            end
        `OP_I_TYPE:
            begin
                immCtrl <= `IMM_CTRL_ITYPE;
                case (funct3)
                    `FUNCT3_ADDI:
                        ALUCtrl <= `ALU_CTRL_ADD;
                    `FUNCT3_SLTI:
                        ALUCtrl <= `ALU_CTRL_SLT;
                    `FUNCT3_SLTIU:
                        ALUCtrl <= `ALU_CTRL_SLTU;
                    `FUNCT3_XORI:
                        ALUCtrl <= `ALU_CTRL_XOR;
                    `FUNCT3_ORI:
                        ALUCtrl <= `ALU_CTRL_OR;
                    `FUNCT3_ANDI:
                        ALUCtrl <= `ALU_CTRL_AND;
                    `FUNCT3_SLL:
                        ALUCtrl <= `ALU_CTRL_SLL;
                    `FUNCT3_SR:
                        case (funct7)
                            `FUNCT7_SRL:
                                ALUCtrl <= `ALU_CTRL_SRL;
                            `FUNCT7_SRA:
                                ALUCtrl <= `ALU_CTRL_SRA;
                            default:
                                ALUCtrl <= `ALU_CTRL_ZERO;
                        endcase
                    default:
                        ALUCtrl <= `ALU_CTRL_ZERO;
                endcase
            end
        `OP_R_TYPE:
            case (funct3)
                `FUNCT3_ADD:
                    case (funct7)
                        `FUNCT7_ADD:
                            ALUCtrl <= `ALU_CTRL_ADD;
                        `FUNCT7_SUB:
                            ALUCtrl <= `ALU_CTRL_SUB;
                        default:
                            ALUCtrl <= `ALU_CTRL_ZERO;
                    endcase
                `FUNCT3_SL:
                    ALUCtrl <= `ALU_CTRL_SLL;
                `FUNCT3_SLT:
                    ALUCtrl <= `ALU_CTRL_SLT;
                `FUNCT3_SLTU:
                    ALUCtrl <= `ALU_CTRL_SLTU;
                `FUNCT3_XOR:
                    ALUCtrl <= `ALU_CTRL_XOR;
                `FUNCT3_SR:
                    case (funct7)
                        `FUNCT7_SRL:
                            ALUCtrl <= `ALU_CTRL_SRL;
                        `FUNCT7_SRA:
                            ALUCtrl <= `ALU_CTRL_SRA;
                        default:
                            ALUCtrl <= `ALU_CTRL_ZERO;
                    endcase
                `FUNCT3_OR:
                    ALUCtrl <= `ALU_CTRL_OR;
                `FUNCT3_AND:
                    ALUCtrl <= `ALU_CTRL_AND;
            endcase
        default:    ALUCtrl <= `ALU_CTRL_ZERO;
	endcase
endmodule