data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:34: syntax error, unexpected ::, expecting ')' or ','\n  parameter tcdm_interconnect_pkg::topo_e Topology        = tcdm_interconnect_pkg::LIC,\n                                 ^~\n                                                                                                                                     : ... Perhaps 'tcdm_interconnect_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:39: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned                  ClosConfig      = 2\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:41: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:43: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                                  rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:45: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0]                      req_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:46: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][AddrWidth-1:0]       add_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:47: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0]                      wen_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:48: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][DataWidth-1:0]       wdata_i,    \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:49: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [NumIn-1:0][BeWidth-1:0]         be_i,       \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:50: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0]                      gnt_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:51: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0]                      vld_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:52: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [NumIn-1:0][DataWidth-1:0]       rdata_o,    \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:54: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output  logic [NumOut-1:0]                    req_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:55: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input   logic [NumOut-1:0]                    gnt_i,      \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:56: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output  logic [NumOut-1:0][AddrMemWidth-1:0]  add_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:57: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output  logic [NumOut-1:0]                    wen_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:58: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output  logic [NumOut-1:0][DataWidth-1:0]     wdata_o,    \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:59: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output  logic [NumOut-1:0][BeWidth-1:0]       be_o,       \n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:60: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input   logic [NumOut-1:0][DataWidth-1:0]     rdata_i     \n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:61: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:73: syntax error, unexpected for\nfor (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs\n^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:135: syntax error, unexpected IDENTIFIER\n  lfsr #(\n  ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv:239: syntax error, unexpected assign\n    assign rr2 = $clog2(NumPar)'(rr[$clog2(NumPar)-1:0]);\n    ^~~~~~\n%Error: Exiting due to 23 error(s)\n"
module tcdm_interconnect #(


  parameter int unsigned                  NumIn           = 32,
  parameter int unsigned                  NumOut          = 64,
  parameter int unsigned                  AddrWidth       = 32,
  parameter int unsigned                  DataWidth       = 32,
  parameter int unsigned                  BeWidth         = DataWidth/8,
  parameter int unsigned                  AddrMemWidth    = 12,
  parameter bit                           WriteRespOn     = 1,
  parameter int unsigned                  RespLat         = 1,


  parameter int unsigned                  ByteOffWidth    = $clog2(DataWidth-1)-3,


  parameter tcdm_interconnect_pkg::topo_e Topology        = tcdm_interconnect_pkg::LIC,

  parameter int unsigned                  NumPar          = 1,


  parameter int unsigned                  ClosConfig      = 2

) (
  input  logic                                  clk_i,
  input  logic                                  rst_ni,

  input  logic [NumIn-1:0]                      req_i,
  input  logic [NumIn-1:0][AddrWidth-1:0]       add_i,
  input  logic [NumIn-1:0]                      wen_i,
  input  logic [NumIn-1:0][DataWidth-1:0]       wdata_i,
  input  logic [NumIn-1:0][BeWidth-1:0]         be_i,
  output logic [NumIn-1:0]                      gnt_o,
  output logic [NumIn-1:0]                      vld_o,
  output logic [NumIn-1:0][DataWidth-1:0]       rdata_o,

  output  logic [NumOut-1:0]                    req_o,
  input   logic [NumOut-1:0]                    gnt_i,
  output  logic [NumOut-1:0][AddrMemWidth-1:0]  add_o,
  output  logic [NumOut-1:0]                    wen_o,
  output  logic [NumOut-1:0][DataWidth-1:0]     wdata_o,
  output  logic [NumOut-1:0][BeWidth-1:0]       be_o,
  input   logic [NumOut-1:0][DataWidth-1:0]     rdata_i
);





localparam int unsigned NumOutLog2    = $clog2(NumOut);
localparam int unsigned AggDataWidth  = 1+BeWidth+AddrMemWidth+DataWidth;
logic [NumIn-1:0][AggDataWidth-1:0]  data_agg_in;
logic [NumOut-1:0][AggDataWidth-1:0] data_agg_out;
logic [NumIn-1:0][NumOutLog2-1:0] bank_sel;

for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs

  assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth];

  assign data_agg_in[j] = {wen_i[j], be_i[j], add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], wdata_i[j]};
end


for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
  assign {wen_o[k], be_o[k], add_o[k], wdata_o[k]} = data_agg_out[k];
end




if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic
  xbar #(
    .NumIn         ( NumIn        ),
    .NumOut        ( NumOut       ),
    .ReqDataWidth  ( AggDataWidth ),
    .RespDataWidth ( DataWidth    ),
    .RespLat       ( RespLat      ),
    .WriteRespOn   ( WriteRespOn  )
  ) i_xbar (
    .clk_i   ( clk_i        ),
    .rst_ni  ( rst_ni       ),
    .req_i   ( req_i        ),
    .add_i   ( bank_sel     ),
    .wen_i   ( wen_i        ),
    .wdata_i ( data_agg_in  ),
    .gnt_o   ( gnt_o        ),
    .rdata_o ( rdata_o      ),
    .rr_i    ( '0           ),
    .vld_o   ( vld_o        ),
    .gnt_i   ( gnt_i        ),
    .req_o   ( req_o        ),
    .wdata_o ( data_agg_out ),
    .rdata_i ( rdata_i      )
  );




end else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin : gen_bfly
  localparam int unsigned NumPerSlice = NumIn/NumPar;
  localparam int unsigned Radix       = 2**Topology;
  logic [NumOut-1:0][NumPar-1:0][AggDataWidth-1:0]  data1;
  logic [NumOut-1:0][NumPar-1:0][DataWidth-1:0]     rdata1;
  logic [NumOut-1:0][NumPar-1:0] gnt1, req1;

  logic [NumPar-1:0][NumOut-1:0][AggDataWidth-1:0]  data1_trsp;
  logic [NumPar-1:0][NumOut-1:0][DataWidth-1:0]     rdata1_trsp;
  logic [NumPar-1:0][NumOut-1:0] gnt1_trsp, req1_trsp;

  logic [$clog2(NumIn)-1:0] rr;
  logic [NumOutLog2-1:0] rr1;






  lfsr #(
    .LfsrWidth(64),
    .OutWidth($clog2(NumIn)),
    .CipherLayers(3),
    .CipherReg(1'b1)
  ) lfsr_i (
    .clk_i,
    .rst_ni,
    .en_i(|(gnt_i & req_o)),
    .out_o(rr)
  );















































  assign rr1 = NumOutLog2'(rr[$high(rr):$clog2(NumPar)]);

  for (genvar j = 0; unsigned'(j) < NumPar; j++) begin : gen_bfly2_net
    bfly_net #(
      .NumIn         ( NumPerSlice  ),
      .NumOut        ( NumOut       ),
      .ReqDataWidth  ( AggDataWidth ),
      .RespDataWidth ( DataWidth    ),
      .RespLat       ( RespLat      ),
      .Radix         ( Radix        ),
      .WriteRespOn   ( WriteRespOn  ),
      .ExtPrio       ( 1'b1         )
    ) i_bfly_net (
      .clk_i    ( clk_i             ),
      .rst_ni   ( rst_ni            ),
      .rr_i     ( rr1               ),
      .req_i    ( req_i[j*NumPerSlice +: NumPerSlice  ]      ),
      .gnt_o    ( gnt_o[j*NumPerSlice +: NumPerSlice ]       ),
      .add_i    ( bank_sel[j*NumPerSlice +: NumPerSlice ]    ),
      .wen_i    ( wen_i[j*NumPerSlice +: NumPerSlice  ]      ),
      .wdata_i  ( data_agg_in[j*NumPerSlice +: NumPerSlice ] ),
      .rdata_o  ( rdata_o[j*NumPerSlice +: NumPerSlice ]     ),
      .vld_o    ( vld_o[j*NumPerSlice +: NumPerSlice  ]      ),
      .req_o    ( req1_trsp[j]      ),
      .gnt_i    ( gnt1_trsp[j]      ),
      .wdata_o  ( data1_trsp[j]     ),
      .rdata_i  ( rdata1_trsp[j]    )
    );
  end


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_trsp1
    assign rdata1[k] = {NumPar{rdata_i[k]}};
    for (genvar j = 0; unsigned'(j) < NumPar; j++) begin : gen_trsp2

      assign data1[k][j] = data1_trsp[j][k];
      assign req1[k][j]  = req1_trsp[j][k];

      assign rdata1_trsp[j][k] = rdata1[k][j];
      assign gnt1_trsp[j][k]   = gnt1[k][j];
    end
  end

  if (NumPar > unsigned'(1)) begin : gen_rr_arb

    logic [$clog2(NumPar)-1:0] rr2;
    assign rr2 = $clog2(NumPar)'(rr[$clog2(NumPar)-1:0]);

    for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_par
      rr_arb_tree #(
        .NumIn     ( NumPar       ),
        .DataWidth ( AggDataWidth ),
        .ExtPrio   ( 1'b1         )
      ) i_rr_arb_tree (
        .clk_i   ( clk_i           ),
        .rst_ni  ( rst_ni          ),
        .flush_i ( 1'b0            ),
        .rr_i    ( rr2             ),
        .req_i   ( req1[k]         ),
        .gnt_o   ( gnt1[k]         ),
        .data_i  ( data1[k]        ),
        .gnt_i   ( gnt_i[k]        ),
        .req_o   ( req_o[k]        ),
        .data_o  ( data_agg_out[k] ),
        .idx_o   (                 )
      );
    end
  end else begin : gen_no_rr_arb

      assign data_agg_out = data1;
      assign req_o        = req1;
      assign gnt1         = gnt_i;
  end

  initial begin
    assert(NumPar >= unsigned'(1)) else
      $fatal(1,"NumPar must be greater or equal 1.");
  end




end else if (Topology == tcdm_interconnect_pkg::CLOS) begin : gen_clos
  clos_net #(
    .NumIn         ( NumIn        ),
    .NumOut        ( NumOut       ),
    .ReqDataWidth  ( AggDataWidth ),
    .RespDataWidth ( DataWidth    ),
    .RespLat       ( RespLat      ),
    .WriteRespOn   ( WriteRespOn  ),
    .ClosConfig    ( ClosConfig   )
  ) i_clos_net (
    .clk_i    ( clk_i        ),
    .rst_ni   ( rst_ni       ),
    .req_i    ( req_i        ),
    .gnt_o    ( gnt_o        ),
    .add_i    ( bank_sel     ),
    .wen_i    ( wen_i        ),
    .wdata_i  ( data_agg_in  ),
    .rdata_o  ( rdata_o      ),
    .vld_o    ( vld_o        ),
    .req_o    ( req_o        ),
    .gnt_i    ( gnt_i        ),
    .wdata_o  ( data_agg_out ),
    .rdata_i  ( rdata_i      )
  );

end else begin : gen_unknown

  initial begin
    $fatal(1,"Unknown TCDM configuration %d.", Topology);
  end

end








initial begin
	assert(AddrMemWidth+NumOutLog2 <= AddrWidth) else
    $fatal(1,"Address not wide enough to accomodate the requested TCDM configuration.");
  assert(NumOut >= NumIn) else
    $fatal(1,"NumOut < NumIn is not supported.");
end


endmodule
module tcdm_interconnect #(


  parameter int unsigned                  NumIn           = 32,
  parameter int unsigned                  NumOut          = 64,
  parameter int unsigned                  AddrWidth       = 32,
  parameter int unsigned                  DataWidth       = 32,
  parameter int unsigned                  BeWidth         = DataWidth/8,
  parameter int unsigned                  AddrMemWidth    = 12,
  parameter bit                           WriteRespOn     = 1,
  parameter int unsigned                  RespLat         = 1,


  parameter int unsigned                  ByteOffWidth    = $clog2(DataWidth-1)-3,


  parameter tcdm_interconnect_pkg::topo_e Topology        = tcdm_interconnect_pkg::LIC,

  parameter int unsigned                  NumPar          = 1,


  parameter int unsigned                  ClosConfig      = 2

) (
  input  logic                                  clk_i,
  input  logic                                  rst_ni,

  input  logic [NumIn-1:0]                      req_i,
  input  logic [NumIn-1:0][AddrWidth-1:0]       add_i,
  input  logic [NumIn-1:0]                      wen_i,
  input  logic [NumIn-1:0][DataWidth-1:0]       wdata_i,
  input  logic [NumIn-1:0][BeWidth-1:0]         be_i,
  output logic [NumIn-1:0]                      gnt_o,
  output logic [NumIn-1:0]                      vld_o,
  output logic [NumIn-1:0][DataWidth-1:0]       rdata_o,

  output  logic [NumOut-1:0]                    req_o,
  input   logic [NumOut-1:0]                    gnt_i,
  output  logic [NumOut-1:0][AddrMemWidth-1:0]  add_o,
  output  logic [NumOut-1:0]                    wen_o,
  output  logic [NumOut-1:0][DataWidth-1:0]     wdata_o,
  output  logic [NumOut-1:0][BeWidth-1:0]       be_o,
  input   logic [NumOut-1:0][DataWidth-1:0]     rdata_i
);






localparam int unsigned NumOutLog2    = $clog2(NumOut);
localparam int unsigned AggDataWidth  = 1+BeWidth+AddrMemWidth+DataWidth;
logic [NumIn-1:0][AggDataWidth-1:0]  data_agg_in;
logic [NumOut-1:0][AggDataWidth-1:0] data_agg_out;
logic [NumIn-1:0][NumOutLog2-1:0] bank_sel;

for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs

  assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth];

  assign data_agg_in[j] = {wen_i[j], be_i[j], add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], wdata_i[j]};
end


for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs
  assign {wen_o[k], be_o[k], add_o[k], wdata_o[k]} = data_agg_out[k];
end




if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic
  xbar #(
    .NumIn         ( NumIn        ),
    .NumOut        ( NumOut       ),
    .ReqDataWidth  ( AggDataWidth ),
    .RespDataWidth ( DataWidth    ),
    .RespLat       ( RespLat      ),
    .WriteRespOn   ( WriteRespOn  )
  ) i_xbar (
    .clk_i   ( clk_i        ),
    .rst_ni  ( rst_ni       ),
    .req_i   ( req_i        ),
    .add_i   ( bank_sel     ),
    .wen_i   ( wen_i        ),
    .wdata_i ( data_agg_in  ),
    .gnt_o   ( gnt_o        ),
    .rdata_o ( rdata_o      ),
    .rr_i    ( '0           ),
    .vld_o   ( vld_o        ),
    .gnt_i   ( gnt_i        ),
    .req_o   ( req_o        ),
    .wdata_o ( data_agg_out ),
    .rdata_i ( rdata_i      )
  );




end else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin : gen_bfly
  localparam int unsigned NumPerSlice = NumIn/NumPar;
  localparam int unsigned Radix       = 2**Topology;
  logic [NumOut-1:0][NumPar-1:0][AggDataWidth-1:0]  data1;
  logic [NumOut-1:0][NumPar-1:0][DataWidth-1:0]     rdata1;
  logic [NumOut-1:0][NumPar-1:0] gnt1, req1;

  logic [NumPar-1:0][NumOut-1:0][AggDataWidth-1:0]  data1_trsp;
  logic [NumPar-1:0][NumOut-1:0][DataWidth-1:0]     rdata1_trsp;
  logic [NumPar-1:0][NumOut-1:0] gnt1_trsp, req1_trsp;

  logic [$clog2(NumIn)-1:0] rr;
  logic [NumOutLog2-1:0] rr1;






  lfsr #(
    .LfsrWidth(64),
    .OutWidth($clog2(NumIn)),
    .CipherLayers(3),
    .CipherReg(1'b1)
  ) lfsr_i (
    .clk_i,
    .rst_ni,
    .en_i(|(gnt_i & req_o)),
    .out_o(rr)
  );















































  assign rr1 = NumOutLog2'(rr[$high(rr):$clog2(NumPar)]);

  for (genvar j = 0; unsigned'(j) < NumPar; j++) begin : gen_bfly2_net
    bfly_net #(
      .NumIn         ( NumPerSlice  ),
      .NumOut        ( NumOut       ),
      .ReqDataWidth  ( AggDataWidth ),
      .RespDataWidth ( DataWidth    ),
      .RespLat       ( RespLat      ),
      .Radix         ( Radix        ),
      .WriteRespOn   ( WriteRespOn  ),
      .ExtPrio       ( 1'b1         )
    ) i_bfly_net (
      .clk_i    ( clk_i             ),
      .rst_ni   ( rst_ni            ),
      .rr_i     ( rr1               ),
      .req_i    ( req_i[j*NumPerSlice +: NumPerSlice  ]      ),
      .gnt_o    ( gnt_o[j*NumPerSlice +: NumPerSlice ]       ),
      .add_i    ( bank_sel[j*NumPerSlice +: NumPerSlice ]    ),
      .wen_i    ( wen_i[j*NumPerSlice +: NumPerSlice  ]      ),
      .wdata_i  ( data_agg_in[j*NumPerSlice +: NumPerSlice ] ),
      .rdata_o  ( rdata_o[j*NumPerSlice +: NumPerSlice ]     ),
      .vld_o    ( vld_o[j*NumPerSlice +: NumPerSlice  ]      ),
      .req_o    ( req1_trsp[j]      ),
      .gnt_i    ( gnt1_trsp[j]      ),
      .wdata_o  ( data1_trsp[j]     ),
      .rdata_i  ( rdata1_trsp[j]    )
    );
  end


  for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_trsp1
    assign rdata1[k] = {NumPar{rdata_i[k]}};
    for (genvar j = 0; unsigned'(j) < NumPar; j++) begin : gen_trsp2

      assign data1[k][j] = data1_trsp[j][k];
      assign req1[k][j]  = req1_trsp[j][k];

      assign rdata1_trsp[j][k] = rdata1[k][j];
      assign gnt1_trsp[j][k]   = gnt1[k][j];
    end
  end

  if (NumPar > unsigned'(1)) begin : gen_rr_arb

    logic [$clog2(NumPar)-1:0] rr2;
    assign rr2 = $clog2(NumPar)'(rr[$clog2(NumPar)-1:0]);

    for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_par
      rr_arb_tree #(
        .NumIn     ( NumPar       ),
        .DataWidth ( AggDataWidth ),
        .ExtPrio   ( 1'b1         )
      ) i_rr_arb_tree (
        .clk_i   ( clk_i           ),
        .rst_ni  ( rst_ni          ),
        .flush_i ( 1'b0            ),
        .rr_i    ( rr2             ),
        .req_i   ( req1[k]         ),
        .gnt_o   ( gnt1[k]         ),
        .data_i  ( data1[k]        ),
        .gnt_i   ( gnt_i[k]        ),
        .req_o   ( req_o[k]        ),
        .data_o  ( data_agg_out[k] ),
        .idx_o   (                 )
      );
    end
  end else begin : gen_no_rr_arb

      assign data_agg_out = data1;
      assign req_o        = req1;
      assign gnt1         = gnt_i;
  end

  initial begin
    assert(NumPar >= unsigned'(1)) else
      $fatal(1,"NumPar must be greater or equal 1.");
  end




end else if (Topology == tcdm_interconnect_pkg::CLOS) begin : gen_clos
  clos_net #(
    .NumIn         ( NumIn        ),
    .NumOut        ( NumOut       ),
    .ReqDataWidth  ( AggDataWidth ),
    .RespDataWidth ( DataWidth    ),
    .RespLat       ( RespLat      ),
    .WriteRespOn   ( WriteRespOn  ),
    .ClosConfig    ( ClosConfig   )
  ) i_clos_net (
    .clk_i    ( clk_i        ),
    .rst_ni   ( rst_ni       ),
    .req_i    ( req_i        ),
    .gnt_o    ( gnt_o        ),
    .add_i    ( bank_sel     ),
    .wen_i    ( wen_i        ),
    .wdata_i  ( data_agg_in  ),
    .rdata_o  ( rdata_o      ),
    .vld_o    ( vld_o        ),
    .req_o    ( req_o        ),
    .gnt_i    ( gnt_i        ),
    .wdata_o  ( data_agg_out ),
    .rdata_i  ( rdata_i      )
  );

end else begin : gen_unknown

  initial begin
    $fatal(1,"Unknown TCDM configuration %d.", Topology);
  end

end








initial begin
	assert(AddrMemWidth+NumOutLog2 <= AddrWidth) else
    $fatal(1,"Address not wide enough to accomodate the requested TCDM configuration.");
  assert(NumOut >= NumIn) else
    $fatal(1,"NumOut < NumIn is not supported.");
end


endmodule