data/full_repos/permissive/502135797/Lab10_April_27_2022/Code/FSM.v
1: b"%Error: data/full_repos/permissive/502135797/Lab10_April_27_2022/Code/FSM.v:11: Cannot find file containing module: 'debounce'\n    debounce debounce(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab10_April_27_2022/Code,data/full_repos/permissive/502135797/debounce\n             data/full_repos/permissive/502135797/Lab10_April_27_2022/Code,data/full_repos/permissive/502135797/debounce.v\n             data/full_repos/permissive/502135797/Lab10_April_27_2022/Code,data/full_repos/permissive/502135797/debounce.sv\n             debounce\n             debounce.v\n             debounce.sv\n             obj_dir/debounce\n             obj_dir/debounce.v\n             obj_dir/debounce.sv\n%Error: Exiting due to 1 error(s)\n"
module FSM(
    input[2:0] sel,
    input  fsmBTN,
    input  rst,
    input  clk,
    output reg [2:0] led1,
    output reg [2:0] led2
    );
    wire debouncedSig; 
    debounce debounce(
        .clk(clk), 
        .btnIN(fsmBTN),
        .outSig(debouncedSig)
    );
    reg state;
    reg next_state;

    always@(posedge clk)
    begin
        if (rst) 
            state = 0;
        else state = next_state;
    end
    
    always@(debouncedSig)
    begin
       next_state <= debouncedSig; 
    end
    
    always@(state or sel)
    begin
        if(state)
            led1 = sel;
        else
            led2 = sel;
    end
endmodule
module FSM(
    input[2:0] sel,
    input  fsmBTN,
    input  rst,
    input  clk,
    output reg [2:0] led1,
    output reg [2:0] led2
    );

    wire debouncedSig; 
    debounce debounce(
        .clk(clk), 
        .btnIN(fsmBTN),
        .outSig(debouncedSig)
    );
    reg state;
    reg next_state;

    always@(posedge clk)
    begin
        if (rst) 
            state = 0;
        else state = next_state;
    end
    
    always@(debouncedSig)
    begin
       next_state <= debouncedSig; 
    end
    
    always@(state or sel)
    begin
        if(state)
            led1 = sel;
        else
            led2 = sel;
    end
endmodule