data/full_repos/permissive/48007633/rhd2000_dm.v
1: b'%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:12: Cannot find include file: llLib.v\n`include "llLib.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v.v\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v.sv\n             llLib.v\n             llLib.v.v\n             llLib.v.sv\n             obj_dir/llLib.v\n             obj_dir/llLib.v.v\n             obj_dir/llLib.v.sv\n%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:175: syntax error, unexpected \'@\'\n            @(negedge nCs);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm.v:187: Unsupported: Ignoring delay on this delayed statement.\n            #delay;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:197: syntax error, unexpected \'@\'\n                @(posedge sClk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm.v:201: Unsupported: Ignoring delay on this delayed statement.\n                #delay;\n                ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:207: syntax error, unexpected \'@\'\n                @(negedge sClk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm.v:211: Unsupported: Ignoring delay on this delayed statement.\n                #delay;\n                ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:223: syntax error, unexpected \'@\'\n            @(posedge sClk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm.v:227: Unsupported: Ignoring delay on this delayed statement.\n            #delay;\n            ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm.v:233: syntax error, unexpected \'@\'\n            @(posedge nCs);\n            ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module rhd2000_dm #(
    parameter CHANNELS = 32,
    parameter REVISION = 1,
    parameter UNIPOLAR = 0,
    parameter ID       = 1
)(

    input   [(16 * CHANNELS) - 1:0] analogIn,
    
    input   nCs,
    input   mosi,
    input   sClk,

    output reg aux,
    output reg miso
);


    reg [7:0] ram [17:0];


    reg [7:0] rom [8:0];


    integer address = 0;
    reg [7:0] data = 0;

    

    initial begin


        rom[0] = "I";
        rom[1] = "N";
        rom[2] = "T";
        rom[3] = "A";
        rom[4] = "N";

        rom[5] = REVISION;

        rom[6] = UNIPOLAR;

        rom[7] = CHANNELS;

        rom[8] = ID;



        ram[0] = {  2'd3,
                    1'b0,
                    1'b1,
                    2'd3,
                    2'd2
                };

        ram[1] = {  1'bX,
                    1'b0,
                    6'd32
                };

        ram[2] = { 2'bXX, 6'd40
                };

        ram[3] = {  3'd0,
                    2'd0,
                    1'b0,
                    1'b0,
                    1'b0
                };

        ram[4] = {  1'b0,
                    1'b1,
                    1'b0,
                    1'b0,
                    4'd0
                };

        ram[5] = {  1'bX,
                    1'b0,
                    1'b0,
                    2'd0,
                    1'b0,
                    1'b0,
                    1'b0
                };

        ram[6] = 8'd0;

        ram[7] = {  2'bXX,
                    6'd0
                };

        ram[8] = {  1'b0,
                    1'bX,
                    6'd0
                };
        ram[9] = {  1'b0,
                    2'bXX,
                    5'd0
                };
        ram[10] = { 1'b0,
                    1'bX,
                    6'd0
                };
        ram[11] = { 1'b0,
                    2'bXX,
                    5'd0
                };
        ram[12] = { 1'b0,
                    1'bX,
                    6'd0
                };
        ram[13] = { 1'b0,
                    1'b0,
                    6'd0
                };

        ram[14] = 8'b1111_1111;
        ram[15] = 8'b1111_1111;
        ram[16] = 8'b1111_1111;
        ram[17] = 8'b1111_1111;
    end



    reg [15:0] iBuffer = 0;
    reg [15:0] oBuffer = 16'hXXXX;
    reg [15:0] out = 16'hXXXX;


    integer bCount = 15;


    integer delay = 0;


    reg convert = 0;
    integer cChannel = 0;


    reg calibrate = 0;
    integer calCounter = 0;

    

    always @(ram[3]) begin
        if (ram[3][1]) begin
            aux = 1'bZ;
        end else if (ram[3][0]) begin
            aux = 1'b1;
        end else begin
            aux = 1'b0;
        end
    end

    

    always begin
        while (1) begin


            @(negedge nCs);


            iBuffer = 0;

            if (convert) begin
                oBuffer = analogIn[(cChannel) * 16 +: 16];
                convert = 0;
            end
            

            delay = llLib.RANDRANGE (12, 6);
            #delay;


            bCount = 15;
            miso = out[bCount];


            repeat (15) begin
                

                @(posedge sClk);


                delay = llLib.RANDRANGE (12, 6);
                #delay;


                iBuffer[bCount] = mosi;


                @(negedge sClk);


                delay = llLib.RANDRANGE (12, 6);
                #delay;


                bCount = bCount - 1;


                miso = out[bCount];
            end




            @(posedge sClk);
            

            delay = llLib.RANDRANGE (12, 6);
            #delay;
            

            iBuffer[bCount] = mosi;


            @(posedge nCs);

            

            if (ram[4][7] == 1'b1) begin
                miso = 1'bZ;
            end else begin
                miso = 1'b0;
            end

            

            out = oBuffer;

            
            if (!calibrate) begin

                case (iBuffer[15:14])
                    

                    2'b00 : begin
                        cChannel = iBuffer >> 8;
                        convert = 1;
                    end


                    2'b01 : begin
                        if (iBuffer[13:8] == 6'b010101) begin
                            calCounter = 8;
                            calibrate = 1;
                        end

                        oBuffer = { ram[4][6], 15'd0 };
                    end


                    2'b10 : begin
                        address = iBuffer[13:8];
                        data = iBuffer[7:0];

                        if (address <= 17) begin
                            ram[address] = data;
                        end

                        oBuffer = { {8{1'b1}}, data };
                    end


                    2'b11 : begin
                        address = iBuffer[13:8];

                        if (address <= 17) begin
                            oBuffer = { 8'd0, ram[address] };
                        
                        end else if (address >= 40 && address <= 44) begin
                            oBuffer = { 8'd0, rom[address - 40] };
                        
                        end else if (address >= 60) begin
                            oBuffer = { 8'd0, rom[address - 55] };
                        end
                    end
                endcase
            
            end else begin
                calCounter = calCounter - 1;

                oBuffer = { ram[4][6], 15'd0 };


                iBuffer = { 2'b01, 14'd0 };

                if (calCounter == 0) begin
                    calibrate = 0;
                end
            end
        end
    end



 endmodule
module rhd2000_dm #(
    parameter CHANNELS = 32,
    parameter REVISION = 1,
    parameter UNIPOLAR = 0,
    parameter ID       = 1
)(

    input   [(16 * CHANNELS) - 1:0] analogIn,
    
    input   nCs,
    input   mosi,
    input   sClk,

    output reg aux,
    output reg miso
);



    reg [7:0] ram [17:0];


    reg [7:0] rom [8:0];


    integer address = 0;
    reg [7:0] data = 0;

    

    initial begin


        rom[0] = "I";
        rom[1] = "N";
        rom[2] = "T";
        rom[3] = "A";
        rom[4] = "N";

        rom[5] = REVISION;

        rom[6] = UNIPOLAR;

        rom[7] = CHANNELS;

        rom[8] = ID;



        ram[0] = {  2'd3,
                    1'b0,
                    1'b1,
                    2'd3,
                    2'd2
                };

        ram[1] = {  1'bX,
                    1'b0,
                    6'd32
                };

        ram[2] = { 2'bXX, 6'd40
                };

        ram[3] = {  3'd0,
                    2'd0,
                    1'b0,
                    1'b0,
                    1'b0
                };

        ram[4] = {  1'b0,
                    1'b1,
                    1'b0,
                    1'b0,
                    4'd0
                };

        ram[5] = {  1'bX,
                    1'b0,
                    1'b0,
                    2'd0,
                    1'b0,
                    1'b0,
                    1'b0
                };

        ram[6] = 8'd0;

        ram[7] = {  2'bXX,
                    6'd0
                };

        ram[8] = {  1'b0,
                    1'bX,
                    6'd0
                };
        ram[9] = {  1'b0,
                    2'bXX,
                    5'd0
                };
        ram[10] = { 1'b0,
                    1'bX,
                    6'd0
                };
        ram[11] = { 1'b0,
                    2'bXX,
                    5'd0
                };
        ram[12] = { 1'b0,
                    1'bX,
                    6'd0
                };
        ram[13] = { 1'b0,
                    1'b0,
                    6'd0
                };

        ram[14] = 8'b1111_1111;
        ram[15] = 8'b1111_1111;
        ram[16] = 8'b1111_1111;
        ram[17] = 8'b1111_1111;
    end



    reg [15:0] iBuffer = 0;
    reg [15:0] oBuffer = 16'hXXXX;
    reg [15:0] out = 16'hXXXX;


    integer bCount = 15;


    integer delay = 0;


    reg convert = 0;
    integer cChannel = 0;


    reg calibrate = 0;
    integer calCounter = 0;

    

    always @(ram[3]) begin
        if (ram[3][1]) begin
            aux = 1'bZ;
        end else if (ram[3][0]) begin
            aux = 1'b1;
        end else begin
            aux = 1'b0;
        end
    end

    

    always begin
        while (1) begin


            @(negedge nCs);


            iBuffer = 0;

            if (convert) begin
                oBuffer = analogIn[(cChannel) * 16 +: 16];
                convert = 0;
            end
            

            delay = llLib.RANDRANGE (12, 6);
            #delay;


            bCount = 15;
            miso = out[bCount];


            repeat (15) begin
                

                @(posedge sClk);


                delay = llLib.RANDRANGE (12, 6);
                #delay;


                iBuffer[bCount] = mosi;


                @(negedge sClk);


                delay = llLib.RANDRANGE (12, 6);
                #delay;


                bCount = bCount - 1;


                miso = out[bCount];
            end




            @(posedge sClk);
            

            delay = llLib.RANDRANGE (12, 6);
            #delay;
            

            iBuffer[bCount] = mosi;


            @(posedge nCs);

            

            if (ram[4][7] == 1'b1) begin
                miso = 1'bZ;
            end else begin
                miso = 1'b0;
            end

            

            out = oBuffer;

            
            if (!calibrate) begin

                case (iBuffer[15:14])
                    

                    2'b00 : begin
                        cChannel = iBuffer >> 8;
                        convert = 1;
                    end


                    2'b01 : begin
                        if (iBuffer[13:8] == 6'b010101) begin
                            calCounter = 8;
                            calibrate = 1;
                        end

                        oBuffer = { ram[4][6], 15'd0 };
                    end


                    2'b10 : begin
                        address = iBuffer[13:8];
                        data = iBuffer[7:0];

                        if (address <= 17) begin
                            ram[address] = data;
                        end

                        oBuffer = { {8{1'b1}}, data };
                    end


                    2'b11 : begin
                        address = iBuffer[13:8];

                        if (address <= 17) begin
                            oBuffer = { 8'd0, ram[address] };
                        
                        end else if (address >= 40 && address <= 44) begin
                            oBuffer = { 8'd0, rom[address - 40] };
                        
                        end else if (address >= 60) begin
                            oBuffer = { 8'd0, rom[address - 55] };
                        end
                    end
                endcase
            
            end else begin
                calCounter = calCounter - 1;

                oBuffer = { ram[4][6], 15'd0 };


                iBuffer = { 2'b01, 14'd0 };

                if (calCounter == 0) begin
                    calibrate = 0;
                end
            end
        end
    end



 endmodule