data/full_repos/permissive/506636840/rtl/pss/rtl/pss.sv
1: b'%Error: data/full_repos/permissive/506636840/rtl/pss/rtl/pss.sv:20: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/rtl/pss/rtl,data/full_repos/permissive/506636840/timescale.v\n             data/full_repos/permissive/506636840/rtl/pss/rtl,data/full_repos/permissive/506636840/timescale.v.v\n             data/full_repos/permissive/506636840/rtl/pss/rtl,data/full_repos/permissive/506636840/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/506636840/rtl/pss/rtl/pss.sv:21: Cannot find include file: gpio_defines.v\n`include "gpio_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module pss(
           input HCLK,
           input HRESETn,
           input[31:0] HADDR,
           input[1:0] HTRANS,
           input HWRITE,
           input[2:0] HSIZE,
           input[2:0] HBURST,
           input[3:0] HPROT,
           input[31:0] HWDATA,
           input HSEL,
           output [31:0] HRDATA,
           output HREADY,
           output [1:0] HRESP,

           output[7:0] spi_cs,
           output spi_clk,
           output spi_mosi,
           input spi_miso,

           input[31:0] gpi,
           output[31:0] gpo,
           output[31:0] gpoe,

           input rxd,
           output txd,

           output rts,
           input cts,
           output dtr,
           input dsr,
           input ri,
           input dcd,
           output baud,

           input[4:0] IREQ,
           output IRQ);

wire[31:0] PADDR;
wire[31:0] PWDATA;
wire PENABLE;
wire PWRITE;
wire[3:0] PSEL;
wire[31:0] SPI_PRDATA;
wire SPI_PREADY;
wire[31:0] GPIO_PRDATA;
wire GPIO_PREADY;
wire[31:0] ICPIT_PRDATA;
wire ICPIT_PREADY;
wire[31:0] UART_PRDATA;
wire UART_PREADY;
wire UART_IREQ;
wire SPI_IREQ;
wire GPIO_IREQ;
wire PIT_OUT;
wire WATCHDOG;

typedef logic[31:0] read_port_t[3];



ahb_apb_bridge
  #(.NO_OF_SLAVES(4),
    .SLAVE_START_ADDR_0(0),
    .SLAVE_END_ADDR_0(32'hFF),
    .SLAVE_START_ADDR_1(32'h100),
    .SLAVE_END_ADDR_1(32'h1FF),
    .SLAVE_START_ADDR_2(32'h200),
    .SLAVE_END_ADDR_2(32'h2FF),
    .SLAVE_START_ADDR_3(32'h300),
    .SLAVE_END_ADDR_3(32'h3FF)
    )
    U_BRIDGE
    (

     .HCLK(HCLK),
     .HRESETn(HRESETn),
     .HADDR(HADDR),
     .HTRANS(HTRANS),
     .HWRITE(HWRITE),
     .HSIZE(HSIZE),
     .HBURST(HBURST),
     .HPROT(HPROT),
     .HWDATA(HWDATA),
     .HSEL(HSEL),
     .HRDATA(HRDATA),
     .HREADY(HREADY),
     .HRESP(HRESP),

     .PADDR(PADDR),
     .PWDATA(PWDATA),
     .PENABLE(PENABLE),
     .PWRITE(PWRITE),
     .PSEL(PSEL),
     .PRDATA('{UART_PRDATA, ICPIT_PRDATA, GPIO_PRDATA, SPI_PRDATA}),
     .PREADY({UART_PREADY, ICPIT_PREADY, GPIO_PREADY, SPI_PREADY}),
     .PSLVERR(4'b0));

spi_top U_SPI(

    .PCLK(HCLK),
    .PRESETN(HRESETn),
    .PSEL(PSEL[0]),
    .PADDR(PADDR[4:0]),
    .PWDATA(PWDATA),
    .PRDATA(SPI_PRDATA),
    .PENABLE(PENABLE),
    .PREADY(SPI_PREADY),
    .PSLVERR(),
    .PWRITE(PWRITE),

    .IRQ(SPI_IREQ),

    .ss_pad_o(spi_cs),
    .sclk_pad_o(spi_clk),
    .mosi_pad_o(spi_mosi),
    .miso_pad_i(spi_miso)
);

gpio_top U_GPIO(

  .PCLK(HCLK),
  .PRESETN(HRESETn),
  .PSEL(PSEL[1]),
  .PADDR(PADDR[7:0]),
  .PWDATA(PWDATA),
  .PRDATA(GPIO_PRDATA),
  .PENABLE(PENABLE),
  .PREADY(GPIO_PREADY),
  .PSLVERR(),
  .PWRITE(PWRITE),

  .IRQ(GPIO_IREQ),
`ifdef GPIO_AUX_IMPLEMENT

  .aux_i({PIT_OUT, WATCHDOG, 30'h0}),
`endif

  .ext_pad_i(gpi),
  .ext_pad_o(gpo),
  .ext_padoe_o(gpoe)
`ifdef GPIO_CLKPAD
  , .clk_pad_i(1'b0)
`endif
);

icpit U_ICPIT(
              .PCLK(HCLK),
              .PRESETN(HRESETn),
              .PADDR(PADDR[4:2]),
              .PSEL(PSEL[2]),
              .PENABLE(PENABLE),
              .PWRITE(PWRITE),
              .PWDATA(PWDATA),
              .PRDATA(ICPIT_PRDATA),
              .PREADY(ICPIT_PREADY),

              .IRQ(IRQ),
              .IREQ({IREQ[4:0], UART_IREQ, GPIO_IREQ, SPI_IREQ}),

              .PIT_OUT(PIT_OUT),

              .WATCHDOG(WATCHDOG));

uart_top U_UART(

                .PCLK(HCLK),


                .PRESETn(HRESETn),
                .PADDR(PADDR),
                .PWDATA(PWDATA),
                .PRDATA(UART_PRDATA),
                .PWRITE(PWRITE),
                .PENABLE(PENABLE),
                .PSEL(PSEL[3]),
                .PREADY(UART_PREADY),
                .int_o(UART_IREQ),



                .stx_pad_o(txd),
                .srx_pad_i(rxd),


                .rts_pad_o(rts),
                .cts_pad_i(cts),
                .dtr_pad_o(dtr),
                .dsr_pad_i(dsr),
                .ri_pad_i(ri),
                .dcd_pad_i(dcd),
                .baud_o(baud)
                );

endmodule
module pss(
           input HCLK,
           input HRESETn,
           input[31:0] HADDR,
           input[1:0] HTRANS,
           input HWRITE,
           input[2:0] HSIZE,
           input[2:0] HBURST,
           input[3:0] HPROT,
           input[31:0] HWDATA,
           input HSEL,
           output [31:0] HRDATA,
           output HREADY,
           output [1:0] HRESP,

           output[7:0] spi_cs,
           output spi_clk,
           output spi_mosi,
           input spi_miso,

           input[31:0] gpi,
           output[31:0] gpo,
           output[31:0] gpoe,

           input rxd,
           output txd,

           output rts,
           input cts,
           output dtr,
           input dsr,
           input ri,
           input dcd,
           output baud,

           input[4:0] IREQ,
           output IRQ);


wire[31:0] PADDR;
wire[31:0] PWDATA;
wire PENABLE;
wire PWRITE;
wire[3:0] PSEL;
wire[31:0] SPI_PRDATA;
wire SPI_PREADY;
wire[31:0] GPIO_PRDATA;
wire GPIO_PREADY;
wire[31:0] ICPIT_PRDATA;
wire ICPIT_PREADY;
wire[31:0] UART_PRDATA;
wire UART_PREADY;
wire UART_IREQ;
wire SPI_IREQ;
wire GPIO_IREQ;
wire PIT_OUT;
wire WATCHDOG;

typedef logic[31:0] read_port_t[3];



ahb_apb_bridge
  #(.NO_OF_SLAVES(4),
    .SLAVE_START_ADDR_0(0),
    .SLAVE_END_ADDR_0(32'hFF),
    .SLAVE_START_ADDR_1(32'h100),
    .SLAVE_END_ADDR_1(32'h1FF),
    .SLAVE_START_ADDR_2(32'h200),
    .SLAVE_END_ADDR_2(32'h2FF),
    .SLAVE_START_ADDR_3(32'h300),
    .SLAVE_END_ADDR_3(32'h3FF)
    )
    U_BRIDGE
    (

     .HCLK(HCLK),
     .HRESETn(HRESETn),
     .HADDR(HADDR),
     .HTRANS(HTRANS),
     .HWRITE(HWRITE),
     .HSIZE(HSIZE),
     .HBURST(HBURST),
     .HPROT(HPROT),
     .HWDATA(HWDATA),
     .HSEL(HSEL),
     .HRDATA(HRDATA),
     .HREADY(HREADY),
     .HRESP(HRESP),

     .PADDR(PADDR),
     .PWDATA(PWDATA),
     .PENABLE(PENABLE),
     .PWRITE(PWRITE),
     .PSEL(PSEL),
     .PRDATA('{UART_PRDATA, ICPIT_PRDATA, GPIO_PRDATA, SPI_PRDATA}),
     .PREADY({UART_PREADY, ICPIT_PREADY, GPIO_PREADY, SPI_PREADY}),
     .PSLVERR(4'b0));

spi_top U_SPI(

    .PCLK(HCLK),
    .PRESETN(HRESETn),
    .PSEL(PSEL[0]),
    .PADDR(PADDR[4:0]),
    .PWDATA(PWDATA),
    .PRDATA(SPI_PRDATA),
    .PENABLE(PENABLE),
    .PREADY(SPI_PREADY),
    .PSLVERR(),
    .PWRITE(PWRITE),

    .IRQ(SPI_IREQ),

    .ss_pad_o(spi_cs),
    .sclk_pad_o(spi_clk),
    .mosi_pad_o(spi_mosi),
    .miso_pad_i(spi_miso)
);

gpio_top U_GPIO(

  .PCLK(HCLK),
  .PRESETN(HRESETn),
  .PSEL(PSEL[1]),
  .PADDR(PADDR[7:0]),
  .PWDATA(PWDATA),
  .PRDATA(GPIO_PRDATA),
  .PENABLE(PENABLE),
  .PREADY(GPIO_PREADY),
  .PSLVERR(),
  .PWRITE(PWRITE),

  .IRQ(GPIO_IREQ),
`ifdef GPIO_AUX_IMPLEMENT

  .aux_i({PIT_OUT, WATCHDOG, 30'h0}),
`endif

  .ext_pad_i(gpi),
  .ext_pad_o(gpo),
  .ext_padoe_o(gpoe)
`ifdef GPIO_CLKPAD
  , .clk_pad_i(1'b0)
`endif
);

icpit U_ICPIT(
              .PCLK(HCLK),
              .PRESETN(HRESETn),
              .PADDR(PADDR[4:2]),
              .PSEL(PSEL[2]),
              .PENABLE(PENABLE),
              .PWRITE(PWRITE),
              .PWDATA(PWDATA),
              .PRDATA(ICPIT_PRDATA),
              .PREADY(ICPIT_PREADY),

              .IRQ(IRQ),
              .IREQ({IREQ[4:0], UART_IREQ, GPIO_IREQ, SPI_IREQ}),

              .PIT_OUT(PIT_OUT),

              .WATCHDOG(WATCHDOG));

uart_top U_UART(

                .PCLK(HCLK),


                .PRESETn(HRESETn),
                .PADDR(PADDR),
                .PWDATA(PWDATA),
                .PRDATA(UART_PRDATA),
                .PWRITE(PWRITE),
                .PENABLE(PENABLE),
                .PSEL(PSEL[3]),
                .PREADY(UART_PREADY),
                .int_o(UART_IREQ),



                .stx_pad_o(txd),
                .srx_pad_i(rxd),


                .rts_pad_o(rts),
                .cts_pad_i(cts),
                .dtr_pad_o(dtr),
                .dsr_pad_i(dsr),
                .ri_pad_i(ri),
                .dcd_pad_i(dcd),
                .baud_o(baud)
                );

endmodule