data/full_repos/permissive/446997925/hw3/and_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/and_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/and_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw3/and_testbench.v:22: Unsupported or unknown PLI call: $monitor\n$monitor("time = %2d, input1 =%d, input2=%d out=%d " , $time, input1, input2, out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_testbench();

reg [31:0] input1, input2;
wire [31:0] out;
wire caryout;

and_32 test_and(out,input1,input2);

initial begin
input1 = 32'd0;
input2 = 32'd1;
#`DELAY;
input1 = 32'd4;
input2 = 32'd1;
#`DELAY;
end

initial
begin
$monitor("time = %2d, input1 =%d, input2=%d out=%d " , $time, input1, input2, out);
end


endmodule
module and_testbench();


reg [31:0] input1, input2;
wire [31:0] out;
wire caryout;

and_32 test_and(out,input1,input2);

initial begin
input1 = 32'd0;
input2 = 32'd1;
#`DELAY;
input1 = 32'd4;
input2 = 32'd1;
#`DELAY;
end

initial
begin
$monitor("time = %2d, input1 =%d, input2=%d out=%d " , $time, input1, input2, out);
end


endmodule