data/full_repos/permissive/445929378/multiplicative_inverse.v
1: b'%Error: data/full_repos/permissive/445929378/multiplicative_inverse.v:90: Cannot find file containing module: \'division\'\n   division div_r(\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/division\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/division.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/division.sv\n             division\n             division.v\n             division.sv\n             obj_dir/division\n             obj_dir/division.v\n             obj_dir/division.sv\n%Error: data/full_repos/permissive/445929378/multiplicative_inverse.v:104: Cannot find file containing module: \'multiplication_modulo\'\n   multiplication_modulo mult_t(\n   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445929378/multiplicative_inverse.v:119: Cannot find file containing module: \'multiplication_modulo\'\n   multiplication_modulo mult_r(\n   ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/445929378/multiplicative_inverse.v:173: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'r\' generates 64 bits.\n                                                                                 : ... In instance mult_inverse\n   if(r) begin\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/445929378/multiplicative_inverse.v:151: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'new_r\' generates 64 bits.\n                                                                                 : ... In instance mult_inverse\n       if(new_r) begin\n       ^~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module mult_inverse #(parameter SIZE = 64)
   (
    input wire 		     clk, rst,

    wire [SIZE-1 : 0] 	     input_base_tdata,
    input wire 		     input_base_tvalid,
    output wire 	     input_base_tready,
   

    wire [SIZE-1 : 0] 	     input_modulus_tdata,
    input wire 		     input_modulus_tvalid,
    output wire 	     input_modulus_tready,

    output wire [SIZE-1 : 0] output_tdata,
    output wire 	     output_tvalid, 
    input wire 		     output_tready
    );
   


   reg [SIZE-1 : 0] 	     t;
   reg [SIZE-1 : 0] 	     new_t;
   wire [SIZE-1 : 0] 	     t_wire;
   
   reg [SIZE-1 : 0] 	     r;
   reg [SIZE-1 : 0] 	     new_r;
   wire [SIZE-1 : 0] 	     r_wire;
   
   reg [SIZE-1 : 0] 	     quotient;
   wire [SIZE-1 : 0] 	     quotient_wire;
   
   reg [SIZE-1 : 0] 	     modulus;

   reg [SIZE-1 : 0] 	     output_reg = 1;
   wire [SIZE-1 : 0] 	     output_wire;
   reg 			     out_valid = 0;
   
   reg 			     data_read = 0;

   wire 		     input_rdy;

   reg 			     new_r_empty_reg;
   wire 		     new_r_empty;
   
   wire 		     t_valid;
   wire 		     t_ready;
   reg 			     t_ready_reg;
   
   wire 		     r_valid;
   wire 		     r_ready;
   reg 			     r_ready_reg;
   
   wire 		     modulus_read;

   wire 		     div_valid;   
   wire 		     div_ready;

   wire 		     iteration_finished;

   reg 			     reset;
   wire 		     rst_div;
   wire 		     rst_mult;

   reg 			     quotient_rdy_reg;
   wire 		     quotient_rdy;

   assign input_rdy = input_base_tvalid & input_modulus_tvalid;


   assign modulus_read = data_read;

   assign div_valid = data_read & (~rst_div);

   assign t_valid = div_ready & quotient_rdy;
   assign r_valid = div_ready & quotient_rdy;

   assign quotient_rdy = quotient_rdy_reg;
   
   assign iteration_finished = t_ready & r_ready;

   

   assign output_tdata = output_reg;
   assign output_tvalid = out_valid;
   assign rst_div = reset;
   assign rst_mult = reset;
   
   division div_r(
		  .clk(clk), 
		  .rst(rst_div),
		  .input_dividen_tdata(r),
		  .input_dividen_tvalid(div_valid),
		  .input_dividen_tready(),
		  .input_divisor_tdata(new_r),
		  .input_divisor_tvalid(div_valid),
		  .input_divisor_tready(),
		  .output_tdata(quotient_wire),
		  .output_tvalid(div_ready),
		  .output_tready(div_valid)
		  );
   
   multiplication_modulo mult_t(
				.clk(clk), 
				.rst(rst_mult), 
				.input_multiplier_tdata(quotient),
				.input_multiplier_tvalid(t_valid),
				.input_multiplier_tready(quotient_t_ready),
				.input_multiplicand_tdata(new_t), 
				.input_multiplicand_tvalid(t_valid),
				.input_modulus_tdata(modulus), 
				.input_modulus_tvalid(modulus_read), 
				.output_tdata(t_wire), 
				.output_tvalid(t_ready), 
				.output_tready(t_valid & quotient_t_ready)
				);

   multiplication_modulo mult_r(
				.clk(clk), 
				.rst(rst_mult), 
				.input_multiplier_tdata(quotient), 
				.input_multiplier_tvalid(r_valid),
				.input_multiplier_tready(quotient_r_ready),				
				.input_multiplicand_tdata(new_r), 
				.input_multiplicand_tvalid(r_valid), 
				.input_modulus_tdata(modulus), 
				.input_modulus_tvalid(modulus_read), 
				.output_tdata(r_wire), 
				.output_tvalid(r_ready), 
				.output_tready(r_valid)
				);
   always @(posedge clk)
     begin
	if(rst) begin
	   modulus <= 0;
	   data_read <= 0;
	   reset <= 1;
	end else begin
	   if(data_read == 0) begin
	      new_r <= input_base_tdata;
	      r <= input_modulus_tdata;
	      t <= 0;
	      new_t <= 1;
	      modulus <= input_modulus_tdata;
	      quotient_rdy_reg <= 0;

	      reset <= 0;
	      if(input_rdy) data_read <= 1;
	   end else begin
	      if(new_r) begin
		 if(r < new_r) begin
		    t <= new_t;
		    new_t <= t;
		    r <= new_r;
		    new_r <= r;
		    reset <= 1;
		 end
		 else begin
		    quotient_rdy_reg <= 1;
		    if(div_ready) quotient <= quotient_wire;
		    if(iteration_finished) begin
		       t <= new_t;
		       new_t <= t - t_wire;
		       r <= new_r;
		       new_r <= r - r_wire;
		       
		       reset <= 1;
		    end
		 end
	      end
	      else begin
		 if(r) begin
		    $display("not invertible");
		 end
		 if(t < 0) t <= t + modulus;
		 else begin
		    output_reg <= t;
		    out_valid <= 1;
		 end
	      end
	   end
	end
	if(reset) reset <= 0;
     end

endmodule
module mult_inverse #(parameter SIZE = 64)
   (
    input wire 		     clk, rst,

    wire [SIZE-1 : 0] 	     input_base_tdata,
    input wire 		     input_base_tvalid,
    output wire 	     input_base_tready,
   

    wire [SIZE-1 : 0] 	     input_modulus_tdata,
    input wire 		     input_modulus_tvalid,
    output wire 	     input_modulus_tready,

    output wire [SIZE-1 : 0] output_tdata,
    output wire 	     output_tvalid, 
    input wire 		     output_tready
    );

   


   reg [SIZE-1 : 0] 	     t;
   reg [SIZE-1 : 0] 	     new_t;
   wire [SIZE-1 : 0] 	     t_wire;
   
   reg [SIZE-1 : 0] 	     r;
   reg [SIZE-1 : 0] 	     new_r;
   wire [SIZE-1 : 0] 	     r_wire;
   
   reg [SIZE-1 : 0] 	     quotient;
   wire [SIZE-1 : 0] 	     quotient_wire;
   
   reg [SIZE-1 : 0] 	     modulus;

   reg [SIZE-1 : 0] 	     output_reg = 1;
   wire [SIZE-1 : 0] 	     output_wire;
   reg 			     out_valid = 0;
   
   reg 			     data_read = 0;

   wire 		     input_rdy;

   reg 			     new_r_empty_reg;
   wire 		     new_r_empty;
   
   wire 		     t_valid;
   wire 		     t_ready;
   reg 			     t_ready_reg;
   
   wire 		     r_valid;
   wire 		     r_ready;
   reg 			     r_ready_reg;
   
   wire 		     modulus_read;

   wire 		     div_valid;   
   wire 		     div_ready;

   wire 		     iteration_finished;

   reg 			     reset;
   wire 		     rst_div;
   wire 		     rst_mult;

   reg 			     quotient_rdy_reg;
   wire 		     quotient_rdy;

   assign input_rdy = input_base_tvalid & input_modulus_tvalid;


   assign modulus_read = data_read;

   assign div_valid = data_read & (~rst_div);

   assign t_valid = div_ready & quotient_rdy;
   assign r_valid = div_ready & quotient_rdy;

   assign quotient_rdy = quotient_rdy_reg;
   
   assign iteration_finished = t_ready & r_ready;

   

   assign output_tdata = output_reg;
   assign output_tvalid = out_valid;
   assign rst_div = reset;
   assign rst_mult = reset;
   
   division div_r(
		  .clk(clk), 
		  .rst(rst_div),
		  .input_dividen_tdata(r),
		  .input_dividen_tvalid(div_valid),
		  .input_dividen_tready(),
		  .input_divisor_tdata(new_r),
		  .input_divisor_tvalid(div_valid),
		  .input_divisor_tready(),
		  .output_tdata(quotient_wire),
		  .output_tvalid(div_ready),
		  .output_tready(div_valid)
		  );
   
   multiplication_modulo mult_t(
				.clk(clk), 
				.rst(rst_mult), 
				.input_multiplier_tdata(quotient),
				.input_multiplier_tvalid(t_valid),
				.input_multiplier_tready(quotient_t_ready),
				.input_multiplicand_tdata(new_t), 
				.input_multiplicand_tvalid(t_valid),
				.input_modulus_tdata(modulus), 
				.input_modulus_tvalid(modulus_read), 
				.output_tdata(t_wire), 
				.output_tvalid(t_ready), 
				.output_tready(t_valid & quotient_t_ready)
				);

   multiplication_modulo mult_r(
				.clk(clk), 
				.rst(rst_mult), 
				.input_multiplier_tdata(quotient), 
				.input_multiplier_tvalid(r_valid),
				.input_multiplier_tready(quotient_r_ready),				
				.input_multiplicand_tdata(new_r), 
				.input_multiplicand_tvalid(r_valid), 
				.input_modulus_tdata(modulus), 
				.input_modulus_tvalid(modulus_read), 
				.output_tdata(r_wire), 
				.output_tvalid(r_ready), 
				.output_tready(r_valid)
				);
   always @(posedge clk)
     begin
	if(rst) begin
	   modulus <= 0;
	   data_read <= 0;
	   reset <= 1;
	end else begin
	   if(data_read == 0) begin
	      new_r <= input_base_tdata;
	      r <= input_modulus_tdata;
	      t <= 0;
	      new_t <= 1;
	      modulus <= input_modulus_tdata;
	      quotient_rdy_reg <= 0;

	      reset <= 0;
	      if(input_rdy) data_read <= 1;
	   end else begin
	      if(new_r) begin
		 if(r < new_r) begin
		    t <= new_t;
		    new_t <= t;
		    r <= new_r;
		    new_r <= r;
		    reset <= 1;
		 end
		 else begin
		    quotient_rdy_reg <= 1;
		    if(div_ready) quotient <= quotient_wire;
		    if(iteration_finished) begin
		       t <= new_t;
		       new_t <= t - t_wire;
		       r <= new_r;
		       new_r <= r - r_wire;
		       
		       reset <= 1;
		    end
		 end
	      end
	      else begin
		 if(r) begin
		    $display("not invertible");
		 end
		 if(t < 0) t <= t + modulus;
		 else begin
		    output_reg <= t;
		    out_valid <= 1;
		 end
	      end
	   end
	end
	if(reset) reset <= 0;
     end

endmodule