data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/2014_q3fsm/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/2014_q3fsm,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/2014_q3fsm/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire s,
    input  wire w,
    output reg  z
);

  parameter STATE_A = 2'b00;
  parameter STATE_B = 2'b01;
  parameter STATE_C = 2'b10;
  parameter STATE_ILLEGAL = 2'b11;

  reg [1:0] state = STATE_A, next_state = STATE_A;
  reg [1:0] cyclecounter = 2'b0, next_cyclecounter = 2'b0;
  reg [1:0] bitcounter = 2'b0, next_bitcounter = 2'b0;
  reg flag = 1'b0;


  always @(*) begin
    casez ({
      s, state
    })
      {1'b0, STATE_A} : next_state = STATE_A;
      {1'b1, STATE_A} : next_state = STATE_B;
      {1'bz, STATE_B} : next_state = STATE_C;
      {1'bz, STATE_C} : next_state = STATE_C;

      default: next_state = STATE_ILLEGAL;
    endcase

    if (state == STATE_C) begin

      if (cyclecounter == 2'b10) next_cyclecounter = 2'b0;
      else next_cyclecounter = cyclecounter + 2'b1;


      if (cyclecounter == 2'b10 && bitcounter == 2'b10) flag = 1'b1;
      else flag = 1'b0;
    end else begin

      next_cyclecounter = 2'b0;
      flag = 1'b0;
    end

    if (state == STATE_B || state == STATE_C) begin

      if (next_cyclecounter == 2'b0) next_bitcounter = w;
      else next_bitcounter = bitcounter + w;
    end else next_bitcounter = 2'b0;

  end


  always @(posedge clk) begin
    if (reset) begin
      state <= STATE_A;
    end else if (clk) begin
      state <= next_state;
      cyclecounter <= next_cyclecounter;
      bitcounter <= next_bitcounter;
    end
  end


  always @(*) begin
    z = flag;
  end
endmodule
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire s,
    input  wire w,
    output reg  z
);


  parameter STATE_A = 2'b00;
  parameter STATE_B = 2'b01;
  parameter STATE_C = 2'b10;
  parameter STATE_ILLEGAL = 2'b11;

  reg [1:0] state = STATE_A, next_state = STATE_A;
  reg [1:0] cyclecounter = 2'b0, next_cyclecounter = 2'b0;
  reg [1:0] bitcounter = 2'b0, next_bitcounter = 2'b0;
  reg flag = 1'b0;


  always @(*) begin
    casez ({
      s, state
    })
      {1'b0, STATE_A} : next_state = STATE_A;
      {1'b1, STATE_A} : next_state = STATE_B;
      {1'bz, STATE_B} : next_state = STATE_C;
      {1'bz, STATE_C} : next_state = STATE_C;

      default: next_state = STATE_ILLEGAL;
    endcase

    if (state == STATE_C) begin

      if (cyclecounter == 2'b10) next_cyclecounter = 2'b0;
      else next_cyclecounter = cyclecounter + 2'b1;


      if (cyclecounter == 2'b10 && bitcounter == 2'b10) flag = 1'b1;
      else flag = 1'b0;
    end else begin

      next_cyclecounter = 2'b0;
      flag = 1'b0;
    end

    if (state == STATE_B || state == STATE_C) begin

      if (next_cyclecounter == 2'b0) next_bitcounter = w;
      else next_bitcounter = bitcounter + w;
    end else next_bitcounter = 2'b0;

  end


  always @(posedge clk) begin
    if (reset) begin
      state <= STATE_A;
    end else if (clk) begin
      state <= next_state;
      cyclecounter <= next_cyclecounter;
      bitcounter <= next_bitcounter;
    end
  end


  always @(*) begin
    z = flag;
  end
endmodule