data/full_repos/permissive/506562943/HDLBits/Verilog Language/Basics/wire.v
1: b'%Error: Cannot find file containing module: Language/Basics,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Basics,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Basics,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Basics,data/full_repos/permissive/506562943.sv\n             Language/Basics,data/full_repos/permissive/506562943\n             Language/Basics,data/full_repos/permissive/506562943.v\n             Language/Basics,data/full_repos/permissive/506562943.sv\n             obj_dir/Language/Basics,data/full_repos/permissive/506562943\n             obj_dir/Language/Basics,data/full_repos/permissive/506562943.v\n             obj_dir/Language/Basics,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Language/Basics/wire.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( input in, output out );

    assign out = in;

endmodule
module top_module( input in, output out );


    assign out = in;

endmodule