data/full_repos/permissive/420117502/Basic/7_Key_Debounce/Key_Debounce.v
1: b'%Warning-WIDTH: data/full_repos/permissive/420117502/Basic/7_Key_Debounce/Key_Debounce.v:49: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance Key_Debounce\n  c_stat<=1\'b0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Key_Debounce (
    input       clk         ,
    input       rst_n       ,
    input       key_in      ,
    output reg  key_out
);

parameter N = 32 ;
parameter FREQ = 50;
parameter MAX_TIME = 20;
localparam TIMER_MAX_VAL =   MAX_TIME * 1000 * FREQ  - 1 ;


reg key_in_d0;
wire key_in_flip;
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        key_in_d0 <= 1'b1;
    end
    else begin
        key_in_d0 <= key_in;
    end
end
assign key_in_flip = key_in ^ key_in_d0;


reg [N-1:0] cnt;
reg [1:0] c_stat;
reg [1:0] n_stat;
localparam idle     = 2'b0;
localparam flip     = 2'b1;
localparam counting = 2'd2;


always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		c_stat<=1'b0;
	else
		c_stat<=n_stat;
end

always@(*) begin
	case(c_stat)
        idle: begin
            n_stat = (key_in_flip==1'b1) ? flip : idle ;
        end
        flip: begin
            n_stat = (key_in_flip==1'b1) ? flip : counting ;
        end
        counting : begin
            if (key_in_flip == 1'b1) begin
                n_stat = flip;
            end
            else if (cnt == TIMER_MAX_VAL)
                n_stat = idle;
            else 
                n_stat = counting;
        end
    endcase
end


always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        cnt<='b0;
    end
    else begin
        case (c_stat)
            idle     : cnt <= 'b0       ;
            flip     : cnt <= 'b0       ;
            counting : cnt <=  cnt+1'b1 ;
        endcase
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        key_out <= key_in;
    end
    else begin
        if (cnt == TIMER_MAX_VAL)
            key_out <= key_in;
    end
end 

endmodule
module Key_Debounce (
    input       clk         ,
    input       rst_n       ,
    input       key_in      ,
    output reg  key_out
);


parameter N = 32 ;
parameter FREQ = 50;
parameter MAX_TIME = 20;
localparam TIMER_MAX_VAL =   MAX_TIME * 1000 * FREQ  - 1 ;


reg key_in_d0;
wire key_in_flip;
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        key_in_d0 <= 1'b1;
    end
    else begin
        key_in_d0 <= key_in;
    end
end
assign key_in_flip = key_in ^ key_in_d0;


reg [N-1:0] cnt;
reg [1:0] c_stat;
reg [1:0] n_stat;
localparam idle     = 2'b0;
localparam flip     = 2'b1;
localparam counting = 2'd2;


always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		c_stat<=1'b0;
	else
		c_stat<=n_stat;
end

always@(*) begin
	case(c_stat)
        idle: begin
            n_stat = (key_in_flip==1'b1) ? flip : idle ;
        end
        flip: begin
            n_stat = (key_in_flip==1'b1) ? flip : counting ;
        end
        counting : begin
            if (key_in_flip == 1'b1) begin
                n_stat = flip;
            end
            else if (cnt == TIMER_MAX_VAL)
                n_stat = idle;
            else 
                n_stat = counting;
        end
    endcase
end


always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        cnt<='b0;
    end
    else begin
        case (c_stat)
            idle     : cnt <= 'b0       ;
            flip     : cnt <= 'b0       ;
            counting : cnt <=  cnt+1'b1 ;
        endcase
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        key_out <= key_in;
    end
    else begin
        if (cnt == TIMER_MAX_VAL)
            key_out <= key_in;
    end
end 

endmodule