data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        A1 = 4\'b1111;A2 = 4\'b0000;s=0; #1000;\n                                       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        A1 = 4\'b1111;A2 = 4\'b0000;s=1; #1000;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        A1 = 4\'b0000;A2 = 4\'b1111;s=0; #1000;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        A1 = 4\'b0000;A2 = 4\'b1111;s=1; #1000;\n                                       ^\n%Error: data/full_repos/permissive/434840709/lab2/mux4bit/test_mux4bit2to1_tb.v:7: Cannot find file containing module: \'mux4bit2to1\'\n    mux4bit2to1 t(.a(A1), .b(A2), .s(a), .y(y));\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab2/mux4bit,data/full_repos/permissive/434840709/mux4bit2to1\n             data/full_repos/permissive/434840709/lab2/mux4bit,data/full_repos/permissive/434840709/mux4bit2to1.v\n             data/full_repos/permissive/434840709/lab2/mux4bit,data/full_repos/permissive/434840709/mux4bit2to1.sv\n             mux4bit2to1\n             mux4bit2to1.v\n             mux4bit2to1.sv\n             obj_dir/mux4bit2to1\n             obj_dir/mux4bit2to1.v\n             obj_dir/mux4bit2to1.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mux4bit2to1_tb();
    reg [3:0]A1;
    reg [3:0]A2;
    reg  s;
    wire a;
    wire [3:0]y;
    mux4bit2to1 t(.a(A1), .b(A2), .s(a), .y(y));
    assign a = s;
    initial
    begin
        A1 = 4'b1111;A2 = 4'b0000;s=0; #1000;
        A1 = 4'b1111;A2 = 4'b0000;s=1; #1000;
        A1 = 4'b0000;A2 = 4'b1111;s=0; #1000;
        A1 = 4'b0000;A2 = 4'b1111;s=1; #1000;
    end




endmodule
module test_mux4bit2to1_tb();

    reg [3:0]A1;
    reg [3:0]A2;
    reg  s;
    wire a;
    wire [3:0]y;
    mux4bit2to1 t(.a(A1), .b(A2), .s(a), .y(y));
    assign a = s;
    initial
    begin
        A1 = 4'b1111;A2 = 4'b0000;s=0; #1000;
        A1 = 4'b1111;A2 = 4'b0000;s=1; #1000;
        A1 = 4'b0000;A2 = 4'b1111;s=0; #1000;
        A1 = 4'b0000;A2 = 4'b1111;s=1; #1000;
    end




endmodule