data/full_repos/permissive/412929931/sine_wave_gen_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/412929931/sine_wave_gen_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/412929931/sine_wave_gen_tb.v:48: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sine_wave_gen_tb(

    );
    
    reg clk = 0;
    wire signed [15:0] sine_wave;
    reg [31:0] phase_step = 16'd50;
    reg rst = 0;
    

    always begin
        #2
        clk = ~clk;
    end
    
    integer i, sine_wave_file;

    
    initial begin
        sine_wave_file = $fopen("sine_wave_file.csv", "w");
        

        for(i=0; i<200000; i=i+1000)begin
            phase_step = i;
            repeat (100000)begin
                @(posedge clk);
                $fwrite(sine_wave_file,"%d,%d\n",sine_wave,phase_step);
            end 
        end
        $fclose(sine_wave_file);
        $stop;

    end
    
    

    sine_wave_gen_quarter sine_wave_gen_quarter_inst(
        .i_clk(clk),
        .i_rst(rst),
        .i_phase_step(phase_step),
        .o_gen_out(sine_wave)
    );
    
endmodule
module sine_wave_gen_tb(

    );

    
    reg clk = 0;
    wire signed [15:0] sine_wave;
    reg [31:0] phase_step = 16'd50;
    reg rst = 0;
    

    always begin
        #2
        clk = ~clk;
    end
    
    integer i, sine_wave_file;

    
    initial begin
        sine_wave_file = $fopen("sine_wave_file.csv", "w");
        

        for(i=0; i<200000; i=i+1000)begin
            phase_step = i;
            repeat (100000)begin
                @(posedge clk);
                $fwrite(sine_wave_file,"%d,%d\n",sine_wave,phase_step);
            end 
        end
        $fclose(sine_wave_file);
        $stop;

    end
    
    

    sine_wave_gen_quarter sine_wave_gen_quarter_inst(
        .i_clk(clk),
        .i_rst(rst),
        .i_phase_step(phase_step),
        .o_gen_out(sine_wave)
    );
    
endmodule