data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider/ClockDiv.v
data/verilator_xmls/c12e86ec-c52a-4fbe-87a9-8ecef017c0fe.xml
module ClockDiv(

			input wire 	CLK_I,

			output wire CLK_O

    );






	assign CLK_O = CLK_I;

endmodule
module ClockDiv(

			input wire 	CLK_I,

			output wire CLK_O

    );







	assign CLK_O = CLK_I;

endmodule