data/full_repos/permissive/445929378/mod_exp_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/mod_exp_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mod_exp_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mod_exp_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Error: data/full_repos/permissive/445929378/mod_exp_tb.v:24: Cannot find file containing module: \'mod_exp\'\n   mod_exp uut(\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mod_exp\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mod_exp.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mod_exp.sv\n             mod_exp\n             mod_exp.v\n             mod_exp.sv\n             obj_dir/mod_exp\n             obj_dir/mod_exp.v\n             obj_dir/mod_exp.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mod_exp_tb #(parameter SIZE = 64);


   reg clk;
   reg rst;
   reg [SIZE-1 : 0] base;
   reg 		    base_tvalid;
   reg [SIZE-1 : 0] power;
   reg 		    power_tvalid;
   reg [SIZE-1 : 0] modulus;
   reg 		    modulus_tvalid;
   reg 		    output_tready;


   wire 	    base_tready;
   wire 	    power_tready;
   wire [SIZE-1 : 0] output_tdata;
   wire 	     output_tvalid;
   


   mod_exp uut(
	       .clk(clk), 
	       .rst(rst), 
	       .input_base_tdata(base), 
	       .input_base_tvalid(base_tvalid), 
	       .input_base_tready(base_tready), 
	       .input_power_tdata(power), 
	       .input_power_tvalid(power_tvalid), 
	       .input_power_tready(power_tready),
	       .input_modulus_tdata(modulus), 
	       .input_modulus_tvalid(modulus_tvalid), 
	       .input_modulus_tready(modulus_tready), 
	       .output_tdata(output_tdata), 
	       .output_tvalid(output_tvalid), 
	       .output_tready(output_tready)
	       );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;

      base = 64'd9223372036854775337;
      base_tvalid = 1;

      power = 64'd9223372036854779249;
      power_tvalid = 1;

      modulus = 64'd9223372036854775433;
      modulus_tvalid = 1;
      
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule
module mod_exp_tb #(parameter SIZE = 64);



   reg clk;
   reg rst;
   reg [SIZE-1 : 0] base;
   reg 		    base_tvalid;
   reg [SIZE-1 : 0] power;
   reg 		    power_tvalid;
   reg [SIZE-1 : 0] modulus;
   reg 		    modulus_tvalid;
   reg 		    output_tready;


   wire 	    base_tready;
   wire 	    power_tready;
   wire [SIZE-1 : 0] output_tdata;
   wire 	     output_tvalid;
   


   mod_exp uut(
	       .clk(clk), 
	       .rst(rst), 
	       .input_base_tdata(base), 
	       .input_base_tvalid(base_tvalid), 
	       .input_base_tready(base_tready), 
	       .input_power_tdata(power), 
	       .input_power_tvalid(power_tvalid), 
	       .input_power_tready(power_tready),
	       .input_modulus_tdata(modulus), 
	       .input_modulus_tvalid(modulus_tvalid), 
	       .input_modulus_tready(modulus_tready), 
	       .output_tdata(output_tdata), 
	       .output_tvalid(output_tvalid), 
	       .output_tready(output_tready)
	       );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;

      base = 64'd9223372036854775337;
      base_tvalid = 1;

      power = 64'd9223372036854779249;
      power_tvalid = 1;

      modulus = 64'd9223372036854775433;
      modulus_tvalid = 1;
      
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule