data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:30: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign hour_shi=hour/10;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:31: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign hour_ge=hour%10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:32: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign min_shi=min/10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:33: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign min_ge=min%10;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:34: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign sec_shi=sec/10;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:35: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                                    : ... In instance time_top\nassign sec_ge=sec%10;\n             ^\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:38: Cannot find file containing module: \'clkDiv\'\nclkDiv U1(clk,clk190hz,clk3hz);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4,data/full_repos/permissive/434840709/clkDiv\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4,data/full_repos/permissive/434840709/clkDiv.v\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4,data/full_repos/permissive/434840709/clkDiv.sv\n             clkDiv\n             clkDiv.v\n             clkDiv.sv\n             obj_dir/clkDiv\n             obj_dir/clkDiv.v\n             obj_dir/clkDiv.sv\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:43: Cannot find file containing module: \'key_xd\'\nkey_xd Ukey_xd_hour_up(\n^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:49: Cannot find file containing module: \'key_xd\'\nkey_xd Ukey_xd_min_up(\n^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:55: Cannot find file containing module: \'key_xd\'\nkey_xd Ukey_sec_up(\n^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:61: Cannot find file containing module: \'key_xd\'\nkey_xd Ukey_enter(\n^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:67: Cannot find file containing module: \'time_set\'\ntime_set Utime_set(\n^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:78: Cannot find file containing module: \'time_calc\'\ntime_calc Utime_calc(\n^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:94: Cannot find file containing module: \'segMsg\'\nsegMsg UsegMsg_f(\n^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/time_top.v:100: Cannot find file containing module: \'segMsg\'\nsegMsg UsegMsg_b(\n^~~~~~\n%Error: Exiting due to 9 error(s), 6 warning(s)\n'
module time_top(
	input			clk,
	input			rst_n,
	input			key_start,
	input			key_hour_up,
	input			key_min_up,
	input			key_sec_up,
	input			key_enter,
	output 		[3:0] 	pos_f,
	output 		[7:0] 	seg_f,
	output 		[3:0] 	pos_b,
	output 		[7:0] 	seg_b,
	output			led
	);
wire	[7:0]	hour	;
wire	[7:0]	min		;
wire	[7:0]	sec		;
wire	[3:0]	hour_shi;
wire	[3:0]	hour_ge;
wire	[3:0]	min_shi;
wire	[3:0]	min_ge;
wire	[3:0]	sec_shi;
wire	[3:0]	sec_ge;
wire	[15:0]	databus_b;
wire	[15:0]	databus_f;
wire	[7:0]	hour_set	;	
wire	[7:0]	min_set	    ;
wire	[7:0]	sec_set	    ;

assign	hour_shi=hour/10;
assign	hour_ge=hour%10;
assign	min_shi=min/10;
assign	min_ge=min%10;
assign	sec_shi=sec/10;
assign	sec_ge=sec%10;
assign	databus_f={hour_shi,hour_ge,4'd10,min_shi};
assign	databus_b={min_ge,4'd10,sec_shi,sec_ge};
clkDiv U1(clk,clk190hz,clk3hz);




key_xd Ukey_xd_hour_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_hour_up),
	.key_out    (key_hour_up_out)
		);
key_xd Ukey_xd_min_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_min_up),
	.key_out    (key_min_up_out)
		);
key_xd Ukey_sec_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_sec_up),
	.key_out    (key_sec_up_out)
		);
key_xd Ukey_enter(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_enter),
	.key_out    (key_enter_out)
		);
time_set Utime_set(
	.clk				(clk),
	.rst_n				(rst_n),
	.key_hour_up		(key_hour_up_out),
	.key_min_up			(key_min_up_out ),
	.key_sec_up			(key_sec_up_out ),
	.key_enter			(key_enter_out),
	.hour_set			(hour_set	),
	.min_set			(min_set	),
	.sec_set		    (sec_set	)
	);
time_calc Utime_calc(
	.clk				(clk),
	.rst_n				(rst_n),
	.key_start			(key_start),
	.key_hour_up		(key_hour_up_out),
	.key_min_up			(key_min_up_out ),
	.key_sec_up			(key_sec_up_out ),
	.key_enter			(key_enter_out),
	.hour_set			(hour_set	),
	.min_set			(min_set	),
	.sec_set		    (sec_set	),
	.hour				(hour),
	.min				(min),
	.sec    			(sec),
	.led				(led)
	);
segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(databus_f),
	.pos			(pos_f),
	.seg            (seg_f)
    );
segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(databus_b),
	.pos			(pos_b),
	.seg            (seg_b)
    );
endmodule
module time_top(
	input			clk,
	input			rst_n,
	input			key_start,
	input			key_hour_up,
	input			key_min_up,
	input			key_sec_up,
	input			key_enter,
	output 		[3:0] 	pos_f,
	output 		[7:0] 	seg_f,
	output 		[3:0] 	pos_b,
	output 		[7:0] 	seg_b,
	output			led
	);

wire	[7:0]	hour	;
wire	[7:0]	min		;
wire	[7:0]	sec		;
wire	[3:0]	hour_shi;
wire	[3:0]	hour_ge;
wire	[3:0]	min_shi;
wire	[3:0]	min_ge;
wire	[3:0]	sec_shi;
wire	[3:0]	sec_ge;
wire	[15:0]	databus_b;
wire	[15:0]	databus_f;
wire	[7:0]	hour_set	;	
wire	[7:0]	min_set	    ;
wire	[7:0]	sec_set	    ;

assign	hour_shi=hour/10;
assign	hour_ge=hour%10;
assign	min_shi=min/10;
assign	min_ge=min%10;
assign	sec_shi=sec/10;
assign	sec_ge=sec%10;
assign	databus_f={hour_shi,hour_ge,4'd10,min_shi};
assign	databus_b={min_ge,4'd10,sec_shi,sec_ge};
clkDiv U1(clk,clk190hz,clk3hz);




key_xd Ukey_xd_hour_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_hour_up),
	.key_out    (key_hour_up_out)
		);
key_xd Ukey_xd_min_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_min_up),
	.key_out    (key_min_up_out)
		);
key_xd Ukey_sec_up(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_sec_up),
	.key_out    (key_sec_up_out)
		);
key_xd Ukey_enter(
	.clk		(clk),
	.rst_n		(rst_n),
	.key_in		(key_enter),
	.key_out    (key_enter_out)
		);
time_set Utime_set(
	.clk				(clk),
	.rst_n				(rst_n),
	.key_hour_up		(key_hour_up_out),
	.key_min_up			(key_min_up_out ),
	.key_sec_up			(key_sec_up_out ),
	.key_enter			(key_enter_out),
	.hour_set			(hour_set	),
	.min_set			(min_set	),
	.sec_set		    (sec_set	)
	);
time_calc Utime_calc(
	.clk				(clk),
	.rst_n				(rst_n),
	.key_start			(key_start),
	.key_hour_up		(key_hour_up_out),
	.key_min_up			(key_min_up_out ),
	.key_sec_up			(key_sec_up_out ),
	.key_enter			(key_enter_out),
	.hour_set			(hour_set	),
	.min_set			(min_set	),
	.sec_set		    (sec_set	),
	.hour				(hour),
	.min				(min),
	.sec    			(sec),
	.led				(led)
	);
segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(databus_f),
	.pos			(pos_f),
	.seg            (seg_f)
    );
segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(databus_b),
	.pos			(pos_b),
	.seg            (seg_b)
    );
endmodule