data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/multiple_blocking.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/multiple_blocking.v:16: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                       : ... In instance multiple_blocking\n      c = ~din;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/multiple_blocking.v:18: Bit extraction of var[31:0] requires 5 bit index, not 6 bits.\n                                                                                                                       : ... In instance multiple_blocking\n      dout[a*b+:SLICE] = c;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/multiple_blocking.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'c\' generates 3 bits.\n                                                                                                                       : ... In instance multiple_blocking\n      dout[a*b+:SLICE] = c;\n                       ^\n%Error: Exiting due to 3 warning(s)\n'
module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);
   
   localparam SLICE = WIDTH/(SELW**2);
   reg [CTRLW:0] 	   a;
   reg [SELW-1:0] 	   b;
   reg [DINW:0] 	   c;
   always @(posedge clk) begin
      a = ctrl + 1;
      b = sel - 1;
      c = ~din;
      dout = dout + 1;
      dout[a*b+:SLICE] = c;
   end
endmodule
module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);

   
   localparam SLICE = WIDTH/(SELW**2);
   reg [CTRLW:0] 	   a;
   reg [SELW-1:0] 	   b;
   reg [DINW:0] 	   c;
   always @(posedge clk) begin
      a = ctrl + 1;
      b = sel - 1;
      c = ~din;
      dout = dout + 1;
      dout[a*b+:SLICE] = c;
   end
endmodule