data/full_repos/permissive/514217463/core/rtl/frequency_divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:16: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                    : ... In instance frequency_divider\n          cnt_pos  <= 10\'d0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:37: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                    : ... In instance frequency_divider\n              cnt_pos <= 10\'d0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:30: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance frequency_divider\n            if(cnt_pos <= (N-2\'d2))\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:50: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                    : ... In instance frequency_divider\n          cnt_neg <= 10\'d0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:71: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                    : ... In instance frequency_divider\n              cnt_neg <= 10\'d0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:64: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance frequency_divider\n            if(cnt_neg <= (N-2\'d2))\n                            ^\n%Warning-CMPCONST: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:24: Comparison is constant due to limited range\n                                                                                       : ... In instance frequency_divider\n            if(cnt_pos <= ((N-1\'d1)/2)- 1\'d1)\n                       ^~\n%Warning-CMPCONST: data/full_repos/permissive/514217463/core/rtl/frequency_divider.v:58: Comparison is constant due to limited range\n                                                                                       : ... In instance frequency_divider\n            if(cnt_neg <= ((N-1\'d1)/2)- 1\'d1)\n                       ^~\n%Error: Exiting due to 8 warning(s)\n'
module frequency_divider(
  input	 clk_in,
  input	 rst,
  output clk_out
);

  parameter	N = 2;
  parameter	WIDTH = 6;
  
  reg clk_pos;
  reg [WIDTH:0] cnt_pos;
  always @(posedge clk_in or posedge rst)
    begin
      if(rst)
        begin
          cnt_pos		<=	10'd0;
          clk_pos	<=	1'd0;
        end
      else
        begin
          if(N==2)
            clk_pos <= ~clk_pos;
          else
            if(cnt_pos <= ((N-1'd1)/2)- 1'd1)
              begin
                cnt_pos <= cnt_pos + 1'd1;
                clk_pos <= 1'd1;
              end
          else
            if(cnt_pos <= (N-2'd2))
              begin
                cnt_pos <= cnt_pos + 1'd1;
                clk_pos <= 1'd0;
              end
          else
            begin
              cnt_pos <= 10'd0;
              clk_pos <= 1'd0;
            end
        end
    end


  reg clk_neg;
  reg [WIDTH:0] cnt_neg;
  always @(negedge clk_in or posedge rst)
    begin
      if(rst)
        begin
          cnt_neg <= 10'd0;
          clk_neg <= 1'd0;
        end
      else
        begin
          if(N==2)
            clk_neg <= ~clk_neg;
          else
            if(cnt_neg <= ((N-1'd1)/2)- 1'd1)
              begin
                cnt_neg <= cnt_neg + 1'd1;
                clk_neg <= 1'd1;
              end
          else
            if(cnt_neg <= (N-2'd2))
              begin
                cnt_neg <= cnt_neg + 1'd1;
                clk_neg <= 1'd0;
              end
          else
            begin
              cnt_neg <= 10'd0;
              clk_neg <= 1'd0;
            end
        end
    end	

  assign	clk_out = clk_pos | clk_neg;	

endmodule
module frequency_divider(
  input	 clk_in,
  input	 rst,
  output clk_out
);


  parameter	N = 2;
  parameter	WIDTH = 6;
  
  reg clk_pos;
  reg [WIDTH:0] cnt_pos;
  always @(posedge clk_in or posedge rst)
    begin
      if(rst)
        begin
          cnt_pos		<=	10'd0;
          clk_pos	<=	1'd0;
        end
      else
        begin
          if(N==2)
            clk_pos <= ~clk_pos;
          else
            if(cnt_pos <= ((N-1'd1)/2)- 1'd1)
              begin
                cnt_pos <= cnt_pos + 1'd1;
                clk_pos <= 1'd1;
              end
          else
            if(cnt_pos <= (N-2'd2))
              begin
                cnt_pos <= cnt_pos + 1'd1;
                clk_pos <= 1'd0;
              end
          else
            begin
              cnt_pos <= 10'd0;
              clk_pos <= 1'd0;
            end
        end
    end


  reg clk_neg;
  reg [WIDTH:0] cnt_neg;
  always @(negedge clk_in or posedge rst)
    begin
      if(rst)
        begin
          cnt_neg <= 10'd0;
          clk_neg <= 1'd0;
        end
      else
        begin
          if(N==2)
            clk_neg <= ~clk_neg;
          else
            if(cnt_neg <= ((N-1'd1)/2)- 1'd1)
              begin
                cnt_neg <= cnt_neg + 1'd1;
                clk_neg <= 1'd1;
              end
          else
            if(cnt_neg <= (N-2'd2))
              begin
                cnt_neg <= cnt_neg + 1'd1;
                clk_neg <= 1'd0;
              end
          else
            begin
              cnt_neg <= 10'd0;
              clk_neg <= 1'd0;
            end
        end
    end	

  assign	clk_out = clk_pos | clk_neg;	

endmodule