data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v
1: b'%Warning-WIDTH: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:18: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'audio_l\' generates 1 bits.\n                                                                                                    : ... In instance user_module_341424636358034002\nassign io_out[4:0] = audio_l;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'audio_r\' generates 1 bits.\n                                                                                                    : ... In instance user_module_341424636358034002\nassign io_out[7:5] = audio_r;\n                   ^\n%Error-PROCASSWIRE: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:32: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'audio_l\'\n                                                                                                        : ... In instance user_module_341424636358034002\n    audio_l = 0;\n    ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:33: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'audio_r\'\n                                                                                                        : ... In instance user_module_341424636358034002\n    audio_r = 0;  \n    ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:50: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'audio_l\'\n                                                                                                        : ... In instance user_module_341424636358034002\n        audio_l <= ~audio_l;\n        ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/520428138/verilog/rtl/user_module_341424636358034002.v:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'audio_r\'\n                                                                                                        : ... In instance user_module_341424636358034002\n        audio_r <= ~audio_r;\n        ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module user_module_341424636358034002(
  input [7:0] io_in, 
  output [7:0] io_out
);


wire clk;
assign clk = io_in[0];

wire audio_l, audio_r;

assign io_out[4:0] = audio_l;
assign io_out[7:5] = audio_r;

parameter TONE_A4 = 440/100;
parameter TONE_B4 = 494/100;
parameter TONE_C5 = 523/100;
parameter TONE_D5 = 587/100;
parameter TONE_E5 = 659/100;
parameter TONE_F5 = 698/100;
parameter TONE_G5 = 783/100;

reg [25:0] counter;
initial 
begin
    audio_l = 0;
    audio_r = 0;  
    counter = 0;
end

always @(posedge clk) 
    if(counter==26'b0) counter <= ( io_in[7] ? TONE_A4-1 : 
                               io_in[6] ? TONE_B4-1 : 
                               io_in[5] ? TONE_C5-1 : 
                               io_in[4] ? TONE_D5-1 : 
                               io_in[3] ? TONE_D5-1 : 
                               io_in[2] ? TONE_F5-1 : 
                               io_in[1] ? TONE_G5-1 : 
                               100); else counter <= counter-1;

always @(posedge clk) 
    if(counter==0)
    begin
        audio_l <= ~audio_l;
        audio_r <= ~audio_r;
    end

endmodule
module user_module_341424636358034002(
  input [7:0] io_in, 
  output [7:0] io_out
);



wire clk;
assign clk = io_in[0];

wire audio_l, audio_r;

assign io_out[4:0] = audio_l;
assign io_out[7:5] = audio_r;

parameter TONE_A4 = 440/100;
parameter TONE_B4 = 494/100;
parameter TONE_C5 = 523/100;
parameter TONE_D5 = 587/100;
parameter TONE_E5 = 659/100;
parameter TONE_F5 = 698/100;
parameter TONE_G5 = 783/100;

reg [25:0] counter;
initial 
begin
    audio_l = 0;
    audio_r = 0;  
    counter = 0;
end

always @(posedge clk) 
    if(counter==26'b0) counter <= ( io_in[7] ? TONE_A4-1 : 
                               io_in[6] ? TONE_B4-1 : 
                               io_in[5] ? TONE_C5-1 : 
                               io_in[4] ? TONE_D5-1 : 
                               io_in[3] ? TONE_D5-1 : 
                               io_in[2] ? TONE_F5-1 : 
                               io_in[1] ? TONE_G5-1 : 
                               100); else counter <= counter-1;

always @(posedge clk) 
    if(counter==0)
    begin
        audio_l <= ~audio_l;
        audio_r <= ~audio_r;
    end

endmodule