data/full_repos/permissive/515100461/sequential/fetch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=64\'d32;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/fetch_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/515100461/sequential/fetch_tb.v:44: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d,PC=%d,icode=%b,ifun=%b,rA=%b,rB=%b,valC=%d,valP=%d\\n",clk,PC,icode,ifun,rA,rB,valC,valP);\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fetch_testbench();

reg clk;
reg [63:0] PC;

wire [3:0] icode,ifun,rA,rB;
wire [63:0] valC,valP;

fetch uut(clk,PC,icode,ifun,rA,rB,valP,valC);

initial begin 
    clk=0;
    PC=64'd0;

    #10 clk=~clk;PC=64'd32;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
  end 
  
  initial 
		$monitor("clk=%d,PC=%d,icode=%b,ifun=%b,rA=%b,rB=%b,valC=%d,valP=%d\n",clk,PC,icode,ifun,rA,rB,valC,valP);
endmodule
module fetch_testbench();


reg clk;
reg [63:0] PC;

wire [3:0] icode,ifun,rA,rB;
wire [63:0] valC,valP;

fetch uut(clk,PC,icode,ifun,rA,rB,valP,valC);

initial begin 
    clk=0;
    PC=64'd0;

    #10 clk=~clk;PC=64'd32;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
  end 
  
  initial 
		$monitor("clk=%d,PC=%d,icode=%b,ifun=%b,rA=%b,rB=%b,valC=%d,valP=%d\n",clk,PC,icode,ifun,rA,rB,valC,valP);
endmodule