data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:12: Define or directive not defined: \'`OPCODE_COUNT\'\n    input  wire [`OPCODE_COUNT-1:0] opcode_type    ,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:16: Define or directive not defined: \'`SIGNAL_COUNT\'\n    input  wire [`SIGNAL_COUNT-1:0] signals        ,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:49: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n        signals[`CONTROL_REG_RR_READ] ?\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        signals[`CONTROL_REG_RR_READ] ?\n                                    ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:50: Define or directive not defined: \'`TYPE_LD_X\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XH :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:50: Define or directive not defined: \'`TYPE_ST_X\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XH :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:50: Define or directive not defined: \'`XH\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XH :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:51: Define or directive not defined: \'`TYPE_LD_Y\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YH :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:51: Define or directive not defined: \'`TYPE_ST_Y\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YH :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:51: Define or directive not defined: \'`YH\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YH :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:52: Define or directive not defined: \'`TYPE_LD_Z\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZH :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:52: Define or directive not defined: \'`TYPE_ST_Z\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZH :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:52: Define or directive not defined: \'`ZH\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZH :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:57: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n        signals[`CONTROL_REG_RD_READ] ?\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        signals[`CONTROL_REG_RD_READ] ?\n                                    ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:58: Define or directive not defined: \'`TYPE_LD_X\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XL :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:58: Define or directive not defined: \'`TYPE_ST_X\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XL :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:58: Define or directive not defined: \'`XL\'\n        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XL :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:59: Define or directive not defined: \'`TYPE_LD_Y\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YL :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:59: Define or directive not defined: \'`TYPE_ST_Y\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YL :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:59: Define or directive not defined: \'`YL\'\n        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YL :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:60: Define or directive not defined: \'`TYPE_LD_Z\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZL :\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:60: Define or directive not defined: \'`TYPE_ST_Z\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZL :\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:60: Define or directive not defined: \'`ZL\'\n        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZL :\n                                                                   ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:62: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n        signals[`CONTROL_REG_RD_WRITE] ?\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:68: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :\n                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :\n                                                  ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:71: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_we = signals[`CONTROL_REG_RD_READ] ? 1\'b0 :\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:71: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_we = signals[`CONTROL_REG_RD_READ] ? 1\'b0 :\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:72: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n        signals[`CONTROL_REG_RD_WRITE] ? 1\'b1 : 1\'bx;\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:73: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_we = signals[`CONTROL_REG_RR_READ] ? 1\'b0 : 1\'bx;\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:73: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_we = signals[`CONTROL_REG_RR_READ] ? 1\'b0 : 1\'bx;\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:75: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_oe = signals[`CONTROL_REG_RR_READ] ? 1\'b1 : 1\'bx;\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_oe = signals[`CONTROL_REG_RR_READ] ? 1\'b1 : 1\'bx;\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:76: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_oe = signals[`CONTROL_REG_RD_READ] ? 1\'b1 : 1\'bx;\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_oe = signals[`CONTROL_REG_RD_READ] ? 1\'b1 : 1\'bx;\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:78: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_cs = signals[`CONTROL_REG_RR_READ];\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_cs = signals[`CONTROL_REG_RR_READ];\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:79: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_cs = signals[`CONTROL_REG_RD_READ] ||\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:79: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_cs = signals[`CONTROL_REG_RD_READ] ||\n                                               ^\n%Error: data/full_repos/permissive/418819021/lab-05/reg_file_interface_unit.v:80: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n        signals[`CONTROL_REG_RD_WRITE];\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 42 error(s)\n'
module reg_file_interface_unit #(
    parameter INSTR_WIDTH  = 16,
    parameter DATA_WIDTH   = 8 ,
    parameter R_ADDR_WIDTH = 5
) (
    input  wire [`OPCODE_COUNT-1:0] opcode_type    ,
    input  wire [   DATA_WIDTH-1:0] writeback_value,
    input  wire [ R_ADDR_WIDTH-1:0] opcode_rd      ,
    input  wire [ R_ADDR_WIDTH-1:0] opcode_rr      ,
    input  wire [`SIGNAL_COUNT-1:0] signals        ,
    output wire [ R_ADDR_WIDTH-1:0] rr_addr        ,
    output wire [ R_ADDR_WIDTH-1:0] rd_addr        ,
    inout  wire [   DATA_WIDTH-1:0] rr_data        ,
    inout  wire [   DATA_WIDTH-1:0] rd_data        ,
    output wire                     rr_cs          ,
    output wire                     rd_cs          ,
    output wire                     rr_we          ,
    output wire                     rd_we          ,
    output wire                     rr_oe          ,
    output wire                     rd_oe
);





    wire [R_ADDR_WIDTH-1:0] internal_rr_addr;
    wire [R_ADDR_WIDTH-1:0] internal_rd_addr;


    assign internal_rr_addr =
        signals[`CONTROL_REG_RR_READ] ?
        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XH :
        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YH :
        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZH :
        opcode_rr :
        {R_ADDR_WIDTH{1'bx}};

    assign internal_rd_addr =
        signals[`CONTROL_REG_RD_READ] ?
        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XL :
        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YL :
        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZL :
        opcode_rd :
        signals[`CONTROL_REG_RD_WRITE] ?
        opcode_rd :
        {R_ADDR_WIDTH{1'bx}};


    assign rr_data = {DATA_WIDTH{1'bz}};
    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :
        {DATA_WIDTH{1'bz}};

    assign rd_we = signals[`CONTROL_REG_RD_READ] ? 1'b0 :
        signals[`CONTROL_REG_RD_WRITE] ? 1'b1 : 1'bx;
    assign rr_we = signals[`CONTROL_REG_RR_READ] ? 1'b0 : 1'bx;

    assign rr_oe = signals[`CONTROL_REG_RR_READ] ? 1'b1 : 1'bx;
    assign rd_oe = signals[`CONTROL_REG_RD_READ] ? 1'b1 : 1'bx;

    assign rr_cs = signals[`CONTROL_REG_RR_READ];
    assign rd_cs = signals[`CONTROL_REG_RD_READ] ||
        signals[`CONTROL_REG_RD_WRITE];

    assign rr_addr = (rr_cs) ? internal_rr_addr : {R_ADDR_WIDTH{1'bx}};
    assign rd_addr = (rd_cs) ? internal_rd_addr : {R_ADDR_WIDTH{1'bx}};

endmodule
module reg_file_interface_unit #(
    parameter INSTR_WIDTH  = 16,
    parameter DATA_WIDTH   = 8 ,
    parameter R_ADDR_WIDTH = 5
) (
    input  wire [`OPCODE_COUNT-1:0] opcode_type    ,
    input  wire [   DATA_WIDTH-1:0] writeback_value,
    input  wire [ R_ADDR_WIDTH-1:0] opcode_rd      ,
    input  wire [ R_ADDR_WIDTH-1:0] opcode_rr      ,
    input  wire [`SIGNAL_COUNT-1:0] signals        ,
    output wire [ R_ADDR_WIDTH-1:0] rr_addr        ,
    output wire [ R_ADDR_WIDTH-1:0] rd_addr        ,
    inout  wire [   DATA_WIDTH-1:0] rr_data        ,
    inout  wire [   DATA_WIDTH-1:0] rd_data        ,
    output wire                     rr_cs          ,
    output wire                     rd_cs          ,
    output wire                     rr_we          ,
    output wire                     rd_we          ,
    output wire                     rr_oe          ,
    output wire                     rd_oe
);






    wire [R_ADDR_WIDTH-1:0] internal_rr_addr;
    wire [R_ADDR_WIDTH-1:0] internal_rd_addr;


    assign internal_rr_addr =
        signals[`CONTROL_REG_RR_READ] ?
        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XH :
        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YH :
        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZH :
        opcode_rr :
        {R_ADDR_WIDTH{1'bx}};

    assign internal_rd_addr =
        signals[`CONTROL_REG_RD_READ] ?
        (opcode_type == `TYPE_LD_X || opcode_type == `TYPE_ST_X) ? `XL :
        (opcode_type == `TYPE_LD_Y || opcode_type == `TYPE_ST_Y) ? `YL :
        (opcode_type == `TYPE_LD_Z || opcode_type == `TYPE_ST_Z) ? `ZL :
        opcode_rd :
        signals[`CONTROL_REG_RD_WRITE] ?
        opcode_rd :
        {R_ADDR_WIDTH{1'bx}};


    assign rr_data = {DATA_WIDTH{1'bz}};
    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :
        {DATA_WIDTH{1'bz}};

    assign rd_we = signals[`CONTROL_REG_RD_READ] ? 1'b0 :
        signals[`CONTROL_REG_RD_WRITE] ? 1'b1 : 1'bx;
    assign rr_we = signals[`CONTROL_REG_RR_READ] ? 1'b0 : 1'bx;

    assign rr_oe = signals[`CONTROL_REG_RR_READ] ? 1'b1 : 1'bx;
    assign rd_oe = signals[`CONTROL_REG_RD_READ] ? 1'b1 : 1'bx;

    assign rr_cs = signals[`CONTROL_REG_RR_READ];
    assign rd_cs = signals[`CONTROL_REG_RD_READ] ||
        signals[`CONTROL_REG_RD_WRITE];

    assign rr_addr = (rr_cs) ? internal_rr_addr : {R_ADDR_WIDTH{1'bx}};
    assign rd_addr = (rd_cs) ? internal_rd_addr : {R_ADDR_WIDTH{1'bx}};

endmodule