data/full_repos/permissive/445357518/shifter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/shifter_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/445357518/shifter_tb.v:8: Cannot find file containing module: \'shifter\'\n shifter DUT(in, shift, out);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/shifter\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/shifter.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/shifter.sv\n             shifter\n             shifter.v\n             shifter.sv\n             obj_dir/shifter\n             obj_dir/shifter.v\n             obj_dir/shifter.sv\n%Error: Exiting due to 1 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shifter_tb;
	reg [15:0] in;
	reg[1:0] shift;
	wire[15:0] out;
	reg err;
	

	shifter DUT(in, shift, out);

	initial begin

		err = 1'b0;



		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b01;
		#5;
		if (out !== 16'b1110000110011110) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1110000110011110);
			err = 1'b1;
		end
		#5
		

		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b10;
		#5;
		if (out !== 16'b0111100001100111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0111100001100111);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b11;
		#5;
		if (out !== 16'b1111100001100111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111100001100111);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b00;
		#5;
		if (out !== 16'b1111000011001111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111000011001111);
			err = 1'b1;
		end
		#5
		

		$display("REPEATING TESTING SEQUENCE FOR 16'b1111111111111111");

		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b01;
		#5;
		if (out !== 16'b1111111111111110) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111110);
			err = 1'b1;
		end
		#5
		

		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b10;
		#5;
		if (out !== 16'b0111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0111111111111111);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b11;
		#5;
		if (out !== 16'b1111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111111);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b00;
		#5;
		if (out !== 16'b1111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111111);
			err = 1'b1;
		end
		#5


		$display("REPEATING TESTING SEQUENCE FOR 0");

		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b01;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b10;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b11;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'd0;
		shift = 2'b00;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("REPEATING TESTING SEQUENCE FOR 1");


		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b0000000000000001; 
		shift = 2'b01;
		#5;
		if (out !== 16'b0000000000000010) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0000000000000010);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b10;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b11;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b00;
		#5;
		if (out !== 16'b0000000000000001) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0000000000000001);
			err = 1'b1;
		end
		#5

		if (~err) $display("PASSED");
		else $display("FAILED");
	
	end
endmodule
module shifter_tb;

	reg [15:0] in;
	reg[1:0] shift;
	wire[15:0] out;
	reg err;
	

	shifter DUT(in, shift, out);

	initial begin

		err = 1'b0;



		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b01;
		#5;
		if (out !== 16'b1110000110011110) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1110000110011110);
			err = 1'b1;
		end
		#5
		

		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b10;
		#5;
		if (out !== 16'b0111100001100111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0111100001100111);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b11;
		#5;
		if (out !== 16'b1111100001100111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111100001100111);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b1111000011001111;
		shift = 2'b00;
		#5;
		if (out !== 16'b1111000011001111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111000011001111);
			err = 1'b1;
		end
		#5
		

		$display("REPEATING TESTING SEQUENCE FOR 16'b1111111111111111");

		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b01;
		#5;
		if (out !== 16'b1111111111111110) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111110);
			err = 1'b1;
		end
		#5
		

		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b10;
		#5;
		if (out !== 16'b0111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0111111111111111);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b11;
		#5;
		if (out !== 16'b1111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111111);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b1111111111111111;
		shift = 2'b00;
		#5;
		if (out !== 16'b1111111111111111) begin
			$display("ERROR, output is %b, expected %b", out, 16'b1111111111111111);
			err = 1'b1;
		end
		#5


		$display("REPEATING TESTING SEQUENCE FOR 0");

		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b01;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b10;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'd0;
		shift = 2'b11;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'd0;
		shift = 2'b00;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("REPEATING TESTING SEQUENCE FOR 1");


		$display("TESTING LEFT SHIFT OPERATION");
		in = 16'b0000000000000001; 
		shift = 2'b01;
		#5;
		if (out !== 16'b0000000000000010) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0000000000000010);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b10;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING RIGHT SHIFT OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b11;
		#5;
		if (out !== 16'd0) begin
			$display("ERROR, output is %b, expected %b", out, 16'd0);
			err = 1'b1;
		end
		#5


		$display("TESTING BASE CASE OPERATION");
		in = 16'b0000000000000001;
		shift = 2'b00;
		#5;
		if (out !== 16'b0000000000000001) begin
			$display("ERROR, output is %b, expected %b", out, 16'b0000000000000001);
			err = 1'b1;
		end
		#5

		if (~err) $display("PASSED");
		else $display("FAILED");
	
	end
endmodule