data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:13: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #1 MEMDAT = 32\'h0000CAFE ; MEMLOAD = 1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #5 MFC = 1 ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #7 MFC = 0 ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #1 MEMDAT = 32\'hCAFE0000 ; MEMLOAD = 1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #5 MFC = 1 ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #7 MFC = 0 ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:39: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:40: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench.v:42: Unsupported or unknown PLI call: $monitor\n $monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench;

parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	case(MEMADD) 
		8'h00:begin
			#1 MEMDAT = 32'h0000CAFE ; MEMLOAD = 1; 
			#5 MFC = 1 ;
			#7 MFC = 0 ;
		end
		8'h01:begin
			#1 MEMDAT = 32'hCAFE0000 ; MEMLOAD = 1; 
			#5 MFC = 1 ;
			#7 MFC = 0 ;
		end
	endcase
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench);
	$display(" Test Results" );
	$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end

endmodule
module ARM_CU_ALU_TestBench;


parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	case(MEMADD) 
		8'h00:begin
			#1 MEMDAT = 32'h0000CAFE ; MEMLOAD = 1; 
			#5 MFC = 1 ;
			#7 MFC = 0 ;
		end
		8'h01:begin
			#1 MEMDAT = 32'hCAFE0000 ; MEMLOAD = 1; 
			#5 MFC = 1 ;
			#7 MFC = 0 ;
		end
	endcase
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench);
	$display(" Test Results" );
	$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end

endmodule