data/full_repos/permissive/481044442/BDCDrv/uart_parser.v
1: b"%Error: data/full_repos/permissive/481044442/BDCDrv/uart_parser.v:38: Cannot find file containing module: 'pwm_module'\npwm_module instance1_pwm_module(.clk(clk), \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/pwm_module\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/pwm_module.v\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/pwm_module.sv\n             pwm_module\n             pwm_module.v\n             pwm_module.sv\n             obj_dir/pwm_module\n             obj_dir/pwm_module.v\n             obj_dir/pwm_module.sv\n%Error: data/full_repos/permissive/481044442/BDCDrv/uart_parser.v:45: Cannot find file containing module: 'pwm_module'\npwm_module instance2_pwm_module(.clk(clk), \n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart_parser(clk,reset,Start_En_Sig,Rx_Done_Sig,Data_In,led,motor_pwm,Done_Sig);
input clk;
input reset;
input Start_En_Sig;
input Rx_Done_Sig;
input [7:0] Data_In;

output reg [1:0] led;
output [3:0] motor_pwm;
output reg Done_Sig;
















reg [7:0] data_buf[4:0];

reg [2:0] counter;
reg [1:0] continous_run;


reg M1_Start_En_Sig;
reg M2_Start_En_Sig;
wire M1_Done_Sig;
wire M2_Done_Sig;
reg [3:0] work_mode;
pwm_module instance1_pwm_module(.clk(clk),
								.reset(reset),
								.Start_En_Sig(M1_Start_En_Sig),
								.work_mode(work_mode),
								.pwm1(motor_pwm[0]),
								.pwm2(motor_pwm[1]),
								.Done_Sig(M1_Done_Sig));
pwm_module instance2_pwm_module(.clk(clk),
								.reset(reset),
								.Start_En_Sig(M2_Start_En_Sig),
								.work_mode(work_mode),
								.pwm1(motor_pwm[2]),
								.pwm2(motor_pwm[3]),
								.Done_Sig(M2_Done_Sig));

always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					data_buf[0]<=8'd0;
					data_buf[1]<=8'd0;
					data_buf[2]<=8'd0;
					data_buf[3]<=8'd0;
					data_buf[4]<=8'd0;
					counter<=3'd0;
					Done_Sig<=1'b0;
					continous_run[0]<=1'b0;
					continous_run[1]<=1'b0;
					led[0]<=1'b0;
					led[1]<=1'b0;
				end
	else if(Start_En_Sig)	begin
								Done_Sig<=1'b0;
								if(Rx_Done_Sig)	begin
													data_buf[counter]<=Data_In;
													counter<=counter+1'b1;
												end
								 if(counter==3'd5)	begin
															counter<=3'd0;

															if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h01)	begin
																																	case(data_buf[3])
																																		8'h31:begin work_mode<=4'd0;M1_Start_En_Sig<=1'b1; end
																																		8'h32:begin work_mode<=4'd1;M1_Start_En_Sig<=1'b1; end
																																		8'h33:begin work_mode<=4'd2;M1_Start_En_Sig<=1'b1; end
																																		8'h34:begin work_mode<=4'd3;M1_Start_En_Sig<=1'b1; end
																																		

																																		8'h81:begin continous_run[0]<=1'b1;work_mode<=4'd15;M1_Start_En_Sig<=1'b1; end

																																		8'h82:begin continous_run[0]<=1'b0;work_mode<=4'd15;M1_Start_En_Sig<=1'b1; end
																																		default: begin M1_Start_En_Sig<=1'b0; end
																																	endcase
																																end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h02)	begin
																																		case(data_buf[3])
																																			8'h31:begin work_mode<=4'd0;M2_Start_En_Sig<=1'b1; end
																																			8'h32:begin work_mode<=4'd1;M2_Start_En_Sig<=1'b1; end
																																			8'h33:begin work_mode<=4'd2;M2_Start_En_Sig<=1'b1; end
																																			8'h34:begin work_mode<=4'd3;M2_Start_En_Sig<=1'b1; end
																																			

																																			8'h34:begin continous_run[1]<=1'b1;work_mode<=4'd15;M2_Start_En_Sig<=1'b1; end

																																			8'h34:begin continous_run[1]<=1'b0;work_mode<=4'd15;M2_Start_En_Sig<=1'b1; end
																																			default: begin M2_Start_En_Sig<=1'b0; end
																																		endcase
																																	end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h03)	begin
																																		case(data_buf[3])
																																			8'h01:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[0]<=1'b1;
																																					end
																																			8'h02: begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[0]<=1'b0;
																																				   end
																																			default: begin led[0]<=1'b0; end
																																		endcase
																																	end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h04)	begin
																																		case(data_buf[3])
																																			8'h01:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[1]<=1'b1;
																																					end
																																			8'h02:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[1]<=1'b0;
																																					end
																																			default: begin led[1]<=1'b0; end
																																		endcase
																																	end

															Done_Sig<=1'b1;
														end
								else begin
										if(M1_Done_Sig)	begin
															M1_Start_En_Sig<=1'b0;
														end
										if(M2_Done_Sig)	begin
															M2_Start_En_Sig<=1'b0;
														end
									end
							end
end


endmodule
module uart_parser(clk,reset,Start_En_Sig,Rx_Done_Sig,Data_In,led,motor_pwm,Done_Sig);

input clk;
input reset;
input Start_En_Sig;
input Rx_Done_Sig;
input [7:0] Data_In;

output reg [1:0] led;
output [3:0] motor_pwm;
output reg Done_Sig;
















reg [7:0] data_buf[4:0];

reg [2:0] counter;
reg [1:0] continous_run;


reg M1_Start_En_Sig;
reg M2_Start_En_Sig;
wire M1_Done_Sig;
wire M2_Done_Sig;
reg [3:0] work_mode;
pwm_module instance1_pwm_module(.clk(clk),
								.reset(reset),
								.Start_En_Sig(M1_Start_En_Sig),
								.work_mode(work_mode),
								.pwm1(motor_pwm[0]),
								.pwm2(motor_pwm[1]),
								.Done_Sig(M1_Done_Sig));
pwm_module instance2_pwm_module(.clk(clk),
								.reset(reset),
								.Start_En_Sig(M2_Start_En_Sig),
								.work_mode(work_mode),
								.pwm1(motor_pwm[2]),
								.pwm2(motor_pwm[3]),
								.Done_Sig(M2_Done_Sig));

always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					data_buf[0]<=8'd0;
					data_buf[1]<=8'd0;
					data_buf[2]<=8'd0;
					data_buf[3]<=8'd0;
					data_buf[4]<=8'd0;
					counter<=3'd0;
					Done_Sig<=1'b0;
					continous_run[0]<=1'b0;
					continous_run[1]<=1'b0;
					led[0]<=1'b0;
					led[1]<=1'b0;
				end
	else if(Start_En_Sig)	begin
								Done_Sig<=1'b0;
								if(Rx_Done_Sig)	begin
													data_buf[counter]<=Data_In;
													counter<=counter+1'b1;
												end
								 if(counter==3'd5)	begin
															counter<=3'd0;

															if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h01)	begin
																																	case(data_buf[3])
																																		8'h31:begin work_mode<=4'd0;M1_Start_En_Sig<=1'b1; end
																																		8'h32:begin work_mode<=4'd1;M1_Start_En_Sig<=1'b1; end
																																		8'h33:begin work_mode<=4'd2;M1_Start_En_Sig<=1'b1; end
																																		8'h34:begin work_mode<=4'd3;M1_Start_En_Sig<=1'b1; end
																																		

																																		8'h81:begin continous_run[0]<=1'b1;work_mode<=4'd15;M1_Start_En_Sig<=1'b1; end

																																		8'h82:begin continous_run[0]<=1'b0;work_mode<=4'd15;M1_Start_En_Sig<=1'b1; end
																																		default: begin M1_Start_En_Sig<=1'b0; end
																																	endcase
																																end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h02)	begin
																																		case(data_buf[3])
																																			8'h31:begin work_mode<=4'd0;M2_Start_En_Sig<=1'b1; end
																																			8'h32:begin work_mode<=4'd1;M2_Start_En_Sig<=1'b1; end
																																			8'h33:begin work_mode<=4'd2;M2_Start_En_Sig<=1'b1; end
																																			8'h34:begin work_mode<=4'd3;M2_Start_En_Sig<=1'b1; end
																																			

																																			8'h34:begin continous_run[1]<=1'b1;work_mode<=4'd15;M2_Start_En_Sig<=1'b1; end

																																			8'h34:begin continous_run[1]<=1'b0;work_mode<=4'd15;M2_Start_En_Sig<=1'b1; end
																																			default: begin M2_Start_En_Sig<=1'b0; end
																																		endcase
																																	end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h03)	begin
																																		case(data_buf[3])
																																			8'h01:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[0]<=1'b1;
																																					end
																																			8'h02: begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[0]<=1'b0;
																																				   end
																																			default: begin led[0]<=1'b0; end
																																		endcase
																																	end
															else if(data_buf[0]==8'h55 && data_buf[1]==8'haa && data_buf[2]==8'h04)	begin
																																		case(data_buf[3])
																																			8'h01:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[1]<=1'b1;
																																					end
																																			8'h02:	begin
																																						if(data_buf[0]+data_buf[1]+data_buf[2]+data_buf[3]==data_buf[4])
																																							led[1]<=1'b0;
																																					end
																																			default: begin led[1]<=1'b0; end
																																		endcase
																																	end

															Done_Sig<=1'b1;
														end
								else begin
										if(M1_Done_Sig)	begin
															M1_Start_En_Sig<=1'b0;
														end
										if(M2_Done_Sig)	begin
															M2_Start_En_Sig<=1'b0;
														end
									end
							end
end


endmodule