data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:42: syntax error, unexpected \'@\'\n   @(posedge aclk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   always #5 aclk = ~aclk;\n          ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:56: syntax error, unexpected \'@\'\n   wait(aresetn === 0) @(posedge aclk);\n                       ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:56: Unsupported: wait statements\n   wait(aresetn === 0) @(posedge aclk);\n   ^~~~\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:57: syntax error, unexpected \'@\'\n   wait(aresetn === 1) @(posedge aclk);\n                       ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:57: Unsupported: wait statements\n   wait(aresetn === 1) @(posedge aclk);\n   ^~~~\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:58: syntax error, unexpected \'@\'\n   wait(aresetn === 1) @(posedge aclk);\n                       ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:58: Unsupported: wait statements\n   wait(aresetn === 1) @(posedge aclk);\n   ^~~~\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:59: syntax error, unexpected \'@\'\n   wait(aresetn === 1) @(posedge aclk);\n                       ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:59: Unsupported: wait statements\n   wait(aresetn === 1) @(posedge aclk);\n   ^~~~\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:60: syntax error, unexpected \'@\'\n   wait(aresetn === 1) @(posedge aclk);\n                       ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:60: Unsupported: wait statements\n   wait(aresetn === 1) @(posedge aclk);\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #500 start = 1\'b1;\n   ^\n%Error: data/full_repos/permissive/40989439/simulation/elinkdv/elinkdv.srcs/sim_1/imports/elink_test/elink2new_tb.v:66: Unsupported: wait statements\n   wait( done == 3\'b111);\n   ^~~~\n%Error: Exiting due to 12 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module elink2_tb;
   
   reg aclk;
   reg aresetn;
   reg start;
   wire csysreq = 1'b0;
   wire reset = ~aresetn;



   
   wire [2:0] done;
   wire [2:0] error;


   elink_testbench dut
          (.aclk          (aclk),
           .aresetn       (aresetn),
           .reset         (reset),
           .csysreq       (csysreq),
           .done0         (done[0]),
           .done1         (done[1]),
           .done2         (done[2]),
           .error0        (error[0]),
           .error1        (error[1]),
           .error2        (error[2]),
           .start         (start));





           

   initial begin
	  aresetn = 1'b0;
	  #500;

	  @(posedge aclk);
	  aresetn = 1'b1;
   end


   initial aclk = 1'b0;
   always #5 aclk = ~aclk;


   initial begin

	  start = 1'b0;


	  wait(aresetn === 0) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);

	  #500 start = 1'b1;

	  $display("=== TB Started");
	  
	  wait( done == 3'b111);
	  $display("=== TEST_FINISHED");
	  if ( error != 3'b000 ) begin
		 $display("===_TEST: FAILED!");
	  end else begin
		 $display("=== TEST: PASSED!");
	  end

   end
   
   always @ (posedge done[2])
       $display("=== INIT Complete");
   
   always @ (posedge done[0])
       $display("=== GOLD->ELINK2 Complete");
   
   always @ (posedge done[1])
       $display("=== ELINK2->GOLD Complete");
       
   always @ (posedge error[0])
       if( error[0] == 1'b1 && done[0] == 1'b0)
           $display("=== ERROR FLAG GOLD->ELINK2 @ %t", $time);
   
   always @ (posedge error[1])
       if( error[1] == 1'b1 && done[1] == 1'b0)
           $display("=== ERROR FLAG ELINK2->GOLD @ %T", $time);
        
   always @ (posedge error[2])
       if( error[2] == 1'b1 && done[2] == 1'b0)
           $display("=== ERROR FLAG INIT @ %T", $time);
                
endmodule
module elink2_tb;

   
   reg aclk;
   reg aresetn;
   reg start;
   wire csysreq = 1'b0;
   wire reset = ~aresetn;



   
   wire [2:0] done;
   wire [2:0] error;


   elink_testbench dut
          (.aclk          (aclk),
           .aresetn       (aresetn),
           .reset         (reset),
           .csysreq       (csysreq),
           .done0         (done[0]),
           .done1         (done[1]),
           .done2         (done[2]),
           .error0        (error[0]),
           .error1        (error[1]),
           .error2        (error[2]),
           .start         (start));





           

   initial begin
	  aresetn = 1'b0;
	  #500;

	  @(posedge aclk);
	  aresetn = 1'b1;
   end


   initial aclk = 1'b0;
   always #5 aclk = ~aclk;


   initial begin

	  start = 1'b0;


	  wait(aresetn === 0) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);
	  wait(aresetn === 1) @(posedge aclk);

	  #500 start = 1'b1;

	  $display("=== TB Started");
	  
	  wait( done == 3'b111);
	  $display("=== TEST_FINISHED");
	  if ( error != 3'b000 ) begin
		 $display("===_TEST: FAILED!");
	  end else begin
		 $display("=== TEST: PASSED!");
	  end

   end
   
   always @ (posedge done[2])
       $display("=== INIT Complete");
   
   always @ (posedge done[0])
       $display("=== GOLD->ELINK2 Complete");
   
   always @ (posedge done[1])
       $display("=== ELINK2->GOLD Complete");
       
   always @ (posedge error[0])
       if( error[0] == 1'b1 && done[0] == 1'b0)
           $display("=== ERROR FLAG GOLD->ELINK2 @ %t", $time);
   
   always @ (posedge error[1])
       if( error[1] == 1'b1 && done[1] == 1'b0)
           $display("=== ERROR FLAG ELINK2->GOLD @ %T", $time);
        
   always @ (posedge error[2])
       if( error[2] == 1'b1 && done[2] == 1'b0)
           $display("=== ERROR FLAG INIT @ %T", $time);
                
endmodule