data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:9: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/pdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:11: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:82: Define or directive not defined: \'`x_or_0\'\n            ig2cq_count <= {5{`x_or_0}};\n                              ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:82: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            ig2cq_count <= {5{`x_or_0}};\n                                     ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:130: Define or directive not defined: \'`x_or_0\'\n            cq2eg_adr <= {4{`x_or_0}};\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:130: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            cq2eg_adr <= {4{`x_or_0}};\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:177: Define or directive not defined: \'`x_or_0\'\n            cq2eg_count_p <= {5{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:177: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            cq2eg_count_p <= {5{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:186: Define or directive not defined: \'`x_or_0\'\n            cq2eg_pvld_p <= `x_or_0;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:186: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            cq2eg_pvld_p <= `x_or_0;\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:207: Define or directive not defined: \'`x_or_0\'\n        cq2eg_pd <= {18{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:207: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        cq2eg_pd <= {18{`x_or_0}};\n                               ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:511: Define or directive not defined: \'`x_or_0\'\n    default: dout = {18{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v:511: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {18{`x_or_0}};\n                               ^\n%Error: Exiting due to 14 error(s)\n'
module NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 (
      clk
    , pwrbus_ram_pd
    , di
    , we
    , wa
    , ra
    , dout
    );
input clk;
input [31 : 0] pwrbus_ram_pd;
input [17:0] di;
input we;
input [3:0] wa;
input [3:0] ra;
output [17:0] dout;
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31]));
`ifdef EMU



reg [3:0] Wa0_vmw;
reg we0_vmw;
reg [17:0] Di0_vmw;
always @( posedge clk ) begin
    Wa0_vmw <= wa;
    we0_vmw <= we;
    Di0_vmw <= di;
end
vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 emu_ram (
     .Wa0( Wa0_vmw )
   , .we0( we0_vmw )
   , .Di0( Di0_vmw )
   , .Ra0( ra )
   , .Do0( dout )
   );
`else
reg [17:0] ram_ff0;
reg [17:0] ram_ff1;
reg [17:0] ram_ff2;
reg [17:0] ram_ff3;
reg [17:0] ram_ff4;
reg [17:0] ram_ff5;
reg [17:0] ram_ff6;
reg [17:0] ram_ff7;
reg [17:0] ram_ff8;
reg [17:0] ram_ff9;
reg [17:0] ram_ff10;
reg [17:0] ram_ff11;
reg [17:0] ram_ff12;
reg [17:0] ram_ff13;
reg [17:0] ram_ff14;
reg [17:0] ram_ff15;
always @( posedge clk ) begin
    if ( we && wa == 4'd0 ) begin
 ram_ff0 <= di;
    end
    if ( we && wa == 4'd1 ) begin
 ram_ff1 <= di;
    end
    if ( we && wa == 4'd2 ) begin
 ram_ff2 <= di;
    end
    if ( we && wa == 4'd3 ) begin
 ram_ff3 <= di;
    end
    if ( we && wa == 4'd4 ) begin
 ram_ff4 <= di;
    end
    if ( we && wa == 4'd5 ) begin
 ram_ff5 <= di;
    end
    if ( we && wa == 4'd6 ) begin
 ram_ff6 <= di;
    end
    if ( we && wa == 4'd7 ) begin
 ram_ff7 <= di;
    end
    if ( we && wa == 4'd8 ) begin
 ram_ff8 <= di;
    end
    if ( we && wa == 4'd9 ) begin
 ram_ff9 <= di;
    end
    if ( we && wa == 4'd10 ) begin
 ram_ff10 <= di;
    end
    if ( we && wa == 4'd11 ) begin
 ram_ff11 <= di;
    end
    if ( we && wa == 4'd12 ) begin
 ram_ff12 <= di;
    end
    if ( we && wa == 4'd13 ) begin
 ram_ff13 <= di;
    end
    if ( we && wa == 4'd14 ) begin
 ram_ff14 <= di;
    end
    if ( we && wa == 4'd15 ) begin
 ram_ff15 <= di;
    end
end
reg [17:0] dout;
always @(*) begin
    case( ra )
    4'd0: dout = ram_ff0;
    4'd1: dout = ram_ff1;
    4'd2: dout = ram_ff2;
    4'd3: dout = ram_ff3;
    4'd4: dout = ram_ff4;
    4'd5: dout = ram_ff5;
    4'd6: dout = ram_ff6;
    4'd7: dout = ram_ff7;
    4'd8: dout = ram_ff8;
    4'd9: dout = ram_ff9;
    4'd10: dout = ram_ff10;
    4'd11: dout = ram_ff11;
    4'd12: dout = ram_ff12;
    4'd13: dout = ram_ff13;
    4'd14: dout = ram_ff14;
    4'd15: dout = ram_ff15;

    default: dout = {18{`x_or_0}};

    endcase
end
`endif
endmodule
module NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 (
      clk
    , pwrbus_ram_pd
    , di
    , we
    , wa
    , ra
    , dout
    );

input clk;
input [31 : 0] pwrbus_ram_pd;
input [17:0] di;
input we;
input [3:0] wa;
input [3:0] ra;
output [17:0] dout;
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31]));
`ifdef EMU



reg [3:0] Wa0_vmw;
reg we0_vmw;
reg [17:0] Di0_vmw;
always @( posedge clk ) begin
    Wa0_vmw <= wa;
    we0_vmw <= we;
    Di0_vmw <= di;
end
vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 emu_ram (
     .Wa0( Wa0_vmw )
   , .we0( we0_vmw )
   , .Di0( Di0_vmw )
   , .Ra0( ra )
   , .Do0( dout )
   );
`else
reg [17:0] ram_ff0;
reg [17:0] ram_ff1;
reg [17:0] ram_ff2;
reg [17:0] ram_ff3;
reg [17:0] ram_ff4;
reg [17:0] ram_ff5;
reg [17:0] ram_ff6;
reg [17:0] ram_ff7;
reg [17:0] ram_ff8;
reg [17:0] ram_ff9;
reg [17:0] ram_ff10;
reg [17:0] ram_ff11;
reg [17:0] ram_ff12;
reg [17:0] ram_ff13;
reg [17:0] ram_ff14;
reg [17:0] ram_ff15;
always @( posedge clk ) begin
    if ( we && wa == 4'd0 ) begin
 ram_ff0 <= di;
    end
    if ( we && wa == 4'd1 ) begin
 ram_ff1 <= di;
    end
    if ( we && wa == 4'd2 ) begin
 ram_ff2 <= di;
    end
    if ( we && wa == 4'd3 ) begin
 ram_ff3 <= di;
    end
    if ( we && wa == 4'd4 ) begin
 ram_ff4 <= di;
    end
    if ( we && wa == 4'd5 ) begin
 ram_ff5 <= di;
    end
    if ( we && wa == 4'd6 ) begin
 ram_ff6 <= di;
    end
    if ( we && wa == 4'd7 ) begin
 ram_ff7 <= di;
    end
    if ( we && wa == 4'd8 ) begin
 ram_ff8 <= di;
    end
    if ( we && wa == 4'd9 ) begin
 ram_ff9 <= di;
    end
    if ( we && wa == 4'd10 ) begin
 ram_ff10 <= di;
    end
    if ( we && wa == 4'd11 ) begin
 ram_ff11 <= di;
    end
    if ( we && wa == 4'd12 ) begin
 ram_ff12 <= di;
    end
    if ( we && wa == 4'd13 ) begin
 ram_ff13 <= di;
    end
    if ( we && wa == 4'd14 ) begin
 ram_ff14 <= di;
    end
    if ( we && wa == 4'd15 ) begin
 ram_ff15 <= di;
    end
end
reg [17:0] dout;
always @(*) begin
    case( ra )
    4'd0: dout = ram_ff0;
    4'd1: dout = ram_ff1;
    4'd2: dout = ram_ff2;
    4'd3: dout = ram_ff3;
    4'd4: dout = ram_ff4;
    4'd5: dout = ram_ff5;
    4'd6: dout = ram_ff6;
    4'd7: dout = ram_ff7;
    4'd8: dout = ram_ff8;
    4'd9: dout = ram_ff9;
    4'd10: dout = ram_ff10;
    4'd11: dout = ram_ff11;
    4'd12: dout = ram_ff12;
    4'd13: dout = ram_ff13;
    4'd14: dout = ram_ff14;
    4'd15: dout = ram_ff15;

    default: dout = {18{`x_or_0}};

    endcase
end
`endif
endmodule