data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v
1: b'%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:17: Unsupported or unknown PLI call: $sdf_annotate\n initial $sdf_annotate("../../dc/pe_bzh/PE.syn.sdf", dut);\n         ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #2.5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./PE.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, PE_TB.dut);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:42: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:50: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:55: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:58: Unsupported or unknown PLI call: $dumpall\n         $dumpall;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/467394306/qsim_dc/tb_pe_bzh/pe_tb.v:59: Unsupported or unknown PLI call: $dumpflush\n         $dumpflush;\n         ^~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE_TB();
	reg clk, rstn, fire;
	reg [7:0] w, a;
	wire [31:0] out;
	wire out_f;
	wire [7:0] out_a, out_w;
	reg [7:0] cnt;

	integer i;
	
	initial $sdf_annotate("../../dc/pe_bzh/PE.syn.sdf", dut);

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	always @(posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE dut(clk, rstn, fire, w, a, out_f, out_a, out_w, out);

	initial begin
	$dumpfile("./PE.vcd");
        $dumpvars(0, PE_TB.dut);
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w <= 0;
		a <= 1;
		fire <= 0;

		$display("Initialized");

		@(posedge clk);
		@(negedge clk);

		rstn <= 1;
		fire <= 1;

		for (i=0; i<16; i=i+1) begin
			w <= w + 1;
			@(posedge clk);
		end

		@(negedge clk);
		fire <= 0;
		@(posedge clk);
		@(posedge clk);

        	$dumpall;
        	$dumpflush;
		$finish;
	end
endmodule
module PE_TB();

	reg clk, rstn, fire;
	reg [7:0] w, a;
	wire [31:0] out;
	wire out_f;
	wire [7:0] out_a, out_w;
	reg [7:0] cnt;

	integer i;
	
	initial $sdf_annotate("../../dc/pe_bzh/PE.syn.sdf", dut);

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	always @(posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE dut(clk, rstn, fire, w, a, out_f, out_a, out_w, out);

	initial begin
	$dumpfile("./PE.vcd");
        $dumpvars(0, PE_TB.dut);
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w <= 0;
		a <= 1;
		fire <= 0;

		$display("Initialized");

		@(posedge clk);
		@(negedge clk);

		rstn <= 1;
		fire <= 1;

		for (i=0; i<16; i=i+1) begin
			w <= w + 1;
			@(posedge clk);
		end

		@(negedge clk);
		fire <= 0;
		@(posedge clk);
		@(posedge clk);

        	$dumpall;
        	$dumpflush;
		$finish;
	end
endmodule