data/full_repos/permissive/498662723/Circuits/Sequential Logic/Finite State Machines/fsm ps2 (packet parser).v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/fsm\n%Error: Cannot find file containing module: ps2\n%Error: Cannot find file containing module: (packet\n%Error: Cannot find file containing module: parser).v\n%Error: Exiting due to 8 error(s)\n'
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);
    
    parameter B1 = 2'b00, B2 = 2'b01, B3 = 2'b10, DONE = 2'b11;
    reg [1:0] state,next;


    always @ (*)
        begin
            case(state)
                B1: begin
                    if (in[3])
                        next = B2;
                    else
                        next = B1;
                end
                
                B2: next = B3;
                
                B3: next = DONE;
                
                DONE: begin
                    if(in[3])
                        next = B2;
                    else
                        next = B1;
                end
                
                default: next = B1;
            endcase
        end


    always @ (posedge clk)
        begin
            if (reset)
                state <= B1;
            else
                state <= next;
        end
 

    assign done = (state==DONE);

endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);

    
    parameter B1 = 2'b00, B2 = 2'b01, B3 = 2'b10, DONE = 2'b11;
    reg [1:0] state,next;


    always @ (*)
        begin
            case(state)
                B1: begin
                    if (in[3])
                        next = B2;
                    else
                        next = B1;
                end
                
                B2: next = B3;
                
                B3: next = DONE;
                
                DONE: begin
                    if(in[3])
                        next = B2;
                    else
                        next = B1;
                end
                
                default: next = B1;
            endcase
        end


    always @ (posedge clk)
        begin
            if (reset)
                state <= B1;
            else
                state <= next;
        end
 

    assign done = (state==DONE);

endmodule