data/full_repos/permissive/514354758/verilog/top.v
1: b"%Error: data/full_repos/permissive/514354758/verilog/top.v:11: Cannot find file containing module: 'image_read'\n    image_read image_read_inst(HCLK,HRESETn,VSYNC,HSYNC,data,ctrl_done);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514354758/verilog,data/full_repos/permissive/514354758/image_read\n             data/full_repos/permissive/514354758/verilog,data/full_repos/permissive/514354758/image_read.v\n             data/full_repos/permissive/514354758/verilog,data/full_repos/permissive/514354758/image_read.sv\n             image_read\n             image_read.v\n             image_read.sv\n             obj_dir/image_read\n             obj_dir/image_read.v\n             obj_dir/image_read.sv\n%Error: data/full_repos/permissive/514354758/verilog/top.v:12: Cannot find file containing module: 'remover'\n    remover remover_inst(HCLK,HSYNC,HRESETn,data,VGA_data);\n    ^~~~~~~\n%Error: data/full_repos/permissive/514354758/verilog/top.v:13: Cannot find file containing module: 'image_write'\n    image_write image_write_inst(HCLK,HRESETn,HSYNC,VGA_data,write_done);\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top (
    input HCLK,
    input HRESETn,
    output VSYNC,
    output HSYNC,
    output [7:0] data,
    output [7:0] VGA_data,
    output ctrl_done,
    output write_done
);
    image_read image_read_inst(HCLK,HRESETn,VSYNC,HSYNC,data,ctrl_done);
    remover remover_inst(HCLK,HSYNC,HRESETn,data,VGA_data);
    image_write image_write_inst(HCLK,HRESETn,HSYNC,VGA_data,write_done);

endmodule
module top (
    input HCLK,
    input HRESETn,
    output VSYNC,
    output HSYNC,
    output [7:0] data,
    output [7:0] VGA_data,
    output ctrl_done,
    output write_done
);

    image_read image_read_inst(HCLK,HRESETn,VSYNC,HSYNC,data,ctrl_done);
    remover remover_inst(HCLK,HSYNC,HRESETn,data,VGA_data);
    image_write image_write_inst(HCLK,HRESETn,HSYNC,VGA_data,write_done);

endmodule