data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/syn_lib/FA.v
data/verilator_xmls/f0a8fa70-7962-40c2-b9da-75f4f3372849.xml
module FA( 
	input A, B, CI,
	output S, CO
);

	wire   n1, n2, n3;

	assign n1 = A^CI;
	assign n2 = B^CI;
	assign n3 = n1&n2;
	assign S  = n1^B;
	assign CO = n3^CI;

  
endmodule
module FA( 
	input A, B, CI,
	output S, CO
);


	wire   n1, n2, n3;

	assign n1 = A^CI;
	assign n2 = B^CI;
	assign n3 = n1&n2;
	assign S  = n1^B;
	assign CO = n3^CI;

  
endmodule