data/full_repos/permissive/469273213/counter/rtl/counter.v
data/verilator_xmls/4319a2c8-4206-478f-82cf-4844aa38127d.xml
module counter #(parameter WIDTH = 4) (
    input wire clk,
    input wire rst_n,
    input wire en,
    input wire dn,
    input wire load,
    input wire [WIDTH-1:0] data,
    output reg [WIDTH-1:0] count
);

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            count <= {WIDTH{1'b0}};
        end else if (en) begin
            if (load) begin
                count <= data;
            end else if (dn) begin
                count <= count - 1;
            end else begin
                count <= count + 1;
            end
        end else begin
            count <= count;
        end
    end

endmodule
module counter #(parameter WIDTH = 4) (
    input wire clk,
    input wire rst_n,
    input wire en,
    input wire dn,
    input wire load,
    input wire [WIDTH-1:0] data,
    output reg [WIDTH-1:0] count
);


    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            count <= {WIDTH{1'b0}};
        end else if (en) begin
            if (load) begin
                count <= data;
            end else if (dn) begin
                count <= count - 1;
            end else begin
                count <= count + 1;
            end
        end else begin
            count <= count;
        end
    end

endmodule