data/full_repos/permissive/418752214/smart_run/logical/common/BUFGCE.v
data/verilator_xmls/54aab678-4b41-4651-9ef5-81012bbf2308.xml
module BUFGCE(
  I,
  CE,
  O 
);

input  I;
input  CE;
output O;

wire clk_in;
wire external_en;

assign clk_in = I;
assign external_en = CE;

reg    clk_en_af_latch;
always @(clk_in or external_en)
begin
  if(!clk_in)
    clk_en_af_latch <= external_en;
end

reg clk_en ;
always @ (clk_en_af_latch )
begin
    clk_en <= clk_en_af_latch;
end
assign O = clk_in && clk_en ;

endmodule
module BUFGCE(
  I,
  CE,
  O 
);


input  I;
input  CE;
output O;

wire clk_in;
wire external_en;

assign clk_in = I;
assign external_en = CE;

reg    clk_en_af_latch;
always @(clk_in or external_en)
begin
  if(!clk_in)
    clk_en_af_latch <= external_en;
end

reg clk_en ;
always @ (clk_en_af_latch )
begin
    clk_en <= clk_en_af_latch;
end
assign O = clk_in && clk_en ;

endmodule