data/full_repos/permissive/463481430/RTL/core/fpu.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/fpu.v:4: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/defines.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/defines.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/fpu.v:5: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module FPU32(
    input wire i_clk,
    input wire i_rsn,

    input wire[31:0] i_op1,
    input wire[31:0] i_op2,

    
    output wire[31:0] o_addres,
    output wire[31:0] o_subres,
    output wire[31:0] o_mulres,
    output wire[31:0] o_divres
);


wire[31:0] addres, subres, mulres, divres;
add_sub u_add(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( addres    ),
    .sub       ( 0       ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);

add_sub u_sub(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( subres    ),
    .sub       ( 1       ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);


div u_div(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( divres    ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);

mul u_mul(
    .n1        ( i_op1     ),
    .n2        ( i_op2     ),
    .result    ( mulres    ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);


assign o_addres = addres;
assign o_subres = subres;
assign o_mulres = mulres;
assign o_divres = divres;












endmodule
module FPU32(
    input wire i_clk,
    input wire i_rsn,

    input wire[31:0] i_op1,
    input wire[31:0] i_op2,

    
    output wire[31:0] o_addres,
    output wire[31:0] o_subres,
    output wire[31:0] o_mulres,
    output wire[31:0] o_divres
);



wire[31:0] addres, subres, mulres, divres;
add_sub u_add(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( addres    ),
    .sub       ( 0       ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);

add_sub u_sub(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( subres    ),
    .sub       ( 1       ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);


div u_div(
    .n1        ( i_op1        ),
    .n2        ( i_op2        ),
    .result    ( divres    ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);

mul u_mul(
    .n1        ( i_op1     ),
    .n2        ( i_op2     ),
    .result    ( mulres    ),
    .Overflow  (   ),
    .Underflow (  ),
    .Exception  (   )
);


assign o_addres = addres;
assign o_subres = subres;
assign o_mulres = mulres;
assign o_divres = divres;












endmodule