data/full_repos/permissive/469979476/language/18.v
data/verilator_xmls/df63b1c8-a491-4eac-a1d4-cb3fc013699f.xml
module top_module (
    input [7:0] in,
    output [31:0] out );



    assign out = {{24{in[7]}}, in};
endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );




    assign out = {{24{in[7]}}, in};
endmodule