data/full_repos/permissive/488093047/Verilog Codes/FullAdder.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/FullAdder.v\n%Error: Exiting due to 3 error(s)\n'
module FullAdder(A,B,C,Sum,Cout);
input A,B,C;
output Sum,Cout;
wire sum1,cout1,cout2;
HalfAdder DUT1(.A(A),.B(B),.Cout(cout1),.Sum(sum1));
HalfAdder DUT2(.A(sum1),.B(C),.Cout(cout2),.Sum(Sum));
xor DUT3(Cout,cout1,cout2);

endmodule
module FullAdder(A,B,C,Sum,Cout);

input A,B,C;
output Sum,Cout;
wire sum1,cout1,cout2;
HalfAdder DUT1(.A(A),.B(B),.Cout(cout1),.Sum(sum1));
HalfAdder DUT2(.A(sum1),.B(C),.Cout(cout2),.Sum(Sum));
xor DUT3(Cout,cout1,cout2);

endmodule