data/full_repos/permissive/441359809/src/yosys/manual/APPNOTE_011_Design_Investigation/primetest.v
data/verilator_xmls/9b45a73a-9e92-4146-a525-ae0579bf9699.xml
module primetest(p, a, b, ok);
input [15:0] p, a, b;
output ok = p != a*b || a == 1 || b == 1;
endmodule
module primetest(p, a, b, ok);

input [15:0] p, a, b;
output ok = p != a*b || a == 1 || b == 1;
endmodule