data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new/main.v
1: b"%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new/main.v:38: Cannot find file containing module: 'nanocpu'\n nanocpu CPU(p_address,p_data,d_address,d_data,wr,clock,nreset);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/nanocpu\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/nanocpu.v\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/nanocpu.sv\n             nanocpu\n             nanocpu.v\n             nanocpu.sv\n             obj_dir/nanocpu\n             obj_dir/nanocpu.v\n             obj_dir/nanocpu.sv\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new/main.v:39: Cannot find file containing module: 'rom2'\n rom2  PROGMEM(p_data,p_address[17:2]);\n ^~~~\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new/main.v:40: Cannot find file containing module: 'memory'\n memory  DATAMEM(d_data,d_address[15:0],wr,clock,SW,seg,an);\n ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/lab03.srcs/sources_1/imports/new/main.v:47: Cannot find file containing module: 'Switch'\n   Switch s(SW[i],sw[i],clock);\n   ^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module main(
	output wire [6:0] seg,
	output wire [3:0] an,
	input [11:0] sw,
	input clock
);
    wire 	[31:0]	p_address;
	wire 	[31:0]	p_data;
	wire	[31:0]	d_address;
	wire	[31:0]	d_data;
	wire wr;
	reg		nreset;

	wire [11:0] SW;

	nanocpu	CPU(p_address,p_data,d_address,d_data,wr,clock,nreset);
	rom2 	PROGMEM(p_data,p_address[17:2]);
	memory 	DATAMEM(d_data,d_address[15:0],wr,clock,SW,seg,an);

	initial nreset=1;

	genvar i;
	generate
		for(i = 0; i < 12; i=i+1) begin
			Switch s(SW[i],sw[i],clock);
		end
	endgenerate

endmodule
module main(
	output wire [6:0] seg,
	output wire [3:0] an,
	input [11:0] sw,
	input clock
);

    wire 	[31:0]	p_address;
	wire 	[31:0]	p_data;
	wire	[31:0]	d_address;
	wire	[31:0]	d_data;
	wire wr;
	reg		nreset;

	wire [11:0] SW;

	nanocpu	CPU(p_address,p_data,d_address,d_data,wr,clock,nreset);
	rom2 	PROGMEM(p_data,p_address[17:2]);
	memory 	DATAMEM(d_data,d_address[15:0],wr,clock,SW,seg,an);

	initial nreset=1;

	genvar i;
	generate
		for(i = 0; i < 12; i=i+1) begin
			Switch s(SW[i],sw[i],clock);
		end
	endgenerate

endmodule