data/full_repos/permissive/41807012/rtl/generic/crc7.v
1: b"%Error: data/full_repos/permissive/41807012/rtl/generic/crc7.v:48: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n  input                 bit,\n                           ^\n%Error: data/full_repos/permissive/41807012/rtl/generic/crc7.v:50: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input                 en\n  ^~~~~\n%Error: data/full_repos/permissive/41807012/rtl/generic/crc7.v:58: syntax error, unexpected assign\nassign  inv = bit ^ crc[6];                    \n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module crc7 #(
  parameter             POLYNOMIAL  =   8'h09,
  parameter             SEED        =   8'h00
)(
  input                 clk,
  input                 rst,
  input                 bit,
  output reg    [6:0]   crc,
  input                 en
);


wire          inv;



assign  inv = bit ^ crc[6];



always @ (posedge clk) begin
  if (rst) begin
    crc  <=  SEED;
  end
  else begin

    if (en) begin
      crc[6] <=  crc[5];
      crc[5] <=  crc[4];
      crc[4] <=  crc[3];
      crc[3] <=  crc[2] ^ inv;
      crc[2] <=  crc[1];
      crc[1] <=  crc[0];
      crc[0] <=  inv;
    end
  end
end

endmodule
module crc7 #(
  parameter             POLYNOMIAL  =   8'h09,
  parameter             SEED        =   8'h00
)(
  input                 clk,
  input                 rst,
  input                 bit,
  output reg    [6:0]   crc,
  input                 en
);



wire          inv;



assign  inv = bit ^ crc[6];



always @ (posedge clk) begin
  if (rst) begin
    crc  <=  SEED;
  end
  else begin

    if (en) begin
      crc[6] <=  crc[5];
      crc[5] <=  crc[4];
      crc[4] <=  crc[3];
      crc[3] <=  crc[2] ^ inv;
      crc[2] <=  crc[1];
      crc[1] <=  crc[0];
      crc[0] <=  inv;
    end
  end
end

endmodule