data/full_repos/permissive/482132588/design/code/imemory.v
1: b"%Error: data/full_repos/permissive/482132588/design/code/imemory.v:14: Define or directive not defined: '`LINE_COUNT'\nreg [31:0] temparr[0:`LINE_COUNT - 1];\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:15: Define or directive not defined: '`MEM_DEPTH'\nreg [7:0]memory[0:`MEM_DEPTH - 1];\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:34: Define or directive not defined: '`MEM_PATH'\n      $readmemh (`MEM_PATH,temparr);\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:34: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n      $readmemh (`MEM_PATH,temparr);\n                          ^\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:36: Define or directive not defined: '`LINE_COUNT'\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:36: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                            ^\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:36: syntax error, unexpected ')', expecting ';'\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                                   ^\n%Error: data/full_repos/permissive/482132588/design/code/imemory.v:49: syntax error, unexpected '[', expecting IDENTIFIER\n      memory[address - 32'h01000000] <= data_in[7:0];\n            ^\n%Error: Cannot continue\n"
module imemory(
  input  wire clock,
  input wire reset,
  input  wire [31:0] address,
  input  wire [31:0] data_in,
  input  wire read_write,
  output wire [31:0] data_out 
);


reg [31:0] temparr[0:`LINE_COUNT - 1];
reg [7:0]memory[0:`MEM_DEPTH - 1];

integer i;




assign data_out[7:0] =  memory[address - `offset];
assign data_out[15:8] = memory[address - `offset + 1];
assign data_out[23:16] = memory[address - `offset + 2];
assign data_out[31:24] = memory[address - `offset + 3];
        




  always @(posedge clock or posedge reset) begin
    if(reset)begin
      
      $readmemh (`MEM_PATH,temparr);
    
      for(i=0; i<`LINE_COUNT; i=i+1) begin

        memory[i*4] = temparr[i][7:0];
        memory[i*4 + 1] = temparr[i][15:8];
        memory[i*4 + 2] = temparr[i][23:16];
        memory[i*4 + 3] = temparr[i][31:24]; 
        
      end

    end

    if (read_write) begin

      memory[address - `offset] <= data_in[7:0];
      memory[address  - `offset + 1] <= data_in[15:8];
      memory[address - `offset + 2] <= data_in[23:16];
      memory[address  - `offset + 3] <= data_in[31:24];     
          
    end


  end
  
endmodule
module imemory(
  input  wire clock,
  input wire reset,
  input  wire [31:0] address,
  input  wire [31:0] data_in,
  input  wire read_write,
  output wire [31:0] data_out 
);



reg [31:0] temparr[0:`LINE_COUNT - 1];
reg [7:0]memory[0:`MEM_DEPTH - 1];

integer i;




assign data_out[7:0] =  memory[address - `offset];
assign data_out[15:8] = memory[address - `offset + 1];
assign data_out[23:16] = memory[address - `offset + 2];
assign data_out[31:24] = memory[address - `offset + 3];
        




  always @(posedge clock or posedge reset) begin
    if(reset)begin
      
      $readmemh (`MEM_PATH,temparr);
    
      for(i=0; i<`LINE_COUNT; i=i+1) begin

        memory[i*4] = temparr[i][7:0];
        memory[i*4 + 1] = temparr[i][15:8];
        memory[i*4 + 2] = temparr[i][23:16];
        memory[i*4 + 3] = temparr[i][31:24]; 
        
      end

    end

    if (read_write) begin

      memory[address - `offset] <= data_in[7:0];
      memory[address  - `offset + 1] <= data_in[15:8];
      memory[address - `offset + 2] <= data_in[23:16];
      memory[address  - `offset + 3] <= data_in[31:24];     
          
    end


  end
  
endmodule