data/full_repos/permissive/441359809/src/yosys/tests/simple/attrib03_parameter.v
data/verilator_xmls/422833cf-503c-4aac-9589-cc26aace2146.xml
module foo(clk, rst, inp, out);
  input  wire clk;
  input  wire rst;
  input  wire [7:0] inp;
  output wire [7:0] out;

  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
endmodule
module foo(clk, rst, inp, out);

  input  wire clk;
  input  wire rst;
  input  wire [7:0] inp;
  output wire [7:0] out;

  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
endmodule