data/full_repos/permissive/418749135/alu_8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:8: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 4 bits.\n                                                              : ... In instance alu_8\n       3\'b000:out=a;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:11: Operator DIV expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b011:out=a/b;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:11: Operator DIV expects 5 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b011:out=a/b;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:12: Operator MODDIV expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b100:out=a%b;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:12: Operator MODDIV expects 5 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b100:out=a%b;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:13: Operator SHIFTL expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b101:out=a<<1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:14: Operator SHIFTR expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                               : ... In instance alu_8\n       3\'b110:out=a>>1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/418749135/alu_8.v:15: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                               : ... In instance alu_8\n       3\'b111:out=(a>b);\n                 ^\n%Error: Exiting due to 8 warning(s)\n'
module alu_8(out,a,b,s);
   output reg [4:0] out;
   input [3:0] a,b;
   input [2:0] s;

   always @(a,b,s) begin
       case(s)
       3'b000:out=a;
       3'b001:out=a+b;
       3'b010:out=a-b;
       3'b011:out=a/b;
       3'b100:out=a%b;
       3'b101:out=a<<1;
       3'b110:out=a>>1;
       3'b111:out=(a>b);
       endcase
   end
endmodule
module alu_8(out,a,b,s);

   output reg [4:0] out;
   input [3:0] a,b;
   input [2:0] s;

   always @(a,b,s) begin
       case(s)
       3'b000:out=a;
       3'b001:out=a+b;
       3'b010:out=a-b;
       3'b011:out=a/b;
       3'b100:out=a%b;
       3'b101:out=a<<1;
       3'b110:out=a>>1;
       3'b111:out=(a>b);
       endcase
   end
endmodule