data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:38: Cannot find file containing module: \'setting_reg\'\n   setting_reg #(.my_addr(BASE),.width(1)) sr_8to16\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.sv\n             setting_reg\n             setting_reg.v\n             setting_reg.sv\n             obj_dir/setting_reg\n             obj_dir/setting_reg.v\n             obj_dir/setting_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_streamid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_classid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_classid\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_secs\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_tics\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:63: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'has_tics\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [3:0]   hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;\n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:75: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'is_odd\' generates 1 bits.\n                                                                                            : ... In instance dspengine_8to16\n   wire [15:0]        data_in_lenx2 = {data_in_len[14:0], 1\'b0} - is_odd;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:106: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'hdr_length\' generates 4 bits.\n                                                                                             : ... In instance dspengine_8to16\n       hdr_length_reg <= hdr_length;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:113: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                             : ... In instance dspengine_8to16\n     read_adr <= access_dat_i[15:0] + HEADER_OFFSET - 1;  \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:116: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'hdr_length\' generates 4 bits.\n                                                                                             : ... In instance dspengine_8to16\n     data_in_len <= access_dat_i[15:0] - hdr_length - 1  ;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:127: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                             : ... In instance dspengine_8to16\n       write_adr <= hdr_length_reg + data_in_lenx2 + HEADER_OFFSET;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:135: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'write_adr\' generates 9 bits.\n                                                                                             : ... In instance dspengine_8to16\n       new_header[15:0] <= write_adr + (1 - HEADER_OFFSET);  \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:154: Operator EQ expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'write_adr\' generates 9 bits.\n                                                                                             : ... In instance dspengine_8to16\n       if(write_adr == (hdr_length_reg+HEADER_OFFSET))\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:165: Operator EQ expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'write_adr\' generates 9 bits.\n                                                                                             : ... In instance dspengine_8to16\n       if(write_adr == (hdr_length_reg+HEADER_OFFSET))\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dspengine_8to16.v:198: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s CONST \'34\'hdeadbeef\' generates 34 bits.\n                                                                                             : ... In instance dspengine_8to16\n    (dsp_state == DSP_WRITE_1) ? { 4\'h0, i8_1, 8\'d0, q8_1, 8\'d0 } :\n                               ^\n%Error: Exiting due to 1 error(s), 15 warning(s)\n'
module dspengine_8to16
  #(parameter BASE = 0,
    parameter BUF_SIZE = 9,
    parameter HEADER_OFFSET = 0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,

    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
    );

   wire 	 convert;
   
   setting_reg #(.my_addr(BASE),.width(1)) sr_8to16
     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(convert),.changed());
   
   reg [3:0] 	 dsp_state;
   localparam DSP_IDLE = 0;
   localparam DSP_IDLE_RD = 1;
   localparam DSP_PARSE_HEADER = 2;
   localparam DSP_READ = 3;
   localparam DSP_READ_WAIT = 4;
   localparam DSP_WRITE_1 = 5;
   localparam DSP_WRITE_0 = 6;
   localparam DSP_READ_TRAILER = 7;
   localparam DSP_WRITE_TRAILER = 8;
   localparam DSP_WRITE_HEADER = 9;
   localparam DSP_DONE = 10;
   

   wire 	 is_if_data = (access_dat_i[31:29] == 3'b000);
   wire 	 has_streamid = access_dat_i[28];
   wire 	 has_classid = access_dat_i[27];
   wire 	 has_trailer = access_dat_i[26];

   wire 	 has_secs = |access_dat_i[23:22];
   wire 	 has_tics = |access_dat_i[21:20];
   wire [3:0] 	 hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;
   reg [15:0] 	 hdr_length_reg;
 	 
   reg 		 odd;
   
   reg [BUF_SIZE-1:0] read_adr, write_adr;
   reg 		      has_trailer_reg;
   
   reg [31:0] 	      new_header, new_trailer, trailer_mask;
   reg 		      wait_for_trailer;
   reg [15:0] 	      data_in_len;
   wire       	      is_odd = access_dat_i[22] & access_dat_i[10];
   wire [15:0] 	      data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd;

   reg [7:0] 	      i8_0, q8_0;
   wire [7:0] 	      i8_1 = access_dat_i[15:8];
   wire [7:0] 	      q8_1 = access_dat_i[7:0];
   reg 		      skip;
   

   always @(posedge clk)
     { i8_0, q8_0 } <= access_dat_i[31:16];
   
   always @(posedge clk)
     if(reset | clear)
       dsp_state <= DSP_IDLE;
     else
       case(dsp_state)
	 DSP_IDLE :
	   begin
	      read_adr <= HEADER_OFFSET;
	      write_adr <= HEADER_OFFSET;
	      if(access_ok)
		dsp_state <= DSP_IDLE_RD;
	   end

	 DSP_IDLE_RD:
		dsp_state <= DSP_PARSE_HEADER;

	 DSP_PARSE_HEADER :
	   begin
	      has_trailer_reg <= has_trailer;
	      new_header[31:0] <= access_dat_i[31:0];
	      hdr_length_reg <= hdr_length;
	      if(~is_if_data | ~convert | ~has_trailer)


		dsp_state <= DSP_WRITE_HEADER;  
	      else
		begin
		   read_adr <= access_dat_i[15:0] + HEADER_OFFSET - 1;
		   dsp_state <= DSP_READ_TRAILER;
		   wait_for_trailer <= 0;
		   data_in_len <= access_dat_i[15:0] - hdr_length - 1;
		end
	   end
	 
	 DSP_READ_TRAILER :
	   begin
	      wait_for_trailer <= 1;
	      if(wait_for_trailer)
		dsp_state <= DSP_WRITE_TRAILER;
	      new_trailer <= access_dat_i[31:0];
	      odd <= is_odd;
	      write_adr <= hdr_length_reg + data_in_lenx2 + HEADER_OFFSET;
	   end

	 DSP_WRITE_TRAILER :
	   begin
	      dsp_state <= DSP_READ;
	      write_adr <= write_adr - 1;
	      read_adr <= read_adr - 1;
	      new_header[15:0] <= write_adr + (1 - HEADER_OFFSET);
	   end

	 DSP_READ :
	   begin
	      read_adr <= read_adr - 1;
	      if(odd)
		dsp_state <= DSP_READ_WAIT;
	      else
		dsp_state <= DSP_WRITE_1;
	      odd <= 0;
	   end

	 DSP_READ_WAIT :
	   dsp_state <= DSP_WRITE_0;
	 
	 DSP_WRITE_1 :
	   begin
	      write_adr <= write_adr - 1;
	      if(write_adr == (hdr_length_reg+HEADER_OFFSET))
		begin
		   write_adr <= HEADER_OFFSET;
		   dsp_state <= DSP_WRITE_HEADER;
		end
	      dsp_state <= DSP_WRITE_0;
	   end

	 DSP_WRITE_0 :
	   begin
	      write_adr <= write_adr - 1;
	      if(write_adr == (hdr_length_reg+HEADER_OFFSET))
		begin
		   write_adr <= HEADER_OFFSET;
		   dsp_state <= DSP_WRITE_HEADER;
		end
	      else
		dsp_state <= DSP_READ;
	   end

	 DSP_WRITE_HEADER :
	   dsp_state <= DSP_DONE;

	 DSP_DONE :
	   begin
	      read_adr <= HEADER_OFFSET;
	      write_adr <= HEADER_OFFSET;
	      dsp_state <= DSP_IDLE;
	   end
       endcase

   assign access_skip_read = 0;
   assign access_done = (dsp_state == DSP_DONE);

   assign access_stb = 1;

   assign access_we = (dsp_state == DSP_WRITE_HEADER) | 
		      (dsp_state == DSP_WRITE_TRAILER) |
		      (dsp_state == DSP_WRITE_0) |
		      (dsp_state == DSP_WRITE_1);
   
   assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h0, new_header } :
			 (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
			 (dsp_state == DSP_WRITE_0) ? { 4'h0, i8_0, 8'd0, q8_0, 8'd0 } :
			 (dsp_state == DSP_WRITE_1) ? { 4'h0, i8_1, 8'd0, q8_1, 8'd0 } :
			 34'h0DEADBEEF;
         
   assign access_adr = access_we ? write_adr : read_adr;
      
endmodule
module dspengine_8to16
  #(parameter BASE = 0,
    parameter BUF_SIZE = 9,
    parameter HEADER_OFFSET = 0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,

    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
    );


   wire 	 convert;
   
   setting_reg #(.my_addr(BASE),.width(1)) sr_8to16
     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(convert),.changed());
   
   reg [3:0] 	 dsp_state;
   localparam DSP_IDLE = 0;
   localparam DSP_IDLE_RD = 1;
   localparam DSP_PARSE_HEADER = 2;
   localparam DSP_READ = 3;
   localparam DSP_READ_WAIT = 4;
   localparam DSP_WRITE_1 = 5;
   localparam DSP_WRITE_0 = 6;
   localparam DSP_READ_TRAILER = 7;
   localparam DSP_WRITE_TRAILER = 8;
   localparam DSP_WRITE_HEADER = 9;
   localparam DSP_DONE = 10;
   

   wire 	 is_if_data = (access_dat_i[31:29] == 3'b000);
   wire 	 has_streamid = access_dat_i[28];
   wire 	 has_classid = access_dat_i[27];
   wire 	 has_trailer = access_dat_i[26];

   wire 	 has_secs = |access_dat_i[23:22];
   wire 	 has_tics = |access_dat_i[21:20];
   wire [3:0] 	 hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;
   reg [15:0] 	 hdr_length_reg;
 	 
   reg 		 odd;
   
   reg [BUF_SIZE-1:0] read_adr, write_adr;
   reg 		      has_trailer_reg;
   
   reg [31:0] 	      new_header, new_trailer, trailer_mask;
   reg 		      wait_for_trailer;
   reg [15:0] 	      data_in_len;
   wire       	      is_odd = access_dat_i[22] & access_dat_i[10];
   wire [15:0] 	      data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd;

   reg [7:0] 	      i8_0, q8_0;
   wire [7:0] 	      i8_1 = access_dat_i[15:8];
   wire [7:0] 	      q8_1 = access_dat_i[7:0];
   reg 		      skip;
   

   always @(posedge clk)
     { i8_0, q8_0 } <= access_dat_i[31:16];
   
   always @(posedge clk)
     if(reset | clear)
       dsp_state <= DSP_IDLE;
     else
       case(dsp_state)
	 DSP_IDLE :
	   begin
	      read_adr <= HEADER_OFFSET;
	      write_adr <= HEADER_OFFSET;
	      if(access_ok)
		dsp_state <= DSP_IDLE_RD;
	   end

	 DSP_IDLE_RD:
		dsp_state <= DSP_PARSE_HEADER;

	 DSP_PARSE_HEADER :
	   begin
	      has_trailer_reg <= has_trailer;
	      new_header[31:0] <= access_dat_i[31:0];
	      hdr_length_reg <= hdr_length;
	      if(~is_if_data | ~convert | ~has_trailer)


		dsp_state <= DSP_WRITE_HEADER;  
	      else
		begin
		   read_adr <= access_dat_i[15:0] + HEADER_OFFSET - 1;
		   dsp_state <= DSP_READ_TRAILER;
		   wait_for_trailer <= 0;
		   data_in_len <= access_dat_i[15:0] - hdr_length - 1;
		end
	   end
	 
	 DSP_READ_TRAILER :
	   begin
	      wait_for_trailer <= 1;
	      if(wait_for_trailer)
		dsp_state <= DSP_WRITE_TRAILER;
	      new_trailer <= access_dat_i[31:0];
	      odd <= is_odd;
	      write_adr <= hdr_length_reg + data_in_lenx2 + HEADER_OFFSET;
	   end

	 DSP_WRITE_TRAILER :
	   begin
	      dsp_state <= DSP_READ;
	      write_adr <= write_adr - 1;
	      read_adr <= read_adr - 1;
	      new_header[15:0] <= write_adr + (1 - HEADER_OFFSET);
	   end

	 DSP_READ :
	   begin
	      read_adr <= read_adr - 1;
	      if(odd)
		dsp_state <= DSP_READ_WAIT;
	      else
		dsp_state <= DSP_WRITE_1;
	      odd <= 0;
	   end

	 DSP_READ_WAIT :
	   dsp_state <= DSP_WRITE_0;
	 
	 DSP_WRITE_1 :
	   begin
	      write_adr <= write_adr - 1;
	      if(write_adr == (hdr_length_reg+HEADER_OFFSET))
		begin
		   write_adr <= HEADER_OFFSET;
		   dsp_state <= DSP_WRITE_HEADER;
		end
	      dsp_state <= DSP_WRITE_0;
	   end

	 DSP_WRITE_0 :
	   begin
	      write_adr <= write_adr - 1;
	      if(write_adr == (hdr_length_reg+HEADER_OFFSET))
		begin
		   write_adr <= HEADER_OFFSET;
		   dsp_state <= DSP_WRITE_HEADER;
		end
	      else
		dsp_state <= DSP_READ;
	   end

	 DSP_WRITE_HEADER :
	   dsp_state <= DSP_DONE;

	 DSP_DONE :
	   begin
	      read_adr <= HEADER_OFFSET;
	      write_adr <= HEADER_OFFSET;
	      dsp_state <= DSP_IDLE;
	   end
       endcase

   assign access_skip_read = 0;
   assign access_done = (dsp_state == DSP_DONE);

   assign access_stb = 1;

   assign access_we = (dsp_state == DSP_WRITE_HEADER) | 
		      (dsp_state == DSP_WRITE_TRAILER) |
		      (dsp_state == DSP_WRITE_0) |
		      (dsp_state == DSP_WRITE_1);
   
   assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h0, new_header } :
			 (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
			 (dsp_state == DSP_WRITE_0) ? { 4'h0, i8_0, 8'd0, q8_0, 8'd0 } :
			 (dsp_state == DSP_WRITE_1) ? { 4'h0, i8_1, 8'd0, q8_1, 8'd0 } :
			 34'h0DEADBEEF;
         
   assign access_adr = access_we ? write_adr : read_adr;
      
endmodule