data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/PS2 Packet parser.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/PS2\n%Error: Cannot find file containing module: Packet\n%Error: Cannot find file containing module: parser.v\n%Error: Exiting due to 7 error(s)\n'
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);

    parameter BYTE1=2'b00,BYTE2=2'B01, BYTE3=2'b10, DONE=2'b11;
    reg [1:0] state;
    reg [1:0] next_state;


    always @(*)
        begin
        next_state=state;
            case(state)
                BYTE1: if(in[3]) 
                         next_state=BYTE2;
                      else
                          next_state=BYTE1;
                BYTE2:  next_state=BYTE3;
                BYTE3: next_state=DONE;
                DONE: if(in[3]) 
             next_state=BYTE2;
                 else
              next_state=BYTE1;  
             
             endcase   
       end
            always @(posedge clk)
                begin
                    if (reset)
                         state=BYTE1;
                      else
                         state=next_state;
                end
    

            assign done =(state==DONE)?1'b1:1'b0;

endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);


    parameter BYTE1=2'b00,BYTE2=2'B01, BYTE3=2'b10, DONE=2'b11;
    reg [1:0] state;
    reg [1:0] next_state;


    always @(*)
        begin
        next_state=state;
            case(state)
                BYTE1: if(in[3]) 
                         next_state=BYTE2;
                      else
                          next_state=BYTE1;
                BYTE2:  next_state=BYTE3;
                BYTE3: next_state=DONE;
                DONE: if(in[3]) 
             next_state=BYTE2;
                 else
              next_state=BYTE1;  
             
             endcase   
       end
            always @(posedge clk)
                begin
                    if (reset)
                         state=BYTE1;
                      else
                         state=next_state;
                end
    

            assign done =(state==DONE)?1'b1:1'b0;

endmodule