data/full_repos/permissive/492140037/CPU/仿真文件/main_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #3 reset = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #100 status = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #1000 submit = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #3000 submit = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #1000 submit = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #3000 submit = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1000 submit = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #3000 submit = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #1000 submit = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #3000 submit = 1\'b0;\n    ^\n%Error: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/main_sim.v:11: Cannot find file containing module: \'main\'\nmain main(clk, reset, leds, switches, submit, status, seg_en, seg_out);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/main\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/main.v\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_sim();

reg clk, reset, submit, status;
reg[23:0] switches;
wire[23:0] leds;

wire[7:0] seg_en, seg_out;

main main(clk, reset, leds, switches, submit, status, seg_en, seg_out);

initial begin
    clk = 1'b0;
    reset = 1'b1;
    #3 reset = 1'b0;
    forever begin
        #5 clk = ~clk;
    end
end











































initial begin
    submit = 1'b0;
    status = 1'b0;
    switches = {8'h00, 16'd3};
    #100 status = 1'b1;

    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd13};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd9};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd4};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

end

endmodule
module main_sim();


reg clk, reset, submit, status;
reg[23:0] switches;
wire[23:0] leds;

wire[7:0] seg_en, seg_out;

main main(clk, reset, leds, switches, submit, status, seg_en, seg_out);

initial begin
    clk = 1'b0;
    reset = 1'b1;
    #3 reset = 1'b0;
    forever begin
        #5 clk = ~clk;
    end
end











































initial begin
    submit = 1'b0;
    status = 1'b0;
    switches = {8'h00, 16'd3};
    #100 status = 1'b1;

    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd13};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd9};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

    switches = {8'h00, 16'd4};
    #1000 submit = 1'b1;
    #3000 submit = 1'b0;

end

endmodule