data/full_repos/permissive/46078519/crt_test.v
1: b'%Error: data/full_repos/permissive/46078519/crt_test.v:2: Cannot find include file: crt.v\n`include "crt.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v.v\n             data/full_repos/permissive/46078519,data/full_repos/permissive/46078519/crt.v.sv\n             crt.v\n             crt.v.v\n             crt.v.sv\n             obj_dir/crt.v\n             obj_dir/crt.v.v\n             obj_dir/crt.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/46078519/crt_test.v:40: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("crt_test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/46078519/crt_test.v:41: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, crt_test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:84: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:88: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:90: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'h9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hA;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hC;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:94: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:96: Unsupported: Ignoring delay on this delayed statement.\n #2 outaddr <= 4\'hF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:97: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:101: Unsupported: Ignoring delay on this delayed statement.\n #1320402;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/46078519/crt_test.v:114: Unsupported: Ignoring delay on this delayed statement.\n #(2201*1125*2*2+30) $finish;\n ^\n%Error: Exiting due to 3 error(s), 26 warning(s)\n'
module crt_test;

reg clk;
initial clk = 0;
always #1 clk <= ~clk;

reg reset;

reg cs, we;
wire [15:0] data;
wire [3:0] addr;
reg [3:0] outaddr;
reg [15:0] outdata;
wire irq;
wire hs, vs;
wire ven;
wire [31:0] pixaddr;
assign data = we ? outdata : 16'bz;
assign addr = cs ? outaddr : 4'bz;

crt uut(
	.clk(clk),
	.reset(reset),
	.cs(cs),
	.we(we),
	.addr(addr),
	.data(data),
	.irq(irq),
	.vs(vs),
	.hs(hs),
	.ven(ven),
	.pixaddr(pixaddr)
);

initial
begin
	$dumpfile("crt_test.vcd");
	$dumpvars(0, crt_test);
	
	reset <= 1;
	cs <= 0;
	we <= 0;
	
	#2;
	reset <= 0;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hC;
	outdata <= 16'd200;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hD;
	outdata <= 16'd300;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hF;
	outdata <= 16'b1000000000000010;
	
	#2;
	cs <= 1'b0;
	we <= 1'b0;
	outaddr <= 4'h0;
	outdata <= 16'bz;
	

	#2;
	cs <= 1'b1;
	we <= 1'b0;
	outaddr <= 4'h0;
	#2 outaddr <= 4'h1;
	#2 outaddr <= 4'h2;
	#2 outaddr <= 4'h3;
	#2 outaddr <= 4'h4;
	#2 outaddr <= 4'h5;
	#2 outaddr <= 4'h6;
	#2 outaddr <= 4'h7;
	#2 outaddr <= 4'h8;
	#2 outaddr <= 4'h9;
	#2 outaddr <= 4'hA;
	#2 outaddr <= 4'hB;
	#2 outaddr <= 4'hC;
	#2 outaddr <= 4'hD;
	#2 outaddr <= 4'hE;
	#2 outaddr <= 4'hF;
	#2;
	cs <= 1'b0;
	outaddr <= 4'h1;
	
	#1320402;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hE;
	outdata <= 16'b0;

	#2;
	cs <= 1'b0;
	we <= 1'b0;
	outaddr <= 4'h0;
	outdata <= 16'b0;


	#(2201*1125*2*2+30) $finish;
end

endmodule
module crt_test;


reg clk;
initial clk = 0;
always #1 clk <= ~clk;

reg reset;

reg cs, we;
wire [15:0] data;
wire [3:0] addr;
reg [3:0] outaddr;
reg [15:0] outdata;
wire irq;
wire hs, vs;
wire ven;
wire [31:0] pixaddr;
assign data = we ? outdata : 16'bz;
assign addr = cs ? outaddr : 4'bz;

crt uut(
	.clk(clk),
	.reset(reset),
	.cs(cs),
	.we(we),
	.addr(addr),
	.data(data),
	.irq(irq),
	.vs(vs),
	.hs(hs),
	.ven(ven),
	.pixaddr(pixaddr)
);

initial
begin
	$dumpfile("crt_test.vcd");
	$dumpvars(0, crt_test);
	
	reset <= 1;
	cs <= 0;
	we <= 0;
	
	#2;
	reset <= 0;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hC;
	outdata <= 16'd200;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hD;
	outdata <= 16'd300;
	

	#2;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hF;
	outdata <= 16'b1000000000000010;
	
	#2;
	cs <= 1'b0;
	we <= 1'b0;
	outaddr <= 4'h0;
	outdata <= 16'bz;
	

	#2;
	cs <= 1'b1;
	we <= 1'b0;
	outaddr <= 4'h0;
	#2 outaddr <= 4'h1;
	#2 outaddr <= 4'h2;
	#2 outaddr <= 4'h3;
	#2 outaddr <= 4'h4;
	#2 outaddr <= 4'h5;
	#2 outaddr <= 4'h6;
	#2 outaddr <= 4'h7;
	#2 outaddr <= 4'h8;
	#2 outaddr <= 4'h9;
	#2 outaddr <= 4'hA;
	#2 outaddr <= 4'hB;
	#2 outaddr <= 4'hC;
	#2 outaddr <= 4'hD;
	#2 outaddr <= 4'hE;
	#2 outaddr <= 4'hF;
	#2;
	cs <= 1'b0;
	outaddr <= 4'h1;
	
	#1320402;
	cs <= 1'b1;
	we <= 1'b1;
	outaddr <= 4'hE;
	outdata <= 16'b0;

	#2;
	cs <= 1'b0;
	we <= 1'b0;
	outaddr <= 4'h0;
	outdata <= 16'b0;


	#(2201*1125*2*2+30) $finish;
end

endmodule