data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:265: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:274: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:278: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:264: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:290: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:299: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:303: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:289: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:322: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 8 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 16 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:326: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b010: mem_out6 = {16\'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:313: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n  if ((core_l15_rqtype == 4\'b0000) & (l15_core_val == 1)) begin\n                       ^~\n%Error: Exiting due to 15 warning(s)\n'
module piton_fsm (
	clk,
	nrst,
	addr6,
	data_in6,
	m_rd6,
	bw06,
	bw16,
	bw26,
	bw36,
	m_op6,
	mem_op6,
	core_l15_rqtype,
	core_l15_size,
	core_l15_address,
	core_l15_data,
	core_l15_val,
	l15_core_data_0,
	l15_core_data_1,
	l15_core_returntype,
	l15_core_val,
	l15_core_ack,
	l15_core_header_ack,
	core_l15_req_ack,
	mem_out6,
	memOp_done
);
	input wire clk;
	input wire nrst;
	input wire [31:0] addr6;
	input wire [31:0] data_in6;
	input wire m_rd6;
	input wire bw06;
	input wire bw16;
	input wire bw26;
	input wire bw36;
	input wire m_op6;
	input wire [3:0] mem_op6;
	output reg [4:0] core_l15_rqtype;
	output reg [2:0] core_l15_size;
	output reg [31:0] core_l15_address;
	output reg [63:0] core_l15_data;
	output reg core_l15_val;
	input wire [63:0] l15_core_data_0;
	input wire [63:0] l15_core_data_1;
	input wire [3:0] l15_core_returntype;
	input wire l15_core_val;
	input wire l15_core_ack;
	input wire l15_core_header_ack;
	output wire core_l15_req_ack;
	output reg [31:0] mem_out6;
	output reg memOp_done;
	reg state_reg;
	wire req_fire;
	wire resp_int;
	wire resp_fire;
	wire [31:0] wdata;
	wire [3:0] bw;
	reg [3:0] mem_opReg;
	reg [1:0] baddr;
	wire [3:0] rqtypeReg;
	wire [31:0] addrReg;
	reg [31:0] rdata;
	reg [31:0] piton_out;
	assign req_fire = (l15_core_header_ack && (state_reg == 1'd0)) && m_op6;
	assign resp_fire = l15_core_val && (state_reg == 1'd1);
	assign wdata = {data_in6[7:0], data_in6[15:8], data_in6[23:16], data_in6[31:24]};
	assign bw = {bw36, bw26, bw16, bw06};
	assign core_l15_req_ack = resp_fire || l15_core_val;
	always @(posedge clk or negedge nrst)
		if (!nrst)
			state_reg <= 1'd0;
		else
			case (state_reg)
				1'd0:
					if (req_fire) begin
						state_reg <= 1'd1;
						mem_opReg <= mem_op6;
					end
				1'd1:
					if (resp_fire)
						case (core_l15_rqtype)
							4'b0000:
								if (l15_core_returntype == 4'b0000)
									state_reg <= 1'd0;
							4'b0001:
								if (l15_core_returntype == 4'b0100)
									state_reg <= 1'd0;
							default: state_reg <= state_reg;
						endcase
			endcase
	always @(*)
		case (state_reg)
			1'd0: begin
				memOp_done = 0;
				baddr = addr6[1:0];
				core_l15_data = {wdata, wdata};
				core_l15_address = addr6;
				core_l15_val = m_op6;
				if (bw) begin
					core_l15_rqtype = 4'b0001;
					case (bw)
						4'b1111: core_l15_size = 3'b011;
						4'b1100, 4'b0011: core_l15_size = 3'b010;
						4'b0001, 4'b0010, 4'b0100, 4'b1000: core_l15_size = 3'b001;
						default: core_l15_size = 3'b000;
					endcase
				end
				else if (m_rd6) begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
				else begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
			end
			1'd1: begin
				core_l15_val = 0;
				memOp_done = l15_core_val;
				baddr = addr6[1:0];
				core_l15_data = {wdata, wdata};
				core_l15_address = addr6;
				core_l15_val = m_op6;
				if (bw) begin
					core_l15_rqtype = 4'b0001;
					case (bw)
						4'b1111: core_l15_size = 3'b011;
						4'b1100, 4'b0011: core_l15_size = 3'b010;
						4'b0001, 4'b0010, 4'b0100, 4'b1000: core_l15_size = 3'b001;
						default: core_l15_size = 3'b000;
					endcase
				end
				else if (m_rd6) begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
				else begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
			end
		endcase
	function automatic signed [31:0] sv2v_cast_32_signed;
		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction
	always @(*)
		if ((core_l15_rqtype == 4'b0000) & (l15_core_val == 1)) begin
			case (core_l15_address[3:2])
				2'b00: rdata = l15_core_data_0[63:32];
				2'b01: rdata = l15_core_data_0[31:0];
				2'b10: rdata = l15_core_data_1[63:32];
				2'b11: rdata = l15_core_data_1[31:0];
			endcase
			piton_out = {rdata[7:0], rdata[15:8], rdata[23:16], rdata[31:24]};
			case (mem_opReg[2:0])
				3'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));
				3'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));
				3'b111: mem_out6 = piton_out;
				3'b100: mem_out6 = {24'b000000000000000000000000, piton_out[baddr * 8+:8]};
				3'b010: mem_out6 = {16'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};
				default: mem_out6 = 0;
			endcase
		end
		else
			mem_out6 = 0;
endmodule
module piton_fsm (
	clk,
	nrst,
	addr6,
	data_in6,
	m_rd6,
	bw06,
	bw16,
	bw26,
	bw36,
	m_op6,
	mem_op6,
	core_l15_rqtype,
	core_l15_size,
	core_l15_address,
	core_l15_data,
	core_l15_val,
	l15_core_data_0,
	l15_core_data_1,
	l15_core_returntype,
	l15_core_val,
	l15_core_ack,
	l15_core_header_ack,
	core_l15_req_ack,
	mem_out6,
	memOp_done
);

	input wire clk;
	input wire nrst;
	input wire [31:0] addr6;
	input wire [31:0] data_in6;
	input wire m_rd6;
	input wire bw06;
	input wire bw16;
	input wire bw26;
	input wire bw36;
	input wire m_op6;
	input wire [3:0] mem_op6;
	output reg [4:0] core_l15_rqtype;
	output reg [2:0] core_l15_size;
	output reg [31:0] core_l15_address;
	output reg [63:0] core_l15_data;
	output reg core_l15_val;
	input wire [63:0] l15_core_data_0;
	input wire [63:0] l15_core_data_1;
	input wire [3:0] l15_core_returntype;
	input wire l15_core_val;
	input wire l15_core_ack;
	input wire l15_core_header_ack;
	output wire core_l15_req_ack;
	output reg [31:0] mem_out6;
	output reg memOp_done;
	reg state_reg;
	wire req_fire;
	wire resp_int;
	wire resp_fire;
	wire [31:0] wdata;
	wire [3:0] bw;
	reg [3:0] mem_opReg;
	reg [1:0] baddr;
	wire [3:0] rqtypeReg;
	wire [31:0] addrReg;
	reg [31:0] rdata;
	reg [31:0] piton_out;
	assign req_fire = (l15_core_header_ack && (state_reg == 1'd0)) && m_op6;
	assign resp_fire = l15_core_val && (state_reg == 1'd1);
	assign wdata = {data_in6[7:0], data_in6[15:8], data_in6[23:16], data_in6[31:24]};
	assign bw = {bw36, bw26, bw16, bw06};
	assign core_l15_req_ack = resp_fire || l15_core_val;
	always @(posedge clk or negedge nrst)
		if (!nrst)
			state_reg <= 1'd0;
		else
			case (state_reg)
				1'd0:
					if (req_fire) begin
						state_reg <= 1'd1;
						mem_opReg <= mem_op6;
					end
				1'd1:
					if (resp_fire)
						case (core_l15_rqtype)
							4'b0000:
								if (l15_core_returntype == 4'b0000)
									state_reg <= 1'd0;
							4'b0001:
								if (l15_core_returntype == 4'b0100)
									state_reg <= 1'd0;
							default: state_reg <= state_reg;
						endcase
			endcase
	always @(*)
		case (state_reg)
			1'd0: begin
				memOp_done = 0;
				baddr = addr6[1:0];
				core_l15_data = {wdata, wdata};
				core_l15_address = addr6;
				core_l15_val = m_op6;
				if (bw) begin
					core_l15_rqtype = 4'b0001;
					case (bw)
						4'b1111: core_l15_size = 3'b011;
						4'b1100, 4'b0011: core_l15_size = 3'b010;
						4'b0001, 4'b0010, 4'b0100, 4'b1000: core_l15_size = 3'b001;
						default: core_l15_size = 3'b000;
					endcase
				end
				else if (m_rd6) begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
				else begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
			end
			1'd1: begin
				core_l15_val = 0;
				memOp_done = l15_core_val;
				baddr = addr6[1:0];
				core_l15_data = {wdata, wdata};
				core_l15_address = addr6;
				core_l15_val = m_op6;
				if (bw) begin
					core_l15_rqtype = 4'b0001;
					case (bw)
						4'b1111: core_l15_size = 3'b011;
						4'b1100, 4'b0011: core_l15_size = 3'b010;
						4'b0001, 4'b0010, 4'b0100, 4'b1000: core_l15_size = 3'b001;
						default: core_l15_size = 3'b000;
					endcase
				end
				else if (m_rd6) begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
				else begin
					core_l15_rqtype = 4'b0000;
					core_l15_size = 3'b011;
				end
			end
		endcase
	function automatic signed [31:0] sv2v_cast_32_signed;
		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction
	always @(*)
		if ((core_l15_rqtype == 4'b0000) & (l15_core_val == 1)) begin
			case (core_l15_address[3:2])
				2'b00: rdata = l15_core_data_0[63:32];
				2'b01: rdata = l15_core_data_0[31:0];
				2'b10: rdata = l15_core_data_1[63:32];
				2'b11: rdata = l15_core_data_1[31:0];
			endcase
			piton_out = {rdata[7:0], rdata[15:8], rdata[23:16], rdata[31:24]};
			case (mem_opReg[2:0])
				3'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));
				3'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));
				3'b111: mem_out6 = piton_out;
				3'b100: mem_out6 = {24'b000000000000000000000000, piton_out[baddr * 8+:8]};
				3'b010: mem_out6 = {16'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};
				default: mem_out6 = 0;
			endcase
		end
		else
			mem_out6 = 0;
endmodule