data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ring_osc(
    output osc_out
    );
  
   
   localparam [3:0] length = 4'd15;
   wire [length:0] del;
   assign del[0] = del[length]; 
    

    
   genvar i;
   generate 
   for (i=0; i<length; i=i+1)begin
      sky130_fd_sc_hd__inv_2 inverters (
        .A(del[i]),
        .Y(del[i+1])
      );
   end
   endgenerate
    
   assign osc_out = del[length];  
   
endmodule
module ring_osc(
    output osc_out
    );

  
   
   localparam [3:0] length = 4'd15;
   wire [length:0] del;
   assign del[0] = del[length]; 
    

    
   genvar i;
   generate 
   for (i=0; i<length; i=i+1)begin
      sky130_fd_sc_hd__inv_2 inverters (
        .A(del[i]),
        .Y(del[i+1])
      );
   end
   endgenerate
    
   assign osc_out = del[length];  
   
endmodule