data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:23: Cannot find include file: ../genericIOSateliteEnv.v\n`include "../genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:24: Cannot find include file: ../genericIOSateliteEnv_TB.v\n`include "../genericIOSateliteEnv_TB.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:25: Cannot find include file: shiftReg.v\n`include "shiftReg.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:43: Define or directive not defined: \'`OSCH_FREQ\'\n OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1\'b0), .OSC(masterClk), .SEDSTDBY ());\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:63: Define or directive not defined: \'`LOAD_SERIAL_GEN_32\'\n  `LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8\'h55, 8\'hAA, 8\'h00, 8\'hFF)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:63: syntax error, unexpected \',\'\n  `LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8\'h55, 8\'hAA, 8\'h00, 8\'hFF)\n                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:65: Define or directive not defined: \'`SHIFT_SERIAL_GEN_32\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:65: syntax error, unexpected \',\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n                                 ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:65: Define or directive not defined: \'`K800_NS\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n                                                                               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:68: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("shiftReg", parallelOutput, 8\'h55, 8\'hAA, 8\'h00, 8\'hFF)\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:68: syntax error, unexpected \',\'\n  `CHECK_WIRE_32("shiftReg", parallelOutput, 8\'h55, 8\'hAA, 8\'h00, 8\'hFF)\n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:72: Define or directive not defined: \'`SET_WIRE_32\'\n  `SET_WIRE_32("shiftReg", parallelInput, 8\'h0F, 8\'h1E, 8\'h2D, 8\'h3C)\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:72: syntax error, unexpected \',\'\n  `SET_WIRE_32("shiftReg", parallelInput, 8\'h0F, 8\'h1E, 8\'h2D, 8\'h3C)\n                         ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:73: Define or directive not defined: \'`LOAD_SERIAL_GEN_32\'\n  `LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n  ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:78: Define or directive not defined: \'`CHECK_WIRE_1\'\n  `CHECK_WIRE_1("shiftReg", loaded, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:78: syntax error, unexpected \',\'\n  `CHECK_WIRE_1("shiftReg", loaded, 1\'b1)\n                          ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:79: Define or directive not defined: \'`SHIFT_SERIAL_GEN_32\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:79: Define or directive not defined: \'`K800_NS\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n                                                                               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:82: Define or directive not defined: \'`CHECK_WIRE_1\'\n  `CHECK_WIRE_1("shiftReg", loaded, 1\'b0)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:82: syntax error, unexpected \',\'\n  `CHECK_WIRE_1("shiftReg", loaded, 1\'b0)\n                          ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:83: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("shiftReg", parallelOutput,  8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:84: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("shiftReg", result,  8\'h0F, 8\'h1E, 8\'h2D, 8\'h3C)\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:89: Define or directive not defined: \'`LOAD_SERIAL_GEN_32\'\n  `LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:89: syntax error, unexpected \',\'\n  `LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:90: Define or directive not defined: \'`SHIFT_SERIAL_GEN_32\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:90: Define or directive not defined: \'`K800_NS\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:91: Define or directive not defined: \'`SHIFT_SERIAL_GEN_32\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:91: Define or directive not defined: \'`K800_NS\'\n  `SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)\n                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:93: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("shiftReg", result,  8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg_TB.v:93: syntax error, unexpected \',\'\n  `CHECK_WIRE_32("shiftReg", result,  8\'hFF, 8\'hAA, 8\'h55, 8\'h00)\n                           ^\n%Error: Exiting due to 30 error(s), 3 warning(s)\n'
module shiftReg_TB ();
	reg[31:0] parallelInput;
	wire masterClk;
	reg serialInput;
	reg clk;
	reg load;
	reg enableShift;
	wire[31:0] parallelOutput;
	wire serialOutput;
	wire loaded;

	reg[31:0] result;
	reg[31:0] serialGen;
	integer shiftIndex, shiftOutIndex, valIndex;

	shiftReg #(.WIDTH(32)) DUT(.parallelInput(parallelInput), .serialInput(serialInput), .clk(clk), .load(load), .enableShift(enableShift), .masterClk(masterClk), .parallelOutput(parallelOutput), .serialOutput(serialOutput), .loaded(loaded));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());

	always @(negedge clk) begin
		for(shiftIndex=31; shiftIndex>0; shiftIndex=shiftIndex-1) begin
				result[shiftIndex] <= result[shiftIndex-1];
		end
		result[0] <= serialOutput;
	end

	initial begin
		$display("shiftReg: Running simulation for a 32 bit shift reg");
		$display("ws2811Decoder: Initializing simulation for WS2811Decoder");

		clk = 1'b0;
		load = 1'b0;
		enableShift = 1'b0;
		serialInput = 1'b0;
		parallelInput = 32'b0;


		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'h55, 8'hAA, 8'h00, 8'hFF)
		enableShift = 1'b1;
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		#100;
		`CHECK_WIRE_32("shiftReg", parallelOutput, 8'h55, 8'hAA, 8'h00, 8'hFF)
		#1000;


		`SET_WIRE_32("shiftReg", parallelInput, 8'h0F, 8'h1E, 8'h2D, 8'h3C)
		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'hFF, 8'hAA, 8'h55, 8'h00)
		enableShift = 1'b1;
		load = 1'b1;
		#100;
		load = 1'b0;
		`CHECK_WIRE_1("shiftReg", loaded, 1'b1)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		#100;
		`CHECK_WIRE_1("shiftReg", loaded, 1'b0)
		`CHECK_WIRE_32("shiftReg", parallelOutput,  8'hFF, 8'hAA, 8'h55, 8'h00)
		`CHECK_WIRE_32("shiftReg", result,  8'h0F, 8'h1E, 8'h2D, 8'h3C)
		#1000;


		enableShift = 1'b1;
		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'hFF, 8'hAA, 8'h55, 8'h00)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		`CHECK_WIRE_32("shiftReg", result,  8'hFF, 8'hAA, 8'h55, 8'h00)
		$display("shiftReg: Simulation successful");
		$stop;
	end
endmodule
module shiftReg_TB ();

	reg[31:0] parallelInput;
	wire masterClk;
	reg serialInput;
	reg clk;
	reg load;
	reg enableShift;
	wire[31:0] parallelOutput;
	wire serialOutput;
	wire loaded;

	reg[31:0] result;
	reg[31:0] serialGen;
	integer shiftIndex, shiftOutIndex, valIndex;

	shiftReg #(.WIDTH(32)) DUT(.parallelInput(parallelInput), .serialInput(serialInput), .clk(clk), .load(load), .enableShift(enableShift), .masterClk(masterClk), .parallelOutput(parallelOutput), .serialOutput(serialOutput), .loaded(loaded));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());

	always @(negedge clk) begin
		for(shiftIndex=31; shiftIndex>0; shiftIndex=shiftIndex-1) begin
				result[shiftIndex] <= result[shiftIndex-1];
		end
		result[0] <= serialOutput;
	end

	initial begin
		$display("shiftReg: Running simulation for a 32 bit shift reg");
		$display("ws2811Decoder: Initializing simulation for WS2811Decoder");

		clk = 1'b0;
		load = 1'b0;
		enableShift = 1'b0;
		serialInput = 1'b0;
		parallelInput = 32'b0;


		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'h55, 8'hAA, 8'h00, 8'hFF)
		enableShift = 1'b1;
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		#100;
		`CHECK_WIRE_32("shiftReg", parallelOutput, 8'h55, 8'hAA, 8'h00, 8'hFF)
		#1000;


		`SET_WIRE_32("shiftReg", parallelInput, 8'h0F, 8'h1E, 8'h2D, 8'h3C)
		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'hFF, 8'hAA, 8'h55, 8'h00)
		enableShift = 1'b1;
		load = 1'b1;
		#100;
		load = 1'b0;
		`CHECK_WIRE_1("shiftReg", loaded, 1'b1)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		#100;
		`CHECK_WIRE_1("shiftReg", loaded, 1'b0)
		`CHECK_WIRE_32("shiftReg", parallelOutput,  8'hFF, 8'hAA, 8'h55, 8'h00)
		`CHECK_WIRE_32("shiftReg", result,  8'h0F, 8'h1E, 8'h2D, 8'h3C)
		#1000;


		enableShift = 1'b1;
		`LOAD_SERIAL_GEN_32("shiftReg", serialGen, 8'hFF, 8'hAA, 8'h55, 8'h00)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		`SHIFT_SERIAL_GEN_32("shiftReg", serialGen, serialInput, shiftOutIndex, clk, `K800_NS)
		enableShift = 1'b0;
		`CHECK_WIRE_32("shiftReg", result,  8'hFF, 8'hAA, 8'h55, 8'h00)
		$display("shiftReg: Simulation successful");
		$stop;
	end
endmodule