data/full_repos/permissive/461069000/spi/tb/spi_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS/2) clk <= !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:82: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("spi_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:83: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/spi/tb/spi_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*1000);\n        ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_tb;
    localparam CLOCK_PERIOD_NS = 100;

    reg clk = 0;
    reg rst = 1;

    reg enable_0 = 0;
    reg enable_1 = 0;
    
    reg [1:0] config_address_0 = 0;
    reg [1:0] config_address_1 = 0;
    
    reg config_write_enable_0 = 0;
    reg config_write_enable_1 = 0;
    
    reg [7:0] write_data_0 = 0;
    reg [7:0] write_data_1 = 0;

    wire [7:0] read_data_0;
    wire [7:0] read_data_1;


    wire sdi;
    wire sdo;
    wire sclk;

    wire cs;
    

    wire done_int_0;
    wire done_int_1;
    
    spi spi_0(
        .clk(clk),
        .rst(rst),
        .enable(enable_0),
        .write_enable(config_write_enable_0),
        .address(config_address_0),
        .write_data(write_data_0),
        .read_data(read_data_0),
        
        .sdi(sdi),
        .sdo(sdo),
        .cs_i(),
        .cs_o(cs),
        .sclk_i(),
        .sclk_o(sclk),

        .done_int(done_int_0)
   );

    spi spi_1(
        .clk(clk),
        .rst(rst),
        .enable(enable_1),
        .write_enable(config_write_enable_1),
        .address(config_address_1),
        .write_data(write_data_1),
        .read_data(read_data_1),
        
        .sdi(sdo),
        .sdo(sdi),
        
        .cs_o(),
        .cs_i(cs),
        .sclk_i(sclk),
        .sclk_o(),

        
        .done_int(done_int_1)
   );

  

    always 
        #(CLOCK_PERIOD_NS/2) clk <= !clk;

    initial 
    begin
        $dumpfile("spi_tb.vcd");
        $dumpvars;
        #(CLOCK_PERIOD_NS*2);
        rst = 0;
        #(CLOCK_PERIOD_NS*2);
        rst = 1;
        #(CLOCK_PERIOD_NS*2);

    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 0;
        write_data_0 = 8'b1_0_0_001_00;



    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 0;
        write_data_1 = 8'b1_1_0_000_00;


        #(CLOCK_PERIOD_NS*2);


    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 1;
        write_data_0 = 8'hFA; 


    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 1;
        write_data_1 = 8'hAD; 

        #(CLOCK_PERIOD_NS*2);



    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 0;
        write_data_0 = 8'b1_0_1_001_00;



    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 0;
        write_data_1 = 8'b1_1_1_000_00;


        #(CLOCK_PERIOD_NS*2);

       

    
        enable_0 = 1;
        config_write_enable_0 = 0;
        config_address_0 = 2;
        


    
        enable_1 = 1;
        config_write_enable_1 = 0;
        config_address_1 = 2;

        #(CLOCK_PERIOD_NS*1000);


        $finish;
    end


endmodule
module spi_tb;

    localparam CLOCK_PERIOD_NS = 100;

    reg clk = 0;
    reg rst = 1;

    reg enable_0 = 0;
    reg enable_1 = 0;
    
    reg [1:0] config_address_0 = 0;
    reg [1:0] config_address_1 = 0;
    
    reg config_write_enable_0 = 0;
    reg config_write_enable_1 = 0;
    
    reg [7:0] write_data_0 = 0;
    reg [7:0] write_data_1 = 0;

    wire [7:0] read_data_0;
    wire [7:0] read_data_1;


    wire sdi;
    wire sdo;
    wire sclk;

    wire cs;
    

    wire done_int_0;
    wire done_int_1;
    
    spi spi_0(
        .clk(clk),
        .rst(rst),
        .enable(enable_0),
        .write_enable(config_write_enable_0),
        .address(config_address_0),
        .write_data(write_data_0),
        .read_data(read_data_0),
        
        .sdi(sdi),
        .sdo(sdo),
        .cs_i(),
        .cs_o(cs),
        .sclk_i(),
        .sclk_o(sclk),

        .done_int(done_int_0)
   );

    spi spi_1(
        .clk(clk),
        .rst(rst),
        .enable(enable_1),
        .write_enable(config_write_enable_1),
        .address(config_address_1),
        .write_data(write_data_1),
        .read_data(read_data_1),
        
        .sdi(sdo),
        .sdo(sdi),
        
        .cs_o(),
        .cs_i(cs),
        .sclk_i(sclk),
        .sclk_o(),

        
        .done_int(done_int_1)
   );

  

    always 
        #(CLOCK_PERIOD_NS/2) clk <= !clk;

    initial 
    begin
        $dumpfile("spi_tb.vcd");
        $dumpvars;
        #(CLOCK_PERIOD_NS*2);
        rst = 0;
        #(CLOCK_PERIOD_NS*2);
        rst = 1;
        #(CLOCK_PERIOD_NS*2);

    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 0;
        write_data_0 = 8'b1_0_0_001_00;



    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 0;
        write_data_1 = 8'b1_1_0_000_00;


        #(CLOCK_PERIOD_NS*2);


    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 1;
        write_data_0 = 8'hFA; 


    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 1;
        write_data_1 = 8'hAD; 

        #(CLOCK_PERIOD_NS*2);



    
        enable_0 = 1;
        config_write_enable_0 = 1;
        config_address_0 = 0;
        write_data_0 = 8'b1_0_1_001_00;



    
        enable_1 = 1;
        config_write_enable_1 = 1;
        config_address_1 = 0;
        write_data_1 = 8'b1_1_1_000_00;


        #(CLOCK_PERIOD_NS*2);

       

    
        enable_0 = 1;
        config_write_enable_0 = 0;
        config_address_0 = 2;
        


    
        enable_1 = 1;
        config_write_enable_1 = 0;
        config_address_1 = 2;

        #(CLOCK_PERIOD_NS*1000);


        $finish;
    end


endmodule