data/full_repos/permissive/430260837/DesClockDivider.v
data/verilator_xmls/cf2979d4-626b-43ca-8722-d9bb35f29768.xml
module DesClockDivider(cin, start, cout);




input cin;
input start;
output reg cout;

reg[31:0] count; 
parameter D = 32'd5000000;

always @(posedge cin)
begin
	if(start) begin
		count <= count + 32'd1;
		if (count >= (D-1)) begin
			cout <= 1;
			count <= 32'd0;
		end else begin
			cout <= 0;
		end
	end else begin
		count <= 32'd0;
	end
end

endmodule
module DesClockDivider(cin, start, cout);





input cin;
input start;
output reg cout;

reg[31:0] count; 
parameter D = 32'd5000000;

always @(posedge cin)
begin
	if(start) begin
		count <= count + 32'd1;
		if (count >= (D-1)) begin
			cout <= 1;
			count <= 32'd0;
		end else begin
			cout <= 0;
		end
	end else begin
		count <= 32'd0;
	end
end

endmodule