data/full_repos/permissive/518304031/iiitb_tlc_tb.v
1: b'%Error: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("tlc_out.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0, iiitb_tlc_tb);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #60\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   # 140\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #120\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #120\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #120 sensor = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #120 sensor = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #120 sensor = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #120 sensor = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:83: Unsupported or unknown PLI call: $monitor\n   $monitor("TIME = %d, reset = %b, sensor = %b, light of highway = %h, light of farm road = %h",$time,rst_n ,sensor,light_highway,light_farm );\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518304031/iiitb_tlc_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #ENDTIME\n    ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_tlc_tb;

	parameter ENDTIME  = 40000;

	reg clk;
	reg rst_n;
	reg sensor;
	wire [2:0] light_farm;
	wire [2:0] light_highway;


	iiitb_tlc test(light_highway, light_farm, sensor, clk, rst_n);


	initial
		 begin
		 clk = 1'b0;
		 rst_n = 1'b0;
		 sensor = 1'b0;

		 end
	initial
		  begin
		   $dumpfile("tlc_out.vcd");
		   $dumpvars(0, iiitb_tlc_tb);
	  	  end


	always #1 clk = !clk;
	initial
		begin
			rst_n = 0;
			sensor = 0;
			#60
			sensor = 1;
			# 140
			rst_n = 1;
			#120
			sensor = 0;
			#120
			sensor = 1;
			#120 sensor = 0;
			#120 sensor = 1;
			#120 sensor = 0;
			#120 sensor = 1;
			#1000
			sensor = 0;
		end


	initial
		begin
			$display("----------------------------------------------");
			$display("------------------     -----------------------");
	 		$display("----------- SIMULATION RESULT ----------------");
	  		$display("--------------             -------------------");
			$display("----------------         ---------------------");
			$display("----------------------------------------------");
			$monitor("TIME = %d, reset = %b, sensor = %b, light of highway = %h, light of farm road = %h",$time,rst_n ,sensor,light_highway,light_farm );
		end

	initial
		begin
			 #ENDTIME
			 $display("-------------- THE SIMUALTION END ------------");
			 $finish;
	 	end
    
endmodule
module iiitb_tlc_tb;


	parameter ENDTIME  = 40000;

	reg clk;
	reg rst_n;
	reg sensor;
	wire [2:0] light_farm;
	wire [2:0] light_highway;


	iiitb_tlc test(light_highway, light_farm, sensor, clk, rst_n);


	initial
		 begin
		 clk = 1'b0;
		 rst_n = 1'b0;
		 sensor = 1'b0;

		 end
	initial
		  begin
		   $dumpfile("tlc_out.vcd");
		   $dumpvars(0, iiitb_tlc_tb);
	  	  end


	always #1 clk = !clk;
	initial
		begin
			rst_n = 0;
			sensor = 0;
			#60
			sensor = 1;
			# 140
			rst_n = 1;
			#120
			sensor = 0;
			#120
			sensor = 1;
			#120 sensor = 0;
			#120 sensor = 1;
			#120 sensor = 0;
			#120 sensor = 1;
			#1000
			sensor = 0;
		end


	initial
		begin
			$display("----------------------------------------------");
			$display("------------------     -----------------------");
	 		$display("----------- SIMULATION RESULT ----------------");
	  		$display("--------------             -------------------");
			$display("----------------         ---------------------");
			$display("----------------------------------------------");
			$monitor("TIME = %d, reset = %b, sensor = %b, light of highway = %h, light of farm road = %h",$time,rst_n ,sensor,light_highway,light_farm );
		end

	initial
		begin
			 #ENDTIME
			 $display("-------------- THE SIMUALTION END ------------");
			 $finish;
	 	end
    
endmodule