data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:25: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:28: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:43: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]  pcx_data_px2; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:48: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]  pcx_data_px_l; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:57: Define or directive not defined: \'`PCX_WIDTH\'\n   wire [`PCX_WIDTH-1:0]  pcx_data_px2_l; \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:60: Define or directive not defined: \'`PCX_WIDTH\'\n   dff_s #(`PCX_WIDTH) dff_cpx_data(\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:61: Define or directive not defined: \'`PCX_WIDTH\'\n            .din           (pcx_data_px_l[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:62: Define or directive not defined: \'`PCX_WIDTH\'\n     .q             (pcx_data_px2_l[`PCX_WIDTH-1:0]),\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_data_px2.v:65: Define or directive not defined: \'`PCX_WIDTH\'\n     .si            (`PCX_WIDTH\'d0),\n                     ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module pcx_data_px2(

   pcx_data_px2, pcx_data_rdy_px2, pcx_stall_pq_buf, so, 

   pcx_data_px_l, pcx_data_rdy_px, pcx_stall_pq, rclk, si, se
   );
   

   output [`PCX_WIDTH-1:0]		pcx_data_px2;	
   output 		pcx_data_rdy_px2;	
   output 		pcx_stall_pq_buf;	
   output 		so;
   
   input [`PCX_WIDTH-1:0]		pcx_data_px_l;	
   input 		pcx_data_rdy_px;	
   input 		pcx_stall_pq;	

   input 		rclk;
   input 		si;
   input 		se;
   

   wire [`PCX_WIDTH-1:0]		pcx_data_px2_l;	
   
   
   dff_s #(`PCX_WIDTH) dff_cpx_data(
            .din           (pcx_data_px_l[`PCX_WIDTH-1:0]),
	    .q             (pcx_data_px2_l[`PCX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (`PCX_WIDTH'd0),
	    .so            ());

assign pcx_data_px2 = ~pcx_data_px2_l; 



      dff_s #(1) dff_cpx_datardy(
            .din           (pcx_data_rdy_px),
	    .q             (pcx_data_rdy_px2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'd0),
	    .so            ());


assign pcx_stall_pq_buf  =  pcx_stall_pq ;

endmodule
module pcx_data_px2(

   pcx_data_px2, pcx_data_rdy_px2, pcx_stall_pq_buf, so, 

   pcx_data_px_l, pcx_data_rdy_px, pcx_stall_pq, rclk, si, se
   );

   

   output [`PCX_WIDTH-1:0]		pcx_data_px2;	
   output 		pcx_data_rdy_px2;	
   output 		pcx_stall_pq_buf;	
   output 		so;
   
   input [`PCX_WIDTH-1:0]		pcx_data_px_l;	
   input 		pcx_data_rdy_px;	
   input 		pcx_stall_pq;	

   input 		rclk;
   input 		si;
   input 		se;
   

   wire [`PCX_WIDTH-1:0]		pcx_data_px2_l;	
   
   
   dff_s #(`PCX_WIDTH) dff_cpx_data(
            .din           (pcx_data_px_l[`PCX_WIDTH-1:0]),
	    .q             (pcx_data_px2_l[`PCX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (`PCX_WIDTH'd0),
	    .so            ());

assign pcx_data_px2 = ~pcx_data_px2_l; 



      dff_s #(1) dff_cpx_datardy(
            .din           (pcx_data_rdy_px),
	    .q             (pcx_data_rdy_px2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'd0),
	    .so            ());


assign pcx_stall_pq_buf  =  pcx_stall_pq ;

endmodule