data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:8: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src/peripherals/i2cm/bench,data/full_repos/permissive/494148647/timescale.v\n             data/full_repos/permissive/494148647/src/peripherals/i2cm/bench,data/full_repos/permissive/494148647/timescale.v.v\n             data/full_repos/permissive/494148647/src/peripherals/i2cm/bench,data/full_repos/permissive/494148647/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        repeat(2) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:87: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("i2cm_iom_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:88: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, i2cm_iom_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:91: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/bench/i2cm_iom_tb.v:98: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module i2cm_iom_tb();

    localparam PRER_LO = 5'b00000;
    localparam PRER_HI = 5'b00100;
    localparam CTR     = 5'b01000;
    localparam RXR     = 5'b01100;
    localparam TXR     = 5'b01100;
    localparam CR      = 5'b10000;
    localparam SR      = 5'b10000;

    localparam TXR_R   = 5'b10100;
    localparam CR_R    = 5'b11000;

    localparam RD      = 1'b1;
    localparam WR      = 1'b0;
    localparam SADR    = 7'b0010_000;

    reg clk, rst;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;

    wire irq;
    wire scl, sda;

    pullup(scl);
    pullup(sda);


    i2cm_iom DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),
        .irq(irq),
        .scl(scl),
        .sda(sda)
    );


    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );




    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(2) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("i2cm_iom_tb.vcd");
        $dumpvars(0, i2cm_iom_tb);

        value = 32'b0;
        @(negedge rst);
        @(posedge clk);

        io.io_write(PRER_LO, 32'hfa);
        io.io_write(PRER_LO, 32'hc8);
        io.io_write(PRER_HI, 32'h00);

        repeat(2) @(posedge clk);

        io.io_check(PRER_LO, 32'hc8);
        io.io_check(PRER_HI, 32'h00);

        io.io_read(CR, value);
        $display("%t: io_read(CR) = %h", $time, value);
        io.io_read(SR, value);
        $display("%t: io_read(SR) = %h", $time, value);

        io.io_read(32'h100, value);
        $display("%t: io_read(0x100) = %h", $time, value);

        $finish;
    end

endmodule
module i2cm_iom_tb();


    localparam PRER_LO = 5'b00000;
    localparam PRER_HI = 5'b00100;
    localparam CTR     = 5'b01000;
    localparam RXR     = 5'b01100;
    localparam TXR     = 5'b01100;
    localparam CR      = 5'b10000;
    localparam SR      = 5'b10000;

    localparam TXR_R   = 5'b10100;
    localparam CR_R    = 5'b11000;

    localparam RD      = 1'b1;
    localparam WR      = 1'b0;
    localparam SADR    = 7'b0010_000;

    reg clk, rst;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;

    wire irq;
    wire scl, sda;

    pullup(scl);
    pullup(sda);


    i2cm_iom DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),
        .irq(irq),
        .scl(scl),
        .sda(sda)
    );


    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );




    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(2) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("i2cm_iom_tb.vcd");
        $dumpvars(0, i2cm_iom_tb);

        value = 32'b0;
        @(negedge rst);
        @(posedge clk);

        io.io_write(PRER_LO, 32'hfa);
        io.io_write(PRER_LO, 32'hc8);
        io.io_write(PRER_HI, 32'h00);

        repeat(2) @(posedge clk);

        io.io_check(PRER_LO, 32'hc8);
        io.io_check(PRER_HI, 32'h00);

        io.io_read(CR, value);
        $display("%t: io_read(CR) = %h", $time, value);
        io.io_read(SR, value);
        $display("%t: io_read(SR) = %h", $time, value);

        io.io_read(32'h100, value);
        $display("%t: io_read(0x100) = %h", $time, value);

        $finish;
    end

endmodule