data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxconv2clk.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxconv2clk.v:98: Cannot find file containing module: 'ipsmacge_rxshift'\nipsmacge_rxshift  #(DAT_DW,DAT_EW,MAC_DW,MAC_BW) irxshift\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/ipsmacge_rxshift\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/ipsmacge_rxshift.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/ipsmacge_rxshift.sv\n             ipsmacge_rxshift\n             ipsmacge_rxshift.v\n             ipsmacge_rxshift.sv\n             obj_dir/ipsmacge_rxshift\n             obj_dir/ipsmacge_rxshift.v\n             obj_dir/ipsmacge_rxshift.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxconv2clk.v:118: Cannot find file containing module: 'ipsmacge_rx2clk'\nipsmacge_rx2clk #(2,2,RAM_DW) irx2clk\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ipsmacge_rxconv2clk
    (
     rxclk,
     rxrst_,

     rx_idat, 
     rx_isop,  
     rx_ieop,  
     rx_ivld,  
     rx_ierr,

     maclk,
     marst_,
     ma_odat,
     ma_onob,
     ma_ovld,
     ma_osop,
     ma_oeop,
     ma_oerr,

     rxrderr,
     upact
     );



parameter DAT_DW = 8;
parameter DAT_EW = 4;

parameter MAC_DW = 32;
parameter MAC_BW = 2;
parameter MAC_EW = 4;

parameter RAM_DW =  MAC_DW + MAC_EW + MAC_BW + 2;


input               rxrst_;
input               rxclk;

input  [DAT_DW-1:0] rx_idat;
input               rx_ivld;
input               rx_isop;
input               rx_ieop;
input  [DAT_EW-1:0] rx_ierr;

input               maclk;
input               marst_;
output [MAC_DW-1:0] ma_odat; 
output [MAC_BW-1:0] ma_onob;
output              ma_ovld;
output              ma_osop;
output              ma_oeop;
output [MAC_EW-1:0] ma_oerr;

output              rxrderr;
input               upact;



wire [MAC_DW-1:0]   out_dat;
wire [MAC_BW-1:0]   out_nob;
wire                out_vld;
wire                out_sop;
wire                out_eop;
wire [MAC_EW-1:0]   out_err;

wire [RAM_DW-1:0]   rdat;
wire                rvld;
















ipsmacge_rxshift  #(DAT_DW,DAT_EW,MAC_DW,MAC_BW) irxshift
    (
     .rxclk   (rxclk),
     .rxrst_  (rxrst_),

     .rx_idat (rx_idat), 
     .rx_isop (rx_isop),  
     .rx_ieop (rx_ieop),  
     .rx_ivld (rx_ivld & upact),  
     .rx_ierr (rx_ierr),

     .out_dat (out_dat),
     .out_nob (out_nob),
     .out_vld (out_vld),
     .out_sop (out_sop),
     .out_eop (out_eop),
     .out_err (out_err)
     );


ipsmacge_rx2clk #(2,2,RAM_DW) irx2clk
    (
     .wrst_ (rxrst_),

     .wclk  (rxclk),
     .wvld  (out_vld & upact),
     .wdat  ({out_nob, out_err, out_eop, out_sop, out_dat}),

     .rrst_ (marst_),
     .rclk  (maclk),
     .rdat  ({ma_onob, ma_oerr, ma_oeop, ma_osop, ma_odat}),
     .rvld  (ma_ovld),
     .rerr  (rxrderr)
     );

endmodule
module ipsmacge_rxconv2clk
    (
     rxclk,
     rxrst_,

     rx_idat, 
     rx_isop,  
     rx_ieop,  
     rx_ivld,  
     rx_ierr,

     maclk,
     marst_,
     ma_odat,
     ma_onob,
     ma_ovld,
     ma_osop,
     ma_oeop,
     ma_oerr,

     rxrderr,
     upact
     );




parameter DAT_DW = 8;
parameter DAT_EW = 4;

parameter MAC_DW = 32;
parameter MAC_BW = 2;
parameter MAC_EW = 4;

parameter RAM_DW =  MAC_DW + MAC_EW + MAC_BW + 2;


input               rxrst_;
input               rxclk;

input  [DAT_DW-1:0] rx_idat;
input               rx_ivld;
input               rx_isop;
input               rx_ieop;
input  [DAT_EW-1:0] rx_ierr;

input               maclk;
input               marst_;
output [MAC_DW-1:0] ma_odat; 
output [MAC_BW-1:0] ma_onob;
output              ma_ovld;
output              ma_osop;
output              ma_oeop;
output [MAC_EW-1:0] ma_oerr;

output              rxrderr;
input               upact;



wire [MAC_DW-1:0]   out_dat;
wire [MAC_BW-1:0]   out_nob;
wire                out_vld;
wire                out_sop;
wire                out_eop;
wire [MAC_EW-1:0]   out_err;

wire [RAM_DW-1:0]   rdat;
wire                rvld;
















ipsmacge_rxshift  #(DAT_DW,DAT_EW,MAC_DW,MAC_BW) irxshift
    (
     .rxclk   (rxclk),
     .rxrst_  (rxrst_),

     .rx_idat (rx_idat), 
     .rx_isop (rx_isop),  
     .rx_ieop (rx_ieop),  
     .rx_ivld (rx_ivld & upact),  
     .rx_ierr (rx_ierr),

     .out_dat (out_dat),
     .out_nob (out_nob),
     .out_vld (out_vld),
     .out_sop (out_sop),
     .out_eop (out_eop),
     .out_err (out_err)
     );


ipsmacge_rx2clk #(2,2,RAM_DW) irx2clk
    (
     .wrst_ (rxrst_),

     .wclk  (rxclk),
     .wvld  (out_vld & upact),
     .wdat  ({out_nob, out_err, out_eop, out_sop, out_dat}),

     .rrst_ (marst_),
     .rclk  (maclk),
     .rdat  ({ma_onob, ma_oerr, ma_oeop, ma_osop, ma_odat}),
     .rvld  (ma_ovld),
     .rerr  (rxrderr)
     );

endmodule