data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfdsu/rtl/aq_fdsu_srt.v
data/verilator_xmls/df2db2f3-38af-4b34-8a36-2e1e7a33da4d.xml
module aq_fdsu_srt(
  bhalf0_ex2_result_denorm_round_add_num,
  bhalf0_remainder_nxt,
  double_ex2_result_denorm_round_add_num,
  double_pipe_cur_rem_1,
  double_pipe_cur_rem_2,
  double_pipe_ex2_expnt_adder_op0,
  double_pipe_ex2_expnt_adder_op1,
  double_pipe_ex2_of,
  double_pipe_ex2_of_rm_lfn,
  double_pipe_ex2_op0_norm,
  double_pipe_ex2_op1_norm,
  double_pipe_ex2_potnt_of,
  double_pipe_ex2_potnt_uf,
  double_pipe_ex2_result_inf,
  double_pipe_ex2_result_lfn,
  double_pipe_ex2_rslt_denorm,
  double_pipe_ex2_srt_expnt_rst,
  double_pipe_ex2_uf,
  double_pipe_ex2_uf_srt_skip,
  double_pipe_qt_rt_const_shift_std,
  double_pipe_srt_divisor,
  double_pipe_srt_remainder,
  double_pipe_srt_remainder_zero,
  double_pipe_total_qt_rt,
  double_pipe_total_qt_rt_minus,
  double_remainder_nxt,
  double_srt_remainder,
  double_srt_remainder_add1_op1,
  double_srt_remainder_add1_op2,
  double_srt_remainder_add2_op1,
  double_srt_remainder_add2_op2,
  double_srt_remainder_shift,
  double_total_qt_rt_minus_next,
  double_total_qt_rt_next,
  ex2_pipe_clk,
  ex2_pipedown,
  ex2_srt_first_round,
  fdsu_ex2_bhalf,
  fdsu_ex2_div,
  fdsu_ex2_double,
  fdsu_ex2_half,
  fdsu_ex2_single,
  fdsu_ex2_sqrt,
  fdsu_ex3_id_srt_skip,
  fdsu_ex3_rem_sign,
  fdsu_ex3_rem_zero,
  half0_ex2_result_denorm_round_add_num,
  half0_remainder_nxt,
  half0_total_qt_rt_minus_next,
  half0_total_qt_rt_next,
  single0_ex2_result_denorm_round_add_num,
  single0_remainder_nxt,
  single0_total_qt_rt_minus_next,
  single0_total_qt_rt_next
);


input   [59:0]  double_pipe_cur_rem_1;                  
input   [59:0]  double_pipe_cur_rem_2;                  
input   [12:0]  double_pipe_ex2_expnt_adder_op0;        
input   [12:0]  double_pipe_ex2_expnt_adder_op1;        
input           double_pipe_ex2_of_rm_lfn;              
input           double_pipe_ex2_op0_norm;               
input           double_pipe_ex2_op1_norm;               
input   [57:0]  double_pipe_qt_rt_const_shift_std;      
input   [52:0]  double_pipe_srt_divisor;                
input   [59:0]  double_pipe_srt_remainder;              
input   [57:0]  double_pipe_total_qt_rt;                
input   [57:0]  double_pipe_total_qt_rt_minus;          
input   [59:0]  double_srt_remainder;                   
input           ex2_pipe_clk;                           
input           ex2_pipedown;                           
input           ex2_srt_first_round;                    
input           fdsu_ex2_bhalf;                         
input           fdsu_ex2_div;                           
input           fdsu_ex2_double;                        
input           fdsu_ex2_half;                          
input           fdsu_ex2_single;                        
input           fdsu_ex2_sqrt;                          
output  [7 :0]  bhalf0_ex2_result_denorm_round_add_num; 
output  [14:0]  bhalf0_remainder_nxt;                   
output  [52:0]  double_ex2_result_denorm_round_add_num; 
output          double_pipe_ex2_of;                     
output          double_pipe_ex2_potnt_of;               
output          double_pipe_ex2_potnt_uf;               
output          double_pipe_ex2_result_inf;             
output          double_pipe_ex2_result_lfn;             
output          double_pipe_ex2_rslt_denorm;            
output  [12:0]  double_pipe_ex2_srt_expnt_rst;          
output          double_pipe_ex2_uf;                     
output          double_pipe_ex2_uf_srt_skip;            
output          double_pipe_srt_remainder_zero;         
output  [59:0]  double_remainder_nxt;                   
output  [59:0]  double_srt_remainder_add1_op1;          
output  [59:0]  double_srt_remainder_add1_op2;          
output  [59:0]  double_srt_remainder_add2_op1;          
output  [59:0]  double_srt_remainder_add2_op2;          
output  [59:0]  double_srt_remainder_shift;             
output  [57:0]  double_total_qt_rt_minus_next;          
output  [57:0]  double_total_qt_rt_next;                
output          fdsu_ex3_id_srt_skip;                   
output          fdsu_ex3_rem_sign;                      
output          fdsu_ex3_rem_zero;                      
output  [10:0]  half0_ex2_result_denorm_round_add_num;  
output  [18:0]  half0_remainder_nxt;                    
output  [15:0]  half0_total_qt_rt_minus_next;           
output  [15:0]  half0_total_qt_rt_next;                 
output  [23:0]  single0_ex2_result_denorm_round_add_num; 
output  [30:0]  single0_remainder_nxt;                  
output  [27:0]  single0_total_qt_rt_minus_next;         
output  [27:0]  single0_total_qt_rt_next;               


reg     [59:0]  cur_rem;                                
reg     [7 :0]  digit_bound_1;                          
reg     [7 :0]  digit_bound_2;                          
reg     [52:0]  double_ex2_result_denorm_round_add_num; 
reg             fdsu_ex3_id_srt_skip;                   
reg             fdsu_ex3_rem_sign;                      
reg             fdsu_ex3_rem_zero;                      
reg     [10:0]  half0_ex2_result_denorm_round_add_num;  
reg     [7 :0]  qtrt_sel_rem;                           
reg     [59:0]  rem_add1_op1;                           
reg     [18:0]  rem_add1_op1_h;                         
reg     [30:0]  rem_add1_op1_s;                         
reg     [59:0]  rem_add2_op1;                           
reg     [18:0]  rem_add2_op1_h;                         
reg     [30:0]  rem_add2_op1_s;                         
reg     [23:0]  single0_ex2_result_denorm_round_add_num; 
reg     [57:0]  total_qt_rt_minus_next;                 
reg     [57:0]  total_qt_rt_next;                       


wire    [7 :0]  bhalf0_ex2_result_denorm_round_add_num; 
wire    [14:0]  bhalf0_remainder_nxt;                   
wire    [7 :0]  bound1_cmp_result;                      
wire            bound1_cmp_sign;                        
wire    [7 :0]  bound2_cmp_result;                      
wire            bound2_cmp_sign;                        
wire    [3 :0]  bound_sel;                              
wire    [59:0]  div_qt_1_rem_add_op1;                   
wire    [18:0]  div_qt_1_rem_add_op1_h;                 
wire    [30:0]  div_qt_1_rem_add_op1_s;                 
wire    [59:0]  div_qt_2_rem_add_op1;                   
wire    [18:0]  div_qt_2_rem_add_op1_h;                 
wire    [30:0]  div_qt_2_rem_add_op1_s;                 
wire    [59:0]  div_qt_r1_rem_add_op1;                  
wire    [18:0]  div_qt_r1_rem_add_op1_h;                
wire    [30:0]  div_qt_r1_rem_add_op1_s;                
wire    [59:0]  div_qt_r2_rem_add_op1;                  
wire    [18:0]  div_qt_r2_rem_add_op1_h;                
wire    [30:0]  div_qt_r2_rem_add_op1_s;                
wire    [59:0]  double_pipe_cur_rem_1;                  
wire    [59:0]  double_pipe_cur_rem_2;                  
wire    [12:0]  double_pipe_ex2_expnt_adder_op0;        
wire    [12:0]  double_pipe_ex2_expnt_adder_op1;        
wire            double_pipe_ex2_of;                     
wire            double_pipe_ex2_of_rm_lfn;              
wire            double_pipe_ex2_op0_norm;               
wire            double_pipe_ex2_op1_norm;               
wire            double_pipe_ex2_potnt_of;               
wire            double_pipe_ex2_potnt_uf;               
wire            double_pipe_ex2_result_inf;             
wire            double_pipe_ex2_result_lfn;             
wire            double_pipe_ex2_rslt_denorm;            
wire    [12:0]  double_pipe_ex2_srt_expnt_rst;          
wire            double_pipe_ex2_uf;                     
wire            double_pipe_ex2_uf_srt_skip;            
wire    [57:0]  double_pipe_qt_rt_const_shift_std;      
wire    [52:0]  double_pipe_srt_divisor;                
wire    [59:0]  double_pipe_srt_remainder;              
wire            double_pipe_srt_remainder_zero;         
wire    [57:0]  double_pipe_total_qt_rt;                
wire    [57:0]  double_pipe_total_qt_rt_minus;          
wire    [59:0]  double_remainder_nxt;                   
wire    [59:0]  double_srt_remainder;                   
wire    [59:0]  double_srt_remainder_add1_op1;          
wire    [59:0]  double_srt_remainder_add1_op2;          
wire    [59:0]  double_srt_remainder_add2_op1;          
wire    [59:0]  double_srt_remainder_add2_op2;          
wire    [59:0]  double_srt_remainder_shift;             
wire            double_srt_remainder_zero;              
wire    [57:0]  double_total_qt_rt_minus_next;          
wire    [57:0]  double_total_qt_rt_next;                
wire            ex2_bhalf_div_of;                       
wire            ex2_bhalf_div_uf;                       
wire            ex2_bhalf_exp_potnt_of;                 
wire            ex2_bhalf_exp_potnt_uf;                 
wire            ex2_bhalf_expnt_of;                     
wire            ex2_bhalf_expnt_uf;                     
wire            ex2_bhalf_id_nor_srt_skip;              
wire            ex2_bhalf_potnt_of;                     
wire            ex2_bhalf_potnt_uf;                     
wire            ex2_div_of;                             
wire            ex2_doub_exp_potnt_of;                  
wire            ex2_doub_exp_potnt_uf;                  
wire            ex2_doub_expnt_of;                      
wire            ex2_doub_expnt_uf;                      
wire            ex2_doub_potnt_uf;                      
wire            ex2_double_div_of;                      
wire            ex2_double_div_uf;                      
wire            ex2_double_id_nor_srt_skip;             
wire            ex2_double_potnt_of;                    
wire    [12:0]  ex2_expnt_result;                       
wire            ex2_half_div_of;                        
wire            ex2_half_div_uf;                        
wire            ex2_half_exp_potnt_of;                  
wire            ex2_half_exp_potnt_uf;                  
wire            ex2_half_expnt_of;                      
wire            ex2_half_expnt_uf;                      
wire            ex2_half_id_nor_srt_skip;               
wire            ex2_half_potnt_of;                      
wire            ex2_half_potnt_uf;                      
wire            ex2_id_nor_srt_skip;                    
wire            ex2_of_plus;                            
wire            ex2_pipe_clk;                           
wire            ex2_pipedown;                           
wire            ex2_sing_exp_potnt_of;                  
wire            ex2_sing_exp_potnt_uf;                  
wire            ex2_sing_expnt_of;                      
wire            ex2_sing_expnt_uf;                      
wire            ex2_sing_potnt_uf;                      
wire            ex2_single_div_of;                      
wire            ex2_single_div_uf;                      
wire            ex2_single_id_nor_srt_skip;             
wire            ex2_single_potnt_of;                    
wire    [12:0]  ex2_sqrt_expnt_result;                  
wire    [12:0]  ex2_srt_expnt_rst;                      
wire            ex2_srt_first_round;                    
wire            ex2_uf;                                 
wire            ex2_uf_plus;                            
wire            fdsu_ex2_bhalf;                         
wire            fdsu_ex2_div;                           
wire            fdsu_ex2_double;                        
wire    [12:0]  fdsu_ex2_expnt_rst;                     
wire            fdsu_ex2_half;                          
wire            fdsu_ex2_of_rm_lfn;                     
wire            fdsu_ex2_op0_norm;                      
wire            fdsu_ex2_op1_norm;                      
wire            fdsu_ex2_result_lfn;                    
wire            fdsu_ex2_single;                        
wire            fdsu_ex2_sqrt;                          
wire    [18:0]  half0_remainder_nxt;                    
wire    [15:0]  half0_total_qt_rt_minus_next;           
wire    [15:0]  half0_total_qt_rt_next;                 
wire    [57:0]  qt_rt_const_pre_sel_q1;                 
wire    [57:0]  qt_rt_const_pre_sel_q2;                 
wire    [57:0]  qt_rt_const_q1;                         
wire    [57:0]  qt_rt_const_q2;                         
wire    [57:0]  qt_rt_const_q3;                         
wire    [57:0]  qt_rt_mins_const_pre_sel_q1;            
wire    [57:0]  qt_rt_mins_const_pre_sel_q2;            
wire            rem_sign;                               
wire    [30:0]  single0_remainder_nxt;                  
wire    [27:0]  single0_total_qt_rt_minus_next;         
wire    [27:0]  single0_total_qt_rt_next;               
wire    [59:0]  sqrt_qt_1_rem_add_op1;                  
wire    [18:0]  sqrt_qt_1_rem_add_op1_h;                
wire    [30:0]  sqrt_qt_1_rem_add_op1_s;                
wire    [59:0]  sqrt_qt_2_rem_add_op1;                  
wire    [18:0]  sqrt_qt_2_rem_add_op1_h;                
wire    [30:0]  sqrt_qt_2_rem_add_op1_s;                
wire    [59:0]  sqrt_qt_r1_rem_add_op1;                 
wire    [18:0]  sqrt_qt_r1_rem_add_op1_h;               
wire    [30:0]  sqrt_qt_r1_rem_add_op1_s;               
wire    [59:0]  sqrt_qt_r2_rem_add_op1;                 
wire    [18:0]  sqrt_qt_r2_rem_add_op1_h;               
wire    [30:0]  sqrt_qt_r2_rem_add_op1_s;               
wire    [59:0]  srt_remainder_shift;                    
wire    [59:0]  srt_remainder_shift_cur;                
wire    [18:0]  srt_remainder_shift_h;                  
wire    [30:0]  srt_remainder_shift_s;                  
wire            srt_remainder_sign;                     
wire            srt_remainder_zero;                     
wire    [57:0]  total_qt_rt_pre_sel;                    




assign fdsu_ex2_op0_norm        = double_pipe_ex2_op0_norm;
assign fdsu_ex2_op1_norm        = double_pipe_ex2_op1_norm;
assign fdsu_ex2_of_rm_lfn       = double_pipe_ex2_of_rm_lfn;
assign fdsu_ex2_result_lfn      = 1'b0;





assign ex2_expnt_result[12:0] =  double_pipe_ex2_expnt_adder_op0[12:0] -
                                 double_pipe_ex2_expnt_adder_op1[12:0];




assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12],
                                      ex2_expnt_result[12:1]};

assign ex2_srt_expnt_rst[12:0] = (fdsu_ex2_sqrt)
                               ? ex2_sqrt_expnt_result[12:0]
                               : ex2_expnt_result[12:0];
assign double_pipe_ex2_srt_expnt_rst[12:0] = ex2_srt_expnt_rst[12:0];
assign fdsu_ex2_expnt_rst[12:0]            = ex2_srt_expnt_rst[12:0];








assign ex2_doub_expnt_of = ~fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] > 12'd1024);
assign ex2_sing_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8:0] > 9'd128);
assign ex2_half_expnt_of = ~fdsu_ex2_expnt_rst[6] && (fdsu_ex2_expnt_rst[5:0] > 6'd16);
assign ex2_bhalf_expnt_of = ex2_sing_expnt_of;




assign double_pipe_ex2_of      = ex2_of_plus;
assign ex2_of_plus = ex2_div_of  && fdsu_ex2_div;
assign ex2_double_div_of  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_doub_expnt_of;
assign ex2_single_div_of  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_sing_expnt_of;
assign ex2_half_div_of    = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_half_expnt_of;
assign ex2_bhalf_div_of   = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_bhalf_expnt_of;
assign ex2_div_of         = fdsu_ex2_double && ex2_double_div_of || 
                            fdsu_ex2_single && ex2_single_div_of ||
                            fdsu_ex2_half   && ex2_half_div_of   ||
                            fdsu_ex2_bhalf  && ex2_bhalf_div_of;


assign ex2_doub_exp_potnt_of  = fdsu_ex2_expnt_rst[12:0] == 13'd1024;
assign ex2_sing_exp_potnt_of  = fdsu_ex2_expnt_rst[9:0]  == 10'd128;
assign ex2_half_exp_potnt_of  = fdsu_ex2_expnt_rst[6:0]  == 7'd16;
assign ex2_bhalf_exp_potnt_of = ex2_sing_exp_potnt_of;
assign ex2_double_potnt_of      = ex2_doub_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_single_potnt_of      = ex2_sing_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_half_potnt_of        = ex2_half_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_bhalf_potnt_of       = ex2_bhalf_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign double_pipe_ex2_potnt_of = fdsu_ex2_div  && (
                                  fdsu_ex2_double && ex2_double_potnt_of ||
                                  fdsu_ex2_single && ex2_single_potnt_of ||
                                  fdsu_ex2_half   && ex2_half_potnt_of   ||
                                  fdsu_ex2_bhalf  && ex2_bhalf_potnt_of);



assign  ex2_doub_expnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] <= 12'hc01);
assign ex2_sing_expnt_uf  = fdsu_ex2_expnt_rst[12] &&(fdsu_ex2_expnt_rst[11:0] <= 12'hf81);
assign ex2_half_expnt_uf  = fdsu_ex2_expnt_rst[12] &&(fdsu_ex2_expnt_rst[11:0] <= 12'hff1);
assign ex2_bhalf_expnt_uf = ex2_sing_expnt_uf;




assign ex2_uf      = ex2_uf_plus;
assign ex2_uf_plus = fdsu_ex2_div && (
                     fdsu_ex2_double && ex2_double_div_uf || 
                     fdsu_ex2_single && ex2_single_div_uf ||
                     fdsu_ex2_half   && ex2_half_div_uf   ||
                     fdsu_ex2_bhalf  && ex2_bhalf_div_uf);
assign ex2_double_div_uf  = fdsu_ex2_op0_norm &&
                           fdsu_ex2_op1_norm &&
                           ex2_doub_expnt_uf;
assign ex2_single_div_uf  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_sing_expnt_uf; 
assign ex2_half_div_uf    = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_half_expnt_uf;
assign ex2_bhalf_div_uf   = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_bhalf_expnt_uf;



assign ex2_double_id_nor_srt_skip =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hbcd);
assign ex2_single_id_nor_srt_skip =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hf6a);
assign ex2_half_id_nor_srt_skip   =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hfe7);
assign ex2_bhalf_id_nor_srt_skip   =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hf7a); 

assign ex2_id_nor_srt_skip        = fdsu_ex2_double && ex2_double_id_nor_srt_skip || 
                                    fdsu_ex2_single && ex2_single_id_nor_srt_skip || 
                                    fdsu_ex2_half   && ex2_half_id_nor_srt_skip   || 
                                    fdsu_ex2_bhalf  && ex2_bhalf_id_nor_srt_skip;
assign double_pipe_ex2_uf_srt_skip            = ex2_id_nor_srt_skip;



assign ex2_doub_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hc02);
assign ex2_sing_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hf82);
assign ex2_half_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hff2);
assign ex2_bhalf_exp_potnt_uf= ex2_sing_potnt_uf;
assign double_pipe_ex2_potnt_uf          = fdsu_ex2_double && ex2_doub_potnt_uf || 
                               fdsu_ex2_single && ex2_sing_potnt_uf ||
                               fdsu_ex2_half   && ex2_half_potnt_uf ||
                               fdsu_ex2_bhalf  && ex2_bhalf_potnt_uf;
assign ex2_doub_potnt_uf      = (ex2_doub_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_doub_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_sing_potnt_uf      = (ex2_sing_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_sing_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_half_potnt_uf      = (ex2_half_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_half_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_bhalf_potnt_uf      = (ex2_bhalf_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_bhalf_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);




assign double_pipe_ex2_result_inf  = ex2_of_plus && !fdsu_ex2_of_rm_lfn;
assign double_pipe_ex2_result_lfn  = fdsu_ex2_result_lfn ||
                                     ex2_of_plus &&  fdsu_ex2_of_rm_lfn;
assign double_pipe_ex2_rslt_denorm     = ex2_uf;

                       


always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1c02:double_ex2_result_denorm_round_add_num[52:0] = 53'h1;
  13'h1c01:double_ex2_result_denorm_round_add_num[52:0] = 53'h2;
  13'h1c00:double_ex2_result_denorm_round_add_num[52:0] = 53'h4;
  13'h1bff:double_ex2_result_denorm_round_add_num[52:0] = 53'h8;
  13'h1bfe:double_ex2_result_denorm_round_add_num[52:0] = 53'h10;
  13'h1bfd:double_ex2_result_denorm_round_add_num[52:0] = 53'h20;
  13'h1bfc:double_ex2_result_denorm_round_add_num[52:0] = 53'h40;
  13'h1bfb:double_ex2_result_denorm_round_add_num[52:0] = 53'h80;
  13'h1bfa:double_ex2_result_denorm_round_add_num[52:0] = 53'h100;
  13'h1bf9:double_ex2_result_denorm_round_add_num[52:0] = 53'h200;
  13'h1bf8:double_ex2_result_denorm_round_add_num[52:0] = 53'h400;
  13'h1bf7:double_ex2_result_denorm_round_add_num[52:0] = 53'h800;
  13'h1bf6:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000;
  13'h1bf5:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000;
  13'h1bf4:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000;
  13'h1bf3:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000;
  13'h1bf2:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000;
  13'h1bf1:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000;
  13'h1bf0:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000;
  13'h1bef:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000;
  13'h1bee:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000;
  13'h1bed:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000;
  13'h1bec:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000;
  13'h1beb:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000;
  13'h1bea:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000;
  13'h1be9:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000;
  13'h1be8:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000;
  13'h1be7:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000;
  13'h1be6:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000;
  13'h1be5:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1be4:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1be3:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1be2:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1be1:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1be0:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1bdf:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1bde:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1bdd:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1bdc:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1bdb:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1bda:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1bd9:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1bd8:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1bd7:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1bd6:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1bd5:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1bd4:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1bd3:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1bd2:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1bd1:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1bd0:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1bcf:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1bce:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: double_ex2_result_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1f82:single0_ex2_result_denorm_round_add_num[23:0] = 24'h1;
  13'h1f81:single0_ex2_result_denorm_round_add_num[23:0] = 24'h2;
  13'h1f80:single0_ex2_result_denorm_round_add_num[23:0] = 24'h4;
  13'h1f7f:single0_ex2_result_denorm_round_add_num[23:0] = 24'h8;
  13'h1f7e:single0_ex2_result_denorm_round_add_num[23:0] = 24'h10;
  13'h1f7d:single0_ex2_result_denorm_round_add_num[23:0] = 24'h20;
  13'h1f7c:single0_ex2_result_denorm_round_add_num[23:0] = 24'h40;
  13'h1f7b:single0_ex2_result_denorm_round_add_num[23:0] = 24'h80;
  13'h1f7a:single0_ex2_result_denorm_round_add_num[23:0] = 24'h100;
  13'h1f79:single0_ex2_result_denorm_round_add_num[23:0] = 24'h200;
  13'h1f78:single0_ex2_result_denorm_round_add_num[23:0] = 24'h400;
  13'h1f77:single0_ex2_result_denorm_round_add_num[23:0] = 24'h800;
  13'h1f76:single0_ex2_result_denorm_round_add_num[23:0] = 24'h1000;
  13'h1f75:single0_ex2_result_denorm_round_add_num[23:0] = 24'h2000;
  13'h1f74:single0_ex2_result_denorm_round_add_num[23:0] = 24'h4000;
  13'h1f73:single0_ex2_result_denorm_round_add_num[23:0] = 24'h8000;
  13'h1f72:single0_ex2_result_denorm_round_add_num[23:0] = 24'h10000;
  13'h1f71:single0_ex2_result_denorm_round_add_num[23:0] = 24'h20000;
  13'h1f70:single0_ex2_result_denorm_round_add_num[23:0] = 24'h40000;
  13'h1f6f:single0_ex2_result_denorm_round_add_num[23:0] = 24'h80000;
  13'h1f6e:single0_ex2_result_denorm_round_add_num[23:0] = 24'h100000;
  13'h1f6d:single0_ex2_result_denorm_round_add_num[23:0] = 24'h200000;
  13'h1f6c:single0_ex2_result_denorm_round_add_num[23:0] = 24'h400000;
  13'h1f6b:single0_ex2_result_denorm_round_add_num[23:0] = 24'h800000;
  default: single0_ex2_result_denorm_round_add_num[23:0] = 24'h0;
endcase

end


always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1ff2:half0_ex2_result_denorm_round_add_num[10:0] = 11'h1;
  13'h1ff1:half0_ex2_result_denorm_round_add_num[10:0] = 11'h2;
  13'h1ff0:half0_ex2_result_denorm_round_add_num[10:0] = 11'h4;
  13'h1fef:half0_ex2_result_denorm_round_add_num[10:0] = 11'h8;
  13'h1fee:half0_ex2_result_denorm_round_add_num[10:0] = 11'h10;
  13'h1fed:half0_ex2_result_denorm_round_add_num[10:0] = 11'h20;
  13'h1fec:half0_ex2_result_denorm_round_add_num[10:0] = 11'h40;
  13'h1feb:half0_ex2_result_denorm_round_add_num[10:0] = 11'h80;
  13'h1fea:half0_ex2_result_denorm_round_add_num[10:0] = 11'h100;
  13'h1fe9:half0_ex2_result_denorm_round_add_num[10:0] = 11'h200;
  13'h1fe8:half0_ex2_result_denorm_round_add_num[10:0] = 11'h400;
  default: half0_ex2_result_denorm_round_add_num[10:0] = 11'h0;
endcase

end
assign bhalf0_ex2_result_denorm_round_add_num[7:0] = single0_ex2_result_denorm_round_add_num[7:0];







































always @(posedge ex2_pipe_clk)
begin
  if(ex2_pipedown)
  begin
    fdsu_ex3_rem_sign        <= srt_remainder_sign;
    fdsu_ex3_rem_zero        <= srt_remainder_zero;
    fdsu_ex3_id_srt_skip     <= ex2_id_nor_srt_skip;
  end
  else
  begin
    fdsu_ex3_rem_sign        <= fdsu_ex3_rem_sign;
    fdsu_ex3_rem_zero        <= fdsu_ex3_rem_zero;
    fdsu_ex3_id_srt_skip    <=  fdsu_ex3_id_srt_skip;
  end
end











































































  
assign bound_sel[3:0] = (fdsu_ex2_div)
                      ? double_pipe_srt_divisor[52:49]
                      : (ex2_srt_first_round)
                        ? 4'b1010
                        : double_pipe_total_qt_rt[56:53];





always @( bound_sel[3:0])
begin
case(bound_sel[3:0])
4'b0000:
   begin
     digit_bound_1[7:0] = 8'b11110100;
     digit_bound_2[7:0] = 8'b11010001;
   end
4'b1000:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100111;
   end
4'b1001:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100100;
   end
4'b1010:
   begin
     digit_bound_1[7:0] = 8'b11111000;
     digit_bound_2[7:0] = 8'b11100001;
   end
4'b1011:
   begin
     digit_bound_1[7:0] = 8'b11110111;
     digit_bound_2[7:0] = 8'b11011111;
   end
4'b1100:
   begin
     digit_bound_1[7:0] = 8'b11110111;
     digit_bound_2[7:0] = 8'b11011100;
   end
4'b1101:
   begin
     digit_bound_1[7:0] = 8'b11110110;
     digit_bound_2[7:0] = 8'b11011001;
   end
4'b1110:
   begin
     digit_bound_1[7:0] = 8'b11110101;
     digit_bound_2[7:0] = 8'b11010111;
   end
4'b1111:
   begin
     digit_bound_1[7:0] = 8'b11110100;
     digit_bound_2[7:0] = 8'b11010001;
   end
default:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100111;
   end
endcase

end


assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0];
assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0];
assign bound1_cmp_sign        = bound1_cmp_result[7];
assign bound2_cmp_sign        = bound2_cmp_result[7];
assign rem_sign               = double_pipe_srt_remainder[57];












always @( ex2_srt_first_round
       or fdsu_ex2_sqrt
       or double_pipe_srt_remainder[57:49])
begin
if(ex2_srt_first_round && fdsu_ex2_sqrt)
  qtrt_sel_rem[7:0] = {double_pipe_srt_remainder[57],   double_pipe_srt_remainder[55:49]};
else
  qtrt_sel_rem[7:0] =  double_pipe_srt_remainder[57] ? ~double_pipe_srt_remainder[57:50]
                                         :  double_pipe_srt_remainder[57:50];

end














































assign qt_rt_const_q1[57:0] =  double_pipe_qt_rt_const_shift_std[57:0];
assign qt_rt_const_q2[57:0] = {double_pipe_qt_rt_const_shift_std[56:0],1'b0};
assign qt_rt_const_q3[57:0] =  qt_rt_const_q1[57:0] |
                               qt_rt_const_q2[57:0];
















assign total_qt_rt_pre_sel[57:0]         = (rem_sign) ?
                                           double_pipe_total_qt_rt_minus[57:0] :
                                           double_pipe_total_qt_rt[57:0];

assign qt_rt_const_pre_sel_q2[57:0]      = qt_rt_const_q2[57:0];
assign qt_rt_mins_const_pre_sel_q2[57:0] = qt_rt_const_q1[57:0];

assign qt_rt_const_pre_sel_q1[57:0]      = (rem_sign) ?
                                           qt_rt_const_q3[57:0] :
                                           qt_rt_const_q1[57:0];
assign qt_rt_mins_const_pre_sel_q1[57:0] = (rem_sign) ?
                                           qt_rt_const_q2[57:0] :
                                           58'b0;



always @( qt_rt_mins_const_pre_sel_q2[57:0]
       or qt_rt_mins_const_pre_sel_q1[57:0]
       or double_pipe_total_qt_rt_minus[57:0]
       or bound1_cmp_sign
       or total_qt_rt_pre_sel[57:0]
       or qt_rt_const_pre_sel_q1[57:0]
       or qt_rt_const_q3[57:0]
       or bound2_cmp_sign
       or qt_rt_const_pre_sel_q2[57:0]
       or double_pipe_total_qt_rt[57:0])
begin
casez({bound1_cmp_sign,bound2_cmp_sign})
  2'b00:
  begin
    total_qt_rt_next[57:0]       = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_const_pre_sel_q2[57:0];
    total_qt_rt_minus_next[57:0] = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_mins_const_pre_sel_q2[57:0];
  end
  2'b01:
  begin
    total_qt_rt_next[57:0]       = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_const_pre_sel_q1[57:0];
    total_qt_rt_minus_next[57:0] = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_mins_const_pre_sel_q1[57:0];
  end
  2'b1?:
  begin
    total_qt_rt_next[57:0]       = double_pipe_total_qt_rt[57:0];
    total_qt_rt_minus_next[57:0] = double_pipe_total_qt_rt_minus[57:0] |
                                      qt_rt_const_q3[57:0];
  end
  default:
  begin
    total_qt_rt_next[57:0]       = 58'b0;
    total_qt_rt_minus_next[57:0] = 58'b0;
  end
endcase

end
assign double_total_qt_rt_next[57:0]       = total_qt_rt_next[57:0];
assign double_total_qt_rt_minus_next[57:0] = total_qt_rt_minus_next[57:0];
assign single0_total_qt_rt_next[27:0]       = total_qt_rt_next[57:30];
assign single0_total_qt_rt_minus_next[27:0] = total_qt_rt_minus_next[57:30];
assign half0_total_qt_rt_next[15:0]         = total_qt_rt_next[57:42];
assign half0_total_qt_rt_minus_next[15:0]   = total_qt_rt_minus_next[57:42];






assign div_qt_1_rem_add_op1[59:0]     = ~{3'b0,double_pipe_srt_divisor[52:0],4'b0};
assign div_qt_1_rem_add_op1_s[30:0]   = ~{3'b0,double_pipe_srt_divisor[52:29],4'b0};
assign div_qt_1_rem_add_op1_h[18:0]   = ~{3'b0,double_pipe_srt_divisor[52:42],5'b0};

assign div_qt_2_rem_add_op1[59:0]     = ~{2'b0,double_pipe_srt_divisor[52:0],5'b0};
assign div_qt_2_rem_add_op1_s[30:0]   = ~{2'b0,double_pipe_srt_divisor[52:29],5'b0};
assign div_qt_2_rem_add_op1_h[18:0]   = ~{2'b0,double_pipe_srt_divisor[52:42],6'b0};

assign div_qt_r1_rem_add_op1[59:0]    =  {3'b0,double_pipe_srt_divisor[52:0],4'b0};
assign div_qt_r1_rem_add_op1_s[30:0]  =  {3'b0,double_pipe_srt_divisor[52:29],4'b0};
assign div_qt_r1_rem_add_op1_h[18:0]  =  {3'b0,double_pipe_srt_divisor[52:42],5'b0};

assign div_qt_r2_rem_add_op1[59:0]    =  {2'b0,double_pipe_srt_divisor[52:0],5'b0};
assign div_qt_r2_rem_add_op1_s[30:0]  =  {2'b0,double_pipe_srt_divisor[52:29],5'b0};
assign div_qt_r2_rem_add_op1_h[18:0]  =  {2'b0,double_pipe_srt_divisor[52:42],6'b0};



assign sqrt_qt_1_rem_add_op1[59:0]    = ~({2'b0,double_pipe_total_qt_rt[57:0]} |
                                        {3'b0,qt_rt_const_q1[57:1]});
assign sqrt_qt_1_rem_add_op1_s[30:0]  = ~({2'b0,double_pipe_total_qt_rt[57:30],1'b0} |
                                         {3'b0,qt_rt_const_q1[57:30]});
assign sqrt_qt_1_rem_add_op1_h[18:0]  = ~({2'b0,double_pipe_total_qt_rt[57:42],1'b0} |
                                         {3'b0,qt_rt_const_q1[57:42]});

assign sqrt_qt_2_rem_add_op1[59:0]  = ~({1'b0,double_pipe_total_qt_rt[57:0],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0});

assign sqrt_qt_2_rem_add_op1_s[30:0]  = ~({1'b0,double_pipe_total_qt_rt[57:30],2'b0} |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0});
assign sqrt_qt_2_rem_add_op1_h[18:0]  = ~({1'b0,double_pipe_total_qt_rt[57:42],2'b0} |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0});

assign sqrt_qt_r1_rem_add_op1[59:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:0]} |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0}  |
                                        {2'b0,qt_rt_const_q1[57:0]}       |
                                        {3'b0,qt_rt_const_q1[57:1]};
assign sqrt_qt_r1_rem_add_op1_s[30:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:30],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0}  |
                                        {2'b0,qt_rt_const_q1[57:30],1'b0}       |
                                        {3'b0,qt_rt_const_q1[57:30]};
assign sqrt_qt_r1_rem_add_op1_h[18:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:42],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0}  |
                                        {2'b0,qt_rt_const_q1[57:42],1'b0}       |
                                        {3'b0,qt_rt_const_q1[57:42]};

assign sqrt_qt_r2_rem_add_op1[59:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:0],1'b0} |
                                        {qt_rt_const_q1[57:0],2'b0}       |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0};
assign sqrt_qt_r2_rem_add_op1_s[30:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:30],2'b0} |
                                        {qt_rt_const_q1[57:30],3'b0}       |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0};
assign sqrt_qt_r2_rem_add_op1_h[18:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:42],2'b0} |
                                        {qt_rt_const_q1[57:42],3'b0}       |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0};


always @( div_qt_1_rem_add_op1_s[30:0]
       or sqrt_qt_2_rem_add_op1_h[18:0]
       or rem_sign
       or div_qt_1_rem_add_op1[59:0]
       or sqrt_qt_r2_rem_add_op1[59:0]
       or div_qt_2_rem_add_op1_h[18:0]
       or sqrt_qt_r1_rem_add_op1[59:0]
       or sqrt_qt_1_rem_add_op1[59:0]
       or div_qt_r1_rem_add_op1[59:0]
       or div_qt_r2_rem_add_op1_h[18:0]
       or div_qt_2_rem_add_op1[59:0]
       or fdsu_ex2_sqrt
       or sqrt_qt_2_rem_add_op1[59:0]
       or sqrt_qt_r2_rem_add_op1_h[18:0]
       or div_qt_r1_rem_add_op1_s[30:0]
       or sqrt_qt_r1_rem_add_op1_h[18:0]
       or sqrt_qt_2_rem_add_op1_s[30:0]
       or sqrt_qt_r2_rem_add_op1_s[30:0]
       or sqrt_qt_1_rem_add_op1_h[18:0]
       or div_qt_r1_rem_add_op1_h[18:0]
       or sqrt_qt_r1_rem_add_op1_s[30:0]
       or div_qt_1_rem_add_op1_h[18:0]
       or div_qt_r2_rem_add_op1_s[30:0]
       or div_qt_r2_rem_add_op1[59:0]
       or sqrt_qt_1_rem_add_op1_s[30:0]
       or div_qt_2_rem_add_op1_s[30:0])
begin
case({rem_sign,fdsu_ex2_sqrt})
  2'b01:
  begin
        rem_add1_op1[59:0]   = sqrt_qt_1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = sqrt_qt_2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = sqrt_qt_1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = sqrt_qt_2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = sqrt_qt_1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = sqrt_qt_2_rem_add_op1_h[18:0];
  end
  2'b00:
  begin
        rem_add1_op1[59:0]   = div_qt_1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = div_qt_2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = div_qt_1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = div_qt_2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = div_qt_1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = div_qt_2_rem_add_op1_h[18:0];
  end
  2'b11:
  begin
        rem_add1_op1[59:0]   = sqrt_qt_r1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = sqrt_qt_r2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = sqrt_qt_r1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = sqrt_qt_r2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = sqrt_qt_r1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = sqrt_qt_r2_rem_add_op1_h[18:0];
  end
  2'b10:
  begin
        rem_add1_op1[59:0]   = div_qt_r1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = div_qt_r2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = div_qt_r1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = div_qt_r2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = div_qt_r1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = div_qt_r2_rem_add_op1_h[18:0];
  end
  default :
  begin
        rem_add1_op1[59:0] = 60'b0;
        rem_add2_op1[59:0] = 60'b0;
        rem_add1_op1_s[30:0] = 31'b0;
        rem_add2_op1_s[30:0] = 31'b0;
        rem_add1_op1_h[18:0] = 19'b0;
        rem_add2_op1_h[18:0] = 19'b0;
  end
  endcase

end
assign srt_remainder_shift[59:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:0],2'b0};
assign srt_remainder_shift_s[30:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:29],2'b0};
assign srt_remainder_shift_h[18:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:41],2'b0};
assign srt_remainder_shift_cur[59:0] = {60{fdsu_ex2_double}} & srt_remainder_shift[59:0]  |
                                       {60{fdsu_ex2_single}} & {srt_remainder_shift_s[30:0],29'b0} |
                                       {60{(fdsu_ex2_half 
                                        || fdsu_ex2_bhalf)}} & {srt_remainder_shift_h[18:0],41'b0};
assign double_srt_remainder_shift[59:0]     = srt_remainder_shift[59:0];

assign double_srt_remainder_add1_op1[59:0]  = rem_add1_op1[59:0];
assign double_srt_remainder_add1_op2[59:0]  = {59'b0, ~rem_sign};


assign double_srt_remainder_add2_op1[59:0]  = rem_add2_op1[59:0];
assign double_srt_remainder_add2_op2[59:0]  = {59'b0, ~rem_sign};
















always @( srt_remainder_shift_cur[59:0]
       or bound1_cmp_sign
       or double_pipe_cur_rem_1[59:0]
       or double_pipe_cur_rem_2[59:0]
       or bound2_cmp_sign)
begin
case({bound1_cmp_sign,bound2_cmp_sign})
  2'b00:   cur_rem[59:0]         = double_pipe_cur_rem_2[59:0];
  2'b01:   cur_rem[59:0]         = double_pipe_cur_rem_1[59:0];
  default: cur_rem[59:0]         = srt_remainder_shift_cur[59:0];
endcase

end
assign double_remainder_nxt[59:0]   = cur_rem[59:0];
assign single0_remainder_nxt[30:0]  = cur_rem[59:29];
assign half0_remainder_nxt[18:0]    = cur_rem[59:41];
assign bhalf0_remainder_nxt[14:0]   = cur_rem[59:45];




assign double_pipe_srt_remainder_zero         = srt_remainder_zero;
assign double_srt_remainder_zero  = ~|double_srt_remainder[59:0];
assign srt_remainder_zero = double_srt_remainder_zero;

assign srt_remainder_sign        =   double_remainder_nxt[59];

assign double_pipe_ex2_uf = ex2_uf;

endmodule
module aq_fdsu_srt(
  bhalf0_ex2_result_denorm_round_add_num,
  bhalf0_remainder_nxt,
  double_ex2_result_denorm_round_add_num,
  double_pipe_cur_rem_1,
  double_pipe_cur_rem_2,
  double_pipe_ex2_expnt_adder_op0,
  double_pipe_ex2_expnt_adder_op1,
  double_pipe_ex2_of,
  double_pipe_ex2_of_rm_lfn,
  double_pipe_ex2_op0_norm,
  double_pipe_ex2_op1_norm,
  double_pipe_ex2_potnt_of,
  double_pipe_ex2_potnt_uf,
  double_pipe_ex2_result_inf,
  double_pipe_ex2_result_lfn,
  double_pipe_ex2_rslt_denorm,
  double_pipe_ex2_srt_expnt_rst,
  double_pipe_ex2_uf,
  double_pipe_ex2_uf_srt_skip,
  double_pipe_qt_rt_const_shift_std,
  double_pipe_srt_divisor,
  double_pipe_srt_remainder,
  double_pipe_srt_remainder_zero,
  double_pipe_total_qt_rt,
  double_pipe_total_qt_rt_minus,
  double_remainder_nxt,
  double_srt_remainder,
  double_srt_remainder_add1_op1,
  double_srt_remainder_add1_op2,
  double_srt_remainder_add2_op1,
  double_srt_remainder_add2_op2,
  double_srt_remainder_shift,
  double_total_qt_rt_minus_next,
  double_total_qt_rt_next,
  ex2_pipe_clk,
  ex2_pipedown,
  ex2_srt_first_round,
  fdsu_ex2_bhalf,
  fdsu_ex2_div,
  fdsu_ex2_double,
  fdsu_ex2_half,
  fdsu_ex2_single,
  fdsu_ex2_sqrt,
  fdsu_ex3_id_srt_skip,
  fdsu_ex3_rem_sign,
  fdsu_ex3_rem_zero,
  half0_ex2_result_denorm_round_add_num,
  half0_remainder_nxt,
  half0_total_qt_rt_minus_next,
  half0_total_qt_rt_next,
  single0_ex2_result_denorm_round_add_num,
  single0_remainder_nxt,
  single0_total_qt_rt_minus_next,
  single0_total_qt_rt_next
);



input   [59:0]  double_pipe_cur_rem_1;                  
input   [59:0]  double_pipe_cur_rem_2;                  
input   [12:0]  double_pipe_ex2_expnt_adder_op0;        
input   [12:0]  double_pipe_ex2_expnt_adder_op1;        
input           double_pipe_ex2_of_rm_lfn;              
input           double_pipe_ex2_op0_norm;               
input           double_pipe_ex2_op1_norm;               
input   [57:0]  double_pipe_qt_rt_const_shift_std;      
input   [52:0]  double_pipe_srt_divisor;                
input   [59:0]  double_pipe_srt_remainder;              
input   [57:0]  double_pipe_total_qt_rt;                
input   [57:0]  double_pipe_total_qt_rt_minus;          
input   [59:0]  double_srt_remainder;                   
input           ex2_pipe_clk;                           
input           ex2_pipedown;                           
input           ex2_srt_first_round;                    
input           fdsu_ex2_bhalf;                         
input           fdsu_ex2_div;                           
input           fdsu_ex2_double;                        
input           fdsu_ex2_half;                          
input           fdsu_ex2_single;                        
input           fdsu_ex2_sqrt;                          
output  [7 :0]  bhalf0_ex2_result_denorm_round_add_num; 
output  [14:0]  bhalf0_remainder_nxt;                   
output  [52:0]  double_ex2_result_denorm_round_add_num; 
output          double_pipe_ex2_of;                     
output          double_pipe_ex2_potnt_of;               
output          double_pipe_ex2_potnt_uf;               
output          double_pipe_ex2_result_inf;             
output          double_pipe_ex2_result_lfn;             
output          double_pipe_ex2_rslt_denorm;            
output  [12:0]  double_pipe_ex2_srt_expnt_rst;          
output          double_pipe_ex2_uf;                     
output          double_pipe_ex2_uf_srt_skip;            
output          double_pipe_srt_remainder_zero;         
output  [59:0]  double_remainder_nxt;                   
output  [59:0]  double_srt_remainder_add1_op1;          
output  [59:0]  double_srt_remainder_add1_op2;          
output  [59:0]  double_srt_remainder_add2_op1;          
output  [59:0]  double_srt_remainder_add2_op2;          
output  [59:0]  double_srt_remainder_shift;             
output  [57:0]  double_total_qt_rt_minus_next;          
output  [57:0]  double_total_qt_rt_next;                
output          fdsu_ex3_id_srt_skip;                   
output          fdsu_ex3_rem_sign;                      
output          fdsu_ex3_rem_zero;                      
output  [10:0]  half0_ex2_result_denorm_round_add_num;  
output  [18:0]  half0_remainder_nxt;                    
output  [15:0]  half0_total_qt_rt_minus_next;           
output  [15:0]  half0_total_qt_rt_next;                 
output  [23:0]  single0_ex2_result_denorm_round_add_num; 
output  [30:0]  single0_remainder_nxt;                  
output  [27:0]  single0_total_qt_rt_minus_next;         
output  [27:0]  single0_total_qt_rt_next;               


reg     [59:0]  cur_rem;                                
reg     [7 :0]  digit_bound_1;                          
reg     [7 :0]  digit_bound_2;                          
reg     [52:0]  double_ex2_result_denorm_round_add_num; 
reg             fdsu_ex3_id_srt_skip;                   
reg             fdsu_ex3_rem_sign;                      
reg             fdsu_ex3_rem_zero;                      
reg     [10:0]  half0_ex2_result_denorm_round_add_num;  
reg     [7 :0]  qtrt_sel_rem;                           
reg     [59:0]  rem_add1_op1;                           
reg     [18:0]  rem_add1_op1_h;                         
reg     [30:0]  rem_add1_op1_s;                         
reg     [59:0]  rem_add2_op1;                           
reg     [18:0]  rem_add2_op1_h;                         
reg     [30:0]  rem_add2_op1_s;                         
reg     [23:0]  single0_ex2_result_denorm_round_add_num; 
reg     [57:0]  total_qt_rt_minus_next;                 
reg     [57:0]  total_qt_rt_next;                       


wire    [7 :0]  bhalf0_ex2_result_denorm_round_add_num; 
wire    [14:0]  bhalf0_remainder_nxt;                   
wire    [7 :0]  bound1_cmp_result;                      
wire            bound1_cmp_sign;                        
wire    [7 :0]  bound2_cmp_result;                      
wire            bound2_cmp_sign;                        
wire    [3 :0]  bound_sel;                              
wire    [59:0]  div_qt_1_rem_add_op1;                   
wire    [18:0]  div_qt_1_rem_add_op1_h;                 
wire    [30:0]  div_qt_1_rem_add_op1_s;                 
wire    [59:0]  div_qt_2_rem_add_op1;                   
wire    [18:0]  div_qt_2_rem_add_op1_h;                 
wire    [30:0]  div_qt_2_rem_add_op1_s;                 
wire    [59:0]  div_qt_r1_rem_add_op1;                  
wire    [18:0]  div_qt_r1_rem_add_op1_h;                
wire    [30:0]  div_qt_r1_rem_add_op1_s;                
wire    [59:0]  div_qt_r2_rem_add_op1;                  
wire    [18:0]  div_qt_r2_rem_add_op1_h;                
wire    [30:0]  div_qt_r2_rem_add_op1_s;                
wire    [59:0]  double_pipe_cur_rem_1;                  
wire    [59:0]  double_pipe_cur_rem_2;                  
wire    [12:0]  double_pipe_ex2_expnt_adder_op0;        
wire    [12:0]  double_pipe_ex2_expnt_adder_op1;        
wire            double_pipe_ex2_of;                     
wire            double_pipe_ex2_of_rm_lfn;              
wire            double_pipe_ex2_op0_norm;               
wire            double_pipe_ex2_op1_norm;               
wire            double_pipe_ex2_potnt_of;               
wire            double_pipe_ex2_potnt_uf;               
wire            double_pipe_ex2_result_inf;             
wire            double_pipe_ex2_result_lfn;             
wire            double_pipe_ex2_rslt_denorm;            
wire    [12:0]  double_pipe_ex2_srt_expnt_rst;          
wire            double_pipe_ex2_uf;                     
wire            double_pipe_ex2_uf_srt_skip;            
wire    [57:0]  double_pipe_qt_rt_const_shift_std;      
wire    [52:0]  double_pipe_srt_divisor;                
wire    [59:0]  double_pipe_srt_remainder;              
wire            double_pipe_srt_remainder_zero;         
wire    [57:0]  double_pipe_total_qt_rt;                
wire    [57:0]  double_pipe_total_qt_rt_minus;          
wire    [59:0]  double_remainder_nxt;                   
wire    [59:0]  double_srt_remainder;                   
wire    [59:0]  double_srt_remainder_add1_op1;          
wire    [59:0]  double_srt_remainder_add1_op2;          
wire    [59:0]  double_srt_remainder_add2_op1;          
wire    [59:0]  double_srt_remainder_add2_op2;          
wire    [59:0]  double_srt_remainder_shift;             
wire            double_srt_remainder_zero;              
wire    [57:0]  double_total_qt_rt_minus_next;          
wire    [57:0]  double_total_qt_rt_next;                
wire            ex2_bhalf_div_of;                       
wire            ex2_bhalf_div_uf;                       
wire            ex2_bhalf_exp_potnt_of;                 
wire            ex2_bhalf_exp_potnt_uf;                 
wire            ex2_bhalf_expnt_of;                     
wire            ex2_bhalf_expnt_uf;                     
wire            ex2_bhalf_id_nor_srt_skip;              
wire            ex2_bhalf_potnt_of;                     
wire            ex2_bhalf_potnt_uf;                     
wire            ex2_div_of;                             
wire            ex2_doub_exp_potnt_of;                  
wire            ex2_doub_exp_potnt_uf;                  
wire            ex2_doub_expnt_of;                      
wire            ex2_doub_expnt_uf;                      
wire            ex2_doub_potnt_uf;                      
wire            ex2_double_div_of;                      
wire            ex2_double_div_uf;                      
wire            ex2_double_id_nor_srt_skip;             
wire            ex2_double_potnt_of;                    
wire    [12:0]  ex2_expnt_result;                       
wire            ex2_half_div_of;                        
wire            ex2_half_div_uf;                        
wire            ex2_half_exp_potnt_of;                  
wire            ex2_half_exp_potnt_uf;                  
wire            ex2_half_expnt_of;                      
wire            ex2_half_expnt_uf;                      
wire            ex2_half_id_nor_srt_skip;               
wire            ex2_half_potnt_of;                      
wire            ex2_half_potnt_uf;                      
wire            ex2_id_nor_srt_skip;                    
wire            ex2_of_plus;                            
wire            ex2_pipe_clk;                           
wire            ex2_pipedown;                           
wire            ex2_sing_exp_potnt_of;                  
wire            ex2_sing_exp_potnt_uf;                  
wire            ex2_sing_expnt_of;                      
wire            ex2_sing_expnt_uf;                      
wire            ex2_sing_potnt_uf;                      
wire            ex2_single_div_of;                      
wire            ex2_single_div_uf;                      
wire            ex2_single_id_nor_srt_skip;             
wire            ex2_single_potnt_of;                    
wire    [12:0]  ex2_sqrt_expnt_result;                  
wire    [12:0]  ex2_srt_expnt_rst;                      
wire            ex2_srt_first_round;                    
wire            ex2_uf;                                 
wire            ex2_uf_plus;                            
wire            fdsu_ex2_bhalf;                         
wire            fdsu_ex2_div;                           
wire            fdsu_ex2_double;                        
wire    [12:0]  fdsu_ex2_expnt_rst;                     
wire            fdsu_ex2_half;                          
wire            fdsu_ex2_of_rm_lfn;                     
wire            fdsu_ex2_op0_norm;                      
wire            fdsu_ex2_op1_norm;                      
wire            fdsu_ex2_result_lfn;                    
wire            fdsu_ex2_single;                        
wire            fdsu_ex2_sqrt;                          
wire    [18:0]  half0_remainder_nxt;                    
wire    [15:0]  half0_total_qt_rt_minus_next;           
wire    [15:0]  half0_total_qt_rt_next;                 
wire    [57:0]  qt_rt_const_pre_sel_q1;                 
wire    [57:0]  qt_rt_const_pre_sel_q2;                 
wire    [57:0]  qt_rt_const_q1;                         
wire    [57:0]  qt_rt_const_q2;                         
wire    [57:0]  qt_rt_const_q3;                         
wire    [57:0]  qt_rt_mins_const_pre_sel_q1;            
wire    [57:0]  qt_rt_mins_const_pre_sel_q2;            
wire            rem_sign;                               
wire    [30:0]  single0_remainder_nxt;                  
wire    [27:0]  single0_total_qt_rt_minus_next;         
wire    [27:0]  single0_total_qt_rt_next;               
wire    [59:0]  sqrt_qt_1_rem_add_op1;                  
wire    [18:0]  sqrt_qt_1_rem_add_op1_h;                
wire    [30:0]  sqrt_qt_1_rem_add_op1_s;                
wire    [59:0]  sqrt_qt_2_rem_add_op1;                  
wire    [18:0]  sqrt_qt_2_rem_add_op1_h;                
wire    [30:0]  sqrt_qt_2_rem_add_op1_s;                
wire    [59:0]  sqrt_qt_r1_rem_add_op1;                 
wire    [18:0]  sqrt_qt_r1_rem_add_op1_h;               
wire    [30:0]  sqrt_qt_r1_rem_add_op1_s;               
wire    [59:0]  sqrt_qt_r2_rem_add_op1;                 
wire    [18:0]  sqrt_qt_r2_rem_add_op1_h;               
wire    [30:0]  sqrt_qt_r2_rem_add_op1_s;               
wire    [59:0]  srt_remainder_shift;                    
wire    [59:0]  srt_remainder_shift_cur;                
wire    [18:0]  srt_remainder_shift_h;                  
wire    [30:0]  srt_remainder_shift_s;                  
wire            srt_remainder_sign;                     
wire            srt_remainder_zero;                     
wire    [57:0]  total_qt_rt_pre_sel;                    




assign fdsu_ex2_op0_norm        = double_pipe_ex2_op0_norm;
assign fdsu_ex2_op1_norm        = double_pipe_ex2_op1_norm;
assign fdsu_ex2_of_rm_lfn       = double_pipe_ex2_of_rm_lfn;
assign fdsu_ex2_result_lfn      = 1'b0;





assign ex2_expnt_result[12:0] =  double_pipe_ex2_expnt_adder_op0[12:0] -
                                 double_pipe_ex2_expnt_adder_op1[12:0];




assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12],
                                      ex2_expnt_result[12:1]};

assign ex2_srt_expnt_rst[12:0] = (fdsu_ex2_sqrt)
                               ? ex2_sqrt_expnt_result[12:0]
                               : ex2_expnt_result[12:0];
assign double_pipe_ex2_srt_expnt_rst[12:0] = ex2_srt_expnt_rst[12:0];
assign fdsu_ex2_expnt_rst[12:0]            = ex2_srt_expnt_rst[12:0];








assign ex2_doub_expnt_of = ~fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] > 12'd1024);
assign ex2_sing_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8:0] > 9'd128);
assign ex2_half_expnt_of = ~fdsu_ex2_expnt_rst[6] && (fdsu_ex2_expnt_rst[5:0] > 6'd16);
assign ex2_bhalf_expnt_of = ex2_sing_expnt_of;




assign double_pipe_ex2_of      = ex2_of_plus;
assign ex2_of_plus = ex2_div_of  && fdsu_ex2_div;
assign ex2_double_div_of  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_doub_expnt_of;
assign ex2_single_div_of  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_sing_expnt_of;
assign ex2_half_div_of    = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_half_expnt_of;
assign ex2_bhalf_div_of   = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_bhalf_expnt_of;
assign ex2_div_of         = fdsu_ex2_double && ex2_double_div_of || 
                            fdsu_ex2_single && ex2_single_div_of ||
                            fdsu_ex2_half   && ex2_half_div_of   ||
                            fdsu_ex2_bhalf  && ex2_bhalf_div_of;


assign ex2_doub_exp_potnt_of  = fdsu_ex2_expnt_rst[12:0] == 13'd1024;
assign ex2_sing_exp_potnt_of  = fdsu_ex2_expnt_rst[9:0]  == 10'd128;
assign ex2_half_exp_potnt_of  = fdsu_ex2_expnt_rst[6:0]  == 7'd16;
assign ex2_bhalf_exp_potnt_of = ex2_sing_exp_potnt_of;
assign ex2_double_potnt_of      = ex2_doub_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_single_potnt_of      = ex2_sing_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_half_potnt_of        = ex2_half_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign ex2_bhalf_potnt_of       = ex2_bhalf_exp_potnt_of &&
                                  fdsu_ex2_op0_norm &&
                                  fdsu_ex2_op1_norm;
assign double_pipe_ex2_potnt_of = fdsu_ex2_div  && (
                                  fdsu_ex2_double && ex2_double_potnt_of ||
                                  fdsu_ex2_single && ex2_single_potnt_of ||
                                  fdsu_ex2_half   && ex2_half_potnt_of   ||
                                  fdsu_ex2_bhalf  && ex2_bhalf_potnt_of);



assign  ex2_doub_expnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] <= 12'hc01);
assign ex2_sing_expnt_uf  = fdsu_ex2_expnt_rst[12] &&(fdsu_ex2_expnt_rst[11:0] <= 12'hf81);
assign ex2_half_expnt_uf  = fdsu_ex2_expnt_rst[12] &&(fdsu_ex2_expnt_rst[11:0] <= 12'hff1);
assign ex2_bhalf_expnt_uf = ex2_sing_expnt_uf;




assign ex2_uf      = ex2_uf_plus;
assign ex2_uf_plus = fdsu_ex2_div && (
                     fdsu_ex2_double && ex2_double_div_uf || 
                     fdsu_ex2_single && ex2_single_div_uf ||
                     fdsu_ex2_half   && ex2_half_div_uf   ||
                     fdsu_ex2_bhalf  && ex2_bhalf_div_uf);
assign ex2_double_div_uf  = fdsu_ex2_op0_norm &&
                           fdsu_ex2_op1_norm &&
                           ex2_doub_expnt_uf;
assign ex2_single_div_uf  = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_sing_expnt_uf; 
assign ex2_half_div_uf    = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_half_expnt_uf;
assign ex2_bhalf_div_uf   = fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            ex2_bhalf_expnt_uf;



assign ex2_double_id_nor_srt_skip =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hbcd);
assign ex2_single_id_nor_srt_skip =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hf6a);
assign ex2_half_id_nor_srt_skip   =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hfe7);
assign ex2_bhalf_id_nor_srt_skip   =  fdsu_ex2_expnt_rst[12]
                                     && (fdsu_ex2_expnt_rst[11:0]<12'hf7a); 

assign ex2_id_nor_srt_skip        = fdsu_ex2_double && ex2_double_id_nor_srt_skip || 
                                    fdsu_ex2_single && ex2_single_id_nor_srt_skip || 
                                    fdsu_ex2_half   && ex2_half_id_nor_srt_skip   || 
                                    fdsu_ex2_bhalf  && ex2_bhalf_id_nor_srt_skip;
assign double_pipe_ex2_uf_srt_skip            = ex2_id_nor_srt_skip;



assign ex2_doub_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hc02);
assign ex2_sing_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hf82);
assign ex2_half_exp_potnt_uf = fdsu_ex2_expnt_rst[12] && (fdsu_ex2_expnt_rst[11:0] == 12'hff2);
assign ex2_bhalf_exp_potnt_uf= ex2_sing_potnt_uf;
assign double_pipe_ex2_potnt_uf          = fdsu_ex2_double && ex2_doub_potnt_uf || 
                               fdsu_ex2_single && ex2_sing_potnt_uf ||
                               fdsu_ex2_half   && ex2_half_potnt_uf ||
                               fdsu_ex2_bhalf  && ex2_bhalf_potnt_uf;
assign ex2_doub_potnt_uf      = (ex2_doub_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_doub_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_sing_potnt_uf      = (ex2_sing_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_sing_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_half_potnt_uf      = (ex2_half_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_half_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);
assign ex2_bhalf_potnt_uf      = (ex2_bhalf_exp_potnt_uf &&
                            fdsu_ex2_op0_norm &&
                            fdsu_ex2_op1_norm &&
                            fdsu_ex2_div)     ||
                           (ex2_bhalf_exp_potnt_uf &&
                            fdsu_ex2_op0_norm);




assign double_pipe_ex2_result_inf  = ex2_of_plus && !fdsu_ex2_of_rm_lfn;
assign double_pipe_ex2_result_lfn  = fdsu_ex2_result_lfn ||
                                     ex2_of_plus &&  fdsu_ex2_of_rm_lfn;
assign double_pipe_ex2_rslt_denorm     = ex2_uf;

                       


always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1c02:double_ex2_result_denorm_round_add_num[52:0] = 53'h1;
  13'h1c01:double_ex2_result_denorm_round_add_num[52:0] = 53'h2;
  13'h1c00:double_ex2_result_denorm_round_add_num[52:0] = 53'h4;
  13'h1bff:double_ex2_result_denorm_round_add_num[52:0] = 53'h8;
  13'h1bfe:double_ex2_result_denorm_round_add_num[52:0] = 53'h10;
  13'h1bfd:double_ex2_result_denorm_round_add_num[52:0] = 53'h20;
  13'h1bfc:double_ex2_result_denorm_round_add_num[52:0] = 53'h40;
  13'h1bfb:double_ex2_result_denorm_round_add_num[52:0] = 53'h80;
  13'h1bfa:double_ex2_result_denorm_round_add_num[52:0] = 53'h100;
  13'h1bf9:double_ex2_result_denorm_round_add_num[52:0] = 53'h200;
  13'h1bf8:double_ex2_result_denorm_round_add_num[52:0] = 53'h400;
  13'h1bf7:double_ex2_result_denorm_round_add_num[52:0] = 53'h800;
  13'h1bf6:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000;
  13'h1bf5:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000;
  13'h1bf4:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000;
  13'h1bf3:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000;
  13'h1bf2:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000;
  13'h1bf1:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000;
  13'h1bf0:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000;
  13'h1bef:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000;
  13'h1bee:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000;
  13'h1bed:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000;
  13'h1bec:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000;
  13'h1beb:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000;
  13'h1bea:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000;
  13'h1be9:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000;
  13'h1be8:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000;
  13'h1be7:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000;
  13'h1be6:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000;
  13'h1be5:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1be4:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1be3:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1be2:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1be1:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1be0:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1bdf:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1bde:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1bdd:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1bdc:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1bdb:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1bda:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1bd9:double_ex2_result_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1bd8:double_ex2_result_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1bd7:double_ex2_result_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1bd6:double_ex2_result_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1bd5:double_ex2_result_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1bd4:double_ex2_result_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1bd3:double_ex2_result_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1bd2:double_ex2_result_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1bd1:double_ex2_result_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1bd0:double_ex2_result_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1bcf:double_ex2_result_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1bce:double_ex2_result_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: double_ex2_result_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1f82:single0_ex2_result_denorm_round_add_num[23:0] = 24'h1;
  13'h1f81:single0_ex2_result_denorm_round_add_num[23:0] = 24'h2;
  13'h1f80:single0_ex2_result_denorm_round_add_num[23:0] = 24'h4;
  13'h1f7f:single0_ex2_result_denorm_round_add_num[23:0] = 24'h8;
  13'h1f7e:single0_ex2_result_denorm_round_add_num[23:0] = 24'h10;
  13'h1f7d:single0_ex2_result_denorm_round_add_num[23:0] = 24'h20;
  13'h1f7c:single0_ex2_result_denorm_round_add_num[23:0] = 24'h40;
  13'h1f7b:single0_ex2_result_denorm_round_add_num[23:0] = 24'h80;
  13'h1f7a:single0_ex2_result_denorm_round_add_num[23:0] = 24'h100;
  13'h1f79:single0_ex2_result_denorm_round_add_num[23:0] = 24'h200;
  13'h1f78:single0_ex2_result_denorm_round_add_num[23:0] = 24'h400;
  13'h1f77:single0_ex2_result_denorm_round_add_num[23:0] = 24'h800;
  13'h1f76:single0_ex2_result_denorm_round_add_num[23:0] = 24'h1000;
  13'h1f75:single0_ex2_result_denorm_round_add_num[23:0] = 24'h2000;
  13'h1f74:single0_ex2_result_denorm_round_add_num[23:0] = 24'h4000;
  13'h1f73:single0_ex2_result_denorm_round_add_num[23:0] = 24'h8000;
  13'h1f72:single0_ex2_result_denorm_round_add_num[23:0] = 24'h10000;
  13'h1f71:single0_ex2_result_denorm_round_add_num[23:0] = 24'h20000;
  13'h1f70:single0_ex2_result_denorm_round_add_num[23:0] = 24'h40000;
  13'h1f6f:single0_ex2_result_denorm_round_add_num[23:0] = 24'h80000;
  13'h1f6e:single0_ex2_result_denorm_round_add_num[23:0] = 24'h100000;
  13'h1f6d:single0_ex2_result_denorm_round_add_num[23:0] = 24'h200000;
  13'h1f6c:single0_ex2_result_denorm_round_add_num[23:0] = 24'h400000;
  13'h1f6b:single0_ex2_result_denorm_round_add_num[23:0] = 24'h800000;
  default: single0_ex2_result_denorm_round_add_num[23:0] = 24'h0;
endcase

end


always @( fdsu_ex2_expnt_rst[12:0])
begin
case(fdsu_ex2_expnt_rst[12:0])
  13'h1ff2:half0_ex2_result_denorm_round_add_num[10:0] = 11'h1;
  13'h1ff1:half0_ex2_result_denorm_round_add_num[10:0] = 11'h2;
  13'h1ff0:half0_ex2_result_denorm_round_add_num[10:0] = 11'h4;
  13'h1fef:half0_ex2_result_denorm_round_add_num[10:0] = 11'h8;
  13'h1fee:half0_ex2_result_denorm_round_add_num[10:0] = 11'h10;
  13'h1fed:half0_ex2_result_denorm_round_add_num[10:0] = 11'h20;
  13'h1fec:half0_ex2_result_denorm_round_add_num[10:0] = 11'h40;
  13'h1feb:half0_ex2_result_denorm_round_add_num[10:0] = 11'h80;
  13'h1fea:half0_ex2_result_denorm_round_add_num[10:0] = 11'h100;
  13'h1fe9:half0_ex2_result_denorm_round_add_num[10:0] = 11'h200;
  13'h1fe8:half0_ex2_result_denorm_round_add_num[10:0] = 11'h400;
  default: half0_ex2_result_denorm_round_add_num[10:0] = 11'h0;
endcase

end
assign bhalf0_ex2_result_denorm_round_add_num[7:0] = single0_ex2_result_denorm_round_add_num[7:0];







































always @(posedge ex2_pipe_clk)
begin
  if(ex2_pipedown)
  begin
    fdsu_ex3_rem_sign        <= srt_remainder_sign;
    fdsu_ex3_rem_zero        <= srt_remainder_zero;
    fdsu_ex3_id_srt_skip     <= ex2_id_nor_srt_skip;
  end
  else
  begin
    fdsu_ex3_rem_sign        <= fdsu_ex3_rem_sign;
    fdsu_ex3_rem_zero        <= fdsu_ex3_rem_zero;
    fdsu_ex3_id_srt_skip    <=  fdsu_ex3_id_srt_skip;
  end
end











































































  
assign bound_sel[3:0] = (fdsu_ex2_div)
                      ? double_pipe_srt_divisor[52:49]
                      : (ex2_srt_first_round)
                        ? 4'b1010
                        : double_pipe_total_qt_rt[56:53];





always @( bound_sel[3:0])
begin
case(bound_sel[3:0])
4'b0000:
   begin
     digit_bound_1[7:0] = 8'b11110100;
     digit_bound_2[7:0] = 8'b11010001;
   end
4'b1000:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100111;
   end
4'b1001:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100100;
   end
4'b1010:
   begin
     digit_bound_1[7:0] = 8'b11111000;
     digit_bound_2[7:0] = 8'b11100001;
   end
4'b1011:
   begin
     digit_bound_1[7:0] = 8'b11110111;
     digit_bound_2[7:0] = 8'b11011111;
   end
4'b1100:
   begin
     digit_bound_1[7:0] = 8'b11110111;
     digit_bound_2[7:0] = 8'b11011100;
   end
4'b1101:
   begin
     digit_bound_1[7:0] = 8'b11110110;
     digit_bound_2[7:0] = 8'b11011001;
   end
4'b1110:
   begin
     digit_bound_1[7:0] = 8'b11110101;
     digit_bound_2[7:0] = 8'b11010111;
   end
4'b1111:
   begin
     digit_bound_1[7:0] = 8'b11110100;
     digit_bound_2[7:0] = 8'b11010001;
   end
default:
   begin
     digit_bound_1[7:0] = 8'b11111001;
     digit_bound_2[7:0] = 8'b11100111;
   end
endcase

end


assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0];
assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0];
assign bound1_cmp_sign        = bound1_cmp_result[7];
assign bound2_cmp_sign        = bound2_cmp_result[7];
assign rem_sign               = double_pipe_srt_remainder[57];












always @( ex2_srt_first_round
       or fdsu_ex2_sqrt
       or double_pipe_srt_remainder[57:49])
begin
if(ex2_srt_first_round && fdsu_ex2_sqrt)
  qtrt_sel_rem[7:0] = {double_pipe_srt_remainder[57],   double_pipe_srt_remainder[55:49]};
else
  qtrt_sel_rem[7:0] =  double_pipe_srt_remainder[57] ? ~double_pipe_srt_remainder[57:50]
                                         :  double_pipe_srt_remainder[57:50];

end














































assign qt_rt_const_q1[57:0] =  double_pipe_qt_rt_const_shift_std[57:0];
assign qt_rt_const_q2[57:0] = {double_pipe_qt_rt_const_shift_std[56:0],1'b0};
assign qt_rt_const_q3[57:0] =  qt_rt_const_q1[57:0] |
                               qt_rt_const_q2[57:0];
















assign total_qt_rt_pre_sel[57:0]         = (rem_sign) ?
                                           double_pipe_total_qt_rt_minus[57:0] :
                                           double_pipe_total_qt_rt[57:0];

assign qt_rt_const_pre_sel_q2[57:0]      = qt_rt_const_q2[57:0];
assign qt_rt_mins_const_pre_sel_q2[57:0] = qt_rt_const_q1[57:0];

assign qt_rt_const_pre_sel_q1[57:0]      = (rem_sign) ?
                                           qt_rt_const_q3[57:0] :
                                           qt_rt_const_q1[57:0];
assign qt_rt_mins_const_pre_sel_q1[57:0] = (rem_sign) ?
                                           qt_rt_const_q2[57:0] :
                                           58'b0;



always @( qt_rt_mins_const_pre_sel_q2[57:0]
       or qt_rt_mins_const_pre_sel_q1[57:0]
       or double_pipe_total_qt_rt_minus[57:0]
       or bound1_cmp_sign
       or total_qt_rt_pre_sel[57:0]
       or qt_rt_const_pre_sel_q1[57:0]
       or qt_rt_const_q3[57:0]
       or bound2_cmp_sign
       or qt_rt_const_pre_sel_q2[57:0]
       or double_pipe_total_qt_rt[57:0])
begin
casez({bound1_cmp_sign,bound2_cmp_sign})
  2'b00:
  begin
    total_qt_rt_next[57:0]       = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_const_pre_sel_q2[57:0];
    total_qt_rt_minus_next[57:0] = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_mins_const_pre_sel_q2[57:0];
  end
  2'b01:
  begin
    total_qt_rt_next[57:0]       = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_const_pre_sel_q1[57:0];
    total_qt_rt_minus_next[57:0] = total_qt_rt_pre_sel[57:0] |
                                      qt_rt_mins_const_pre_sel_q1[57:0];
  end
  2'b1?:
  begin
    total_qt_rt_next[57:0]       = double_pipe_total_qt_rt[57:0];
    total_qt_rt_minus_next[57:0] = double_pipe_total_qt_rt_minus[57:0] |
                                      qt_rt_const_q3[57:0];
  end
  default:
  begin
    total_qt_rt_next[57:0]       = 58'b0;
    total_qt_rt_minus_next[57:0] = 58'b0;
  end
endcase

end
assign double_total_qt_rt_next[57:0]       = total_qt_rt_next[57:0];
assign double_total_qt_rt_minus_next[57:0] = total_qt_rt_minus_next[57:0];
assign single0_total_qt_rt_next[27:0]       = total_qt_rt_next[57:30];
assign single0_total_qt_rt_minus_next[27:0] = total_qt_rt_minus_next[57:30];
assign half0_total_qt_rt_next[15:0]         = total_qt_rt_next[57:42];
assign half0_total_qt_rt_minus_next[15:0]   = total_qt_rt_minus_next[57:42];






assign div_qt_1_rem_add_op1[59:0]     = ~{3'b0,double_pipe_srt_divisor[52:0],4'b0};
assign div_qt_1_rem_add_op1_s[30:0]   = ~{3'b0,double_pipe_srt_divisor[52:29],4'b0};
assign div_qt_1_rem_add_op1_h[18:0]   = ~{3'b0,double_pipe_srt_divisor[52:42],5'b0};

assign div_qt_2_rem_add_op1[59:0]     = ~{2'b0,double_pipe_srt_divisor[52:0],5'b0};
assign div_qt_2_rem_add_op1_s[30:0]   = ~{2'b0,double_pipe_srt_divisor[52:29],5'b0};
assign div_qt_2_rem_add_op1_h[18:0]   = ~{2'b0,double_pipe_srt_divisor[52:42],6'b0};

assign div_qt_r1_rem_add_op1[59:0]    =  {3'b0,double_pipe_srt_divisor[52:0],4'b0};
assign div_qt_r1_rem_add_op1_s[30:0]  =  {3'b0,double_pipe_srt_divisor[52:29],4'b0};
assign div_qt_r1_rem_add_op1_h[18:0]  =  {3'b0,double_pipe_srt_divisor[52:42],5'b0};

assign div_qt_r2_rem_add_op1[59:0]    =  {2'b0,double_pipe_srt_divisor[52:0],5'b0};
assign div_qt_r2_rem_add_op1_s[30:0]  =  {2'b0,double_pipe_srt_divisor[52:29],5'b0};
assign div_qt_r2_rem_add_op1_h[18:0]  =  {2'b0,double_pipe_srt_divisor[52:42],6'b0};



assign sqrt_qt_1_rem_add_op1[59:0]    = ~({2'b0,double_pipe_total_qt_rt[57:0]} |
                                        {3'b0,qt_rt_const_q1[57:1]});
assign sqrt_qt_1_rem_add_op1_s[30:0]  = ~({2'b0,double_pipe_total_qt_rt[57:30],1'b0} |
                                         {3'b0,qt_rt_const_q1[57:30]});
assign sqrt_qt_1_rem_add_op1_h[18:0]  = ~({2'b0,double_pipe_total_qt_rt[57:42],1'b0} |
                                         {3'b0,qt_rt_const_q1[57:42]});

assign sqrt_qt_2_rem_add_op1[59:0]  = ~({1'b0,double_pipe_total_qt_rt[57:0],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0});

assign sqrt_qt_2_rem_add_op1_s[30:0]  = ~({1'b0,double_pipe_total_qt_rt[57:30],2'b0} |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0});
assign sqrt_qt_2_rem_add_op1_h[18:0]  = ~({1'b0,double_pipe_total_qt_rt[57:42],2'b0} |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0});

assign sqrt_qt_r1_rem_add_op1[59:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:0]} |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0}  |
                                        {2'b0,qt_rt_const_q1[57:0]}       |
                                        {3'b0,qt_rt_const_q1[57:1]};
assign sqrt_qt_r1_rem_add_op1_s[30:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:30],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0}  |
                                        {2'b0,qt_rt_const_q1[57:30],1'b0}       |
                                        {3'b0,qt_rt_const_q1[57:30]};
assign sqrt_qt_r1_rem_add_op1_h[18:0] =   {2'b0,double_pipe_total_qt_rt_minus[57:42],1'b0} |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0}  |
                                        {2'b0,qt_rt_const_q1[57:42],1'b0}       |
                                        {3'b0,qt_rt_const_q1[57:42]};

assign sqrt_qt_r2_rem_add_op1[59:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:0],1'b0} |
                                        {qt_rt_const_q1[57:0],2'b0}       |
                                        {1'b0,qt_rt_const_q1[57:0],1'b0};
assign sqrt_qt_r2_rem_add_op1_s[30:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:30],2'b0} |
                                        {qt_rt_const_q1[57:30],3'b0}       |
                                        {1'b0,qt_rt_const_q1[57:30],2'b0};
assign sqrt_qt_r2_rem_add_op1_h[18:0] =   {1'b0,
                                         double_pipe_total_qt_rt_minus[57:42],2'b0} |
                                        {qt_rt_const_q1[57:42],3'b0}       |
                                        {1'b0,qt_rt_const_q1[57:42],2'b0};


always @( div_qt_1_rem_add_op1_s[30:0]
       or sqrt_qt_2_rem_add_op1_h[18:0]
       or rem_sign
       or div_qt_1_rem_add_op1[59:0]
       or sqrt_qt_r2_rem_add_op1[59:0]
       or div_qt_2_rem_add_op1_h[18:0]
       or sqrt_qt_r1_rem_add_op1[59:0]
       or sqrt_qt_1_rem_add_op1[59:0]
       or div_qt_r1_rem_add_op1[59:0]
       or div_qt_r2_rem_add_op1_h[18:0]
       or div_qt_2_rem_add_op1[59:0]
       or fdsu_ex2_sqrt
       or sqrt_qt_2_rem_add_op1[59:0]
       or sqrt_qt_r2_rem_add_op1_h[18:0]
       or div_qt_r1_rem_add_op1_s[30:0]
       or sqrt_qt_r1_rem_add_op1_h[18:0]
       or sqrt_qt_2_rem_add_op1_s[30:0]
       or sqrt_qt_r2_rem_add_op1_s[30:0]
       or sqrt_qt_1_rem_add_op1_h[18:0]
       or div_qt_r1_rem_add_op1_h[18:0]
       or sqrt_qt_r1_rem_add_op1_s[30:0]
       or div_qt_1_rem_add_op1_h[18:0]
       or div_qt_r2_rem_add_op1_s[30:0]
       or div_qt_r2_rem_add_op1[59:0]
       or sqrt_qt_1_rem_add_op1_s[30:0]
       or div_qt_2_rem_add_op1_s[30:0])
begin
case({rem_sign,fdsu_ex2_sqrt})
  2'b01:
  begin
        rem_add1_op1[59:0]   = sqrt_qt_1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = sqrt_qt_2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = sqrt_qt_1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = sqrt_qt_2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = sqrt_qt_1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = sqrt_qt_2_rem_add_op1_h[18:0];
  end
  2'b00:
  begin
        rem_add1_op1[59:0]   = div_qt_1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = div_qt_2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = div_qt_1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = div_qt_2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = div_qt_1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = div_qt_2_rem_add_op1_h[18:0];
  end
  2'b11:
  begin
        rem_add1_op1[59:0]   = sqrt_qt_r1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = sqrt_qt_r2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = sqrt_qt_r1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = sqrt_qt_r2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = sqrt_qt_r1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = sqrt_qt_r2_rem_add_op1_h[18:0];
  end
  2'b10:
  begin
        rem_add1_op1[59:0]   = div_qt_r1_rem_add_op1[59:0];
        rem_add2_op1[59:0]   = div_qt_r2_rem_add_op1[59:0];
        rem_add1_op1_s[30:0] = div_qt_r1_rem_add_op1_s[30:0];
        rem_add2_op1_s[30:0] = div_qt_r2_rem_add_op1_s[30:0];
        rem_add1_op1_h[18:0] = div_qt_r1_rem_add_op1_h[18:0];
        rem_add2_op1_h[18:0] = div_qt_r2_rem_add_op1_h[18:0];
  end
  default :
  begin
        rem_add1_op1[59:0] = 60'b0;
        rem_add2_op1[59:0] = 60'b0;
        rem_add1_op1_s[30:0] = 31'b0;
        rem_add2_op1_s[30:0] = 31'b0;
        rem_add1_op1_h[18:0] = 19'b0;
        rem_add2_op1_h[18:0] = 19'b0;
  end
  endcase

end
assign srt_remainder_shift[59:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:0],2'b0};
assign srt_remainder_shift_s[30:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:29],2'b0};
assign srt_remainder_shift_h[18:0] = {double_pipe_srt_remainder[59],
                                    double_pipe_srt_remainder[56:41],2'b0};
assign srt_remainder_shift_cur[59:0] = {60{fdsu_ex2_double}} & srt_remainder_shift[59:0]  |
                                       {60{fdsu_ex2_single}} & {srt_remainder_shift_s[30:0],29'b0} |
                                       {60{(fdsu_ex2_half 
                                        || fdsu_ex2_bhalf)}} & {srt_remainder_shift_h[18:0],41'b0};
assign double_srt_remainder_shift[59:0]     = srt_remainder_shift[59:0];

assign double_srt_remainder_add1_op1[59:0]  = rem_add1_op1[59:0];
assign double_srt_remainder_add1_op2[59:0]  = {59'b0, ~rem_sign};


assign double_srt_remainder_add2_op1[59:0]  = rem_add2_op1[59:0];
assign double_srt_remainder_add2_op2[59:0]  = {59'b0, ~rem_sign};
















always @( srt_remainder_shift_cur[59:0]
       or bound1_cmp_sign
       or double_pipe_cur_rem_1[59:0]
       or double_pipe_cur_rem_2[59:0]
       or bound2_cmp_sign)
begin
case({bound1_cmp_sign,bound2_cmp_sign})
  2'b00:   cur_rem[59:0]         = double_pipe_cur_rem_2[59:0];
  2'b01:   cur_rem[59:0]         = double_pipe_cur_rem_1[59:0];
  default: cur_rem[59:0]         = srt_remainder_shift_cur[59:0];
endcase

end
assign double_remainder_nxt[59:0]   = cur_rem[59:0];
assign single0_remainder_nxt[30:0]  = cur_rem[59:29];
assign half0_remainder_nxt[18:0]    = cur_rem[59:41];
assign bhalf0_remainder_nxt[14:0]   = cur_rem[59:45];




assign double_pipe_srt_remainder_zero         = srt_remainder_zero;
assign double_srt_remainder_zero  = ~|double_srt_remainder[59:0];
assign srt_remainder_zero = double_srt_remainder_zero;

assign srt_remainder_sign        =   double_remainder_nxt[59];

assign double_pipe_ex2_uf = ex2_uf;

endmodule