data/full_repos/permissive/486588912/verilog/mmio_addr.v
data/verilator_xmls/b74b0ce4-135a-472f-8980-be4a0f283ee9.xml
module mmio_addr(
    input [31:0] addr,
    output reg is_mmio
);
    always @* begin
        casex(addr)
            32'hFFFF????:   is_mmio = 1;
            default:        is_mmio = 0;
        endcase
    end

endmodule
module mmio_addr(
    input [31:0] addr,
    output reg is_mmio
);

    always @* begin
        casex(addr)
            32'hFFFF????:   is_mmio = 1;
            default:        is_mmio = 0;
        endcase
    end

endmodule