data/full_repos/permissive/513806017/generated/Leros.v
data/verilator_xmls/89e8d668-0412-4ac1-97d0-bdf2db6b5e63.xml
module Leros(
  input         clock,
  input         reset,
  output [31:0] io_dout,
  output [31:0] io_dbg_acc,
  output [9:0]  io_dbg_pc,
  output [15:0] io_dbg_instr,
  output        io_dbg_exit
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_3;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
`endif
  wire  alu_clock;
  wire  alu_reset;
  wire [2:0] alu_io_op;
  wire [31:0] alu_io_din;
  wire  alu_io_ena;
  wire [31:0] alu_io_accu;
  wire  mem_clock;
  wire  mem_reset;
  wire [9:0] mem_io_addr;
  wire [15:0] mem_io_instr;
  reg [31:0] registerMem [0:255];
  wire  registerMem_registerRead_en;
  wire [7:0] registerMem_registerRead_addr;
  wire [31:0] registerMem_registerRead_data;
  wire [31:0] registerMem_MPORT_data;
  wire [7:0] registerMem_MPORT_addr;
  wire  registerMem_MPORT_mask;
  wire  registerMem_MPORT_en;
  reg  registerMem_registerRead_en_pipe_0;
  reg [7:0] registerMem_registerRead_addr_pipe_0;
  reg [31:0] dataMem [0:1023];
  wire  dataMem_dataRead_en;
  wire [9:0] dataMem_dataRead_addr;
  wire [31:0] dataMem_dataRead_data;
  wire [31:0] dataMem_MPORT_1_data;
  wire [9:0] dataMem_MPORT_1_addr;
  wire  dataMem_MPORT_1_mask;
  wire  dataMem_MPORT_1_en;
  reg  dataMem_dataRead_en_pipe_0;
  reg [9:0] dataMem_dataRead_addr_pipe_0;
  wire [7:0] dec_io_din;
  wire  dec_io_dout_ena;
  wire [2:0] dec_io_dout_op;
  wire  dec_io_dout_isRegOpd;
  wire  dec_io_dout_isStore;
  wire  dec_io_dout_isStoreInd;
  wire  dec_io_dout_isLoadInd;
  wire  dec_io_dout_isLoadAddr;
  wire  dec_io_dout_enahi;
  wire  dec_io_dout_enah2i;
  wire  dec_io_dout_enah3i;
  wire  dec_io_dout_nosext;
  wire  dec_io_dout_exit;
  reg [9:0] pcReg;
  reg [9:0] addrReg;
  reg  stateReg;
  wire  _T_2 = ~stateReg;
  wire  _GEN_0 = stateReg ? 1'h0 : stateReg;
  wire  _GEN_1 = ~stateReg | _GEN_0;
  wire [9:0] pcNext = pcReg + 10'h1;
  reg  decReg_ena;
  reg [2:0] decReg_op;
  reg  decReg_isRegOpd;
  reg  decReg_isStore;
  reg  decReg_isStoreInd;
  reg  decReg_isLoadInd;
  reg  decReg_isLoadAddr;
  reg  decReg_exit;
  reg [31:0] opdReg;
  wire [15:0] _registerRead_T = mem_io_instr;
  wire [31:0] _dataRead_T_2 = decReg_isLoadAddr & stateReg ? alu_io_accu : {{22'd0}, addrReg};
  wire [7:0] _op16sex_T_1 = mem_io_instr[7:0];
  wire [31:0] _operand_T_2 = {24'h0,mem_io_instr[7:0]};
  wire [23:0] _operand_T_3 = {{16{_op16sex_T_1[7]}},_op16sex_T_1};
  wire [31:0] _operand_T_6 = {_operand_T_3,alu_io_accu[7:0]};
  wire [15:0] _operand_T_7 = {{8{_op16sex_T_1[7]}},_op16sex_T_1};
  wire [31:0] _operand_T_10 = {_operand_T_7,alu_io_accu[15:0]};
  wire [31:0] _operand_T_14 = {mem_io_instr[7:0],alu_io_accu[23:0]};
  wire [31:0] _GEN_8 = dec_io_dout_enah3i ? $signed(_operand_T_14) : $signed({{24{_op16sex_T_1[7]}},_op16sex_T_1});
  wire [31:0] _GEN_9 = dec_io_dout_enah2i ? $signed(_operand_T_10) : $signed(_GEN_8);
  wire [31:0] _GEN_10 = dec_io_dout_enahi ? $signed(_operand_T_6) : $signed(_GEN_9);
  wire [31:0] _alu_io_din_T = decReg_isRegOpd ? registerMem_registerRead_data : opdReg;
  wire [31:0] _opdReg_T = dec_io_dout_nosext ? $signed(_operand_T_2) : $signed(_GEN_10);
  wire [31:0] _GEN_17 = decReg_isLoadAddr ? alu_io_accu : {{22'd0}, addrReg};
  wire  _GEN_26 = stateReg & decReg_isStore;
  wire [31:0] _GEN_29 = stateReg ? _GEN_17 : {{22'd0}, addrReg};
  wire  _GEN_32 = stateReg & decReg_isStoreInd;
  wire [31:0] _GEN_55 = _T_2 ? {{22'd0}, addrReg} : _GEN_29;
  reg  exit;
  reg  exit_REG;
  reg [31:0] io_dbg_acc_REG;
  reg [31:0] io_dbg_acc_REG_1;
  reg [9:0] io_dbg_pc_REG;
  reg [9:0] io_dbg_pc_REG_1;
  reg [15:0] io_dbg_instr_REG;
  reg [15:0] io_dbg_instr_REG_1;
  reg  io_dbg_exit_REG;
  reg  io_dbg_exit_REG_1;
  wire [31:0] _GEN_61 = reset ? 32'h0 : _GEN_55;
  Alu alu (
    .clock(alu_clock),
    .reset(alu_reset),
    .io_op(alu_io_op),
    .io_din(alu_io_din),
    .io_ena(alu_io_ena),
    .io_accu(alu_io_accu)
  );
  InstrMem mem (
    .clock(mem_clock),
    .reset(mem_reset),
    .io_addr(mem_io_addr),
    .io_instr(mem_io_instr)
  );
  Decode dec (
    .io_din(dec_io_din),
    .io_dout_ena(dec_io_dout_ena),
    .io_dout_op(dec_io_dout_op),
    .io_dout_isRegOpd(dec_io_dout_isRegOpd),
    .io_dout_isStore(dec_io_dout_isStore),
    .io_dout_isStoreInd(dec_io_dout_isStoreInd),
    .io_dout_isLoadInd(dec_io_dout_isLoadInd),
    .io_dout_isLoadAddr(dec_io_dout_isLoadAddr),
    .io_dout_enahi(dec_io_dout_enahi),
    .io_dout_enah2i(dec_io_dout_enah2i),
    .io_dout_enah3i(dec_io_dout_enah3i),
    .io_dout_nosext(dec_io_dout_nosext),
    .io_dout_exit(dec_io_dout_exit)
  );
  assign registerMem_registerRead_en = registerMem_registerRead_en_pipe_0;
  assign registerMem_registerRead_addr = registerMem_registerRead_addr_pipe_0;
  assign registerMem_registerRead_data = registerMem[registerMem_registerRead_addr];
  assign registerMem_MPORT_data = alu_io_accu;
  assign registerMem_MPORT_addr = opdReg[7:0];
  assign registerMem_MPORT_mask = 1'h1;
  assign registerMem_MPORT_en = _T_2 ? 1'h0 : _GEN_26;
  assign dataMem_dataRead_en = dataMem_dataRead_en_pipe_0;
  assign dataMem_dataRead_addr = dataMem_dataRead_addr_pipe_0;
  assign dataMem_dataRead_data = dataMem[dataMem_dataRead_addr];
  assign dataMem_MPORT_1_data = alu_io_accu;
  assign dataMem_MPORT_1_addr = addrReg;
  assign dataMem_MPORT_1_mask = 1'h1;
  assign dataMem_MPORT_1_en = _T_2 ? 1'h0 : _GEN_32;
  assign io_dout = 32'h2a;
  assign io_dbg_acc = io_dbg_acc_REG_1;
  assign io_dbg_pc = io_dbg_pc_REG_1;
  assign io_dbg_instr = io_dbg_instr_REG_1;
  assign io_dbg_exit = io_dbg_exit_REG_1;
  assign alu_clock = clock;
  assign alu_reset = reset;
  assign alu_io_op = decReg_op;
  assign alu_io_din = decReg_isLoadInd ? dataMem_dataRead_data : _alu_io_din_T;
  assign alu_io_ena = decReg_ena & stateReg;
  assign mem_clock = clock;
  assign mem_reset = reset;
  assign mem_io_addr = pcReg + 10'h1;
  assign dec_io_din = mem_io_instr[15:8];
  always @(posedge clock) begin
    if (registerMem_MPORT_en & registerMem_MPORT_mask) begin
      registerMem[registerMem_MPORT_addr] <= registerMem_MPORT_data;
    end
    registerMem_registerRead_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      registerMem_registerRead_addr_pipe_0 <= _registerRead_T[7:0];
    end
    if (dataMem_MPORT_1_en & dataMem_MPORT_1_mask) begin
      dataMem[dataMem_MPORT_1_addr] <= dataMem_MPORT_1_data;
    end
    dataMem_dataRead_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      dataMem_dataRead_addr_pipe_0 <= _dataRead_T_2[9:0];
    end
    if (reset) begin
      pcReg <= 10'h0;
    end else if (!(_T_2)) begin
      if (stateReg) begin
        pcReg <= pcNext;
      end
    end
    addrReg <= _GEN_61[9:0];
    if (reset) begin
      stateReg <= 1'h0;
    end else begin
      stateReg <= _GEN_1;
    end
    if (reset) begin
      decReg_ena <= 1'h0;
    end else if (_T_2) begin
      decReg_ena <= dec_io_dout_ena;
    end
    if (reset) begin
      decReg_op <= 3'h0;
    end else if (_T_2) begin
      decReg_op <= dec_io_dout_op;
    end
    if (reset) begin
      decReg_isRegOpd <= 1'h0;
    end else if (_T_2) begin
      decReg_isRegOpd <= dec_io_dout_isRegOpd;
    end
    if (reset) begin
      decReg_isStore <= 1'h0;
    end else if (_T_2) begin
      decReg_isStore <= dec_io_dout_isStore;
    end
    if (reset) begin
      decReg_isStoreInd <= 1'h0;
    end else if (_T_2) begin
      decReg_isStoreInd <= dec_io_dout_isStoreInd;
    end
    if (reset) begin
      decReg_isLoadInd <= 1'h0;
    end else if (_T_2) begin
      decReg_isLoadInd <= dec_io_dout_isLoadInd;
    end
    if (reset) begin
      decReg_isLoadAddr <= 1'h0;
    end else if (_T_2) begin
      decReg_isLoadAddr <= dec_io_dout_isLoadAddr;
    end
    if (reset) begin
      decReg_exit <= 1'h0;
    end else if (_T_2) begin
      decReg_exit <= dec_io_dout_exit;
    end
    if (reset) begin
      opdReg <= 32'h0;
    end else if (_T_2) begin
      opdReg <= _opdReg_T;
    end
    if (reset) begin
      exit <= 1'h0;
    end else begin
      exit <= exit_REG;
    end
    exit_REG <= decReg_exit;
    io_dbg_acc_REG <= alu_io_accu;
    io_dbg_acc_REG_1 <= io_dbg_acc_REG;
    io_dbg_pc_REG <= pcReg;
    io_dbg_pc_REG_1 <= io_dbg_pc_REG;
    io_dbg_instr_REG <= mem_io_instr;
    io_dbg_instr_REG_1 <= io_dbg_instr_REG;
    io_dbg_exit_REG <= exit;
    io_dbg_exit_REG_1 <= io_dbg_exit_REG;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    registerMem[initvar] = _RAND_0[31:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dataMem[initvar] = _RAND_3[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  registerMem_registerRead_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  registerMem_registerRead_addr_pipe_0 = _RAND_2[7:0];
  _RAND_4 = {1{`RANDOM}};
  dataMem_dataRead_en_pipe_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  dataMem_dataRead_addr_pipe_0 = _RAND_5[9:0];
  _RAND_6 = {1{`RANDOM}};
  pcReg = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  addrReg = _RAND_7[9:0];
  _RAND_8 = {1{`RANDOM}};
  stateReg = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  decReg_ena = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  decReg_op = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  decReg_isRegOpd = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  decReg_isStore = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  decReg_isStoreInd = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  decReg_isLoadInd = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  decReg_isLoadAddr = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  decReg_exit = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  opdReg = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  exit = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  exit_REG = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  io_dbg_acc_REG = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  io_dbg_acc_REG_1 = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  io_dbg_pc_REG = _RAND_22[9:0];
  _RAND_23 = {1{`RANDOM}};
  io_dbg_pc_REG_1 = _RAND_23[9:0];
  _RAND_24 = {1{`RANDOM}};
  io_dbg_instr_REG = _RAND_24[15:0];
  _RAND_25 = {1{`RANDOM}};
  io_dbg_instr_REG_1 = _RAND_25[15:0];
  _RAND_26 = {1{`RANDOM}};
  io_dbg_exit_REG = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  io_dbg_exit_REG_1 = _RAND_27[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Leros(
  input         clock,
  input         reset,
  output [31:0] io_dout,
  output [31:0] io_dbg_acc,
  output [9:0]  io_dbg_pc,
  output [15:0] io_dbg_instr,
  output        io_dbg_exit
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_3;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
`endif
  wire  alu_clock;
  wire  alu_reset;
  wire [2:0] alu_io_op;
  wire [31:0] alu_io_din;
  wire  alu_io_ena;
  wire [31:0] alu_io_accu;
  wire  mem_clock;
  wire  mem_reset;
  wire [9:0] mem_io_addr;
  wire [15:0] mem_io_instr;
  reg [31:0] registerMem [0:255];
  wire  registerMem_registerRead_en;
  wire [7:0] registerMem_registerRead_addr;
  wire [31:0] registerMem_registerRead_data;
  wire [31:0] registerMem_MPORT_data;
  wire [7:0] registerMem_MPORT_addr;
  wire  registerMem_MPORT_mask;
  wire  registerMem_MPORT_en;
  reg  registerMem_registerRead_en_pipe_0;
  reg [7:0] registerMem_registerRead_addr_pipe_0;
  reg [31:0] dataMem [0:1023];
  wire  dataMem_dataRead_en;
  wire [9:0] dataMem_dataRead_addr;
  wire [31:0] dataMem_dataRead_data;
  wire [31:0] dataMem_MPORT_1_data;
  wire [9:0] dataMem_MPORT_1_addr;
  wire  dataMem_MPORT_1_mask;
  wire  dataMem_MPORT_1_en;
  reg  dataMem_dataRead_en_pipe_0;
  reg [9:0] dataMem_dataRead_addr_pipe_0;
  wire [7:0] dec_io_din;
  wire  dec_io_dout_ena;
  wire [2:0] dec_io_dout_op;
  wire  dec_io_dout_isRegOpd;
  wire  dec_io_dout_isStore;
  wire  dec_io_dout_isStoreInd;
  wire  dec_io_dout_isLoadInd;
  wire  dec_io_dout_isLoadAddr;
  wire  dec_io_dout_enahi;
  wire  dec_io_dout_enah2i;
  wire  dec_io_dout_enah3i;
  wire  dec_io_dout_nosext;
  wire  dec_io_dout_exit;
  reg [9:0] pcReg;
  reg [9:0] addrReg;
  reg  stateReg;
  wire  _T_2 = ~stateReg;
  wire  _GEN_0 = stateReg ? 1'h0 : stateReg;
  wire  _GEN_1 = ~stateReg | _GEN_0;
  wire [9:0] pcNext = pcReg + 10'h1;
  reg  decReg_ena;
  reg [2:0] decReg_op;
  reg  decReg_isRegOpd;
  reg  decReg_isStore;
  reg  decReg_isStoreInd;
  reg  decReg_isLoadInd;
  reg  decReg_isLoadAddr;
  reg  decReg_exit;
  reg [31:0] opdReg;
  wire [15:0] _registerRead_T = mem_io_instr;
  wire [31:0] _dataRead_T_2 = decReg_isLoadAddr & stateReg ? alu_io_accu : {{22'd0}, addrReg};
  wire [7:0] _op16sex_T_1 = mem_io_instr[7:0];
  wire [31:0] _operand_T_2 = {24'h0,mem_io_instr[7:0]};
  wire [23:0] _operand_T_3 = {{16{_op16sex_T_1[7]}},_op16sex_T_1};
  wire [31:0] _operand_T_6 = {_operand_T_3,alu_io_accu[7:0]};
  wire [15:0] _operand_T_7 = {{8{_op16sex_T_1[7]}},_op16sex_T_1};
  wire [31:0] _operand_T_10 = {_operand_T_7,alu_io_accu[15:0]};
  wire [31:0] _operand_T_14 = {mem_io_instr[7:0],alu_io_accu[23:0]};
  wire [31:0] _GEN_8 = dec_io_dout_enah3i ? $signed(_operand_T_14) : $signed({{24{_op16sex_T_1[7]}},_op16sex_T_1});
  wire [31:0] _GEN_9 = dec_io_dout_enah2i ? $signed(_operand_T_10) : $signed(_GEN_8);
  wire [31:0] _GEN_10 = dec_io_dout_enahi ? $signed(_operand_T_6) : $signed(_GEN_9);
  wire [31:0] _alu_io_din_T = decReg_isRegOpd ? registerMem_registerRead_data : opdReg;
  wire [31:0] _opdReg_T = dec_io_dout_nosext ? $signed(_operand_T_2) : $signed(_GEN_10);
  wire [31:0] _GEN_17 = decReg_isLoadAddr ? alu_io_accu : {{22'd0}, addrReg};
  wire  _GEN_26 = stateReg & decReg_isStore;
  wire [31:0] _GEN_29 = stateReg ? _GEN_17 : {{22'd0}, addrReg};
  wire  _GEN_32 = stateReg & decReg_isStoreInd;
  wire [31:0] _GEN_55 = _T_2 ? {{22'd0}, addrReg} : _GEN_29;
  reg  exit;
  reg  exit_REG;
  reg [31:0] io_dbg_acc_REG;
  reg [31:0] io_dbg_acc_REG_1;
  reg [9:0] io_dbg_pc_REG;
  reg [9:0] io_dbg_pc_REG_1;
  reg [15:0] io_dbg_instr_REG;
  reg [15:0] io_dbg_instr_REG_1;
  reg  io_dbg_exit_REG;
  reg  io_dbg_exit_REG_1;
  wire [31:0] _GEN_61 = reset ? 32'h0 : _GEN_55;
  Alu alu (
    .clock(alu_clock),
    .reset(alu_reset),
    .io_op(alu_io_op),
    .io_din(alu_io_din),
    .io_ena(alu_io_ena),
    .io_accu(alu_io_accu)
  );
  InstrMem mem (
    .clock(mem_clock),
    .reset(mem_reset),
    .io_addr(mem_io_addr),
    .io_instr(mem_io_instr)
  );
  Decode dec (
    .io_din(dec_io_din),
    .io_dout_ena(dec_io_dout_ena),
    .io_dout_op(dec_io_dout_op),
    .io_dout_isRegOpd(dec_io_dout_isRegOpd),
    .io_dout_isStore(dec_io_dout_isStore),
    .io_dout_isStoreInd(dec_io_dout_isStoreInd),
    .io_dout_isLoadInd(dec_io_dout_isLoadInd),
    .io_dout_isLoadAddr(dec_io_dout_isLoadAddr),
    .io_dout_enahi(dec_io_dout_enahi),
    .io_dout_enah2i(dec_io_dout_enah2i),
    .io_dout_enah3i(dec_io_dout_enah3i),
    .io_dout_nosext(dec_io_dout_nosext),
    .io_dout_exit(dec_io_dout_exit)
  );
  assign registerMem_registerRead_en = registerMem_registerRead_en_pipe_0;
  assign registerMem_registerRead_addr = registerMem_registerRead_addr_pipe_0;
  assign registerMem_registerRead_data = registerMem[registerMem_registerRead_addr];
  assign registerMem_MPORT_data = alu_io_accu;
  assign registerMem_MPORT_addr = opdReg[7:0];
  assign registerMem_MPORT_mask = 1'h1;
  assign registerMem_MPORT_en = _T_2 ? 1'h0 : _GEN_26;
  assign dataMem_dataRead_en = dataMem_dataRead_en_pipe_0;
  assign dataMem_dataRead_addr = dataMem_dataRead_addr_pipe_0;
  assign dataMem_dataRead_data = dataMem[dataMem_dataRead_addr];
  assign dataMem_MPORT_1_data = alu_io_accu;
  assign dataMem_MPORT_1_addr = addrReg;
  assign dataMem_MPORT_1_mask = 1'h1;
  assign dataMem_MPORT_1_en = _T_2 ? 1'h0 : _GEN_32;
  assign io_dout = 32'h2a;
  assign io_dbg_acc = io_dbg_acc_REG_1;
  assign io_dbg_pc = io_dbg_pc_REG_1;
  assign io_dbg_instr = io_dbg_instr_REG_1;
  assign io_dbg_exit = io_dbg_exit_REG_1;
  assign alu_clock = clock;
  assign alu_reset = reset;
  assign alu_io_op = decReg_op;
  assign alu_io_din = decReg_isLoadInd ? dataMem_dataRead_data : _alu_io_din_T;
  assign alu_io_ena = decReg_ena & stateReg;
  assign mem_clock = clock;
  assign mem_reset = reset;
  assign mem_io_addr = pcReg + 10'h1;
  assign dec_io_din = mem_io_instr[15:8];
  always @(posedge clock) begin
    if (registerMem_MPORT_en & registerMem_MPORT_mask) begin
      registerMem[registerMem_MPORT_addr] <= registerMem_MPORT_data;
    end
    registerMem_registerRead_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      registerMem_registerRead_addr_pipe_0 <= _registerRead_T[7:0];
    end
    if (dataMem_MPORT_1_en & dataMem_MPORT_1_mask) begin
      dataMem[dataMem_MPORT_1_addr] <= dataMem_MPORT_1_data;
    end
    dataMem_dataRead_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      dataMem_dataRead_addr_pipe_0 <= _dataRead_T_2[9:0];
    end
    if (reset) begin
      pcReg <= 10'h0;
    end else if (!(_T_2)) begin
      if (stateReg) begin
        pcReg <= pcNext;
      end
    end
    addrReg <= _GEN_61[9:0];
    if (reset) begin
      stateReg <= 1'h0;
    end else begin
      stateReg <= _GEN_1;
    end
    if (reset) begin
      decReg_ena <= 1'h0;
    end else if (_T_2) begin
      decReg_ena <= dec_io_dout_ena;
    end
    if (reset) begin
      decReg_op <= 3'h0;
    end else if (_T_2) begin
      decReg_op <= dec_io_dout_op;
    end
    if (reset) begin
      decReg_isRegOpd <= 1'h0;
    end else if (_T_2) begin
      decReg_isRegOpd <= dec_io_dout_isRegOpd;
    end
    if (reset) begin
      decReg_isStore <= 1'h0;
    end else if (_T_2) begin
      decReg_isStore <= dec_io_dout_isStore;
    end
    if (reset) begin
      decReg_isStoreInd <= 1'h0;
    end else if (_T_2) begin
      decReg_isStoreInd <= dec_io_dout_isStoreInd;
    end
    if (reset) begin
      decReg_isLoadInd <= 1'h0;
    end else if (_T_2) begin
      decReg_isLoadInd <= dec_io_dout_isLoadInd;
    end
    if (reset) begin
      decReg_isLoadAddr <= 1'h0;
    end else if (_T_2) begin
      decReg_isLoadAddr <= dec_io_dout_isLoadAddr;
    end
    if (reset) begin
      decReg_exit <= 1'h0;
    end else if (_T_2) begin
      decReg_exit <= dec_io_dout_exit;
    end
    if (reset) begin
      opdReg <= 32'h0;
    end else if (_T_2) begin
      opdReg <= _opdReg_T;
    end
    if (reset) begin
      exit <= 1'h0;
    end else begin
      exit <= exit_REG;
    end
    exit_REG <= decReg_exit;
    io_dbg_acc_REG <= alu_io_accu;
    io_dbg_acc_REG_1 <= io_dbg_acc_REG;
    io_dbg_pc_REG <= pcReg;
    io_dbg_pc_REG_1 <= io_dbg_pc_REG;
    io_dbg_instr_REG <= mem_io_instr;
    io_dbg_instr_REG_1 <= io_dbg_instr_REG;
    io_dbg_exit_REG <= exit;
    io_dbg_exit_REG_1 <= io_dbg_exit_REG;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    registerMem[initvar] = _RAND_0[31:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dataMem[initvar] = _RAND_3[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  registerMem_registerRead_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  registerMem_registerRead_addr_pipe_0 = _RAND_2[7:0];
  _RAND_4 = {1{`RANDOM}};
  dataMem_dataRead_en_pipe_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  dataMem_dataRead_addr_pipe_0 = _RAND_5[9:0];
  _RAND_6 = {1{`RANDOM}};
  pcReg = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  addrReg = _RAND_7[9:0];
  _RAND_8 = {1{`RANDOM}};
  stateReg = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  decReg_ena = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  decReg_op = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  decReg_isRegOpd = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  decReg_isStore = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  decReg_isStoreInd = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  decReg_isLoadInd = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  decReg_isLoadAddr = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  decReg_exit = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  opdReg = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  exit = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  exit_REG = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  io_dbg_acc_REG = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  io_dbg_acc_REG_1 = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  io_dbg_pc_REG = _RAND_22[9:0];
  _RAND_23 = {1{`RANDOM}};
  io_dbg_pc_REG_1 = _RAND_23[9:0];
  _RAND_24 = {1{`RANDOM}};
  io_dbg_instr_REG = _RAND_24[15:0];
  _RAND_25 = {1{`RANDOM}};
  io_dbg_instr_REG_1 = _RAND_25[15:0];
  _RAND_26 = {1{`RANDOM}};
  io_dbg_exit_REG = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  io_dbg_exit_REG_1 = _RAND_27[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule