data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module fulladder5bits(a,b,s0,s1);
	input[5:0]  a,b;
	output[5:0] s0;
	output s1;
	reg[5:0] s0;
	reg s1;
	wire sum1,sum2,sum3,sum4,sum5;
	
	halfsum   SOMA1(a[0],b[0],s0[0],sum1);
	fulladder SOMA2(a[1],b[1],sum1,s0[1],sum2);
	fulladder SOMA3(a[2],b[2],sum2,so[2],sum3);
	fulladder SOMA4(a[3],b[3],sum3,so[3],sum4);
	fulladder SOMA5(a[4],b[4],sum4,so[4],s1);
endmodule
module fulladder5bits(a,b,s0,s1);

	input[5:0]  a,b;
	output[5:0] s0;
	output s1;
	reg[5:0] s0;
	reg s1;
	wire sum1,sum2,sum3,sum4,sum5;
	
	halfsum   SOMA1(a[0],b[0],s0[0],sum1);
	fulladder SOMA2(a[1],b[1],sum1,s0[1],sum2);
	fulladder SOMA3(a[2],b[2],sum2,so[2],sum3);
	fulladder SOMA4(a[3],b[3],sum3,so[3],sum4);
	fulladder SOMA5(a[4],b[4],sum4,so[4],s1);
endmodule