data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:19: Cannot find include file: ccx2mb.h\n`include "ccx2mb.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.sv\n             ccx2mb.h\n             ccx2mb.h.v\n             ccx2mb.h.sv\n             obj_dir/ccx2mb.h\n             obj_dir/ccx2mb.h.v\n             obj_dir/ccx2mb.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:55: Define or directive not defined: \'`PCX_WIDTH\'\n    output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:63: Define or directive not defined: \'`PCX_WIDTH\'\n    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:71: Define or directive not defined: \'`PCX_WIDTH\'\n    input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:78: Define or directive not defined: \'`PCX_WIDTH\'\n    reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb_entry.v:88: Define or directive not defined: \'`PCX_WIDTH\'\n     e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1\'b0}};\n                ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module pcx2mb_entry (

	e_data,
	e_active,
	e_dest,


	rclk,
	reset_l,

	any_req_pa,
	spc_pcx_data_pa,
	req_dest_pa,
	req_atom_pa,
	any_req_px,
	req_dest_px,
	req_atom_px,
	load_data,

	prev_data,
	prev_active,
	prev_dest,

	next_active
	);

`ifdef PCX2MB_5_BIT_REQ
    parameter PCX_REQ_WIDTH = 5;
`else
    parameter PCX_REQ_WIDTH = 2;
`endif


    output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
    output       e_active;
    output [4:0] e_dest;

    input rclk;
    input reset_l;

    input                  any_req_pa;
    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input [4:0]            req_dest_pa;
    input                  req_atom_pa;
    input                  any_req_px;
    input [4:0]            req_dest_px;
    input                  req_atom_px;
    input                  load_data;

    input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;
    input       prev_active;
    input [4:0] prev_dest;

    input       next_active;


    reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
    reg       e_active;
    reg [4:0] e_dest;





    always @(posedge rclk) begin
	if (!reset_l) begin
	    e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}};
	    e_active <= 1'b0;
	    e_dest <= 5'b00000;
	end
	else if (load_data && prev_active) begin
	    e_data <= prev_data;
	    e_active <= prev_active;
	    e_dest <= prev_dest;
	end
	else if (any_req_pa && (
		    (next_active && !load_data && !e_active) ||
		    (next_active && load_data && e_active && !prev_active)))
	begin
`ifdef PCX2MB_5_BIT_REQ
	    e_data <= { req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
	    e_data <= { req_dest_pa[4], (|req_dest_pa[3:0]), req_atom_pa,
		    	spc_pcx_data_pa};
`endif
	    e_active <= 1'b1;
	    e_dest <= req_dest_pa;
	end
	else if (any_req_px && req_atom_px && (
		    (next_active && !load_data && !e_active) ||
		    (next_active && load_data && e_active && !prev_active)))
	begin
`ifdef PCX2MB_5_BIT_REQ
	    e_data <= { req_dest_px[4:0], req_atom_px, spc_pcx_data_pa};
`else
	    e_data <= { req_dest_px[4], (|req_dest_px[3:0]), 1'b0,
			spc_pcx_data_pa};
`endif
	    e_active <= 1'b1;
	    e_dest <= req_dest_px;
	end
	else begin
	    e_data <= e_data;
	    e_dest <= e_dest;
	    
	    if (load_data && e_active) begin
		e_active <= 1'b0;
	    end
	    else begin
		e_active <= e_active;
	    end
	end
    end

endmodule
module pcx2mb_entry (

	e_data,
	e_active,
	e_dest,


	rclk,
	reset_l,

	any_req_pa,
	spc_pcx_data_pa,
	req_dest_pa,
	req_atom_pa,
	any_req_px,
	req_dest_px,
	req_atom_px,
	load_data,

	prev_data,
	prev_active,
	prev_dest,

	next_active
	);


`ifdef PCX2MB_5_BIT_REQ
    parameter PCX_REQ_WIDTH = 5;
`else
    parameter PCX_REQ_WIDTH = 2;
`endif


    output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
    output       e_active;
    output [4:0] e_dest;

    input rclk;
    input reset_l;

    input                  any_req_pa;
    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input [4:0]            req_dest_pa;
    input                  req_atom_pa;
    input                  any_req_px;
    input [4:0]            req_dest_px;
    input                  req_atom_px;
    input                  load_data;

    input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;
    input       prev_active;
    input [4:0] prev_dest;

    input       next_active;


    reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
    reg       e_active;
    reg [4:0] e_dest;





    always @(posedge rclk) begin
	if (!reset_l) begin
	    e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}};
	    e_active <= 1'b0;
	    e_dest <= 5'b00000;
	end
	else if (load_data && prev_active) begin
	    e_data <= prev_data;
	    e_active <= prev_active;
	    e_dest <= prev_dest;
	end
	else if (any_req_pa && (
		    (next_active && !load_data && !e_active) ||
		    (next_active && load_data && e_active && !prev_active)))
	begin
`ifdef PCX2MB_5_BIT_REQ
	    e_data <= { req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
	    e_data <= { req_dest_pa[4], (|req_dest_pa[3:0]), req_atom_pa,
		    	spc_pcx_data_pa};
`endif
	    e_active <= 1'b1;
	    e_dest <= req_dest_pa;
	end
	else if (any_req_px && req_atom_px && (
		    (next_active && !load_data && !e_active) ||
		    (next_active && load_data && e_active && !prev_active)))
	begin
`ifdef PCX2MB_5_BIT_REQ
	    e_data <= { req_dest_px[4:0], req_atom_px, spc_pcx_data_pa};
`else
	    e_data <= { req_dest_px[4], (|req_dest_px[3:0]), 1'b0,
			spc_pcx_data_pa};
`endif
	    e_active <= 1'b1;
	    e_dest <= req_dest_px;
	end
	else begin
	    e_data <= e_data;
	    e_dest <= e_dest;
	    
	    if (load_data && e_active) begin
		e_active <= 1'b0;
	    end
	    else begin
		e_active <= e_active;
	    end
	end
    end

endmodule