data/full_repos/permissive/480681467/main/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:25: Operator ASSIGN expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                   : ... In instance control.i.x_mod_y\n           p = {p[WIDTH-2:0],A[WIDTH-1]};\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:38: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 65 bits.\n                                                                   : ... In instance control.i.x_mod_y\n   assign R = p,Q = A;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'p\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'q\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:119: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_reg\' generates 32 bits.\n                                                                    : ... In instance control.i\n    assign e = e_reg;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:151: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_plus3\' generates 32 bits.\n                                                                    : ... In instance control.i\n                         b <= e_plus3;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:77: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                   : ... In instance control.m\n            result_reg <= 32\'d1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:190: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'msg_in\' generates 32 bits.\n                                                                    : ... In instance control\n         msg_reg <= msg_in;\n                 ^~\n%Error: Exiting due to 8 warning(s)\n'
module control(
    input [WIDTH-1:0] p,q,
    input clk,
    input reset,
    input reset1,
    input encrypt_decrypt,
    input [WIDTH-1:0] msg_in,
  output [WIDTH*2-1:0] msg_out,
    output mod_exp_finish
    );
    
    parameter WIDTH = 32;
    
    wire inverter_finish;
    wire [WIDTH*2-1:0] e,d;
    wire [WIDTH*2-1:0] exponent = encrypt_decrypt?e:d;
    wire [WIDTH*2-1:0] modulo = p*q;
    wire mod_exp_reset  = 1'b0;
    
    reg [WIDTH*2-1:0] exp_reg,msg_reg;
    reg [WIDTH*2-1:0] mod_reg;
    
    always @(posedge clk)begin
         exp_reg <= exponent;
         mod_reg <= modulo;
         msg_reg <= msg_in;
    end
    
    inverter i(p,q,clk,reset,inverter_finish,e,d);
    defparam i.WIDTH = WIDTH;
    mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out);
    defparam m.WIDTH = WIDTH;
    
endmodule
module control(
    input [WIDTH-1:0] p,q,
    input clk,
    input reset,
    input reset1,
    input encrypt_decrypt,
    input [WIDTH-1:0] msg_in,
  output [WIDTH*2-1:0] msg_out,
    output mod_exp_finish
    );

    
    parameter WIDTH = 32;
    
    wire inverter_finish;
    wire [WIDTH*2-1:0] e,d;
    wire [WIDTH*2-1:0] exponent = encrypt_decrypt?e:d;
    wire [WIDTH*2-1:0] modulo = p*q;
    wire mod_exp_reset  = 1'b0;
    
    reg [WIDTH*2-1:0] exp_reg,msg_reg;
    reg [WIDTH*2-1:0] mod_reg;
    
    always @(posedge clk)begin
         exp_reg <= exponent;
         mod_reg <= modulo;
         msg_reg <= msg_in;
    end
    
    inverter i(p,q,clk,reset,inverter_finish,e,d);
    defparam i.WIDTH = WIDTH;
    mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out);
    defparam m.WIDTH = WIDTH;
    
endmodule