data/full_repos/permissive/434840709/lab6/6.1/add32_2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:16: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                          : ... In instance add32_2\n  {firstc,firsts} = ina[15:0]+inb[15:0]+cin;\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:17: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 17 bits.\n                                                                          : ... In instance add32_2\n  tempa = ina[31:15];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:18: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 17 bits.\n                                                                          : ... In instance add32_2\n  tempb = inb[31:15];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:22: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'tempa\' generates 16 bits.\n                                                                          : ... In instance add32_2\n  {cout, sum[31:15]} = tempa+tempb+firstc;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:22: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'tempb\' generates 16 bits.\n                                                                          : ... In instance add32_2\n  {cout, sum[31:15]} = tempa+tempb+firstc;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab6/6.1/add32_2.v:22: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'firstc\' generates 1 bits.\n                                                                          : ... In instance add32_2\n  {cout, sum[31:15]} = tempa+tempb+firstc;\n                                  ^\n%Error: Exiting due to 6 warning(s)\n'
module add32_2(
	input[31:0] ina,
	input[31:0] inb,
	input clk,
	input cin,
	output reg cout,
	output reg [31:0] sum
);

	reg [15:0] tempa,tempb,firsts;
	reg firstc;

	always@(posedge clk)begin
		{firstc,firsts} = ina[15:0]+inb[15:0]+cin;
		tempa = ina[31:15];
		tempb = inb[31:15];
	end

	always@(posedge clk)begin
		{cout, sum[31:15]} = tempa+tempb+firstc;
		sum[15:0] = firsts;
	end
	
endmodule
module add32_2(
	input[31:0] ina,
	input[31:0] inb,
	input clk,
	input cin,
	output reg cout,
	output reg [31:0] sum
);


	reg [15:0] tempa,tempb,firsts;
	reg firstc;

	always@(posedge clk)begin
		{firstc,firsts} = ina[15:0]+inb[15:0]+cin;
		tempa = ina[31:15];
		tempb = inb[31:15];
	end

	always@(posedge clk)begin
		{cout, sum[31:15]} = tempa+tempb+firstc;
		sum[15:0] = firsts;
	end
	
endmodule