data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v:15: Cannot find file containing module: 'SRA_EN'\n SRA_EN sra_en(EN_SRA,ctrl_ALUopcode);  \n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/SRA_EN\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/SRA_EN.v\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/SRA_EN.sv\n             SRA_EN\n             SRA_EN.v\n             SRA_EN.sv\n             obj_dir/SRA_EN\n             obj_dir/SRA_EN.v\n             obj_dir/SRA_EN.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v:16: Cannot find file containing module: 'SLL_EN'\n SLL_EN sll_en(EN_SLL,ctrl_ALUopcode);  \n ^~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v:19: Cannot find file containing module: 'SRA_32'\n SRA_32 sra(temp_out_SRA, data_in, shift_ctrl);\n ^~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v:20: Cannot find file containing module: 'SLL_32'\n SLL_32 sll(data_in, temp_out_SLL, shift_ctrl);\n ^~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/shifter.v:28: Cannot find file containing module: 'logic_or'\n logic_or out(data_out_SRA, data_out_SLL, data_out);\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module shifter(data_out, data_in, shift_ctrl, ctrl_ALUopcode);
	
	input [31:0] data_in; 
	input [4:0] shift_ctrl, ctrl_ALUopcode;
	output [31:0] data_out;
	

	
	wire EN_SRA, EN_SLL;
	SRA_EN sra_en(EN_SRA,ctrl_ALUopcode);
	SLL_EN sll_en(EN_SLL,ctrl_ALUopcode);
	
	wire [31:0] temp_out_SRA, temp_out_SLL;
	SRA_32 sra(temp_out_SRA, data_in, shift_ctrl);
	SLL_32 sll(data_in, temp_out_SLL, shift_ctrl);
	

	wire [31:0] data_out_SRA, data_out_SLL;
	
	assign data_out_SRA = EN_SRA ? temp_out_SRA : 0;
	assign data_out_SLL = EN_SLL ? temp_out_SLL : 0;
	
	logic_or out(data_out_SRA, data_out_SLL, data_out);
	
endmodule
module shifter(data_out, data_in, shift_ctrl, ctrl_ALUopcode);

	
	input [31:0] data_in; 
	input [4:0] shift_ctrl, ctrl_ALUopcode;
	output [31:0] data_out;
	

	
	wire EN_SRA, EN_SLL;
	SRA_EN sra_en(EN_SRA,ctrl_ALUopcode);
	SLL_EN sll_en(EN_SLL,ctrl_ALUopcode);
	
	wire [31:0] temp_out_SRA, temp_out_SLL;
	SRA_32 sra(temp_out_SRA, data_in, shift_ctrl);
	SLL_32 sll(data_in, temp_out_SLL, shift_ctrl);
	

	wire [31:0] data_out_SRA, data_out_SLL;
	
	assign data_out_SRA = EN_SRA ? temp_out_SRA : 0;
	assign data_out_SLL = EN_SLL ? temp_out_SLL : 0;
	
	logic_or out(data_out_SRA, data_out_SLL, data_out);
	
endmodule