data/full_repos/permissive/493019833/test/testcase/firrtl/AdderTests/sbt/AdderTests.v
data/verilator_xmls/d46448cb-3bc1-404b-a965-ec6988a76370.xml
module AdderTests(
  input   clock,
  input   reset
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire [9:0] c_io_in0;
  wire [9:0] c_io_in1;
  wire [9:0] c_io_out;
  reg [3:0] value;
  reg  _T_6;
  wire  _T_8 = ~_T_6;
  wire [9:0] _GEN_1 = 4'h1 == value ? 10'h26c : 10'h353;
  wire [9:0] _GEN_2 = 4'h2 == value ? 10'h13c : _GEN_1;
  wire [9:0] _GEN_3 = 4'h3 == value ? 10'h77 : _GEN_2;
  wire [9:0] _GEN_4 = 4'h4 == value ? 10'h320 : _GEN_3;
  wire [9:0] _GEN_5 = 4'h5 == value ? 10'h102 : _GEN_4;
  wire [9:0] _GEN_6 = 4'h6 == value ? 10'h273 : _GEN_5;
  wire [9:0] _GEN_7 = 4'h7 == value ? 10'h3ee : _GEN_6;
  wire [9:0] _GEN_8 = 4'h8 == value ? 10'h17 : _GEN_7;
  wire [9:0] _GEN_9 = 4'h9 == value ? 10'hb4 : _GEN_8;
  wire [9:0] _GEN_12 = 4'h1 == value ? 10'hf6 : 10'h2ec;
  wire [9:0] _GEN_13 = 4'h2 == value ? 10'h28c : _GEN_12;
  wire [9:0] _GEN_14 = 4'h3 == value ? 10'h233 : _GEN_13;
  wire [9:0] _GEN_15 = 4'h4 == value ? 10'h263 : _GEN_14;
  wire [9:0] _GEN_16 = 4'h5 == value ? 10'h155 : _GEN_15;
  wire [9:0] _GEN_17 = 4'h6 == value ? 10'h18a : _GEN_16;
  wire [9:0] _GEN_18 = 4'h7 == value ? 10'h3f0 : _GEN_17;
  wire [9:0] _GEN_19 = 4'h8 == value ? 10'h384 : _GEN_18;
  wire [9:0] _GEN_20 = 4'h9 == value ? 10'h3c3 : _GEN_19;
  wire  _GEN_32 = 4'ha == value ? 1'h0 : 1'h1;
  wire [9:0] _GEN_34 = 4'h1 == value ? 10'h362 : 10'h23f;
  wire [9:0] _GEN_35 = 4'h2 == value ? 10'h3c8 : _GEN_34;
  wire [9:0] _GEN_36 = 4'h3 == value ? 10'h2aa : _GEN_35;
  wire [9:0] _GEN_37 = 4'h4 == value ? 10'h183 : _GEN_36;
  wire [9:0] _GEN_38 = 4'h5 == value ? 10'h257 : _GEN_37;
  wire [9:0] _GEN_39 = 4'h6 == value ? 10'h3fd : _GEN_38;
  wire [9:0] _GEN_40 = 4'h7 == value ? 10'h3de : _GEN_39;
  wire [9:0] _GEN_41 = 4'h8 == value ? 10'h39b : _GEN_40;
  wire [9:0] _GEN_42 = 4'h9 == value ? 10'h77 : _GEN_41;
  wire [9:0] _GEN_43 = 4'ha == value ? 10'h0 : _GEN_42;
  wire  _T_154 = c_io_out == _GEN_43;
  wire  _T_156 = ~reset;
  wire  _T_158 = ~(c_io_out == _GEN_43);
  wire  _T_169 = value == 4'ha;
  wire [3:0] _T_172 = value + 4'h1;
  wire  _GEN_45 = _T_169 | _T_6;
  wire  _GEN_50 = _T_8 & _GEN_32;
  wire  _GEN_53 = _GEN_50 & _T_158;
  wire  _GEN_60 = _T_8 & _T_169;
  Adder c (
    .io_in0(c_io_in0),
    .io_in1(c_io_in1),
    .io_out(c_io_out)
  );
  assign c_io_in0 = 4'ha == value ? 10'h3c3 : _GEN_20;
  assign c_io_in1 = 4'ha == value ? 10'hb4 : _GEN_9;
  always @(posedge clock) begin
    if (reset) begin
      value <= 4'h0;
    end else if (~_T_6) begin
      if (_T_169) begin
        value <= 4'h0;
      end else begin
        value <= _T_172;
      end
    end
    if (reset) begin
      _T_6 <= 1'h0;
    end else if (~_T_6) begin
      _T_6 <= _GEN_45;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & _GEN_32 & _T_154 & ~reset) begin
          $fwrite(32'h80000002,"    passed step %d -- out:  %d\n",value,c_io_out);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_50 & _T_158 & _T_156) begin
          $fwrite(32'h80000002,"    failed on step %d -- port out:  %d expected %d\n",value,c_io_out,_GEN_43);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $fwrite(32'h80000002,"Assertion failed\n    at SteppedHWIOTester.scala:158 assert(false.B)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & _T_169 & _T_156) begin
          $fwrite(32'h80000002,"Stopping, end of tests, 11 steps\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_60 & _T_156) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  value = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  _T_6 = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AdderTests(
  input   clock,
  input   reset
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire [9:0] c_io_in0;
  wire [9:0] c_io_in1;
  wire [9:0] c_io_out;
  reg [3:0] value;
  reg  _T_6;
  wire  _T_8 = ~_T_6;
  wire [9:0] _GEN_1 = 4'h1 == value ? 10'h26c : 10'h353;
  wire [9:0] _GEN_2 = 4'h2 == value ? 10'h13c : _GEN_1;
  wire [9:0] _GEN_3 = 4'h3 == value ? 10'h77 : _GEN_2;
  wire [9:0] _GEN_4 = 4'h4 == value ? 10'h320 : _GEN_3;
  wire [9:0] _GEN_5 = 4'h5 == value ? 10'h102 : _GEN_4;
  wire [9:0] _GEN_6 = 4'h6 == value ? 10'h273 : _GEN_5;
  wire [9:0] _GEN_7 = 4'h7 == value ? 10'h3ee : _GEN_6;
  wire [9:0] _GEN_8 = 4'h8 == value ? 10'h17 : _GEN_7;
  wire [9:0] _GEN_9 = 4'h9 == value ? 10'hb4 : _GEN_8;
  wire [9:0] _GEN_12 = 4'h1 == value ? 10'hf6 : 10'h2ec;
  wire [9:0] _GEN_13 = 4'h2 == value ? 10'h28c : _GEN_12;
  wire [9:0] _GEN_14 = 4'h3 == value ? 10'h233 : _GEN_13;
  wire [9:0] _GEN_15 = 4'h4 == value ? 10'h263 : _GEN_14;
  wire [9:0] _GEN_16 = 4'h5 == value ? 10'h155 : _GEN_15;
  wire [9:0] _GEN_17 = 4'h6 == value ? 10'h18a : _GEN_16;
  wire [9:0] _GEN_18 = 4'h7 == value ? 10'h3f0 : _GEN_17;
  wire [9:0] _GEN_19 = 4'h8 == value ? 10'h384 : _GEN_18;
  wire [9:0] _GEN_20 = 4'h9 == value ? 10'h3c3 : _GEN_19;
  wire  _GEN_32 = 4'ha == value ? 1'h0 : 1'h1;
  wire [9:0] _GEN_34 = 4'h1 == value ? 10'h362 : 10'h23f;
  wire [9:0] _GEN_35 = 4'h2 == value ? 10'h3c8 : _GEN_34;
  wire [9:0] _GEN_36 = 4'h3 == value ? 10'h2aa : _GEN_35;
  wire [9:0] _GEN_37 = 4'h4 == value ? 10'h183 : _GEN_36;
  wire [9:0] _GEN_38 = 4'h5 == value ? 10'h257 : _GEN_37;
  wire [9:0] _GEN_39 = 4'h6 == value ? 10'h3fd : _GEN_38;
  wire [9:0] _GEN_40 = 4'h7 == value ? 10'h3de : _GEN_39;
  wire [9:0] _GEN_41 = 4'h8 == value ? 10'h39b : _GEN_40;
  wire [9:0] _GEN_42 = 4'h9 == value ? 10'h77 : _GEN_41;
  wire [9:0] _GEN_43 = 4'ha == value ? 10'h0 : _GEN_42;
  wire  _T_154 = c_io_out == _GEN_43;
  wire  _T_156 = ~reset;
  wire  _T_158 = ~(c_io_out == _GEN_43);
  wire  _T_169 = value == 4'ha;
  wire [3:0] _T_172 = value + 4'h1;
  wire  _GEN_45 = _T_169 | _T_6;
  wire  _GEN_50 = _T_8 & _GEN_32;
  wire  _GEN_53 = _GEN_50 & _T_158;
  wire  _GEN_60 = _T_8 & _T_169;
  Adder c (
    .io_in0(c_io_in0),
    .io_in1(c_io_in1),
    .io_out(c_io_out)
  );
  assign c_io_in0 = 4'ha == value ? 10'h3c3 : _GEN_20;
  assign c_io_in1 = 4'ha == value ? 10'hb4 : _GEN_9;
  always @(posedge clock) begin
    if (reset) begin
      value <= 4'h0;
    end else if (~_T_6) begin
      if (_T_169) begin
        value <= 4'h0;
      end else begin
        value <= _T_172;
      end
    end
    if (reset) begin
      _T_6 <= 1'h0;
    end else if (~_T_6) begin
      _T_6 <= _GEN_45;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & _GEN_32 & _T_154 & ~reset) begin
          $fwrite(32'h80000002,"    passed step %d -- out:  %d\n",value,c_io_out);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_50 & _T_158 & _T_156) begin
          $fwrite(32'h80000002,"    failed on step %d -- port out:  %d expected %d\n",value,c_io_out,_GEN_43);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $fwrite(32'h80000002,"Assertion failed\n    at SteppedHWIOTester.scala:158 assert(false.B)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_53 & _T_156) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & _T_169 & _T_156) begin
          $fwrite(32'h80000002,"Stopping, end of tests, 11 steps\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_60 & _T_156) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  value = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  _T_6 = _RAND_1[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule