data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/Wire_decl.v
data/verilator_xmls/461b3846-4c75-4a36-aa49-f3da50ae89c2.xml
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 

    wire aAndB;
    wire cAndD;

    assign aAndB = a & b;
    assign cAndD = c & d;
    assign out = aAndB | cAndD;
    assign out_n = ~out;
endmodule
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );
 

    wire aAndB;
    wire cAndD;

    assign aAndB = a & b;
    assign cAndD = c & d;
    assign out = aAndB | cAndD;
    assign out_n = ~out;
endmodule