data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_exu_mul.v
1: b'%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_exu_mul.v:12: Cannot find include file: pa_chip_param.v\n`include "pa_chip_param.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.sv\n             pa_chip_param.v\n             pa_chip_param.v.v\n             pa_chip_param.v.sv\n             obj_dir/pa_chip_param.v\n             obj_dir/pa_chip_param.v.v\n             obj_dir/pa_chip_param.v.sv\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_exu_mul.v:15: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   data1_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_exu_mul.v:16: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   data2_i,\n                 ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module pa_core_exu_mul (
    input  wire [`DATA_BUS_WIDTH-1:0]   data1_i,
    input  wire [`DATA_BUS_WIDTH-1:0]   data2_i,

    input  wire                         sign_i,

    output wire [63:0]                  data_o
);

wire [47:0]                             iresult_final_high;
wire [47:0]                             iresult_final_low;



assign iresult_final_high[47:0] = data1_i[31:0] * {16'b0, data2_i[31:16]};
assign iresult_final_low [47:0] = data1_i[31:0] * {16'b0, data2_i[15: 0]};

wire [63:0]                             iresult_final;

assign iresult_final[63:0] = {iresult_final_high[47:0], 16'b0}
                           + {16'b0,  iresult_final_low[47:0]};

assign data_o[63:0] = sign_i ? (~iresult_final[63:0] + 63'b1)
                             : ( iresult_final[63:0]);

endmodule
module pa_core_exu_mul (
    input  wire [`DATA_BUS_WIDTH-1:0]   data1_i,
    input  wire [`DATA_BUS_WIDTH-1:0]   data2_i,

    input  wire                         sign_i,

    output wire [63:0]                  data_o
);


wire [47:0]                             iresult_final_high;
wire [47:0]                             iresult_final_low;



assign iresult_final_high[47:0] = data1_i[31:0] * {16'b0, data2_i[31:16]};
assign iresult_final_low [47:0] = data1_i[31:0] * {16'b0, data2_i[15: 0]};

wire [63:0]                             iresult_final;

assign iresult_final[63:0] = {iresult_final_high[47:0], 16'b0}
                           + {16'b0,  iresult_final_low[47:0]};

assign data_o[63:0] = sign_i ? (~iresult_final[63:0] + 63'b1)
                             : ( iresult_final[63:0]);

endmodule