data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More Verilog Features/Conditional ternary operator.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More\n%Error: Cannot find file containing module: Features/Conditional\n%Error: Cannot find file containing module: ternary\n%Error: Cannot find file containing module: operator.v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);


    reg [7:0] mid_min_1, mid_min_2;
    assign mid_min_1 = (a < b) ? a : b;
    assign mid_min_2 = (c < d) ? c : d;

    assign min = (mid_min_1 < mid_min_2) ? mid_min_1 : mid_min_2;

endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);



    reg [7:0] mid_min_1, mid_min_2;
    assign mid_min_1 = (a < b) ? a : b;
    assign mid_min_2 = (c < d) ? c : d;

    assign min = (mid_min_1 < mid_min_2) ? mid_min_1 : mid_min_2;

endmodule