data/full_repos/permissive/423667690/src/top_module.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/423667690/src/top_module.v:47: Signal definition not found, creating implicitly: \'key1_tick\'\n   threshold=key1_tick? threshold+1:threshold;   \n             ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/423667690/src/top_module.v:48: Signal definition not found, creating implicitly: \'key2_tick\'\n                                                                           : ... Suggested alternative: \'key1_tick\'\n   threshold=key2_tick? threshold-1:threshold;  \n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/423667690/src/top_module.v:49: Signal definition not found, creating implicitly: \'key3_tick\'\n                                                                           : ... Suggested alternative: \'key1_tick\'\n   sobel<=key3_tick? !sobel:sobel;  \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:55: Cannot find file containing module: \'camera_interface\'\n camera_interface m0  \n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/camera_interface\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/camera_interface.v\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/camera_interface.sv\n             camera_interface\n             camera_interface.v\n             camera_interface.sv\n             obj_dir/camera_interface\n             obj_dir/camera_interface.v\n             obj_dir/camera_interface.sv\n%Error: data/full_repos/permissive/423667690/src/top_module.v:83: Cannot find file containing module: \'sdram_interface\'\n  sdram_interface m1  \n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:114: Cannot find file containing module: \'vga_interface\'\n  vga_interface m2  \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:130: Cannot find file containing module: \'sobel_convolution\'\n sobel_convolution m3 \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:145: Cannot find file containing module: \'pll_SDRAM\'\n pll_SDRAM m4\n ^~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:151: Cannot find file containing module: \'debounce_explicit\'\n  debounce_explicit m5\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:160: Cannot find file containing module: \'debounce_explicit\'\n  debounce_explicit m6\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/top_module.v:169: Cannot find file containing module: \'debounce_explicit\'\n  debounce_explicit m7\n  ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module top_module(
	input wire clk,rst_n,
	input wire[3:0] key,

	input wire cmos_pclk,cmos_href,cmos_vsync,
	input wire[7:0] cmos_db,
	inout cmos_sda,cmos_scl, 
	output wire cmos_rst_n, cmos_pwdn, cmos_xclk,

	output[7:0] led, 

	output wire sdram_clk,
	output wire sdram_cke, 
	output wire sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n, 
	output wire[12:0] sdram_addr,
	output wire[1:0] sdram_ba, 
	output wire[1:0] sdram_dqm, 
	inout[15:0] sdram_dq,

	output [3:0] gpdi_dp
    );
	 
	 wire f2s_data_valid;
	 wire[10:0] data_count_r,data_count_r_sobel;
	 wire[16:0] dout,din;
	 wire clk_sdram;
	 wire empty_fifo,empty;
	 wire clk_vga,clk_sobel;
	 wire state;
	 wire rd_sobel;
	 wire rd_en,rd_fifo;
	 wire[8:0] sobel_data;
	 wire[9:0] data_count_sobel;
	 wire rd_en_sobel;
	 wire[16:0] dout_sobel;
	 reg[7:0] threshold=0;
	 reg sobel=0;

	always @(posedge clk) begin
		if(!rst_n) begin
			threshold=0;
			sobel<=0;
		end
		else begin
			threshold=key1_tick? threshold+1:threshold;
			threshold=key2_tick? threshold-1:threshold;
			sobel<=key3_tick? !sobel:sobel;
		end
	end
	
	

	camera_interface m0
	(
		.clk(clk),
		.clk_100(clk_sdram),
		.rst_n(rst_n),
		.key(),

		.rd_en_sobel(rd_en_sobel),
		.dout_sobel(dout_sobel),
		.data_count_r_sobel(data_count_r_sobel),

		.rd_en(rd_fifo),
		.data_count_r(data_count_r),
		.dout(dout),

		.cmos_pclk(cmos_pclk),
		.cmos_href(cmos_href),
		.cmos_vsync(cmos_vsync),
		.cmos_db(cmos_db),
		.cmos_sda(cmos_sda),
		.cmos_scl(cmos_scl), 
		.cmos_rst_n(cmos_rst_n),
		.cmos_pwdn(cmos_pwdn),
		.cmos_xclk(cmos_xclk),

		.led(led)
    );
	 
	 sdram_interface m1
	 (
		.clk(clk_sdram),
		.rst_n(rst_n),
		.clk_vga(clk_vga),
		.rd_en(rd_en),
		.sobel(sobel),

		.data_count_camera_fifo(data_count_r),
		.din(dout),
		.rd_camera(rd_fifo),

		.sobel_data(sobel_data),
		.data_count_r(data_count_sobel),
		.rd_sobel(rd_sobel),

		.empty_fifo(empty_fifo),
		.dout(din),

		.sdram_clk(sdram_clk),
		.sdram_cke(sdram_cke), 
		.sdram_cs_n(sdram_cs_n),
		.sdram_ras_n(sdram_ras_n),
		.sdram_cas_n(sdram_cas_n),
		.sdram_we_n(sdram_we_n), 
		.sdram_addr(sdram_addr),
		.sdram_ba(sdram_ba), 
		.sdram_dqm(sdram_dqm),
		.sdram_dq(sdram_dq)
    );
	 
	 vga_interface m2
	 (
		.clk(clk),
		.rst_n(rst_n),
		.sobel(sobel),
		.align_tick(key[3]),

		.empty_fifo(empty_fifo),
		.din(din),
		.clk_vga(clk_vga),
		.rd_en(rd_en),
		.threshold(threshold),

		.gpdi_dp(gpdi_dp)
    );
	
	sobel_convolution m3 
	 (	
		.clk_w(clk),
		.clk_r(clk_sdram),
		.rst_n(rst_n),
		.din(dout_sobel),
		.data_count_r_sobel(data_count_r_sobel),
		.rd_fifo(rd_sobel), 
		.rd_fifo_cam(rd_en_sobel),
		.dout(sobel_data),
		.data_count_r(data_count_sobel)
    );
	 
	

	pll_SDRAM m4
   (
    .clkin(clk),
    .clkout0(clk_sdram)
	);      
	
	 debounce_explicit m5
	(
		.clk(clk),
		.rst_n(rst_n),
		.sw({key[0]}),
		.db_level(),
		.db_tick(key1_tick)
    );
	 
	 debounce_explicit m6
	(
		.clk(clk),
		.rst_n(rst_n),
		.sw({key[1]}),
		.db_level(),
		.db_tick(key2_tick)
    );
	 
	 debounce_explicit m7
	(
		.clk(clk), 
		.rst_n(rst_n),
		.sw({key[2]}),
		.db_level(),
		.db_tick(key3_tick)
    );
	
	   
	

	 
	 

endmodule
module top_module(
	input wire clk,rst_n,
	input wire[3:0] key,

	input wire cmos_pclk,cmos_href,cmos_vsync,
	input wire[7:0] cmos_db,
	inout cmos_sda,cmos_scl, 
	output wire cmos_rst_n, cmos_pwdn, cmos_xclk,

	output[7:0] led, 

	output wire sdram_clk,
	output wire sdram_cke, 
	output wire sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n, 
	output wire[12:0] sdram_addr,
	output wire[1:0] sdram_ba, 
	output wire[1:0] sdram_dqm, 
	inout[15:0] sdram_dq,

	output [3:0] gpdi_dp
    );

	 
	 wire f2s_data_valid;
	 wire[10:0] data_count_r,data_count_r_sobel;
	 wire[16:0] dout,din;
	 wire clk_sdram;
	 wire empty_fifo,empty;
	 wire clk_vga,clk_sobel;
	 wire state;
	 wire rd_sobel;
	 wire rd_en,rd_fifo;
	 wire[8:0] sobel_data;
	 wire[9:0] data_count_sobel;
	 wire rd_en_sobel;
	 wire[16:0] dout_sobel;
	 reg[7:0] threshold=0;
	 reg sobel=0;

	always @(posedge clk) begin
		if(!rst_n) begin
			threshold=0;
			sobel<=0;
		end
		else begin
			threshold=key1_tick? threshold+1:threshold;
			threshold=key2_tick? threshold-1:threshold;
			sobel<=key3_tick? !sobel:sobel;
		end
	end
	
	

	camera_interface m0
	(
		.clk(clk),
		.clk_100(clk_sdram),
		.rst_n(rst_n),
		.key(),

		.rd_en_sobel(rd_en_sobel),
		.dout_sobel(dout_sobel),
		.data_count_r_sobel(data_count_r_sobel),

		.rd_en(rd_fifo),
		.data_count_r(data_count_r),
		.dout(dout),

		.cmos_pclk(cmos_pclk),
		.cmos_href(cmos_href),
		.cmos_vsync(cmos_vsync),
		.cmos_db(cmos_db),
		.cmos_sda(cmos_sda),
		.cmos_scl(cmos_scl), 
		.cmos_rst_n(cmos_rst_n),
		.cmos_pwdn(cmos_pwdn),
		.cmos_xclk(cmos_xclk),

		.led(led)
    );
	 
	 sdram_interface m1
	 (
		.clk(clk_sdram),
		.rst_n(rst_n),
		.clk_vga(clk_vga),
		.rd_en(rd_en),
		.sobel(sobel),

		.data_count_camera_fifo(data_count_r),
		.din(dout),
		.rd_camera(rd_fifo),

		.sobel_data(sobel_data),
		.data_count_r(data_count_sobel),
		.rd_sobel(rd_sobel),

		.empty_fifo(empty_fifo),
		.dout(din),

		.sdram_clk(sdram_clk),
		.sdram_cke(sdram_cke), 
		.sdram_cs_n(sdram_cs_n),
		.sdram_ras_n(sdram_ras_n),
		.sdram_cas_n(sdram_cas_n),
		.sdram_we_n(sdram_we_n), 
		.sdram_addr(sdram_addr),
		.sdram_ba(sdram_ba), 
		.sdram_dqm(sdram_dqm),
		.sdram_dq(sdram_dq)
    );
	 
	 vga_interface m2
	 (
		.clk(clk),
		.rst_n(rst_n),
		.sobel(sobel),
		.align_tick(key[3]),

		.empty_fifo(empty_fifo),
		.din(din),
		.clk_vga(clk_vga),
		.rd_en(rd_en),
		.threshold(threshold),

		.gpdi_dp(gpdi_dp)
    );
	
	sobel_convolution m3 
	 (	
		.clk_w(clk),
		.clk_r(clk_sdram),
		.rst_n(rst_n),
		.din(dout_sobel),
		.data_count_r_sobel(data_count_r_sobel),
		.rd_fifo(rd_sobel), 
		.rd_fifo_cam(rd_en_sobel),
		.dout(sobel_data),
		.data_count_r(data_count_sobel)
    );
	 
	

	pll_SDRAM m4
   (
    .clkin(clk),
    .clkout0(clk_sdram)
	);      
	
	 debounce_explicit m5
	(
		.clk(clk),
		.rst_n(rst_n),
		.sw({key[0]}),
		.db_level(),
		.db_tick(key1_tick)
    );
	 
	 debounce_explicit m6
	(
		.clk(clk),
		.rst_n(rst_n),
		.sw({key[1]}),
		.db_level(),
		.db_tick(key2_tick)
    );
	 
	 debounce_explicit m7
	(
		.clk(clk), 
		.rst_n(rst_n),
		.sw({key[2]}),
		.db_level(),
		.db_tick(key3_tick)
    );
	
	   
	

	 
	 

endmodule