data/full_repos/permissive/46343463/src/ROM.v
data/verilator_xmls/4eb444a3-b1e8-414d-9560-1c6e70ec4b82.xml
module ROM
#(
	parameter addr_width 	= 32,
	parameter data_width	= 32,
	parameter mem_size 		= 1024
)
(
	input							clk,
	input		[addr_width-1:0]	addr_i,
	input							cs,		
	input							we,
	output		[data_width-1:0]	data_o
);

	integer i;

	reg	[data_width-1:0]	memory	[0:mem_size-1];
	
	assign data_o = memory[addr_i >> 2];

endmodule
module ROM
#(
	parameter addr_width 	= 32,
	parameter data_width	= 32,
	parameter mem_size 		= 1024
)
(
	input							clk,
	input		[addr_width-1:0]	addr_i,
	input							cs,		
	input							we,
	output		[data_width-1:0]	data_o
);


	integer i;

	reg	[data_width-1:0]	memory	[0:mem_size-1];
	
	assign data_o = memory[addr_i >> 2];

endmodule