data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/oneHz_generator.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: breadboard),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: breadboard)/oneHz_generator.v\n%Error: Exiting due to 9 error(s)\n'
module oneHz_generator(
    input clk_in,
    output clk_out
    );
    
    reg [25:0] clk_counter = 0;
    reg clk_1Hz = 0;
    
    always @(posedge clk_in) begin
        if(clk_counter == 49_999_999) begin
            clk_counter <= 0;
            clk_1Hz <= ~clk_1Hz;
        end
        else
            clk_counter <= clk_counter + 1;
    end
    
    assign clk_out = clk_1Hz;
    
endmodule
module oneHz_generator(
    input clk_in,
    output clk_out
    );

    
    reg [25:0] clk_counter = 0;
    reg clk_1Hz = 0;
    
    always @(posedge clk_in) begin
        if(clk_counter == 49_999_999) begin
            clk_counter <= 0;
            clk_1Hz <= ~clk_1Hz;
        end
        else
            clk_counter <= clk_counter + 1;
    end
    
    assign clk_out = clk_1Hz;
    
endmodule