data/full_repos/permissive/441359809/src/yosys/examples/smtbmc/demo3.v
data/verilator_xmls/aa467bcc-1d71-4756-af99-b4236e219f54.xml
module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data);
	reg [31:0] mem [0:2**16-1];
	reg [15:0] addr_q;

	always @(posedge clk) begin
		if (rst) begin
			data <= mem[0] ^ 123456789;
			addr_q <= 0;
		end else begin
			mem[addr_q] <= data ^ 123456789;
			data <= mem[addr] ^ 123456789;
			addr_q <= addr;
		end
	end
endmodule
module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data);

	reg [31:0] mem [0:2**16-1];
	reg [15:0] addr_q;

	always @(posedge clk) begin
		if (rst) begin
			data <= mem[0] ^ 123456789;
			addr_q <= 0;
		end else begin
			mem[addr_q] <= data ^ 123456789;
			data <= mem[addr] ^ 123456789;
			addr_q <= addr;
		end
	end
endmodule