data/full_repos/permissive/46343463/src/4WayMux_TestBench.v
1: b'%Error: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:10: Unsupported: fork statements\n  fork   \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #0 a_i   = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #10 sel_i = 2\'b01;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #20 sel_i = 2\'b10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #30 sel_i = 2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/4WayMux_TestBench.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #40 sel_i = 2\'b00;\n      ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FourWayMux_TestBench;

	reg		[3:0]		a_i, b_i, c_i, d_i;
	reg		[1:0]	 	sel_i;
	wire 	[3:0]		q_o;
	
	initial begin
		fork   
	    	#0	a_i   = 1;
	    	    b_i   = 3;
	    	    c_i   = 5;
	    	    d_i   = 7;
	    	    sel_i = 2'b00;
	        
	    	#10 sel_i = 2'b01;
	    	#20 sel_i = 2'b10;
	    	#30 sel_i = 2'b11;
	    	#40 sel_i = 2'b00;
		join
	end

	Multiplexer4Way #(.width(4)) u_mux_case (
		.data_1  	(a_i),
	  	.data_2  	(b_i),
	  	.data_3  	(c_i),
	  	.data_4  	(d_i),
	  	.sel_i		(sel_i),
	  	.data_o  	(q_o)
	);

endmodule
module FourWayMux_TestBench;


	reg		[3:0]		a_i, b_i, c_i, d_i;
	reg		[1:0]	 	sel_i;
	wire 	[3:0]		q_o;
	
	initial begin
		fork   
	    	#0	a_i   = 1;
	    	    b_i   = 3;
	    	    c_i   = 5;
	    	    d_i   = 7;
	    	    sel_i = 2'b00;
	        
	    	#10 sel_i = 2'b01;
	    	#20 sel_i = 2'b10;
	    	#30 sel_i = 2'b11;
	    	#40 sel_i = 2'b00;
		join
	end

	Multiplexer4Way #(.width(4)) u_mux_case (
		.data_1  	(a_i),
	  	.data_2  	(b_i),
	  	.data_3  	(c_i),
	  	.data_4  	(d_i),
	  	.sel_i		(sel_i),
	  	.data_o  	(q_o)
	);

endmodule