data/full_repos/permissive/419538859/lab8/lab8.v
data/verilator_xmls/72eaa1fa-e1a0-4b8a-9606-e8f8e9cdaa6a.xml
module 	lab8(clk, row, red, green, column, sel, reset);

input 		reset, clk;
input 		[2:0]column;
output	    [7:0]red, row, green;


output 		[2:0]sel;
wire 		press, press_valid, coll,clk_out,clk_outt;
wire 		[3:0]key_code, scan_code, addr;
wire		[2:0]idx;
wire		[7:0]hor, ver;


assign 	addr = { coll, idx };
freq_div#(14) 	M6 (clk, reset, clk_out);

key_decode 	M1 (sel, column, press, scan_code);
key_buff 	M2 (clk_out, reset, press_valid, scan_code, key_code);
vaild		M3 (clk_out,reset,press,press_valid);
count6  	M4 (clk_out, reset, sel);

move		M5 (reset, coll, key_code, ver, hor,clk_out);
 	
map		M7 (addr,green);
idx		M8 (clk_out, reset, idx, row);
mix		M9 (ver, hor, row, red);
collision 	M10 (clk_out, reset, red, green, coll);

endmodule
module 	lab8(clk, row, red, green, column, sel, reset);


input 		reset, clk;
input 		[2:0]column;
output	    [7:0]red, row, green;


output 		[2:0]sel;
wire 		press, press_valid, coll,clk_out,clk_outt;
wire 		[3:0]key_code, scan_code, addr;
wire		[2:0]idx;
wire		[7:0]hor, ver;


assign 	addr = { coll, idx };
freq_div#(14) 	M6 (clk, reset, clk_out);

key_decode 	M1 (sel, column, press, scan_code);
key_buff 	M2 (clk_out, reset, press_valid, scan_code, key_code);
vaild		M3 (clk_out,reset,press,press_valid);
count6  	M4 (clk_out, reset, sel);

move		M5 (reset, coll, key_code, ver, hor,clk_out);
 	
map		M7 (addr,green);
idx		M8 (clk_out, reset, idx, row);
mix		M9 (ver, hor, row, red);
collision 	M10 (clk_out, reset, red, green, coll);

endmodule