data/full_repos/permissive/439731184/ft.v
1: b'%Error: data/full_repos/permissive/439731184/ft.v:196: Unsupported or unknown PLI call: $urandom\n    i1 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:197: Unsupported or unknown PLI call: $urandom\n    i2 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:198: Unsupported or unknown PLI call: $urandom\n    i3 = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/ft.v:199: Unsupported or unknown PLI call: $urandom\n    i4 = $urandom;\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:195: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/ft.v:204: Unsupported or unknown PLI call: $monitor\n    $monitor("(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n(%d,%d)\\t(%d,%d)\\n", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/ft.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module neg #(parameter N_BITS = 4) (a, b);

    input [N_BITS-1:0] a;
    wire [N_BITS-1:0] c, d;
    output [N_BITS-1:0] b;
    
    genvar i;
    generate
        for (i=0; i<N_BITS; i=i+1) begin
            not(c[i], a[i]);
        end
    endgenerate
    
    assign b[0] = a[0];
    assign d[0] = c[0];
    
    genvar j;
    generate
        for (j=1; j<N_BITS; j=j+1) begin
            and(d[j], d[j-1], c[j]);
            xor(b[j], d[j-1], c[j]);
        end
    endgenerate

endmodule
module neg #(parameter N_BITS = 4) (a, b);


    input [N_BITS-1:0] a;
    wire [N_BITS-1:0] c, d;
    output [N_BITS-1:0] b;
    
    genvar i;
    generate
        for (i=0; i<N_BITS; i=i+1) begin
            not(c[i], a[i]);
        end
    endgenerate
    
    assign b[0] = a[0];
    assign d[0] = c[0];
    
    genvar j;
    generate
        for (j=1; j<N_BITS; j=j+1) begin
            and(d[j], d[j-1], c[j]);
            xor(b[j], d[j-1], c[j]);
        end
    endgenerate

endmodule