data/full_repos/permissive/511377659/iverilog_deinter_22/sram.v
data/verilator_xmls/e1888ff7-534b-4645-93da-84f1f80eaf5a.xml
module syncRAM( dataIn,
                dataOut,
                Addr, 
                CS, 
                WE, 
                RD, 
                Clk
);



parameter ADR   = 14;
parameter DAT   = 11;
parameter DPTH  = 12288;


input   [DAT-1:0]  dataIn;
output reg [DAT-1:0]  dataOut;
input   [ADR-1:0]  Addr;
input CS, 
      WE, 
      RD, 
      Clk;

      



reg [DAT-1:0] SRAM [0:DPTH-1];


always @ (posedge Clk)
begin

 if (CS == 1'b1) begin

  if (WE == 1'b1 && RD == 1'b0) begin

   SRAM [Addr] <= dataIn;

  end

  else if (RD == 1'b1 && WE == 1'b0) begin

   dataOut <= SRAM [Addr]; 

  end

  else;

 end

 else;

end

endmodule
module syncRAM( dataIn,
                dataOut,
                Addr, 
                CS, 
                WE, 
                RD, 
                Clk
);




parameter ADR   = 14;
parameter DAT   = 11;
parameter DPTH  = 12288;


input   [DAT-1:0]  dataIn;
output reg [DAT-1:0]  dataOut;
input   [ADR-1:0]  Addr;
input CS, 
      WE, 
      RD, 
      Clk;

      



reg [DAT-1:0] SRAM [0:DPTH-1];


always @ (posedge Clk)
begin

 if (CS == 1'b1) begin

  if (WE == 1'b1 && RD == 1'b0) begin

   SRAM [Addr] <= dataIn;

  end

  else if (RD == 1'b1 && WE == 1'b0) begin

   dataOut <= SRAM [Addr]; 

  end

  else;

 end

 else;

end

endmodule