data/full_repos/permissive/522139538/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #10 sys_clk = !sys_clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #201\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522139538/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #100000;\n    ^\n%Error: data/full_repos/permissive/522139538/tb.v:11: Cannot find file containing module: \'uart_top\'\nuart_top u_uart_top(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_top\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_top.v\n             data/full_repos/permissive/522139538,data/full_repos/permissive/522139538/uart_top.sv\n             uart_top\n             uart_top.v\n             uart_top.sv\n             obj_dir/uart_top\n             obj_dir/uart_top.v\n             obj_dir/uart_top.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_timer_tb();
reg sys_clk;
reg sys_rst_n;
reg send_en;
reg [15:0]data_16;
wire send_busy;
wire uart_txd;

uart_top u_uart_top(
     .sys_clk(sys_clk),
     .sys_rst_n(sys_rst_n),
    
     .send_en(send_en),
     .data_16(data_16),
    
     .uart_tx_busy(send_busy),
     .uart_txd(uart_txd)
);

initial sys_clk = 1;
always #10 sys_clk = !sys_clk;

initial begin
    sys_rst_n = 0;
    #201
    sys_rst_n = 1;
    data_16 = 16'h1234;
    send_en = 1;
    #20;
    send_en = 0;
    #1000000;
    data_16 = 16'h4321;
    send_en = 1;
    #20;
    send_en = 0;
    #100000;
    $stop;
end

endmodule
module uart_timer_tb();

reg sys_clk;
reg sys_rst_n;
reg send_en;
reg [15:0]data_16;
wire send_busy;
wire uart_txd;

uart_top u_uart_top(
     .sys_clk(sys_clk),
     .sys_rst_n(sys_rst_n),
    
     .send_en(send_en),
     .data_16(data_16),
    
     .uart_tx_busy(send_busy),
     .uart_txd(uart_txd)
);

initial sys_clk = 1;
always #10 sys_clk = !sys_clk;

initial begin
    sys_rst_n = 0;
    #201
    sys_rst_n = 1;
    data_16 = 16'h1234;
    send_en = 1;
    #20;
    send_en = 0;
    #1000000;
    data_16 = 16'h4321;
    send_en = 1;
    #20;
    send_en = 0;
    #100000;
    $stop;
end

endmodule