data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_lut.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_lut.v:14: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n                                                                                     : ... In instance top\nassign o2 = (s ? a : a - b);\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_lut.v:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                     : ... In instance top\nassign o3 = (s ? 4\'b1111 : d + c);\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module top(
    input [8:0] a,
    input [8:0] b,
    output [8:0] o1,
    output [2:0] o2,
    input [2:0] c,
    input [2:0] d,
    output [2:0] o3,
    output [2:0] o4,
    input s
);

assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);

endmodule
module top(
    input [8:0] a,
    input [8:0] b,
    output [8:0] o1,
    output [2:0] o2,
    input [2:0] c,
    input [2:0] d,
    output [2:0] o3,
    output [2:0] o4,
    input s
);


assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);

endmodule