data/full_repos/permissive/518306354/iiitb_fifo_tb.v
1: b'%Error: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:50: Unsupported: fork statements\n      fork  \n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n           forever #10 clk = !clk;  \n                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n           #(10*2)  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n           # 7.9  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n           # 7.09  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n                #(10*5)  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n                #(10*2)  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n                #(10*2)  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n                #(10*2)  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n           #(10)  \n           ^\n%Error: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:100: Unsupported or unknown PLI call: $monitor\n           $monitor("TIME = %d, wr = %b, rd = %b, data_in = %h",$time, wr, rd, data_in);  \n           ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n           #ENDTIME  \n           ^\n%Error: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:139: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("Fifo_Memory_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/518306354/iiitb_fifo_tb.v:140: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,iiitb_fifo_tb);\n     ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module     iiitb_fifo_tb;  

 parameter     ENDTIME      = 40000;  

 reg     clk;  
 reg     rst_n;  
 reg     wr;  
 reg     rd;  
 reg     [7:0] data_in;  

 wire     [7:0] data_out;  
 wire     fifo_empty;  
 wire     fifo_full;  
 wire     fifo_threshold;  
 wire     fifo_overflow;  
 wire     fifo_underflow;  
 integer i;  

 
 iiitb_fifo tb (

   data_out, fifo_full, fifo_empty, fifo_threshold, fifo_overflow,   
   fifo_underflow,   

   clk, rst_n, wr, rd, data_in  
   );  

 initial  
      begin  
           clk     = 1'b0;  
           rst_n     = 1'b0;  
           wr     = 1'b0;  
           rd     = 1'b0;  
           data_in     = 8'd0;  
      end  

 initial  
      begin  
           main;  
      end  
 task main;  
      fork  
           clock_generator;  
           reset_generator;  
           operation_process;  
           debug_fifo;  
           endsimulation;  
      join  
 endtask  
 task clock_generator;  
      begin  
           forever #`DELAY clk = !clk;  
      end  
 endtask  
 task reset_generator;  
      begin  
           #(`DELAY*2)  
           rst_n = 1'b1;  
           # 7.9  
           rst_n = 1'b0;  
           # 7.09  
           rst_n = 1'b1;  
      end  
 endtask  
 task operation_process;  
      begin  
           for (i = 0; i < 17; i = i + 1) begin: WRE  
                #(`DELAY*5)  
                wr = 1'b1;  
                data_in = data_in + 8'd1;  
                #(`DELAY*2)  
                wr = 1'b0;  
           end  
           #(`DELAY)  
           for (i = 0; i < 17; i = i + 1) begin: RDE  
                #(`DELAY*2)  
                rd = 1'b1;  
                #(`DELAY*2)  
                rd = 1'b0;  
           end  
      end  
 endtask  

 task debug_fifo;  
      begin  
           $display("----------------------------------------------");  
           $display("------------------   -----------------------");  
           $display("----------- SIMULATION RESULT ----------------");  
           $display("--------------       -------------------");  
           $display("----------------     ---------------------");  
           $display("----------------------------------------------");  
           $monitor("TIME = %d, wr = %b, rd = %b, data_in = %h",$time, wr, rd, data_in);  
      end  
 endtask  

 reg [5:0] waddr, raddr;  
 reg [7:0] mem[64:0];  
 always @ (posedge clk) begin  
      if (~rst_n) begin  
           waddr     <= 6'd0;  
      end  
      else if (wr) begin  
           mem[waddr] <= data_in;  
           waddr <= waddr + 1;  
      end  
      $display("TIME = %d, data_out = %d, mem = %d",$time, data_out,mem[raddr]);  
      if (~rst_n) raddr     <= 6'd0;  
      else if (rd & (~fifo_empty)) raddr <= raddr + 1;  
      if (rd & (~fifo_empty)) begin  
           if (mem[raddr]  
            == data_out) begin  
                $display("=== PASS ===== PASS ==== PASS ==== PASS ===");  
                if (raddr == 16) $finish;  
           end  
           else begin  
                $display ("=== FAIL ==== FAIL ==== FAIL ==== FAIL ===");  
                $display("-------------- THE SIMUALTION FINISHED ------------");  
                $finish;  
           end  
      end  
 end  

 task endsimulation;  
      begin  
           #ENDTIME  
           $display("-------------- THE SIMUALTION FINISHED ------------");  
           $finish;  
      end  
 endtask  
   initial begin
        $dumpfile("Fifo_Memory_tb.vcd");
     $dumpvars(0,iiitb_fifo_tb);

        clk = 0;
        rst_n = 0;
        wr = 1;
        rd = 0;
        data_in = 8'd1;
    end
 endmodule
module     iiitb_fifo_tb;
  

 parameter     ENDTIME      = 40000;  

 reg     clk;  
 reg     rst_n;  
 reg     wr;  
 reg     rd;  
 reg     [7:0] data_in;  

 wire     [7:0] data_out;  
 wire     fifo_empty;  
 wire     fifo_full;  
 wire     fifo_threshold;  
 wire     fifo_overflow;  
 wire     fifo_underflow;  
 integer i;  

 
 iiitb_fifo tb (

   data_out, fifo_full, fifo_empty, fifo_threshold, fifo_overflow,   
   fifo_underflow,   

   clk, rst_n, wr, rd, data_in  
   );  

 initial  
      begin  
           clk     = 1'b0;  
           rst_n     = 1'b0;  
           wr     = 1'b0;  
           rd     = 1'b0;  
           data_in     = 8'd0;  
      end  

 initial  
      begin  
           main;  
      end  
 task main;  
      fork  
           clock_generator;  
           reset_generator;  
           operation_process;  
           debug_fifo;  
           endsimulation;  
      join  
 endtask  
 task clock_generator;  
      begin  
           forever #`DELAY clk = !clk;  
      end  
 endtask  
 task reset_generator;  
      begin  
           #(`DELAY*2)  
           rst_n = 1'b1;  
           # 7.9  
           rst_n = 1'b0;  
           # 7.09  
           rst_n = 1'b1;  
      end  
 endtask  
 task operation_process;  
      begin  
           for (i = 0; i < 17; i = i + 1) begin: WRE  
                #(`DELAY*5)  
                wr = 1'b1;  
                data_in = data_in + 8'd1;  
                #(`DELAY*2)  
                wr = 1'b0;  
           end  
           #(`DELAY)  
           for (i = 0; i < 17; i = i + 1) begin: RDE  
                #(`DELAY*2)  
                rd = 1'b1;  
                #(`DELAY*2)  
                rd = 1'b0;  
           end  
      end  
 endtask  

 task debug_fifo;  
      begin  
           $display("----------------------------------------------");  
           $display("------------------   -----------------------");  
           $display("----------- SIMULATION RESULT ----------------");  
           $display("--------------       -------------------");  
           $display("----------------     ---------------------");  
           $display("----------------------------------------------");  
           $monitor("TIME = %d, wr = %b, rd = %b, data_in = %h",$time, wr, rd, data_in);  
      end  
 endtask  

 reg [5:0] waddr, raddr;  
 reg [7:0] mem[64:0];  
 always @ (posedge clk) begin  
      if (~rst_n) begin  
           waddr     <= 6'd0;  
      end  
      else if (wr) begin  
           mem[waddr] <= data_in;  
           waddr <= waddr + 1;  
      end  
      $display("TIME = %d, data_out = %d, mem = %d",$time, data_out,mem[raddr]);  
      if (~rst_n) raddr     <= 6'd0;  
      else if (rd & (~fifo_empty)) raddr <= raddr + 1;  
      if (rd & (~fifo_empty)) begin  
           if (mem[raddr]  
            == data_out) begin  
                $display("=== PASS ===== PASS ==== PASS ==== PASS ===");  
                if (raddr == 16) $finish;  
           end  
           else begin  
                $display ("=== FAIL ==== FAIL ==== FAIL ==== FAIL ===");  
                $display("-------------- THE SIMUALTION FINISHED ------------");  
                $finish;  
           end  
      end  
 end  

 task endsimulation;  
      begin  
           #ENDTIME  
           $display("-------------- THE SIMUALTION FINISHED ------------");  
           $finish;  
      end  
 endtask  
   initial begin
        $dumpfile("Fifo_Memory_tb.vcd");
     $dumpvars(0,iiitb_fifo_tb);

        clk = 0;
        rst_n = 0;
        wr = 1;
        rd = 0;
        data_in = 8'd1;
    end
 endmodule