data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module rdyspibuffer(
	input clk,
	input dclk,
	input rst,
	input in,
	
	output reg out
);

reg f_in = 0;
reg n_in = 0;

reg nout = 0;
reg nin = 0;

always@(posedge dclk or posedge rst)begin
	if(rst) out <= 0;
	else out <= in;
end

endmodule
module rdyspibuffer(
	input clk,
	input dclk,
	input rst,
	input in,
	
	output reg out
);


reg f_in = 0;
reg n_in = 0;

reg nout = 0;
reg nin = 0;

always@(posedge dclk or posedge rst)begin
	if(rst) out <= 0;
	else out <= in;
end

endmodule