data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v
1: b'%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:3: Cannot find include file: softMC.inc\n`include "softMC.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459857219/hw/boards/ML605,data/full_repos/permissive/459857219/softMC.inc\n             data/full_repos/permissive/459857219/hw/boards/ML605,data/full_repos/permissive/459857219/softMC.inc.v\n             data/full_repos/permissive/459857219/hw/boards/ML605,data/full_repos/permissive/459857219/softMC.inc.sv\n             softMC.inc\n             softMC.inc.v\n             softMC.inc.sv\n             obj_dir/softMC.inc\n             obj_dir/softMC.inc.v\n             obj_dir/softMC.inc.sv\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:74: Define or directive not defined: \'`END_ISEQ\'\n  maint_instr = {`END_ISEQ, 28\'d0};\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:74: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  maint_instr = {`END_ISEQ, 28\'d0};\n                          ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:99: Define or directive not defined: \'`SET_BUSDIR\'\n      maint_instr[31:28] = `SET_BUSDIR;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `SET_BUSDIR;\n                                      ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:110: Define or directive not defined: \'`DDR_INSTR\'\n      maint_instr[31:28] = `DDR_INSTR;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:110: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `DDR_INSTR;\n                                     ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:111: Define or directive not defined: \'`CKE_OFFSET\'\n      maint_instr[`CKE_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:111: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CKE_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:112: Define or directive not defined: \'`CS_OFFSET\'\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:112: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                             ^~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:113: Define or directive not defined: \'`RAS_OFFSET\'\n      maint_instr[`RAS_OFFSET] = LOW;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`RAS_OFFSET] = LOW;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:114: Define or directive not defined: \'`CAS_OFFSET\'\n      maint_instr[`CAS_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:114: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CAS_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:115: Define or directive not defined: \'`WE_OFFSET\'\n      maint_instr[`WE_OFFSET] = LOW;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:115: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`WE_OFFSET] = LOW;\n                            ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:123: Define or directive not defined: \'`WAIT\'\n      maint_instr[31:28] = `WAIT;\n                           ^~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `WAIT;\n                                ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:124: Define or directive not defined: \'`DEF_TRP\'\n      maint_instr[27:0] = `DEF_TRP;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[27:0] = `DEF_TRP;\n                                  ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:132: Define or directive not defined: \'`DDR_INSTR\'\n      maint_instr[31:28] = `DDR_INSTR;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `DDR_INSTR;\n                                     ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:133: Define or directive not defined: \'`CKE_OFFSET\'\n      maint_instr[`CKE_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:133: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CKE_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:134: Define or directive not defined: \'`CS_OFFSET\'\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:134: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                             ^~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:135: Define or directive not defined: \'`RAS_OFFSET\'\n      maint_instr[`RAS_OFFSET] = LOW;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:135: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`RAS_OFFSET] = LOW;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:136: Define or directive not defined: \'`CAS_OFFSET\'\n      maint_instr[`CAS_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:136: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CAS_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:137: Define or directive not defined: \'`WE_OFFSET\'\n      maint_instr[`WE_OFFSET] = HIGH;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:137: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`WE_OFFSET] = HIGH;\n                            ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:144: Define or directive not defined: \'`WAIT\'\n      maint_instr[31:28] = `WAIT;\n                           ^~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `WAIT;\n                                ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:145: Define or directive not defined: \'`DEF_TRCD\'\n      maint_instr[27:0] = `DEF_TRCD;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:145: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[27:0] = `DEF_TRCD;\n                                   ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:154: Define or directive not defined: \'`DDR_INSTR\'\n      maint_instr[31:28] = `DDR_INSTR;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:154: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      maint_instr[31:28] = `DDR_INSTR;\n                                     ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:155: Define or directive not defined: \'`CKE_OFFSET\'\n      maint_instr[`CKE_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:155: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CKE_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:156: Define or directive not defined: \'`CS_OFFSET\'\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:156: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n      maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\n                             ^~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:157: Define or directive not defined: \'`RAS_OFFSET\'\n      maint_instr[`RAS_OFFSET] = HIGH;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:157: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`RAS_OFFSET] = HIGH;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:158: Define or directive not defined: \'`CAS_OFFSET\'\n      maint_instr[`CAS_OFFSET] = LOW;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:158: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`CAS_OFFSET] = LOW;\n                             ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:159: Define or directive not defined: \'`WE_OFFSET\'\n      maint_instr[`WE_OFFSET] = HIGH;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:159: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      maint_instr[`WE_OFFSET] = HIGH;\n                            ^\n%Error: data/full_repos/permissive/459857219/hw/boards/ML605/maint_handler.v:166: Define or directive not defined: \'`WAIT\'\n      maint_instr[31:28] = `WAIT;\n                           ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module maint_handler #(parameter CS_WIDTH = 1)(
			input clk,
			input rst,
			
			input pr_rd_req,
			input zq_req,
			input autoref_req,
			input[1:0] cur_bus_dir,
			
			output maint_instr_en,
			input maint_ack,
			output reg[31:0] maint_instr,
			
			input pr_rd_ack,
			output reg zq_ack,
			output reg autoref_ack,
			
			output periodic_read_lock,
			
			input[27:0] trfc
    );
	 
	 localparam HIGH = 1'b1;
	 localparam LOW = 1'b0;
	 

	 reg pr_rd_process_ns, pr_rd_process_r = 1'b0;
    reg zq_process_ns, zq_process_r = 1'b0;
	 reg autoref_process_ns, autoref_process_r = 1'b0;
	 wire maint_process;
	 
	 localparam PR_RD_IO = 4'b0000;
	 localparam PR_RD_PRE = 4'b0001;
	 localparam PR_RD_WAIT_PRE = 4'b0010;
	 localparam PR_RD_ACT = 4'b0011;
	 localparam PR_RD_WAIT_ACT = 4'b0100;
	 localparam PR_RD_READ = 4'b0101;
	 localparam PR_RD_WAIT_READ = 4'b0110;
	 localparam PR_RD_PRE2 = 4'b0111;
	 localparam PR_RD_WAIT_PRE2 = 4'b1000;
	 localparam PR_RD_WR_IO = 4'b1001;
	 localparam MAINT_FIN = 4'b1010;
	 
	 localparam ZQ_PRE = 4'b0000;
	 localparam ZQ_WAIT_PRE = 4'b0001;
	 localparam ZQ_ZQ = 4'b0010;
	 localparam ZQ_WAIT_ZQ = 4'b0011;
	 
	 localparam AREF_PRE = 4'b0000;
	 localparam AREF_WAIT_PRE = 4'b0001;
	 localparam AREF_REF = 4'b0010;
	 localparam AREF_WAIT_REF = 4'b0011;
	 
	 reg[3:0] maint_state, maint_state_ns;
	 
	 reg lock_pr_rd_r, lock_pr_rd_ns;
	 reg[1:0] cur_bus_dir_r, cur_bus_dir_ns;
	 
	 always@* begin
		pr_rd_process_ns = pr_rd_process_r;
		zq_process_ns = zq_process_r;
		autoref_process_ns = autoref_process_r;
		
		lock_pr_rd_ns = lock_pr_rd_r;
		
		zq_ack = 1'b0;
		autoref_ack = 1'b0;
		
		maint_state_ns = maint_state;
		maint_instr = {`END_ISEQ, 28'd0};
		
		cur_bus_dir_ns = cur_bus_dir_r;
			

		if(~maint_process) begin
			if(pr_rd_req & ~lock_pr_rd_r) begin
				pr_rd_process_ns = 1'b1;
				maint_state_ns = PR_RD_IO;
			end
			else if(zq_req) begin
				zq_process_ns = 1'b1;
				maint_state_ns = ZQ_PRE;
			end
			else if(autoref_req) begin
				autoref_process_ns = 1'b1;
				maint_state_ns = AREF_PRE;
			end
		end
		

		if(maint_process) begin
			if(pr_rd_process_r) begin
				case(maint_state)
					PR_RD_IO: begin
						maint_instr[31:28] = `SET_BUSDIR;
						
						cur_bus_dir_ns = cur_bus_dir;
						
						if(maint_ack)
							maint_state_ns = PR_RD_PRE;
					end
					
					PR_RD_PRE: begin
					

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_PRE;
					end
					
					PR_RD_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = PR_RD_ACT;
					end
					
					PR_RD_ACT: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = HIGH;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_ACT;
					end
					
					PR_RD_WAIT_ACT: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRCD;
						
						if(maint_ack)
							maint_state_ns = PR_RD_READ;
					end
					
					PR_RD_READ: begin
					

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = HIGH;
						maint_instr[`CAS_OFFSET] = LOW;
						maint_instr[`WE_OFFSET] = HIGH;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_READ;
					end
					
					PR_RD_WAIT_READ: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRAS - `DEF_TRCD;
						
						if(maint_ack)
							maint_state_ns = PR_RD_PRE2;
					end
					
					PR_RD_PRE2: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_PRE2;
					end
					
					PR_RD_WAIT_PRE2: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = (cur_bus_dir_r == `BUS_DIR_READ) ? MAINT_FIN : PR_RD_WR_IO;
					end
					
					PR_RD_WR_IO: begin
						maint_instr[31:28] = `SET_BUSDIR;
						maint_instr[1:0] = `BUS_DIR_WRITE;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						pr_rd_process_ns = 1'b0;
						lock_pr_rd_ns = 1'b1;
					end
					
				endcase
			end
			else if(zq_process_r) begin
				case(maint_state)
					ZQ_PRE: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = ZQ_WAIT_PRE;
					end
					
					ZQ_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = ZQ_ZQ;
					end
					
					ZQ_ZQ: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = HIGH;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = ZQ_WAIT_ZQ;
					end
					
					ZQ_WAIT_ZQ: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TZQCS;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						zq_process_ns = 1'b0;
						zq_ack = 1'b1;
					end
				
				endcase
			end
			
			else if(autoref_process_r) begin
				case(maint_state)
					AREF_PRE: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = AREF_WAIT_PRE;
					end
					
					AREF_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = AREF_REF;
					end
					
					AREF_REF: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = LOW;
						maint_instr[`WE_OFFSET] = HIGH;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = AREF_WAIT_REF;
					end
					
					AREF_WAIT_REF: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = trfc;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						autoref_process_ns = 1'b0;
						autoref_ack = 1'b1;
					end
					
				endcase
			end
			
		end
		
		if(pr_rd_ack) begin
			lock_pr_rd_ns = 1'b0;
			pr_rd_process_ns = 1'b0;
		end
			
    end
	 
	 assign periodic_read_lock = lock_pr_rd_r;
	 
	 always@(posedge clk) begin
		if(rst) begin
			lock_pr_rd_r <= 1'b0;
			maint_state <= 4'd0;
			cur_bus_dir_r <= `BUS_DIR_READ;
		end
		else begin
			lock_pr_rd_r <= lock_pr_rd_ns;
			maint_state <= maint_state_ns;
			cur_bus_dir_r <= cur_bus_dir_ns;
		end
	 end
	 
	 assign maint_process = pr_rd_process_r | zq_process_r | autoref_process_r;
	 
	 assign maint_instr_en = maint_process;
		
	 always@(posedge clk) begin
		pr_rd_process_r <= pr_rd_process_ns;
		zq_process_r <= zq_process_ns;
		autoref_process_r <= autoref_process_ns;
	 end


endmodule
module maint_handler #(parameter CS_WIDTH = 1)(
			input clk,
			input rst,
			
			input pr_rd_req,
			input zq_req,
			input autoref_req,
			input[1:0] cur_bus_dir,
			
			output maint_instr_en,
			input maint_ack,
			output reg[31:0] maint_instr,
			
			input pr_rd_ack,
			output reg zq_ack,
			output reg autoref_ack,
			
			output periodic_read_lock,
			
			input[27:0] trfc
    );

	 
	 localparam HIGH = 1'b1;
	 localparam LOW = 1'b0;
	 

	 reg pr_rd_process_ns, pr_rd_process_r = 1'b0;
    reg zq_process_ns, zq_process_r = 1'b0;
	 reg autoref_process_ns, autoref_process_r = 1'b0;
	 wire maint_process;
	 
	 localparam PR_RD_IO = 4'b0000;
	 localparam PR_RD_PRE = 4'b0001;
	 localparam PR_RD_WAIT_PRE = 4'b0010;
	 localparam PR_RD_ACT = 4'b0011;
	 localparam PR_RD_WAIT_ACT = 4'b0100;
	 localparam PR_RD_READ = 4'b0101;
	 localparam PR_RD_WAIT_READ = 4'b0110;
	 localparam PR_RD_PRE2 = 4'b0111;
	 localparam PR_RD_WAIT_PRE2 = 4'b1000;
	 localparam PR_RD_WR_IO = 4'b1001;
	 localparam MAINT_FIN = 4'b1010;
	 
	 localparam ZQ_PRE = 4'b0000;
	 localparam ZQ_WAIT_PRE = 4'b0001;
	 localparam ZQ_ZQ = 4'b0010;
	 localparam ZQ_WAIT_ZQ = 4'b0011;
	 
	 localparam AREF_PRE = 4'b0000;
	 localparam AREF_WAIT_PRE = 4'b0001;
	 localparam AREF_REF = 4'b0010;
	 localparam AREF_WAIT_REF = 4'b0011;
	 
	 reg[3:0] maint_state, maint_state_ns;
	 
	 reg lock_pr_rd_r, lock_pr_rd_ns;
	 reg[1:0] cur_bus_dir_r, cur_bus_dir_ns;
	 
	 always@* begin
		pr_rd_process_ns = pr_rd_process_r;
		zq_process_ns = zq_process_r;
		autoref_process_ns = autoref_process_r;
		
		lock_pr_rd_ns = lock_pr_rd_r;
		
		zq_ack = 1'b0;
		autoref_ack = 1'b0;
		
		maint_state_ns = maint_state;
		maint_instr = {`END_ISEQ, 28'd0};
		
		cur_bus_dir_ns = cur_bus_dir_r;
			

		if(~maint_process) begin
			if(pr_rd_req & ~lock_pr_rd_r) begin
				pr_rd_process_ns = 1'b1;
				maint_state_ns = PR_RD_IO;
			end
			else if(zq_req) begin
				zq_process_ns = 1'b1;
				maint_state_ns = ZQ_PRE;
			end
			else if(autoref_req) begin
				autoref_process_ns = 1'b1;
				maint_state_ns = AREF_PRE;
			end
		end
		

		if(maint_process) begin
			if(pr_rd_process_r) begin
				case(maint_state)
					PR_RD_IO: begin
						maint_instr[31:28] = `SET_BUSDIR;
						
						cur_bus_dir_ns = cur_bus_dir;
						
						if(maint_ack)
							maint_state_ns = PR_RD_PRE;
					end
					
					PR_RD_PRE: begin
					

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_PRE;
					end
					
					PR_RD_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = PR_RD_ACT;
					end
					
					PR_RD_ACT: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = HIGH;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_ACT;
					end
					
					PR_RD_WAIT_ACT: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRCD;
						
						if(maint_ack)
							maint_state_ns = PR_RD_READ;
					end
					
					PR_RD_READ: begin
					

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = HIGH;
						maint_instr[`CAS_OFFSET] = LOW;
						maint_instr[`WE_OFFSET] = HIGH;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_READ;
					end
					
					PR_RD_WAIT_READ: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRAS - `DEF_TRCD;
						
						if(maint_ack)
							maint_state_ns = PR_RD_PRE2;
					end
					
					PR_RD_PRE2: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = PR_RD_WAIT_PRE2;
					end
					
					PR_RD_WAIT_PRE2: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = (cur_bus_dir_r == `BUS_DIR_READ) ? MAINT_FIN : PR_RD_WR_IO;
					end
					
					PR_RD_WR_IO: begin
						maint_instr[31:28] = `SET_BUSDIR;
						maint_instr[1:0] = `BUS_DIR_WRITE;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						pr_rd_process_ns = 1'b0;
						lock_pr_rd_ns = 1'b1;
					end
					
				endcase
			end
			else if(zq_process_r) begin
				case(maint_state)
					ZQ_PRE: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = ZQ_WAIT_PRE;
					end
					
					ZQ_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = ZQ_ZQ;
					end
					
					ZQ_ZQ: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = HIGH;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = LOW;
						
						if(maint_ack)
							maint_state_ns = ZQ_WAIT_ZQ;
					end
					
					ZQ_WAIT_ZQ: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TZQCS;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						zq_process_ns = 1'b0;
						zq_ack = 1'b1;
					end
				
				endcase
			end
			
			else if(autoref_process_r) begin
				case(maint_state)
					AREF_PRE: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = HIGH;
						maint_instr[`WE_OFFSET] = LOW;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = AREF_WAIT_PRE;
					end
					
					AREF_WAIT_PRE: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = `DEF_TRP;
						
						if(maint_ack)
							maint_state_ns = AREF_REF;
					end
					
					AREF_REF: begin

						maint_instr[31:28] = `DDR_INSTR;
						maint_instr[`CKE_OFFSET] = HIGH;
						maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
						maint_instr[`RAS_OFFSET] = LOW;
						maint_instr[`CAS_OFFSET] = LOW;
						maint_instr[`WE_OFFSET] = HIGH;
						maint_instr[10] = HIGH;
						
						if(maint_ack)
							maint_state_ns = AREF_WAIT_REF;
					end
					
					AREF_WAIT_REF: begin
						maint_instr[31:28] = `WAIT;
						maint_instr[27:0] = trfc;
						
						if(maint_ack)
							maint_state_ns = MAINT_FIN;
					end
					
					MAINT_FIN: begin
						maint_instr[31:28] = `END_ISEQ;
						autoref_process_ns = 1'b0;
						autoref_ack = 1'b1;
					end
					
				endcase
			end
			
		end
		
		if(pr_rd_ack) begin
			lock_pr_rd_ns = 1'b0;
			pr_rd_process_ns = 1'b0;
		end
			
    end
	 
	 assign periodic_read_lock = lock_pr_rd_r;
	 
	 always@(posedge clk) begin
		if(rst) begin
			lock_pr_rd_r <= 1'b0;
			maint_state <= 4'd0;
			cur_bus_dir_r <= `BUS_DIR_READ;
		end
		else begin
			lock_pr_rd_r <= lock_pr_rd_ns;
			maint_state <= maint_state_ns;
			cur_bus_dir_r <= cur_bus_dir_ns;
		end
	 end
	 
	 assign maint_process = pr_rd_process_r | zq_process_r | autoref_process_r;
	 
	 assign maint_instr_en = maint_process;
		
	 always@(posedge clk) begin
		pr_rd_process_r <= pr_rd_process_ns;
		zq_process_r <= zq_process_ns;
		autoref_process_r <= autoref_process_ns;
	 end


endmodule