data/full_repos/permissive/529457593/Sprint10/Parallel_IN.v
data/verilator_xmls/2985fa4d-e1b3-415e-baca-9d38201c56f5.xml
module Parallel_IN (input[7:0] MemData, Address, DataIn, output[7:0] RegData);

	assign RegData = (Address == 8'hff) ? DataIn : MemData;

endmodule
module Parallel_IN (input[7:0] MemData, Address, DataIn, output[7:0] RegData);


	assign RegData = (Address == 8'hff) ? DataIn : MemData;

endmodule