data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/DR.v
data/verilator_xmls/dbbd4e0a-8b90-4fa4-a612-32b48928b0d9.xml
module DR(
    input clk,
    input [31:0] DRIn,
    output reg [31:0] DROut
    );
    
    always@(posedge clk)begin
        DROut <= DRIn;
    end
endmodule
module DR(
    input clk,
    input [31:0] DRIn,
    output reg [31:0] DROut
    );

    
    always@(posedge clk)begin
        DROut <= DRIn;
    end
endmodule