data/full_repos/permissive/488739248/rtl/ttl/ttl_74374_sync.sv
data/verilator_xmls/f0c32102-bcf7-4d39-bad0-8dee99d3ef63.xml
module ttl_74374_sync
(
    input  wire RESETn,
    input  wire Clk,
    input  wire Cen,
    input  wire OCn,
    input  wire [7:0] D,
    output wire [7:0] Q
);
    reg [7:0] Q_current;
    reg last_cen;
    
    always_ff @(posedge Clk) begin
        if (!RESETn) begin
            Q_current <= 0;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;

            if (Cen && !last_cen) Q_current <= D;
        end
    end


    assign Q = (!OCn) ?  Q_current : 8'hff;
endmodule
module ttl_74374_sync
(
    input  wire RESETn,
    input  wire Clk,
    input  wire Cen,
    input  wire OCn,
    input  wire [7:0] D,
    output wire [7:0] Q
);

    reg [7:0] Q_current;
    reg last_cen;
    
    always_ff @(posedge Clk) begin
        if (!RESETn) begin
            Q_current <= 0;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;

            if (Cen && !last_cen) Q_current <= D;
        end
    end


    assign Q = (!OCn) ?  Q_current : 8'hff;
endmodule