data/full_repos/permissive/458737381/src/verilog-parser/tests/xor_switch.v
data/verilator_xmls/d4b2c23d-6c5a-4cdd-b1e0-7b77663f168a.xml
module nor2_switch (a,b,y);
input a, b;
output y;

supply1 power;
supply0 ground;

wire  connect;

nmos (y,ground,a);
nmos (y,ground,b);
pmos (y,connect,b);
pmos (power,connect,a);

endmodule
module nor2_switch (a,b,y);

input a, b;
output y;

supply1 power;
supply0 ground;

wire  connect;

nmos (y,ground,a);
nmos (y,ground,b);
pmos (y,connect,b);
pmos (power,connect,a);

endmodule