data/full_repos/permissive/528831163/tb/boron_dec_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_dec_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/528831163/tb/boron_dec_tb.v:9: syntax error, unexpected interface, expecting IDENTIFIER or do or final\n    wire [63:0] interface, x2sb, sb2bs, bs2rp, rp2xor,\n                ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_dec_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_dec_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_dec_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module boron_dec_tb ();
     reg clk, rst, start;

    always begin
        #5 clk = ~clk;
    end
    wire [63:0] cipher_text;
    reg [79:0] master_key;
    wire [63:0] interface, x2sb, sb2bs, bs2rp, rp2xor,
    dxor2rp, drp2bs, dbs2sb, dsb2x;

    reg [63:0] plain_text;
    wire [63:0] resulting_text;

    add_round_key ark(.i_ark_msg(plain_text), .i_ark_key(master_key[63:0]), .o_ark_cipher(cipher_text));
    dec_add_round_key dark(.i_ark_cipher(cipher_text), .i_ark_key(master_key[63:0]), .o_ark_msg(resulting_text));

    initial begin
        clk = 0;
        plain_text = 64'h29337c6644443822;
        master_key = 80'h0000080000000001c00e;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        plain_text = 64'h7777aaaa3333eeee;
        master_key = 80'h0000000000000000000e;
        #100;
        plain_text = 64'h29337c6644443822;
        master_key = 80'h0000080000000001c00e;
        #100;


        
        
    end

endmodule
module boron_dec_tb ();

     reg clk, rst, start;

    always begin
        #5 clk = ~clk;
    end
    wire [63:0] cipher_text;
    reg [79:0] master_key;
    wire [63:0] interface, x2sb, sb2bs, bs2rp, rp2xor,
    dxor2rp, drp2bs, dbs2sb, dsb2x;

    reg [63:0] plain_text;
    wire [63:0] resulting_text;

    add_round_key ark(.i_ark_msg(plain_text), .i_ark_key(master_key[63:0]), .o_ark_cipher(cipher_text));
    dec_add_round_key dark(.i_ark_cipher(cipher_text), .i_ark_key(master_key[63:0]), .o_ark_msg(resulting_text));

    initial begin
        clk = 0;
        plain_text = 64'h29337c6644443822;
        master_key = 80'h0000080000000001c00e;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        plain_text = 64'h7777aaaa3333eeee;
        master_key = 80'h0000000000000000000e;
        #100;
        plain_text = 64'h29337c6644443822;
        master_key = 80'h0000080000000001c00e;
        #100;


        
        
    end

endmodule