data/full_repos/permissive/440081696/receiver.v
1: b'%Warning-WIDTH: data/full_repos/permissive/440081696/receiver.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance receiver\n    bitpos            <= 3\'b0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/440081696/receiver.v:62: Operator EQ expects 32 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                  : ... In instance receiver\n              if(i == bitpos[2:0])\n                   ^~\n%Error: Exiting due to 2 warning(s)\n'
module receiver(
  input                 clk_50m_i,
  input                 rst_n_i,
  input                 clken_i,
  output  reg   [7:0]   dout_8b_o,
  output  reg           dout_valid_o,
  input                 rx_i
);


parameter RX_STATE_START  = 2'b00;
parameter RX_STATE_DATA   = 2'b01;
parameter RX_STATE_STOP   = 2'b10;

reg [1:0] state;
reg [3:0] sample;
reg [3:0] bitpos;
reg [7:0] scratch;

integer i;
always @(posedge clk_50m_i or negedge rst_n_i) begin
  if (!rst_n_i) begin
    dout_valid_o      <= 1'b0;
    dout_8b_o         <= 8'b0;
    state             <= RX_STATE_START;
    bitpos            <= 3'b0;
    sample            <= 4'b0;
    scratch           <= 8'b0;
  end
  else begin
    dout_valid_o      <= 1'b0;
    if (clken_i) begin
      case (state)
        RX_STATE_START: begin

          if (!rx_i || sample != 0)
            sample      <= sample + 4'b1;

          if (sample == 4'd15) begin
            state       <= RX_STATE_DATA;
            bitpos      <= 0;
            sample      <= 0;
            scratch     <= 0;
          end
        end
        RX_STATE_DATA: begin
          sample        <= sample + 4'b1;
          if (sample == 4'h8) begin
            for(i=0; i<8; i=i+1) begin
              if(i == bitpos[2:0])
                scratch[i] <= rx_i;
            end
            bitpos      <= bitpos + 4'b1;
          end
          if (bitpos == 4'd8 && sample == 4'd15)
            state       <= RX_STATE_STOP;
        end
        RX_STATE_STOP: begin

          if (sample == 4'd15 || (sample >= 4'd8 && !rx_i)) begin
            state         <= RX_STATE_START;
            dout_8b_o     <= scratch;
            dout_valid_o  <= 1'b1;
            sample        <= 0;
          end else begin
            sample        <= sample + 4'b1;
          end
        end
        default: begin
          state           <= RX_STATE_START;
        end
      endcase
    end
  end
end

endmodule
module receiver(
  input                 clk_50m_i,
  input                 rst_n_i,
  input                 clken_i,
  output  reg   [7:0]   dout_8b_o,
  output  reg           dout_valid_o,
  input                 rx_i
);



parameter RX_STATE_START  = 2'b00;
parameter RX_STATE_DATA   = 2'b01;
parameter RX_STATE_STOP   = 2'b10;

reg [1:0] state;
reg [3:0] sample;
reg [3:0] bitpos;
reg [7:0] scratch;

integer i;
always @(posedge clk_50m_i or negedge rst_n_i) begin
  if (!rst_n_i) begin
    dout_valid_o      <= 1'b0;
    dout_8b_o         <= 8'b0;
    state             <= RX_STATE_START;
    bitpos            <= 3'b0;
    sample            <= 4'b0;
    scratch           <= 8'b0;
  end
  else begin
    dout_valid_o      <= 1'b0;
    if (clken_i) begin
      case (state)
        RX_STATE_START: begin

          if (!rx_i || sample != 0)
            sample      <= sample + 4'b1;

          if (sample == 4'd15) begin
            state       <= RX_STATE_DATA;
            bitpos      <= 0;
            sample      <= 0;
            scratch     <= 0;
          end
        end
        RX_STATE_DATA: begin
          sample        <= sample + 4'b1;
          if (sample == 4'h8) begin
            for(i=0; i<8; i=i+1) begin
              if(i == bitpos[2:0])
                scratch[i] <= rx_i;
            end
            bitpos      <= bitpos + 4'b1;
          end
          if (bitpos == 4'd8 && sample == 4'd15)
            state       <= RX_STATE_STOP;
        end
        RX_STATE_STOP: begin

          if (sample == 4'd15 || (sample >= 4'd8 && !rx_i)) begin
            state         <= RX_STATE_START;
            dout_8b_o     <= scratch;
            dout_valid_o  <= 1'b1;
            sample        <= 0;
          end else begin
            sample        <= sample + 4'b1;
          end
        end
        default: begin
          state           <= RX_STATE_START;
        end
      endcase
    end
  end
end

endmodule