data/full_repos/permissive/490649362/single-cycle/src/ALU.v
data/verilator_xmls/e01a3f92-598e-4f3f-bfcf-96529f0d852d.xml
module ALU(control, in_1, in_2, zero, result);

    input  [3:0]  control;
    input  [31:0] in_1, in_2;
    output        zero;
    output [31:0] result;

    reg    [31:0] result;

    assign zero = (result == 0);


    initial begin
        result = 32'b0;
    end


    always @(control, in_1, in_2) begin
        case (control)
            4'b0000: result = in_1 & in_2;
            4'b0001: result = in_1 | in_2;
            4'b0010: result = in_1 + in_2;
            4'b0110: result = in_1 - in_2;
            4'b0111: result = (in_1 < in_2) ? 1 : 0;
        endcase
    end

endmodule
module ALU(control, in_1, in_2, zero, result);


    input  [3:0]  control;
    input  [31:0] in_1, in_2;
    output        zero;
    output [31:0] result;

    reg    [31:0] result;

    assign zero = (result == 0);


    initial begin
        result = 32'b0;
    end


    always @(control, in_1, in_2) begin
        case (control)
            4'b0000: result = in_1 & in_2;
            4'b0001: result = in_1 | in_2;
            4'b0010: result = in_1 + in_2;
            4'b0110: result = in_1 - in_2;
            4'b0111: result = (in_1 < in_2) ? 1 : 0;
        endcase
    end

endmodule