data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/vlibs/p_SSYNC3DO_S_PPP.v
data/verilator_xmls/f9574f89-fd99-4c89-b68b-df53f115f3a7.xml
module  p_SSYNC3DO_S_PPP (
	 clk
	,d
	,set_
	,q
	);




input	 clk ;
input	 d ;
input	 set_ ;
output	 q ;

reg q,d1,d0;
always @(posedge clk or negedge set_)
begin
    if(~set_)
        {q,d1,d0} <= 3'b111;
    else
        {q,d1,d0} <= {d1,d0,d};
end

first_stage_of_sync first_stage_of_sync();

endmodule
module  p_SSYNC3DO_S_PPP (
	 clk
	,d
	,set_
	,q
	);





input	 clk ;
input	 d ;
input	 set_ ;
output	 q ;

reg q,d1,d0;
always @(posedge clk or negedge set_)
begin
    if(~set_)
        {q,d1,d0} <= 3'b111;
    else
        {q,d1,d0} <= {d1,d0,d};
end

first_stage_of_sync first_stage_of_sync();

endmodule