data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT.v
data/verilator_xmls/175e4bf2-ed38-4799-91a9-4e7276dc172e.xml
module LIGHT(   CLK, RESETB,
                TA, TB, 
                LA1, LA0,
                LB1, LB0
);

input CLK, RESETB, TA, TB;
output LA1, LA0, LB1, LB0;

wire [1:0] LA = {LA1, LA0};
wire [1:0] LB = {LB1, LB0};


reg     [1:0]   S;
wire    [1:0]   NEXT_S;


assign NEXT_S[1] = S[1] ^ S[0];
assign NEXT_S[0] = ( ~S[1] & ~S[0] & ~TA ) | ( S[1] & ~S[0] & ~TB );


always @( negedge RESETB or posedge CLK)
    if (~RESETB)
        S <= 2'b00;
    else
        S <= NEXT_S;


assign LA1 =  S[1];
assign LA0 = ~S[1] & S[0];
assign LB1 = ~S[1];
assign LB0 =  S[1] & S[0];

endmodule
module LIGHT(   CLK, RESETB,
                TA, TB, 
                LA1, LA0,
                LB1, LB0
);


input CLK, RESETB, TA, TB;
output LA1, LA0, LB1, LB0;

wire [1:0] LA = {LA1, LA0};
wire [1:0] LB = {LB1, LB0};


reg     [1:0]   S;
wire    [1:0]   NEXT_S;


assign NEXT_S[1] = S[1] ^ S[0];
assign NEXT_S[0] = ( ~S[1] & ~S[0] & ~TA ) | ( S[1] & ~S[0] & ~TB );


always @( negedge RESETB or posedge CLK)
    if (~RESETB)
        S <= 2'b00;
    else
        S <= NEXT_S;


assign LA1 =  S[1];
assign LA0 = ~S[1] & S[0];
assign LB1 = ~S[1];
assign LB0 =  S[1] & S[0];

endmodule