data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_rhy.v
data/verilator_xmls/a775bdc6-bdcf-464a-99ff-e5bfc671ae41.xml
module jtopl_pg_rhy (
    input wire       [ 9:0]  phase_pre,

    input wire              noise,
    input wire      [ 9:0]  hh,
    input wire              hh_en,
    input wire              tc_en,
    input wire              sd_en,
    input wire              rm_xor,
    output reg  [ 9:0]  phase_op
);

always @(*) begin
    if( hh_en ) begin
        phase_op = {rm_xor, 9'd0 };
        if( rm_xor ^ noise )
            phase_op = phase_op | 10'hd0;
        else
            phase_op = phase_op | 10'h34;
    end else if( sd_en ) begin
        phase_op = { hh[8], hh[8]^noise, 8'd0 };
    end else if( tc_en ) begin
        phase_op = { rm_xor, 9'h80 };
    end else
        phase_op = phase_pre;
end

endmodule
module jtopl_pg_rhy (
    input wire       [ 9:0]  phase_pre,

    input wire              noise,
    input wire      [ 9:0]  hh,
    input wire              hh_en,
    input wire              tc_en,
    input wire              sd_en,
    input wire              rm_xor,
    output reg  [ 9:0]  phase_op
);


always @(*) begin
    if( hh_en ) begin
        phase_op = {rm_xor, 9'd0 };
        if( rm_xor ^ noise )
            phase_op = phase_op | 10'hd0;
        else
            phase_op = phase_op | 10'h34;
    end else if( sd_en ) begin
        phase_op = { hh[8], hh[8]^noise, 8'd0 };
    end else if( tc_en ) begin
        phase_op = { rm_xor, 9'h80 };
    end else
        phase_op = phase_pre;
end

endmodule