data/full_repos/permissive/488739248/rtl/ttl/ttl_74169_sync.v
data/verilator_xmls/1400f26f-b06a-4c4f-882d-9c6d059b8994.xml
module ttl_74169_sync
(
  input wire Reset_n,
  input wire clk,
  input wire cen,
  input wire direction,
  input wire load_n,
  input wire ent_n,
  input wire enp_n,
  input wire [3:0] P,

  output wire rco_n,
  output wire [3:0] Q
);


reg [3:0] count = 0;
reg last_cen;

always @(posedge clk) begin
    if(!Reset_n) begin
        count <= 4'h0;
        last_cen<= 1'b1;
    end
    else begin
        last_cen <= cen;

        if (cen && !last_cen) begin
            if (~load_n)
            begin
                count <=  P;
            end
            else if (~ent_n & ~enp_n)
            begin
                if (direction)
                begin

                count <=  count + 1;
                end
                else
                begin

                count <=  count - 1;
                end
            end
        end
    end
end

assign Q = count;

assign rco_n = !load_n ? 1'b0: ~((&count) & ~ent_n); 

endmodule
module ttl_74169_sync
(
  input wire Reset_n,
  input wire clk,
  input wire cen,
  input wire direction,
  input wire load_n,
  input wire ent_n,
  input wire enp_n,
  input wire [3:0] P,

  output wire rco_n,
  output wire [3:0] Q
);



reg [3:0] count = 0;
reg last_cen;

always @(posedge clk) begin
    if(!Reset_n) begin
        count <= 4'h0;
        last_cen<= 1'b1;
    end
    else begin
        last_cen <= cen;

        if (cen && !last_cen) begin
            if (~load_n)
            begin
                count <=  P;
            end
            else if (~ent_n & ~enp_n)
            begin
                if (direction)
                begin

                count <=  count + 1;
                end
                else
                begin

                count <=  count - 1;
                end
            end
        end
    end
end

assign Q = count;

assign rco_n = !load_n ? 1'b0: ~((&count) & ~ent_n); 

endmodule