data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v
1: b'%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:27: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:38: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] csr_i_rs1,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:39: Define or directive not defined: \'`E203_DECINFO_CSR_WIDTH\'\n  input  [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,\n          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:48: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] read_csr_dat,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:49: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] wbck_csr_dat,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:70: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] csr_o_wbck_wdat,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:108: Define or directive not defined: \'`E203_DECINFO_CSR_CSRRW\'\n  wire        csrrw  = csr_i_info[`E203_DECINFO_CSR_CSRRW ];     \n                                  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire        csrrw  = csr_i_info[`E203_DECINFO_CSR_CSRRW ];     \n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:109: Define or directive not defined: \'`E203_DECINFO_CSR_CSRRS\'\n  wire        csrrs  = csr_i_info[`E203_DECINFO_CSR_CSRRS ];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire        csrrs  = csr_i_info[`E203_DECINFO_CSR_CSRRS ];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:110: Define or directive not defined: \'`E203_DECINFO_CSR_CSRRC\'\n  wire        csrrc  = csr_i_info[`E203_DECINFO_CSR_CSRRC ];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:110: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire        csrrc  = csr_i_info[`E203_DECINFO_CSR_CSRRC ];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:111: Define or directive not defined: \'`E203_DECINFO_CSR_RS1IMM\'\n  wire        rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:111: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire        rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:112: Define or directive not defined: \'`E203_DECINFO_CSR_RS1IS0\'\n  wire        rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:112: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire        rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:113: Define or directive not defined: \'`E203_DECINFO_CSR_ZIMMM\'\n  wire [4:0]  zimm   = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [4:0]  zimm   = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:114: Define or directive not defined: \'`E203_DECINFO_CSR_CSRIDX\'\n  wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:114: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];\n                                                          ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:116: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27\'b0,zimm} : csr_i_rs1;   \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:133: Define or directive not defined: \'`E203_XLEN\'\n              ({`E203_XLEN{csrrw}} & csr_op1)\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:134: Define or directive not defined: \'`E203_XLEN\'\n            | ({`E203_XLEN{csrrs}} & (  csr_op1  | read_csr_dat))\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_csrctrl.v:135: Define or directive not defined: \'`E203_XLEN\'\n            | ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));\n                ^~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module e203_exu_alu_csrctrl(





  input  csr_i_valid,
  output csr_i_ready,

  input  [`E203_XLEN-1:0] csr_i_rs1,
  input  [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
  input  csr_i_rdwen,   

  output csr_ena,
  output csr_wr_en,
  output csr_rd_en,
  output [12-1:0] csr_idx,

  input  csr_access_ilgl,
  input  [`E203_XLEN-1:0] read_csr_dat,
  output [`E203_XLEN-1:0] wbck_csr_dat,

  
  `ifdef E203_HAS_CSR_NICE
  input          nice_xs_off,
  output         csr_sel_nice,
  output         nice_csr_valid,
  input          nice_csr_ready,
  output  [31:0] nice_csr_addr,
  output         nice_csr_wr,
  output  [31:0] nice_csr_wdata,
  input   [31:0] nice_csr_rdata,
  `endif





  output csr_o_valid,
  input  csr_o_ready,

  output [`E203_XLEN-1:0] csr_o_wbck_wdat,
  output csr_o_wbck_err,   

  input  clk,
  input  rst_n
  );


  `ifdef E203_HAS_CSR_NICE

  assign csr_sel_nice        = (csr_idx[11:8] == 4'hE);
  wire sel_nice            = csr_sel_nice & (~nice_xs_off);
  wire addi_condi         = sel_nice ? nice_csr_ready : 1'b1; 

  assign csr_o_valid      = csr_i_valid
                            & addi_condi;

  assign nice_csr_valid    = sel_nice & csr_i_valid & 
                            csr_o_ready;


  assign csr_i_ready      = sel_nice ? (nice_csr_ready & csr_o_ready) : csr_o_ready; 

  assign csr_o_wbck_err   = csr_access_ilgl;
  assign csr_o_wbck_wdat  = sel_nice ? nice_csr_rdata : read_csr_dat;

  assign nice_csr_addr = csr_idx;
  assign nice_csr_wr   = csr_wr_en;
  assign nice_csr_wdata = wbck_csr_dat;
  `else
  wire   sel_nice      = 1'b0;
  assign csr_o_valid      = csr_i_valid;
  assign csr_i_ready      = csr_o_ready;
  assign csr_o_wbck_err   = csr_access_ilgl;
  assign csr_o_wbck_wdat  = read_csr_dat;
  `endif


  wire        csrrw  = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
  wire        csrrs  = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
  wire        csrrc  = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
  wire        rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
  wire        rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
  wire [4:0]  zimm   = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
  wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];

  wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;

  assign csr_rd_en = csr_i_valid &
    (
      (csrrw ? csr_i_rdwen : 1'b0)
      | csrrs | csrrc
     );
  assign csr_wr_en = csr_i_valid & (
                csrrw
               | ((csrrs | csrrc) & (~rs1is0))
            );                                                                           
                                                                                         
  assign csr_idx = csridx;

  assign csr_ena = csr_o_valid & csr_o_ready & (~sel_nice);

  assign wbck_csr_dat =
              ({`E203_XLEN{csrrw}} & csr_op1)
            | ({`E203_XLEN{csrrs}} & (  csr_op1  | read_csr_dat))
            | ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));

endmodule
module e203_exu_alu_csrctrl(





  input  csr_i_valid,
  output csr_i_ready,

  input  [`E203_XLEN-1:0] csr_i_rs1,
  input  [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
  input  csr_i_rdwen,   

  output csr_ena,
  output csr_wr_en,
  output csr_rd_en,
  output [12-1:0] csr_idx,

  input  csr_access_ilgl,
  input  [`E203_XLEN-1:0] read_csr_dat,
  output [`E203_XLEN-1:0] wbck_csr_dat,

  
  `ifdef E203_HAS_CSR_NICE
  input          nice_xs_off,
  output         csr_sel_nice,
  output         nice_csr_valid,
  input          nice_csr_ready,
  output  [31:0] nice_csr_addr,
  output         nice_csr_wr,
  output  [31:0] nice_csr_wdata,
  input   [31:0] nice_csr_rdata,
  `endif





  output csr_o_valid,
  input  csr_o_ready,

  output [`E203_XLEN-1:0] csr_o_wbck_wdat,
  output csr_o_wbck_err,   

  input  clk,
  input  rst_n
  );



  `ifdef E203_HAS_CSR_NICE

  assign csr_sel_nice        = (csr_idx[11:8] == 4'hE);
  wire sel_nice            = csr_sel_nice & (~nice_xs_off);
  wire addi_condi         = sel_nice ? nice_csr_ready : 1'b1; 

  assign csr_o_valid      = csr_i_valid
                            & addi_condi;

  assign nice_csr_valid    = sel_nice & csr_i_valid & 
                            csr_o_ready;


  assign csr_i_ready      = sel_nice ? (nice_csr_ready & csr_o_ready) : csr_o_ready; 

  assign csr_o_wbck_err   = csr_access_ilgl;
  assign csr_o_wbck_wdat  = sel_nice ? nice_csr_rdata : read_csr_dat;

  assign nice_csr_addr = csr_idx;
  assign nice_csr_wr   = csr_wr_en;
  assign nice_csr_wdata = wbck_csr_dat;
  `else
  wire   sel_nice      = 1'b0;
  assign csr_o_valid      = csr_i_valid;
  assign csr_i_ready      = csr_o_ready;
  assign csr_o_wbck_err   = csr_access_ilgl;
  assign csr_o_wbck_wdat  = read_csr_dat;
  `endif


  wire        csrrw  = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
  wire        csrrs  = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
  wire        csrrc  = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
  wire        rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
  wire        rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
  wire [4:0]  zimm   = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
  wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];

  wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;

  assign csr_rd_en = csr_i_valid &
    (
      (csrrw ? csr_i_rdwen : 1'b0)
      | csrrs | csrrc
     );
  assign csr_wr_en = csr_i_valid & (
                csrrw
               | ((csrrs | csrrc) & (~rs1is0))
            );                                                                           
                                                                                         
  assign csr_idx = csridx;

  assign csr_ena = csr_o_valid & csr_o_ready & (~sel_nice);

  assign wbck_csr_dat =
              ({`E203_XLEN{csrrw}} & csr_op1)
            | ({`E203_XLEN{csrrs}} & (  csr_op1  | read_csr_dat))
            | ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));

endmodule