data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v
1: b'%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:16: Unsupported: wait statements\n        wait (rdy == 1\'b1)\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #164000\n        ^\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:31: Unsupported or unknown PLI call: $monitor\n        $monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h", \n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #40 rst = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/counter/counter_fpga_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 clock = ~clock;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb();

    reg clock, rst;
    reg d_en;
    wire rdy;
    wire [11:0] d_out;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
        
        d_en = 1'b0;

        wait (rdy == 1'b1)
            begin
                 d_en = 1'b0;
            end

        #10
        d_en = 1'b1;

        #164000
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h", 
                           clock,      rst,      d_en,      d_out);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #40 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    counter dut (    .d_out(d_out),
                     .d_en(d_en),
                     .clock(clock),
                     .rst(rst),
                     .rdy(rdy)
                   );

endmodule
module counter_tb();


    reg clock, rst;
    reg d_en;
    wire rdy;
    wire [11:0] d_out;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
        
        d_en = 1'b0;

        wait (rdy == 1'b1)
            begin
                 d_en = 1'b0;
            end

        #10
        d_en = 1'b1;

        #164000
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h", 
                           clock,      rst,      d_en,      d_out);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #40 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    counter dut (    .d_out(d_out),
                     .d_en(d_en),
                     .clock(clock),
                     .rst(rst),
                     .rdy(rdy)
                   );

endmodule