data/full_repos/permissive/449071180/D_Flip_Flop_eight_bit.v
data/verilator_xmls/30e0e608-01ec-4c81-b8ad-2fdb359434bd.xml
module D_Flip_Flop_eight_bit(D,Q,Rst,Clk,set);
input [7:0] D;
input Rst,Clk,set;
output reg [7:0] Q;

always@(posedge Clk,posedge Rst, posedge set) begin
if(set == 1) begin
Q <= 8'b1;
end
else if(Rst == 1) begin
Q <= 8'b0;
end
else begin
Q <= D;
end
end

endmodule
module D_Flip_Flop_eight_bit(D,Q,Rst,Clk,set);

input [7:0] D;
input Rst,Clk,set;
output reg [7:0] Q;

always@(posedge Clk,posedge Rst, posedge set) begin
if(set == 1) begin
Q <= 8'b1;
end
else if(Rst == 1) begin
Q <= 8'b0;
end
else begin
Q <= D;
end
end

endmodule