data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v
1: b'%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:15: Cannot find file containing module: \'bin2bcd\'\nbin2bcd conv (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/ISE_devel/7seg,data/full_repos/permissive/501791642/bin2bcd\n             data/full_repos/permissive/501791642/ISE_devel/7seg,data/full_repos/permissive/501791642/bin2bcd.v\n             data/full_repos/permissive/501791642/ISE_devel/7seg,data/full_repos/permissive/501791642/bin2bcd.sv\n             bin2bcd\n             bin2bcd.v\n             bin2bcd.sv\n             obj_dir/bin2bcd\n             obj_dir/bin2bcd.v\n             obj_dir/bin2bcd.sv\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:20: Cannot find file containing module: \'up_cnt_mod\'\nup_cnt_mod #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:32: Cannot find file containing module: \'prescaler\'\nprescaler #(\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:45: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\nassign AN_OUT[0] = ~(Q == 2\'d0);\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:46: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\nassign AN_OUT[1] = ~(Q == 2\'d1);\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:47: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\nassign AN_OUT[2] = ~(Q == 2\'d2);\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:48: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\nassign AN_OUT[3] = ~(Q == 2\'d3);\n                       ^~\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:56: Cannot find file containing module: \'bcd7seg\'\nbcd7seg bcdseg0 (\n^~~~~~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:63: Cannot find file containing module: \'bcd7seg\'\nbcd7seg bcdseg1 (\n^~~~~~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:70: Cannot find file containing module: \'bcd7seg\'\nbcd7seg bcdseg2 (\n^~~~~~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:77: Cannot find file containing module: \'bcd7seg\'\nbcd7seg bcdseg3 (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:93: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\n  case (Q)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:93: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\n  case (Q)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:93: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\n  case (Q)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/501791642/ISE_devel/7seg/seg_8bit.v:93: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                 : ... In instance seg_8bit\n  case (Q)\n  ^~~~\n%Error: Exiting due to 7 error(s), 8 warning(s)\n'
module seg_8bit (
	input CLK,
	input CE,
	input [7:0] BIN_IN,
	output reg [7:0] SEG = 255,
	output reg [3:0] AN
);

wire [2:0] Q;
wire CEO;


wire [11:0] bcd;

bin2bcd conv (
	.BIN(BIN_IN),
	.BCD(bcd)
);

up_cnt_mod #(
	.MODULO(4),
	.W(2)
)
cnt
(
	.CLK(CLK),
	.CE(CEO),
	.CLR(1'd0),
	.Q(Q)
);

prescaler #(
	.MODULO(500000),
	.W(27)
)
pre
(
	.CLK(CLK),
	.CE(1'd1),
	.CEO(CEO)
);

wire [3:0] AN_OUT;

assign AN_OUT[0] = ~(Q == 2'd0);
assign AN_OUT[1] = ~(Q == 2'd1);
assign AN_OUT[2] = ~(Q == 2'd2);
assign AN_OUT[3] = ~(Q == 2'd3);


wire [7:0] seg0;
wire [7:0] seg1;
wire [7:0] seg2;
wire [7:0] seg3;

bcd7seg bcdseg0 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[3:0]),
	.SEG(seg0)
);

bcd7seg bcdseg1 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[7:4]),
	.SEG(seg1)
);

bcd7seg bcdseg2 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[11:8]),
	.SEG(seg2)
);

bcd7seg bcdseg3 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(4'd0),
	.SEG(seg3)
);




always @(posedge CLK)
	if(CEO)
		AN <= AN_OUT;

always @(posedge CLK)
	if(CEO)
		case (Q)
			2'd0 : SEG <= seg0; 
			2'd1 : SEG <= seg1; 
			2'd2 : SEG <= seg2; 
			2'd3 : SEG <= {seg3[7:1],1'd0}; 
		endcase


endmodule
module seg_8bit (
	input CLK,
	input CE,
	input [7:0] BIN_IN,
	output reg [7:0] SEG = 255,
	output reg [3:0] AN
);


wire [2:0] Q;
wire CEO;


wire [11:0] bcd;

bin2bcd conv (
	.BIN(BIN_IN),
	.BCD(bcd)
);

up_cnt_mod #(
	.MODULO(4),
	.W(2)
)
cnt
(
	.CLK(CLK),
	.CE(CEO),
	.CLR(1'd0),
	.Q(Q)
);

prescaler #(
	.MODULO(500000),
	.W(27)
)
pre
(
	.CLK(CLK),
	.CE(1'd1),
	.CEO(CEO)
);

wire [3:0] AN_OUT;

assign AN_OUT[0] = ~(Q == 2'd0);
assign AN_OUT[1] = ~(Q == 2'd1);
assign AN_OUT[2] = ~(Q == 2'd2);
assign AN_OUT[3] = ~(Q == 2'd3);


wire [7:0] seg0;
wire [7:0] seg1;
wire [7:0] seg2;
wire [7:0] seg3;

bcd7seg bcdseg0 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[3:0]),
	.SEG(seg0)
);

bcd7seg bcdseg1 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[7:4]),
	.SEG(seg1)
);

bcd7seg bcdseg2 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(bcd[11:8]),
	.SEG(seg2)
);

bcd7seg bcdseg3 (
	.CLK(CLK),
	.CE(1'd1),
	.BCD(4'd0),
	.SEG(seg3)
);




always @(posedge CLK)
	if(CEO)
		AN <= AN_OUT;

always @(posedge CLK)
	if(CEO)
		case (Q)
			2'd0 : SEG <= seg0; 
			2'd1 : SEG <= seg1; 
			2'd2 : SEG <= seg2; 
			2'd3 : SEG <= {seg3[7:1],1'd0}; 
		endcase


endmodule