data/full_repos/permissive/457911422/Master_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/457911422/Master_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n#PERIOD start = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/457911422/Master_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD*17) if (masterDataReceived == 8\'b11010011) begin\n^\n%Warning-STMTDLY: data/full_repos/permissive/457911422/Master_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD clk = ~clk;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/457911422/Master_TB.v:7: Little bit endian vector: MSB < LSB of bit range: 0:2\nwire [0:2] CS;\n     ^\n%Error: data/full_repos/permissive/457911422/Master_TB.v:51: Cannot find file containing module: \'Master\'\nMaster M(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/457911422,data/full_repos/permissive/457911422/Master\n             data/full_repos/permissive/457911422,data/full_repos/permissive/457911422/Master.v\n             data/full_repos/permissive/457911422,data/full_repos/permissive/457911422/Master.sv\n             Master\n             Master.v\n             Master.sv\n             obj_dir/Master\n             obj_dir/Master.v\n             obj_dir/Master.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Master_tb ();
reg clk, reset, start;
reg[1:0] slaveSelect;
wire [7:0] masterDataToSend;
wire [7:0] masterDataReceived;
wire sclk;
wire [0:2] CS;
reg MISO;
wire MOSI;

localparam PERIOD = 5;

reg [7:0] slave = 8'b11010011;

assign masterDataToSend = 8'b11010110;


initial begin
clk = 0;
reset = 0;
start = 1;
slaveSelect = 0;
#PERIOD start = 0;
$display ("          Master     Slave");
$display ("Initial: %b | %b", masterDataToSend, slave);
#(PERIOD*17) if (masterDataReceived == 8'b11010011) begin
	$display ("Final:   %b | %b", masterDataReceived, slave);
	$display ("Success!");
	$finish;
end
else begin
	$display ("Failed!");
	$finish;
end
end
always begin
	#PERIOD clk = ~clk;
end
always @(posedge clk) begin
if (!CS[0]) begin
	MISO = slave[0];
	slave = slave >> 1;
end
end
always @(negedge clk) begin
if (!CS[0]) begin
	slave[7] = MOSI;
end
end

Master M(
clk, 
reset,
start, 
slaveSelect,
masterDataToSend,
masterDataReceived,
sclk,
CS,
MOSI,
MISO
);


endmodule
module Master_tb ();

reg clk, reset, start;
reg[1:0] slaveSelect;
wire [7:0] masterDataToSend;
wire [7:0] masterDataReceived;
wire sclk;
wire [0:2] CS;
reg MISO;
wire MOSI;

localparam PERIOD = 5;

reg [7:0] slave = 8'b11010011;

assign masterDataToSend = 8'b11010110;


initial begin
clk = 0;
reset = 0;
start = 1;
slaveSelect = 0;
#PERIOD start = 0;
$display ("          Master     Slave");
$display ("Initial: %b | %b", masterDataToSend, slave);
#(PERIOD*17) if (masterDataReceived == 8'b11010011) begin
	$display ("Final:   %b | %b", masterDataReceived, slave);
	$display ("Success!");
	$finish;
end
else begin
	$display ("Failed!");
	$finish;
end
end
always begin
	#PERIOD clk = ~clk;
end
always @(posedge clk) begin
if (!CS[0]) begin
	MISO = slave[0];
	slave = slave >> 1;
end
end
always @(negedge clk) begin
if (!CS[0]) begin
	slave[7] = MOSI;
end
end

Master M(
clk, 
reset,
start, 
slaveSelect,
masterDataToSend,
masterDataReceived,
sclk,
CS,
MOSI,
MISO
);


endmodule