data/full_repos/permissive/421048855/Circuits/Sequential Logic/Shift Registers/Shift Register.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers,data/full_repos/permissive/421048855\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/Shift\n%Error: Cannot find file containing module: Register.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
);
reg [3:0] LEDR_ins;
wire [3:0] W;

assign W = {KEY[3],LEDR[3:1]};

always @(posedge KEY[0]) begin
	LEDR <= LEDR_ins;
end

generate 
	genvar geni;
	for(geni = 0; geni < 4; geni = geni + 1) begin: loop
		MUXDFF(
		.Q_nxt	(LEDR[geni]),
		.w		(W[geni]),
		.E		(KEY[1]),
		.R		(SW[geni]),
		.L		(KEY[2]),
		.D_pre	(LEDR_ins[geni])
		);
	end
endgenerate

endmodule
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
);

reg [3:0] LEDR_ins;
wire [3:0] W;

assign W = {KEY[3],LEDR[3:1]};

always @(posedge KEY[0]) begin
	LEDR <= LEDR_ins;
end

generate 
	genvar geni;
	for(geni = 0; geni < 4; geni = geni + 1) begin: loop
		MUXDFF(
		.Q_nxt	(LEDR[geni]),
		.w		(W[geni]),
		.E		(KEY[1]),
		.R		(SW[geni]),
		.L		(KEY[2]),
		.D_pre	(LEDR_ins[geni])
		);
	end
endgenerate

endmodule