data/full_repos/permissive/430260837/ClockDividerSixty.v
data/verilator_xmls/1e68da4f-f91d-46c7-8ee4-8d28c6b333e4.xml
module ClockDividerSixty(cin,cout);



input cin;
output reg cout;

reg[31:0] count; 
parameter D = 32'd1000000;

always @(posedge cin)
begin
   count <= count + 32'd1;
      if (count >= (D-1)) begin
         cout <= 1;
         count <= 32'd0;
      end
        else begin
            cout <= 0;
        end
end


endmodule
module ClockDividerSixty(cin,cout);




input cin;
output reg cout;

reg[31:0] count; 
parameter D = 32'd1000000;

always @(posedge cin)
begin
   count <= count + 32'd1;
      if (count >= (D-1)) begin
         cout <= 1;
         count <= 32'd0;
      end
        else begin
            cout <= 0;
        end
end


endmodule