data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:83: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:86: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:99: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:102: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:115: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:118: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:178: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:181: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:209: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:212: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:241: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:244: Unsupported: Ignoring delay on this delayed statement.\n                    #2; \n                    ^\n%Error: data/full_repos/permissive/506186384/project-files/lab6/Cache_Line.v:50: Cannot find file containing module: \'DataMemory\'\n    DataMemory DataMemory(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506186384/project-files/lab6,data/full_repos/permissive/506186384/DataMemory\n             data/full_repos/permissive/506186384/project-files/lab6,data/full_repos/permissive/506186384/DataMemory.v\n             data/full_repos/permissive/506186384/project-files/lab6,data/full_repos/permissive/506186384/DataMemory.sv\n             DataMemory\n             DataMemory.v\n             DataMemory.sv\n             obj_dir/DataMemory\n             obj_dir/DataMemory.v\n             obj_dir/DataMemory.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Cache_Line(
    input Clk,
    input reset,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    input [1:0] MByte,
    output [31:0] ReadData
    );
    





    reg [68:0] CacheData [0:1];
    reg [31:0] rd;
    


    reg [31:0] Main_Address;
    reg [31:0] Main_MemWriteData;
    wire [31:0] Main_ReadData;
    reg Main_MemWrite;
    reg Main_MemRead;
    reg [1:0] Main_MByte;
    DataMemory DataMemory(
        .Clk(Clk),
        .Address(Main_Address),
        .WriteData(Main_MemWriteData),
        .MemWrite(Main_MemWrite),
        .MemRead(Main_MemRead),
        .MByte(Main_MByte),
        .ReadData(Main_ReadData)
    );
    


    integer ptr;
    always @(posedge Clk) begin
        if(MemRead == 1) begin

            if(CacheData[0][68] == 1 && CacheData[0][67:64] == Address[4:1]) begin
                if(Address[0] == 0) rd = CacheData[0][31:0];
                else if(Address[0] == 1) rd = CacheData[0][63:32];
            end
            else if(CacheData[1][68] == 1 && CacheData[1][67:64] == Address[4:1]) begin
                if(Address[0] == 0) rd = CacheData[1][31:0];
                else if(Address[0] == 1) rd = CacheData[1][63:32];
            end

            else begin

                if(CacheData[0][68] == 0) begin
                    CacheData[0][67:64] = Address[4:1];
                    CacheData[0][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[0][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[0][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[0][31:0];
                    else if(Address[0] == 1) rd = CacheData[0][63:32];
                end
                else if(CacheData[1][68] == 0) begin
                    CacheData[1][67:64] = Address[4:1];
                    CacheData[1][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[1][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[1][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[1][31:0];
                    else if(Address[0] == 1) rd = CacheData[1][63:32];
                end

                else begin
                    CacheData[ptr][67:64] = Address[4:1];

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[ptr][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[ptr][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[ptr][31:0];
                    else if(Address[0] == 1) rd = CacheData[ptr][63:32];

                    ptr = (ptr + 1) % 2;
                end
            end
            Main_MemWrite = 0;
        end
        else if(MemWrite == 1) begin

            if(CacheData[0][68] == 1 && CacheData[0][67:64] == Address[4:1]) begin
                if(Address[0] == 0) begin
                    case(MByte)
                        2'b00: CacheData[0][31:0] = WriteData;
                        2'b01: CacheData[0][15:0] = WriteData[15:0];
                        2'b10: CacheData[0][7:0] = WriteData[7:0];
                        default: CacheData[0][31:0] = WriteData;
                    endcase 
                end
                else if(Address[0] == 1) begin
                    case(MByte)
                        2'b00: CacheData[0][63:32] = WriteData;
                        2'b01: CacheData[0][47:32] = WriteData[15:0];
                        2'b10: CacheData[0][39:32] = WriteData[7:0];
                        default: CacheData[0][63:32] = WriteData;
                    endcase 
                end
            end
            else if(CacheData[1][68] == 1 && CacheData[1][67:64] == Address[4:1]) begin
                if(Address[0] == 0) begin
                    case(MByte)
                        2'b00: CacheData[1][31:0] = WriteData;
                        2'b01: CacheData[1][15:0] = WriteData[15:0];
                        2'b10: CacheData[1][7:0] = WriteData[7:0];
                        default: CacheData[1][31:0] = WriteData;
                    endcase 
                end
                else if(Address[0] == 1) begin
                    case(MByte)
                        2'b00: CacheData[1][63:32] = WriteData;
                        2'b01: CacheData[1][47:32] = WriteData[15:0];
                        2'b10: CacheData[1][39:32] = WriteData[7:0];
                        default: CacheData[1][63:32] = WriteData;
                    endcase 
                end
            end


            else begin

                if(CacheData[0][68] == 0) begin
                    CacheData[0][67:64] = Address[4:1];
                    CacheData[0][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[0][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[0][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[0][31:0] = WriteData;
                            2'b01: CacheData[0][15:0] = WriteData[15:0];
                            2'b10: CacheData[0][7:0] = WriteData[7:0];
                            default: CacheData[0][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[0][63:32] = WriteData;
                            2'b01: CacheData[0][47:32] = WriteData[15:0];
                            2'b10: CacheData[0][39:32] = WriteData[7:0];
                            default: CacheData[0][63:32] = WriteData;
                        endcase 
                    end

                end
                else if(CacheData[1][68] == 0) begin
                    CacheData[1][67:64] = Address[4:1];
                    CacheData[1][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[1][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[1][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[1][31:0] = WriteData;
                            2'b01: CacheData[1][15:0] = WriteData[15:0];
                            2'b10: CacheData[1][7:0] = WriteData[7:0];
                            default: CacheData[1][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[1][63:32] = WriteData;
                            2'b01: CacheData[1][47:32] = WriteData[15:0];
                            2'b10: CacheData[1][39:32] = WriteData[7:0];
                            default: CacheData[1][63:32] = WriteData;
                        endcase 
                    end

                end

                else begin

                    CacheData[ptr][67:64] = Address[4:1];

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[ptr][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[ptr][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[ptr][31:0] = WriteData;
                            2'b01: CacheData[ptr][15:0] = WriteData[15:0];
                            2'b10: CacheData[ptr][7:0] = WriteData[7:0];
                            default: CacheData[ptr][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[ptr][63:32] = WriteData;
                            2'b01: CacheData[ptr][47:32] = WriteData[15:0];
                            2'b10: CacheData[ptr][39:32] = WriteData[7:0];
                            default: CacheData[ptr][63:32] = WriteData;
                        endcase 
                    end

                    ptr = (ptr + 1) % 2;

                end
            end

            Main_MemWrite = 1;
            Main_Address = Address;
            Main_MemWriteData = WriteData;
            Main_MByte = MByte;
        end
        else begin
            Main_MemRead = 0;
            Main_MemWrite = 0;
        end
    end
    
    assign ReadData = rd;
    

    always @(negedge Clk) begin

    end
    
    always @(posedge reset)
        begin
            CacheData[0] = 0;
            CacheData[1] = 0;
            ptr = 0;
            Main_MemWrite = 0;
            Main_MemRead = 0;
        end
endmodule
module Cache_Line(
    input Clk,
    input reset,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    input [1:0] MByte,
    output [31:0] ReadData
    );

    





    reg [68:0] CacheData [0:1];
    reg [31:0] rd;
    


    reg [31:0] Main_Address;
    reg [31:0] Main_MemWriteData;
    wire [31:0] Main_ReadData;
    reg Main_MemWrite;
    reg Main_MemRead;
    reg [1:0] Main_MByte;
    DataMemory DataMemory(
        .Clk(Clk),
        .Address(Main_Address),
        .WriteData(Main_MemWriteData),
        .MemWrite(Main_MemWrite),
        .MemRead(Main_MemRead),
        .MByte(Main_MByte),
        .ReadData(Main_ReadData)
    );
    


    integer ptr;
    always @(posedge Clk) begin
        if(MemRead == 1) begin

            if(CacheData[0][68] == 1 && CacheData[0][67:64] == Address[4:1]) begin
                if(Address[0] == 0) rd = CacheData[0][31:0];
                else if(Address[0] == 1) rd = CacheData[0][63:32];
            end
            else if(CacheData[1][68] == 1 && CacheData[1][67:64] == Address[4:1]) begin
                if(Address[0] == 0) rd = CacheData[1][31:0];
                else if(Address[0] == 1) rd = CacheData[1][63:32];
            end

            else begin

                if(CacheData[0][68] == 0) begin
                    CacheData[0][67:64] = Address[4:1];
                    CacheData[0][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[0][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[0][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[0][31:0];
                    else if(Address[0] == 1) rd = CacheData[0][63:32];
                end
                else if(CacheData[1][68] == 0) begin
                    CacheData[1][67:64] = Address[4:1];
                    CacheData[1][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[1][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[1][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[1][31:0];
                    else if(Address[0] == 1) rd = CacheData[1][63:32];
                end

                else begin
                    CacheData[ptr][67:64] = Address[4:1];

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[ptr][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[ptr][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) rd = CacheData[ptr][31:0];
                    else if(Address[0] == 1) rd = CacheData[ptr][63:32];

                    ptr = (ptr + 1) % 2;
                end
            end
            Main_MemWrite = 0;
        end
        else if(MemWrite == 1) begin

            if(CacheData[0][68] == 1 && CacheData[0][67:64] == Address[4:1]) begin
                if(Address[0] == 0) begin
                    case(MByte)
                        2'b00: CacheData[0][31:0] = WriteData;
                        2'b01: CacheData[0][15:0] = WriteData[15:0];
                        2'b10: CacheData[0][7:0] = WriteData[7:0];
                        default: CacheData[0][31:0] = WriteData;
                    endcase 
                end
                else if(Address[0] == 1) begin
                    case(MByte)
                        2'b00: CacheData[0][63:32] = WriteData;
                        2'b01: CacheData[0][47:32] = WriteData[15:0];
                        2'b10: CacheData[0][39:32] = WriteData[7:0];
                        default: CacheData[0][63:32] = WriteData;
                    endcase 
                end
            end
            else if(CacheData[1][68] == 1 && CacheData[1][67:64] == Address[4:1]) begin
                if(Address[0] == 0) begin
                    case(MByte)
                        2'b00: CacheData[1][31:0] = WriteData;
                        2'b01: CacheData[1][15:0] = WriteData[15:0];
                        2'b10: CacheData[1][7:0] = WriteData[7:0];
                        default: CacheData[1][31:0] = WriteData;
                    endcase 
                end
                else if(Address[0] == 1) begin
                    case(MByte)
                        2'b00: CacheData[1][63:32] = WriteData;
                        2'b01: CacheData[1][47:32] = WriteData[15:0];
                        2'b10: CacheData[1][39:32] = WriteData[7:0];
                        default: CacheData[1][63:32] = WriteData;
                    endcase 
                end
            end


            else begin

                if(CacheData[0][68] == 0) begin
                    CacheData[0][67:64] = Address[4:1];
                    CacheData[0][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[0][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[0][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[0][31:0] = WriteData;
                            2'b01: CacheData[0][15:0] = WriteData[15:0];
                            2'b10: CacheData[0][7:0] = WriteData[7:0];
                            default: CacheData[0][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[0][63:32] = WriteData;
                            2'b01: CacheData[0][47:32] = WriteData[15:0];
                            2'b10: CacheData[0][39:32] = WriteData[7:0];
                            default: CacheData[0][63:32] = WriteData;
                        endcase 
                    end

                end
                else if(CacheData[1][68] == 0) begin
                    CacheData[1][67:64] = Address[4:1];
                    CacheData[1][68] = 1;

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[1][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[1][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[1][31:0] = WriteData;
                            2'b01: CacheData[1][15:0] = WriteData[15:0];
                            2'b10: CacheData[1][7:0] = WriteData[7:0];
                            default: CacheData[1][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[1][63:32] = WriteData;
                            2'b01: CacheData[1][47:32] = WriteData[15:0];
                            2'b10: CacheData[1][39:32] = WriteData[7:0];
                            default: CacheData[1][63:32] = WriteData;
                        endcase 
                    end

                end

                else begin

                    CacheData[ptr][67:64] = Address[4:1];

                    Main_MemRead = 1;
                    Main_Address = {Address[31:1],1'b0};
                    #2;
                    CacheData[ptr][31:0] = Main_ReadData;
                    Main_Address = {Address[31:1],1'b1};
                    #2;
                    CacheData[ptr][63:32] = Main_ReadData;
                    Main_MemRead = 0;

                    if(Address[0] == 0) begin
                        case(MByte)
                            2'b00: CacheData[ptr][31:0] = WriteData;
                            2'b01: CacheData[ptr][15:0] = WriteData[15:0];
                            2'b10: CacheData[ptr][7:0] = WriteData[7:0];
                            default: CacheData[ptr][31:0] = WriteData;
                        endcase 
                    end
                    else if(Address[0] == 1) begin
                        case(MByte)
                            2'b00: CacheData[ptr][63:32] = WriteData;
                            2'b01: CacheData[ptr][47:32] = WriteData[15:0];
                            2'b10: CacheData[ptr][39:32] = WriteData[7:0];
                            default: CacheData[ptr][63:32] = WriteData;
                        endcase 
                    end

                    ptr = (ptr + 1) % 2;

                end
            end

            Main_MemWrite = 1;
            Main_Address = Address;
            Main_MemWriteData = WriteData;
            Main_MByte = MByte;
        end
        else begin
            Main_MemRead = 0;
            Main_MemWrite = 0;
        end
    end
    
    assign ReadData = rd;
    

    always @(negedge Clk) begin

    end
    
    always @(posedge reset)
        begin
            CacheData[0] = 0;
            CacheData[1] = 0;
            ptr = 0;
            Main_MemWrite = 0;
            Main_MemRead = 0;
        end
endmodule