data/full_repos/permissive/462122681/div.v
data/verilator_xmls/c8baa8f7-26b3-40e1-9432-d25258652427.xml
module div(
    input wire [31:0] A, 
    input wire [31:0] B, 
    output reg[63:0] out 

);
initial begin
	out = 64'b0;
end 
	always @(*) begin 
		begin
			out = {(A&B), (A-(A%B)) / B};
		end
	end
endmodule
module div(
    input wire [31:0] A, 
    input wire [31:0] B, 
    output reg[63:0] out 

);

initial begin
	out = 64'b0;
end 
	always @(*) begin 
		begin
			out = {(A&B), (A-(A%B)) / B};
		end
	end
endmodule