data/full_repos/permissive/418753087/E902_RTL_FACTORY/gen_rtl/cp0/rtl/cr_cp0_srst.v
data/verilator_xmls/a8f0fc1b-e0a5-4596-b102-2ce7037c24c8.xml
module cr_cp0_srst(
  cache_cp0_srst_ack,
  cp0_cache_srst_req,
  cp0_ifu_srst_mask,
  cp0_ifu_srst_req,
  cp0_sysio_srst,
  cpurst_b,
  ifu_cp0_srst_ack,
  iu_cp0_ex_sel,
  iu_yy_xx_flush,
  srst_iui_stall,
  srst_iui_stall_noinput,
  srst_sm_clk,
  srst_sm_clk_en,
  status_srst_req_valid,
  status_srst_req_valid_noinput,
  status_srst_value
);


input          cache_cp0_srst_ack;           
input          cpurst_b;                     
input          ifu_cp0_srst_ack;             
input          iu_cp0_ex_sel;                
input          iu_yy_xx_flush;               
input          srst_sm_clk;                  
input          status_srst_req_valid;        
input          status_srst_req_valid_noinput; 
input   [1:0]  status_srst_value;            
output         cp0_cache_srst_req;           
output         cp0_ifu_srst_mask;            
output         cp0_ifu_srst_req;             
output  [1:0]  cp0_sysio_srst;               
output         srst_iui_stall;               
output         srst_iui_stall_noinput;       
output         srst_sm_clk_en;               


reg     [1:0]  cur_state;                    
reg     [1:0]  next_state;                   


wire           cache_cp0_srst_ack;           
wire           cp0_cache_srst_req;           
wire           cp0_ifu_srst_mask;            
wire           cp0_ifu_srst_req;             
wire    [1:0]  cp0_sysio_srst;               
wire           cpurst_b;                     
wire           ifu_cp0_srst_ack;             
wire           iu_cp0_ex_sel;                
wire           iu_yy_xx_flush;               
wire           srst_ack;                     
wire           srst_cmplt;                   
wire           srst_in_wait_state;           
wire           srst_iui_stall;               
wire           srst_iui_stall_noinput;       
wire           srst_sm_clk;                  
wire           srst_sm_clk_en;               
wire           status_srst_req_valid;        
wire           status_srst_req_valid_noinput; 
wire    [1:0]  status_srst_value;            


parameter IDLE   = 2'b00;
parameter WFACK  = 2'b01;
parameter WFCPLT = 2'b10;
parameter WFRST  = 2'b11;




assign srst_sm_clk_en = iu_cp0_ex_sel || (cur_state != IDLE); 













always @(posedge srst_sm_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cur_state[1:0] <= IDLE;
  else if(iu_yy_xx_flush)
    cur_state[1:0] <= IDLE;
  else
    cur_state[1:0] <= next_state[1:0];
end


always @( cur_state
       or status_srst_req_valid
       or srst_ack)
begin
  case(cur_state)
  IDLE   : if(status_srst_req_valid)
             next_state = WFACK;
           else
             next_state = IDLE;
  WFACK  : if(srst_ack)
             next_state = WFCPLT;
           else
             next_state = WFACK;
  WFCPLT :   next_state = WFRST;
  WFRST  :   next_state = WFRST;
  default:   next_state = IDLE;
  endcase

end

assign srst_in_wait_state = (cur_state == WFACK);
assign srst_cmplt         = (cur_state == WFCPLT);


assign srst_iui_stall = (cur_state == IDLE) && status_srst_req_valid
                     || (cur_state != IDLE);
assign srst_iui_stall_noinput = (cur_state == IDLE) && status_srst_req_valid_noinput
                     || (cur_state != IDLE);

assign cp0_ifu_srst_req = srst_in_wait_state;
assign cp0_cache_srst_req = srst_in_wait_state;




assign srst_ack = ifu_cp0_srst_ack && cache_cp0_srst_ack;

assign cp0_sysio_srst[1:0] = {2{srst_cmplt}} & status_srst_value[1:0];

assign cp0_ifu_srst_mask = (cur_state == WFCPLT) || (cur_state == WFRST);


endmodule
module cr_cp0_srst(
  cache_cp0_srst_ack,
  cp0_cache_srst_req,
  cp0_ifu_srst_mask,
  cp0_ifu_srst_req,
  cp0_sysio_srst,
  cpurst_b,
  ifu_cp0_srst_ack,
  iu_cp0_ex_sel,
  iu_yy_xx_flush,
  srst_iui_stall,
  srst_iui_stall_noinput,
  srst_sm_clk,
  srst_sm_clk_en,
  status_srst_req_valid,
  status_srst_req_valid_noinput,
  status_srst_value
);



input          cache_cp0_srst_ack;           
input          cpurst_b;                     
input          ifu_cp0_srst_ack;             
input          iu_cp0_ex_sel;                
input          iu_yy_xx_flush;               
input          srst_sm_clk;                  
input          status_srst_req_valid;        
input          status_srst_req_valid_noinput; 
input   [1:0]  status_srst_value;            
output         cp0_cache_srst_req;           
output         cp0_ifu_srst_mask;            
output         cp0_ifu_srst_req;             
output  [1:0]  cp0_sysio_srst;               
output         srst_iui_stall;               
output         srst_iui_stall_noinput;       
output         srst_sm_clk_en;               


reg     [1:0]  cur_state;                    
reg     [1:0]  next_state;                   


wire           cache_cp0_srst_ack;           
wire           cp0_cache_srst_req;           
wire           cp0_ifu_srst_mask;            
wire           cp0_ifu_srst_req;             
wire    [1:0]  cp0_sysio_srst;               
wire           cpurst_b;                     
wire           ifu_cp0_srst_ack;             
wire           iu_cp0_ex_sel;                
wire           iu_yy_xx_flush;               
wire           srst_ack;                     
wire           srst_cmplt;                   
wire           srst_in_wait_state;           
wire           srst_iui_stall;               
wire           srst_iui_stall_noinput;       
wire           srst_sm_clk;                  
wire           srst_sm_clk_en;               
wire           status_srst_req_valid;        
wire           status_srst_req_valid_noinput; 
wire    [1:0]  status_srst_value;            


parameter IDLE   = 2'b00;
parameter WFACK  = 2'b01;
parameter WFCPLT = 2'b10;
parameter WFRST  = 2'b11;




assign srst_sm_clk_en = iu_cp0_ex_sel || (cur_state != IDLE); 













always @(posedge srst_sm_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cur_state[1:0] <= IDLE;
  else if(iu_yy_xx_flush)
    cur_state[1:0] <= IDLE;
  else
    cur_state[1:0] <= next_state[1:0];
end


always @( cur_state
       or status_srst_req_valid
       or srst_ack)
begin
  case(cur_state)
  IDLE   : if(status_srst_req_valid)
             next_state = WFACK;
           else
             next_state = IDLE;
  WFACK  : if(srst_ack)
             next_state = WFCPLT;
           else
             next_state = WFACK;
  WFCPLT :   next_state = WFRST;
  WFRST  :   next_state = WFRST;
  default:   next_state = IDLE;
  endcase

end

assign srst_in_wait_state = (cur_state == WFACK);
assign srst_cmplt         = (cur_state == WFCPLT);


assign srst_iui_stall = (cur_state == IDLE) && status_srst_req_valid
                     || (cur_state != IDLE);
assign srst_iui_stall_noinput = (cur_state == IDLE) && status_srst_req_valid_noinput
                     || (cur_state != IDLE);

assign cp0_ifu_srst_req = srst_in_wait_state;
assign cp0_cache_srst_req = srst_in_wait_state;




assign srst_ack = ifu_cp0_srst_ack && cache_cp0_srst_ack;

assign cp0_sysio_srst[1:0] = {2{srst_cmplt}} & status_srst_value[1:0];

assign cp0_ifu_srst_mask = (cur_state == WFCPLT) || (cur_state == WFRST);


endmodule