data/full_repos/permissive/469195529/sources/hdl/mux8bit8to1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469195529/sources/hdl/mux8bit8to1.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'bxxxxxxx\' generates 7 bits.\n                                                                                 : ... In instance mux8bit8to1\n            default: z = 7\'bxxxxxxx;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux8bit8to1(
    input [7:0] a, b, c, d, e, f, g, h,
    input [2:0] s,
    output reg [7:0] z
);
    always@(a or b or c or d or e or f or g or h or s) begin      
        case(s)
            3'b000: z = a;
            3'b001: z = b;
            3'b010: z = c;
            3'b011: z = d;
            3'b100: z = e;
            3'b101: z = f;
            3'b110: z = g;
            3'b111: z = h;
            default: z = 7'bxxxxxxx;
        endcase
    end
endmodule
module mux8bit8to1(
    input [7:0] a, b, c, d, e, f, g, h,
    input [2:0] s,
    output reg [7:0] z
);

    always@(a or b or c or d or e or f or g or h or s) begin      
        case(s)
            3'b000: z = a;
            3'b001: z = b;
            3'b010: z = c;
            3'b011: z = d;
            3'b100: z = e;
            3'b101: z = f;
            3'b110: z = g;
            3'b111: z = h;
            default: z = 7'bxxxxxxx;
        endcase
    end
endmodule