data/full_repos/permissive/520428138/verilog/rtl/user_module_341457971277988435.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/520428138/verilog/rtl/user_module_341457971277988435.v:65: Little bit endian vector: MSB < LSB of bit range: 0:10\n  wire [0:FRAME_LENGTH-1] current_frame;  \n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module user_module_341457971277988435(
  input [7:0] io_in, 
  output [7:0] io_out
);

  wire uart_tx;

  assign io_out[0] = uart_tx;

  hello_world_341457971277988435 hello_world(
    .clk(io_in[0]),    
    .reset(io_in[1]),
    
    .uart_tx(uart_tx)
  );

endmodule
module user_module_341457971277988435(
  input [7:0] io_in, 
  output [7:0] io_out
);


  wire uart_tx;

  assign io_out[0] = uart_tx;

  hello_world_341457971277988435 hello_world(
    .clk(io_in[0]),    
    .reset(io_in[1]),
    
    .uart_tx(uart_tx)
  );

endmodule