data/full_repos/permissive/430422543/uart/src/uart_tx.v
1: b'%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:1: Cannot find include file: uart_states.vh\n`include "uart_states.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh.v\n             data/full_repos/permissive/430422543/uart/src,data/full_repos/permissive/430422543/uart_states.vh.sv\n             uart_states.vh\n             uart_states.vh.v\n             uart_states.vh.sv\n             obj_dir/uart_states.vh\n             obj_dir/uart_states.vh.v\n             obj_dir/uart_states.vh.sv\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:15: Define or directive not defined: \'`RESET\'\n    reg [2:0] state  = `RESET;\n                       ^~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [2:0] state  = `RESET;\n                             ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:25: Define or directive not defined: \'`IDLE\'\n                state   <= `IDLE;\n                           ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `IDLE;\n                                ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:27: Define or directive not defined: \'`IDLE\'\n            `IDLE       : begin\n            ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:27: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `IDLE       : begin\n                          ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:35: Define or directive not defined: \'`START_BIT\'\n                    state   <= `START_BIT;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    state   <= `START_BIT;\n                                         ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:38: Define or directive not defined: \'`START_BIT\'\n            `START_BIT  : begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:38: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `START_BIT  : begin\n                          ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:41: Define or directive not defined: \'`DATA_BIT\'\n                state   <= `DATA_BIT;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `DATA_BIT;\n                                    ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:43: Define or directive not defined: \'`DATA_BIT\'\n            `DATA_BIT  : begin \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:43: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `DATA_BIT  : begin \n                         ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:47: Define or directive not defined: \'`STOP_BIT\'\n                    state   <= `STOP_BIT;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:47: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    state   <= `STOP_BIT;\n                                        ^\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:52: Define or directive not defined: \'`STOP_BIT\'\n            `STOP_BIT   : begin \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:52: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `STOP_BIT   : begin \n                          ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:55: Define or directive not defined: \'`IDLE\'\n                state   <= `IDLE;\n                           ^~~~~\n%Error: data/full_repos/permissive/430422543/uart/src/uart_tx.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `IDLE;\n                                ^\n%Error: Exiting due to 21 error(s)\n'
module uart_tx #(
  parameter PAYLOAD_SIZE = 8
)(
    input  wire       clk,   
    input  wire       enable, 
    input  wire       start, 
    input  wire [PAYLOAD_SIZE-1:0] in,    
    output reg        out,   
    output reg        done,  
    output reg        busy
);
    parameter BIT_WIDTH = $clog2(PAYLOAD_SIZE);
    reg [2:0] state  = `RESET;
    reg [PAYLOAD_SIZE-1:0] data   = 0; 
    reg [BIT_WIDTH-1:0] bit_index  = 0; 
    reg [BIT_WIDTH-1:0] index;

    assign index = bit_index;

    always @(posedge clk) begin
        case (state)
            default     : begin
                state   <= `IDLE;
            end
            `IDLE       : begin
                out     <= 1'b1;
                done    <= 1'b0;
                busy    <= 1'b0;
                bit_index  <= 0;
                data    <= 0;
                if (start & enable) begin
                    data    <= in; 
                    state   <= `START_BIT;
                end
            end
            `START_BIT  : begin
                out     <= 1'b0; 
                busy    <= 1'b1;
                state   <= `DATA_BIT;
            end
            `DATA_BIT  : begin 
                out     <= data[index];
                if (&bit_index) begin
                    bit_index  <= 0;
                    state   <= `STOP_BIT;
                end else begin
                    bit_index  <= bit_index + 1'b1;
                end
            end
            `STOP_BIT   : begin 
                done    <= 1'b1;
                data    <= 8'b0;
                state   <= `IDLE;
            end
        endcase
    end

endmodule
module uart_tx #(
  parameter PAYLOAD_SIZE = 8
)(
    input  wire       clk,   
    input  wire       enable, 
    input  wire       start, 
    input  wire [PAYLOAD_SIZE-1:0] in,    
    output reg        out,   
    output reg        done,  
    output reg        busy
);

    parameter BIT_WIDTH = $clog2(PAYLOAD_SIZE);
    reg [2:0] state  = `RESET;
    reg [PAYLOAD_SIZE-1:0] data   = 0; 
    reg [BIT_WIDTH-1:0] bit_index  = 0; 
    reg [BIT_WIDTH-1:0] index;

    assign index = bit_index;

    always @(posedge clk) begin
        case (state)
            default     : begin
                state   <= `IDLE;
            end
            `IDLE       : begin
                out     <= 1'b1;
                done    <= 1'b0;
                busy    <= 1'b0;
                bit_index  <= 0;
                data    <= 0;
                if (start & enable) begin
                    data    <= in; 
                    state   <= `START_BIT;
                end
            end
            `START_BIT  : begin
                out     <= 1'b0; 
                busy    <= 1'b1;
                state   <= `DATA_BIT;
            end
            `DATA_BIT  : begin 
                out     <= data[index];
                if (&bit_index) begin
                    bit_index  <= 0;
                    state   <= `STOP_BIT;
                end else begin
                    bit_index  <= bit_index + 1'b1;
                end
            end
            `STOP_BIT   : begin 
                done    <= 1'b1;
                data    <= 8'b0;
                state   <= `IDLE;
            end
        endcase
    end

endmodule