data/full_repos/permissive/458958636/verilog/rtl/cfg_shift_register.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/458958636/verilog/rtl/cfg_shift_register.v:26: Little bit endian vector: MSB < LSB of bit range: 0:31\n    output [0:31] q\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module cfg_shift_register (
    input clk,
    input din,
    output [0:31] q
);

    always @(posedge clk) begin
        q[1:31] <= q[0:30];
        q[0] <= din;
    end

endmodule
module cfg_shift_register (
    input clk,
    input din,
    output [0:31] q
);


    always @(posedge clk) begin
        q[1:31] <= q[0:30];
        q[0] <= din;
    end

endmodule