data/full_repos/permissive/494664634/AxisFifoWrite/src/hdl/AxiStreamFifoWrite.v
1: b"%Error: data/full_repos/permissive/494664634/AxisFifoWrite/src/hdl/AxiStreamFifoWrite.v:334: Cannot find file containing module: 'xpm_fifo_sync'\n  xpm_fifo_sync\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494664634/AxisFifoWrite/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync\n             data/full_repos/permissive/494664634/AxisFifoWrite/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync.v\n             data/full_repos/permissive/494664634/AxisFifoWrite/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync.sv\n             xpm_fifo_sync\n             xpm_fifo_sync.v\n             xpm_fifo_sync.sv\n             obj_dir/xpm_fifo_sync\n             obj_dir/xpm_fifo_sync.v\n             obj_dir/xpm_fifo_sync.sv\n%Error: Exiting due to 1 error(s)\n"
module AxiStreamFifoWrite(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE:M_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready
);
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  wire  fifo_almost_empty;
  wire  fifo_almost_full;
  wire  fifo_data_valid;
  wire  fifo_dbiterr;
  wire [31:0] fifo_din;
  wire [31:0] fifo_dout;
  wire  fifo_empty;
  wire  fifo_full;
  wire  fifo_injectdbiterr;
  wire  fifo_injectsbiterr;
  wire  fifo_overflow;
  wire  fifo_prog_empty;
  wire  fifo_prog_full;
  wire [9:0] fifo_rd_data_count;
  wire  fifo_rd_en;
  wire  fifo_rd_rst_busy;
  wire  fifo_rst;
  wire  fifo_sbiterr;
  wire  fifo_sleep;
  wire  fifo_underflow;
  wire  fifo_wr_ack;
  wire  fifo_wr_clk;
  wire [9:0] fifo_wr_data_count;
  wire  fifo_wr_en;
  wire  fifo_wr_rst_busy;
  wire  _T = axi_ctrl_wr_addr == 12'h8;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h8 ? axi_ctrl_wr_data : 32'h0;
  wire  _rd_data_T = ~fifo_full;
  wire [15:0] _GEN_4 = axi_ctrl_rd_addr == 12'h0 ? {{15'd0}, _rd_data_T} : 16'hdead;
  wire [15:0] _GEN_5 = axi_ctrl_rd_addr == 12'h4 ? {{6'd0}, fifo_wr_data_count} : _GEN_4;
  wire [15:0] _GEN_6 = axi_ctrl_rd_en ? _GEN_5 : 16'hdead;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  xpm_fifo_sync
    #(.RD_DATA_COUNT_WIDTH(10), .READ_DATA_WIDTH(32), .WRITE_DATA_WIDTH(32), .FIFO_WRITE_DEPTH(512), .PROG_EMPTY_THRESH(5), .READ_MODE("fwft"), .WR_DATA_COUNT_WIDTH(10), .PROG_FULL_THRESH(507), .FULL_RESET_VALUE(1), .FIFO_READ_LATENCY(1))
    fifo (
    .almost_empty(fifo_almost_empty),
    .almost_full(fifo_almost_full),
    .data_valid(fifo_data_valid),
    .dbiterr(fifo_dbiterr),
    .din(fifo_din),
    .dout(fifo_dout),
    .empty(fifo_empty),
    .full(fifo_full),
    .injectdbiterr(fifo_injectdbiterr),
    .injectsbiterr(fifo_injectsbiterr),
    .overflow(fifo_overflow),
    .prog_empty(fifo_prog_empty),
    .prog_full(fifo_prog_full),
    .rd_data_count(fifo_rd_data_count),
    .rd_en(fifo_rd_en),
    .rd_rst_busy(fifo_rd_rst_busy),
    .rst(fifo_rst),
    .sbiterr(fifo_sbiterr),
    .sleep(fifo_sleep),
    .underflow(fifo_underflow),
    .wr_ack(fifo_wr_ack),
    .wr_clk(fifo_wr_clk),
    .wr_data_count(fifo_wr_data_count),
    .wr_en(fifo_wr_en),
    .wr_rst_busy(fifo_wr_rst_busy)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign m_axis_tdata = fifo_dout;
  assign m_axis_tvalid = ~fifo_empty;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_6};
  assign fifo_din = axi_ctrl_wr_en ? _GEN_0 : 32'h0;
  assign fifo_injectdbiterr = 1'h0;
  assign fifo_injectsbiterr = 1'h0;
  assign fifo_rd_en = m_axis_tready;
  assign fifo_rst = reset;
  assign fifo_sleep = 1'h0;
  assign fifo_wr_clk = clock;
  assign fifo_wr_en = axi_ctrl_wr_en & _T;
endmodule
module AxiStreamFifoWrite(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE:M_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready
);

  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  wire  fifo_almost_empty;
  wire  fifo_almost_full;
  wire  fifo_data_valid;
  wire  fifo_dbiterr;
  wire [31:0] fifo_din;
  wire [31:0] fifo_dout;
  wire  fifo_empty;
  wire  fifo_full;
  wire  fifo_injectdbiterr;
  wire  fifo_injectsbiterr;
  wire  fifo_overflow;
  wire  fifo_prog_empty;
  wire  fifo_prog_full;
  wire [9:0] fifo_rd_data_count;
  wire  fifo_rd_en;
  wire  fifo_rd_rst_busy;
  wire  fifo_rst;
  wire  fifo_sbiterr;
  wire  fifo_sleep;
  wire  fifo_underflow;
  wire  fifo_wr_ack;
  wire  fifo_wr_clk;
  wire [9:0] fifo_wr_data_count;
  wire  fifo_wr_en;
  wire  fifo_wr_rst_busy;
  wire  _T = axi_ctrl_wr_addr == 12'h8;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h8 ? axi_ctrl_wr_data : 32'h0;
  wire  _rd_data_T = ~fifo_full;
  wire [15:0] _GEN_4 = axi_ctrl_rd_addr == 12'h0 ? {{15'd0}, _rd_data_T} : 16'hdead;
  wire [15:0] _GEN_5 = axi_ctrl_rd_addr == 12'h4 ? {{6'd0}, fifo_wr_data_count} : _GEN_4;
  wire [15:0] _GEN_6 = axi_ctrl_rd_en ? _GEN_5 : 16'hdead;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  xpm_fifo_sync
    #(.RD_DATA_COUNT_WIDTH(10), .READ_DATA_WIDTH(32), .WRITE_DATA_WIDTH(32), .FIFO_WRITE_DEPTH(512), .PROG_EMPTY_THRESH(5), .READ_MODE("fwft"), .WR_DATA_COUNT_WIDTH(10), .PROG_FULL_THRESH(507), .FULL_RESET_VALUE(1), .FIFO_READ_LATENCY(1))
    fifo (
    .almost_empty(fifo_almost_empty),
    .almost_full(fifo_almost_full),
    .data_valid(fifo_data_valid),
    .dbiterr(fifo_dbiterr),
    .din(fifo_din),
    .dout(fifo_dout),
    .empty(fifo_empty),
    .full(fifo_full),
    .injectdbiterr(fifo_injectdbiterr),
    .injectsbiterr(fifo_injectsbiterr),
    .overflow(fifo_overflow),
    .prog_empty(fifo_prog_empty),
    .prog_full(fifo_prog_full),
    .rd_data_count(fifo_rd_data_count),
    .rd_en(fifo_rd_en),
    .rd_rst_busy(fifo_rd_rst_busy),
    .rst(fifo_rst),
    .sbiterr(fifo_sbiterr),
    .sleep(fifo_sleep),
    .underflow(fifo_underflow),
    .wr_ack(fifo_wr_ack),
    .wr_clk(fifo_wr_clk),
    .wr_data_count(fifo_wr_data_count),
    .wr_en(fifo_wr_en),
    .wr_rst_busy(fifo_wr_rst_busy)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign m_axis_tdata = fifo_dout;
  assign m_axis_tvalid = ~fifo_empty;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_6};
  assign fifo_din = axi_ctrl_wr_en ? _GEN_0 : 32'h0;
  assign fifo_injectdbiterr = 1'h0;
  assign fifo_injectsbiterr = 1'h0;
  assign fifo_rd_en = m_axis_tready;
  assign fifo_rst = reset;
  assign fifo_sleep = 1'h0;
  assign fifo_wr_clk = clock;
  assign fifo_wr_en = axi_ctrl_wr_en & _T;
endmodule