data/full_repos/permissive/448780010/code/tools.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/448780010/code/tools.v:14: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'decoder_2_4\'\nmodule decoder_2_4(\n       ^~~~~~~~~~~\n                                                                       : ... Top module \'decoder_4_16\'\nmodule decoder_4_16(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'decoder_5_32\'\nmodule decoder_5_32(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'decoder_6_64\'\nmodule decoder_6_64(\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_r\'\nmodule fifo_buffer_r #(\n       ^~~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_w\'\nmodule fifo_buffer_w #(\n       ^~~~~~~~~~~~~\n                                                                       : ... Top module \'fifo_buffer_data\'\nmodule fifo_buffer_data #(\n       ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/448780010/code/tools.v:265: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'related_valid\' generates 5 bits.\n                                                                     : ... In instance fifo_buffer_data\n        assign related_valid[i] = valid[i] && (related_valid == buff[i][RELA_WIDTH - 1:0]);\n                                                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module decoder_4_16(
    input  [ 3:0] in,
    output [15:0] out
);

genvar i;
generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16
    assign out[i] = (in == i);
end endgenerate

endmodule
module decoder_4_16(
    input  [ 3:0] in,
    output [15:0] out
);


genvar i;
generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16
    assign out[i] = (in == i);
end endgenerate

endmodule