data/full_repos/permissive/517406069/verilog/rtl/counter32_by2.v
1: b"%Error: data/full_repos/permissive/517406069/verilog/rtl/counter32_by2.v:56: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module counter32_by2_module (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    input wire clk,
    input wire rst,


    input wire [31:0] debugDriver0_i,
    input wire [31:0] debugDriver1_i,
    input wire [31:0] debugDriver2_i,
    
    output wire [31:0] debugProbe0_o,
    output wire [31:0] debugProbe1_o,
    output wire [31:0] debugProbe2_o,
    
    input wire [31:0] debugControl0_i,
    input wire [31:0] debugControl1_i,
    input wire [31:0] debugControl2_i,








);

    counter #(
        .WIDTH(32),
        .INCREMENT_AMOUNT(2)
    ) counter_instance (
        .clk(clk),
        .rst(rst),

        .set_i(debugControl0_i[0]),
        .setValue_i(debugDriver0_i),
        .count_o(debugProbe0_o),
    );

endmodule
module counter32_by2_module (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    input wire clk,
    input wire rst,


    input wire [31:0] debugDriver0_i,
    input wire [31:0] debugDriver1_i,
    input wire [31:0] debugDriver2_i,
    
    output wire [31:0] debugProbe0_o,
    output wire [31:0] debugProbe1_o,
    output wire [31:0] debugProbe2_o,
    
    input wire [31:0] debugControl0_i,
    input wire [31:0] debugControl1_i,
    input wire [31:0] debugControl2_i,








);


    counter #(
        .WIDTH(32),
        .INCREMENT_AMOUNT(2)
    ) counter_instance (
        .clk(clk),
        .rst(rst),

        .set_i(debugControl0_i[0]),
        .setValue_i(debugDriver0_i),
        .count_o(debugProbe0_o),
    );

endmodule