data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b0; c=1\'b0; d=1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b0; c=1\'b1; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b0; c=1\'b1; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b1; c=1\'b0; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b1; c=1\'b0; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b1; c=1\'b1; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b1; c=1\'b1; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b0; c=1\'b0; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b0; c=1\'b0; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b0; c=1\'b1; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b0; c=1\'b1; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b1; c=1\'b0; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b1; c=1\'b0; d=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b1; c=1\'b1; d=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b1; c=1\'b1; d=1\'b1;  \n        ^\n%Error: data/full_repos/permissive/469129654/src/aoi_4inputs_testbench.v:5: Cannot find file containing module: \'and_or_invert_4inputs\'\n    and_or_invert_4inputs aoi_instance0(a, b, c, d, out);\n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/and_or_invert_4inputs\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/and_or_invert_4inputs.v\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/and_or_invert_4inputs.sv\n             and_or_invert_4inputs\n             and_or_invert_4inputs.v\n             and_or_invert_4inputs.sv\n             obj_dir/and_or_invert_4inputs\n             obj_dir/and_or_invert_4inputs.v\n             obj_dir/and_or_invert_4inputs.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module aoi_4inputs_testbench;
    reg a, b, c, d;
    wire out;

    and_or_invert_4inputs aoi_instance0(a, b, c, d, out);

    initial begin
            a=1'b0; b=1'b0; c=1'b0; d=1'b0;
        #50 a=1'b0; b=1'b0; c=1'b0; d=1'b1;
        #50 a=1'b0; b=1'b0; c=1'b1; d=1'b0;
        #50 a=1'b0; b=1'b0; c=1'b1; d=1'b1;

        #50 a=1'b0; b=1'b1; c=1'b0; d=1'b0;
        #50 a=1'b0; b=1'b1; c=1'b0; d=1'b1;
        #50 a=1'b0; b=1'b1; c=1'b1; d=1'b0;
        #50 a=1'b0; b=1'b1; c=1'b1; d=1'b1;

        #50 a=1'b1; b=1'b0; c=1'b0; d=1'b0;
        #50 a=1'b1; b=1'b0; c=1'b0; d=1'b1;
        #50 a=1'b1; b=1'b0; c=1'b1; d=1'b0;
        #50 a=1'b1; b=1'b0; c=1'b1; d=1'b1;

        #50 a=1'b1; b=1'b1; c=1'b0; d=1'b0;
        #50 a=1'b1; b=1'b1; c=1'b0; d=1'b1;
        #50 a=1'b1; b=1'b1; c=1'b1; d=1'b0;
        #50 a=1'b1; b=1'b1; c=1'b1; d=1'b1;
    end

endmodule
module aoi_4inputs_testbench;

    reg a, b, c, d;
    wire out;

    and_or_invert_4inputs aoi_instance0(a, b, c, d, out);

    initial begin
            a=1'b0; b=1'b0; c=1'b0; d=1'b0;
        #50 a=1'b0; b=1'b0; c=1'b0; d=1'b1;
        #50 a=1'b0; b=1'b0; c=1'b1; d=1'b0;
        #50 a=1'b0; b=1'b0; c=1'b1; d=1'b1;

        #50 a=1'b0; b=1'b1; c=1'b0; d=1'b0;
        #50 a=1'b0; b=1'b1; c=1'b0; d=1'b1;
        #50 a=1'b0; b=1'b1; c=1'b1; d=1'b0;
        #50 a=1'b0; b=1'b1; c=1'b1; d=1'b1;

        #50 a=1'b1; b=1'b0; c=1'b0; d=1'b0;
        #50 a=1'b1; b=1'b0; c=1'b0; d=1'b1;
        #50 a=1'b1; b=1'b0; c=1'b1; d=1'b0;
        #50 a=1'b1; b=1'b0; c=1'b1; d=1'b1;

        #50 a=1'b1; b=1'b1; c=1'b0; d=1'b0;
        #50 a=1'b1; b=1'b1; c=1'b0; d=1'b1;
        #50 a=1'b1; b=1'b1; c=1'b1; d=1'b0;
        #50 a=1'b1; b=1'b1; c=1'b1; d=1'b1;
    end

endmodule