data/full_repos/permissive/437677776/rtl/verilog/rx_hold_fifo.v
1: b'%Error: data/full_repos/permissive/437677776/rtl/verilog/rx_hold_fifo.v:39: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437677776/rtl/verilog/rx_hold_fifo.v:66: Define or directive not defined: \'`RX_HOLD_FIFO_AWIDTH\'\n  .AWIDTH (`RX_HOLD_FIFO_AWIDTH),\n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/rx_hold_fifo.v:71: Define or directive not defined: \'`MEM_AUTO_SMALL\'\n  .MEM_TYPE (`MEM_AUTO_SMALL)\n             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module rx_hold_fifo(

  rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
  rxhfifo_ralmost_empty,

  clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus,
  rxhfifo_wen, rxhfifo_ren
  );

input         clk_xgmii_rx;
input         reset_xgmii_rx_n;

input [63:0]  rxhfifo_wdata;
input [7:0]   rxhfifo_wstatus;
input         rxhfifo_wen;

input         rxhfifo_ren;

output [63:0] rxhfifo_rdata;
output [7:0]  rxhfifo_rstatus;
output        rxhfifo_rempty;
output        rxhfifo_ralmost_empty;

generic_fifo #(
  .DWIDTH (72),
  .AWIDTH (`RX_HOLD_FIFO_AWIDTH),
  .REGISTER_READ (1),
  .EARLY_READ (1),
  .CLOCK_CROSSING (0),
  .ALMOST_EMPTY_THRESH (7),
  .MEM_TYPE (`MEM_AUTO_SMALL)
)
fifo0(
    .wclk (clk_xgmii_rx),
    .wrst_n (reset_xgmii_rx_n),
    .wen (rxhfifo_wen),
    .wdata ({rxhfifo_wstatus, rxhfifo_wdata}),
    .wfull (),
    .walmost_full (),

    .rclk (clk_xgmii_rx),
    .rrst_n (reset_xgmii_rx_n),
    .ren (rxhfifo_ren),
    .rdata ({rxhfifo_rstatus, rxhfifo_rdata}),
    .rempty (rxhfifo_rempty),
    .ralmost_empty (rxhfifo_ralmost_empty)
);

   
endmodule
module rx_hold_fifo(

  rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
  rxhfifo_ralmost_empty,

  clk_xgmii_rx, reset_xgmii_rx_n, rxhfifo_wdata, rxhfifo_wstatus,
  rxhfifo_wen, rxhfifo_ren
  );


input         clk_xgmii_rx;
input         reset_xgmii_rx_n;

input [63:0]  rxhfifo_wdata;
input [7:0]   rxhfifo_wstatus;
input         rxhfifo_wen;

input         rxhfifo_ren;

output [63:0] rxhfifo_rdata;
output [7:0]  rxhfifo_rstatus;
output        rxhfifo_rempty;
output        rxhfifo_ralmost_empty;

generic_fifo #(
  .DWIDTH (72),
  .AWIDTH (`RX_HOLD_FIFO_AWIDTH),
  .REGISTER_READ (1),
  .EARLY_READ (1),
  .CLOCK_CROSSING (0),
  .ALMOST_EMPTY_THRESH (7),
  .MEM_TYPE (`MEM_AUTO_SMALL)
)
fifo0(
    .wclk (clk_xgmii_rx),
    .wrst_n (reset_xgmii_rx_n),
    .wen (rxhfifo_wen),
    .wdata ({rxhfifo_wstatus, rxhfifo_wdata}),
    .wfull (),
    .walmost_full (),

    .rclk (clk_xgmii_rx),
    .rrst_n (reset_xgmii_rx_n),
    .ren (rxhfifo_ren),
    .rdata ({rxhfifo_rstatus, rxhfifo_rdata}),
    .rempty (rxhfifo_rempty),
    .ralmost_empty (rxhfifo_ralmost_empty)
);

   
endmodule