data/full_repos/permissive/493441306/Verilog Language/modules_hierarchy/08_moduleaddsub.v
1: b'%Error: Cannot find file containing module: Language/modules_hierarchy,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             Language/modules_hierarchy,data/full_repos/permissive/493441306\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/modules_hierarchy/08_moduleaddsub.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

    wire c;

    add16 addL ( .a(a[15:0]), .b( b[15:0] ^ {16{sub}} ), .sum(sum[15:0]), .cin(sub), .cout(c) );
    add16 addH ( .a(a[31:16]), .b( b[31:16] ^ {16{sub}} ), .sum(sum[31:16]), .cin(c) );

endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);


    wire c;

    add16 addL ( .a(a[15:0]), .b( b[15:0] ^ {16{sub}} ), .sum(sum[15:0]), .cin(sub), .cout(c) );
    add16 addH ( .a(a[31:16]), .b( b[31:16] ^ {16{sub}} ), .sum(sum[31:16]), .cin(c) );

endmodule