data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:167: Signal definition not found, creating implicitly: \'equal\'\n    assign equal = (regReadData1_ID == regReadData2_ID);\n           ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:88: Cannot find file containing module: \'MUX_4x1\'\n    MUX_4x1 pcSrc_mux(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490649362/pipeline/src,data/full_repos/permissive/490649362/MUX_4x1\n             data/full_repos/permissive/490649362/pipeline/src,data/full_repos/permissive/490649362/MUX_4x1.v\n             data/full_repos/permissive/490649362/pipeline/src,data/full_repos/permissive/490649362/MUX_4x1.sv\n             MUX_4x1\n             MUX_4x1.v\n             MUX_4x1.sv\n             obj_dir/MUX_4x1\n             obj_dir/MUX_4x1.v\n             obj_dir/MUX_4x1.sv\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:95: Cannot find file containing module: \'PC\'\n    PC pc(\n    ^~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:102: Cannot find file containing module: \'Inst_Mem\'\n    Inst_Mem im(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:108: Cannot find file containing module: \'IF_ID\'\n    IF_ID ifid(\n    ^~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:124: Cannot find file containing module: \'Hazard_Detection\'\n    Hazard_Detection hazard_detect(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:139: Cannot find file containing module: \'Control\'\n    Control control(\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:151: Cannot find file containing module: \'Reg_File_32\'\n    Reg_File_32 rf(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:161: Cannot find file containing module: \'Sign_Extend\'\n    Sign_Extend signextend(\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:166: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 30 bits.\n                                                                                    : ... In instance Pipeline_CPU\n    assign jump_addr = {pcAdd4_ID[31:28], (inst_ID[25:0] << 2)};\n                     ^\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:168: Cannot find file containing module: \'Branch_Detection\'\n    Branch_Detection branch_detect(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:179: Cannot find file containing module: \'ID_EX\'\n    ID_EX idex(\n    ^~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:212: Cannot find file containing module: \'ALU_32\'\n    ALU_32 alu(\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:219: Cannot find file containing module: \'MUX_4x1\'\n    MUX_4x1 forwardA_mux(\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:226: Cannot find file containing module: \'MUX_4x1\'\n    MUX_4x1 forwardB_mux(\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:234: Cannot find file containing module: \'ALU_control\'\n    ALU_control alu_ctrl(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:239: Cannot find file containing module: \'Forwarding\'\n    Forwarding forward(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:254: Cannot find file containing module: \'EX_MEM\'\n    EX_MEM exmem(\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:274: Cannot find file containing module: \'Data_Mem\'\n    Data_Mem dm(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/490649362/pipeline/src/Pipeline_CPU.v:284: Cannot find file containing module: \'MEM_WB\'\n    MEM_WB memwb(\n    ^~~~~~\n%Error: Exiting due to 18 error(s), 2 warning(s)\n'
module Pipeline_CPU(clk);


    input clk;

    wire    [31:0]  pcIn_IF,
                    pcOut_IF,
                    pcAdd4_IF,
                    inst_IF;
    wire            IFID_Write,
                    IF_Flush;


    wire            isBranch,
                    Jump;
    wire    [31:0]  jump_addr,
                    branch_addr;
    wire    [31:0]  pcAdd4_ID,
                    inst_ID;

    wire    [4:0]   Rs_ID,
                    Rt_ID,
                    Rd_ID;
    wire    [5:0]   opcode,
                    funct;
    wire            Branch,
                    Hazard,
                    PCWrite;
    wire    [1:0]   ALUOp_ID;
    wire            RegDst_ID,
                    ALUSrc_ID,
                    MemRead_ID,
                    MemWrite_ID,
                    MemtoReg_ID,
                    RegWrite_ID;
    wire    [31:0]  regReadData1_ID,
                    regReadData2_ID;
    wire    [31:0]  signExtend_ID;


    wire    [1:0]   ALUOp_EX;
    wire            RegDst_EX,
                    ALUSrc_EX,
                    MemRead_EX,
                    MemWrite_EX,
                    MemtoReg_EX,
                    RegWrite_EX;
    wire    [31:0]  regReadData1_EX,
                    regReadData2_EX,
                    signExtend_EX;
    wire    [4:0]   Rs_EX,
                    Rt_EX,
                    Rd_EX,
                    Dst_EX;

    wire    [1:0]   ForwardA,
                    ForwardB;
    wire    [31:0]  aluInA_EX,
                    aluInB_EX,
                    ForwardBOut_EX,
                    ALUResult_EX;
    wire    [3:0]   aluControl_EX;
    wire            aluzero_EX;


    wire            MemRead_MEM,
                    MemWrite_MEM,
                    MemtoReg_MEM,
                    RegWrite_MEM;
    wire    [31:0]  ALUResult_MEM,
                    ForwardBOut_MEM,
                    dmReadData_MEM;
    wire    [4:0]   Dst_MEM;


    wire            MemtoReg_WB,
                    RegWrite_WB;
    wire    [31:0]  dmReadData_WB,
                    ALUResult_WB,
                    regWriteData_WB;
    wire    [4:0]   Dst_WB;



    MUX_4x1 pcSrc_mux(
                .A0(pcAdd4_IF),
                .A1(jump_addr),
                .A2(branch_addr),
                .sel({isBranch,Jump}),
                .F(pcIn_IF)
            );
    PC pc(
           .clk(clk),
           .in(pcIn_IF),
           .out(pcOut_IF),
           .PCWrite(PCWrite)
       );
    assign pcAdd4_IF = pcOut_IF + 4;
    Inst_Mem im(
                 .R_addr(pcOut_IF),
                 .inst(inst_IF)
             );


    IF_ID ifid(
              .clk(clk),
              .IFID_Write(IFID_Write),
              .IF_Flush(IF_Flush),
              .pcAdd4_IF(pcAdd4_IF),
              .inst_IF(inst_IF),
              .pcAdd4_ID(pcAdd4_ID),
              .inst_ID(inst_ID)
          );


    assign opcode = inst_ID[31:26];
    assign Rs_ID = inst_ID[25:21];
    assign Rt_ID = inst_ID[20:16];
    assign Rd_ID = inst_ID[15:11];
    assign funct = inst_ID[5:0];
    Hazard_Detection hazard_detect(
                         .Branch(Branch),
                         .MemRead_EX(MemRead_EX),
                         .RegWrite_EX(RegWrite_EX),
                         .RegWrite_MEM(RegWrite_MEM),
                         .MemRead_MEM(MemRead_MEM),
                         .Rs_ID(Rs_ID),
                         .Rt_ID(Rt_ID),
                         .Rt_EX(Rt_EX),
                         .Rd_EX(Rd_EX),
                         .Dst_MEM(Dst_MEM),
                         .IFID_Write(IFID_Write),
                         .Hazard(Hazard),
                         .PC_Write(PCWrite)
                     );
    Control control(
                .inst_31_26(opcode),
                .RegDst(RegDst_ID),
                .Jump(Jump),
                .Branch(Branch),
                .MemRead(MemRead_ID),
                .MemtoReg(MemtoReg_ID),
                .ALUOp(ALUOp_ID),
                .MemWrite(MemWrite_ID),
                .ALUSrc(ALUSrc_ID),
                .RegWrite(RegWrite_ID)
            );
    Reg_File_32 rf(
                    .clk(clk),
                    .R_reg1(Rs_ID),
                    .R_reg2(Rt_ID),
                    .W_reg(Dst_WB),
                    .W_data(regWriteData_WB),
                    .R_data1(regReadData1_ID),
                    .R_data2(regReadData2_ID),
                    .RegWrite(RegWrite_WB)
                );
    Sign_Extend signextend(
                    .in(inst_ID[15:0]),
                    .out(signExtend_ID)
                );
    assign branch_addr = (signExtend_ID << 2) + pcAdd4_ID;
    assign jump_addr = {pcAdd4_ID[31:28], (inst_ID[25:0] << 2)};
    assign equal = (regReadData1_ID == regReadData2_ID);
    Branch_Detection branch_detect(
                         .Branch(Branch),
                         .equal(equal),
                         .Hazard(Hazard),
                         .Jump(Jump),
                         .opcode(opcode),
                         .isBranch(isBranch),
                         .IF_Flush(IF_Flush)
                     );


    ID_EX idex(
              .clk(clk),
              .Hazard(Hazard),
              .ALUOp_ID(ALUOp_ID),
              .RegDst_ID(RegDst_ID),
              .ALUSrc_ID(ALUSrc_ID),
              .MemRead_ID(MemRead_ID),
              .MemWrite_ID(MemWrite_ID),
              .MemtoReg_ID(MemtoReg_ID),
              .RegWrite_ID(RegWrite_ID),
              .regReadData1_ID(regReadData1_ID),
              .regReadData2_ID(regReadData2_ID),
              .signExtend_ID(signExtend_ID),
              .Rs_ID(Rs_ID),
              .Rt_ID(Rt_ID),
              .Rd_ID(Rd_ID),

              .ALUOp_EX(ALUOp_EX),
              .RegDst_EX(RegDst_EX),
              .ALUSrc_EX(ALUSrc_EX),
              .MemRead_EX(MemRead_EX),
              .MemWrite_EX(MemWrite_EX),
              .MemtoReg_EX(MemtoReg_EX),
              .RegWrite_EX(RegWrite_EX),
              .regReadData1_EX(regReadData1_EX),
              .regReadData2_EX(regReadData2_EX),
              .signExtend_EX(signExtend_EX),
              .Rs_EX(Rs_EX),
              .Rt_EX(Rt_EX),
              .Rd_EX(Rd_EX)
          );


    ALU_32 alu(
               .A(aluInA_EX),
               .B(aluInB_EX),
               .alu_control(aluControl_EX),
               .zero(aluzero_EX),
               .result(ALUResult_EX)
           );
    MUX_4x1 forwardA_mux(
                .A0(regReadData1_EX),
                .A1(regWriteData_WB),
                .A2(ALUResult_MEM),
                .sel(ForwardA),
                .F(aluInA_EX)
            );
    MUX_4x1 forwardB_mux(
                .A0(regReadData2_EX),
                .A1(regWriteData_WB),
                .A2(ALUResult_MEM),
                .sel(ForwardB),
                .F(ForwardBOut_EX)
            );
    assign aluInB_EX = ALUSrc_EX ? signExtend_EX : ForwardBOut_EX;
    ALU_control alu_ctrl(
                    .funct(signExtend_EX[5:0]),
                    .ALUOp(ALUOp_EX),
                    .alu_control(aluControl_EX)
                );
    Forwarding forward(
                   .Rs_ID(Rs_ID),
                   .Rt_ID(Rt_ID),
                   .Rs_EX(Rs_EX),
                   .Rt_EX(Rt_EX),
                   .Dst_MEM(Dst_MEM),
                   .Dst_WB(Dst_WB),
                   .RegWrite_MEM(RegWrite_MEM),
                   .RegWrite_WB(RegWrite_WB),
                   .ForwardA(ForwardA),
                   .ForwardB(ForwardB)
               );
    assign Dst_EX = RegDst_EX ? Rd_EX : Rt_EX;


    EX_MEM exmem(
               .clk(clk),
               .MemRead_EX(MemRead_EX),
               .MemWrite_EX(MemWrite_EX),
               .MemtoReg_EX(MemtoReg_EX),
               .RegWrite_EX(RegWrite_EX),
               .ALUResult_EX(ALUResult_EX),
               .ForwardBOut_EX(ForwardBOut_EX),
               .Dst_EX(Dst_EX),

               .MemRead_MEM(MemRead_MEM),
               .MemWrite_MEM(MemWrite_MEM),
               .MemtoReg_MEM(MemtoReg_MEM),
               .RegWrite_MEM(RegWrite_MEM),
               .ALUResult_MEM(ALUResult_MEM),
               .ForwardBOut_MEM(ForwardBOut_MEM),
               .Dst_MEM(Dst_MEM)
           );


    Data_Mem dm(
                 .clk(clk),
                 .addr(ALUResult_MEM),
                 .W_data(ForwardBOut_MEM),
                 .R_data(dmReadData_MEM),
                 .MemWrite(MemWrite_MEM),
                 .MemRead(MemRead_MEM)
             );


    MEM_WB memwb(
               .clk(clk),
               .MemtoReg_MEM(MemtoReg_MEM),
               .RegWrite_MEM(RegWrite_MEM),
               .dmReadData_MEM(dmReadData_MEM),
               .ALUResult_MEM(ALUResult_MEM),
               .Dst_MEM(Dst_MEM),

               .MemtoReg_WB(MemtoReg_WB),
               .RegWrite_WB(RegWrite_WB),
               .dmReadData_WB(dmReadData_WB),
               .ALUResult_WB(ALUResult_WB),
               .Dst_WB(Dst_WB)
           );


    assign regWriteData_WB = MemtoReg_WB ? dmReadData_WB : ALUResult_WB;


endmodule
module Pipeline_CPU(clk);



    input clk;

    wire    [31:0]  pcIn_IF,
                    pcOut_IF,
                    pcAdd4_IF,
                    inst_IF;
    wire            IFID_Write,
                    IF_Flush;


    wire            isBranch,
                    Jump;
    wire    [31:0]  jump_addr,
                    branch_addr;
    wire    [31:0]  pcAdd4_ID,
                    inst_ID;

    wire    [4:0]   Rs_ID,
                    Rt_ID,
                    Rd_ID;
    wire    [5:0]   opcode,
                    funct;
    wire            Branch,
                    Hazard,
                    PCWrite;
    wire    [1:0]   ALUOp_ID;
    wire            RegDst_ID,
                    ALUSrc_ID,
                    MemRead_ID,
                    MemWrite_ID,
                    MemtoReg_ID,
                    RegWrite_ID;
    wire    [31:0]  regReadData1_ID,
                    regReadData2_ID;
    wire    [31:0]  signExtend_ID;


    wire    [1:0]   ALUOp_EX;
    wire            RegDst_EX,
                    ALUSrc_EX,
                    MemRead_EX,
                    MemWrite_EX,
                    MemtoReg_EX,
                    RegWrite_EX;
    wire    [31:0]  regReadData1_EX,
                    regReadData2_EX,
                    signExtend_EX;
    wire    [4:0]   Rs_EX,
                    Rt_EX,
                    Rd_EX,
                    Dst_EX;

    wire    [1:0]   ForwardA,
                    ForwardB;
    wire    [31:0]  aluInA_EX,
                    aluInB_EX,
                    ForwardBOut_EX,
                    ALUResult_EX;
    wire    [3:0]   aluControl_EX;
    wire            aluzero_EX;


    wire            MemRead_MEM,
                    MemWrite_MEM,
                    MemtoReg_MEM,
                    RegWrite_MEM;
    wire    [31:0]  ALUResult_MEM,
                    ForwardBOut_MEM,
                    dmReadData_MEM;
    wire    [4:0]   Dst_MEM;


    wire            MemtoReg_WB,
                    RegWrite_WB;
    wire    [31:0]  dmReadData_WB,
                    ALUResult_WB,
                    regWriteData_WB;
    wire    [4:0]   Dst_WB;



    MUX_4x1 pcSrc_mux(
                .A0(pcAdd4_IF),
                .A1(jump_addr),
                .A2(branch_addr),
                .sel({isBranch,Jump}),
                .F(pcIn_IF)
            );
    PC pc(
           .clk(clk),
           .in(pcIn_IF),
           .out(pcOut_IF),
           .PCWrite(PCWrite)
       );
    assign pcAdd4_IF = pcOut_IF + 4;
    Inst_Mem im(
                 .R_addr(pcOut_IF),
                 .inst(inst_IF)
             );


    IF_ID ifid(
              .clk(clk),
              .IFID_Write(IFID_Write),
              .IF_Flush(IF_Flush),
              .pcAdd4_IF(pcAdd4_IF),
              .inst_IF(inst_IF),
              .pcAdd4_ID(pcAdd4_ID),
              .inst_ID(inst_ID)
          );


    assign opcode = inst_ID[31:26];
    assign Rs_ID = inst_ID[25:21];
    assign Rt_ID = inst_ID[20:16];
    assign Rd_ID = inst_ID[15:11];
    assign funct = inst_ID[5:0];
    Hazard_Detection hazard_detect(
                         .Branch(Branch),
                         .MemRead_EX(MemRead_EX),
                         .RegWrite_EX(RegWrite_EX),
                         .RegWrite_MEM(RegWrite_MEM),
                         .MemRead_MEM(MemRead_MEM),
                         .Rs_ID(Rs_ID),
                         .Rt_ID(Rt_ID),
                         .Rt_EX(Rt_EX),
                         .Rd_EX(Rd_EX),
                         .Dst_MEM(Dst_MEM),
                         .IFID_Write(IFID_Write),
                         .Hazard(Hazard),
                         .PC_Write(PCWrite)
                     );
    Control control(
                .inst_31_26(opcode),
                .RegDst(RegDst_ID),
                .Jump(Jump),
                .Branch(Branch),
                .MemRead(MemRead_ID),
                .MemtoReg(MemtoReg_ID),
                .ALUOp(ALUOp_ID),
                .MemWrite(MemWrite_ID),
                .ALUSrc(ALUSrc_ID),
                .RegWrite(RegWrite_ID)
            );
    Reg_File_32 rf(
                    .clk(clk),
                    .R_reg1(Rs_ID),
                    .R_reg2(Rt_ID),
                    .W_reg(Dst_WB),
                    .W_data(regWriteData_WB),
                    .R_data1(regReadData1_ID),
                    .R_data2(regReadData2_ID),
                    .RegWrite(RegWrite_WB)
                );
    Sign_Extend signextend(
                    .in(inst_ID[15:0]),
                    .out(signExtend_ID)
                );
    assign branch_addr = (signExtend_ID << 2) + pcAdd4_ID;
    assign jump_addr = {pcAdd4_ID[31:28], (inst_ID[25:0] << 2)};
    assign equal = (regReadData1_ID == regReadData2_ID);
    Branch_Detection branch_detect(
                         .Branch(Branch),
                         .equal(equal),
                         .Hazard(Hazard),
                         .Jump(Jump),
                         .opcode(opcode),
                         .isBranch(isBranch),
                         .IF_Flush(IF_Flush)
                     );


    ID_EX idex(
              .clk(clk),
              .Hazard(Hazard),
              .ALUOp_ID(ALUOp_ID),
              .RegDst_ID(RegDst_ID),
              .ALUSrc_ID(ALUSrc_ID),
              .MemRead_ID(MemRead_ID),
              .MemWrite_ID(MemWrite_ID),
              .MemtoReg_ID(MemtoReg_ID),
              .RegWrite_ID(RegWrite_ID),
              .regReadData1_ID(regReadData1_ID),
              .regReadData2_ID(regReadData2_ID),
              .signExtend_ID(signExtend_ID),
              .Rs_ID(Rs_ID),
              .Rt_ID(Rt_ID),
              .Rd_ID(Rd_ID),

              .ALUOp_EX(ALUOp_EX),
              .RegDst_EX(RegDst_EX),
              .ALUSrc_EX(ALUSrc_EX),
              .MemRead_EX(MemRead_EX),
              .MemWrite_EX(MemWrite_EX),
              .MemtoReg_EX(MemtoReg_EX),
              .RegWrite_EX(RegWrite_EX),
              .regReadData1_EX(regReadData1_EX),
              .regReadData2_EX(regReadData2_EX),
              .signExtend_EX(signExtend_EX),
              .Rs_EX(Rs_EX),
              .Rt_EX(Rt_EX),
              .Rd_EX(Rd_EX)
          );


    ALU_32 alu(
               .A(aluInA_EX),
               .B(aluInB_EX),
               .alu_control(aluControl_EX),
               .zero(aluzero_EX),
               .result(ALUResult_EX)
           );
    MUX_4x1 forwardA_mux(
                .A0(regReadData1_EX),
                .A1(regWriteData_WB),
                .A2(ALUResult_MEM),
                .sel(ForwardA),
                .F(aluInA_EX)
            );
    MUX_4x1 forwardB_mux(
                .A0(regReadData2_EX),
                .A1(regWriteData_WB),
                .A2(ALUResult_MEM),
                .sel(ForwardB),
                .F(ForwardBOut_EX)
            );
    assign aluInB_EX = ALUSrc_EX ? signExtend_EX : ForwardBOut_EX;
    ALU_control alu_ctrl(
                    .funct(signExtend_EX[5:0]),
                    .ALUOp(ALUOp_EX),
                    .alu_control(aluControl_EX)
                );
    Forwarding forward(
                   .Rs_ID(Rs_ID),
                   .Rt_ID(Rt_ID),
                   .Rs_EX(Rs_EX),
                   .Rt_EX(Rt_EX),
                   .Dst_MEM(Dst_MEM),
                   .Dst_WB(Dst_WB),
                   .RegWrite_MEM(RegWrite_MEM),
                   .RegWrite_WB(RegWrite_WB),
                   .ForwardA(ForwardA),
                   .ForwardB(ForwardB)
               );
    assign Dst_EX = RegDst_EX ? Rd_EX : Rt_EX;


    EX_MEM exmem(
               .clk(clk),
               .MemRead_EX(MemRead_EX),
               .MemWrite_EX(MemWrite_EX),
               .MemtoReg_EX(MemtoReg_EX),
               .RegWrite_EX(RegWrite_EX),
               .ALUResult_EX(ALUResult_EX),
               .ForwardBOut_EX(ForwardBOut_EX),
               .Dst_EX(Dst_EX),

               .MemRead_MEM(MemRead_MEM),
               .MemWrite_MEM(MemWrite_MEM),
               .MemtoReg_MEM(MemtoReg_MEM),
               .RegWrite_MEM(RegWrite_MEM),
               .ALUResult_MEM(ALUResult_MEM),
               .ForwardBOut_MEM(ForwardBOut_MEM),
               .Dst_MEM(Dst_MEM)
           );


    Data_Mem dm(
                 .clk(clk),
                 .addr(ALUResult_MEM),
                 .W_data(ForwardBOut_MEM),
                 .R_data(dmReadData_MEM),
                 .MemWrite(MemWrite_MEM),
                 .MemRead(MemRead_MEM)
             );


    MEM_WB memwb(
               .clk(clk),
               .MemtoReg_MEM(MemtoReg_MEM),
               .RegWrite_MEM(RegWrite_MEM),
               .dmReadData_MEM(dmReadData_MEM),
               .ALUResult_MEM(ALUResult_MEM),
               .Dst_MEM(Dst_MEM),

               .MemtoReg_WB(MemtoReg_WB),
               .RegWrite_WB(RegWrite_WB),
               .dmReadData_WB(dmReadData_WB),
               .ALUResult_WB(ALUResult_WB),
               .Dst_WB(Dst_WB)
           );


    assign regWriteData_WB = MemtoReg_WB ? dmReadData_WB : ALUResult_WB;


endmodule