data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool/maxpool_top.v
1: b"%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool/maxpool_top.v:84: Cannot find file containing module: 'maxpool_poolturn'\nmaxpool_poolturn #(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool,data/full_repos/permissive/514467334/maxpool_poolturn\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool,data/full_repos/permissive/514467334/maxpool_poolturn.v\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool,data/full_repos/permissive/514467334/maxpool_poolturn.sv\n             maxpool_poolturn\n             maxpool_poolturn.v\n             maxpool_poolturn.sv\n             obj_dir/maxpool_poolturn\n             obj_dir/maxpool_poolturn.v\n             obj_dir/maxpool_poolturn.sv\n%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool/maxpool_top.v:110: Cannot find file containing module: 'maxpool_pick'\nmaxpool_pick #(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/MaxPool/maxpool_top.v:135: Cannot find file containing module: 'maxpool_compare'\nmaxpool_compare #(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module maxpool_top #(
    parameter datai_width = 4,
    parameter datai_height = 4,

    parameter kernel_width = 2,
    parameter kernel_height = 2,
    parameter stride = 2,

    parameter padding_en =0,
    parameter padding = 0,
  
    parameter datao_width = ((datai_width-kernel_width+2*padding)/stride)+1,
    parameter datao_height = ((datai_height-kernel_height+2*padding)/stride)+1,

    parameter bitwidth = 3
) (
    input clk_en,
    input reset_n,
    
    input work_en,
    input [datai_width*datai_height*bitwidth-1:0] data_i,
    
    output [datao_width*datao_height*bitwidth-1:0] data_o,
    output work_fin
);

reg state;
localparam IDLE = 0;
localparam BUSY = 1;

wire all_fin;
wire pool_on;
reg rpool_on;
reg rpool_fin;
assign pool_on = rpool_on;
assign work_fin = rpool_fin;
always @(posedge clk_en ) begin
    if(!reset_n)begin
        state<=0;
        rpool_on<=0;
        rpool_fin<=0;
    end
    else begin
        case (state)
            IDLE:begin
                if(work_en)begin
                    state<=BUSY;
                    rpool_on <= 1;
                    rpool_fin <= 0;
                end
                else begin
                    state<=state;
                    rpool_fin<=rpool_fin;
                    rpool_on<=rpool_on;
                end
            end
            BUSY:begin
                if(all_fin)begin
                    state <= IDLE;
                    rpool_fin<= 1;
                    rpool_on<=0;
                end
                else begin
                    state <= state;
                    rpool_fin<=rpool_fin;
                    rpool_on<=rpool_on;
                end
            end
        endcase
    end
end

wire [3:0] data_l;
wire [3:0] data_c;
wire [3:0] resu_l;
wire [3:0] resu_c;

wire part_fin;
wire turn_fin;

wire [bitwidth-1:0] data;


maxpool_poolturn #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth
)maxpool_poolturn_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),

    .data_l     (data_l),
    .data_c     (data_c),
    .resu_l     (resu_l),
    .resu_c     (resu_c),

    .part_fin   (part_fin),
    .turn_fin   (turn_fin)
);


maxpool_pick #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth  
)maxpool_pick_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),

    .data_i     (data_i),

    .data_l     (data_l),
    .data_c     (data_c),

    .data_o     (data)
);


maxpool_compare #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth  
)maxpool_compare_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),
    .part_fin   (part_fin),
    .turn_fin   (turn_fin),

    .data       (data),
    .resu_l     (resu_l),
    .resu_c     (resu_c),

    .data_o     (data_o),
    .all_fin    (all_fin)
);


    
endmodule
module maxpool_top #(
    parameter datai_width = 4,
    parameter datai_height = 4,

    parameter kernel_width = 2,
    parameter kernel_height = 2,
    parameter stride = 2,

    parameter padding_en =0,
    parameter padding = 0,
  
    parameter datao_width = ((datai_width-kernel_width+2*padding)/stride)+1,
    parameter datao_height = ((datai_height-kernel_height+2*padding)/stride)+1,

    parameter bitwidth = 3
) (
    input clk_en,
    input reset_n,
    
    input work_en,
    input [datai_width*datai_height*bitwidth-1:0] data_i,
    
    output [datao_width*datao_height*bitwidth-1:0] data_o,
    output work_fin
);


reg state;
localparam IDLE = 0;
localparam BUSY = 1;

wire all_fin;
wire pool_on;
reg rpool_on;
reg rpool_fin;
assign pool_on = rpool_on;
assign work_fin = rpool_fin;
always @(posedge clk_en ) begin
    if(!reset_n)begin
        state<=0;
        rpool_on<=0;
        rpool_fin<=0;
    end
    else begin
        case (state)
            IDLE:begin
                if(work_en)begin
                    state<=BUSY;
                    rpool_on <= 1;
                    rpool_fin <= 0;
                end
                else begin
                    state<=state;
                    rpool_fin<=rpool_fin;
                    rpool_on<=rpool_on;
                end
            end
            BUSY:begin
                if(all_fin)begin
                    state <= IDLE;
                    rpool_fin<= 1;
                    rpool_on<=0;
                end
                else begin
                    state <= state;
                    rpool_fin<=rpool_fin;
                    rpool_on<=rpool_on;
                end
            end
        endcase
    end
end

wire [3:0] data_l;
wire [3:0] data_c;
wire [3:0] resu_l;
wire [3:0] resu_c;

wire part_fin;
wire turn_fin;

wire [bitwidth-1:0] data;


maxpool_poolturn #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth
)maxpool_poolturn_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),

    .data_l     (data_l),
    .data_c     (data_c),
    .resu_l     (resu_l),
    .resu_c     (resu_c),

    .part_fin   (part_fin),
    .turn_fin   (turn_fin)
);


maxpool_pick #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth  
)maxpool_pick_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),

    .data_i     (data_i),

    .data_l     (data_l),
    .data_c     (data_c),

    .data_o     (data)
);


maxpool_compare #(
    datai_width,
    datai_height,
    kernel_width,
    kernel_height,
    stride,
    padding_en,
    padding,
    datao_width,
    datao_height,
    bitwidth  
)maxpool_compare_inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .pool_on    (pool_on),
    .part_fin   (part_fin),
    .turn_fin   (turn_fin),

    .data       (data),
    .resu_l     (resu_l),
    .resu_c     (resu_c),

    .data_o     (data_o),
    .all_fin    (all_fin)
);


    
endmodule