data/full_repos/permissive/42434302/ivltests/br937.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/br937.v:3: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\nlocalparam [8*8:0] expect = "0123456789";\n                   ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/br937.v:3: syntax error, unexpected \'=\', expecting IDENTIFIER\nlocalparam [8*8:0] expect = "0123456789";\n                          ^\n%Error: data/full_repos/permissive/42434302/ivltests/br937.v:11: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n  if (passed && (str == expect))\n                        ^~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/br937.v:11: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (passed && (str == expect))\n                              ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

localparam [8*8:0] expect = "0123456789";

reg [8*8:0] str;
reg passed;

initial begin
  passed = $value$plusargs("string=%s", str);
  $display("%h", str);
  if (passed && (str == expect))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module top;


localparam [8*8:0] expect = "0123456789";

reg [8*8:0] str;
reg passed;

initial begin
  passed = $value$plusargs("string=%s", str);
  $display("%h", str);
  if (passed && (str == expect))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule