data/full_repos/permissive/42061259/Proyecto 1/FIFO_LIFO/ram.v
1: b'%Error: Cannot find file containing module: 1/FIFO_LIFO,data/full_repos/permissive/42061259\n        ... Looked in:\n             data/full_repos/permissive/42061259/Proyecto/1/FIFO_LIFO,data/full_repos/permissive/42061259\n             data/full_repos/permissive/42061259/Proyecto/1/FIFO_LIFO,data/full_repos/permissive/42061259.v\n             data/full_repos/permissive/42061259/Proyecto/1/FIFO_LIFO,data/full_repos/permissive/42061259.sv\n             1/FIFO_LIFO,data/full_repos/permissive/42061259\n             1/FIFO_LIFO,data/full_repos/permissive/42061259.v\n             1/FIFO_LIFO,data/full_repos/permissive/42061259.sv\n             obj_dir/1/FIFO_LIFO,data/full_repos/permissive/42061259\n             obj_dir/1/FIFO_LIFO,data/full_repos/permissive/42061259.v\n             obj_dir/1/FIFO_LIFO,data/full_repos/permissive/42061259.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/42061259/Proyecto\n%Error: Cannot find file containing module: 1/FIFO_LIFO/ram.v\n%Error: Exiting due to 3 error(s)\n'
module ram (dat_i, dat_o, adr_wr_i, adr_rd_i, we_i, rde_i, clk );

   parameter dat_width = 32;
   parameter adr_width = 6;
   parameter mem_size  = 64;
   
   input [dat_width-1:0]      dat_i;
   input [adr_width-1:0]      adr_rd_i;
   input [adr_width-1:0]      adr_wr_i;
   input 		      we_i;
   input 		      rde_i; 
   output reg [dat_width-1:0] dat_o;
   input 		      clk;   
  
   reg [dat_width-1:0] ram [0:mem_size - 1]; 
   
   always @ (posedge clk)
     begin 
       	if (we_i)
	  ram[adr_wr_i] <= dat_i;
     end 

   always @ (posedge clk)
     begin 
        if (rde_i)
	  dat_o <= ram[adr_rd_i];
     end
endmodule
module ram (dat_i, dat_o, adr_wr_i, adr_rd_i, we_i, rde_i, clk );


   parameter dat_width = 32;
   parameter adr_width = 6;
   parameter mem_size  = 64;
   
   input [dat_width-1:0]      dat_i;
   input [adr_width-1:0]      adr_rd_i;
   input [adr_width-1:0]      adr_wr_i;
   input 		      we_i;
   input 		      rde_i; 
   output reg [dat_width-1:0] dat_o;
   input 		      clk;   
  
   reg [dat_width-1:0] ram [0:mem_size - 1]; 
   
   always @ (posedge clk)
     begin 
       	if (we_i)
	  ram[adr_wr_i] <= dat_i;
     end 

   always @ (posedge clk)
     begin 
        if (rde_i)
	  dat_o <= ram[adr_rd_i];
     end
endmodule