data/full_repos/permissive/466874195/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/466874195/verilog/rtl/user_proj_example.v:85: Cannot find file containing module: 'wb_calc_e'\n    wb_calc_e #\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/wb_calc_e\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/wb_calc_e.v\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/wb_calc_e.sv\n             wb_calc_e\n             wb_calc_e.v\n             wb_calc_e.sv\n             obj_dir/wb_calc_e\n             obj_dir/wb_calc_e.v\n             obj_dir/wb_calc_e.sv\n%Error: Exiting due to 1 error(s)\n"
module user_proj_example #(
    parameter SEQ_WIDTH = 64,
    parameter E_WIDTH = 20,

    parameter STAGE_WIDTH = 8,
    parameter PARALLEL_UNITS = 1
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    output [2:0] irq
);
    wire clk;
    wire rst;


    assign irq = 3'b000;






    assign clk = wb_clk_i;
    assign rst = wb_rst_i;


    wb_calc_e #
    (
        .SEQ_WIDTH(SEQ_WIDTH),
        .E_WIDTH(E_WIDTH),

        .STAGE_WIDTH(STAGE_WIDTH)
    ) inst_wb_calc_e (
        .wb_clk_i(clk),
        .wb_rst_i(rst),

        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),

        .wbs_we_i(wbs_we_i),
        .wbs_sel_i(wbs_sel_i),

        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),

        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),

        .la_data_in(la_data_in),
        .la_data_out(la_data_out),
        .la_oenb(la_oenb)
    );
    

endmodule
module user_proj_example #(
    parameter SEQ_WIDTH = 64,
    parameter E_WIDTH = 20,

    parameter STAGE_WIDTH = 8,
    parameter PARALLEL_UNITS = 1
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    output [2:0] irq
);

    wire clk;
    wire rst;


    assign irq = 3'b000;






    assign clk = wb_clk_i;
    assign rst = wb_rst_i;


    wb_calc_e #
    (
        .SEQ_WIDTH(SEQ_WIDTH),
        .E_WIDTH(E_WIDTH),

        .STAGE_WIDTH(STAGE_WIDTH)
    ) inst_wb_calc_e (
        .wb_clk_i(clk),
        .wb_rst_i(rst),

        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),

        .wbs_we_i(wbs_we_i),
        .wbs_sel_i(wbs_sel_i),

        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),

        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),

        .la_data_in(la_data_in),
        .la_data_out(la_data_out),
        .la_oenb(la_oenb)
    );
    

endmodule