data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tPortOut.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tPortOut.v:9: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module tPortOut #(
    `include "noc_parameter.vh"
)
(




    output  wire    [NOC_HEADER_SIZE-1:0]   header_o,
    output  wire    [NOC_PAYLOAD_SIZE-1:0]  payload_o,
    output  wire                            wrreq_o,
    input   wire                            BEstall_i,


    input   wire    [NOC_HEADER_SIZE-1:0]   flitHeader_i,
    input   wire    [NOC_PAYLOAD_SIZE-1:0]  flitPayload_i,
    input   wire                            flitWrreq_i,
    output  wire                            flitStall_o
);


    assign header_o     = flitHeader_i;
    assign payload_o    = flitPayload_i;
    assign wrreq_o      = flitWrreq_i;
    assign flitStall_o  = BEstall_i;

endmodule
module tPortOut #(
    `include "noc_parameter.vh"
)
(




    output  wire    [NOC_HEADER_SIZE-1:0]   header_o,
    output  wire    [NOC_PAYLOAD_SIZE-1:0]  payload_o,
    output  wire                            wrreq_o,
    input   wire                            BEstall_i,


    input   wire    [NOC_HEADER_SIZE-1:0]   flitHeader_i,
    input   wire    [NOC_PAYLOAD_SIZE-1:0]  flitPayload_i,
    input   wire                            flitWrreq_i,
    output  wire                            flitStall_o
);



    assign header_o     = flitHeader_i;
    assign payload_o    = flitPayload_i;
    assign wrreq_o      = flitWrreq_i;
    assign flitStall_o  = BEstall_i;

endmodule