data/full_repos/permissive/522064891/efinity/ram512.v
1: b"%Error: data/full_repos/permissive/522064891/efinity/ram512.v:16: Cannot find file containing module: 'EFX_RAM_5K'\nEFX_RAM_5K # (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/EFX_RAM_5K\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/EFX_RAM_5K.v\n             data/full_repos/permissive/522064891/efinity,data/full_repos/permissive/522064891/EFX_RAM_5K.sv\n             EFX_RAM_5K\n             EFX_RAM_5K.v\n             EFX_RAM_5K.sv\n             obj_dir/EFX_RAM_5K\n             obj_dir/EFX_RAM_5K.v\n             obj_dir/EFX_RAM_5K.sv\n%Error: Exiting due to 1 error(s)\n"
module ram512
(
    input        clock,
    input [8:0]  address,
    input        select,
    input        rw,
    input [7:0]  dataIn,
    output [7:0] dataOut
);

EFX_RAM_5K # (
    .READ_WIDTH(8),
    .WRITE_WIDTH(8),
    .OUTPUT_REG(1'b0),
    .RCLK_POLARITY(1'b1),
    .RE_POLARITY(1'b1),
    .WCLK_POLARITY(1'b1),
    .WE_POLARITY(1'b1),
    .WCLKE_POLARITY(1'b1),
    .WRITE_MODE("READ_FIRST"),
    .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ramBlock (
    .RDATA(dataOut),
    .RADDR(address),
    .RCLK(select),
    .RE(rw),
    .WDATA(dataIn),
    .WADDR(address),
    .WCLK(select),
    .WE(!rw),
    .WCLKE(1'b1)
);
endmodule
module ram512
(
    input        clock,
    input [8:0]  address,
    input        select,
    input        rw,
    input [7:0]  dataIn,
    output [7:0] dataOut
);


EFX_RAM_5K # (
    .READ_WIDTH(8),
    .WRITE_WIDTH(8),
    .OUTPUT_REG(1'b0),
    .RCLK_POLARITY(1'b1),
    .RE_POLARITY(1'b1),
    .WCLK_POLARITY(1'b1),
    .WE_POLARITY(1'b1),
    .WCLKE_POLARITY(1'b1),
    .WRITE_MODE("READ_FIRST"),
    .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ramBlock (
    .RDATA(dataOut),
    .RADDR(address),
    .RCLK(select),
    .RE(rw),
    .WDATA(dataIn),
    .WADDR(address),
    .WCLK(select),
    .WE(!rw),
    .WCLKE(1'b1)
);
endmodule