data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module InstrMem #(parameter instrNum=8, addr_width=8, instr_width=32)(
    input [instr_width-1:0] addr,
    output reg [instr_width-1:0] instruction
);
    localparam regNum = 1 << instrNum;
    reg [instr_width-1:0] instrMem [regNum-1:0];
    integer i;
    initial begin 
        for (i=0;i<regNum;i=i+1) begin instrMem[i] = 0; end
        $readmemb("./test.txt", instrMem);
        instruction = 0;
    end
    always @(*) begin instruction = instrMem[addr >> 2]; end
endmodule
module InstrMem #(parameter instrNum=8, addr_width=8, instr_width=32)(
    input [instr_width-1:0] addr,
    output reg [instr_width-1:0] instruction
);

    localparam regNum = 1 << instrNum;
    reg [instr_width-1:0] instrMem [regNum-1:0];
    integer i;
    initial begin 
        for (i=0;i<regNum;i=i+1) begin instrMem[i] = 0; end
        $readmemb("./test.txt", instrMem);
        instruction = 0;
    end
    always @(*) begin instruction = instrMem[addr >> 2]; end
endmodule