data/full_repos/permissive/434840709/week13/5.v
data/verilator_xmls/1206583d-f89a-480d-8596-4bc2b7f37bfe.xml
module top_module (
	input clk,
	input reset,
	input shift_ena,
	input count_ena,
	input data,
	output [3:0] q
);
    reg [3:0] q_reg;
	always @(posedge clk) begin
		if(reset) begin 
			q_reg <= 0;
		end
		else begin
			if (shift_ena == 1) begin
                q_reg =  q_reg << 1;
				q_reg[0] = data;
			end

			if (count_ena == 1) begin
				q_reg = q_reg - 1;
			end
		end
	end

    assign q = q_reg;

endmodule
module top_module (
	input clk,
	input reset,
	input shift_ena,
	input count_ena,
	input data,
	output [3:0] q
);

    reg [3:0] q_reg;
	always @(posedge clk) begin
		if(reset) begin 
			q_reg <= 0;
		end
		else begin
			if (shift_ena == 1) begin
                q_reg =  q_reg << 1;
				q_reg[0] = data;
			end

			if (count_ena == 1) begin
				q_reg = q_reg - 1;
			end
		end
	end

    assign q = q_reg;

endmodule