data/full_repos/permissive/498129202/src/mux81.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/498129202/src/mux81.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] d;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/498129202/src/mux81.v:5: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] sel;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module mux81 (d, sel, o);


input [0:7] d;
input [0:2] sel;
output reg o;

always @ (d, sel) begin
    case (sel)
        3'b000:  o = d[0];
        3'b001:  o = d[1];
        3'b010:  o = d[2];
        3'b011:  o = d[3];
        3'b100:  o = d[4];
        3'b101:  o = d[5];
        3'b110:  o = d[6];
        3'b111:  o = d[7];
        default: o = 1'b0;
    endcase
end

endmodule
module mux81 (d, sel, o);



input [0:7] d;
input [0:2] sel;
output reg o;

always @ (d, sel) begin
    case (sel)
        3'b000:  o = d[0];
        3'b001:  o = d[1];
        3'b010:  o = d[2];
        3'b011:  o = d[3];
        3'b100:  o = d[4];
        3'b101:  o = d[5];
        3'b110:  o = d[6];
        3'b111:  o = d[7];
        default: o = 1'b0;
    endcase
end

endmodule