data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/UPDOWN_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/UPDOWN_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/UPDOWN_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/UPDOWN_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk1_tb = ~clk1_tb;\n        ^\n%Error: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/UPDOWN_TB.v:15: Cannot find file containing module: \'UPDOWN\'\n    UPDOWN COMP (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/UPDOWN\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/UPDOWN.v\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/UPDOWN.sv\n             UPDOWN\n             UPDOWN.v\n             UPDOWN.sv\n             obj_dir/UPDOWN\n             obj_dir/UPDOWN.v\n             obj_dir/UPDOWN.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UPDOWN_TB(

    );
    reg clk1_tb,rst_tb;
    reg en_tb;
    reg ud_tb;
    reg l;
    reg [3:0] u;
    reg [2:0] n;
    
    wire [31:0] cnt_tb;
    
    UPDOWN COMP (
    .clk1(clk1_tb),
    .rst1(rst_tb),
    .en(en_tb),
    .ud(ud_tb),
    .load(l),
    .udsw(u),
    .numsel(n),
    .tmp(cnt_tb)       
    );
    
    initial 
        begin
        clk1_tb = 0;
        rst_tb = 1;
        ud_tb = 0;
        en_tb = 1;
        #10
        rst_tb = 0;
        l=1;
        n=1;
        u=4;
        #1000
        $finish;
        end
        
    always   
        begin
        #5 clk1_tb = ~clk1_tb;
        end
        

        endmodule
module UPDOWN_TB(

    );

    reg clk1_tb,rst_tb;
    reg en_tb;
    reg ud_tb;
    reg l;
    reg [3:0] u;
    reg [2:0] n;
    
    wire [31:0] cnt_tb;
    
    UPDOWN COMP (
    .clk1(clk1_tb),
    .rst1(rst_tb),
    .en(en_tb),
    .ud(ud_tb),
    .load(l),
    .udsw(u),
    .numsel(n),
    .tmp(cnt_tb)       
    );
    
    initial 
        begin
        clk1_tb = 0;
        rst_tb = 1;
        ud_tb = 0;
        en_tb = 1;
        #10
        rst_tb = 0;
        l=1;
        n=1;
        u=4;
        #1000
        $finish;
        end
        
    always   
        begin
        #5 clk1_tb = ~clk1_tb;
        end
        

        endmodule