data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:29: Cannot find include file: usrp_tasks.v\n`include "usrp_tasks.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v.v\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v.sv\n             usrp_tasks.v\n             usrp_tasks.v.v\n             usrp_tasks.v.sv\n             obj_dir/usrp_tasks.v\n             obj_dir/usrp_tasks.v.v\n             obj_dir/usrp_tasks.v.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:98: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fullchip_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:99: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, fullchip_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\nalways #24 clk_120mhz = ~clk_120mhz;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\nalways #60 usbclk = ~usbclk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\ninitial #500 reset = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:132: syntax error, unexpected \'@\'\n       #30000 @(posedge usbclk);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n       #30000 @(posedge usbclk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n       #30000 burst_usb_read(256);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n       #10000 $finish;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\ninitial #40000 enable_tx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\ninitial #40000 enable_rx = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:158: Define or directive not defined: \'`ch1in_freq\'\n #1000 send_config_word(`ch1in_freq,32\'h0);  \n                        ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1000 send_config_word(`ch1in_freq,32\'h0);  \n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:159: Define or directive not defined: \'`ch2in_freq\'\n send_config_word(`ch2in_freq,32\'h0);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:160: Define or directive not defined: \'`ch3in_freq\'\n send_config_word(`ch3in_freq,32\'h0);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:161: Define or directive not defined: \'`ch4in_freq\'\n send_config_word(`ch4in_freq,32\'h0);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:162: Define or directive not defined: \'`ch1out_freq\'\n send_config_word(`ch1out_freq,32\'h01234567);\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:163: Define or directive not defined: \'`ch2out_freq\'\n send_config_word(`ch2out_freq,32\'h0);\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:164: Define or directive not defined: \'`ch3out_freq\'\n send_config_word(`ch3out_freq,32\'h0);\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:165: Define or directive not defined: \'`ch4out_freq\'\n send_config_word(`ch4out_freq,32\'h0);\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:166: Define or directive not defined: \'`misc\'\n send_config_word(`misc,32\'h0);\n                  ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/fullchip_tb.v:167: Define or directive not defined: \'`rates\'\n send_config_word(`rates,{8\'d2,8\'d12,8\'h0f,8\'h07});\n                  ^~~~~~\n%Error: Exiting due to 14 error(s), 9 warning(s)\n'
module fullchip_tb();

`include "usrp_tasks.v"

fullchip fullchip
  (
   .clk_120mhz(clk_120mhz),
   .reset(reset),
   .enable_rx(enable_rx),
   .enable_tx(enable_tx),
   .SLD(serload),
   .SEN(serenable),
   .clear_status(),
   .SDI(serdata),
   .SCLK(serclk),
	  
   .adc1_data(adc1_data),
   .adc2_data(adc2_data),
   .adc3_data(adc1_data),
   .adc4_data(adc2_data),
   
   .dac1_data(dac1_data),
   .dac2_data(dac2_data),
   .dac3_data(),.dac4_data(),
   
   .adclk0(adclk),.adclk1(),
   
   .adc_oeb(),.adc_otr(4'b0),
   
   .clk_out(clk_out),
   
   .misc_pins(),
   

   .usbclk(usbclk),.usbctl(usbctl),
   .usbrdy(usbrdy),.usbdata(usbdata)
   );	
	
	reg clk_120mhz;
	reg usbclk;
	reg reset;

	reg [11:0] adc1_data, adc2_data;
	wire [13:0] dac1_data, dac2_data;

	wire [5:0] usbctl;
	wire [5:0] usbrdy;

	wire [15:0] usbdata;

	reg WE, RD, OE;

        assign usbctl[0] = WE;
        assign usbctl[1] = RD;
        assign usbctl[2] = OE;
	assign usbctl[5:3] = 0;

        wire have_packet_rdy = usbrdy[1];
   
	reg tb_oe;
   initial tb_oe=1'b1;
   
	assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
	reg serload, serenable, serclk, serdata;
	reg enable_tx, enable_rx;
	reg [15:0] usbdatareg;



initial
begin
	$dumpfile("fullchip_tb.vcd");
	$dumpvars(0, fullchip_tb);
end











initial clk_120mhz = 0;
initial usbclk = 0;
always #24 clk_120mhz = ~clk_120mhz;
always #60 usbclk = ~usbclk;

initial reset = 1'b1;
initial #500 reset = 1'b0;




always @(posedge adclk)	 adc1_data <= #1 12'd1234;
always @(posedge adclk)	 adc2_data <= #1 12'd1234;




  initial 
    begin
       initialize_usb;
       #30000 @(posedge usbclk);
       burst_usb_write(257);
       
       #30000 burst_usb_read(256);
       #10000 $finish;
   





end




initial enable_tx = 1'b0;
initial #40000 enable_tx = 1'b1;
initial enable_rx = 1'b0;
initial #40000 enable_rx = 1'b1;




initial 
begin
	#1000 send_config_word(`ch1in_freq,32'h0);
	send_config_word(`ch2in_freq,32'h0);
	send_config_word(`ch3in_freq,32'h0);
	send_config_word(`ch4in_freq,32'h0);
	send_config_word(`ch1out_freq,32'h01234567);
	send_config_word(`ch2out_freq,32'h0);
	send_config_word(`ch3out_freq,32'h0);
	send_config_word(`ch4out_freq,32'h0);
	send_config_word(`misc,32'h0);
	send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07});

end



endmodule
module fullchip_tb();


`include "usrp_tasks.v"

fullchip fullchip
  (
   .clk_120mhz(clk_120mhz),
   .reset(reset),
   .enable_rx(enable_rx),
   .enable_tx(enable_tx),
   .SLD(serload),
   .SEN(serenable),
   .clear_status(),
   .SDI(serdata),
   .SCLK(serclk),
	  
   .adc1_data(adc1_data),
   .adc2_data(adc2_data),
   .adc3_data(adc1_data),
   .adc4_data(adc2_data),
   
   .dac1_data(dac1_data),
   .dac2_data(dac2_data),
   .dac3_data(),.dac4_data(),
   
   .adclk0(adclk),.adclk1(),
   
   .adc_oeb(),.adc_otr(4'b0),
   
   .clk_out(clk_out),
   
   .misc_pins(),
   

   .usbclk(usbclk),.usbctl(usbctl),
   .usbrdy(usbrdy),.usbdata(usbdata)
   );	
	
	reg clk_120mhz;
	reg usbclk;
	reg reset;

	reg [11:0] adc1_data, adc2_data;
	wire [13:0] dac1_data, dac2_data;

	wire [5:0] usbctl;
	wire [5:0] usbrdy;

	wire [15:0] usbdata;

	reg WE, RD, OE;

        assign usbctl[0] = WE;
        assign usbctl[1] = RD;
        assign usbctl[2] = OE;
	assign usbctl[5:3] = 0;

        wire have_packet_rdy = usbrdy[1];
   
	reg tb_oe;
   initial tb_oe=1'b1;
   
	assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
	reg serload, serenable, serclk, serdata;
	reg enable_tx, enable_rx;
	reg [15:0] usbdatareg;



initial
begin
	$dumpfile("fullchip_tb.vcd");
	$dumpvars(0, fullchip_tb);
end











initial clk_120mhz = 0;
initial usbclk = 0;
always #24 clk_120mhz = ~clk_120mhz;
always #60 usbclk = ~usbclk;

initial reset = 1'b1;
initial #500 reset = 1'b0;




always @(posedge adclk)	 adc1_data <= #1 12'd1234;
always @(posedge adclk)	 adc2_data <= #1 12'd1234;




  initial 
    begin
       initialize_usb;
       #30000 @(posedge usbclk);
       burst_usb_write(257);
       
       #30000 burst_usb_read(256);
       #10000 $finish;
   





end




initial enable_tx = 1'b0;
initial #40000 enable_tx = 1'b1;
initial enable_rx = 1'b0;
initial #40000 enable_rx = 1'b1;




initial 
begin
	#1000 send_config_word(`ch1in_freq,32'h0);
	send_config_word(`ch2in_freq,32'h0);
	send_config_word(`ch3in_freq,32'h0);
	send_config_word(`ch4in_freq,32'h0);
	send_config_word(`ch1out_freq,32'h01234567);
	send_config_word(`ch2out_freq,32'h0);
	send_config_word(`ch3out_freq,32'h0);
	send_config_word(`ch4out_freq,32'h0);
	send_config_word(`misc,32'h0);
	send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07});

end



endmodule