data/full_repos/permissive/452461941/AES_Decryption/Register.v
data/verilator_xmls/3f560973-9d12-457e-9a44-73125ba531f6.xml
module Register #(parameter n = 128) (output reg [n-1:0] Q, input [n-1:0] D, input enable, clock, reset);
	always @(posedge clock, posedge reset) begin
		if (reset)
			Q <= 128'd0;
		else if (enable)
			Q <= D;
	end
endmodule
module Register #(parameter n = 128) (output reg [n-1:0] Q, input [n-1:0] D, input enable, clock, reset);

	always @(posedge clock, posedge reset) begin
		if (reset)
			Q <= 128'd0;
		else if (enable)
			Q <= D;
	end
endmodule