data/full_repos/permissive/439345921/Screen_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439345921/Screen_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #10 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439345921/Screen_tb.v:17: Cannot find file containing module: \'Screen\'\n Screen Screen_inst (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/Screen\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/Screen.v\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/Screen.sv\n             Screen\n             Screen.v\n             Screen.sv\n             obj_dir/Screen\n             obj_dir/Screen.v\n             obj_dir/Screen.sv\n%Error: data/full_repos/permissive/439345921/Screen_tb.v:27: Cannot find file containing module: \'VRAM8K\'\n VRAM8K VRAM8K_inst (\n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Screen_tb();

	reg clk;
	reg rst_n;
	

	wire [12:0] address_vram_vga;
	wire hsync;
	wire vsync;
	wire [15:0] data_vram_vga;
	wire rgb;
	

	wire [15:0] data_vram_cpu;

	Screen Screen_inst (
		.clk(clk),
		.rst_n(rst_n),
		.data_vram(data_vram_vga),
		.address_vram(address_vram_vga),
		.hsync(hsync),
		.vsync(vsync),
		.rgb(rgb)
	);
	
	VRAM8K VRAM8K_inst (
		.address_a(13'd0),
		.address_b(address_vram_vga),
		.clock_a(clk),
		.clock_b(clk),
		.data_a(16'd0),
		.data_b(16'd0),
		.wren_a(1'b0),
		.wren_b(1'b0),
		.q_a(data_vram_cpu),
		.q_b(data_vram_vga)
	);

	initial begin
		clk = 0;
		rst_n = 1;
	end
	
	always #10 begin
		clk = ~clk;
	end
	
endmodule
module Screen_tb();


	reg clk;
	reg rst_n;
	

	wire [12:0] address_vram_vga;
	wire hsync;
	wire vsync;
	wire [15:0] data_vram_vga;
	wire rgb;
	

	wire [15:0] data_vram_cpu;

	Screen Screen_inst (
		.clk(clk),
		.rst_n(rst_n),
		.data_vram(data_vram_vga),
		.address_vram(address_vram_vga),
		.hsync(hsync),
		.vsync(vsync),
		.rgb(rgb)
	);
	
	VRAM8K VRAM8K_inst (
		.address_a(13'd0),
		.address_b(address_vram_vga),
		.clock_a(clk),
		.clock_b(clk),
		.data_a(16'd0),
		.data_b(16'd0),
		.wren_a(1'b0),
		.wren_b(1'b0),
		.q_a(data_vram_cpu),
		.q_b(data_vram_vga)
	);

	initial begin
		clk = 0;
		rst_n = 1;
	end
	
	always #10 begin
		clk = ~clk;
	end
	
endmodule