data/full_repos/permissive/422447942/Codebase/keyboard.v
1: b'%Warning-WIDTH: data/full_repos/permissive/422447942/Codebase/keyboard.v:21: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance keyboard\n b <= 1\'h1;\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module keyboard( clk, data, outputBinData);





	input wire data;
	input wire clk;
	output reg[7:0] outputBinData;
	
	
	reg [7:0] bitInfo;
	reg [7:0] storage;
	reg [3:0] b;
	reg endSwitch;
	
	initial
	begin
	bitInfo <= 8'hf0;
	storage <= 8'hf0;
	b <= 1'h1;
	endSwitch <= 1'b0;
	end
	
	always@(negedge clk)
	begin



	case(b)
	2:bitInfo[0] <= data;
	3:bitInfo[1] <= data;
	4:bitInfo[2] <= data;
	5:bitInfo[3] <= data;
	6:bitInfo[4] <= data;
	7:bitInfo[5] <= data;
	8:bitInfo[6] <= data;
	9:bitInfo[7] <= data;
	10:endSwitch <= 1'b1;
	11:endSwitch <= 1'b0;
	endcase
	

	if(b < 11) 
		b <= b + 1;
	else if(b == 11)
		b <= 1;	
	end
	
	always@(posedge endSwitch)

	begin	
	if(bitInfo == 8'hf0)
		begin
		outputBinData = storage;

		storage = 8'hf0;
		end
	else
		storage <= bitInfo;	
	end
		

endmodule
module keyboard( clk, data, outputBinData);






	input wire data;
	input wire clk;
	output reg[7:0] outputBinData;
	
	
	reg [7:0] bitInfo;
	reg [7:0] storage;
	reg [3:0] b;
	reg endSwitch;
	
	initial
	begin
	bitInfo <= 8'hf0;
	storage <= 8'hf0;
	b <= 1'h1;
	endSwitch <= 1'b0;
	end
	
	always@(negedge clk)
	begin



	case(b)
	2:bitInfo[0] <= data;
	3:bitInfo[1] <= data;
	4:bitInfo[2] <= data;
	5:bitInfo[3] <= data;
	6:bitInfo[4] <= data;
	7:bitInfo[5] <= data;
	8:bitInfo[6] <= data;
	9:bitInfo[7] <= data;
	10:endSwitch <= 1'b1;
	11:endSwitch <= 1'b0;
	endcase
	

	if(b < 11) 
		b <= b + 1;
	else if(b == 11)
		b <= 1;	
	end
	
	always@(posedge endSwitch)

	begin	
	if(bitInfo == 8'hf0)
		begin
		outputBinData = storage;

		storage = 8'hf0;
		end
	else
		storage <= bitInfo;	
	end
		

endmodule