data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:43: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'gen_test1\'\nmodule gen_test1(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test2\'\nmodule gen_test2(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test3\'\nmodule gen_test3(a, b, sel, y, z);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test4\'\nmodule gen_test4(a, b);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test5\'\nmodule gen_test5(input_bits, out);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test6\'\nmodule gen_test6(output [3:0] o);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test7\'\nmodule gen_test7;\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test8\'\nmodule gen_test8;\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:177: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out1 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:178: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out1 = x;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:183: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out2 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:184: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out2 = x;\n             ^\n%Error: Exiting due to 5 warning(s)\n'
module gen_test8;


`ifdef VERIFY
	`define ASSERT(expr) assert property (expr);
`else
	`define ASSERT(expr)
`endif

	wire [1:0] x = 2'b11;
	generate
		begin : A
			wire [1:0] x;
			begin : B
				wire [1:0] x = 2'b00;
				`ASSERT(x == 0)
				`ASSERT(A.x == 2)
				`ASSERT(A.C.x == 1)
				`ASSERT(A.B.x == 0)
				`ASSERT(gen_test8.x == 3)
				`ASSERT(gen_test8.A.x == 2)
				`ASSERT(gen_test8.A.C.x == 1)
				`ASSERT(gen_test8.A.B.x == 0)
			end
			begin : C
				wire [1:0] x = 2'b01;
				`ASSERT(x == 1)
				`ASSERT(A.x == 2)
				`ASSERT(A.C.x == 1)
				`ASSERT(A.B.x == 0)
				`ASSERT(gen_test8.x == 3)
				`ASSERT(gen_test8.A.x == 2)
				`ASSERT(gen_test8.A.C.x == 1)
				`ASSERT(gen_test8.A.B.x == 0)
			end
			assign x = B.x ^ 2'b11 ^ C.x;
			`ASSERT(x == 2)
			`ASSERT(A.x == 2)
			`ASSERT(A.C.x == 1)
			`ASSERT(A.B.x == 0)
			`ASSERT(gen_test8.x == 3)
			`ASSERT(gen_test8.A.x == 2)
			`ASSERT(gen_test8.A.C.x == 1)
			`ASSERT(gen_test8.A.B.x == 0)
		end
	endgenerate

	`ASSERT(x == 3)
	`ASSERT(A.x == 2)
	`ASSERT(A.C.x == 1)
	`ASSERT(A.B.x == 0)
	`ASSERT(gen_test8.x == 3)
	`ASSERT(gen_test8.A.x == 2)
	`ASSERT(gen_test8.A.C.x == 1)
	`ASSERT(gen_test8.A.B.x == 0)
endmodule
module gen_test8;



`ifdef VERIFY
	`define ASSERT(expr) assert property (expr);
`else
	`define ASSERT(expr)
`endif

	wire [1:0] x = 2'b11;
	generate
		begin : A
			wire [1:0] x;
			begin : B
				wire [1:0] x = 2'b00;
				`ASSERT(x == 0)
				`ASSERT(A.x == 2)
				`ASSERT(A.C.x == 1)
				`ASSERT(A.B.x == 0)
				`ASSERT(gen_test8.x == 3)
				`ASSERT(gen_test8.A.x == 2)
				`ASSERT(gen_test8.A.C.x == 1)
				`ASSERT(gen_test8.A.B.x == 0)
			end
			begin : C
				wire [1:0] x = 2'b01;
				`ASSERT(x == 1)
				`ASSERT(A.x == 2)
				`ASSERT(A.C.x == 1)
				`ASSERT(A.B.x == 0)
				`ASSERT(gen_test8.x == 3)
				`ASSERT(gen_test8.A.x == 2)
				`ASSERT(gen_test8.A.C.x == 1)
				`ASSERT(gen_test8.A.B.x == 0)
			end
			assign x = B.x ^ 2'b11 ^ C.x;
			`ASSERT(x == 2)
			`ASSERT(A.x == 2)
			`ASSERT(A.C.x == 1)
			`ASSERT(A.B.x == 0)
			`ASSERT(gen_test8.x == 3)
			`ASSERT(gen_test8.A.x == 2)
			`ASSERT(gen_test8.A.C.x == 1)
			`ASSERT(gen_test8.A.B.x == 0)
		end
	endgenerate

	`ASSERT(x == 3)
	`ASSERT(A.x == 2)
	`ASSERT(A.C.x == 1)
	`ASSERT(A.B.x == 0)
	`ASSERT(gen_test8.x == 3)
	`ASSERT(gen_test8.A.x == 2)
	`ASSERT(gen_test8.A.C.x == 1)
	`ASSERT(gen_test8.A.B.x == 0)
endmodule