data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:76: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_basic,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504248338/verilog/dv/user_basic,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_basic,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK1_PERIOD/2) clock  <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1\'b0);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n   #200;  \n   ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:174: syntax error, unexpected \'@\'\n   repeat (10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:177: syntax error, unexpected \'@\'\n   repeat (2) @(posedge clock);\n              ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:180: Unsupported: fork statements\n   fork\n   ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:191: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h0,8\'h0,8\'h0});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:191: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h0,8\'h0,8\'h0});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:191: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h0,8\'h0,8\'h0});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:196: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h40,8\'h60,8\'h1,8\'h40});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:196: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h40,8\'h60,8\'h1,8\'h40});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:196: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h40,8\'h60,8\'h1,8\'h40});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:201: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h20,8\'h61,8\'h2,8\'h20});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:201: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h20,8\'h61,8\'h2,8\'h20});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:201: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h20,8\'h61,8\'h2,8\'h20});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:206: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h21,8\'h62,8\'h3,8\'h21});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:206: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h21,8\'h62,8\'h3,8\'h21});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:206: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h21,8\'h62,8\'h3,8\'h21});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:211: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h22,8\'h63,8\'h4,8\'h22});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:211: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h22,8\'h63,8\'h4,8\'h22});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:211: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h22,8\'h63,8\'h4,8\'h22});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:216: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h23,8\'h64,8\'h5,8\'h23});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:216: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h23,8\'h64,8\'h5,8\'h23});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:216: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h23,8\'h64,8\'h5,8\'h23});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:221: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h60,8\'h65,8\'h6,8\'h60});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:221: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h60,8\'h65,8\'h6,8\'h60});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:221: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h60,8\'h65,8\'h6,8\'h60});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:226: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h61,8\'h66,8\'h7,8\'h61});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:226: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h61,8\'h66,8\'h7,8\'h61});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:226: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h61,8\'h66,8\'h7,8\'h61});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:231: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h62,8\'h67,8\'h8,8\'h62});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:231: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h62,8\'h67,8\'h8,8\'h62});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:231: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h62,8\'h67,8\'h8,8\'h62});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:236: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h68,8\'h80,8\'h63});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:236: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h68,8\'h80,8\'h63});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:236: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h68,8\'h80,8\'h63});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:241: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h69,8\'hFF,8\'h64});\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:241: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h69,8\'hFF,8\'h64});\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:241: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h63,8\'h69,8\'hFF,8\'h64});\n                                                                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:249: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b100,4\'b0000,8\'h2});\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:249: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b100,4\'b0000,8\'h2});\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:249: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b100,4\'b0000,8\'h2});\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:250: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b0,5\'h3,26\'h00000});\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:250: Define or directive not defined: \'`WBHOST_PLL_CTRL\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b0,5\'h3,26\'h00000});\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:250: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b0,5\'h3,26\'h00000});\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:251: syntax error, unexpected \'@\'\n         repeat (100) @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:256: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b000,4\'b0000,8\'h2});\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:256: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b000,4\'b0000,8\'h2});\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16\'h0,1\'b1,3\'b000,4\'b0000,8\'h2});\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:257: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b1,5\'h0,26\'h0000});\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:257: Define or directive not defined: \'`WBHOST_PLL_CTRL\'\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b1,5\'h0,26\'h0000});\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_basic/user_basic_tb.v:257: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1\'b1,5\'h0,26\'h0000});\n                                                               ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module user_basic_tb;
parameter CLK1_PERIOD = 10;
parameter CLK2_PERIOD = 2;

reg            clock         ;
reg            clock2        ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

wire           clock_mon;
integer        test_step;

integer i,j;





	always #(CLK1_PERIOD/2) clock  <= (clock === 1'b0);
	always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);

	initial begin
		test_step = 0;
		clock = 0;
		clock2 = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, user_basic_tb);


	   	$dumpvars(0, user_basic_tb.u_top.u_wb_host);



	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end


initial
begin

   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Basic Test Started");
   
   repeat (2) @(posedge clock);

   test_fail=0;
   fork
      begin







	  $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1");
	  test_step = 1;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0});
	  clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD);

	  $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2");
	  test_step = 2;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40});
	  clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD);

	  $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2");
	  test_step = 3;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20});
	  clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD);

	  $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3");
	  test_step = 4;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21});
	  clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD);

	  $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4");
	  test_step = 5;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22});
	  clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD);

	  $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
	  test_step = 6;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23});
	  clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);

	  $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)");
	  test_step = 7;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60});
	  clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD);

	  $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3");
	  test_step = 8;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61});
	  clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD);

	  $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4");
	  test_step = 9;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62});
	  clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD);

	  $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)");
	  test_step = 10;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63});
	  clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD);

	  $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
	  test_step = 10;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
	  clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
  
         $display("###################################################");
         $display("Monitor: Checking the PLL:");
         $display("###################################################");
	 test_step = 11;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
         repeat (100) @(posedge clock);
	 pll_clock_monitor(5);

	 test_step = 12;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
         repeat (100) @(posedge clock);
	 pll_clock_monitor(4);

         $display("###################################################");
         $display("Monitor: Monitor Clock output:");
         $display("###################################################");
	 $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
	 test_step = 13;
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});


         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
	 dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
         
	 $display("###################################################");
         $display("Monitor: Checking the chip signature :");
         $display("###################################################");
	 test_step = 14;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022);
	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000);

      end
   
      begin
      repeat (30000) @(posedge clock);

      test_fail = 1;
      end
      join_any
      disable fork;

   
      $display("###################################################");
      if(test_fail == 0) begin
         `ifdef GL
             $display("Monitor: Standalone User UART Test (GL) Passed");
         `else
             $display("Monitor: Standalone User UART Test (RTL) Passed");
         `endif
      end else begin
          `ifdef GL
              $display("Monitor: Standalone User UART Test (GL) Failed");
          `else
              $display("Monitor: Standalone User UART Test (RTL) Failed");
          `endif
       end
      $display("###################################################");
      #100
      $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (clock2),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin


    end
`endif    


task clock_monitor;
input [15:0] exp_cpu_period;
input [15:0] exp_usb_period;
input [15:0] exp_rtc_period;
input [15:0] exp_wbs_period;
begin
   force clock_mon = u_top.u_wb_host.cpu_clk;
   check_clock_period("CPU CLock",exp_cpu_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.usb_clk;
   check_clock_period("USB Clock",exp_usb_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.rtc_clk;
   check_clock_period("RTC Clock",exp_rtc_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.wbs_clk_out;
   check_clock_period("WBS Clock",exp_wbs_period);
   release clock_mon;
end
endtask

task pll_clock_monitor;
input [15:0] exp_period;
begin

   `ifdef GL
      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.u_buf.X;
    `else
      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
    `endif
   check_clock_period("PLL CLock",exp_period);
   release clock_mon;
end
endtask


wire dbg_clk_mon = io_out[33];

task dbg_clk_monitor;
input [15:0] exp_pll_div16_period;
input [15:0] exp_pll_ref_period;
input [15:0] exp_cpu_period;
input [15:0] exp_usb_period;
input [15:0] exp_rtc_period;
input [15:0] exp_wbs_period;
begin
   force clock_mon = dbg_clk_mon;

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
   check_clock_period("PLL CLock",exp_pll_div16_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2});
   check_clock_period("PLL REF Clock",exp_pll_ref_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2});
   check_clock_period("WBS Clock",exp_wbs_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2});
   check_clock_period("CPU CLock",exp_cpu_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2});
   check_clock_period("RTC Clock",exp_rtc_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2});
   check_clock_period("USB Clock",exp_usb_period);
   release clock_mon;
end
endtask




task check_clock_period;
input [127:0] clk_name;
input [15:0] clk_period;
time prev_t, next_t, periodd;
begin
	$timeformat(-12,3,"ns",10);
   repeat(1) @(posedge clock_mon);
   repeat(1) @(posedge clock_mon);
   prev_t  = $realtime;
   repeat(100) @(posedge clock_mon);
   next_t  = $realtime;
   periodd = (next_t-prev_t)/100;

   if(clk_period != periodd) begin
       $display("STATUS: FAIL => %s Exp Period: %d Rxd: %d",clk_name,clk_period,periodd);
       test_fail = 1;
   end else begin
       $display("STATUS: PASS => %s  Period: %d ",clk_name,clk_period);
   end
end
endtask






task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule
module user_basic_tb;

parameter CLK1_PERIOD = 10;
parameter CLK2_PERIOD = 2;

reg            clock         ;
reg            clock2        ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

wire           clock_mon;
integer        test_step;

integer i,j;





	always #(CLK1_PERIOD/2) clock  <= (clock === 1'b0);
	always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);

	initial begin
		test_step = 0;
		clock = 0;
		clock2 = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, user_basic_tb);


	   	$dumpvars(0, user_basic_tb.u_top.u_wb_host);



	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end


initial
begin

   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Basic Test Started");
   
   repeat (2) @(posedge clock);

   test_fail=0;
   fork
      begin







	  $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1");
	  test_step = 1;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0});
	  clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD);

	  $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2");
	  test_step = 2;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40});
	  clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD);

	  $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2");
	  test_step = 3;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20});
	  clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD);

	  $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3");
	  test_step = 4;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21});
	  clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD);

	  $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4");
	  test_step = 5;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22});
	  clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD);

	  $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
	  test_step = 6;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23});
	  clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);

	  $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)");
	  test_step = 7;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60});
	  clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD);

	  $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3");
	  test_step = 8;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61});
	  clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD);

	  $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4");
	  test_step = 9;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62});
	  clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD);

	  $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)");
	  test_step = 10;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63});
	  clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD);

	  $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
	  test_step = 10;
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
	  clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
  
         $display("###################################################");
         $display("Monitor: Checking the PLL:");
         $display("###################################################");
	 test_step = 11;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
         repeat (100) @(posedge clock);
	 pll_clock_monitor(5);

	 test_step = 12;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
         repeat (100) @(posedge clock);
	 pll_clock_monitor(4);

         $display("###################################################");
         $display("Monitor: Monitor Clock output:");
         $display("###################################################");
	 $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
	 test_step = 13;
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});


         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
	 dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
         
	 $display("###################################################");
         $display("Monitor: Checking the chip signature :");
         $display("###################################################");
	 test_step = 14;

         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022);
	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000);

      end
   
      begin
      repeat (30000) @(posedge clock);

      test_fail = 1;
      end
      join_any
      disable fork;

   
      $display("###################################################");
      if(test_fail == 0) begin
         `ifdef GL
             $display("Monitor: Standalone User UART Test (GL) Passed");
         `else
             $display("Monitor: Standalone User UART Test (RTL) Passed");
         `endif
      end else begin
          `ifdef GL
              $display("Monitor: Standalone User UART Test (GL) Failed");
          `else
              $display("Monitor: Standalone User UART Test (RTL) Failed");
          `endif
       end
      $display("###################################################");
      #100
      $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (clock2),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin


    end
`endif    


task clock_monitor;
input [15:0] exp_cpu_period;
input [15:0] exp_usb_period;
input [15:0] exp_rtc_period;
input [15:0] exp_wbs_period;
begin
   force clock_mon = u_top.u_wb_host.cpu_clk;
   check_clock_period("CPU CLock",exp_cpu_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.usb_clk;
   check_clock_period("USB Clock",exp_usb_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.rtc_clk;
   check_clock_period("RTC Clock",exp_rtc_period);
   release clock_mon;

   force clock_mon = u_top.u_wb_host.wbs_clk_out;
   check_clock_period("WBS Clock",exp_wbs_period);
   release clock_mon;
end
endtask

task pll_clock_monitor;
input [15:0] exp_period;
begin

   `ifdef GL
      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.u_buf.X;
    `else
      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
    `endif
   check_clock_period("PLL CLock",exp_period);
   release clock_mon;
end
endtask


wire dbg_clk_mon = io_out[33];

task dbg_clk_monitor;
input [15:0] exp_pll_div16_period;
input [15:0] exp_pll_ref_period;
input [15:0] exp_cpu_period;
input [15:0] exp_usb_period;
input [15:0] exp_rtc_period;
input [15:0] exp_wbs_period;
begin
   force clock_mon = dbg_clk_mon;

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
   check_clock_period("PLL CLock",exp_pll_div16_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2});
   check_clock_period("PLL REF Clock",exp_pll_ref_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2});
   check_clock_period("WBS Clock",exp_wbs_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2});
   check_clock_period("CPU CLock",exp_cpu_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2});
   check_clock_period("RTC Clock",exp_rtc_period);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2});
   check_clock_period("USB Clock",exp_usb_period);
   release clock_mon;
end
endtask




task check_clock_period;
input [127:0] clk_name;
input [15:0] clk_period;
time prev_t, next_t, periodd;
begin
	$timeformat(-12,3,"ns",10);
   repeat(1) @(posedge clock_mon);
   repeat(1) @(posedge clock_mon);
   prev_t  = $realtime;
   repeat(100) @(posedge clock_mon);
   next_t  = $realtime;
   periodd = (next_t-prev_t)/100;

   if(clk_period != periodd) begin
       $display("STATUS: FAIL => %s Exp Period: %d Rxd: %d",clk_name,clk_period,periodd);
       test_fail = 1;
   end else begin
       $display("STATUS: PASS => %s  Period: %d ",clk_name,clk_period);
   end
end
endtask






task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule