data/full_repos/permissive/530250155/verilog/rtl/site/io_intf.v
1: b'%Error: data/full_repos/permissive/530250155/verilog/rtl/site/io_intf.v:22: Cannot find include file: ../toysram.vh\n`include "../toysram.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.v\n             data/full_repos/permissive/530250155/verilog/rtl/site,data/full_repos/permissive/530250155/../toysram.vh.sv\n             ../toysram.vh\n             ../toysram.vh.v\n             ../toysram.vh.sv\n             obj_dir/../toysram.vh\n             obj_dir/../toysram.vh.v\n             obj_dir/../toysram.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module io_intf  #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif

   input          clk,
   input          reset
);


endmodule
module io_intf  #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif

   input          clk,
   input          reset
);



endmodule