data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:52: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n            data_cnt    <= 16\'h0000;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:69: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= 16\'h0000;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:72: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:67: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0001) begin\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:79: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= 16\'h0000;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:82: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:82: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:77: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0001) begin\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:84: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                        rx_id <= {rx_id[OCT-1:0], rx_ethernet_data};\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:89: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= 16\'h0000;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:92: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:92: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                          : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:87: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                          : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0001) begin\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:107: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= 16\'h0000;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:110: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:110: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:105: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0001) begin\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:112: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                        rx_checksum <= {rx_checksum[OCT-1:0], rx_ethernet_data};\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:117: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= 16\'h0000;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:120: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:120: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:115: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0003) begin\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:128: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= {10\'b00_0000_0000, rx_header_len, 2\'b00};\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:131: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:131: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                           : ... In instance rx_ipv4\n                            data_cnt    <= data_cnt + 16\'h0001;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/522401967/verilog/rtl/Vthernet_MAC/rx_ipv4.v:125: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 8 bits.\n                                                                                           : ... In instance rx_ipv4\n                        if(data_cnt == 16\'h0003) begin\n                                    ^~\n%Error: Exiting due to 27 warning(s)\n'
module rx_ipv4 #(
    parameter   OCT = 8,
    parameter   UDP = 8'h11
)(
    input   wire                rst,
    input   wire                func_en,
    input   wire    [OCT*4-1:0] ip_addr,
    output  reg     [OCT*4-1:0] rx_src_ip,
    output  reg     [3:0]       rx_version,
    output  reg     [3:0]       rx_header_len,
    output  reg     [OCT-1:0]   rx_tos,
    output  reg     [OCT*2-1:0] rx_total_len,
    output  reg     [OCT-1:0]   rx_id,
    output  reg     [OCT*2-1:0] rx_flag_frag,
    output  reg     [OCT-1:0]   rx_ttl,
    output  reg     [OCT-1:0]   rx_protocol,
    output  reg     [OCT-1:0]   rx_checksum,
    input   wire                rx_ethernet_irq,
    output  reg                 rx_ipv4_irq,

    input   wire                RX_CLK,
    input   wire                rx_ethernet_data_v,
    input   wire    [OCT-1:0]   rx_ethernet_data,

    output  reg                 rx_ipv4_data_v,
    output  reg     [OCT-1:0]   rx_ipv4_data
);

    parameter RX_IHL_VER    = 8'b00000000;
    parameter RX_TOS        = 8'b00000001;
    parameter RX_TOTAL_LEN  = 8'b00000011;
    parameter RX_ID         = 8'b00000111;
    parameter RX_FLAG_FRAG  = 8'b00001111;
    parameter RX_TTL        = 8'b00011110;
    parameter RX_PROTOCOL   = 8'b00111110;
    parameter RX_CHECKSUM   = 8'b00111100;
    parameter RX_SRC_IP     = 8'b00011100;
    parameter RX_DST_IP     = 8'b00001100;
    parameter RX_DATA       = 8'b00000100;

    reg [OCT-1:0]   rx_state;

    reg [OCT*4-1:0] rx_dst_ip;

    
    reg [OCT-1:0]   data_cnt;

    always @(posedge RX_CLK) begin 
        if(rst) begin
            rx_state    <= RX_IHL_VER;
            data_cnt    <= 16'h0000;
            rx_ipv4_irq <= 1'b0;
        end else if(func_en) begin
            rx_ipv4_irq <= rx_ethernet_irq;
            if(rx_ethernet_data_v) begin
                case(rx_state)
                    RX_IHL_VER  : begin
                        rx_state    <= RX_TOS;
                        {rx_version, rx_header_len} <= rx_ethernet_data;
                    end
                    RX_TOS      : begin
                        rx_state    <= RX_TOTAL_LEN;
                        rx_tos      <= rx_ethernet_data;
                    end
                    RX_TOTAL_LEN: begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_ID;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_TOTAL_LEN;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_total_len <= {rx_total_len[OCT-1:0], rx_ethernet_data};
                    end
                    RX_ID       : begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_FLAG_FRAG;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_ID;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_id <= {rx_id[OCT-1:0], rx_ethernet_data};
                    end
                    RX_FLAG_FRAG: begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_TTL;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_FLAG_FRAG;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_flag_frag <= {rx_flag_frag[OCT-1:0], rx_ethernet_data};
                    end
                    RX_TTL      : begin
                        rx_state    <= RX_PROTOCOL;
                        rx_ttl      <= rx_ethernet_data;
                    end
                    RX_PROTOCOL : begin
                        rx_state    <= RX_CHECKSUM;
                        rx_protocol <= rx_ethernet_data;
                    end
                    RX_CHECKSUM : begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_SRC_IP;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_CHECKSUM;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_checksum <= {rx_checksum[OCT-1:0], rx_ethernet_data};
                    end
                    RX_SRC_IP   : begin
                        if(data_cnt == 16'h0003) begin
                            rx_state    <= RX_DST_IP;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_SRC_IP;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_src_ip <= {rx_src_ip[OCT*3-1:0], rx_ethernet_data};
                    end
                    RX_DST_IP   : begin
                        if(data_cnt == 16'h0003) begin
                            rx_state    <= RX_DATA;

                            data_cnt    <= {10'b00_0000_0000, rx_header_len, 2'b00};
                        end else begin
                            rx_state    <= RX_DST_IP;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_dst_ip <= {rx_dst_ip[OCT*3-1:0], rx_ethernet_data};
                    end
                    RX_DATA     : begin
                        rx_ipv4_data <= rx_ethernet_data;

                        case(rx_protocol)
                            UDP : begin
                                rx_ipv4_data_v <= 1'b1;
                            end
                            default : begin
                                rx_ipv4_data_v <= 1'b0;
                            end
                        endcase
                    end
                    default : begin
                        rx_ipv4_data_v <= 1'b0;
                    end
                endcase
            end else begin
                rx_ipv4_data_v <= 1'b0;
            end
        end
    end
endmodule
module rx_ipv4 #(
    parameter   OCT = 8,
    parameter   UDP = 8'h11
)(
    input   wire                rst,
    input   wire                func_en,
    input   wire    [OCT*4-1:0] ip_addr,
    output  reg     [OCT*4-1:0] rx_src_ip,
    output  reg     [3:0]       rx_version,
    output  reg     [3:0]       rx_header_len,
    output  reg     [OCT-1:0]   rx_tos,
    output  reg     [OCT*2-1:0] rx_total_len,
    output  reg     [OCT-1:0]   rx_id,
    output  reg     [OCT*2-1:0] rx_flag_frag,
    output  reg     [OCT-1:0]   rx_ttl,
    output  reg     [OCT-1:0]   rx_protocol,
    output  reg     [OCT-1:0]   rx_checksum,
    input   wire                rx_ethernet_irq,
    output  reg                 rx_ipv4_irq,

    input   wire                RX_CLK,
    input   wire                rx_ethernet_data_v,
    input   wire    [OCT-1:0]   rx_ethernet_data,

    output  reg                 rx_ipv4_data_v,
    output  reg     [OCT-1:0]   rx_ipv4_data
);


    parameter RX_IHL_VER    = 8'b00000000;
    parameter RX_TOS        = 8'b00000001;
    parameter RX_TOTAL_LEN  = 8'b00000011;
    parameter RX_ID         = 8'b00000111;
    parameter RX_FLAG_FRAG  = 8'b00001111;
    parameter RX_TTL        = 8'b00011110;
    parameter RX_PROTOCOL   = 8'b00111110;
    parameter RX_CHECKSUM   = 8'b00111100;
    parameter RX_SRC_IP     = 8'b00011100;
    parameter RX_DST_IP     = 8'b00001100;
    parameter RX_DATA       = 8'b00000100;

    reg [OCT-1:0]   rx_state;

    reg [OCT*4-1:0] rx_dst_ip;

    
    reg [OCT-1:0]   data_cnt;

    always @(posedge RX_CLK) begin 
        if(rst) begin
            rx_state    <= RX_IHL_VER;
            data_cnt    <= 16'h0000;
            rx_ipv4_irq <= 1'b0;
        end else if(func_en) begin
            rx_ipv4_irq <= rx_ethernet_irq;
            if(rx_ethernet_data_v) begin
                case(rx_state)
                    RX_IHL_VER  : begin
                        rx_state    <= RX_TOS;
                        {rx_version, rx_header_len} <= rx_ethernet_data;
                    end
                    RX_TOS      : begin
                        rx_state    <= RX_TOTAL_LEN;
                        rx_tos      <= rx_ethernet_data;
                    end
                    RX_TOTAL_LEN: begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_ID;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_TOTAL_LEN;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_total_len <= {rx_total_len[OCT-1:0], rx_ethernet_data};
                    end
                    RX_ID       : begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_FLAG_FRAG;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_ID;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_id <= {rx_id[OCT-1:0], rx_ethernet_data};
                    end
                    RX_FLAG_FRAG: begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_TTL;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_FLAG_FRAG;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_flag_frag <= {rx_flag_frag[OCT-1:0], rx_ethernet_data};
                    end
                    RX_TTL      : begin
                        rx_state    <= RX_PROTOCOL;
                        rx_ttl      <= rx_ethernet_data;
                    end
                    RX_PROTOCOL : begin
                        rx_state    <= RX_CHECKSUM;
                        rx_protocol <= rx_ethernet_data;
                    end
                    RX_CHECKSUM : begin
                        if(data_cnt == 16'h0001) begin
                            rx_state    <= RX_SRC_IP;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_CHECKSUM;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_checksum <= {rx_checksum[OCT-1:0], rx_ethernet_data};
                    end
                    RX_SRC_IP   : begin
                        if(data_cnt == 16'h0003) begin
                            rx_state    <= RX_DST_IP;
                            data_cnt    <= 16'h0000;
                        end else begin
                            rx_state    <= RX_SRC_IP;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_src_ip <= {rx_src_ip[OCT*3-1:0], rx_ethernet_data};
                    end
                    RX_DST_IP   : begin
                        if(data_cnt == 16'h0003) begin
                            rx_state    <= RX_DATA;

                            data_cnt    <= {10'b00_0000_0000, rx_header_len, 2'b00};
                        end else begin
                            rx_state    <= RX_DST_IP;
                            data_cnt    <= data_cnt + 16'h0001;
                        end
                        rx_dst_ip <= {rx_dst_ip[OCT*3-1:0], rx_ethernet_data};
                    end
                    RX_DATA     : begin
                        rx_ipv4_data <= rx_ethernet_data;

                        case(rx_protocol)
                            UDP : begin
                                rx_ipv4_data_v <= 1'b1;
                            end
                            default : begin
                                rx_ipv4_data_v <= 1'b0;
                            end
                        endcase
                    end
                    default : begin
                        rx_ipv4_data_v <= 1'b0;
                    end
                endcase
            end else begin
                rx_ipv4_data_v <= 1'b0;
            end
        end
    end
endmodule