data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v
1: b"%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:24: Define or directive not defined: '`CLK_PERIOD'\nparameter FCPU = 1000000000/`CLK_PERIOD;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:24: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nparameter FCPU = 1000000000/`CLK_PERIOD;\n                                       ^\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:31: Define or directive not defined: '`clk'\nalways @(posedge `clk or negedge `rst_b)\n                 ^~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:31: syntax error, unexpected or, expecting TYPE-IDENTIFIER\nalways @(posedge `clk or negedge `rst_b)\n                      ^~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:31: Define or directive not defined: '`rst_b'\nalways @(posedge `clk or negedge `rst_b)\n                                 ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:33: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:62: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:62: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\nalways @(posedge baud_clk or negedge `rst_b)\n                                           ^\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:64: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:73: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:73: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\nalways @(posedge baud_clk or negedge `rst_b)\n                                           ^\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:75: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:83: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:85: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:93: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:95: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:103: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:105: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:115: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:115: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\nalways @(posedge baud_clk or negedge `rst_b)\n                                           ^\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:117: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:125: Define or directive not defined: '`rst_b'\nalways @(posedge baud_clk or negedge `rst_b)\n                                     ^~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/logical/tb/uart_mnt.v:127: Define or directive not defined: '`rst_b'\n  if(!`rst_b)\n      ^~~~~~\n%Error: Exiting due to 23 error(s)\n"
module uart_mnt();




parameter FCPU = 1000000000/`CLK_PERIOD;
parameter BAUD = 19200;
parameter CYCLE_CUNT=FCPU/(BAUD*16) - 1;


reg[31:0] div_counter;

always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
  begin
    div_counter[31:0]<=CYCLE_CUNT;
  end
  else if(div_counter[31:0]==32'b0)
  begin
    div_counter[31:0]<=CYCLE_CUNT;
  end
  else 
  begin
    div_counter[31:0]<=div_counter[31:0] - 1'b1;
  end
end

assign baud_clk=(div_counter[31:0]>=(CYCLE_CUNT/2))?0:1;






reg sout_flop;
reg trig_count_en;
reg [4:0] trig_count;
reg shift_en;
reg [3:0] shift_count;
reg [3:0] capture_time;
reg[7:0] pack_data;

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    sout_flop<=1'b0;
  else
    sout_flop<=`sout;
end

assign trig = sout_flop && !`sout && !shift_en;


always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    trig_count_en<=1'b0;
  else if(trig)
    trig_count_en<=1'b1;
  else if(shift_en)
    trig_count_en<=1'b0;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    trig_count[4:0]<=5'b0;
  else if(!trig_count_en)
    trig_count[4:0]<=5'b0;
  else if(trig_count_en)
    trig_count[4:0]<= trig_count[4:0] + 1;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    shift_en<=1'b0;
  else if(trig_count[4:0]==22)
    shift_en<=1'b1;
  else if(capture_time[3:0]==8)
    shift_en<=1'b0;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    shift_count[3:0]<=4'b0;
  else if(trig)
    shift_count[3:0]<=4'b0;
  else if(shift_en)
    shift_count[3:0]<= shift_count[3:0] + 1;
end

assign capture_en = shift_en && (shift_count[3:0]==0);

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    capture_time[3:0]<=4'b0;
  else if(trig)
    capture_time[3:0]<=4'b0;
  else if(capture_en)
    capture_time[3:0]<= capture_time[3:0] + 1;
  end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
  begin 
    pack_data[7:0]<=8'b0;
  end
  else if (capture_en)
  begin
    pack_data[7:0]<={`sout,pack_data[7:1]};
  end
  else 
  begin
    pack_data[7:0]<=pack_data[7:0];
  end
end

assign print_en = (capture_time[3:0]==8) && shift_en;




integer output_file;

initial
begin
  output_file=$fopen("uart_output.inf","w");
end

always @(posedge baud_clk )
begin
  if(print_en)
  begin
    $fwrite(output_file,"%C",pack_data[7:0]);
    $write("\033[0;31m%C\033[0m",pack_data[7:0]);
  end 
end

endmodule
module uart_mnt();





parameter FCPU = 1000000000/`CLK_PERIOD;
parameter BAUD = 19200;
parameter CYCLE_CUNT=FCPU/(BAUD*16) - 1;


reg[31:0] div_counter;

always @(posedge `clk or negedge `rst_b)
begin
  if(!`rst_b)
  begin
    div_counter[31:0]<=CYCLE_CUNT;
  end
  else if(div_counter[31:0]==32'b0)
  begin
    div_counter[31:0]<=CYCLE_CUNT;
  end
  else 
  begin
    div_counter[31:0]<=div_counter[31:0] - 1'b1;
  end
end

assign baud_clk=(div_counter[31:0]>=(CYCLE_CUNT/2))?0:1;






reg sout_flop;
reg trig_count_en;
reg [4:0] trig_count;
reg shift_en;
reg [3:0] shift_count;
reg [3:0] capture_time;
reg[7:0] pack_data;

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    sout_flop<=1'b0;
  else
    sout_flop<=`sout;
end

assign trig = sout_flop && !`sout && !shift_en;


always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    trig_count_en<=1'b0;
  else if(trig)
    trig_count_en<=1'b1;
  else if(shift_en)
    trig_count_en<=1'b0;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    trig_count[4:0]<=5'b0;
  else if(!trig_count_en)
    trig_count[4:0]<=5'b0;
  else if(trig_count_en)
    trig_count[4:0]<= trig_count[4:0] + 1;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    shift_en<=1'b0;
  else if(trig_count[4:0]==22)
    shift_en<=1'b1;
  else if(capture_time[3:0]==8)
    shift_en<=1'b0;
end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    shift_count[3:0]<=4'b0;
  else if(trig)
    shift_count[3:0]<=4'b0;
  else if(shift_en)
    shift_count[3:0]<= shift_count[3:0] + 1;
end

assign capture_en = shift_en && (shift_count[3:0]==0);

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
    capture_time[3:0]<=4'b0;
  else if(trig)
    capture_time[3:0]<=4'b0;
  else if(capture_en)
    capture_time[3:0]<= capture_time[3:0] + 1;
  end

always @(posedge baud_clk or negedge `rst_b)
begin
  if(!`rst_b)
  begin 
    pack_data[7:0]<=8'b0;
  end
  else if (capture_en)
  begin
    pack_data[7:0]<={`sout,pack_data[7:1]};
  end
  else 
  begin
    pack_data[7:0]<=pack_data[7:0];
  end
end

assign print_en = (capture_time[3:0]==8) && shift_en;




integer output_file;

initial
begin
  output_file=$fopen("uart_output.inf","w");
end

always @(posedge baud_clk )
begin
  if(print_en)
  begin
    $fwrite(output_file,"%C",pack_data[7:0]);
    $write("\033[0;31m%C\033[0m",pack_data[7:0]);
  end 
end

endmodule