data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/InstructionFetch/HardInstructionMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/InstructionFetch/HardInstructionMemory.v:33: Bit extraction of array[256:0] requires 9 bit index, not 8 bits.\n                                                                                                                                        : ... In instance HardInstructionMemory\n            instruction = hardMemory[address[9:2]];\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module HardInstructionMemory(
    input [63:0] address,

    output reg [31:0] instruction
);

    reg [31:0] hardMemory [0:256];

    integer i;

    initial begin
        for (i = 0; i < 1024; i = i + 1)
            hardMemory[i] = 32'b10011;


        
    end
    
    always @(*) begin
        if (|address[63:10] == 0)
            instruction = hardMemory[address[9:2]];
        else
            instruction = 32'b10011;
    end

endmodule
module HardInstructionMemory(
    input [63:0] address,

    output reg [31:0] instruction
);


    reg [31:0] hardMemory [0:256];

    integer i;

    initial begin
        for (i = 0; i < 1024; i = i + 1)
            hardMemory[i] = 32'b10011;


        
    end
    
    always @(*) begin
        if (|address[63:10] == 0)
            instruction = hardMemory[address[9:2]];
        else
            instruction = 32'b10011;
    end

endmodule