data/full_repos/permissive/485129576/reg2.v
data/verilator_xmls/1f1c7961-c2db-4fab-88de-ba1037eca7f4.xml
module REG2 (
    input clkR,
    input [1:0] D,
    output reg [1:0] Q
);
    initial begin
        Q = 2'b0;
    end

    always @(posedge clkR) begin
        Q = D;
    end

endmodule
module REG2 (
    input clkR,
    input [1:0] D,
    output reg [1:0] Q
);

    initial begin
        Q = 2'b0;
    end

    always @(posedge clkR) begin
        Q = D;
    end

endmodule