data/full_repos/permissive/447283927/main.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447283927/main.v:70: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] ForwardAE, ForwardBE;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447283927/main.v:77: Cannot find file containing module: \'hazard_controller\'\nhazard_controller hc(ForwardAE, ForwardBE, StallF, StallD, FlushD, rs1, rs2, FlushE , RdE, beqE, jump_flag, ResultSrcE, Rs1E, Rs2E, RdM, RegWriteM, RdW, RegWriteW);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/hazard_controller\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/hazard_controller.v\n             data/full_repos/permissive/447283927,data/full_repos/permissive/447283927/hazard_controller.sv\n             hazard_controller\n             hazard_controller.v\n             hazard_controller.sv\n             obj_dir/hazard_controller\n             obj_dir/hazard_controller.v\n             obj_dir/hazard_controller.sv\n%Error: data/full_repos/permissive/447283927/main.v:85: Cannot find file containing module: \'control_unit\'\ncontrol_unit cu(beqD, ResultSrcD, MemWriteD, FunctionD, ALUSrcD, ImmSrcD, RegWriteD, retD, opcode, func3, func7);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:86: Cannot find file containing module: \'Instruction_Memory\'\nInstruction_Memory imem(PCF,InstrF);\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:87: Cannot find file containing module: \'register_file\'\nregister_file rf(RD1D, RD2D, ResultW, rs1, rs2, RdW, RegWriteW,div_clk);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:88: Cannot find file containing module: \'Instruction_fetch\'\nInstruction_fetch ift(InstrD, opcode,func3, func7,RdD,rs1,rs2,immediate);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:89: Cannot find file containing module: \'sign_extend\'\nsign_extend sgext(immediate,ImmExtD,ImmSrcD);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:90: Cannot find file containing module: \'address_generator\'\naddress_generator adgen(PCF, beqE, jump_flag,ImmExtE + PCE, div_clk, rst, StallF, addressSrc, isrAddress);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:91: Cannot find file containing module: \'ALU\'\nALU alu(ALUResultE,alu_z,SrcAE,SrcBE,FunctionE);\n^~~\n%Error: data/full_repos/permissive/447283927/main.v:92: Cannot find file containing module: \'Data_Memory\'\nData_Memory dmem(ReadDataM,WriteDataM, ALUResultM,MemWriteM,div_clk\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:95: Cannot find file containing module: \'fd_reg\'\nfd_reg fd(InstrF,PCF,\n^~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:98: Cannot find file containing module: \'de_reg\'\nde_reg de(\n^~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:104: Cannot find file containing module: \'em_reg\'\nem_reg em(\n^~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:109: Cannot find file containing module: \'mw_reg\'\nmw_reg mw(\n^~~~~~\n%Error: data/full_repos/permissive/447283927/main.v:115: Cannot find file containing module: \'csr\'\ncsr csreg(interrupt, PCE, retE, FlushDCSR, FlushECSR, FlushM, isrAddress , addressSrc);\n^~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module main(rst, clk, alu_z, Anode_Activate, LED_out, BTN_in, interrupt
);
input rst, clk;
output alu_z;
output reg[7:0] Anode_Activate;
output reg [6:0] LED_out;
input [15:0] BTN_in;
input interrupt;




wire [31:0] PCF, PCD,PCE;
wire [31:0] Result;
wire [31:0] InstrF, InstrD;
wire [31:0] ALUResultE, ALUResultM, ALUResultW;
wire [3:0] FunctionD, FunctionE;
wire [31:0] RD1D, RD1E;
wire [31:0]  RD2D, RD2E, WriteDataE, WriteDataM;
wire [31:0] isrAddress;
wire addressSrc;


wire [31:0] SrcAE;
wire [31:0] SrcBE;

wire [31:0] ResultW;
wire [11:0] immediate;
wire [31:0] ImmExtD, ImmExtE;
wire ImmSrcD;
wire beqD, beqE;
wire jump_flag;
wire [31:0] ReadDataM, ReadDataW;
wire MemWriteD, MemWriteE, MemWriteM;
wire [31:0] seg_en;


reg [31:0] counter;
reg [2:0] seg_on;

reg [3:0] display;

wire div_clk;
assign div_clk = clk;





wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] Rs1E, Rs2E;
wire [4:0] RdD, RdE, RdM, RdW;

assign jump_flag = !alu_z;



wire [6:0] opcode;
wire [2:0] func3;
wire [6:0] func7;


wire ResultSrcD, ResultSrcE, ResultSrcM, ResultSrcW;
wire ALUSrcD, ALUSrcE;
wire RegWriteD, RegWriteE, RegWriteM, RegWriteW;


wire [0:1] ForwardAE, ForwardBE;

assign SrcAE = (ForwardAE == 0)? RD1E: ( (ForwardAE == 1)? ResultW : ALUResultM );
wire [31:0] RD2E_mul;
wire StallD, FlushD, FlushE, StallF, FlushM, retE, retD, FlushDCSR, FlushECSR; 
assign SrcBE = ALUSrcE ? ImmExtE : RD2E_mul;
assign RD2E_mul = (ForwardBE == 0)? RD2E: ( (ForwardBE == 1)? ResultW : ALUResultM );
hazard_controller hc(ForwardAE, ForwardBE, StallF, StallD, FlushD, rs1, rs2, FlushE , RdE, beqE, jump_flag, ResultSrcE, Rs1E, Rs2E, RdM, RegWriteM, RdW, RegWriteW);


assign WriteDataE = RD2E_mul;


assign ResultW = ResultSrcW ? ReadDataW : ALUResultW;

control_unit cu(beqD, ResultSrcD, MemWriteD, FunctionD, ALUSrcD, ImmSrcD, RegWriteD, retD, opcode, func3, func7);
Instruction_Memory imem(PCF,InstrF);
register_file rf(RD1D, RD2D, ResultW, rs1, rs2, RdW, RegWriteW,div_clk);
Instruction_fetch ift(InstrD, opcode,func3, func7,RdD,rs1,rs2,immediate);
sign_extend sgext(immediate,ImmExtD,ImmSrcD);
address_generator adgen(PCF, beqE, jump_flag,ImmExtE + PCE, div_clk, rst, StallF, addressSrc, isrAddress);
ALU alu(ALUResultE,alu_z,SrcAE,SrcBE,FunctionE);
Data_Memory dmem(ReadDataM,WriteDataM, ALUResultM,MemWriteM,div_clk
    ,Result,seg_en, BTN_in);

fd_reg fd(InstrF,PCF,
InstrD,PCD, div_clk, StallD, FlushD | FlushDCSR);

de_reg de(
RegWriteD, ResultSrcD, MemWriteD,beqD, FunctionD, ALUSrcD, RD1D, RD2D, PCD, RdD,ImmExtD,rs1, rs2, retD,
RegWriteE, ResultSrcE, MemWriteE, beqE, FunctionE, ALUSrcE, RD1E, RD2E, PCE, RdE, ImmExtE, Rs1E, Rs2E, retE,
div_clk, FlushE | FlushECSR
);

em_reg em(
 RegWriteE ,ResultSrcE,MemWriteE ,ALUResultE,WriteDataE,RdE,
 RegWriteM, ResultSrcM, MemWriteM ,ALUResultM, WriteDataM,RdM ,div_clk, FlushM      
);

mw_reg mw(
RegWriteM,ResultSrcM, ALUResultM, ReadDataM, RdM,
RegWriteW, ResultSrcW, ALUResultW, ReadDataW, RdW,
div_clk
    );
    
csr csreg(interrupt, PCE, retE, FlushDCSR, FlushECSR, FlushM, isrAddress , addressSrc);




always @(posedge clk)
    begin
            if(counter>=100000) begin
                counter <= 0;
                if (seg_on == 3'b111)
                begin
                    seg_on <= 0;
                end
                else
                begin
                    seg_on <= seg_on + 1;
                end
                end
                else 
                begin
                counter <= counter + 1;
				end
    end 


    always @(*)
    begin
        case(seg_on)
        3'd0: begin
            Anode_Activate = 8'b01111111 + ~seg_en[7:0]; 
            display = Result[31:28];
              end
        3'd1: begin
            Anode_Activate = 8'b10111111 + ~seg_en[7:0]; 
            display = Result[27:24];
            end
        3'd2: begin
            Anode_Activate = 8'b11011111 + ~seg_en[7:0];
            display = Result[23:20];
            end
                    
        3'd3: begin
             Anode_Activate = 8'b11101111 + ~seg_en[7:0];
             display = Result[19:16];
             end
                    
        3'd4: begin
            Anode_Activate = 8'b11110111 + ~seg_en[7:0];
            display = Result[15:12];
        end                                
                    
        3'd5: begin
            Anode_Activate = 8'b11111011 + ~seg_en[7:0];
            display = Result[11:8];
        end  
        3'd6: begin
            Anode_Activate = 8'b11111101 + ~seg_en[7:0];
            display = Result[7:4];
        end
        3'd7: begin
            Anode_Activate = 8'b11111110 + ~seg_en[7:0];
            display = Result[3:0];
        end 
                                                                          
        endcase
    end
    

    always @(*)
    begin
    case(display)
            4'b0000: LED_out = 7'b0000001;
            4'b0001: LED_out = 7'b1001111;
            4'b0010: LED_out = 7'b0010010;
            4'b0011: LED_out = 7'b0000110;
            4'b0100: LED_out = 7'b1001100;
            4'b0101: LED_out = 7'b0100100;
            4'b0110: LED_out = 7'b0100000;
            4'b0111: LED_out = 7'b0001111;
            4'b1000: LED_out = 7'b0000000;
            4'b1001: LED_out = 7'b0000100;
            4'b1010: LED_out = 7'b0001000;
            4'b1011: LED_out = 7'b1100000;
            4'b1100: LED_out = 7'b0110001;
            4'b1101: LED_out = 7'b1000010;
            4'b1110: LED_out = 7'b0110000;
            4'b1111: LED_out = 7'b0111000;
            
            default: LED_out = 7'b0111000;
            endcase
    end

endmodule
module main(rst, clk, alu_z, Anode_Activate, LED_out, BTN_in, interrupt
);

input rst, clk;
output alu_z;
output reg[7:0] Anode_Activate;
output reg [6:0] LED_out;
input [15:0] BTN_in;
input interrupt;




wire [31:0] PCF, PCD,PCE;
wire [31:0] Result;
wire [31:0] InstrF, InstrD;
wire [31:0] ALUResultE, ALUResultM, ALUResultW;
wire [3:0] FunctionD, FunctionE;
wire [31:0] RD1D, RD1E;
wire [31:0]  RD2D, RD2E, WriteDataE, WriteDataM;
wire [31:0] isrAddress;
wire addressSrc;


wire [31:0] SrcAE;
wire [31:0] SrcBE;

wire [31:0] ResultW;
wire [11:0] immediate;
wire [31:0] ImmExtD, ImmExtE;
wire ImmSrcD;
wire beqD, beqE;
wire jump_flag;
wire [31:0] ReadDataM, ReadDataW;
wire MemWriteD, MemWriteE, MemWriteM;
wire [31:0] seg_en;


reg [31:0] counter;
reg [2:0] seg_on;

reg [3:0] display;

wire div_clk;
assign div_clk = clk;





wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] Rs1E, Rs2E;
wire [4:0] RdD, RdE, RdM, RdW;

assign jump_flag = !alu_z;



wire [6:0] opcode;
wire [2:0] func3;
wire [6:0] func7;


wire ResultSrcD, ResultSrcE, ResultSrcM, ResultSrcW;
wire ALUSrcD, ALUSrcE;
wire RegWriteD, RegWriteE, RegWriteM, RegWriteW;


wire [0:1] ForwardAE, ForwardBE;

assign SrcAE = (ForwardAE == 0)? RD1E: ( (ForwardAE == 1)? ResultW : ALUResultM );
wire [31:0] RD2E_mul;
wire StallD, FlushD, FlushE, StallF, FlushM, retE, retD, FlushDCSR, FlushECSR; 
assign SrcBE = ALUSrcE ? ImmExtE : RD2E_mul;
assign RD2E_mul = (ForwardBE == 0)? RD2E: ( (ForwardBE == 1)? ResultW : ALUResultM );
hazard_controller hc(ForwardAE, ForwardBE, StallF, StallD, FlushD, rs1, rs2, FlushE , RdE, beqE, jump_flag, ResultSrcE, Rs1E, Rs2E, RdM, RegWriteM, RdW, RegWriteW);


assign WriteDataE = RD2E_mul;


assign ResultW = ResultSrcW ? ReadDataW : ALUResultW;

control_unit cu(beqD, ResultSrcD, MemWriteD, FunctionD, ALUSrcD, ImmSrcD, RegWriteD, retD, opcode, func3, func7);
Instruction_Memory imem(PCF,InstrF);
register_file rf(RD1D, RD2D, ResultW, rs1, rs2, RdW, RegWriteW,div_clk);
Instruction_fetch ift(InstrD, opcode,func3, func7,RdD,rs1,rs2,immediate);
sign_extend sgext(immediate,ImmExtD,ImmSrcD);
address_generator adgen(PCF, beqE, jump_flag,ImmExtE + PCE, div_clk, rst, StallF, addressSrc, isrAddress);
ALU alu(ALUResultE,alu_z,SrcAE,SrcBE,FunctionE);
Data_Memory dmem(ReadDataM,WriteDataM, ALUResultM,MemWriteM,div_clk
    ,Result,seg_en, BTN_in);

fd_reg fd(InstrF,PCF,
InstrD,PCD, div_clk, StallD, FlushD | FlushDCSR);

de_reg de(
RegWriteD, ResultSrcD, MemWriteD,beqD, FunctionD, ALUSrcD, RD1D, RD2D, PCD, RdD,ImmExtD,rs1, rs2, retD,
RegWriteE, ResultSrcE, MemWriteE, beqE, FunctionE, ALUSrcE, RD1E, RD2E, PCE, RdE, ImmExtE, Rs1E, Rs2E, retE,
div_clk, FlushE | FlushECSR
);

em_reg em(
 RegWriteE ,ResultSrcE,MemWriteE ,ALUResultE,WriteDataE,RdE,
 RegWriteM, ResultSrcM, MemWriteM ,ALUResultM, WriteDataM,RdM ,div_clk, FlushM      
);

mw_reg mw(
RegWriteM,ResultSrcM, ALUResultM, ReadDataM, RdM,
RegWriteW, ResultSrcW, ALUResultW, ReadDataW, RdW,
div_clk
    );
    
csr csreg(interrupt, PCE, retE, FlushDCSR, FlushECSR, FlushM, isrAddress , addressSrc);




always @(posedge clk)
    begin
            if(counter>=100000) begin
                counter <= 0;
                if (seg_on == 3'b111)
                begin
                    seg_on <= 0;
                end
                else
                begin
                    seg_on <= seg_on + 1;
                end
                end
                else 
                begin
                counter <= counter + 1;
				end
    end 


    always @(*)
    begin
        case(seg_on)
        3'd0: begin
            Anode_Activate = 8'b01111111 + ~seg_en[7:0]; 
            display = Result[31:28];
              end
        3'd1: begin
            Anode_Activate = 8'b10111111 + ~seg_en[7:0]; 
            display = Result[27:24];
            end
        3'd2: begin
            Anode_Activate = 8'b11011111 + ~seg_en[7:0];
            display = Result[23:20];
            end
                    
        3'd3: begin
             Anode_Activate = 8'b11101111 + ~seg_en[7:0];
             display = Result[19:16];
             end
                    
        3'd4: begin
            Anode_Activate = 8'b11110111 + ~seg_en[7:0];
            display = Result[15:12];
        end                                
                    
        3'd5: begin
            Anode_Activate = 8'b11111011 + ~seg_en[7:0];
            display = Result[11:8];
        end  
        3'd6: begin
            Anode_Activate = 8'b11111101 + ~seg_en[7:0];
            display = Result[7:4];
        end
        3'd7: begin
            Anode_Activate = 8'b11111110 + ~seg_en[7:0];
            display = Result[3:0];
        end 
                                                                          
        endcase
    end
    

    always @(*)
    begin
    case(display)
            4'b0000: LED_out = 7'b0000001;
            4'b0001: LED_out = 7'b1001111;
            4'b0010: LED_out = 7'b0010010;
            4'b0011: LED_out = 7'b0000110;
            4'b0100: LED_out = 7'b1001100;
            4'b0101: LED_out = 7'b0100100;
            4'b0110: LED_out = 7'b0100000;
            4'b0111: LED_out = 7'b0001111;
            4'b1000: LED_out = 7'b0000000;
            4'b1001: LED_out = 7'b0000100;
            4'b1010: LED_out = 7'b0001000;
            4'b1011: LED_out = 7'b1100000;
            4'b1100: LED_out = 7'b0110001;
            4'b1101: LED_out = 7'b1000010;
            4'b1110: LED_out = 7'b0110000;
            4'b1111: LED_out = 7'b0111000;
            
            default: LED_out = 7'b0111000;
            endcase
    end

endmodule