data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/tb_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/tb_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/tb_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire [7:0]  A;
wire [2:0]  Y;

encoder_test tester (.t1(A), .t2(Y));


encoder         dut (.A(A), .Y(Y));

always @(A or Y)
begin
    #1;
    $display("%8b %3b",A,Y);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire [7:0]  A;
wire [2:0]  Y;

encoder_test tester (.t1(A), .t2(Y));


encoder         dut (.A(A), .Y(Y));

always @(A or Y)
begin
    #1;
    $display("%8b %3b",A,Y);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule