data/full_repos/permissive/444465810/func/axi/PC.v
data/verilator_xmls/2ea4cbac-0294-4efe-8371-fe0f944706b9.xml
module PC(
    input clk,
    input rst,
    input PCWr,
    input [31:0]NPC,
    output reg[31:0] PC
);
always @(posedge clk) begin
    if(rst)
        PC <= 32'hBFC00000;
    else if(PCWr)begin
        PC <= NPC;
    end
end
endmodule
module PC(
    input clk,
    input rst,
    input PCWr,
    input [31:0]NPC,
    output reg[31:0] PC
);

always @(posedge clk) begin
    if(rst)
        PC <= 32'hBFC00000;
    else if(PCWr)begin
        PC <= NPC;
    end
end
endmodule