data/full_repos/permissive/506268796/M.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/506268796/M.v:37: Multiple top level modules\n                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                              : ... Top module \'spiclkgen\'\nmodule spiclkgen(input clk\n       ^~~~~~~~~\n                                                              : ... Top module \'linespitransmitter\'\nmodule linespitransmitter(input clk\n       ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/506268796/M.v:114: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel\' generates 33 bits.\n                                                            : ... In instance linespitransmitter\n                    pixel_reg <= pixel;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/506268796/M.v:128: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel\' generates 33 bits.\n                                                            : ... In instance linespitransmitter\n                        pixel_reg <= pixel;                        \n                                  ^~\n%Error: Exiting due to 3 warning(s)\n'
module spiclkgen(input clk
    , input rst
    ,   output reg clk_dvd
    ,   output reg shifted
    , output reg mreset
);

    reg [3:0] cntr;
    
    wire [1:0] cnt;
    
    assign cnt = cntr[1:0];

    
    always @(posedge clk) begin
        if (~rst) begin
            cntr <= cntr + 1;
            if (cnt == 0) begin
                clk_dvd <= ~clk_dvd;
            end
            if (cnt == 1) begin
                shifted <= ~shifted;
            end
            if (cntr == 15) begin
                mreset <= 0;
            end
        end else begin
            cntr <= 0;
            clk_dvd <= 0;
            shifted <= 1;
            mreset <= 1;
        end
    end
    
endmodule
module spiclkgen(input clk
    , input rst
    ,   output reg clk_dvd
    ,   output reg shifted
    , output reg mreset
);


    reg [3:0] cntr;
    
    wire [1:0] cnt;
    
    assign cnt = cntr[1:0];

    
    always @(posedge clk) begin
        if (~rst) begin
            cntr <= cntr + 1;
            if (cnt == 0) begin
                clk_dvd <= ~clk_dvd;
            end
            if (cnt == 1) begin
                shifted <= ~shifted;
            end
            if (cntr == 15) begin
                mreset <= 0;
            end
        end else begin
            cntr <= 0;
            clk_dvd <= 0;
            shifted <= 1;
            mreset <= 1;
        end
    end
    
endmodule