data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v
1: b"%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v:25: Cannot find file containing module: 'FMADD_LZD_layer_0'\nFMADD_LZD_layer_0 L0 (.L0_input_man_48(FMADD_PN_LZD_input_man_48), .L0_output_pos_val(LZD_wire_output_L0));\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FMADD_LZD_layer_0\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FMADD_LZD_layer_0.v\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FMADD_LZD_layer_0.sv\n             FMADD_LZD_layer_0\n             FMADD_LZD_layer_0.v\n             FMADD_LZD_layer_0.sv\n             obj_dir/FMADD_LZD_layer_0\n             obj_dir/FMADD_LZD_layer_0.v\n             obj_dir/FMADD_LZD_layer_0.sv\n%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v:28: Cannot find file containing module: 'FMADD_LZD_layer_1'\nFMADD_LZD_layer_1 L1 (.L1_input_pos_val(LZD_wire_output_L0), .L1_output_pos_val(LZD_wire_output_L1));\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v:31: Cannot find file containing module: 'FMADD_LZD_layer_2'\nFMADD_LZD_layer_2 L2 (.L2_input_pos_val(LZD_wire_output_L1), .L2_output_pos_val(LZD_wire_output_L2));\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v:34: Cannot find file containing module: 'FMADD_LZD_layer_3'\nFMADD_LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3));\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_main.v:37: Cannot find file containing module: 'FMADD_LZD_layer_4'\nFMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos_interim_1));\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module FMADD_PN_LZD (FMADD_PN_LZD_input_man_48, FMADD_PN_LZD_output_pos);

parameter lzd = 4;
parameter man = 22;

input [23 : 0]FMADD_PN_LZD_input_man_48;

output [lzd : 0]FMADD_PN_LZD_output_pos;

wire [4 : 0]FMADD_PN_LZD_output_pos_interim_1;
wire [5 : 0]FMADD_PN_LZD_output_pos_interim_2;

wire [23 : 0] LZD_wire_output_L0;
wire [17 : 0] LZD_wire_output_L1;
wire [11 : 0] LZD_wire_output_L2;
wire [9 : 0] LZD_wire_output_L3;


FMADD_LZD_layer_0 L0 (.L0_input_man_48(FMADD_PN_LZD_input_man_48), .L0_output_pos_val(LZD_wire_output_L0));


FMADD_LZD_layer_1 L1 (.L1_input_pos_val(LZD_wire_output_L0), .L1_output_pos_val(LZD_wire_output_L1));


FMADD_LZD_layer_2 L2 (.L2_input_pos_val(LZD_wire_output_L1), .L2_output_pos_val(LZD_wire_output_L2));


FMADD_LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3));


FMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos_interim_1));

assign FMADD_PN_LZD_output_pos_interim_2 = 
(man == 22) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b011000) :
(man == 9 ) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101011) :
			  (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101000) ;


assign FMADD_PN_LZD_output_pos = FMADD_PN_LZD_output_pos_interim_2[lzd : 0];

endmodule
module FMADD_PN_LZD (FMADD_PN_LZD_input_man_48, FMADD_PN_LZD_output_pos);


parameter lzd = 4;
parameter man = 22;

input [23 : 0]FMADD_PN_LZD_input_man_48;

output [lzd : 0]FMADD_PN_LZD_output_pos;

wire [4 : 0]FMADD_PN_LZD_output_pos_interim_1;
wire [5 : 0]FMADD_PN_LZD_output_pos_interim_2;

wire [23 : 0] LZD_wire_output_L0;
wire [17 : 0] LZD_wire_output_L1;
wire [11 : 0] LZD_wire_output_L2;
wire [9 : 0] LZD_wire_output_L3;


FMADD_LZD_layer_0 L0 (.L0_input_man_48(FMADD_PN_LZD_input_man_48), .L0_output_pos_val(LZD_wire_output_L0));


FMADD_LZD_layer_1 L1 (.L1_input_pos_val(LZD_wire_output_L0), .L1_output_pos_val(LZD_wire_output_L1));


FMADD_LZD_layer_2 L2 (.L2_input_pos_val(LZD_wire_output_L1), .L2_output_pos_val(LZD_wire_output_L2));


FMADD_LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3));


FMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos_interim_1));

assign FMADD_PN_LZD_output_pos_interim_2 = 
(man == 22) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b011000) :
(man == 9 ) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101011) :
			  (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101000) ;


assign FMADD_PN_LZD_output_pos = FMADD_PN_LZD_output_pos_interim_2[lzd : 0];

endmodule