data/full_repos/permissive/516809949/digital/rtl/clkg.v
1: b"%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:65: Cannot find file containing module: 'CKLNQD1'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.v\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:116: Cannot find file containing module: 'INVLONG_OSC37'\n    INVLONG_OSC37 U_CLK_OSC(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:122: Cannot find file containing module: 'INVD2'\n    INVD2 U_CLK_OSC_DRV(\n    ^~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:126: Cannot find file containing module: 'MUX2D0'\n    MUX2D0 U_MUX2_JTAG_OSC(\n    ^~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:139: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_SMP(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:145: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_NCM(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:151: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_MSK(\n    ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module clkg (
    input  wire        clk_jtag,
    input  wire        rst_n,
    input  wire        i_osc_en,
    input  wire        i_clk_en,
    input  wire        i_smp_en,
    input  wire        i_ncm_en,
    input  wire        i_msk_en,
    input  wire [2:0]  i_clk_div,
    output wire        o_clk,
    output wire        o_clk_smp,
    output wire        o_clk_ncm,
    output wire        o_clk_msk);

    wire clk_osc_pre;
    wire clk_osc;
    wire clk_glitch;

    INVLONG_OSC37 U_CLK_OSC(
        .EN  ( i_osc_en     ),
        .OUT ( clk_osc_pre  ) );


    INVD2 U_CLK_OSC_DRV(
        .I  ( clk_osc_pre ),
        .ZN ( clk_osc     ) );

    MUX2D0 U_MUX2_JTAG_OSC(
        .I0( clk_jtag       ),
        .I1( clk_osc        ),
        .S ( i_osc_en       ),
        .Z ( clk_glitch     ) );

    clkdiv U_CLKDIV(
        .clk         ( clk_glitch ) ,
        .rst_n       ( rst_n      ) ,
        .i_en        ( i_clk_en   ) ,
        .i_div       ( i_clk_div  ) ,
        .o_clk_div   ( o_clk      ) );

    CKLNQD1 U_CLK_GATE_SMP(
        .TE ( 1'b0       ) ,
        .E  ( i_smp_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_smp  ) );

    CKLNQD1 U_CLK_GATE_NCM(
        .TE ( 1'b0       ) ,
        .E  ( i_ncm_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_ncm  ) );

    CKLNQD1 U_CLK_GATE_MSK(
        .TE ( 1'b0       ) ,
        .E  ( i_msk_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_msk  ) );

endmodule
module clkg (
    input  wire        clk_jtag,
    input  wire        rst_n,
    input  wire        i_osc_en,
    input  wire        i_clk_en,
    input  wire        i_smp_en,
    input  wire        i_ncm_en,
    input  wire        i_msk_en,
    input  wire [2:0]  i_clk_div,
    output wire        o_clk,
    output wire        o_clk_smp,
    output wire        o_clk_ncm,
    output wire        o_clk_msk);


    wire clk_osc_pre;
    wire clk_osc;
    wire clk_glitch;

    INVLONG_OSC37 U_CLK_OSC(
        .EN  ( i_osc_en     ),
        .OUT ( clk_osc_pre  ) );


    INVD2 U_CLK_OSC_DRV(
        .I  ( clk_osc_pre ),
        .ZN ( clk_osc     ) );

    MUX2D0 U_MUX2_JTAG_OSC(
        .I0( clk_jtag       ),
        .I1( clk_osc        ),
        .S ( i_osc_en       ),
        .Z ( clk_glitch     ) );

    clkdiv U_CLKDIV(
        .clk         ( clk_glitch ) ,
        .rst_n       ( rst_n      ) ,
        .i_en        ( i_clk_en   ) ,
        .i_div       ( i_clk_div  ) ,
        .o_clk_div   ( o_clk      ) );

    CKLNQD1 U_CLK_GATE_SMP(
        .TE ( 1'b0       ) ,
        .E  ( i_smp_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_smp  ) );

    CKLNQD1 U_CLK_GATE_NCM(
        .TE ( 1'b0       ) ,
        .E  ( i_ncm_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_ncm  ) );

    CKLNQD1 U_CLK_GATE_MSK(
        .TE ( 1'b0       ) ,
        .E  ( i_msk_en   ) ,
        .CP ( o_clk      ) ,
        .Q  ( o_clk_msk  ) );

endmodule