data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:107: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:108: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:113: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module part3(iColour,iResetn,iClock,oX,oY,oColour,oPlot);
	
	input wire [2:0] iColour;
	input wire iResetn, iClock;
	
	output wire [7:0] oX;
	output wire [6:0] oY;
	output wire [2:0] oColour;
	output wire oPlot;
	
	parameter X_SCREENSIZE = 160, Y_SCREENSIZE = 120, CLOCKS_PER_SECOND = 5000, X_BOXSIZE = 8'd4, Y_BOXSIZE = 7'd4, X_MAX = X_SCREENSIZE - 1 - X_BOXSIZE, Y_MAX = Y_SCREENSIZE - 1 - Y_BOXSIZE, PULSES_PER_SIXTIETH_SECOND = CLOCKS_PER_SECOND / 60;
	
	wire Frame_next_ld, Create_enable, Black_enable, Move_enable, Count_enable;
	wire [3:0] Counter;
	
	RateDivider u0(iClock, iResetn, PULSES_PER_SIXTIETH_SECOND, Count_enable);
	FrameCounter u1(iClock, iResetn, Count_enable, Frame_next_ld);
	datapath u2(iClock, iResetn, iColour, X_MAX, Y_MAX, oX, oY, oColour, Counter, Create_enable, Black_enable, Move_enable);
	controlpath u3(iClock, iResetn, Counter, Frame_next_ld, oPlot, Create_enable, Black_enable, Move_enable);

endmodule
module part3(iColour,iResetn,iClock,oX,oY,oColour,oPlot);

	
	input wire [2:0] iColour;
	input wire iResetn, iClock;
	
	output wire [7:0] oX;
	output wire [6:0] oY;
	output wire [2:0] oColour;
	output wire oPlot;
	
	parameter X_SCREENSIZE = 160, Y_SCREENSIZE = 120, CLOCKS_PER_SECOND = 5000, X_BOXSIZE = 8'd4, Y_BOXSIZE = 7'd4, X_MAX = X_SCREENSIZE - 1 - X_BOXSIZE, Y_MAX = Y_SCREENSIZE - 1 - Y_BOXSIZE, PULSES_PER_SIXTIETH_SECOND = CLOCKS_PER_SECOND / 60;
	
	wire Frame_next_ld, Create_enable, Black_enable, Move_enable, Count_enable;
	wire [3:0] Counter;
	
	RateDivider u0(iClock, iResetn, PULSES_PER_SIXTIETH_SECOND, Count_enable);
	FrameCounter u1(iClock, iResetn, Count_enable, Frame_next_ld);
	datapath u2(iClock, iResetn, iColour, X_MAX, Y_MAX, oX, oY, oColour, Counter, Create_enable, Black_enable, Move_enable);
	controlpath u3(iClock, iResetn, Counter, Frame_next_ld, oPlot, Create_enable, Black_enable, Move_enable);

endmodule