data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/enconder_tst.v:37: Cannot find file containing module: \'Encoder\'\n Encoder uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/Encoder\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/Encoder.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/Encoder.sv\n             Encoder\n             Encoder.v\n             Encoder.sv\n             obj_dir/Encoder\n             obj_dir/Encoder.v\n             obj_dir/Encoder.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module enconder_tst;


	reg [15:0] Theta;
	reg [15:0] Ref;
	reg [31:0] DataIn;


	wire [7:0] Address;
	wire [31:0] DataOut;


	Encoder uut (
		.Theta(Theta), 
		.Ref(Ref), 
		.DataIn(DataIn), 
		.Address(Address), 
		.DataOut(DataOut)
	);

	initial begin

		Theta = 45;
		Ref = 45;
		DataIn = 1234;


		#100;

		
		#10;
		Theta = 47;
		#10;
		Theta = 48;
		#10;
		Theta = 43;
		#10;
		Theta = 40;
		
	end
      
endmodule
module enconder_tst;



	reg [15:0] Theta;
	reg [15:0] Ref;
	reg [31:0] DataIn;


	wire [7:0] Address;
	wire [31:0] DataOut;


	Encoder uut (
		.Theta(Theta), 
		.Ref(Ref), 
		.DataIn(DataIn), 
		.Address(Address), 
		.DataOut(DataOut)
	);

	initial begin

		Theta = 45;
		Ref = 45;
		DataIn = 1234;


		#100;

		
		#10;
		Theta = 47;
		#10;
		Theta = 48;
		#10;
		Theta = 43;
		#10;
		Theta = 40;
		
	end
      
endmodule