data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:335: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_dmapack'\nNV_NVDLA_SDP_CORE_Y_dmapack u_alu_dmapack (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_CORE_Y_dmapack\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_CORE_Y_dmapack.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_CORE_Y_dmapack.sv\n             NV_NVDLA_SDP_CORE_Y_dmapack\n             NV_NVDLA_SDP_CORE_Y_dmapack.v\n             NV_NVDLA_SDP_CORE_Y_dmapack.sv\n             obj_dir/NV_NVDLA_SDP_CORE_Y_dmapack\n             obj_dir/NV_NVDLA_SDP_CORE_Y_dmapack.v\n             obj_dir/NV_NVDLA_SDP_CORE_Y_dmapack.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:347: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_cvt'\nNV_NVDLA_SDP_CORE_Y_cvt u_alu_cvt (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:366: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_dmapack'\nNV_NVDLA_SDP_CORE_Y_dmapack u_mul_dmapack (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:378: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_cvt'\nNV_NVDLA_SDP_CORE_Y_cvt u_mul_cvt (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:397: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_dppack'\nNV_NVDLA_SDP_CORE_Y_dppack u_dppack (\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:409: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_core'\nNV_NVDLA_SDP_CORE_Y_core u_core (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:449: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_idx'\nNV_NVDLA_SDP_CORE_Y_idx u_idx (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:473: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_lut'\nNV_NVDLA_SDP_CORE_Y_lut u_lut (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:515: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_inp'\nNV_NVDLA_SDP_CORE_Y_inp u_inp (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v:533: Cannot find file containing module: 'NV_NVDLA_SDP_CORE_Y_dpunpack'\nNV_NVDLA_SDP_CORE_Y_dpunpack u_dpunpack (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module NV_NVDLA_SDP_CORE_y (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,ew_alu_in_data
  ,ew_alu_in_vld
  ,ew_data_in_pd
  ,ew_data_in_pvld
  ,ew_data_out_prdy
  ,ew_mul_in_data
  ,ew_mul_in_vld
  ,op_en_load
  ,pwrbus_ram_pd
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_alu_cvt_bypass
  ,reg2dp_ew_alu_cvt_offset
  ,reg2dp_ew_alu_cvt_scale
  ,reg2dp_ew_alu_cvt_truncate
  ,reg2dp_ew_alu_operand
  ,reg2dp_ew_alu_src
  ,reg2dp_ew_lut_bypass
  ,reg2dp_ew_mul_bypass
  ,reg2dp_ew_mul_cvt_bypass
  ,reg2dp_ew_mul_cvt_offset
  ,reg2dp_ew_mul_cvt_scale
  ,reg2dp_ew_mul_cvt_truncate
  ,reg2dp_ew_mul_operand
  ,reg2dp_ew_mul_prelu
  ,reg2dp_ew_mul_src
  ,reg2dp_ew_truncate
  ,reg2dp_lut_hybrid_priority
  ,reg2dp_lut_int_access_type
  ,reg2dp_lut_int_addr
  ,reg2dp_lut_int_data
  ,reg2dp_lut_int_data_wr
  ,reg2dp_lut_int_table_id
  ,reg2dp_lut_le_end
  ,reg2dp_lut_le_function
  ,reg2dp_lut_le_index_offset
  ,reg2dp_lut_le_index_select
  ,reg2dp_lut_le_slope_oflow_scale
  ,reg2dp_lut_le_slope_oflow_shift
  ,reg2dp_lut_le_slope_uflow_scale
  ,reg2dp_lut_le_slope_uflow_shift
  ,reg2dp_lut_le_start
  ,reg2dp_lut_lo_end
  ,reg2dp_lut_lo_index_select
  ,reg2dp_lut_lo_slope_oflow_scale
  ,reg2dp_lut_lo_slope_oflow_shift
  ,reg2dp_lut_lo_slope_uflow_scale
  ,reg2dp_lut_lo_slope_uflow_shift
  ,reg2dp_lut_lo_start
  ,reg2dp_lut_oflow_priority
  ,reg2dp_lut_uflow_priority
  ,reg2dp_nan_to_zero
  ,reg2dp_perf_lut_en
  ,reg2dp_proc_precision
  ,dp2reg_lut_hybrid
  ,dp2reg_lut_int_data
  ,dp2reg_lut_le_hit
  ,dp2reg_lut_lo_hit
  ,dp2reg_lut_oflow
  ,dp2reg_lut_uflow
  ,ew_alu_in_rdy
  ,ew_data_in_prdy
  ,ew_data_out_pd
  ,ew_data_out_pvld
  ,ew_mul_in_rdy
  );

input          nvdla_core_clk;
input          nvdla_core_rstn;
input  [255:0] ew_alu_in_data;
input          ew_alu_in_vld;
input  [511:0] ew_data_in_pd;
input          ew_data_in_pvld;
input          ew_data_out_prdy;
input  [255:0] ew_mul_in_data;
input          ew_mul_in_vld;
output         ew_alu_in_rdy;
output         ew_data_in_prdy;
output [511:0] ew_data_out_pd;
output         ew_data_out_pvld;
output         ew_mul_in_rdy;
input    [1:0] reg2dp_ew_alu_algo;
input          reg2dp_ew_alu_bypass;
input          reg2dp_ew_alu_cvt_bypass;
input   [31:0] reg2dp_ew_alu_cvt_offset;
input   [15:0] reg2dp_ew_alu_cvt_scale;
input    [5:0] reg2dp_ew_alu_cvt_truncate;
input   [31:0] reg2dp_ew_alu_operand;
input          reg2dp_ew_alu_src;
input          reg2dp_ew_lut_bypass;
input          reg2dp_ew_mul_bypass;
input          reg2dp_ew_mul_cvt_bypass;
input   [31:0] reg2dp_ew_mul_cvt_offset;
input   [15:0] reg2dp_ew_mul_cvt_scale;
input    [5:0] reg2dp_ew_mul_cvt_truncate;
input   [31:0] reg2dp_ew_mul_operand;
input          reg2dp_ew_mul_prelu;
input          reg2dp_ew_mul_src;
input    [9:0] reg2dp_ew_truncate;
input          reg2dp_lut_hybrid_priority;
input          reg2dp_lut_int_access_type;
input    [9:0] reg2dp_lut_int_addr;
input   [15:0] reg2dp_lut_int_data;
input          reg2dp_lut_int_data_wr;
input          reg2dp_lut_int_table_id;
input   [31:0] reg2dp_lut_le_end;
input          reg2dp_lut_le_function;
input    [7:0] reg2dp_lut_le_index_offset;
input    [7:0] reg2dp_lut_le_index_select;
input   [15:0] reg2dp_lut_le_slope_oflow_scale;
input    [4:0] reg2dp_lut_le_slope_oflow_shift;
input   [15:0] reg2dp_lut_le_slope_uflow_scale;
input    [4:0] reg2dp_lut_le_slope_uflow_shift;
input   [31:0] reg2dp_lut_le_start;
input   [31:0] reg2dp_lut_lo_end;
input    [7:0] reg2dp_lut_lo_index_select;
input   [15:0] reg2dp_lut_lo_slope_oflow_scale;
input    [4:0] reg2dp_lut_lo_slope_oflow_shift;
input   [15:0] reg2dp_lut_lo_slope_uflow_scale;
input    [4:0] reg2dp_lut_lo_slope_uflow_shift;
input   [31:0] reg2dp_lut_lo_start;
input          reg2dp_lut_oflow_priority;
input          reg2dp_lut_uflow_priority;
input          reg2dp_nan_to_zero;
input          reg2dp_perf_lut_en;
input    [1:0] reg2dp_proc_precision;
output  [31:0] dp2reg_lut_hybrid;
output  [15:0] dp2reg_lut_int_data;
output  [31:0] dp2reg_lut_le_hit;
output  [31:0] dp2reg_lut_lo_hit;
output  [31:0] dp2reg_lut_oflow;
output  [31:0] dp2reg_lut_uflow;

input   [31:0] pwrbus_ram_pd;
input          op_en_load;
reg      [1:0] cfg_ew_alu_algo;
reg            cfg_ew_alu_bypass;
reg            cfg_ew_alu_cvt_bypass;
reg     [31:0] cfg_ew_alu_cvt_offset;
reg     [15:0] cfg_ew_alu_cvt_scale;
reg      [5:0] cfg_ew_alu_cvt_truncate;
reg     [31:0] cfg_ew_alu_operand;
reg            cfg_ew_alu_src;
reg            cfg_ew_lut_bypass;
reg            cfg_ew_mul_bypass;
reg            cfg_ew_mul_cvt_bypass;
reg     [31:0] cfg_ew_mul_cvt_offset;
reg     [15:0] cfg_ew_mul_cvt_scale;
reg      [5:0] cfg_ew_mul_cvt_truncate;
reg     [31:0] cfg_ew_mul_operand;
reg            cfg_ew_mul_prelu;
reg            cfg_ew_mul_src;
reg      [9:0] cfg_ew_truncate;
reg            cfg_lut_hybrid_priority;
reg     [31:0] cfg_lut_le_end;
reg            cfg_lut_le_function;
reg      [7:0] cfg_lut_le_index_offset;
reg      [7:0] cfg_lut_le_index_select;
reg     [15:0] cfg_lut_le_slope_oflow_scale;
reg      [4:0] cfg_lut_le_slope_oflow_shift;
reg     [15:0] cfg_lut_le_slope_uflow_scale;
reg      [4:0] cfg_lut_le_slope_uflow_shift;
reg     [31:0] cfg_lut_le_start;
reg     [31:0] cfg_lut_lo_end;
reg      [7:0] cfg_lut_lo_index_select;
reg     [15:0] cfg_lut_lo_slope_oflow_scale;
reg      [4:0] cfg_lut_lo_slope_oflow_shift;
reg     [15:0] cfg_lut_lo_slope_uflow_scale;
reg      [4:0] cfg_lut_lo_slope_uflow_shift;
reg     [31:0] cfg_lut_lo_start;
reg            cfg_lut_oflow_priority;
reg            cfg_lut_uflow_priority;
reg            cfg_nan_to_zero;
reg      [1:0] cfg_proc_precision;
wire   [127:0] alu_cvt_out_pd;
wire           alu_cvt_out_prdy;
wire           alu_cvt_out_pvld;
wire   [127:0] core_out_pd;
wire           core_out_prdy;
wire           core_out_pvld;
wire    [63:0] flop_ew_alu_in_data;
wire           flop_ew_alu_in_rdy;
wire           flop_ew_alu_in_vld;
wire   [127:0] flop_ew_data_in_pd;
wire           flop_ew_data_in_prdy;
wire           flop_ew_data_in_pvld;
wire    [63:0] flop_ew_mul_in_data;
wire           flop_ew_mul_in_rdy;
wire           flop_ew_mul_in_vld;
wire   [323:0] idx2lut_pd;
wire           idx2lut_prdy;
wire           idx2lut_pvld;
wire   [127:0] idx_in_pd;
wire           idx_in_prdy;
wire           idx_in_pvld;
wire   [127:0] inp_out_pd;
wire           inp_out_prdy;
wire           inp_out_pvld;
wire   [739:0] lut2inp_pd;
wire           lut2inp_prdy;
wire           lut2inp_pvld;
wire   [127:0] mul_cvt_out_pd;
wire           mul_cvt_out_prdy;
wire           mul_cvt_out_pvld;
wire   [127:0] unpack_in_pd;
wire           unpack_in_prdy;
wire           unpack_in_pvld;
















    

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_ew_alu_operand <= {32{1'b0}};
    cfg_ew_alu_bypass <= 1'b0;
    cfg_ew_alu_algo <= {2{1'b0}};
    cfg_ew_alu_src <= 1'b0;
    cfg_ew_alu_cvt_bypass <= 1'b0;
    cfg_ew_alu_cvt_offset <= {32{1'b0}};
    cfg_ew_alu_cvt_scale <= {16{1'b0}};
    cfg_ew_alu_cvt_truncate <= {6{1'b0}};
    cfg_ew_mul_operand <= {32{1'b0}};
    cfg_ew_mul_bypass <= 1'b0;
    cfg_ew_mul_src <= 1'b0;
    cfg_ew_mul_cvt_bypass <= 1'b0;
    cfg_ew_mul_cvt_offset <= {32{1'b0}};
    cfg_ew_mul_cvt_scale <= {16{1'b0}};
    cfg_ew_mul_cvt_truncate <= {6{1'b0}};
    cfg_ew_truncate <= {10{1'b0}};
    cfg_ew_mul_prelu <= 1'b0;
    cfg_ew_lut_bypass <= 1'b0;
    cfg_lut_le_start <= {32{1'b0}};
    cfg_lut_le_end <= {32{1'b0}};
    cfg_lut_lo_start <= {32{1'b0}};
    cfg_lut_lo_end <= {32{1'b0}};
    cfg_lut_le_index_offset <= {8{1'b0}};
    cfg_lut_le_index_select <= {8{1'b0}};
    cfg_lut_lo_index_select <= {8{1'b0}};
    cfg_lut_le_function <= 1'b0;
    cfg_lut_uflow_priority <= 1'b0;
    cfg_lut_oflow_priority <= 1'b0;
    cfg_lut_hybrid_priority <= 1'b0;
    cfg_lut_le_slope_oflow_scale <= {16{1'b0}};
    cfg_lut_le_slope_oflow_shift <= {5{1'b0}};
    cfg_lut_le_slope_uflow_scale <= {16{1'b0}};
    cfg_lut_le_slope_uflow_shift <= {5{1'b0}};
    cfg_lut_lo_slope_oflow_scale <= {16{1'b0}};
    cfg_lut_lo_slope_oflow_shift <= {5{1'b0}};
    cfg_lut_lo_slope_uflow_scale <= {16{1'b0}};
    cfg_lut_lo_slope_uflow_shift <= {5{1'b0}};
    cfg_proc_precision <= {2{1'b0}};
    cfg_nan_to_zero <= 1'b0;
  end else begin
    if (op_en_load) begin
        cfg_ew_alu_operand      <= reg2dp_ew_alu_operand     ;
        cfg_ew_alu_bypass       <= reg2dp_ew_alu_bypass      ;
        cfg_ew_alu_algo         <= reg2dp_ew_alu_algo        ;
        cfg_ew_alu_src          <= reg2dp_ew_alu_src         ;
        cfg_ew_alu_cvt_bypass   <= reg2dp_ew_alu_cvt_bypass  ;
        cfg_ew_alu_cvt_offset   <= reg2dp_ew_alu_cvt_offset  ;
        cfg_ew_alu_cvt_scale    <= reg2dp_ew_alu_cvt_scale   ;
        cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate;
        cfg_ew_mul_operand      <= reg2dp_ew_mul_operand     ;
        cfg_ew_mul_bypass       <= reg2dp_ew_mul_bypass      ;
        cfg_ew_mul_src          <= reg2dp_ew_mul_src         ;
        cfg_ew_mul_cvt_bypass   <= reg2dp_ew_mul_cvt_bypass  ;
        cfg_ew_mul_cvt_offset   <= reg2dp_ew_mul_cvt_offset  ;
        cfg_ew_mul_cvt_scale    <= reg2dp_ew_mul_cvt_scale   ;
        cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate;
        cfg_ew_truncate         <= reg2dp_ew_truncate        ;
        cfg_ew_mul_prelu        <= reg2dp_ew_mul_prelu       ;
        cfg_ew_lut_bypass       <= reg2dp_ew_lut_bypass      ;

        cfg_lut_le_start        <= reg2dp_lut_le_start       ;      
        cfg_lut_le_end          <= reg2dp_lut_le_end         ;
        cfg_lut_lo_start        <= reg2dp_lut_lo_start       ;
        cfg_lut_lo_end          <= reg2dp_lut_lo_end         ;
        cfg_lut_le_index_offset <= reg2dp_lut_le_index_offset;
        cfg_lut_le_index_select <= reg2dp_lut_le_index_select;
        cfg_lut_lo_index_select <= reg2dp_lut_lo_index_select;
        cfg_lut_le_function     <= reg2dp_lut_le_function    ;
        cfg_lut_uflow_priority  <= reg2dp_lut_uflow_priority ;
        cfg_lut_oflow_priority  <= reg2dp_lut_oflow_priority ;
        cfg_lut_hybrid_priority <= reg2dp_lut_hybrid_priority;

        cfg_lut_le_slope_oflow_scale <= reg2dp_lut_le_slope_oflow_scale;
        cfg_lut_le_slope_oflow_shift <= reg2dp_lut_le_slope_oflow_shift;
        cfg_lut_le_slope_uflow_scale <= reg2dp_lut_le_slope_uflow_scale;
        cfg_lut_le_slope_uflow_shift <= reg2dp_lut_le_slope_uflow_shift;

        cfg_lut_lo_slope_oflow_scale <= reg2dp_lut_lo_slope_oflow_scale;
        cfg_lut_lo_slope_oflow_shift <= reg2dp_lut_lo_slope_oflow_shift;
        cfg_lut_lo_slope_uflow_scale <= reg2dp_lut_lo_slope_uflow_scale;
        cfg_lut_lo_slope_uflow_shift <= reg2dp_lut_lo_slope_uflow_shift;

        cfg_proc_precision      <= reg2dp_proc_precision     ;
        cfg_nan_to_zero         <= reg2dp_nan_to_zero     ;
    end
  end
end
 






NV_NVDLA_SDP_CORE_Y_dmapack u_alu_dmapack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_alu_in_vld)
  ,.inp_data                        (ew_alu_in_data[255:0])
  ,.inp_prdy                        (ew_alu_in_rdy)
  ,.out_pvld                        (flop_ew_alu_in_vld)
  ,.out_data                        (flop_ew_alu_in_data[63:0])
  ,.out_prdy                        (flop_ew_alu_in_rdy)
  );


NV_NVDLA_SDP_CORE_Y_cvt u_alu_cvt (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_in_rsc_z                    (flop_ew_alu_in_data[63:0])
  ,.chn_in_rsc_vz                   (flop_ew_alu_in_vld)
  ,.chn_in_rsc_lz                   (flop_ew_alu_in_rdy)
  ,.cfg_bypass_rsc_z                (cfg_ew_alu_cvt_bypass)
  ,.cfg_offset_rsc_z                (cfg_ew_alu_cvt_offset[31:0])
  ,.cfg_scale_rsc_z                 (cfg_ew_alu_cvt_scale[15:0])
  ,.cfg_truncate_rsc_z              (cfg_ew_alu_cvt_truncate[5:0])
  ,.cfg_nan_to_zero_rsc_z           (cfg_nan_to_zero)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_out_rsc_z                   (alu_cvt_out_pd[127:0])
  ,.chn_out_rsc_vz                  (alu_cvt_out_prdy)
  ,.chn_out_rsc_lz                  (alu_cvt_out_pvld)
  );



NV_NVDLA_SDP_CORE_Y_dmapack u_mul_dmapack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_mul_in_vld)
  ,.inp_data                        (ew_mul_in_data[255:0])
  ,.inp_prdy                        (ew_mul_in_rdy)
  ,.out_pvld                        (flop_ew_mul_in_vld)
  ,.out_data                        (flop_ew_mul_in_data[63:0])
  ,.out_prdy                        (flop_ew_mul_in_rdy)
  );


NV_NVDLA_SDP_CORE_Y_cvt u_mul_cvt (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_in_rsc_z                    (flop_ew_mul_in_data[63:0])
  ,.chn_in_rsc_vz                   (flop_ew_mul_in_vld)
  ,.chn_in_rsc_lz                   (flop_ew_mul_in_rdy)
  ,.cfg_bypass_rsc_z                (cfg_ew_mul_cvt_bypass)
  ,.cfg_offset_rsc_z                (cfg_ew_mul_cvt_offset[31:0])
  ,.cfg_scale_rsc_z                 (cfg_ew_mul_cvt_scale[15:0])
  ,.cfg_truncate_rsc_z              (cfg_ew_mul_cvt_truncate[5:0])
  ,.cfg_nan_to_zero_rsc_z           (cfg_nan_to_zero)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_out_rsc_z                   (mul_cvt_out_pd[127:0])
  ,.chn_out_rsc_vz                  (mul_cvt_out_prdy)
  ,.chn_out_rsc_lz                  (mul_cvt_out_pvld)
  );



NV_NVDLA_SDP_CORE_Y_dppack u_dppack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_data_in_pvld)
  ,.inp_data                        (ew_data_in_pd[511:0])
  ,.inp_prdy                        (ew_data_in_prdy)
  ,.out_pvld                        (flop_ew_data_in_pvld)
  ,.out_data                        (flop_ew_data_in_pd[127:0])
  ,.out_prdy                        (flop_ew_data_in_prdy)
  );


NV_NVDLA_SDP_CORE_Y_core u_core (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_data_in_rsc_z               (flop_ew_data_in_pd[127:0])
  ,.chn_data_in_rsc_vz              (flop_ew_data_in_pvld)
  ,.chn_data_in_rsc_lz              (flop_ew_data_in_prdy)
  ,.chn_alu_op_rsc_z                (alu_cvt_out_pd[127:0])
  ,.chn_alu_op_rsc_vz               (alu_cvt_out_pvld)
  ,.chn_alu_op_rsc_lz               (alu_cvt_out_prdy)
  ,.chn_mul_op_rsc_z                (mul_cvt_out_pd[127:0])
  ,.chn_mul_op_rsc_vz               (mul_cvt_out_pvld)
  ,.chn_mul_op_rsc_lz               (mul_cvt_out_prdy)
  ,.cfg_alu_bypass_rsc_z            (cfg_ew_alu_bypass)
  ,.cfg_alu_bypass_rsc_triosy_lz    ()
  ,.cfg_alu_src_rsc_z               (cfg_ew_alu_src)
  ,.cfg_alu_src_rsc_triosy_lz       ()
  ,.cfg_alu_op_rsc_z                (cfg_ew_alu_operand[31:0])
  ,.cfg_alu_op_rsc_triosy_lz        ()
  ,.cfg_alu_algo_rsc_z              (cfg_ew_alu_algo[1:0])
  ,.cfg_alu_algo_rsc_triosy_lz      ()
  ,.cfg_mul_bypass_rsc_z            (cfg_ew_mul_bypass)
  ,.cfg_mul_bypass_rsc_triosy_lz    ()
  ,.cfg_mul_src_rsc_z               (cfg_ew_mul_src)
  ,.cfg_mul_src_rsc_triosy_lz       ()
  ,.cfg_mul_op_rsc_z                (cfg_ew_mul_operand[31:0])
  ,.cfg_mul_op_rsc_triosy_lz        ()
  ,.cfg_truncate_rsc_z              (cfg_ew_truncate[9:0])
  ,.cfg_truncate_rsc_triosy_lz      ()
  ,.cfg_mul_prelu_rsc_z             (cfg_ew_mul_prelu)
  ,.cfg_mul_prelu_rsc_triosy_lz     ()
  ,.cfg_precision                   (cfg_proc_precision[1:0])
  ,.chn_data_out_rsc_z              (core_out_pd[127:0])
  ,.chn_data_out_rsc_vz             (core_out_prdy)
  ,.chn_data_out_rsc_lz             (core_out_pvld)
  );

assign idx_in_pvld = cfg_ew_lut_bypass ? 1'b0 : core_out_pvld;
assign idx_in_pd   =  {128{idx_in_pvld}} & core_out_pd;
assign core_out_prdy = cfg_ew_lut_bypass ? unpack_in_prdy : idx_in_prdy;

NV_NVDLA_SDP_CORE_Y_idx u_idx (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_lut_in_rsc_z                (idx_in_pd[127:0])
  ,.chn_lut_in_rsc_vz               (idx_in_pvld)
  ,.chn_lut_in_rsc_lz               (idx_in_prdy)
  ,.cfg_lut_le_start_rsc_z          (cfg_lut_le_start[31:0])
  ,.cfg_lut_lo_start_rsc_z          (cfg_lut_lo_start[31:0])
  ,.cfg_lut_le_index_offset_rsc_z   (cfg_lut_le_index_offset[7:0])
  ,.cfg_lut_le_index_select_rsc_z   (cfg_lut_le_index_select[7:0])
  ,.cfg_lut_lo_index_select_rsc_z   (cfg_lut_lo_index_select[7:0])
  ,.cfg_lut_le_function_rsc_z       (cfg_lut_le_function)
  ,.cfg_lut_uflow_priority_rsc_z    (cfg_lut_uflow_priority)
  ,.cfg_lut_oflow_priority_rsc_z    (cfg_lut_oflow_priority)
  ,.cfg_lut_hybrid_priority_rsc_z   (cfg_lut_hybrid_priority)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_lut_out_rsc_z               (idx2lut_pd[323:0])
  ,.chn_lut_out_rsc_vz              (idx2lut_prdy)
  ,.chn_lut_out_rsc_lz              (idx2lut_pvld)
  );




NV_NVDLA_SDP_CORE_Y_lut u_lut (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.lut2inp_pvld                    (lut2inp_pvld)
  ,.lut2inp_prdy                    (lut2inp_prdy)
  ,.lut2inp_pd                      (lut2inp_pd[739:0])
  ,.idx2lut_pvld                    (idx2lut_pvld)
  ,.idx2lut_prdy                    (idx2lut_prdy)
  ,.idx2lut_pd                      (idx2lut_pd[323:0])
  ,.reg2dp_lut_int_access_type      (reg2dp_lut_int_access_type)
  ,.reg2dp_lut_int_addr             (reg2dp_lut_int_addr[9:0])
  ,.reg2dp_lut_int_data             (reg2dp_lut_int_data[15:0])
  ,.reg2dp_lut_int_data_wr          (reg2dp_lut_int_data_wr)
  ,.reg2dp_lut_int_table_id         (reg2dp_lut_int_table_id)
  ,.reg2dp_lut_le_end               (cfg_lut_le_end[31:0])
  ,.reg2dp_lut_le_function          (reg2dp_lut_le_function)
  ,.reg2dp_lut_le_index_offset      (reg2dp_lut_le_index_offset[7:0])
  ,.reg2dp_lut_le_slope_oflow_scale (cfg_lut_le_slope_oflow_scale[15:0])
  ,.reg2dp_lut_le_slope_oflow_shift (cfg_lut_le_slope_oflow_shift[4:0])
  ,.reg2dp_lut_le_slope_uflow_scale (cfg_lut_le_slope_uflow_scale[15:0])
  ,.reg2dp_lut_le_slope_uflow_shift (cfg_lut_le_slope_uflow_shift[4:0])
  ,.reg2dp_lut_le_start             (cfg_lut_le_start[31:0])
  ,.reg2dp_lut_lo_end               (cfg_lut_lo_end[31:0])
  ,.reg2dp_lut_lo_slope_oflow_scale (cfg_lut_lo_slope_oflow_scale[15:0])
  ,.reg2dp_lut_lo_slope_oflow_shift (cfg_lut_lo_slope_oflow_shift[4:0])
  ,.reg2dp_lut_lo_slope_uflow_scale (cfg_lut_lo_slope_uflow_scale[15:0])
  ,.reg2dp_lut_lo_slope_uflow_shift (cfg_lut_lo_slope_uflow_shift[4:0])
  ,.reg2dp_lut_lo_start             (cfg_lut_lo_start[31:0])
  ,.reg2dp_perf_lut_en              (reg2dp_perf_lut_en)
  ,.reg2dp_proc_precision           (reg2dp_proc_precision[1:0])
  ,.dp2reg_lut_hybrid               (dp2reg_lut_hybrid[31:0])
  ,.dp2reg_lut_int_data             (dp2reg_lut_int_data[15:0])
  ,.dp2reg_lut_le_hit               (dp2reg_lut_le_hit[31:0])
  ,.dp2reg_lut_lo_hit               (dp2reg_lut_lo_hit[31:0])
  ,.dp2reg_lut_oflow                (dp2reg_lut_oflow[31:0])
  ,.dp2reg_lut_uflow                (dp2reg_lut_uflow[31:0])
  ,.pwrbus_ram_pd                   (pwrbus_ram_pd[31:0])
  ,.op_en_load                      (op_en_load)
  );



NV_NVDLA_SDP_CORE_Y_inp u_inp (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_inp_in_rsc_z                (lut2inp_pd[739:0])
  ,.chn_inp_in_rsc_vz               (lut2inp_pvld)
  ,.chn_inp_in_rsc_lz               (lut2inp_prdy)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_inp_out_rsc_z               (inp_out_pd[127:0])
  ,.chn_inp_out_rsc_vz              (inp_out_prdy)
  ,.chn_inp_out_rsc_lz              (inp_out_pvld)
  );

assign unpack_in_pvld = cfg_ew_lut_bypass ? core_out_pvld : inp_out_pvld;
assign unpack_in_pd   = cfg_ew_lut_bypass ? core_out_pd   : inp_out_pd;
assign inp_out_prdy   = cfg_ew_lut_bypass ? 1'b0 : unpack_in_prdy;



NV_NVDLA_SDP_CORE_Y_dpunpack u_dpunpack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (unpack_in_pvld)
  ,.inp_data                        (unpack_in_pd[127:0])
  ,.inp_prdy                        (unpack_in_prdy)
  ,.out_pvld                        (ew_data_out_pvld)
  ,.out_data                        (ew_data_out_pd[511:0])
  ,.out_prdy                        (ew_data_out_prdy)
  );

endmodule
module NV_NVDLA_SDP_CORE_y (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,ew_alu_in_data
  ,ew_alu_in_vld
  ,ew_data_in_pd
  ,ew_data_in_pvld
  ,ew_data_out_prdy
  ,ew_mul_in_data
  ,ew_mul_in_vld
  ,op_en_load
  ,pwrbus_ram_pd
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_alu_cvt_bypass
  ,reg2dp_ew_alu_cvt_offset
  ,reg2dp_ew_alu_cvt_scale
  ,reg2dp_ew_alu_cvt_truncate
  ,reg2dp_ew_alu_operand
  ,reg2dp_ew_alu_src
  ,reg2dp_ew_lut_bypass
  ,reg2dp_ew_mul_bypass
  ,reg2dp_ew_mul_cvt_bypass
  ,reg2dp_ew_mul_cvt_offset
  ,reg2dp_ew_mul_cvt_scale
  ,reg2dp_ew_mul_cvt_truncate
  ,reg2dp_ew_mul_operand
  ,reg2dp_ew_mul_prelu
  ,reg2dp_ew_mul_src
  ,reg2dp_ew_truncate
  ,reg2dp_lut_hybrid_priority
  ,reg2dp_lut_int_access_type
  ,reg2dp_lut_int_addr
  ,reg2dp_lut_int_data
  ,reg2dp_lut_int_data_wr
  ,reg2dp_lut_int_table_id
  ,reg2dp_lut_le_end
  ,reg2dp_lut_le_function
  ,reg2dp_lut_le_index_offset
  ,reg2dp_lut_le_index_select
  ,reg2dp_lut_le_slope_oflow_scale
  ,reg2dp_lut_le_slope_oflow_shift
  ,reg2dp_lut_le_slope_uflow_scale
  ,reg2dp_lut_le_slope_uflow_shift
  ,reg2dp_lut_le_start
  ,reg2dp_lut_lo_end
  ,reg2dp_lut_lo_index_select
  ,reg2dp_lut_lo_slope_oflow_scale
  ,reg2dp_lut_lo_slope_oflow_shift
  ,reg2dp_lut_lo_slope_uflow_scale
  ,reg2dp_lut_lo_slope_uflow_shift
  ,reg2dp_lut_lo_start
  ,reg2dp_lut_oflow_priority
  ,reg2dp_lut_uflow_priority
  ,reg2dp_nan_to_zero
  ,reg2dp_perf_lut_en
  ,reg2dp_proc_precision
  ,dp2reg_lut_hybrid
  ,dp2reg_lut_int_data
  ,dp2reg_lut_le_hit
  ,dp2reg_lut_lo_hit
  ,dp2reg_lut_oflow
  ,dp2reg_lut_uflow
  ,ew_alu_in_rdy
  ,ew_data_in_prdy
  ,ew_data_out_pd
  ,ew_data_out_pvld
  ,ew_mul_in_rdy
  );


input          nvdla_core_clk;
input          nvdla_core_rstn;
input  [255:0] ew_alu_in_data;
input          ew_alu_in_vld;
input  [511:0] ew_data_in_pd;
input          ew_data_in_pvld;
input          ew_data_out_prdy;
input  [255:0] ew_mul_in_data;
input          ew_mul_in_vld;
output         ew_alu_in_rdy;
output         ew_data_in_prdy;
output [511:0] ew_data_out_pd;
output         ew_data_out_pvld;
output         ew_mul_in_rdy;
input    [1:0] reg2dp_ew_alu_algo;
input          reg2dp_ew_alu_bypass;
input          reg2dp_ew_alu_cvt_bypass;
input   [31:0] reg2dp_ew_alu_cvt_offset;
input   [15:0] reg2dp_ew_alu_cvt_scale;
input    [5:0] reg2dp_ew_alu_cvt_truncate;
input   [31:0] reg2dp_ew_alu_operand;
input          reg2dp_ew_alu_src;
input          reg2dp_ew_lut_bypass;
input          reg2dp_ew_mul_bypass;
input          reg2dp_ew_mul_cvt_bypass;
input   [31:0] reg2dp_ew_mul_cvt_offset;
input   [15:0] reg2dp_ew_mul_cvt_scale;
input    [5:0] reg2dp_ew_mul_cvt_truncate;
input   [31:0] reg2dp_ew_mul_operand;
input          reg2dp_ew_mul_prelu;
input          reg2dp_ew_mul_src;
input    [9:0] reg2dp_ew_truncate;
input          reg2dp_lut_hybrid_priority;
input          reg2dp_lut_int_access_type;
input    [9:0] reg2dp_lut_int_addr;
input   [15:0] reg2dp_lut_int_data;
input          reg2dp_lut_int_data_wr;
input          reg2dp_lut_int_table_id;
input   [31:0] reg2dp_lut_le_end;
input          reg2dp_lut_le_function;
input    [7:0] reg2dp_lut_le_index_offset;
input    [7:0] reg2dp_lut_le_index_select;
input   [15:0] reg2dp_lut_le_slope_oflow_scale;
input    [4:0] reg2dp_lut_le_slope_oflow_shift;
input   [15:0] reg2dp_lut_le_slope_uflow_scale;
input    [4:0] reg2dp_lut_le_slope_uflow_shift;
input   [31:0] reg2dp_lut_le_start;
input   [31:0] reg2dp_lut_lo_end;
input    [7:0] reg2dp_lut_lo_index_select;
input   [15:0] reg2dp_lut_lo_slope_oflow_scale;
input    [4:0] reg2dp_lut_lo_slope_oflow_shift;
input   [15:0] reg2dp_lut_lo_slope_uflow_scale;
input    [4:0] reg2dp_lut_lo_slope_uflow_shift;
input   [31:0] reg2dp_lut_lo_start;
input          reg2dp_lut_oflow_priority;
input          reg2dp_lut_uflow_priority;
input          reg2dp_nan_to_zero;
input          reg2dp_perf_lut_en;
input    [1:0] reg2dp_proc_precision;
output  [31:0] dp2reg_lut_hybrid;
output  [15:0] dp2reg_lut_int_data;
output  [31:0] dp2reg_lut_le_hit;
output  [31:0] dp2reg_lut_lo_hit;
output  [31:0] dp2reg_lut_oflow;
output  [31:0] dp2reg_lut_uflow;

input   [31:0] pwrbus_ram_pd;
input          op_en_load;
reg      [1:0] cfg_ew_alu_algo;
reg            cfg_ew_alu_bypass;
reg            cfg_ew_alu_cvt_bypass;
reg     [31:0] cfg_ew_alu_cvt_offset;
reg     [15:0] cfg_ew_alu_cvt_scale;
reg      [5:0] cfg_ew_alu_cvt_truncate;
reg     [31:0] cfg_ew_alu_operand;
reg            cfg_ew_alu_src;
reg            cfg_ew_lut_bypass;
reg            cfg_ew_mul_bypass;
reg            cfg_ew_mul_cvt_bypass;
reg     [31:0] cfg_ew_mul_cvt_offset;
reg     [15:0] cfg_ew_mul_cvt_scale;
reg      [5:0] cfg_ew_mul_cvt_truncate;
reg     [31:0] cfg_ew_mul_operand;
reg            cfg_ew_mul_prelu;
reg            cfg_ew_mul_src;
reg      [9:0] cfg_ew_truncate;
reg            cfg_lut_hybrid_priority;
reg     [31:0] cfg_lut_le_end;
reg            cfg_lut_le_function;
reg      [7:0] cfg_lut_le_index_offset;
reg      [7:0] cfg_lut_le_index_select;
reg     [15:0] cfg_lut_le_slope_oflow_scale;
reg      [4:0] cfg_lut_le_slope_oflow_shift;
reg     [15:0] cfg_lut_le_slope_uflow_scale;
reg      [4:0] cfg_lut_le_slope_uflow_shift;
reg     [31:0] cfg_lut_le_start;
reg     [31:0] cfg_lut_lo_end;
reg      [7:0] cfg_lut_lo_index_select;
reg     [15:0] cfg_lut_lo_slope_oflow_scale;
reg      [4:0] cfg_lut_lo_slope_oflow_shift;
reg     [15:0] cfg_lut_lo_slope_uflow_scale;
reg      [4:0] cfg_lut_lo_slope_uflow_shift;
reg     [31:0] cfg_lut_lo_start;
reg            cfg_lut_oflow_priority;
reg            cfg_lut_uflow_priority;
reg            cfg_nan_to_zero;
reg      [1:0] cfg_proc_precision;
wire   [127:0] alu_cvt_out_pd;
wire           alu_cvt_out_prdy;
wire           alu_cvt_out_pvld;
wire   [127:0] core_out_pd;
wire           core_out_prdy;
wire           core_out_pvld;
wire    [63:0] flop_ew_alu_in_data;
wire           flop_ew_alu_in_rdy;
wire           flop_ew_alu_in_vld;
wire   [127:0] flop_ew_data_in_pd;
wire           flop_ew_data_in_prdy;
wire           flop_ew_data_in_pvld;
wire    [63:0] flop_ew_mul_in_data;
wire           flop_ew_mul_in_rdy;
wire           flop_ew_mul_in_vld;
wire   [323:0] idx2lut_pd;
wire           idx2lut_prdy;
wire           idx2lut_pvld;
wire   [127:0] idx_in_pd;
wire           idx_in_prdy;
wire           idx_in_pvld;
wire   [127:0] inp_out_pd;
wire           inp_out_prdy;
wire           inp_out_pvld;
wire   [739:0] lut2inp_pd;
wire           lut2inp_prdy;
wire           lut2inp_pvld;
wire   [127:0] mul_cvt_out_pd;
wire           mul_cvt_out_prdy;
wire           mul_cvt_out_pvld;
wire   [127:0] unpack_in_pd;
wire           unpack_in_prdy;
wire           unpack_in_pvld;
















    

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_ew_alu_operand <= {32{1'b0}};
    cfg_ew_alu_bypass <= 1'b0;
    cfg_ew_alu_algo <= {2{1'b0}};
    cfg_ew_alu_src <= 1'b0;
    cfg_ew_alu_cvt_bypass <= 1'b0;
    cfg_ew_alu_cvt_offset <= {32{1'b0}};
    cfg_ew_alu_cvt_scale <= {16{1'b0}};
    cfg_ew_alu_cvt_truncate <= {6{1'b0}};
    cfg_ew_mul_operand <= {32{1'b0}};
    cfg_ew_mul_bypass <= 1'b0;
    cfg_ew_mul_src <= 1'b0;
    cfg_ew_mul_cvt_bypass <= 1'b0;
    cfg_ew_mul_cvt_offset <= {32{1'b0}};
    cfg_ew_mul_cvt_scale <= {16{1'b0}};
    cfg_ew_mul_cvt_truncate <= {6{1'b0}};
    cfg_ew_truncate <= {10{1'b0}};
    cfg_ew_mul_prelu <= 1'b0;
    cfg_ew_lut_bypass <= 1'b0;
    cfg_lut_le_start <= {32{1'b0}};
    cfg_lut_le_end <= {32{1'b0}};
    cfg_lut_lo_start <= {32{1'b0}};
    cfg_lut_lo_end <= {32{1'b0}};
    cfg_lut_le_index_offset <= {8{1'b0}};
    cfg_lut_le_index_select <= {8{1'b0}};
    cfg_lut_lo_index_select <= {8{1'b0}};
    cfg_lut_le_function <= 1'b0;
    cfg_lut_uflow_priority <= 1'b0;
    cfg_lut_oflow_priority <= 1'b0;
    cfg_lut_hybrid_priority <= 1'b0;
    cfg_lut_le_slope_oflow_scale <= {16{1'b0}};
    cfg_lut_le_slope_oflow_shift <= {5{1'b0}};
    cfg_lut_le_slope_uflow_scale <= {16{1'b0}};
    cfg_lut_le_slope_uflow_shift <= {5{1'b0}};
    cfg_lut_lo_slope_oflow_scale <= {16{1'b0}};
    cfg_lut_lo_slope_oflow_shift <= {5{1'b0}};
    cfg_lut_lo_slope_uflow_scale <= {16{1'b0}};
    cfg_lut_lo_slope_uflow_shift <= {5{1'b0}};
    cfg_proc_precision <= {2{1'b0}};
    cfg_nan_to_zero <= 1'b0;
  end else begin
    if (op_en_load) begin
        cfg_ew_alu_operand      <= reg2dp_ew_alu_operand     ;
        cfg_ew_alu_bypass       <= reg2dp_ew_alu_bypass      ;
        cfg_ew_alu_algo         <= reg2dp_ew_alu_algo        ;
        cfg_ew_alu_src          <= reg2dp_ew_alu_src         ;
        cfg_ew_alu_cvt_bypass   <= reg2dp_ew_alu_cvt_bypass  ;
        cfg_ew_alu_cvt_offset   <= reg2dp_ew_alu_cvt_offset  ;
        cfg_ew_alu_cvt_scale    <= reg2dp_ew_alu_cvt_scale   ;
        cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate;
        cfg_ew_mul_operand      <= reg2dp_ew_mul_operand     ;
        cfg_ew_mul_bypass       <= reg2dp_ew_mul_bypass      ;
        cfg_ew_mul_src          <= reg2dp_ew_mul_src         ;
        cfg_ew_mul_cvt_bypass   <= reg2dp_ew_mul_cvt_bypass  ;
        cfg_ew_mul_cvt_offset   <= reg2dp_ew_mul_cvt_offset  ;
        cfg_ew_mul_cvt_scale    <= reg2dp_ew_mul_cvt_scale   ;
        cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate;
        cfg_ew_truncate         <= reg2dp_ew_truncate        ;
        cfg_ew_mul_prelu        <= reg2dp_ew_mul_prelu       ;
        cfg_ew_lut_bypass       <= reg2dp_ew_lut_bypass      ;

        cfg_lut_le_start        <= reg2dp_lut_le_start       ;      
        cfg_lut_le_end          <= reg2dp_lut_le_end         ;
        cfg_lut_lo_start        <= reg2dp_lut_lo_start       ;
        cfg_lut_lo_end          <= reg2dp_lut_lo_end         ;
        cfg_lut_le_index_offset <= reg2dp_lut_le_index_offset;
        cfg_lut_le_index_select <= reg2dp_lut_le_index_select;
        cfg_lut_lo_index_select <= reg2dp_lut_lo_index_select;
        cfg_lut_le_function     <= reg2dp_lut_le_function    ;
        cfg_lut_uflow_priority  <= reg2dp_lut_uflow_priority ;
        cfg_lut_oflow_priority  <= reg2dp_lut_oflow_priority ;
        cfg_lut_hybrid_priority <= reg2dp_lut_hybrid_priority;

        cfg_lut_le_slope_oflow_scale <= reg2dp_lut_le_slope_oflow_scale;
        cfg_lut_le_slope_oflow_shift <= reg2dp_lut_le_slope_oflow_shift;
        cfg_lut_le_slope_uflow_scale <= reg2dp_lut_le_slope_uflow_scale;
        cfg_lut_le_slope_uflow_shift <= reg2dp_lut_le_slope_uflow_shift;

        cfg_lut_lo_slope_oflow_scale <= reg2dp_lut_lo_slope_oflow_scale;
        cfg_lut_lo_slope_oflow_shift <= reg2dp_lut_lo_slope_oflow_shift;
        cfg_lut_lo_slope_uflow_scale <= reg2dp_lut_lo_slope_uflow_scale;
        cfg_lut_lo_slope_uflow_shift <= reg2dp_lut_lo_slope_uflow_shift;

        cfg_proc_precision      <= reg2dp_proc_precision     ;
        cfg_nan_to_zero         <= reg2dp_nan_to_zero     ;
    end
  end
end
 






NV_NVDLA_SDP_CORE_Y_dmapack u_alu_dmapack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_alu_in_vld)
  ,.inp_data                        (ew_alu_in_data[255:0])
  ,.inp_prdy                        (ew_alu_in_rdy)
  ,.out_pvld                        (flop_ew_alu_in_vld)
  ,.out_data                        (flop_ew_alu_in_data[63:0])
  ,.out_prdy                        (flop_ew_alu_in_rdy)
  );


NV_NVDLA_SDP_CORE_Y_cvt u_alu_cvt (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_in_rsc_z                    (flop_ew_alu_in_data[63:0])
  ,.chn_in_rsc_vz                   (flop_ew_alu_in_vld)
  ,.chn_in_rsc_lz                   (flop_ew_alu_in_rdy)
  ,.cfg_bypass_rsc_z                (cfg_ew_alu_cvt_bypass)
  ,.cfg_offset_rsc_z                (cfg_ew_alu_cvt_offset[31:0])
  ,.cfg_scale_rsc_z                 (cfg_ew_alu_cvt_scale[15:0])
  ,.cfg_truncate_rsc_z              (cfg_ew_alu_cvt_truncate[5:0])
  ,.cfg_nan_to_zero_rsc_z           (cfg_nan_to_zero)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_out_rsc_z                   (alu_cvt_out_pd[127:0])
  ,.chn_out_rsc_vz                  (alu_cvt_out_prdy)
  ,.chn_out_rsc_lz                  (alu_cvt_out_pvld)
  );



NV_NVDLA_SDP_CORE_Y_dmapack u_mul_dmapack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_mul_in_vld)
  ,.inp_data                        (ew_mul_in_data[255:0])
  ,.inp_prdy                        (ew_mul_in_rdy)
  ,.out_pvld                        (flop_ew_mul_in_vld)
  ,.out_data                        (flop_ew_mul_in_data[63:0])
  ,.out_prdy                        (flop_ew_mul_in_rdy)
  );


NV_NVDLA_SDP_CORE_Y_cvt u_mul_cvt (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_in_rsc_z                    (flop_ew_mul_in_data[63:0])
  ,.chn_in_rsc_vz                   (flop_ew_mul_in_vld)
  ,.chn_in_rsc_lz                   (flop_ew_mul_in_rdy)
  ,.cfg_bypass_rsc_z                (cfg_ew_mul_cvt_bypass)
  ,.cfg_offset_rsc_z                (cfg_ew_mul_cvt_offset[31:0])
  ,.cfg_scale_rsc_z                 (cfg_ew_mul_cvt_scale[15:0])
  ,.cfg_truncate_rsc_z              (cfg_ew_mul_cvt_truncate[5:0])
  ,.cfg_nan_to_zero_rsc_z           (cfg_nan_to_zero)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_out_rsc_z                   (mul_cvt_out_pd[127:0])
  ,.chn_out_rsc_vz                  (mul_cvt_out_prdy)
  ,.chn_out_rsc_lz                  (mul_cvt_out_pvld)
  );



NV_NVDLA_SDP_CORE_Y_dppack u_dppack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (ew_data_in_pvld)
  ,.inp_data                        (ew_data_in_pd[511:0])
  ,.inp_prdy                        (ew_data_in_prdy)
  ,.out_pvld                        (flop_ew_data_in_pvld)
  ,.out_data                        (flop_ew_data_in_pd[127:0])
  ,.out_prdy                        (flop_ew_data_in_prdy)
  );


NV_NVDLA_SDP_CORE_Y_core u_core (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_data_in_rsc_z               (flop_ew_data_in_pd[127:0])
  ,.chn_data_in_rsc_vz              (flop_ew_data_in_pvld)
  ,.chn_data_in_rsc_lz              (flop_ew_data_in_prdy)
  ,.chn_alu_op_rsc_z                (alu_cvt_out_pd[127:0])
  ,.chn_alu_op_rsc_vz               (alu_cvt_out_pvld)
  ,.chn_alu_op_rsc_lz               (alu_cvt_out_prdy)
  ,.chn_mul_op_rsc_z                (mul_cvt_out_pd[127:0])
  ,.chn_mul_op_rsc_vz               (mul_cvt_out_pvld)
  ,.chn_mul_op_rsc_lz               (mul_cvt_out_prdy)
  ,.cfg_alu_bypass_rsc_z            (cfg_ew_alu_bypass)
  ,.cfg_alu_bypass_rsc_triosy_lz    ()
  ,.cfg_alu_src_rsc_z               (cfg_ew_alu_src)
  ,.cfg_alu_src_rsc_triosy_lz       ()
  ,.cfg_alu_op_rsc_z                (cfg_ew_alu_operand[31:0])
  ,.cfg_alu_op_rsc_triosy_lz        ()
  ,.cfg_alu_algo_rsc_z              (cfg_ew_alu_algo[1:0])
  ,.cfg_alu_algo_rsc_triosy_lz      ()
  ,.cfg_mul_bypass_rsc_z            (cfg_ew_mul_bypass)
  ,.cfg_mul_bypass_rsc_triosy_lz    ()
  ,.cfg_mul_src_rsc_z               (cfg_ew_mul_src)
  ,.cfg_mul_src_rsc_triosy_lz       ()
  ,.cfg_mul_op_rsc_z                (cfg_ew_mul_operand[31:0])
  ,.cfg_mul_op_rsc_triosy_lz        ()
  ,.cfg_truncate_rsc_z              (cfg_ew_truncate[9:0])
  ,.cfg_truncate_rsc_triosy_lz      ()
  ,.cfg_mul_prelu_rsc_z             (cfg_ew_mul_prelu)
  ,.cfg_mul_prelu_rsc_triosy_lz     ()
  ,.cfg_precision                   (cfg_proc_precision[1:0])
  ,.chn_data_out_rsc_z              (core_out_pd[127:0])
  ,.chn_data_out_rsc_vz             (core_out_prdy)
  ,.chn_data_out_rsc_lz             (core_out_pvld)
  );

assign idx_in_pvld = cfg_ew_lut_bypass ? 1'b0 : core_out_pvld;
assign idx_in_pd   =  {128{idx_in_pvld}} & core_out_pd;
assign core_out_prdy = cfg_ew_lut_bypass ? unpack_in_prdy : idx_in_prdy;

NV_NVDLA_SDP_CORE_Y_idx u_idx (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_lut_in_rsc_z                (idx_in_pd[127:0])
  ,.chn_lut_in_rsc_vz               (idx_in_pvld)
  ,.chn_lut_in_rsc_lz               (idx_in_prdy)
  ,.cfg_lut_le_start_rsc_z          (cfg_lut_le_start[31:0])
  ,.cfg_lut_lo_start_rsc_z          (cfg_lut_lo_start[31:0])
  ,.cfg_lut_le_index_offset_rsc_z   (cfg_lut_le_index_offset[7:0])
  ,.cfg_lut_le_index_select_rsc_z   (cfg_lut_le_index_select[7:0])
  ,.cfg_lut_lo_index_select_rsc_z   (cfg_lut_lo_index_select[7:0])
  ,.cfg_lut_le_function_rsc_z       (cfg_lut_le_function)
  ,.cfg_lut_uflow_priority_rsc_z    (cfg_lut_uflow_priority)
  ,.cfg_lut_oflow_priority_rsc_z    (cfg_lut_oflow_priority)
  ,.cfg_lut_hybrid_priority_rsc_z   (cfg_lut_hybrid_priority)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_lut_out_rsc_z               (idx2lut_pd[323:0])
  ,.chn_lut_out_rsc_vz              (idx2lut_prdy)
  ,.chn_lut_out_rsc_lz              (idx2lut_pvld)
  );




NV_NVDLA_SDP_CORE_Y_lut u_lut (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.lut2inp_pvld                    (lut2inp_pvld)
  ,.lut2inp_prdy                    (lut2inp_prdy)
  ,.lut2inp_pd                      (lut2inp_pd[739:0])
  ,.idx2lut_pvld                    (idx2lut_pvld)
  ,.idx2lut_prdy                    (idx2lut_prdy)
  ,.idx2lut_pd                      (idx2lut_pd[323:0])
  ,.reg2dp_lut_int_access_type      (reg2dp_lut_int_access_type)
  ,.reg2dp_lut_int_addr             (reg2dp_lut_int_addr[9:0])
  ,.reg2dp_lut_int_data             (reg2dp_lut_int_data[15:0])
  ,.reg2dp_lut_int_data_wr          (reg2dp_lut_int_data_wr)
  ,.reg2dp_lut_int_table_id         (reg2dp_lut_int_table_id)
  ,.reg2dp_lut_le_end               (cfg_lut_le_end[31:0])
  ,.reg2dp_lut_le_function          (reg2dp_lut_le_function)
  ,.reg2dp_lut_le_index_offset      (reg2dp_lut_le_index_offset[7:0])
  ,.reg2dp_lut_le_slope_oflow_scale (cfg_lut_le_slope_oflow_scale[15:0])
  ,.reg2dp_lut_le_slope_oflow_shift (cfg_lut_le_slope_oflow_shift[4:0])
  ,.reg2dp_lut_le_slope_uflow_scale (cfg_lut_le_slope_uflow_scale[15:0])
  ,.reg2dp_lut_le_slope_uflow_shift (cfg_lut_le_slope_uflow_shift[4:0])
  ,.reg2dp_lut_le_start             (cfg_lut_le_start[31:0])
  ,.reg2dp_lut_lo_end               (cfg_lut_lo_end[31:0])
  ,.reg2dp_lut_lo_slope_oflow_scale (cfg_lut_lo_slope_oflow_scale[15:0])
  ,.reg2dp_lut_lo_slope_oflow_shift (cfg_lut_lo_slope_oflow_shift[4:0])
  ,.reg2dp_lut_lo_slope_uflow_scale (cfg_lut_lo_slope_uflow_scale[15:0])
  ,.reg2dp_lut_lo_slope_uflow_shift (cfg_lut_lo_slope_uflow_shift[4:0])
  ,.reg2dp_lut_lo_start             (cfg_lut_lo_start[31:0])
  ,.reg2dp_perf_lut_en              (reg2dp_perf_lut_en)
  ,.reg2dp_proc_precision           (reg2dp_proc_precision[1:0])
  ,.dp2reg_lut_hybrid               (dp2reg_lut_hybrid[31:0])
  ,.dp2reg_lut_int_data             (dp2reg_lut_int_data[15:0])
  ,.dp2reg_lut_le_hit               (dp2reg_lut_le_hit[31:0])
  ,.dp2reg_lut_lo_hit               (dp2reg_lut_lo_hit[31:0])
  ,.dp2reg_lut_oflow                (dp2reg_lut_oflow[31:0])
  ,.dp2reg_lut_uflow                (dp2reg_lut_uflow[31:0])
  ,.pwrbus_ram_pd                   (pwrbus_ram_pd[31:0])
  ,.op_en_load                      (op_en_load)
  );



NV_NVDLA_SDP_CORE_Y_inp u_inp (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.chn_inp_in_rsc_z                (lut2inp_pd[739:0])
  ,.chn_inp_in_rsc_vz               (lut2inp_pvld)
  ,.chn_inp_in_rsc_lz               (lut2inp_prdy)
  ,.cfg_precision_rsc_z             (cfg_proc_precision[1:0])
  ,.chn_inp_out_rsc_z               (inp_out_pd[127:0])
  ,.chn_inp_out_rsc_vz              (inp_out_prdy)
  ,.chn_inp_out_rsc_lz              (inp_out_pvld)
  );

assign unpack_in_pvld = cfg_ew_lut_bypass ? core_out_pvld : inp_out_pvld;
assign unpack_in_pd   = cfg_ew_lut_bypass ? core_out_pd   : inp_out_pd;
assign inp_out_prdy   = cfg_ew_lut_bypass ? 1'b0 : unpack_in_prdy;



NV_NVDLA_SDP_CORE_Y_dpunpack u_dpunpack (
   .nvdla_core_clk                  (nvdla_core_clk)
  ,.nvdla_core_rstn                 (nvdla_core_rstn)
  ,.inp_pvld                        (unpack_in_pvld)
  ,.inp_data                        (unpack_in_pd[127:0])
  ,.inp_prdy                        (unpack_in_prdy)
  ,.out_pvld                        (ew_data_out_pvld)
  ,.out_data                        (ew_data_out_pd[511:0])
  ,.out_prdy                        (ew_data_out_prdy)
  );

endmodule