data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:51: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:57: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,                  \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:60: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,    \n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:61: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,    \n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:62: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] requested_rate,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:63: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    output wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:68: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp0;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:69: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp1;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:70: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp2;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:71: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] effective_rate;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:72: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_value;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:73: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] requested_rate_shifted;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:75: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [COUNTER_WIDTH-1:0] counter [0:`NUM_OPERATORS_PER_BANK-1];\n                                       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:77: Define or directive not defined: \'`CLOG2\'\n    wire [`CLOG2(OVERFLOW_TMP_MAX_VALUE)-1:0] overflow_tmp;\n          ^~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:99: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n        for (i = 0; i < `NUM_OPERATORS_PER_BANK; i = i + 1) begin: named\n                        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for (i = 0; i < `NUM_OPERATORS_PER_BANK; i = i + 1) begin: named\n                                               ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/env_rate_counter.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module env_rate_counter (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,                  
    input wire ksr,
    input wire nts,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,    
    input wire [`REG_BLOCK_WIDTH-1:0] block,    
    input wire [`REG_ENV_WIDTH-1:0] requested_rate,
    output wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow
);
    localparam COUNTER_WIDTH = 15;
    localparam OVERFLOW_TMP_MAX_VALUE = 7<<15;
    
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp0;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp1;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp2;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] effective_rate;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_value;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] requested_rate_shifted;
    wire [1:0] rof;
    reg [COUNTER_WIDTH-1:0] counter [0:`NUM_OPERATORS_PER_BANK-1];

    wire [`CLOG2(OVERFLOW_TMP_MAX_VALUE)-1:0] overflow_tmp;
    reg sample_clk_en_d0;
    
    assign rate_tmp0 = nts ? fnum[8] : fnum[9];
    assign rate_tmp1 = rate_tmp0 | (block << 1);
    assign rate_tmp2 = ksr ? rate_tmp1 : rate_tmp1 >> 2;
    assign requested_rate_shifted = requested_rate << 2;
    
    assign effective_rate = (rate_tmp2 + requested_rate_shifted > 60) ? 
     60 : rate_tmp2 + requested_rate_shifted;
        
    assign rate_value = effective_rate >> 2;
    assign rof = effective_rate[1:0];

    always @(posedge clk)
        if (reset)
            sample_clk_en_d0 <= 0;
        else
            sample_clk_en_d0 <= sample_clk_en;

    genvar i;
    generate
        for (i = 0; i < `NUM_OPERATORS_PER_BANK; i = i + 1) begin: named
            always @(posedge clk) begin
                if (reset)
                    counter[i] <= 0;
                else if (sample_clk_en_d0 && requested_rate != 0 && (op_num == i))
                    counter[i] <= counter[i] + ((4 | rof) << rate_value);
            end
        end
    endgenerate
        
    assign overflow_tmp = counter[op_num] + ((4 | rof) << rate_value);
    
    assign
        rate_counter_overflow = overflow_tmp >> 15;
    
endmodule
module env_rate_counter (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,                  
    input wire ksr,
    input wire nts,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,    
    input wire [`REG_BLOCK_WIDTH-1:0] block,    
    input wire [`REG_ENV_WIDTH-1:0] requested_rate,
    output wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow
);

    localparam COUNTER_WIDTH = 15;
    localparam OVERFLOW_TMP_MAX_VALUE = 7<<15;
    
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp0;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp1;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp2;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] effective_rate;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_value;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] requested_rate_shifted;
    wire [1:0] rof;
    reg [COUNTER_WIDTH-1:0] counter [0:`NUM_OPERATORS_PER_BANK-1];

    wire [`CLOG2(OVERFLOW_TMP_MAX_VALUE)-1:0] overflow_tmp;
    reg sample_clk_en_d0;
    
    assign rate_tmp0 = nts ? fnum[8] : fnum[9];
    assign rate_tmp1 = rate_tmp0 | (block << 1);
    assign rate_tmp2 = ksr ? rate_tmp1 : rate_tmp1 >> 2;
    assign requested_rate_shifted = requested_rate << 2;
    
    assign effective_rate = (rate_tmp2 + requested_rate_shifted > 60) ? 
     60 : rate_tmp2 + requested_rate_shifted;
        
    assign rate_value = effective_rate >> 2;
    assign rof = effective_rate[1:0];

    always @(posedge clk)
        if (reset)
            sample_clk_en_d0 <= 0;
        else
            sample_clk_en_d0 <= sample_clk_en;

    genvar i;
    generate
        for (i = 0; i < `NUM_OPERATORS_PER_BANK; i = i + 1) begin: named
            always @(posedge clk) begin
                if (reset)
                    counter[i] <= 0;
                else if (sample_clk_en_d0 && requested_rate != 0 && (op_num == i))
                    counter[i] <= counter[i] + ((4 | rof) << rate_value);
            end
        end
    endgenerate
        
    assign overflow_tmp = counter[op_num] + ((4 | rof) << rate_value);
    
    assign
        rate_counter_overflow = overflow_tmp >> 15;
    
endmodule