data/full_repos/permissive/46454310/waterbear.v
1: b'%Error: data/full_repos/permissive/46454310/waterbear.v:44: Duplicate declaration of signal: \'PC\'\n                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg[7:0]  PC;               \n            ^~\n        data/full_repos/permissive/46454310/waterbear.v:14: ... Location of original declaration\n  output[7:0] PC);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/46454310/waterbear.v:225: Signal definition not found, creating implicitly: \'reset\'\n                                                                      : ... Suggested alternative: \'rst\'\n  waterbear core1(clk, reset, PC);\n                       ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module waterbear(
  input clk,
  input rst,
  output[7:0] PC);
  


  parameter IF=2'b00;
  parameter ID=2'b01;
  parameter EX=2'b10;
  parameter WB=2'b11;
  

  integer i;
  

  reg[1:0]  control_unit_current;
  reg[1:0]  control_unit_next;
  

  parameter LDR = 4'b001;
  parameter STR = 4'b010;
  parameter ADD = 4'b011;
  parameter SUB = 4'b100;
  parameter EQU = 4'b101;
  parameter JMP = 4'b110;
  parameter HLT = 4'b111;
  

  reg[15:0] MEM[0:255];
  reg[5:0]  WORKMEM[0:127];
  reg[5:0]  DESTMEM[0:127];
  reg[5:0]  R1;
  reg[7:0]  PC;
  
  reg[7:0]  MAR;
  reg[15:0] MDR;
  reg[15:0] CIR;
  

  reg[4:0]  reserved = 5'b00000;
  reg[3:0]  op_code  = 0;
  reg       numbit   = 0;
  reg[5:0]  operand  = 0;


  
  

  initial begin


    init_regs();
    

    


    

    MEM[0] = {reserved, LDR, 1'b1, 6'b000101};
    MEM[1] = {reserved, STR, 1'b0, 6'b001111};
    MEM[2] = {reserved, LDR, 1'b1, 6'b000000};
    MEM[3] = {reserved, EQU, 1'b0, 6'b001111};
    MEM[4] = {reserved, JMP, 1'b1, 6'b000110};
    MEM[5] = {reserved, HLT, 1'b0, 6'b000000};
    MEM[6] = {reserved, ADD, 1'b1, 6'b000001};
    MEM[7] = {reserved, JMP, 1'b1, 6'b000011};
  end
  

  always @ (clk, rst) begin
    if(rst) begin
      init_regs();
    end
    else begin
      

      case(control_unit_current)
        IF: begin
          MAR = PC;
          PC = PC +1;
          MDR = MEM[MAR];
          CIR = MDR;
          control_unit_next=ID;
        end
        
        ID: begin
          control_unit_next=EX;
          InstructionDecoder(CIR, op_code, numbit, operand);
        end
        
        EX: begin
        

          case(op_code)
            LDR: begin
              if(numbit==1) begin
                R1 = operand;
              end else begin
                R1 = WORKMEM[operand];
              end
              control_unit_next=WB;
            end
            
            STR: begin
              WORKMEM[operand] = R1;
              control_unit_next=WB;
            end
            
            ADD: begin
              if(numbit==1) begin
                R1=R1+operand;
              end else begin
                R1=R1+WORKMEM[operand];
              end
              control_unit_next=WB;
            end
            
            JMP : begin
              PC=operand;
              control_unit_next=WB;
            end
            
            EQU: begin
              if(R1 == WORKMEM[operand]) begin
                PC=PC+1;
              end
              control_unit_next=WB;
            end
                
            HLT: begin
              control_unit_next=EX;
            end
            
            default: begin end
          endcase
        end
        
        WB: begin


          for (i=0; i<127; i=i+1 ) begin
            DESTMEM[i] <= WORKMEM[i];
          end
          
          control_unit_next=IF;
        end
        
        default: begin end
      endcase
      
      control_unit_current=control_unit_next;
    end
  end


  task init_regs;
  begin
    PC                    = 0;
    R1                    = 0;
    MDR                   = 0;
    MAR                   = 0;
    CIR                   = 0;


    control_unit_current  = IF;
    numbit                = 0;
    operand               = 0;
    op_code               = 0;
    reserved              = 0;
  end
  endtask


  task InstructionDecoder;
    input[15:0] CIR;
    output[3:0] op_code;
    output numbit;
    output[5:0] operand;
    begin
      op_code= CIR[10:7];
      numbit=CIR[6:6];
      operand=CIR[5:0];
    end
  endtask
    
endmodule
module waterbear(
  input clk,
  input rst,
  output[7:0] PC);

  


  parameter IF=2'b00;
  parameter ID=2'b01;
  parameter EX=2'b10;
  parameter WB=2'b11;
  

  integer i;
  

  reg[1:0]  control_unit_current;
  reg[1:0]  control_unit_next;
  

  parameter LDR = 4'b001;
  parameter STR = 4'b010;
  parameter ADD = 4'b011;
  parameter SUB = 4'b100;
  parameter EQU = 4'b101;
  parameter JMP = 4'b110;
  parameter HLT = 4'b111;
  

  reg[15:0] MEM[0:255];
  reg[5:0]  WORKMEM[0:127];
  reg[5:0]  DESTMEM[0:127];
  reg[5:0]  R1;
  reg[7:0]  PC;
  
  reg[7:0]  MAR;
  reg[15:0] MDR;
  reg[15:0] CIR;
  

  reg[4:0]  reserved = 5'b00000;
  reg[3:0]  op_code  = 0;
  reg       numbit   = 0;
  reg[5:0]  operand  = 0;


  
  

  initial begin


    init_regs();
    

    


    

    MEM[0] = {reserved, LDR, 1'b1, 6'b000101};
    MEM[1] = {reserved, STR, 1'b0, 6'b001111};
    MEM[2] = {reserved, LDR, 1'b1, 6'b000000};
    MEM[3] = {reserved, EQU, 1'b0, 6'b001111};
    MEM[4] = {reserved, JMP, 1'b1, 6'b000110};
    MEM[5] = {reserved, HLT, 1'b0, 6'b000000};
    MEM[6] = {reserved, ADD, 1'b1, 6'b000001};
    MEM[7] = {reserved, JMP, 1'b1, 6'b000011};
  end
  

  always @ (clk, rst) begin
    if(rst) begin
      init_regs();
    end
    else begin
      

      case(control_unit_current)
        IF: begin
          MAR = PC;
          PC = PC +1;
          MDR = MEM[MAR];
          CIR = MDR;
          control_unit_next=ID;
        end
        
        ID: begin
          control_unit_next=EX;
          InstructionDecoder(CIR, op_code, numbit, operand);
        end
        
        EX: begin
        

          case(op_code)
            LDR: begin
              if(numbit==1) begin
                R1 = operand;
              end else begin
                R1 = WORKMEM[operand];
              end
              control_unit_next=WB;
            end
            
            STR: begin
              WORKMEM[operand] = R1;
              control_unit_next=WB;
            end
            
            ADD: begin
              if(numbit==1) begin
                R1=R1+operand;
              end else begin
                R1=R1+WORKMEM[operand];
              end
              control_unit_next=WB;
            end
            
            JMP : begin
              PC=operand;
              control_unit_next=WB;
            end
            
            EQU: begin
              if(R1 == WORKMEM[operand]) begin
                PC=PC+1;
              end
              control_unit_next=WB;
            end
                
            HLT: begin
              control_unit_next=EX;
            end
            
            default: begin end
          endcase
        end
        
        WB: begin


          for (i=0; i<127; i=i+1 ) begin
            DESTMEM[i] <= WORKMEM[i];
          end
          
          control_unit_next=IF;
        end
        
        default: begin end
      endcase
      
      control_unit_current=control_unit_next;
    end
  end


  task init_regs;
  begin
    PC                    = 0;
    R1                    = 0;
    MDR                   = 0;
    MAR                   = 0;
    CIR                   = 0;


    control_unit_current  = IF;
    numbit                = 0;
    operand               = 0;
    op_code               = 0;
    reserved              = 0;
  end
  endtask


  task InstructionDecoder;
    input[15:0] CIR;
    output[3:0] op_code;
    output numbit;
    output[5:0] operand;
    begin
      op_code= CIR[10:7];
      numbit=CIR[6:6];
      operand=CIR[5:0];
    end
  endtask
    
endmodule