data/full_repos/permissive/523038000/lab6/counter_pushbutton.v
1: b'%Warning-WIDTH: data/full_repos/permissive/523038000/lab6/counter_pushbutton.v:64: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance counter_pushbutton\n       pc_r <= 1\'b0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter_pushbutton(
	input 	clk,
	input 	rst,
	input 	push_button,
	output [8:0] pc
    );
    

reg [8:0] pc_r;
reg	 push_button_r, pc_en;			
 

always@(posedge clk or posedge rst)
begin
    if (rst)
       push_button_r <= 1'b0;
    else
       push_button_r <= push_button;
end



always@* 
   pc_en <= push_button & ~ push_button_r;
   
   
always@(posedge pc_en or posedge rst)
begin
    if (rst)
       pc_r <= 1'b0;
    else
       pc_r <= pc+1;
end


assign pc = pc_r;


endmodule
module counter_pushbutton(
	input 	clk,
	input 	rst,
	input 	push_button,
	output [8:0] pc
    );

    

reg [8:0] pc_r;
reg	 push_button_r, pc_en;			
 

always@(posedge clk or posedge rst)
begin
    if (rst)
       push_button_r <= 1'b0;
    else
       push_button_r <= push_button;
end



always@* 
   pc_en <= push_button & ~ push_button_r;
   
   
always@(posedge pc_en or posedge rst)
begin
    if (rst)
       pc_r <= 1'b0;
    else
       pc_r <= pc+1;
end


assign pc = pc_r;


endmodule