data/full_repos/permissive/482006041/6-2/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:5: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("wave.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:6: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0, tb);\n       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n       #6000 $finish;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #20 X <= $random();\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482006041/6-2/user/sim/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1\'b1;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb ();

    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg X, clk = 1'b0, reset = 1'b1;

    always 
        #10 clk <= ~clk;

    always 
        #20 X <= $random();

    initial begin
        #10 reset = 1'b0;
        #10 reset = 1'b1;
    end

    wire Z;

    string01011_moore u_string01011_moore(

        .clk   		( clk   		),
        .reset 		( reset 		),
        .X     		( X     		),
        .Z     		( Z     		)
    );

endmodule
module tb ();


    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg X, clk = 1'b0, reset = 1'b1;

    always 
        #10 clk <= ~clk;

    always 
        #20 X <= $random();

    initial begin
        #10 reset = 1'b0;
        #10 reset = 1'b1;
    end

    wire Z;

    string01011_moore u_string01011_moore(

        .clk   		( clk   		),
        .reset 		( reset 		),
        .X     		( X     		),
        .Z     		( Z     		)
    );

endmodule