data/full_repos/permissive/51711917/2/nexys2/uxa/ps2io/M_uxa_ps2_busctl.v
data/verilator_xmls/81a2f8fb-4d61-43c2-a0ad-8432b617ea14.xml
module M_uxa_ps2_busctl(
	input sys_clk_i,
	input sys_reset_i,
	input wb_we_i,
	input wb_stb_i,
	input wb_dat_8_i,
	input wb_dat_9_i,
	output wb_ack_o,
	output rp_inc_o,
	output c_oe_o,
	output d_oe_o
);












	reg wb_ack;
	assign wb_ack_o = wb_ack;
	



	reg c_oe;
	reg d_oe;
	assign c_oe_o = c_oe;
	assign d_oe_o = d_oe;
	


	reg rp_inc;
	wire rp_inc_n = (~sys_reset_i & wb_stb_i & wb_we_i);
	assign rp_inc_o = rp_inc;

	always @(posedge sys_clk_i) begin
		if (sys_reset_i) begin
			c_oe <= 0;
			d_oe <= 0;
			rp_inc <= 0;
			wb_ack <= 0;
		end else begin
			wb_ack <= ~wb_ack & wb_stb_i;
			rp_inc <= rp_inc_n;
			if(wb_stb_i & wb_we_i) begin
				c_oe <= ~wb_dat_9_i;
				d_oe <= ~wb_dat_8_i;
			end
		end
	end
endmodule
module M_uxa_ps2_busctl(
	input sys_clk_i,
	input sys_reset_i,
	input wb_we_i,
	input wb_stb_i,
	input wb_dat_8_i,
	input wb_dat_9_i,
	output wb_ack_o,
	output rp_inc_o,
	output c_oe_o,
	output d_oe_o
);













	reg wb_ack;
	assign wb_ack_o = wb_ack;
	



	reg c_oe;
	reg d_oe;
	assign c_oe_o = c_oe;
	assign d_oe_o = d_oe;
	


	reg rp_inc;
	wire rp_inc_n = (~sys_reset_i & wb_stb_i & wb_we_i);
	assign rp_inc_o = rp_inc;

	always @(posedge sys_clk_i) begin
		if (sys_reset_i) begin
			c_oe <= 0;
			d_oe <= 0;
			rp_inc <= 0;
			wb_ack <= 0;
		end else begin
			wb_ack <= ~wb_ack & wb_stb_i;
			rp_inc <= rp_inc_n;
			if(wb_stb_i & wb_we_i) begin
				c_oe <= ~wb_dat_9_i;
				d_oe <= ~wb_dat_8_i;
			end
		end
	end
endmodule