data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/sbt/AddSub.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/sbt/AddSub.v:25: Operator DIVS expects 6 bits on the LHS, but LHS\'s SIGNED generates 4 bits.\n                                                                                                : ... In instance AddSub\n  wire [4:0] _T_58 = $signed(io_s2) / $signed(io_s3);  \n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/sbt/AddSub.v:25: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s DIVS generates 6 bits.\n                                                                                                : ... In instance AddSub\n  wire [4:0] _T_58 = $signed(io_s2) / $signed(io_s3);  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/sbt/AddSub.v:40: Operator DIV expects 6 bits on the LHS, but LHS\'s VARREF \'io_u2\' generates 4 bits.\n                                                                                                : ... In instance AddSub\n  assign io_uout_div = io_u2 / io_u3;  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/sbt/AddSub.v:40: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 6 bits.\n                                                                                                : ... In instance AddSub\n  assign io_uout_div = io_u2 / io_u3;  \n                     ^\n%Error: Exiting due to 4 warning(s)\n'
module AddSub(
  input        clock,
  input        reset,
  input  [7:0] io_u0,
  input  [7:0] io_u1,
  input  [7:0] io_s0,
  input  [7:0] io_s1,
  output [8:0] io_uout_add,
  output [8:0] io_sout_add,
  output [7:0] io_uout_add_no_co,
  output [7:0] io_sout_add_no_co,
  output [8:0] io_uout_sub,
  output [8:0] io_sout_sub,
  input  [3:0] io_u2,
  input  [5:0] io_u3,
  input  [3:0] io_s2,
  input  [5:0] io_s3,
  output [9:0] io_uout_mul,
  output [9:0] io_sout_mul,
  output [3:0] io_uout_div,
  output [3:0] io_sout_div,
  output [5:0] io_uout_rem,
  output [5:0] io_sout_rem
);
  wire [4:0] _T_58 = $signed(io_s2) / $signed(io_s3);
  wire [5:0] _GEN_0 = {{2'd0}, io_u2};
  wire [5:0] _GEN_2 = _GEN_0 % io_u3;
  wire [3:0] _T_59 = _GEN_2[3:0];
  wire [5:0] _GEN_1 = {{2{io_s2[3]}},io_s2};
  wire [5:0] _GEN_3 = $signed(_GEN_1) % $signed(io_s3);
  wire [3:0] _T_60 = _GEN_3[3:0];
  assign io_uout_add = io_u0 + io_u1;
  assign io_sout_add = $signed(io_s0) + $signed(io_s1);
  assign io_uout_add_no_co = io_u0 + io_u1;
  assign io_sout_add_no_co = $signed(io_s0) + $signed(io_s1);
  assign io_uout_sub = io_u0 - io_u1;
  assign io_sout_sub = $signed(io_s0) - $signed(io_s1);
  assign io_uout_mul = io_u2 * io_u3;
  assign io_sout_mul = $signed(io_s2) * $signed(io_s3);
  assign io_uout_div = io_u2 / io_u3;
  assign io_sout_div = _T_58[3:0];
  assign io_uout_rem = {{2'd0}, _T_59};
  assign io_sout_rem = {{2'd0}, _T_60};
endmodule
module AddSub(
  input        clock,
  input        reset,
  input  [7:0] io_u0,
  input  [7:0] io_u1,
  input  [7:0] io_s0,
  input  [7:0] io_s1,
  output [8:0] io_uout_add,
  output [8:0] io_sout_add,
  output [7:0] io_uout_add_no_co,
  output [7:0] io_sout_add_no_co,
  output [8:0] io_uout_sub,
  output [8:0] io_sout_sub,
  input  [3:0] io_u2,
  input  [5:0] io_u3,
  input  [3:0] io_s2,
  input  [5:0] io_s3,
  output [9:0] io_uout_mul,
  output [9:0] io_sout_mul,
  output [3:0] io_uout_div,
  output [3:0] io_sout_div,
  output [5:0] io_uout_rem,
  output [5:0] io_sout_rem
);

  wire [4:0] _T_58 = $signed(io_s2) / $signed(io_s3);
  wire [5:0] _GEN_0 = {{2'd0}, io_u2};
  wire [5:0] _GEN_2 = _GEN_0 % io_u3;
  wire [3:0] _T_59 = _GEN_2[3:0];
  wire [5:0] _GEN_1 = {{2{io_s2[3]}},io_s2};
  wire [5:0] _GEN_3 = $signed(_GEN_1) % $signed(io_s3);
  wire [3:0] _T_60 = _GEN_3[3:0];
  assign io_uout_add = io_u0 + io_u1;
  assign io_sout_add = $signed(io_s0) + $signed(io_s1);
  assign io_uout_add_no_co = io_u0 + io_u1;
  assign io_sout_add_no_co = $signed(io_s0) + $signed(io_s1);
  assign io_uout_sub = io_u0 - io_u1;
  assign io_sout_sub = $signed(io_s0) - $signed(io_s1);
  assign io_uout_mul = io_u2 * io_u3;
  assign io_sout_mul = $signed(io_s2) * $signed(io_s3);
  assign io_uout_div = io_u2 / io_u3;
  assign io_sout_div = _T_58[3:0];
  assign io_uout_rem = {{2'd0}, _T_59};
  assign io_sout_rem = {{2'd0}, _T_60};
endmodule