data/full_repos/permissive/515100461/sequential/fetch.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/515100461/sequential/fetch.v:7: Little bit endian vector: MSB < LSB of bit range: 0:7\n  reg [0:7] inst_mem[0:512];\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/515100461/sequential/fetch.v:8: Little bit endian vector: MSB < LSB of bit range: 0:79\n  reg [0:79] inst;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:68: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:68: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:68: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:68: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:68: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:69: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:69: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:69: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:69: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/sequential/fetch.v:69: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                          : ... In instance fetch\n             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                                                     ^\n%Error: Exiting due to 12 warning(s)\n'
module fetch(clk,PC,icode,ifun,rA,rB,valP,valC,hlt,inst_valid,mem_error);
  input clk;
  input [63:0] PC;
  output reg [3:0] icode, ifun;
  output reg [3:0] rA, rB;
  output reg [63:0] valC, valP;
  reg [0:7] inst_mem[0:512];
  reg [0:79] inst;
  output reg hlt,inst_valid,mem_error;

initial begin

  





  inst_mem[1]=8'b00110000;
  inst_mem[2]=8'b00100100;
  inst_mem[3]=8'b00000000;           
  inst_mem[4]=8'b00000000;           
  inst_mem[5]=8'b00000000;           
  inst_mem[6]=8'b00000000;           
  inst_mem[7]=8'b00000000;           
  inst_mem[8]=8'b00000000;          
  inst_mem[9]=8'b00000001; 
  inst_mem[10]=8'b10000001;


  inst_mem[11]=8'b00100000;
  inst_mem[12]=8'b01000010;







  


    inst_mem[19] = 8'b01100000;
    inst_mem[20] = 8'b00110010;
    inst_mem[21] = 8'b01100000;
    inst_mem[22] = 8'b01100111;
    inst_mem[23] = 8'b00100000;
    inst_mem[24] = 8'b01100111;

    













  end

always @(posedge clk)
begin
    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], 
             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};

    icode = inst[0:3];
    ifun = inst[4:7];
    mem_error=0;
    if(PC>512)
    mem_error = 1;

    inst_valid= 1;

    case(icode)

        4'b0000 :
        begin 
            valP = PC + 64'd1;
            hlt = 1;       
        end

        4'b0001 : valP = PC + 64'd1;

        4'b0010 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2;
        end

        4'b0011 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end
  
        4'b0100 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end

        4'b0101 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end

        4'b0110 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2;
        end

        4'b0111 :
        begin 
            valC = inst[8:71];
            valP = PC + 64'd9;
        end

        4'b1000 :
        begin
            valC = inst[8:71];
            valP = PC + 64'd9; 
        end

        4'b1001 :
        begin
            valP = PC + 64'd1;
        end

        4'b1010:
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2; 
            end

        4'b1011:
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2; 
        end

        default : inst_valid=0;
  endcase
end 
endmodule
module fetch(clk,PC,icode,ifun,rA,rB,valP,valC,hlt,inst_valid,mem_error);

  input clk;
  input [63:0] PC;
  output reg [3:0] icode, ifun;
  output reg [3:0] rA, rB;
  output reg [63:0] valC, valP;
  reg [0:7] inst_mem[0:512];
  reg [0:79] inst;
  output reg hlt,inst_valid,mem_error;

initial begin

  





  inst_mem[1]=8'b00110000;
  inst_mem[2]=8'b00100100;
  inst_mem[3]=8'b00000000;           
  inst_mem[4]=8'b00000000;           
  inst_mem[5]=8'b00000000;           
  inst_mem[6]=8'b00000000;           
  inst_mem[7]=8'b00000000;           
  inst_mem[8]=8'b00000000;          
  inst_mem[9]=8'b00000001; 
  inst_mem[10]=8'b10000001;


  inst_mem[11]=8'b00100000;
  inst_mem[12]=8'b01000010;







  


    inst_mem[19] = 8'b01100000;
    inst_mem[20] = 8'b00110010;
    inst_mem[21] = 8'b01100000;
    inst_mem[22] = 8'b01100111;
    inst_mem[23] = 8'b00100000;
    inst_mem[24] = 8'b01100111;

    













  end

always @(posedge clk)
begin
    inst ={inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], 
             inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};

    icode = inst[0:3];
    ifun = inst[4:7];
    mem_error=0;
    if(PC>512)
    mem_error = 1;

    inst_valid= 1;

    case(icode)

        4'b0000 :
        begin 
            valP = PC + 64'd1;
            hlt = 1;       
        end

        4'b0001 : valP = PC + 64'd1;

        4'b0010 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2;
        end

        4'b0011 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end
  
        4'b0100 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end

        4'b0101 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valC = inst[16:79];
            valP = PC + 64'd10;
        end

        4'b0110 :
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2;
        end

        4'b0111 :
        begin 
            valC = inst[8:71];
            valP = PC + 64'd9;
        end

        4'b1000 :
        begin
            valC = inst[8:71];
            valP = PC + 64'd9; 
        end

        4'b1001 :
        begin
            valP = PC + 64'd1;
        end

        4'b1010:
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2; 
            end

        4'b1011:
        begin
            rA = inst[8:11];
            rB = inst[12:15];
            valP = PC + 64'd2; 
        end

        default : inst_valid=0;
  endcase
end 
endmodule