data/full_repos/permissive/51449864/verilog/binary_to_bcd.v
data/verilator_xmls/de993bb3-63da-40ed-9b45-c5fde9620f61.xml
module binary_to_bcd(binary, bcd);
	parameter BITS_IN = 8;
	parameter DIGITS_OUT = 3;
	
	input [BITS_IN-1:0] binary;
	
	output reg [4*DIGITS_OUT-1:0] bcd;
	
	integer b, d;
	

	always @(binary)
	begin
		bcd = 0;
		for (b = BITS_IN - 1; b >= 0; b = b - 1)
		begin
			for (d = 0; d < DIGITS_OUT; d = d + 1)
				if (bcd[d*4 +: 4] >= 5)
					bcd[d*4 +: 4] = bcd[d*4 +: 4] + 3;
			bcd = bcd << 1; 
			bcd[0] = binary[b];
		end
	end
endmodule
module binary_to_bcd(binary, bcd);

	parameter BITS_IN = 8;
	parameter DIGITS_OUT = 3;
	
	input [BITS_IN-1:0] binary;
	
	output reg [4*DIGITS_OUT-1:0] bcd;
	
	integer b, d;
	

	always @(binary)
	begin
		bcd = 0;
		for (b = BITS_IN - 1; b >= 0; b = b - 1)
		begin
			for (d = 0; d < DIGITS_OUT; d = d + 1)
				if (bcd[d*4 +: 4] >= 5)
					bcd[d*4 +: 4] = bcd[d*4 +: 4] + 3;
			bcd = bcd << 1; 
			bcd[0] = binary[b];
		end
	end
endmodule