data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:11: Unsupported: Ignoring delay on this delayed statement.\n    always #5000 clock <= !clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("timer_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,timer_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #7500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #5700000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #8000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/timer_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #6764500; $finish;\n        ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module timer_tb ();

    reg [3:0] data;
    reg loadn, clearn, clock, en;

    wire [3:0] sec_ones, sec_tens, mins;
    wire zero;

    always #5000 clock <= !clock;

    timer DUT(.data(data), .loadn(loadn), .clock(clock), .clearn(clearn), .en(en), .sec_ones(sec_ones), .sec_tens(sec_tens), .mins(mins), .zero(zero));


    initial begin
        $dumpfile("timer_tb.vcd");
        $dumpvars(0,timer_tb);
        
    end


    initial begin
        loadn = 0;
        clearn = 0;
        clock = 1;
        en = 0;

        data = 4'd8;
        #7500;

        data = 4'd5;
        #10000;

        data = 4'd7;
        #10000;

        loadn = 1;
        en = 1;

        #5700000;
        clearn = 1;
        #8000;
        clearn = 0;
        #6764500; $finish;
    end
endmodule
module timer_tb ();


    reg [3:0] data;
    reg loadn, clearn, clock, en;

    wire [3:0] sec_ones, sec_tens, mins;
    wire zero;

    always #5000 clock <= !clock;

    timer DUT(.data(data), .loadn(loadn), .clock(clock), .clearn(clearn), .en(en), .sec_ones(sec_ones), .sec_tens(sec_tens), .mins(mins), .zero(zero));


    initial begin
        $dumpfile("timer_tb.vcd");
        $dumpvars(0,timer_tb);
        
    end


    initial begin
        loadn = 0;
        clearn = 0;
        clock = 1;
        en = 0;

        data = 4'd8;
        #7500;

        data = 4'd5;
        #10000;

        data = 4'd7;
        #10000;

        loadn = 1;
        en = 1;

        #5700000;
        clearn = 1;
        #8000;
        clearn = 0;
        #6764500; $finish;
    end
endmodule