data/full_repos/permissive/441359809/src/yosys/tests/svtypes/multirange_array.sv
data/verilator_xmls/04544e67-3f5b-467e-80ad-a200fecae0bf.xml
module top;

	logic a [3];
	logic b [3][5];
	logic c [3][5][7];

	`STATIC_ASSERT($bits(a) == 3);
	`STATIC_ASSERT($bits(b) == 15);
	`STATIC_ASSERT($bits(c) == 105);

endmodule
module top;


	logic a [3];
	logic b [3][5];
	logic c [3][5][7];

	`STATIC_ASSERT($bits(a) == 3);
	`STATIC_ASSERT($bits(b) == 15);
	`STATIC_ASSERT($bits(c) == 105);

endmodule