data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:38: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                  : ... In instance Controller\n                state <= 3\'b0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:60: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_state\' generates 3 bits.\n                                                                                  : ... In instance Controller\n                    state <= next_state;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_state\' generates 3 bits.\n                                                                                  : ... In instance Controller\n                    state <= next_state;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:102: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_state\' generates 3 bits.\n                                                                                   : ... In instance Controller\n                    state <= next_state;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:113: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                            next_state <= sIF;\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:119: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                            next_state <= sIF;\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:153: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n        next_state <= sIF;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:170: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:176: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:187: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:191: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:197: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_state\' generates 3 bits.\n                                                                                   : ... In instance Controller\n                    state<=next_state;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:204: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:211: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:218: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:222: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n                                next_state <= sIF;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:195: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                   : ... In instance Controller\n            else if (next_state == 2\'d3) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:100: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                   : ... In instance Controller\n            else if (next_state == 2\'d2) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:80: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'sID\' generates 2 bits.\n                                                                                  : ... In instance Controller\n            else if (next_state == sID) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:57: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                  : ... In instance Controller\n            if (next_state == sIF) \n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:256: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                   : ... In instance Controller\n   else if (next_state == 2\'d2)begin\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:253: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'sID\' generates 2 bits.\n                                                                                   : ... In instance Controller\n   else if (next_state == sID)begin\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/505446010/4_state_CPU_2/Controller.v:250: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'sIF\' generates 2 bits.\n                                                                                   : ... In instance Controller\n   if (next_state == sIF)begin\n                  ^~\n%Error: Exiting due to 23 warning(s)\n'
module Controller(reset, clk, OpCode, Funct, 
                PCWrite, PCWriteCond, IorD, MemWrite, MemRead,
                IRWrite, MemtoReg, RegDst, RegWrite, ExtOp, LuiOp,
                ALUSrcA, ALUSrcB, ALUOp, PCSource);

    input reset;
    input clk;

    input  [5:0] OpCode;
    input  [5:0] Funct;

    output reg PCWrite;
    output reg PCWriteCond;
    output reg IorD;
    output reg MemWrite;
    output reg MemRead;
    output reg IRWrite;
    output reg [1:0] MemtoReg;
    output reg [1:0] RegDst;
    output reg RegWrite;
    output reg ExtOp;
    output reg LuiOp;
    output reg [1:0] ALUSrcA;
    output reg [1:0] ALUSrcB;
    output reg [3:0] ALUOp;
    output reg [1:0] PCSource;
      
	reg [1:0] state;
	reg [2:0] next_state;
	parameter sIF = 2'b0 ,sID = 2'b1; 

    always @(posedge reset or posedge clk) 
    begin
        if (reset) 
            begin
                state <= 3'b0;
                next_state <=3'b0;
                PCWrite <= 1'b0;
                PCWriteCond <= 1'b0;
                IorD <= 1'b0;
                MemWrite <= 1'b0;
                MemRead <= 1'b0;
                IRWrite <= 1'b0;
                MemtoReg <= 2'b00;
                RegDst <= 2'b0;
                RegWrite <= 1'b0;
                ExtOp <= 1'b0;
                LuiOp <= 1'b0;
                ALUSrcA <= 2'b0;
                ALUSrcB <= 2'b0;
                PCSource <=2'b0;
            end
        else
        begin
            if (next_state == sIF) 
                begin
                    
                    state <= next_state;
                    next_state <= next_state + 2'b1;
                    
                    MemRead <= 1'b1;
                    IRWrite <= 1'b1;
                    PCWrite <= 1'b1;
                    PCSource <= 2'b00;
                    ALUSrcA <= 2'b00;
                    IorD <= 1'b0;
                    ALUSrcB <= 2'b01;
        
                    PCWriteCond <= 1'b0;
                    MemWrite <= 1'b0;
                    MemtoReg <= 2'b00;
                    RegDst <= 2'b0;
                    RegWrite <= 1'b0;
                    ExtOp <= 1'b0;
                    LuiOp <= 1'b0;
                end
                
            else if (next_state == sID) 
                begin
                    state <= next_state;
                    next_state <= next_state + 2'b1;
                    ALUSrcA <= 2'b00;
                    ALUSrcB <= 2'b11;    
                    ExtOp <= 1'b1;
                    
                    PCWrite <= 1'b0;
                    PCWriteCond <= 1'b0;
                    IorD <= 1'b0;
                    MemWrite <= 1'b0;
                    MemRead <= 1'b0;
                    IRWrite <= 1'b0;
                    MemtoReg <= 2'b00;
                    RegDst <= 2'b0;
                    RegWrite <= 1'b0;
                    LuiOp <= 1'b0;
                    PCSource <=2'b0;
                end
            else if (next_state == 2'd2) 
                begin
                    state <= next_state;
                    case(OpCode)
                        6'h00: 
                            begin
                                ALUSrcA <= (Funct==6'h00 || Funct==6'h02 || Funct==6'h03 ) ? 2'b10 : 2'b01; 
                                ALUSrcB <= 2'b00;                       
                                case(Funct)
                                    6'h08:      
                                        begin
                                            PCSource <= 2'b00;
                                            PCWrite  <= 1'b1;
                                            next_state <= sIF;
                                        end
                                    6'h09:        
                                        begin
                                            PCSource <= 2'b00;
                                            PCWrite  <= 1'b1;
                                            next_state <= sIF;
                                            
                                            RegDst <= 2'b01;   
                                            MemtoReg <= 2'b10;
                                            RegWrite <= 1'b1;
                                        end
                                    default:
                                        begin
                                            next_state <= next_state + 2'b1;
                                        end
                                endcase
                            end

						6'h23:
							begin
								ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <= 1;      
                                LuiOp <= 0;
								MemRead <= 1'b1;
                                IorD <= 1'b1;
                                IRWrite <=1'b0;
								
                                next_state <= next_state +2'b1;
							end
						6'h2b:
							begin
								ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <= 1;      
                                LuiOp <= 0;
								MemWrite<=1'b1;
                                IorD <=1'b1;
								
								next_state <= sIF;
							end

                        6'h0f,6'h08,6'h09,6'h0c,6'h0b,6'h0a:      
                            begin
                                ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <=((OpCode==6'h0c)? 0 : 1);      
                                LuiOp <=((OpCode==6'h0f)? 1 : 0);      
                                next_state <= next_state +2'b1;
                            end
                        6'h04: 
                            begin
                                PCWriteCond <= 1'b1;
                                ALUSrcA <= 2'b01;
                                ALUSrcB <= 2'b00;
                                PCSource <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h02: 
                            begin
                                PCWrite <= 1'b1;
                                PCSource <= 2'b10;
                                next_state <= sIF;
                            end
                        6'h03: 
                            begin
                                PCWrite <= 1'b1;
                                PCSource <= 2'b10;
                                                               
                                RegDst <=  2'b10;   
                                MemtoReg <= 2'b10;
                                RegWrite <= 1'b1;
                                
                                next_state <= sIF;
                            end 
                        default: 
                            begin
                                next_state <= sIF;
                            end
                    endcase
                end
            else if (next_state == 2'd3) 
                begin
                    state<=next_state;
                    case(OpCode)
                        6'h00: 
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b01;
                                MemtoReg <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h08,6'h09,6'h0c,6'h0b,6'h0a,6'h0f:      
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b00;
                                MemtoReg <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h23:      
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b00;
                                MemtoReg <= 2'b00;
                                next_state <= sIF;
                            end
                        default: 
                            begin
                                next_state <= sIF;
                            end
                    endcase
                end
         end
    end
    
    



	parameter ADD=4'h0;
	parameter SUB=4'h1;
	parameter FUNCT=4'h2;
	parameter AND=4'h3;
	parameter LU=4'h4;
	parameter SLT=4'h5;
	parameter ADDU=4'h6;
	parameter SLTU=4'h7;
	
    always @(posedge reset or posedge clk) 
    begin
        if (reset) 
            begin
                ALUOp<=4'h0;
            end
        else
        begin
			if (next_state == sIF)begin
				ALUOp<=ADD;
			end
			else if (next_state == sID)begin
				ALUOp<=ADD;
			end
			else if (next_state == 2'd2)begin
				case(OpCode)
					6'h04:begin
						ALUOp<=SUB;
					end
					6'h00:begin
						ALUOp<=FUNCT;
					end
					6'h0c:begin
						ALUOp<=AND;
					end
					6'h0f:begin
						ALUOp<=LU;
					end
					6'h0a:begin
						ALUOp<=SLT;
					end
					6'h0b:begin
						ALUOp<=SLTU;
					end
					6'h23,6'h2b,6'h08:begin
						ALUOp<=ADD;
					end
					6'h09:begin
						ALUOp<=ADDU;
					end
					default:begin
						ALUOp<=4'h0;
					end
				endcase
			end
			else ALUOp<=4'h0;
		end
	end



endmodule
module Controller(reset, clk, OpCode, Funct, 
                PCWrite, PCWriteCond, IorD, MemWrite, MemRead,
                IRWrite, MemtoReg, RegDst, RegWrite, ExtOp, LuiOp,
                ALUSrcA, ALUSrcB, ALUOp, PCSource);


    input reset;
    input clk;

    input  [5:0] OpCode;
    input  [5:0] Funct;

    output reg PCWrite;
    output reg PCWriteCond;
    output reg IorD;
    output reg MemWrite;
    output reg MemRead;
    output reg IRWrite;
    output reg [1:0] MemtoReg;
    output reg [1:0] RegDst;
    output reg RegWrite;
    output reg ExtOp;
    output reg LuiOp;
    output reg [1:0] ALUSrcA;
    output reg [1:0] ALUSrcB;
    output reg [3:0] ALUOp;
    output reg [1:0] PCSource;
      
	reg [1:0] state;
	reg [2:0] next_state;
	parameter sIF = 2'b0 ,sID = 2'b1; 

    always @(posedge reset or posedge clk) 
    begin
        if (reset) 
            begin
                state <= 3'b0;
                next_state <=3'b0;
                PCWrite <= 1'b0;
                PCWriteCond <= 1'b0;
                IorD <= 1'b0;
                MemWrite <= 1'b0;
                MemRead <= 1'b0;
                IRWrite <= 1'b0;
                MemtoReg <= 2'b00;
                RegDst <= 2'b0;
                RegWrite <= 1'b0;
                ExtOp <= 1'b0;
                LuiOp <= 1'b0;
                ALUSrcA <= 2'b0;
                ALUSrcB <= 2'b0;
                PCSource <=2'b0;
            end
        else
        begin
            if (next_state == sIF) 
                begin
                    
                    state <= next_state;
                    next_state <= next_state + 2'b1;
                    
                    MemRead <= 1'b1;
                    IRWrite <= 1'b1;
                    PCWrite <= 1'b1;
                    PCSource <= 2'b00;
                    ALUSrcA <= 2'b00;
                    IorD <= 1'b0;
                    ALUSrcB <= 2'b01;
        
                    PCWriteCond <= 1'b0;
                    MemWrite <= 1'b0;
                    MemtoReg <= 2'b00;
                    RegDst <= 2'b0;
                    RegWrite <= 1'b0;
                    ExtOp <= 1'b0;
                    LuiOp <= 1'b0;
                end
                
            else if (next_state == sID) 
                begin
                    state <= next_state;
                    next_state <= next_state + 2'b1;
                    ALUSrcA <= 2'b00;
                    ALUSrcB <= 2'b11;    
                    ExtOp <= 1'b1;
                    
                    PCWrite <= 1'b0;
                    PCWriteCond <= 1'b0;
                    IorD <= 1'b0;
                    MemWrite <= 1'b0;
                    MemRead <= 1'b0;
                    IRWrite <= 1'b0;
                    MemtoReg <= 2'b00;
                    RegDst <= 2'b0;
                    RegWrite <= 1'b0;
                    LuiOp <= 1'b0;
                    PCSource <=2'b0;
                end
            else if (next_state == 2'd2) 
                begin
                    state <= next_state;
                    case(OpCode)
                        6'h00: 
                            begin
                                ALUSrcA <= (Funct==6'h00 || Funct==6'h02 || Funct==6'h03 ) ? 2'b10 : 2'b01; 
                                ALUSrcB <= 2'b00;                       
                                case(Funct)
                                    6'h08:      
                                        begin
                                            PCSource <= 2'b00;
                                            PCWrite  <= 1'b1;
                                            next_state <= sIF;
                                        end
                                    6'h09:        
                                        begin
                                            PCSource <= 2'b00;
                                            PCWrite  <= 1'b1;
                                            next_state <= sIF;
                                            
                                            RegDst <= 2'b01;   
                                            MemtoReg <= 2'b10;
                                            RegWrite <= 1'b1;
                                        end
                                    default:
                                        begin
                                            next_state <= next_state + 2'b1;
                                        end
                                endcase
                            end

						6'h23:
							begin
								ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <= 1;      
                                LuiOp <= 0;
								MemRead <= 1'b1;
                                IorD <= 1'b1;
                                IRWrite <=1'b0;
								
                                next_state <= next_state +2'b1;
							end
						6'h2b:
							begin
								ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <= 1;      
                                LuiOp <= 0;
								MemWrite<=1'b1;
                                IorD <=1'b1;
								
								next_state <= sIF;
							end

                        6'h0f,6'h08,6'h09,6'h0c,6'h0b,6'h0a:      
                            begin
                                ALUSrcA <= 2'b01;   
                                ALUSrcB <= 2'b10;   
                                ExtOp <=((OpCode==6'h0c)? 0 : 1);      
                                LuiOp <=((OpCode==6'h0f)? 1 : 0);      
                                next_state <= next_state +2'b1;
                            end
                        6'h04: 
                            begin
                                PCWriteCond <= 1'b1;
                                ALUSrcA <= 2'b01;
                                ALUSrcB <= 2'b00;
                                PCSource <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h02: 
                            begin
                                PCWrite <= 1'b1;
                                PCSource <= 2'b10;
                                next_state <= sIF;
                            end
                        6'h03: 
                            begin
                                PCWrite <= 1'b1;
                                PCSource <= 2'b10;
                                                               
                                RegDst <=  2'b10;   
                                MemtoReg <= 2'b10;
                                RegWrite <= 1'b1;
                                
                                next_state <= sIF;
                            end 
                        default: 
                            begin
                                next_state <= sIF;
                            end
                    endcase
                end
            else if (next_state == 2'd3) 
                begin
                    state<=next_state;
                    case(OpCode)
                        6'h00: 
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b01;
                                MemtoReg <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h08,6'h09,6'h0c,6'h0b,6'h0a,6'h0f:      
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b00;
                                MemtoReg <= 2'b01;
                                next_state <= sIF;
                            end
                        6'h23:      
                            begin
                                RegWrite <= 1'b1;
                                RegDst <= 2'b00;
                                MemtoReg <= 2'b00;
                                next_state <= sIF;
                            end
                        default: 
                            begin
                                next_state <= sIF;
                            end
                    endcase
                end
         end
    end
    
    



	parameter ADD=4'h0;
	parameter SUB=4'h1;
	parameter FUNCT=4'h2;
	parameter AND=4'h3;
	parameter LU=4'h4;
	parameter SLT=4'h5;
	parameter ADDU=4'h6;
	parameter SLTU=4'h7;
	
    always @(posedge reset or posedge clk) 
    begin
        if (reset) 
            begin
                ALUOp<=4'h0;
            end
        else
        begin
			if (next_state == sIF)begin
				ALUOp<=ADD;
			end
			else if (next_state == sID)begin
				ALUOp<=ADD;
			end
			else if (next_state == 2'd2)begin
				case(OpCode)
					6'h04:begin
						ALUOp<=SUB;
					end
					6'h00:begin
						ALUOp<=FUNCT;
					end
					6'h0c:begin
						ALUOp<=AND;
					end
					6'h0f:begin
						ALUOp<=LU;
					end
					6'h0a:begin
						ALUOp<=SLT;
					end
					6'h0b:begin
						ALUOp<=SLTU;
					end
					6'h23,6'h2b,6'h08:begin
						ALUOp<=ADD;
					end
					6'h09:begin
						ALUOp<=ADDU;
					end
					default:begin
						ALUOp<=4'h0;
					end
				endcase
			end
			else ALUOp<=4'h0;
		end
	end



endmodule