data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_match5_str_arch.v
1: b"%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_match5_str_arch.v:23: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_match5_str_arch.v:52: syntax error, unexpected always\nalways @(posedge clock)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module 	bm_match5_str_arch(clock, 
		reset_n, 
		a_in, 
		b_in,
		c_in, 
		d_in, 
		e_in, 
		f_in, 
		g_in, 
		h_in, 
		i_in, 
		j_in, 
		out0,
		out1,
		out2,
);


input	clock;
input 	reset_n;

input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
input [`BITS0-1:0] g_in;
input [`BITS0-1:0] h_in;
input [`BITS0-1:0] i_in;
input [`BITS0-1:0] j_in;

output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS2-1:0] out2;

reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS2-1:0] out2;





always @(posedge clock)
begin
	out0 <= a_in * b_in + c_in * d_in;
	out1 <= c_in + d_in;
	out2 <= a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in + g_in * h_in + i_in * j_in;
end

endmodule
module 	bm_match5_str_arch(clock, 
		reset_n, 
		a_in, 
		b_in,
		c_in, 
		d_in, 
		e_in, 
		f_in, 
		g_in, 
		h_in, 
		i_in, 
		j_in, 
		out0,
		out1,
		out2,
);



input	clock;
input 	reset_n;

input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
input [`BITS0-1:0] g_in;
input [`BITS0-1:0] h_in;
input [`BITS0-1:0] i_in;
input [`BITS0-1:0] j_in;

output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS2-1:0] out2;

reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS2-1:0] out2;





always @(posedge clock)
begin
	out0 <= a_in * b_in + c_in * d_in;
	out1 <= c_in + d_in;
	out2 <= a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in + g_in * h_in + i_in * j_in;
end

endmodule