data/full_repos/permissive/515458360/counter4.5_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515458360/counter4.5_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #5  clk=~clk; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515458360/counter4.5_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n               #6 reset=1\'b1;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/515458360/counter4.5_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n               #6 reset=1\'b0;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/515458360/counter4.5_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #6 reset=1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/515458360/counter4.5_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n               #500 $finish;\n               ^\n%Error: data/full_repos/permissive/515458360/counter4.5_tb.v:20: Unsupported or unknown PLI call: $monitor\n               $monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/515458360/counter4.5_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n              $dumpfile("clkdiv3_tb.vcd");\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/515458360/counter4.5_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n              $dumpvars(0,clkdiv3_tb);\n              ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clkdiv3_tb;
  reg clk,reset;
  wire clk_out;
 
     clk_divn t1(clk,reset,clk_out);
        initial
          clk= 1'b0;
     always
        #5  clk=~clk; 
        initial
            begin
               #6 reset=1'b1;
               #6 reset=1'b0;
			   #6 reset=1'b1;
               #500 $finish;
            end
 
        initial
               $monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);
 
        initial
            begin
              $dumpfile("clkdiv3_tb.vcd");
              $dumpvars(0,clkdiv3_tb);
             end
    endmodule
module clkdiv3_tb;

  reg clk,reset;
  wire clk_out;
 
     clk_divn t1(clk,reset,clk_out);
        initial
          clk= 1'b0;
     always
        #5  clk=~clk; 
        initial
            begin
               #6 reset=1'b1;
               #6 reset=1'b0;
			   #6 reset=1'b1;
               #500 $finish;
            end
 
        initial
               $monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);
 
        initial
            begin
              $dumpfile("clkdiv3_tb.vcd");
              $dumpvars(0,clkdiv3_tb);
             end
    endmodule