data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/ALU.v:50: Operator ASSIGN expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                    : ... In instance ALU1\n            out = 24\'b0;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/ALU.v:91: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                    : ... In instance ALU1\n                    out<=24\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/ALU.v:93: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                    : ... In instance ALU1\n                    out<=24\'b0;\n                       ^~\n%Error: Exiting due to 3 warning(s)\n'
module ALU1(
    input enable,
    input clk,
    input [27:0] A,
    input [27:0] B,
    output reg [27:0] out,
    output reg z_flag,
    input [3:0] sel
    );

    parameter ADD = 4'b0001;
    parameter LSHIFT1 = 4'b0010;
    parameter RSHIFT1 = 4'b0011;
    parameter LSHIFT8 = 4'b0100;
    parameter DEAC = 4'b0101;
    parameter RESET = 4'b0110;
    parameter PASS_B = 4'b0111;
    parameter PASS_A = 4'b1000;
    parameter SUB = 4'b1001;
    parameter INCAC = 4'b1011;


    
    reg [1:0] state = 2'b0;
    
    initial 
        begin
            out = 24'b0;
            z_flag = 1'b0;
        end
        
    always @(posedge clk)
        if (enable==1'b1)
            begin
            state<=state+1;           
            end    
        
    
    always @(posedge clk)
    begin
        if (state==2'b11)
            begin
                case(sel)
                ADD:
                    out<=A+B;
                SUB:
                    begin
                    out<=A-B;
                    if (out==28'b0)
                        z_flag = 1'b1;
                    else
                        z_flag = 1'b0;
                     end
                PASS_A:
                    out<=A;
                PASS_B:
                    out<=B;
                INCAC:
                    out<=A+1;
                DEAC:
                    out<=A-1;
                LSHIFT1:
                    out<=A<<1;
                LSHIFT8:
                    out<=A<<2;   
                RSHIFT1:
                    out<=A>>1;
                RESET:
                    out<=24'b0;
                default:
                    out<=24'b0;
                    
                    
                endcase 
             end      
    end    
endmodule
module ALU1(
    input enable,
    input clk,
    input [27:0] A,
    input [27:0] B,
    output reg [27:0] out,
    output reg z_flag,
    input [3:0] sel
    );


    parameter ADD = 4'b0001;
    parameter LSHIFT1 = 4'b0010;
    parameter RSHIFT1 = 4'b0011;
    parameter LSHIFT8 = 4'b0100;
    parameter DEAC = 4'b0101;
    parameter RESET = 4'b0110;
    parameter PASS_B = 4'b0111;
    parameter PASS_A = 4'b1000;
    parameter SUB = 4'b1001;
    parameter INCAC = 4'b1011;


    
    reg [1:0] state = 2'b0;
    
    initial 
        begin
            out = 24'b0;
            z_flag = 1'b0;
        end
        
    always @(posedge clk)
        if (enable==1'b1)
            begin
            state<=state+1;           
            end    
        
    
    always @(posedge clk)
    begin
        if (state==2'b11)
            begin
                case(sel)
                ADD:
                    out<=A+B;
                SUB:
                    begin
                    out<=A-B;
                    if (out==28'b0)
                        z_flag = 1'b1;
                    else
                        z_flag = 1'b0;
                     end
                PASS_A:
                    out<=A;
                PASS_B:
                    out<=B;
                INCAC:
                    out<=A+1;
                DEAC:
                    out<=A-1;
                LSHIFT1:
                    out<=A<<1;
                LSHIFT8:
                    out<=A<<2;   
                RSHIFT1:
                    out<=A>>1;
                RESET:
                    out<=24'b0;
                default:
                    out<=24'b0;
                    
                    
                endcase 
             end      
    end    
endmodule