data/full_repos/permissive/419538859/lab1_1/lab1_1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab1_1/lab1_1.v:8: Signal definition not found, creating implicitly: \'clk_work\'\nfreq_div#(20) M1 (clk, reset, clk_work); \n                              ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lab01_1 (clk, reset, shift_out);
input clk, reset;
output	[7:0]shift_out;
reg	[7:0]	shift_out;
always@ (posedge clk or posedge reset)
begin
if(reset)
shift_out= 8'b1100_0000;
else
shift_out= {shift_out[0], shift_out[7:1]};
end
endmodule
module lab01_1 (clk, reset, shift_out);

input clk, reset;
output	[7:0]shift_out;
reg	[7:0]	shift_out;
always@ (posedge clk or posedge reset)
begin
if(reset)
shift_out= 8'b1100_0000;
else
shift_out= {shift_out[0], shift_out[7:1]};
end
endmodule