data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = clk + 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 data = 10\'d3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:38: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:39: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();
  reg clk = 1'd1;
  reg load = 1'd0;
  reg [9:0] data;
  wire tc;

  localparam ITERATIONS = 10000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #1;
    #10 data = 10'd3;
    load = 1'b1;
    #10 load = 1'b0;
    #100;
  end

  top_module uut (
      .clk(clk),
      .load(load),
      .data(data),
      .tc(tc)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg clk = 1'd1;
  reg load = 1'd0;
  reg [9:0] data;
  wire tc;

  localparam ITERATIONS = 10000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #1;
    #10 data = 10'd3;
    load = 1'b1;
    #10 load = 1'b0;
    #100;
  end

  top_module uut (
      .clk(clk),
      .load(load),
      .data(data),
      .tc(tc)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule