data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:100: Little bit endian vector: MSB < LSB of bit range: 0:15\n      wire [0:LUT_DEPTH-1]            lut_lookup_hit;\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:123: Little bit endian vector: MSB < LSB of bit range: 0:15\n      wire [0:LUT_DEPTH-1]            lut_learn_hit;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_lite_output_port_lookup_v1_0_0/hdl/mac_cam_lut.v:139: Operator ASSIGNDLY expects 56 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 55 bits.\n                                                                                                                                                                     : ... In instance mac_cam_lut\n    lut[i] <= {(NUM_OUTPUT_QUEUES+48-1){1\'b0}};\n           ^~\n%Error: Exiting due to 3 warning(s)\n'
module mac_cam_lut
 #(
   parameter NUM_OUTPUT_QUEUES = 8,
   parameter LUT_DEPTH_BITS    = 4,
   parameter LUT_DEPTH         = 2**LUT_DEPTH_BITS,
   parameter DEFAULT_MISS_OUTPUT_PORTS = 8'h55
 )
 (

   input  [47:0]                       dst_mac,
   input  [47:0]                       src_mac,
   input  [NUM_OUTPUT_QUEUES-1:0]      src_port,
   input                               lookup_req,
   output reg [NUM_OUTPUT_QUEUES-1:0]  dst_ports,
   

   output reg                          lookup_done,
   output reg                          lut_miss,
   output reg                          lut_hit,
   

   input                               clk,
   input                               reset
 );
 
  function integer log2;
    input integer number;
    begin
      log2=0;
      while(2**log2<number) begin
      log2=log2+1;
      end
    end
  endfunction
 

 

  
  genvar i;
   
  reg [NUM_OUTPUT_QUEUES+48-1:0]    lut [0:LUT_DEPTH-1];
  reg [LUT_DEPTH_BITS-1:0]		    lut_wr_addr;
  

  
      wire [NUM_OUTPUT_QUEUES-1:0]    rd_oq[0:LUT_DEPTH-1];
      wire [0:LUT_DEPTH-1]            lut_lookup_hit;

  generate

    for (i=0; i<LUT_DEPTH; i=i+1)
	begin: LUT_LOOKUP
	  
  
	  if (i == 0) begin: _0
	    assign rd_oq[i][NUM_OUTPUT_QUEUES-1:0] = (lut[i][47:0] == dst_mac) ? lut[i][NUM_OUTPUT_QUEUES+48-1:48] 
		                                                       : {(NUM_OUTPUT_QUEUES){1'b0}};
		assign lut_lookup_hit[i]   = (lut[i][47:0] == dst_mac) ? 1                                 
		                                                       : 0;
      end
	  else begin: _N
	    assign rd_oq[i][NUM_OUTPUT_QUEUES-1:0] = (lut[i][47:0] == dst_mac) ? lut[i][NUM_OUTPUT_QUEUES+48-1:48] 
		                                                       : rd_oq[i-1][NUM_OUTPUT_QUEUES-1:0];
		assign lut_lookup_hit[i]   = (lut[i][47:0] == dst_mac) ? 1                                 
		                                                       : lut_lookup_hit[i-1];
	  end
	end
	

      wire [0:LUT_DEPTH-1]            lut_learn_hit;
	for (i=0; i<LUT_DEPTH; i=i+1)
	begin: LUT_LEARN

	  
	  if (i == 0) begin: _0
		assign lut_learn_hit[i]     = (lut[i][47:0] == src_mac) ? 1      
		                                                        : 0;
      end
	  else begin: _N
		assign lut_learn_hit[i]     = (lut[i][47:0] == src_mac) ? 1      
		                                                        : lut_learn_hit[i-1];
	  end
	  
	  always @ (posedge clk) begin: _A
	    if (reset)
		  lut[i] <= {(NUM_OUTPUT_QUEUES+48-1){1'b0}};
		else if (lookup_req) begin
		  if ((lut[i][47:0] == src_mac) ||
		      (~lut_learn_hit[LUT_DEPTH-1] && (lut_wr_addr == i)))
	        lut[i] <= {src_port, src_mac};
		end
	  end
	end
  endgenerate
  
  always @ (posedge clk) begin
    if(reset) begin
      lut_hit  <= 0;
	  lut_miss <= 0;
	  
	  lookup_done <= 0;
	  dst_ports   <= {NUM_OUTPUT_QUEUES{1'b0}};
	  
	  lut_wr_addr <= {LUT_DEPTH_BITS{1'b0}};
	end
	else begin
	  lut_hit     <= 0;
	  lut_miss    <= 0;
	  lookup_done <= 0;
	  
	  if (lookup_req) begin
	    lut_hit  <= lut_lookup_hit[LUT_DEPTH-1];
		lut_miss <= ~lut_lookup_hit[LUT_DEPTH-1];
		

        dst_ports <= (lut_lookup_hit[LUT_DEPTH-1]) ? (rd_oq[LUT_DEPTH-1][NUM_OUTPUT_QUEUES-1:0] & ~src_port)
                                                   : (DEFAULT_MISS_OUTPUT_PORTS     & ~src_port);
	    lookup_done <= 1;
		
		if (~lut_learn_hit[LUT_DEPTH-1])
		  lut_wr_addr <= lut_wr_addr + 1;
	  end
	end
  end
  
endmodule
module mac_cam_lut
 #(
   parameter NUM_OUTPUT_QUEUES = 8,
   parameter LUT_DEPTH_BITS    = 4,
   parameter LUT_DEPTH         = 2**LUT_DEPTH_BITS,
   parameter DEFAULT_MISS_OUTPUT_PORTS = 8'h55
 )
 (

   input  [47:0]                       dst_mac,
   input  [47:0]                       src_mac,
   input  [NUM_OUTPUT_QUEUES-1:0]      src_port,
   input                               lookup_req,
   output reg [NUM_OUTPUT_QUEUES-1:0]  dst_ports,
   

   output reg                          lookup_done,
   output reg                          lut_miss,
   output reg                          lut_hit,
   

   input                               clk,
   input                               reset
 );

 
  function integer log2;
    input integer number;
    begin
      log2=0;
      while(2**log2<number) begin
      log2=log2+1;
      end
    end
  endfunction
 

 

  
  genvar i;
   
  reg [NUM_OUTPUT_QUEUES+48-1:0]    lut [0:LUT_DEPTH-1];
  reg [LUT_DEPTH_BITS-1:0]		    lut_wr_addr;
  

  
      wire [NUM_OUTPUT_QUEUES-1:0]    rd_oq[0:LUT_DEPTH-1];
      wire [0:LUT_DEPTH-1]            lut_lookup_hit;

  generate

    for (i=0; i<LUT_DEPTH; i=i+1)
	begin: LUT_LOOKUP
	  
  
	  if (i == 0) begin: _0
	    assign rd_oq[i][NUM_OUTPUT_QUEUES-1:0] = (lut[i][47:0] == dst_mac) ? lut[i][NUM_OUTPUT_QUEUES+48-1:48] 
		                                                       : {(NUM_OUTPUT_QUEUES){1'b0}};
		assign lut_lookup_hit[i]   = (lut[i][47:0] == dst_mac) ? 1                                 
		                                                       : 0;
      end
	  else begin: _N
	    assign rd_oq[i][NUM_OUTPUT_QUEUES-1:0] = (lut[i][47:0] == dst_mac) ? lut[i][NUM_OUTPUT_QUEUES+48-1:48] 
		                                                       : rd_oq[i-1][NUM_OUTPUT_QUEUES-1:0];
		assign lut_lookup_hit[i]   = (lut[i][47:0] == dst_mac) ? 1                                 
		                                                       : lut_lookup_hit[i-1];
	  end
	end
	

      wire [0:LUT_DEPTH-1]            lut_learn_hit;
	for (i=0; i<LUT_DEPTH; i=i+1)
	begin: LUT_LEARN

	  
	  if (i == 0) begin: _0
		assign lut_learn_hit[i]     = (lut[i][47:0] == src_mac) ? 1      
		                                                        : 0;
      end
	  else begin: _N
		assign lut_learn_hit[i]     = (lut[i][47:0] == src_mac) ? 1      
		                                                        : lut_learn_hit[i-1];
	  end
	  
	  always @ (posedge clk) begin: _A
	    if (reset)
		  lut[i] <= {(NUM_OUTPUT_QUEUES+48-1){1'b0}};
		else if (lookup_req) begin
		  if ((lut[i][47:0] == src_mac) ||
		      (~lut_learn_hit[LUT_DEPTH-1] && (lut_wr_addr == i)))
	        lut[i] <= {src_port, src_mac};
		end
	  end
	end
  endgenerate
  
  always @ (posedge clk) begin
    if(reset) begin
      lut_hit  <= 0;
	  lut_miss <= 0;
	  
	  lookup_done <= 0;
	  dst_ports   <= {NUM_OUTPUT_QUEUES{1'b0}};
	  
	  lut_wr_addr <= {LUT_DEPTH_BITS{1'b0}};
	end
	else begin
	  lut_hit     <= 0;
	  lut_miss    <= 0;
	  lookup_done <= 0;
	  
	  if (lookup_req) begin
	    lut_hit  <= lut_lookup_hit[LUT_DEPTH-1];
		lut_miss <= ~lut_lookup_hit[LUT_DEPTH-1];
		

        dst_ports <= (lut_lookup_hit[LUT_DEPTH-1]) ? (rd_oq[LUT_DEPTH-1][NUM_OUTPUT_QUEUES-1:0] & ~src_port)
                                                   : (DEFAULT_MISS_OUTPUT_PORTS     & ~src_port);
	    lookup_done <= 1;
		
		if (~lut_learn_hit[LUT_DEPTH-1])
		  lut_wr_addr <= lut_wr_addr + 1;
	  end
	end
  end
  
endmodule