data/full_repos/permissive/463439324/keygen/inverse4591.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/463439324/keygen/inverse4591.v:57: Signal definition not found, creating implicitly: \'SQUARE_FIN\'\n                                                                               : ... Suggested alternative: \'SQUARE\'\n assign SQUARE_FIN = (state==SQUARE)&&(cnt==3);\n        ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/463439324/keygen/inverse4591.v:58: Signal definition not found, creating implicitly: \'MULT_FIN\'\n assign MULT_FIN = (state==MULT)&&(cnt==3);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/inverse4591.v:55: Cannot find file containing module: \'modmul4591S\'\n modmul4591S mod_0(.Clk(Clk), .Reset(Reset), .In({{28-P_WIDTH*2{mul_mod_in[P_WIDTH*2-1]}},mul_mod_in}), .Out(mul_mod_out));\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/modmul4591S\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/modmul4591S.v\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/modmul4591S.sv\n             modmul4591S\n             modmul4591S.v\n             modmul4591S.sv\n             obj_dir/modmul4591S\n             obj_dir/modmul4591S.v\n             obj_dir/modmul4591S.sv\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/inverse4591.v:119: Operator COND expects 26 bits on the Conditional True, but Conditional True\'s VARREF \'mul_mod_out\' generates 13 bits.\n                                                                             : ... In instance inverse4591\n    mul_mod_in <= mul_mod_out*((state==SQUARE) ? mul_mod_out : In);\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/inverse4591.v:119: Operator COND expects 26 bits on the Conditional False, but Conditional False\'s VARREF \'In\' generates 13 bits.\n                                                                             : ... In instance inverse4591\n    mul_mod_in <= mul_mod_out*((state==SQUARE) ? mul_mod_out : In);\n                                               ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module inverse4591(Clk, Reset, In, En, Out, Valid);

	parameter P_WIDTH = 13;
	input							Clk;
	input							Reset;
	input signed		[P_WIDTH-1 : 0]		In;
	input							En;
	output signed 		[P_WIDTH-1 : 0]		Out;
	output							Valid;

	parameter IDLE = 0;
	parameter SQUARE = 1;
	parameter MULT = 2;
	
	reg [12:0] r_4591 = 13'd4589;
	reg [1:0] state;
	reg [1:0] next_state;
	reg [3:0] ptr;
	wire [3:0] ptr_minus;
	reg [3:0] next_ptr;
	reg [3:0] cnt;
	reg [3:0] next_cnt;
	reg signed  [P_WIDTH*2-1:0] mul_mod_in;
	wire signed [P_WIDTH-1:0]   mul_mod_out;

	modmul4591S mod_0(.Clk(Clk), .Reset(Reset), .In({{28-P_WIDTH*2{mul_mod_in[P_WIDTH*2-1]}},mul_mod_in}), .Out(mul_mod_out));
	
	assign SQUARE_FIN = (state==SQUARE)&&(cnt==3);
	assign MULT_FIN = (state==MULT)&&(cnt==3);
	assign ptr_minus = ptr-1;

	assign Valid = (ptr==0)&&(state==0);

	assign Out = (Valid) ? mul_mod_out : 0;


	always @(*) begin
		if(SQUARE_FIN||MULT_FIN)
			next_cnt = 0;
		else if(state==SQUARE||state==MULT)
			next_cnt = cnt + 1;
		else
			next_cnt = 0;
	end
	always @(posedge Clk or posedge Reset) begin
		if(Reset)
			cnt <= 0;
		else
			cnt <= next_cnt;
	end


	always @(posedge Clk or posedge Reset) begin
		if(Reset)
			state <= 0;
		else
			state <= next_state;
	end
	always @(*) begin
		case(state)
			IDLE : next_state = (En) ? SQUARE : IDLE;
			SQUARE : next_state = (SQUARE_FIN && r_4591[ptr_minus]) ? MULT : SQUARE;
			MULT : next_state = (ptr==0 && MULT_FIN) ? IDLE : (MULT_FIN) ? SQUARE : MULT;
			default : next_state = state;
		endcase
	end


	always @(posedge Clk or posedge Reset) begin
		if(Reset) begin
			ptr <= 12;
		end else begin
			ptr <= next_ptr;
		end
	end

	always @(*) begin
		next_ptr = (SQUARE_FIN) ? ptr_minus : ptr;
	end

	always @(posedge Clk or posedge Reset) begin
		if(Reset) begin
			mul_mod_in <= 0;
		end else begin
			if(state==IDLE)
				mul_mod_in <= mul_mod_in;
			else if(ptr==12)
				mul_mod_in <= In*In;
			else if(cnt==0)
				mul_mod_in <= mul_mod_out*((state==SQUARE) ? mul_mod_out : In);
			else
				mul_mod_in <= mul_mod_in;
		end
	end

endmodule
module inverse4591(Clk, Reset, In, En, Out, Valid);


	parameter P_WIDTH = 13;
	input							Clk;
	input							Reset;
	input signed		[P_WIDTH-1 : 0]		In;
	input							En;
	output signed 		[P_WIDTH-1 : 0]		Out;
	output							Valid;

	parameter IDLE = 0;
	parameter SQUARE = 1;
	parameter MULT = 2;
	
	reg [12:0] r_4591 = 13'd4589;
	reg [1:0] state;
	reg [1:0] next_state;
	reg [3:0] ptr;
	wire [3:0] ptr_minus;
	reg [3:0] next_ptr;
	reg [3:0] cnt;
	reg [3:0] next_cnt;
	reg signed  [P_WIDTH*2-1:0] mul_mod_in;
	wire signed [P_WIDTH-1:0]   mul_mod_out;

	modmul4591S mod_0(.Clk(Clk), .Reset(Reset), .In({{28-P_WIDTH*2{mul_mod_in[P_WIDTH*2-1]}},mul_mod_in}), .Out(mul_mod_out));
	
	assign SQUARE_FIN = (state==SQUARE)&&(cnt==3);
	assign MULT_FIN = (state==MULT)&&(cnt==3);
	assign ptr_minus = ptr-1;

	assign Valid = (ptr==0)&&(state==0);

	assign Out = (Valid) ? mul_mod_out : 0;


	always @(*) begin
		if(SQUARE_FIN||MULT_FIN)
			next_cnt = 0;
		else if(state==SQUARE||state==MULT)
			next_cnt = cnt + 1;
		else
			next_cnt = 0;
	end
	always @(posedge Clk or posedge Reset) begin
		if(Reset)
			cnt <= 0;
		else
			cnt <= next_cnt;
	end


	always @(posedge Clk or posedge Reset) begin
		if(Reset)
			state <= 0;
		else
			state <= next_state;
	end
	always @(*) begin
		case(state)
			IDLE : next_state = (En) ? SQUARE : IDLE;
			SQUARE : next_state = (SQUARE_FIN && r_4591[ptr_minus]) ? MULT : SQUARE;
			MULT : next_state = (ptr==0 && MULT_FIN) ? IDLE : (MULT_FIN) ? SQUARE : MULT;
			default : next_state = state;
		endcase
	end


	always @(posedge Clk or posedge Reset) begin
		if(Reset) begin
			ptr <= 12;
		end else begin
			ptr <= next_ptr;
		end
	end

	always @(*) begin
		next_ptr = (SQUARE_FIN) ? ptr_minus : ptr;
	end

	always @(posedge Clk or posedge Reset) begin
		if(Reset) begin
			mul_mod_in <= 0;
		end else begin
			if(state==IDLE)
				mul_mod_in <= mul_mod_in;
			else if(ptr==12)
				mul_mod_in <= In*In;
			else if(cnt==0)
				mul_mod_in <= mul_mod_out*((state==SQUARE) ? mul_mod_out : In);
			else
				mul_mod_in <= mul_mod_in;
		end
	end

endmodule