data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:47: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                                : ... In instance InstructionRegControl\n  reg [15:0] currAddr = 8\'b00000000;\n                        ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:77: Cannot find file containing module: \'InstructionReg\'\n  InstructionReg instrReg(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InstructionReg\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InstructionReg.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InstructionReg.sv\n             InstructionReg\n             InstructionReg.v\n             InstructionReg.sv\n             obj_dir/InstructionReg\n             obj_dir/InstructionReg.v\n             obj_dir/InstructionReg.sv\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:84: Cannot find file containing module: \'SevSeg\'\n  SevSeg sevSeg(\n  ^~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:92: Cannot find file containing module: \'Debouncer\'\n  Debouncer dbL(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:98: Cannot find file containing module: \'Debouncer\'\n  Debouncer dbC(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionRegControl.v:104: Cannot find file containing module: \'Debouncer\'\n  Debouncer dbR(\n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module InstructionRegControl(
    input clk,
    input [15:0] sw,
    input btnL,
    input btnC,
    input btnR,
    
    output [6:0] seg,
    output [3:0] an,
    output [15:0] led,
    output dp
  );
  

  wire button_left;
  wire button_center;
  wire button_right;
  

  reg buttonLPressed = 1'b0;
  reg buttonCPressed = 1'b0;
  reg buttonRPressed = 1'b0;
  

  reg [15:0] currAddr = 8'b00000000;
  
  always @ (posedge clk) begin
    

    if(button_left == 1'b0)
      buttonLPressed <= 1'b0;
    if(button_center == 1'b0)
      buttonCPressed <= 1'b0;
    if(button_right == 1'b0)
      buttonRPressed <= 1'b0;
    

    if(buttonLPressed == 1'b0 & button_left == 1'b1) begin
      currAddr <= currAddr - 1;
      buttonLPressed <= 1'b1;
    end
    

    else if(buttonCPressed == 1'b0 & button_center == 1'b1) begin
      buttonCPressed <= 1'b1;
    end
    

    else if(buttonRPressed == 1'b0 & button_right == 1'b1) begin
      currAddr <= currAddr + 1;
      buttonRPressed <= 1'b1;
    end
  end
  
  InstructionReg instrReg(
    .clk(buttonCPressed),
    .address(currAddr[7:0]),
    .data_in(sw[15:0]),
    .data_out(led[15:0])
  );

  SevSeg sevSeg(
    .clk(clk),
    .valIn(currAddr[15:0]),
    .segs(seg[6:0]),
    .anodes(an[3:0]),
    .dp(dp)
  );
  
  Debouncer dbL(
    .clock(clk),
    .in(btnL),
    .out(button_left)  
  );
  
  Debouncer dbC(
    .clock(clk),
    .in(btnC),
    .out(button_center)  
  );
  
  Debouncer dbR(
    .clock(clk),
    .in(btnR),
    .out(button_right)  
  );
  
endmodule
module InstructionRegControl(
    input clk,
    input [15:0] sw,
    input btnL,
    input btnC,
    input btnR,
    
    output [6:0] seg,
    output [3:0] an,
    output [15:0] led,
    output dp
  );

  

  wire button_left;
  wire button_center;
  wire button_right;
  

  reg buttonLPressed = 1'b0;
  reg buttonCPressed = 1'b0;
  reg buttonRPressed = 1'b0;
  

  reg [15:0] currAddr = 8'b00000000;
  
  always @ (posedge clk) begin
    

    if(button_left == 1'b0)
      buttonLPressed <= 1'b0;
    if(button_center == 1'b0)
      buttonCPressed <= 1'b0;
    if(button_right == 1'b0)
      buttonRPressed <= 1'b0;
    

    if(buttonLPressed == 1'b0 & button_left == 1'b1) begin
      currAddr <= currAddr - 1;
      buttonLPressed <= 1'b1;
    end
    

    else if(buttonCPressed == 1'b0 & button_center == 1'b1) begin
      buttonCPressed <= 1'b1;
    end
    

    else if(buttonRPressed == 1'b0 & button_right == 1'b1) begin
      currAddr <= currAddr + 1;
      buttonRPressed <= 1'b1;
    end
  end
  
  InstructionReg instrReg(
    .clk(buttonCPressed),
    .address(currAddr[7:0]),
    .data_in(sw[15:0]),
    .data_out(led[15:0])
  );

  SevSeg sevSeg(
    .clk(clk),
    .valIn(currAddr[15:0]),
    .segs(seg[6:0]),
    .anodes(an[3:0]),
    .dp(dp)
  );
  
  Debouncer dbL(
    .clock(clk),
    .in(btnL),
    .out(button_left)  
  );
  
  Debouncer dbC(
    .clock(clk),
    .in(btnC),
    .out(button_center)  
  );
  
  Debouncer dbR(
    .clock(clk),
    .in(btnR),
    .out(button_right)  
  );
  
endmodule