data/full_repos/permissive/519551680/sim/tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/519551680/sim/tb.sv:5: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519551680/sim/tb.sv:14: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/519551680/sim/tb.sv:7: Cannot find file containing module: \'int_clk_div\'\n  int_clk_div dut(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519551680/sim,data/full_repos/permissive/519551680/int_clk_div\n             data/full_repos/permissive/519551680/sim,data/full_repos/permissive/519551680/int_clk_div.v\n             data/full_repos/permissive/519551680/sim,data/full_repos/permissive/519551680/int_clk_div.sv\n             int_clk_div\n             int_clk_div.v\n             int_clk_div.sv\n             obj_dir/int_clk_div\n             obj_dir/int_clk_div.v\n             obj_dir/int_clk_div.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb ();
  reg clk = 0;
  wire out;
  
  always #10 clk <= ~clk;

  int_clk_div dut(
    .clk(clk),
    .out(out)
  );

  initial begin
    $display("=== SIMULATION STARTED ===");
    #1000;
    $display("=== SIMULATION FINISHED ===");
    $finish;
  end
endmodule
module tb ();

  reg clk = 0;
  wire out;
  
  always #10 clk <= ~clk;

  int_clk_div dut(
    .clk(clk),
    .out(out)
  );

  initial begin
    $display("=== SIMULATION STARTED ===");
    #1000;
    $display("=== SIMULATION FINISHED ===");
    $finish;
  end
endmodule