data/full_repos/permissive/497819211/04/CPU_tb.v
1: b'%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:1: Cannot find include file: Mux16.v\n`include "Mux16.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v.v\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v.sv\n             Mux16.v\n             Mux16.v.v\n             Mux16.v.sv\n             obj_dir/Mux16.v\n             obj_dir/Mux16.v.v\n             obj_dir/Mux16.v.sv\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:2: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:3: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:4: Cannot find include file: PC.v\n`include "PC.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:5: Cannot find include file: Not16.v\n`include "Not16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:6: Cannot find include file: And16.v\n`include "And16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:7: Cannot find include file: Add16.v\n`include "Add16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:8: Cannot find include file: Or8Way.v\n`include "Or8Way.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:9: Cannot find include file: And.v\n`include "And.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:10: Cannot find include file: Not.v\n`include "Not.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:11: Cannot find include file: Or.v\n`include "Or.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:13: Cannot find include file: CPU.v\n`include "CPU.v" \n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497819211/04/CPU_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497819211/04/CPU_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n     #1 $fwrite(file, "|%6d|%6d|%16b|  %1b  |%6d|  %1b   |%6d|%6d|\\n",t,inM,instruction,reset,outM,writeM,addressM[14:0],pc);\n     ^\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:47: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("CPU_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/CPU_tb.v:48: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, CPU_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 14 error(s), 2 warning(s)\n'
module CPU_tb();

	integer file;
	reg clk = 1;	
	reg [15:0] inM=0;
	reg [15:0] instruction=0;
	reg reset=0;
	wire signed [15:0] outM;
	wire writeM;
	wire [15:0] addressM;
	wire [15:0] pc;
    reg[9:0] t = 10'b0;

	CPU CPU(
		.clk(clk),
		.inM(inM),
		.instruction(instruction),
		.reset(reset),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);

	 
	always #1 clk = ~clk;

	task display;
    	#1 $fwrite(file, "|%6d|%6d|%16b|  %1b  |%6d|  %1b   |%6d|%6d|\n",t,inM,instruction,reset,outM,writeM,addressM[14:0],pc);
  	endtask
  	
  	initial begin
  		$dumpfile("CPU_tb.vcd");
  		$dumpvars(0, CPU_tb);
		file = $fopen("CPU.out","w");
    	$fwrite(file, "| time |  inM |  instruction   |reset| outM |writeM|addres|  pc  |\n");
		

instruction = 16'b0011000000111001;
display();
t=1;display();

instruction = 16'b1110110000010000;
display();
t=2;display();

instruction = 16'b0101101110100000;
display();
t=3;display();

instruction = 16'b1110000111110000;
inM = 11111;
display();
t=4;display();

instruction = 16'b0000001111101011;
display();
t=5;display();

instruction = 16'b1110001100001000;
display();
t=6;display();

instruction = 16'b0000001111101100;
display();
t=7;display();

instruction = 16'b1110001110011000;
display();
t=8;display();

instruction = 16'b0000001111101000;
display();
t=9;display();

instruction = 16'b1111010011110000;
display();
t=10;display();

instruction = 16'b0000000000001110;
display();
t=11;display();

instruction = 16'b1110001100000100;
display();
t=12;display();

instruction = 16'b0000001111100111;
display();
t=13;display();

instruction = 16'b1111110111100000;
display();
t=14;display();

instruction = 16'b1110001100101000;
display();
t=15;display();

instruction = 16'b0000000000010101;
display();
t=16;display();

instruction = 16'b1110011111000010;
display();
t=17;display();

instruction = 16'b0000000000000010;
display();
t=18;display();

instruction = 16'b1110000010111000;
display();
t=19;display();




















































































$finish;
end
endmodule
module CPU_tb();


	integer file;
	reg clk = 1;	
	reg [15:0] inM=0;
	reg [15:0] instruction=0;
	reg reset=0;
	wire signed [15:0] outM;
	wire writeM;
	wire [15:0] addressM;
	wire [15:0] pc;
    reg[9:0] t = 10'b0;

	CPU CPU(
		.clk(clk),
		.inM(inM),
		.instruction(instruction),
		.reset(reset),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);

	 
	always #1 clk = ~clk;

	task display;
    	#1 $fwrite(file, "|%6d|%6d|%16b|  %1b  |%6d|  %1b   |%6d|%6d|\n",t,inM,instruction,reset,outM,writeM,addressM[14:0],pc);
  	endtask
  	
  	initial begin
  		$dumpfile("CPU_tb.vcd");
  		$dumpvars(0, CPU_tb);
		file = $fopen("CPU.out","w");
    	$fwrite(file, "| time |  inM |  instruction   |reset| outM |writeM|addres|  pc  |\n");
		

instruction = 16'b0011000000111001;
display();
t=1;display();

instruction = 16'b1110110000010000;
display();
t=2;display();

instruction = 16'b0101101110100000;
display();
t=3;display();

instruction = 16'b1110000111110000;
inM = 11111;
display();
t=4;display();

instruction = 16'b0000001111101011;
display();
t=5;display();

instruction = 16'b1110001100001000;
display();
t=6;display();

instruction = 16'b0000001111101100;
display();
t=7;display();

instruction = 16'b1110001110011000;
display();
t=8;display();

instruction = 16'b0000001111101000;
display();
t=9;display();

instruction = 16'b1111010011110000;
display();
t=10;display();

instruction = 16'b0000000000001110;
display();
t=11;display();

instruction = 16'b1110001100000100;
display();
t=12;display();

instruction = 16'b0000001111100111;
display();
t=13;display();

instruction = 16'b1111110111100000;
display();
t=14;display();

instruction = 16'b1110001100101000;
display();
t=15;display();

instruction = 16'b0000000000010101;
display();
t=16;display();

instruction = 16'b1110011111000010;
display();
t=17;display();

instruction = 16'b0000000000000010;
display();
t=18;display();

instruction = 16'b1110000010111000;
display();
t=19;display();




















































































$finish;
end
endmodule