data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk <=  ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:40: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:42: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:45: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:56: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:58: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:63: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:74: syntax error, unexpected \'@\'\n  @(posedge rst_n);\n  ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:77: syntax error, unexpected \'@\'\n  repeat (10) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:80: Unsupported or unknown PLI call: $urandom\n  single_rq($urandom, $urandom%5) ; \n            ^~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:80: Unsupported or unknown PLI call: $urandom\n  single_rq($urandom, $urandom%5) ; \n                      ^~~~~~~~\n%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/DN/complex_multiplier_test.v:82: syntax error, unexpected \'@\'\n  repeat (50) @(posedge clk);\n              ^\n%Error: Exiting due to 11 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module complex_multiplier_test ;
reg                     clk       ;
reg                     rst_n     ;

reg                     op_val    ;
wire                    op_rdy    ;
reg   [2 * 2 * 8 - 1:0] op_data   ;

wire                    res_val   ;
reg                     res_rdy   ;
wire  [2 * 18    - 1:0] res_data  ;


reg        [2 * 2 * 8 - 1:0] operands_fifo [16   -1      :0];
reg        [3            :0] wr_ptr; 
reg        [3            :0] rd_ptr; 
reg signed [8         - 1:0] x1, y1, x2, y2 ;
reg signed [18        - 1:0] re;
reg signed [18        - 1:0] im;

initial begin
  clk <=  1'b0; 
  forever #5 clk <=  ~clk;
end

initial begin
  rst_n <=  1'b1;  
  @(posedge clk);
  rst_n <=  1'b0;
  @(posedge clk);
  @(posedge clk);
  rst_n <=  1'b1;  
  @(posedge clk);
end

task single_rq;
input [2 * 2 * 8  -1:0]  data_p     ;
input [10         -1:0]  break_p    ;
begin
  op_val      <=  1'b1;  
  op_data     <=  data_p;  
  operands_fifo[wr_ptr] <=  data_p;
  wr_ptr      <=  wr_ptr + 1; 
  @(posedge clk);
  while (~op_rdy)
    @(posedge clk);
  if (break_p != 'd0) begin
    op_val    <=  1'b0;  
    op_data   <=  'bx;  
    repeat (break_p)
      @(posedge clk);
  end
end
endtask

initial begin
  res_rdy    <=  1'b1;
  wr_ptr     <=  4'b0; 
  rd_ptr     <=  4'b0; 
  op_val     <=  1'b0;  
  op_data    <=  'bx;  
  @(posedge rst_n);
  

  repeat (10) @(posedge clk);
  single_rq({8'd2, 8'd3, 8'd4, 8'd2}, 10) ; 
  repeat (1000) 
  single_rq($urandom, $urandom%5) ; 
    
  repeat (50) @(posedge clk);
  $display ("%M INFO: End of stimulus.");
  $stop;
end

always @(posedge clk)
if (res_val & res_rdy) begin
  {x1, y1, x2, y2} = operands_fifo[rd_ptr];
  re = x1 * x2 - y1 * y2;
  im = x1 * y2 + y1 * x2;
  rd_ptr <=  rd_ptr + 1;
  if (res_data !== {re, im}) begin
    $display("%M %0t ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
    x1, y1, x2, y2, res_data[18+:18], res_data[0+:18], re, im);
    $stop;
  end
  else
    $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di)", $time,
      x1, y1, x2, y2, re, im);
end

vld_rdy_checker #(
.DATA_WIDTH       (2 * 2 * 8)
) i_src (     
.clk              (clk      ),
.rst_n            (rst_n    ),
.valid            (op_val   ),               
.ready            (op_rdy   ),               
.data             (op_data  )
);
vld_rdy_checker #(
.DATA_WIDTH       (2 * 18   )
) i_dst (     
.clk              (clk      ),
.rst_n            (rst_n    ),
.valid            (res_val  ),               
.ready            (res_rdy  ),               
.data             (res_data )
);

complex_multiplier i_complex_multiplier (
.clk       (clk     ),
.rst_n     (rst_n   ),
.op_val    (op_val  ),
.op_rdy    (op_rdy  ),
.op_data   (op_data ),
.res_val   (res_val ),
.res_rdy   (res_rdy ),
.res_data  (res_data)
);

endmodule
module complex_multiplier_test ;

reg                     clk       ;
reg                     rst_n     ;

reg                     op_val    ;
wire                    op_rdy    ;
reg   [2 * 2 * 8 - 1:0] op_data   ;

wire                    res_val   ;
reg                     res_rdy   ;
wire  [2 * 18    - 1:0] res_data  ;


reg        [2 * 2 * 8 - 1:0] operands_fifo [16   -1      :0];
reg        [3            :0] wr_ptr; 
reg        [3            :0] rd_ptr; 
reg signed [8         - 1:0] x1, y1, x2, y2 ;
reg signed [18        - 1:0] re;
reg signed [18        - 1:0] im;

initial begin
  clk <=  1'b0; 
  forever #5 clk <=  ~clk;
end

initial begin
  rst_n <=  1'b1;  
  @(posedge clk);
  rst_n <=  1'b0;
  @(posedge clk);
  @(posedge clk);
  rst_n <=  1'b1;  
  @(posedge clk);
end

task single_rq;
input [2 * 2 * 8  -1:0]  data_p     ;
input [10         -1:0]  break_p    ;
begin
  op_val      <=  1'b1;  
  op_data     <=  data_p;  
  operands_fifo[wr_ptr] <=  data_p;
  wr_ptr      <=  wr_ptr + 1; 
  @(posedge clk);
  while (~op_rdy)
    @(posedge clk);
  if (break_p != 'd0) begin
    op_val    <=  1'b0;  
    op_data   <=  'bx;  
    repeat (break_p)
      @(posedge clk);
  end
end
endtask

initial begin
  res_rdy    <=  1'b1;
  wr_ptr     <=  4'b0; 
  rd_ptr     <=  4'b0; 
  op_val     <=  1'b0;  
  op_data    <=  'bx;  
  @(posedge rst_n);
  

  repeat (10) @(posedge clk);
  single_rq({8'd2, 8'd3, 8'd4, 8'd2}, 10) ; 
  repeat (1000) 
  single_rq($urandom, $urandom%5) ; 
    
  repeat (50) @(posedge clk);
  $display ("%M INFO: End of stimulus.");
  $stop;
end

always @(posedge clk)
if (res_val & res_rdy) begin
  {x1, y1, x2, y2} = operands_fifo[rd_ptr];
  re = x1 * x2 - y1 * y2;
  im = x1 * y2 + y1 * x2;
  rd_ptr <=  rd_ptr + 1;
  if (res_data !== {re, im}) begin
    $display("%M %0t ERROR: (%0d + %0di) * (%0d + %0di) = (%0d + %0di), expected (%0d + %0di)", $time,
    x1, y1, x2, y2, res_data[18+:18], res_data[0+:18], re, im);
    $stop;
  end
  else
    $display("%M %0t GOOD: (%0d + %0di) * (%0d + %0di) = (%0d + %0di)", $time,
      x1, y1, x2, y2, re, im);
end

vld_rdy_checker #(
.DATA_WIDTH       (2 * 2 * 8)
) i_src (     
.clk              (clk      ),
.rst_n            (rst_n    ),
.valid            (op_val   ),               
.ready            (op_rdy   ),               
.data             (op_data  )
);
vld_rdy_checker #(
.DATA_WIDTH       (2 * 18   )
) i_dst (     
.clk              (clk      ),
.rst_n            (rst_n    ),
.valid            (res_val  ),               
.ready            (res_rdy  ),               
.data             (res_data )
);

complex_multiplier i_complex_multiplier (
.clk       (clk     ),
.rst_n     (rst_n   ),
.op_val    (op_val  ),
.op_rdy    (op_rdy  ),
.op_data   (op_data ),
.res_val   (res_val ),
.res_rdy   (res_rdy ),
.res_data  (res_data)
);

endmodule