data/full_repos/permissive/434837003/test/declaration.v
1: b'%Error: data/full_repos/permissive/434837003/test/declaration.v:8: Unsupported: event data types\nevent e;\n^~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:11: Unsupported: trireg\ntrireg  \n^~~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:12: Unsupported: Verilog 1995 strength specifiers\n    (highz0, pull1) scalared\n     ^~~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:12: Unsupported: Verilog 1995 strength specifiers\n    (highz0, pull1) scalared\n             ^~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:15: Unsupported: wand\nwand\n^~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:16: Unsupported: Verilog 1995 strength specifiers\n    (supply0, weak1)\n     ^~~~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:16: Unsupported: Verilog 1995 strength specifiers\n    (supply0, weak1)\n              ^~~~~\n%Error: data/full_repos/permissive/434837003/test/declaration.v:21: syntax error, unexpected wire, expecting IDENTIFIER or do or final\nwire i = 1, j = 2,\n^~~~\n%Error: Exiting due to 8 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

parameter A = 5;
localparam B = 3;

wire signed [5:2] c [0:3];
reg d;
event e;
integer f;

trireg
    (highz0, pull1) scalared
    signed [B:A] #(1:2:3, 4:5:6) g = 2, h = 3;

wand
    (supply0, weak1)
vectoredsigned
[2:0] #(A:B:2) m = 2, n = 6,


wire i = 1, j = 2,
k = 9;


endmodule
module test;


parameter A = 5;
localparam B = 3;

wire signed [5:2] c [0:3];
reg d;
event e;
integer f;

trireg
    (highz0, pull1) scalared
    signed [B:A] #(1:2:3, 4:5:6) g = 2, h = 3;

wand
    (supply0, weak1)
vectoredsigned
[2:0] #(A:B:2) m = 2, n = 6,


wire i = 1, j = 2,
k = 9;


endmodule