data/full_repos/permissive/416147434/blink.v
data/verilator_xmls/1321af74-7acb-44b2-8646-8e9212c3633f.xml
module blinks(clk,led);

input clk;
output reg led;
reg[23:0] cnt;

always @ (posedge clk) begin
cnt<=cnt+1 'b1;
led<=cnt[23];

end

endmodule
module blinks(clk,led);


input clk;
output reg led;
reg[23:0] cnt;

always @ (posedge clk) begin
cnt<=cnt+1 'b1;
led<=cnt[23];

end

endmodule