data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_my_D_latch1.v
data/verilator_xmls/ad0ed79c-9437-4349-a08f-ea088bef879d.xml
module bm_my_D_latch1(D, C, Q, reset);
	input D, C;
	input reset;
	output Q;
	reg Q;
	
	always @(*)
	begin
		if (~reset)
		begin
			Q = 0;
		end
		else
		begin
			Q = D;
		end
	end
endmodule
module bm_my_D_latch1(D, C, Q, reset);

	input D, C;
	input reset;
	output Q;
	reg Q;
	
	always @(*)
	begin
		if (~reset)
		begin
			Q = 0;
		end
		else
		begin
			Q = D;
		end
	end
endmodule