data/full_repos/permissive/448698580/rtl/basics/src/full_adder.v
data/verilator_xmls/05be832b-55c2-42fc-a4dc-4fd0c0930082.xml
module full_adder
       (
           input x,
           input y,
           input carry_in,
           output carry_out,
           output sum
       );

assign sum = (x ^ y) ^ carry_in;
assign carry_out = ((x ^ y) & carry_in) | (x & y);

endmodule
module full_adder
       (
           input x,
           input y,
           input carry_in,
           output carry_out,
           output sum
       );


assign sum = (x ^ y) ^ carry_in;
assign carry_out = ((x ^ y) & carry_in) | (x & y);

endmodule