data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:214: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sub_counter\' generates 9 bits.\n                                                                              : ... In instance opl2_intf.timer1\n        if (!sub_counter) begin\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:79: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 8 bits.\n                                                                             : ... In instance opl2_intf\n        reg_num <= din;\n                ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:183: Cannot find file containing module: \'opl2\'\nopl2 opl2\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2.v\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2.sv\n             opl2\n             opl2.v\n             opl2.sv\n             obj_dir/opl2\n             obj_dir/opl2.v\n             obj_dir/opl2.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module opl2_intf
(
	input                clk,
	input                clk_opl,
	input                rst_n,
	output               irq_n,

	input                addr,
	output         [7:0] dout,
	input          [7:0] din,
	input                we,
	input                rd,

	output [15:0] sample_l,
	output [15:0] sample_r
);



assign dout  = { timer1_overflow | timer2_overflow, timer1_overflow, timer2_overflow, 5'd0 };
assign irq_n = ~(timer1_overflow | timer2_overflow);



reg [4:0] clk_counter;
wire ce_1us = ( clk_counter == 13 );

always @(posedge clk_opl) begin


    if ( clk_counter == 13 ) begin
        clk_counter <= 0;
    end else begin
        clk_counter <= clk_counter + 1;
    end

end

reg old_write;

always @(posedge clk) begin
	old_write <= we;
end

wire write = (~old_write & we);

reg [8:0] reg_num;

always @(posedge clk) begin
    if (rst_n == 0) begin
        reg_num <= 0;
    end else if (addr == 0 && write) begin
        reg_num <= din;
    end
end

wire       io_write     = (addr && write);
wire [7:0] io_writedata = din;



reg [7:0] timer1_preset;
always @(posedge clk) begin
    if (rst_n == 0) begin
		timer1_preset <= 0;
	end else if (io_write && reg_num == 2) begin
        timer1_preset <= io_writedata;
    end
end

reg timer1_mask;
reg timer1_active;

always @(posedge clk) begin
    if (rst_n == 0) begin
        {timer1_mask, timer1_active} <= 0;
    end else if (io_write && reg_num == 4 && ~io_writedata[7]) begin
        {timer1_mask, timer1_active} <= {io_writedata[6], io_writedata[0]};
    end
end

wire timer1_pulse;

timer #(79) timer1( ce_1us, timer1_preset, timer1_active, timer1_pulse );

reg timer1_overflow;

always @(posedge clk) begin
	if (rst_n == 0) begin
        timer1_overflow <= 0;
	end else begin
		if (io_write && reg_num == 4) begin
            timer1_overflow <= 0;
        end
		if ((timer1_pulse || force_overflow) && ~timer1_mask) begin
            timer1_overflow <= 1;
        end
	end
end




reg [7:0] timer2_preset;

always @(posedge clk) begin
    if (rst_n == 0) begin
        timer2_preset <= 0;
    end else if (io_write && reg_num == 3) begin
        timer2_preset <= io_writedata;
    end
end

reg timer2_mask;
reg timer2_active;

always @(posedge clk) begin
    if (rst_n == 0) begin
        {timer2_mask, timer2_active} <= 0;
    end else if (io_write && reg_num == 4 && ~io_writedata[7]) begin
        {timer2_mask, timer2_active} <= {io_writedata[5], io_writedata[1]};
    end
end

wire timer2_pulse;

timer #(319) timer2( ce_1us, timer2_preset, timer2_active, timer2_pulse );

reg timer2_overflow;

always @(posedge clk) begin
	if (rst_n == 0) begin
        timer2_overflow <= 0;
    end	else begin
		if (io_write && reg_num == 4) begin
            timer2_overflow <= 0;
        end
		if ((timer2_pulse || force_overflow) && ~timer2_mask) begin
            timer2_overflow <= 1;
        end
	end
end

reg force_overflow;






assign sample_l = opl2_channel_a;
assign sample_r = opl2_channel_b;

wire signed [15:0] opl2_channel_a;
wire signed [15:0] opl2_channel_b;

opl2 opl2
(
    .clk(clk),
    .OPL2_clk(clk_opl),

    .opl2_adr(reg_num),
    .opl2_data(din),
    .opl2_we(write & addr),

    .channel_a(opl2_channel_a),
    .channel_b(opl2_channel_b)
);

endmodule
module opl2_intf
(
	input                clk,
	input                clk_opl,
	input                rst_n,
	output               irq_n,

	input                addr,
	output         [7:0] dout,
	input          [7:0] din,
	input                we,
	input                rd,

	output [15:0] sample_l,
	output [15:0] sample_r
);




assign dout  = { timer1_overflow | timer2_overflow, timer1_overflow, timer2_overflow, 5'd0 };
assign irq_n = ~(timer1_overflow | timer2_overflow);



reg [4:0] clk_counter;
wire ce_1us = ( clk_counter == 13 );

always @(posedge clk_opl) begin


    if ( clk_counter == 13 ) begin
        clk_counter <= 0;
    end else begin
        clk_counter <= clk_counter + 1;
    end

end

reg old_write;

always @(posedge clk) begin
	old_write <= we;
end

wire write = (~old_write & we);

reg [8:0] reg_num;

always @(posedge clk) begin
    if (rst_n == 0) begin
        reg_num <= 0;
    end else if (addr == 0 && write) begin
        reg_num <= din;
    end
end

wire       io_write     = (addr && write);
wire [7:0] io_writedata = din;



reg [7:0] timer1_preset;
always @(posedge clk) begin
    if (rst_n == 0) begin
		timer1_preset <= 0;
	end else if (io_write && reg_num == 2) begin
        timer1_preset <= io_writedata;
    end
end

reg timer1_mask;
reg timer1_active;

always @(posedge clk) begin
    if (rst_n == 0) begin
        {timer1_mask, timer1_active} <= 0;
    end else if (io_write && reg_num == 4 && ~io_writedata[7]) begin
        {timer1_mask, timer1_active} <= {io_writedata[6], io_writedata[0]};
    end
end

wire timer1_pulse;

timer #(79) timer1( ce_1us, timer1_preset, timer1_active, timer1_pulse );

reg timer1_overflow;

always @(posedge clk) begin
	if (rst_n == 0) begin
        timer1_overflow <= 0;
	end else begin
		if (io_write && reg_num == 4) begin
            timer1_overflow <= 0;
        end
		if ((timer1_pulse || force_overflow) && ~timer1_mask) begin
            timer1_overflow <= 1;
        end
	end
end




reg [7:0] timer2_preset;

always @(posedge clk) begin
    if (rst_n == 0) begin
        timer2_preset <= 0;
    end else if (io_write && reg_num == 3) begin
        timer2_preset <= io_writedata;
    end
end

reg timer2_mask;
reg timer2_active;

always @(posedge clk) begin
    if (rst_n == 0) begin
        {timer2_mask, timer2_active} <= 0;
    end else if (io_write && reg_num == 4 && ~io_writedata[7]) begin
        {timer2_mask, timer2_active} <= {io_writedata[5], io_writedata[1]};
    end
end

wire timer2_pulse;

timer #(319) timer2( ce_1us, timer2_preset, timer2_active, timer2_pulse );

reg timer2_overflow;

always @(posedge clk) begin
	if (rst_n == 0) begin
        timer2_overflow <= 0;
    end	else begin
		if (io_write && reg_num == 4) begin
            timer2_overflow <= 0;
        end
		if ((timer2_pulse || force_overflow) && ~timer2_mask) begin
            timer2_overflow <= 1;
        end
	end
end

reg force_overflow;






assign sample_l = opl2_channel_a;
assign sample_r = opl2_channel_b;

wire signed [15:0] opl2_channel_a;
wire signed [15:0] opl2_channel_b;

opl2 opl2
(
    .clk(clk),
    .OPL2_clk(clk_opl),

    .opl2_adr(reg_num),
    .opl2_data(din),
    .opl2_we(write & addr),

    .channel_a(opl2_channel_a),
    .channel_b(opl2_channel_b)
);

endmodule