data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/udcounter.v
data/verilator_xmls/bc080202-6e73-4aae-affa-ae1e01d4e1d4.xml
module udcounter(
    input clk1,
    input rst1,
    input en,
    input ud,
    output reg [26:0] tmp
    );

    always@(posedge clk1 or posedge rst1)
    begin
    if(en)

      begin
        if(rst1)
            begin
                if(ud)
                tmp<= 27'd99999999;
                else
                tmp<= 27'd0;
             end
        else
            begin
                if(ud)
                    if(tmp==27'd0)
                        tmp <= 27'd99999999;
                    else
                        tmp <= tmp-1;
                else
                    if(tmp==27'd99999999)
                        tmp <= 27'd0;
                    else
                        tmp <= tmp+1;
             end 

       end
       else
       tmp=tmp;
    end

endmodule
module udcounter(
    input clk1,
    input rst1,
    input en,
    input ud,
    output reg [26:0] tmp
    );


    always@(posedge clk1 or posedge rst1)
    begin
    if(en)

      begin
        if(rst1)
            begin
                if(ud)
                tmp<= 27'd99999999;
                else
                tmp<= 27'd0;
             end
        else
            begin
                if(ud)
                    if(tmp==27'd0)
                        tmp <= 27'd99999999;
                    else
                        tmp <= tmp-1;
                else
                    if(tmp==27'd99999999)
                        tmp <= 27'd0;
                    else
                        tmp <= tmp+1;
             end 

       end
       else
       tmp=tmp;
    end

endmodule