data/full_repos/permissive/515599642/Simple CPU module using Verilog/ALU.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/ALU.v\n%Error: Exiting due to 6 error(s)\n'
module ALU(A, M, ALU_OP, X);

input [3:0] A;
input [3:0] M;
input [2:0] ALU_OP;
output reg [3:0] X;


always@(*) begin
case(ALU_OP)		
        3'b000: 
           X = A; 
        3'b001: 
           X = A + M;
        3'b010: 
           X = A - M;
        3'b011: 
           X = M-A;
        3'b100: 
           X = -(A+M);
        3'b101: 
           X = A & M;
        3'b110: 
           X = A | M;
        3'b111: 
           X = A ^ M;
          endcase
 end
endmodule
module ALU(A, M, ALU_OP, X);


input [3:0] A;
input [3:0] M;
input [2:0] ALU_OP;
output reg [3:0] X;


always@(*) begin
case(ALU_OP)		
        3'b000: 
           X = A; 
        3'b001: 
           X = A + M;
        3'b010: 
           X = A - M;
        3'b011: 
           X = M-A;
        3'b100: 
           X = -(A+M);
        3'b101: 
           X = A & M;
        3'b110: 
           X = A | M;
        3'b111: 
           X = A ^ M;
          endcase
 end
endmodule