data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v
1: b"%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:21: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(23)(clk, reset, clk_cnt);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:22: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(15)(clk, reset, clk_sel);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:24: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select#(4)(clk_sel, reset, seg7_sel);\n                ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:36: syntax error, unexpected '(', expecting IDENTIFIER\nryg_ctl (clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);\n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module 		freq_div(clk_in,reset,clk_out);

parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule
module 		freq_div(clk_in,reset,clk_out);


parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule