data/full_repos/permissive/434840709/lab1/4bitAdder.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/434840709/lab1/4bitAdder.v:11: Signal definition not found, creating implicitly: \'c1\'\n                                                                           : ... Suggested alternative: \'s1\'\n    fulladd stage0(carryin,x0,y0,s0,c1);\n                                    ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/434840709/lab1/4bitAdder.v:12: Signal definition not found, creating implicitly: \'c2\'\n                                                                           : ... Suggested alternative: \'s2\'\n    fulladd stage1(c1,x1,y1,s1,c2);\n                               ^~\n%Warning-IMPLICIT: data/full_repos/permissive/434840709/lab1/4bitAdder.v:13: Signal definition not found, creating implicitly: \'c3\'\n                                                                           : ... Suggested alternative: \'s3\'\n    fulladd stage2(c2,x2,y2,s2,c3);\n                               ^~\n%Error: Exiting due to 3 warning(s)\n'
module fulladd (
    Cin,
    x,
    y,
    s,
    Cout
);

    input Cin,x,y;
    output s,Cout;

    assign s = x^y ^ Cin;
    assign Cout = (x&y) | (x&Cin) | (y&Cin);
    
endmodule
module fulladd (
    Cin,
    x,
    y,
    s,
    Cout
);


    input Cin,x,y;
    output s,Cout;

    assign s = x^y ^ Cin;
    assign Cout = (x&y) | (x&Cin) | (y&Cin);
    
endmodule