data/full_repos/permissive/431605717/Code/RV32IM/EX.v
data/verilator_xmls/25ff423e-f399-43c8-9251-0d93ec3ed4ef.xml
module risc_v_32_ex(pc,a,b,inst,inst_decode,imm_in,m_addr,d_t_mem,wreg,wmem,rmem,i_load,alu_out,next_pc,PCSrc);
    input  [31:0] inst;

    input  [31:0] pc;
    input  [31:0] a;
    input  [31:0] b;
    input  [36:0] inst_decode;
    input  [31:0] imm_in;
    output [31:0] m_addr;
    output [31:0] d_t_mem;
    output        wreg;
    output        wmem;
    output        rmem;
    output        i_load;
    output [31:0] alu_out;

    output [31:0] next_pc;
    output        PCSrc;


    wire [6:0]    opcode = inst[6:0];
    wire [2:0]    func3  = inst[14:12];
    wire [6:0]    func7  = inst[31:25];
    wire [4:0]    rd     = inst[11:7];
    wire [4:0]    rs     = inst[19:15];
    wire [4:0]    rt     = inst[24:20];
    wire [4:0]    shamt  = inst[24:20];
    wire          sign   = inst[31];


    wire          i_auipc = inst_decode[0] ;
    wire          i_lui   = inst_decode[1] ;
    wire          i_jal   = inst_decode[2] ;
    wire          i_jalr  = inst_decode[3] ;
    wire          i_beq   = inst_decode[4] ;
    wire          i_bne   = inst_decode[5] ;
    wire          i_blt   = inst_decode[6] ;
    wire          i_bge   = inst_decode[7] ;
    wire          i_bltu  = inst_decode[8] ;
    wire          i_bgeu  = inst_decode[9] ;
    wire          i_lb    = inst_decode[10];
    wire          i_lh    = inst_decode[11];
    wire          i_lw    = inst_decode[12];
    wire          i_lbu   = inst_decode[13];
    wire          i_lhu   = inst_decode[14];
    wire          i_sb    = inst_decode[15];
    wire          i_sh    = inst_decode[16];
    wire          i_sw    = inst_decode[17];
    wire          i_addi  = inst_decode[18];
    wire          i_slti  = inst_decode[19];
    wire          i_sltiu = inst_decode[20];
    wire          i_xori  = inst_decode[21];
    wire          i_ori   = inst_decode[22];
    wire          i_andi  = inst_decode[23];
    wire          i_slli  = inst_decode[24];
    wire          i_srli  = inst_decode[25];
    wire          i_srai  = inst_decode[26];
    wire          i_add   = inst_decode[27];
    wire          i_sub   = inst_decode[28];
    wire          i_sll   = inst_decode[29];
    wire          i_slt   = inst_decode[30];
    wire          i_sltu  = inst_decode[31];
    wire          i_xor   = inst_decode[32];
    wire          i_srl   = inst_decode[33];
    wire          i_sra   = inst_decode[34];
    wire          i_or    = inst_decode[35];
    wire          i_and   = inst_decode[36];




    assign d_t_mem =  b;


    assign i_load = i_lw | i_lb | i_lbu | i_lh | i_lhu;

    

    reg           wreg;
    reg           wmem;
    reg           rmem;
    reg   [31:0]  alu_out;

    reg   [31:0]  m_addr;
    reg   [31:0]  next_pc;
    reg           PCSrc;
    wire  [31:0]  pc_plus_4 = pc + 4;


    always @(*) begin
        alu_out = 0;

        m_addr  = 0;
        wreg    = 0;
        wmem    = 0;
        rmem    = 0;
        PCSrc   = 0;
        case (1'b1)
            i_add: begin
                alu_out = a + b;
                wreg    = 1; end
            i_sub: begin
                alu_out = a - b;
                wreg    = 1; end
            i_and: begin
                alu_out = a & b;
                wreg    = 1; end
            i_or: begin
                alu_out = a | b;
                wreg    = 1; end
            i_xor: begin
                alu_out = a ^ b;
                wreg    = 1; end
            i_sll: begin
                alu_out = a << b[4:0];
                wreg    = 1; end
            i_srl: begin
                alu_out = a >> b[4:0];
                wreg    = 1; end
            i_sra: begin
                alu_out = $signed(a) >>> b[4:0];
                wreg    = 1; end
            i_slli: begin
                alu_out = a << shamt;
                wreg    = 1; end
            i_srli: begin
                alu_out = a >> shamt;
                wreg    = 1; end
            i_srai: begin
                alu_out = $signed(a) >>> shamt;
                wreg    = 1; end
            i_slt: begin
                if ($signed(a) < $signed(b)) 
                  alu_out = 1; end
            i_sltu: begin
                if ({1'b0,a} < {1'b0,b}) 
                  alu_out = 1; end
            i_addi: begin
                alu_out = a + imm_in;
                wreg    = 1; end
            i_andi: begin
                alu_out = a & imm_in;
                wreg    = 1; end
            i_ori: begin
                alu_out = a | imm_in;
                wreg    = 1; end
            i_xori: begin
                alu_out = a ^ imm_in;
                wreg    = 1; end
            i_slti: begin
                if ($signed(a) < $signed(imm_in)) 
                  alu_out = 1; end
            i_sltiu: begin
                if ({1'b0,a} < {1'b0,imm_in}) 
                  alu_out = 1; end
            i_lw: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:2],2'b00};
                rmem    = 1;

                wreg    = 1; end
            i_lbu: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                rmem    = 1;

                wreg    = 1; end
            i_lb: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                rmem    = 1;

                wreg    = 1; end
            i_lhu: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                rmem    = 1;

                wreg    = 1; end
            i_lh: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                rmem    = 1;

                wreg    = 1; end
            i_sb: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                wmem    = 1; end
            i_sh: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                wmem    = 1; end
            i_sw: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:2],2'b00};
                wmem    = 1; end
            i_beq: begin
                if (a == b) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bne: begin
                if (a != b) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_blt: begin
                if ($signed(a) < $signed(b)) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bge: begin
                if ($signed(a) >= $signed(b)) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bltu: begin
                if ({1'b0,a} < {1'b0,b}) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bgeu: begin
                if ({1'b0,a} >= {1'b0,b}) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_auipc: begin
                alu_out = pc + imm_in;
                wreg    = 1; end
            i_lui: begin
                alu_out = imm_in;
                wreg    = 1; end
            i_jal: begin
                alu_out = pc_plus_4;
                wreg    = 1;
                next_pc = pc + imm_in;
                PCSrc   = 1; end
            i_jalr: begin
                alu_out = pc_plus_4;
                wreg    = 1;
                next_pc = a + imm_in;
                PCSrc   = 1; end
            default: ;
        endcase
    end
endmodule
module risc_v_32_ex(pc,a,b,inst,inst_decode,imm_in,m_addr,d_t_mem,wreg,wmem,rmem,i_load,alu_out,next_pc,PCSrc);

    input  [31:0] inst;

    input  [31:0] pc;
    input  [31:0] a;
    input  [31:0] b;
    input  [36:0] inst_decode;
    input  [31:0] imm_in;
    output [31:0] m_addr;
    output [31:0] d_t_mem;
    output        wreg;
    output        wmem;
    output        rmem;
    output        i_load;
    output [31:0] alu_out;

    output [31:0] next_pc;
    output        PCSrc;


    wire [6:0]    opcode = inst[6:0];
    wire [2:0]    func3  = inst[14:12];
    wire [6:0]    func7  = inst[31:25];
    wire [4:0]    rd     = inst[11:7];
    wire [4:0]    rs     = inst[19:15];
    wire [4:0]    rt     = inst[24:20];
    wire [4:0]    shamt  = inst[24:20];
    wire          sign   = inst[31];


    wire          i_auipc = inst_decode[0] ;
    wire          i_lui   = inst_decode[1] ;
    wire          i_jal   = inst_decode[2] ;
    wire          i_jalr  = inst_decode[3] ;
    wire          i_beq   = inst_decode[4] ;
    wire          i_bne   = inst_decode[5] ;
    wire          i_blt   = inst_decode[6] ;
    wire          i_bge   = inst_decode[7] ;
    wire          i_bltu  = inst_decode[8] ;
    wire          i_bgeu  = inst_decode[9] ;
    wire          i_lb    = inst_decode[10];
    wire          i_lh    = inst_decode[11];
    wire          i_lw    = inst_decode[12];
    wire          i_lbu   = inst_decode[13];
    wire          i_lhu   = inst_decode[14];
    wire          i_sb    = inst_decode[15];
    wire          i_sh    = inst_decode[16];
    wire          i_sw    = inst_decode[17];
    wire          i_addi  = inst_decode[18];
    wire          i_slti  = inst_decode[19];
    wire          i_sltiu = inst_decode[20];
    wire          i_xori  = inst_decode[21];
    wire          i_ori   = inst_decode[22];
    wire          i_andi  = inst_decode[23];
    wire          i_slli  = inst_decode[24];
    wire          i_srli  = inst_decode[25];
    wire          i_srai  = inst_decode[26];
    wire          i_add   = inst_decode[27];
    wire          i_sub   = inst_decode[28];
    wire          i_sll   = inst_decode[29];
    wire          i_slt   = inst_decode[30];
    wire          i_sltu  = inst_decode[31];
    wire          i_xor   = inst_decode[32];
    wire          i_srl   = inst_decode[33];
    wire          i_sra   = inst_decode[34];
    wire          i_or    = inst_decode[35];
    wire          i_and   = inst_decode[36];




    assign d_t_mem =  b;


    assign i_load = i_lw | i_lb | i_lbu | i_lh | i_lhu;

    

    reg           wreg;
    reg           wmem;
    reg           rmem;
    reg   [31:0]  alu_out;

    reg   [31:0]  m_addr;
    reg   [31:0]  next_pc;
    reg           PCSrc;
    wire  [31:0]  pc_plus_4 = pc + 4;


    always @(*) begin
        alu_out = 0;

        m_addr  = 0;
        wreg    = 0;
        wmem    = 0;
        rmem    = 0;
        PCSrc   = 0;
        case (1'b1)
            i_add: begin
                alu_out = a + b;
                wreg    = 1; end
            i_sub: begin
                alu_out = a - b;
                wreg    = 1; end
            i_and: begin
                alu_out = a & b;
                wreg    = 1; end
            i_or: begin
                alu_out = a | b;
                wreg    = 1; end
            i_xor: begin
                alu_out = a ^ b;
                wreg    = 1; end
            i_sll: begin
                alu_out = a << b[4:0];
                wreg    = 1; end
            i_srl: begin
                alu_out = a >> b[4:0];
                wreg    = 1; end
            i_sra: begin
                alu_out = $signed(a) >>> b[4:0];
                wreg    = 1; end
            i_slli: begin
                alu_out = a << shamt;
                wreg    = 1; end
            i_srli: begin
                alu_out = a >> shamt;
                wreg    = 1; end
            i_srai: begin
                alu_out = $signed(a) >>> shamt;
                wreg    = 1; end
            i_slt: begin
                if ($signed(a) < $signed(b)) 
                  alu_out = 1; end
            i_sltu: begin
                if ({1'b0,a} < {1'b0,b}) 
                  alu_out = 1; end
            i_addi: begin
                alu_out = a + imm_in;
                wreg    = 1; end
            i_andi: begin
                alu_out = a & imm_in;
                wreg    = 1; end
            i_ori: begin
                alu_out = a | imm_in;
                wreg    = 1; end
            i_xori: begin
                alu_out = a ^ imm_in;
                wreg    = 1; end
            i_slti: begin
                if ($signed(a) < $signed(imm_in)) 
                  alu_out = 1; end
            i_sltiu: begin
                if ({1'b0,a} < {1'b0,imm_in}) 
                  alu_out = 1; end
            i_lw: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:2],2'b00};
                rmem    = 1;

                wreg    = 1; end
            i_lbu: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                rmem    = 1;

                wreg    = 1; end
            i_lb: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                rmem    = 1;

                wreg    = 1; end
            i_lhu: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                rmem    = 1;

                wreg    = 1; end
            i_lh: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                rmem    = 1;

                wreg    = 1; end
            i_sb: begin
                alu_out = a + imm_in;
                m_addr  = alu_out;
                wmem    = 1; end
            i_sh: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:1],1'b0};
                wmem    = 1; end
            i_sw: begin
                alu_out = a + imm_in;
                m_addr  = {alu_out[31:2],2'b00};
                wmem    = 1; end
            i_beq: begin
                if (a == b) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bne: begin
                if (a != b) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_blt: begin
                if ($signed(a) < $signed(b)) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bge: begin
                if ($signed(a) >= $signed(b)) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bltu: begin
                if ({1'b0,a} < {1'b0,b}) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_bgeu: begin
                if ({1'b0,a} >= {1'b0,b}) begin
                  next_pc = pc + imm_in;
                  PCSrc   = 1; end end
            i_auipc: begin
                alu_out = pc + imm_in;
                wreg    = 1; end
            i_lui: begin
                alu_out = imm_in;
                wreg    = 1; end
            i_jal: begin
                alu_out = pc_plus_4;
                wreg    = 1;
                next_pc = pc + imm_in;
                PCSrc   = 1; end
            i_jalr: begin
                alu_out = pc_plus_4;
                wreg    = 1;
                next_pc = a + imm_in;
                PCSrc   = 1; end
            default: ;
        endcase
    end
endmodule