data/full_repos/permissive/511502298/Testbenches/rec_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n #150;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n #8000 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8680.5 rx = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/rec_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n%Error: data/full_repos/permissive/511502298/Testbenches/rec_test.v:16: Cannot find file containing module: \'receiver\'\n receiver uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/receiver\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/receiver.v\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/receiver.sv\n             receiver\n             receiver.v\n             receiver.sv\n             obj_dir/receiver\n             obj_dir/receiver.v\n             obj_dir/receiver.sv\n%Error: Exiting due to 1 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rec_test;


	reg clk;
	reg rx;
	reg rst;


	wire ready;
	wire [7:0] data;


	receiver uut (
		.clk(clk), 
		.rx(rx), 
		.ready(ready), 
		.data(data),
		.rst(rst)
	);

	initial begin
	
	
	#150;
				rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	
	#8000	;
	
				rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	
	
	
		
	end

	initial begin

		clk = 0;
		rx = 1;
		rst = 0;


		#100;
			rst = 1;
		
		forever
		#5 clk = !clk;
		        


	end
      
endmodule
module rec_test;



	reg clk;
	reg rx;
	reg rst;


	wire ready;
	wire [7:0] data;


	receiver uut (
		.clk(clk), 
		.rx(rx), 
		.ready(ready), 
		.data(data),
		.rst(rst)
	);

	initial begin
	
	
	#150;
				rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	
	#8000	;
	
				rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 0;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	#8680.5	rx = 1;
	
	
	
		
	end

	initial begin

		clk = 0;
		rx = 1;
		rst = 0;


		#100;
			rst = 1;
		
		forever
		#5 clk = !clk;
		        


	end
      
endmodule