data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/OPAD.v
data/verilator_xmls/99ebd336-cee4-4ca7-9da6-92d0bb76b28c.xml
module OPAD (PAD, EN, I);
parameter WIDE = 1;

output [WIDE-1:0] PAD;
input [WIDE-1:0]  I;
input             EN;

wire [WIDE-1:0] PAD = EN ? I : {WIDE{1'bZ}}; 
endmodule
module OPAD (PAD, EN, I);

parameter WIDE = 1;

output [WIDE-1:0] PAD;
input [WIDE-1:0]  I;
input             EN;

wire [WIDE-1:0] PAD = EN ? I : {WIDE{1'bZ}}; 
endmodule