data/full_repos/permissive/477054115/iitb-risc/InstrMem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/477054115/iitb-risc/InstrMem.v:24: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                            : ... In instance instr_mem\n    assign instruction = (pc[15:0] < 48) ? rom[rom_addr]: 16\'b0111000000000000;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module instr_mem
 (
    input   [15:0]  pc,
    input clk, reset,
    output wire [15:0]  instruction
 );
    wire [3:0] rom_addr = pc[3:0];


    reg [15:0] rom [16:0];
    integer i;
    

    assign instruction = (pc[15:0] < 48) ? rom[rom_addr]: 16'b0111000000000000;

    always @(posedge clk)
		begin
			if(reset== 1'b1)
				begin
					for(i=0;i<16;i=i+1) rom[i] = 16'b0111000000000000;
				end
            else begin
                rom[0] = 16'b0111000000000000;
                rom[1] = 16'b0000000000011111;
                rom[2] = 16'b0000000000100001;
                rom[3] = 16'b0000001001000100;
                rom[4] = 16'b0001000001010001;












                








            end

        end		
endmodule
module instr_mem
 (
    input   [15:0]  pc,
    input clk, reset,
    output wire [15:0]  instruction
 );

    wire [3:0] rom_addr = pc[3:0];


    reg [15:0] rom [16:0];
    integer i;
    

    assign instruction = (pc[15:0] < 48) ? rom[rom_addr]: 16'b0111000000000000;

    always @(posedge clk)
		begin
			if(reset== 1'b1)
				begin
					for(i=0;i<16;i=i+1) rom[i] = 16'b0111000000000000;
				end
            else begin
                rom[0] = 16'b0111000000000000;
                rom[1] = 16'b0000000000011111;
                rom[2] = 16'b0000000000100001;
                rom[3] = 16'b0000001001000100;
                rom[4] = 16'b0001000001010001;












                








            end

        end		
endmodule