data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/main.v
1: b"%Error: data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/main.v:47: Cannot find file containing module: 'Counter'\n    Counter #(20) c(counter,clk);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.v\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new,data/full_repos/permissive/423958267/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Error: data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/main.v:51: Cannot find file containing module: 'Mux4to1'\n    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/main.v:52: Cannot find file containing module: 'Decoder4'\n    Decoder4 dec(sel,q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/main.v:53: Cannot find file containing module: 'HexTo7Seg'\n    HexTo7Seg h(seg,d);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input clk
);
    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0;
    wire [3:0] digit1;
    wire [3:0] digit2;
    wire [3:0] digit3;
    wire [3:0] sel;
    wire [19:0] counter;
    
    assign digit0 = 4'd4;
    assign digit1 = 4'd3;
    assign digit2 = 4'd2;
    assign digit3 = 4'd1;
    
    assign q = {counter[19],counter[18]};
    
    assign an = ~sel;
    Counter #(20) c(counter,clk);
    

    
    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);
    
endmodule
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input clk
);

    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0;
    wire [3:0] digit1;
    wire [3:0] digit2;
    wire [3:0] digit3;
    wire [3:0] sel;
    wire [19:0] counter;
    
    assign digit0 = 4'd4;
    assign digit1 = 4'd3;
    assign digit2 = 4'd2;
    assign digit3 = 4'd1;
    
    assign q = {counter[19],counter[18]};
    
    assign an = ~sel;
    Counter #(20) c(counter,clk);
    

    
    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);
    
endmodule