data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v
1: b'%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:32: Cannot find include file: sd_defines.h\n`include "sd_defines.h" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.v\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.sv\n             sd_defines.h\n             sd_defines.h.v\n             sd_defines.h.sv\n             obj_dir/sd_defines.h\n             obj_dir/sd_defines.h.v\n             obj_dir/sd_defines.h.sv\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:51: Define or directive not defined: \'`CMD_REG_SIZE\'\n    input [`CMD_REG_SIZE-1:0] command_i,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:52: Define or directive not defined: \'`CMD_TIMEOUT_W\'\n    input [`CMD_TIMEOUT_W-1:0] timeout_i,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:53: Define or directive not defined: \'`INT_CMD_SIZE\'\n    output [`INT_CMD_SIZE-1:0] int_status_o,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:62: Define or directive not defined: \'`INT_CMD_SIZE\'\nreg [`INT_CMD_SIZE-1:0] int_status_reg;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:63: Define or directive not defined: \'`CMD_TIMEOUT_W\'\nreg [`CMD_TIMEOUT_W-1:0] watchdog;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:95: Define or directive not defined: \'`CMD_RESPONSE_CHECK\'\n                if (command_i[`CMD_RESPONSE_CHECK]  == 2\'b10 || command_i[`CMD_RESPONSE_CHECK] == 2\'b11) begin\n                              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:95: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                if (command_i[`CMD_RESPONSE_CHECK]  == 2\'b10 || command_i[`CMD_RESPONSE_CHECK] == 2\'b11) begin\n                                                 ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:95: Define or directive not defined: \'`CMD_RESPONSE_CHECK\'\n                if (command_i[`CMD_RESPONSE_CHECK]  == 2\'b10 || command_i[`CMD_RESPONSE_CHECK] == 2\'b11) begin\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:98: syntax error, unexpected else, expecting endcase\n                end else if (command_i[`CMD_RESPONSE_CHECK] == 2\'b01) begin\n                    ^~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:98: Define or directive not defined: \'`CMD_RESPONSE_CHECK\'\n                end else if (command_i[`CMD_RESPONSE_CHECK] == 2\'b01) begin\n                                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:106: Define or directive not defined: \'`CMD_INDEX\'\n                cmd_o[37:32] <= command_i[`CMD_INDEX];\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:106: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                cmd_o[37:32] <= command_i[`CMD_INDEX];\n                                                    ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:117: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n            EXECUTE: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:120: syntax error, unexpected \'[\', expecting IDENTIFIER\n                    int_status_reg[`INT_CMD_CTE] <= 1;\n                                  ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:120: Define or directive not defined: \'`INT_CMD_CTE\'\n                    int_status_reg[`INT_CMD_CTE] <= 1;\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:121: Define or directive not defined: \'`INT_CMD_EI\'\n                    int_status_reg[`INT_CMD_EI] <= 1;\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:126: syntax error, unexpected <=, expecting IDENTIFIER\n                        watchdog <= watchdog + 1;\n                                 ^~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:127: syntax error, unexpected <=, expecting IDENTIFIER\n                        if (watchdog >= timeout_i) watchdog_alarm <= 1;\n                                                                  ^~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:130: Define or directive not defined: \'`CMD_CRC_CHECK\'\n                        if (command_i[`CMD_CRC_CHECK] && !crc_ok_i) begin\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:130: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        if (command_i[`CMD_CRC_CHECK] && !crc_ok_i) begin\n                                                    ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:131: Define or directive not defined: \'`INT_CMD_CCRCE\'\n                            int_status_reg[`INT_CMD_CCRCE] <= 1;\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:132: Define or directive not defined: \'`INT_CMD_EI\'\n                            int_status_reg[`INT_CMD_EI] <= 1;\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:134: Define or directive not defined: \'`CMD_IDX_CHECK\'\n                        if (command_i[`CMD_IDX_CHECK] && !index_ok_i) begin\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:134: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        if (command_i[`CMD_IDX_CHECK] && !index_ok_i) begin\n                                                    ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:135: Define or directive not defined: \'`INT_CMD_CIE\'\n                            int_status_reg[`INT_CMD_CIE] <= 1;\n                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:136: Define or directive not defined: \'`INT_CMD_EI\'\n                            int_status_reg[`INT_CMD_EI] <= 1;\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:138: syntax error, unexpected \'[\', expecting IDENTIFIER\n                        int_status_reg[`INT_CMD_CC] <= 1;\n                                      ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:138: Define or directive not defined: \'`INT_CMD_CC\'\n                        int_status_reg[`INT_CMD_CC] <= 1;\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:140: syntax error, unexpected <=, expecting IDENTIFIER\n                            response_0_o <= response_i[119:88];\n                                         ^~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:145: Define or directive not defined: \'`CMD_BUSY_CHECK\'\n                        if (command_i[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_master.v:145: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        if (command_i[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;\n                                                     ^\n%Error: Cannot continue\n'
module sd_cmd_master(
    input clock,
    input clock_posedge,
    input rst,
    input start_i,
    input int_status_rst_i,
    output [1:0] setting_o,
    output reg start_xfr_o,
    output reg go_idle_o,
    output reg  [39:0] cmd_o,
    input [119:0] response_i,
    input crc_ok_i,
    input index_ok_i,
    input finish_i,
    input busy_i,

    input [31:0] argument_i,
    input [`CMD_REG_SIZE-1:0] command_i,
    input [`CMD_TIMEOUT_W-1:0] timeout_i,
    output [`INT_CMD_SIZE-1:0] int_status_o,
    output reg [31:0] response_0_o,
    output reg [31:0] response_1_o,
    output reg [31:0] response_2_o,
    output reg [31:0] response_3_o
);

reg expect_response;
reg long_response;
reg [`INT_CMD_SIZE-1:0] int_status_reg;
reg [`CMD_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg watchdog_alarm;

reg [2:0] state;
parameter IDLE       = 3'b001;
parameter EXECUTE    = 3'b010;
parameter BUSY_CHECK = 3'b100;

assign setting_o[1:0] = {long_response, expect_response};
assign int_status_o = state == IDLE ? int_status_reg : 5'h0;

always @(posedge clock) begin
    if (rst) begin
        response_0_o <= 0;
        response_1_o <= 0;
        response_2_o <= 0;
        response_3_o <= 0;
        int_status_reg <= 0;
        expect_response <= 0;
        long_response <= 0;
        cmd_o <= 0;
        start_xfr_o <= 0;
        watchdog <= 0;
        watchdog_enable <= 0;
        watchdog_alarm <= 0;
        go_idle_o <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                go_idle_o <= 0;
                if (command_i[`CMD_RESPONSE_CHECK]  == 2'b10 || command_i[`CMD_RESPONSE_CHECK] == 2'b11) begin
                    expect_response <=  1;
                    long_response <= 1;
                end else if (command_i[`CMD_RESPONSE_CHECK] == 2'b01) begin
                    expect_response <= 1;
                    long_response <= 0;
                end else begin
                    expect_response <= 0;
                    long_response <= 0;
                end
                cmd_o[39:38] <= 2'b01;
                cmd_o[37:32] <= command_i[`CMD_INDEX];
                cmd_o[31:0] <= argument_i;
                watchdog <= 0;
                watchdog_enable <= timeout_i != 0;
                watchdog_alarm <= 0;
                if (start_i) begin
                    start_xfr_o <= 1;
                    int_status_reg <= 0;
                    state <= EXECUTE;
                end
            end
            EXECUTE: begin
                start_xfr_o <= 0;
                if (watchdog_alarm) begin
                    int_status_reg[`INT_CMD_CTE] <= 1;
                    int_status_reg[`INT_CMD_EI] <= 1;
                    go_idle_o <= 1;
                    state <= IDLE;
                end else begin
                    if (watchdog_enable) begin
                        watchdog <= watchdog + 1;
                        if (watchdog >= timeout_i) watchdog_alarm <= 1;
                    end
                    if (finish_i) begin
                        if (command_i[`CMD_CRC_CHECK] && !crc_ok_i) begin
                            int_status_reg[`INT_CMD_CCRCE] <= 1;
                            int_status_reg[`INT_CMD_EI] <= 1;
                        end
                        if (command_i[`CMD_IDX_CHECK] && !index_ok_i) begin
                            int_status_reg[`INT_CMD_CIE] <= 1;
                            int_status_reg[`INT_CMD_EI] <= 1;
                        end
                        int_status_reg[`INT_CMD_CC] <= 1;
                        if (expect_response) begin
                            response_0_o <= response_i[119:88];
                            response_1_o <= response_i[87:56];
                            response_2_o <= response_i[55:24];
                            response_3_o <= {response_i[23:0], 8'h00};
                        end
                        if (command_i[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;
                        else state <= IDLE;
                    end
                end
            end
            BUSY_CHECK: begin
                if (!busy_i) state <= IDLE;
            end
        endcase
        if (int_status_rst_i)
            int_status_reg <= 0;
    end
end

endmodule
module sd_cmd_master(
    input clock,
    input clock_posedge,
    input rst,
    input start_i,
    input int_status_rst_i,
    output [1:0] setting_o,
    output reg start_xfr_o,
    output reg go_idle_o,
    output reg  [39:0] cmd_o,
    input [119:0] response_i,
    input crc_ok_i,
    input index_ok_i,
    input finish_i,
    input busy_i,

    input [31:0] argument_i,
    input [`CMD_REG_SIZE-1:0] command_i,
    input [`CMD_TIMEOUT_W-1:0] timeout_i,
    output [`INT_CMD_SIZE-1:0] int_status_o,
    output reg [31:0] response_0_o,
    output reg [31:0] response_1_o,
    output reg [31:0] response_2_o,
    output reg [31:0] response_3_o
);


reg expect_response;
reg long_response;
reg [`INT_CMD_SIZE-1:0] int_status_reg;
reg [`CMD_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg watchdog_alarm;

reg [2:0] state;
parameter IDLE       = 3'b001;
parameter EXECUTE    = 3'b010;
parameter BUSY_CHECK = 3'b100;

assign setting_o[1:0] = {long_response, expect_response};
assign int_status_o = state == IDLE ? int_status_reg : 5'h0;

always @(posedge clock) begin
    if (rst) begin
        response_0_o <= 0;
        response_1_o <= 0;
        response_2_o <= 0;
        response_3_o <= 0;
        int_status_reg <= 0;
        expect_response <= 0;
        long_response <= 0;
        cmd_o <= 0;
        start_xfr_o <= 0;
        watchdog <= 0;
        watchdog_enable <= 0;
        watchdog_alarm <= 0;
        go_idle_o <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                go_idle_o <= 0;
                if (command_i[`CMD_RESPONSE_CHECK]  == 2'b10 || command_i[`CMD_RESPONSE_CHECK] == 2'b11) begin
                    expect_response <=  1;
                    long_response <= 1;
                end else if (command_i[`CMD_RESPONSE_CHECK] == 2'b01) begin
                    expect_response <= 1;
                    long_response <= 0;
                end else begin
                    expect_response <= 0;
                    long_response <= 0;
                end
                cmd_o[39:38] <= 2'b01;
                cmd_o[37:32] <= command_i[`CMD_INDEX];
                cmd_o[31:0] <= argument_i;
                watchdog <= 0;
                watchdog_enable <= timeout_i != 0;
                watchdog_alarm <= 0;
                if (start_i) begin
                    start_xfr_o <= 1;
                    int_status_reg <= 0;
                    state <= EXECUTE;
                end
            end
            EXECUTE: begin
                start_xfr_o <= 0;
                if (watchdog_alarm) begin
                    int_status_reg[`INT_CMD_CTE] <= 1;
                    int_status_reg[`INT_CMD_EI] <= 1;
                    go_idle_o <= 1;
                    state <= IDLE;
                end else begin
                    if (watchdog_enable) begin
                        watchdog <= watchdog + 1;
                        if (watchdog >= timeout_i) watchdog_alarm <= 1;
                    end
                    if (finish_i) begin
                        if (command_i[`CMD_CRC_CHECK] && !crc_ok_i) begin
                            int_status_reg[`INT_CMD_CCRCE] <= 1;
                            int_status_reg[`INT_CMD_EI] <= 1;
                        end
                        if (command_i[`CMD_IDX_CHECK] && !index_ok_i) begin
                            int_status_reg[`INT_CMD_CIE] <= 1;
                            int_status_reg[`INT_CMD_EI] <= 1;
                        end
                        int_status_reg[`INT_CMD_CC] <= 1;
                        if (expect_response) begin
                            response_0_o <= response_i[119:88];
                            response_1_o <= response_i[87:56];
                            response_2_o <= response_i[55:24];
                            response_3_o <= {response_i[23:0], 8'h00};
                        end
                        if (command_i[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;
                        else state <= IDLE;
                    end
                end
            end
            BUSY_CHECK: begin
                if (!busy_i) state <= IDLE;
            end
        endcase
        if (int_status_rst_i)
            int_status_reg <= 0;
    end
end

endmodule