data/full_repos/permissive/480141277/decoder.v
data/verilator_xmls/b4f0091a-3794-4406-b03a-84f343312bb6.xml
module decoder(
					input [7:0]in,
					output reg [6:0]outSeg);

always @ (*)
	begin 
		case (in)
		8'h16: outSeg = 7'b1111001;
		8'h1E: outSeg = 7'b0100100;
		8'h26: outSeg = 7'b0110000;
		8'h25: outSeg = 7'b0011001;
		8'h2E: outSeg = 7'b0010010;
		8'h36: outSeg = 7'b0000010;
		8'h3D: outSeg = 7'b1111000;
		8'h3E: outSeg = 7'b0000000;
		8'h46: outSeg = 7'b0010000;
		8'h45: outSeg = 7'b1000000;
		
		8'h15: outSeg = 7'b0011000;
		8'h1D: outSeg = 7'b0111111;
		8'h24: outSeg = 7'b0000110;
		8'h2D: outSeg = 7'b0101111;
		8'h2C: outSeg = 7'b0000111;
		8'h35: outSeg = 7'b0010001;
		8'h3C: outSeg = 7'b1000001;
		8'h43: outSeg = 7'b1111001;
		8'h44: outSeg = 7'b0100011;
		8'h4D: outSeg = 7'b0001100;
		8'h1C: outSeg = 7'b0001000;
		8'h1B: outSeg = 7'b0010010;
		8'h23: outSeg = 7'b0100001;
		8'h2B: outSeg = 7'b0001110;
		8'h34: outSeg = 7'b0010000;
		8'h33: outSeg = 7'b0001001;
		8'h3B: outSeg = 7'b1100001;
		8'h42: outSeg = 7'b0111111;
		8'h4B: outSeg = 7'b1000111;
		8'h1A: outSeg = 7'b0111111;
		8'h22: outSeg = 7'b0111111;
		8'h21: outSeg = 7'b1000110;
		8'h2A: outSeg = 7'b1100011;
		8'h32: outSeg = 7'b0000011;
		8'h31: outSeg = 7'b0101011;
		8'h3A: outSeg = 7'b0111111;
		
		default: outSeg=7'b1111111;
		endcase
	end
endmodule
module decoder(
					input [7:0]in,
					output reg [6:0]outSeg);


always @ (*)
	begin 
		case (in)
		8'h16: outSeg = 7'b1111001;
		8'h1E: outSeg = 7'b0100100;
		8'h26: outSeg = 7'b0110000;
		8'h25: outSeg = 7'b0011001;
		8'h2E: outSeg = 7'b0010010;
		8'h36: outSeg = 7'b0000010;
		8'h3D: outSeg = 7'b1111000;
		8'h3E: outSeg = 7'b0000000;
		8'h46: outSeg = 7'b0010000;
		8'h45: outSeg = 7'b1000000;
		
		8'h15: outSeg = 7'b0011000;
		8'h1D: outSeg = 7'b0111111;
		8'h24: outSeg = 7'b0000110;
		8'h2D: outSeg = 7'b0101111;
		8'h2C: outSeg = 7'b0000111;
		8'h35: outSeg = 7'b0010001;
		8'h3C: outSeg = 7'b1000001;
		8'h43: outSeg = 7'b1111001;
		8'h44: outSeg = 7'b0100011;
		8'h4D: outSeg = 7'b0001100;
		8'h1C: outSeg = 7'b0001000;
		8'h1B: outSeg = 7'b0010010;
		8'h23: outSeg = 7'b0100001;
		8'h2B: outSeg = 7'b0001110;
		8'h34: outSeg = 7'b0010000;
		8'h33: outSeg = 7'b0001001;
		8'h3B: outSeg = 7'b1100001;
		8'h42: outSeg = 7'b0111111;
		8'h4B: outSeg = 7'b1000111;
		8'h1A: outSeg = 7'b0111111;
		8'h22: outSeg = 7'b0111111;
		8'h21: outSeg = 7'b1000110;
		8'h2A: outSeg = 7'b1100011;
		8'h32: outSeg = 7'b0000011;
		8'h31: outSeg = 7'b0101011;
		8'h3A: outSeg = 7'b0111111;
		
		default: outSeg=7'b1111111;
		endcase
	end
endmodule