data/full_repos/permissive/479997390/src/PipelineRegisters.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/479997390/src/PipelineRegisters.v:28: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'IF_ID\'\nmodule IF_ID (\n       ^~~~~\n                                                                                  : ... Top module \'ID_EX\'\nmodule ID_EX (\n       ^~~~~\n                                                                                  : ... Top module \'EX_MEM\'\nmodule EX_MEM (\n       ^~~~~~\n                                                                                  : ... Top module \'MEM_WB\'\nmodule MEM_WB (\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MEM_WB (
  clk,
  DataOutIn, 
  ALUOutIn,
  MemToRegIn,
  WriteRegAddrOutIn,
  RegWriteIn,
  DataOutOut, 
  ALUOutOut,
  MemToRegOut,
  WriteRegAddrOutOut,
  RegWriteOut
);

  input clk;
  input [31:0] DataOutIn, ALUOutIn;
  input MemToRegIn, RegWriteIn;
  input [4:0] WriteRegAddrOutIn;
  output reg [31:0] DataOutOut, ALUOutOut;
  output reg MemToRegOut, RegWriteOut;
  output reg [4:0] WriteRegAddrOutOut;

  always @(posedge clk) begin
    DataOutOut <= DataOutIn;
    ALUOutOut <= ALUOutIn;
    MemToRegOut <= MemToRegIn;
    RegWriteOut <= RegWriteIn;
    WriteRegAddrOutOut <= WriteRegAddrOutIn;
  end
endmodule
module MEM_WB (
  clk,
  DataOutIn, 
  ALUOutIn,
  MemToRegIn,
  WriteRegAddrOutIn,
  RegWriteIn,
  DataOutOut, 
  ALUOutOut,
  MemToRegOut,
  WriteRegAddrOutOut,
  RegWriteOut
);


  input clk;
  input [31:0] DataOutIn, ALUOutIn;
  input MemToRegIn, RegWriteIn;
  input [4:0] WriteRegAddrOutIn;
  output reg [31:0] DataOutOut, ALUOutOut;
  output reg MemToRegOut, RegWriteOut;
  output reg [4:0] WriteRegAddrOutOut;

  always @(posedge clk) begin
    DataOutOut <= DataOutIn;
    ALUOutOut <= ALUOutIn;
    MemToRegOut <= MemToRegIn;
    RegWriteOut <= RegWriteIn;
    WriteRegAddrOutOut <= WriteRegAddrOutIn;
  end
endmodule