data/full_repos/permissive/515100461/sequential/processor.v
1: b'%Error: data/full_repos/permissive/515100461/sequential/processor.v:1: Cannot find include file: fetch.v\n`include "fetch.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/515100461/sequential/processor.v:2: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/sequential/processor.v:3: Cannot find include file: decode.v\n`include "decode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/sequential/processor.v:4: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/sequential/processor.v:5: Cannot find include file: pcupdate.v\n`include "pcupdate.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/processor.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/515100461/sequential/processor.v:70: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d PC=%d icode=%b ifun=%b \\nrA=%b rB=%b valA=%d valB=%d\\nr4=%d r2=%d\\nr6=%d r7=%d\\n",clk,PC,icode,ifun,rA,rB,valA,valB,regmem4,regmem2,regmem6,regmem7);\n  ^~~~~~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module proc_tb;

reg clk=0;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
reg [2:0]status;
wire inst_valid, mem_error;
wire [3:0] rA,rB,icode,ifun;
wire signed [63:0] valA,valB,valC,valP,valM,valE;
wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire cnd,hlt;
wire [63:0] pcupd;
fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC,hlt,inst_valid,mem_error);
execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);
decode uut2(icode,clk,rA,rB,cnd,valE,valM,regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,regmem15,valA,valB);
memory uut4(clk,icode,valE,valP,valA,valM);
pcupdate uut5(clk,valP,valC,valM,cnd,icode,pcupd);

initial 
begin

    PC = 64'd1;
    clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
end
 always@(*)
 begin
   if(hlt==1) 
   begin
   status = 2'b01;
    $display("status=%d Halt has occured!",status);
    $finish;
   end
   if(mem_error==1) 
   begin
   status = 2'b10;
   $display("status=%d memory error has occured!",status);
   $finish;
   end
   if(inst_valid==0) 
   begin 
     status = 2'b11;
     $display("status=%d instr invalid error has occured!",status);
     $finish;
   end
   else  status = 2'b00;
 end   
 
always@(negedge clk) PC = pcupd;



initial 

  $monitor("clk=%d PC=%d icode=%b ifun=%b \nrA=%b rB=%b valA=%d valB=%d\nr4=%d r2=%d\nr6=%d r7=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,regmem4,regmem2,regmem6,regmem7);

endmodule
module proc_tb;


reg clk=0;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
reg [2:0]status;
wire inst_valid, mem_error;
wire [3:0] rA,rB,icode,ifun;
wire signed [63:0] valA,valB,valC,valP,valM,valE;
wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire cnd,hlt;
wire [63:0] pcupd;
fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC,hlt,inst_valid,mem_error);
execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);
decode uut2(icode,clk,rA,rB,cnd,valE,valM,regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,regmem15,valA,valB);
memory uut4(clk,icode,valE,valP,valA,valM);
pcupdate uut5(clk,valP,valC,valM,cnd,icode,pcupd);

initial 
begin

    PC = 64'd1;
    clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
end
 always@(*)
 begin
   if(hlt==1) 
   begin
   status = 2'b01;
    $display("status=%d Halt has occured!",status);
    $finish;
   end
   if(mem_error==1) 
   begin
   status = 2'b10;
   $display("status=%d memory error has occured!",status);
   $finish;
   end
   if(inst_valid==0) 
   begin 
     status = 2'b11;
     $display("status=%d instr invalid error has occured!",status);
     $finish;
   end
   else  status = 2'b00;
 end   
 
always@(negedge clk) PC = pcupd;



initial 

  $monitor("clk=%d PC=%d icode=%b ifun=%b \nrA=%b rB=%b valA=%d valB=%d\nr4=%d r2=%d\nr6=%d r7=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,regmem4,regmem2,regmem6,regmem7);

endmodule