data/full_repos/permissive/449071180/tb_digit_store.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:35: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:39: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:42: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:57: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:59: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:65: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:67: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:69: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:74: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:76: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:81: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:83: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:88: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_digit_store.v:90: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_digit_store.v:8: Cannot find file containing module: \'digit_store\'\ndigit_store port_map(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/digit_store\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/digit_store.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/digit_store.sv\n             digit_store\n             digit_store.v\n             digit_store.sv\n             obj_dir/digit_store\n             obj_dir/digit_store.v\n             obj_dir/digit_store.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_digit_store();
reg clk_test,set_test,reset_test,left_shift_test,right_shift_test,up_shift_test,down_shift_test;
reg [2:0] user_input_test;
wire out_up_test,out_down_test,out_left_test,out_right_test,data_out_test;

integer input_test;

digit_store port_map(
.clk(clk_test),
.set(set_test),
.reset(reset_test),
.left_shift(left_shift_test),
.right_shift(right_shift_test),
.up_shift(up_shift_test),
.down_shift(down_shift_test),
.user_input(user_input_test),
.out_up(out_up_test),
.out_down(out_down_test),
.out_left(out_left_test),
.out_right(out_right_test),
.data_out(data_out_test)
);

initial begin 
clk_test = 0;
set_test = 0;
reset_test = 0;
left_shift_test= 0;
right_shift_test = 0;
up_shift_test= 0;
down_shift_test = 0;
user_input_test = 3'b111;

reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;

set_test = 1;
#5;
set_test = 0;

end

always begin







for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
up_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;

end

up_shift_test = 0;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;


for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
down_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;
end

user_input_test = 3'b010;
#5;
set_test = 1;
#5;
set_test = 0;

for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
right_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;
end




end
endmodule
module tb_digit_store();

reg clk_test,set_test,reset_test,left_shift_test,right_shift_test,up_shift_test,down_shift_test;
reg [2:0] user_input_test;
wire out_up_test,out_down_test,out_left_test,out_right_test,data_out_test;

integer input_test;

digit_store port_map(
.clk(clk_test),
.set(set_test),
.reset(reset_test),
.left_shift(left_shift_test),
.right_shift(right_shift_test),
.up_shift(up_shift_test),
.down_shift(down_shift_test),
.user_input(user_input_test),
.out_up(out_up_test),
.out_down(out_down_test),
.out_left(out_left_test),
.out_right(out_right_test),
.data_out(data_out_test)
);

initial begin 
clk_test = 0;
set_test = 0;
reset_test = 0;
left_shift_test= 0;
right_shift_test = 0;
up_shift_test= 0;
down_shift_test = 0;
user_input_test = 3'b111;

reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
#5;

set_test = 1;
#5;
set_test = 0;

end

always begin







for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
up_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;

end

up_shift_test = 0;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;


for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
down_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;
end

user_input_test = 3'b010;
#5;
set_test = 1;
#5;
set_test = 0;

for (input_test = 0; input_test < 4; input_test = input_test + 1) begin 
right_shift_test = 1;
#5;
clk_test =1;
#5;
clk_test = 0;
end




end
endmodule