data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk1x_2x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk1x_2x.v:72: Cannot find file containing module: 'phasedet_ck1x'\nphasedet_ck1x   phasedet_ck1xi\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x.sv\n             phasedet_ck1x\n             phasedet_ck1x.v\n             phasedet_ck1x.sv\n             obj_dir/phasedet_ck1x\n             obj_dir/phasedet_ck1x.v\n             obj_dir/phasedet_ck1x.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk1x_2x.v:93: Cannot find file containing module: 'fflopxe'\nfflopxe #(WIDTH) dpp1x2x (clk2x, rst2x_, phase_one_1xr, data1x, data2x);\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module convclk1x_2x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     sync1x,
     data1x,

     sync2x,
     data2x
     );

parameter WIDTH = 8;



input   rst2x_,
        rst1x_,
        clk2x,
        clk1x;

input   scanmode;

input   sync1x;
input   [WIDTH-1:0]   data1x;

output  sync2x;
output  [WIDTH-1:0]   data2x;























wire                phase_one_1xr;

phasedet_ck1x   phasedet_ck1xi
    (
     .rst1x_    (rst1x_),
     .rst2x_    (rst2x_),
     .clk2x     (clk2x),
     .clk1x     (clk1x),

     .scanmode  (scanmode),

     .phaseout  (phase_one_1xr)
     );

reg     sync2x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) sync2x <= 1'b0;
    else if(phase_one_1xr) sync2x <= sync1x;
    else sync2x <= 1'b0;
    end

wire    [WIDTH-1:0]   data2x;
fflopxe #(WIDTH) dpp1x2x (clk2x, rst2x_, phase_one_1xr, data1x, data2x);

endmodule
module convclk1x_2x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     sync1x,
     data1x,

     sync2x,
     data2x
     );


parameter WIDTH = 8;



input   rst2x_,
        rst1x_,
        clk2x,
        clk1x;

input   scanmode;

input   sync1x;
input   [WIDTH-1:0]   data1x;

output  sync2x;
output  [WIDTH-1:0]   data2x;























wire                phase_one_1xr;

phasedet_ck1x   phasedet_ck1xi
    (
     .rst1x_    (rst1x_),
     .rst2x_    (rst2x_),
     .clk2x     (clk2x),
     .clk1x     (clk1x),

     .scanmode  (scanmode),

     .phaseout  (phase_one_1xr)
     );

reg     sync2x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) sync2x <= 1'b0;
    else if(phase_one_1xr) sync2x <= sync1x;
    else sync2x <= 1'b0;
    end

wire    [WIDTH-1:0]   data2x;
fflopxe #(WIDTH) dpp1x2x (clk2x, rst2x_, phase_one_1xr, data1x, data2x);

endmodule