data/full_repos/permissive/463439324/keygen/inv.v
1: b'%Error: data/full_repos/permissive/463439324/keygen/inv.v:270: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f_times_g0 ( f[0], f[1],g0[0],g0[1],fg0[0],fg0[1]);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0.v\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0.sv\n             f0_times_g0\n             f0_times_g0.v\n             f0_times_g0.sv\n             obj_dir/f0_times_g0\n             obj_dir/f0_times_g0.v\n             obj_dir/f0_times_g0.sv\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:271: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f0_times_g (f0[0],f0[1], g[0],g [1],gf0[0],gf0[1]);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:273: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 v_times_g0 (v_s1[0],v_s1[1],  g0[0],  g0[1],vg0[0],vg0[1]);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:274: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f0_times_r (  f0[0],  f0[1],r_s1[0],r_s1[1],rf0[0],rf0[1]);\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/inv.v:170: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                     : ... In instance r3_inverse\n            state <= 3\'d0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module inv(
    clk,
    s,
    pass_in,
    start_in,
    delta_in,
    vrfg_in,
    pass_out,
    start_out,
    delta_out,
    vrfg_out
);
    input                    clk;
    input                    s;
    input                    pass_in;
    input                    start_in;
    input      signed [10:0] delta_in;
    input             [7:0]  vrfg_in;
    output reg               pass_out;
    output reg               start_out;
    output reg signed [10:0] delta_out;
    output            [7:0]  vrfg_out;

    wire [1:0] v, r, f, g; 
    reg        start_s1, start_s2;
    reg        case1;
    reg  [1:0] f0, g0;
    reg  [1:0] f_s1, f_s2, f_out;
    reg  [1:0] g_s1, g_s2, g_out;
    reg  [1:0] v_s1, v_s2, v_s3, v_out;
    reg  [1:0] r_s1, r_s2, r_out;
    wire [1:0] fg0, gf0, vg0, rf0;
    reg  [1:0] fg0_r, gf0_r, vg0_r, rf0_r;
    reg  [1:0] fg, vr;
    reg        pass_s1, pass_s2;

    f0_times_g0 f_times_g0 ( f[0], f[1],g0[0],g0[1],fg0[0],fg0[1]);
    f0_times_g0 f0_times_g (f0[0],f0[1], g[0],g [1],gf0[0],gf0[1]);

    f0_times_g0 v_times_g0 (v_s1[0],v_s1[1],  g0[0],  g0[1],vg0[0],vg0[1]);
    f0_times_g0 f0_times_r (  f0[0],  f0[1],r_s1[0],r_s1[1],rf0[0],rf0[1]);

    assign v = vrfg_in[7:6];
    assign r = vrfg_in[5:4];
    assign f = vrfg_in[3:2];
    assign g = vrfg_in[1:0];

    assign vrfg_out[7:6] = v_out;
    assign vrfg_out[5:4] = r_out;
    assign vrfg_out[3:2] = f_out;
    assign vrfg_out[1:0] = g_out;



    always @(posedge clk ) begin
        pass_s1 <= pass_in;
        pass_s2 <= pass_s1;
        pass_out <= pass_s2;
    end


    always @(posedge clk ) begin
        if (start_in) begin
            fg0_r <= 0;
            gf0_r <= 0;
        end else begin
            fg0_r <= fg0;
            gf0_r <= gf0;
        end
        
        vg0_r <= vg0;
        rf0_r <= rf0;
    end


    always@(*)
    begin
	    case({fg0_r, gf0_r, case1})
            5'b00010: fg = 2'b01;
            5'b00110: fg = 2'b11;
            5'b01000: fg = 2'b11;
            5'b01110: fg = 2'b01;
            5'b11000: fg = 2'b01;
            5'b11010: fg = 2'b11;
            5'b00011: fg = 2'b11;
            5'b00111: fg = 2'b01;
            5'b01001: fg = 2'b01;
            5'b01111: fg = 2'b11;
            5'b11001: fg = 2'b11;
            5'b11011: fg = 2'b01;
	    	default: fg = 2'b00;
	    endcase
    end


    always@(*)
    begin
        case({vg0_r, rf0_r, case1})
            5'b00010: vr = 2'b01;
            5'b00110: vr = 2'b11;
            5'b01000: vr = 2'b11;
            5'b01110: vr = 2'b01;
            5'b11000: vr = 2'b01;
            5'b11010: vr = 2'b11;
            5'b00011: vr = 2'b11;
            5'b00111: vr = 2'b01;
            5'b01001: vr = 2'b01;
            5'b01111: vr = 2'b11;
            5'b11001: vr = 2'b11;
            5'b11011: vr = 2'b01;
	    	default: vr = 2'b00;
	    endcase
    end


    always @(posedge clk ) begin
        f_s1 <= f;
        f_s2 <= f_s1;
        if (s && pass_s2) begin
            f_out <= f_s2;
        end else if (case1) begin
            f_out <= g_s2;
        end else begin
            f_out <= f_s2;
        end
    end


    always @(posedge clk ) begin
        g_s1 <= g;
        g_s2 <= g_s1;
        if (s && pass_s2) begin
            g_out <= g_s2;
        end else begin
            g_out <= fg;
        end
    end


    always @(posedge clk ) begin
        v_s1 <= v;
        v_s2 <= v_s1;
        if (case1) begin
            v_s3 <= r_s2;
        end else begin
            v_s3 <= v_s2;
        end

        if (s && pass_s2) begin
            v_out <= v_s2;
        end else if (start_s2) begin
            v_out <= 0;
            
        end else if (s == 0 && pass_s2 && f0 == 2'b11) begin
            if (v_s3 == 2'b01) begin
                v_out <= 2'b11;
            end else if (v_s3 == 2'b11) begin
                v_out <= 2'b01;
            end else begin
                v_out <= v_s3;
            end
            
        end else begin
            v_out <= v_s3;
        end
    end


    always @(posedge clk ) begin
        r_s1 <= r;
        r_s2 <= r_s1;
        if (s && pass_s2) begin
            r_out <= r_s2;
        end else begin
            r_out <= vr;
        end
    end


    always @(posedge clk ) begin
        start_s1 <= start_in;
        start_s2 <= start_s1;
        start_out <= start_s2;
    end


    always @(posedge clk ) begin
        if (start_in) begin
            f0 <= f;
            g0 <= g;
        end else begin
            f0 <= f0;
            g0 <= g0;
        end

    end


    always @(posedge clk ) begin
        if (start_s1) begin
            if (delta_in > 0 && g0[0] == 1) begin
                case1 <= 1;
            end else begin
                case1 <= 0;
            end
        end else begin
            case1 <= case1;
        end
    end


    always @(posedge clk ) begin
        if (start_s2) begin
            if (case1) begin
                delta_out <= 1 - delta_in;
            end else begin
                delta_out <= 1 + delta_in;
            end
        end else begin
            delta_out <= delta_out;
        end
    end

endmodule
module inv(
    clk,
    s,
    pass_in,
    start_in,
    delta_in,
    vrfg_in,
    pass_out,
    start_out,
    delta_out,
    vrfg_out
);

    input                    clk;
    input                    s;
    input                    pass_in;
    input                    start_in;
    input      signed [10:0] delta_in;
    input             [7:0]  vrfg_in;
    output reg               pass_out;
    output reg               start_out;
    output reg signed [10:0] delta_out;
    output            [7:0]  vrfg_out;

    wire [1:0] v, r, f, g; 
    reg        start_s1, start_s2;
    reg        case1;
    reg  [1:0] f0, g0;
    reg  [1:0] f_s1, f_s2, f_out;
    reg  [1:0] g_s1, g_s2, g_out;
    reg  [1:0] v_s1, v_s2, v_s3, v_out;
    reg  [1:0] r_s1, r_s2, r_out;
    wire [1:0] fg0, gf0, vg0, rf0;
    reg  [1:0] fg0_r, gf0_r, vg0_r, rf0_r;
    reg  [1:0] fg, vr;
    reg        pass_s1, pass_s2;

    f0_times_g0 f_times_g0 ( f[0], f[1],g0[0],g0[1],fg0[0],fg0[1]);
    f0_times_g0 f0_times_g (f0[0],f0[1], g[0],g [1],gf0[0],gf0[1]);

    f0_times_g0 v_times_g0 (v_s1[0],v_s1[1],  g0[0],  g0[1],vg0[0],vg0[1]);
    f0_times_g0 f0_times_r (  f0[0],  f0[1],r_s1[0],r_s1[1],rf0[0],rf0[1]);

    assign v = vrfg_in[7:6];
    assign r = vrfg_in[5:4];
    assign f = vrfg_in[3:2];
    assign g = vrfg_in[1:0];

    assign vrfg_out[7:6] = v_out;
    assign vrfg_out[5:4] = r_out;
    assign vrfg_out[3:2] = f_out;
    assign vrfg_out[1:0] = g_out;



    always @(posedge clk ) begin
        pass_s1 <= pass_in;
        pass_s2 <= pass_s1;
        pass_out <= pass_s2;
    end


    always @(posedge clk ) begin
        if (start_in) begin
            fg0_r <= 0;
            gf0_r <= 0;
        end else begin
            fg0_r <= fg0;
            gf0_r <= gf0;
        end
        
        vg0_r <= vg0;
        rf0_r <= rf0;
    end


    always@(*)
    begin
	    case({fg0_r, gf0_r, case1})
            5'b00010: fg = 2'b01;
            5'b00110: fg = 2'b11;
            5'b01000: fg = 2'b11;
            5'b01110: fg = 2'b01;
            5'b11000: fg = 2'b01;
            5'b11010: fg = 2'b11;
            5'b00011: fg = 2'b11;
            5'b00111: fg = 2'b01;
            5'b01001: fg = 2'b01;
            5'b01111: fg = 2'b11;
            5'b11001: fg = 2'b11;
            5'b11011: fg = 2'b01;
	    	default: fg = 2'b00;
	    endcase
    end


    always@(*)
    begin
        case({vg0_r, rf0_r, case1})
            5'b00010: vr = 2'b01;
            5'b00110: vr = 2'b11;
            5'b01000: vr = 2'b11;
            5'b01110: vr = 2'b01;
            5'b11000: vr = 2'b01;
            5'b11010: vr = 2'b11;
            5'b00011: vr = 2'b11;
            5'b00111: vr = 2'b01;
            5'b01001: vr = 2'b01;
            5'b01111: vr = 2'b11;
            5'b11001: vr = 2'b11;
            5'b11011: vr = 2'b01;
	    	default: vr = 2'b00;
	    endcase
    end


    always @(posedge clk ) begin
        f_s1 <= f;
        f_s2 <= f_s1;
        if (s && pass_s2) begin
            f_out <= f_s2;
        end else if (case1) begin
            f_out <= g_s2;
        end else begin
            f_out <= f_s2;
        end
    end


    always @(posedge clk ) begin
        g_s1 <= g;
        g_s2 <= g_s1;
        if (s && pass_s2) begin
            g_out <= g_s2;
        end else begin
            g_out <= fg;
        end
    end


    always @(posedge clk ) begin
        v_s1 <= v;
        v_s2 <= v_s1;
        if (case1) begin
            v_s3 <= r_s2;
        end else begin
            v_s3 <= v_s2;
        end

        if (s && pass_s2) begin
            v_out <= v_s2;
        end else if (start_s2) begin
            v_out <= 0;
            
        end else if (s == 0 && pass_s2 && f0 == 2'b11) begin
            if (v_s3 == 2'b01) begin
                v_out <= 2'b11;
            end else if (v_s3 == 2'b11) begin
                v_out <= 2'b01;
            end else begin
                v_out <= v_s3;
            end
            
        end else begin
            v_out <= v_s3;
        end
    end


    always @(posedge clk ) begin
        r_s1 <= r;
        r_s2 <= r_s1;
        if (s && pass_s2) begin
            r_out <= r_s2;
        end else begin
            r_out <= vr;
        end
    end


    always @(posedge clk ) begin
        start_s1 <= start_in;
        start_s2 <= start_s1;
        start_out <= start_s2;
    end


    always @(posedge clk ) begin
        if (start_in) begin
            f0 <= f;
            g0 <= g;
        end else begin
            f0 <= f0;
            g0 <= g0;
        end

    end


    always @(posedge clk ) begin
        if (start_s1) begin
            if (delta_in > 0 && g0[0] == 1) begin
                case1 <= 1;
            end else begin
                case1 <= 0;
            end
        end else begin
            case1 <= case1;
        end
    end


    always @(posedge clk ) begin
        if (start_s2) begin
            if (case1) begin
                delta_out <= 1 - delta_in;
            end else begin
                delta_out <= 1 + delta_in;
            end
        end else begin
            delta_out <= delta_out;
        end
    end

endmodule