data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:47: Cannot find file containing module: 'bw_u1_inv_2x'\nbw_u1_inv_2x ps_inv (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x.sv\n             bw_u1_inv_2x\n             bw_u1_inv_2x.v\n             bw_u1_inv_2x.sv\n             obj_dir/bw_u1_inv_2x\n             obj_dir/bw_u1_inv_2x.v\n             obj_dir/bw_u1_inv_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:50: Cannot find file containing module: 'bw_u1_muxi21_2x'\nbw_u1_muxi21_2x bs_mux1 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:55: Cannot find file containing module: 'bw_u1_muxi21_2x'\nbw_u1_muxi21_2x bs_mux2 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:60: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x ps_nand2 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:64: Cannot find file containing module: 'bw_u1_inv_2x'\nbw_u1_inv_2x ctl_inv2x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:67: Cannot find file containing module: 'bw_io_jp_bs_baseblk'\nbw_io_jp_bs_baseblk bs_baseblk (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:75: Cannot find file containing module: 'bw_u1_inv_5x'\nbw_u1_inv_5x out_inv5x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:78: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x bs_inv1x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_dq_bscan.v:81: Cannot find file containing module: 'bw_u1_nor2_1x'\nbw_u1_nor2_1x ctl_nor1x (\n^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module bw_io_jp_sstl_dq_bscan(se ,mode_ctl ,bypass_enable ,clock_dr ,in
      ,ps_in ,bsr_so ,ps_select ,out ,bypass ,shift_dr ,bsr_si ,
     update_dr );
output		bsr_so ;
output		out ;
output		bypass ;
input		se ;
input		mode_ctl ;
input		bypass_enable ;
input		clock_dr ;
input		in ;
input		ps_in ;
input		ps_select ;
input		shift_dr ;
input		bsr_si ;
input		update_dr ;
 
wire		net39 ;
wire		net47 ;
wire		net51 ;
wire		net58 ;
wire		net60 ;
wire		net63 ;
wire		net66 ;
 
 
bw_u1_inv_2x ps_inv (
     .z               (bypass ),
     .a               (net63 ) );
bw_u1_muxi21_2x bs_mux1 (
     .z               (net51 ),
     .d0              (net58 ),
     .d1              (ps_in ),
     .s               (ps_select ) );
bw_u1_muxi21_2x bs_mux2 (
     .z               (net47 ),
     .d0              (in ),
     .d1              (net60 ),
     .s               (net39 ) );
bw_u1_nand2_1x ps_nand2 (
     .z               (net63 ),
     .a               (net58 ),
     .b               (bypass_enable ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net39 ),
     .a               (net66 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (net58 ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net47 ) );
bw_u1_inv_1x bs_inv1x (
     .z               (net60 ),
     .a               (net51 ) );
bw_u1_nor2_1x ctl_nor1x (
     .z               (net66 ),
     .a               (se ),
     .b               (mode_ctl ) );
endmodule
module bw_io_jp_sstl_dq_bscan(se ,mode_ctl ,bypass_enable ,clock_dr ,in
      ,ps_in ,bsr_so ,ps_select ,out ,bypass ,shift_dr ,bsr_si ,
     update_dr );

output		bsr_so ;
output		out ;
output		bypass ;
input		se ;
input		mode_ctl ;
input		bypass_enable ;
input		clock_dr ;
input		in ;
input		ps_in ;
input		ps_select ;
input		shift_dr ;
input		bsr_si ;
input		update_dr ;
 
wire		net39 ;
wire		net47 ;
wire		net51 ;
wire		net58 ;
wire		net60 ;
wire		net63 ;
wire		net66 ;
 
 
bw_u1_inv_2x ps_inv (
     .z               (bypass ),
     .a               (net63 ) );
bw_u1_muxi21_2x bs_mux1 (
     .z               (net51 ),
     .d0              (net58 ),
     .d1              (ps_in ),
     .s               (ps_select ) );
bw_u1_muxi21_2x bs_mux2 (
     .z               (net47 ),
     .d0              (in ),
     .d1              (net60 ),
     .s               (net39 ) );
bw_u1_nand2_1x ps_nand2 (
     .z               (net63 ),
     .a               (net58 ),
     .b               (bypass_enable ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net39 ),
     .a               (net66 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (net58 ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net47 ) );
bw_u1_inv_1x bs_inv1x (
     .z               (net60 ),
     .a               (net51 ) );
bw_u1_nor2_1x ctl_nor1x (
     .z               (net66 ),
     .a               (se ),
     .b               (mode_ctl ) );
endmodule