data/full_repos/permissive/431362747/Processor-prev-versions/Vivado Project/ImageDownSample.srcs/sources_1/new/MAR.v
1: b'%Error: Cannot find file containing module: Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n        ... Looked in:\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             data/full_repos/permissive/431362747/Processor-prev-versions/Vivado/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.v\n             obj_dir/Project/ImageDownSample.srcs/sources_1/new,data/full_repos/permissive/431362747.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/431362747/Processor-prev-versions/Vivado\n%Error: Cannot find file containing module: Project/ImageDownSample.srcs/sources_1/new/MAR.v\n%Error: Exiting due to 3 error(s)\n'
module MAR(
    input clk,
    input w_en,
    output reg [27:0] data_out,
    input [27:0] data_in,
    output reg [17:0] data_addr
    );
     always @(posedge clk)
        begin
            if (w_en==1)
                data_addr<=data_in[17:0];
                data_out<=data_in;
        end
    
endmodule
module MAR(
    input clk,
    input w_en,
    output reg [27:0] data_out,
    input [27:0] data_in,
    output reg [17:0] data_addr
    );

     always @(posedge clk)
        begin
            if (w_en==1)
                data_addr<=data_in[17:0];
                data_out<=data_in;
        end
    
endmodule