data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:39: Cannot find include file: c_functions.v\n`include "c_functions.v"    \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/verif/router,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/verif/router,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/verif/router,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:40: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:41: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:42: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:64: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:66: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:66: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:68: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:70: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:75: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:76: Define or directive not defined: \'`TOPOLOGY_FBFLY\'\n   parameter topology       = `TOPOLOGY_FBFLY;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter topology       = `TOPOLOGY_FBFLY;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:92: Define or directive not defined: \'`TOPOLOGY_MESH\'\n     = (topology == `TOPOLOGY_MESH) ?\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:92: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (topology == `TOPOLOGY_MESH) ?\n                                  ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/router/ugal_sniffer.v:94: Define or directive not defined: \'`TOPOLOGY_FBFLY\'\n       (topology == `TOPOLOGY_FBFLY) ?\n                    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module ugal_sniffer(

   credit_count,

   clk, reset, flit_ctrl, flow_ctrl
   );

`include "c_functions.v"   
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"


   parameter buffer_size 	   = 16;

   parameter num_message_classes   = 1;
   

   parameter num_resource_classes  = 2;
   

   localparam num_packet_classes   = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class 	   = 1;
   

   localparam num_vcs 		   = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width 	   = clogb(num_vcs);

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;

   localparam flow_ctrl_width 	     = 1 + vc_idx_width;
   parameter reset_type = `RESET_TYPE_ASYNC;
   parameter topology 	     = `TOPOLOGY_FBFLY;

   parameter num_nodes 		     = 64;
   

   parameter num_dimensions 	     = 2;
   

   parameter num_nodes_per_router    = 4;

   localparam num_routers
 				     = (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;

   localparam num_routers_per_dim    = croot(num_routers, num_dimensions);

   localparam num_neighbors_per_dim
     = (topology == `TOPOLOGY_MESH) ?
       2 :
       (topology == `TOPOLOGY_FBFLY) ?
       (num_routers_per_dim - 1) :
       -1;

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   
   localparam credit_count_width  = clogb(buffer_size)+1;
   
   
   
   input clk;
   input reset;
   input [0:(num_ports-num_nodes_per_router)*flit_ctrl_width-1] flit_ctrl;

   input [0:(num_ports-num_nodes_per_router)*flow_ctrl_width-1] flow_ctrl;
   
   output [0:(num_ports-num_nodes_per_router)*credit_count_width-1] credit_count;

   generate
      genvar port;
      for(port = 0; port<num_ports-num_nodes_per_router; port=port+1)
	begin:ports
	   wire [0:credit_count_width-1] count_q;
	   wire [0:credit_count_width-1] count_s;
	   c_dff
		 #(

		   .width		(credit_count_width),
		   .reset_type		(reset_type))
	   credit_ff
	     (

		  .q			(count_q[0:credit_count_width-1]),

		  .clk			(clk),
		  .reset		(reset),
		  .active		(active),
		  .d			(count_s[0:credit_count_width-1]));
	   assign count_s  = count_q
			     +flit_ctrl[port*flit_ctrl_width]
	     -flow_ctrl[port*flow_ctrl_width];
	   assign credit_count [port*credit_count_width:(port+1)*credit_count_width-1] = count_q[0:credit_count_width-1];
	   
	end
   endgenerate

   
endmodule
module ugal_sniffer(

   credit_count,

   clk, reset, flit_ctrl, flow_ctrl
   );


`include "c_functions.v"   
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"


   parameter buffer_size 	   = 16;

   parameter num_message_classes   = 1;
   

   parameter num_resource_classes  = 2;
   

   localparam num_packet_classes   = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class 	   = 1;
   

   localparam num_vcs 		   = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width 	   = clogb(num_vcs);

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;

   localparam flow_ctrl_width 	     = 1 + vc_idx_width;
   parameter reset_type = `RESET_TYPE_ASYNC;
   parameter topology 	     = `TOPOLOGY_FBFLY;

   parameter num_nodes 		     = 64;
   

   parameter num_dimensions 	     = 2;
   

   parameter num_nodes_per_router    = 4;

   localparam num_routers
 				     = (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;

   localparam num_routers_per_dim    = croot(num_routers, num_dimensions);

   localparam num_neighbors_per_dim
     = (topology == `TOPOLOGY_MESH) ?
       2 :
       (topology == `TOPOLOGY_FBFLY) ?
       (num_routers_per_dim - 1) :
       -1;

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   
   localparam credit_count_width  = clogb(buffer_size)+1;
   
   
   
   input clk;
   input reset;
   input [0:(num_ports-num_nodes_per_router)*flit_ctrl_width-1] flit_ctrl;

   input [0:(num_ports-num_nodes_per_router)*flow_ctrl_width-1] flow_ctrl;
   
   output [0:(num_ports-num_nodes_per_router)*credit_count_width-1] credit_count;

   generate
      genvar port;
      for(port = 0; port<num_ports-num_nodes_per_router; port=port+1)
	begin:ports
	   wire [0:credit_count_width-1] count_q;
	   wire [0:credit_count_width-1] count_s;
	   c_dff
		 #(

		   .width		(credit_count_width),
		   .reset_type		(reset_type))
	   credit_ff
	     (

		  .q			(count_q[0:credit_count_width-1]),

		  .clk			(clk),
		  .reset		(reset),
		  .active		(active),
		  .d			(count_s[0:credit_count_width-1]));
	   assign count_s  = count_q
			     +flit_ctrl[port*flit_ctrl_width]
	     -flow_ctrl[port*flow_ctrl_width];
	   assign credit_count [port*credit_count_width:(port+1)*credit_count_width-1] = count_q[0:credit_count_width-1];
	   
	end
   endgenerate

   
endmodule