data/full_repos/permissive/441359809/src/yosys/tests/arch/common/memory_attributes/attributes_test.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/arch/common/memory_attributes/attributes_test.v:24: Multiple top level modules\n                                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                          : ... Top module \'block_ram\'\nmodule block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10)\n       ^~~~~~~~~\n                                                                                                                          : ... Top module \'distributed_ram\'\nmodule distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)\n       ^~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'distributed_ram_manual\'\nmodule distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'distributed_ram_manual_syn\'\nmodule distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
   (input  wire                      write_enable, clk,
    input  wire  [DATA_WIDTH-1:0]    data_in,
    input  wire  [ADDRESS_WIDTH-1:0] address_in,
    output wire  [DATA_WIDTH-1:0]    data_out);

   localparam WORD  = (DATA_WIDTH-1);
   localparam DEPTH = (2**ADDRESS_WIDTH-1);

   reg [WORD:0] data_out_r;
   reg [WORD:0] memory [0:DEPTH];

   always @(posedge clk) begin
      if (write_enable)
        memory[address_in] <= data_in;
      data_out_r <= memory[address_in];
   end

   assign data_out = data_out_r;
endmodule
module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
   (input  wire                      write_enable, clk,
    input  wire  [DATA_WIDTH-1:0]    data_in,
    input  wire  [ADDRESS_WIDTH-1:0] address_in,
    output wire  [DATA_WIDTH-1:0]    data_out);


   localparam WORD  = (DATA_WIDTH-1);
   localparam DEPTH = (2**ADDRESS_WIDTH-1);

   reg [WORD:0] data_out_r;
   reg [WORD:0] memory [0:DEPTH];

   always @(posedge clk) begin
      if (write_enable)
        memory[address_in] <= data_in;
      data_out_r <= memory[address_in];
   end

   assign data_out = data_out_r;
endmodule