data/full_repos/permissive/524567962/designs/Adder/Half_Adder.sv
data/verilator_xmls/da7e1005-7280-4999-ab94-2f43da28b743.xml
module Half_Adder(
  input logic   a, b,

  output logic  y, cout

);

assign y = a ^ b;
assign cout = a & b;

endmodule
module Half_Adder(
  input logic   a, b,

  output logic  y, cout

);


assign y = a ^ b;
assign cout = a & b;

endmodule