data/full_repos/permissive/432564927/Lab1 (Verilog)/Lab1_Unal (Verilog)/Unal_Lab1.srcs/sim_1/new/posEdgeDFFTest.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab1_Unal\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.sv\n             (Verilog)/Lab1_Unal\n             (Verilog)/Lab1_Unal.v\n             (Verilog)/Lab1_Unal.sv\n             obj_dir/(Verilog)/Lab1_Unal\n             obj_dir/(Verilog)/Lab1_Unal.v\n             obj_dir/(Verilog)/Lab1_Unal.sv\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sim_1/new,data/full_repos/permissive/432564927\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sim_1/new/posEdgeDFFTest.v\n%Error: Exiting due to 4 error(s)\n'
module posEdgeDFFTest;

    reg [2:0] currentState;
    reg clk;
    reg reset;

    wire [2:0] nextState;
    
    posEdgeDFF uut(currentState,clk,reset,nextState);
    initial begin
        clk = 0;
            forever #10 clk = ~clk;
    end
    initial begin
        reset=1;
        currentState <= 0;
        #100;
        reset=0;
        currentState <= 1;
        #100;
        currentState <= 0;
        #100;
        currentState <=1;
    end
endmodule
module posEdgeDFFTest;


    reg [2:0] currentState;
    reg clk;
    reg reset;

    wire [2:0] nextState;
    
    posEdgeDFF uut(currentState,clk,reset,nextState);
    initial begin
        clk = 0;
            forever #10 clk = ~clk;
    end
    initial begin
        reset=1;
        currentState <= 0;
        #100;
        reset=0;
        currentState <= 1;
        #100;
        currentState <= 0;
        #100;
        currentState <=1;
    end
endmodule