data/full_repos/permissive/52836497/sha1_guesser_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52836497/sha1_guesser_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52836497/sha1_guesser_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/52836497/sha1_guesser_tb.v:18: Cannot find file containing module: \'sha1_guesser\'\nsha1_guesser #(.NONCE_SIZE(16)) sha1_guesser (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52836497,data/full_repos/permissive/52836497/sha1_guesser\n             data/full_repos/permissive/52836497,data/full_repos/permissive/52836497/sha1_guesser.v\n             data/full_repos/permissive/52836497,data/full_repos/permissive/52836497/sha1_guesser.sv\n             sha1_guesser\n             sha1_guesser.v\n             sha1_guesser.sv\n             obj_dir/sha1_guesser\n             obj_dir/sha1_guesser.v\n             obj_dir/sha1_guesser.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbed;

integer ticks;

reg clk, start;
wire hash, match, done;
wire [159:0] context_initial = {32'h67452301, 32'hEFCDAB89, 32'h98BADCFE, 32'h10325476, 32'hC3D2E1F0};
wire [15:0] nonce;
wire [511:0] block_out;
wire [159:0] context_out;


wire [511:0] block = {"abc", 8'h80, 416'd0, 64'd24};
wire [159:0] target = { 160'hFF };
wire [159:0] target_mask = { 160'hFF };


sha1_guesser #(.NONCE_SIZE(16)) sha1_guesser (
    .clk(clk),
    .start(start),
    .context_in(context_initial),
    .block_in(block),
    .target(target),
    .target_mask(target_mask),
    .hash(hash),
    .match(match),
    .done(done),
    .nonce(nonce),
    .block_out(block_out),
    .context_out(context_out));

initial
begin
  ticks = 0;
  $display("starting");

  tick;
  start = 1'b1;
  tick;
  tick;
  tick;
  start = 1'b0;
  while (!done) begin
    tick;
  end
  tick;
  $display("done");
  $finish;
end

task tick;
begin
  #1;
  clk = 1;
  #1;
  clk = 0;
  ticks = ticks + 1;
  dumpstate;
end
endtask

task dumpstate;
begin
  if (match) begin
    $display("%d %b %b %b %h %h", ticks, start, match, done, nonce, context_out);
  end










end
endtask


endmodule
module testbed;


integer ticks;

reg clk, start;
wire hash, match, done;
wire [159:0] context_initial = {32'h67452301, 32'hEFCDAB89, 32'h98BADCFE, 32'h10325476, 32'hC3D2E1F0};
wire [15:0] nonce;
wire [511:0] block_out;
wire [159:0] context_out;


wire [511:0] block = {"abc", 8'h80, 416'd0, 64'd24};
wire [159:0] target = { 160'hFF };
wire [159:0] target_mask = { 160'hFF };


sha1_guesser #(.NONCE_SIZE(16)) sha1_guesser (
    .clk(clk),
    .start(start),
    .context_in(context_initial),
    .block_in(block),
    .target(target),
    .target_mask(target_mask),
    .hash(hash),
    .match(match),
    .done(done),
    .nonce(nonce),
    .block_out(block_out),
    .context_out(context_out));

initial
begin
  ticks = 0;
  $display("starting");

  tick;
  start = 1'b1;
  tick;
  tick;
  tick;
  start = 1'b0;
  while (!done) begin
    tick;
  end
  tick;
  $display("done");
  $finish;
end

task tick;
begin
  #1;
  clk = 1;
  #1;
  clk = 0;
  ticks = ticks + 1;
  dumpstate;
end
endtask

task dumpstate;
begin
  if (match) begin
    $display("%d %b %b %b %h %h", ticks, start, match, done, nonce, context_out);
  end










end
endtask


endmodule