data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv
1: b'%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:1: Cannot find include file: ../hdl/cacheline_adaptor.sv\n`include "../hdl/cacheline_adaptor.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl,data/full_repos/permissive/444559342/../hdl/cacheline_adaptor.sv\n             data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl,data/full_repos/permissive/444559342/../hdl/cacheline_adaptor.sv.v\n             data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl,data/full_repos/permissive/444559342/../hdl/cacheline_adaptor.sv.sv\n             ../hdl/cacheline_adaptor.sv\n             ../hdl/cacheline_adaptor.sv.v\n             ../hdl/cacheline_adaptor.sv.sv\n             obj_dir/../hdl/cacheline_adaptor.sv\n             obj_dir/../hdl/cacheline_adaptor.sv.v\n             obj_dir/../hdl/cacheline_adaptor.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:8: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = (clk === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:27: syntax error, unexpected \'@\', expecting \';\'\n    default clocking cb @(posedge clk);\n                        ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:30: syntax error, unexpected endclocking\n    endclocking\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:46: Unsupported or unknown PLI call: $exit\n            $exit;\n            ^~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:46: syntax error, unexpected ${ignored-bbox-sys}\n            $exit;\n                 ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:57: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.read_i <= 1\'b0;\n                  ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:58: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.write_i <= 1\'b0;\n                   ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:59: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.reset_n <= 1\'b0;\n                   ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:60: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.resp_i <= 1\'b0;\n                  ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:64: syntax error, unexpected $fdisplay\n            $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:71: Unsupported: Static in this context\n        static integer it;\n        ^~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:72: Unsupported: Static in this context\n        static bit [255:0] readline;\n        ^~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:73: Unsupported: Static in this context\n        static bit [4:0] delay;\n        ^~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:74: syntax error, unexpected \'@\'\n        @(cb iff ~(cb.read_o | cb.write_o));\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:75: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.read_i <= 1\'b1;\n                  ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:76: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.write_i <= 1\'b0;\n                   ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:77: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.reset_n <= 1\'b1;\n                   ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:78: syntax error, unexpected <=, expecting IDENTIFIER\n        cb.address_i <= $urandom;\n                     ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:78: Unsupported or unknown PLI call: $urandom\n        cb.address_i <= $urandom;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:80: syntax error, unexpected \'[\', expecting IDENTIFIER\n            readline[32*it +: 32] = $urandom;\n                    ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:80: Unsupported or unknown PLI call: $urandom\n            readline[32*it +: 32] = $urandom;\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:82: syntax error, unexpected \'=\', expecting IDENTIFIER\n        delay = $urandom;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:82: Unsupported or unknown PLI call: $urandom\n        delay = $urandom;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:88: syntax error, unexpected $fdisplay\n                $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:94: syntax error, unexpected <=, expecting IDENTIFIER\n            cb.burst_i <= readline[64*it +: 64];\n                       ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:95: syntax error, unexpected <=, expecting IDENTIFIER\n            cb.read_i <= 1\'b0;\n                      ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:103: syntax error, unexpected $fdisplay\n                $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:109: syntax error, unexpected $fdisplay\n                $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:115: syntax error, unexpected $fdisplay\n            $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:124: Unsupported: Static in this context\n        static integer it;\n        ^~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:125: Unsupported: Static in this context\n        static bit [4:0] delay;\n        ^~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:126: syntax error, unexpected \'@\'\n        @(cb iff ~(cb.read_o | cb.write_o));\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:130: Unsupported or unknown PLI call: $urandom\n        cb.address_i <= $urandom;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:132: Unsupported or unknown PLI call: $urandom\n            line_i[32*it +: 32] = $urandom;\n                                  ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:134: Unsupported or unknown PLI call: $urandom\n        delay = $urandom;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:136: syntax error, unexpected \'@\'\n        @(cb iff cb.write_o);\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:142: syntax error, unexpected ##\n            ##1;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:146: syntax error, unexpected ##\n            ##1;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:153: syntax error, unexpected \'@\'\n        @(cb iff cb.resp_o);\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:163: syntax error, unexpected ##\n        ##1\n        ^~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:167: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:173: syntax error, unexpected iff, expecting \')\' or \',\' or or\n    always @(cb iff cb.write_o && cb.read_o && reset_n) begin\n                ^~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:175: syntax error, unexpected $fdisplay\n        $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:180: syntax error, unexpected $fdisplay\n        $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:182: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/444559342/mp1/cacheline_adaptor/hvl/testbench.sv:198: syntax error, unexpected $fdisplay\n        $error("%s", s); $fdisplay(fd, "%s", s); $fdisplay(lfd, "%s", s);\n                         ^~~~~~~~~\n%Error: Cannot continue\n'
module testbench;
    string s;
    int fd, lfd;

    bit clk;
    always #5 clk = (clk === 1'b0);
    bit reset_n, read_i, write_i, resp_o, read_o, write_o, resp_i;
    bit [255:0] line_i, line_o;
    bit [63:0] burst_i, burst_o;
    bit [31:0] address_i, address_o;



    int read_o_counter = 0;
    int write_o_counter = 0;
    always_ff @(posedge clk) begin
        read_o_counter <= read_o_counter + cb.read_o;
    end
    always_ff @(posedge clk) begin
        write_o_counter <= write_o_counter + cb.write_o;
    end

    cacheline_adaptor dut(.*);

    default clocking cb @(posedge clk);
        input line_o, resp_o, burst_o, address_o, read_o, write_o;
        output reset_n, line_i, address_i, read_i, write_i, burst_i, resp_i;
    endclocking

    initial begin








        fd = $fopen("./student_log.txt", "w");
        lfd = $fopen("./log.txt", "w");
        if (fd == 0 || lfd == 0) begin
            $error("%s %0d: Unable to open log file(s)",
                        `__FILE__, `__LINE__);
            $exit;
        end

    end

    final begin
        $fclose(fd);
        $fclose(lfd);
    end

    task reset;
        cb.read_i <= 1'b0;
        cb.write_i <= 1'b0;
        cb.reset_n <= 1'b0;
        cb.resp_i <= 1'b0;
        ##10;
        assert((cb.read_o == 1'b0) && cb.write_o == 1'b0) else begin
            $sformat(s, "@%0t TB: memory access during reset", $time);
            `LOG;
        end
        cb.reset_n <= 1'b1;
        ##10;
    endtask

    task read_test;
        static integer it;
        static bit [255:0] readline;
        static bit [4:0] delay;
        @(cb iff ~(cb.read_o | cb.write_o));
        cb.read_i <= 1'b1;
        cb.write_i <= 1'b0;
        cb.reset_n <= 1'b1;
        cb.address_i <= $urandom;
        for (it = 0; it < 8; ++it) begin
            readline[32*it +: 32] = $urandom;
        end
        delay = $urandom;

        @(cb iff cb.read_o);
        repeat (delay) begin
            assert(cb.address_o == address_i) else begin
                $sformat(s, "@%0t TB: mismatch in read addresses", $time);
                `LOG;
            end
            ##1;
        end
        for (it = 0; it < 4; ++it) begin
            cb.resp_i <= 1'b1;
            cb.burst_i <= readline[64*it +: 64];
            cb.read_i <= 1'b0;
            ##1;
        end
        cb.resp_i <= 1'b0;

        @(cb iff cb.resp_o);
        assert((read_o_counter - delay - 1) == 4) else begin
            $sformat(s, "@%0t TB: read_o assertion mismatch", $time);
                `LOG;
        end
        repeat (5) begin
            assert(cb.line_o == readline) else begin
                $sformat(s, "@%0t TB: read / expected\n\t%x\n\t%x", $time,
                    cb.line_o, readline);
                `LOG;
            end
        end
        ##1
        if (cb.resp_o) begin
            $sformat(s, "@%0t TB: resp_o raised for too long on read", $time);
            `LOG;
        end

        read_o_counter <= '0;

    endtask : read_test

    bit [255:0] writeline;
    task write_test;
        static integer it;
        static bit [4:0] delay;
        @(cb iff ~(cb.read_o | cb.write_o));
        cb.read_i <= 1'b0;
        cb.write_i <= 1'b1;
        cb.reset_n <= 1'b1;
        cb.address_i <= $urandom;
        for (it = 0; it < 8; ++it) begin
            line_i[32*it +: 32] = $urandom;
        end
        delay = $urandom;

        @(cb iff cb.write_o);
        for (int it = 0; it < delay; ++it) begin
            assert(cb.address_o == address_i) else begin
                $sformat(s, "@%0t TB: mismatch in read addresses", $time);
                `LOG;
            end
            ##1;
        end
        ##1 cb.resp_i <= 1'b1;
        for (it = 0; it < 4; ++it) begin
            ##1;
            cb.resp_i <= 1'b1;
            cb.write_i <= 1'b0;
            writeline[64*it +: 64] <= cb.burst_o;
        end
        cb.resp_i <= 1'b0;

        @(cb iff cb.resp_o);
        assert((write_o_counter - delay - 2) == 4) else begin
            $sformat(s, "@%0t TB: write_o assertion mismatch", $time);
                `LOG;
        end
        assert(writeline == line_i) else begin
            $sformat(s, "@%0t TB: writeline / expected\n\t%x\n\t%x", $time,
                writeline, line_i);
            `LOG;
        end
        ##1
        if (cb.resp_o) begin
            $sformat(s, "@%0t TB: resp_o raised for too long on write", $time);
            `LOG;
        end

        write_o_counter <= '0;

    endtask : write_test

    always @(cb iff cb.write_o && cb.read_o && reset_n) begin
        $sformat(s, "@%0t TB: Simultaneous read and write to mem", $time);
        `LOG;
    end

    always @(cb iff write_i && read_i) begin
        $sformat(s, "@%0t TB: Simultaneous read and write to adaptor", $time);
        `LOG;
        $fatal("Fatal Error");
    end

    initial begin
        reset();
        $display("Starting Read Tests");
        repeat (50) read_test();
        $display("Read Tests Complete");
        $display("Starting Write Tests");
        repeat (50) write_test();
        $display("Write Tests Complete");
        $finish;
    end

    initial begin : timeout
        ##50000;
        $sformat(s, "@%0t TB: timeout", $time);
        `LOG;
        $finish;
    end

endmodule
module testbench;

    string s;
    int fd, lfd;

    bit clk;
    always #5 clk = (clk === 1'b0);
    bit reset_n, read_i, write_i, resp_o, read_o, write_o, resp_i;
    bit [255:0] line_i, line_o;
    bit [63:0] burst_i, burst_o;
    bit [31:0] address_i, address_o;



    int read_o_counter = 0;
    int write_o_counter = 0;
    always_ff @(posedge clk) begin
        read_o_counter <= read_o_counter + cb.read_o;
    end
    always_ff @(posedge clk) begin
        write_o_counter <= write_o_counter + cb.write_o;
    end

    cacheline_adaptor dut(.*);

    default clocking cb @(posedge clk);
        input line_o, resp_o, burst_o, address_o, read_o, write_o;
        output reset_n, line_i, address_i, read_i, write_i, burst_i, resp_i;
    endclocking

    initial begin








        fd = $fopen("./student_log.txt", "w");
        lfd = $fopen("./log.txt", "w");
        if (fd == 0 || lfd == 0) begin
            $error("%s %0d: Unable to open log file(s)",
                        `__FILE__, `__LINE__);
            $exit;
        end

    end

    final begin
        $fclose(fd);
        $fclose(lfd);
    end

    task reset;
        cb.read_i <= 1'b0;
        cb.write_i <= 1'b0;
        cb.reset_n <= 1'b0;
        cb.resp_i <= 1'b0;
        ##10;
        assert((cb.read_o == 1'b0) && cb.write_o == 1'b0) else begin
            $sformat(s, "@%0t TB: memory access during reset", $time);
            `LOG;
        end
        cb.reset_n <= 1'b1;
        ##10;
    endtask

    task read_test;
        static integer it;
        static bit [255:0] readline;
        static bit [4:0] delay;
        @(cb iff ~(cb.read_o | cb.write_o));
        cb.read_i <= 1'b1;
        cb.write_i <= 1'b0;
        cb.reset_n <= 1'b1;
        cb.address_i <= $urandom;
        for (it = 0; it < 8; ++it) begin
            readline[32*it +: 32] = $urandom;
        end
        delay = $urandom;

        @(cb iff cb.read_o);
        repeat (delay) begin
            assert(cb.address_o == address_i) else begin
                $sformat(s, "@%0t TB: mismatch in read addresses", $time);
                `LOG;
            end
            ##1;
        end
        for (it = 0; it < 4; ++it) begin
            cb.resp_i <= 1'b1;
            cb.burst_i <= readline[64*it +: 64];
            cb.read_i <= 1'b0;
            ##1;
        end
        cb.resp_i <= 1'b0;

        @(cb iff cb.resp_o);
        assert((read_o_counter - delay - 1) == 4) else begin
            $sformat(s, "@%0t TB: read_o assertion mismatch", $time);
                `LOG;
        end
        repeat (5) begin
            assert(cb.line_o == readline) else begin
                $sformat(s, "@%0t TB: read / expected\n\t%x\n\t%x", $time,
                    cb.line_o, readline);
                `LOG;
            end
        end
        ##1
        if (cb.resp_o) begin
            $sformat(s, "@%0t TB: resp_o raised for too long on read", $time);
            `LOG;
        end

        read_o_counter <= '0;

    endtask : read_test

    bit [255:0] writeline;
    task write_test;
        static integer it;
        static bit [4:0] delay;
        @(cb iff ~(cb.read_o | cb.write_o));
        cb.read_i <= 1'b0;
        cb.write_i <= 1'b1;
        cb.reset_n <= 1'b1;
        cb.address_i <= $urandom;
        for (it = 0; it < 8; ++it) begin
            line_i[32*it +: 32] = $urandom;
        end
        delay = $urandom;

        @(cb iff cb.write_o);
        for (int it = 0; it < delay; ++it) begin
            assert(cb.address_o == address_i) else begin
                $sformat(s, "@%0t TB: mismatch in read addresses", $time);
                `LOG;
            end
            ##1;
        end
        ##1 cb.resp_i <= 1'b1;
        for (it = 0; it < 4; ++it) begin
            ##1;
            cb.resp_i <= 1'b1;
            cb.write_i <= 1'b0;
            writeline[64*it +: 64] <= cb.burst_o;
        end
        cb.resp_i <= 1'b0;

        @(cb iff cb.resp_o);
        assert((write_o_counter - delay - 2) == 4) else begin
            $sformat(s, "@%0t TB: write_o assertion mismatch", $time);
                `LOG;
        end
        assert(writeline == line_i) else begin
            $sformat(s, "@%0t TB: writeline / expected\n\t%x\n\t%x", $time,
                writeline, line_i);
            `LOG;
        end
        ##1
        if (cb.resp_o) begin
            $sformat(s, "@%0t TB: resp_o raised for too long on write", $time);
            `LOG;
        end

        write_o_counter <= '0;

    endtask : write_test

    always @(cb iff cb.write_o && cb.read_o && reset_n) begin
        $sformat(s, "@%0t TB: Simultaneous read and write to mem", $time);
        `LOG;
    end

    always @(cb iff write_i && read_i) begin
        $sformat(s, "@%0t TB: Simultaneous read and write to adaptor", $time);
        `LOG;
        $fatal("Fatal Error");
    end

    initial begin
        reset();
        $display("Starting Read Tests");
        repeat (50) read_test();
        $display("Read Tests Complete");
        $display("Starting Write Tests");
        repeat (50) write_test();
        $display("Write Tests Complete");
        $finish;
    end

    initial begin : timeout
        ##50000;
        $sformat(s, "@%0t TB: timeout", $time);
        `LOG;
        $finish;
    end

endmodule