data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:55: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n     0: a_to_g = 8\'b1000000;   \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:56: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h79\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n     1: a_to_g = 8\'b1111001;   \n               ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:57: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h24\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 2: a_to_g = 8\'b0100100;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:58: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h30\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 3: a_to_g = 8\'b0110000;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:59: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h19\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 4: a_to_g = 8\'b0011001;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:60: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h12\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 5: a_to_g = 8\'b0010010;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:61: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 6: a_to_g = 8\'b0000010;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:62: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h78\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 7: a_to_g = 8\'b1111000;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:63: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 8: a_to_g = 8\'b0000000;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:64: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h10\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n 9: a_to_g = 8\'b0010000;   \n           ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v:65: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                                                         : ... In instance seven_segment_leds_x_8\n default: a_to_g = 8\'b11111111;   \n                 ^\n%Error: Exiting due to 11 warning(s)\n'
module seven_segment_leds_x_8(
    input [31:0] bcd_in,
    input [7:0] decimal_points,
    input clk,
    output  reg [6:0] a_to_g,
    output reg decimal_point,
    output reg [7:0] anode 
    );

wire [2:0] counter;
reg [3:0] digit;
reg [20:0] clkdiv;	
	 

assign counter = clkdiv[20:18];


always @(posedge clk)
    case(counter)
	0: {digit, decimal_point} = {bcd_in[3:0], ~decimal_points[0]};
	1: {digit, decimal_point} = {bcd_in[7:4], ~decimal_points[1]};
	2: {digit, decimal_point} = {bcd_in[11:8], ~decimal_points[2]};
	3: {digit, decimal_point} = {bcd_in[15:12], ~decimal_points[3]};
	4: {digit, decimal_point} = {bcd_in[19:16], ~decimal_points[4]};
    	5: {digit, decimal_point} = {bcd_in[23:20], ~decimal_points[5]};
    	6: {digit, decimal_point} = {bcd_in[27:24], ~decimal_points[6]};
    	7: {digit, decimal_point} = {bcd_in[31:28], ~decimal_points[7]};
     endcase


always @(posedge clk)
     case(digit)
    	0: a_to_g = 8'b1000000;
    	1: a_to_g = 8'b1111001;
	2: a_to_g = 8'b0100100;
	3: a_to_g = 8'b0110000;
	4: a_to_g = 8'b0011001;
	5: a_to_g = 8'b0010010;
	6: a_to_g = 8'b0000010;
	7: a_to_g = 8'b1111000;
	8: a_to_g = 8'b0000000;
	9: a_to_g = 8'b0010000;
	default: a_to_g = 8'b11111111;
    endcase
	  

always @(posedge clk)
    case(counter)
        0: anode = 8'b11111110;
	1: anode = 8'b11111101;
	2: anode = 8'b11111011;
	3: anode = 8'b11110111;
	4: anode = 8'b11101111;
        5: anode = 8'b11011111;
        6: anode = 8'b10111111;
        7: anode = 8'b01111111;
	default: anode = 8'b11111111;
     endcase
     

always  @ (posedge clk)
   begin
	clkdiv <= clkdiv + 21'b1;
    end 
	  
endmodule
module seven_segment_leds_x_8(
    input [31:0] bcd_in,
    input [7:0] decimal_points,
    input clk,
    output  reg [6:0] a_to_g,
    output reg decimal_point,
    output reg [7:0] anode 
    );


wire [2:0] counter;
reg [3:0] digit;
reg [20:0] clkdiv;	
	 

assign counter = clkdiv[20:18];


always @(posedge clk)
    case(counter)
	0: {digit, decimal_point} = {bcd_in[3:0], ~decimal_points[0]};
	1: {digit, decimal_point} = {bcd_in[7:4], ~decimal_points[1]};
	2: {digit, decimal_point} = {bcd_in[11:8], ~decimal_points[2]};
	3: {digit, decimal_point} = {bcd_in[15:12], ~decimal_points[3]};
	4: {digit, decimal_point} = {bcd_in[19:16], ~decimal_points[4]};
    	5: {digit, decimal_point} = {bcd_in[23:20], ~decimal_points[5]};
    	6: {digit, decimal_point} = {bcd_in[27:24], ~decimal_points[6]};
    	7: {digit, decimal_point} = {bcd_in[31:28], ~decimal_points[7]};
     endcase


always @(posedge clk)
     case(digit)
    	0: a_to_g = 8'b1000000;
    	1: a_to_g = 8'b1111001;
	2: a_to_g = 8'b0100100;
	3: a_to_g = 8'b0110000;
	4: a_to_g = 8'b0011001;
	5: a_to_g = 8'b0010010;
	6: a_to_g = 8'b0000010;
	7: a_to_g = 8'b1111000;
	8: a_to_g = 8'b0000000;
	9: a_to_g = 8'b0010000;
	default: a_to_g = 8'b11111111;
    endcase
	  

always @(posedge clk)
    case(counter)
        0: anode = 8'b11111110;
	1: anode = 8'b11111101;
	2: anode = 8'b11111011;
	3: anode = 8'b11110111;
	4: anode = 8'b11101111;
        5: anode = 8'b11011111;
        6: anode = 8'b10111111;
        7: anode = 8'b01111111;
	default: anode = 8'b11111111;
     endcase
     

always  @ (posedge clk)
   begin
	clkdiv <= clkdiv + 21'b1;
    end 
	  
endmodule