data/full_repos/permissive/487568919/basic_verilog/read_ahead_buf.sv
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/read_ahead_buf.sv:79: Cannot find file containing module: 'edge_detect'\n  edge_detect r_req_ed (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/edge_detect\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/edge_detect.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/edge_detect.sv\n             edge_detect\n             edge_detect.v\n             edge_detect.sv\n             obj_dir/edge_detect\n             obj_dir/edge_detect.v\n             obj_dir/edge_detect.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/read_ahead_buf.sv:108: Cannot find file containing module: 'soft_latch'\n  soft_latch #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module read_ahead_buf #( parameter
  DATA_W = 32
)(
  input clk,
  input anrst,


  output fifo_r_req,
  input [DATA_W-1:0] fifo_r_data,
  input fifo_empty,


  input r_req,
  output logic [DATA_W-1:0] r_data,
  output logic empty
);


  logic buf_empty = 1'b1;


  logic buf_fill_req;
  assign buf_fill_req = ~fifo_empty &&
                        buf_empty &&
                        ~buf_fill_req_d1;


  logic buf_fill_req_d1 = 1'b0;
  always_ff @(posedge clk or negedge anrst) begin
    if( ~anrst ) begin
      buf_fill_req_d1 <= 1'b0;
    end else begin
      buf_fill_req_d1 <= buf_fill_req;
    end
  end


  logic r_req_filt;
  assign r_req_filt = anrst &&
                      ~fifo_empty &&
                      ~buf_empty &&
                      ~buf_fill_req && r_req;

  logic r_req_rise;
  logic r_req_fall;
  edge_detect r_req_ed (
    .clk( clk ),
    .nrst( anrst ),
    .in( r_req_filt ),
    .rising( r_req_rise ),
    .falling( r_req_fall ),
    .both(  )
  );

  assign fifo_r_req = r_req_filt;
  assign empty = anrst && fifo_empty && buf_empty;


  logic [DATA_W-1:0] r_data_buf = '0;
  always_ff @(posedge clk or negedge anrst) begin
    if( ~anrst ) begin
      buf_empty = 1'b1;
    end else begin

      if( buf_fill_req_d1 ) begin
        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
        buf_empty = 1'b0;
      end else if( ~r_req_filt && r_req_fall )  begin
        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
      end

    end
  end

  soft_latch #(
    .WIDTH( DATA_W )
  ) r_data_latch (
    .clk( clk ),
    .anrst( anrst ),
    .latch( r_req_filt ),
    .in( (r_req_rise)?(r_data_buf[DATA_W-1:0]):(fifo_r_data[DATA_W-1:0]) ),
    .out( r_data[DATA_W-1:0] )
  );

endmodule
module read_ahead_buf #( parameter
  DATA_W = 32
)(
  input clk,
  input anrst,


  output fifo_r_req,
  input [DATA_W-1:0] fifo_r_data,
  input fifo_empty,


  input r_req,
  output logic [DATA_W-1:0] r_data,
  output logic empty
);



  logic buf_empty = 1'b1;


  logic buf_fill_req;
  assign buf_fill_req = ~fifo_empty &&
                        buf_empty &&
                        ~buf_fill_req_d1;


  logic buf_fill_req_d1 = 1'b0;
  always_ff @(posedge clk or negedge anrst) begin
    if( ~anrst ) begin
      buf_fill_req_d1 <= 1'b0;
    end else begin
      buf_fill_req_d1 <= buf_fill_req;
    end
  end


  logic r_req_filt;
  assign r_req_filt = anrst &&
                      ~fifo_empty &&
                      ~buf_empty &&
                      ~buf_fill_req && r_req;

  logic r_req_rise;
  logic r_req_fall;
  edge_detect r_req_ed (
    .clk( clk ),
    .nrst( anrst ),
    .in( r_req_filt ),
    .rising( r_req_rise ),
    .falling( r_req_fall ),
    .both(  )
  );

  assign fifo_r_req = r_req_filt;
  assign empty = anrst && fifo_empty && buf_empty;


  logic [DATA_W-1:0] r_data_buf = '0;
  always_ff @(posedge clk or negedge anrst) begin
    if( ~anrst ) begin
      buf_empty = 1'b1;
    end else begin

      if( buf_fill_req_d1 ) begin
        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
        buf_empty = 1'b0;
      end else if( ~r_req_filt && r_req_fall )  begin
        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
      end

    end
  end

  soft_latch #(
    .WIDTH( DATA_W )
  ) r_data_latch (
    .clk( clk ),
    .anrst( anrst ),
    .latch( r_req_filt ),
    .in( (r_req_rise)?(r_data_buf[DATA_W-1:0]):(fifo_r_data[DATA_W-1:0]) ),
    .out( r_data[DATA_W-1:0] )
  );

endmodule