data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_dp_macc_l.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_dp_macc_l.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_dp_macc_l.v:33: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module cpx_dp_macc_l(

   data_out_cx_l, scan_out, shiftenable_buf, 

   arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca, 
   arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca, 
   data_crit_cx_l, data_ncrit_cx_l, rclk, scan_in, shiftenable
   );	

   output [149:0] data_out_cx_l;
   output 		   scan_out;
   output 		   shiftenable_buf;
   
   input  	           arb_cpxdp_qsel1_ca;
   input  	           arb_cpxdp_qsel0_ca;
   input 		   arb_cpxdp_grant_ca;
   input 		   arb_cpxdp_shift_cx;
   input 		   arb_cpxdp_q0_hold_ca;
   input [149:0]  src_cpx_data_ca;
   input [149:0]  data_crit_cx_l;
   input [149:0]  data_ncrit_cx_l;	    
   input 		   rclk;

   input 		   scan_in;
   input 		   shiftenable;

   wire 		   grant_cx;
   wire [149:0]   q1_datain_ca, q0_datain_ca;
   wire [149:0]   q1_dataout, q0_dataout;
   wire [149:0]   data_cx_l;
   wire 		   clkq0, clkq1;

   reg 			   clkenq0, clkenq1;




assign shiftenable_buf  =  shiftenable;





wire   se_l ;
assign se_l  = ~shiftenable ;


   
clken_buf ck0 (
	       .clk  (clkq0),
	       .rclk (rclk),
	       .enb_l(~arb_cpxdp_q0_hold_ca),
	       .tmb_l(se_l));

clken_buf ck1 (
	       .clk  (clkq1),
	       .rclk (rclk),
	       .enb_l(~arb_cpxdp_qsel1_ca),
	       .tmb_l(se_l));

   
   dff_s   #(1) dff_cpx_grin_r(
	    .din           (arb_cpxdp_grant_ca),
	    .q             (grant_cx),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());



   
   dff_s   #(150) dff_cpx_datain_q1(
	    .din           (src_cpx_data_ca[149:0]),
	    .q             (q1_dataout[149:0]),
	    .clk           (clkq1),
	    .se            (1'b0),
	    .si            (),
	    .so            ());

   
assign q0_datain_ca[149:0] = 
             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
   
   
   dff_s   #(150) dff_cpx_datain_q0(
	    .din           (q0_datain_ca[149:0]),
	    .q             (q0_dataout[149:0]),
	    .clk           (clkq0),
	    .se            (1'b0),
	    .si            (),
	    .so            ());
   
   assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
   assign data_out_cx_l[149:0] = data_crit_cx_l[149:0] & data_ncrit_cx_l[149:0] & data_cx_l[149:0];
   





   


endmodule
module cpx_dp_macc_l(

   data_out_cx_l, scan_out, shiftenable_buf, 

   arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca, 
   arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca, 
   data_crit_cx_l, data_ncrit_cx_l, rclk, scan_in, shiftenable
   );
	

   output [149:0] data_out_cx_l;
   output 		   scan_out;
   output 		   shiftenable_buf;
   
   input  	           arb_cpxdp_qsel1_ca;
   input  	           arb_cpxdp_qsel0_ca;
   input 		   arb_cpxdp_grant_ca;
   input 		   arb_cpxdp_shift_cx;
   input 		   arb_cpxdp_q0_hold_ca;
   input [149:0]  src_cpx_data_ca;
   input [149:0]  data_crit_cx_l;
   input [149:0]  data_ncrit_cx_l;	    
   input 		   rclk;

   input 		   scan_in;
   input 		   shiftenable;

   wire 		   grant_cx;
   wire [149:0]   q1_datain_ca, q0_datain_ca;
   wire [149:0]   q1_dataout, q0_dataout;
   wire [149:0]   data_cx_l;
   wire 		   clkq0, clkq1;

   reg 			   clkenq0, clkenq1;




assign shiftenable_buf  =  shiftenable;





wire   se_l ;
assign se_l  = ~shiftenable ;


   
clken_buf ck0 (
	       .clk  (clkq0),
	       .rclk (rclk),
	       .enb_l(~arb_cpxdp_q0_hold_ca),
	       .tmb_l(se_l));

clken_buf ck1 (
	       .clk  (clkq1),
	       .rclk (rclk),
	       .enb_l(~arb_cpxdp_qsel1_ca),
	       .tmb_l(se_l));

   
   dff_s   #(1) dff_cpx_grin_r(
	    .din           (arb_cpxdp_grant_ca),
	    .q             (grant_cx),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());



   
   dff_s   #(150) dff_cpx_datain_q1(
	    .din           (src_cpx_data_ca[149:0]),
	    .q             (q1_dataout[149:0]),
	    .clk           (clkq1),
	    .se            (1'b0),
	    .si            (),
	    .so            ());

   
assign q0_datain_ca[149:0] = 
             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
   
   
   dff_s   #(150) dff_cpx_datain_q0(
	    .din           (q0_datain_ca[149:0]),
	    .q             (q0_dataout[149:0]),
	    .clk           (clkq0),
	    .se            (1'b0),
	    .si            (),
	    .so            ());
   
   assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
   assign data_out_cx_l[149:0] = data_crit_cx_l[149:0] & data_ncrit_cx_l[149:0] & data_cx_l[149:0];
   





   


endmodule