data/full_repos/permissive/506562943/HDLBits/Verilog Language/More Verilog Features/adder100i.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Features/adder100i.v\n%Error: Exiting due to 5 error(s)\n'
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );

    always @(*) begin
        sum[0] = a[0] ^ b[0] ^ cin;
        cout[0] = (a[0] & b[0]) | ((a[0] ^ b[0]) & cin);
        for (integer i = 1; i < 100; i++) begin
            sum[i] = a[i] ^ b[i] ^ cout[i - 1];
            cout[i] = (a[i] & b[i]) | ((a[i] ^ b[i]) & cout[i - 1]);
        end
    end
    
endmodule
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );


    always @(*) begin
        sum[0] = a[0] ^ b[0] ^ cin;
        cout[0] = (a[0] & b[0]) | ((a[0] ^ b[0]) & cin);
        for (integer i = 1; i < 100; i++) begin
            sum[i] = a[i] ^ b[i] ^ cout[i - 1];
            cout[i] = (a[i] & b[i]) | ((a[i] ^ b[i]) & cout[i - 1]);
        end
    end
    
endmodule