data/full_repos/permissive/446128190/rtl/Bitlet_CE.v
1: b'%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:12: Cannot find include file: Bitlet_Defs.vh\n`include "Bitlet_Defs.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.v\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.sv\n             Bitlet_Defs.vh\n             Bitlet_Defs.vh.v\n             Bitlet_Defs.vh.sv\n             obj_dir/Bitlet_Defs.vh\n             obj_dir/Bitlet_Defs.vh.v\n             obj_dir/Bitlet_Defs.vh.sv\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:22: Define or directive not defined: \'`Max_quant\'\n    input       [`Max_quant-1:0]            prune,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:25: Define or directive not defined: \'`Wid_abs\'\n    input       [N_total*`Wid_abs-1:0]      Wabs_vec,\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:26: Define or directive not defined: \'`Wid_fix\'\n    input       [N_total*`Wid_fix-1:0]      Afix_vec,\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:28: Define or directive not defined: \'`N_channel\'\n    output reg  [`N_channel*`Wid_fix-1:0]   Asel_vec\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:28: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    output reg  [`N_channel*`Wid_fix-1:0]   Asel_vec\n                           ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:28: Define or directive not defined: \'`Wid_fix\'\n    output reg  [`N_channel*`Wid_fix-1:0]   Asel_vec\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:32: syntax error, unexpected genvar\ngenvar  g, k;\n^~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:37: Define or directive not defined: \'`Wid_abs\'\nwire    [`Wid_abs-1:0]      Wabs[N_total-1:0];\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:38: Define or directive not defined: \'`Wid_fix\'\nwire    [`Wid_fix-1:0]      Afix[N_total-1:0];\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:40: syntax error, unexpected generate\ngenerate\n^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:43: Define or directive not defined: \'`Wid_abs\'\n        assign  Wabs[g] = Wabs_vec[(g*`Wid_abs)+:`Wid_abs];\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:43: Define or directive not defined: \'`Wid_abs\'\n        assign  Wabs[g] = Wabs_vec[(g*`Wid_abs)+:`Wid_abs];\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:44: Define or directive not defined: \'`Wid_fix\'\n        assign  Afix[g] = Afix_vec[(g*`Wid_fix)+:`Wid_fix];\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:44: Define or directive not defined: \'`Wid_fix\'\n        assign  Afix[g] = Afix_vec[(g*`Wid_fix)+:`Wid_fix];\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:49: Define or directive not defined: \'`N_channel\'\nwire    [N_total-1:0]       Wtrans[`N_channel-1:0];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:52: syntax error, unexpected assign\nassign  Wtrans_vld  = Wabs_vld;\n^~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:55: Define or directive not defined: \'`N_channel\'\n    for (g=0; g<`N_channel; g=g+1)\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:65: Define or directive not defined: \'`N_channel\'\nwire    [Wid_sel-1:0]       sel[`N_channel-1:0];\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:66: Define or directive not defined: \'`N_channel\'\nwire    [`N_channel-1:0]    sel_vld;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:67: Define or directive not defined: \'`N_channel\'\nwire    [`N_channel-1:0]    sel_zero;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:69: syntax error, unexpected generate\ngenerate\n^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:70: Define or directive not defined: \'`N_channel\'\n    for (g=0; g<`N_channel; g=g+1)\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:88: Define or directive not defined: \'`Wid_fix\'\nreg     [`Wid_fix-1:0]      Asel[`N_channel-1:0];\n         ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:88: Define or directive not defined: \'`N_channel\'\nreg     [`Wid_fix-1:0]      Asel[`N_channel-1:0];\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:90: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n)\n^~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:101: Define or directive not defined: \'`N_channel\'\nfor (g=0; g<`N_channel; g=g+1)\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:119: Define or directive not defined: \'`N_channel\'\n    for (i=0; i<`N_channel; i=i+1)\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:121: Define or directive not defined: \'`Wid_fix\'\n        Asel_vec[(i*`Wid_fix)+:`Wid_fix]    = Asel[i];\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_CE.v:121: Define or directive not defined: \'`Wid_fix\'\n        Asel_vec[(i*`Wid_fix)+:`Wid_fix]    = Asel[i];\n                               ^~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module Bitlet_CE
#(
    parameter   N_total = 64
)
(
    input                                   clk,
    input                                   rst_n,
    input       [$clog2(N_total)-1:0]       N_calculate,
    input       [`Max_quant-1:0]            prune,
    input                                   flush,
    input                                   Wabs_vld,
    input       [N_total*`Wid_abs-1:0]      Wabs_vec,
    input       [N_total*`Wid_fix-1:0]      Afix_vec,
    output reg                              Asel_vld,
    output reg  [`N_channel*`Wid_fix-1:0]   Asel_vec
);

integer i;
genvar  g, k;

localparam  Wid_sel = $clog2(N_total);


wire    [`Wid_abs-1:0]      Wabs[N_total-1:0];
wire    [`Wid_fix-1:0]      Afix[N_total-1:0];

generate
    for (g=0; g<N_total; g=g+1)
    begin
        assign  Wabs[g] = Wabs_vec[(g*`Wid_abs)+:`Wid_abs];
        assign  Afix[g] = Afix_vec[(g*`Wid_fix)+:`Wid_fix];
    end
endgenerate


wire    [N_total-1:0]       Wtrans[`N_channel-1:0];
wire                        Wtrans_vld;

assign  Wtrans_vld  = Wabs_vld;

generate
    for (g=0; g<`N_channel; g=g+1)
    begin
        for (k=0; k<N_total; k=k+1)
        begin
            assign  Wtrans[g][k]    = Wabs[k][g];
        end
    end
endgenerate


wire    [Wid_sel-1:0]       sel[`N_channel-1:0];
wire    [`N_channel-1:0]    sel_vld;
wire    [`N_channel-1:0]    sel_zero;

generate
    for (g=0; g<`N_channel; g=g+1)
    begin
        Bitlet_CheckWindow #(.N_total(N_total)) UCHECKWINDOW
        (
            .clk(clk),
            .rst_n(rst_n),
            .N_calculate(N_calculate),
            .flush(flush),
            .en(Wtrans_vld&prune[g]),
            .Wtrans(Wtrans[g]),
            .sel_vld(sel_vld[g]),
            .zero(sel_zero[g]),
            .sel(sel[g])
        );
    end
endgenerate


reg     [`Wid_fix-1:0]      Asel[`N_channel-1:0];

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Asel_vld    <= 1'b0;
    else if (flush)
        Asel_vld    <= 1'b0;
    else if (|sel_vld)
        Asel_vld    <= 1'b1;
    else if (Asel_vld)
        Asel_vld    <= 1'b0;
end
for (g=0; g<`N_channel; g=g+1)
begin
    always @(posedge clk or negedge rst_n)
    begin
        if (!rst_n)
            Asel[g] <= 'b0;
        else if (flush)
            Asel[g] <= 'b0;
        else if (sel_vld[g])
            Asel[g] <= (sel_zero[g]) ? 'b0 : Afix[sel[g]];
        else if ((!sel_vld[g])&&(Asel[g]!='b0))
            Asel[g] <= 'b0;
    end
end


always @(*)
begin
    for (i=0; i<`N_channel; i=i+1)
    begin
        Asel_vec[(i*`Wid_fix)+:`Wid_fix]    = Asel[i];
    end
end

endmodule
module Bitlet_CE
#(
    parameter   N_total = 64
)
(
    input                                   clk,
    input                                   rst_n,
    input       [$clog2(N_total)-1:0]       N_calculate,
    input       [`Max_quant-1:0]            prune,
    input                                   flush,
    input                                   Wabs_vld,
    input       [N_total*`Wid_abs-1:0]      Wabs_vec,
    input       [N_total*`Wid_fix-1:0]      Afix_vec,
    output reg                              Asel_vld,
    output reg  [`N_channel*`Wid_fix-1:0]   Asel_vec
);


integer i;
genvar  g, k;

localparam  Wid_sel = $clog2(N_total);


wire    [`Wid_abs-1:0]      Wabs[N_total-1:0];
wire    [`Wid_fix-1:0]      Afix[N_total-1:0];

generate
    for (g=0; g<N_total; g=g+1)
    begin
        assign  Wabs[g] = Wabs_vec[(g*`Wid_abs)+:`Wid_abs];
        assign  Afix[g] = Afix_vec[(g*`Wid_fix)+:`Wid_fix];
    end
endgenerate


wire    [N_total-1:0]       Wtrans[`N_channel-1:0];
wire                        Wtrans_vld;

assign  Wtrans_vld  = Wabs_vld;

generate
    for (g=0; g<`N_channel; g=g+1)
    begin
        for (k=0; k<N_total; k=k+1)
        begin
            assign  Wtrans[g][k]    = Wabs[k][g];
        end
    end
endgenerate


wire    [Wid_sel-1:0]       sel[`N_channel-1:0];
wire    [`N_channel-1:0]    sel_vld;
wire    [`N_channel-1:0]    sel_zero;

generate
    for (g=0; g<`N_channel; g=g+1)
    begin
        Bitlet_CheckWindow #(.N_total(N_total)) UCHECKWINDOW
        (
            .clk(clk),
            .rst_n(rst_n),
            .N_calculate(N_calculate),
            .flush(flush),
            .en(Wtrans_vld&prune[g]),
            .Wtrans(Wtrans[g]),
            .sel_vld(sel_vld[g]),
            .zero(sel_zero[g]),
            .sel(sel[g])
        );
    end
endgenerate


reg     [`Wid_fix-1:0]      Asel[`N_channel-1:0];

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Asel_vld    <= 1'b0;
    else if (flush)
        Asel_vld    <= 1'b0;
    else if (|sel_vld)
        Asel_vld    <= 1'b1;
    else if (Asel_vld)
        Asel_vld    <= 1'b0;
end
for (g=0; g<`N_channel; g=g+1)
begin
    always @(posedge clk or negedge rst_n)
    begin
        if (!rst_n)
            Asel[g] <= 'b0;
        else if (flush)
            Asel[g] <= 'b0;
        else if (sel_vld[g])
            Asel[g] <= (sel_zero[g]) ? 'b0 : Afix[sel[g]];
        else if ((!sel_vld[g])&&(Asel[g]!='b0))
            Asel[g] <= 'b0;
    end
end


always @(*)
begin
    for (i=0; i<`N_channel; i=i+1)
    begin
        Asel_vec[(i*`Wid_fix)+:`Wid_fix]    = Asel[i];
    end
end

endmodule