data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_task_global.v
data/verilator_xmls/27d3a124-10ac-4363-9040-d4997bae10c5.xml
module task_global();

reg [7:0] temp_out;
reg [7:0] temp_in;

task convert;
begin
  temp_out = (9/5) *( temp_in + 32);
end
endtask

endmodule
module task_global();


reg [7:0] temp_out;
reg [7:0] temp_in;

task convert;
begin
  temp_out = (9/5) *( temp_in + 32);
end
endtask

endmodule