data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:46: Cannot find include file: spi_defines.v\n`include "spi_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog,data/full_repos/permissive/447976230/spi_defines.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog,data/full_repos/permissive/447976230/spi_defines.v.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog,data/full_repos/permissive/447976230/spi_defines.v.sv\n             spi_defines.v\n             spi_defines.v.v\n             spi_defines.v.sv\n             obj_dir/spi_defines.v\n             obj_dir/spi_defines.v.v\n             obj_dir/spi_defines.v.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:62: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;              \n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:68: Define or directive not defined: \'`SPI_CHAR_LEN_BITS\'\n   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;          \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:83: Define or directive not defined: \'`SPI_DIVIDE\'\n   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);\n                                                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);\n                                                                               ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:84: Define or directive not defined: \'`SPI_CTRL\'\n   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);\n                                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:85: Define or directive not defined: \'`SPI_TX_0\'\n   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);\n                                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:86: Define or directive not defined: \'`SPI_TX_1\'\n   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:86: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);\n                                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:87: Define or directive not defined: \'`SPI_TX_2\'\n   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:87: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);\n                                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:88: Define or directive not defined: \'`SPI_TX_3\'\n   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);\n                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);\n                                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:89: Define or directive not defined: \'`SPI_SS\'\n   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);\n                                                                    ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:89: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);\n                                                                           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:93: Define or directive not defined: \'`SPI_RX_0\'\n       `SPI_RX_0:    wb_dat = rx[31:0];\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:93: syntax error, unexpected \':\', expecting endcase\n       `SPI_RX_0:    wb_dat = rx[31:0];\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:94: Define or directive not defined: \'`SPI_CTRL\'\n       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1\'b0}}, ctrl};\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:94: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1\'b0}}, ctrl};\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:95: Define or directive not defined: \'`SPI_DIVIDE\'\n       `SPI_DIVIDE:  wb_dat = {16\'b0, divider};\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:96: Define or directive not defined: \'`SPI_SS\'\n       `SPI_SS:      wb_dat = {16\'b0, ss};\n       ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:133: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n       ctrl <= {`SPI_CTRL_BIT_NB{1\'b0}};\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:139: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:139: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:142: Define or directive not defined: \'`SPI_CTRL_GO\'\n       ctrl[`SPI_CTRL_GO] <= 1\'b0;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:142: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n       ctrl[`SPI_CTRL_GO] <= 1\'b0;\n                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:144: Define or directive not defined: \'`SPI_CTRL_RX_NEGEDGE\'\n   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:144: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];\n                                                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:145: Define or directive not defined: \'`SPI_CTRL_TX_NEGEDGE\'\n   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:145: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];\n                                                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:146: Define or directive not defined: \'`SPI_CTRL_GO\'\n   assign go         = ctrl[`SPI_CTRL_GO];\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:146: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign go         = ctrl[`SPI_CTRL_GO];\n                                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:147: Define or directive not defined: \'`SPI_CTRL_CHAR_LEN\'\n   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:147: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];\n                                              ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:148: Define or directive not defined: \'`SPI_CTRL_LSB\'\n   assign lsb        = ctrl[`SPI_CTRL_LSB];\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:148: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign lsb        = ctrl[`SPI_CTRL_LSB];\n                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:149: Define or directive not defined: \'`SPI_CTRL_IE\'\n   assign ie         = ctrl[`SPI_CTRL_IE];\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:149: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign ie         = ctrl[`SPI_CTRL_IE];\n                                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:150: Define or directive not defined: \'`SPI_CTRL_ASS\'\n   assign ass        = ctrl[`SPI_CTRL_ASS];\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:150: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign ass        = ctrl[`SPI_CTRL_ASS];\n                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:167: Define or directive not defined: \'`SPI_DIVIDER_LEN\'\n                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), \n                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v:174: Define or directive not defined: \'`SPI_CHAR_LEN_BITS\'\n   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),\n                                                                  ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 44 error(s)\n'
module spi_top16
  (input wb_clk_i, input wb_rst_i, 
   input [4:0] wb_adr_i, 
   input [15:0] wb_dat_i, 
   output reg [15:0] wb_dat_o, 
   input [1:0] wb_sel_i,
   input wb_we_i, input wb_stb_i, input wb_cyc_i, 
   output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
   

   output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
   

   reg [15:0] divider;
   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;
   reg [15:0] 		      ss;
   reg [31:0] 		      wb_dat;
   wire [31:0] 		      rx;
   wire 		      rx_negedge;
   wire 		      tx_negedge;
   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;
   wire 			 go;
   wire 			 lsb;
   wire 			 ie;
   wire 			 ass;
   wire 			 spi_divider_sel;
   wire 			 spi_ctrl_sel;
   wire [3:0] 			 spi_tx_sel;
   wire 			 spi_ss_sel;
   wire 			 tip;
   wire 			 pos_edge;
   wire 			 neg_edge;
   wire 			 last_bit;
   

   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
   
   always @(wb_adr_i or rx or ctrl or divider or ss)
     case (wb_adr_i[4:2])   
       `SPI_RX_0:    wb_dat = rx[31:0];
       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
       `SPI_DIVIDE:  wb_dat = {16'b0, divider};
       `SPI_SS:      wb_dat = {16'b0, ss};
       default : wb_dat = 32'd0;
     endcase
   
   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_dat_o <= 32'b0;
     else
       wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
   
   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_ack_o <= 1'b0;
     else
       wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
   
   assign wb_err_o = 1'b0;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_int_o <= 1'b0;
     else if (ie && tip && last_bit && pos_edge)
       wb_int_o <= 1'b1;
     else if (wb_ack_o)
       wb_int_o <= 1'b0;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       divider <= 16'b0;
     else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
       divider <= wb_dat_i;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
     else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
       begin
          if (wb_sel_i[0])
            ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
          if (wb_sel_i[1])
            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
       end
     else if(tip && last_bit && pos_edge)
       ctrl[`SPI_CTRL_GO] <= 1'b0;
   
   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
   assign go         = ctrl[`SPI_CTRL_GO];
   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
   assign lsb        = ctrl[`SPI_CTRL_LSB];
   assign ie         = ctrl[`SPI_CTRL_IE];
   assign ass        = ctrl[`SPI_CTRL_ASS];
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       ss <= 16'b0;
     else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
       begin
          if (wb_sel_i[0])
            ss[7:0] <= wb_dat_i[7:0];
          if (wb_sel_i[1])
            ss[15:8] <= wb_dat_i[15:8];
       end
   
   assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
   
   spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
                    .neg_edge(neg_edge));

   wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), 
			   (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
   
   
   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
                    .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), 
                    .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
                    .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
                    .tip(tip), .last(last_bit), 
                    .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), 
                    .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));

endmodule
module spi_top16
  (input wb_clk_i, input wb_rst_i, 
   input [4:0] wb_adr_i, 
   input [15:0] wb_dat_i, 
   output reg [15:0] wb_dat_o, 
   input [1:0] wb_sel_i,
   input wb_we_i, input wb_stb_i, input wb_cyc_i, 
   output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
   

   output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);

   

   reg [15:0] divider;
   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;
   reg [15:0] 		      ss;
   reg [31:0] 		      wb_dat;
   wire [31:0] 		      rx;
   wire 		      rx_negedge;
   wire 		      tx_negedge;
   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;
   wire 			 go;
   wire 			 lsb;
   wire 			 ie;
   wire 			 ass;
   wire 			 spi_divider_sel;
   wire 			 spi_ctrl_sel;
   wire [3:0] 			 spi_tx_sel;
   wire 			 spi_ss_sel;
   wire 			 tip;
   wire 			 pos_edge;
   wire 			 neg_edge;
   wire 			 last_bit;
   

   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
   
   always @(wb_adr_i or rx or ctrl or divider or ss)
     case (wb_adr_i[4:2])   
       `SPI_RX_0:    wb_dat = rx[31:0];
       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
       `SPI_DIVIDE:  wb_dat = {16'b0, divider};
       `SPI_SS:      wb_dat = {16'b0, ss};
       default : wb_dat = 32'd0;
     endcase
   
   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_dat_o <= 32'b0;
     else
       wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
   
   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_ack_o <= 1'b0;
     else
       wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
   
   assign wb_err_o = 1'b0;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       wb_int_o <= 1'b0;
     else if (ie && tip && last_bit && pos_edge)
       wb_int_o <= 1'b1;
     else if (wb_ack_o)
       wb_int_o <= 1'b0;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       divider <= 16'b0;
     else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
       divider <= wb_dat_i;
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
     else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
       begin
          if (wb_sel_i[0])
            ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
          if (wb_sel_i[1])
            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
       end
     else if(tip && last_bit && pos_edge)
       ctrl[`SPI_CTRL_GO] <= 1'b0;
   
   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
   assign go         = ctrl[`SPI_CTRL_GO];
   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
   assign lsb        = ctrl[`SPI_CTRL_LSB];
   assign ie         = ctrl[`SPI_CTRL_IE];
   assign ass        = ctrl[`SPI_CTRL_ASS];
   

   always @(posedge wb_clk_i)
     if (wb_rst_i)
       ss <= 16'b0;
     else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
       begin
          if (wb_sel_i[0])
            ss[7:0] <= wb_dat_i[7:0];
          if (wb_sel_i[1])
            ss[15:8] <= wb_dat_i[15:8];
       end
   
   assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
   
   spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
                    .neg_edge(neg_edge));

   wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), 
			   (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
   
   
   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
                    .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), 
                    .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
                    .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
                    .tip(tip), .last(last_bit), 
                    .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), 
                    .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));

endmodule