data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/01_Latches_and_Flip-Flops/01_D-flip-flop.v
data/verilator_xmls/5fdfda87-2f8b-473c-b4ce-3bf47c44f735.xml
module top_module (
    input clk,
    input d,
    output reg q
);
    
    always @(posedge clk) begin
        q <= d;
    end
    
endmodule
module top_module (
    input clk,
    input d,
    output reg q
);

    
    always @(posedge clk) begin
        q <= d;
    end
    
endmodule