data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v
1: b'%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:1: Cannot find include file: fixedpt.vh\n`include "fixedpt.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.v\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.sv\n             fixedpt.vh\n             fixedpt.vh.v\n             fixedpt.vh.sv\n             obj_dir/fixedpt.vh\n             obj_dir/fixedpt.vh.v\n             obj_dir/fixedpt.vh.sv\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:67: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT u_v1_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:68: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT u_v2_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:69: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT u_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:71: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT v_v1_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:72: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT v_v2_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:73: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT v_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:135: Define or directive not defined: \'`SATURATE\'\n      o_r <= `SATURATE(8\'d0, 8\'d255, (r_pipe[PIPELINE_WIDTH]));\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:135: syntax error, unexpected \',\'\n      o_r <= `SATURATE(8\'d0, 8\'d255, (r_pipe[PIPELINE_WIDTH]));\n                           ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:136: Define or directive not defined: \'`SATURATE\'\n      o_g <= `SATURATE(8\'d0, 8\'d255, (g_pipe[PIPELINE_WIDTH]));\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:136: syntax error, unexpected \',\'\n      o_g <= `SATURATE(8\'d0, 8\'d255, (g_pipe[PIPELINE_WIDTH]));\n                           ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:137: Define or directive not defined: \'`SATURATE\'\n      o_b <= `SATURATE(8\'d0, 8\'d255, (b_pipe[PIPELINE_WIDTH]));\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex3.v:137: syntax error, unexpected \',\'\n      o_b <= `SATURATE(8\'d0, 8\'d255, (b_pipe[PIPELINE_WIDTH]));\n                           ^\n%Error: Exiting due to 13 error(s)\n'
module RasterPipelineEX3(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,



  input [7:0]             i_r,
  input [7:0]             i_g,
  input [7:0]             i_b,






  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg [7:0]        o_r,
  output reg [7:0]        o_g,
  output reg [7:0]        o_b
);
  
  parameter PIPELINE_WIDTH = 4;
  wire valid;

  reg signed [15:0] x_pipe[0:PIPELINE_WIDTH];
  reg signed [15:0] y_pipe[0:PIPELINE_WIDTH];
  reg [7:0] r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] b_pipe[0:PIPELINE_WIDTH];

  integer i;
  always @(posedge i_clk)
  begin
    if (i_write_enable)
    begin
      r_pipe[0] <= i_r;
      g_pipe[0] <= i_g;
      b_pipe[0] <= i_b;
      x_pipe[0] <= i_x_pos;
      y_pipe[0] <= i_y_pos;
    end
    for (i = 1; i <= PIPELINE_WIDTH; i = i + 1)
    begin
      r_pipe[i] <= r_pipe[i - 1];
      g_pipe[i] <= g_pipe[i - 1];
      b_pipe[i] <= b_pipe[i - 1];
      x_pipe[i] <= x_pipe[i - 1];
      y_pipe[i] <= y_pipe[i - 1];
    end
  end

  pipeline_ctrl #(PIPELINE_WIDTH) pc(
    .i_clk      (i_clk),
    .i_enable   (i_write_enable),
    .o_ack      (valid)
  );

  wire [7:0] clut_index;
  wire [15:0] texel_address;

  wire `FIXPT u_v1_value_fixpt;
  wire `FIXPT u_v2_value_fixpt;
  wire `FIXPT u_v3_value_fixpt;

  wire `FIXPT v_v1_value_fixpt;
  wire `FIXPT v_v2_value_fixpt;
  wire `FIXPT v_v3_value_fixpt;






















































  always @(posedge i_clk)
  begin
    if (valid)
    begin
      o_write_pixel <= 1;
      o_x <= x_pipe[PIPELINE_WIDTH];
      o_y <= y_pipe[PIPELINE_WIDTH];
      o_r <= `SATURATE(8'd0, 8'd255, (r_pipe[PIPELINE_WIDTH]));
      o_g <= `SATURATE(8'd0, 8'd255, (g_pipe[PIPELINE_WIDTH]));
      o_b <= `SATURATE(8'd0, 8'd255, (b_pipe[PIPELINE_WIDTH]));
    end
    else
    begin
      o_write_pixel <= 0;
      o_x <= 32'bx;
      o_y <= 32'bx;
      o_r <= 32'bx;
      o_g <= 32'bx;
      o_b <= 32'bx;
    end
  end

endmodule
module RasterPipelineEX3(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,



  input [7:0]             i_r,
  input [7:0]             i_g,
  input [7:0]             i_b,






  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg [7:0]        o_r,
  output reg [7:0]        o_g,
  output reg [7:0]        o_b
);

  
  parameter PIPELINE_WIDTH = 4;
  wire valid;

  reg signed [15:0] x_pipe[0:PIPELINE_WIDTH];
  reg signed [15:0] y_pipe[0:PIPELINE_WIDTH];
  reg [7:0] r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] b_pipe[0:PIPELINE_WIDTH];

  integer i;
  always @(posedge i_clk)
  begin
    if (i_write_enable)
    begin
      r_pipe[0] <= i_r;
      g_pipe[0] <= i_g;
      b_pipe[0] <= i_b;
      x_pipe[0] <= i_x_pos;
      y_pipe[0] <= i_y_pos;
    end
    for (i = 1; i <= PIPELINE_WIDTH; i = i + 1)
    begin
      r_pipe[i] <= r_pipe[i - 1];
      g_pipe[i] <= g_pipe[i - 1];
      b_pipe[i] <= b_pipe[i - 1];
      x_pipe[i] <= x_pipe[i - 1];
      y_pipe[i] <= y_pipe[i - 1];
    end
  end

  pipeline_ctrl #(PIPELINE_WIDTH) pc(
    .i_clk      (i_clk),
    .i_enable   (i_write_enable),
    .o_ack      (valid)
  );

  wire [7:0] clut_index;
  wire [15:0] texel_address;

  wire `FIXPT u_v1_value_fixpt;
  wire `FIXPT u_v2_value_fixpt;
  wire `FIXPT u_v3_value_fixpt;

  wire `FIXPT v_v1_value_fixpt;
  wire `FIXPT v_v2_value_fixpt;
  wire `FIXPT v_v3_value_fixpt;






















































  always @(posedge i_clk)
  begin
    if (valid)
    begin
      o_write_pixel <= 1;
      o_x <= x_pipe[PIPELINE_WIDTH];
      o_y <= y_pipe[PIPELINE_WIDTH];
      o_r <= `SATURATE(8'd0, 8'd255, (r_pipe[PIPELINE_WIDTH]));
      o_g <= `SATURATE(8'd0, 8'd255, (g_pipe[PIPELINE_WIDTH]));
      o_b <= `SATURATE(8'd0, 8'd255, (b_pipe[PIPELINE_WIDTH]));
    end
    else
    begin
      o_write_pixel <= 0;
      o_x <= 32'bx;
      o_y <= 32'bx;
      o_r <= 32'bx;
      o_g <= 32'bx;
      o_b <= 32'bx;
    end
  end

endmodule