data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/demux.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/demux.v:43: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module demux
    #(
      parameter C_OUTPUTS = 12,
      parameter C_WIDTH = 1
      )
    (
     input [C_WIDTH-1:0]            WR_DATA,
     input [clog2s(C_OUTPUTS)-1:0]  WR_SEL,
     output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA
     );
    genvar                          i;
    reg [C_OUTPUTS*C_WIDTH-1:0]     _rOut;
    assign RD_DATA = _rOut;
    always @(*) begin
        _rOut = 0;
        _rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
    end
endmodule
module demux
    #(
      parameter C_OUTPUTS = 12,
      parameter C_WIDTH = 1
      )
    (
     input [C_WIDTH-1:0]            WR_DATA,
     input [clog2s(C_OUTPUTS)-1:0]  WR_SEL,
     output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA
     );

    genvar                          i;
    reg [C_OUTPUTS*C_WIDTH-1:0]     _rOut;
    assign RD_DATA = _rOut;
    always @(*) begin
        _rOut = 0;
        _rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
    end
endmodule