data/full_repos/permissive/529706848/verilog/tb_user_module.v
1: b'%Error: data/full_repos/permissive/529706848/verilog/tb_user_module.v:27: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_user_module.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_user_module();


wire [7:0] inputs;
wire [7:0] outputs;

reg [2:0] state_in;
wire [2:0] next_state;

reg [2:0] sym_in;
wire [2:0] new_sym;

wire direction;

assign inputs = {1'b0, sym_in, state_in, 1'b0};
assign next_state = outputs[7:5];
assign new_sym = outputs[4:2];
assign direction = outputs[1];

user_module_PROJECT_ID um(
    .io_in(inputs),
    .io_out(outputs)
);

integer i;
initial begin
    $dumpvars;
    sym_in = 3'b0;
    #10;
    for (i = 0; i < 8; i = i + 1) begin
        state_in = i;

        sym_in = 3'b000;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b001;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b010;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b100;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b101;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        $display;
    end
end

endmodule
module tb_user_module();



wire [7:0] inputs;
wire [7:0] outputs;

reg [2:0] state_in;
wire [2:0] next_state;

reg [2:0] sym_in;
wire [2:0] new_sym;

wire direction;

assign inputs = {1'b0, sym_in, state_in, 1'b0};
assign next_state = outputs[7:5];
assign new_sym = outputs[4:2];
assign direction = outputs[1];

user_module_PROJECT_ID um(
    .io_in(inputs),
    .io_out(outputs)
);

integer i;
initial begin
    $dumpvars;
    sym_in = 3'b0;
    #10;
    for (i = 0; i < 8; i = i + 1) begin
        state_in = i;

        sym_in = 3'b000;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b001;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b010;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b100;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        sym_in = 3'b101;
        #10;
        $display("in 0b%b -> out 0b%b", inputs, outputs);
        $display("  state %c + symbol %b", "A" + state_in, sym_in);
        $display("  -> next state %c", "A" + next_state);
        $display("  -> direction %b", direction);
        #10;

        $display;
    end
end

endmodule