data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:42: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma,data/full_repos/permissive/447976230/test_exec.svh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma,data/full_repos/permissive/447976230/test_exec.svh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma,data/full_repos/permissive/447976230/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:43: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgAxiLiteBfm::*;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:54: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  AxiLiteBfm #(32, 32) axi = new(.master(mgt_axil));\n                           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:55: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  TestExec mac_test = new();\n                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:85: Unsupported: wait statements\n    wait(!clk40_rst);\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:86: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk40);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:88: syntax error, unexpected TIME NUMBER, expecting \')\'\n    mac_test.start_test("model_10gbe::Wait for phy reset done", 150us);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:89: Unsupported: wait statements\n    wait(phy_reset===1\'b0);\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:92: syntax error, unexpected TIME NUMBER, expecting \')\'\n    mac_test.start_test("model_10gbe::Wait for MAC link_up", 150us);\n                                                             ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv:94: Unsupported: wait statements\n    wait(link_up===1\'b1);\n    ^~~~\n%Error: Exiting due to 10 error(s)\n'
module model_10gbe  #(
  parameter [7:0] PORTNUM = 8'd0
)(
  input  logic areset,

  input  logic ref_clk,


  output logic tx_p,
  output logic tx_n,
  input  logic rx_p,
  input  logic rx_n,


  output logic mgt_clk,
  output logic mgt_rst,
  output logic link_up,



  AxiStreamIf.slave  mgt_tx,
  AxiStreamIf.master mgt_rx

);


  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiLiteBfm::*;
  import PkgTestExec::*;

  logic clk40,clk40_rst;
  logic clk100,clk100_rst;
  logic phy_reset;


  AxiLiteIf #(32,32)
   mgt_axil (clk40, clk40_rst);

  AxiLiteBfm #(32, 32) axi = new(.master(mgt_axil));
  TestExec mac_test = new();

  sim_clock_gen #(.PERIOD(25.0), .AUTOSTART(1))
    clk40_gen    (.clk(clk40), .rst(clk40_rst));
  sim_clock_gen #(.PERIOD(100.0), .AUTOSTART(1))
    clk100_gen    (.clk(clk100), .rst(clk100_rst));















  logic [31:0] phy_status;
  logic [31:0] mac_status;
  logic [31:0] mac_ctrl;

  initial begin : init_model
    mac_ctrl = 0;

    clk40_gen.reset();
    axi.run();
    wait(!clk40_rst);
    repeat (10) @(posedge clk40);

    mac_test.start_test("model_10gbe::Wait for phy reset done", 150us);
    wait(phy_reset===1'b0);
    mac_test.end_test();

    mac_test.start_test("model_10gbe::Wait for MAC link_up", 150us);
    mac_ctrl[0] = 1;
    wait(link_up===1'b1);
    mac_test.end_test();
  end

  logic [0:0] qpll0_reset;
  logic [0:0] qpll0_lock;
  logic [0:0] qpll0_clk;
  logic [0:0] qpll0_refclk;
  logic [0:0] qpll1_reset;
  logic [0:0] qpll1_lock;
  logic [0:0] qpll1_clk;
  logic [0:0] qpll1_refclk;

  xge_pcs_pma_common_wrapper xge_pcs_pma_common_wrapperx (
    .refclk         (ref_clk),
    .qpll0reset     (qpll0_reset),
    .qpll0lock      (qpll0_lock),
    .qpll0outclk    (qpll0_clk),
    .qpll0outrefclk (qpll0_refclk),
    .qpll1reset     (qpll1_reset),
    .qpll1lock      (qpll1_lock),
    .qpll1outclk    (qpll1_clk),
    .qpll1outrefclk (qpll1_refclk)
  );

  AxiStreamIf #(.DATA_WIDTH(64),.USER_WIDTH(4))
    eth10g_rx(mgt_clk,mgt_rst);

  always_comb begin
    mgt_rx.tdata    = eth10g_rx.tdata;
    mgt_rx.tuser    = eth10g_rx.tuser;
    mgt_rx.tkeep    = eth10g_rx.trailing2keep(eth10g_rx.tuser);
    mgt_rx.tvalid   = eth10g_rx.tvalid;
    mgt_rx.tlast    = eth10g_rx.tlast;

    if (!mgt_rst) begin
      if (!mgt_rx.tready && mgt_rx.tvalid) begin
        $error("Model 100Gbe : can't hold off the MAC");
      end
    end
  end

  eth_10g eth_10g_i (
    .areset(areset),

    .clk100(clk100),

    .qpll0_refclk   (qpll0_refclk),
    .qpll0_clk      (qpll0_clk),
    .qpll0_lock     (qpll0_lock),
    .qpll0_reset    (qpll0_reset),
    .qpll1_refclk   (qpll1_refclk),
    .qpll1_clk      (qpll1_clk),
    .qpll1_lock     (qpll1_lock),
    .qpll1_reset    (qpll1_reset),

    .tx_p(tx_p),
    .tx_n(tx_n),
    .rx_p(rx_p),
    .rx_n(rx_n),

    .mgt_clk(mgt_clk),
    .mgt_rst(mgt_rst),

    .mgt_tx(mgt_tx),




    .mgt_rx(eth10g_rx),

    .mgt_axil(mgt_axil),

    .phy_status(phy_status),
    .mac_ctrl(mac_ctrl),
    .mac_status(mac_status),
    .phy_reset(phy_reset),
    .link_up(link_up)
  );

endmodule
module model_10gbe  #(
  parameter [7:0] PORTNUM = 8'd0
)(
  input  logic areset,

  input  logic ref_clk,


  output logic tx_p,
  output logic tx_n,
  input  logic rx_p,
  input  logic rx_n,


  output logic mgt_clk,
  output logic mgt_rst,
  output logic link_up,



  AxiStreamIf.slave  mgt_tx,
  AxiStreamIf.master mgt_rx

);



  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiLiteBfm::*;
  import PkgTestExec::*;

  logic clk40,clk40_rst;
  logic clk100,clk100_rst;
  logic phy_reset;


  AxiLiteIf #(32,32)
   mgt_axil (clk40, clk40_rst);

  AxiLiteBfm #(32, 32) axi = new(.master(mgt_axil));
  TestExec mac_test = new();

  sim_clock_gen #(.PERIOD(25.0), .AUTOSTART(1))
    clk40_gen    (.clk(clk40), .rst(clk40_rst));
  sim_clock_gen #(.PERIOD(100.0), .AUTOSTART(1))
    clk100_gen    (.clk(clk100), .rst(clk100_rst));















  logic [31:0] phy_status;
  logic [31:0] mac_status;
  logic [31:0] mac_ctrl;

  initial begin : init_model
    mac_ctrl = 0;

    clk40_gen.reset();
    axi.run();
    wait(!clk40_rst);
    repeat (10) @(posedge clk40);

    mac_test.start_test("model_10gbe::Wait for phy reset done", 150us);
    wait(phy_reset===1'b0);
    mac_test.end_test();

    mac_test.start_test("model_10gbe::Wait for MAC link_up", 150us);
    mac_ctrl[0] = 1;
    wait(link_up===1'b1);
    mac_test.end_test();
  end

  logic [0:0] qpll0_reset;
  logic [0:0] qpll0_lock;
  logic [0:0] qpll0_clk;
  logic [0:0] qpll0_refclk;
  logic [0:0] qpll1_reset;
  logic [0:0] qpll1_lock;
  logic [0:0] qpll1_clk;
  logic [0:0] qpll1_refclk;

  xge_pcs_pma_common_wrapper xge_pcs_pma_common_wrapperx (
    .refclk         (ref_clk),
    .qpll0reset     (qpll0_reset),
    .qpll0lock      (qpll0_lock),
    .qpll0outclk    (qpll0_clk),
    .qpll0outrefclk (qpll0_refclk),
    .qpll1reset     (qpll1_reset),
    .qpll1lock      (qpll1_lock),
    .qpll1outclk    (qpll1_clk),
    .qpll1outrefclk (qpll1_refclk)
  );

  AxiStreamIf #(.DATA_WIDTH(64),.USER_WIDTH(4))
    eth10g_rx(mgt_clk,mgt_rst);

  always_comb begin
    mgt_rx.tdata    = eth10g_rx.tdata;
    mgt_rx.tuser    = eth10g_rx.tuser;
    mgt_rx.tkeep    = eth10g_rx.trailing2keep(eth10g_rx.tuser);
    mgt_rx.tvalid   = eth10g_rx.tvalid;
    mgt_rx.tlast    = eth10g_rx.tlast;

    if (!mgt_rst) begin
      if (!mgt_rx.tready && mgt_rx.tvalid) begin
        $error("Model 100Gbe : can't hold off the MAC");
      end
    end
  end

  eth_10g eth_10g_i (
    .areset(areset),

    .clk100(clk100),

    .qpll0_refclk   (qpll0_refclk),
    .qpll0_clk      (qpll0_clk),
    .qpll0_lock     (qpll0_lock),
    .qpll0_reset    (qpll0_reset),
    .qpll1_refclk   (qpll1_refclk),
    .qpll1_clk      (qpll1_clk),
    .qpll1_lock     (qpll1_lock),
    .qpll1_reset    (qpll1_reset),

    .tx_p(tx_p),
    .tx_n(tx_n),
    .rx_p(rx_p),
    .rx_n(rx_n),

    .mgt_clk(mgt_clk),
    .mgt_rst(mgt_rst),

    .mgt_tx(mgt_tx),




    .mgt_rx(eth10g_rx),

    .mgt_axil(mgt_axil),

    .phy_status(phy_status),
    .mac_ctrl(mac_ctrl),
    .mac_status(mac_status),
    .phy_reset(phy_reset),
    .link_up(link_up)
  );

endmodule