data/full_repos/permissive/486216880/alu.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/486216880/alu.v:13: Signal definition not found, creating implicitly: \'isEqual\'\n                                                                : ... Suggested alternative: \'isEqual_o\'\n    assign isEqual = A_i == B_i;\n           ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:36: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            0:  result = A_signed +   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:36: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            0:  result = A_signed +   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:37: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            1:  result = A_signed -   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:37: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            1:  result = A_signed -   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:38: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            2:  result = A_signed &   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:38: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            2:  result = A_signed &   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:39: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            3:  result = A_signed |   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:39: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            3:  result = A_signed |   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:40: Operator XOR expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            4:  result = A_signed ^   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:40: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            4:  result = A_signed ^   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:41: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            5:  result = A_signed <<  B_signed[4:0];  \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:42: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            6:  result = A_signed >>  B_signed[4:0];  \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:43: Operator SHIFTRS expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            7:  result = A_signed >>> B_signed[4:0];  \n                                  ^~~\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:46: Operator DIVS expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            10: result = A_signed /   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:46: Operator DIVS expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            10: result = A_signed /   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:47: Operator MODDIVS expects 64 bits on the LHS, but LHS\'s VARREF \'A_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            11: result = A_signed %   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:47: Operator MODDIVS expects 64 bits on the RHS, but RHS\'s VARREF \'B_signed\' generates 32 bits.\n                                                             : ... In instance alu\n            11: result = A_signed %   B_signed;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:48: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'1\'h1\' generates 1 bits.\n                                                             : ... In instance alu\n            12: result = (less_than_signed(A_i, B_i) ? 1\'b1 : 1\'b0);  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:48: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                             : ... In instance alu\n            12: result = (less_than_signed(A_i, B_i) ? 1\'b1 : 1\'b0);  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:49: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'1\'h1\' generates 1 bits.\n                                                             : ... In instance alu\n            13: result = (A_i < B_i ? 1\'b1 : 1\'b0);  \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/486216880/alu.v:49: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                             : ... In instance alu\n            13: result = (A_i < B_i ? 1\'b1 : 1\'b0);  \n                                    ^\n%Error: Exiting due to 22 warning(s)\n'
function [0:0] less_than_signed;
    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
    begin
    v = (x - y);
    if (x[31] != y[31])
        less_than_signed = x[31];
    else
        less_than_signed = v[31];
    end
    endfunction
function [0:0] less_than_signed;

    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
    begin
    v = (x - y);
    if (x[31] != y[31])
        less_than_signed = x[31];
    else
        less_than_signed = v[31];
    end
    endfunction