data/full_repos/permissive/488739248/rtl/ttl/ttl_74164_half.v
data/verilator_xmls/a9ce06bb-45ed-448a-bc99-125504264d39.xml
module ttl_74164_half (
    input wire A, B,
    input wire clk,
    input wire MRn,
    output reg Q0, Q1, Q2, Q3);

    localparam MRDLY = 24;
    localparam REGDLY = 19;

    wire serdata;
    assign serdata = A & B;

    always @(posedge clk, negedge MRn) begin
        if (!MRn) begin
            Q0 <= #MRDLY 1'b0;
            Q1 <= #MRDLY 1'b1;
            Q2 <= #MRDLY 1'b0;
            Q3 <= #MRDLY 1'b0;

        end else begin
            Q0 <= #REGDLY serdata;
            Q1 <= #REGDLY Q0;
            Q2 <= #REGDLY Q1;
            Q3 <= #REGDLY Q2;
        end
    end
endmodule
module ttl_74164_half (
    input wire A, B,
    input wire clk,
    input wire MRn,
    output reg Q0, Q1, Q2, Q3);


    localparam MRDLY = 24;
    localparam REGDLY = 19;

    wire serdata;
    assign serdata = A & B;

    always @(posedge clk, negedge MRn) begin
        if (!MRn) begin
            Q0 <= #MRDLY 1'b0;
            Q1 <= #MRDLY 1'b1;
            Q2 <= #MRDLY 1'b0;
            Q3 <= #MRDLY 1'b0;

        end else begin
            Q0 <= #REGDLY serdata;
            Q1 <= #REGDLY Q0;
            Q2 <= #REGDLY Q1;
            Q3 <= #REGDLY Q2;
        end
    end
endmodule