data/full_repos/permissive/43858668/final_verilog/src/clib/c_clkgate.v
data/verilator_xmls/af1a5e99-3043-4b5d-a0c5-e632d5f8378f.xml
module c_clkgate
  (clk, active, clk_gated);
   
   input clk;
   input active;
   
   output clk_gated;
   wire clk_gated;
   
   reg 	active_q;
   always @(clk, active)
     begin
	if(clk == 0)
          active_q <= active;
     end
   
   assign clk_gated = clk & active_q;
   
endmodule
module c_clkgate
  (clk, active, clk_gated);

   
   input clk;
   input active;
   
   output clk_gated;
   wire clk_gated;
   
   reg 	active_q;
   always @(clk, active)
     begin
	if(clk == 0)
          active_q <= active;
     end
   
   assign clk_gated = clk & active_q;
   
endmodule