data/full_repos/permissive/484799296/verilog/buffer_tri/buffer_tri.v
data/verilator_xmls/cee19439-5e16-49ed-bb3d-f136eaa2805f.xml
module buffer_tri (
    input enable,
    input [7:0] in,
    output [7:0] out
);

    assign out = enable?in:8'bzzzz_zzzz;

endmodule
module buffer_tri (
    input enable,
    input [7:0] in,
    output [7:0] out
);


    assign out = enable?in:8'bzzzz_zzzz;

endmodule