data/full_repos/permissive/48250786/test_memkey.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #20 add = add + 1; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_memkey.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n%Error: data/full_repos/permissive/48250786/test_memkey.v:36: Cannot find file containing module: \'keymem\'\n keymem uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/keymem\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/keymem.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/keymem.sv\n             keymem\n             keymem.v\n             keymem.sv\n             obj_dir/keymem\n             obj_dir/keymem.v\n             obj_dir/keymem.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_memkey;


	reg [3:0] add;
	reg clock;
	reg en;


	wire [127:0] dout;


	keymem uut (
		.dout(dout), 
		.add(add), 
		.clock(clock), 
		.en(en)
	);
	
	always begin
		clock = 0;
		#10;
		clock = 1;
		#10;
	end
	

	initial begin

		add = 0;
		en = 1;
		
      #20 add = add + 1; 
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;

		#20 add = add + 1; 
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;

	end
      
endmodule
module test_memkey;



	reg [3:0] add;
	reg clock;
	reg en;


	wire [127:0] dout;


	keymem uut (
		.dout(dout), 
		.add(add), 
		.clock(clock), 
		.en(en)
	);
	
	always begin
		clock = 0;
		#10;
		clock = 1;
		#10;
	end
	

	initial begin

		add = 0;
		en = 1;
		
      #20 add = add + 1; 
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;

		#20 add = add + 1; 
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;
		#20 add = add + 1;

	end
      
endmodule