data/full_repos/permissive/456818331/rtl/Average3x3.v
1: b'%Warning-WIDTH: data/full_repos/permissive/456818331/rtl/Average3x3.v:108: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'k22_reg\' generates 14 bits.\n                                                                         : ... In instance Average3x3\n                add_delay_04 <= k22_reg;\n                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/456818331/rtl/Average3x3.v:128: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_delay_04\' generates 15 bits.\n                                                                         : ... In instance Average3x3\n                add_delay_12 <= add_delay_04;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/456818331/rtl/Average3x3.v:145: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_delay_12\' generates 16 bits.\n                                                                         : ... In instance Average3x3\n                add_delay_21 <= add_delay_12;\n                             ^~\n%Error: Exiting due to 3 warning(s)\n'
function integer clogb2(input integer bit_depth);
    begin
        for(clogb2 = 0;bit_depth >0; clogb2 = clogb2 + 1)
            bit_depth = bit_depth >> 1;
    end
endfunction
function integer clogb2(input integer bit_depth);

    begin
        for(clogb2 = 0;bit_depth >0; clogb2 = clogb2 + 1)
            bit_depth = bit_depth >> 1;
    end
endfunction