data/full_repos/permissive/501791642/src/nco/nco.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/501791642/src/nco/nco.v:17: Signal definition not found, creating implicitly: \'LED\'\nassign LED = sample_out;\n       ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/501791642/src/nco/nco.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'sample_out\' generates 8 bits.\n                                                                     : ... In instance nco\nassign LED = sample_out;\n           ^\n%Error: data/full_repos/permissive/501791642/src/nco/nco.v:28: Cannot find file containing module: \'prescaler\'\nprescaler #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/src/nco,data/full_repos/permissive/501791642/prescaler\n             data/full_repos/permissive/501791642/src/nco,data/full_repos/permissive/501791642/prescaler.v\n             data/full_repos/permissive/501791642/src/nco,data/full_repos/permissive/501791642/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: data/full_repos/permissive/501791642/src/nco/nco.v:40: Cannot find file containing module: \'register\'\nregister #(\n^~~~~~~~\n%Error: data/full_repos/permissive/501791642/src/nco/nco.v:52: Cannot find file containing module: \'step_size_rom\'\nstep_size_rom step_rom (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501791642/src/nco/nco.v:59: Cannot find file containing module: \'phase2sample\'\nphase2sample sampler( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501791642/src/nco/nco.v:68: Cannot find file containing module: \'volume_rom\'\nvolume_rom vel_rom (\n^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module nco (
	input CLK,
	input CE,
	input [6:0] NOTE_NUM,
	input [6:0] NOTE_VEL,
	input [6:0] PROGRAM,
	output[7:0] SAMPLE_OUT,
	output TRIG
);


wire trig_sample;
wire [7:0] sample_out;
wire [7:0] sample;

assign SAMPLE_OUT = sample_out;
assign LED = sample_out;
assign TRIG = trig_sample;

wire [15:0] step;
wire [15:0] phase_add_out;
wire [15:0] phase_reg_out;

assign phase_add_out = phase_reg_out + step;



prescaler #(

	.MODULO(3125),
	.W(12)
)
sample_rate
(
	.CLK(CLK),
	.CE(1'd1),
	.CEO(trig_sample)
);

register #(
    .W(16)
)
phase_reg
(
    .CLK(CLK),
    .CE(trig_sample),
    .D(phase_add_out),
    .Q(phase_reg_out)
);


step_size_rom step_rom (
	.CLK(CLK),
	.CE(CE),
	.A(NOTE_NUM),
	.D(step)
);

phase2sample sampler( 
    .CLK(CLK),
    .CE(CE),
    .PHASE(phase_reg_out[15:9]),
    .PROGRAM(PROGRAM),
    .SAMPLE(sample)
);


volume_rom vel_rom (
	.CLK(CLK),
	.CE(CE),
	.SAMPLE(sample),
	.VEL(NOTE_VEL),
	.SAMPLE_OUT(sample_out)
);


endmodule
module nco (
	input CLK,
	input CE,
	input [6:0] NOTE_NUM,
	input [6:0] NOTE_VEL,
	input [6:0] PROGRAM,
	output[7:0] SAMPLE_OUT,
	output TRIG
);



wire trig_sample;
wire [7:0] sample_out;
wire [7:0] sample;

assign SAMPLE_OUT = sample_out;
assign LED = sample_out;
assign TRIG = trig_sample;

wire [15:0] step;
wire [15:0] phase_add_out;
wire [15:0] phase_reg_out;

assign phase_add_out = phase_reg_out + step;



prescaler #(

	.MODULO(3125),
	.W(12)
)
sample_rate
(
	.CLK(CLK),
	.CE(1'd1),
	.CEO(trig_sample)
);

register #(
    .W(16)
)
phase_reg
(
    .CLK(CLK),
    .CE(trig_sample),
    .D(phase_add_out),
    .Q(phase_reg_out)
);


step_size_rom step_rom (
	.CLK(CLK),
	.CE(CE),
	.A(NOTE_NUM),
	.D(step)
);

phase2sample sampler( 
    .CLK(CLK),
    .CE(CE),
    .PHASE(phase_reg_out[15:9]),
    .PROGRAM(PROGRAM),
    .SAMPLE(sample)
);


volume_rom vel_rom (
	.CLK(CLK),
	.CE(CE),
	.SAMPLE(sample),
	.VEL(NOTE_VEL),
	.SAMPLE_OUT(sample_out)
);


endmodule