data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:61: Cannot find file containing module: \'tc141_fflopx\'\ntc141_fflopx #(ADDR+1,{ADDR+1{1\'b0}},1)    cr_addr(wclk,wrst,nxt_addr,addr);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx.sv\n             tc141_fflopx\n             tc141_fflopx.v\n             tc141_fflopx.sv\n             obj_dir/tc141_fflopx\n             obj_dir/tc141_fflopx.v\n             obj_dir/tc141_fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:64: Cannot find file containing module: \'tc141_fflopx\'\ntc141_fflopx #(ADDR+1,{ADDR+1{1\'b0}},1)    cr_gaddr(wclk,wrst,nxt_gaddr,gaddr);\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:67: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'inc\' generates 1 bits.\n                                                                                                                                           : ... In instance af4eos_agg_wprt_ctrl\nassign              nxt_addr = addr + inc;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:68: Cannot find file containing module: \'af4eos_agg_bin2gray\'\naf4eos_agg_bin2gray #(ADDR+1) bin2gray(.b(nxt_addr),.g(nxt_gaddr));\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:70: Cannot find file containing module: \'tc141_fflopx\'\ntc141_fflopx #(ADDR+1,{ADDR+1{1\'b0}},1)    cr_grprt1(wclk,wrst,grprt ,grprt1);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:71: Cannot find file containing module: \'tc141_fflopx\'\ntc141_fflopx #(ADDR+1,{ADDR+1{1\'b0}},1)    cr_grprt2(wclk,wrst,grprt1,grprt2);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:77: Cannot find file containing module: \'af4eos_agg_gray2bin\'\naf4eos_agg_gray2bin #(ADDR+1) gray2bin(.g(grprt2),.b(brprt));\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:88: Cannot find file containing module: \'fflopnx\'\nfflopnx #(1)         cr_wfull (wclk,wrst,full ,wfull);\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:89: Cannot find file containing module: \'fflopnx\'\nfflopnx #(1)         cr_whfull(wclk,wrst,hfull,whfull);\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_wprt_ctrl.v:90: Cannot find file containing module: \'fflopnx\'\nfflopnx #(ADDR+1)    cr_wlen  (wclk,wrst,len,wlen);\n^~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module af4eos_agg_wprt_ctrl
    (
     wrst,
     wclk,
     wen,
     waddr,
     gwprt,
     grprt,
     wfull,
     whfull,
     wlen
     );



parameter           ADDR = 8;
parameter           DEP = 256;



input               wrst;
input               wclk;
input               wen;
output [ADDR-1:0]   waddr;
output [ADDR:0]     gwprt;
input [ADDR:0]      grprt;
output              wfull;
output              whfull;
output [ADDR:0]     wlen;



wire                wrst;
wire                wclk;
wire                wen;
wire [ADDR-1:0]     waddr;
wire [ADDR:0]       gwprt;
wire [ADDR:0]       grprt;
wire                wfull;
wire                whfull;



wire [ADDR:0]       addr;
wire [ADDR:0]       nxt_addr;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_addr(wclk,wrst,nxt_addr,addr);
wire [ADDR:0]       gaddr;
wire [ADDR:0]       nxt_gaddr;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_gaddr(wclk,wrst,nxt_gaddr,gaddr);
wire                inc;
assign              inc = (~wfull) & wen;
assign              nxt_addr = addr + inc;
af4eos_agg_bin2gray #(ADDR+1) bin2gray(.b(nxt_addr),.g(nxt_gaddr));
wire [ADDR:0]       grprt1,grprt2;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_grprt1(wclk,wrst,grprt ,grprt1);
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_grprt2(wclk,wrst,grprt1,grprt2);
wire                full;

wire                hfull;

wire [ADDR:0]       brprt;
af4eos_agg_gray2bin #(ADDR+1) gray2bin(.g(grprt2),.b(brprt));
wire [ADDR:0]       len;
assign              len     = nxt_addr - brprt;

assign              full    = (len == DEP-1);
assign              hfull   = |len[ADDR:ADDR-1];



assign              waddr = addr[ADDR-1:0];
assign              gwprt = gaddr;
fflopnx #(1)         cr_wfull (wclk,wrst,full ,wfull);
fflopnx #(1)         cr_whfull(wclk,wrst,hfull,whfull);
fflopnx #(ADDR+1)    cr_wlen  (wclk,wrst,len,wlen);




endmodule
module af4eos_agg_wprt_ctrl
    (
     wrst,
     wclk,
     wen,
     waddr,
     gwprt,
     grprt,
     wfull,
     whfull,
     wlen
     );




parameter           ADDR = 8;
parameter           DEP = 256;



input               wrst;
input               wclk;
input               wen;
output [ADDR-1:0]   waddr;
output [ADDR:0]     gwprt;
input [ADDR:0]      grprt;
output              wfull;
output              whfull;
output [ADDR:0]     wlen;



wire                wrst;
wire                wclk;
wire                wen;
wire [ADDR-1:0]     waddr;
wire [ADDR:0]       gwprt;
wire [ADDR:0]       grprt;
wire                wfull;
wire                whfull;



wire [ADDR:0]       addr;
wire [ADDR:0]       nxt_addr;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_addr(wclk,wrst,nxt_addr,addr);
wire [ADDR:0]       gaddr;
wire [ADDR:0]       nxt_gaddr;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_gaddr(wclk,wrst,nxt_gaddr,gaddr);
wire                inc;
assign              inc = (~wfull) & wen;
assign              nxt_addr = addr + inc;
af4eos_agg_bin2gray #(ADDR+1) bin2gray(.b(nxt_addr),.g(nxt_gaddr));
wire [ADDR:0]       grprt1,grprt2;
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_grprt1(wclk,wrst,grprt ,grprt1);
tc141_fflopx #(ADDR+1,{ADDR+1{1'b0}},1)    cr_grprt2(wclk,wrst,grprt1,grprt2);
wire                full;

wire                hfull;

wire [ADDR:0]       brprt;
af4eos_agg_gray2bin #(ADDR+1) gray2bin(.g(grprt2),.b(brprt));
wire [ADDR:0]       len;
assign              len     = nxt_addr - brprt;

assign              full    = (len == DEP-1);
assign              hfull   = |len[ADDR:ADDR-1];



assign              waddr = addr[ADDR-1:0];
assign              gwprt = gaddr;
fflopnx #(1)         cr_wfull (wclk,wrst,full ,wfull);
fflopnx #(1)         cr_whfull(wclk,wrst,hfull,whfull);
fflopnx #(ADDR+1)    cr_wlen  (wclk,wrst,len,wlen);




endmodule