data/full_repos/permissive/435516446/MIPS/SignExtension.v
data/verilator_xmls/8e902895-fd99-439d-b4c8-74a9d89ed4a0.xml
module SignExtension(
    input clock,
    input [15:0] value,
    output reg [31:0] sign_extended_value
    );
	 
	 
	always @ (negedge clock) 
	begin
		sign_extended_value = {{16{value[15]}}, value[15:0]};
	end

endmodule
module SignExtension(
    input clock,
    input [15:0] value,
    output reg [31:0] sign_extended_value
    );

	 
	 
	always @ (negedge clock) 
	begin
		sign_extended_value = {{16{value[15]}}, value[15:0]};
	end

endmodule