data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp12anon5/reference/MultiClockSpecanonfun22anonfunapplymcVsp12anon5.v
data/verilator_xmls/9272881c-134c-485f-9a70-d6ede1ec1a41.xml
module BITWISEAND(y, a, b);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a & b;
endmodule
module BITWISEAND(y, a, b);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a & b;
endmodule