data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:90: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:96: syntax error, unexpected \'@\'\n  @(posedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:104: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:110: syntax error, unexpected \';\'\n for (i=0;i<9;i=i+1)begin\n             ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:110: syntax error, unexpected \')\', expecting \';\'\n for (i=0;i<9;i=i+1)begin\n                   ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:118: syntax error, unexpected \'@\'\n  @(posedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:129: syntax error, unexpected $stop\n $stop;\n ^~~~~\n%Error: data/full_repos/permissive/436253691/hardware/testbench/FIFO_tb.v:139: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO_tb();


parameter tb_data_width=16;
parameter tb_fifo_size=720;
parameter tb_addr_width=10;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_rdptclr;
reg tb_wrptclr;
reg tb_rdinc;
reg tb_wrdinc;
reg tb_wren;
reg tb_ren;
reg [tb_data_width-1:0] tb_data_in;



wire [tb_data_width-1:0] tb_data_out;
reg [tb_data_width-1:0] tb_expected_output;




FIFO #(.DATA_WIDTH(tb_data_width),.FIFO_SIZE(tb_fifo_size), .ADDR_WIDTH(tb_addr_width)) Fifo
(
.FIFO_Clk(tb_clk),
.FIFO_Rdptclr(tb_rdptclr),
.FIFO_Wrptclr(tb_wrptclr),
.FIFO_Rdinc(tb_rdinc),
.FIFO_Wrinc(tb_wrdinc),
.FIFO_Wen(tb_wren),
.FIFO_Ren(tb_ren),
.FIFO_Data_in(tb_data_in),
.FIFO_Data_out(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	tb_rdptclr<=0;
	tb_wrptclr<=0;
	tb_rdinc<=1;
	tb_wrdinc<=1;
	tb_wren<=0;
	tb_ren<=0;
	tb_data_in<=0;
	tb_expected_output<=0;
	
	

	for (i=0;i<9;i=i+1)begin
		
		@(negedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_data_in<=i+1;
		tb_wren<=1;
		
		@(posedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_data_in<=i+1;
		tb_wren<=0;
		
	end
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_wren<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	for (i=0;i<9;i=i+1)begin
		
		@(negedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_rdinc<=1;
		tb_wrdinc<=1;
		
		@(posedge tb_clk)
		
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_rdinc<=1;
		tb_wrdinc<=1;
		tb_wren<=0;
		tb_ren<=1;
		tb_expected_output<=i+1;
	end
	
	$stop;
	
	
	
end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask



endmodule
module FIFO_tb();



parameter tb_data_width=16;
parameter tb_fifo_size=720;
parameter tb_addr_width=10;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_rdptclr;
reg tb_wrptclr;
reg tb_rdinc;
reg tb_wrdinc;
reg tb_wren;
reg tb_ren;
reg [tb_data_width-1:0] tb_data_in;



wire [tb_data_width-1:0] tb_data_out;
reg [tb_data_width-1:0] tb_expected_output;




FIFO #(.DATA_WIDTH(tb_data_width),.FIFO_SIZE(tb_fifo_size), .ADDR_WIDTH(tb_addr_width)) Fifo
(
.FIFO_Clk(tb_clk),
.FIFO_Rdptclr(tb_rdptclr),
.FIFO_Wrptclr(tb_wrptclr),
.FIFO_Rdinc(tb_rdinc),
.FIFO_Wrinc(tb_wrdinc),
.FIFO_Wen(tb_wren),
.FIFO_Ren(tb_ren),
.FIFO_Data_in(tb_data_in),
.FIFO_Data_out(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	tb_rdptclr<=0;
	tb_wrptclr<=0;
	tb_rdinc<=1;
	tb_wrdinc<=1;
	tb_wren<=0;
	tb_ren<=0;
	tb_data_in<=0;
	tb_expected_output<=0;
	
	

	for (i=0;i<9;i=i+1)begin
		
		@(negedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_data_in<=i+1;
		tb_wren<=1;
		
		@(posedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_data_in<=i+1;
		tb_wren<=0;
		
	end
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_wren<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	for (i=0;i<9;i=i+1)begin
		
		@(negedge tb_clk)
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_rdinc<=1;
		tb_wrdinc<=1;
		
		@(posedge tb_clk)
		
		tb_rdptclr<=1;
		tb_wrptclr<=1;
		tb_rdinc<=1;
		tb_wrdinc<=1;
		tb_wren<=0;
		tb_ren<=1;
		tb_expected_output<=i+1;
	end
	
	$stop;
	
	
	
end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask



endmodule