data/full_repos/permissive/441359809/src/yosys/tests/simple/implicit_ports.v
data/verilator_xmls/18a3ce0e-ca3b-4355-ab08-e39c1c3b4404.xml
module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
	assign cout = cin;
	assign result = a + b;
endmodule
module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);

	assign cout = cin;
	assign result = a + b;
endmodule