data/full_repos/permissive/435885222/sources/ex_mem.v
data/verilator_xmls/6af384a4-cf61-40f5-a154-7ada898fec2c.xml
module ex_mem(
    input clk,
    input rst,
    input [4:0] ex_wd,
    input ex_wreg,
    input [31:0] ex_wdata,
    input [7:0] ex_aluop,
    input [31:0] ex_mem_addr,
    input [31:0] ex_reg2,
    output reg[4:0] mem_wd,
    output reg mem_wreg,
    output reg[31:0] mem_wdata,
    output reg[7:0] mem_aluop,
    output reg[31:0] mem_mem_addr,
    output reg[31:0] mem_reg2
    );
    always @(posedge clk)begin
        if(rst==1'b1)begin
            mem_wd<=5'b00000;
            mem_wreg<=1'b0;
            mem_wdata<=32'h00000000;
            mem_aluop<=8'b00000000;
            mem_mem_addr<=32'h00000000;
            mem_reg2<=32'h00000000;
        end else begin
            mem_wd<=ex_wd;
            mem_wreg<=ex_wreg;
            mem_wdata<=ex_wdata;
            mem_aluop<=ex_aluop;
            mem_mem_addr<=ex_mem_addr;
            mem_reg2<=ex_reg2;
        end
    end
endmodule
module ex_mem(
    input clk,
    input rst,
    input [4:0] ex_wd,
    input ex_wreg,
    input [31:0] ex_wdata,
    input [7:0] ex_aluop,
    input [31:0] ex_mem_addr,
    input [31:0] ex_reg2,
    output reg[4:0] mem_wd,
    output reg mem_wreg,
    output reg[31:0] mem_wdata,
    output reg[7:0] mem_aluop,
    output reg[31:0] mem_mem_addr,
    output reg[31:0] mem_reg2
    );

    always @(posedge clk)begin
        if(rst==1'b1)begin
            mem_wd<=5'b00000;
            mem_wreg<=1'b0;
            mem_wdata<=32'h00000000;
            mem_aluop<=8'b00000000;
            mem_mem_addr<=32'h00000000;
            mem_reg2<=32'h00000000;
        end else begin
            mem_wd<=ex_wd;
            mem_wreg<=ex_wreg;
            mem_wdata<=ex_wdata;
            mem_aluop<=ex_aluop;
            mem_mem_addr<=ex_mem_addr;
            mem_reg2<=ex_reg2;
        end
    end
endmodule