data/full_repos/permissive/441359809/src/yosys/tests/proc/bug_1268.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/proc/bug_1268.v:13: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'gold\'\nmodule gold (input clock, ctrl, din, output reg dout);\n       ^~~~\n                                                                                          : ... Top module \'gate\'\nmodule gate (input clock, ctrl, din, output reg dout);\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module gate (input clock, ctrl, din, output reg dout);
	always @(posedge clock) begin
		if (1'b1) begin
			if (1'b0) begin end else begin
				dout <= 0;
			end
		end
		if (ctrl)
			dout <= din;
	end
endmodule
module gate (input clock, ctrl, din, output reg dout);

	always @(posedge clock) begin
		if (1'b1) begin
			if (1'b0) begin end else begin
				dout <= 0;
			end
		end
		if (ctrl)
			dout <= din;
	end
endmodule