data/full_repos/permissive/479923049/datapath_tb.v
1: b'%Error: data/full_repos/permissive/479923049/datapath_tb.v:19: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n    task checker; \n         ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    task checker; \n                ^\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:22: syntax error, unexpected begin\n        begin \n        ^~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:63: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b0000_0000_0001_0111, 3\'b000);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:91: syntax error, unexpected $display\n            $display("ERROR ** regfile is %d, expected %d",  datapath_tb.DUT.REGFILE.R2, 16\'d16 );\n            ^~~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:94: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d16, 3\'b000);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:107: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d0, 3\'b001);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:127: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b0000_0000_0000_0000, 3\'b001);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:148: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b1111_1111_1111_1110, 3\'b110);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath_tb.v:151: syntax error, unexpected $display\n        if( ~err ) $display("PASSED");\n                   ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module datapath_tb;
    reg clk, loada, loadb, asel, bsel, loadc, loads, write;
    reg [1:0] vsel;
    reg [2:0] readnum; 
    reg [1:0] shift;
    reg [1:0] ALUop;
    reg [2:0] writenum;
    reg [15:0] sximm8;
    reg [15:0] sximm5;
    reg [15:0] mdata;
    reg [7:0] PC;
    wire [2:0] status_out; 
    wire [15:0] datapath_out;

    reg err; 

    datapath DUT (clk, readnum, vsel, loada, loadb, shift, asel, bsel, ALUop, loadc, loads, writenum, write, mdata, sximm8, sximm5, PC, status_out, datapath_out);
    
    task checker; 
        input [15:0] expected_datapath_out;
        input [2:0] expected_status_out;
        begin 
            if( datapath_out !== expected_datapath_out ) begin
            $display("ERROR ** datapath output is %d, expected %d", datapath_out, expected_datapath_out );
            err = 1'b1;
            end
      
            if( status_out !== expected_status_out) begin
            $display("ERROR ** status output is %b, expected %b", status_out, expected_status_out );
            err = 1'b1;
            end
        end
    endtask

    initial begin
        clk = 0; #5;
        forever begin
            clk = 1; #5;
            clk = 0; #5;
        end
    end

    initial begin 
        err = 1'b0;        

        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_1111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0000_0000_0000_1000; writenum = 3'b001; 
        #10;
        readnum = 3'b001; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b00;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;
        checker(16'b0000_0000_0001_0111, 3'b000);
        




        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_0111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b0; loadb = 1'b1;
        #10;
        sximm8 = 16'b0000_0000_0000_0010; writenum = 3'b001;
        #10;
        readnum = 3'b001; loada = 1'b1; loadb = 1'b0;
        #10
        shift = 2'b01;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1; 
        #10;
        vsel = 2'b11; writenum = 3'b010; 
        #10;
        readnum = 3'b010;
        #10;
        if( datapath_tb.DUT.REGFILE.R2 !== 16'd16) begin
            $display("ERROR ** regfile is %d, expected %d",  datapath_tb.DUT.REGFILE.R2, 16'd16 );
            err = 1'b1; 
        end
        checker(16'd16, 3'b000);


        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_0000; writenum = 3'b011; write = 1'b1; 
        #10;
        readnum = 3'b011; loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0101_0110_0000_1111; writenum = 3'b010; write = 1'b1; 
        #10;
        readnum = 3'b010; loada = 1'b0; loadb = 1'b1;
        #10;
        asel = 1'b0; bsel = 1'b0; ALUop = 2'b10; loadc = 1'b1; loads = 1'b1; #10;
        #10;
        checker(16'd0, 3'b001);


        vsel = 2'b11; sximm8 = 16'b0000_0000_0000_0000; #10;
        writenum = 3'b011; write = 1'b1;
        #10;
        readnum = 3'b011; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b1011_1111_1111_1111; writenum = 3'b100; 
        #10;
        readnum = 3'b100; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b11;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b10; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;    
        checker(16'b0000_0000_0000_0000, 3'b001);
                


        vsel = 2'b01; sximm8 = 16'b0111_1111_1111_1111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0111_1111_1111_1111; writenum = 3'b001; 
        #10;
        readnum = 3'b001; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b00;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;
        checker(16'b1111_1111_1111_1110, 3'b110);

        
        if( ~err ) $display("PASSED");
        else $display("FAILED");
        $stop;


    end
endmodule
module datapath_tb;

    reg clk, loada, loadb, asel, bsel, loadc, loads, write;
    reg [1:0] vsel;
    reg [2:0] readnum; 
    reg [1:0] shift;
    reg [1:0] ALUop;
    reg [2:0] writenum;
    reg [15:0] sximm8;
    reg [15:0] sximm5;
    reg [15:0] mdata;
    reg [7:0] PC;
    wire [2:0] status_out; 
    wire [15:0] datapath_out;

    reg err; 

    datapath DUT (clk, readnum, vsel, loada, loadb, shift, asel, bsel, ALUop, loadc, loads, writenum, write, mdata, sximm8, sximm5, PC, status_out, datapath_out);
    
    task checker; 
        input [15:0] expected_datapath_out;
        input [2:0] expected_status_out;
        begin 
            if( datapath_out !== expected_datapath_out ) begin
            $display("ERROR ** datapath output is %d, expected %d", datapath_out, expected_datapath_out );
            err = 1'b1;
            end
      
            if( status_out !== expected_status_out) begin
            $display("ERROR ** status output is %b, expected %b", status_out, expected_status_out );
            err = 1'b1;
            end
        end
    endtask

    initial begin
        clk = 0; #5;
        forever begin
            clk = 1; #5;
            clk = 0; #5;
        end
    end

    initial begin 
        err = 1'b0;        

        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_1111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0000_0000_0000_1000; writenum = 3'b001; 
        #10;
        readnum = 3'b001; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b00;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;
        checker(16'b0000_0000_0001_0111, 3'b000);
        




        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_0111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b0; loadb = 1'b1;
        #10;
        sximm8 = 16'b0000_0000_0000_0010; writenum = 3'b001;
        #10;
        readnum = 3'b001; loada = 1'b1; loadb = 1'b0;
        #10
        shift = 2'b01;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1; 
        #10;
        vsel = 2'b11; writenum = 3'b010; 
        #10;
        readnum = 3'b010;
        #10;
        if( datapath_tb.DUT.REGFILE.R2 !== 16'd16) begin
            $display("ERROR ** regfile is %d, expected %d",  datapath_tb.DUT.REGFILE.R2, 16'd16 );
            err = 1'b1; 
        end
        checker(16'd16, 3'b000);


        vsel = 2'b01; sximm8 = 16'b0000_0000_0000_0000; writenum = 3'b011; write = 1'b1; 
        #10;
        readnum = 3'b011; loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0101_0110_0000_1111; writenum = 3'b010; write = 1'b1; 
        #10;
        readnum = 3'b010; loada = 1'b0; loadb = 1'b1;
        #10;
        asel = 1'b0; bsel = 1'b0; ALUop = 2'b10; loadc = 1'b1; loads = 1'b1; #10;
        #10;
        checker(16'd0, 3'b001);


        vsel = 2'b11; sximm8 = 16'b0000_0000_0000_0000; #10;
        writenum = 3'b011; write = 1'b1;
        #10;
        readnum = 3'b011; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b1011_1111_1111_1111; writenum = 3'b100; 
        #10;
        readnum = 3'b100; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b11;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b10; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;    
        checker(16'b0000_0000_0000_0000, 3'b001);
                


        vsel = 2'b01; sximm8 = 16'b0111_1111_1111_1111; #10;
        writenum = 3'b000; write = 1'b1;
        #10;
        readnum = 3'b000; #10;
        loada = 1'b1; loadb = 1'b0;
        #10;
        sximm8 = 16'b0111_1111_1111_1111; writenum = 3'b001; 
        #10;
        readnum = 3'b001; loada = 1'b0; loadb = 1'b1;
        #10
        shift = 2'b00;
        #10;
        asel = 1'b0; bsel = 1'b0; 
        #10;
        ALUop = 2'b00; #10;
        loadc = 1'b1; loads = 1'b1;
        #10;
        checker(16'b1111_1111_1111_1110, 3'b110);

        
        if( ~err ) $display("PASSED");
        else $display("FAILED");
        $stop;


    end
endmodule