data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:53: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:54: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:55: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:62: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:63: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516842842/verilog/rtl/user_proj_example.v:78: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module homegrown_watch #(
    parameter BITS = 2
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    

    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb


);

    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [BITS-1:0] count;

    wire la_write;








    assign io_out = count;
    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};





    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = la_data_in[63]; 




    counter #(
        .BITS(BITS)
    ) counter(
        .trigger(la_write),
        .count(count)
    );

endmodule
module homegrown_watch #(
    parameter BITS = 2
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    

    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb


);


    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [BITS-1:0] count;

    wire la_write;








    assign io_out = count;
    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};





    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = la_data_in[63]; 




    counter #(
        .BITS(BITS)
    ) counter(
        .trigger(la_write),
        .count(count)
    );

endmodule