data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n# 10 a= 19\'d 65536;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n# 10 a=19\'d 123456;\n^\n%Warning-STMTDLY: data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#100 $finish;\n^\n%Error: data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v:23: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fxd2float.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/422146575/Simulations/pre_synthesis/fxd2float_tb.v:24: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, fxd2float_tb);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fxd2float_tb;
parameter in = 19;
parameter man = 23;
parameter exp = 8;
reg [in-1:0] a;

wire [exp+man:0] b;
wire zro;

fxd2flot u1 (a, b, zro);

initial
begin
a=19'd 1024;
# 10 a= 19'd 65536;
# 10 a=19'd 123456;
	  
#100 $finish;
end

initial 
begin
	$dumpfile("fxd2float.vcd");
	$dumpvars(0, fxd2float_tb);

end

endmodule
module fxd2float_tb;

parameter in = 19;
parameter man = 23;
parameter exp = 8;
reg [in-1:0] a;

wire [exp+man:0] b;
wire zro;

fxd2flot u1 (a, b, zro);

initial
begin
a=19'd 1024;
# 10 a= 19'd 65536;
# 10 a=19'd 123456;
	  
#100 $finish;
end

initial 
begin
	$dumpfile("fxd2float.vcd");
	$dumpvars(0, fxd2float_tb);

end

endmodule