data/full_repos/permissive/461620575/Galaga on FPGA/VGA/vga_control.v
1: b'%Error: Cannot find file containing module: on\n        ... Looked in:\n             data/full_repos/permissive/461620575/Galaga/on\n             data/full_repos/permissive/461620575/Galaga/on.v\n             data/full_repos/permissive/461620575/Galaga/on.sv\n             on\n             on.v\n             on.sv\n             obj_dir/on\n             obj_dir/on.v\n             obj_dir/on.sv\n%Error: Cannot find file containing module: FPGA/VGA,data/full_repos/permissive/461620575\n%Error: Cannot find file containing module: data/full_repos/permissive/461620575/Galaga\n%Error: Cannot find file containing module: FPGA/VGA/vga_control.v\n%Error: Exiting due to 4 error(s)\n'
module vga_control (clk, rst, hsync, vsync, vga_blank_n, vga_clk, hcount, vcount);
	input clk, rst;
	output hsync, vsync;
	output reg vga_blank_n, vga_clk;
	output reg [9:0] hcount, vcount;
	



	localparam H_SYNC        = 10'd96;
	localparam H_FRONT_PORCH = 10'd16;
	localparam H_DISPLAY_INT = 10'd640;
	localparam H_BACK_PORCH  = 10'd48;
	localparam H_TOTAL       = 10'd800;
	
	localparam V_SYNC        = 10'd2;
	localparam V_BACK_PORCH  = 10'd33;
	localparam V_DISPLAY_INT = 10'd480;
	localparam V_FRONT_PORCH = 10'd10;
	localparam V_TOTAL       = 10'd525;
	
	assign hsync = ~((hcount >= H_FRONT_PORCH) & (hcount < H_FRONT_PORCH + H_SYNC));
	assign vsync = ~((vcount >= V_DISPLAY_INT + V_FRONT_PORCH) & (vcount < V_DISPLAY_INT + V_FRONT_PORCH + V_SYNC));

	always @(posedge clk) begin
	
	if (rst) begin
		vcount  <= 10'd0;
		hcount  <= 10'd0;
		vga_clk <= 1'b0;
	end
	
	else begin
		if (vga_clk) begin
			hcount <= hcount + 1'b1;
			

			if (hcount == H_TOTAL) begin
				hcount <= 10'd0;
				vcount <= vcount + 1'b1;
				
				if (vcount == V_TOTAL)
					vcount <= 10'd0;
			end
		end
		vga_clk <= ~vga_clk;
	end
end

always @(hcount,vcount) begin
	

	if ((hcount >= H_FRONT_PORCH + H_SYNC + H_BACK_PORCH) &&
		 (hcount < H_TOTAL - H_FRONT_PORCH) &&
		 (vcount < V_DISPLAY_INT))
		 vga_blank_n = 1'b1;
	 
	 else 
		vga_blank_n = 1'b0;
		
end
	

endmodule
module vga_control (clk, rst, hsync, vsync, vga_blank_n, vga_clk, hcount, vcount);

	input clk, rst;
	output hsync, vsync;
	output reg vga_blank_n, vga_clk;
	output reg [9:0] hcount, vcount;
	



	localparam H_SYNC        = 10'd96;
	localparam H_FRONT_PORCH = 10'd16;
	localparam H_DISPLAY_INT = 10'd640;
	localparam H_BACK_PORCH  = 10'd48;
	localparam H_TOTAL       = 10'd800;
	
	localparam V_SYNC        = 10'd2;
	localparam V_BACK_PORCH  = 10'd33;
	localparam V_DISPLAY_INT = 10'd480;
	localparam V_FRONT_PORCH = 10'd10;
	localparam V_TOTAL       = 10'd525;
	
	assign hsync = ~((hcount >= H_FRONT_PORCH) & (hcount < H_FRONT_PORCH + H_SYNC));
	assign vsync = ~((vcount >= V_DISPLAY_INT + V_FRONT_PORCH) & (vcount < V_DISPLAY_INT + V_FRONT_PORCH + V_SYNC));

	always @(posedge clk) begin
	
	if (rst) begin
		vcount  <= 10'd0;
		hcount  <= 10'd0;
		vga_clk <= 1'b0;
	end
	
	else begin
		if (vga_clk) begin
			hcount <= hcount + 1'b1;
			

			if (hcount == H_TOTAL) begin
				hcount <= 10'd0;
				vcount <= vcount + 1'b1;
				
				if (vcount == V_TOTAL)
					vcount <= 10'd0;
			end
		end
		vga_clk <= ~vga_clk;
	end
end

always @(hcount,vcount) begin
	

	if ((hcount >= H_FRONT_PORCH + H_SYNC + H_BACK_PORCH) &&
		 (hcount < H_TOTAL - H_FRONT_PORCH) &&
		 (vcount < V_DISPLAY_INT))
		 vga_blank_n = 1'b1;
	 
	 else 
		vga_blank_n = 1'b0;
		
end
	

endmodule