data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/dff32.v
data/verilator_xmls/00d40a45-4143-4379-9882-d1868a931eef.xml
module dff32(
    input[31:0] d,
    input clk,
    input clrn,
    input e,
    output reg [31:0] q
    );
    always @ (negedge clrn or posedge clk)
        if (clrn == 0) begin
           q <= 0;
        end else begin
            if (e==1) q <= d;
       end
endmodule
module dff32(
    input[31:0] d,
    input clk,
    input clrn,
    input e,
    output reg [31:0] q
    );

    always @ (negedge clrn or posedge clk)
        if (clrn == 0) begin
           q <= 0;
        end else begin
            if (e==1) q <= d;
       end
endmodule