data/full_repos/permissive/528252229/pc_reg.v
1: b'%Error: data/full_repos/permissive/528252229/pc_reg.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/pc_reg.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] branch_target_address_i,  \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] branch_target_address_i,  \n                        ^\n%Error: data/full_repos/permissive/528252229/pc_reg.v:10: Define or directive not defined: \'`StopBus\'\n input wire[`StopBus]  stall,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:12: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] pc,                         \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:13: Define or directive not defined: \'`InstAddrBus\'\n output wire[`InstAddrBus]   pc_three,                  \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:19: syntax error, unexpected assign\n    assign pc_ds = pc + 32\'h4;\n    ^~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:22: Define or directive not defined: \'`RstDisable\'\n        if (rst == `RstDisable) begin\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:23: Define or directive not defined: \'`InitialPc\'\n            pc <= `InitialPc;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:24: Define or directive not defined: \'`ReadEnable\'\n            ce <= `ReadEnable;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:26: Define or directive not defined: \'`NoStop\'\n        else if(stall[0] == `NoStop) begin\n                            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:27: Define or directive not defined: \'`ReadEnable\'\n            ce <= `ReadEnable;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/pc_reg.v:28: Define or directive not defined: \'`Branch\'\n            if(branch_flag_i == `Branch) begin\n                                ^~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module pc_reg(

	input wire				    clk,
	input wire				    rst,
	
	input wire 					branch_flag_i,
	input wire[`InstAddrBus]	branch_target_address_i,
	input wire[`StopBus]		stall,

	output reg[`InstAddrBus]	pc,
	output wire[`InstAddrBus]   pc_three,
	output reg                  ce
	
    );
	
	wire [31:0] pc_ds;
    assign pc_ds = pc + 32'h4;
	
	always @(posedge clk) begin
        if (rst == `RstDisable) begin
            pc <= `InitialPc;
            ce <= `ReadEnable;
        end
        else if(stall[0] == `NoStop) begin
            ce <= `ReadEnable;
            if(branch_flag_i == `Branch) begin
                pc <= branch_target_address_i;
            end
            else begin
                pc <= pc_ds;
            end
        end
    end
	
endmodule
module pc_reg(

	input wire				    clk,
	input wire				    rst,
	
	input wire 					branch_flag_i,
	input wire[`InstAddrBus]	branch_target_address_i,
	input wire[`StopBus]		stall,

	output reg[`InstAddrBus]	pc,
	output wire[`InstAddrBus]   pc_three,
	output reg                  ce
	
    );

	
	wire [31:0] pc_ds;
    assign pc_ds = pc + 32'h4;
	
	always @(posedge clk) begin
        if (rst == `RstDisable) begin
            pc <= `InitialPc;
            ce <= `ReadEnable;
        end
        else if(stall[0] == `NoStop) begin
            ce <= `ReadEnable;
            if(branch_flag_i == `Branch) begin
                pc <= branch_target_address_i;
            end
            else begin
                pc <= pc_ds;
            end
        end
    end
	
endmodule