data/full_repos/permissive/446312960/Verilog_Simulation/08_adder4bit/adder4bit_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/08_adder4bit/adder4bit_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/08_adder4bit/adder4bit_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder4bit_test(t1, t2, t3, p1, p2);

output [3:0]  t1, t2;
output            t3;
input  [3:0]      p1;
input             p2;


reg      [3:0] t1, t2;
reg                t3;

initial begin
   t1 <= 4'b0011; t2 <= 4'b0001; t3 <= 1'b0;

   #100;
   t1 <= 4'b1100; t2 <= 4'b0011; t3 <= 1'b1;

   #100;
   $finish;
end

endmodule
module adder4bit_test(t1, t2, t3, p1, p2);


output [3:0]  t1, t2;
output            t3;
input  [3:0]      p1;
input             p2;


reg      [3:0] t1, t2;
reg                t3;

initial begin
   t1 <= 4'b0011; t2 <= 4'b0001; t3 <= 1'b0;

   #100;
   t1 <= 4'b1100; t2 <= 4'b0011; t3 <= 1'b1;

   #100;
   $finish;
end

endmodule