data/full_repos/permissive/482848318/bcd7segDEC_testbench.v
1: b'%Error: data/full_repos/permissive/482848318/bcd7segDEC_testbench.v:18: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " SW=%b, HEX5=%b, LEDR=%b ",SW,HEX5,LEDR);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/482848318/bcd7segDEC_testbench.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("bcd7segDEC.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482848318/bcd7segDEC_testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, bcd7segDEC_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482848318/bcd7segDEC_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #0  SW=0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482848318/bcd7segDEC_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #50 SW <= SW + 1;\n      ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd7segDEC_testbench();
  
  reg [3:0] SW;

  wire [7:0] HEX5;
  wire [9:0] LEDR;
  
  bcd7segDEC DUT ( .SW(SW), .HEX5(HEX5), .LEDR(LEDR));
  
  initial
  begin
    $monitor($time, " SW=%b, HEX5=%b, LEDR=%b ",SW,HEX5,LEDR);
  end
  
  initial
  begin
    $dumpfile("bcd7segDEC.vcd");
    $dumpvars(1, bcd7segDEC_testbench);
    
    #0  SW=0;
    repeat (15)
    begin
      #50 SW <= SW + 1;
    end
    
  end
  
endmodule
module bcd7segDEC_testbench();

  
  reg [3:0] SW;

  wire [7:0] HEX5;
  wire [9:0] LEDR;
  
  bcd7segDEC DUT ( .SW(SW), .HEX5(HEX5), .LEDR(LEDR));
  
  initial
  begin
    $monitor($time, " SW=%b, HEX5=%b, LEDR=%b ",SW,HEX5,LEDR);
  end
  
  initial
  begin
    $dumpfile("bcd7segDEC.vcd");
    $dumpvars(1, bcd7segDEC_testbench);
    
    #0  SW=0;
    repeat (15)
    begin
      #50 SW <= SW + 1;
    end
    
  end
  
endmodule