data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_using_assign.v
data/verilator_xmls/d6148dba-a971-4629-9d92-35283a5c728c.xml
module  mux_using_assign(
din_0      ,
din_1      ,
sel        ,
mux_out
);

input din_0, din_1, sel ;

output mux_out;

wire  mux_out;

assign mux_out = (sel) ? din_1 : din_0;

endmodule
module  mux_using_assign(
din_0      ,
din_1      ,
sel        ,
mux_out
);


input din_0, din_1, sel ;

output mux_out;

wire  mux_out;

assign mux_out = (sel) ? din_1 : din_0;

endmodule