data/full_repos/permissive/473722449/counter_4bit_upxdown.v
data/verilator_xmls/e9d72f42-edbb-4bb6-9cd3-b6556b8afc95.xml
module counter_4bit_upxdown( clk,reset,dir,count);
   input clk,reset,dir;
   output reg [3:0] count=0;
    
    always@(posedge (clk) or posedge(reset))
    begin
        if (reset==1)
            count<=0;
        else
            if (dir==0)
                if (count==15)
                    count<=0;
                else
                    count<=count+1;
            else
                if (count==0)
                    count<=15;
                else
                    count<=count-1;                                 
    end
endmodule
module counter_4bit_upxdown( clk,reset,dir,count);

   input clk,reset,dir;
   output reg [3:0] count=0;
    
    always@(posedge (clk) or posedge(reset))
    begin
        if (reset==1)
            count<=0;
        else
            if (dir==0)
                if (count==15)
                    count<=0;
                else
                    count<=count+1;
            else
                if (count==0)
                    count<=15;
                else
                    count<=count-1;                                 
    end
endmodule