data/full_repos/permissive/510160664/Adders/src/ripple_carry.v
data/verilator_xmls/4594d74b-b972-4b79-8b58-9f02628346e7.xml
module ripple_carry
#(
					parameter WIDTH = 32
)
(
					input 	[WIDTH-1:0] Number1_i,
					input 	[WIDTH-1:0] Number2_i,
					input					 	Carry_i,

					output 	[WIDTH-1:0] Result_o,
					output 			 		Carry_o
);


wire [WIDTH-2:0] c_o;


full_adder fa0
(
				.A_i(Number1_i[0]),
				.B_i(Number2_i[0]),
				.C_i(Carry_i),

				.S_o(Result_o[0]),
				.C_o(c_o[0])
);


full_adder fa_last
(
				.A_i(Number1_i[WIDTH-1]),
				.B_i(Number2_i[WIDTH-1]),
				.C_i(c_o[WIDTH-2]),

				.S_o(Result_o[WIDTH-1]),
				.C_o(Carry_o)
);


generate
	genvar j;

	for (j = 1; j < WIDTH - 1; j = j + 1) begin :fa
		full_adder fa
		(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
		);
	end
endgenerate

endmodule
module ripple_carry
#(
					parameter WIDTH = 32
)
(
					input 	[WIDTH-1:0] Number1_i,
					input 	[WIDTH-1:0] Number2_i,
					input					 	Carry_i,

					output 	[WIDTH-1:0] Result_o,
					output 			 		Carry_o
);



wire [WIDTH-2:0] c_o;


full_adder fa0
(
				.A_i(Number1_i[0]),
				.B_i(Number2_i[0]),
				.C_i(Carry_i),

				.S_o(Result_o[0]),
				.C_o(c_o[0])
);


full_adder fa_last
(
				.A_i(Number1_i[WIDTH-1]),
				.B_i(Number2_i[WIDTH-1]),
				.C_i(c_o[WIDTH-2]),

				.S_o(Result_o[WIDTH-1]),
				.C_o(Carry_o)
);


generate
	genvar j;

	for (j = 1; j < WIDTH - 1; j = j + 1) begin :fa
		full_adder fa
		(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
		);
	end
endgenerate

endmodule