data/full_repos/permissive/522668124/verilog/rtl/pc.sv
data/verilator_xmls/f0937b4b-c8ac-443e-b5d2-b204fecc6760.xml
module pc

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input  logic         clk,
  input  logic         rst_n,
  input  logic  [31:0] rs1_data,
  input  logic  [31:0] immediate,
  input  logic         jump_jal,
  input  logic         jump_jalr,
  input  logic         branch,
  input  logic         alu_branch,
  
  output logic  [31:0] pc_out
);
  
  logic [31:0] pc = 0;
  logic [31:0] pc_plus_4;
  logic jalr_value = 0;
  
  always_ff @(posedge clk) begin
    if (!rst_n) pc <= 32'h00000000;
    else if (jump_jal) pc <= pc_out + immediate;
    else if (jump_jalr) pc <= pc_out + $signed(((rs1_data + immediate) >> 1) << 1); 
    else if (branch && alu_branch) pc <= pc_out + immediate;
    else pc <= pc_plus_4;
  end 
  
  assign pc_plus_4 = pc+4;
  assign pc_out = pc;

endmodule
module pc

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input  logic         clk,
  input  logic         rst_n,
  input  logic  [31:0] rs1_data,
  input  logic  [31:0] immediate,
  input  logic         jump_jal,
  input  logic         jump_jalr,
  input  logic         branch,
  input  logic         alu_branch,
  
  output logic  [31:0] pc_out
);

  
  logic [31:0] pc = 0;
  logic [31:0] pc_plus_4;
  logic jalr_value = 0;
  
  always_ff @(posedge clk) begin
    if (!rst_n) pc <= 32'h00000000;
    else if (jump_jal) pc <= pc_out + immediate;
    else if (jump_jalr) pc <= pc_out + $signed(((rs1_data + immediate) >> 1) << 1); 
    else if (branch && alu_branch) pc <= pc_out + immediate;
    else pc <= pc_plus_4;
  end 
  
  assign pc_plus_4 = pc+4;
  assign pc_out = pc;

endmodule