data/full_repos/permissive/510160664/Adders/src/cs_adder.v
data/verilator_xmls/366819ef-6dc7-4989-842a-1cec9e804764.xml
module csa_submodule
(
			input 	A_i,
			input 	B_i,
			input		C_i,

			output 	S_o,
			output 	C_o
);


wire P_w;

assign P_w = A_i ^ B_i;


assign S_o = P_w ^ C_i;
assign C_o = (A_i & B_i) | (P_w & C_i);

endmodule
module csa_submodule
(
			input 	A_i,
			input 	B_i,
			input		C_i,

			output 	S_o,
			output 	C_o
);



wire P_w;

assign P_w = A_i ^ B_i;


assign S_o = P_w ^ C_i;
assign C_o = (A_i & B_i) | (P_w & C_i);

endmodule