data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_multiply.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_multiply.v:6: Operator SHIFTL expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                                                                 : ... In instance muliply\n      assign product  = a << 1;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module muliply (a,product);
  	  	input [3:0] a;
  	  	output [4:0] product;
  	  	wire [4:0] product;
  	  	 
  	  	assign product  = a << 1;
  	  	 
endmodule
module muliply (a,product);

  	  	input [3:0] a;
  	  	output [4:0] product;
  	  	wire [4:0] product;
  	  	 
  	  	assign product  = a << 1;
  	  	 
endmodule