data/full_repos/permissive/52633518/control_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52633518/control_fsm.v:81: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'NAND\' generates 4 bits.\n                                                                    : ... In instance control_fsm\n   case (state)\n   ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52633518/control_fsm.v:157: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'NAND\' generates 4 bits.\n                                                                     : ... In instance control_fsm\n  case (state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/52633518/control_fsm.v:401: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'NAND\' generates 4 bits.\n                                                                     : ... In instance control_fsm\n case (state)\n ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module control_fsm
(
  input	clk, reset,  run_n,
  input [15:0] sram_d, regA, regB, alu_status, alu_out,
  
  output reg sram_we_n, reg_we,
  output reg [2:0] alu_op,
  output reg [3:0] reg_addr_a, reg_addr_b, reg_addr_c,
  output [15:0] alu_op_a, reg_data_c,
  output reg [15:0] sram_addr, sram_q
  
 );
  

  `define alu_op_size 3





parameter ADD = 5'd0;
parameter ADDI = 5'd1; 
parameter SUB = 5'd2; 
parameter SUBI = 5'd3; 
parameter MULT = 5'd4; 
parameter SW = 5'd5; 
parameter LW = 5'd6; 
parameter LT = 5'd7; 
parameter NAND = 4'd8; 
parameter DIV = 5'd9; 
parameter MOD = 5'd10; 
parameter LTE = 5'd11; 
parameter BLT = 5'd12; 
parameter BLE = 5'd13; 
parameter BEQ = 5'd14; 
parameter JUMP = 5'd15; 
parameter FETCH = 5'd16; 
parameter BLT2 = 5'd17;
parameter BLE2 = 5'd18; 
parameter BEQ2 = 5'd19; 
parameter SW2 = 5'd20;
parameter DECODE = 5'd21; 
parameter LW2 = 5'd22; 
parameter LW3 = 5'd23; 
parameter SW3 = 5'd24; 
parameter SW4 = 5'd25; 
parameter JUMP2 = 5'd26;
parameter BLE3 = 5'd27;	
parameter BLT3 = 5'd28;
parameter BEQ3 = 5'd29; 



  reg im_en;
  reg	[4:0] state;
  reg [15:0] instruction,pc, regC;

  wire ram_to_reg;
  wire [3:0] op_code, op1, op2, op3, im;
  wire [11:0] jump;

  

  assign op_code = instruction[15:12];
  assign op1 = instruction[3:0];
  assign op2 = instruction[7:4];
  assign op3 = instruction[11:8];
  assign im = instruction[3:0];
  assign jump = instruction[11:0];

  assign alu_op_a = im_en ? {12'd0, im} : regA;
  assign ram_to_reg = (state == LW) | (state == LW2) | (state == LW3);
  assign reg_data_c = ram_to_reg ? sram_d : alu_out;
  


	always @ (posedge clk or negedge reset) begin
		if (reset == 1'b0) begin
			state <= FETCH;
		end else if(!run_n)
			case (state)
        FETCH:
		      state <= DECODE;
  		  DECODE:
          state <= {1'b0, op_code};
  		  ADD:
			    state <= FETCH;	
  		  ADDI:
			    state <= FETCH;
  		  SUB:
			    state <= FETCH;	
  		  SUBI:
          state <= FETCH;					
        MULT:
          state <= FETCH;
        SW:
          state <= SW2;
        SW2:
		      state <= SW3;
  		  SW3:
		      state <= SW4;
		    SW4:
		      state <= FETCH;
        LW:
		      state <= LW2;
		    LW2:
		      state <= LW3;
		    LW3:
          state <= FETCH;
        LT:
          state <= FETCH;
        NAND:
          state <= FETCH;
        DIV:
          state <= FETCH;
        MOD:
          state <= FETCH;
        LTE:
          state <= FETCH;
        BLT:
          state <= BLT2;
        BLE:
          state <= BLE2;
        BEQ:
          state <= BEQ2;
        JUMP:
          state <= JUMP2;
		    JUMP2:
		      state <= FETCH;
        BLT2:
          state <= BLT3;
        BLT3:
          state <= FETCH;
        BLE2:
		      state <= BLE3;
		    BLE3:
          state <= FETCH;  
        BEQ2:
          state <= BEQ3;
        BEQ3:
          state <= FETCH;
        default:
          state <= FETCH;
			endcase
    end 
    


	always @ (posedge clk or negedge reset) begin
		if(reset == 1'b0) begin
			pc <= 16'h0000;
			instruction <= 16'hf000;
			sram_addr <= 16'h0000;
			sram_we_n <= 1'b1;
			sram_q <= 16'h0000;
	  end else begin
		case (state)
      FETCH: begin
        instruction <= sram_d;
        sram_addr <= pc;
        sram_we_n <= 1'b1;
		    pc <= pc;
		    sram_q <= 16'hffff;
		  end
		DECODE: begin
		  pc <= pc;
		  instruction <= instruction;
		  sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		ADD: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		ADDI: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
       sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		SUB: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		SUBI: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    MULT: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		  end
    SW: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		end
		SW2: begin
      sram_we_n <= 1'b0;
      sram_q <= regA;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		end
		SW3: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= pc;
      pc <= pc;
		  instruction <= instruction;
		  end
		SW4: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= pc;
      pc <= pc + 16'd1;
		  instruction <= instruction;
		end
    LW:begin
      sram_we_n <= 1'b1;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
		LW2:begin
      sram_we_n <= 1'b1;
		  sram_addr <= pc;
      pc <= pc;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
		LW3:begin
      sram_we_n <= 1'b1;
		  sram_addr <= pc;
      pc <= pc + 16'd1;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
    LT: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    NAND: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		  end
    DIV: begin 
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    MOD: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    LTE: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BLT: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BLE: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BEQ: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    JUMP: begin


      pc <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;

		  sram_addr <= pc + {jump[11],jump[11],jump[11],jump[11],jump}  - 16'd1;
		end
    JUMP2: begin
      pc <= pc + 16'd1; 
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;

		  sram_addr <= pc;
		end
    BLT2: begin
      if(alu_status == 16'd1) begin
        pc <= pc + {12'd0, im};
        sram_addr <= pc + {12'd0, im};
      end else begin 
        pc <= pc;
        sram_addr <= sram_addr;
		  end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		end
    BLT3: begin

      pc <= pc + 16'd1;
      instruction <= instruction;
      sram_we_n <= 1'b1;
      sram_q <= 16'hffff;
      sram_addr <= sram_addr;
    end
    BLE2: begin
      if(alu_status == 16'd1) begin
        pc <= pc + {12'd0, im};
		    sram_addr <= pc + {12'd0, im};
      end else begin
        pc <= pc;
        sram_addr <= sram_addr;
		  end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		end
    BLE3: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BEQ2: begin
      if(alu_status == 16'd0) begin
        pc <= pc + {12'd0, im};
        sram_addr <= pc + {12'd0, im};
      end else begin
        pc <= pc;
        sram_addr <= sram_addr;
   		end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
	  	sram_q <= 16'hffff;
	  end
    BEQ3: begin

      pc <= pc + 16'd1;
      instruction <= instruction;
      sram_we_n <= 1'b1;
      sram_q <= 16'hffff;
      sram_addr <= sram_addr;
    end
    default: begin
      pc <= 16'd0;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		endcase
  end
end

always@(*) begin
	case (state)
    FETCH: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
    end
		DECODE: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
		end
		ADD: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
		end
		ADDI: begin
      reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
		SUB: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h1;
      im_en = 1'b0;
		end
		SUBI: begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h1;
      im_en = 1'b1;
		end
    MULT: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h2;
      im_en = 1'b0;
		end
    SW: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
		SW2: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		SW3: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		SW4: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
    LW:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		  reg_we = 1'b0;
		end
		LW2:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		LW3:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
    LT: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h6;
      im_en = 1'b0;
		end
    NAND: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h3;
      im_en = 1'b0;
	  end
    DIV: begin 
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h4;
      im_en = 1'b0;
	  end
    MOD: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h5;
      im_en = 1'b0;
		end
    LTE: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h7;
      im_en = 1'b0;
		end
    BLT: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h6;
      im_en = 1'b0;
		end
    BLE: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h7;
      im_en = 1'b0;
    end
    BEQ: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h1;
      im_en = 1'b0;
		end
    JUMP: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    JUMP2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		  end
    BLT2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLE2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BEQ2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLT3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLE3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BEQ3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end

    default: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
		endcase
end


endmodule
module control_fsm
(
  input	clk, reset,  run_n,
  input [15:0] sram_d, regA, regB, alu_status, alu_out,
  
  output reg sram_we_n, reg_we,
  output reg [2:0] alu_op,
  output reg [3:0] reg_addr_a, reg_addr_b, reg_addr_c,
  output [15:0] alu_op_a, reg_data_c,
  output reg [15:0] sram_addr, sram_q
  
 );

  

  `define alu_op_size 3





parameter ADD = 5'd0;
parameter ADDI = 5'd1; 
parameter SUB = 5'd2; 
parameter SUBI = 5'd3; 
parameter MULT = 5'd4; 
parameter SW = 5'd5; 
parameter LW = 5'd6; 
parameter LT = 5'd7; 
parameter NAND = 4'd8; 
parameter DIV = 5'd9; 
parameter MOD = 5'd10; 
parameter LTE = 5'd11; 
parameter BLT = 5'd12; 
parameter BLE = 5'd13; 
parameter BEQ = 5'd14; 
parameter JUMP = 5'd15; 
parameter FETCH = 5'd16; 
parameter BLT2 = 5'd17;
parameter BLE2 = 5'd18; 
parameter BEQ2 = 5'd19; 
parameter SW2 = 5'd20;
parameter DECODE = 5'd21; 
parameter LW2 = 5'd22; 
parameter LW3 = 5'd23; 
parameter SW3 = 5'd24; 
parameter SW4 = 5'd25; 
parameter JUMP2 = 5'd26;
parameter BLE3 = 5'd27;	
parameter BLT3 = 5'd28;
parameter BEQ3 = 5'd29; 



  reg im_en;
  reg	[4:0] state;
  reg [15:0] instruction,pc, regC;

  wire ram_to_reg;
  wire [3:0] op_code, op1, op2, op3, im;
  wire [11:0] jump;

  

  assign op_code = instruction[15:12];
  assign op1 = instruction[3:0];
  assign op2 = instruction[7:4];
  assign op3 = instruction[11:8];
  assign im = instruction[3:0];
  assign jump = instruction[11:0];

  assign alu_op_a = im_en ? {12'd0, im} : regA;
  assign ram_to_reg = (state == LW) | (state == LW2) | (state == LW3);
  assign reg_data_c = ram_to_reg ? sram_d : alu_out;
  


	always @ (posedge clk or negedge reset) begin
		if (reset == 1'b0) begin
			state <= FETCH;
		end else if(!run_n)
			case (state)
        FETCH:
		      state <= DECODE;
  		  DECODE:
          state <= {1'b0, op_code};
  		  ADD:
			    state <= FETCH;	
  		  ADDI:
			    state <= FETCH;
  		  SUB:
			    state <= FETCH;	
  		  SUBI:
          state <= FETCH;					
        MULT:
          state <= FETCH;
        SW:
          state <= SW2;
        SW2:
		      state <= SW3;
  		  SW3:
		      state <= SW4;
		    SW4:
		      state <= FETCH;
        LW:
		      state <= LW2;
		    LW2:
		      state <= LW3;
		    LW3:
          state <= FETCH;
        LT:
          state <= FETCH;
        NAND:
          state <= FETCH;
        DIV:
          state <= FETCH;
        MOD:
          state <= FETCH;
        LTE:
          state <= FETCH;
        BLT:
          state <= BLT2;
        BLE:
          state <= BLE2;
        BEQ:
          state <= BEQ2;
        JUMP:
          state <= JUMP2;
		    JUMP2:
		      state <= FETCH;
        BLT2:
          state <= BLT3;
        BLT3:
          state <= FETCH;
        BLE2:
		      state <= BLE3;
		    BLE3:
          state <= FETCH;  
        BEQ2:
          state <= BEQ3;
        BEQ3:
          state <= FETCH;
        default:
          state <= FETCH;
			endcase
    end 
    


	always @ (posedge clk or negedge reset) begin
		if(reset == 1'b0) begin
			pc <= 16'h0000;
			instruction <= 16'hf000;
			sram_addr <= 16'h0000;
			sram_we_n <= 1'b1;
			sram_q <= 16'h0000;
	  end else begin
		case (state)
      FETCH: begin
        instruction <= sram_d;
        sram_addr <= pc;
        sram_we_n <= 1'b1;
		    pc <= pc;
		    sram_q <= 16'hffff;
		  end
		DECODE: begin
		  pc <= pc;
		  instruction <= instruction;
		  sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		ADD: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		ADDI: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
       sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		SUB: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		SUBI: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    MULT: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		  end
    SW: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		end
		SW2: begin
      sram_we_n <= 1'b0;
      sram_q <= regA;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		end
		SW3: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= pc;
      pc <= pc;
		  instruction <= instruction;
		  end
		SW4: begin
      sram_we_n <= 1'b1;
      sram_q <= regA;
		  sram_addr <= pc;
      pc <= pc + 16'd1;
		  instruction <= instruction;
		end
    LW:begin
      sram_we_n <= 1'b1;
		  sram_addr <= alu_out;
      pc <= pc;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
		LW2:begin
      sram_we_n <= 1'b1;
		  sram_addr <= pc;
      pc <= pc;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
		LW3:begin
      sram_we_n <= 1'b1;
		  sram_addr <= pc;
      pc <= pc + 16'd1;
		  instruction <= instruction;
		  sram_q <= 16'hffff;
		end
    LT: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    NAND: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		  end
    DIV: begin 
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    MOD: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    LTE: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BLT: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BLE: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BEQ: begin
		  pc <= pc;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    JUMP: begin


      pc <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;

		  sram_addr <= pc + {jump[11],jump[11],jump[11],jump[11],jump}  - 16'd1;
		end
    JUMP2: begin
      pc <= pc + 16'd1; 
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;

		  sram_addr <= pc;
		end
    BLT2: begin
      if(alu_status == 16'd1) begin
        pc <= pc + {12'd0, im};
        sram_addr <= pc + {12'd0, im};
      end else begin 
        pc <= pc;
        sram_addr <= sram_addr;
		  end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		end
    BLT3: begin

      pc <= pc + 16'd1;
      instruction <= instruction;
      sram_we_n <= 1'b1;
      sram_q <= 16'hffff;
      sram_addr <= sram_addr;
    end
    BLE2: begin
      if(alu_status == 16'd1) begin
        pc <= pc + {12'd0, im};
		    sram_addr <= pc + {12'd0, im};
      end else begin
        pc <= pc;
        sram_addr <= sram_addr;
		  end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		end
    BLE3: begin
      pc <= pc + 16'd1;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
    BEQ2: begin
      if(alu_status == 16'd0) begin
        pc <= pc + {12'd0, im};
        sram_addr <= pc + {12'd0, im};
      end else begin
        pc <= pc;
        sram_addr <= sram_addr;
   		end
		  instruction <= instruction;
      sram_we_n <= 1'b1;
	  	sram_q <= 16'hffff;
	  end
    BEQ3: begin

      pc <= pc + 16'd1;
      instruction <= instruction;
      sram_we_n <= 1'b1;
      sram_q <= 16'hffff;
      sram_addr <= sram_addr;
    end
    default: begin
      pc <= 16'd0;
		  instruction <= instruction;
      sram_we_n <= 1'b1;
		  sram_q <= 16'hffff;
		  sram_addr <= sram_addr;
		end
		endcase
  end
end

always@(*) begin
	case (state)
    FETCH: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
    end
		DECODE: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
		end
		ADD: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b0;
		end
		ADDI: begin
      reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
		SUB: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h1;
      im_en = 1'b0;
		end
		SUBI: begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h1;
      im_en = 1'b1;
		end
    MULT: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
		  alu_op = `alu_op_size'h2;
      im_en = 1'b0;
		end
    SW: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
		SW2: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		SW3: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		SW4: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
    LW:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		  reg_we = 1'b0;
		end
		LW2:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
      reg_we = 1'b0;
		end
		LW3:begin
		  reg_addr_a = 4'hx;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h0;
      im_en = 1'b1;
		end
    LT: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h6;
      im_en = 1'b0;
		end
    NAND: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h3;
      im_en = 1'b0;
	  end
    DIV: begin 
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h4;
      im_en = 1'b0;
	  end
    MOD: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h5;
      im_en = 1'b0;
		end
    LTE: begin
		  reg_addr_a = op1;
      reg_addr_b = op2;
      reg_addr_c = op3;
      reg_we = 1'b1;
      alu_op = `alu_op_size'h7;
      im_en = 1'b0;
		end
    BLT: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h6;
      im_en = 1'b0;
		end
    BLE: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h7;
      im_en = 1'b0;
    end
    BEQ: begin
		  reg_addr_a = op3;
      reg_addr_b = op2;
      reg_addr_c = 4'hx;
      reg_we = 1'b0;
      alu_op = `alu_op_size'h1;
      im_en = 1'b0;
		end
    JUMP: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    JUMP2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		  end
    BLT2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLE2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BEQ2: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
      reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLT3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BLE3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
    BEQ3: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end

    default: begin
		  reg_addr_a = 4'hf;
      reg_addr_b = 4'hf;
      reg_addr_c = 4'hf;
		  reg_we = 1'b0;
		  alu_op = `alu_op_size'h0;
		  im_en = 1'b0;
		end
		endcase
end


endmodule