data/full_repos/permissive/509809169/Verilog Language/Modules_Hierarchy/Adder 2.v
1: b'%Error: Cannot find file containing module: Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Modules_Hierarchy/Adder\n%Error: Cannot find file containing module: 2.v\n%Error: Exiting due to 4 error(s)\n'
module add1 ( input a, input b, input cin,   output sum, output cout );
	assign sum= a^b^cin;
    assign cout=a&b | b&cin | cin&a;
endmodule
module add1 ( input a, input b, input cin,   output sum, output cout );

	assign sum= a^b^cin;
    assign cout=a&b | b&cin | cin&a;
endmodule