data/full_repos/permissive/458737381/src/verilog-parser/tests/t_gate_switch.v
data/verilator_xmls/18213b3e-dada-4b3e-be27-e91a35d4d165.xml
module t_gate_switch (L,R,nC,C);
 inout L;
 inout R;
 input nC;
 input C;


 pmos p1 (L,R,nC);
 nmos p2 (L,R,C);

endmodule
module t_gate_switch (L,R,nC,C);

 inout L;
 inout R;
 input nC;
 input C;


 pmos p1 (L,R,nC);
 nmos p2 (L,R,C);

endmodule