data/full_repos/permissive/441359809/src/yosys/frontends/verific/example.sv
data/verilator_xmls/3dedb1a8-cdaf-48d3-9c61-bc01772d7d46.xml
module top (
  input clk, rst,
  output reg [3:0] cnt
);
  initial cnt = 0;

  always @(posedge clk) begin
    if (rst)
      cnt <= 0;
    else
      cnt <= cnt + 4'd 1;
  end

  always @(posedge clk) begin
    assume (cnt != 10);
    assert (cnt != 15);
  end
endmodule
module top (
  input clk, rst,
  output reg [3:0] cnt
);

  initial cnt = 0;

  always @(posedge clk) begin
    if (rst)
      cnt <= 0;
    else
      cnt <= cnt + 4'd 1;
  end

  always @(posedge clk) begin
    assume (cnt != 10);
    assert (cnt != 15);
  end
endmodule