data/full_repos/permissive/452305748/L3/comp_conv/comp_conv.v
data/verilator_xmls/aad22a26-fe6d-429c-a602-daaed8561f7a.xml
module comp_conv(a,
                 a_comp);
    input[7:0] a;
    output[7:0] a_comp;



    wire[7:0] y;

    assign y[6:0] = ~a[6:0]+1;

    assign y = {a[7],y[6:0]};
    
    assign a_comp=a[7]?y:a;
endmodule
module comp_conv(a,
                 a_comp);

    input[7:0] a;
    output[7:0] a_comp;



    wire[7:0] y;

    assign y[6:0] = ~a[6:0]+1;

    assign y = {a[7],y[6:0]};
    
    assign a_comp=a[7]?y:a;
endmodule