data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc/register.v
data/verilator_xmls/410076c9-659c-4397-afa6-3a9940d7a3ba.xml
module register(input clk, input [D_WIDTH-1:0] in, input load, output [D_WIDTH-1:0] out);
	parameter D_WIDTH = 16;
	
	reg [D_WIDTH-1:0] data;
	
	assign out=data;
	
	always @(posedge clk) 
	begin
		if(load) begin
			data <= in;
		end		
	end
	
endmodule
module register(input clk, input [D_WIDTH-1:0] in, input load, output [D_WIDTH-1:0] out);

	parameter D_WIDTH = 16;
	
	reg [D_WIDTH-1:0] data;
	
	assign out=data;
	
	always @(posedge clk) 
	begin
		if(load) begin
			data <= in;
		end		
	end
	
endmodule