data/full_repos/permissive/409580086/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/409580086/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n  always #(clock_period/2) clock=~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/409580086/test.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #(bit_period);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/409580086/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #(bit_period);\n        ^\n%Error: data/full_repos/permissive/409580086/test.v:29: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/409580086/test.v:30: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/409580086/test.v:32: Unsupported or unknown PLI call: $monitor\n    $monitor("Received byte --- %b",output_stream);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/409580086/test.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #(bit_period);\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg input_stream,clock;
  wire [7:0]output_stream;


  parameter clock_period=40;
  parameter bit_period=104200;
  integer i;
  uart i1(input_stream,clock,output_stream);
  
  always #(clock_period/2) clock=~clock;

  task check;
    input [7:0]in;
    begin
      input_stream=1'b0;
      #(bit_period);
    	for(i=0;i<8;i=i+1) begin
      		input_stream=in[i];
      		#(bit_period);
    	end
      input_stream=1'b1;
    end
  endtask
  
  initial begin
    clock=0;
    $dumpfile("tb.vcd");
    $dumpvars;
    $display("Sent byte --- 10010011");
    $monitor("Received byte --- %b",output_stream);
    check(8'b10010011);
    #(bit_period);
    if(output_stream==8'b10010011) begin
      $display("Correct sequence received.");
      $display("Receiving frequency --- %f MHz",25.0);
      $display("Sending frequency --- %f Mhz",2605000.0/bit_period);
    end
    else begin
      $display("Incorrect sequence received.");
      $display("Receiving frequency --- %f MHz",25.0);
      $display("Sending frequency --- %f Mhz",260500.0/bit_period);
    end
    $finish;
  end
endmodule
module tb();

  reg input_stream,clock;
  wire [7:0]output_stream;


  parameter clock_period=40;
  parameter bit_period=104200;
  integer i;
  uart i1(input_stream,clock,output_stream);
  
  always #(clock_period/2) clock=~clock;

  task check;
    input [7:0]in;
    begin
      input_stream=1'b0;
      #(bit_period);
    	for(i=0;i<8;i=i+1) begin
      		input_stream=in[i];
      		#(bit_period);
    	end
      input_stream=1'b1;
    end
  endtask
  
  initial begin
    clock=0;
    $dumpfile("tb.vcd");
    $dumpvars;
    $display("Sent byte --- 10010011");
    $monitor("Received byte --- %b",output_stream);
    check(8'b10010011);
    #(bit_period);
    if(output_stream==8'b10010011) begin
      $display("Correct sequence received.");
      $display("Receiving frequency --- %f MHz",25.0);
      $display("Sending frequency --- %f Mhz",2605000.0/bit_period);
    end
    else begin
      $display("Incorrect sequence received.");
      $display("Receiving frequency --- %f MHz",25.0);
      $display("Sending frequency --- %f Mhz",260500.0/bit_period);
    end
    $finish;
  end
endmodule