data/full_repos/permissive/46454310/waterbear.v
1: b'%Error: data/full_repos/permissive/46454310/waterbear.v:44: Duplicate declaration of signal: \'PC\'\n                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg[7:0]  PC;               \n            ^~\n        data/full_repos/permissive/46454310/waterbear.v:14: ... Location of original declaration\n  output[7:0] PC);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/46454310/waterbear.v:225: Signal definition not found, creating implicitly: \'reset\'\n                                                                      : ... Suggested alternative: \'rst\'\n  waterbear core1(clk, reset, PC);\n                       ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module multicore(
  input clk,
  input rst,
  output[7:0] PC);
  
  waterbear core1(clk, reset, PC);
  waterbear core2(clk, reset, PC);
  waterbear core3(clk, reset, PC);
  waterbear core4(clk, reset, PC);
  
endmodule
module multicore(
  input clk,
  input rst,
  output[7:0] PC);

  
  waterbear core1(clk, reset, PC);
  waterbear core2(clk, reset, PC);
  waterbear core3(clk, reset, PC);
  waterbear core4(clk, reset, PC);
  
endmodule