data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:23: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:81: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:90: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:97: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:104: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:111: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:115: Unsupported: wait statements\n        wait (tb_syn_task5.dut.LEDR[0] == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_task5.sv:116: syntax error, unexpected \'@\'\n        @(posedge CLOCK_50);\n        ^\n%Error: Exiting due to 7 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_task5();

    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [9:0] SW, LEDR;


    logic [7:0] exp_pt [255:0];

    task5 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task hex_checker;
        input [31:0] index;
        input [6:0] exp_HEX5, exp_HEX4, exp_HEX3, exp_HEX2, exp_HEX1, exp_HEX0;
        begin
            if (tb_syn_task5.dut.HEX5 !== exp_HEX5) begin
                $display("ERROR %dA: Expected HEX5 is %b, actual HEX5 is %b", index, exp_HEX5, tb_syn_task5.dut.HEX5);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX4 !== exp_HEX4) begin
                $display("ERROR %dB: Expected HEX4 is %b, actual HEX4 is %b", index, exp_HEX4, tb_syn_task5.dut.HEX4);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX3 !== exp_HEX3) begin
                $display("ERROR %dC: Expected HEX3 is %b, actual HEX3 is %b", index, exp_HEX3, tb_syn_task5.dut.HEX3);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX2 !== exp_HEX2) begin
                $display("ERROR %dD: Expected HEX2 is %b, actual HEX2 is %b", index, exp_HEX2, tb_syn_task5.dut.HEX2);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX1 !== exp_HEX1) begin
                $display("ERROR %dE: Expected HEX1 is %b, actual HEX1 is %b", index, exp_HEX1, tb_syn_task5.dut.HEX1);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX0 !== exp_HEX0) begin
                $display("ERROR %dF: Expected HEX0 is %b, actual HEX0 is %b", index, exp_HEX0, tb_syn_task5.dut.HEX0);
                err = 1'b1;
            end
        end
    endtask


    `define NONE   7'b1111111
    `define DASH   7'b0111111
    `define ZERO   7'b1000000
    `define ONE    7'b1111001
    `define SEVEN  7'b1111000
    `define EIGHT  7'b0000000


     `define KEY_MAX     24'hFFFFFF

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", tb_syn_task5.dut.\ct|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem);


        KEY[3] = 1'b0;
        @(posedge CLOCK_50);
        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 1: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 2: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b1) begin
            $display("ERROR 3: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b1, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 4: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        hex_checker(5, `NONE, `NONE, `NONE, `NONE, `NONE, `NONE);


        wait (tb_syn_task5.dut.LEDR[0] == 1'b1);
        @(posedge CLOCK_50);


        hex_checker(6, `ZERO, `ZERO, `ZERO, `ZERO, `ONE, `EIGHT);


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_task5.dut.\dc|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_syn_task5.dut.\dc|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_task5.dut.\dc|c1|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("C1.PT MEM [%d] ERROR: Expected c1.pt is %h, actual c1.pt is %h", i[7:0], exp_pt[i], tb_syn_task5.dut.\dc|c1|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_syn_task5();


    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [9:0] SW, LEDR;


    logic [7:0] exp_pt [255:0];

    task5 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task hex_checker;
        input [31:0] index;
        input [6:0] exp_HEX5, exp_HEX4, exp_HEX3, exp_HEX2, exp_HEX1, exp_HEX0;
        begin
            if (tb_syn_task5.dut.HEX5 !== exp_HEX5) begin
                $display("ERROR %dA: Expected HEX5 is %b, actual HEX5 is %b", index, exp_HEX5, tb_syn_task5.dut.HEX5);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX4 !== exp_HEX4) begin
                $display("ERROR %dB: Expected HEX4 is %b, actual HEX4 is %b", index, exp_HEX4, tb_syn_task5.dut.HEX4);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX3 !== exp_HEX3) begin
                $display("ERROR %dC: Expected HEX3 is %b, actual HEX3 is %b", index, exp_HEX3, tb_syn_task5.dut.HEX3);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX2 !== exp_HEX2) begin
                $display("ERROR %dD: Expected HEX2 is %b, actual HEX2 is %b", index, exp_HEX2, tb_syn_task5.dut.HEX2);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX1 !== exp_HEX1) begin
                $display("ERROR %dE: Expected HEX1 is %b, actual HEX1 is %b", index, exp_HEX1, tb_syn_task5.dut.HEX1);
                err = 1'b1;
            end
            if (tb_syn_task5.dut.HEX0 !== exp_HEX0) begin
                $display("ERROR %dF: Expected HEX0 is %b, actual HEX0 is %b", index, exp_HEX0, tb_syn_task5.dut.HEX0);
                err = 1'b1;
            end
        end
    endtask


    `define NONE   7'b1111111
    `define DASH   7'b0111111
    `define ZERO   7'b1000000
    `define ONE    7'b1111001
    `define SEVEN  7'b1111000
    `define EIGHT  7'b0000000


     `define KEY_MAX     24'hFFFFFF

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", tb_syn_task5.dut.\ct|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem);


        KEY[3] = 1'b0;
        @(posedge CLOCK_50);
        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 1: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 2: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b1) begin
            $display("ERROR 3: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b1, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        if (tb_syn_task5.dut.LEDR[0] !== 1'b0) begin
            $display("ERROR 4: Expected LEDR[0] is %d, actual LEDR[0] is %d", 1'b0, tb_syn_task5.dut.LEDR[0]);
            err = 1'b1;
        end


        @(posedge CLOCK_50);
        hex_checker(5, `NONE, `NONE, `NONE, `NONE, `NONE, `NONE);


        wait (tb_syn_task5.dut.LEDR[0] == 1'b1);
        @(posedge CLOCK_50);


        hex_checker(6, `ZERO, `ZERO, `ZERO, `ZERO, `ONE, `EIGHT);


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_task5.dut.\dc|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_syn_task5.dut.\dc|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_task5.dut.\dc|c1|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("C1.PT MEM [%d] ERROR: Expected c1.pt is %h, actual c1.pt is %h", i[7:0], exp_pt[i], tb_syn_task5.dut.\dc|c1|pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule