data/full_repos/permissive/489075769/read_address_ms.v
data/verilator_xmls/305d190c-6254-439f-b668-7f97aa70d8fb.xml
module read_address_slave(ACLK, ARESETn, i_ARREADY, o_ARREADY, ARVALID, i_ARADDR, o_ARADDR);

input ACLK, ARESETn;
input i_ARREADY, ARVALID;
input [31:0] i_ARADDR;

output reg [31:0] o_ARADDR;
output reg o_ARREADY;


always @(posedge ACLK) begin
o_ARREADY <= i_ARREADY;
if(ARESETn) begin
o_ARADDR <= 0;
o_ARREADY <= 0;
end

if(ARVALID && o_ARREADY) 
o_ARADDR <= i_ARADDR;
else
o_ARADDR<=0;
end

endmodule
module read_address_slave(ACLK, ARESETn, i_ARREADY, o_ARREADY, ARVALID, i_ARADDR, o_ARADDR);


input ACLK, ARESETn;
input i_ARREADY, ARVALID;
input [31:0] i_ARADDR;

output reg [31:0] o_ARADDR;
output reg o_ARREADY;


always @(posedge ACLK) begin
o_ARREADY <= i_ARREADY;
if(ARESETn) begin
o_ARADDR <= 0;
o_ARREADY <= 0;
end

if(ARVALID && o_ARREADY) 
o_ARADDR <= i_ARADDR;
else
o_ARADDR<=0;
end

endmodule