data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_6/rom_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_6,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_6/rom_TB.v\n%Error: Exiting due to 5 error(s)\n'
module rom_TB;
	reg  [3:0] address;
	wire [7:0] data;

	rom DUT(.address(address), .data(data));

	integer i;
	initial begin
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			#2;
		end	
	end

	initial begin
		$dumpfile("rom_TB.vcd");
		$dumpvars(0, rom_TB);
	end

endmodule
module rom_TB;

	reg  [3:0] address;
	wire [7:0] data;

	rom DUT(.address(address), .data(data));

	integer i;
	initial begin
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			#2;
		end	
	end

	initial begin
		$dumpfile("rom_TB.vcd");
		$dumpvars(0, rom_TB);
	end

endmodule