data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n always #50 clock  <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #10 io_clk <= (io_clk === 1\'b0);\n        ^\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:94: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("kairos_wb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:95: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, kairos_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:99: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos_wb/kairos_wb_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module kairos_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	reg io_clk;





	always #50 clock  <= (clock === 1'b0);
	always #10 io_clk <= (io_clk === 1'b0);

	initial begin
		clock = 0;
		io_clk = 0;
	end

    reg    [`ADDR_WIDTH - 1 : 0] input_adr_r;

    wire                         input_rdy_w;
    reg                          input_vld_r;
    reg   [`INPUT_WIDTH - 1 : 0] input_data_r;

    reg                          output_rdy_r;
    wire                         output_vld_w;
    wire [`OUTPUT_WIDTH - 1 : 0] output_data_w;

    integer file;


    assign mprj_io[37]   = io_clk;
    assign mprj_io[36]   = RSTB;
    assign mprj_io[15:0] = input_data_r;
    assign mprj_io[16]   = input_rdy_w & input_vld_r;
    assign mprj_io[17]   = output_rdy_r;


    assign output_data_w = mprj_io[33:18];
    assign output_vld_w  = mprj_io[34];
    assign input_rdy_w   = mprj_io[35];











	initial begin
		$dumpfile("kairos_wb.vcd");
		$dumpvars(0, kairos_tb);


		repeat (200) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("kairos_wb.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module kairos_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	reg io_clk;





	always #50 clock  <= (clock === 1'b0);
	always #10 io_clk <= (io_clk === 1'b0);

	initial begin
		clock = 0;
		io_clk = 0;
	end

    reg    [`ADDR_WIDTH - 1 : 0] input_adr_r;

    wire                         input_rdy_w;
    reg                          input_vld_r;
    reg   [`INPUT_WIDTH - 1 : 0] input_data_r;

    reg                          output_rdy_r;
    wire                         output_vld_w;
    wire [`OUTPUT_WIDTH - 1 : 0] output_data_w;

    integer file;


    assign mprj_io[37]   = io_clk;
    assign mprj_io[36]   = RSTB;
    assign mprj_io[15:0] = input_data_r;
    assign mprj_io[16]   = input_rdy_w & input_vld_r;
    assign mprj_io[17]   = output_rdy_r;


    assign output_data_w = mprj_io[33:18];
    assign output_vld_w  = mprj_io[34];
    assign input_rdy_w   = mprj_io[35];











	initial begin
		$dumpfile("kairos_wb.vcd");
		$dumpvars(0, kairos_tb);


		repeat (200) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("kairos_wb.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule