data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/2012_q2b/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/2012_q2b,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/2012_q2b/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire [5:0] y,
    input wire w,
    output wire Y1,
    output wire Y3
);

  parameter STATE_A = 3'd0;
  parameter STATE_B = 3'd1;
  parameter STATE_C = 3'd2;
  parameter STATE_D = 3'd3;
  parameter STATE_E = 3'd4;
  parameter STATE_F = 3'd5;

  wire [5:0] state, next_state;
  assign state = y;
  assign Y1 = next_state[1];
  assign Y3 = next_state[3];


  assign next_state[STATE_A] =
    state[STATE_A] & ~w |
    state[STATE_D] & ~w;

  assign next_state[STATE_B] =
    state[STATE_A] & w;

  assign next_state[STATE_C] =
    state[STATE_B] & w |
    state[STATE_F] & w;

  assign next_state[STATE_D] =
    state[STATE_B] & ~w |
    state[STATE_C] & ~w |
    state[STATE_E] & ~w |
    state[STATE_F] & ~w;

  assign next_state[STATE_E] =
    state[STATE_E] & w |
    state[STATE_C] & w;

  assign next_state[STATE_F] =
    state[STATE_D] & w;

endmodule
module top_module (
    input wire [5:0] y,
    input wire w,
    output wire Y1,
    output wire Y3
);


  parameter STATE_A = 3'd0;
  parameter STATE_B = 3'd1;
  parameter STATE_C = 3'd2;
  parameter STATE_D = 3'd3;
  parameter STATE_E = 3'd4;
  parameter STATE_F = 3'd5;

  wire [5:0] state, next_state;
  assign state = y;
  assign Y1 = next_state[1];
  assign Y3 = next_state[3];


  assign next_state[STATE_A] =
    state[STATE_A] & ~w |
    state[STATE_D] & ~w;

  assign next_state[STATE_B] =
    state[STATE_A] & w;

  assign next_state[STATE_C] =
    state[STATE_B] & w |
    state[STATE_F] & w;

  assign next_state[STATE_D] =
    state[STATE_B] & ~w |
    state[STATE_C] & ~w |
    state[STATE_E] & ~w |
    state[STATE_F] & ~w;

  assign next_state[STATE_E] =
    state[STATE_E] & w |
    state[STATE_C] & w;

  assign next_state[STATE_F] =
    state[STATE_D] & w;

endmodule