data/full_repos/permissive/470392519/rtl/Regfile.v
1: b'%Error: data/full_repos/permissive/470392519/rtl/Regfile.v:1: Cannot find include file: types.vh\n`include "types.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.v\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.sv\n             types.vh\n             types.vh.v\n             types.vh.sv\n             obj_dir/types.vh\n             obj_dir/types.vh.v\n             obj_dir/types.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module Regfile (
    input                       i_clk, i_wrEn,
    input   [(ADDR_WIDTH-1):0]  i_rs1Addr, i_rs2Addr, i_rdAddr,
    input   [(XLEN-1):0]        i_rdData,
    output  [(XLEN-1):0]        o_rs1Data, o_rs2Data
);
    parameter XLEN          = 32;
    parameter ADDR_WIDTH    = 5;

    reg                 r_fwdRs1En, r_fwdRs2En;
    reg  [(XLEN-1):0]   r_rdDataSave;
    wire [(XLEN-1):0]   w_rs1PortOut, w_rs2PortOut;


    DualPortRam #(
        .XLEN(XLEN),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) RS1_PORT (
        .i_clk                (i_clk),
        .i_we                 (i_wrEn),
        .i_dataIn             (i_rdData),
        .i_rAddr              (i_rs1Addr),
        .i_wAddr              (i_rdAddr),
        .o_q                  (w_rs1PortOut)
    );
    DualPortRam #(
        .XLEN(XLEN),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) RS2_PORT (
        .i_clk                (i_clk),
        .i_we                 (i_wrEn),
        .i_dataIn             (i_rdData),
        .i_rAddr              (i_rs2Addr),
        .i_wAddr              (i_rdAddr),
        .o_q                  (w_rs2PortOut)
    );


    always @(posedge i_clk) begin
        r_fwdRs1En      <= (i_rs1Addr == i_rdAddr) && i_wrEn;
        r_fwdRs2En      <= (i_rs2Addr == i_rdAddr) && i_wrEn;
        r_rdDataSave    <= i_rdData;
    end
    assign o_rs1Data    = r_fwdRs1En ? r_rdDataSave : w_rs1PortOut;
    assign o_rs2Data    = r_fwdRs2En ? r_rdDataSave : w_rs2PortOut;

endmodule
module Regfile (
    input                       i_clk, i_wrEn,
    input   [(ADDR_WIDTH-1):0]  i_rs1Addr, i_rs2Addr, i_rdAddr,
    input   [(XLEN-1):0]        i_rdData,
    output  [(XLEN-1):0]        o_rs1Data, o_rs2Data
);

    parameter XLEN          = 32;
    parameter ADDR_WIDTH    = 5;

    reg                 r_fwdRs1En, r_fwdRs2En;
    reg  [(XLEN-1):0]   r_rdDataSave;
    wire [(XLEN-1):0]   w_rs1PortOut, w_rs2PortOut;


    DualPortRam #(
        .XLEN(XLEN),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) RS1_PORT (
        .i_clk                (i_clk),
        .i_we                 (i_wrEn),
        .i_dataIn             (i_rdData),
        .i_rAddr              (i_rs1Addr),
        .i_wAddr              (i_rdAddr),
        .o_q                  (w_rs1PortOut)
    );
    DualPortRam #(
        .XLEN(XLEN),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) RS2_PORT (
        .i_clk                (i_clk),
        .i_we                 (i_wrEn),
        .i_dataIn             (i_rdData),
        .i_rAddr              (i_rs2Addr),
        .i_wAddr              (i_rdAddr),
        .o_q                  (w_rs2PortOut)
    );


    always @(posedge i_clk) begin
        r_fwdRs1En      <= (i_rs1Addr == i_rdAddr) && i_wrEn;
        r_fwdRs2En      <= (i_rs2Addr == i_rdAddr) && i_wrEn;
        r_rdDataSave    <= i_rdData;
    end
    assign o_rs1Data    = r_fwdRs1En ? r_rdDataSave : w_rs1PortOut;
    assign o_rs2Data    = r_fwdRs2En ? r_rdDataSave : w_rs2PortOut;

endmodule