data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:32: Cannot find file containing module: 'imem'\n    imem my_imem(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/imem\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/imem.v\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/imem.sv\n             imem\n             imem.v\n             imem.sv\n             obj_dir/imem\n             obj_dir/imem.v\n             obj_dir/imem.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:41: Cannot find file containing module: 'clk_div_2'\n  clk_div_2 clock_div_2(.clk(clock) ,.rst(~reset), .out_clk(dmem_clock));\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:48: Cannot find file containing module: 'dmem'\n    dmem my_dmem(\n    ^~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:58: Cannot find file containing module: 'clk_div_4'\n  clk_div_4 clock_div_4(.clk(clock) ,.reset(reset), .clk_out(regfile_clock));\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:66: Cannot find file containing module: 'regfile'\n    regfile my_regfile(\n    ^~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:81: Cannot find file containing module: 'clk_div_4'\n  clk_div_4 clock_divider_4(.clk(clock) ,.reset(reset), .clk_out(processor_clock));\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/skeleton.v:83: Cannot find file containing module: 'processor'\n    processor my_processor(\n    ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module skeleton(clock, reset, imem_clock, dmem_clock, processor_clock, regfile_clock);
    input clock, reset;

    output imem_clock, dmem_clock, processor_clock, regfile_clock;
	
	 



	 assign imem_clock = clock; 
	 
	 
    wire [11:0] address_imem;
    wire [31:0] q_imem;
    imem my_imem(
        .address    (address_imem),
        .clock      (imem_clock),
        .q          (q_imem)
    );




	 clk_div_2 clock_div_2(.clk(clock) ,.rst(~reset), .out_clk(dmem_clock));
	 
	 
    wire [11:0] address_dmem;
    wire [31:0] data;
    wire wren;
    wire [31:0] q_dmem;
    dmem my_dmem(
        .address    (address_dmem),
        .clock      (~dmem_clock),
        .data	    (data),
        .wren	    (wren),
        .q          (q_dmem)
    );



	 clk_div_4 clock_div_4(.clk(clock) ,.reset(reset), .clk_out(regfile_clock));
	 
    wire ctrl_writeEnable;
    wire [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    wire [31:0] data_writeReg;
    wire [31:0] data_readRegA, data_readRegB;
	 
	 
    regfile my_regfile(
        ~regfile_clock,
        ctrl_writeEnable,
        reset,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB,
    );
	 
	 


	 clk_div_4 clock_divider_4(.clk(clock) ,.reset(reset), .clk_out(processor_clock));
	 
    processor my_processor(

        processor_clock,
        reset,


        address_imem,
        q_imem,


        address_dmem,
        data,
        wren,
        q_dmem,


        ctrl_writeEnable,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
    );
	
	
	
endmodule
module skeleton(clock, reset, imem_clock, dmem_clock, processor_clock, regfile_clock);

    input clock, reset;

    output imem_clock, dmem_clock, processor_clock, regfile_clock;
	
	 



	 assign imem_clock = clock; 
	 
	 
    wire [11:0] address_imem;
    wire [31:0] q_imem;
    imem my_imem(
        .address    (address_imem),
        .clock      (imem_clock),
        .q          (q_imem)
    );




	 clk_div_2 clock_div_2(.clk(clock) ,.rst(~reset), .out_clk(dmem_clock));
	 
	 
    wire [11:0] address_dmem;
    wire [31:0] data;
    wire wren;
    wire [31:0] q_dmem;
    dmem my_dmem(
        .address    (address_dmem),
        .clock      (~dmem_clock),
        .data	    (data),
        .wren	    (wren),
        .q          (q_dmem)
    );



	 clk_div_4 clock_div_4(.clk(clock) ,.reset(reset), .clk_out(regfile_clock));
	 
    wire ctrl_writeEnable;
    wire [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    wire [31:0] data_writeReg;
    wire [31:0] data_readRegA, data_readRegB;
	 
	 
    regfile my_regfile(
        ~regfile_clock,
        ctrl_writeEnable,
        reset,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB,
    );
	 
	 


	 clk_div_4 clock_divider_4(.clk(clock) ,.reset(reset), .clk_out(processor_clock));
	 
    processor my_processor(

        processor_clock,
        reset,


        address_imem,
        q_imem,


        address_dmem,
        data,
        wren,
        q_dmem,


        ctrl_writeEnable,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
    );
	
	
	
endmodule