data/full_repos/permissive/522668124/verilog/rtl/DMemory.sv
data/verilator_xmls/24c7959d-1b66-4408-8e68-9b9a45a41492.xml
module DMemory

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif

  input  logic         clk,
  input  logic         rst_n,
  input  logic         mem_write,
  input  logic  [4:0]  rd,
  input  logic  [2:0]  funct3,
  input  logic  [31:0] memory_address,
  input  logic  [31:0] write_data,
  
  input  logic  [3:0] la_dram_select,
  
  output logic [31:0]  read_data,
  
  output logic [31:0]  la_read_data

);

  logic [31:0] dram[0:15];
  

  integer i;
  always_ff @(negedge clk) begin
    if (!rst_n) begin
      for (i=0;i<15;i=i+1) begin
        dram[i] = 32'h00000000;
      end
    end else if (mem_write) begin
      case (funct3)
        3'b000: dram[memory_address][31:0] <= {{24{1'b0}}, write_data[7:0]};
        3'b001: dram[memory_address][31:0] <= {{16{1'b0}}, write_data[15:0]};
        3'b010: dram[memory_address][31:0] <= write_data[31:0];
        default: dram[memory_address] <= write_data;
      endcase
    end 
  end
  

  always_ff  @(posedge clk) begin 
    read_data <= dram[memory_address];
    la_read_data <= dram[la_dram_select];
  end

endmodule
module DMemory

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif

  input  logic         clk,
  input  logic         rst_n,
  input  logic         mem_write,
  input  logic  [4:0]  rd,
  input  logic  [2:0]  funct3,
  input  logic  [31:0] memory_address,
  input  logic  [31:0] write_data,
  
  input  logic  [3:0] la_dram_select,
  
  output logic [31:0]  read_data,
  
  output logic [31:0]  la_read_data

);


  logic [31:0] dram[0:15];
  

  integer i;
  always_ff @(negedge clk) begin
    if (!rst_n) begin
      for (i=0;i<15;i=i+1) begin
        dram[i] = 32'h00000000;
      end
    end else if (mem_write) begin
      case (funct3)
        3'b000: dram[memory_address][31:0] <= {{24{1'b0}}, write_data[7:0]};
        3'b001: dram[memory_address][31:0] <= {{16{1'b0}}, write_data[15:0]};
        3'b010: dram[memory_address][31:0] <= write_data[31:0];
        default: dram[memory_address] <= write_data;
      endcase
    end 
  end
  

  always_ff  @(posedge clk) begin 
    read_data <= dram[memory_address];
    la_read_data <= dram[la_dram_select];
  end

endmodule