data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/CODESIGN.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/CODESIGN.v:27: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                           : ... In instance CODESIGN\n        codeSign = d[WL-1] == \'b1 ? \'b11 : d[WL-1] == \'b0 ? \'b01 : \'bXX;       \n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module CODESIGN #(parameter WL = 16)(
        input signed [WL-1:0] d,
        output reg signed [1:0] codeSign
    );
    always @(*) begin
        codeSign = d[WL-1] == 'b1 ? 'b11 : d[WL-1] == 'b0 ? 'b01 : 'bXX;       
    end
endmodule
module CODESIGN #(parameter WL = 16)(
        input signed [WL-1:0] d,
        output reg signed [1:0] codeSign
    );

    always @(*) begin
        codeSign = d[WL-1] == 'b1 ? 'b11 : d[WL-1] == 'b0 ? 'b01 : 'bXX;       
    end
endmodule