data/full_repos/permissive/487568919/SvLibDR/ReceiverUART/ReceiverUART.sv
1: b"%Error: data/full_repos/permissive/487568919/SvLibDR/ReceiverUART/ReceiverUART.sv:55: Cannot find file containing module: 'SingleRxUART'\nSingleRxUART SingleRxUART\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/SvLibDR/ReceiverUART,data/full_repos/permissive/487568919/SingleRxUART\n             data/full_repos/permissive/487568919/SvLibDR/ReceiverUART,data/full_repos/permissive/487568919/SingleRxUART.v\n             data/full_repos/permissive/487568919/SvLibDR/ReceiverUART,data/full_repos/permissive/487568919/SingleRxUART.sv\n             SingleRxUART\n             SingleRxUART.v\n             SingleRxUART.sv\n             obj_dir/SingleRxUART\n             obj_dir/SingleRxUART.v\n             obj_dir/SingleRxUART.sv\n%Error: data/full_repos/permissive/487568919/SvLibDR/ReceiverUART/ReceiverUART.sv:68: Cannot find file containing module: 'RxUART_logic'\nRxUART_logic RxUART_logic\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/SvLibDR/ReceiverUART/ReceiverUART.sv:89: Cannot find file containing module: 'RxUART_timeout'\nRxUART_timeout RxUART_timeout\n^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ReceiverUART 
#(
	parameter int CLOCK = 10_000_000,
	parameter int BAUD = 1_000_000,
	parameter PARITY = "NO",
	parameter FIRST_BIT = "LSB",
	parameter NUMBER = 256,
	parameter TIMEOUT = 10
)
(
input clk,
input reset,
input rxd,
output rx_done,
output [7:0] cmd_rx,
output [clogb2(NUMBER)-1:0] len_rx,
output [7:0] wr_data,
output [clogb2(NUMBER)-1:0] wr_addr,
output wr_clock,
output we
);



wire [7:0] rx_data;
wire single_done;
wire single_busy;
wire timeout;



defparam SingleRxUART.CLOCK = CLOCK;
defparam SingleRxUART.BAUD = BAUD;
defparam SingleRxUART.PARITY = PARITY;
defparam SingleRxUART.FIRST_BIT = FIRST_BIT;
SingleRxUART SingleRxUART
(
  .clk (clk), .reset (reset),
  .rxd (rxd),
  .rx_data (rx_data), 
  .parity_err (),
  .done (single_done),
  .busy (single_busy)
);



defparam RxUART_logic.NUMBER = NUMBER;
RxUART_logic RxUART_logic
(
  .clk (clk), .reset (reset),
  .rx_data (rx_data),
  .rx_done (single_done),
  .timeout (timeout),
  .pck_done (rx_done),
  .cmd_rx (cmd_rx),
  .len_rx (len_rx),
  .wr_data (wr_data),
  .wr_addr (wr_addr),
  .wr_clock (wr_clock),
  .we (we)
);



defparam RxUART_timeout.CLOCK = CLOCK;
defparam RxUART_timeout.BAUD = BAUD;
defparam RxUART_timeout.PARITY = PARITY;
defparam RxUART_timeout.TIMEOUT = TIMEOUT;
RxUART_timeout RxUART_timeout
(
  .clk (clk), .reset (reset),
  .rx_done (single_done), .rx_busy (single_busy),
  .timeout (timeout)
);

endmodule
module ReceiverUART 
#(
	parameter int CLOCK = 10_000_000,
	parameter int BAUD = 1_000_000,
	parameter PARITY = "NO",
	parameter FIRST_BIT = "LSB",
	parameter NUMBER = 256,
	parameter TIMEOUT = 10
)
(
input clk,
input reset,
input rxd,
output rx_done,
output [7:0] cmd_rx,
output [clogb2(NUMBER)-1:0] len_rx,
output [7:0] wr_data,
output [clogb2(NUMBER)-1:0] wr_addr,
output wr_clock,
output we
);




wire [7:0] rx_data;
wire single_done;
wire single_busy;
wire timeout;



defparam SingleRxUART.CLOCK = CLOCK;
defparam SingleRxUART.BAUD = BAUD;
defparam SingleRxUART.PARITY = PARITY;
defparam SingleRxUART.FIRST_BIT = FIRST_BIT;
SingleRxUART SingleRxUART
(
  .clk (clk), .reset (reset),
  .rxd (rxd),
  .rx_data (rx_data), 
  .parity_err (),
  .done (single_done),
  .busy (single_busy)
);



defparam RxUART_logic.NUMBER = NUMBER;
RxUART_logic RxUART_logic
(
  .clk (clk), .reset (reset),
  .rx_data (rx_data),
  .rx_done (single_done),
  .timeout (timeout),
  .pck_done (rx_done),
  .cmd_rx (cmd_rx),
  .len_rx (len_rx),
  .wr_data (wr_data),
  .wr_addr (wr_addr),
  .wr_clock (wr_clock),
  .we (we)
);



defparam RxUART_timeout.CLOCK = CLOCK;
defparam RxUART_timeout.BAUD = BAUD;
defparam RxUART_timeout.PARITY = PARITY;
defparam RxUART_timeout.TIMEOUT = TIMEOUT;
RxUART_timeout RxUART_timeout
(
  .clk (clk), .reset (reset),
  .rx_done (single_done), .rx_busy (single_busy),
  .timeout (timeout)
);

endmodule