data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/ece241_2013_q8/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/ece241_2013_q8,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/ece241_2013_q8/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire aresetn,
    input  wire x,
    output reg  z
);

  parameter STATE_S0 = 2'b00;
  parameter STATE_S1 = 2'b01;
  parameter STATE_S2 = 2'b10;
  parameter STATE_ILLEGAL = 2'b11;

  reg [1:0] state, next_state = STATE_S0;


  always @(*) begin
    casez ({
      x, state
    })
      {1'b0, STATE_S0} : next_state = STATE_S0;
      {1'b1, STATE_S0} : next_state = STATE_S1;

      {1'b0, STATE_S1} : next_state = STATE_S2;
      {1'b1, STATE_S1} : next_state = STATE_S1;

      {1'b0, STATE_S2} : next_state = STATE_S0;
      {1'b1, STATE_S2} : next_state = STATE_S1;

      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk, negedge aresetn) begin
    if (~aresetn) state <= STATE_S0;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case ({
      state, x
    })
      {STATE_S0, 1'b0} : z = 1'b0;
      {STATE_S0, 1'b1} : z = 1'b0;
      {STATE_S1, 1'b0} : z = 1'b0;
      {STATE_S1, 1'b1} : z = 1'b0;
      {STATE_S2, 1'b0} : z = 1'b0;
      {STATE_S2, 1'b1} : z = 1'b1;
      default: z = 1'bx;
    endcase
  end

endmodule
module top_module (
    input  wire clk,
    input  wire aresetn,
    input  wire x,
    output reg  z
);


  parameter STATE_S0 = 2'b00;
  parameter STATE_S1 = 2'b01;
  parameter STATE_S2 = 2'b10;
  parameter STATE_ILLEGAL = 2'b11;

  reg [1:0] state, next_state = STATE_S0;


  always @(*) begin
    casez ({
      x, state
    })
      {1'b0, STATE_S0} : next_state = STATE_S0;
      {1'b1, STATE_S0} : next_state = STATE_S1;

      {1'b0, STATE_S1} : next_state = STATE_S2;
      {1'b1, STATE_S1} : next_state = STATE_S1;

      {1'b0, STATE_S2} : next_state = STATE_S0;
      {1'b1, STATE_S2} : next_state = STATE_S1;

      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk, negedge aresetn) begin
    if (~aresetn) state <= STATE_S0;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case ({
      state, x
    })
      {STATE_S0, 1'b0} : z = 1'b0;
      {STATE_S0, 1'b1} : z = 1'b0;
      {STATE_S1, 1'b0} : z = 1'b0;
      {STATE_S1, 1'b1} : z = 1'b0;
      {STATE_S2, 1'b0} : z = 1'b0;
      {STATE_S2, 1'b1} : z = 1'b1;
      default: z = 1'bx;
    endcase
  end

endmodule