data/full_repos/permissive/49670587/vtr/vtr_flow/benchmarks/verilog/single_inv/single_inv.v
data/verilator_xmls/de9ea5cd-68ab-49a8-87f9-2f07396773de.xml
module single_inv
(
    d_in,
    d_out,
    clock,
    rst
);

    input clock;
    input rst;
    input d_in;

    output d_out;

    assign d_out = ~d_in;

endmodule
module single_inv
(
    d_in,
    d_out,
    clock,
    rst
);


    input clock;
    input rst;
    input d_in;

    output d_out;

    assign d_out = ~d_in;

endmodule