data/full_repos/permissive/493019833/test/testcase/firrtl/VendingMachineSwitch/VendingMachineSwitch-Berkeley.v
data/verilator_xmls/a926abb9-ab3d-4985-9c4d-f93d283ca29a.xml
module VendingMachineSwitch(
  input   clock,
  input   reset,
  input   io_nickel,
  input   io_dime,
  output  io_valid
);
  reg [2:0] state;
  reg [31:0] _RAND_0;
  wire  _T_12;
  wire [2:0] _GEN_0;
  wire [2:0] _GEN_1;
  wire  _T_13;
  wire [2:0] _GEN_2;
  wire [2:0] _GEN_3;
  wire  _T_14;
  wire [2:0] _GEN_4;
  wire [2:0] _GEN_5;
  wire  _T_15;
  wire [2:0] _GEN_6;
  wire [2:0] _GEN_7;
  wire  _T_16;
  wire [2:0] _GEN_8;
  wire [2:0] _GEN_9;
  wire [2:0] _GEN_10;
  wire [2:0] _GEN_11;
  wire [2:0] _GEN_12;
  assign _T_12 = 3'h0 == state;
  assign _GEN_0 = io_nickel ? 3'h1 : state;
  assign _GEN_1 = io_dime ? 3'h2 : _GEN_0;
  assign _T_13 = 3'h1 == state;
  assign _GEN_2 = io_nickel ? 3'h2 : state;
  assign _GEN_3 = io_dime ? 3'h3 : _GEN_2;
  assign _T_14 = 3'h2 == state;
  assign _GEN_4 = io_nickel ? 3'h3 : state;
  assign _GEN_5 = io_dime ? 3'h4 : _GEN_4;
  assign _T_15 = 3'h3 == state;
  assign _GEN_6 = io_nickel ? 3'h4 : state;
  assign _GEN_7 = io_dime ? 3'h4 : _GEN_6;
  assign _T_16 = 3'h4 == state;
  assign _GEN_8 = _T_16 ? 3'h0 : state;
  assign _GEN_9 = _T_15 ? _GEN_7 : _GEN_8;
  assign _GEN_10 = _T_14 ? _GEN_5 : _GEN_9;
  assign _GEN_11 = _T_13 ? _GEN_3 : _GEN_10;
  assign _GEN_12 = _T_12 ? _GEN_1 : _GEN_11;
  assign io_valid = state == 3'h4;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[2:0];
  `endif
  end
`endif
  always @(posedge clock) begin
    if (reset) begin
      state <= 3'h0;
    end else begin
      if (_T_12) begin
        if (io_dime) begin
          state <= 3'h2;
        end else begin
          if (io_nickel) begin
            state <= 3'h1;
          end
        end
      end else begin
        if (_T_13) begin
          if (io_dime) begin
            state <= 3'h3;
          end else begin
            if (io_nickel) begin
              state <= 3'h2;
            end
          end
        end else begin
          if (_T_14) begin
            if (io_dime) begin
              state <= 3'h4;
            end else begin
              if (io_nickel) begin
                state <= 3'h3;
              end
            end
          end else begin
            if (_T_15) begin
              if (io_dime) begin
                state <= 3'h4;
              end else begin
                if (io_nickel) begin
                  state <= 3'h4;
                end
              end
            end else begin
              if (_T_16) begin
                state <= 3'h0;
              end
            end
          end
        end
      end
    end
  end
endmodule
module VendingMachineSwitch(
  input   clock,
  input   reset,
  input   io_nickel,
  input   io_dime,
  output  io_valid
);

  reg [2:0] state;
  reg [31:0] _RAND_0;
  wire  _T_12;
  wire [2:0] _GEN_0;
  wire [2:0] _GEN_1;
  wire  _T_13;
  wire [2:0] _GEN_2;
  wire [2:0] _GEN_3;
  wire  _T_14;
  wire [2:0] _GEN_4;
  wire [2:0] _GEN_5;
  wire  _T_15;
  wire [2:0] _GEN_6;
  wire [2:0] _GEN_7;
  wire  _T_16;
  wire [2:0] _GEN_8;
  wire [2:0] _GEN_9;
  wire [2:0] _GEN_10;
  wire [2:0] _GEN_11;
  wire [2:0] _GEN_12;
  assign _T_12 = 3'h0 == state;
  assign _GEN_0 = io_nickel ? 3'h1 : state;
  assign _GEN_1 = io_dime ? 3'h2 : _GEN_0;
  assign _T_13 = 3'h1 == state;
  assign _GEN_2 = io_nickel ? 3'h2 : state;
  assign _GEN_3 = io_dime ? 3'h3 : _GEN_2;
  assign _T_14 = 3'h2 == state;
  assign _GEN_4 = io_nickel ? 3'h3 : state;
  assign _GEN_5 = io_dime ? 3'h4 : _GEN_4;
  assign _T_15 = 3'h3 == state;
  assign _GEN_6 = io_nickel ? 3'h4 : state;
  assign _GEN_7 = io_dime ? 3'h4 : _GEN_6;
  assign _T_16 = 3'h4 == state;
  assign _GEN_8 = _T_16 ? 3'h0 : state;
  assign _GEN_9 = _T_15 ? _GEN_7 : _GEN_8;
  assign _GEN_10 = _T_14 ? _GEN_5 : _GEN_9;
  assign _GEN_11 = _T_13 ? _GEN_3 : _GEN_10;
  assign _GEN_12 = _T_12 ? _GEN_1 : _GEN_11;
  assign io_valid = state == 3'h4;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[2:0];
  `endif
  end
`endif
  always @(posedge clock) begin
    if (reset) begin
      state <= 3'h0;
    end else begin
      if (_T_12) begin
        if (io_dime) begin
          state <= 3'h2;
        end else begin
          if (io_nickel) begin
            state <= 3'h1;
          end
        end
      end else begin
        if (_T_13) begin
          if (io_dime) begin
            state <= 3'h3;
          end else begin
            if (io_nickel) begin
              state <= 3'h2;
            end
          end
        end else begin
          if (_T_14) begin
            if (io_dime) begin
              state <= 3'h4;
            end else begin
              if (io_nickel) begin
                state <= 3'h3;
              end
            end
          end else begin
            if (_T_15) begin
              if (io_dime) begin
                state <= 3'h4;
              end else begin
                if (io_nickel) begin
                  state <= 3'h4;
                end
              end
            end else begin
              if (_T_16) begin
                state <= 3'h0;
              end
            end
          end
        end
      end
    end
  end
endmodule