data/full_repos/permissive/406635962/src/rtl/cpu_top.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:9: Define or directive not defined: \'`PC_SIZE\'\n    input[`PC_SIZE-1:0] pc_rtvec, \n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:10: Define or directive not defined: \'`ITCM_RAM_AW\'\n    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:11: Define or directive not defined: \'`DTCM_RAM_AW\'\n    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:17: Define or directive not defined: \'`ITCM_RAM_DW\'\nwire [`ITCM_RAM_DW-1:0] itcm_ram_dout;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:20: Define or directive not defined: \'`DTCM_RAM_DW\'\nwire [`DTCM_RAM_DW-1:0] dtcm_ram_din;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:21: Define or directive not defined: \'`DTCM_RAM_MW\'\nwire [`DTCM_RAM_MW-1:0] dtcm_ram_wem;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu_top.v:22: Define or directive not defined: \'`DTCM_RAM_DW\'\nwire [`DTCM_RAM_DW-1:0] dtcm_ram_dout;\n      ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module cpu_top (
    input[`PC_SIZE-1:0] pc_rtvec,
    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    input clk,
    input rst_n
);


wire [`ITCM_RAM_DW-1:0] itcm_ram_dout;

wire dtcm_ram_we;
wire [`DTCM_RAM_DW-1:0] dtcm_ram_din;
wire [`DTCM_RAM_MW-1:0] dtcm_ram_wem;
wire [`DTCM_RAM_DW-1:0] dtcm_ram_dout;

cpu u_cpu (
    .pc_rtvec(pc_rtvec),
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);


srams u_srams (
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk)
);
endmodule
module cpu_top (
    input[`PC_SIZE-1:0] pc_rtvec,
    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    input clk,
    input rst_n
);



wire [`ITCM_RAM_DW-1:0] itcm_ram_dout;

wire dtcm_ram_we;
wire [`DTCM_RAM_DW-1:0] dtcm_ram_din;
wire [`DTCM_RAM_MW-1:0] dtcm_ram_wem;
wire [`DTCM_RAM_DW-1:0] dtcm_ram_dout;

cpu u_cpu (
    .pc_rtvec(pc_rtvec),
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);


srams u_srams (
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk)
);
endmodule