data/full_repos/permissive/52696447/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #10000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Error: data/full_repos/permissive/52696447/testbench.v:63: Cannot find file containing module: \'i2c_master\'\n i2c_master uut2 (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/i2c_master\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/i2c_master.v\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/i2c_master.sv\n             i2c_master\n             i2c_master.v\n             i2c_master.sv\n             obj_dir/i2c_master\n             obj_dir/i2c_master.v\n             obj_dir/i2c_master.sv\n%Error: data/full_repos/permissive/52696447/testbench.v:79: Cannot find file containing module: \'clk_divider\'\n clk_divider #(.DIVIDER(500)) i2c_clk_divider (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/52696447/testbench.v:85: Cannot find file containing module: \'read_eeprom\'\n read_eeprom uut (\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/52696447/testbench.v:126: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'haa\' generates 8 bits.\n                                                                   : ... In instance testbench\n  slave_addr = 8\'haa;\n             ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


	reg clk;
	reg reset;
	reg i2c_reset;
	reg [15:0] mem_addr;
	reg [6:0] slave_addr;
	reg [7:0] read_nbytes;
	reg data_ready;

	reg start;



	wire scl;
	wire [7:0] data_out;



	wire sda_w;


	wire i2c_clk;
	wire [7:0] i2c_nbytes;
	wire [6:0] i2c_slave_addr;
	wire i2c_rw;
	wire [7:0] i2c_write_data;
	wire [7:0] i2c_read_data;
	wire i2c_tx_data_req;
	wire i2c_rx_data_ready;
	wire i2c_start;
	
	wire byte_ready;




	i2c_master uut2 (
		.clk(i2c_clk), 
		.reset(i2c_reset), 
		.start(i2c_start), 
		.nbytes_in(i2c_nbytes), 
		.addr_in(i2c_slave_addr), 
		.rw_in(i2c_rw), 
		.write_data(i2c_write_data), 
		.read_data(i2c_read_data), 
		.tx_data_req(i2c_tx_data_req), 
		.rx_data_ready(i2c_rx_data_ready), 
		.sda_w(sda_w), 
		.scl(scl)
	);


	clk_divider #(.DIVIDER(500)) i2c_clk_divider (
		.reset(reset), 
		.clk_in(clk), 
		.clk_out(i2c_clk)
	);
	
	read_eeprom uut (
    .clk(clk), 
    .reset(reset), 
    .slave_addr_w(slave_addr), 
    .mem_addr_w(mem_addr), 
    .read_nbytes_w(read_nbytes), 
    .start(start), 
    .i2c_slave_addr(i2c_slave_addr), 
    .i2c_rw(i2c_rw), 
    .i2c_write_data(i2c_write_data), 
    .i2c_nbytes(i2c_nbytes), 
    .i2c_read_data(i2c_read_data), 
    .i2c_tx_data_req(i2c_tx_data_req), 
    .i2c_rx_data_ready(i2c_rx_data_ready), 
    .i2c_start(i2c_start), 
    .data_out(data_out), 
    .byte_ready(byte_ready)
    );
	 
	
	initial begin

		clk = 0;
		forever begin 
			clk = #1 ~clk;
		end
	end

	initial begin

		reset = 1;
		i2c_reset = 1;


		#5000;

		reset = 0;
		#5000;
        

		i2c_reset = 0;
		slave_addr = 8'haa;
		mem_addr = 16'hF0F0;
		read_nbytes = 2;
		
		#10000;
		

		start = 1;
		
		
		#10000
		start = 0;
		#100000;
		
		
		$finish;
		
	end
      
endmodule
module testbench;



	reg clk;
	reg reset;
	reg i2c_reset;
	reg [15:0] mem_addr;
	reg [6:0] slave_addr;
	reg [7:0] read_nbytes;
	reg data_ready;

	reg start;



	wire scl;
	wire [7:0] data_out;



	wire sda_w;


	wire i2c_clk;
	wire [7:0] i2c_nbytes;
	wire [6:0] i2c_slave_addr;
	wire i2c_rw;
	wire [7:0] i2c_write_data;
	wire [7:0] i2c_read_data;
	wire i2c_tx_data_req;
	wire i2c_rx_data_ready;
	wire i2c_start;
	
	wire byte_ready;




	i2c_master uut2 (
		.clk(i2c_clk), 
		.reset(i2c_reset), 
		.start(i2c_start), 
		.nbytes_in(i2c_nbytes), 
		.addr_in(i2c_slave_addr), 
		.rw_in(i2c_rw), 
		.write_data(i2c_write_data), 
		.read_data(i2c_read_data), 
		.tx_data_req(i2c_tx_data_req), 
		.rx_data_ready(i2c_rx_data_ready), 
		.sda_w(sda_w), 
		.scl(scl)
	);


	clk_divider #(.DIVIDER(500)) i2c_clk_divider (
		.reset(reset), 
		.clk_in(clk), 
		.clk_out(i2c_clk)
	);
	
	read_eeprom uut (
    .clk(clk), 
    .reset(reset), 
    .slave_addr_w(slave_addr), 
    .mem_addr_w(mem_addr), 
    .read_nbytes_w(read_nbytes), 
    .start(start), 
    .i2c_slave_addr(i2c_slave_addr), 
    .i2c_rw(i2c_rw), 
    .i2c_write_data(i2c_write_data), 
    .i2c_nbytes(i2c_nbytes), 
    .i2c_read_data(i2c_read_data), 
    .i2c_tx_data_req(i2c_tx_data_req), 
    .i2c_rx_data_ready(i2c_rx_data_ready), 
    .i2c_start(i2c_start), 
    .data_out(data_out), 
    .byte_ready(byte_ready)
    );
	 
	
	initial begin

		clk = 0;
		forever begin 
			clk = #1 ~clk;
		end
	end

	initial begin

		reset = 1;
		i2c_reset = 1;


		#5000;

		reset = 0;
		#5000;
        

		i2c_reset = 0;
		slave_addr = 8'haa;
		mem_addr = 16'hF0F0;
		read_nbytes = 2;
		
		#10000;
		

		start = 1;
		
		
		#10000
		start = 0;
		#100000;
		
		
		$finish;
		
	end
      
endmodule