data/full_repos/permissive/496508301/Lesson4/counter/counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #20     res<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #6000   $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:38: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("conv_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:39: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module con(clk, res, y);
input        clk;
input        res;
output[7:0]  y;

reg[7:0]     y;
wire[7:0]    sum;

assign       sum=y+1;
always @(posedge clk or negedge res) begin
    if(~res) begin
        y<=0;
    end
    else begin
        y<=sum;
    end
end
endmodule
module con(clk, res, y);

input        clk;
input        res;
output[7:0]  y;

reg[7:0]     y;
wire[7:0]    sum;

assign       sum=y+1;
always @(posedge clk or negedge res) begin
    if(~res) begin
        y<=0;
    end
    else begin
        y<=sum;
    end
end
endmodule