data/full_repos/permissive/472097485/Chu03/BcdInc_03/BcdInc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BcdInc.v:10: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'d\' generates 1 bits.\n                                                                                : ... In instance BcdInc\n r = a + d;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BcdInc( input [3:0] a, input d, output reg [3:0] r, output reg c );

always @*
begin
	r = a + d;
	if( r == 4'b1010 )
		begin
		r = 4'b0000;
		c = 1'b1;
		end
	else
		c = 1'b0;
end

endmodule
module BcdInc( input [3:0] a, input d, output reg [3:0] r, output reg c );


always @*
begin
	r = a + d;
	if( r == 4'b1010 )
		begin
		r = 4'b0000;
		c = 1'b1;
		end
	else
		c = 1'b0;
end

endmodule