data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v:160: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                     : ... In instance FixedRing1.s_pad_7\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v:160: Operator COND expects 13 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 12 bits.\n                                                                                                                     : ... In instance FixedRing1.s_pad_9\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v:160: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 5 bits.\n                                                                                                                     : ... In instance FixedRing1.s_pad_14\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v:137: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                     : ... In instance FixedRing1.s_shr_1\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/reference/FixedRing1.lo.v:137: Operator COND expects 13 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                     : ... In instance FixedRing1.s_shr_16\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Error: Exiting due to 5 warning(s)\n'
module SHR_SIGNED(y, in);
    parameter width = 4;
    parameter n = 2;
    output [(n < width ? (width-n-1) : 0):0] y;
    input [width-1:0] in;
    assign y = n < width ? in[width-1:n] : in[width-1:width-1];
endmodule
module SHR_SIGNED(y, in);

    parameter width = 4;
    parameter n = 2;
    output [(n < width ? (width-n-1) : 0):0] y;
    input [width-1:0] in;
    assign y = n < width ? in[width-1:n] : in[width-1:width-1];
endmodule