data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v:176: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                               : ... In instance SmallOdds5.smalls.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v:176: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                               : ... In instance SmallOdds5.odds.u_pad_35\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module SmallOdds5Filter(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);
    wire _valid__q;
    wire _valid__d;
    DFF_POSCLK #(.width(1)) valid (
        .q(_valid__q),
        .d(_valid__d),
        .clk(clock)
    );
    wire [31:0] _result__q;
    wire [31:0] _result__d;
    DFF_POSCLK #(.width(32)) result (
        .q(_result__q),
        .d(_result__d),
        .clk(clock)
    );
    wire _T_17;
    wire [31:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(4), .n(32)) u_pad_1 (
        .y(_WTEMP_0),
        .in(4'hA)
    );
    LT_UNSIGNED #(.width(32)) u_lt_2 (
        .y(_T_17),
        .a(io_in_bits),
        .b(_WTEMP_0)
    );
    wire _T_18;
    BITWISEAND #(.width(1)) bitwiseand_3 (
        .y(_T_18),
        .a(io_in_valid),
        .b(_T_17)
    );
    wire _T_21;
    EQ_UNSIGNED #(.width(1)) u_eq_4 (
        .y(_T_21),
        .a(_T_18),
        .b(1'h0)
    );
    wire _node_0;
    MUX_UNSIGNED #(.width(1)) u_mux_5 (
        .y(_node_0),
        .sel(_T_18),
        .a(1'h1),
        .b(_valid__q)
    );
    wire _T_23;
    BITWISEAND #(.width(1)) bitwiseand_6 (
        .y(_T_23),
        .a(io_out_ready),
        .b(_valid__q)
    );
    assign io_in_ready = io_out_ready;
    assign io_out_bits = _result__q;
    assign io_out_valid = _T_23;
    MUX_UNSIGNED #(.width(32)) u_mux_7 (
        .y(_result__d),
        .sel(_T_18),
        .a(io_in_bits),
        .b(_result__q)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_8 (
        .y(_valid__d),
        .sel(_T_21),
        .a(1'h0),
        .b(_node_0)
    );
endmodule
module SmallOdds5Filter(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);

    wire _valid__q;
    wire _valid__d;
    DFF_POSCLK #(.width(1)) valid (
        .q(_valid__q),
        .d(_valid__d),
        .clk(clock)
    );
    wire [31:0] _result__q;
    wire [31:0] _result__d;
    DFF_POSCLK #(.width(32)) result (
        .q(_result__q),
        .d(_result__d),
        .clk(clock)
    );
    wire _T_17;
    wire [31:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(4), .n(32)) u_pad_1 (
        .y(_WTEMP_0),
        .in(4'hA)
    );
    LT_UNSIGNED #(.width(32)) u_lt_2 (
        .y(_T_17),
        .a(io_in_bits),
        .b(_WTEMP_0)
    );
    wire _T_18;
    BITWISEAND #(.width(1)) bitwiseand_3 (
        .y(_T_18),
        .a(io_in_valid),
        .b(_T_17)
    );
    wire _T_21;
    EQ_UNSIGNED #(.width(1)) u_eq_4 (
        .y(_T_21),
        .a(_T_18),
        .b(1'h0)
    );
    wire _node_0;
    MUX_UNSIGNED #(.width(1)) u_mux_5 (
        .y(_node_0),
        .sel(_T_18),
        .a(1'h1),
        .b(_valid__q)
    );
    wire _T_23;
    BITWISEAND #(.width(1)) bitwiseand_6 (
        .y(_T_23),
        .a(io_out_ready),
        .b(_valid__q)
    );
    assign io_in_ready = io_out_ready;
    assign io_out_bits = _result__q;
    assign io_out_valid = _T_23;
    MUX_UNSIGNED #(.width(32)) u_mux_7 (
        .y(_result__d),
        .sel(_T_18),
        .a(io_in_bits),
        .b(_result__q)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_8 (
        .y(_valid__d),
        .sel(_T_21),
        .a(1'h0),
        .b(_node_0)
    );
endmodule