data/full_repos/permissive/487039227/build/tb_delayer.v
1: b'%Error: data/full_repos/permissive/487039227/build/tb_delayer.v:17: Cannot find include file: ./src/delayer.v\n`include "./src/delayer.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487039227/build,data/full_repos/permissive/487039227/./src/delayer.v\n             data/full_repos/permissive/487039227/build,data/full_repos/permissive/487039227/./src/delayer.v.v\n             data/full_repos/permissive/487039227/build,data/full_repos/permissive/487039227/./src/delayer.v.sv\n             ./src/delayer.v\n             ./src/delayer.v.v\n             ./src/delayer.v.sv\n             obj_dir/./src/delayer.v\n             obj_dir/./src/delayer.v.v\n             obj_dir/./src/delayer.v.sv\n%Error: data/full_repos/permissive/487039227/build/tb_delayer.v:26: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/487039227/build/tb_delayer.v:27: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_delayer);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #20 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #6000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/487039227/build/tb_delayer.v:51: Unsupported: Ignoring delay on this delayed statement.\n    always #20 clk = !clk;\n           ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module tb_delayer;
    reg         clk;
    reg         rstn;
    reg         stall;
    reg [31:0]  in;
    wire [31:0] out;
    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb_delayer);
        
        clk = 'b0;
        rstn = 'b1;
        stall = 'b0;
        in = 'd1;
        
        #20 
        rstn = 'b0;
        stall = 'b0;

        #20
        rstn = 'b1;
        stall = 'b0;

        #100
        stall = 'b1;

        #100
        stall = 'b0;

        #6000 $finish;
    end

    always #20 clk = !clk;

    always@(posedge clk)begin
        in <= in + 'd1;
    end

    delayer
    #(.WIDTH(32),
      .DELAY(5))
      mydelayer(
        .clk(clk),
        .rstn(rstn),
        .stall(stall),
        .in(in),
        .out(out)
    );

endmodule
module tb_delayer;

    reg         clk;
    reg         rstn;
    reg         stall;
    reg [31:0]  in;
    wire [31:0] out;
    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb_delayer);
        
        clk = 'b0;
        rstn = 'b1;
        stall = 'b0;
        in = 'd1;
        
        #20 
        rstn = 'b0;
        stall = 'b0;

        #20
        rstn = 'b1;
        stall = 'b0;

        #100
        stall = 'b1;

        #100
        stall = 'b0;

        #6000 $finish;
    end

    always #20 clk = !clk;

    always@(posedge clk)begin
        in <= in + 'd1;
    end

    delayer
    #(.WIDTH(32),
      .DELAY(5))
      mydelayer(
        .clk(clk),
        .rstn(rstn),
        .stall(stall),
        .in(in),
        .out(out)
    );

endmodule