data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/SyncSpRam.sv
data/verilator_xmls/4ada2797-a6d8-4cf0-abda-594018849e3f.xml
module SyncSpRam
#(
  parameter ADDR_WIDTH = 10,
  parameter DATA_DEPTH = 1024,
  parameter DATA_WIDTH = 32,
  parameter OUT_REGS   = 0,
  parameter SIM_INIT   = 0


)(
  input  logic                    Clk_CI,
  input  logic                    Rst_RBI,
  input  logic                    CSel_SI,
  input  logic                    WrEn_SI,
  input  logic [ADDR_WIDTH-1:0]   Addr_DI,
  input  logic [DATA_WIDTH-1:0]   WrData_DI,
  output logic [DATA_WIDTH-1:0]   RdData_DO
);





  logic [DATA_WIDTH-1:0] RdData_DN;
  logic [DATA_WIDTH-1:0] RdData_DP;
  logic [DATA_WIDTH-1:0] Mem_DP [DATA_DEPTH-1:0];





  always_ff @(posedge Clk_CI)
  begin

    automatic logic [DATA_WIDTH-1:0] val;
    if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
      for(int k=0; k<DATA_DEPTH;k++) begin
        if(SIM_INIT==1) val = '0;
        `ifndef VERILATOR
        else if(SIM_INIT==2) void'(randomize(val));
        `endif
        Mem_DP[k] = val;
      end
    end else

    if (CSel_SI) begin
      if (WrEn_SI) begin
        Mem_DP[Addr_DI] <= WrData_DI;
      end
      else
      begin
        RdData_DN <= Mem_DP[Addr_DI];
      end
    end
  end






  generate
    if (OUT_REGS>0) begin : g_outreg
      always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
        if(Rst_RBI == 1'b0)
        begin
          RdData_DP  <= 0;
        end
        else
        begin
          RdData_DP  <= RdData_DN;
        end
      end
    end
  endgenerate


  generate
    if (OUT_REGS==0) begin : g_oureg_byp
      assign RdData_DP  = RdData_DN;
    end
  endgenerate

  assign RdData_DO = RdData_DP;






  assert property
    (@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
    else $error("depth out of bounds");


endmodule
module SyncSpRam
#(
  parameter ADDR_WIDTH = 10,
  parameter DATA_DEPTH = 1024,
  parameter DATA_WIDTH = 32,
  parameter OUT_REGS   = 0,
  parameter SIM_INIT   = 0


)(
  input  logic                    Clk_CI,
  input  logic                    Rst_RBI,
  input  logic                    CSel_SI,
  input  logic                    WrEn_SI,
  input  logic [ADDR_WIDTH-1:0]   Addr_DI,
  input  logic [DATA_WIDTH-1:0]   WrData_DI,
  output logic [DATA_WIDTH-1:0]   RdData_DO
);






  logic [DATA_WIDTH-1:0] RdData_DN;
  logic [DATA_WIDTH-1:0] RdData_DP;
  logic [DATA_WIDTH-1:0] Mem_DP [DATA_DEPTH-1:0];





  always_ff @(posedge Clk_CI)
  begin

    automatic logic [DATA_WIDTH-1:0] val;
    if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
      for(int k=0; k<DATA_DEPTH;k++) begin
        if(SIM_INIT==1) val = '0;
        `ifndef VERILATOR
        else if(SIM_INIT==2) void'(randomize(val));
        `endif
        Mem_DP[k] = val;
      end
    end else

    if (CSel_SI) begin
      if (WrEn_SI) begin
        Mem_DP[Addr_DI] <= WrData_DI;
      end
      else
      begin
        RdData_DN <= Mem_DP[Addr_DI];
      end
    end
  end






  generate
    if (OUT_REGS>0) begin : g_outreg
      always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
        if(Rst_RBI == 1'b0)
        begin
          RdData_DP  <= 0;
        end
        else
        begin
          RdData_DP  <= RdData_DN;
        end
      end
    end
  endgenerate


  generate
    if (OUT_REGS==0) begin : g_oureg_byp
      assign RdData_DP  = RdData_DN;
    end
  endgenerate

  assign RdData_DO = RdData_DP;






  assert property
    (@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
    else $error("depth out of bounds");


endmodule