data/full_repos/permissive/523744529/Verilog/MUL.v
1: b"%Error: data/full_repos/permissive/523744529/Verilog/MUL.v:6: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module MUL (

	input  wire [7:0] IN1,
	input  wire [7:0] IN2,
	output wire [7:0] OUTPUT,
);
	assign OUTPUT = IN1 * IN2;
endmodule
module MUL (

	input  wire [7:0] IN1,
	input  wire [7:0] IN2,
	output wire [7:0] OUTPUT,
);

	assign OUTPUT = IN1 * IN2;
endmodule