data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: Define or directive not defined: \'`BIN_SIZE\'\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                                   ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: Define or directive not defined: \'`SERIAL_WCNT\'\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                             ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:88: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: Define or directive not defined: \'`SERIAL_WCNT\'\n    assign waitcnt = `SERIAL_WCNT;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign waitcnt = `SERIAL_WCNT;\n                                 ^\n%Error: Exiting due to 8 error(s)\n'
module serialc(CLK, RST_X, rxd, DATA, EN);
    input  wire   CLK, RST_X, rxd;
    output [7:0]  DATA;
    output reg    EN;

    reg    [7:0]   DATA;
    reg    [3:0]   stage;
    reg    [12:0]  cnt;
    reg    [11:0]  cnt_start;
    wire   [12:0]  waitcnt;

    assign waitcnt = `SERIAL_WCNT;

    always @(posedge CLK) begin
        if (!RST_X) cnt_start <= 0;
        else        cnt_start <= (RXD) ? 0 : cnt_start + 1;
    end

    reg RXD=0, s0=0, s1=0;

    always @(posedge CLK) begin
        s0 <= rxd;
        s1 <= s0;
        RXD <= s1;
    end


    always @(posedge CLK) begin
        if(!RST_X) begin
            EN     <= 0;
            stage  <= `SS_SER_WAIT;
            cnt    <= 1;
            DATA   <= 0;
        end else if (stage == `SS_SER_WAIT) begin
            EN <= 0;
            stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
        end else begin
            if (cnt != waitcnt) begin
                cnt <= cnt + 1;
                EN <= 0;
            end else begin
                stage  <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
                EN     <= (stage == 8)  ? 1 : 0;
                DATA   <= {RXD, DATA[7:1]};
                cnt <= 1;
            end
        end
    end

    (* mark_debug *) reg EN_d;
    (* mark_debug *) reg [7:0] DATA_d;
    always @(posedge CLK) begin
	EN_d <= EN;
	if(EN) begin
	    DATA_d <= DATA;
	end
    end

endmodule
module serialc(CLK, RST_X, rxd, DATA, EN);

    input  wire   CLK, RST_X, rxd;
    output [7:0]  DATA;
    output reg    EN;

    reg    [7:0]   DATA;
    reg    [3:0]   stage;
    reg    [12:0]  cnt;
    reg    [11:0]  cnt_start;
    wire   [12:0]  waitcnt;

    assign waitcnt = `SERIAL_WCNT;

    always @(posedge CLK) begin
        if (!RST_X) cnt_start <= 0;
        else        cnt_start <= (RXD) ? 0 : cnt_start + 1;
    end

    reg RXD=0, s0=0, s1=0;

    always @(posedge CLK) begin
        s0 <= rxd;
        s1 <= s0;
        RXD <= s1;
    end


    always @(posedge CLK) begin
        if(!RST_X) begin
            EN     <= 0;
            stage  <= `SS_SER_WAIT;
            cnt    <= 1;
            DATA   <= 0;
        end else if (stage == `SS_SER_WAIT) begin
            EN <= 0;
            stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
        end else begin
            if (cnt != waitcnt) begin
                cnt <= cnt + 1;
                EN <= 0;
            end else begin
                stage  <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
                EN     <= (stage == 8)  ? 1 : 0;
                DATA   <= {RXD, DATA[7:1]};
                cnt <= 1;
            end
        end
    end

    (* mark_debug *) reg EN_d;
    (* mark_debug *) reg [7:0] DATA_d;
    always @(posedge CLK) begin
	EN_d <= EN;
	if(EN) begin
	    DATA_d <= DATA;
	end
    end

endmodule