data/full_repos/permissive/437157208/src/Data_Path.v
1: b"%Error: data/full_repos/permissive/437157208/src/Data_Path.v:55: Cannot find file containing module: 'Program_counter'\nProgram_counter  PC(.D(PC_source_o), .clk(clk), .reset(reset), .enable(enable_PC), .Q(PC_o));\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Program_counter\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Program_counter.v\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Program_counter.sv\n             Program_counter\n             Program_counter.v\n             Program_counter.sv\n             obj_dir/Program_counter\n             obj_dir/Program_counter.v\n             obj_dir/Program_counter.sv\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:58: Cannot find file containing module: 'MUX2_1'\nMUX2_1  Address_MUX(.data_1(ALU_o), .data_2(PC_o), .selector(Selector_Addr), .data_o(Mux1_o));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:61: Cannot find file containing module: 'Memory_system'\nMemory_system Memories(.write_enable_i(enable_MemSys), .clock(clk), .Write_Data(Reg_B_o), .Address_i(Mux1_o), .Instruction_o(Mem_o)); \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:64: Cannot find file containing module: 'Register'\nRegister  Inst_Reg(.Rd(Mem_o), .clk(clk), .reset(reset), .enable(enable_RegIns), .Q1(Ins_Reg_o));\n^~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:67: Cannot find file containing module: 'Register_W_en'\nRegister_W_en  Data(.D(Mem_o), .clk(clk), .reset(reset), .Q(Data_Reg_o));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:70: Cannot find file containing module: 'Register_File'\nRegister_File RF(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:83: Cannot find file containing module: 'MUX2_1'\nMUX2_1 #(.WIDTH(5)) MUX_IR(.data_1(Ins_Reg_o[15:11]), .data_2(Ins_Reg_o[20:16]), .selector(Selector_RF_WR), .data_o(Mux2_o));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:86: Cannot find file containing module: 'MUX2_1'\nMUX2_1  MUX_DATA(.data_1(Data_Reg_o), .data_2(Reg_ALU_o), .selector(Selector_RF_WD), .data_o(Mux_RF_WD));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:89: Cannot find file containing module: 'Register_W_en'\nRegister_W_en  Read_Data_A(.D(Data1_o), .clk(clk), .reset(reset), .Q(Reg_A_o));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:90: Cannot find file containing module: 'Register_W_en'\nRegister_W_en  Read_Data_B(.D(Data2_o), .clk(clk), .reset(reset), .Q(Reg_B_o));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:93: Cannot find file containing module: 'MUX2_1'\nMUX2_1  Source_A(.data_1(Reg_A_o), .data_2(PC_o), .selector(Selector_ALU_Src_A), .data_o(Src_A));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:96: Cannot find file containing module: 'MUX4_1'\nMUX4_1  Source_B(.data_1(Reg_B_o), .data_2(Mux_SZ_Ext_o), .dato_3({ Mux_SZ_Ext_o[29:0], 2'b0}), .selector(Selector_ALU_Src_B), .data_o(Src_B));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:99: Cannot find file containing module: 'ALU'\nALU  Alu_mod(.data_a(Src_A), .data_b(Src_B), .select(Selector_ALU_Op), .y(ALU_o), .zero(Zero));\n^~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:102: Cannot find file containing module: 'Register_W_en'\nRegister_W_en  Read_ALU_Output(.D(ALU_o), .clk(clk), .reset(reset), .Q(Reg_ALU_o));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:105: Cannot find file containing module: 'MUX2_1'\nMUX2_1  PC_Source(.data_1(Reg_ALU_o), .data_2(ALU_o), .selector(Selector_PC_Source), .data_o(PC_ALU));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:108: Cannot find file containing module: 'MUX2_1'\nMUX2_1  PC_J(.data_1(PC_ALU), .data_2({ PC_o[31:28], Ins_Reg_o[25:0], {2{1'b0}} }), .selector(Selector_Jump), .data_o(PC_source_o));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:111: Cannot find file containing module: 'Sign_Extend'\nSign_Extend  SE(.Sign_Ext_i(Ins_Reg_o[15:0]), .Sign_Ext_o(Sign_Extend_o));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:114: Cannot find file containing module: 'Zero_extend'\nZero_extend   ZE_EXT(.GPIO_i(GPIO_i), .Zero_Ext(Zero_Extend_o));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:117: Cannot find file containing module: 'MUX2_1'\nMUX2_1  GPIO_SIGN(.data_1(Zero_Extend_o), .data_2(Sign_Extend_o), .selector(Selector_Zero), .data_o(Mux_SZ_Ext_o));\n^~~~~~\n%Error: data/full_repos/permissive/437157208/src/Data_Path.v:120: Cannot find file containing module: 'ControlUnit2'\nControlUnit2 FSM( \n^~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n"
module Data_Path
(

	input clk,
	input reset,
	input [7:0] GPIO_i,

	output [7:0] GPIO_o,
	output clk_signal
);

wire [31:0]	PC_o, 
				Mux1_o, 
				Mem_o, 
				Ins_Reg_o,
				Data_Reg_o,
				Mux_RF_WD,
				Data1_o, 
				Data2_o,
				Reg_A_o,
				Reg_B_o,
				Src_A,
				Src_B,
				ALU_o,
				Reg_ALU_o,
				PC_source_o,
				PC_ALU,
				Jump_o,
				Sign_Extend_o,
				Zero_Extend_o,
				Mux_SZ_Ext_o;
				
wire [4:0]	Mux2_o;

wire		enable_PC, 
		Selector_Addr, 
		enable_MemSys, 
		enable_RegIns, 
		Branch,
		enable_RF, 
		Selector_RF_WR, 
		Selector_ALU_Src_A, 
		Selector_PC_Source,
		Selector_RF_WD, 
		PC_Write,
		AND_o,
		Selector_Jump,
		Zero,
		Selector_Zero;
		
wire [1:0] Selector_ALU_Src_B;
wire [2:0] Selector_ALU_Op;


Program_counter 	PC(.D(PC_source_o), .clk(clk), .reset(reset), .enable(enable_PC), .Q(PC_o));


MUX2_1		Address_MUX(.data_1(ALU_o), .data_2(PC_o), .selector(Selector_Addr), .data_o(Mux1_o));


Memory_system	Memories(.write_enable_i(enable_MemSys), .clock(clk), .Write_Data(Reg_B_o), .Address_i(Mux1_o), .Instruction_o(Mem_o)); 


Register 	Inst_Reg(.Rd(Mem_o), .clk(clk), .reset(reset), .enable(enable_RegIns), .Q1(Ins_Reg_o));


Register_W_en 	Data(.D(Mem_o), .clk(clk), .reset(reset), .Q(Data_Reg_o));


Register_File	RF(
	.clk(clk),
	.reset(reset),
	.Reg_Write_i(enable_RF), 	
	.Read_Register_1_i(Ins_Reg_o[25:21]),
	.Read_Register_2_i(Ins_Reg_o[20:16]),
	.Write_Register_i(Mux2_o),
	.Write_Data_i(Mux_RF_WD),
	.Read_Data_1_i(Data1_o),
	.Read_Data_2_i(Data2_o)
);


MUX2_1	#(.WIDTH(5))	MUX_IR(.data_1(Ins_Reg_o[15:11]), .data_2(Ins_Reg_o[20:16]), .selector(Selector_RF_WR), .data_o(Mux2_o));


MUX2_1		MUX_DATA(.data_1(Data_Reg_o), .data_2(Reg_ALU_o), .selector(Selector_RF_WD), .data_o(Mux_RF_WD));


Register_W_en 	Read_Data_A(.D(Data1_o), .clk(clk), .reset(reset), .Q(Reg_A_o));
Register_W_en 	Read_Data_B(.D(Data2_o), .clk(clk), .reset(reset), .Q(Reg_B_o));


MUX2_1		Source_A(.data_1(Reg_A_o), .data_2(PC_o), .selector(Selector_ALU_Src_A), .data_o(Src_A));


MUX4_1		Source_B(.data_1(Reg_B_o), .data_2(Mux_SZ_Ext_o), .dato_3({ Mux_SZ_Ext_o[29:0], 2'b0}), .selector(Selector_ALU_Src_B), .data_o(Src_B));


ALU		Alu_mod(.data_a(Src_A), .data_b(Src_B), .select(Selector_ALU_Op), .y(ALU_o), .zero(Zero));


Register_W_en 	Read_ALU_Output(.D(ALU_o), .clk(clk), .reset(reset), .Q(Reg_ALU_o));


MUX2_1		PC_Source(.data_1(Reg_ALU_o), .data_2(ALU_o), .selector(Selector_PC_Source), .data_o(PC_ALU));


MUX2_1		PC_J(.data_1(PC_ALU), .data_2({ PC_o[31:28], Ins_Reg_o[25:0], {2{1'b0}} }), .selector(Selector_Jump), .data_o(PC_source_o));


Sign_Extend		SE(.Sign_Ext_i(Ins_Reg_o[15:0]), .Sign_Ext_o(Sign_Extend_o));


Zero_extend 		ZE_EXT(.GPIO_i(GPIO_i), .Zero_Ext(Zero_Extend_o));


MUX2_1		GPIO_SIGN(.data_1(Zero_Extend_o), .data_2(Sign_Extend_o), .selector(Selector_Zero), .data_o(Mux_SZ_Ext_o));


ControlUnit2 FSM( 
					.clk(clk), 
					.rst(reset),
					.Op(Ins_Reg_o[31:26]), 
					.Funct(Ins_Reg_o[5:0]),
					.IorD(Selector_Addr),
					.Mem_Write(enable_MemSys),
					.IR_Write(enable_RegIns),
					.PC_Write(PC_Write),
					.PC_Src(Selector_PC_Source),
					.Branch(Branch),
					.ALU_SrcA(Selector_ALU_Src_A),
					.Reg_Write(enable_RF),
					.Mem_Reg(Selector_RF_WD),
					.Reg_Dst(Selector_RF_WR),
					.PC_J(Selector_Jump),
					.ALU_Control(Selector_ALU_Op),
					.ALU_SrcB(Selector_ALU_Src_B),
					.Zero_Ext(Selector_Zero)
);

and Comp1 (AND_o, Branch, Zero);
or Comp2 (enable_PC, PC_Write, AND_o);




assign GPIO_o = ALU_o[7:0];
endmodule
module Data_Path
(

	input clk,
	input reset,
	input [7:0] GPIO_i,

	output [7:0] GPIO_o,
	output clk_signal
);


wire [31:0]	PC_o, 
				Mux1_o, 
				Mem_o, 
				Ins_Reg_o,
				Data_Reg_o,
				Mux_RF_WD,
				Data1_o, 
				Data2_o,
				Reg_A_o,
				Reg_B_o,
				Src_A,
				Src_B,
				ALU_o,
				Reg_ALU_o,
				PC_source_o,
				PC_ALU,
				Jump_o,
				Sign_Extend_o,
				Zero_Extend_o,
				Mux_SZ_Ext_o;
				
wire [4:0]	Mux2_o;

wire		enable_PC, 
		Selector_Addr, 
		enable_MemSys, 
		enable_RegIns, 
		Branch,
		enable_RF, 
		Selector_RF_WR, 
		Selector_ALU_Src_A, 
		Selector_PC_Source,
		Selector_RF_WD, 
		PC_Write,
		AND_o,
		Selector_Jump,
		Zero,
		Selector_Zero;
		
wire [1:0] Selector_ALU_Src_B;
wire [2:0] Selector_ALU_Op;


Program_counter 	PC(.D(PC_source_o), .clk(clk), .reset(reset), .enable(enable_PC), .Q(PC_o));


MUX2_1		Address_MUX(.data_1(ALU_o), .data_2(PC_o), .selector(Selector_Addr), .data_o(Mux1_o));


Memory_system	Memories(.write_enable_i(enable_MemSys), .clock(clk), .Write_Data(Reg_B_o), .Address_i(Mux1_o), .Instruction_o(Mem_o)); 


Register 	Inst_Reg(.Rd(Mem_o), .clk(clk), .reset(reset), .enable(enable_RegIns), .Q1(Ins_Reg_o));


Register_W_en 	Data(.D(Mem_o), .clk(clk), .reset(reset), .Q(Data_Reg_o));


Register_File	RF(
	.clk(clk),
	.reset(reset),
	.Reg_Write_i(enable_RF), 	
	.Read_Register_1_i(Ins_Reg_o[25:21]),
	.Read_Register_2_i(Ins_Reg_o[20:16]),
	.Write_Register_i(Mux2_o),
	.Write_Data_i(Mux_RF_WD),
	.Read_Data_1_i(Data1_o),
	.Read_Data_2_i(Data2_o)
);


MUX2_1	#(.WIDTH(5))	MUX_IR(.data_1(Ins_Reg_o[15:11]), .data_2(Ins_Reg_o[20:16]), .selector(Selector_RF_WR), .data_o(Mux2_o));


MUX2_1		MUX_DATA(.data_1(Data_Reg_o), .data_2(Reg_ALU_o), .selector(Selector_RF_WD), .data_o(Mux_RF_WD));


Register_W_en 	Read_Data_A(.D(Data1_o), .clk(clk), .reset(reset), .Q(Reg_A_o));
Register_W_en 	Read_Data_B(.D(Data2_o), .clk(clk), .reset(reset), .Q(Reg_B_o));


MUX2_1		Source_A(.data_1(Reg_A_o), .data_2(PC_o), .selector(Selector_ALU_Src_A), .data_o(Src_A));


MUX4_1		Source_B(.data_1(Reg_B_o), .data_2(Mux_SZ_Ext_o), .dato_3({ Mux_SZ_Ext_o[29:0], 2'b0}), .selector(Selector_ALU_Src_B), .data_o(Src_B));


ALU		Alu_mod(.data_a(Src_A), .data_b(Src_B), .select(Selector_ALU_Op), .y(ALU_o), .zero(Zero));


Register_W_en 	Read_ALU_Output(.D(ALU_o), .clk(clk), .reset(reset), .Q(Reg_ALU_o));


MUX2_1		PC_Source(.data_1(Reg_ALU_o), .data_2(ALU_o), .selector(Selector_PC_Source), .data_o(PC_ALU));


MUX2_1		PC_J(.data_1(PC_ALU), .data_2({ PC_o[31:28], Ins_Reg_o[25:0], {2{1'b0}} }), .selector(Selector_Jump), .data_o(PC_source_o));


Sign_Extend		SE(.Sign_Ext_i(Ins_Reg_o[15:0]), .Sign_Ext_o(Sign_Extend_o));


Zero_extend 		ZE_EXT(.GPIO_i(GPIO_i), .Zero_Ext(Zero_Extend_o));


MUX2_1		GPIO_SIGN(.data_1(Zero_Extend_o), .data_2(Sign_Extend_o), .selector(Selector_Zero), .data_o(Mux_SZ_Ext_o));


ControlUnit2 FSM( 
					.clk(clk), 
					.rst(reset),
					.Op(Ins_Reg_o[31:26]), 
					.Funct(Ins_Reg_o[5:0]),
					.IorD(Selector_Addr),
					.Mem_Write(enable_MemSys),
					.IR_Write(enable_RegIns),
					.PC_Write(PC_Write),
					.PC_Src(Selector_PC_Source),
					.Branch(Branch),
					.ALU_SrcA(Selector_ALU_Src_A),
					.Reg_Write(enable_RF),
					.Mem_Reg(Selector_RF_WD),
					.Reg_Dst(Selector_RF_WR),
					.PC_J(Selector_Jump),
					.ALU_Control(Selector_ALU_Op),
					.ALU_SrcB(Selector_ALU_Src_B),
					.Zero_Ext(Selector_Zero)
);

and Comp1 (AND_o, Branch, Zero);
or Comp2 (enable_PC, PC_Write, AND_o);




assign GPIO_o = ALU_o[7:0];
endmodule