data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v
1: b'%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter AXI_ID_WIDTH   = 4,\n    ^\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:5: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_ADDR_WIDTH  = 32,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_DATA_WIDTH  = 128\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:7: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 [31:0] mem_axi4_error_o,     \n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mem_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mem_req_i,           \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire   [AXI_ADDR_WIDTH-1:0] mem_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [AXI_DATA_WIDTH/8-1:0] mem_wben_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire   [AXI_DATA_WIDTH-1:0] mem_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire   [AXI_DATA_WIDTH-1:0] mem_rdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mem_rdata_avail_o,   \n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mem_wdata_infifo_o,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mem_wabort_i,        \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mem_wstall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mem_rstall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mem_access_i,        \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire                        axi4_aw_ready_i,\n ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                         axi4_aw_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire     [AXI_ID_WIDTH-1:0] axi4_aw_id_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg    [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                   [7:0] axi4_aw_len_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire                  [2:0] axi4_aw_size_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                  [1:0] axi4_aw_burst_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        axi4_w_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                         axi4_w_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg    [AXI_DATA_WIDTH-1:0] axi4_w_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                         axi4_w_last_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire                        axi4_b_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        axi4_b_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [AXI_ID_WIDTH-1:0] axi4_b_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                  [1:0] axi4_b_resp_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:45: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        axi4_ar_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                         axi4_ar_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:47: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire     [AXI_ID_WIDTH-1:0] axi4_ar_id_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:48: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg    [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:49: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                   [7:0] axi4_ar_len_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:50: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire                  [2:0] axi4_ar_size_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:51: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                  [1:0] axi4_ar_burst_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:52: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        axi4_r_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:53: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        axi4_r_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [AXI_ID_WIDTH-1:0] axi4_r_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire   [AXI_DATA_WIDTH-1:0] axi4_r_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:56: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                  [1:0] axi4_r_resp_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        axi4_r_last_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/mem_axi4_bridge.v:191: syntax error, unexpected IDENTIFIER\n    util_reset_sync i_reset_sync_axi4_bridge (\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 49 error(s)\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem_axi4_bridge #(
    `include "noc_parameter.vh"
    ,parameter AXI_ID_WIDTH   = 4,
    parameter AXI_ADDR_WIDTH  = 32,
    parameter AXI_DATA_WIDTH  = 128
)
(
    input  wire                        clk_i,
    input  wire                        reset_n_i,

    output wire                 [31:0] mem_axi4_error_o,


    input  wire                        mem_en_i,
    input  wire                        mem_req_i,
    input  wire   [AXI_ADDR_WIDTH-1:0] mem_addr_i,
    input  wire [AXI_DATA_WIDTH/8-1:0] mem_wben_i,
    input  wire   [AXI_DATA_WIDTH-1:0] mem_wdata_i,
    output wire   [AXI_DATA_WIDTH-1:0] mem_rdata_o,
    output wire                        mem_rdata_avail_o,
    output wire                        mem_wdata_infifo_o,
    input  wire                        mem_wabort_i,
    output wire                        mem_wstall_o,
    output wire                        mem_rstall_o,
    input  wire                        mem_access_i,


	input  wire                        axi4_aw_ready_i,
    output reg                         axi4_aw_valid_o,
    output wire     [AXI_ID_WIDTH-1:0] axi4_aw_id_o,
    output reg    [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_o,
    output reg                   [7:0] axi4_aw_len_o,
    output wire                  [2:0] axi4_aw_size_o,
    output wire                  [1:0] axi4_aw_burst_o,
    input  wire                        axi4_w_ready_i,
    output reg                         axi4_w_valid_o,
    output reg    [AXI_DATA_WIDTH-1:0] axi4_w_data_o,
    output reg  [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_o,
    output reg                         axi4_w_last_o,
    output wire                        axi4_b_ready_o,
    input  wire                        axi4_b_valid_i,
    input  wire     [AXI_ID_WIDTH-1:0] axi4_b_id_i,
    input  wire                  [1:0] axi4_b_resp_i,
    input  wire                        axi4_ar_ready_i,
    output reg                         axi4_ar_valid_o,
    output wire     [AXI_ID_WIDTH-1:0] axi4_ar_id_o,
    output reg    [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_o,
    output reg                   [7:0] axi4_ar_len_o,
    output wire                  [2:0] axi4_ar_size_o,
    output wire                  [1:0] axi4_ar_burst_o,
    output wire                        axi4_r_ready_o,
    input  wire                        axi4_r_valid_i,
    input  wire     [AXI_ID_WIDTH-1:0] axi4_r_id_i,
    input  wire   [AXI_DATA_WIDTH-1:0] axi4_r_data_i,
    input  wire                  [1:0] axi4_r_resp_i,
    input  wire                        axi4_r_last_i
);

    localparam AUXMEM_ADDR_WIDTH = 9;

    localparam NUM_STATES_WFIFO    = 3;
    localparam S_WFIFO_IDLE        = 3'h0;
    localparam S_WFIFO_WRITE_WAIT  = 3'h1;
    localparam S_WFIFO_WRITE_BURST = 3'h2;
    localparam S_WFIFO_WAIT_BRESP  = 3'h3;
    localparam S_WFIFO_ABORT       = 3'h4;
    localparam S_WFIFO_ERROR       = 3'h5;
    localparam S_WFIFO_FINISH      = 3'h7;

    localparam NUM_STATES_RFIFO   = 3;
    localparam S_RFIFO_IDLE       = 3'h0;
    localparam S_RFIFO_REQNREAD   = 3'h1;
    localparam S_RFIFO_WAIT_FETCH = 3'h2;
    localparam S_RFIFO_WAITLAST   = 3'h3;
    localparam S_RFIFO_ERROR      = 3'h4;
    localparam S_RFIFO_FINISH     = 3'h7;

    localparam AXI_BURST_TYPE_FIXED = 2'h0;
    localparam AXI_BURST_TYPE_INCR  = 2'h1;
    localparam AXI_BURST_TYPE_WRAP  = 2'h2;

    localparam AXI_RESP_TYPE_OKAY   = 2'h0;
    localparam AXI_RESP_TYPE_EXOKAY = 2'h1;
    localparam AXI_RESP_TYPE_SLVERR = 2'h2;
    localparam AXI_RESP_TYPE_DECERR = 2'h3;


    localparam DATA_BYTES = AXI_DATA_WIDTH/8;
    localparam LOG_DATA_BYTES = $clog2(DATA_BYTES);

    localparam [AUXMEM_ADDR_WIDTH-1:0] RD_WR_THRESHOLD = 5;


    reg [NUM_STATES_WFIFO-1:0] state_wfifo, next_state_wfifo;
    reg [NUM_STATES_RFIFO-1:0] state_rfifo, next_state_rfifo;



    reg [AUXMEM_ADDR_WIDTH-1:0] r_auxmem_waddr, rin_auxmem_waddr;
    reg	[AUXMEM_ADDR_WIDTH-1:0] r_auxmem_raddr, rin_auxmem_raddr;
    reg                         rin_auxmem_ren;
    reg                  [15:0] r_auxmem_wloops, rin_auxmem_wloops;
    reg                  [15:0] r_auxmem_rloops, rin_auxmem_rloops;

    reg req_wfifo_pop;
    reg r_req_rfifo_pop, rin_req_rfifo_pop;

    reg r_read_stall;


    reg [31:0] r_error, rin_error;


    reg r_wabort, rin_wabort;

    reg   [AXI_ADDR_WIDTH-1:0] r_write_addr, rin_write_addr;
    reg  [31-LOG_DATA_BYTES:0] r_write_count, rin_write_count;
    reg                  [8:0] r_tmp_write_count, rin_tmp_write_count;

    reg [AXI_DATA_WIDTH/8-1:0] r_tmp_wben, rin_tmp_wben;
    reg   [AXI_DATA_WIDTH-1:0] r_tmp_wdata, rin_tmp_wdata;

    reg   [AXI_ADDR_WIDTH-1:0] r_ar_addr, rin_ar_addr;
    reg  [31-LOG_DATA_BYTES:0] r_req_count, rin_req_count;

    wire reset_sync_n;

    wire [AXI_DATA_WIDTH/8-1:0] mem_wben_wout;
    wire   [AXI_ADDR_WIDTH-1:0] mem_addr_wout;
    wire   [AXI_DATA_WIDTH-1:0] mem_wdata_wout;
    wire                        mem_wreq_wout;
    wire   [AXI_ADDR_WIDTH-1:0] mem_addr_rout;
    wire   [AXI_DATA_WIDTH-1:0] mem_wdata_rout;

    wire req_wfifo_empty, req_wfifo_full;
    wire req_rfifo_empty, req_rfifo_full;






    wire    [LOG_DATA_BYTES:0] extra_req_count = mem_wdata_rout[LOG_DATA_BYTES-1:0] + mem_addr_rout[LOG_DATA_BYTES-1:0];
    wire [31-LOG_DATA_BYTES:0] req_count = req_rfifo_empty ? {(32-LOG_DATA_BYTES){1'b0}} :
                                                mem_wdata_rout[31:LOG_DATA_BYTES] +
                                                ((extra_req_count != 'h0) ? 1 : 0) +
                                                ((extra_req_count > DATA_BYTES) ? 1 : 0);


    wire req_count_overflow = (req_count > 'd256);


    wire [31-LOG_DATA_BYTES:0] tmp_req_count = rin_auxmem_waddr + {rin_auxmem_wloops, {AUXMEM_ADDR_WIDTH{1'b0}}};





    wire req_wfifo_push = (mem_en_i || mem_req_i) && |mem_wben_i;
    wire req_rfifo_push = mem_req_i && !mem_wben_i;


    wire mem_wreq = mem_req_i && |mem_wben_i;

    wire    [LOG_DATA_BYTES:0] extra_write_count = mem_wdata_wout[LOG_DATA_BYTES-1:0] + mem_addr_wout[LOG_DATA_BYTES-1:0];
    wire [31-LOG_DATA_BYTES:0] write_count = mem_wdata_wout[31:LOG_DATA_BYTES] +
                                                ((extra_write_count != 'h0) ? 1 : 0) +
                                                ((extra_write_count > DATA_BYTES) ? 1 : 0);

    wire write_count_overflow = (write_count > 'd256);


    wire wloops_greater_rloops = (r_auxmem_wloops > r_auxmem_rloops);


    wire auxmem_overflow = ((r_auxmem_raddr - r_auxmem_waddr) == RD_WR_THRESHOLD) && (r_auxmem_raddr != r_auxmem_waddr);


    wire mem_rdata_avail = ((r_auxmem_waddr > r_auxmem_raddr) || wloops_greater_rloops) && mem_access_i;

    wire auxmem_wen = axi4_r_valid_i && (axi4_r_id_i == 'h1) && axi4_r_ready_o;

    wire [AUXMEM_ADDR_WIDTH-1:0] auxmem_raddr_incr = rin_auxmem_raddr + 1;



    wire read_stall = (rin_auxmem_waddr == auxmem_raddr_incr) && (tmp_req_count < req_count);


    util_reset_sync i_reset_sync_axi4_bridge (
        .clk_i           (clk_i),
        .reset_q_i       (reset_n_i & (~r_wabort)),
        .scan_mode_i     (1'b0),
        .sync_reset_q_o  (reset_sync_n)
    );



    mem_tp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(AXI_DATA_WIDTH),
        .MEM_ADDRWIDTH(AUXMEM_ADDR_WIDTH)
    ) auxmem (
        .clk	(clk_i),
        .reset  (~reset_n_i),

        .ena	(auxmem_wen),
        .wea	(16'hFFFF),
        .addra	(r_auxmem_waddr),
        .dina	(axi4_r_data_i),

        .enb	(rin_auxmem_ren),
        .addrb	(rin_auxmem_raddr),
        .doutb	(mem_rdata_o)
    );



    sync_fifo #(
        .DATA_WIDTH (AXI_DATA_WIDTH/8+AXI_ADDR_WIDTH+AXI_DATA_WIDTH+1),
        .ADDR_WIDTH ($clog2(MAX_BURST_LENGTH_MSG))
    ) req_wfifo (
        .clk_i		(clk_i),
        .resetn_i	(reset_sync_n),

        .wr_en_i	(req_wfifo_push),
        .wdata_i	({mem_wben_i, mem_addr_i, mem_wdata_i, mem_wreq}),
        .wfull_o	(req_wfifo_full),

        .rd_en_i	(req_wfifo_pop),
        .rdata_o	({mem_wben_wout, mem_addr_wout, mem_wdata_wout, mem_wreq_wout}),
        .rempty_o	(req_wfifo_empty)
    );



    sync_fifo #(
        .DATA_WIDTH (AXI_ADDR_WIDTH+AXI_DATA_WIDTH),
        .ADDR_WIDTH (2)
    ) req_rfifo (
        .clk_i		(clk_i),
        .resetn_i	(reset_n_i),

        .wr_en_i	(req_rfifo_push),
        .wdata_i	({mem_addr_i, mem_wdata_i}),
        .wfull_o	(req_rfifo_full),

        .rd_en_i	(r_req_rfifo_pop),
        .rdata_o	({mem_addr_rout, mem_wdata_rout}),
        .rempty_o	(req_rfifo_empty)
    );



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            state_wfifo <= S_WFIFO_IDLE;
            state_rfifo <= S_RFIFO_IDLE;

            r_auxmem_waddr <= {AUXMEM_ADDR_WIDTH{1'b0}};
            r_auxmem_raddr <= {AUXMEM_ADDR_WIDTH{1'b0}};

            r_auxmem_wloops <= 16'h0;
            r_auxmem_rloops <= 16'h0;

            r_req_rfifo_pop <= 1'b0;

            r_read_stall <= 1'b0;

            r_error <= 32'h0;
            r_wabort <= 1'b0;

            r_write_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_write_count <= {(32-LOG_DATA_BYTES){1'b0}};
            r_tmp_write_count <= 9'h0;

            r_tmp_wben <= {(AXI_ADDR_WIDTH/8){1'b0}};
            r_tmp_wdata <= {AXI_ADDR_WIDTH{1'b0}};

            r_ar_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_req_count <= {(32-LOG_DATA_BYTES){1'b0}};
        end
        else begin
            state_wfifo <= next_state_wfifo;
            state_rfifo <= next_state_rfifo;

            r_auxmem_waddr <= rin_auxmem_waddr;
            r_auxmem_raddr <= rin_auxmem_raddr;

            r_auxmem_wloops <= rin_auxmem_wloops;
            r_auxmem_rloops <= rin_auxmem_rloops;

            r_req_rfifo_pop <= rin_req_rfifo_pop;

            r_read_stall <= read_stall;

            r_error <= rin_error;
            r_wabort <= rin_wabort;

            r_write_addr <= rin_write_addr;
            r_write_count <= rin_write_count;
            r_tmp_write_count <= rin_tmp_write_count;

            r_tmp_wben <= rin_tmp_wben;
            r_tmp_wdata <= rin_tmp_wdata;

            r_ar_addr <= rin_ar_addr;
            r_req_count <= rin_req_count;
        end
    end





    always @* begin
        rin_auxmem_ren = 1'b0;
        rin_auxmem_raddr = r_auxmem_raddr;
        rin_auxmem_rloops = r_auxmem_rloops;


        if (state_rfifo == S_RFIFO_FINISH) begin
            rin_auxmem_raddr = {AUXMEM_ADDR_WIDTH{1'b0}};
            rin_auxmem_rloops = 16'h0;
        end


        else if ((state_rfifo != S_RFIFO_IDLE) && mem_en_i && !mem_wben_i) begin
            rin_auxmem_ren = 1'b1;


            rin_auxmem_raddr = mem_addr_i[AXI_ADDR_WIDTH-1:LOG_DATA_BYTES] - mem_addr_rout[AXI_ADDR_WIDTH-1:LOG_DATA_BYTES];


            if ((r_auxmem_raddr == {AUXMEM_ADDR_WIDTH{1'b0}}) && wloops_greater_rloops) begin
                rin_auxmem_rloops = r_auxmem_rloops + 'd1;
            end
        end
    end


    always @* begin
        rin_auxmem_waddr = r_auxmem_waddr;
        rin_auxmem_wloops = r_auxmem_wloops;


        if (state_rfifo == S_RFIFO_FINISH) begin
            rin_auxmem_waddr = {AUXMEM_ADDR_WIDTH{1'b0}};
            rin_auxmem_wloops = 16'h0;
        end


        else if ((state_rfifo == S_RFIFO_REQNREAD) && auxmem_wen) begin
            rin_auxmem_waddr = r_auxmem_waddr + 'h1;


            if (r_auxmem_waddr == {AUXMEM_ADDR_WIDTH{1'b1}}) begin
                rin_auxmem_wloops = r_auxmem_wloops + 'd1;
            end
        end
    end



    always @* begin
        rin_error = r_error;
        if ((state_wfifo == S_WFIFO_ERROR) || (state_rfifo == S_RFIFO_ERROR)) begin
            rin_error = r_error + 1;
        end
    end

    assign mem_axi4_error_o = r_error;



    always @* begin
        rin_wabort = r_wabort;

        if (mem_wabort_i) begin
            rin_wabort = 1'b1;
        end
        else if ((state_wfifo == S_WFIFO_FINISH) ||
                 (state_wfifo == S_WFIFO_IDLE)) begin
            rin_wabort = 1'b0;
        end
    end



    assign mem_rdata_avail_o = mem_rdata_avail;
    assign mem_wdata_infifo_o = (r_write_count > 'd0) || (r_tmp_write_count > 'd0) ||
                                (state_wfifo == S_WFIFO_WAIT_BRESP);
    assign mem_wstall_o = req_wfifo_full || r_wabort;
    assign mem_rstall_o = req_rfifo_full || (r_read_stall && mem_rdata_avail);



    assign axi4_aw_id_o = 'h1;
    assign axi4_aw_size_o = LOG_DATA_BYTES;
    assign axi4_aw_burst_o = AXI_BURST_TYPE_INCR;

    assign axi4_b_ready_o = (state_wfifo == S_WFIFO_WAIT_BRESP);




    always @* begin
        next_state_wfifo = state_wfifo;

        req_wfifo_pop = 1'b0;

        axi4_aw_valid_o = 1'b0;
        axi4_aw_addr_o = {AXI_ADDR_WIDTH{1'b0}};
        axi4_aw_len_o = 8'h0;
        axi4_w_valid_o = 1'b0;
        axi4_w_data_o = mem_wdata_wout;
        axi4_w_strb_o = mem_wben_wout;
        axi4_w_last_o = 1'b0;

        rin_write_addr = r_write_addr;
        rin_write_count = r_write_count;
        rin_tmp_write_count = r_tmp_write_count;

        rin_tmp_wben = r_tmp_wben;
        rin_tmp_wdata = r_tmp_wdata;

        case (state_wfifo)



            S_WFIFO_IDLE: begin
                if (!req_wfifo_empty) begin


                    if (mem_wreq_wout) begin

                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_addr_o = mem_addr_wout;
                        rin_write_addr = mem_addr_wout;


                        if (write_count_overflow) begin
                            axi4_aw_len_o = 'd255;
                            rin_write_count = write_count - 'd256;
                            rin_tmp_write_count = 'd256;
                        end
                        else begin
                            axi4_aw_len_o = write_count - 1;
                            rin_write_count = 'd0;
                            rin_tmp_write_count = write_count;
                        end


                        if (axi4_aw_ready_i) begin
                            req_wfifo_pop = 1'b1;

                            if (r_wabort) begin
                                next_state_wfifo = S_WFIFO_ABORT;
                            end else begin
                                next_state_wfifo = S_WFIFO_WRITE_BURST;
                            end
                        end
                        else if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end


                    else if (r_write_count > 'h0) begin
                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_addr_o = r_write_addr;


                        if (r_write_count > 'd256) begin
                            axi4_aw_len_o = 'd255;
                            rin_tmp_write_count = 'd256;
                        end
                        else begin
                            axi4_aw_len_o = r_write_count - 1;
                            rin_tmp_write_count = r_write_count;
                        end

                        if (axi4_aw_ready_i) begin

                            if (r_write_count > 'd256) begin
                                rin_write_count = r_write_count - 'd256;
                            end else begin
                                rin_write_count = 'd0;
                            end

                            if (r_wabort) begin
                                next_state_wfifo = S_WFIFO_ABORT;
                            end else begin
                                next_state_wfifo = S_WFIFO_WRITE_BURST;
                            end
                        end
                        else if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end


                    else begin

                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_len_o = 8'h0;
                        axi4_aw_addr_o = mem_addr_wout;

                        if (axi4_aw_ready_i) begin

                            axi4_w_valid_o = 1'b1;
                            axi4_w_last_o = 1'b1;
                            
                            if (axi4_w_ready_i) begin
                                req_wfifo_pop = 1'b1;
                                next_state_wfifo = S_WFIFO_WAIT_BRESP;
                            end
                            else if (r_wabort) begin
                                rin_tmp_write_count = 'd1;
                                next_state_wfifo = S_WFIFO_ABORT;
                            end
                            else begin
                                next_state_wfifo = S_WFIFO_WRITE_WAIT;
                            end
                        end
                        if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end
                end
            end



            S_WFIFO_WRITE_WAIT: begin
                axi4_w_valid_o = 1'b1;
                axi4_w_last_o = 1'b1;
            
                if (axi4_w_ready_i) begin
                    req_wfifo_pop = 1'b1;
                    next_state_wfifo = S_WFIFO_WAIT_BRESP;
                end
                else if (r_wabort) begin
                    rin_tmp_write_count = 'd1;
                    next_state_wfifo = S_WFIFO_ABORT;
                end
            end



            S_WFIFO_WRITE_BURST: begin
                if (r_wabort) begin
                    next_state_wfifo = S_WFIFO_ABORT;
                end
                else if (!req_wfifo_empty) begin
                    

                    if (!mem_wreq_wout) begin


                        if (mem_wben_wout[AXI_DATA_WIDTH/8-1] || !(|mem_wben_wout) || (r_tmp_write_count == 'd1)) begin
                            axi4_w_valid_o = 1'b1;

                            if (axi4_w_ready_i) begin
                                req_wfifo_pop = 1'b1;
                                rin_tmp_write_count = r_tmp_write_count - 1;


                                axi4_w_data_o = r_tmp_wdata | mem_wdata_wout;
                                axi4_w_strb_o = r_tmp_wben | mem_wben_wout;

                                if (r_tmp_wben) begin
                                    rin_tmp_wben = {(AXI_DATA_WIDTH/8){1'b0}};
                                    rin_tmp_wdata = {AXI_DATA_WIDTH{1'b0}};
                                end

                                if (r_tmp_write_count == 'd1) begin
                                    axi4_w_last_o = 1'b1;
                                    next_state_wfifo = S_WFIFO_WAIT_BRESP;
                                end
                            end
                        end


                        else begin
                            rin_tmp_wben = mem_wben_wout;
                            rin_tmp_wdata = mem_wdata_wout;

                            req_wfifo_pop = 1'b1;
                        end
                    end
                    else begin

                        next_state_wfifo = S_WFIFO_ABORT;
                    end
                end
            end



            S_WFIFO_WAIT_BRESP: begin
                if (axi4_b_valid_i && (axi4_b_id_i == 'h1)) begin
                    if (axi4_b_resp_i == AXI_RESP_TYPE_OKAY) begin
                        if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end else begin
                            next_state_wfifo = S_WFIFO_FINISH;
                        end
                    end
                    else begin
                        next_state_wfifo = S_WFIFO_ERROR;
                    end
                end
            end



            S_WFIFO_ABORT: begin
                if (r_tmp_write_count != 'd0) begin
                    axi4_w_valid_o = 1'b1;
                    axi4_w_data_o = {AXI_DATA_WIDTH{1'b0}};
                    axi4_w_strb_o = {(AXI_DATA_WIDTH/8){1'b0}};

                    if (axi4_w_ready_i) begin
                        rin_tmp_write_count = r_tmp_write_count - 1;

                        if (r_tmp_write_count == 'd1) begin
                            axi4_w_last_o = 1'b1;
                            next_state_wfifo = S_WFIFO_WAIT_BRESP;
                        end
                    end
                end
                else begin
                    next_state_wfifo = S_WFIFO_ERROR;
                end
            end



            S_WFIFO_ERROR: begin
                rin_write_count = 'd0;


                next_state_wfifo = S_WFIFO_FINISH;
            end


            S_WFIFO_FINISH: begin

                rin_write_addr = r_write_addr + ('d256 << LOG_DATA_BYTES);


                rin_tmp_wben = {(AXI_DATA_WIDTH/8){1'b0}};
                rin_tmp_wdata = {AXI_DATA_WIDTH{1'b0}};

                next_state_wfifo = S_WFIFO_IDLE;
            end

            default: next_state_wfifo = S_WFIFO_IDLE;
        endcase
    end



    assign axi4_ar_id_o = 'h1;
    assign axi4_ar_size_o = LOG_DATA_BYTES;
    assign axi4_ar_burst_o = AXI_BURST_TYPE_INCR;

    assign axi4_r_ready_o = !auxmem_overflow;




    always @* begin
        next_state_rfifo = state_rfifo;

        rin_req_rfifo_pop = 1'b0;
        rin_req_count = r_req_count;
        rin_ar_addr = r_ar_addr;

        axi4_ar_valid_o = 1'b0;
        axi4_ar_len_o = 8'h0;
        axi4_ar_addr_o = {AXI_ADDR_WIDTH{1'b0}};


        case (state_rfifo)



            S_RFIFO_IDLE: begin

                if (!req_rfifo_empty && !auxmem_overflow) begin


                    axi4_ar_addr_o = mem_addr_rout;
                    axi4_ar_valid_o = 1'b1;

                    if (req_count_overflow) begin

                        axi4_ar_len_o = 'd255;
                    end


                    else begin
                        axi4_ar_len_o = req_count - 1;
                    end

                    if (axi4_ar_ready_i) begin
                        if (req_count_overflow) begin
                            rin_req_count = req_count - 'd256;
                            rin_ar_addr = mem_addr_rout + ('d256 << LOG_DATA_BYTES);
                        end
                        else begin
                            rin_req_count = 'h0;
                        end

                        next_state_rfifo = S_RFIFO_REQNREAD;
                    end
                end
            end


            S_RFIFO_REQNREAD: begin

                if ((r_req_count > 'h0) && !auxmem_overflow) begin

                    axi4_ar_addr_o = r_ar_addr;
                    axi4_ar_valid_o = 1'b1;

                    if (r_req_count > 'd256) begin
                        axi4_ar_len_o = 'd255;
                    end else begin
                        axi4_ar_len_o = r_req_count - 1;
                    end

                    if (axi4_ar_ready_i) begin
                        if (r_req_count > 'd256) begin

                            rin_req_count = r_req_count - 'd256;
                            rin_ar_addr = r_ar_addr + ('d256 << LOG_DATA_BYTES);
                        end
                        else begin
                            rin_req_count = 'h0;
                        end
                    end
                end


                if (axi4_r_valid_i) begin
                    if (axi4_r_resp_i != AXI_RESP_TYPE_OKAY) begin
                        rin_req_rfifo_pop = 1'b1;
                        if (axi4_r_last_i) begin
                            next_state_rfifo = S_RFIFO_ERROR;
                        end else begin
                            next_state_rfifo = S_RFIFO_WAITLAST;
                        end
                    end
                    else if (axi4_r_last_i && (r_req_count == 'h0)) begin

                        if (tmp_req_count == req_count) begin
                            next_state_rfifo = S_RFIFO_WAIT_FETCH;
                        end


                        else if (tmp_req_count > req_count) begin
                            rin_req_rfifo_pop = 1'b1;
                            next_state_rfifo = S_RFIFO_ERROR;
                        end
                    end
                end


                if (!mem_access_i) begin
                    rin_req_rfifo_pop = 1'b1;
                    if (axi4_r_valid_i && axi4_r_last_i) begin
                        next_state_rfifo = S_RFIFO_ERROR;
                    end else begin
                        next_state_rfifo = S_RFIFO_WAITLAST;
                    end
                end
            end


            S_RFIFO_WAIT_FETCH: begin
                if (!mem_rdata_avail) begin
                    rin_req_rfifo_pop = 1'b1;
                    next_state_rfifo = S_RFIFO_FINISH;
                end
            end




            S_RFIFO_WAITLAST: begin
                if (axi4_r_valid_i && axi4_r_last_i) begin

                    next_state_rfifo = S_RFIFO_ERROR;
                end
            end



            S_RFIFO_ERROR: begin

                next_state_rfifo = S_RFIFO_FINISH;
            end


            S_RFIFO_FINISH: begin
                next_state_rfifo = S_RFIFO_IDLE;
            end

            default: next_state_rfifo = S_RFIFO_IDLE;
        endcase
    end


endmodule
module mem_axi4_bridge #(
    `include "noc_parameter.vh"
    ,parameter AXI_ID_WIDTH   = 4,
    parameter AXI_ADDR_WIDTH  = 32,
    parameter AXI_DATA_WIDTH  = 128
)
(
    input  wire                        clk_i,
    input  wire                        reset_n_i,

    output wire                 [31:0] mem_axi4_error_o,


    input  wire                        mem_en_i,
    input  wire                        mem_req_i,
    input  wire   [AXI_ADDR_WIDTH-1:0] mem_addr_i,
    input  wire [AXI_DATA_WIDTH/8-1:0] mem_wben_i,
    input  wire   [AXI_DATA_WIDTH-1:0] mem_wdata_i,
    output wire   [AXI_DATA_WIDTH-1:0] mem_rdata_o,
    output wire                        mem_rdata_avail_o,
    output wire                        mem_wdata_infifo_o,
    input  wire                        mem_wabort_i,
    output wire                        mem_wstall_o,
    output wire                        mem_rstall_o,
    input  wire                        mem_access_i,


	input  wire                        axi4_aw_ready_i,
    output reg                         axi4_aw_valid_o,
    output wire     [AXI_ID_WIDTH-1:0] axi4_aw_id_o,
    output reg    [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_o,
    output reg                   [7:0] axi4_aw_len_o,
    output wire                  [2:0] axi4_aw_size_o,
    output wire                  [1:0] axi4_aw_burst_o,
    input  wire                        axi4_w_ready_i,
    output reg                         axi4_w_valid_o,
    output reg    [AXI_DATA_WIDTH-1:0] axi4_w_data_o,
    output reg  [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_o,
    output reg                         axi4_w_last_o,
    output wire                        axi4_b_ready_o,
    input  wire                        axi4_b_valid_i,
    input  wire     [AXI_ID_WIDTH-1:0] axi4_b_id_i,
    input  wire                  [1:0] axi4_b_resp_i,
    input  wire                        axi4_ar_ready_i,
    output reg                         axi4_ar_valid_o,
    output wire     [AXI_ID_WIDTH-1:0] axi4_ar_id_o,
    output reg    [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_o,
    output reg                   [7:0] axi4_ar_len_o,
    output wire                  [2:0] axi4_ar_size_o,
    output wire                  [1:0] axi4_ar_burst_o,
    output wire                        axi4_r_ready_o,
    input  wire                        axi4_r_valid_i,
    input  wire     [AXI_ID_WIDTH-1:0] axi4_r_id_i,
    input  wire   [AXI_DATA_WIDTH-1:0] axi4_r_data_i,
    input  wire                  [1:0] axi4_r_resp_i,
    input  wire                        axi4_r_last_i
);


    localparam AUXMEM_ADDR_WIDTH = 9;

    localparam NUM_STATES_WFIFO    = 3;
    localparam S_WFIFO_IDLE        = 3'h0;
    localparam S_WFIFO_WRITE_WAIT  = 3'h1;
    localparam S_WFIFO_WRITE_BURST = 3'h2;
    localparam S_WFIFO_WAIT_BRESP  = 3'h3;
    localparam S_WFIFO_ABORT       = 3'h4;
    localparam S_WFIFO_ERROR       = 3'h5;
    localparam S_WFIFO_FINISH      = 3'h7;

    localparam NUM_STATES_RFIFO   = 3;
    localparam S_RFIFO_IDLE       = 3'h0;
    localparam S_RFIFO_REQNREAD   = 3'h1;
    localparam S_RFIFO_WAIT_FETCH = 3'h2;
    localparam S_RFIFO_WAITLAST   = 3'h3;
    localparam S_RFIFO_ERROR      = 3'h4;
    localparam S_RFIFO_FINISH     = 3'h7;

    localparam AXI_BURST_TYPE_FIXED = 2'h0;
    localparam AXI_BURST_TYPE_INCR  = 2'h1;
    localparam AXI_BURST_TYPE_WRAP  = 2'h2;

    localparam AXI_RESP_TYPE_OKAY   = 2'h0;
    localparam AXI_RESP_TYPE_EXOKAY = 2'h1;
    localparam AXI_RESP_TYPE_SLVERR = 2'h2;
    localparam AXI_RESP_TYPE_DECERR = 2'h3;


    localparam DATA_BYTES = AXI_DATA_WIDTH/8;
    localparam LOG_DATA_BYTES = $clog2(DATA_BYTES);

    localparam [AUXMEM_ADDR_WIDTH-1:0] RD_WR_THRESHOLD = 5;


    reg [NUM_STATES_WFIFO-1:0] state_wfifo, next_state_wfifo;
    reg [NUM_STATES_RFIFO-1:0] state_rfifo, next_state_rfifo;



    reg [AUXMEM_ADDR_WIDTH-1:0] r_auxmem_waddr, rin_auxmem_waddr;
    reg	[AUXMEM_ADDR_WIDTH-1:0] r_auxmem_raddr, rin_auxmem_raddr;
    reg                         rin_auxmem_ren;
    reg                  [15:0] r_auxmem_wloops, rin_auxmem_wloops;
    reg                  [15:0] r_auxmem_rloops, rin_auxmem_rloops;

    reg req_wfifo_pop;
    reg r_req_rfifo_pop, rin_req_rfifo_pop;

    reg r_read_stall;


    reg [31:0] r_error, rin_error;


    reg r_wabort, rin_wabort;

    reg   [AXI_ADDR_WIDTH-1:0] r_write_addr, rin_write_addr;
    reg  [31-LOG_DATA_BYTES:0] r_write_count, rin_write_count;
    reg                  [8:0] r_tmp_write_count, rin_tmp_write_count;

    reg [AXI_DATA_WIDTH/8-1:0] r_tmp_wben, rin_tmp_wben;
    reg   [AXI_DATA_WIDTH-1:0] r_tmp_wdata, rin_tmp_wdata;

    reg   [AXI_ADDR_WIDTH-1:0] r_ar_addr, rin_ar_addr;
    reg  [31-LOG_DATA_BYTES:0] r_req_count, rin_req_count;

    wire reset_sync_n;

    wire [AXI_DATA_WIDTH/8-1:0] mem_wben_wout;
    wire   [AXI_ADDR_WIDTH-1:0] mem_addr_wout;
    wire   [AXI_DATA_WIDTH-1:0] mem_wdata_wout;
    wire                        mem_wreq_wout;
    wire   [AXI_ADDR_WIDTH-1:0] mem_addr_rout;
    wire   [AXI_DATA_WIDTH-1:0] mem_wdata_rout;

    wire req_wfifo_empty, req_wfifo_full;
    wire req_rfifo_empty, req_rfifo_full;






    wire    [LOG_DATA_BYTES:0] extra_req_count = mem_wdata_rout[LOG_DATA_BYTES-1:0] + mem_addr_rout[LOG_DATA_BYTES-1:0];
    wire [31-LOG_DATA_BYTES:0] req_count = req_rfifo_empty ? {(32-LOG_DATA_BYTES){1'b0}} :
                                                mem_wdata_rout[31:LOG_DATA_BYTES] +
                                                ((extra_req_count != 'h0) ? 1 : 0) +
                                                ((extra_req_count > DATA_BYTES) ? 1 : 0);


    wire req_count_overflow = (req_count > 'd256);


    wire [31-LOG_DATA_BYTES:0] tmp_req_count = rin_auxmem_waddr + {rin_auxmem_wloops, {AUXMEM_ADDR_WIDTH{1'b0}}};





    wire req_wfifo_push = (mem_en_i || mem_req_i) && |mem_wben_i;
    wire req_rfifo_push = mem_req_i && !mem_wben_i;


    wire mem_wreq = mem_req_i && |mem_wben_i;

    wire    [LOG_DATA_BYTES:0] extra_write_count = mem_wdata_wout[LOG_DATA_BYTES-1:0] + mem_addr_wout[LOG_DATA_BYTES-1:0];
    wire [31-LOG_DATA_BYTES:0] write_count = mem_wdata_wout[31:LOG_DATA_BYTES] +
                                                ((extra_write_count != 'h0) ? 1 : 0) +
                                                ((extra_write_count > DATA_BYTES) ? 1 : 0);

    wire write_count_overflow = (write_count > 'd256);


    wire wloops_greater_rloops = (r_auxmem_wloops > r_auxmem_rloops);


    wire auxmem_overflow = ((r_auxmem_raddr - r_auxmem_waddr) == RD_WR_THRESHOLD) && (r_auxmem_raddr != r_auxmem_waddr);


    wire mem_rdata_avail = ((r_auxmem_waddr > r_auxmem_raddr) || wloops_greater_rloops) && mem_access_i;

    wire auxmem_wen = axi4_r_valid_i && (axi4_r_id_i == 'h1) && axi4_r_ready_o;

    wire [AUXMEM_ADDR_WIDTH-1:0] auxmem_raddr_incr = rin_auxmem_raddr + 1;



    wire read_stall = (rin_auxmem_waddr == auxmem_raddr_incr) && (tmp_req_count < req_count);


    util_reset_sync i_reset_sync_axi4_bridge (
        .clk_i           (clk_i),
        .reset_q_i       (reset_n_i & (~r_wabort)),
        .scan_mode_i     (1'b0),
        .sync_reset_q_o  (reset_sync_n)
    );



    mem_tp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(AXI_DATA_WIDTH),
        .MEM_ADDRWIDTH(AUXMEM_ADDR_WIDTH)
    ) auxmem (
        .clk	(clk_i),
        .reset  (~reset_n_i),

        .ena	(auxmem_wen),
        .wea	(16'hFFFF),
        .addra	(r_auxmem_waddr),
        .dina	(axi4_r_data_i),

        .enb	(rin_auxmem_ren),
        .addrb	(rin_auxmem_raddr),
        .doutb	(mem_rdata_o)
    );



    sync_fifo #(
        .DATA_WIDTH (AXI_DATA_WIDTH/8+AXI_ADDR_WIDTH+AXI_DATA_WIDTH+1),
        .ADDR_WIDTH ($clog2(MAX_BURST_LENGTH_MSG))
    ) req_wfifo (
        .clk_i		(clk_i),
        .resetn_i	(reset_sync_n),

        .wr_en_i	(req_wfifo_push),
        .wdata_i	({mem_wben_i, mem_addr_i, mem_wdata_i, mem_wreq}),
        .wfull_o	(req_wfifo_full),

        .rd_en_i	(req_wfifo_pop),
        .rdata_o	({mem_wben_wout, mem_addr_wout, mem_wdata_wout, mem_wreq_wout}),
        .rempty_o	(req_wfifo_empty)
    );



    sync_fifo #(
        .DATA_WIDTH (AXI_ADDR_WIDTH+AXI_DATA_WIDTH),
        .ADDR_WIDTH (2)
    ) req_rfifo (
        .clk_i		(clk_i),
        .resetn_i	(reset_n_i),

        .wr_en_i	(req_rfifo_push),
        .wdata_i	({mem_addr_i, mem_wdata_i}),
        .wfull_o	(req_rfifo_full),

        .rd_en_i	(r_req_rfifo_pop),
        .rdata_o	({mem_addr_rout, mem_wdata_rout}),
        .rempty_o	(req_rfifo_empty)
    );



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            state_wfifo <= S_WFIFO_IDLE;
            state_rfifo <= S_RFIFO_IDLE;

            r_auxmem_waddr <= {AUXMEM_ADDR_WIDTH{1'b0}};
            r_auxmem_raddr <= {AUXMEM_ADDR_WIDTH{1'b0}};

            r_auxmem_wloops <= 16'h0;
            r_auxmem_rloops <= 16'h0;

            r_req_rfifo_pop <= 1'b0;

            r_read_stall <= 1'b0;

            r_error <= 32'h0;
            r_wabort <= 1'b0;

            r_write_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_write_count <= {(32-LOG_DATA_BYTES){1'b0}};
            r_tmp_write_count <= 9'h0;

            r_tmp_wben <= {(AXI_ADDR_WIDTH/8){1'b0}};
            r_tmp_wdata <= {AXI_ADDR_WIDTH{1'b0}};

            r_ar_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_req_count <= {(32-LOG_DATA_BYTES){1'b0}};
        end
        else begin
            state_wfifo <= next_state_wfifo;
            state_rfifo <= next_state_rfifo;

            r_auxmem_waddr <= rin_auxmem_waddr;
            r_auxmem_raddr <= rin_auxmem_raddr;

            r_auxmem_wloops <= rin_auxmem_wloops;
            r_auxmem_rloops <= rin_auxmem_rloops;

            r_req_rfifo_pop <= rin_req_rfifo_pop;

            r_read_stall <= read_stall;

            r_error <= rin_error;
            r_wabort <= rin_wabort;

            r_write_addr <= rin_write_addr;
            r_write_count <= rin_write_count;
            r_tmp_write_count <= rin_tmp_write_count;

            r_tmp_wben <= rin_tmp_wben;
            r_tmp_wdata <= rin_tmp_wdata;

            r_ar_addr <= rin_ar_addr;
            r_req_count <= rin_req_count;
        end
    end





    always @* begin
        rin_auxmem_ren = 1'b0;
        rin_auxmem_raddr = r_auxmem_raddr;
        rin_auxmem_rloops = r_auxmem_rloops;


        if (state_rfifo == S_RFIFO_FINISH) begin
            rin_auxmem_raddr = {AUXMEM_ADDR_WIDTH{1'b0}};
            rin_auxmem_rloops = 16'h0;
        end


        else if ((state_rfifo != S_RFIFO_IDLE) && mem_en_i && !mem_wben_i) begin
            rin_auxmem_ren = 1'b1;


            rin_auxmem_raddr = mem_addr_i[AXI_ADDR_WIDTH-1:LOG_DATA_BYTES] - mem_addr_rout[AXI_ADDR_WIDTH-1:LOG_DATA_BYTES];


            if ((r_auxmem_raddr == {AUXMEM_ADDR_WIDTH{1'b0}}) && wloops_greater_rloops) begin
                rin_auxmem_rloops = r_auxmem_rloops + 'd1;
            end
        end
    end


    always @* begin
        rin_auxmem_waddr = r_auxmem_waddr;
        rin_auxmem_wloops = r_auxmem_wloops;


        if (state_rfifo == S_RFIFO_FINISH) begin
            rin_auxmem_waddr = {AUXMEM_ADDR_WIDTH{1'b0}};
            rin_auxmem_wloops = 16'h0;
        end


        else if ((state_rfifo == S_RFIFO_REQNREAD) && auxmem_wen) begin
            rin_auxmem_waddr = r_auxmem_waddr + 'h1;


            if (r_auxmem_waddr == {AUXMEM_ADDR_WIDTH{1'b1}}) begin
                rin_auxmem_wloops = r_auxmem_wloops + 'd1;
            end
        end
    end



    always @* begin
        rin_error = r_error;
        if ((state_wfifo == S_WFIFO_ERROR) || (state_rfifo == S_RFIFO_ERROR)) begin
            rin_error = r_error + 1;
        end
    end

    assign mem_axi4_error_o = r_error;



    always @* begin
        rin_wabort = r_wabort;

        if (mem_wabort_i) begin
            rin_wabort = 1'b1;
        end
        else if ((state_wfifo == S_WFIFO_FINISH) ||
                 (state_wfifo == S_WFIFO_IDLE)) begin
            rin_wabort = 1'b0;
        end
    end



    assign mem_rdata_avail_o = mem_rdata_avail;
    assign mem_wdata_infifo_o = (r_write_count > 'd0) || (r_tmp_write_count > 'd0) ||
                                (state_wfifo == S_WFIFO_WAIT_BRESP);
    assign mem_wstall_o = req_wfifo_full || r_wabort;
    assign mem_rstall_o = req_rfifo_full || (r_read_stall && mem_rdata_avail);



    assign axi4_aw_id_o = 'h1;
    assign axi4_aw_size_o = LOG_DATA_BYTES;
    assign axi4_aw_burst_o = AXI_BURST_TYPE_INCR;

    assign axi4_b_ready_o = (state_wfifo == S_WFIFO_WAIT_BRESP);




    always @* begin
        next_state_wfifo = state_wfifo;

        req_wfifo_pop = 1'b0;

        axi4_aw_valid_o = 1'b0;
        axi4_aw_addr_o = {AXI_ADDR_WIDTH{1'b0}};
        axi4_aw_len_o = 8'h0;
        axi4_w_valid_o = 1'b0;
        axi4_w_data_o = mem_wdata_wout;
        axi4_w_strb_o = mem_wben_wout;
        axi4_w_last_o = 1'b0;

        rin_write_addr = r_write_addr;
        rin_write_count = r_write_count;
        rin_tmp_write_count = r_tmp_write_count;

        rin_tmp_wben = r_tmp_wben;
        rin_tmp_wdata = r_tmp_wdata;

        case (state_wfifo)



            S_WFIFO_IDLE: begin
                if (!req_wfifo_empty) begin


                    if (mem_wreq_wout) begin

                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_addr_o = mem_addr_wout;
                        rin_write_addr = mem_addr_wout;


                        if (write_count_overflow) begin
                            axi4_aw_len_o = 'd255;
                            rin_write_count = write_count - 'd256;
                            rin_tmp_write_count = 'd256;
                        end
                        else begin
                            axi4_aw_len_o = write_count - 1;
                            rin_write_count = 'd0;
                            rin_tmp_write_count = write_count;
                        end


                        if (axi4_aw_ready_i) begin
                            req_wfifo_pop = 1'b1;

                            if (r_wabort) begin
                                next_state_wfifo = S_WFIFO_ABORT;
                            end else begin
                                next_state_wfifo = S_WFIFO_WRITE_BURST;
                            end
                        end
                        else if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end


                    else if (r_write_count > 'h0) begin
                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_addr_o = r_write_addr;


                        if (r_write_count > 'd256) begin
                            axi4_aw_len_o = 'd255;
                            rin_tmp_write_count = 'd256;
                        end
                        else begin
                            axi4_aw_len_o = r_write_count - 1;
                            rin_tmp_write_count = r_write_count;
                        end

                        if (axi4_aw_ready_i) begin

                            if (r_write_count > 'd256) begin
                                rin_write_count = r_write_count - 'd256;
                            end else begin
                                rin_write_count = 'd0;
                            end

                            if (r_wabort) begin
                                next_state_wfifo = S_WFIFO_ABORT;
                            end else begin
                                next_state_wfifo = S_WFIFO_WRITE_BURST;
                            end
                        end
                        else if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end


                    else begin

                        axi4_aw_valid_o = 1'b1;
                        axi4_aw_len_o = 8'h0;
                        axi4_aw_addr_o = mem_addr_wout;

                        if (axi4_aw_ready_i) begin

                            axi4_w_valid_o = 1'b1;
                            axi4_w_last_o = 1'b1;
                            
                            if (axi4_w_ready_i) begin
                                req_wfifo_pop = 1'b1;
                                next_state_wfifo = S_WFIFO_WAIT_BRESP;
                            end
                            else if (r_wabort) begin
                                rin_tmp_write_count = 'd1;
                                next_state_wfifo = S_WFIFO_ABORT;
                            end
                            else begin
                                next_state_wfifo = S_WFIFO_WRITE_WAIT;
                            end
                        end
                        if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end
                    end
                end
            end



            S_WFIFO_WRITE_WAIT: begin
                axi4_w_valid_o = 1'b1;
                axi4_w_last_o = 1'b1;
            
                if (axi4_w_ready_i) begin
                    req_wfifo_pop = 1'b1;
                    next_state_wfifo = S_WFIFO_WAIT_BRESP;
                end
                else if (r_wabort) begin
                    rin_tmp_write_count = 'd1;
                    next_state_wfifo = S_WFIFO_ABORT;
                end
            end



            S_WFIFO_WRITE_BURST: begin
                if (r_wabort) begin
                    next_state_wfifo = S_WFIFO_ABORT;
                end
                else if (!req_wfifo_empty) begin
                    

                    if (!mem_wreq_wout) begin


                        if (mem_wben_wout[AXI_DATA_WIDTH/8-1] || !(|mem_wben_wout) || (r_tmp_write_count == 'd1)) begin
                            axi4_w_valid_o = 1'b1;

                            if (axi4_w_ready_i) begin
                                req_wfifo_pop = 1'b1;
                                rin_tmp_write_count = r_tmp_write_count - 1;


                                axi4_w_data_o = r_tmp_wdata | mem_wdata_wout;
                                axi4_w_strb_o = r_tmp_wben | mem_wben_wout;

                                if (r_tmp_wben) begin
                                    rin_tmp_wben = {(AXI_DATA_WIDTH/8){1'b0}};
                                    rin_tmp_wdata = {AXI_DATA_WIDTH{1'b0}};
                                end

                                if (r_tmp_write_count == 'd1) begin
                                    axi4_w_last_o = 1'b1;
                                    next_state_wfifo = S_WFIFO_WAIT_BRESP;
                                end
                            end
                        end


                        else begin
                            rin_tmp_wben = mem_wben_wout;
                            rin_tmp_wdata = mem_wdata_wout;

                            req_wfifo_pop = 1'b1;
                        end
                    end
                    else begin

                        next_state_wfifo = S_WFIFO_ABORT;
                    end
                end
            end



            S_WFIFO_WAIT_BRESP: begin
                if (axi4_b_valid_i && (axi4_b_id_i == 'h1)) begin
                    if (axi4_b_resp_i == AXI_RESP_TYPE_OKAY) begin
                        if (r_wabort) begin
                            next_state_wfifo = S_WFIFO_ERROR;
                        end else begin
                            next_state_wfifo = S_WFIFO_FINISH;
                        end
                    end
                    else begin
                        next_state_wfifo = S_WFIFO_ERROR;
                    end
                end
            end



            S_WFIFO_ABORT: begin
                if (r_tmp_write_count != 'd0) begin
                    axi4_w_valid_o = 1'b1;
                    axi4_w_data_o = {AXI_DATA_WIDTH{1'b0}};
                    axi4_w_strb_o = {(AXI_DATA_WIDTH/8){1'b0}};

                    if (axi4_w_ready_i) begin
                        rin_tmp_write_count = r_tmp_write_count - 1;

                        if (r_tmp_write_count == 'd1) begin
                            axi4_w_last_o = 1'b1;
                            next_state_wfifo = S_WFIFO_WAIT_BRESP;
                        end
                    end
                end
                else begin
                    next_state_wfifo = S_WFIFO_ERROR;
                end
            end



            S_WFIFO_ERROR: begin
                rin_write_count = 'd0;


                next_state_wfifo = S_WFIFO_FINISH;
            end


            S_WFIFO_FINISH: begin

                rin_write_addr = r_write_addr + ('d256 << LOG_DATA_BYTES);


                rin_tmp_wben = {(AXI_DATA_WIDTH/8){1'b0}};
                rin_tmp_wdata = {AXI_DATA_WIDTH{1'b0}};

                next_state_wfifo = S_WFIFO_IDLE;
            end

            default: next_state_wfifo = S_WFIFO_IDLE;
        endcase
    end



    assign axi4_ar_id_o = 'h1;
    assign axi4_ar_size_o = LOG_DATA_BYTES;
    assign axi4_ar_burst_o = AXI_BURST_TYPE_INCR;

    assign axi4_r_ready_o = !auxmem_overflow;




    always @* begin
        next_state_rfifo = state_rfifo;

        rin_req_rfifo_pop = 1'b0;
        rin_req_count = r_req_count;
        rin_ar_addr = r_ar_addr;

        axi4_ar_valid_o = 1'b0;
        axi4_ar_len_o = 8'h0;
        axi4_ar_addr_o = {AXI_ADDR_WIDTH{1'b0}};


        case (state_rfifo)



            S_RFIFO_IDLE: begin

                if (!req_rfifo_empty && !auxmem_overflow) begin


                    axi4_ar_addr_o = mem_addr_rout;
                    axi4_ar_valid_o = 1'b1;

                    if (req_count_overflow) begin

                        axi4_ar_len_o = 'd255;
                    end


                    else begin
                        axi4_ar_len_o = req_count - 1;
                    end

                    if (axi4_ar_ready_i) begin
                        if (req_count_overflow) begin
                            rin_req_count = req_count - 'd256;
                            rin_ar_addr = mem_addr_rout + ('d256 << LOG_DATA_BYTES);
                        end
                        else begin
                            rin_req_count = 'h0;
                        end

                        next_state_rfifo = S_RFIFO_REQNREAD;
                    end
                end
            end


            S_RFIFO_REQNREAD: begin

                if ((r_req_count > 'h0) && !auxmem_overflow) begin

                    axi4_ar_addr_o = r_ar_addr;
                    axi4_ar_valid_o = 1'b1;

                    if (r_req_count > 'd256) begin
                        axi4_ar_len_o = 'd255;
                    end else begin
                        axi4_ar_len_o = r_req_count - 1;
                    end

                    if (axi4_ar_ready_i) begin
                        if (r_req_count > 'd256) begin

                            rin_req_count = r_req_count - 'd256;
                            rin_ar_addr = r_ar_addr + ('d256 << LOG_DATA_BYTES);
                        end
                        else begin
                            rin_req_count = 'h0;
                        end
                    end
                end


                if (axi4_r_valid_i) begin
                    if (axi4_r_resp_i != AXI_RESP_TYPE_OKAY) begin
                        rin_req_rfifo_pop = 1'b1;
                        if (axi4_r_last_i) begin
                            next_state_rfifo = S_RFIFO_ERROR;
                        end else begin
                            next_state_rfifo = S_RFIFO_WAITLAST;
                        end
                    end
                    else if (axi4_r_last_i && (r_req_count == 'h0)) begin

                        if (tmp_req_count == req_count) begin
                            next_state_rfifo = S_RFIFO_WAIT_FETCH;
                        end


                        else if (tmp_req_count > req_count) begin
                            rin_req_rfifo_pop = 1'b1;
                            next_state_rfifo = S_RFIFO_ERROR;
                        end
                    end
                end


                if (!mem_access_i) begin
                    rin_req_rfifo_pop = 1'b1;
                    if (axi4_r_valid_i && axi4_r_last_i) begin
                        next_state_rfifo = S_RFIFO_ERROR;
                    end else begin
                        next_state_rfifo = S_RFIFO_WAITLAST;
                    end
                end
            end


            S_RFIFO_WAIT_FETCH: begin
                if (!mem_rdata_avail) begin
                    rin_req_rfifo_pop = 1'b1;
                    next_state_rfifo = S_RFIFO_FINISH;
                end
            end




            S_RFIFO_WAITLAST: begin
                if (axi4_r_valid_i && axi4_r_last_i) begin

                    next_state_rfifo = S_RFIFO_ERROR;
                end
            end



            S_RFIFO_ERROR: begin

                next_state_rfifo = S_RFIFO_FINISH;
            end


            S_RFIFO_FINISH: begin
                next_state_rfifo = S_RFIFO_IDLE;
            end

            default: next_state_rfifo = S_RFIFO_IDLE;
        endcase
    end


endmodule