data/full_repos/permissive/514939538/Controller_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk =~ clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #600\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #400\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #600\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/514939538/Controller_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #2000 \n    ^\n%Error: data/full_repos/permissive/514939538/Controller_TB.v:30: Cannot find file containing module: \'Controller\'\nController dut(clk,reset,requested_floor,wait_floor,door,Up,Down,y);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514939538,data/full_repos/permissive/514939538/Controller\n             data/full_repos/permissive/514939538,data/full_repos/permissive/514939538/Controller.v\n             data/full_repos/permissive/514939538,data/full_repos/permissive/514939538/Controller.sv\n             Controller\n             Controller.v\n             Controller.sv\n             obj_dir/Controller\n             obj_dir/Controller.v\n             obj_dir/Controller.sv\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller_TB.v:43: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hc\' generates 4 bits.\n                                                                       : ... In instance Controller_TB\n    requested_floor=4\'d12;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller_TB.v:45: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                                       : ... In instance Controller_TB\n    requested_floor=4\'d3;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller_TB.v:47: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n                                                                       : ... In instance Controller_TB\n    requested_floor=4\'d13;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller_TB.v:49: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                       : ... In instance Controller_TB\n    requested_floor=4\'d5;\n                   ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Controller_TB();

reg clk,reset;
reg [4:0] requested_floor;
wire [1:0] wait_floor,door,Up,Down; 
wire [4:0] y;

Controller dut(clk,reset,requested_floor,wait_floor,door,Up,Down,y);

initial 
begin
    clk=0;
    forever #5 clk =~ clk;
end

initial 
begin 
    reset = 1;
    #10;
    reset=0;
    requested_floor=4'd12;
    #600
    requested_floor=4'd3;
    #400
    requested_floor=4'd13;
    #600
    requested_floor=4'd5;
    
    #2000 
    $finish;
    
end



endmodule
module Controller_TB();


reg clk,reset;
reg [4:0] requested_floor;
wire [1:0] wait_floor,door,Up,Down; 
wire [4:0] y;

Controller dut(clk,reset,requested_floor,wait_floor,door,Up,Down,y);

initial 
begin
    clk=0;
    forever #5 clk =~ clk;
end

initial 
begin 
    reset = 1;
    #10;
    reset=0;
    requested_floor=4'd12;
    #600
    requested_floor=4'd3;
    #400
    requested_floor=4'd13;
    #600
    requested_floor=4'd5;
    
    #2000 
    $finish;
    
end



endmodule