data/full_repos/permissive/427281804/FPU/verilog/misc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427281804/FPU/verilog/misc.v:23: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'xchg\'\nmodule xchg #(\n       ^~~~\n                                                                             : ... Top module \'bsr\'\nmodule bsr #(\n       ^~~\n                                                                             : ... Top module \'bsl\'\nmodule bsl #(\n       ^~~\n                                                                             : ... Top module \'count_lead_zero\'\nmodule count_lead_zero #(\n       ^~~~~~~~~~~~~~~\n                                                                             : ... Top module \'booth_enc_r4\'\nmodule booth_enc_r4(\n       ^~~~~~~~~~~~\n                                                                             : ... Top module \'cla_adder\'\nmodule cla_adder #(\n       ^~~~~~~~~\n                                                                             : ... Top module \'booth_ppgen_r4\'\nmodule booth_ppgen_r4 #(\n       ^~~~~~~~~~~~~~\n                                                                             : ... Top module \'compl2s\'\nmodule compl2s #(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:195: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                           : ... In instance booth_ppgen_r4\n  o = {(DWIDTH){1\'bx}};\n    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 36 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 40 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 40 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 48 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 36 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 40 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 40 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 48 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Error: Exiting due to 22 warning(s)\n'
module count_lead_zero #(
    parameter W_IN = 32,
    parameter W_OUT = $clog2(W_IN)
) (
    input wire  [W_IN-1:0] in,
    output wire [W_OUT-1:0] out
);

generate
	if (W_IN > 2) begin : gen_recurse
		wire [W_OUT-2:0] half_count;
		wire [W_IN / 2-1:0] lhs = in[W_IN / 2 +: W_IN / 2];
		wire [W_IN / 2-1:0] rhs = in[0        +: W_IN / 2];
		wire left_empty = ~|lhs;

		count_lead_zero #(
			.W_IN (W_IN / 2)
		) inner (
			.in  (left_empty ? rhs : lhs),
			.out (half_count)
		);
		assign out = {left_empty, half_count};
	end else begin : gen_terminal
		assign out = !in[1];
	end
endgenerate

endmodule
module count_lead_zero #(
    parameter W_IN = 32,
    parameter W_OUT = $clog2(W_IN)
) (
    input wire  [W_IN-1:0] in,
    output wire [W_OUT-1:0] out
);


generate
	if (W_IN > 2) begin : gen_recurse
		wire [W_OUT-2:0] half_count;
		wire [W_IN / 2-1:0] lhs = in[W_IN / 2 +: W_IN / 2];
		wire [W_IN / 2-1:0] rhs = in[0        +: W_IN / 2];
		wire left_empty = ~|lhs;

		count_lead_zero #(
			.W_IN (W_IN / 2)
		) inner (
			.in  (left_empty ? rhs : lhs),
			.out (half_count)
		);
		assign out = {left_empty, half_count};
	end else begin : gen_terminal
		assign out = !in[1];
	end
endgenerate

endmodule