data/full_repos/permissive/459277146/complete.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:262: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:270: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd"); $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpvars\n  $dumpfile("dump.vcd"); $dumpvars;\n                         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:368: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD / 2) clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/459277146/complete.v:371: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%d:\\t%d /%d =%d (r =) (V=) (DBZ=)",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:378: Unsupported: Ignoring delay on this delayed statement.\n        #100    x = 4\'b0000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:381: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:383: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:386: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:388: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:391: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:393: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:396: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:398: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0001;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:401: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:403: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:406: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:410: Unsupported: Ignoring delay on this delayed statement.\n        #50     $finish;\n        ^\n%Error: data/full_repos/permissive/459277146/complete.v:413: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("div.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:414: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars; \n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BCD_convert #(parameter DWIDTH = 8)(
    input [DWIDTH-1:0] bin_in,
    output reg [11:0] BCD_out
    );
    
   
    integer i;
    
    always @(bin_in)
    begin
        BCD_out = 0;
        for (i = 0; i < DWIDTH+1; i = i + 1)
        begin

            if (BCD_out[3:0] > 4)
                BCD_out[3:0] = BCD_out[3:0] + 3;
            if (BCD_out[7:4] > 4)
                BCD_out[7:4] = BCD_out[7:4] + 3;
            if (BCD_out[11:8] > 4)
                BCD_out[11:8] = BCD_out[11:8] + 3;
            BCD_out = {BCD_out[DWIDTH+1:0], bin_in[DWIDTH+1 - i]};
        end
    end
    
endmodule
module BCD_convert #(parameter DWIDTH = 8)(
    input [DWIDTH-1:0] bin_in,
    output reg [11:0] BCD_out
    );

    
   
    integer i;
    
    always @(bin_in)
    begin
        BCD_out = 0;
        for (i = 0; i < DWIDTH+1; i = i + 1)
        begin

            if (BCD_out[3:0] > 4)
                BCD_out[3:0] = BCD_out[3:0] + 3;
            if (BCD_out[7:4] > 4)
                BCD_out[7:4] = BCD_out[7:4] + 3;
            if (BCD_out[11:8] > 4)
                BCD_out[11:8] = BCD_out[11:8] + 3;
            BCD_out = {BCD_out[DWIDTH+1:0], bin_in[DWIDTH+1 - i]};
        end
    end
    
endmodule