data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarraysp2x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarraysp2x.v:26: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarraysp2x.v:44: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;\n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarraysp2x.v:53: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg [WIDTH-1:0]     do;\n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarraysp2x.v:64: syntax error, unexpected <=\n    if (~rst_)  do  <= {WIDTH{1'b0}};\n                    ^~\n%Error: Cannot continue\n"
module iarraysp2x
    (
     clk,
     rst_,
     a,
     we,
     re,
     di,
     do,

     test,
     mask
     );

parameter ADDRBIT = 11;
parameter DEPTH = 1536;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               clk;
input               rst_;
input [ADDRBIT-1:0] a;
input               we;
input               re;
input [WIDTH-1:0]   di;
output [WIDTH-1:0]  do;
input               test;
input               mask;

wire [ADDRBIT-1:0]  ia;
wire                iwe;
wire                ire;
wire [WIDTH-1:0]    idi;
wire [WIDTH-1:0]    ido;
reg [WIDTH-1:0]     do;



assign ia   = a;
assign iwe  = we;
assign idi  = di;
assign ire  = re;


always @ (posedge clk or negedge rst_)
    if (~rst_)  do  <= {WIDTH{1'b0}};
    else        do  <= ido;


iramspx #(ADDRBIT,DEPTH,WIDTH) ram (clk,ia,iwe,ire,idi,ido,test,mask);

endmodule
module iarraysp2x
    (
     clk,
     rst_,
     a,
     we,
     re,
     di,
     do,

     test,
     mask
     );


parameter ADDRBIT = 11;
parameter DEPTH = 1536;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               clk;
input               rst_;
input [ADDRBIT-1:0] a;
input               we;
input               re;
input [WIDTH-1:0]   di;
output [WIDTH-1:0]  do;
input               test;
input               mask;

wire [ADDRBIT-1:0]  ia;
wire                iwe;
wire                ire;
wire [WIDTH-1:0]    idi;
wire [WIDTH-1:0]    ido;
reg [WIDTH-1:0]     do;



assign ia   = a;
assign iwe  = we;
assign idi  = di;
assign ire  = re;


always @ (posedge clk or negedge rst_)
    if (~rst_)  do  <= {WIDTH{1'b0}};
    else        do  <= ido;


iramspx #(ADDRBIT,DEPTH,WIDTH) ram (clk,ia,iwe,ire,idi,ido,test,mask);

endmodule