data/full_repos/permissive/458134463/Modules/InstructionMemory_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/InstructionMemory_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10 read_address = 32\'h00000001;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/InstructionMemory_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10 read_address = 32\'h00000002;\n^\n%Error: data/full_repos/permissive/458134463/Modules/InstructionMemory_tb.v:27: Unsupported or unknown PLI call: $monitor\n$monitor("Time        : %2d\\nRead Address: %32b\\nInstruction : %16b\\n", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module InstructionMemory_tb();

reg [31:0] read_address;

wire [15:0] instruction;


InstructionMemory im(read_address, instruction);


initial begin
im.memory[0] = 16'hFFFF;
im.memory[1] = 16'h00FF;
im.memory[2] = 16'hAAAA;

		  read_address = 32'h00000000;
#`DELAY read_address = 32'h00000001;
#`DELAY read_address = 32'h00000002;

end




initial begin
$monitor("Time        : %2d\nRead Address: %32b\nInstruction : %16b\n", 
			$time, read_address, instruction);
end

endmodule
module InstructionMemory_tb();


reg [31:0] read_address;

wire [15:0] instruction;


InstructionMemory im(read_address, instruction);


initial begin
im.memory[0] = 16'hFFFF;
im.memory[1] = 16'h00FF;
im.memory[2] = 16'hAAAA;

		  read_address = 32'h00000000;
#`DELAY read_address = 32'h00000001;
#`DELAY read_address = 32'h00000002;

end




initial begin
$monitor("Time        : %2d\nRead Address: %32b\nInstruction : %16b\n", 
			$time, read_address, instruction);
end

endmodule