data/full_repos/permissive/523038000/lab11/alu_ctl.v
data/verilator_xmls/ed61c305-a7d4-4cb9-9639-3811255d3895.xml
module ALU_Control(Operation, F, ALUop);
    output [2:0] Operation;
    input  [5:0] F;
    input  [1:0] ALUop;

    assign Operation[2] = (F[1] & ALUop[1]) | (ALUop[0]);

    assign Operation[1] =  (~ALUop[1]) | (~F[2]);

    assign Operation[0] = (F[3] | F[0]) & (ALUop[1]);


 


 


endmodule
module ALU_Control(Operation, F, ALUop);

    output [2:0] Operation;
    input  [5:0] F;
    input  [1:0] ALUop;

    assign Operation[2] = (F[1] & ALUop[1]) | (ALUop[0]);

    assign Operation[1] =  (~ALUop[1]) | (~F[2]);

    assign Operation[0] = (F[3] | F[0]) & (ALUop[1]);


 


 


endmodule