data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clock = ~clock; \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n  always #80 clear = ~clear;\n         ^\n%Error: data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("counter_7.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, counter_7_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491294671/timer_input_control/counter/counter_7_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #300 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_7_tb;
  
  reg clock, clear;
  wire saida;
  
  
  counter_7 dut(.clock(clock), .clear(clear), .saida(saida));
  
  always #5 clock = ~clock; 
  always #80 clear = ~clear;
  
  initial begin
    
    $dumpfile("counter_7.vcd");
    $dumpvars(0, counter_7_tb);
    
    clock = 0; clear = 0;
    #300 $finish;
     
  end
  
endmodule
module counter_7_tb;

  
  reg clock, clear;
  wire saida;
  
  
  counter_7 dut(.clock(clock), .clear(clear), .saida(saida));
  
  always #5 clock = ~clock; 
  always #80 clear = ~clear;
  
  initial begin
    
    $dumpfile("counter_7.vcd");
    $dumpvars(0, counter_7_tb);
    
    clock = 0; clear = 0;
    #300 $finish;
     
  end
  
endmodule