data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen/gen_counter.v
data/verilator_xmls/31bdb5da-d09c-4bdf-9e87-069d41faeecc.xml
module gen_counter
#(
	parameter DATA_WIDTH = 32
)
(
	input  clk,
	input  en,
	input  [DATA_WIDTH - 1 : 0] wait_val,
	output f
);

	reg [DATA_WIDTH - 1 : 0] count = 0;
	reg F_O = 0;
	assign f = F_O;

always @ (posedge clk)
	begin
	if (!en)
	begin
		count <= 0;
		F_O = 0;
	end
	else if (count < wait_val)
		count <= count + 1;
	else if (count >= wait_val)
		F_O = 1;
	end
endmodule
module gen_counter
#(
	parameter DATA_WIDTH = 32
)
(
	input  clk,
	input  en,
	input  [DATA_WIDTH - 1 : 0] wait_val,
	output f
);


	reg [DATA_WIDTH - 1 : 0] count = 0;
	reg F_O = 0;
	assign f = F_O;

always @ (posedge clk)
	begin
	if (!en)
	begin
		count <= 0;
		F_O = 0;
	end
	else if (count < wait_val)
		count <= count + 1;
	else if (count >= wait_val)
		F_O = 1;
	end
endmodule