data/full_repos/permissive/426072575/labs/lab6_adder-subtractor/codes/signed full adder-subtractor(Question 3 4 5)/sim_fulladd.v
1: b'%Error: Cannot find file containing module: full\n        ... Looked in:\n             data/full_repos/permissive/426072575/labs/lab6_adder-subtractor/codes/signed/full\n             data/full_repos/permissive/426072575/labs/lab6_adder-subtractor/codes/signed/full.v\n             data/full_repos/permissive/426072575/labs/lab6_adder-subtractor/codes/signed/full.sv\n             full\n             full.v\n             full.sv\n             obj_dir/full\n             obj_dir/full.v\n             obj_dir/full.sv\n%Error: Cannot find file containing module: adder-subtractor(Question\n%Error: Cannot find file containing module: 3\n%Error: Cannot find file containing module: 4\n%Error: Cannot find file containing module: 5),data/full_repos/permissive/426072575\n%Error: Cannot find file containing module: data/full_repos/permissive/426072575/labs/lab6_adder-subtractor/codes/signed\n%Error: Cannot find file containing module: 5)/sim_fulladd.v\n%Error: Exiting due to 7 error(s)\n'
module sim_fulladd;
reg  [4:0] x, y;
reg subFlag;
wire [4:0] sum;
wire cout, overflow;
reg clk;

initial clk = 0;
always # 10 clk = ~clk;
initial begin
x = 5'b0;
y = 5'b0;
subFlag = 0;

end

initial begin
    
    #50 subFlag = 0;
    #50 x = 5'd3;
    #50 y = 5'd5;
    
    
    #50 x = 0;
    #50 y = 0;
    
    
    #50 subFlag = 1;
    #50 x = 5'd3;
    #50 y = 5'd5;
    
    #50 x = 0;
    #50 y = 0;
    

    #50 subFlag = 1;
    #50 x = 5'd0;
    #50 y = 5'd0;
    
    #50 subFlag = 0;
    #50 x = 5'd7;
    #50 y = 5'd9;
    
    #50 x = 0;
    #50 y = 0;
    
    #50 subFlag = 0;
    #50 x = 5'd3;
    #50 y = 5'd3;
    
    #50 subFlag = 1;
    #50 x = 5'b11111;
    #50 y = 5'b10001;
    
    
    #50 x = 0;
    #50 y = 0;   
end

FullAddSub addsub(x, y, subFlag, sum, cout, overflow);
endmodule
module sim_fulladd;

reg  [4:0] x, y;
reg subFlag;
wire [4:0] sum;
wire cout, overflow;
reg clk;

initial clk = 0;
always # 10 clk = ~clk;
initial begin
x = 5'b0;
y = 5'b0;
subFlag = 0;

end

initial begin
    
    #50 subFlag = 0;
    #50 x = 5'd3;
    #50 y = 5'd5;
    
    
    #50 x = 0;
    #50 y = 0;
    
    
    #50 subFlag = 1;
    #50 x = 5'd3;
    #50 y = 5'd5;
    
    #50 x = 0;
    #50 y = 0;
    

    #50 subFlag = 1;
    #50 x = 5'd0;
    #50 y = 5'd0;
    
    #50 subFlag = 0;
    #50 x = 5'd7;
    #50 y = 5'd9;
    
    #50 x = 0;
    #50 y = 0;
    
    #50 subFlag = 0;
    #50 x = 5'd3;
    #50 y = 5'd3;
    
    #50 subFlag = 1;
    #50 x = 5'b11111;
    #50 y = 5'b10001;
    
    
    #50 x = 0;
    #50 y = 0;   
end

FullAddSub addsub(x, y, subFlag, sum, cout, overflow);
endmodule