data/full_repos/permissive/451861474/8 Bit Carry Look ahead Adder/A2Q1_CLA_8bit.v
1: b'%Error: Cannot find file containing module: Bit\n        ... Looked in:\n             data/full_repos/permissive/451861474/8/Bit\n             data/full_repos/permissive/451861474/8/Bit.v\n             data/full_repos/permissive/451861474/8/Bit.sv\n             Bit\n             Bit.v\n             Bit.sv\n             obj_dir/Bit\n             obj_dir/Bit.v\n             obj_dir/Bit.sv\n%Error: Cannot find file containing module: Carry\n%Error: Cannot find file containing module: Look\n%Error: Cannot find file containing module: ahead\n%Error: Cannot find file containing module: Adder,data/full_repos/permissive/451861474\n%Error: Cannot find file containing module: data/full_repos/permissive/451861474/8\n%Error: Cannot find file containing module: Adder/A2Q1_CLA_8bit.v\n%Error: Exiting due to 7 error(s)\n'
module CLA_8bit(A, B, carryIn, carryOut,  Sum);
    input[7:0] A, B;
    input carryIn;
    output carryOut;
    output[7:0] Sum;
    wire[7:0] g, p, C;

    assign g = A & B;
    assign p = A ^ B;
    assign Sum = p ^ C;

    assign C[0] = carryIn;
    assign C[1] = g[0] | (p[0] & C[0]);
    assign C[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & C[0]);
    assign C[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & C[0]);
    assign C[4] = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) |  (p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[5] = g[4]|(g[3] &p[4]) | (p[4] &p[3] & g[2]) | (p[4] &p[3] & p[2] & g[1]) | 
            (p[4] &p[3] & p[2] & p[1] & g[0]) | (p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[6] = g[5]|(g[4] & p[5])|(g[3] &p[4] & p[5]) | (p[5]&p[4] &p[3] & g[2]) | 
            (p[5]&p[4] &p[3] & p[2] & g[1]) | (p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | 
            (p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[7] = g[6]|(g[5] & p[6])|(g[4] & p[5] & p[6])|(g[3] &p[4] & p[5] & p[6]) | 
            (p[6]& p[5]&p[4] &p[3] & g[2]) | (p[6]&p[5]&p[4] &p[3] & p[2] & g[1]) |
            (p[6] &p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | (p[6]&p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign carryOut = g[7]|(g[6]&p[7])|(g[5] & p[6]&p[7])|(g[4] & p[5] & p[6]&p[7])|(g[3] &p[4] & p[5] & 
            p[6]&p[7]) | (p[7]&p[6]& p[5]&p[4] &p[3] & g[2]) | (p[7]&p[6]&p[5]&p[4] &p[3] & p[2] & g[1]) |(p[7]&p[6] &p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | (p[7]&p[6]&p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
endmodule
module CLA_8bit(A, B, carryIn, carryOut,  Sum);

    input[7:0] A, B;
    input carryIn;
    output carryOut;
    output[7:0] Sum;
    wire[7:0] g, p, C;

    assign g = A & B;
    assign p = A ^ B;
    assign Sum = p ^ C;

    assign C[0] = carryIn;
    assign C[1] = g[0] | (p[0] & C[0]);
    assign C[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & C[0]);
    assign C[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & C[0]);
    assign C[4] = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) |  (p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[5] = g[4]|(g[3] &p[4]) | (p[4] &p[3] & g[2]) | (p[4] &p[3] & p[2] & g[1]) | 
            (p[4] &p[3] & p[2] & p[1] & g[0]) | (p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[6] = g[5]|(g[4] & p[5])|(g[3] &p[4] & p[5]) | (p[5]&p[4] &p[3] & g[2]) | 
            (p[5]&p[4] &p[3] & p[2] & g[1]) | (p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | 
            (p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign C[7] = g[6]|(g[5] & p[6])|(g[4] & p[5] & p[6])|(g[3] &p[4] & p[5] & p[6]) | 
            (p[6]& p[5]&p[4] &p[3] & g[2]) | (p[6]&p[5]&p[4] &p[3] & p[2] & g[1]) |
            (p[6] &p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | (p[6]&p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
    assign carryOut = g[7]|(g[6]&p[7])|(g[5] & p[6]&p[7])|(g[4] & p[5] & p[6]&p[7])|(g[3] &p[4] & p[5] & 
            p[6]&p[7]) | (p[7]&p[6]& p[5]&p[4] &p[3] & g[2]) | (p[7]&p[6]&p[5]&p[4] &p[3] & p[2] & g[1]) |(p[7]&p[6] &p[5]&p[4] &p[3] & p[2] & p[1] & g[0]) | (p[7]&p[6]&p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & C[0]);
endmodule