data/full_repos/permissive/528912093/Proiect/ProgramCounter0to15.v
1: b"%Error: data/full_repos/permissive/528912093/Proiect/ProgramCounter0to15.v:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire w2,w3,w4,w6,w8,w10,;\n                         ^\n%Error: data/full_repos/permissive/528912093/Proiect/ProgramCounter0to15.v:18: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ProgramCounter0to15( ClearCounter,EnableCOunt,MainClock,PC[3],PC[2],PC[1],PC[0]);
 input ClearCounter,EnableCOunt,MainClock;
 output PC[3],PC[2],PC[1],PC[0];
 wire w2,w3,w4,w6,w8,w10,;
 dreg #(4) dreg_1(PC[0],w2,w2,w3,w4);
 dreg #(4) dreg_2(PC[1],w6,w6,w3,PC[0]);
 dreg #(4) dreg_3(PC[2],w8,w8,w3,PC[1]);
 dreg #(4) dreg_4(PC[3],w10,w10,w3,PC[2]);
 not #(3) inv_5(w3,ClearCounter);
 and #(3) and2_6(w4,EnableCOunt,MainClock);
endmodule
module ProgramCounter0to15( ClearCounter,EnableCOunt,MainClock,PC[3],PC[2],PC[1],PC[0]);

 input ClearCounter,EnableCOunt,MainClock;
 output PC[3],PC[2],PC[1],PC[0];
 wire w2,w3,w4,w6,w8,w10,;
 dreg #(4) dreg_1(PC[0],w2,w2,w3,w4);
 dreg #(4) dreg_2(PC[1],w6,w6,w3,PC[0]);
 dreg #(4) dreg_3(PC[2],w8,w8,w3,PC[1]);
 dreg #(4) dreg_4(PC[3],w10,w10,w3,PC[2]);
 not #(3) inv_5(w3,ClearCounter);
 and #(3) and2_6(w4,EnableCOunt,MainClock);
endmodule