data/full_repos/permissive/454159683/mux2to1c/mux2to1c.v
data/verilator_xmls/7eb4ae95-c19f-4483-8259-3f7ae1c65ea2.xml
module mux2to1c(input a, b, sel, output reg out);
	always @(sel)
	begin
		out = sel ? b : a;
	end
	







	







endmodule
module mux2to1c(input a, b, sel, output reg out);

	always @(sel)
	begin
		out = sel ? b : a;
	end
	







	







endmodule