data/full_repos/permissive/477054115/Mips16_singlecycle/mips_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/477054115/Mips16_singlecycle/mips_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n           forever #10 clk = ~clk;  \n                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/477054115/Mips16_singlecycle/mips_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n          $dumpvars();\n          ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/477054115/Mips16_singlecycle/mips_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n          #10;  \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/477054115/Mips16_singlecycle/mips_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n          #165 $finish;  \n          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mips16;  

      reg clk;  
      reg reset;  

      wire [15:0] pc_out;  
      wire [15:0] alu_result;

      mips_16 uut (  
           .clk(clk),   
           .reset(reset),   
           .pc_out(pc_out),   
           .alu_result(alu_result)  


      );  
      initial begin  
           clk = 0;  
           forever #10 clk = ~clk;  
      end  
      initial begin  


          $dumpvars();
          reset = 1;  

          #10;  
          reset = 0;  

        
          #165 $finish;  
      end  
 endmodule
module tb_mips16;
  

      reg clk;  
      reg reset;  

      wire [15:0] pc_out;  
      wire [15:0] alu_result;

      mips_16 uut (  
           .clk(clk),   
           .reset(reset),   
           .pc_out(pc_out),   
           .alu_result(alu_result)  


      );  
      initial begin  
           clk = 0;  
           forever #10 clk = ~clk;  
      end  
      initial begin  


          $dumpvars();
          reset = 1;  

          #10;  
          reset = 0;  

        
          #165 $finish;  
      end  
 endmodule