data/full_repos/permissive/460468583/data/yosys/quicklogic/lut_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/quicklogic/lut_sim.v:19: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'LUT1\'\nmodule LUT1 (\n       ^~~~\n                                                                                          : ... Top module \'LUT2\'\nmodule LUT2 (\n       ^~~~\n                                                                                          : ... Top module \'LUT3\'\nmodule LUT3 (\n       ^~~~\n                                                                                          : ... Top module \'LUT4\'\nmodule LUT4 (\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module LUT3 (
  output O,
  input I0, I1, I2
);
  parameter [7:0] INIT = 8'h0;
  parameter EQN = "(I0)";


  specify
    (I0 => O) = 1251;
    (I1 => O) = 1406;
    (I2 => O) = 1699;
  endspecify

  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT3 (
  output O,
  input I0, I1, I2
);

  parameter [7:0] INIT = 8'h0;
  parameter EQN = "(I0)";


  specify
    (I0 => O) = 1251;
    (I1 => O) = 1406;
    (I2 => O) = 1699;
  endspecify

  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  assign O = I0 ? s1[1] : s1[0];
endmodule