data/full_repos/permissive/515565147/LIFO.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515565147/LIFO.v:36: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance LIFO\n    index <= 1\'b0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515565147/LIFO.v:52: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                              : ... In instance LIFO\n  stack[index] = din;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/515565147/LIFO.v:57: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                              : ... In instance LIFO\n  next_dout  = stack[index-1\'b1];\n                    ^\n%Error: Exiting due to 3 warning(s)\n'
module LIFO(
 clk,
 rstn,
 pop,
 push,
 empty,
 full,
 din,
 dout
    );

parameter WIDTH = 8;
parameter DEPTH = 8;

input clk;
input rstn;
input pop;
input push;
input [WIDTH-1:0]din;

output [WIDTH-1:0]dout;
output empty;
output full;

reg [WIDTH-1:0]stack[DEPTH-1:0];
reg [WIDTH-1:0]index, next_index; 
reg [WIDTH-1:0]dout, next_dout;

wire empty, full;

always @ (posedge clk)
begin
  if(!rstn)
  begin
    dout  <= 8'd0;
    index <= 1'b0;
  end
  else
  begin
    dout  <= next_dout;
    index <= next_index;
  end
end

assign empty = !(|index);
assign full  = !(|(index ^ DEPTH));

always @ (*)
begin
  if(push && !full)
  begin
  stack[index] = din;
  next_index   = index+1'b1;
  end
  else if(pop && !empty)
  begin
  next_dout  = stack[index-1'b1];
  next_index = index-1'b1;
  end
  else
  begin
  next_dout  = dout;
  next_index = index;
  end
 
end
endmodule
module LIFO(
 clk,
 rstn,
 pop,
 push,
 empty,
 full,
 din,
 dout
    );


parameter WIDTH = 8;
parameter DEPTH = 8;

input clk;
input rstn;
input pop;
input push;
input [WIDTH-1:0]din;

output [WIDTH-1:0]dout;
output empty;
output full;

reg [WIDTH-1:0]stack[DEPTH-1:0];
reg [WIDTH-1:0]index, next_index; 
reg [WIDTH-1:0]dout, next_dout;

wire empty, full;

always @ (posedge clk)
begin
  if(!rstn)
  begin
    dout  <= 8'd0;
    index <= 1'b0;
  end
  else
  begin
    dout  <= next_dout;
    index <= next_index;
  end
end

assign empty = !(|index);
assign full  = !(|(index ^ DEPTH));

always @ (*)
begin
  if(push && !full)
  begin
  stack[index] = din;
  next_index   = index+1'b1;
  end
  else if(pop && !empty)
  begin
  next_dout  = stack[index-1'b1];
  next_index = index-1'b1;
  end
  else
  begin
  next_dout  = dout;
  next_index = index;
  end
 
end
endmodule