data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_gray_counter.v
data/verilator_xmls/3ecf07f6-2941-4cf3-ab55-7ec813c04bd9.xml
module gray_counter (
  out    ,
  enable ,
  clk    ,
  rst
  );
  

  input clk, rst, enable; 

  output [ 7:0] out;

  wire [7:0] out;
  reg [7:0] count;

  always @ (posedge clk) 
  if (rst) 
    count <= 0; 
  else if (enable) 
    count <= count + 1; 
    
  assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ 
               count[5]),(count[5] ^ count[4]), (count[4] ^ 
               count[3]),(count[3] ^ count[2]), (count[2] ^ 
               count[1]),(count[1] ^ count[0]) };
    
endmodule
module gray_counter (
  out    ,
  enable ,
  clk    ,
  rst
  );

  

  input clk, rst, enable; 

  output [ 7:0] out;

  wire [7:0] out;
  reg [7:0] count;

  always @ (posedge clk) 
  if (rst) 
    count <= 0; 
  else if (enable) 
    count <= count + 1; 
    
  assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ 
               count[5]),(count[5] ^ count[4]), (count[4] ^ 
               count[3]),(count[3] ^ count[2]), (count[2] ^ 
               count[1]),(count[1] ^ count[0]) };
    
endmodule