data/full_repos/permissive/429421342/files/renamed_pixelTop.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/429421342/files/renamed_pixelTop.v:15: Signal definition not found, creating implicitly: \'RAMP\'\n    assign RAMP = CONVERT ? CLK : 0;\n           ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/429421342/files/renamed_pixelTop.v:16: Signal definition not found, creating implicitly: \'VBN1\'\n    assign VBN1 = EXPOSE ? CLK : 0;\n           ^~~~\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop.v:31: Cannot find file containing module: \'PIXEL_ARRAY\'\nPIXEL_ARRAY array(VBN1, RAMP, CLK, RESET, ERASE, EXPOSE, CONVERT, READ, DATA_BUS);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429421342/files,data/full_repos/permissive/429421342/PIXEL_ARRAY\n             data/full_repos/permissive/429421342/files,data/full_repos/permissive/429421342/PIXEL_ARRAY.v\n             data/full_repos/permissive/429421342/files,data/full_repos/permissive/429421342/PIXEL_ARRAY.sv\n             PIXEL_ARRAY\n             PIXEL_ARRAY.v\n             PIXEL_ARRAY.sv\n             obj_dir/PIXEL_ARRAY\n             obj_dir/PIXEL_ARRAY.v\n             obj_dir/PIXEL_ARRAY.sv\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop.v:33: Cannot find file containing module: \'PIXEL_STATE\'\nPIXEL_STATE state(CLK, RESET, ERASE, EXPOSE, READ[3], READ[2], READ[1], READ[0], CONVERT);\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module pixelTop(
    input logic RESET,
    input logic CLK,
    inout [7:0] DATA_BUS, 
    output [3:0] READ
    );

    logic[7:0] DATA;
    wire CONVERT;
    wire ERASE;
    wire EXPOSE;

    assign RAMP = CONVERT ? CLK : 0;
    assign VBN1 = EXPOSE ? CLK : 0;
    assign DATA_BUS = CONVERT ? DATA : 8'bZ;

    always_ff @(posedge CLK or posedge RESET) begin
      if(RESET) begin
         DATA =0;
      end
      if(CONVERT) begin
         DATA +=  1;
      end
      else begin
         DATA = 0;
      end
   end

PIXEL_ARRAY array(VBN1, RAMP, CLK, RESET, ERASE, EXPOSE, CONVERT, READ, DATA_BUS);

PIXEL_STATE state(CLK, RESET, ERASE, EXPOSE, READ[3], READ[2], READ[1], READ[0], CONVERT);

endmodule
module pixelTop(
    input logic RESET,
    input logic CLK,
    inout [7:0] DATA_BUS, 
    output [3:0] READ
    );


    logic[7:0] DATA;
    wire CONVERT;
    wire ERASE;
    wire EXPOSE;

    assign RAMP = CONVERT ? CLK : 0;
    assign VBN1 = EXPOSE ? CLK : 0;
    assign DATA_BUS = CONVERT ? DATA : 8'bZ;

    always_ff @(posedge CLK or posedge RESET) begin
      if(RESET) begin
         DATA =0;
      end
      if(CONVERT) begin
         DATA +=  1;
      end
      else begin
         DATA = 0;
      end
   end

PIXEL_ARRAY array(VBN1, RAMP, CLK, RESET, ERASE, EXPOSE, CONVERT, READ, DATA_BUS);

PIXEL_STATE state(CLK, RESET, ERASE, EXPOSE, READ[3], READ[2], READ[1], READ[0], CONVERT);

endmodule