data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:40: Cannot find file containing module: \'fifo_short\'\n   fifo_short #(.WIDTH(36)) head_fifo\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/fifo_short\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/fifo_short.v\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/fifo_short.sv\n             fifo_short\n             fifo_short.v\n             fifo_short.sv\n             obj_dir/fifo_short\n             obj_dir/fifo_short.v\n             obj_dir/fifo_short.sv\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:80: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'f36_data_int\' generates 36 bits.\n                                                                                          : ... In instance fifo36_to_fifo72\n  dat0 <= f36_data_int;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:96: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'f36_data_int\' generates 36 bits.\n                                                                                          : ... In instance fifo36_to_fifo72\n  dat1 <= f36_data_int;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:109: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'f36_data_int\' generates 36 bits.\n                                                                                           : ... In instance fifo36_to_fifo72\n    dat0 <= f36_data_int;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:133: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'state\' generates 2 bits.\n                                                                                           : ... In instance fifo36_to_fifo72\n   assign    debug = state;\n                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo36_to_fifo72.v:136: Cannot find file containing module: \'fifo_short\'\n   fifo_short #(.WIDTH(72)) tail_fifo\n   ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module fifo36_to_fifo72
  #(parameter LE=0)
   (input clk, input reset, input clear,
    input [35:0] f36_datain,
    input f36_src_rdy_i,
    output f36_dst_rdy_o,

    output [71:0] f72_dataout,
    output f72_src_rdy_o,
    input f72_dst_rdy_i,
    output [31:0] debug
    );
   

   wire [35:0] 	  f36_data_int;
   wire 	  f36_src_rdy_int, f36_dst_rdy_int;
   
   fifo_short #(.WIDTH(36)) head_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
      .space(),.occupied() );


   reg 		  f72_sof_int, f72_eof_int;
   reg [2:0] 	  f72_occ_int;
   wire [71:0] 	  f72_data_int;
   wire 	  f72_src_rdy_int, f72_dst_rdy_int;
      
   reg [1:0] 	  state;
   reg [31:0] 	  dat0, dat1;

   wire 	  f36_sof_int  = f36_data_int[32];
   wire 	  f36_eof_int  = f36_data_int[33];
   wire [1:0]	  f36_occ_int  = f36_data_int[35:34];

   wire 	  xfer_out = f72_src_rdy_int & f72_dst_rdy_int;

   always @(posedge clk)
     if(f36_src_rdy_int & ((state==0)|xfer_out))
       f72_sof_int 	<= f36_sof_int;

   always @(posedge clk)
     if(f36_src_rdy_int & ((state != 2)|xfer_out))
       f72_eof_int 	<= f36_eof_int;

   always @(posedge clk)
     if(reset)
       begin
	  state 	<= 0;
	  f72_occ_int   <= 0;
       end
     else
       if(f36_src_rdy_int)
	 case(state)
	   0 : 
	     begin
		dat0 <= f36_data_int;
		if(f36_eof_int)
		  begin
		     state <= 2;
		     case (f36_occ_int)
		       0 : f72_occ_int <= 3'd4;
		       1 : f72_occ_int <= 3'd1;
		       2 : f72_occ_int <= 3'd2;
		       3 : f72_occ_int <= 3'd3;
		     endcase
		  end
		else
		  state <= 1;
	     end
	   1 : 
	     begin
		dat1 <= f36_data_int;
		state <= 2;
		if(f36_eof_int)
		  case (f36_occ_int)
		    0 : f72_occ_int <= 3'd0;
		    1 : f72_occ_int <= 3'd5;
		    2 : f72_occ_int <= 3'd6;
		    3 : f72_occ_int <= 3'd7;
		  endcase
	     end
	   2 : 
	     if(xfer_out)
	       begin
		  dat0 <= f36_data_int;
		  if(f36_eof_int)
		    case (f36_occ_int)
		      0 : f72_occ_int <= 3'd4;
		      1 : f72_occ_int <= 3'd1;
		      2 : f72_occ_int <= 3'd2;
		      3 : f72_occ_int <= 3'd3;
		    endcase
		  else
		    state 	   <= 1;
	       end
	 endcase
       else
	 if(xfer_out)
	   begin
	      state 	   <= 0;
	      f72_occ_int  <= 0;
	   end
   
   assign    f36_dst_rdy_int  = xfer_out | (state != 2);
   assign    f72_data_int     = LE ? {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat1,dat0} :
				{3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat0,dat1};
   assign    f72_src_rdy_int  = (state == 2);

   assign    debug = state;


   fifo_short #(.WIDTH(72)) tail_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(f72_data_int), .src_rdy_i(f72_src_rdy_int), .dst_rdy_o(f72_dst_rdy_int),
      .dataout(f72_dataout), .src_rdy_o(f72_src_rdy_o), .dst_rdy_i(f72_dst_rdy_i),
      .space(),.occupied() );
   
endmodule
module fifo36_to_fifo72
  #(parameter LE=0)
   (input clk, input reset, input clear,
    input [35:0] f36_datain,
    input f36_src_rdy_i,
    output f36_dst_rdy_o,

    output [71:0] f72_dataout,
    output f72_src_rdy_o,
    input f72_dst_rdy_i,
    output [31:0] debug
    );

   

   wire [35:0] 	  f36_data_int;
   wire 	  f36_src_rdy_int, f36_dst_rdy_int;
   
   fifo_short #(.WIDTH(36)) head_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
      .space(),.occupied() );


   reg 		  f72_sof_int, f72_eof_int;
   reg [2:0] 	  f72_occ_int;
   wire [71:0] 	  f72_data_int;
   wire 	  f72_src_rdy_int, f72_dst_rdy_int;
      
   reg [1:0] 	  state;
   reg [31:0] 	  dat0, dat1;

   wire 	  f36_sof_int  = f36_data_int[32];
   wire 	  f36_eof_int  = f36_data_int[33];
   wire [1:0]	  f36_occ_int  = f36_data_int[35:34];

   wire 	  xfer_out = f72_src_rdy_int & f72_dst_rdy_int;

   always @(posedge clk)
     if(f36_src_rdy_int & ((state==0)|xfer_out))
       f72_sof_int 	<= f36_sof_int;

   always @(posedge clk)
     if(f36_src_rdy_int & ((state != 2)|xfer_out))
       f72_eof_int 	<= f36_eof_int;

   always @(posedge clk)
     if(reset)
       begin
	  state 	<= 0;
	  f72_occ_int   <= 0;
       end
     else
       if(f36_src_rdy_int)
	 case(state)
	   0 : 
	     begin
		dat0 <= f36_data_int;
		if(f36_eof_int)
		  begin
		     state <= 2;
		     case (f36_occ_int)
		       0 : f72_occ_int <= 3'd4;
		       1 : f72_occ_int <= 3'd1;
		       2 : f72_occ_int <= 3'd2;
		       3 : f72_occ_int <= 3'd3;
		     endcase
		  end
		else
		  state <= 1;
	     end
	   1 : 
	     begin
		dat1 <= f36_data_int;
		state <= 2;
		if(f36_eof_int)
		  case (f36_occ_int)
		    0 : f72_occ_int <= 3'd0;
		    1 : f72_occ_int <= 3'd5;
		    2 : f72_occ_int <= 3'd6;
		    3 : f72_occ_int <= 3'd7;
		  endcase
	     end
	   2 : 
	     if(xfer_out)
	       begin
		  dat0 <= f36_data_int;
		  if(f36_eof_int)
		    case (f36_occ_int)
		      0 : f72_occ_int <= 3'd4;
		      1 : f72_occ_int <= 3'd1;
		      2 : f72_occ_int <= 3'd2;
		      3 : f72_occ_int <= 3'd3;
		    endcase
		  else
		    state 	   <= 1;
	       end
	 endcase
       else
	 if(xfer_out)
	   begin
	      state 	   <= 0;
	      f72_occ_int  <= 0;
	   end
   
   assign    f36_dst_rdy_int  = xfer_out | (state != 2);
   assign    f72_data_int     = LE ? {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat1,dat0} :
				{3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat0,dat1};
   assign    f72_src_rdy_int  = (state == 2);

   assign    debug = state;


   fifo_short #(.WIDTH(72)) tail_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(f72_data_int), .src_rdy_i(f72_src_rdy_int), .dst_rdy_o(f72_dst_rdy_int),
      .dataout(f72_dataout), .src_rdy_o(f72_src_rdy_o), .dst_rdy_i(f72_dst_rdy_i),
      .space(),.occupied() );
   
endmodule