data/full_repos/permissive/511902453/pc_reg.v
1: b'%Error: data/full_repos/permissive/511902453/pc_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/511902453,data/full_repos/permissive/511902453/define.v\n             data/full_repos/permissive/511902453,data/full_repos/permissive/511902453/define.v.v\n             data/full_repos/permissive/511902453,data/full_repos/permissive/511902453/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/511902453/pc_reg.v:17: Define or directive not defined: \'`zero_word\'\n   pc_out<=`zero_word;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/511902453/pc_reg.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   pc_out<=`zero_word;\n                     ^\n%Error: Exiting due to 3 error(s)\n'
module pc_reg(
	clk,
	rst_n,
	pc_new,
	pc_out
    );
	input clk;
	input rst_n;
	input [31:0]pc_new;
	
	output reg [31:0]pc_out;
	
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			pc_out<=`zero_word;
		else
			pc_out<=pc_new;
	end	

endmodule
module pc_reg(
	clk,
	rst_n,
	pc_new,
	pc_out
    );

	input clk;
	input rst_n;
	input [31:0]pc_new;
	
	output reg [31:0]pc_out;
	
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			pc_out<=`zero_word;
		else
			pc_out<=pc_new;
	end	

endmodule