data/full_repos/permissive/471089853/src/l2a.v
1: b"%Error: data/full_repos/permissive/471089853/src/l2a.v:236: Cannot find file containing module: 'LZOCShifterSticky_32_to_7_counting_64_F400_uid22'\n  LZOCShifterSticky_32_to_7_counting_64_F400_uid22 lzoc_inst (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifterSticky_32_to_7_counting_64_F400_uid22\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifterSticky_32_to_7_counting_64_F400_uid22.v\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifterSticky_32_to_7_counting_64_F400_uid22.sv\n             LZOCShifterSticky_32_to_7_counting_64_F400_uid22\n             LZOCShifterSticky_32_to_7_counting_64_F400_uid22.v\n             LZOCShifterSticky_32_to_7_counting_64_F400_uid22.sv\n             obj_dir/LZOCShifterSticky_32_to_7_counting_64_F400_uid22\n             obj_dir/LZOCShifterSticky_32_to_7_counting_64_F400_uid22.v\n             obj_dir/LZOCShifterSticky_32_to_7_counting_64_F400_uid22.sv\n%Error: data/full_repos/permissive/471089853/src/l2a.v:244: Cannot find file containing module: 'RightShifterSticky8_by_max_8_F400_uid24'\n  RightShifterSticky8_by_max_8_F400_uid24 rshift (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module l2a(clk, A, isNaN, arith_o);
  reg _00_;
  reg _01_;
  reg [5:0] _02_;
  reg [5:0] _03_;
  reg [5:0] _04_;
  reg [3:0] _05_;
  reg _06_;
  reg [6:0] _07_;
  reg [6:0] _08_;
  reg [6:0] _09_;
  reg _10_;
  reg _11_;
  reg _12_;
  reg _13_;
  reg _14_;
  reg _15_;
  reg _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg _21_;
  reg _22_;
  reg _23_;
  reg _24_;
  reg _25_;
  reg _26_;
  reg _27_;
  wire [5:0] _28_;
  wire [6:0] _29_;
  wire _30_;
  wire [5:0] _31_;
  wire _32_;
  reg _33_;
  wire [3:0] _34_;
  wire [3:0] _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire [1:0] _39_;
  wire [7:0] _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  reg _44_;
  wire _45_;
  wire _46_;
  wire [6:0] _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire [7:0] _51_;
  wire _52_;
  wire [7:0] _53_;
  reg _54_;
  reg _55_;
  reg _56_;
  reg _57_;
  input [31:0] A;
  output [7:0] arith_o;
  wire [3:0] bin_regime;
  wire [3:0] bin_regime_d1;
  input clk;
  wire count_bit;
  wire count_bit_d1;
  wire count_bit_d2;
  wire count_bit_d3;
  wire count_bit_d4;
  wire count_bit_d5;
  wire count_bit_d6;
  wire count_bit_d7;
  wire [5:0] count_lzoc_o;
  wire [7:0] extended_posit;
  wire first_regime;
  wire first_regime_d1;
  wire [6:0] frac_lzoc_o;
  wire [5:0] fraction;
  wire [5:0] fraction_d1;
  wire [5:0] fraction_d2;
  wire [5:0] fraction_d3;
  wire guard;
  wire guard_d1;
  wire guard_d2;
  wire [7:0] in_shift;
  input isNaN;
  wire is_nar;
  wire is_nar_d1;
  wire is_nar_d2;
  wire is_nar_d3;
  wire is_nar_d4;
  wire is_nar_d5;
  wire is_nar_d6;
  wire is_nar_d7;
  wire is_zero;
  wire is_zero_d1;
  wire is_zero_d2;
  wire is_zero_d3;
  wire is_zero_d4;
  wire lsb;
  wire lsb_d1;
  wire lsb_d2;
  wire pad;
  wire pre_sticky;
  wire [3:0] regime;
  wire [31:0] rippled_carry;
  wire round_bit;
  wire round_bit_d1;
  wire [7:0] rounded_posit;
  wire [7:0] rounded_posit_zero;
  wire [6:0] rounded_reg_exp_frac;
  wire [1:0] start_regime;
  wire sticky;
  wire sticky_lzoc_o;
  wire sticky_lzoc_o_d1;
  wire sticky_lzoc_o_d2;
  wire sticky_lzoc_o_d3;
  wire [6:0] truncated_posit;
  wire [6:0] truncated_posit_d1;
  wire [6:0] truncated_posit_d2;
  wire [6:0] truncated_posit_d3;
  wire [5:0] unbiased_exp;
  assign _42_ = fraction_d3[0] | pre_sticky;
  assign _43_ = _42_ | sticky_lzoc_o_d3;
  assign _45_ = sticky | lsb_d2;
  assign _46_ = guard_d2 & _45_;
  assign _47_ = truncated_posit_d3 + { 6'h00, round_bit_d1 };
  assign _48_ = fraction == 6'h00;
  assign _49_ = _48_ ? count_lzoc_o[5] : 1'h0;
  assign _50_ = ~ is_zero_d4;
  assign _51_ = _50_ ? rounded_posit : 8'h00;
  assign _52_ = ~ is_nar_d7;
  assign _53_ = _52_ ? rounded_posit_zero : 8'h80;
  always @(posedge clk)
    _00_ <= count_bit;
  always @(posedge clk)
    _11_ <= count_bit_d1;
  always @(posedge clk)
    _22_ <= count_bit_d2;
  always @(posedge clk)
    _33_ <= count_bit_d3;
  always @(posedge clk)
    _44_ <= count_bit_d4;
  always @(posedge clk)
    _54_ <= count_bit_d5;
  always @(posedge clk)
    _55_ <= count_bit_d6;
  always @(posedge clk)
    _56_ <= sticky_lzoc_o;
  always @(posedge clk)
    _57_ <= sticky_lzoc_o_d1;
  always @(posedge clk)
    _01_ <= sticky_lzoc_o_d2;
  always @(posedge clk)
    _02_ <= fraction;
  always @(posedge clk)
    _03_ <= fraction_d1;
  always @(posedge clk)
    _04_ <= fraction_d2;
  always @(posedge clk)
    _05_ <= bin_regime;
  always @(posedge clk)
    _06_ <= first_regime;
  always @(posedge clk)
    _07_ <= truncated_posit;
  always @(posedge clk)
    _08_ <= truncated_posit_d1;
  always @(posedge clk)
    _09_ <= truncated_posit_d2;
  always @(posedge clk)
    _10_ <= lsb;
  always @(posedge clk)
    _12_ <= lsb_d1;
  always @(posedge clk)
    _13_ <= guard;
  always @(posedge clk)
    _14_ <= guard_d1;
  always @(posedge clk)
    _15_ <= round_bit;
  always @(posedge clk)
    _16_ <= is_nar;
  always @(posedge clk)
    _17_ <= is_nar_d1;
  always @(posedge clk)
    _18_ <= is_nar_d2;
  always @(posedge clk)
    _19_ <= is_nar_d3;
  always @(posedge clk)
    _20_ <= is_nar_d4;
  always @(posedge clk)
    _21_ <= is_nar_d5;
  always @(posedge clk)
    _23_ <= is_nar_d6;
  always @(posedge clk)
    _24_ <= is_zero;
  always @(posedge clk)
    _25_ <= is_zero_d1;
  always @(posedge clk)
    _26_ <= is_zero_d2;
  always @(posedge clk)
    _27_ <= is_zero_d3;
  assign _31_ = 6'h13 - count_lzoc_o;
  assign _32_ = first_regime_d1 == 1'h0;
  assign _34_ = ~ bin_regime_d1;
  function [3:0] \85 ;
    input [3:0] a;
    input [3:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \85  = b[3:0];
      default:
        \85  = a;
    endcase
  endfunction
  assign _35_ = \85 (_34_, bin_regime_d1, _32_);
  assign _36_ = first_regime_d1 ^ count_bit_d4;
  assign _37_ = ~ _36_;
  assign _38_ = pad == 1'h0;
  function [1:0] \92 ;
    input [1:0] a;
    input [1:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \92  = b[1:0];
      default:
        \92  = a;
    endcase
  endfunction
  assign _39_ = \92 (2'h2, 2'h1, _38_);
  LZOCShifterSticky_32_to_7_counting_64_F400_uid22 lzoc_inst (
    .Count(_28_),
    .I(rippled_carry),
    .O(_29_),
    .OZb(count_bit),
    .Sticky(_30_),
    .clk(clk)
  );
  RightShifterSticky8_by_max_8_F400_uid24 rshift (
    .R(_40_),
    .S(regime),
    .Sticky(_41_),
    .X(in_shift),
    .clk(clk),
    .padBit(pad)
  );
  assign rippled_carry = A;
  assign count_bit = rippled_carry[31];
  assign count_bit_d1 = _00_;
  assign count_bit_d2 = _11_;
  assign count_bit_d3 = _22_;
  assign count_bit_d4 = _33_;
  assign count_bit_d5 = _44_;
  assign count_bit_d6 = _54_;
  assign count_bit_d7 = _55_;
  assign count_lzoc_o = _28_;
  assign frac_lzoc_o = _29_;
  assign sticky_lzoc_o = _30_;
  assign sticky_lzoc_o_d1 = _56_;
  assign sticky_lzoc_o_d2 = _57_;
  assign sticky_lzoc_o_d3 = _01_;
  assign unbiased_exp = _31_;
  assign fraction = frac_lzoc_o[5:0];
  assign fraction_d1 = _02_;
  assign fraction_d2 = _03_;
  assign fraction_d3 = _04_;
  assign bin_regime = unbiased_exp[3:0];
  assign bin_regime_d1 = _05_;
  assign first_regime = unbiased_exp[5];
  assign first_regime_d1 = _06_;
  assign regime = _35_;
  assign pad = _37_;
  assign start_regime = _39_;
  assign in_shift = { start_regime, fraction_d1 };
  assign extended_posit = _40_;
  assign pre_sticky = _41_;
  assign truncated_posit = extended_posit[7:1];
  assign truncated_posit_d1 = _07_;
  assign truncated_posit_d2 = _08_;
  assign truncated_posit_d3 = _09_;
  assign lsb = extended_posit[1];
  assign lsb_d1 = _10_;
  assign lsb_d2 = _12_;
  assign guard = extended_posit[0];
  assign guard_d1 = _13_;
  assign guard_d2 = _14_;
  assign sticky = _43_;
  assign round_bit = _46_;
  assign round_bit_d1 = _15_;
  assign is_nar = isNaN;
  assign is_nar_d1 = _16_;
  assign is_nar_d2 = _17_;
  assign is_nar_d3 = _18_;
  assign is_nar_d4 = _19_;
  assign is_nar_d5 = _20_;
  assign is_nar_d6 = _21_;
  assign is_nar_d7 = _23_;
  assign rounded_reg_exp_frac = _47_;
  assign rounded_posit = { count_bit_d7, rounded_reg_exp_frac };
  assign is_zero = _49_;
  assign is_zero_d1 = _24_;
  assign is_zero_d2 = _25_;
  assign is_zero_d3 = _26_;
  assign is_zero_d4 = _27_;
  assign rounded_posit_zero = _51_;
  assign arith_o = _53_;
endmodule
module l2a(clk, A, isNaN, arith_o);

  reg _00_;
  reg _01_;
  reg [5:0] _02_;
  reg [5:0] _03_;
  reg [5:0] _04_;
  reg [3:0] _05_;
  reg _06_;
  reg [6:0] _07_;
  reg [6:0] _08_;
  reg [6:0] _09_;
  reg _10_;
  reg _11_;
  reg _12_;
  reg _13_;
  reg _14_;
  reg _15_;
  reg _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg _21_;
  reg _22_;
  reg _23_;
  reg _24_;
  reg _25_;
  reg _26_;
  reg _27_;
  wire [5:0] _28_;
  wire [6:0] _29_;
  wire _30_;
  wire [5:0] _31_;
  wire _32_;
  reg _33_;
  wire [3:0] _34_;
  wire [3:0] _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire [1:0] _39_;
  wire [7:0] _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  reg _44_;
  wire _45_;
  wire _46_;
  wire [6:0] _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire [7:0] _51_;
  wire _52_;
  wire [7:0] _53_;
  reg _54_;
  reg _55_;
  reg _56_;
  reg _57_;
  input [31:0] A;
  output [7:0] arith_o;
  wire [3:0] bin_regime;
  wire [3:0] bin_regime_d1;
  input clk;
  wire count_bit;
  wire count_bit_d1;
  wire count_bit_d2;
  wire count_bit_d3;
  wire count_bit_d4;
  wire count_bit_d5;
  wire count_bit_d6;
  wire count_bit_d7;
  wire [5:0] count_lzoc_o;
  wire [7:0] extended_posit;
  wire first_regime;
  wire first_regime_d1;
  wire [6:0] frac_lzoc_o;
  wire [5:0] fraction;
  wire [5:0] fraction_d1;
  wire [5:0] fraction_d2;
  wire [5:0] fraction_d3;
  wire guard;
  wire guard_d1;
  wire guard_d2;
  wire [7:0] in_shift;
  input isNaN;
  wire is_nar;
  wire is_nar_d1;
  wire is_nar_d2;
  wire is_nar_d3;
  wire is_nar_d4;
  wire is_nar_d5;
  wire is_nar_d6;
  wire is_nar_d7;
  wire is_zero;
  wire is_zero_d1;
  wire is_zero_d2;
  wire is_zero_d3;
  wire is_zero_d4;
  wire lsb;
  wire lsb_d1;
  wire lsb_d2;
  wire pad;
  wire pre_sticky;
  wire [3:0] regime;
  wire [31:0] rippled_carry;
  wire round_bit;
  wire round_bit_d1;
  wire [7:0] rounded_posit;
  wire [7:0] rounded_posit_zero;
  wire [6:0] rounded_reg_exp_frac;
  wire [1:0] start_regime;
  wire sticky;
  wire sticky_lzoc_o;
  wire sticky_lzoc_o_d1;
  wire sticky_lzoc_o_d2;
  wire sticky_lzoc_o_d3;
  wire [6:0] truncated_posit;
  wire [6:0] truncated_posit_d1;
  wire [6:0] truncated_posit_d2;
  wire [6:0] truncated_posit_d3;
  wire [5:0] unbiased_exp;
  assign _42_ = fraction_d3[0] | pre_sticky;
  assign _43_ = _42_ | sticky_lzoc_o_d3;
  assign _45_ = sticky | lsb_d2;
  assign _46_ = guard_d2 & _45_;
  assign _47_ = truncated_posit_d3 + { 6'h00, round_bit_d1 };
  assign _48_ = fraction == 6'h00;
  assign _49_ = _48_ ? count_lzoc_o[5] : 1'h0;
  assign _50_ = ~ is_zero_d4;
  assign _51_ = _50_ ? rounded_posit : 8'h00;
  assign _52_ = ~ is_nar_d7;
  assign _53_ = _52_ ? rounded_posit_zero : 8'h80;
  always @(posedge clk)
    _00_ <= count_bit;
  always @(posedge clk)
    _11_ <= count_bit_d1;
  always @(posedge clk)
    _22_ <= count_bit_d2;
  always @(posedge clk)
    _33_ <= count_bit_d3;
  always @(posedge clk)
    _44_ <= count_bit_d4;
  always @(posedge clk)
    _54_ <= count_bit_d5;
  always @(posedge clk)
    _55_ <= count_bit_d6;
  always @(posedge clk)
    _56_ <= sticky_lzoc_o;
  always @(posedge clk)
    _57_ <= sticky_lzoc_o_d1;
  always @(posedge clk)
    _01_ <= sticky_lzoc_o_d2;
  always @(posedge clk)
    _02_ <= fraction;
  always @(posedge clk)
    _03_ <= fraction_d1;
  always @(posedge clk)
    _04_ <= fraction_d2;
  always @(posedge clk)
    _05_ <= bin_regime;
  always @(posedge clk)
    _06_ <= first_regime;
  always @(posedge clk)
    _07_ <= truncated_posit;
  always @(posedge clk)
    _08_ <= truncated_posit_d1;
  always @(posedge clk)
    _09_ <= truncated_posit_d2;
  always @(posedge clk)
    _10_ <= lsb;
  always @(posedge clk)
    _12_ <= lsb_d1;
  always @(posedge clk)
    _13_ <= guard;
  always @(posedge clk)
    _14_ <= guard_d1;
  always @(posedge clk)
    _15_ <= round_bit;
  always @(posedge clk)
    _16_ <= is_nar;
  always @(posedge clk)
    _17_ <= is_nar_d1;
  always @(posedge clk)
    _18_ <= is_nar_d2;
  always @(posedge clk)
    _19_ <= is_nar_d3;
  always @(posedge clk)
    _20_ <= is_nar_d4;
  always @(posedge clk)
    _21_ <= is_nar_d5;
  always @(posedge clk)
    _23_ <= is_nar_d6;
  always @(posedge clk)
    _24_ <= is_zero;
  always @(posedge clk)
    _25_ <= is_zero_d1;
  always @(posedge clk)
    _26_ <= is_zero_d2;
  always @(posedge clk)
    _27_ <= is_zero_d3;
  assign _31_ = 6'h13 - count_lzoc_o;
  assign _32_ = first_regime_d1 == 1'h0;
  assign _34_ = ~ bin_regime_d1;
  function [3:0] \85 ;
    input [3:0] a;
    input [3:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \85  = b[3:0];
      default:
        \85  = a;
    endcase
  endfunction
  assign _35_ = \85 (_34_, bin_regime_d1, _32_);
  assign _36_ = first_regime_d1 ^ count_bit_d4;
  assign _37_ = ~ _36_;
  assign _38_ = pad == 1'h0;
  function [1:0] \92 ;
    input [1:0] a;
    input [1:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \92  = b[1:0];
      default:
        \92  = a;
    endcase
  endfunction
  assign _39_ = \92 (2'h2, 2'h1, _38_);
  LZOCShifterSticky_32_to_7_counting_64_F400_uid22 lzoc_inst (
    .Count(_28_),
    .I(rippled_carry),
    .O(_29_),
    .OZb(count_bit),
    .Sticky(_30_),
    .clk(clk)
  );
  RightShifterSticky8_by_max_8_F400_uid24 rshift (
    .R(_40_),
    .S(regime),
    .Sticky(_41_),
    .X(in_shift),
    .clk(clk),
    .padBit(pad)
  );
  assign rippled_carry = A;
  assign count_bit = rippled_carry[31];
  assign count_bit_d1 = _00_;
  assign count_bit_d2 = _11_;
  assign count_bit_d3 = _22_;
  assign count_bit_d4 = _33_;
  assign count_bit_d5 = _44_;
  assign count_bit_d6 = _54_;
  assign count_bit_d7 = _55_;
  assign count_lzoc_o = _28_;
  assign frac_lzoc_o = _29_;
  assign sticky_lzoc_o = _30_;
  assign sticky_lzoc_o_d1 = _56_;
  assign sticky_lzoc_o_d2 = _57_;
  assign sticky_lzoc_o_d3 = _01_;
  assign unbiased_exp = _31_;
  assign fraction = frac_lzoc_o[5:0];
  assign fraction_d1 = _02_;
  assign fraction_d2 = _03_;
  assign fraction_d3 = _04_;
  assign bin_regime = unbiased_exp[3:0];
  assign bin_regime_d1 = _05_;
  assign first_regime = unbiased_exp[5];
  assign first_regime_d1 = _06_;
  assign regime = _35_;
  assign pad = _37_;
  assign start_regime = _39_;
  assign in_shift = { start_regime, fraction_d1 };
  assign extended_posit = _40_;
  assign pre_sticky = _41_;
  assign truncated_posit = extended_posit[7:1];
  assign truncated_posit_d1 = _07_;
  assign truncated_posit_d2 = _08_;
  assign truncated_posit_d3 = _09_;
  assign lsb = extended_posit[1];
  assign lsb_d1 = _10_;
  assign lsb_d2 = _12_;
  assign guard = extended_posit[0];
  assign guard_d1 = _13_;
  assign guard_d2 = _14_;
  assign sticky = _43_;
  assign round_bit = _46_;
  assign round_bit_d1 = _15_;
  assign is_nar = isNaN;
  assign is_nar_d1 = _16_;
  assign is_nar_d2 = _17_;
  assign is_nar_d3 = _18_;
  assign is_nar_d4 = _19_;
  assign is_nar_d5 = _20_;
  assign is_nar_d6 = _21_;
  assign is_nar_d7 = _23_;
  assign rounded_reg_exp_frac = _47_;
  assign rounded_posit = { count_bit_d7, rounded_reg_exp_frac };
  assign is_zero = _49_;
  assign is_zero_d1 = _24_;
  assign is_zero_d2 = _25_;
  assign is_zero_d3 = _26_;
  assign is_zero_d4 = _27_;
  assign rounded_posit_zero = _51_;
  assign arith_o = _53_;
endmodule