data/full_repos/permissive/507383616/rtl/pmu_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:32: Operator VAR \'ESCAPE_CHARCTER\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'hd\' generates 8 bits.\n                                                                            : ... In instance pmu_controller\n    parameter [8:0]ESCAPE_CHARCTER = 8\'h0D,\n                   ^~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:33: Operator VAR \'CLEAN_CHARCTER\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'h20\' generates 8 bits.\n                                                                            : ... In instance pmu_controller\n    parameter [8:0]CLEAN_CHARCTER = 8\'h20,\n                   ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:34: Operator VAR \'LINEFEED\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'ha\' generates 8 bits.\n                                                                            : ... In instance pmu_controller\n    parameter [8:0]LINEFEED = 8\'h0A,\n                   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:35: Operator VAR \'NEWLINE\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'hd\' generates 8 bits.\n                                                                            : ... In instance pmu_controller\n    parameter [8:0]NEWLINE = 8\'h0D\n                   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:58: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                            : ... In instance pmu_controller\n    reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);\n                                                 ^\n%Error: data/full_repos/permissive/507383616/rtl/pmu_controller.v:78: Cannot find file containing module: \'pmu_module\'\n    pmu_module #(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507383616/rtl,data/full_repos/permissive/507383616/pmu_module\n             data/full_repos/permissive/507383616/rtl,data/full_repos/permissive/507383616/pmu_module.v\n             data/full_repos/permissive/507383616/rtl,data/full_repos/permissive/507383616/pmu_module.sv\n             pmu_module\n             pmu_module.v\n             pmu_module.sv\n             obj_dir/pmu_module\n             obj_dir/pmu_module.v\n             obj_dir/pmu_module.sv\n%Error: data/full_repos/permissive/507383616/rtl/pmu_controller.v:95: Cannot find file containing module: \'uart\'\n    uart #(\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:175: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'LINEFEED\' generates 9 bits.\n                                                                             : ... In instance pmu_controller\n                send_data_register[(COUNTERSIZE * 3)-1: (COUNTERSIZE * 2)] <= LINEFEED;\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:176: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'NEWLINE\' generates 9 bits.\n                                                                             : ... In instance pmu_controller\n                send_data_register[(COUNTERSIZE * 4)-1: (COUNTERSIZE * 3)] <= NEWLINE;\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:199: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'uart_rx_axis_tdata\' generates 8 bits.\n                                                                             : ... In instance pmu_controller\n                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_controller.v:192: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'uart_rx_axis_tdata\' generates 8 bits.\n                                                                             : ... In instance pmu_controller\n                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)\n                                            ^~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module pmu_controller#(

    parameter COUNTERSIZE = 8,
    parameter REGISTER_SIZE = 4,
    parameter SIZE_WORD = 3,
    parameter DATA_WIDTH = 8,
    parameter SYMBOL_WITH = 4,
    parameter BAUD_RATE = 115200,
    parameter CLOCK_SPEED = 125000000,
    parameter [8:0]ESCAPE_CHARCTER = 8'h0D,
    parameter [8:0]CLEAN_CHARCTER = 8'h20,
    parameter [8:0]LINEFEED = 8'h0A,
    parameter [8:0]NEWLINE = 8'h0D
	)
(
    
    input  wire clk,
    input  wire rst,
    input  wire rxd_pmu,
    input  wire [2:0] trx_error,
    input  wire [2:0] output_io_error,
    input  wire [2:0] command_arrive,
    input  wire  [2:0] command_arrive_discrepancy,
    output wire  txd_pmu

    );


    (* mark_debug = "true" *)reg [REGISTER_SIZE-1:0] pmu_register;
    (* mark_debug = "true" *)reg [REGISTER_SIZE-1:0] input_data;
    (* mark_debug = "true" *)reg valid_pmu_register;

    (* mark_debug = "true" *)wire valid_value;
    (* mark_debug = "true" *)wire [COUNTERSIZE-1:0] pmu_value;

    reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);


    (* mark_debug = "true" *)reg [DATA_WIDTH-1:0] uart_tx_axis_tdata;
    reg uart_tx_axis_tvalid;
    wire uart_tx_axis_tready;


    (* mark_debug = "true" *)wire [DATA_WIDTH-1:0] uart_rx_axis_tdata;
    wire uart_rx_axis_tvalid;
    reg uart_rx_axis_tready;


    (* mark_debug = "true" *)  reg [(COUNTERSIZE * 4)-1:0] send_data_register;

    (* mark_debug = "true" *)  reg sending_data;

    (* mark_debug = "true" *)reg [SIZE_WORD-1:0] data_size_actual;


    pmu_module #(
        .COUNTERSIZE(COUNTERSIZE),
        .REGISTER_SIZE(REGISTER_SIZE)
        ) pmu_module_inst(
            .clk(clk),
            .rst(rst),
            .trx_error(trx_error),
            .output_io_error(output_io_error),
            .command_arrive(command_arrive),
            .command_arrive_discrepancy(command_arrive_discrepancy),
            .pmu_register(pmu_register),
            .valid_pmu_register(valid_pmu_register),
            .pmu_value(pmu_value),
            .valid_value(valid_value)
            );


    uart #(
        .DATA_WIDTH(DATA_WIDTH)
    )
    uart_inst_pmu(
        .clk(clk),
        .rst(rst),
        .prescale (preescalar_data_rate),
        .s_axis_tdata(uart_tx_axis_tdata),
        .s_axis_tvalid(uart_tx_axis_tvalid),
        .s_axis_tready(uart_tx_axis_tready),

        .m_axis_tdata(uart_rx_axis_tdata),
        .m_axis_tvalid(uart_rx_axis_tvalid),
        .m_axis_tready(uart_rx_axis_tready),
        .rxd(rxd_pmu),
        .txd(txd_pmu),
        .tx_busy(),
        .rx_busy(),
        .rx_overrun_error(),
        .rx_frame_error()
    );


    always @(posedge clk or posedge rst) begin
        if (rst) begin
            uart_tx_axis_tdata <= 0;
            uart_rx_axis_tready <= 0;
            uart_tx_axis_tvalid <= 0;
            data_size_actual <= 0; 
            send_data_register <= 0;
            sending_data <= 0;
            pmu_register <= 0;
            input_data <= 0;
            valid_pmu_register <= 1'b0;
        end
        else begin
                if (uart_tx_axis_tvalid) begin


                uart_rx_axis_tready <= 0;

                if (uart_tx_axis_tready) begin
                    uart_tx_axis_tvalid <= 0;
                end
            end

            else if (sending_data) begin

                valid_pmu_register <= 1'b0;
                if (data_size_actual == 3'b000)begin

                    send_data_register <= 0;
                    sending_data <= 0;
                    uart_tx_axis_tvalid <= 0;
                end
                else begin

                    data_size_actual <= data_size_actual - 1'b1;

                    uart_tx_axis_tvalid <= 1'b1;

                    uart_tx_axis_tdata <= send_data_register[DATA_WIDTH-1: 0];

                    send_data_register <= send_data_register >> DATA_WIDTH;
                end
            end

            if (valid_value) begin

                valid_pmu_register <= 1'b0;

                sending_data <= 1'b1;

                uart_tx_axis_tvalid <= 0;


                send_data_register[7: 0] <= {4'h3,pmu_value[7: 4]} ;

                send_data_register[(COUNTERSIZE * 2)-1: (COUNTERSIZE)] <=   {4'h3,pmu_value[3: 0]};

                send_data_register[(COUNTERSIZE * 3)-1: (COUNTERSIZE * 2)] <= LINEFEED;
                send_data_register[(COUNTERSIZE * 4)-1: (COUNTERSIZE * 3)] <= NEWLINE;
                data_size_actual <= 3'h4;
            end
            else begin

                uart_rx_axis_tready <= 1;
                valid_pmu_register <= 1'b0;
                if (uart_rx_axis_tvalid) begin



                    uart_rx_axis_tready <= ~uart_rx_axis_tready;

                    input_data <= input_data << SYMBOL_WITH;
                    input_data [SYMBOL_WITH-1: 0] <= uart_rx_axis_tdata[SYMBOL_WITH-1:0];

                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)
                    begin
                        valid_pmu_register <= 1'b1;
                        pmu_register <= input_data;
                        input_data <= 0;
                        
                    end
                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin
                        input_data <= 0;
                    end
                    else begin
                        valid_pmu_register <= 1'b0;
                    end
                    
                end
            end
        end
    end

endmodule
module pmu_controller#(

    parameter COUNTERSIZE = 8,
    parameter REGISTER_SIZE = 4,
    parameter SIZE_WORD = 3,
    parameter DATA_WIDTH = 8,
    parameter SYMBOL_WITH = 4,
    parameter BAUD_RATE = 115200,
    parameter CLOCK_SPEED = 125000000,
    parameter [8:0]ESCAPE_CHARCTER = 8'h0D,
    parameter [8:0]CLEAN_CHARCTER = 8'h20,
    parameter [8:0]LINEFEED = 8'h0A,
    parameter [8:0]NEWLINE = 8'h0D
	)
(
    
    input  wire clk,
    input  wire rst,
    input  wire rxd_pmu,
    input  wire [2:0] trx_error,
    input  wire [2:0] output_io_error,
    input  wire [2:0] command_arrive,
    input  wire  [2:0] command_arrive_discrepancy,
    output wire  txd_pmu

    );



    (* mark_debug = "true" *)reg [REGISTER_SIZE-1:0] pmu_register;
    (* mark_debug = "true" *)reg [REGISTER_SIZE-1:0] input_data;
    (* mark_debug = "true" *)reg valid_pmu_register;

    (* mark_debug = "true" *)wire valid_value;
    (* mark_debug = "true" *)wire [COUNTERSIZE-1:0] pmu_value;

    reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH);


    (* mark_debug = "true" *)reg [DATA_WIDTH-1:0] uart_tx_axis_tdata;
    reg uart_tx_axis_tvalid;
    wire uart_tx_axis_tready;


    (* mark_debug = "true" *)wire [DATA_WIDTH-1:0] uart_rx_axis_tdata;
    wire uart_rx_axis_tvalid;
    reg uart_rx_axis_tready;


    (* mark_debug = "true" *)  reg [(COUNTERSIZE * 4)-1:0] send_data_register;

    (* mark_debug = "true" *)  reg sending_data;

    (* mark_debug = "true" *)reg [SIZE_WORD-1:0] data_size_actual;


    pmu_module #(
        .COUNTERSIZE(COUNTERSIZE),
        .REGISTER_SIZE(REGISTER_SIZE)
        ) pmu_module_inst(
            .clk(clk),
            .rst(rst),
            .trx_error(trx_error),
            .output_io_error(output_io_error),
            .command_arrive(command_arrive),
            .command_arrive_discrepancy(command_arrive_discrepancy),
            .pmu_register(pmu_register),
            .valid_pmu_register(valid_pmu_register),
            .pmu_value(pmu_value),
            .valid_value(valid_value)
            );


    uart #(
        .DATA_WIDTH(DATA_WIDTH)
    )
    uart_inst_pmu(
        .clk(clk),
        .rst(rst),
        .prescale (preescalar_data_rate),
        .s_axis_tdata(uart_tx_axis_tdata),
        .s_axis_tvalid(uart_tx_axis_tvalid),
        .s_axis_tready(uart_tx_axis_tready),

        .m_axis_tdata(uart_rx_axis_tdata),
        .m_axis_tvalid(uart_rx_axis_tvalid),
        .m_axis_tready(uart_rx_axis_tready),
        .rxd(rxd_pmu),
        .txd(txd_pmu),
        .tx_busy(),
        .rx_busy(),
        .rx_overrun_error(),
        .rx_frame_error()
    );


    always @(posedge clk or posedge rst) begin
        if (rst) begin
            uart_tx_axis_tdata <= 0;
            uart_rx_axis_tready <= 0;
            uart_tx_axis_tvalid <= 0;
            data_size_actual <= 0; 
            send_data_register <= 0;
            sending_data <= 0;
            pmu_register <= 0;
            input_data <= 0;
            valid_pmu_register <= 1'b0;
        end
        else begin
                if (uart_tx_axis_tvalid) begin


                uart_rx_axis_tready <= 0;

                if (uart_tx_axis_tready) begin
                    uart_tx_axis_tvalid <= 0;
                end
            end

            else if (sending_data) begin

                valid_pmu_register <= 1'b0;
                if (data_size_actual == 3'b000)begin

                    send_data_register <= 0;
                    sending_data <= 0;
                    uart_tx_axis_tvalid <= 0;
                end
                else begin

                    data_size_actual <= data_size_actual - 1'b1;

                    uart_tx_axis_tvalid <= 1'b1;

                    uart_tx_axis_tdata <= send_data_register[DATA_WIDTH-1: 0];

                    send_data_register <= send_data_register >> DATA_WIDTH;
                end
            end

            if (valid_value) begin

                valid_pmu_register <= 1'b0;

                sending_data <= 1'b1;

                uart_tx_axis_tvalid <= 0;


                send_data_register[7: 0] <= {4'h3,pmu_value[7: 4]} ;

                send_data_register[(COUNTERSIZE * 2)-1: (COUNTERSIZE)] <=   {4'h3,pmu_value[3: 0]};

                send_data_register[(COUNTERSIZE * 3)-1: (COUNTERSIZE * 2)] <= LINEFEED;
                send_data_register[(COUNTERSIZE * 4)-1: (COUNTERSIZE * 3)] <= NEWLINE;
                data_size_actual <= 3'h4;
            end
            else begin

                uart_rx_axis_tready <= 1;
                valid_pmu_register <= 1'b0;
                if (uart_rx_axis_tvalid) begin



                    uart_rx_axis_tready <= ~uart_rx_axis_tready;

                    input_data <= input_data << SYMBOL_WITH;
                    input_data [SYMBOL_WITH-1: 0] <= uart_rx_axis_tdata[SYMBOL_WITH-1:0];

                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)
                    begin
                        valid_pmu_register <= 1'b1;
                        pmu_register <= input_data;
                        input_data <= 0;
                        
                    end
                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin
                        input_data <= 0;
                    end
                    else begin
                        valid_pmu_register <= 1'b0;
                    end
                    
                end
            end
        end
    end

endmodule