data/full_repos/permissive/493441306/Verilog Language/modules_hierarchy/00_module.v
1: b'%Error: Cannot find file containing module: Language/modules_hierarchy,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             Language/modules_hierarchy,data/full_repos/permissive/493441306\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/modules_hierarchy/00_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( input a, input b, output out );
    
    mod_a instance1( .out(out), .in1(a), .in2(b) );

endmodule
module top_module ( input a, input b, output out );

    
    mod_a instance1( .out(out), .in1(a), .in2(b) );

endmodule