data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_explicit_mem/cachelib/v_rtl/dut_Add_3U_1_4.v
data/verilator_xmls/41949877-e59f-4844-9692-78a5c2a119a9.xml
module dut_Add_3U_1_4 (
	in2,
	in1,
	out1
	);
input [2:0] in2,
	in1;
output [2:0] out1;
wire [2:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_3U_1_4 (
	in2,
	in1,
	out1
	);

input [2:0] in2,
	in1;
output [2:0] out1;
wire [2:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule