data/full_repos/permissive/524567962/designs/SequenceDetector/seq_detector.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/524567962/designs/SequenceDetector/seq_detector.sv:18: Operator ENUMITEM \'S0\' expects 2 bits on the Enum value, but Enum value\'s CONST \'3\'h0\' generates 3 bits.\n  {S0=3\'b00, S1=3\'b01, S2=3\'b10, S3=3\'b11} state_type;\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/524567962/designs/SequenceDetector/seq_detector.sv:18: Operator ENUMITEM \'S1\' expects 2 bits on the Enum value, but Enum value\'s CONST \'3\'h1\' generates 3 bits.\n  {S0=3\'b00, S1=3\'b01, S2=3\'b10, S3=3\'b11} state_type;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/524567962/designs/SequenceDetector/seq_detector.sv:18: Operator ENUMITEM \'S2\' expects 2 bits on the Enum value, but Enum value\'s CONST \'3\'h2\' generates 3 bits.\n  {S0=3\'b00, S1=3\'b01, S2=3\'b10, S3=3\'b11} state_type;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/524567962/designs/SequenceDetector/seq_detector.sv:18: Operator ENUMITEM \'S3\' expects 2 bits on the Enum value, but Enum value\'s CONST \'3\'h3\' generates 3 bits.\n  {S0=3\'b00, S1=3\'b01, S2=3\'b10, S3=3\'b11} state_type;\n                                 ^~\n%Error: Exiting due to 4 warning(s)\n'
module seq_detector(
  input  logic d, clk, reset,

  output logic y
);


  typedef enum logic [1:0]
  {S0=3'b00, S1=3'b01, S2=3'b10, S3=3'b11} state_type;


  state_type CURRENT_STATE, NEXT_STATE;



  always_ff @(posedge clk, posedge reset)
	begin
	  if(reset)
      CURRENT_STATE <= S0;
	  else
      CURRENT_STATE <= NEXT_STATE;
  end

  

  always_comb
  begin

    NEXT_STATE = S0;


    case(CURRENT_STATE)
      S0:
      begin
        NEXT_STATE = (d==1'b0) ? S1 : S0;
      end

      S1:
      begin
        NEXT_STATE = (d==1'b1) ? S2 : S1;
      end
          
      S2:
      begin
        NEXT_STATE = (d==1'b1) ? S3 : S1;
      end

      S3:
      begin
        NEXT_STATE = (d==1'b1) ? S0 : S1;
      end

	    default:
      begin
        NEXT_STATE = S0;
	  	end

    endcase

  end

  assign y = (CURRENT_STATE == S3) & (d == 1'b1);

endmodule
module seq_detector(
  input  logic d, clk, reset,

  output logic y
);



  typedef enum logic [1:0]
  {S0=3'b00, S1=3'b01, S2=3'b10, S3=3'b11} state_type;


  state_type CURRENT_STATE, NEXT_STATE;



  always_ff @(posedge clk, posedge reset)
	begin
	  if(reset)
      CURRENT_STATE <= S0;
	  else
      CURRENT_STATE <= NEXT_STATE;
  end

  

  always_comb
  begin

    NEXT_STATE = S0;


    case(CURRENT_STATE)
      S0:
      begin
        NEXT_STATE = (d==1'b0) ? S1 : S0;
      end

      S1:
      begin
        NEXT_STATE = (d==1'b1) ? S2 : S1;
      end
          
      S2:
      begin
        NEXT_STATE = (d==1'b1) ? S3 : S1;
      end

      S3:
      begin
        NEXT_STATE = (d==1'b1) ? S0 : S1;
      end

	    default:
      begin
        NEXT_STATE = S0;
	  	end

    endcase

  end

  assign y = (CURRENT_STATE == S3) & (d == 1'b1);

endmodule