data/full_repos/permissive/506245779/CU_SelectionSort.v
1: b'%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:17: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'next_state\' generates 2 bits.\n                                                                          : ... In instance CU_SelectionSort\n  present_state = (rst == 1) ? IDLE : next_state;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:17: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n  present_state = (rst == 1) ? IDLE : next_state;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:28: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n    next_state = (run == 1) ? LOAD : IDLE;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:33: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n    next_state = (end_load == 1) ? ANCHOR : LOAD;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:38: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n    next_state = (hit_i == 1) ? SHOW : FINDMIN;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:44: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n    next_state = (hit_j == 1) ? ANCHOR : FINDMIN;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:49: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 3 bits.\n                                                                          : ... In instance CU_SelectionSort\n    next_state = (end_show == 1) ? IDLE : SHOW;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:23: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'present_state\' generates 2 bits.\n                                                                          : ... In instance CU_SelectionSort\n  case(present_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/506245779/CU_SelectionSort.v:57: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'present_state\' generates 2 bits.\n                                                                          : ... In instance CU_SelectionSort\n  PS = present_state;\n     ^\n%Error: Exiting due to 9 warning(s)\n'
module CU_SelectionSort (
	input clk, rst, run, end_load, hit_i, hit_j, end_show,
	output reg swap,
	output reg [2:0] PS
);

	localparam IDLE = 3'b000,
					LOAD = 3'b001,
					ANCHOR = 3'b010,
					FINDMIN = 3'b011,
					SHOW = 3'b100;
	
	reg [1:0] present_state, next_state;
	
	always @ (posedge clk or posedge rst)
	begin
		present_state = (rst == 1) ? IDLE : next_state;
	end
	
	always @ (*)
	begin
		next_state = present_state;
		case(present_state)
		

			IDLE: begin
				swap = 0;
				next_state = (run == 1) ? LOAD : IDLE;
			end
			

			LOAD: begin
				next_state = (end_load == 1) ? ANCHOR : LOAD;
			end
			

			ANCHOR: begin
				next_state = (hit_i == 1) ? SHOW : FINDMIN;
			end
			

			FINDMIN: begin
				swap = (hit_j == 1) ? 1 : 0;
				next_state = (hit_j == 1) ? ANCHOR : FINDMIN;
			end
			

			SHOW: begin
				next_state = (end_show == 1) ? IDLE : SHOW;
			end
			
			default: begin
				next_state = present_state;
			end
			
		endcase
		PS = present_state;
	end

endmodule
module CU_SelectionSort (
	input clk, rst, run, end_load, hit_i, hit_j, end_show,
	output reg swap,
	output reg [2:0] PS
);


	localparam IDLE = 3'b000,
					LOAD = 3'b001,
					ANCHOR = 3'b010,
					FINDMIN = 3'b011,
					SHOW = 3'b100;
	
	reg [1:0] present_state, next_state;
	
	always @ (posedge clk or posedge rst)
	begin
		present_state = (rst == 1) ? IDLE : next_state;
	end
	
	always @ (*)
	begin
		next_state = present_state;
		case(present_state)
		

			IDLE: begin
				swap = 0;
				next_state = (run == 1) ? LOAD : IDLE;
			end
			

			LOAD: begin
				next_state = (end_load == 1) ? ANCHOR : LOAD;
			end
			

			ANCHOR: begin
				next_state = (hit_i == 1) ? SHOW : FINDMIN;
			end
			

			FINDMIN: begin
				swap = (hit_j == 1) ? 1 : 0;
				next_state = (hit_j == 1) ? ANCHOR : FINDMIN;
			end
			

			SHOW: begin
				next_state = (end_show == 1) ? IDLE : SHOW;
			end
			
			default: begin
				next_state = present_state;
			end
			
		endcase
		PS = present_state;
	end

endmodule