data/full_repos/permissive/418749135/rsff.v
data/verilator_xmls/5e752ab3-5ccb-448d-92d3-07481b9239c5.xml
module Main(input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );
    reg M,N;

always @(posedge clk) begin
  M <= !(S & clk);
  N <= !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);

endmodule
module Main(input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );

    reg M,N;

always @(posedge clk) begin
  M <= !(S & clk);
  N <= !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);

endmodule