data/full_repos/permissive/523043017/Verilog microcontroller/RAM_unit.v
1: b'%Error: Cannot find file containing module: microcontroller,data/full_repos/permissive/523043017\n        ... Looked in:\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.v\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.sv\n             microcontroller,data/full_repos/permissive/523043017\n             microcontroller,data/full_repos/permissive/523043017.v\n             microcontroller,data/full_repos/permissive/523043017.sv\n             obj_dir/microcontroller,data/full_repos/permissive/523043017\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.v\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/523043017/Verilog\n%Error: Cannot find file containing module: microcontroller/RAM_unit.v\n%Error: Exiting due to 3 error(s)\n'
module RAM_unit(
		input wire [7:0] A,
		output [7:0] D,
		input [7:0] Dd,
		input wire wr,
		output [7:0] PORTA,
		output [7:0] PORTB,
		output [7:0] PORTC,
		output [7:0] PORTD
	);
	reg [7:0] ram[255:0];
	initial
	begin
		$readmemh("RAM.dat", ram);
	end
	assign D = ram[A];
	
	always @(posedge wr)
		ram[A] <= Dd;
	
	assign PORTA = ram[8'hff];
	assign PORTB = ram[8'hfe];
	assign PORTC = ram[8'hfd];
	assign PORTD = ram[8'hfc];
	
endmodule
module RAM_unit(
		input wire [7:0] A,
		output [7:0] D,
		input [7:0] Dd,
		input wire wr,
		output [7:0] PORTA,
		output [7:0] PORTB,
		output [7:0] PORTC,
		output [7:0] PORTD
	);

	reg [7:0] ram[255:0];
	initial
	begin
		$readmemh("RAM.dat", ram);
	end
	assign D = ram[A];
	
	always @(posedge wr)
		ram[A] <= Dd;
	
	assign PORTA = ram[8'hff];
	assign PORTB = ram[8'hfe];
	assign PORTC = ram[8'hfd];
	assign PORTD = ram[8'hfc];
	
endmodule