data/full_repos/permissive/492363527/StateMachine.v
data/verilator_xmls/37fd00fc-6582-440a-a1c6-daa910e575c8.xml
module StateMachine(x,clk,ma,Z);
	input x, clk, ma;
	output reg Z;
	
	initial
    begin
		Z = 0;
    end
	
	always@(posedge clk) begin
    Z = (x & ~Z) | (~ma & Z);
	end
	
endmodule
module StateMachine(x,clk,ma,Z);

	input x, clk, ma;
	output reg Z;
	
	initial
    begin
		Z = 0;
    end
	
	always@(posedge clk) begin
    Z = (x & ~Z) | (~ma & Z);
	end
	
endmodule