data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:205: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'Synthesis_Harness_Input\'\nmodule Synthesis_Harness_Input #(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'Synthesis_Harness_Output\'\nmodule Synthesis_Harness_Output #(\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:177: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                               : ... In instance Synthesis_Harness_Input\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Warning-LITENDIAN: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:75: Little bit endian vector: MSB < LSB of bit range: -1:0\n    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0\n              ^\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:75: Operator VAR \'RESET_VALUES\' expects 2 bits on the Initial value, but Initial value\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesis_Harness_Input.shift_bit_into_word\n    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:216: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                               : ... In instance Synthesis_Harness_Output\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:88: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                              : ... In instance Synthesis_Harness_Output.word_register\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module Synthesis_Harness_Input #(
    parameter WORD_WIDTH = 0
)
(
    input clock,
    input clear,
    input bit_in,
    input bit_in_valid,
    output [WORD_WIDTH-1:0] word_out
);

localparam WORD_ZERO = {WORD_WIDTH{1'b0}};


(* IOB = "false" *)
(* DONT_TOUCH = "true" *)


(* useioff = 0 *)
(* preserve *)

Register_Pipeline #(
    .WORD_WIDTH     (1),
    .PIPE_DEPTH     (WORD_WIDTH),
    .RESET_VALUES   (WORD_ZERO)
) shift_bit_into_word (
    .clock          (clock),
    .clock_enable   (bit_in_valid),
    .clear          (clear),
    .parallel_load  (1'b0),
    .parallel_in    (WORD_ZERO),
    .parallel_out   (word_out),
    .pipe_in        (bit_in),
    .pipe_out       ()
);

endmodule
module Synthesis_Harness_Input #(
    parameter WORD_WIDTH = 0
)
(
    input clock,
    input clear,
    input bit_in,
    input bit_in_valid,
    output [WORD_WIDTH-1:0] word_out
);


localparam WORD_ZERO = {WORD_WIDTH{1'b0}};


(* IOB = "false" *)
(* DONT_TOUCH = "true" *)


(* useioff = 0 *)
(* preserve *)

Register_Pipeline #(
    .WORD_WIDTH     (1),
    .PIPE_DEPTH     (WORD_WIDTH),
    .RESET_VALUES   (WORD_ZERO)
) shift_bit_into_word (
    .clock          (clock),
    .clock_enable   (bit_in_valid),
    .clear          (clear),
    .parallel_load  (1'b0),
    .parallel_in    (WORD_ZERO),
    .parallel_out   (word_out),
    .pipe_in        (bit_in),
    .pipe_out       ()
);

endmodule