data/full_repos/permissive/514217463/core/rtl/examine_next.v
data/verilator_xmls/2ad8b206-65de-41d1-a5d7-60b41b39888c.xml
module examine_next(
  input clk,
  input reset,
  input rd,
  input examine,
  output reg [7:0] data_out,
  output examine_latch
);

  reg [2:0] state = 3'b000;
  reg prev_rd = 1'b0;
  reg en_lt = 1'b0;
  
  always @(posedge clk)
    begin
      if (reset) begin 
        en_lt <= 1'b0; 
      end  
      else if (examine) 
      begin 
        state <= 3'b000; 
        en_lt <= 1'b1; 
      end
      else begin
     	  if (rd && prev_rd==1'b0)
		    begin
          case (state)
          3'b000 : begin
              en_lt <= 1'b1;
              state <= 3'b101;
              data_out <= 8'b00000000;
				    end
          3'b101 : begin						
              state <= 3'b101;
     		      en_lt <= 1'b0;
            end
          endcase
		    end
		  prev_rd = rd;  
      end
    end
	  assign examine_latch = en_lt;
endmodule
module examine_next(
  input clk,
  input reset,
  input rd,
  input examine,
  output reg [7:0] data_out,
  output examine_latch
);


  reg [2:0] state = 3'b000;
  reg prev_rd = 1'b0;
  reg en_lt = 1'b0;
  
  always @(posedge clk)
    begin
      if (reset) begin 
        en_lt <= 1'b0; 
      end  
      else if (examine) 
      begin 
        state <= 3'b000; 
        en_lt <= 1'b1; 
      end
      else begin
     	  if (rd && prev_rd==1'b0)
		    begin
          case (state)
          3'b000 : begin
              en_lt <= 1'b1;
              state <= 3'b101;
              data_out <= 8'b00000000;
				    end
          3'b101 : begin						
              state <= 3'b101;
     		      en_lt <= 1'b0;
            end
          endcase
		    end
		  prev_rd = rd;  
      end
    end
	  assign examine_latch = en_lt;
endmodule