data/full_repos/permissive/496508301/Lesson10/UART_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #17       res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #3000000  $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:67: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson10/UART_top.v:82: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("UART_top_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson10/UART_top.v:83: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(clk, res, RX, TX);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_top(
            clk,
            res,
            RX,
            TX
);
input       clk;
input       res;
input       RX;
output      TX;

wire[7:0]   din_pro;
wire        en_din_pro;
wire[7:0]   dout_pro;
wire        en_dout_pro;
wire        rdy;
UART_RX UART_RX(
            .clk(clk),
            .res(res),
            .RX(RX),
            .data_out(din_pro),
            .en_data_out(en_din_pro)
);
UART_TX UART_TX(
            .clk(clk),
            .res(res),
            .TX(TX),
            .data_in(dout_pro),
            .en_data_in(en_dout_pro),
            .rdy(rdy)
);
cmd_pro cmd_pro(
            .clk(clk), 
            .res(res), 
            .din_pro(din_pro), 
            .en_din_pro(en_din_pro), 
            .dout_pro(dout_pro), 
            .en_dout_pro(en_dout_pro),
            .rdy(rdy)
);
endmodule
module UART_top(
            clk,
            res,
            RX,
            TX
);

input       clk;
input       res;
input       RX;
output      TX;

wire[7:0]   din_pro;
wire        en_din_pro;
wire[7:0]   dout_pro;
wire        en_dout_pro;
wire        rdy;
UART_RX UART_RX(
            .clk(clk),
            .res(res),
            .RX(RX),
            .data_out(din_pro),
            .en_data_out(en_din_pro)
);
UART_TX UART_TX(
            .clk(clk),
            .res(res),
            .TX(TX),
            .data_in(dout_pro),
            .en_data_in(en_dout_pro),
            .rdy(rdy)
);
cmd_pro cmd_pro(
            .clk(clk), 
            .res(res), 
            .din_pro(din_pro), 
            .en_din_pro(en_din_pro), 
            .dout_pro(dout_pro), 
            .en_dout_pro(en_dout_pro),
            .rdy(rdy)
);
endmodule