data/full_repos/permissive/487368624/Lab M/cpu.v
1: b'%Error: Cannot find file containing module: M,data/full_repos/permissive/487368624\n        ... Looked in:\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.v\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.sv\n             M,data/full_repos/permissive/487368624\n             M,data/full_repos/permissive/487368624.v\n             M,data/full_repos/permissive/487368624.sv\n             obj_dir/M,data/full_repos/permissive/487368624\n             obj_dir/M,data/full_repos/permissive/487368624.v\n             obj_dir/M,data/full_repos/permissive/487368624.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/487368624/Lab\n%Error: Cannot find file containing module: M/cpu.v\n%Error: Exiting due to 3 error(s)\n'
module yChip(ins, rd2, wb, entryPoint, INT, clk);
    output [31:0] ins, rd2, wb;
    input [31:0] entryPoint;
    input INT, clk;

    wire [31:0] wd, rd1, imm, PCp4, jTarget, exeOut, branch, memOut, PCin, PC;
    wire zero;
    wire [6:0] opCode;
    wire isStype, isRtype, isItype, isLw, isjump, isbranch;
    wire RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg;
    wire [2:0] op, funct3;
    wire [1:0] ALUop;

    yIF myIF(ins, PC, PCp4, PCin, clk);
    yID myID(rd1, rd2, imm, jTarget, branch, ins, wd, RegWrite, clk);
    yEX myEx(exeOut, zero, rd1, rd2, imm, op, ALUSrc);
    yDM myDM(memOut, exeOut, rd2, clk, MemRead, MemWrite);
    yWB myWB(wb, exeOut, memOut, Mem2Reg);
    yPC myPC(PCin, PC, PCp4, INT, entryPoint, branch, jTarget, zero, isbranch, isjump);
    assign opCode = ins[6:0];
    yC1 myC1(isStype, isRtype, isItype, isLw, isjump, isbranch, opCode);
    yC2 myC2(RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg, 
              isStype, isRtype, isItype, isLw, isjump, isbranch);
    yC3 myC3(ALUop, isRtype, isbranch);
    assign funct3=ins[14:12];
    yC4 myC4(op, ALUop, funct3);
    assign wd = wb; 
endmodule
module yChip(ins, rd2, wb, entryPoint, INT, clk);

    output [31:0] ins, rd2, wb;
    input [31:0] entryPoint;
    input INT, clk;

    wire [31:0] wd, rd1, imm, PCp4, jTarget, exeOut, branch, memOut, PCin, PC;
    wire zero;
    wire [6:0] opCode;
    wire isStype, isRtype, isItype, isLw, isjump, isbranch;
    wire RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg;
    wire [2:0] op, funct3;
    wire [1:0] ALUop;

    yIF myIF(ins, PC, PCp4, PCin, clk);
    yID myID(rd1, rd2, imm, jTarget, branch, ins, wd, RegWrite, clk);
    yEX myEx(exeOut, zero, rd1, rd2, imm, op, ALUSrc);
    yDM myDM(memOut, exeOut, rd2, clk, MemRead, MemWrite);
    yWB myWB(wb, exeOut, memOut, Mem2Reg);
    yPC myPC(PCin, PC, PCp4, INT, entryPoint, branch, jTarget, zero, isbranch, isjump);
    assign opCode = ins[6:0];
    yC1 myC1(isStype, isRtype, isItype, isLw, isjump, isbranch, opCode);
    yC2 myC2(RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg, 
              isStype, isRtype, isItype, isLw, isjump, isbranch);
    yC3 myC3(ALUop, isRtype, isbranch);
    assign funct3=ins[14:12];
    yC4 myC4(op, ALUop, funct3);
    assign wd = wb; 
endmodule