data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:174: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX.sv\n             MUX\n             MUX.v\n             MUX.sv\n             obj_dir/MUX\n             obj_dir/MUX.v\n             obj_dir/MUX.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:186: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:199: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:214: Cannot find file containing module: 'ADD'\n ADD \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:228: Cannot find file containing module: 'COMP'\n COMP\n ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:239: Cannot find file containing module: 'SUB'\n SUB \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:251: Cannot find file containing module: 'COMP'\n COMP\n ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:264: Cannot find file containing module: 'SUB'\n SUB \n ^~~\n%Error: Exiting due to 8 error(s)\n"
module modmult_step
#(
	parameter N 	= 4
)
(
	xregN_1,
	y,
	n,
	zin,
	zout
);
	input 	xregN_1;
	input 	[N-1:0]	y;
	input 	[N-1:0]	n;
	
	input 			[N+1:0]	zin;
	output[N+1:0]	zout;



	wire 	[N+1:0]	y_ext;
	wire 	[N+1:0]	n_ext;

	wire 	[N+1:0]	z1, z2, z3;
	wire 	[N+1:0]	w1, w2, w3;


	wire c1, c2, c2p;


	assign y_ext = {2'b0, y};
	assign n_ext = {2'b0, n};



	assign z1 = {zin[N:0], 1'b0};






	

	MUX 
	#(
		.N(N+2)
	)
	MUX_1
	(
		.A(y_ext),
		.B({(N+2){1'b0}}),
		.S(xregN_1),
		.O(w1)
	);	

	MUX 
	#(
		.N(N+2)
	)
	MUX_2
	(
		.A(n_ext),
		.B({(N+2){1'b0}}),
		.S(c1),
		.O(w2)
	);	


	MUX 
	#(
		.N(N+2)
	)
	MUX_3
	(
		.A(n_ext),
		.B({(N+2){1'b0}}),
		.S(c2p),
		.O(w3)
	);	




	ADD 
	#(
		.N(N+2)
	)
	ADD_1
	(
		.A(z1),
		.B(w1),
		.CI(1'b0),
		.S(z2),
		.CO()
	);
	
	
	COMP
	#(
		.N(N+2)
	)
	COMP_1
	(
		.A(z2),
		.B(n_ext), 
		.O(c1)
	);

	SUB 
	#(
		.N(N+2)
	)
	SUB_1
	(
		.A(z2),
		.B(w2),
		.S(z3),
		.CO()
	);

	COMP
	#(
		.N(N+2)
	)
	COMP_2
	(
		.A(n_ext),
		.B(z3), 
		.O(c2)
	);

	assign c2p = ~c2;

	SUB 
	#(
		.N(N+2)
	)
	SUB_2
	(
		.A(z3),
		.B(w3),
		.S(zout),
		.CO()
	);




endmodule
module modmult_step
#(
	parameter N 	= 4
)
(
	xregN_1,
	y,
	n,
	zin,
	zout
);

	input 	xregN_1;
	input 	[N-1:0]	y;
	input 	[N-1:0]	n;
	
	input 			[N+1:0]	zin;
	output[N+1:0]	zout;



	wire 	[N+1:0]	y_ext;
	wire 	[N+1:0]	n_ext;

	wire 	[N+1:0]	z1, z2, z3;
	wire 	[N+1:0]	w1, w2, w3;


	wire c1, c2, c2p;


	assign y_ext = {2'b0, y};
	assign n_ext = {2'b0, n};



	assign z1 = {zin[N:0], 1'b0};






	

	MUX 
	#(
		.N(N+2)
	)
	MUX_1
	(
		.A(y_ext),
		.B({(N+2){1'b0}}),
		.S(xregN_1),
		.O(w1)
	);	

	MUX 
	#(
		.N(N+2)
	)
	MUX_2
	(
		.A(n_ext),
		.B({(N+2){1'b0}}),
		.S(c1),
		.O(w2)
	);	


	MUX 
	#(
		.N(N+2)
	)
	MUX_3
	(
		.A(n_ext),
		.B({(N+2){1'b0}}),
		.S(c2p),
		.O(w3)
	);	




	ADD 
	#(
		.N(N+2)
	)
	ADD_1
	(
		.A(z1),
		.B(w1),
		.CI(1'b0),
		.S(z2),
		.CO()
	);
	
	
	COMP
	#(
		.N(N+2)
	)
	COMP_1
	(
		.A(z2),
		.B(n_ext), 
		.O(c1)
	);

	SUB 
	#(
		.N(N+2)
	)
	SUB_1
	(
		.A(z2),
		.B(w2),
		.S(z3),
		.CO()
	);

	COMP
	#(
		.N(N+2)
	)
	COMP_2
	(
		.A(n_ext),
		.B(z3), 
		.O(c2)
	);

	assign c2p = ~c2;

	SUB 
	#(
		.N(N+2)
	)
	SUB_2
	(
		.A(z3),
		.B(w3),
		.S(zout),
		.CO()
	);




endmodule