data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedSubTester/sbt/IntervalChainedSubTester.v
data/verilator_xmls/342a9984-3ecc-4b50-b67c-460b51959768.xml
module IntervalChainedSubTester(
  input   clock,
  input   reset
);
  wire [6:0] _GEN_0 = 6'sh11 - 6'sh2;
  wire [4:0] _intervalResult1_T = _GEN_0[4:0];
  wire [5:0] _GEN_2 = $signed(_intervalResult1_T) - 5'sh2;
  wire [4:0] _intervalResult1_T_1 = _GEN_2[4:0];
  wire [5:0] _GEN_4 = $signed(_intervalResult1_T_1) - 5'sh2;
  wire [4:0] _intervalResult1_T_2 = _GEN_4[4:0];
  wire [5:0] _GEN_6 = $signed(_intervalResult1_T_2) - 5'sh2;
  wire [4:0] _intervalResult1_T_3 = _GEN_6[4:0];
  wire [5:0] _GEN_8 = $signed(_intervalResult1_T_3) - 5'sh2;
  wire [3:0] _intervalResult1_T_4 = _GEN_8[3:0];
  wire [4:0] _GEN_10 = $signed(_intervalResult1_T_4) - 4'sh2;
  wire [3:0] intervalResult1 = _GEN_10[3:0];
  wire [5:0] _uIntResult_T = 5'h11 - 5'h2;
  wire [6:0] _uIntResult_T_2 = _uIntResult_T - 6'h2;
  wire [7:0] _uIntResult_T_4 = _uIntResult_T_2 - 7'h2;
  wire [8:0] _uIntResult_T_6 = _uIntResult_T_4 - 8'h2;
  wire [9:0] _uIntResult_T_8 = _uIntResult_T_6 - 9'h2;
  wire [10:0] uIntResult = _uIntResult_T_8 - 10'h2;
  wire [7:0] _fixedResult_T_1 = $signed(_GEN_0) - 7'sh2;
  wire [8:0] _fixedResult_T_2 = $signed(_fixedResult_T_1) - 8'sh2;
  wire [9:0] _fixedResult_T_3 = $signed(_fixedResult_T_2) - 9'sh2;
  wire [10:0] _fixedResult_T_4 = $signed(_fixedResult_T_3) - 10'sh2;
  wire [11:0] fixedResult = $signed(_fixedResult_T_4) - 11'sh2;
  wire [11:0] _T_8 = $signed(_fixedResult_T_4) - 11'sh2;
  wire  _T_16 = ~($signed(intervalResult1) == 4'sh5 | reset);
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~(uIntResult == 11'h5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:403 assert(uIntResult === 5.U)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(uIntResult == 11'h5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~($signed(fixedResult) == 12'sh5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:404 assert(sIntResult === 5.S)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~($signed(fixedResult) == 12'sh5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~(_T_8 == 12'h5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:405 assert(fixedResult.asUInt === 5.U)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_8 == 12'h5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~($signed(intervalResult1) == 4'sh5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:406 assert(intervalResult1 === 5.I)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~($signed(intervalResult1) == 4'sh5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_16) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:407 assert(intervalResult2 === 5.I)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_16) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
endmodule
module IntervalChainedSubTester(
  input   clock,
  input   reset
);

  wire [6:0] _GEN_0 = 6'sh11 - 6'sh2;
  wire [4:0] _intervalResult1_T = _GEN_0[4:0];
  wire [5:0] _GEN_2 = $signed(_intervalResult1_T) - 5'sh2;
  wire [4:0] _intervalResult1_T_1 = _GEN_2[4:0];
  wire [5:0] _GEN_4 = $signed(_intervalResult1_T_1) - 5'sh2;
  wire [4:0] _intervalResult1_T_2 = _GEN_4[4:0];
  wire [5:0] _GEN_6 = $signed(_intervalResult1_T_2) - 5'sh2;
  wire [4:0] _intervalResult1_T_3 = _GEN_6[4:0];
  wire [5:0] _GEN_8 = $signed(_intervalResult1_T_3) - 5'sh2;
  wire [3:0] _intervalResult1_T_4 = _GEN_8[3:0];
  wire [4:0] _GEN_10 = $signed(_intervalResult1_T_4) - 4'sh2;
  wire [3:0] intervalResult1 = _GEN_10[3:0];
  wire [5:0] _uIntResult_T = 5'h11 - 5'h2;
  wire [6:0] _uIntResult_T_2 = _uIntResult_T - 6'h2;
  wire [7:0] _uIntResult_T_4 = _uIntResult_T_2 - 7'h2;
  wire [8:0] _uIntResult_T_6 = _uIntResult_T_4 - 8'h2;
  wire [9:0] _uIntResult_T_8 = _uIntResult_T_6 - 9'h2;
  wire [10:0] uIntResult = _uIntResult_T_8 - 10'h2;
  wire [7:0] _fixedResult_T_1 = $signed(_GEN_0) - 7'sh2;
  wire [8:0] _fixedResult_T_2 = $signed(_fixedResult_T_1) - 8'sh2;
  wire [9:0] _fixedResult_T_3 = $signed(_fixedResult_T_2) - 9'sh2;
  wire [10:0] _fixedResult_T_4 = $signed(_fixedResult_T_3) - 10'sh2;
  wire [11:0] fixedResult = $signed(_fixedResult_T_4) - 11'sh2;
  wire [11:0] _T_8 = $signed(_fixedResult_T_4) - 11'sh2;
  wire  _T_16 = ~($signed(intervalResult1) == 4'sh5 | reset);
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~(uIntResult == 11'h5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:403 assert(uIntResult === 5.U)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(uIntResult == 11'h5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~($signed(fixedResult) == 12'sh5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:404 assert(sIntResult === 5.S)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~($signed(fixedResult) == 12'sh5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~(_T_8 == 12'h5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:405 assert(fixedResult.asUInt === 5.U)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_8 == 12'h5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~($signed(intervalResult1) == 4'sh5 | reset)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:406 assert(intervalResult1 === 5.I)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~($signed(intervalResult1) == 4'sh5 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_16) begin
          $fwrite(32'h80000002,"Assertion failed\n    at IntervalSpec.scala:407 assert(intervalResult2 === 5.I)\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_16) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
endmodule