data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Design a Moore FSM.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Design\n%Error: Cannot find file containing module: a\n%Error: Cannot find file containing module: Moore\n%Error: Cannot find file containing module: FSM.v\n%Error: Exiting due to 8 error(s)\n'
module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [2:0] current, next; 
    

    parameter below_s1 = 0, s2s1_nom = 1, s3s2_nom = 2, above_s3 = 3, s3s2_sup = 4, s2s1_sup = 5;


    always@(*)begin
       case(current)
           below_s1: if(s[3]==0 && s[2] == 0 && s[1] == 1)
               				next <= s2s1_nom;
           			 else 
                         	next <= below_s1;
           s2s1_nom: if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_nom;
          			 else if(s[3]==0 && s[2] == 0 && s[1] == 0)
               				next <= below_s1;
           			 else 
                         	next <= s2s1_nom;
           s3s2_nom: if(s[3]==1 && s[2] == 1 && s[1] == 1)
               				next <= above_s3;
           			 else if(s[3]==0 && s[2] == 0 && s[1] == 1)
                            next <= s2s1_sup;
           			 else 
                         	next <= s3s2_nom;
           above_s3: if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_sup;
           			 else
                         	next<= above_s3;
           s3s2_sup: if(s[3]==0 && s[2] == 0 && s[1] == 1)
               				next <= s2s1_sup;
           			 else if(s[3]==1 && s[2] == 1 && s[1] == 1)
               				next <= above_s3;
           			 else
                         	next<= s3s2_sup;
           s2s1_sup: if(s[3]==0 && s[2] == 0 && s[1] == 0)
               				next <= below_s1;
           			 else if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_nom;
           			 else
                         	next<= s2s1_sup;
           default: next <= below_s1;
       endcase      
    end

    always@(posedge clk)begin
        if(reset) begin
       		current <= below_s1;
        end
        else 
            current <= next;
    end
        

    assign dfr = (current == below_s1 || current == s2s1_sup || current == s3s2_sup);
    assign fr1 = (current != above_s3);
    assign fr2 = (current == below_s1 || current == s2s1_nom || current == s2s1_sup);
    assign fr3 = (current == below_s1);
endmodule
module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
);
 
    reg [2:0] current, next; 
    

    parameter below_s1 = 0, s2s1_nom = 1, s3s2_nom = 2, above_s3 = 3, s3s2_sup = 4, s2s1_sup = 5;


    always@(*)begin
       case(current)
           below_s1: if(s[3]==0 && s[2] == 0 && s[1] == 1)
               				next <= s2s1_nom;
           			 else 
                         	next <= below_s1;
           s2s1_nom: if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_nom;
          			 else if(s[3]==0 && s[2] == 0 && s[1] == 0)
               				next <= below_s1;
           			 else 
                         	next <= s2s1_nom;
           s3s2_nom: if(s[3]==1 && s[2] == 1 && s[1] == 1)
               				next <= above_s3;
           			 else if(s[3]==0 && s[2] == 0 && s[1] == 1)
                            next <= s2s1_sup;
           			 else 
                         	next <= s3s2_nom;
           above_s3: if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_sup;
           			 else
                         	next<= above_s3;
           s3s2_sup: if(s[3]==0 && s[2] == 0 && s[1] == 1)
               				next <= s2s1_sup;
           			 else if(s[3]==1 && s[2] == 1 && s[1] == 1)
               				next <= above_s3;
           			 else
                         	next<= s3s2_sup;
           s2s1_sup: if(s[3]==0 && s[2] == 0 && s[1] == 0)
               				next <= below_s1;
           			 else if(s[3]==0 && s[2] == 1 && s[1] == 1)
               				next <= s3s2_nom;
           			 else
                         	next<= s2s1_sup;
           default: next <= below_s1;
       endcase      
    end

    always@(posedge clk)begin
        if(reset) begin
       		current <= below_s1;
        end
        else 
            current <= next;
    end
        

    assign dfr = (current == below_s1 || current == s2s1_sup || current == s3s2_sup);
    assign fr1 = (current != above_s3);
    assign fr2 = (current == below_s1 || current == s2s1_nom || current == s2s1_sup);
    assign fr3 = (current == below_s1);
endmodule