data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Register.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Register.v:45: Cannot find file containing module: 'Buffer16B'\n  Buffer16B buf0 (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B.sv\n             Buffer16B\n             Buffer16B.v\n             Buffer16B.sv\n             obj_dir/Buffer16B\n             obj_dir/Buffer16B.v\n             obj_dir/Buffer16B.sv\n%Error: Exiting due to 1 error(s)\n"
module SyzFETRegister3Out (
    input [15:0] dIn,
    input clockSig,
    input read,
    input write,
    input reset,
    output [15:0] dOut,
    output [15:0] dOut2,
    output [15:0] debugOut
  );

  reg [15:0] data = 16'h0000;
  wire [15:0] wOutput;
  

  assign dOut2[15:0] = data[15:0];
  

  assign debugOut[15:0] = data[15:0];
  

  wire [15:0] wBuf;
  Buffer16B buf0 (
    .dIn(dIn[15:0]),
    .dOut(wBuf[15:0])
  );
  

  always @ (negedge clockSig) begin
    if(reset) begin
      data[15:0] <= 16'h0000;
    end else begin
      if(write) begin
        data[15:0] <= wBuf[15:0];
      end
    end
  end
  

  assign wOutput[15:0] = (read) ? data[15:0] : 16'h0000;
  

  assign dOut[15:0] = wOutput[15:0];
  
  
endmodule
module SyzFETRegister3Out (
    input [15:0] dIn,
    input clockSig,
    input read,
    input write,
    input reset,
    output [15:0] dOut,
    output [15:0] dOut2,
    output [15:0] debugOut
  );


  reg [15:0] data = 16'h0000;
  wire [15:0] wOutput;
  

  assign dOut2[15:0] = data[15:0];
  

  assign debugOut[15:0] = data[15:0];
  

  wire [15:0] wBuf;
  Buffer16B buf0 (
    .dIn(dIn[15:0]),
    .dOut(wBuf[15:0])
  );
  

  always @ (negedge clockSig) begin
    if(reset) begin
      data[15:0] <= 16'h0000;
    end else begin
      if(write) begin
        data[15:0] <= wBuf[15:0];
      end
    end
  end
  

  assign wOutput[15:0] = (read) ? data[15:0] : 16'h0000;
  

  assign dOut[15:0] = wOutput[15:0];
  
  
endmodule