data/full_repos/permissive/460328193/ipa_proj_seq/pc_update.v
data/verilator_xmls/278c18b0-45db-4110-b25c-ba1188cefe5d.xml
module pc_update(PC,icode,Cnd,valC,valM,valP,clk);
input clk;
input [3:0]icode;
input Cnd;
input [63:0]valC;
input [63:0]valM;
input [63:0]valP;
output reg [63:0]PC;

reg [63:0]new_pc;
always @(*)
begin
	if(icode==4'h7 && Cnd==1'b1)
        new_pc<=valC;
	else if(icode==4'h8)
        new_pc<=valC;
	else if(icode==4'h9)
        new_pc<=valM;
	else
        new_pc<=valP;
    PC<=new_pc;
end

endmodule
module pc_update(PC,icode,Cnd,valC,valM,valP,clk);

input clk;
input [3:0]icode;
input Cnd;
input [63:0]valC;
input [63:0]valM;
input [63:0]valP;
output reg [63:0]PC;

reg [63:0]new_pc;
always @(*)
begin
	if(icode==4'h7 && Cnd==1'b1)
        new_pc<=valC;
	else if(icode==4'h8)
        new_pc<=valC;
	else if(icode==4'h9)
        new_pc<=valM;
	else
        new_pc<=valP;
    PC<=new_pc;
end

endmodule