data/full_repos/permissive/46132596/processor/SingleCycleDatapath/ControlUnit.v
data/verilator_xmls/bf5c1b05-16f6-41d2-92ab-471cb52fe0b1.xml
module ControlUnit(input[5:0] opcode,
		input[5:0] funct,
		output reg reg_dst,
		output reg reg_write,
		output reg[1:0] alu_src,
		output reg[3:0] alu_op,
		output reg branch,
		output reg mem_write,
		output reg mem_to_reg,
        	output reg zero_sign_ext,
		output reg mult_op,
		output reg mfhi,
		output reg mflo);

	always @(opcode, funct) begin
		


		reg_dst = 1'bx;
		reg_write = 1'bx;
		alu_src = 2'bxx;
		alu_op = 4'bxxxx;
		branch = 1'bx;
		mem_write = 1'bx;
		mem_to_reg = 1'bx;
		zero_sign_ext = 1'bx;

		mult_op = 1'b0;
		mfhi = 1'b0;
		mflo = 1'b0;


		case (opcode)


			6'h00: begin


				reg_dst = 1;
				reg_write = 1;
				alu_src = 0;
				branch = 0;
				mem_write = 0;
				mem_to_reg = 0;
			

				case (funct)


					6'h20: begin
						alu_op = 4'b0000;
						$display("\tInstruction 'add'");
					end


                   			 6'h21: begin
                   			     alu_op = 4'b0000;
                   			     $display("\tInstruction 'addu'");
                   			 end


					6'h22: begin
						alu_op = 4'b0001;
						$display("\tInstruction 'sub'");
					end


					6'h23: begin
						alu_op = 4'b0001;
						$display("\tInstruction 'subu'");
					end


					6'h24: begin
						alu_op = 4'b0010;
						$display("\tInstruction 'and'");
					end


                   			 6'h27: begin
                   			     alu_op = 4'b0100;
                   			     $display("\tInstruction 'nor'");
                   			 end


					6'h25: begin
						alu_op = 4'b0011;
						$display("\tInstruction 'or'");
					end


                   			 6'h26: begin
                   			     alu_op = 4'b0101;
                   			     $display("\tInstruction 'xor'");
                   			 end
                   			 

                   			 6'h0: begin
                   			     alu_op = 6;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'sll'");
                   			 end


                   			 6'h2: begin
                   			     alu_op = 7;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'srl'");
                   			 end


                   			 6'h3: begin
                   			     alu_op = 8;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'sra'");
                   			 end


                   			 6'h4: begin
                   			     alu_op = 6;
                   			     $display("\tInstruction 'sllv'");
                   			 end


                   			 6'h6: begin
                   			     alu_op = 7;
                   			     $display("\tInstruction 'srlv'");
                   			 end


                   			 6'h7: begin
                   			     alu_op = 8;
                   			     $display("\tInstruction 'srav'");
                   			 end


					6'h2a: begin
						alu_op = 4'b1001;
						$display("\tInstruction 'slt'");
					end


					6'h2b: begin
						alu_op = 4'b1010;
						$display("\tInstruction 'sltu'");
					end


					6'h18: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0010;
						$display("\tInstruction 'mult'");
					end


					6'h19: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0011;
						$display("\tInstruction 'multu'");
					end


					6'h1A: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0000;
						$display("\tInstruction 'div'");
					end


					6'h1B: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0001;
						$display("\tInstruction 'divu'");
					end


					6'h10: begin
						alu_op = 4'b1111;
						mfhi = 1;
						$display("\tInstruction 'mfhi'");
					end


					6'h12: begin
						alu_op = 4'b1111;
						mflo = 1;
						$display("\tInstruction 'mflo'");
					end
				endcase
			end


			6'h23: begin
				reg_dst = 0;
				reg_write = 1;
				alu_src = 1;
				alu_op = 4'b0000;
				branch = 0;
				mem_write = 0;
				mem_to_reg = 1;
				zero_sign_ext = 0;
				$display("\tInstruction 'lw'");
			end


			6'h2b: begin
				reg_write = 0;
				alu_src = 1;
				alu_op = 4'b0000;
				branch = 0;
				mem_write = 1;
				zero_sign_ext = 0;
				$display("\tInstruction 'sw'");
			end


			6'h04: begin
				reg_write = 0;
				alu_src = 0;
				alu_op = 4'b0001;
				branch = 1;
				mem_write = 0;
				$display("\tInstruction 'beq'");
			end
		endcase
	end
endmodule
module ControlUnit(input[5:0] opcode,
		input[5:0] funct,
		output reg reg_dst,
		output reg reg_write,
		output reg[1:0] alu_src,
		output reg[3:0] alu_op,
		output reg branch,
		output reg mem_write,
		output reg mem_to_reg,
        	output reg zero_sign_ext,
		output reg mult_op,
		output reg mfhi,
		output reg mflo);


	always @(opcode, funct) begin
		


		reg_dst = 1'bx;
		reg_write = 1'bx;
		alu_src = 2'bxx;
		alu_op = 4'bxxxx;
		branch = 1'bx;
		mem_write = 1'bx;
		mem_to_reg = 1'bx;
		zero_sign_ext = 1'bx;

		mult_op = 1'b0;
		mfhi = 1'b0;
		mflo = 1'b0;


		case (opcode)


			6'h00: begin


				reg_dst = 1;
				reg_write = 1;
				alu_src = 0;
				branch = 0;
				mem_write = 0;
				mem_to_reg = 0;
			

				case (funct)


					6'h20: begin
						alu_op = 4'b0000;
						$display("\tInstruction 'add'");
					end


                   			 6'h21: begin
                   			     alu_op = 4'b0000;
                   			     $display("\tInstruction 'addu'");
                   			 end


					6'h22: begin
						alu_op = 4'b0001;
						$display("\tInstruction 'sub'");
					end


					6'h23: begin
						alu_op = 4'b0001;
						$display("\tInstruction 'subu'");
					end


					6'h24: begin
						alu_op = 4'b0010;
						$display("\tInstruction 'and'");
					end


                   			 6'h27: begin
                   			     alu_op = 4'b0100;
                   			     $display("\tInstruction 'nor'");
                   			 end


					6'h25: begin
						alu_op = 4'b0011;
						$display("\tInstruction 'or'");
					end


                   			 6'h26: begin
                   			     alu_op = 4'b0101;
                   			     $display("\tInstruction 'xor'");
                   			 end
                   			 

                   			 6'h0: begin
                   			     alu_op = 6;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'sll'");
                   			 end


                   			 6'h2: begin
                   			     alu_op = 7;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'srl'");
                   			 end


                   			 6'h3: begin
                   			     alu_op = 8;
                   			     alu_src = 2;
                   			     $display("\tInstruction 'sra'");
                   			 end


                   			 6'h4: begin
                   			     alu_op = 6;
                   			     $display("\tInstruction 'sllv'");
                   			 end


                   			 6'h6: begin
                   			     alu_op = 7;
                   			     $display("\tInstruction 'srlv'");
                   			 end


                   			 6'h7: begin
                   			     alu_op = 8;
                   			     $display("\tInstruction 'srav'");
                   			 end


					6'h2a: begin
						alu_op = 4'b1001;
						$display("\tInstruction 'slt'");
					end


					6'h2b: begin
						alu_op = 4'b1010;
						$display("\tInstruction 'sltu'");
					end


					6'h18: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0010;
						$display("\tInstruction 'mult'");
					end


					6'h19: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0011;
						$display("\tInstruction 'multu'");
					end


					6'h1A: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0000;
						$display("\tInstruction 'div'");
					end


					6'h1B: begin
						mult_op = 1;
						reg_write = 0;
						alu_op = 4'b0001;
						$display("\tInstruction 'divu'");
					end


					6'h10: begin
						alu_op = 4'b1111;
						mfhi = 1;
						$display("\tInstruction 'mfhi'");
					end


					6'h12: begin
						alu_op = 4'b1111;
						mflo = 1;
						$display("\tInstruction 'mflo'");
					end
				endcase
			end


			6'h23: begin
				reg_dst = 0;
				reg_write = 1;
				alu_src = 1;
				alu_op = 4'b0000;
				branch = 0;
				mem_write = 0;
				mem_to_reg = 1;
				zero_sign_ext = 0;
				$display("\tInstruction 'lw'");
			end


			6'h2b: begin
				reg_write = 0;
				alu_src = 1;
				alu_op = 4'b0000;
				branch = 0;
				mem_write = 1;
				zero_sign_ext = 0;
				$display("\tInstruction 'sw'");
			end


			6'h04: begin
				reg_write = 0;
				alu_src = 0;
				alu_op = 4'b0001;
				branch = 1;
				mem_write = 0;
				$display("\tInstruction 'beq'");
			end
		endcase
	end
endmodule