data/full_repos/permissive/42434302/ivltests/test_when_else.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/test_when_else.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (dst != 4\'b0001) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/test_when_else.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (dst != 4\'b0010) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/test_when_else.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (dst != 4\'b0100) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/test_when_else.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (dst != 4\'b1000) begin\n      ^\n%Error: data/full_repos/permissive/42434302/ivltests/test_when_else.v:6: Cannot find file containing module: \'foo_entity\'\n   foo_entity dut (.data_o(dst), .data_i(src));\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/foo_entity\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/foo_entity.v\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/foo_entity.sv\n             foo_entity\n             foo_entity.v\n             foo_entity.sv\n             obj_dir/foo_entity\n             obj_dir/foo_entity.v\n             obj_dir/foo_entity.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] src;
   wire [3:0] dst;

   foo_entity dut (.data_o(dst), .data_i(src));

   initial begin
      src = 2'b00;
      #1 if (dst != 4'b0001) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b01;
      #1 if (dst != 4'b0010) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b10;
      #1 if (dst != 4'b0100) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b11;
      #1 if (dst != 4'b1000) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg [1:0] src;
   wire [3:0] dst;

   foo_entity dut (.data_o(dst), .data_i(src));

   initial begin
      src = 2'b00;
      #1 if (dst != 4'b0001) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b01;
      #1 if (dst != 4'b0010) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b10;
      #1 if (dst != 4'b0100) begin
	 $display("FAILED");
	 $finish;
      end

      src = 2'b11;
      #1 if (dst != 4'b1000) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end
endmodule