data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc/tri_state_bus.v
1: b"%Error: data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc/tri_state_bus.v:20: Cannot find file containing module: 'TRI_BUF'\n    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverA ( .in(a), .con(con1), .out(tri_bus) );\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc,data/full_repos/permissive/503973366/TRI_BUF\n             data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc,data/full_repos/permissive/503973366/TRI_BUF.v\n             data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc,data/full_repos/permissive/503973366/TRI_BUF.sv\n             TRI_BUF\n             TRI_BUF.v\n             TRI_BUF.sv\n             obj_dir/TRI_BUF\n             obj_dir/TRI_BUF.v\n             obj_dir/TRI_BUF.sv\n%Error: data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/etc/tri_state_bus.v:21: Cannot find file containing module: 'TRI_BUF'\n    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverB ( .in(b), .con(con2), .out(tri_bus) );\n    ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module TRI_STATE_BUS #(

    parameter   DATA_WIDTH = 64
    )
    (

    input                       clk,
    input                       rst_n,
    input                       en,
    input                       con1, con2,
    input   [DATA_WIDTH-1:0]    a, b,
    output  [DATA_WIDTH-1:0]    q
    );


    tri [DATA_WIDTH-1:0]    tri_bus;
    reg [DATA_WIDTH-1:0]    temp;


    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverA ( .in(a), .con(con1), .out(tri_bus) );
    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverB ( .in(b), .con(con2), .out(tri_bus) );


    always @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            temp <= {(DATA_WIDTH){1'b0}};
        end else if (en) begin
            temp <= tri_bus;
        end 
    end
    
    assign q = temp;

endmodule
module TRI_STATE_BUS #(

    parameter   DATA_WIDTH = 64
    )
    (

    input                       clk,
    input                       rst_n,
    input                       en,
    input                       con1, con2,
    input   [DATA_WIDTH-1:0]    a, b,
    output  [DATA_WIDTH-1:0]    q
    );



    tri [DATA_WIDTH-1:0]    tri_bus;
    reg [DATA_WIDTH-1:0]    temp;


    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverA ( .in(a), .con(con1), .out(tri_bus) );
    TRI_BUF #( .DATA_WIDTH(DATA_WIDTH) ) driverB ( .in(b), .con(con2), .out(tri_bus) );


    always @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            temp <= {(DATA_WIDTH){1'b0}};
        end else if (en) begin
            temp <= tri_bus;
        end 
    end
    
    assign q = temp;

endmodule