data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v
1: b'%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter AXI_ID_WIDTH   = 4,\n    ^\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:5: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_ADDR_WIDTH  = NOC_ADDR_SIZE,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_DATA_WIDTH  = 2*NOC_DATA_SIZE  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:7: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                   [31:0] noc_error_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           axi4_aw_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:16: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                          axi4_aw_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire       [AXI_ID_WIDTH-1:0] axi4_aw_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [7:0] axi4_aw_len_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [2:0] axi4_aw_size_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [1:0] axi4_aw_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           axi4_w_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:23: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                          axi4_w_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [AXI_DATA_WIDTH-1:0] axi4_w_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire   [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          axi4_w_last_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          axi4_b_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           axi4_b_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire       [AXI_ID_WIDTH-1:0] axi4_b_id_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                     [1:0] axi4_b_resp_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           axi4_ar_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:32: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                          axi4_ar_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire       [AXI_ID_WIDTH-1:0] axi4_ar_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [7:0] axi4_ar_len_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [2:0] axi4_ar_size_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                    [1:0] axi4_ar_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          axi4_r_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           axi4_r_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire       [AXI_ID_WIDTH-1:0] axi4_r_id_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg      [AXI_DATA_WIDTH-1:0] axi4_r_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                     [1:0] axi4_r_resp_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           axi4_r_last_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:47: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                          noc_rx_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_rx_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:49: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_BSEL_SIZE-1:0] noc_rx_bsel_i,          \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:50: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_src_chipid_i,    \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:51: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_src_modid_i,     \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:52: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_trg_chipid_i,    \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:53: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_trg_modid_i,     \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_MODE_SIZE-1:0] noc_rx_mode_i,          \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_ADDR_SIZE-1:0] noc_rx_addr_i,          \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:56: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data0_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data1_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:58: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           noc_rx_stall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:60: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           noc_tx_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_noc_bridge.v:61: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           noc_tx_burst_o,\n    ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module axi4_noc_bridge #(
    `include "noc_parameter.vh"
    ,parameter AXI_ID_WIDTH   = 4,
    parameter AXI_ADDR_WIDTH  = NOC_ADDR_SIZE,
    parameter AXI_DATA_WIDTH  = 2*NOC_DATA_SIZE
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    output wire                   [31:0] noc_error_o,



    output reg                           axi4_aw_ready_o,
    input  wire                          axi4_aw_valid_i,
    input  wire       [AXI_ID_WIDTH-1:0] axi4_aw_id_i,
    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_i,
    input  wire                    [7:0] axi4_aw_len_i,
    input  wire                    [2:0] axi4_aw_size_i,
    input  wire                    [1:0] axi4_aw_burst_i,
    output reg                           axi4_w_ready_o,
    input  wire                          axi4_w_valid_i,
    input  wire     [AXI_DATA_WIDTH-1:0] axi4_w_data_i,
    input  wire   [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_i,
    input  wire                          axi4_w_last_i,
    input  wire                          axi4_b_ready_i,
    output reg                           axi4_b_valid_o,
    output wire       [AXI_ID_WIDTH-1:0] axi4_b_id_o,
    output reg                     [1:0] axi4_b_resp_o,
    output reg                           axi4_ar_ready_o,
    input  wire                          axi4_ar_valid_i,
    input  wire       [AXI_ID_WIDTH-1:0] axi4_ar_id_i,
    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_i,
    input  wire                    [7:0] axi4_ar_len_i,
    input  wire                    [2:0] axi4_ar_size_i,
    input  wire                    [1:0] axi4_ar_burst_i,
    input  wire                          axi4_r_ready_i,
    output reg                           axi4_r_valid_o,
    output wire       [AXI_ID_WIDTH-1:0] axi4_r_id_o,
    output reg      [AXI_DATA_WIDTH-1:0] axi4_r_data_o,
    output reg                     [1:0] axi4_r_resp_o,
    output reg                           axi4_r_last_o,



    input  wire                          noc_rx_wrreq_i,
    input  wire                          noc_rx_burst_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_rx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_rx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_rx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data1_i,
    output reg                           noc_rx_stall_o,

    output reg                           noc_tx_wrreq_o,
    output reg                           noc_tx_burst_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_tx_bsel_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_tx_src_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_tx_src_modid_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_tx_trg_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_tx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_tx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc_tx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_tx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_tx_data1_o,
    input  wire                          noc_tx_stall_i
);


    localparam AXI4_STATES_SIZE       = 4;
    localparam S_AXI4_IDLE            = 4'h0;
    localparam S_AXI4_READ            = 4'h1;
    localparam S_AXI4_WRITE           = 4'h2;
    localparam S_AXI4_WRITE_ACK       = 4'h3;
    localparam S_AXI4_WAIT_WVALID     = 4'h4;
    localparam S_AXI4_WRITE_ABORT     = 4'h5;
    localparam S_AXI4_READ_DROP       = 4'h6;
    localparam S_AXI4_READ_ABORT      = 4'h7;
    localparam S_AXI4_DROP_NOC_PACKET = 4'h8;

    localparam AXI_BURST_TYPE_FIXED = 2'h0;
    localparam AXI_BURST_TYPE_INCR  = 2'h1;
    localparam AXI_BURST_TYPE_WRAP  = 2'h2;

    localparam AXI_RESP_TYPE_OKAY   = 2'h0;
    localparam AXI_RESP_TYPE_EXOKAY = 2'h1;
    localparam AXI_RESP_TYPE_SLVERR = 2'h2;
    localparam AXI_RESP_TYPE_DECERR = 2'h3;

    localparam LOG_DATA_BYTES = $clog2(AXI_DATA_WIDTH/8);




    reg [AXI4_STATES_SIZE-1:0] state, next_state;


    reg   [AXI_ID_WIDTH-1:0] r_axi_req_id, rin_axi_req_id;
    reg [AXI_ADDR_WIDTH-1:0] r_axi_req_addr, rin_axi_req_addr;
    reg                [7:0] r_axi_req_len, rin_axi_req_len;



    reg                [7:0] r_tmp_len, rin_tmp_len;

    reg                      r_noc_rx_burst;


    reg [31:0] r_error, rin_error;








    assign noc_error_o = r_error;



    assign axi4_r_id_o = r_axi_req_id;
    assign axi4_b_id_o = r_axi_req_id;


    assign noc_tx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
    assign noc_tx_src_modid_o = {NOC_MODID_SIZE{1'b0}};
    assign noc_tx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
    assign noc_tx_trg_modid_o = {NOC_MODID_SIZE{1'b0}};



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            state <= S_AXI4_IDLE;

            r_axi_req_id <= {AXI_ID_WIDTH{1'b0}};
            r_axi_req_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_axi_req_len <= 8'h0;



            r_tmp_len <= 8'h0;

            r_noc_rx_burst <= 1'b0;

            r_error <= 32'h0;
        end
        else begin
            state <= next_state;

            r_axi_req_id <= rin_axi_req_id;
            r_axi_req_addr <= rin_axi_req_addr;
            r_axi_req_len <= rin_axi_req_len;



            r_tmp_len <= rin_tmp_len;

            r_noc_rx_burst <= (noc_rx_wrreq_i && !noc_rx_stall_o) ? noc_rx_burst_i : r_noc_rx_burst;

            r_error <= rin_error;
        end
    end




    always @* begin
        next_state = state;

        rin_axi_req_id = r_axi_req_id;
        rin_axi_req_addr = r_axi_req_addr;
        rin_axi_req_len = r_axi_req_len;



        rin_tmp_len = r_tmp_len;

        noc_tx_wrreq_o = 1'b0;
        noc_tx_burst_o = 1'b0;
        noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b0}};
        noc_tx_mode_o = MODE_WRITE_POSTED;
        noc_tx_addr_o = {NOC_ADDR_SIZE{1'b0}};
        noc_tx_data0_o = {NOC_DATA_SIZE{1'b0}};
        noc_tx_data1_o = {NOC_DATA_SIZE{1'b0}};

        noc_rx_stall_o = 1'b1;

        axi4_aw_ready_o = 1'b0;
        axi4_ar_ready_o = 1'b0;

        axi4_r_valid_o = 1'b0;
        axi4_r_data_o = {AXI_DATA_WIDTH{1'b0}};
        axi4_r_last_o = 1'b0;
        axi4_b_resp_o = AXI_RESP_TYPE_OKAY;

        axi4_w_ready_o = 1'b0;

        axi4_r_resp_o = AXI_RESP_TYPE_OKAY;
        axi4_b_valid_o = 1'b0;

        rin_error = r_error;



        case (state)



            S_AXI4_IDLE: begin
                rin_tmp_len = 'h0;


                if (noc_rx_wrreq_i) begin
                    next_state = S_AXI4_DROP_NOC_PACKET;
                end


                else if (axi4_ar_valid_i) begin
                    rin_axi_req_id = axi4_ar_id_i;
                    rin_axi_req_addr = axi4_ar_addr_i;
                    rin_axi_req_len = axi4_ar_len_i;



                    noc_tx_addr_o = axi4_ar_addr_i;
                    noc_tx_mode_o = MODE_READ_REQ_2;

                    if (!noc_tx_stall_i) begin
                        axi4_ar_ready_o = 1'b1;



                        if ((axi4_ar_size_i != LOG_DATA_BYTES) && (axi4_ar_len_i != 8'h0) ||
                            (axi4_ar_burst_i != AXI_BURST_TYPE_INCR)) begin
                            next_state = S_AXI4_READ_ABORT;
                        end
                        else begin

                            noc_tx_wrreq_o = 1'b1;
                            noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                            noc_tx_data0_o = {(axi4_ar_len_i+1), {LOG_DATA_BYTES{1'b0}}, axi4_ar_addr_i};
                            next_state = S_AXI4_READ;
                        end
                    end
                end


                else if (axi4_aw_valid_i) begin
                    rin_axi_req_id = axi4_aw_id_i;
                    rin_axi_req_addr = axi4_aw_addr_i;
                    rin_axi_req_len = axi4_aw_len_i;


                    noc_tx_addr_o = axi4_aw_addr_i;
                    noc_tx_mode_o = MODE_WRITE_POSTED_2;



                    if (((axi4_aw_size_i != LOG_DATA_BYTES) && (axi4_aw_len_i != 8'h0)) ||
                        (axi4_aw_burst_i != AXI_BURST_TYPE_INCR)) begin
                        next_state = S_AXI4_WRITE_ABORT;
                    end



                    else if (!noc_tx_stall_i) begin
                        axi4_aw_ready_o = 1'b1;


                        if ((axi4_aw_size_i > 3'h3) || (axi4_aw_len_i != 8'h0)) begin


                            noc_tx_wrreq_o = 1'b1;
                            noc_tx_burst_o = 1'b1;
                            noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                            noc_tx_data0_o = axi4_aw_len_i + 1;

                            next_state = S_AXI4_WRITE;
                        end


                        else begin
                            axi4_w_ready_o = 1'b1;


                            if (axi4_w_valid_i) begin
                                noc_tx_wrreq_o = 1'b1;
                                noc_tx_bsel_o = axi4_w_strb_i;
                                noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];


                                if (axi4_w_last_i) begin
                                    next_state = S_AXI4_WRITE_ACK;
                                end else begin
                                    next_state = S_AXI4_WRITE_ABORT;
                                end
                            end


                            else begin
                                next_state = S_AXI4_WAIT_WVALID;
                            end
                        end
                    end
                end
            end



            S_AXI4_WAIT_WVALID: begin
                noc_tx_addr_o = r_axi_req_addr;
                noc_tx_mode_o = MODE_WRITE_POSTED_2;

                if (!noc_tx_stall_i) begin
                    axi4_w_ready_o = 1'b1;

                    if (axi4_w_valid_i) begin
                        noc_tx_wrreq_o = 1'b1;
                        noc_tx_bsel_o = axi4_w_strb_i;
                        noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];


                        if (axi4_w_last_i) begin
                            next_state = S_AXI4_WRITE_ACK;
                        end else begin
                            next_state = S_AXI4_WRITE_ABORT;
                        end
                    end
                end
            end



            S_AXI4_READ: begin

                if (noc_rx_wrreq_i) begin


                    if (!r_noc_rx_burst && (noc_rx_mode_i != MODE_READ_RSP_2)) begin
                        next_state = S_AXI4_READ_DROP;
                    end


                    else if (!r_noc_rx_burst && noc_rx_burst_i) begin

                        rin_tmp_len = r_tmp_len + noc_rx_data0_i[7:0] - 'h1;
                        noc_rx_stall_o = 1'b0;
                    end


                    else begin
                        axi4_r_valid_o = 1'b1;
                        axi4_r_data_o = {noc_rx_data1_i, noc_rx_data0_i};

                        if (axi4_r_ready_i) begin
                            noc_rx_stall_o = 1'b0;



                            if (!noc_rx_burst_i && (r_tmp_len == r_axi_req_len)) begin
                                axi4_r_last_o = 1'b1;
                                next_state = S_AXI4_IDLE;
                            end
                        end
                    end
                end
            end



            S_AXI4_WRITE: begin




                if (!noc_tx_stall_i) begin
                    axi4_w_ready_o = 1'b1;

                    if (axi4_w_valid_i) begin
                        noc_tx_wrreq_o = 1'b1;
                        noc_tx_bsel_o = axi4_w_strb_i;
                        noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];
                        noc_tx_data1_o = axi4_w_data_i[2*NOC_DATA_SIZE-1:NOC_DATA_SIZE];




                        if (axi4_w_last_i) begin
                            next_state = S_AXI4_WRITE_ACK;
                        end


                        else begin
                            noc_tx_burst_o = 1'b1;
                        end
                    end
                end
            end



            S_AXI4_WRITE_ACK: begin
                axi4_b_valid_o = 1'b1;
                axi4_b_resp_o = AXI_RESP_TYPE_OKAY;

                if (axi4_b_ready_i) begin
                    next_state = S_AXI4_IDLE;
                end
            end



            S_AXI4_WRITE_ABORT: begin
                axi4_b_valid_o = 1'b1;
                axi4_b_resp_o = AXI_RESP_TYPE_SLVERR;

                if (axi4_b_ready_i) begin
                    next_state = S_AXI4_IDLE;
                end
            end


            S_AXI4_READ_DROP: begin
                if (noc_rx_wrreq_i) begin
                    noc_rx_stall_o = 1'b0;


                    if (!noc_rx_burst_i) begin
                        rin_error = r_error + 1;
                        next_state = S_AXI4_READ_ABORT;
                    end
                end
            end


            S_AXI4_READ_ABORT: begin
                axi4_r_valid_o = 1'b1;
                axi4_r_resp_o = AXI_RESP_TYPE_SLVERR;

                if (r_tmp_len == r_axi_req_len) begin
                    axi4_r_last_o = 1'b1;
                end

                if (axi4_r_ready_i) begin
                    rin_tmp_len = r_tmp_len + 1;

                    if (r_tmp_len == r_axi_req_len) begin
                        next_state = S_AXI4_IDLE;
                    end
                end
            end



            S_AXI4_DROP_NOC_PACKET: begin
                if (noc_rx_wrreq_i) begin
                    noc_rx_stall_o = 1'b0;


                    if (!noc_rx_burst_i) begin
                        rin_error = r_error + 1;
                        next_state = S_AXI4_IDLE;
                    end
                end
            end

            default: begin
                next_state = S_AXI4_IDLE;
            end
        endcase
    end

endmodule
module axi4_noc_bridge #(
    `include "noc_parameter.vh"
    ,parameter AXI_ID_WIDTH   = 4,
    parameter AXI_ADDR_WIDTH  = NOC_ADDR_SIZE,
    parameter AXI_DATA_WIDTH  = 2*NOC_DATA_SIZE
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    output wire                   [31:0] noc_error_o,



    output reg                           axi4_aw_ready_o,
    input  wire                          axi4_aw_valid_i,
    input  wire       [AXI_ID_WIDTH-1:0] axi4_aw_id_i,
    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_aw_addr_i,
    input  wire                    [7:0] axi4_aw_len_i,
    input  wire                    [2:0] axi4_aw_size_i,
    input  wire                    [1:0] axi4_aw_burst_i,
    output reg                           axi4_w_ready_o,
    input  wire                          axi4_w_valid_i,
    input  wire     [AXI_DATA_WIDTH-1:0] axi4_w_data_i,
    input  wire   [AXI_DATA_WIDTH/8-1:0] axi4_w_strb_i,
    input  wire                          axi4_w_last_i,
    input  wire                          axi4_b_ready_i,
    output reg                           axi4_b_valid_o,
    output wire       [AXI_ID_WIDTH-1:0] axi4_b_id_o,
    output reg                     [1:0] axi4_b_resp_o,
    output reg                           axi4_ar_ready_o,
    input  wire                          axi4_ar_valid_i,
    input  wire       [AXI_ID_WIDTH-1:0] axi4_ar_id_i,
    input  wire     [AXI_ADDR_WIDTH-1:0] axi4_ar_addr_i,
    input  wire                    [7:0] axi4_ar_len_i,
    input  wire                    [2:0] axi4_ar_size_i,
    input  wire                    [1:0] axi4_ar_burst_i,
    input  wire                          axi4_r_ready_i,
    output reg                           axi4_r_valid_o,
    output wire       [AXI_ID_WIDTH-1:0] axi4_r_id_o,
    output reg      [AXI_DATA_WIDTH-1:0] axi4_r_data_o,
    output reg                     [1:0] axi4_r_resp_o,
    output reg                           axi4_r_last_o,



    input  wire                          noc_rx_wrreq_i,
    input  wire                          noc_rx_burst_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_rx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_rx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_rx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_rx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_rx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_rx_data1_i,
    output reg                           noc_rx_stall_o,

    output reg                           noc_tx_wrreq_o,
    output reg                           noc_tx_burst_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_tx_bsel_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_tx_src_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_tx_src_modid_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_tx_trg_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_tx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_tx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc_tx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_tx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_tx_data1_o,
    input  wire                          noc_tx_stall_i
);



    localparam AXI4_STATES_SIZE       = 4;
    localparam S_AXI4_IDLE            = 4'h0;
    localparam S_AXI4_READ            = 4'h1;
    localparam S_AXI4_WRITE           = 4'h2;
    localparam S_AXI4_WRITE_ACK       = 4'h3;
    localparam S_AXI4_WAIT_WVALID     = 4'h4;
    localparam S_AXI4_WRITE_ABORT     = 4'h5;
    localparam S_AXI4_READ_DROP       = 4'h6;
    localparam S_AXI4_READ_ABORT      = 4'h7;
    localparam S_AXI4_DROP_NOC_PACKET = 4'h8;

    localparam AXI_BURST_TYPE_FIXED = 2'h0;
    localparam AXI_BURST_TYPE_INCR  = 2'h1;
    localparam AXI_BURST_TYPE_WRAP  = 2'h2;

    localparam AXI_RESP_TYPE_OKAY   = 2'h0;
    localparam AXI_RESP_TYPE_EXOKAY = 2'h1;
    localparam AXI_RESP_TYPE_SLVERR = 2'h2;
    localparam AXI_RESP_TYPE_DECERR = 2'h3;

    localparam LOG_DATA_BYTES = $clog2(AXI_DATA_WIDTH/8);




    reg [AXI4_STATES_SIZE-1:0] state, next_state;


    reg   [AXI_ID_WIDTH-1:0] r_axi_req_id, rin_axi_req_id;
    reg [AXI_ADDR_WIDTH-1:0] r_axi_req_addr, rin_axi_req_addr;
    reg                [7:0] r_axi_req_len, rin_axi_req_len;



    reg                [7:0] r_tmp_len, rin_tmp_len;

    reg                      r_noc_rx_burst;


    reg [31:0] r_error, rin_error;








    assign noc_error_o = r_error;



    assign axi4_r_id_o = r_axi_req_id;
    assign axi4_b_id_o = r_axi_req_id;


    assign noc_tx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
    assign noc_tx_src_modid_o = {NOC_MODID_SIZE{1'b0}};
    assign noc_tx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
    assign noc_tx_trg_modid_o = {NOC_MODID_SIZE{1'b0}};



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            state <= S_AXI4_IDLE;

            r_axi_req_id <= {AXI_ID_WIDTH{1'b0}};
            r_axi_req_addr <= {AXI_ADDR_WIDTH{1'b0}};
            r_axi_req_len <= 8'h0;



            r_tmp_len <= 8'h0;

            r_noc_rx_burst <= 1'b0;

            r_error <= 32'h0;
        end
        else begin
            state <= next_state;

            r_axi_req_id <= rin_axi_req_id;
            r_axi_req_addr <= rin_axi_req_addr;
            r_axi_req_len <= rin_axi_req_len;



            r_tmp_len <= rin_tmp_len;

            r_noc_rx_burst <= (noc_rx_wrreq_i && !noc_rx_stall_o) ? noc_rx_burst_i : r_noc_rx_burst;

            r_error <= rin_error;
        end
    end




    always @* begin
        next_state = state;

        rin_axi_req_id = r_axi_req_id;
        rin_axi_req_addr = r_axi_req_addr;
        rin_axi_req_len = r_axi_req_len;



        rin_tmp_len = r_tmp_len;

        noc_tx_wrreq_o = 1'b0;
        noc_tx_burst_o = 1'b0;
        noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b0}};
        noc_tx_mode_o = MODE_WRITE_POSTED;
        noc_tx_addr_o = {NOC_ADDR_SIZE{1'b0}};
        noc_tx_data0_o = {NOC_DATA_SIZE{1'b0}};
        noc_tx_data1_o = {NOC_DATA_SIZE{1'b0}};

        noc_rx_stall_o = 1'b1;

        axi4_aw_ready_o = 1'b0;
        axi4_ar_ready_o = 1'b0;

        axi4_r_valid_o = 1'b0;
        axi4_r_data_o = {AXI_DATA_WIDTH{1'b0}};
        axi4_r_last_o = 1'b0;
        axi4_b_resp_o = AXI_RESP_TYPE_OKAY;

        axi4_w_ready_o = 1'b0;

        axi4_r_resp_o = AXI_RESP_TYPE_OKAY;
        axi4_b_valid_o = 1'b0;

        rin_error = r_error;



        case (state)



            S_AXI4_IDLE: begin
                rin_tmp_len = 'h0;


                if (noc_rx_wrreq_i) begin
                    next_state = S_AXI4_DROP_NOC_PACKET;
                end


                else if (axi4_ar_valid_i) begin
                    rin_axi_req_id = axi4_ar_id_i;
                    rin_axi_req_addr = axi4_ar_addr_i;
                    rin_axi_req_len = axi4_ar_len_i;



                    noc_tx_addr_o = axi4_ar_addr_i;
                    noc_tx_mode_o = MODE_READ_REQ_2;

                    if (!noc_tx_stall_i) begin
                        axi4_ar_ready_o = 1'b1;



                        if ((axi4_ar_size_i != LOG_DATA_BYTES) && (axi4_ar_len_i != 8'h0) ||
                            (axi4_ar_burst_i != AXI_BURST_TYPE_INCR)) begin
                            next_state = S_AXI4_READ_ABORT;
                        end
                        else begin

                            noc_tx_wrreq_o = 1'b1;
                            noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                            noc_tx_data0_o = {(axi4_ar_len_i+1), {LOG_DATA_BYTES{1'b0}}, axi4_ar_addr_i};
                            next_state = S_AXI4_READ;
                        end
                    end
                end


                else if (axi4_aw_valid_i) begin
                    rin_axi_req_id = axi4_aw_id_i;
                    rin_axi_req_addr = axi4_aw_addr_i;
                    rin_axi_req_len = axi4_aw_len_i;


                    noc_tx_addr_o = axi4_aw_addr_i;
                    noc_tx_mode_o = MODE_WRITE_POSTED_2;



                    if (((axi4_aw_size_i != LOG_DATA_BYTES) && (axi4_aw_len_i != 8'h0)) ||
                        (axi4_aw_burst_i != AXI_BURST_TYPE_INCR)) begin
                        next_state = S_AXI4_WRITE_ABORT;
                    end



                    else if (!noc_tx_stall_i) begin
                        axi4_aw_ready_o = 1'b1;


                        if ((axi4_aw_size_i > 3'h3) || (axi4_aw_len_i != 8'h0)) begin


                            noc_tx_wrreq_o = 1'b1;
                            noc_tx_burst_o = 1'b1;
                            noc_tx_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                            noc_tx_data0_o = axi4_aw_len_i + 1;

                            next_state = S_AXI4_WRITE;
                        end


                        else begin
                            axi4_w_ready_o = 1'b1;


                            if (axi4_w_valid_i) begin
                                noc_tx_wrreq_o = 1'b1;
                                noc_tx_bsel_o = axi4_w_strb_i;
                                noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];


                                if (axi4_w_last_i) begin
                                    next_state = S_AXI4_WRITE_ACK;
                                end else begin
                                    next_state = S_AXI4_WRITE_ABORT;
                                end
                            end


                            else begin
                                next_state = S_AXI4_WAIT_WVALID;
                            end
                        end
                    end
                end
            end



            S_AXI4_WAIT_WVALID: begin
                noc_tx_addr_o = r_axi_req_addr;
                noc_tx_mode_o = MODE_WRITE_POSTED_2;

                if (!noc_tx_stall_i) begin
                    axi4_w_ready_o = 1'b1;

                    if (axi4_w_valid_i) begin
                        noc_tx_wrreq_o = 1'b1;
                        noc_tx_bsel_o = axi4_w_strb_i;
                        noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];


                        if (axi4_w_last_i) begin
                            next_state = S_AXI4_WRITE_ACK;
                        end else begin
                            next_state = S_AXI4_WRITE_ABORT;
                        end
                    end
                end
            end



            S_AXI4_READ: begin

                if (noc_rx_wrreq_i) begin


                    if (!r_noc_rx_burst && (noc_rx_mode_i != MODE_READ_RSP_2)) begin
                        next_state = S_AXI4_READ_DROP;
                    end


                    else if (!r_noc_rx_burst && noc_rx_burst_i) begin

                        rin_tmp_len = r_tmp_len + noc_rx_data0_i[7:0] - 'h1;
                        noc_rx_stall_o = 1'b0;
                    end


                    else begin
                        axi4_r_valid_o = 1'b1;
                        axi4_r_data_o = {noc_rx_data1_i, noc_rx_data0_i};

                        if (axi4_r_ready_i) begin
                            noc_rx_stall_o = 1'b0;



                            if (!noc_rx_burst_i && (r_tmp_len == r_axi_req_len)) begin
                                axi4_r_last_o = 1'b1;
                                next_state = S_AXI4_IDLE;
                            end
                        end
                    end
                end
            end



            S_AXI4_WRITE: begin




                if (!noc_tx_stall_i) begin
                    axi4_w_ready_o = 1'b1;

                    if (axi4_w_valid_i) begin
                        noc_tx_wrreq_o = 1'b1;
                        noc_tx_bsel_o = axi4_w_strb_i;
                        noc_tx_data0_o = axi4_w_data_i[NOC_DATA_SIZE-1:0];
                        noc_tx_data1_o = axi4_w_data_i[2*NOC_DATA_SIZE-1:NOC_DATA_SIZE];




                        if (axi4_w_last_i) begin
                            next_state = S_AXI4_WRITE_ACK;
                        end


                        else begin
                            noc_tx_burst_o = 1'b1;
                        end
                    end
                end
            end



            S_AXI4_WRITE_ACK: begin
                axi4_b_valid_o = 1'b1;
                axi4_b_resp_o = AXI_RESP_TYPE_OKAY;

                if (axi4_b_ready_i) begin
                    next_state = S_AXI4_IDLE;
                end
            end



            S_AXI4_WRITE_ABORT: begin
                axi4_b_valid_o = 1'b1;
                axi4_b_resp_o = AXI_RESP_TYPE_SLVERR;

                if (axi4_b_ready_i) begin
                    next_state = S_AXI4_IDLE;
                end
            end


            S_AXI4_READ_DROP: begin
                if (noc_rx_wrreq_i) begin
                    noc_rx_stall_o = 1'b0;


                    if (!noc_rx_burst_i) begin
                        rin_error = r_error + 1;
                        next_state = S_AXI4_READ_ABORT;
                    end
                end
            end


            S_AXI4_READ_ABORT: begin
                axi4_r_valid_o = 1'b1;
                axi4_r_resp_o = AXI_RESP_TYPE_SLVERR;

                if (r_tmp_len == r_axi_req_len) begin
                    axi4_r_last_o = 1'b1;
                end

                if (axi4_r_ready_i) begin
                    rin_tmp_len = r_tmp_len + 1;

                    if (r_tmp_len == r_axi_req_len) begin
                        next_state = S_AXI4_IDLE;
                    end
                end
            end



            S_AXI4_DROP_NOC_PACKET: begin
                if (noc_rx_wrreq_i) begin
                    noc_rx_stall_o = 1'b0;


                    if (!noc_rx_burst_i) begin
                        rin_error = r_error + 1;
                        next_state = S_AXI4_IDLE;
                    end
                end
            end

            default: begin
                next_state = S_AXI4_IDLE;
            end
        endcase
    end

endmodule