data/full_repos/permissive/417288846/List_1/Task_4/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_4/counter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #1 nclr = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_4/counter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk <= ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_4/counter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: data/full_repos/permissive/417288846/List_1/Task_4/counter_tb.v:19: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " clk = %d | val = %d%d%d%d", clk, num1, num2, num3, num4);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg clk, nclr;
    wire num1, num2, num3, num4; 
    integer i;

    counter_10 cnt(.clk(clk), .nclr(nclr), .num1(num1), .num2(num2), .num3(num3), .num4(num4));
    initial begin
        clk = 0;
        nclr = 0;
        #1 nclr = 1;

        for (i = 0; i < 20; i = i + 1) begin
            #1 clk <= ~clk;
        end


        #2 $finish;
    end
    initial $monitor ($time, " clk = %d | val = %d%d%d%d", clk, num1, num2, num3, num4);
endmodule
module testbench;

    reg clk, nclr;
    wire num1, num2, num3, num4; 
    integer i;

    counter_10 cnt(.clk(clk), .nclr(nclr), .num1(num1), .num2(num2), .num3(num3), .num4(num4));
    initial begin
        clk = 0;
        nclr = 0;
        #1 nclr = 1;

        for (i = 0; i < 20; i = i + 1) begin
            #1 clk <= ~clk;
        end


        #2 $finish;
    end
    initial $monitor ($time, " clk = %d | val = %d%d%d%d", clk, num1, num2, num3, num4);
endmodule