data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v
1: b'%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:4: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:5: Cannot find include file: mod_ids.vh\n    ,`include "mod_ids.vh" \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:7: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                            reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                            config_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_REG_BSEL_SIZE-1:0] config_wben_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_REG_ADDR_SIZE-1:0] config_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_REG_DATA_SIZE-1:0] config_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [TCU_REG_DATA_SIZE-1:0] config_rdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                            rocket_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                            rocket_ext_int1_o,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                            rocket_ext_int2_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                     [31:0] tcu_mem_axi4_error_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                     [31:0] axi4_mem_bridge_error_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                            rocket_trace_enabled_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_ptr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_count_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:29: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/rocket_regfile.v:66: syntax error, unexpected always\n    always @(posedge clk_i or negedge reset_n_i) begin\n    ^~~~~~\n%Error: Exiting due to 21 error(s)\n'
module rocket_regfile #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,`include "mod_ids.vh"
    ,parameter ROCKET_MEM_ADDR_SIZE = 32
)(
    input  wire                            clk_i,
    input  wire                            reset_n_i,



    input  wire                            config_en_i,
    input  wire    [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire    [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire    [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire    [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    output wire                            rocket_en_o,
    output wire                            rocket_ext_int1_o,
    output wire                            rocket_ext_int2_o,
    input  wire                     [31:0] tcu_mem_axi4_error_i,
    input  wire                     [31:0] axi4_mem_bridge_error_i,
    output wire                            rocket_trace_enabled_o,
    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_ptr_i,
    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_count_i
);



    localparam REG_ROCKET_EN             = 32'h00000000;
    localparam REG_ROCKET_EXT_INT1       = 32'h00000008;
    localparam REG_ROCKET_EXT_INT2       = 32'h00000010;

    localparam REG_TCU_MEM_AXI4_ERROR    = 32'h00000030;
    localparam REG_AXI4_MEM_BRIDGE_ERROR = 32'h00000038;

    localparam REG_ROCKET_TRACE_ENABLED  = 32'h00000040;
    localparam REG_ROCKET_TRACE_PTR      = 32'h00000048;
    localparam REG_ROCKET_TRACE_COUNT    = 32'h00000050;






    reg        r_rocket_en, rin_rocket_en;
    

    reg        r_rocket_ext_int1, rin_rocket_ext_int1;
    reg        r_rocket_ext_int2, rin_rocket_ext_int2;


    reg        r_rocket_trace_enabled, rin_rocket_trace_enabled;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_rocket_en <= 1'b0;

            r_rocket_ext_int1 <= 1'b0;
            r_rocket_ext_int2 <= 1'b0;

            r_rocket_trace_enabled <= 1'b0;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_rocket_en <= rin_rocket_en;

            r_rocket_ext_int1 <= rin_rocket_ext_int1;
            r_rocket_ext_int2 <= rin_rocket_ext_int2;

            r_rocket_trace_enabled <= rin_rocket_trace_enabled;

            r_config_rdata <= rin_config_rdata;
        end
    end




    always @* begin

        rin_rocket_en = r_rocket_en;

        rin_rocket_ext_int1 = r_rocket_ext_int1;
        rin_rocket_ext_int2 = r_rocket_ext_int2;

        rin_rocket_trace_enabled = r_rocket_trace_enabled;

        rin_config_rdata = r_config_rdata;





        if (reg_w_en) begin
            case (config_addr_i)
                REG_ROCKET_EN: begin
                    if(config_wben_i[0]) rin_rocket_en = config_wdata_i[0];
                end

                REG_ROCKET_EXT_INT1: begin
                    if(config_wben_i[0]) rin_rocket_ext_int1 = config_wdata_i[0];
                end

                REG_ROCKET_EXT_INT2: begin
                    if(config_wben_i[0]) rin_rocket_ext_int2 = config_wdata_i[0];
                end

                REG_ROCKET_TRACE_ENABLED: begin
                    if(config_wben_i[0]) rin_rocket_trace_enabled = config_wdata_i[0];
                end


            endcase
        end



        else if (reg_r_en) begin
            case (config_addr_i)
                REG_ROCKET_EN: begin
                    rin_config_rdata = r_rocket_en;
                end

                REG_ROCKET_EXT_INT1: begin
                    rin_config_rdata = r_rocket_ext_int1;
                end

                REG_ROCKET_EXT_INT2: begin
                    rin_config_rdata = r_rocket_ext_int2;
                end

                REG_TCU_MEM_AXI4_ERROR: begin
                    rin_config_rdata = tcu_mem_axi4_error_i;
                end

                REG_AXI4_MEM_BRIDGE_ERROR: begin
                    rin_config_rdata = axi4_mem_bridge_error_i;
                end

                REG_ROCKET_TRACE_ENABLED: begin
                    rin_config_rdata = r_rocket_trace_enabled;
                end

                REG_ROCKET_TRACE_PTR: begin
                    rin_config_rdata = rocket_trace_ptr_i;
                end

                REG_ROCKET_TRACE_COUNT: begin
                    rin_config_rdata = rocket_trace_count_i;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;

    assign rocket_en_o = r_rocket_en;

    assign rocket_ext_int1_o = r_rocket_ext_int1;
    assign rocket_ext_int2_o = r_rocket_ext_int2;

    assign rocket_trace_enabled_o = r_rocket_trace_enabled;

endmodule
module rocket_regfile #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,`include "mod_ids.vh"
    ,parameter ROCKET_MEM_ADDR_SIZE = 32
)(
    input  wire                            clk_i,
    input  wire                            reset_n_i,



    input  wire                            config_en_i,
    input  wire    [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
    input  wire    [TCU_REG_ADDR_SIZE-1:0] config_addr_i,
    input  wire    [TCU_REG_DATA_SIZE-1:0] config_wdata_i,
    output wire    [TCU_REG_DATA_SIZE-1:0] config_rdata_o,



    output wire                            rocket_en_o,
    output wire                            rocket_ext_int1_o,
    output wire                            rocket_ext_int2_o,
    input  wire                     [31:0] tcu_mem_axi4_error_i,
    input  wire                     [31:0] axi4_mem_bridge_error_i,
    output wire                            rocket_trace_enabled_o,
    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_ptr_i,
    input  wire [ROCKET_MEM_ADDR_SIZE-1:0] rocket_trace_count_i
);




    localparam REG_ROCKET_EN             = 32'h00000000;
    localparam REG_ROCKET_EXT_INT1       = 32'h00000008;
    localparam REG_ROCKET_EXT_INT2       = 32'h00000010;

    localparam REG_TCU_MEM_AXI4_ERROR    = 32'h00000030;
    localparam REG_AXI4_MEM_BRIDGE_ERROR = 32'h00000038;

    localparam REG_ROCKET_TRACE_ENABLED  = 32'h00000040;
    localparam REG_ROCKET_TRACE_PTR      = 32'h00000048;
    localparam REG_ROCKET_TRACE_COUNT    = 32'h00000050;






    reg        r_rocket_en, rin_rocket_en;
    

    reg        r_rocket_ext_int1, rin_rocket_ext_int1;
    reg        r_rocket_ext_int2, rin_rocket_ext_int2;


    reg        r_rocket_trace_enabled, rin_rocket_trace_enabled;

    reg [63:0] r_config_rdata, rin_config_rdata;


    wire reg_w_en = (config_en_i &&  (|config_wben_i));
    wire reg_r_en = (config_en_i && !(|config_wben_i));



    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_rocket_en <= 1'b0;

            r_rocket_ext_int1 <= 1'b0;
            r_rocket_ext_int2 <= 1'b0;

            r_rocket_trace_enabled <= 1'b0;

            r_config_rdata <= 64'h0;
        end
        else begin
            r_rocket_en <= rin_rocket_en;

            r_rocket_ext_int1 <= rin_rocket_ext_int1;
            r_rocket_ext_int2 <= rin_rocket_ext_int2;

            r_rocket_trace_enabled <= rin_rocket_trace_enabled;

            r_config_rdata <= rin_config_rdata;
        end
    end




    always @* begin

        rin_rocket_en = r_rocket_en;

        rin_rocket_ext_int1 = r_rocket_ext_int1;
        rin_rocket_ext_int2 = r_rocket_ext_int2;

        rin_rocket_trace_enabled = r_rocket_trace_enabled;

        rin_config_rdata = r_config_rdata;





        if (reg_w_en) begin
            case (config_addr_i)
                REG_ROCKET_EN: begin
                    if(config_wben_i[0]) rin_rocket_en = config_wdata_i[0];
                end

                REG_ROCKET_EXT_INT1: begin
                    if(config_wben_i[0]) rin_rocket_ext_int1 = config_wdata_i[0];
                end

                REG_ROCKET_EXT_INT2: begin
                    if(config_wben_i[0]) rin_rocket_ext_int2 = config_wdata_i[0];
                end

                REG_ROCKET_TRACE_ENABLED: begin
                    if(config_wben_i[0]) rin_rocket_trace_enabled = config_wdata_i[0];
                end


            endcase
        end



        else if (reg_r_en) begin
            case (config_addr_i)
                REG_ROCKET_EN: begin
                    rin_config_rdata = r_rocket_en;
                end

                REG_ROCKET_EXT_INT1: begin
                    rin_config_rdata = r_rocket_ext_int1;
                end

                REG_ROCKET_EXT_INT2: begin
                    rin_config_rdata = r_rocket_ext_int2;
                end

                REG_TCU_MEM_AXI4_ERROR: begin
                    rin_config_rdata = tcu_mem_axi4_error_i;
                end

                REG_AXI4_MEM_BRIDGE_ERROR: begin
                    rin_config_rdata = axi4_mem_bridge_error_i;
                end

                REG_ROCKET_TRACE_ENABLED: begin
                    rin_config_rdata = r_rocket_trace_enabled;
                end

                REG_ROCKET_TRACE_PTR: begin
                    rin_config_rdata = rocket_trace_ptr_i;
                end

                REG_ROCKET_TRACE_COUNT: begin
                    rin_config_rdata = rocket_trace_count_i;
                end

                default: begin
                    rin_config_rdata = 64'h0;
                end
            endcase
        end
    end



    assign config_rdata_o = r_config_rdata;

    assign rocket_en_o = r_rocket_en;

    assign rocket_ext_int1_o = r_rocket_ext_int1;
    assign rocket_ext_int2_o = r_rocket_ext_int2;

    assign rocket_trace_enabled_o = r_rocket_trace_enabled;

endmodule