data/full_repos/permissive/461069000/pwm/src/counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461069000/pwm/src/counter.v:12: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance counter\n            out <= 1\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter
#(parameter BIT_WIDTH = 8)
(
    input clk,
    input reset,
    output reg[BIT_WIDTH-1:0] out
);
    
    always @(posedge clk, negedge reset) begin
        if (!reset)
            out <= 1'b0;
        else
            out <= out + 1'b1;
    end

endmodule
module counter
#(parameter BIT_WIDTH = 8)
(
    input clk,
    input reset,
    output reg[BIT_WIDTH-1:0] out
);

    
    always @(posedge clk, negedge reset) begin
        if (!reset)
            out <= 1'b0;
        else
            out <= out + 1'b1;
    end

endmodule