data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:80: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'row_select\' generates 6 bits.\n                                                                                      : ... In instance driver_sequencer\n  assign mem_offset  = ((row_select<<MEM_ADDRESS_LENGTH) - (row_select<<4))  + col_select; \n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:80: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'row_select\' generates 6 bits.\n                                                                                      : ... In instance driver_sequencer\n  assign mem_offset  = ((row_select<<MEM_ADDRESS_LENGTH) - (row_select<<4))  + col_select; \n                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:80: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'col_select\' generates 6 bits.\n                                                                                      : ... In instance driver_sequencer\n  assign mem_offset  = ((row_select<<MEM_ADDRESS_LENGTH) - (row_select<<4))  + col_select; \n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:81: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                      : ... In instance driver_sequencer\n  assign active_mem_offset = ACTIVE_MEM_LOWER_BOUND+mem_offset[9:4];\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:84: Bit extraction of array[194:0] requires 8 bit index, not 10 bits.\n                                                                                      : ... In instance driver_sequencer\n    active_mem <= mem[active_mem_offset];  \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:95: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                      : ... In instance driver_sequencer\n  assign driver_mem_offset = row_col_select ? select_mem_col : select_mem_row;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/529248833/verilog/rtl/driver_sequencer.v:98: Operator ADD expects 32 or 6 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                      : ... In instance driver_sequencer\n    driver_mem = mem[DOT_MEM_LOWER_BOUND+driver_mem_offset[MEM_ADDRESS_LENGTH-1:4]];  \n                                        ^\n%Error: Exiting due to 7 warning(s)\n'
module driver_sequencer
#(
  parameter MEM_LENGTH = 48,
  parameter MEM_ADDRESS_LENGTH=6
)
(
  input   wire                            clock,
  input   wire [9:0] mem_address,
  input   wire                            mem_write_n,
  input   wire [MEM_ADDRESS_LENGTH-1:0]   row_select,
  input   wire [MEM_ADDRESS_LENGTH-1:0]   col_select,
  input   wire [15:0]                     data_in,
  input   wire                            row_col_select,
  output  wire                            driver_data,
  output  reg                             driver_enable
);


  localparam NUM_OF_DOTS_PER_MEM    = 3;
  localparam ACTIVE_MEM_LOWER_BOUND = 0;
  localparam ACTIVE_MEM_UPPER_BOUND = ACTIVE_MEM_LOWER_BOUND + NUM_OF_DOTS_PER_MEM * MEM_LENGTH - 1 ;
  localparam SELECT_MEM_LOWER_BOUND = ACTIVE_MEM_UPPER_BOUND + 1 ;
  localparam SELECT_MEM_UPPER_BOUND = SELECT_MEM_LOWER_BOUND + MEM_LENGTH -1 ;
  localparam DOT_MEM_LOWER_BOUND    = SELECT_MEM_UPPER_BOUND + 1 ; 
  localparam DOT_MEM_UPPER_BOUND    = DOT_MEM_LOWER_BOUND + NUM_OF_DOTS_PER_MEM - 1 ;
  localparam SYS_MEM_BOUND          = DOT_MEM_UPPER_BOUND;
  localparam SYS_MEM_ADDRESS_LENGTH = 2*MEM_ADDRESS_LENGTH;

  wire [MEM_LENGTH-1:0]                   current_row;
  reg  [15:0]                             firing_mem ;
  reg  [15:0]                             select_mem;
  reg  [15:0]                             dot_mem;
  wire                                    current_bit;
  wire [MEM_ADDRESS_LENGTH-1:0]           current_data_idx;


  wire [9:0]         mem_offset;
  wire [9:0]         active_mem_offset;
  wire [MEM_ADDRESS_LENGTH-1:0]           driver_mem_offset;
  reg [15:0]                              mem [0:SYS_MEM_BOUND];
  reg [15:0]                              active_mem;
  reg [15:0]                              select_mem_col;
  reg [15:0]                              select_mem_row;
  reg [15:0]                              driver_mem;

  genvar I;
  generate
    for(I=0;I<SYS_MEM_BOUND+1;I++) begin : mem_gen
      always@(posedge clock) begin

        mem[I] <= (I==mem_address) && (mem_write_n == 0) ? data_in : mem[I];
      end
    end
  endgenerate

  assign mem_offset  = ((row_select<<MEM_ADDRESS_LENGTH) - (row_select<<4))  + col_select; 
  assign active_mem_offset = ACTIVE_MEM_LOWER_BOUND+mem_offset[9:4];

  always@(posedge clock) begin
    active_mem <= mem[active_mem_offset];
  end

  always@(posedge clock)
    driver_enable = active_mem[mem_offset[3:0]];

  always@(posedge clock) begin
    select_mem_col = mem[SELECT_MEM_LOWER_BOUND+col_select];
    select_mem_row = mem[SELECT_MEM_LOWER_BOUND+row_select];
  end

  assign driver_mem_offset = row_col_select ? select_mem_col : select_mem_row;

  always@(posedge clock) begin
    driver_mem = mem[DOT_MEM_LOWER_BOUND+driver_mem_offset[MEM_ADDRESS_LENGTH-1:4]];
  end

  assign driver_data = driver_mem[driver_mem_offset[3:0]]; 

endmodule
module driver_sequencer
#(
  parameter MEM_LENGTH = 48,
  parameter MEM_ADDRESS_LENGTH=6
)
(
  input   wire                            clock,
  input   wire [9:0] mem_address,
  input   wire                            mem_write_n,
  input   wire [MEM_ADDRESS_LENGTH-1:0]   row_select,
  input   wire [MEM_ADDRESS_LENGTH-1:0]   col_select,
  input   wire [15:0]                     data_in,
  input   wire                            row_col_select,
  output  wire                            driver_data,
  output  reg                             driver_enable
);



  localparam NUM_OF_DOTS_PER_MEM    = 3;
  localparam ACTIVE_MEM_LOWER_BOUND = 0;
  localparam ACTIVE_MEM_UPPER_BOUND = ACTIVE_MEM_LOWER_BOUND + NUM_OF_DOTS_PER_MEM * MEM_LENGTH - 1 ;
  localparam SELECT_MEM_LOWER_BOUND = ACTIVE_MEM_UPPER_BOUND + 1 ;
  localparam SELECT_MEM_UPPER_BOUND = SELECT_MEM_LOWER_BOUND + MEM_LENGTH -1 ;
  localparam DOT_MEM_LOWER_BOUND    = SELECT_MEM_UPPER_BOUND + 1 ; 
  localparam DOT_MEM_UPPER_BOUND    = DOT_MEM_LOWER_BOUND + NUM_OF_DOTS_PER_MEM - 1 ;
  localparam SYS_MEM_BOUND          = DOT_MEM_UPPER_BOUND;
  localparam SYS_MEM_ADDRESS_LENGTH = 2*MEM_ADDRESS_LENGTH;

  wire [MEM_LENGTH-1:0]                   current_row;
  reg  [15:0]                             firing_mem ;
  reg  [15:0]                             select_mem;
  reg  [15:0]                             dot_mem;
  wire                                    current_bit;
  wire [MEM_ADDRESS_LENGTH-1:0]           current_data_idx;


  wire [9:0]         mem_offset;
  wire [9:0]         active_mem_offset;
  wire [MEM_ADDRESS_LENGTH-1:0]           driver_mem_offset;
  reg [15:0]                              mem [0:SYS_MEM_BOUND];
  reg [15:0]                              active_mem;
  reg [15:0]                              select_mem_col;
  reg [15:0]                              select_mem_row;
  reg [15:0]                              driver_mem;

  genvar I;
  generate
    for(I=0;I<SYS_MEM_BOUND+1;I++) begin : mem_gen
      always@(posedge clock) begin

        mem[I] <= (I==mem_address) && (mem_write_n == 0) ? data_in : mem[I];
      end
    end
  endgenerate

  assign mem_offset  = ((row_select<<MEM_ADDRESS_LENGTH) - (row_select<<4))  + col_select; 
  assign active_mem_offset = ACTIVE_MEM_LOWER_BOUND+mem_offset[9:4];

  always@(posedge clock) begin
    active_mem <= mem[active_mem_offset];
  end

  always@(posedge clock)
    driver_enable = active_mem[mem_offset[3:0]];

  always@(posedge clock) begin
    select_mem_col = mem[SELECT_MEM_LOWER_BOUND+col_select];
    select_mem_row = mem[SELECT_MEM_LOWER_BOUND+row_select];
  end

  assign driver_mem_offset = row_col_select ? select_mem_col : select_mem_row;

  always@(posedge clock) begin
    driver_mem = mem[DOT_MEM_LOWER_BOUND+driver_mem_offset[MEM_ADDRESS_LENGTH-1:4]];
  end

  assign driver_data = driver_mem[driver_mem_offset[3:0]]; 

endmodule