data/full_repos/permissive/418819021/lab-04/test_pop.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:7: Define or directive not defined: \'`STAGE_COUNT\'\n input [`STAGE_COUNT-1:0]       pipeline_stage;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:8: Define or directive not defined: \'`GROUP_COUNT\'\n input [`GROUP_COUNT-1:0]       opcode_group;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:9: Define or directive not defined: \'`OPCODE_COUNT\'\n input [`OPCODE_COUNT-1:0]      opcode_type;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:11: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   writeback_value;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:12: Define or directive not defined: \'`SIGNAL_COUNT\'\n input [`SIGNAL_COUNT-1:0]      signals;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:13: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:14: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:15: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_rr;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:16: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_rd;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:17: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_out;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:18: Define or directive not defined: \'`TEST_INSTR_WIDTH\'\n input [`TEST_INSTR_WIDTH-1:0] bus_address;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:19: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   sp;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:21: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] register_rr;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:22: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] register_rd;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:27: Define or directive not defined: \'`STAGE_IF\'\n   `STAGE_IF:  TEST_POP = 1\'b1;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:27: syntax error, unexpected \':\', expecting endcase\n   `STAGE_IF:  TEST_POP = 1\'b1;\n            ^\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:28: Define or directive not defined: \'`STAGE_ID\'\n   `STAGE_ID:  TEST_POP = 1\'b1;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:29: Define or directive not defined: \'`STAGE_EX\'\n   `STAGE_EX:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:31: Define or directive not defined: \'`GROUP_STACK\'\n    if(opcode_group[`GROUP_STACK]\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:32: Define or directive not defined: \'`TYPE_POP\'\n    && opcode_type == `TYPE_POP && signals[`CONTROL_STACK_PREINC] == 1 && sp == stack_pointer[7:0])\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:32: Define or directive not defined: \'`CONTROL_STACK_PREINC\'\n    && opcode_type == `TYPE_POP && signals[`CONTROL_STACK_PREINC] == 1 && sp == stack_pointer[7:0])\n                                           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:37: syntax error, unexpected else\n    else\n    ^~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:40: Define or directive not defined: \'`CONTROL_STACK_PREINC\'\n      if (signals[`CONTROL_STACK_PREINC] != 1) begin\n                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      if (signals[`CONTROL_STACK_PREINC] != 1) begin\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:47: Define or directive not defined: \'`STAGE_MEM\'\n   `STAGE_MEM:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:48: Define or directive not defined: \'`GROUP_STACK\'\n    if (opcode_group[`GROUP_STACK] &&\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:49: Define or directive not defined: \'`TYPE_POP\'\n        opcode_type == `TYPE_POP &&\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:54: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:59: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:60: Define or directive not defined: \'`STAGE_WB\'\n   `STAGE_WB:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:61: Define or directive not defined: \'`GROUP_STACK\'\n    if (opcode_group[`GROUP_STACK] &&\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:62: Define or directive not defined: \'`TYPE_POP\'\n        opcode_type == `TYPE_POP &&\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:63: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n      writeback_value == value[`TEST_DATA_WIDTH-1:0])\n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:67: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-04/test_pop.vh:72: syntax error, unexpected end\n     end\n     ^~~\n%Error: Cannot continue\n'
function TEST_POP;
	input [`STAGE_COUNT-1:0]       pipeline_stage;
	input [`GROUP_COUNT-1:0]       opcode_group;
	input [`OPCODE_COUNT-1:0]      opcode_type;
	input [11:0]                   opcode_imd;
	input [`TEST_DATA_WIDTH-1:0]   writeback_value;
	input [`SIGNAL_COUNT-1:0]      signals;
	input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;
	input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rd;
	input [`TEST_DATA_WIDTH-1:0]   alu_out;
	input [`TEST_INSTR_WIDTH-1:0] bus_address;
	input [`TEST_DATA_WIDTH-1:0]   sp;
	input integer address;
	input [`TEST_R_ADDR_WIDTH-1:0] register_rr;
	input [`TEST_R_ADDR_WIDTH-1:0] register_rd;
	input integer value;
	input integer stack_pointer;
	begin
		case (pipeline_stage)
			`STAGE_IF:  TEST_POP = 1'b1;
			`STAGE_ID:  TEST_POP = 1'b1;
			`STAGE_EX:

				if(opcode_group[`GROUP_STACK]
				&& opcode_type == `TYPE_POP && signals[`CONTROL_STACK_PREINC] == 1 && sp == stack_pointer[7:0])
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - EX: OK", register_rd);
					end
				else
					begin
						TEST_POP = 1'bx;
						if (signals[`CONTROL_STACK_PREINC] != 1) begin
							$display("POP R%2d - EX: FAILED => signals[`CONTROL_STACK_PREINC]: 1 vs 0", register_rd );
						end
						if (sp !== stack_pointer[7:0]) begin
							$display("POP R%2d - EX: FAILED => sp: (%2H) vs (%2H)", register_rd, stack_pointer[7:0], sp );
						end
					end
			`STAGE_MEM:
				if (opcode_group[`GROUP_STACK] &&
				    opcode_type == `TYPE_POP &&
					 bus_address == {8'd0, address[7:0] - 8'h40})
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - MEM: OK (bus_addr = %2H)", register_rd,  bus_address);
					end
				else
					begin
						TEST_POP = 1'bx;
						$display("POP R%2d - MEM: FAILED => bus_addr: (%2H) vs (%2H)", register_rd, address[7:0] - 8'h40, bus_address);
					end
			`STAGE_WB:
				if (opcode_group[`GROUP_STACK] &&
				    opcode_type == `TYPE_POP &&
					 writeback_value == value[`TEST_DATA_WIDTH-1:0])
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - WB: OK (R%2d = %3d)", register_rd, register_rd, value);
					end
				else
					begin
						TEST_POP = 1'bx;
						$display("POP R%2d - WB: FAILED => R%2d:(%3d) vs (%3d)", register_rd, register_rd, writeback_value, value);
					end
		endcase
	end
endfunction
function TEST_POP;

	input [`STAGE_COUNT-1:0]       pipeline_stage;
	input [`GROUP_COUNT-1:0]       opcode_group;
	input [`OPCODE_COUNT-1:0]      opcode_type;
	input [11:0]                   opcode_imd;
	input [`TEST_DATA_WIDTH-1:0]   writeback_value;
	input [`SIGNAL_COUNT-1:0]      signals;
	input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;
	input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rd;
	input [`TEST_DATA_WIDTH-1:0]   alu_out;
	input [`TEST_INSTR_WIDTH-1:0] bus_address;
	input [`TEST_DATA_WIDTH-1:0]   sp;
	input integer address;
	input [`TEST_R_ADDR_WIDTH-1:0] register_rr;
	input [`TEST_R_ADDR_WIDTH-1:0] register_rd;
	input integer value;
	input integer stack_pointer;
	begin
		case (pipeline_stage)
			`STAGE_IF:  TEST_POP = 1'b1;
			`STAGE_ID:  TEST_POP = 1'b1;
			`STAGE_EX:

				if(opcode_group[`GROUP_STACK]
				&& opcode_type == `TYPE_POP && signals[`CONTROL_STACK_PREINC] == 1 && sp == stack_pointer[7:0])
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - EX: OK", register_rd);
					end
				else
					begin
						TEST_POP = 1'bx;
						if (signals[`CONTROL_STACK_PREINC] != 1) begin
							$display("POP R%2d - EX: FAILED => signals[`CONTROL_STACK_PREINC]: 1 vs 0", register_rd );
						end
						if (sp !== stack_pointer[7:0]) begin
							$display("POP R%2d - EX: FAILED => sp: (%2H) vs (%2H)", register_rd, stack_pointer[7:0], sp );
						end
					end
			`STAGE_MEM:
				if (opcode_group[`GROUP_STACK] &&
				    opcode_type == `TYPE_POP &&
					 bus_address == {8'd0, address[7:0] - 8'h40})
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - MEM: OK (bus_addr = %2H)", register_rd,  bus_address);
					end
				else
					begin
						TEST_POP = 1'bx;
						$display("POP R%2d - MEM: FAILED => bus_addr: (%2H) vs (%2H)", register_rd, address[7:0] - 8'h40, bus_address);
					end
			`STAGE_WB:
				if (opcode_group[`GROUP_STACK] &&
				    opcode_type == `TYPE_POP &&
					 writeback_value == value[`TEST_DATA_WIDTH-1:0])
				begin
						TEST_POP = 1'b1;
						$display("POP R%2d - WB: OK (R%2d = %3d)", register_rd, register_rd, value);
					end
				else
					begin
						TEST_POP = 1'bx;
						$display("POP R%2d - WB: FAILED => R%2d:(%3d) vs (%3d)", register_rd, register_rd, writeback_value, value);
					end
		endcase
	end
endfunction