data/full_repos/permissive/458113953/LAB 5&6_2019A8PS0621H/Test_Car_FSM.v
1: b'%Error: Cannot find file containing module: 5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n        ... Looked in:\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/458113953/LAB\n%Error: Cannot find file containing module: 5&6_2019A8PS0621H/Test_Car_FSM.v\n%Error: Exiting due to 3 error(s)\n'
module Test_Car_FSM(
    );
    reg left,right;
    reg Clk,Reset;
    wire [5:0] out;
    Car_FSM c1(left,right, Clk, Reset, out);

    initial begin
    Clk=1'b0;
    repeat(32)
    #5 Clk=~Clk;
    $finish;
    end

    initial begin
    Reset=1'b1;
    #9
    Reset=1'b0;
    end

    initial begin
    #40
    left=1;
    right=0;
    #30
    right=1;
    left=0;
    end
endmodule
module Test_Car_FSM(
    );

    reg left,right;
    reg Clk,Reset;
    wire [5:0] out;
    Car_FSM c1(left,right, Clk, Reset, out);

    initial begin
    Clk=1'b0;
    repeat(32)
    #5 Clk=~Clk;
    $finish;
    end

    initial begin
    Reset=1'b1;
    #9
    Reset=1'b0;
    end

    initial begin
    #40
    left=1;
    right=0;
    #30
    right=1;
    left=0;
    end
endmodule