data/full_repos/permissive/446623173/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446623173/tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb.v:77: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~ clk;\n       ^\n%Error: data/full_repos/permissive/446623173/tb.v:44: Cannot find file containing module: \'FourDigitLEDdriver\'\n FourDigitLEDdriver uut (\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/FourDigitLEDdriver\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/FourDigitLEDdriver.v\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/FourDigitLEDdriver.sv\n             FourDigitLEDdriver\n             FourDigitLEDdriver.v\n             FourDigitLEDdriver.sv\n             obj_dir/FourDigitLEDdriver\n             obj_dir/FourDigitLEDdriver.v\n             obj_dir/FourDigitLEDdriver.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;


	reg reset;
	reg clk;
	reg [3:0] hex3;
	reg [3:0] hex2;
	reg [3:0] hex1;
	reg [3:0] hex0;


	wire an3;
	wire an2;
	wire an1;
	wire an0;
	wire [6:0] led_seg;
	wire dp;


	FourDigitLEDdriver uut (
		.reset(reset), 
		.clk(clk), 
		.hex3(hex3), 
		.hex2(hex2), 
		.hex1(hex1), 
		.hex0(hex0), 
		.an3(an3), 
		.an2(an2), 
		.an1(an1), 
		.an0(an0), 
		.led_seg(led_seg), 
		.dp(dp)
	);

	initial begin

		reset = 1;
		clk = 0;
		hex3 = 4;
		hex2 = 5;
		hex1 = 6;
		hex0 = 7;


		#100;
        

		reset=0;
		#10000 $finish;
		
	end
	
always #10 clk = ~ clk;
      
endmodule
module tb;



	reg reset;
	reg clk;
	reg [3:0] hex3;
	reg [3:0] hex2;
	reg [3:0] hex1;
	reg [3:0] hex0;


	wire an3;
	wire an2;
	wire an1;
	wire an0;
	wire [6:0] led_seg;
	wire dp;


	FourDigitLEDdriver uut (
		.reset(reset), 
		.clk(clk), 
		.hex3(hex3), 
		.hex2(hex2), 
		.hex1(hex1), 
		.hex0(hex0), 
		.an3(an3), 
		.an2(an2), 
		.an1(an1), 
		.an0(an0), 
		.led_seg(led_seg), 
		.dp(dp)
	);

	initial begin

		reset = 1;
		clk = 0;
		hex3 = 4;
		hex2 = 5;
		hex1 = 6;
		hex0 = 7;


		#100;
        

		reset=0;
		#10000 $finish;
		
	end
	
always #10 clk = ~ clk;
      
endmodule