data/full_repos/permissive/435516446/MIPS/ALU_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ALU_TEST.v:47: Unsupported: Ignoring delay on this delayed statement.\n always #50 ALUCnt = (ALUCnt+1)% 8;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ALU_TEST.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #25 input1 = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ALU_TEST.v:49: Unsupported: Ignoring delay on this delayed statement.\n always #25 input2 = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ALU_TEST.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #300;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/ALU_TEST.v:38: Cannot find file containing module: \'ALU\'\n ALU uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ALU\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ALU.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_TEST;


	reg [3:0] ALUCnt;
	reg [31:0] input1;
	reg [31:0] input2;
	reg [4:0] shamt;


	wire [31:0] result;
	wire zero;


	ALU uut (
		.ALUCnt(ALUCnt), 
		.input1(input1), 
		.input2(input2), 
		.shamt(shamt), 
		.result(result), 
		.zero(zero)
	);

	always #50 ALUCnt = (ALUCnt+1)% 8;
	always #25 input1 = $random;
	always #25 input2 = $random;
	initial begin

		ALUCnt = 0;
		input1 = 0;
		input2 = 0;
		shamt = 2;


		#300;
        


	end
      
endmodule
module ALU_TEST;



	reg [3:0] ALUCnt;
	reg [31:0] input1;
	reg [31:0] input2;
	reg [4:0] shamt;


	wire [31:0] result;
	wire zero;


	ALU uut (
		.ALUCnt(ALUCnt), 
		.input1(input1), 
		.input2(input2), 
		.shamt(shamt), 
		.result(result), 
		.zero(zero)
	);

	always #50 ALUCnt = (ALUCnt+1)% 8;
	always #25 input1 = $random;
	always #25 input2 = $random;
	initial begin

		ALUCnt = 0;
		input1 = 0;
		input2 = 0;
		shamt = 2;


		#300;
        


	end
      
endmodule