data/full_repos/permissive/444555755/mp4/hvl/top.sv
1: b"%Error: data/full_repos/permissive/444555755/mp4/hvl/top.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport rv32i_types::*; \n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hvl/top.sv:37: syntax error, unexpected iff, expecting ')' or ',' or or\nalways @(posedge itf.clk iff rvfi.commit) rvfi.order <= rvfi.order + 1;  \n                         ^~~\n%Error: Exiting due to 2 error(s)\n"
module mp4_tb;
`timescale 1ns/10ps



tb_itf itf();
rvfi_itf rvfi(itf.clk, itf.rst);


source_tb tb(
    .magic_mem_itf(itf),
    .mem_itf(itf),
    .sm_itf(itf),
    .tb_itf(itf),
    .rvfi(rvfi)
);



bit f;






assign rvfi.commit = 0;

assign rvfi.halt = dut.datapath.load_pc && (dut.datapath.pc_out == dut.datapath.EX_MEM_stage.data.DataWord.pc) &&
                   (dut.datapath.MEM_WB_stage.data.ControlWord.opcode == 0) && 
                   (dut.datapath.EX_MEM_stage.data.ControlWord.br_en == 1 || 
                   dut.datapath.EX_MEM_stage.data.ControlWord.opcode == op_jal ||
                   dut.datapath.EX_MEM_stage.data.ControlWord.opcode == op_jalr);

initial rvfi.order = 0;
always @(posedge itf.clk iff rvfi.commit) rvfi.order <= rvfi.order + 1;












assign itf.registers = '{default: '0};




mp4 dut(    
    .clk(itf.clk),
    .rst(itf.rst),
    .mem_rdata(itf.mem_rdata), 
    .mem_resp(itf.mem_resp), 
    .mem_wdata(itf.mem_wdata), 
    .mem_write(itf.mem_write), 
    .mem_read(itf.mem_read), 
    .mem_addr(itf.mem_addr));





endmodule
module mp4_tb;

`timescale 1ns/10ps



tb_itf itf();
rvfi_itf rvfi(itf.clk, itf.rst);


source_tb tb(
    .magic_mem_itf(itf),
    .mem_itf(itf),
    .sm_itf(itf),
    .tb_itf(itf),
    .rvfi(rvfi)
);



bit f;






assign rvfi.commit = 0;

assign rvfi.halt = dut.datapath.load_pc && (dut.datapath.pc_out == dut.datapath.EX_MEM_stage.data.DataWord.pc) &&
                   (dut.datapath.MEM_WB_stage.data.ControlWord.opcode == 0) && 
                   (dut.datapath.EX_MEM_stage.data.ControlWord.br_en == 1 || 
                   dut.datapath.EX_MEM_stage.data.ControlWord.opcode == op_jal ||
                   dut.datapath.EX_MEM_stage.data.ControlWord.opcode == op_jalr);

initial rvfi.order = 0;
always @(posedge itf.clk iff rvfi.commit) rvfi.order <= rvfi.order + 1;












assign itf.registers = '{default: '0};




mp4 dut(    
    .clk(itf.clk),
    .rst(itf.rst),
    .mem_rdata(itf.mem_rdata), 
    .mem_resp(itf.mem_resp), 
    .mem_wdata(itf.mem_wdata), 
    .mem_write(itf.mem_write), 
    .mem_read(itf.mem_read), 
    .mem_addr(itf.mem_addr));





endmodule