data/full_repos/permissive/439514885/testbench/ram_testbench.v
1: b'%Error: data/full_repos/permissive/439514885/testbench/ram_testbench.v:14: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("ram.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/439514885/testbench/ram_testbench.v:15: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,ram_testbench);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/ram_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk = ~clk;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/ram_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #6 resetB = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/ram_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #25 resetB = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/ram_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n   #500 $finish;\n   ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_testbench();

wire [7:0] data;
wire externalRamCEB;
wire externalRamWEB;
wire externalRamOEB;
wire[18:0] externalRamAddr;

reg clk;
reg resetB;


initial begin
   $dumpfile("ram.vcd");
   $dumpvars(0,ram_testbench);
end


initial begin
   $readmemh("testbench/memory.mem", externalRam.mem);
end


initial begin
   clk = 1'b0;
   resetB = 1'b1;
end

always
  begin
     #5 clk = ~clk;
  end


initial
  begin
    #6 resetB = 1'b0;
    #25 resetB = 1'b1;
  end


initial
   begin
   #500 $finish;
   end

cy62148E externalRam(

    .data(data[7:0]),


    .ce_b(externalRamCEB),
    .we_b(externalRamWEB),
    .oe_b(externalRamOEB),
    .addr(externalRamAddr)
);

ram_loader ram_loader(

   .internalRamAddress(),
   .internalRamWdata(),
   .internalRamCEB(),
   .internalRamWEB(),
   .externalRamCEB(externalRamCEB),
   .externalRamWEB(externalRamWEB),
   .externalRamOEB(externalRamOEB),
   .externalRamAddress(externalRamAddr),


   .clk(clk),
   .resetB(resetB),
   .externalRamReadData(data[7:0])
);

endmodule
module ram_testbench();


wire [7:0] data;
wire externalRamCEB;
wire externalRamWEB;
wire externalRamOEB;
wire[18:0] externalRamAddr;

reg clk;
reg resetB;


initial begin
   $dumpfile("ram.vcd");
   $dumpvars(0,ram_testbench);
end


initial begin
   $readmemh("testbench/memory.mem", externalRam.mem);
end


initial begin
   clk = 1'b0;
   resetB = 1'b1;
end

always
  begin
     #5 clk = ~clk;
  end


initial
  begin
    #6 resetB = 1'b0;
    #25 resetB = 1'b1;
  end


initial
   begin
   #500 $finish;
   end

cy62148E externalRam(

    .data(data[7:0]),


    .ce_b(externalRamCEB),
    .we_b(externalRamWEB),
    .oe_b(externalRamOEB),
    .addr(externalRamAddr)
);

ram_loader ram_loader(

   .internalRamAddress(),
   .internalRamWdata(),
   .internalRamCEB(),
   .internalRamWEB(),
   .externalRamCEB(externalRamCEB),
   .externalRamWEB(externalRamWEB),
   .externalRamOEB(externalRamOEB),
   .externalRamAddress(externalRamAddr),


   .clk(clk),
   .resetB(resetB),
   .externalRamReadData(data[7:0])
);

endmodule