data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v:11: Pin not found: '__pinNumber3'\n    );\n    ^\n%Error: Exiting due to 1 error(s)\n"
module user_module_341457494561784402(
    input  wire [7:0] io_in,
    output wire [7:0] io_out
);
    ChiselWrapper_341457494561784402 chiselwrapper(
        .io_in(io_in),
        .io_out(io_out),
    );

endmodule
module user_module_341457494561784402(
    input  wire [7:0] io_in,
    output wire [7:0] io_out
);

    ChiselWrapper_341457494561784402 chiselwrapper(
        .io_in(io_in),
        .io_out(io_out),
    );

endmodule