data/full_repos/permissive/527249789/src/pc_reg.v
1: b'%Error: data/full_repos/permissive/527249789/src/pc_reg.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:7: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]          epc,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstAddrBus]          epc,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:12: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]          branch_addr,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`InstAddrBus]       pc\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:15: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]       pc\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:18: Define or directive not defined: \'`InstAddrBus\'\nreg[`InstAddrBus] npc;\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstAddrBus] npc;\n                ^\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:20: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable)                       npc = `InitialPC;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:20: Define or directive not defined: \'`InitialPC\'\n    if (resetn == `RstEnable)                       npc = `InitialPC;\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:21: Define or directive not defined: \'`FlushEnable\'\n    else if (flush == `FlushEnable)                 npc = epc;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:31: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable)                       inst_req <= `RequestDisable;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:31: Define or directive not defined: \'`RequestDisable\'\n    if (resetn == `RstEnable)                       inst_req <= `RequestDisable;\n                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:32: Define or directive not defined: \'`FlushEnable\'\n    else if (flush == `FlushEnable)                 inst_req <= `RequestDisable;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:32: Define or directive not defined: \'`RequestDisable\'\n    else if (flush == `FlushEnable)                 inst_req <= `RequestDisable;\n                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:33: Define or directive not defined: \'`RequestDisable\'\n    else if (ibuffer_full == 1\'b1)                  inst_req <= `RequestDisable;\n                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:34: Define or directive not defined: \'`RequestDisable\'\n    else if (inst_req_success == 1\'b1)              inst_req <= `RequestDisable;\n                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:35: Define or directive not defined: \'`AddrOK\'\n    else if (inst_addr_ok == `AddrOK)               inst_req <= `RequestEnable;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/pc_reg.v:35: Define or directive not defined: \'`RequestEnable\'\n    else if (inst_addr_ok == `AddrOK)               inst_req <= `RequestEnable;\n                                                                ^~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module pc_reg(
    input                           clk,
    input                           resetn,
    input                           flush,
    input   [`InstAddrBus]          epc,
    input                           ibuffer_full,
    input                           inst_addr_ok,
    input                           inst_req_success,
    input                           branch_flag,
    input   [`InstAddrBus]          branch_addr,

    output  reg                     inst_req,
    output  reg[`InstAddrBus]       pc
);

reg[`InstAddrBus] npc;
always @(*) begin
    if (resetn == `RstEnable)                       npc = `InitialPC;
    else if (flush == `FlushEnable)                 npc = epc;
    else if (branch_flag)                           npc = branch_addr;
    else if (ibuffer_full == 1'b1)                  npc = pc;
    else if (inst_req_success == 1'b1)              npc = pc + 4;
    else                                            npc = pc;
end

always @(posedge clk) pc <= npc;

always @(posedge clk) begin
    if (resetn == `RstEnable)                       inst_req <= `RequestDisable;
    else if (flush == `FlushEnable)                 inst_req <= `RequestDisable;
    else if (ibuffer_full == 1'b1)                  inst_req <= `RequestDisable;
    else if (inst_req_success == 1'b1)              inst_req <= `RequestDisable;
    else if (inst_addr_ok == `AddrOK)               inst_req <= `RequestEnable;
end

endmodule
module pc_reg(
    input                           clk,
    input                           resetn,
    input                           flush,
    input   [`InstAddrBus]          epc,
    input                           ibuffer_full,
    input                           inst_addr_ok,
    input                           inst_req_success,
    input                           branch_flag,
    input   [`InstAddrBus]          branch_addr,

    output  reg                     inst_req,
    output  reg[`InstAddrBus]       pc
);


reg[`InstAddrBus] npc;
always @(*) begin
    if (resetn == `RstEnable)                       npc = `InitialPC;
    else if (flush == `FlushEnable)                 npc = epc;
    else if (branch_flag)                           npc = branch_addr;
    else if (ibuffer_full == 1'b1)                  npc = pc;
    else if (inst_req_success == 1'b1)              npc = pc + 4;
    else                                            npc = pc;
end

always @(posedge clk) pc <= npc;

always @(posedge clk) begin
    if (resetn == `RstEnable)                       inst_req <= `RequestDisable;
    else if (flush == `FlushEnable)                 inst_req <= `RequestDisable;
    else if (ibuffer_full == 1'b1)                  inst_req <= `RequestDisable;
    else if (inst_req_success == 1'b1)              inst_req <= `RequestDisable;
    else if (inst_addr_ok == `AddrOK)               inst_req <= `RequestEnable;
end

endmodule