data/full_repos/permissive/520811519/rtl/front_turbo/A5004_4.sv
data/verilator_xmls/5a5cdf48-7a6a-45a5-ae2b-7774398aaf7f.xml
module A5004_4(
	input wire YC,
	input wire Y7,
	input wire Y6,
	input wire Y5,
	input wire XC,
	input wire X7,
	input wire X6,
	input wire X5,
	input wire H8,
	input wire Y8,
	input wire V8,
	input wire X8,
	output logic D1,
	output logic D0
);
	logic F15, F16;
	
	assign D1 = ~((~XC & ~X7 & ~X6 & ~X5 & ~F15) |
		          ( XC &  X7 &  X6 &  X5 & ~F15) |
		          ( XC & ~X7 & ~X6 & ~X5 &  F15) |
		          (~XC &  X7 &  X6 &  X5 &  F15));

	assign F15 = ~((~V8 & ~X8) | (V8 & X8));

	assign F16 = ~((~H8 & ~Y8) | (H8 & Y8));

	assign D0 = ~((~YC & ~Y7 & ~Y6 & ~Y5 & ~F16) |
		          ( YC &  Y7 &  Y6 &  Y5 & ~F16) |
		          ( YC & ~Y7 & ~Y6 & ~Y5 &  F16) |
		          (~YC &  Y7 &  Y6 &  Y5 &  F16));
endmodule
module A5004_4(
	input wire YC,
	input wire Y7,
	input wire Y6,
	input wire Y5,
	input wire XC,
	input wire X7,
	input wire X6,
	input wire X5,
	input wire H8,
	input wire Y8,
	input wire V8,
	input wire X8,
	output logic D1,
	output logic D0
);

	logic F15, F16;
	
	assign D1 = ~((~XC & ~X7 & ~X6 & ~X5 & ~F15) |
		          ( XC &  X7 &  X6 &  X5 & ~F15) |
		          ( XC & ~X7 & ~X6 & ~X5 &  F15) |
		          (~XC &  X7 &  X6 &  X5 &  F15));

	assign F15 = ~((~V8 & ~X8) | (V8 & X8));

	assign F16 = ~((~H8 & ~Y8) | (H8 & Y8));

	assign D0 = ~((~YC & ~Y7 & ~Y6 & ~Y5 & ~F16) |
		          ( YC &  Y7 &  Y6 &  Y5 & ~F16) |
		          ( YC & ~Y7 & ~Y6 & ~Y5 &  F16) |
		          (~YC &  Y7 &  Y6 &  Y5 &  F16));
endmodule