data/full_repos/permissive/505514178/source_code/StallingUnit.v
data/verilator_xmls/f017af37-7f07-42b0-8dff-6a63322637ed.xml
module StallingUnit(
	input [4:0] rs1,
	input [4:0] rs2,
	input [4:0] rd,
	input memread,
	output stall
    );

assign stall = ((rd == rs1 || rd == rs2) && memread == 1 && rd != 0)? 1 : 0;

endmodule
module StallingUnit(
	input [4:0] rs1,
	input [4:0] rs2,
	input [4:0] rd,
	input memread,
	output stall
    );


assign stall = ((rd == rs1 || rd == rs2) && memread == 1 && rd != 0)? 1 : 0;

endmodule