data/full_repos/permissive/516759878/RTL/Top_Design.v
1: b"%Error: data/full_repos/permissive/516759878/RTL/Top_Design.v:40: Cannot find file containing module: 'Seven_seg'\nSeven_seg  SEVEN_SEG1(.i_data(S_out) , .seg_out(Sseg_out));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/Seven_seg\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/Seven_seg.v\n             data/full_repos/permissive/516759878/RTL,data/full_repos/permissive/516759878/Seven_seg.sv\n             Seven_seg\n             Seven_seg.v\n             Seven_seg.sv\n             obj_dir/Seven_seg\n             obj_dir/Seven_seg.v\n             obj_dir/Seven_seg.sv\n%Error: data/full_repos/permissive/516759878/RTL/Top_Design.v:41: Cannot find file containing module: 'Clk_div'\nClk_div CLK_1HZ(.i_clk(i_clk) , .clk_div(clk_out)); \n^~~~~~~\n%Error: data/full_repos/permissive/516759878/RTL/Top_Design.v:43: Cannot find file containing module: 'Mux_seven_seg'\nMux_seven_seg MUX(.i_clk(clk_out) ,\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Top_Design(
input i_clk  , 

input [`WIDTH_DATA-1:0] data_in , 
output [`WIDTH_SEG_EN-1:0] an_seg , 
output [`WIDTH_SEG_EN-1:0] a_seg ,  
output [`WIDTH_SEG_OUT-1:0] Sseg_out
    );

assign a_seg = 4'b1111;
wire [`WIDTH_Seg-1:0] S_out ; 
wire clk_out ;
    
    
Seven_seg  SEVEN_SEG1(.i_data(S_out) , .seg_out(Sseg_out));
Clk_div CLK_1HZ(.i_clk(i_clk) , .clk_div(clk_out)); 
    
Mux_seven_seg MUX(.i_clk(clk_out) ,
     .o_seg1(data_in[3:0]) ,
     .o_seg2(data_in[7:4])  , 
     .o_seg3(data_in[11:8]) ,
     .o_seg4(data_in[15:12]) ,
     .o_en(an_seg) ,  
     .o_seg(S_out));

    
    
endmodule
module Top_Design(
input i_clk  , 

input [`WIDTH_DATA-1:0] data_in , 
output [`WIDTH_SEG_EN-1:0] an_seg , 
output [`WIDTH_SEG_EN-1:0] a_seg ,  
output [`WIDTH_SEG_OUT-1:0] Sseg_out
    );


assign a_seg = 4'b1111;
wire [`WIDTH_Seg-1:0] S_out ; 
wire clk_out ;
    
    
Seven_seg  SEVEN_SEG1(.i_data(S_out) , .seg_out(Sseg_out));
Clk_div CLK_1HZ(.i_clk(i_clk) , .clk_div(clk_out)); 
    
Mux_seven_seg MUX(.i_clk(clk_out) ,
     .o_seg1(data_in[3:0]) ,
     .o_seg2(data_in[7:4])  , 
     .o_seg3(data_in[11:8]) ,
     .o_seg4(data_in[15:12]) ,
     .o_en(an_seg) ,  
     .o_seg(S_out));

    
    
endmodule