data/full_repos/permissive/475928601/J Component/mealy.v
1: b'%Error: Cannot find file containing module: Component,data/full_repos/permissive/475928601\n        ... Looked in:\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601.v\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601.sv\n             Component,data/full_repos/permissive/475928601\n             Component,data/full_repos/permissive/475928601.v\n             Component,data/full_repos/permissive/475928601.sv\n             obj_dir/Component,data/full_repos/permissive/475928601\n             obj_dir/Component,data/full_repos/permissive/475928601.v\n             obj_dir/Component,data/full_repos/permissive/475928601.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/475928601/J\n%Error: Cannot find file containing module: Component/mealy.v\n%Error: Exiting due to 3 error(s)\n'
module mealy(
    input clk,
    input reset,
    input in,
    output reg out
);
    reg state, nextState;
    parameter S0 = 0, S1 = 1, S2 = 2;

    initial out = 0;
    
    always @(posedge clk, posedge reset)
        state <= reset ? S0 : nextState;

    always @(state or in) begin
        case (state):
            S0: begin out <= 0; nextState <= in ? S1 : S2; end
            S1: begin out <= 1; nextState <= in ? S1 : S2; end
            S2: begin out <= 0; nextState <= in ? S1 : S2; end
            default: nextState <= S0;
        endcase
    end
endmodule
module mealy(
    input clk,
    input reset,
    input in,
    output reg out
);

    reg state, nextState;
    parameter S0 = 0, S1 = 1, S2 = 2;

    initial out = 0;
    
    always @(posedge clk, posedge reset)
        state <= reset ? S0 : nextState;

    always @(state or in) begin
        case (state):
            S0: begin out <= 0; nextState <= in ? S1 : S2; end
            S1: begin out <= 1; nextState <= in ? S1 : S2; end
            S2: begin out <= 0; nextState <= in ? S1 : S2; end
            default: nextState <= S0;
        endcase
    end
endmodule