data/full_repos/permissive/491294671/timer_input_control/timer_input_control.v
1: b'%Error: data/full_repos/permissive/491294671/timer_input_control/timer_input_control.v:1: Cannot find include file: counter/counter_7.v\n`include "counter/counter_7.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491294671/timer_input_control,data/full_repos/permissive/491294671/counter/counter_7.v\n             data/full_repos/permissive/491294671/timer_input_control,data/full_repos/permissive/491294671/counter/counter_7.v.v\n             data/full_repos/permissive/491294671/timer_input_control,data/full_repos/permissive/491294671/counter/counter_7.v.sv\n             counter/counter_7.v\n             counter/counter_7.v.v\n             counter/counter_7.v.sv\n             obj_dir/counter/counter_7.v\n             obj_dir/counter/counter_7.v.v\n             obj_dir/counter/counter_7.v.sv\n%Error: data/full_repos/permissive/491294671/timer_input_control/timer_input_control.v:2: Cannot find include file: div_100/div_100.v\n`include "div_100/div_100.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491294671/timer_input_control/timer_input_control.v:3: Cannot find include file: encoder/encoder.v\n`include "encoder/encoder.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491294671/timer_input_control/timer_input_control.v:4: Cannot find include file: mux/mux.v\n`include "mux/mux.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module timer_input_control (output wire [3:0] D,
                output wire loadn, pgt_1Hz,
                input wire [9:0] teclado,
                input wire enablen, clock
                );

    wire borda_subida, clear, clock_div; 

  
    encoder encoder(D, loadn, teclado, enablen);
 
    div_100 dividir(clock, clock_div);

    counter_7 delay(clock, loadn, borda_subida);

    mux mux(pgt_1Hz, borda_subida, clock_div, enablen);

endmodule
module timer_input_control (output wire [3:0] D,
                output wire loadn, pgt_1Hz,
                input wire [9:0] teclado,
                input wire enablen, clock
                );


    wire borda_subida, clear, clock_div; 

  
    encoder encoder(D, loadn, teclado, enablen);
 
    div_100 dividir(clock, clock_div);

    counter_7 delay(clock, loadn, borda_subida);

    mux mux(pgt_1Hz, borda_subida, clock_div, enablen);

endmodule