data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/HU.v
data/verilator_xmls/fc1bb51b-7cdd-41d1-afaf-96a85ccc540f.xml
module HU(
    input BranchD,
    input [4:0] rsD,
    input [4:0] rtD,
    input [4:0] rsE,
    input [4:0] rtE,
    input [4:0] RFAE,
    input MtoRFSelE,
    input RFWEE,
    input [4:0] RFAM,
    input RFWEM,
    input [4:0] RFAW,
    input RFWEW,
    output reg Stall,
    output reg ForwardAD,
    output reg ForwardBD,
    output reg Flush,
    output reg [1:0] ForwardAE,
    output reg [1:0] ForwardBE
    );
    
    reg LWStall;
    reg BRStall;


    always@(BranchD or rsD or rtD or rsE or rtE or RFAE or MtoRFSelE or RFWEE or RFAM or RFWEM or RFAW or RFWEW)begin



    

        if ((rsE!=0) && (RFWEM) && (rsE==RFAM)) begin
            ForwardAE <= 2'b10;
        end
        else if((rsE!=0) && (RFWEW) && (rsE==RFAW)) begin
            ForwardAE <= 2'b01;
        end
        else begin
            ForwardAE <= 2'b00;
        end
        

        if ((rtE!=0) && (RFWEM) && (rtE==RFAM)) begin
            ForwardBE <= 2'b10;
        end
        else if((rtE!=0) && (RFWEW) && (rtE==RFAW)) begin
            ForwardBE <= 2'b01;
        end
        else begin
            ForwardBE <= 2'b00;
        end 
        

        LWStall <= (MtoRFSelE) && ((rtE == rsD) || (rtE == rtD));
        
        ForwardAD <= (rsD != 0) && (rsD == RFAM) && RFWEM;
        ForwardBD <= (rtD != 0) && (rtD == RFAM) && RFWEM;
        
        BRStall <= ((rsD == RFAE) || (rtD == RFAE)) && BranchD && RFWEE || 
                   ((rsD == RFAM) || (rtD == RFAM)) && BranchD && MtoRFSelE;
        
        Stall <= LWStall || BRStall;
        Flush <= Stall; 
    end    
endmodule
module HU(
    input BranchD,
    input [4:0] rsD,
    input [4:0] rtD,
    input [4:0] rsE,
    input [4:0] rtE,
    input [4:0] RFAE,
    input MtoRFSelE,
    input RFWEE,
    input [4:0] RFAM,
    input RFWEM,
    input [4:0] RFAW,
    input RFWEW,
    output reg Stall,
    output reg ForwardAD,
    output reg ForwardBD,
    output reg Flush,
    output reg [1:0] ForwardAE,
    output reg [1:0] ForwardBE
    );

    
    reg LWStall;
    reg BRStall;


    always@(BranchD or rsD or rtD or rsE or rtE or RFAE or MtoRFSelE or RFWEE or RFAM or RFWEM or RFAW or RFWEW)begin



    

        if ((rsE!=0) && (RFWEM) && (rsE==RFAM)) begin
            ForwardAE <= 2'b10;
        end
        else if((rsE!=0) && (RFWEW) && (rsE==RFAW)) begin
            ForwardAE <= 2'b01;
        end
        else begin
            ForwardAE <= 2'b00;
        end
        

        if ((rtE!=0) && (RFWEM) && (rtE==RFAM)) begin
            ForwardBE <= 2'b10;
        end
        else if((rtE!=0) && (RFWEW) && (rtE==RFAW)) begin
            ForwardBE <= 2'b01;
        end
        else begin
            ForwardBE <= 2'b00;
        end 
        

        LWStall <= (MtoRFSelE) && ((rtE == rsD) || (rtE == rtD));
        
        ForwardAD <= (rsD != 0) && (rsD == RFAM) && RFWEM;
        ForwardBD <= (rtD != 0) && (rtD == RFAM) && RFWEM;
        
        BRStall <= ((rsD == RFAE) || (rtD == RFAE)) && BranchD && RFWEE || 
                   ((rsD == RFAM) || (rtD == RFAM)) && BranchD && MtoRFSelE;
        
        Stall <= LWStall || BRStall;
        Flush <= Stall; 
    end    
endmodule