data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:31: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:32: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:33: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:56: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:59: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:63: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:63: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:89: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:89: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:91: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:93: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:105: Define or directive not defined: \'`REGFILE_TYPE_FF_2D\'\n   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;\n                                                  ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:108: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:113: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:161: Unsupported or unknown PLI call: $dist_uniform\n consume <= $dist_uniform(seed, 0, 99) < consume_rate;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/verif/mesh_3x3/flit_sink.v:179: Define or directive not defined: \'`ARBITER_TYPE_MATRIX\'\n       .arbiter_type(`ARBITER_TYPE_MATRIX),\n                     ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module flit_sink
  (clk, reset, channel, flow_ctrl, error);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   parameter initial_seed = 0;
   

   parameter consume_rate = 50;
   

   parameter buffer_size = 64;
   

   parameter num_vcs = 8;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam buffer_size_per_vc = buffer_size / num_vcs;
   

   localparam flit_count_width = clogb(buffer_size_per_vc + 1);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   parameter route_info_width = 14;
   

   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter atomic_vc_allocation = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   
   input [0:channel_width-1] channel;
   
   output [0:flow_ctrl_width-1] flow_ctrl;
   wire [0:flow_ctrl_width-1] 	flow_ctrl;
   
   output 			error;
   wire 			error;
   
   integer 			seed = initial_seed;
   
   wire 			flit_valid;
   wire 			flit_head;
   wire [0:num_vcs-1] 		flit_head_ivc;
   wire 			flit_tail;
   wire [0:num_vcs-1] 		flit_tail_ivc;
   wire [0:flit_data_width-1] 	flit_data;
   wire [0:num_vcs-1] 		flit_sel_ivc;
   rtr_channel_input
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .max_payload_length(max_payload_length),
       .min_payload_length(min_payload_length),
       .route_info_width(route_info_width),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   chi
     (.clk(clk),
      .reset(reset),
      .active(1'b1),
      .channel_in(channel),
      .flit_valid_out(flit_valid),
      .flit_head_out(flit_head),
      .flit_head_out_ivc(flit_head_ivc),
      .flit_tail_out(flit_tail),
      .flit_tail_out_ivc(flit_tail_ivc),
      .flit_data_out(flit_data),
      .flit_sel_out_ivc(flit_sel_ivc));
   
   reg 				consume;
   
   always @(posedge clk, posedge reset)
     begin
	consume <= $dist_uniform(seed, 0, 99) < consume_rate;
     end
   
   wire [0:num_vcs-1] empty_ivc;
   
   wire [0:num_vcs-1] req_ivc;
   assign req_ivc = ({num_vcs{flit_valid}} & flit_sel_ivc) | ~empty_ivc;
   
   wire 	      gnt;
   assign gnt = |req_ivc & consume;
   
   wire 	      update;
   assign update = gnt;
   
   wire [0:num_vcs-1] gnt_ivc;
   c_arbiter
     #(.num_ports(num_vcs),
       .num_priorities(1),
       .arbiter_type(`ARBITER_TYPE_MATRIX),
       .reset_type(reset_type))
   gnt_ivc_arb
     (.clk(clk),
      .reset(reset),
      .update(update),
      .active(1'b1),
      .req_pr(req_ivc),
      .gnt_pr(gnt_ivc),
      .gnt());
   
   wire [0:num_vcs*2-1] errors_ivc;
   rtr_flit_buffer
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flit_data_width(flit_data_width),
       .header_info_width(flit_data_width),
       .regfile_type(fb_regfile_type),
       .explicit_pipeline_register(0),
       .gate_buffer_write(0),
       .mgmt_type(fb_mgmt_type),
       .atomic_vc_allocation(atomic_vc_allocation),
       .enable_bypass(1),
       .reset_type(reset_type))
   fb
     (.clk(clk),
      .reset(reset),
      .push_active(1'b1),
      .push_valid(flit_valid),
      .push_sel_ivc(flit_sel_ivc),
      .push_head(flit_head),
      .push_tail(flit_tail),
      .push_data(flit_data),
      .pop_active(1'b1),
      .pop_valid(gnt),
      .pop_sel_ivc(gnt_ivc),
      .pop_data(),
      .pop_tail_ivc(),
      .pop_next_header_info(),
      .almost_empty_ivc(),
      .empty_ivc(empty_ivc),
      .full(),
      .errors_ivc(errors_ivc));
   
   rtr_flow_ctrl_output
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fco
     (.clk(clk),
      .reset(reset),
      .active(1'b1),
      .fc_event_valid_in(update),
      .fc_event_sel_in_ivc(gnt_ivc),
      .flow_ctrl_out(flow_ctrl));
   
   assign error = |errors_ivc;
   
endmodule
module flit_sink
  (clk, reset, channel, flow_ctrl, error);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   parameter initial_seed = 0;
   

   parameter consume_rate = 50;
   

   parameter buffer_size = 64;
   

   parameter num_vcs = 8;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam buffer_size_per_vc = buffer_size / num_vcs;
   

   localparam flit_count_width = clogb(buffer_size_per_vc + 1);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   parameter route_info_width = 14;
   

   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter atomic_vc_allocation = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   
   input [0:channel_width-1] channel;
   
   output [0:flow_ctrl_width-1] flow_ctrl;
   wire [0:flow_ctrl_width-1] 	flow_ctrl;
   
   output 			error;
   wire 			error;
   
   integer 			seed = initial_seed;
   
   wire 			flit_valid;
   wire 			flit_head;
   wire [0:num_vcs-1] 		flit_head_ivc;
   wire 			flit_tail;
   wire [0:num_vcs-1] 		flit_tail_ivc;
   wire [0:flit_data_width-1] 	flit_data;
   wire [0:num_vcs-1] 		flit_sel_ivc;
   rtr_channel_input
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .max_payload_length(max_payload_length),
       .min_payload_length(min_payload_length),
       .route_info_width(route_info_width),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   chi
     (.clk(clk),
      .reset(reset),
      .active(1'b1),
      .channel_in(channel),
      .flit_valid_out(flit_valid),
      .flit_head_out(flit_head),
      .flit_head_out_ivc(flit_head_ivc),
      .flit_tail_out(flit_tail),
      .flit_tail_out_ivc(flit_tail_ivc),
      .flit_data_out(flit_data),
      .flit_sel_out_ivc(flit_sel_ivc));
   
   reg 				consume;
   
   always @(posedge clk, posedge reset)
     begin
	consume <= $dist_uniform(seed, 0, 99) < consume_rate;
     end
   
   wire [0:num_vcs-1] empty_ivc;
   
   wire [0:num_vcs-1] req_ivc;
   assign req_ivc = ({num_vcs{flit_valid}} & flit_sel_ivc) | ~empty_ivc;
   
   wire 	      gnt;
   assign gnt = |req_ivc & consume;
   
   wire 	      update;
   assign update = gnt;
   
   wire [0:num_vcs-1] gnt_ivc;
   c_arbiter
     #(.num_ports(num_vcs),
       .num_priorities(1),
       .arbiter_type(`ARBITER_TYPE_MATRIX),
       .reset_type(reset_type))
   gnt_ivc_arb
     (.clk(clk),
      .reset(reset),
      .update(update),
      .active(1'b1),
      .req_pr(req_ivc),
      .gnt_pr(gnt_ivc),
      .gnt());
   
   wire [0:num_vcs*2-1] errors_ivc;
   rtr_flit_buffer
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flit_data_width(flit_data_width),
       .header_info_width(flit_data_width),
       .regfile_type(fb_regfile_type),
       .explicit_pipeline_register(0),
       .gate_buffer_write(0),
       .mgmt_type(fb_mgmt_type),
       .atomic_vc_allocation(atomic_vc_allocation),
       .enable_bypass(1),
       .reset_type(reset_type))
   fb
     (.clk(clk),
      .reset(reset),
      .push_active(1'b1),
      .push_valid(flit_valid),
      .push_sel_ivc(flit_sel_ivc),
      .push_head(flit_head),
      .push_tail(flit_tail),
      .push_data(flit_data),
      .pop_active(1'b1),
      .pop_valid(gnt),
      .pop_sel_ivc(gnt_ivc),
      .pop_data(),
      .pop_tail_ivc(),
      .pop_next_header_info(),
      .almost_empty_ivc(),
      .empty_ivc(empty_ivc),
      .full(),
      .errors_ivc(errors_ivc));
   
   rtr_flow_ctrl_output
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fco
     (.clk(clk),
      .reset(reset),
      .active(1'b1),
      .fc_event_valid_in(update),
      .fc_event_sel_in_ivc(gnt_ivc),
      .flow_ctrl_out(flow_ctrl));
   
   assign error = |errors_ivc;
   
endmodule