data/full_repos/permissive/501470173/verilog/rtl/shiftbyte.v
data/verilator_xmls/3ceb2ab9-463e-438e-a5eb-8e0a95a3bada.xml
module shiftbyte(
    input [7:0] din,
    output reg [7:0] dshift,
    input [2:0] sh
    );

	always@*
		case (sh)
			0: dshift <= {din[6:0], 1'b0};
			1: dshift <= {din[6:0], din[7]};
			2: dshift <= {1'b0, din[7:1]};
			3: dshift <= {din[0], din[7:1]};
			4: dshift <= din;
			5: dshift <= {din[6:0], 1'b1};
			6: dshift <= {1'b1, din[7:1]};
			default: dshift <= din;
		endcase

endmodule
module shiftbyte(
    input [7:0] din,
    output reg [7:0] dshift,
    input [2:0] sh
    );


	always@*
		case (sh)
			0: dshift <= {din[6:0], 1'b0};
			1: dshift <= {din[6:0], din[7]};
			2: dshift <= {1'b0, din[7:1]};
			3: dshift <= {din[0], din[7:1]};
			4: dshift <= din;
			5: dshift <= {din[6:0], 1'b1};
			6: dshift <= {1'b1, din[7:1]};
			default: dshift <= din;
		endcase

endmodule