data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on basys3)/btn_debouncer.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: basys3),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: basys3)/btn_debouncer.v\n%Error: Exiting due to 9 error(s)\n'
module btn_debouncer(
    input clk_100MHz,
    input btn_in,
    output btn_out
    );
    
    reg temp1, temp2, temp3;
    
    always @(posedge clk_100MHz) begin
        temp1 <= btn_in;
        temp2 <= temp1;
        temp3 <= temp2;
    end
    
    assign btn_out = temp3;
    
endmodule
module btn_debouncer(
    input clk_100MHz,
    input btn_in,
    output btn_out
    );

    
    reg temp1, temp2, temp3;
    
    always @(posedge clk_100MHz) begin
        temp1 <= btn_in;
        temp2 <= temp1;
        temp3 <= temp2;
    end
    
    assign btn_out = temp3;
    
endmodule