data/full_repos/permissive/450769585/testbench.v
1: b'%Error: data/full_repos/permissive/450769585/testbench.v:7: Unsupported or unknown PLI call: $monitor\n $monitor($time," Access=%b,Alarm=%b,Input=%h,Reset=%b",access,alarm,in,reset);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12345678; reset=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h14343542;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h1242adcb;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h1234abcd;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h14343542;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12345678; reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12342378; reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h1234abcd;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12345678;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12acfe38; reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h12345678; reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h1242adcb;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 in=\'h1234abcd; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/450769585/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 $stop;\n ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
wire access,alarm;
reg [31:0]in;
reg reset;
password p0(access,alarm,in,reset);
initial begin
	$monitor($time," Access=%b,Alarm=%b,Input=%h,Reset=%b",access,alarm,in,reset);
end

initial begin
	#10 in='h12345678;	reset=0;
	#10 in='h14343542;
	#10 in='h1242adcb;
	#10 in='h1234abcd;
	#10 in='h14343542;
	#10 in='h12345678;	reset=1;
	#10 in='h12342378;	reset=0;
	#10 in='h1234abcd;
	#10 in='h12345678;
	#10 in='h12acfe38;	reset=1;
	#10 in='h12345678;	reset=0;
	#10 in='h1242adcb;
	#10 in='h1234abcd;	
	#10 $stop;
end
endmodule
module testbench;

wire access,alarm;
reg [31:0]in;
reg reset;
password p0(access,alarm,in,reset);
initial begin
	$monitor($time," Access=%b,Alarm=%b,Input=%h,Reset=%b",access,alarm,in,reset);
end

initial begin
	#10 in='h12345678;	reset=0;
	#10 in='h14343542;
	#10 in='h1242adcb;
	#10 in='h1234abcd;
	#10 in='h14343542;
	#10 in='h12345678;	reset=1;
	#10 in='h12342378;	reset=0;
	#10 in='h1234abcd;
	#10 in='h12345678;
	#10 in='h12acfe38;	reset=1;
	#10 in='h12345678;	reset=0;
	#10 in='h1242adcb;
	#10 in='h1234abcd;	
	#10 $stop;
end
endmodule