data/full_repos/permissive/528831163/tb/boron_env_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_env_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_env_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/528831163/tb/boron_env_tb.v:11: Cannot find file containing module: \'boron_enc\'\n    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), .master_key(master_key), .done(done_enc), .cipher_text(cipher_text));\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc.v\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc.sv\n             boron_enc\n             boron_enc.v\n             boron_enc.sv\n             obj_dir/boron_enc\n             obj_dir/boron_enc.v\n             obj_dir/boron_enc.sv\n%Error: data/full_repos/permissive/528831163/tb/boron_env_tb.v:12: Cannot find file containing module: \'boron_dec\'\n    boron_dec bd(.clk(clk), .rst(rst), .start(done_enc), .plain_text(cipher_text), .master_key(master_key), .done(done_dec), .cipher_text(resulting_text));\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module boron_env ();
    reg clk, rst, start;
    reg [63:0] plain_text;
    reg [79:0] master_key;
    wire done_enc, done_dec;
    wire [63:0] cipher_text, resulting_text;

    always begin
        #5 clk = ~clk;
    end
    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), .master_key(master_key), .done(done_enc), .cipher_text(cipher_text));
    boron_dec bd(.clk(clk), .rst(rst), .start(done_enc), .plain_text(cipher_text), .master_key(master_key), .done(done_dec), .cipher_text(resulting_text));

        initial begin
        clk = 0;
        plain_text = 64'd0;
        master_key = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        
        
    end


endmodule
module boron_env ();

    reg clk, rst, start;
    reg [63:0] plain_text;
    reg [79:0] master_key;
    wire done_enc, done_dec;
    wire [63:0] cipher_text, resulting_text;

    always begin
        #5 clk = ~clk;
    end
    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), .master_key(master_key), .done(done_enc), .cipher_text(cipher_text));
    boron_dec bd(.clk(clk), .rst(rst), .start(done_enc), .plain_text(cipher_text), .master_key(master_key), .done(done_dec), .cipher_text(resulting_text));

        initial begin
        clk = 0;
        plain_text = 64'd0;
        master_key = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        
        
    end


endmodule