data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:9: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:15: Define or directive not defined: \'`RAND_WIDTH\'\n    input  wire [     `RAND_WIDTH-1:0] rand_i,\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:17: Define or directive not defined: \'`H_DISP_LEN\'\n    input  wire [     `H_DISP_LEN-1:0] req_x_addr_i,\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:18: Define or directive not defined: \'`V_DISP_LEN\'\n    input  wire [     `V_DISP_LEN-1:0] req_y_addr_i,\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:24: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    output wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_o,\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:25: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o\n                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:48: Define or directive not defined: \'`ENEMY1_NUM\'\n    wire [               `ENEMY1_NUM-1:0] disappear;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:49: Define or directive not defined: \'`ENEMY1_BRAM_DEPTH_BIT_LEN\'\n    wire [`ENEMY1_BRAM_DEPTH_BIT_LEN-1:0] bram_addr;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:50: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_normal;\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:52: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down1;\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:54: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down2;\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:57: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down3;\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:58: Define or directive not defined: \'`ENEMY1_BRAM_WIDTH\'\n    wire [        `ENEMY1_BRAM_WIDTH-1:0] bram_info;\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:60: Define or directive not defined: \'`ENEMY1_NUM_BIT_LEN\'\n    wire [       `ENEMY1_NUM_BIT_LEN-1:0] curr_enemy_idx;\n                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:62: Define or directive not defined: \'`ENEMY1_STATE_REG_WIDTH\'\n    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] state_unit       [`ENEMY1_NUM-1:0];\n             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:62: Define or directive not defined: \'`ENEMY1_NUM\'\n    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] state_unit       [`ENEMY1_NUM-1:0];\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:63: Define or directive not defined: \'`ENEMY1_STATE_REG_WIDTH\'\n    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] n_state_unit     [`ENEMY1_NUM-1:0];\n             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:63: Define or directive not defined: \'`ENEMY1_NUM\'\n    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] n_state_unit     [`ENEMY1_NUM-1:0];\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:65: Define or directive not defined: \'`ENEMY1_CNT_MAX_TRIGGER_BIT_LEN\'\n    reg  [`ENEMY1_CNT_MAX_TRIGGER_BIT_LEN-1:0] cnt_trigger;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:66: Define or directive not defined: \'`ENEMY_CNT_MAX_DOWN_BIT_LEN\'\n    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:71: Define or directive not defined: \'`ENEMY1_NUM_BIT_LEN\'\n    wire [`ENEMY1_NUM_BIT_LEN-1:0]        trigger_idx;\n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:73: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    reg  [          `COLOR_RGB_DEPTH-1:0] vga_rgb;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:74: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    wire [      `ADD_SCORE_BIT_WIDTH-1:0] disappear_num;\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:78: Define or directive not defined: \'`ENEMY1_NUM\'\n        .MAX_ENEMY_NUM(`ENEMY1_NUM),\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:79: Define or directive not defined: \'`ENEMY1_NUM_BIT_LEN\'\n        .MAX_ENEMY_NUM_BIT_LEN(`ENEMY1_NUM_BIT_LEN),\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:80: Define or directive not defined: \'`ENEMY1_SPEED_LOW\'\n        .SPEED(`ENEMY1_SPEED_LOW),\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:82: Define or directive not defined: \'`ENEMY1_CNT_MAX_TRIGGER\'\n        .ENEMY_CNT_MAX_TRIGGER(`ENEMY1_CNT_MAX_TRIGGER),\n                               ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:83: Define or directive not defined: \'`ENEMY1_X_SIZE\'\n        .ENEMY_X_SIZE(`ENEMY1_X_SIZE),\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:84: Define or directive not defined: \'`ENEMY1_Y_SIZE\'\n        .ENEMY_Y_SIZE(`ENEMY1_Y_SIZE),\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:85: Define or directive not defined: \'`OBJ_X_POS_BIT_LEN\'\n        .RAND_POS_BIT_LEN(`OBJ_X_POS_BIT_LEN-1),\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:86: Define or directive not defined: \'`ENEMY1_SLOW_RAND_OFFSET\'\n        .RAND_OFFSET(`ENEMY1_SLOW_RAND_OFFSET),\n                     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:87: Define or directive not defined: \'`ENEMY1_BRAM_WIDTH\'\n        .BRAM_WIDTH(`ENEMY1_BRAM_WIDTH),\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:88: Define or directive not defined: \'`ENEMY1_BRAM_DEPTH\'\n        .BRAM_DEPTH(`ENEMY1_BRAM_DEPTH),\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:89: Define or directive not defined: \'`ENEMY1_BRAM_DEPTH_BIT_LEN\'\n        .BRAM_DEPTH_BIT_LEN(`ENEMY1_BRAM_DEPTH_BIT_LEN)\n                            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:128: Define or directive not defined: \'`ENEMY_CNT_MAX_DOWN\'\n            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin\n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:177: Define or directive not defined: \'`ENEMY1_NUM\'\n        for(i=0;i<`ENEMY1_NUM;i=i+1)begin: loop\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:177: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for(i=0;i<`ENEMY1_NUM;i=i+1)begin: loop\n                             ^\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:192: syntax error, unexpected IDENTIFIER\n                        n_state_unit[i] = state_change ? STATE_DOWN2 : STATE_DOWN1;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:194: syntax error, unexpected IDENTIFIER\n                        n_state_unit[i] = state_change ? STATE_DOWN3 : STATE_DOWN2;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:196: syntax error, unexpected IDENTIFIER\n                        n_state_unit[i] = state_change ? STATE_UNVISUAL : STATE_DOWN3;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy1_slow.v:198: syntax error, unexpected IDENTIFIER\n                        n_state_unit[i] = (trigger && trigger_idx == i) ? STATE_NORMAL : STATE_UNVISUAL;\n                        ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module enemy1_slow (
    input  wire                        clk_run,
    input  wire                        clk_vga,
    input  wire                        rst,
    input  wire                        en_i,
    input  wire [     `RAND_WIDTH-1:0] rand_i,
    input  wire                        v_sync_i,
    input  wire [     `H_DISP_LEN-1:0] req_x_addr_i,
    input  wire [     `V_DISP_LEN-1:0] req_y_addr_i,
    input  wire                        crash_enemy_bullet_i,
    input  wire                        crash_me_enemy_i,
    input  wire                        bomb_i,

    output wire                        vga_alpha_o,
    output wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_o,
    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o
);



    localparam STATE_NORMAL = 3'b101;
    localparam STATE_DOWN1 = 3'b110;
    localparam STATE_DOWN2 = 3'b010;
    localparam STATE_DOWN3 = 3'b011;
    localparam STATE_UNVISUAL = 3'b111;


    wire [               `ENEMY1_NUM-1:0] disappear;
    wire [`ENEMY1_BRAM_DEPTH_BIT_LEN-1:0] bram_addr;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_normal;
    wire                                  bram_alpha_normal;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down1;
    wire                                  bram_alpha_down1;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down2;
    wire                                  bram_alpha_down2;
    wire                                  bram_alpha_down3;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down3;
    wire [        `ENEMY1_BRAM_WIDTH-1:0] bram_info;
    wire                                  enemy_vali;
    wire [       `ENEMY1_NUM_BIT_LEN-1:0] curr_enemy_idx;

    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] state_unit       [`ENEMY1_NUM-1:0];
    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] n_state_unit     [`ENEMY1_NUM-1:0];

    reg  [`ENEMY1_CNT_MAX_TRIGGER_BIT_LEN-1:0] cnt_trigger;
    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;

    reg                                   state_change;

    wire                                  trigger;
    wire [`ENEMY1_NUM_BIT_LEN-1:0]        trigger_idx;
    reg                                   vga_alpha;
    reg  [          `COLOR_RGB_DEPTH-1:0] vga_rgb;
    wire [      `ADD_SCORE_BIT_WIDTH-1:0] disappear_num;

    enemy_base
    #(
        .MAX_ENEMY_NUM(`ENEMY1_NUM),
        .MAX_ENEMY_NUM_BIT_LEN(`ENEMY1_NUM_BIT_LEN),
        .SPEED(`ENEMY1_SPEED_LOW),

        .ENEMY_CNT_MAX_TRIGGER(`ENEMY1_CNT_MAX_TRIGGER),
        .ENEMY_X_SIZE(`ENEMY1_X_SIZE),
        .ENEMY_Y_SIZE(`ENEMY1_Y_SIZE),
        .RAND_POS_BIT_LEN(`OBJ_X_POS_BIT_LEN-1),
        .RAND_OFFSET(`ENEMY1_SLOW_RAND_OFFSET),
        .BRAM_WIDTH(`ENEMY1_BRAM_WIDTH),
        .BRAM_DEPTH(`ENEMY1_BRAM_DEPTH),
        .BRAM_DEPTH_BIT_LEN(`ENEMY1_BRAM_DEPTH_BIT_LEN)
    ) enemy1_slow
    (
        .clk_vga(clk_vga),
        .clk_run(clk_run),
        .rst(rst),
        .en_i(en_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .disappear_i(disappear),
        .rand_pos_i(rand_i),
        .bram_addr_o(bram_addr),
        .enemy_vali_o(enemy_vali),
        .curr_enemy_idx_o(curr_enemy_idx),
        .trigger_o(trigger),
        .trigger_idx_o(trigger_idx),
        .disappear_num_o(disappear_num)
    );

    assign add_score_o = disappear_num;

    bram_enemy1 bram_enemy1_slow
    (
        .clka(clk_vga),
        .ena(1'b1),
        .addra(bram_addr),
        .douta(bram_info)
    );

    assign {bram_alpha_normal, bram_gray_normal,
        bram_alpha_down1, bram_gray_down1,
        bram_alpha_down2, bram_gray_down2,
        bram_alpha_down3, bram_gray_down3} = bram_info;

    always @(posedge clk_vga or posedge rst)begin
        if(rst) begin
            cnt_down <= 0;
        end else begin
            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin
                state_change <= 1;
                cnt_down <= 0;
            end else begin
                state_change <= 0;
                cnt_down <= cnt_down + 1;
            end
        end
    end

    always @(*) begin
        if(enemy_vali) begin
            case(state_unit[curr_enemy_idx])
                STATE_NORMAL:begin
                    vga_alpha = bram_alpha_normal;
                    vga_rgb   = {3{bram_gray_normal}};
                end
                STATE_DOWN1:begin
                    vga_alpha = bram_alpha_down1;
                    vga_rgb   = {3{bram_gray_down1}};
                end
                STATE_DOWN2:begin
                    vga_alpha = bram_alpha_down2;
                    vga_rgb   = {3{bram_gray_down2}};
                end
                STATE_DOWN3:begin
                    vga_alpha = bram_alpha_down3;
                    vga_rgb   = {3{bram_gray_down3}};
                end
                STATE_UNVISUAL:begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
                default: begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
            endcase
        end else begin
            vga_alpha = 0;
            vga_rgb   = 0;
        end
    end

    assign vga_alpha_o = vga_alpha;
    assign vga_rgb_o   = vga_rgb;

    genvar i;
    generate
        for(i=0;i<`ENEMY1_NUM;i=i+1)begin: loop
            always @(posedge clk_vga or posedge rst) begin
                if(rst)begin
                    state_unit[i] <= STATE_NORMAL;
                end else begin
                    state_unit[i] <= n_state_unit[i];
                end
            end

            always @(*)begin
                case(state_unit[i])
                    STATE_NORMAL:
                        n_state_unit[i] = ((crash_enemy_bullet_i || crash_me_enemy_i) && i == curr_enemy_idx || bomb_i) ?
                                         STATE_DOWN1 : STATE_NORMAL;
                    STATE_DOWN1:
                        n_state_unit[i] = state_change ? STATE_DOWN2 : STATE_DOWN1;
                    STATE_DOWN2:
                        n_state_unit[i] = state_change ? STATE_DOWN3 : STATE_DOWN2;
                    STATE_DOWN3:
                        n_state_unit[i] = state_change ? STATE_UNVISUAL : STATE_DOWN3;
                    STATE_UNVISUAL:
                        n_state_unit[i] = (trigger && trigger_idx == i) ? STATE_NORMAL : STATE_UNVISUAL;
                    default:
                        n_state_unit[i] = STATE_UNVISUAL;
                endcase
            end
    

            assign disappear[i] = state_unit[i] == STATE_DOWN3 && state_change;
        end
    endgenerate

endmodule
module enemy1_slow (
    input  wire                        clk_run,
    input  wire                        clk_vga,
    input  wire                        rst,
    input  wire                        en_i,
    input  wire [     `RAND_WIDTH-1:0] rand_i,
    input  wire                        v_sync_i,
    input  wire [     `H_DISP_LEN-1:0] req_x_addr_i,
    input  wire [     `V_DISP_LEN-1:0] req_y_addr_i,
    input  wire                        crash_enemy_bullet_i,
    input  wire                        crash_me_enemy_i,
    input  wire                        bomb_i,

    output wire                        vga_alpha_o,
    output wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_o,
    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o
);




    localparam STATE_NORMAL = 3'b101;
    localparam STATE_DOWN1 = 3'b110;
    localparam STATE_DOWN2 = 3'b010;
    localparam STATE_DOWN3 = 3'b011;
    localparam STATE_UNVISUAL = 3'b111;


    wire [               `ENEMY1_NUM-1:0] disappear;
    wire [`ENEMY1_BRAM_DEPTH_BIT_LEN-1:0] bram_addr;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_normal;
    wire                                  bram_alpha_normal;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down1;
    wire                                  bram_alpha_down1;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down2;
    wire                                  bram_alpha_down2;
    wire                                  bram_alpha_down3;
    wire [         `COLOR_GRAY_DEPTH-1:0] bram_gray_down3;
    wire [        `ENEMY1_BRAM_WIDTH-1:0] bram_info;
    wire                                  enemy_vali;
    wire [       `ENEMY1_NUM_BIT_LEN-1:0] curr_enemy_idx;

    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] state_unit       [`ENEMY1_NUM-1:0];
    reg  [   `ENEMY1_STATE_REG_WIDTH-1:0] n_state_unit     [`ENEMY1_NUM-1:0];

    reg  [`ENEMY1_CNT_MAX_TRIGGER_BIT_LEN-1:0] cnt_trigger;
    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;

    reg                                   state_change;

    wire                                  trigger;
    wire [`ENEMY1_NUM_BIT_LEN-1:0]        trigger_idx;
    reg                                   vga_alpha;
    reg  [          `COLOR_RGB_DEPTH-1:0] vga_rgb;
    wire [      `ADD_SCORE_BIT_WIDTH-1:0] disappear_num;

    enemy_base
    #(
        .MAX_ENEMY_NUM(`ENEMY1_NUM),
        .MAX_ENEMY_NUM_BIT_LEN(`ENEMY1_NUM_BIT_LEN),
        .SPEED(`ENEMY1_SPEED_LOW),

        .ENEMY_CNT_MAX_TRIGGER(`ENEMY1_CNT_MAX_TRIGGER),
        .ENEMY_X_SIZE(`ENEMY1_X_SIZE),
        .ENEMY_Y_SIZE(`ENEMY1_Y_SIZE),
        .RAND_POS_BIT_LEN(`OBJ_X_POS_BIT_LEN-1),
        .RAND_OFFSET(`ENEMY1_SLOW_RAND_OFFSET),
        .BRAM_WIDTH(`ENEMY1_BRAM_WIDTH),
        .BRAM_DEPTH(`ENEMY1_BRAM_DEPTH),
        .BRAM_DEPTH_BIT_LEN(`ENEMY1_BRAM_DEPTH_BIT_LEN)
    ) enemy1_slow
    (
        .clk_vga(clk_vga),
        .clk_run(clk_run),
        .rst(rst),
        .en_i(en_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .disappear_i(disappear),
        .rand_pos_i(rand_i),
        .bram_addr_o(bram_addr),
        .enemy_vali_o(enemy_vali),
        .curr_enemy_idx_o(curr_enemy_idx),
        .trigger_o(trigger),
        .trigger_idx_o(trigger_idx),
        .disappear_num_o(disappear_num)
    );

    assign add_score_o = disappear_num;

    bram_enemy1 bram_enemy1_slow
    (
        .clka(clk_vga),
        .ena(1'b1),
        .addra(bram_addr),
        .douta(bram_info)
    );

    assign {bram_alpha_normal, bram_gray_normal,
        bram_alpha_down1, bram_gray_down1,
        bram_alpha_down2, bram_gray_down2,
        bram_alpha_down3, bram_gray_down3} = bram_info;

    always @(posedge clk_vga or posedge rst)begin
        if(rst) begin
            cnt_down <= 0;
        end else begin
            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin
                state_change <= 1;
                cnt_down <= 0;
            end else begin
                state_change <= 0;
                cnt_down <= cnt_down + 1;
            end
        end
    end

    always @(*) begin
        if(enemy_vali) begin
            case(state_unit[curr_enemy_idx])
                STATE_NORMAL:begin
                    vga_alpha = bram_alpha_normal;
                    vga_rgb   = {3{bram_gray_normal}};
                end
                STATE_DOWN1:begin
                    vga_alpha = bram_alpha_down1;
                    vga_rgb   = {3{bram_gray_down1}};
                end
                STATE_DOWN2:begin
                    vga_alpha = bram_alpha_down2;
                    vga_rgb   = {3{bram_gray_down2}};
                end
                STATE_DOWN3:begin
                    vga_alpha = bram_alpha_down3;
                    vga_rgb   = {3{bram_gray_down3}};
                end
                STATE_UNVISUAL:begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
                default: begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
            endcase
        end else begin
            vga_alpha = 0;
            vga_rgb   = 0;
        end
    end

    assign vga_alpha_o = vga_alpha;
    assign vga_rgb_o   = vga_rgb;

    genvar i;
    generate
        for(i=0;i<`ENEMY1_NUM;i=i+1)begin: loop
            always @(posedge clk_vga or posedge rst) begin
                if(rst)begin
                    state_unit[i] <= STATE_NORMAL;
                end else begin
                    state_unit[i] <= n_state_unit[i];
                end
            end

            always @(*)begin
                case(state_unit[i])
                    STATE_NORMAL:
                        n_state_unit[i] = ((crash_enemy_bullet_i || crash_me_enemy_i) && i == curr_enemy_idx || bomb_i) ?
                                         STATE_DOWN1 : STATE_NORMAL;
                    STATE_DOWN1:
                        n_state_unit[i] = state_change ? STATE_DOWN2 : STATE_DOWN1;
                    STATE_DOWN2:
                        n_state_unit[i] = state_change ? STATE_DOWN3 : STATE_DOWN2;
                    STATE_DOWN3:
                        n_state_unit[i] = state_change ? STATE_UNVISUAL : STATE_DOWN3;
                    STATE_UNVISUAL:
                        n_state_unit[i] = (trigger && trigger_idx == i) ? STATE_NORMAL : STATE_UNVISUAL;
                    default:
                        n_state_unit[i] = STATE_UNVISUAL;
                endcase
            end
    

            assign disappear[i] = state_unit[i] == STATE_DOWN3 && state_change;
        end
    endgenerate

endmodule