data/full_repos/permissive/522187840/PE.v
data/verilator_xmls/59b3bda9-12b2-4fb9-9ab6-4c846fe3a735.xml
module PE(a,b,c,a1,b1,out,clock);

parameter n = 31;

input [n:0] a,b,c; 
output  [n:0] a1,b1;
input clock;

output [n:0] out;
reg [n:0] a1,b1;
reg [n:0] out;



function [n:0] allocate(input [n:0] a);
    begin
        allocate = 2*a-a;
    end
endfunction

function [n:0] func(input [n:0] a,b,c);
    begin
        func = c+a*b;
    end
endfunction







always @(posedge clock)
begin
	a1 <= allocate(a);
	b1 <= allocate(b);

    out <= func(a,b,c);

end

endmodule
module PE(a,b,c,a1,b1,out,clock);


parameter n = 31;

input [n:0] a,b,c; 
output  [n:0] a1,b1;
input clock;

output [n:0] out;
reg [n:0] a1,b1;
reg [n:0] out;



function [n:0] allocate(input [n:0] a);
    begin
        allocate = 2*a-a;
    end
endfunction

function [n:0] func(input [n:0] a,b,c);
    begin
        func = c+a*b;
    end
endfunction







always @(posedge clock)
begin
	a1 <= allocate(a);
	b1 <= allocate(b);

    out <= func(a,b,c);

end

endmodule