data/full_repos/permissive/447976230/fpga/usrp1/models/fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/models/fifo.v:75: Operator EQ expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'wrusedw\' generates 10 bits.\n                                                                                : ... In instance fifo\n   assign wrfull = (wrusedw == depth-1);\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/models/fifo.v:78: Operator EQ expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'rdusedw\' generates 10 bits.\n                                                                                : ... In instance fifo\n   assign rdfull = (rdusedw == depth-1);\n                            ^~\n%Error: Exiting due to 2 warning(s)\n'
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
   
   parameter width = 16;
   parameter depth = 1024;
   parameter addr_bits = 10;
   

   
   input [width-1:0] data;
   input 	     wrreq;
   input 	     rdreq;
   input 	     rdclk;
   input 	     wrclk;
   input 	     aclr;
   output [width-1:0] q;
   output 	      rdfull;
   output 	      rdempty;
   output reg [addr_bits-1:0]  rdusedw;
   output wrfull;
   output wrempty;
   output reg [addr_bits-1:0]  wrusedw;
   
   reg [width-1:0] mem [0:depth-1];
   reg [addr_bits-1:0] 	      rdptr;
   reg [addr_bits-1:0] 	      wrptr;
   
`ifdef rd_req
   reg [width-1:0]    q;
`else
   wire [width-1:0]   q;
`endif
   
   integer 	      i;
   
   always @( aclr)
     begin
	wrptr <= #1 0;
	rdptr <= #1 0;
	for(i=0;i<depth;i=i+1)
	  mem[i] <= #1 0;
     end
   
   always @(posedge wrclk)
     if(wrreq)
       begin
	  wrptr <= #1 wrptr+1;
	  mem[wrptr] <= #1 data;
       end
   
   always @(posedge rdclk)
     if(rdreq)
       begin
   	  rdptr <= #1 rdptr+1;
`ifdef rd_req
	  q <= #1 mem[rdptr];
`endif
       end
   
`ifdef rd_req
`else
   assign q = mem[rdptr];
`endif
   

   always @(posedge wrclk)
     wrusedw <= #1 wrptr - rdptr;
   
   always @(posedge rdclk)
     rdusedw <= #1 wrptr - rdptr;
   
   assign wrempty = (wrusedw == 0);
   assign wrfull = (wrusedw == depth-1);
   
   assign rdempty = (rdusedw == 0);
   assign rdfull = (rdusedw == depth-1);
   
endmodule
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);

   
   parameter width = 16;
   parameter depth = 1024;
   parameter addr_bits = 10;
   

   
   input [width-1:0] data;
   input 	     wrreq;
   input 	     rdreq;
   input 	     rdclk;
   input 	     wrclk;
   input 	     aclr;
   output [width-1:0] q;
   output 	      rdfull;
   output 	      rdempty;
   output reg [addr_bits-1:0]  rdusedw;
   output wrfull;
   output wrempty;
   output reg [addr_bits-1:0]  wrusedw;
   
   reg [width-1:0] mem [0:depth-1];
   reg [addr_bits-1:0] 	      rdptr;
   reg [addr_bits-1:0] 	      wrptr;
   
`ifdef rd_req
   reg [width-1:0]    q;
`else
   wire [width-1:0]   q;
`endif
   
   integer 	      i;
   
   always @( aclr)
     begin
	wrptr <= #1 0;
	rdptr <= #1 0;
	for(i=0;i<depth;i=i+1)
	  mem[i] <= #1 0;
     end
   
   always @(posedge wrclk)
     if(wrreq)
       begin
	  wrptr <= #1 wrptr+1;
	  mem[wrptr] <= #1 data;
       end
   
   always @(posedge rdclk)
     if(rdreq)
       begin
   	  rdptr <= #1 rdptr+1;
`ifdef rd_req
	  q <= #1 mem[rdptr];
`endif
       end
   
`ifdef rd_req
`else
   assign q = mem[rdptr];
`endif
   

   always @(posedge wrclk)
     wrusedw <= #1 wrptr - rdptr;
   
   always @(posedge rdclk)
     rdusedw <= #1 wrptr - rdptr;
   
   assign wrempty = (wrusedw == 0);
   assign wrfull = (wrusedw == depth-1);
   
   assign rdempty = (rdusedw == 0);
   assign rdfull = (rdusedw == depth-1);
   
endmodule