data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:52: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:58: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:60: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    output reg [`REG_FNUM_WIDTH-1:0] vib_val\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:65: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire [`REG_FNUM_WIDTH-1:0] delta0;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:66: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire [`REG_FNUM_WIDTH-1:0] delta1;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/vibrato.v:67: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire [`REG_FNUM_WIDTH-1:0] delta2;\n          ^~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module vibrato (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,   
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire dvb,    
    output reg [`REG_FNUM_WIDTH-1:0] vib_val
);
    localparam VIBRATO_INDEX_WIDTH = 13;
    
    reg [VIBRATO_INDEX_WIDTH-1:0] vibrato_index = 0;
    wire [`REG_FNUM_WIDTH-1:0] delta0;
    wire [`REG_FNUM_WIDTH-1:0] delta1;
    wire [`REG_FNUM_WIDTH-1:0] delta2;
        

    always @(posedge clk)
        if (reset)
            vibrato_index <= 0;
        else if (sample_clk_en)
            vibrato_index <= vibrato_index + 1;
        
    assign delta0 = fnum >> 7;
    assign delta1 = ((vibrato_index >> 10) & 3) == 3 ? delta0 >> 1 : delta0;
    assign delta2 = !dvb ? delta1 >> 1 : delta1;
    
    always @(posedge clk)
        if (reset)
            vib_val <= 0;
        else
            vib_val <= ((vibrato_index >> 10) & 4) != 0 ? ~delta2 : delta2;
endmodule
module vibrato (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,   
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire dvb,    
    output reg [`REG_FNUM_WIDTH-1:0] vib_val
);

    localparam VIBRATO_INDEX_WIDTH = 13;
    
    reg [VIBRATO_INDEX_WIDTH-1:0] vibrato_index = 0;
    wire [`REG_FNUM_WIDTH-1:0] delta0;
    wire [`REG_FNUM_WIDTH-1:0] delta1;
    wire [`REG_FNUM_WIDTH-1:0] delta2;
        

    always @(posedge clk)
        if (reset)
            vibrato_index <= 0;
        else if (sample_clk_en)
            vibrato_index <= vibrato_index + 1;
        
    assign delta0 = fnum >> 7;
    assign delta1 = ((vibrato_index >> 10) & 3) == 3 ? delta0 >> 1 : delta0;
    assign delta2 = !dvb ? delta1 >> 1 : delta1;
    
    always @(posedge clk)
        if (reset)
            vib_val <= 0;
        else
            vib_val <= ((vibrato_index >> 10) & 4) != 0 ? ~delta2 : delta2;
endmodule