data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:52: Cannot find include file: ../opl3.vh\n`include "../opl3.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.sv\n             ../opl3.vh\n             ../opl3.vh.v\n             ../opl3.vh.sv\n             obj_dir/../opl3.vh\n             obj_dir/../opl3.vh.v\n             obj_dir/../opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:57: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:58: Define or directive not defined: \'`REG_MULT_WIDTH\'\n    input wire [`REG_MULT_WIDTH-1:0] mult,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:59: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:62: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:64: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:65: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult = 0;\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/calc_phase_inc.v:67: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;\n                 ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module calc_phase_inc (
    input wire clk,
    input wire sample_clk_en,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire vib,
    input wire dvb,
    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc
);   
    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;
    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult = 0;
    
    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;
    
    assign pre_mult = fnum << block;
    
    always @(posedge clk)
        case (mult)
        'h0: post_mult <= pre_mult >> 1;
        'h1: post_mult <= pre_mult;
        'h2: post_mult <= pre_mult*2;
        'h3: post_mult <= pre_mult*3;
        'h4: post_mult <= pre_mult*4;
        'h5: post_mult <= pre_mult*5;
        'h6: post_mult <= pre_mult*6;
        'h7: post_mult <= pre_mult*7;
        'h8: post_mult <= pre_mult*8;
        'h9: post_mult <= pre_mult*9;
        'hA: post_mult <= pre_mult*10;
        'hB: post_mult <= pre_mult*10;
        'hC: post_mult <= pre_mult*12;
        'hD: post_mult <= pre_mult*12;
        'hE: post_mult <= pre_mult*15;
        'hF: post_mult <= pre_mult*15;
        endcase
    
    always @ *
        if (vib)
            phase_inc = post_mult + vib_val;
        else
            phase_inc = post_mult;
    

    vibrato vibrato (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .dvb(dvb),
        .vib_val(vib_val)
    );
endmodule
module calc_phase_inc (
    input wire clk,
    input wire sample_clk_en,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire vib,
    input wire dvb,
    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc
);
   
    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;
    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult = 0;
    
    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;
    
    assign pre_mult = fnum << block;
    
    always @(posedge clk)
        case (mult)
        'h0: post_mult <= pre_mult >> 1;
        'h1: post_mult <= pre_mult;
        'h2: post_mult <= pre_mult*2;
        'h3: post_mult <= pre_mult*3;
        'h4: post_mult <= pre_mult*4;
        'h5: post_mult <= pre_mult*5;
        'h6: post_mult <= pre_mult*6;
        'h7: post_mult <= pre_mult*7;
        'h8: post_mult <= pre_mult*8;
        'h9: post_mult <= pre_mult*9;
        'hA: post_mult <= pre_mult*10;
        'hB: post_mult <= pre_mult*10;
        'hC: post_mult <= pre_mult*12;
        'hD: post_mult <= pre_mult*12;
        'hE: post_mult <= pre_mult*15;
        'hF: post_mult <= pre_mult*15;
        endcase
    
    always @ *
        if (vib)
            phase_inc = post_mult + vib_val;
        else
            phase_inc = post_mult;
    

    vibrato vibrato (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .dvb(dvb),
        .vib_val(vib_val)
    );
endmodule