data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Latches and Flip-Flops/Edge capture register.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Edge\n%Error: Cannot find file containing module: capture\n%Error: Cannot find file containing module: register.v\n%Error: Exiting due to 7 error(s)\n'
module test (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] in_reg;

    always @(posedge clk) begin
        in_reg <= in;

        if (reset) begin
            out_temp <= 32'b0;
        end else begin
            out_temp <= ~in & in_reg | out; 



        end
    end
endmodule
module test (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] in_reg;

    always @(posedge clk) begin
        in_reg <= in;

        if (reset) begin
            out_temp <= 32'b0;
        end else begin
            out_temp <= ~in & in_reg | out; 



        end
    end
endmodule