data/full_repos/permissive/486367830/debug/top_debug/deb_src/mem_1rw.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486367830/debug/top_debug/deb_src/mem_1rw.v:35: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 512 bits.\n                                                                                         : ... In instance mem_1rw\nassign ext_be = {8*WORD_BYTES{be}};\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486367830/debug/top_debug/deb_src/mem_1rw.v:46: Unsized constant being X/Z extended to 64 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                         : ... In instance mem_1rw\n                rd_data <= \'bx;              \n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/486367830/debug/top_debug/deb_src/mem_1rw.v:77: Operator GTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n                                                                                         : ... In instance mem_1rw\n  if (ce & (addr >= MEM_DEPTH)) begin\n                 ^~\n%Error: Exiting due to 3 warning(s)\n'
module mem_1rw  #(
parameter  ADDR_WIDTH = 8   ,
parameter  MEM_DEPTH  = 256 ,
parameter  WORD_BYTES =  8
)(
input                             clk       ,
input                             ce        ,
input                             we        ,
input       [ADDR_WIDTH   -1 : 0] addr      ,
input       [8*WORD_BYTES -1 : 0] wr_data   ,
input       [WORD_BYTES   -1 : 0] be        ,
output reg  [8*WORD_BYTES -1 : 0] rd_data
);

reg         [8*WORD_BYTES -1 : 0] mem[MEM_DEPTH -1 : 0];


wire [8*WORD_BYTES -1:0] ext_be ;

assign ext_be = {8*WORD_BYTES{be}};


always @(posedge clk)
if (ce & we) 
  mem[addr] <=  (mem[addr] & (~ext_be)) |
                (wr_data   &   ext_be );


always @(posedge clk)
if (ce & (~we)) rd_data <= mem[addr]; else
                rd_data <= 'bx;


integer    idx ;
initial begin

  if (MEM_DEPTH > (1 << ADDR_WIDTH)) begin
    $display("%M EROARE: MEM_DEPTH=%0d, maximum=%0d", 
      MEM_DEPTH, (1 << ADDR_WIDTH));
    $stop;
  end

  if (WORD_BYTES == 'd0) begin
    $display("%M EROARE: WORD_BYTES>0");
    $stop;
  end



  $readmemh("../deb_src/mem.hex", mem);


end


always @(posedge clk) begin

  if (ce & (addr >= MEM_DEPTH)) begin
    $display("%M %0t EROARE: Memorie accesata (%s) in afara spatiului (MEM_DEPTH =%0d, addr=%0d).",
      $time, we ? "WRITE" : "READ", MEM_DEPTH, addr);
    $stop;
  end















end       
      
endmodule
module mem_1rw  #(
parameter  ADDR_WIDTH = 8   ,
parameter  MEM_DEPTH  = 256 ,
parameter  WORD_BYTES =  8
)(
input                             clk       ,
input                             ce        ,
input                             we        ,
input       [ADDR_WIDTH   -1 : 0] addr      ,
input       [8*WORD_BYTES -1 : 0] wr_data   ,
input       [WORD_BYTES   -1 : 0] be        ,
output reg  [8*WORD_BYTES -1 : 0] rd_data
);


reg         [8*WORD_BYTES -1 : 0] mem[MEM_DEPTH -1 : 0];


wire [8*WORD_BYTES -1:0] ext_be ;

assign ext_be = {8*WORD_BYTES{be}};


always @(posedge clk)
if (ce & we) 
  mem[addr] <=  (mem[addr] & (~ext_be)) |
                (wr_data   &   ext_be );


always @(posedge clk)
if (ce & (~we)) rd_data <= mem[addr]; else
                rd_data <= 'bx;


integer    idx ;
initial begin

  if (MEM_DEPTH > (1 << ADDR_WIDTH)) begin
    $display("%M EROARE: MEM_DEPTH=%0d, maximum=%0d", 
      MEM_DEPTH, (1 << ADDR_WIDTH));
    $stop;
  end

  if (WORD_BYTES == 'd0) begin
    $display("%M EROARE: WORD_BYTES>0");
    $stop;
  end



  $readmemh("../deb_src/mem.hex", mem);


end


always @(posedge clk) begin

  if (ce & (addr >= MEM_DEPTH)) begin
    $display("%M %0t EROARE: Memorie accesata (%s) in afara spatiului (MEM_DEPTH =%0d, addr=%0d).",
      $time, we ? "WRITE" : "READ", MEM_DEPTH, addr);
    $stop;
  end















end       
      
endmodule