data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:2: syntax error, unexpected '.', expecting '['\nmodule top(...);\n           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:3: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=1 *) input a;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:4: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=1 *) input b;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:5: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=2 *) input c;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:6: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=1 *) input d;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:7: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=3 *) input e;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:8: Unsupported or unknown PLI call: $flowmap_level\n (* $flowmap_level=1 *) input f;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/passes/tests/flowmap/pack2p.v:14: syntax error, unexpected output\n output n2 = v&n1;\n ^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module top(...);
	(* $flowmap_level=1 *) input a;
	(* $flowmap_level=1 *) input b;
	(* $flowmap_level=2 *) input c;
	(* $flowmap_level=1 *) input d;
	(* $flowmap_level=3 *) input e;
	(* $flowmap_level=1 *) input f;
	wire u = a&b;
	wire w = c|d;
	wire v = u|w;
	wire n0 = w&e;
	wire n1 = n0|f;
	output n2 = v&n1;
endmodule
module top(...);

	(* $flowmap_level=1 *) input a;
	(* $flowmap_level=1 *) input b;
	(* $flowmap_level=2 *) input c;
	(* $flowmap_level=1 *) input d;
	(* $flowmap_level=3 *) input e;
	(* $flowmap_level=1 *) input f;
	wire u = a&b;
	wire w = c|d;
	wire v = u|w;
	wire n0 = w&e;
	wire n1 = n0|f;
	output n2 = v&n1;
endmodule