data/full_repos/permissive/506186384/project-files/lab6/ZeroExt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/506186384/project-files/lab6/ZeroExt.v:27: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                    : ... In instance ZeroExt\n    assign Data[31:0] = Instr[15:0];\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ZeroExt(
    input [15:0] Instr,
    output [31:0] Data
    );
    assign Data[31:0] = Instr[15:0];
endmodule
module ZeroExt(
    input [15:0] Instr,
    output [31:0] Data
    );

    assign Data[31:0] = Instr[15:0];
endmodule