data/full_repos/permissive/450072296/verilog/rtl/stud_dsmod.v
1: b'%Error: data/full_repos/permissive/450072296/verilog/rtl/stud_dsmod.v:25: Cannot find include file: stud_second_order_modulator.v\n`include "stud_second_order_modulator.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450072296/verilog/rtl,data/full_repos/permissive/450072296/stud_second_order_modulator.v\n             data/full_repos/permissive/450072296/verilog/rtl,data/full_repos/permissive/450072296/stud_second_order_modulator.v.v\n             data/full_repos/permissive/450072296/verilog/rtl,data/full_repos/permissive/450072296/stud_second_order_modulator.v.sv\n             stud_second_order_modulator.v\n             stud_second_order_modulator.v.v\n             stud_second_order_modulator.v.sv\n             obj_dir/stud_second_order_modulator.v\n             obj_dir/stud_second_order_modulator.v.v\n             obj_dir/stud_second_order_modulator.v.sv\n%Error: data/full_repos/permissive/450072296/verilog/rtl/stud_dsmod.v:26: Cannot find include file: stud_first_order_modulator.v\n`include "stud_first_order_modulator.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module stud_dsmod
#(
    parameter BITWIDTH = 16
)
(
    input n_rst_i,
    input clk_i,

    input mode_i,
    
    input [BITWIDTH - 1 : 0] data_i,

    output wire mod_o
);


reg prev_mode;

reg rst_strb;





reg [BITWIDTH - 1 : 0] first_order_data;


wire [1 : 0] stage1;

wire stage2;


always @(posedge clk_i) begin
    if (!n_rst_i) begin

        prev_mode <= 1'b0;
    end else begin

        prev_mode <= mode_i;
    end
end


always @* begin

    rst_strb = mode_i == prev_mode;

    if (mode_i) begin


        first_order_data = {stage1, {BITWIDTH - 2 {1'b0}}};
    end else begin

        first_order_data = data_i;
    end
end


stud_second_order_modulator #(.BITWIDTH(BITWIDTH)) modulator1
(
    .n_rst_i(n_rst_i & mode_i),
    .clk_i(clk_i),
    .data_i(data_i),
    .mod_o(stage1)
);


stud_first_order_modulator #(.BITWIDTH(BITWIDTH)) modulator2
(
    .n_rst_i(n_rst_i & rst_strb),
    .clk_i(clk_i),
    .data_i(first_order_data),
    .mod_o(stage2)
);


assign mod_o = stage2;

endmodule
module stud_dsmod
#(
    parameter BITWIDTH = 16
)
(
    input n_rst_i,
    input clk_i,

    input mode_i,
    
    input [BITWIDTH - 1 : 0] data_i,

    output wire mod_o
);



reg prev_mode;

reg rst_strb;





reg [BITWIDTH - 1 : 0] first_order_data;


wire [1 : 0] stage1;

wire stage2;


always @(posedge clk_i) begin
    if (!n_rst_i) begin

        prev_mode <= 1'b0;
    end else begin

        prev_mode <= mode_i;
    end
end


always @* begin

    rst_strb = mode_i == prev_mode;

    if (mode_i) begin


        first_order_data = {stage1, {BITWIDTH - 2 {1'b0}}};
    end else begin

        first_order_data = data_i;
    end
end


stud_second_order_modulator #(.BITWIDTH(BITWIDTH)) modulator1
(
    .n_rst_i(n_rst_i & mode_i),
    .clk_i(clk_i),
    .data_i(data_i),
    .mod_o(stage1)
);


stud_first_order_modulator #(.BITWIDTH(BITWIDTH)) modulator2
(
    .n_rst_i(n_rst_i & rst_strb),
    .clk_i(clk_i),
    .data_i(first_order_data),
    .mod_o(stage2)
);


assign mod_o = stage2;

endmodule