data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/cluster_clock_and2.sv
data/verilator_xmls/bd8a11de-19c1-4a56-8566-b20ebf2d5335.xml
module cluster_clock_and2
(
    input  logic clk0_i,
    input  logic clk1_i,
    output logic clk_o
);

   assign clk_o = clk0_i & clk1_i;

endmodule
module cluster_clock_and2
(
    input  logic clk0_i,
    input  logic clk1_i,
    output logic clk_o
);


   assign clk_o = clk0_i & clk1_i;

endmodule