data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module starteri(
	input clk,
	input rst,
	
	input n_init,
	
	input ready,
	
	output reg csz,
	output reg[3:0] f_timinit,
	
	output reg start2= 0,
	output reg[7:0] in2 = 0,
	output reg rdy2 = 0

);


always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_timinit <= 0;
		f_starti <= 0;
		f_tttim <= 0;
		
	end else
	begin
		f_timinit <= n_timinit;
		f_starti <= n_starti;
		f_tttim <= n_tttim;
		
	end
end


reg[2:0] f_tttim = 0;
reg[2:0] n_tttim = 0;

reg f_starti;
reg n_starti;


reg[3:0] n_timinit;

always@(*) begin
	start2 = 0;
	in2 = 0;
	rdy2 = 0;
	csz = 0;
	
	n_timinit = f_timinit;
	n_starti = f_starti;
	n_tttim = f_tttim;
	
	
	if(n_init)begin
		n_timinit = 1;
		n_tttim = 0;
		start2 = 1;
		in2 = 8'hFF;
		csz = 1;
	end
	
	if(f_timinit != 0)begin
			csz = 1;
			if(ready) begin
				n_starti = 1;
				n_tttim = 1;
			end
			
			if(f_tttim == 7)begin
				if(f_timinit == 10)begin
				
					n_timinit = 0;
					rdy2 = 1;
					n_tttim = 0;
					
				end else
				begin
					start2 = 1;
					in2 = 8'hFF;
					n_tttim = 0;
					
					n_timinit = f_timinit + 1;
				end
			end else if(f_tttim != 0) n_tttim = f_tttim + 1;
		end
	
end

endmodule
module starteri(
	input clk,
	input rst,
	
	input n_init,
	
	input ready,
	
	output reg csz,
	output reg[3:0] f_timinit,
	
	output reg start2= 0,
	output reg[7:0] in2 = 0,
	output reg rdy2 = 0

);



always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_timinit <= 0;
		f_starti <= 0;
		f_tttim <= 0;
		
	end else
	begin
		f_timinit <= n_timinit;
		f_starti <= n_starti;
		f_tttim <= n_tttim;
		
	end
end


reg[2:0] f_tttim = 0;
reg[2:0] n_tttim = 0;

reg f_starti;
reg n_starti;


reg[3:0] n_timinit;

always@(*) begin
	start2 = 0;
	in2 = 0;
	rdy2 = 0;
	csz = 0;
	
	n_timinit = f_timinit;
	n_starti = f_starti;
	n_tttim = f_tttim;
	
	
	if(n_init)begin
		n_timinit = 1;
		n_tttim = 0;
		start2 = 1;
		in2 = 8'hFF;
		csz = 1;
	end
	
	if(f_timinit != 0)begin
			csz = 1;
			if(ready) begin
				n_starti = 1;
				n_tttim = 1;
			end
			
			if(f_tttim == 7)begin
				if(f_timinit == 10)begin
				
					n_timinit = 0;
					rdy2 = 1;
					n_tttim = 0;
					
				end else
				begin
					start2 = 1;
					in2 = 8'hFF;
					n_tttim = 0;
					
					n_timinit = f_timinit + 1;
				end
			end else if(f_tttim != 0) n_tttim = f_tttim + 1;
		end
	
end

endmodule