data/full_repos/permissive/473722449/sr_flipflop.v
data/verilator_xmls/36404692-37f5-4d56-b7ce-df7de92d2ec7.xml
module sr_flipflop(s,r,clk,q,qbar);
    input wire s,r,clk;
    output reg q,qbar;
    
   always@(posedge clk)
   begin
    if (s ==1 & r == 0)
    begin
        q<=1;
        qbar<=0;
    end
    else if (s ==0 & r==1)
    begin
          q<=0;
          qbar<=1;
    end       
    else if (s ==0 & r==0)
    begin
          q<=q;
          qbar<=qbar;
    end
   end 
endmodule
module sr_flipflop(s,r,clk,q,qbar);

    input wire s,r,clk;
    output reg q,qbar;
    
   always@(posedge clk)
   begin
    if (s ==1 & r == 0)
    begin
        q<=1;
        qbar<=0;
    end
    else if (s ==0 & r==1)
    begin
          q<=0;
          qbar<=1;
    end       
    else if (s ==0 & r==0)
    begin
          q<=q;
          qbar<=qbar;
    end
   end 
endmodule