data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Shift Registers/2014_q4b/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers/2014_q4b,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/2014_q4b/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input  wire [3:0] SW,
    input  wire [3:0] KEY,
    output wire [3:0] LEDR
);

  wire clk, E, L, w;
  assign clk = KEY[0];
  assign E   = KEY[1];
  assign L   = KEY[2];
  assign w   = KEY[3];

  MUXDFF md3 (
      clk,
      w,
      SW[3],
      E,
      L,
      LEDR[3]
  );
  MUXDFF md2 (
      clk,
      LEDR[3],
      SW[2],
      E,
      L,
      LEDR[2]
  );
  MUXDFF md1 (
      clk,
      LEDR[2],
      SW[1],
      E,
      L,
      LEDR[1]
  );
  MUXDFF md0 (
      clk,
      LEDR[1],
      SW[0],
      E,
      L,
      LEDR[0]
  );

endmodule
module top_module (
    input  wire [3:0] SW,
    input  wire [3:0] KEY,
    output wire [3:0] LEDR
);


  wire clk, E, L, w;
  assign clk = KEY[0];
  assign E   = KEY[1];
  assign L   = KEY[2];
  assign w   = KEY[3];

  MUXDFF md3 (
      clk,
      w,
      SW[3],
      E,
      L,
      LEDR[3]
  );
  MUXDFF md2 (
      clk,
      LEDR[3],
      SW[2],
      E,
      L,
      LEDR[2]
  );
  MUXDFF md1 (
      clk,
      LEDR[2],
      SW[1],
      E,
      L,
      LEDR[1]
  );
  MUXDFF md0 (
      clk,
      LEDR[1],
      SW[0],
      E,
      L,
      LEDR[0]
  );

endmodule