data/full_repos/permissive/515646879/Code.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5 A=4\'b1110;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #5 B=4\'b1101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #5 A=4\'b1110;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 B=4\'b1111;\n    ^\n%Error: data/full_repos/permissive/515646879/Code.v:39: Unsupported or unknown PLI call: $monitor\n    $monitor("time=%t,A=%d,B=%d,O=%d",$time,A,B,O);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515646879/Code.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #80 $finish;\n    ^\n%Error: data/full_repos/permissive/515646879/Code.v:44: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("multiplier.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515646879/Code.v:45: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,multiplier_4bit_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier_4bit_tb;
  reg [3:0]A,B;
  wire [7:0]O;
  
  multiplier_4bit dut(A,B,O);
  
  initial begin
    #5 A=4'b1110;
    #5 B=4'b1101;
    #10
    #5 A=4'b1110;
    #5 B=4'b1111;
  end
  
  initial begin
    $monitor("time=%t,A=%d,B=%d,O=%d",$time,A,B,O);
    #80 $finish;
  end
  
  initial begin
    $dumpfile("multiplier.vcd");
    $dumpvars(0,multiplier_4bit_tb);
  end
endmodule
module multiplier_4bit_tb;

  reg [3:0]A,B;
  wire [7:0]O;
  
  multiplier_4bit dut(A,B,O);
  
  initial begin
    #5 A=4'b1110;
    #5 B=4'b1101;
    #10
    #5 A=4'b1110;
    #5 B=4'b1111;
  end
  
  initial begin
    $monitor("time=%t,A=%d,B=%d,O=%d",$time,A,B,O);
    #80 $finish;
  end
  
  initial begin
    $dumpfile("multiplier.vcd");
    $dumpvars(0,multiplier_4bit_tb);
  end
endmodule