data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/Decoder4x16_Cond.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/Decoder4x16_Cond.v:7: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                           : ... In instance Decoder4x16_Cond\nassign Out = {16{Cond}} & (1\'b1 << In);\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Decoder4x16_Cond  (
	input 	wire [3:0] 	In,
	input 	wire 			Cond,
	output 	wire  [15:0]	Out
);

assign Out = {16{Cond}} & (1'b1 << In);























	
endmodule
module Decoder4x16_Cond  (
	input 	wire [3:0] 	In,
	input 	wire 			Cond,
	output 	wire  [15:0]	Out
);


assign Out = {16{Cond}} & (1'b1 << In);























	
endmodule