data/full_repos/permissive/434840709/lab2/mux4bit/mux4bit2to1.v
data/verilator_xmls/87648f28-4d93-4cd2-a72b-2c4e90243b9b.xml
module mux4bit2to1(
    input [3:0] a,
    input [3:0] b,
    input s,
    output [3:0]y 
);

    
    assign y = s==1 ? a : b;
   

    

endmodule
module mux4bit2to1(
    input [3:0] a,
    input [3:0] b,
    input s,
    output [3:0]y 
);


    
    assign y = s==1 ? a : b;
   

    

endmodule