data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:118: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'okHost\'\nmodule okHost\n       ^~~~~~\n                                                                                    : ... Top module \'okWireOR\'\nmodule okWireOR # (parameter N = 1) (\n       ^~~~~~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:43: Cannot find file containing module: \'IBUFG\'\n IBUFG hi_in0_bufg (.I(hi_in[0]), .O(hi_in0_ibufg));\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/492772061/ADPPulse/okV,data/full_repos/permissive/492772061/IBUFG\n             data/full_repos/permissive/492772061/ADPPulse/okV,data/full_repos/permissive/492772061/IBUFG.v\n             data/full_repos/permissive/492772061/ADPPulse/okV,data/full_repos/permissive/492772061/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:45: Cannot find file containing module: \'MMCME2_BASE\'\n MMCME2_BASE #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mmcm0_bufg   (.I(mmcm0_clk0), .O(ti_clk));\n ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:66: Cannot find file containing module: \'BUFG\'\n BUFG mmcm0fb_bufg (.I(mmcm0_clkfb), .O(mmcm0_clkfb_bufg));\n ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:73: Cannot find file containing module: \'IOBUF\'\n   IOBUF iobf0 (\n   ^~~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:81: Cannot find file containing module: \'FDRE\'\n   FDRE fdrein0 (\n   ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:91: Cannot find file containing module: \'FDRE\'\n   FDRE fdreout0 (\n   ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:100: Cannot find file containing module: \'FDRE\'\n   FDRE fdreout1 (\n   ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:111: Cannot find file containing module: \'OBUF\'\n OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));\n ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:112: Cannot find file containing module: \'OBUF\'\n OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));\n ^~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:113: Cannot find file containing module: \'IOBUF\'\n IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));\n ^~~~~\n%Error: data/full_repos/permissive/492772061/ADPPulse/okV/okLibrary.v:115: Cannot find file containing module: \'okCoreHarness\'\n okCoreHarness core0(.okHC(okHC), .okCH(okCH), .ok1(ok1), .ok2(ok2));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module okHost
	(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,
	output wire        ti_clk,
	output wire [30:0] ok1,
	input  wire [16:0] ok2
	);

	wire [24:0] okHC;
	wire [20:0] okCH;
		
	wire [15:0] iobf0_hi_datain;
	wire [15:0] hi_datain;
	
	wire [15:0] fdreout0_hi_dataout;
	wire [15:0] fdreout1_hi_drive; 
	
	assign okHC[0]     = ti_clk;
	assign okHC[7:1]   = hi_in[7:1];
	assign okHC[23:8]  = hi_datain;


	wire mmcm0_clk0,mmcm0_clk0_bufg;
	wire mmcm0_clkfb,mmcm0_clkfb_bufg;
	wire mmcm0_locked;
	wire hi_in0_ibufg;

	IBUFG hi_in0_bufg (.I(hi_in[0]), .O(hi_in0_ibufg));

	MMCME2_BASE #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(20),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(20.833),
		.CLKOUT0_DIVIDE_F(20.0),
		.CLKOUT0_PHASE(4.5),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	mmcm0 (
		.CLKOUT0(mmcm0_clk0),
		.CLKFBOUT(mmcm0_clkfb),
		.LOCKED(mmcm0_locked),
		.CLKIN1(hi_in0_ibufg),
		.RST(1'b0),
		.CLKFBIN(mmcm0_clkfb_bufg)
	);

	BUFG mmcm0_bufg   (.I(mmcm0_clk0), .O(ti_clk));
	BUFG mmcm0fb_bufg (.I(mmcm0_clkfb), .O(mmcm0_clkfb_bufg));
	

	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin : delays
			
			IOBUF iobf0 (
				.IO(hi_inout[i]),
				.I(fdreout0_hi_dataout[i]), 
				.O(iobf0_hi_datain[i]), 
				.T(fdreout1_hi_drive[i]) 
			);

			(* IOB = "true" *)
			FDRE fdrein0 (
				.D              (iobf0_hi_datain[i]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (hi_datain[i])
			);


			(* IOB = "true" *)
			FDRE fdreout0 (
				.D              (okCH[i+3]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout0_hi_dataout[i])
			);

			(* IOB = "true" *)
			FDRE fdreout1 (
				.D              (~okCH[2]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout1_hi_drive[i])
			);

		end
	endgenerate
	
	OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));
	OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));
	IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));

	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .ok1(ok1), .ok2(ok2));
endmodule
module okHost
	(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,
	output wire        ti_clk,
	output wire [30:0] ok1,
	input  wire [16:0] ok2
	);


	wire [24:0] okHC;
	wire [20:0] okCH;
		
	wire [15:0] iobf0_hi_datain;
	wire [15:0] hi_datain;
	
	wire [15:0] fdreout0_hi_dataout;
	wire [15:0] fdreout1_hi_drive; 
	
	assign okHC[0]     = ti_clk;
	assign okHC[7:1]   = hi_in[7:1];
	assign okHC[23:8]  = hi_datain;


	wire mmcm0_clk0,mmcm0_clk0_bufg;
	wire mmcm0_clkfb,mmcm0_clkfb_bufg;
	wire mmcm0_locked;
	wire hi_in0_ibufg;

	IBUFG hi_in0_bufg (.I(hi_in[0]), .O(hi_in0_ibufg));

	MMCME2_BASE #(
		.BANDWIDTH("OPTIMIZED"),
		.CLKFBOUT_MULT_F(20),
		.CLKFBOUT_PHASE(0.0),
		.CLKIN1_PERIOD(20.833),
		.CLKOUT0_DIVIDE_F(20.0),
		.CLKOUT0_PHASE(4.5),
		.DIVCLK_DIVIDE(1),
		.REF_JITTER1(0.0),
		.STARTUP_WAIT("FALSE")
	)
	mmcm0 (
		.CLKOUT0(mmcm0_clk0),
		.CLKFBOUT(mmcm0_clkfb),
		.LOCKED(mmcm0_locked),
		.CLKIN1(hi_in0_ibufg),
		.RST(1'b0),
		.CLKFBIN(mmcm0_clkfb_bufg)
	);

	BUFG mmcm0_bufg   (.I(mmcm0_clk0), .O(ti_clk));
	BUFG mmcm0fb_bufg (.I(mmcm0_clkfb), .O(mmcm0_clkfb_bufg));
	

	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin : delays
			
			IOBUF iobf0 (
				.IO(hi_inout[i]),
				.I(fdreout0_hi_dataout[i]), 
				.O(iobf0_hi_datain[i]), 
				.T(fdreout1_hi_drive[i]) 
			);

			(* IOB = "true" *)
			FDRE fdrein0 (
				.D              (iobf0_hi_datain[i]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (hi_datain[i])
			);


			(* IOB = "true" *)
			FDRE fdreout0 (
				.D              (okCH[i+3]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout0_hi_dataout[i])
			);

			(* IOB = "true" *)
			FDRE fdreout1 (
				.D              (~okCH[2]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout1_hi_drive[i])
			);

		end
	endgenerate
	
	OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));
	OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));
	IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));

	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .ok1(ok1), .ok2(ok2));
endmodule