data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/01_Basic_Gates/01_Wire.v
data/verilator_xmls/6af97d66-5e59-4f03-b0fb-50bf1feb83ee.xml
module top_module (
    input in,
    output out
);
    
    assign out = in;

endmodule
module top_module (
    input in,
    output out
);

    
    assign out = in;

endmodule