data/full_repos/permissive/431474762/mycpu_core.v
1: b'%Error: data/full_repos/permissive/431474762/mycpu_core.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.v\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:5: syntax error, unexpected int, expecting IDENTIFIER or \'[\' or do or final\n    input wire [5:0] int,\n                     ^~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:8: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] inst_sram_wen, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:9: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] inst_sram_addr, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] inst_sram_wdata, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [31:0] inst_sram_rdata, \n    ^~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire data_sram_en, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] data_sram_wen, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] data_sram_addr, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] data_sram_wdata, \n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [31:0] data_sram_rdata, \n    ^~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] debug_wb_pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] debug_wb_rf_wen,\n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [4:0] debug_wb_rf_wnum,\n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] debug_wb_rf_wdata\n    ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:23: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:24: Define or directive not defined: \'`IF_TO_ID_WD\'\n    wire [`IF_TO_ID_WD-1:0] if_to_id_bus;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:25: Define or directive not defined: \'`ID_TO_EX_WD\'\n    wire [`ID_TO_EX_WD-1:0] id_to_ex_bus;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:26: Define or directive not defined: \'`EX_TO_MEM_WD\'\n    wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:27: Define or directive not defined: \'`EX_TO_ID_WD\'\n    wire [`EX_TO_ID_WD-1:0] ex_to_id_bus; \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:28: Define or directive not defined: \'`MEM_TO_WB_WD\'\n    wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:29: Define or directive not defined: \'`MEM_TO_ID_WD\'\n    wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus; \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:30: Define or directive not defined: \'`BR_WD\'\n    wire [`BR_WD-1:0] br_bus; \n          ^~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:31: Define or directive not defined: \'`DATA_SRAM_WD\'\n    wire [`DATA_SRAM_WD-1:0] ex_dt_sram_bus;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:32: Define or directive not defined: \'`WB_TO_RF_WD\'\n    wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:33: Define or directive not defined: \'`StallBus\'\n    wire [`StallBus-1:0] stall;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/mycpu_core.v:41: syntax error, unexpected IDENTIFIER\n    IF u_IF(\n    ^~\n%Error: Exiting due to 27 error(s)\n'
module mycpu_core(
    input wire clk,
    input wire rst,
    input wire [5:0] int,

    output wire inst_sram_en,
    output wire [3:0] inst_sram_wen,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata,
    input wire [31:0] inst_sram_rdata,

    output wire data_sram_en,
    output wire [3:0] data_sram_wen,
    output wire [31:0] data_sram_addr,
    output wire [31:0] data_sram_wdata,
    input wire [31:0] data_sram_rdata,

    output wire [31:0] debug_wb_pc,
    output wire [3:0] debug_wb_rf_wen,
    output wire [4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
);
    wire [`IF_TO_ID_WD-1:0] if_to_id_bus;
    wire [`ID_TO_EX_WD-1:0] id_to_ex_bus;
    wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus;
    wire [`EX_TO_ID_WD-1:0] ex_to_id_bus;
    wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus;
    wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus;
    wire [`BR_WD-1:0] br_bus; 
    wire [`DATA_SRAM_WD-1:0] ex_dt_sram_bus;
    wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus;
    wire [`StallBus-1:0] stall;



    wire id_stall;
    wire ex_stall;
    wire [5:0] ex_aluop;
    wire [4:0] ex_raddr;
    IF u_IF(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .br_bus          (br_bus          ),
        .if_to_id_bus    (if_to_id_bus    ),
        .inst_sram_en    (inst_sram_en    ),
        .inst_sram_wen   (inst_sram_wen   ),
        .inst_sram_addr  (inst_sram_addr  ),
        .inst_sram_wdata (inst_sram_wdata )
    );
    

    ID u_ID(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .stallreq        (stallreq        ),
        .if_to_id_bus    (if_to_id_bus    ),
        .ex_to_id_bus    (ex_to_id_bus    ),
        .mem_to_id_bus   (mem_to_id_bus   ),
        .inst_sram_rdata (inst_sram_rdata ),
        .wb_to_rf_bus    (wb_to_rf_bus    ),
        .id_to_ex_bus    (id_to_ex_bus    ),
        .br_bus          (br_bus          ),



        .stallreq_id(id_stall),
        .ex_aluop (ex_aluop),
        .ex_addr  (ex_raddr)
    );
    EX u_EX(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .id_to_ex_bus    (id_to_ex_bus    ),
        .ex_to_mem_bus   (ex_to_mem_bus   ),
        .ex_to_id_bus    (ex_to_id_bus    ),
        .data_sram_en    (data_sram_en    ),
        .data_sram_wen   (data_sram_wen   ),
        .data_sram_addr  (data_sram_addr  ),
        .data_sram_wdata (data_sram_wdata ),



        .stall_ex                   (ex_stall),
        .ex_aluop_o                 (ex_aluop),
        .ex_addr_o                  (ex_raddr)
    );

    MEM u_MEM(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .ex_to_mem_bus   (ex_to_mem_bus   ),
        .data_sram_rdata (data_sram_rdata ),
        .mem_to_wb_bus   (mem_to_wb_bus   ),
        .mem_to_id_bus   (mem_to_id_bus   )
    );
    
    WB u_WB(
    	.clk               (clk               ),
        .rst               (rst               ),
        .stall             (stall             ),
        .mem_to_wb_bus     (mem_to_wb_bus     ),
        .wb_to_rf_bus      (wb_to_rf_bus      ),
        .debug_wb_pc       (debug_wb_pc       ),
        .debug_wb_rf_wen   (debug_wb_rf_wen   ),
        .debug_wb_rf_wnum  (debug_wb_rf_wnum  ),
        .debug_wb_rf_wdata (debug_wb_rf_wdata )
    );

    CTRL u_CTRL(
    	.rst   (rst   ),
        .stall (stall ),
        .stall_for_id(id_stall),
        .stall_for_ex(ex_stall)
    );
    
endmodule
module mycpu_core(
    input wire clk,
    input wire rst,
    input wire [5:0] int,

    output wire inst_sram_en,
    output wire [3:0] inst_sram_wen,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata,
    input wire [31:0] inst_sram_rdata,

    output wire data_sram_en,
    output wire [3:0] data_sram_wen,
    output wire [31:0] data_sram_addr,
    output wire [31:0] data_sram_wdata,
    input wire [31:0] data_sram_rdata,

    output wire [31:0] debug_wb_pc,
    output wire [3:0] debug_wb_rf_wen,
    output wire [4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
);

    wire [`IF_TO_ID_WD-1:0] if_to_id_bus;
    wire [`ID_TO_EX_WD-1:0] id_to_ex_bus;
    wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus;
    wire [`EX_TO_ID_WD-1:0] ex_to_id_bus;
    wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus;
    wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus;
    wire [`BR_WD-1:0] br_bus; 
    wire [`DATA_SRAM_WD-1:0] ex_dt_sram_bus;
    wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus;
    wire [`StallBus-1:0] stall;



    wire id_stall;
    wire ex_stall;
    wire [5:0] ex_aluop;
    wire [4:0] ex_raddr;
    IF u_IF(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .br_bus          (br_bus          ),
        .if_to_id_bus    (if_to_id_bus    ),
        .inst_sram_en    (inst_sram_en    ),
        .inst_sram_wen   (inst_sram_wen   ),
        .inst_sram_addr  (inst_sram_addr  ),
        .inst_sram_wdata (inst_sram_wdata )
    );
    

    ID u_ID(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .stallreq        (stallreq        ),
        .if_to_id_bus    (if_to_id_bus    ),
        .ex_to_id_bus    (ex_to_id_bus    ),
        .mem_to_id_bus   (mem_to_id_bus   ),
        .inst_sram_rdata (inst_sram_rdata ),
        .wb_to_rf_bus    (wb_to_rf_bus    ),
        .id_to_ex_bus    (id_to_ex_bus    ),
        .br_bus          (br_bus          ),



        .stallreq_id(id_stall),
        .ex_aluop (ex_aluop),
        .ex_addr  (ex_raddr)
    );
    EX u_EX(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .id_to_ex_bus    (id_to_ex_bus    ),
        .ex_to_mem_bus   (ex_to_mem_bus   ),
        .ex_to_id_bus    (ex_to_id_bus    ),
        .data_sram_en    (data_sram_en    ),
        .data_sram_wen   (data_sram_wen   ),
        .data_sram_addr  (data_sram_addr  ),
        .data_sram_wdata (data_sram_wdata ),



        .stall_ex                   (ex_stall),
        .ex_aluop_o                 (ex_aluop),
        .ex_addr_o                  (ex_raddr)
    );

    MEM u_MEM(
    	.clk             (clk             ),
        .rst             (rst             ),
        .stall           (stall           ),
        .ex_to_mem_bus   (ex_to_mem_bus   ),
        .data_sram_rdata (data_sram_rdata ),
        .mem_to_wb_bus   (mem_to_wb_bus   ),
        .mem_to_id_bus   (mem_to_id_bus   )
    );
    
    WB u_WB(
    	.clk               (clk               ),
        .rst               (rst               ),
        .stall             (stall             ),
        .mem_to_wb_bus     (mem_to_wb_bus     ),
        .wb_to_rf_bus      (wb_to_rf_bus      ),
        .debug_wb_pc       (debug_wb_pc       ),
        .debug_wb_rf_wen   (debug_wb_rf_wen   ),
        .debug_wb_rf_wnum  (debug_wb_rf_wnum  ),
        .debug_wb_rf_wdata (debug_wb_rf_wdata )
    );

    CTRL u_CTRL(
    	.rst   (rst   ),
        .stall (stall ),
        .stall_for_id(id_stall),
        .stall_for_ex(ex_stall)
    );
    
endmodule