data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:67: Signal definition not found, creating implicitly: \'FUNCT3_out\'\n                                                                                              : ... Suggested alternative: \'FUNCT3_EX\'\n    assign FUNCT3_out = FUNCT3_EX;\n           ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:48: Cannot find file containing module: \'mux4_1\'\n    mux4_1 mux1(REG_DATA1_EX, ALU_DATA_WB, ALU_OUT_MEM, 32\'b0, forwardA, out_mux1);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/mux4_1\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/mux4_1.v\n             data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new,data/full_repos/permissive/465067219/mux4_1.sv\n             mux4_1\n             mux4_1.v\n             mux4_1.sv\n             obj_dir/mux4_1\n             obj_dir/mux4_1.v\n             obj_dir/mux4_1.sv\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:50: Cannot find file containing module: \'mux4_1\'\n    mux4_1 mux2(REG_DATA2_EX, ALU_DATA_WB, ALU_OUT_MEM, 32\'b0, forwardB, REG_DATA2_EX_FINAL);\n    ^~~~~~\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:52: Cannot find file containing module: \'mux2_1\'\n    mux2_1 mux3(REG_DATA2_EX_FINAL, IMM_EX, ALUSrc_EX, out_mux3);\n    ^~~~~~\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:54: Cannot find file containing module: \'adder\'\n    adder adder1(PC_EX, IMM_EX, PC_Branch_EX);\n    ^~~~~\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:56: Cannot find file containing module: \'ALUcontrol\'\n    ALUcontrol alu_control(ALUop_EX, FUNCT7_EX, FUNCT3_EX, ALUInput);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:57: Cannot find file containing module: \'ALU\'\n    ALU alu(ALUInput, out_mux1, out_mux3, ZERO_EX, ALU_OUT_EX);\n    ^~~\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/EX.v:67: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'FUNCT3_EX\' generates 3 bits.\n                                                                                           : ... In instance EX\n    assign FUNCT3_out = FUNCT3_EX;\n                      ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module EX(input [31:0] IMM_EX,
          input [31:0] REG_DATA1_EX,
          input [31:0] REG_DATA2_EX,
          input [31:0] PC_EX,

          input [2:0] FUNCT3_EX,
          input [6:0] FUNCT7_EX,
          

          input [4:0] RD_EX,
          input [4:0] RS1_EX,
          input [4:0] RS2_EX,
          input RegWrite_EX,
          input MemtoReg_EX,
          input MemRead_EX,
          input MemWrite_EX,
          
          input [1:0] ALUop_EX,
          input ALUSrc_EX,
          input Branch_EX,
          input [1:0] forwardA,
          input [1:0] forwardB,
          
          input [31:0] ALU_DATA_WB,
          input [31:0] ALU_OUT_MEM,
          

          output ZERO_EX,
          output [31:0] ALU_OUT_EX,
          
          output [31:0] PC_Branch_EX,
          output [31:0] REG_DATA2_EX_FINAL,

          output MemRead_EX_out,
          output MemtoReg_EX_out,
          output MemWrite_EX_out,
          output RegWrite_EX_out,
          output Branch_EX_out,
          output [4:0] RD_EX_out,
          output [4:0] RS1_out);
        
    wire [3:0]ALUInput;
    wire [31:0]out_mux1, out_mux2, out_mux3;
    wire [31:0]rez_addr;
        
    mux4_1 mux1(REG_DATA1_EX, ALU_DATA_WB, ALU_OUT_MEM, 32'b0, forwardA, out_mux1);

    mux4_1 mux2(REG_DATA2_EX, ALU_DATA_WB, ALU_OUT_MEM, 32'b0, forwardB, REG_DATA2_EX_FINAL);
        
    mux2_1 mux3(REG_DATA2_EX_FINAL, IMM_EX, ALUSrc_EX, out_mux3);
        
    adder adder1(PC_EX, IMM_EX, PC_Branch_EX);
        
    ALUcontrol alu_control(ALUop_EX, FUNCT7_EX, FUNCT3_EX, ALUInput);
    ALU alu(ALUInput, out_mux1, out_mux3, ZERO_EX, ALU_OUT_EX);
        

    assign MemRead_EX_out = MemRead_EX;
    assign MemtoReg_EX_out = MemtoReg_EX;
    assign MemWrite_EX_out = MemWrite_EX;
    assign RegWrite_EX_out = RegWrite_EX;
    assign Branch_EX_out = Branch_EX;
    assign RD_EX_out = RD_EX;
    assign RS1_out = RS1_EX;
    assign FUNCT3_out = FUNCT3_EX;
        
endmodule
module EX(input [31:0] IMM_EX,
          input [31:0] REG_DATA1_EX,
          input [31:0] REG_DATA2_EX,
          input [31:0] PC_EX,

          input [2:0] FUNCT3_EX,
          input [6:0] FUNCT7_EX,
          

          input [4:0] RD_EX,
          input [4:0] RS1_EX,
          input [4:0] RS2_EX,
          input RegWrite_EX,
          input MemtoReg_EX,
          input MemRead_EX,
          input MemWrite_EX,
          
          input [1:0] ALUop_EX,
          input ALUSrc_EX,
          input Branch_EX,
          input [1:0] forwardA,
          input [1:0] forwardB,
          
          input [31:0] ALU_DATA_WB,
          input [31:0] ALU_OUT_MEM,
          

          output ZERO_EX,
          output [31:0] ALU_OUT_EX,
          
          output [31:0] PC_Branch_EX,
          output [31:0] REG_DATA2_EX_FINAL,

          output MemRead_EX_out,
          output MemtoReg_EX_out,
          output MemWrite_EX_out,
          output RegWrite_EX_out,
          output Branch_EX_out,
          output [4:0] RD_EX_out,
          output [4:0] RS1_out);

        
    wire [3:0]ALUInput;
    wire [31:0]out_mux1, out_mux2, out_mux3;
    wire [31:0]rez_addr;
        
    mux4_1 mux1(REG_DATA1_EX, ALU_DATA_WB, ALU_OUT_MEM, 32'b0, forwardA, out_mux1);

    mux4_1 mux2(REG_DATA2_EX, ALU_DATA_WB, ALU_OUT_MEM, 32'b0, forwardB, REG_DATA2_EX_FINAL);
        
    mux2_1 mux3(REG_DATA2_EX_FINAL, IMM_EX, ALUSrc_EX, out_mux3);
        
    adder adder1(PC_EX, IMM_EX, PC_Branch_EX);
        
    ALUcontrol alu_control(ALUop_EX, FUNCT7_EX, FUNCT3_EX, ALUInput);
    ALU alu(ALUInput, out_mux1, out_mux3, ZERO_EX, ALU_OUT_EX);
        

    assign MemRead_EX_out = MemRead_EX;
    assign MemtoReg_EX_out = MemtoReg_EX;
    assign MemWrite_EX_out = MemWrite_EX;
    assign RegWrite_EX_out = RegWrite_EX;
    assign Branch_EX_out = Branch_EX;
    assign RD_EX_out = RD_EX;
    assign RS1_out = RS1_EX;
    assign FUNCT3_out = FUNCT3_EX;
        
endmodule