data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v:71: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                  : ... In instance baudrate_generate\n   cnt4txclkx4<=8\'d0;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v:77: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                  : ... In instance baudrate_generate\n    cnt4txclkx4<=8\'d0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v:89: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                  : ... In instance baudrate_generate\n   cnt4rxclkx4<=8\'d0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v:95: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                  : ... In instance baudrate_generate\n    cnt4rxclkx4<=8\'d0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/baudrate_generate.v:92: Operator EQ expects 12 bits on the RHS, but RHS\'s VARREF \'CNT_RXCLKx4\' generates 8 bits.\n                                                                                  : ... In instance baudrate_generate\n  if(cnt4rxclkx4==CNT_RXCLKx4)\n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module baudrate_generate(clk,reset,txclk,rxclk,txclkx4,rxclkx4);
input clk;
input reset;
output reg txclk;
output reg rxclk;
output reg txclkx4;
output reg rxclkx4;





parameter CNT_TXCLK=12'd2559;
reg [11:0] cnt4txclk;

parameter CNT_TXCLKx4=12'd640;
reg [11:0] cnt4txclkx4;




parameter CNT_RXCLK=8'd160;
reg [7:0] cnt4rxclk;

parameter CNT_RXCLKx4=8'd40;
reg [11:0] cnt4rxclkx4;



always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclk<=0;
			cnt4txclk<=12'd0;
		end
	else
		if(cnt4txclk==CNT_TXCLK)
			begin
				txclk<=~txclk;
				cnt4txclk<=12'd0;
			end
		else
			cnt4txclk<=cnt4txclk+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			rxclk<=0;
			cnt4rxclk<=8'd0;
		end
	else
		if(cnt4rxclk==CNT_RXCLK)
			begin
				rxclk<=~rxclk;
				cnt4rxclk<=8'd0;
			end
		else
			cnt4rxclk<=cnt4rxclk+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclkx4<=0;
			cnt4txclkx4<=8'd0;
		end
	else
		if(cnt4txclkx4==CNT_TXCLKx4)
			begin
				txclkx4<=~txclkx4;
				cnt4txclkx4<=8'd0;
			end
		else
			cnt4txclkx4<=cnt4txclkx4+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			rxclkx4<=0;
			cnt4rxclkx4<=8'd0;
		end
	else
		if(cnt4rxclkx4==CNT_RXCLKx4)
			begin
				rxclkx4<=~rxclkx4;
				cnt4rxclkx4<=8'd0;
			end
		else
			cnt4rxclkx4<=cnt4rxclkx4+1'b1;
end
endmodule
module baudrate_generate(clk,reset,txclk,rxclk,txclkx4,rxclkx4);

input clk;
input reset;
output reg txclk;
output reg rxclk;
output reg txclkx4;
output reg rxclkx4;





parameter CNT_TXCLK=12'd2559;
reg [11:0] cnt4txclk;

parameter CNT_TXCLKx4=12'd640;
reg [11:0] cnt4txclkx4;




parameter CNT_RXCLK=8'd160;
reg [7:0] cnt4rxclk;

parameter CNT_RXCLKx4=8'd40;
reg [11:0] cnt4rxclkx4;



always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclk<=0;
			cnt4txclk<=12'd0;
		end
	else
		if(cnt4txclk==CNT_TXCLK)
			begin
				txclk<=~txclk;
				cnt4txclk<=12'd0;
			end
		else
			cnt4txclk<=cnt4txclk+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			rxclk<=0;
			cnt4rxclk<=8'd0;
		end
	else
		if(cnt4rxclk==CNT_RXCLK)
			begin
				rxclk<=~rxclk;
				cnt4rxclk<=8'd0;
			end
		else
			cnt4rxclk<=cnt4rxclk+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclkx4<=0;
			cnt4txclkx4<=8'd0;
		end
	else
		if(cnt4txclkx4==CNT_TXCLKx4)
			begin
				txclkx4<=~txclkx4;
				cnt4txclkx4<=8'd0;
			end
		else
			cnt4txclkx4<=cnt4txclkx4+1'b1;
end


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			rxclkx4<=0;
			cnt4rxclkx4<=8'd0;
		end
	else
		if(cnt4rxclkx4==CNT_RXCLKx4)
			begin
				rxclkx4<=~rxclkx4;
				cnt4rxclkx4<=8'd0;
			end
		else
			cnt4rxclkx4<=cnt4rxclkx4+1'b1;
end
endmodule