data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:66: Define or directive not defined: \'`FROM_INC4\'\n  `FROM_INC4:\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:66: syntax error, unexpected \':\', expecting endcase\n  `FROM_INC4:\n            ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:68: Define or directive not defined: \'`FROM_OPCODE25_0\'\n  `FROM_OPCODE25_0:\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:70: Define or directive not defined: \'`FROM_BRANCH\'\n  `FROM_BRANCH:\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/PC_Next.v:72: Define or directive not defined: \'`FROM_LBRANCH\'\n  `FROM_LBRANCH:\n  ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module PC_Next
( 
	clk,
	rst,
	pc_new,
	take_branch,
	opcode25_0,
	pc_source,
	pc_current,
	pc_plus4
);

	input 			clk;
	input 			rst;
	input 	[31:2] 	pc_new;
	input 			take_branch;
	input 	[25:0] 	opcode25_0;
	input 	[1:0] 	pc_source;
	output 	[31:2] 	pc_current;
	output 	[31:2] 	pc_plus4;


	reg		[31:2]	pc;
	reg 	[31:2] 	pc_future;
	
	assign pc_current=pc;
	

	assign pc_plus4=pc+1;


	wire	[31:2]	pc_jump;
	
	assign pc_jump = pc+{{14{opcode25_0[15]}},opcode25_0[15:0]};


	always@(*)
	begin
		pc_future<=pc_plus4;
		case(pc_source)
		`FROM_INC4:
			pc_future<=pc_plus4;
		`FROM_OPCODE25_0:
			pc_future<={pc[31:28],opcode25_0};
		`FROM_BRANCH:
			pc_future<=(take_branch)?pc_jump:pc_plus4;
		`FROM_LBRANCH:
			pc_future<=pc_new;
		default:
			pc_future<=pc_plus4;
		endcase
	end
	
	
	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			pc<=30'b0;
		end
		else 
		begin
			pc<=pc_future;
		end
	end
endmodule
module PC_Next
( 
	clk,
	rst,
	pc_new,
	take_branch,
	opcode25_0,
	pc_source,
	pc_current,
	pc_plus4
);


	input 			clk;
	input 			rst;
	input 	[31:2] 	pc_new;
	input 			take_branch;
	input 	[25:0] 	opcode25_0;
	input 	[1:0] 	pc_source;
	output 	[31:2] 	pc_current;
	output 	[31:2] 	pc_plus4;


	reg		[31:2]	pc;
	reg 	[31:2] 	pc_future;
	
	assign pc_current=pc;
	

	assign pc_plus4=pc+1;


	wire	[31:2]	pc_jump;
	
	assign pc_jump = pc+{{14{opcode25_0[15]}},opcode25_0[15:0]};


	always@(*)
	begin
		pc_future<=pc_plus4;
		case(pc_source)
		`FROM_INC4:
			pc_future<=pc_plus4;
		`FROM_OPCODE25_0:
			pc_future<={pc[31:28],opcode25_0};
		`FROM_BRANCH:
			pc_future<=(take_branch)?pc_jump:pc_plus4;
		`FROM_LBRANCH:
			pc_future<=pc_new;
		default:
			pc_future<=pc_plus4;
		endcase
	end
	
	
	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			pc<=30'b0;
		end
		else 
		begin
			pc<=pc_future;
		end
	end
endmodule