data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v
1: b'%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:31: Cannot find include file: jedro_1_defines.v\n`include "jedro_1_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl,data/full_repos/permissive/522553437/jedro_1_defines.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl,data/full_repos/permissive/522553437/jedro_1_defines.v.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl,data/full_repos/permissive/522553437/jedro_1_defines.v.sv\n             jedro_1_defines.v\n             jedro_1_defines.v.v\n             jedro_1_defines.v.sv\n             obj_dir/jedro_1_defines.v\n             obj_dir/jedro_1_defines.v.v\n             obj_dir/jedro_1_defines.v.sv\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:38: Define or directive not defined: \'`ALU_OP_WIDTH\'\n  input  wire [`ALU_OP_WIDTH-1:0]   sel_i,  \n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:40: Define or directive not defined: \'`DATA_WIDTH\'\n  input  wire [`DATA_WIDTH-1:0]     op_a_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:41: Define or directive not defined: \'`DATA_WIDTH\'\n  input  wire [`DATA_WIDTH-1:0]     op_b_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:42: Define or directive not defined: \'`DATA_WIDTH\'\n  output reg  [`DATA_WIDTH-1:0]     res_ro,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:46: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n  input  wire [`REG_ADDR_WIDTH-1:0] dest_addr_i,\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:47: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n  output reg  [`REG_ADDR_WIDTH-1:0] dest_addr_ro,\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:56: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] adder_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:57: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] and_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:58: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] or_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:59: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] xor_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:60: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] less_than_sign_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:61: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] less_than_unsign_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:62: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] shifter_right_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:63: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH-1:0] shifter_left_res;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:66: Define or directive not defined: \'`DATA_WIDTH\'\nreg  [`DATA_WIDTH-1:0] res_w;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:105: Define or directive not defined: \'`DATA_WIDTH\'\nripple_carry_adder_Nb #(.N(`DATA_WIDTH)) ripple_carry_adder_32b_inst (\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:119: Define or directive not defined: \'`DATA_WIDTH\'\nless_than_sign_Nb #(.N(`DATA_WIDTH)) less_than_sign_32b_inst\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:125: Define or directive not defined: \'`DATA_WIDTH\'\nless_than_unsign_Nb #(.N(`DATA_WIDTH)) less_than_unsign_32b_inst\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:131: Define or directive not defined: \'`DATA_WIDTH\'\nequality_Nb #(.N(`DATA_WIDTH)) equality_32b_inst\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:160: Define or directive not defined: \'`ALU_OP_ADD\'\n    `ALU_OP_ADD: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:160: syntax error, unexpected \':\', expecting endcase\n    `ALU_OP_ADD: begin\n               ^\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:164: Define or directive not defined: \'`ALU_OP_SUB\'\n    `ALU_OP_SUB: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:164: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SUB: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:168: Define or directive not defined: \'`ALU_OP_SLL\'\n    `ALU_OP_SLL: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:168: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SLL: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:172: Define or directive not defined: \'`ALU_OP_SLT\'\n    `ALU_OP_SLT: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:172: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SLT: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:176: Define or directive not defined: \'`ALU_OP_SLTU\'\n    `ALU_OP_SLTU: begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:176: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SLTU: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:180: Define or directive not defined: \'`ALU_OP_XOR\'\n    `ALU_OP_XOR: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:180: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_XOR: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:184: Define or directive not defined: \'`ALU_OP_SRL\'\n    `ALU_OP_SRL: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:184: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SRL: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:188: Define or directive not defined: \'`ALU_OP_SRA\'\n    `ALU_OP_SRA: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:188: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_SRA: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:192: Define or directive not defined: \'`ALU_OP_OR\'\n    `ALU_OP_OR: begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:192: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_OR: begin\n                ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:196: Define or directive not defined: \'`ALU_OP_AND\'\n    `ALU_OP_AND: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:196: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ALU_OP_AND: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/jedro_1_alu.v:200: syntax error, unexpected \':\', expecting clocking\n    default: begin \n           ^\n%Error: Cannot continue\n'
module jedro_1_alu
(
  input  wire clk_i,
  input  wire rstn_i,

  input  wire [`ALU_OP_WIDTH-1:0]   sel_i,

  input  wire [`DATA_WIDTH-1:0]     op_a_i,
  input  wire [`DATA_WIDTH-1:0]     op_b_i,
  output reg  [`DATA_WIDTH-1:0]     res_ro,
  output reg                       ops_eq_ro,
  output reg                       overflow_ro,

  input  wire [`REG_ADDR_WIDTH-1:0] dest_addr_i,
  output reg  [`REG_ADDR_WIDTH-1:0] dest_addr_ro,
  
  input  wire                      wb_i,
  output reg                       wb_ro
);


wire [`DATA_WIDTH-1:0] adder_res;
wire [`DATA_WIDTH-1:0] and_res;
wire [`DATA_WIDTH-1:0] or_res;
wire [`DATA_WIDTH-1:0] xor_res;
wire [`DATA_WIDTH-1:0] less_than_sign_res;
wire [`DATA_WIDTH-1:0] less_than_unsign_res;
wire [`DATA_WIDTH-1:0] shifter_right_res;
wire [`DATA_WIDTH-1:0] shifter_left_res;
wire                   ops_eq_res;
wire                   adder_overflow;
reg  [`DATA_WIDTH-1:0] res_w;



always@(posedge clk_i) begin
  if (rstn_i == 1'b0) begin
    overflow_ro <= 0;
    res_ro <= 0;
    ops_eq_ro <= 0;
  end
  else begin
    overflow_ro <= adder_overflow;
	res_ro <= res_w;
    ops_eq_ro <= ops_eq_res;
  end
end



always@(posedge clk_i) begin
  if (rstn_i == 1'b0) begin
    wb_ro <= 0;
    dest_addr_ro <= 0; 
  end
  else begin
    wb_ro <= wb_i; 
    dest_addr_ro <= dest_addr_i; 
  end
end




ripple_carry_adder_Nb #(.N(`DATA_WIDTH)) ripple_carry_adder_32b_inst (
  .carry_i (1'b0),
  .opa_i   (op_a_i),
  .opb_i   (op_b_i),
  .inv_b_i (sel_i[3]),
  .res_o  (adder_res),
  .carry_o (adder_overflow)
);

assign and_res = op_a_i & op_b_i;
assign or_res = op_a_i | op_b_i;
assign xor_res = op_a_i ^ op_b_i;


less_than_sign_Nb #(.N(`DATA_WIDTH)) less_than_sign_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (less_than_sign_res)
);
less_than_unsign_Nb #(.N(`DATA_WIDTH)) less_than_unsign_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (less_than_unsign_res)
);
equality_Nb #(.N(`DATA_WIDTH)) equality_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (ops_eq_res)
);


barrel_shifter_left_32b shifter_left_32b_inst
(
  .in    (op_a_i),
  .cntrl (op_b_i[5-1:0]),
  .out   (shifter_left_res)
);
barrel_shifter_right_32b shifter_right_32b_inst
(
  .in    (op_a_i),
  .cntrl (op_b_i[5-1:0]),
  .arith (sel_i[3]),
  .out   (shifter_right_res)
);



always@(*)
begin
  case (sel_i)
    `ALU_OP_ADD: begin
      res_w = adder_res; 
    end

    `ALU_OP_SUB: begin
      res_w = adder_res;
    end

    `ALU_OP_SLL: begin
      res_w = shifter_left_res; 
    end

    `ALU_OP_SLT: begin
      res_w = less_than_sign_res;
    end

    `ALU_OP_SLTU: begin
      res_w = less_than_unsign_res;
    end

    `ALU_OP_XOR: begin
      res_w = xor_res;
    end

    `ALU_OP_SRL: begin
      res_w = shifter_right_res;
    end

    `ALU_OP_SRA: begin
      res_w = shifter_right_res;
    end

    `ALU_OP_OR: begin
      res_w = or_res;
    end

    `ALU_OP_AND: begin
      res_w = and_res; 
    end

    default: begin 
      res_w = 32'b0;
    end
  endcase
end

endmodule
module jedro_1_alu
(
  input  wire clk_i,
  input  wire rstn_i,

  input  wire [`ALU_OP_WIDTH-1:0]   sel_i,

  input  wire [`DATA_WIDTH-1:0]     op_a_i,
  input  wire [`DATA_WIDTH-1:0]     op_b_i,
  output reg  [`DATA_WIDTH-1:0]     res_ro,
  output reg                       ops_eq_ro,
  output reg                       overflow_ro,

  input  wire [`REG_ADDR_WIDTH-1:0] dest_addr_i,
  output reg  [`REG_ADDR_WIDTH-1:0] dest_addr_ro,
  
  input  wire                      wb_i,
  output reg                       wb_ro
);



wire [`DATA_WIDTH-1:0] adder_res;
wire [`DATA_WIDTH-1:0] and_res;
wire [`DATA_WIDTH-1:0] or_res;
wire [`DATA_WIDTH-1:0] xor_res;
wire [`DATA_WIDTH-1:0] less_than_sign_res;
wire [`DATA_WIDTH-1:0] less_than_unsign_res;
wire [`DATA_WIDTH-1:0] shifter_right_res;
wire [`DATA_WIDTH-1:0] shifter_left_res;
wire                   ops_eq_res;
wire                   adder_overflow;
reg  [`DATA_WIDTH-1:0] res_w;



always@(posedge clk_i) begin
  if (rstn_i == 1'b0) begin
    overflow_ro <= 0;
    res_ro <= 0;
    ops_eq_ro <= 0;
  end
  else begin
    overflow_ro <= adder_overflow;
	res_ro <= res_w;
    ops_eq_ro <= ops_eq_res;
  end
end



always@(posedge clk_i) begin
  if (rstn_i == 1'b0) begin
    wb_ro <= 0;
    dest_addr_ro <= 0; 
  end
  else begin
    wb_ro <= wb_i; 
    dest_addr_ro <= dest_addr_i; 
  end
end




ripple_carry_adder_Nb #(.N(`DATA_WIDTH)) ripple_carry_adder_32b_inst (
  .carry_i (1'b0),
  .opa_i   (op_a_i),
  .opb_i   (op_b_i),
  .inv_b_i (sel_i[3]),
  .res_o  (adder_res),
  .carry_o (adder_overflow)
);

assign and_res = op_a_i & op_b_i;
assign or_res = op_a_i | op_b_i;
assign xor_res = op_a_i ^ op_b_i;


less_than_sign_Nb #(.N(`DATA_WIDTH)) less_than_sign_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (less_than_sign_res)
);
less_than_unsign_Nb #(.N(`DATA_WIDTH)) less_than_unsign_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (less_than_unsign_res)
);
equality_Nb #(.N(`DATA_WIDTH)) equality_32b_inst
(
  .a (op_a_i),
  .b (op_b_i),
  .r (ops_eq_res)
);


barrel_shifter_left_32b shifter_left_32b_inst
(
  .in    (op_a_i),
  .cntrl (op_b_i[5-1:0]),
  .out   (shifter_left_res)
);
barrel_shifter_right_32b shifter_right_32b_inst
(
  .in    (op_a_i),
  .cntrl (op_b_i[5-1:0]),
  .arith (sel_i[3]),
  .out   (shifter_right_res)
);



always@(*)
begin
  case (sel_i)
    `ALU_OP_ADD: begin
      res_w = adder_res; 
    end

    `ALU_OP_SUB: begin
      res_w = adder_res;
    end

    `ALU_OP_SLL: begin
      res_w = shifter_left_res; 
    end

    `ALU_OP_SLT: begin
      res_w = less_than_sign_res;
    end

    `ALU_OP_SLTU: begin
      res_w = less_than_unsign_res;
    end

    `ALU_OP_XOR: begin
      res_w = xor_res;
    end

    `ALU_OP_SRL: begin
      res_w = shifter_right_res;
    end

    `ALU_OP_SRA: begin
      res_w = shifter_right_res;
    end

    `ALU_OP_OR: begin
      res_w = or_res;
    end

    `ALU_OP_AND: begin
      res_w = and_res; 
    end

    default: begin 
      res_w = 32'b0;
    end
  endcase
end

endmodule