data/full_repos/permissive/469979476/language/9.v
data/verilator_xmls/466981ed-1189-492f-a4f0-e60534a2343e.xml
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );

    wire and1,and2,or1;
    assign and1 = (a&b);
    assign and2 = (c&d);
    assign or1  = and1|and2;
    assign out = or1;
    assign out_n = ~or1;

endmodule
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );


    wire and1,and2,or1;
    assign and1 = (a&b);
    assign and2 = (c&d);
    assign or1  = and1|and2;
    assign out = or1;
    assign out_n = ~or1;

endmodule