data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_and3 (z, a, b,c);

output z;
input  a;
input  b;
input  c;

bw_u1_nand3_4x u_nand2 ( .z(tmp), .a(a),  .b(b), .c(c) );
bw_u1_inv_8x   u_inv   ( .z(z),   .a(tmp) );

endmodule
module ctu_and3 (z, a, b,c);


output z;
input  a;
input  b;
input  c;

bw_u1_nand3_4x u_nand2 ( .z(tmp), .a(a),  .b(b), .c(c) );
bw_u1_inv_8x   u_inv   ( .z(z),   .a(tmp) );

endmodule