data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:14: Unsupported or unknown PLI call: $monitor\n  $monitor (" ENABLE = %b  D = %b Q = %b",enable,d,q);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 enable = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/avoid_latch_else.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module avoid_latch_else ();

reg q;
reg enable, d;

always @ (enable or d)
if (enable) begin
  q = d;
end else begin
  q = 0;
end

initial begin
  $monitor (" ENABLE = %b  D = %b Q = %b",enable,d,q);
  #1 enable = 0;
  #1 d = 0;
  #1 enable = 1;
  #1 d = 1;
  #1 d = 0;
  #1 d = 1;
  #1 d = 0;
  #1 d = 1;
  #1 enable = 0;
  #1 $finish;
end

endmodule
module avoid_latch_else ();


reg q;
reg enable, d;

always @ (enable or d)
if (enable) begin
  q = d;
end else begin
  q = 0;
end

initial begin
  $monitor (" ENABLE = %b  D = %b Q = %b",enable,d,q);
  #1 enable = 0;
  #1 d = 0;
  #1 enable = 1;
  #1 d = 1;
  #1 d = 0;
  #1 d = 1;
  #1 d = 0;
  #1 d = 1;
  #1 enable = 0;
  #1 $finish;
end

endmodule