data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/UPDOWN_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/UPDOWN_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk_tb = ~clk_tb;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/UPDOWN_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n            #20 l_tb = ~l_tb;\n            ^\n%Error: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/UPDOWN_TB.v:9: Cannot find file containing module: \'UPDOWN\'\n        UPDOWN COMP (\n        ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/UPDOWN\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/UPDOWN.v\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/UPDOWN.sv\n             UPDOWN\n             UPDOWN.v\n             UPDOWN.sv\n             obj_dir/UPDOWN\n             obj_dir/UPDOWN.v\n             obj_dir/UPDOWN.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UPDOWN_TB(
        );
        reg clk_tb,rst_tb;
        reg l_tb;
        reg ud_tb;
        reg [3:0] atb;
        wire [3:0] cnt_tb;    
        UPDOWN COMP (
        .clk1(clk_tb),
        .rst1(rst_tb),
        .load(l_tb),
        .ud(ud_tb),
        .a(atb),
        .tmp(cnt_tb)       
        );    
        initial 
            begin
            clk_tb = 0;
            rst_tb = 0;
            ud_tb = 0;
            l_tb= 1;
            atb= 3;
            end        
        always   
            begin
            #5 clk_tb = ~clk_tb;
            end        
       always   
            begin
            #20 l_tb = ~l_tb;
            end   
    endmodule
module UPDOWN_TB(
        );

        reg clk_tb,rst_tb;
        reg l_tb;
        reg ud_tb;
        reg [3:0] atb;
        wire [3:0] cnt_tb;    
        UPDOWN COMP (
        .clk1(clk_tb),
        .rst1(rst_tb),
        .load(l_tb),
        .ud(ud_tb),
        .a(atb),
        .tmp(cnt_tb)       
        );    
        initial 
            begin
            clk_tb = 0;
            rst_tb = 0;
            ud_tb = 0;
            l_tb= 1;
            atb= 3;
            end        
        always   
            begin
            #5 clk_tb = ~clk_tb;
            end        
       always   
            begin
            #20 l_tb = ~l_tb;
            end   
    endmodule