data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:331: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex1_pipe6_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:429: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex2_pipe6_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:498: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex3_pipe6_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:574: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex4_pipe6_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:625: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex5_pipe6_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:671: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex1_pipe7_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:743: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex2_pipe7_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:835: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex3_pipe7_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:908: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex4_pipe7_gated_clk (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_ctrl.v:957: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ctrl_ex5_pipe7_gated_clk (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module ct_vfpu_ctrl(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  ctrl_dp_ex2_pipe7_inst_vld,
  ctrl_ex1_pipe6_data_vld,
  ctrl_ex1_pipe6_data_vld_dup0,
  ctrl_ex1_pipe6_data_vld_dup1,
  ctrl_ex1_pipe6_data_vld_dup2,
  ctrl_ex1_pipe6_eu_sel,
  ctrl_ex1_pipe6_inst_vld,
  ctrl_ex1_pipe6_mfvr_inst_vld,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup0,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup1,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup2,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup3,
  ctrl_ex1_pipe7_data_vld,
  ctrl_ex1_pipe7_data_vld_dup0,
  ctrl_ex1_pipe7_data_vld_dup1,
  ctrl_ex1_pipe7_data_vld_dup2,
  ctrl_ex1_pipe7_eu_sel,
  ctrl_ex1_pipe7_mfvr_inst_vld,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup0,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup1,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup2,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup3,
  ctrl_ex2_pipe6_data_vld,
  ctrl_ex2_pipe6_data_vld_dup0,
  ctrl_ex2_pipe6_data_vld_dup1,
  ctrl_ex2_pipe6_data_vld_dup2,
  ctrl_ex2_pipe6_inst_vld,
  ctrl_ex2_pipe6_mfvr_inst_vld,
  ctrl_ex2_pipe7_data_vld,
  ctrl_ex2_pipe7_data_vld_dup0,
  ctrl_ex2_pipe7_data_vld_dup1,
  ctrl_ex2_pipe7_data_vld_dup2,
  ctrl_ex2_pipe7_inst_vld,
  ctrl_ex2_pipe7_mfvr_inst_vld,
  ctrl_ex3_pipe6_data_vld,
  ctrl_ex3_pipe6_data_vld_dup0,
  ctrl_ex3_pipe6_data_vld_dup1,
  ctrl_ex3_pipe6_data_vld_dup2,
  ctrl_ex3_pipe6_fwd_vld,
  ctrl_ex3_pipe6_inst_vld,
  ctrl_ex3_pipe7_data_vld,
  ctrl_ex3_pipe7_data_vld_dup0,
  ctrl_ex3_pipe7_data_vld_dup1,
  ctrl_ex3_pipe7_data_vld_dup2,
  ctrl_ex3_pipe7_fwd_vld,
  ctrl_ex3_pipe7_inst_vld,
  ctrl_ex4_pipe6_fwd_vld,
  ctrl_ex4_pipe6_inst_vld,
  ctrl_ex4_pipe7_fwd_vld,
  ctrl_ex4_pipe7_inst_vld,
  ctrl_ex5_pipe6_clk,
  ctrl_ex5_pipe7_clk,
  dp_ctrl_ex1_pipe6_data_vld_pre,
  dp_ctrl_ex1_pipe7_data_vld_pre,
  dp_ctrl_ex2_pipe6_data_vld_pre,
  dp_ctrl_ex2_pipe7_data_vld_pre,
  dp_ctrl_ex3_pipe6_data_vld_pre,
  dp_ctrl_ex3_pipe6_fwd_vld_pre,
  dp_ctrl_ex3_pipe7_data_vld_pre,
  dp_ctrl_ex3_pipe7_fwd_vld_pre,
  dp_ctrl_ex4_pipe6_fwd_vld_pre,
  dp_ctrl_ex4_pipe7_fwd_vld_pre,
  dp_ctrl_pipe6_vfdsu_inst_vld,
  dp_ex1_pipe6_dst_vld_pre,
  dp_ex1_pipe7_dst_vld_pre,
  dp_vfmau_rf_pipe6_sel,
  dp_vfmau_rf_pipe7_sel,
  forever_cpuclk,
  idu_vfpu_rf_pipe6_eu_sel,
  idu_vfpu_rf_pipe6_gateclk_sel,
  idu_vfpu_rf_pipe6_sel,
  idu_vfpu_rf_pipe7_eu_sel,
  idu_vfpu_rf_pipe7_gateclk_sel,
  idu_vfpu_rf_pipe7_sel,
  iu_vfpu_ex1_pipe0_mtvr_inst,
  iu_vfpu_ex1_pipe0_mtvr_vld,
  iu_vfpu_ex1_pipe1_mtvr_inst,
  iu_vfpu_ex1_pipe1_mtvr_vld,
  pad_yy_icg_scan_en,
  pipe6_dp_vfdsu_inst_vld,
  rtu_yy_xx_flush,
  vdivu_vfpu_ex1_pipe6_result_vld
);


input           cp0_vfpu_icg_en;                  
input           cp0_yy_clk_en;                    
input           cpurst_b;                         
input           dp_ctrl_ex1_pipe6_data_vld_pre;   
input           dp_ctrl_ex1_pipe7_data_vld_pre;   
input           dp_ctrl_ex2_pipe6_data_vld_pre;   
input           dp_ctrl_ex2_pipe7_data_vld_pre;   
input           dp_ctrl_ex3_pipe6_data_vld_pre;   
input           dp_ctrl_ex3_pipe6_fwd_vld_pre;    
input           dp_ctrl_ex3_pipe7_data_vld_pre;   
input           dp_ctrl_ex3_pipe7_fwd_vld_pre;    
input           dp_ctrl_ex4_pipe6_fwd_vld_pre;    
input           dp_ctrl_ex4_pipe7_fwd_vld_pre;    
input           dp_ctrl_pipe6_vfdsu_inst_vld;     
input           dp_ex1_pipe6_dst_vld_pre;         
input           dp_ex1_pipe7_dst_vld_pre;         
input           forever_cpuclk;                   
input   [11:0]  idu_vfpu_rf_pipe6_eu_sel;         
input           idu_vfpu_rf_pipe6_gateclk_sel;    
input           idu_vfpu_rf_pipe6_sel;            
input   [11:0]  idu_vfpu_rf_pipe7_eu_sel;         
input           idu_vfpu_rf_pipe7_gateclk_sel;    
input           idu_vfpu_rf_pipe7_sel;            
input   [4 :0]  iu_vfpu_ex1_pipe0_mtvr_inst;      
input           iu_vfpu_ex1_pipe0_mtvr_vld;       
input   [4 :0]  iu_vfpu_ex1_pipe1_mtvr_inst;      
input           iu_vfpu_ex1_pipe1_mtvr_vld;       
input           pad_yy_icg_scan_en;               
input           pipe6_dp_vfdsu_inst_vld;          
input           rtu_yy_xx_flush;                  
input           vdivu_vfpu_ex1_pipe6_result_vld;  
output          ctrl_dp_ex2_pipe7_inst_vld;       
output          ctrl_ex1_pipe6_data_vld;          
output          ctrl_ex1_pipe6_data_vld_dup0;     
output          ctrl_ex1_pipe6_data_vld_dup1;     
output          ctrl_ex1_pipe6_data_vld_dup2;     
output  [11:0]  ctrl_ex1_pipe6_eu_sel;            
output          ctrl_ex1_pipe6_inst_vld;          
output          ctrl_ex1_pipe6_mfvr_inst_vld;     
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup0; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup1; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup2; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup3; 
output          ctrl_ex1_pipe7_data_vld;          
output          ctrl_ex1_pipe7_data_vld_dup0;     
output          ctrl_ex1_pipe7_data_vld_dup1;     
output          ctrl_ex1_pipe7_data_vld_dup2;     
output  [11:0]  ctrl_ex1_pipe7_eu_sel;            
output          ctrl_ex1_pipe7_mfvr_inst_vld;     
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup0; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup1; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup2; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup3; 
output          ctrl_ex2_pipe6_data_vld;          
output          ctrl_ex2_pipe6_data_vld_dup0;     
output          ctrl_ex2_pipe6_data_vld_dup1;     
output          ctrl_ex2_pipe6_data_vld_dup2;     
output          ctrl_ex2_pipe6_inst_vld;          
output          ctrl_ex2_pipe6_mfvr_inst_vld;     
output          ctrl_ex2_pipe7_data_vld;          
output          ctrl_ex2_pipe7_data_vld_dup0;     
output          ctrl_ex2_pipe7_data_vld_dup1;     
output          ctrl_ex2_pipe7_data_vld_dup2;     
output          ctrl_ex2_pipe7_inst_vld;          
output          ctrl_ex2_pipe7_mfvr_inst_vld;     
output          ctrl_ex3_pipe6_data_vld;          
output          ctrl_ex3_pipe6_data_vld_dup0;     
output          ctrl_ex3_pipe6_data_vld_dup1;     
output          ctrl_ex3_pipe6_data_vld_dup2;     
output          ctrl_ex3_pipe6_fwd_vld;           
output          ctrl_ex3_pipe6_inst_vld;          
output          ctrl_ex3_pipe7_data_vld;          
output          ctrl_ex3_pipe7_data_vld_dup0;     
output          ctrl_ex3_pipe7_data_vld_dup1;     
output          ctrl_ex3_pipe7_data_vld_dup2;     
output          ctrl_ex3_pipe7_fwd_vld;           
output          ctrl_ex3_pipe7_inst_vld;          
output          ctrl_ex4_pipe6_fwd_vld;           
output          ctrl_ex4_pipe6_inst_vld;          
output          ctrl_ex4_pipe7_fwd_vld;           
output          ctrl_ex4_pipe7_inst_vld;          
output          ctrl_ex5_pipe6_clk;               
output          ctrl_ex5_pipe7_clk;               
output          dp_vfmau_rf_pipe6_sel;            
output          dp_vfmau_rf_pipe7_sel;            


reg             ctrl_ex1_pipe6_data_vld;          
reg             ctrl_ex1_pipe6_data_vld_dup0;     
reg             ctrl_ex1_pipe6_data_vld_dup1;     
reg             ctrl_ex1_pipe6_data_vld_dup2;     
reg     [11:0]  ctrl_ex1_pipe6_eu_sel_tmp;        
reg             ctrl_ex1_pipe6_inst_vld;          
reg             ctrl_ex1_pipe6_mfvr_inst_vld;     
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup0; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup1; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup2; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup3; 
reg             ctrl_ex1_pipe7_data_vld;          
reg             ctrl_ex1_pipe7_data_vld_dup0;     
reg             ctrl_ex1_pipe7_data_vld_dup1;     
reg             ctrl_ex1_pipe7_data_vld_dup2;     
reg     [11:0]  ctrl_ex1_pipe7_eu_sel_tmp;        
reg             ctrl_ex1_pipe7_inst_vld;          
reg             ctrl_ex1_pipe7_mfvr_inst_vld;     
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup0; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup1; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup2; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup3; 
reg             ctrl_ex2_pipe6_data_vld;          
reg             ctrl_ex2_pipe6_data_vld_dup0;     
reg             ctrl_ex2_pipe6_data_vld_dup1;     
reg             ctrl_ex2_pipe6_data_vld_dup2;     
reg             ctrl_ex2_pipe6_inst_vld;          
reg             ctrl_ex2_pipe6_mfvr_inst_vld;     
reg             ctrl_ex2_pipe7_data_vld;          
reg             ctrl_ex2_pipe7_data_vld_dup0;     
reg             ctrl_ex2_pipe7_data_vld_dup1;     
reg             ctrl_ex2_pipe7_data_vld_dup2;     
reg             ctrl_ex2_pipe7_inst_vld;          
reg             ctrl_ex2_pipe7_mfvr_inst_vld;     
reg             ctrl_ex3_pipe6_data_vld;          
reg             ctrl_ex3_pipe6_data_vld_dup0;     
reg             ctrl_ex3_pipe6_data_vld_dup1;     
reg             ctrl_ex3_pipe6_data_vld_dup2;     
reg             ctrl_ex3_pipe6_fwd_vld;           
reg             ctrl_ex3_pipe6_inst_vld;          
reg             ctrl_ex3_pipe7_data_vld;          
reg             ctrl_ex3_pipe7_data_vld_dup0;     
reg             ctrl_ex3_pipe7_data_vld_dup1;     
reg             ctrl_ex3_pipe7_data_vld_dup2;     
reg             ctrl_ex3_pipe7_fwd_vld;           
reg             ctrl_ex3_pipe7_inst_vld;          
reg             ctrl_ex4_pipe6_fwd_vld;           
reg             ctrl_ex4_pipe6_inst_vld;          
reg             ctrl_ex4_pipe7_fwd_vld;           
reg             ctrl_ex4_pipe7_inst_vld;          
reg             ctrl_ex5_pipe6_inst_vld;          
reg             ctrl_ex5_pipe7_inst_vld;          


wire            cp0_vfpu_icg_en;                  
wire            cp0_yy_clk_en;                    
wire            cpurst_b;                         
wire            ctrl_dp_ex2_pipe7_inst_vld;       
wire            ctrl_ex1_pipe6_clk;               
wire            ctrl_ex1_pipe6_en;                
wire    [11:0]  ctrl_ex1_pipe6_eu_sel;            
wire            ctrl_ex1_pipe6_inst_vld_pre;      
wire            ctrl_ex1_pipe6_mfvr_inst_vld_pre; 
wire            ctrl_ex1_pipe7_clk;               
wire            ctrl_ex1_pipe7_en;                
wire    [11:0]  ctrl_ex1_pipe7_eu_sel;            
wire            ctrl_ex1_pipe7_inst_vld_pre;      
wire            ctrl_ex1_pipe7_mfvr_inst_vld_pre; 
wire            ctrl_ex2_pipe6_clk;               
wire            ctrl_ex2_pipe6_data_vld_pre;      
wire            ctrl_ex2_pipe6_en;                
wire            ctrl_ex2_pipe6_inst_vld_pre;      
wire            ctrl_ex2_pipe7_clk;               
wire            ctrl_ex2_pipe7_en;                
wire            ctrl_ex2_pipe7_inst_vld_pre;      
wire            ctrl_ex3_pipe6_clk;               
wire            ctrl_ex3_pipe6_en;                
wire            ctrl_ex3_pipe7_clk;               
wire            ctrl_ex3_pipe7_en;                
wire            ctrl_ex4_pipe6_clk;               
wire            ctrl_ex4_pipe6_en;                
wire            ctrl_ex4_pipe7_clk;               
wire            ctrl_ex4_pipe7_en;                
wire            ctrl_ex5_pipe6_clk;               
wire            ctrl_ex5_pipe6_en;                
wire            ctrl_ex5_pipe6_inst_vld_pre;      
wire            ctrl_ex5_pipe7_clk;               
wire            ctrl_ex5_pipe7_en;                
wire            dp_ctrl_ex1_pipe6_data_vld_pre;   
wire            dp_ctrl_ex1_pipe7_data_vld_pre;   
wire            dp_ctrl_ex2_pipe6_data_vld_pre;   
wire            dp_ctrl_ex2_pipe7_data_vld_pre;   
wire            dp_ctrl_ex3_pipe6_data_vld_pre;   
wire            dp_ctrl_ex3_pipe6_fwd_vld_pre;    
wire            dp_ctrl_ex3_pipe7_data_vld_pre;   
wire            dp_ctrl_ex3_pipe7_fwd_vld_pre;    
wire            dp_ctrl_ex4_pipe6_fwd_vld_pre;    
wire            dp_ctrl_ex4_pipe7_fwd_vld_pre;    
wire            dp_ctrl_pipe6_vfdsu_inst_vld;     
wire            dp_ex1_pipe6_dst_vld_pre;         
wire            dp_ex1_pipe7_dst_vld_pre;         
wire            dp_vfmau_rf_pipe6_sel;            
wire            dp_vfmau_rf_pipe7_sel;            
wire            forever_cpuclk;                   
wire    [11:0]  idu_vfpu_rf_pipe6_eu_sel;         
wire            idu_vfpu_rf_pipe6_gateclk_sel;    
wire            idu_vfpu_rf_pipe6_sel;            
wire    [11:0]  idu_vfpu_rf_pipe7_eu_sel;         
wire            idu_vfpu_rf_pipe7_gateclk_sel;    
wire            idu_vfpu_rf_pipe7_sel;            
wire    [4 :0]  iu_vfpu_ex1_pipe0_mtvr_inst;      
wire            iu_vfpu_ex1_pipe0_mtvr_vld;       
wire    [4 :0]  iu_vfpu_ex1_pipe1_mtvr_inst;      
wire            iu_vfpu_ex1_pipe1_mtvr_vld;       
wire            pad_yy_icg_scan_en;               
wire            pipe6_dp_vfdsu_inst_vld;          
wire    [11:0]  pipe6_eu_sel;                     
wire    [11:0]  pipe6_mtvr_eu_sel;                
wire    [11:0]  pipe7_eu_sel;                     
wire    [11:0]  pipe7_mtvr_eu_sel;                
wire            rtu_yy_xx_flush;                  
wire            vdivu_vfpu_ex1_pipe6_result_vld;  



parameter EU_WIDTH = 12;









 assign ctrl_ex1_pipe6_en = idu_vfpu_rf_pipe6_gateclk_sel
                         || iu_vfpu_ex1_pipe0_mtvr_vld
                         || ctrl_ex1_pipe6_inst_vld;


gated_clk_cell  x_ctrl_ex1_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex1_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex1_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex1_pipe6_inst_vld <= ctrl_ex1_pipe6_inst_vld_pre;
end

always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
  end
end
assign ctrl_ex1_pipe6_mfvr_inst_vld_pre = ctrl_ex1_pipe6_inst_vld_pre && 
                                          dp_ex1_pipe6_dst_vld_pre;



always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe6_data_vld <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe6_data_vld <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe6_data_vld <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup0 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup1 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup2 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
  end
end




assign ctrl_ex1_pipe6_inst_vld_pre = idu_vfpu_rf_pipe6_sel
                                  || iu_vfpu_ex1_pipe0_mtvr_vld;







assign ctrl_ex2_pipe6_en =  ctrl_ex1_pipe6_inst_vld
                         || ctrl_ex2_pipe6_inst_vld 
                         || pipe6_dp_vfdsu_inst_vld 
                         || vdivu_vfpu_ex1_pipe6_result_vld;

gated_clk_cell  x_ctrl_ex2_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex2_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex2_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe6_inst_vld <= ctrl_ex2_pipe6_inst_vld_pre;
end

assign ctrl_ex2_pipe6_inst_vld_pre = ctrl_ex1_pipe6_inst_vld 
                                  || pipe6_dp_vfdsu_inst_vld 
                                  || vdivu_vfpu_ex1_pipe6_result_vld;

always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex2_pipe6_data_vld <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex2_pipe6_data_vld <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex2_pipe6_data_vld <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup0 <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup1 <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup2 <= ctrl_ex2_pipe6_data_vld_pre;
  end
end

assign ctrl_ex2_pipe6_data_vld_pre = dp_ctrl_ex2_pipe6_data_vld_pre && ctrl_ex1_pipe6_inst_vld 
                                  || pipe6_dp_vfdsu_inst_vld 
                                  || vdivu_vfpu_ex1_pipe6_result_vld;







 assign ctrl_ex3_pipe6_en = ctrl_ex2_pipe6_inst_vld
                         || ctrl_ex3_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex3_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex3_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex3_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex3_pipe6_inst_vld <= ctrl_ex2_pipe6_inst_vld;
end

always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex3_pipe6_data_vld <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush)  begin
    ctrl_ex3_pipe6_data_vld <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup2 <= 1'b0;
  end
  else  begin
    ctrl_ex3_pipe6_data_vld <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup0 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup1 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup2 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
  end
end







always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe6_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe6_fwd_vld <= 1'b0;
  else
    ctrl_ex3_pipe6_fwd_vld <= dp_ctrl_ex3_pipe6_fwd_vld_pre && ctrl_ex2_pipe6_inst_vld;
end






assign ctrl_ex4_pipe6_en =  ctrl_ex3_pipe6_inst_vld
                         || ctrl_ex4_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex4_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex4_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex4_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex4_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex4_pipe6_inst_vld <= ctrl_ex3_pipe6_inst_vld;
end

always @(posedge ctrl_ex4_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe6_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe6_fwd_vld <= 1'b0;
  else
    ctrl_ex4_pipe6_fwd_vld <= dp_ctrl_ex4_pipe6_fwd_vld_pre && ctrl_ex3_pipe6_inst_vld;
end








assign ctrl_ex5_pipe6_en =  ctrl_ex4_pipe6_inst_vld
                         || dp_ctrl_pipe6_vfdsu_inst_vld
                         || ctrl_ex5_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex5_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex5_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex5_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










assign ctrl_ex5_pipe6_inst_vld_pre = ctrl_ex4_pipe6_inst_vld
                                  || dp_ctrl_pipe6_vfdsu_inst_vld;



always @(posedge ctrl_ex5_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex5_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex5_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex5_pipe6_inst_vld <= ctrl_ex5_pipe6_inst_vld_pre;
end









 assign ctrl_ex1_pipe7_en = idu_vfpu_rf_pipe7_gateclk_sel
                         || iu_vfpu_ex1_pipe1_mtvr_vld
                         || ctrl_ex1_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex1_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex1_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex1_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex1_pipe7_inst_vld <= ctrl_ex1_pipe7_inst_vld_pre;
end
assign dp_vfmau_rf_pipe7_sel   = ctrl_ex1_pipe7_inst_vld_pre && pipe7_eu_sel[4];
assign dp_vfmau_rf_pipe6_sel   = ctrl_ex1_pipe6_inst_vld_pre && pipe6_eu_sel[4];
always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe7_data_vld <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe7_data_vld <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe7_data_vld <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup0 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup1 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup2 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;



  end
end






assign ctrl_ex1_pipe7_inst_vld_pre = idu_vfpu_rf_pipe7_sel
                                  || iu_vfpu_ex1_pipe1_mtvr_vld;






assign ctrl_ex2_pipe7_en =  ctrl_ex1_pipe7_inst_vld
                         || ctrl_ex2_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex2_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex2_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex2_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe7_inst_vld <= ctrl_ex2_pipe7_inst_vld_pre;
end

always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
  end
end
assign ctrl_ex1_pipe7_mfvr_inst_vld_pre = ctrl_ex1_pipe7_inst_vld_pre && 
                                          dp_ex1_pipe7_dst_vld_pre;


always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex2_pipe7_data_vld <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush)begin
    ctrl_ex2_pipe7_data_vld <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex2_pipe7_data_vld <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup0 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup1 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup2 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
  end
end

assign ctrl_ex2_pipe7_inst_vld_pre = ctrl_ex1_pipe7_inst_vld;

assign ctrl_dp_ex2_pipe7_inst_vld = ctrl_ex2_pipe7_inst_vld_pre;






 assign ctrl_ex3_pipe7_en = ctrl_ex2_pipe7_inst_vld
                         || ctrl_ex3_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex3_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex3_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex3_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex3_pipe7_inst_vld <= ctrl_ex2_pipe7_inst_vld;
end

always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)begin
    ctrl_ex3_pipe7_data_vld <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex3_pipe7_data_vld <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex3_pipe7_data_vld <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup0 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup1 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup2 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
  end
end




always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe7_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe7_fwd_vld <= 1'b0;
  else
    ctrl_ex3_pipe7_fwd_vld <= dp_ctrl_ex3_pipe7_fwd_vld_pre && ctrl_ex2_pipe7_inst_vld;
end





assign ctrl_ex4_pipe7_en =  ctrl_ex3_pipe7_inst_vld
                         || ctrl_ex4_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex4_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex4_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex4_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex4_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex4_pipe7_inst_vld <= ctrl_ex3_pipe7_inst_vld;
end

always @(posedge ctrl_ex4_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe7_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe7_fwd_vld <= 1'b0;
  else
    ctrl_ex4_pipe7_fwd_vld <= dp_ctrl_ex4_pipe7_fwd_vld_pre && ctrl_ex3_pipe7_inst_vld;
end







assign ctrl_ex5_pipe7_en =  ctrl_ex4_pipe7_inst_vld
                         || ctrl_ex5_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex5_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex5_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex5_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);













always @(posedge ctrl_ex5_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex5_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex5_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex5_pipe7_inst_vld <= ctrl_ex4_pipe7_inst_vld;
end











always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe6_mfvr_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe6_mfvr_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe6_mfvr_inst_vld <= ctrl_ex1_pipe6_mfvr_inst_vld;
end








                                   
always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe7_mfvr_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe7_mfvr_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe7_mfvr_inst_vld <= ctrl_ex1_pipe7_mfvr_inst_vld;
end











assign pipe6_mtvr_eu_sel[EU_WIDTH-1:0] = |iu_vfpu_ex1_pipe0_mtvr_inst[1:0]
                                         || iu_vfpu_ex1_pipe0_mtvr_inst[4]
                                         ? {{EU_WIDTH-1{1'b0}},1'b1}
                                         : {{EU_WIDTH-8{1'b0}},1'b1,7'b0};

assign pipe6_eu_sel[EU_WIDTH-1:0] = iu_vfpu_ex1_pipe0_mtvr_vld ? pipe6_mtvr_eu_sel[EU_WIDTH-1:0]
                                                               : idu_vfpu_rf_pipe6_eu_sel[EU_WIDTH-1:0];
  



always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= pipe6_eu_sel[EU_WIDTH-1:0];
end

assign ctrl_ex1_pipe6_eu_sel[EU_WIDTH-1:0] ={EU_WIDTH{ctrl_ex1_pipe6_inst_vld}} & ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0];




assign pipe7_mtvr_eu_sel[EU_WIDTH-1:0] = |iu_vfpu_ex1_pipe1_mtvr_inst[1:0] 
                                         || iu_vfpu_ex1_pipe1_mtvr_inst[4]
                                         ? {{EU_WIDTH-1{1'b0}},1'b1}
                                         : {{EU_WIDTH-8{1'b0}},1'b1,7'b0};

assign pipe7_eu_sel[EU_WIDTH-1:0] = iu_vfpu_ex1_pipe1_mtvr_vld ? pipe7_mtvr_eu_sel[EU_WIDTH-1:0]
                                                               : idu_vfpu_rf_pipe7_eu_sel[EU_WIDTH-1:0];
 



always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= pipe7_eu_sel[EU_WIDTH-1:0];
end

assign ctrl_ex1_pipe7_eu_sel[EU_WIDTH-1:0] ={EU_WIDTH{ctrl_ex1_pipe7_inst_vld}} & ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0];





endmodule
module ct_vfpu_ctrl(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  ctrl_dp_ex2_pipe7_inst_vld,
  ctrl_ex1_pipe6_data_vld,
  ctrl_ex1_pipe6_data_vld_dup0,
  ctrl_ex1_pipe6_data_vld_dup1,
  ctrl_ex1_pipe6_data_vld_dup2,
  ctrl_ex1_pipe6_eu_sel,
  ctrl_ex1_pipe6_inst_vld,
  ctrl_ex1_pipe6_mfvr_inst_vld,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup0,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup1,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup2,
  ctrl_ex1_pipe6_mfvr_inst_vld_dup3,
  ctrl_ex1_pipe7_data_vld,
  ctrl_ex1_pipe7_data_vld_dup0,
  ctrl_ex1_pipe7_data_vld_dup1,
  ctrl_ex1_pipe7_data_vld_dup2,
  ctrl_ex1_pipe7_eu_sel,
  ctrl_ex1_pipe7_mfvr_inst_vld,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup0,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup1,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup2,
  ctrl_ex1_pipe7_mfvr_inst_vld_dup3,
  ctrl_ex2_pipe6_data_vld,
  ctrl_ex2_pipe6_data_vld_dup0,
  ctrl_ex2_pipe6_data_vld_dup1,
  ctrl_ex2_pipe6_data_vld_dup2,
  ctrl_ex2_pipe6_inst_vld,
  ctrl_ex2_pipe6_mfvr_inst_vld,
  ctrl_ex2_pipe7_data_vld,
  ctrl_ex2_pipe7_data_vld_dup0,
  ctrl_ex2_pipe7_data_vld_dup1,
  ctrl_ex2_pipe7_data_vld_dup2,
  ctrl_ex2_pipe7_inst_vld,
  ctrl_ex2_pipe7_mfvr_inst_vld,
  ctrl_ex3_pipe6_data_vld,
  ctrl_ex3_pipe6_data_vld_dup0,
  ctrl_ex3_pipe6_data_vld_dup1,
  ctrl_ex3_pipe6_data_vld_dup2,
  ctrl_ex3_pipe6_fwd_vld,
  ctrl_ex3_pipe6_inst_vld,
  ctrl_ex3_pipe7_data_vld,
  ctrl_ex3_pipe7_data_vld_dup0,
  ctrl_ex3_pipe7_data_vld_dup1,
  ctrl_ex3_pipe7_data_vld_dup2,
  ctrl_ex3_pipe7_fwd_vld,
  ctrl_ex3_pipe7_inst_vld,
  ctrl_ex4_pipe6_fwd_vld,
  ctrl_ex4_pipe6_inst_vld,
  ctrl_ex4_pipe7_fwd_vld,
  ctrl_ex4_pipe7_inst_vld,
  ctrl_ex5_pipe6_clk,
  ctrl_ex5_pipe7_clk,
  dp_ctrl_ex1_pipe6_data_vld_pre,
  dp_ctrl_ex1_pipe7_data_vld_pre,
  dp_ctrl_ex2_pipe6_data_vld_pre,
  dp_ctrl_ex2_pipe7_data_vld_pre,
  dp_ctrl_ex3_pipe6_data_vld_pre,
  dp_ctrl_ex3_pipe6_fwd_vld_pre,
  dp_ctrl_ex3_pipe7_data_vld_pre,
  dp_ctrl_ex3_pipe7_fwd_vld_pre,
  dp_ctrl_ex4_pipe6_fwd_vld_pre,
  dp_ctrl_ex4_pipe7_fwd_vld_pre,
  dp_ctrl_pipe6_vfdsu_inst_vld,
  dp_ex1_pipe6_dst_vld_pre,
  dp_ex1_pipe7_dst_vld_pre,
  dp_vfmau_rf_pipe6_sel,
  dp_vfmau_rf_pipe7_sel,
  forever_cpuclk,
  idu_vfpu_rf_pipe6_eu_sel,
  idu_vfpu_rf_pipe6_gateclk_sel,
  idu_vfpu_rf_pipe6_sel,
  idu_vfpu_rf_pipe7_eu_sel,
  idu_vfpu_rf_pipe7_gateclk_sel,
  idu_vfpu_rf_pipe7_sel,
  iu_vfpu_ex1_pipe0_mtvr_inst,
  iu_vfpu_ex1_pipe0_mtvr_vld,
  iu_vfpu_ex1_pipe1_mtvr_inst,
  iu_vfpu_ex1_pipe1_mtvr_vld,
  pad_yy_icg_scan_en,
  pipe6_dp_vfdsu_inst_vld,
  rtu_yy_xx_flush,
  vdivu_vfpu_ex1_pipe6_result_vld
);



input           cp0_vfpu_icg_en;                  
input           cp0_yy_clk_en;                    
input           cpurst_b;                         
input           dp_ctrl_ex1_pipe6_data_vld_pre;   
input           dp_ctrl_ex1_pipe7_data_vld_pre;   
input           dp_ctrl_ex2_pipe6_data_vld_pre;   
input           dp_ctrl_ex2_pipe7_data_vld_pre;   
input           dp_ctrl_ex3_pipe6_data_vld_pre;   
input           dp_ctrl_ex3_pipe6_fwd_vld_pre;    
input           dp_ctrl_ex3_pipe7_data_vld_pre;   
input           dp_ctrl_ex3_pipe7_fwd_vld_pre;    
input           dp_ctrl_ex4_pipe6_fwd_vld_pre;    
input           dp_ctrl_ex4_pipe7_fwd_vld_pre;    
input           dp_ctrl_pipe6_vfdsu_inst_vld;     
input           dp_ex1_pipe6_dst_vld_pre;         
input           dp_ex1_pipe7_dst_vld_pre;         
input           forever_cpuclk;                   
input   [11:0]  idu_vfpu_rf_pipe6_eu_sel;         
input           idu_vfpu_rf_pipe6_gateclk_sel;    
input           idu_vfpu_rf_pipe6_sel;            
input   [11:0]  idu_vfpu_rf_pipe7_eu_sel;         
input           idu_vfpu_rf_pipe7_gateclk_sel;    
input           idu_vfpu_rf_pipe7_sel;            
input   [4 :0]  iu_vfpu_ex1_pipe0_mtvr_inst;      
input           iu_vfpu_ex1_pipe0_mtvr_vld;       
input   [4 :0]  iu_vfpu_ex1_pipe1_mtvr_inst;      
input           iu_vfpu_ex1_pipe1_mtvr_vld;       
input           pad_yy_icg_scan_en;               
input           pipe6_dp_vfdsu_inst_vld;          
input           rtu_yy_xx_flush;                  
input           vdivu_vfpu_ex1_pipe6_result_vld;  
output          ctrl_dp_ex2_pipe7_inst_vld;       
output          ctrl_ex1_pipe6_data_vld;          
output          ctrl_ex1_pipe6_data_vld_dup0;     
output          ctrl_ex1_pipe6_data_vld_dup1;     
output          ctrl_ex1_pipe6_data_vld_dup2;     
output  [11:0]  ctrl_ex1_pipe6_eu_sel;            
output          ctrl_ex1_pipe6_inst_vld;          
output          ctrl_ex1_pipe6_mfvr_inst_vld;     
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup0; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup1; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup2; 
output          ctrl_ex1_pipe6_mfvr_inst_vld_dup3; 
output          ctrl_ex1_pipe7_data_vld;          
output          ctrl_ex1_pipe7_data_vld_dup0;     
output          ctrl_ex1_pipe7_data_vld_dup1;     
output          ctrl_ex1_pipe7_data_vld_dup2;     
output  [11:0]  ctrl_ex1_pipe7_eu_sel;            
output          ctrl_ex1_pipe7_mfvr_inst_vld;     
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup0; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup1; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup2; 
output          ctrl_ex1_pipe7_mfvr_inst_vld_dup3; 
output          ctrl_ex2_pipe6_data_vld;          
output          ctrl_ex2_pipe6_data_vld_dup0;     
output          ctrl_ex2_pipe6_data_vld_dup1;     
output          ctrl_ex2_pipe6_data_vld_dup2;     
output          ctrl_ex2_pipe6_inst_vld;          
output          ctrl_ex2_pipe6_mfvr_inst_vld;     
output          ctrl_ex2_pipe7_data_vld;          
output          ctrl_ex2_pipe7_data_vld_dup0;     
output          ctrl_ex2_pipe7_data_vld_dup1;     
output          ctrl_ex2_pipe7_data_vld_dup2;     
output          ctrl_ex2_pipe7_inst_vld;          
output          ctrl_ex2_pipe7_mfvr_inst_vld;     
output          ctrl_ex3_pipe6_data_vld;          
output          ctrl_ex3_pipe6_data_vld_dup0;     
output          ctrl_ex3_pipe6_data_vld_dup1;     
output          ctrl_ex3_pipe6_data_vld_dup2;     
output          ctrl_ex3_pipe6_fwd_vld;           
output          ctrl_ex3_pipe6_inst_vld;          
output          ctrl_ex3_pipe7_data_vld;          
output          ctrl_ex3_pipe7_data_vld_dup0;     
output          ctrl_ex3_pipe7_data_vld_dup1;     
output          ctrl_ex3_pipe7_data_vld_dup2;     
output          ctrl_ex3_pipe7_fwd_vld;           
output          ctrl_ex3_pipe7_inst_vld;          
output          ctrl_ex4_pipe6_fwd_vld;           
output          ctrl_ex4_pipe6_inst_vld;          
output          ctrl_ex4_pipe7_fwd_vld;           
output          ctrl_ex4_pipe7_inst_vld;          
output          ctrl_ex5_pipe6_clk;               
output          ctrl_ex5_pipe7_clk;               
output          dp_vfmau_rf_pipe6_sel;            
output          dp_vfmau_rf_pipe7_sel;            


reg             ctrl_ex1_pipe6_data_vld;          
reg             ctrl_ex1_pipe6_data_vld_dup0;     
reg             ctrl_ex1_pipe6_data_vld_dup1;     
reg             ctrl_ex1_pipe6_data_vld_dup2;     
reg     [11:0]  ctrl_ex1_pipe6_eu_sel_tmp;        
reg             ctrl_ex1_pipe6_inst_vld;          
reg             ctrl_ex1_pipe6_mfvr_inst_vld;     
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup0; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup1; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup2; 
reg             ctrl_ex1_pipe6_mfvr_inst_vld_dup3; 
reg             ctrl_ex1_pipe7_data_vld;          
reg             ctrl_ex1_pipe7_data_vld_dup0;     
reg             ctrl_ex1_pipe7_data_vld_dup1;     
reg             ctrl_ex1_pipe7_data_vld_dup2;     
reg     [11:0]  ctrl_ex1_pipe7_eu_sel_tmp;        
reg             ctrl_ex1_pipe7_inst_vld;          
reg             ctrl_ex1_pipe7_mfvr_inst_vld;     
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup0; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup1; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup2; 
reg             ctrl_ex1_pipe7_mfvr_inst_vld_dup3; 
reg             ctrl_ex2_pipe6_data_vld;          
reg             ctrl_ex2_pipe6_data_vld_dup0;     
reg             ctrl_ex2_pipe6_data_vld_dup1;     
reg             ctrl_ex2_pipe6_data_vld_dup2;     
reg             ctrl_ex2_pipe6_inst_vld;          
reg             ctrl_ex2_pipe6_mfvr_inst_vld;     
reg             ctrl_ex2_pipe7_data_vld;          
reg             ctrl_ex2_pipe7_data_vld_dup0;     
reg             ctrl_ex2_pipe7_data_vld_dup1;     
reg             ctrl_ex2_pipe7_data_vld_dup2;     
reg             ctrl_ex2_pipe7_inst_vld;          
reg             ctrl_ex2_pipe7_mfvr_inst_vld;     
reg             ctrl_ex3_pipe6_data_vld;          
reg             ctrl_ex3_pipe6_data_vld_dup0;     
reg             ctrl_ex3_pipe6_data_vld_dup1;     
reg             ctrl_ex3_pipe6_data_vld_dup2;     
reg             ctrl_ex3_pipe6_fwd_vld;           
reg             ctrl_ex3_pipe6_inst_vld;          
reg             ctrl_ex3_pipe7_data_vld;          
reg             ctrl_ex3_pipe7_data_vld_dup0;     
reg             ctrl_ex3_pipe7_data_vld_dup1;     
reg             ctrl_ex3_pipe7_data_vld_dup2;     
reg             ctrl_ex3_pipe7_fwd_vld;           
reg             ctrl_ex3_pipe7_inst_vld;          
reg             ctrl_ex4_pipe6_fwd_vld;           
reg             ctrl_ex4_pipe6_inst_vld;          
reg             ctrl_ex4_pipe7_fwd_vld;           
reg             ctrl_ex4_pipe7_inst_vld;          
reg             ctrl_ex5_pipe6_inst_vld;          
reg             ctrl_ex5_pipe7_inst_vld;          


wire            cp0_vfpu_icg_en;                  
wire            cp0_yy_clk_en;                    
wire            cpurst_b;                         
wire            ctrl_dp_ex2_pipe7_inst_vld;       
wire            ctrl_ex1_pipe6_clk;               
wire            ctrl_ex1_pipe6_en;                
wire    [11:0]  ctrl_ex1_pipe6_eu_sel;            
wire            ctrl_ex1_pipe6_inst_vld_pre;      
wire            ctrl_ex1_pipe6_mfvr_inst_vld_pre; 
wire            ctrl_ex1_pipe7_clk;               
wire            ctrl_ex1_pipe7_en;                
wire    [11:0]  ctrl_ex1_pipe7_eu_sel;            
wire            ctrl_ex1_pipe7_inst_vld_pre;      
wire            ctrl_ex1_pipe7_mfvr_inst_vld_pre; 
wire            ctrl_ex2_pipe6_clk;               
wire            ctrl_ex2_pipe6_data_vld_pre;      
wire            ctrl_ex2_pipe6_en;                
wire            ctrl_ex2_pipe6_inst_vld_pre;      
wire            ctrl_ex2_pipe7_clk;               
wire            ctrl_ex2_pipe7_en;                
wire            ctrl_ex2_pipe7_inst_vld_pre;      
wire            ctrl_ex3_pipe6_clk;               
wire            ctrl_ex3_pipe6_en;                
wire            ctrl_ex3_pipe7_clk;               
wire            ctrl_ex3_pipe7_en;                
wire            ctrl_ex4_pipe6_clk;               
wire            ctrl_ex4_pipe6_en;                
wire            ctrl_ex4_pipe7_clk;               
wire            ctrl_ex4_pipe7_en;                
wire            ctrl_ex5_pipe6_clk;               
wire            ctrl_ex5_pipe6_en;                
wire            ctrl_ex5_pipe6_inst_vld_pre;      
wire            ctrl_ex5_pipe7_clk;               
wire            ctrl_ex5_pipe7_en;                
wire            dp_ctrl_ex1_pipe6_data_vld_pre;   
wire            dp_ctrl_ex1_pipe7_data_vld_pre;   
wire            dp_ctrl_ex2_pipe6_data_vld_pre;   
wire            dp_ctrl_ex2_pipe7_data_vld_pre;   
wire            dp_ctrl_ex3_pipe6_data_vld_pre;   
wire            dp_ctrl_ex3_pipe6_fwd_vld_pre;    
wire            dp_ctrl_ex3_pipe7_data_vld_pre;   
wire            dp_ctrl_ex3_pipe7_fwd_vld_pre;    
wire            dp_ctrl_ex4_pipe6_fwd_vld_pre;    
wire            dp_ctrl_ex4_pipe7_fwd_vld_pre;    
wire            dp_ctrl_pipe6_vfdsu_inst_vld;     
wire            dp_ex1_pipe6_dst_vld_pre;         
wire            dp_ex1_pipe7_dst_vld_pre;         
wire            dp_vfmau_rf_pipe6_sel;            
wire            dp_vfmau_rf_pipe7_sel;            
wire            forever_cpuclk;                   
wire    [11:0]  idu_vfpu_rf_pipe6_eu_sel;         
wire            idu_vfpu_rf_pipe6_gateclk_sel;    
wire            idu_vfpu_rf_pipe6_sel;            
wire    [11:0]  idu_vfpu_rf_pipe7_eu_sel;         
wire            idu_vfpu_rf_pipe7_gateclk_sel;    
wire            idu_vfpu_rf_pipe7_sel;            
wire    [4 :0]  iu_vfpu_ex1_pipe0_mtvr_inst;      
wire            iu_vfpu_ex1_pipe0_mtvr_vld;       
wire    [4 :0]  iu_vfpu_ex1_pipe1_mtvr_inst;      
wire            iu_vfpu_ex1_pipe1_mtvr_vld;       
wire            pad_yy_icg_scan_en;               
wire            pipe6_dp_vfdsu_inst_vld;          
wire    [11:0]  pipe6_eu_sel;                     
wire    [11:0]  pipe6_mtvr_eu_sel;                
wire    [11:0]  pipe7_eu_sel;                     
wire    [11:0]  pipe7_mtvr_eu_sel;                
wire            rtu_yy_xx_flush;                  
wire            vdivu_vfpu_ex1_pipe6_result_vld;  



parameter EU_WIDTH = 12;









 assign ctrl_ex1_pipe6_en = idu_vfpu_rf_pipe6_gateclk_sel
                         || iu_vfpu_ex1_pipe0_mtvr_vld
                         || ctrl_ex1_pipe6_inst_vld;


gated_clk_cell  x_ctrl_ex1_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex1_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex1_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex1_pipe6_inst_vld <= ctrl_ex1_pipe6_inst_vld_pre;
end

always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe6_mfvr_inst_vld <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup0 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup1 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup2 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
    ctrl_ex1_pipe6_mfvr_inst_vld_dup3 <= ctrl_ex1_pipe6_mfvr_inst_vld_pre;
  end
end
assign ctrl_ex1_pipe6_mfvr_inst_vld_pre = ctrl_ex1_pipe6_inst_vld_pre && 
                                          dp_ex1_pipe6_dst_vld_pre;



always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe6_data_vld <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe6_data_vld <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe6_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe6_data_vld <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup0 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup1 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
    ctrl_ex1_pipe6_data_vld_dup2 <= dp_ctrl_ex1_pipe6_data_vld_pre && idu_vfpu_rf_pipe6_sel || iu_vfpu_ex1_pipe0_mtvr_vld;
  end
end




assign ctrl_ex1_pipe6_inst_vld_pre = idu_vfpu_rf_pipe6_sel
                                  || iu_vfpu_ex1_pipe0_mtvr_vld;







assign ctrl_ex2_pipe6_en =  ctrl_ex1_pipe6_inst_vld
                         || ctrl_ex2_pipe6_inst_vld 
                         || pipe6_dp_vfdsu_inst_vld 
                         || vdivu_vfpu_ex1_pipe6_result_vld;

gated_clk_cell  x_ctrl_ex2_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex2_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex2_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe6_inst_vld <= ctrl_ex2_pipe6_inst_vld_pre;
end

assign ctrl_ex2_pipe6_inst_vld_pre = ctrl_ex1_pipe6_inst_vld 
                                  || pipe6_dp_vfdsu_inst_vld 
                                  || vdivu_vfpu_ex1_pipe6_result_vld;

always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex2_pipe6_data_vld <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex2_pipe6_data_vld <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe6_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex2_pipe6_data_vld <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup0 <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup1 <= ctrl_ex2_pipe6_data_vld_pre;
    ctrl_ex2_pipe6_data_vld_dup2 <= ctrl_ex2_pipe6_data_vld_pre;
  end
end

assign ctrl_ex2_pipe6_data_vld_pre = dp_ctrl_ex2_pipe6_data_vld_pre && ctrl_ex1_pipe6_inst_vld 
                                  || pipe6_dp_vfdsu_inst_vld 
                                  || vdivu_vfpu_ex1_pipe6_result_vld;







 assign ctrl_ex3_pipe6_en = ctrl_ex2_pipe6_inst_vld
                         || ctrl_ex3_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex3_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex3_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex3_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex3_pipe6_inst_vld <= ctrl_ex2_pipe6_inst_vld;
end

always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex3_pipe6_data_vld <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush)  begin
    ctrl_ex3_pipe6_data_vld <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe6_data_vld_dup2 <= 1'b0;
  end
  else  begin
    ctrl_ex3_pipe6_data_vld <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup0 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup1 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
    ctrl_ex3_pipe6_data_vld_dup2 <= dp_ctrl_ex3_pipe6_data_vld_pre && ctrl_ex2_pipe6_inst_vld;
  end
end







always @(posedge ctrl_ex3_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe6_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe6_fwd_vld <= 1'b0;
  else
    ctrl_ex3_pipe6_fwd_vld <= dp_ctrl_ex3_pipe6_fwd_vld_pre && ctrl_ex2_pipe6_inst_vld;
end






assign ctrl_ex4_pipe6_en =  ctrl_ex3_pipe6_inst_vld
                         || ctrl_ex4_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex4_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex4_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex4_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex4_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex4_pipe6_inst_vld <= ctrl_ex3_pipe6_inst_vld;
end

always @(posedge ctrl_ex4_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe6_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe6_fwd_vld <= 1'b0;
  else
    ctrl_ex4_pipe6_fwd_vld <= dp_ctrl_ex4_pipe6_fwd_vld_pre && ctrl_ex3_pipe6_inst_vld;
end








assign ctrl_ex5_pipe6_en =  ctrl_ex4_pipe6_inst_vld
                         || dp_ctrl_pipe6_vfdsu_inst_vld
                         || ctrl_ex5_pipe6_inst_vld;

gated_clk_cell  x_ctrl_ex5_pipe6_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex5_pipe6_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex5_pipe6_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);










assign ctrl_ex5_pipe6_inst_vld_pre = ctrl_ex4_pipe6_inst_vld
                                  || dp_ctrl_pipe6_vfdsu_inst_vld;



always @(posedge ctrl_ex5_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex5_pipe6_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex5_pipe6_inst_vld <= 1'b0;
  else
    ctrl_ex5_pipe6_inst_vld <= ctrl_ex5_pipe6_inst_vld_pre;
end









 assign ctrl_ex1_pipe7_en = idu_vfpu_rf_pipe7_gateclk_sel
                         || iu_vfpu_ex1_pipe1_mtvr_vld
                         || ctrl_ex1_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex1_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex1_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex1_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex1_pipe7_inst_vld <= ctrl_ex1_pipe7_inst_vld_pre;
end
assign dp_vfmau_rf_pipe7_sel   = ctrl_ex1_pipe7_inst_vld_pre && pipe7_eu_sel[4];
assign dp_vfmau_rf_pipe6_sel   = ctrl_ex1_pipe6_inst_vld_pre && pipe6_eu_sel[4];
always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe7_data_vld <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe7_data_vld <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe7_data_vld <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup0 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup1 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;
    ctrl_ex1_pipe7_data_vld_dup2 <= dp_ctrl_ex1_pipe7_data_vld_pre && idu_vfpu_rf_pipe7_sel || iu_vfpu_ex1_pipe1_mtvr_vld;



  end
end






assign ctrl_ex1_pipe7_inst_vld_pre = idu_vfpu_rf_pipe7_sel
                                  || iu_vfpu_ex1_pipe1_mtvr_vld;






assign ctrl_ex2_pipe7_en =  ctrl_ex1_pipe7_inst_vld
                         || ctrl_ex2_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex2_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex2_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex2_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe7_inst_vld <= ctrl_ex2_pipe7_inst_vld_pre;
end

always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= 1'b0;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= 1'b0;
  end
  else begin
    ctrl_ex1_pipe7_mfvr_inst_vld <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup0 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup1 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup2 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
    ctrl_ex1_pipe7_mfvr_inst_vld_dup3 <= ctrl_ex1_pipe7_mfvr_inst_vld_pre;
  end
end
assign ctrl_ex1_pipe7_mfvr_inst_vld_pre = ctrl_ex1_pipe7_inst_vld_pre && 
                                          dp_ex1_pipe7_dst_vld_pre;


always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b) begin
    ctrl_ex2_pipe7_data_vld <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush)begin
    ctrl_ex2_pipe7_data_vld <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex2_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex2_pipe7_data_vld <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup0 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup1 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
    ctrl_ex2_pipe7_data_vld_dup2 <= dp_ctrl_ex2_pipe7_data_vld_pre && ctrl_ex1_pipe7_inst_vld;
  end
end

assign ctrl_ex2_pipe7_inst_vld_pre = ctrl_ex1_pipe7_inst_vld;

assign ctrl_dp_ex2_pipe7_inst_vld = ctrl_ex2_pipe7_inst_vld_pre;






 assign ctrl_ex3_pipe7_en = ctrl_ex2_pipe7_inst_vld
                         || ctrl_ex3_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex3_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex3_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex3_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex3_pipe7_inst_vld <= ctrl_ex2_pipe7_inst_vld;
end

always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)begin
    ctrl_ex3_pipe7_data_vld <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup2 <= 1'b0;
  end
  else if(rtu_yy_xx_flush) begin
    ctrl_ex3_pipe7_data_vld <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup0 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup1 <= 1'b0;
    ctrl_ex3_pipe7_data_vld_dup2 <= 1'b0;
  end
  else begin
    ctrl_ex3_pipe7_data_vld <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup0 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup1 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
    ctrl_ex3_pipe7_data_vld_dup2 <= dp_ctrl_ex3_pipe7_data_vld_pre && ctrl_ex2_pipe7_inst_vld;
  end
end




always @(posedge ctrl_ex3_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex3_pipe7_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex3_pipe7_fwd_vld <= 1'b0;
  else
    ctrl_ex3_pipe7_fwd_vld <= dp_ctrl_ex3_pipe7_fwd_vld_pre && ctrl_ex2_pipe7_inst_vld;
end





assign ctrl_ex4_pipe7_en =  ctrl_ex3_pipe7_inst_vld
                         || ctrl_ex4_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex4_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex4_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex4_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge ctrl_ex4_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex4_pipe7_inst_vld <= ctrl_ex3_pipe7_inst_vld;
end

always @(posedge ctrl_ex4_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex4_pipe7_fwd_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex4_pipe7_fwd_vld <= 1'b0;
  else
    ctrl_ex4_pipe7_fwd_vld <= dp_ctrl_ex4_pipe7_fwd_vld_pre && ctrl_ex3_pipe7_inst_vld;
end







assign ctrl_ex5_pipe7_en =  ctrl_ex4_pipe7_inst_vld
                         || ctrl_ex5_pipe7_inst_vld;

gated_clk_cell  x_ctrl_ex5_pipe7_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ctrl_ex5_pipe7_clk),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ctrl_ex5_pipe7_en ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);













always @(posedge ctrl_ex5_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex5_pipe7_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex5_pipe7_inst_vld <= 1'b0;
  else
    ctrl_ex5_pipe7_inst_vld <= ctrl_ex4_pipe7_inst_vld;
end











always @(posedge ctrl_ex2_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe6_mfvr_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe6_mfvr_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe6_mfvr_inst_vld <= ctrl_ex1_pipe6_mfvr_inst_vld;
end








                                   
always @(posedge ctrl_ex2_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex2_pipe7_mfvr_inst_vld <= 1'b0;
  else if(rtu_yy_xx_flush)
    ctrl_ex2_pipe7_mfvr_inst_vld <= 1'b0;
  else
    ctrl_ex2_pipe7_mfvr_inst_vld <= ctrl_ex1_pipe7_mfvr_inst_vld;
end











assign pipe6_mtvr_eu_sel[EU_WIDTH-1:0] = |iu_vfpu_ex1_pipe0_mtvr_inst[1:0]
                                         || iu_vfpu_ex1_pipe0_mtvr_inst[4]
                                         ? {{EU_WIDTH-1{1'b0}},1'b1}
                                         : {{EU_WIDTH-8{1'b0}},1'b1,7'b0};

assign pipe6_eu_sel[EU_WIDTH-1:0] = iu_vfpu_ex1_pipe0_mtvr_vld ? pipe6_mtvr_eu_sel[EU_WIDTH-1:0]
                                                               : idu_vfpu_rf_pipe6_eu_sel[EU_WIDTH-1:0];
  



always @(posedge ctrl_ex1_pipe6_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else
    ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0] <= pipe6_eu_sel[EU_WIDTH-1:0];
end

assign ctrl_ex1_pipe6_eu_sel[EU_WIDTH-1:0] ={EU_WIDTH{ctrl_ex1_pipe6_inst_vld}} & ctrl_ex1_pipe6_eu_sel_tmp[EU_WIDTH-1:0];




assign pipe7_mtvr_eu_sel[EU_WIDTH-1:0] = |iu_vfpu_ex1_pipe1_mtvr_inst[1:0] 
                                         || iu_vfpu_ex1_pipe1_mtvr_inst[4]
                                         ? {{EU_WIDTH-1{1'b0}},1'b1}
                                         : {{EU_WIDTH-8{1'b0}},1'b1,7'b0};

assign pipe7_eu_sel[EU_WIDTH-1:0] = iu_vfpu_ex1_pipe1_mtvr_vld ? pipe7_mtvr_eu_sel[EU_WIDTH-1:0]
                                                               : idu_vfpu_rf_pipe7_eu_sel[EU_WIDTH-1:0];
 



always @(posedge ctrl_ex1_pipe7_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else if(rtu_yy_xx_flush)
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= {EU_WIDTH{1'b0}};
  else
    ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0] <= pipe7_eu_sel[EU_WIDTH-1:0];
end

assign ctrl_ex1_pipe7_eu_sel[EU_WIDTH-1:0] ={EU_WIDTH{ctrl_ex1_pipe7_inst_vld}} & ctrl_ex1_pipe7_eu_sel_tmp[EU_WIDTH-1:0];





endmodule