data/full_repos/permissive/411457613/Pyverilog/verilogcode/casex.v
data/verilator_xmls/271d4565-1d76-4bce-8fa3-67a29b431b7f.xml
module TOP(CLK, RST);
  input CLK, RST;
  reg [7:0] cnt;
  always @(posedge CLK) begin
    if(RST) begin
      cnt <= 0;
    end else begin
      casex(cnt)
        'b00: begin
          cnt <= cnt + 1;
        end
        'b1x: begin
          cnt <= 0;
        end
        default: begin
          cnt <= cnt + 1;
        end
      endcase
    end
  end
endmodule
module TOP(CLK, RST);

  input CLK, RST;
  reg [7:0] cnt;
  always @(posedge CLK) begin
    if(RST) begin
      cnt <= 0;
    end else begin
      casex(cnt)
        'b00: begin
          cnt <= cnt + 1;
        end
        'b1x: begin
          cnt <= 0;
        end
        default: begin
          cnt <= cnt + 1;
        end
      endcase
    end
  end
endmodule