data/full_repos/permissive/419538859/lab8/lab8.v
data/verilator_xmls/72eaa1fa-e1a0-4b8a-9606-e8f8e9cdaa6a.xml
module key_buff(clk, rst, press, scan_code, key_code);
input clk, rst, press;
input[3:0] scan_code;
output[3:0]key_code;
reg[3:0]key_code;
always@(posedge clk or posedge rst) begin
if(rst)
key_code= 4'b0;
else
key_code= press ? scan_code:4'b0;
end 
endmodule
module key_buff(clk, rst, press, scan_code, key_code);

input clk, rst, press;
input[3:0] scan_code;
output[3:0]key_code;
reg[3:0]key_code;
always@(posedge clk or posedge rst) begin
if(rst)
key_code= 4'b0;
else
key_code= press ? scan_code:4'b0;
end 
endmodule