data/full_repos/permissive/516679177/TOP/CAT_32.v
data/verilator_xmls/802ebd20-2a95-4526-b80d-43c5a4f384cd.xml
module CAT_32(input [7:0] A,
              input [7:0] B,
              input [7:0] C,
              input [3:0] D,
              input [3:0] E,
              output reg [31:0] out
             ); 

  always @(*)
    begin
        out = {E, D, C, B, A};
    end
  
endmodule
module CAT_32(input [7:0] A,
              input [7:0] B,
              input [7:0] C,
              input [3:0] D,
              input [3:0] E,
              output reg [31:0] out
             );
 

  always @(*)
    begin
        out = {E, D, C, B, A};
    end
  
endmodule