data/full_repos/permissive/519759804/test_delayslot/test_cpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/519759804/test_delayslot/test_cpu.v:14: Unsupported: Ignoring delay on this delayed statement.\n #50 reset <= 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519759804/test_delayslot/test_cpu.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/519759804/test_delayslot/test_cpu.v:9: Cannot find file containing module: \'CPU\'\nCPU #(.USE_DELAY_SLOT(1),.Inst_Num(47),.Inst_Num_BIT(8)) cpu(reset, clk, PC, v0);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/519759804/test_delayslot,data/full_repos/permissive/519759804/CPU\n             data/full_repos/permissive/519759804/test_delayslot,data/full_repos/permissive/519759804/CPU.v\n             data/full_repos/permissive/519759804/test_delayslot,data/full_repos/permissive/519759804/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_cpu();
	
reg reset;
reg clk;
wire [31:0] PC;
wire [31:0] v0;

CPU #(.USE_DELAY_SLOT(1),.Inst_Num(47),.Inst_Num_BIT(8)) cpu(reset, clk, PC, v0);

initial begin
	reset <= 1;
	clk <= 1;
	#50 reset <= 0;
end

always #50 clk <= ~clk;
		
endmodule
module test_cpu();

	
reg reset;
reg clk;
wire [31:0] PC;
wire [31:0] v0;

CPU #(.USE_DELAY_SLOT(1),.Inst_Num(47),.Inst_Num_BIT(8)) cpu(reset, clk, PC, v0);

initial begin
	reset <= 1;
	clk <= 1;
	#50 reset <= 0;
end

always #50 clk <= ~clk;
		
endmodule