data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:12: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:21: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:24: Unsupported: wait statements\n        x0 = 59; x1 = 50; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);\n                                                 ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:24: Unsupported: wait statements\n        x0 = 59; x1 = 50; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);\n                                                                      ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:25: Unsupported: wait statements\n        x0 = 59; x1 = 50; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);\n                                                 ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:25: Unsupported: wait statements\n        x0 = 59; x1 = 50; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);\n                                                                      ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:26: Unsupported: wait statements\n        x0 = 50; x1 = 59; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);\n                                                 ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:26: Unsupported: wait statements\n        x0 = 50; x1 = 59; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);\n                                                                      ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:27: Unsupported: wait statements\n        x0 = 50; x1 = 59; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);\n                                                 ^~~~\n%Error: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:27: Unsupported: wait statements\n        x0 = 50; x1 = 59; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);\n                                                                      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm2/task1/tb_rtl_drawline.sv:29: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: Exiting due to 8 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_drawline();

    logic clk=0;
    logic rst_n=1;
    logic [2:0] colour,vga_colour;
    logic [7:0] x0, x1, vga_x;
    logic [6:0] y0, y1, vga_y;
    logic start, done, vga_plot;

    always #5 clk = ~clk;

    drawline dut(.*);

    initial
    begin
        start=0;
        colour = 2;
        rst_n = 0;
        #10
        rst_n = 1;

        x0 = 59; x1 = 50; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);
        x0 = 59; x1 = 50; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);
        x0 = 50; x1 = 59; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);
        x0 = 50; x1 = 59; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);

        #20;
        $display(done);
        $stop;
    end

endmodule
module tb_rtl_drawline();


    logic clk=0;
    logic rst_n=1;
    logic [2:0] colour,vga_colour;
    logic [7:0] x0, x1, vga_x;
    logic [6:0] y0, y1, vga_y;
    logic start, done, vga_plot;

    always #5 clk = ~clk;

    drawline dut(.*);

    initial
    begin
        start=0;
        colour = 2;
        rst_n = 0;
        #10
        rst_n = 1;

        x0 = 59; x1 = 50; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);
        x0 = 59; x1 = 50; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);
        x0 = 50; x1 = 59; y0=20; y1=25; start=1; wait(done); start=0; wait(!done);
        x0 = 50; x1 = 59; y0=25; y1=20; start=1; wait(done); start=0; wait(!done);

        #20;
        $display(done);
        $stop;
    end

endmodule