data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/prioarbiter.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/prioarbiter.sv:61: Logical Operator GENIF expects 1 bit on the If, but If\'s VARREF \'LOCK_IN\' generates 32 bits.\n                                                                                                                            : ... In instance prioarbiter\n  if (LOCK_IN) begin : gen_lock_in\n  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated/prioarbiter.sv:54: Cannot find file containing module: \'onehot_to_bin\'\n  onehot_to_bin #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/onehot_to_bin\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/onehot_to_bin.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/deprecated,data/full_repos/permissive/473423187/onehot_to_bin.sv\n             onehot_to_bin\n             onehot_to_bin.v\n             onehot_to_bin.sv\n             obj_dir/onehot_to_bin\n             obj_dir/onehot_to_bin.v\n             obj_dir/onehot_to_bin.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module prioarbiter #(
  parameter int unsigned NUM_REQ = 13,
  parameter int unsigned LOCK_IN = 0
) (
  input logic                         clk_i,
  input logic                         rst_ni,

  input logic                         flush_i,
  input logic                         en_i,
  input logic [NUM_REQ-1:0]           req_i,

  output logic [NUM_REQ-1:0]          ack_o,
  output logic                        vld_o,
  output logic [$clog2(NUM_REQ)-1:0]  idx_o
);

  localparam SEL_WIDTH = $clog2(NUM_REQ);

  logic [SEL_WIDTH-1:0] arb_sel_lock_d, arb_sel_lock_q;
  logic lock_d, lock_q;

  logic [$clog2(NUM_REQ)-1:0] idx;


  assign vld_o = (|req_i) & en_i;
  assign idx_o  = (lock_q) ? arb_sel_lock_q : idx;



  assign ack_o[0] = (req_i[0]) ? en_i : 1'b0;

  for (genvar i = 1; i < NUM_REQ; i++) begin : gen_arb_req_ports

      assign ack_o[i] = (req_i[i] & ~(|ack_o[i-1:0])) ? en_i : 1'b0;
  end

  onehot_to_bin #(
    .ONEHOT_WIDTH ( NUM_REQ )
  ) i_onehot_to_bin (
    .onehot ( ack_o ),
    .bin    ( idx   )
  );

  if (LOCK_IN) begin : gen_lock_in

    assign lock_d         = (|req_i) & ~en_i;
    assign arb_sel_lock_d = idx_o;
  end else begin

    assign lock_d         = '0;
    assign arb_sel_lock_d = '0;
  end

  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
    if (!rst_ni) begin
      lock_q         <= 1'b0;
      arb_sel_lock_q <= '0;
    end else begin
      if (flush_i) begin
        lock_q         <= 1'b0;
        arb_sel_lock_q <= '0;
      end else begin
        lock_q         <= lock_d;
        arb_sel_lock_q <= arb_sel_lock_d;
      end
    end
  end

endmodule
module prioarbiter #(
  parameter int unsigned NUM_REQ = 13,
  parameter int unsigned LOCK_IN = 0
) (
  input logic                         clk_i,
  input logic                         rst_ni,

  input logic                         flush_i,
  input logic                         en_i,
  input logic [NUM_REQ-1:0]           req_i,

  output logic [NUM_REQ-1:0]          ack_o,
  output logic                        vld_o,
  output logic [$clog2(NUM_REQ)-1:0]  idx_o
);


  localparam SEL_WIDTH = $clog2(NUM_REQ);

  logic [SEL_WIDTH-1:0] arb_sel_lock_d, arb_sel_lock_q;
  logic lock_d, lock_q;

  logic [$clog2(NUM_REQ)-1:0] idx;


  assign vld_o = (|req_i) & en_i;
  assign idx_o  = (lock_q) ? arb_sel_lock_q : idx;



  assign ack_o[0] = (req_i[0]) ? en_i : 1'b0;

  for (genvar i = 1; i < NUM_REQ; i++) begin : gen_arb_req_ports

      assign ack_o[i] = (req_i[i] & ~(|ack_o[i-1:0])) ? en_i : 1'b0;
  end

  onehot_to_bin #(
    .ONEHOT_WIDTH ( NUM_REQ )
  ) i_onehot_to_bin (
    .onehot ( ack_o ),
    .bin    ( idx   )
  );

  if (LOCK_IN) begin : gen_lock_in

    assign lock_d         = (|req_i) & ~en_i;
    assign arb_sel_lock_d = idx_o;
  end else begin

    assign lock_d         = '0;
    assign arb_sel_lock_d = '0;
  end

  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
    if (!rst_ni) begin
      lock_q         <= 1'b0;
      arb_sel_lock_q <= '0;
    end else begin
      if (flush_i) begin
        lock_q         <= 1'b0;
        arb_sel_lock_q <= '0;
      end else begin
        lock_q         <= lock_d;
        arb_sel_lock_q <= arb_sel_lock_d;
      end
    end
  end

endmodule