data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module processing_unit (
  input             clk
, input             clr
, output wire [7:0] instruction
, output wire       zero_flag
, output wire       carry_flag
, output wire [7:0] address
, output reg  [7:0] dbuso
, input       [7:0] dbusi
, input             ld_r0
, output wire [7:0] regR0
, input             ld_r1
, output wire [7:0] regR1
, input             ld_r2
, output wire [7:0] regR2
, input             ld_r3
, output wire [7:0] regR3
, input             ld_ir
, input             ld_address_reg
, input             ld_reg_y
, input             ld_reg_z
, input             ld_pc
, input             inc_pc
, input       [2:0] sel_dbus_mux
, input       [1:0] sel_bus2_mux
);


  wire       reg_ZeroFlag, reg_CarryFlag;
  wire                     alu_carry_flag;
  wire [7:0] reg_R0, reg_R1, reg_R2, reg_R3, reg_MAR, reg_IR, reg_PC, reg_Y;
  reg  [7:0] bus2;
  reg  [7:0] aluY;
  wire [7:0] aluAdderY;
  wire       alu_zero_flag = ~|aluY;
  wire [3:0] opcode = instruction [7:4];
  wire       aluAdderC = (opcode == `OPSUB) ? 1'b1 : ((opcode == `OPADD) ? 1'b0 : reg_CarryFlag);
  wire [7:0] aluAdderB = (opcode == `OPSUB) ? ~dbuso : dbuso;
  
  assign regR0       = reg_R0;
  assign regR1       = reg_R1;
  assign regR2       = reg_R2;
  assign regR3       = reg_R3;
  assign carry_flag  = reg_CarryFlag;
  assign zero_flag   = reg_ZeroFlag;
  assign address     = reg_MAR;
  assign instruction = reg_IR;
  

  MinxProgramCounter #(8) unit_PC (clk, clr, ld_pc, inc_pc, bus2, reg_PC);
  

  MinxRegister #(8) unit_MAR (clk, clr, ld_address_reg, bus2, reg_MAR);
  

  MinxRegister #(8) unit_IR  (clk, clr, ld_ir, bus2, reg_IR);
  

  MinxRegister #(8) unit_Y   (clk, clr, ld_reg_y, bus2, reg_Y);


  MinxRegister #(1) unit_ZF  (clk, clr, ld_reg_z, alu_zero_flag,  reg_ZeroFlag);
  MinxRegister #(1) unit_CF  (clk, clr, ld_reg_z, alu_carry_flag, reg_CarryFlag);


  MinxRegister #(8) unit_R0  (clk, clr, ld_r0, bus2, reg_R0);
  MinxRegister #(8) unit_R1  (clk, clr, ld_r1, bus2, reg_R1);
  MinxRegister #(8) unit_R2  (clk, clr, ld_r2, bus2, reg_R2);
  MinxRegister #(8) unit_R3  (clk, clr, ld_r3, bus2, reg_R3);

  always @* 
    case(sel_dbus_mux)
      3'b000  : dbuso <= reg_R0;
      3'b001  : dbuso <= reg_R1;
      3'b010  : dbuso <= reg_R2;
      3'b011  : dbuso <= reg_R3;
      3'b100  : dbuso <= reg_PC;
      3'b101  : dbuso <= 8'h00;
      3'b110  : dbuso <= 8'h00;
      3'b111  : dbuso <= 8'h00;
      default : dbuso <= 8'h00;
    endcase
  
  always @*
    case(sel_bus2_mux)
      2'b00   : bus2 <= aluY;
      2'b01   : bus2 <= dbuso;
      2'b10   : bus2 <= dbusi;
      2'b11   : bus2 <= 8'h00;
      default : bus2 <= 8'h00;
    endcase

  cla_adder_parm #(8) addmagic (aluAdderC, reg_Y, aluAdderB, aluAdderY, alu_carry_flag); 
  
  always @*
    case(opcode)
      `OPNOP  : aluY = 0;
      `OPADD  : aluY = aluAdderY;
      `OPADC  : aluY = aluAdderY;
      `OPSUB  : aluY = aluAdderY;
      `OPAND  : aluY = reg_Y & dbuso;
      `OPNOT  : aluY =        ~dbuso;
      `OPIOR  : aluY = reg_Y | dbuso;
      `OPEOR  : aluY = reg_Y ^ dbuso;
      default : aluY = 0;
    endcase

endmodule
module processing_unit (
  input             clk
, input             clr
, output wire [7:0] instruction
, output wire       zero_flag
, output wire       carry_flag
, output wire [7:0] address
, output reg  [7:0] dbuso
, input       [7:0] dbusi
, input             ld_r0
, output wire [7:0] regR0
, input             ld_r1
, output wire [7:0] regR1
, input             ld_r2
, output wire [7:0] regR2
, input             ld_r3
, output wire [7:0] regR3
, input             ld_ir
, input             ld_address_reg
, input             ld_reg_y
, input             ld_reg_z
, input             ld_pc
, input             inc_pc
, input       [2:0] sel_dbus_mux
, input       [1:0] sel_bus2_mux
);



  wire       reg_ZeroFlag, reg_CarryFlag;
  wire                     alu_carry_flag;
  wire [7:0] reg_R0, reg_R1, reg_R2, reg_R3, reg_MAR, reg_IR, reg_PC, reg_Y;
  reg  [7:0] bus2;
  reg  [7:0] aluY;
  wire [7:0] aluAdderY;
  wire       alu_zero_flag = ~|aluY;
  wire [3:0] opcode = instruction [7:4];
  wire       aluAdderC = (opcode == `OPSUB) ? 1'b1 : ((opcode == `OPADD) ? 1'b0 : reg_CarryFlag);
  wire [7:0] aluAdderB = (opcode == `OPSUB) ? ~dbuso : dbuso;
  
  assign regR0       = reg_R0;
  assign regR1       = reg_R1;
  assign regR2       = reg_R2;
  assign regR3       = reg_R3;
  assign carry_flag  = reg_CarryFlag;
  assign zero_flag   = reg_ZeroFlag;
  assign address     = reg_MAR;
  assign instruction = reg_IR;
  

  MinxProgramCounter #(8) unit_PC (clk, clr, ld_pc, inc_pc, bus2, reg_PC);
  

  MinxRegister #(8) unit_MAR (clk, clr, ld_address_reg, bus2, reg_MAR);
  

  MinxRegister #(8) unit_IR  (clk, clr, ld_ir, bus2, reg_IR);
  

  MinxRegister #(8) unit_Y   (clk, clr, ld_reg_y, bus2, reg_Y);


  MinxRegister #(1) unit_ZF  (clk, clr, ld_reg_z, alu_zero_flag,  reg_ZeroFlag);
  MinxRegister #(1) unit_CF  (clk, clr, ld_reg_z, alu_carry_flag, reg_CarryFlag);


  MinxRegister #(8) unit_R0  (clk, clr, ld_r0, bus2, reg_R0);
  MinxRegister #(8) unit_R1  (clk, clr, ld_r1, bus2, reg_R1);
  MinxRegister #(8) unit_R2  (clk, clr, ld_r2, bus2, reg_R2);
  MinxRegister #(8) unit_R3  (clk, clr, ld_r3, bus2, reg_R3);

  always @* 
    case(sel_dbus_mux)
      3'b000  : dbuso <= reg_R0;
      3'b001  : dbuso <= reg_R1;
      3'b010  : dbuso <= reg_R2;
      3'b011  : dbuso <= reg_R3;
      3'b100  : dbuso <= reg_PC;
      3'b101  : dbuso <= 8'h00;
      3'b110  : dbuso <= 8'h00;
      3'b111  : dbuso <= 8'h00;
      default : dbuso <= 8'h00;
    endcase
  
  always @*
    case(sel_bus2_mux)
      2'b00   : bus2 <= aluY;
      2'b01   : bus2 <= dbuso;
      2'b10   : bus2 <= dbusi;
      2'b11   : bus2 <= 8'h00;
      default : bus2 <= 8'h00;
    endcase

  cla_adder_parm #(8) addmagic (aluAdderC, reg_Y, aluAdderB, aluAdderY, alu_carry_flag); 
  
  always @*
    case(opcode)
      `OPNOP  : aluY = 0;
      `OPADD  : aluY = aluAdderY;
      `OPADC  : aluY = aluAdderY;
      `OPSUB  : aluY = aluAdderY;
      `OPAND  : aluY = reg_Y & dbuso;
      `OPNOT  : aluY =        ~dbuso;
      `OPIOR  : aluY = reg_Y | dbuso;
      `OPEOR  : aluY = reg_Y ^ dbuso;
      default : aluY = 0;
    endcase

endmodule