data/full_repos/permissive/499787978/projects/arty_s7_atrover/rtl/vexriscv_ram.v
data/verilator_xmls/00cc0726-a012-4943-b187-15c617cf0f43.xml
module vexriscv_ram #(
  parameter NB_COL = 4,
  parameter COL_WIDTH = 8,
  parameter RAM_DEPTH = 1024,
  parameter INIT_FILE = ""
)
(
  input wire clk,
  
  input wire                            ibus_en,
  input wire  [NB_COL-1:0]              ibus_we,
  input wire  [$clog2(RAM_DEPTH-1)-1:0] ibus_addr,
  input wire  [(NB_COL*COL_WIDTH)-1:0]  ibus_din,
  output wire [(NB_COL*COL_WIDTH)-1:0]  ibus_dout,
  
  input wire                            dbus_en,
  input wire  [NB_COL-1:0]              dbus_we,
  input wire  [$clog2(RAM_DEPTH-1)-1:0] dbus_addr,
  input wire  [(NB_COL*COL_WIDTH)-1:0]  dbus_din,
  output wire [(NB_COL*COL_WIDTH)-1:0]  dbus_dout
);
  
  reg [(NB_COL*COL_WIDTH)-1:0] vexriscv_mem[RAM_DEPTH-1:0];
  reg [(NB_COL*COL_WIDTH)-1:0] ibus_ram_data = {(NB_COL*COL_WIDTH){1'b0}};
  reg [(NB_COL*COL_WIDTH)-1:0] dbus_ram_data = {(NB_COL*COL_WIDTH){1'b0}};
  

  generate
    if (INIT_FILE != "") begin: use_init_file
      initial begin
        $readmemh(INIT_FILE, vexriscv_mem);
      end
    end else begin: init_bram_to_zero
      integer inx;
      initial
        for (inx = 0; inx < RAM_DEPTH; inx = inx + 1)
          vexriscv_mem[inx] = {(NB_COL*COL_WIDTH){1'b0}};
    end
  endgenerate
  
  generate
    genvar i;
       for (i = 0; i < NB_COL; i = i+1) begin: byte_write
         always @(posedge clk)
           if (ibus_en)
             if (ibus_we[i]) begin
               vexriscv_mem[ibus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ibus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
               ibus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ibus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end else begin
               ibus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= vexriscv_mem[ibus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end
             
         always @(posedge clk)
           if (dbus_en)
             if (dbus_we[i]) begin
               vexriscv_mem[dbus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dbus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
               dbus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dbus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end else begin
               dbus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= vexriscv_mem[dbus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end
       end
  endgenerate
  
  assign ibus_dout = ibus_ram_data;
  assign dbus_dout = dbus_ram_data;

endmodule
module vexriscv_ram #(
  parameter NB_COL = 4,
  parameter COL_WIDTH = 8,
  parameter RAM_DEPTH = 1024,
  parameter INIT_FILE = ""
)
(
  input wire clk,
  
  input wire                            ibus_en,
  input wire  [NB_COL-1:0]              ibus_we,
  input wire  [$clog2(RAM_DEPTH-1)-1:0] ibus_addr,
  input wire  [(NB_COL*COL_WIDTH)-1:0]  ibus_din,
  output wire [(NB_COL*COL_WIDTH)-1:0]  ibus_dout,
  
  input wire                            dbus_en,
  input wire  [NB_COL-1:0]              dbus_we,
  input wire  [$clog2(RAM_DEPTH-1)-1:0] dbus_addr,
  input wire  [(NB_COL*COL_WIDTH)-1:0]  dbus_din,
  output wire [(NB_COL*COL_WIDTH)-1:0]  dbus_dout
);

  
  reg [(NB_COL*COL_WIDTH)-1:0] vexriscv_mem[RAM_DEPTH-1:0];
  reg [(NB_COL*COL_WIDTH)-1:0] ibus_ram_data = {(NB_COL*COL_WIDTH){1'b0}};
  reg [(NB_COL*COL_WIDTH)-1:0] dbus_ram_data = {(NB_COL*COL_WIDTH){1'b0}};
  

  generate
    if (INIT_FILE != "") begin: use_init_file
      initial begin
        $readmemh(INIT_FILE, vexriscv_mem);
      end
    end else begin: init_bram_to_zero
      integer inx;
      initial
        for (inx = 0; inx < RAM_DEPTH; inx = inx + 1)
          vexriscv_mem[inx] = {(NB_COL*COL_WIDTH){1'b0}};
    end
  endgenerate
  
  generate
    genvar i;
       for (i = 0; i < NB_COL; i = i+1) begin: byte_write
         always @(posedge clk)
           if (ibus_en)
             if (ibus_we[i]) begin
               vexriscv_mem[ibus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ibus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
               ibus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ibus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end else begin
               ibus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= vexriscv_mem[ibus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end
             
         always @(posedge clk)
           if (dbus_en)
             if (dbus_we[i]) begin
               vexriscv_mem[dbus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dbus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
               dbus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dbus_din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end else begin
               dbus_ram_data[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= vexriscv_mem[dbus_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             end
       end
  endgenerate
  
  assign ibus_dout = ibus_ram_data;
  assign dbus_dout = dbus_ram_data;

endmodule