data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v
1: b'%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:23: Cannot find include file: tb_prog.v\n`include "tb_prog.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493514142/verilog/dv/FPU_Single,data/full_repos/permissive/493514142/tb_prog.v\n             data/full_repos/permissive/493514142/verilog/dv/FPU_Single,data/full_repos/permissive/493514142/tb_prog.v.v\n             data/full_repos/permissive/493514142/verilog/dv/FPU_Single,data/full_repos/permissive/493514142/tb_prog.v.sv\n             tb_prog.v\n             tb_prog.v.v\n             tb_prog.v.sv\n             obj_dir/tb_prog.v\n             obj_dir/tb_prog.v.v\n             obj_dir/tb_prog.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    always #12.5 clock <= (clock === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:50: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("FPU_Single.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:51: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, FPU_Single_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:139: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'h421FAF69);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:64: Unsupported: wait statements\n     wait(mprj_ready == 1\'b1)\n     ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:140: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC05FDF3C);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:141: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC636EF85);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:142: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC3F0D1EC);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:143: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC204B540);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:144: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'h444BBD70);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:145: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'h3EB2007E);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:146: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hBCA715C9);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:147: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC1E45772);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:148: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC0EBB646);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:149: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'h470BC01F);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:150: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC3FE6148);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:151: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'h4268AB02);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:152: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hC45CE8F6);\n            ^~~~\n%Error: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:153: Unsupported: wait statements\n            wait(mprj_io_0 == 32\'hBEB465E8);\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n        #170000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/493514142/verilog/dv/FPU_Single/FPU_Single_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO state = %h, at time = %0t  ", mprj_io_0[31:0], $time);\n  ^\n%Error: Exiting due to 19 error(s), 8 warning(s)\n'
module FPU_Single_tb();
    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;
    
    wire gpio;
    wire [37:0] mprj_io;

    wire [31:0] mprj_io_0;
    wire mprj_ready;
    
    assign mprj_io_0 = {mprj_io[4],mprj_io[36:6]};
    assign mprj_ready = mprj_io[37];
    
    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
    
    always #12.5 clock <= (clock === 1'b0);
    
    initial begin
        clock = 0;
    end
 
    initial begin
        $dumpfile("FPU_Single.vcd");
        $dumpvars(0, FPU_Single_tb);









    end

	initial begin
	    wait(mprj_ready == 1'b1)











            
            wait(mprj_io_0 == 32'h421FAF69);
            wait(mprj_io_0 == 32'hC05FDF3C);
            wait(mprj_io_0 == 32'hC636EF85);
            wait(mprj_io_0 == 32'hC3F0D1EC);
            wait(mprj_io_0 == 32'hC204B540);
            wait(mprj_io_0 == 32'h444BBD70);
            wait(mprj_io_0 == 32'h3EB2007E);
            wait(mprj_io_0 == 32'hBCA715C9);
            wait(mprj_io_0 == 32'hC1E45772);
            wait(mprj_io_0 == 32'hC0EBB646);
            wait(mprj_io_0 == 32'h470BC01F);
            wait(mprj_io_0 == 32'hC3FE6148);
            wait(mprj_io_0 == 32'h4268AB02);
            wait(mprj_io_0 == 32'hC45CE8F6);
            wait(mprj_io_0 == 32'hBEB465E8);
           
            
            $display("MPRJ-IO state = %h", mprj_io_0[31:0]);  
		
		`ifdef GL
	    	    $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end
	

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #170000;
        CSB = 1'b0;
    end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end
	
	always @(mprj_io_0) begin
		#1 $display("MPRJ-IO state = %h, at time = %0t  ", mprj_io_0[31:0], $time);
	end
	
	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire r_Rx_Serial;
	assign mprj_io[5] = r_Rx_Serial;
        
        assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("FPU_Single.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);
	
	
	uartprog #(
		.FILENAME("../hex/uart.hex")
	) prog_uut (

		.mprj_ready (mprj_ready),
		.r_Rx_Serial (r_Rx_Serial)
	);

endmodule
module FPU_Single_tb();

    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;
    
    wire gpio;
    wire [37:0] mprj_io;

    wire [31:0] mprj_io_0;
    wire mprj_ready;
    
    assign mprj_io_0 = {mprj_io[4],mprj_io[36:6]};
    assign mprj_ready = mprj_io[37];
    
    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
    
    always #12.5 clock <= (clock === 1'b0);
    
    initial begin
        clock = 0;
    end
 
    initial begin
        $dumpfile("FPU_Single.vcd");
        $dumpvars(0, FPU_Single_tb);









    end

	initial begin
	    wait(mprj_ready == 1'b1)











            
            wait(mprj_io_0 == 32'h421FAF69);
            wait(mprj_io_0 == 32'hC05FDF3C);
            wait(mprj_io_0 == 32'hC636EF85);
            wait(mprj_io_0 == 32'hC3F0D1EC);
            wait(mprj_io_0 == 32'hC204B540);
            wait(mprj_io_0 == 32'h444BBD70);
            wait(mprj_io_0 == 32'h3EB2007E);
            wait(mprj_io_0 == 32'hBCA715C9);
            wait(mprj_io_0 == 32'hC1E45772);
            wait(mprj_io_0 == 32'hC0EBB646);
            wait(mprj_io_0 == 32'h470BC01F);
            wait(mprj_io_0 == 32'hC3FE6148);
            wait(mprj_io_0 == 32'h4268AB02);
            wait(mprj_io_0 == 32'hC45CE8F6);
            wait(mprj_io_0 == 32'hBEB465E8);
           
            
            $display("MPRJ-IO state = %h", mprj_io_0[31:0]);  
		
		`ifdef GL
	    	    $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end
	

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #170000;
        CSB = 1'b0;
    end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end
	
	always @(mprj_io_0) begin
		#1 $display("MPRJ-IO state = %h, at time = %0t  ", mprj_io_0[31:0], $time);
	end
	
	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire r_Rx_Serial;
	assign mprj_io[5] = r_Rx_Serial;
        
        assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("FPU_Single.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);
	
	
	uartprog #(
		.FILENAME("../hex/uart.hex")
	) prog_uut (

		.mprj_ready (mprj_ready),
		.r_Rx_Serial (r_Rx_Serial)
	);

endmodule