data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v:506: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ex2_pipe_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v:661: Cannot find file containing module: 'ct_vfdsu_srt_radix16_with_sqrt'\nct_vfdsu_srt_radix16_with_sqrt  x_ct_vfdsu_srt_radix16_with_sqrt (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ct_vfdsu_srt(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  ex1_div,
  ex1_divisor,
  ex1_pipedown,
  ex1_remainder,
  ex1_sqrt,
  ex2_pipedown,
  ex2_srt_first_round,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  srt_ctrl_rem_zero,
  srt_ctrl_skip_srt,
  srt_secd_round,
  srt_sm_on,
  total_qt_rt_58,
  vfdsu_ex2_div,
  vfdsu_ex2_double,
  vfdsu_ex2_dz,
  vfdsu_ex2_expnt_add0,
  vfdsu_ex2_expnt_add1,
  vfdsu_ex2_nv,
  vfdsu_ex2_of_rm_lfn,
  vfdsu_ex2_op0_norm,
  vfdsu_ex2_op1_norm,
  vfdsu_ex2_qnan_f,
  vfdsu_ex2_qnan_sign,
  vfdsu_ex2_result_inf,
  vfdsu_ex2_result_qnan,
  vfdsu_ex2_result_sign,
  vfdsu_ex2_result_zero,
  vfdsu_ex2_rm,
  vfdsu_ex2_single,
  vfdsu_ex2_sqrt,
  vfdsu_ex2_srt_skip,
  vfdsu_ex3_doub_expnt_rst,
  vfdsu_ex3_double,
  vfdsu_ex3_dz,
  vfdsu_ex3_half_expnt_rst,
  vfdsu_ex3_id_srt_skip,
  vfdsu_ex3_nv,
  vfdsu_ex3_of,
  vfdsu_ex3_potnt_of,
  vfdsu_ex3_potnt_uf,
  vfdsu_ex3_qnan_f,
  vfdsu_ex3_qnan_sign,
  vfdsu_ex3_rem_sign,
  vfdsu_ex3_rem_zero,
  vfdsu_ex3_result_denorm_round_add_num,
  vfdsu_ex3_result_inf,
  vfdsu_ex3_result_lfn,
  vfdsu_ex3_result_qnan,
  vfdsu_ex3_result_sign,
  vfdsu_ex3_result_zero,
  vfdsu_ex3_rm,
  vfdsu_ex3_rslt_denorm,
  vfdsu_ex3_sing_expnt_rst,
  vfdsu_ex3_single,
  vfdsu_ex3_uf
);


input           cp0_vfpu_icg_en;                       
input           cp0_yy_clk_en;                         
input           cpurst_b;                              
input           ex1_div;                               
input   [52:0]  ex1_divisor;                           
input           ex1_pipedown;                          
input   [59:0]  ex1_remainder;                         
input           ex1_sqrt;                              
input           ex2_pipedown;                          
input           ex2_srt_first_round;                   
input           forever_cpuclk;                        
input           pad_yy_icg_scan_en;                    
input           srt_secd_round;                        
input           srt_sm_on;                             
input           vfdsu_ex2_div;                         
input           vfdsu_ex2_double;                      
input           vfdsu_ex2_dz;                          
input   [12:0]  vfdsu_ex2_expnt_add0;                  
input   [12:0]  vfdsu_ex2_expnt_add1;                  
input           vfdsu_ex2_nv;                          
input           vfdsu_ex2_of_rm_lfn;                   
input           vfdsu_ex2_op0_norm;                    
input           vfdsu_ex2_op1_norm;                    
input   [51:0]  vfdsu_ex2_qnan_f;                      
input           vfdsu_ex2_qnan_sign;                   
input           vfdsu_ex2_result_inf;                  
input           vfdsu_ex2_result_qnan;                 
input           vfdsu_ex2_result_sign;                 
input           vfdsu_ex2_result_zero;                 
input   [2 :0]  vfdsu_ex2_rm;                          
input           vfdsu_ex2_single;                      
input           vfdsu_ex2_sqrt;                        
input           vfdsu_ex2_srt_skip;                    
output          srt_ctrl_rem_zero;                     
output          srt_ctrl_skip_srt;                     
output  [57:0]  total_qt_rt_58;                        
output  [12:0]  vfdsu_ex3_doub_expnt_rst;              
output          vfdsu_ex3_double;                      
output          vfdsu_ex3_dz;                          
output  [12:0]  vfdsu_ex3_half_expnt_rst;              
output          vfdsu_ex3_id_srt_skip;                 
output          vfdsu_ex3_nv;                          
output          vfdsu_ex3_of;                          
output          vfdsu_ex3_potnt_of;                    
output          vfdsu_ex3_potnt_uf;                    
output  [51:0]  vfdsu_ex3_qnan_f;                      
output          vfdsu_ex3_qnan_sign;                   
output          vfdsu_ex3_rem_sign;                    
output          vfdsu_ex3_rem_zero;                    
output  [52:0]  vfdsu_ex3_result_denorm_round_add_num; 
output          vfdsu_ex3_result_inf;                  
output          vfdsu_ex3_result_lfn;                  
output          vfdsu_ex3_result_qnan;                 
output          vfdsu_ex3_result_sign;                 
output          vfdsu_ex3_result_zero;                 
output  [2 :0]  vfdsu_ex3_rm;                          
output          vfdsu_ex3_rslt_denorm;                 
output  [8 :0]  vfdsu_ex3_sing_expnt_rst;              
output          vfdsu_ex3_single;                      
output          vfdsu_ex3_uf;                          


reg     [52:0]  ex2_result_double_denorm_round_add_num; 
reg     [52:0]  ex2_result_half_denorm_round_add_num;  
reg     [52:0]  ex2_result_single_denorm_round_add_num; 
reg     [12:0]  vfdsu_ex3_doub_expnt_rst;              
reg             vfdsu_ex3_double;                      
reg             vfdsu_ex3_dz;                          
reg     [12:0]  vfdsu_ex3_half_expnt_rst;              
reg             vfdsu_ex3_id_srt_skip;                 
reg             vfdsu_ex3_nv;                          
reg             vfdsu_ex3_of;                          
reg             vfdsu_ex3_potnt_of;                    
reg             vfdsu_ex3_potnt_uf;                    
reg     [51:0]  vfdsu_ex3_qnan_f;                      
reg             vfdsu_ex3_qnan_sign;                   
reg             vfdsu_ex3_rem_sign;                    
reg     [52:0]  vfdsu_ex3_result_denorm_round_add_num; 
reg             vfdsu_ex3_result_inf;                  
reg             vfdsu_ex3_result_lfn;                  
reg             vfdsu_ex3_result_qnan;                 
reg             vfdsu_ex3_result_sign;                 
reg             vfdsu_ex3_result_zero;                 
reg     [2 :0]  vfdsu_ex3_rm;                          
reg             vfdsu_ex3_rslt_denorm;                 
reg     [8 :0]  vfdsu_ex3_sing_expnt_rst;              
reg             vfdsu_ex3_single;                      
reg             vfdsu_ex3_uf;                          


wire            cp0_vfpu_icg_en;                       
wire            cp0_yy_clk_en;                         
wire            cpurst_b;                              
wire            ex1_div;                               
wire    [52:0]  ex1_divisor;                           
wire            ex1_pipedown;                          
wire    [59:0]  ex1_remainder;                         
wire            ex1_sqrt;                              
wire            ex2_div_of;                            
wire            ex2_div_uf;                            
wire            ex2_doub_expnt_of;                     
wire            ex2_doub_expnt_uf;                     
wire            ex2_doub_potnt_of;                     
wire            ex2_doub_potnt_uf;                     
wire            ex2_double_id_nor_srt_skip;            
wire            ex2_expnt_of;                          
wire    [12:0]  ex2_expnt_result;                      
wire            ex2_expnt_uf;                          
wire            ex2_half_expnt_of;                     
wire            ex2_half_expnt_uf;                     
wire            ex2_half_id_nor_srt_skip;              
wire            ex2_half_potnt_of;                     
wire            ex2_half_potnt_uf;                     
wire            ex2_id_nor_srt_skip;                   
wire            ex2_of;                                
wire            ex2_of_plus;                           
wire            ex2_pipe_clk;                          
wire            ex2_pipe_clk_en;                       
wire            ex2_pipedown;                          
wire            ex2_potnt_of;                          
wire            ex2_potnt_of_pre;                      
wire            ex2_potnt_uf;                          
wire            ex2_potnt_uf_pre;                      
wire    [52:0]  ex2_result_denorm_round_add_num;       
wire            ex2_result_inf;                        
wire            ex2_result_lfn;                        
wire            ex2_result_qnan;                       
wire            ex2_result_zero;                       
wire            ex2_rslt_denorm;                       
wire            ex2_sing_expnt_of;                     
wire            ex2_sing_expnt_uf;                     
wire            ex2_sing_potnt_of;                     
wire            ex2_sing_potnt_uf;                     
wire            ex2_single_id_nor_srt_skip;            
wire    [12:0]  ex2_sqrt_expnt_result;                 
wire            ex2_srt_first_round;                   
wire            ex2_uf;                                
wire            ex2_uf_plus;                           
wire            forever_cpuclk;                        
wire    [6 :0]  initial_bound_sel_in;                  
wire    [55:0]  initial_divisor_in;                    
wire    [60:0]  initial_remainder_in;                  
wire            initial_srt_en;                        
wire            initial_srt_sel_div_in;                
wire            initial_srt_sel_sqrt_in;               
wire            pad_yy_icg_scan_en;                    
wire            srt_ctrl_rem_zero;                     
wire            srt_ctrl_skip_srt;                     
wire            srt_first_round;                       
wire    [60:0]  srt_remainder;                         
wire    [59:0]  srt_remainder_out;                     
wire            srt_remainder_sign;                    
wire            srt_secd_round;                        
wire            srt_sm_on;                             
wire    [57:0]  total_qt_rt;                           
wire    [57:0]  total_qt_rt_58;                        
wire    [57:0]  vdiv_qt_rt;                            
wire            vfdsu_ex2_div;                         
wire            vfdsu_ex2_double;                      
wire            vfdsu_ex2_dz;                          
wire    [12:0]  vfdsu_ex2_expnt_add0;                  
wire    [12:0]  vfdsu_ex2_expnt_add1;                  
wire    [12:0]  vfdsu_ex2_expnt_rst;                   
wire            vfdsu_ex2_nv;                          
wire            vfdsu_ex2_of_rm_lfn;                   
wire            vfdsu_ex2_op0_norm;                    
wire            vfdsu_ex2_op1_norm;                    
wire    [51:0]  vfdsu_ex2_qnan_f;                      
wire            vfdsu_ex2_qnan_sign;                   
wire            vfdsu_ex2_result_inf;                  
wire            vfdsu_ex2_result_qnan;                 
wire            vfdsu_ex2_result_sign;                 
wire            vfdsu_ex2_result_zero;                 
wire    [2 :0]  vfdsu_ex2_rm;                          
wire            vfdsu_ex2_single;                      
wire            vfdsu_ex2_sqrt;                        
wire            vfdsu_ex2_srt_skip;                    
wire            vfdsu_ex3_rem_zero;                    









assign vfdsu_ex2_expnt_rst[12:0] =  (vfdsu_ex2_sqrt)
                                    ? ex2_sqrt_expnt_result[12:0]
                                    : ex2_expnt_result[12:0];
assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12],
                                      ex2_expnt_result[12:1]};
assign ex2_expnt_result[12:0]  = vfdsu_ex2_expnt_add0[12:0] - vfdsu_ex2_expnt_add1[12:0];
assign ex2_doub_expnt_of = ~vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11] 
                                                        || (vfdsu_ex2_expnt_rst[10] &&
                                                            |vfdsu_ex2_expnt_rst[9:0]));
assign ex2_sing_expnt_of = ~vfdsu_ex2_expnt_rst[9] && (vfdsu_ex2_expnt_rst[8] 
                                                      || (vfdsu_ex2_expnt_rst[7]  &&
                                                          |vfdsu_ex2_expnt_rst[6:0]));

assign ex2_half_expnt_of = ~vfdsu_ex2_expnt_rst[6] && (vfdsu_ex2_expnt_rst[5] 
                                                      || (vfdsu_ex2_expnt_rst[4]  &&
                                                          |vfdsu_ex2_expnt_rst[3:0]));
assign ex2_expnt_of      = vfdsu_ex2_double ? ex2_doub_expnt_of :
                                              vfdsu_ex2_single  ? ex2_sing_expnt_of
                                                                : ex2_half_expnt_of;
assign ex2_potnt_of_pre  = vfdsu_ex2_double ? ex2_doub_potnt_of :
                           vfdsu_ex2_single ? ex2_sing_potnt_of : ex2_half_potnt_of;   
assign ex2_potnt_uf_pre  = vfdsu_ex2_double ? ex2_doub_potnt_uf : 
                           vfdsu_ex2_single ? ex2_sing_potnt_uf : ex2_half_potnt_uf;
assign ex2_expnt_uf      = vfdsu_ex2_double ? ex2_doub_expnt_uf :
                           vfdsu_ex2_single ? ex2_sing_expnt_uf : ex2_half_expnt_uf;
assign ex2_id_nor_srt_skip   = vfdsu_ex2_double ? ex2_double_id_nor_srt_skip :
                               vfdsu_ex2_single ? ex2_single_id_nor_srt_skip
                                                : ex2_half_id_nor_srt_skip; 
assign ex2_result_denorm_round_add_num[52:0] = vfdsu_ex2_double ? 
                                               ex2_result_double_denorm_round_add_num[52:0] :
                                               vfdsu_ex2_single ? 
                                               ex2_result_single_denorm_round_add_num[52:0] :
                                               ex2_result_half_denorm_round_add_num[52:0];
                                             
                                                      

assign ex2_doub_potnt_of = ~vfdsu_ex2_expnt_rst[12] && 
                           ~vfdsu_ex2_expnt_rst[11] &&
                            vfdsu_ex2_expnt_rst[10] &&
                          ~|vfdsu_ex2_expnt_rst[9:0];
assign ex2_sing_potnt_of = ~vfdsu_ex2_expnt_rst[9]  &&
                           ~vfdsu_ex2_expnt_rst[8]  &&
                            vfdsu_ex2_expnt_rst[7]  &&
                          ~|vfdsu_ex2_expnt_rst[6:0];
assign ex2_half_potnt_of = ~vfdsu_ex2_expnt_rst[6]  &&
                           ~vfdsu_ex2_expnt_rst[5]  &&
                            vfdsu_ex2_expnt_rst[4]  &&
                          ~|vfdsu_ex2_expnt_rst[3:0];  
assign ex2_potnt_of      = ex2_potnt_of_pre && 
                           vfdsu_ex2_op0_norm && 
                           vfdsu_ex2_op1_norm && 
                           vfdsu_ex2_div;


assign ex2_doub_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hc01);
assign ex2_sing_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hf81);
assign ex2_half_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hff1);
assign ex2_half_potnt_uf = &vfdsu_ex2_expnt_rst[6:4]   &&
                          ~|vfdsu_ex2_expnt_rst[3:2]   &&
                            vfdsu_ex2_expnt_rst[1]     &&
                           !vfdsu_ex2_expnt_rst[0];



assign ex2_doub_potnt_uf = &vfdsu_ex2_expnt_rst[12:10] &&
                          ~|vfdsu_ex2_expnt_rst[9:2]   &&
                            vfdsu_ex2_expnt_rst[1]     && 
                           !vfdsu_ex2_expnt_rst[0];
assign ex2_sing_potnt_uf = &vfdsu_ex2_expnt_rst[9:7]   &&
                          ~|vfdsu_ex2_expnt_rst[6:2]   &&
                            vfdsu_ex2_expnt_rst[1]     &&
                           !vfdsu_ex2_expnt_rst[0];

assign ex2_potnt_uf      = (ex2_potnt_uf_pre && 
                            vfdsu_ex2_op0_norm && 
                            vfdsu_ex2_op1_norm &&
                            vfdsu_ex2_div)     ||
                           (ex2_potnt_uf_pre   && 
                            vfdsu_ex2_op0_norm);





assign ex2_of      = ex2_of_plus;
assign ex2_of_plus = ex2_div_of  && vfdsu_ex2_div; 
assign ex2_div_of  = vfdsu_ex2_op0_norm && 
                     vfdsu_ex2_op1_norm && 
                     ex2_expnt_of;






assign ex2_uf      = ex2_uf_plus;
assign ex2_uf_plus = ex2_div_uf  && vfdsu_ex2_div; 
assign ex2_div_uf  = vfdsu_ex2_op0_norm && 
                     vfdsu_ex2_op1_norm && 
                     ex2_expnt_uf;
assign ex2_double_id_nor_srt_skip =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hbcd);
assign ex2_single_id_nor_srt_skip =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hf6a);
assign ex2_half_id_nor_srt_skip   =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hfe7);
assign ex2_rslt_denorm            = ex2_uf;


assign srt_ctrl_skip_srt   =  ex2_of || ex2_id_nor_srt_skip
                                     || vfdsu_ex2_srt_skip;


always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1c02:ex2_result_double_denorm_round_add_num[52:0] = 53'h1;
  13'h1c01:ex2_result_double_denorm_round_add_num[52:0] = 53'h2;
  13'h1c00:ex2_result_double_denorm_round_add_num[52:0] = 53'h4;
  13'h1bff:ex2_result_double_denorm_round_add_num[52:0] = 53'h8;
  13'h1bfe:ex2_result_double_denorm_round_add_num[52:0] = 53'h10;
  13'h1bfd:ex2_result_double_denorm_round_add_num[52:0] = 53'h20;
  13'h1bfc:ex2_result_double_denorm_round_add_num[52:0] = 53'h40;
  13'h1bfb:ex2_result_double_denorm_round_add_num[52:0] = 53'h80;
  13'h1bfa:ex2_result_double_denorm_round_add_num[52:0] = 53'h100;
  13'h1bf9:ex2_result_double_denorm_round_add_num[52:0] = 53'h200;
  13'h1bf8:ex2_result_double_denorm_round_add_num[52:0] = 53'h400;
  13'h1bf7:ex2_result_double_denorm_round_add_num[52:0] = 53'h800;
  13'h1bf6:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000;
  13'h1bf5:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000;
  13'h1bf4:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000;
  13'h1bf3:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000;
  13'h1bf2:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000;
  13'h1bf1:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000;
  13'h1bf0:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000;
  13'h1bef:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000;
  13'h1bee:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000;
  13'h1bed:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000;
  13'h1bec:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000;
  13'h1beb:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000;
  13'h1bea:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000;
  13'h1be9:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000;
  13'h1be8:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000;
  13'h1be7:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000;
  13'h1be6:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000;
  13'h1be5:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1be4:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1be3:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1be2:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1be1:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1be0:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1bdf:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1bde:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1bdd:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1bdc:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1bdb:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1bda:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1bd9:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1bd8:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1bd7:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1bd6:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1bd5:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1bd4:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1bd3:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1bd2:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1bd1:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1bd0:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1bcf:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1bce:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_double_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1f82:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1f81:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1f80:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1f7f:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1f7e:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1f7d:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1f7c:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1f7b:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1f7a:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1f79:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1f78:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1f77:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1f76:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1f75:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1f74:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1f73:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1f72:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1f71:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1f70:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1f6f:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1f6e:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1f6d:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1f6c:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1f6b:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_single_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1ff2:ex2_result_half_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1ff1:ex2_result_half_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1ff0:ex2_result_half_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1fef:ex2_result_half_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1fee:ex2_result_half_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1fed:ex2_result_half_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1fec:ex2_result_half_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1feb:ex2_result_half_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1fea:ex2_result_half_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1fe9:ex2_result_half_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1fe8:ex2_result_half_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_half_denorm_round_add_num[52:0] = 53'h0;
endcase

end


assign ex2_result_zero = vfdsu_ex2_result_zero;
assign ex2_result_qnan = vfdsu_ex2_result_qnan;
assign ex2_result_inf  = vfdsu_ex2_result_inf || 
                         ex2_of_plus && !vfdsu_ex2_of_rm_lfn;
assign ex2_result_lfn  =  
                         ex2_of_plus &&  vfdsu_ex2_of_rm_lfn;






gated_clk_cell  x_ex2_pipe_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ex2_pipe_clk      ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ex2_pipe_clk_en   ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








assign ex2_pipe_clk_en = ex2_pipedown;

always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    vfdsu_ex3_result_zero     <= 1'b0;
    vfdsu_ex3_result_qnan     <= 1'b0;
    vfdsu_ex3_result_inf      <= 1'b0;
    vfdsu_ex3_result_lfn      <= 1'b0;
    vfdsu_ex3_of              <= 1'b0;
    vfdsu_ex3_uf              <= 1'b0;
    vfdsu_ex3_nv              <= 1'b0;
    vfdsu_ex3_dz              <= 1'b0;
    vfdsu_ex3_potnt_of        <= 1'b0;
    vfdsu_ex3_potnt_uf        <= 1'b0;
    vfdsu_ex3_rem_sign        <= 1'b0;

    vfdsu_ex3_doub_expnt_rst[12:0] <= 13'b0;
    vfdsu_ex3_sing_expnt_rst[8:0] <= 9'b0;
    vfdsu_ex3_half_expnt_rst[12:0] <= 13'b0;
    vfdsu_ex3_result_sign     <= 1'b0;
    vfdsu_ex3_qnan_sign       <= 1'b0;    
    vfdsu_ex3_qnan_f[51:0]    <= 52'b0;
    vfdsu_ex3_rm[2:0]         <= 3'b0;
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= 53'b0;
    vfdsu_ex3_rslt_denorm     <= 1'b0;
    vfdsu_ex3_id_srt_skip     <= 1'b0;
    vfdsu_ex3_double          <=  1'b0;
    vfdsu_ex3_single          <=  1'b0;
  end
  else if(ex2_pipedown)
  begin
    vfdsu_ex3_result_zero     <= ex2_result_zero; 
    vfdsu_ex3_result_qnan     <= ex2_result_qnan;
    vfdsu_ex3_result_inf      <= ex2_result_inf;
    vfdsu_ex3_result_lfn      <= ex2_result_lfn; 
    vfdsu_ex3_of              <= ex2_of;
    vfdsu_ex3_uf              <= ex2_uf;
    vfdsu_ex3_nv              <= vfdsu_ex2_nv;
    vfdsu_ex3_dz              <= vfdsu_ex2_dz;
    vfdsu_ex3_potnt_of        <= ex2_potnt_of;
    vfdsu_ex3_potnt_uf        <= ex2_potnt_uf;
    vfdsu_ex3_rem_sign        <= srt_remainder_sign;

    vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
    vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex2_expnt_rst[8:0];
    vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
    vfdsu_ex3_result_sign     <= vfdsu_ex2_result_sign;
    vfdsu_ex3_qnan_sign       <= vfdsu_ex2_qnan_sign;    
    vfdsu_ex3_qnan_f[51:0]    <= vfdsu_ex2_qnan_f[51:0];
    vfdsu_ex3_rm[2:0]         <= vfdsu_ex2_rm[2:0];
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= ex2_result_denorm_round_add_num[52:0];
    vfdsu_ex3_rslt_denorm     <= ex2_rslt_denorm;
    vfdsu_ex3_id_srt_skip     <= ex2_id_nor_srt_skip;
    vfdsu_ex3_double          <= vfdsu_ex2_double;
    vfdsu_ex3_single          <= vfdsu_ex2_single;
  end
  else
  begin
    vfdsu_ex3_result_zero     <= vfdsu_ex3_result_zero; 
    vfdsu_ex3_result_qnan     <= vfdsu_ex3_result_qnan;
    vfdsu_ex3_result_inf      <= vfdsu_ex3_result_inf;
    vfdsu_ex3_result_lfn      <= vfdsu_ex3_result_lfn;
    vfdsu_ex3_of              <= vfdsu_ex3_of;
    vfdsu_ex3_uf              <= vfdsu_ex3_uf;
    vfdsu_ex3_nv              <= vfdsu_ex3_nv;
    vfdsu_ex3_dz              <= vfdsu_ex3_dz;
    vfdsu_ex3_potnt_of        <= vfdsu_ex3_potnt_of;
    vfdsu_ex3_potnt_uf        <= vfdsu_ex3_potnt_uf;
    vfdsu_ex3_rem_sign        <= vfdsu_ex3_rem_sign;

    vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex3_doub_expnt_rst[12:0];
    vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex3_sing_expnt_rst[8:0];
    vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex3_half_expnt_rst[12:0];
    vfdsu_ex3_result_sign     <= vfdsu_ex3_result_sign;
    vfdsu_ex3_qnan_sign       <= vfdsu_ex3_qnan_sign;     
    vfdsu_ex3_qnan_f[51:0]    <= vfdsu_ex3_qnan_f[51:0];
    vfdsu_ex3_rm[2:0]         <= vfdsu_ex3_rm[2:0];
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= vfdsu_ex3_result_denorm_round_add_num[52:0];
    vfdsu_ex3_rslt_denorm     <=  vfdsu_ex3_rslt_denorm;
    vfdsu_ex3_id_srt_skip    <=  vfdsu_ex3_id_srt_skip;
    vfdsu_ex3_double          <= vfdsu_ex3_double;
    vfdsu_ex3_single          <= vfdsu_ex3_single;
  end
end
assign vfdsu_ex3_rem_zero       =  ~|srt_remainder[60:0];
assign srt_ctrl_rem_zero        =  vfdsu_ex3_rem_zero;


































assign initial_divisor_in[55:0]   = {ex1_divisor[52:0],3'b000}; 

assign initial_remainder_in[60:0] = {2'b00,ex1_remainder[59:1]};

assign initial_bound_sel_in[6:0]  = ex1_div ? initial_divisor_in[55:49]:{7{1'b0}};

assign initial_srt_en             = ex1_pipedown;
assign initial_srt_sel_div_in     = ex1_div;
assign initial_srt_sel_sqrt_in    = ex1_sqrt;

assign srt_first_round            = ex2_srt_first_round;


ct_vfdsu_srt_radix16_with_sqrt  x_ct_vfdsu_srt_radix16_with_sqrt (
  .cp0_vfpu_icg_en         (cp0_vfpu_icg_en        ),
  .cp0_yy_clk_en           (cp0_yy_clk_en          ),
  .cpurst_b                (cpurst_b               ),
  .forever_cpuclk          (forever_cpuclk         ),
  .initial_bound_sel_in    (initial_bound_sel_in   ),
  .initial_divisor_in      (initial_divisor_in     ),
  .initial_remainder_in    (initial_remainder_in   ),
  .initial_srt_en          (initial_srt_en         ),
  .initial_srt_sel_div_in  (initial_srt_sel_div_in ),
  .initial_srt_sel_sqrt_in (initial_srt_sel_sqrt_in),
  .pad_yy_icg_scan_en      (pad_yy_icg_scan_en     ),
  .srt_first_round         (srt_first_round        ),
  .srt_remainder           (srt_remainder          ),
  .srt_remainder_out       (srt_remainder_out      ),
  .srt_remainder_sign      (srt_remainder_sign     ),
  .srt_secd_round          (srt_secd_round         ),
  .srt_sm_on               (srt_sm_on              ),
  .total_qt_rt             (total_qt_rt            ),
  .vdiv_qt_rt              (vdiv_qt_rt             )
);




assign total_qt_rt_58[57:0] = {total_qt_rt[57:2],2'b00};


endmodule
module ct_vfdsu_srt(
  cp0_vfpu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  ex1_div,
  ex1_divisor,
  ex1_pipedown,
  ex1_remainder,
  ex1_sqrt,
  ex2_pipedown,
  ex2_srt_first_round,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  srt_ctrl_rem_zero,
  srt_ctrl_skip_srt,
  srt_secd_round,
  srt_sm_on,
  total_qt_rt_58,
  vfdsu_ex2_div,
  vfdsu_ex2_double,
  vfdsu_ex2_dz,
  vfdsu_ex2_expnt_add0,
  vfdsu_ex2_expnt_add1,
  vfdsu_ex2_nv,
  vfdsu_ex2_of_rm_lfn,
  vfdsu_ex2_op0_norm,
  vfdsu_ex2_op1_norm,
  vfdsu_ex2_qnan_f,
  vfdsu_ex2_qnan_sign,
  vfdsu_ex2_result_inf,
  vfdsu_ex2_result_qnan,
  vfdsu_ex2_result_sign,
  vfdsu_ex2_result_zero,
  vfdsu_ex2_rm,
  vfdsu_ex2_single,
  vfdsu_ex2_sqrt,
  vfdsu_ex2_srt_skip,
  vfdsu_ex3_doub_expnt_rst,
  vfdsu_ex3_double,
  vfdsu_ex3_dz,
  vfdsu_ex3_half_expnt_rst,
  vfdsu_ex3_id_srt_skip,
  vfdsu_ex3_nv,
  vfdsu_ex3_of,
  vfdsu_ex3_potnt_of,
  vfdsu_ex3_potnt_uf,
  vfdsu_ex3_qnan_f,
  vfdsu_ex3_qnan_sign,
  vfdsu_ex3_rem_sign,
  vfdsu_ex3_rem_zero,
  vfdsu_ex3_result_denorm_round_add_num,
  vfdsu_ex3_result_inf,
  vfdsu_ex3_result_lfn,
  vfdsu_ex3_result_qnan,
  vfdsu_ex3_result_sign,
  vfdsu_ex3_result_zero,
  vfdsu_ex3_rm,
  vfdsu_ex3_rslt_denorm,
  vfdsu_ex3_sing_expnt_rst,
  vfdsu_ex3_single,
  vfdsu_ex3_uf
);



input           cp0_vfpu_icg_en;                       
input           cp0_yy_clk_en;                         
input           cpurst_b;                              
input           ex1_div;                               
input   [52:0]  ex1_divisor;                           
input           ex1_pipedown;                          
input   [59:0]  ex1_remainder;                         
input           ex1_sqrt;                              
input           ex2_pipedown;                          
input           ex2_srt_first_round;                   
input           forever_cpuclk;                        
input           pad_yy_icg_scan_en;                    
input           srt_secd_round;                        
input           srt_sm_on;                             
input           vfdsu_ex2_div;                         
input           vfdsu_ex2_double;                      
input           vfdsu_ex2_dz;                          
input   [12:0]  vfdsu_ex2_expnt_add0;                  
input   [12:0]  vfdsu_ex2_expnt_add1;                  
input           vfdsu_ex2_nv;                          
input           vfdsu_ex2_of_rm_lfn;                   
input           vfdsu_ex2_op0_norm;                    
input           vfdsu_ex2_op1_norm;                    
input   [51:0]  vfdsu_ex2_qnan_f;                      
input           vfdsu_ex2_qnan_sign;                   
input           vfdsu_ex2_result_inf;                  
input           vfdsu_ex2_result_qnan;                 
input           vfdsu_ex2_result_sign;                 
input           vfdsu_ex2_result_zero;                 
input   [2 :0]  vfdsu_ex2_rm;                          
input           vfdsu_ex2_single;                      
input           vfdsu_ex2_sqrt;                        
input           vfdsu_ex2_srt_skip;                    
output          srt_ctrl_rem_zero;                     
output          srt_ctrl_skip_srt;                     
output  [57:0]  total_qt_rt_58;                        
output  [12:0]  vfdsu_ex3_doub_expnt_rst;              
output          vfdsu_ex3_double;                      
output          vfdsu_ex3_dz;                          
output  [12:0]  vfdsu_ex3_half_expnt_rst;              
output          vfdsu_ex3_id_srt_skip;                 
output          vfdsu_ex3_nv;                          
output          vfdsu_ex3_of;                          
output          vfdsu_ex3_potnt_of;                    
output          vfdsu_ex3_potnt_uf;                    
output  [51:0]  vfdsu_ex3_qnan_f;                      
output          vfdsu_ex3_qnan_sign;                   
output          vfdsu_ex3_rem_sign;                    
output          vfdsu_ex3_rem_zero;                    
output  [52:0]  vfdsu_ex3_result_denorm_round_add_num; 
output          vfdsu_ex3_result_inf;                  
output          vfdsu_ex3_result_lfn;                  
output          vfdsu_ex3_result_qnan;                 
output          vfdsu_ex3_result_sign;                 
output          vfdsu_ex3_result_zero;                 
output  [2 :0]  vfdsu_ex3_rm;                          
output          vfdsu_ex3_rslt_denorm;                 
output  [8 :0]  vfdsu_ex3_sing_expnt_rst;              
output          vfdsu_ex3_single;                      
output          vfdsu_ex3_uf;                          


reg     [52:0]  ex2_result_double_denorm_round_add_num; 
reg     [52:0]  ex2_result_half_denorm_round_add_num;  
reg     [52:0]  ex2_result_single_denorm_round_add_num; 
reg     [12:0]  vfdsu_ex3_doub_expnt_rst;              
reg             vfdsu_ex3_double;                      
reg             vfdsu_ex3_dz;                          
reg     [12:0]  vfdsu_ex3_half_expnt_rst;              
reg             vfdsu_ex3_id_srt_skip;                 
reg             vfdsu_ex3_nv;                          
reg             vfdsu_ex3_of;                          
reg             vfdsu_ex3_potnt_of;                    
reg             vfdsu_ex3_potnt_uf;                    
reg     [51:0]  vfdsu_ex3_qnan_f;                      
reg             vfdsu_ex3_qnan_sign;                   
reg             vfdsu_ex3_rem_sign;                    
reg     [52:0]  vfdsu_ex3_result_denorm_round_add_num; 
reg             vfdsu_ex3_result_inf;                  
reg             vfdsu_ex3_result_lfn;                  
reg             vfdsu_ex3_result_qnan;                 
reg             vfdsu_ex3_result_sign;                 
reg             vfdsu_ex3_result_zero;                 
reg     [2 :0]  vfdsu_ex3_rm;                          
reg             vfdsu_ex3_rslt_denorm;                 
reg     [8 :0]  vfdsu_ex3_sing_expnt_rst;              
reg             vfdsu_ex3_single;                      
reg             vfdsu_ex3_uf;                          


wire            cp0_vfpu_icg_en;                       
wire            cp0_yy_clk_en;                         
wire            cpurst_b;                              
wire            ex1_div;                               
wire    [52:0]  ex1_divisor;                           
wire            ex1_pipedown;                          
wire    [59:0]  ex1_remainder;                         
wire            ex1_sqrt;                              
wire            ex2_div_of;                            
wire            ex2_div_uf;                            
wire            ex2_doub_expnt_of;                     
wire            ex2_doub_expnt_uf;                     
wire            ex2_doub_potnt_of;                     
wire            ex2_doub_potnt_uf;                     
wire            ex2_double_id_nor_srt_skip;            
wire            ex2_expnt_of;                          
wire    [12:0]  ex2_expnt_result;                      
wire            ex2_expnt_uf;                          
wire            ex2_half_expnt_of;                     
wire            ex2_half_expnt_uf;                     
wire            ex2_half_id_nor_srt_skip;              
wire            ex2_half_potnt_of;                     
wire            ex2_half_potnt_uf;                     
wire            ex2_id_nor_srt_skip;                   
wire            ex2_of;                                
wire            ex2_of_plus;                           
wire            ex2_pipe_clk;                          
wire            ex2_pipe_clk_en;                       
wire            ex2_pipedown;                          
wire            ex2_potnt_of;                          
wire            ex2_potnt_of_pre;                      
wire            ex2_potnt_uf;                          
wire            ex2_potnt_uf_pre;                      
wire    [52:0]  ex2_result_denorm_round_add_num;       
wire            ex2_result_inf;                        
wire            ex2_result_lfn;                        
wire            ex2_result_qnan;                       
wire            ex2_result_zero;                       
wire            ex2_rslt_denorm;                       
wire            ex2_sing_expnt_of;                     
wire            ex2_sing_expnt_uf;                     
wire            ex2_sing_potnt_of;                     
wire            ex2_sing_potnt_uf;                     
wire            ex2_single_id_nor_srt_skip;            
wire    [12:0]  ex2_sqrt_expnt_result;                 
wire            ex2_srt_first_round;                   
wire            ex2_uf;                                
wire            ex2_uf_plus;                           
wire            forever_cpuclk;                        
wire    [6 :0]  initial_bound_sel_in;                  
wire    [55:0]  initial_divisor_in;                    
wire    [60:0]  initial_remainder_in;                  
wire            initial_srt_en;                        
wire            initial_srt_sel_div_in;                
wire            initial_srt_sel_sqrt_in;               
wire            pad_yy_icg_scan_en;                    
wire            srt_ctrl_rem_zero;                     
wire            srt_ctrl_skip_srt;                     
wire            srt_first_round;                       
wire    [60:0]  srt_remainder;                         
wire    [59:0]  srt_remainder_out;                     
wire            srt_remainder_sign;                    
wire            srt_secd_round;                        
wire            srt_sm_on;                             
wire    [57:0]  total_qt_rt;                           
wire    [57:0]  total_qt_rt_58;                        
wire    [57:0]  vdiv_qt_rt;                            
wire            vfdsu_ex2_div;                         
wire            vfdsu_ex2_double;                      
wire            vfdsu_ex2_dz;                          
wire    [12:0]  vfdsu_ex2_expnt_add0;                  
wire    [12:0]  vfdsu_ex2_expnt_add1;                  
wire    [12:0]  vfdsu_ex2_expnt_rst;                   
wire            vfdsu_ex2_nv;                          
wire            vfdsu_ex2_of_rm_lfn;                   
wire            vfdsu_ex2_op0_norm;                    
wire            vfdsu_ex2_op1_norm;                    
wire    [51:0]  vfdsu_ex2_qnan_f;                      
wire            vfdsu_ex2_qnan_sign;                   
wire            vfdsu_ex2_result_inf;                  
wire            vfdsu_ex2_result_qnan;                 
wire            vfdsu_ex2_result_sign;                 
wire            vfdsu_ex2_result_zero;                 
wire    [2 :0]  vfdsu_ex2_rm;                          
wire            vfdsu_ex2_single;                      
wire            vfdsu_ex2_sqrt;                        
wire            vfdsu_ex2_srt_skip;                    
wire            vfdsu_ex3_rem_zero;                    









assign vfdsu_ex2_expnt_rst[12:0] =  (vfdsu_ex2_sqrt)
                                    ? ex2_sqrt_expnt_result[12:0]
                                    : ex2_expnt_result[12:0];
assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12],
                                      ex2_expnt_result[12:1]};
assign ex2_expnt_result[12:0]  = vfdsu_ex2_expnt_add0[12:0] - vfdsu_ex2_expnt_add1[12:0];
assign ex2_doub_expnt_of = ~vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11] 
                                                        || (vfdsu_ex2_expnt_rst[10] &&
                                                            |vfdsu_ex2_expnt_rst[9:0]));
assign ex2_sing_expnt_of = ~vfdsu_ex2_expnt_rst[9] && (vfdsu_ex2_expnt_rst[8] 
                                                      || (vfdsu_ex2_expnt_rst[7]  &&
                                                          |vfdsu_ex2_expnt_rst[6:0]));

assign ex2_half_expnt_of = ~vfdsu_ex2_expnt_rst[6] && (vfdsu_ex2_expnt_rst[5] 
                                                      || (vfdsu_ex2_expnt_rst[4]  &&
                                                          |vfdsu_ex2_expnt_rst[3:0]));
assign ex2_expnt_of      = vfdsu_ex2_double ? ex2_doub_expnt_of :
                                              vfdsu_ex2_single  ? ex2_sing_expnt_of
                                                                : ex2_half_expnt_of;
assign ex2_potnt_of_pre  = vfdsu_ex2_double ? ex2_doub_potnt_of :
                           vfdsu_ex2_single ? ex2_sing_potnt_of : ex2_half_potnt_of;   
assign ex2_potnt_uf_pre  = vfdsu_ex2_double ? ex2_doub_potnt_uf : 
                           vfdsu_ex2_single ? ex2_sing_potnt_uf : ex2_half_potnt_uf;
assign ex2_expnt_uf      = vfdsu_ex2_double ? ex2_doub_expnt_uf :
                           vfdsu_ex2_single ? ex2_sing_expnt_uf : ex2_half_expnt_uf;
assign ex2_id_nor_srt_skip   = vfdsu_ex2_double ? ex2_double_id_nor_srt_skip :
                               vfdsu_ex2_single ? ex2_single_id_nor_srt_skip
                                                : ex2_half_id_nor_srt_skip; 
assign ex2_result_denorm_round_add_num[52:0] = vfdsu_ex2_double ? 
                                               ex2_result_double_denorm_round_add_num[52:0] :
                                               vfdsu_ex2_single ? 
                                               ex2_result_single_denorm_round_add_num[52:0] :
                                               ex2_result_half_denorm_round_add_num[52:0];
                                             
                                                      

assign ex2_doub_potnt_of = ~vfdsu_ex2_expnt_rst[12] && 
                           ~vfdsu_ex2_expnt_rst[11] &&
                            vfdsu_ex2_expnt_rst[10] &&
                          ~|vfdsu_ex2_expnt_rst[9:0];
assign ex2_sing_potnt_of = ~vfdsu_ex2_expnt_rst[9]  &&
                           ~vfdsu_ex2_expnt_rst[8]  &&
                            vfdsu_ex2_expnt_rst[7]  &&
                          ~|vfdsu_ex2_expnt_rst[6:0];
assign ex2_half_potnt_of = ~vfdsu_ex2_expnt_rst[6]  &&
                           ~vfdsu_ex2_expnt_rst[5]  &&
                            vfdsu_ex2_expnt_rst[4]  &&
                          ~|vfdsu_ex2_expnt_rst[3:0];  
assign ex2_potnt_of      = ex2_potnt_of_pre && 
                           vfdsu_ex2_op0_norm && 
                           vfdsu_ex2_op1_norm && 
                           vfdsu_ex2_div;


assign ex2_doub_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hc01);
assign ex2_sing_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hf81);
assign ex2_half_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hff1);
assign ex2_half_potnt_uf = &vfdsu_ex2_expnt_rst[6:4]   &&
                          ~|vfdsu_ex2_expnt_rst[3:2]   &&
                            vfdsu_ex2_expnt_rst[1]     &&
                           !vfdsu_ex2_expnt_rst[0];



assign ex2_doub_potnt_uf = &vfdsu_ex2_expnt_rst[12:10] &&
                          ~|vfdsu_ex2_expnt_rst[9:2]   &&
                            vfdsu_ex2_expnt_rst[1]     && 
                           !vfdsu_ex2_expnt_rst[0];
assign ex2_sing_potnt_uf = &vfdsu_ex2_expnt_rst[9:7]   &&
                          ~|vfdsu_ex2_expnt_rst[6:2]   &&
                            vfdsu_ex2_expnt_rst[1]     &&
                           !vfdsu_ex2_expnt_rst[0];

assign ex2_potnt_uf      = (ex2_potnt_uf_pre && 
                            vfdsu_ex2_op0_norm && 
                            vfdsu_ex2_op1_norm &&
                            vfdsu_ex2_div)     ||
                           (ex2_potnt_uf_pre   && 
                            vfdsu_ex2_op0_norm);





assign ex2_of      = ex2_of_plus;
assign ex2_of_plus = ex2_div_of  && vfdsu_ex2_div; 
assign ex2_div_of  = vfdsu_ex2_op0_norm && 
                     vfdsu_ex2_op1_norm && 
                     ex2_expnt_of;






assign ex2_uf      = ex2_uf_plus;
assign ex2_uf_plus = ex2_div_uf  && vfdsu_ex2_div; 
assign ex2_div_uf  = vfdsu_ex2_op0_norm && 
                     vfdsu_ex2_op1_norm && 
                     ex2_expnt_uf;
assign ex2_double_id_nor_srt_skip =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hbcd);
assign ex2_single_id_nor_srt_skip =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hf6a);
assign ex2_half_id_nor_srt_skip   =  vfdsu_ex2_expnt_rst[12] 
                                     && (vfdsu_ex2_expnt_rst[11:0]<12'hfe7);
assign ex2_rslt_denorm            = ex2_uf;


assign srt_ctrl_skip_srt   =  ex2_of || ex2_id_nor_srt_skip
                                     || vfdsu_ex2_srt_skip;


always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1c02:ex2_result_double_denorm_round_add_num[52:0] = 53'h1;
  13'h1c01:ex2_result_double_denorm_round_add_num[52:0] = 53'h2;
  13'h1c00:ex2_result_double_denorm_round_add_num[52:0] = 53'h4;
  13'h1bff:ex2_result_double_denorm_round_add_num[52:0] = 53'h8;
  13'h1bfe:ex2_result_double_denorm_round_add_num[52:0] = 53'h10;
  13'h1bfd:ex2_result_double_denorm_round_add_num[52:0] = 53'h20;
  13'h1bfc:ex2_result_double_denorm_round_add_num[52:0] = 53'h40;
  13'h1bfb:ex2_result_double_denorm_round_add_num[52:0] = 53'h80;
  13'h1bfa:ex2_result_double_denorm_round_add_num[52:0] = 53'h100;
  13'h1bf9:ex2_result_double_denorm_round_add_num[52:0] = 53'h200;
  13'h1bf8:ex2_result_double_denorm_round_add_num[52:0] = 53'h400;
  13'h1bf7:ex2_result_double_denorm_round_add_num[52:0] = 53'h800;
  13'h1bf6:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000;
  13'h1bf5:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000;
  13'h1bf4:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000;
  13'h1bf3:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000;
  13'h1bf2:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000;
  13'h1bf1:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000;
  13'h1bf0:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000;
  13'h1bef:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000;
  13'h1bee:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000;
  13'h1bed:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000;
  13'h1bec:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000;
  13'h1beb:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000;
  13'h1bea:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000;
  13'h1be9:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000;
  13'h1be8:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000;
  13'h1be7:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000;
  13'h1be6:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000;
  13'h1be5:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1be4:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1be3:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1be2:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1be1:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1be0:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1bdf:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1bde:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1bdd:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1bdc:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1bdb:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1bda:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1bd9:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1bd8:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1bd7:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1bd6:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1bd5:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1bd4:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1bd3:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1bd2:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1bd1:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1bd0:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1bcf:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1bce:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_double_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1f82:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000;
  13'h1f81:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000;
  13'h1f80:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000;
  13'h1f7f:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000;
  13'h1f7e:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000;
  13'h1f7d:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000;
  13'h1f7c:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000;
  13'h1f7b:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000;
  13'h1f7a:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000;
  13'h1f79:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000;
  13'h1f78:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000;
  13'h1f77:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000;
  13'h1f76:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000000;
  13'h1f75:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1f74:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1f73:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1f72:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1f71:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1f70:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1f6f:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1f6e:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1f6d:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1f6c:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1f6b:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_single_denorm_round_add_num[52:0] = 53'h0;
endcase

end

always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
  13'h1ff2:ex2_result_half_denorm_round_add_num[52:0] = 53'h40000000000;
  13'h1ff1:ex2_result_half_denorm_round_add_num[52:0] = 53'h80000000000;
  13'h1ff0:ex2_result_half_denorm_round_add_num[52:0] = 53'h100000000000;
  13'h1fef:ex2_result_half_denorm_round_add_num[52:0] = 53'h200000000000;
  13'h1fee:ex2_result_half_denorm_round_add_num[52:0] = 53'h400000000000;
  13'h1fed:ex2_result_half_denorm_round_add_num[52:0] = 53'h800000000000;
  13'h1fec:ex2_result_half_denorm_round_add_num[52:0] = 53'h1000000000000;
  13'h1feb:ex2_result_half_denorm_round_add_num[52:0] = 53'h2000000000000;
  13'h1fea:ex2_result_half_denorm_round_add_num[52:0] = 53'h4000000000000;
  13'h1fe9:ex2_result_half_denorm_round_add_num[52:0] = 53'h8000000000000;
  13'h1fe8:ex2_result_half_denorm_round_add_num[52:0] = 53'h10000000000000;
  default: ex2_result_half_denorm_round_add_num[52:0] = 53'h0;
endcase

end


assign ex2_result_zero = vfdsu_ex2_result_zero;
assign ex2_result_qnan = vfdsu_ex2_result_qnan;
assign ex2_result_inf  = vfdsu_ex2_result_inf || 
                         ex2_of_plus && !vfdsu_ex2_of_rm_lfn;
assign ex2_result_lfn  =  
                         ex2_of_plus &&  vfdsu_ex2_of_rm_lfn;






gated_clk_cell  x_ex2_pipe_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ex2_pipe_clk      ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ex2_pipe_clk_en   ),
  .module_en          (cp0_vfpu_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








assign ex2_pipe_clk_en = ex2_pipedown;

always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    vfdsu_ex3_result_zero     <= 1'b0;
    vfdsu_ex3_result_qnan     <= 1'b0;
    vfdsu_ex3_result_inf      <= 1'b0;
    vfdsu_ex3_result_lfn      <= 1'b0;
    vfdsu_ex3_of              <= 1'b0;
    vfdsu_ex3_uf              <= 1'b0;
    vfdsu_ex3_nv              <= 1'b0;
    vfdsu_ex3_dz              <= 1'b0;
    vfdsu_ex3_potnt_of        <= 1'b0;
    vfdsu_ex3_potnt_uf        <= 1'b0;
    vfdsu_ex3_rem_sign        <= 1'b0;

    vfdsu_ex3_doub_expnt_rst[12:0] <= 13'b0;
    vfdsu_ex3_sing_expnt_rst[8:0] <= 9'b0;
    vfdsu_ex3_half_expnt_rst[12:0] <= 13'b0;
    vfdsu_ex3_result_sign     <= 1'b0;
    vfdsu_ex3_qnan_sign       <= 1'b0;    
    vfdsu_ex3_qnan_f[51:0]    <= 52'b0;
    vfdsu_ex3_rm[2:0]         <= 3'b0;
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= 53'b0;
    vfdsu_ex3_rslt_denorm     <= 1'b0;
    vfdsu_ex3_id_srt_skip     <= 1'b0;
    vfdsu_ex3_double          <=  1'b0;
    vfdsu_ex3_single          <=  1'b0;
  end
  else if(ex2_pipedown)
  begin
    vfdsu_ex3_result_zero     <= ex2_result_zero; 
    vfdsu_ex3_result_qnan     <= ex2_result_qnan;
    vfdsu_ex3_result_inf      <= ex2_result_inf;
    vfdsu_ex3_result_lfn      <= ex2_result_lfn; 
    vfdsu_ex3_of              <= ex2_of;
    vfdsu_ex3_uf              <= ex2_uf;
    vfdsu_ex3_nv              <= vfdsu_ex2_nv;
    vfdsu_ex3_dz              <= vfdsu_ex2_dz;
    vfdsu_ex3_potnt_of        <= ex2_potnt_of;
    vfdsu_ex3_potnt_uf        <= ex2_potnt_uf;
    vfdsu_ex3_rem_sign        <= srt_remainder_sign;

    vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
    vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex2_expnt_rst[8:0];
    vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
    vfdsu_ex3_result_sign     <= vfdsu_ex2_result_sign;
    vfdsu_ex3_qnan_sign       <= vfdsu_ex2_qnan_sign;    
    vfdsu_ex3_qnan_f[51:0]    <= vfdsu_ex2_qnan_f[51:0];
    vfdsu_ex3_rm[2:0]         <= vfdsu_ex2_rm[2:0];
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= ex2_result_denorm_round_add_num[52:0];
    vfdsu_ex3_rslt_denorm     <= ex2_rslt_denorm;
    vfdsu_ex3_id_srt_skip     <= ex2_id_nor_srt_skip;
    vfdsu_ex3_double          <= vfdsu_ex2_double;
    vfdsu_ex3_single          <= vfdsu_ex2_single;
  end
  else
  begin
    vfdsu_ex3_result_zero     <= vfdsu_ex3_result_zero; 
    vfdsu_ex3_result_qnan     <= vfdsu_ex3_result_qnan;
    vfdsu_ex3_result_inf      <= vfdsu_ex3_result_inf;
    vfdsu_ex3_result_lfn      <= vfdsu_ex3_result_lfn;
    vfdsu_ex3_of              <= vfdsu_ex3_of;
    vfdsu_ex3_uf              <= vfdsu_ex3_uf;
    vfdsu_ex3_nv              <= vfdsu_ex3_nv;
    vfdsu_ex3_dz              <= vfdsu_ex3_dz;
    vfdsu_ex3_potnt_of        <= vfdsu_ex3_potnt_of;
    vfdsu_ex3_potnt_uf        <= vfdsu_ex3_potnt_uf;
    vfdsu_ex3_rem_sign        <= vfdsu_ex3_rem_sign;

    vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex3_doub_expnt_rst[12:0];
    vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex3_sing_expnt_rst[8:0];
    vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex3_half_expnt_rst[12:0];
    vfdsu_ex3_result_sign     <= vfdsu_ex3_result_sign;
    vfdsu_ex3_qnan_sign       <= vfdsu_ex3_qnan_sign;     
    vfdsu_ex3_qnan_f[51:0]    <= vfdsu_ex3_qnan_f[51:0];
    vfdsu_ex3_rm[2:0]         <= vfdsu_ex3_rm[2:0];
    vfdsu_ex3_result_denorm_round_add_num[52:0] 
                              <= vfdsu_ex3_result_denorm_round_add_num[52:0];
    vfdsu_ex3_rslt_denorm     <=  vfdsu_ex3_rslt_denorm;
    vfdsu_ex3_id_srt_skip    <=  vfdsu_ex3_id_srt_skip;
    vfdsu_ex3_double          <= vfdsu_ex3_double;
    vfdsu_ex3_single          <= vfdsu_ex3_single;
  end
end
assign vfdsu_ex3_rem_zero       =  ~|srt_remainder[60:0];
assign srt_ctrl_rem_zero        =  vfdsu_ex3_rem_zero;


































assign initial_divisor_in[55:0]   = {ex1_divisor[52:0],3'b000}; 

assign initial_remainder_in[60:0] = {2'b00,ex1_remainder[59:1]};

assign initial_bound_sel_in[6:0]  = ex1_div ? initial_divisor_in[55:49]:{7{1'b0}};

assign initial_srt_en             = ex1_pipedown;
assign initial_srt_sel_div_in     = ex1_div;
assign initial_srt_sel_sqrt_in    = ex1_sqrt;

assign srt_first_round            = ex2_srt_first_round;


ct_vfdsu_srt_radix16_with_sqrt  x_ct_vfdsu_srt_radix16_with_sqrt (
  .cp0_vfpu_icg_en         (cp0_vfpu_icg_en        ),
  .cp0_yy_clk_en           (cp0_yy_clk_en          ),
  .cpurst_b                (cpurst_b               ),
  .forever_cpuclk          (forever_cpuclk         ),
  .initial_bound_sel_in    (initial_bound_sel_in   ),
  .initial_divisor_in      (initial_divisor_in     ),
  .initial_remainder_in    (initial_remainder_in   ),
  .initial_srt_en          (initial_srt_en         ),
  .initial_srt_sel_div_in  (initial_srt_sel_div_in ),
  .initial_srt_sel_sqrt_in (initial_srt_sel_sqrt_in),
  .pad_yy_icg_scan_en      (pad_yy_icg_scan_en     ),
  .srt_first_round         (srt_first_round        ),
  .srt_remainder           (srt_remainder          ),
  .srt_remainder_out       (srt_remainder_out      ),
  .srt_remainder_sign      (srt_remainder_sign     ),
  .srt_secd_round          (srt_secd_round         ),
  .srt_sm_on               (srt_sm_on              ),
  .total_qt_rt             (total_qt_rt            ),
  .vdiv_qt_rt              (vdiv_qt_rt             )
);




assign total_qt_rt_58[57:0] = {total_qt_rt[57:2],2'b00};


endmodule