data/full_repos/permissive/517777997/verilog/rtl/simple_por.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/517777997/verilog/rtl/simple_por.v:48: Unsupported: Ignoring delay on this delayed statement.\n #500 inode <= 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_por(
`ifdef USE_POWER_PINS
    inout VDD,
    inout VSS,
`endif
    output porb,
    output por
);

    reg inode;





    initial begin
	inode <= 1'b0; 
    end 










    initial begin
	#500 inode <= 1'b1;
    end





    assign porb = inode;



    assign por = ~porb;
endmodule
module simple_por(
`ifdef USE_POWER_PINS
    inout VDD,
    inout VSS,
`endif
    output porb,
    output por
);


    reg inode;





    initial begin
	inode <= 1'b0; 
    end 










    initial begin
	#500 inode <= 1'b1;
    end





    assign porb = inode;



    assign por = ~porb;
endmodule