data/full_repos/permissive/488093047/Verilog Codes/Decoder2x1.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/Decoder2x1.v\n%Error: Exiting due to 3 error(s)\n'
module Decoder2x1(S,EN,Y0,Y1);
input S,EN;
output Y0,Y1;
wire Sbar;
not DUT1(Sbar,S);
and DUT2(Y0,EN,Sbar);
and DUT3(Y1,EN,S);
endmodule
module Decoder2x1(S,EN,Y0,Y1);

input S,EN;
output Y0,Y1;
wire Sbar;
not DUT1(Sbar,S);
and DUT2(Y0,EN,Sbar);
and DUT3(Y1,EN,S);
endmodule