data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Q5a_ Serial two's complementer(Moores FSM).v
1: b"%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Q5a_\n%Error: Cannot find file containing module: Serial\n%Error: Cannot find file containing module: two's\n%Error: Cannot find file containing module: complementer(Moores\n%Error: Cannot find file containing module: FSM).v\n%Error: Exiting due to 9 error(s)\n"
module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
parameter a=0,b=1;
    reg state, next;
    always @(*) begin
        case(state)
            0: next = x?b:a;
            1: next = x?b:b;
        endcase
    end
    
    always @(posedge clk or posedge areset)begin
        if(areset) state<=a;
        else state <= next;
    end
    
    always @(posedge clk or posedge areset) begin
        if(areset) z=0;
        else begin
        	if(state==a)
            	 z=x;
        	else  z=~x;
        end
    end
        
endmodule
module top_module (
    input clk,
    input areset,
    input x,
    output z
);
 
parameter a=0,b=1;
    reg state, next;
    always @(*) begin
        case(state)
            0: next = x?b:a;
            1: next = x?b:b;
        endcase
    end
    
    always @(posedge clk or posedge areset)begin
        if(areset) state<=a;
        else state <= next;
    end
    
    always @(posedge clk or posedge areset) begin
        if(areset) z=0;
        else begin
        	if(state==a)
            	 z=x;
        	else  z=~x;
        end
    end
        
endmodule