data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/convclk_grayffwr.v
data/verilator_xmls/05371cc7-345a-4900-972f-e4b366532af5.xml
module convclk_grayffwr
    (
     wrclk,
     wrrst,

     fifowr,
     fifoflush,
     fifofull,
     half_full,
     wrfifolen,
     wrpnt_gray,
     
     write,
     wraddr,


     rdpnt_gray
     );



parameter   ADDRB = 4;
parameter   FSHW = 2;



input               wrclk;
input               wrrst;

input               fifowr;
input               fifoflush;
output              fifofull;
output              half_full;
output [ADDRB:0]    wrfifolen;
output [ADDRB:0]    wrpnt_gray;

output              write;
output [ADDRB-1:0]  wraddr;

input [ADDRB:0]     rdpnt_gray;









reg [ADDRB:0]       rdpnt_gray1= {(ADDRB+1){1'b0}};
reg [ADDRB:0]       rdpnt_gray2= {(ADDRB+1){1'b0}};

always @ ( posedge wrclk )






        begin
        rdpnt_gray1  <= rdpnt_gray;
        rdpnt_gray2  <= rdpnt_gray1;      
        end

reg [ADDRB:0] rdpnt_bin= {(ADDRB+1){1'b0}};
reg [ADDRB:0] rdpnt_bin_n= {(ADDRB+1){1'b0}};
integer       i;
always @ (rdpnt_gray2)  for (i=0;i<(ADDRB+1);i=i+1) rdpnt_bin_n[i] = ^(rdpnt_gray2[ADDRB:0]>>i);
generate
    begin
    if (FSHW == 2)
        begin: inst_2clkpp
        always @ (rdpnt_bin_n) rdpnt_bin = rdpnt_bin_n;
        end
    else
        begin : inst_3clkpp
        always @ (posedge wrclk)    rdpnt_bin <= rdpnt_bin_n;
        end
    end
endgenerate


reg     [ADDRB:0]   wrpnt_bin= {(ADDRB+1){1'b0}};


wire                fifofull;
assign              fifofull    = (wrpnt_bin[ADDRB]^rdpnt_bin[ADDRB]) &
                                  (wrpnt_bin[ADDRB-1:0] == rdpnt_bin[ADDRB-1:0]);

wire [ADDRB:0]      sublen;
assign              sublen      = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];

wire                half_full;
assign              half_full   = fifofull | sublen[ADDRB-1];

wire [ADDRB:0]      wrfifolen;
assign              wrfifolen   = sublen;

wire                write;
assign              write       = fifowr & (~fifofull);

wire [ADDRB-1:0]    wraddr;
assign              wraddr      = wrpnt_bin[ADDRB-1:0];


always @ ( posedge wrclk)
    if(wrrst)
        begin
        wrpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) wrpnt_bin <= {(ADDRB+1){1'b0}};
        else if (write) wrpnt_bin <= wrpnt_bin + 1'b1;      
        end




reg [ADDRB:0]       wrpnt_gray= {(ADDRB+1){1'b0}};

always @ ( posedge wrclk )
    if(wrrst)
        begin
        wrpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        wrpnt_gray  <= wrpnt_bin ^ {1'b0,wrpnt_bin[ADDRB:1]};
        end


endmodule
module convclk_grayffwr
    (
     wrclk,
     wrrst,

     fifowr,
     fifoflush,
     fifofull,
     half_full,
     wrfifolen,
     wrpnt_gray,
     
     write,
     wraddr,


     rdpnt_gray
     );




parameter   ADDRB = 4;
parameter   FSHW = 2;



input               wrclk;
input               wrrst;

input               fifowr;
input               fifoflush;
output              fifofull;
output              half_full;
output [ADDRB:0]    wrfifolen;
output [ADDRB:0]    wrpnt_gray;

output              write;
output [ADDRB-1:0]  wraddr;

input [ADDRB:0]     rdpnt_gray;









reg [ADDRB:0]       rdpnt_gray1= {(ADDRB+1){1'b0}};
reg [ADDRB:0]       rdpnt_gray2= {(ADDRB+1){1'b0}};

always @ ( posedge wrclk )






        begin
        rdpnt_gray1  <= rdpnt_gray;
        rdpnt_gray2  <= rdpnt_gray1;      
        end

reg [ADDRB:0] rdpnt_bin= {(ADDRB+1){1'b0}};
reg [ADDRB:0] rdpnt_bin_n= {(ADDRB+1){1'b0}};
integer       i;
always @ (rdpnt_gray2)  for (i=0;i<(ADDRB+1);i=i+1) rdpnt_bin_n[i] = ^(rdpnt_gray2[ADDRB:0]>>i);
generate
    begin
    if (FSHW == 2)
        begin: inst_2clkpp
        always @ (rdpnt_bin_n) rdpnt_bin = rdpnt_bin_n;
        end
    else
        begin : inst_3clkpp
        always @ (posedge wrclk)    rdpnt_bin <= rdpnt_bin_n;
        end
    end
endgenerate


reg     [ADDRB:0]   wrpnt_bin= {(ADDRB+1){1'b0}};


wire                fifofull;
assign              fifofull    = (wrpnt_bin[ADDRB]^rdpnt_bin[ADDRB]) &
                                  (wrpnt_bin[ADDRB-1:0] == rdpnt_bin[ADDRB-1:0]);

wire [ADDRB:0]      sublen;
assign              sublen      = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];

wire                half_full;
assign              half_full   = fifofull | sublen[ADDRB-1];

wire [ADDRB:0]      wrfifolen;
assign              wrfifolen   = sublen;

wire                write;
assign              write       = fifowr & (~fifofull);

wire [ADDRB-1:0]    wraddr;
assign              wraddr      = wrpnt_bin[ADDRB-1:0];


always @ ( posedge wrclk)
    if(wrrst)
        begin
        wrpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) wrpnt_bin <= {(ADDRB+1){1'b0}};
        else if (write) wrpnt_bin <= wrpnt_bin + 1'b1;      
        end




reg [ADDRB:0]       wrpnt_gray= {(ADDRB+1){1'b0}};

always @ ( posedge wrclk )
    if(wrrst)
        begin
        wrpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        wrpnt_gray  <= wrpnt_bin ^ {1'b0,wrpnt_bin[ADDRB:1]};
        end


endmodule