data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlconflict112x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlconflict112x.v:71: Cannot find file containing module: 'fflopx'\nfflopx #(ADDRBIT+1) memrapl1 (clk,rst,{memramre,memramra},{memramre1,memramra1});\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlconflict112x.v:75: Cannot find file containing module: 'fflopx'\nfflopx #(ADDRBIT+1) memrapl2 (clk,rst,{memramre1,memramra1},{memramre2,memramra2});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlconflict112x.v:79: Cannot find file containing module: 'fflopx'\nfflopx #(ADDRBIT+1) memrapl3 (clk,rst,{memramre2,memramra2},{memramre3,memramra3});\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module rtlconflict112x
    (
     clk,
     rst,


     eng_re,
     eng_ra,
     eng_rdd2,
     eng_wrd3,


     memwe,
     memre,
     memwa,
     memwrd,
     memra,
     memrdd
     );




parameter ADDRBIT  = 5;
parameter WIDTH    = 32;




input                   clk;
input                   rst;

input                   eng_re;
input  [ADDRBIT-1:0]    eng_ra;
output [WIDTH-1:0]      eng_rdd2;
input  [WIDTH-1:0]      eng_wrd3;

output                  memwe;
output                  memre;
output [ADDRBIT-1:0]    memwa;
output [WIDTH-1:0]      memwrd;
output [ADDRBIT-1:0]    memra;
input  [WIDTH-1:0]      memrdd;




wire                memramre = eng_re;
wire [ADDRBIT-1:0]  memramra = eng_ra;

wire                memramre1;
wire [ADDRBIT-1:0]  memramra1;
fflopx #(ADDRBIT+1) memrapl1 (clk,rst,{memramre,memramra},{memramre1,memramra1});

wire                memramre2;
wire [ADDRBIT-1:0]  memramra2;
fflopx #(ADDRBIT+1) memrapl2 (clk,rst,{memramre1,memramra1},{memramre2,memramra2});

wire                memramre3;
wire [ADDRBIT-1:0]  memramra3;
fflopx #(ADDRBIT+1) memrapl3 (clk,rst,{memramre2,memramra2},{memramre3,memramra3});

wire                memramwe = memramre3;
wire [ADDRBIT-1:0]  memramwa = memramra3;
wire [WIDTH-1:0]    memramwrd = eng_wrd3;


wire                wrconflict;
assign              wrconflict  = memramwe & (memramwa == memramra);

wire                wrconflict1;
assign              wrconflict1 = memramwe & (memramra1 == memramwa);

reg                 samestage3,samestage3_n;
reg                 samestage2;
reg                 samestage1;
always @ (posedge clk)
    begin
    if (rst)
        begin
        samestage3_n <= 1'b0;
        samestage3 <= 1'b0;
        samestage2 <= 1'b0;
        samestage1 <= 1'b0;
        end
    else
        begin
        samestage1 <= memramre & wrconflict;
        samestage2 <= wrconflict1 | samestage1;

        samestage3_n <= memramre1  & (memramra == memramra1);
        samestage3 <= samestage3_n;
        end
    end

reg [WIDTH-1:0]     memramwrd1 = {WIDTH{1'b0}};
reg [WIDTH-1:0]     memramwrd2 = {WIDTH{1'b0}};
always @ (posedge clk)
    begin
    memramwrd1 <= memramwrd;
    memramwrd2 <= wrconflict1 ? memramwrd : memramwrd1;
    end

wire [WIDTH-1:0]    eng_rdd2;
assign              eng_rdd2  = samestage3 ? memramwrd  :
                                samestage2 ? memramwrd2 : memrdd;


assign              memwe   = memramwe;
assign              memre   = memramre & (~wrconflict);
assign              memwa   = memramwa;
assign              memwrd  = memramwrd;
assign              memra   = memramra;

endmodule
module rtlconflict112x
    (
     clk,
     rst,


     eng_re,
     eng_ra,
     eng_rdd2,
     eng_wrd3,


     memwe,
     memre,
     memwa,
     memwrd,
     memra,
     memrdd
     );





parameter ADDRBIT  = 5;
parameter WIDTH    = 32;




input                   clk;
input                   rst;

input                   eng_re;
input  [ADDRBIT-1:0]    eng_ra;
output [WIDTH-1:0]      eng_rdd2;
input  [WIDTH-1:0]      eng_wrd3;

output                  memwe;
output                  memre;
output [ADDRBIT-1:0]    memwa;
output [WIDTH-1:0]      memwrd;
output [ADDRBIT-1:0]    memra;
input  [WIDTH-1:0]      memrdd;




wire                memramre = eng_re;
wire [ADDRBIT-1:0]  memramra = eng_ra;

wire                memramre1;
wire [ADDRBIT-1:0]  memramra1;
fflopx #(ADDRBIT+1) memrapl1 (clk,rst,{memramre,memramra},{memramre1,memramra1});

wire                memramre2;
wire [ADDRBIT-1:0]  memramra2;
fflopx #(ADDRBIT+1) memrapl2 (clk,rst,{memramre1,memramra1},{memramre2,memramra2});

wire                memramre3;
wire [ADDRBIT-1:0]  memramra3;
fflopx #(ADDRBIT+1) memrapl3 (clk,rst,{memramre2,memramra2},{memramre3,memramra3});

wire                memramwe = memramre3;
wire [ADDRBIT-1:0]  memramwa = memramra3;
wire [WIDTH-1:0]    memramwrd = eng_wrd3;


wire                wrconflict;
assign              wrconflict  = memramwe & (memramwa == memramra);

wire                wrconflict1;
assign              wrconflict1 = memramwe & (memramra1 == memramwa);

reg                 samestage3,samestage3_n;
reg                 samestage2;
reg                 samestage1;
always @ (posedge clk)
    begin
    if (rst)
        begin
        samestage3_n <= 1'b0;
        samestage3 <= 1'b0;
        samestage2 <= 1'b0;
        samestage1 <= 1'b0;
        end
    else
        begin
        samestage1 <= memramre & wrconflict;
        samestage2 <= wrconflict1 | samestage1;

        samestage3_n <= memramre1  & (memramra == memramra1);
        samestage3 <= samestage3_n;
        end
    end

reg [WIDTH-1:0]     memramwrd1 = {WIDTH{1'b0}};
reg [WIDTH-1:0]     memramwrd2 = {WIDTH{1'b0}};
always @ (posedge clk)
    begin
    memramwrd1 <= memramwrd;
    memramwrd2 <= wrconflict1 ? memramwrd : memramwrd1;
    end

wire [WIDTH-1:0]    eng_rdd2;
assign              eng_rdd2  = samestage3 ? memramwrd  :
                                samestage2 ? memramwrd2 : memrdd;


assign              memwe   = memramwe;
assign              memre   = memramre & (~wrconflict);
assign              memwa   = memramwa;
assign              memwrd  = memramwrd;
assign              memra   = memramra;

endmodule