data/full_repos/permissive/46454310/test.v
1: b'%Error: data/full_repos/permissive/46454310/test.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/46454310/test.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46454310/test.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46454310/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1300 rst = 0;\n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();
  reg clk, rst;
  wire [7:0] pc;
  waterbear cores (
    clk, reset, pc
  );
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, test);
  end
  

  
  initial begin
    clk = 1;
    rst = 0;
    #1 rst = 0;
    #1300 rst = 0;
    $finish;
  end
  
  always clk = #1 ~clk;
 endmodule
module test ();

  reg clk, rst;
  wire [7:0] pc;
  waterbear cores (
    clk, reset, pc
  );
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, test);
  end
  

  
  initial begin
    clk = 1;
    rst = 0;
    #1 rst = 0;
    #1300 rst = 0;
    $finish;
  end
  
  always clk = #1 ~clk;
 endmodule