data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:1: Cannot find include file: VX_tex_define.vh\n`include "VX_tex_define.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.v\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.sv\n             VX_tex_define.vh\n             VX_tex_define.vh.v\n             VX_tex_define.vh.sv\n             obj_dir/VX_tex_define.vh\n             obj_dir/VX_tex_define.vh.v\n             obj_dir/VX_tex_define.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:16: Define or directive not defined: \'`TEX_FORMAT_BITS\'\n    input wire [`TEX_FORMAT_BITS-1:0]   req_format,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:17: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    input wire [`TEX_FILTER_BITS-1:0]   req_filter,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:18: Define or directive not defined: \'`TEX_WRAP_BITS\'\n    input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:19: Define or directive not defined: \'`TEX_ADDR_BITS\'\n    input wire [`TEX_ADDR_BITS-1:0]     req_baseaddr,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:20: Define or directive not defined: \'`TEX_MIPOFF_BITS\'\n    input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,    \n                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:21: Define or directive not defined: \'`TEX_DIM_BITS\'\n    input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:29: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    output wire [`TEX_FILTER_BITS-1:0]  rsp_filter,\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:30: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    output wire [`TEX_STRIDE_BITS-1:0]  rsp_stride,\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:32: Define or directive not defined: \'`BLEND_FRAC\'\n    output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:37: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (CORE_ID)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:37: syntax error, unexpected \'(\'\n    `UNUSED_PARAM (CORE_ID)\n                   ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`MAX\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                            ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`TEX_DIM_BITS\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: Define or directive not defined: \'`FIXED_INT\'\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                                                         ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:41: Define or directive not defined: \'`FIXED_INT\'\n    localparam SCALED_X_W = (2 * `FIXED_INT);\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:41: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    localparam SCALED_X_W = (2 * `FIXED_INT);\n                                           ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:42: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;\n                                                         ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:46: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    wire [`TEX_FILTER_BITS-1:0] filter_s0;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:48: Define or directive not defined: \'`FIXED_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:49: Define or directive not defined: \'`FIXED_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:50: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:52: Define or directive not defined: \'`TEX_DIM_BITS\'\n    wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0;\n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: Define or directive not defined: \'`FIXED_FRAC\'\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: Define or directive not defined: \'`FIXED_HALF\'\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                                                        ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_FILTER_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_DIM_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`FIXED_FRAC\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                                                                       ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:107: Define or directive not defined: \'`FIXED_INT\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_lo;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:108: Define or directive not defined: \'`FIXED_INT\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_hi;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:109: Define or directive not defined: \'`BLEND_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] blends;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: Define or directive not defined: \'`BLEND_FRAC\'\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: Define or directive not defined: \'`BLEND_FRAC\'\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                                                ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:120: Define or directive not defined: \'`UNUSED_VAR\'\n    `UNUSED_VAR (log_pitch_s0)\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:120: syntax error, unexpected \'(\'\n    `UNUSED_VAR (log_pitch_s0)\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:136: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`TEX_FILTER_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`BLEND_FRAC\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                                                                                       ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:169: Define or directive not defined: \'`FIXED_INT\'\nfunction logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:169: Define or directive not defined: \'`FIXED_FRAC\'\nfunction logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, \n                                                           ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
function logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, 
                                              input logic [`TEX_DIM_BITS-1:0] dim);
`IGNORE_WARNINGS_BEGIN
    logic [`FIXED_BITS-1:0] out;
`IGNORE_WARNINGS_END
    out = `FIXED_BITS'(src) << dim;
    return out[`FIXED_FRAC +: `FIXED_INT];
endfunction
function logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, 
                                              input logic [`TEX_DIM_BITS-1:0] dim);

`IGNORE_WARNINGS_BEGIN
    logic [`FIXED_BITS-1:0] out;
`IGNORE_WARNINGS_END
    out = `FIXED_BITS'(src) << dim;
    return out[`FIXED_FRAC +: `FIXED_INT];
endfunction