data/full_repos/permissive/487568919/basic_verilog/dual_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v
data/verilator_xmls/cdf36599-f4ab-47d1-aacc-354eee123d0f.xml
function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction
function integer clogb2;

    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction