data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv:70: Cannot find file containing module: 'addr_decoder'\n    addr_decoder #(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/addr_decoder\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/addr_decoder.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/addr_decoder.sv\n             addr_decoder\n             addr_decoder.v\n             addr_decoder.sv\n             obj_dir/addr_decoder\n             obj_dir/addr_decoder.v\n             obj_dir/addr_decoder.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv:106: Cannot find file containing module: 'rr_arb_tree'\n    rr_arb_tree #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv:128: Cannot find file containing module: 'spill_register'\n      spill_register #(\n      ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module simplex_xbar #(
  parameter int unsigned NumIn      = 4,
  parameter int unsigned NumOut     = 4,
  parameter int unsigned DataWidth  = 32,
  parameter bit ExtPrio             = 1'b0,
  parameter bit AxiVldRdy           = 1'b0,
  parameter bit SpillRegister       = 1'b0,
  parameter bit FallThroughRegister = 1'b0,

  localparam int unsigned NumInLog  = NumIn == 1 ? 1 : $clog2(NumIn),
  localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut)
) (
  input  logic                             clk_i,
  input  logic                             rst_ni,

  input  logic [NumOut-1:0][NumInLog-1:0]  rr_i,

  input  logic [NumIn-1:0]                 valid_i,
  output logic [NumIn-1:0]                 ready_o,
  input  logic [NumIn-1:0][NumOutLog-1:0]  tgt_addr_i,
  input  logic [NumIn-1:0][DataWidth-1:0]  data_i,

  output logic [NumOut-1:0]                valid_o,
  input  logic [NumOut-1:0]                ready_i,
  output logic [NumOut-1:0][NumInLog-1:0]  ini_addr_o,
  output logic [NumOut-1:0][DataWidth-1:0] data_o
);



  logic [NumOut-1:0][ NumIn-1:0][DataWidth-1:0] tgt_data;
  logic [NumOut-1:0][ NumIn-1:0]                tgt_ready, tgt_valid;

  logic [ NumIn-1:0][NumOut-1:0][DataWidth-1:0] ini_data;
  logic [ NumIn-1:0][NumOut-1:0]                ini_ready, ini_valid;

  logic [NumOut-1:0]                arb_valid, arb_ready;
  logic [NumOut-1:0][DataWidth-1:0] arb_data;
  logic [NumOut-1:0][NumInLog-1:0]  arb_ini_addr;



  for (genvar j = 0; unsigned'(j) < NumIn; j++) begin: gen_inputs




    addr_decoder #(
      .NumOut   (NumOut   ),
      .DataWidth(DataWidth),
      .AxiVldRdy(AxiVldRdy)
    ) i_addr_decoder (

      .valid_i(valid_i[j]   ),
      .addr_i (tgt_addr_i[j]),
      .data_i (data_i[j]    ),
      .ready_o(ready_o[j]   ),

      .valid_o(ini_valid[j] ),
      .ready_i(ini_ready[j] ),
      .data_o (ini_data[j]  )
    );


    for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape
      assign tgt_valid[k][j] = ini_valid[j][k];
      assign ini_ready[j][k] = tgt_ready[k][j];
      assign tgt_data[k][j]  = ini_data[j][k] ;
    end

  end : gen_inputs



  for (genvar k = 0; k < NumOut; k++) begin: gen_rr_outputs




    rr_arb_tree #(
      .NumIn    (NumIn    ),
      .DataWidth(DataWidth),
      .ExtPrio  (ExtPrio  ),
      .AxiVldRdy(AxiVldRdy)
    ) i_rr_arb_tree (
      .clk_i  (clk_i          ),
      .rst_ni (rst_ni         ),
      .flush_i(1'b0           ),
      .rr_i   (rr_i[k]        ),
      .req_i  (tgt_valid[k]   ),
      .gnt_o  (tgt_ready[k]   ),
      .data_i (tgt_data[k]    ),
      .gnt_i  (arb_ready[k]   ),
      .req_o  (arb_valid[k]   ),
      .data_o (arb_data[k]    ),
      .idx_o  (arb_ini_addr[k])
    );



    if (!FallThroughRegister || SpillRegister) begin
      spill_register #(
        .Bypass(!SpillRegister               ),
        .T     (logic[DataWidth+NumInLog-1:0])
      ) i_register (
        .clk_i  (clk_i                         ),
        .rst_ni (rst_ni                        ),
        .data_i ({arb_data[k], arb_ini_addr[k]}),
        .valid_i(arb_valid[k]                  ),
        .ready_o(arb_ready[k]                  ),
        .data_o ({data_o[k], ini_addr_o[k]}    ),
        .valid_o(valid_o[k]                    ),
        .ready_i(ready_i[k]                    )
      );
    end else begin
      fall_through_register #(
        .T(logic[DataWidth+NumInLog-1:0])
      ) i_register (
        .clk_i     (clk_i                         ),
        .rst_ni    (rst_ni                        ),
        .clr_i     (1'b0                          ),
        .testmode_i(1'b0                          ),
        .data_i    ({arb_data[k], arb_ini_addr[k]}),
        .valid_i   (arb_valid[k]                  ),
        .ready_o   (arb_ready[k]                  ),
        .data_o    ({data_o[k], ini_addr_o[k]}    ),
        .valid_o   (valid_o[k]                    ),
        .ready_i   (ready_i[k]                    )
      );
    end

  end : gen_rr_outputs



  if (NumIn <= 0)
    $fatal(1, "[simplex_xbar] NumIn needs to be larger than 0.");

  if (NumOut <= 0)
    $fatal(1, "[simplex_xbar] NumOut needs to be larger than 0.");

endmodule
module simplex_xbar #(
  parameter int unsigned NumIn      = 4,
  parameter int unsigned NumOut     = 4,
  parameter int unsigned DataWidth  = 32,
  parameter bit ExtPrio             = 1'b0,
  parameter bit AxiVldRdy           = 1'b0,
  parameter bit SpillRegister       = 1'b0,
  parameter bit FallThroughRegister = 1'b0,

  localparam int unsigned NumInLog  = NumIn == 1 ? 1 : $clog2(NumIn),
  localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut)
) (
  input  logic                             clk_i,
  input  logic                             rst_ni,

  input  logic [NumOut-1:0][NumInLog-1:0]  rr_i,

  input  logic [NumIn-1:0]                 valid_i,
  output logic [NumIn-1:0]                 ready_o,
  input  logic [NumIn-1:0][NumOutLog-1:0]  tgt_addr_i,
  input  logic [NumIn-1:0][DataWidth-1:0]  data_i,

  output logic [NumOut-1:0]                valid_o,
  input  logic [NumOut-1:0]                ready_i,
  output logic [NumOut-1:0][NumInLog-1:0]  ini_addr_o,
  output logic [NumOut-1:0][DataWidth-1:0] data_o
);




  logic [NumOut-1:0][ NumIn-1:0][DataWidth-1:0] tgt_data;
  logic [NumOut-1:0][ NumIn-1:0]                tgt_ready, tgt_valid;

  logic [ NumIn-1:0][NumOut-1:0][DataWidth-1:0] ini_data;
  logic [ NumIn-1:0][NumOut-1:0]                ini_ready, ini_valid;

  logic [NumOut-1:0]                arb_valid, arb_ready;
  logic [NumOut-1:0][DataWidth-1:0] arb_data;
  logic [NumOut-1:0][NumInLog-1:0]  arb_ini_addr;



  for (genvar j = 0; unsigned'(j) < NumIn; j++) begin: gen_inputs




    addr_decoder #(
      .NumOut   (NumOut   ),
      .DataWidth(DataWidth),
      .AxiVldRdy(AxiVldRdy)
    ) i_addr_decoder (

      .valid_i(valid_i[j]   ),
      .addr_i (tgt_addr_i[j]),
      .data_i (data_i[j]    ),
      .ready_o(ready_o[j]   ),

      .valid_o(ini_valid[j] ),
      .ready_i(ini_ready[j] ),
      .data_o (ini_data[j]  )
    );


    for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape
      assign tgt_valid[k][j] = ini_valid[j][k];
      assign ini_ready[j][k] = tgt_ready[k][j];
      assign tgt_data[k][j]  = ini_data[j][k] ;
    end

  end : gen_inputs



  for (genvar k = 0; k < NumOut; k++) begin: gen_rr_outputs




    rr_arb_tree #(
      .NumIn    (NumIn    ),
      .DataWidth(DataWidth),
      .ExtPrio  (ExtPrio  ),
      .AxiVldRdy(AxiVldRdy)
    ) i_rr_arb_tree (
      .clk_i  (clk_i          ),
      .rst_ni (rst_ni         ),
      .flush_i(1'b0           ),
      .rr_i   (rr_i[k]        ),
      .req_i  (tgt_valid[k]   ),
      .gnt_o  (tgt_ready[k]   ),
      .data_i (tgt_data[k]    ),
      .gnt_i  (arb_ready[k]   ),
      .req_o  (arb_valid[k]   ),
      .data_o (arb_data[k]    ),
      .idx_o  (arb_ini_addr[k])
    );



    if (!FallThroughRegister || SpillRegister) begin
      spill_register #(
        .Bypass(!SpillRegister               ),
        .T     (logic[DataWidth+NumInLog-1:0])
      ) i_register (
        .clk_i  (clk_i                         ),
        .rst_ni (rst_ni                        ),
        .data_i ({arb_data[k], arb_ini_addr[k]}),
        .valid_i(arb_valid[k]                  ),
        .ready_o(arb_ready[k]                  ),
        .data_o ({data_o[k], ini_addr_o[k]}    ),
        .valid_o(valid_o[k]                    ),
        .ready_i(ready_i[k]                    )
      );
    end else begin
      fall_through_register #(
        .T(logic[DataWidth+NumInLog-1:0])
      ) i_register (
        .clk_i     (clk_i                         ),
        .rst_ni    (rst_ni                        ),
        .clr_i     (1'b0                          ),
        .testmode_i(1'b0                          ),
        .data_i    ({arb_data[k], arb_ini_addr[k]}),
        .valid_i   (arb_valid[k]                  ),
        .ready_o   (arb_ready[k]                  ),
        .data_o    ({data_o[k], ini_addr_o[k]}    ),
        .valid_o   (valid_o[k]                    ),
        .ready_i   (ready_i[k]                    )
      );
    end

  end : gen_rr_outputs



  if (NumIn <= 0)
    $fatal(1, "[simplex_xbar] NumIn needs to be larger than 0.");

  if (NumOut <= 0)
    $fatal(1, "[simplex_xbar] NumOut needs to be larger than 0.");

endmodule