data/full_repos/permissive/434187796/src/SEG.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/434187796/src/SEG.v:15: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'FLASH_SEG\'\nmodule FLASH_SEG\n       ^~~~~~~~~\n                                                                    : ... Top module \'SEG_DECODER\'\nmodule SEG_DECODER\n       ^~~~~~~~~~~\n                                                                    : ... Top module \'SEG_SCAN\'\nmodule SEG_SCAN\n       ^~~~~~~~\n%Error: data/full_repos/permissive/434187796/src/SEG.v:67: Cannot find file containing module: \'TIMER\'\n        TIMER #(.cycle(32\'d41_667)) timer_833us (.clk(clk), .rst(rst), .cy(clk_833us));\n        ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/434187796/src,data/full_repos/permissive/434187796/TIMER\n             data/full_repos/permissive/434187796/src,data/full_repos/permissive/434187796/TIMER.v\n             data/full_repos/permissive/434187796/src,data/full_repos/permissive/434187796/TIMER.sv\n             TIMER\n             TIMER.v\n             TIMER.sv\n             obj_dir/TIMER\n             obj_dir/TIMER.v\n             obj_dir/TIMER.sv\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:23: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n                seg_data <= 7\'b111_1111;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:28: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h40\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d0:seg_data <= 7\'b100_0000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:29: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h79\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d1:seg_data <= 7\'b111_1001;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:30: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h24\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d2:seg_data <= 7\'b010_0100;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:31: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h30\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d3:seg_data <= 7\'b011_0000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:32: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h19\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d4:seg_data <= 7\'b001_1001;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:33: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h12\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d5:seg_data <= 7\'b001_0010;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d6:seg_data <= 7\'b000_0010;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h78\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d7:seg_data <= 7\'b111_1000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:36: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d8:seg_data <= 7\'b000_0000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:37: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h10\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'d9:seg_data <= 7\'b001_0000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:38: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h8\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'ha:seg_data <= 7\'b000_1000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'hb:seg_data <= 7\'b000_0011;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:40: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h46\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'hc:seg_data <= 7\'b100_0110;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:41: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h21\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'hd:seg_data <= 7\'b010_0001;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:42: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'he:seg_data <= 7\'b000_0110;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:43: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'he\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         4\'hf:seg_data <= 7\'b000_1110;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/434187796/src/SEG.v:44: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                 : ... In instance SEG_DECODER\n         default:seg_data <= 7\'b111_1111;\n                          ^~\n%Error: Exiting due to 1 error(s), 19 warning(s)\n'
module SEG_DECODER
        (
                input [3:0] bin_data,
                input dot,
                output reg [7:0] seg_data
        );

        initial begin
                seg_data <= 7'b111_1111;
        end

        always @(bin_data or dot) begin
	        case(bin_data)
	        4'd0:seg_data <= 7'b100_0000;
	        4'd1:seg_data <= 7'b111_1001;
	        4'd2:seg_data <= 7'b010_0100;
	        4'd3:seg_data <= 7'b011_0000;
	        4'd4:seg_data <= 7'b001_1001;
	        4'd5:seg_data <= 7'b001_0010;
	        4'd6:seg_data <= 7'b000_0010;
	        4'd7:seg_data <= 7'b111_1000;
	        4'd8:seg_data <= 7'b000_0000;
	        4'd9:seg_data <= 7'b001_0000;
	        4'ha:seg_data <= 7'b000_1000;
	        4'hb:seg_data <= 7'b000_0011;
	        4'hc:seg_data <= 7'b100_0110;
	        4'hd:seg_data <= 7'b010_0001;
	        4'he:seg_data <= 7'b000_0110;
	        4'hf:seg_data <= 7'b000_1110;
	        default:seg_data <= 7'b111_1111;
	        endcase
                seg_data[7] <= ~dot;
        end
endmodule
module SEG_DECODER
        (
                input [3:0] bin_data,
                input dot,
                output reg [7:0] seg_data
        );


        initial begin
                seg_data <= 7'b111_1111;
        end

        always @(bin_data or dot) begin
	        case(bin_data)
	        4'd0:seg_data <= 7'b100_0000;
	        4'd1:seg_data <= 7'b111_1001;
	        4'd2:seg_data <= 7'b010_0100;
	        4'd3:seg_data <= 7'b011_0000;
	        4'd4:seg_data <= 7'b001_1001;
	        4'd5:seg_data <= 7'b001_0010;
	        4'd6:seg_data <= 7'b000_0010;
	        4'd7:seg_data <= 7'b111_1000;
	        4'd8:seg_data <= 7'b000_0000;
	        4'd9:seg_data <= 7'b001_0000;
	        4'ha:seg_data <= 7'b000_1000;
	        4'hb:seg_data <= 7'b000_0011;
	        4'hc:seg_data <= 7'b100_0110;
	        4'hd:seg_data <= 7'b010_0001;
	        4'he:seg_data <= 7'b000_0110;
	        4'hf:seg_data <= 7'b000_1110;
	        default:seg_data <= 7'b111_1111;
	        endcase
                seg_data[7] <= ~dot;
        end
endmodule