data/full_repos/permissive/450072296/verilog/rtl/stud_ds_volume.v
data/verilator_xmls/5ac26b92-04bc-465a-a228-453fbb15b5e2.xml
module stud_ds_volume
#(
	parameter AUDIO_WIDTH=16,
	VOLUME_WIDTH=8
)
(
	output reg [AUDIO_WIDTH - 1:0] audio_o,

	input signed [AUDIO_WIDTH - 1:0] audio_i,

	input mute_i,
	input [VOLUME_WIDTH - 1:0] volume_i,

	input clk_i,
	input n_rst_i
);



reg [VOLUME_WIDTH : 0] volume;

reg signed [AUDIO_WIDTH : 0] audio_scaled;

reg signed [AUDIO_WIDTH-1 : 0] audio_offset;

reg [AUDIO_WIDTH-1 : 0] next_audio_out;

reg dummy1;
reg [VOLUME_WIDTH-1:0] dummy2;



always @* begin
	if (mute_i) begin

		volume = {VOLUME_WIDTH + 1 {1'b0}};
	end else begin

		volume = {1'b0, volume_i} + {{VOLUME_WIDTH {1'b0}}, 1'b1};
	end


	{dummy2,audio_scaled} = ({{VOLUME_WIDTH {audio_i[AUDIO_WIDTH - 1]}}, audio_i} * volume) >>> VOLUME_WIDTH;


	{dummy1,audio_offset} = audio_scaled[AUDIO_WIDTH : 0] + {2'b01, {AUDIO_WIDTH - 1 {1'b0}}};
	

	next_audio_out = audio_offset[AUDIO_WIDTH - 1 : 0];
end


always @(posedge clk_i) begin
	if (!n_rst_i) begin


		audio_o <= {1'b0, {AUDIO_WIDTH - 1 {1'b1}}};
	end else begin
		audio_o <= next_audio_out;
	end
end
	
endmodule
module stud_ds_volume
#(
	parameter AUDIO_WIDTH=16,
	VOLUME_WIDTH=8
)
(
	output reg [AUDIO_WIDTH - 1:0] audio_o,

	input signed [AUDIO_WIDTH - 1:0] audio_i,

	input mute_i,
	input [VOLUME_WIDTH - 1:0] volume_i,

	input clk_i,
	input n_rst_i
);




reg [VOLUME_WIDTH : 0] volume;

reg signed [AUDIO_WIDTH : 0] audio_scaled;

reg signed [AUDIO_WIDTH-1 : 0] audio_offset;

reg [AUDIO_WIDTH-1 : 0] next_audio_out;

reg dummy1;
reg [VOLUME_WIDTH-1:0] dummy2;



always @* begin
	if (mute_i) begin

		volume = {VOLUME_WIDTH + 1 {1'b0}};
	end else begin

		volume = {1'b0, volume_i} + {{VOLUME_WIDTH {1'b0}}, 1'b1};
	end


	{dummy2,audio_scaled} = ({{VOLUME_WIDTH {audio_i[AUDIO_WIDTH - 1]}}, audio_i} * volume) >>> VOLUME_WIDTH;


	{dummy1,audio_offset} = audio_scaled[AUDIO_WIDTH : 0] + {2'b01, {AUDIO_WIDTH - 1 {1'b0}}};
	

	next_audio_out = audio_offset[AUDIO_WIDTH - 1 : 0];
end


always @(posedge clk_i) begin
	if (!n_rst_i) begin


		audio_o <= {1'b0, {AUDIO_WIDTH - 1 {1'b1}}};
	end else begin
		audio_o <= next_audio_out;
	end
end
	
endmodule