data/full_repos/permissive/488093047/Verilog Codes/D_FlipflopFeed.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/D_FlipflopFeed.v\n%Error: Exiting due to 3 error(s)\n'
module D_FlipflopFeed (In,clk,reset,Q);
input In,clk,reset;
output  Q;
wire D,Qbar;
not DUT1(Qbar,Q);
or  DUT2(D,In,Qbar);
D_Flipflop DUT3(.D(D),.Q(Q),.clk(clk),.reset(reset));
endmodule
module D_FlipflopFeed (In,clk,reset,Q);

input In,clk,reset;
output  Q;
wire D,Qbar;
not DUT1(Qbar,Q);
or  DUT2(D,In,Qbar);
D_Flipflop DUT3(.D(D),.Q(Q),.clk(clk),.reset(reset));
endmodule