data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src/m7s_emb.v
1: b"%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src/m7s_emb.v:45: Cannot find file containing module: 'M7S_EMB18K'\nM7S_EMB18K #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src,data/full_repos/permissive/507203156/M7S_EMB18K\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src,data/full_repos/permissive/507203156/M7S_EMB18K.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src,data/full_repos/permissive/507203156/M7S_EMB18K.sv\n             M7S_EMB18K\n             M7S_EMB18K.v\n             M7S_EMB18K.sv\n             obj_dir/M7S_EMB18K\n             obj_dir/M7S_EMB18K.v\n             obj_dir/M7S_EMB18K.sv\n%Error: Exiting due to 1 error(s)\n"
module m7s_emb(
    clk,
    a,
    d,
    ce,
    we,
    q
);

input clk;
input [8:0] a;
input [31:0] d;
input ce;
input we;
output [31:0] q;

wire [17:0] q0;
wire [17:0] q1;
wire [17:0] q2;
wire [17:0] q3;
reg [0:0] a_reg;
always @(posedge clk) begin
	if (ce && !we)  begin
		a_reg <= a[8];
	end
end
assign q = (~a_reg[0])? {q1[15], q0[15], q1[14], q0[14], q1[13], q0[13], q1[12], q0[12], q1[11], q0[11], q1[10], q0[10], q1[9], q0[9], q1[8], q0[8], q1[7], q0[7], q1[6], q0[6], q1[5], q0[5], q1[4], q0[4], q1[3], q0[3], q1[2], q0[2], q1[1], q0[1], q1[0], q0[0]} :
            {q3[15], q2[15], q3[14], q2[14], q3[13], q2[13], q3[12], q2[12], q3[11], q2[11], q3[10], q2[10], q3[9], q2[9], q3[8], q2[8], q3[7], q2[7], q3[6], q2[6], q3[5], q2[5], q3[4], q2[4], q3[3], q2[3], q3[2], q2[2], q3[1], q2[1], q3[0], q2[0]};

M7S_EMB18K #(
        .width_ext_mode (1'b1),
        .depth_ext_mode (1'b0),
        .dedicated_cfg (16'b1111111111111111),
        .fifo_en (1'b0),
        .emb5k_1_porta_prog (8'b11110000),
        .emb5k_1_portb_prog (8'b00001111),
        .emb5k_1_modea_sel (4'b0000),
        .emb5k_1_modeb_sel (4'b0000),
        .emb5k_1_porta_wr_mode (2'b00),
        .emb5k_1_portb_wr_mode (2'b00),
        .emb5k_1_porta_reg_out (1'b0),
        .emb5k_1_portb_reg_out (1'b0),
        .emb5k_1_reset_value_a (9'b000000000),
        .emb5k_1_reset_value_b (9'b000000000),
        .emb5k_1_porta_data_width (16),
        .emb5k_1_portb_data_width (16),
        .emb5k_1_operation_mode ("single_port"),
        .emb5k_1_init_file (""),
        .emb5k_2_porta_prog (8'b11110000),
        .emb5k_2_portb_prog (8'b00001111),
        .emb5k_2_modea_sel (4'b0000),
        .emb5k_2_modeb_sel (4'b0000),
        .emb5k_2_porta_wr_mode (2'b00),
        .emb5k_2_portb_wr_mode (2'b00),
        .emb5k_2_porta_reg_out (1'b0),
        .emb5k_2_portb_reg_out (1'b0),
        .emb5k_2_reset_value_a (9'b000000000),
        .emb5k_2_reset_value_b (9'b000000000),
        .emb5k_2_porta_data_width (16),
        .emb5k_2_portb_data_width (16),
        .emb5k_2_operation_mode ("single_port"),
        .emb5k_2_init_file (""),
        .emb5k_3_porta_prog (8'b11110000),
        .emb5k_3_portb_prog (8'b00001111),
        .emb5k_3_modea_sel (4'b0000),
        .emb5k_3_modeb_sel (4'b0000),
        .emb5k_3_porta_wr_mode (2'b00),
        .emb5k_3_portb_wr_mode (2'b00),
        .emb5k_3_porta_reg_out (1'b0),
        .emb5k_3_portb_reg_out (1'b0),
        .emb5k_3_reset_value_a (9'b000000000),
        .emb5k_3_reset_value_b (9'b000000000),
        .emb5k_3_porta_data_width (16),
        .emb5k_3_portb_data_width (16),
        .emb5k_3_operation_mode ("single_port"),
        .emb5k_3_init_file (""),
        .emb5k_4_porta_prog (8'b11110000),
        .emb5k_4_portb_prog (8'b00001111),
        .emb5k_4_modea_sel (4'b0000),
        .emb5k_4_modeb_sel (4'b0000),
        .emb5k_4_porta_wr_mode (2'b00),
        .emb5k_4_portb_wr_mode (2'b00),
        .emb5k_4_porta_reg_out (1'b0),
        .emb5k_4_portb_reg_out (1'b0),
        .emb5k_4_reset_value_a (9'b000000000),
        .emb5k_4_reset_value_b (9'b000000000),
        .emb5k_4_porta_data_width (16),
        .emb5k_4_portb_data_width (16),
        .emb5k_4_operation_mode ("single_port"),
        .emb5k_4_init_file ("")
) u_emb18k_0 (
        .wfull (),
        .wfull_almost (),
        .rempty (),
        .rempty_almost (),
        .overflow (),
        .wr_ack (),
        .underflow (),
        .rd_ack (),
        .fifo_clr (),
        .wr_req_n (),
        .rd_req_n (),
        .rd_ha (),
        .rd_la (),
        .cea (ce),
        .ceb (1'b0),
        .haa ({1'b0, a[8]}),
        .hab (),
        .wea (we),
        .web (1'b0),
        .c1r1_cea (),
        .c1r1_ceb (),
        .c1r1_wea (),
        .c1r1_web (),
        .c1r1_clka (clk),
        .c1r1_clkb (1'b0),
        .c1r1_rstna (1'b1),
        .c1r1_rstnb (1'b1),
        .c1r1_aa ({a[7:0], 4'b0}),
        .c1r1_ab (),
        .c1r1_da ({2'b0, d[30], d[28], d[26], d[24], d[22], d[20], d[18], d[16], d[14], d[12], d[10], d[8], d[6], d[4], d[2], d[0]}),
        .c1r1_db (),
        .c1r1_q (q0),
        .c1r2_cea (),
        .c1r2_ceb (),
        .c1r2_wea (),
        .c1r2_web (),
        .c1r2_clka (clk),
        .c1r2_clkb (1'b0),
        .c1r2_rstna (1'b1),
        .c1r2_rstnb (1'b1),
        .c1r2_aa (),
        .c1r2_ab (),
        .c1r2_da ({2'b0, d[31], d[29], d[27], d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], d[9], d[7], d[5], d[3], d[1]}),
        .c1r2_db (),
        .c1r2_q (q1),
        .c1r3_cea (),
        .c1r3_ceb (),
        .c1r3_wea (),
        .c1r3_web (),
        .c1r3_clka (clk),
        .c1r3_clkb (1'b0),
        .c1r3_rstna (1'b1),
        .c1r3_rstnb (1'b1),
        .c1r3_aa (),
        .c1r3_ab (),
        .c1r3_da ({2'b0, d[30], d[28], d[26], d[24], d[22], d[20], d[18], d[16], d[14], d[12], d[10], d[8], d[6], d[4], d[2], d[0]}),
        .c1r3_db (),
        .c1r3_q (q2),
        .c1r4_cea (),
        .c1r4_ceb (),
        .c1r4_wea (),
        .c1r4_web (),
        .c1r4_clka (clk),
        .c1r4_clkb (1'b0),
        .c1r4_rstna (1'b1),
        .c1r4_rstnb (1'b1),
        .c1r4_aa (),
        .c1r4_ab (),
        .c1r4_da ({2'b0, d[31], d[29], d[27], d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], d[9], d[7], d[5], d[3], d[1]}),
        .c1r4_db (),
        .c1r4_q (q3)
);

endmodule
module m7s_emb(
    clk,
    a,
    d,
    ce,
    we,
    q
);


input clk;
input [8:0] a;
input [31:0] d;
input ce;
input we;
output [31:0] q;

wire [17:0] q0;
wire [17:0] q1;
wire [17:0] q2;
wire [17:0] q3;
reg [0:0] a_reg;
always @(posedge clk) begin
	if (ce && !we)  begin
		a_reg <= a[8];
	end
end
assign q = (~a_reg[0])? {q1[15], q0[15], q1[14], q0[14], q1[13], q0[13], q1[12], q0[12], q1[11], q0[11], q1[10], q0[10], q1[9], q0[9], q1[8], q0[8], q1[7], q0[7], q1[6], q0[6], q1[5], q0[5], q1[4], q0[4], q1[3], q0[3], q1[2], q0[2], q1[1], q0[1], q1[0], q0[0]} :
            {q3[15], q2[15], q3[14], q2[14], q3[13], q2[13], q3[12], q2[12], q3[11], q2[11], q3[10], q2[10], q3[9], q2[9], q3[8], q2[8], q3[7], q2[7], q3[6], q2[6], q3[5], q2[5], q3[4], q2[4], q3[3], q2[3], q3[2], q2[2], q3[1], q2[1], q3[0], q2[0]};

M7S_EMB18K #(
        .width_ext_mode (1'b1),
        .depth_ext_mode (1'b0),
        .dedicated_cfg (16'b1111111111111111),
        .fifo_en (1'b0),
        .emb5k_1_porta_prog (8'b11110000),
        .emb5k_1_portb_prog (8'b00001111),
        .emb5k_1_modea_sel (4'b0000),
        .emb5k_1_modeb_sel (4'b0000),
        .emb5k_1_porta_wr_mode (2'b00),
        .emb5k_1_portb_wr_mode (2'b00),
        .emb5k_1_porta_reg_out (1'b0),
        .emb5k_1_portb_reg_out (1'b0),
        .emb5k_1_reset_value_a (9'b000000000),
        .emb5k_1_reset_value_b (9'b000000000),
        .emb5k_1_porta_data_width (16),
        .emb5k_1_portb_data_width (16),
        .emb5k_1_operation_mode ("single_port"),
        .emb5k_1_init_file (""),
        .emb5k_2_porta_prog (8'b11110000),
        .emb5k_2_portb_prog (8'b00001111),
        .emb5k_2_modea_sel (4'b0000),
        .emb5k_2_modeb_sel (4'b0000),
        .emb5k_2_porta_wr_mode (2'b00),
        .emb5k_2_portb_wr_mode (2'b00),
        .emb5k_2_porta_reg_out (1'b0),
        .emb5k_2_portb_reg_out (1'b0),
        .emb5k_2_reset_value_a (9'b000000000),
        .emb5k_2_reset_value_b (9'b000000000),
        .emb5k_2_porta_data_width (16),
        .emb5k_2_portb_data_width (16),
        .emb5k_2_operation_mode ("single_port"),
        .emb5k_2_init_file (""),
        .emb5k_3_porta_prog (8'b11110000),
        .emb5k_3_portb_prog (8'b00001111),
        .emb5k_3_modea_sel (4'b0000),
        .emb5k_3_modeb_sel (4'b0000),
        .emb5k_3_porta_wr_mode (2'b00),
        .emb5k_3_portb_wr_mode (2'b00),
        .emb5k_3_porta_reg_out (1'b0),
        .emb5k_3_portb_reg_out (1'b0),
        .emb5k_3_reset_value_a (9'b000000000),
        .emb5k_3_reset_value_b (9'b000000000),
        .emb5k_3_porta_data_width (16),
        .emb5k_3_portb_data_width (16),
        .emb5k_3_operation_mode ("single_port"),
        .emb5k_3_init_file (""),
        .emb5k_4_porta_prog (8'b11110000),
        .emb5k_4_portb_prog (8'b00001111),
        .emb5k_4_modea_sel (4'b0000),
        .emb5k_4_modeb_sel (4'b0000),
        .emb5k_4_porta_wr_mode (2'b00),
        .emb5k_4_portb_wr_mode (2'b00),
        .emb5k_4_porta_reg_out (1'b0),
        .emb5k_4_portb_reg_out (1'b0),
        .emb5k_4_reset_value_a (9'b000000000),
        .emb5k_4_reset_value_b (9'b000000000),
        .emb5k_4_porta_data_width (16),
        .emb5k_4_portb_data_width (16),
        .emb5k_4_operation_mode ("single_port"),
        .emb5k_4_init_file ("")
) u_emb18k_0 (
        .wfull (),
        .wfull_almost (),
        .rempty (),
        .rempty_almost (),
        .overflow (),
        .wr_ack (),
        .underflow (),
        .rd_ack (),
        .fifo_clr (),
        .wr_req_n (),
        .rd_req_n (),
        .rd_ha (),
        .rd_la (),
        .cea (ce),
        .ceb (1'b0),
        .haa ({1'b0, a[8]}),
        .hab (),
        .wea (we),
        .web (1'b0),
        .c1r1_cea (),
        .c1r1_ceb (),
        .c1r1_wea (),
        .c1r1_web (),
        .c1r1_clka (clk),
        .c1r1_clkb (1'b0),
        .c1r1_rstna (1'b1),
        .c1r1_rstnb (1'b1),
        .c1r1_aa ({a[7:0], 4'b0}),
        .c1r1_ab (),
        .c1r1_da ({2'b0, d[30], d[28], d[26], d[24], d[22], d[20], d[18], d[16], d[14], d[12], d[10], d[8], d[6], d[4], d[2], d[0]}),
        .c1r1_db (),
        .c1r1_q (q0),
        .c1r2_cea (),
        .c1r2_ceb (),
        .c1r2_wea (),
        .c1r2_web (),
        .c1r2_clka (clk),
        .c1r2_clkb (1'b0),
        .c1r2_rstna (1'b1),
        .c1r2_rstnb (1'b1),
        .c1r2_aa (),
        .c1r2_ab (),
        .c1r2_da ({2'b0, d[31], d[29], d[27], d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], d[9], d[7], d[5], d[3], d[1]}),
        .c1r2_db (),
        .c1r2_q (q1),
        .c1r3_cea (),
        .c1r3_ceb (),
        .c1r3_wea (),
        .c1r3_web (),
        .c1r3_clka (clk),
        .c1r3_clkb (1'b0),
        .c1r3_rstna (1'b1),
        .c1r3_rstnb (1'b1),
        .c1r3_aa (),
        .c1r3_ab (),
        .c1r3_da ({2'b0, d[30], d[28], d[26], d[24], d[22], d[20], d[18], d[16], d[14], d[12], d[10], d[8], d[6], d[4], d[2], d[0]}),
        .c1r3_db (),
        .c1r3_q (q2),
        .c1r4_cea (),
        .c1r4_ceb (),
        .c1r4_wea (),
        .c1r4_web (),
        .c1r4_clka (clk),
        .c1r4_clkb (1'b0),
        .c1r4_rstna (1'b1),
        .c1r4_rstnb (1'b1),
        .c1r4_aa (),
        .c1r4_ab (),
        .c1r4_da ({2'b0, d[31], d[29], d[27], d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], d[9], d[7], d[5], d[3], d[1]}),
        .c1r4_db (),
        .c1r4_q (q3)
);

endmodule