data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:289: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'aurora_201_pcore\'\nmodule aurora_201_pcore #\n       ^~~~~~~~~~~~~~~~\n                                                                                                       : ... Top module \'icon\'\nmodule icon \n       ^~~~\n                                                                                                       : ... Top module \'ila\'\nmodule ila\n       ^~~\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:53: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input   [0:15]     TX_D;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:58: Little bit endian vector: MSB < LSB of bit range: 0:15\n    output  [0:15]     RX_D;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:76: Little bit endian vector: MSB < LSB of bit range: 0:3\n    reg     [0:3]      reset_debounce_r;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:77: Little bit endian vector: MSB < LSB of bit range: 0:3\n    reg     [0:3]      debounce_pma_init_r;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:83: Little bit endian vector: MSB < LSB of bit range: 0:15\n    wire    [0:15]     tx_d_i;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:87: Little bit endian vector: MSB < LSB of bit range: 0:15\n    wire    [0:15]     rx_d_i;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:106: Little bit endian vector: MSB < LSB of bit range: 0:2\n    wire    [0:2]      loopback_i;\n            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:115: Cannot find file containing module: \'IBUFDS\'\n IBUFDS IBUFDS\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS.sv\n             IBUFDS\n             IBUFDS.v\n             IBUFDS.sv\n             obj_dir/IBUFDS\n             obj_dir/IBUFDS.v\n             obj_dir/IBUFDS.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:121: Cannot find file containing module: \'BUFG\'\n BUFG BUFG\n ^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:130: Cannot find file containing module: \'aurora_201_CLOCK_MODULE\'\n    aurora_201_CLOCK_MODULE clock_module_i\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:191: Cannot find file containing module: \'aurora_201\'\n    aurora_201 #\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:231: Cannot find file containing module: \'aurora_201_STANDARD_CC_MODULE\'\n    aurora_201_STANDARD_CC_MODULE standard_cc_module_i\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module icon 
  (
      control0
  );
  output [35:0] control0;
endmodule
module icon 
  (
      control0
  );

  output [35:0] control0;
endmodule