data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc/spi_sram_encoder.v
data/verilator_xmls/f052f44f-c02f-4e89-8c3f-32e6627e0289.xml
function [31:0] max3(input [31:0] x, y, z);
    begin
        max3 = x > y ? (x > z ? x :z) : (y > z ? y : z);
    end
endfunction
function [31:0] max3(input [31:0] x, y, z);

    begin
        max3 = x > y ? (x > z ? x :z) : (y > z ? y : z);
    end
endfunction