data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v
1: b'%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:21: Cannot find include file: svo_defines.vh\n`include "svo_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh.v\n             data/full_repos/permissive/522149450/01.hdmi/src/hdmi,data/full_repos/permissive/522149450/svo_defines.vh.sv\n             svo_defines.vh\n             svo_defines.vh.v\n             svo_defines.vh.sv\n             obj_dir/svo_defines.vh\n             obj_dir/svo_defines.vh.v\n             obj_dir/svo_defines.vh.sv\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:24: Define or directive not defined: \'`SVO_DEFAULT_PARAMS\'\n `SVO_DEFAULT_PARAMS,\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:24: syntax error, unexpected \',\', expecting \'[\'\n `SVO_DEFAULT_PARAMS,\n                    ^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:26: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter MEM_DATA_WIDTH = 64,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:27: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter MEM_BURST_LEN = 8,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:28: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter FIFO_DEPTH = 64\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:29: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:48: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_awvalid,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:57: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_bready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:64: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input             cfg_axi_rready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:69: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [MEM_ADDR_WIDTH-1:0] mem_axi_araddr,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:70: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output     [               7:0] mem_axi_arlen,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:75: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input                           mem_axi_arready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:84: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output                          out_axis_tvalid,\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:93: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input            term_axis_tready,\n ^~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:96: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:97: Define or directive not defined: \'`SVO_DECLS\'\n `SVO_DECLS\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:121: syntax error, unexpected always\n always @(posedge oclk)\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:137: syntax error, unexpected assign\n assign reg_resolution[31:16] = SVO_VER_PIXELS, reg_resolution[15:0] = SVO_HOR_PIXELS;\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:190: syntax error, unexpected assign\n assign mem_axi_arlen = MEM_BURST_LEN-1;\n ^~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:251: syntax error, unexpected IDENTIFIER\n svo_vdma_crossclock_fifo #(\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi/svo_vdma.v:304: syntax error, unexpected always\n always @(posedge oclk) begin\n ^~~~~~\n%Error: Exiting due to 22 error(s)\n'
module svo_vdma_crossclock_fifo #(
	parameter WIDTH = 8,
	parameter DEPTH = 12,
	parameter ABITS = 4
) (
	input                  in_clk,
	input                  in_resetn,
	input                  in_enable,
	input      [WIDTH-1:0] in_data,
	output reg [ABITS-1:0] in_free,

	input                  out_clk,
	input                  out_resetn,
	input                  out_enable,
	output reg [WIDTH-1:0] out_data,
	output reg [ABITS-1:0] out_avail
);
	reg [WIDTH-1:0] fifo [0:DEPTH-1];
	reg [ABITS-1:0] in_ptr, in_ptr_gray;
	reg [ABITS-1:0] out_ptr, out_ptr_gray;

	reg [ABITS-1:0] out_ptr_for_in_clk, in_ptr_for_out_clk;
	reg [ABITS-1:0] sync_in_ptr_0, sync_out_ptr_0;
	reg [ABITS-1:0] sync_in_ptr_1, sync_out_ptr_1;
	reg [ABITS-1:0] sync_in_ptr_2, sync_out_ptr_2;

	function [ABITS-1:0] bin2gray(input [ABITS-1:0] in);
		integer i;
		reg [ABITS:0] temp;
		begin
			temp = in;
			for (i=0; i<ABITS; i=i+1)
				bin2gray[i] = ^temp[i +: 2];
		end
	endfunction

	function [ABITS-1:0] gray2bin(input [ABITS-1:0] in);
		integer i;
		begin
			for (i=0; i<ABITS; i=i+1)
				gray2bin[i] = ^(in >> i);
		end
	endfunction

	always @(posedge in_clk) begin
		if (!in_resetn) begin
			in_ptr <= 0;
			in_ptr_gray <= 0;
		end else begin
			if (in_enable) begin
				fifo[in_ptr] <= in_data;
				in_ptr <= in_ptr + 1'b1;
				in_ptr_gray <= bin2gray(in_ptr + 1'b1);
			end
		end

		sync_out_ptr_0 <= out_ptr_gray;
		sync_out_ptr_1 <= sync_out_ptr_0;
		sync_out_ptr_2 <= sync_out_ptr_1;
		out_ptr_for_in_clk <= gray2bin(sync_out_ptr_2);

		in_free <= DEPTH - in_ptr + out_ptr_for_in_clk - 1;
	end

	always @(posedge out_clk) begin
		if (!out_resetn) begin
			out_ptr <= 0;
			out_ptr_gray <= 0;
		end else begin
			if (out_enable) begin
				out_ptr <= out_ptr + 1'b1;
				out_ptr_gray <= bin2gray(out_ptr + 1'b1);
				out_data <= fifo[out_ptr + 1'b1];
			end else
				out_data <= fifo[out_ptr];
		end

		sync_in_ptr_0 <= in_ptr_gray;
		sync_in_ptr_1 <= sync_in_ptr_0;
		sync_in_ptr_2 <= sync_in_ptr_1;
		in_ptr_for_out_clk <= gray2bin(sync_in_ptr_2);

		out_avail <= in_ptr_for_out_clk - out_ptr;
	end
endmodule
module svo_vdma_crossclock_fifo #(
	parameter WIDTH = 8,
	parameter DEPTH = 12,
	parameter ABITS = 4
) (
	input                  in_clk,
	input                  in_resetn,
	input                  in_enable,
	input      [WIDTH-1:0] in_data,
	output reg [ABITS-1:0] in_free,

	input                  out_clk,
	input                  out_resetn,
	input                  out_enable,
	output reg [WIDTH-1:0] out_data,
	output reg [ABITS-1:0] out_avail
);

	reg [WIDTH-1:0] fifo [0:DEPTH-1];
	reg [ABITS-1:0] in_ptr, in_ptr_gray;
	reg [ABITS-1:0] out_ptr, out_ptr_gray;

	reg [ABITS-1:0] out_ptr_for_in_clk, in_ptr_for_out_clk;
	reg [ABITS-1:0] sync_in_ptr_0, sync_out_ptr_0;
	reg [ABITS-1:0] sync_in_ptr_1, sync_out_ptr_1;
	reg [ABITS-1:0] sync_in_ptr_2, sync_out_ptr_2;

	function [ABITS-1:0] bin2gray(input [ABITS-1:0] in);
		integer i;
		reg [ABITS:0] temp;
		begin
			temp = in;
			for (i=0; i<ABITS; i=i+1)
				bin2gray[i] = ^temp[i +: 2];
		end
	endfunction

	function [ABITS-1:0] gray2bin(input [ABITS-1:0] in);
		integer i;
		begin
			for (i=0; i<ABITS; i=i+1)
				gray2bin[i] = ^(in >> i);
		end
	endfunction

	always @(posedge in_clk) begin
		if (!in_resetn) begin
			in_ptr <= 0;
			in_ptr_gray <= 0;
		end else begin
			if (in_enable) begin
				fifo[in_ptr] <= in_data;
				in_ptr <= in_ptr + 1'b1;
				in_ptr_gray <= bin2gray(in_ptr + 1'b1);
			end
		end

		sync_out_ptr_0 <= out_ptr_gray;
		sync_out_ptr_1 <= sync_out_ptr_0;
		sync_out_ptr_2 <= sync_out_ptr_1;
		out_ptr_for_in_clk <= gray2bin(sync_out_ptr_2);

		in_free <= DEPTH - in_ptr + out_ptr_for_in_clk - 1;
	end

	always @(posedge out_clk) begin
		if (!out_resetn) begin
			out_ptr <= 0;
			out_ptr_gray <= 0;
		end else begin
			if (out_enable) begin
				out_ptr <= out_ptr + 1'b1;
				out_ptr_gray <= bin2gray(out_ptr + 1'b1);
				out_data <= fifo[out_ptr + 1'b1];
			end else
				out_data <= fifo[out_ptr];
		end

		sync_in_ptr_0 <= in_ptr_gray;
		sync_in_ptr_1 <= sync_in_ptr_0;
		sync_in_ptr_2 <= sync_in_ptr_1;
		in_ptr_for_out_clk <= gray2bin(sync_in_ptr_2);

		out_avail <= in_ptr_for_out_clk - out_ptr;
	end
endmodule