data/full_repos/permissive/477054115/iitb-risc/ctrlUnit.v
data/verilator_xmls/4de53aad-8eb8-472e-998f-eaa678268917.xml
module control_decoder (opcode, ir_lsb_2, RR_A1_Address_sel, RR_A2_Address_sel, RR_A3_Address_sel, RR_Wr_En, 
						EXE_ALU_Src, EXE_ALU_Oper, Reg_D3_Sel, MEM_Wr_En, pc_data_select);

input [3:0] opcode;
input [1:0] ir_lsb_2;


output reg RR_A1_Address_sel, RR_A2_Address_sel, RR_Wr_En, MEM_Wr_En, pc_data_select;
output reg [1:0] RR_A3_Address_sel, EXE_ALU_Oper, Reg_D3_Sel, EXE_ALU_Src;

always @(*) begin
    case (opcode)
		4'b0001: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			if ( ir_lsb_2 == 2'b11)
				EXE_ALU_Src = 2'b10;
			else
				EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0;
		end		
		4'b0000: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b01;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;                           
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0; 
		end
		4'b0010: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b01;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0;
		end	
		4'b0011: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b10;
			EXE_ALU_Oper = 2'b10;
			Reg_D3_Sel = 2'b10;
			MEM_Wr_En = 1'b0;
		end
		4'b0100: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b0;
		end
		4'b0101: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1; 
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b1;
		end
		4'b1001: begin
			RR_A1_Address_sel = 1'b1 ;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			EXE_ALU_Src = 2'b00;
			pc_data_select = 1'b1;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00; 
			MEM_Wr_En = 1'b0;
		end
		4'b1010 : begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b0; 
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			EXE_ALU_Src = 2'b00;
			pc_data_select = 1'b1;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00; 
			MEM_Wr_En = 1'b0;
		end
		4'b1110, 4'b1100: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b0;
		end
		4'b1111, 4'b1101: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b1;
		end

		default: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
		    EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0; 
		end
	endcase
end

endmodule
module control_decoder (opcode, ir_lsb_2, RR_A1_Address_sel, RR_A2_Address_sel, RR_A3_Address_sel, RR_Wr_En, 
						EXE_ALU_Src, EXE_ALU_Oper, Reg_D3_Sel, MEM_Wr_En, pc_data_select);


input [3:0] opcode;
input [1:0] ir_lsb_2;


output reg RR_A1_Address_sel, RR_A2_Address_sel, RR_Wr_En, MEM_Wr_En, pc_data_select;
output reg [1:0] RR_A3_Address_sel, EXE_ALU_Oper, Reg_D3_Sel, EXE_ALU_Src;

always @(*) begin
    case (opcode)
		4'b0001: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			if ( ir_lsb_2 == 2'b11)
				EXE_ALU_Src = 2'b10;
			else
				EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0;
		end		
		4'b0000: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b01;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;                           
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0; 
		end
		4'b0010: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b01;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0;
		end	
		4'b0011: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b10;
			EXE_ALU_Oper = 2'b10;
			Reg_D3_Sel = 2'b10;
			MEM_Wr_En = 1'b0;
		end
		4'b0100: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b0;
		end
		4'b0101: begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b1; 
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b1;
		end
		4'b1001: begin
			RR_A1_Address_sel = 1'b1 ;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			EXE_ALU_Src = 2'b00;
			pc_data_select = 1'b1;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00; 
			MEM_Wr_En = 1'b0;
		end
		4'b1010 : begin
			RR_A1_Address_sel = 1'b1;
			RR_A2_Address_sel = 1'b0; 
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			EXE_ALU_Src = 2'b00;
			pc_data_select = 1'b1;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00; 
			MEM_Wr_En = 1'b0;
		end
		4'b1110, 4'b1100: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b1;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b0;
		end
		4'b1111, 4'b1101: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b1;
			RR_A3_Address_sel = 2'b00;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
			EXE_ALU_Src = 2'b01;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b01;
			MEM_Wr_En = 1'b1;
		end

		default: begin
			RR_A1_Address_sel = 1'b0;
			RR_A2_Address_sel = 1'b0;
			RR_A3_Address_sel = 2'b10;
			RR_Wr_En = 1'b0;
			pc_data_select = 1'b0;
		    EXE_ALU_Src = 2'b00;
			EXE_ALU_Oper = 2'b00;
			Reg_D3_Sel = 2'b00;
			MEM_Wr_En = 1'b0; 
		end
	endcase
end

endmodule