data/full_repos/permissive/502544928/tb_Real_Cores_Mesh_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502544928/tb_Real_Cores_Mesh_top.v:43: Unsupported: Ignoring delay on this delayed statement.\nalways #1 Bus2IP_Clk = ~Bus2IP_Clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502544928/tb_Real_Cores_Mesh_top.v:54: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge Bus2IP_Clk);\n             ^\n%Error: data/full_repos/permissive/502544928/tb_Real_Cores_Mesh_top.v:57: syntax error, unexpected \'@\'\n  repeat (10) @ (posedge Bus2IP_Clk);\n              ^\n%Error: data/full_repos/permissive/502544928/tb_Real_Cores_Mesh_top.v:60: syntax error, unexpected \'@\'\n  repeat (300) @ (posedge Bus2IP_Clk);\n               ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_Real_Cores_Mesh_top (
); 

    
wire [31: 0] data; 
wire valid;
reg cmd; 
reg Bus2IP_Reset;
reg Bus2IP_Clk; 
integer outfile3,outfile2,outfile1,outfile0,dBlockCache0,i,grantFile;     
wire [14:0] req_ports; 
assign output0 = data[0];

 parameter cacheLines=12  ;

Real_Cores_Mesh_Wrapper TB_M(.clock(Bus2IP_Clk), .RST(Bus2IP_Reset), .cmd(cmd), .data(data), .valid(valid));  
  

always #1 Bus2IP_Clk = ~Bus2IP_Clk;

initial begin
   grantFile=$fopen("grantFile.txt","w");
 outfile0=$fopen("regfile0.txt","w");
 outfile1=$fopen("regfile1.txt","w");
  outfile2=$fopen("regfile2.txt","w");
 outfile3=$fopen("regfile3.txt","w");
  $display (" --- Start --- ");
  Bus2IP_Clk <= 0; 
  Bus2IP_Reset <= 1; 
  repeat (1) @ (posedge Bus2IP_Clk);
  Bus2IP_Reset <= 0; 
  cmd <= 0;
  repeat (10) @ (posedge Bus2IP_Clk);
  
  cmd <= 1;
  repeat (300) @ (posedge Bus2IP_Clk);

  
end

reg [31:0] counter=0;
always  @(posedge Bus2IP_Clk)
counter=counter+1;

always  @(posedge Bus2IP_Clk)
begin
showRequestAndGrantsStatus;
 if (counter==7500) begin
saveCacheBlocksContents;
$fclose(grantFile);
$stop;
end
end


always @ (posedge Bus2IP_Clk)
  if(valid) 
begin
  $display ("Data [%h]", data);
    saveImemContents;
	if (data==0)
	begin
	saveCacheBlocksContents;
$fclose(grantFile);
	$stop;
	end
end  


task saveImemContents; begin


  




  end
  endtask  

always@(posedge Bus2IP_Clk) begin


      













	end

  always@(posedge Bus2IP_Clk) begin


      













	end

  always@(posedge Bus2IP_Clk) begin


      













	end
  

  always@(posedge Bus2IP_Clk) begin


      













	end
  
  task saveCacheBlocksContents; begin 
  dBlockCache0=$fopen("dBlockCache0.txt","w");
  for (i=0;i<2**cacheLines;i=i+1) begin
$fdisplay(dBlockCache0,"#block7=%d -#block6=%d -#block5=%d -#block4=%d -#block3=%d -#block2=%d - #block1=%d - #block0=%d -",
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][255:224],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][223:192],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][191:160],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][159:128],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][127:96],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][95:64],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][63:32],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][31:0]
);
end
$fclose(dBlockCache0);
  end
  endtask 
 


task showRequestAndGrantsStatus; begin



  end
  endtask    
  
  
  
  endmodule
module tb_Real_Cores_Mesh_top (
);
 

    
wire [31: 0] data; 
wire valid;
reg cmd; 
reg Bus2IP_Reset;
reg Bus2IP_Clk; 
integer outfile3,outfile2,outfile1,outfile0,dBlockCache0,i,grantFile;     
wire [14:0] req_ports; 
assign output0 = data[0];

 parameter cacheLines=12  ;

Real_Cores_Mesh_Wrapper TB_M(.clock(Bus2IP_Clk), .RST(Bus2IP_Reset), .cmd(cmd), .data(data), .valid(valid));  
  

always #1 Bus2IP_Clk = ~Bus2IP_Clk;

initial begin
   grantFile=$fopen("grantFile.txt","w");
 outfile0=$fopen("regfile0.txt","w");
 outfile1=$fopen("regfile1.txt","w");
  outfile2=$fopen("regfile2.txt","w");
 outfile3=$fopen("regfile3.txt","w");
  $display (" --- Start --- ");
  Bus2IP_Clk <= 0; 
  Bus2IP_Reset <= 1; 
  repeat (1) @ (posedge Bus2IP_Clk);
  Bus2IP_Reset <= 0; 
  cmd <= 0;
  repeat (10) @ (posedge Bus2IP_Clk);
  
  cmd <= 1;
  repeat (300) @ (posedge Bus2IP_Clk);

  
end

reg [31:0] counter=0;
always  @(posedge Bus2IP_Clk)
counter=counter+1;

always  @(posedge Bus2IP_Clk)
begin
showRequestAndGrantsStatus;
 if (counter==7500) begin
saveCacheBlocksContents;
$fclose(grantFile);
$stop;
end
end


always @ (posedge Bus2IP_Clk)
  if(valid) 
begin
  $display ("Data [%h]", data);
    saveImemContents;
	if (data==0)
	begin
	saveCacheBlocksContents;
$fclose(grantFile);
	$stop;
	end
end  


task saveImemContents; begin


  




  end
  endtask  

always@(posedge Bus2IP_Clk) begin


      













	end

  always@(posedge Bus2IP_Clk) begin


      













	end

  always@(posedge Bus2IP_Clk) begin


      













	end
  

  always@(posedge Bus2IP_Clk) begin


      













	end
  
  task saveCacheBlocksContents; begin 
  dBlockCache0=$fopen("dBlockCache0.txt","w");
  for (i=0;i<2**cacheLines;i=i+1) begin
$fdisplay(dBlockCache0,"#block7=%d -#block6=%d -#block5=%d -#block4=%d -#block3=%d -#block2=%d - #block1=%d - #block0=%d -",
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][255:224],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][223:192],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][191:160],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][159:128],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][127:96],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][95:64],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][63:32],
tb_Real_Cores_Mesh_top.TB_M.U.MESH_NODE1[4].NODES.memory_sub_system.mem_packetizer.unified.DCache.CACHE.CACHE_RAM.ram[i][31:0]
);
end
$fclose(dBlockCache0);
  end
  endtask 
 


task showRequestAndGrantsStatus; begin



  end
  endtask    
  
  
  
  endmodule