data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:518: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:518: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:519: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:519: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:520: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:520: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_acc_block_k2n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:360: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k0_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:360: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k0_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:361: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k1_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:361: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k1_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:362: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k0_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add1_k0_st2 <= sqr_k0_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k2n3_top.v:363: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k1_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k2n3_top.kmeans_pipeline_k2_d3\n    add1_k1_st2 <= sqr_k1_d2_st1;\n                ^~\n%Error: Exiting due to 12 warning(s)\n'
module RAM #
(
  parameter read_f = 0,
  parameter init_file = "mem_file.txt",
  parameter write_f = 0,
  parameter output_file = "mem_out_file.txt",
  parameter depth = 8,
  parameter width = 16
)
(
  input clk,
  input [depth-1:0] rd_addr,
  output [width-1:0] out,
  input wr,
  input [depth-1:0] wr_addr,
  input [width-1:0] wr_data
);

  reg [width-1:0] mem [0:2**depth-1];
  assign out = mem[rd_addr];

  always @(posedge clk) begin
    if(wr) begin
      mem[wr_addr] <= wr_data;
    end 
  end



  always @(posedge clk) begin
    if(wr && write_f) begin
      $writememh(output_file, mem);
    end 
  end


  initial begin
    if(read_f) begin
      $readmemh(init_file, mem);
    end 
  end



endmodule
module RAM #
(
  parameter read_f = 0,
  parameter init_file = "mem_file.txt",
  parameter write_f = 0,
  parameter output_file = "mem_out_file.txt",
  parameter depth = 8,
  parameter width = 16
)
(
  input clk,
  input [depth-1:0] rd_addr,
  output [width-1:0] out,
  input wr,
  input [depth-1:0] wr_addr,
  input [width-1:0] wr_data
);


  reg [width-1:0] mem [0:2**depth-1];
  assign out = mem[rd_addr];

  always @(posedge clk) begin
    if(wr) begin
      mem[wr_addr] <= wr_data;
    end 
  end



  always @(posedge clk) begin
    if(wr && write_f) begin
      $writememh(output_file, mem);
    end 
  end


  initial begin
    if(read_f) begin
      $readmemh(init_file, mem);
    end 
  end



endmodule