data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/common_cells/src/stream_demux.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/common_cells/src/stream_demux.sv:25: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic  [LOG_N_OUP-1:0] oup_sel_i,\n                ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/common_cells/src/stream_demux.sv:33: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                                                                                         : ... In instance stream_demux\n    oup_valid_o[oup_sel_i] = inp_valid_i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/common_cells/src/stream_demux.sv:35: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                                                                                         : ... In instance stream_demux\n  assign inp_ready_o = oup_ready_i[oup_sel_i];\n                                  ^\n%Error: Exiting due to 3 warning(s)\n'
module stream_demux #(
  parameter integer N_OUP = 1,

  parameter integer LOG_N_OUP = $clog2(N_OUP)
) (
  input  logic                  inp_valid_i,
  output logic                  inp_ready_o,

  input  logic  [LOG_N_OUP-1:0] oup_sel_i,

  output logic  [N_OUP-1:0]     oup_valid_o,
  input  logic  [N_OUP-1:0]     oup_ready_i
);

  always_comb begin
    oup_valid_o = '0;
    oup_valid_o[oup_sel_i] = inp_valid_i;
  end
  assign inp_ready_o = oup_ready_i[oup_sel_i];

endmodule
module stream_demux #(
  parameter integer N_OUP = 1,

  parameter integer LOG_N_OUP = $clog2(N_OUP)
) (
  input  logic                  inp_valid_i,
  output logic                  inp_ready_o,

  input  logic  [LOG_N_OUP-1:0] oup_sel_i,

  output logic  [N_OUP-1:0]     oup_valid_o,
  input  logic  [N_OUP-1:0]     oup_ready_i
);


  always_comb begin
    oup_valid_o = '0;
    oup_valid_o[oup_sel_i] = inp_valid_i;
  end
  assign inp_ready_o = oup_ready_i[oup_sel_i];

endmodule