data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v:52: Can't resolve module reference: 'sky130_fd_sc_hd__dlxtp_1'\n    sky130_fd_sc_hd__dlxtp_1 mode_lat_i (\n                             ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module buffer_chain_341353780122485332 ((* dont_touch *) input A, (* dont_touch *) output X);

    localparam N = 3;

    (* dont_touch *) wire [N:0] c;
    assign c[0] = A;
    assign X = c[N];

    generate
        genvar ii;
        for (ii = 1'b0; ii < N; ii = ii + 1'b1) begin : bufs
            (* keep, dont_touch *) sky130_fd_sc_hd__clkdlybuf4s50_1 buf_i (.A(c[ii]), .X(c[ii + 1'b1]), .VPWR(1'b1), .VGND(1'b0));
        end
    endgenerate

endmodule
module buffer_chain_341353780122485332 ((* dont_touch *) input A, (* dont_touch *) output X);


    localparam N = 3;

    (* dont_touch *) wire [N:0] c;
    assign c[0] = A;
    assign X = c[N];

    generate
        genvar ii;
        for (ii = 1'b0; ii < N; ii = ii + 1'b1) begin : bufs
            (* keep, dont_touch *) sky130_fd_sc_hd__clkdlybuf4s50_1 buf_i (.A(c[ii]), .X(c[ii + 1'b1]), .VPWR(1'b1), .VGND(1'b0));
        end
    endgenerate

endmodule