data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_crossbar_v1_0_0/hdl/verilog/input_queues.v
1: b"%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_crossbar_v1_0_0/hdl/verilog/input_queues.v:136: Cannot find file containing module: 'fallthrough_small_fifo'\n      fallthrough_small_fifo\n      ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_crossbar_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/fallthrough_small_fifo\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_crossbar_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/fallthrough_small_fifo.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_crossbar_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/fallthrough_small_fifo.sv\n             fallthrough_small_fifo\n             fallthrough_small_fifo.v\n             fallthrough_small_fifo.sv\n             obj_dir/fallthrough_small_fifo\n             obj_dir/fallthrough_small_fifo.v\n             obj_dir/fallthrough_small_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module input_queues
#(

    parameter C_M_AXIS_DATA_WIDTH=256,
    parameter C_S_AXIS_DATA_WIDTH=256,
    parameter C_M_AXIS_TUSER_WIDTH=128,
    parameter C_S_AXIS_TUSER_WIDTH=128,
    parameter NUM_QUEUES=5
)
(


    input axi_aclk,
    input axi_resetn,


    output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
    output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tstrb,
    output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
    output m_axis_tvalid,
    input  m_axis_tready,
    output m_axis_tlast,


    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_0,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_0,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_0,
    input  s_axis_tvalid_0,
    output s_axis_tready_0,
    input  s_axis_tlast_0,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_1,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_1,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_1,
    input  s_axis_tvalid_1,
    output s_axis_tready_1,
    input  s_axis_tlast_1,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_2,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_2,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_2,
    input  s_axis_tvalid_2,
    output s_axis_tready_2,
    input  s_axis_tlast_2,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_3,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_3,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_3,
    input  s_axis_tvalid_3,
    output s_axis_tready_3,
    input  s_axis_tlast_3,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_4,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_4,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_4,
    input  s_axis_tvalid_4,
    output s_axis_tready_4,
    input  s_axis_tlast_4
);

function integer log2;
   input integer number;
   begin
      log2=0;
      while(2**log2<number) begin
         log2=log2+1;
      end
   end
endfunction


parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES);
parameter NUM_STATES = 1;
parameter IDLE = 0;
parameter WR_PKT = 1;

localparam MAX_PKT_SIZE = 2048;
localparam IN_FIFO_DEPTH_BIT = log2(MAX_PKT_SIZE/(C_M_AXIS_DATA_WIDTH/8));


wire [NUM_QUEUES-1:0]                  nearly_full;
wire [NUM_QUEUES-1:0]                  empty;
wire [C_M_AXIS_DATA_WIDTH-1:0]         in_tdata[NUM_QUEUES-1:0];
wire [((C_M_AXIS_DATA_WIDTH/8))-1:0]   in_tstrb[NUM_QUEUES-1:0];
wire [C_M_AXIS_TUSER_WIDTH-1:0]        in_tuser[NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] 	               in_tvalid;
wire [NUM_QUEUES-1:0]                  in_tlast;
wire [C_M_AXIS_TUSER_WIDTH-1:0]        fifo_out_tuser[NUM_QUEUES-1:0];
wire [C_M_AXIS_DATA_WIDTH-1:0]         fifo_out_tdata[NUM_QUEUES-1:0];
wire [((C_M_AXIS_DATA_WIDTH/8))-1:0]   fifo_out_tstrb[NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] 	               fifo_out_tlast;
wire                                   fifo_tvalid;
wire                                   fifo_tlast;

reg [NUM_QUEUES-1:0]                   rd_en;
reg [NUM_QUEUES_WIDTH-1:0]             cur_queue, cur_queue_next;
reg [NUM_STATES-1:0]                   state;
reg [NUM_STATES-1:0]                   state_next;


generate
   genvar i;
   for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues
      fallthrough_small_fifo
      #(
         .WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1),
         .MAX_DEPTH_BITS(IN_FIFO_DEPTH_BIT)
      )
      in_arb_fifo
      (

      .dout          (  {fifo_out_tlast[i], fifo_out_tuser[i], fifo_out_tstrb[i], fifo_out_tdata[i]}),
      .full          (),
      .nearly_full   (  nearly_full[i]),
      .prog_full     (),
      .empty         (  empty[i]),

      .din           (  {in_tlast[i], in_tuser[i], in_tstrb[i], in_tdata[i]}),
      .wr_en         (  in_tvalid[i] & ~nearly_full[i]),
      .rd_en         (  rd_en[i]),
      .reset         (  ~axi_resetn),
      .clk           (  axi_aclk));
   end
endgenerate


assign in_tdata[0]        = s_axis_tdata_0;
assign in_tstrb[0]        = s_axis_tstrb_0;
assign in_tuser[0]        = s_axis_tuser_0;
assign in_tvalid[0]       = s_axis_tvalid_0;
assign in_tlast[0]        = s_axis_tlast_0;
assign s_axis_tready_0    = !nearly_full[0];

assign in_tdata[1]        = s_axis_tdata_1;
assign in_tstrb[1]        = s_axis_tstrb_1;
assign in_tuser[1]        = s_axis_tuser_1;
assign in_tvalid[1]       = s_axis_tvalid_1;
assign in_tlast[1]        = s_axis_tlast_1;
assign s_axis_tready_1    = !nearly_full[1];

assign in_tdata[2]        = s_axis_tdata_2;
assign in_tstrb[2]        = s_axis_tstrb_2;
assign in_tuser[2]        = s_axis_tuser_2;
assign in_tvalid[2]       = s_axis_tvalid_2;
assign in_tlast[2]        = s_axis_tlast_2;
assign s_axis_tready_2    = !nearly_full[2];

assign in_tdata[3]        = s_axis_tdata_3;
assign in_tstrb[3]        = s_axis_tstrb_3;
assign in_tuser[3]        = s_axis_tuser_3;
assign in_tvalid[3]       = s_axis_tvalid_3;
assign in_tlast[3]        = s_axis_tlast_3;
assign s_axis_tready_3    = !nearly_full[3];

assign in_tdata[4]        = s_axis_tdata_4;
assign in_tstrb[4]        = s_axis_tstrb_4;
assign in_tuser[4]        = s_axis_tuser_4;
assign in_tvalid[4]       = s_axis_tvalid_4;
assign in_tlast[4]        = s_axis_tlast_4;
assign s_axis_tready_4    = !nearly_full[4];

assign m_axis_tuser = fifo_out_tuser[cur_queue];
assign m_axis_tdata = fifo_out_tdata[cur_queue];
assign m_axis_tlast = fifo_out_tlast[cur_queue];
assign m_axis_tstrb = fifo_out_tstrb[cur_queue];
assign m_axis_tvalid = ~empty[cur_queue];

always @(*) begin
   state_next      = 0;
   rd_en           = 0;
   cur_queue_next  = cur_queue;
   case(state)
      IDLE: begin
         if (m_axis_tready & ~empty[cur_queue]) begin
            state_next = WR_PKT;
            rd_en[cur_queue] = 1;
         end
         else begin
            state_next = IDLE;
            cur_queue_next   = (cur_queue == NUM_QUEUES-1) ? 0 : cur_queue + 1;
         end
      end
      WR_PKT: begin
         if (m_axis_tready & m_axis_tlast) begin
            state_next = IDLE;
            rd_en[cur_queue] = 1;
            cur_queue_next    = (cur_queue == NUM_QUEUES-1) ? 0 : cur_queue + 1;
         end
         else begin
            rd_en[cur_queue] = (m_axis_tready & ~empty[cur_queue]);
            state_next = WR_PKT;
         end
      end
   endcase
end

always @(posedge axi_aclk)
   if(~axi_resetn) begin
      state       <= IDLE;
      cur_queue   <= 0;
   end
   else begin
      state       <= state_next;
      cur_queue   <= cur_queue_next;
   end

endmodule
module input_queues
#(

    parameter C_M_AXIS_DATA_WIDTH=256,
    parameter C_S_AXIS_DATA_WIDTH=256,
    parameter C_M_AXIS_TUSER_WIDTH=128,
    parameter C_S_AXIS_TUSER_WIDTH=128,
    parameter NUM_QUEUES=5
)
(


    input axi_aclk,
    input axi_resetn,


    output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
    output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tstrb,
    output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
    output m_axis_tvalid,
    input  m_axis_tready,
    output m_axis_tlast,


    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_0,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_0,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_0,
    input  s_axis_tvalid_0,
    output s_axis_tready_0,
    input  s_axis_tlast_0,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_1,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_1,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_1,
    input  s_axis_tvalid_1,
    output s_axis_tready_1,
    input  s_axis_tlast_1,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_2,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_2,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_2,
    input  s_axis_tvalid_2,
    output s_axis_tready_2,
    input  s_axis_tlast_2,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_3,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_3,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_3,
    input  s_axis_tvalid_3,
    output s_axis_tready_3,
    input  s_axis_tlast_3,

    input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_4,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_4,
    input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser_4,
    input  s_axis_tvalid_4,
    output s_axis_tready_4,
    input  s_axis_tlast_4
);


function integer log2;
   input integer number;
   begin
      log2=0;
      while(2**log2<number) begin
         log2=log2+1;
      end
   end
endfunction


parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES);
parameter NUM_STATES = 1;
parameter IDLE = 0;
parameter WR_PKT = 1;

localparam MAX_PKT_SIZE = 2048;
localparam IN_FIFO_DEPTH_BIT = log2(MAX_PKT_SIZE/(C_M_AXIS_DATA_WIDTH/8));


wire [NUM_QUEUES-1:0]                  nearly_full;
wire [NUM_QUEUES-1:0]                  empty;
wire [C_M_AXIS_DATA_WIDTH-1:0]         in_tdata[NUM_QUEUES-1:0];
wire [((C_M_AXIS_DATA_WIDTH/8))-1:0]   in_tstrb[NUM_QUEUES-1:0];
wire [C_M_AXIS_TUSER_WIDTH-1:0]        in_tuser[NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] 	               in_tvalid;
wire [NUM_QUEUES-1:0]                  in_tlast;
wire [C_M_AXIS_TUSER_WIDTH-1:0]        fifo_out_tuser[NUM_QUEUES-1:0];
wire [C_M_AXIS_DATA_WIDTH-1:0]         fifo_out_tdata[NUM_QUEUES-1:0];
wire [((C_M_AXIS_DATA_WIDTH/8))-1:0]   fifo_out_tstrb[NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] 	               fifo_out_tlast;
wire                                   fifo_tvalid;
wire                                   fifo_tlast;

reg [NUM_QUEUES-1:0]                   rd_en;
reg [NUM_QUEUES_WIDTH-1:0]             cur_queue, cur_queue_next;
reg [NUM_STATES-1:0]                   state;
reg [NUM_STATES-1:0]                   state_next;


generate
   genvar i;
   for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues
      fallthrough_small_fifo
      #(
         .WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1),
         .MAX_DEPTH_BITS(IN_FIFO_DEPTH_BIT)
      )
      in_arb_fifo
      (

      .dout          (  {fifo_out_tlast[i], fifo_out_tuser[i], fifo_out_tstrb[i], fifo_out_tdata[i]}),
      .full          (),
      .nearly_full   (  nearly_full[i]),
      .prog_full     (),
      .empty         (  empty[i]),

      .din           (  {in_tlast[i], in_tuser[i], in_tstrb[i], in_tdata[i]}),
      .wr_en         (  in_tvalid[i] & ~nearly_full[i]),
      .rd_en         (  rd_en[i]),
      .reset         (  ~axi_resetn),
      .clk           (  axi_aclk));
   end
endgenerate


assign in_tdata[0]        = s_axis_tdata_0;
assign in_tstrb[0]        = s_axis_tstrb_0;
assign in_tuser[0]        = s_axis_tuser_0;
assign in_tvalid[0]       = s_axis_tvalid_0;
assign in_tlast[0]        = s_axis_tlast_0;
assign s_axis_tready_0    = !nearly_full[0];

assign in_tdata[1]        = s_axis_tdata_1;
assign in_tstrb[1]        = s_axis_tstrb_1;
assign in_tuser[1]        = s_axis_tuser_1;
assign in_tvalid[1]       = s_axis_tvalid_1;
assign in_tlast[1]        = s_axis_tlast_1;
assign s_axis_tready_1    = !nearly_full[1];

assign in_tdata[2]        = s_axis_tdata_2;
assign in_tstrb[2]        = s_axis_tstrb_2;
assign in_tuser[2]        = s_axis_tuser_2;
assign in_tvalid[2]       = s_axis_tvalid_2;
assign in_tlast[2]        = s_axis_tlast_2;
assign s_axis_tready_2    = !nearly_full[2];

assign in_tdata[3]        = s_axis_tdata_3;
assign in_tstrb[3]        = s_axis_tstrb_3;
assign in_tuser[3]        = s_axis_tuser_3;
assign in_tvalid[3]       = s_axis_tvalid_3;
assign in_tlast[3]        = s_axis_tlast_3;
assign s_axis_tready_3    = !nearly_full[3];

assign in_tdata[4]        = s_axis_tdata_4;
assign in_tstrb[4]        = s_axis_tstrb_4;
assign in_tuser[4]        = s_axis_tuser_4;
assign in_tvalid[4]       = s_axis_tvalid_4;
assign in_tlast[4]        = s_axis_tlast_4;
assign s_axis_tready_4    = !nearly_full[4];

assign m_axis_tuser = fifo_out_tuser[cur_queue];
assign m_axis_tdata = fifo_out_tdata[cur_queue];
assign m_axis_tlast = fifo_out_tlast[cur_queue];
assign m_axis_tstrb = fifo_out_tstrb[cur_queue];
assign m_axis_tvalid = ~empty[cur_queue];

always @(*) begin
   state_next      = 0;
   rd_en           = 0;
   cur_queue_next  = cur_queue;
   case(state)
      IDLE: begin
         if (m_axis_tready & ~empty[cur_queue]) begin
            state_next = WR_PKT;
            rd_en[cur_queue] = 1;
         end
         else begin
            state_next = IDLE;
            cur_queue_next   = (cur_queue == NUM_QUEUES-1) ? 0 : cur_queue + 1;
         end
      end
      WR_PKT: begin
         if (m_axis_tready & m_axis_tlast) begin
            state_next = IDLE;
            rd_en[cur_queue] = 1;
            cur_queue_next    = (cur_queue == NUM_QUEUES-1) ? 0 : cur_queue + 1;
         end
         else begin
            rd_en[cur_queue] = (m_axis_tready & ~empty[cur_queue]);
            state_next = WR_PKT;
         end
      end
   endcase
end

always @(posedge axi_aclk)
   if(~axi_resetn) begin
      state       <= IDLE;
      cur_queue   <= 0;
   end
   else begin
      state       <= state_next;
      cur_queue   <= cur_queue_next;
   end

endmodule