data/full_repos/permissive/468066752/rtl/LCD.sv
data/verilator_xmls/d5dd6d82-ae9f-409d-bc75-70332de1e2f9.xml
module LCD #(
    parameter int BASEADDRESS = 32'h5000_0000

) (
    input logic         ACLK,
    input logic         RESET,
    input logic [31:00] DATA_I,
    input logic [31:00] ADDR,
    input logic         WRSTB,


    output logic              LCD_BLON,
    inout  wire logic [07:00] LCD_DATA,
    output logic              LCD_EN,
    output logic              LCD_ON,
    output logic              LCD_RS,
    output logic              LCD_RW
);

  logic [07:00] data;

  logic         enable;

  logic         rs;

  logic         we;

  logic [16:00] counter;

  typedef enum bit [1:0] {
    IDLE,
    SEND_COMMAND,
    SEND_DATA,
    DELAY
  } state;
  state currState, nextState;


  assign LCD_BLON = 1'b1;

  assign LCD_ON   = 1'b1;

  assign LCD_RW   = 1'b0;

  assign LCD_DATA = data;

  assign LCD_EN   = enable;

  assign LCD_RS   = rs;




  always_ff @(posedge ACLK or posedge RESET) begin : currStateRegs
    if (RESET == 1) begin
      currState <= IDLE;
    end else begin
      currState <= nextState;
    end
  end : currStateRegs


  always_comb begin : nextStateLogic
    nextState = currState;
    we = 0;
    case (currState)
      IDLE: begin
        if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR <= BASEADDRESS + 1)) begin
          we = 1;
          if (ADDR[0] == 1'b0) begin
            nextState = SEND_COMMAND;
          end else begin
            nextState = SEND_DATA;
          end
        end
      end
      SEND_COMMAND: begin
        nextState = DELAY;
      end
      SEND_DATA: begin
        nextState = DELAY;
      end
      DELAY: begin
        if (counter == 'd0) begin
          nextState = IDLE;
        end else begin
          nextState = DELAY;
        end
      end
      default: begin
        nextState = IDLE;
      end
    endcase
  end : nextStateLogic


  always_ff @(posedge ACLK or posedge RESET) begin : regsUpdate
    if (RESET == 1) begin
      data    <= 8'd0;
      enable  <= 1'd0;
      rs      <= 1'd0;
      counter <= 17'd0;
    end else begin
      if (we == 1'b1) begin
        data <= DATA_I[07:00];
      end
      if (currState == SEND_COMMAND || currState == SEND_DATA || currState == DELAY) begin
        enable <= 1'b1;
      end else begin
        enable <= 1'b0;
      end
      if (currState == SEND_COMMAND) begin
        rs <= 1'd0;
      end else if (currState == SEND_DATA) begin
        rs <= 1'd1;
      end
      if (currState == SEND_COMMAND || currState == SEND_DATA) begin
        counter <= 17'd100000;
      end else if (currState == DELAY) begin
        counter <= counter - 17'd1;
      end
    end
  end : regsUpdate

endmodule
module LCD #(
    parameter int BASEADDRESS = 32'h5000_0000

) (
    input logic         ACLK,
    input logic         RESET,
    input logic [31:00] DATA_I,
    input logic [31:00] ADDR,
    input logic         WRSTB,


    output logic              LCD_BLON,
    inout  wire logic [07:00] LCD_DATA,
    output logic              LCD_EN,
    output logic              LCD_ON,
    output logic              LCD_RS,
    output logic              LCD_RW
);


  logic [07:00] data;

  logic         enable;

  logic         rs;

  logic         we;

  logic [16:00] counter;

  typedef enum bit [1:0] {
    IDLE,
    SEND_COMMAND,
    SEND_DATA,
    DELAY
  } state;
  state currState, nextState;


  assign LCD_BLON = 1'b1;

  assign LCD_ON   = 1'b1;

  assign LCD_RW   = 1'b0;

  assign LCD_DATA = data;

  assign LCD_EN   = enable;

  assign LCD_RS   = rs;




  always_ff @(posedge ACLK or posedge RESET) begin : currStateRegs
    if (RESET == 1) begin
      currState <= IDLE;
    end else begin
      currState <= nextState;
    end
  end : currStateRegs


  always_comb begin : nextStateLogic
    nextState = currState;
    we = 0;
    case (currState)
      IDLE: begin
        if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR <= BASEADDRESS + 1)) begin
          we = 1;
          if (ADDR[0] == 1'b0) begin
            nextState = SEND_COMMAND;
          end else begin
            nextState = SEND_DATA;
          end
        end
      end
      SEND_COMMAND: begin
        nextState = DELAY;
      end
      SEND_DATA: begin
        nextState = DELAY;
      end
      DELAY: begin
        if (counter == 'd0) begin
          nextState = IDLE;
        end else begin
          nextState = DELAY;
        end
      end
      default: begin
        nextState = IDLE;
      end
    endcase
  end : nextStateLogic


  always_ff @(posedge ACLK or posedge RESET) begin : regsUpdate
    if (RESET == 1) begin
      data    <= 8'd0;
      enable  <= 1'd0;
      rs      <= 1'd0;
      counter <= 17'd0;
    end else begin
      if (we == 1'b1) begin
        data <= DATA_I[07:00];
      end
      if (currState == SEND_COMMAND || currState == SEND_DATA || currState == DELAY) begin
        enable <= 1'b1;
      end else begin
        enable <= 1'b0;
      end
      if (currState == SEND_COMMAND) begin
        rs <= 1'd0;
      end else if (currState == SEND_DATA) begin
        rs <= 1'd1;
      end
      if (currState == SEND_COMMAND || currState == SEND_DATA) begin
        counter <= 17'd100000;
      end else if (currState == DELAY) begin
        counter <= counter - 17'd1;
      end
    end
  end : regsUpdate

endmodule