data/full_repos/permissive/405912356/rv32i_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/405912356/rv32i_decoder.v:61: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                       : ... In instance Decoder\n                imm = {inst[31] == 0 ? 20\'h00000 : 20\'hFFFFF, inst[31], inst[7], inst[30:25], inst[11:8], 1\'b0};\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/405912356/rv32i_decoder.v:70: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 20 bits.\n                                                                       : ... In instance Decoder\n                imm = inst[31:12] << 12;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/405912356/rv32i_decoder.v:80: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 20 bits.\n                                                                       : ... In instance Decoder\n                imm = inst[31:12] << 12;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/405912356/rv32i_decoder.v:90: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                       : ... In instance Decoder\n                imm = {inst[31] == 0 ? 12\'h000 : 12\'hFFF, inst[31], inst[19:12], inst[20], inst[30:21], 1\'b0};\n                    ^\n%Error: Exiting due to 4 warning(s)\n'
module Decoder(
    input [31:0] inst,
    output reg [3:0] alu_sel,
    output reg [2:0] val_sel,
    output reg [1:0] regw_type,
    output [2:0]funct3,
    output reg [31:0] imm,
    output reg [4:0] rd,
    output reg [4:0] rs1,
    output reg [4:0] rs2
    );
    wire [6:0] opcode;
    wire [6:0] funct7;

    assign opcode = inst[6:0];
    assign funct3 = inst[14:12];
    assign funct7 = (opcode == 7'b1101100) ? inst[31:25] : 0;

    always @(*) begin
        case(opcode)

            7'b0010011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                val_sel = 3'b001;
                case(funct3)
                    3'bx01: begin
                        imm = {27'b0, inst[24:20]};
                        alu_sel = {inst[30], funct3};
                    end
                    3'b011: begin
                        imm = {20'b0, inst[31:20]};
                        alu_sel = {1'b0, funct3};
                    end
                    default: begin
                        imm = inst[31] == 0 ? {20'h00000, inst[31:20]} : {20'hFFFFF, inst[31:20]};
                        alu_sel = {1'b0, funct3};
                    end
                endcase
                regw_type = 2'b00;
                rs2 = 0;
            end

            7'b0110011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                alu_sel = {inst[30], funct3};
                val_sel = 3'b010;
                regw_type = 2'b00;
                imm = 0;
            end

            7'b1100011: begin
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                imm = {inst[31] == 0 ? 20'h00000 : 20'hFFFFF, inst[31], inst[7], inst[30:25], inst[11:8], 1'b0};
                alu_sel = 4'b0000;
                val_sel = 3'b011;
                regw_type = 2'b00;
                rd = 0;
            end

            7'b0110111: begin
                rd = inst[11:7];
                imm = inst[31:12] << 12;
                rs1 = 0;
                alu_sel = 4'b0000;
                val_sel = 3'b001;
                regw_type = 2'b00;
                rs2 = 0;
            end

            7'b0010111: begin
                rd = inst[11:7];
                imm = inst[31:12] << 12;
                alu_sel = 4'b0000;
                val_sel = 3'b100;
                regw_type = 2'b00;
                rs1 = 0;
                rs2 = 0;
            end

            7'b1101111: begin
                rd = inst[11:7];
                imm = {inst[31] == 0 ? 12'h000 : 12'hFFF, inst[31], inst[19:12], inst[20], inst[30:21], 1'b0};
                alu_sel = 4'b0000;
                val_sel = 3'b100;
                regw_type = 2'b10;
                rs1 = 0;
                rs2 = 0;
            end
            

            7'b1100111: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFF, inst[31:20]};
                alu_sel = 4'b0000;
                val_sel = 3'b001;
                regw_type = 2'b10;
                rs2 = 0;
            end
            

            7'b0000011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFFFF, inst[31:20]};
                alu_sel = 4'b0000;
                val_sel = 3'b101;
                regw_type = 2'b01;
                rs2 = 0;
            end

            7'b0100011: begin
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFFFF, inst[31:25], inst[11:7]};
                alu_sel = 4'b0000;
                val_sel = 3'b110;
                regw_type = 0;
                rd = 0;
            end
            default: begin
                rd = 0;
                rs1 = 0;
                rs2 = 0;
                val_sel = 0;
                regw_type = 2'b00;
                imm = 0;
            end
        endcase
    end
endmodule
module Decoder(
    input [31:0] inst,
    output reg [3:0] alu_sel,
    output reg [2:0] val_sel,
    output reg [1:0] regw_type,
    output [2:0]funct3,
    output reg [31:0] imm,
    output reg [4:0] rd,
    output reg [4:0] rs1,
    output reg [4:0] rs2
    );

    wire [6:0] opcode;
    wire [6:0] funct7;

    assign opcode = inst[6:0];
    assign funct3 = inst[14:12];
    assign funct7 = (opcode == 7'b1101100) ? inst[31:25] : 0;

    always @(*) begin
        case(opcode)

            7'b0010011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                val_sel = 3'b001;
                case(funct3)
                    3'bx01: begin
                        imm = {27'b0, inst[24:20]};
                        alu_sel = {inst[30], funct3};
                    end
                    3'b011: begin
                        imm = {20'b0, inst[31:20]};
                        alu_sel = {1'b0, funct3};
                    end
                    default: begin
                        imm = inst[31] == 0 ? {20'h00000, inst[31:20]} : {20'hFFFFF, inst[31:20]};
                        alu_sel = {1'b0, funct3};
                    end
                endcase
                regw_type = 2'b00;
                rs2 = 0;
            end

            7'b0110011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                alu_sel = {inst[30], funct3};
                val_sel = 3'b010;
                regw_type = 2'b00;
                imm = 0;
            end

            7'b1100011: begin
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                imm = {inst[31] == 0 ? 20'h00000 : 20'hFFFFF, inst[31], inst[7], inst[30:25], inst[11:8], 1'b0};
                alu_sel = 4'b0000;
                val_sel = 3'b011;
                regw_type = 2'b00;
                rd = 0;
            end

            7'b0110111: begin
                rd = inst[11:7];
                imm = inst[31:12] << 12;
                rs1 = 0;
                alu_sel = 4'b0000;
                val_sel = 3'b001;
                regw_type = 2'b00;
                rs2 = 0;
            end

            7'b0010111: begin
                rd = inst[11:7];
                imm = inst[31:12] << 12;
                alu_sel = 4'b0000;
                val_sel = 3'b100;
                regw_type = 2'b00;
                rs1 = 0;
                rs2 = 0;
            end

            7'b1101111: begin
                rd = inst[11:7];
                imm = {inst[31] == 0 ? 12'h000 : 12'hFFF, inst[31], inst[19:12], inst[20], inst[30:21], 1'b0};
                alu_sel = 4'b0000;
                val_sel = 3'b100;
                regw_type = 2'b10;
                rs1 = 0;
                rs2 = 0;
            end
            

            7'b1100111: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFF, inst[31:20]};
                alu_sel = 4'b0000;
                val_sel = 3'b001;
                regw_type = 2'b10;
                rs2 = 0;
            end
            

            7'b0000011: begin
                rd = inst[11:7];
                rs1 = inst[19:15];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFFFF, inst[31:20]};
                alu_sel = 4'b0000;
                val_sel = 3'b101;
                regw_type = 2'b01;
                rs2 = 0;
            end

            7'b0100011: begin
                rs1 = inst[19:15];
                rs2 = inst[24:20];
                imm = {inst[31] == 0 ? 20'h000 : 20'hFFFFF, inst[31:25], inst[11:7]};
                alu_sel = 4'b0000;
                val_sel = 3'b110;
                regw_type = 0;
                rd = 0;
            end
            default: begin
                rd = 0;
                rs1 = 0;
                rs2 = 0;
                val_sel = 0;
                regw_type = 2'b00;
                imm = 0;
            end
        endcase
    end
endmodule