data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Individual Modules/Ram_example/Ram_example/tb_window.v
1: b'%Error: Cannot find file containing module: Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097\n        ... Looked in:\n             data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Individual/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097\n             data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Individual/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.v\n             data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Individual/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.sv\n             Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097\n             Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.v\n             Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.sv\n             obj_dir/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097\n             obj_dir/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.v\n             obj_dir/Modules/Ram_example/Ram_example,data/full_repos/permissive/52196097.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Individual\n%Error: Cannot find file containing module: Modules/Ram_example/Ram_example/tb_window.v\n%Error: Exiting due to 3 error(s)\n'
module tb_window();
	reg clk;
	reg [11:0] in1, in2;
	wire [11:0] out1, out2;
	wire next;
	wire [2:0] state;
	integer i;
	
	initial clk = 0;
	always #400 clk = ~clk;

	windowing windowing_inst (.clk(clk), .in1(in1), .in2(in2), .out1(out1),
				.out2(out2), .next(next), .state(state));
	
	initial begin
		in1 <= 12'b010000000000;
		in2 <= 12'b010000000000;

		
		@(posedge next);
		for(i = 0; i < 2048; i = i + 2) begin

			@(posedge clk);
			@(posedge clk);
			#100;
			$display("i = %d, out = %d", i, out1);
			$display("i = %d, out = %d", i+1, out2);
		end
		
		#1000;
		$finish;
	end			
	
	always @ (posedge clk) begin

	end
		
endmodule
module tb_window();

	reg clk;
	reg [11:0] in1, in2;
	wire [11:0] out1, out2;
	wire next;
	wire [2:0] state;
	integer i;
	
	initial clk = 0;
	always #400 clk = ~clk;

	windowing windowing_inst (.clk(clk), .in1(in1), .in2(in2), .out1(out1),
				.out2(out2), .next(next), .state(state));
	
	initial begin
		in1 <= 12'b010000000000;
		in2 <= 12'b010000000000;

		
		@(posedge next);
		for(i = 0; i < 2048; i = i + 2) begin

			@(posedge clk);
			@(posedge clk);
			#100;
			$display("i = %d, out = %d", i, out1);
			$display("i = %d, out = %d", i+1, out2);
		end
		
		#1000;
		$finish;
	end			
	
	always @ (posedge clk) begin

	end
		
endmodule