data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:30: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                        : ... Top module \'MISTRAL_MUL27X27\'\nmodule MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);\n       ^~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'MISTRAL_MUL18X18\'\nmodule MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);\n       ^~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'MISTRAL_MUL9X9\'\nmodule MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:72: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 9 bits.\n                                                                                                     : ... In instance MISTRAL_MUL9X9\n    assign A_ = $signed(A);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:77: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 9 bits.\n                                                                                                     : ... In instance MISTRAL_MUL9X9\n    assign B_ = $signed(B);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:44: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 18 bits.\n                                                                                                     : ... In instance MISTRAL_MUL18X18\n    assign A_ = $signed(A);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:49: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 18 bits.\n                                                                                                     : ... In instance MISTRAL_MUL18X18\n    assign B_ = $signed(B);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:16: Operator ASSIGNW expects 54 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 27 bits.\n                                                                                                     : ... In instance MISTRAL_MUL27X27\n    assign A_ = $signed(A);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/intel_alm/common/dsp_sim.v:21: Operator ASSIGNW expects 54 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 27 bits.\n                                                                                                     : ... In instance MISTRAL_MUL27X27\n    assign B_ = $signed(B);\n              ^\n%Error: Exiting due to 7 warning(s)\n'
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);

parameter A_SIGNED = 1;
parameter B_SIGNED = 1;


specify
    (A *> Y) = 2818;
    (B *> Y) = 3051;
endspecify

wire [17:0] A_, B_;

if (A_SIGNED)
    assign A_ = $signed(A);
else
    assign A_ = $unsigned(A);

if (B_SIGNED)
    assign B_ = $signed(B);
else
    assign B_ = $unsigned(B);

assign Y = A_ * B_;

endmodule
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);


parameter A_SIGNED = 1;
parameter B_SIGNED = 1;


specify
    (A *> Y) = 2818;
    (B *> Y) = 3051;
endspecify

wire [17:0] A_, B_;

if (A_SIGNED)
    assign A_ = $signed(A);
else
    assign A_ = $unsigned(A);

if (B_SIGNED)
    assign B_ = $signed(B);
else
    assign B_ = $unsigned(B);

assign Y = A_ * B_;

endmodule