data/full_repos/permissive/463481430/RTL/core/wb.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:8: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:22: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_rdidx0,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`rfidxlen_def] i_rdidx0,\n                            ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:23: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_rdwdata0,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_rdwen1,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_rdidx1,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:27: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_rdidx1,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:28: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_rdwdata1,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_rdwen2,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_rdidx2,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:32: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_rdidx2,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:33: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_rdwdata2,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`xlen_def] i_exu_jaddr,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:36: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_exu_jaddr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`xlen_def] o_exu_jaddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:38: Define or directive not defined: \'`xlen_def\'\n    output reg[`xlen_def] o_exu_jaddr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_wb_rdwen,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`rfidxlen_def] o_wb_rdidx,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:42: Define or directive not defined: \'`rfidxlen_def\'\n    output wire[`rfidxlen_def] o_wb_rdidx,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:43: Define or directive not defined: \'`xlen_def\'\n    output wire[`xlen_def] o_wb_rdwdata\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:48: Define or directive not defined: \'`rfidxlen_def\'\n    reg[`rfidxlen_def] rdidx0;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`rfidxlen_def] rdidx0;\n                     ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:49: Define or directive not defined: \'`rfidxlen_def\'\n    reg[`rfidxlen_def] rdidx1;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`rfidxlen_def] rdidx1;\n                     ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:50: Define or directive not defined: \'`rfidxlen_def\'\n    reg[`rfidxlen_def] rdidx2;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`rfidxlen_def] rdidx2;\n                     ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:51: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] rdwdata0;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] rdwdata0;\n                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:52: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] rdwdata1;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] rdwdata1;\n                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:53: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] rdwdata2;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/wb.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] rdwdata2;\n                 ^\n%Error: Exiting due to 32 error(s)\n'
module WB (
    input wire i_clk,
    input wire i_rstn,

    input wire i_flush,


    input wire i_rdwen0,
    input wire[`rfidxlen_def] i_rdidx0,
    input wire[`xlen_def] i_rdwdata0,

    input wire i_mdu_working,
    input wire i_rdwen1,
    input wire[`rfidxlen_def] i_rdidx1,
    input wire[`xlen_def] i_rdwdata1,

    input wire i_lsu_working,
    input wire i_rdwen2,
    input wire[`rfidxlen_def] i_rdidx2,
    input wire[`xlen_def] i_rdwdata2,

    input wire i_exu_taken,
    input wire[`xlen_def] i_exu_jaddr,
    output reg o_exu_taken,
    output reg[`xlen_def] o_exu_jaddr,

    output wire o_wait,
    output wire o_wb_rdwen,
    output wire[`rfidxlen_def] o_wb_rdidx,
    output wire[`xlen_def] o_wb_rdwdata
);
    reg rdwen0;
    reg rdwen1;
    reg rdwen2;
    reg[`rfidxlen_def] rdidx0;
    reg[`rfidxlen_def] rdidx1;
    reg[`rfidxlen_def] rdidx2;
    reg[`xlen_def] rdwdata0;
    reg[`xlen_def] rdwdata1;
    reg[`xlen_def] rdwdata2;


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            rdwen0<=0;
            rdwen1<=0;
            rdwen2<=0;
        end
        else if((~o_wait) | i_flush) begin
            rdwen0 <= i_flush ? 0 : i_rdwen0;
            rdwen1 <= (i_flush&(~i_rdwen1)) ? 0 : i_rdwen1;
            rdwen2 <= (i_flush&(~i_rdwen2)) ? 0 : i_rdwen2;
            rdidx0 <= i_rdidx0;
            rdidx1 <= i_rdidx1;
            rdidx2 <= i_rdidx2;
            rdwdata0 <= i_rdwdata0;
            rdwdata1 <= i_rdwdata1;
            rdwdata2 <= i_rdwdata2;
            
        end
        else if(o_wait)begin
            if(rdwen2)begin
                rdwen2<=0;
            end 
            else if(rdwen1)begin
                rdwen1<=0;
            end
        end

    end


    assign o_wait = (rdwen0 & rdwen1) | (rdwen0 & rdwen2) | (rdwen1 & rdwen2);
    assign o_wb_rdwen = rdwen0 | rdwen1 | rdwen2;

    assign o_wb_rdidx = rdwen2 ? rdidx2 : (rdwen1 ? rdidx1 : rdidx0);
    assign o_wb_rdwdata = rdwen2 ? rdwdata2 : (rdwen1 ? rdwdata1 : rdwdata0);


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            o_exu_taken<=0;
            o_exu_jaddr<=0;
        end
        else begin
            o_exu_taken <= i_flush ? 0 : i_exu_taken;
            o_exu_jaddr <= i_exu_jaddr;
        end
    end

endmodule
module WB (
    input wire i_clk,
    input wire i_rstn,

    input wire i_flush,


    input wire i_rdwen0,
    input wire[`rfidxlen_def] i_rdidx0,
    input wire[`xlen_def] i_rdwdata0,

    input wire i_mdu_working,
    input wire i_rdwen1,
    input wire[`rfidxlen_def] i_rdidx1,
    input wire[`xlen_def] i_rdwdata1,

    input wire i_lsu_working,
    input wire i_rdwen2,
    input wire[`rfidxlen_def] i_rdidx2,
    input wire[`xlen_def] i_rdwdata2,

    input wire i_exu_taken,
    input wire[`xlen_def] i_exu_jaddr,
    output reg o_exu_taken,
    output reg[`xlen_def] o_exu_jaddr,

    output wire o_wait,
    output wire o_wb_rdwen,
    output wire[`rfidxlen_def] o_wb_rdidx,
    output wire[`xlen_def] o_wb_rdwdata
);

    reg rdwen0;
    reg rdwen1;
    reg rdwen2;
    reg[`rfidxlen_def] rdidx0;
    reg[`rfidxlen_def] rdidx1;
    reg[`rfidxlen_def] rdidx2;
    reg[`xlen_def] rdwdata0;
    reg[`xlen_def] rdwdata1;
    reg[`xlen_def] rdwdata2;


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            rdwen0<=0;
            rdwen1<=0;
            rdwen2<=0;
        end
        else if((~o_wait) | i_flush) begin
            rdwen0 <= i_flush ? 0 : i_rdwen0;
            rdwen1 <= (i_flush&(~i_rdwen1)) ? 0 : i_rdwen1;
            rdwen2 <= (i_flush&(~i_rdwen2)) ? 0 : i_rdwen2;
            rdidx0 <= i_rdidx0;
            rdidx1 <= i_rdidx1;
            rdidx2 <= i_rdidx2;
            rdwdata0 <= i_rdwdata0;
            rdwdata1 <= i_rdwdata1;
            rdwdata2 <= i_rdwdata2;
            
        end
        else if(o_wait)begin
            if(rdwen2)begin
                rdwen2<=0;
            end 
            else if(rdwen1)begin
                rdwen1<=0;
            end
        end

    end


    assign o_wait = (rdwen0 & rdwen1) | (rdwen0 & rdwen2) | (rdwen1 & rdwen2);
    assign o_wb_rdwen = rdwen0 | rdwen1 | rdwen2;

    assign o_wb_rdidx = rdwen2 ? rdidx2 : (rdwen1 ? rdidx1 : rdidx0);
    assign o_wb_rdwdata = rdwen2 ? rdwdata2 : (rdwen1 ? rdwdata1 : rdwdata0);


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            o_exu_taken<=0;
            o_exu_jaddr<=0;
        end
        else begin
            o_exu_taken <= i_flush ? 0 : i_exu_taken;
            o_exu_jaddr <= i_exu_jaddr;
        end
    end

endmodule