data/full_repos/permissive/522064891/efinity/dataBus.v
data/verilator_xmls/d05598af-05e3-40c2-b34a-af2b778a3cfc.xml
module dataBus
(
  input [7:0]  romData,
  input [7:0]  ramData,
  input [7:0]  usbData,
  
  input        romSelect,
  input        ramSelect,
  input        usbSelect,
  
  output wire [7:0] dataOut
);

  reg [7:0] source;
  
  always @* begin
    if (romSelect)                      source = romData;
    else if (ramSelect)                 source = ramData;
    else if (usbSelect)                 source = usbData;
    else                                source = 8'hFF;  
  end
  
  assign dataOut = source;
  
endmodule
module dataBus
(
  input [7:0]  romData,
  input [7:0]  ramData,
  input [7:0]  usbData,
  
  input        romSelect,
  input        ramSelect,
  input        usbSelect,
  
  output wire [7:0] dataOut
);


  reg [7:0] source;
  
  always @* begin
    if (romSelect)                      source = romData;
    else if (ramSelect)                 source = ramData;
    else if (usbSelect)                 source = usbData;
    else                                source = 8'hFF;  
  end
  
  assign dataOut = source;
  
endmodule