data/full_repos/permissive/520428138/verilog/rtl/user_module_341452019534398035.v
data/verilator_xmls/3d76943f-cf17-42b3-b231-57fb5d28453e.xml
module user_module_341452019534398035(
  input [7:0] io_in, 
  output [7:0] io_out
);

  hello_341452019534398035 hello_core(
    .clk(io_in[0]),
    .dip_switch(io_in[7:1]),
    .segments(io_out[6:0]),
    .decimal(io_out[7])
  );

endmodule
module user_module_341452019534398035(
  input [7:0] io_in, 
  output [7:0] io_out
);


  hello_341452019534398035 hello_core(
    .clk(io_in[0]),
    .dip_switch(io_in[7:1]),
    .segments(io_out[6:0]),
    .decimal(io_out[7])
  );

endmodule