data/full_repos/permissive/461069000/spi/src/prescaler.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461069000/spi/src/prescaler.v:22: Operator GTE expects 8 bits on the LHS, but LHS\'s VARREF \'count\' generates 3 bits.\n                                                                           : ... In instance prescaler\n            if(count >= scale)\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461069000/spi/src/prescaler.v:25: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'count\' generates 3 bits.\n                                                                           : ... In instance prescaler\n            clk_out <= (count < scale/2) ? 1 : 0;\n                              ^\n%Error: Exiting due to 2 warning(s)\n'
module prescaler #(
    parameter RESOLUTION_BITS=3
)(
 input clk_in,
 input enable,
 input [RESOLUTION_BITS-1:0] scale_sel,
 output reg clk_out);
 
    parameter SCALE_WIRE_VALUE = $clog2(1 << (2**RESOLUTION_BITS));
    
    reg [RESOLUTION_BITS-1:0] count = 0;
    
    wire [SCALE_WIRE_VALUE-1:0] scale = (1 << scale_sel);

    always @(posedge(clk_in)) 
    begin
        if(enable)
        begin
            count <= count + 1;
            if(count >= scale)
                count <= 0;
            
            clk_out <= (count < scale/2) ? 1 : 0;
        end
    end 

endmodule
module prescaler #(
    parameter RESOLUTION_BITS=3
)(
 input clk_in,
 input enable,
 input [RESOLUTION_BITS-1:0] scale_sel,
 output reg clk_out);

 
    parameter SCALE_WIRE_VALUE = $clog2(1 << (2**RESOLUTION_BITS));
    
    reg [RESOLUTION_BITS-1:0] count = 0;
    
    wire [SCALE_WIRE_VALUE-1:0] scale = (1 << scale_sel);

    always @(posedge(clk_in)) 
    begin
        if(enable)
        begin
            count <= count + 1;
            if(count >= scale)
                count <= 0;
            
            clk_out <= (count < scale/2) ? 1 : 0;
        end
    end 

endmodule