data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v
1: b'%Error: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:2: Cannot find include file: sim/src/control_machine.v\n`include "sim/src/control_machine.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/510956372/sim,data/full_repos/permissive/510956372/sim/src/control_machine.v\n             data/full_repos/permissive/510956372/sim,data/full_repos/permissive/510956372/sim/src/control_machine.v.v\n             data/full_repos/permissive/510956372/sim,data/full_repos/permissive/510956372/sim/src/control_machine.v.sv\n             sim/src/control_machine.v\n             sim/src/control_machine.v.v\n             sim/src/control_machine.v.sv\n             obj_dir/sim/src/control_machine.v\n             obj_dir/sim/src/control_machine.v.v\n             obj_dir/sim/src/control_machine.v.sv\n%Error: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:3: Cannot find include file: sim/src/d_slp_counter.v\n`include "sim/src/d_slp_counter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n     #1 clk = ~clk;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sim/vcd/adc_dual_slope.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, adc_dual_slope_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #5 start = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #3000 cap_discharged = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #20 cap_discharged = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #5 start = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 start = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #3000 cap_discharged = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/510956372/sim/adc_dual_slope_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 cap_discharged = 0;\n    ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n'
module adc_dual_slope_tb();

reg clk, start, cap_discharged;
wire finished_counting, load, reset, enable_counting;
wire ch_Zero, ch_Vref, ch_Vmeasured;
wire [6:0] ssg_0;
wire [6:0] ssg_1;
wire [6:0] ssg_2;

control_machine ctrl_logic( start, clk, finished_counting,
                            cap_discharged, ch_Vmeasured, ch_Vref,
                            ch_Zero, load, reset, enable_counting);

d_slp_counter counter(  enable_counting, reset, load,
                        clk, ssg_0, ssg_1, ssg_2,
                        finished_counting);

always 
     #1 clk = ~clk;
initial begin 
    $dumpfile("sim/vcd/adc_dual_slope.vcd");
    $dumpvars(0, adc_dual_slope_tb);
    clk = 0;
    start = 1;
    cap_discharged = 0; 
    #5 start = 0;
    #3000 cap_discharged = 1;
    #20 cap_discharged = 0;

    #5 start = 1;
    #5 start = 0;
    #3000 cap_discharged = 1;
    #10 cap_discharged = 0;
    $finish();  
end
endmodule
module adc_dual_slope_tb();


reg clk, start, cap_discharged;
wire finished_counting, load, reset, enable_counting;
wire ch_Zero, ch_Vref, ch_Vmeasured;
wire [6:0] ssg_0;
wire [6:0] ssg_1;
wire [6:0] ssg_2;

control_machine ctrl_logic( start, clk, finished_counting,
                            cap_discharged, ch_Vmeasured, ch_Vref,
                            ch_Zero, load, reset, enable_counting);

d_slp_counter counter(  enable_counting, reset, load,
                        clk, ssg_0, ssg_1, ssg_2,
                        finished_counting);

always 
     #1 clk = ~clk;
initial begin 
    $dumpfile("sim/vcd/adc_dual_slope.vcd");
    $dumpvars(0, adc_dual_slope_tb);
    clk = 0;
    start = 1;
    cap_discharged = 0; 
    #5 start = 0;
    #3000 cap_discharged = 1;
    #20 cap_discharged = 0;

    #5 start = 1;
    #5 start = 0;
    #3000 cap_discharged = 1;
    #10 cap_discharged = 0;
    $finish();  
end
endmodule