data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v
1: b'%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:30: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.v\n             data/full_repos/permissive/423783006/rtl/e203/core,data/full_repos/permissive/423783006/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:41: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_i_rs1,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:42: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_i_rs2,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:43: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_i_imm,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:44: Define or directive not defined: \'`E203_DECINFO_AGU_WIDTH\'\n  input  [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,\n          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:45: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n  input  [`E203_ITAG_WIDTH-1:0] agu_i_itag,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:60: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] agu_o_wbck_wdat,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:67: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:77: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr,  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:79: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]      agu_icb_cmd_wdata, \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:80: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]    agu_icb_cmd_wmask, \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:80: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  output [`E203_XLEN/8-1:0]    agu_icb_cmd_wmask, \n                    ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:85: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n  output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:94: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]      agu_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:104: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] agu_req_alu_op1,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:105: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] agu_req_alu_op2,   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:115: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_req_alu_res,  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:119: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] agu_sbf_0_nxt,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:120: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_sbf_0_r,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:123: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] agu_sbf_1_nxt,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:124: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] agu_sbf_1_r,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:136: Define or directive not defined: \'`E203_DECINFO_AGU_LOAD\'\n  wire       agu_i_load    = agu_i_info [`E203_DECINFO_AGU_LOAD   ] & (~flush_block);\n                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:136: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_load    = agu_i_info [`E203_DECINFO_AGU_LOAD   ] & (~flush_block);\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:137: Define or directive not defined: \'`E203_DECINFO_AGU_STORE\'\n  wire       agu_i_store   = agu_i_info [`E203_DECINFO_AGU_STORE  ] & (~flush_block);\n                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:137: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_store   = agu_i_info [`E203_DECINFO_AGU_STORE  ] & (~flush_block);\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:138: Define or directive not defined: \'`E203_DECINFO_AGU_AMO\'\n  wire       agu_i_amo     = agu_i_info [`E203_DECINFO_AGU_AMO    ] & (~flush_block);\n                                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:138: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amo     = agu_i_info [`E203_DECINFO_AGU_AMO    ] & (~flush_block);\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:140: Define or directive not defined: \'`E203_DECINFO_AGU_SIZE\'\n  wire [1:0] agu_i_size    = agu_i_info [`E203_DECINFO_AGU_SIZE   ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:140: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [1:0] agu_i_size    = agu_i_info [`E203_DECINFO_AGU_SIZE   ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:141: Define or directive not defined: \'`E203_DECINFO_AGU_USIGN\'\n  wire       agu_i_usign   = agu_i_info [`E203_DECINFO_AGU_USIGN  ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:141: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_usign   = agu_i_info [`E203_DECINFO_AGU_USIGN  ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:142: Define or directive not defined: \'`E203_DECINFO_AGU_EXCL\'\n  wire       agu_i_excl    = agu_i_info [`E203_DECINFO_AGU_EXCL   ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:142: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_excl    = agu_i_info [`E203_DECINFO_AGU_EXCL   ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:143: Define or directive not defined: \'`E203_DECINFO_AGU_AMOSWAP\'\n  wire       agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:143: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:144: Define or directive not defined: \'`E203_DECINFO_AGU_AMOADD\'\n  wire       agu_i_amoadd  = agu_i_info [`E203_DECINFO_AGU_AMOADD ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:144: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amoadd  = agu_i_info [`E203_DECINFO_AGU_AMOADD ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:145: Define or directive not defined: \'`E203_DECINFO_AGU_AMOAND\'\n  wire       agu_i_amoand  = agu_i_info [`E203_DECINFO_AGU_AMOAND ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:145: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amoand  = agu_i_info [`E203_DECINFO_AGU_AMOAND ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:146: Define or directive not defined: \'`E203_DECINFO_AGU_AMOOR\'\n  wire       agu_i_amoor   = agu_i_info [`E203_DECINFO_AGU_AMOOR  ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:146: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amoor   = agu_i_info [`E203_DECINFO_AGU_AMOOR  ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:147: Define or directive not defined: \'`E203_DECINFO_AGU_AMOXOR\'\n  wire       agu_i_amoxor  = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:147: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amoxor  = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:148: Define or directive not defined: \'`E203_DECINFO_AGU_AMOMAX\'\n  wire       agu_i_amomax  = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:148: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amomax  = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:149: Define or directive not defined: \'`E203_DECINFO_AGU_AMOMIN\'\n  wire       agu_i_amomin  = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:149: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amomin  = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:150: Define or directive not defined: \'`E203_DECINFO_AGU_AMOMAXU\'\n  wire       agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:150: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];\n                                                                  ^\n%Error: data/full_repos/permissive/423783006/rtl/e203/core/e203_exu_alu_lsuagu.v:151: Define or directive not defined: \'`E203_DECINFO_AGU_AMOMINU\'\n  wire       agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module e203_exu_alu_lsuagu(





  input  agu_i_valid,
  output agu_i_ready,

  input  [`E203_XLEN-1:0] agu_i_rs1,
  input  [`E203_XLEN-1:0] agu_i_rs2,
  input  [`E203_XLEN-1:0] agu_i_imm,
  input  [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,
  input  [`E203_ITAG_WIDTH-1:0] agu_i_itag,

  output agu_i_longpipe,

  input  flush_req,
  input  flush_pulse,

  output amo_wait,
  input  oitf_empty,




  output agu_o_valid,
  input  agu_o_ready,
  output [`E203_XLEN-1:0] agu_o_wbck_wdat,
  output agu_o_wbck_err,   

  output agu_o_cmt_misalgn,
  output agu_o_cmt_ld,
  output agu_o_cmt_stamo,
  output agu_o_cmt_buserr,
  output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,





  output                       agu_icb_cmd_valid,
  input                        agu_icb_cmd_ready,


  output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr,
  output                       agu_icb_cmd_read,
  output [`E203_XLEN-1:0]      agu_icb_cmd_wdata, 
  output [`E203_XLEN/8-1:0]    agu_icb_cmd_wmask, 
  output                       agu_icb_cmd_back2agu, 
  output                       agu_icb_cmd_lock,
  output                       agu_icb_cmd_excl,
  output [1:0]                 agu_icb_cmd_size,
  output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,
  output                       agu_icb_cmd_usign,


  input                        agu_icb_rsp_valid,
  output                       agu_icb_rsp_ready,
  input                        agu_icb_rsp_err  ,
  input                        agu_icb_rsp_excl_ok,

  input  [`E203_XLEN-1:0]      agu_icb_rsp_rdata,









  output [`E203_XLEN-1:0] agu_req_alu_op1,
  output [`E203_XLEN-1:0] agu_req_alu_op2,
  output agu_req_alu_swap,
  output agu_req_alu_add ,
  output agu_req_alu_and ,
  output agu_req_alu_or  ,
  output agu_req_alu_xor ,
  output agu_req_alu_max ,
  output agu_req_alu_min ,
  output agu_req_alu_maxu,
  output agu_req_alu_minu,
  input  [`E203_XLEN-1:0] agu_req_alu_res,


  output agu_sbf_0_ena,
  output [`E203_XLEN-1:0] agu_sbf_0_nxt,
  input  [`E203_XLEN-1:0] agu_sbf_0_r,

  output agu_sbf_1_ena,
  output [`E203_XLEN-1:0] agu_sbf_1_nxt,
  input  [`E203_XLEN-1:0] agu_sbf_1_r,

  input  clk,
  input  rst_n
  );




  wire       icb_sta_is_idle;
  wire       flush_block = flush_req & icb_sta_is_idle; 

  wire       agu_i_load    = agu_i_info [`E203_DECINFO_AGU_LOAD   ] & (~flush_block);
  wire       agu_i_store   = agu_i_info [`E203_DECINFO_AGU_STORE  ] & (~flush_block);
  wire       agu_i_amo     = agu_i_info [`E203_DECINFO_AGU_AMO    ] & (~flush_block);

  wire [1:0] agu_i_size    = agu_i_info [`E203_DECINFO_AGU_SIZE   ];
  wire       agu_i_usign   = agu_i_info [`E203_DECINFO_AGU_USIGN  ];
  wire       agu_i_excl    = agu_i_info [`E203_DECINFO_AGU_EXCL   ];
  wire       agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];
  wire       agu_i_amoadd  = agu_i_info [`E203_DECINFO_AGU_AMOADD ];
  wire       agu_i_amoand  = agu_i_info [`E203_DECINFO_AGU_AMOAND ];
  wire       agu_i_amoor   = agu_i_info [`E203_DECINFO_AGU_AMOOR  ];
  wire       agu_i_amoxor  = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];
  wire       agu_i_amomax  = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];
  wire       agu_i_amomin  = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];
  wire       agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];
  wire       agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];


  wire agu_icb_cmd_hsked = agu_icb_cmd_valid & agu_icb_cmd_ready; 
  `ifdef E203_SUPPORT_AMO
  wire agu_icb_rsp_hsked = agu_icb_rsp_valid & agu_icb_rsp_ready; 
  `endif


  `ifndef E203_SUPPORT_AMO
    `ifndef E203_SUPPORT_UNALGNLDST
  wire agu_icb_rsp_hsked = 1'b0;
    `endif
  `endif

  wire agu_i_size_b  = (agu_i_size == 2'b00);
  wire agu_i_size_hw = (agu_i_size == 2'b01);
  wire agu_i_size_w  = (agu_i_size == 2'b10);

  wire agu_i_addr_unalgn =
            (agu_i_size_hw &  agu_icb_cmd_addr[0])
          | (agu_i_size_w  &  (|agu_icb_cmd_addr[1:0]));

  wire state_last_exit_ena;
  `ifdef E203_SUPPORT_AMO
  wire state_idle_exit_ena;
  wire unalgn_flg_r;

  wire unalgn_flg_set = agu_i_addr_unalgn & state_idle_exit_ena;

  wire unalgn_flg_clr = unalgn_flg_r & state_last_exit_ena;
  wire unalgn_flg_ena = unalgn_flg_set | unalgn_flg_clr;
  wire unalgn_flg_nxt = unalgn_flg_set | (~unalgn_flg_clr);
  sirv_gnrl_dfflr #(1) unalgn_flg_dffl (unalgn_flg_ena, unalgn_flg_nxt, unalgn_flg_r, clk, rst_n);
  `endif

  wire agu_addr_unalgn = 
  `ifndef E203_SUPPORT_UNALGNLDST
      `ifdef E203_SUPPORT_AMO
      icb_sta_is_idle ? agu_i_addr_unalgn : unalgn_flg_r;
      `endif
      `ifndef E203_SUPPORT_AMO
      agu_i_addr_unalgn;
      `endif
  `endif

 
  wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load)
                      ; 
  wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store)
                      ;
  wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst)
                      ;
  wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load
                      ; 
  wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store
                      ; 
  wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst)
                      ;

  `ifdef E203_SUPPORT_AMO
  wire agu_i_unalgnamo = (agu_addr_unalgn & agu_i_amo) 
                        ;
  wire agu_i_algnamo = ((~agu_addr_unalgn) & agu_i_amo) 
                        ;
  `endif

  wire agu_i_ofst0  = agu_i_amo | ((agu_i_load | agu_i_store) & agu_i_excl); 


  localparam ICB_STATE_WIDTH = 4;

  wire icb_state_ena;
  wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
  wire [ICB_STATE_WIDTH-1:0] icb_state_r;


  localparam ICB_STATE_IDLE = 4'd0;
  `ifdef E203_SUPPORT_AMO

  localparam ICB_STATE_1ST  = 4'd1;

  localparam ICB_STATE_WAIT2ND  = 4'd2;

  localparam ICB_STATE_2ND  = 4'd3;


  localparam ICB_STATE_AMOALU  = 4'd4;


  localparam ICB_STATE_AMORDY  = 4'd5;


  localparam ICB_STATE_WBCK  = 4'd6;
  `endif
  
   
  
 
  `ifdef E203_SUPPORT_AMO
  wire [ICB_STATE_WIDTH-1:0] state_idle_nxt   ;
  wire [ICB_STATE_WIDTH-1:0] state_1st_nxt    ;
  wire [ICB_STATE_WIDTH-1:0] state_wait2nd_nxt;
  wire [ICB_STATE_WIDTH-1:0] state_2nd_nxt    ;
  wire [ICB_STATE_WIDTH-1:0] state_amoalu_nxt ;
  wire [ICB_STATE_WIDTH-1:0] state_amordy_nxt ;
  wire [ICB_STATE_WIDTH-1:0] state_wbck_nxt ;
  `endif
  `ifdef E203_SUPPORT_AMO
  wire state_1st_exit_ena      ;
  wire state_wait2nd_exit_ena  ;
  wire state_2nd_exit_ena      ;
  wire state_amoalu_exit_ena   ;
  wire state_amordy_exit_ena   ;
  wire state_wbck_exit_ena   ;
  `endif


  assign icb_sta_is_idle    = (icb_state_r == ICB_STATE_IDLE   );
  `ifdef E203_SUPPORT_AMO
  wire   icb_sta_is_1st     = (icb_state_r == ICB_STATE_1ST    );
  wire   icb_sta_is_amoalu  = (icb_state_r == ICB_STATE_AMOALU );
  wire   icb_sta_is_amordy  = (icb_state_r == ICB_STATE_AMORDY );
  wire   icb_sta_is_wait2nd = (icb_state_r == ICB_STATE_WAIT2ND);
  wire   icb_sta_is_2nd     = (icb_state_r == ICB_STATE_2ND    );
  wire   icb_sta_is_wbck    = (icb_state_r == ICB_STATE_WBCK    );
  `endif


  `ifdef E203_SUPPORT_AMO



  wire state_idle_to_exit =    (( agu_i_algnamo










                                  & oitf_empty)
                                 );
  assign state_idle_exit_ena = icb_sta_is_idle & state_idle_to_exit 
                               & agu_icb_cmd_hsked & (~flush_pulse);
  assign state_idle_nxt      = ICB_STATE_1ST;



  assign state_1st_exit_ena = icb_sta_is_1st & (agu_icb_rsp_hsked | flush_pulse);
  assign state_1st_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (


                  ICB_STATE_AMOALU
                );
            



  assign state_amoalu_exit_ena = icb_sta_is_amoalu & ( 1'b1 | flush_pulse);
  assign state_amoalu_nxt      = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_AMORDY;
            


  assign state_amordy_exit_ena = icb_sta_is_amordy & ( 1'b1 | flush_pulse);
  assign state_amordy_nxt      = flush_pulse ? ICB_STATE_IDLE : 
            (



                                       ICB_STATE_WAIT2ND
            );


  assign state_wait2nd_exit_ena = icb_sta_is_wait2nd & (agu_icb_cmd_ready | flush_pulse);

  assign state_wait2nd_nxt      = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_2ND;
  


  assign state_2nd_exit_ena = icb_sta_is_2nd & (agu_icb_rsp_hsked | flush_pulse);
  assign state_2nd_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (
                  ICB_STATE_WBCK 
                );



  assign state_wbck_exit_ena = icb_sta_is_wbck & (agu_o_ready | flush_pulse);
  assign state_wbck_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (
                  ICB_STATE_IDLE 
                );
  `endif


  assign icb_state_ena = 1'b0 
         `ifdef E203_SUPPORT_AMO
            | state_idle_exit_ena | state_1st_exit_ena  
            | state_amoalu_exit_ena  | state_amordy_exit_ena  
            | state_wait2nd_exit_ena | state_2nd_exit_ena   
            | state_wbck_exit_ena 
          `endif
          ;


  assign icb_state_nxt = 
              ({ICB_STATE_WIDTH{1'b0}})
         `ifdef E203_SUPPORT_AMO
            | ({ICB_STATE_WIDTH{state_idle_exit_ena   }} & state_idle_nxt   )
            | ({ICB_STATE_WIDTH{state_1st_exit_ena    }} & state_1st_nxt    )
            | ({ICB_STATE_WIDTH{state_amoalu_exit_ena }} & state_amoalu_nxt )
            | ({ICB_STATE_WIDTH{state_amordy_exit_ena }} & state_amordy_nxt )
            | ({ICB_STATE_WIDTH{state_wait2nd_exit_ena}} & state_wait2nd_nxt)
            | ({ICB_STATE_WIDTH{state_2nd_exit_ena    }} & state_2nd_nxt    )
            | ({ICB_STATE_WIDTH{state_wbck_exit_ena   }} & state_wbck_nxt   )
          `endif
              ;


  sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);


  `ifdef E203_SUPPORT_AMO
  wire  icb_sta_is_last = icb_sta_is_wbck;
  `endif
  `ifndef E203_SUPPORT_AMO
  wire  icb_sta_is_last = 1'b0; 
  `endif

  `ifdef E203_SUPPORT_AMO
  assign state_last_exit_ena = state_wbck_exit_ena;
  `endif
  `ifndef E203_SUPPORT_AMO
  assign state_last_exit_ena = 1'b0;
  `endif

  `ifndef E203_SUPPORT_UNALGNLDST
  `else
      `ifndef E203_SUPPORT_AMO 
  !!!! ERROR: This config is not supported, must be something wrong 
      `endif
  `endif



  `ifdef E203_SUPPORT_AMO




  assign amo_wait = ~icb_sta_is_idle;
  `endif
  `ifndef E203_SUPPORT_AMO
  assign amo_wait = 1'b0;
  `endif



  wire leftover_ena;
  wire [`E203_XLEN-1:0] leftover_nxt;
  wire [`E203_XLEN-1:0] leftover_r;
  wire leftover_err_nxt;
  wire leftover_err_r;

  wire [`E203_XLEN-1:0] leftover_1_r;
  wire leftover_1_ena;
  wire [`E203_XLEN-1:0] leftover_1_nxt;

 `ifdef E203_SUPPORT_AMO
  wire amo_1stuop = icb_sta_is_1st & agu_i_algnamo;
  wire amo_2nduop = icb_sta_is_2nd & agu_i_algnamo;
 `endif
  assign leftover_ena = agu_icb_rsp_hsked & (
                   1'b0
                   `ifdef E203_SUPPORT_AMO
                   | amo_1stuop 
                   | amo_2nduop 
                   `endif
                   );
  assign leftover_nxt = 
              {`E203_XLEN{1'b0}}
         `ifdef E203_SUPPORT_AMO
            | ({`E203_XLEN{amo_1stuop        }} & agu_icb_rsp_rdata)
            | ({`E203_XLEN{amo_2nduop        }} & leftover_r)
         `endif
            ;
                                   
  assign leftover_err_nxt = 1'b0 
         `ifdef E203_SUPPORT_AMO
            | ({{amo_1stuop        }} & agu_icb_rsp_err)
            | ({{amo_2nduop        }} & (agu_icb_rsp_err | leftover_err_r))
         `endif
         ;


  assign agu_sbf_0_ena = leftover_ena;
  assign agu_sbf_0_nxt = leftover_nxt;
  assign leftover_r    = agu_sbf_0_r;


  sirv_gnrl_dfflr #(1) icb_leftover_err_dfflr (leftover_ena, leftover_err_nxt, leftover_err_r, clk, rst_n);
  
  assign leftover_1_ena = 1'b0 
         `ifdef E203_SUPPORT_AMO
           | icb_sta_is_amoalu 
         `endif
         ;
  assign leftover_1_nxt = agu_req_alu_res;


  assign agu_sbf_1_ena   = leftover_1_ena;
  assign agu_sbf_1_nxt   = leftover_1_nxt;
  assign leftover_1_r = agu_sbf_1_r;


  assign agu_req_alu_add  = 1'b0
                     `ifdef E203_SUPPORT_AMO
                           | (icb_sta_is_amoalu & agu_i_amoadd)

                           | (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck))
                     `endif


                           | icb_sta_is_idle
                           ;

  assign agu_req_alu_op1 =  icb_sta_is_idle   ? agu_i_rs1
                     `ifdef E203_SUPPORT_AMO
                          : icb_sta_is_amoalu ? leftover_r

                          : (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_i_rs1
                     `endif
                     `ifndef E203_SUPPORT_UNALGNLDST
                          : `E203_XLEN'd0 
                     `endif
                     ;

  wire [`E203_XLEN-1:0] agu_addr_gen_op2 = agu_i_ofst0 ? `E203_XLEN'b0 : agu_i_imm;
  assign agu_req_alu_op2 =  icb_sta_is_idle   ? agu_addr_gen_op2
                     `ifdef E203_SUPPORT_AMO
                          : icb_sta_is_amoalu ? agu_i_rs2

                          : (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_addr_gen_op2
                     `endif
                     `ifndef E203_SUPPORT_UNALGNLDST
                          : `E203_XLEN'd0 
                     `endif
                     ;

  `ifdef E203_SUPPORT_AMO
  assign agu_req_alu_swap = (icb_sta_is_amoalu & agu_i_amoswap );
  assign agu_req_alu_and  = (icb_sta_is_amoalu & agu_i_amoand  );
  assign agu_req_alu_or   = (icb_sta_is_amoalu & agu_i_amoor   );
  assign agu_req_alu_xor  = (icb_sta_is_amoalu & agu_i_amoxor  );
  assign agu_req_alu_max  = (icb_sta_is_amoalu & agu_i_amomax  );
  assign agu_req_alu_min  = (icb_sta_is_amoalu & agu_i_amomin  );
  assign agu_req_alu_maxu = (icb_sta_is_amoalu & agu_i_amomaxu );
  assign agu_req_alu_minu = (icb_sta_is_amoalu & agu_i_amominu );
  `endif
  `ifndef E203_SUPPORT_AMO
  assign agu_req_alu_swap = 1'b0;
  assign agu_req_alu_and  = 1'b0;
  assign agu_req_alu_or   = 1'b0;
  assign agu_req_alu_xor  = 1'b0;
  assign agu_req_alu_max  = 1'b0;
  assign agu_req_alu_min  = 1'b0;
  assign agu_req_alu_maxu = 1'b0;
  assign agu_req_alu_minu = 1'b0;
  `endif














  `ifndef E203_SUPPORT_UNALGNLDST
  `else
  !!!! ERROR: This UNALIGNED load/store is not supported, must be something wrong 
  `endif

  assign agu_i_ready =
      ( 1'b0
  `ifdef E203_SUPPORT_AMO
       | agu_i_algnamo 
  `endif
       ) ? state_last_exit_ena :
      (agu_icb_cmd_ready & agu_o_ready) ;
  


  assign agu_i_longpipe = agu_i_algnldst;
  









  assign agu_o_valid = 
        `ifdef E203_SUPPORT_AMO



      icb_sta_is_last 
        `endif


      |(
         agu_i_valid & ( agu_i_algnldst 
        `ifndef E203_SUPPORT_UNALGNLDST




           | agu_i_unalgnldst
        `endif
        `ifdef E203_SUPPORT_AMO
           | agu_i_unalgnamo 
        `endif
         )





          & agu_icb_cmd_ready
      );

  assign agu_o_wbck_wdat = {`E203_XLEN{1'b0 }}
       `ifdef E203_SUPPORT_AMO
                    | ({`E203_XLEN{agu_i_algnamo  }} & leftover_r) 
                    | ({`E203_XLEN{agu_i_unalgnamo}} & `E203_XLEN'b0) 
       `endif
       ;

  assign agu_o_cmt_buserr = (1'b0 
                `ifdef E203_SUPPORT_AMO
                      | (agu_i_algnamo    & leftover_err_r) 
                      | (agu_i_unalgnamo  & 1'b0) 
                `endif
                      )
                ;
  assign agu_o_cmt_badaddr = agu_icb_cmd_addr;


  assign agu_o_cmt_misalgn = (1'b0
                `ifdef E203_SUPPORT_AMO
                       | agu_i_unalgnamo 
                `endif
                       | (agu_i_unalgnldst)
                       )
                       ;
  assign agu_o_cmt_ld      = agu_i_load & (~agu_i_excl); 
  assign agu_o_cmt_stamo   = agu_i_store | agu_i_amo | agu_i_excl;

  

  assign agu_o_wbck_err = agu_o_cmt_buserr | agu_o_cmt_misalgn
                          ;


  assign agu_icb_rsp_ready = 1'b1;


  

  assign agu_icb_cmd_valid = 
            ((agu_i_algnldst & agu_i_valid)


              & (agu_o_ready)
            )
          `ifdef E203_SUPPORT_AMO
            | (agu_i_algnamo & (
                         (icb_sta_is_idle & agu_i_valid 


                             & agu_o_ready)
                       | (icb_sta_is_wait2nd)))
            | (agu_i_unalgnamo & 1'b0) 
          `endif
            ;
  assign agu_icb_cmd_addr = agu_req_alu_res[`E203_ADDR_SIZE-1:0];

  assign agu_icb_cmd_read = 
            (agu_i_algnldst & agu_i_load) 
          `ifdef E203_SUPPORT_AMO
          | (agu_i_algnamo & icb_sta_is_idle & 1'b1)
          | (agu_i_algnamo & icb_sta_is_wait2nd & 1'b0) 
          `endif
          ;






  wire [`E203_XLEN-1:0] algnst_wdata = 
            ({`E203_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
          | ({`E203_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
          | ({`E203_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
  wire [`E203_XLEN/8-1:0] algnst_wmask = 
            ({`E203_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_icb_cmd_addr[1:0]))
          | ({`E203_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_icb_cmd_addr[1],1'b0}))
          | ({`E203_XLEN/8{agu_i_size_w }} & (4'b1111));

          
  assign agu_icb_cmd_wdata = 
  `ifdef E203_SUPPORT_AMO
      agu_i_amo ? leftover_1_r :
  `endif
      algnst_wdata;

  assign agu_icb_cmd_wmask =
  `ifdef E203_SUPPORT_AMO

      agu_i_amo ? (leftover_err_r ? 4'h0 : 4'hF) :
  `endif
      algnst_wmask; 

  assign agu_icb_cmd_back2agu = 1'b0 
             `ifdef E203_SUPPORT_AMO
                | agu_i_algnamo  
             `endif
             ;

  assign agu_icb_cmd_lock     = 1'b0 
             `ifdef E203_SUPPORT_AMO
                 | (agu_i_algnamo & icb_sta_is_idle)
             `endif
                 ;
  assign agu_icb_cmd_excl     = 1'b0
             `ifdef E203_SUPPORT_AMO
                 | agu_i_excl
             `endif
                 ;

  assign agu_icb_cmd_itag     = agu_i_itag;
  assign agu_icb_cmd_usign    = agu_i_usign;
  assign agu_icb_cmd_size     = 
                agu_i_size;


endmodule
module e203_exu_alu_lsuagu(





  input  agu_i_valid,
  output agu_i_ready,

  input  [`E203_XLEN-1:0] agu_i_rs1,
  input  [`E203_XLEN-1:0] agu_i_rs2,
  input  [`E203_XLEN-1:0] agu_i_imm,
  input  [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,
  input  [`E203_ITAG_WIDTH-1:0] agu_i_itag,

  output agu_i_longpipe,

  input  flush_req,
  input  flush_pulse,

  output amo_wait,
  input  oitf_empty,




  output agu_o_valid,
  input  agu_o_ready,
  output [`E203_XLEN-1:0] agu_o_wbck_wdat,
  output agu_o_wbck_err,   

  output agu_o_cmt_misalgn,
  output agu_o_cmt_ld,
  output agu_o_cmt_stamo,
  output agu_o_cmt_buserr,
  output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,





  output                       agu_icb_cmd_valid,
  input                        agu_icb_cmd_ready,


  output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr,
  output                       agu_icb_cmd_read,
  output [`E203_XLEN-1:0]      agu_icb_cmd_wdata, 
  output [`E203_XLEN/8-1:0]    agu_icb_cmd_wmask, 
  output                       agu_icb_cmd_back2agu, 
  output                       agu_icb_cmd_lock,
  output                       agu_icb_cmd_excl,
  output [1:0]                 agu_icb_cmd_size,
  output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,
  output                       agu_icb_cmd_usign,


  input                        agu_icb_rsp_valid,
  output                       agu_icb_rsp_ready,
  input                        agu_icb_rsp_err  ,
  input                        agu_icb_rsp_excl_ok,

  input  [`E203_XLEN-1:0]      agu_icb_rsp_rdata,









  output [`E203_XLEN-1:0] agu_req_alu_op1,
  output [`E203_XLEN-1:0] agu_req_alu_op2,
  output agu_req_alu_swap,
  output agu_req_alu_add ,
  output agu_req_alu_and ,
  output agu_req_alu_or  ,
  output agu_req_alu_xor ,
  output agu_req_alu_max ,
  output agu_req_alu_min ,
  output agu_req_alu_maxu,
  output agu_req_alu_minu,
  input  [`E203_XLEN-1:0] agu_req_alu_res,


  output agu_sbf_0_ena,
  output [`E203_XLEN-1:0] agu_sbf_0_nxt,
  input  [`E203_XLEN-1:0] agu_sbf_0_r,

  output agu_sbf_1_ena,
  output [`E203_XLEN-1:0] agu_sbf_1_nxt,
  input  [`E203_XLEN-1:0] agu_sbf_1_r,

  input  clk,
  input  rst_n
  );





  wire       icb_sta_is_idle;
  wire       flush_block = flush_req & icb_sta_is_idle; 

  wire       agu_i_load    = agu_i_info [`E203_DECINFO_AGU_LOAD   ] & (~flush_block);
  wire       agu_i_store   = agu_i_info [`E203_DECINFO_AGU_STORE  ] & (~flush_block);
  wire       agu_i_amo     = agu_i_info [`E203_DECINFO_AGU_AMO    ] & (~flush_block);

  wire [1:0] agu_i_size    = agu_i_info [`E203_DECINFO_AGU_SIZE   ];
  wire       agu_i_usign   = agu_i_info [`E203_DECINFO_AGU_USIGN  ];
  wire       agu_i_excl    = agu_i_info [`E203_DECINFO_AGU_EXCL   ];
  wire       agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];
  wire       agu_i_amoadd  = agu_i_info [`E203_DECINFO_AGU_AMOADD ];
  wire       agu_i_amoand  = agu_i_info [`E203_DECINFO_AGU_AMOAND ];
  wire       agu_i_amoor   = agu_i_info [`E203_DECINFO_AGU_AMOOR  ];
  wire       agu_i_amoxor  = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];
  wire       agu_i_amomax  = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];
  wire       agu_i_amomin  = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];
  wire       agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];
  wire       agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];


  wire agu_icb_cmd_hsked = agu_icb_cmd_valid & agu_icb_cmd_ready; 
  `ifdef E203_SUPPORT_AMO
  wire agu_icb_rsp_hsked = agu_icb_rsp_valid & agu_icb_rsp_ready; 
  `endif


  `ifndef E203_SUPPORT_AMO
    `ifndef E203_SUPPORT_UNALGNLDST
  wire agu_icb_rsp_hsked = 1'b0;
    `endif
  `endif

  wire agu_i_size_b  = (agu_i_size == 2'b00);
  wire agu_i_size_hw = (agu_i_size == 2'b01);
  wire agu_i_size_w  = (agu_i_size == 2'b10);

  wire agu_i_addr_unalgn =
            (agu_i_size_hw &  agu_icb_cmd_addr[0])
          | (agu_i_size_w  &  (|agu_icb_cmd_addr[1:0]));

  wire state_last_exit_ena;
  `ifdef E203_SUPPORT_AMO
  wire state_idle_exit_ena;
  wire unalgn_flg_r;

  wire unalgn_flg_set = agu_i_addr_unalgn & state_idle_exit_ena;

  wire unalgn_flg_clr = unalgn_flg_r & state_last_exit_ena;
  wire unalgn_flg_ena = unalgn_flg_set | unalgn_flg_clr;
  wire unalgn_flg_nxt = unalgn_flg_set | (~unalgn_flg_clr);
  sirv_gnrl_dfflr #(1) unalgn_flg_dffl (unalgn_flg_ena, unalgn_flg_nxt, unalgn_flg_r, clk, rst_n);
  `endif

  wire agu_addr_unalgn = 
  `ifndef E203_SUPPORT_UNALGNLDST
      `ifdef E203_SUPPORT_AMO
      icb_sta_is_idle ? agu_i_addr_unalgn : unalgn_flg_r;
      `endif
      `ifndef E203_SUPPORT_AMO
      agu_i_addr_unalgn;
      `endif
  `endif

 
  wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load)
                      ; 
  wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store)
                      ;
  wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst)
                      ;
  wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load
                      ; 
  wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store
                      ; 
  wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst)
                      ;

  `ifdef E203_SUPPORT_AMO
  wire agu_i_unalgnamo = (agu_addr_unalgn & agu_i_amo) 
                        ;
  wire agu_i_algnamo = ((~agu_addr_unalgn) & agu_i_amo) 
                        ;
  `endif

  wire agu_i_ofst0  = agu_i_amo | ((agu_i_load | agu_i_store) & agu_i_excl); 


  localparam ICB_STATE_WIDTH = 4;

  wire icb_state_ena;
  wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
  wire [ICB_STATE_WIDTH-1:0] icb_state_r;


  localparam ICB_STATE_IDLE = 4'd0;
  `ifdef E203_SUPPORT_AMO

  localparam ICB_STATE_1ST  = 4'd1;

  localparam ICB_STATE_WAIT2ND  = 4'd2;

  localparam ICB_STATE_2ND  = 4'd3;


  localparam ICB_STATE_AMOALU  = 4'd4;


  localparam ICB_STATE_AMORDY  = 4'd5;


  localparam ICB_STATE_WBCK  = 4'd6;
  `endif
  
   
  
 
  `ifdef E203_SUPPORT_AMO
  wire [ICB_STATE_WIDTH-1:0] state_idle_nxt   ;
  wire [ICB_STATE_WIDTH-1:0] state_1st_nxt    ;
  wire [ICB_STATE_WIDTH-1:0] state_wait2nd_nxt;
  wire [ICB_STATE_WIDTH-1:0] state_2nd_nxt    ;
  wire [ICB_STATE_WIDTH-1:0] state_amoalu_nxt ;
  wire [ICB_STATE_WIDTH-1:0] state_amordy_nxt ;
  wire [ICB_STATE_WIDTH-1:0] state_wbck_nxt ;
  `endif
  `ifdef E203_SUPPORT_AMO
  wire state_1st_exit_ena      ;
  wire state_wait2nd_exit_ena  ;
  wire state_2nd_exit_ena      ;
  wire state_amoalu_exit_ena   ;
  wire state_amordy_exit_ena   ;
  wire state_wbck_exit_ena   ;
  `endif


  assign icb_sta_is_idle    = (icb_state_r == ICB_STATE_IDLE   );
  `ifdef E203_SUPPORT_AMO
  wire   icb_sta_is_1st     = (icb_state_r == ICB_STATE_1ST    );
  wire   icb_sta_is_amoalu  = (icb_state_r == ICB_STATE_AMOALU );
  wire   icb_sta_is_amordy  = (icb_state_r == ICB_STATE_AMORDY );
  wire   icb_sta_is_wait2nd = (icb_state_r == ICB_STATE_WAIT2ND);
  wire   icb_sta_is_2nd     = (icb_state_r == ICB_STATE_2ND    );
  wire   icb_sta_is_wbck    = (icb_state_r == ICB_STATE_WBCK    );
  `endif


  `ifdef E203_SUPPORT_AMO



  wire state_idle_to_exit =    (( agu_i_algnamo










                                  & oitf_empty)
                                 );
  assign state_idle_exit_ena = icb_sta_is_idle & state_idle_to_exit 
                               & agu_icb_cmd_hsked & (~flush_pulse);
  assign state_idle_nxt      = ICB_STATE_1ST;



  assign state_1st_exit_ena = icb_sta_is_1st & (agu_icb_rsp_hsked | flush_pulse);
  assign state_1st_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (


                  ICB_STATE_AMOALU
                );
            



  assign state_amoalu_exit_ena = icb_sta_is_amoalu & ( 1'b1 | flush_pulse);
  assign state_amoalu_nxt      = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_AMORDY;
            


  assign state_amordy_exit_ena = icb_sta_is_amordy & ( 1'b1 | flush_pulse);
  assign state_amordy_nxt      = flush_pulse ? ICB_STATE_IDLE : 
            (



                                       ICB_STATE_WAIT2ND
            );


  assign state_wait2nd_exit_ena = icb_sta_is_wait2nd & (agu_icb_cmd_ready | flush_pulse);

  assign state_wait2nd_nxt      = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_2ND;
  


  assign state_2nd_exit_ena = icb_sta_is_2nd & (agu_icb_rsp_hsked | flush_pulse);
  assign state_2nd_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (
                  ICB_STATE_WBCK 
                );



  assign state_wbck_exit_ena = icb_sta_is_wbck & (agu_o_ready | flush_pulse);
  assign state_wbck_nxt      = flush_pulse ? ICB_STATE_IDLE : 
                (
                  ICB_STATE_IDLE 
                );
  `endif


  assign icb_state_ena = 1'b0 
         `ifdef E203_SUPPORT_AMO
            | state_idle_exit_ena | state_1st_exit_ena  
            | state_amoalu_exit_ena  | state_amordy_exit_ena  
            | state_wait2nd_exit_ena | state_2nd_exit_ena   
            | state_wbck_exit_ena 
          `endif
          ;


  assign icb_state_nxt = 
              ({ICB_STATE_WIDTH{1'b0}})
         `ifdef E203_SUPPORT_AMO
            | ({ICB_STATE_WIDTH{state_idle_exit_ena   }} & state_idle_nxt   )
            | ({ICB_STATE_WIDTH{state_1st_exit_ena    }} & state_1st_nxt    )
            | ({ICB_STATE_WIDTH{state_amoalu_exit_ena }} & state_amoalu_nxt )
            | ({ICB_STATE_WIDTH{state_amordy_exit_ena }} & state_amordy_nxt )
            | ({ICB_STATE_WIDTH{state_wait2nd_exit_ena}} & state_wait2nd_nxt)
            | ({ICB_STATE_WIDTH{state_2nd_exit_ena    }} & state_2nd_nxt    )
            | ({ICB_STATE_WIDTH{state_wbck_exit_ena   }} & state_wbck_nxt   )
          `endif
              ;


  sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);


  `ifdef E203_SUPPORT_AMO
  wire  icb_sta_is_last = icb_sta_is_wbck;
  `endif
  `ifndef E203_SUPPORT_AMO
  wire  icb_sta_is_last = 1'b0; 
  `endif

  `ifdef E203_SUPPORT_AMO
  assign state_last_exit_ena = state_wbck_exit_ena;
  `endif
  `ifndef E203_SUPPORT_AMO
  assign state_last_exit_ena = 1'b0;
  `endif

  `ifndef E203_SUPPORT_UNALGNLDST
  `else
      `ifndef E203_SUPPORT_AMO 
  !!!! ERROR: This config is not supported, must be something wrong 
      `endif
  `endif



  `ifdef E203_SUPPORT_AMO




  assign amo_wait = ~icb_sta_is_idle;
  `endif
  `ifndef E203_SUPPORT_AMO
  assign amo_wait = 1'b0;
  `endif



  wire leftover_ena;
  wire [`E203_XLEN-1:0] leftover_nxt;
  wire [`E203_XLEN-1:0] leftover_r;
  wire leftover_err_nxt;
  wire leftover_err_r;

  wire [`E203_XLEN-1:0] leftover_1_r;
  wire leftover_1_ena;
  wire [`E203_XLEN-1:0] leftover_1_nxt;

 `ifdef E203_SUPPORT_AMO
  wire amo_1stuop = icb_sta_is_1st & agu_i_algnamo;
  wire amo_2nduop = icb_sta_is_2nd & agu_i_algnamo;
 `endif
  assign leftover_ena = agu_icb_rsp_hsked & (
                   1'b0
                   `ifdef E203_SUPPORT_AMO
                   | amo_1stuop 
                   | amo_2nduop 
                   `endif
                   );
  assign leftover_nxt = 
              {`E203_XLEN{1'b0}}
         `ifdef E203_SUPPORT_AMO
            | ({`E203_XLEN{amo_1stuop        }} & agu_icb_rsp_rdata)
            | ({`E203_XLEN{amo_2nduop        }} & leftover_r)
         `endif
            ;
                                   
  assign leftover_err_nxt = 1'b0 
         `ifdef E203_SUPPORT_AMO
            | ({{amo_1stuop        }} & agu_icb_rsp_err)
            | ({{amo_2nduop        }} & (agu_icb_rsp_err | leftover_err_r))
         `endif
         ;


  assign agu_sbf_0_ena = leftover_ena;
  assign agu_sbf_0_nxt = leftover_nxt;
  assign leftover_r    = agu_sbf_0_r;


  sirv_gnrl_dfflr #(1) icb_leftover_err_dfflr (leftover_ena, leftover_err_nxt, leftover_err_r, clk, rst_n);
  
  assign leftover_1_ena = 1'b0 
         `ifdef E203_SUPPORT_AMO
           | icb_sta_is_amoalu 
         `endif
         ;
  assign leftover_1_nxt = agu_req_alu_res;


  assign agu_sbf_1_ena   = leftover_1_ena;
  assign agu_sbf_1_nxt   = leftover_1_nxt;
  assign leftover_1_r = agu_sbf_1_r;


  assign agu_req_alu_add  = 1'b0
                     `ifdef E203_SUPPORT_AMO
                           | (icb_sta_is_amoalu & agu_i_amoadd)

                           | (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck))
                     `endif


                           | icb_sta_is_idle
                           ;

  assign agu_req_alu_op1 =  icb_sta_is_idle   ? agu_i_rs1
                     `ifdef E203_SUPPORT_AMO
                          : icb_sta_is_amoalu ? leftover_r

                          : (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_i_rs1
                     `endif
                     `ifndef E203_SUPPORT_UNALGNLDST
                          : `E203_XLEN'd0 
                     `endif
                     ;

  wire [`E203_XLEN-1:0] agu_addr_gen_op2 = agu_i_ofst0 ? `E203_XLEN'b0 : agu_i_imm;
  assign agu_req_alu_op2 =  icb_sta_is_idle   ? agu_addr_gen_op2
                     `ifdef E203_SUPPORT_AMO
                          : icb_sta_is_amoalu ? agu_i_rs2

                          : (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_addr_gen_op2
                     `endif
                     `ifndef E203_SUPPORT_UNALGNLDST
                          : `E203_XLEN'd0 
                     `endif
                     ;

  `ifdef E203_SUPPORT_AMO
  assign agu_req_alu_swap = (icb_sta_is_amoalu & agu_i_amoswap );
  assign agu_req_alu_and  = (icb_sta_is_amoalu & agu_i_amoand  );
  assign agu_req_alu_or   = (icb_sta_is_amoalu & agu_i_amoor   );
  assign agu_req_alu_xor  = (icb_sta_is_amoalu & agu_i_amoxor  );
  assign agu_req_alu_max  = (icb_sta_is_amoalu & agu_i_amomax  );
  assign agu_req_alu_min  = (icb_sta_is_amoalu & agu_i_amomin  );
  assign agu_req_alu_maxu = (icb_sta_is_amoalu & agu_i_amomaxu );
  assign agu_req_alu_minu = (icb_sta_is_amoalu & agu_i_amominu );
  `endif
  `ifndef E203_SUPPORT_AMO
  assign agu_req_alu_swap = 1'b0;
  assign agu_req_alu_and  = 1'b0;
  assign agu_req_alu_or   = 1'b0;
  assign agu_req_alu_xor  = 1'b0;
  assign agu_req_alu_max  = 1'b0;
  assign agu_req_alu_min  = 1'b0;
  assign agu_req_alu_maxu = 1'b0;
  assign agu_req_alu_minu = 1'b0;
  `endif














  `ifndef E203_SUPPORT_UNALGNLDST
  `else
  !!!! ERROR: This UNALIGNED load/store is not supported, must be something wrong 
  `endif

  assign agu_i_ready =
      ( 1'b0
  `ifdef E203_SUPPORT_AMO
       | agu_i_algnamo 
  `endif
       ) ? state_last_exit_ena :
      (agu_icb_cmd_ready & agu_o_ready) ;
  


  assign agu_i_longpipe = agu_i_algnldst;
  









  assign agu_o_valid = 
        `ifdef E203_SUPPORT_AMO



      icb_sta_is_last 
        `endif


      |(
         agu_i_valid & ( agu_i_algnldst 
        `ifndef E203_SUPPORT_UNALGNLDST




           | agu_i_unalgnldst
        `endif
        `ifdef E203_SUPPORT_AMO
           | agu_i_unalgnamo 
        `endif
         )





          & agu_icb_cmd_ready
      );

  assign agu_o_wbck_wdat = {`E203_XLEN{1'b0 }}
       `ifdef E203_SUPPORT_AMO
                    | ({`E203_XLEN{agu_i_algnamo  }} & leftover_r) 
                    | ({`E203_XLEN{agu_i_unalgnamo}} & `E203_XLEN'b0) 
       `endif
       ;

  assign agu_o_cmt_buserr = (1'b0 
                `ifdef E203_SUPPORT_AMO
                      | (agu_i_algnamo    & leftover_err_r) 
                      | (agu_i_unalgnamo  & 1'b0) 
                `endif
                      )
                ;
  assign agu_o_cmt_badaddr = agu_icb_cmd_addr;


  assign agu_o_cmt_misalgn = (1'b0
                `ifdef E203_SUPPORT_AMO
                       | agu_i_unalgnamo 
                `endif
                       | (agu_i_unalgnldst)
                       )
                       ;
  assign agu_o_cmt_ld      = agu_i_load & (~agu_i_excl); 
  assign agu_o_cmt_stamo   = agu_i_store | agu_i_amo | agu_i_excl;

  

  assign agu_o_wbck_err = agu_o_cmt_buserr | agu_o_cmt_misalgn
                          ;


  assign agu_icb_rsp_ready = 1'b1;


  

  assign agu_icb_cmd_valid = 
            ((agu_i_algnldst & agu_i_valid)


              & (agu_o_ready)
            )
          `ifdef E203_SUPPORT_AMO
            | (agu_i_algnamo & (
                         (icb_sta_is_idle & agu_i_valid 


                             & agu_o_ready)
                       | (icb_sta_is_wait2nd)))
            | (agu_i_unalgnamo & 1'b0) 
          `endif
            ;
  assign agu_icb_cmd_addr = agu_req_alu_res[`E203_ADDR_SIZE-1:0];

  assign agu_icb_cmd_read = 
            (agu_i_algnldst & agu_i_load) 
          `ifdef E203_SUPPORT_AMO
          | (agu_i_algnamo & icb_sta_is_idle & 1'b1)
          | (agu_i_algnamo & icb_sta_is_wait2nd & 1'b0) 
          `endif
          ;






  wire [`E203_XLEN-1:0] algnst_wdata = 
            ({`E203_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
          | ({`E203_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
          | ({`E203_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
  wire [`E203_XLEN/8-1:0] algnst_wmask = 
            ({`E203_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_icb_cmd_addr[1:0]))
          | ({`E203_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_icb_cmd_addr[1],1'b0}))
          | ({`E203_XLEN/8{agu_i_size_w }} & (4'b1111));

          
  assign agu_icb_cmd_wdata = 
  `ifdef E203_SUPPORT_AMO
      agu_i_amo ? leftover_1_r :
  `endif
      algnst_wdata;

  assign agu_icb_cmd_wmask =
  `ifdef E203_SUPPORT_AMO

      agu_i_amo ? (leftover_err_r ? 4'h0 : 4'hF) :
  `endif
      algnst_wmask; 

  assign agu_icb_cmd_back2agu = 1'b0 
             `ifdef E203_SUPPORT_AMO
                | agu_i_algnamo  
             `endif
             ;

  assign agu_icb_cmd_lock     = 1'b0 
             `ifdef E203_SUPPORT_AMO
                 | (agu_i_algnamo & icb_sta_is_idle)
             `endif
                 ;
  assign agu_icb_cmd_excl     = 1'b0
             `ifdef E203_SUPPORT_AMO
                 | agu_i_excl
             `endif
                 ;

  assign agu_icb_cmd_itag     = agu_i_itag;
  assign agu_icb_cmd_usign    = agu_i_usign;
  assign agu_icb_cmd_size     = 
                agu_i_size;


endmodule