data/full_repos/permissive/514758517/design.v
1: b'%Error: data/full_repos/permissive/514758517/design.v:2: Cannot find include file: logic_top.v\n`include "logic_top.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logic_top.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logic_top.v.v\n             data/full_repos/permissive/514758517,data/full_repos/permissive/514758517/logic_top.v.sv\n             logic_top.v\n             logic_top.v.v\n             logic_top.v.sv\n             obj_dir/logic_top.v\n             obj_dir/logic_top.v.v\n             obj_dir/logic_top.v.sv\n%Error: data/full_repos/permissive/514758517/design.v:3: Cannot find include file: arth_top.v\n`include "arth_top.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module design_top(clk , rstn , in1 , in2 , opcode , out_top);
	input clk;
	input rstn;
	input [2:0]opcode;
	input signed [4:0]in1;
	input signed [4:0]in2;
	output reg signed [8:0]out_top;
	
	wire [8:0]out_arth , out_logic;
	
	arth_top    u0_arth_top  (in1 , in2 , opcode , out_arth);
	logic_top   u1_logic_top (in1 , in2 , opcode , out_logic);   
	
  	always@(posedge clk , negedge rstn)
		begin
			if(!rstn)
				out_top <= 0;
			else
				begin
					case(opcode[2])
						0 : out_top <= out_arth;
						1 : out_top <= out_logic;
					endcase
				end
		end
  
endmodule
module design_top(clk , rstn , in1 , in2 , opcode , out_top);

	input clk;
	input rstn;
	input [2:0]opcode;
	input signed [4:0]in1;
	input signed [4:0]in2;
	output reg signed [8:0]out_top;
	
	wire [8:0]out_arth , out_logic;
	
	arth_top    u0_arth_top  (in1 , in2 , opcode , out_arth);
	logic_top   u1_logic_top (in1 , in2 , opcode , out_logic);   
	
  	always@(posedge clk , negedge rstn)
		begin
			if(!rstn)
				out_top <= 0;
			else
				begin
					case(opcode[2])
						0 : out_top <= out_arth;
						1 : out_top <= out_logic;
					endcase
				end
		end
  
endmodule