data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/ece241_2014_q5b/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/ece241_2014_q5b,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/ece241_2014_q5b/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire x,
    output wire z
);

  parameter STATE_A = 1'b0;
  parameter STATE_B = 1'b1;

  reg  [1:0] state;
  wire [1:0] next_state;


  assign next_state[STATE_A] = state[STATE_A] & ~x;
  assign next_state[STATE_B] = state[STATE_A] & x | state[STATE_B];


  always @(posedge clk, posedge areset) begin
    if (areset) state <= (1'b1 << STATE_A);
    else if (clk) state <= next_state;
  end


  assign z = state[STATE_A] & x | state[STATE_B] & ~x;
endmodule
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire x,
    output wire z
);


  parameter STATE_A = 1'b0;
  parameter STATE_B = 1'b1;

  reg  [1:0] state;
  wire [1:0] next_state;


  assign next_state[STATE_A] = state[STATE_A] & ~x;
  assign next_state[STATE_B] = state[STATE_A] & x | state[STATE_B];


  always @(posedge clk, posedge areset) begin
    if (areset) state <= (1'b1 << STATE_A);
    else if (clk) state <= next_state;
  end


  assign z = state[STATE_A] & x | state[STATE_B] & ~x;
endmodule