data/full_repos/permissive/505514178/source_code/if_id.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505514178/source_code/if_id.v:20: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h13\' generates 8 bits.\n                                                                           : ... In instance if_id\ncode_IF_ID = 8\'h0000_0013;    \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module if_id(
	input clk,
	input reset,
	input enable,
	input clear,
	input [31:0] code_IM,
	input [31:0] PC,
	input prediction,
	output reg [31:0] code_IF_ID,
	output reg [31:0] PC_IF_ID,
	output reg prediction_IF_ID
    );

always@(posedge clk,negedge reset)
begin
if(reset == 0 || clear == 1)
begin
code_IF_ID = 8'h0000_0013;
PC_IF_ID = 0;
prediction_IF_ID = 0;
end
else if(enable == 1)
begin
code_IF_ID = code_IM;
PC_IF_ID = PC;
prediction_IF_ID = prediction;
end
end
endmodule
module if_id(
	input clk,
	input reset,
	input enable,
	input clear,
	input [31:0] code_IM,
	input [31:0] PC,
	input prediction,
	output reg [31:0] code_IF_ID,
	output reg [31:0] PC_IF_ID,
	output reg prediction_IF_ID
    );


always@(posedge clk,negedge reset)
begin
if(reset == 0 || clear == 1)
begin
code_IF_ID = 8'h0000_0013;
PC_IF_ID = 0;
prediction_IF_ID = 0;
end
else if(enable == 1)
begin
code_IF_ID = code_IM;
PC_IF_ID = PC;
prediction_IF_ID = prediction;
end
end
endmodule