data/full_repos/permissive/433367655/Source/RF.v
data/verilator_xmls/97c08ed7-2954-4e59-9564-471848fb601d.xml
module RF(
    input clk,
    input we3,
    input [4:0] a1,
    input [4:0] a2,
    input [4:0] a3,
    input [31:0] wd3,
    input rst,
    
    output [31:0] rd1,
    output [31:0] rd2
    );
    

    reg [31:0] rf [0:31];

    assign rd1 = (a1 != 0) ? rf[a1] : 0;
    assign rd2 = (a2 != 0) ? rf[a2] : 0;   
 
    integer i;

    always @ (posedge clk)
        if (rst) begin 
            for (i=0; i<31; i=i+1) begin
               rf[i] <= 32'd0;
            end
        end 
        else begin
            if (we3) rf[a3] <= wd3;
        end
        

endmodule
module RF(
    input clk,
    input we3,
    input [4:0] a1,
    input [4:0] a2,
    input [4:0] a3,
    input [31:0] wd3,
    input rst,
    
    output [31:0] rd1,
    output [31:0] rd2
    );

    

    reg [31:0] rf [0:31];

    assign rd1 = (a1 != 0) ? rf[a1] : 0;
    assign rd2 = (a2 != 0) ? rf[a2] : 0;   
 
    integer i;

    always @ (posedge clk)
        if (rst) begin 
            for (i=0; i<31; i=i+1) begin
               rf[i] <= 32'd0;
            end
        end 
        else begin
            if (we3) rf[a3] <= wd3;
        end
        

endmodule