data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv:42: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport PkgEth100gLbus::*;\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module eth_100g_lbus2axi #(
   parameter FIFO_DEPTH = 5,
   parameter NUM_SEG = 4
)
(


  AxiStreamIf.master    axis,


  input lbus_t lbus_in [NUM_SEG-1:0]

);

  localparam SEG_BYTES        = SEG_DATA_WIDTH/8;
  localparam SEG_MTY_WIDTH    = $clog2(SEG_BYTES);
  localparam SEG_SHMEAR_WIDTH = SEG_DATA_WIDTH + SEG_MTY_WIDTH + 4;





  lbus_t  lbus_fout_p[NUM_SEG-1:0];
  lbus_t  lbus_fout[NUM_SEG-1:0];

  logic                push;
  logic [NUM_SEG-1:0]  pop;

  logic [NUM_SEG-1:0]  full;
  logic [NUM_SEG-1:0]  empty;


  assign push = lbus_in[0].ena;


  generate
  genvar b1,gseg1;
  begin : gen_seg_fifo
    for(gseg1 = 0; gseg1 < NUM_SEG; gseg1=gseg1+1) begin






      always_comb begin
        if (push) begin
          assert (!full[gseg1]) else $error("Pushing full fifo!");
        end
      end


      (* max_fanout = 75 *) logic [4:0] a;

      for (b1=0;b1<SEG_DATA_WIDTH;b1=b1+1) begin : gen_srl_data
        SRLC32E srl_data(
          .Q(lbus_fout_p[gseg1].data[b1]), .Q31(),
          .A(a),
          .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].data[b1])
        );
      end
      for (b1=0;b1<SEG_MTY_WIDTH;b1=b1+1) begin : gen_srl_mty
        SRLC32E srl_mty(
          .Q(lbus_fout_p[gseg1].mty[b1]), .Q31(),
          .A(a),
          .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].mty[b1])
        );
      end
      SRLC32E srl_err(
        .Q(lbus_fout_p[gseg1].err), .Q31(),
        .A(a),
        .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].err)
      );


      logic my_empty;
      always @(posedge axis.clk)
      begin
        if(axis.rst) begin
          a <= 0;
          my_empty <= 1;
          full[gseg1] <= 0;
        end else if(pop[gseg1] & ~push) begin
          full[gseg1] <= 0;
          if(a==0) begin
            my_empty <= 1;
          end else begin
            a <= a - 1;
          end
        end else if(push & ~pop[gseg1]) begin
          my_empty <= 0;
          if(~my_empty) begin
            a <= a + 1;
          end
          if(a == 30) begin
            full[gseg1] <= 1;
          end
        end
      end





      logic [4:0]  w_ptr,r_ptr,r_ptr_d,fullness;
      logic [31:0] ena_mem, sop_mem, eop_mem;







      logic push_dff;


      always_comb begin
        if (pop[gseg1]) begin
          r_ptr_d = r_ptr+1;
        end else begin
          r_ptr_d = r_ptr;
        end
        fullness = w_ptr-r_ptr_d;
        push_dff = (fullness != 0) & (pop[gseg1] | empty[gseg1]);
      end




      always @(posedge axis.clk)
      begin
        if(axis.rst) begin
          ena_mem <= '0;
          sop_mem <= '0;
          eop_mem <= '0;
          lbus_fout_p[gseg1].ena <= 1'b0;
          lbus_fout_p[gseg1].sop <= 1'b0;
          lbus_fout_p[gseg1].eop <= 1'b0;
          w_ptr <= 0;
          r_ptr <= 0;
          empty[gseg1] <= 1'b1;
        end else begin
          if(push) begin
            ena_mem[w_ptr] <= lbus_in[gseg1].ena;
            sop_mem[w_ptr] <= lbus_in[gseg1].sop;
            eop_mem[w_ptr] <= lbus_in[gseg1].eop;
            w_ptr <= w_ptr+1;
          end

          r_ptr <= r_ptr_d;

          if (push_dff) begin
            empty[gseg1] <= 1'b0;
            lbus_fout_p[gseg1].ena <= ena_mem[r_ptr_d];
            lbus_fout_p[gseg1].sop <= sop_mem[r_ptr_d];
            lbus_fout_p[gseg1].eop <= eop_mem[r_ptr_d];
          end else if (pop[gseg1]) begin
            empty[gseg1] <= 1'b1;
          end
        end
      end


      always_comb begin

        lbus_fout[gseg1] = lbus_fout_p[gseg1];
        if (empty[gseg1]) begin

          lbus_fout[gseg1].ena = 0;
          lbus_fout[gseg1].err = 0;
          lbus_fout[gseg1].eop = 0;
          lbus_fout[gseg1].sop = 0;
          lbus_fout[gseg1].mty = '0;
        end else begin

          lbus_fout[gseg1].eop = lbus_fout_p[gseg1].eop && lbus_fout_p[gseg1].ena;
          lbus_fout[gseg1].sop = lbus_fout_p[gseg1].sop && lbus_fout_p[gseg1].ena;
          lbus_fout[gseg1].err = lbus_fout_p[gseg1].err && lbus_fout_p[gseg1].ena;
        end
      end

    end
  end : gen_seg_fifo
  endgenerate


  lbus_t lbus_rot [NUM_SEG-1:0];


  logic  [NUM_SEG-1:0]         ena;
  logic  [NUM_SEG-1:0]         sop;
  logic  [NUM_SEG-1:0]         eop;
  logic  [NUM_SEG-1:0]         rot_ena;
  logic  [NUM_SEG-1:0]         rot_sop;
  logic  [NUM_SEG-1:0]         rot_eop;
  logic  [NUM_SEG-1:0]         rot_empty;

  always_comb begin
    foreach (rot_ena[s]) begin
      ena[s] = lbus_fout[s].ena;
      sop[s] = lbus_fout[s].sop;
      eop[s] = lbus_fout[s].eop;
      rot_ena[s] = lbus_rot[s].ena;
      rot_sop[s] = lbus_rot[s].sop;
      rot_eop[s] = lbus_rot[s].eop;
    end
  end


  logic  [$clog2(NUM_SEG)-1:0] rot;




  logic                        no_sop;
  logic                        no_eop;
  logic                        no_ena;
  logic                        some_empty;
  logic                        send_idle;

  always_comb begin
    no_sop     = sop == 0;
    no_eop     = eop == 0;
    no_ena     = ena == 0;

    some_empty = 1'b0;
    foreach (ena[seg]) begin : segment_loop
      if (ena[seg] == 0) begin
        some_empty = 1'b1;
      end
    end : segment_loop;
  end

  always_comb begin
    if (no_ena) begin
      send_idle = 1'b0;
    end else begin



      send_idle = no_eop & some_empty;
    end
  end





























  logic [NUM_SEG-1:0] rot_xfer_now;
  logic [NUM_SEG-1:0] mask  [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] m1hot [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] meop  [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] match;

  always_comb begin
    rot_xfer_now = '0;
    foreach (rot_eop[s]) begin










      mask[s]  = 2**(s+1)-1;





      m1hot[s] = 2**s;

      meop[s]  = rot_eop & mask[s];

      match[s] = meop[s] == m1hot[s];
      if (match[s]) begin
        rot_xfer_now = mask[s];
      end
    end
  end


  logic [NUM_SEG-1:0] xfer_now;
  logic [NUM_SEG-1:0] filler_seg;

  always_comb begin
    if (send_idle)
      xfer_now = '0;
    else if (no_eop | no_sop)
      xfer_now = '1;
    else

      xfer_now = {rot_xfer_now,rot_xfer_now} >> (NUM_SEG - rot);
  end


  assign filler_seg = ~ena & ~empty;

  assign pop = (xfer_now | filler_seg) & ~empty;




  logic  [$clog2(NUM_SEG)-1:0]  next_rot;
  always_comb begin
    next_rot = 0;
    foreach (rot_empty[s]) begin
      if (~rot_empty[s] & lbus_rot[s].sop) begin
        next_rot = s;
      end
    end
  end

  always @(posedge axis.clk)
  begin
    if(axis.rst) begin
      rot <= '0;

    end else if( no_ena ) begin
      rot <= '0;

    end else if( no_sop & ~no_eop & some_empty) begin
      rot <= '0;

    end else if( ~no_sop ) begin
      rot <= rot+next_rot;
    end
  end




  generate
  genvar b2,gseg2;
  begin : rotate_lbus

    for(b2 = 0; b2 < SEG_SHMEAR_WIDTH; b2=b2+1) begin
      logic [NUM_SEG-1:0] slice, slice_rotated;


      for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
        assign slice[gseg2] = lbus_fout[gseg2][b2];
      end


      assign slice_rotated = {slice,slice} >> rot;


      for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
        assign lbus_rot[gseg2][b2] = slice_rotated[gseg2];
      end

    end
  end : rotate_lbus
  endgenerate

  always_comb begin : rotate_data_valid
    rot_empty = {empty,empty} >> rot;
  end : rotate_data_valid







  lbus_t lbus_out [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] axi_seg_valid;

  always_ff @(posedge axis.clk)
  begin
    if (axis.rst) begin
      foreach (lbus_out[seg]) begin : segment_loop
        lbus_out[seg] <= '0;
      end
      axi_seg_valid   <= '0;
    end else begin
      lbus_out <= lbus_rot;
      if (send_idle)
        axi_seg_valid <= '0;
      else if (no_eop)
        axi_seg_valid <= '1;
      else
        axi_seg_valid <= rot_xfer_now;
      end
  end




  logic    [axis.DATA_WIDTH - 1:0]           axis_tdata_w;
  logic    [$clog2(axis.DATA_WIDTH/8) - 1:0] axis_tuser_bytes_w;
  logic    [axis.DATA_WIDTH/8 - 1:0]         axis_tkeep_w;
  logic    [NUM_SEG-1:0]                     axis_tlast_w;
  logic    [NUM_SEG-1:0]                     axis_tvalid_w;
  logic    [NUM_SEG-1:0]                     axis_tuser_err_w;

  always_comb begin : axis_translate
    axis_tuser_bytes_w = 'd0;
    foreach (axis_tvalid_w[seg]) begin : segment_loop
      axis_tvalid_w[seg]     = lbus_out[seg].ena & axi_seg_valid[seg];
      axis_tlast_w[seg]      = lbus_out[seg].eop;
      axis_tuser_err_w[seg]  = lbus_out[seg].err;


      if (lbus_out[seg].ena && axi_seg_valid[seg]) begin
        axis_tuser_bytes_w += SEG_DATA_WIDTH/8 - lbus_out[seg].mty;
      end









      for(int b = 0; b < SEG_BYTES; b=b+1) begin : tdata_loop



















        axis_tdata_w[((seg+1)*axis.DATA_WIDTH/NUM_SEG-8-b*8) +: 8] = lbus_out[seg].data[b*8 +: 8];
      end : tdata_loop
    end : segment_loop
  end : axis_translate


  always_comb begin
    axis_tkeep_w = '1;
    if (axis_tlast_w != 0 && axis_tuser_bytes_w != 0) begin
      foreach(axis_tkeep_w[b]) begin
        axis_tkeep_w[b] = axis_tuser_bytes_w > b;
      end
    end
  end





  localparam AXIS_MTY_WIDTH = $clog2(axis.BYTES_PER_WORD);

  always_ff @(posedge axis.clk)
  begin
    if (axis.rst) begin
      axis.tdata     <= '0;
      axis.tvalid    <= 1'b0;
      axis.tlast     <= 1'b0;
      axis.tuser     <= '0;
      axis.tkeep     <= '0;
    end else begin
      axis.tdata     <= axis_tdata_w;
      axis.tvalid    <= |axis_tvalid_w;
      axis.tlast     <= |axis_tlast_w;

      if (axis.TKEEP == 1) begin
        axis.tkeep     <= axis_tkeep_w;
      end else begin
        axis.tkeep     <= 'X;
      end


      axis.tuser[AXIS_MTY_WIDTH-1:0]  <= axis_tuser_bytes_w;

      axis.tuser[AXIS_MTY_WIDTH]      <= |axis_tuser_err_w;
    end
  end

endmodule
module eth_100g_lbus2axi #(
   parameter FIFO_DEPTH = 5,
   parameter NUM_SEG = 4
)
(


  AxiStreamIf.master    axis,


  input lbus_t lbus_in [NUM_SEG-1:0]

);


  localparam SEG_BYTES        = SEG_DATA_WIDTH/8;
  localparam SEG_MTY_WIDTH    = $clog2(SEG_BYTES);
  localparam SEG_SHMEAR_WIDTH = SEG_DATA_WIDTH + SEG_MTY_WIDTH + 4;





  lbus_t  lbus_fout_p[NUM_SEG-1:0];
  lbus_t  lbus_fout[NUM_SEG-1:0];

  logic                push;
  logic [NUM_SEG-1:0]  pop;

  logic [NUM_SEG-1:0]  full;
  logic [NUM_SEG-1:0]  empty;


  assign push = lbus_in[0].ena;


  generate
  genvar b1,gseg1;
  begin : gen_seg_fifo
    for(gseg1 = 0; gseg1 < NUM_SEG; gseg1=gseg1+1) begin






      always_comb begin
        if (push) begin
          assert (!full[gseg1]) else $error("Pushing full fifo!");
        end
      end


      (* max_fanout = 75 *) logic [4:0] a;

      for (b1=0;b1<SEG_DATA_WIDTH;b1=b1+1) begin : gen_srl_data
        SRLC32E srl_data(
          .Q(lbus_fout_p[gseg1].data[b1]), .Q31(),
          .A(a),
          .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].data[b1])
        );
      end
      for (b1=0;b1<SEG_MTY_WIDTH;b1=b1+1) begin : gen_srl_mty
        SRLC32E srl_mty(
          .Q(lbus_fout_p[gseg1].mty[b1]), .Q31(),
          .A(a),
          .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].mty[b1])
        );
      end
      SRLC32E srl_err(
        .Q(lbus_fout_p[gseg1].err), .Q31(),
        .A(a),
        .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].err)
      );


      logic my_empty;
      always @(posedge axis.clk)
      begin
        if(axis.rst) begin
          a <= 0;
          my_empty <= 1;
          full[gseg1] <= 0;
        end else if(pop[gseg1] & ~push) begin
          full[gseg1] <= 0;
          if(a==0) begin
            my_empty <= 1;
          end else begin
            a <= a - 1;
          end
        end else if(push & ~pop[gseg1]) begin
          my_empty <= 0;
          if(~my_empty) begin
            a <= a + 1;
          end
          if(a == 30) begin
            full[gseg1] <= 1;
          end
        end
      end





      logic [4:0]  w_ptr,r_ptr,r_ptr_d,fullness;
      logic [31:0] ena_mem, sop_mem, eop_mem;







      logic push_dff;


      always_comb begin
        if (pop[gseg1]) begin
          r_ptr_d = r_ptr+1;
        end else begin
          r_ptr_d = r_ptr;
        end
        fullness = w_ptr-r_ptr_d;
        push_dff = (fullness != 0) & (pop[gseg1] | empty[gseg1]);
      end




      always @(posedge axis.clk)
      begin
        if(axis.rst) begin
          ena_mem <= '0;
          sop_mem <= '0;
          eop_mem <= '0;
          lbus_fout_p[gseg1].ena <= 1'b0;
          lbus_fout_p[gseg1].sop <= 1'b0;
          lbus_fout_p[gseg1].eop <= 1'b0;
          w_ptr <= 0;
          r_ptr <= 0;
          empty[gseg1] <= 1'b1;
        end else begin
          if(push) begin
            ena_mem[w_ptr] <= lbus_in[gseg1].ena;
            sop_mem[w_ptr] <= lbus_in[gseg1].sop;
            eop_mem[w_ptr] <= lbus_in[gseg1].eop;
            w_ptr <= w_ptr+1;
          end

          r_ptr <= r_ptr_d;

          if (push_dff) begin
            empty[gseg1] <= 1'b0;
            lbus_fout_p[gseg1].ena <= ena_mem[r_ptr_d];
            lbus_fout_p[gseg1].sop <= sop_mem[r_ptr_d];
            lbus_fout_p[gseg1].eop <= eop_mem[r_ptr_d];
          end else if (pop[gseg1]) begin
            empty[gseg1] <= 1'b1;
          end
        end
      end


      always_comb begin

        lbus_fout[gseg1] = lbus_fout_p[gseg1];
        if (empty[gseg1]) begin

          lbus_fout[gseg1].ena = 0;
          lbus_fout[gseg1].err = 0;
          lbus_fout[gseg1].eop = 0;
          lbus_fout[gseg1].sop = 0;
          lbus_fout[gseg1].mty = '0;
        end else begin

          lbus_fout[gseg1].eop = lbus_fout_p[gseg1].eop && lbus_fout_p[gseg1].ena;
          lbus_fout[gseg1].sop = lbus_fout_p[gseg1].sop && lbus_fout_p[gseg1].ena;
          lbus_fout[gseg1].err = lbus_fout_p[gseg1].err && lbus_fout_p[gseg1].ena;
        end
      end

    end
  end : gen_seg_fifo
  endgenerate


  lbus_t lbus_rot [NUM_SEG-1:0];


  logic  [NUM_SEG-1:0]         ena;
  logic  [NUM_SEG-1:0]         sop;
  logic  [NUM_SEG-1:0]         eop;
  logic  [NUM_SEG-1:0]         rot_ena;
  logic  [NUM_SEG-1:0]         rot_sop;
  logic  [NUM_SEG-1:0]         rot_eop;
  logic  [NUM_SEG-1:0]         rot_empty;

  always_comb begin
    foreach (rot_ena[s]) begin
      ena[s] = lbus_fout[s].ena;
      sop[s] = lbus_fout[s].sop;
      eop[s] = lbus_fout[s].eop;
      rot_ena[s] = lbus_rot[s].ena;
      rot_sop[s] = lbus_rot[s].sop;
      rot_eop[s] = lbus_rot[s].eop;
    end
  end


  logic  [$clog2(NUM_SEG)-1:0] rot;




  logic                        no_sop;
  logic                        no_eop;
  logic                        no_ena;
  logic                        some_empty;
  logic                        send_idle;

  always_comb begin
    no_sop     = sop == 0;
    no_eop     = eop == 0;
    no_ena     = ena == 0;

    some_empty = 1'b0;
    foreach (ena[seg]) begin : segment_loop
      if (ena[seg] == 0) begin
        some_empty = 1'b1;
      end
    end : segment_loop;
  end

  always_comb begin
    if (no_ena) begin
      send_idle = 1'b0;
    end else begin



      send_idle = no_eop & some_empty;
    end
  end





























  logic [NUM_SEG-1:0] rot_xfer_now;
  logic [NUM_SEG-1:0] mask  [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] m1hot [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] meop  [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] match;

  always_comb begin
    rot_xfer_now = '0;
    foreach (rot_eop[s]) begin










      mask[s]  = 2**(s+1)-1;





      m1hot[s] = 2**s;

      meop[s]  = rot_eop & mask[s];

      match[s] = meop[s] == m1hot[s];
      if (match[s]) begin
        rot_xfer_now = mask[s];
      end
    end
  end


  logic [NUM_SEG-1:0] xfer_now;
  logic [NUM_SEG-1:0] filler_seg;

  always_comb begin
    if (send_idle)
      xfer_now = '0;
    else if (no_eop | no_sop)
      xfer_now = '1;
    else

      xfer_now = {rot_xfer_now,rot_xfer_now} >> (NUM_SEG - rot);
  end


  assign filler_seg = ~ena & ~empty;

  assign pop = (xfer_now | filler_seg) & ~empty;




  logic  [$clog2(NUM_SEG)-1:0]  next_rot;
  always_comb begin
    next_rot = 0;
    foreach (rot_empty[s]) begin
      if (~rot_empty[s] & lbus_rot[s].sop) begin
        next_rot = s;
      end
    end
  end

  always @(posedge axis.clk)
  begin
    if(axis.rst) begin
      rot <= '0;

    end else if( no_ena ) begin
      rot <= '0;

    end else if( no_sop & ~no_eop & some_empty) begin
      rot <= '0;

    end else if( ~no_sop ) begin
      rot <= rot+next_rot;
    end
  end




  generate
  genvar b2,gseg2;
  begin : rotate_lbus

    for(b2 = 0; b2 < SEG_SHMEAR_WIDTH; b2=b2+1) begin
      logic [NUM_SEG-1:0] slice, slice_rotated;


      for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
        assign slice[gseg2] = lbus_fout[gseg2][b2];
      end


      assign slice_rotated = {slice,slice} >> rot;


      for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
        assign lbus_rot[gseg2][b2] = slice_rotated[gseg2];
      end

    end
  end : rotate_lbus
  endgenerate

  always_comb begin : rotate_data_valid
    rot_empty = {empty,empty} >> rot;
  end : rotate_data_valid







  lbus_t lbus_out [NUM_SEG-1:0];
  logic [NUM_SEG-1:0] axi_seg_valid;

  always_ff @(posedge axis.clk)
  begin
    if (axis.rst) begin
      foreach (lbus_out[seg]) begin : segment_loop
        lbus_out[seg] <= '0;
      end
      axi_seg_valid   <= '0;
    end else begin
      lbus_out <= lbus_rot;
      if (send_idle)
        axi_seg_valid <= '0;
      else if (no_eop)
        axi_seg_valid <= '1;
      else
        axi_seg_valid <= rot_xfer_now;
      end
  end




  logic    [axis.DATA_WIDTH - 1:0]           axis_tdata_w;
  logic    [$clog2(axis.DATA_WIDTH/8) - 1:0] axis_tuser_bytes_w;
  logic    [axis.DATA_WIDTH/8 - 1:0]         axis_tkeep_w;
  logic    [NUM_SEG-1:0]                     axis_tlast_w;
  logic    [NUM_SEG-1:0]                     axis_tvalid_w;
  logic    [NUM_SEG-1:0]                     axis_tuser_err_w;

  always_comb begin : axis_translate
    axis_tuser_bytes_w = 'd0;
    foreach (axis_tvalid_w[seg]) begin : segment_loop
      axis_tvalid_w[seg]     = lbus_out[seg].ena & axi_seg_valid[seg];
      axis_tlast_w[seg]      = lbus_out[seg].eop;
      axis_tuser_err_w[seg]  = lbus_out[seg].err;


      if (lbus_out[seg].ena && axi_seg_valid[seg]) begin
        axis_tuser_bytes_w += SEG_DATA_WIDTH/8 - lbus_out[seg].mty;
      end









      for(int b = 0; b < SEG_BYTES; b=b+1) begin : tdata_loop



















        axis_tdata_w[((seg+1)*axis.DATA_WIDTH/NUM_SEG-8-b*8) +: 8] = lbus_out[seg].data[b*8 +: 8];
      end : tdata_loop
    end : segment_loop
  end : axis_translate


  always_comb begin
    axis_tkeep_w = '1;
    if (axis_tlast_w != 0 && axis_tuser_bytes_w != 0) begin
      foreach(axis_tkeep_w[b]) begin
        axis_tkeep_w[b] = axis_tuser_bytes_w > b;
      end
    end
  end





  localparam AXIS_MTY_WIDTH = $clog2(axis.BYTES_PER_WORD);

  always_ff @(posedge axis.clk)
  begin
    if (axis.rst) begin
      axis.tdata     <= '0;
      axis.tvalid    <= 1'b0;
      axis.tlast     <= 1'b0;
      axis.tuser     <= '0;
      axis.tkeep     <= '0;
    end else begin
      axis.tdata     <= axis_tdata_w;
      axis.tvalid    <= |axis_tvalid_w;
      axis.tlast     <= |axis_tlast_w;

      if (axis.TKEEP == 1) begin
        axis.tkeep     <= axis_tkeep_w;
      end else begin
        axis.tkeep     <= 'X;
      end


      axis.tuser[AXIS_MTY_WIDTH-1:0]  <= axis_tuser_bytes_w;

      axis.tuser[AXIS_MTY_WIDTH]      <= |axis_tuser_err_w;
    end
  end

endmodule