data/full_repos/permissive/514758517/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514758517/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/514758517/testbench.v:28: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/514758517/testbench.v:37: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514758517/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #6;\n      ^\n%Error: data/full_repos/permissive/514758517/testbench.v:64: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("design_top.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/514758517/testbench.v:65: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0 , design_top_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/514758517/testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n      #200 $finish;\n      ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module design_top_tb;
  reg clk , rstn;
  reg signed [4:0]in1;
  reg signed [4:0]in2;
  reg [2:0]opcode;
  wire signed [8:0]out_top;
  
  design_top DUT(clk , rstn , in1 , in2 , opcode , out_top);
  
  initial
    begin
      clk = 1'b1;
      forever
        #5 clk = ~clk;
    end
  
  task initialize;
    begin
      {in1 , in2 , opcode} = 0;

      rstn = 1;
    end
  endtask
  
  task reset_input;
    begin
      @(negedge clk)
      rstn = 1'b0;
      @(negedge clk)
      rstn = 1'b1;
    end
  endtask
  
  task data_input(input [4:0]a , input [4:0]b , input [2:0]c);
    begin
      @(negedge clk)
      in1 = a;
      in2 = b;
      opcode = c;
      if(c == 0)
        $display("ADDITION");
      else if (c == 1)
        $display("SUBTRACTION");
      else if (c == 2)
        $display("MULTIPLICATION");
      else if (c == 3)
        $display("DIVISION");
      else if (c == 4)
        $display("LOGICAL OR");
      else if (c == 5)
        $display("LOGICAL AND");
      else if (c == 6)
        $display("LOGICAL NAND");
      else if (c == 7)
        $display("LOGICAL NOR");
      #6;
      $display($time, " opcode = %d , in1 = %d, in2 = %d, out = %d", opcode , in1 , in2 , out_top);
    end
  endtask
  
  initial
    begin
      $dumpfile("design_top.vcd");
      $dumpvars(0 , design_top_tb);

      initialize;
      reset_input;
      data_input(4'd2 , 4'd3 , 0);
      data_input(-4'd2 , 4'd6 , 1);

      data_input(4'd2 , 4'd5 , 2);
      data_input(4'd12 , 4'd4 , 3);
      reset_input;
      data_input(4'd6 , -4'd6 , 4);
      data_input(4'd2 , 4'd0 , 5);

      data_input(-4'd8 , 4'd5 , 6);
      data_input(4'd0 , 4'd0 , 7);


      #200 $finish;
    end
endmodule
module design_top_tb;

  reg clk , rstn;
  reg signed [4:0]in1;
  reg signed [4:0]in2;
  reg [2:0]opcode;
  wire signed [8:0]out_top;
  
  design_top DUT(clk , rstn , in1 , in2 , opcode , out_top);
  
  initial
    begin
      clk = 1'b1;
      forever
        #5 clk = ~clk;
    end
  
  task initialize;
    begin
      {in1 , in2 , opcode} = 0;

      rstn = 1;
    end
  endtask
  
  task reset_input;
    begin
      @(negedge clk)
      rstn = 1'b0;
      @(negedge clk)
      rstn = 1'b1;
    end
  endtask
  
  task data_input(input [4:0]a , input [4:0]b , input [2:0]c);
    begin
      @(negedge clk)
      in1 = a;
      in2 = b;
      opcode = c;
      if(c == 0)
        $display("ADDITION");
      else if (c == 1)
        $display("SUBTRACTION");
      else if (c == 2)
        $display("MULTIPLICATION");
      else if (c == 3)
        $display("DIVISION");
      else if (c == 4)
        $display("LOGICAL OR");
      else if (c == 5)
        $display("LOGICAL AND");
      else if (c == 6)
        $display("LOGICAL NAND");
      else if (c == 7)
        $display("LOGICAL NOR");
      #6;
      $display($time, " opcode = %d , in1 = %d, in2 = %d, out = %d", opcode , in1 , in2 , out_top);
    end
  endtask
  
  initial
    begin
      $dumpfile("design_top.vcd");
      $dumpvars(0 , design_top_tb);

      initialize;
      reset_input;
      data_input(4'd2 , 4'd3 , 0);
      data_input(-4'd2 , 4'd6 , 1);

      data_input(4'd2 , 4'd5 , 2);
      data_input(4'd12 , 4'd4 , 3);
      reset_input;
      data_input(4'd6 , -4'd6 , 4);
      data_input(4'd2 , 4'd0 , 5);

      data_input(-4'd8 , 4'd5 , 6);
      data_input(4'd0 , 4'd0 , 7);


      #200 $finish;
    end
endmodule