data/full_repos/permissive/493019833/test/testcase/firrtl/RingModule/reference/RingModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RingModule/reference/RingModule.v:49: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                              : ... In instance RingModule.s_pad_1\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module RingModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);
    wire [10:0] _T_6;
    wire [9:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(10)) s_pad_1 (
        .y(_WTEMP_0),
        .in(1'sh0)
    );
    ADD_SIGNED #(.width(10)) s_add_2 (
        .y(_T_6),
        .a(io_in),
        .b(_WTEMP_0)
    );
    wire [9:0] _T_7;
    TAIL #(.width(11), .n(1)) tail_3 (
        .y(_T_7),
        .in(_T_6)
    );
    wire [9:0] _T_8;
    ASSINT #(.width(10)) assint_4 (
        .y(_T_8),
        .in(_T_7)
    );
    wire [11:0] _T_9;
    MUL2_SIGNED #(.width_a(2), .width_b(10)) s_mul2_5 (
        .y(_T_9),
        .a(2'sh1),
        .b(_T_8)
    );
    wire [9:0] _WTEMP_1;
    BITS #(.width(12), .high(9), .low(0)) bits_6 (
        .y(_WTEMP_1),
        .in(_T_9)
    );
    ASSINT #(.width(10)) assint_7 (
        .y(io_out),
        .in(_WTEMP_1)
    );
endmodule
module RingModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);

    wire [10:0] _T_6;
    wire [9:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(10)) s_pad_1 (
        .y(_WTEMP_0),
        .in(1'sh0)
    );
    ADD_SIGNED #(.width(10)) s_add_2 (
        .y(_T_6),
        .a(io_in),
        .b(_WTEMP_0)
    );
    wire [9:0] _T_7;
    TAIL #(.width(11), .n(1)) tail_3 (
        .y(_T_7),
        .in(_T_6)
    );
    wire [9:0] _T_8;
    ASSINT #(.width(10)) assint_4 (
        .y(_T_8),
        .in(_T_7)
    );
    wire [11:0] _T_9;
    MUL2_SIGNED #(.width_a(2), .width_b(10)) s_mul2_5 (
        .y(_T_9),
        .a(2'sh1),
        .b(_T_8)
    );
    wire [9:0] _WTEMP_1;
    BITS #(.width(12), .high(9), .low(0)) bits_6 (
        .y(_WTEMP_1),
        .in(_T_9)
    );
    ASSINT #(.width(10)) assint_7 (
        .y(io_out),
        .in(_WTEMP_1)
    );
endmodule