data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v:9: syntax error, unexpected ',', expecting ')'\nbuf u_buf1 (out_0, out_1, out_2, out_3, in);\n                        ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v:11: syntax error, unexpected ',', expecting ')'\nnot u_not0 (out_a, out_b, out_c, in);\n                        ^\n%Error: Exiting due to 2 error(s)\n"
module n_out_primitive();

wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c;
wire in;


buf u_buf0 (out,in);

buf u_buf1 (out_0, out_1, out_2, out_3, in);

not u_not0 (out_a, out_b, out_c, in);
 
endmodule
module n_out_primitive();


wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c;
wire in;


buf u_buf0 (out,in);

buf u_buf1 (out_0, out_1, out_2, out_3, in);

not u_not0 (out_a, out_b, out_c, in);
 
endmodule