data/full_repos/permissive/445929378/rng_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/rng_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/rng_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #12;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/rng_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/445929378/rng_tb.v:11: Cannot find file containing module: \'LFSR\'\n   LFSR uut (\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.sv\n             LFSR\n             LFSR.v\n             LFSR.sv\n             obj_dir/LFSR\n             obj_dir/LFSR.v\n             obj_dir/LFSR.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LFSR_tb;
   reg clk;
   reg rst;
   reg [63:0] seed;

   reg 	      input_ready;

   wire       output_valid;
   wire [63:0] rnd;

   LFSR uut (
	     .clk(clk), 
	     .rst(rst),
	     .input_tvalid(input_ready),
	     .seed(seed),
	     .output_tvalid(output_valid),
	     .rnd(rnd)
	     );
   
   initial begin
      clk = 0;
      forever
	#10 clk = ~clk;
   end
   
   initial begin
      seed = 64'hFFFFFFFFFFFFFFFF;
      input_ready = 1;
      rst = 1;
      #12;
      rst = 0;
      #100;
   end
endmodule
module LFSR_tb;

   reg clk;
   reg rst;
   reg [63:0] seed;

   reg 	      input_ready;

   wire       output_valid;
   wire [63:0] rnd;

   LFSR uut (
	     .clk(clk), 
	     .rst(rst),
	     .input_tvalid(input_ready),
	     .seed(seed),
	     .output_tvalid(output_valid),
	     .rnd(rnd)
	     );
   
   initial begin
      clk = 0;
      forever
	#10 clk = ~clk;
   end
   
   initial begin
      seed = 64'hFFFFFFFFFFFFFFFF;
      input_ready = 1;
      rst = 1;
      #12;
      rst = 0;
      #100;
   end
endmodule