data/full_repos/permissive/433122322/src/PSK.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433122322/src/PSK.v:15: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'N\' generates 1 bits.\n                                                                 : ... In instance PSK\n  address <= address + N + 1;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/433122322/src/PSK.v:19: Cannot find file containing module: \'sin_256\'\nsin_256 sin(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256.v\n             data/full_repos/permissive/433122322/src,data/full_repos/permissive/433122322/sin_256.sv\n             sin_256\n             sin_256.v\n             sin_256.sv\n             obj_dir/sin_256\n             obj_dir/sin_256.v\n             obj_dir/sin_256.sv\n%Error: data/full_repos/permissive/433122322/src/PSK.v:26: Cannot find file containing module: \'CLK\'\nCLK clk_div(\n^~~\n%Error: data/full_repos/permissive/433122322/src/PSK.v:32: Cannot find file containing module: \'MXL\'\nMXL mxl(\n^~~\n%Error: data/full_repos/permissive/433122322/src/PSK.v:37: Cannot find file containing module: \'choose_PSK\'\nchoose_PSK ch(\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module PSK(
	input clk, rst_n,
	input N,
	output [7: 0] dout_PSK
);


reg [7: 0] address;

always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address <= 0;
	else 
		address <= address + N + 1;
end

wire [7: 0] sin_wave;
sin_256 sin(
	.address(address),
	.clock(clk),
	.q(sin_wave)
);

wire clk_out;
CLK clk_div(
	.clk(clk),
	.clk_out(clk_out)
);

wire mxl_out;
MXL mxl(
	.clk(clk_out),
	.out(mxl_out)
);

choose_PSK ch(
	.data_in(sin_wave),
	.sel(mxl_out),
	.data_out(dout_PSK)
);

endmodule
module PSK(
	input clk, rst_n,
	input N,
	output [7: 0] dout_PSK
);



reg [7: 0] address;

always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		address <= 0;
	else 
		address <= address + N + 1;
end

wire [7: 0] sin_wave;
sin_256 sin(
	.address(address),
	.clock(clk),
	.q(sin_wave)
);

wire clk_out;
CLK clk_div(
	.clk(clk),
	.clk_out(clk_out)
);

wire mxl_out;
MXL mxl(
	.clk(clk_out),
	.out(mxl_out)
);

choose_PSK ch(
	.data_in(sin_wave),
	.sel(mxl_out),
	.data_out(dout_PSK)
);

endmodule