data/full_repos/permissive/507850313/rtl/core/core_mem.v
1: b'%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:24: Cannot find include file: core_defines.v\n`include "core_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.sv\n             core_defines.v\n             core_defines.v.v\n             core_defines.v.sv\n             obj_dir/core_defines.v\n             obj_dir/core_defines.v.v\n             obj_dir/core_defines.v.sv\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:31: Define or directive not defined: \'`CPU_PC_SIZE\'\n    input [`CPU_PC_SIZE-1:0] pc_i,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:32: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    input [`CPU_INSTR_SIZE-1:0] instr_i,\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:33: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    input [`CPU_RFIDX_WIDTH-1:0] rs1_idx_i,    \n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:34: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    input [`CPU_RFIDX_WIDTH-1:0] rs2_idx_i,    \n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:35: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    input [`CPU_RFIDX_WIDTH-1:0] rsd_idx_i,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:36: Define or directive not defined: \'`CPU_XLEN\'\n    input [`CPU_XLEN-1:0] rs1_data_i,    \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:37: Define or directive not defined: \'`CPU_XLEN\'\n    input [`CPU_XLEN-1:0] rs2_data_i,    \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:38: Define or directive not defined: \'`CPU_XLEN\'\n    input [`CPU_XLEN-1:0] rsd_data_i,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:41: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0] pc_o,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:42: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    output [`CPU_INSTR_SIZE-1:0] instr_o,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:43: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    output [`CPU_RFIDX_WIDTH-1:0] rs1_idx_o,    \n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:44: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    output [`CPU_RFIDX_WIDTH-1:0] rs2_idx_o,    \n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:45: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\n    output [`CPU_RFIDX_WIDTH-1:0] rsd_idx_o,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:46: Define or directive not defined: \'`CPU_XLEN\'\n    output [`CPU_XLEN-1:0] rs1_data_o,    \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:47: Define or directive not defined: \'`CPU_XLEN\'\n    output [`CPU_XLEN-1:0] rs2_data_o,    \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_mem.v:48: Define or directive not defined: \'`CPU_XLEN\'\n    output [`CPU_XLEN-1:0] rsd_data_o,    \n            ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module core_mem #(

) (


    input [`CPU_PC_SIZE-1:0] pc_i,
    input [`CPU_INSTR_SIZE-1:0] instr_i,
    input [`CPU_RFIDX_WIDTH-1:0] rs1_idx_i,    
    input [`CPU_RFIDX_WIDTH-1:0] rs2_idx_i,    
    input [`CPU_RFIDX_WIDTH-1:0] rsd_idx_i,
    input [`CPU_XLEN-1:0] rs1_data_i,    
    input [`CPU_XLEN-1:0] rs2_data_i,    
    input [`CPU_XLEN-1:0] rsd_data_i,  


    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,
    output [`CPU_RFIDX_WIDTH-1:0] rs1_idx_o,    
    output [`CPU_RFIDX_WIDTH-1:0] rs2_idx_o,    
    output [`CPU_RFIDX_WIDTH-1:0] rsd_idx_o,
    output [`CPU_XLEN-1:0] rs1_data_o,    
    output [`CPU_XLEN-1:0] rs2_data_o,    
    output [`CPU_XLEN-1:0] rsd_data_o,    






    input clk,
    input rst_n
);



endmodule
module core_mem #(

) (


    input [`CPU_PC_SIZE-1:0] pc_i,
    input [`CPU_INSTR_SIZE-1:0] instr_i,
    input [`CPU_RFIDX_WIDTH-1:0] rs1_idx_i,    
    input [`CPU_RFIDX_WIDTH-1:0] rs2_idx_i,    
    input [`CPU_RFIDX_WIDTH-1:0] rsd_idx_i,
    input [`CPU_XLEN-1:0] rs1_data_i,    
    input [`CPU_XLEN-1:0] rs2_data_i,    
    input [`CPU_XLEN-1:0] rsd_data_i,  


    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,
    output [`CPU_RFIDX_WIDTH-1:0] rs1_idx_o,    
    output [`CPU_RFIDX_WIDTH-1:0] rs2_idx_o,    
    output [`CPU_RFIDX_WIDTH-1:0] rsd_idx_o,
    output [`CPU_XLEN-1:0] rs1_data_o,    
    output [`CPU_XLEN-1:0] rs2_data_o,    
    output [`CPU_XLEN-1:0] rsd_data_o,    






    input clk,
    input rst_n
);




endmodule