data/full_repos/permissive/427221126/src/Butterfly.v
1: b'%Error: data/full_repos/permissive/427221126/src/Butterfly.v:54: Cannot find file containing module: \'ComplexMult\'\n  ComplexMult #(.INWIDTH(INWIDTH)) CM1\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ComplexMult\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ComplexMult.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ComplexMult.sv\n             ComplexMult\n             ComplexMult.v\n             ComplexMult.sv\n             obj_dir/ComplexMult\n             obj_dir/ComplexMult.v\n             obj_dir/ComplexMult.sv\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/Butterfly.v:87: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 29 bits.\n                                                                       : ... In instance Butterfly\n  assign XP_R_D5 = $signed({XP_R_D[6], {FRACWIDTH{1\'b0}}});\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/Butterfly.v:88: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 29 bits.\n                                                                       : ... In instance Butterfly\n  assign XP_I_D5 = $signed({XP_I_D[6], {FRACWIDTH{1\'b0}}});\n                 ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Butterfly 
  #(
    parameter INWIDTH = 16,
              FRACWIDTH = 13
  ) 
  (
    input  CLK,
    input  RESET,
    input  EN,
    input  signed [INWIDTH-1:0]   XP_R,
    input  signed [INWIDTH-1:0]   XP_I,
    input  signed [INWIDTH-1:0]   XQ_R,
    input  signed [INWIDTH-1:0]   XQ_I,
    input  signed [INWIDTH-1:0]   TF_R,
    input  signed [INWIDTH-1:0]   TF_I,
    output signed [2*INWIDTH+1:0] YP_R,
    output signed [2*INWIDTH+1:0] YP_I,
    output signed [2*INWIDTH+1:0] YQ_R,
    output signed [2*INWIDTH+1:0] YQ_I 
  );

  reg  signed [INWIDTH-1:0]   XP_R_D [1:6];
  reg  signed [INWIDTH-1:0]   XP_I_D [1:6];
  wire signed [2*INWIDTH:0]   XP_R_D5;
  wire signed [2*INWIDTH:0]   XP_I_D5;
  wire signed [2*INWIDTH:0]   xq_mult_r, xq_mult_i;

  reg  signed [2*INWIDTH+1:0] yp_real, yp_imag, yq_real, yq_imag;
  genvar gg;


  ComplexMult #(.INWIDTH(INWIDTH)) CM1
    ( 
      .clk(CLK), .reset(RESET), .en(EN),
      .ar(XQ_R), .ai(XQ_I), .br(TF_R), .bi(TF_I),
      .pr(xq_mult_r), .pi(xq_mult_i)
    );


  generate
    for (gg = 1; gg <= 6; gg = gg + 1) begin : XP_pipeline
      if (gg == 1) begin
        always @(posedge CLK) 
          if (RESET) begin
            XP_R_D[gg] <= 0;
            XP_I_D[gg] <= 0;
          end else if (EN) begin
            XP_R_D[gg] <= XP_R;
            XP_I_D[gg] <= XP_I;
          end
      end
      else begin 
        always @(posedge CLK) 
          if (RESET) begin
            XP_R_D[gg] <= 0;
            XP_I_D[gg] <= 0;
          end else if (EN) begin
            XP_R_D[gg] <= XP_R_D[gg-1];
            XP_I_D[gg] <= XP_I_D[gg-1];
          end
      end
    end
  endgenerate
  
  assign XP_R_D5 = $signed({XP_R_D[6], {FRACWIDTH{1'b0}}});
  assign XP_I_D5 = $signed({XP_I_D[6], {FRACWIDTH{1'b0}}});


  always @(posedge CLK) begin : yp_and_yq
    if (RESET) begin
      yp_real <= 0;
      yp_imag <= 0;
      yq_real <= 0;
      yq_imag <= 0;
    end else if (EN) begin
      yp_real <= XP_R_D5 + xq_mult_r;
      yp_imag <= XP_I_D5 + xq_mult_i;
      yq_real <= XP_R_D5 - xq_mult_r;
      yq_imag <= XP_I_D5 - xq_mult_i;
    end
  end

  assign YP_R = yp_real;
  assign YP_I = yp_imag;
  assign YQ_R = yq_real;
  assign YQ_I = yq_imag;
endmodule
module Butterfly 
  #(
    parameter INWIDTH = 16,
              FRACWIDTH = 13
  ) 
  (
    input  CLK,
    input  RESET,
    input  EN,
    input  signed [INWIDTH-1:0]   XP_R,
    input  signed [INWIDTH-1:0]   XP_I,
    input  signed [INWIDTH-1:0]   XQ_R,
    input  signed [INWIDTH-1:0]   XQ_I,
    input  signed [INWIDTH-1:0]   TF_R,
    input  signed [INWIDTH-1:0]   TF_I,
    output signed [2*INWIDTH+1:0] YP_R,
    output signed [2*INWIDTH+1:0] YP_I,
    output signed [2*INWIDTH+1:0] YQ_R,
    output signed [2*INWIDTH+1:0] YQ_I 
  );


  reg  signed [INWIDTH-1:0]   XP_R_D [1:6];
  reg  signed [INWIDTH-1:0]   XP_I_D [1:6];
  wire signed [2*INWIDTH:0]   XP_R_D5;
  wire signed [2*INWIDTH:0]   XP_I_D5;
  wire signed [2*INWIDTH:0]   xq_mult_r, xq_mult_i;

  reg  signed [2*INWIDTH+1:0] yp_real, yp_imag, yq_real, yq_imag;
  genvar gg;


  ComplexMult #(.INWIDTH(INWIDTH)) CM1
    ( 
      .clk(CLK), .reset(RESET), .en(EN),
      .ar(XQ_R), .ai(XQ_I), .br(TF_R), .bi(TF_I),
      .pr(xq_mult_r), .pi(xq_mult_i)
    );


  generate
    for (gg = 1; gg <= 6; gg = gg + 1) begin : XP_pipeline
      if (gg == 1) begin
        always @(posedge CLK) 
          if (RESET) begin
            XP_R_D[gg] <= 0;
            XP_I_D[gg] <= 0;
          end else if (EN) begin
            XP_R_D[gg] <= XP_R;
            XP_I_D[gg] <= XP_I;
          end
      end
      else begin 
        always @(posedge CLK) 
          if (RESET) begin
            XP_R_D[gg] <= 0;
            XP_I_D[gg] <= 0;
          end else if (EN) begin
            XP_R_D[gg] <= XP_R_D[gg-1];
            XP_I_D[gg] <= XP_I_D[gg-1];
          end
      end
    end
  endgenerate
  
  assign XP_R_D5 = $signed({XP_R_D[6], {FRACWIDTH{1'b0}}});
  assign XP_I_D5 = $signed({XP_I_D[6], {FRACWIDTH{1'b0}}});


  always @(posedge CLK) begin : yp_and_yq
    if (RESET) begin
      yp_real <= 0;
      yp_imag <= 0;
      yq_real <= 0;
      yq_imag <= 0;
    end else if (EN) begin
      yp_real <= XP_R_D5 + xq_mult_r;
      yp_imag <= XP_I_D5 + xq_mult_i;
      yq_real <= XP_R_D5 - xq_mult_r;
      yq_imag <= XP_I_D5 - xq_mult_i;
    end
  end

  assign YP_R = yp_real;
  assign YP_I = yp_imag;
  assign YQ_R = yq_real;
  assign YQ_I = yq_imag;
endmodule