data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module SignExtend(inst_IF, immOut);
    input [31:0] inst_IF;
    output reg [31:0] immOut;
    wire [15:0] imm;
    
    assign imm = inst_IF[15:0];
    always @(imm) begin
        immOut = {{16{imm[15]}},imm};
    end
endmodule
module SignExtend(inst_IF, immOut);

    input [31:0] inst_IF;
    output reg [31:0] immOut;
    wire [15:0] imm;
    
    assign imm = inst_IF[15:0];
    always @(imm) begin
        immOut = {{16{imm[15]}},imm};
    end
endmodule