data/full_repos/permissive/480141277/counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480141277/counter.v:45: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'Q\' generates 6 bits.\n                                                                 : ... In instance counter\n assign count = Q;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter(
	input clk,
	input clr,
	input rst,
	output [6:0] count
	);
	
	wire [5:0] D;
	reg[5:0] Q;
	
	always @(negedge clk or posedge rst) begin
		if(rst)
			Q <= 0;
		else if(clr)
			Q <= 0;
		else if(~clk)
			Q <= Q + 1;
	end
	
	assign count = Q;
	
endmodule
module counter(
	input clk,
	input clr,
	input rst,
	output [6:0] count
	);

	
	wire [5:0] D;
	reg[5:0] Q;
	
	always @(negedge clk or posedge rst) begin
		if(rst)
			Q <= 0;
		else if(clr)
			Q <= 0;
		else if(~clk)
			Q <= Q + 1;
	end
	
	assign count = Q;
	
endmodule