data/full_repos/permissive/497870922/rtl/ubsoc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/497870922/rtl/ubsoc.v:50: Operator ADD expects 6 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                   : ... In instance ubsoc\n  reset_cnt <= reset_cnt + !resetn;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/497870922/rtl/ubsoc.v:191: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 16 bits.\n                                                                    : ... In instance ubsoc\n    iomem_addr == 32\'h03000100 ? {gpio_button_i, gpio_switch_i} : \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/497870922/rtl/ubsoc.v:192: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'i2c_data_rx\' generates 8 bits.\n                                                                    : ... In instance ubsoc\n    iomem_addr == 32\'h06010000 ? i2c_data_rx : \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/497870922/rtl/ubsoc.v:193: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'i2c_data_st\' generates 8 bits.\n                                                                    : ... In instance ubsoc\n    iomem_addr == 32\'h06010100 ? i2c_data_st : \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/497870922/rtl/ubsoc.v:194: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'spi_data_o\' generates 8 bits.\n                                                                    : ... In instance ubsoc\n    iomem_addr[31:16] == 16\'h0501 ? spi_data_o : 32\'h00000000;\n                                  ^\n%Error: data/full_repos/permissive/497870922/rtl/ubsoc.v:201: Cannot find file containing module: \'picosoc_noflash\'\n picosoc_noflash soc (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl,data/full_repos/permissive/497870922/picosoc_noflash\n             data/full_repos/permissive/497870922/rtl,data/full_repos/permissive/497870922/picosoc_noflash.v\n             data/full_repos/permissive/497870922/rtl,data/full_repos/permissive/497870922/picosoc_noflash.sv\n             picosoc_noflash\n             picosoc_noflash.v\n             picosoc_noflash.sv\n             obj_dir/picosoc_noflash\n             obj_dir/picosoc_noflash.v\n             obj_dir/picosoc_noflash.sv\n%Error: data/full_repos/permissive/497870922/rtl/ubsoc.v:220: Cannot find file containing module: \'spi_master_top\'\n spi_master_top spi_top (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/497870922/rtl/ubsoc.v:241: Cannot find file containing module: \'i2c_master_top\'\n i2c_master_top i2c_module (\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module ubsoc (
	input clk_i,


	output suart_tx_o,
	input suart_rx_i,


	output [7:0] gpio_led_o,
	input [7:0] gpio_switch_i,
	input [7:0] gpio_button_i,


	inout i2c_scl_io,
	inout i2c_sda_io,


	output spi_sck,
	output [7:0] spi_ss,
	output spi_mosi,
	input  spi_miso,


	output spi_cpol_debug,
	output spi_cpha_debug
);

	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clk_i) begin
		reset_cnt <= reset_cnt + !resetn;
	end

	wire        iomem_valid;
	reg         iomem_ready;
	wire [3:0]  iomem_wstrb;
	wire [31:0] iomem_addr;
	wire [31:0] iomem_wdata;
	wire [31:0] iomem_rdata;




	
	reg [7:0] leds;
	assign gpio_led_o = leds;






	parameter I2C_PRER_LO = 5'b0_0001;
	parameter I2C_PRER_HI = 5'b0_0010;
	parameter I2C_CTR 	  = 5'b0_0100;
	parameter I2C_TXR 	  = 5'b0_1000;
	parameter I2C_CR 	  = 5'b1_0000;


	wire scl_padoen_o, sda_padoen_o;
	wire scl_pad_o, sda_pad_o;
	wire scl_pad_i, sda_pad_i;

	assign i2c_scl_io = scl_padoen_o ? 1'b1 : scl_pad_o;
	assign scl_pad_i  = i2c_scl_io;

	assign i2c_sda_io = sda_padoen_o ? 1'bz : sda_pad_o;
	assign sda_pad_i  = i2c_sda_io;


	wire [7:0] i2c_rx_byte;
	wire [7:0] i2c_status;
	reg  [7:0] i2c_data_i;
	reg  [4:0] i2c_reg_enable;

	wire [7:0] i2c_data_rx;

	wire [7:0] i2c_data_rx_rst;
	wire [7:0] i2c_data_st;

	assign i2c_data_rx_rst = !resetn ? 8'h00 : i2c_data_rx;
	assign i2c_data_rx  = !i2c_data_st[1] ? i2c_rx_byte : i2c_data_rx_rst;
	assign i2c_data_st  = i2c_status;






	parameter SPI_CTRL = 8'h00;
	parameter SPI_STAT = 8'h01;
	parameter SPI_BUFF = 8'h02;
	parameter SPI_SS   = 8'h03;
	parameter SPI_PRE  = 8'h04;


	reg spi_wr = 0;
	reg spi_rd = 0;
	reg [7:0] spi_addr = 0;
	reg [7:0] spi_data_i = 0;
	wire [7:0] spi_data_o;






	always @(posedge clk_i) begin
		if (!resetn) begin
			leds <= 0;
			i2c_reg_enable <= 0;
			i2c_data_i <= 0;
			spi_wr <= 0;
			spi_rd <= 0;
		end else begin
			iomem_ready <= 0;
			spi_wr <= 0;
			spi_rd <= 0;


			if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
				iomem_ready <= 1;
				
				if (iomem_wstrb[0]) leds[7:0] <= iomem_wdata[ 7: 0];

			end


			else if ((iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 05)) begin
				iomem_ready <= 1;
				if (iomem_addr[23:16] == 8'h00) begin
					spi_wr <= 1;

					if 		(iomem_addr[15:8] == 8'h00) spi_addr <= SPI_CTRL;
					else if (iomem_addr[15:8] == 8'h03) spi_addr <= SPI_SS;
					else if (iomem_addr[15:8] == 8'h04) spi_addr <= SPI_PRE;
					else if (iomem_addr[15:8] == 8'h02) spi_addr <= SPI_BUFF;

					if (iomem_wstrb[0]) spi_data_i[ 7: 0] <= iomem_wdata[ 7: 0];

				end else if (iomem_addr[23:16] == 8'h01) begin
					spi_rd <= 1;
					if 		(iomem_addr[15:8] == 8'h00) spi_addr <= SPI_BUFF;
					else if (iomem_addr[15:8] == 8'h01) spi_addr <= SPI_STAT;
				end
			end


			else if ((iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h06)) begin
				iomem_ready <= 1;
				if (iomem_addr[23:16] == 8'h00) begin

					if 		(iomem_addr[15: 8] == 8'h00) i2c_reg_enable <= I2C_PRER_LO;
					else if (iomem_addr[15: 8] == 8'h01) i2c_reg_enable <= I2C_PRER_HI;
					else if (iomem_addr[15: 8] == 8'h02) i2c_reg_enable <= I2C_CTR;
					else if (iomem_addr[15: 8] == 8'h03) i2c_reg_enable <= I2C_TXR;
					else if (iomem_addr[15: 8] == 8'h04) i2c_reg_enable <= I2C_CR;

					if (iomem_wstrb[0]) i2c_data_i [ 7: 0] <= iomem_wdata[ 7: 0];

				end
			end 

			else begin
				i2c_reg_enable <= 0;
			end

		end
	end

	assign iomem_rdata = 				
				iomem_addr == 32'h03000100 ? {gpio_button_i, gpio_switch_i} : 
				iomem_addr == 32'h06010000 ? i2c_data_rx : 
				iomem_addr == 32'h06010100 ? i2c_data_st : 
				iomem_addr[31:16] == 16'h0501 ? spi_data_o : 32'h00000000;






	picosoc_noflash soc (
		.clk          (clk_i	   ),
		.resetn       (resetn      ),

		.ser_tx       (suart_tx_o  ),
		.ser_rx       (suart_rx_i  ),

		.irq_5        (1'b0        ),
		.irq_6        (1'b0        ),
		.irq_7        (1'b0        ),

		.iomem_valid  (iomem_valid ),
		.iomem_ready  (iomem_ready ),
		.iomem_wstrb  (iomem_wstrb ),
		.iomem_addr   (iomem_addr  ),
		.iomem_wdata  (iomem_wdata ),
		.iomem_rdata  (iomem_rdata )
	);

	spi_master_top spi_top (
		.Clk 	 (clk_i		 ),
		.Rst_n 	 (resetn 	 ),

		.Wr 	 (spi_wr 	 ),
		.Rd 	 (spi_rd 	 ),

		.Addr 	 (spi_addr 	 ),
		.DataIn  (spi_data_i ),
		.DataOut (spi_data_o ),

		.SCLK 	 (spi_sck 	 ),
		.MOSI	 (spi_mosi 	 ),
		.MISO	 (spi_miso 	 ),
		.SS 	 (spi_ss 	 ),

		.Int 	 ( 			 ),
		.spi_cpol_debug (spi_cpol_debug),
		.spi_cpha_debug (spi_cpha_debug)
	);

	i2c_master_top i2c_module (
		.clk_i			(clk_i     		   ),
		.arst_i			(resetn    		   ),
	

		.reg_i			(i2c_data_i		   ),
		.en_prer_lo_i	(i2c_reg_enable[0] ),
		.en_prer_hi_i	(i2c_reg_enable[1] ),
		.en_ctr_i		(i2c_reg_enable[2] ),
		.en_txr_i		(i2c_reg_enable[3] ),
		.en_cr_i 		(i2c_reg_enable[4] ),

		.rxr_o 			(i2c_rx_byte	   ),
		.sr_o 			(i2c_status		   ),
	


		.scl_pad_i 		(scl_pad_i		   ),
		.scl_pad_o 		(scl_pad_o 		   ),
		.scl_padoen_o 	(scl_padoen_o	   ),


		.sda_pad_i 		(sda_pad_i 		   ),
		.sda_pad_o 		(sda_pad_o 		   ),
		.sda_padoen_o 	(sda_padoen_o 	   )
	);


endmodule
module ubsoc (
	input clk_i,


	output suart_tx_o,
	input suart_rx_i,


	output [7:0] gpio_led_o,
	input [7:0] gpio_switch_i,
	input [7:0] gpio_button_i,


	inout i2c_scl_io,
	inout i2c_sda_io,


	output spi_sck,
	output [7:0] spi_ss,
	output spi_mosi,
	input  spi_miso,


	output spi_cpol_debug,
	output spi_cpha_debug
);


	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clk_i) begin
		reset_cnt <= reset_cnt + !resetn;
	end

	wire        iomem_valid;
	reg         iomem_ready;
	wire [3:0]  iomem_wstrb;
	wire [31:0] iomem_addr;
	wire [31:0] iomem_wdata;
	wire [31:0] iomem_rdata;




	
	reg [7:0] leds;
	assign gpio_led_o = leds;






	parameter I2C_PRER_LO = 5'b0_0001;
	parameter I2C_PRER_HI = 5'b0_0010;
	parameter I2C_CTR 	  = 5'b0_0100;
	parameter I2C_TXR 	  = 5'b0_1000;
	parameter I2C_CR 	  = 5'b1_0000;


	wire scl_padoen_o, sda_padoen_o;
	wire scl_pad_o, sda_pad_o;
	wire scl_pad_i, sda_pad_i;

	assign i2c_scl_io = scl_padoen_o ? 1'b1 : scl_pad_o;
	assign scl_pad_i  = i2c_scl_io;

	assign i2c_sda_io = sda_padoen_o ? 1'bz : sda_pad_o;
	assign sda_pad_i  = i2c_sda_io;


	wire [7:0] i2c_rx_byte;
	wire [7:0] i2c_status;
	reg  [7:0] i2c_data_i;
	reg  [4:0] i2c_reg_enable;

	wire [7:0] i2c_data_rx;

	wire [7:0] i2c_data_rx_rst;
	wire [7:0] i2c_data_st;

	assign i2c_data_rx_rst = !resetn ? 8'h00 : i2c_data_rx;
	assign i2c_data_rx  = !i2c_data_st[1] ? i2c_rx_byte : i2c_data_rx_rst;
	assign i2c_data_st  = i2c_status;






	parameter SPI_CTRL = 8'h00;
	parameter SPI_STAT = 8'h01;
	parameter SPI_BUFF = 8'h02;
	parameter SPI_SS   = 8'h03;
	parameter SPI_PRE  = 8'h04;


	reg spi_wr = 0;
	reg spi_rd = 0;
	reg [7:0] spi_addr = 0;
	reg [7:0] spi_data_i = 0;
	wire [7:0] spi_data_o;






	always @(posedge clk_i) begin
		if (!resetn) begin
			leds <= 0;
			i2c_reg_enable <= 0;
			i2c_data_i <= 0;
			spi_wr <= 0;
			spi_rd <= 0;
		end else begin
			iomem_ready <= 0;
			spi_wr <= 0;
			spi_rd <= 0;


			if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
				iomem_ready <= 1;
				
				if (iomem_wstrb[0]) leds[7:0] <= iomem_wdata[ 7: 0];

			end


			else if ((iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 05)) begin
				iomem_ready <= 1;
				if (iomem_addr[23:16] == 8'h00) begin
					spi_wr <= 1;

					if 		(iomem_addr[15:8] == 8'h00) spi_addr <= SPI_CTRL;
					else if (iomem_addr[15:8] == 8'h03) spi_addr <= SPI_SS;
					else if (iomem_addr[15:8] == 8'h04) spi_addr <= SPI_PRE;
					else if (iomem_addr[15:8] == 8'h02) spi_addr <= SPI_BUFF;

					if (iomem_wstrb[0]) spi_data_i[ 7: 0] <= iomem_wdata[ 7: 0];

				end else if (iomem_addr[23:16] == 8'h01) begin
					spi_rd <= 1;
					if 		(iomem_addr[15:8] == 8'h00) spi_addr <= SPI_BUFF;
					else if (iomem_addr[15:8] == 8'h01) spi_addr <= SPI_STAT;
				end
			end


			else if ((iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h06)) begin
				iomem_ready <= 1;
				if (iomem_addr[23:16] == 8'h00) begin

					if 		(iomem_addr[15: 8] == 8'h00) i2c_reg_enable <= I2C_PRER_LO;
					else if (iomem_addr[15: 8] == 8'h01) i2c_reg_enable <= I2C_PRER_HI;
					else if (iomem_addr[15: 8] == 8'h02) i2c_reg_enable <= I2C_CTR;
					else if (iomem_addr[15: 8] == 8'h03) i2c_reg_enable <= I2C_TXR;
					else if (iomem_addr[15: 8] == 8'h04) i2c_reg_enable <= I2C_CR;

					if (iomem_wstrb[0]) i2c_data_i [ 7: 0] <= iomem_wdata[ 7: 0];

				end
			end 

			else begin
				i2c_reg_enable <= 0;
			end

		end
	end

	assign iomem_rdata = 				
				iomem_addr == 32'h03000100 ? {gpio_button_i, gpio_switch_i} : 
				iomem_addr == 32'h06010000 ? i2c_data_rx : 
				iomem_addr == 32'h06010100 ? i2c_data_st : 
				iomem_addr[31:16] == 16'h0501 ? spi_data_o : 32'h00000000;






	picosoc_noflash soc (
		.clk          (clk_i	   ),
		.resetn       (resetn      ),

		.ser_tx       (suart_tx_o  ),
		.ser_rx       (suart_rx_i  ),

		.irq_5        (1'b0        ),
		.irq_6        (1'b0        ),
		.irq_7        (1'b0        ),

		.iomem_valid  (iomem_valid ),
		.iomem_ready  (iomem_ready ),
		.iomem_wstrb  (iomem_wstrb ),
		.iomem_addr   (iomem_addr  ),
		.iomem_wdata  (iomem_wdata ),
		.iomem_rdata  (iomem_rdata )
	);

	spi_master_top spi_top (
		.Clk 	 (clk_i		 ),
		.Rst_n 	 (resetn 	 ),

		.Wr 	 (spi_wr 	 ),
		.Rd 	 (spi_rd 	 ),

		.Addr 	 (spi_addr 	 ),
		.DataIn  (spi_data_i ),
		.DataOut (spi_data_o ),

		.SCLK 	 (spi_sck 	 ),
		.MOSI	 (spi_mosi 	 ),
		.MISO	 (spi_miso 	 ),
		.SS 	 (spi_ss 	 ),

		.Int 	 ( 			 ),
		.spi_cpol_debug (spi_cpol_debug),
		.spi_cpha_debug (spi_cpha_debug)
	);

	i2c_master_top i2c_module (
		.clk_i			(clk_i     		   ),
		.arst_i			(resetn    		   ),
	

		.reg_i			(i2c_data_i		   ),
		.en_prer_lo_i	(i2c_reg_enable[0] ),
		.en_prer_hi_i	(i2c_reg_enable[1] ),
		.en_ctr_i		(i2c_reg_enable[2] ),
		.en_txr_i		(i2c_reg_enable[3] ),
		.en_cr_i 		(i2c_reg_enable[4] ),

		.rxr_o 			(i2c_rx_byte	   ),
		.sr_o 			(i2c_status		   ),
	


		.scl_pad_i 		(scl_pad_i		   ),
		.scl_pad_o 		(scl_pad_o 		   ),
		.scl_padoen_o 	(scl_padoen_o	   ),


		.sda_pad_i 		(sda_pad_i 		   ),
		.sda_pad_o 		(sda_pad_o 		   ),
		.sda_padoen_o 	(sda_padoen_o 	   )
	);


endmodule