data/full_repos/permissive/516359259/APB_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n            #5 PCLK = ~PCLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #15 Transfer = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #20 Transfer = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/516359259/APB_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;\n        ^\n%Error: data/full_repos/permissive/516359259/APB_tb.v:52: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("APB_wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/516359259/APB_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module APB_tb;
    reg PCLK, PRESETn, Transfer, Wr_Rd; 
    reg [4:0] Address; 
    reg [31:0] write_data; 
    wire [31:0] read_data; 
    APB_top DUT (PCLK,PRESETn,Transfer,Wr_Rd,Address,write_data,read_data);
    
    initial begin
        PCLK = 0;
        forever begin
            #5 PCLK = ~PCLK;
        end
    end
    
    
    initial begin
        PRESETn  = 1;
        Transfer = 1;
        

        Address = 5'b10010;
        #10
        Wr_Rd      = 1;
        write_data = 32'hDEADBEEF;
        #10
        

        Address    = 5'b10101;
        Wr_Rd      = 1;
        write_data = 32'hDABBCAFE;
        #30
        write_data = 32'hx;
        #10
        Transfer     = 0;
        #15 Transfer = 1;


        Wr_Rd   = 0;
        Address = 5'b10010;
        

        #30
        Address = 5'b10101;
        
        #20 Transfer = 0;
        #20 $finish;
        
    end
    
    
    initial begin
        $dumpfile("APB_wave.vcd");
        $dumpvars;
    end
    
endmodule
module APB_tb;

    reg PCLK, PRESETn, Transfer, Wr_Rd; 
    reg [4:0] Address; 
    reg [31:0] write_data; 
    wire [31:0] read_data; 
    APB_top DUT (PCLK,PRESETn,Transfer,Wr_Rd,Address,write_data,read_data);
    
    initial begin
        PCLK = 0;
        forever begin
            #5 PCLK = ~PCLK;
        end
    end
    
    
    initial begin
        PRESETn  = 1;
        Transfer = 1;
        

        Address = 5'b10010;
        #10
        Wr_Rd      = 1;
        write_data = 32'hDEADBEEF;
        #10
        

        Address    = 5'b10101;
        Wr_Rd      = 1;
        write_data = 32'hDABBCAFE;
        #30
        write_data = 32'hx;
        #10
        Transfer     = 0;
        #15 Transfer = 1;


        Wr_Rd   = 0;
        Address = 5'b10010;
        

        #30
        Address = 5'b10101;
        
        #20 Transfer = 0;
        #20 $finish;
        
    end
    
    
    initial begin
        $dumpfile("APB_wave.vcd");
        $dumpvars;
    end
    
endmodule