data/full_repos/permissive/520428138/verilog/rtl/user_module_341497938559631956.v
data/verilator_xmls/a6fd0ca0-667a-45c9-82b3-5c573fc06231.xml
module user_module_341497938559631956(
  input wire [7:0] io_in,
  output wire [7:0] out
);
  assign out = ~io_in;
endmodule
module user_module_341497938559631956(
  input wire [7:0] io_in,
  output wire [7:0] out
);

  assign out = ~io_in;
endmodule