data/full_repos/permissive/527578197/v1/testbench/binary_tb.v
1: b'%Error: data/full_repos/permissive/527578197/v1/testbench/binary_tb.v:16: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("wave.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527578197/v1/testbench/binary_tb.v:17: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars("+all");\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/binary_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#1000000 $finish;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/binary_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100 data_raw <= {10, 20 ,-20};\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module binary_tb();

reg	signed [31:0]	data_raw[2:0];
reg	signed [1:0]	data_binarized[2:0];

binary #(
	.WIDTH(3)
)
binary_tb
(
	.data_raw(data_raw),
	.data_binarized(data_binarized)
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

initial begin
	data_raw	<=	{1, -1, 3};
	#100 data_raw <= {10, 20 ,-20};
end


endmodule
module binary_tb();


reg	signed [31:0]	data_raw[2:0];
reg	signed [1:0]	data_binarized[2:0];

binary #(
	.WIDTH(3)
)
binary_tb
(
	.data_raw(data_raw),
	.data_binarized(data_binarized)
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

initial begin
	data_raw	<=	{1, -1, 3};
	#100 data_raw <= {10, 20 ,-20};
end


endmodule