data/full_repos/permissive/490013975/wrapper.v
1: b"%Error: data/full_repos/permissive/490013975/wrapper.v:57: Define or directive not defined: '`MPRJ_IO_PADS'\n    input wire [`MPRJ_IO_PADS-1:0] io_in,            \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:58: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout wire [`MPRJ_IO_PADS-1:0] io_out,           \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:59: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,           \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:80: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:81: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:140: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:141: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490013975/wrapper.v:149: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};\n                         ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module wrapped_etpu(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire [3:0]    wbs_sel_i,
    input wire [31:0]   wbs_dat_i,
    input wire [31:0]   wbs_adr_i,
    inout wire          wbs_ack_o,
    inout wire [31:0]   wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    inout wire          rambus_wb_clk_o,
    inout wire          rambus_wb_rst_o,
    inout wire          rambus_wb_stb_o,
    inout wire          rambus_wb_cyc_o,
    inout wire          rambus_wb_we_o,
    inout wire [3:0]    rambus_wb_sel_o,
    inout wire [31:0]   rambus_wb_dat_o,
    inout wire [9:0]    rambus_wb_adr_o,
    input wire          rambus_wb_ack_i,
    input wire [31:0]   rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input wire [31:0]   la1_data_in,
    inout wire [31:0]   la1_data_out,
    input wire [31:0]   la1_oenb,
`endif


`ifdef USE_IO
    input wire [`MPRJ_IO_PADS-1:0] io_in,
    inout wire [`MPRJ_IO_PADS-1:0] io_out,
    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    inout wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);


    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};
    assign buf_io_out[29] = active;
    
    edu_tpu etpu(
                .caravel_wb_clk_i   (wb_clk_i ),
                .caravel_wb_rst_i   (wb_rst_i | !active),
                .caravel_wb_stb_i   (wbs_stb_i),
                .caravel_wb_cyc_i   (wbs_cyc_i),
                .caravel_wb_we_i    (wbs_we_i ),
                .caravel_wb_sel_i   (wbs_sel_i),
                .caravel_wb_dat_i   (wbs_dat_i),
                .caravel_wb_adr_i   (wbs_adr_i),
                .caravel_wb_ack_o   (buf_wbs_ack_o),
                .caravel_wb_dat_o   (buf_wbs_dat_o),
                .out1               (buf_io_out[23:8]),
                .load_end           (buf_io_out[27:24]),
                .en                 (buf_io_out[28])
               );


endmodule
module wrapped_etpu(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire [3:0]    wbs_sel_i,
    input wire [31:0]   wbs_dat_i,
    input wire [31:0]   wbs_adr_i,
    inout wire          wbs_ack_o,
    inout wire [31:0]   wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    inout wire          rambus_wb_clk_o,
    inout wire          rambus_wb_rst_o,
    inout wire          rambus_wb_stb_o,
    inout wire          rambus_wb_cyc_o,
    inout wire          rambus_wb_we_o,
    inout wire [3:0]    rambus_wb_sel_o,
    inout wire [31:0]   rambus_wb_dat_o,
    inout wire [9:0]    rambus_wb_adr_o,
    input wire          rambus_wb_ack_i,
    input wire [31:0]   rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input wire [31:0]   la1_data_in,
    inout wire [31:0]   la1_data_out,
    input wire [31:0]   la1_oenb,
`endif


`ifdef USE_IO
    input wire [`MPRJ_IO_PADS-1:0] io_in,
    inout wire [`MPRJ_IO_PADS-1:0] io_out,
    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    inout wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);



    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};
    assign buf_io_out[29] = active;
    
    edu_tpu etpu(
                .caravel_wb_clk_i   (wb_clk_i ),
                .caravel_wb_rst_i   (wb_rst_i | !active),
                .caravel_wb_stb_i   (wbs_stb_i),
                .caravel_wb_cyc_i   (wbs_cyc_i),
                .caravel_wb_we_i    (wbs_we_i ),
                .caravel_wb_sel_i   (wbs_sel_i),
                .caravel_wb_dat_i   (wbs_dat_i),
                .caravel_wb_adr_i   (wbs_adr_i),
                .caravel_wb_ack_o   (buf_wbs_ack_o),
                .caravel_wb_dat_o   (buf_wbs_dat_o),
                .out1               (buf_io_out[23:8]),
                .load_end           (buf_io_out[27:24]),
                .en                 (buf_io_out[28])
               );


endmodule