data/full_repos/permissive/497039278/ram.v
data/verilator_xmls/a14126b0-5a80-46cd-ad27-e2a097d50da9.xml
module ram(
input               clock,
input[31:0]          addr,
input               wr,
input[31:0]         wdata,
input               rd,
output reg[31:0]    rdata = 32'bz
);

reg[31:0]           ram[255:0];
always @(negedge clock) begin
    if (wr)begin
        ram[addr] <= wdata;
    end
    if (rd) begin
        rdata <= ram[addr];
    end
    else begin
        rdata <= 32'bz;
    end
end
endmodule
module ram(
input               clock,
input[31:0]          addr,
input               wr,
input[31:0]         wdata,
input               rd,
output reg[31:0]    rdata = 32'bz
);


reg[31:0]           ram[255:0];
always @(negedge clock) begin
    if (wr)begin
        ram[addr] <= wdata;
    end
    if (rd) begin
        rdata <= ram[addr];
    end
    else begin
        rdata <= 32'bz;
    end
end
endmodule