data/full_repos/permissive/459604085/src/soc_lite_top.v
1: b"%Error: data/full_repos/permissive/459604085/src/soc_lite_top.v:175: Cannot find file containing module: 'bridge_1x2'\nbridge_1x2 bridge_1x2(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459604085/src,data/full_repos/permissive/459604085/bridge_1x2\n             data/full_repos/permissive/459604085/src,data/full_repos/permissive/459604085/bridge_1x2.v\n             data/full_repos/permissive/459604085/src,data/full_repos/permissive/459604085/bridge_1x2.sv\n             bridge_1x2\n             bridge_1x2.v\n             bridge_1x2.sv\n             obj_dir/bridge_1x2\n             obj_dir/bridge_1x2.v\n             obj_dir/bridge_1x2.sv\n%Error: data/full_repos/permissive/459604085/src/soc_lite_top.v:210: Cannot find file containing module: 'confreg'\nconfreg #(.SIMULATION(SIMULATION)) confreg\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module soc_lite_top #(parameter SIMULATION=1'b0)
(
    input         resetn, 
    input         clk,


    output [15:0] led,
    output [1 :0] led_rg0,
    output [1 :0] led_rg1,
    output [7 :0] num_csn,
    output [6 :0] num_a_g,
    input  [7 :0] switch_, 
    output [3 :0] btn_key_col,
    input  [3 :0] btn_key_row,
    input  [1 :0] btn_step
);

wire [31:0] debug_wb_pc;
wire [3 :0] debug_wb_rf_wen;
wire [4 :0] debug_wb_rf_wnum;
wire [31:0] debug_wb_rf_wdata;


wire cpu_clk;
wire timer_clk;
reg cpu_resetn;
always @(posedge cpu_clk)
begin
    cpu_resetn <= resetn;
end















assign cpu_clk   = clk;
assign timer_clk = clk;


wire        cpu_inst_en;
wire [3 :0] cpu_inst_wen;
wire [31:0] cpu_inst_addr;
wire [31:0] cpu_inst_wdata;
wire [31:0] cpu_inst_rdata;

wire        cpu_data_en;
wire [3 :0] cpu_data_wen;
wire [31:0] cpu_data_addr;
wire [31:0] cpu_data_wdata;
wire [31:0] cpu_data_rdata;


wire        data_sram_en;
wire [3 :0] data_sram_wen;
wire [31:0] data_sram_addr;
wire [31:0] data_sram_wdata;
wire [31:0] data_sram_rdata;

wire        conf_en;
wire [3 :0] conf_wen;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
wire [31:0] conf_rdata;












    
























bridge_1x2 bridge_1x2(
    .clk             ( cpu_clk         ),
    .resetn          ( cpu_resetn      ),

    .cpu_data_en     ( cpu_data_en     ),
    .cpu_data_wen    ( cpu_data_wen    ),
    .cpu_data_addr   ( cpu_data_addr   ),
    .cpu_data_wdata  ( cpu_data_wdata  ),
    .cpu_data_rdata  ( cpu_data_rdata  ),

    .data_sram_en    ( data_sram_en    ),
    .data_sram_wen   ( data_sram_wen   ),
    .data_sram_addr  ( data_sram_addr  ),
    .data_sram_wdata ( data_sram_wdata ),
    .data_sram_rdata ( data_sram_rdata ),

    .conf_en         ( conf_en         ),
    .conf_wen        ( conf_wen        ),
    .conf_addr       ( conf_addr       ),
    .conf_wdata      ( conf_wdata      ),
    .conf_rdata      ( conf_rdata      )
 );













confreg #(.SIMULATION(SIMULATION)) confreg
(
    .clk         ( cpu_clk    ),
    .timer_clk   ( timer_clk  ),
    .resetn      ( cpu_resetn ),
    .conf_en     ( conf_en    ),
    .conf_wen    ( conf_wen   ),
    .conf_addr   ( conf_addr  ),
    .conf_wdata  ( conf_wdata ),
    .conf_rdata  ( conf_rdata ),
    .led         ( led        ),
    .led_rg0     ( led_rg0    ),
    .led_rg1     ( led_rg1    ),
    .num_csn     ( num_csn    ),
    .num_a_g     ( num_a_g    ),
    .switch_      ( switch_     ),
    .btn_key_col ( btn_key_col),
    .btn_key_row ( btn_key_row),
    .btn_step    ( btn_step   )
);

endmodule
module soc_lite_top #(parameter SIMULATION=1'b0)
(
    input         resetn, 
    input         clk,


    output [15:0] led,
    output [1 :0] led_rg0,
    output [1 :0] led_rg1,
    output [7 :0] num_csn,
    output [6 :0] num_a_g,
    input  [7 :0] switch_, 
    output [3 :0] btn_key_col,
    input  [3 :0] btn_key_row,
    input  [1 :0] btn_step
);


wire [31:0] debug_wb_pc;
wire [3 :0] debug_wb_rf_wen;
wire [4 :0] debug_wb_rf_wnum;
wire [31:0] debug_wb_rf_wdata;


wire cpu_clk;
wire timer_clk;
reg cpu_resetn;
always @(posedge cpu_clk)
begin
    cpu_resetn <= resetn;
end















assign cpu_clk   = clk;
assign timer_clk = clk;


wire        cpu_inst_en;
wire [3 :0] cpu_inst_wen;
wire [31:0] cpu_inst_addr;
wire [31:0] cpu_inst_wdata;
wire [31:0] cpu_inst_rdata;

wire        cpu_data_en;
wire [3 :0] cpu_data_wen;
wire [31:0] cpu_data_addr;
wire [31:0] cpu_data_wdata;
wire [31:0] cpu_data_rdata;


wire        data_sram_en;
wire [3 :0] data_sram_wen;
wire [31:0] data_sram_addr;
wire [31:0] data_sram_wdata;
wire [31:0] data_sram_rdata;

wire        conf_en;
wire [3 :0] conf_wen;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
wire [31:0] conf_rdata;












    
























bridge_1x2 bridge_1x2(
    .clk             ( cpu_clk         ),
    .resetn          ( cpu_resetn      ),

    .cpu_data_en     ( cpu_data_en     ),
    .cpu_data_wen    ( cpu_data_wen    ),
    .cpu_data_addr   ( cpu_data_addr   ),
    .cpu_data_wdata  ( cpu_data_wdata  ),
    .cpu_data_rdata  ( cpu_data_rdata  ),

    .data_sram_en    ( data_sram_en    ),
    .data_sram_wen   ( data_sram_wen   ),
    .data_sram_addr  ( data_sram_addr  ),
    .data_sram_wdata ( data_sram_wdata ),
    .data_sram_rdata ( data_sram_rdata ),

    .conf_en         ( conf_en         ),
    .conf_wen        ( conf_wen        ),
    .conf_addr       ( conf_addr       ),
    .conf_wdata      ( conf_wdata      ),
    .conf_rdata      ( conf_rdata      )
 );













confreg #(.SIMULATION(SIMULATION)) confreg
(
    .clk         ( cpu_clk    ),
    .timer_clk   ( timer_clk  ),
    .resetn      ( cpu_resetn ),
    .conf_en     ( conf_en    ),
    .conf_wen    ( conf_wen   ),
    .conf_addr   ( conf_addr  ),
    .conf_wdata  ( conf_wdata ),
    .conf_rdata  ( conf_rdata ),
    .led         ( led        ),
    .led_rg0     ( led_rg0    ),
    .led_rg1     ( led_rg1    ),
    .num_csn     ( num_csn    ),
    .num_a_g     ( num_a_g    ),
    .switch_      ( switch_     ),
    .btn_key_col ( btn_key_col),
    .btn_key_row ( btn_key_row),
    .btn_step    ( btn_step   )
);

endmodule