data/full_repos/permissive/447976230/fpga/usrp2/custom/custom_engine_tx.v
data/verilator_xmls/95cc0f9b-f204-41b2-9dc0-29d63159dd03.xml
module custom_engine_tx
#(

    parameter BUF_SIZE = 10,



    parameter HEADER_OFFSET = 0
)
(

    input clock, input reset, input clear,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
);

    assign access_done = access_ok;

endmodule
module custom_engine_tx
#(

    parameter BUF_SIZE = 10,



    parameter HEADER_OFFSET = 0
)
(

    input clock, input reset, input clear,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output access_we,
    output access_stb,
    input access_ok,
    output access_done,
    output access_skip_read,
    output [BUF_SIZE-1:0] access_adr,
    input [BUF_SIZE-1:0] access_len,
    output [35:0] access_dat_o,
    input [35:0] access_dat_i
);


    assign access_done = access_ok;

endmodule