data/full_repos/permissive/445357518/top.v
1: b"%Error: data/full_repos/permissive/445357518/top.v:42: Cannot find file containing module: 'cpu'\ncpu CPU(clk,reset,read_data,datapath_out,N,V,Z,mem_cmd,mem_addr);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/445357518/top.v:72: Cannot find file containing module: 'vDFF1'\nvDFF1 #(8) LED_REG(clk, write_data[7:0], loadOut, LEDR[7:0]);\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
input [3:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire clk,reset,msel,writeMem,N,V,Z;
wire [8:0] mem_addr;
wire [7:0] read_address,write_address;
wire [15:0]read_data,datapath_out,dout,write_data;
wire [1:0] mem_cmd;
wire o1, o2, loadOut;
wire equals;


assign clk=~KEY[0];


assign reset=~KEY[1];


assign HEX5[0] = ~Z;
  assign HEX5[6] = ~N;
  assign HEX5[3] = ~V;


  sseg H0(datapath_out[3:0],   HEX0);
  sseg H1(datapath_out[7:4],   HEX1);
  sseg H2(datapath_out[11:8],  HEX2);
  sseg H3(datapath_out[15:12], HEX3);

  assign HEX4 = 7'b1111111;
  assign {HEX5[2:1],HEX5[5:4]} = 4'b1111;


RAM #(16,8,"data.txt") MEM (clk,read_address,write_address,writeMem,datapath_out,dout);


cpu CPU(clk,reset,read_data,datapath_out,N,V,Z,mem_cmd,mem_addr);


assign write_data = datapath_out;


assign read_address = mem_addr[7:0];

assign write_address = mem_addr[7:0];

assign msel = (mem_addr[8]==1'b0) ? 1'b1: 1'b0;


assign read_data = msel&(mem_cmd==`MREAD)? dout : {16{1'bz}};

assign writeMem = msel&(mem_cmd==`MWRITE);

assign read_data[7:0] = (mem_addr == 9'h140)&(mem_cmd==`MREAD) ? SW[7:0]: {8{1'bz}};
assign read_data[15:8] = (mem_addr == 9'h140)&(mem_cmd==`MREAD) ? 8'h00: {8{1'bz}};


assign equals = (mem_addr === 9'h100);

assign o2 = equals & mem_cmd[1];

assign o1 = equals & ~mem_cmd[0];

assign loadOut = o2 & o1;


vDFF1 #(8) LED_REG(clk, write_data[7:0], loadOut, LEDR[7:0]);

endmodule
module top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);

input [3:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire clk,reset,msel,writeMem,N,V,Z;
wire [8:0] mem_addr;
wire [7:0] read_address,write_address;
wire [15:0]read_data,datapath_out,dout,write_data;
wire [1:0] mem_cmd;
wire o1, o2, loadOut;
wire equals;


assign clk=~KEY[0];


assign reset=~KEY[1];


assign HEX5[0] = ~Z;
  assign HEX5[6] = ~N;
  assign HEX5[3] = ~V;


  sseg H0(datapath_out[3:0],   HEX0);
  sseg H1(datapath_out[7:4],   HEX1);
  sseg H2(datapath_out[11:8],  HEX2);
  sseg H3(datapath_out[15:12], HEX3);

  assign HEX4 = 7'b1111111;
  assign {HEX5[2:1],HEX5[5:4]} = 4'b1111;


RAM #(16,8,"data.txt") MEM (clk,read_address,write_address,writeMem,datapath_out,dout);


cpu CPU(clk,reset,read_data,datapath_out,N,V,Z,mem_cmd,mem_addr);


assign write_data = datapath_out;


assign read_address = mem_addr[7:0];

assign write_address = mem_addr[7:0];

assign msel = (mem_addr[8]==1'b0) ? 1'b1: 1'b0;


assign read_data = msel&(mem_cmd==`MREAD)? dout : {16{1'bz}};

assign writeMem = msel&(mem_cmd==`MWRITE);

assign read_data[7:0] = (mem_addr == 9'h140)&(mem_cmd==`MREAD) ? SW[7:0]: {8{1'bz}};
assign read_data[15:8] = (mem_addr == 9'h140)&(mem_cmd==`MREAD) ? 8'h00: {8{1'bz}};


assign equals = (mem_addr === 9'h100);

assign o2 = equals & mem_cmd[1];

assign o1 = equals & ~mem_cmd[0];

assign loadOut = o2 & o1;


vDFF1 #(8) LED_REG(clk, write_data[7:0], loadOut, LEDR[7:0]);

endmodule