data/full_repos/permissive/472025725/multiplication by repeated addtion/MUL.v
1: b'%Error: Cannot find file containing module: by\n        ... Looked in:\n             data/full_repos/permissive/472025725/multiplication/by\n             data/full_repos/permissive/472025725/multiplication/by.v\n             data/full_repos/permissive/472025725/multiplication/by.sv\n             by\n             by.v\n             by.sv\n             obj_dir/by\n             obj_dir/by.v\n             obj_dir/by.sv\n%Error: Cannot find file containing module: repeated\n%Error: Cannot find file containing module: addtion,data/full_repos/permissive/472025725\n%Error: Cannot find file containing module: data/full_repos/permissive/472025725/multiplication\n%Error: Cannot find file containing module: addtion/MUL.v\n%Error: Exiting due to 5 error(s)\n'
module MUL_controller (LdA,LdB,LdP,clrP,decB,done,clk,eqz,start);
input clk,eqz,start;
output reg LdA,LdB,LdP,clrP,decB,done;
reg [2:0] state;
parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100;
always @(posedge clk)
begin
case (state)
S0: if (start) state <= S1;
S1: state <= S2;
S2: state <= S3;
S3: #2 if (eqz) state <= S4;
S4: state <= S4;
default : state <= S0;
endcase
end 
always @(state)
begin
case(state)
S0: begin #1 LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =0; end
S1: begin #1 LdA = 1; end
S2: begin #1 LdA = 0; LdB = 1; clrP=1; end
S3: begin #1 LdA = 0; LdP = 1; clrP=0; decB = 1; done =0; end
S4: begin #1 LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =1; end
default : begin  LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =0; end
endcase
end
endmodule
module MUL_controller (LdA,LdB,LdP,clrP,decB,done,clk,eqz,start);

input clk,eqz,start;
output reg LdA,LdB,LdP,clrP,decB,done;
reg [2:0] state;
parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100;
always @(posedge clk)
begin
case (state)
S0: if (start) state <= S1;
S1: state <= S2;
S2: state <= S3;
S3: #2 if (eqz) state <= S4;
S4: state <= S4;
default : state <= S0;
endcase
end 
always @(state)
begin
case(state)
S0: begin #1 LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =0; end
S1: begin #1 LdA = 1; end
S2: begin #1 LdA = 0; LdB = 1; clrP=1; end
S3: begin #1 LdA = 0; LdP = 1; clrP=0; decB = 1; done =0; end
S4: begin #1 LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =1; end
default : begin  LdA = 0; LdB = 0; LdP = 0; clrP=0; decB = 0; done =0; end
endcase
end
endmodule