data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:206: Signal definition not found, creating implicitly: \'empty\'\n   assign dest_ip_filter_vld = !empty;\n                                ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:225: Signal definition not found, creating implicitly: \'lookup_ack\'\n                        if(lookup_ack)\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:110: Cannot find file containing module: \'cam\'\n   cam \n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/cam\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/cam.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/cam.sv\n             cam\n             cam.v\n             cam.sv\n             obj_dir/cam\n             obj_dir/cam.v\n             obj_dir/cam.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:129: Cannot find file containing module: \'unencoded_cam_lut_sm\'\n   unencoded_cam_lut_sm\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:175: Cannot find file containing module: \'fallthrough_small_fifo\'\n   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/dest_ip_filter.v:190: Cannot find file containing module: \'fallthrough_small_fifo\'\n  fallthrough_small_fifo #(.WIDTH(32), .MAX_DEPTH_BITS  (2))\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module dest_ip_filter
    #(parameter C_S_AXIS_DATA_WIDTH	= 256,
      parameter LUT_DEPTH		= 32,
      parameter LUT_DEPTH_BITS		= log2(LUT_DEPTH)
      )
   (
    input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,


    output                             dest_ip_hit,
    output                             dest_ip_filter_vld,
    input                              rd_dest_ip_filter_result,


    input                              word_IP_DST_HI,
    input                              word_IP_DST_LO,



    input  [LUT_DEPTH_BITS-1:0]        dest_ip_filter_rd_addr,
    input                              dest_ip_filter_rd_req,
    output [31:0]                      dest_ip_filter_rd_ip,
    output                             dest_ip_filter_rd_ack,


    input [LUT_DEPTH_BITS-1:0]         dest_ip_filter_wr_addr,
    input                              dest_ip_filter_wr_req,
    input [31:0]                       dest_ip_filter_wr_ip,
    output                             dest_ip_filter_wr_ack,


    input                              reset,
    input                              clk
   );


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction

   localparam	WAIT	= 1;
   localparam	PROCESS	= 2;



   wire                                  cam_busy;
   wire                                  cam_match;
   wire [LUT_DEPTH-1:0]   	         cam_match_addr;
   wire [31:0]                           cam_cmp_din, cam_cmp_data_mask;
   wire [31:0]                           cam_din, cam_data_mask;
   wire                                  cam_we;
   wire [LUT_DEPTH_BITS-1:0]             cam_wr_addr;

   reg                                   dst_ip_vld;
   reg [31:0]                            dst_ip;

   reg                                   rd_dest;
   reg                                   dst_ip_ready;
   wire [31:0]                           dst_ip_fifo;
   wire                                  dest_fifo_empty;

   reg [1:0]                             state,state_next;






   cam 
	#(.C_TCAM_ADDR_WIDTH	(LUT_DEPTH_BITS),
	  .C_TCAM_DATA_WIDTH	(32),
	  .C_TCAM_ADDR_TYPE	(1),
	  .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH)
	)
   dest_ip_cam
     (

      .BUSY                             (cam_busy),
      .MATCH                            (cam_match),
      .MATCH_ADDR                       (cam_match_addr),

      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din),
      .DIN                              (cam_din),
      .WE                               (cam_we),
      .ADDR_WR                          (cam_wr_addr));

   unencoded_cam_lut_sm
     #(.CMP_WIDTH(32),
       .DATA_WIDTH(1),
       .LUT_DEPTH(LUT_DEPTH),
       .DEFAULT_DATA(0)
      ) cam_lut_sm
       (
        .lookup_req          (dst_ip_ready),
        .lookup_cmp_data     (dst_ip_fifo),
        .lookup_cmp_dmask    (32'h0),
        .lookup_ack          (lookup_ack),
        .lookup_hit          (lookup_hit),
        .lookup_data         (),



        .rd_addr             (dest_ip_filter_rd_addr),
        .rd_req              (dest_ip_filter_rd_req),
        .rd_data             (),
        .rd_cmp_data         (dest_ip_filter_rd_ip),
        .rd_cmp_dmask        (),
        .rd_ack              (dest_ip_filter_rd_ack),


        .wr_addr             (dest_ip_filter_wr_addr),
        .wr_req              (dest_ip_filter_wr_req),
        .wr_data             (1'b0),
        .wr_cmp_data         (dest_ip_filter_wr_ip),
        .wr_cmp_dmask        (32'h0),
        .wr_ack              (dest_ip_filter_wr_ack),


        .cam_busy            (cam_busy),
        .cam_match           (cam_match),
        .cam_match_addr      (cam_match_addr),
        .cam_cmp_din         (cam_cmp_din),
        .cam_din             (cam_din),
        .cam_we              (cam_we),
        .cam_wr_addr         (cam_wr_addr),
        .cam_cmp_data_mask   (cam_cmp_data_mask),
        .cam_data_mask       (cam_data_mask),


        .reset               (reset),
        .clk                 (clk));

   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))
      dest_ip_filter_fifo
        (.din           (lookup_hit),
         .wr_en         (lookup_ack),
         .rd_en         (rd_dest_ip_filter_result),
         .dout          (dest_ip_hit),
         .full          (),
         .nearly_full   (),
         .prog_full     (),
         .empty         (empty),
         .reset         (reset),
         .clk           (clk)
         );


  fallthrough_small_fifo #(.WIDTH(32), .MAX_DEPTH_BITS  (2))
      dest_fifo2
        (.din           (dst_ip),
         .wr_en         (dst_ip_vld),
         .rd_en         (rd_dest),
         .dout          (dst_ip_fifo),
         .full          (),
         .nearly_full   (filter_fifo_nearly_full),
         .prog_full     (),
         .empty         (dest_fifo_empty),
         .reset         (reset),
         .clk           (clk)
         );



   assign dest_ip_filter_vld = !empty;


    always @(*) begin
        rd_dest = 0;
        dst_ip_ready = 0;
        state_next = state;

        case(state)

                WAIT: begin
                        if(!dest_fifo_empty) begin
                                rd_dest = 1;
                                dst_ip_ready = 1;
                                state_next = PROCESS;
                        end
                end

                PROCESS: begin
                        if(lookup_ack)
                                state_next = WAIT;
                end
        endcase
     end


   always @(posedge clk) begin
        if(reset)
                state <= WAIT;
        else
                state <= state_next;
   end



   always @(posedge clk) begin
      if(reset) begin
         dst_ip <= 0;
         dst_ip_vld <= 0;
      end
      else begin
         if(word_IP_DST_HI) begin
         	dst_ip[31:16] <= tdata[15:0];
            	dst_ip_vld <= 0;
         end
         if(word_IP_DST_LO) begin
            	dst_ip[15:0]  <= tdata[255:240];
            	dst_ip_vld <= 1;
         end
         else begin
            dst_ip_vld <= 0;
         end
      end
   end

endmodule
module dest_ip_filter
    #(parameter C_S_AXIS_DATA_WIDTH	= 256,
      parameter LUT_DEPTH		= 32,
      parameter LUT_DEPTH_BITS		= log2(LUT_DEPTH)
      )
   (
    input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,


    output                             dest_ip_hit,
    output                             dest_ip_filter_vld,
    input                              rd_dest_ip_filter_result,


    input                              word_IP_DST_HI,
    input                              word_IP_DST_LO,



    input  [LUT_DEPTH_BITS-1:0]        dest_ip_filter_rd_addr,
    input                              dest_ip_filter_rd_req,
    output [31:0]                      dest_ip_filter_rd_ip,
    output                             dest_ip_filter_rd_ack,


    input [LUT_DEPTH_BITS-1:0]         dest_ip_filter_wr_addr,
    input                              dest_ip_filter_wr_req,
    input [31:0]                       dest_ip_filter_wr_ip,
    output                             dest_ip_filter_wr_ack,


    input                              reset,
    input                              clk
   );



   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction

   localparam	WAIT	= 1;
   localparam	PROCESS	= 2;



   wire                                  cam_busy;
   wire                                  cam_match;
   wire [LUT_DEPTH-1:0]   	         cam_match_addr;
   wire [31:0]                           cam_cmp_din, cam_cmp_data_mask;
   wire [31:0]                           cam_din, cam_data_mask;
   wire                                  cam_we;
   wire [LUT_DEPTH_BITS-1:0]             cam_wr_addr;

   reg                                   dst_ip_vld;
   reg [31:0]                            dst_ip;

   reg                                   rd_dest;
   reg                                   dst_ip_ready;
   wire [31:0]                           dst_ip_fifo;
   wire                                  dest_fifo_empty;

   reg [1:0]                             state,state_next;






   cam 
	#(.C_TCAM_ADDR_WIDTH	(LUT_DEPTH_BITS),
	  .C_TCAM_DATA_WIDTH	(32),
	  .C_TCAM_ADDR_TYPE	(1),
	  .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH)
	)
   dest_ip_cam
     (

      .BUSY                             (cam_busy),
      .MATCH                            (cam_match),
      .MATCH_ADDR                       (cam_match_addr),

      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din),
      .DIN                              (cam_din),
      .WE                               (cam_we),
      .ADDR_WR                          (cam_wr_addr));

   unencoded_cam_lut_sm
     #(.CMP_WIDTH(32),
       .DATA_WIDTH(1),
       .LUT_DEPTH(LUT_DEPTH),
       .DEFAULT_DATA(0)
      ) cam_lut_sm
       (
        .lookup_req          (dst_ip_ready),
        .lookup_cmp_data     (dst_ip_fifo),
        .lookup_cmp_dmask    (32'h0),
        .lookup_ack          (lookup_ack),
        .lookup_hit          (lookup_hit),
        .lookup_data         (),



        .rd_addr             (dest_ip_filter_rd_addr),
        .rd_req              (dest_ip_filter_rd_req),
        .rd_data             (),
        .rd_cmp_data         (dest_ip_filter_rd_ip),
        .rd_cmp_dmask        (),
        .rd_ack              (dest_ip_filter_rd_ack),


        .wr_addr             (dest_ip_filter_wr_addr),
        .wr_req              (dest_ip_filter_wr_req),
        .wr_data             (1'b0),
        .wr_cmp_data         (dest_ip_filter_wr_ip),
        .wr_cmp_dmask        (32'h0),
        .wr_ack              (dest_ip_filter_wr_ack),


        .cam_busy            (cam_busy),
        .cam_match           (cam_match),
        .cam_match_addr      (cam_match_addr),
        .cam_cmp_din         (cam_cmp_din),
        .cam_din             (cam_din),
        .cam_we              (cam_we),
        .cam_wr_addr         (cam_wr_addr),
        .cam_cmp_data_mask   (cam_cmp_data_mask),
        .cam_data_mask       (cam_data_mask),


        .reset               (reset),
        .clk                 (clk));

   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))
      dest_ip_filter_fifo
        (.din           (lookup_hit),
         .wr_en         (lookup_ack),
         .rd_en         (rd_dest_ip_filter_result),
         .dout          (dest_ip_hit),
         .full          (),
         .nearly_full   (),
         .prog_full     (),
         .empty         (empty),
         .reset         (reset),
         .clk           (clk)
         );


  fallthrough_small_fifo #(.WIDTH(32), .MAX_DEPTH_BITS  (2))
      dest_fifo2
        (.din           (dst_ip),
         .wr_en         (dst_ip_vld),
         .rd_en         (rd_dest),
         .dout          (dst_ip_fifo),
         .full          (),
         .nearly_full   (filter_fifo_nearly_full),
         .prog_full     (),
         .empty         (dest_fifo_empty),
         .reset         (reset),
         .clk           (clk)
         );



   assign dest_ip_filter_vld = !empty;


    always @(*) begin
        rd_dest = 0;
        dst_ip_ready = 0;
        state_next = state;

        case(state)

                WAIT: begin
                        if(!dest_fifo_empty) begin
                                rd_dest = 1;
                                dst_ip_ready = 1;
                                state_next = PROCESS;
                        end
                end

                PROCESS: begin
                        if(lookup_ack)
                                state_next = WAIT;
                end
        endcase
     end


   always @(posedge clk) begin
        if(reset)
                state <= WAIT;
        else
                state <= state_next;
   end



   always @(posedge clk) begin
      if(reset) begin
         dst_ip <= 0;
         dst_ip_vld <= 0;
      end
      else begin
         if(word_IP_DST_HI) begin
         	dst_ip[31:16] <= tdata[15:0];
            	dst_ip_vld <= 0;
         end
         if(word_IP_DST_LO) begin
            	dst_ip[15:0]  <= tdata[255:240];
            	dst_ip_vld <= 1;
         end
         else begin
            dst_ip_vld <= 0;
         end
      end
   end

endmodule