data/full_repos/permissive/473722449/johnsoncounter_4bit.v
data/verilator_xmls/38ea9c6c-137e-4e95-82d8-a987051227f5.xml
module johnsoncounter_4bit(
    input clk,
    input reset,
    output reg [3:0] count
    );
    reg [3:0] temp;
    always@(posedge clk or reset)
    begin
        if (reset==1)
            temp=4'b0000;
        else
        begin
            temp ={~temp[0],temp[3:1]};
        end    
        assign count= temp;
    
    end
    
endmodule
module johnsoncounter_4bit(
    input clk,
    input reset,
    output reg [3:0] count
    );

    reg [3:0] temp;
    always@(posedge clk or reset)
    begin
        if (reset==1)
            temp=4'b0000;
        else
        begin
            temp ={~temp[0],temp[3:1]};
        end    
        assign count= temp;
    
    end
    
endmodule