data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 0; B = 0; C = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:31: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 0; B = 1; C = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 0; B = 1; C = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 1; B = 0; C = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:35: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 1; B = 0; C = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 1; B = 1; C = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:37: Unsupported: Ignoring delay on this delayed statement.\n #100;  A = 1; B = 1; C = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Error: data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script/test_FA.v:18: Cannot find file containing module: \'FullAdder\'\n FullAdder uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script,data/full_repos/permissive/448192472/FullAdder\n             data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script,data/full_repos/permissive/448192472/FullAdder.v\n             data/full_repos/permissive/448192472/V07_Full_Adder_Verilog_script,data/full_repos/permissive/448192472/FullAdder.sv\n             FullAdder\n             FullAdder.v\n             FullAdder.sv\n             obj_dir/FullAdder\n             obj_dir/FullAdder.v\n             obj_dir/FullAdder.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_FA;


	reg A;
	reg B;
	reg C;


	wire Sum;
	wire Cy;


	FullAdder uut (
		.A(A), 
		.B(B), 
		.C(C), 
		.Sum(Sum), 
		.Cy(Cy)
	);

	initial 
	begin

		A = 0; B = 0; C = 0;
	#100; 	A = 0; B = 0; C = 1;
	#100; 	A = 0; B = 1; C = 0;
	#100; 	A = 0; B = 1; C = 1;
	
	#100; 	A = 1; B = 0; C = 0;
	#100; 	A = 1; B = 0; C = 1;
	#100; 	A = 1; B = 1; C = 0;
	#100; 	A = 1; B = 1; C = 1;
	#100; 	
	
	$finish;

	end
      
endmodule
module test_FA;



	reg A;
	reg B;
	reg C;


	wire Sum;
	wire Cy;


	FullAdder uut (
		.A(A), 
		.B(B), 
		.C(C), 
		.Sum(Sum), 
		.Cy(Cy)
	);

	initial 
	begin

		A = 0; B = 0; C = 0;
	#100; 	A = 0; B = 0; C = 1;
	#100; 	A = 0; B = 1; C = 0;
	#100; 	A = 0; B = 1; C = 1;
	
	#100; 	A = 1; B = 0; C = 0;
	#100; 	A = 1; B = 0; C = 1;
	#100; 	A = 1; B = 1; C = 0;
	#100; 	A = 1; B = 1; C = 1;
	#100; 	
	
	$finish;

	end
      
endmodule