data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_controller.v:64: Operator SUB expects 16 bits on the LHS, but LHS\'s CONST \'5\'h19\' generates 5 bits.\n                                                                                        : ... In instance data_controller\n   assign temp = (sel != 2\'b11) ? (unsigned_data * 4\'b1001) : {4\'b0000, (5\'d25 - (data - 5\'d25))};\n                                                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_controller.v:64: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'5\'h19\' generates 5 bits.\n                                                                                        : ... In instance data_controller\n   assign temp = (sel != 2\'b11) ? (unsigned_data * 4\'b1001) : {4\'b0000, (5\'d25 - (data - 5\'d25))};\n                                                                                       ^\n%Error: data/full_repos/permissive/52714256/GYRACC/src/GYRO/data_controller.v:68: Cannot find file containing module: \'Binary_To_BCD\'\n   Binary_To_BCD BtoBCD(\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/Binary_To_BCD\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/Binary_To_BCD.v\n             data/full_repos/permissive/52714256/GYRACC/src/GYRO,data/full_repos/permissive/52714256/Binary_To_BCD.sv\n             Binary_To_BCD\n             Binary_To_BCD.v\n             Binary_To_BCD.sv\n             obj_dir/Binary_To_BCD\n             obj_dir/Binary_To_BCD.v\n             obj_dir/Binary_To_BCD.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module data_controller(
		clk,
		dclk,
		rst,
		display_sel,
		sel,
		data,
		D1,
		D2,
		D3,
		D4,
		frmt
);




			input			 clk;
			input			 dclk;
			input			 rst;
			input        display_sel;
			input [1:0]  sel;
			input [15:0] data;
			output [3:0] D1;
			output [3:0] D2;
			output [3:0] D3;
			output [3:0] D4;
            output [15:0] frmt;
   



			wire [15:0]  bcd_buf;
			wire [19:0]  temp;
			wire [15:0]  unsigned_data;
			wire [19:0]  unsigned_scaled_data;
			wire [15:0]  bcd;
   





			assign D1 = (display_sel == 1'b1) ? bcd[15:12] : 4'b0000;
			assign D2 = (display_sel == 1'b1) ? bcd[11:8] : data[15:12];
			assign D3 = (display_sel == 1'b1) ? bcd[7:4] : data[11:8];
			assign D4 = (display_sel == 1'b1) ? bcd[3:0] : data[7:4];
			assign frmt = {D1, D2, D3, D4};
			

			assign bcd[15:12] = ((data[15] == 1'b1 & (bcd[11:0] != 0))) ? 4'b1111 : 4'b1010;
			

			assign unsigned_data = (data[15] == 1'b1) ? ((~(data)) + 1'b1) : data;
			

			assign temp = (sel != 2'b11) ? (unsigned_data * 4'b1001) : {4'b0000, (5'd25 - (data - 5'd25))};
			assign unsigned_scaled_data = (sel != 2'b11) ? {10'b0000000000, temp[19:10]} : temp;
			

			Binary_To_BCD BtoBCD(
						.CLK(clk),
						.RST(rst),
						.START(dclk),
						.BIN(unsigned_scaled_data[15:0]),
						.BCDOUT(bcd_buf)
			);
			

			assign bcd[11:0] = (sel == 2'b11) ? {bcd_buf[7:0], 4'b1011} : bcd_buf[11:0];
   
endmodule
module data_controller(
		clk,
		dclk,
		rst,
		display_sel,
		sel,
		data,
		D1,
		D2,
		D3,
		D4,
		frmt
);





			input			 clk;
			input			 dclk;
			input			 rst;
			input        display_sel;
			input [1:0]  sel;
			input [15:0] data;
			output [3:0] D1;
			output [3:0] D2;
			output [3:0] D3;
			output [3:0] D4;
            output [15:0] frmt;
   



			wire [15:0]  bcd_buf;
			wire [19:0]  temp;
			wire [15:0]  unsigned_data;
			wire [19:0]  unsigned_scaled_data;
			wire [15:0]  bcd;
   





			assign D1 = (display_sel == 1'b1) ? bcd[15:12] : 4'b0000;
			assign D2 = (display_sel == 1'b1) ? bcd[11:8] : data[15:12];
			assign D3 = (display_sel == 1'b1) ? bcd[7:4] : data[11:8];
			assign D4 = (display_sel == 1'b1) ? bcd[3:0] : data[7:4];
			assign frmt = {D1, D2, D3, D4};
			

			assign bcd[15:12] = ((data[15] == 1'b1 & (bcd[11:0] != 0))) ? 4'b1111 : 4'b1010;
			

			assign unsigned_data = (data[15] == 1'b1) ? ((~(data)) + 1'b1) : data;
			

			assign temp = (sel != 2'b11) ? (unsigned_data * 4'b1001) : {4'b0000, (5'd25 - (data - 5'd25))};
			assign unsigned_scaled_data = (sel != 2'b11) ? {10'b0000000000, temp[19:10]} : temp;
			

			Binary_To_BCD BtoBCD(
						.CLK(clk),
						.RST(rst),
						.START(dclk),
						.BIN(unsigned_scaled_data[15:0]),
						.BCDOUT(bcd_buf)
			);
			

			assign bcd[11:0] = (sel == 2'b11) ? {bcd_buf[7:0], 4'b1011} : bcd_buf[11:0];
   
endmodule