data/full_repos/permissive/451577625/system/cla_4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b0100; in_y = 4\'b0010; in_carry = 0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b0000; in_y = 4\'b0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b0100; in_y = 4\'b0010; in_carry = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b0000; in_y = 4\'b0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b1111; in_y = 4\'b0010; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b0000; in_y = 4\'b0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 4\'b1111; in_y = 4\'b0010; in_carry = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_4.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-IMPLICIT: data/full_repos/permissive/451577625/system/cla_4.v:8: Signal definition not found, creating implicitly: \'out_carry\'\n                                                                        : ... Suggested alternative: \'in_carry\'\n assign out_carry = w_carry[4];\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/cla_4.v:14: Cannot find file containing module: \'b_cell_1\'\n   b_cell_1 bcell(.in_x (in_x[i]),\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/b_cell_1\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/b_cell_1.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/b_cell_1.sv\n             b_cell_1\n             b_cell_1.v\n             b_cell_1.sv\n             obj_dir/b_cell_1\n             obj_dir/b_cell_1.v\n             obj_dir/b_cell_1.sv\n%Error: data/full_repos/permissive/451577625/system/cla_4.v:23: Cannot find file containing module: \'cla_logic\'\n cla_logic cla(.in_carry (w_carry[0]),\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cla_4_tb;

	reg [3:0] in_x, in_y;
	reg in_carry;
	
	wire [3:0] out_sum;
	wire out_generate, out_propogate, out_carry;
	
	parameter delay = 10;
	
	cla_4 DUT(.in_x (in_x),
		.in_y (in_y),
		.in_carry (in_carry),
		.out_sum (out_sum),
		.out_generate (out_generate),
		.out_propogate (out_propogate));
		
	initial begin
		in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		
		#(delay) in_x = 4'b0100; in_y = 4'b0010; in_carry = 0;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b0100; in_y = 4'b0010; in_carry = 1;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b1111; in_y = 4'b0010; in_carry = 0;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b1111; in_y = 4'b0010; in_carry = 1;
		#100;
	end

endmodule
module cla_4_tb;


	reg [3:0] in_x, in_y;
	reg in_carry;
	
	wire [3:0] out_sum;
	wire out_generate, out_propogate, out_carry;
	
	parameter delay = 10;
	
	cla_4 DUT(.in_x (in_x),
		.in_y (in_y),
		.in_carry (in_carry),
		.out_sum (out_sum),
		.out_generate (out_generate),
		.out_propogate (out_propogate));
		
	initial begin
		in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		
		#(delay) in_x = 4'b0100; in_y = 4'b0010; in_carry = 0;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b0100; in_y = 4'b0010; in_carry = 1;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b1111; in_y = 4'b0010; in_carry = 0;
		#(delay) in_x = 4'b0000; in_y = 4'b0000; in_carry = 0;
		#(delay) in_x = 4'b1111; in_y = 4'b0010; in_carry = 1;
		#100;
	end

endmodule