data/full_repos/permissive/476296842/rtl/tb/tb_pc.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:3: Cannot find include file: rtl/core/pc.v\n`include "rtl/core/pc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/pc.v\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/pc.v.v\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/pc.v.sv\n             rtl/core/pc.v\n             rtl/core/pc.v.v\n             rtl/core/pc.v.sv\n             obj_dir/rtl/core/pc.v\n             obj_dir/rtl/core/pc.v.v\n             obj_dir/rtl/core/pc.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:15: Define or directive not defined: \'`inst_addr_bus\'\nreg   [`inst_addr_bus] jump_addr_i         = 0 ;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg   [`inst_addr_bus] jump_addr_i         = 0 ;\n                     ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:16: Define or directive not defined: \'`holdpip_bus\'\nreg   [`holdpip_bus]   hold_flag_i         = 0 ;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg   [`holdpip_bus]   hold_flag_i         = 0 ;\n                   ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:20: Define or directive not defined: \'`inst_bus\'\nwire  [`inst_bus]     pc_o                 ;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire  [`inst_bus]     pc_o                 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:25: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2)  clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD*2) rst_n  =  1;\n    ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:31: syntax error, unexpected \'@\'\n    repeat(10) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:32: Define or directive not defined: \'`hold_wait\'\n    hold_flag_i = `hold_wait;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    hold_flag_i = `hold_wait;\n                            ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:33: syntax error, unexpected \'@\'\n    repeat(2) @(negedge clk);\n              ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:34: Define or directive not defined: \'`hold_no\'\n    hold_flag_i = `hold_no;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    hold_flag_i = `hold_no;\n                          ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:35: syntax error, unexpected \'@\'\n    repeat(10) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:36: Define or directive not defined: \'`hold_flush\'\n    hold_flag_i = `hold_flush;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    hold_flag_i = `hold_flush;\n                             ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:37: Define or directive not defined: \'`jump_enable\'\n    jump_flag_i = `jump_enable;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    jump_flag_i = `jump_enable;\n                              ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:39: syntax error, unexpected \'@\'\n    repeat(1) @(negedge clk);\n              ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:40: Define or directive not defined: \'`hold_no\'\n    hold_flag_i = `hold_no;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    hold_flag_i = `hold_no;\n                          ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:41: Define or directive not defined: \'`jump_disable\'\n    jump_flag_i = `jump_disable;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    jump_flag_i = `jump_disable;\n                               ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:42: syntax error, unexpected \'@\'\n    repeat(10) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:59: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./release/tb_pc.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_pc.v:60: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, tb_pc);\n    ^~~~~~~~~\n%Error: Exiting due to 26 error(s), 2 warning(s)\n'
module tb_pc;


parameter PERIOD  = 10;



reg   clk                                  = 0 ;
reg   rst_n                                = 0 ;
reg   jump_flag_i                          = 0 ;
reg   [`inst_addr_bus] jump_addr_i         = 0 ;
reg   [`holdpip_bus]   hold_flag_i         = 0 ;
reg   jtag_reset_i                         = 0 ;


wire  [`inst_bus]     pc_o                 ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
    repeat(10) @(negedge clk);
    hold_flag_i = `hold_wait;
    repeat(2) @(negedge clk);
    hold_flag_i = `hold_no;
    repeat(10) @(negedge clk);
    hold_flag_i = `hold_flush;
    jump_flag_i = `jump_enable;
    jump_addr_i = 32'h02000000;
    repeat(1) @(negedge clk);
    hold_flag_i = `hold_no;
    jump_flag_i = `jump_disable;
    repeat(10) @(negedge clk);
    $finish;
end

pc  u_pc (
    .clk                            ( clk                            ),
    .rst_n                          ( rst_n                          ),
    .jump_flag_i                    ( jump_flag_i                    ),
    .jump_addr_i                    ( jump_addr_i                    ),
    .hold_flag_i                    ( hold_flag_i                    ),
    .jtag_reset_i                   ( jtag_reset_i                   ),

    .pc_o                           ( pc_o                           )
);

initial
begin
    $dumpfile("./release/tb_pc.vcd");
    $dumpvars(0, tb_pc);
end

endmodule
module tb_pc;



parameter PERIOD  = 10;



reg   clk                                  = 0 ;
reg   rst_n                                = 0 ;
reg   jump_flag_i                          = 0 ;
reg   [`inst_addr_bus] jump_addr_i         = 0 ;
reg   [`holdpip_bus]   hold_flag_i         = 0 ;
reg   jtag_reset_i                         = 0 ;


wire  [`inst_bus]     pc_o                 ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
    repeat(10) @(negedge clk);
    hold_flag_i = `hold_wait;
    repeat(2) @(negedge clk);
    hold_flag_i = `hold_no;
    repeat(10) @(negedge clk);
    hold_flag_i = `hold_flush;
    jump_flag_i = `jump_enable;
    jump_addr_i = 32'h02000000;
    repeat(1) @(negedge clk);
    hold_flag_i = `hold_no;
    jump_flag_i = `jump_disable;
    repeat(10) @(negedge clk);
    $finish;
end

pc  u_pc (
    .clk                            ( clk                            ),
    .rst_n                          ( rst_n                          ),
    .jump_flag_i                    ( jump_flag_i                    ),
    .jump_addr_i                    ( jump_addr_i                    ),
    .hold_flag_i                    ( hold_flag_i                    ),
    .jtag_reset_i                   ( jtag_reset_i                   ),

    .pc_o                           ( pc_o                           )
);

initial
begin
    $dumpfile("./release/tb_pc.vcd");
    $dumpvars(0, tb_pc);
end

endmodule