data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:187: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'CPU\'\nmodule CPU(\n       ^~~\n                                                                                    : ... Top module \'toRAMCollect\'\nmodule toRAMCollect(\n       ^~~~~~~~~~~~\n                                                                                    : ... Top module \'toMem\'\nmodule toMem(\n       ^~~~~\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:104: Cannot find file containing module: \'core\'\ncore QDP(.clk(clk),\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.v\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:147: Cannot find file containing module: \'memCont\'\nmemCont mCa(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:249: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance toMem\n if(status == 0) addrROM <= addrMemory[10:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:257: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                 : ... In instance toMem\n  if(addrMemory[12:11] == 2\'b10) addrRAM8 <= {1\'b1,addrMemory[10:0]};\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:258: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                 : ... In instance toMem\n  else addrRAM8 <= {addrMemory[10:0]};\n                ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module irqcollector(
	input clk,
	input rst,
	
	input irq1,
	input irq2,
	input irq3,
	input irq4,
	input irq5,
	input irq6,
	input irq7,
	
	output reg[2:0] irq
	
);

reg[2:0] s_r0;
reg[2:0] s_r1;
reg[2:0] s_r2;
reg[2:0] s_r3;
reg[2:0] s_r4;
reg[2:0] s_r5;
reg[2:0] s_r6;
reg[2:0] s_r7;

reg[2:0] f_r0;
reg[2:0] f_r1;
reg[2:0] f_r2;
reg[2:0] f_r3;
reg[2:0] f_r4;
reg[2:0] f_r5;
reg[2:0] f_r6;
reg[2:0] f_r7;

reg[2:0] f_t;
reg[2:0] n_t;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_r0 <= 0;
		f_r1 <= 0;
		f_r2 <= 0;
		f_r3 <= 0;
		f_r4 <= 0;
		f_r5 <= 0;
		f_r6 <= 0;
		f_r7 <= 0;
		
		f_t <= 0;
	end else
	begin
		f_r0 <= s_r0;
		f_r1 <= s_r1;
		f_r2 <= s_r2;
		f_r3 <= s_r3;
		f_r4 <= s_r4;
		f_r5 <= s_r5;
		f_r6 <= s_r6;
		f_r7 <= s_r7;
		
		f_t <= n_t;
	end
		
end

always@(*)begin

		irq = 0;
		
		s_r0 = f_r0;
		s_r1 = f_r1;
		s_r2 = f_r2;
		s_r3 = f_r3;
		s_r4 = f_r4;
		s_r5 = f_r5;
		s_r6 = f_r6;
		s_r7 = f_r7;
	
		n_t = f_t + 1;
		
		if(irq1) s_r1 = 3'b001;
		if(irq2) s_r2 = 3'b010;
		if(irq3) s_r3 = 3'b011;
		if(irq4) s_r4 = 3'b100;
		if(irq5) s_r5 = 3'b101;
		if(irq6) s_r6 = 3'b110;
		if(irq7) s_r7 = 3'b111;
		
		case(f_t)
			0: irq = 0;
			1: if(irq1)begin
					irq = 3'd1;
					s_r1 = 0;
				end else
				begin
					irq = f_r1;
					s_r1 = 0;
				end
			2: if(irq2)begin
					irq = 3'd2;
					s_r2 = 0;
				end else
				begin
					irq = f_r2;
					s_r2 = 0;
				end
			3: if(irq3)begin
					irq = 3'd3;
					s_r3 = 0;
				end else
				begin
					irq = f_r3;
					s_r3 = 0;
				end
			4: if(irq4)begin
					irq = 3'd4;
					s_r4 = 0;
				end else
				begin
					irq = f_r4;
					s_r4 = 0;
				end
			5: if(irq5)begin
					irq = 3'd5;
					s_r5 = 0;
				end else
				begin
					irq = f_r5;
					s_r5 = 0;
				end
			6: if(irq6)begin
					irq = 3'd6;
					s_r6 = 0;
				end else
				begin
					irq = f_r6;
					s_r6 = 0;
				end
			7: if(irq7)begin
					irq = 3'd7;
					s_r7 = 0;
				end else
				begin
					irq = f_r7;
					s_r7 = 0;
				end
			default:;
		endcase
end


endmodule
module irqcollector(
	input clk,
	input rst,
	
	input irq1,
	input irq2,
	input irq3,
	input irq4,
	input irq5,
	input irq6,
	input irq7,
	
	output reg[2:0] irq
	
);


reg[2:0] s_r0;
reg[2:0] s_r1;
reg[2:0] s_r2;
reg[2:0] s_r3;
reg[2:0] s_r4;
reg[2:0] s_r5;
reg[2:0] s_r6;
reg[2:0] s_r7;

reg[2:0] f_r0;
reg[2:0] f_r1;
reg[2:0] f_r2;
reg[2:0] f_r3;
reg[2:0] f_r4;
reg[2:0] f_r5;
reg[2:0] f_r6;
reg[2:0] f_r7;

reg[2:0] f_t;
reg[2:0] n_t;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_r0 <= 0;
		f_r1 <= 0;
		f_r2 <= 0;
		f_r3 <= 0;
		f_r4 <= 0;
		f_r5 <= 0;
		f_r6 <= 0;
		f_r7 <= 0;
		
		f_t <= 0;
	end else
	begin
		f_r0 <= s_r0;
		f_r1 <= s_r1;
		f_r2 <= s_r2;
		f_r3 <= s_r3;
		f_r4 <= s_r4;
		f_r5 <= s_r5;
		f_r6 <= s_r6;
		f_r7 <= s_r7;
		
		f_t <= n_t;
	end
		
end

always@(*)begin

		irq = 0;
		
		s_r0 = f_r0;
		s_r1 = f_r1;
		s_r2 = f_r2;
		s_r3 = f_r3;
		s_r4 = f_r4;
		s_r5 = f_r5;
		s_r6 = f_r6;
		s_r7 = f_r7;
	
		n_t = f_t + 1;
		
		if(irq1) s_r1 = 3'b001;
		if(irq2) s_r2 = 3'b010;
		if(irq3) s_r3 = 3'b011;
		if(irq4) s_r4 = 3'b100;
		if(irq5) s_r5 = 3'b101;
		if(irq6) s_r6 = 3'b110;
		if(irq7) s_r7 = 3'b111;
		
		case(f_t)
			0: irq = 0;
			1: if(irq1)begin
					irq = 3'd1;
					s_r1 = 0;
				end else
				begin
					irq = f_r1;
					s_r1 = 0;
				end
			2: if(irq2)begin
					irq = 3'd2;
					s_r2 = 0;
				end else
				begin
					irq = f_r2;
					s_r2 = 0;
				end
			3: if(irq3)begin
					irq = 3'd3;
					s_r3 = 0;
				end else
				begin
					irq = f_r3;
					s_r3 = 0;
				end
			4: if(irq4)begin
					irq = 3'd4;
					s_r4 = 0;
				end else
				begin
					irq = f_r4;
					s_r4 = 0;
				end
			5: if(irq5)begin
					irq = 3'd5;
					s_r5 = 0;
				end else
				begin
					irq = f_r5;
					s_r5 = 0;
				end
			6: if(irq6)begin
					irq = 3'd6;
					s_r6 = 0;
				end else
				begin
					irq = f_r6;
					s_r6 = 0;
				end
			7: if(irq7)begin
					irq = 3'd7;
					s_r7 = 0;
				end else
				begin
					irq = f_r7;
					s_r7 = 0;
				end
			default:;
		endcase
end


endmodule