data/full_repos/permissive/497530416/pipe/AND_64bit/and_64bit.v
data/verilator_xmls/b7bf11bc-452c-4b82-bd97-495d58d1233c.xml
module and_64bit(a, b, c);

input [63:0] a, b;
output [63:0] c;
genvar i;

generate
    for(i = 0; i < 64; i = i+1)
        begin
            and a1(c[i], a[i], b[i]);
        end
endgenerate

endmodule
module and_64bit(a, b, c);


input [63:0] a, b;
output [63:0] c;
genvar i;

generate
    for(i = 0; i < 64; i = i+1)
        begin
            and a1(c[i], a[i], b[i]);
        end
endgenerate

endmodule