data/full_repos/permissive/417394359/uart_tx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417394359/uart_tx_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417394359/uart_tx_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/417394359/uart_tx_tb.v:29: Cannot find file containing module: \'uart_tx\'\nuart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) uut\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/417394359,data/full_repos/permissive/417394359/uart_tx\n             data/full_repos/permissive/417394359,data/full_repos/permissive/417394359/uart_tx.v\n             data/full_repos/permissive/417394359,data/full_repos/permissive/417394359/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tx_tb();

parameter CLKS_PER_BIT=17;

reg       i_Clock;
reg       i_Tx_DV; 
wire      o_Tx_Active;
wire  o_Tx_Serial;
wire clk2mhz;
wire      o_Tx_Done;

uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) uut
  (
   .i_Clock(i_Clock),
   .i_Tx_DV(i_Tx_DV), 
   .clk2mhz(clk2mhz),
   .o_Tx_Active(o_Tx_Active),
   .o_Tx_Serial(o_Tx_Serial),
   .o_Tx_Done(o_Tx_Done)
   );

initial begin
i_Tx_DV=1'b1;
end

always begin
i_Clock=1'b0;
#10;
i_Clock=1'b1;
#10;
end

endmodule
module uart_tx_tb();


parameter CLKS_PER_BIT=17;

reg       i_Clock;
reg       i_Tx_DV; 
wire      o_Tx_Active;
wire  o_Tx_Serial;
wire clk2mhz;
wire      o_Tx_Done;

uart_tx #(.CLKS_PER_BIT(CLKS_PER_BIT)) uut
  (
   .i_Clock(i_Clock),
   .i_Tx_DV(i_Tx_DV), 
   .clk2mhz(clk2mhz),
   .o_Tx_Active(o_Tx_Active),
   .o_Tx_Serial(o_Tx_Serial),
   .o_Tx_Done(o_Tx_Done)
   );

initial begin
i_Tx_DV=1'b1;
end

always begin
i_Clock=1'b0;
#10;
i_Clock=1'b1;
#10;
end

endmodule