data/full_repos/permissive/519458744/BLI201V32I/rtl/core/bli201v32i_core_wbu.v
data/verilator_xmls/954d95a8-3754-423a-8d2c-e1bfdfd883d7.xml
module wbu (
  input  clk,
  input  rst,
  input  [31:0] wbu_i_pc,
  input  [31:0] wbu_i_exu_data,
  input  [31:0] wbu_i_memu_data,
  input  [2:0]  wbu_i_wb_sel,
  output [31:0] wbu_o_wb_data
);

  assign wbu_o_wb_data = (
      ({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
    | ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_data)
    | ({32{wbu_i_wb_sel[2]}} & (wbu_i_pc + 4))
  );

endmodule
module wbu (
  input  clk,
  input  rst,
  input  [31:0] wbu_i_pc,
  input  [31:0] wbu_i_exu_data,
  input  [31:0] wbu_i_memu_data,
  input  [2:0]  wbu_i_wb_sel,
  output [31:0] wbu_o_wb_data
);


  assign wbu_o_wb_data = (
      ({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
    | ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_data)
    | ({32{wbu_i_wb_sel[2]}} & (wbu_i_pc + 4))
  );

endmodule