data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module alu(
	input clk,
	input rst,
	
	input[15:0] fromRAM,
	input[15:0] fstack,
	
	input[15:0] fexp,
	input sexp,
	
	input s,
	
	input[15:0] in,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	input[15:0] data,
	
	input[3:0] mOper,
	
	input[15:0] muldiv,
	
	output[15:0] ssreg1,
	output[15:0] ssreg2,
	output[15:0] ssreg3,
	output[15:0] ssreg4,
	
	input[1:0] bank,
	
	output overflow,
	
	output readIt
);

wire save;
wire block;

wire[15:0] sreg1;
wire[15:0] sreg2;
wire[15:0] sreg3;
wire[15:0] sreg4;
	
wire[15:0] f_sreg1;
wire[15:0] f_sreg2;
wire[15:0] f_sreg3;
wire[15:0] f_sreg4;

wire over;

registers regs(  .bank(0),
					  .clk(clk),
					  .rst(rst),
					  .save(save),
					  
					  .f_sreg1(f_sreg1),
					  .f_sreg2(f_sreg2),
					  .f_sreg3(f_sreg3),
					  .f_sreg4(f_sreg4),
					  
					  .sreg1(sreg1),
					  .sreg2(sreg2),
					  .sreg3(sreg3),
					  .sreg4(sreg4)
);

wire[15:0] num1;
wire[15:0] num2;

selector sel(.ireg1(sreg1),
			.ireg2(sreg2),
			.ireg3(sreg3),
			.ireg4(sreg4),
	
			.reg1(reg1),
			.reg2(reg2),
	
			.num1(num1),
			.num2(num2)
);

wire[15:0] result;

basicALU cmp(

			.in(in),
			
			.fromRAM(fromRAM),
		   .num1(num1),
		   .num2(num2),
		   .muldiv(muldiv),
		  
		  .operation(mOper),
		  
		  .save(save),
		  .arg(data),
	
		  .result(result),
		  
		  .fexp(fexp),
		  .sexp(sexp),
		  
		  .overflow(over),
		  
		  .block(block),
		  
		  .readIt(readIt)

);

saver sav(.result(result),
			 .reg1(reg1),
	
			.ireg1(sreg1),
			.ireg2(sreg2),
			.ireg3(sreg3),
			.ireg4(sreg4),
	
			.oreg1(f_sreg1),
			.oreg2(f_sreg2),
			.oreg3(f_sreg3),
			.oreg4(f_sreg4),
			
			.s(s)
);


assign ssreg1 = sreg1;
assign ssreg2 = sreg2;
assign ssreg3 = sreg3;
assign ssreg4 = sreg4;

assign overflow = over;

endmodule
module alu(
	input clk,
	input rst,
	
	input[15:0] fromRAM,
	input[15:0] fstack,
	
	input[15:0] fexp,
	input sexp,
	
	input s,
	
	input[15:0] in,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	input[15:0] data,
	
	input[3:0] mOper,
	
	input[15:0] muldiv,
	
	output[15:0] ssreg1,
	output[15:0] ssreg2,
	output[15:0] ssreg3,
	output[15:0] ssreg4,
	
	input[1:0] bank,
	
	output overflow,
	
	output readIt
);


wire save;
wire block;

wire[15:0] sreg1;
wire[15:0] sreg2;
wire[15:0] sreg3;
wire[15:0] sreg4;
	
wire[15:0] f_sreg1;
wire[15:0] f_sreg2;
wire[15:0] f_sreg3;
wire[15:0] f_sreg4;

wire over;

registers regs(  .bank(0),
					  .clk(clk),
					  .rst(rst),
					  .save(save),
					  
					  .f_sreg1(f_sreg1),
					  .f_sreg2(f_sreg2),
					  .f_sreg3(f_sreg3),
					  .f_sreg4(f_sreg4),
					  
					  .sreg1(sreg1),
					  .sreg2(sreg2),
					  .sreg3(sreg3),
					  .sreg4(sreg4)
);

wire[15:0] num1;
wire[15:0] num2;

selector sel(.ireg1(sreg1),
			.ireg2(sreg2),
			.ireg3(sreg3),
			.ireg4(sreg4),
	
			.reg1(reg1),
			.reg2(reg2),
	
			.num1(num1),
			.num2(num2)
);

wire[15:0] result;

basicALU cmp(

			.in(in),
			
			.fromRAM(fromRAM),
		   .num1(num1),
		   .num2(num2),
		   .muldiv(muldiv),
		  
		  .operation(mOper),
		  
		  .save(save),
		  .arg(data),
	
		  .result(result),
		  
		  .fexp(fexp),
		  .sexp(sexp),
		  
		  .overflow(over),
		  
		  .block(block),
		  
		  .readIt(readIt)

);

saver sav(.result(result),
			 .reg1(reg1),
	
			.ireg1(sreg1),
			.ireg2(sreg2),
			.ireg3(sreg3),
			.ireg4(sreg4),
	
			.oreg1(f_sreg1),
			.oreg2(f_sreg2),
			.oreg3(f_sreg3),
			.oreg4(f_sreg4),
			
			.s(s)
);


assign ssreg1 = sreg1;
assign ssreg2 = sreg2;
assign ssreg3 = sreg3;
assign ssreg4 = sreg4;

assign overflow = over;

endmodule