data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit.v:9: Signal definition not found, creating implicitly: \'w1\'\nxor X1(w1, a, b);\n       ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit.v:13: Signal definition not found, creating implicitly: \'w2\'\n                                                                                  : ... Suggested alternative: \'w1\'\nand A1(w2, a, b);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_1bit.v:14: Signal definition not found, creating implicitly: \'w3\'\n                                                                                  : ... Suggested alternative: \'w1\'\nand A2(w3, w1, c_in);\n       ^~\n%Error: Exiting due to 3 warning(s)\n'
module add_1bit(a,b,c_in,sum,c_out);

input a,b,c_in;
output sum,c_out;




xor X1(w1, a, b);
xor X2(sum, w1, c_in);


and A1(w2, a, b);
and A2(w3, w1, c_in);
or O1(c_out, w2, w3);

endmodule
module add_1bit(a,b,c_in,sum,c_out);


input a,b,c_in;
output sum,c_out;




xor X1(w1, a, b);
xor X2(sum, w1, c_in);


and A1(w2, a, b);
and A2(w3, w1, c_in);
or O1(c_out, w2, w3);

endmodule