data/full_repos/permissive/463481430/RTL/periph/sdram2rib.v
1: b"%Error: data/full_repos/permissive/463481430/RTL/periph/sdram2rib.v:61: Cannot find file containing module: 'sdr_as_ram'\nsdr_as_ram #( \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/periph,data/full_repos/permissive/463481430/sdr_as_ram\n             data/full_repos/permissive/463481430/RTL/periph,data/full_repos/permissive/463481430/sdr_as_ram.v\n             data/full_repos/permissive/463481430/RTL/periph,data/full_repos/permissive/463481430/sdr_as_ram.sv\n             sdr_as_ram\n             sdr_as_ram.v\n             sdr_as_ram.sv\n             obj_dir/sdr_as_ram\n             obj_dir/sdr_as_ram.v\n             obj_dir/sdr_as_ram.sv\n%Error: data/full_repos/permissive/463481430/RTL/periph/sdram2rib.v:96: Cannot find file containing module: 'SDRAM'\nSDRAM sdram(\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module SDRAM2RIB (
    input wire i_clk,
    input wire i_rstn,


    input wire[31:0] i_ribs_addr,
    input wire i_ribs_wrcs,
    input wire[3:0] i_ribs_mask,
    input wire[31:0] i_ribs_wdata,
    output wire[31:0] o_ribs_rdata,

    input wire i_ribs_req, 
    output wire o_ribs_gnt, 
    output wire o_ribs_rsp, 
    input wire i_ribs_rdy
);

wire  			SDRAM_CLK;
wire 			SDR_RAS;
wire  			SDR_CAS;
wire  			SDR_WE;
wire  [1:0]		SDR_BA; 
wire  [10:0]	SDR_ADDR;
wire  [31:0]	SDR_DQ ;
wire  [3:0]		SDR_DM; 

wire Sdr_init_done;
wire Sdr_init_ref_vld;
wire Sdr_busy;

wire sdr_read_finish;

wire handshake = i_ribs_req & o_ribs_gnt;
reg handshake_rdy;
always @(posedge i_clk or negedge i_rstn) begin
	if(~i_rstn)begin
		handshake_rdy <= 0;
	end
	else if(handshake & (i_ribs_wrcs==1)) begin
		handshake_rdy<=1;
	end
	else begin
		handshake_rdy<=~o_ribs_rsp;
	end
end


assign o_ribs_rsp = (Sdr_init_done & (~(Sdr_init_ref_vld|Sdr_busy))) ?  handshake_rdy | sdr_read_finish : 0;

assign o_ribs_gnt = Sdr_init_ref_vld|Sdr_busy ? 0 : i_ribs_req;


sdr_as_ram #( 
.self_refresh_open(1'b1)
)u2_ram( 
	.Sdr_clk(i_clk),
	.Sdr_clk_sft(i_clk),
	.Rst(~i_rstn),
						
	.Sdr_init_done(Sdr_init_done),
	.Sdr_init_ref_vld(Sdr_init_ref_vld),
	.Sdr_busy(Sdr_busy),
	
	.App_ref_req(1'b0),
	
	.App_wr_en		( (i_ribs_req&(i_ribs_wrcs==1)) 	),
	.App_wr_addr	( i_ribs_addr[22:2] 			),
	.App_wr_dm		( i_ribs_mask 					),
	.App_wr_din		( i_ribs_wdata 					),

	.App_rd_en		( (i_ribs_req&(i_ribs_wrcs==0))	),
	.App_rd_addr	( i_ribs_addr[22:2]				),
	.Sdr_rd_en		( sdr_read_finish					),
	.Sdr_rd_dout	( o_ribs_rdata					),


	.SDRAM_CLK(SDRAM_CLK),
	.SDR_RAS(SDR_RAS),
	.SDR_CAS(SDR_CAS),
	.SDR_WE(SDR_WE),
	.SDR_BA(SDR_BA),
	.SDR_ADDR(SDR_ADDR),
	.SDR_DM(SDR_DM),
	.SDR_DQ(SDR_DQ)	
);


SDRAM sdram(
	.clk(SDRAM_CLK),
	.ras_n(SDR_RAS),
	.cas_n(SDR_CAS),
	.we_n(SDR_WE),
	.addr(SDR_ADDR[10:0]),
	.ba(SDR_BA),
	.dq(SDR_DQ),
	.cs_n(1'b0),
	.dm0(SDR_DM[0]),
	.dm1(SDR_DM[1]),
	.dm2(SDR_DM[2]),
	.dm3(SDR_DM[3]),
	.cke(1'b1)
);
endmodule
module SDRAM2RIB (
    input wire i_clk,
    input wire i_rstn,


    input wire[31:0] i_ribs_addr,
    input wire i_ribs_wrcs,
    input wire[3:0] i_ribs_mask,
    input wire[31:0] i_ribs_wdata,
    output wire[31:0] o_ribs_rdata,

    input wire i_ribs_req, 
    output wire o_ribs_gnt, 
    output wire o_ribs_rsp, 
    input wire i_ribs_rdy
);


wire  			SDRAM_CLK;
wire 			SDR_RAS;
wire  			SDR_CAS;
wire  			SDR_WE;
wire  [1:0]		SDR_BA; 
wire  [10:0]	SDR_ADDR;
wire  [31:0]	SDR_DQ ;
wire  [3:0]		SDR_DM; 

wire Sdr_init_done;
wire Sdr_init_ref_vld;
wire Sdr_busy;

wire sdr_read_finish;

wire handshake = i_ribs_req & o_ribs_gnt;
reg handshake_rdy;
always @(posedge i_clk or negedge i_rstn) begin
	if(~i_rstn)begin
		handshake_rdy <= 0;
	end
	else if(handshake & (i_ribs_wrcs==1)) begin
		handshake_rdy<=1;
	end
	else begin
		handshake_rdy<=~o_ribs_rsp;
	end
end


assign o_ribs_rsp = (Sdr_init_done & (~(Sdr_init_ref_vld|Sdr_busy))) ?  handshake_rdy | sdr_read_finish : 0;

assign o_ribs_gnt = Sdr_init_ref_vld|Sdr_busy ? 0 : i_ribs_req;


sdr_as_ram #( 
.self_refresh_open(1'b1)
)u2_ram( 
	.Sdr_clk(i_clk),
	.Sdr_clk_sft(i_clk),
	.Rst(~i_rstn),
						
	.Sdr_init_done(Sdr_init_done),
	.Sdr_init_ref_vld(Sdr_init_ref_vld),
	.Sdr_busy(Sdr_busy),
	
	.App_ref_req(1'b0),
	
	.App_wr_en		( (i_ribs_req&(i_ribs_wrcs==1)) 	),
	.App_wr_addr	( i_ribs_addr[22:2] 			),
	.App_wr_dm		( i_ribs_mask 					),
	.App_wr_din		( i_ribs_wdata 					),

	.App_rd_en		( (i_ribs_req&(i_ribs_wrcs==0))	),
	.App_rd_addr	( i_ribs_addr[22:2]				),
	.Sdr_rd_en		( sdr_read_finish					),
	.Sdr_rd_dout	( o_ribs_rdata					),


	.SDRAM_CLK(SDRAM_CLK),
	.SDR_RAS(SDR_RAS),
	.SDR_CAS(SDR_CAS),
	.SDR_WE(SDR_WE),
	.SDR_BA(SDR_BA),
	.SDR_ADDR(SDR_ADDR),
	.SDR_DM(SDR_DM),
	.SDR_DQ(SDR_DQ)	
);


SDRAM sdram(
	.clk(SDRAM_CLK),
	.ras_n(SDR_RAS),
	.cas_n(SDR_CAS),
	.we_n(SDR_WE),
	.addr(SDR_ADDR[10:0]),
	.ba(SDR_BA),
	.dq(SDR_DQ),
	.cs_n(1'b0),
	.dm0(SDR_DM[0]),
	.dm1(SDR_DM[1]),
	.dm2(SDR_DM[2]),
	.dm3(SDR_DM[3]),
	.cke(1'b1)
);
endmodule