data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v
1: b'%Error: data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v:5: Cannot find include file: rv_macros.svh\n`include "rv_macros.svh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447030470/verilog/rtl,data/full_repos/permissive/447030470/rv_macros.svh\n             data/full_repos/permissive/447030470/verilog/rtl,data/full_repos/permissive/447030470/rv_macros.svh.v\n             data/full_repos/permissive/447030470/verilog/rtl,data/full_repos/permissive/447030470/rv_macros.svh.sv\n             rv_macros.svh\n             rv_macros.svh.v\n             rv_macros.svh.sv\n             obj_dir/rv_macros.svh\n             obj_dir/rv_macros.svh.v\n             obj_dir/rv_macros.svh.sv\n%Error: data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v:17: Define or directive not defined: \'`RV_TARGET_PORT\'\n  `RV_TARGET_PORT(i_, WIDTH),\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v:17: syntax error, unexpected \'(\', expecting \'[\'\n  `RV_TARGET_PORT(i_, WIDTH),\n                  ^~\n%Error: data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v:18: Define or directive not defined: \'`RV_INITIATOR_PORT\'\n  `RV_INITIATOR_PORT(o_, WIDTH)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447030470/verilog/rtl/fw_rv_buffer.v:25: syntax error, unexpected assign\n assign i_ready = (dat_v == 1\'b0 || (o_valid & o_ready));\n ^~~~~~\n%Error: Exiting due to 5 error(s)\n'
module fw_rv_buffer #(
		parameter WIDTH=8
		) (
		input			clock,
		input			reset,
		`RV_TARGET_PORT(i_, WIDTH),
		`RV_INITIATOR_PORT(o_, WIDTH)
		);
	reg[WIDTH-1:0]			dat;
	reg						dat_v;



	assign i_ready = (dat_v == 1'b0 || (o_valid & o_ready));
	assign o_valid = dat_v;
	assign o_dat = dat;
	
	always @(posedge clock) begin
		if (reset) begin
			dat <= {WIDTH{1'b0}};
			dat_v <= 1'b0;
		end else begin
			if (i_valid && i_ready) begin
				dat <= i_dat;
			end
		
			if (i_valid && i_ready) begin
				dat_v <= 1'b1;
			end else if (o_valid && o_ready) begin
				dat_v <= 1'b0;
			end
		end
	end
endmodule
module fw_rv_buffer #(
		parameter WIDTH=8
		) (
		input			clock,
		input			reset,
		`RV_TARGET_PORT(i_, WIDTH),
		`RV_INITIATOR_PORT(o_, WIDTH)
		);

	reg[WIDTH-1:0]			dat;
	reg						dat_v;



	assign i_ready = (dat_v == 1'b0 || (o_valid & o_ready));
	assign o_valid = dat_v;
	assign o_dat = dat;
	
	always @(posedge clock) begin
		if (reset) begin
			dat <= {WIDTH{1'b0}};
			dat_v <= 1'b0;
		end else begin
			if (i_valid && i_ready) begin
				dat <= i_dat;
			end
		
			if (i_valid && i_ready) begin
				dat_v <= 1'b1;
			end else if (o_valid && o_ready) begin
				dat_v <= 1'b0;
			end
		end
	end
endmodule