data/full_repos/permissive/423547971/FPGA Projects/Candy_Machine_Basys3/twoHz_gen.v
1: b'%Error: Cannot find file containing module: Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/Candy_Machine_Basys3,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/Candy_Machine_Basys3/twoHz_gen.v\n%Error: Exiting due to 3 error(s)\n'
module twoHz_gen(
    input clk_100MHz,
    input reset,
    output clk_2Hz
    );
    
    reg [24:0] counter_reg = 0; 
    reg clk_out = 0;
    
    always @(posedge clk_100MHz or posedge reset) begin
        if(reset)
            counter_reg <= 0;
        else
            if(counter_reg == 24_999_999) begin
                counter_reg <= 0;
                clk_out <= ~clk_out;
            end
            else
                counter_reg <= counter_reg + 1;
    end
    
    assign clk_2Hz = clk_out;
    
endmodule
module twoHz_gen(
    input clk_100MHz,
    input reset,
    output clk_2Hz
    );

    
    reg [24:0] counter_reg = 0; 
    reg clk_out = 0;
    
    always @(posedge clk_100MHz or posedge reset) begin
        if(reset)
            counter_reg <= 0;
        else
            if(counter_reg == 24_999_999) begin
                counter_reg <= 0;
                clk_out <= ~clk_out;
            end
            else
                counter_reg <= counter_reg + 1;
    end
    
    assign clk_2Hz = clk_out;
    
endmodule