data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:29: Unsupported or unknown PLI call: $__XILINX_SHREG_\nmodule $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:29: syntax error, unexpected ${ignored-bbox-sys}, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);\n                       ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:36: syntax error, unexpected always\nalways @(posedge C)\n^~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xilinx_srl_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;

always @(posedge clk) begin
    head <= i;
    shift1 <= {shift1[2:0], head};
    shift2 <= {shift2[2:0], head};
end

assign q = {shift2[3], shift1[3]};
endmodule
module xilinx_srl_static_test(input i, clk, output [1:0] q);

reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;

always @(posedge clk) begin
    head <= i;
    shift1 <= {shift1[2:0], head};
    shift2 <= {shift2[2:0], head};
end

assign q = {shift2[3], shift1[3]};
endmodule