data/full_repos/permissive/420819839/Basics/AndGate.v
data/verilator_xmls/b0b54c35-a54e-4189-a6d6-cf2a9e291417.xml
module top_module(
        input a,
        input b,
        output out );
    assign out = a && b;
endmodule
module top_module(
        input a,
        input b,
        output out );

    assign out = a && b;
endmodule