data/full_repos/permissive/531012469/verilog/rtl/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:368: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            1 : r_result =  in1 <  in2;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:369: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            2 : r_result = sin1 < sin2;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:256: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'cnt_start\' generates 12 bits.\n                                                                           : ... In instance rvcorep.ploader.serc\n          stage <= (cnt_start == (waitcnt >> 1)) ? \'d1 : stage;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:484: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire w_bmis = ExMa_b & (ExMa_b_rslt ? ExMa_b_rslt_t1 : ExMa_b_rslt_t2);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:485: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [17:0] w_pc_true = {((ExMa_b_rslt) ? ExMa_tkn_pc[17:2]: ExMa_npc[17:2]), 2\'b00};\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:491: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign I_ADDR = {w_npc, 2\'b00};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:623: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[1]) ? IfId_pc + {IfId_ir[31:12], 12\'b0} :   \n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:624: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[2]) ? IfId_pc + 4                       : 0;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IdEx_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:711: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [7:0]  w_lb_t = D_IN >> ({w_adr, 3\'d0});\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:760: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'MaWb_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n        else r_rout <= (MaWb_v) ? MaWb_pc : r_rout;  \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:58: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'initwe\' generates 4 bits.\n                                                                          : ... In instance rvcorep\n        initaddr <= (r_rst) ? 0 : (initwe)   ? initaddr + 4 : initaddr;\n                                             ^\n%Error: Exiting due to 13 warning(s)\n'
module rvcorep(clk, rst, w_rxd, r_txd, led);
    input  wire       clk, rst;
    input  wire       w_rxd;
    output reg        r_txd;
    output wire [3:0] led;
    
    wire w_clk = clk;

    reg r_rst;
    always @(posedge w_clk) r_rst <= rst;
    
    reg core_rst;
    always @(posedge w_clk) core_rst <= (r_rst | !initdone);

    reg [31:0] r_scnt;
    always @(posedge w_clk) begin
       if(r_rst) r_scnt = 0;
       else  r_scnt <= r_scnt + 1;
    end
    
    reg r_inv;
    always @(posedge w_clk) r_inv <= rst;
    
    assign led = {r_scnt[24:22], r_inv};
    

    reg r_rxd_t1,  r_rxd_t2;
    always@(posedge w_clk) r_rxd_t1 <= w_rxd;
    always@(posedge w_clk) r_rxd_t2 <= r_rxd_t1;
    

    wire [31:0] w_initdata;
    wire [31:0] w_initaddr;
    wire        w_initwe;
    wire        w_initdone;
    PLOADER ploader(w_clk, !r_rst, r_rxd_t2, w_initaddr, w_initdata, w_initwe, w_initdone);

    reg  [31:0] initdata;
    reg  [31:0] initaddr;
    reg  [3:0]  initwe;
    reg         initdone;
    always@(posedge w_clk) begin
        initdata <= (r_rst) ? 0 : (w_initwe) ? w_initdata   : 0;
        initaddr <= (r_rst) ? 0 : (initwe)   ? initaddr + 4 : initaddr;
        initwe   <= (r_rst) ? 0 : {4{w_initwe}};
        initdone <= (r_rst) ? 0 : w_initdone;
    end


    wire        w_halt;
    wire [31:0] w_rout, I_DATA, I_ADDR, D_DATA, WD_DATA, D_ADDR;
    wire [3:0]  D_WE;

    RVCore p(w_clk, !core_rst, w_rout, w_halt, I_ADDR, D_ADDR, I_DATA, D_DATA, WD_DATA, D_WE);

    wire [31:0] tmpdata;
    m_IMEM#(32,`MEM_SIZE/4) imem(w_clk, initwe[0], initaddr[$clog2(`MEM_SIZE)-1:2], 
                                 I_ADDR[$clog2(`MEM_SIZE)-1:2], initdata, I_DATA);
    m_DMEM#(32,`MEM_SIZE/4) dmem(w_clk, core_rst, initwe, initaddr[$clog2(`MEM_SIZE)-1:2], 
                                 initdata, tmpdata, w_clk, !core_rst, D_WE, 
                                 D_ADDR[$clog2(`MEM_SIZE)-1:2], WD_DATA, D_DATA);
                                 

    reg        r_D_ADDR;
    reg        r_D_WE;
    reg [31:0] r_WD_DATA;
    always@(posedge w_clk) begin
        if(r_rst) begin
            r_D_ADDR  <= 0;
            r_D_WE    <= 0;
            r_WD_DATA <= 0;
        end
        else begin
            r_D_ADDR  <= D_ADDR[15] & D_ADDR[30];
            r_D_WE    <= D_WE[0];
            r_WD_DATA <= WD_DATA;
        end
    end

    reg        tohost_we;
    reg [31:0] tohost_data;
    reg [7:0]  tohost_char;
    reg [1:0]  tohost_cmd;
    always@(posedge w_clk) begin
        if(r_rst) begin
            tohost_we   <= 0;
            tohost_data <= 0;
            tohost_char <= 0;
            tohost_cmd  <= 0;           
        end
        else begin
            tohost_we   <= (r_D_ADDR && (r_D_WE));
            tohost_data <= r_WD_DATA;
            tohost_char <= (tohost_we) ? tohost_data[7:0] : 0;
            tohost_cmd  <= (tohost_we) ? tohost_data[17:16] : 0;
        end
    end


    reg [7:0] squeue[0:`QUEUE_SIZE-1];
    reg  [$clog2(`QUEUE_SIZE)-1:0] queue_head = 0;
    reg  [$clog2(`QUEUE_SIZE)-1:0] queue_num  = 0;
    always@(posedge w_clk) begin
        if(r_rst) begin
            queue_head <= 0;
            queue_num <= 0;
        end
        else begin
            if(printchar) squeue[queue_addr] <= tohost_char;
            queue_head <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? 
                           queue_head + 1 : queue_head;
            queue_num <= (printchar) ? queue_num + 1 : (tx_ready & (queue_num > 0) & !uartwe)
                          ? queue_num - 1 : queue_num;
        end
    end
    wire [$clog2(`QUEUE_SIZE)-1:0] queue_addr = queue_head+queue_num;
    wire printchar = (tohost_cmd==1);
    
    reg [7:0] uartdata;
    reg       uartwe;
    always@(posedge w_clk) begin
        if(r_rst) begin
            uartdata <= 0;
            uartwe <= 0;
        end
        else begin
            uartdata <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? squeue[queue_head] : 0;
            uartwe   <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? 1                  : 0;
        end
    end
    
    always@(posedge w_clk) r_txd <= w_txd;
    wire w_txd;
    wire tx_ready;
    UartTx UartTx0(w_clk, !core_rst, uartdata, uartwe, w_txd, tx_ready);
endmodule
module rvcorep(clk, rst, w_rxd, r_txd, led);

    input  wire       clk, rst;
    input  wire       w_rxd;
    output reg        r_txd;
    output wire [3:0] led;
    
    wire w_clk = clk;

    reg r_rst;
    always @(posedge w_clk) r_rst <= rst;
    
    reg core_rst;
    always @(posedge w_clk) core_rst <= (r_rst | !initdone);

    reg [31:0] r_scnt;
    always @(posedge w_clk) begin
       if(r_rst) r_scnt = 0;
       else  r_scnt <= r_scnt + 1;
    end
    
    reg r_inv;
    always @(posedge w_clk) r_inv <= rst;
    
    assign led = {r_scnt[24:22], r_inv};
    

    reg r_rxd_t1,  r_rxd_t2;
    always@(posedge w_clk) r_rxd_t1 <= w_rxd;
    always@(posedge w_clk) r_rxd_t2 <= r_rxd_t1;
    

    wire [31:0] w_initdata;
    wire [31:0] w_initaddr;
    wire        w_initwe;
    wire        w_initdone;
    PLOADER ploader(w_clk, !r_rst, r_rxd_t2, w_initaddr, w_initdata, w_initwe, w_initdone);

    reg  [31:0] initdata;
    reg  [31:0] initaddr;
    reg  [3:0]  initwe;
    reg         initdone;
    always@(posedge w_clk) begin
        initdata <= (r_rst) ? 0 : (w_initwe) ? w_initdata   : 0;
        initaddr <= (r_rst) ? 0 : (initwe)   ? initaddr + 4 : initaddr;
        initwe   <= (r_rst) ? 0 : {4{w_initwe}};
        initdone <= (r_rst) ? 0 : w_initdone;
    end


    wire        w_halt;
    wire [31:0] w_rout, I_DATA, I_ADDR, D_DATA, WD_DATA, D_ADDR;
    wire [3:0]  D_WE;

    RVCore p(w_clk, !core_rst, w_rout, w_halt, I_ADDR, D_ADDR, I_DATA, D_DATA, WD_DATA, D_WE);

    wire [31:0] tmpdata;
    m_IMEM#(32,`MEM_SIZE/4) imem(w_clk, initwe[0], initaddr[$clog2(`MEM_SIZE)-1:2], 
                                 I_ADDR[$clog2(`MEM_SIZE)-1:2], initdata, I_DATA);
    m_DMEM#(32,`MEM_SIZE/4) dmem(w_clk, core_rst, initwe, initaddr[$clog2(`MEM_SIZE)-1:2], 
                                 initdata, tmpdata, w_clk, !core_rst, D_WE, 
                                 D_ADDR[$clog2(`MEM_SIZE)-1:2], WD_DATA, D_DATA);
                                 

    reg        r_D_ADDR;
    reg        r_D_WE;
    reg [31:0] r_WD_DATA;
    always@(posedge w_clk) begin
        if(r_rst) begin
            r_D_ADDR  <= 0;
            r_D_WE    <= 0;
            r_WD_DATA <= 0;
        end
        else begin
            r_D_ADDR  <= D_ADDR[15] & D_ADDR[30];
            r_D_WE    <= D_WE[0];
            r_WD_DATA <= WD_DATA;
        end
    end

    reg        tohost_we;
    reg [31:0] tohost_data;
    reg [7:0]  tohost_char;
    reg [1:0]  tohost_cmd;
    always@(posedge w_clk) begin
        if(r_rst) begin
            tohost_we   <= 0;
            tohost_data <= 0;
            tohost_char <= 0;
            tohost_cmd  <= 0;           
        end
        else begin
            tohost_we   <= (r_D_ADDR && (r_D_WE));
            tohost_data <= r_WD_DATA;
            tohost_char <= (tohost_we) ? tohost_data[7:0] : 0;
            tohost_cmd  <= (tohost_we) ? tohost_data[17:16] : 0;
        end
    end


    reg [7:0] squeue[0:`QUEUE_SIZE-1];
    reg  [$clog2(`QUEUE_SIZE)-1:0] queue_head = 0;
    reg  [$clog2(`QUEUE_SIZE)-1:0] queue_num  = 0;
    always@(posedge w_clk) begin
        if(r_rst) begin
            queue_head <= 0;
            queue_num <= 0;
        end
        else begin
            if(printchar) squeue[queue_addr] <= tohost_char;
            queue_head <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? 
                           queue_head + 1 : queue_head;
            queue_num <= (printchar) ? queue_num + 1 : (tx_ready & (queue_num > 0) & !uartwe)
                          ? queue_num - 1 : queue_num;
        end
    end
    wire [$clog2(`QUEUE_SIZE)-1:0] queue_addr = queue_head+queue_num;
    wire printchar = (tohost_cmd==1);
    
    reg [7:0] uartdata;
    reg       uartwe;
    always@(posedge w_clk) begin
        if(r_rst) begin
            uartdata <= 0;
            uartwe <= 0;
        end
        else begin
            uartdata <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? squeue[queue_head] : 0;
            uartwe   <= (!printchar & tx_ready & (queue_num > 0) & !uartwe) ? 1                  : 0;
        end
    end
    
    always@(posedge w_clk) r_txd <= w_txd;
    wire w_txd;
    wire tx_ready;
    UartTx UartTx0(w_clk, !core_rst, uartdata, uartwe, w_txd, tx_ready);
endmodule