data/full_repos/permissive/465389471/TLC_topModule_labsland.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:60: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'an\' generates 4 bits.\n                                                                                : ... In instance TLC_topModule_labsland\n    assign LEDG[0] = an;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:67: Cannot find file containing module: \'TwelveHourBCDclock\'\nTwelveHourBCDclock BCD_clk(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.v\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.sv\n             TwelveHourBCDclock\n             TwelveHourBCDclock.v\n             TwelveHourBCDclock.sv\n             obj_dir/TwelveHourBCDclock\n             obj_dir/TwelveHourBCDclock.v\n             obj_dir/TwelveHourBCDclock.sv\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:77: Cannot find file containing module: \'peak_offpeak\'\npeak_offpeak BCD_peak(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:83: Cannot find file containing module: \'TLC_main\'\nTLC_main Tlc_1(\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module decoder_7seg(in1,out1);

  input [3:0] in1;
  output reg [6:0] out1;
 

    
  always @ (in1)
    case (in1)
      4'b0000 : out1=7'b1000000;
      4'b0001 : out1=7'b1111001;
      4'b0010 : out1=7'b0100100;
      4'b0011 : out1=7'b0110000;
      4'b0100 : out1=7'b0011001;
      4'b0101 : out1=7'b0010010;
      4'b0110 : out1=7'b0000010;
      4'b0111 : out1=7'b1111000;
      4'b1000 : out1=7'b0000000;
      4'b1001 : out1=7'b0010000;
      4'b1010 : out1=7'b0001000;
      4'b1011 : out1=7'b0000011;
      4'b1100 : out1=7'b1000110;
      4'b1101 : out1=7'b0100001;
      4'b1110 : out1=7'b0000110;
      4'b1111 : out1=7'b0001110;
    endcase
    
    
endmodule
module decoder_7seg(in1,out1);


  input [3:0] in1;
  output reg [6:0] out1;
 

    
  always @ (in1)
    case (in1)
      4'b0000 : out1=7'b1000000;
      4'b0001 : out1=7'b1111001;
      4'b0010 : out1=7'b0100100;
      4'b0011 : out1=7'b0110000;
      4'b0100 : out1=7'b0011001;
      4'b0101 : out1=7'b0010010;
      4'b0110 : out1=7'b0000010;
      4'b0111 : out1=7'b1111000;
      4'b1000 : out1=7'b0000000;
      4'b1001 : out1=7'b0010000;
      4'b1010 : out1=7'b0001000;
      4'b1011 : out1=7'b0000011;
      4'b1100 : out1=7'b1000110;
      4'b1101 : out1=7'b0100001;
      4'b1110 : out1=7'b0000110;
      4'b1111 : out1=7'b0001110;
    endcase
    
    
endmodule