data/full_repos/permissive/477770962/add4.v
data/verilator_xmls/c5ca913d-cf5e-41ac-bd2e-363877c74bf2.xml
module add4(a, b, sum, cout);
	input [3:0] a, b; 
	output reg [3:0] sum;
	output reg cout;
	
	wire [4:0] sum1;

	assign sum1 = a + b;
	assign cout = sum1[4];
	assign sum = sum1[3:0];
	
endmodule
module add4(a, b, sum, cout);

	input [3:0] a, b; 
	output reg [3:0] sum;
	output reg cout;
	
	wire [4:0] sum1;

	assign sum1 = a + b;
	assign cout = sum1[4];
	assign sum = sum1[3:0];
	
endmodule