data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:20: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 0; shift = 3\'b0; immediate_value = 16\'b0010_0100_0001_1xxx; source1 = 32\'h5555_5555; source2 = 32\'h3333_3333; cond = 4\'b0000; opcode = 4\'b0001; pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:22: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b001; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'b0000_1001; source2 = 32\'b0000_0110; cond = 4\'b0000; opcode = 4\'b0011; pc_trigger=1\'b1; pc_reset=1\'b1;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:24: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0000_1111; source2 = 32\'h0000_1111; cond = 4\'b0000; opcode = 4\'b0001; pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:26: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0000_0000; source2 = 32\'h0000_ffff; cond = 4\'b0000; opcode = 4\'b0001; pc_trigger=1\'b1; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10     s = 1; shift=3\'b0; immediate_value = 16\'b0001_0011_0000_1xxx; source1 = 32\'b101; source2 = 32\'b101; cond = 4\'b0000; opcode = 4\'b0010; pc_trigger=1\'b0; pc_reset=1\'b1;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:30: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0001_1111; source2 = 32\'h0000_1111; cond = 4\'b0000; opcode = 4\'b0100; pc_trigger=1\'b1; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:32: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0001_1110; source2 = 32\'h0000_1111; cond = 4\'b0000; opcode = 4\'b0101;  pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:34: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b1111_1111_1111_1111; source1 = 32\'h0001_1110; source2 = 32\'h0000_1111; cond = 4\'b0000; opcode = 4\'b0110;  pc_trigger=1\'b1; pc_reset=1\'b0; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:36: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b1111_1111_1111_1111; source1 = 32\'h0001_1110; source2 = 32\'h0000_1111; cond = 4\'b0000; opcode = 4\'b0111;  pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:38: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0000_1111; source2 = 32\'h0000_1111; cond = 4\'b0001; opcode = 4\'b1000;  pc_trigger=1\'b1; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:40: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'hF001_1111; source2 = 32\'h0000_1111; cond = 4\'b0010; opcode = 4\'b1000;  pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:42: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0001_1111; source2 = 32\'h0000_1111; cond = 4\'b0110; opcode = 4\'b1000;  pc_trigger=1\'b1; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0001_1111; source2 = 32\'h0000_1111; cond = 4\'b0110; opcode = 4\'b1001;  pc_trigger=1\'b0; pc_reset=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:46: Unsupported: Ignoring delay on this delayed statement.\n#10  s = 1; shift = 3\'b0; immediate_value = 16\'b0001_0011_0001_1xxx; source1 = 32\'h0001_1111; source2 = 32\'h0000_1111; cond = 4\'b0110; opcode = 4\'b1111;  pc_trigger=1\'b1; pc_reset=1\'b1; \n^\n%Error: data/full_repos/permissive/449807379/CPU_design/Test_bench_alu.v:52: Unsupported or unknown PLI call: $monitor\n$monitor($time, " \\nsource1 = %b \\nsource2 = %b\\nsrce2_int=%b \\nresult =  %b, flags (nzcv) = %b, program counter=%d", source1, source2, Test_ALU_call.intermediate_source2, result, flags, pc_out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_ALU;
reg s;
reg [2:0] shift;
reg [15:0] immediate_value;
reg [31:0] source1,source2;
reg [3:0] cond,opcode;
wire [31:0] result;
wire [3:0] flags;

reg pc_trigger, pc_reset;
wire [7:0] pc_out;




initial
begin
	s = 0; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_00001; source2 = 32'h0000_0002; cond = 4'b0000; opcode = 4'b0000; pc_trigger=1'b1; pc_reset=1'b0;

#10 	s = 0; shift = 3'b0; immediate_value = 16'b0010_0100_0001_1xxx; source1 = 32'h5555_5555; source2 = 32'h3333_3333; cond = 4'b0000; opcode = 4'b0001;	pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b001; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'b0000_1001; source2 = 32'b0000_0110; cond = 4'b0000; opcode = 4'b0011; pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_1111; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0001;	pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_0000; source2 = 32'h0000_ffff; cond = 4'b0000; opcode = 4'b0001; pc_trigger=1'b1; pc_reset=1'b1;

#10     s = 1; shift=3'b0; immediate_value = 16'b0001_0011_0000_1xxx; source1 = 32'b101; source2 = 32'b101; cond = 4'b0000; opcode = 4'b0010; pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0100;	pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0101;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b1111_1111_1111_1111; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0110;	 pc_trigger=1'b1; pc_reset=1'b0;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b1111_1111_1111_1111; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0111;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_1111; source2 = 32'h0000_1111; cond = 4'b0001; opcode = 4'b1000;	 pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'hF001_1111; source2 = 32'h0000_1111; cond = 4'b0010; opcode = 4'b1000;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1000;	 pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1001;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1111;	 pc_trigger=1'b1; pc_reset=1'b1;


end
initial
begin
$monitor($time, " \nsource1 = %b \nsource2 = %b\nsrce2_int=%b \nresult =  %b, flags (nzcv) = %b, program counter=%d", source1, source2, Test_ALU_call.intermediate_source2, result, flags, pc_out);
end

alu_control Test_ALU_call(cond, opcode, s, shift, immediate_value, source1, source2, result, flags, pc_trigger, pc_out, pc_reset);
endmodule
module Test_ALU;

reg s;
reg [2:0] shift;
reg [15:0] immediate_value;
reg [31:0] source1,source2;
reg [3:0] cond,opcode;
wire [31:0] result;
wire [3:0] flags;

reg pc_trigger, pc_reset;
wire [7:0] pc_out;




initial
begin
	s = 0; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_00001; source2 = 32'h0000_0002; cond = 4'b0000; opcode = 4'b0000; pc_trigger=1'b1; pc_reset=1'b0;

#10 	s = 0; shift = 3'b0; immediate_value = 16'b0010_0100_0001_1xxx; source1 = 32'h5555_5555; source2 = 32'h3333_3333; cond = 4'b0000; opcode = 4'b0001;	pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b001; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'b0000_1001; source2 = 32'b0000_0110; cond = 4'b0000; opcode = 4'b0011; pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_1111; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0001;	pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_0000; source2 = 32'h0000_ffff; cond = 4'b0000; opcode = 4'b0001; pc_trigger=1'b1; pc_reset=1'b1;

#10     s = 1; shift=3'b0; immediate_value = 16'b0001_0011_0000_1xxx; source1 = 32'b101; source2 = 32'b101; cond = 4'b0000; opcode = 4'b0010; pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0100;	pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0101;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b1111_1111_1111_1111; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0110;	 pc_trigger=1'b1; pc_reset=1'b0;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b1111_1111_1111_1111; source1 = 32'h0001_1110; source2 = 32'h0000_1111; cond = 4'b0000; opcode = 4'b0111;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0000_1111; source2 = 32'h0000_1111; cond = 4'b0001; opcode = 4'b1000;	 pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'hF001_1111; source2 = 32'h0000_1111; cond = 4'b0010; opcode = 4'b1000;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1000;	 pc_trigger=1'b1; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1001;	 pc_trigger=1'b0; pc_reset=1'b1;

#10 	s = 1; shift = 3'b0; immediate_value = 16'b0001_0011_0001_1xxx; source1 = 32'h0001_1111; source2 = 32'h0000_1111; cond = 4'b0110; opcode = 4'b1111;	 pc_trigger=1'b1; pc_reset=1'b1;


end
initial
begin
$monitor($time, " \nsource1 = %b \nsource2 = %b\nsrce2_int=%b \nresult =  %b, flags (nzcv) = %b, program counter=%d", source1, source2, Test_ALU_call.intermediate_source2, result, flags, pc_out);
end

alu_control Test_ALU_call(cond, opcode, s, shift, immediate_value, source1, source2, result, flags, pc_trigger, pc_out, pc_reset);
endmodule