data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/46_NOR_q4e.v
data/verilator_xmls/2f356985-7377-4040-8192-8e14e3a8a7e0.xml
module top_module (
    input in1,
    input in2,
    output out);

    assign out = ~(in1 | in2); 
endmodule
module top_module (
    input in1,
    input in2,
    output out);


    assign out = ~(in1 | in2); 
endmodule