data/full_repos/permissive/487568919/basic_verilog/soft_latch.sv
data/verilator_xmls/2f458c43-8a41-4619-b7ec-3080377f0c81.xml
module soft_latch #( parameter
  bit [7:0] WIDTH = 1
)(
  input clk,
  input anrst,

  input latch,
  input [WIDTH-1:0] in,
  output logic [WIDTH-1:0] out
);

logic [WIDTH-1:0] in_buf = '0;


always_ff @(posedge clk or negedge anrst) begin
  if( ~anrst ) begin
    in_buf[WIDTH-1:0] <= '0;
  end else if( latch ) begin
    in_buf[WIDTH-1:0] <= in[WIDTH-1:0];
  end
end


always_comb begin
  if( ~anrst ) begin
    out[WIDTH-1:0] <= '0;
  end else if( latch ) begin
    out[WIDTH-1:0] <= in[WIDTH-1:0];
  end else begin
    out[WIDTH-1:0] <= in_buf[WIDTH-1:0];
  end


end

endmodule
module soft_latch #( parameter
  bit [7:0] WIDTH = 1
)(
  input clk,
  input anrst,

  input latch,
  input [WIDTH-1:0] in,
  output logic [WIDTH-1:0] out
);


logic [WIDTH-1:0] in_buf = '0;


always_ff @(posedge clk or negedge anrst) begin
  if( ~anrst ) begin
    in_buf[WIDTH-1:0] <= '0;
  end else if( latch ) begin
    in_buf[WIDTH-1:0] <= in[WIDTH-1:0];
  end
end


always_comb begin
  if( ~anrst ) begin
    out[WIDTH-1:0] <= '0;
  end else if( latch ) begin
    out[WIDTH-1:0] <= in[WIDTH-1:0];
  end else begin
    out[WIDTH-1:0] <= in_buf[WIDTH-1:0];
  end


end

endmodule