data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module DataMemory (MEMWRITE, ALUDATA_IN ,QBDATA_IN, DMDATA_OUT);
    input MEMWRITE;
    input [31:0] ALUDATA_IN, QBDATA_IN;

    reg [31:0] DM [0:36];

    output reg [31:0] DMDATA_OUT;

    initial begin
        DM[32'd0] = 32'hA00000AA;
        DM[32'd4] = 32'h10000011;
        DM[32'd8] = 32'h20000022;
        DM[32'd12] = 32'h30000033;
        DM[32'd16] = 32'h40000044;
        DM[32'd20] = 32'h50000055;
        DM[32'd24] = 32'h60000066;
        DM[32'd28] = 32'h70000077;
        DM[32'd32] = 32'h80000088;
        DM[32'd36] = 32'h90000099;
    end
    
    always @ (ALUDATA_IN, QBDATA_IN) begin
        case (MEMWRITE)
            1'b0: DMDATA_OUT <= DM[ALUDATA_IN];
            1'b1: DMDATA_OUT <= DM[QBDATA_IN];  
        endcase
    end
endmodule
module DataMemory (MEMWRITE, ALUDATA_IN ,QBDATA_IN, DMDATA_OUT);

    input MEMWRITE;
    input [31:0] ALUDATA_IN, QBDATA_IN;

    reg [31:0] DM [0:36];

    output reg [31:0] DMDATA_OUT;

    initial begin
        DM[32'd0] = 32'hA00000AA;
        DM[32'd4] = 32'h10000011;
        DM[32'd8] = 32'h20000022;
        DM[32'd12] = 32'h30000033;
        DM[32'd16] = 32'h40000044;
        DM[32'd20] = 32'h50000055;
        DM[32'd24] = 32'h60000066;
        DM[32'd28] = 32'h70000077;
        DM[32'd32] = 32'h80000088;
        DM[32'd36] = 32'h90000099;
    end
    
    always @ (ALUDATA_IN, QBDATA_IN) begin
        case (MEMWRITE)
            1'b0: DMDATA_OUT <= DM[ALUDATA_IN];
            1'b1: DMDATA_OUT <= DM[QBDATA_IN];  
        endcase
    end
endmodule