data/full_repos/permissive/450922687/Task 1/registerFile.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687.sv\n             1,data/full_repos/permissive/450922687\n             1,data/full_repos/permissive/450922687.v\n             1,data/full_repos/permissive/450922687.sv\n             obj_dir/1,data/full_repos/permissive/450922687\n             obj_dir/1,data/full_repos/permissive/450922687.v\n             obj_dir/1,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 1/registerFile.v\n%Error: Exiting due to 3 error(s)\n'
module registerFile (
    input clk, reset, RegWrite,
    input [63:0] WriteData,
    input [4:0] RS1, RS2, RD,
    output reg [63:0] ReadData1, ReadData2
);
  reg[63:0] Registers[31:0];
 
  initial
    begin
      for (int i = 0 ; i < 32; i++)
        begin
          Registers[i]   = 64'b0;
        end
      Registers[11] = 64'd6;
    end
 
  always @(posedge clk)
    begin
      if (RegWrite == 1'b1)
        Registers[RD] = WriteData;
    end
 
  always @(*)
    begin
      if (reset == 1'b1)
        begin
          ReadData1 = 64'b0;
          ReadData2 = 64'b0;
        end
      else
        begin
          ReadData1 = Registers[RS1];
          ReadData2 = Registers[RS2];
        end
    end
endmodule
module registerFile (
    input clk, reset, RegWrite,
    input [63:0] WriteData,
    input [4:0] RS1, RS2, RD,
    output reg [63:0] ReadData1, ReadData2
);

  reg[63:0] Registers[31:0];
 
  initial
    begin
      for (int i = 0 ; i < 32; i++)
        begin
          Registers[i]   = 64'b0;
        end
      Registers[11] = 64'd6;
    end
 
  always @(posedge clk)
    begin
      if (RegWrite == 1'b1)
        Registers[RD] = WriteData;
    end
 
  always @(*)
    begin
      if (reset == 1'b1)
        begin
          ReadData1 = 64'b0;
          ReadData2 = 64'b0;
        end
      else
        begin
          ReadData1 = Registers[RS1];
          ReadData2 = Registers[RS2];
        end
    end
endmodule