data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/MEM.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/MEM.v:91: Signal definition not found, creating implicitly: \'O_TOMEM_WB_EX_isindelayslot\'\n                                                                                                                         : ... Suggested alternative: \'O_TOMEM_WB_isindelayslot\'\n    assign O_TOMEM_WB_EX_isindelayslot = I_FROMEX_MEM_isindelayslot;\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module MEM(

	input wire										rst,
	

	input wire       I_FROMEX_MEM_wreg,
	input wire[4:0]         I_FROMEX_MEM_wd,
	input wire[31:0]	  I_FROMEX_MEM_wdata,
	input wire[31:0]           I_FROMEX_MEM_hi,
	input wire[31:0]           I_FROMEX_MEM_lo,
	input wire                    I_FROMEX_MEM_whilo,

    input wire[7:0]        I_FROMEX_MEM_aloup,
	input wire[31:0]          I_FROMEX_MEM_mem_addr,
	input wire[31:0]          I_FROMEX_MEM_reg2,
	

	input wire[31:0]          I_FROMDATA_RAM_mem_data,








	input wire                   I_FROMEX_MEM_isindelayslot,

	output wire                  O_TOMEM_WB_isindelayslot,

	output reg[4:0]      O_TOMEM_WB_ID_wd,
	output reg           O_TOMEM_WB_ID_wreg,
	output reg[31:0]	 O_TOMEM_WB_ID_wdata,
	output reg[31:0]     O_TOMEM_WB_EX_hi,
	output reg[31:0]     O_TOMEM_WB_EX_lo,
	output reg           O_TOMEM_WB_EX_whilo,



	

	output reg[31:0]          O_TODATA_RAM_mem_addr,
	output wire					O_TODATA_RAM_mem_we,
	output reg[3:0]              O_TODATA_RAM_mem_sel,
	output reg[31:0]          O_TODATA_RAM_mem_data,
	output reg                   O_TODATA_RAM_mem_ce
	
);


	wire[31:0] zero32;
	reg                   mem_we;

	assign O_TODATA_RAM_mem_we = mem_we ;
	assign zero32 = 32'h00000000;
    
    assign O_TOMEM_WB_EX_isindelayslot = I_FROMEX_MEM_isindelayslot;



	
	always @ (*) begin
		if(rst == 1'b0) begin
			O_TOMEM_WB_ID_wd <= 5'b00000;
			O_TOMEM_WB_ID_wreg <= 1'b0;
		  O_TOMEM_WB_ID_wdata <= 32'h00000000;
		  O_TOMEM_WB_EX_hi <= 32'h00000000;
		  O_TOMEM_WB_EX_lo <= 32'h00000000;
		  O_TOMEM_WB_EX_whilo <= 1'b0;		
		  O_TODATA_RAM_mem_addr <= 32'h00000000;
		  mem_we <= 1'b0;
		  O_TODATA_RAM_mem_sel <= 4'b0000;
		  O_TODATA_RAM_mem_data <= 32'h00000000;
		  O_TODATA_RAM_mem_ce <= 1'b0;		


		end else begin
		    O_TOMEM_WB_ID_wd <= I_FROMEX_MEM_wd;
			O_TOMEM_WB_ID_wreg <= I_FROMEX_MEM_wreg;
			O_TOMEM_WB_ID_wdata <= I_FROMEX_MEM_wdata;
			O_TOMEM_WB_EX_hi <= I_FROMEX_MEM_hi;
			O_TOMEM_WB_EX_lo <= I_FROMEX_MEM_lo;
			O_TOMEM_WB_EX_whilo <= I_FROMEX_MEM_whilo;		
			mem_we <= 1'b0;
			O_TODATA_RAM_mem_addr <= 32'h00000000;
			O_TODATA_RAM_mem_sel <= 4'b1111;
			O_TODATA_RAM_mem_ce <= 1'b0;


			case (I_FROMEX_MEM_aloup)
				8'b11100000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[31]}},I_FROMDATA_RAM_mem_data[31:24]};
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[23]}},I_FROMDATA_RAM_mem_data[23:16]};
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[15]}},I_FROMDATA_RAM_mem_data[15:8]};
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[7]}},I_FROMDATA_RAM_mem_data[7:0]};
							O_TODATA_RAM_mem_sel <= 4'b0001;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase
				end
				8'b11100100:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[31:24]};
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[23:16]};
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[15:8]};
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[7:0]};
							O_TODATA_RAM_mem_sel <= 4'b0001;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100001:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{16{I_FROMDATA_RAM_mem_data[31]}},I_FROMDATA_RAM_mem_data[31:16]};
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{16{I_FROMDATA_RAM_mem_data[15]}},I_FROMDATA_RAM_mem_data[15:0]};
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase					
				end
				8'b11100101:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{16{1'b0}},I_FROMDATA_RAM_mem_data[31:16]};
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{16{1'b0}},I_FROMDATA_RAM_mem_data[15:0]};
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100011:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;
					O_TODATA_RAM_mem_sel <= 4'b1111;		
					O_TODATA_RAM_mem_ce <= 1'b1;
				end
				8'b11100010:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_sel <= 4'b1111;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data[31:0];
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[23:0],I_FROMEX_MEM_reg2[7:0]};
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[15:0],I_FROMEX_MEM_reg2[15:0]};
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[7:0],I_FROMEX_MEM_reg2[23:0]};	
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100110:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_sel <= 4'b1111;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:8],I_FROMDATA_RAM_mem_data[31:24]};
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:16],I_FROMDATA_RAM_mem_data[31:16]};
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:24],I_FROMDATA_RAM_mem_data[31:8]};
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;	
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase					
				end
				8'b11110000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;


		  		O_TODATA_RAM_mem_sel <= 4'b1111;			
		  		O_TODATA_RAM_mem_ce <= 1'b1;					
				end				
				8'b11101000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0]};
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b0001;	
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase				
				end
				8'b11101001:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[15:0],I_FROMEX_MEM_reg2[15:0]};
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase						
				end
				8'b11101011:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2;
					O_TODATA_RAM_mem_sel <= 4'b1111;			
					O_TODATA_RAM_mem_ce <= 1'b1;
				end
				8'b11101010:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin						  
							O_TODATA_RAM_mem_sel <= 4'b1111;
							O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2;
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b0111;
							O_TODATA_RAM_mem_data <= {zero32[7:0],I_FROMEX_MEM_reg2[31:8]};
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0011;
							O_TODATA_RAM_mem_data <= {zero32[15:0],I_FROMEX_MEM_reg2[31:16]};
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b0001;	
							O_TODATA_RAM_mem_data <= {zero32[23:0],I_FROMEX_MEM_reg2[31:24]};
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase							
				end
				8'b11101110:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin						  
							O_TODATA_RAM_mem_sel <= 4'b1000;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[7:0],zero32[23:0]};
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b1100;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[15:0],zero32[15:0]};
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b1110;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[23:0],zero32[7:0]};
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b1111;	
							O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2[31:0];
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase											
				end 
				
				default:		begin

				end
			endcase							
		end
	end
			

endmodule
module MEM(

	input wire										rst,
	

	input wire       I_FROMEX_MEM_wreg,
	input wire[4:0]         I_FROMEX_MEM_wd,
	input wire[31:0]	  I_FROMEX_MEM_wdata,
	input wire[31:0]           I_FROMEX_MEM_hi,
	input wire[31:0]           I_FROMEX_MEM_lo,
	input wire                    I_FROMEX_MEM_whilo,

    input wire[7:0]        I_FROMEX_MEM_aloup,
	input wire[31:0]          I_FROMEX_MEM_mem_addr,
	input wire[31:0]          I_FROMEX_MEM_reg2,
	

	input wire[31:0]          I_FROMDATA_RAM_mem_data,








	input wire                   I_FROMEX_MEM_isindelayslot,

	output wire                  O_TOMEM_WB_isindelayslot,

	output reg[4:0]      O_TOMEM_WB_ID_wd,
	output reg           O_TOMEM_WB_ID_wreg,
	output reg[31:0]	 O_TOMEM_WB_ID_wdata,
	output reg[31:0]     O_TOMEM_WB_EX_hi,
	output reg[31:0]     O_TOMEM_WB_EX_lo,
	output reg           O_TOMEM_WB_EX_whilo,



	

	output reg[31:0]          O_TODATA_RAM_mem_addr,
	output wire					O_TODATA_RAM_mem_we,
	output reg[3:0]              O_TODATA_RAM_mem_sel,
	output reg[31:0]          O_TODATA_RAM_mem_data,
	output reg                   O_TODATA_RAM_mem_ce
	
);



	wire[31:0] zero32;
	reg                   mem_we;

	assign O_TODATA_RAM_mem_we = mem_we ;
	assign zero32 = 32'h00000000;
    
    assign O_TOMEM_WB_EX_isindelayslot = I_FROMEX_MEM_isindelayslot;



	
	always @ (*) begin
		if(rst == 1'b0) begin
			O_TOMEM_WB_ID_wd <= 5'b00000;
			O_TOMEM_WB_ID_wreg <= 1'b0;
		  O_TOMEM_WB_ID_wdata <= 32'h00000000;
		  O_TOMEM_WB_EX_hi <= 32'h00000000;
		  O_TOMEM_WB_EX_lo <= 32'h00000000;
		  O_TOMEM_WB_EX_whilo <= 1'b0;		
		  O_TODATA_RAM_mem_addr <= 32'h00000000;
		  mem_we <= 1'b0;
		  O_TODATA_RAM_mem_sel <= 4'b0000;
		  O_TODATA_RAM_mem_data <= 32'h00000000;
		  O_TODATA_RAM_mem_ce <= 1'b0;		


		end else begin
		    O_TOMEM_WB_ID_wd <= I_FROMEX_MEM_wd;
			O_TOMEM_WB_ID_wreg <= I_FROMEX_MEM_wreg;
			O_TOMEM_WB_ID_wdata <= I_FROMEX_MEM_wdata;
			O_TOMEM_WB_EX_hi <= I_FROMEX_MEM_hi;
			O_TOMEM_WB_EX_lo <= I_FROMEX_MEM_lo;
			O_TOMEM_WB_EX_whilo <= I_FROMEX_MEM_whilo;		
			mem_we <= 1'b0;
			O_TODATA_RAM_mem_addr <= 32'h00000000;
			O_TODATA_RAM_mem_sel <= 4'b1111;
			O_TODATA_RAM_mem_ce <= 1'b0;


			case (I_FROMEX_MEM_aloup)
				8'b11100000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[31]}},I_FROMDATA_RAM_mem_data[31:24]};
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[23]}},I_FROMDATA_RAM_mem_data[23:16]};
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[15]}},I_FROMDATA_RAM_mem_data[15:8]};
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {{24{I_FROMDATA_RAM_mem_data[7]}},I_FROMDATA_RAM_mem_data[7:0]};
							O_TODATA_RAM_mem_sel <= 4'b0001;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase
				end
				8'b11100100:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[31:24]};
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[23:16]};
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[15:8]};
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {{24{1'b0}},I_FROMDATA_RAM_mem_data[7:0]};
							O_TODATA_RAM_mem_sel <= 4'b0001;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100001:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{16{I_FROMDATA_RAM_mem_data[31]}},I_FROMDATA_RAM_mem_data[31:16]};
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{16{I_FROMDATA_RAM_mem_data[15]}},I_FROMDATA_RAM_mem_data[15:0]};
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase					
				end
				8'b11100101:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {{16{1'b0}},I_FROMDATA_RAM_mem_data[31:16]};
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {{16{1'b0}},I_FROMDATA_RAM_mem_data[15:0]};
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100011:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;
					O_TODATA_RAM_mem_sel <= 4'b1111;		
					O_TODATA_RAM_mem_ce <= 1'b1;
				end
				8'b11100010:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_sel <= 4'b1111;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data[31:0];
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[23:0],I_FROMEX_MEM_reg2[7:0]};
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[15:0],I_FROMEX_MEM_reg2[15:0]};
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMDATA_RAM_mem_data[7:0],I_FROMEX_MEM_reg2[23:0]};	
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase				
				end
				8'b11100110:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b0;
					O_TODATA_RAM_mem_sel <= 4'b1111;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:8],I_FROMDATA_RAM_mem_data[31:24]};
						end
						2'b01:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:16],I_FROMDATA_RAM_mem_data[31:16]};
						end
						2'b10:	begin
							O_TOMEM_WB_ID_wdata <= {I_FROMEX_MEM_reg2[31:24],I_FROMDATA_RAM_mem_data[31:8]};
						end
						2'b11:	begin
							O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;	
						end
						default:	begin
							O_TOMEM_WB_ID_wdata <= 32'h00000000;
						end
					endcase					
				end
				8'b11110000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b0;
					O_TOMEM_WB_ID_wdata <= I_FROMDATA_RAM_mem_data;


		  		O_TODATA_RAM_mem_sel <= 4'b1111;			
		  		O_TODATA_RAM_mem_ce <= 1'b1;					
				end				
				8'b11101000:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0],I_FROMEX_MEM_reg2[7:0]};
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TODATA_RAM_mem_sel <= 4'b1000;
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b0100;
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0010;
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b0001;	
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase				
				end
				8'b11101001:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[15:0],I_FROMEX_MEM_reg2[15:0]};
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin
							O_TODATA_RAM_mem_sel <= 4'b1100;
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0011;
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase						
				end
				8'b11101011:		begin
					O_TODATA_RAM_mem_addr <= I_FROMEX_MEM_mem_addr;
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2;
					O_TODATA_RAM_mem_sel <= 4'b1111;			
					O_TODATA_RAM_mem_ce <= 1'b1;
				end
				8'b11101010:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin						  
							O_TODATA_RAM_mem_sel <= 4'b1111;
							O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2;
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b0111;
							O_TODATA_RAM_mem_data <= {zero32[7:0],I_FROMEX_MEM_reg2[31:8]};
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b0011;
							O_TODATA_RAM_mem_data <= {zero32[15:0],I_FROMEX_MEM_reg2[31:16]};
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b0001;	
							O_TODATA_RAM_mem_data <= {zero32[23:0],I_FROMEX_MEM_reg2[31:24]};
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase							
				end
				8'b11101110:		begin
					O_TODATA_RAM_mem_addr <= {I_FROMEX_MEM_mem_addr[31:2], 2'b00};
					mem_we <= 1'b1;
					O_TODATA_RAM_mem_ce <= 1'b1;
					case (I_FROMEX_MEM_mem_addr[1:0])
						2'b00:	begin						  
							O_TODATA_RAM_mem_sel <= 4'b1000;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[7:0],zero32[23:0]};
						end
						2'b01:	begin
							O_TODATA_RAM_mem_sel <= 4'b1100;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[15:0],zero32[15:0]};
						end
						2'b10:	begin
							O_TODATA_RAM_mem_sel <= 4'b1110;
							O_TODATA_RAM_mem_data <= {I_FROMEX_MEM_reg2[23:0],zero32[7:0]};
						end
						2'b11:	begin
							O_TODATA_RAM_mem_sel <= 4'b1111;	
							O_TODATA_RAM_mem_data <= I_FROMEX_MEM_reg2[31:0];
						end
						default:	begin
							O_TODATA_RAM_mem_sel <= 4'b0000;
						end
					endcase											
				end 
				
				default:		begin

				end
			endcase							
		end
	end
			

endmodule