data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_buf.sv
data/verilator_xmls/0ca5ceb6-bcef-41f5-8b95-6f4a474ee078.xml
module prim_xilinx_buf #(
  parameter int Width = 1
) (
  input [Width-1:0] in_i,
  (* keep = "true" *) output logic [Width-1:0] out_o
);

  assign out_o = in_i;

endmodule
module prim_xilinx_buf #(
  parameter int Width = 1
) (
  input [Width-1:0] in_i,
  (* keep = "true" *) output logic [Width-1:0] out_o
);


  assign out_o = in_i;

endmodule