data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/07_adder/adder_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_test(t1, t2, t3, p1, p2);

output t1, t2, t3;
input  p1, p2;


reg       t1, t2, t3;

initial begin
   t1 <= 1'b0; t2 <= 1'b0;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b0; t2 <= 1'b0;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b0; t2 <= 1'b1;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b0; t2 <= 1'b1;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b1; t2 <= 1'b0;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b1; t2 <= 1'b0;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b1; t2 <= 1'b1;  t3 <= 1'b0; 
   
   #100;
   t1 <= 1'b1; t2 <= 1'b1;  t3 <= 1'b1;

   #100;
   $finish;
end

endmodule
module adder_test(t1, t2, t3, p1, p2);


output t1, t2, t3;
input  p1, p2;


reg       t1, t2, t3;

initial begin
   t1 <= 1'b0; t2 <= 1'b0;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b0; t2 <= 1'b0;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b0; t2 <= 1'b1;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b0; t2 <= 1'b1;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b1; t2 <= 1'b0;  t3 <= 1'b0; 

   #100;
   t1 <= 1'b1; t2 <= 1'b0;  t3 <= 1'b1; 

   #100;
   t1 <= 1'b1; t2 <= 1'b1;  t3 <= 1'b0; 
   
   #100;
   t1 <= 1'b1; t2 <= 1'b1;  t3 <= 1'b1;

   #100;
   $finish;
end

endmodule