data/full_repos/permissive/433621701/generic_CB_array/generic_CB_array.v
data/verilator_xmls/fd06e278-bb93-4e8c-8afc-57a7fd90af91.xml
module mux(input a, b, select, output reg out);
    always @(a or b or select)
    begin
        out = (a&~select)|(b&select);
    end
endmodule
module mux(input a, b, select, output reg out);

    always @(a or b or select)
    begin
        out = (a&~select)|(b&select);
    end
endmodule