data/full_repos/permissive/433367655/Source/microarchitecture.v
1: b'%Error: data/full_repos/permissive/433367655/Source/microarchitecture.v:3: Cannot find include file: instruction_memory.v\n`include "instruction_memory.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/instruction_memory.v\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/instruction_memory.v.v\n             data/full_repos/permissive/433367655/Source,data/full_repos/permissive/433367655/instruction_memory.v.sv\n             instruction_memory.v\n             instruction_memory.v.v\n             instruction_memory.v.sv\n             obj_dir/instruction_memory.v\n             obj_dir/instruction_memory.v.v\n             obj_dir/instruction_memory.v.sv\n%Error: data/full_repos/permissive/433367655/Source/microarchitecture.v:4: Cannot find include file: ALU_RISCV.v\n`include "ALU_RISCV.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433367655/Source/microarchitecture.v:5: Cannot find include file: RF.v\n`include "RF.v" \n         ^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module microarchitecture(
    input clk,
    input rst,
    input [31:0] sw,

    output [31:0] out
);

    wire [31:0] instr;


    wire we3; 
    assign we3 = instr[29] | instr [28]; 
    
    wire [31:0] rd1;
    wire [31:0] rd2;
    reg [31:0] wd3;
    
    reg [7:0] pc;
    
    wire [31:0] aluResult;
    wire flag;

    assign out = aluResult[31:0];
   
    wire [1:0] pcOp;
    assign pcOp = ((flag & instr[30])) | instr[31];
    reg [7:0] pcInput;
    

    always @ (*) begin
        case(pcOp)
            2'b0: begin pcInput = 8'h1; end
            2'b1: begin pcInput = instr[12:5]; end
        endcase    
    end
    

    always @ (posedge clk or posedge rst) begin
        if (rst) begin
            pc <= 0;
        end
        else begin
            pc <= pc + pcInput;
        end
    end
    

    instruction_memory IM (pc, instr);
    RF finalRF(clk, we3, instr[22:18], instr[17:13], instr[4:0], wd3, rst, rd1, rd2);
    Alu_riscv ALU(rd1, rd2, instr[27:23], flag, aluResult);
    

    wire [1:0] wdOp = instr[29:28];
    wire [31:0] seConst = {{9{instr[27]}}, instr[27:5]};
    

    always @ (*) begin
        case(wdOp)
            2'd1: begin assign wd3 = sw; end
            2'd3: begin assign wd3 = aluResult; end
            2'd2: begin assign wd3 = seConst; end
        endcase
    end
    
endmodule
module microarchitecture(
    input clk,
    input rst,
    input [31:0] sw,

    output [31:0] out
);


    wire [31:0] instr;


    wire we3; 
    assign we3 = instr[29] | instr [28]; 
    
    wire [31:0] rd1;
    wire [31:0] rd2;
    reg [31:0] wd3;
    
    reg [7:0] pc;
    
    wire [31:0] aluResult;
    wire flag;

    assign out = aluResult[31:0];
   
    wire [1:0] pcOp;
    assign pcOp = ((flag & instr[30])) | instr[31];
    reg [7:0] pcInput;
    

    always @ (*) begin
        case(pcOp)
            2'b0: begin pcInput = 8'h1; end
            2'b1: begin pcInput = instr[12:5]; end
        endcase    
    end
    

    always @ (posedge clk or posedge rst) begin
        if (rst) begin
            pc <= 0;
        end
        else begin
            pc <= pc + pcInput;
        end
    end
    

    instruction_memory IM (pc, instr);
    RF finalRF(clk, we3, instr[22:18], instr[17:13], instr[4:0], wd3, rst, rd1, rd2);
    Alu_riscv ALU(rd1, rd2, instr[27:23], flag, aluResult);
    

    wire [1:0] wdOp = instr[29:28];
    wire [31:0] seConst = {{9{instr[27]}}, instr[27:5]};
    

    always @ (*) begin
        case(wdOp)
            2'd1: begin assign wd3 = sw; end
            2'd3: begin assign wd3 = aluResult; end
            2'd2: begin assign wd3 = seConst; end
        endcase
    end
    
endmodule