data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem.v
1: b"%Error: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem.v:39: Cannot find file containing module: 'tcm_mem_ram'\ntcm_mem_ram\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/tcm_mem_ram\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/tcm_mem_ram.v\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/tcm_mem_ram.sv\n             tcm_mem_ram\n             tcm_mem_ram.v\n             tcm_mem_ram.sv\n             obj_dir/tcm_mem_ram\n             obj_dir/tcm_mem_ram.v\n             obj_dir/tcm_mem_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module tcm_mem
(

     input           clk
    ,input           rst_n
    ,input           mem_i_rd_i
    ,input           mem_i_flush_i
    ,input           mem_i_invalidate_i
    ,input  [ 31:0]  mem_i_pc_i
    ,input  [ 31:0]  mem_d_addr_i
    ,input  [ 31:0]  mem_d_data_wr_i
    ,input           mem_d_rd_i
    ,input  [  3:0]  mem_d_wr_i
    ,input           mem_d_cacheable_i
    ,input  [ 10:0]  mem_d_req_tag_i
    ,input           mem_d_invalidate_i
    ,input           mem_d_writeback_i
    ,input           mem_d_flush_i


    ,output          mem_i_accept_o
    ,output          mem_i_valid_o
    ,output          mem_i_error_o
    ,output [ 63:0]  mem_i_inst_o
    ,output [ 31:0]  mem_d_data_rd_o
    ,output          mem_d_accept_o
    ,output          mem_d_ack_o
    ,output          mem_d_error_o
    ,output [ 10:0]  mem_d_resp_tag_o
);




wire        muxed_hi_w   = mem_d_addr_i[2];
wire [63:0] data_r_w;

tcm_mem_ram
u_ram
(

     .clk(clk)
    ,.rst_n(rst_n)
    ,.addr0_i(mem_i_pc_i[16:3])
    ,.data0_i(64'b0)
    ,.wr0_i(8'b0)


    ,.addr1_i(mem_d_addr_i[16:3])
    ,.data1_i(muxed_hi_w ? {mem_d_data_wr_i, 32'b0} : {32'b0, mem_d_data_wr_i})
    ,.wr1_i(muxed_hi_w ? {mem_d_wr_i, 4'b0} : {4'b0, mem_d_wr_i})


    ,.data0_o(mem_i_inst_o)
    ,.data1_o(data_r_w)
);

reg muxed_hi_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        muxed_hi_q <= 1'b0;
    end

    else begin
        muxed_hi_q <= muxed_hi_w;
    end
end




reg        mem_i_valid_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        mem_i_valid_q <= 1'b0;
    end

    else begin
        mem_i_valid_q <= mem_i_rd_i;
    end
end

assign mem_i_accept_o  = 1'b1;
assign mem_i_valid_o   = mem_i_valid_q;
assign mem_i_error_o   = 1'b0;




reg        mem_d_accept_q;
reg        mem_d_ack_q;
reg [10:0] mem_d_tag_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        mem_d_ack_q    <= 1'b0;
        mem_d_tag_q    <= 11'b0;
    end

    else if ((mem_d_rd_i || mem_d_wr_i != 4'b0 || mem_d_flush_i || mem_d_invalidate_i || mem_d_writeback_i) && mem_d_accept_o) begin
        mem_d_ack_q    <= 1'b1;
        mem_d_tag_q    <= mem_d_req_tag_i;
    end

    else begin
        mem_d_ack_q    <= 1'b0;
    end
end

assign mem_d_ack_o          = mem_d_ack_q;
assign mem_d_resp_tag_o     = mem_d_tag_q;
assign mem_d_data_rd_o      = muxed_hi_q ? data_r_w[63:32] : data_r_w[31:0];
assign mem_d_error_o        = 1'b0;

assign mem_d_accept_o       = 1'b1;

endmodule
module tcm_mem
(

     input           clk
    ,input           rst_n
    ,input           mem_i_rd_i
    ,input           mem_i_flush_i
    ,input           mem_i_invalidate_i
    ,input  [ 31:0]  mem_i_pc_i
    ,input  [ 31:0]  mem_d_addr_i
    ,input  [ 31:0]  mem_d_data_wr_i
    ,input           mem_d_rd_i
    ,input  [  3:0]  mem_d_wr_i
    ,input           mem_d_cacheable_i
    ,input  [ 10:0]  mem_d_req_tag_i
    ,input           mem_d_invalidate_i
    ,input           mem_d_writeback_i
    ,input           mem_d_flush_i


    ,output          mem_i_accept_o
    ,output          mem_i_valid_o
    ,output          mem_i_error_o
    ,output [ 63:0]  mem_i_inst_o
    ,output [ 31:0]  mem_d_data_rd_o
    ,output          mem_d_accept_o
    ,output          mem_d_ack_o
    ,output          mem_d_error_o
    ,output [ 10:0]  mem_d_resp_tag_o
);





wire        muxed_hi_w   = mem_d_addr_i[2];
wire [63:0] data_r_w;

tcm_mem_ram
u_ram
(

     .clk(clk)
    ,.rst_n(rst_n)
    ,.addr0_i(mem_i_pc_i[16:3])
    ,.data0_i(64'b0)
    ,.wr0_i(8'b0)


    ,.addr1_i(mem_d_addr_i[16:3])
    ,.data1_i(muxed_hi_w ? {mem_d_data_wr_i, 32'b0} : {32'b0, mem_d_data_wr_i})
    ,.wr1_i(muxed_hi_w ? {mem_d_wr_i, 4'b0} : {4'b0, mem_d_wr_i})


    ,.data0_o(mem_i_inst_o)
    ,.data1_o(data_r_w)
);

reg muxed_hi_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        muxed_hi_q <= 1'b0;
    end

    else begin
        muxed_hi_q <= muxed_hi_w;
    end
end




reg        mem_i_valid_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        mem_i_valid_q <= 1'b0;
    end

    else begin
        mem_i_valid_q <= mem_i_rd_i;
    end
end

assign mem_i_accept_o  = 1'b1;
assign mem_i_valid_o   = mem_i_valid_q;
assign mem_i_error_o   = 1'b0;




reg        mem_d_accept_q;
reg        mem_d_ack_q;
reg [10:0] mem_d_tag_q;


always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        mem_d_ack_q    <= 1'b0;
        mem_d_tag_q    <= 11'b0;
    end

    else if ((mem_d_rd_i || mem_d_wr_i != 4'b0 || mem_d_flush_i || mem_d_invalidate_i || mem_d_writeback_i) && mem_d_accept_o) begin
        mem_d_ack_q    <= 1'b1;
        mem_d_tag_q    <= mem_d_req_tag_i;
    end

    else begin
        mem_d_ack_q    <= 1'b0;
    end
end

assign mem_d_ack_o          = mem_d_ack_q;
assign mem_d_resp_tag_o     = mem_d_tag_q;
assign mem_d_data_rd_o      = muxed_hi_q ? data_r_w[63:32] : data_r_w[31:0];
assign mem_d_error_o        = 1'b0;

assign mem_d_accept_o       = 1'b1;

endmodule