data/full_repos/permissive/497530416/pipe/control_logic.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/control_logic.v:49: syntax error, unexpected always\nalways @(*)\n^~~~~~\n%Error: Cannot continue\n'
module control_logic_pipe(D_icode, d_rA, d_rB, E_icode, E_dstM, e_cnd, M_icode,
F_bubble, F_stall, D_bubble, D_stall, E_bubble, E_stall);

input e_cnd;
input [3:0] D_icode, d_rA, d_rB, E_icode, E_dstM, M_icode;

output F_bubble, F_stall, D_bubble, D_stall, E_bubble, E_stall;









always @(*)
    begin
        if( (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB)
            || (D_icode==9 || E_icode==9 || M_icode==9) )
        begin
            F_stall = 1;
        end
        else
        begin
            F_stall = 0;
        end
    end


always @(*)
begin
    F_bubble = 0;
end


always @(*)
    begin
        if( (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB) )
        begin
            D_stall = 1;
        end
        else
        begin
            D_stall = 0;
        end


always @(*)
    begin
        if( (E_icode==7 && !e_cnd) || (D_icode==9 || E_icode==9 || M_icode==9) )
        begin
            D_bubble = 1;
        end
        else
        begin
            D_bubble = 0;
        end


always @(*)
    begin
        E_stall = 0;
    end


always @(*)
    begin
        if( (E_icode==7 && !e_cnd) || (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB) )
        begin
            E_bubble = 1;
        end
        else
        begin
            E_bubble = 0;
        end


endmodule
module control_logic_pipe(D_icode, d_rA, d_rB, E_icode, E_dstM, e_cnd, M_icode,
F_bubble, F_stall, D_bubble, D_stall, E_bubble, E_stall);


input e_cnd;
input [3:0] D_icode, d_rA, d_rB, E_icode, E_dstM, M_icode;

output F_bubble, F_stall, D_bubble, D_stall, E_bubble, E_stall;









always @(*)
    begin
        if( (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB)
            || (D_icode==9 || E_icode==9 || M_icode==9) )
        begin
            F_stall = 1;
        end
        else
        begin
            F_stall = 0;
        end
    end


always @(*)
begin
    F_bubble = 0;
end


always @(*)
    begin
        if( (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB) )
        begin
            D_stall = 1;
        end
        else
        begin
            D_stall = 0;
        end


always @(*)
    begin
        if( (E_icode==7 && !e_cnd) || (D_icode==9 || E_icode==9 || M_icode==9) )
        begin
            D_bubble = 1;
        end
        else
        begin
            D_bubble = 0;
        end


always @(*)
    begin
        E_stall = 0;
    end


always @(*)
    begin
        if( (E_icode==7 && !e_cnd) || (E_icode==5 || E_icode==11) && (E_dstM==d_rA || E_dstM==d_rB) )
        begin
            E_bubble = 1;
        end
        else
        begin
            E_bubble = 0;
        end


endmodule