data/full_repos/permissive/434840709/lab2/add32_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/add32_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    always #100 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/add32_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #150;\n        ^\n%Warning-MULTITOP: data/full_repos/permissive/434840709/lab2/add32_tb.v:32: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                          : ... Top module \'add32_tb\'\nmodule add32_tb();\n       ^~~~~~~~\n                                                                          : ... Top module \'add1\'\nmodule add1(\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab2/add32_tb.v:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bxxxx\' generates 4 bits.\n                                                                       : ... In instance add32_tb\n        a = 4\'bxxxx;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab2/add32_tb.v:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bxxxx\' generates 4 bits.\n                                                                       : ... In instance add32_tb\n        b = 4\'bxxxx;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/434840709/lab2/add32_tb.v:20: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                       : ... In instance add32_tb\n        cin={$random}%2;\n           ^\n%Error: data/full_repos/permissive/434840709/lab2/add32_tb.v:25: Cannot find file containing module: \'csadd32\'\n    csadd32 A(a,b,cin,s0,cout0);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab2,data/full_repos/permissive/434840709/csadd32\n             data/full_repos/permissive/434840709/lab2,data/full_repos/permissive/434840709/csadd32.v\n             data/full_repos/permissive/434840709/lab2,data/full_repos/permissive/434840709/csadd32.sv\n             csadd32\n             csadd32.v\n             csadd32.sv\n             obj_dir/csadd32\n             obj_dir/csadd32.v\n             obj_dir/csadd32.sv\n%Error: data/full_repos/permissive/434840709/lab2/add32_tb.v:26: Cannot find file containing module: \'rcadd32\'\n    rcadd32 B(a,b,cin,s1,cout1);\n    ^~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add32_tb();
    reg [31:0]a;
    reg [31:0]b;
    reg cin;
    reg clk;
    wire [31:0]s0,s1,s2;
    wire cout0,cout1,cout2;
    initial begin
        a = 4'bxxxx;
        b = 4'bxxxx;
        cin = 1'bx;
        clk = 0;
    end
    always #100 clk = ~clk;
    always@(posedge clk)begin
        a={$random}%2**30;
        b={$random}%2**30;
        cin={$random}%2;
        #150;
        cin=1'bx;
    end

    csadd32 A(a,b,cin,s0,cout0);
    rcadd32 B(a,b,cin,s1,cout1);

endmodule
module add32_tb();

    reg [31:0]a;
    reg [31:0]b;
    reg cin;
    reg clk;
    wire [31:0]s0,s1,s2;
    wire cout0,cout1,cout2;
    initial begin
        a = 4'bxxxx;
        b = 4'bxxxx;
        cin = 1'bx;
        clk = 0;
    end
    always #100 clk = ~clk;
    always@(posedge clk)begin
        a={$random}%2**30;
        b={$random}%2**30;
        cin={$random}%2;
        #150;
        cin=1'bx;
    end

    csadd32 A(a,b,cin,s0,cout0);
    rcadd32 B(a,b,cin,s1,cout1);

endmodule