data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v:73: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v:80: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/WREG_tb.v:84: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module WREG_tb();



parameter tb_data_width = 8;
parameter tb_clk_period=20;



reg tb_clk;
reg tb_reset;
reg tb_set;
reg [tb_data_width-1:0] tb_input_data;


wire [tb_data_width-1:0] tb_output_data;



WREG #(.WREG_DATA_WIDTH(tb_data_width)) Wreg(


.WREG_Clk(tb_clk),
.WREG_Reset(tb_reset),
.WREG_Set(tb_set),
.WREG_Input_Data(tb_input_data),

.WREG_Output_Data(tb_output_data)


);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin
	
	tb_reset<=0;
	tb_set<=0;
	tb_input_data<=0;
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_reset<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_set<=1;
	tb_input_data<=4;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_set<=0;
	tb_input_data<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	$stop;

end

endmodule
module WREG_tb();




parameter tb_data_width = 8;
parameter tb_clk_period=20;



reg tb_clk;
reg tb_reset;
reg tb_set;
reg [tb_data_width-1:0] tb_input_data;


wire [tb_data_width-1:0] tb_output_data;



WREG #(.WREG_DATA_WIDTH(tb_data_width)) Wreg(


.WREG_Clk(tb_clk),
.WREG_Reset(tb_reset),
.WREG_Set(tb_set),
.WREG_Input_Data(tb_input_data),

.WREG_Output_Data(tb_output_data)


);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin
	
	tb_reset<=0;
	tb_set<=0;
	tb_input_data<=0;
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_reset<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_set<=1;
	tb_input_data<=4;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_set<=0;
	tb_input_data<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	$stop;

end

endmodule