data/full_repos/permissive/461069000/pwm/src/counter_top.v
1: b'%Error: data/full_repos/permissive/461069000/pwm/src/counter_top.v:13: Unsupported or unknown PLI call: $from_myhdl\n $from_myhdl(clk, reset);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/counter_top.v:14: Unsupported or unknown PLI call: $to_myhdl\n $to_myhdl(out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/counter_top.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("counter_top.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/counter_top.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_top;

reg clk = 0;
reg reset = 0;

wire [7:0] out;

counter dut (.clk(clk), .reset(reset), .out(out));

initial begin
	$from_myhdl(clk, reset);
	$to_myhdl(out);
end

initial begin
    $dumpfile("counter_top.vcd");
    $dumpvars();
end

endmodule
module counter_top;


reg clk = 0;
reg reset = 0;

wire [7:0] out;

counter dut (.clk(clk), .reset(reset), .out(out));

initial begin
	$from_myhdl(clk, reset);
	$to_myhdl(out);
end

initial begin
    $dumpfile("counter_top.vcd");
    $dumpvars();
end

endmodule