data/full_repos/permissive/51625123/src/scores2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/51625123/src/scores2.v:166: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'scores\'\nmodule scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);\n       ^~~~~~\n                                                                        : ... Top module \'mux2x4\'\nmodule mux2x4(sel, d0, d1, d2, d3, q);\n       ^~~~~~\n                                                                        : ... Top module \'counter_mod8\'\nmodule counter_mod8(c, r, q, cout);\n       ^~~~~~~~~~~~\n                                                                        : ... Top module \'counter_mod4\'\nmodule counter_mod4(c, r, q, cout);\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/51625123/src/scores2.v:113: Cannot find file containing module: \'scorecopymux\'\nscorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux.v\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux.sv\n             scorecopymux\n             scorecopymux.v\n             scorecopymux.sv\n             obj_dir/scorecopymux\n             obj_dir/scorecopymux.v\n             obj_dir/scorecopymux.sv\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/scores2.v:172: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h1\' generates 2 bits.\n                                                                     : ... In instance mux2x4\n       2\'b01 ? d1 :\n             ^\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/scores2.v:173: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h2\' generates 2 bits.\n                                                                     : ... In instance mux2x4\n       2\'b10 ? d2 : d3;\n             ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module charrom(clk, char, line, q);
	input clk;
	input [3:0] char;
	input [2:0] line;

	output reg[3:0] q;
	always @(char or pixels0 or pixels1 or pixels2 or pixels3 or pixels4 or pixels5 or pixels6 or pixels7 or pixels8 or pixels9)
		case (char)
			4'd0 : q <= pixels0;
			4'd1 : q <= pixels1;
			4'd2 : q <= pixels2;
			4'd3 : q <= pixels3;
			4'd4 : q <= pixels4;
			4'd5 : q <= pixels5;
			4'd6 : q <= pixels6;
			4'd7 : q <= pixels7;
			4'd8 : q <= pixels8;
			4'd9 : q <= pixels9;
			default:
				q <= 0;
		endcase

	wire [3:0] pixels0;
	digit #(
		4'b1110,
		4'b1010,
		4'b1010,
		4'b1010,
		4'b1110
				) dzigit0(line, pixels0);
	wire [3:0] pixels1;
	digit #(
		4'b1100,
		4'b0100,
		4'b0100,
		4'b0100,
		4'b1110
				) dzigit1(line, pixels1);
	wire [3:0] pixels2;
	digit #(
		4'b1110,
		4'b0010,
		4'b1110,
		4'b1000,
		4'b1110
				) dzigit2(line, pixels2);
	wire [3:0] pixels3;
	digit #(
		4'b1110,
		4'b0010,
		4'b0110,
		4'b0010,
		4'b1110
				) dzigit3(line, pixels3);
	wire [3:0] pixels4;
	digit #(
		4'b1010,
		4'b1010,
		4'b1110,
		4'b0010,
		4'b0010
				) dzigit4(line, pixels4);
	wire [3:0] pixels5;
	digit #(
		4'b1110,
		4'b1000,
		4'b1110,
		4'b0010,
		4'b1110
				) dzigit5(line, pixels5);
	wire [3:0] pixels6;
	digit #(
		4'b1110,
		4'b1000,
		4'b1110,
		4'b1010,
		4'b1110
				) dzigit6(line, pixels6);
	wire [3:0] pixels7;
	digit #(
		4'b1110,
		4'b0010,
		4'b0010,
		4'b0010,
		4'b0010
				) dzigit7(line, pixels7);
	wire [3:0] pixels8;
	digit #(
		4'b1110,
		4'b1010,
		4'b1110,
		4'b1010,
		4'b1110
				) dzigit8(line, pixels8);
	wire [3:0] pixels9;
	digit #(
		4'b1110,
		4'b1010,
		4'b1110,
		4'b0010,
		4'b1110
				) dzigit9(line, pixels9);
endmodule
module charrom(clk, char, line, q);

	input clk;
	input [3:0] char;
	input [2:0] line;

	output reg[3:0] q;
	always @(char or pixels0 or pixels1 or pixels2 or pixels3 or pixels4 or pixels5 or pixels6 or pixels7 or pixels8 or pixels9)
		case (char)
			4'd0 : q <= pixels0;
			4'd1 : q <= pixels1;
			4'd2 : q <= pixels2;
			4'd3 : q <= pixels3;
			4'd4 : q <= pixels4;
			4'd5 : q <= pixels5;
			4'd6 : q <= pixels6;
			4'd7 : q <= pixels7;
			4'd8 : q <= pixels8;
			4'd9 : q <= pixels9;
			default:
				q <= 0;
		endcase

	wire [3:0] pixels0;
	digit #(
		4'b1110,
		4'b1010,
		4'b1010,
		4'b1010,
		4'b1110
				) dzigit0(line, pixels0);
	wire [3:0] pixels1;
	digit #(
		4'b1100,
		4'b0100,
		4'b0100,
		4'b0100,
		4'b1110
				) dzigit1(line, pixels1);
	wire [3:0] pixels2;
	digit #(
		4'b1110,
		4'b0010,
		4'b1110,
		4'b1000,
		4'b1110
				) dzigit2(line, pixels2);
	wire [3:0] pixels3;
	digit #(
		4'b1110,
		4'b0010,
		4'b0110,
		4'b0010,
		4'b1110
				) dzigit3(line, pixels3);
	wire [3:0] pixels4;
	digit #(
		4'b1010,
		4'b1010,
		4'b1110,
		4'b0010,
		4'b0010
				) dzigit4(line, pixels4);
	wire [3:0] pixels5;
	digit #(
		4'b1110,
		4'b1000,
		4'b1110,
		4'b0010,
		4'b1110
				) dzigit5(line, pixels5);
	wire [3:0] pixels6;
	digit #(
		4'b1110,
		4'b1000,
		4'b1110,
		4'b1010,
		4'b1110
				) dzigit6(line, pixels6);
	wire [3:0] pixels7;
	digit #(
		4'b1110,
		4'b0010,
		4'b0010,
		4'b0010,
		4'b0010
				) dzigit7(line, pixels7);
	wire [3:0] pixels8;
	digit #(
		4'b1110,
		4'b1010,
		4'b1110,
		4'b1010,
		4'b1110
				) dzigit8(line, pixels8);
	wire [3:0] pixels9;
	digit #(
		4'b1110,
		4'b1010,
		4'b1110,
		4'b0010,
		4'b1110
				) dzigit9(line, pixels9);
endmodule