data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv
1: b'%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:2: Cannot find include file: riscv_pkg.sv\n`include "riscv_pkg.sv" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_uvm,data/full_repos/permissive/435890256/riscv_pkg.sv\n             data/full_repos/permissive/435890256/riscv_uvm,data/full_repos/permissive/435890256/riscv_pkg.sv.v\n             data/full_repos/permissive/435890256/riscv_uvm,data/full_repos/permissive/435890256/riscv_pkg.sv.sv\n             riscv_pkg.sv\n             riscv_pkg.sv.v\n             riscv_pkg.sv.sv\n             obj_dir/riscv_pkg.sv\n             obj_dir/riscv_pkg.sv.v\n             obj_dir/riscv_pkg.sv.sv\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:3: Cannot find include file: riscv_pipeline.sv\n`include "riscv_pipeline.sv" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:4: Cannot find include file: control_if.sv\n`include "control_if.sv" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:7: Cannot find include file: dualport_bus.sv\n`include "dualport_bus.sv" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:12: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n        ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:31: syntax error, unexpected \'#\'\n  uvm_resource_db#(virtual control_if)::set\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:58: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:60: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:69: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n      mem_vif.rd_data = $random(int\'(mem_vif.rd_addr));\n                        ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_tb_top.sv:69: ../V3Ast.cpp:358: Null item passed to setOp1p\n      mem_vif.rd_data = $random(int\'(mem_vif.rd_addr));\n                      ^\n'
module riscv_tb_top;
	import uvm_pkg::*;


	control_if ctrl_vif();
  dualport_bus instr_vif();
  dualport_bus mem_vif();


  riscv_pipeline DUT(
    .clk(ctrl_vif.clk),
    .rst_n(ctrl_vif.rst_n),
    .i_boot_addr(ctrl_vif.i_boot_addr),
    .instr_master(instr_vif.master),
    .mem_master(mem_vif.master)
  );

	initial begin


		uvm_resource_db#(virtual control_if)::set
			(.scope("ifs"), .name("control_if"), .val(ctrl_vif));
    uvm_resource_db#(virtual dualport_bus)::set
			(.scope("ifs"), .name("dualport_bus_instr"), .val(instr_vif));
    uvm_resource_db#(virtual dualport_bus)::set
			(.scope("ifs"), .name("dualport_bus_mem"), .val(mem_vif));


		run_test();
	end



  initial begin
    ctrl_vif.clk <= 1'b1;
    ctrl_vif.i_boot_addr <= 32'h0000_0000;
    ctrl_vif.rst_n <= 1'b1;
    instr_vif.rd_data <= 32'h0000_0000;
  end

  assign instr_vif.rd_gnt = instr_vif.rd_req;
  assign instr_vif.wr_gnt = instr_vif.wr_req;
  assign mem_vif.rd_gnt = mem_vif.rd_req;
  assign mem_vif.wr_gnt = mem_vif.wr_req;


  initial begin
    #10;
    ctrl_vif.rst_n = 1'b0;
    #10;
    ctrl_vif.rst_n = 1'b1;
  end

  always_ff @ (mem_vif.rd_addr or negedge ctrl_vif.rst_n) begin
    if (!ctrl_vif.rst_n) begin
      mem_vif.rd_data = 0;
    end else begin

      mem_vif.rd_data = $random(int'(mem_vif.rd_addr));
    end
  end


	always
		#5 ctrl_vif.clk = ~ctrl_vif.clk;
endmodule
module riscv_tb_top;

	import uvm_pkg::*;


	control_if ctrl_vif();
  dualport_bus instr_vif();
  dualport_bus mem_vif();


  riscv_pipeline DUT(
    .clk(ctrl_vif.clk),
    .rst_n(ctrl_vif.rst_n),
    .i_boot_addr(ctrl_vif.i_boot_addr),
    .instr_master(instr_vif.master),
    .mem_master(mem_vif.master)
  );

	initial begin


		uvm_resource_db#(virtual control_if)::set
			(.scope("ifs"), .name("control_if"), .val(ctrl_vif));
    uvm_resource_db#(virtual dualport_bus)::set
			(.scope("ifs"), .name("dualport_bus_instr"), .val(instr_vif));
    uvm_resource_db#(virtual dualport_bus)::set
			(.scope("ifs"), .name("dualport_bus_mem"), .val(mem_vif));


		run_test();
	end



  initial begin
    ctrl_vif.clk <= 1'b1;
    ctrl_vif.i_boot_addr <= 32'h0000_0000;
    ctrl_vif.rst_n <= 1'b1;
    instr_vif.rd_data <= 32'h0000_0000;
  end

  assign instr_vif.rd_gnt = instr_vif.rd_req;
  assign instr_vif.wr_gnt = instr_vif.wr_req;
  assign mem_vif.rd_gnt = mem_vif.rd_req;
  assign mem_vif.wr_gnt = mem_vif.wr_req;


  initial begin
    #10;
    ctrl_vif.rst_n = 1'b0;
    #10;
    ctrl_vif.rst_n = 1'b1;
  end

  always_ff @ (mem_vif.rd_addr or negedge ctrl_vif.rst_n) begin
    if (!ctrl_vif.rst_n) begin
      mem_vif.rd_data = 0;
    end else begin

      mem_vif.rd_data = $random(int'(mem_vif.rd_addr));
    end
  end


	always
		#5 ctrl_vif.clk = ~ctrl_vif.clk;
endmodule