data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:43: Cannot find file containing module: 'bw_u1_muxi21_2x'\nbw_u1_muxi21_2x bs_mux (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x.sv\n             bw_u1_muxi21_2x\n             bw_u1_muxi21_2x.v\n             bw_u1_muxi21_2x.sv\n             obj_dir/bw_u1_muxi21_2x\n             obj_dir/bw_u1_muxi21_2x.v\n             obj_dir/bw_u1_muxi21_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:48: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x hiz_inv (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:51: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x se_inv (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:54: Cannot find file containing module: 'bw_u1_nand3_1x'\nbw_u1_nand3_1x hiz_nand (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:59: Cannot find file containing module: 'bw_u1_inv_2x'\nbw_u1_inv_2x ctl_inv2x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:62: Cannot find file containing module: 'bw_io_jp_bs_baseblk'\nbw_io_jp_bs_baseblk bs_baseblk (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:70: Cannot find file containing module: 'bw_u1_inv_5x'\nbw_u1_inv_5x out_inv5x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_odt_oebscan.v:73: Cannot find file containing module: 'bw_u1_nor2_1x'\nbw_u1_nor2_1x ctl_nor1x (\n^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module bw_io_jp_sstl_odt_oebscan(test_mode_oe ,bsr_hiz_l ,in ,update_dr
      ,mode_ctl ,shift_dr ,clock_dr ,bsr_so ,out ,bsr_si );
output		bsr_so ;
output		out ;
input		test_mode_oe ;
input		bsr_hiz_l ;
input		in ;
input		update_dr ;
input		mode_ctl ;
input		shift_dr ;
input		clock_dr ;
input		bsr_si ;
 
wire		net021 ;
wire		upd_hiz ;
wire		net037 ;
wire		net039 ;
wire		net046 ;
wire		net047 ;
wire		net54 ;
 
 
bw_u1_muxi21_2x bs_mux (
     .z               (net54 ),
     .d0              (in ),
     .d1              (upd_hiz ),
     .s               (net021 ) );
bw_u1_inv_1x hiz_inv (
     .z               (upd_hiz ),
     .a               (net037 ) );
bw_u1_inv_1x se_inv (
     .z               (net039 ),
     .a               (test_mode_oe ) );
bw_u1_nand3_1x hiz_nand (
     .z               (net037 ),
     .a               (net046 ),
     .b               (bsr_hiz_l ),
     .c               (net039 ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net021 ),
     .a               (net047 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (net046 ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net54 ) );
bw_u1_nor2_1x ctl_nor1x (
     .z               (net047 ),
     .a               (mode_ctl ),
     .b               (test_mode_oe ) );
endmodule
module bw_io_jp_sstl_odt_oebscan(test_mode_oe ,bsr_hiz_l ,in ,update_dr
      ,mode_ctl ,shift_dr ,clock_dr ,bsr_so ,out ,bsr_si );

output		bsr_so ;
output		out ;
input		test_mode_oe ;
input		bsr_hiz_l ;
input		in ;
input		update_dr ;
input		mode_ctl ;
input		shift_dr ;
input		clock_dr ;
input		bsr_si ;
 
wire		net021 ;
wire		upd_hiz ;
wire		net037 ;
wire		net039 ;
wire		net046 ;
wire		net047 ;
wire		net54 ;
 
 
bw_u1_muxi21_2x bs_mux (
     .z               (net54 ),
     .d0              (in ),
     .d1              (upd_hiz ),
     .s               (net021 ) );
bw_u1_inv_1x hiz_inv (
     .z               (upd_hiz ),
     .a               (net037 ) );
bw_u1_inv_1x se_inv (
     .z               (net039 ),
     .a               (test_mode_oe ) );
bw_u1_nand3_1x hiz_nand (
     .z               (net037 ),
     .a               (net046 ),
     .b               (bsr_hiz_l ),
     .c               (net039 ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net021 ),
     .a               (net047 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (net046 ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net54 ) );
bw_u1_nor2_1x ctl_nor1x (
     .z               (net047 ),
     .a               (mode_ctl ),
     .b               (test_mode_oe ) );
endmodule