data/full_repos/permissive/505918157/instruction_decoder.v
1: b'%Error: data/full_repos/permissive/505918157/instruction_decoder.v:21: Cannot find include file: INSTRUCTIONS.v\n`include "INSTRUCTIONS.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v.v\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v.sv\n             INSTRUCTIONS.v\n             INSTRUCTIONS.v.v\n             INSTRUCTIONS.v.sv\n             obj_dir/INSTRUCTIONS.v\n             obj_dir/INSTRUCTIONS.v.v\n             obj_dir/INSTRUCTIONS.v.sv\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:50: Define or directive not defined: \'`OP_range\'\n    assign R = (instruction[`OP_range] == `R_OP);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign R = (instruction[`OP_range] == `R_OP);\n                                     ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:50: Define or directive not defined: \'`R_OP\'\n    assign R = (instruction[`OP_range] == `R_OP);\n                                          ^~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:51: Define or directive not defined: \'`OP_range\'\n    assign I = (instruction[`OP_range] == `I_OP);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign I = (instruction[`OP_range] == `I_OP);\n                                     ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:51: Define or directive not defined: \'`I_OP\'\n    assign I = (instruction[`OP_range] == `I_OP);\n                                          ^~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:52: Define or directive not defined: \'`OP_range\'\n    assign S = (instruction[`OP_range] == `S_OP);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign S = (instruction[`OP_range] == `S_OP);\n                                     ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:52: Define or directive not defined: \'`S_OP\'\n    assign S = (instruction[`OP_range] == `S_OP);\n                                          ^~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:53: Define or directive not defined: \'`OP_range\'\n    assign J = (instruction[`OP_range] == `J_OP);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign J = (instruction[`OP_range] == `J_OP);\n                                     ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:53: Define or directive not defined: \'`J_OP\'\n    assign J = (instruction[`OP_range] == `J_OP);\n                                          ^~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:54: Define or directive not defined: \'`OP_range\'\n    assign IMM = (instruction[`OP_range] == `IMM_OP);\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign IMM = (instruction[`OP_range] == `IMM_OP);\n                                       ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:54: Define or directive not defined: \'`IMM_OP\'\n    assign IMM = (instruction[`OP_range] == `IMM_OP);\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:55: Define or directive not defined: \'`OP_range\'\n    assign LUI = (instruction[`OP_range] == `LUI_OP);\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign LUI = (instruction[`OP_range] == `LUI_OP);\n                                       ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:55: Define or directive not defined: \'`LUI_OP\'\n    assign LUI = (instruction[`OP_range] == `LUI_OP);\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:57: Define or directive not defined: \'`FUN3_range\'\n    assign ins_ADD = R && (instruction[`FUN3_range] == `R_FUN3_ADD)\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign ins_ADD = R && (instruction[`FUN3_range] == `R_FUN3_ADD)\n                                                  ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:57: Define or directive not defined: \'`R_FUN3_ADD\'\n    assign ins_ADD = R && (instruction[`FUN3_range] == `R_FUN3_ADD)\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:58: Define or directive not defined: \'`FUN7_range\'\n        && (instruction[`FUN7_range] ==`R_FUN7_ADD);\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:58: Define or directive not defined: \'`R_FUN7_ADD\'\n        && (instruction[`FUN7_range] ==`R_FUN7_ADD);\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:60: Define or directive not defined: \'`FUN3_range\'\n    assign ins_SUB = R && (instruction[`FUN3_range] == `R_FUN3_SUB)\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign ins_SUB = R && (instruction[`FUN3_range] == `R_FUN3_SUB)\n                                                  ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:60: Define or directive not defined: \'`R_FUN3_SUB\'\n    assign ins_SUB = R && (instruction[`FUN3_range] == `R_FUN3_SUB)\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:61: Define or directive not defined: \'`FUN7_range\'\n        && (instruction[`FUN7_range] == `R_FUN7_SUB);\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:61: Define or directive not defined: \'`R_FUN7_SUB\'\n        && (instruction[`FUN7_range] == `R_FUN7_SUB);\n                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:63: Define or directive not defined: \'`FUN3_range\'\n    assign ins_LW = I && (instruction[`FUN3_range] == `I_FUN3_LW);\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign ins_LW = I && (instruction[`FUN3_range] == `I_FUN3_LW);\n                                                 ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:63: Define or directive not defined: \'`I_FUN3_LW\'\n    assign ins_LW = I && (instruction[`FUN3_range] == `I_FUN3_LW);\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:64: Define or directive not defined: \'`FUN3_range\'\n    assign ins_SW = S && (instruction[`FUN3_range] == `S_FUN3_SW);\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign ins_SW = S && (instruction[`FUN3_range] == `S_FUN3_SW);\n                                                 ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:64: Define or directive not defined: \'`S_FUN3_SW\'\n    assign ins_SW = S && (instruction[`FUN3_range] == `S_FUN3_SW);\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:66: Define or directive not defined: \'`FUN3_range\'\n    assign ins_ADDI = IMM && (instruction[`FUN3_range] == `IMM_FUN3_ADDI);\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign ins_ADDI = IMM && (instruction[`FUN3_range] == `IMM_FUN3_ADDI);\n                                                     ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:66: Define or directive not defined: \'`IMM_FUN3_ADDI\'\n    assign ins_ADDI = IMM && (instruction[`FUN3_range] == `IMM_FUN3_ADDI);\n                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:96: Define or directive not defined: \'`rs1_range\'\n            reg_rs1 = instruction[`rs1_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs1 = instruction[`rs1_range];\n                                            ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:99: Define or directive not defined: \'`rs1_range\'\n            reg_rs1 = instruction[`rs1_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:99: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs1 = instruction[`rs1_range];\n                                            ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:102: Define or directive not defined: \'`rs1_range\'\n            reg_rs1 = instruction[`rs1_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:102: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs1 = instruction[`rs1_range];\n                                            ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:105: Define or directive not defined: \'`rs1_range\'\n            reg_rs1 = instruction[`rs1_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:105: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs1 = instruction[`rs1_range];\n                                            ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:108: Define or directive not defined: \'`rs1_range\'\n            reg_rs1 = instruction[`rs1_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs1 = instruction[`rs1_range];\n                                            ^\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:118: Define or directive not defined: \'`rs2_range\'\n            reg_rs2 = instruction[`rs2_range];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/instruction_decoder.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            reg_rs2 = instruction[`rs2_range];\n                                            ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module instruction_decoder(
    input [31:0] instruction,
    output ins_ADD,
    output ins_SUB,
    output ins_SW,
    output ins_LW,
    output ins_ADDI,
    output ins_LUI,
    output ins_JAL,
    output [31:0] IM,
    output reg [4:0] reg_rs1,
    output reg [4:0] reg_rs2,
    output reg [4:0] reg_rd,
    output [1:0] cnt_set,
    output stop
    );

    wire R, I, S, J, IMM, LUI;

    reg [1:0] cnt_set_r;
    assign cnt_set = cnt_set_r;

    reg [31:0] IM_in;
    assign IM = IM_in;

    assign stop = ~R & ~I & ~S & ~J & ~IMM & ~LUI;

    assign R = (instruction[`OP_range] == `R_OP);
    assign I = (instruction[`OP_range] == `I_OP);
    assign S = (instruction[`OP_range] == `S_OP);
    assign J = (instruction[`OP_range] == `J_OP);
    assign IMM = (instruction[`OP_range] == `IMM_OP);
    assign LUI = (instruction[`OP_range] == `LUI_OP);

    assign ins_ADD = R && (instruction[`FUN3_range] == `R_FUN3_ADD)
        && (instruction[`FUN7_range] ==`R_FUN7_ADD);
    
    assign ins_SUB = R && (instruction[`FUN3_range] == `R_FUN3_SUB)
        && (instruction[`FUN7_range] == `R_FUN7_SUB);
    
    assign ins_LW = I && (instruction[`FUN3_range] == `I_FUN3_LW);
    assign ins_SW = S && (instruction[`FUN3_range] == `S_FUN3_SW);
    assign ins_JAL = J;
    assign ins_ADDI = IMM && (instruction[`FUN3_range] == `IMM_FUN3_ADDI);
    assign ins_LUI = LUI;
    
    
    always @(*) begin
        IM_in = 32'b0;
        if (ins_LW) begin
            IM_in = {20'b0, instruction[31:20]};
        end
        else if (ins_SW) begin
            IM_in = {20'b0, instruction[31:25],instruction[11:7]};
        end
        else if (ins_ADDI) begin
            IM_in = {{20{instruction[31]}}, instruction[31:20]};
        end
        else if (ins_LUI) begin
            IM_in = {instruction[31:12], 12'b0};
        end
        else if (ins_JAL) begin
            IM_in = {11'b0 ,instruction[31], instruction[19:12], 
            instruction[20], instruction[30:21], 1'b0};
        end
        else begin
            IM_in = 32'b0;
        end
    end

    always @(*) begin
        reg_rs1 = 5'b0;
        if (ins_LW) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_SW) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_ADD) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_SUB) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_ADDI) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else begin
            reg_rs1 = 5'b0;
        end
    end

    always @(*) begin
        reg_rs2 = 5'b0;
        if (ins_SW) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else if (ins_ADD) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else if (ins_SUB) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else begin
            reg_rs2 = 5'b0;
        end
    end

    always @(*) begin
        reg_rd = 5'b0;
        if (ins_LW) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_ADD) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_SUB) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_ADDI) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_LUI) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_JAL) begin
            reg_rd = instruction[`rd_range];
        end
        else begin
            reg_rd = 5'b0;
        end
    end

    always @(*) begin
        cnt_set_r = 2'd0;
        if (ins_ADD) begin
            cnt_set_r = `ADD_cnt;
        end
        else if (ins_ADDI) begin
            cnt_set_r = `ADDI_cnt;
        end
        else if (ins_SUB) begin
            cnt_set_r = `SUB_cnt;
        end
        else if (ins_JAL) begin
            cnt_set_r = `JAL_cnt;
        end
        else if (ins_LUI) begin
            cnt_set_r = `LUI_cnt;
        end
        else if (ins_SW) begin
            cnt_set_r = `SW_cnt;
        end
        else if (ins_LW) begin
            cnt_set_r = `LW_cnt;
        end
        else begin
            cnt_set_r = 2'd0;
        end
    end

endmodule
module instruction_decoder(
    input [31:0] instruction,
    output ins_ADD,
    output ins_SUB,
    output ins_SW,
    output ins_LW,
    output ins_ADDI,
    output ins_LUI,
    output ins_JAL,
    output [31:0] IM,
    output reg [4:0] reg_rs1,
    output reg [4:0] reg_rs2,
    output reg [4:0] reg_rd,
    output [1:0] cnt_set,
    output stop
    );


    wire R, I, S, J, IMM, LUI;

    reg [1:0] cnt_set_r;
    assign cnt_set = cnt_set_r;

    reg [31:0] IM_in;
    assign IM = IM_in;

    assign stop = ~R & ~I & ~S & ~J & ~IMM & ~LUI;

    assign R = (instruction[`OP_range] == `R_OP);
    assign I = (instruction[`OP_range] == `I_OP);
    assign S = (instruction[`OP_range] == `S_OP);
    assign J = (instruction[`OP_range] == `J_OP);
    assign IMM = (instruction[`OP_range] == `IMM_OP);
    assign LUI = (instruction[`OP_range] == `LUI_OP);

    assign ins_ADD = R && (instruction[`FUN3_range] == `R_FUN3_ADD)
        && (instruction[`FUN7_range] ==`R_FUN7_ADD);
    
    assign ins_SUB = R && (instruction[`FUN3_range] == `R_FUN3_SUB)
        && (instruction[`FUN7_range] == `R_FUN7_SUB);
    
    assign ins_LW = I && (instruction[`FUN3_range] == `I_FUN3_LW);
    assign ins_SW = S && (instruction[`FUN3_range] == `S_FUN3_SW);
    assign ins_JAL = J;
    assign ins_ADDI = IMM && (instruction[`FUN3_range] == `IMM_FUN3_ADDI);
    assign ins_LUI = LUI;
    
    
    always @(*) begin
        IM_in = 32'b0;
        if (ins_LW) begin
            IM_in = {20'b0, instruction[31:20]};
        end
        else if (ins_SW) begin
            IM_in = {20'b0, instruction[31:25],instruction[11:7]};
        end
        else if (ins_ADDI) begin
            IM_in = {{20{instruction[31]}}, instruction[31:20]};
        end
        else if (ins_LUI) begin
            IM_in = {instruction[31:12], 12'b0};
        end
        else if (ins_JAL) begin
            IM_in = {11'b0 ,instruction[31], instruction[19:12], 
            instruction[20], instruction[30:21], 1'b0};
        end
        else begin
            IM_in = 32'b0;
        end
    end

    always @(*) begin
        reg_rs1 = 5'b0;
        if (ins_LW) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_SW) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_ADD) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_SUB) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else if (ins_ADDI) begin
            reg_rs1 = instruction[`rs1_range];
        end
        else begin
            reg_rs1 = 5'b0;
        end
    end

    always @(*) begin
        reg_rs2 = 5'b0;
        if (ins_SW) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else if (ins_ADD) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else if (ins_SUB) begin
            reg_rs2 = instruction[`rs2_range];
        end
        else begin
            reg_rs2 = 5'b0;
        end
    end

    always @(*) begin
        reg_rd = 5'b0;
        if (ins_LW) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_ADD) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_SUB) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_ADDI) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_LUI) begin
            reg_rd = instruction[`rd_range];
        end
        else if (ins_JAL) begin
            reg_rd = instruction[`rd_range];
        end
        else begin
            reg_rd = 5'b0;
        end
    end

    always @(*) begin
        cnt_set_r = 2'd0;
        if (ins_ADD) begin
            cnt_set_r = `ADD_cnt;
        end
        else if (ins_ADDI) begin
            cnt_set_r = `ADDI_cnt;
        end
        else if (ins_SUB) begin
            cnt_set_r = `SUB_cnt;
        end
        else if (ins_JAL) begin
            cnt_set_r = `JAL_cnt;
        end
        else if (ins_LUI) begin
            cnt_set_r = `LUI_cnt;
        end
        else if (ins_SW) begin
            cnt_set_r = `SW_cnt;
        end
        else if (ins_LW) begin
            cnt_set_r = `LW_cnt;
        end
        else begin
            cnt_set_r = 2'd0;
        end
    end

endmodule