data/full_repos/permissive/529469310/RSA/Smulti.v
data/verilator_xmls/c8571797-1f03-41cd-8ad8-9105c8a406bd.xml
module S_multi(clk, start, busy, A, B, Hreg, Lreg);

input clk, start;
input [`Bit-1:0] A,B;
output busy;
output [`Bit:0] Hreg;
output [`Bit-1:0] Lreg;

reg busy;
reg [`Bit:0] Hreg;
reg [`Bit-1:0] Lreg;
reg [1:0] state;
reg [`BitN:0] count;
wire [`Bit:0] sum;

assign sum = Hreg + A;

always @(posedge clk or negedge start) begin
if(!start) begin
    busy <= 0;
    count <= `BitN1'd`Bit;
    state <= 2'd`Init;
end else begin
    if(count != 0) begin
        if(state == `Init) begin
            Hreg <= 0;
            Lreg <= B;
            busy <= 1;
            state <= `Add;
        end else if(state == `Add) begin
            Hreg <= (Lreg[0] ? sum : Hreg);
            state <= `Shift;
        end else if(state == `Shift) begin
            {Hreg, Lreg} <= {1'b0, Hreg, Lreg[`Bit-1:1]};
            count <= count - 1;
            state <= `Add;
        end else begin
            busy <= 0;
        end
    end else begin
    busy <= 0;
    end
end
end

endmodule
module S_multi(clk, start, busy, A, B, Hreg, Lreg);


input clk, start;
input [`Bit-1:0] A,B;
output busy;
output [`Bit:0] Hreg;
output [`Bit-1:0] Lreg;

reg busy;
reg [`Bit:0] Hreg;
reg [`Bit-1:0] Lreg;
reg [1:0] state;
reg [`BitN:0] count;
wire [`Bit:0] sum;

assign sum = Hreg + A;

always @(posedge clk or negedge start) begin
if(!start) begin
    busy <= 0;
    count <= `BitN1'd`Bit;
    state <= 2'd`Init;
end else begin
    if(count != 0) begin
        if(state == `Init) begin
            Hreg <= 0;
            Lreg <= B;
            busy <= 1;
            state <= `Add;
        end else if(state == `Add) begin
            Hreg <= (Lreg[0] ? sum : Hreg);
            state <= `Shift;
        end else if(state == `Shift) begin
            {Hreg, Lreg} <= {1'b0, Hreg, Lreg[`Bit-1:1]};
            count <= count - 1;
            state <= `Add;
        end else begin
            busy <= 0;
        end
    end else begin
    busy <= 0;
    end
end
end

endmodule