data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:205: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                               : ... In instance PipeTester.u_pad_5\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:205: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                               : ... In instance PipeTester.u_pad_9\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:166: Input port connection \'a\' expects 4 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                               : ... In instance PipeTester.pipe\n        .a(1\'d0),\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module Pipe(
    input clock,
    input reset,
    input [3:0] in,
    output [3:0] out
);
    wire [3:0] _r__q;
    wire [3:0] _r__d;
    DFF_POSCLK #(.width(4)) r (
        .q(_r__q),
        .d(_r__d),
        .clk(clock)
    );
    wire [3:0] _s__q;
    wire [3:0] _s__d;
    DFF_POSCLK #(.width(4)) s (
        .q(_s__q),
        .d(_s__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(4)) u_mux_1 (
        .y(_s__d),
        .sel(reset),
        .a(1'd0),
        .b(_WTEMP_0)
    );
    assign out = _s__q;
    wire [3:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_2 (
        .y(_WTEMP_1),
        .in(1'd0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_3 (
        .y(_r__d),
        .sel(reset),
        .a(_WTEMP_1),
        .b(in)
    );
    assign _WTEMP_0 = _r__q;
endmodule
module Pipe(
    input clock,
    input reset,
    input [3:0] in,
    output [3:0] out
);

    wire [3:0] _r__q;
    wire [3:0] _r__d;
    DFF_POSCLK #(.width(4)) r (
        .q(_r__q),
        .d(_r__d),
        .clk(clock)
    );
    wire [3:0] _s__q;
    wire [3:0] _s__d;
    DFF_POSCLK #(.width(4)) s (
        .q(_s__q),
        .d(_s__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(4)) u_mux_1 (
        .y(_s__d),
        .sel(reset),
        .a(1'd0),
        .b(_WTEMP_0)
    );
    assign out = _s__q;
    wire [3:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_2 (
        .y(_WTEMP_1),
        .in(1'd0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_3 (
        .y(_r__d),
        .sel(reset),
        .a(_WTEMP_1),
        .b(in)
    );
    assign _WTEMP_0 = _r__q;
endmodule