data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:59: syntax error, unexpected \'@\'\n        @(negedge clk)\n        ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:62: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:64: syntax error, unexpected \';\'\n for(inti=0; inti<test_count; inti=inti+1) begin\n                            ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:64: syntax error, unexpected \')\', expecting \';\'\n for(inti=0; inti<test_count; inti=inti+1) begin\n                                         ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:65: syntax error, unexpected \';\'\n            for (intj=0; intj<ROWS; intj=intj+1) begin\n                                  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:65: syntax error, unexpected \')\', expecting \';\'\n            for (intj=0; intj<ROWS; intj=intj+1) begin\n                                               ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe_arr/pe_arr_test.v:73: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module pe_arr_test();
    parameter ROWS = 16;
    parameter COLS = 16;
    parameter test_count = 32;

    reg clk;
    reg rstn;
    reg fire;

    reg [7:0] in_w [0:COLS-1];
    wire [0 : 8*(COLS)-1] in_w_bus;

    reg [7:0] in_a [0:ROWS-1];
    wire [0 : 8*(ROWS)-1] in_a_bus;

    wire[31:0] outs [0:COLS*ROWS-1];
    wire[0 : 32*(COLS*ROWS)-1] outs_bus;

    integer inti, intj;
    genvar i,j;
    generate
        for (i=0; i<ROWS; i=i+1) begin
            assign in_w_bus[8*i : 8*(i+1)-1] = in_w[i];
        end
        for (i=0; i<COLS; i=i+1) begin
            assign in_a_bus[8*i : 8*(i+1)-1] = in_a[i];
        end
        for (i=0; i<ROWS*COLS; i=i+1) begin
            assign outs[i] = outs_bus[32*i : 32*(i+1)-1];
        end
    endgenerate


    initial forever 
    begin
        `HALF_CLOCK clk = ~clk;
    end


    PE_ARR #(.rows(ROWS), .cols(COLS)) 
        dut (.clk(clk), .rstn(rstn), .fire(fire), .in_w_port(in_w_bus), .in_a_port(in_a_bus), .outs_port(outs_bus));


    initial begin    

        clk <= 1;
        rstn <= 0;
        for (inti=0; inti<ROWS; inti=inti+1) begin
            in_w[inti] = inti;
        end
        for (inti=0; inti<COLS; inti=inti+1) begin
           in_a[inti] = 1;
        end

        @(negedge clk)
        fire <= 1;
        rstn <= 1;
        @(posedge clk)
	
	for(inti=0; inti<test_count; inti=inti+1) begin
            for (intj=0; intj<ROWS; intj=intj+1) begin
                in_w[intj] = in_w[intj] + 1;
            end
            @(posedge clk);
	end

        fire <= 0;
        for(inti=0; inti<COLS+1; inti=inti+1) begin
            @(posedge clk);
        end
	$finish;
    end
endmodule
module pe_arr_test();

    parameter ROWS = 16;
    parameter COLS = 16;
    parameter test_count = 32;

    reg clk;
    reg rstn;
    reg fire;

    reg [7:0] in_w [0:COLS-1];
    wire [0 : 8*(COLS)-1] in_w_bus;

    reg [7:0] in_a [0:ROWS-1];
    wire [0 : 8*(ROWS)-1] in_a_bus;

    wire[31:0] outs [0:COLS*ROWS-1];
    wire[0 : 32*(COLS*ROWS)-1] outs_bus;

    integer inti, intj;
    genvar i,j;
    generate
        for (i=0; i<ROWS; i=i+1) begin
            assign in_w_bus[8*i : 8*(i+1)-1] = in_w[i];
        end
        for (i=0; i<COLS; i=i+1) begin
            assign in_a_bus[8*i : 8*(i+1)-1] = in_a[i];
        end
        for (i=0; i<ROWS*COLS; i=i+1) begin
            assign outs[i] = outs_bus[32*i : 32*(i+1)-1];
        end
    endgenerate


    initial forever 
    begin
        `HALF_CLOCK clk = ~clk;
    end


    PE_ARR #(.rows(ROWS), .cols(COLS)) 
        dut (.clk(clk), .rstn(rstn), .fire(fire), .in_w_port(in_w_bus), .in_a_port(in_a_bus), .outs_port(outs_bus));


    initial begin    

        clk <= 1;
        rstn <= 0;
        for (inti=0; inti<ROWS; inti=inti+1) begin
            in_w[inti] = inti;
        end
        for (inti=0; inti<COLS; inti=inti+1) begin
           in_a[inti] = 1;
        end

        @(negedge clk)
        fire <= 1;
        rstn <= 1;
        @(posedge clk)
	
	for(inti=0; inti<test_count; inti=inti+1) begin
            for (intj=0; intj<ROWS; intj=intj+1) begin
                in_w[intj] = in_w[intj] + 1;
            end
            @(posedge clk);
	end

        fire <= 0;
        for(inti=0; inti<COLS+1; inti=inti+1) begin
            @(posedge clk);
        end
	$finish;
    end
endmodule