data/full_repos/permissive/469129654/src/aoi_primitive.v
data/verilator_xmls/8684a6f4-fc79-4aed-b3c0-08b2346d8e8c.xml
module aoi_primitive(a, b, c, d, y);
    input a, b, c, d;
    output y;

    wire connect1, connect2, connect3;

    and #(3) and0(connect1, a, b);
    and #(3) and1(connect2, c, d);
    or  #(3) or0(connect3, connect1, connect2);
    not #(3) not0(y, connect3);
endmodule
module aoi_primitive(a, b, c, d, y);

    input a, b, c, d;
    output y;

    wire connect1, connect2, connect3;

    and #(3) and0(connect1, a, b);
    and #(3) and1(connect2, c, d);
    or  #(3) or0(connect3, connect1, connect2);
    not #(3) not0(y, connect3);
endmodule