data/full_repos/permissive/495988601/ram.sv
data/verilator_xmls/d61d9104-ac32-4480-ab43-9111389c1389.xml
module  frameROM
(
		input int  address,
		input Clk,

		output logic [23:0] color_data
);


logic [23:0] mem [0:399];

initial
begin
	 $readmemh("tetris_I.txt", mem);
end


always_ff @ (posedge Clk) begin
	color_data<= mem[address];
end

endmodule
module  frameROM
(
		input int  address,
		input Clk,

		output logic [23:0] color_data
);



logic [23:0] mem [0:399];

initial
begin
	 $readmemh("tetris_I.txt", mem);
end


always_ff @ (posedge Clk) begin
	color_data<= mem[address];
end

endmodule