data/full_repos/permissive/507307707/generated/CellProcessing.v
data/verilator_xmls/ab97e684-dfea-49c9-88b0-d7fe90873c62.xml
module CellProcessing(
  input          clock,
  input          reset,
  input  [31:0]  io_north_din,
  input          io_north_din_v,
  input  [31:0]  io_east_din,
  input          io_east_din_v,
  input  [31:0]  io_south_din,
  input          io_south_din_v,
  input  [31:0]  io_west_din,
  input          io_west_din_v,
  output         io_FU_din_1_r,
  output         io_FU_din_2_r,
  output [31:0]  io_dout,
  output         io_dout_v,
  input          io_north_dout_r,
  input          io_east_dout_r,
  input          io_south_dout_r,
  input          io_west_dout_r,
  input  [181:0] io_config_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif
  wire [5:0] FR_1_io_valid_in;
  wire [3:0] FR_1_io_ready_out;
  wire [2:0] FR_1_io_valid_mux_sel;
  wire [3:0] FR_1_io_fork_mask;
  wire  FR_1_io_valid_out;
  wire [2:0] MUX_1_io_selector;
  wire [191:0] MUX_1_io_mux_input;
  wire [31:0] MUX_1_io_mux_output;
  wire  SEB_1_clock;
  wire  SEB_1_reset;
  wire [31:0] SEB_1_io_din;
  wire  SEB_1_io_din_v;
  wire  SEB_1_io_din_r;
  wire [31:0] SEB_1_io_dout;
  wire  SEB_1_io_dout_v;
  wire  SEB_1_io_dout_r;
  wire [5:0] FR_2_io_valid_in;
  wire [3:0] FR_2_io_ready_out;
  wire [2:0] FR_2_io_valid_mux_sel;
  wire [3:0] FR_2_io_fork_mask;
  wire  FR_2_io_valid_out;
  wire [2:0] MUX_2_io_selector;
  wire [191:0] MUX_2_io_mux_input;
  wire [31:0] MUX_2_io_mux_output;
  wire  SEB_2_clock;
  wire  SEB_2_reset;
  wire [31:0] SEB_2_io_din;
  wire  SEB_2_io_din_v;
  wire  SEB_2_io_din_r;
  wire [31:0] SEB_2_io_dout;
  wire  SEB_2_io_dout_v;
  wire  SEB_2_io_dout_r;
  wire [31:0] JOIN_INST_io_din_1;
  wire [31:0] JOIN_INST_io_din_2;
  wire  JOIN_INST_io_dout_r;
  wire  JOIN_INST_io_din_1_v;
  wire  JOIN_INST_io_din_2_v;
  wire  JOIN_INST_io_dout_v;
  wire  JOIN_INST_io_din_1_r;
  wire  JOIN_INST_io_din_2_r;
  wire [31:0] JOIN_INST_io_dout_1;
  wire [31:0] JOIN_INST_io_dout_2;
  wire  FU_INST_clock;
  wire  FU_INST_reset;
  wire [31:0] FU_INST_io_din_1;
  wire [31:0] FU_INST_io_din_2;
  wire  FU_INST_io_din_v;
  wire  FU_INST_io_dout_r;
  wire [1:0] FU_INST_io_loop_source;
  wire [15:0] FU_INST_io_iterations_reset;
  wire [3:0] FU_INST_io_op_config;
  wire  FU_INST_io_din_r;
  wire [31:0] FU_INST_io_dout;
  wire  FU_INST_io_dout_v;
  wire  SEB_OUT_clock;
  wire  SEB_OUT_reset;
  wire [31:0] SEB_OUT_io_din;
  wire  SEB_OUT_io_din_v;
  wire  SEB_OUT_io_din_r;
  wire [31:0] SEB_OUT_io_dout;
  wire  SEB_OUT_io_dout_v;
  wire  SEB_OUT_io_dout_r;
  wire [4:0] FS_io_ready_out;
  wire [4:0] FS_io_fork_mask;
  wire  FS_io_ready_in;
  reg [2:0] selector_mux_1;
  reg [2:0] selector_mux_2;
  reg [3:0] fork_receiver_mask_1;
  reg [3:0] fork_receiver_mask_2;
  reg [4:0] op_config;
  reg [4:0] fork_sender_mask;
  reg [31:0] I1_const;
  reg [15:0] iterations_reset_load;
  reg [1:0] load_initial_value;
  reg [31:0] FU_dout;
  reg [31:0] EB_din_1;
  reg [31:0] EB_din_2;
  reg [31:0] join_din_1;
  reg [31:0] join_dout_1;
  reg [31:0] join_dout_2;
  wire [1:0] ready_FR1_lo = {io_south_dout_r,io_west_dout_r};
  wire [1:0] ready_FR1_hi = {io_north_dout_r,io_east_dout_r};
  wire [2:0] valid_in_FR1_lo = {io_south_din_v,io_east_din_v,io_north_din_v};
  wire  FU_dout_v = FU_INST_io_dout_v;
  wire [2:0] valid_in_FR1_hi = {FU_dout_v,1'h1,io_west_din_v};
  wire [95:0] MUX_1_io_mux_input_lo = {io_south_din,io_east_din,io_north_din};
  wire [95:0] MUX_1_io_mux_input_hi = {FU_dout,I1_const,io_west_din};
  wire [31:0] _MUX_2_io_mux_input_T = FU_dout & I1_const;
  wire [31:0] _MUX_2_io_mux_input_T_1 = _MUX_2_io_mux_input_T & io_west_din;
  wire [31:0] _MUX_2_io_mux_input_T_2 = _MUX_2_io_mux_input_T_1 & io_south_din;
  wire [31:0] _MUX_2_io_mux_input_T_3 = _MUX_2_io_mux_input_T_2 & io_east_din;
  wire [31:0] _MUX_2_io_mux_input_T_4 = _MUX_2_io_mux_input_T_3 & io_north_din;
  wire [2:0] ready_out_FS_hi = {1'h1,io_north_dout_r,io_east_dout_r};
  wire  join_din_1_v = SEB_1_io_dout_v;
  FR FR_1 (
    .io_valid_in(FR_1_io_valid_in),
    .io_ready_out(FR_1_io_ready_out),
    .io_valid_mux_sel(FR_1_io_valid_mux_sel),
    .io_fork_mask(FR_1_io_fork_mask),
    .io_valid_out(FR_1_io_valid_out)
  );
  ConfMux_1 MUX_1 (
    .io_selector(MUX_1_io_selector),
    .io_mux_input(MUX_1_io_mux_input),
    .io_mux_output(MUX_1_io_mux_output)
  );
  D_SEB SEB_1 (
    .clock(SEB_1_clock),
    .reset(SEB_1_reset),
    .io_din(SEB_1_io_din),
    .io_din_v(SEB_1_io_din_v),
    .io_din_r(SEB_1_io_din_r),
    .io_dout(SEB_1_io_dout),
    .io_dout_v(SEB_1_io_dout_v),
    .io_dout_r(SEB_1_io_dout_r)
  );
  FR FR_2 (
    .io_valid_in(FR_2_io_valid_in),
    .io_ready_out(FR_2_io_ready_out),
    .io_valid_mux_sel(FR_2_io_valid_mux_sel),
    .io_fork_mask(FR_2_io_fork_mask),
    .io_valid_out(FR_2_io_valid_out)
  );
  ConfMux_1 MUX_2 (
    .io_selector(MUX_2_io_selector),
    .io_mux_input(MUX_2_io_mux_input),
    .io_mux_output(MUX_2_io_mux_output)
  );
  D_SEB SEB_2 (
    .clock(SEB_2_clock),
    .reset(SEB_2_reset),
    .io_din(SEB_2_io_din),
    .io_din_v(SEB_2_io_din_v),
    .io_din_r(SEB_2_io_din_r),
    .io_dout(SEB_2_io_dout),
    .io_dout_v(SEB_2_io_dout_v),
    .io_dout_r(SEB_2_io_dout_r)
  );
  Join JOIN_INST (
    .io_din_1(JOIN_INST_io_din_1),
    .io_din_2(JOIN_INST_io_din_2),
    .io_dout_r(JOIN_INST_io_dout_r),
    .io_din_1_v(JOIN_INST_io_din_1_v),
    .io_din_2_v(JOIN_INST_io_din_2_v),
    .io_dout_v(JOIN_INST_io_dout_v),
    .io_din_1_r(JOIN_INST_io_din_1_r),
    .io_din_2_r(JOIN_INST_io_din_2_r),
    .io_dout_1(JOIN_INST_io_dout_1),
    .io_dout_2(JOIN_INST_io_dout_2)
  );
  FU FU_INST (
    .clock(FU_INST_clock),
    .reset(FU_INST_reset),
    .io_din_1(FU_INST_io_din_1),
    .io_din_2(FU_INST_io_din_2),
    .io_din_v(FU_INST_io_din_v),
    .io_dout_r(FU_INST_io_dout_r),
    .io_loop_source(FU_INST_io_loop_source),
    .io_iterations_reset(FU_INST_io_iterations_reset),
    .io_op_config(FU_INST_io_op_config),
    .io_din_r(FU_INST_io_din_r),
    .io_dout(FU_INST_io_dout),
    .io_dout_v(FU_INST_io_dout_v)
  );
  D_SEB SEB_OUT (
    .clock(SEB_OUT_clock),
    .reset(SEB_OUT_reset),
    .io_din(SEB_OUT_io_din),
    .io_din_v(SEB_OUT_io_din_v),
    .io_din_r(SEB_OUT_io_din_r),
    .io_dout(SEB_OUT_io_dout),
    .io_dout_v(SEB_OUT_io_dout_v),
    .io_dout_r(SEB_OUT_io_dout_r)
  );
  FS FS (
    .io_ready_out(FS_io_ready_out),
    .io_fork_mask(FS_io_fork_mask),
    .io_ready_in(FS_io_ready_in)
  );
  assign io_FU_din_1_r = SEB_1_io_din_r;
  assign io_FU_din_2_r = SEB_2_io_din_r;
  assign io_dout = SEB_OUT_io_dout;
  assign io_dout_v = SEB_OUT_io_dout_v;
  assign FR_1_io_valid_in = {valid_in_FR1_hi,valid_in_FR1_lo};
  assign FR_1_io_ready_out = {ready_FR1_hi,ready_FR1_lo};
  assign FR_1_io_valid_mux_sel = selector_mux_1;
  assign FR_1_io_fork_mask = fork_receiver_mask_1;
  assign MUX_1_io_selector = selector_mux_1;
  assign MUX_1_io_mux_input = {MUX_1_io_mux_input_hi,MUX_1_io_mux_input_lo};
  assign SEB_1_clock = clock;
  assign SEB_1_reset = reset;
  assign SEB_1_io_din = EB_din_1;
  assign SEB_1_io_din_v = FR_1_io_valid_out;
  assign SEB_1_io_dout_r = JOIN_INST_io_din_1_r;
  assign FR_2_io_valid_in = {valid_in_FR1_hi,valid_in_FR1_lo};
  assign FR_2_io_ready_out = {ready_FR1_hi,ready_FR1_lo};
  assign FR_2_io_valid_mux_sel = selector_mux_2;
  assign FR_2_io_fork_mask = fork_receiver_mask_2;
  assign MUX_2_io_selector = selector_mux_2;
  assign MUX_2_io_mux_input = {{160'd0}, _MUX_2_io_mux_input_T_4};
  assign SEB_2_clock = clock;
  assign SEB_2_reset = reset;
  assign SEB_2_io_din = EB_din_2;
  assign SEB_2_io_din_v = FR_2_io_valid_out;
  assign SEB_2_io_dout_r = JOIN_INST_io_din_2_r;
  assign JOIN_INST_io_din_1 = join_din_1;
  assign JOIN_INST_io_din_2 = {{31'd0}, join_din_1_v};
  assign JOIN_INST_io_dout_r = FU_INST_io_din_r;
  assign JOIN_INST_io_din_1_v = SEB_1_io_dout_v;
  assign JOIN_INST_io_din_2_v = SEB_1_io_dout_v;
  assign FU_INST_clock = clock;
  assign FU_INST_reset = reset;
  assign FU_INST_io_din_1 = join_dout_1;
  assign FU_INST_io_din_2 = join_dout_2;
  assign FU_INST_io_din_v = JOIN_INST_io_dout_v;
  assign FU_INST_io_dout_r = SEB_OUT_io_din_r;
  assign FU_INST_io_loop_source = load_initial_value;
  assign FU_INST_io_iterations_reset = iterations_reset_load;
  assign FU_INST_io_op_config = op_config[3:0];
  assign SEB_OUT_clock = clock;
  assign SEB_OUT_reset = reset;
  assign SEB_OUT_io_din = FU_dout;
  assign SEB_OUT_io_din_v = FU_INST_io_dout_v;
  assign SEB_OUT_io_dout_r = FS_io_ready_in;
  assign FS_io_ready_out = {ready_out_FS_hi,ready_FR1_lo};
  assign FS_io_fork_mask = fork_sender_mask;
  always @(posedge clock) begin
    if (reset) begin
      selector_mux_1 <= 3'h0;
    end else begin
      selector_mux_1 <= io_config_bits[2:0];
    end
    if (reset) begin
      selector_mux_2 <= 3'h0;
    end else begin
      selector_mux_2 <= io_config_bits[5:3];
    end
    if (reset) begin
      fork_receiver_mask_1 <= 4'h0;
    end else begin
      fork_receiver_mask_1 <= io_config_bits[17:14];
    end
    if (reset) begin
      fork_receiver_mask_2 <= 4'h0;
    end else begin
      fork_receiver_mask_2 <= io_config_bits[23:20];
    end
    if (reset) begin
      op_config <= 5'h0;
    end else begin
      op_config <= io_config_bits[48:44];
    end
    if (reset) begin
      fork_sender_mask <= 5'h0;
    end else begin
      fork_sender_mask <= io_config_bits[56:52];
    end
    if (reset) begin
      I1_const <= 32'h0;
    end else begin
      I1_const <= io_config_bits[115:84];
    end
    if (reset) begin
      iterations_reset_load <= 16'h0;
    end else begin
      iterations_reset_load <= io_config_bits[179:164];
    end
    if (reset) begin
      load_initial_value <= 2'h0;
    end else begin
      load_initial_value <= io_config_bits[181:180];
    end
    if (reset) begin
      FU_dout <= 32'h0;
    end else begin
      FU_dout <= FU_INST_io_dout;
    end
    if (reset) begin
      EB_din_1 <= 32'h0;
    end else begin
      EB_din_1 <= MUX_1_io_mux_output;
    end
    if (reset) begin
      EB_din_2 <= 32'h0;
    end else begin
      EB_din_2 <= MUX_2_io_mux_output;
    end
    if (reset) begin
      join_din_1 <= 32'h0;
    end else begin
      join_din_1 <= SEB_1_io_dout;
    end
    if (reset) begin
      join_dout_1 <= 32'h0;
    end else begin
      join_dout_1 <= JOIN_INST_io_dout_1;
    end
    if (reset) begin
      join_dout_2 <= 32'h0;
    end else begin
      join_dout_2 <= JOIN_INST_io_dout_2;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  selector_mux_1 = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  selector_mux_2 = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  fork_receiver_mask_1 = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  fork_receiver_mask_2 = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  op_config = _RAND_4[4:0];
  _RAND_5 = {1{`RANDOM}};
  fork_sender_mask = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  I1_const = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  iterations_reset_load = _RAND_7[15:0];
  _RAND_8 = {1{`RANDOM}};
  load_initial_value = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  FU_dout = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  EB_din_1 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  EB_din_2 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  join_din_1 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  join_dout_1 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  join_dout_2 = _RAND_14[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module CellProcessing(
  input          clock,
  input          reset,
  input  [31:0]  io_north_din,
  input          io_north_din_v,
  input  [31:0]  io_east_din,
  input          io_east_din_v,
  input  [31:0]  io_south_din,
  input          io_south_din_v,
  input  [31:0]  io_west_din,
  input          io_west_din_v,
  output         io_FU_din_1_r,
  output         io_FU_din_2_r,
  output [31:0]  io_dout,
  output         io_dout_v,
  input          io_north_dout_r,
  input          io_east_dout_r,
  input          io_south_dout_r,
  input          io_west_dout_r,
  input  [181:0] io_config_bits
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif
  wire [5:0] FR_1_io_valid_in;
  wire [3:0] FR_1_io_ready_out;
  wire [2:0] FR_1_io_valid_mux_sel;
  wire [3:0] FR_1_io_fork_mask;
  wire  FR_1_io_valid_out;
  wire [2:0] MUX_1_io_selector;
  wire [191:0] MUX_1_io_mux_input;
  wire [31:0] MUX_1_io_mux_output;
  wire  SEB_1_clock;
  wire  SEB_1_reset;
  wire [31:0] SEB_1_io_din;
  wire  SEB_1_io_din_v;
  wire  SEB_1_io_din_r;
  wire [31:0] SEB_1_io_dout;
  wire  SEB_1_io_dout_v;
  wire  SEB_1_io_dout_r;
  wire [5:0] FR_2_io_valid_in;
  wire [3:0] FR_2_io_ready_out;
  wire [2:0] FR_2_io_valid_mux_sel;
  wire [3:0] FR_2_io_fork_mask;
  wire  FR_2_io_valid_out;
  wire [2:0] MUX_2_io_selector;
  wire [191:0] MUX_2_io_mux_input;
  wire [31:0] MUX_2_io_mux_output;
  wire  SEB_2_clock;
  wire  SEB_2_reset;
  wire [31:0] SEB_2_io_din;
  wire  SEB_2_io_din_v;
  wire  SEB_2_io_din_r;
  wire [31:0] SEB_2_io_dout;
  wire  SEB_2_io_dout_v;
  wire  SEB_2_io_dout_r;
  wire [31:0] JOIN_INST_io_din_1;
  wire [31:0] JOIN_INST_io_din_2;
  wire  JOIN_INST_io_dout_r;
  wire  JOIN_INST_io_din_1_v;
  wire  JOIN_INST_io_din_2_v;
  wire  JOIN_INST_io_dout_v;
  wire  JOIN_INST_io_din_1_r;
  wire  JOIN_INST_io_din_2_r;
  wire [31:0] JOIN_INST_io_dout_1;
  wire [31:0] JOIN_INST_io_dout_2;
  wire  FU_INST_clock;
  wire  FU_INST_reset;
  wire [31:0] FU_INST_io_din_1;
  wire [31:0] FU_INST_io_din_2;
  wire  FU_INST_io_din_v;
  wire  FU_INST_io_dout_r;
  wire [1:0] FU_INST_io_loop_source;
  wire [15:0] FU_INST_io_iterations_reset;
  wire [3:0] FU_INST_io_op_config;
  wire  FU_INST_io_din_r;
  wire [31:0] FU_INST_io_dout;
  wire  FU_INST_io_dout_v;
  wire  SEB_OUT_clock;
  wire  SEB_OUT_reset;
  wire [31:0] SEB_OUT_io_din;
  wire  SEB_OUT_io_din_v;
  wire  SEB_OUT_io_din_r;
  wire [31:0] SEB_OUT_io_dout;
  wire  SEB_OUT_io_dout_v;
  wire  SEB_OUT_io_dout_r;
  wire [4:0] FS_io_ready_out;
  wire [4:0] FS_io_fork_mask;
  wire  FS_io_ready_in;
  reg [2:0] selector_mux_1;
  reg [2:0] selector_mux_2;
  reg [3:0] fork_receiver_mask_1;
  reg [3:0] fork_receiver_mask_2;
  reg [4:0] op_config;
  reg [4:0] fork_sender_mask;
  reg [31:0] I1_const;
  reg [15:0] iterations_reset_load;
  reg [1:0] load_initial_value;
  reg [31:0] FU_dout;
  reg [31:0] EB_din_1;
  reg [31:0] EB_din_2;
  reg [31:0] join_din_1;
  reg [31:0] join_dout_1;
  reg [31:0] join_dout_2;
  wire [1:0] ready_FR1_lo = {io_south_dout_r,io_west_dout_r};
  wire [1:0] ready_FR1_hi = {io_north_dout_r,io_east_dout_r};
  wire [2:0] valid_in_FR1_lo = {io_south_din_v,io_east_din_v,io_north_din_v};
  wire  FU_dout_v = FU_INST_io_dout_v;
  wire [2:0] valid_in_FR1_hi = {FU_dout_v,1'h1,io_west_din_v};
  wire [95:0] MUX_1_io_mux_input_lo = {io_south_din,io_east_din,io_north_din};
  wire [95:0] MUX_1_io_mux_input_hi = {FU_dout,I1_const,io_west_din};
  wire [31:0] _MUX_2_io_mux_input_T = FU_dout & I1_const;
  wire [31:0] _MUX_2_io_mux_input_T_1 = _MUX_2_io_mux_input_T & io_west_din;
  wire [31:0] _MUX_2_io_mux_input_T_2 = _MUX_2_io_mux_input_T_1 & io_south_din;
  wire [31:0] _MUX_2_io_mux_input_T_3 = _MUX_2_io_mux_input_T_2 & io_east_din;
  wire [31:0] _MUX_2_io_mux_input_T_4 = _MUX_2_io_mux_input_T_3 & io_north_din;
  wire [2:0] ready_out_FS_hi = {1'h1,io_north_dout_r,io_east_dout_r};
  wire  join_din_1_v = SEB_1_io_dout_v;
  FR FR_1 (
    .io_valid_in(FR_1_io_valid_in),
    .io_ready_out(FR_1_io_ready_out),
    .io_valid_mux_sel(FR_1_io_valid_mux_sel),
    .io_fork_mask(FR_1_io_fork_mask),
    .io_valid_out(FR_1_io_valid_out)
  );
  ConfMux_1 MUX_1 (
    .io_selector(MUX_1_io_selector),
    .io_mux_input(MUX_1_io_mux_input),
    .io_mux_output(MUX_1_io_mux_output)
  );
  D_SEB SEB_1 (
    .clock(SEB_1_clock),
    .reset(SEB_1_reset),
    .io_din(SEB_1_io_din),
    .io_din_v(SEB_1_io_din_v),
    .io_din_r(SEB_1_io_din_r),
    .io_dout(SEB_1_io_dout),
    .io_dout_v(SEB_1_io_dout_v),
    .io_dout_r(SEB_1_io_dout_r)
  );
  FR FR_2 (
    .io_valid_in(FR_2_io_valid_in),
    .io_ready_out(FR_2_io_ready_out),
    .io_valid_mux_sel(FR_2_io_valid_mux_sel),
    .io_fork_mask(FR_2_io_fork_mask),
    .io_valid_out(FR_2_io_valid_out)
  );
  ConfMux_1 MUX_2 (
    .io_selector(MUX_2_io_selector),
    .io_mux_input(MUX_2_io_mux_input),
    .io_mux_output(MUX_2_io_mux_output)
  );
  D_SEB SEB_2 (
    .clock(SEB_2_clock),
    .reset(SEB_2_reset),
    .io_din(SEB_2_io_din),
    .io_din_v(SEB_2_io_din_v),
    .io_din_r(SEB_2_io_din_r),
    .io_dout(SEB_2_io_dout),
    .io_dout_v(SEB_2_io_dout_v),
    .io_dout_r(SEB_2_io_dout_r)
  );
  Join JOIN_INST (
    .io_din_1(JOIN_INST_io_din_1),
    .io_din_2(JOIN_INST_io_din_2),
    .io_dout_r(JOIN_INST_io_dout_r),
    .io_din_1_v(JOIN_INST_io_din_1_v),
    .io_din_2_v(JOIN_INST_io_din_2_v),
    .io_dout_v(JOIN_INST_io_dout_v),
    .io_din_1_r(JOIN_INST_io_din_1_r),
    .io_din_2_r(JOIN_INST_io_din_2_r),
    .io_dout_1(JOIN_INST_io_dout_1),
    .io_dout_2(JOIN_INST_io_dout_2)
  );
  FU FU_INST (
    .clock(FU_INST_clock),
    .reset(FU_INST_reset),
    .io_din_1(FU_INST_io_din_1),
    .io_din_2(FU_INST_io_din_2),
    .io_din_v(FU_INST_io_din_v),
    .io_dout_r(FU_INST_io_dout_r),
    .io_loop_source(FU_INST_io_loop_source),
    .io_iterations_reset(FU_INST_io_iterations_reset),
    .io_op_config(FU_INST_io_op_config),
    .io_din_r(FU_INST_io_din_r),
    .io_dout(FU_INST_io_dout),
    .io_dout_v(FU_INST_io_dout_v)
  );
  D_SEB SEB_OUT (
    .clock(SEB_OUT_clock),
    .reset(SEB_OUT_reset),
    .io_din(SEB_OUT_io_din),
    .io_din_v(SEB_OUT_io_din_v),
    .io_din_r(SEB_OUT_io_din_r),
    .io_dout(SEB_OUT_io_dout),
    .io_dout_v(SEB_OUT_io_dout_v),
    .io_dout_r(SEB_OUT_io_dout_r)
  );
  FS FS (
    .io_ready_out(FS_io_ready_out),
    .io_fork_mask(FS_io_fork_mask),
    .io_ready_in(FS_io_ready_in)
  );
  assign io_FU_din_1_r = SEB_1_io_din_r;
  assign io_FU_din_2_r = SEB_2_io_din_r;
  assign io_dout = SEB_OUT_io_dout;
  assign io_dout_v = SEB_OUT_io_dout_v;
  assign FR_1_io_valid_in = {valid_in_FR1_hi,valid_in_FR1_lo};
  assign FR_1_io_ready_out = {ready_FR1_hi,ready_FR1_lo};
  assign FR_1_io_valid_mux_sel = selector_mux_1;
  assign FR_1_io_fork_mask = fork_receiver_mask_1;
  assign MUX_1_io_selector = selector_mux_1;
  assign MUX_1_io_mux_input = {MUX_1_io_mux_input_hi,MUX_1_io_mux_input_lo};
  assign SEB_1_clock = clock;
  assign SEB_1_reset = reset;
  assign SEB_1_io_din = EB_din_1;
  assign SEB_1_io_din_v = FR_1_io_valid_out;
  assign SEB_1_io_dout_r = JOIN_INST_io_din_1_r;
  assign FR_2_io_valid_in = {valid_in_FR1_hi,valid_in_FR1_lo};
  assign FR_2_io_ready_out = {ready_FR1_hi,ready_FR1_lo};
  assign FR_2_io_valid_mux_sel = selector_mux_2;
  assign FR_2_io_fork_mask = fork_receiver_mask_2;
  assign MUX_2_io_selector = selector_mux_2;
  assign MUX_2_io_mux_input = {{160'd0}, _MUX_2_io_mux_input_T_4};
  assign SEB_2_clock = clock;
  assign SEB_2_reset = reset;
  assign SEB_2_io_din = EB_din_2;
  assign SEB_2_io_din_v = FR_2_io_valid_out;
  assign SEB_2_io_dout_r = JOIN_INST_io_din_2_r;
  assign JOIN_INST_io_din_1 = join_din_1;
  assign JOIN_INST_io_din_2 = {{31'd0}, join_din_1_v};
  assign JOIN_INST_io_dout_r = FU_INST_io_din_r;
  assign JOIN_INST_io_din_1_v = SEB_1_io_dout_v;
  assign JOIN_INST_io_din_2_v = SEB_1_io_dout_v;
  assign FU_INST_clock = clock;
  assign FU_INST_reset = reset;
  assign FU_INST_io_din_1 = join_dout_1;
  assign FU_INST_io_din_2 = join_dout_2;
  assign FU_INST_io_din_v = JOIN_INST_io_dout_v;
  assign FU_INST_io_dout_r = SEB_OUT_io_din_r;
  assign FU_INST_io_loop_source = load_initial_value;
  assign FU_INST_io_iterations_reset = iterations_reset_load;
  assign FU_INST_io_op_config = op_config[3:0];
  assign SEB_OUT_clock = clock;
  assign SEB_OUT_reset = reset;
  assign SEB_OUT_io_din = FU_dout;
  assign SEB_OUT_io_din_v = FU_INST_io_dout_v;
  assign SEB_OUT_io_dout_r = FS_io_ready_in;
  assign FS_io_ready_out = {ready_out_FS_hi,ready_FR1_lo};
  assign FS_io_fork_mask = fork_sender_mask;
  always @(posedge clock) begin
    if (reset) begin
      selector_mux_1 <= 3'h0;
    end else begin
      selector_mux_1 <= io_config_bits[2:0];
    end
    if (reset) begin
      selector_mux_2 <= 3'h0;
    end else begin
      selector_mux_2 <= io_config_bits[5:3];
    end
    if (reset) begin
      fork_receiver_mask_1 <= 4'h0;
    end else begin
      fork_receiver_mask_1 <= io_config_bits[17:14];
    end
    if (reset) begin
      fork_receiver_mask_2 <= 4'h0;
    end else begin
      fork_receiver_mask_2 <= io_config_bits[23:20];
    end
    if (reset) begin
      op_config <= 5'h0;
    end else begin
      op_config <= io_config_bits[48:44];
    end
    if (reset) begin
      fork_sender_mask <= 5'h0;
    end else begin
      fork_sender_mask <= io_config_bits[56:52];
    end
    if (reset) begin
      I1_const <= 32'h0;
    end else begin
      I1_const <= io_config_bits[115:84];
    end
    if (reset) begin
      iterations_reset_load <= 16'h0;
    end else begin
      iterations_reset_load <= io_config_bits[179:164];
    end
    if (reset) begin
      load_initial_value <= 2'h0;
    end else begin
      load_initial_value <= io_config_bits[181:180];
    end
    if (reset) begin
      FU_dout <= 32'h0;
    end else begin
      FU_dout <= FU_INST_io_dout;
    end
    if (reset) begin
      EB_din_1 <= 32'h0;
    end else begin
      EB_din_1 <= MUX_1_io_mux_output;
    end
    if (reset) begin
      EB_din_2 <= 32'h0;
    end else begin
      EB_din_2 <= MUX_2_io_mux_output;
    end
    if (reset) begin
      join_din_1 <= 32'h0;
    end else begin
      join_din_1 <= SEB_1_io_dout;
    end
    if (reset) begin
      join_dout_1 <= 32'h0;
    end else begin
      join_dout_1 <= JOIN_INST_io_dout_1;
    end
    if (reset) begin
      join_dout_2 <= 32'h0;
    end else begin
      join_dout_2 <= JOIN_INST_io_dout_2;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  selector_mux_1 = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  selector_mux_2 = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  fork_receiver_mask_1 = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  fork_receiver_mask_2 = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  op_config = _RAND_4[4:0];
  _RAND_5 = {1{`RANDOM}};
  fork_sender_mask = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  I1_const = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  iterations_reset_load = _RAND_7[15:0];
  _RAND_8 = {1{`RANDOM}};
  load_initial_value = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  FU_dout = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  EB_din_1 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  EB_din_2 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  join_din_1 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  join_dout_1 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  join_dout_2 = _RAND_14[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule