data/full_repos/permissive/489462235/final_projSrc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:170: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwda = 2\'b00;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:171: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwdb = 2\'b00;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:174: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwda = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:173: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rs) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:178: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwdb = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:177: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rt) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:183: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:186: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:192: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:195: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Input port connection \'edestReg\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'edestReg\' generates 5 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                             ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwda\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwda\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwdb\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwdb\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                                    ^~~~\n%Error: Exiting due to 13 warning(s)\n'
module control_unit (op, func, rs, rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);
    input [5:0] op;
    input [5:0] func;
    input [4:0] rs;
    input [4:0] rt;
    input [4:0] mdestReg;
    input mm2reg, mwreg, edestReg, em2reg, ewreg;
    output reg regrt, wreg, m2reg, wmem, aluimm;
    output reg [3:0] aluc;
    output reg [31:0] fwda;
    output reg [31:0] fwdb;
    
    always @(*) begin
        fwda = 2'b00;
        fwdb = 2'b00;
        
        if (edestReg == rs) begin
            fwda = 2'b01;
        end
        
        if (edestReg == rt) begin
            fwdb = 2'b01;
        end
        
        if (mdestReg == rs) begin
            if (mm2reg == 1) begin
                fwda = 2'b11;
            end
            else begin
                fwda = 2'b10;
            end
        end
        
        if (mdestReg == rt) begin
            if (mm2reg == 1) begin
                fwdb = 2'b11;
            end
            else begin
                fwdb = 2'b10;
            end
        end
    end
    
    always @(*) begin
        if (op == 6'b000000) begin
            if (func == 6'b100000) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0;
                aluimm <= 1'b0;
                aluc <= 4'b0010;
            end
            else if (func == 6'b100010) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0110;
            end
            else if (func == 6'b100100) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0000;
            end
            else if (func == 6'b100101) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0001;                
            end
            else if (func == 6'b100110) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0011;
            end
        end
  
        else if (op == 6'b100011) begin
            regrt <= 1'b1; 
            wreg <= 1'b1; 
            m2reg <= 1'b1; 
            wmem <= 1'b0; 
            aluimm <= 1'b1;
            aluc <= 4'b0010;
        end
    end
endmodule
module control_unit (op, func, rs, rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);

    input [5:0] op;
    input [5:0] func;
    input [4:0] rs;
    input [4:0] rt;
    input [4:0] mdestReg;
    input mm2reg, mwreg, edestReg, em2reg, ewreg;
    output reg regrt, wreg, m2reg, wmem, aluimm;
    output reg [3:0] aluc;
    output reg [31:0] fwda;
    output reg [31:0] fwdb;
    
    always @(*) begin
        fwda = 2'b00;
        fwdb = 2'b00;
        
        if (edestReg == rs) begin
            fwda = 2'b01;
        end
        
        if (edestReg == rt) begin
            fwdb = 2'b01;
        end
        
        if (mdestReg == rs) begin
            if (mm2reg == 1) begin
                fwda = 2'b11;
            end
            else begin
                fwda = 2'b10;
            end
        end
        
        if (mdestReg == rt) begin
            if (mm2reg == 1) begin
                fwdb = 2'b11;
            end
            else begin
                fwdb = 2'b10;
            end
        end
    end
    
    always @(*) begin
        if (op == 6'b000000) begin
            if (func == 6'b100000) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0;
                aluimm <= 1'b0;
                aluc <= 4'b0010;
            end
            else if (func == 6'b100010) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0110;
            end
            else if (func == 6'b100100) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0000;
            end
            else if (func == 6'b100101) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0001;                
            end
            else if (func == 6'b100110) begin
                regrt <= 1'b0; 
                wreg <= 1'b1; 
                m2reg <= 1'b0; 
                wmem <= 1'b0; 
                aluimm <= 1'b0;
                aluc <= 4'b0011;
            end
        end
  
        else if (op == 6'b100011) begin
            regrt <= 1'b1; 
            wreg <= 1'b1; 
            m2reg <= 1'b1; 
            wmem <= 1'b0; 
            aluimm <= 1'b1;
            aluc <= 4'b0010;
        end
    end
endmodule