data/full_repos/permissive/41195792/FPGA/Process.v
1: b'%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:54: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s VARREF \'key\' generates 4 bits.\n                                                                     : ... In instance Process\n      sex <= key;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:62: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'sex\' generates 26 bits.\n                                                                     : ... In instance Process\n   else if(key == 4\'hb && sex)\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:72: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'key\' generates 4 bits.\n                                                                     : ... In instance Process\n      age <= age*10+key;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:75: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'age\' generates 8 bits.\n                                                                     : ... In instance Process\n      if(age)\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:83: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'age\' generates 8 bits.\n                                                                     : ... In instance Process\n   else if(key == 4\'hb && age)\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:93: Operator ADD expects 32 or 26 bits on the RHS, but RHS\'s VARREF \'key\' generates 4 bits.\n                                                                     : ... In instance Process\n      height <= height*10+key;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:96: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'height\' generates 26 bits.\n                                                                     : ... In instance Process\n      if(height)\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:104: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'height\' generates 26 bits.\n                                                                      : ... In instance Process\n      else if(key == 4\'hb && height) \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:148: Operator DIV expects 32 or 26 bits on the RHS, but RHS\'s VARREF \'voltage\' generates 8 bits.\n                                                                      : ... In instance Process\n    TBW <= 1000 - ((height * current / voltage) /512 + sex * 4 + weight /4) * 100 /73;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:165: Operator ADD expects 32 or 26 bits on the RHS, but RHS\'s VARREF \'temp1\' generates 4 bits.\n                                                                      : ... In instance Process\n    weight <= temp3*100+temp2*10+temp1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:170: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'flash\' generates 11 bits.\n                                                                      : ... In instance Process\n   if(!flash)\n      ^\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:184: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'bit3\' generates 4 bits.\n                                                                      : ... In instance Process\n   else if(!(bit3 && bit2 && bit1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:184: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'bit2\' generates 4 bits.\n                                                                      : ... In instance Process\n   else if(!(bit3 && bit2 && bit1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:184: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'bit1\' generates 4 bits.\n                                                                      : ... In instance Process\n   else if(!(bit3 && bit2 && bit1))\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/41195792/FPGA/Process.v:174: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'count\' generates 11 bits.\n                                                                      : ... In instance Process\n       if(count)\n       ^~\n%Error: data/full_repos/permissive/41195792/FPGA/Process.v:206: Cannot find file containing module: \'BinToDec\'\nBinToDec b1(.Code(BMI[7:0]),.bit1(BMI1),.bit2(BMI2),.bit3(BMI3));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/41195792/FPGA,data/full_repos/permissive/41195792/BinToDec\n             data/full_repos/permissive/41195792/FPGA,data/full_repos/permissive/41195792/BinToDec.v\n             data/full_repos/permissive/41195792/FPGA,data/full_repos/permissive/41195792/BinToDec.sv\n             BinToDec\n             BinToDec.v\n             BinToDec.sv\n             obj_dir/BinToDec\n             obj_dir/BinToDec.v\n             obj_dir/BinToDec.sv\n%Error: data/full_repos/permissive/41195792/FPGA/Process.v:207: Cannot find file containing module: \'BinToDec\'\nBinToDec b2(.Code(TBW[7:0]),.bit1(TBW1),.bit2(TBW2),.bit3(TBW3));\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 15 warning(s)\n'
module Process
(  
   input Clock, press, reset, 
   input [7:0] voltage, current,
   input [3:0] key, bit1, bit2, bit3, 
	output reg [3:0] out0, out1, out2, out3,
	output reg dip
);

reg[7:0] age, vol, cur;
reg[3:0] temp0, temp1, temp2, temp3, dig0, dig1, dig2, dig3;
reg[1:0] state, setting;

reg[25:0] height, weight, BMI, TBW, sex;
reg[10:0] count, flash;

wire[3:0] BMI1, BMI2, BMI3, TBW1, TBW2, TBW3;

parameter
   Welcome = 2'b00,
   Set = 2'b01,
	Measure = 2'b10,
	Read = 2'b11;

parameter
	Ready = 2'b00,
   Sex = 2'b01,
	Age = 2'b10,
	Height = 2'b11;
	
always @(posedge press)
begin 
if(key == 4'hc)
	begin
	   setting <= Sex;
		{dig3, dig2, dig1, dig0} <= 16'b0101111111111111;
		age <= 0;
		sex <= 0;
		height <= 0;
	end
	else if(state == Set)
	begin
		if(setting == Sex)
		begin
			if(key == 1 || key == 2)
			begin
			   sex <= key;
				dig0 <= key;
			end
			else if(key == 4'ha)
			begin
				sex <= 0;
				dig0 <= 4'b1111;
			end
			else if(key == 4'hb && sex)
			begin
			   {dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
			   setting <= Age;
			end
		end
		else if(setting == Age)
		begin
			if(key < 10 && age < 15)
			begin
			   age <= age*10+key;
				dig0 <= key;
				dig2 = dig1;	
			   if(age)
					dig1 <= dig0;
			end
			else if(key == 4'ha)
			begin
			   age <= 0;
				{dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
			end
			else if(key == 4'hb && age)
			begin
			   setting <= Height;
		      {dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
			end
		end
		else if(setting == Height)
	   begin		
    		if(key < 10 && height < 25)
			begin
			   height <= height*10+key;
				dig0 <= key;
			   dig2 <= dig1;	
			   if(height)
					dig1 <= dig0;
			end
			else if(key == 4'ha)
			begin
			   height <= 0;
				{dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
			end
    		else if(key == 4'hb && height) 
			begin
			   height <= height * height;
			   setting <= Ready;
				{dig3, dig2, dig1, dig0} <= 16'b1001101110111101;
			end
      end
	end
end		
		
always @(posedge Clock)
begin
if(setting == Sex)
	begin
	   state <= Set;
		count <= 0;
		flash <= 0;
	end
	else
	begin
	   case(state)
		Set:
		   if(setting == Ready)
			begin
			   count <= count+1;
	         if(count == 250)
		      begin
		         state <= Measure;
			      count <= 0;
		      end
			end
			else
			   count <= 0;
		Measure:
		begin
		   if(count == 500)
		   begin
			   flash <= flash+1;
				BMI <= weight * 100000 / height;
				TBW <= 1000 - ((height * current / voltage) /512 + sex * 4 + weight /4) * 100 /73;
				if(flash == 500)
				begin
		         state <=	Read;
	            flash <= 750;  				
		         count <= 0;
				end
		   end
		   else
			begin
	         if(temp2 == bit2 && temp3 == bit3)
	            count <= count+1;
	         else
		         count <= 0;
		      temp1 <= bit1;
		      temp2 <= bit2;
		      temp3 <= bit3;
				weight <= temp3*100+temp2*10+temp1;
			end
	   end
		Read:
		begin
			if(!flash)
			   flash <= 750;
			else	
		      flash <= flash-1;
	      if(count)
			begin
	         count <= count+1;
	         if(count == 2000)
	         begin
		         state <= Measure;
					flash <= 0;
		         count <= 0;
		      end
	      end
			else if(!(bit3 && bit2 && bit1))
	         count <= count+1;
	   end
		default:
		begin

		end
		endcase
	end
end

BinToDec b1(.Code(BMI[7:0]),.bit1(BMI1),.bit2(BMI2),.bit3(BMI3));
BinToDec b2(.Code(TBW[7:0]),.bit1(TBW1),.bit2(TBW2),.bit3(TBW3));

always @(state or bit1 or bit2 or bit3 or flash)
begin
   case(state)

	Set:
	   begin
         {out3, out2, out1, out0} <= {dig3, dig2, dig1, dig0};
			dip <= 0;
		end
	Measure:
	   begin
		   dip <= 0;
	      if((flash>0 && flash<125) || (flash>250 && flash<375))
            {out3, out2, out1, out0} <= 16'b1111111111111111;
	      else
		      {out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
		end
	Read:
	   if(flash>500)
		begin
		   {out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
			dip <= 0;
		end
	   else if(flash>250)
		begin
		   {out3, out2, out1, out0} <= {4'b1111, BMI3, BMI2, BMI1};
			dip <= 1;
		end
		else		
		begin
         {out3, out2, out1, out0} <= {4'b1111, TBW3, TBW2, TBW1};
			dip <= 1;
		end
	endcase	 
end
		
endmodule
module Process
(  
   input Clock, press, reset, 
   input [7:0] voltage, current,
   input [3:0] key, bit1, bit2, bit3, 
	output reg [3:0] out0, out1, out2, out3,
	output reg dip
);


reg[7:0] age, vol, cur;
reg[3:0] temp0, temp1, temp2, temp3, dig0, dig1, dig2, dig3;
reg[1:0] state, setting;

reg[25:0] height, weight, BMI, TBW, sex;
reg[10:0] count, flash;

wire[3:0] BMI1, BMI2, BMI3, TBW1, TBW2, TBW3;

parameter
   Welcome = 2'b00,
   Set = 2'b01,
	Measure = 2'b10,
	Read = 2'b11;

parameter
	Ready = 2'b00,
   Sex = 2'b01,
	Age = 2'b10,
	Height = 2'b11;
	
always @(posedge press)
begin 
if(key == 4'hc)
	begin
	   setting <= Sex;
		{dig3, dig2, dig1, dig0} <= 16'b0101111111111111;
		age <= 0;
		sex <= 0;
		height <= 0;
	end
	else if(state == Set)
	begin
		if(setting == Sex)
		begin
			if(key == 1 || key == 2)
			begin
			   sex <= key;
				dig0 <= key;
			end
			else if(key == 4'ha)
			begin
				sex <= 0;
				dig0 <= 4'b1111;
			end
			else if(key == 4'hb && sex)
			begin
			   {dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
			   setting <= Age;
			end
		end
		else if(setting == Age)
		begin
			if(key < 10 && age < 15)
			begin
			   age <= age*10+key;
				dig0 <= key;
				dig2 = dig1;	
			   if(age)
					dig1 <= dig0;
			end
			else if(key == 4'ha)
			begin
			   age <= 0;
				{dig3, dig2, dig1, dig0} <= 16'b1010111111111111;
			end
			else if(key == 4'hb && age)
			begin
			   setting <= Height;
		      {dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
			end
		end
		else if(setting == Height)
	   begin		
    		if(key < 10 && height < 25)
			begin
			   height <= height*10+key;
				dig0 <= key;
			   dig2 <= dig1;	
			   if(height)
					dig1 <= dig0;
			end
			else if(key == 4'ha)
			begin
			   height <= 0;
				{dig3, dig2, dig1, dig0} <= 16'b1100111111111111;
			end
    		else if(key == 4'hb && height) 
			begin
			   height <= height * height;
			   setting <= Ready;
				{dig3, dig2, dig1, dig0} <= 16'b1001101110111101;
			end
      end
	end
end		
		
always @(posedge Clock)
begin
if(setting == Sex)
	begin
	   state <= Set;
		count <= 0;
		flash <= 0;
	end
	else
	begin
	   case(state)
		Set:
		   if(setting == Ready)
			begin
			   count <= count+1;
	         if(count == 250)
		      begin
		         state <= Measure;
			      count <= 0;
		      end
			end
			else
			   count <= 0;
		Measure:
		begin
		   if(count == 500)
		   begin
			   flash <= flash+1;
				BMI <= weight * 100000 / height;
				TBW <= 1000 - ((height * current / voltage) /512 + sex * 4 + weight /4) * 100 /73;
				if(flash == 500)
				begin
		         state <=	Read;
	            flash <= 750;  				
		         count <= 0;
				end
		   end
		   else
			begin
	         if(temp2 == bit2 && temp3 == bit3)
	            count <= count+1;
	         else
		         count <= 0;
		      temp1 <= bit1;
		      temp2 <= bit2;
		      temp3 <= bit3;
				weight <= temp3*100+temp2*10+temp1;
			end
	   end
		Read:
		begin
			if(!flash)
			   flash <= 750;
			else	
		      flash <= flash-1;
	      if(count)
			begin
	         count <= count+1;
	         if(count == 2000)
	         begin
		         state <= Measure;
					flash <= 0;
		         count <= 0;
		      end
	      end
			else if(!(bit3 && bit2 && bit1))
	         count <= count+1;
	   end
		default:
		begin

		end
		endcase
	end
end

BinToDec b1(.Code(BMI[7:0]),.bit1(BMI1),.bit2(BMI2),.bit3(BMI3));
BinToDec b2(.Code(TBW[7:0]),.bit1(TBW1),.bit2(TBW2),.bit3(TBW3));

always @(state or bit1 or bit2 or bit3 or flash)
begin
   case(state)

	Set:
	   begin
         {out3, out2, out1, out0} <= {dig3, dig2, dig1, dig0};
			dip <= 0;
		end
	Measure:
	   begin
		   dip <= 0;
	      if((flash>0 && flash<125) || (flash>250 && flash<375))
            {out3, out2, out1, out0} <= 16'b1111111111111111;
	      else
		      {out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
		end
	Read:
	   if(flash>500)
		begin
		   {out3, out2, out1, out0} <= {4'b1111, temp3, temp2, temp1};
			dip <= 0;
		end
	   else if(flash>250)
		begin
		   {out3, out2, out1, out0} <= {4'b1111, BMI3, BMI2, BMI1};
			dip <= 1;
		end
		else		
		begin
         {out3, out2, out1, out0} <= {4'b1111, TBW3, TBW2, TBW1};
			dip <= 1;
		end
	endcase	 
end
		
endmodule