data/full_repos/permissive/415843050/cpu-src/cp0.v
data/verilator_xmls/74730be4-d27f-4fa4-a847-1c892eeaa1e8.xml
module CP0(
    clock,reset,
    Cause_write,Cause_write_data,Cause_read_data,
    Status_write,Status_write_data,Status_read_data,
    EPC_write,EPC_write_data,EPC_read_data
    );
    
    input       clock;
    input       reset;
    
    input       Cause_write,Status_write,EPC_write;
    input[31:0] Cause_write_data,Status_write_data,EPC_write_data;
    output[31:0]    Cause_read_data,Status_read_data,EPC_read_data;
    
    reg[31:0]  cause,status,epc;
    
    
    

    assign Cause_read_data = cause;
    assign Status_read_data = status;
    assign EPC_read_data = epc;
    

    always @(negedge clock)
    begin
        if (reset)
        begin


            status <= 32'b0000_0000_0000_0000_111111_00_000_00_00_1;
            



            cause <= 32'b0000_0000_0000_0000_00_000000_0_000000_00;
            

            epc <= 32'h00000000;
        end
        else
        begin
            if (Status_write)
                status <= Status_write_data;
            if (Cause_write)
                cause <= Cause_write_data;
            if (EPC_write)
                epc <= EPC_write_data;
        end
    end
    
endmodule
module CP0(
    clock,reset,
    Cause_write,Cause_write_data,Cause_read_data,
    Status_write,Status_write_data,Status_read_data,
    EPC_write,EPC_write_data,EPC_read_data
    );

    
    input       clock;
    input       reset;
    
    input       Cause_write,Status_write,EPC_write;
    input[31:0] Cause_write_data,Status_write_data,EPC_write_data;
    output[31:0]    Cause_read_data,Status_read_data,EPC_read_data;
    
    reg[31:0]  cause,status,epc;
    
    
    

    assign Cause_read_data = cause;
    assign Status_read_data = status;
    assign EPC_read_data = epc;
    

    always @(negedge clock)
    begin
        if (reset)
        begin


            status <= 32'b0000_0000_0000_0000_111111_00_000_00_00_1;
            



            cause <= 32'b0000_0000_0000_0000_00_000000_0_000000_00;
            

            epc <= 32'h00000000;
        end
        else
        begin
            if (Status_write)
                status <= Status_write_data;
            if (Cause_write)
                cause <= Cause_write_data;
            if (EPC_write)
                epc <= EPC_write_data;
        end
    end
    
endmodule