data/full_repos/permissive/488739248/rtl/ttl/ttl_74164_sync.v
data/verilator_xmls/1a38a92f-39e0-43bd-9837-8c5dcfccfe62.xml
module ttl_74164_sync (
    input wire A, B,
    input wire Reset_n,
    input wire clk,

    input wire Cen,
    input wire MRn,
    output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
);
    wire serdata;
    assign serdata = A & B;
    reg last_cen;

    always @(posedge clk) begin
        if (!Reset_n) begin
            Q0 <= 1'b0;
            Q1 <= 1'b0;
            Q2 <= 1'b0;
            Q3 <= 1'b0;
            Q4 <= 1'b0;
            Q5 <= 1'b0;
            Q6 <= 1'b0;
            Q7 <= 1'b0;
            last_cen <= 1'b1;
        end else begin
            last_cen <= Cen;
            
            if (!MRn) begin
                Q0 <= 1'b0;
                Q1 <= 1'b0;
                Q2 <= 1'b0;
                Q3 <= 1'b0;
                Q4 <= 1'b0;
                Q5 <= 1'b0;
                Q6 <= 1'b0;
                Q7 <= 1'b0;
            end else if (Cen && !last_cen) begin
                Q0 <= serdata;
                Q1 <= Q0;
                Q2 <= Q1;
                Q3 <= Q2;
                Q4 <= Q3;
                Q5 <= Q4;
                Q6 <= Q5;
                Q7 <= Q6;
            end
        end
    end
endmodule
module ttl_74164_sync (
    input wire A, B,
    input wire Reset_n,
    input wire clk,

    input wire Cen,
    input wire MRn,
    output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
);

    wire serdata;
    assign serdata = A & B;
    reg last_cen;

    always @(posedge clk) begin
        if (!Reset_n) begin
            Q0 <= 1'b0;
            Q1 <= 1'b0;
            Q2 <= 1'b0;
            Q3 <= 1'b0;
            Q4 <= 1'b0;
            Q5 <= 1'b0;
            Q6 <= 1'b0;
            Q7 <= 1'b0;
            last_cen <= 1'b1;
        end else begin
            last_cen <= Cen;
            
            if (!MRn) begin
                Q0 <= 1'b0;
                Q1 <= 1'b0;
                Q2 <= 1'b0;
                Q3 <= 1'b0;
                Q4 <= 1'b0;
                Q5 <= 1'b0;
                Q6 <= 1'b0;
                Q7 <= 1'b0;
            end else if (Cen && !last_cen) begin
                Q0 <= serdata;
                Q1 <= Q0;
                Q2 <= Q1;
                Q3 <= Q2;
                Q4 <= Q3;
                Q5 <= Q4;
                Q6 <= Q5;
                Q7 <= Q6;
            end
        end
    end
endmodule