data/full_repos/permissive/474294847/rtl-src/arithmetic-logic/saturated-adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/474294847/rtl-src/arithmetic-logic/saturated-adder.v:21: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 9 bits.\n                                                                                                  : ... In instance saturated_adder\nassign c = (adder_tmp >= SATURATED_MAX) ? (SATURATED_MAX) : \n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module saturated_adder (a, b, c);

    parameter  WIDTH = 8;
    localparam SATURATED_MAX = (1 << WIDTH - 1) - 1;
    localparam SATURATED_MIN = -(1 << WIDTH - 1);
    input signed [WIDTH-1:0] a, b; 
    output signed [WIDTH-1:0] c;

reg signed [WIDTH:0] adder_tmp;

initial
begin
    adder_tmp = 0;
end

always@*
begin
    adder_tmp = a + b;
end

assign c = (adder_tmp >= SATURATED_MAX) ? (SATURATED_MAX) : 
    (adder_tmp <= SATURATED_MIN) ? (SATURATED_MIN) : 
        (adder_tmp);

endmodule
module saturated_adder (a, b, c);


    parameter  WIDTH = 8;
    localparam SATURATED_MAX = (1 << WIDTH - 1) - 1;
    localparam SATURATED_MIN = -(1 << WIDTH - 1);
    input signed [WIDTH-1:0] a, b; 
    output signed [WIDTH-1:0] c;

reg signed [WIDTH:0] adder_tmp;

initial
begin
    adder_tmp = 0;
end

always@*
begin
    adder_tmp = a + b;
end

assign c = (adder_tmp >= SATURATED_MAX) ? (SATURATED_MAX) : 
    (adder_tmp <= SATURATED_MIN) ? (SATURATED_MIN) : 
        (adder_tmp);

endmodule