data/full_repos/permissive/427221126/src/ShiftRegister.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ShiftRegister.v:165: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'ShiftRegSIPOnB\'\nmodule ShiftRegSIPOnB\n       ^~~~~~~~~~~~~~\n                                                                               : ... Top module \'ShiftRegPISO\'\nmodule ShiftRegPISO\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ShiftRegSIPOnB
  #(
    parameter INWIDTH = 16,
              DEPTH = 9,
              NUM_BANKS = 2
  )
  (
    input clk, 
    input reset,
    input en,
    input [INWIDTH-1:0] din,
    input               din_valid,
    input               bksh,
    output [INWIDTH*DEPTH-1:0] pout,
    output [INWIDTH-1:0]       casout
  );

  reg [INWIDTH-1:0] content [0:DEPTH-1][0:NUM_BANKS-1];
  genvar i, bb;

  generate
    for (i = 0; i < DEPTH; i = i + 1) begin : bank0
      always @(posedge clk) begin
        if (reset) begin
          content[i][0] <= 0;
        end
        else if (en) begin
          if (bksh) begin
            content[i][0] <= {INWIDTH{1'b0}};
          end
          else if (din_valid) begin
            if (i > 0)
              content[i][0] <= content[i-1][0];
            else
              content[i][0] <= din;
          end
        end
      end
    end
  endgenerate

  generate
    if (NUM_BANKS > 1) begin
      for (i = 0; i < DEPTH; i = i + 1) begin : bank1
        always @(posedge clk) begin
          if (reset == 1'b1) 
            content[i][1] <= {INWIDTH{1'b0}};
          else if (en)
            if (bksh) 
              if (!din_valid)
                content[i][1] <= content[i][0];
              else
                if (i == 0)
                  content[i][1] <= din;
                else
                  content[i][1] <= content[i-1][0];
        end
      end
      
      if (NUM_BANKS > 2) begin
        for (bb = 2; bb < NUM_BANKS; bb = bb + 1) begin : bank_n
          for (i = 0; i < DEPTH; i = i + 1) begin : elem
            always @(posedge clk) begin
              if (reset) 
                content[i][bb] <= {INWIDTH{1'b0}};
              else if (en) 
                if (bksh)
                  content[i][bb] <= content[i][bb-1];
            end
          end
        end
      end
    end
  endgenerate

  generate
    for (i = 0; i < DEPTH; i = i + 1) begin
      assign pout[INWIDTH*(i+1)-1:INWIDTH*i] = content[i][NUM_BANKS-1];
    end
  endgenerate

  assign casout = content[DEPTH-1][0];
endmodule
module ShiftRegSIPOnB
  #(
    parameter INWIDTH = 16,
              DEPTH = 9,
              NUM_BANKS = 2
  )
  (
    input clk, 
    input reset,
    input en,
    input [INWIDTH-1:0] din,
    input               din_valid,
    input               bksh,
    output [INWIDTH*DEPTH-1:0] pout,
    output [INWIDTH-1:0]       casout
  );


  reg [INWIDTH-1:0] content [0:DEPTH-1][0:NUM_BANKS-1];
  genvar i, bb;

  generate
    for (i = 0; i < DEPTH; i = i + 1) begin : bank0
      always @(posedge clk) begin
        if (reset) begin
          content[i][0] <= 0;
        end
        else if (en) begin
          if (bksh) begin
            content[i][0] <= {INWIDTH{1'b0}};
          end
          else if (din_valid) begin
            if (i > 0)
              content[i][0] <= content[i-1][0];
            else
              content[i][0] <= din;
          end
        end
      end
    end
  endgenerate

  generate
    if (NUM_BANKS > 1) begin
      for (i = 0; i < DEPTH; i = i + 1) begin : bank1
        always @(posedge clk) begin
          if (reset == 1'b1) 
            content[i][1] <= {INWIDTH{1'b0}};
          else if (en)
            if (bksh) 
              if (!din_valid)
                content[i][1] <= content[i][0];
              else
                if (i == 0)
                  content[i][1] <= din;
                else
                  content[i][1] <= content[i-1][0];
        end
      end
      
      if (NUM_BANKS > 2) begin
        for (bb = 2; bb < NUM_BANKS; bb = bb + 1) begin : bank_n
          for (i = 0; i < DEPTH; i = i + 1) begin : elem
            always @(posedge clk) begin
              if (reset) 
                content[i][bb] <= {INWIDTH{1'b0}};
              else if (en) 
                if (bksh)
                  content[i][bb] <= content[i][bb-1];
            end
          end
        end
      end
    end
  endgenerate

  generate
    for (i = 0; i < DEPTH; i = i + 1) begin
      assign pout[INWIDTH*(i+1)-1:INWIDTH*i] = content[i][NUM_BANKS-1];
    end
  endgenerate

  assign casout = content[DEPTH-1][0];
endmodule