data/full_repos/permissive/443770883/lab3/d.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/443770883/lab3/d.v:39: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'nand2\'\nmodule nand2(input wire i0, i1, output wire o5);\n       ^~~~~\n                                                                   : ... Top module \'fulladdR\'\nmodule fulladdR(input wire [3:0] a, b, input wire cin, output wire [3:0] sum, output wire cout);\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module fulladd(input wire a, b, cin, output wire sum, cout);
wire [4:0] t;
    xor2 x0(a, b, t[0]);
    xor2 x1(t[0], cin, sum);

    and2 a0(a, b, t[1]);
    and2 a1(a, cin, t[2]);
    and2 a2(b, cin, t[3]);

    or2 o0(t[1], t[2], t[4]);
    or2 o1(t[3], t[4], cout);
endmodule
module fulladd(input wire a, b, cin, output wire sum, cout);

wire [4:0] t;
    xor2 x0(a, b, t[0]);
    xor2 x1(t[0], cin, sum);

    and2 a0(a, b, t[1]);
    and2 a1(a, cin, t[2]);
    and2 a2(b, cin, t[3]);

    or2 o0(t[1], t[2], t[4]);
    or2 o1(t[3], t[4], cout);
endmodule