data/full_repos/permissive/488739248/rtl/ttl/ttl_74298_sync.v
1: b'%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74298_sync.v:5: Cannot find include file: helper.v\n`include "helper.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.sv\n             helper.v\n             helper.v.v\n             helper.v.sv\n             obj_dir/helper.v\n             obj_dir/helper.v.v\n             obj_dir/helper.v.sv\n%Error: Exiting due to 1 error(s)\n'
module SR_FF_sync
(
    input wire VIDEO_RSTn,
    input wire clk,
    input wire Cen,
    input wire S,
    input wire R,

    output wire Q,
    output wire Qn
);
	reg Qr;
    reg last_cen;
    
	always @(posedge clk) begin
        if(!VIDEO_RSTn) begin
            Qr <= 1'b0;
            last_cen <= 1'b1;
        end
        else
        begin
            last_cen <= Cen;

            if(!Cen && last_cen) begin
                case({S,R})
                    2'b00: Qr <= Qr;
                    2'b01: Qr <= 1'b0;
                    2'b10: Qr <= 1'b1;
                    2'b11: Qr <= 1'bx;
                endcase
            end
        end
    end
    assign Q  =  Qr;
    assign Qn = ~Qr;
endmodule
module SR_FF_sync
(
    input wire VIDEO_RSTn,
    input wire clk,
    input wire Cen,
    input wire S,
    input wire R,

    output wire Q,
    output wire Qn
);

	reg Qr;
    reg last_cen;
    
	always @(posedge clk) begin
        if(!VIDEO_RSTn) begin
            Qr <= 1'b0;
            last_cen <= 1'b1;
        end
        else
        begin
            last_cen <= Cen;

            if(!Cen && last_cen) begin
                case({S,R})
                    2'b00: Qr <= Qr;
                    2'b01: Qr <= 1'b0;
                    2'b10: Qr <= 1'b1;
                    2'b11: Qr <= 1'bx;
                endcase
            end
        end
    end
    assign Q  =  Qr;
    assign Qn = ~Qr;
endmodule