data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/qsecTicker_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/qsecTicker_sim.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #OFFSET\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/qsecTicker_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/qsecTicker_sim.v:28: Cannot find file containing module: \'qsecTicker\'\nqsecTicker UUT (.clk(clk), .frame(frame), .reset(reset), .qsec(qsec));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/qsecTicker\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/qsecTicker.v\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/qsecTicker.sv\n             qsecTicker\n             qsecTicker.v\n             qsecTicker.sv\n             obj_dir/qsecTicker\n             obj_dir/qsecTicker.v\n             obj_dir/qsecTicker.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module qsecTicker_sim();

reg clk, frame, reset;
wire qsec;

qsecTicker UUT (.clk(clk), .frame(frame), .reset(reset), .qsec(qsec));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
   frame = 1'b1;
   reset = 1'b0;
	end
endmodule
module qsecTicker_sim();


reg clk, frame, reset;
wire qsec;

qsecTicker UUT (.clk(clk), .frame(frame), .reset(reset), .qsec(qsec));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
   frame = 1'b1;
   reset = 1'b0;
	end
endmodule