data/full_repos/permissive/493441306/Verilog Language/more_verilog_features/00_conditional.v
1: b'%Error: Cannot find file containing module: Language/more_verilog_features,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             Language/more_verilog_features,data/full_repos/permissive/493441306\n             Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/more_verilog_features/00_conditional.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);


    wire [7:0] m1, m2;
    
    assign m1 = (a>b)?b:a;
    assign m2 = (m1>c)?c:m1;
    assign min = (m2>d)?d:m2;

endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);



    wire [7:0] m1, m2;
    
    assign m1 = (a>b)?b:a;
    assign m2 = (m1>c)?c:m1;
    assign min = (m2>d)?d:m2;

endmodule