data/full_repos/permissive/522240207/iiitb_bc.v
data/verilator_xmls/57201721-7e38-402f-9f49-3f4cea106494.xml
module iiitb_bc(
    Clk,
    reset,
    UpOrDown,
    Count
    );

    

    input Clk,reset,UpOrDown;

    output [3 : 0] Count;

    reg [3 : 0] Count = 0;  
    
     always @(posedge(Clk) or posedge(reset))
     begin
        if(reset == 1) 
            Count <= 0;
        else    
            if(UpOrDown == 1)
                if(Count == 15)
                    Count <= 0;
                else
                    Count <= Count + 1;
            else
                if(Count == 0)
                    Count <= 15;
                else
                    Count <= Count - 1;
     end    
    
endmodule
module iiitb_bc(
    Clk,
    reset,
    UpOrDown,
    Count
    );


    

    input Clk,reset,UpOrDown;

    output [3 : 0] Count;

    reg [3 : 0] Count = 0;  
    
     always @(posedge(Clk) or posedge(reset))
     begin
        if(reset == 1) 
            Count <= 0;
        else    
            if(UpOrDown == 1)
                if(Count == 15)
                    Count <= 0;
                else
                    Count <= Count + 1;
            else
                if(Count == 0)
                    Count <= 15;
                else
                    Count <= Count - 1;
     end    
    
endmodule