data/full_repos/permissive/458935738/common/minmax.v
data/verilator_xmls/a68231ec-d3e1-4b49-bbf7-f2b2d08cf73a.xml
module minmax8 (
    data0, data1, data2, data3,
    data4, data5, data6, data7,
    min, max
);
    parameter BIT_WIDTH = 16;

    input [BIT_WIDTH-1:0] data0, data1, data2, data3;
    input [BIT_WIDTH-1:0] data4, data5, data6, data7;
    output wire [BIT_WIDTH-1:0] min, max;

    wire [BIT_WIDTH-1:0] min0, min1, max0, max1;

    minmax4 #(BIT_WIDTH) comp1 (data0, data1, data2, data3, min0, max0);
    minmax4 #(BIT_WIDTH) comp2 (data4, data5, data6, data7, min1, max1);

    assign min = min0 < min1 ? min0 : min1;
    assign max = max0 > max1 ? max0 : max1;

endmodule
module minmax8 (
    data0, data1, data2, data3,
    data4, data5, data6, data7,
    min, max
);

    parameter BIT_WIDTH = 16;

    input [BIT_WIDTH-1:0] data0, data1, data2, data3;
    input [BIT_WIDTH-1:0] data4, data5, data6, data7;
    output wire [BIT_WIDTH-1:0] min, max;

    wire [BIT_WIDTH-1:0] min0, min1, max0, max1;

    minmax4 #(BIT_WIDTH) comp1 (data0, data1, data2, data3, min0, max0);
    minmax4 #(BIT_WIDTH) comp2 (data4, data5, data6, data7, min1, max1);

    assign min = min0 < min1 ? min0 : min1;
    assign max = max0 > max1 ? max0 : max1;

endmodule