data/full_repos/permissive/421450529/PC_beq.v
data/verilator_xmls/4a70d0a3-89d8-4422-9abb-f3bf81eeee9c.xml
module PC_b(
   input[31:0] Instr,
   input[31:0] after_ext,
	input[31:0] PC4_D,
	input equal,
	input g_or_e,
	input greater,
	output reg[31:0] pc_beq
    );


	   always@(*)begin
		  if((equal&&Instr[31:26]==6'b000100)||(~equal&&Instr[31:26]==6'b000101)||(~greater&&Instr[31:26]==6'b000110)||(greater&&Instr[31:26]==6'b000111)||(~g_or_e&&Instr[31:26]==6'b000001&&Instr[20:16]==5'b00000)||(g_or_e&&Instr[31:26]==6'b000001&&Instr[20:16]==5'b00001))begin
          pc_beq=PC4_D+(after_ext<<2);
		  end
		  else begin
		    pc_beq=PC4_D+4;
		  end
	  end
		 
endmodule
module PC_b(
   input[31:0] Instr,
   input[31:0] after_ext,
	input[31:0] PC4_D,
	input equal,
	input g_or_e,
	input greater,
	output reg[31:0] pc_beq
    );



	   always@(*)begin
		  if((equal&&Instr[31:26]==6'b000100)||(~equal&&Instr[31:26]==6'b000101)||(~greater&&Instr[31:26]==6'b000110)||(greater&&Instr[31:26]==6'b000111)||(~g_or_e&&Instr[31:26]==6'b000001&&Instr[20:16]==5'b00000)||(g_or_e&&Instr[31:26]==6'b000001&&Instr[20:16]==5'b00001))begin
          pc_beq=PC4_D+(after_ext<<2);
		  end
		  else begin
		    pc_beq=PC4_D+4;
		  end
	  end
		 
endmodule