data/full_repos/permissive/500326609/a6/alu32.v
1: b"%Error: data/full_repos/permissive/500326609/a6/alu32.v:9: Duplicate declaration of signal: 'rvout'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg rvout;\n        ^~~~~\n        data/full_repos/permissive/500326609/a6/alu32.v:5: ... Location of original declaration\n    output [31:0] rvout,   \n                  ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module alu32(
    input [5:0] op,
    input [31:0] rv1,
    input [31:0] rv2,
    output [31:0] rvout,
    output condition_out
);

    reg rvout;
    assign condition_out = (rvout == 0);
    always @(rv1 or rv2 or op) begin
      case(op[3:1])
        3'b000: rvout = (2'b11 == {op[4],op[0]}) ?  rv1 - rv2 : rv1 + rv2;
        3'b001: rvout = $signed(rv1) << $signed(rv2[4:0]);
        3'b010: rvout = ($signed(rv2) > $signed(rv1))?32'h1:32'h0;
        3'b011: rvout = (rv2>rv1)?32'h1:32'h0;
        3'b100: rvout = rv1 ^ rv2;
        3'b101: rvout = (op[0]) ? $signed(rv1) >>> $signed(rv2[4:0]):$signed(rv1) >> $signed(rv2[4:0]);
        3'b110: rvout = rv1 | rv2;
        3'b111: rvout = rv1 & rv2;
        default: rvout = 0;
      endcase
    end

endmodule
module alu32(
    input [5:0] op,
    input [31:0] rv1,
    input [31:0] rv2,
    output [31:0] rvout,
    output condition_out
);


    reg rvout;
    assign condition_out = (rvout == 0);
    always @(rv1 or rv2 or op) begin
      case(op[3:1])
        3'b000: rvout = (2'b11 == {op[4],op[0]}) ?  rv1 - rv2 : rv1 + rv2;
        3'b001: rvout = $signed(rv1) << $signed(rv2[4:0]);
        3'b010: rvout = ($signed(rv2) > $signed(rv1))?32'h1:32'h0;
        3'b011: rvout = (rv2>rv1)?32'h1:32'h0;
        3'b100: rvout = rv1 ^ rv2;
        3'b101: rvout = (op[0]) ? $signed(rv1) >>> $signed(rv2[4:0]):$signed(rv1) >> $signed(rv2[4:0]);
        3'b110: rvout = rv1 | rv2;
        3'b111: rvout = rv1 & rv2;
        default: rvout = 0;
      endcase
    end

endmodule