data/full_repos/permissive/459421171/Pipelined/execute_new.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:416: Little bit endian vector: MSB < LSB of bit range: 0:63\ninput[0:63] x,y;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:417: Little bit endian vector: MSB < LSB of bit range: 0:63\noutput[0:63]z;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module ADD(x,y,sum,OF);
input signed[63:0] x,y;
output signed[63:0] sum;
output signed OF;
wire signed[63:0] ci;

wire carry_in;
assign carry_in = 1'b0;


full_adder FA1(x[0],y[0],carry_in,sum[0],ci[0]);
genvar i;
generate
for(i=1;i<64;i=i+1) 
begin
full_adder FA0(x[i] , y[i] , ci[i-1] , sum[i] , ci[i]);
end
endgenerate

xor(OF,ci[62],ci[63]);

endmodule
module ADD(x,y,sum,OF);

input signed[63:0] x,y;
output signed[63:0] sum;
output signed OF;
wire signed[63:0] ci;

wire carry_in;
assign carry_in = 1'b0;


full_adder FA1(x[0],y[0],carry_in,sum[0],ci[0]);
genvar i;
generate
for(i=1;i<64;i=i+1) 
begin
full_adder FA0(x[i] , y[i] , ci[i-1] , sum[i] , ci[i]);
end
endgenerate

xor(OF,ci[62],ci[63]);

endmodule