data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array112x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array112x.v:28: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array112x.v:51: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0] do;      \n                   ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array112x.v:88: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    .q(do)\n       ^~\n%Error: Exiting due to 3 error(s)\n"
module array112x
    (
     rst,
     wclk,
     wa,
     we,
     di,
     rclk,
     ra,
     do
     );



parameter ADDRBIT = 5;
parameter DEPTH = 32;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";
parameter NUMCLK= 1;
parameter NCLK = 2;



input       rst;
input       wclk;
input [ADDRBIT-1:0] wa;
input            we;
input [WIDTH-1:0] di;
input             rclk;
input [ADDRBIT-1:0]  ra;
output [WIDTH-1:0] do;
reg [ADDRBIT-1:0]   cnt;
wire [ADDRBIT-1:0]  iwa;
wire                iwe;
wire [WIDTH-1:0]    idi;

generate
    if (MEM_RESET == "ON")
        begin: on_reset
always @(posedge wclk) cnt <= cnt + 1'b1;
assign iwa  = rst ? cnt : wa;
assign iwe  = rst ? 1'b1 : we;
assign idi  = rst ? {WIDTH{1'b0}} : di;
        end
    else
        begin: off_reset
assign iwa  = wa;
assign iwe  = we;
assign idi  = di;
        end
endgenerate

`ifdef  RTL_SIMULATION
wire [WIDTH-1:0] ido;
fflopx #(WIDTH) ppido (rclk,rst,ido,do);
wire   sameadd = (iwe & (iwa == ra));
wire   re = !sameadd;
iramrwpx #(ADDRBIT,DEPTH,WIDTH) array (wclk,iwa,iwe,idi,rclk,ra,re,ido,1'b0,1'b0);
`else
alsyncram112x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH,NUMCLK,NCLK) mem
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ra),
    .wrclock(wclk),
    .rdclock(rclk),
    .q(do)
    );
`endif
endmodule
module array112x
    (
     rst,
     wclk,
     wa,
     we,
     di,
     rclk,
     ra,
     do
     );




parameter ADDRBIT = 5;
parameter DEPTH = 32;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";
parameter NUMCLK= 1;
parameter NCLK = 2;



input       rst;
input       wclk;
input [ADDRBIT-1:0] wa;
input            we;
input [WIDTH-1:0] di;
input             rclk;
input [ADDRBIT-1:0]  ra;
output [WIDTH-1:0] do;
reg [ADDRBIT-1:0]   cnt;
wire [ADDRBIT-1:0]  iwa;
wire                iwe;
wire [WIDTH-1:0]    idi;

generate
    if (MEM_RESET == "ON")
        begin: on_reset
always @(posedge wclk) cnt <= cnt + 1'b1;
assign iwa  = rst ? cnt : wa;
assign iwe  = rst ? 1'b1 : we;
assign idi  = rst ? {WIDTH{1'b0}} : di;
        end
    else
        begin: off_reset
assign iwa  = wa;
assign iwe  = we;
assign idi  = di;
        end
endgenerate

`ifdef  RTL_SIMULATION
wire [WIDTH-1:0] ido;
fflopx #(WIDTH) ppido (rclk,rst,ido,do);
wire   sameadd = (iwe & (iwa == ra));
wire   re = !sameadd;
iramrwpx #(ADDRBIT,DEPTH,WIDTH) array (wclk,iwa,iwe,idi,rclk,ra,re,ido,1'b0,1'b0);
`else
alsyncram112x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH,NUMCLK,NCLK) mem
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ra),
    .wrclock(wclk),
    .rdclock(rclk),
    .q(do)
    );
`endif
endmodule