data/full_repos/permissive/433621701/generic_CB_array/generic_CB_array.v
data/verilator_xmls/fd06e278-bb93-4e8c-8afc-57a7fd90af91.xml
module tri_state(input a, enable, output reg out);
    always @(a or enable)
    begin
    if (enable == 0)
        out = 1'bz;        
    else
        out = a;
    end
endmodule
module tri_state(input a, enable, output reg out);

    always @(a or enable)
    begin
    if (enable == 0)
        out = 1'bz;        
    else
        out = a;
    end
endmodule