data/full_repos/permissive/467394306/rtl/sa_core.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/sa_core.sv:14: Little bit endian vector: MSB < LSB of bit range: 0:7\n    output [0 : ROWS-1] rvalidport);\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/rtl/sa_core.sv:26: Cannot find file containing module: \'PE_ARR\'\n    PE_ARR #(.ROWS(ROWS), .COLS(ROWS)) sysarr (.clk(clk), .rstn(rstn),\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/PE_ARR\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/PE_ARR.v\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/PE_ARR.sv\n             PE_ARR\n             PE_ARR.v\n             PE_ARR.sv\n             obj_dir/PE_ARR\n             obj_dir/PE_ARR.v\n             obj_dir/PE_ARR.sv\n%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/sa_core.sv:40: Little bit endian vector: MSB < LSB of bit range: 0:63\n    wire [0 : (ROWS*ROWS)-1] v_t;\n         ^\n%Error: data/full_repos/permissive/467394306/rtl/sa_core.sv:50: Cannot find file containing module: \'COL_OUTPUT_CTRL\'\n        COL_OUTPUT_CTRL output_ctrl(.clk(clk), .rstn(rstn),\n        ^~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/sa_core.sv:60: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0 : ROWS-1] aemptys, wemptys;\n         ^\n%Error: data/full_repos/permissive/467394306/rtl/sa_core.sv:67: Cannot find file containing module: \'CORE_INPUT_CTRL\'\n    CORE_INPUT_CTRL input_ctrl(.clk(clk), .rstn(rstn),\n    ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/467394306/rtl/sa_core.sv:87: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s NOT generates 8 bits.\n                                                                      : ... In instance SA_CORE\n                if (~aemptys && ~wemptys) begin\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/467394306/rtl/sa_core.sv:87: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 8 bits.\n                                                                      : ... In instance SA_CORE\n                if (~aemptys && ~wemptys) begin\n                             ^~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module SA_CORE #(
    parameter ROWS=8,
    parameter INWIDTH=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,

    input inpvalid,
    input outread,
    input [INWIDTH-1 : 0] ainport [0 : ROWS-1],
    input [INWIDTH-1 : 0] winport [0 : ROWS-1],
    output [OUTWIDTH-1 : 0] routport [0 : ROWS-1],
    output [0 : ROWS-1] rvalidport);




    reg fire;
    wire f_in;
    wire [INWIDTH-1 : 0] arr_w_in [0 : ROWS-1];
    wire [INWIDTH-1 : 0] arr_a_in [0 : ROWS-1];
    wire [OUTWIDTH-1 : 0] r_outs [0 : (ROWS*ROWS)-1];
    wire                 pe_valids [0 : (ROWS*ROWS)-1];

    PE_ARR #(.ROWS(ROWS), .COLS(ROWS)) sysarr (.clk(clk), .rstn(rstn),
        .fire(fire),
        .in_w(arr_w_in),
        .in_a(arr_a_in),
        .outs(r_outs),
        .outvalids(pe_valids));







    wire [OUTWIDTH-1 : 0] r_t [0 : (ROWS*ROWS)-1];
    wire [0 : (ROWS*ROWS)-1] v_t;
    genvar i, j;
    generate
    for (i=0; i<ROWS; i=i+1) begin
        for (j=0; j<ROWS; j=j+1) begin
            assign r_t[j + i*(ROWS)] = r_outs[i + j*ROWS];
            assign v_t[j + i*(ROWS)] = pe_valids[i + j*ROWS];
        end
    end
    for (i=0; i<ROWS; i=i+1) begin
        COL_OUTPUT_CTRL output_ctrl(.clk(clk), .rstn(rstn),
            .in_r(r_t[ROWS*i : ROWS*(i+1)-1]),
            .in_v(v_t[ROWS*i : ROWS*(i+1)-1]),
            .rread(outread),
            .out_r(routport[i]),
            .rvalid(rvalidport[i]));
    end
    endgenerate


    wire [0 : ROWS-1] aemptys, wemptys;
    wire inpwrite;
    wire inpread;
    assign inpread = fire;
    assign inpwrite = inpvalid;


    CORE_INPUT_CTRL input_ctrl(.clk(clk), .rstn(rstn),
        .ainport(ainport),
        .winport(winport),
        .write(inpwrite),
        .read(inpread),
        .aemptys(aemptys),
        .wemptys(wemptys),
        .ws(arr_w_in),
        .as(arr_a_in));




    reg start;
    always_ff @ (posedge clk) begin
        if (!rstn) begin
            fire <= 0;
            start <= 0;
        end else begin
            if (start) begin
                if (~aemptys && ~wemptys) begin

                    fire <= 1;
                end else begin

                    fire <= 0;
                    start <= 0;
                end
            end else begin

                if (inpvalid == 1) begin
                    start <= 1;
                end
            end
        end
    end

endmodule
module SA_CORE #(
    parameter ROWS=8,
    parameter INWIDTH=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,

    input inpvalid,
    input outread,
    input [INWIDTH-1 : 0] ainport [0 : ROWS-1],
    input [INWIDTH-1 : 0] winport [0 : ROWS-1],
    output [OUTWIDTH-1 : 0] routport [0 : ROWS-1],
    output [0 : ROWS-1] rvalidport);





    reg fire;
    wire f_in;
    wire [INWIDTH-1 : 0] arr_w_in [0 : ROWS-1];
    wire [INWIDTH-1 : 0] arr_a_in [0 : ROWS-1];
    wire [OUTWIDTH-1 : 0] r_outs [0 : (ROWS*ROWS)-1];
    wire                 pe_valids [0 : (ROWS*ROWS)-1];

    PE_ARR #(.ROWS(ROWS), .COLS(ROWS)) sysarr (.clk(clk), .rstn(rstn),
        .fire(fire),
        .in_w(arr_w_in),
        .in_a(arr_a_in),
        .outs(r_outs),
        .outvalids(pe_valids));







    wire [OUTWIDTH-1 : 0] r_t [0 : (ROWS*ROWS)-1];
    wire [0 : (ROWS*ROWS)-1] v_t;
    genvar i, j;
    generate
    for (i=0; i<ROWS; i=i+1) begin
        for (j=0; j<ROWS; j=j+1) begin
            assign r_t[j + i*(ROWS)] = r_outs[i + j*ROWS];
            assign v_t[j + i*(ROWS)] = pe_valids[i + j*ROWS];
        end
    end
    for (i=0; i<ROWS; i=i+1) begin
        COL_OUTPUT_CTRL output_ctrl(.clk(clk), .rstn(rstn),
            .in_r(r_t[ROWS*i : ROWS*(i+1)-1]),
            .in_v(v_t[ROWS*i : ROWS*(i+1)-1]),
            .rread(outread),
            .out_r(routport[i]),
            .rvalid(rvalidport[i]));
    end
    endgenerate


    wire [0 : ROWS-1] aemptys, wemptys;
    wire inpwrite;
    wire inpread;
    assign inpread = fire;
    assign inpwrite = inpvalid;


    CORE_INPUT_CTRL input_ctrl(.clk(clk), .rstn(rstn),
        .ainport(ainport),
        .winport(winport),
        .write(inpwrite),
        .read(inpread),
        .aemptys(aemptys),
        .wemptys(wemptys),
        .ws(arr_w_in),
        .as(arr_a_in));




    reg start;
    always_ff @ (posedge clk) begin
        if (!rstn) begin
            fire <= 0;
            start <= 0;
        end else begin
            if (start) begin
                if (~aemptys && ~wemptys) begin

                    fire <= 1;
                end else begin

                    fire <= 0;
                    start <= 0;
                end
            end else begin

                if (inpvalid == 1) begin
                    start <= 1;
                end
            end
        end
    end

endmodule