data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_backend_lut_fifo.v
1: b'%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_backend_lut_fifo.v:40: Cannot find include file: openGFX430_defines.v\n`include "openGFX430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.sv\n             openGFX430_defines.v\n             openGFX430_defines.v.v\n             openGFX430_defines.v.sv\n             obj_dir/openGFX430_defines.v\n             obj_dir/openGFX430_defines.v.v\n             obj_dir/openGFX430_defines.v.sv\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_backend_lut_fifo.v:443: Cannot find include file: openGFX430_undefines.v\n`include "openGFX430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module  ogfx_backend_lut_fifo (


    frame_data_request_o,

    refresh_data_o,
    refresh_data_ready_o,

`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_addr_o,
    lut_ram_cen_o,
`endif


    mclk,
    puc_rst,

    frame_data_i,
    frame_data_ready_i,

    gfx_mode_i,

`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_dout_i,
    lut_ram_dout_rdy_nxt_i,
`endif

    refresh_active_i,
    refresh_data_request_i,

    hw_lut_palette_sel_i,
    hw_lut_bgcolor_i,
    hw_lut_fgcolor_i,
    sw_lut_enable_i,
    sw_lut_bank_select_i
);



output               frame_data_request_o;

output        [15:0] refresh_data_o;
output               refresh_data_ready_o;

`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o;
output               lut_ram_cen_o;
`endif



input                mclk;
input                puc_rst;

input         [15:0] frame_data_i;
input                frame_data_ready_i;

input          [2:0] gfx_mode_i;

`ifdef WITH_PROGRAMMABLE_LUT
input         [15:0] lut_ram_dout_i;
input                lut_ram_dout_rdy_nxt_i;
`endif

input                refresh_active_i;
input                refresh_data_request_i;

input          [2:0] hw_lut_palette_sel_i;
input          [3:0] hw_lut_bgcolor_i;
input          [3:0] hw_lut_fgcolor_i;
input                sw_lut_enable_i;
input                sw_lut_bank_select_i;







reg    [1:0] lut_state;
reg    [1:0] lut_state_nxt;


parameter    STATE_IDLE        =   0,
             STATE_FRAME_DATA  =   1,
             STATE_LUT_DATA    =   2,
             STATE_HOLD        =   3;


parameter    FIFO_EMPTY        =  3'h0,
             FIFO_FULL         =  3'h5;


wire         gfx_mode_1_bpp    =  (gfx_mode_i == 3'b000);
wire         gfx_mode_2_bpp    =  (gfx_mode_i == 3'b001);
wire         gfx_mode_4_bpp    =  (gfx_mode_i == 3'b010);
wire         gfx_mode_8_bpp    =  (gfx_mode_i == 3'b011);
wire         gfx_mode_16_bpp   = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
                                   gfx_mode_2_bpp | gfx_mode_1_bpp);


reg    [2:0] fifo_counter;
wire   [2:0] fifo_counter_nxt;







parameter [3:0] CGA_BLACK         = 4'h0,
                CGA_BLUE          = 4'h1,
                CGA_GREEN         = 4'h2,
                CGA_CYAN          = 4'h3,
                CGA_RED           = 4'h4,
                CGA_MAGENTA       = 4'h5,
                CGA_BROWN         = 4'h6,
                CGA_LIGHT_GRAY    = 4'h7,
                CGA_GRAY          = 4'h8,
                CGA_LIGHT_BLUE    = 4'h9,
                CGA_LIGHT_GREEN   = 4'hA,
                CGA_LIGHT_CYAN    = 4'hB,
                CGA_LIGHT_RED     = 4'hC,
                CGA_LIGHT_MAGENTA = 4'hD,
                CGA_YELLOW        = 4'hE,
                CGA_WHITE         = 4'hF;


wire         cga_palette0_hi   = (hw_lut_palette_sel_i==3'h0);
wire         cga_palette0_lo   = (hw_lut_palette_sel_i==3'h1);
wire         cga_palette1_hi   = (hw_lut_palette_sel_i==3'h2);
wire         cga_palette1_lo   = (hw_lut_palette_sel_i==3'h3);
wire         cga_palette2_hi   = (hw_lut_palette_sel_i==3'h4);
wire         cga_palette2_lo   = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);



wire   [3:0] lut_hw_sel_1bpp   = ({4{gfx_mode_1_bpp                   & (frame_data_i[0]  ==1'b0 )}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_1_bpp                   & (frame_data_i[0]  ==1'b1 )}} & hw_lut_fgcolor_i ) ;


wire   [3:0] lut_hw_sel_2bpp   = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN        ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED          ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN        ) |


                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN  ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED    ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW       ) |


                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN         ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA      ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY   ) |


                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN   ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE        ) |


                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN         ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED          ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY   ) |


                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN   ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED    ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE        ) ;


wire   [3:0] lut_hw_sel_4bpp   = ({4{gfx_mode_4_bpp}}                 &  frame_data_i[3:0]);

wire   [3:0] lut_hw_color_sel  =  lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;


reg   [15:0] lut_hw_data_1_2_4_bpp;
always @(lut_hw_color_sel)
  case(lut_hw_color_sel)
    CGA_BLACK         :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b000000, 5'b00000};
    CGA_BLUE          :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b000000, 5'b10101};
    CGA_GREEN         :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b101011, 5'b00000};
    CGA_CYAN          :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b101011, 5'b10101};
    CGA_RED           :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b000000, 5'b00000};
    CGA_MAGENTA       :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b000000, 5'b10101};
    CGA_BROWN         :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b010101, 5'b00000};
    CGA_LIGHT_GRAY    :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b101011, 5'b10101};
    CGA_GRAY          :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b010101, 5'b01011};
    CGA_LIGHT_BLUE    :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b010101, 5'b11111};
    CGA_LIGHT_GREEN   :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b111111, 5'b01011};
    CGA_LIGHT_CYAN    :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b111111, 5'b11111};
    CGA_LIGHT_RED     :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b010101, 5'b01011};
    CGA_LIGHT_MAGENTA :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b010101, 5'b11111};
    CGA_YELLOW        :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b111111, 5'b01011};
    CGA_WHITE         :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b111111, 5'b11111};

    default           :  lut_hw_data_1_2_4_bpp  =  16'h0000;

  endcase


wire  [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5],
                                  frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2],
                                  frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]};

wire  [15:0] lut_hw_data       = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
                                 (lut_hw_data_8_bpp     & {16{gfx_mode_8_bpp}});

wire         lut_hw_enabled    = ~gfx_mode_16_bpp   & ~sw_lut_enable_i;
wire         lut_sw_enabled    = ~gfx_mode_16_bpp   &  sw_lut_enable_i;









always @(lut_state or refresh_active_i or frame_data_ready_i     or
`ifdef WITH_PROGRAMMABLE_LUT
                      lut_sw_enabled   or lut_ram_dout_rdy_nxt_i or
`endif
                      fifo_counter_nxt)
    case(lut_state)

      STATE_IDLE           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       : STATE_FRAME_DATA ;

      STATE_FRAME_DATA     :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              ~frame_data_ready_i           ? STATE_FRAME_DATA :
`ifdef WITH_PROGRAMMABLE_LUT
                                               lut_sw_enabled               ? STATE_LUT_DATA   :
`endif
                                                                                                 STATE_HOLD       ;

`ifdef WITH_PROGRAMMABLE_LUT
      STATE_LUT_DATA       :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                               lut_ram_dout_rdy_nxt_i       ? STATE_HOLD       : STATE_LUT_DATA   ;
`endif

      STATE_HOLD           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              (fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD       ;


      default              :  lut_state_nxt =  STATE_IDLE;

    endcase




always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_state  <= STATE_IDLE;
  else         lut_state  <= lut_state_nxt;



assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);









`ifdef WITH_PROGRAMMABLE_LUT
   assign lut_ram_cen_o  = ~(lut_state == STATE_LUT_DATA);
`endif






`ifdef WITH_PROGRAMMABLE_LUT
  `ifdef WITH_EXTRA_LUT_BANK

    reg refresh_lut_bank_select_sync;
    always @(posedge mclk or posedge puc_rst)
      if (puc_rst)                refresh_lut_bank_select_sync  <=  1'b0;
      else if (~refresh_active_i) refresh_lut_bank_select_sync  <=  sw_lut_bank_select_i;

    assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
  `else
    assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
  `endif
`endif






reg            lut_ram_dout_ready;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_ram_dout_ready  <=  1'b0;
`ifdef WITH_PROGRAMMABLE_LUT
  else         lut_ram_dout_ready  <=  lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
                                                        (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`else
  else         lut_ram_dout_ready  <=  (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`endif







wire      fifo_push =  lut_ram_dout_ready     & (fifo_counter != FIFO_FULL);
wire      fifo_pop  =  refresh_data_request_i & (fifo_counter != FIFO_EMPTY);


assign fifo_counter_nxt = ~refresh_active_i      ?  FIFO_EMPTY          :
                          (fifo_push & fifo_pop) ?  fifo_counter        :
                           fifo_push             ?  fifo_counter + 3'h1 :
                           fifo_pop              ?  fifo_counter - 3'h1 :
                                                    fifo_counter;

always @(posedge mclk or posedge puc_rst)
  if (puc_rst) fifo_counter <= FIFO_EMPTY;
  else         fifo_counter <= fifo_counter_nxt;







reg [2:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    wr_ptr  <=  3'h0;
  else if (~refresh_active_i)     wr_ptr  <=  3'h0;
  else if (fifo_push)
    begin
       if (wr_ptr==(FIFO_FULL-1)) wr_ptr  <=  3'h0;
       else                       wr_ptr  <=  wr_ptr + 3'h1;
    end


reg [15:0] fifo_mem [0:4];
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)
    begin
       fifo_mem[0]      <=  16'h0000;
       fifo_mem[1]      <=  16'h0000;
       fifo_mem[2]      <=  16'h0000;
       fifo_mem[3]      <=  16'h0000;
       fifo_mem[4]      <=  16'h0000;
    end
  else if (fifo_push)
    begin
       fifo_mem[wr_ptr] <=  lut_hw_enabled ? lut_hw_data    :
`ifdef WITH_PROGRAMMABLE_LUT
                            lut_sw_enabled ? lut_ram_dout_i :
`endif
                                             frame_data_i;
    end


reg [2:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    rd_ptr  <=  3'h0;
  else if (~refresh_active_i)     rd_ptr  <=  3'h0;
  else if (fifo_pop)
    begin
       if (rd_ptr==(FIFO_FULL-1)) rd_ptr  <=  3'h0;
       else                       rd_ptr  <=  rd_ptr + 3'h1;
    end






reg        refresh_data_ready_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_ready_o <=  1'h0;
  else if (~refresh_active_i) refresh_data_ready_o <=  1'h0;
  else                        refresh_data_ready_o <=  fifo_pop;


reg [15:0] refresh_data_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_o <= 16'h0000;
  else if (fifo_pop)          refresh_data_o <= fifo_mem[rd_ptr];


endmodule
module  ogfx_backend_lut_fifo (


    frame_data_request_o,

    refresh_data_o,
    refresh_data_ready_o,

`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_addr_o,
    lut_ram_cen_o,
`endif


    mclk,
    puc_rst,

    frame_data_i,
    frame_data_ready_i,

    gfx_mode_i,

`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_dout_i,
    lut_ram_dout_rdy_nxt_i,
`endif

    refresh_active_i,
    refresh_data_request_i,

    hw_lut_palette_sel_i,
    hw_lut_bgcolor_i,
    hw_lut_fgcolor_i,
    sw_lut_enable_i,
    sw_lut_bank_select_i
);




output               frame_data_request_o;

output        [15:0] refresh_data_o;
output               refresh_data_ready_o;

`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o;
output               lut_ram_cen_o;
`endif



input                mclk;
input                puc_rst;

input         [15:0] frame_data_i;
input                frame_data_ready_i;

input          [2:0] gfx_mode_i;

`ifdef WITH_PROGRAMMABLE_LUT
input         [15:0] lut_ram_dout_i;
input                lut_ram_dout_rdy_nxt_i;
`endif

input                refresh_active_i;
input                refresh_data_request_i;

input          [2:0] hw_lut_palette_sel_i;
input          [3:0] hw_lut_bgcolor_i;
input          [3:0] hw_lut_fgcolor_i;
input                sw_lut_enable_i;
input                sw_lut_bank_select_i;







reg    [1:0] lut_state;
reg    [1:0] lut_state_nxt;


parameter    STATE_IDLE        =   0,
             STATE_FRAME_DATA  =   1,
             STATE_LUT_DATA    =   2,
             STATE_HOLD        =   3;


parameter    FIFO_EMPTY        =  3'h0,
             FIFO_FULL         =  3'h5;


wire         gfx_mode_1_bpp    =  (gfx_mode_i == 3'b000);
wire         gfx_mode_2_bpp    =  (gfx_mode_i == 3'b001);
wire         gfx_mode_4_bpp    =  (gfx_mode_i == 3'b010);
wire         gfx_mode_8_bpp    =  (gfx_mode_i == 3'b011);
wire         gfx_mode_16_bpp   = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
                                   gfx_mode_2_bpp | gfx_mode_1_bpp);


reg    [2:0] fifo_counter;
wire   [2:0] fifo_counter_nxt;







parameter [3:0] CGA_BLACK         = 4'h0,
                CGA_BLUE          = 4'h1,
                CGA_GREEN         = 4'h2,
                CGA_CYAN          = 4'h3,
                CGA_RED           = 4'h4,
                CGA_MAGENTA       = 4'h5,
                CGA_BROWN         = 4'h6,
                CGA_LIGHT_GRAY    = 4'h7,
                CGA_GRAY          = 4'h8,
                CGA_LIGHT_BLUE    = 4'h9,
                CGA_LIGHT_GREEN   = 4'hA,
                CGA_LIGHT_CYAN    = 4'hB,
                CGA_LIGHT_RED     = 4'hC,
                CGA_LIGHT_MAGENTA = 4'hD,
                CGA_YELLOW        = 4'hE,
                CGA_WHITE         = 4'hF;


wire         cga_palette0_hi   = (hw_lut_palette_sel_i==3'h0);
wire         cga_palette0_lo   = (hw_lut_palette_sel_i==3'h1);
wire         cga_palette1_hi   = (hw_lut_palette_sel_i==3'h2);
wire         cga_palette1_lo   = (hw_lut_palette_sel_i==3'h3);
wire         cga_palette2_hi   = (hw_lut_palette_sel_i==3'h4);
wire         cga_palette2_lo   = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);



wire   [3:0] lut_hw_sel_1bpp   = ({4{gfx_mode_1_bpp                   & (frame_data_i[0]  ==1'b0 )}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_1_bpp                   & (frame_data_i[0]  ==1'b1 )}} & hw_lut_fgcolor_i ) ;


wire   [3:0] lut_hw_sel_2bpp   = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN        ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED          ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN        ) |


                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN  ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED    ) |
                                 ({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW       ) |


                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN         ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA      ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY   ) |


                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN   ) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) |
                                 ({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE        ) |


                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN         ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED          ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY   ) |


                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN   ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED    ) |
                                 ({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE        ) ;


wire   [3:0] lut_hw_sel_4bpp   = ({4{gfx_mode_4_bpp}}                 &  frame_data_i[3:0]);

wire   [3:0] lut_hw_color_sel  =  lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;


reg   [15:0] lut_hw_data_1_2_4_bpp;
always @(lut_hw_color_sel)
  case(lut_hw_color_sel)
    CGA_BLACK         :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b000000, 5'b00000};
    CGA_BLUE          :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b000000, 5'b10101};
    CGA_GREEN         :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b101011, 5'b00000};
    CGA_CYAN          :  lut_hw_data_1_2_4_bpp  =  {5'b00000, 6'b101011, 5'b10101};
    CGA_RED           :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b000000, 5'b00000};
    CGA_MAGENTA       :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b000000, 5'b10101};
    CGA_BROWN         :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b010101, 5'b00000};
    CGA_LIGHT_GRAY    :  lut_hw_data_1_2_4_bpp  =  {5'b10101, 6'b101011, 5'b10101};
    CGA_GRAY          :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b010101, 5'b01011};
    CGA_LIGHT_BLUE    :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b010101, 5'b11111};
    CGA_LIGHT_GREEN   :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b111111, 5'b01011};
    CGA_LIGHT_CYAN    :  lut_hw_data_1_2_4_bpp  =  {5'b01011, 6'b111111, 5'b11111};
    CGA_LIGHT_RED     :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b010101, 5'b01011};
    CGA_LIGHT_MAGENTA :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b010101, 5'b11111};
    CGA_YELLOW        :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b111111, 5'b01011};
    CGA_WHITE         :  lut_hw_data_1_2_4_bpp  =  {5'b11111, 6'b111111, 5'b11111};

    default           :  lut_hw_data_1_2_4_bpp  =  16'h0000;

  endcase


wire  [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5],
                                  frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2],
                                  frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]};

wire  [15:0] lut_hw_data       = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
                                 (lut_hw_data_8_bpp     & {16{gfx_mode_8_bpp}});

wire         lut_hw_enabled    = ~gfx_mode_16_bpp   & ~sw_lut_enable_i;
wire         lut_sw_enabled    = ~gfx_mode_16_bpp   &  sw_lut_enable_i;









always @(lut_state or refresh_active_i or frame_data_ready_i     or
`ifdef WITH_PROGRAMMABLE_LUT
                      lut_sw_enabled   or lut_ram_dout_rdy_nxt_i or
`endif
                      fifo_counter_nxt)
    case(lut_state)

      STATE_IDLE           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       : STATE_FRAME_DATA ;

      STATE_FRAME_DATA     :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              ~frame_data_ready_i           ? STATE_FRAME_DATA :
`ifdef WITH_PROGRAMMABLE_LUT
                                               lut_sw_enabled               ? STATE_LUT_DATA   :
`endif
                                                                                                 STATE_HOLD       ;

`ifdef WITH_PROGRAMMABLE_LUT
      STATE_LUT_DATA       :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                               lut_ram_dout_rdy_nxt_i       ? STATE_HOLD       : STATE_LUT_DATA   ;
`endif

      STATE_HOLD           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              (fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD       ;


      default              :  lut_state_nxt =  STATE_IDLE;

    endcase




always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_state  <= STATE_IDLE;
  else         lut_state  <= lut_state_nxt;



assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);









`ifdef WITH_PROGRAMMABLE_LUT
   assign lut_ram_cen_o  = ~(lut_state == STATE_LUT_DATA);
`endif






`ifdef WITH_PROGRAMMABLE_LUT
  `ifdef WITH_EXTRA_LUT_BANK

    reg refresh_lut_bank_select_sync;
    always @(posedge mclk or posedge puc_rst)
      if (puc_rst)                refresh_lut_bank_select_sync  <=  1'b0;
      else if (~refresh_active_i) refresh_lut_bank_select_sync  <=  sw_lut_bank_select_i;

    assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
  `else
    assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
  `endif
`endif






reg            lut_ram_dout_ready;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_ram_dout_ready  <=  1'b0;
`ifdef WITH_PROGRAMMABLE_LUT
  else         lut_ram_dout_ready  <=  lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
                                                        (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`else
  else         lut_ram_dout_ready  <=  (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`endif







wire      fifo_push =  lut_ram_dout_ready     & (fifo_counter != FIFO_FULL);
wire      fifo_pop  =  refresh_data_request_i & (fifo_counter != FIFO_EMPTY);


assign fifo_counter_nxt = ~refresh_active_i      ?  FIFO_EMPTY          :
                          (fifo_push & fifo_pop) ?  fifo_counter        :
                           fifo_push             ?  fifo_counter + 3'h1 :
                           fifo_pop              ?  fifo_counter - 3'h1 :
                                                    fifo_counter;

always @(posedge mclk or posedge puc_rst)
  if (puc_rst) fifo_counter <= FIFO_EMPTY;
  else         fifo_counter <= fifo_counter_nxt;







reg [2:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    wr_ptr  <=  3'h0;
  else if (~refresh_active_i)     wr_ptr  <=  3'h0;
  else if (fifo_push)
    begin
       if (wr_ptr==(FIFO_FULL-1)) wr_ptr  <=  3'h0;
       else                       wr_ptr  <=  wr_ptr + 3'h1;
    end


reg [15:0] fifo_mem [0:4];
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)
    begin
       fifo_mem[0]      <=  16'h0000;
       fifo_mem[1]      <=  16'h0000;
       fifo_mem[2]      <=  16'h0000;
       fifo_mem[3]      <=  16'h0000;
       fifo_mem[4]      <=  16'h0000;
    end
  else if (fifo_push)
    begin
       fifo_mem[wr_ptr] <=  lut_hw_enabled ? lut_hw_data    :
`ifdef WITH_PROGRAMMABLE_LUT
                            lut_sw_enabled ? lut_ram_dout_i :
`endif
                                             frame_data_i;
    end


reg [2:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    rd_ptr  <=  3'h0;
  else if (~refresh_active_i)     rd_ptr  <=  3'h0;
  else if (fifo_pop)
    begin
       if (rd_ptr==(FIFO_FULL-1)) rd_ptr  <=  3'h0;
       else                       rd_ptr  <=  rd_ptr + 3'h1;
    end






reg        refresh_data_ready_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_ready_o <=  1'h0;
  else if (~refresh_active_i) refresh_data_ready_o <=  1'h0;
  else                        refresh_data_ready_o <=  fifo_pop;


reg [15:0] refresh_data_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_o <= 16'h0000;
  else if (fifo_pop)          refresh_data_o <= fifo_mem[rd_ptr];


endmodule