data/full_repos/permissive/470392519/rtl/Execute.v
1: b'%Error: data/full_repos/permissive/470392519/rtl/Execute.v:1: Cannot find include file: types.vh\n`include "types.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.v\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.sv\n             types.vh\n             types.vh.v\n             types.vh.sv\n             obj_dir/types.vh\n             obj_dir/types.vh.v\n             obj_dir/types.vh.sv\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:19: Define or directive not defined: \'`NO_FWD\'\n            `NO_FWD         : rs1Out = i_EXEC_rs1;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:19: syntax error, unexpected \':\', expecting endcase\n            `NO_FWD         : rs1Out = i_EXEC_rs1;\n                            ^\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:20: Define or directive not defined: \'`FWD_MEM\'\n            `FWD_MEM        : rs1Out = i_MEM_rd;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:21: Define or directive not defined: \'`FWD_WB\'\n            `FWD_WB         : rs1Out = i_WB_rd;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:25: Define or directive not defined: \'`NO_FWD\'\n            `NO_FWD         : rs2Out = i_EXEC_rs2;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:26: Define or directive not defined: \'`FWD_MEM\'\n            `FWD_MEM        : rs2Out = i_MEM_rd;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:27: Define or directive not defined: \'`FWD_WB\'\n            `FWD_WB         : rs2Out = i_WB_rd;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:33: Define or directive not defined: \'`PC\'\n    wire [31:0] aluSrcAin = (i_aluSrcA == `PC ) ? i_PC  : rs1Out;\n                                          ^~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:34: Define or directive not defined: \'`IMM\'\n    wire [31:0] aluSrcBin = (i_aluSrcB == `IMM) ? i_IMM : rs2Out;\n                                          ^~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:51: Define or directive not defined: \'`ALU_OP_I_JUMP\'\n    wire indirJump = `ALU_OP_I_JUMP == i_aluOp;  \n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/Execute.v:58: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module Execute (
    input   [6:0]   i_funct7,
    input   [2:0]   i_funct3,
    input   [3:0]   i_aluOp,
    input   [1:0]   i_fwdRs1, i_fwdRs2,
    input           i_aluSrcA, i_aluSrcB,
    input   [31:0]  i_EXEC_rs1, i_EXEC_rs2, i_MEM_rd, i_WB_rd,
    input   [31:0]  i_PC, i_IMM,
    output  [31:0]  o_aluOut, o_addrGenOut, o_rs2FwdOut
);
    parameter XLEN = 32;


    reg [31:0] rs1Out, rs2Out;
    always@(*) begin
        case (i_fwdRs1)
            `NO_FWD         : rs1Out = i_EXEC_rs1;
            `FWD_MEM        : rs1Out = i_MEM_rd;
            `FWD_WB         : rs1Out = i_WB_rd;
            default         : rs1Out = i_EXEC_rs1;
        endcase
        case (i_fwdRs2)
            `NO_FWD         : rs2Out = i_EXEC_rs2;
            `FWD_MEM        : rs2Out = i_MEM_rd;
            `FWD_WB         : rs2Out = i_WB_rd;
            default         : rs2Out = i_EXEC_rs2;
        endcase
    end


    wire [31:0] aluSrcAin = (i_aluSrcA == `PC ) ? i_PC  : rs1Out;
    wire [31:0] aluSrcBin = (i_aluSrcB == `IMM) ? i_IMM : rs2Out;


    wire [4:0]  aluControl;
    ALU_Control ALU_CTRL_unit (
        .i_aluOp        (i_aluOp),
        .i_funct7       (i_funct7),
        .i_funct3       (i_funct3),
        .o_aluControl   (aluControl)
    );
    ALU #(.XLEN(XLEN)) alu_unit (
        .i_a      (aluSrcAin),
        .i_b      (aluSrcBin),
        .i_op     (aluControl),
        .o_result (o_aluOut)
    );

    wire indirJump = `ALU_OP_I_JUMP == i_aluOp;
    wire [XLEN-1:0] ctrlTransSrcA = indirJump ? rs1Out : i_PC;
    wire [XLEN-1:0] jmpResult = ctrlTransSrcA + i_IMM;

    assign o_addrGenOut = indirJump ? {jmpResult[XLEN-1:1],1'b0} : jmpResult;
    assign o_rs2FwdOut  = rs2Out;

endmodule
module Execute (
    input   [6:0]   i_funct7,
    input   [2:0]   i_funct3,
    input   [3:0]   i_aluOp,
    input   [1:0]   i_fwdRs1, i_fwdRs2,
    input           i_aluSrcA, i_aluSrcB,
    input   [31:0]  i_EXEC_rs1, i_EXEC_rs2, i_MEM_rd, i_WB_rd,
    input   [31:0]  i_PC, i_IMM,
    output  [31:0]  o_aluOut, o_addrGenOut, o_rs2FwdOut
);

    parameter XLEN = 32;


    reg [31:0] rs1Out, rs2Out;
    always@(*) begin
        case (i_fwdRs1)
            `NO_FWD         : rs1Out = i_EXEC_rs1;
            `FWD_MEM        : rs1Out = i_MEM_rd;
            `FWD_WB         : rs1Out = i_WB_rd;
            default         : rs1Out = i_EXEC_rs1;
        endcase
        case (i_fwdRs2)
            `NO_FWD         : rs2Out = i_EXEC_rs2;
            `FWD_MEM        : rs2Out = i_MEM_rd;
            `FWD_WB         : rs2Out = i_WB_rd;
            default         : rs2Out = i_EXEC_rs2;
        endcase
    end


    wire [31:0] aluSrcAin = (i_aluSrcA == `PC ) ? i_PC  : rs1Out;
    wire [31:0] aluSrcBin = (i_aluSrcB == `IMM) ? i_IMM : rs2Out;


    wire [4:0]  aluControl;
    ALU_Control ALU_CTRL_unit (
        .i_aluOp        (i_aluOp),
        .i_funct7       (i_funct7),
        .i_funct3       (i_funct3),
        .o_aluControl   (aluControl)
    );
    ALU #(.XLEN(XLEN)) alu_unit (
        .i_a      (aluSrcAin),
        .i_b      (aluSrcBin),
        .i_op     (aluControl),
        .o_result (o_aluOut)
    );

    wire indirJump = `ALU_OP_I_JUMP == i_aluOp;
    wire [XLEN-1:0] ctrlTransSrcA = indirJump ? rs1Out : i_PC;
    wire [XLEN-1:0] jmpResult = ctrlTransSrcA + i_IMM;

    assign o_addrGenOut = indirJump ? {jmpResult[XLEN-1:1],1'b0} : jmpResult;
    assign o_rs2FwdOut  = rs2Out;

endmodule