data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:42: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/functions.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/functions.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume,data/full_repos/permissive/498471995/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:43: Cannot find include file: riffa.vh\n`include "riffa.vh" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:44: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:48: Cannot find include file: nf_riffa_dma_cpu_regs_defines.v\n`include "nf_riffa_dma_cpu_regs_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:87: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n    output wire [(`SIG_RQ_TUSER_W-1):0]       s_axis_rq_tuser,\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:96: Define or directive not defined: \'`SIG_RC_TUSER_W\'\n    input wire [(`SIG_RC_TUSER_W-1):0]        m_axis_rc_tuser,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:107: Define or directive not defined: \'`SIG_CQ_TUSER_W\'\n    input wire [(`SIG_CQ_TUSER_W-1):0]        m_axis_cq_tuser,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:117: Define or directive not defined: \'`SIG_CC_TUSER_W\'\n    output wire [(`SIG_CC_TUSER_W-1):0]       s_axis_cc_tuser,\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:275: Define or directive not defined: \'`SIG_CHNL_LENGTH_W\'\n    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_rx_len; \n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:275: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_rx_len; \n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:276: Define or directive not defined: \'`SIG_CHNL_OFFSET_W\'\n    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_rx_off; \n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:276: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_rx_off; \n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:285: Define or directive not defined: \'`SIG_CHNL_LENGTH_W\'\n    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_tx_len; \n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:285: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_tx_len; \n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:286: Define or directive not defined: \'`SIG_CHNL_OFFSET_W\'\n    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_tx_off; \n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:286: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_tx_off; \n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:291: Define or directive not defined: \'`REG_ID_BITS\'\n    reg      [`REG_ID_BITS]    id_reg;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:291: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_ID_BITS]    id_reg;\n                          ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:292: Define or directive not defined: \'`REG_VERSION_BITS\'\n    reg      [`REG_VERSION_BITS]    version_reg;\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:292: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_VERSION_BITS]    version_reg;\n                               ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:293: Define or directive not defined: \'`REG_RESET_BITS\'\n    wire     [`REG_RESET_BITS]    reset_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:293: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire     [`REG_RESET_BITS]    reset_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:294: Define or directive not defined: \'`REG_FLIP_BITS\'\n    reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:294: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:295: Define or directive not defined: \'`REG_FLIP_BITS\'\n    wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:295: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:296: Define or directive not defined: \'`REG_DEBUG_BITS\'\n    reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:296: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:297: Define or directive not defined: \'`REG_DEBUG_BITS\'\n    wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:297: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:298: Define or directive not defined: \'`REG_RQPKT_BITS\'\n    reg      [`REG_RQPKT_BITS]    rqpkt_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:298: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_RQPKT_BITS]    rqpkt_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:300: Define or directive not defined: \'`REG_RCPKT_BITS\'\n    reg      [`REG_RCPKT_BITS]    rcpkt_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:300: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_RCPKT_BITS]    rcpkt_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:302: Define or directive not defined: \'`REG_CQPKT_BITS\'\n    reg      [`REG_CQPKT_BITS]    cqpkt_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:302: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_CQPKT_BITS]    cqpkt_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:304: Define or directive not defined: \'`REG_CCPKT_BITS\'\n    reg      [`REG_CCPKT_BITS]    ccpkt_reg;\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:304: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_CCPKT_BITS]    ccpkt_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:306: Define or directive not defined: \'`REG_XGETXPKT_BITS\'\n    reg      [`REG_XGETXPKT_BITS]    xgetxpkt_reg;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:306: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_XGETXPKT_BITS]    xgetxpkt_reg;\n                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:308: Define or directive not defined: \'`REG_XGERXPKT_BITS\'\n    reg      [`REG_XGERXPKT_BITS]    xgerxpkt_reg;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:308: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_XGERXPKT_BITS]    xgerxpkt_reg;\n                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:310: Define or directive not defined: \'`REG_PCIERQ_BITS\'\n    reg      [`REG_PCIERQ_BITS]    pcierq_reg;\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:310: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_PCIERQ_BITS]    pcierq_reg;\n                              ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:311: Define or directive not defined: \'`REG_PCIEPHY_BITS\'\n    reg      [`REG_PCIEPHY_BITS]    pciephy_reg;\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:311: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_PCIEPHY_BITS]    pciephy_reg;\n                               ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:312: Define or directive not defined: \'`REG_PCIECONFIG_BITS\'\n    reg      [`REG_PCIECONFIG_BITS]    pcieconfig_reg;\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:312: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_PCIECONFIG_BITS]    pcieconfig_reg;\n                                  ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:313: Define or directive not defined: \'`REG_PCIECONFIG2_BITS\'\n    reg      [`REG_PCIECONFIG2_BITS]    pcieconfig2_reg;\n              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/nf_riffa_dma.v:313: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg      [`REG_PCIECONFIG2_BITS]    pcieconfig2_reg;\n                                   ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module nf_riffa_dma
    #(
      parameter C_NUM_CHNL = 2,


      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_MAX_PAYLOAD_BYTES = 128, 
      parameter C_LOG_NUM_TAGS = 6,

      parameter C_AXIS_TDATA_WIDTH  = 128,
      parameter C_AXIS_TKEEP_WIDTH  = 16,
      parameter C_AXIS_TUSER_WIDTH  = 128,
      parameter C_PREAM_VALUE    = 51966,

      parameter C_M_AXI_LITE_ADDR_WIDTH = 32,
      parameter C_M_AXI_LITE_DATA_WIDTH = 32,
      parameter C_M_AXI_LITE_STRB_WIDTH = 4,

      parameter C_S_AXI_DATA_WIDTH    = 32,
      parameter C_S_AXI_ADDR_WIDTH    = 12,
      parameter C_BASEADDR            = 32'h00000000
                 
      ) 
    (
 
    input wire                              user_clk,
    input wire                              user_reset,
    input wire                              user_lnk_up,
    



    input wire                              s_axis_rq_tready,
    output wire                             s_axis_rq_tvalid,
    output wire                             s_axis_rq_tlast,
    output wire [127:0]                     s_axis_rq_tdata,    
    output wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep,
    output wire [(`SIG_RQ_TUSER_W-1):0]       s_axis_rq_tuser,
    



    output wire [21:0]                      m_axis_rc_tready,
    input wire                              m_axis_rc_tvalid,
    input wire                              m_axis_rc_tlast, 
    input wire [(C_PCI_DATA_WIDTH-1):0]       m_axis_rc_tdata,
    input wire [(`SIG_RC_TUSER_W-1):0]        m_axis_rc_tuser,
    input wire [((C_PCI_DATA_WIDTH/32)-1):0]  m_axis_rc_tkeep,
    



    output wire [21:0]                      m_axis_cq_tready, 
    input wire                              m_axis_cq_tvalid,
    input wire                              m_axis_cq_tlast,
    input wire [(C_PCI_DATA_WIDTH-1):0]       m_axis_cq_tdata,
    input wire [(C_PCI_DATA_WIDTH/32)-1:0]  m_axis_cq_tkeep,
    input wire [(`SIG_CQ_TUSER_W-1):0]        m_axis_cq_tuser,
    



    input wire                              s_axis_cc_tready,
    output wire                             s_axis_cc_tvalid,
    output wire                             s_axis_cc_tlast,
    output wire [127:0]                     s_axis_cc_tdata,
    output wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep,
    output wire [(`SIG_CC_TUSER_W-1):0]       s_axis_cc_tuser,
    



    input wire [3:0]                        pcie_rq_seq_num,
    input wire                              pcie_rq_seq_num_vld,
    input wire [5:0]                        pcie_rq_tag,
    input wire                              pcie_rq_tag_vld,    
    output wire                             pcie_cq_np_req,
    input wire [5:0]                        pcie_cq_np_req_count,
    input wire                              cfg_phy_link_down,
    input wire [1:0]                        cfg_phy_link_status,
    input wire [3:0]                        cfg_negotiated_width,
    input wire [2:0]                        cfg_current_speed,
    input wire [2:0]                        cfg_max_payload,
    input wire [2:0]                        cfg_max_read_req,
    input wire [7:0]                        cfg_function_status,
    input wire [5:0]                        cfg_function_power_state,
    input wire [11:0]                       cfg_vf_status,
    input wire [17:0]                       cfg_vf_power_state,
    input wire [1:0]                        cfg_link_power_state,
    input wire                              cfg_err_cor_out,
    input wire                              cfg_err_nonfatal_out,
    input wire                              cfg_err_fatal_out, 
    input wire                              cfg_ltr_enable,
    input wire [5:0]                        cfg_ltssm_state,
    input wire [1:0]                        cfg_rcb_status, 
    input wire [1:0]                        cfg_dpa_substate_change,  
    input wire [1:0]                        cfg_obff_enable,
    input wire                              cfg_pl_status_change,
    input wire [1:0]                        cfg_tph_requester_enable, 
    input wire [5:0]                        cfg_tph_st_mode, 
    input wire [5:0]                        cfg_vf_tph_requester_enable,
    input wire [17:0]                       cfg_vf_tph_st_mode,
    input wire [7:0]                        cfg_fc_ph,
    input wire [11:0]                       cfg_fc_pd,
    input wire [7:0]                        cfg_fc_nph,
    input wire [11:0]                       cfg_fc_npd,
    input wire [7:0]                        cfg_fc_cplh,
    input wire [11:0]                       cfg_fc_cpld,
    output wire [2:0]                       cfg_fc_sel,    




    output wire [3:0]                       cfg_interrupt_int,
    output wire [1:0]                       cfg_interrupt_pending,
    input wire                              cfg_interrupt_sent,  
    input wire [1:0]                        cfg_interrupt_msi_enable,
    input wire [5:0]                        cfg_interrupt_msi_vf_enable,    
    input wire [5:0]                        cfg_interrupt_msi_mmenable,   
    input wire                              cfg_interrupt_msi_mask_update,
    input wire [31:0]                       cfg_interrupt_msi_data,    
    output wire [3:0]                       cfg_interrupt_msi_select,
    output wire [31:0]                      cfg_interrupt_msi_int,
    output wire [63:0]                      cfg_interrupt_msi_pending_status, 
    input wire                              cfg_interrupt_msi_sent,
    input wire                              cfg_interrupt_msi_fail,
    output wire [2:0]                       cfg_interrupt_msi_attr,
    output wire                             cfg_interrupt_msi_tph_present,
    output wire [1:0]                       cfg_interrupt_msi_tph_type,
    output wire [8:0]                       cfg_interrupt_msi_tph_st_tag,
    output wire [2:0]                       cfg_interrupt_msi_function_number,
    



   
    output wire [(C_AXIS_TDATA_WIDTH-1):0]       m_axis_xge_tx_tdata, 
    output wire [(C_AXIS_TKEEP_WIDTH-1):0]       m_axis_xge_tx_tkeep, 
    output wire [(C_AXIS_TUSER_WIDTH-1):0]       m_axis_xge_tx_tuser,
    output wire                              m_axis_xge_tx_tlast, 
    output wire                              m_axis_xge_tx_tvalid, 
    input wire                               m_axis_xge_tx_tready,            
 
    input wire [(C_AXIS_TDATA_WIDTH-1):0]        s_axis_xge_rx_tdata, 
    input wire [(C_AXIS_TKEEP_WIDTH-1):0]        s_axis_xge_rx_tkeep,
    input wire [(C_AXIS_TUSER_WIDTH-1):0]        s_axis_xge_rx_tuser,
    input wire                               s_axis_xge_rx_tlast, 
    input wire                               s_axis_xge_rx_tvalid,   
    output wire                              s_axis_xge_rx_tready,
    



    input  wire                              m_axi_lite_aclk,
    input  wire                              m_axi_lite_aresetn,
    
    input  wire                              m_axi_lite_arready,
    output wire                               m_axi_lite_arvalid,
    output wire [(C_M_AXI_LITE_ADDR_WIDTH-1):0] m_axi_lite_araddr,
    output wire [2:0]                         m_axi_lite_arprot,
    
    output wire                               m_axi_lite_rready,
    input wire                               m_axi_lite_rvalid,
    input wire [(C_M_AXI_LITE_DATA_WIDTH-1):0] m_axi_lite_rdata,
    input wire [1:0]                         m_axi_lite_rresp,
    
    input wire                               m_axi_lite_awready,
    output wire                               m_axi_lite_awvalid,
    output wire [(C_M_AXI_LITE_ADDR_WIDTH-1):0] m_axi_lite_awaddr,
    output wire [2:0]                         m_axi_lite_awprot,
    
    input wire                               m_axi_lite_wready,
    output wire                               m_axi_lite_wvalid,
    output wire [(C_M_AXI_LITE_DATA_WIDTH-1):0] m_axi_lite_wdata,
    output wire [(C_M_AXI_LITE_STRB_WIDTH-1):0] m_axi_lite_wstrb,
      
    output wire                               m_axi_lite_bready,
    input  wire                              m_axi_lite_bvalid,
    input  wire [1:0]                        m_axi_lite_bresp,
    


        input      [C_S_AXI_ADDR_WIDTH-1 : 0]     s_axi_lite_awaddr,
        input                                     s_axi_lite_awvalid,
        input      [C_S_AXI_DATA_WIDTH-1 : 0]     s_axi_lite_wdata,
        input      [C_S_AXI_DATA_WIDTH/8-1 : 0]   s_axi_lite_wstrb,
        input                                     s_axi_lite_wvalid,
        input                                     s_axi_lite_bready,
        input      [C_S_AXI_ADDR_WIDTH-1 : 0]     s_axi_lite_araddr,
        input                                     s_axi_lite_arvalid,
        input                                     s_axi_lite_rready,
        output                                    s_axi_lite_arready,
        output     [C_S_AXI_DATA_WIDTH-1 : 0]     s_axi_lite_rdata,
        output     [1 : 0]                        s_axi_lite_rresp,
        output                                    s_axi_lite_rvalid,
        output                                    s_axi_lite_wready,
        output     [1 :0]                         s_axi_lite_bresp,
        output                                    s_axi_lite_bvalid,
        output                                    s_axi_lite_awready,
    
    output wire                               md_error   
   );






   localparam axis_chnl_num_lp       = 0;
   localparam axi_lite_chnl_num_lp   = 1;
   




    wire                                       m_axis_cq_tready_bit;
    wire                                       m_axis_rc_tready_bit;
    

    wire                                       rst_out; 
    
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_clk;  
    wire [(C_NUM_CHNL-1):0]                      chnl_rx; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_ack; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_last; 
    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_rx_len; 
    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_rx_off; 
    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_data_valid; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_data_ren;

    wire [(C_NUM_CHNL-1):0]                      chnl_tx_clk; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_ack;
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_last; 
    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_tx_len; 
    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_tx_off; 
    wire [((C_NUM_CHNL*C_PCI_DATA_WIDTH)-1):0]   chnl_tx_data; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_data_valid; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_data_ren;
 
    reg      [`REG_ID_BITS]    id_reg;
    reg      [`REG_VERSION_BITS]    version_reg;
    wire     [`REG_RESET_BITS]    reset_reg;
    reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;
    wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;
    reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;
    wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;
    reg      [`REG_RQPKT_BITS]    rqpkt_reg;
    wire                             rqpkt_reg_clear;
    reg      [`REG_RCPKT_BITS]    rcpkt_reg;
    wire                             rcpkt_reg_clear;
    reg      [`REG_CQPKT_BITS]    cqpkt_reg;
    wire                             cqpkt_reg_clear;
    reg      [`REG_CCPKT_BITS]    ccpkt_reg;
    wire                             ccpkt_reg_clear;
    reg      [`REG_XGETXPKT_BITS]    xgetxpkt_reg;
    wire                             xgetxpkt_reg_clear;
    reg      [`REG_XGERXPKT_BITS]    xgerxpkt_reg;
    wire                             xgerxpkt_reg_clear;
    reg      [`REG_PCIERQ_BITS]    pcierq_reg;
    reg      [`REG_PCIEPHY_BITS]    pciephy_reg;
    reg      [`REG_PCIECONFIG_BITS]    pcieconfig_reg;
    reg      [`REG_PCIECONFIG2_BITS]    pcieconfig2_reg;
    reg      [`REG_PCIEERROR_BITS]    pcieerror_reg;
    reg      [`REG_PCIEMISC_BITS]    pciemisc_reg;
    reg      [`REG_PCIETPH_BITS]    pcietph_reg;
    reg      [`REG_PCIEFC1_BITS]    pciefc1_reg;
    reg      [`REG_PCIEFC2_BITS]    pciefc2_reg;
    reg      [`REG_PCIEFC3_BITS]    pciefc3_reg;
    reg      [`REG_PCIEINTERRUPT_BITS]    pcieinterrupt_reg;
    reg      [`REG_PCIEMSIDATA_BITS]    pciemsidata_reg;
    reg      [`REG_PCIEMSIINT_BITS]    pciemsiint_reg;
    reg      [`REG_PCIEMSIPENDINGSTATUS_BITS]    pciemsipendingstatus_reg;
    reg      [`REG_PCIEMSIPENDINGSTATUS2_BITS]    pciemsipendingstatus2_reg;
    reg      [`REG_PCIEINTERRUPT2_BITS]    pcieinterrupt2_reg;

    wire     clear_counters;
    wire     reset_registers;

    genvar                                     chnl;



 assign m_axis_cq_tready =  {22{m_axis_cq_tready_bit}};
 assign m_axis_rc_tready =  {22{m_axis_rc_tready_bit}};


    riffa_wrapper_sume #(
        .C_LOG_NUM_TAGS                                     (C_LOG_NUM_TAGS),
        .C_NUM_CHNL                                         (C_NUM_CHNL),
        .C_PCI_DATA_WIDTH                                   (C_PCI_DATA_WIDTH),
        .C_MAX_PAYLOAD_BYTES                                (C_MAX_PAYLOAD_BYTES)
    ) riffa (

        .M_AXIS_CQ_TREADY                                   (m_axis_cq_tready_bit), 
        .M_AXIS_RC_TREADY                                   (m_axis_rc_tready_bit), 
         
         .S_AXIS_CC_TVALID                                  (s_axis_cc_tvalid), 
         .S_AXIS_CC_TLAST                                   (s_axis_cc_tlast), 
         .S_AXIS_CC_TDATA                                   (s_axis_cc_tdata), 
         .S_AXIS_CC_TKEEP                                   (s_axis_cc_tkeep), 
         .S_AXIS_CC_TUSER                                   (s_axis_cc_tuser),
         
         .S_AXIS_RQ_TVALID                                  (s_axis_rq_tvalid),
         .S_AXIS_RQ_TLAST                                   (s_axis_rq_tlast), 
         .S_AXIS_RQ_TDATA                                   (s_axis_rq_tdata), 
         .S_AXIS_RQ_TKEEP                                   (s_axis_rq_tkeep), 
         .S_AXIS_RQ_TUSER                                   (s_axis_rq_tuser), 
         
         .USER_CLK                                          (user_clk), 
         .USER_RESET                                        (user_reset), 
         
         .CFG_INTERRUPT_INT                                 (cfg_interrupt_int[3:0]), 
         .CFG_INTERRUPT_PENDING                             (cfg_interrupt_pending[1:0]), 
         .CFG_INTERRUPT_MSI_SELECT                          (cfg_interrupt_msi_select[3:0]), 
         .CFG_INTERRUPT_MSI_INT                             (cfg_interrupt_msi_int[31:0]), 
         .CFG_INTERRUPT_MSI_PENDING_STATUS                  (cfg_interrupt_msi_pending_status[63:0]), 
         .CFG_INTERRUPT_MSI_ATTR                            (cfg_interrupt_msi_attr[2:0]), 
         .CFG_INTERRUPT_MSI_TPH_PRESENT                     (cfg_interrupt_msi_tph_present), 
         .CFG_INTERRUPT_MSI_TPH_TYPE                        (cfg_interrupt_msi_tph_type[1:0]), 
         .CFG_INTERRUPT_MSI_TPH_ST_TAG                      (cfg_interrupt_msi_tph_st_tag[8:0]), 
         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER                 (cfg_interrupt_msi_function_number[2:0]),
         .CFG_FC_SEL                                        (cfg_fc_sel[2:0]),
         
         .PCIE_CQ_NP_REQ                                    (pcie_cq_np_req),
             
         .RST_OUT                                           (rst_out), 
                  
         .CHNL_RX                                           (chnl_rx), 
         .CHNL_RX_LAST                                      (chnl_rx_last),  
         .CHNL_RX_LEN                                       (chnl_rx_len), 
         .CHNL_RX_OFF                                       (chnl_rx_off), 
         .CHNL_RX_DATA                                      (chnl_rx_data), 
         .CHNL_RX_DATA_VALID                                (chnl_rx_data_valid), 
         .CHNL_TX_ACK                                       (chnl_tx_ack), 
         .CHNL_TX_DATA_REN                                  (chnl_tx_data_ren), 
         

         .M_AXIS_CQ_TVALID                                  (m_axis_cq_tvalid), 
         .M_AXIS_CQ_TLAST                                   (m_axis_cq_tlast), 
         .M_AXIS_CQ_TDATA                                   (m_axis_cq_tdata), 
         .M_AXIS_CQ_TKEEP                                   (m_axis_cq_tkeep), 
         .M_AXIS_CQ_TUSER                                   (m_axis_cq_tuser), 
         
         .M_AXIS_RC_TVALID                                  (m_axis_rc_tvalid), 
         .M_AXIS_RC_TLAST                                   (m_axis_rc_tlast), 
         .M_AXIS_RC_TDATA                                   (m_axis_rc_tdata), 
         .M_AXIS_RC_TKEEP                                   (m_axis_rc_tkeep), 
         .M_AXIS_RC_TUSER                                   (m_axis_rc_tuser), 
         
         .S_AXIS_CC_TREADY                                  (s_axis_cc_tready), 
         .S_AXIS_RQ_TREADY                                  (s_axis_rq_tready), 
         
         .CFG_INTERRUPT_MSI_ENABLE                          (cfg_interrupt_msi_enable[1:0]), 
         .CFG_INTERRUPT_MSI_MASK_UPDATE                     (cfg_interrupt_msi_mask_update), 
         .CFG_INTERRUPT_MSI_DATA                            (cfg_interrupt_msi_data[31:0]), 
         .CFG_INTERRUPT_MSI_SENT                            (cfg_interrupt_msi_sent), 
         .CFG_INTERRUPT_MSI_FAIL                            (cfg_interrupt_msi_fail), 
         .CFG_FC_CPLH                                       (cfg_fc_cplh[7:0]), 
         .CFG_FC_CPLD                                       (cfg_fc_cpld[11:0]), 
         .CFG_NEGOTIATED_WIDTH                              (cfg_negotiated_width[3:0]),
         .CFG_CURRENT_SPEED                                 (cfg_current_speed[2:0]), 
         .CFG_MAX_PAYLOAD                                   (cfg_max_payload[2:0]), 
         .CFG_MAX_READ_REQ                                  (cfg_max_read_req[2:0]),
         .CFG_FUNCTION_STATUS                               (cfg_function_status[7:0]), 
         .CFG_RCB_STATUS                                    (cfg_rcb_status[1:0]), 
         
         .CHNL_RX_CLK                                       (chnl_rx_clk),
         .CHNL_RX_ACK                                       (chnl_rx_ack),
         .CHNL_RX_DATA_REN                                  (chnl_rx_data_ren),
         .CHNL_TX_CLK                                       (chnl_tx_clk),
         .CHNL_TX                                           (chnl_tx),
         .CHNL_TX_LAST                                      (chnl_tx_last),
         .CHNL_TX_LEN                                       (chnl_tx_len),
         .CHNL_TX_OFF                                       (chnl_tx_off),
         .CHNL_TX_DATA                                      (chnl_tx_data),
         .CHNL_TX_DATA_VALID                                (chnl_tx_data_valid)
         );


 axis_sume_attachment_top #(
     .C_PCI_DATA_WIDTH                                      (C_PCI_DATA_WIDTH),     
     .C_AXIS_TDATA_WIDTH                                      (C_AXIS_TDATA_WIDTH),
     .C_AXIS_TKEEP_WIDTH                                      (C_AXIS_TKEEP_WIDTH),
     .C_AXIS_TUSER_WIDTH                                      (C_AXIS_TUSER_WIDTH),
     .C_PREAM_VALUE                                         (C_PREAM_VALUE)
 ) riffa_axis_attachment (

     .CLK                                                   (user_clk),
     .RST                                                   (rst_out),
     
     .CHNL_RX_CLK                                           (chnl_rx_clk[axis_chnl_num_lp]), 
     .CHNL_RX                                               (chnl_rx[axis_chnl_num_lp]), 
     .CHNL_RX_ACK                                           (chnl_rx_ack[axis_chnl_num_lp]), 
     .CHNL_RX_LAST                                          (chnl_rx_last[axis_chnl_num_lp]), 
     .CHNL_RX_LEN                                           (chnl_rx_len[(`SIG_CHNL_LENGTH_W*axis_chnl_num_lp) +:32]), 
     .CHNL_RX_OFF                                           (chnl_rx_off[(`SIG_CHNL_OFFSET_W*axis_chnl_num_lp) +:31]), 
     .CHNL_RX_DATA                                          (chnl_rx_data[(C_PCI_DATA_WIDTH*axis_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
     .CHNL_RX_DATA_VALID                                    (chnl_rx_data_valid[axis_chnl_num_lp]), 
     .CHNL_RX_DATA_REN                                      (chnl_rx_data_ren[axis_chnl_num_lp]),
 
     .CHNL_TX_CLK                                           (chnl_tx_clk[axis_chnl_num_lp]), 
     .CHNL_TX                                               (chnl_tx[axis_chnl_num_lp]), 
     .CHNL_TX_ACK                                           (chnl_tx_ack[axis_chnl_num_lp]), 
     .CHNL_TX_LAST                                          (chnl_tx_last[axis_chnl_num_lp]), 
     .CHNL_TX_LEN                                           (chnl_tx_len[(`SIG_CHNL_LENGTH_W*axis_chnl_num_lp) +:32]), 
     .CHNL_TX_OFF                                           (chnl_tx_off[(`SIG_CHNL_OFFSET_W*axis_chnl_num_lp) +:31]), 
     .CHNL_TX_DATA                                          (chnl_tx_data[(C_PCI_DATA_WIDTH*axis_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
     .CHNL_TX_DATA_VALID                                    (chnl_tx_data_valid[axis_chnl_num_lp]), 
     .CHNL_TX_DATA_REN                                      (chnl_tx_data_ren[axis_chnl_num_lp]),  
 

    .m_axis_xge_tx_tdata                                    (m_axis_xge_tx_tdata),
    .m_axis_xge_tx_tkeep                                    (m_axis_xge_tx_tkeep), 
    .m_axis_xge_tx_tuser                                    (m_axis_xge_tx_tuser),
    .m_axis_xge_tx_tlast                                    (m_axis_xge_tx_tlast), 
    .m_axis_xge_tx_tvalid                                   (m_axis_xge_tx_tvalid), 
    .m_axis_xge_tx_tready                                   (m_axis_xge_tx_tready),            
    
    .s_axis_xge_rx_tdata                                    (s_axis_xge_rx_tdata), 
    .s_axis_xge_rx_tkeep                                    (s_axis_xge_rx_tkeep),
    .s_axis_xge_rx_tuser                                    (s_axis_xge_rx_tuser),
    .s_axis_xge_rx_tlast                                    (s_axis_xge_rx_tlast), 
    .s_axis_xge_rx_tvalid                                   (s_axis_xge_rx_tvalid),   
    .s_axis_xge_rx_tready                                   (s_axis_xge_rx_tready)
 );


riffa_axi_lite #(
    .C_PCI_DATA_WIDTH                                         (C_PCI_DATA_WIDTH),
    .C_M_AXI_LITE_ADDR_WIDTH                                  (C_M_AXI_LITE_ADDR_WIDTH),
    .C_M_AXI_LITE_DATA_WIDTH                                  (C_M_AXI_LITE_DATA_WIDTH),
    .C_M_AXI_LITE_STRB_WIDTH                                  (C_M_AXI_LITE_STRB_WIDTH)
) riffa_axi_lite_attachment (
    .CLK                                                      (user_clk),
    .RST                                                      (rst_out),
  
    .CHNL_RX_CLK                                              (chnl_rx_clk[axi_lite_chnl_num_lp]), 
    .CHNL_RX                                                  (chnl_rx[axi_lite_chnl_num_lp]), 
    .CHNL_RX_ACK                                              (chnl_rx_ack[axi_lite_chnl_num_lp]), 
    .CHNL_RX_LAST                                             (chnl_rx_last[axi_lite_chnl_num_lp]), 
    .CHNL_RX_LEN                                              (chnl_rx_len[(`SIG_CHNL_LENGTH_W*axi_lite_chnl_num_lp) +:32]), 
    .CHNL_RX_OFF                                              (chnl_rx_off[(`SIG_CHNL_OFFSET_W*axi_lite_chnl_num_lp) +:31]), 
    .CHNL_RX_DATA                                             (chnl_rx_data[(C_PCI_DATA_WIDTH*axi_lite_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
    .CHNL_RX_DATA_VALID                                       (chnl_rx_data_valid[axi_lite_chnl_num_lp]), 
    .CHNL_RX_DATA_REN                                         (chnl_rx_data_ren[axi_lite_chnl_num_lp]),
  
    .CHNL_TX_CLK                                              (chnl_tx_clk[axi_lite_chnl_num_lp]), 
    .CHNL_TX                                                  (chnl_tx[axi_lite_chnl_num_lp]), 
    .CHNL_TX_ACK                                              (chnl_tx_ack[axi_lite_chnl_num_lp]), 
    .CHNL_TX_LAST                                             (chnl_tx_last[axi_lite_chnl_num_lp]), 
    .CHNL_TX_LEN                                              (chnl_tx_len[(`SIG_CHNL_LENGTH_W*axi_lite_chnl_num_lp) +:32]), 
    .CHNL_TX_OFF                                              (chnl_tx_off[(`SIG_CHNL_OFFSET_W*axi_lite_chnl_num_lp) +:31]), 
    .CHNL_TX_DATA                                             (chnl_tx_data[(C_PCI_DATA_WIDTH*axi_lite_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
    .CHNL_TX_DATA_VALID                                       (chnl_tx_data_valid[axi_lite_chnl_num_lp]), 
    .CHNL_TX_DATA_REN                                         (chnl_tx_data_ren[axi_lite_chnl_num_lp]),
  

    .m_axi_lite_aclk                                          (m_axi_lite_aclk),
    .m_axi_lite_aresetn                                       (m_axi_lite_aresetn),
  
    .m_axi_lite_arready                                       (m_axi_lite_arready),
    .m_axi_lite_arvalid                                       (m_axi_lite_arvalid),
    .m_axi_lite_araddr                                        (m_axi_lite_araddr),
    .m_axi_lite_arprot                                        (m_axi_lite_arprot),

    .m_axi_lite_rready                                        (m_axi_lite_rready),
    .m_axi_lite_rvalid                                        (m_axi_lite_rvalid),
    .m_axi_lite_rdata                                         (m_axi_lite_rdata),
    .m_axi_lite_rresp                                         (m_axi_lite_rresp),
      
    .m_axi_lite_awready                                       (m_axi_lite_awready),
    .m_axi_lite_awvalid                                       (m_axi_lite_awvalid),
    .m_axi_lite_awaddr                                        (m_axi_lite_awaddr),
    .m_axi_lite_awprot                                        (m_axi_lite_awprot),
  
    .m_axi_lite_wready                                        (m_axi_lite_wready),
    .m_axi_lite_wvalid                                        (m_axi_lite_wvalid),
    .m_axi_lite_wdata                                         (m_axi_lite_wdata),
    .m_axi_lite_wstrb                                         (m_axi_lite_wstrb),
    
    .m_axi_lite_bready                                        (m_axi_lite_bready),
    .m_axi_lite_bvalid                                        (m_axi_lite_bvalid),
    .m_axi_lite_bresp                                         (m_axi_lite_bresp),

    .md_error                                                 (md_error)
);



 nf_riffa_dma_cpu_regs 
 #(
     .C_BASE_ADDRESS        (C_BASEADDR ),
     .C_S_AXI_DATA_WIDTH    (C_S_AXI_DATA_WIDTH),
     .C_S_AXI_ADDR_WIDTH    (C_S_AXI_ADDR_WIDTH)
 ) nf_riffa_dma_cpu_regs_inst
 (   

    .clk                    (user_clk),
    .resetn                 (~user_reset),

    .S_AXI_ACLK             (user_clk),
    .S_AXI_ARESETN          (~user_reset),
    .S_AXI_AWADDR           (s_axi_lite_awaddr),
    .S_AXI_AWVALID          (s_axi_lite_awvalid),
    .S_AXI_WDATA            (s_axi_lite_wdata),
    .S_AXI_WSTRB            (s_axi_lite_wstrb),
    .S_AXI_WVALID           (s_axi_lite_wvalid),
    .S_AXI_BREADY           (s_axi_lite_bready),
    .S_AXI_ARADDR           (s_axi_lite_araddr),
    .S_AXI_ARVALID          (s_axi_lite_arvalid),
    .S_AXI_RREADY           (s_axi_lite_rready),
    .S_AXI_ARREADY          (s_axi_lite_arready),
    .S_AXI_RDATA            (s_axi_lite_rdata),
    .S_AXI_RRESP            (s_axi_lite_rresp),
    .S_AXI_RVALID           (s_axi_lite_rvalid),
    .S_AXI_WREADY           (s_axi_lite_wready),
    .S_AXI_BRESP            (s_axi_lite_bresp),
    .S_AXI_BVALID           (s_axi_lite_bvalid),
    .S_AXI_AWREADY          (s_axi_lite_awready),
   

   .id_reg          (id_reg),
   .version_reg          (version_reg),
   .reset_reg          (reset_reg),
   .ip2cpu_flip_reg          (ip2cpu_flip_reg),
   .cpu2ip_flip_reg          (cpu2ip_flip_reg),
   .ip2cpu_debug_reg          (ip2cpu_debug_reg),
   .cpu2ip_debug_reg          (cpu2ip_debug_reg),
   .rqpkt_reg          (rqpkt_reg),
   .rqpkt_reg_clear    (rqpkt_reg_clear),
   .rcpkt_reg          (rcpkt_reg),
   .rcpkt_reg_clear    (rcpkt_reg_clear),
   .cqpkt_reg          (cqpkt_reg),
   .cqpkt_reg_clear    (cqpkt_reg_clear),
   .ccpkt_reg          (ccpkt_reg),
   .ccpkt_reg_clear    (ccpkt_reg_clear),
   .xgetxpkt_reg          (xgetxpkt_reg),
   .xgetxpkt_reg_clear    (xgetxpkt_reg_clear),
   .xgerxpkt_reg          (xgerxpkt_reg),
   .xgerxpkt_reg_clear    (xgerxpkt_reg_clear),
   .pcierq_reg          (pcierq_reg),
   .pciephy_reg          (pciephy_reg),
   .pcieconfig_reg          (pcieconfig_reg),
   .pcieconfig2_reg          (pcieconfig2_reg),
   .pcieerror_reg          (pcieerror_reg),
   .pciemisc_reg          (pciemisc_reg),
   .pcietph_reg          (pcietph_reg),
   .pciefc1_reg          (pciefc1_reg),
   .pciefc2_reg          (pciefc2_reg),
   .pciefc3_reg          (pciefc3_reg),
   .pcieinterrupt_reg          (pcieinterrupt_reg),
   .pciemsidata_reg          (pciemsidata_reg),
   .pciemsiint_reg          (pciemsiint_reg),
   .pciemsipendingstatus_reg          (pciemsipendingstatus_reg),
   .pciemsipendingstatus2_reg          (pciemsipendingstatus2_reg),
   .pcieinterrupt2_reg          (pcieinterrupt2_reg),

   .cpu_resetn_soft(),
   .resetn_soft    (),
   .resetn_sync    (resetn_sync)
);


    assign     clear_counters = reset_reg[0];
    assign     reset_registers = reset_reg[4];



always @(posedge user_clk)
	if (user_reset | reset_registers) begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;
		rqpkt_reg <= #1    `REG_RQPKT_DEFAULT;
		rcpkt_reg <= #1    `REG_RCPKT_DEFAULT;
		cqpkt_reg <= #1    `REG_CQPKT_DEFAULT;
		ccpkt_reg <= #1    `REG_CCPKT_DEFAULT;
		xgetxpkt_reg <= #1    `REG_XGETXPKT_DEFAULT;
		xgerxpkt_reg <= #1    `REG_XGERXPKT_DEFAULT;
		pcierq_reg <= #1    `REG_PCIERQ_DEFAULT;
		pciephy_reg <= #1    `REG_PCIEPHY_DEFAULT;
		pcieconfig_reg <= #1    `REG_PCIECONFIG_DEFAULT;
		pcieconfig2_reg <= #1    `REG_PCIECONFIG2_DEFAULT;
		pcieerror_reg <= #1    `REG_PCIEERROR_DEFAULT;
		pciemisc_reg <= #1    `REG_PCIEMISC_DEFAULT;
		pcietph_reg <= #1    `REG_PCIETPH_DEFAULT;
		pciefc1_reg <= #1    `REG_PCIEFC1_DEFAULT;
		pciefc2_reg <= #1    `REG_PCIEFC2_DEFAULT;
		pciefc3_reg <= #1    `REG_PCIEFC3_DEFAULT;
		pcieinterrupt_reg <= #1    `REG_PCIEINTERRUPT_DEFAULT;
		pciemsidata_reg <= #1    `REG_PCIEMSIDATA_DEFAULT;
		pciemsiint_reg <= #1    `REG_PCIEMSIINT_DEFAULT;
		pciemsipendingstatus_reg <= #1    `REG_PCIEMSIPENDINGSTATUS_DEFAULT;
		pciemsipendingstatus2_reg <= #1    `REG_PCIEMSIPENDINGSTATUS2_DEFAULT;
		pcieinterrupt2_reg <= #1    `REG_PCIEINTERRUPT2_DEFAULT;
	end
	else begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    ~cpu2ip_flip_reg;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT+cpu2ip_debug_reg;
		              
		rqpkt_reg [`REG_RQPKT_WIDTH -2: 0] <= #1  clear_counters | rqpkt_reg_clear ? 'h0  : rqpkt_reg[`REG_RQPKT_WIDTH -2: 0] + (s_axis_rq_tlast && s_axis_rq_tvalid && s_axis_rq_tready) ;
		rqpkt_reg [`REG_RQPKT_WIDTH-1    ] <= #1  clear_counters | rqpkt_reg_clear ? 'h0  : rqpkt_reg[`REG_RQPKT_WIDTH-2:0] + (s_axis_rq_tlast && s_axis_rq_tvalid && s_axis_rq_tready)
				                                                     > {(`REG_RQPKT_WIDTH-1){1'b1}} ? 1'b1 : rqpkt_reg[`REG_RQPKT_WIDTH-1];
				                                                     
		rcpkt_reg [`REG_RCPKT_WIDTH -2: 0] <= #1  clear_counters | rcpkt_reg_clear ? 'h0  : rcpkt_reg[`REG_RCPKT_WIDTH -2: 0] + (m_axis_rc_tlast && m_axis_rc_tvalid && m_axis_rc_tready) ;
		rcpkt_reg [`REG_RCPKT_WIDTH-1    ] <= #1  clear_counters | rcpkt_reg_clear ? 'h0  : rcpkt_reg[`REG_RCPKT_WIDTH-2:0] + (m_axis_rc_tlast && m_axis_rc_tvalid && m_axis_rc_tready)
						                                                     > {(`REG_RCPKT_WIDTH-1){1'b1}} ? 1'b1 : rcpkt_reg[`REG_RCPKT_WIDTH-1];
						                                                     
		cqpkt_reg [`REG_CQPKT_WIDTH -2: 0] <= #1  clear_counters | cqpkt_reg_clear ? 'h0  : cqpkt_reg[`REG_CQPKT_WIDTH -2: 0] + (m_axis_cq_tlast && m_axis_cq_tvalid && m_axis_cq_tready) ;
		cqpkt_reg [`REG_CQPKT_WIDTH-1    ] <= #1  clear_counters | cqpkt_reg_clear ? 'h0  : cqpkt_reg[`REG_CQPKT_WIDTH-2:0] + (m_axis_cq_tlast && m_axis_cq_tvalid && m_axis_cq_tready)
						                                                     > {(`REG_CQPKT_WIDTH-1){1'b1}} ? 1'b1 : cqpkt_reg[`REG_CQPKT_WIDTH-1];
				                                                     
		ccpkt_reg [`REG_CCPKT_WIDTH -2: 0] <= #1  clear_counters | ccpkt_reg_clear ? 'h0  : ccpkt_reg[`REG_CCPKT_WIDTH -2: 0] + (s_axis_cc_tlast && s_axis_cc_tvalid && s_axis_cc_tready) ;
		ccpkt_reg [`REG_CCPKT_WIDTH-1    ] <= #1  clear_counters | ccpkt_reg_clear ? 'h0  : ccpkt_reg[`REG_CCPKT_WIDTH-2:0] + (s_axis_cc_tlast && s_axis_cc_tvalid && s_axis_cc_tready)
				                                                     > {(`REG_CCPKT_WIDTH-1){1'b1}} ? 1'b1 : ccpkt_reg[`REG_CCPKT_WIDTH-1];
	
		xgetxpkt_reg [`REG_XGETXPKT_WIDTH -2: 0] <= #1  clear_counters | xgetxpkt_reg_clear ? 'h0  : xgetxpkt_reg[`REG_XGETXPKT_WIDTH -2: 0] + (m_axis_xge_tx_tlast && m_axis_xge_tx_tvalid && m_axis_xge_tx_tready) ;
		xgetxpkt_reg [`REG_XGETXPKT_WIDTH-1    ] <= #1  clear_counters | xgetxpkt_reg_clear ? 'h0  : xgetxpkt_reg[`REG_XGETXPKT_WIDTH-2:0] + (m_axis_xge_tx_tlast && m_axis_xge_tx_tvalid && m_axis_xge_tx_tready) > {(`REG_XGETXPKT_WIDTH-1){1'b1}} ? 1'b1 : xgetxpkt_reg[`REG_XGETXPKT_WIDTH-1];
						                                                     
		xgerxpkt_reg [`REG_XGERXPKT_WIDTH -2: 0] <= #1  clear_counters | xgerxpkt_reg_clear ? 'h0  : xgerxpkt_reg[`REG_XGERXPKT_WIDTH -2: 0] + (s_axis_xge_rx_tlast && s_axis_xge_rx_tvalid && s_axis_xge_rx_tready) ;
		xgerxpkt_reg [`REG_XGERXPKT_WIDTH-1    ] <= #1  clear_counters | xgerxpkt_reg_clear ? 'h0  : xgerxpkt_reg[`REG_XGERXPKT_WIDTH-2:0] + (s_axis_xge_rx_tlast && s_axis_xge_rx_tvalid && s_axis_xge_rx_tready)> {(`REG_XGERXPKT_WIDTH-1){1'b1}} ? 1'b1 : xgerxpkt_reg[`REG_XGERXPKT_WIDTH-1];
						                                                     
		pcierq_reg [3:0]   <= #1    pcie_rq_seq_num_vld ? pcie_rq_seq_num : pcierq_reg [3:0];
		pcierq_reg [20:16] <= #1    pcie_rq_tag_vld ? pcie_rq_tag : pcierq_reg [20:16];
		
		pciephy_reg [2:0] <= #1   {cfg_phy_link_status,cfg_phy_link_down};
		pciephy_reg [19:16] <= #1   cfg_negotiated_width;
		
		pcieconfig_reg [2:0] <= #1     cfg_current_speed;
		pcieconfig_reg [6:4] <= #1     cfg_max_payload;
		pcieconfig_reg [10:8] <= #1     cfg_max_read_req;
		pcieconfig_reg [19:12] <= #1     cfg_function_status;
		pcieconfig_reg [25:20] <= #1     cfg_function_power_state;
		pcieconfig_reg [29:28] <= #1     cfg_link_power_state;
		
		pcieconfig2_reg [11:0] <= #1    cfg_vf_status;
		pcieconfig2_reg [29:12] <= #1    cfg_vf_power_state;		
		
		pcieerror_reg [0] <= #1    cfg_err_cor_out;
		pcieerror_reg [4] <= #1    cfg_err_nonfatal_out;
		pcieerror_reg [8] <= #1    cfg_err_fatal_out;

				
		pciemisc_reg [5:0]  <= #1    cfg_ltssm_state;
		pciemisc_reg [8]    <= #1    cfg_ltr_enable;
		pciemisc_reg [13:12]<= #1    cfg_rcb_status;		
		pciemisc_reg [17:16]<= #1    cfg_dpa_substate_change;
		pciemisc_reg [20]   <= #1    cfg_obff_enable;
		pciemisc_reg [24]   <= #1    cfg_pl_status_change;		
		
		pcietph_reg[1:0] <= #1    cfg_tph_requester_enable;
		pcietph_reg[7:2] <= #1    cfg_tph_st_mode;
		pcietph_reg[13:8] <= #1    cfg_vf_tph_requester_enable;
		pcietph_reg[31:14] <= #1    cfg_vf_tph_st_mode;					
		
		pciefc1_reg [7:0] <= #1    cfg_fc_ph;
		pciefc1_reg [19:8] <= #1    cfg_fc_pd;
		
		pciefc2_reg [7:0] <= #1    cfg_fc_nph;
		pciefc2_reg [19:8] <= #1    cfg_fc_npd;
		
		pciefc3_reg [7:0] <= #1    cfg_fc_cplh;
		pciefc3_reg [19:8] <= #1    cfg_fc_cpld;
		pciefc3_reg [22:20] <= #1    cfg_fc_sel;
		

		pcieinterrupt_reg [3:0] <= #1    cfg_interrupt_int;
		pcieinterrupt_reg [5:4] <= #1    cfg_interrupt_pending;
		pcieinterrupt_reg [8] <= #1    cfg_interrupt_sent;
		pcieinterrupt_reg [13:12] <= #1    cfg_interrupt_msi_enable;
		pcieinterrupt_reg [21:16] <= #1    cfg_interrupt_msi_vf_enable;
		pcieinterrupt_reg [29:24] <= #1    cfg_interrupt_msi_mmenable;
		pcieinterrupt_reg [31] <= #1    cfg_interrupt_msi_mask_update;
		
		pciemsidata_reg <= #1     cfg_interrupt_msi_data;
		
		pciemsiint_reg <= #1    cfg_interrupt_msi_int;
		
		pciemsipendingstatus_reg <= #1    cfg_interrupt_msi_pending_status[31:0];
		pciemsipendingstatus2_reg <= #1   cfg_interrupt_msi_pending_status[63:32];
		
		pcieinterrupt2_reg [3:0]  <= #1   cfg_interrupt_msi_select;
		pcieinterrupt2_reg [4]  <= #1   cfg_interrupt_msi_sent;
		pcieinterrupt2_reg [5]  <= #1   cfg_interrupt_msi_fail;
		pcieinterrupt2_reg [10:8]  <= #1   cfg_interrupt_msi_attr;
		pcieinterrupt2_reg [12]  <= #1   cfg_interrupt_msi_tph_present;
		pcieinterrupt2_reg [14:13]  <= #1   cfg_interrupt_msi_tph_type;
		pcieinterrupt2_reg [24:16]  <= #1   cfg_interrupt_msi_tph_st_tag;
		pcieinterrupt2_reg [30:28]  <= #1   cfg_interrupt_msi_function_number;
		
    end

    
endmodule
module nf_riffa_dma
    #(
      parameter C_NUM_CHNL = 2,


      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_MAX_PAYLOAD_BYTES = 128, 
      parameter C_LOG_NUM_TAGS = 6,

      parameter C_AXIS_TDATA_WIDTH  = 128,
      parameter C_AXIS_TKEEP_WIDTH  = 16,
      parameter C_AXIS_TUSER_WIDTH  = 128,
      parameter C_PREAM_VALUE    = 51966,

      parameter C_M_AXI_LITE_ADDR_WIDTH = 32,
      parameter C_M_AXI_LITE_DATA_WIDTH = 32,
      parameter C_M_AXI_LITE_STRB_WIDTH = 4,

      parameter C_S_AXI_DATA_WIDTH    = 32,
      parameter C_S_AXI_ADDR_WIDTH    = 12,
      parameter C_BASEADDR            = 32'h00000000
                 
      ) 
    (
 
    input wire                              user_clk,
    input wire                              user_reset,
    input wire                              user_lnk_up,
    



    input wire                              s_axis_rq_tready,
    output wire                             s_axis_rq_tvalid,
    output wire                             s_axis_rq_tlast,
    output wire [127:0]                     s_axis_rq_tdata,    
    output wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep,
    output wire [(`SIG_RQ_TUSER_W-1):0]       s_axis_rq_tuser,
    



    output wire [21:0]                      m_axis_rc_tready,
    input wire                              m_axis_rc_tvalid,
    input wire                              m_axis_rc_tlast, 
    input wire [(C_PCI_DATA_WIDTH-1):0]       m_axis_rc_tdata,
    input wire [(`SIG_RC_TUSER_W-1):0]        m_axis_rc_tuser,
    input wire [((C_PCI_DATA_WIDTH/32)-1):0]  m_axis_rc_tkeep,
    



    output wire [21:0]                      m_axis_cq_tready, 
    input wire                              m_axis_cq_tvalid,
    input wire                              m_axis_cq_tlast,
    input wire [(C_PCI_DATA_WIDTH-1):0]       m_axis_cq_tdata,
    input wire [(C_PCI_DATA_WIDTH/32)-1:0]  m_axis_cq_tkeep,
    input wire [(`SIG_CQ_TUSER_W-1):0]        m_axis_cq_tuser,
    



    input wire                              s_axis_cc_tready,
    output wire                             s_axis_cc_tvalid,
    output wire                             s_axis_cc_tlast,
    output wire [127:0]                     s_axis_cc_tdata,
    output wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep,
    output wire [(`SIG_CC_TUSER_W-1):0]       s_axis_cc_tuser,
    



    input wire [3:0]                        pcie_rq_seq_num,
    input wire                              pcie_rq_seq_num_vld,
    input wire [5:0]                        pcie_rq_tag,
    input wire                              pcie_rq_tag_vld,    
    output wire                             pcie_cq_np_req,
    input wire [5:0]                        pcie_cq_np_req_count,
    input wire                              cfg_phy_link_down,
    input wire [1:0]                        cfg_phy_link_status,
    input wire [3:0]                        cfg_negotiated_width,
    input wire [2:0]                        cfg_current_speed,
    input wire [2:0]                        cfg_max_payload,
    input wire [2:0]                        cfg_max_read_req,
    input wire [7:0]                        cfg_function_status,
    input wire [5:0]                        cfg_function_power_state,
    input wire [11:0]                       cfg_vf_status,
    input wire [17:0]                       cfg_vf_power_state,
    input wire [1:0]                        cfg_link_power_state,
    input wire                              cfg_err_cor_out,
    input wire                              cfg_err_nonfatal_out,
    input wire                              cfg_err_fatal_out, 
    input wire                              cfg_ltr_enable,
    input wire [5:0]                        cfg_ltssm_state,
    input wire [1:0]                        cfg_rcb_status, 
    input wire [1:0]                        cfg_dpa_substate_change,  
    input wire [1:0]                        cfg_obff_enable,
    input wire                              cfg_pl_status_change,
    input wire [1:0]                        cfg_tph_requester_enable, 
    input wire [5:0]                        cfg_tph_st_mode, 
    input wire [5:0]                        cfg_vf_tph_requester_enable,
    input wire [17:0]                       cfg_vf_tph_st_mode,
    input wire [7:0]                        cfg_fc_ph,
    input wire [11:0]                       cfg_fc_pd,
    input wire [7:0]                        cfg_fc_nph,
    input wire [11:0]                       cfg_fc_npd,
    input wire [7:0]                        cfg_fc_cplh,
    input wire [11:0]                       cfg_fc_cpld,
    output wire [2:0]                       cfg_fc_sel,    




    output wire [3:0]                       cfg_interrupt_int,
    output wire [1:0]                       cfg_interrupt_pending,
    input wire                              cfg_interrupt_sent,  
    input wire [1:0]                        cfg_interrupt_msi_enable,
    input wire [5:0]                        cfg_interrupt_msi_vf_enable,    
    input wire [5:0]                        cfg_interrupt_msi_mmenable,   
    input wire                              cfg_interrupt_msi_mask_update,
    input wire [31:0]                       cfg_interrupt_msi_data,    
    output wire [3:0]                       cfg_interrupt_msi_select,
    output wire [31:0]                      cfg_interrupt_msi_int,
    output wire [63:0]                      cfg_interrupt_msi_pending_status, 
    input wire                              cfg_interrupt_msi_sent,
    input wire                              cfg_interrupt_msi_fail,
    output wire [2:0]                       cfg_interrupt_msi_attr,
    output wire                             cfg_interrupt_msi_tph_present,
    output wire [1:0]                       cfg_interrupt_msi_tph_type,
    output wire [8:0]                       cfg_interrupt_msi_tph_st_tag,
    output wire [2:0]                       cfg_interrupt_msi_function_number,
    



   
    output wire [(C_AXIS_TDATA_WIDTH-1):0]       m_axis_xge_tx_tdata, 
    output wire [(C_AXIS_TKEEP_WIDTH-1):0]       m_axis_xge_tx_tkeep, 
    output wire [(C_AXIS_TUSER_WIDTH-1):0]       m_axis_xge_tx_tuser,
    output wire                              m_axis_xge_tx_tlast, 
    output wire                              m_axis_xge_tx_tvalid, 
    input wire                               m_axis_xge_tx_tready,            
 
    input wire [(C_AXIS_TDATA_WIDTH-1):0]        s_axis_xge_rx_tdata, 
    input wire [(C_AXIS_TKEEP_WIDTH-1):0]        s_axis_xge_rx_tkeep,
    input wire [(C_AXIS_TUSER_WIDTH-1):0]        s_axis_xge_rx_tuser,
    input wire                               s_axis_xge_rx_tlast, 
    input wire                               s_axis_xge_rx_tvalid,   
    output wire                              s_axis_xge_rx_tready,
    



    input  wire                              m_axi_lite_aclk,
    input  wire                              m_axi_lite_aresetn,
    
    input  wire                              m_axi_lite_arready,
    output wire                               m_axi_lite_arvalid,
    output wire [(C_M_AXI_LITE_ADDR_WIDTH-1):0] m_axi_lite_araddr,
    output wire [2:0]                         m_axi_lite_arprot,
    
    output wire                               m_axi_lite_rready,
    input wire                               m_axi_lite_rvalid,
    input wire [(C_M_AXI_LITE_DATA_WIDTH-1):0] m_axi_lite_rdata,
    input wire [1:0]                         m_axi_lite_rresp,
    
    input wire                               m_axi_lite_awready,
    output wire                               m_axi_lite_awvalid,
    output wire [(C_M_AXI_LITE_ADDR_WIDTH-1):0] m_axi_lite_awaddr,
    output wire [2:0]                         m_axi_lite_awprot,
    
    input wire                               m_axi_lite_wready,
    output wire                               m_axi_lite_wvalid,
    output wire [(C_M_AXI_LITE_DATA_WIDTH-1):0] m_axi_lite_wdata,
    output wire [(C_M_AXI_LITE_STRB_WIDTH-1):0] m_axi_lite_wstrb,
      
    output wire                               m_axi_lite_bready,
    input  wire                              m_axi_lite_bvalid,
    input  wire [1:0]                        m_axi_lite_bresp,
    


        input      [C_S_AXI_ADDR_WIDTH-1 : 0]     s_axi_lite_awaddr,
        input                                     s_axi_lite_awvalid,
        input      [C_S_AXI_DATA_WIDTH-1 : 0]     s_axi_lite_wdata,
        input      [C_S_AXI_DATA_WIDTH/8-1 : 0]   s_axi_lite_wstrb,
        input                                     s_axi_lite_wvalid,
        input                                     s_axi_lite_bready,
        input      [C_S_AXI_ADDR_WIDTH-1 : 0]     s_axi_lite_araddr,
        input                                     s_axi_lite_arvalid,
        input                                     s_axi_lite_rready,
        output                                    s_axi_lite_arready,
        output     [C_S_AXI_DATA_WIDTH-1 : 0]     s_axi_lite_rdata,
        output     [1 : 0]                        s_axi_lite_rresp,
        output                                    s_axi_lite_rvalid,
        output                                    s_axi_lite_wready,
        output     [1 :0]                         s_axi_lite_bresp,
        output                                    s_axi_lite_bvalid,
        output                                    s_axi_lite_awready,
    
    output wire                               md_error   
   );







   localparam axis_chnl_num_lp       = 0;
   localparam axi_lite_chnl_num_lp   = 1;
   




    wire                                       m_axis_cq_tready_bit;
    wire                                       m_axis_rc_tready_bit;
    

    wire                                       rst_out; 
    
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_clk;  
    wire [(C_NUM_CHNL-1):0]                      chnl_rx; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_ack; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_last; 
    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_rx_len; 
    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_rx_off; 
    wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   chnl_rx_data; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_data_valid; 
    wire [(C_NUM_CHNL-1):0]                      chnl_rx_data_ren;

    wire [(C_NUM_CHNL-1):0]                      chnl_tx_clk; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_ack;
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_last; 
    wire [((C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1):0] chnl_tx_len; 
    wire [((C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1):0] chnl_tx_off; 
    wire [((C_NUM_CHNL*C_PCI_DATA_WIDTH)-1):0]   chnl_tx_data; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_data_valid; 
    wire [(C_NUM_CHNL-1):0]                      chnl_tx_data_ren;
 
    reg      [`REG_ID_BITS]    id_reg;
    reg      [`REG_VERSION_BITS]    version_reg;
    wire     [`REG_RESET_BITS]    reset_reg;
    reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;
    wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;
    reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;
    wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;
    reg      [`REG_RQPKT_BITS]    rqpkt_reg;
    wire                             rqpkt_reg_clear;
    reg      [`REG_RCPKT_BITS]    rcpkt_reg;
    wire                             rcpkt_reg_clear;
    reg      [`REG_CQPKT_BITS]    cqpkt_reg;
    wire                             cqpkt_reg_clear;
    reg      [`REG_CCPKT_BITS]    ccpkt_reg;
    wire                             ccpkt_reg_clear;
    reg      [`REG_XGETXPKT_BITS]    xgetxpkt_reg;
    wire                             xgetxpkt_reg_clear;
    reg      [`REG_XGERXPKT_BITS]    xgerxpkt_reg;
    wire                             xgerxpkt_reg_clear;
    reg      [`REG_PCIERQ_BITS]    pcierq_reg;
    reg      [`REG_PCIEPHY_BITS]    pciephy_reg;
    reg      [`REG_PCIECONFIG_BITS]    pcieconfig_reg;
    reg      [`REG_PCIECONFIG2_BITS]    pcieconfig2_reg;
    reg      [`REG_PCIEERROR_BITS]    pcieerror_reg;
    reg      [`REG_PCIEMISC_BITS]    pciemisc_reg;
    reg      [`REG_PCIETPH_BITS]    pcietph_reg;
    reg      [`REG_PCIEFC1_BITS]    pciefc1_reg;
    reg      [`REG_PCIEFC2_BITS]    pciefc2_reg;
    reg      [`REG_PCIEFC3_BITS]    pciefc3_reg;
    reg      [`REG_PCIEINTERRUPT_BITS]    pcieinterrupt_reg;
    reg      [`REG_PCIEMSIDATA_BITS]    pciemsidata_reg;
    reg      [`REG_PCIEMSIINT_BITS]    pciemsiint_reg;
    reg      [`REG_PCIEMSIPENDINGSTATUS_BITS]    pciemsipendingstatus_reg;
    reg      [`REG_PCIEMSIPENDINGSTATUS2_BITS]    pciemsipendingstatus2_reg;
    reg      [`REG_PCIEINTERRUPT2_BITS]    pcieinterrupt2_reg;

    wire     clear_counters;
    wire     reset_registers;

    genvar                                     chnl;



 assign m_axis_cq_tready =  {22{m_axis_cq_tready_bit}};
 assign m_axis_rc_tready =  {22{m_axis_rc_tready_bit}};


    riffa_wrapper_sume #(
        .C_LOG_NUM_TAGS                                     (C_LOG_NUM_TAGS),
        .C_NUM_CHNL                                         (C_NUM_CHNL),
        .C_PCI_DATA_WIDTH                                   (C_PCI_DATA_WIDTH),
        .C_MAX_PAYLOAD_BYTES                                (C_MAX_PAYLOAD_BYTES)
    ) riffa (

        .M_AXIS_CQ_TREADY                                   (m_axis_cq_tready_bit), 
        .M_AXIS_RC_TREADY                                   (m_axis_rc_tready_bit), 
         
         .S_AXIS_CC_TVALID                                  (s_axis_cc_tvalid), 
         .S_AXIS_CC_TLAST                                   (s_axis_cc_tlast), 
         .S_AXIS_CC_TDATA                                   (s_axis_cc_tdata), 
         .S_AXIS_CC_TKEEP                                   (s_axis_cc_tkeep), 
         .S_AXIS_CC_TUSER                                   (s_axis_cc_tuser),
         
         .S_AXIS_RQ_TVALID                                  (s_axis_rq_tvalid),
         .S_AXIS_RQ_TLAST                                   (s_axis_rq_tlast), 
         .S_AXIS_RQ_TDATA                                   (s_axis_rq_tdata), 
         .S_AXIS_RQ_TKEEP                                   (s_axis_rq_tkeep), 
         .S_AXIS_RQ_TUSER                                   (s_axis_rq_tuser), 
         
         .USER_CLK                                          (user_clk), 
         .USER_RESET                                        (user_reset), 
         
         .CFG_INTERRUPT_INT                                 (cfg_interrupt_int[3:0]), 
         .CFG_INTERRUPT_PENDING                             (cfg_interrupt_pending[1:0]), 
         .CFG_INTERRUPT_MSI_SELECT                          (cfg_interrupt_msi_select[3:0]), 
         .CFG_INTERRUPT_MSI_INT                             (cfg_interrupt_msi_int[31:0]), 
         .CFG_INTERRUPT_MSI_PENDING_STATUS                  (cfg_interrupt_msi_pending_status[63:0]), 
         .CFG_INTERRUPT_MSI_ATTR                            (cfg_interrupt_msi_attr[2:0]), 
         .CFG_INTERRUPT_MSI_TPH_PRESENT                     (cfg_interrupt_msi_tph_present), 
         .CFG_INTERRUPT_MSI_TPH_TYPE                        (cfg_interrupt_msi_tph_type[1:0]), 
         .CFG_INTERRUPT_MSI_TPH_ST_TAG                      (cfg_interrupt_msi_tph_st_tag[8:0]), 
         .CFG_INTERRUPT_MSI_FUNCTION_NUMBER                 (cfg_interrupt_msi_function_number[2:0]),
         .CFG_FC_SEL                                        (cfg_fc_sel[2:0]),
         
         .PCIE_CQ_NP_REQ                                    (pcie_cq_np_req),
             
         .RST_OUT                                           (rst_out), 
                  
         .CHNL_RX                                           (chnl_rx), 
         .CHNL_RX_LAST                                      (chnl_rx_last),  
         .CHNL_RX_LEN                                       (chnl_rx_len), 
         .CHNL_RX_OFF                                       (chnl_rx_off), 
         .CHNL_RX_DATA                                      (chnl_rx_data), 
         .CHNL_RX_DATA_VALID                                (chnl_rx_data_valid), 
         .CHNL_TX_ACK                                       (chnl_tx_ack), 
         .CHNL_TX_DATA_REN                                  (chnl_tx_data_ren), 
         

         .M_AXIS_CQ_TVALID                                  (m_axis_cq_tvalid), 
         .M_AXIS_CQ_TLAST                                   (m_axis_cq_tlast), 
         .M_AXIS_CQ_TDATA                                   (m_axis_cq_tdata), 
         .M_AXIS_CQ_TKEEP                                   (m_axis_cq_tkeep), 
         .M_AXIS_CQ_TUSER                                   (m_axis_cq_tuser), 
         
         .M_AXIS_RC_TVALID                                  (m_axis_rc_tvalid), 
         .M_AXIS_RC_TLAST                                   (m_axis_rc_tlast), 
         .M_AXIS_RC_TDATA                                   (m_axis_rc_tdata), 
         .M_AXIS_RC_TKEEP                                   (m_axis_rc_tkeep), 
         .M_AXIS_RC_TUSER                                   (m_axis_rc_tuser), 
         
         .S_AXIS_CC_TREADY                                  (s_axis_cc_tready), 
         .S_AXIS_RQ_TREADY                                  (s_axis_rq_tready), 
         
         .CFG_INTERRUPT_MSI_ENABLE                          (cfg_interrupt_msi_enable[1:0]), 
         .CFG_INTERRUPT_MSI_MASK_UPDATE                     (cfg_interrupt_msi_mask_update), 
         .CFG_INTERRUPT_MSI_DATA                            (cfg_interrupt_msi_data[31:0]), 
         .CFG_INTERRUPT_MSI_SENT                            (cfg_interrupt_msi_sent), 
         .CFG_INTERRUPT_MSI_FAIL                            (cfg_interrupt_msi_fail), 
         .CFG_FC_CPLH                                       (cfg_fc_cplh[7:0]), 
         .CFG_FC_CPLD                                       (cfg_fc_cpld[11:0]), 
         .CFG_NEGOTIATED_WIDTH                              (cfg_negotiated_width[3:0]),
         .CFG_CURRENT_SPEED                                 (cfg_current_speed[2:0]), 
         .CFG_MAX_PAYLOAD                                   (cfg_max_payload[2:0]), 
         .CFG_MAX_READ_REQ                                  (cfg_max_read_req[2:0]),
         .CFG_FUNCTION_STATUS                               (cfg_function_status[7:0]), 
         .CFG_RCB_STATUS                                    (cfg_rcb_status[1:0]), 
         
         .CHNL_RX_CLK                                       (chnl_rx_clk),
         .CHNL_RX_ACK                                       (chnl_rx_ack),
         .CHNL_RX_DATA_REN                                  (chnl_rx_data_ren),
         .CHNL_TX_CLK                                       (chnl_tx_clk),
         .CHNL_TX                                           (chnl_tx),
         .CHNL_TX_LAST                                      (chnl_tx_last),
         .CHNL_TX_LEN                                       (chnl_tx_len),
         .CHNL_TX_OFF                                       (chnl_tx_off),
         .CHNL_TX_DATA                                      (chnl_tx_data),
         .CHNL_TX_DATA_VALID                                (chnl_tx_data_valid)
         );


 axis_sume_attachment_top #(
     .C_PCI_DATA_WIDTH                                      (C_PCI_DATA_WIDTH),     
     .C_AXIS_TDATA_WIDTH                                      (C_AXIS_TDATA_WIDTH),
     .C_AXIS_TKEEP_WIDTH                                      (C_AXIS_TKEEP_WIDTH),
     .C_AXIS_TUSER_WIDTH                                      (C_AXIS_TUSER_WIDTH),
     .C_PREAM_VALUE                                         (C_PREAM_VALUE)
 ) riffa_axis_attachment (

     .CLK                                                   (user_clk),
     .RST                                                   (rst_out),
     
     .CHNL_RX_CLK                                           (chnl_rx_clk[axis_chnl_num_lp]), 
     .CHNL_RX                                               (chnl_rx[axis_chnl_num_lp]), 
     .CHNL_RX_ACK                                           (chnl_rx_ack[axis_chnl_num_lp]), 
     .CHNL_RX_LAST                                          (chnl_rx_last[axis_chnl_num_lp]), 
     .CHNL_RX_LEN                                           (chnl_rx_len[(`SIG_CHNL_LENGTH_W*axis_chnl_num_lp) +:32]), 
     .CHNL_RX_OFF                                           (chnl_rx_off[(`SIG_CHNL_OFFSET_W*axis_chnl_num_lp) +:31]), 
     .CHNL_RX_DATA                                          (chnl_rx_data[(C_PCI_DATA_WIDTH*axis_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
     .CHNL_RX_DATA_VALID                                    (chnl_rx_data_valid[axis_chnl_num_lp]), 
     .CHNL_RX_DATA_REN                                      (chnl_rx_data_ren[axis_chnl_num_lp]),
 
     .CHNL_TX_CLK                                           (chnl_tx_clk[axis_chnl_num_lp]), 
     .CHNL_TX                                               (chnl_tx[axis_chnl_num_lp]), 
     .CHNL_TX_ACK                                           (chnl_tx_ack[axis_chnl_num_lp]), 
     .CHNL_TX_LAST                                          (chnl_tx_last[axis_chnl_num_lp]), 
     .CHNL_TX_LEN                                           (chnl_tx_len[(`SIG_CHNL_LENGTH_W*axis_chnl_num_lp) +:32]), 
     .CHNL_TX_OFF                                           (chnl_tx_off[(`SIG_CHNL_OFFSET_W*axis_chnl_num_lp) +:31]), 
     .CHNL_TX_DATA                                          (chnl_tx_data[(C_PCI_DATA_WIDTH*axis_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
     .CHNL_TX_DATA_VALID                                    (chnl_tx_data_valid[axis_chnl_num_lp]), 
     .CHNL_TX_DATA_REN                                      (chnl_tx_data_ren[axis_chnl_num_lp]),  
 

    .m_axis_xge_tx_tdata                                    (m_axis_xge_tx_tdata),
    .m_axis_xge_tx_tkeep                                    (m_axis_xge_tx_tkeep), 
    .m_axis_xge_tx_tuser                                    (m_axis_xge_tx_tuser),
    .m_axis_xge_tx_tlast                                    (m_axis_xge_tx_tlast), 
    .m_axis_xge_tx_tvalid                                   (m_axis_xge_tx_tvalid), 
    .m_axis_xge_tx_tready                                   (m_axis_xge_tx_tready),            
    
    .s_axis_xge_rx_tdata                                    (s_axis_xge_rx_tdata), 
    .s_axis_xge_rx_tkeep                                    (s_axis_xge_rx_tkeep),
    .s_axis_xge_rx_tuser                                    (s_axis_xge_rx_tuser),
    .s_axis_xge_rx_tlast                                    (s_axis_xge_rx_tlast), 
    .s_axis_xge_rx_tvalid                                   (s_axis_xge_rx_tvalid),   
    .s_axis_xge_rx_tready                                   (s_axis_xge_rx_tready)
 );


riffa_axi_lite #(
    .C_PCI_DATA_WIDTH                                         (C_PCI_DATA_WIDTH),
    .C_M_AXI_LITE_ADDR_WIDTH                                  (C_M_AXI_LITE_ADDR_WIDTH),
    .C_M_AXI_LITE_DATA_WIDTH                                  (C_M_AXI_LITE_DATA_WIDTH),
    .C_M_AXI_LITE_STRB_WIDTH                                  (C_M_AXI_LITE_STRB_WIDTH)
) riffa_axi_lite_attachment (
    .CLK                                                      (user_clk),
    .RST                                                      (rst_out),
  
    .CHNL_RX_CLK                                              (chnl_rx_clk[axi_lite_chnl_num_lp]), 
    .CHNL_RX                                                  (chnl_rx[axi_lite_chnl_num_lp]), 
    .CHNL_RX_ACK                                              (chnl_rx_ack[axi_lite_chnl_num_lp]), 
    .CHNL_RX_LAST                                             (chnl_rx_last[axi_lite_chnl_num_lp]), 
    .CHNL_RX_LEN                                              (chnl_rx_len[(`SIG_CHNL_LENGTH_W*axi_lite_chnl_num_lp) +:32]), 
    .CHNL_RX_OFF                                              (chnl_rx_off[(`SIG_CHNL_OFFSET_W*axi_lite_chnl_num_lp) +:31]), 
    .CHNL_RX_DATA                                             (chnl_rx_data[(C_PCI_DATA_WIDTH*axi_lite_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
    .CHNL_RX_DATA_VALID                                       (chnl_rx_data_valid[axi_lite_chnl_num_lp]), 
    .CHNL_RX_DATA_REN                                         (chnl_rx_data_ren[axi_lite_chnl_num_lp]),
  
    .CHNL_TX_CLK                                              (chnl_tx_clk[axi_lite_chnl_num_lp]), 
    .CHNL_TX                                                  (chnl_tx[axi_lite_chnl_num_lp]), 
    .CHNL_TX_ACK                                              (chnl_tx_ack[axi_lite_chnl_num_lp]), 
    .CHNL_TX_LAST                                             (chnl_tx_last[axi_lite_chnl_num_lp]), 
    .CHNL_TX_LEN                                              (chnl_tx_len[(`SIG_CHNL_LENGTH_W*axi_lite_chnl_num_lp) +:32]), 
    .CHNL_TX_OFF                                              (chnl_tx_off[(`SIG_CHNL_OFFSET_W*axi_lite_chnl_num_lp) +:31]), 
    .CHNL_TX_DATA                                             (chnl_tx_data[(C_PCI_DATA_WIDTH*axi_lite_chnl_num_lp) +:C_PCI_DATA_WIDTH]), 
    .CHNL_TX_DATA_VALID                                       (chnl_tx_data_valid[axi_lite_chnl_num_lp]), 
    .CHNL_TX_DATA_REN                                         (chnl_tx_data_ren[axi_lite_chnl_num_lp]),
  

    .m_axi_lite_aclk                                          (m_axi_lite_aclk),
    .m_axi_lite_aresetn                                       (m_axi_lite_aresetn),
  
    .m_axi_lite_arready                                       (m_axi_lite_arready),
    .m_axi_lite_arvalid                                       (m_axi_lite_arvalid),
    .m_axi_lite_araddr                                        (m_axi_lite_araddr),
    .m_axi_lite_arprot                                        (m_axi_lite_arprot),

    .m_axi_lite_rready                                        (m_axi_lite_rready),
    .m_axi_lite_rvalid                                        (m_axi_lite_rvalid),
    .m_axi_lite_rdata                                         (m_axi_lite_rdata),
    .m_axi_lite_rresp                                         (m_axi_lite_rresp),
      
    .m_axi_lite_awready                                       (m_axi_lite_awready),
    .m_axi_lite_awvalid                                       (m_axi_lite_awvalid),
    .m_axi_lite_awaddr                                        (m_axi_lite_awaddr),
    .m_axi_lite_awprot                                        (m_axi_lite_awprot),
  
    .m_axi_lite_wready                                        (m_axi_lite_wready),
    .m_axi_lite_wvalid                                        (m_axi_lite_wvalid),
    .m_axi_lite_wdata                                         (m_axi_lite_wdata),
    .m_axi_lite_wstrb                                         (m_axi_lite_wstrb),
    
    .m_axi_lite_bready                                        (m_axi_lite_bready),
    .m_axi_lite_bvalid                                        (m_axi_lite_bvalid),
    .m_axi_lite_bresp                                         (m_axi_lite_bresp),

    .md_error                                                 (md_error)
);



 nf_riffa_dma_cpu_regs 
 #(
     .C_BASE_ADDRESS        (C_BASEADDR ),
     .C_S_AXI_DATA_WIDTH    (C_S_AXI_DATA_WIDTH),
     .C_S_AXI_ADDR_WIDTH    (C_S_AXI_ADDR_WIDTH)
 ) nf_riffa_dma_cpu_regs_inst
 (   

    .clk                    (user_clk),
    .resetn                 (~user_reset),

    .S_AXI_ACLK             (user_clk),
    .S_AXI_ARESETN          (~user_reset),
    .S_AXI_AWADDR           (s_axi_lite_awaddr),
    .S_AXI_AWVALID          (s_axi_lite_awvalid),
    .S_AXI_WDATA            (s_axi_lite_wdata),
    .S_AXI_WSTRB            (s_axi_lite_wstrb),
    .S_AXI_WVALID           (s_axi_lite_wvalid),
    .S_AXI_BREADY           (s_axi_lite_bready),
    .S_AXI_ARADDR           (s_axi_lite_araddr),
    .S_AXI_ARVALID          (s_axi_lite_arvalid),
    .S_AXI_RREADY           (s_axi_lite_rready),
    .S_AXI_ARREADY          (s_axi_lite_arready),
    .S_AXI_RDATA            (s_axi_lite_rdata),
    .S_AXI_RRESP            (s_axi_lite_rresp),
    .S_AXI_RVALID           (s_axi_lite_rvalid),
    .S_AXI_WREADY           (s_axi_lite_wready),
    .S_AXI_BRESP            (s_axi_lite_bresp),
    .S_AXI_BVALID           (s_axi_lite_bvalid),
    .S_AXI_AWREADY          (s_axi_lite_awready),
   

   .id_reg          (id_reg),
   .version_reg          (version_reg),
   .reset_reg          (reset_reg),
   .ip2cpu_flip_reg          (ip2cpu_flip_reg),
   .cpu2ip_flip_reg          (cpu2ip_flip_reg),
   .ip2cpu_debug_reg          (ip2cpu_debug_reg),
   .cpu2ip_debug_reg          (cpu2ip_debug_reg),
   .rqpkt_reg          (rqpkt_reg),
   .rqpkt_reg_clear    (rqpkt_reg_clear),
   .rcpkt_reg          (rcpkt_reg),
   .rcpkt_reg_clear    (rcpkt_reg_clear),
   .cqpkt_reg          (cqpkt_reg),
   .cqpkt_reg_clear    (cqpkt_reg_clear),
   .ccpkt_reg          (ccpkt_reg),
   .ccpkt_reg_clear    (ccpkt_reg_clear),
   .xgetxpkt_reg          (xgetxpkt_reg),
   .xgetxpkt_reg_clear    (xgetxpkt_reg_clear),
   .xgerxpkt_reg          (xgerxpkt_reg),
   .xgerxpkt_reg_clear    (xgerxpkt_reg_clear),
   .pcierq_reg          (pcierq_reg),
   .pciephy_reg          (pciephy_reg),
   .pcieconfig_reg          (pcieconfig_reg),
   .pcieconfig2_reg          (pcieconfig2_reg),
   .pcieerror_reg          (pcieerror_reg),
   .pciemisc_reg          (pciemisc_reg),
   .pcietph_reg          (pcietph_reg),
   .pciefc1_reg          (pciefc1_reg),
   .pciefc2_reg          (pciefc2_reg),
   .pciefc3_reg          (pciefc3_reg),
   .pcieinterrupt_reg          (pcieinterrupt_reg),
   .pciemsidata_reg          (pciemsidata_reg),
   .pciemsiint_reg          (pciemsiint_reg),
   .pciemsipendingstatus_reg          (pciemsipendingstatus_reg),
   .pciemsipendingstatus2_reg          (pciemsipendingstatus2_reg),
   .pcieinterrupt2_reg          (pcieinterrupt2_reg),

   .cpu_resetn_soft(),
   .resetn_soft    (),
   .resetn_sync    (resetn_sync)
);


    assign     clear_counters = reset_reg[0];
    assign     reset_registers = reset_reg[4];



always @(posedge user_clk)
	if (user_reset | reset_registers) begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;
		rqpkt_reg <= #1    `REG_RQPKT_DEFAULT;
		rcpkt_reg <= #1    `REG_RCPKT_DEFAULT;
		cqpkt_reg <= #1    `REG_CQPKT_DEFAULT;
		ccpkt_reg <= #1    `REG_CCPKT_DEFAULT;
		xgetxpkt_reg <= #1    `REG_XGETXPKT_DEFAULT;
		xgerxpkt_reg <= #1    `REG_XGERXPKT_DEFAULT;
		pcierq_reg <= #1    `REG_PCIERQ_DEFAULT;
		pciephy_reg <= #1    `REG_PCIEPHY_DEFAULT;
		pcieconfig_reg <= #1    `REG_PCIECONFIG_DEFAULT;
		pcieconfig2_reg <= #1    `REG_PCIECONFIG2_DEFAULT;
		pcieerror_reg <= #1    `REG_PCIEERROR_DEFAULT;
		pciemisc_reg <= #1    `REG_PCIEMISC_DEFAULT;
		pcietph_reg <= #1    `REG_PCIETPH_DEFAULT;
		pciefc1_reg <= #1    `REG_PCIEFC1_DEFAULT;
		pciefc2_reg <= #1    `REG_PCIEFC2_DEFAULT;
		pciefc3_reg <= #1    `REG_PCIEFC3_DEFAULT;
		pcieinterrupt_reg <= #1    `REG_PCIEINTERRUPT_DEFAULT;
		pciemsidata_reg <= #1    `REG_PCIEMSIDATA_DEFAULT;
		pciemsiint_reg <= #1    `REG_PCIEMSIINT_DEFAULT;
		pciemsipendingstatus_reg <= #1    `REG_PCIEMSIPENDINGSTATUS_DEFAULT;
		pciemsipendingstatus2_reg <= #1    `REG_PCIEMSIPENDINGSTATUS2_DEFAULT;
		pcieinterrupt2_reg <= #1    `REG_PCIEINTERRUPT2_DEFAULT;
	end
	else begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    ~cpu2ip_flip_reg;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT+cpu2ip_debug_reg;
		              
		rqpkt_reg [`REG_RQPKT_WIDTH -2: 0] <= #1  clear_counters | rqpkt_reg_clear ? 'h0  : rqpkt_reg[`REG_RQPKT_WIDTH -2: 0] + (s_axis_rq_tlast && s_axis_rq_tvalid && s_axis_rq_tready) ;
		rqpkt_reg [`REG_RQPKT_WIDTH-1    ] <= #1  clear_counters | rqpkt_reg_clear ? 'h0  : rqpkt_reg[`REG_RQPKT_WIDTH-2:0] + (s_axis_rq_tlast && s_axis_rq_tvalid && s_axis_rq_tready)
				                                                     > {(`REG_RQPKT_WIDTH-1){1'b1}} ? 1'b1 : rqpkt_reg[`REG_RQPKT_WIDTH-1];
				                                                     
		rcpkt_reg [`REG_RCPKT_WIDTH -2: 0] <= #1  clear_counters | rcpkt_reg_clear ? 'h0  : rcpkt_reg[`REG_RCPKT_WIDTH -2: 0] + (m_axis_rc_tlast && m_axis_rc_tvalid && m_axis_rc_tready) ;
		rcpkt_reg [`REG_RCPKT_WIDTH-1    ] <= #1  clear_counters | rcpkt_reg_clear ? 'h0  : rcpkt_reg[`REG_RCPKT_WIDTH-2:0] + (m_axis_rc_tlast && m_axis_rc_tvalid && m_axis_rc_tready)
						                                                     > {(`REG_RCPKT_WIDTH-1){1'b1}} ? 1'b1 : rcpkt_reg[`REG_RCPKT_WIDTH-1];
						                                                     
		cqpkt_reg [`REG_CQPKT_WIDTH -2: 0] <= #1  clear_counters | cqpkt_reg_clear ? 'h0  : cqpkt_reg[`REG_CQPKT_WIDTH -2: 0] + (m_axis_cq_tlast && m_axis_cq_tvalid && m_axis_cq_tready) ;
		cqpkt_reg [`REG_CQPKT_WIDTH-1    ] <= #1  clear_counters | cqpkt_reg_clear ? 'h0  : cqpkt_reg[`REG_CQPKT_WIDTH-2:0] + (m_axis_cq_tlast && m_axis_cq_tvalid && m_axis_cq_tready)
						                                                     > {(`REG_CQPKT_WIDTH-1){1'b1}} ? 1'b1 : cqpkt_reg[`REG_CQPKT_WIDTH-1];
				                                                     
		ccpkt_reg [`REG_CCPKT_WIDTH -2: 0] <= #1  clear_counters | ccpkt_reg_clear ? 'h0  : ccpkt_reg[`REG_CCPKT_WIDTH -2: 0] + (s_axis_cc_tlast && s_axis_cc_tvalid && s_axis_cc_tready) ;
		ccpkt_reg [`REG_CCPKT_WIDTH-1    ] <= #1  clear_counters | ccpkt_reg_clear ? 'h0  : ccpkt_reg[`REG_CCPKT_WIDTH-2:0] + (s_axis_cc_tlast && s_axis_cc_tvalid && s_axis_cc_tready)
				                                                     > {(`REG_CCPKT_WIDTH-1){1'b1}} ? 1'b1 : ccpkt_reg[`REG_CCPKT_WIDTH-1];
	
		xgetxpkt_reg [`REG_XGETXPKT_WIDTH -2: 0] <= #1  clear_counters | xgetxpkt_reg_clear ? 'h0  : xgetxpkt_reg[`REG_XGETXPKT_WIDTH -2: 0] + (m_axis_xge_tx_tlast && m_axis_xge_tx_tvalid && m_axis_xge_tx_tready) ;
		xgetxpkt_reg [`REG_XGETXPKT_WIDTH-1    ] <= #1  clear_counters | xgetxpkt_reg_clear ? 'h0  : xgetxpkt_reg[`REG_XGETXPKT_WIDTH-2:0] + (m_axis_xge_tx_tlast && m_axis_xge_tx_tvalid && m_axis_xge_tx_tready) > {(`REG_XGETXPKT_WIDTH-1){1'b1}} ? 1'b1 : xgetxpkt_reg[`REG_XGETXPKT_WIDTH-1];
						                                                     
		xgerxpkt_reg [`REG_XGERXPKT_WIDTH -2: 0] <= #1  clear_counters | xgerxpkt_reg_clear ? 'h0  : xgerxpkt_reg[`REG_XGERXPKT_WIDTH -2: 0] + (s_axis_xge_rx_tlast && s_axis_xge_rx_tvalid && s_axis_xge_rx_tready) ;
		xgerxpkt_reg [`REG_XGERXPKT_WIDTH-1    ] <= #1  clear_counters | xgerxpkt_reg_clear ? 'h0  : xgerxpkt_reg[`REG_XGERXPKT_WIDTH-2:0] + (s_axis_xge_rx_tlast && s_axis_xge_rx_tvalid && s_axis_xge_rx_tready)> {(`REG_XGERXPKT_WIDTH-1){1'b1}} ? 1'b1 : xgerxpkt_reg[`REG_XGERXPKT_WIDTH-1];
						                                                     
		pcierq_reg [3:0]   <= #1    pcie_rq_seq_num_vld ? pcie_rq_seq_num : pcierq_reg [3:0];
		pcierq_reg [20:16] <= #1    pcie_rq_tag_vld ? pcie_rq_tag : pcierq_reg [20:16];
		
		pciephy_reg [2:0] <= #1   {cfg_phy_link_status,cfg_phy_link_down};
		pciephy_reg [19:16] <= #1   cfg_negotiated_width;
		
		pcieconfig_reg [2:0] <= #1     cfg_current_speed;
		pcieconfig_reg [6:4] <= #1     cfg_max_payload;
		pcieconfig_reg [10:8] <= #1     cfg_max_read_req;
		pcieconfig_reg [19:12] <= #1     cfg_function_status;
		pcieconfig_reg [25:20] <= #1     cfg_function_power_state;
		pcieconfig_reg [29:28] <= #1     cfg_link_power_state;
		
		pcieconfig2_reg [11:0] <= #1    cfg_vf_status;
		pcieconfig2_reg [29:12] <= #1    cfg_vf_power_state;		
		
		pcieerror_reg [0] <= #1    cfg_err_cor_out;
		pcieerror_reg [4] <= #1    cfg_err_nonfatal_out;
		pcieerror_reg [8] <= #1    cfg_err_fatal_out;

				
		pciemisc_reg [5:0]  <= #1    cfg_ltssm_state;
		pciemisc_reg [8]    <= #1    cfg_ltr_enable;
		pciemisc_reg [13:12]<= #1    cfg_rcb_status;		
		pciemisc_reg [17:16]<= #1    cfg_dpa_substate_change;
		pciemisc_reg [20]   <= #1    cfg_obff_enable;
		pciemisc_reg [24]   <= #1    cfg_pl_status_change;		
		
		pcietph_reg[1:0] <= #1    cfg_tph_requester_enable;
		pcietph_reg[7:2] <= #1    cfg_tph_st_mode;
		pcietph_reg[13:8] <= #1    cfg_vf_tph_requester_enable;
		pcietph_reg[31:14] <= #1    cfg_vf_tph_st_mode;					
		
		pciefc1_reg [7:0] <= #1    cfg_fc_ph;
		pciefc1_reg [19:8] <= #1    cfg_fc_pd;
		
		pciefc2_reg [7:0] <= #1    cfg_fc_nph;
		pciefc2_reg [19:8] <= #1    cfg_fc_npd;
		
		pciefc3_reg [7:0] <= #1    cfg_fc_cplh;
		pciefc3_reg [19:8] <= #1    cfg_fc_cpld;
		pciefc3_reg [22:20] <= #1    cfg_fc_sel;
		

		pcieinterrupt_reg [3:0] <= #1    cfg_interrupt_int;
		pcieinterrupt_reg [5:4] <= #1    cfg_interrupt_pending;
		pcieinterrupt_reg [8] <= #1    cfg_interrupt_sent;
		pcieinterrupt_reg [13:12] <= #1    cfg_interrupt_msi_enable;
		pcieinterrupt_reg [21:16] <= #1    cfg_interrupt_msi_vf_enable;
		pcieinterrupt_reg [29:24] <= #1    cfg_interrupt_msi_mmenable;
		pcieinterrupt_reg [31] <= #1    cfg_interrupt_msi_mask_update;
		
		pciemsidata_reg <= #1     cfg_interrupt_msi_data;
		
		pciemsiint_reg <= #1    cfg_interrupt_msi_int;
		
		pciemsipendingstatus_reg <= #1    cfg_interrupt_msi_pending_status[31:0];
		pciemsipendingstatus2_reg <= #1   cfg_interrupt_msi_pending_status[63:32];
		
		pcieinterrupt2_reg [3:0]  <= #1   cfg_interrupt_msi_select;
		pcieinterrupt2_reg [4]  <= #1   cfg_interrupt_msi_sent;
		pcieinterrupt2_reg [5]  <= #1   cfg_interrupt_msi_fail;
		pcieinterrupt2_reg [10:8]  <= #1   cfg_interrupt_msi_attr;
		pcieinterrupt2_reg [12]  <= #1   cfg_interrupt_msi_tph_present;
		pcieinterrupt2_reg [14:13]  <= #1   cfg_interrupt_msi_tph_type;
		pcieinterrupt2_reg [24:16]  <= #1   cfg_interrupt_msi_tph_st_tag;
		pcieinterrupt2_reg [30:28]  <= #1   cfg_interrupt_msi_function_number;
		
    end

    
endmodule