data/full_repos/permissive/500717851/verilog/rtl/merge_memory.sv
data/verilator_xmls/851335c7-f21a-4288-9c17-c9a0668054cc.xml
module merge_memory (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input         csb,
    input  [ 9:0] addr,
    output logic [31:0] dout,
    

    output logic        csb_mem0,
    output logic [ 8:0] addr_mem0,
    input  [31:0] dout_mem0,
    

    output logic        csb_mem1,
    output logic [ 8:0] addr_mem1,
    input  [31:0] dout_mem1
);
    assign csb_mem0 = csb;
    assign csb_mem1 = csb;
    
    assign addr_mem0 = addr[8:0];
    assign addr_mem1 = addr[8:0];

    always_comb begin
        if (addr[9] == 0) begin
            dout = dout_mem0;
        end else begin
            dout = dout_mem1;
        end
    end

endmodule
module merge_memory (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input         csb,
    input  [ 9:0] addr,
    output logic [31:0] dout,
    

    output logic        csb_mem0,
    output logic [ 8:0] addr_mem0,
    input  [31:0] dout_mem0,
    

    output logic        csb_mem1,
    output logic [ 8:0] addr_mem1,
    input  [31:0] dout_mem1
);

    assign csb_mem0 = csb;
    assign csb_mem1 = csb;
    
    assign addr_mem0 = addr[8:0];
    assign addr_mem1 = addr[8:0];

    always_comb begin
        if (addr[9] == 0) begin
            dout = dout_mem0;
        end else begin
            dout = dout_mem1;
        end
    end

endmodule