data/full_repos/permissive/493019833/test/testcase/firrtl/NestedModsWithReg/reference/NestedModsWithReg.v
data/verilator_xmls/df9e1374-d511-4bee-a424-b81a16869189.xml
module Top(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out1,
    output [15:0] out2,
    output [15:0] out3
);
    wire _level1__clk;
    wire _level1__reset;
    wire [15:0] _level1__in1;
    wire [15:0] _level1__out1;
    wire [15:0] _level1__out2;
    wire [15:0] _level1__out3;
    Level1 level1 (
        .clk(_level1__clk),
        .reset(_level1__reset),
        .in1(_level1__in1),
        .out1(_level1__out1),
        .out2(_level1__out2),
        .out3(_level1__out3)
    );
    assign _level1__clk = clk;
    assign _level1__in1 = in1;
    assign _level1__reset = reset;
    assign out1 = _level1__out1;
    assign out2 = _level1__out2;
    assign out3 = _level1__out3;
endmodule
module Top(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out1,
    output [15:0] out2,
    output [15:0] out3
);

    wire _level1__clk;
    wire _level1__reset;
    wire [15:0] _level1__in1;
    wire [15:0] _level1__out1;
    wire [15:0] _level1__out2;
    wire [15:0] _level1__out3;
    Level1 level1 (
        .clk(_level1__clk),
        .reset(_level1__reset),
        .in1(_level1__in1),
        .out1(_level1__out1),
        .out2(_level1__out2),
        .out3(_level1__out3)
    );
    assign _level1__clk = clk;
    assign _level1__in1 = in1;
    assign _level1__reset = reset;
    assign out1 = _level1__out1;
    assign out2 = _level1__out2;
    assign out3 = _level1__out3;
endmodule