data/full_repos/permissive/481044442/BDCDrv/rx_bps_module.v
data/verilator_xmls/2b889382-9459-4115-99a7-d43ac5fdb420.xml
module rx_bps_module(clk,reset,bps_clk);
input clk;
input reset;
output bps_clk;





reg[7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset)
		counter<=8'd0;
	else if(counter==8'd127)
		counter<=8'd0;
	else 
		counter<=counter+1'b1;
end


assign bps_clk=(counter==8'd64)?1'b1:1'b0;
endmodule
module rx_bps_module(clk,reset,bps_clk);

input clk;
input reset;
output bps_clk;





reg[7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset)
		counter<=8'd0;
	else if(counter==8'd127)
		counter<=8'd0;
	else 
		counter<=counter+1'b1;
end


assign bps_clk=(counter==8'd64)?1'b1:1'b0;
endmodule