data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pulp_clock_gating_xilinx.sv
data/verilator_xmls/7ff2ce82-095c-4b63-8589-f528897dc8db.xml
module pulp_clock_gating
  (
   input  logic clk_i,
   input  logic en_i,
   input  logic test_en_i,
   output logic clk_o
   );

   assign clk_o = clk_i;
   
endmodule
module pulp_clock_gating
  (
   input  logic clk_i,
   input  logic en_i,
   input  logic test_en_i,
   output logic clk_o
   );


   assign clk_o = clk_i;
   
endmodule