data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/ClockDivider.v
data/verilator_xmls/ae394925-532f-4373-af64-f43b0f5cc075.xml
module ClockDivider(
    input cIn,
    input [31:0] reqCount,
    output reg cOut = 0
  );
  
  reg [31:0] counter = 32'h00000000;
  
  always @ (negedge cIn) begin
    if(counter == reqCount) begin
      cOut = ~cOut;
      counter = 0;
    end else begin
      counter = counter + 1;
    end
  end
  
endmodule
module ClockDivider(
    input cIn,
    input [31:0] reqCount,
    output reg cOut = 0
  );

  
  reg [31:0] counter = 32'h00000000;
  
  always @ (negedge cIn) begin
    if(counter == reqCount) begin
      cOut = ~cOut;
      counter = 0;
    end else begin
      counter = counter + 1;
    end
  end
  
endmodule