data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sources_1/new/Stack.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sources_1/new/Stack.v:47: Bit extraction of array[256:0] requires 9 bit index, not 8 bits.\n                                                                                                  : ... In instance Stack\n        mem[size] = din;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sources_1/new/Stack.v:44: Operator LT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'size\' generates 8 bits.\n                                                                                                  : ... In instance Stack\n    if(push && size < 256)\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sources_1/new/Stack.v:52: Bit extraction of array[256:0] requires 9 bit index, not 8 bits.\n                                                                                                  : ... In instance Stack\n        top = mem[size];\n                 ^\n%Error: Exiting due to 3 warning(s)\n'
module Stack(
    output reg [7:0] size,
    output reg [7:0] top,
    input push,
    input pop,
    input [7:0] din,
    input reset,
    input clock
);

reg [7:0] mem [256:0];

initial
begin
    top <= 0;
    size <= 0;
    mem[0] <= 0;
end

always @(posedge clock)
begin
    if(push && size < 256)
    begin
        size = size + 1;
        mem[size] = din;
    end

    if(pop && size > 0)
    begin
        top = mem[size];
        size = size - 1;
    end
    
    if(reset)
    begin
        size <= 0;
        top <= 0;
    end
end
endmodule
module Stack(
    output reg [7:0] size,
    output reg [7:0] top,
    input push,
    input pop,
    input [7:0] din,
    input reset,
    input clock
);


reg [7:0] mem [256:0];

initial
begin
    top <= 0;
    size <= 0;
    mem[0] <= 0;
end

always @(posedge clock)
begin
    if(push && size < 256)
    begin
        size = size + 1;
        mem[size] = din;
    end

    if(pop && size > 0)
    begin
        top = mem[size];
        size = size - 1;
    end
    
    if(reset)
    begin
        size <= 0;
        top <= 0;
    end
end
endmodule