data/full_repos/permissive/505236095/fw/rtl/n64rgb_flex.v
data/verilator_xmls/178275b6-af34-448b-b166-f91a5ad04503.xml
module n64rgb_flex(
  VCLK_i,
  nDSYNC_i,
  D_i,
  nViDeBlur_i,
  R_o,
  G_o,
  B_o,
  nCSYNC_o
);

input VCLK_i;
input nDSYNC_i;
input [6:0] D_i;
input nViDeBlur_i;
output reg [6:0] R_o;
output reg [6:0] G_o;
output reg [6:0] B_o;
output reg nCSYNC_o;



wire VCLK_w;
wire negedge_nVSYNC_w, negedge_nHSYNC_w, posedge_nCSYNC_w;


reg [3:0] SYNC_L;
reg [6:0] R_L [0:1];
reg [6:0] G_L [0:1];
reg [6:0] B_L [0:1];

reg [1:0] line_cnt = 2'b00;
reg        palmode = 1'b0;

reg field_id, n64_480i;

reg [1:0] phase_cnt = 2'b00;
reg nblank_vdata;


`ifdef USE_POSEDGE_VCLK
  assign VCLK_w = VCLK_i;
`else
  assign VCLK_w = ~VCLK_i;
`endif

assign negedge_nVSYNC_w =  SYNC_L[3] & !D_i[3];
assign negedge_nHSYNC_w =  SYNC_L[1] & !D_i[1];
assign posedge_nCSYNC_w = !SYNC_L[0] &  D_i[0];


always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if(negedge_nVSYNC_w) begin
      line_cnt <= 2'b00;
      palmode <= ~line_cnt[1];
    end else if (negedge_nHSYNC_w) begin
      line_cnt <= line_cnt + 1'b1;
    end
  end
  
always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if (negedge_nVSYNC_w) begin
      field_id <= negedge_nHSYNC_w;
      n64_480i <= field_id ^ negedge_nHSYNC_w;
    end
  end
  
always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if (nViDeBlur_i | n64_480i) begin
      nblank_vdata <= 1'b1;
    end else begin
      if(posedge_nCSYNC_w)
        nblank_vdata <= palmode;
      else
        nblank_vdata <= ~nblank_vdata;
    end
  end

always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    phase_cnt <= 2'b00;
    SYNC_L <= D_i[3:0];
    if (nblank_vdata) begin
      R_L[1] <= R_L[0];
      G_L[1] <= G_L[0];
      B_L[1] <= B_L[0];
    end
  end else begin
    casez(phase_cnt)
      2'b00: R_L[0] <= D_i;
      2'b01: G_L[0] <= D_i;
      2'b10: B_L[0] <= D_i;
    endcase
    phase_cnt <= phase_cnt + 2'b01;
  end

always @(SYNC_L,R_L[1],G_L[1],B_L[1]) begin
  nCSYNC_o <= SYNC_L[0];
  {R_o,G_o,B_o} <= {R_L[1],G_L[1],B_L[1]};
end

endmodule
module n64rgb_flex(
  VCLK_i,
  nDSYNC_i,
  D_i,
  nViDeBlur_i,
  R_o,
  G_o,
  B_o,
  nCSYNC_o
);


input VCLK_i;
input nDSYNC_i;
input [6:0] D_i;
input nViDeBlur_i;
output reg [6:0] R_o;
output reg [6:0] G_o;
output reg [6:0] B_o;
output reg nCSYNC_o;



wire VCLK_w;
wire negedge_nVSYNC_w, negedge_nHSYNC_w, posedge_nCSYNC_w;


reg [3:0] SYNC_L;
reg [6:0] R_L [0:1];
reg [6:0] G_L [0:1];
reg [6:0] B_L [0:1];

reg [1:0] line_cnt = 2'b00;
reg        palmode = 1'b0;

reg field_id, n64_480i;

reg [1:0] phase_cnt = 2'b00;
reg nblank_vdata;


`ifdef USE_POSEDGE_VCLK
  assign VCLK_w = VCLK_i;
`else
  assign VCLK_w = ~VCLK_i;
`endif

assign negedge_nVSYNC_w =  SYNC_L[3] & !D_i[3];
assign negedge_nHSYNC_w =  SYNC_L[1] & !D_i[1];
assign posedge_nCSYNC_w = !SYNC_L[0] &  D_i[0];


always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if(negedge_nVSYNC_w) begin
      line_cnt <= 2'b00;
      palmode <= ~line_cnt[1];
    end else if (negedge_nHSYNC_w) begin
      line_cnt <= line_cnt + 1'b1;
    end
  end
  
always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if (negedge_nVSYNC_w) begin
      field_id <= negedge_nHSYNC_w;
      n64_480i <= field_id ^ negedge_nHSYNC_w;
    end
  end
  
always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    if (nViDeBlur_i | n64_480i) begin
      nblank_vdata <= 1'b1;
    end else begin
      if(posedge_nCSYNC_w)
        nblank_vdata <= palmode;
      else
        nblank_vdata <= ~nblank_vdata;
    end
  end

always @(posedge VCLK_w)
  if (!nDSYNC_i) begin
    phase_cnt <= 2'b00;
    SYNC_L <= D_i[3:0];
    if (nblank_vdata) begin
      R_L[1] <= R_L[0];
      G_L[1] <= G_L[0];
      B_L[1] <= B_L[0];
    end
  end else begin
    casez(phase_cnt)
      2'b00: R_L[0] <= D_i;
      2'b01: G_L[0] <= D_i;
      2'b10: B_L[0] <= D_i;
    endcase
    phase_cnt <= phase_cnt + 2'b01;
  end

always @(SYNC_L,R_L[1],G_L[1],B_L[1]) begin
  nCSYNC_o <= SYNC_L[0];
  {R_o,G_o,B_o} <= {R_L[1],G_L[1],B_L[1]};
end

endmodule