data/full_repos/permissive/503578084/pipeline/id_get_opposite.v
data/verilator_xmls/95d50f8a-40d7-465d-b4be-2dca78e75679.xml
module id_get_opposite(
    input   [31:0]  rD2,
    output  reg [31:0]  rD2_opposite
    );
    
wire  [30:0]  tmp;
wire    tmp31;
assign tmp=~rD2[30:0]+1;
assign  tmp31=(rD2==0 || rD2==32'h80000000)?rD2[31]:~rD2[31];
    
always @ (*) begin
    rD2_opposite={tmp31,tmp};
end
    
endmodule
module id_get_opposite(
    input   [31:0]  rD2,
    output  reg [31:0]  rD2_opposite
    );

    
wire  [30:0]  tmp;
wire    tmp31;
assign tmp=~rD2[30:0]+1;
assign  tmp31=(rD2==0 || rD2==32'h80000000)?rD2[31]:~rD2[31];
    
always @ (*) begin
    rD2_opposite={tmp31,tmp};
end
    
endmodule