data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v
1: b'%Error: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        { x, clk } = 2\'b00; #20;\n                            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        { x, clk } = 2\'b01; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        { x, clk } = 2\'b10; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        { x, clk } = 2\'b11; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        x=0; clk=0; #20;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        x=0; clk=1; #20;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        x=1; clk=0; #20;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/475928601/Assignments/mealey_sr_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        x=1; clk=1; #20;\n                    ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mealey_sr_tb;
    reg x, clk;
    wire z;

    mealey_sr uut(x, clk, z);

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(1);

        { x, clk } = 2'b00; #20;
        { x, clk } = 2'b01; #20;
        { x, clk } = 2'b10; #20;
        { x, clk } = 2'b11; #20;

        x=0; clk=0; #20;
        x=0; clk=1; #20;
        x=1; clk=0; #20;
        x=1; clk=1; #20;
    end

endmodule
module mealey_sr_tb;

    reg x, clk;
    wire z;

    mealey_sr uut(x, clk, z);

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(1);

        { x, clk } = 2'b00; #20;
        { x, clk } = 2'b01; #20;
        { x, clk } = 2'b10; #20;
        { x, clk } = 2'b11; #20;

        x=0; clk=0; #20;
        x=0; clk=1; #20;
        x=1; clk=0; #20;
        x=1; clk=1; #20;
    end

endmodule