data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/instr_rom.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/instr_rom.sv:3: Multiple top level modules\n                                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                         : ... Top module \'instr_rom\'\nmodule instr_rom(\n       ^~~~~~~~~\n                                                                                                         : ... Top module \'naive_bus\'\n    naive_bus.slave  bus\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/instr_rom.sv:3: Unsupported: Interfaced port on top level module\n    naive_bus.slave  bus\n                     ^~~\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/instr_rom.sv:3: Cannot find file containing interface: \'naive_bus\'\n    naive_bus.slave  bus\n    ^~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/RTL/instr_rom.sv:3: ../V3LinkDot.cpp:2055: Unlinked interface\n    naive_bus.slave  bus\n    ^~~~~~~~~\n'
module instr_rom(
    input  logic clk, rst_n,
    naive_bus.slave  bus
);
localparam  INSTR_CNT = 30'd18;
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
    32'h000062b3,
    32'h000302b7,
    32'h06806313,
    32'h00628023,
    32'h06506313,
    32'h00628023,
    32'h06c06313,
    32'h00628023,
    32'h06c06313,
    32'h00628023,
    32'h06f06313,
    32'h00628023,
    32'h00a06313,
    32'h00628023,
    32'h00c003b7,
    32'hfff38393,
    32'hfe039ee3,
    32'hfc5ff06f
};

logic [29:0] cell_rd_addr;

assign bus.rd_gnt = bus.rd_req;
assign bus.wr_gnt = bus.wr_req;
assign cell_rd_addr = bus.rd_addr[31:2];
always @ (posedge clk or negedge rst_n)
    if(~rst_n)
        bus.rd_data <= 0;
    else begin
        if(bus.rd_req)
            bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
        else
            bus.rd_data <= 0;
        end

endmodule
module instr_rom(
    input  logic clk, rst_n,
    naive_bus.slave  bus
);

localparam  INSTR_CNT = 30'd18;
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
    32'h000062b3,
    32'h000302b7,
    32'h06806313,
    32'h00628023,
    32'h06506313,
    32'h00628023,
    32'h06c06313,
    32'h00628023,
    32'h06c06313,
    32'h00628023,
    32'h06f06313,
    32'h00628023,
    32'h00a06313,
    32'h00628023,
    32'h00c003b7,
    32'hfff38393,
    32'hfe039ee3,
    32'hfc5ff06f
};

logic [29:0] cell_rd_addr;

assign bus.rd_gnt = bus.rd_req;
assign bus.wr_gnt = bus.wr_req;
assign cell_rd_addr = bus.rd_addr[31:2];
always @ (posedge clk or negedge rst_n)
    if(~rst_n)
        bus.rd_data <= 0;
    else begin
        if(bus.rd_req)
            bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
        else
            bus.rd_data <= 0;
        end

endmodule