data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv
1: b"%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv:10: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv:78: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv:82: syntax error, unexpected if\n    if (test_running) begin\n    ^~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv:93: syntax error, unexpected IDENTIFIER\n                full_filename = test_file;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/riscv_runtests.sv:110: syntax error, unexpected force\n         force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1;\n         ^~~~~\n%Error: Exiting due to 5 error(s)\n"
function logic [2047:0] remove_trailing_whitespaces (logic [2047:0] str);
        int i;
        begin
            for (i = 0; i <= 2040; i += 8) begin
                if (str[i+:8] != 8'h20) begin
                    break;
                end
            end
            str = str >> i;
            return str;
        end
        endfunction
function logic [2047:0] remove_trailing_whitespaces (logic [2047:0] str);

        int i;
        begin
            for (i = 0; i <= 2040; i += 8) begin
                if (str[i+:8] != 8'h20) begin
                    break;
                end
            end
            str = str >> i;
            return str;
        end
        endfunction