data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v
1: b'%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:66: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance f2m_mul\n        cnt <= 1\'b0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:68: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance f2m_mul\n        cnt <= 1\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:100: Operator ASSIGNDLY expects 165 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 163 bits.\n                                                                          : ... In instance f2m_mul\n        b_r <= b;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:106: Operator SHIFTL expects 218 bits on the LHS, but LHS\'s VARREF \'z_r\' generates 163 bits.\n                                                                          : ... In instance f2m_mul\nassign z_mul_r = z_r << SEG_BITS;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:109: Operator ASSIGN expects 218 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance f2m_mul\n    a_mul_b = 1\'b0;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:112: Operator AND expects 218 bits on the LHS, but LHS\'s VARREF \'a_r\' generates 163 bits.\n                                                                          : ... In instance f2m_mul\n        t = (a_r & {M{b_seg[j1]}}) << j1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:112: Operator AND expects 218 bits on the RHS, but RHS\'s REPLICATE generates 163 bits.\n                                                                          : ... In instance f2m_mul\n        t = (a_r & {M{b_seg[j1]}}) << j1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_mul.v:128: Operator ASSIGNDLY expects 163 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance f2m_mul\n        z_r <= 1\'b0;\n            ^~\n%Error: Exiting due to 8 warning(s)\n'
module f2m_mul #(
    parameter M = 163,
    parameter FX = 163'hc9,
    parameter NUM_SEG = 3
)
(

    input clk,
    input rst_n,
    input clr,


    input start,
    input [M-1:0] a,
    input [M-1:0] b,
    output reg done,
    output [M-1:0] z
);


localparam SEG_BITS = (M % NUM_SEG == 0) ? (M / NUM_SEG) : (M / NUM_SEG + 1);
localparam TOT_BITS = SEG_BITS * NUM_SEG;
localparam CNT_WIDTH = $clog2(NUM_SEG);



wire [M-1:0] xpow [SEG_BITS-1:0];
genvar i;
reg en;
reg [CNT_WIDTH-1:0] cnt;
reg [M-1:0] a_r;
reg [TOT_BITS-1:0] b_r;
wire [SEG_BITS-1:0] b_seg;
wire [M+SEG_BITS-1:0] z_mul_r;
reg [M+SEG_BITS-1:0] a_mul_b;
integer j1, j2;
wire [M+SEG_BITS-1:0] z_sum;
reg [M-1:0] z_red;
reg [M-1:0] z_r;



generate
    assign xpow[0] = FX;
    for (i = 1; i <= SEG_BITS-1; i = i + 1) begin : gen_xpow
        assign xpow[i] = {xpow[i-1][M-2:0], 1'b0} ^ (FX & {M{xpow[i-1][M-1]}});
    end
endgenerate



always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt <= 1'b0;
    else if (clr | start)
        cnt <= 1'b0;
    else if (en)
        cnt <= cnt + 1'b1;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        en <= 1'b0;
    else if (clr)
        en <= 1'b0;
    else if (start)
        en <= 1'b1;
    else if (cnt == NUM_SEG - 1)
        en <= 1'b0;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        done <= 1'b0;
    else if (clr | start)
        done <= 1'b0;
    else if (cnt == NUM_SEG - 1)
        done <= 1'b1;
end

always @ (posedge clk) begin
    if (start)
        a_r <= a;
end

always @ (posedge clk) begin
    if (start)
        b_r <= b;
    else if (en)
        b_r <= b_r << SEG_BITS;
end

assign b_seg = b_r[TOT_BITS-1:TOT_BITS-SEG_BITS];
assign z_mul_r = z_r << SEG_BITS;

always @ (*) begin
    a_mul_b = 1'b0;
    for (j1 = 0; j1 <= SEG_BITS-1; j1 = j1 + 1) begin : gen_a_mul_b
        reg [M+SEG_BITS-1:0] t;
        t = (a_r & {M{b_seg[j1]}}) << j1;
        a_mul_b = a_mul_b ^ t;
    end
end

assign z_sum = z_mul_r ^ a_mul_b;

always @ (*) begin
    z_red = z_sum[M-1:0];
    for (j2 = M; j2 <= M+SEG_BITS-1; j2 = j2 + 1) begin
        z_red = z_red ^ (xpow[j2 - M] & {M{z_sum[j2]}});
    end
end

always @ (posedge clk) begin
    if (start)
        z_r <= 1'b0;
    else if (en)
        z_r <= z_red;
end

assign z = z_r;


endmodule
module f2m_mul #(
    parameter M = 163,
    parameter FX = 163'hc9,
    parameter NUM_SEG = 3
)
(

    input clk,
    input rst_n,
    input clr,


    input start,
    input [M-1:0] a,
    input [M-1:0] b,
    output reg done,
    output [M-1:0] z
);



localparam SEG_BITS = (M % NUM_SEG == 0) ? (M / NUM_SEG) : (M / NUM_SEG + 1);
localparam TOT_BITS = SEG_BITS * NUM_SEG;
localparam CNT_WIDTH = $clog2(NUM_SEG);



wire [M-1:0] xpow [SEG_BITS-1:0];
genvar i;
reg en;
reg [CNT_WIDTH-1:0] cnt;
reg [M-1:0] a_r;
reg [TOT_BITS-1:0] b_r;
wire [SEG_BITS-1:0] b_seg;
wire [M+SEG_BITS-1:0] z_mul_r;
reg [M+SEG_BITS-1:0] a_mul_b;
integer j1, j2;
wire [M+SEG_BITS-1:0] z_sum;
reg [M-1:0] z_red;
reg [M-1:0] z_r;



generate
    assign xpow[0] = FX;
    for (i = 1; i <= SEG_BITS-1; i = i + 1) begin : gen_xpow
        assign xpow[i] = {xpow[i-1][M-2:0], 1'b0} ^ (FX & {M{xpow[i-1][M-1]}});
    end
endgenerate



always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt <= 1'b0;
    else if (clr | start)
        cnt <= 1'b0;
    else if (en)
        cnt <= cnt + 1'b1;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        en <= 1'b0;
    else if (clr)
        en <= 1'b0;
    else if (start)
        en <= 1'b1;
    else if (cnt == NUM_SEG - 1)
        en <= 1'b0;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        done <= 1'b0;
    else if (clr | start)
        done <= 1'b0;
    else if (cnt == NUM_SEG - 1)
        done <= 1'b1;
end

always @ (posedge clk) begin
    if (start)
        a_r <= a;
end

always @ (posedge clk) begin
    if (start)
        b_r <= b;
    else if (en)
        b_r <= b_r << SEG_BITS;
end

assign b_seg = b_r[TOT_BITS-1:TOT_BITS-SEG_BITS];
assign z_mul_r = z_r << SEG_BITS;

always @ (*) begin
    a_mul_b = 1'b0;
    for (j1 = 0; j1 <= SEG_BITS-1; j1 = j1 + 1) begin : gen_a_mul_b
        reg [M+SEG_BITS-1:0] t;
        t = (a_r & {M{b_seg[j1]}}) << j1;
        a_mul_b = a_mul_b ^ t;
    end
end

assign z_sum = z_mul_r ^ a_mul_b;

always @ (*) begin
    z_red = z_sum[M-1:0];
    for (j2 = M; j2 <= M+SEG_BITS-1; j2 = j2 + 1) begin
        z_red = z_red ^ (xpow[j2 - M] & {M{z_sum[j2]}});
    end
end

always @ (posedge clk) begin
    if (start)
        z_r <= 1'b0;
    else if (en)
        z_r <= z_red;
end

assign z = z_r;


endmodule