data/full_repos/permissive/424312442/lab_6_digital clock/sources_1/new/clock.v
1: b'%Error: Cannot find file containing module: clock/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             clock/sources_1/new,data/full_repos/permissive/424312442\n             clock/sources_1/new,data/full_repos/permissive/424312442.v\n             clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_6_digital\n%Error: Cannot find file containing module: clock/sources_1/new/clock.v\n%Error: Exiting due to 3 error(s)\n'
module clock_mod(clk, BCD0, BCD1, BCD2, BCD3);
input clk;
output [3:0] BCD0;
output [3:0] BCD1;
output [3:0] BCD2;
output [3:0] BCD3;

reg [3:0] BCD0 = 0;
reg [3:0] BCD1 = 0;
reg [3:0] BCD2 = 2;
reg [3:0] BCD3 = 1;
wire c0;
reg [8:0] sm = 0;


clock_divider (clk, c0);
always @(posedge c0) begin
    sm <= sm + 1;
    if (sm == 59) begin
        sm <= 0;
        BCD0 <= BCD0 + 1;
        if (BCD0 == 9) begin
            BCD0 <= 0;
            BCD1 <= BCD1 + 1;
            if (BCD1 == 5) begin
                BCD1 <= 0;
                BCD2 <= BCD2 + 1;
                if (BCD2 == 9) begin
                    BCD2 <= 0;
                    BCD3 <= BCD3 + 1;
                end 
                else if ((BCD3 == 1) && (BCD2 == 2)) begin  

                    BCD2 <= 1;
                    BCD3 <= 0;
                end
            end
        end
    end
end
endmodule
module clock_mod(clk, BCD0, BCD1, BCD2, BCD3);

input clk;
output [3:0] BCD0;
output [3:0] BCD1;
output [3:0] BCD2;
output [3:0] BCD3;

reg [3:0] BCD0 = 0;
reg [3:0] BCD1 = 0;
reg [3:0] BCD2 = 2;
reg [3:0] BCD3 = 1;
wire c0;
reg [8:0] sm = 0;


clock_divider (clk, c0);
always @(posedge c0) begin
    sm <= sm + 1;
    if (sm == 59) begin
        sm <= 0;
        BCD0 <= BCD0 + 1;
        if (BCD0 == 9) begin
            BCD0 <= 0;
            BCD1 <= BCD1 + 1;
            if (BCD1 == 5) begin
                BCD1 <= 0;
                BCD2 <= BCD2 + 1;
                if (BCD2 == 9) begin
                    BCD2 <= 0;
                    BCD3 <= BCD3 + 1;
                end 
                else if ((BCD3 == 1) && (BCD2 == 2)) begin  

                    BCD2 <= 1;
                    BCD3 <= 0;
                end
            end
        end
    end
end
endmodule