data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:47: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:57: syntax error, unexpected \'@\'\n            while (~io_ready) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:69: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:78: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:79: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/494148647/src/mbiobus/bench/iobus_master_model.v:88: syntax error, unexpected \'@\'\n            while (~io_ready) @(posedge clk);\n                              ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iobus_master_model(
    input  clk,
    input  rst,
    output reg io_addr_strobe,
    output reg io_read_strobe,
    output reg io_write_strobe,
    output reg [3:0] io_byte_en,
    output reg [31:0] io_addr,
    output reg [31:0] io_write_data,
    input  [31:0] io_read_data,
    input  io_ready
    );


    reg [31:0] tmp;

    initial begin
        io_addr = 32'b0;
        io_addr_strobe = 1'b0;
        io_read_strobe = 1'b0;
        io_write_strobe = 1'b0;
        io_byte_en = 3'b0;
        io_write_data = 32'b0;
    end

    task io_read;
        input  [31:0] addr;
        output [31:0] data;
        begin

            #1;
            io_addr = addr;
            io_addr_strobe = 1'b1;
            io_read_strobe = 1'b1;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b1111;
            io_write_data = 32'b0;


            @(posedge clk);
            #1;
            io_addr = 32'b0;
            io_addr_strobe = 1'b0;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b0;
            io_write_data = 32'b0;


            while (~io_ready) @(posedge clk);


            data = io_read_data;
        end
    endtask

    task io_write;
        input [31:0] addr;
        input [31:0] data;
        begin

            #1;
            io_addr = addr;
            io_addr_strobe = 1'b1;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b1;
            io_byte_en = 4'b1111;
            io_write_data = data;


            @(posedge clk);
            #1;
            io_addr = 32'b0;
            io_addr_strobe = 1'b0;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b0;
            io_write_data = 32'b0;


            while (~io_ready) @(posedge clk);
        end
    endtask

    task io_check;
        input [31:0] addr;
        input [31:0] exp_data;
        begin
            io_read(addr, tmp);
            if (tmp != exp_data)
                $display("%t: io_check failure, expected %h, got %h", $time, exp_data, tmp);
        end
    endtask

endmodule
module iobus_master_model(
    input  clk,
    input  rst,
    output reg io_addr_strobe,
    output reg io_read_strobe,
    output reg io_write_strobe,
    output reg [3:0] io_byte_en,
    output reg [31:0] io_addr,
    output reg [31:0] io_write_data,
    input  [31:0] io_read_data,
    input  io_ready
    );



    reg [31:0] tmp;

    initial begin
        io_addr = 32'b0;
        io_addr_strobe = 1'b0;
        io_read_strobe = 1'b0;
        io_write_strobe = 1'b0;
        io_byte_en = 3'b0;
        io_write_data = 32'b0;
    end

    task io_read;
        input  [31:0] addr;
        output [31:0] data;
        begin

            #1;
            io_addr = addr;
            io_addr_strobe = 1'b1;
            io_read_strobe = 1'b1;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b1111;
            io_write_data = 32'b0;


            @(posedge clk);
            #1;
            io_addr = 32'b0;
            io_addr_strobe = 1'b0;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b0;
            io_write_data = 32'b0;


            while (~io_ready) @(posedge clk);


            data = io_read_data;
        end
    endtask

    task io_write;
        input [31:0] addr;
        input [31:0] data;
        begin

            #1;
            io_addr = addr;
            io_addr_strobe = 1'b1;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b1;
            io_byte_en = 4'b1111;
            io_write_data = data;


            @(posedge clk);
            #1;
            io_addr = 32'b0;
            io_addr_strobe = 1'b0;
            io_read_strobe = 1'b0;
            io_write_strobe = 1'b0;
            io_byte_en = 4'b0;
            io_write_data = 32'b0;


            while (~io_ready) @(posedge clk);
        end
    endtask

    task io_check;
        input [31:0] addr;
        input [31:0] exp_data;
        begin
            io_read(addr, tmp);
            if (tmp != exp_data)
                $display("%t: io_check failure, expected %h, got %h", $time, exp_data, tmp);
        end
    endtask

endmodule