data/full_repos/permissive/491573622/ext_dm.v
1: b'%Error: data/full_repos/permissive/491573622/ext_dm.v:29: syntax error, unexpected byte, expecting IDENTIFIER or do or final\n    wire [7:0] byte;\n               ^~~~\n%Error: data/full_repos/permissive/491573622/ext_dm.v:31: syntax error, unexpected byte, expecting TYPE-IDENTIFIER\n    assign byte = (byte_addr == 2\'b00) ? din[7:0]:\n           ^~~~\n%Error: data/full_repos/permissive/491573622/ext_dm.v:41: syntax error, unexpected \'[\', expecting "\'{"\n                  (ext_dm == 3\'b001) ? {{24{byte[7]}}, byte}:\n                                                ^\n%Error: Exiting due to 3 error(s)\n'
module ext_dm(
    input [1:0] byte_addr,
    input [2:0] ext_dm,
    input [31:0] din,
    output [31:0] dout
    );
    wire [7:0] byte;
    wire [15:0] half_byte;
    assign byte = (byte_addr == 2'b00) ? din[7:0]:
                 (byte_addr == 2'b01) ? din[15:8]:
                (byte_addr == 2'b10) ? din[23:16]:
                (byte_addr == 2'b11) ? din[31:24]:
                                                0;
                                                
    assign half_byte = (byte_addr[1] == 0) ? din[15:0]:
                      (byte_addr[1] == 1) ? din[31:16]:
                                                     0;
    assign dout = (ext_dm == 3'b000) ? din:
                  (ext_dm == 3'b001) ? {{24{byte[7]}}, byte}:
                  (ext_dm == 3'b010) ? {{24{1'b0}}, byte}:
                  (ext_dm == 3'b011) ? {{16{half_byte[15]}}, half_byte}:
                  (ext_dm == 3'b100) ? {{16{1'b0}}, half_byte}:
                                                         32'h0;
    
endmodule
module ext_dm(
    input [1:0] byte_addr,
    input [2:0] ext_dm,
    input [31:0] din,
    output [31:0] dout
    );

    wire [7:0] byte;
    wire [15:0] half_byte;
    assign byte = (byte_addr == 2'b00) ? din[7:0]:
                 (byte_addr == 2'b01) ? din[15:8]:
                (byte_addr == 2'b10) ? din[23:16]:
                (byte_addr == 2'b11) ? din[31:24]:
                                                0;
                                                
    assign half_byte = (byte_addr[1] == 0) ? din[15:0]:
                      (byte_addr[1] == 1) ? din[31:16]:
                                                     0;
    assign dout = (ext_dm == 3'b000) ? din:
                  (ext_dm == 3'b001) ? {{24{byte[7]}}, byte}:
                  (ext_dm == 3'b010) ? {{24{1'b0}}, byte}:
                  (ext_dm == 3'b011) ? {{16{half_byte[15]}}, half_byte}:
                  (ext_dm == 3'b100) ? {{16{1'b0}}, half_byte}:
                                                         32'h0;
    
endmodule