data/full_repos/permissive/452215364/rtl/chip_select.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:80: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'prog_rom_cs'\n                                                                             : ... In instance chip_select\n            prog_rom_cs       = m68k_cs( 'h000000, 19 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:81: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ram_cs'\n                                                                             : ... In instance chip_select\n            ram_cs            = m68k_cs( 'h080000, 15 );\n            ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:82: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'shared_ram_cs'\n                                                                             : ... In instance chip_select\n            shared_ram_cs     = m68k_cs( 'h440000, 12 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:83: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vblank_cs'\n                                                                             : ... In instance chip_select\n            vblank_cs         = m68k_cs( 'h400000,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:84: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_en_cs'\n                                                                             : ... In instance chip_select\n            int_en_cs         = m68k_cs( 'h400002,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:85: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_palette_cs'\n                                                                             : ... In instance chip_select\n            tile_palette_cs   = m68k_cs( 'h404000, 11 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:86: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_palette_cs'\n                                                                             : ... In instance chip_select\n            sprite_palette_cs = m68k_cs( 'h406000, 11 );\n            ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:87: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_ofs_x_cs'\n                                                                             : ... In instance chip_select\n            scroll_ofs_x_cs   = m68k_cs( 'h0c0000,  1 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:88: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_ofs_y_cs'\n                                                                             : ... In instance chip_select\n            scroll_ofs_y_cs   = m68k_cs( 'h0c0002,  1 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:89: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_ofs_cs'\n                                                                             : ... In instance chip_select\n            tile_ofs_cs       = m68k_cs( 'h480002,  1 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:90: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_attr_cs'\n                                                                             : ... In instance chip_select\n            tile_attr_cs      = m68k_cs( 'h480004,  1 );\n            ^~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:91: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_num_cs'\n                                                                             : ... In instance chip_select\n            tile_num_cs       = m68k_cs( 'h480006,  1 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:92: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_cs'\n                                                                             : ... In instance chip_select\n            scroll_cs         = m68k_cs( 'h480010,  4 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:93: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'frame_done_cs'\n                                                                             : ... In instance chip_select\n            frame_done_cs     = m68k_cs( 'h4c0000,  1 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:94: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_ofs_cs'\n                                                                             : ... In instance chip_select\n            sprite_ofs_cs     = m68k_cs( 'h4c0002,  1 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:95: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_cs'\n                                                                             : ... In instance chip_select\n            sprite_cs         = m68k_cs( 'h4c0004,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:96: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_size_cs'\n                                                                             : ... In instance chip_select\n            sprite_size_cs    = m68k_cs( 'h4c0006,  1 );\n            ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:98: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_p1_cs'\n                                                                             : ... In instance chip_select\n            z80_p1_cs         = z80_cs( 8'h00 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:99: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_p2_cs'\n                                                                             : ... In instance chip_select\n            z80_p2_cs         = z80_cs( 8'h08 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:100: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_dswa_cs'\n                                                                              : ... In instance chip_select\n            z80_dswa_cs       = z80_cs( 8'h20 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:101: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_dswb_cs'\n                                                                              : ... In instance chip_select\n            z80_dswb_cs       = z80_cs( 8'h28 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:102: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_system_cs'\n                                                                              : ... In instance chip_select\n            z80_system_cs     = z80_cs( 8'h80 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:103: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_tjump_cs'\n                                                                              : ... In instance chip_select\n            z80_tjump_cs      = z80_cs( 8'h88 );\n            ^~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:104: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_sound0_cs'\n                                                                              : ... In instance chip_select\n            z80_sound0_cs     = z80_cs( 8'ha8 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:105: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_sound1_cs'\n                                                                              : ... In instance chip_select\n            z80_sound1_cs     = z80_cs( 8'ha9 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:109: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'prog_rom_cs'\n                                                                              : ... In instance chip_select\n            prog_rom_cs       = m68k_cs( 'h000000, 18 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:110: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ram_cs'\n                                                                              : ... In instance chip_select\n            ram_cs            = m68k_cs( 'h240000, 14 );\n            ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:111: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'shared_ram_cs'\n                                                                              : ... In instance chip_select\n            shared_ram_cs     = m68k_cs( 'h140000, 12 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:112: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vblank_cs'\n                                                                              : ... In instance chip_select\n            vblank_cs         = m68k_cs( 'h300000,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:113: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_en_cs'\n                                                                              : ... In instance chip_select\n            int_en_cs         = m68k_cs( 'h300002,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:114: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_ofs_x_cs'\n                                                                              : ... In instance chip_select\n            scroll_ofs_x_cs   = m68k_cs( 'h340000,  1 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:115: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_ofs_y_cs'\n                                                                              : ... In instance chip_select\n            scroll_ofs_y_cs   = m68k_cs( 'h340002,  1 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:116: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_palette_cs'\n                                                                              : ... In instance chip_select\n            tile_palette_cs   = m68k_cs( 'h304000, 11 );\n            ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:117: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_palette_cs'\n                                                                              : ... In instance chip_select\n            sprite_palette_cs = m68k_cs( 'h306000, 11 );\n            ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:118: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_ofs_cs'\n                                                                              : ... In instance chip_select\n            tile_ofs_cs       = m68k_cs( 'h200002,  1 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:119: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_attr_cs'\n                                                                              : ... In instance chip_select\n            tile_attr_cs      = m68k_cs( 'h200004,  1 );\n            ^~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:120: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tile_num_cs'\n                                                                              : ... In instance chip_select\n            tile_num_cs       = m68k_cs( 'h200006,  1 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:121: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'scroll_cs'\n                                                                              : ... In instance chip_select\n            scroll_cs         = m68k_cs( 'h200010,  4 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:122: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'frame_done_cs'\n                                                                              : ... In instance chip_select\n            frame_done_cs     = m68k_cs( 'h100000,  1 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:123: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_ofs_cs'\n                                                                              : ... In instance chip_select\n            sprite_ofs_cs     = m68k_cs( 'h100002,  1 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:124: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_cs'\n                                                                              : ... In instance chip_select\n            sprite_cs         = m68k_cs( 'h100004,  1 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:125: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sprite_size_cs'\n                                                                              : ... In instance chip_select\n            sprite_size_cs    = m68k_cs( 'h100006,  1 );\n            ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:127: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_p1_cs'\n                                                                              : ... In instance chip_select\n            z80_p1_cs         = z80_cs( 8'h14 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:128: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_p2_cs'\n                                                                              : ... In instance chip_select\n            z80_p2_cs         = z80_cs( 8'h18 );\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:129: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_dswa_cs'\n                                                                              : ... In instance chip_select\n            z80_dswa_cs       = z80_cs( 8'h08 );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:130: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_dswb_cs'\n                                                                              : ... In instance chip_select\n            z80_dswb_cs       = z80_cs( 8'h0c );\n            ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:131: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_system_cs'\n                                                                              : ... In instance chip_select\n            z80_system_cs     = z80_cs( 8'h10 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:132: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_tjump_cs'\n                                                                              : ... In instance chip_select\n            z80_tjump_cs      = z80_cs( 8'h1c );\n            ^~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:133: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_sound0_cs'\n                                                                              : ... In instance chip_select\n            z80_sound0_cs     = z80_cs( 8'h00 );\n            ^~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/452215364/rtl/chip_select.v:134: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z80_sound1_cs'\n                                                                              : ... In instance chip_select\n            z80_sound1_cs     = z80_cs( 8'h01 );\n            ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n"
function z80_cs;
        input [7:0] address_lo;
begin
	z80_cs = ( IORQ_n == 0 && z80_addr[7:0] == address_lo );
end
endfunction
function z80_cs;

        input [7:0] address_lo;
begin
	z80_cs = ( IORQ_n == 0 && z80_addr[7:0] == address_lo );
end
endfunction