data/full_repos/permissive/488964817/seven_segment_display.v
data/verilator_xmls/b81d6262-5533-4208-bf4c-0425d4fd77ce.xml
module seven_segment_display(value, outSeg) ;
	input [3:0] value ;
	output [6:0] outSeg ;
	reg [6:0] outSeg ;
	always @(value)
	begin
		case(value)
			4'b0000: outSeg = 7'b1000000 ;
			4'b0001: outSeg = 7'b1111001 ;
			4'b0010: outSeg = 7'b0100100 ;
			4'b0011: outSeg = 7'b0110000 ;
			4'b0100: outSeg = 7'b0011001 ;
			4'b0101: outSeg = 7'b0010010 ;
			4'b0110: outSeg = 7'b0000010 ;
			4'b0111: outSeg = 7'b1111000 ;
			4'b1000: outSeg = 7'b0000000 ;
			4'b1001: outSeg = 7'b0011000 ;
			4'b1010: outSeg = 7'b0001000 ;
			4'b1011: outSeg = 7'b0000011 ;
			4'b1100: outSeg = 7'b1000110 ;
			4'b1101: outSeg = 7'b0100001 ;
			4'b1110: outSeg = 7'b0000110 ;
			4'b1111: outSeg = 7'b0001110 ;
		endcase
	end
endmodule
module seven_segment_display(value, outSeg) ;

	input [3:0] value ;
	output [6:0] outSeg ;
	reg [6:0] outSeg ;
	always @(value)
	begin
		case(value)
			4'b0000: outSeg = 7'b1000000 ;
			4'b0001: outSeg = 7'b1111001 ;
			4'b0010: outSeg = 7'b0100100 ;
			4'b0011: outSeg = 7'b0110000 ;
			4'b0100: outSeg = 7'b0011001 ;
			4'b0101: outSeg = 7'b0010010 ;
			4'b0110: outSeg = 7'b0000010 ;
			4'b0111: outSeg = 7'b1111000 ;
			4'b1000: outSeg = 7'b0000000 ;
			4'b1001: outSeg = 7'b0011000 ;
			4'b1010: outSeg = 7'b0001000 ;
			4'b1011: outSeg = 7'b0000011 ;
			4'b1100: outSeg = 7'b1000110 ;
			4'b1101: outSeg = 7'b0100001 ;
			4'b1110: outSeg = 7'b0000110 ;
			4'b1111: outSeg = 7'b0001110 ;
		endcase
	end
endmodule