data/full_repos/permissive/42434302/ivltests/wait3.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/wait3.v:14: Unsupported: wait statements\n   wait(r);\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #1 a=1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/wait3.v:16: Unsupported: wait statements\n   wait(!r);\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #1 a=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:31: Unsupported: Ignoring delay on this delayed statement.\n   10: #1 a=1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:33: Unsupported: Ignoring delay on this delayed statement.\n   01: #1 a=0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:45: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk= !clk;\n       ^\n%Error: data/full_repos/permissive/42434302/ivltests/wait3.v:48: Unsupported or unknown PLI call: $monitor\n   $monitor($time," ",r1,a1);\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #100 r1=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #100 r1=1;\n   ^\n%Error: data/full_repos/permissive/42434302/ivltests/wait3.v:52: Unsupported: wait statements\n   wait(a1);\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #100 r1=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/wait3.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #1000 $display("timeout"); $finish;\n   ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
reg r1;
wire a1;
reg clk;

skip skip1(r1,a1);

always #50 clk= !clk;

initial begin
   $monitor($time," ",r1,a1);
   $display("starting");
   #100 r1=0;
   #100 r1=1;
   wait(a1);
   #100 r1=0;
   #1000 $display("timeout"); $finish;
end
endmodule
module test;

reg r1;
wire a1;
reg clk;

skip skip1(r1,a1);

always #50 clk= !clk;

initial begin
   $monitor($time," ",r1,a1);
   $display("starting");
   #100 r1=0;
   #100 r1=1;
   wait(a1);
   #100 r1=0;
   #1000 $display("timeout"); $finish;
end
endmodule