data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    always #100 clk = ~ clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #period; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #15000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #period; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n        #5000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n        #period; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new/multi_flotante_tb.v:33: Cannot find file containing module: \'multi_flotante\'\n    multi_flotante UUT (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new,data/full_repos/permissive/477877520/multi_flotante\n             data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new,data/full_repos/permissive/477877520/multi_flotante.v\n             data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sim_1/new,data/full_repos/permissive/477877520/multi_flotante.sv\n             multi_flotante\n             multi_flotante.v\n             multi_flotante.sv\n             obj_dir/multi_flotante\n             obj_dir/multi_flotante.v\n             obj_dir/multi_flotante.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multi_flotante_tb();

    reg clk,reset;
    reg [31:0]a,b;
    wire [31:0]c;
   
    always #100 clk = ~ clk;

    localparam period = 200;  

    multi_flotante UUT (
        .clk(clk), 
        .reset(reset), 
        .a(a),
        .b(b),
        .c(c));
        
    initial begin
        clk <= 1'b0;


        

        reset <= 1'b0;
        a <= 32'b11000001100011000000000000000000;
        b <= 32'b00111111100101000000000000000000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #15000;


        $display("inicia assert 1...");
        if(c === 32'b11000001101000011110000000000000) 
            $display("test 1 correcto!!!");
        else 
            $display("error en test 1.");
            
            



        reset <= 1'b0;
        a <= 32'b10000000000000000000000000000000;
        b <= 32'b00000000000000000000000000000000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #5000;


        $display("inicia assert 2...");
        if(c === 32'b00000000000000000000000000000000) 
            $display("test 2 correcto!!!");
        else 
            $display("error en test 2.");
        



        reset <= 1'b0;
        a <= 32'H3F500000;
        b <= 32'H3DC00000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #10000;


        $display("inicia assert 3...");
        if(c === 32'H3D9C0000) 
            $display("test 3 correcto!!!");
        else 
            $display("error en test 3.");

  
        $finish;
       
    end
endmodule
module multi_flotante_tb();


    reg clk,reset;
    reg [31:0]a,b;
    wire [31:0]c;
   
    always #100 clk = ~ clk;

    localparam period = 200;  

    multi_flotante UUT (
        .clk(clk), 
        .reset(reset), 
        .a(a),
        .b(b),
        .c(c));
        
    initial begin
        clk <= 1'b0;


        

        reset <= 1'b0;
        a <= 32'b11000001100011000000000000000000;
        b <= 32'b00111111100101000000000000000000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #15000;


        $display("inicia assert 1...");
        if(c === 32'b11000001101000011110000000000000) 
            $display("test 1 correcto!!!");
        else 
            $display("error en test 1.");
            
            



        reset <= 1'b0;
        a <= 32'b10000000000000000000000000000000;
        b <= 32'b00000000000000000000000000000000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #5000;


        $display("inicia assert 2...");
        if(c === 32'b00000000000000000000000000000000) 
            $display("test 2 correcto!!!");
        else 
            $display("error en test 2.");
        



        reset <= 1'b0;
        a <= 32'H3F500000;
        b <= 32'H3DC00000;
        #period; 


        reset <= 1'b1;
        #period;


        reset <= 1'b0;
        #10000;


        $display("inicia assert 3...");
        if(c === 32'H3D9C0000) 
            $display("test 3 correcto!!!");
        else 
            $display("error en test 3.");

  
        $finish;
       
    end
endmodule