data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder/full_adder_1b.v
data/verilator_xmls/6637fa0a-5d8c-4392-8035-868e1a383109.xml
module full_adder_1b(
	input a,
	input b,
	input ci,
	output s,
	output co
	);

	wire sum;

	assign sum = a ^ b;
	assign s   = sum ^ ci;
	assign co  = (ci & sum) | (a & b);

endmodule
module full_adder_1b(
	input a,
	input b,
	input ci,
	output s,
	output co
	);


	wire sum;

	assign sum = a ^ b;
	assign s   = sum ^ ci;
	assign co  = (ci & sum) | (a & b);

endmodule