data/full_repos/permissive/486367830/debug/core_debug/deb_src/vld_rdy_checker.v
1: b"%Error: data/full_repos/permissive/486367830/debug/core_debug/deb_src/vld_rdy_checker.v:37: syntax error, unexpected '@'\n@(negedge rst_n);\n^\n%Error: Exiting due to 1 error(s)\n"
module vld_rdy_checker #(
parameter  DATA_WIDTH       = 24
)     
(     
input                     clk     ,
input                     rst_n   ,
                          
input                     ready   ,
input                     valid   ,
input [DATA_WIDTH - 1: 0] data
);

reg                             ready_del                 ;
reg                             valid_del                 ;
reg [DATA_WIDTH - 1: 0]         data_del                  ;

wire                            initialize                ;
reg                             before_hw_rst             ;

assign initialize = before_hw_rst ? 1'b1 : (~rst_n) ;


initial begin
before_hw_rst = 1'b1;
@(negedge rst_n);
@(posedge rst_n);
@(posedge clk);
before_hw_rst = 1'b0;
end


always @(posedge clk)
if (initialize) begin
  ready_del <=  1'b0                 ;
  valid_del <=  1'b0                 ;
  data_del  <=  {DATA_WIDTH{1'b0}}   ;
end
else begin
  ready_del <=  ready    ;
  valid_del <=  valid    ;
  data_del  <=  data     ;
end

always @(posedge clk or negedge rst_n)
if (~before_hw_rst) begin

  if ((valid !== 1'b0) & (valid !== 1'b1)) begin
    $display("%M %0t VLD-RDY ERROR: VLD = x.", $time);
    $stop;
  end

  if ((ready !== 1'b0) & (ready !== 1'b1)) begin
    $display("%M %0t VLD-RDY ERROR: READY = x.", $time);
    $stop;
  end
  


  if (valid_del & ~valid & ~ready_del ) begin
    $display("%M %0t VLD-RDY ERROR: VALID deactivated wrong.", $time);
    $stop;
  end
  



  if (valid_del & valid & ~ready_del & (data !== data_del)) begin
    $display("%M %0t VLD-RDY ERROR: DATA changed during VALID without RDY.", $time);
    $stop;
  end  
end

endmodule
module vld_rdy_checker #(
parameter  DATA_WIDTH       = 24
)     
(     
input                     clk     ,
input                     rst_n   ,
                          
input                     ready   ,
input                     valid   ,
input [DATA_WIDTH - 1: 0] data
);


reg                             ready_del                 ;
reg                             valid_del                 ;
reg [DATA_WIDTH - 1: 0]         data_del                  ;

wire                            initialize                ;
reg                             before_hw_rst             ;

assign initialize = before_hw_rst ? 1'b1 : (~rst_n) ;


initial begin
before_hw_rst = 1'b1;
@(negedge rst_n);
@(posedge rst_n);
@(posedge clk);
before_hw_rst = 1'b0;
end


always @(posedge clk)
if (initialize) begin
  ready_del <=  1'b0                 ;
  valid_del <=  1'b0                 ;
  data_del  <=  {DATA_WIDTH{1'b0}}   ;
end
else begin
  ready_del <=  ready    ;
  valid_del <=  valid    ;
  data_del  <=  data     ;
end

always @(posedge clk or negedge rst_n)
if (~before_hw_rst) begin

  if ((valid !== 1'b0) & (valid !== 1'b1)) begin
    $display("%M %0t VLD-RDY ERROR: VLD = x.", $time);
    $stop;
  end

  if ((ready !== 1'b0) & (ready !== 1'b1)) begin
    $display("%M %0t VLD-RDY ERROR: READY = x.", $time);
    $stop;
  end
  


  if (valid_del & ~valid & ~ready_del ) begin
    $display("%M %0t VLD-RDY ERROR: VALID deactivated wrong.", $time);
    $stop;
  end
  



  if (valid_del & valid & ~ready_del & (data !== data_del)) begin
    $display("%M %0t VLD-RDY ERROR: DATA changed during VALID without RDY.", $time);
    $stop;
  end  
end

endmodule