data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MUX_2_1.v
data/verilator_xmls/b0b59c97-8593-4c64-858c-b3c0ad0b8e7b.xml
module MUX_2_1 #(parameter INPUT_DATA_WIDTH =8)(


input [INPUT_DATA_WIDTH-1:0] MUX_Input_0,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_1,
input MUX_sel,



output[INPUT_DATA_WIDTH-1:0]  MUX_OUTPUT


);


reg [INPUT_DATA_WIDTH-1:0] Data;

always@(*)
begin
	case(MUX_sel)
		1'b0: Data=MUX_Input_0;
		1'b1: Data=MUX_Input_1;
	endcase
end


assign MUX_OUTPUT=Data;


endmodule
module MUX_2_1 #(parameter INPUT_DATA_WIDTH =8)(


input [INPUT_DATA_WIDTH-1:0] MUX_Input_0,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_1,
input MUX_sel,



output[INPUT_DATA_WIDTH-1:0]  MUX_OUTPUT


);



reg [INPUT_DATA_WIDTH-1:0] Data;

always@(*)
begin
	case(MUX_sel)
		1'b0: Data=MUX_Input_0;
		1'b1: Data=MUX_Input_1;
	endcase
end


assign MUX_OUTPUT=Data;


endmodule