data/full_repos/permissive/513199821/spi.v
1: b'%Error: data/full_repos/permissive/513199821/spi.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module spi_master #(
    parameter SPI_MODE		= 0,
    parameter CLKS_PER_HALF_BIT = 8
  ) (

    input	 i_Rst_L,
    input	 i_Clk,


    input [7:0]  i_TX_Byte,
    input	 i_TX_DV,
    output reg	 o_TX_Ready,


    output reg	     o_RX_DV,
    output reg [7:0] o_RX_Byte,


    output reg o_SPI_Clk,
    input      i_SPI_MISO,
    output reg o_SPI_MOSI
);


wire w_CPOL;
wire w_CPHA;

reg [$clog2(CLKS_PER_HALF_BIT*2) - 1:0] r_SPI_Clk_Count;
reg r_SPI_Clk;
reg [4:0] r_SPI_Clk_Edges;
reg r_Leading_Edge;
reg r_Trailing_Edge;
reg	  r_TX_DV;
reg [7:0] r_TX_Byte;

reg [2:0] r_RX_Bit_Count;
reg [2:0] r_TX_Bit_Count;




assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);






assign w_CPHA  = (SPI_MODE == 1) | (SPI_MODE == 3);


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_SPI_Clk <= w_CPOL;
  end else begin
    o_SPI_Clk <= r_SPI_Clk;
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_TX_Ready	    <= 1'b0;
    r_SPI_Clk_Edges <= 0;
    r_Leading_Edge  <= 1'b0;
    r_Trailing_Edge <= 1'b0;
    r_SPI_Clk	    <= w_CPOL;
    r_SPI_Clk_Count <= 0;
  end else begin

    r_Leading_Edge  <= 1'b0;
    r_Trailing_Edge <= 1'b0;

    if (i_TX_DV) begin
      o_TX_Ready      <= 1'b0;
      r_SPI_Clk_Edges <= 16;
    end else if (r_SPI_Clk_Edges > 0) begin
      o_TX_Ready <= 1'b0;
      if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT * 2 - 1) begin
	r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1'b1;
	r_Trailing_Edge <= 1'b1;
	r_SPI_Clk_Count <= 0;
	r_SPI_Clk	<= ~r_SPI_Clk;
      end else if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT - 1) begin
	r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1'b1;
	r_Leading_Edge	<= 1'b1;
	r_SPI_Clk_Count <= r_SPI_Clk_Count + 1'b1;
	r_SPI_Clk	<= ~r_SPI_Clk;
      end else begin
	r_SPI_Clk_Count <= r_SPI_Clk_Count + 1'b1;
      end
    end else begin
      o_TX_Ready <= 1'b1;
    end
  end
end



always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    r_TX_Byte <= 8'h00;
    r_TX_DV   <= 1'b0;
  end else begin
    r_TX_DV <= i_TX_DV;
    if (i_TX_DV) begin
      r_TX_Byte <= i_TX_Byte;
    end
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_SPI_MOSI	   <= 1'b0;
    r_TX_Bit_Count <= 3'b111;
  end else begin

    if (o_TX_Ready) begin
      r_TX_Bit_Count <= 3'b111;
`ifdef SPI_TEST_OFF
      $display ("spimas begin %t MOSI", $time);
`endif
    end else if (r_TX_DV & ~w_CPHA) begin

      o_SPI_MOSI     <= r_TX_Byte[3'b111];
      r_TX_Bit_Count <= 3'b110;
`ifdef SPI_TEST
      $display ("spimas mosi  %t byte %x", $time, r_TX_Byte);
`endif
    end else if ((r_Leading_Edge & w_CPHA) | (r_Trailing_Edge & ~w_CPHA)) begin
      r_TX_Bit_Count <= r_TX_Bit_Count - 1;
      o_SPI_MOSI     <= r_TX_Byte[r_TX_Bit_Count];
    end
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_RX_Byte	   <= 8'h00;
    o_RX_DV	   <= 1'b0;
    r_RX_Bit_Count <= 3'b111;
  end else begin

    o_RX_DV <= 1'b0;

    if (o_TX_Ready) begin
      r_RX_Bit_Count <= 3'b111;
    end else if ((r_Leading_Edge & ~w_CPHA) | (r_Trailing_Edge & w_CPHA)) begin
      o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO;
      r_RX_Bit_Count		<= r_RX_Bit_Count - 1;
`ifdef SPI_TEST

`endif
      if (r_RX_Bit_Count == 3'b000) begin
	o_RX_DV   <= 1'b1;
`ifdef SPI_TEST
	$strobe ("spimas miso  %t byte %x", $time, o_RX_Byte);
`endif
      end
    end
  end
end

endmodule
module spi_master #(
    parameter SPI_MODE		= 0,
    parameter CLKS_PER_HALF_BIT = 8
  ) (

    input	 i_Rst_L,
    input	 i_Clk,


    input [7:0]  i_TX_Byte,
    input	 i_TX_DV,
    output reg	 o_TX_Ready,


    output reg	     o_RX_DV,
    output reg [7:0] o_RX_Byte,


    output reg o_SPI_Clk,
    input      i_SPI_MISO,
    output reg o_SPI_MOSI
);



wire w_CPOL;
wire w_CPHA;

reg [$clog2(CLKS_PER_HALF_BIT*2) - 1:0] r_SPI_Clk_Count;
reg r_SPI_Clk;
reg [4:0] r_SPI_Clk_Edges;
reg r_Leading_Edge;
reg r_Trailing_Edge;
reg	  r_TX_DV;
reg [7:0] r_TX_Byte;

reg [2:0] r_RX_Bit_Count;
reg [2:0] r_TX_Bit_Count;




assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);






assign w_CPHA  = (SPI_MODE == 1) | (SPI_MODE == 3);


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_SPI_Clk <= w_CPOL;
  end else begin
    o_SPI_Clk <= r_SPI_Clk;
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_TX_Ready	    <= 1'b0;
    r_SPI_Clk_Edges <= 0;
    r_Leading_Edge  <= 1'b0;
    r_Trailing_Edge <= 1'b0;
    r_SPI_Clk	    <= w_CPOL;
    r_SPI_Clk_Count <= 0;
  end else begin

    r_Leading_Edge  <= 1'b0;
    r_Trailing_Edge <= 1'b0;

    if (i_TX_DV) begin
      o_TX_Ready      <= 1'b0;
      r_SPI_Clk_Edges <= 16;
    end else if (r_SPI_Clk_Edges > 0) begin
      o_TX_Ready <= 1'b0;
      if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT * 2 - 1) begin
	r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1'b1;
	r_Trailing_Edge <= 1'b1;
	r_SPI_Clk_Count <= 0;
	r_SPI_Clk	<= ~r_SPI_Clk;
      end else if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT - 1) begin
	r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1'b1;
	r_Leading_Edge	<= 1'b1;
	r_SPI_Clk_Count <= r_SPI_Clk_Count + 1'b1;
	r_SPI_Clk	<= ~r_SPI_Clk;
      end else begin
	r_SPI_Clk_Count <= r_SPI_Clk_Count + 1'b1;
      end
    end else begin
      o_TX_Ready <= 1'b1;
    end
  end
end



always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    r_TX_Byte <= 8'h00;
    r_TX_DV   <= 1'b0;
  end else begin
    r_TX_DV <= i_TX_DV;
    if (i_TX_DV) begin
      r_TX_Byte <= i_TX_Byte;
    end
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_SPI_MOSI	   <= 1'b0;
    r_TX_Bit_Count <= 3'b111;
  end else begin

    if (o_TX_Ready) begin
      r_TX_Bit_Count <= 3'b111;
`ifdef SPI_TEST_OFF
      $display ("spimas begin %t MOSI", $time);
`endif
    end else if (r_TX_DV & ~w_CPHA) begin

      o_SPI_MOSI     <= r_TX_Byte[3'b111];
      r_TX_Bit_Count <= 3'b110;
`ifdef SPI_TEST
      $display ("spimas mosi  %t byte %x", $time, r_TX_Byte);
`endif
    end else if ((r_Leading_Edge & w_CPHA) | (r_Trailing_Edge & ~w_CPHA)) begin
      r_TX_Bit_Count <= r_TX_Bit_Count - 1;
      o_SPI_MOSI     <= r_TX_Byte[r_TX_Bit_Count];
    end
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    o_RX_Byte	   <= 8'h00;
    o_RX_DV	   <= 1'b0;
    r_RX_Bit_Count <= 3'b111;
  end else begin

    o_RX_DV <= 1'b0;

    if (o_TX_Ready) begin
      r_RX_Bit_Count <= 3'b111;
    end else if ((r_Leading_Edge & ~w_CPHA) | (r_Trailing_Edge & w_CPHA)) begin
      o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO;
      r_RX_Bit_Count		<= r_RX_Bit_Count - 1;
`ifdef SPI_TEST

`endif
      if (r_RX_Bit_Count == 3'b000) begin
	o_RX_DV   <= 1'b1;
`ifdef SPI_TEST
	$strobe ("spimas miso  %t byte %x", $time, o_RX_Byte);
`endif
      end
    end
  end
end

endmodule