data/full_repos/permissive/427221126/workspace/rom_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        if(n == 0) begin #5; ADDR <= 6\'d0;end\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 7) begin #5; ADDR <= 6\'d55;end\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 12) begin #5; ADDR <= 6\'d7;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 19) begin #5; ADDR <= 6\'d52;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 24) begin #5; ADDR <= 6\'d0;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 31) begin #5; ADDR <= 6\'d49;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 36) begin #5; ADDR <= 6\'d21;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 45) begin #5; ADDR <= 6\'d28;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 54) begin #5; ADDR <= 6\'d35;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        else if(n == 63) begin #5; ADDR <= 6\'d42;end\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/427221126/workspace/rom_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        else begin #5; ADDR = ADDR + 6\'d1;end\n                   ^\n%Error: data/full_repos/permissive/427221126/workspace/rom_tb.v:67: Unsupported or unknown PLI call: $fsdbDumpfile\n        $fsdbDumpfile("rom.fsdb");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/workspace/rom_tb.v:68: Unsupported or unknown PLI call: $fsdbDumpvars\n        $fsdbDumpvars(0,rom_test);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/workspace/rom_tb.v:69: Unsupported or unknown PLI call: $fsdbDumpon\n        $fsdbDumpon;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/workspace/rom_tb.v:70: Unsupported or unknown PLI call: $fsdbDumpMDA\n     $fsdbDumpMDA();\n     ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_tb();
reg clk,rst,read;
reg [5:0] ADDR;
wire[15:0]dout;
reg[6:0]n;
reg en;
rom rom_test
    (
       .clk(clk),
       .rst(rst),
       .read(read),
       .addr(ADDR),
       .dout(dout)
    );


    initial begin 
        clk = 0;
        forever
        #10
        clk = ~clk;
    end
        

    initial begin
        rst = 0;
        #3;
        rst = 1;
        #30
        rst = 0;
        #1000;
        $finish;
    end   

        initial begin
        #50
        en = 1;
        #20
        en = 0;
    end   
    initial begin

        read = 1;
    end    

    always @(posedge clk) begin
        if(en) n <= 0;
        else n <= n + 1;
    end

    always @(posedge clk) begin
        if(n == 0) begin #5; ADDR <= 6'd0;end
        else if(n == 7) begin #5; ADDR <= 6'd55;end
        else if(n == 12) begin #5; ADDR <= 6'd7;end
        else if(n == 19) begin #5; ADDR <= 6'd52;end
        else if(n == 24) begin #5; ADDR <= 6'd0;end
        else if(n == 31) begin #5; ADDR <= 6'd49;end
        else if(n == 36) begin #5; ADDR <= 6'd21;end
        else if(n == 45) begin #5; ADDR <= 6'd28;end
        else if(n == 54) begin #5; ADDR <= 6'd35;end
        else if(n == 63) begin #5; ADDR <= 6'd42;end
        else begin #5; ADDR = ADDR + 6'd1;end
    end

    initial begin
        $fsdbDumpfile("rom.fsdb");
        $fsdbDumpvars(0,rom_test);
        $fsdbDumpon;
	    $fsdbDumpMDA();
        end  
    
    endmodule
module rom_tb();

reg clk,rst,read;
reg [5:0] ADDR;
wire[15:0]dout;
reg[6:0]n;
reg en;
rom rom_test
    (
       .clk(clk),
       .rst(rst),
       .read(read),
       .addr(ADDR),
       .dout(dout)
    );


    initial begin 
        clk = 0;
        forever
        #10
        clk = ~clk;
    end
        

    initial begin
        rst = 0;
        #3;
        rst = 1;
        #30
        rst = 0;
        #1000;
        $finish;
    end   

        initial begin
        #50
        en = 1;
        #20
        en = 0;
    end   
    initial begin

        read = 1;
    end    

    always @(posedge clk) begin
        if(en) n <= 0;
        else n <= n + 1;
    end

    always @(posedge clk) begin
        if(n == 0) begin #5; ADDR <= 6'd0;end
        else if(n == 7) begin #5; ADDR <= 6'd55;end
        else if(n == 12) begin #5; ADDR <= 6'd7;end
        else if(n == 19) begin #5; ADDR <= 6'd52;end
        else if(n == 24) begin #5; ADDR <= 6'd0;end
        else if(n == 31) begin #5; ADDR <= 6'd49;end
        else if(n == 36) begin #5; ADDR <= 6'd21;end
        else if(n == 45) begin #5; ADDR <= 6'd28;end
        else if(n == 54) begin #5; ADDR <= 6'd35;end
        else if(n == 63) begin #5; ADDR <= 6'd42;end
        else begin #5; ADDR = ADDR + 6'd1;end
    end

    initial begin
        $fsdbDumpfile("rom.fsdb");
        $fsdbDumpvars(0,rom_test);
        $fsdbDumpon;
	    $fsdbDumpMDA();
        end  
    
    endmodule