data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_ddiv.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_ddiv.v:82: Cannot find file containing module: 'ctu_clsp_clkgn_1div'\nctu_clsp_clkgn_1div pos(\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ctu_clsp_clkgn_1div\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ctu_clsp_clkgn_1div.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ctu_clsp_clkgn_1div.sv\n             ctu_clsp_clkgn_1div\n             ctu_clsp_clkgn_1div.v\n             ctu_clsp_clkgn_1div.sv\n             obj_dir/ctu_clsp_clkgn_1div\n             obj_dir/ctu_clsp_clkgn_1div.v\n             obj_dir/ctu_clsp_clkgn_1div.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_ddiv.v:97: Cannot find file containing module: 'ctu_clsp_clkgn_1div'\nctu_clsp_clkgn_1div neg(\n^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ctu_clsp_clkgn_ddiv (

dom_div0, align_edge, align_edge_b, dom_div1, so, 

pll_clk_out, pll_clk_out_l, rst_l, rst_b_l, div_dec, stretch_l, 
stretch_b_l, se, si
);



   input                                pll_clk_out;
   input                                pll_clk_out_l;
   input 				rst_l;
   input 				rst_b_l;
   

   input [14:0] 			div_dec	;


   input 				stretch_l;
   input                                stretch_b_l;


   output                               dom_div0;
   output                               align_edge;
   output                               align_edge_b;
   output                               dom_div1;
   
   input                                si;
   input 				se;
   output				so;




ctu_clsp_clkgn_1div pos(

			.dom_div	(dom_div0),
			.align_edge	(align_edge),
			.align_edge_b	(align_edge_b),
			.so		(),

			.pll_clk	(pll_clk_out),
			.pll_clk_l	(pll_clk_out_l),
			.init_l		(rst_l),
			.div_dec	(div_dec[14:0]),
			.stretch_l	(stretch_l),
			.se		(se),
			.si		());

ctu_clsp_clkgn_1div neg(

			.dom_div	(dom_div1),
			.align_edge	(),
			.align_edge_b	(),
			.so		(),

			.pll_clk	(pll_clk_out_l),
			.pll_clk_l	(pll_clk_out),
			.init_l		(rst_b_l),
			.div_dec	(div_dec[14:0]),
			.stretch_l	(stretch_b_l),
			.se		(se),
			.si		());


endmodule
module ctu_clsp_clkgn_ddiv (

dom_div0, align_edge, align_edge_b, dom_div1, so, 

pll_clk_out, pll_clk_out_l, rst_l, rst_b_l, div_dec, stretch_l, 
stretch_b_l, se, si
);




   input                                pll_clk_out;
   input                                pll_clk_out_l;
   input 				rst_l;
   input 				rst_b_l;
   

   input [14:0] 			div_dec	;


   input 				stretch_l;
   input                                stretch_b_l;


   output                               dom_div0;
   output                               align_edge;
   output                               align_edge_b;
   output                               dom_div1;
   
   input                                si;
   input 				se;
   output				so;




ctu_clsp_clkgn_1div pos(

			.dom_div	(dom_div0),
			.align_edge	(align_edge),
			.align_edge_b	(align_edge_b),
			.so		(),

			.pll_clk	(pll_clk_out),
			.pll_clk_l	(pll_clk_out_l),
			.init_l		(rst_l),
			.div_dec	(div_dec[14:0]),
			.stretch_l	(stretch_l),
			.se		(se),
			.si		());

ctu_clsp_clkgn_1div neg(

			.dom_div	(dom_div1),
			.align_edge	(),
			.align_edge_b	(),
			.so		(),

			.pll_clk	(pll_clk_out_l),
			.pll_clk_l	(pll_clk_out),
			.init_l		(rst_b_l),
			.div_dec	(div_dec[14:0]),
			.stretch_l	(stretch_b_l),
			.se		(se),
			.si		());


endmodule