data/full_repos/permissive/42434302/vpi/pr2048463.v
1: b'%Error: data/full_repos/permissive/42434302/vpi/pr2048463.v:20: Unsupported or unknown PLI call: $my_monitor\n    $my_monitor(i1);\n    ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #0 a = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #0 b = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #0 ci = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/vpi/pr2048463.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg   a, b, ci, clk;
  wire  sum, co;

  addbit i1 (a, b, ci, sum, co);

  initial
    $my_monitor(i1);

  initial
    begin
      #0 a = 0;
      #0 b = 0;
      #0 ci = 0;
      #10 a = 1;
      #10 a = 0;
      #10 b = 1;
      #10 a = 1;
      #10 $finish;
    end

endmodule
module test;

  reg   a, b, ci, clk;
  wire  sum, co;

  addbit i1 (a, b, ci, sum, co);

  initial
    $my_monitor(i1);

  initial
    begin
      #0 a = 0;
      #0 b = 0;
      #0 ci = 0;
      #10 a = 1;
      #10 a = 0;
      #10 b = 1;
      #10 a = 1;
      #10 $finish;
    end

endmodule