data/full_repos/permissive/446939020/risc-v/hazard_unit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:13: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardAE = 32\'b10;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:16: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardAE = 32\'b01;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:19: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardAE = 32\'b00;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:15: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'Rs1E\' generates 5 bits.\n                                                                            : ... In instance hazard\n    else if (((Rs1E == RdW) && RegWriteW) && (Rs1E != 32\'b0)) begin\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:12: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'Rs1E\' generates 5 bits.\n                                                                            : ... In instance hazard\n    if (((Rs1E == RdM) && RegWriteM) && (Rs1E != 32\'b0)) begin\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:24: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardBE = 32\'b10;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:27: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardBE = 32\'b01;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:30: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                            : ... In instance hazard\n      ForwardBE = 32\'b00;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/446939020/risc-v/hazard_unit.v:23: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'Rs2E\' generates 5 bits.\n                                                                            : ... In instance hazard\n    if (((Rs2E == RdM) && RegWriteM) && (Rs2E != 32\'b0)) begin\n                                              ^~\n%Error: Exiting due to 9 warning(s)\n'
module hazard(input [4:0]Rs1E,Rs2E,RdM,RdW,
              input RegWriteM,RegWriteW,
              input ResultSrcE0,
              input [4:0]Rs1D,Rs2D,RdE,
              input PCSrcE,reset,
              output reg StallD,StallF,FlushE,FlushD,
              output reg [1:0]ForwardAE,ForwardBE);
  
  reg lwStall=0;
  always@(*) begin	
  
    if (((Rs1E == RdM) && RegWriteM) && (Rs1E != 32'b0)) begin
      ForwardAE = 32'b10;
    end
    else if (((Rs1E == RdW) && RegWriteW) && (Rs1E != 32'b0)) begin
      ForwardAE = 32'b01;
    end
    else begin
      ForwardAE = 32'b00;
    end
    
  
    if (((Rs2E == RdM) && RegWriteM) && (Rs2E != 32'b0)) begin
      ForwardBE = 32'b10;
    end
    else if (((Rs2E == RdW) && RegWriteW) && (Rs2E != 0)) begin
      ForwardBE = 32'b01;
    end
    else begin
      ForwardBE = 32'b00;
    end
  end
  
  always@(*)begin

    lwStall = ResultSrcE0 && ((Rs1D == RdE) || (Rs2D == RdE));
    StallF = lwStall;
    StallD = lwStall;
    FlushD = PCSrcE;
    FlushE = lwStall || PCSrcE;

  end
  
endmodule
module hazard(input [4:0]Rs1E,Rs2E,RdM,RdW,
              input RegWriteM,RegWriteW,
              input ResultSrcE0,
              input [4:0]Rs1D,Rs2D,RdE,
              input PCSrcE,reset,
              output reg StallD,StallF,FlushE,FlushD,
              output reg [1:0]ForwardAE,ForwardBE);

  
  reg lwStall=0;
  always@(*) begin	
  
    if (((Rs1E == RdM) && RegWriteM) && (Rs1E != 32'b0)) begin
      ForwardAE = 32'b10;
    end
    else if (((Rs1E == RdW) && RegWriteW) && (Rs1E != 32'b0)) begin
      ForwardAE = 32'b01;
    end
    else begin
      ForwardAE = 32'b00;
    end
    
  
    if (((Rs2E == RdM) && RegWriteM) && (Rs2E != 32'b0)) begin
      ForwardBE = 32'b10;
    end
    else if (((Rs2E == RdW) && RegWriteW) && (Rs2E != 0)) begin
      ForwardBE = 32'b01;
    end
    else begin
      ForwardBE = 32'b00;
    end
  end
  
  always@(*)begin

    lwStall = ResultSrcE0 && ((Rs1D == RdE) || (Rs2D == RdE));
    StallF = lwStall;
    StallD = lwStall;
    FlushD = PCSrcE;
    FlushE = lwStall || PCSrcE;

  end
  
endmodule