data/full_repos/permissive/528912093/Proiect/OutputReg.v
1: b"%Error: data/full_repos/permissive/528912093/Proiect/OutputReg.v:9: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire w6,w7,w9,w11,w13,w15,;\n                           ^\n%Error: data/full_repos/permissive/528912093/Proiect/OutputReg.v:19: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module OutputReg( IB[0],IB[1],IB[2],IB[3],LoadOut,MainReset,MainClock,Out3,
 Out0,Out2,Out1);
 input IB[0],IB[1],IB[2],IB[3],LoadOut,MainReset,MainClock;
 output Out3,Out0,Out2,Out1;
 wire w6,w7,w9,w11,w13,w15,;
 dreg #(4) dreg_1(Out0,w9,IB[0],w6,w7);
 dreg #(4) dreg_2(Out1,w11,IB[1],w6,w7);
 dreg #(4) dreg_3(Out2,w13,IB[2],w6,w7);
 dreg #(4) dreg_4(Out3,w15,IB[3],w6,w7);
 nand #(4) nand2_5(w7,MainClock,LoadOut);
 not #(3) inv_6(w6,MainReset);
endmodule
module OutputReg( IB[0],IB[1],IB[2],IB[3],LoadOut,MainReset,MainClock,Out3,
 Out0,Out2,Out1);

 input IB[0],IB[1],IB[2],IB[3],LoadOut,MainReset,MainClock;
 output Out3,Out0,Out2,Out1;
 wire w6,w7,w9,w11,w13,w15,;
 dreg #(4) dreg_1(Out0,w9,IB[0],w6,w7);
 dreg #(4) dreg_2(Out1,w11,IB[1],w6,w7);
 dreg #(4) dreg_3(Out2,w13,IB[2],w6,w7);
 dreg #(4) dreg_4(Out3,w15,IB[3],w6,w7);
 nand #(4) nand2_5(w7,MainClock,LoadOut);
 not #(3) inv_6(w6,MainReset);
endmodule