data/full_repos/permissive/424312442/lab_6_digital clock/sources_1/new/clock.v
1: b'%Error: Cannot find file containing module: clock/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             clock/sources_1/new,data/full_repos/permissive/424312442\n             clock/sources_1/new,data/full_repos/permissive/424312442.v\n             clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_6_digital\n%Error: Cannot find file containing module: clock/sources_1/new/clock.v\n%Error: Exiting due to 3 error(s)\n'
module clock_divider(clk_100Mhz, clk_1hz);
input clk_100Mhz;
output clk_1hz;

reg [25:0] counter = 0;
reg clk_1hz = 0;

always @(posedge clk_100Mhz) begin
    counter <= counter + 1;
    if (counter >= 49999999) begin



        counter <= 0;
        clk_1hz <= !clk_1hz;
    end
end
endmodule
module clock_divider(clk_100Mhz, clk_1hz);

input clk_100Mhz;
output clk_1hz;

reg [25:0] counter = 0;
reg clk_1hz = 0;

always @(posedge clk_100Mhz) begin
    counter <= counter + 1;
    if (counter >= 49999999) begin



        counter <= 0;
        clk_1hz <= !clk_1hz;
    end
end
endmodule