data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc/pc.v
1: b"%Error: data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc/pc.v:10: Cannot find file containing module: 'register'\n register #(.D_WIDTH(D_WIDTH)) REG (.clk(clk), .in(pc_in), .load(pc_load), .out(pc_out));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc,data/full_repos/permissive/470816788/register\n             data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc,data/full_repos/permissive/470816788/register.v\n             data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc,data/full_repos/permissive/470816788/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Error: Exiting due to 1 error(s)\n"
module pc(input clk, input reset, input [D_WIDTH-1:0] in, input load, input inc, output [D_WIDTH-1:0] out);
	parameter D_WIDTH = 16;
	
	wire [D_WIDTH-1:0] pc_in;
	wire [D_WIDTH-1:0] pc_out;
	wire pc_load;
	register #(.D_WIDTH(D_WIDTH)) REG (.clk(clk), .in(pc_in), .load(pc_load), .out(pc_out));
	
	assign out = pc_out;
	assign pc_load = 1'b1;
	assign pc_in = (reset ? {D_WIDTH{1'b0}} : 
				((load) ? in :	
				((inc) ? pc_out + 1 :	
				pc_out)));					


endmodule
module pc(input clk, input reset, input [D_WIDTH-1:0] in, input load, input inc, output [D_WIDTH-1:0] out);

	parameter D_WIDTH = 16;
	
	wire [D_WIDTH-1:0] pc_in;
	wire [D_WIDTH-1:0] pc_out;
	wire pc_load;
	register #(.D_WIDTH(D_WIDTH)) REG (.clk(clk), .in(pc_in), .load(pc_load), .out(pc_out));
	
	assign out = pc_out;
	assign pc_load = 1'b1;
	assign pc_in = (reset ? {D_WIDTH{1'b0}} : 
				((load) ? in :	
				((inc) ? pc_out + 1 :	
				pc_out)));					


endmodule