data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v
1: b'%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:148: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482719158/verilog/rtl,data/full_repos/permissive/482719158/uart_defines.v\n             data/full_repos/permissive/482719158/verilog/rtl,data/full_repos/permissive/482719158/uart_defines.v.v\n             data/full_repos/permissive/482719158/verilog/rtl,data/full_repos/permissive/482719158/uart_defines.v.sv\n             uart_defines.v\n             uart_defines.v.v\n             uart_defines.v.sv\n             obj_dir/uart_defines.v\n             obj_dir/uart_defines.v.v\n             obj_dir/uart_defines.v.sv\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:164: Define or directive not defined: \'`UART_FIFO_COUNTER_W\'\noutput [`UART_FIFO_COUNTER_W-1:0]  tf_count;\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:178: Define or directive not defined: \'`UART_FIFO_WIDTH\'\nwire [`UART_FIFO_WIDTH-1:0]    tf_data_in;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:179: Define or directive not defined: \'`UART_FIFO_WIDTH\'\nwire [`UART_FIFO_WIDTH-1:0]    tf_data_out;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:182: Define or directive not defined: \'`UART_FIFO_COUNTER_W\'\nwire [`UART_FIFO_COUNTER_W-1:0]   tf_count;\n      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:291: Define or directive not defined: \'`UART_LC_PE\'\n     if (~lcr[`UART_LC_PE])\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:291: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n     if (~lcr[`UART_LC_PE])\n                         ^\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:297: Define or directive not defined: \'`UART_LC_EP\'\n      case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:297: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})\n                            ^\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:297: Define or directive not defined: \'`UART_LC_SP\'\n      case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:307: syntax error, unexpected else, expecting endcase\n    else\n    ^~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:327: Define or directive not defined: \'`UART_LC_SB\'\n      casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:327: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})\n                             ^\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:327: Define or directive not defined: \'`UART_LC_BITS\'\n      casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:344: syntax error, unexpected default\n  default :  \n  ^~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:352: Define or directive not defined: \'`UART_LC_BC\'\nassign stx_pad_o = lcr[`UART_LC_BC] ? 1\'b0 : stx_o_tmp;     \n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/rtl/uart_transmitter.v:352: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign stx_pad_o = lcr[`UART_LC_BC] ? 1\'b0 : stx_o_tmp;     \n                                  ^\n%Error: Exiting due to 17 error(s)\n'
module uart_transmitter
#(parameter SIM = 0)
 (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable,	stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);

input 										clk;
input 										wb_rst_i;
input [7:0] 								lcr;
input 										tf_push;
input [7:0] 								wb_dat_i;
input 										enable;
input 										tx_reset;
input 										lsr_mask;
output 										stx_pad_o;
output [2:0] 								tstate;
output [`UART_FIFO_COUNTER_W-1:0] 	tf_count;

reg [2:0] 									tstate;
reg [4:0] 									counter;
reg [2:0] 									bit_counter;
reg [6:0] 									shift_out;
reg 											stx_o_tmp;
reg 											parity_xor;
reg 											tf_pop;
reg 											bit_out;




wire [`UART_FIFO_WIDTH-1:0] 			tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] 			tf_data_out;
wire 											tf_push;
wire 											tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] 		tf_count;

assign 										tf_data_in = wb_dat_i;

uart_tfifo fifo_tx(
	.clk(		clk		), 
	.wb_rst_i(	wb_rst_i	),
	.data_in(	tf_data_in	),
	.data_out(	tf_data_out	),
	.push(		tf_push		),
	.pop(		tf_pop		),
	.overrun(	tf_overrun	),
	.count(		tf_count	),
	.fifo_reset(	tx_reset	),
	.reset_status(lsr_mask)
);



localparam s_idle        = 3'd0;
localparam s_send_start  = 3'd1;
localparam s_send_byte   = 3'd2;
localparam s_send_parity = 3'd3;
localparam s_send_stop   = 3'd4;
localparam s_pop_byte    = 3'd5;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	tstate       <= s_idle;
	stx_o_tmp       <= 1'b1;
	counter   <= 5'b0;
	shift_out   <= 7'b0;
	bit_out     <= 1'b0;
	parity_xor  <= 1'b0;
	tf_pop      <= 1'b0;
	bit_counter <= 3'b0;
  end
  else
  if (enable | SIM)
  begin
	case (tstate)
	s_idle	 :	if (~|tf_count)
			begin
				tstate <= s_idle;
				stx_o_tmp <= 1'b1;
			end
			else
			begin
				tf_pop <= 1'b0;
				stx_o_tmp  <= 1'b1;
				tstate  <= s_pop_byte;
			end
	s_pop_byte :	begin
				tf_pop <= 1'b1;
				case (lcr[1:0])
				2'b00 : begin
					bit_counter <= 3'b100;
					parity_xor  <= ^tf_data_out[4:0];
				     end
				2'b01 : begin
					bit_counter <= 3'b101;
					parity_xor  <= ^tf_data_out[5:0];
				     end
				2'b10 : begin
					bit_counter <= 3'b110;
					parity_xor  <= ^tf_data_out[6:0];
				     end
				2'b11 : begin
					bit_counter <= 3'b111;
					parity_xor  <= ^tf_data_out[7:0];
				     end
				endcase
				{shift_out[6:0], bit_out} <= tf_data_out;
				tstate <= s_send_start;
			end
	s_send_start :	begin
				tf_pop <= 1'b0;
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					counter <= 0;
					tstate <= s_send_byte;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= 1'b0;
				if (SIM) begin
					tstate <= s_idle;
					$write("%c", tf_data_out);
					$fflush(32'h80000001);
				end
			end
	s_send_byte :	begin
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					if (bit_counter > 3'b0)
					begin
						bit_counter <= bit_counter - 3'd1;
						{shift_out[5:0],bit_out  } <= {shift_out[6:1], shift_out[0]};
						tstate <= s_send_byte;
					end
					else
					if (~lcr[`UART_LC_PE])
					begin
						tstate <= s_send_stop;
					end
					else
					begin
						case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
						2'b00:	bit_out <= ~parity_xor;
						2'b01:	bit_out <= 1'b1;
						2'b10:	bit_out <= parity_xor;
						2'b11:	bit_out <= 1'b0;
						endcase
						tstate <= s_send_parity;
					end
					counter <= 0;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= bit_out;
			end
	s_send_parity :	begin
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					counter <= 5'd0;
					tstate <= s_send_stop;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= bit_out;
			end
	s_send_stop :  begin
				if (~|counter)
				  begin
						casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
  						3'b0??:	  counter <= 5'b01101;
  						3'b100:	  counter <= 5'b10101;
  						default:	  counter <= 5'b11101;
						endcase
					end
				else
				if (counter == 5'b00001)
				begin
					counter <= 0;
					tstate <= s_idle;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= 1'b1;
			end

		default :
			tstate <= s_idle;
	endcase
  end
  else
    tf_pop <= 1'b0;
end

assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;
	
endmodule
module uart_transmitter
#(parameter SIM = 0)
 (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable,	stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);


input 										clk;
input 										wb_rst_i;
input [7:0] 								lcr;
input 										tf_push;
input [7:0] 								wb_dat_i;
input 										enable;
input 										tx_reset;
input 										lsr_mask;
output 										stx_pad_o;
output [2:0] 								tstate;
output [`UART_FIFO_COUNTER_W-1:0] 	tf_count;

reg [2:0] 									tstate;
reg [4:0] 									counter;
reg [2:0] 									bit_counter;
reg [6:0] 									shift_out;
reg 											stx_o_tmp;
reg 											parity_xor;
reg 											tf_pop;
reg 											bit_out;




wire [`UART_FIFO_WIDTH-1:0] 			tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] 			tf_data_out;
wire 											tf_push;
wire 											tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] 		tf_count;

assign 										tf_data_in = wb_dat_i;

uart_tfifo fifo_tx(
	.clk(		clk		), 
	.wb_rst_i(	wb_rst_i	),
	.data_in(	tf_data_in	),
	.data_out(	tf_data_out	),
	.push(		tf_push		),
	.pop(		tf_pop		),
	.overrun(	tf_overrun	),
	.count(		tf_count	),
	.fifo_reset(	tx_reset	),
	.reset_status(lsr_mask)
);



localparam s_idle        = 3'd0;
localparam s_send_start  = 3'd1;
localparam s_send_byte   = 3'd2;
localparam s_send_parity = 3'd3;
localparam s_send_stop   = 3'd4;
localparam s_pop_byte    = 3'd5;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	tstate       <= s_idle;
	stx_o_tmp       <= 1'b1;
	counter   <= 5'b0;
	shift_out   <= 7'b0;
	bit_out     <= 1'b0;
	parity_xor  <= 1'b0;
	tf_pop      <= 1'b0;
	bit_counter <= 3'b0;
  end
  else
  if (enable | SIM)
  begin
	case (tstate)
	s_idle	 :	if (~|tf_count)
			begin
				tstate <= s_idle;
				stx_o_tmp <= 1'b1;
			end
			else
			begin
				tf_pop <= 1'b0;
				stx_o_tmp  <= 1'b1;
				tstate  <= s_pop_byte;
			end
	s_pop_byte :	begin
				tf_pop <= 1'b1;
				case (lcr[1:0])
				2'b00 : begin
					bit_counter <= 3'b100;
					parity_xor  <= ^tf_data_out[4:0];
				     end
				2'b01 : begin
					bit_counter <= 3'b101;
					parity_xor  <= ^tf_data_out[5:0];
				     end
				2'b10 : begin
					bit_counter <= 3'b110;
					parity_xor  <= ^tf_data_out[6:0];
				     end
				2'b11 : begin
					bit_counter <= 3'b111;
					parity_xor  <= ^tf_data_out[7:0];
				     end
				endcase
				{shift_out[6:0], bit_out} <= tf_data_out;
				tstate <= s_send_start;
			end
	s_send_start :	begin
				tf_pop <= 1'b0;
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					counter <= 0;
					tstate <= s_send_byte;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= 1'b0;
				if (SIM) begin
					tstate <= s_idle;
					$write("%c", tf_data_out);
					$fflush(32'h80000001);
				end
			end
	s_send_byte :	begin
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					if (bit_counter > 3'b0)
					begin
						bit_counter <= bit_counter - 3'd1;
						{shift_out[5:0],bit_out  } <= {shift_out[6:1], shift_out[0]};
						tstate <= s_send_byte;
					end
					else
					if (~lcr[`UART_LC_PE])
					begin
						tstate <= s_send_stop;
					end
					else
					begin
						case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
						2'b00:	bit_out <= ~parity_xor;
						2'b01:	bit_out <= 1'b1;
						2'b10:	bit_out <= parity_xor;
						2'b11:	bit_out <= 1'b0;
						endcase
						tstate <= s_send_parity;
					end
					counter <= 0;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= bit_out;
			end
	s_send_parity :	begin
				if (~|counter)
					counter <= 5'b01111;
				else
				if (counter == 5'b00001)
				begin
					counter <= 5'd0;
					tstate <= s_send_stop;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= bit_out;
			end
	s_send_stop :  begin
				if (~|counter)
				  begin
						casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
  						3'b0??:	  counter <= 5'b01101;
  						3'b100:	  counter <= 5'b10101;
  						default:	  counter <= 5'b11101;
						endcase
					end
				else
				if (counter == 5'b00001)
				begin
					counter <= 0;
					tstate <= s_idle;
				end
				else
					counter <= counter - 5'd1;
				stx_o_tmp <= 1'b1;
			end

		default :
			tstate <= s_idle;
	endcase
  end
  else
    tf_pop <= 1'b0;
end

assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;
	
endmodule