data/full_repos/permissive/480681467/main/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:25: Operator ASSIGN expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                   : ... In instance control.i.x_mod_y\n           p = {p[WIDTH-2:0],A[WIDTH-1]};\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:38: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 65 bits.\n                                                                   : ... In instance control.i.x_mod_y\n   assign R = p,Q = A;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'p\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'q\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:119: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_reg\' generates 32 bits.\n                                                                    : ... In instance control.i\n    assign e = e_reg;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:151: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_plus3\' generates 32 bits.\n                                                                    : ... In instance control.i\n                         b <= e_plus3;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:77: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                   : ... In instance control.m\n            result_reg <= 32\'d1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:190: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'msg_in\' generates 32 bits.\n                                                                    : ... In instance control\n         msg_reg <= msg_in;\n                 ^~\n%Error: Exiting due to 8 warning(s)\n'
module mod_exp(
    input [WIDTH*2-1:0] base,
	input [WIDTH*2-1:0] modulo,
	input [WIDTH*2-1:0] exponent,
	input clk,
	input reset,
	output finish,
    output [WIDTH*2-1:0] result
    );
    
    parameter WIDTH = 32;
        
    reg [WIDTH*2-1:0] base_reg,modulo_reg,exponent_reg,result_reg;
    reg [1:0] state;
    
    wire [WIDTH*2-1:0] result_mul_base = result_reg * base_reg;
    wire [WIDTH*2-1:0] result_next;
    wire [WIDTH*2-1:0] base_squared = base_reg * base_reg;
    wire [WIDTH*2-1:0] base_next;
    wire [WIDTH*2-1:0] exponent_next = exponent_reg >> 1;
    
    assign finish = (state == `HOLD) ? 1'b1:1'b0;
    assign result = result_reg;
    
    mod base_squared_mod(base_squared,modulo_reg,base_next,);
    defparam base_squared_mod.WIDTH = WIDTH*2;
                                                                                  
    mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,);
    defparam result_mul_base_mod.WIDTH = WIDTH*2;
    
   
    always @(posedge clk) begin
        if(reset) begin
            base_reg <= base;
            modulo_reg <= modulo;
            exponent_reg <= exponent;                
            result_reg <= 32'd1;
            state <= `UPDATE;
        end
        else case(state)
            `UPDATE: begin
                if (exponent_reg != 64'd0) begin
                    if (exponent_reg[0])
                        result_reg <= result_next;
                    base_reg <= base_next;
                    exponent_reg <= exponent_next;
                    state <= `UPDATE;
                end
                else state <= `HOLD;
            end
            
           `HOLD: begin
                end
       endcase
    end
endmodule
module mod_exp(
    input [WIDTH*2-1:0] base,
	input [WIDTH*2-1:0] modulo,
	input [WIDTH*2-1:0] exponent,
	input clk,
	input reset,
	output finish,
    output [WIDTH*2-1:0] result
    );

    
    parameter WIDTH = 32;
        
    reg [WIDTH*2-1:0] base_reg,modulo_reg,exponent_reg,result_reg;
    reg [1:0] state;
    
    wire [WIDTH*2-1:0] result_mul_base = result_reg * base_reg;
    wire [WIDTH*2-1:0] result_next;
    wire [WIDTH*2-1:0] base_squared = base_reg * base_reg;
    wire [WIDTH*2-1:0] base_next;
    wire [WIDTH*2-1:0] exponent_next = exponent_reg >> 1;
    
    assign finish = (state == `HOLD) ? 1'b1:1'b0;
    assign result = result_reg;
    
    mod base_squared_mod(base_squared,modulo_reg,base_next,);
    defparam base_squared_mod.WIDTH = WIDTH*2;
                                                                                  
    mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,);
    defparam result_mul_base_mod.WIDTH = WIDTH*2;
    
   
    always @(posedge clk) begin
        if(reset) begin
            base_reg <= base;
            modulo_reg <= modulo;
            exponent_reg <= exponent;                
            result_reg <= 32'd1;
            state <= `UPDATE;
        end
        else case(state)
            `UPDATE: begin
                if (exponent_reg != 64'd0) begin
                    if (exponent_reg[0])
                        result_reg <= result_next;
                    base_reg <= base_next;
                    exponent_reg <= exponent_next;
                    state <= `UPDATE;
                end
                else state <= `HOLD;
            end
            
           `HOLD: begin
                end
       endcase
    end
endmodule