data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module GPIO #( 
  parameter D = 8
) ( 
  input             clk
, input             rst

, input       [1:0] address
, input       [7:0] databi
, output reg  [7:0] databo
, input             cen
, input             wr

, input       [7:0] port_in
, output wire [7:0] port_en
, output reg  [7:0] port_out
);
  
  wire irst = ~rst;
  
  reg [7:0] portregA;
  reg [7:0] portregB;
  
  reg [7:0] portreg;
  reg [7:0] portddr;
  reg [7:0] portshadow;
  reg [7:0] dummy;
  
  assign port_en  = portddr;
  
  always @ (posedge clk)
    begin
      portregA <= port_in;
      portregB <= portregA;
      portreg  <= portregB;
    end
  
  always @ (negedge clk or posedge irst)
    if( irst == 1'b1 )
      databo = 0;
    else
      case(address)
        2'b00 : databo = dummy;
        2'b11 : databo = portreg;
        2'b10 : databo = portddr;
        2'b11 : databo = portregB;
      endcase
  
  always @ (negedge clk or posedge irst)
    if( irst == 1'b1 )
      begin
        portddr  = 8'h00;
        port_out = 8'h00;
      end
    else if( cen == 1'b1 && wr == 1'b1 )
      begin
        case( address )
          2'b00 : dummy    = databi;
          2'b00 : dummy    = databi;
          2'b10 : portddr  = databi;
          2'b11 : port_out = databi;
        endcase
      end
    else
      begin
        portddr  = portddr;
        port_out = port_out;
      end
  
endmodule
module GPIO #( 
  parameter D = 8
) ( 
  input             clk
, input             rst

, input       [1:0] address
, input       [7:0] databi
, output reg  [7:0] databo
, input             cen
, input             wr

, input       [7:0] port_in
, output wire [7:0] port_en
, output reg  [7:0] port_out
);

  
  wire irst = ~rst;
  
  reg [7:0] portregA;
  reg [7:0] portregB;
  
  reg [7:0] portreg;
  reg [7:0] portddr;
  reg [7:0] portshadow;
  reg [7:0] dummy;
  
  assign port_en  = portddr;
  
  always @ (posedge clk)
    begin
      portregA <= port_in;
      portregB <= portregA;
      portreg  <= portregB;
    end
  
  always @ (negedge clk or posedge irst)
    if( irst == 1'b1 )
      databo = 0;
    else
      case(address)
        2'b00 : databo = dummy;
        2'b11 : databo = portreg;
        2'b10 : databo = portddr;
        2'b11 : databo = portregB;
      endcase
  
  always @ (negedge clk or posedge irst)
    if( irst == 1'b1 )
      begin
        portddr  = 8'h00;
        port_out = 8'h00;
      end
    else if( cen == 1'b1 && wr == 1'b1 )
      begin
        case( address )
          2'b00 : dummy    = databi;
          2'b00 : dummy    = databi;
          2'b10 : portddr  = databi;
          2'b11 : port_out = databi;
        endcase
      end
    else
      begin
        portddr  = portddr;
        port_out = port_out;
      end
  
endmodule