data/full_repos/permissive/415491487/design_src/dpdatamem.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/415491487/design_src/dpdatamem.v:16: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'imem\'\nmodule imem(\n       ^~~~\n                                                                                 : ... Top module \'dpdmem\'\nmodule dpdmem(\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/415491487/design_src/dpdatamem.v:32: Bit extraction of array[127:0] requires 7 bit index, not 24 bits.\n                                                                              : ... In instance dpdmem\n            ram[waddr] <= wdata;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/415491487/design_src/dpdatamem.v:34: Bit extraction of array[127:0] requires 7 bit index, not 24 bits.\n                                                                              : ... In instance dpdmem\n        rdata <= ram[raddr];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/415491487/design_src/dpdatamem.v:12: Bit extraction of array[127:0] requires 7 bit index, not 24 bits.\n                                                                              : ... In instance imem\n        data <= rom[addr];\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module dpdmem(
    input clk,
    input [23:0] waddr,
    input [23:0] wdata,
    
    input [23:0] raddr,
    output reg [23:0] rdata,
    
    input wen
);
    
    parameter mem_size = 128;
    reg [23:0] ram[mem_size - 1:0];
    
    always @(negedge clk) begin
        if (wen) begin
            ram[waddr] <= wdata;
        end
        rdata <= ram[raddr];
    end
endmodule
module dpdmem(
    input clk,
    input [23:0] waddr,
    input [23:0] wdata,
    
    input [23:0] raddr,
    output reg [23:0] rdata,
    
    input wen
);

    
    parameter mem_size = 128;
    reg [23:0] ram[mem_size - 1:0];
    
    always @(negedge clk) begin
        if (wen) begin
            ram[waddr] <= wdata;
        end
        rdata <= ram[raddr];
    end
endmodule