data/full_repos/permissive/516809949/digital/rtl/clkg.v
1: b"%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:65: Cannot find file containing module: 'CKLNQD1'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.v\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:116: Cannot find file containing module: 'INVLONG_OSC37'\n    INVLONG_OSC37 U_CLK_OSC(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:122: Cannot find file containing module: 'INVD2'\n    INVD2 U_CLK_OSC_DRV(\n    ^~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:126: Cannot find file containing module: 'MUX2D0'\n    MUX2D0 U_MUX2_JTAG_OSC(\n    ^~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:139: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_SMP(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:145: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_NCM(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:151: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_MSK(\n    ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module clkdiv(input  wire       clk,
              input  wire       rst_n,
              input  wire       i_en,
              input  wire [2:0] i_div,
              output reg        o_clk_div);
              
  wire clk_pre;

  wire clk_div2;
  wire clk_div4;
  wire clk_div8;
  wire clk_div16;
  wire clk_div32;
  wire clk_div64;
  wire clk_div128;
  wire clk_div256;

  CKLNQD1 U_CLK_GATE(
    .TE ( 1'b0    ) ,
    .E  ( i_en    ) ,
    .CP ( clk     ) ,
    .Q  ( clk_pre ) );

  clkdiv256 U_CLK_DIV(
    .clk          ( clk_pre    ) ,
    .rst_n        ( rst_n      ) ,
    .o_clk_div2   ( clk_div2   ) ,
    .o_clk_div4   ( clk_div4   ) ,
    .o_clk_div8   ( clk_div8   ) ,
    .o_clk_div16  ( clk_div16  ) ,
    .o_clk_div32  ( clk_div32  ) ,
    .o_clk_div64  ( clk_div64  ) ,
    .o_clk_div128 ( clk_div128 ) ,
    .o_clk_div256 ( clk_div256 ) );

  always @*
    case (i_div)
      3'd0: o_clk_div = clk_div2;
      3'd1: o_clk_div = clk_div4;
      3'd2: o_clk_div = clk_div8;
      3'd3: o_clk_div = clk_div16;
      3'd4: o_clk_div = clk_div32;
      3'd5: o_clk_div = clk_div64;
      3'd6: o_clk_div = clk_div128;
      3'd7: o_clk_div = clk_div256;
      default: o_clk_div = clk_div2;
    endcase

endmodule
module clkdiv(input  wire       clk,
              input  wire       rst_n,
              input  wire       i_en,
              input  wire [2:0] i_div,
              output reg        o_clk_div);

              
  wire clk_pre;

  wire clk_div2;
  wire clk_div4;
  wire clk_div8;
  wire clk_div16;
  wire clk_div32;
  wire clk_div64;
  wire clk_div128;
  wire clk_div256;

  CKLNQD1 U_CLK_GATE(
    .TE ( 1'b0    ) ,
    .E  ( i_en    ) ,
    .CP ( clk     ) ,
    .Q  ( clk_pre ) );

  clkdiv256 U_CLK_DIV(
    .clk          ( clk_pre    ) ,
    .rst_n        ( rst_n      ) ,
    .o_clk_div2   ( clk_div2   ) ,
    .o_clk_div4   ( clk_div4   ) ,
    .o_clk_div8   ( clk_div8   ) ,
    .o_clk_div16  ( clk_div16  ) ,
    .o_clk_div32  ( clk_div32  ) ,
    .o_clk_div64  ( clk_div64  ) ,
    .o_clk_div128 ( clk_div128 ) ,
    .o_clk_div256 ( clk_div256 ) );

  always @*
    case (i_div)
      3'd0: o_clk_div = clk_div2;
      3'd1: o_clk_div = clk_div4;
      3'd2: o_clk_div = clk_div8;
      3'd3: o_clk_div = clk_div16;
      3'd4: o_clk_div = clk_div32;
      3'd5: o_clk_div = clk_div64;
      3'd6: o_clk_div = clk_div128;
      3'd7: o_clk_div = clk_div256;
      default: o_clk_div = clk_div2;
    endcase

endmodule