data/full_repos/permissive/42434302/ivltests/pr2815398b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:11: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 3 bits.\n                                                                            : ... In instance top\n      if (arr[i] !== i) begin\n                 ^~~\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:21: Selection index out of range: 20 outside 7:0\n                                                                               : ... In instance top\n  assign arr[20] = \'b0;\n            ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 8 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?h8\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 9 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?h9\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 10 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?ha\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 11 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hb\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 12 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hc\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 13 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hd\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 14 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?he\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Warning-SELRANGE: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Selection index out of range: 15 outside 7:0\n                                                                               : ... In instance top\n      assign arr[m] = m;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2815398b.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hf\' generates 32 or 4 bits.\n                                                                            : ... In instance top\n      assign arr[m] = m;\n                    ^\n%Error: Exiting due to 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  wire [2:0] arr [0:7];
  reg rarr [0:7];
  integer i;

  initial begin
    pass = 1'b1;
    #1;
    for (i = 0; i <=7 ; i = i + 1) begin
      if (arr[i] !== i) begin
        $display("FAILED: index %1d, expected %1d, got %1d", i, i, arr[i]);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end


  assign arr[20] = 'b0;
  assign arr[-1] = 'b0;


  genvar m;
  generate

    for (m=0; m<=15; m=m+1) begin: arr_loop
      assign arr[m] = m;
    end
  endgenerate
endmodule
module top;

  reg pass;
  wire [2:0] arr [0:7];
  reg rarr [0:7];
  integer i;

  initial begin
    pass = 1'b1;
    #1;
    for (i = 0; i <=7 ; i = i + 1) begin
      if (arr[i] !== i) begin
        $display("FAILED: index %1d, expected %1d, got %1d", i, i, arr[i]);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end


  assign arr[20] = 'b0;
  assign arr[-1] = 'b0;


  genvar m;
  generate

    for (m=0; m<=15; m=m+1) begin: arr_loop
      assign arr[m] = m;
    end
  endgenerate
endmodule