data/full_repos/permissive/43856783/Integrador/comp.v
data/verilator_xmls/043398c2-71ac-48d6-b0d0-871a8b76764e.xml
module comp(
    input [15:0] A,
    output [15:0] C
    );
	 
	 assign C = (~A)+1'b1;
	 
endmodule
module comp(
    input [15:0] A,
    output [15:0] C
    );

	 
	 assign C = (~A)+1'b1;
	 
endmodule