data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:1: Cannot find include file: UART_defines.v\n`include "UART_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/UART_defines.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/UART_defines.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/UART_defines.v.sv\n             UART_defines.v\n             UART_defines.v.v\n             UART_defines.v.sv\n             obj_dir/UART_defines.v\n             obj_dir/UART_defines.v.v\n             obj_dir/UART_defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:14: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~ clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:38: Unsupported: Ignoring delay on this delayed statement.\n #4 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 data_in = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10 pop = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 pop = 0;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:50: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:56: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:59: Unsupported: Ignoring delay on this delayed statement.\n              #2;\n              ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:65: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:68: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_FIFO_t.v:77: Unsupported: Ignoring delay on this delayed statement.\n     #1 $finish;\n     ^\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module FIFO_test ();

reg clk;

initial
begin
	clk = 0;

end

always
	#5 clk = ~ clk;

wire [4:0] count;
reg [7:0] data_in;
wire [7:0] data_out;
reg push, pop;
reg reset;

integer i,j,d,c;

UART_FIFO f(clk, 
	reset, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count

	);

initial 
begin
	#4 reset = 1;
	#10 reset = 0;
	#10 data_in = 1;
	#10 pop = 1;
	#10 pop = 0;
     for ( j=1; j<=2; j=j+1 )
     begin
	$display("Running with j=", j);
	d = j*5;
	for ( i=0 ;i<=17 ;i=i+1 )
	begin
		data_in = i;
		@(posedge clk);



		push <= #1 1;
		if (j==2) begin
			@(posedge clk);
			push <= #1 0;
		end
              #2;
		
	end
	push <= #1 0;
	for ( i=0 ;i<=17 ;i=i+1 )
	begin
		@(posedge clk);
		pop <= #1 1 ;
		if (j==2) begin
			@(posedge clk);
			pop <= #1 0;
		end
		c = i<=16 ? i : 16;


	end
	pop <= #1 0;
     end
     #1 $finish;
end

endmodule
module FIFO_test ();


reg clk;

initial
begin
	clk = 0;

end

always
	#5 clk = ~ clk;

wire [4:0] count;
reg [7:0] data_in;
wire [7:0] data_out;
reg push, pop;
reg reset;

integer i,j,d,c;

UART_FIFO f(clk, 
	reset, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count

	);

initial 
begin
	#4 reset = 1;
	#10 reset = 0;
	#10 data_in = 1;
	#10 pop = 1;
	#10 pop = 0;
     for ( j=1; j<=2; j=j+1 )
     begin
	$display("Running with j=", j);
	d = j*5;
	for ( i=0 ;i<=17 ;i=i+1 )
	begin
		data_in = i;
		@(posedge clk);



		push <= #1 1;
		if (j==2) begin
			@(posedge clk);
			push <= #1 0;
		end
              #2;
		
	end
	push <= #1 0;
	for ( i=0 ;i<=17 ;i=i+1 )
	begin
		@(posedge clk);
		pop <= #1 1 ;
		if (j==2) begin
			@(posedge clk);
			pop <= #1 0;
		end
		c = i<=16 ? i : 16;


	end
	pop <= #1 0;
     end
     #1 $finish;
end

endmodule