data/full_repos/permissive/517406069/verilog/rtl/la_switch.v
1: b"%Error: data/full_repos/permissive/517406069/verilog/rtl/la_switch.v:30: syntax error, unexpected ')', expecting '['\n)(\n^\n%Error: data/full_repos/permissive/517406069/verilog/rtl/la_switch.v:48: syntax error, unexpected assign\n    assign count_o <= count_r;\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module la_switch #(
    parameter WIDTH = 128,
)(

    input externalClock,
    input externalReset,


    input testClock,
    input testReset,

    input clockSelect,
);


    assign clockSelect = ~la_oenb[64];
    assign clk = clockSelect ? testRest : externalClock;
    assign rst = la_data_in[65];

    reg [BITS-1:0] count_r;
    assign count_o <= count_r;

    always @(posedge clk) begin
        if (rst) begin
            count_r <= 0;
        end
        
        else begin
            count_r <= next_count;
        end
    end

    always @(*) begin
        if(set) begin
            next_count = setValue_i;
        else begin
            next_count = count_r + INCREMENT_AMOUNT;
        end
    end
endmodule
module la_switch #(
    parameter WIDTH = 128,
)(

    input externalClock,
    input externalReset,


    input testClock,
    input testReset,

    input clockSelect,
);



    assign clockSelect = ~la_oenb[64];
    assign clk = clockSelect ? testRest : externalClock;
    assign rst = la_data_in[65];

    reg [BITS-1:0] count_r;
    assign count_o <= count_r;

    always @(posedge clk) begin
        if (rst) begin
            count_r <= 0;
        end
        
        else begin
            count_r <= next_count;
        end
    end

    always @(*) begin
        if(set) begin
            next_count = setValue_i;
        else begin
            next_count = count_r + INCREMENT_AMOUNT;
        end
    end
endmodule