data/full_repos/permissive/46989236/memory/memory.v
1: b'%Error: data/full_repos/permissive/46989236/memory/memory.v:9: Cannot find include file: attributes.v\n`include "attributes.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v.v\n             data/full_repos/permissive/46989236/memory,data/full_repos/permissive/46989236/attributes.v.sv\n             attributes.v\n             attributes.v.v\n             attributes.v.sv\n             obj_dir/attributes.v\n             obj_dir/attributes.v.v\n             obj_dir/attributes.v.sv\n%Error: data/full_repos/permissive/46989236/memory/memory.v:2: Define or directive not defined: \'`ADDR_WIDTH\'\ninput [`ADDR_WIDTH-1:0]addr,\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory.v:3: Define or directive not defined: \'`INSTR_WIDTH\'\ninput [`INSTR_WIDTH-1:0]d_in,\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory.v:5: Define or directive not defined: \'`INSTR_WIDTH\'\noutput reg [`INSTR_WIDTH-1:0]d_out\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory.v:7: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1:0] binary [0:`MEM_SIZE-1];\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/memory/memory.v:7: Define or directive not defined: \'`MEM_SIZE\'\nreg [`INSTR_WIDTH-1:0] binary [0:`MEM_SIZE-1];\n                                 ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module memory(
input [`ADDR_WIDTH-1:0]addr,
input [`INSTR_WIDTH-1:0]d_in,
input rwbar,
output reg [`INSTR_WIDTH-1:0]d_out
);
reg [`INSTR_WIDTH-1:0] binary [0:`MEM_SIZE-1];
initial begin
`include "attributes.v"
$readmemh("binary.hex",binary);
end

always @ (rwbar)
if (rwbar)
d_out = binary[addr];
else
binary[addr] = d_in;

always @ (addr)
if (rwbar)
d_out = binary[addr];
else
binary[addr] = d_in;

endmodule
module memory(
input [`ADDR_WIDTH-1:0]addr,
input [`INSTR_WIDTH-1:0]d_in,
input rwbar,
output reg [`INSTR_WIDTH-1:0]d_out
);

reg [`INSTR_WIDTH-1:0] binary [0:`MEM_SIZE-1];
initial begin
`include "attributes.v"
$readmemh("binary.hex",binary);
end

always @ (rwbar)
if (rwbar)
d_out = binary[addr];
else
binary[addr] = d_in;

always @ (addr)
if (rwbar)
d_out = binary[addr];
else
binary[addr] = d_in;

endmodule