data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:40: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n wire [W+1:0] dist;\n              ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:40: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire [W+1:0] dist;\n                  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:57: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n  .dist(dist)\n   ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:57: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n  .dist(dist)\n        ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:57: syntax error, unexpected '('\n  .dist(dist)\n            ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:68: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n  .B(dist),\n     ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/first_nns_seq_td.v:90: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n  .A(dist),\n     ^~~~\n%Error: Exiting due to 7 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
function integer log2;
		input [31:0] value;
		reg [31:0] temp;
	begin
		temp = value;
		for (log2=0; temp>0; log2=log2+1)
			temp = temp>>1;
	end
	endfunction
function integer log2;

		input [31:0] value;
		reg [31:0] temp;
	begin
		temp = value;
		for (log2=0; temp>0; log2=log2+1)
			temp = temp>>1;
	end
	endfunction