data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    always #50 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd"); $dumpvars(0,"ttl_74166_tb");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpfile("dump.vcd"); $dumpvars(0,"ttl_74166_tb");\n                               ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #125;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:39: syntax error, unexpected always\n        repeat (7) always @(posedge clk);\n                   ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #75;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #175;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #75;\n        ^\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_tb.v:57: syntax error, unexpected always\n        repeat (10) always @(posedge clk);\n                    ^~~~~~\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ttl_74166_tb();
    reg clr;
    reg inh;
    reg sh_ldn;
    reg ser_in;
    reg [7:0] d_in;
    wire ser_out;
    integer i;


    reg clk = 0;
    always #50 clk = !clk;
  
    initial begin
        $dumpfile("dump.vcd"); $dumpvars(0,"ttl_74166_tb");
        inh = 1'b0;
        clr = 1'b1;
        ser_in = 1'b0;
        sh_ldn = 1'b1;
        d_in = 8'b00000000;

        

        #25;
        clr = 1'b0;
        #50;
        clr = 1'b1;


        #50;
        ser_in = 1'b1;
        #125;
        ser_in = 1'b0;
        #50;

        repeat (7) always @(posedge clk);


        #50;
        sh_ldn = 1'b0;
        d_in = 8'b10011010;


        #75;
        inh = 1'b1;
        #25;
        sh_ldn = 1'b1;
        d_in = 8'b00000000;
        #175;
        inh = 1'b0;
        #75;


        repeat (10) always @(posedge clk);
        $finish;
    end
  
    ttl_74166 uut
        (
        .CLRn(clr),
        .CLK(clk),
        .INH(inh),
        .SH_LDn(sh_ldn),
        .SER(ser_in),
        .D(d_in),
        .Q(ser_out));
endmodule
module ttl_74166_tb();

    reg clr;
    reg inh;
    reg sh_ldn;
    reg ser_in;
    reg [7:0] d_in;
    wire ser_out;
    integer i;


    reg clk = 0;
    always #50 clk = !clk;
  
    initial begin
        $dumpfile("dump.vcd"); $dumpvars(0,"ttl_74166_tb");
        inh = 1'b0;
        clr = 1'b1;
        ser_in = 1'b0;
        sh_ldn = 1'b1;
        d_in = 8'b00000000;

        

        #25;
        clr = 1'b0;
        #50;
        clr = 1'b1;


        #50;
        ser_in = 1'b1;
        #125;
        ser_in = 1'b0;
        #50;

        repeat (7) always @(posedge clk);


        #50;
        sh_ldn = 1'b0;
        d_in = 8'b10011010;


        #75;
        inh = 1'b1;
        #25;
        sh_ldn = 1'b1;
        d_in = 8'b00000000;
        #175;
        inh = 1'b0;
        #75;


        repeat (10) always @(posedge clk);
        $finish;
    end
  
    ttl_74166 uut
        (
        .CLRn(clr),
        .CLK(clk),
        .INH(inh),
        .SH_LDn(sh_ldn),
        .SER(ser_in),
        .D(d_in),
        .Q(ser_out));
endmodule