data/full_repos/permissive/491135068/DFF2.v
data/verilator_xmls/a251b61b-d83c-461c-b320-38a2c1b12403.xml
module DFF2(
    input [1:0] DFFIN2,
    input clk,
    output reg [1:0] DFFOUT2
    );
    always @(posedge clk) begin
        DFFOUT2 = DFFIN2;
    end
endmodule
module DFF2(
    input [1:0] DFFIN2,
    input clk,
    output reg [1:0] DFFOUT2
    );

    always @(posedge clk) begin
        DFFOUT2 = DFFIN2;
    end
endmodule