data/full_repos/permissive/503053625/fpga_projects/SPGD/src/pulse_FSM.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/pulse_FSM.v:15: Cannot find file containing module: 'my_D_FF'\nmy_D_FF FF_0(.d(ad), .clk(clk), .rst(rst), .q(A));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/my_D_FF\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/my_D_FF.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/my_D_FF.sv\n             my_D_FF\n             my_D_FF.v\n             my_D_FF.sv\n             obj_dir/my_D_FF\n             obj_dir/my_D_FF.v\n             obj_dir/my_D_FF.sv\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/pulse_FSM.v:16: Cannot find file containing module: 'my_D_FF'\nmy_D_FF FF_1(.d(bd), .clk(clk), .rst(rst), .q(B));\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module pulse_FSM
(
	input s,
	input clk,
	input rst,
	output P,
	output L,
	output A,
	output B
);

wire ad;
wire bd;

my_D_FF FF_0(.d(ad), .clk(clk), .rst(rst), .q(A));
my_D_FF FF_1(.d(bd), .clk(clk), .rst(rst), .q(B));

assign ad = ~B&s | A&~B | A&~s;
assign bd = A | B&s;
assign P = A&~B;
assign L = B;

endmodule
module pulse_FSM
(
	input s,
	input clk,
	input rst,
	output P,
	output L,
	output A,
	output B
);


wire ad;
wire bd;

my_D_FF FF_0(.d(ad), .clk(clk), .rst(rst), .q(A));
my_D_FF FF_1(.d(bd), .clk(clk), .rst(rst), .q(B));

assign ad = ~B&s | A&~B | A&~s;
assign bd = A | B&s;
assign P = A&~B;
assign L = B;

endmodule