data/full_repos/permissive/503578084/pipeline/stop_pipelined_unit.v
data/verilator_xmls/8274d4f7-a29c-462b-9906-881979d198dc.xml
module stop_pipelined_unit(
    input   rst_n,
    input   load_use_hazard,
    output  reg stop
    );
    
always @ (*) begin
    if(rst_n=='b0) begin
        stop='b0;
    end
    else if(load_use_hazard=='b1) begin
        stop='b1;
    end
    else begin
        stop='b0;
    end
end
    
endmodule
module stop_pipelined_unit(
    input   rst_n,
    input   load_use_hazard,
    output  reg stop
    );

    
always @ (*) begin
    if(rst_n=='b0) begin
        stop='b0;
    end
    else if(load_use_hazard=='b1) begin
        stop='b1;
    end
    else begin
        stop='b0;
    end
end
    
endmodule