data/full_repos/permissive/417288846/List_3/Task_3/stoper.v
data/verilator_xmls/11db30f6-6c84-4996-b994-2b0189c376f4.xml
module stoper(input clk, rst, output [15:0] num);
    wire reset_all, reset_seconds, n1, n2;

    assign reset_all = rst | (num[15:12] == 9 & num[11:8] == 9);
    assign  reset_seconds = reset_all | (num[7:4] == 6);

    BCD b1(.clk(clk), .rst(rst), .num(num[3:0]), .next(n1));
    BCD b2(.clk(n1), .rst(reset_seconds), .num(num[7:4]), .next());

    BCD b3(.clk(reset_seconds), .rst(reset_all), .num(num[11:8]), .next(n2));
    BCD b4(.clk(n2), .rst(reset_all), .num(num[15:12]), .next());
endmodule
module stoper(input clk, rst, output [15:0] num);

    wire reset_all, reset_seconds, n1, n2;

    assign reset_all = rst | (num[15:12] == 9 & num[11:8] == 9);
    assign  reset_seconds = reset_all | (num[7:4] == 6);

    BCD b1(.clk(clk), .rst(rst), .num(num[3:0]), .next(n1));
    BCD b2(.clk(n1), .rst(reset_seconds), .num(num[7:4]), .next());

    BCD b3(.clk(reset_seconds), .rst(reset_all), .num(num[11:8]), .next(n2));
    BCD b4(.clk(n2), .rst(reset_all), .num(num[15:12]), .next());
endmodule