data/full_repos/permissive/463439324/keygen/modmul4591S28.v
1: b'%Error: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:67: Cannot find file containing module: \'mod4591Svec28\'\n    mod4591Svec28 m4591Sv0 ( .z_in(regZ), .p0(intP0), .p1(intP1), .n0(intN0), .n1(intN1) );\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/mod4591Svec28\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/mod4591Svec28.v\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/mod4591Svec28.sv\n             mod4591Svec28\n             mod4591Svec28.v\n             mod4591Svec28.sv\n             obj_dir/mod4591Svec28\n             obj_dir/mod4591Svec28.v\n             obj_dir/mod4591Svec28.sv\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:83: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h5c22\' generates 15 bits.\n                                                                              : ... In instance modmul4591S\n            4\'h7:                           intMODQ = 15\'h5c22;  \n                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:84: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h6e11\' generates 15 bits.\n                                                                              : ... In instance modmul4591S\n            4\'h2, 4\'h3, 4\'h4, 4\'h5, 4\'h6:   intMODQ = 15\'h6e11;  \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:85: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                              : ... In instance modmul4591S\n            4\'he, 4\'hf, 4\'h0, 4\'h1:         intMODQ = 15\'h0000;  \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:86: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h11ef\' generates 15 bits.\n                                                                              : ... In instance modmul4591S\n            4\'h9, 4\'ha, 4\'hb, 4\'hc, 4\'hd:   intMODQ = 15\'h11ef;  \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:87: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h23de\' generates 15 bits.\n                                                                              : ... In instance modmul4591S\n            4\'h8:                           intMODQ = 15\'h23de;  \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/modmul4591S28.v:91: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 15 bits.\n                                                                              : ... In instance modmul4591S\n    assign intAB = { regD[13], regD } + intMODQ;\n                 ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module modmul4591S ( Clk, Reset, In, Out );

    input                       Clk;
	input						Reset;
    input signed        [27:0]  In;
    output reg          [12:0]  Out;

    reg signed  [27:0]  regZ;

    wire        [11:0]  intP0;
    wire        [11:0]  intP1;
    wire        [11:0]  intN0;
    wire        [11:0]  intN1;

    wire        [12:0]  intP;
    wire        [12:0]  intN;

    reg         [13:0]  regD;
    reg         [13:0]  intMODQ;

    wire        [13:0]  intAB;
	

    always @ ( posedge Clk ) begin
        if(Reset)
			regZ <= 0;
		else 
			regZ <= In[27:0];
    end

    mod4591Svec28 m4591Sv0 ( .z_in(regZ), .p0(intP0), .p1(intP1), .n0(intN0), .n1(intN1) );





    assign intP = intP0 + intP1;
    assign intN = intN0 + intN1;

    always @ ( posedge Clk ) begin

        regD <= { 1'b0, intP } - { 1'b0, intN };
    end

    always @ (*) begin
        case(regD[13:10])
            4'h7:                           intMODQ = 15'h5c22;
            4'h2, 4'h3, 4'h4, 4'h5, 4'h6:   intMODQ = 15'h6e11;
            4'he, 4'hf, 4'h0, 4'h1:         intMODQ = 15'h0000;
            4'h9, 4'ha, 4'hb, 4'hc, 4'hd:   intMODQ = 15'h11ef;
            4'h8:                           intMODQ = 15'h23de;
        endcase
    end

    assign intAB = { regD[13], regD } + intMODQ;

    always @ ( posedge Clk ) begin
        if(Reset)
			Out <= 0;
			
		
		else if($signed(intAB[12:0])>2295)
			Out <= $signed(intAB[12:0]) - 4591;
		else if($signed(intAB[12:0])<-2295)
			Out <= $signed(intAB[12:0]) + 4591;
		
		else 
			Out <= $signed(intAB[12:0]);
			
    end

endmodule
module modmul4591S ( Clk, Reset, In, Out );


    input                       Clk;
	input						Reset;
    input signed        [27:0]  In;
    output reg          [12:0]  Out;

    reg signed  [27:0]  regZ;

    wire        [11:0]  intP0;
    wire        [11:0]  intP1;
    wire        [11:0]  intN0;
    wire        [11:0]  intN1;

    wire        [12:0]  intP;
    wire        [12:0]  intN;

    reg         [13:0]  regD;
    reg         [13:0]  intMODQ;

    wire        [13:0]  intAB;
	

    always @ ( posedge Clk ) begin
        if(Reset)
			regZ <= 0;
		else 
			regZ <= In[27:0];
    end

    mod4591Svec28 m4591Sv0 ( .z_in(regZ), .p0(intP0), .p1(intP1), .n0(intN0), .n1(intN1) );





    assign intP = intP0 + intP1;
    assign intN = intN0 + intN1;

    always @ ( posedge Clk ) begin

        regD <= { 1'b0, intP } - { 1'b0, intN };
    end

    always @ (*) begin
        case(regD[13:10])
            4'h7:                           intMODQ = 15'h5c22;
            4'h2, 4'h3, 4'h4, 4'h5, 4'h6:   intMODQ = 15'h6e11;
            4'he, 4'hf, 4'h0, 4'h1:         intMODQ = 15'h0000;
            4'h9, 4'ha, 4'hb, 4'hc, 4'hd:   intMODQ = 15'h11ef;
            4'h8:                           intMODQ = 15'h23de;
        endcase
    end

    assign intAB = { regD[13], regD } + intMODQ;

    always @ ( posedge Clk ) begin
        if(Reset)
			Out <= 0;
			
		
		else if($signed(intAB[12:0])>2295)
			Out <= $signed(intAB[12:0]) - 4591;
		else if($signed(intAB[12:0])<-2295)
			Out <= $signed(intAB[12:0]) + 4591;
		
		else 
			Out <= $signed(intAB[12:0]);
			
    end

endmodule