data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchEightBitRippleCarryAdder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchEightBitRippleCarryAdder.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #20 a <= a + 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchEightBitRippleCarryAdder.v:12: Unsupported: Ignoring delay on this delayed statement.\n     #10 b <= b + 1;\n     ^\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchEightBitRippleCarryAdder.v:4: Cannot find file containing module: \'EightBitRippleCarryAdder\'\n   EightBitRippleCarryAdder ebrca(a,b,1\'b0,S);\n   ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/EightBitRippleCarryAdder\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/EightBitRippleCarryAdder.v\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/EightBitRippleCarryAdder.sv\n             EightBitRippleCarryAdder\n             EightBitRippleCarryAdder.v\n             EightBitRippleCarryAdder.sv\n             obj_dir/EightBitRippleCarryAdder\n             obj_dir/EightBitRippleCarryAdder.v\n             obj_dir/EightBitRippleCarryAdder.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchEightBitRippleCarryAdder;
   reg [7:0] a,b;
   wire [8:0] S;
   EightBitRippleCarryAdder ebrca(a,b,1'b0,S);
   initial begin
     a = 8'b00000000;
     b = 8'b00001111;
   end
   always
     #20 a <= a + 1;
   always
     #10 b <= b + 1;
endmodule
module TestBenchEightBitRippleCarryAdder;

   reg [7:0] a,b;
   wire [8:0] S;
   EightBitRippleCarryAdder ebrca(a,b,1'b0,S);
   initial begin
     a = 8'b00000000;
     b = 8'b00001111;
   end
   always
     #20 a <= a + 1;
   always
     #10 b <= b + 1;
endmodule