data/full_repos/permissive/528677531/LAB-4/Q3/qb.v
data/verilator_xmls/3ab07b3f-5c20-4c54-b0fc-3e356b6c8d54.xml
module adder2(x,y,cin,s,cout);
input [1:0]x,y;
input cin;
output [1:0]s;
output cout;
wire c1;
fulladder stage0(x[0],y[0],cin,s[0],c1);
fulladder stage1(x[1],y[1],c1,s[1],cout);
endmodule
module adder2(x,y,cin,s,cout);

input [1:0]x,y;
input cin;
output [1:0]s;
output cout;
wire c1;
fulladder stage0(x[0],y[0],cin,s[0],c1);
fulladder stage1(x[1],y[1],c1,s[1],cout);
endmodule