data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 3 bits.\n                                                                                                          : ... In instance Legalize.u_pad_2\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                          : ... In instance Legalize.u_pad_4\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:97: Operator COND expects 17 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 16 bits.\n                                                                                                          : ... In instance Legalize.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Legalize/reference/Legalize.v:18: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                          : ... In instance Legalize\n        .a(1\'d0),\n         ^\n%Error: Exiting due to 4 warning(s)\n'
module Legalize(
    input clock,
    input reset
);
    wire [2:0] done;
    assign done = 3'd6;
    wire [15:0] _count__q;
    wire [15:0] _count__d;
    DFF_POSCLK #(.width(16)) count (
        .q(_count__q),
        .d(_count__d),
        .clk(clock)
    );
    wire [15:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(16)) u_mux_1 (
        .y(_count__d),
        .sel(reset),
        .a(1'd0),
        .b(_WTEMP_0)
    );
    wire _node_0;
    wire [15:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(3), .n(16)) u_pad_2 (
        .y(_WTEMP_1),
        .in(done)
    );
    NEQ_UNSIGNED #(.width(16)) u_neq_3 (
        .y(_node_0),
        .a(_count__q),
        .b(_WTEMP_1)
    );
    wire [16:0] _node_1;
    wire [15:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_4 (
        .y(_WTEMP_2),
        .in(1'd1)
    );
    ADD_UNSIGNED #(.width(16)) u_add_5 (
        .y(_node_1),
        .a(_count__q),
        .b(_WTEMP_2)
    );
    wire [31:0] x;
    assign x = 32'hDEADBEEF;
    wire [15:0] y;
    wire [2:0] b;
    assign b = 3'h6;
    wire b2;
    assign b2 = 1'h1;
    wire [15:0] bar;
    assign bar = -16'sh1;
    wire bar_15;
    assign bar_15 = 1'h1;
    wire [16:0] _WTEMP_3;
    wire [16:0] _WTEMP_4;
    PAD_UNSIGNED #(.width(16), .n(17)) u_pad_6 (
        .y(_WTEMP_4),
        .in(_count__q)
    );
    MUX_UNSIGNED #(.width(17)) u_mux_7 (
        .y(_WTEMP_3),
        .sel(_node_0),
        .a(_node_1),
        .b(_WTEMP_4)
    );
    BITS #(.width(17), .high(15), .low(0)) bits_8 (
        .y(_WTEMP_0),
        .in(_WTEMP_3)
    );
    BITS #(.width(32), .high(15), .low(0)) bits_9 (
        .y(y),
        .in(32'hDEADBEEF)
    );
endmodule
module Legalize(
    input clock,
    input reset
);

    wire [2:0] done;
    assign done = 3'd6;
    wire [15:0] _count__q;
    wire [15:0] _count__d;
    DFF_POSCLK #(.width(16)) count (
        .q(_count__q),
        .d(_count__d),
        .clk(clock)
    );
    wire [15:0] _WTEMP_0;
    MUX_UNSIGNED #(.width(16)) u_mux_1 (
        .y(_count__d),
        .sel(reset),
        .a(1'd0),
        .b(_WTEMP_0)
    );
    wire _node_0;
    wire [15:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(3), .n(16)) u_pad_2 (
        .y(_WTEMP_1),
        .in(done)
    );
    NEQ_UNSIGNED #(.width(16)) u_neq_3 (
        .y(_node_0),
        .a(_count__q),
        .b(_WTEMP_1)
    );
    wire [16:0] _node_1;
    wire [15:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(16)) u_pad_4 (
        .y(_WTEMP_2),
        .in(1'd1)
    );
    ADD_UNSIGNED #(.width(16)) u_add_5 (
        .y(_node_1),
        .a(_count__q),
        .b(_WTEMP_2)
    );
    wire [31:0] x;
    assign x = 32'hDEADBEEF;
    wire [15:0] y;
    wire [2:0] b;
    assign b = 3'h6;
    wire b2;
    assign b2 = 1'h1;
    wire [15:0] bar;
    assign bar = -16'sh1;
    wire bar_15;
    assign bar_15 = 1'h1;
    wire [16:0] _WTEMP_3;
    wire [16:0] _WTEMP_4;
    PAD_UNSIGNED #(.width(16), .n(17)) u_pad_6 (
        .y(_WTEMP_4),
        .in(_count__q)
    );
    MUX_UNSIGNED #(.width(17)) u_mux_7 (
        .y(_WTEMP_3),
        .sel(_node_0),
        .a(_node_1),
        .b(_WTEMP_4)
    );
    BITS #(.width(17), .high(15), .low(0)) bits_8 (
        .y(_WTEMP_0),
        .in(_WTEMP_3)
    );
    BITS #(.width(32), .high(15), .low(0)) bits_9 (
        .y(y),
        .in(32'hDEADBEEF)
    );
endmodule