data/full_repos/permissive/435516446/MIPS/MIPS_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MIPS_TEST.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #100 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MIPS_TEST.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS_TEST.v:31: Cannot find file containing module: \'MIPS\'\n MIPS uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MIPS\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MIPS.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MIPS.sv\n             MIPS\n             MIPS.v\n             MIPS.sv\n             obj_dir/MIPS\n             obj_dir/MIPS.v\n             obj_dir/MIPS.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_TEST;


	reg clock;


	MIPS uut (
		.clock(clock)
	);
	always #100 clock = ~clock;
	initial begin

		clock = 0;


		#1000;
        


	end
      
endmodule
module MIPS_TEST;



	reg clock;


	MIPS uut (
		.clock(clock)
	);
	always #100 clock = ~clock;
	initial begin

		clock = 0;


		#1000;
        


	end
      
endmodule