data/full_repos/permissive/439731184/and_from_nand.v
1: b'%Error: data/full_repos/permissive/439731184/and_from_nand.v:26: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b", in0, in1, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/and_from_nand.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/and_from_nand.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/and_from_nand.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/and_from_nand.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_from_nands_tb();

reg in0, in1;
wire out;

and_from_nands N(out, in0, in1);

initial begin
    $display("in0\tin1\tout");
    $monitor("%b\t%b\t%b", in0, in1, out);
    in0 <= 0;
    in1 <= 0;
    #1 in0 <= 1;
    #1 in0 <= 0;
    in1 <= 1;
    #1 in0 <= 1;
    #1 $finish;
end

endmodule
module and_from_nands_tb();


reg in0, in1;
wire out;

and_from_nands N(out, in0, in1);

initial begin
    $display("in0\tin1\tout");
    $monitor("%b\t%b\t%b", in0, in1, out);
    in0 <= 0;
    in1 <= 0;
    #1 in0 <= 1;
    #1 in0 <= 0;
    in1 <= 1;
    #1 in0 <= 1;
    #1 $finish;
end

endmodule