data/full_repos/permissive/445357518/top.v
1: b"%Error: data/full_repos/permissive/445357518/top.v:42: Cannot find file containing module: 'cpu'\ncpu CPU(clk,reset,read_data,datapath_out,N,V,Z,mem_cmd,mem_addr);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/445357518/top.v:72: Cannot find file containing module: 'vDFF1'\nvDFF1 #(8) LED_REG(clk, write_data[7:0], loadOut, LEDR[7:0]);\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module sseg(in,segs);
  input [3:0] in;
  output [6:0] segs;
  reg [6:0] segs;


  always @* begin
    case(in)
     4'd0: segs = 7'b1000000;
     4'd1: segs = 7'b1111001;
     4'd2: segs = 7'b0100100; 
     4'd3: segs = 7'b0110000;
     4'd4: segs = 7'b0011001;
     4'd5: segs = 7'b0010010;
     4'd6: segs = 7'b0000010; 
     4'd7: segs = 7'b1111000;
     4'd8: segs = 7'b0000000;
     4'd9: segs = 7'b0010000;
     4'd10: segs = 7'b0001000;
     4'd11: segs = 7'b0000011;
     4'd12: segs = 7'b1000110;
     4'd13: segs = 7'b0100001;
     4'd14: segs = 7'b0000110;
     4'd15: segs = 7'b0001110;
     default: segs=7'bxxxxxxx;
    endcase
  end
endmodule
module sseg(in,segs);

  input [3:0] in;
  output [6:0] segs;
  reg [6:0] segs;


  always @* begin
    case(in)
     4'd0: segs = 7'b1000000;
     4'd1: segs = 7'b1111001;
     4'd2: segs = 7'b0100100; 
     4'd3: segs = 7'b0110000;
     4'd4: segs = 7'b0011001;
     4'd5: segs = 7'b0010010;
     4'd6: segs = 7'b0000010; 
     4'd7: segs = 7'b1111000;
     4'd8: segs = 7'b0000000;
     4'd9: segs = 7'b0010000;
     4'd10: segs = 7'b0001000;
     4'd11: segs = 7'b0000011;
     4'd12: segs = 7'b1000110;
     4'd13: segs = 7'b0100001;
     4'd14: segs = 7'b0000110;
     4'd15: segs = 7'b0001110;
     default: segs=7'bxxxxxxx;
    endcase
  end
endmodule