data/full_repos/permissive/445929378/modulo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/modulo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/modulo_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/modulo_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Error: data/full_repos/permissive/445929378/modulo_tb.v:21: Cannot find file containing module: \'modulo\'\n   modulo uut(\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/modulo\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/modulo.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/modulo.sv\n             modulo\n             modulo.v\n             modulo.sv\n             obj_dir/modulo\n             obj_dir/modulo.v\n             obj_dir/modulo.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module modulo_tb #(parameter SIZE = 128);


   reg clk;
   reg rst;
   reg [SIZE-1 : 0] dividen;
   reg 		    dividen_tvalid;
   reg [(SIZE/2)-1 : 0] divisor;
   reg 		    divisor_tvalid;
   reg 		    output_tready;


   wire 	    dividen_tready;
   wire 	    divisor_tready;
   wire [(SIZE/2)-1 : 0] output_tdata;
   wire 		 output_tvalid;


   modulo uut(
	      .clk(clk), 
	      .rst(rst), 
	      .input_dividen_tdata(dividen), 
	      .input_dividen_tvalid(dividen_tvalid), 
	      .input_dividen_tready(dividen_tready), 
	      .input_divisor_tdata(divisor), 
	      .input_divisor_tvalid(divisor_tvalid), 
	      .input_divisor_tready(divisor_tready), 
	      .output_tdata(output_tdata), 
	      .output_tvalid(output_tvalid), 
	      .output_tready(output_tready)
	      
	      );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;


      dividen = 128'd85070591730234607177427193140743463569;
      dividen_tvalid = 1;

      divisor = 64'd9223372036854775433;
      divisor_tvalid = 1;
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule
module modulo_tb #(parameter SIZE = 128);



   reg clk;
   reg rst;
   reg [SIZE-1 : 0] dividen;
   reg 		    dividen_tvalid;
   reg [(SIZE/2)-1 : 0] divisor;
   reg 		    divisor_tvalid;
   reg 		    output_tready;


   wire 	    dividen_tready;
   wire 	    divisor_tready;
   wire [(SIZE/2)-1 : 0] output_tdata;
   wire 		 output_tvalid;


   modulo uut(
	      .clk(clk), 
	      .rst(rst), 
	      .input_dividen_tdata(dividen), 
	      .input_dividen_tvalid(dividen_tvalid), 
	      .input_dividen_tready(dividen_tready), 
	      .input_divisor_tdata(divisor), 
	      .input_divisor_tvalid(divisor_tvalid), 
	      .input_divisor_tready(divisor_tready), 
	      .output_tdata(output_tdata), 
	      .output_tvalid(output_tvalid), 
	      .output_tready(output_tready)
	      
	      );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;


      dividen = 128'd85070591730234607177427193140743463569;
      dividen_tvalid = 1;

      divisor = 64'd9223372036854775433;
      divisor_tvalid = 1;
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule