data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #20 rst_n = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:44: syntax error, unexpected \'@\'\n     @ (negedge clk_i) ;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:46: Unsupported: Ignoring delay on this delayed statement.\n         #2 spi_en = 0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20 master_spi_ncs = 1;\n  ^\n%Error: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:82: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("nvram_prog.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:83: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:84: Unsupported: Ignoring delay on this delayed statement.\n      #200 write_spi(32\'h9B8012AA, 4);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:85: Unsupported: Ignoring delay on this delayed statement.\n      #200;write_spi(32\'h0B20AA, 3);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #200;write_spi(8\'hAA, 1);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/415275006/NVRAM/FPGA/t_nvram_prog.v:87: Unsupported: Ignoring delay on this delayed statement.\n      #100 $finish;      \n      ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_nvram_prog;
   
   parameter tp=16;   
   reg           clk_i;
   reg 		 master_spi_ncs;
   wire 	 master_spi_miso;
   reg 		 master_spi_mosi;
   wire          nce, noe, nwe;

   wire [12:0]   addr;
   reg [7:0]     ram_data;
   reg [7:0]    in_data;
   reg           rst_n;
   reg           spi_en;
   
   initial begin
      rst_n = 0;
      spi_en = 0;
      master_spi_ncs = 1;      
      #20 rst_n = 1;
   end
   
   always
     if (spi_en)
       clk_i = #(tp/2) ~clk_i;
     else
       clk_i = #(tp/2) 0;

   task write_spi;
      input [31:0] spi_data;
      input [2:0]  spi_bytes;
      
      integer     spi_cnt;
      integer     bits;

      begin
         bits = spi_bytes * 8;         
	 master_spi_ncs = 0;
         spi_en = 1;
	 for(spi_cnt = 0; spi_cnt <bits-1; spi_cnt= spi_cnt+1) begin
            master_spi_mosi = spi_data[bits - 1 -spi_cnt];
	    @ (negedge clk_i) ;
	 end
         #2 spi_en = 0;
	 #20 master_spi_ncs = 1;
      end
   endtask

   always @ (posedge clk_i)
     if (~master_spi_ncs) begin
	in_data[7:1] <= in_data[6:0];
	in_data[0] <= master_spi_miso;
     end

   always @ (negedge nce)
     if (~noe & nwe)
       ram_data <= #2 addr[7:0];
   
   wire [7:0] data_prog;
   assign data_prog = ~noe ? ram_data : 8'hzz;

   always @ (posedge master_spi_ncs)
     $display("spi read data: 0x%02x\n", in_data[7:0]);
   

   nvram_prog prog0 (.rst_n(rst_n), 
                     .spi_clk_i(clk_i), 
                     .spi_ncs_i(master_spi_ncs), 
                     .spi_mosi(master_spi_mosi), 
                     .spi_miso(master_spi_miso),
                     .addr(addr),
                     .data(data_prog),
                     .nce(nce),
                     .noe(noe),
                     .nwe(nwe),
                     .led()
                     );
   initial begin
      $display("start simulation");
      $dumpfile("nvram_prog.vcd");
      $dumpvars;
      #200 write_spi(32'h9B8012AA, 4);
      #200;write_spi(32'h0B20AA, 3);
      #200;write_spi(8'hAA, 1);
      #100 $finish;      
   end
   
   initial begin

   end
endmodule
module t_nvram_prog;

   
   parameter tp=16;   
   reg           clk_i;
   reg 		 master_spi_ncs;
   wire 	 master_spi_miso;
   reg 		 master_spi_mosi;
   wire          nce, noe, nwe;

   wire [12:0]   addr;
   reg [7:0]     ram_data;
   reg [7:0]    in_data;
   reg           rst_n;
   reg           spi_en;
   
   initial begin
      rst_n = 0;
      spi_en = 0;
      master_spi_ncs = 1;      
      #20 rst_n = 1;
   end
   
   always
     if (spi_en)
       clk_i = #(tp/2) ~clk_i;
     else
       clk_i = #(tp/2) 0;

   task write_spi;
      input [31:0] spi_data;
      input [2:0]  spi_bytes;
      
      integer     spi_cnt;
      integer     bits;

      begin
         bits = spi_bytes * 8;         
	 master_spi_ncs = 0;
         spi_en = 1;
	 for(spi_cnt = 0; spi_cnt <bits-1; spi_cnt= spi_cnt+1) begin
            master_spi_mosi = spi_data[bits - 1 -spi_cnt];
	    @ (negedge clk_i) ;
	 end
         #2 spi_en = 0;
	 #20 master_spi_ncs = 1;
      end
   endtask

   always @ (posedge clk_i)
     if (~master_spi_ncs) begin
	in_data[7:1] <= in_data[6:0];
	in_data[0] <= master_spi_miso;
     end

   always @ (negedge nce)
     if (~noe & nwe)
       ram_data <= #2 addr[7:0];
   
   wire [7:0] data_prog;
   assign data_prog = ~noe ? ram_data : 8'hzz;

   always @ (posedge master_spi_ncs)
     $display("spi read data: 0x%02x\n", in_data[7:0]);
   

   nvram_prog prog0 (.rst_n(rst_n), 
                     .spi_clk_i(clk_i), 
                     .spi_ncs_i(master_spi_ncs), 
                     .spi_mosi(master_spi_mosi), 
                     .spi_miso(master_spi_miso),
                     .addr(addr),
                     .data(data_prog),
                     .nce(nce),
                     .noe(noe),
                     .nwe(nwe),
                     .led()
                     );
   initial begin
      $display("start simulation");
      $dumpfile("nvram_prog.vcd");
      $dumpvars;
      #200 write_spi(32'h9B8012AA, 4);
      #200;write_spi(32'h0B20AA, 3);
      #200;write_spi(8'hAA, 1);
      #100 $finish;      
   end
   
   initial begin

   end
endmodule