data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:1: Cannot find include file: A5Q1_gcd.v\n`include "A5Q1_gcd.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd,data/full_repos/permissive/450205124/A5Q1_gcd.v\n             data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd,data/full_repos/permissive/450205124/A5Q1_gcd.v.v\n             data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd,data/full_repos/permissive/450205124/A5Q1_gcd.v.sv\n             A5Q1_gcd.v\n             A5Q1_gcd.v.v\n             A5Q1_gcd.v.sv\n             obj_dir/A5Q1_gcd.v\n             obj_dir/A5Q1_gcd.v.v\n             obj_dir/A5Q1_gcd.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n always #(10) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #15;\n  ^\n%Error: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:15: Unsupported or unknown PLI call: $monitor\n  $monitor("GCD: %b[%d]", gcd, gcd);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #5000  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #5000  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment5/Q1-8bit-gcd/A5Q1_gcd_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #5000\n  ^\n%Error: Exiting due to 2 error(s), 45 warning(s)\n'
module gcd_tb ();
	reg reset_reg = 1;
	reg clk = 0;
	reg rst = 0;
	reg [7:0] a = 8'b00000011;
	reg [7:0] b = 8'b00000110;
	wire [7:0] gcd;
	always #(10) clk = ~clk;

	gcd GCD1(.clk(clk), .rst(rst), .a(a), .b(b), .c(gcd));

	initial begin
		#15;
		$monitor("GCD: %b[%d]", gcd, gcd);
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000;

		#25 rst = 1;
		#25 rst = 0;
		a = 27; b = 18;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256-1; b = $random%256+2;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = 2; b = 4;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000;
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000		

		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256-1;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000		

		#25 rst = 1;
		#25 rst = 0;
		a = 240; b = 120;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 220; b = 22;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 36; b = 48;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 4; b = 93;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = 46; b = 92;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 64; b = 128;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		$finish;
	end

	
endmodule
module gcd_tb ();

	reg reset_reg = 1;
	reg clk = 0;
	reg rst = 0;
	reg [7:0] a = 8'b00000011;
	reg [7:0] b = 8'b00000110;
	wire [7:0] gcd;
	always #(10) clk = ~clk;

	gcd GCD1(.clk(clk), .rst(rst), .a(a), .b(b), .c(gcd));

	initial begin
		#15;
		$monitor("GCD: %b[%d]", gcd, gcd);
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000;

		#25 rst = 1;
		#25 rst = 0;
		a = 27; b = 18;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256-1; b = $random%256+2;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = 2; b = 4;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000;
		
		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000		

		#25 rst = 1;
		#25 rst = 0;
		a = $random%256; b = $random%256-1;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000		

		#25 rst = 1;
		#25 rst = 0;
		a = 240; b = 120;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 220; b = 22;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 36; b = 48;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 4; b = 93;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000
		
		#25 rst = 1;
		#25 rst = 0;
		a = 46; b = 92;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		#25 rst = 1;
		#25 rst = 0;
		a = 64; b = 128;
		$display("a: %b[%d]  b: %b[%d]", a, a, b, b);
		#5000

		$finish;
	end

	
endmodule