data/full_repos/permissive/497819211/01/Mux16_tb.v
1: b'%Error: data/full_repos/permissive/497819211/01/Mux16_tb.v:1: Cannot find include file: Mux16.v\n`include "Mux16.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux16.v\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux16.v.v\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux16.v.sv\n             Mux16.v\n             Mux16.v.v\n             Mux16.v.sv\n             obj_dir/Mux16.v\n             obj_dir/Mux16.v.v\n             obj_dir/Mux16.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/497819211/01/Mux16_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #1 $fwrite(file, "|%16b|%16b|%1b|%16b|\\n", a,b,sel,out);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/497819211/01/Mux16_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Mux16_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/01/Mux16_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Mux16_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Mux16_tb();

	integer file;

	reg[15:0] a = 16'b0000000000000000;
	reg[15:0] b = 16'b0000000000000000;
	reg sel = 0;
	wire[15:0] out;
	
	Mux16 MUX16(
		.a(a),
		.b(b),
		.sel(sel),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%16b|%16b|%1b|%16b|\n", a,b,sel,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Mux16_tb.vcd");
  		$dumpvars(0, Mux16_tb);
		file = $fopen("Mux16.out","w");
    	$fwrite(file, "|a|b|sel|out|\n");
		
		display();
  		
		sel = 1;
		display();

        a=16'b0000000000000000;
        b=16'b0001001000110100;
		sel=0;
		display();
		
		sel = 1;
		display();

        a=16'b1001100001110110;
        b=16'b0000000000000000;
		sel=0;
		display();

		sel=1;
		display();

		a=16'b1010101010101010;
        b=16'b0101010101010101;
		sel=0;
		display();

		sel=1;
		display();
		$finish();	
	end

endmodule
module Mux16_tb();


	integer file;

	reg[15:0] a = 16'b0000000000000000;
	reg[15:0] b = 16'b0000000000000000;
	reg sel = 0;
	wire[15:0] out;
	
	Mux16 MUX16(
		.a(a),
		.b(b),
		.sel(sel),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%16b|%16b|%1b|%16b|\n", a,b,sel,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Mux16_tb.vcd");
  		$dumpvars(0, Mux16_tb);
		file = $fopen("Mux16.out","w");
    	$fwrite(file, "|a|b|sel|out|\n");
		
		display();
  		
		sel = 1;
		display();

        a=16'b0000000000000000;
        b=16'b0001001000110100;
		sel=0;
		display();
		
		sel = 1;
		display();

        a=16'b1001100001110110;
        b=16'b0000000000000000;
		sel=0;
		display();

		sel=1;
		display();

		a=16'b1010101010101010;
        b=16'b0101010101010101;
		sel=0;
		display();

		sel=1;
		display();
		$finish();	
	end

endmodule