data/full_repos/permissive/506268796/M.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/506268796/M.v:37: Multiple top level modules\n                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                              : ... Top module \'spiclkgen\'\nmodule spiclkgen(input clk\n       ^~~~~~~~~\n                                                              : ... Top module \'linespitransmitter\'\nmodule linespitransmitter(input clk\n       ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/506268796/M.v:114: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel\' generates 33 bits.\n                                                            : ... In instance linespitransmitter\n                    pixel_reg <= pixel;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/506268796/M.v:128: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel\' generates 33 bits.\n                                                            : ... In instance linespitransmitter\n                        pixel_reg <= pixel;                        \n                                  ^~\n%Error: Exiting due to 3 warning(s)\n'
module linespitransmitter(input clk
    , input rst
    , input [ADD_WIDTH:0] pixel_count
    , input [32:0] pixel
    , output [ADD_WIDTH - 1:0] address
    , output out
    , output done);
    
    parameter ADD_WIDTH = 8;
    
    localparam RESET = 4'b1xxx
    , FRAME_OPENING = 4'b0100
    , DATA_SENDING = 4'b0110
    , FRAME_CLOSE = 4'b0101
    , SESSION_DONE = 4'b0111;
    
    reg metada_sent;
    reg data_sent;
    
    reg [31:0] pixel_reg;
    reg [31:0] outgoing_pixel_reg;
    reg [4:0] bits_sent;
    reg pixel_ack;
    reg pixel_need_ack;
    reg done_reg;
    
    reg [ADD_WIDTH:0] address_reg;
    reg [ADD_WIDTH:0] sent_cnt;
    
    wire [3:0] state;
    assign state = {rst, bits_sent == 30, metada_sent, data_sent};
    assign address = address_reg[ADD_WIDTH - 1:0];
    assign out = outgoing_pixel_reg[31];
    assign done = done_reg;
    
    always @(posedge clk) begin
        
    end
    
    always @(posedge clk) begin

		if (~rst) begin
            bits_sent <= bits_sent + 1;
            if (bits_sent == 29) begin
                pixel_ack <= 1;
                sent_cnt <= sent_cnt + 1;
                if (~data_sent) begin
                    address_reg <= address_reg + 1;
                end
            end        
            if (pixel_need_ack) begin
                outgoing_pixel_reg <= pixel_reg;
                pixel_need_ack <= 0;
            end else begin
                outgoing_pixel_reg <= {outgoing_pixel_reg[30:0], outgoing_pixel_reg[31]};
                
            end            
        
        end
    
        casex (state)
            RESET: begin
                pixel_reg <= 0;
                outgoing_pixel_reg <= 0;
                pixel_ack <= 0;
                address_reg <= 0;
                sent_cnt <= 0;
                metada_sent <= 0;
                data_sent <= 0;
                bits_sent <= 0;
                pixel_need_ack <= 1;
                done_reg <= 0;
            end
            FRAME_OPENING: begin                
                if (pixel_ack) begin
                    sent_cnt <= 0;
                    metada_sent <= 1;
                    pixel_reg <= pixel;
                    pixel_need_ack <= 1;
                    pixel_ack <= 0;
                end
            end
            DATA_SENDING: begin                
                if (pixel_ack) begin                                        
                    pixel_need_ack <= 1;
                    pixel_ack <= 0;
                    if (sent_cnt == pixel_count) begin
                        metada_sent <= 0;
                        data_sent <= 1;
                        pixel_reg <= 32'hFFFFFFFF;
                    end else begin
                        pixel_reg <= pixel;                        
                    end
                end
                if (sent_cnt == pixel_count) begin
                    metada_sent <= 0;
                    data_sent <= 1;
                end
                pixel_ack <= 0;
            end
            FRAME_CLOSE: begin                
                if (pixel_ack) begin
                    metada_sent <= 1;
						  done_reg <= 1;
                end
            end
        endcase
    end
    

endmodule
module linespitransmitter(input clk
    , input rst
    , input [ADD_WIDTH:0] pixel_count
    , input [32:0] pixel
    , output [ADD_WIDTH - 1:0] address
    , output out
    , output done);

    
    parameter ADD_WIDTH = 8;
    
    localparam RESET = 4'b1xxx
    , FRAME_OPENING = 4'b0100
    , DATA_SENDING = 4'b0110
    , FRAME_CLOSE = 4'b0101
    , SESSION_DONE = 4'b0111;
    
    reg metada_sent;
    reg data_sent;
    
    reg [31:0] pixel_reg;
    reg [31:0] outgoing_pixel_reg;
    reg [4:0] bits_sent;
    reg pixel_ack;
    reg pixel_need_ack;
    reg done_reg;
    
    reg [ADD_WIDTH:0] address_reg;
    reg [ADD_WIDTH:0] sent_cnt;
    
    wire [3:0] state;
    assign state = {rst, bits_sent == 30, metada_sent, data_sent};
    assign address = address_reg[ADD_WIDTH - 1:0];
    assign out = outgoing_pixel_reg[31];
    assign done = done_reg;
    
    always @(posedge clk) begin
        
    end
    
    always @(posedge clk) begin

		if (~rst) begin
            bits_sent <= bits_sent + 1;
            if (bits_sent == 29) begin
                pixel_ack <= 1;
                sent_cnt <= sent_cnt + 1;
                if (~data_sent) begin
                    address_reg <= address_reg + 1;
                end
            end        
            if (pixel_need_ack) begin
                outgoing_pixel_reg <= pixel_reg;
                pixel_need_ack <= 0;
            end else begin
                outgoing_pixel_reg <= {outgoing_pixel_reg[30:0], outgoing_pixel_reg[31]};
                
            end            
        
        end
    
        casex (state)
            RESET: begin
                pixel_reg <= 0;
                outgoing_pixel_reg <= 0;
                pixel_ack <= 0;
                address_reg <= 0;
                sent_cnt <= 0;
                metada_sent <= 0;
                data_sent <= 0;
                bits_sent <= 0;
                pixel_need_ack <= 1;
                done_reg <= 0;
            end
            FRAME_OPENING: begin                
                if (pixel_ack) begin
                    sent_cnt <= 0;
                    metada_sent <= 1;
                    pixel_reg <= pixel;
                    pixel_need_ack <= 1;
                    pixel_ack <= 0;
                end
            end
            DATA_SENDING: begin                
                if (pixel_ack) begin                                        
                    pixel_need_ack <= 1;
                    pixel_ack <= 0;
                    if (sent_cnt == pixel_count) begin
                        metada_sent <= 0;
                        data_sent <= 1;
                        pixel_reg <= 32'hFFFFFFFF;
                    end else begin
                        pixel_reg <= pixel;                        
                    end
                end
                if (sent_cnt == pixel_count) begin
                    metada_sent <= 0;
                    data_sent <= 1;
                end
                pixel_ack <= 0;
            end
            FRAME_CLOSE: begin                
                if (pixel_ack) begin
                    metada_sent <= 1;
						  done_reg <= 1;
                end
            end
        endcase
    end
    

endmodule