data/full_repos/permissive/484316383/rtl/common/unit186.v
1: b"%Error: data/full_repos/permissive/484316383/rtl/common/unit186.v:87: Cannot find file containing module: 'Next186_CPU'\n Next186_CPU cpu \n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/Next186_CPU\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/Next186_CPU.v\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/Next186_CPU.sv\n             Next186_CPU\n             Next186_CPU.v\n             Next186_CPU.sv\n             obj_dir/Next186_CPU\n             obj_dir/Next186_CPU.v\n             obj_dir/Next186_CPU.sv\n%Error: data/full_repos/permissive/484316383/rtl/common/unit186.v:113: Cannot find file containing module: 'BIU186_32bSync_2T_DelayRead'\n BIU186_32bSync_2T_DelayRead BIU \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module unit186(
		input [15:0]INPORT,
		input [31:0]DIN,
		output [15:0]CPU_DOUT,
		output [31:0]DOUT,
		output [20:0]ADDR,
		output [3:0]WMASK,
		output [15:0]PORT_ADDR,
		
		input CLK,
		input CE,
		output CPU_CE,
		output CE_186,
		input INTR,
		input NMI,
		input RST,		
		output INTA,
		output LOCK,
		output HALT,
		output MREQ,
		output IORQ,
		output WR,
		output WORD,
		input FASTIO
		
    );

	wire [15:0] CPU_DIN;
	wire [15:0]CPU_WDATA;
	wire [20:0] CPU_IADDR;
	wire [20:0] CPU_ADDR;
	wire [47:0] CPU_INSTR;
	wire CPU_MREQ;
	wire IFETCH;
	wire FLUSH;
	wire [2:0]ISIZE;
	
	assign ADDR[1:0] = CPU_ADDR[1:0];
	assign CPU_CE = CE_186 & CE;


	Next186_CPU cpu 
	(
		 .ADDR(CPU_ADDR), 
		 .PORT_ADDR(PORT_ADDR),
		 .DIN(IORQ | INTA ? INPORT : CPU_DIN), 
		 .DOUT(CPU_WDATA),
		 .POUT(CPU_DOUT),
		 .CLK(CLK), 
		 .CE(CPU_CE), 
		 .INTR(INTR), 
		 .NMI(NMI), 
		 .RST(RST),		 
		 .MREQ(CPU_MREQ), 
		 .IORQ(IORQ), 
		 .INTA(INTA), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .LOCK(LOCK), 
		 .IADDR(CPU_IADDR), 
		 .INSTR(CPU_INSTR), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .ISIZE(ISIZE), 
		 .HALT(HALT)
   );	 

	BIU186_32bSync_2T_DelayRead BIU 
	(
		 .CLK(CLK), 
		 .INSTR(CPU_INSTR), 
		 .ISIZE(ISIZE), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .MREQ(CPU_MREQ), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .ADDR(CPU_ADDR), 
		 .IADDR(CPU_IADDR), 
		 .CE186(CE_186), 
		 .RAM_DIN(DIN), 
		 .RAM_DOUT(DOUT),
		 .RAM_ADDR(ADDR[20:2]), 
		 .RAM_MREQ(MREQ), 
		 .RAM_WMASK(WMASK), 
		 .DOUT(CPU_DIN), 
		 .DIN(CPU_WDATA), 
		 .CE(CE),
		 .WSEL({~CPU_ADDR[0], CPU_ADDR[0]}),
		 .IORQ(IORQ),
		 .FASTIO(FASTIO)
	);
		 
endmodule
module unit186(
		input [15:0]INPORT,
		input [31:0]DIN,
		output [15:0]CPU_DOUT,
		output [31:0]DOUT,
		output [20:0]ADDR,
		output [3:0]WMASK,
		output [15:0]PORT_ADDR,
		
		input CLK,
		input CE,
		output CPU_CE,
		output CE_186,
		input INTR,
		input NMI,
		input RST,		
		output INTA,
		output LOCK,
		output HALT,
		output MREQ,
		output IORQ,
		output WR,
		output WORD,
		input FASTIO
		
    );


	wire [15:0] CPU_DIN;
	wire [15:0]CPU_WDATA;
	wire [20:0] CPU_IADDR;
	wire [20:0] CPU_ADDR;
	wire [47:0] CPU_INSTR;
	wire CPU_MREQ;
	wire IFETCH;
	wire FLUSH;
	wire [2:0]ISIZE;
	
	assign ADDR[1:0] = CPU_ADDR[1:0];
	assign CPU_CE = CE_186 & CE;


	Next186_CPU cpu 
	(
		 .ADDR(CPU_ADDR), 
		 .PORT_ADDR(PORT_ADDR),
		 .DIN(IORQ | INTA ? INPORT : CPU_DIN), 
		 .DOUT(CPU_WDATA),
		 .POUT(CPU_DOUT),
		 .CLK(CLK), 
		 .CE(CPU_CE), 
		 .INTR(INTR), 
		 .NMI(NMI), 
		 .RST(RST),		 
		 .MREQ(CPU_MREQ), 
		 .IORQ(IORQ), 
		 .INTA(INTA), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .LOCK(LOCK), 
		 .IADDR(CPU_IADDR), 
		 .INSTR(CPU_INSTR), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .ISIZE(ISIZE), 
		 .HALT(HALT)
   );	 

	BIU186_32bSync_2T_DelayRead BIU 
	(
		 .CLK(CLK), 
		 .INSTR(CPU_INSTR), 
		 .ISIZE(ISIZE), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .MREQ(CPU_MREQ), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .ADDR(CPU_ADDR), 
		 .IADDR(CPU_IADDR), 
		 .CE186(CE_186), 
		 .RAM_DIN(DIN), 
		 .RAM_DOUT(DOUT),
		 .RAM_ADDR(ADDR[20:2]), 
		 .RAM_MREQ(MREQ), 
		 .RAM_WMASK(WMASK), 
		 .DOUT(CPU_DIN), 
		 .DIN(CPU_WDATA), 
		 .CE(CE),
		 .WSEL({~CPU_ADDR[0], CPU_ADDR[0]}),
		 .IORQ(IORQ),
		 .FASTIO(FASTIO)
	);
		 
endmodule