data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/ControlUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/ControlUnit.v:475: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                              : ... In instance ControlUnit\n            pcSel = 1\'b1;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/ControlUnit.v:478: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                              : ... In instance ControlUnit\n            pcSel = 1\'b0;\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module ControlUnit (
    input [6:0] funct7,
    input [4:0] rs2, rs1,
    input [2:0] funct3,
    input [6:0] opcode,
    input eq, lt,
    input [4:0] erd, mrd, rd,
    input ewreg, mwreg,
    input em2reg, mm2reg,
    input [2:0] ebType,
    input eisJal,

    output reg aSel,
    output reg bSel,
    output reg [3:0] aluc,
    output reg [1:0] rSel,
    output reg wmem, m2reg, wreg,
    output reg [2:0] immType,
    output [2:0] bType,
    output reg isJal, signedComp,
    output reg [1:0] qaSel, qbSel,
    output reg [1:0] pcSel,
    output reg pcStall, ifidStall, instNop
);


    reg isBranch;
    assign bType = {isBranch, funct3[2], funct3[0]};


    reg rs1Usage, rs2Usage;


    initial begin
        wmem = 0;
        wreg = 0;
        isBranch = 0;
        pcSel = 0;
        pcStall = 0;
        ifidStall = 0;
        instNop = 0;
    end

    always @(*) begin

        case (opcode) 
            7'b0110011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        aluc = funct7[5] ? 4'h1 : 4'h0;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b111: begin
                        aluc = 4'h2;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b110: begin
                        aluc = 4'h3;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        aluc = 4'h4;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        aluc = 4'h5;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'h7 : 4'h6;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b010: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b1;
                    end
                    3'b011: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0111011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        aluc = funct7[5] ? 4'h9 : 4'h8;
                    end
                    3'b001: begin
                        aluc = 4'hD;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'hF : 4'hE;
                    end
                endcase
            end
            7'b0010011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
                case (funct3)
                    3'b000: begin
                        aluc = 4'h0;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b111: begin
                        aluc = 4'h2;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b110: begin
                        aluc = 4'h3;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        aluc = 4'h4;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        aluc = 4'h5;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'h7 : 4'h6;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b010: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b1;
                    end
                    3'b011: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0011011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h1;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
                case (funct3)
                    3'b000: begin
                        aluc = 4'h8;
                    end
                    3'b001: begin
                        aluc = 4'hD;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'hF : 4'hE;
                    end
                endcase
            end
            7'b1100011: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'h2;
                isBranch = 1'b1;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        signedComp = 1'b1;
                    end
                    3'b101: begin
                        signedComp = 1'b1;
                    end
                    3'b110: begin
                        signedComp = 1'b0;
                    end
                    3'b111: begin
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0000011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b1;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
            end
            7'b0100011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b1;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'h1;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
            end
            7'b0001111: begin
                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1110011: begin
                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b0110111: begin
                aSel = 1'bx;
                bSel = 1'b1;
                aluc = 4'hB;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h3;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b0010111: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h3;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1101111: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h2;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h4;
                isBranch = 1'b0;
                isJal = 1'b1;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1100111: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h2;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'b1;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
            end
            default: begin



                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
        endcase


        if (ewreg && (erd != 5'h0) && (erd == rs1) && ~em2reg)
            qaSel = 2'h1;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs1) & ~mm2reg)
            qaSel = 2'h2;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs1) & mm2reg)
            qaSel = 2'h3;
        else
            qaSel = 2'h0;
    
        if (ewreg & (erd != 5'h0) & (erd == rs2) & ~em2reg)
            qbSel = 2'h1;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs2) & ~mm2reg)
            qbSel = 2'h2;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs2) & mm2reg)
            qbSel = 2'h3;
        else
            qbSel = 2'h0;
    

        if (ewreg & em2reg & (erd != 5'h0) & (rd != 5'h0) &
            ((rs1Usage & (rd == rs1)) | (rs2Usage & (rd == rs2))))
        begin
            wreg = 1'b0;
            wmem = 1'b0;
            pcStall = 1'b1;
            ifidStall = 1'b1;
        end else begin
            pcStall = 1'b0;
            ifidStall = 1'b0;
        end
        

        if (
            (ebType == 3'h4 & eq == 1'b1) |
            (ebType == 3'h5 & eq == 1'b0) |
            (ebType == 3'h6 & lt == 1'b1) |
            (ebType == 3'h7 & lt == 1'b0) |
            (eisJal)
        )
        begin
            wreg = 1'b0;
            wmem = 1'b0;
            pcSel = 1'b1;
            instNop = 1'b1;
        end else begin
            pcSel = 1'b0;
            instNop = 1'b0;
        end
        
    end


endmodule
module ControlUnit (
    input [6:0] funct7,
    input [4:0] rs2, rs1,
    input [2:0] funct3,
    input [6:0] opcode,
    input eq, lt,
    input [4:0] erd, mrd, rd,
    input ewreg, mwreg,
    input em2reg, mm2reg,
    input [2:0] ebType,
    input eisJal,

    output reg aSel,
    output reg bSel,
    output reg [3:0] aluc,
    output reg [1:0] rSel,
    output reg wmem, m2reg, wreg,
    output reg [2:0] immType,
    output [2:0] bType,
    output reg isJal, signedComp,
    output reg [1:0] qaSel, qbSel,
    output reg [1:0] pcSel,
    output reg pcStall, ifidStall, instNop
);



    reg isBranch;
    assign bType = {isBranch, funct3[2], funct3[0]};


    reg rs1Usage, rs2Usage;


    initial begin
        wmem = 0;
        wreg = 0;
        isBranch = 0;
        pcSel = 0;
        pcStall = 0;
        ifidStall = 0;
        instNop = 0;
    end

    always @(*) begin

        case (opcode) 
            7'b0110011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        aluc = funct7[5] ? 4'h1 : 4'h0;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b111: begin
                        aluc = 4'h2;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b110: begin
                        aluc = 4'h3;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        aluc = 4'h4;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        aluc = 4'h5;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'h7 : 4'h6;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b010: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b1;
                    end
                    3'b011: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0111011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        aluc = funct7[5] ? 4'h9 : 4'h8;
                    end
                    3'b001: begin
                        aluc = 4'hD;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'hF : 4'hE;
                    end
                endcase
            end
            7'b0010011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
                case (funct3)
                    3'b000: begin
                        aluc = 4'h0;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b111: begin
                        aluc = 4'h2;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b110: begin
                        aluc = 4'h3;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        aluc = 4'h4;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        aluc = 4'h5;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'h7 : 4'h6;
                        rSel = 2'h0;
                        signedComp = 1'bx;
                    end
                    3'b010: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b1;
                    end
                    3'b011: begin
                        aluc = 4'hx;
                        rSel = 2'h1;
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0011011: begin
                aSel = 1'b0;
                bSel = 1'b0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h1;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
                case (funct3)
                    3'b000: begin
                        aluc = 4'h8;
                    end
                    3'b001: begin
                        aluc = 4'hD;
                    end
                    3'b101: begin
                        aluc = funct7[5] ? 4'hF : 4'hE;
                    end
                endcase
            end
            7'b1100011: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'h2;
                isBranch = 1'b1;
                isJal = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
                case (funct3)
                    3'b000: begin
                        signedComp = 1'bx;
                    end
                    3'b001: begin
                        signedComp = 1'bx;
                    end
                    3'b100: begin
                        signedComp = 1'b1;
                    end
                    3'b101: begin
                        signedComp = 1'b1;
                    end
                    3'b110: begin
                        signedComp = 1'b0;
                    end
                    3'b111: begin
                        signedComp = 1'b0;
                    end
                endcase
            end
            7'b0000011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b1;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
            end
            7'b0100011: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b1;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'h1;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b1;
            end
            7'b0001111: begin
                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1110011: begin
                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b0110111: begin
                aSel = 1'bx;
                bSel = 1'b1;
                aluc = 4'hB;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h3;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b0010111: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h0;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h3;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1101111: begin
                aSel = 1'b1;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h2;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h4;
                isBranch = 1'b0;
                isJal = 1'b1;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
            7'b1100111: begin
                aSel = 1'b0;
                bSel = 1'b1;
                aluc = 4'h0;
                rSel = 2'h2;
                wmem = 1'b0;
                m2reg = 1'b0;
                wreg = 1'b1;
                immType = 3'h0;
                isBranch = 1'b0;
                isJal = 1'b1;
                signedComp = 1'bx;
                rs1Usage = 1'b1;
                rs2Usage = 1'b0;
            end
            default: begin



                aSel = 1'bx;
                bSel = 1'bx;
                aluc = 4'hx;
                rSel = 2'hx;
                wmem = 1'b0;
                m2reg = 1'bx;
                wreg = 1'b0;
                immType = 3'hx;
                isBranch = 1'b0;
                isJal = 1'bx;
                signedComp = 1'bx;
                rs1Usage = 1'b0;
                rs2Usage = 1'b0;
            end
        endcase


        if (ewreg && (erd != 5'h0) && (erd == rs1) && ~em2reg)
            qaSel = 2'h1;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs1) & ~mm2reg)
            qaSel = 2'h2;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs1) & mm2reg)
            qaSel = 2'h3;
        else
            qaSel = 2'h0;
    
        if (ewreg & (erd != 5'h0) & (erd == rs2) & ~em2reg)
            qbSel = 2'h1;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs2) & ~mm2reg)
            qbSel = 2'h2;
        else if (mwreg & (mrd != 5'h0) & (mrd == rs2) & mm2reg)
            qbSel = 2'h3;
        else
            qbSel = 2'h0;
    

        if (ewreg & em2reg & (erd != 5'h0) & (rd != 5'h0) &
            ((rs1Usage & (rd == rs1)) | (rs2Usage & (rd == rs2))))
        begin
            wreg = 1'b0;
            wmem = 1'b0;
            pcStall = 1'b1;
            ifidStall = 1'b1;
        end else begin
            pcStall = 1'b0;
            ifidStall = 1'b0;
        end
        

        if (
            (ebType == 3'h4 & eq == 1'b1) |
            (ebType == 3'h5 & eq == 1'b0) |
            (ebType == 3'h6 & lt == 1'b1) |
            (ebType == 3'h7 & lt == 1'b0) |
            (eisJal)
        )
        begin
            wreg = 1'b0;
            wmem = 1'b0;
            pcSel = 1'b1;
            instNop = 1'b1;
        end else begin
            pcSel = 1'b0;
            instNop = 1'b0;
        end
        
    end


endmodule