data/full_repos/permissive/522095295/top.v
1: b'%Error: data/full_repos/permissive/522095295/top.v:8: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/522095295/top.v:9: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,top);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/522095295/top.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #10 reset = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top ();

   wire clk;
   reg reset = 1;
   
   initial begin

      $dumpfile("wave.vcd");
      $dumpvars(0,top);


      #10 reset = 0;
   end
   

   clock clock0 (
	   .clk_o (clk));
   

   cpu cpu0 (
	   .clk (clk),
	   .reset (reset));
endmodule
module top ();


   wire clk;
   reg reset = 1;
   
   initial begin

      $dumpfile("wave.vcd");
      $dumpvars(0,top);


      #10 reset = 0;
   end
   

   clock clock0 (
	   .clk_o (clk));
   

   cpu cpu0 (
	   .clk (clk),
	   .reset (reset));
endmodule