data/full_repos/permissive/439731184/d_flip_flop.v
1: b'%Error: data/full_repos/permissive/439731184/d_flip_flop.v:27: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%b\\t%b\\t%b\\t%b\\t%b", \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/d_flip_flop.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #3 d = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/d_flip_flop.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #3 d = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/d_flip_flop.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/d_flip_flop.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n       ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff_from_nand_tb();

reg clk, d;
wire q, q_bar;

dff_from_nand D (q, q_bar, clk, d);

initial begin
    $display("clk\td\tx\ty\tq\tq_bar");
    $monitor("%h\t%b\t%b\t%b\t%b\t%b", 
             clk, d, D.x, D.y, q, q_bar);
    clk = 0;
    d = 0;
    #3 d = 1;
    #3 d = 0;
    #10 $finish;
end

always #2 clk = ~clk;

endmodule
module dff_from_nand_tb();


reg clk, d;
wire q, q_bar;

dff_from_nand D (q, q_bar, clk, d);

initial begin
    $display("clk\td\tx\ty\tq\tq_bar");
    $monitor("%h\t%b\t%b\t%b\t%b\t%b", 
             clk, d, D.x, D.y, q, q_bar);
    clk = 0;
    d = 0;
    #3 d = 1;
    #3 d = 0;
    #10 $finish;
end

always #2 clk = ~clk;

endmodule