data/full_repos/permissive/503578084/single_cycle/alu_adder.v
data/verilator_xmls/0c58d659-c26c-483a-94f8-22dd4a910c60.xml
module alu_adder(
    input   [31:0]  A,
    input   [31:0]  B,
    output  reg [31:0]  C,
    output  reg zero
    );
    
always @ (*) begin
    C=A+B;
    if(C==32'b0) zero=1'b1;
    else zero=1'b0;
end
    
endmodule
module alu_adder(
    input   [31:0]  A,
    input   [31:0]  B,
    output  reg [31:0]  C,
    output  reg zero
    );

    
always @ (*) begin
    C=A+B;
    if(C==32'b0) zero=1'b1;
    else zero=1'b0;
end
    
endmodule