data/full_repos/permissive/493019833/test/testcase/firrtl/AdderTests/sbt/AdderTests.v
data/verilator_xmls/d46448cb-3bc1-404b-a965-ec6988a76370.xml
module Adder(
  input  [9:0] io_in0,
  input  [9:0] io_in1,
  output [9:0] io_out
);
  assign io_out = io_in0 + io_in1;
endmodule
module Adder(
  input  [9:0] io_in0,
  input  [9:0] io_in1,
  output [9:0] io_out
);

  assign io_out = io_in0 + io_in1;
endmodule