data/full_repos/permissive/421450529/ID_module.v
1: b"%Error: data/full_repos/permissive/421450529/ID_module.v:52: Cannot find file containing module: 'Controller'\n  Controller Controller_D(.func(Instr[5:0]),.op(Instr[31:26]),.RegDst(RegDst),.Extop(Extop),.pc_sel1(pc_sel1),.pc_sel2(pc_sel2),.M(M));\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller.v\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller.sv\n             Controller\n             Controller.v\n             Controller.sv\n             obj_dir/Controller\n             obj_dir/Controller.v\n             obj_dir/Controller.sv\n%Error: data/full_repos/permissive/421450529/ID_module.v:53: Cannot find file containing module: 'EXT'\n    EXT EXT(Instr[15:0],Extop,after_ext);\n    ^~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:54: Cannot find file containing module: 'GRF'\n  GRF GRF(clk,reset,pc_w,RegWrite_W,Instr[25:21],Instr[20:16],Write_register_W,Write_data_W,RF_RD1,RF_RD2);\n  ^~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:55: Cannot find file containing module: 'CMP'\n  CMP CMP(RF_RD1_trans,RF_RD2_trans,equal,g_or_e,greater);\n  ^~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:56: Cannot find file containing module: 'PC_b'\n  PC_b PC_b(Instr,after_ext,PC4_D,equal,g_or_e,greater,pc_beq);\n  ^~~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:57: Cannot find file containing module: 'PC_jal'\n  PC_jal PC_jal(Instr,PC4_D,pc_jal);\n  ^~~~~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:58: Cannot find file containing module: 'mux4_32'\n  mux4_32 nextpc_2(.D1(pc_jal),.D2(pc_beq),.D3(RF_RD1_trans),.control(pc_sel2),.out(nextpc));\n  ^~~~~~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:59: Cannot find file containing module: 'mux4_32'\n  mux4_32 MFRSD(.D1(RF_RD1),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRSD),.out(RF_RD1_trans));\n  ^~~~~~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:60: Cannot find file containing module: 'mux4_32'\n  mux4_32 MFRTD(.D1(RF_RD2),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRTD),.out(RF_RD2_trans));\n  ^~~~~~~\n%Error: data/full_repos/permissive/421450529/ID_module.v:61: Cannot find file containing module: 'mux4_5'\n  mux4_5 Wreg_D(.D1(Instr[20:16]),.D2(Instr[15:11]),.D3(5'b11111),.control(RegDst),.out(write_register_D));\n  ^~~~~~\n%Error: Exiting due to 10 error(s)\n"
module ID_module(
    input Busy,
    input clk,
    input reset,
    input [31:0] Instr,
	 input RegWrite_W,
	 input[4:0] Write_register_W,
	 input[31:0] Write_data_W,
	 input[31:0] PC4_D,
	 input[31:0] PC4_W,
	 input[1:0] ForwardRSD, 
	 input[1:0] ForwardRTD,
	 input[31:0] ALUout_M,
    output[31:0] RF_RD1_trans,
    output[31:0] RF_RD2_trans,
    output[31:0] after_ext,
	 output[31:0] nextpc,
	 output pc_sel1,
	 output[4:0] write_register_D,
	 
	 output Start,
	 output stall_m
    );

    wire[31:0] pc_beq,pc_jal,RF_RD1,RF_RD2,pc_w;
	 wire[1:0] Extop,RegDst,pc_sel2;
	 wire equal,g_or_e,greater,M;
	 assign pc_w=PC4_W-4;
	 assign Start=(M==1&&Busy==0)?1'b1:1'b0;
	 assign stall_m=(M==1&&Busy==1)?1'b1:1'b0;
	 
	 Controller Controller_D(.func(Instr[5:0]),.op(Instr[31:26]),.RegDst(RegDst),.Extop(Extop),.pc_sel1(pc_sel1),.pc_sel2(pc_sel2),.M(M));
    EXT EXT(Instr[15:0],Extop,after_ext);
	 GRF GRF(clk,reset,pc_w,RegWrite_W,Instr[25:21],Instr[20:16],Write_register_W,Write_data_W,RF_RD1,RF_RD2);
	 CMP CMP(RF_RD1_trans,RF_RD2_trans,equal,g_or_e,greater);
	 PC_b PC_b(Instr,after_ext,PC4_D,equal,g_or_e,greater,pc_beq);
	 PC_jal PC_jal(Instr,PC4_D,pc_jal);
	 mux4_32 nextpc_2(.D1(pc_jal),.D2(pc_beq),.D3(RF_RD1_trans),.control(pc_sel2),.out(nextpc));
	 mux4_32 MFRSD(.D1(RF_RD1),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRSD),.out(RF_RD1_trans));
	 mux4_32 MFRTD(.D1(RF_RD2),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRTD),.out(RF_RD2_trans));
	 mux4_5 Wreg_D(.D1(Instr[20:16]),.D2(Instr[15:11]),.D3(5'b11111),.control(RegDst),.out(write_register_D));
	 endmodule
module ID_module(
    input Busy,
    input clk,
    input reset,
    input [31:0] Instr,
	 input RegWrite_W,
	 input[4:0] Write_register_W,
	 input[31:0] Write_data_W,
	 input[31:0] PC4_D,
	 input[31:0] PC4_W,
	 input[1:0] ForwardRSD, 
	 input[1:0] ForwardRTD,
	 input[31:0] ALUout_M,
    output[31:0] RF_RD1_trans,
    output[31:0] RF_RD2_trans,
    output[31:0] after_ext,
	 output[31:0] nextpc,
	 output pc_sel1,
	 output[4:0] write_register_D,
	 
	 output Start,
	 output stall_m
    );


    wire[31:0] pc_beq,pc_jal,RF_RD1,RF_RD2,pc_w;
	 wire[1:0] Extop,RegDst,pc_sel2;
	 wire equal,g_or_e,greater,M;
	 assign pc_w=PC4_W-4;
	 assign Start=(M==1&&Busy==0)?1'b1:1'b0;
	 assign stall_m=(M==1&&Busy==1)?1'b1:1'b0;
	 
	 Controller Controller_D(.func(Instr[5:0]),.op(Instr[31:26]),.RegDst(RegDst),.Extop(Extop),.pc_sel1(pc_sel1),.pc_sel2(pc_sel2),.M(M));
    EXT EXT(Instr[15:0],Extop,after_ext);
	 GRF GRF(clk,reset,pc_w,RegWrite_W,Instr[25:21],Instr[20:16],Write_register_W,Write_data_W,RF_RD1,RF_RD2);
	 CMP CMP(RF_RD1_trans,RF_RD2_trans,equal,g_or_e,greater);
	 PC_b PC_b(Instr,after_ext,PC4_D,equal,g_or_e,greater,pc_beq);
	 PC_jal PC_jal(Instr,PC4_D,pc_jal);
	 mux4_32 nextpc_2(.D1(pc_jal),.D2(pc_beq),.D3(RF_RD1_trans),.control(pc_sel2),.out(nextpc));
	 mux4_32 MFRSD(.D1(RF_RD1),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRSD),.out(RF_RD1_trans));
	 mux4_32 MFRTD(.D1(RF_RD2),.D2(ALUout_M),.D3(Write_data_W),.control(ForwardRTD),.out(RF_RD2_trans));
	 mux4_5 Wreg_D(.D1(Instr[20:16]),.D2(Instr[15:11]),.D3(5'b11111),.control(RegDst),.out(write_register_D));
	 endmodule