data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v
1: b'%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:11: Cannot find include file: pa_soc_param.v\n`include "pa_soc_param.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.sv\n             pa_soc_param.v\n             pa_soc_param.v.v\n             pa_soc_param.v.sv\n             obj_dir/pa_soc_param.v\n             obj_dir/pa_soc_param.v.v\n             obj_dir/pa_soc_param.v.sv\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:17: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n    input  wire [`ADDR_BUS_WIDTH-1:0]   inst_addr_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:18: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   inst_data_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:23: Define or directive not defined: \'`ROM_SIZE\'\nreg  [7:0]                              _rom[0:`ROM_SIZE*1024-1];\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:23: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg  [7:0]                              _rom[0:`ROM_SIZE*1024-1];\n                                                        ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:25: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\nwire [`ADDR_BUS_WIDTH-1:0]              index;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:27: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\nassign index[`ADDR_BUS_WIDTH-1:0] = {2\'b0, inst_addr_i[31:2]};\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:29: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _inst_data;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:33: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _inst_data[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:33: Define or directive not defined: \'`ZERO_WORD\'\n        _inst_data[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        _inst_data[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                                    ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:36: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _inst_data[`DATA_BUS_WIDTH-1:0] = {_rom[index*4+0], _rom[index*4+1], _rom[index*4+2], _rom[index*4+3]};\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:40: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign inst_data_o[`DATA_BUS_WIDTH-1:0] = _inst_data[`DATA_BUS_WIDTH-1:0];\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_itcm.v:40: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign inst_data_o[`DATA_BUS_WIDTH-1:0] = _inst_data[`DATA_BUS_WIDTH-1:0];\n                                                     ^~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module pa_soc_itcm (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    input  wire [`ADDR_BUS_WIDTH-1:0]   inst_addr_i,
    output wire [`DATA_BUS_WIDTH-1:0]   inst_data_o,

    output wire                         unalign_expt_o
);

reg  [7:0]                              _rom[0:`ROM_SIZE*1024-1];

wire [`ADDR_BUS_WIDTH-1:0]              index;

assign index[`ADDR_BUS_WIDTH-1:0] = {2'b0, inst_addr_i[31:2]};

reg  [`DATA_BUS_WIDTH-1:0]              _inst_data;

always @ (*) begin
    if (!rst_n_i) begin
        _inst_data[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _inst_data[`DATA_BUS_WIDTH-1:0] = {_rom[index*4+0], _rom[index*4+1], _rom[index*4+2], _rom[index*4+3]};
    end
end

assign inst_data_o[`DATA_BUS_WIDTH-1:0] = _inst_data[`DATA_BUS_WIDTH-1:0];

assign unalign_expt_o = (|inst_addr_i[1:0]);

endmodule
module pa_soc_itcm (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    input  wire [`ADDR_BUS_WIDTH-1:0]   inst_addr_i,
    output wire [`DATA_BUS_WIDTH-1:0]   inst_data_o,

    output wire                         unalign_expt_o
);


reg  [7:0]                              _rom[0:`ROM_SIZE*1024-1];

wire [`ADDR_BUS_WIDTH-1:0]              index;

assign index[`ADDR_BUS_WIDTH-1:0] = {2'b0, inst_addr_i[31:2]};

reg  [`DATA_BUS_WIDTH-1:0]              _inst_data;

always @ (*) begin
    if (!rst_n_i) begin
        _inst_data[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _inst_data[`DATA_BUS_WIDTH-1:0] = {_rom[index*4+0], _rom[index*4+1], _rom[index*4+2], _rom[index*4+3]};
    end
end

assign inst_data_o[`DATA_BUS_WIDTH-1:0] = _inst_data[`DATA_BUS_WIDTH-1:0];

assign unalign_expt_o = (|inst_addr_i[1:0]);

endmodule