data/full_repos/permissive/506186384/project-files/lab6/PC.v
data/verilator_xmls/ada626d7-ce4d-425e-962c-2113db115e93.xml
module PC(
    input [31:0] NextPC,
    input D_Bubble,
    input Clk,
    input reset,
    output [31:0] CurPC
    );
    reg [31:0] PCReg;
    
    
    always @ (posedge Clk)
        begin
            if(D_Bubble == 0) PCReg = NextPC;
        end
    assign CurPC = PCReg;
    
    always @ (posedge reset)
        begin
            PCReg = 0;
        end
endmodule
module PC(
    input [31:0] NextPC,
    input D_Bubble,
    input Clk,
    input reset,
    output [31:0] CurPC
    );

    reg [31:0] PCReg;
    
    
    always @ (posedge Clk)
        begin
            if(D_Bubble == 0) PCReg = NextPC;
        end
    assign CurPC = PCReg;
    
    always @ (posedge reset)
        begin
            PCReg = 0;
        end
endmodule