data/full_repos/permissive/505213911/tb/my_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505213911/tb/my_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/505213911/tb/my_tb.v:24: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505213911/tb/my_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505213911/tb/my_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505213911/tb/my_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505213911/tb/my_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_gp();

reg             clk;
reg             reset;
reg     [127:0] data_i;

wire    [127:0] data_o;
wire            busy;

grasspopper gr (
    .clk(clk),
    .reset(reset),
    .data_i(data_i),
    .data_o(data_o),
    .busy(busy)
);

always #5 clk = ~clk;

initial begin
    clk = 0;
    reset = 1;
    @(negedge clk);
    reset = 0;
    #5
    data_i <= 128'h1122334455667700ffeeddccbbaa9988;
    #10;
    data_i <= 128'h0;
    reset = 0;
    #5
    data_i <= 128'h0;
    #2000;
    
    $finish();
end
endmodule
module tb_gp();


reg             clk;
reg             reset;
reg     [127:0] data_i;

wire    [127:0] data_o;
wire            busy;

grasspopper gr (
    .clk(clk),
    .reset(reset),
    .data_i(data_i),
    .data_o(data_o),
    .busy(busy)
);

always #5 clk = ~clk;

initial begin
    clk = 0;
    reset = 1;
    @(negedge clk);
    reset = 0;
    #5
    data_i <= 128'h1122334455667700ffeeddccbbaa9988;
    #10;
    data_i <= 128'h0;
    reset = 0;
    #5
    data_i <= 128'h0;
    #2000;
    
    $finish();
end
endmodule