data/full_repos/permissive/434840709/lab5/code/press.v
data/verilator_xmls/6333bb26-f85a-4316-8434-960a86a5e916.xml
module press(
    input clk190hz,
    input press, 
    output signal
);

    reg[5:0] de;
    
    always @(posedge clk190hz)
    begin
        de[5] <= de[4];
        de[4] <= de[3];
        de[3] <= de[2];
        de[2] <= de[1]; 
        de[1] <= de[0];  
        de[0] <= press;
    end
    
    assign signal = de[0] & de[1] & de[2] & de[3] & de[4] & de[5];
endmodule
module press(
    input clk190hz,
    input press, 
    output signal
);


    reg[5:0] de;
    
    always @(posedge clk190hz)
    begin
        de[5] <= de[4];
        de[4] <= de[3];
        de[3] <= de[2];
        de[2] <= de[1]; 
        de[1] <= de[0];  
        de[0] <= press;
    end
    
    assign signal = de[0] & de[1] & de[2] & de[3] & de[4] & de[5];
endmodule