data/full_repos/permissive/449071180/tb_control_signal_mux.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_control_signal_mux.v:22: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_control_signal_mux.v:24: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_control_signal_mux.v:8: Cannot find file containing module: \'control_signal_mux\'\ncontrol_signal_mux port_map(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/control_signal_mux\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/control_signal_mux.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/control_signal_mux.sv\n             control_signal_mux\n             control_signal_mux.v\n             control_signal_mux.sv\n             obj_dir/control_signal_mux\n             obj_dir/control_signal_mux.v\n             obj_dir/control_signal_mux.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_control_signal_mux.v:21: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n                                                                               : ... In instance tb_control_signal_mux\nin_test = count;\n        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_control_signal_mux();
reg select_test;
reg [2:0] in_test;
wire [2:0] out_test;

integer count;

control_signal_mux port_map(
.select(select_test),
.in(in_test),
.out(out_test)
);

initial begin 
select_test = 0;
in_test = 3'b0;
end

always begin 
for(count = 0; count < 8; count = count + 1) begin
in_test = count;
#5;
select_test = 1;
#5;
select_test = 0;
end
end

endmodule
module tb_control_signal_mux();

reg select_test;
reg [2:0] in_test;
wire [2:0] out_test;

integer count;

control_signal_mux port_map(
.select(select_test),
.in(in_test),
.out(out_test)
);

initial begin 
select_test = 0;
in_test = 3'b0;
end

always begin 
for(count = 0; count < 8; count = count + 1) begin
in_test = count;
#5;
select_test = 1;
#5;
select_test = 0;
end
end

endmodule