data/full_repos/permissive/434840709/week12/7.v
data/verilator_xmls/0efc82ed-e9b7-4539-873e-3c297e3bf5fb.xml
module top_module (
    input clk,
    input d, 
    input ar,
    output reg q
);
    wire out1,out2;
    always @(posedge clk or posedge ar) begin
        if(ar == 1) begin
            q <= 0;
        end
        else if(!ar) begin
            q <= d;
        end
    end
endmodule
module top_module (
    input clk,
    input d, 
    input ar,
    output reg q
);

    wire out1,out2;
    always @(posedge clk or posedge ar) begin
        if(ar == 1) begin
            q <= 0;
        end
        else if(!ar) begin
            q <= d;
        end
    end
endmodule