data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10 s = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10 s = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10 s = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 s = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/pulse_tb.v:11: Cannot find file containing module: \'pulse_FSM\'\n pulse_FSM pulse(.s(s), .clk(clk), .rst(rst), .P(P), .L(L), .A(A), .B(B));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/pulse_FSM\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/pulse_FSM.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/pulse_FSM.sv\n             pulse_FSM\n             pulse_FSM.v\n             pulse_FSM.sv\n             obj_dir/pulse_FSM\n             obj_dir/pulse_FSM.v\n             obj_dir/pulse_FSM.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pulse_tb;
	reg s;
	reg rst;
	reg clk;

	wire P;
	wire L;
	wire A;
	wire B;

	pulse_FSM pulse(.s(s), .clk(clk), .rst(rst), .P(P), .L(L), .A(A), .B(B));

	initial
	begin
		s = 0;
		rst = 0;
		clk = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 rst = 1;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 1;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 1;
		repeat(8)
		#10 clk = ~clk;
		#10 s = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 $finish;
	end
endmodule
module pulse_tb;

	reg s;
	reg rst;
	reg clk;

	wire P;
	wire L;
	wire A;
	wire B;

	pulse_FSM pulse(.s(s), .clk(clk), .rst(rst), .P(P), .L(L), .A(A), .B(B));

	initial
	begin
		s = 0;
		rst = 0;
		clk = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 rst = 1;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 1;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 s = 1;
		repeat(8)
		#10 clk = ~clk;
		#10 s = 0;
		#10 clk = ~clk;
		#10 clk = ~clk;
		#10 $finish;
	end
endmodule