data/full_repos/permissive/527176783/Single/A_Single/ALU.v
1: b'%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:4: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:17: Define or directive not defined: \'`ALUAdd\'\n            `ALUAdd: out = a + b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:17: syntax error, unexpected \':\', expecting endcase\n            `ALUAdd: out = a + b;\n                   ^\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:18: Define or directive not defined: \'`ALUSub\'\n            `ALUSub: out = a - b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:19: Define or directive not defined: \'`ALUAnd\'\n            `ALUAnd: out = a & b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:20: Define or directive not defined: \'`ALUOr\'\n            `ALUOr: out = a | b;\n            ^~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:21: Define or directive not defined: \'`ALUCmpu\'\n            `ALUCmpu: out = (a < b) ? 1: 0; \n            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:22: Define or directive not defined: \'`ALUCmps\'\n            `ALUCmps: begin  \n            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:29: Define or directive not defined: \'`ALUSll\'\n            `ALUSll: out = b << a;\n            ^~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:29: End label \'out\' does not match begin label \'\'\n            `ALUSll: out = b << a;\n                     ^~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:29: syntax error, unexpected \'=\'\n            `ALUSll: out = b << a;\n                         ^\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:30: Define or directive not defined: \'`ALUXor\'\n            `ALUXor: out = a ^ b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:31: Define or directive not defined: \'`ALUSra\'\n            `ALUSra: out = b >>> a;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:32: Define or directive not defined: \'`ALUSrl\'\n            `ALUSrl: out = b >> a;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:33: Define or directive not defined: \'`ALUJoint\'\n            `ALUJoint: out = {b,16\'d0}; \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/ALU.v:34: Define or directive not defined: \'`ALUSubZero\'\n            `ALUSubZero: out = a - 32\'d0;\n            ^~~~~~~~~~~\n%Error: Cannot continue\n'
module ALU(
        input       [3:0]   Aluc,
        input       [31:0]  a,
        input       [31:0]  b,
        output  reg [31:0]  out,
        output  reg         zero,
        output  reg         sign
);

    always @(*) begin
        case (Aluc)
            `ALUAdd: out = a + b;
            `ALUSub: out = a - b;
            `ALUAnd: out = a & b;
            `ALUOr: out = a | b;
            `ALUCmpu: out = (a < b) ? 1: 0;
            `ALUCmps: begin
                if (a < b &&((a[31] == 0 && b[31]==0) ||
                    (a[31] == 1 && b[31]==1))) out = 1;
                else if (a[31] == 0 && b[31]==1) out = 0;
                else if (a[31] == 1 && b[31]==0) out = 1;
                else out = 0;
            end
            `ALUSll: out = b << a;
            `ALUXor: out = a ^ b;
            `ALUSra: out = b >>> a;
            `ALUSrl: out = b >> a;
            `ALUJoint: out = {b,16'd0};
            `ALUSubZero: out = a - 32'd0;

            default: out = a + b;
        endcase

        if (out == 0) zero = 1;
        else zero = 0;
        
        sign = out[31];
    end

    


endmodule
module ALU(
        input       [3:0]   Aluc,
        input       [31:0]  a,
        input       [31:0]  b,
        output  reg [31:0]  out,
        output  reg         zero,
        output  reg         sign
);


    always @(*) begin
        case (Aluc)
            `ALUAdd: out = a + b;
            `ALUSub: out = a - b;
            `ALUAnd: out = a & b;
            `ALUOr: out = a | b;
            `ALUCmpu: out = (a < b) ? 1: 0;
            `ALUCmps: begin
                if (a < b &&((a[31] == 0 && b[31]==0) ||
                    (a[31] == 1 && b[31]==1))) out = 1;
                else if (a[31] == 0 && b[31]==1) out = 0;
                else if (a[31] == 1 && b[31]==0) out = 1;
                else out = 0;
            end
            `ALUSll: out = b << a;
            `ALUXor: out = a ^ b;
            `ALUSra: out = b >>> a;
            `ALUSrl: out = b >> a;
            `ALUJoint: out = {b,16'd0};
            `ALUSubZero: out = a - 32'd0;

            default: out = a + b;
        endcase

        if (out == 0) zero = 1;
        else zero = 0;
        
        sign = out[31];
    end

    


endmodule