data/full_repos/permissive/412284801/d_ff/d_ff.v
data/verilator_xmls/29a12d09-6ff0-427a-922d-4fd09ab58fdf.xml
module d_ff(
    clk, d, q, qbar
);

input clk, d;
output reg q, qbar;

always @(posedge clk) begin
    if(d == 1)
        begin
            q <= 1;
            qbar <= 0;
        end
    else
        begin
            q <= 0;
            qbar <= 1;
        end
end

endmodule
module d_ff(
    clk, d, q, qbar
);


input clk, d;
output reg q, qbar;

always @(posedge clk) begin
    if(d == 1)
        begin
            q <= 1;
            qbar <= 0;
        end
    else
        begin
            q <= 0;
            qbar <= 1;
        end
end

endmodule