data/full_repos/permissive/492581806/dcache.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #1\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #0.9 hit=1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:47: Unsupported: Ignoring delay on this delayed statement.\n    # 0.9 hit=1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #1\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:97: Unsupported: Ignoring delay on this delayed statement.\n   #1\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:204: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/dcache.v:226: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dcache (clock,reset,C_WRITE,C_READ,C_Address,C_WRITEDATA,C_READDATA,busywait,mem_write,mem_read,mem_address,mem_writedata,mem_readdata,mem_busywait);

    input  clock, reset,C_WRITE,C_READ,mem_busywait;
    input [7:0] C_WRITEDATA,C_Address;
    input [31:0] mem_readdata;

    output reg mem_write,mem_read,busywait;
    output reg [5:0] mem_address;
    output reg [7:0] C_READDATA;
    output reg [31:0] mem_writedata;
   
   reg readaccess,writeaccess,dirtybit,validbit;
   reg [1:0] offset;
   reg [2:0] index,tag;
   reg [36:0] Cache_MEM [7:0];
   reg [31:0] BLOCK;
   reg hit;
  
   always@(BLOCK[7:0],BLOCK[15:8],BLOCK[23:16],BLOCK[31:24],offset)
   begin
   #1
   case(offset)
         2'b00 :C_READDATA=BLOCK[7:0]; 
         2'b01 :C_READDATA=BLOCK[15:8];
         2'b10 :C_READDATA=BLOCK[23:16];
         2'b11 :C_READDATA=BLOCK[31:24];

  endcase 
  end
    
   always @(C_Address[5],C_Address[6],C_Address[7],tag[0],tag[1],tag[2],validbit)
    begin
    if(tag[0]==C_Address[5] && tag[1]==C_Address[6] && tag[2]==C_Address[7] && validbit)
    #0.9 hit=1'b1;
    else
    # 0.9 hit=1'b0;
    end
    

	
  always @(C_WRITE,C_READ)
	begin

		busywait = ((C_READ || C_WRITE))? 1 : 0;
		readaccess = (C_READ && !C_WRITE)? 1 : 0;
		writeaccess = (!C_READ && C_WRITE)? 1 : 0;
	end

 always @(posedge clock)begin 
	
		if(readaccess == 1'b1 && hit == 1'b1)begin
			
			readaccess = 1'b0;
			busywait= 1'b0;
		end
		else if(writeaccess == 1'b1 && hit == 1'b1)begin
			busywait = 1'b0;
			
			#1
			case(offset)
			

				2'b00	:	Cache_MEM[index][7:0] = C_WRITEDATA;
				2'b01 	:	Cache_MEM[index][15:8] = C_WRITEDATA;
				2'b10 	:	Cache_MEM[index][23:16] = C_WRITEDATA;
				2'b11   :	Cache_MEM[index][31:24] = C_WRITEDATA;
		
			endcase
			Cache_MEM[index][35] = 1'b1;
                        Cache_MEM[index][36]=1'b1;
			writeaccess = 1'b0;
			
		 
		 end
	end
    
  


always @(*)begin
		

		if(readaccess == 1'b1 || writeaccess == 1'b1)
                begin
		
			#1
                        
			BLOCK =  Cache_MEM[C_Address[4:2]][31:0];
			tag =  Cache_MEM[ C_Address[4:2] ][34:32];
			dirtybit =  Cache_MEM[C_Address[4:2]][35];
			validbit = Cache_MEM[C_Address[4:2]][36];
			offset =  C_Address[1:0];
			index =  C_Address[4:2];
			
		end
		
	
	end





    parameter IDLE = 3'b000, MEM_READ = 3'b001,MEM_WRITE=3'b010,C_MEM_WRITE=3'b011;
    reg [2:0] state, next_state;


    always @(*)
    begin
        case (state)
            IDLE:
                if ((C_READ || C_WRITE) && !dirtybit && !hit)
                    next_state = MEM_READ;
                else if ((C_READ ||C_WRITE) && dirtybit && !hit)
                    next_state = MEM_WRITE;
                else
                    next_state = IDLE;
            
            MEM_READ:
                if (!mem_busywait)
                    next_state = C_MEM_WRITE;
                else    
                    next_state = MEM_READ;


           MEM_WRITE:
             if (!mem_busywait)
                    next_state = MEM_READ;
                else    
                    next_state = MEM_WRITE;
					
	  C_MEM_WRITE:
               if ((C_READ || C_WRITE) && dirtybit && !hit)
                  next_state =C_MEM_WRITE ;
               else 
                  next_state =IDLE ;
              

               
        endcase
    end


    always @(*)
    begin
        case(state)
            IDLE:
            begin
                mem_read = 0;
                mem_write = 0;
                mem_address = 6'dx;
                mem_writedata = 32'dx;
                
                
            end
         
            MEM_READ: 
            begin
                mem_read = 1;
                mem_write = 0;
                mem_address = {tag,index};
                mem_writedata = 32'dx;
                busywait=1;
                

               
               
            end


           		MEM_WRITE: 
            begin
                mem_read  = 1'd0;
                mem_write = 1'd1;
                mem_address ={tag,index};
                mem_writedata =BLOCK;
               busywait=1;
                
               
               
              
            end
			
			C_MEM_WRITE: 
            begin
                mem_read = 1'd0;
                mem_write = 1'd0;
                mem_address = 6'dx;
                mem_writedata = 32'dx;
                 busywait=1;

                
				#1
				Cache_MEM[index][31:0] = mem_readdata;
				Cache_MEM[index][34:32] = C_Address[7:5];
				Cache_MEM[index][35] = 1'd0;
				Cache_MEM[index][36] = 1'd1;
			
            end
            
            
            
            
        endcase
    end
    integer j;

    always @(posedge clock, reset)
    
    begin
        if(reset)
        begin
            state = IDLE;
            busywait=1'b0;
             #1;
             for( j=0;j<8;j=j+1)
            begin
            Cache_MEM[j] = 37'd0;
            end
        end
        
        else begin
            state = next_state;
         end
    end


endmodule
module dcache (clock,reset,C_WRITE,C_READ,C_Address,C_WRITEDATA,C_READDATA,busywait,mem_write,mem_read,mem_address,mem_writedata,mem_readdata,mem_busywait);


    input  clock, reset,C_WRITE,C_READ,mem_busywait;
    input [7:0] C_WRITEDATA,C_Address;
    input [31:0] mem_readdata;

    output reg mem_write,mem_read,busywait;
    output reg [5:0] mem_address;
    output reg [7:0] C_READDATA;
    output reg [31:0] mem_writedata;
   
   reg readaccess,writeaccess,dirtybit,validbit;
   reg [1:0] offset;
   reg [2:0] index,tag;
   reg [36:0] Cache_MEM [7:0];
   reg [31:0] BLOCK;
   reg hit;
  
   always@(BLOCK[7:0],BLOCK[15:8],BLOCK[23:16],BLOCK[31:24],offset)
   begin
   #1
   case(offset)
         2'b00 :C_READDATA=BLOCK[7:0]; 
         2'b01 :C_READDATA=BLOCK[15:8];
         2'b10 :C_READDATA=BLOCK[23:16];
         2'b11 :C_READDATA=BLOCK[31:24];

  endcase 
  end
    
   always @(C_Address[5],C_Address[6],C_Address[7],tag[0],tag[1],tag[2],validbit)
    begin
    if(tag[0]==C_Address[5] && tag[1]==C_Address[6] && tag[2]==C_Address[7] && validbit)
    #0.9 hit=1'b1;
    else
    # 0.9 hit=1'b0;
    end
    

	
  always @(C_WRITE,C_READ)
	begin

		busywait = ((C_READ || C_WRITE))? 1 : 0;
		readaccess = (C_READ && !C_WRITE)? 1 : 0;
		writeaccess = (!C_READ && C_WRITE)? 1 : 0;
	end

 always @(posedge clock)begin 
	
		if(readaccess == 1'b1 && hit == 1'b1)begin
			
			readaccess = 1'b0;
			busywait= 1'b0;
		end
		else if(writeaccess == 1'b1 && hit == 1'b1)begin
			busywait = 1'b0;
			
			#1
			case(offset)
			

				2'b00	:	Cache_MEM[index][7:0] = C_WRITEDATA;
				2'b01 	:	Cache_MEM[index][15:8] = C_WRITEDATA;
				2'b10 	:	Cache_MEM[index][23:16] = C_WRITEDATA;
				2'b11   :	Cache_MEM[index][31:24] = C_WRITEDATA;
		
			endcase
			Cache_MEM[index][35] = 1'b1;
                        Cache_MEM[index][36]=1'b1;
			writeaccess = 1'b0;
			
		 
		 end
	end
    
  


always @(*)begin
		

		if(readaccess == 1'b1 || writeaccess == 1'b1)
                begin
		
			#1
                        
			BLOCK =  Cache_MEM[C_Address[4:2]][31:0];
			tag =  Cache_MEM[ C_Address[4:2] ][34:32];
			dirtybit =  Cache_MEM[C_Address[4:2]][35];
			validbit = Cache_MEM[C_Address[4:2]][36];
			offset =  C_Address[1:0];
			index =  C_Address[4:2];
			
		end
		
	
	end





    parameter IDLE = 3'b000, MEM_READ = 3'b001,MEM_WRITE=3'b010,C_MEM_WRITE=3'b011;
    reg [2:0] state, next_state;


    always @(*)
    begin
        case (state)
            IDLE:
                if ((C_READ || C_WRITE) && !dirtybit && !hit)
                    next_state = MEM_READ;
                else if ((C_READ ||C_WRITE) && dirtybit && !hit)
                    next_state = MEM_WRITE;
                else
                    next_state = IDLE;
            
            MEM_READ:
                if (!mem_busywait)
                    next_state = C_MEM_WRITE;
                else    
                    next_state = MEM_READ;


           MEM_WRITE:
             if (!mem_busywait)
                    next_state = MEM_READ;
                else    
                    next_state = MEM_WRITE;
					
	  C_MEM_WRITE:
               if ((C_READ || C_WRITE) && dirtybit && !hit)
                  next_state =C_MEM_WRITE ;
               else 
                  next_state =IDLE ;
              

               
        endcase
    end


    always @(*)
    begin
        case(state)
            IDLE:
            begin
                mem_read = 0;
                mem_write = 0;
                mem_address = 6'dx;
                mem_writedata = 32'dx;
                
                
            end
         
            MEM_READ: 
            begin
                mem_read = 1;
                mem_write = 0;
                mem_address = {tag,index};
                mem_writedata = 32'dx;
                busywait=1;
                

               
               
            end


           		MEM_WRITE: 
            begin
                mem_read  = 1'd0;
                mem_write = 1'd1;
                mem_address ={tag,index};
                mem_writedata =BLOCK;
               busywait=1;
                
               
               
              
            end
			
			C_MEM_WRITE: 
            begin
                mem_read = 1'd0;
                mem_write = 1'd0;
                mem_address = 6'dx;
                mem_writedata = 32'dx;
                 busywait=1;

                
				#1
				Cache_MEM[index][31:0] = mem_readdata;
				Cache_MEM[index][34:32] = C_Address[7:5];
				Cache_MEM[index][35] = 1'd0;
				Cache_MEM[index][36] = 1'd1;
			
            end
            
            
            
            
        endcase
    end
    integer j;

    always @(posedge clock, reset)
    
    begin
        if(reset)
        begin
            state = IDLE;
            busywait=1'b0;
             #1;
             for( j=0;j<8;j=j+1)
            begin
            Cache_MEM[j] = 37'd0;
            end
        end
        
        else begin
            state = next_state;
         end
    end


endmodule