data/full_repos/permissive/441359809/src/yosys/tests/svtypes/logic_rom.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/svtypes/logic_rom.sv:5: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                           : ... In instance top\n    initial for(i = 0; i < 16; i = i + 1) mem[i] = i;\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top(input [3:0] addr, output [7:0] data);
    logic [7:0] mem[0:15];
    assign data = mem[addr];
    integer i;
    initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
endmodule
module top(input [3:0] addr, output [7:0] data);

    logic [7:0] mem[0:15];
    assign data = mem[addr];
    integer i;
    initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
endmodule