data/full_repos/permissive/425529933/Proyecto1Digitales2/parallel-serial/parallel_serial_e.v
data/verilator_xmls/ce696033-cb60-4866-a823-704d45aeacbd.xml
module parallel_serial_e(clk_32f, reset, valid_in, Data_in, Data_out_e);
  (* src = "parallel_serial_e.v:11" *)
  reg _0_;
  (* src = "parallel_serial_e.v:11" *)
  reg [2:0] _1_;
  (* src = "parallel_serial_e.v:11" *)
  reg [7:0] _2_;
  (* src = "parallel_serial_e.v:19" *)
  reg _3_;
  (* src = "parallel_serial_e.v:19" *)
  reg [2:0] _4_;
  (* src = "parallel_serial_e.v:19" *)
  reg [7:0] _5_;
  (* src = "parallel_serial_e.v:12" *)
  wire _6_;
  (* src = "parallel_serial_e.v:5" *)
  input [7:0] Data_in;
  (* src = "parallel_serial_e.v:6" *)
  output Data_out_e;
  reg Data_out_e;
  (* src = "parallel_serial_e.v:2" *)
  input clk_32f;
  (* src = "parallel_serial_e.v:9" *)
  reg [2:0] contador;
  (* src = "parallel_serial_e.v:8" *)
  reg [7:0] data2send;
  (* src = "parallel_serial_e.v:3" *)
  input reset;
  (* src = "parallel_serial_e.v:4" *)
  input valid_in;
  assign _6_ = ~(* src = "parallel_serial_e.v:12" *) reset;
  always @* begin
    _1_ = contador;
    _0_ = Data_out_e;
    _2_ = data2send;
    (* src = "parallel_serial_e.v:12" *)
    casez (_6_)

      1'h1:
        begin
          _0_ = 1'h0;
          _2_ = 8'hbc;
          _1_ = 3'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      contador <= _1_;
      Data_out_e <= _0_;
      data2send <= _2_;
  end
  always @* begin
    _4_ = contador;
    _3_ = Data_out_e;
    _5_ = data2send;
    (* src = "parallel_serial_e.v:20" *)
    casez (contador)

      3'h0:
        begin
          _3_ = data2send[7];
          _4_ = 3'h1;
        end

      3'h1:
        begin
          _3_ = data2send[6];
          _4_ = 3'h2;
        end

      3'h2:
        begin
          _3_ = data2send[5];
          _4_ = 3'h3;
        end

      3'h3:
        begin
          _3_ = data2send[4];
          _4_ = 3'h4;
        end

      3'h4:
        begin
          _3_ = data2send[3];
          _4_ = 3'h5;
        end

      3'h5:
        begin
          _3_ = data2send[2];
          _4_ = 3'h6;
        end

      3'h6:
        begin
          _3_ = data2send[1];
          _4_ = 3'h7;
        end

      3'h7:
        begin
          _3_ = data2send[0];
          _4_ = 3'h0;
          (* src = "parallel_serial_e.v:60" *)
          casez (valid_in)

            1'h1:
                _5_ = Data_in;

            default:
                _5_ = 8'hbc;
          endcase
        end
      default:
;
    endcase
  end
  always @(posedge clk_32f) begin
      contador <= _4_;
      Data_out_e <= _3_;
      data2send <= _5_;
  end
endmodule
module parallel_serial_e(clk_32f, reset, valid_in, Data_in, Data_out_e);

  (* src = "parallel_serial_e.v:11" *)
  reg _0_;
  (* src = "parallel_serial_e.v:11" *)
  reg [2:0] _1_;
  (* src = "parallel_serial_e.v:11" *)
  reg [7:0] _2_;
  (* src = "parallel_serial_e.v:19" *)
  reg _3_;
  (* src = "parallel_serial_e.v:19" *)
  reg [2:0] _4_;
  (* src = "parallel_serial_e.v:19" *)
  reg [7:0] _5_;
  (* src = "parallel_serial_e.v:12" *)
  wire _6_;
  (* src = "parallel_serial_e.v:5" *)
  input [7:0] Data_in;
  (* src = "parallel_serial_e.v:6" *)
  output Data_out_e;
  reg Data_out_e;
  (* src = "parallel_serial_e.v:2" *)
  input clk_32f;
  (* src = "parallel_serial_e.v:9" *)
  reg [2:0] contador;
  (* src = "parallel_serial_e.v:8" *)
  reg [7:0] data2send;
  (* src = "parallel_serial_e.v:3" *)
  input reset;
  (* src = "parallel_serial_e.v:4" *)
  input valid_in;
  assign _6_ = ~(* src = "parallel_serial_e.v:12" *) reset;
  always @* begin
    _1_ = contador;
    _0_ = Data_out_e;
    _2_ = data2send;
    (* src = "parallel_serial_e.v:12" *)
    casez (_6_)

      1'h1:
        begin
          _0_ = 1'h0;
          _2_ = 8'hbc;
          _1_ = 3'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      contador <= _1_;
      Data_out_e <= _0_;
      data2send <= _2_;
  end
  always @* begin
    _4_ = contador;
    _3_ = Data_out_e;
    _5_ = data2send;
    (* src = "parallel_serial_e.v:20" *)
    casez (contador)

      3'h0:
        begin
          _3_ = data2send[7];
          _4_ = 3'h1;
        end

      3'h1:
        begin
          _3_ = data2send[6];
          _4_ = 3'h2;
        end

      3'h2:
        begin
          _3_ = data2send[5];
          _4_ = 3'h3;
        end

      3'h3:
        begin
          _3_ = data2send[4];
          _4_ = 3'h4;
        end

      3'h4:
        begin
          _3_ = data2send[3];
          _4_ = 3'h5;
        end

      3'h5:
        begin
          _3_ = data2send[2];
          _4_ = 3'h6;
        end

      3'h6:
        begin
          _3_ = data2send[1];
          _4_ = 3'h7;
        end

      3'h7:
        begin
          _3_ = data2send[0];
          _4_ = 3'h0;
          (* src = "parallel_serial_e.v:60" *)
          casez (valid_in)

            1'h1:
                _5_ = Data_in;

            default:
                _5_ = 8'hbc;
          endcase
        end
      default:
;
    endcase
  end
  always @(posedge clk_32f) begin
      contador <= _4_;
      Data_out_e <= _3_;
      data2send <= _5_;
  end
endmodule