data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv
1: b'%Error: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:2: Cannot find include file: riscv_pipeline.sv\n`include "riscv_pipeline.sv" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/riscv_pipeline.sv\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/riscv_pipeline.sv.v\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/riscv_pipeline.sv.sv\n             riscv_pipeline.sv\n             riscv_pipeline.sv.v\n             riscv_pipeline.sv.sv\n             obj_dir/riscv_pipeline.sv\n             obj_dir/riscv_pipeline.sv.v\n             obj_dir/riscv_pipeline.sv.sv\n%Error: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:3: Cannot find include file: instr_rom.sv\n`include "instr_rom.sv" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:4: Cannot find include file: ram_bus.sv\n`include "ram_bus.sv" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:7: Unsupported or unknown PLI call: $timeformat\n initial $timeformat(-9,1," ns",9);\n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ! clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:50: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/435890256/my_riscv/tb_riscv_pipeline.sv:52: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module tb_riscv_pipeline;

  logic clk;
  logic rst_n;
  logic [31:0] i_boot_addr;
  dualport_bus instr_master();
  dualport_bus mem_master();
  int counter_finish = 0;

  riscv_pipeline DUT(
    .clk(clk),
    .rst_n(rst_n),
    .i_boot_addr(i_boot_addr),
    .instr_master(instr_master.master),
    .mem_master(mem_master.master)
  );
  
  instr_rom ideal_instr(
    .clk(clk),
    .rst_n(rst_n),
    .instr_slave(instr_master.slave)
  );

  ram_bus ideal_mem(
    .clk(clk),
    .rst_n(rst_n),
    .mem_slave(mem_master.slave)
  );

  initial begin
    clk = 1'b0;
    i_boot_addr = 32'h0000_0000;
    rst_n = 1'b1;
  end

  initial begin
		forever #10 clk = ! clk;
	end

  initial begin
    #20;
    rst_n = 1'b0;
    #20;
    rst_n = 1'b1;
  end


  always@(posedge clk) begin
    counter_finish = counter_finish + 1;

    if(counter_finish == 200) $finish;
  end

endmodule
module tb_riscv_pipeline;


  logic clk;
  logic rst_n;
  logic [31:0] i_boot_addr;
  dualport_bus instr_master();
  dualport_bus mem_master();
  int counter_finish = 0;

  riscv_pipeline DUT(
    .clk(clk),
    .rst_n(rst_n),
    .i_boot_addr(i_boot_addr),
    .instr_master(instr_master.master),
    .mem_master(mem_master.master)
  );
  
  instr_rom ideal_instr(
    .clk(clk),
    .rst_n(rst_n),
    .instr_slave(instr_master.slave)
  );

  ram_bus ideal_mem(
    .clk(clk),
    .rst_n(rst_n),
    .mem_slave(mem_master.slave)
  );

  initial begin
    clk = 1'b0;
    i_boot_addr = 32'h0000_0000;
    rst_n = 1'b1;
  end

  initial begin
		forever #10 clk = ! clk;
	end

  initial begin
    #20;
    rst_n = 1'b0;
    #20;
    rst_n = 1'b1;
  end


  always@(posedge clk) begin
    counter_finish = counter_finish + 1;

    if(counter_finish == 200) $finish;
  end

endmodule