data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteGen.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteGen.v:145: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'sprite\'\nmodule sprite(\n       ^~~~~~\n                                                                                         : ... Top module \'palette\'\nmodule palette(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteGen.v:64: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                     : ... In instance sprite\n   f_relPosX = {5\'d16,3\'b0};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteGen.v:70: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'negpo\' generates 4 bits.\n                                                                                     : ... In instance sprite\n   f_relPosX = relPosX + (negpo);\n                       ^\n%Error: Exiting due to 3 warning(s)\n'
module palette(
	input clk,
	
	input[4:0] bcol1,
	input[4:0] bcol2,
	input[4:0] bcol3,
	input[4:0] bcol4,
	
	input[1:0] scol,
	
	output reg[4:0] col,
	output reg d
);


always@(posedge clk)begin
	case(scol)
		2'd0: begin
				col <= 5'd13;
				d <= 0;
				end
		2'd1: begin
				col <= bcol2;
				d <= 1;
				end
		2'd2: begin
				col <= bcol3;
				d <= 1;
				end
		2'd3: begin
				col <= bcol4;
				d <= 1;
				end
		default: begin
					col <= 0;
					d <= 0;
				end
	endcase
end

endmodule
module palette(
	input clk,
	
	input[4:0] bcol1,
	input[4:0] bcol2,
	input[4:0] bcol3,
	input[4:0] bcol4,
	
	input[1:0] scol,
	
	output reg[4:0] col,
	output reg d
);



always@(posedge clk)begin
	case(scol)
		2'd0: begin
				col <= 5'd13;
				d <= 0;
				end
		2'd1: begin
				col <= bcol2;
				d <= 1;
				end
		2'd2: begin
				col <= bcol3;
				d <= 1;
				end
		2'd3: begin
				col <= bcol4;
				d <= 1;
				end
		default: begin
					col <= 0;
					d <= 0;
				end
	endcase
end

endmodule