data/full_repos/permissive/475642691/simulations/new/simSM.v
1: b'%Error: data/full_repos/permissive/475642691/simulations/new/simSM.v:18: Unsupported or unknown PLI call: $monitor\n$monitor($time,"Next State = %b%b%b%b, Current State = %b%b%b%b, RST = %b, Clock = %b",NS[3],NS[2],NS[1],NS[0],CS[3],CS[2],CS[1],CS[0],RST,CLK);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSM.v:20: Unsupported: Ignoring delay on this delayed statement.\n#5  NS[3] = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSM.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5 NS[3] = 1;\n^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simSM();
reg [3:0]NS;
reg CLK;
reg RST;
wire [3:0]CS;
SM StateMemory(NS,CLK,RST,CS);
initial
begin
CLK <=0;
RST <=0;
NS[3]<=0;
NS[2]<=0;
NS[1]<=0;
NS[0]<=0;
$monitor($time,"Next State = %b%b%b%b, Current State = %b%b%b%b, RST = %b, Clock = %b",NS[3],NS[2],NS[1],NS[0],CS[3],CS[2],CS[1],CS[0],RST,CLK);

#5  NS[3] = 1;
    NS[2] = 1;
    NS[1] = 0;
    NS[0] = 1;
    CLK = 1;

#5 NS[3] = 1;
    NS[2] = 1;
    NS[1] = 0;
    NS[0] = 1;
    CLK = 0;
end
endmodule
module simSM();

reg [3:0]NS;
reg CLK;
reg RST;
wire [3:0]CS;
SM StateMemory(NS,CLK,RST,CS);
initial
begin
CLK <=0;
RST <=0;
NS[3]<=0;
NS[2]<=0;
NS[1]<=0;
NS[0]<=0;
$monitor($time,"Next State = %b%b%b%b, Current State = %b%b%b%b, RST = %b, Clock = %b",NS[3],NS[2],NS[1],NS[0],CS[3],CS[2],CS[1],CS[0],RST,CLK);

#5  NS[3] = 1;
    NS[2] = 1;
    NS[1] = 0;
    NS[0] = 1;
    CLK = 1;

#5 NS[3] = 1;
    NS[2] = 1;
    NS[1] = 0;
    NS[0] = 1;
    CLK = 0;
end
endmodule