data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_32(out, a, b);
input [31:0] a, b;
output [31:0] out;

and_16 f(out[15:0], a[15:0], b[15:0]),
          s(out[31:16], a[31:16], b[31:16]);
endmodule
module and_32(out, a, b);

input [31:0] a, b;
output [31:0] out;

and_16 f(out[15:0], a[15:0], b[15:0]),
          s(out[31:16], a[31:16], b[31:16]);
endmodule