data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:19: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:22: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\n  import prim_esc_pkg::*;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:30: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int PING_CNT_DW = 16,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:40: syntax error, unexpected localparam, expecting IDENTIFIER\n  localparam int MarginFactor = 4,\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:41: syntax error, unexpected localparam, expecting IDENTIFIER\n  localparam int NumWaitCounts = 2,\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:42: syntax error, unexpected localparam, expecting IDENTIFIER\n  localparam int NumTimeoutCounts = 2,\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:43: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int TimeoutCntDw = $clog2(MarginFactor) +\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:48: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:54: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output esc_rx_t esc_rx_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:66: syntax error, unexpected IDENTIFIER\n  prim_buf #(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:96: syntax error, unexpected for\n  for (genvar k = 0; k < 2; k++) begin : gen_timeout_cnt\n  ^~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:103: syntax error, unexpected assign\n    assign cnt_d = (ping_en && !(&cnt_q[k]))         ? TimeoutCntDw\'(1) :\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:134: syntax error, unexpected IDENTIFIER\n  prim_generic_flop #(\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:238: Define or directive not defined: \'`ASSERT_KNOWN\'\n  `ASSERT_KNOWN(EscEnKnownO_A, esc_en_o)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:239: Define or directive not defined: \'`ASSERT_KNOWN\'\n  `ASSERT_KNOWN(RespPKnownO_A, esc_rx_o)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:241: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(SigIntCheck0_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=>\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:243: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(SigIntCheck1_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=> state_q == SigInt)\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:245: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(DiffEncCheck_A, esc_tx_i.esc_p ^ esc_tx_i.esc_n |=>\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:248: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(PingRespCheck_A, $rose(esc_tx_i.esc_p) |=> $fell(esc_tx_i.esc_p) |->\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:248: Unsupported or unknown PLI call: $rose\n  `ASSERT(PingRespCheck_A, $rose(esc_tx_i.esc_p) |=> $fell(esc_tx_i.esc_p) |->\n                           ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:248: Unsupported or unknown PLI call: $fell\n  `ASSERT(PingRespCheck_A, $rose(esc_tx_i.esc_p) |=> $fell(esc_tx_i.esc_p) |->\n                                                     ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:249: Unsupported or unknown PLI call: $rose\n      $rose(esc_rx_o.resp_p) |=> $fell(esc_rx_o.resp_p),\n      ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:249: Unsupported or unknown PLI call: $fell\n      $rose(esc_rx_o.resp_p) |=> $fell(esc_rx_o.resp_p),\n                                 ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:252: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(EscRespCheck_A, esc_tx_i.esc_p && $past(esc_tx_i.esc_p) &&\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:256: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(EscEnCheck_A, esc_tx_i.esc_p && (esc_tx_i.esc_p ^ esc_tx_i.esc_n) && state_q != SigInt\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:259: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(EscCntWrap_A, &cnt_q[0] |=> cnt_q[0] != 0)\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv:261: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(EscCntEsc_A, &cnt_q[0] |-> esc_en_o)\n  ^~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module prim_esc_receiver
  import prim_esc_pkg::*;
#(


  parameter int N_ESC_SEV = 4,



  parameter int PING_CNT_DW = 16,









  localparam int MarginFactor = 4,
  localparam int NumWaitCounts = 2,
  localparam int NumTimeoutCounts = 2,
  parameter int TimeoutCntDw = $clog2(MarginFactor) +
                               $clog2(N_ESC_SEV) +
                               $clog2(NumWaitCounts) +
                               $clog2(NumTimeoutCounts) +
                               PING_CNT_DW
) (
  input           clk_i,
  input           rst_ni,

  output logic    esc_en_o,

  output esc_rx_t esc_rx_o,

  input esc_tx_t  esc_tx_i
);





  logic esc_level, esc_p, esc_n, sigint_detected;


  prim_buf #(
    .Width(2)
  ) u_prim_buf_esc (
    .in_i({esc_tx_i.esc_n,
           esc_tx_i.esc_p}),
    .out_o({esc_n,
            esc_p})
  );

  prim_diff_decode #(
    .AsyncOn(1'b0)
  ) u_decode_esc (
    .clk_i,
    .rst_ni,
    .diff_pi  ( esc_p           ),
    .diff_ni  ( esc_n           ),
    .level_o  ( esc_level       ),
    .rise_o   (                 ),
    .fall_o   (                 ),
    .event_o  (                 ),
    .sigint_o ( sigint_detected )
  );





  logic ping_en, esc_en;
  logic [1:0][TimeoutCntDw-1:0] cnt_q;

  for (genvar k = 0; k < 2; k++) begin : gen_timeout_cnt

    logic [TimeoutCntDw-1:0] cnt_d;




    assign cnt_d = (ping_en && !(&cnt_q[k]))         ? TimeoutCntDw'(1) :
                   ((cnt_q[k] > '0) && !(&cnt_q[k])) ? cnt_q[k] + 1'b1  :
                                                       cnt_q[k];
    prim_flop #(
      .Width(TimeoutCntDw)
    ) u_prim_flop (
      .clk_i,
      .rst_ni,
      .d_i(cnt_d),
      .q_o(cnt_q[k])
    );
  end





  assign esc_en_o = esc_en      ||
                    (&cnt_q[0]) ||
                    (cnt_q[0] != cnt_q[1]);





  typedef enum logic [2:0] {Idle, Check, PingResp, EscResp, SigInt} state_e;
  state_e state_d, state_q;
  logic resp_pd, resp_pq;
  logic resp_nd, resp_nq;


  prim_generic_flop #(
    .Width(2),
    .ResetValue(2'b10)
  ) u_prim_generic_flop (
    .clk_i,
    .rst_ni,
    .d_i({resp_nd, resp_pd}),
    .q_o({resp_nq, resp_pq})
  );

  assign esc_rx_o.resp_p = resp_pq;
  assign esc_rx_o.resp_n = resp_nq;

  always_comb begin : p_fsm

    state_d  = state_q;
    resp_pd  = 1'b0;
    resp_nd  = 1'b1;
    esc_en   = 1'b0;
    ping_en  = 1'b0;

    unique case (state_q)

      Idle: begin
        if (esc_level) begin
          state_d = Check;
          resp_pd = 1'b1;
          resp_nd = 1'b0;
        end
      end


      Check: begin
        state_d = PingResp;
        if (esc_level) begin
          state_d  = EscResp;
          esc_en   = 1'b1;
        end
      end


      PingResp: begin
        state_d = Idle;
        resp_pd = 1'b1;
        resp_nd = 1'b0;
        ping_en = 1'b1;
        if (esc_level) begin
          state_d  = EscResp;
          esc_en   = 1'b1;
        end
      end


      EscResp: begin
        state_d = Idle;
        if (esc_level) begin
          state_d  = EscResp;
          resp_pd  = ~resp_pq;
          resp_nd  = resp_pq;
          esc_en   = 1'b1;
        end
      end





      SigInt: begin
        state_d = Idle;
        if (sigint_detected) begin
          state_d = SigInt;
          resp_pd = ~resp_pq;
          resp_nd = ~resp_pq;
        end
      end
      default : state_d = Idle;
    endcase


    if (sigint_detected && (state_q != SigInt)) begin
      state_d  = SigInt;
      resp_pd  = 1'b0;
      resp_nd  = 1'b0;
    end
  end






  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
    if (!rst_ni) begin
      state_q <= Idle;
    end else begin
      state_q <= state_d;
    end
  end






  `ASSERT_KNOWN(EscEnKnownO_A, esc_en_o)
  `ASSERT_KNOWN(RespPKnownO_A, esc_rx_o)

  `ASSERT(SigIntCheck0_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=>
      esc_rx_o.resp_p == esc_rx_o.resp_n, clk_i, !rst_ni)
  `ASSERT(SigIntCheck1_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=> state_q == SigInt)

  `ASSERT(DiffEncCheck_A, esc_tx_i.esc_p ^ esc_tx_i.esc_n |=>
      esc_rx_o.resp_p ^ esc_rx_o.resp_n)

  `ASSERT(PingRespCheck_A, $rose(esc_tx_i.esc_p) |=> $fell(esc_tx_i.esc_p) |->
      $rose(esc_rx_o.resp_p) |=> $fell(esc_rx_o.resp_p),
      clk_i, !rst_ni || (esc_tx_i.esc_p == esc_tx_i.esc_n))

  `ASSERT(EscRespCheck_A, esc_tx_i.esc_p && $past(esc_tx_i.esc_p) &&
      (esc_tx_i.esc_p ^ esc_tx_i.esc_n) && $past(esc_tx_i.esc_p ^ esc_tx_i.esc_n)
      |=> esc_rx_o.resp_p != $past(esc_rx_o.resp_p))

  `ASSERT(EscEnCheck_A, esc_tx_i.esc_p && (esc_tx_i.esc_p ^ esc_tx_i.esc_n) && state_q != SigInt
      |=> esc_tx_i.esc_p && (esc_tx_i.esc_p ^ esc_tx_i.esc_n) |-> esc_en_o)

  `ASSERT(EscCntWrap_A, &cnt_q[0] |=> cnt_q[0] != 0)

  `ASSERT(EscCntEsc_A, &cnt_q[0] |-> esc_en_o)

endmodule
module prim_esc_receiver
  import prim_esc_pkg::*;

#(


  parameter int N_ESC_SEV = 4,



  parameter int PING_CNT_DW = 16,









  localparam int MarginFactor = 4,
  localparam int NumWaitCounts = 2,
  localparam int NumTimeoutCounts = 2,
  parameter int TimeoutCntDw = $clog2(MarginFactor) +
                               $clog2(N_ESC_SEV) +
                               $clog2(NumWaitCounts) +
                               $clog2(NumTimeoutCounts) +
                               PING_CNT_DW
) (
  input           clk_i,
  input           rst_ni,

  output logic    esc_en_o,

  output esc_rx_t esc_rx_o,

  input esc_tx_t  esc_tx_i
);





  logic esc_level, esc_p, esc_n, sigint_detected;


  prim_buf #(
    .Width(2)
  ) u_prim_buf_esc (
    .in_i({esc_tx_i.esc_n,
           esc_tx_i.esc_p}),
    .out_o({esc_n,
            esc_p})
  );

  prim_diff_decode #(
    .AsyncOn(1'b0)
  ) u_decode_esc (
    .clk_i,
    .rst_ni,
    .diff_pi  ( esc_p           ),
    .diff_ni  ( esc_n           ),
    .level_o  ( esc_level       ),
    .rise_o   (                 ),
    .fall_o   (                 ),
    .event_o  (                 ),
    .sigint_o ( sigint_detected )
  );





  logic ping_en, esc_en;
  logic [1:0][TimeoutCntDw-1:0] cnt_q;

  for (genvar k = 0; k < 2; k++) begin : gen_timeout_cnt

    logic [TimeoutCntDw-1:0] cnt_d;




    assign cnt_d = (ping_en && !(&cnt_q[k]))         ? TimeoutCntDw'(1) :
                   ((cnt_q[k] > '0) && !(&cnt_q[k])) ? cnt_q[k] + 1'b1  :
                                                       cnt_q[k];
    prim_flop #(
      .Width(TimeoutCntDw)
    ) u_prim_flop (
      .clk_i,
      .rst_ni,
      .d_i(cnt_d),
      .q_o(cnt_q[k])
    );
  end





  assign esc_en_o = esc_en      ||
                    (&cnt_q[0]) ||
                    (cnt_q[0] != cnt_q[1]);





  typedef enum logic [2:0] {Idle, Check, PingResp, EscResp, SigInt} state_e;
  state_e state_d, state_q;
  logic resp_pd, resp_pq;
  logic resp_nd, resp_nq;


  prim_generic_flop #(
    .Width(2),
    .ResetValue(2'b10)
  ) u_prim_generic_flop (
    .clk_i,
    .rst_ni,
    .d_i({resp_nd, resp_pd}),
    .q_o({resp_nq, resp_pq})
  );

  assign esc_rx_o.resp_p = resp_pq;
  assign esc_rx_o.resp_n = resp_nq;

  always_comb begin : p_fsm

    state_d  = state_q;
    resp_pd  = 1'b0;
    resp_nd  = 1'b1;
    esc_en   = 1'b0;
    ping_en  = 1'b0;

    unique case (state_q)

      Idle: begin
        if (esc_level) begin
          state_d = Check;
          resp_pd = 1'b1;
          resp_nd = 1'b0;
        end
      end


      Check: begin
        state_d = PingResp;
        if (esc_level) begin
          state_d  = EscResp;
          esc_en   = 1'b1;
        end
      end


      PingResp: begin
        state_d = Idle;
        resp_pd = 1'b1;
        resp_nd = 1'b0;
        ping_en = 1'b1;
        if (esc_level) begin
          state_d  = EscResp;
          esc_en   = 1'b1;
        end
      end


      EscResp: begin
        state_d = Idle;
        if (esc_level) begin
          state_d  = EscResp;
          resp_pd  = ~resp_pq;
          resp_nd  = resp_pq;
          esc_en   = 1'b1;
        end
      end





      SigInt: begin
        state_d = Idle;
        if (sigint_detected) begin
          state_d = SigInt;
          resp_pd = ~resp_pq;
          resp_nd = ~resp_pq;
        end
      end
      default : state_d = Idle;
    endcase


    if (sigint_detected && (state_q != SigInt)) begin
      state_d  = SigInt;
      resp_pd  = 1'b0;
      resp_nd  = 1'b0;
    end
  end






  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
    if (!rst_ni) begin
      state_q <= Idle;
    end else begin
      state_q <= state_d;
    end
  end






  `ASSERT_KNOWN(EscEnKnownO_A, esc_en_o)
  `ASSERT_KNOWN(RespPKnownO_A, esc_rx_o)

  `ASSERT(SigIntCheck0_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=>
      esc_rx_o.resp_p == esc_rx_o.resp_n, clk_i, !rst_ni)
  `ASSERT(SigIntCheck1_A, esc_tx_i.esc_p == esc_tx_i.esc_n |=> state_q == SigInt)

  `ASSERT(DiffEncCheck_A, esc_tx_i.esc_p ^ esc_tx_i.esc_n |=>
      esc_rx_o.resp_p ^ esc_rx_o.resp_n)

  `ASSERT(PingRespCheck_A, $rose(esc_tx_i.esc_p) |=> $fell(esc_tx_i.esc_p) |->
      $rose(esc_rx_o.resp_p) |=> $fell(esc_rx_o.resp_p),
      clk_i, !rst_ni || (esc_tx_i.esc_p == esc_tx_i.esc_n))

  `ASSERT(EscRespCheck_A, esc_tx_i.esc_p && $past(esc_tx_i.esc_p) &&
      (esc_tx_i.esc_p ^ esc_tx_i.esc_n) && $past(esc_tx_i.esc_p ^ esc_tx_i.esc_n)
      |=> esc_rx_o.resp_p != $past(esc_rx_o.resp_p))

  `ASSERT(EscEnCheck_A, esc_tx_i.esc_p && (esc_tx_i.esc_p ^ esc_tx_i.esc_n) && state_q != SigInt
      |=> esc_tx_i.esc_p && (esc_tx_i.esc_p ^ esc_tx_i.esc_n) |-> esc_en_o)

  `ASSERT(EscCntWrap_A, &cnt_q[0] |=> cnt_q[0] != 0)

  `ASSERT(EscCntEsc_A, &cnt_q[0] |-> esc_en_o)

endmodule