data/full_repos/permissive/426889244/verilog/IFExcDecoder.v
data/verilator_xmls/4b91b88e-8dc8-440d-a736-40e3329dc066.xml
module IFExcDecoder (
    input wire[31:0] if_imem_rdata,

    output wire exception,
    output wire eret,
    output wire[4:0] cause
);

    assign exception = if_imem_rdata[31:26] == 6'b000000 & if_imem_rdata[5:0] == 6'b001100;
    assign eret = if_imem_rdata[31:26] == 6'b010000 & if_imem_rdata[5:0] == 6'b011000;
    assign cause = 5'h8;
    
endmodule
module IFExcDecoder (
    input wire[31:0] if_imem_rdata,

    output wire exception,
    output wire eret,
    output wire[4:0] cause
);


    assign exception = if_imem_rdata[31:26] == 6'b000000 & if_imem_rdata[5:0] == 6'b001100;
    assign eret = if_imem_rdata[31:26] == 6'b010000 & if_imem_rdata[5:0] == 6'b011000;
    assign cause = 5'h8;
    
endmodule