data/full_repos/permissive/480681467/Source/Main/mod_exp.v
1: b'%Error: data/full_repos/permissive/480681467/Source/Main/mod_exp.v:29: Cannot find file containing module: \'mod\'\n    mod base_squared_mod(base_squared,modulo_reg,base_next,);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/mod\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/mod.v\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/mod.sv\n             mod\n             mod.v\n             mod.sv\n             obj_dir/mod\n             obj_dir/mod.v\n             obj_dir/mod.sv\n%Error: data/full_repos/permissive/480681467/Source/Main/mod_exp.v:31: Cannot find file containing module: \'mod\'\n    mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,);\n    ^~~\n%Warning-WIDTH: data/full_repos/permissive/480681467/Source/Main/mod_exp.v:40: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                             : ... In instance mod_exp\n            result_reg <= 32\'d1;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module mod_exp(
    input [WIDTH*2-1:0] base, 
	input [WIDTH*2-1:0] modulo,
	input [WIDTH*2-1:0] exponent,
	input clk,
	input reset,
	output finish,
    output [WIDTH*2-1:0] result
    );
    
    parameter WIDTH = 32;
        
    reg [WIDTH*2-1:0] base_reg,modulo_reg,exponent_reg,result_reg;
    reg [1:0] state;
    
    wire [WIDTH*2-1:0] result_mul_base = result_reg * base_reg;
    wire [WIDTH*2-1:0] result_next;
    wire [WIDTH*2-1:0] base_squared = base_reg * base_reg;
    wire [WIDTH*2-1:0] base_next;
    wire [WIDTH*2-1:0] exponent_next = exponent_reg >> 1;
    
    assign finish = (state == `HOLD) ? 1'b1:1'b0;
    assign result = result_reg;
    
    mod base_squared_mod(base_squared,modulo_reg,base_next,);
    defparam base_squared_mod.WIDTH = WIDTH*2; 
    mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,);
    defparam result_mul_base_mod.WIDTH = WIDTH*2;
    
   
    always @(posedge clk) begin
        if(reset) begin
            base_reg <= base;
            modulo_reg <= modulo;
            exponent_reg <= exponent;                
            result_reg <= 32'd1;
            state <= `UPDATE;
        end
        else case(state)
            `UPDATE: begin
                if (exponent_reg != 64'd0) begin
                    if (exponent_reg[0])
                        result_reg <= result_next;
                    base_reg <= base_next;
                    exponent_reg <= exponent_next;
                    state <= `UPDATE;
                end
                else state <= `HOLD;
            end
            
           `HOLD: begin
                end
       endcase
    end
endmodule
module mod_exp(
    input [WIDTH*2-1:0] base, 
	input [WIDTH*2-1:0] modulo,
	input [WIDTH*2-1:0] exponent,
	input clk,
	input reset,
	output finish,
    output [WIDTH*2-1:0] result
    );

    
    parameter WIDTH = 32;
        
    reg [WIDTH*2-1:0] base_reg,modulo_reg,exponent_reg,result_reg;
    reg [1:0] state;
    
    wire [WIDTH*2-1:0] result_mul_base = result_reg * base_reg;
    wire [WIDTH*2-1:0] result_next;
    wire [WIDTH*2-1:0] base_squared = base_reg * base_reg;
    wire [WIDTH*2-1:0] base_next;
    wire [WIDTH*2-1:0] exponent_next = exponent_reg >> 1;
    
    assign finish = (state == `HOLD) ? 1'b1:1'b0;
    assign result = result_reg;
    
    mod base_squared_mod(base_squared,modulo_reg,base_next,);
    defparam base_squared_mod.WIDTH = WIDTH*2; 
    mod result_mul_base_mod (result_mul_base,modulo_reg,result_next,);
    defparam result_mul_base_mod.WIDTH = WIDTH*2;
    
   
    always @(posedge clk) begin
        if(reset) begin
            base_reg <= base;
            modulo_reg <= modulo;
            exponent_reg <= exponent;                
            result_reg <= 32'd1;
            state <= `UPDATE;
        end
        else case(state)
            `UPDATE: begin
                if (exponent_reg != 64'd0) begin
                    if (exponent_reg[0])
                        result_reg <= result_next;
                    base_reg <= base_next;
                    exponent_reg <= exponent_next;
                    state <= `UPDATE;
                end
                else state <= `HOLD;
            end
            
           `HOLD: begin
                end
       endcase
    end
endmodule