data/full_repos/permissive/500326609/a7/biu.v
data/verilator_xmls/b53fd02b-9298-4ef5-afe1-8482022bf301.xml
module biu (
    input clk,
    input reset,
    input [31:0] daddr,
    input [31:0] dwdata,
    input [3:0] dwe,
    output [31:0] drdata,


    output [31:0] daddr1,
    output [31:0] dwdata1,
    output [3:0]  dwe1,
    input  [31:0] drdata1,


    output [31:0] daddr2,
    output [31:0] dwdata2,
    output [3:0]  dwe2,
    input  [31:0] drdata2
);



  assign drdata = (daddr[31:14] === 18'b0) ? drdata1 : drdata2;



  assign daddr1 = daddr;
  assign dwdata1 = dwdata;
  assign dwe1 = (daddr[31:14] === 18'b0) ? dwe : 4'b0000;

  assign daddr2 = daddr;
  assign dwdata2 = dwdata;
  assign dwe2 = (daddr[31:14] === 18'b0) ? 4'b0000 : dwe;

endmodule
module biu (
    input clk,
    input reset,
    input [31:0] daddr,
    input [31:0] dwdata,
    input [3:0] dwe,
    output [31:0] drdata,


    output [31:0] daddr1,
    output [31:0] dwdata1,
    output [3:0]  dwe1,
    input  [31:0] drdata1,


    output [31:0] daddr2,
    output [31:0] dwdata2,
    output [3:0]  dwe2,
    input  [31:0] drdata2
);




  assign drdata = (daddr[31:14] === 18'b0) ? drdata1 : drdata2;



  assign daddr1 = daddr;
  assign dwdata1 = dwdata;
  assign dwe1 = (daddr[31:14] === 18'b0) ? dwe : 4'b0000;

  assign daddr2 = daddr;
  assign dwdata2 = dwdata;
  assign dwe2 = (daddr[31:14] === 18'b0) ? 4'b0000 : dwe;

endmodule