data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Error: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/ALU_TB.v:9: Cannot find file containing module: \'ALU\'\n    ALU alu_tb(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/ALU\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/ALU.v\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();
    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg [1:0] asmtb;
    
    wire [7:0] opctb;
 
    ALU alu_tb(
        .opa(opatb),
        .opb(opbtb),
        .asm(asmtb),

        .opc(opctb)
    );
    initial
        begin: TEST
            asmtb = 3;      
            opatb = 4;
            opbtb = 2;
            
            
            #100

            asmtb = 2;      
            opatb = 4;
            opbtb = 4;
           

            #100    
            
            asmtb = 1;      
            opatb = 9;
            opbtb = 1;
            
            #100    
            asmtb = 3;      
            opatb = 1;
            opbtb = 9;
            #1000
            $finish;
        end
endmodule
module alu_tb();

    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg [1:0] asmtb;
    
    wire [7:0] opctb;
 
    ALU alu_tb(
        .opa(opatb),
        .opb(opbtb),
        .asm(asmtb),

        .opc(opctb)
    );
    initial
        begin: TEST
            asmtb = 3;      
            opatb = 4;
            opbtb = 2;
            
            
            #100

            asmtb = 2;      
            opatb = 4;
            opbtb = 4;
           

            #100    
            
            asmtb = 1;      
            opatb = 9;
            opbtb = 1;
            
            #100    
            asmtb = 3;      
            opatb = 1;
            opbtb = 9;
            #1000
            $finish;
        end
endmodule