data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:15: Define or directive not defined: \'`OPCODE_COUNT\'\n        input  wire [`OPCODE_COUNT-1:0] opcode_type,\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:20: Define or directive not defined: \'`SIGNAL_COUNT\'\n        input  wire [`SIGNAL_COUNT-1:0] signals,\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:43: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :\n                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :\n                                                  ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:46: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_we   = signals[`CONTROL_REG_RD_READ]  ? 1\'b0 :\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_we   = signals[`CONTROL_REG_RD_READ]  ? 1\'b0 :\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:47: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                     signals[`CONTROL_REG_RD_WRITE] ? 1\'b1 : 1\'bx;\n                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:48: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_we   = signals[`CONTROL_REG_RR_READ]  ? 1\'b0 : 1\'bx;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_we   = signals[`CONTROL_REG_RR_READ]  ? 1\'b0 : 1\'bx;\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:49: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_oe   = signals[`CONTROL_REG_RD_READ]  ? 1\'b1 : 1\'bx;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_oe   = signals[`CONTROL_REG_RD_READ]  ? 1\'b1 : 1\'bx;\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:50: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_oe   = signals[`CONTROL_REG_RR_READ]  ? 1\'b1 : 1\'bx;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_oe   = signals[`CONTROL_REG_RR_READ]  ? 1\'b1 : 1\'bx;\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:51: Define or directive not defined: \'`CONTROL_REG_RD_READ\'\n    assign rd_cs   = signals[`CONTROL_REG_RD_READ] ||\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rd_cs   = signals[`CONTROL_REG_RD_READ] ||\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:52: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                     signals[`CONTROL_REG_RD_WRITE];\n                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:53: Define or directive not defined: \'`CONTROL_REG_RR_READ\'\n    assign rr_cs   = signals[`CONTROL_REG_RR_READ];\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/reg_file_interface_unit.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign rr_cs   = signals[`CONTROL_REG_RR_READ];\n                                                 ^\n%Error: Exiting due to 19 error(s)\n'
module reg_file_interface_unit #(

        parameter INSTR_WIDTH  = 16,

        parameter DATA_WIDTH   = 8,
        parameter R_ADDR_WIDTH = 5
    )(

        input  wire [`OPCODE_COUNT-1:0] opcode_type,

        input  wire    [DATA_WIDTH-1:0] writeback_value,


        input  wire [`SIGNAL_COUNT-1:0] signals,

        output wire  [R_ADDR_WIDTH-1:0] rr_addr,
        output wire  [R_ADDR_WIDTH-1:0] rd_addr,

        inout  wire    [DATA_WIDTH-1:0] rr_data,
        inout  wire    [DATA_WIDTH-1:0] rd_data,
        output wire                     rr_cs,
        output wire                     rd_cs,
        output wire                     rr_we,
        output wire                     rd_we,
        output wire                     rr_oe,
        output wire                     rd_oe
    );


    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :
                     {DATA_WIDTH{1'bz}};
    assign rr_data = {DATA_WIDTH{1'bz}};
    assign rd_we   = signals[`CONTROL_REG_RD_READ]  ? 1'b0 :
                     signals[`CONTROL_REG_RD_WRITE] ? 1'b1 : 1'bx;
    assign rr_we   = signals[`CONTROL_REG_RR_READ]  ? 1'b0 : 1'bx;
    assign rd_oe   = signals[`CONTROL_REG_RD_READ]  ? 1'b1 : 1'bx;
    assign rr_oe   = signals[`CONTROL_REG_RR_READ]  ? 1'b1 : 1'bx;
    assign rd_cs   = signals[`CONTROL_REG_RD_READ] ||
                     signals[`CONTROL_REG_RD_WRITE];
    assign rr_cs   = signals[`CONTROL_REG_RR_READ];

endmodule
module reg_file_interface_unit #(

        parameter INSTR_WIDTH  = 16,

        parameter DATA_WIDTH   = 8,
        parameter R_ADDR_WIDTH = 5
    )(

        input  wire [`OPCODE_COUNT-1:0] opcode_type,

        input  wire    [DATA_WIDTH-1:0] writeback_value,


        input  wire [`SIGNAL_COUNT-1:0] signals,

        output wire  [R_ADDR_WIDTH-1:0] rr_addr,
        output wire  [R_ADDR_WIDTH-1:0] rd_addr,

        inout  wire    [DATA_WIDTH-1:0] rr_data,
        inout  wire    [DATA_WIDTH-1:0] rd_data,
        output wire                     rr_cs,
        output wire                     rd_cs,
        output wire                     rr_we,
        output wire                     rd_we,
        output wire                     rr_oe,
        output wire                     rd_oe
    );



    assign rd_data = signals[`CONTROL_REG_RD_WRITE] ? writeback_value :
                     {DATA_WIDTH{1'bz}};
    assign rr_data = {DATA_WIDTH{1'bz}};
    assign rd_we   = signals[`CONTROL_REG_RD_READ]  ? 1'b0 :
                     signals[`CONTROL_REG_RD_WRITE] ? 1'b1 : 1'bx;
    assign rr_we   = signals[`CONTROL_REG_RR_READ]  ? 1'b0 : 1'bx;
    assign rd_oe   = signals[`CONTROL_REG_RD_READ]  ? 1'b1 : 1'bx;
    assign rr_oe   = signals[`CONTROL_REG_RR_READ]  ? 1'b1 : 1'bx;
    assign rd_cs   = signals[`CONTROL_REG_RD_READ] ||
                     signals[`CONTROL_REG_RD_WRITE];
    assign rr_cs   = signals[`CONTROL_REG_RR_READ];

endmodule