data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/rwsgen.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/rwsgen.v:47: Cannot find file containing module: 'atmux1'\natmux1 scmux\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/atmux1\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/atmux1.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/atmux1.sv\n             atmux1\n             atmux1.v\n             atmux1.sv\n             obj_dir/atmux1\n             obj_dir/atmux1.v\n             obj_dir/atmux1.sv\n%Error: Exiting due to 1 error(s)\n"
module rwsgen
    (
     clk,
     rst_,
     pce_,
     prnw,
     pws,
     prs,
     scanmode
     );




input   clk,
        rst_,
        pce_,
        prnw;
input   scanmode;
output  pws,
        prs;










wire    cerst_;

atmux1 scmux
    (
     .a(rst_),
     .b(~(pce_ | ~rst_)),
     .sela(scanmode),
     .o(cerst_)
     );
 


reg [2:0]   rin;
always @(posedge clk or negedge cerst_)
begin
    if(!cerst_) rin <= 3'b0;


    else rin <= {rin[1:0],(~pce_)};
end

wire    pul = ~rin[2] & rin[1];
reg     pws,prs;
always @(posedge clk or negedge cerst_)
    begin
    if(!cerst_)
        begin
        pws <= 1'b0;
        prs <= 1'b0;
        end
    else 
        begin
        pws <= ~prnw & pul;
        prs <= prnw & pul;
        end
    end

endmodule
module rwsgen
    (
     clk,
     rst_,
     pce_,
     prnw,
     pws,
     prs,
     scanmode
     );





input   clk,
        rst_,
        pce_,
        prnw;
input   scanmode;
output  pws,
        prs;










wire    cerst_;

atmux1 scmux
    (
     .a(rst_),
     .b(~(pce_ | ~rst_)),
     .sela(scanmode),
     .o(cerst_)
     );
 


reg [2:0]   rin;
always @(posedge clk or negedge cerst_)
begin
    if(!cerst_) rin <= 3'b0;


    else rin <= {rin[1:0],(~pce_)};
end

wire    pul = ~rin[2] & rin[1];
reg     pws,prs;
always @(posedge clk or negedge cerst_)
    begin
    if(!cerst_)
        begin
        pws <= 1'b0;
        prs <= 1'b0;
        end
    else 
        begin
        pws <= ~prnw & pul;
        prs <= prnw & pul;
        end
    end

endmodule