data/full_repos/permissive/494601143/dp_bram_simple.v
data/verilator_xmls/0f587fc6-ad9b-4bd1-a263-449f3b5ddf2f.xml
module relatively_mundane_sdp_ram #(
    parameter DATA = 72,
    parameter ADDR = 10
) (

    input   wire                clk,
 

    input   wire                wr,
    input   wire    [ADDR-1:0]  wr_addr,
    input   wire    [DATA-1:0]  wr_data,
 

    input   wire    [ADDR-1:0]  rd_addr,
    output  wire    [DATA-1:0]  rd_data
);
 

reg [DATA-1:0] mem [(2**ADDR)-1:0];
 

always @(posedge clk)
    if(wr)
        mem[wr_addr] <= wr_data;
 

reg [ADDR-1:0] rd_addr_reg;
always @(posedge clk)
    rd_addr_reg <= rd_addr;
 
assign rd_data = mem[rd_addr_reg];
 
endmodule
module relatively_mundane_sdp_ram #(
    parameter DATA = 72,
    parameter ADDR = 10
) (

    input   wire                clk,
 

    input   wire                wr,
    input   wire    [ADDR-1:0]  wr_addr,
    input   wire    [DATA-1:0]  wr_data,
 

    input   wire    [ADDR-1:0]  rd_addr,
    output  wire    [DATA-1:0]  rd_data
);

 

reg [DATA-1:0] mem [(2**ADDR)-1:0];
 

always @(posedge clk)
    if(wr)
        mem[wr_addr] <= wr_data;
 

reg [ADDR-1:0] rd_addr_reg;
always @(posedge clk)
    rd_addr_reg <= rd_addr;
 
assign rd_data = mem[rd_addr_reg];
 
endmodule