data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:2: Cannot find include file: ADD.v\n`include "ADD.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder,data/full_repos/permissive/414867793/ADD.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder,data/full_repos/permissive/414867793/ADD.v.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder,data/full_repos/permissive/414867793/ADD.v.sv\n             ADD.v\n             ADD.v.v\n             ADD.v.sv\n             obj_dir/ADD.v\n             obj_dir/ADD.v.v\n             obj_dir/ADD.v.sv\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ADD_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1,ADD_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module ADD_tb();
reg A,B;
wire S,C;
ADD uut(A,B,S,C);
initial begin
  $dumpfile("ADD_tb.vcd");
  $dumpvars(1,ADD_tb);

  A=0;
  B=0;
  #20
  A=0;
  B=1;
  #20
  A=1;
  B=0;
  #20
  A=1;
  B=1;
  #20
  $display("test Done");
end

endmodule
module ADD_tb();

reg A,B;
wire S,C;
ADD uut(A,B,S,C);
initial begin
  $dumpfile("ADD_tb.vcd");
  $dumpvars(1,ADD_tb);

  A=0;
  B=0;
  #20
  A=0;
  B=1;
  #20
  A=1;
  B=0;
  #20
  A=1;
  B=1;
  #20
  $display("test Done");
end

endmodule