data/full_repos/permissive/468929885/verilog/rtl/el_t_mid.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468929885/verilog/rtl/el_t_mid.v:27: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                              : ... In instance el_t_mid\n  sum = sum + in[in_idx];\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module el_t_mid#(
	parameter						IN_NUM = 3
)
(

	input	[IN_NUM-1 : 0]			in,

	output							out

);

localparam SUM_W = 32;

reg [SUM_W - 1:0] sum = 0;
reg out_r = 0;
assign out = out_r;

integer in_idx = 0;

always@(*)
begin
	sum = 0;
	for (in_idx = 0; in_idx < IN_NUM; in_idx = in_idx + 1)
	begin 
		sum = sum + in[in_idx];
	end
	if(sum >= ((IN_NUM+1)/2) )
	begin
		out_r = 1;
	end
	else
	begin
		out_r = 0;
	end
	
	
end

endmodule
module el_t_mid#(
	parameter						IN_NUM = 3
)
(

	input	[IN_NUM-1 : 0]			in,

	output							out

);


localparam SUM_W = 32;

reg [SUM_W - 1:0] sum = 0;
reg out_r = 0;
assign out = out_r;

integer in_idx = 0;

always@(*)
begin
	sum = 0;
	for (in_idx = 0; in_idx < IN_NUM; in_idx = in_idx + 1)
	begin 
		sum = sum + in[in_idx];
	end
	if(sum >= ((IN_NUM+1)/2) )
	begin
		out_r = 1;
	end
	else
	begin
		out_r = 0;
	end
	
	
end

endmodule