data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v
1: b'%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter FPGA_IP_BASE = {8\'d192, 8\'d168, 8\'d42, 8\'d240},\n    ^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:5: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FPGA_MAC_BASE = 48\'h080028_030405\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:6: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:9: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                [31:0] fpga_ip_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                [47:0] fpga_mac_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NOC_CHIPID_SIZE-1:0] home_chipid_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_fpga_config.v:12: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: Exiting due to 8 error(s)\n'
module ethernet_fpga_config #(
    `include "noc_parameter.vh"
    ,parameter FPGA_IP_BASE = {8'd192, 8'd168, 8'd42, 8'd240},
    parameter FPGA_MAC_BASE = 48'h080028_030405
)
(
    input  wire                 [3:0] switches_i,
    output wire                [31:0] fpga_ip_addr_o,
    output wire                [47:0] fpga_mac_addr_o,
    output wire [NOC_CHIPID_SIZE-1:0] home_chipid_o
);


assign fpga_ip_addr_o  = FPGA_IP_BASE + switches_i;
assign fpga_mac_addr_o = FPGA_MAC_BASE + switches_i;
assign home_chipid_o   = {{(NOC_CHIPID_SIZE-4){1'b0}}, switches_i};


endmodule
module ethernet_fpga_config #(
    `include "noc_parameter.vh"
    ,parameter FPGA_IP_BASE = {8'd192, 8'd168, 8'd42, 8'd240},
    parameter FPGA_MAC_BASE = 48'h080028_030405
)
(
    input  wire                 [3:0] switches_i,
    output wire                [31:0] fpga_ip_addr_o,
    output wire                [47:0] fpga_mac_addr_o,
    output wire [NOC_CHIPID_SIZE-1:0] home_chipid_o
);



assign fpga_ip_addr_o  = FPGA_IP_BASE + switches_i;
assign fpga_mac_addr_o = FPGA_MAC_BASE + switches_i;
assign home_chipid_o   = {{(NOC_CHIPID_SIZE-4){1'b0}}, switches_i};


endmodule