data/full_repos/permissive/43974493/src/uart.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/43974493/src/uart.v:36: Signal definition not found, creating implicitly: \'uart_state\'\n   assign uart_state = state;\n          ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/uart.v:36: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'state\' generates 2 bits.\n                                                                 : ... In instance uart\n   assign uart_state = state;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/uart.v:54: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'baud_counter\' generates 13 bits.\n                                                                 : ... In instance uart\n              if (baud_counter == (CLK_DIV / 2) - 1) begin\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/uart.v:65: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'rx_counter\' generates 3 bits.\n                                                                 : ... In instance uart\n                 if (rx_counter == DATA_BITS - 1) begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/uart.v:62: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'baud_counter\' generates 13 bits.\n                                                                 : ... In instance uart\n              if (baud_counter == CLK_DIV - 1) begin\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/43974493/src/uart.v:75: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'baud_counter\' generates 13 bits.\n                                                                 : ... In instance uart\n              if (baud_counter == CLK_DIV - 1) begin\n                               ^~\n%Error: Exiting due to 6 warning(s)\n'
module uart
  (
   input                      clk,
   input                      rst,
   input                      rx,
   output reg                 busy,
   output reg [DATA_BITS-1:0] data
   );

   initial begin
      busy = 0;
      data = 0;
   end


   parameter DATA_BITS = 8;
   parameter BAUD = 19200;
   parameter CLK_RATE = 100000000;
   localparam CLK_DIV = CLK_RATE / BAUD;
   reg [$clog2(CLK_DIV)-1:0] baud_counter = 0;


   `define STATE_IDLE      0
   `define STATE_WAIT_HALF 1
   `define STATE_RX        2
   `define STATE_END       3
   reg [1:0] state = `STATE_IDLE;
   reg rx_reg = 1;
   assign uart_state = state;
   reg [$clog2(DATA_BITS)-1:0] rx_counter = 0;
   always @ (posedge clk) begin
      rx_reg <= rx;
      if (rst) begin
         state <= `STATE_IDLE;
         busy <= 0;
      end else begin
         case (state)
           `STATE_IDLE: begin
              if (~rx_reg) begin
                 busy <= 1;
                 state <= `STATE_WAIT_HALF;
                 baud_counter <= 0;
                 rx_counter <= 0;
              end
           end
           `STATE_WAIT_HALF: begin
              if (baud_counter == (CLK_DIV / 2) - 1) begin
                 state <= `STATE_RX;
                 baud_counter <= 0;
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
           `STATE_RX: begin
              if (baud_counter == CLK_DIV - 1) begin
                 data <= { rx_reg, data[7:1] };
                 baud_counter <= 0;
                 if (rx_counter == DATA_BITS - 1) begin
                    state <= `STATE_END;
                 end else begin
                    rx_counter <= rx_counter + 1;
                 end
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
           `STATE_END: begin
              if (baud_counter == CLK_DIV - 1) begin
                 state <= `STATE_IDLE;
                 busy <= 0;
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
         endcase
      end
   end

endmodule
module uart
  (
   input                      clk,
   input                      rst,
   input                      rx,
   output reg                 busy,
   output reg [DATA_BITS-1:0] data
   );


   initial begin
      busy = 0;
      data = 0;
   end


   parameter DATA_BITS = 8;
   parameter BAUD = 19200;
   parameter CLK_RATE = 100000000;
   localparam CLK_DIV = CLK_RATE / BAUD;
   reg [$clog2(CLK_DIV)-1:0] baud_counter = 0;


   `define STATE_IDLE      0
   `define STATE_WAIT_HALF 1
   `define STATE_RX        2
   `define STATE_END       3
   reg [1:0] state = `STATE_IDLE;
   reg rx_reg = 1;
   assign uart_state = state;
   reg [$clog2(DATA_BITS)-1:0] rx_counter = 0;
   always @ (posedge clk) begin
      rx_reg <= rx;
      if (rst) begin
         state <= `STATE_IDLE;
         busy <= 0;
      end else begin
         case (state)
           `STATE_IDLE: begin
              if (~rx_reg) begin
                 busy <= 1;
                 state <= `STATE_WAIT_HALF;
                 baud_counter <= 0;
                 rx_counter <= 0;
              end
           end
           `STATE_WAIT_HALF: begin
              if (baud_counter == (CLK_DIV / 2) - 1) begin
                 state <= `STATE_RX;
                 baud_counter <= 0;
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
           `STATE_RX: begin
              if (baud_counter == CLK_DIV - 1) begin
                 data <= { rx_reg, data[7:1] };
                 baud_counter <= 0;
                 if (rx_counter == DATA_BITS - 1) begin
                    state <= `STATE_END;
                 end else begin
                    rx_counter <= rx_counter + 1;
                 end
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
           `STATE_END: begin
              if (baud_counter == CLK_DIV - 1) begin
                 state <= `STATE_IDLE;
                 busy <= 0;
              end else begin
                 baud_counter <= baud_counter + 1;
              end
           end
         endcase
      end
   end

endmodule