data/full_repos/permissive/449521261/parallel_to_UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:216: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            end else if(clock_divider == max_counter) begin\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:214: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            if(clock_divider == max_counter/2) begin\n                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module data_latch(
    input clock,
    input reset,
    input enable,
    input [7:0] data_input,
    output reg [7:0] data_output
    );

    always @ (posedge clock or posedge reset) begin
        if(reset == 'b1) begin
            data_output <= 'b0;
        end else if(enable == 'b1) begin
            data_output <= data_input;
        end
    end
endmodule
module data_latch(
    input clock,
    input reset,
    input enable,
    input [7:0] data_input,
    output reg [7:0] data_output
    );


    always @ (posedge clock or posedge reset) begin
        if(reset == 'b1) begin
            data_output <= 'b0;
        end else if(enable == 'b1) begin
            data_output <= data_input;
        end
    end
endmodule