data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module halfsub(a,b,s0,s1);
	input a,b;
	output s0,s1;
	reg s0,s1;
	wire nota,notb,and1,and2;
	
	not NOT1(nota,a);
	not NOT2(notb,b);
	and AND1(and1,nota,b);
	and AND2(and2,a,notb);
	s1 = and1;
	or OR(s0,and1,and2);
endmodule
module halfsub(a,b,s0,s1);

	input a,b;
	output s0,s1;
	reg s0,s1;
	wire nota,notb,and1,and2;
	
	not NOT1(nota,a);
	not NOT2(notb,b);
	and AND1(and1,nota,b);
	and AND2(and2,a,notb);
	s1 = and1;
	or OR(s0,and1,and2);
endmodule