data/full_repos/permissive/491135068/DFF3.v
data/verilator_xmls/2e68568b-5a6a-4765-8c2e-41b35851c6bf.xml
module DFF3(DFFIN3, DFFOUT3, clk);
    input [2:0] DFFIN3; 
    input clk;
    output reg [2:0] DFFOUT3;

    always @(posedge clk) begin
        DFFOUT3 = DFFIN3;
    end
endmodule
module DFF3(DFFIN3, DFFOUT3, clk);

    input [2:0] DFFIN3; 
    input clk;
    output reg [2:0] DFFOUT3;

    always @(posedge clk) begin
        DFFOUT3 = DFFIN3;
    end
endmodule