data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim/tb_soc.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim/tb_soc.sv:6: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;   \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim/tb_soc.sv:22: Unsupported: Ignoring delay on this delayed statement.\ninitial #800000 $stop;\n        ^\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim/tb_soc.sv:11: Cannot find file containing module: \'soc_top\'\nsoc_top soc_inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim,data/full_repos/permissive/435890256/soc_top\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim,data/full_repos/permissive/435890256/soc_top.v\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Simulation_SoC/Questsim,data/full_repos/permissive/435890256/soc_top.sv\n             soc_top\n             soc_top.v\n             soc_top.sv\n             obj_dir/soc_top\n             obj_dir/soc_top.v\n             obj_dir/soc_top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_soc();

logic clk = 1'b1;
always #5 clk = ~clk;

wire uart_tx, vga_hsync, vga_vsync;
wire [ 2:0] vga_pixel;

soc_top soc_inst(
    .clk              ( clk          ),
    .isp_uart_rx      ( 1'b1         ),
    .isp_uart_tx      ( uart_tx      ),
    .vga_hsync        ( vga_hsync    ),
    .vga_vsync        ( vga_vsync    ),
    .vga_red          ( vga_pixel[2] ),
    .vga_green        ( vga_pixel[1] ),
    .vga_blue         ( vga_pixel[0] )
);

initial #800000 $stop;

endmodule
module tb_soc();


logic clk = 1'b1;
always #5 clk = ~clk;

wire uart_tx, vga_hsync, vga_vsync;
wire [ 2:0] vga_pixel;

soc_top soc_inst(
    .clk              ( clk          ),
    .isp_uart_rx      ( 1'b1         ),
    .isp_uart_tx      ( uart_tx      ),
    .vga_hsync        ( vga_hsync    ),
    .vga_vsync        ( vga_vsync    ),
    .vga_red          ( vga_pixel[2] ),
    .vga_green        ( vga_pixel[1] ),
    .vga_blue         ( vga_pixel[0] )
);

initial #800000 $stop;

endmodule