data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/pcLogic.v
data/verilator_xmls/5ef7620c-14cb-4e5b-aed0-aa147fef973f.xml
module pcLogic (
  input             clk, reset,
  input      [31:0] PCIn,
  output reg [31:0] PCOut
);



always @(posedge clk or posedge reset)
  if (reset) PCOut <= 32'b0;
  else       PCOut <= PCIn;

endmodule
module pcLogic (
  input             clk, reset,
  input      [31:0] PCIn,
  output reg [31:0] PCOut
);




always @(posedge clk or posedge reset)
  if (reset) PCOut <= 32'b0;
  else       PCOut <= PCIn;

endmodule