data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do    (ram_rdat)\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: syntax error, unexpected '(', expecting ')'\n     .do    (ram_rdat)\n             ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ippcsge_cpuadap
    (

     syclk,
     syrst_,
     syupen,
     syupa,
     syuprs,
     syupws,
     syupdi,
     syupdo,
     syuprdy,


     rxclk,
     rxrst_,
     rxupen,
     rxupa,
     rxuprs,
     rxupws,
     rxupdi,
     rxupdo,
     rxuprdy
     );



parameter           CPUA = 6;
parameter           CPUD = 16;





input               syclk;
input               syrst_;
input               syupen;
input [CPUA-1:0]    syupa;
input               syuprs;
input               syupws;
input [CPUD-1:0]    syupdi;
output [CPUD-1:0]   syupdo;
output              syuprdy;


input               rxclk;
input               rxrst_;
output              rxupen;
output [CPUA-1:0]   rxupa;
output              rxuprs;
output              rxupws;
output [CPUD-1:0]   rxupdi;
input [CPUD-1:0]    rxupdo;
input               rxuprdy;







assign      rxupdi  = syupdi;
assign      rxupen  = syupen;
assign      rxupa   = syupa;


wire [2:0]  uprssamp;
fflopx #(3) iflrxuprs (rxclk, rxrst_, {uprssamp [1:0], syuprs}, {uprssamp [2:0]});
assign      rxuprs = (~uprssamp [2]) & uprssamp [1];


wire [2:0]  upwssamp;
fflopx #(3) iflrxupws (rxclk, rxrst_, {upwssamp [1:0], syupws}, {upwssamp [2:0]});
assign      rxupws = (~upwssamp [2]) & upwssamp [1];


wire        rxuprdy_stress;
wire        rxuprdy1;

fflopx #(2) iflrxuprdy (rxclk, rxrst_, {(rxuprdy | rxuprdy1), rxuprdy}, {rxuprdy_stress, rxuprdy1});

wire [2:0]  uprdysamp;
fflopx #(3) iflpruprdy (syclk, syrst_, {uprdysamp [1:0], rxuprdy_stress}, {uprdysamp [2:0]});

wire        preuprdy;
assign      preuprdy = (~uprdysamp [2]) & uprdysamp [1];

fflopx #(1) iflsuprdy (syclk, syrst_, preuprdy, syuprdy);


wire [CPUD-1:0] rxupdo_l;
fflopxe #(CPUD) iflrxupdo (rxclk, rxrst_, rxuprdy, rxupdo, rxupdo_l);

assign          syupdo = syupen ? rxupdo_l : {CPUD{1'b0}};


endmodule
module ippcsge_cpuadap
    (

     syclk,
     syrst_,
     syupen,
     syupa,
     syuprs,
     syupws,
     syupdi,
     syupdo,
     syuprdy,


     rxclk,
     rxrst_,
     rxupen,
     rxupa,
     rxuprs,
     rxupws,
     rxupdi,
     rxupdo,
     rxuprdy
     );




parameter           CPUA = 6;
parameter           CPUD = 16;





input               syclk;
input               syrst_;
input               syupen;
input [CPUA-1:0]    syupa;
input               syuprs;
input               syupws;
input [CPUD-1:0]    syupdi;
output [CPUD-1:0]   syupdo;
output              syuprdy;


input               rxclk;
input               rxrst_;
output              rxupen;
output [CPUA-1:0]   rxupa;
output              rxuprs;
output              rxupws;
output [CPUD-1:0]   rxupdi;
input [CPUD-1:0]    rxupdo;
input               rxuprdy;







assign      rxupdi  = syupdi;
assign      rxupen  = syupen;
assign      rxupa   = syupa;


wire [2:0]  uprssamp;
fflopx #(3) iflrxuprs (rxclk, rxrst_, {uprssamp [1:0], syuprs}, {uprssamp [2:0]});
assign      rxuprs = (~uprssamp [2]) & uprssamp [1];


wire [2:0]  upwssamp;
fflopx #(3) iflrxupws (rxclk, rxrst_, {upwssamp [1:0], syupws}, {upwssamp [2:0]});
assign      rxupws = (~upwssamp [2]) & upwssamp [1];


wire        rxuprdy_stress;
wire        rxuprdy1;

fflopx #(2) iflrxuprdy (rxclk, rxrst_, {(rxuprdy | rxuprdy1), rxuprdy}, {rxuprdy_stress, rxuprdy1});

wire [2:0]  uprdysamp;
fflopx #(3) iflpruprdy (syclk, syrst_, {uprdysamp [1:0], rxuprdy_stress}, {uprdysamp [2:0]});

wire        preuprdy;
assign      preuprdy = (~uprdysamp [2]) & uprdysamp [1];

fflopx #(1) iflsuprdy (syclk, syrst_, preuprdy, syuprdy);


wire [CPUD-1:0] rxupdo_l;
fflopxe #(CPUD) iflrxupdo (rxclk, rxrst_, rxuprdy, rxupdo, rxupdo_l);

assign          syupdo = syupen ? rxupdo_l : {CPUD{1'b0}};


endmodule