data/full_repos/permissive/436037353/src/LinkRegister.v
data/verilator_xmls/32793734-2696-4f0d-81ab-55035bacb664.xml
module LinkRegister(
	clock,
	ea,
	PCRegIncreament,
	branchControl,
	brx,
	zero,
	negative,
	linkRegOut);
	
	input 				clock;
	input [7:0]			ea;
	input [7:0] 		PCRegIncreament;
	input [1:0]			branchControl;
	input					brx;
	input					zero;
	input					negative;
	
	output reg [7:0]	linkRegOut;
	
	reg [7:0]			linkReg;
	

	wire compare;
	assign compare = (brx) ? zero : negative;
	
	
	always@(*) begin
	
		case(branchControl)
		
			2'b00:
				begin
				
					linkRegOut = ea;
					
				end
				
			2'b01:
				begin
				
					if (compare) begin
					
						linkRegOut = ea;
					
					end
					else begin
					
						linkRegOut = PCRegIncreament;
					
					end
				
				end
			
			2'b10:
				begin
				
					linkRegOut = ea;
				
				end
			
			2'b11:
				begin
				
					linkRegOut = linkReg;
					
				
				end
		endcase	
	end
	
	always@(posedge clock) begin
	
		case(branchControl)
			2'b10:
				begin
				
					linkReg = PCRegIncreament;
				
				end
		endcase	
	end

endmodule
module LinkRegister(
	clock,
	ea,
	PCRegIncreament,
	branchControl,
	brx,
	zero,
	negative,
	linkRegOut);

	
	input 				clock;
	input [7:0]			ea;
	input [7:0] 		PCRegIncreament;
	input [1:0]			branchControl;
	input					brx;
	input					zero;
	input					negative;
	
	output reg [7:0]	linkRegOut;
	
	reg [7:0]			linkReg;
	

	wire compare;
	assign compare = (brx) ? zero : negative;
	
	
	always@(*) begin
	
		case(branchControl)
		
			2'b00:
				begin
				
					linkRegOut = ea;
					
				end
				
			2'b01:
				begin
				
					if (compare) begin
					
						linkRegOut = ea;
					
					end
					else begin
					
						linkRegOut = PCRegIncreament;
					
					end
				
				end
			
			2'b10:
				begin
				
					linkRegOut = ea;
				
				end
			
			2'b11:
				begin
				
					linkRegOut = linkReg;
					
				
				end
		endcase	
	end
	
	always@(posedge clock) begin
	
		case(branchControl)
			2'b10:
				begin
				
					linkReg = PCRegIncreament;
				
				end
		endcase	
	end

endmodule