data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:61: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:61: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:61: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:61: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:86: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:86: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:86: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv:86: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_stim_sine_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Error: Exiting due to 8 warning(s)\n'
module wfg_stim_sine_wishbone_reg #(
    parameter int BUSW = 32
) (

    input                       wb_clk_i,
    input                       wb_rst_i,
    input                       wbs_stb_i,
    input                       wbs_cyc_i,
    input                       wbs_we_i,
    input        [(BUSW/8-1):0] wbs_sel_i,
    input        [  (BUSW-1):0] wbs_dat_i,
    input        [  (BUSW-1):0] wbs_adr_i,
    output logic                wbs_ack_o,
    output logic [  (BUSW-1):0] wbs_dat_o,







    output logic        ctrl_en_q_o,
    output logic [15:0] gain_val_q_o,
    output logic [15:0] inc_val_q_o,
    output logic [17:0] offset_val_q_o


);






    logic         ctrl_en_ff;
    logic [15: 0] gain_val_ff;
    logic [15: 0] inc_val_ff;
    logic [17: 0] offset_val_ff;




    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin





            ctrl_en_ff    <= 1'b0;
            gain_val_ff   <= 16'h4000;
            inc_val_ff    <= 16'h1000;
            offset_val_ff <= 18'h0000;


        end else if (wbs_stb_i && wbs_we_i && wbs_cyc_i) begin
            case (wbs_adr_i)





                4'h0:       ctrl_en_ff               <= wbs_dat_i[ 0: 0];
                4'h8:       gain_val_ff              <= wbs_dat_i[15: 0];
                4'h4:       inc_val_ff               <= wbs_dat_i[15: 0];
                4'hC:       offset_val_ff            <= wbs_dat_i[17: 0];


                default: begin
                end
            endcase
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin
            wbs_dat_o <= '0;
        end else begin
            if (wbs_stb_i && !wbs_we_i && wbs_cyc_i) begin
                wbs_dat_o <= '0;
                case (wbs_adr_i)





                    4'h0:       wbs_dat_o[ 0: 0] <= ctrl_en_ff;
                    4'h8:       wbs_dat_o[15: 0] <= gain_val_ff;
                    4'h4:       wbs_dat_o[15: 0] <= inc_val_ff;
                    4'hC:       wbs_dat_o[17: 0] <= offset_val_ff;


                    default:    wbs_dat_o <= 'X;
                endcase
            end
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) wbs_ack_o <= 1'b0;
        else wbs_ack_o <= wbs_stb_i && wbs_cyc_i & !wbs_ack_o;
    end






    assign ctrl_en_q_o    = ctrl_en_ff;
    assign gain_val_q_o   = gain_val_ff;
    assign inc_val_q_o    = inc_val_ff;
    assign offset_val_q_o = offset_val_ff;


endmodule
module wfg_stim_sine_wishbone_reg #(
    parameter int BUSW = 32
) (

    input                       wb_clk_i,
    input                       wb_rst_i,
    input                       wbs_stb_i,
    input                       wbs_cyc_i,
    input                       wbs_we_i,
    input        [(BUSW/8-1):0] wbs_sel_i,
    input        [  (BUSW-1):0] wbs_dat_i,
    input        [  (BUSW-1):0] wbs_adr_i,
    output logic                wbs_ack_o,
    output logic [  (BUSW-1):0] wbs_dat_o,







    output logic        ctrl_en_q_o,
    output logic [15:0] gain_val_q_o,
    output logic [15:0] inc_val_q_o,
    output logic [17:0] offset_val_q_o


);







    logic         ctrl_en_ff;
    logic [15: 0] gain_val_ff;
    logic [15: 0] inc_val_ff;
    logic [17: 0] offset_val_ff;




    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin





            ctrl_en_ff    <= 1'b0;
            gain_val_ff   <= 16'h4000;
            inc_val_ff    <= 16'h1000;
            offset_val_ff <= 18'h0000;


        end else if (wbs_stb_i && wbs_we_i && wbs_cyc_i) begin
            case (wbs_adr_i)





                4'h0:       ctrl_en_ff               <= wbs_dat_i[ 0: 0];
                4'h8:       gain_val_ff              <= wbs_dat_i[15: 0];
                4'h4:       inc_val_ff               <= wbs_dat_i[15: 0];
                4'hC:       offset_val_ff            <= wbs_dat_i[17: 0];


                default: begin
                end
            endcase
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin
            wbs_dat_o <= '0;
        end else begin
            if (wbs_stb_i && !wbs_we_i && wbs_cyc_i) begin
                wbs_dat_o <= '0;
                case (wbs_adr_i)





                    4'h0:       wbs_dat_o[ 0: 0] <= ctrl_en_ff;
                    4'h8:       wbs_dat_o[15: 0] <= gain_val_ff;
                    4'h4:       wbs_dat_o[15: 0] <= inc_val_ff;
                    4'hC:       wbs_dat_o[17: 0] <= offset_val_ff;


                    default:    wbs_dat_o <= 'X;
                endcase
            end
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) wbs_ack_o <= 1'b0;
        else wbs_ack_o <= wbs_stb_i && wbs_cyc_i & !wbs_ack_o;
    end






    assign ctrl_en_q_o    = ctrl_en_ff;
    assign gain_val_q_o   = gain_val_ff;
    assign inc_val_q_o    = inc_val_ff;
    assign offset_val_q_o = offset_val_ff;


endmodule