data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:81: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock =~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #50 hit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #50 branchTarget = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #50 zeroFlag = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #50 ALUResult = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #50 readData2 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #50 writeReg = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #50 MemRead = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #50 MemWrite = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #50 Branch = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #50 RegWrite = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #50 MemToReg = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/EM_MEM_Register_TEST.v:55: Cannot find file containing module: \'EM_MEM_Register\'\n EM_MEM_Register uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/EM_MEM_Register\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/EM_MEM_Register.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/EM_MEM_Register.sv\n             EM_MEM_Register\n             EM_MEM_Register.v\n             EM_MEM_Register.sv\n             obj_dir/EM_MEM_Register\n             obj_dir/EM_MEM_Register.v\n             obj_dir/EM_MEM_Register.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module EM_MEM_Register_TEST;


	reg clock;
	reg hit;
	reg [31:0] branchTarget;
	reg zeroFlag;
	reg [31:0] ALUResult;
	reg [31:0] readData2;
	reg [4:0] writeReg;
	reg MemRead;
	reg MemWrite;
	reg Branch;
	reg RegWrite;
	reg MemToReg;


	wire [31:0] branchTargetOut;
	wire zeroFlagOut;
	wire [31:0] ALUResultOut;
	wire [31:0] readData2Out;
	wire [4:0] writeRegOut;
	wire MemReadOut;
	wire MemWriteOut;
	wire BranchOut;
	wire RegWriteOut;
	wire MemToRegOut;
	wire hitOut;


	EM_MEM_Register uut (
		.clock(clock), 
		.hit(hit), 
		.branchTarget(branchTarget), 
		.zeroFlag(zeroFlag), 
		.ALUResult(ALUResult), 
		.readData2(readData2), 
		.writeReg(writeReg), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.Branch(Branch), 
		.RegWrite(RegWrite), 
		.MemToReg(MemToReg), 
		.branchTargetOut(branchTargetOut), 
		.zeroFlagOut(zeroFlagOut), 
		.ALUResultOut(ALUResultOut), 
		.readData2Out(readData2Out), 
		.writeRegOut(writeRegOut), 
		.MemReadOut(MemReadOut), 
		.MemWriteOut(MemWriteOut), 
		.BranchOut(BranchOut), 
		.RegWriteOut(RegWriteOut), 
		.MemToRegOut(MemToRegOut), 
		.hitOut(hitOut)
	);

	always #20 clock =~clock;
	initial begin

		clock = 0;
		hit = 0;
		branchTarget = 0;
		zeroFlag = 0;
		ALUResult = 0;
		readData2 = 0;
		writeReg = 0;
		MemRead = 0;
		MemWrite = 0;
		Branch = 0;
		RegWrite = 0;
		MemToReg = 0;

		#50 hit = 1;
		#50 branchTarget = 0;
		#50 zeroFlag = 0;
		#50 ALUResult = 0;
		#50 readData2 = 0;
		#50 writeReg = 0;
		#50 MemRead = 0;
		#50 MemWrite = 0;
		#50 Branch = 0;
		#50 RegWrite = 0;
		#50 MemToReg = 0;

		#100;
        


	end
      
endmodule
module EM_MEM_Register_TEST;



	reg clock;
	reg hit;
	reg [31:0] branchTarget;
	reg zeroFlag;
	reg [31:0] ALUResult;
	reg [31:0] readData2;
	reg [4:0] writeReg;
	reg MemRead;
	reg MemWrite;
	reg Branch;
	reg RegWrite;
	reg MemToReg;


	wire [31:0] branchTargetOut;
	wire zeroFlagOut;
	wire [31:0] ALUResultOut;
	wire [31:0] readData2Out;
	wire [4:0] writeRegOut;
	wire MemReadOut;
	wire MemWriteOut;
	wire BranchOut;
	wire RegWriteOut;
	wire MemToRegOut;
	wire hitOut;


	EM_MEM_Register uut (
		.clock(clock), 
		.hit(hit), 
		.branchTarget(branchTarget), 
		.zeroFlag(zeroFlag), 
		.ALUResult(ALUResult), 
		.readData2(readData2), 
		.writeReg(writeReg), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.Branch(Branch), 
		.RegWrite(RegWrite), 
		.MemToReg(MemToReg), 
		.branchTargetOut(branchTargetOut), 
		.zeroFlagOut(zeroFlagOut), 
		.ALUResultOut(ALUResultOut), 
		.readData2Out(readData2Out), 
		.writeRegOut(writeRegOut), 
		.MemReadOut(MemReadOut), 
		.MemWriteOut(MemWriteOut), 
		.BranchOut(BranchOut), 
		.RegWriteOut(RegWriteOut), 
		.MemToRegOut(MemToRegOut), 
		.hitOut(hitOut)
	);

	always #20 clock =~clock;
	initial begin

		clock = 0;
		hit = 0;
		branchTarget = 0;
		zeroFlag = 0;
		ALUResult = 0;
		readData2 = 0;
		writeReg = 0;
		MemRead = 0;
		MemWrite = 0;
		Branch = 0;
		RegWrite = 0;
		MemToReg = 0;

		#50 hit = 1;
		#50 branchTarget = 0;
		#50 zeroFlag = 0;
		#50 ALUResult = 0;
		#50 readData2 = 0;
		#50 writeReg = 0;
		#50 MemRead = 0;
		#50 MemWrite = 0;
		#50 Branch = 0;
		#50 RegWrite = 0;
		#50 MemToReg = 0;

		#100;
        


	end
      
endmodule