data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/PEDC_STATEMACHINE.v
data/verilator_xmls/5013878b-2636-426a-af79-02cb24833909.xml
module PEDC_STATEMACHINE(


PEDC_STATEMACHINE_Clk,
PEDC_STATEMACHINE_Start_Routine,
PEDC_STATEMACHINE_Stop_Routine,


PEDC_STATEMACHINE_Reset,
PEDC_STATEMACHINE_Set_Signal_En
);




localparam State_reset			= 0;
localparam State_started		= 1;





input PEDC_STATEMACHINE_Clk;
input PEDC_STATEMACHINE_Start_Routine;
input PEDC_STATEMACHINE_Stop_Routine;
output reg PEDC_STATEMACHINE_Reset;
output reg PEDC_STATEMACHINE_Set_Signal_En;





reg [1:0]State_Register;
reg [1:0]State_Signal;



always @(*)
begin
	case (State_Register)
		State_reset: if(PEDC_STATEMACHINE_Start_Routine)
							State_Signal=State_started;
						 else
							State_Signal=State_reset;
		
		State_started: if (PEDC_STATEMACHINE_Stop_Routine) 
								State_Signal=State_reset;
							else 
								State_Signal=State_started;
		
		default: State_Signal=State_reset;
	
	endcase
	
	
end



always @ (negedge PEDC_STATEMACHINE_Clk )
begin
		State_Register <= State_Signal;
end


always @ (*)
begin
	
	case(State_Register)
		State_reset:
		begin
			PEDC_STATEMACHINE_Reset=0;
			PEDC_STATEMACHINE_Set_Signal_En=0;
		end
		
		State_started:
		begin
			PEDC_STATEMACHINE_Reset=1;
			PEDC_STATEMACHINE_Set_Signal_En=1;
		
		end
		
		default:
		begin	
			PEDC_STATEMACHINE_Reset=0;
			PEDC_STATEMACHINE_Set_Signal_En=0;
		end
	
	endcase
	
end


endmodule
module PEDC_STATEMACHINE(


PEDC_STATEMACHINE_Clk,
PEDC_STATEMACHINE_Start_Routine,
PEDC_STATEMACHINE_Stop_Routine,


PEDC_STATEMACHINE_Reset,
PEDC_STATEMACHINE_Set_Signal_En
);





localparam State_reset			= 0;
localparam State_started		= 1;





input PEDC_STATEMACHINE_Clk;
input PEDC_STATEMACHINE_Start_Routine;
input PEDC_STATEMACHINE_Stop_Routine;
output reg PEDC_STATEMACHINE_Reset;
output reg PEDC_STATEMACHINE_Set_Signal_En;





reg [1:0]State_Register;
reg [1:0]State_Signal;



always @(*)
begin
	case (State_Register)
		State_reset: if(PEDC_STATEMACHINE_Start_Routine)
							State_Signal=State_started;
						 else
							State_Signal=State_reset;
		
		State_started: if (PEDC_STATEMACHINE_Stop_Routine) 
								State_Signal=State_reset;
							else 
								State_Signal=State_started;
		
		default: State_Signal=State_reset;
	
	endcase
	
	
end



always @ (negedge PEDC_STATEMACHINE_Clk )
begin
		State_Register <= State_Signal;
end


always @ (*)
begin
	
	case(State_Register)
		State_reset:
		begin
			PEDC_STATEMACHINE_Reset=0;
			PEDC_STATEMACHINE_Set_Signal_En=0;
		end
		
		State_started:
		begin
			PEDC_STATEMACHINE_Reset=1;
			PEDC_STATEMACHINE_Set_Signal_En=1;
		
		end
		
		default:
		begin	
			PEDC_STATEMACHINE_Reset=0;
			PEDC_STATEMACHINE_Set_Signal_En=0;
		end
	
	endcase
	
end


endmodule