data/full_repos/permissive/419538859/lab7/lab7_2/lab7_2.v
1: b"%Error: data/full_repos/permissive/419538859/lab7/lab7_2/lab7_2.v:23: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(23)(clk, reset, clk_cnt);\n               ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_2/lab7_2.v:24: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(15)(clk, reset, clk_sel);\n               ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_2/lab7_2.v:27: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select #(4)(clk_sel, reset, seg7_sel);\n                 ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_2/lab7_2.v:39: syntax error, unexpected '(', expecting IDENTIFIER\nryg_ctl (clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);\n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module 	ryg_ctl(clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);

input	clk_cnt, reset, day_night;
input	[7:0]g1_cnt;
output	g1_en;
output	[5:0]light_led;
reg 	g1_en;
reg		[5:0]light_led;
reg		[2:0]mode;
output reg [1:0]light_mode;

always@(posedge clk_cnt or posedge reset) 
begin
	if (reset)
		begin
		light_led	= 6'b001_100;
		mode 		= 3'b0;
		g1_en 		= 1'b0;
		light_mode	= 2'b00;
		end
	else if(day_night == 1'b1)
		case(mode)
		3'd0: 
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b00;
			if(g1_cnt 	== 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		3'd1:
			begin
			{light_led[5],light_led[4],light_led[2],light_led[1],light_led[0]}=5'b00100;
			light_led[3]=~light_led[3];
			g1_en 		= 1'b1;
			light_mode	= 2'b01;
			if (g1_cnt 	== 8'b0000_1000)
				mode 	= mode + 3'b1; 
			end	
		3'd2:
			begin
			light_led	= 6'b010_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b10;
			if(g1_cnt 	== 8'b0000_0010)
				begin
				g1_en 	= 1'b0;
				mode 	= mode + 3'b1;
				light_mode	= 2'b10;				
				end

			end
		3'd3: 
			begin
			light_led	= 6'b100_001;
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if(g1_cnt 	== 8'b0001_0010)
				mode 	= mode+ 3'b1; 
			end

		3'd4:
			begin
			{light_led[5],light_led[4],light_led[3],light_led[2],light_led[1]}=5'b10000;
			light_led[0]= ~light_led[0];
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if (g1_cnt 	== 8'b0000_1000)
				begin 
				mode 	= mode + 3'b1; 
				end

			end
		3'd5:
			begin
			light_led	= 6'b100_010; 
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if(g1_cnt 	== 8'b0000_0010)
				begin
				g1_en 	= 1'b0;
				mode 	= 3'b0;
				light_mode	= 2'b11;				
				end
			end
		default:
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b00;
			if(g1_cnt 	== 8'b0000_1001)
				mode 	= mode + 3'b1; 
			end
		endcase

	else if(day_night == 1'b0)
		begin

		{light_led[0],light_led[2],light_led[3],light_led[5]}=4'b0000;
		{light_led[1],light_led[4]}=~{light_led[1],light_led[4]};
		g1_en			=	1'b0;
		light_mode		= 	2'b11;
		mode			=	3'd0;
		end
end
endmodule
module 	ryg_ctl(clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);


input	clk_cnt, reset, day_night;
input	[7:0]g1_cnt;
output	g1_en;
output	[5:0]light_led;
reg 	g1_en;
reg		[5:0]light_led;
reg		[2:0]mode;
output reg [1:0]light_mode;

always@(posedge clk_cnt or posedge reset) 
begin
	if (reset)
		begin
		light_led	= 6'b001_100;
		mode 		= 3'b0;
		g1_en 		= 1'b0;
		light_mode	= 2'b00;
		end
	else if(day_night == 1'b1)
		case(mode)
		3'd0: 
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b00;
			if(g1_cnt 	== 8'b0001_0010)
				mode 	= mode + 3'b1; 
			end
		3'd1:
			begin
			{light_led[5],light_led[4],light_led[2],light_led[1],light_led[0]}=5'b00100;
			light_led[3]=~light_led[3];
			g1_en 		= 1'b1;
			light_mode	= 2'b01;
			if (g1_cnt 	== 8'b0000_1000)
				mode 	= mode + 3'b1; 
			end	
		3'd2:
			begin
			light_led	= 6'b010_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b10;
			if(g1_cnt 	== 8'b0000_0010)
				begin
				g1_en 	= 1'b0;
				mode 	= mode + 3'b1;
				light_mode	= 2'b10;				
				end

			end
		3'd3: 
			begin
			light_led	= 6'b100_001;
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if(g1_cnt 	== 8'b0001_0010)
				mode 	= mode+ 3'b1; 
			end

		3'd4:
			begin
			{light_led[5],light_led[4],light_led[3],light_led[2],light_led[1]}=5'b10000;
			light_led[0]= ~light_led[0];
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if (g1_cnt 	== 8'b0000_1000)
				begin 
				mode 	= mode + 3'b1; 
				end

			end
		3'd5:
			begin
			light_led	= 6'b100_010; 
			g1_en 		= 1'b1;
			light_mode	= 2'b11;
			if(g1_cnt 	== 8'b0000_0010)
				begin
				g1_en 	= 1'b0;
				mode 	= 3'b0;
				light_mode	= 2'b11;				
				end
			end
		default:
			begin
			light_led	= 6'b001_100;
			g1_en 		= 1'b1;
			light_mode	= 2'b00;
			if(g1_cnt 	== 8'b0000_1001)
				mode 	= mode + 3'b1; 
			end
		endcase

	else if(day_night == 1'b0)
		begin

		{light_led[0],light_led[2],light_led[3],light_led[5]}=4'b0000;
		{light_led[1],light_led[4]}=~{light_led[1],light_led[4]};
		g1_en			=	1'b0;
		light_mode		= 	2'b11;
		mode			=	3'd0;
		end
end
endmodule