data/full_repos/permissive/447529080/TESTBED.v
1: b'%Error: data/full_repos/permissive/447529080/TESTBED.v:7: Cannot find include file: SP.v\n`include "SP.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447529080,data/full_repos/permissive/447529080/SP.v\n             data/full_repos/permissive/447529080,data/full_repos/permissive/447529080/SP.v.v\n             data/full_repos/permissive/447529080,data/full_repos/permissive/447529080/SP.v.sv\n             SP.v\n             SP.v.v\n             SP.v.sv\n             obj_dir/SP.v\n             obj_dir/SP.v.v\n             obj_dir/SP.v.sv\n%Error: data/full_repos/permissive/447529080/TESTBED.v:8: Cannot find include file: PATTERN.v\n`include "PATTERN.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447529080/TESTBED.v:9: Cannot find include file: PATTERN_p.v\n`include "PATTERN_p.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447529080/TESTBED.v:10: Cannot find include file: MEM.v\n`include "MEM.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/447529080/TESTBED.v:20: Unsupported or unknown PLI call: $fsdbDumpfile\n    $fsdbDumpfile("SP.fsdb");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447529080/TESTBED.v:21: Unsupported or unknown PLI call: $fsdbDumpvars\n    $fsdbDumpvars(0,"+mda");\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module TESTBED;


wire clk,rst_n,in_valid,out_valid,mem_wen;
wire [11:0] mem_addr;
wire [31:0] inst,mem_dout,inst_addr,mem_din;

initial begin
    $fsdbDumpfile("SP.fsdb");
    $fsdbDumpvars(0,"+mda");
end

SP My_SP(
    .clk(clk),
    .rst_n(rst_n),
    .in_valid(in_valid),
    .out_valid(out_valid),
    .mem_wen(mem_wen),
    .inst(inst),
    .mem_dout(mem_dout),
    .inst_addr(inst_addr),
    .mem_addr(mem_addr),
    .mem_din(mem_din)
);

MEM My_MEM(
    .Q(mem_dout),
    .CLK(clk),
    .CEN(1'b0),
    .WEN(mem_wen),
    .A(mem_addr),
    .D(mem_din),
    .OEN(1'b0)
);


PATTERN My_PATTERN(
    .clk(clk),
    .rst_n(rst_n),
    .in_valid(in_valid),
    .out_valid(out_valid),
    .inst(inst),
    .inst_addr(inst_addr)
);

endmodule
module TESTBED;



wire clk,rst_n,in_valid,out_valid,mem_wen;
wire [11:0] mem_addr;
wire [31:0] inst,mem_dout,inst_addr,mem_din;

initial begin
    $fsdbDumpfile("SP.fsdb");
    $fsdbDumpvars(0,"+mda");
end

SP My_SP(
    .clk(clk),
    .rst_n(rst_n),
    .in_valid(in_valid),
    .out_valid(out_valid),
    .mem_wen(mem_wen),
    .inst(inst),
    .mem_dout(mem_dout),
    .inst_addr(inst_addr),
    .mem_addr(mem_addr),
    .mem_din(mem_din)
);

MEM My_MEM(
    .Q(mem_dout),
    .CLK(clk),
    .CEN(1'b0),
    .WEN(mem_wen),
    .A(mem_addr),
    .D(mem_din),
    .OEN(1'b0)
);


PATTERN My_PATTERN(
    .clk(clk),
    .rst_n(rst_n),
    .in_valid(in_valid),
    .out_valid(out_valid),
    .inst(inst),
    .inst_addr(inst_addr)
);

endmodule