data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20 clk_o <= ~clk_o;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:59: syntax error, unexpected \'@\'\nbegin @(negedge clk_o); @(posedge clk_o);\n      ^\n%Error: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:88: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:89: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:93: syntax error, unexpected \'@\'\n @(posedge clk_o);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:116: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:134: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:152: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:170: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:187: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:205: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:223: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/49387115/bench/verilog/GPIA_BYTE.v:241: Unsupported: Ignoring delay on this delayed statement.\n #2;  \n ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg clk_o;
reg rst_o;
reg [7:0] scenario_o;
reg [1:0] mode_o;
reg [7:0] d_o;
reg stb_o;

wire [7:0] q_i;



GPIA_BYTE dut (
	.clk_i(clk_o),
	.res_i(rst_o),
	.mode_i(mode_o),
	.d_i(d_o),
	.stb_i(stb_o),
	.q_o(q_i)
);



always begin
	#20 clk_o <= ~clk_o;
end



task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask



task setq;
begin
	rst_o <= 0;
	mode_o <= 0;
	d_o <= 8'hFF;
	stb_o <= 1;
	waitclk;
end
endtask



initial begin
	clk_o <= 0;
	rst_o <= 0;
	scenario_o <= 8'h00;
	mode_o <= 0;
	d_o <= 0;
	stb_o <= 0;

	$dumpfile("test.vcd");
	$dumpvars;



	@(posedge clk_o);
	scenario_o <= 8'h01;
	rst_o <= 1;
	waitclk;
	rst_o <= 0;
	waitclk;
	if(q_i == 1) begin
		$display("FAIL 01: Q not $00"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h10;
	waitclk;
	rst_o <= 0;
	mode_o <= 0;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 10: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h14;
	waitclk;
	rst_o <= 0;
	mode_o <= 1;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 14: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h18;
	waitclk;
	rst_o <= 0;
	mode_o <= 2;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 0) begin
		$display("FAIL 18: Q must remain 0"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h1C;
	waitclk;
	rst_o <= 0;
	mode_o <= 3;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 1C: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h30;
	waitclk;
	setq;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 30: Q must reset to $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h34;
	waitclk;
	setq;
	d_o <= 8'h3C;
	mode_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'hFF) begin
		$display("FAIL 34: Q must remain $FF"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h38;
	waitclk;
	setq;
	mode_o <= 2;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'hC3) begin
		$display("FAIL 38: Q must equal $C3"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h3C;
	waitclk;
	setq;
	mode_o <= 3;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'hC3) begin
		$display("FAIL 3C: Q must equal $C3"); $finish;
	end

	$display("PASS"); $finish;
end

endmodule
module test();


reg clk_o;
reg rst_o;
reg [7:0] scenario_o;
reg [1:0] mode_o;
reg [7:0] d_o;
reg stb_o;

wire [7:0] q_i;



GPIA_BYTE dut (
	.clk_i(clk_o),
	.res_i(rst_o),
	.mode_i(mode_o),
	.d_i(d_o),
	.stb_i(stb_o),
	.q_o(q_i)
);



always begin
	#20 clk_o <= ~clk_o;
end



task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask



task setq;
begin
	rst_o <= 0;
	mode_o <= 0;
	d_o <= 8'hFF;
	stb_o <= 1;
	waitclk;
end
endtask



initial begin
	clk_o <= 0;
	rst_o <= 0;
	scenario_o <= 8'h00;
	mode_o <= 0;
	d_o <= 0;
	stb_o <= 0;

	$dumpfile("test.vcd");
	$dumpvars;



	@(posedge clk_o);
	scenario_o <= 8'h01;
	rst_o <= 1;
	waitclk;
	rst_o <= 0;
	waitclk;
	if(q_i == 1) begin
		$display("FAIL 01: Q not $00"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h10;
	waitclk;
	rst_o <= 0;
	mode_o <= 0;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 10: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h14;
	waitclk;
	rst_o <= 0;
	mode_o <= 1;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 14: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h18;
	waitclk;
	rst_o <= 0;
	mode_o <= 2;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 0) begin
		$display("FAIL 18: Q must remain 0"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h1C;
	waitclk;
	rst_o <= 0;
	mode_o <= 3;
	d_o <= 8'h3C;
	stb_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 1C: Q must equal $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h30;
	waitclk;
	setq;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'h3C) begin
		$display("FAIL 30: Q must reset to $3C"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h34;
	waitclk;
	setq;
	d_o <= 8'h3C;
	mode_o <= 1;
	waitclk;
	#2;
	if(q_i != 8'hFF) begin
		$display("FAIL 34: Q must remain $FF"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h38;
	waitclk;
	setq;
	mode_o <= 2;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'hC3) begin
		$display("FAIL 38: Q must equal $C3"); $finish;
	end



	waitclk;
	rst_o <= 1;
	scenario_o <= 8'h3C;
	waitclk;
	setq;
	mode_o <= 3;
	d_o <= 8'h3C;
	waitclk;
	#2;
	if(q_i != 8'hC3) begin
		$display("FAIL 3C: Q must equal $C3"); $finish;
	end

	$display("PASS"); $finish;
end

endmodule