data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/updown_counter.v
data/verilator_xmls/1d585302-ebb2-4d8d-b549-bd45f04678e2.xml
module updown_counter(clk, dir_up, clear, count);

input clk, dir_up, clear;
output reg [2:0] count;

always @(posedge clk or posedge clear)
	begin
		if(clear==1)
		begin
			count <= 3'b000;
		end
		else
		begin
			if(dir_up)
			begin
			 count <= count + 1;
			end
			else
			begin
			 count <= count - 1;
			end
		end
	end
endmodule
module updown_counter(clk, dir_up, clear, count);


input clk, dir_up, clear;
output reg [2:0] count;

always @(posedge clk or posedge clear)
	begin
		if(clear==1)
		begin
			count <= 3'b000;
		end
		else
		begin
			if(dir_up)
			begin
			 count <= count + 1;
			end
			else
			begin
			 count <= count - 1;
			end
		end
	end
endmodule