data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:76: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/riscv_regress,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504248338/verilog/dv/riscv_regress,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             data/full_repos/permissive/504248338/verilog/dv/riscv_regress,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:77: Cannot find include file: is62wvs1288.v\n`include "is62wvs1288.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:314: Cannot find include file: riscv_runtests.sv\n`include "riscv_runtests.sv" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:537: Cannot find include file: s25fl256s.sv\n`include "s25fl256s.sv" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:153: Unsupported: event data types\n        event                reinit_event;\n        ^~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:202: syntax error, unexpected ->\n      -> reinit_event;\n      ^~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:242: Unsupported: wait statements\n  wait (rst_n == 1);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n  #200; \n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:277: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:281: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:281: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:281: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                        ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:282: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:283: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:288: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:291: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:291: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:291: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:294: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:294: Define or directive not defined: \'`WBHOST_BANK_SEL\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:294: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:295: Define or directive not defined: \'`ADDR_SPACE_QSPI\'\n  wb_user_core_write(`ADDR_SPACE_QSPI+32\'h1000001C,{16\'h0,1\'b0,1\'b0,4\'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4\'b0100});\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:296: Define or directive not defined: \'`ADDR_SPACE_QSPI\'\n  wb_user_core_write(`ADDR_SPACE_QSPI+32\'h10000020,{8\'h0,2\'b00,2\'b00,P_FSM_C,8\'h00,8\'h38});\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:297: Define or directive not defined: \'`ADDR_SPACE_QSPI\'\n  wb_user_core_write(`ADDR_SPACE_QSPI+32\'h10000028,32\'h0);\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:303: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:303: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:303: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:438: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:439: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:446: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:447: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:448: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:456: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:465: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:473: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:474: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:476: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:477: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/riscv_regress/user_risc_regress_tb.v:485: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 34 error(s), 8 warning(s)\n'
module user_risc_regress_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;
	wire        clk;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg         test_fail;
	reg [31:0] read_data;


	int unsigned                f_results;
        int unsigned                f_info;
        
        string                      s_results;
        string                      s_info;
        `ifdef SIGNATURE_OUT
        string                      s_testname;
        bit                         b_single_run_flag;
        `endif


	`ifdef VERILATOR
         logic [255:0]          test_file;
	 logic [255:0]          test_ram_file;
         `else
         string                 test_file;
	 string                 test_ram_file;

         `endif


        event	               reinit_event;
	bit                    test_running;
        int unsigned           tests_passed;
        int unsigned           tests_total;

	logic  [7:0]           tem_mem[0:4095];
	logic  [31:0]          mem_data;


parameter P_FSM_C      = 4'b0000;
parameter P_FSM_CW     = 4'b0001;
parameter P_FSM_CA     = 4'b0010;

parameter P_FSM_CAR    = 4'b0011;
parameter P_FSM_CADR   = 4'b0100;
parameter P_FSM_CAMR   = 4'b0101;
parameter P_FSM_CAMDR  = 4'b0110;

parameter P_FSM_CAW    = 4'b0111;
parameter P_FSM_CADW   = 4'b1000;
parameter P_FSM_CAMW   = 4'b1001;

parameter P_FSM_CDR    = 4'b1010;
parameter P_FSM_CDW    = 4'b1011;
parameter P_FSM_CR     = 4'b1100;

parameter P_MODE_SWITCH_IDLE     = 2'b00;
parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
parameter P_MODE_SWITCH_AT_DATA  = 2'b10;

parameter P_SINGLE = 2'b00;
parameter P_DOUBLE = 2'b01;
parameter P_QUAD   = 2'b10;
parameter P_QDDR   = 2'b11;




	bit [1:0]     rst_cnt;
        bit           rst_init;
	wire          rst_n;


        assign rst_n = &rst_cnt;
	assign wb_rst_i    =  !rst_n;
        
        always_ff @(posedge clk) begin
	if (rst_init)   begin
	     rst_cnt <= '0;
	     -> reinit_event;
	end
            else if (~&rst_cnt) rst_cnt <= rst_cnt + 1'b1;
        end





	always #12.5 clock <= (clock === 1'b0);

	assign clk = clock;

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, user_risc_regress_tb);
	   	$dumpvars(1, user_risc_regress_tb.u_top);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_pinmux);
	   end
       `endif

        integer i;

        always @reinit_event
	begin


		wait (rst_n == 1);



                $write("\033[0;34m---Initializing the SPI Memory with Hexfile: %s\033[0m\n", test_file);
                $readmemh(test_file,u_spi_flash_256mb.Mem);



		$sformat(test_ram_file, "%s.ram",test_file);
                $readmemh(test_ram_file,u_sram.memory);







		#200; 
	        repeat (10) @(posedge clock);
		$display("Monitor: Core reset removal");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
	        repeat (2) @(posedge clock);
		#1;




	        repeat (2) @(posedge clock);
		#1;

                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);





                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);

	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;





`include "riscv_runtests.sv"






user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);


logic [31:0] riscv_dmem_req_cnt;
initial 
begin
   riscv_dmem_req_cnt = 0;
end

always @(posedge u_top.wbd_riscv_dmem_stb_i)
begin
    riscv_dmem_req_cnt = riscv_dmem_req_cnt+1;
    if((riscv_dmem_req_cnt %200) == 0)
	$display("STATUS: Total Dmem Req Cnt: %d ",riscv_dmem_req_cnt);
end


`ifndef GL

    initial begin
    end
`endif    






   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;



     s25fl256s #(.mem_file_name("add.hex"),
	         .otp_file_name("none"),
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );


   wire spiram_csb = io_out[27];

   is62wvs1288 #(.mem_file_name("none"))
	u_sram (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );



task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif


endmodule
module user_risc_regress_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;
	wire        clk;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg         test_fail;
	reg [31:0] read_data;


	int unsigned                f_results;
        int unsigned                f_info;
        
        string                      s_results;
        string                      s_info;
        `ifdef SIGNATURE_OUT
        string                      s_testname;
        bit                         b_single_run_flag;
        `endif


	`ifdef VERILATOR
         logic [255:0]          test_file;
	 logic [255:0]          test_ram_file;
         `else
         string                 test_file;
	 string                 test_ram_file;

         `endif


        event	               reinit_event;
	bit                    test_running;
        int unsigned           tests_passed;
        int unsigned           tests_total;

	logic  [7:0]           tem_mem[0:4095];
	logic  [31:0]          mem_data;


parameter P_FSM_C      = 4'b0000;
parameter P_FSM_CW     = 4'b0001;
parameter P_FSM_CA     = 4'b0010;

parameter P_FSM_CAR    = 4'b0011;
parameter P_FSM_CADR   = 4'b0100;
parameter P_FSM_CAMR   = 4'b0101;
parameter P_FSM_CAMDR  = 4'b0110;

parameter P_FSM_CAW    = 4'b0111;
parameter P_FSM_CADW   = 4'b1000;
parameter P_FSM_CAMW   = 4'b1001;

parameter P_FSM_CDR    = 4'b1010;
parameter P_FSM_CDW    = 4'b1011;
parameter P_FSM_CR     = 4'b1100;

parameter P_MODE_SWITCH_IDLE     = 2'b00;
parameter P_MODE_SWITCH_AT_ADDR  = 2'b01;
parameter P_MODE_SWITCH_AT_DATA  = 2'b10;

parameter P_SINGLE = 2'b00;
parameter P_DOUBLE = 2'b01;
parameter P_QUAD   = 2'b10;
parameter P_QDDR   = 2'b11;




	bit [1:0]     rst_cnt;
        bit           rst_init;
	wire          rst_n;


        assign rst_n = &rst_cnt;
	assign wb_rst_i    =  !rst_n;
        
        always_ff @(posedge clk) begin
	if (rst_init)   begin
	     rst_cnt <= '0;
	     -> reinit_event;
	end
            else if (~&rst_cnt) rst_cnt <= rst_cnt + 1'b1;
        end





	always #12.5 clock <= (clock === 1'b0);

	assign clk = clock;

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, user_risc_regress_tb);
	   	$dumpvars(1, user_risc_regress_tb.u_top);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
	   	$dumpvars(0, user_risc_regress_tb.u_top.u_pinmux);
	   end
       `endif

        integer i;

        always @reinit_event
	begin


		wait (rst_n == 1);



                $write("\033[0;34m---Initializing the SPI Memory with Hexfile: %s\033[0m\n", test_file);
                $readmemh(test_file,u_spi_flash_256mb.Mem);



		$sformat(test_ram_file, "%s.ram",test_file);
                $readmemh(test_ram_file,u_sram.memory);







		#200; 
	        repeat (10) @(posedge clock);
		$display("Monitor: Core reset removal");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
	        repeat (2) @(posedge clock);
		#1;




	        repeat (2) @(posedge clock);
		#1;

                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
		wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);





                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);

	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;





`include "riscv_runtests.sv"






user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);


logic [31:0] riscv_dmem_req_cnt;
initial 
begin
   riscv_dmem_req_cnt = 0;
end

always @(posedge u_top.wbd_riscv_dmem_stb_i)
begin
    riscv_dmem_req_cnt = riscv_dmem_req_cnt+1;
    if((riscv_dmem_req_cnt %200) == 0)
	$display("STATUS: Total Dmem Req Cnt: %d ",riscv_dmem_req_cnt);
end


`ifndef GL

    initial begin
    end
`endif    






   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;



     s25fl256s #(.mem_file_name("add.hex"),
	         .otp_file_name("none"),
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );


   wire spiram_csb = io_out[27];

   is62wvs1288 #(.mem_file_name("none"))
	u_sram (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );



task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif


endmodule