data/full_repos/permissive/433624543/ripple_carry_adder.v
1: b'%Error: data/full_repos/permissive/433624543/ripple_carry_adder.v:1: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433624543,data/full_repos/permissive/433624543/full_adder.v\n             data/full_repos/permissive/433624543,data/full_repos/permissive/433624543/full_adder.v.v\n             data/full_repos/permissive/433624543,data/full_repos/permissive/433624543/full_adder.v.sv\n             full_adder.v\n             full_adder.v.v\n             full_adder.v.sv\n             obj_dir/full_adder.v\n             obj_dir/full_adder.v.v\n             obj_dir/full_adder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ripple_carry_adder 
    #(parameter WIDTH = 4)
    (
        input carry_in,
        input [WIDTH-1:0] a,
        input [WIDTH-1:0] b,
        output [WIDTH-1:0]  sum,
        output carry_out
    );
     
    wire [WIDTH:0]     carry_bits;
    wire [WIDTH-1:0]   sum_bits;
   

    assign carry_bits[0] = carry_in;        
   
    genvar             i;
    generate 
        for (i=0; i<WIDTH; i=i+1) 
        begin
            full_adder full_adder_inst
            ( 
                .a(a[i]),
                .b(b[i]),
                .carry_in(carry_bits[i]),
                .sum(sum_bits[i]),
                .carry_out(carry_bits[i+1])
            );
        end
    endgenerate
   

    assign sum = sum_bits;
    assign carry_out = carry_bits[WIDTH];
 
endmodule
module ripple_carry_adder 
    #(parameter WIDTH = 4)
    (
        input carry_in,
        input [WIDTH-1:0] a,
        input [WIDTH-1:0] b,
        output [WIDTH-1:0]  sum,
        output carry_out
    );

     
    wire [WIDTH:0]     carry_bits;
    wire [WIDTH-1:0]   sum_bits;
   

    assign carry_bits[0] = carry_in;        
   
    genvar             i;
    generate 
        for (i=0; i<WIDTH; i=i+1) 
        begin
            full_adder full_adder_inst
            ( 
                .a(a[i]),
                .b(b[i]),
                .carry_in(carry_bits[i]),
                .sum(sum_bits[i]),
                .carry_out(carry_bits[i+1])
            );
        end
    endgenerate
   

    assign sum = sum_bits;
    assign carry_out = carry_bits[WIDTH];
 
endmodule