data/full_repos/permissive/440081696/uart.v
1: b"%Error: data/full_repos/permissive/440081696/uart.v:34: Cannot find file containing module: 'baud_rate_gen'\nbaud_rate_gen uart_baud(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/baud_rate_gen\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/baud_rate_gen.v\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/baud_rate_gen.sv\n             baud_rate_gen\n             baud_rate_gen.v\n             baud_rate_gen.sv\n             obj_dir/baud_rate_gen\n             obj_dir/baud_rate_gen.v\n             obj_dir/baud_rate_gen.sv\n%Error: data/full_repos/permissive/440081696/uart.v:41: Cannot find file containing module: 'transmitter'\ntransmitter uart_tx(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/440081696/uart.v:51: Cannot find file containing module: 'receiver'\nreceiver uart_rx(\n^~~~~~~~\n%Error: data/full_repos/permissive/440081696/uart.v:60: Cannot find file containing module: 'uart_control'\nuart_control uart_ctl(\n^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module uart(
  input                 clk_50m_i,
  input                 rst_n_i,
  output  wire          uart_tx_o,
  input                 uart_rx_i,

  input         [31:0]  addr_32b_i,
  input                 wren_i,
  input                 rden_i,
  input         [31:0]  din_32b_i,
  output  wire  [31:0]  dout_32b_o,
  output  wire          dout_32b_valid_o,
  output  wire          interrupt_o
);


(* mark_debug = "true"*)wire  rxclk_en, txclk_en;


(* mark_debug = "true"*)wire  uart_dataTx_valid, uart_dataRx_valid;
(* mark_debug = "true"*)wire  [7:0] uart_dataTx, uart_dataRx;
(* mark_debug = "true"*)wire  uart_tx_busy_o;


baud_rate_gen uart_baud(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .rxclk_en_o(rxclk_en),
  .txclk_en_o(txclk_en)
);

transmitter uart_tx(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .din_8b_i(uart_dataTx),
  .wren_i(uart_dataTx_valid),
  .clken_i(txclk_en),
  .tx_o(uart_tx_o),
  .tx_busy_o(uart_tx_busy_o)
);

receiver uart_rx(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .clken_i(rxclk_en),
  .dout_8b_o(uart_dataRx),
  .dout_valid_o(uart_dataRx_valid),
  .rx_i(uart_rx_i)
);

uart_control uart_ctl(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .addr_32b_i(addr_32b_i),
  .wren_i(wren_i),
  .rden_i(rden_i),
  .din_32b_i(din_32b_i),
  .dout_32b_o(dout_32b_o),
  .dout_32b_valid_o(dout_32b_valid_o),
  .interrupt_o(interrupt_o),

  .din_8b_i(uart_dataRx),
  .din_valid_i(uart_dataRx_valid),
  .dout_8b_o(uart_dataTx),
  .dout_valid_o(uart_dataTx_valid),
  .tx_busy_i(uart_tx_busy_o)
);

endmodule
module uart(
  input                 clk_50m_i,
  input                 rst_n_i,
  output  wire          uart_tx_o,
  input                 uart_rx_i,

  input         [31:0]  addr_32b_i,
  input                 wren_i,
  input                 rden_i,
  input         [31:0]  din_32b_i,
  output  wire  [31:0]  dout_32b_o,
  output  wire          dout_32b_valid_o,
  output  wire          interrupt_o
);



(* mark_debug = "true"*)wire  rxclk_en, txclk_en;


(* mark_debug = "true"*)wire  uart_dataTx_valid, uart_dataRx_valid;
(* mark_debug = "true"*)wire  [7:0] uart_dataTx, uart_dataRx;
(* mark_debug = "true"*)wire  uart_tx_busy_o;


baud_rate_gen uart_baud(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .rxclk_en_o(rxclk_en),
  .txclk_en_o(txclk_en)
);

transmitter uart_tx(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .din_8b_i(uart_dataTx),
  .wren_i(uart_dataTx_valid),
  .clken_i(txclk_en),
  .tx_o(uart_tx_o),
  .tx_busy_o(uart_tx_busy_o)
);

receiver uart_rx(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .clken_i(rxclk_en),
  .dout_8b_o(uart_dataRx),
  .dout_valid_o(uart_dataRx_valid),
  .rx_i(uart_rx_i)
);

uart_control uart_ctl(
  .clk_50m_i(clk_50m_i),
  .rst_n_i(rst_n_i),
  .addr_32b_i(addr_32b_i),
  .wren_i(wren_i),
  .rden_i(rden_i),
  .din_32b_i(din_32b_i),
  .dout_32b_o(dout_32b_o),
  .dout_32b_valid_o(dout_32b_valid_o),
  .interrupt_o(interrupt_o),

  .din_8b_i(uart_dataRx),
  .din_valid_i(uart_dataRx_valid),
  .dout_8b_o(uart_dataTx),
  .dout_valid_o(uart_dataTx_valid),
  .tx_busy_i(uart_tx_busy_o)
);

endmodule