data/full_repos/permissive/522145661/Test_Read_MUX.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:27: Unsupported: Ignoring delay on this delayed statement.\n always #15  CLK =  ! CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:30: Unsupported: Ignoring delay on this delayed statement.\n #500 RST = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:31: Unsupported: Ignoring delay on this delayed statement.\n #50 RST = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #200 HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random; SEL = 2\'b00; RST = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #200   SEL = 2\'b01; RST = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #200   SEL = 2\'b10; RST = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #200   SEL = 2\'b11; RST = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Read_MUX.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #200   SEL = 2\'b00; RST = 0;\n  ^\n%Error: data/full_repos/permissive/522145661/Test_Read_MUX.v:17: Cannot find file containing module: \'Read_MUX\'\n Read_MUX uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Read_MUX\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Read_MUX.v\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Read_MUX.sv\n             Read_MUX\n             Read_MUX.v\n             Read_MUX.sv\n             obj_dir/Read_MUX\n             obj_dir/Read_MUX.v\n             obj_dir/Read_MUX.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Read_MUX;


	reg CLK;
	reg RST;
	reg [31:0] HRDATA_1;
	reg [31:0] HRDATA_2;
	reg [31:0] HRDATA_3;
	reg [1:0] SEL;


	wire [31:0] HRDATA;


	Read_MUX uut (
		.CLK(CLK), 
		.RST(RST), 
		.HRDATA(HRDATA), 
		.HRDATA_1(HRDATA_1), 
		.HRDATA_2(HRDATA_2), 
		.HRDATA_3(HRDATA_3), 
		.SEL(SEL)
	);
	
	always #15  CLK =  ! CLK;
	
	initial begin
	#500 RST = 1;
	#50 RST = 0;
	end

	initial begin

		CLK = 0;
		RST = 0;
		HRDATA_1 = 0;
		HRDATA_2 = 0;
		HRDATA_3 = 0;
		SEL = 0;


		#15;
        

		
		#200 HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random; SEL = 2'b00; RST = 0;
		#200SEL = 2'b01; RST = 0;
		#200SEL = 2'b10; RST = 0;
		#200SEL = 2'b11; RST = 0;
		#200SEL = 2'b00; RST = 0;
		
	end
      
endmodule
module Test_Read_MUX;



	reg CLK;
	reg RST;
	reg [31:0] HRDATA_1;
	reg [31:0] HRDATA_2;
	reg [31:0] HRDATA_3;
	reg [1:0] SEL;


	wire [31:0] HRDATA;


	Read_MUX uut (
		.CLK(CLK), 
		.RST(RST), 
		.HRDATA(HRDATA), 
		.HRDATA_1(HRDATA_1), 
		.HRDATA_2(HRDATA_2), 
		.HRDATA_3(HRDATA_3), 
		.SEL(SEL)
	);
	
	always #15  CLK =  ! CLK;
	
	initial begin
	#500 RST = 1;
	#50 RST = 0;
	end

	initial begin

		CLK = 0;
		RST = 0;
		HRDATA_1 = 0;
		HRDATA_2 = 0;
		HRDATA_3 = 0;
		SEL = 0;


		#15;
        

		
		#200 HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random; SEL = 2'b00; RST = 0;
		#200SEL = 2'b01; RST = 0;
		#200SEL = 2'b10; RST = 0;
		#200SEL = 2'b11; RST = 0;
		#200SEL = 2'b00; RST = 0;
		
	end
      
endmodule