data/full_repos/permissive/523038000/lab5/regfile_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/523038000/lab5/regfile_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/523038000/lab5/regfile_tb.v:50: Cannot find file containing module: \'RegisterFile\'\n RegisterFile uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab5,data/full_repos/permissive/523038000/RegisterFile\n             data/full_repos/permissive/523038000/lab5,data/full_repos/permissive/523038000/RegisterFile.v\n             data/full_repos/permissive/523038000/lab5,data/full_repos/permissive/523038000/RegisterFile.sv\n             RegisterFile\n             RegisterFile.v\n             RegisterFile.sv\n             obj_dir/RegisterFile\n             obj_dir/RegisterFile.v\n             obj_dir/RegisterFile.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile_tb;


	reg [4:0] ReadRegister1;
	reg [4:0] ReadRegister2;
	reg [4:0] WriteRegister;
	reg [31:0] WriteData;
	reg RegWrite;
	reg Clk;


	wire [31:0] ReadData1;
	wire [31:0] ReadData2;


	RegisterFile uut (
		.ReadRegister1(ReadRegister1), 
		.ReadRegister2(ReadRegister2), 
		.WriteRegister(WriteRegister), 
		.WriteData(WriteData), 
		.RegWrite(RegWrite), 
		.Clk(Clk), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2)
	);

	initial begin

		ReadRegister1 = 0;
		ReadRegister2 = 0;
		WriteRegister = 0;
		WriteData = 0;
		RegWrite = 0;
		Clk = 0;


		#100;
        



	end
      
endmodule
module regfile_tb;



	reg [4:0] ReadRegister1;
	reg [4:0] ReadRegister2;
	reg [4:0] WriteRegister;
	reg [31:0] WriteData;
	reg RegWrite;
	reg Clk;


	wire [31:0] ReadData1;
	wire [31:0] ReadData2;


	RegisterFile uut (
		.ReadRegister1(ReadRegister1), 
		.ReadRegister2(ReadRegister2), 
		.WriteRegister(WriteRegister), 
		.WriteData(WriteData), 
		.RegWrite(RegWrite), 
		.Clk(Clk), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2)
	);

	initial begin

		ReadRegister1 = 0;
		ReadRegister2 = 0;
		WriteRegister = 0;
		WriteData = 0;
		RegWrite = 0;
		Clk = 0;


		#100;
        



	end
      
endmodule