data/full_repos/permissive/449807379/CPU_design/final_design.v
1: b"%Error: data/full_repos/permissive/449807379/CPU_design/final_design.v:38: Cannot find file containing module: 'Registry_Bank_Full'\nRegistry_Bank_Full rgb1(reg_bank_ldr,destination,source1,source2,out_m1,out_m2);\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/Registry_Bank_Full\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/Registry_Bank_Full.v\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/Registry_Bank_Full.sv\n             Registry_Bank_Full\n             Registry_Bank_Full.v\n             Registry_Bank_Full.sv\n             obj_dir/Registry_Bank_Full\n             obj_dir/Registry_Bank_Full.v\n             obj_dir/Registry_Bank_Full.sv\n%Error: data/full_repos/permissive/449807379/CPU_design/final_design.v:41: Cannot find file containing module: 'alu_control'\nalu_control aluc1(condition, opcode, s_bit, shift_control, immediate_value, out_m1, out_m2, alu_result, flags, pc_trigger, pc_counter, pc_reset);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/449807379/CPU_design/final_design.v:43: Cannot find file containing module: 'memory_control_with_RAM'\nmemory_control_with_RAM mcwr1(out_m1, out_m2, alu_result, opcode, reg_bank_ldr, {8'b0, pc_counter}, instruction);\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module final_design(clk, pc_reset, flags);

input clk;
input pc_reset;
output [3:0] flags;

reg [3:0] condition, opcode, destination, source1, source2;
reg s_bit;
reg [4:0] shift_ror;
reg [15:0] immediate_value;
reg [2:0] shift_control;
wire [31:0] instruction;
reg pc_trigger;
wire [7:0] pc_counter;

initial
begin
pc_trigger <= 1'b0;
opcode <= 4'b1111;
end

always @ (posedge clk or negedge clk)
begin
pc_trigger = !pc_trigger;
shift_control = instruction[2:0];
immediate_value = instruction[18:3];
shift_ror = instruction[10:6];
source2 = instruction[14:11];
source1 = instruction[18:15];
destination = instruction[22:19];
s_bit = instruction[23];
opcode = instruction[27:24];
condition = instruction[31:28];
end

wire [31:0] reg_bank_ldr, out_m1, out_m2, alu_result;

Registry_Bank_Full rgb1(reg_bank_ldr,destination,source1,source2,out_m1,out_m2);


alu_control aluc1(condition, opcode, s_bit, shift_control, immediate_value, out_m1, out_m2, alu_result, flags, pc_trigger, pc_counter, pc_reset);

memory_control_with_RAM mcwr1(out_m1, out_m2, alu_result, opcode, reg_bank_ldr, {8'b0, pc_counter}, instruction);

endmodule
module final_design(clk, pc_reset, flags);


input clk;
input pc_reset;
output [3:0] flags;

reg [3:0] condition, opcode, destination, source1, source2;
reg s_bit;
reg [4:0] shift_ror;
reg [15:0] immediate_value;
reg [2:0] shift_control;
wire [31:0] instruction;
reg pc_trigger;
wire [7:0] pc_counter;

initial
begin
pc_trigger <= 1'b0;
opcode <= 4'b1111;
end

always @ (posedge clk or negedge clk)
begin
pc_trigger = !pc_trigger;
shift_control = instruction[2:0];
immediate_value = instruction[18:3];
shift_ror = instruction[10:6];
source2 = instruction[14:11];
source1 = instruction[18:15];
destination = instruction[22:19];
s_bit = instruction[23];
opcode = instruction[27:24];
condition = instruction[31:28];
end

wire [31:0] reg_bank_ldr, out_m1, out_m2, alu_result;

Registry_Bank_Full rgb1(reg_bank_ldr,destination,source1,source2,out_m1,out_m2);


alu_control aluc1(condition, opcode, s_bit, shift_control, immediate_value, out_m1, out_m2, alu_result, flags, pc_trigger, pc_counter, pc_reset);

memory_control_with_RAM mcwr1(out_m1, out_m2, alu_result, opcode, reg_bank_ldr, {8'b0, pc_counter}, instruction);

endmodule