data/full_repos/permissive/490492655/regn_testbench.v
1: b'%Error: data/full_repos/permissive/490492655/regn_testbench.v:15: Unsupported or unknown PLI call: $monitor\n      $monitor($time, " rst=%b, pst=%b, en=%b, d=%d, q=%d", rst, pst, en, d, q);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/490492655/regn_testbench.v:22: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("regn.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/490492655/regn_testbench.v:23: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, regn_testbench);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/490492655/regn_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #0 clk=1; rst=1; pst=0; en=1; d=10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/490492655/regn_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n          #25 clk <= ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/490492655/regn_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n          #25 clk <= ~clk; rst <= (i%8==3)?0:1; pst <= (i%8==5)?1:0; en <= (i%8==7)?0:1; d <= d+1;\n          ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regn_testbench #(parameter n = 8) ();
  
  reg clk, rst, pst, en;
  reg [n-1:0] d;
  wire [n-1:0] q;
  
  regn #(.n(8)) DUT (.clk(clk), .rst(rst), .pst(pst), .en(en), .d(d), .q(q));
  
  initial
    begin
      $monitor($time, " rst=%b, pst=%b, en=%b, d=%d, q=%d", rst, pst, en, d, q);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("regn.vcd");
      $dumpvars(1, regn_testbench);
      
      #0 clk=1; rst=1; pst=0; en=1; d=10;
      
      for (i = 0; i < 20; i = i+1)
        begin
          #25 clk <= ~clk;
          #25 clk <= ~clk; rst <= (i%8==3)?0:1; pst <= (i%8==5)?1:0; en <= (i%8==7)?0:1; d <= d+1;
        end
    end
  
endmodule
module regn_testbench #(parameter n = 8) ();

  
  reg clk, rst, pst, en;
  reg [n-1:0] d;
  wire [n-1:0] q;
  
  regn #(.n(8)) DUT (.clk(clk), .rst(rst), .pst(pst), .en(en), .d(d), .q(q));
  
  initial
    begin
      $monitor($time, " rst=%b, pst=%b, en=%b, d=%d, q=%d", rst, pst, en, d, q);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("regn.vcd");
      $dumpvars(1, regn_testbench);
      
      #0 clk=1; rst=1; pst=0; en=1; d=10;
      
      for (i = 0; i < 20; i = i+1)
        begin
          #25 clk <= ~clk;
          #25 clk <= ~clk; rst <= (i%8==3)?0:1; pst <= (i%8==5)?1:0; en <= (i%8==7)?0:1; d <= d+1;
        end
    end
  
endmodule