data/full_repos/permissive/458113953/lab12_2019A8PS0621H/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/ALU.v:32: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                                 : ... In instance ALU\n    3\'b000:{Yh,Yl}= A+B;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/ALU.v:32: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                                 : ... In instance ALU\n    3\'b000:{Yh,Yl}= A+B;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/ALU.v:33: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                                 : ... In instance ALU\n    3\'b001:{Yh,Yl}=A-B;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/ALU.v:33: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                                 : ... In instance ALU\n    3\'b001:{Yh,Yl}=A-B;\n                    ^\n%Error: Exiting due to 4 warning(s)\n'
module ALU(
    input [7:0] A,
    input [7:0] B,
    input [2:0] S,
    output reg [7:0] Yh,
    output reg [7:0] Yl
    );
    always@(*)
    case(S)
    3'b000:{Yh,Yl}= A+B;
    3'b001:{Yh,Yl}=A-B;
    3'b010:{Yh,Yl}=A*B;
    3'b011:Yl=A+1;
    3'b100:Yl=A<<B;
    3'b101:Yl=A&B;
    3'b110:Yl=A|B;
    3'b111:Yl=A^B;
    endcase
endmodule
module ALU(
    input [7:0] A,
    input [7:0] B,
    input [2:0] S,
    output reg [7:0] Yh,
    output reg [7:0] Yl
    );

    always@(*)
    case(S)
    3'b000:{Yh,Yl}= A+B;
    3'b001:{Yh,Yl}=A-B;
    3'b010:{Yh,Yl}=A*B;
    3'b011:Yl=A+1;
    3'b100:Yl=A<<B;
    3'b101:Yl=A&B;
    3'b110:Yl=A|B;
    3'b111:Yl=A^B;
    endcase
endmodule