data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("caravel_alu74181.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, alu74181_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:53: syntax error, unexpected \'@\'\n  repeat (1000) @(posedge clock);\n                ^\n%Error: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:73: Unsupported: wait statements\n  wait(mprj_io_out == 8\'b10000001);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472033638/caravel_alu74181/caravel_alu74181_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO-OUT state = %b ", mprj_io_out[7:0]);\n  ^\n%Error: Exiting due to 4 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu74181_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	reg M, C;
	reg [3:0] A, B, S;
	wire [7:0]  mprj_io_out;

	assign mprj_io_out = mprj_io[29:22];
	assign mprj_io[21:8] = {M, C, S, B, A};
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("caravel_alu74181.vcd");
		$dumpvars(0, alu74181_tb);


		repeat (25) begin
		repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("ALU 74181 Tests: Failed (GL), Timeout");
		`else
			$display ("ALU 74181 Tests: Failed (RTL), Timeout");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

		M <= 1'b0;
		C <= 1'b1;
		S <= 4'b1001;
		B <= 4'b0000;
		A <= 4'b0001;
		wait(mprj_io_out == 8'b10000001);
		#1000

		$display("%c[1;25m",27);
		`ifdef GL
	    	$display("ALU 74181 Tests: Passed (GL)");
		`else
		    $display("ALU 74181 Tests: Passed (RTL)");
		`endif
		$display("%c[0m",27);
    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end


	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end


	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end


	always @(mprj_io_out) begin
		#1 $display("MPRJ-IO-OUT state = %b ", mprj_io_out[7:0]);
	end


	always @(mprj_io[21:8]) begin
		$display("MPRJ-IO-IN = %b ", mprj_io[21:8]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("caravel_alu74181.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module alu74181_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	reg M, C;
	reg [3:0] A, B, S;
	wire [7:0]  mprj_io_out;

	assign mprj_io_out = mprj_io[29:22];
	assign mprj_io[21:8] = {M, C, S, B, A};
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("caravel_alu74181.vcd");
		$dumpvars(0, alu74181_tb);


		repeat (25) begin
		repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("ALU 74181 Tests: Failed (GL), Timeout");
		`else
			$display ("ALU 74181 Tests: Failed (RTL), Timeout");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

		M <= 1'b0;
		C <= 1'b1;
		S <= 4'b1001;
		B <= 4'b0000;
		A <= 4'b0001;
		wait(mprj_io_out == 8'b10000001);
		#1000

		$display("%c[1;25m",27);
		`ifdef GL
	    	$display("ALU 74181 Tests: Passed (GL)");
		`else
		    $display("ALU 74181 Tests: Passed (RTL)");
		`endif
		$display("%c[0m",27);
    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end


	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end


	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end


	always @(mprj_io_out) begin
		#1 $display("MPRJ-IO-OUT state = %b ", mprj_io_out[7:0]);
	end


	always @(mprj_io[21:8]) begin
		$display("MPRJ-IO-IN = %b ", mprj_io[21:8]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("caravel_alu74181.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule