data/full_repos/permissive/482168662/lab01_water_led.v
data/verilator_xmls/14d9ae6a-920e-4a83-a172-bc54edadee11.xml
module water_led(
    input clk,
    input rst_n,
    output [7:0] led
    );
  parameter MAX = 26'd49_999_999;
    reg [25:0] cnt;
    reg CLK_1Hz_flag;
    reg [7:0] led_reg;

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            cnt <= 26'b0;
        else if(cnt == MAX)
                cnt <= 26'b0;
        else 
            cnt <= cnt + 26'd1;
    end

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
          CLK_1Hz_flag <= 1'd0;
        else if(cnt == MAX)
          CLK_1Hz_flag <= 1'd1;
        else
          CLK_1Hz_flag <= 1'd0; 
    end
    
    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            led_reg <= 8'b00000000;
        else if(CLK_1Hz_flag==1'b1&&led_reg==8'b11111111)
            led_reg <= 8'b00000000;
        else if(CLK_1Hz_flag==1'b1)
            led_reg <= {led[6:0],1'b1};
    end

    assign led = led_reg;   

endmodule
module water_led(
    input clk,
    input rst_n,
    output [7:0] led
    );

  parameter MAX = 26'd49_999_999;
    reg [25:0] cnt;
    reg CLK_1Hz_flag;
    reg [7:0] led_reg;

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            cnt <= 26'b0;
        else if(cnt == MAX)
                cnt <= 26'b0;
        else 
            cnt <= cnt + 26'd1;
    end

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
          CLK_1Hz_flag <= 1'd0;
        else if(cnt == MAX)
          CLK_1Hz_flag <= 1'd1;
        else
          CLK_1Hz_flag <= 1'd0; 
    end
    
    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            led_reg <= 8'b00000000;
        else if(CLK_1Hz_flag==1'b1&&led_reg==8'b11111111)
            led_reg <= 8'b00000000;
        else if(CLK_1Hz_flag==1'b1)
            led_reg <= {led[6:0],1'b1};
    end

    assign led = led_reg;   

endmodule