data/full_repos/permissive/47037127/cache/instructioncache.v
1: b'%Error: data/full_repos/permissive/47037127/cache/instructioncache.v:28: Cannot find file containing module: \'instructionhasher\'\ninstructionhasher hash(addr, lineSel);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/47037127/cache,data/full_repos/permissive/47037127/instructionhasher\n             data/full_repos/permissive/47037127/cache,data/full_repos/permissive/47037127/instructionhasher.v\n             data/full_repos/permissive/47037127/cache,data/full_repos/permissive/47037127/instructionhasher.sv\n             instructionhasher\n             instructionhasher.v\n             instructionhasher.sv\n             obj_dir/instructionhasher\n             obj_dir/instructionhasher.v\n             obj_dir/instructionhasher.sv\n%Warning-WIDTH: data/full_repos/permissive/47037127/cache/instructioncache.v:100: Bit extraction of array[63:0] requires 6 bit index, not 11 bits.\n                                                                                : ... In instance instructioncache\n      tags[i]=32\'hF0000000;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module instructioncache(memdat, addr, clk, rst, wt, DATOUT, OUTADDR, OUTWAIT);

input [15:0] memdat;
input [31:0] addr;
input clk;
input rst;
input wt;
output [63:0] DATOUT;
output [31:0] OUTADDR;
output OUTWAIT;




reg [31:0] outAddr;
assign OUTADDR=outAddr;



reg [63:0] iCache [0:63]; 
reg [31:0] tags [0:63];

wire [5:0] lineSel;
instructionhasher hash(addr, lineSel);

wire [31:0] curLine;
assign curLine=tags[lineSel];
   
assign DATOUT=iCache[lineSel];






assign OUTWAIT=~((addr>=tags[lineSel])&&(addr<(tags[lineSel]+4)));

reg [3:0] stateCtr;


always@(posedge clk) begin
	if(OUTWAIT) begin

		if(stateCtr==0) begin
			outAddr<=addr;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==1) begin
			iCache[lineSel][15:0]<=memdat;
			outAddr<=addr+1;
			


			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==2) begin
			iCache[lineSel][31:16]<=memdat;
			outAddr<=addr+2;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==3) begin
			iCache[lineSel][47:32]<=memdat;
			outAddr<=addr+3;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==4) begin
			iCache[lineSel][63:48]<=memdat;
			tags[lineSel]<=addr;

			if(~wt) begin
				stateCtr<=0;
			end
		end
	end
end

reg [10:0] i;
   
initial begin
   for(i=0;i<64;i=i+1) begin
      tags[i]=32'hF0000000;
      
   end

   stateCtr=0;
   
end

endmodule
module instructioncache(memdat, addr, clk, rst, wt, DATOUT, OUTADDR, OUTWAIT);


input [15:0] memdat;
input [31:0] addr;
input clk;
input rst;
input wt;
output [63:0] DATOUT;
output [31:0] OUTADDR;
output OUTWAIT;




reg [31:0] outAddr;
assign OUTADDR=outAddr;



reg [63:0] iCache [0:63]; 
reg [31:0] tags [0:63];

wire [5:0] lineSel;
instructionhasher hash(addr, lineSel);

wire [31:0] curLine;
assign curLine=tags[lineSel];
   
assign DATOUT=iCache[lineSel];






assign OUTWAIT=~((addr>=tags[lineSel])&&(addr<(tags[lineSel]+4)));

reg [3:0] stateCtr;


always@(posedge clk) begin
	if(OUTWAIT) begin

		if(stateCtr==0) begin
			outAddr<=addr;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==1) begin
			iCache[lineSel][15:0]<=memdat;
			outAddr<=addr+1;
			


			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==2) begin
			iCache[lineSel][31:16]<=memdat;
			outAddr<=addr+2;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==3) begin
			iCache[lineSel][47:32]<=memdat;
			outAddr<=addr+3;

			if(~wt) begin
				stateCtr<=stateCtr+1;
			end
		end

		else if(stateCtr==4) begin
			iCache[lineSel][63:48]<=memdat;
			tags[lineSel]<=addr;

			if(~wt) begin
				stateCtr<=0;
			end
		end
	end
end

reg [10:0] i;
   
initial begin
   for(i=0;i<64;i=i+1) begin
      tags[i]=32'hF0000000;
      
   end

   stateCtr=0;
   
end

endmodule