data/full_repos/permissive/434840709/week12/10.v
data/verilator_xmls/f13c5a75-ebd8-404b-af4f-517a0cb8c6bb.xml
module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);
   reg [7:0] temp;
   always @(posedge clk) begin
       temp <= in;
       anyedge <= temp ^ in;
   end
endmodule
module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);

   reg [7:0] temp;
   always @(posedge clk) begin
       temp <= in;
       anyedge <= temp ^ in;
   end
endmodule