data/full_repos/permissive/531279620/resource/src/tb_cc_line.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #2.5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:51: Unsupported: fork statements\n  fork begin\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #0 clk = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #1000 nrst <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #1000 start <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #10 cc1_io = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #100 cc_check <= 1\'b0;\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_cc_line.v:67: syntax error, unexpected \'@\'\n   @(posedge clk)\n   ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_cc_line;

	reg		clk;
	reg		nrst;
	reg		start;
	
	reg		cc1_io;
	reg		cc1_dout;
	reg		cc2_io;
	reg		cc2_dout;
	
	reg		cc_check;
	
	wire	cc1;
	wire	cc2;
	
	assign cc1 = (cc1_io) ? cc1_dout : 1'b1;
	assign cc2 = (cc2_io) ? cc2_dout : 1'b0;
	
	cc_line DUT(
		.nrst		(nrst),
		.clock		(clk),
		
		.cc1		(cc1),
		.cc2		(cc2),
		
		.cc_check	(cc_check),
		.cc_dout	(1'b0),
		.cc_io_ctrl	(1'b0)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			cc1_io = 1'b0;
			cc1_dout = 1'b0;
			cc2_io = 1'b0;
			cc2_dout = 1'b0;
			cc_check = 1'b0;
			
			#1000 nrst <= 1'b1;
			#1000 start <= 1'b1;
			
			#10 cc1_io = 1'b0;
			
			#100 cc_check <= 1'b0;
			@(posedge clk)
			cc_check <= 1'b1;
			@(posedge clk)
			cc_check <= 1'b0;
			
		end join
	end
	
endmodule
module tb_cc_line;


	reg		clk;
	reg		nrst;
	reg		start;
	
	reg		cc1_io;
	reg		cc1_dout;
	reg		cc2_io;
	reg		cc2_dout;
	
	reg		cc_check;
	
	wire	cc1;
	wire	cc2;
	
	assign cc1 = (cc1_io) ? cc1_dout : 1'b1;
	assign cc2 = (cc2_io) ? cc2_dout : 1'b0;
	
	cc_line DUT(
		.nrst		(nrst),
		.clock		(clk),
		
		.cc1		(cc1),
		.cc2		(cc2),
		
		.cc_check	(cc_check),
		.cc_dout	(1'b0),
		.cc_io_ctrl	(1'b0)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			cc1_io = 1'b0;
			cc1_dout = 1'b0;
			cc2_io = 1'b0;
			cc2_dout = 1'b0;
			cc_check = 1'b0;
			
			#1000 nrst <= 1'b1;
			#1000 start <= 1'b1;
			
			#10 cc1_io = 1'b0;
			
			#100 cc_check <= 1'b0;
			@(posedge clk)
			cc_check <= 1'b1;
			@(posedge clk)
			cc_check <= 1'b0;
			
		end join
	end
	
endmodule