data/full_repos/permissive/423547971/College Coursework/Advanced Computer Architecture Final Project/verilog CPU/control_unit.v
1: b'%Error: Cannot find file containing module: Coursework/Advanced\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Advanced\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.v\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.sv\n             Coursework/Advanced\n             Coursework/Advanced.v\n             Coursework/Advanced.sv\n             obj_dir/Coursework/Advanced\n             obj_dir/Coursework/Advanced.v\n             obj_dir/Coursework/Advanced.sv\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Architecture\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project/verilog\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: CPU/control_unit.v\n%Error: Exiting due to 8 error(s)\n'
module control_unit( instr_reg, fam, opcode, src1_reg, src2_dest_reg, sys_enable, data_out );

input  reg [31:0]  instr_reg;

output [1:0]  fam 		= instr_reg[31:30];
output [2:0]  opcode 		= instr_reg[29:27];
output [2:0]  src1_reg 		= instr_reg[26:24];
output [2:0]  src2_dest_reg	= instr_reg[23:21];
output [0]    sys_enable	= instr_reg[20];
output [0]    			= instr_reg[19];
output [0]			= instr_reg[18];
output [0]			= instr_reg[17];
output [0]			= instr_reg[16];


output [15:0] data_out		= instr_reg[15:0];


endmodule
module control_unit( instr_reg, fam, opcode, src1_reg, src2_dest_reg, sys_enable, data_out );


input  reg [31:0]  instr_reg;

output [1:0]  fam 		= instr_reg[31:30];
output [2:0]  opcode 		= instr_reg[29:27];
output [2:0]  src1_reg 		= instr_reg[26:24];
output [2:0]  src2_dest_reg	= instr_reg[23:21];
output [0]    sys_enable	= instr_reg[20];
output [0]    			= instr_reg[19];
output [0]			= instr_reg[18];
output [0]			= instr_reg[17];
output [0]			= instr_reg[16];


output [15:0] data_out		= instr_reg[15:0];


endmodule