data/full_repos/permissive/497530416/pipe/f_reg.v
data/verilator_xmls/a4f970e4-2d08-4946-8990-ba7273477f93.xml
module f_reg_pipe(clk, predPC, F_predPC);

input clk;
input [63:0] predPC;
output reg [63:0] F_predPC;

always @(posedge clk)
    begin
        F_predPC <= predPC;
    end
endmodule
module f_reg_pipe(clk, predPC, F_predPC);


input clk;
input [63:0] predPC;
output reg [63:0] F_predPC;

always @(posedge clk)
    begin
        F_predPC <= predPC;
    end
endmodule