data/full_repos/permissive/431605717/Code/RV32IM/riscv.v
1: b"%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:71: Cannot find file containing module: 'risc_v_32_if'\nrisc_v_32_if IF(clk,clrn,inst_i,next_pc1,PCSrc1,pc_write,pc1,inst1);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431605717/Code/RV32IM,data/full_repos/permissive/431605717/risc_v_32_if\n             data/full_repos/permissive/431605717/Code/RV32IM,data/full_repos/permissive/431605717/risc_v_32_if.v\n             data/full_repos/permissive/431605717/Code/RV32IM,data/full_repos/permissive/431605717/risc_v_32_if.sv\n             risc_v_32_if\n             risc_v_32_if.v\n             risc_v_32_if.sv\n             obj_dir/risc_v_32_if\n             obj_dir/risc_v_32_if.v\n             obj_dir/risc_v_32_if.sv\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:73: Cannot find file containing module: 'ifidreg'\nifidreg ifid(clk,clrn,ifid_write,PCSrc1,pc1,inst1,pc2,inst2);\n^~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:75: Cannot find file containing module: 'risc_v_32_id'\nrisc_v_32_id ID(inst2,pc2,pc_o,inst_decode1,imm1,rd11,rd21,wr1);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:77: Cannot find file containing module: 'risc_v_32_regfile'\nrisc_v_32_regfile regfile(clk,clrn,rd11,rd21,wr4,data_2_rf,wreg3,read_data11,read_data21);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:79: Cannot find file containing module: 'risc_v_32_hazard'\nrisc_v_32_hazard hazard(rmem1,inst_decode1,rd11,rd21,wr2,pc_write,ifid_write,MUX_out);\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:81: Cannot find file containing module: 'idexreg'\nidexreg idex(clk,clrn,PCSrc1,inst2,pc2,MUX_out,imm1,read_data11,read_data21,wr1,rd11,rd21,inst3,pc3,inst_decode2,imm2,read_data12,read_data22,wr2,rd12,rd22);\n^~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:83: Cannot find file containing module: 'risc_v_32_forward'\nrisc_v_32_forward forward(read_data12,data_2_rf,alu_out2,read_data22,data_2_rf,alu_out2,rd12,rd22,wreg2,wr3,wreg3,wr4,a,b);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:85: Cannot find file containing module: 'risc_v_32_ex'\nrisc_v_32_ex EX(pc3,a,b,inst3,inst_decode2,imm2,m_addr1,d_t_mem_i,wreg1,wmem1,rmem1,i_load1,alu_out1,next_pc1,PCSrc1);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:87: Cannot find file containing module: 'exmemreg'\nexmemreg exmem(clk,clrn,inst3,pc3,next_pc1,m_addr1,d_t_mem_i,wreg1,wr2,wmem1,rmem1,i_load1,alu_out1,PCSrc1,inst_decode2,inst4,pc4,next_pc2,m_addr2,d_t_mem_o,wreg2,wr3,wmem2,rmem2,i_load2,alu_out2,PCSrc2,inst_decode3);\n^~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:89: Cannot find file containing module: 'risc_v_32_mem'\nrisc_v_32_mem MEM(m_addr2,data_i,inst_decode3,mem_out1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:91: Cannot find file containing module: 'memwbreg'\nmemwbreg memwb(clk,clrn,pc4,inst4,mem_out1,alu_out2,wreg2,wr3,i_load2,pc5,inst5,mem_out2,alu_out3,wreg3,wr4,i_load3);\n^~~~~~~~\n%Error: data/full_repos/permissive/431605717/Code/RV32IM/riscv.v:93: Cannot find file containing module: 'risc_v_32_wb'\nrisc_v_32_wb WB(mem_out2,alu_out3,i_load3,data_2_rf);\n^~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module riscv(

    input wire               clk,
    input wire               rst,
    

    input wire[31:0]         inst_i,
    output wire[31:0]        inst_addr_o,
    output wire              inst_ce_o,


    input wire[31:0]         data_i,
    output wire              data_we_o,
    output wire              data_ce_o,
    output wire[31:0]        data_addr_o,
    output wire[31:0]        data_o

);


wire clrn = !rst;

wire        PCSrc1,PCSrc2;
wire [31:0] pc1;
wire [31:0] pc2;
wire [31:0] pc3;
wire [31:0] pc4;
wire [31:0] pc5;
wire [31:0] inst1;
wire [31:0] inst2;
wire [31:0] inst3;
wire [31:0] inst4;
wire [31:0] inst5;
wire [31:0] pc_o;
wire [36:0] inst_decode1;
wire [36:0] inst_decode2;
wire [36:0] inst_decode3;
wire [31:0] imm1;
wire [31:0] imm2;
wire [4:0]  rd11,rd12;
wire [4:0]  rd21,rd22;
wire [4:0]  wr1;
wire [4:0]  wr2,wr3,wr4;
wire        i_load1,i_load2,i_load3;
wire        wreg1,wreg2,wreg3;
wire [31:0] read_data11,read_data12;
wire [31:0] read_data21,read_data22;
wire [31:0] m_addr1,m_addr2;
wire [31:0] d_t_mem_i,d_t_mem_o;
wire        wmem1,wmem2;
wire        rmem1,rmem2;
wire [31:0] data_2_rf;
wire [31:0] alu_out1,alu_out2,alu_out3;
wire [31:0] mem_out1,mem_out2;
wire [31:0] next_pc1,next_pc2;
wire        pc_write;
wire        ifid_write;
wire [36:0] MUX_out;
wire [31:0] a,b;

assign data_ce_o = rmem2 | wmem2;
assign data_we_o = wmem2;
assign data_addr_o = m_addr2;
assign data_o = d_t_mem_i;
assign inst_addr_o = pc1;
assign inst_ce_o = 1;

risc_v_32_if IF(clk,clrn,inst_i,next_pc1,PCSrc1,pc_write,pc1,inst1);

ifidreg ifid(clk,clrn,ifid_write,PCSrc1,pc1,inst1,pc2,inst2);

risc_v_32_id ID(inst2,pc2,pc_o,inst_decode1,imm1,rd11,rd21,wr1);

risc_v_32_regfile regfile(clk,clrn,rd11,rd21,wr4,data_2_rf,wreg3,read_data11,read_data21);

risc_v_32_hazard hazard(rmem1,inst_decode1,rd11,rd21,wr2,pc_write,ifid_write,MUX_out);

idexreg idex(clk,clrn,PCSrc1,inst2,pc2,MUX_out,imm1,read_data11,read_data21,wr1,rd11,rd21,inst3,pc3,inst_decode2,imm2,read_data12,read_data22,wr2,rd12,rd22);

risc_v_32_forward forward(read_data12,data_2_rf,alu_out2,read_data22,data_2_rf,alu_out2,rd12,rd22,wreg2,wr3,wreg3,wr4,a,b);

risc_v_32_ex EX(pc3,a,b,inst3,inst_decode2,imm2,m_addr1,d_t_mem_i,wreg1,wmem1,rmem1,i_load1,alu_out1,next_pc1,PCSrc1);

exmemreg exmem(clk,clrn,inst3,pc3,next_pc1,m_addr1,d_t_mem_i,wreg1,wr2,wmem1,rmem1,i_load1,alu_out1,PCSrc1,inst_decode2,inst4,pc4,next_pc2,m_addr2,d_t_mem_o,wreg2,wr3,wmem2,rmem2,i_load2,alu_out2,PCSrc2,inst_decode3);

risc_v_32_mem MEM(m_addr2,data_i,inst_decode3,mem_out1);

memwbreg memwb(clk,clrn,pc4,inst4,mem_out1,alu_out2,wreg2,wr3,i_load2,pc5,inst5,mem_out2,alu_out3,wreg3,wr4,i_load3);

risc_v_32_wb WB(mem_out2,alu_out3,i_load3,data_2_rf);


endmodule
module riscv(

    input wire               clk,
    input wire               rst,
    

    input wire[31:0]         inst_i,
    output wire[31:0]        inst_addr_o,
    output wire              inst_ce_o,


    input wire[31:0]         data_i,
    output wire              data_we_o,
    output wire              data_ce_o,
    output wire[31:0]        data_addr_o,
    output wire[31:0]        data_o

);



wire clrn = !rst;

wire        PCSrc1,PCSrc2;
wire [31:0] pc1;
wire [31:0] pc2;
wire [31:0] pc3;
wire [31:0] pc4;
wire [31:0] pc5;
wire [31:0] inst1;
wire [31:0] inst2;
wire [31:0] inst3;
wire [31:0] inst4;
wire [31:0] inst5;
wire [31:0] pc_o;
wire [36:0] inst_decode1;
wire [36:0] inst_decode2;
wire [36:0] inst_decode3;
wire [31:0] imm1;
wire [31:0] imm2;
wire [4:0]  rd11,rd12;
wire [4:0]  rd21,rd22;
wire [4:0]  wr1;
wire [4:0]  wr2,wr3,wr4;
wire        i_load1,i_load2,i_load3;
wire        wreg1,wreg2,wreg3;
wire [31:0] read_data11,read_data12;
wire [31:0] read_data21,read_data22;
wire [31:0] m_addr1,m_addr2;
wire [31:0] d_t_mem_i,d_t_mem_o;
wire        wmem1,wmem2;
wire        rmem1,rmem2;
wire [31:0] data_2_rf;
wire [31:0] alu_out1,alu_out2,alu_out3;
wire [31:0] mem_out1,mem_out2;
wire [31:0] next_pc1,next_pc2;
wire        pc_write;
wire        ifid_write;
wire [36:0] MUX_out;
wire [31:0] a,b;

assign data_ce_o = rmem2 | wmem2;
assign data_we_o = wmem2;
assign data_addr_o = m_addr2;
assign data_o = d_t_mem_i;
assign inst_addr_o = pc1;
assign inst_ce_o = 1;

risc_v_32_if IF(clk,clrn,inst_i,next_pc1,PCSrc1,pc_write,pc1,inst1);

ifidreg ifid(clk,clrn,ifid_write,PCSrc1,pc1,inst1,pc2,inst2);

risc_v_32_id ID(inst2,pc2,pc_o,inst_decode1,imm1,rd11,rd21,wr1);

risc_v_32_regfile regfile(clk,clrn,rd11,rd21,wr4,data_2_rf,wreg3,read_data11,read_data21);

risc_v_32_hazard hazard(rmem1,inst_decode1,rd11,rd21,wr2,pc_write,ifid_write,MUX_out);

idexreg idex(clk,clrn,PCSrc1,inst2,pc2,MUX_out,imm1,read_data11,read_data21,wr1,rd11,rd21,inst3,pc3,inst_decode2,imm2,read_data12,read_data22,wr2,rd12,rd22);

risc_v_32_forward forward(read_data12,data_2_rf,alu_out2,read_data22,data_2_rf,alu_out2,rd12,rd22,wreg2,wr3,wreg3,wr4,a,b);

risc_v_32_ex EX(pc3,a,b,inst3,inst_decode2,imm2,m_addr1,d_t_mem_i,wreg1,wmem1,rmem1,i_load1,alu_out1,next_pc1,PCSrc1);

exmemreg exmem(clk,clrn,inst3,pc3,next_pc1,m_addr1,d_t_mem_i,wreg1,wr2,wmem1,rmem1,i_load1,alu_out1,PCSrc1,inst_decode2,inst4,pc4,next_pc2,m_addr2,d_t_mem_o,wreg2,wr3,wmem2,rmem2,i_load2,alu_out2,PCSrc2,inst_decode3);

risc_v_32_mem MEM(m_addr2,data_i,inst_decode3,mem_out1);

memwbreg memwb(clk,clrn,pc4,inst4,mem_out1,alu_out2,wreg2,wr3,i_load2,pc5,inst5,mem_out2,alu_out3,wreg3,wr4,i_load3);

risc_v_32_wb WB(mem_out2,alu_out3,i_load3,data_2_rf);


endmodule