data/full_repos/permissive/521337848/Hardware/MEMORIES/Kernal.v
1: b'%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/MEMORIES/Kernal.v:17: Input port connection \'addr\' expects 8 bits on the pin connection, but pin connection\'s ADD generates 32 or 12 bits.\n                                                                                  : ... In instance KERNAL\n     .addr(addr+1024),\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module KERNAL(
       input clk,
       input[11:0] addr,
       output reg[31:0] out
);

wire[31:0] out1;
wire[31:0] out2;
wire[31:0] out3;

ROM1 r1(.clk(clk),
     .addr(addr),
     .out(out1)
);

ROM2 r2(.clk(clk),
     .addr(addr+1024),
     .out(out2)
);

reg[1:0] bufstat;

always@(posedge clk)begin
	bufstat <= addr[10:9];
end

always@(*)begin
	case(bufstat)
		0: out= out1;
		1: out= out1;
		2: out= out2;
		3: out= out2;
	endcase
end

endmodule
module KERNAL(
       input clk,
       input[11:0] addr,
       output reg[31:0] out
);


wire[31:0] out1;
wire[31:0] out2;
wire[31:0] out3;

ROM1 r1(.clk(clk),
     .addr(addr),
     .out(out1)
);

ROM2 r2(.clk(clk),
     .addr(addr+1024),
     .out(out2)
);

reg[1:0] bufstat;

always@(posedge clk)begin
	bufstat <= addr[10:9];
end

always@(*)begin
	case(bufstat)
		0: out= out1;
		1: out= out1;
		2: out= out2;
		3: out= out2;
	endcase
end

endmodule