data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_local_desc.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_local_desc.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_local_desc.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #500 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_local_desc.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_local_desc.v:56: Cannot find file containing module: \'local_desc\'\n local_desc uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/local_desc\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/local_desc.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/local_desc.sv\n             local_desc\n             local_desc.v\n             local_desc.sv\n             obj_dir/local_desc\n             obj_dir/local_desc.v\n             obj_dir/local_desc.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_local_desc;


	reg clk;
	reg rst;
	reg [17:0] addr_kp;
	reg [7:0] mag;
	reg [5:0] dir;
	reg [5:0] main_dir;
    reg complete1;


	wire [15:0] local_desc_addr;
    wire [63:0] tdesc1;
    wire [63:0] tdesc2;
    wire [63:0] tdesc3;
    wire [63:0] tdesc4;
    wire [63:0] tdesc5;
    wire [63:0] tdesc6;
    wire [63:0] tdesc7;
    wire [63:0] tdesc8;
    wire [63:0] tdesc9;
    wire [63:0] tdesc10;
    wire [63:0] tdesc11;
    wire [63:0] tdesc12;
    wire [63:0] tdesc13;
    wire [63:0] tdesc14;
    wire [63:0] tdesc15;
    wire [63:0] tdesc16;


	local_desc uut (
		.clk(clk), 
		.rst(rst), 
		.addr_kp(addr_kp), 
		.mag(mag), 
		.dir(dir), 
		.main_dir(main_dir), 
		.local_desc_addr(local_desc_addr),
        .tdesc1(tdesc1),
        .tdesc2(tdesc2),
        .tdesc3(tdesc3),
        .tdesc4(tdesc4),
        .tdesc5(tdesc5),
        .tdesc6(tdesc6),
        .tdesc7(tdesc7),
        .tdesc8(tdesc8),
        .tdesc9(tdesc9),
        .tdesc10(tdesc10),
        .tdesc11(tdesc11),
        .tdesc12(tdesc12),
        .tdesc13(tdesc13),
        .tdesc14(tdesc14),
        .tdesc15(tdesc15),
        .tdesc16(tdesc16)   
	);

	initial begin

		clk = 0;
		rst = 0;
		addr_kp = 0;
		mag = 0;
		dir = 0;
		main_dir = 0;
        complete1 = 0;


		#100;
        rst=1;
		addr_kp=10020;


		main_dir=3;

        
        #500 
        complete1 = 1;

	end
	
	always
	#5 clk=~clk;
	
	always@(posedge clk)
	begin
		if(dir<30)
			dir<=dir+1;
		else
			dir<=0;
		if(mag<30)
			mag<=mag+1;
		else
			mag<=0;
	end
      
endmodule
module tf_local_desc;



	reg clk;
	reg rst;
	reg [17:0] addr_kp;
	reg [7:0] mag;
	reg [5:0] dir;
	reg [5:0] main_dir;
    reg complete1;


	wire [15:0] local_desc_addr;
    wire [63:0] tdesc1;
    wire [63:0] tdesc2;
    wire [63:0] tdesc3;
    wire [63:0] tdesc4;
    wire [63:0] tdesc5;
    wire [63:0] tdesc6;
    wire [63:0] tdesc7;
    wire [63:0] tdesc8;
    wire [63:0] tdesc9;
    wire [63:0] tdesc10;
    wire [63:0] tdesc11;
    wire [63:0] tdesc12;
    wire [63:0] tdesc13;
    wire [63:0] tdesc14;
    wire [63:0] tdesc15;
    wire [63:0] tdesc16;


	local_desc uut (
		.clk(clk), 
		.rst(rst), 
		.addr_kp(addr_kp), 
		.mag(mag), 
		.dir(dir), 
		.main_dir(main_dir), 
		.local_desc_addr(local_desc_addr),
        .tdesc1(tdesc1),
        .tdesc2(tdesc2),
        .tdesc3(tdesc3),
        .tdesc4(tdesc4),
        .tdesc5(tdesc5),
        .tdesc6(tdesc6),
        .tdesc7(tdesc7),
        .tdesc8(tdesc8),
        .tdesc9(tdesc9),
        .tdesc10(tdesc10),
        .tdesc11(tdesc11),
        .tdesc12(tdesc12),
        .tdesc13(tdesc13),
        .tdesc14(tdesc14),
        .tdesc15(tdesc15),
        .tdesc16(tdesc16)   
	);

	initial begin

		clk = 0;
		rst = 0;
		addr_kp = 0;
		mag = 0;
		dir = 0;
		main_dir = 0;
        complete1 = 0;


		#100;
        rst=1;
		addr_kp=10020;


		main_dir=3;

        
        #500 
        complete1 = 1;

	end
	
	always
	#5 clk=~clk;
	
	always@(posedge clk)
	begin
		if(dir<30)
			dir<=dir+1;
		else
			dir<=0;
		if(mag<30)
			mag<=mag+1;
		else
			mag<=0;
	end
      
endmodule