data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:101: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                   : ... Top module \'vga_vram_control\'\nmodule vga_vram_control(\n       ^~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'vga_vram_control_old\'\nmodule vga_vram_control_old(\n       ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:145: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h0\' generates 19 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_addr <= 19\'h0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:151: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h0\' generates 19 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_addr <= 19\'h0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:179: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_read_buff <= 3\'h0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:182: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_read_buff <= 3\'h0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:219: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_write_buff <= 3\'h0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_vram_control.sv:222: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance vga_vram_control_old\n   b_write_buff <= 3\'h0;\n                ^~\n%Error: Exiting due to 7 warning(s)\n'
module vga_vram_control(

		input wire iCLOCK,
		input wire iVGA_CLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iREAD_ENABLE,
		input wire iREAD_REQ,
		input wire [19:0] iREAD_ADDR,
		output wire oREAD_BUSY,
		output wire oREAD_VALID,
		output wire [15:0] oREAD_DATA,

		input wire iWRITE_REQ,
		input wire [19:0] iWRITE_ADDR,
		input wire [15:0] iWRITE_DATA,
		output wire oWRITE_BUSY,

		output wire oMEM_VALID,
		output wire [1:0] oMEM_BYTEENA,
		output wire oMEM_RW,
		output wire [31:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY,
		input wire iMEM_VALID,
		input wire [15:0] iMEM_DATA,
		output wire oMEM_BUSY
	);

	assign oREAD_VALID = iMEM_VALID;
	assign oREAD_DATA = iMEM_DATA;

	assign oREAD_BUSY = iMEM_BUSY;
	assign oWRITE_BUSY = iMEM_BUSY || iREAD_ENABLE; 

	reg b_req;
	reg b_rw;
	reg [19:0] b_addr;
	reg [15:0] b_data;

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_rw <= 1'b0;
			b_addr <= 20'h0;
			b_data <= 16'h0;
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_rw <= 1'b0;
			b_addr <= 20'h0;
			b_data <= 16'h0;
		end
		else begin
			if(!iMEM_BUSY)begin
				b_req <= (iREAD_ENABLE && iREAD_REQ) || (!iREAD_ENABLE && iWRITE_REQ);
				b_rw <= !iREAD_ENABLE;
				b_addr <= (iREAD_ENABLE)? iREAD_ADDR : iWRITE_ADDR;
				b_data <= iWRITE_DATA;
			end
		end
	end
	
	assign oMEM_VALID = b_req;
	assign oMEM_BYTEENA = 2'b00;
	assign oMEM_RW = b_rw;
	assign oMEM_ADDR = {12'h0, b_addr};
	assign oMEM_DATA = b_data;

	assign oMEM_BUSY = 1'b0;



	
endmodule
module vga_vram_control(

		input wire iCLOCK,
		input wire iVGA_CLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iREAD_ENABLE,
		input wire iREAD_REQ,
		input wire [19:0] iREAD_ADDR,
		output wire oREAD_BUSY,
		output wire oREAD_VALID,
		output wire [15:0] oREAD_DATA,

		input wire iWRITE_REQ,
		input wire [19:0] iWRITE_ADDR,
		input wire [15:0] iWRITE_DATA,
		output wire oWRITE_BUSY,

		output wire oMEM_VALID,
		output wire [1:0] oMEM_BYTEENA,
		output wire oMEM_RW,
		output wire [31:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY,
		input wire iMEM_VALID,
		input wire [15:0] iMEM_DATA,
		output wire oMEM_BUSY
	);


	assign oREAD_VALID = iMEM_VALID;
	assign oREAD_DATA = iMEM_DATA;

	assign oREAD_BUSY = iMEM_BUSY;
	assign oWRITE_BUSY = iMEM_BUSY || iREAD_ENABLE; 

	reg b_req;
	reg b_rw;
	reg [19:0] b_addr;
	reg [15:0] b_data;

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_rw <= 1'b0;
			b_addr <= 20'h0;
			b_data <= 16'h0;
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_rw <= 1'b0;
			b_addr <= 20'h0;
			b_data <= 16'h0;
		end
		else begin
			if(!iMEM_BUSY)begin
				b_req <= (iREAD_ENABLE && iREAD_REQ) || (!iREAD_ENABLE && iWRITE_REQ);
				b_rw <= !iREAD_ENABLE;
				b_addr <= (iREAD_ENABLE)? iREAD_ADDR : iWRITE_ADDR;
				b_data <= iWRITE_DATA;
			end
		end
	end
	
	assign oMEM_VALID = b_req;
	assign oMEM_BYTEENA = 2'b00;
	assign oMEM_RW = b_rw;
	assign oMEM_ADDR = {12'h0, b_addr};
	assign oMEM_DATA = b_data;

	assign oMEM_BUSY = 1'b0;



	
endmodule