data/full_repos/permissive/443741085/sim/rv_sim.v
1: b'%Error: data/full_repos/permissive/443741085/sim/rv_sim.v:23: Cannot find include file: params.inc\n `include "params.inc" \n          ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443741085/sim,data/full_repos/permissive/443741085/params.inc\n             data/full_repos/permissive/443741085/sim,data/full_repos/permissive/443741085/params.inc.v\n             data/full_repos/permissive/443741085/sim,data/full_repos/permissive/443741085/params.inc.sv\n             params.inc\n             params.inc.v\n             params.inc.sv\n             obj_dir/params.inc\n             obj_dir/params.inc.v\n             obj_dir/params.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/443741085/sim/rv_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n always #PERIOD clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/443741085/sim/rv_sim.v:74: syntax error, unexpected \'@\'\n     repeat (5) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/443741085/sim/rv_sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n     #1 rst = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/443741085/sim/rv_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n     #TIMEOUT;\n     ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module rv_sim;


 localparam DPWIDTH = 32;
 localparam PERIOD = 10;
 localparam IMEM_FILE = "imem.hex";
 localparam DMEM_INFILE = "dmem_init.hex";
 localparam DMEM_OUTFILE = "dmem_out.hex";
 localparam IMEM_SIZE = 1024;
 localparam LOGIMEM_SIZE = 10;
 localparam DMEM_SIZE = 1024;
 localparam LOGDMEM_SIZE = 10;
 localparam TIMEOUT = 10000;


 `include "params.inc"

 reg clk, rst;

 reg [31:0] imem [0:IMEM_SIZE-1];
 reg [31:0] dmem [0:DMEM_SIZE-1];

 wire [DPWIDTH-1:0] imem_addr;
 wire [DPWIDTH-1:0] dmem_addr;
 wire [DPWIDTH-1:0] dmem_dataout;
 wire memrw;

 wire [LOGDMEM_SIZE-1:0] dmem_addr_short = dmem_addr[LOGDMEM_SIZE+1:2];
 wire [LOGDMEM_SIZE-1:0] imem_addr_short = imem_addr[LOGIMEM_SIZE+1:2];
 wire [DPWIDTH-1:0] dmem_datain = dmem[dmem_addr_short];
 wire [DPWIDTH-1:0] imem_datain = imem[imem_addr_short];


 always @(posedge clk)
     if (memrw)
         dmem[dmem_addr_short] <= dmem_dataout;



 rv_top dut
 (


     .imem_addr(imem_addr),
     .dmem_addr(dmem_addr),
     .dmem_dataout(dmem_dataout),
     .memrw(memrw),
     .dmem_datain(dmem_datain),
     .imem_datain(imem_datain),


     .clk(clk),
     .rst(rst)
 );



 always #PERIOD clk <= ~clk;


 initial
 begin
     clk = 1'b0;
     rst = 1'b1;
     $readmemh(IMEM_FILE, imem);
     $readmemh(DMEM_INFILE, dmem);
     repeat (5) @(posedge clk);
     #1 rst = 1'b0;

     #TIMEOUT;
     $display("No completion sequence detected. Probably something went wrong. Exiting on timeout.");
     $finish;
 end


 always @(posedge clk)
     if (memrw && (dmem_dataout == 32'hDEAD) && (dmem_addr == 32'hFFFF))
     begin
        $writememh(DMEM_OUTFILE, dmem);
        $display("Detected completion write sequence. Exiting.");
        $finish;
     end



 always @(posedge clk)
    if (!rst && (dut.ctl.current == 1))
        $display("*** New command start: PC = %X, IR = %X", dut.dp.pcc, dut.dp.ir);
 

 endmodule
module rv_sim;



 localparam DPWIDTH = 32;
 localparam PERIOD = 10;
 localparam IMEM_FILE = "imem.hex";
 localparam DMEM_INFILE = "dmem_init.hex";
 localparam DMEM_OUTFILE = "dmem_out.hex";
 localparam IMEM_SIZE = 1024;
 localparam LOGIMEM_SIZE = 10;
 localparam DMEM_SIZE = 1024;
 localparam LOGDMEM_SIZE = 10;
 localparam TIMEOUT = 10000;


 `include "params.inc"

 reg clk, rst;

 reg [31:0] imem [0:IMEM_SIZE-1];
 reg [31:0] dmem [0:DMEM_SIZE-1];

 wire [DPWIDTH-1:0] imem_addr;
 wire [DPWIDTH-1:0] dmem_addr;
 wire [DPWIDTH-1:0] dmem_dataout;
 wire memrw;

 wire [LOGDMEM_SIZE-1:0] dmem_addr_short = dmem_addr[LOGDMEM_SIZE+1:2];
 wire [LOGDMEM_SIZE-1:0] imem_addr_short = imem_addr[LOGIMEM_SIZE+1:2];
 wire [DPWIDTH-1:0] dmem_datain = dmem[dmem_addr_short];
 wire [DPWIDTH-1:0] imem_datain = imem[imem_addr_short];


 always @(posedge clk)
     if (memrw)
         dmem[dmem_addr_short] <= dmem_dataout;



 rv_top dut
 (


     .imem_addr(imem_addr),
     .dmem_addr(dmem_addr),
     .dmem_dataout(dmem_dataout),
     .memrw(memrw),
     .dmem_datain(dmem_datain),
     .imem_datain(imem_datain),


     .clk(clk),
     .rst(rst)
 );



 always #PERIOD clk <= ~clk;


 initial
 begin
     clk = 1'b0;
     rst = 1'b1;
     $readmemh(IMEM_FILE, imem);
     $readmemh(DMEM_INFILE, dmem);
     repeat (5) @(posedge clk);
     #1 rst = 1'b0;

     #TIMEOUT;
     $display("No completion sequence detected. Probably something went wrong. Exiting on timeout.");
     $finish;
 end


 always @(posedge clk)
     if (memrw && (dmem_dataout == 32'hDEAD) && (dmem_addr == 32'hFFFF))
     begin
        $writememh(DMEM_OUTFILE, dmem);
        $display("Detected completion write sequence. Exiting.");
        $finish;
     end



 always @(posedge clk)
    if (!rst && (dut.ctl.current == 1))
        $display("*** New command start: PC = %X, IR = %X", dut.dp.pcc, dut.dp.ir);
 

 endmodule