data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:196: Signal definition not found, creating implicitly: \'soc_reset\'\n  assign soc_reset = locked & c0_init_calib_complete;\n         ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:150: Cannot find file containing module: \'IBUFDS\'\n  IBUFDS diff_clk (.I(c0_sys_clk_p),\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class,data/full_repos/permissive/435997396/IBUFDS\n             data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class,data/full_repos/permissive/435997396/IBUFDS.v\n             data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class,data/full_repos/permissive/435997396/IBUFDS.sv\n             IBUFDS\n             IBUFDS.v\n             IBUFDS.sv\n             obj_dir/IBUFDS\n             obj_dir/IBUFDS.v\n             obj_dir/IBUFDS.sv\n%Error: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:154: Cannot find file containing module: \'clk_divider\'\n  clk_divider clk_div (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:198: Cannot find file containing module: \'vcu118mig\'\nvcu118mig ddr (\n^~~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:267: Cannot find file containing module: \'clk_converter\'\n   clk_converter clock_converter (\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/vcu118/c-class/fpga_top.v:354: Cannot find file containing module: \'mkSoc\'\n   mkSoc core(\n   ^~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module fpga_top#( parameter AXI_ID_WIDTH   = 4, parameter AXI_ADDR_WIDTH = 31) (

  input                   c0_sys_clk_p,
  input                   c0_sys_clk_n,

  input                   uart_SIN,
  output                  uart_SOUT,      

  output                  locked,
  output                  c0_ddr4_act_n,
  output [16:0]           c0_ddr4_adr,
  output [1:0]            c0_ddr4_ba,
  output [0:0]            c0_ddr4_bg,
  output [0:0]            c0_ddr4_cke,
  output [0:0]            c0_ddr4_odt,
  output [0:0]            c0_ddr4_cs_n,
  output [0:0]            c0_ddr4_ck_t,
  output [0:0]            c0_ddr4_ck_c,
  output                  c0_ddr4_reset_n,
  inout  [7:0]            c0_ddr4_dm_dbi_n,
  inout  [63:0]           c0_ddr4_dq,
  inout  [7:0]            c0_ddr4_dqs_t,
  inout  [7:0]            c0_ddr4_dqs_c,
  output                  c0_init_calib_complete,

  input [3:0]             ext_interrupts,

`ifndef JTAG_BSCAN2E
  input                   pin_tck,
  input                   pin_trst,
  input                   pin_tms,
  input                   pin_tdi,
  output                  pin_tdo,
`endif

  input         sys_rst);



  wire                              core_clk;
  wire sys_clk; 
  wire                              ddr3_main;
  wire                              ddr3_ref;
  wire                              c0_ddr4_ui_clk;
  wire                              c0_ddr4_ui_clk_sync_rst;
  reg                               c0_ddr4_aresetn;

  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_awid;
  wire [AXI_ADDR_WIDTH-1:0]         c0_ddr4_s_axi_awaddr;
  wire [7:0]                        c0_ddr4_s_axi_awlen;
  wire [2:0]                        c0_ddr4_s_axi_awsize;
  wire [1:0]                        c0_ddr4_s_axi_awburst;
  wire [0:0]                        c0_ddr4_s_axi_awlock;
  wire [3:0]                        c0_ddr4_s_axi_awcache;
  wire [2:0]                        c0_ddr4_s_axi_awprot;
  wire                              c0_ddr4_s_axi_awvalid;
  wire                              c0_ddr4_s_axi_awready;    
  wire [63:0]                       c0_ddr4_s_axi_wdata;
  wire [7:0]                        c0_ddr4_s_axi_wstrb;
  wire                              c0_ddr4_s_axi_wlast;
  wire                              c0_ddr4_s_axi_wvalid;
  wire                              c0_ddr4_s_axi_wready;   
  wire                              c0_ddr4_s_axi_bready;
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_bid;
  wire [1:0]                        c0_ddr4_s_axi_bresp;
  wire                              c0_ddr4_s_axi_bvalid;   
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_arid;
  wire [AXI_ADDR_WIDTH-1:0]         c0_ddr4_s_axi_araddr;
  wire [7:0]                        c0_ddr4_s_axi_arlen;
  wire [2:0]                        c0_ddr4_s_axi_arsize;
  wire [1:0]                        c0_ddr4_s_axi_arburst;
  wire [0:0]                        c0_ddr4_s_axi_arlock;
  wire [3:0]                        c0_ddr4_s_axi_arcache;
  wire [2:0]                        c0_ddr4_s_axi_arprot;
  wire                              c0_ddr4_s_axi_arvalid;
  wire                              c0_ddr4_s_axi_arready;    
  wire                              c0_ddr4_s_axi_rready;
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_rid;
  wire [63:0]                      c0_ddr4_s_axi_rdata;
  wire [1:0]                        c0_ddr4_s_axi_rresp;
  wire                              c0_ddr4_s_axi_rlast;
  wire                              c0_ddr4_s_axi_rvalid;   

  wire [AXI_ID_WIDTH-1:0]           s_axi_awid;
  wire [AXI_ADDR_WIDTH-1:0]         s_axi_awaddr;
  wire [7:0]                        s_axi_awlen;
  wire [2:0]                        s_axi_awsize;
  wire [1:0]                        s_axi_awburst;
  wire [0:0]                        s_axi_awlock;
  wire [3:0]                        s_axi_awcache;
  wire [2:0]                        s_axi_awprot;
  wire                              s_axi_awvalid;
  wire                              s_axi_awready;    
  wire [63:0]                       s_axi_wdata;
  wire [7:0]                        s_axi_wstrb;
  wire                              s_axi_wlast;
  wire                              s_axi_wvalid;
  wire                              s_axi_wready;
  wire                              s_axi_bready;
  wire [AXI_ID_WIDTH-1:0]           s_axi_bid;
  wire [1:0]                        s_axi_bresp;
  wire                              s_axi_bvalid;
  wire [AXI_ID_WIDTH-1:0]           s_axi_arid;
  wire [AXI_ADDR_WIDTH-1:0]         s_axi_araddr;
  wire [7:0]                        s_axi_arlen;
  wire [2:0]                        s_axi_arsize;
  wire [1:0]                        s_axi_arburst;
  wire [0:0]                        s_axi_arlock;
  wire [3:0]                        s_axi_arcache;
  wire [2:0]                        s_axi_arprot;
  wire                              s_axi_arvalid;
  wire                              s_axi_arready;
  wire                              s_axi_rready;
  wire [AXI_ID_WIDTH-1:0]           s_axi_rid;
  wire [63:0]                       s_axi_rdata;
  wire [1:0]                        s_axi_rresp;
  wire                              s_axi_rlast;
  wire                              s_axi_rvalid;   


  IBUFDS diff_clk (.I(c0_sys_clk_p),
                   .IB(c0_sys_clk_n),
                   .O(sys_clk));

  clk_divider clk_div (
                    .clk_in1(sys_clk),
                    .clk_out1(core_clk),
                    .resetn(sys_rst), 
                    .locked(locked) );



  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif


  wire [31:0] temp_s_axi_awaddr, temp_s_axi_araddr;
  assign s_axi_awaddr= temp_s_axi_awaddr [AXI_ADDR_WIDTH-1:0];
  assign s_axi_araddr= temp_s_axi_araddr [AXI_ADDR_WIDTH-1:0];
  assign soc_reset = locked & c0_init_calib_complete;

vcu118mig ddr (
  .c0_init_calib_complete(c0_init_calib_complete),
  .dbg_clk(),
  .c0_sys_clk_i(sys_clk),
  .dbg_bus(),
  .c0_ddr4_adr(c0_ddr4_adr),
  .c0_ddr4_ba(c0_ddr4_ba),
  .c0_ddr4_cke(c0_ddr4_cke),
  .c0_ddr4_cs_n(c0_ddr4_cs_n),
  .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
  .c0_ddr4_dq(c0_ddr4_dq),
  .c0_ddr4_dqs_c(c0_ddr4_dqs_c),
  .c0_ddr4_dqs_t(c0_ddr4_dqs_t),
  .c0_ddr4_odt(c0_ddr4_odt),
  .c0_ddr4_bg(c0_ddr4_bg),
  .c0_ddr4_reset_n(c0_ddr4_reset_n),
  .c0_ddr4_act_n(c0_ddr4_act_n),
  .c0_ddr4_ck_c(c0_ddr4_ck_c),
  .c0_ddr4_ck_t(c0_ddr4_ck_t),
  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),
  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),
  .c0_ddr4_aresetn(c0_ddr4_aresetn),
  .c0_ddr4_s_axi_awid(c0_ddr4_s_axi_awid),
  .c0_ddr4_s_axi_awaddr(c0_ddr4_s_axi_awaddr),
  .c0_ddr4_s_axi_awlen(c0_ddr4_s_axi_awlen),
  .c0_ddr4_s_axi_awsize(c0_ddr4_s_axi_awsize),
  .c0_ddr4_s_axi_awburst(c0_ddr4_s_axi_awburst),
  .c0_ddr4_s_axi_awlock(c0_ddr4_s_axi_awlock),
  .c0_ddr4_s_axi_awcache(c0_ddr4_s_axi_awcache),
  .c0_ddr4_s_axi_awprot(c0_ddr4_s_axi_awprot),
  .c0_ddr4_s_axi_awqos(c0_ddr4_s_axi_awqos),
  .c0_ddr4_s_axi_awvalid(c0_ddr4_s_axi_awvalid),
  .c0_ddr4_s_axi_awready(c0_ddr4_s_axi_awready),
  .c0_ddr4_s_axi_wdata(c0_ddr4_s_axi_wdata),
  .c0_ddr4_s_axi_wstrb(c0_ddr4_s_axi_wstrb),
  .c0_ddr4_s_axi_wlast(c0_ddr4_s_axi_wlast),
  .c0_ddr4_s_axi_wvalid(c0_ddr4_s_axi_wvalid),
  .c0_ddr4_s_axi_wready(c0_ddr4_s_axi_wready),
  .c0_ddr4_s_axi_bready(c0_ddr4_s_axi_bready),
  .c0_ddr4_s_axi_bid(c0_ddr4_s_axi_bid),
  .c0_ddr4_s_axi_bresp(c0_ddr4_s_axi_bresp),
  .c0_ddr4_s_axi_bvalid(c0_ddr4_s_axi_bvalid),
  .c0_ddr4_s_axi_arid(c0_ddr4_s_axi_arid),
  .c0_ddr4_s_axi_araddr(c0_ddr4_s_axi_araddr),
  .c0_ddr4_s_axi_arlen(c0_ddr4_s_axi_arlen),
  .c0_ddr4_s_axi_arsize(c0_ddr4_s_axi_arsize),
  .c0_ddr4_s_axi_arburst(c0_ddr4_s_axi_arburst),
  .c0_ddr4_s_axi_arlock(c0_ddr4_s_axi_arlock),
  .c0_ddr4_s_axi_arcache(c0_ddr4_s_axi_arcache),
  .c0_ddr4_s_axi_arprot(c0_ddr4_s_axi_arprot),
  .c0_ddr4_s_axi_arqos(c0_ddr4_s_axi_arqos),
  .c0_ddr4_s_axi_arvalid(c0_ddr4_s_axi_arvalid),
  .c0_ddr4_s_axi_arready(c0_ddr4_s_axi_arready),
  .c0_ddr4_s_axi_rready(c0_ddr4_s_axi_rready),
  .c0_ddr4_s_axi_rlast(c0_ddr4_s_axi_rlast),
  .c0_ddr4_s_axi_rvalid(c0_ddr4_s_axi_rvalid),
  .c0_ddr4_s_axi_rresp(c0_ddr4_s_axi_rresp),
  .c0_ddr4_s_axi_rid(c0_ddr4_s_axi_rid),
  .c0_ddr4_s_axi_rdata(c0_ddr4_s_axi_rdata),
  .sys_rst(sys_rst)
);


   always @(posedge c0_ddr4_ui_clk) begin
     c0_ddr4_aresetn <= ~c0_ddr4_ui_clk_sync_rst;
   end
   


   clk_converter clock_converter (
       .s_axi_aclk(core_clk),
       .s_axi_aresetn(soc_reset),
       .s_axi_awid(s_axi_awid),
       .s_axi_awaddr(s_axi_awaddr),
       .s_axi_awlen(s_axi_awlen),
       .s_axi_awsize(s_axi_awsize),
       .s_axi_awburst(s_axi_awburst),
       .s_axi_awlock(1'b0),
       .s_axi_awcache(4'b10),
       .s_axi_awprot(s_axi_awprot),
       .s_axi_awregion(4'b0),
       .s_axi_awqos(4'b0),
       .s_axi_awvalid(s_axi_awvalid),
       .s_axi_awready(s_axi_awready),
       .s_axi_wdata(s_axi_wdata),
       .s_axi_wstrb(s_axi_wstrb),
       .s_axi_wlast(s_axi_wlast),
       .s_axi_wvalid(s_axi_wvalid),
       .s_axi_wready(s_axi_wready),
       .s_axi_bid(s_axi_bid),
       .s_axi_bresp(s_axi_bresp),
       .s_axi_bvalid(s_axi_bvalid),
       .s_axi_bready(s_axi_bready),
       .s_axi_arid(s_axi_arid),
       .s_axi_araddr(s_axi_araddr),
       .s_axi_arlen(s_axi_arlen),
       .s_axi_arsize(s_axi_arsize),
       .s_axi_arburst(s_axi_arburst),
       .s_axi_arlock(1'b0),
       .s_axi_arcache(4'b10),
       .s_axi_arprot(s_axi_arprot),
       .s_axi_arregion(4'b0),
       .s_axi_arqos(4'b0),
       .s_axi_arvalid(s_axi_arvalid),
       .s_axi_arready(s_axi_arready),
       .s_axi_rid(s_axi_rid),
       .s_axi_rdata(s_axi_rdata),
       .s_axi_rresp(s_axi_rresp),
       .s_axi_rlast(s_axi_rlast),
       .s_axi_rvalid(s_axi_rvalid),
       .s_axi_rready(s_axi_rready),
       .m_axi_aclk(c0_ddr4_ui_clk),
       .m_axi_aresetn(c0_ddr4_aresetn),
       .m_axi_awid(c0_ddr4_s_axi_awid),
       .m_axi_awaddr(c0_ddr4_s_axi_awaddr),
       .m_axi_awlen(c0_ddr4_s_axi_awlen),
       .m_axi_awsize(c0_ddr4_s_axi_awsize),
       .m_axi_awburst(c0_ddr4_s_axi_awburst),
       .m_axi_awlock(c0_ddr4_s_axi_awlock),
       .m_axi_awcache(c0_ddr4_s_axi_awcache),
       .m_axi_awprot(c0_ddr4_s_axi_awprot),
       .m_axi_awregion(),
       .m_axi_awqos(),
       .m_axi_awvalid(c0_ddr4_s_axi_awvalid),
       .m_axi_awready(c0_ddr4_s_axi_awready),
       .m_axi_wdata(c0_ddr4_s_axi_wdata),
       .m_axi_wstrb(c0_ddr4_s_axi_wstrb),
       .m_axi_wlast(c0_ddr4_s_axi_wlast),
       .m_axi_wvalid(c0_ddr4_s_axi_wvalid),
       .m_axi_wready(c0_ddr4_s_axi_wready),
       .m_axi_bid(c0_ddr4_s_axi_bid),
       .m_axi_bresp(c0_ddr4_s_axi_bresp),
       .m_axi_bvalid(c0_ddr4_s_axi_bvalid),
       .m_axi_bready(c0_ddr4_s_axi_bready),
       .m_axi_arid(c0_ddr4_s_axi_arid),
       .m_axi_araddr(c0_ddr4_s_axi_araddr),
       .m_axi_arlen(c0_ddr4_s_axi_arlen),
       .m_axi_arsize(c0_ddr4_s_axi_arsize),
       .m_axi_arburst(c0_ddr4_s_axi_arburst),
       .m_axi_arlock(c0_ddr4_s_axi_arlock),
       .m_axi_arcache(c0_ddr4_s_axi_arcache),
       .m_axi_arprot(c0_ddr4_s_axi_arprot),
       .m_axi_arregion(),
       .m_axi_arqos(),
       .m_axi_arvalid(c0_ddr4_s_axi_arvalid),
       .m_axi_arready(c0_ddr4_s_axi_arready),
       .m_axi_rid(c0_ddr4_s_axi_rid),
       .m_axi_rdata(c0_ddr4_s_axi_rdata),
       .m_axi_rresp(c0_ddr4_s_axi_rresp),
       .m_axi_rlast(c0_ddr4_s_axi_rlast),
       .m_axi_rvalid(c0_ddr4_s_axi_rvalid), 
       .m_axi_rready(c0_ddr4_s_axi_rready)
   );

   

   mkSoc core(

       .CLK(core_clk),
       .RST_N(soc_reset),
`ifndef JTAG_BSCAN2E       

       .CLK_tck_clk(pin_tck),
       .RST_N_trst(pin_trst),
       .wire_tms_tms_in(pin_tms),
       .wire_tdi_tdi_in(pin_tdi),
       .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),     
        .wire_run_test_run_test_in(wire_run_test),     
        .wire_sel_sel_in(wire_sel),     
        .wire_shift_shift_in(wire_shift),     
        .wire_tdi_tdi_in(wire_tdi),     
        .wire_tms_tms_in(wire_tms),     
        .wire_update_update_in(wire_update),     
        .wire_tdo(wire_tdo),
`endif

       .uart_io_SIN(uart_SIN),
       .uart_io_SOUT(uart_SOUT),


       .ma_ext_interrupts_i(ext_interrupts),


		   .mem_master_AWVALID (s_axi_awvalid),
		   .mem_master_AWADDR  (temp_s_axi_awaddr),
		   .mem_master_AWSIZE  (s_axi_awsize),
		   .mem_master_AWPROT  (s_axi_awprot),
		   .mem_master_AWLEN   (s_axi_awlen),
		   .mem_master_AWBURST (s_axi_awburst),
		   .mem_master_AWID    (s_axi_awid),
		   .mem_master_AWREADY (s_axi_awready),
                
		   .mem_master_WVALID  (s_axi_wvalid),
		   .mem_master_WDATA   (s_axi_wdata),
		   .mem_master_WSTRB   (s_axi_wstrb),
		   .mem_master_WLAST   (s_axi_wlast),
		   .mem_master_WID     (),
		   .mem_master_WREADY  (s_axi_wready),
                
		   .mem_master_BVALID  (s_axi_bvalid),
		   .mem_master_BRESP   (s_axi_bresp),
		   .mem_master_BID     (s_axi_bid),
		   .mem_master_BREADY  (s_axi_bready),
                
		   .mem_master_ARVALID (s_axi_arvalid),
		   .mem_master_ARADDR  (temp_s_axi_araddr),
		   .mem_master_ARSIZE  (s_axi_arsize),
		   .mem_master_ARPROT  (s_axi_arprot),
		   .mem_master_ARLEN   (s_axi_arlen),
		   .mem_master_ARBURST (s_axi_arburst),
		   .mem_master_ARID    (s_axi_arid),
		   .mem_master_ARREADY (s_axi_arready),
                
		   .mem_master_RVALID (s_axi_rvalid),
		   .mem_master_RRESP  (s_axi_rresp),
		   .mem_master_RDATA  (s_axi_rdata),
		   .mem_master_RLAST  (s_axi_rlast),
		   .mem_master_RID    (s_axi_rid),
		   .mem_master_RREADY(s_axi_rready)
   );

endmodule
module fpga_top#( parameter AXI_ID_WIDTH   = 4, parameter AXI_ADDR_WIDTH = 31) (

  input                   c0_sys_clk_p,
  input                   c0_sys_clk_n,

  input                   uart_SIN,
  output                  uart_SOUT,      

  output                  locked,
  output                  c0_ddr4_act_n,
  output [16:0]           c0_ddr4_adr,
  output [1:0]            c0_ddr4_ba,
  output [0:0]            c0_ddr4_bg,
  output [0:0]            c0_ddr4_cke,
  output [0:0]            c0_ddr4_odt,
  output [0:0]            c0_ddr4_cs_n,
  output [0:0]            c0_ddr4_ck_t,
  output [0:0]            c0_ddr4_ck_c,
  output                  c0_ddr4_reset_n,
  inout  [7:0]            c0_ddr4_dm_dbi_n,
  inout  [63:0]           c0_ddr4_dq,
  inout  [7:0]            c0_ddr4_dqs_t,
  inout  [7:0]            c0_ddr4_dqs_c,
  output                  c0_init_calib_complete,

  input [3:0]             ext_interrupts,

`ifndef JTAG_BSCAN2E
  input                   pin_tck,
  input                   pin_trst,
  input                   pin_tms,
  input                   pin_tdi,
  output                  pin_tdo,
`endif

  input         sys_rst);




  wire                              core_clk;
  wire sys_clk; 
  wire                              ddr3_main;
  wire                              ddr3_ref;
  wire                              c0_ddr4_ui_clk;
  wire                              c0_ddr4_ui_clk_sync_rst;
  reg                               c0_ddr4_aresetn;

  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_awid;
  wire [AXI_ADDR_WIDTH-1:0]         c0_ddr4_s_axi_awaddr;
  wire [7:0]                        c0_ddr4_s_axi_awlen;
  wire [2:0]                        c0_ddr4_s_axi_awsize;
  wire [1:0]                        c0_ddr4_s_axi_awburst;
  wire [0:0]                        c0_ddr4_s_axi_awlock;
  wire [3:0]                        c0_ddr4_s_axi_awcache;
  wire [2:0]                        c0_ddr4_s_axi_awprot;
  wire                              c0_ddr4_s_axi_awvalid;
  wire                              c0_ddr4_s_axi_awready;    
  wire [63:0]                       c0_ddr4_s_axi_wdata;
  wire [7:0]                        c0_ddr4_s_axi_wstrb;
  wire                              c0_ddr4_s_axi_wlast;
  wire                              c0_ddr4_s_axi_wvalid;
  wire                              c0_ddr4_s_axi_wready;   
  wire                              c0_ddr4_s_axi_bready;
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_bid;
  wire [1:0]                        c0_ddr4_s_axi_bresp;
  wire                              c0_ddr4_s_axi_bvalid;   
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_arid;
  wire [AXI_ADDR_WIDTH-1:0]         c0_ddr4_s_axi_araddr;
  wire [7:0]                        c0_ddr4_s_axi_arlen;
  wire [2:0]                        c0_ddr4_s_axi_arsize;
  wire [1:0]                        c0_ddr4_s_axi_arburst;
  wire [0:0]                        c0_ddr4_s_axi_arlock;
  wire [3:0]                        c0_ddr4_s_axi_arcache;
  wire [2:0]                        c0_ddr4_s_axi_arprot;
  wire                              c0_ddr4_s_axi_arvalid;
  wire                              c0_ddr4_s_axi_arready;    
  wire                              c0_ddr4_s_axi_rready;
  wire [AXI_ID_WIDTH-1:0]           c0_ddr4_s_axi_rid;
  wire [63:0]                      c0_ddr4_s_axi_rdata;
  wire [1:0]                        c0_ddr4_s_axi_rresp;
  wire                              c0_ddr4_s_axi_rlast;
  wire                              c0_ddr4_s_axi_rvalid;   

  wire [AXI_ID_WIDTH-1:0]           s_axi_awid;
  wire [AXI_ADDR_WIDTH-1:0]         s_axi_awaddr;
  wire [7:0]                        s_axi_awlen;
  wire [2:0]                        s_axi_awsize;
  wire [1:0]                        s_axi_awburst;
  wire [0:0]                        s_axi_awlock;
  wire [3:0]                        s_axi_awcache;
  wire [2:0]                        s_axi_awprot;
  wire                              s_axi_awvalid;
  wire                              s_axi_awready;    
  wire [63:0]                       s_axi_wdata;
  wire [7:0]                        s_axi_wstrb;
  wire                              s_axi_wlast;
  wire                              s_axi_wvalid;
  wire                              s_axi_wready;
  wire                              s_axi_bready;
  wire [AXI_ID_WIDTH-1:0]           s_axi_bid;
  wire [1:0]                        s_axi_bresp;
  wire                              s_axi_bvalid;
  wire [AXI_ID_WIDTH-1:0]           s_axi_arid;
  wire [AXI_ADDR_WIDTH-1:0]         s_axi_araddr;
  wire [7:0]                        s_axi_arlen;
  wire [2:0]                        s_axi_arsize;
  wire [1:0]                        s_axi_arburst;
  wire [0:0]                        s_axi_arlock;
  wire [3:0]                        s_axi_arcache;
  wire [2:0]                        s_axi_arprot;
  wire                              s_axi_arvalid;
  wire                              s_axi_arready;
  wire                              s_axi_rready;
  wire [AXI_ID_WIDTH-1:0]           s_axi_rid;
  wire [63:0]                       s_axi_rdata;
  wire [1:0]                        s_axi_rresp;
  wire                              s_axi_rlast;
  wire                              s_axi_rvalid;   


  IBUFDS diff_clk (.I(c0_sys_clk_p),
                   .IB(c0_sys_clk_n),
                   .O(sys_clk));

  clk_divider clk_div (
                    .clk_in1(sys_clk),
                    .clk_out1(core_clk),
                    .resetn(sys_rst), 
                    .locked(locked) );



  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif


  wire [31:0] temp_s_axi_awaddr, temp_s_axi_araddr;
  assign s_axi_awaddr= temp_s_axi_awaddr [AXI_ADDR_WIDTH-1:0];
  assign s_axi_araddr= temp_s_axi_araddr [AXI_ADDR_WIDTH-1:0];
  assign soc_reset = locked & c0_init_calib_complete;

vcu118mig ddr (
  .c0_init_calib_complete(c0_init_calib_complete),
  .dbg_clk(),
  .c0_sys_clk_i(sys_clk),
  .dbg_bus(),
  .c0_ddr4_adr(c0_ddr4_adr),
  .c0_ddr4_ba(c0_ddr4_ba),
  .c0_ddr4_cke(c0_ddr4_cke),
  .c0_ddr4_cs_n(c0_ddr4_cs_n),
  .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
  .c0_ddr4_dq(c0_ddr4_dq),
  .c0_ddr4_dqs_c(c0_ddr4_dqs_c),
  .c0_ddr4_dqs_t(c0_ddr4_dqs_t),
  .c0_ddr4_odt(c0_ddr4_odt),
  .c0_ddr4_bg(c0_ddr4_bg),
  .c0_ddr4_reset_n(c0_ddr4_reset_n),
  .c0_ddr4_act_n(c0_ddr4_act_n),
  .c0_ddr4_ck_c(c0_ddr4_ck_c),
  .c0_ddr4_ck_t(c0_ddr4_ck_t),
  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),
  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),
  .c0_ddr4_aresetn(c0_ddr4_aresetn),
  .c0_ddr4_s_axi_awid(c0_ddr4_s_axi_awid),
  .c0_ddr4_s_axi_awaddr(c0_ddr4_s_axi_awaddr),
  .c0_ddr4_s_axi_awlen(c0_ddr4_s_axi_awlen),
  .c0_ddr4_s_axi_awsize(c0_ddr4_s_axi_awsize),
  .c0_ddr4_s_axi_awburst(c0_ddr4_s_axi_awburst),
  .c0_ddr4_s_axi_awlock(c0_ddr4_s_axi_awlock),
  .c0_ddr4_s_axi_awcache(c0_ddr4_s_axi_awcache),
  .c0_ddr4_s_axi_awprot(c0_ddr4_s_axi_awprot),
  .c0_ddr4_s_axi_awqos(c0_ddr4_s_axi_awqos),
  .c0_ddr4_s_axi_awvalid(c0_ddr4_s_axi_awvalid),
  .c0_ddr4_s_axi_awready(c0_ddr4_s_axi_awready),
  .c0_ddr4_s_axi_wdata(c0_ddr4_s_axi_wdata),
  .c0_ddr4_s_axi_wstrb(c0_ddr4_s_axi_wstrb),
  .c0_ddr4_s_axi_wlast(c0_ddr4_s_axi_wlast),
  .c0_ddr4_s_axi_wvalid(c0_ddr4_s_axi_wvalid),
  .c0_ddr4_s_axi_wready(c0_ddr4_s_axi_wready),
  .c0_ddr4_s_axi_bready(c0_ddr4_s_axi_bready),
  .c0_ddr4_s_axi_bid(c0_ddr4_s_axi_bid),
  .c0_ddr4_s_axi_bresp(c0_ddr4_s_axi_bresp),
  .c0_ddr4_s_axi_bvalid(c0_ddr4_s_axi_bvalid),
  .c0_ddr4_s_axi_arid(c0_ddr4_s_axi_arid),
  .c0_ddr4_s_axi_araddr(c0_ddr4_s_axi_araddr),
  .c0_ddr4_s_axi_arlen(c0_ddr4_s_axi_arlen),
  .c0_ddr4_s_axi_arsize(c0_ddr4_s_axi_arsize),
  .c0_ddr4_s_axi_arburst(c0_ddr4_s_axi_arburst),
  .c0_ddr4_s_axi_arlock(c0_ddr4_s_axi_arlock),
  .c0_ddr4_s_axi_arcache(c0_ddr4_s_axi_arcache),
  .c0_ddr4_s_axi_arprot(c0_ddr4_s_axi_arprot),
  .c0_ddr4_s_axi_arqos(c0_ddr4_s_axi_arqos),
  .c0_ddr4_s_axi_arvalid(c0_ddr4_s_axi_arvalid),
  .c0_ddr4_s_axi_arready(c0_ddr4_s_axi_arready),
  .c0_ddr4_s_axi_rready(c0_ddr4_s_axi_rready),
  .c0_ddr4_s_axi_rlast(c0_ddr4_s_axi_rlast),
  .c0_ddr4_s_axi_rvalid(c0_ddr4_s_axi_rvalid),
  .c0_ddr4_s_axi_rresp(c0_ddr4_s_axi_rresp),
  .c0_ddr4_s_axi_rid(c0_ddr4_s_axi_rid),
  .c0_ddr4_s_axi_rdata(c0_ddr4_s_axi_rdata),
  .sys_rst(sys_rst)
);


   always @(posedge c0_ddr4_ui_clk) begin
     c0_ddr4_aresetn <= ~c0_ddr4_ui_clk_sync_rst;
   end
   


   clk_converter clock_converter (
       .s_axi_aclk(core_clk),
       .s_axi_aresetn(soc_reset),
       .s_axi_awid(s_axi_awid),
       .s_axi_awaddr(s_axi_awaddr),
       .s_axi_awlen(s_axi_awlen),
       .s_axi_awsize(s_axi_awsize),
       .s_axi_awburst(s_axi_awburst),
       .s_axi_awlock(1'b0),
       .s_axi_awcache(4'b10),
       .s_axi_awprot(s_axi_awprot),
       .s_axi_awregion(4'b0),
       .s_axi_awqos(4'b0),
       .s_axi_awvalid(s_axi_awvalid),
       .s_axi_awready(s_axi_awready),
       .s_axi_wdata(s_axi_wdata),
       .s_axi_wstrb(s_axi_wstrb),
       .s_axi_wlast(s_axi_wlast),
       .s_axi_wvalid(s_axi_wvalid),
       .s_axi_wready(s_axi_wready),
       .s_axi_bid(s_axi_bid),
       .s_axi_bresp(s_axi_bresp),
       .s_axi_bvalid(s_axi_bvalid),
       .s_axi_bready(s_axi_bready),
       .s_axi_arid(s_axi_arid),
       .s_axi_araddr(s_axi_araddr),
       .s_axi_arlen(s_axi_arlen),
       .s_axi_arsize(s_axi_arsize),
       .s_axi_arburst(s_axi_arburst),
       .s_axi_arlock(1'b0),
       .s_axi_arcache(4'b10),
       .s_axi_arprot(s_axi_arprot),
       .s_axi_arregion(4'b0),
       .s_axi_arqos(4'b0),
       .s_axi_arvalid(s_axi_arvalid),
       .s_axi_arready(s_axi_arready),
       .s_axi_rid(s_axi_rid),
       .s_axi_rdata(s_axi_rdata),
       .s_axi_rresp(s_axi_rresp),
       .s_axi_rlast(s_axi_rlast),
       .s_axi_rvalid(s_axi_rvalid),
       .s_axi_rready(s_axi_rready),
       .m_axi_aclk(c0_ddr4_ui_clk),
       .m_axi_aresetn(c0_ddr4_aresetn),
       .m_axi_awid(c0_ddr4_s_axi_awid),
       .m_axi_awaddr(c0_ddr4_s_axi_awaddr),
       .m_axi_awlen(c0_ddr4_s_axi_awlen),
       .m_axi_awsize(c0_ddr4_s_axi_awsize),
       .m_axi_awburst(c0_ddr4_s_axi_awburst),
       .m_axi_awlock(c0_ddr4_s_axi_awlock),
       .m_axi_awcache(c0_ddr4_s_axi_awcache),
       .m_axi_awprot(c0_ddr4_s_axi_awprot),
       .m_axi_awregion(),
       .m_axi_awqos(),
       .m_axi_awvalid(c0_ddr4_s_axi_awvalid),
       .m_axi_awready(c0_ddr4_s_axi_awready),
       .m_axi_wdata(c0_ddr4_s_axi_wdata),
       .m_axi_wstrb(c0_ddr4_s_axi_wstrb),
       .m_axi_wlast(c0_ddr4_s_axi_wlast),
       .m_axi_wvalid(c0_ddr4_s_axi_wvalid),
       .m_axi_wready(c0_ddr4_s_axi_wready),
       .m_axi_bid(c0_ddr4_s_axi_bid),
       .m_axi_bresp(c0_ddr4_s_axi_bresp),
       .m_axi_bvalid(c0_ddr4_s_axi_bvalid),
       .m_axi_bready(c0_ddr4_s_axi_bready),
       .m_axi_arid(c0_ddr4_s_axi_arid),
       .m_axi_araddr(c0_ddr4_s_axi_araddr),
       .m_axi_arlen(c0_ddr4_s_axi_arlen),
       .m_axi_arsize(c0_ddr4_s_axi_arsize),
       .m_axi_arburst(c0_ddr4_s_axi_arburst),
       .m_axi_arlock(c0_ddr4_s_axi_arlock),
       .m_axi_arcache(c0_ddr4_s_axi_arcache),
       .m_axi_arprot(c0_ddr4_s_axi_arprot),
       .m_axi_arregion(),
       .m_axi_arqos(),
       .m_axi_arvalid(c0_ddr4_s_axi_arvalid),
       .m_axi_arready(c0_ddr4_s_axi_arready),
       .m_axi_rid(c0_ddr4_s_axi_rid),
       .m_axi_rdata(c0_ddr4_s_axi_rdata),
       .m_axi_rresp(c0_ddr4_s_axi_rresp),
       .m_axi_rlast(c0_ddr4_s_axi_rlast),
       .m_axi_rvalid(c0_ddr4_s_axi_rvalid), 
       .m_axi_rready(c0_ddr4_s_axi_rready)
   );

   

   mkSoc core(

       .CLK(core_clk),
       .RST_N(soc_reset),
`ifndef JTAG_BSCAN2E       

       .CLK_tck_clk(pin_tck),
       .RST_N_trst(pin_trst),
       .wire_tms_tms_in(pin_tms),
       .wire_tdi_tdi_in(pin_tdi),
       .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),     
        .wire_run_test_run_test_in(wire_run_test),     
        .wire_sel_sel_in(wire_sel),     
        .wire_shift_shift_in(wire_shift),     
        .wire_tdi_tdi_in(wire_tdi),     
        .wire_tms_tms_in(wire_tms),     
        .wire_update_update_in(wire_update),     
        .wire_tdo(wire_tdo),
`endif

       .uart_io_SIN(uart_SIN),
       .uart_io_SOUT(uart_SOUT),


       .ma_ext_interrupts_i(ext_interrupts),


		   .mem_master_AWVALID (s_axi_awvalid),
		   .mem_master_AWADDR  (temp_s_axi_awaddr),
		   .mem_master_AWSIZE  (s_axi_awsize),
		   .mem_master_AWPROT  (s_axi_awprot),
		   .mem_master_AWLEN   (s_axi_awlen),
		   .mem_master_AWBURST (s_axi_awburst),
		   .mem_master_AWID    (s_axi_awid),
		   .mem_master_AWREADY (s_axi_awready),
                
		   .mem_master_WVALID  (s_axi_wvalid),
		   .mem_master_WDATA   (s_axi_wdata),
		   .mem_master_WSTRB   (s_axi_wstrb),
		   .mem_master_WLAST   (s_axi_wlast),
		   .mem_master_WID     (),
		   .mem_master_WREADY  (s_axi_wready),
                
		   .mem_master_BVALID  (s_axi_bvalid),
		   .mem_master_BRESP   (s_axi_bresp),
		   .mem_master_BID     (s_axi_bid),
		   .mem_master_BREADY  (s_axi_bready),
                
		   .mem_master_ARVALID (s_axi_arvalid),
		   .mem_master_ARADDR  (temp_s_axi_araddr),
		   .mem_master_ARSIZE  (s_axi_arsize),
		   .mem_master_ARPROT  (s_axi_arprot),
		   .mem_master_ARLEN   (s_axi_arlen),
		   .mem_master_ARBURST (s_axi_arburst),
		   .mem_master_ARID    (s_axi_arid),
		   .mem_master_ARREADY (s_axi_arready),
                
		   .mem_master_RVALID (s_axi_rvalid),
		   .mem_master_RRESP  (s_axi_rresp),
		   .mem_master_RDATA  (s_axi_rdata),
		   .mem_master_RLAST  (s_axi_rlast),
		   .mem_master_RID    (s_axi_rid),
		   .mem_master_RREADY(s_axi_rready)
   );

endmodule