data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_module.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_module.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_module.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module tcam_module
#(
   parameter   TCAM_ADDR_WIDTH         = 4,
   parameter   TCAM_DATA_WIDTH         = 32
)
(
   input                                     CLK,
   input                                     RSTN,

   input                                     WR,
   input          [TCAM_ADDR_WIDTH-1:0]      ADDR_WR,
   input          [TCAM_DATA_WIDTH-1:0]      DIN,
   input          [TCAM_DATA_WIDTH-1:0]      DIN_MASK,
   output   reg                              BUSY,

`ifdef EN_TCAM_RD
   input                                     RD,
   input          [TCAM_ADDR_WIDTH-1:0]      ADDR_RD,
   output   reg   [TCAM_DATA_WIDTH-1:0]      DOUT,
`endif

   input          [TCAM_DATA_WIDTH-1:0]      CAM_DIN,
   input          [TCAM_DATA_WIDTH-1:0]      CAM_DATA_MASK,
   output   reg                              MATCH,
   output   reg   [TCAM_ADDR_WIDTH-1:0]      MATCH_ADDR
);

reg   [TCAM_ADDR_WIDTH-1:0]   rADDR_WR, rADDR_RD;
reg   [TCAM_DATA_WIDTH-1:0]   rDIN, rDIN_MASK, rCAM_DIN, rCAM_DATA_MASK;
reg   rWR, rRD;

always @(posedge CLK)
   if (~RSTN) begin
      rWR               <= 0;
      rRD               <= 0;
      rADDR_WR          <= 0;
      rADDR_RD          <= 0;
      rDIN              <= 0;
      rDIN_MASK         <= 0;
      rCAM_DIN          <= 0;
      rCAM_DATA_MASK    <= 0;
   end
   else begin
      rWR               <= WR;
      `ifdef EN_TCAM_RD
      rRD               <= RD;
      rADDR_RD          <= ADDR_RD;
      `endif
      rADDR_WR          <= ADDR_WR;
      rDIN              <= DIN;
      rDIN_MASK         <= DIN_MASK;
      rCAM_DIN          <= CAM_DIN;
      rCAM_DATA_MASK    <= CAM_DATA_MASK;
   end


`ifdef XIL_TCAM_USE

wire  [TCAM_ADDR_WIDTH-1:0]   wMATCH_ADDR;
wire  wMATCH, wBUSY;

always @(posedge CLK)
   if (~RSTN) begin
      BUSY        <= 0;
      MATCH       <= 0;
      MATCH_ADDR  <= 0;
   end
   else begin
      BUSY        <= wBUSY;
      MATCH       <= wMATCH;
      MATCH_ADDR  <= wMATCH_ADDR;
   end

tcam
#(
   .C_TCAM_ADDR_WIDTH   (  TCAM_ADDR_WIDTH   ),
   .C_TCAM_DATA_WIDTH   (  TCAM_DATA_WIDTH   )
)
xil_tcam
(
   .CLK                 (  CLK               ), 
   .WE                  (  rWR               ), 
   .ADDR_WR             (  rADDR_WR          ),
   .DIN                 (  rDIN              ), 
   .DATA_MASK           (  rDIN_MASK         ), 
   .BUSY                (  wBUSY             ), 

   .CMP_DIN             (  rCAM_DIN          ),
   .CMP_DATA_MASK       (  rCAM_DATA_MASK    ),
   .MATCH               (  wMATCH            ), 
   .MATCH_ADDR          (  wMATCH_ADDR       )
);








































































































































`else

wire  [TCAM_ADDR_WIDTH-1:0]   wMATCH_ADDR;
wire  wMATCH;

always @(posedge CLK)
   if (~RSTN) begin
      BUSY        <= 0;
      MATCH       <= 0;
      MATCH_ADDR  <= 0;
   end
   else begin
      BUSY        <= WR;
      MATCH       <= wMATCH;
      MATCH_ADDR  <= wMATCH_ADDR;
   end


tcam_rtl
#(
   .ADDR_WIDTH    (  TCAM_ADDR_WIDTH         ),
   .DATA_WIDTH    (  TCAM_DATA_WIDTH         )
)
reg_dst_ip_table
(
   .CLK           (  CLK                     ),
   .WR            (  rWR                     ),
   .ADDR_WR       (  rADDR_WR                ),
   .DIN           (  rDIN                    ),
   .DIN_MASK      (  {TCAM_DATA_WIDTH{1'b1}} ),

`ifdef EN_TCAM_RD
   .RD            (  0                       ),
   .ADDR_RD       (  0                       ),
   .DOUT          (                          ),
`endif

   .CAM_IN        (  rCAM_DIN                ),
   .MATCH         (  wMATCH                  ),
   .MATCH_ADDR    (  wMATCH_ADDR             )
);

`endif


endmodule
module tcam_module
#(
   parameter   TCAM_ADDR_WIDTH         = 4,
   parameter   TCAM_DATA_WIDTH         = 32
)
(
   input                                     CLK,
   input                                     RSTN,

   input                                     WR,
   input          [TCAM_ADDR_WIDTH-1:0]      ADDR_WR,
   input          [TCAM_DATA_WIDTH-1:0]      DIN,
   input          [TCAM_DATA_WIDTH-1:0]      DIN_MASK,
   output   reg                              BUSY,

`ifdef EN_TCAM_RD
   input                                     RD,
   input          [TCAM_ADDR_WIDTH-1:0]      ADDR_RD,
   output   reg   [TCAM_DATA_WIDTH-1:0]      DOUT,
`endif

   input          [TCAM_DATA_WIDTH-1:0]      CAM_DIN,
   input          [TCAM_DATA_WIDTH-1:0]      CAM_DATA_MASK,
   output   reg                              MATCH,
   output   reg   [TCAM_ADDR_WIDTH-1:0]      MATCH_ADDR
);


reg   [TCAM_ADDR_WIDTH-1:0]   rADDR_WR, rADDR_RD;
reg   [TCAM_DATA_WIDTH-1:0]   rDIN, rDIN_MASK, rCAM_DIN, rCAM_DATA_MASK;
reg   rWR, rRD;

always @(posedge CLK)
   if (~RSTN) begin
      rWR               <= 0;
      rRD               <= 0;
      rADDR_WR          <= 0;
      rADDR_RD          <= 0;
      rDIN              <= 0;
      rDIN_MASK         <= 0;
      rCAM_DIN          <= 0;
      rCAM_DATA_MASK    <= 0;
   end
   else begin
      rWR               <= WR;
      `ifdef EN_TCAM_RD
      rRD               <= RD;
      rADDR_RD          <= ADDR_RD;
      `endif
      rADDR_WR          <= ADDR_WR;
      rDIN              <= DIN;
      rDIN_MASK         <= DIN_MASK;
      rCAM_DIN          <= CAM_DIN;
      rCAM_DATA_MASK    <= CAM_DATA_MASK;
   end


`ifdef XIL_TCAM_USE

wire  [TCAM_ADDR_WIDTH-1:0]   wMATCH_ADDR;
wire  wMATCH, wBUSY;

always @(posedge CLK)
   if (~RSTN) begin
      BUSY        <= 0;
      MATCH       <= 0;
      MATCH_ADDR  <= 0;
   end
   else begin
      BUSY        <= wBUSY;
      MATCH       <= wMATCH;
      MATCH_ADDR  <= wMATCH_ADDR;
   end

tcam
#(
   .C_TCAM_ADDR_WIDTH   (  TCAM_ADDR_WIDTH   ),
   .C_TCAM_DATA_WIDTH   (  TCAM_DATA_WIDTH   )
)
xil_tcam
(
   .CLK                 (  CLK               ), 
   .WE                  (  rWR               ), 
   .ADDR_WR             (  rADDR_WR          ),
   .DIN                 (  rDIN              ), 
   .DATA_MASK           (  rDIN_MASK         ), 
   .BUSY                (  wBUSY             ), 

   .CMP_DIN             (  rCAM_DIN          ),
   .CMP_DATA_MASK       (  rCAM_DATA_MASK    ),
   .MATCH               (  wMATCH            ), 
   .MATCH_ADDR          (  wMATCH_ADDR       )
);








































































































































`else

wire  [TCAM_ADDR_WIDTH-1:0]   wMATCH_ADDR;
wire  wMATCH;

always @(posedge CLK)
   if (~RSTN) begin
      BUSY        <= 0;
      MATCH       <= 0;
      MATCH_ADDR  <= 0;
   end
   else begin
      BUSY        <= WR;
      MATCH       <= wMATCH;
      MATCH_ADDR  <= wMATCH_ADDR;
   end


tcam_rtl
#(
   .ADDR_WIDTH    (  TCAM_ADDR_WIDTH         ),
   .DATA_WIDTH    (  TCAM_DATA_WIDTH         )
)
reg_dst_ip_table
(
   .CLK           (  CLK                     ),
   .WR            (  rWR                     ),
   .ADDR_WR       (  rADDR_WR                ),
   .DIN           (  rDIN                    ),
   .DIN_MASK      (  {TCAM_DATA_WIDTH{1'b1}} ),

`ifdef EN_TCAM_RD
   .RD            (  0                       ),
   .ADDR_RD       (  0                       ),
   .DOUT          (                          ),
`endif

   .CAM_IN        (  rCAM_DIN                ),
   .MATCH         (  wMATCH                  ),
   .MATCH_ADDR    (  wMATCH_ADDR             )
);

`endif


endmodule