data/full_repos/permissive/447976230/fpga/usrp2/custom/custom_dsp_tx.v
data/verilator_xmls/c0be6510-41bd-4781-9241-29e3434cd70e.xml
module custom_dsp_tx
#(

    parameter WIDTH = 24
)
(

    input clock,
    input reset,
    input clear,
    input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output [WIDTH-1:0] frontend_i,
    output [WIDTH-1:0] frontend_q,


    input [WIDTH-1:0] duc_out_i,
    input [WIDTH-1:0] duc_out_q,


    output [31:0] duc_in_sample,
    input duc_in_strobe,
    output duc_in_enable,


    input [31:0] bb_sample,
    output bb_strobe
);

    assign frontend_i = duc_out_i;
    assign frontend_q = duc_out_q;
    assign duc_in_sample = bb_sample;
    assign bb_strobe = duc_in_strobe;
    assign duc_in_enable = enable;

endmodule
module custom_dsp_tx
#(

    parameter WIDTH = 24
)
(

    input clock,
    input reset,
    input clear,
    input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output [WIDTH-1:0] frontend_i,
    output [WIDTH-1:0] frontend_q,


    input [WIDTH-1:0] duc_out_i,
    input [WIDTH-1:0] duc_out_q,


    output [31:0] duc_in_sample,
    input duc_in_strobe,
    output duc_in_enable,


    input [31:0] bb_sample,
    output bb_strobe
);


    assign frontend_i = duc_out_i;
    assign frontend_q = duc_out_q;
    assign duc_in_sample = bb_sample;
    assign bb_strobe = duc_in_strobe;
    assign duc_in_enable = enable;

endmodule