data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module top #(
    parameter data_width = 32,
    parameter addr_width = 8,
    parameter instr_width = 32,
    parameter len = 4
)(input clk);


    wire [instr_width-1:0] out1;
    wire [instr_width-1:0] out2;
    wire PCsrc;
    wire [instr_width-1:0] potentialPC;
    wire [instr_width-1:0] nextPC;
    wire [instr_width-1:0] addr;
    wire [instr_width-1:0] instruction;
    

    wire [instr_width-1:0] ID_addr;
    wire [instr_width-1:0] ID_instruction;
    wire [instr_width-1:0] ID_out1;
    wire [addr_width-1:0] Raddr1;
    wire [addr_width-1:0] Raddr2;
    wire [addr_width-1:0] Waddr;
    wire [6:0] opcode;
    wire [3:0] ALUin;
    wire [2:0] funct3;
    wire Branch;
    wire [instr_width-1:0] imm;
    wire [addr_width-1:0] WB_Waddr;
    wire MemRead;
    wire MemtoReg;
    wire [1:0] ALUOp;
    wire MemWrite;
    wire ALUSrc;
    wire RegWrite;
    wire WB_RegWrite;
    wire WdataSrc;
    wire RdataSrc;
    wire storeType;
    wire [1:0] loadType;
    wire [data_width-1:0] WdataReg;
    wire [data_width-1:0] Rdata1;
    wire [data_width-1:0] Rdata2;
    wire [data_width-1:0] rs1_data;
    wire [data_width-1:0] rs2_data;
    wire PCWrite;
    wire IF_ID_Write;
    wire hazard;
    wire [11:0] control_signal;
    wire [11:0] ID_EX_control;
    wire en;
    wire IF_ID_en;
    wire IF_ID_clr;
    wire forward_1;
    wire forward_2;
    wire [instr_width-1:0] temp;
    wire branch_stall;


    wire [instr_width-1:0] EX_imm;
    wire [instr_width-1:0] EX_out1;
    wire zero;
    wire [instr_width-1:0] EX_addr;
    wire [3:0] EX_ALUin;
    wire [addr_width-1:0] EX_Waddr;
    wire EX_MemRead;
    wire EX_MemtoReg;
    wire [1:0] EX_ALUOp;
    wire EX_MemWrite;
    wire EX_ALUSrc;
    wire EX_RegWrite;
    wire EX_WdataSrc;
    wire EX_RdataSrc;
    wire EX_storeType;
    wire [1:0] EX_loadType;
    wire [data_width-1:0] EX_Rdata1;
    wire [data_width-1:0] EX_Rdata2;
    wire [data_width-1:0] in2;
    wire [len-1:0] ctrl;
    wire [data_width-1:0] ALUResult;
    wire [1:0] forward_A;
    wire [1:0] forward_B;
    wire [data_width-1:0] ALU_in1;
    wire [data_width-1:0] ALU_in2;
    wire [addr_width-1:0] EX_Raddr1;
    wire [addr_width-1:0] EX_Raddr2;


    wire [instr_width-1:0] MEM_out1;
    wire [addr_width-1:0] MEM_Waddr;
    wire MEM_MemRead;
    wire MEM_MemtoReg;
    wire MEM_MemWrite;
    wire MEM_RegWrite;
    wire MEM_WdataSrc;
    wire MEM_RdataSrc;
    wire MEM_storeType;
    wire [1:0] MEM_loadType;
    wire [data_width-1:0] MEM_Rdata1;
    wire [data_width-1:0] MEM_Rdata2;
    wire [data_width-1:0] MEM_ALUResult;
    wire [data_width-1:0] Rdata;
    wire [addr_width-1:0] MEM_Raddr2;
    wire MEMsrc;
    wire [data_width-1:0] MEM_in;


    wire [instr_width-1:0] WB_out1;
    wire WB_MemtoReg;
    wire WB_MemRead;
    wire WB_WdataSrc;
    wire WB_RdataSrc;
    wire [data_width-1:0] Wdata;
    wire [data_width-1:0] WB_ALUResult;
    wire [data_width-1:0] WB_Rdata;
    wire SelSrc;



    PC uut0(nextPC, clk, PCWrite, addr);
    InstrMem uut1(addr, instruction);
    adder uut2(addr, 4, out1);
    mux_2_to_1 uut3(out1, out2, PCsrc, potentialPC);
    mux_2_to_1 uut4(potentialPC, ALUResult, EX_RdataSrc, nextPC);


    assign IF_ID_en = (~PCsrc) & IF_ID_Write & (~branch_stall);
    assign IF_ID_clr = PCsrc & (~branch_stall);
    hazard_unit uut28(clk, Raddr1, Raddr2, EX_Waddr, EX_MemRead, PCWrite, IF_ID_Write, hazard);
    SubInstr uut5(ID_instruction, Raddr1, Raddr2, Waddr, opcode, ALUin, funct3);
    Control uut6(opcode, funct3, ALUSrc, ALUOp, MemWrite, MemRead, RegWrite, Branch, MemtoReg, WdataSrc, RdataSrc, storeType, loadType);
    ImmGen uut7(ID_instruction, imm);
    Register register_file(Raddr1, Raddr2, WB_Waddr, WdataReg, clk, WB_RegWrite, rs1_data, rs2_data);
    assign control_signal = {ALUOp, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, WdataSrc, RdataSrc, storeType, loadType};
    mux_2_to_1 #(12) uut29(control_signal, 12'b0, hazard, ID_EX_control);
    branch_compare uut31(Rdata1, Rdata2, Branch, funct3, en);
    assign PCsrc = en | WdataSrc;
    branch_forward uut32(Branch, Raddr1, Raddr2, MEM_Waddr, MEM_RegWrite, MEM_MemRead, EX_Waddr, EX_RegWrite, forward_1, forward_2, branch_stall);
    mux_2_to_1 #(32) uut33(rs1_data, MEM_ALUResult, forward_1, Rdata1);
    mux_2_to_1 #(32) uut34(rs2_data, MEM_ALUResult, forward_2, Rdata2);
    shifter uut12(imm, temp);
    adder uut13(ID_addr, temp, out2);
    

    forward_unit uut25(EX_Raddr1, EX_Raddr2, MEM_Waddr, WB_Waddr, MEM_RegWrite, WB_RegWrite, forward_A, forward_B);
    forward_mux uut26(EX_Rdata1, MEM_ALUResult, Wdata, forward_A, ALU_in1);
    forward_mux uut27(EX_Rdata2, MEM_ALUResult, Wdata, forward_B, in2);
    mux_2_to_1 uut8(in2, EX_imm, EX_ALUSrc, ALU_in2);
    ALUcontrol uut9(EX_ALUOp, EX_ALUin, ctrl);
    ALU uut11(ALU_in1, ALU_in2, ctrl, ALUResult, zero);



    DataMem uut14(MEM_MemWrite, MEM_MemRead, MEM_ALUResult, MEM_in, clk, MEM_storeType, MEM_loadType, Rdata);
    assign MEMsrc = (WB_Waddr != 0) & (WB_Waddr == MEM_Raddr2) & WB_MemRead & MEM_MemWrite;
    mux_2_to_1 uut30(MEM_Rdata2, Wdata, MEMsrc, MEM_in);


    mux_2_to_1 uut15(WB_ALUResult, WB_Rdata, WB_MemtoReg, Wdata);
    mux_2_to_1 uut16(Wdata, WB_out1, SelSrc, WdataReg);
    assign SelSrc = WB_WdataSrc | WB_RdataSrc;



    state_register #(96) uut17({addr, instruction, out1}, clk, IF_ID_en, IF_ID_clr, {ID_addr, ID_instruction, ID_out1});

    state_register #(96) uut18({imm, ID_addr, ID_out1}, clk, 1'b1, 1'b0, {EX_imm, EX_addr, EX_out1});
    state_register #(92) uut19({Waddr, ALUin, Rdata1, Rdata2, Raddr1, Raddr2}, clk, 1'b1, 1'b0, {EX_Waddr, EX_ALUin, EX_Rdata1, EX_Rdata2, EX_Raddr1, EX_Raddr2});
    state_register #(12) uut20(ID_EX_control, clk, 1'b1, 1'b0, {EX_ALUOp, EX_MemRead, EX_MemtoReg, EX_MemWrite, EX_ALUSrc, EX_RegWrite, EX_WdataSrc, EX_RdataSrc, EX_storeType, EX_loadType});

    state_register #(144) uut21({EX_out1, EX_Waddr, EX_Rdata1, in2, ALUResult, EX_Raddr2}, clk, 1'b1, 1'b0, {MEM_out1, MEM_Waddr, MEM_Rdata1, MEM_Rdata2, MEM_ALUResult, MEM_Raddr2});
    state_register #(4) uut22({EX_MemRead, EX_MemtoReg, EX_MemWrite, EX_RegWrite}, clk, 1'b1, 1'b0, {MEM_MemRead, MEM_MemtoReg, MEM_MemWrite, MEM_RegWrite});
    state_register #(5) uut23({EX_loadType, EX_storeType, EX_WdataSrc, EX_RdataSrc}, clk, 1'b1, 1'b0, {MEM_loadType, MEM_storeType,MEM_WdataSrc, MEM_RdataSrc});

    state_register #(109) uut24({MEM_out1, MEM_MemtoReg, MEM_WdataSrc, MEM_ALUResult, Rdata, MEM_RegWrite, MEM_Waddr, MEM_RdataSrc, MEM_MemRead}, clk, 1'b1, 1'b0, {WB_out1, WB_MemtoReg, WB_WdataSrc, WB_ALUResult, WB_Rdata, WB_RegWrite, WB_Waddr, WB_RdataSrc, WB_MemRead});
endmodule
module top #(
    parameter data_width = 32,
    parameter addr_width = 8,
    parameter instr_width = 32,
    parameter len = 4
)(input clk);



    wire [instr_width-1:0] out1;
    wire [instr_width-1:0] out2;
    wire PCsrc;
    wire [instr_width-1:0] potentialPC;
    wire [instr_width-1:0] nextPC;
    wire [instr_width-1:0] addr;
    wire [instr_width-1:0] instruction;
    

    wire [instr_width-1:0] ID_addr;
    wire [instr_width-1:0] ID_instruction;
    wire [instr_width-1:0] ID_out1;
    wire [addr_width-1:0] Raddr1;
    wire [addr_width-1:0] Raddr2;
    wire [addr_width-1:0] Waddr;
    wire [6:0] opcode;
    wire [3:0] ALUin;
    wire [2:0] funct3;
    wire Branch;
    wire [instr_width-1:0] imm;
    wire [addr_width-1:0] WB_Waddr;
    wire MemRead;
    wire MemtoReg;
    wire [1:0] ALUOp;
    wire MemWrite;
    wire ALUSrc;
    wire RegWrite;
    wire WB_RegWrite;
    wire WdataSrc;
    wire RdataSrc;
    wire storeType;
    wire [1:0] loadType;
    wire [data_width-1:0] WdataReg;
    wire [data_width-1:0] Rdata1;
    wire [data_width-1:0] Rdata2;
    wire [data_width-1:0] rs1_data;
    wire [data_width-1:0] rs2_data;
    wire PCWrite;
    wire IF_ID_Write;
    wire hazard;
    wire [11:0] control_signal;
    wire [11:0] ID_EX_control;
    wire en;
    wire IF_ID_en;
    wire IF_ID_clr;
    wire forward_1;
    wire forward_2;
    wire [instr_width-1:0] temp;
    wire branch_stall;


    wire [instr_width-1:0] EX_imm;
    wire [instr_width-1:0] EX_out1;
    wire zero;
    wire [instr_width-1:0] EX_addr;
    wire [3:0] EX_ALUin;
    wire [addr_width-1:0] EX_Waddr;
    wire EX_MemRead;
    wire EX_MemtoReg;
    wire [1:0] EX_ALUOp;
    wire EX_MemWrite;
    wire EX_ALUSrc;
    wire EX_RegWrite;
    wire EX_WdataSrc;
    wire EX_RdataSrc;
    wire EX_storeType;
    wire [1:0] EX_loadType;
    wire [data_width-1:0] EX_Rdata1;
    wire [data_width-1:0] EX_Rdata2;
    wire [data_width-1:0] in2;
    wire [len-1:0] ctrl;
    wire [data_width-1:0] ALUResult;
    wire [1:0] forward_A;
    wire [1:0] forward_B;
    wire [data_width-1:0] ALU_in1;
    wire [data_width-1:0] ALU_in2;
    wire [addr_width-1:0] EX_Raddr1;
    wire [addr_width-1:0] EX_Raddr2;


    wire [instr_width-1:0] MEM_out1;
    wire [addr_width-1:0] MEM_Waddr;
    wire MEM_MemRead;
    wire MEM_MemtoReg;
    wire MEM_MemWrite;
    wire MEM_RegWrite;
    wire MEM_WdataSrc;
    wire MEM_RdataSrc;
    wire MEM_storeType;
    wire [1:0] MEM_loadType;
    wire [data_width-1:0] MEM_Rdata1;
    wire [data_width-1:0] MEM_Rdata2;
    wire [data_width-1:0] MEM_ALUResult;
    wire [data_width-1:0] Rdata;
    wire [addr_width-1:0] MEM_Raddr2;
    wire MEMsrc;
    wire [data_width-1:0] MEM_in;


    wire [instr_width-1:0] WB_out1;
    wire WB_MemtoReg;
    wire WB_MemRead;
    wire WB_WdataSrc;
    wire WB_RdataSrc;
    wire [data_width-1:0] Wdata;
    wire [data_width-1:0] WB_ALUResult;
    wire [data_width-1:0] WB_Rdata;
    wire SelSrc;



    PC uut0(nextPC, clk, PCWrite, addr);
    InstrMem uut1(addr, instruction);
    adder uut2(addr, 4, out1);
    mux_2_to_1 uut3(out1, out2, PCsrc, potentialPC);
    mux_2_to_1 uut4(potentialPC, ALUResult, EX_RdataSrc, nextPC);


    assign IF_ID_en = (~PCsrc) & IF_ID_Write & (~branch_stall);
    assign IF_ID_clr = PCsrc & (~branch_stall);
    hazard_unit uut28(clk, Raddr1, Raddr2, EX_Waddr, EX_MemRead, PCWrite, IF_ID_Write, hazard);
    SubInstr uut5(ID_instruction, Raddr1, Raddr2, Waddr, opcode, ALUin, funct3);
    Control uut6(opcode, funct3, ALUSrc, ALUOp, MemWrite, MemRead, RegWrite, Branch, MemtoReg, WdataSrc, RdataSrc, storeType, loadType);
    ImmGen uut7(ID_instruction, imm);
    Register register_file(Raddr1, Raddr2, WB_Waddr, WdataReg, clk, WB_RegWrite, rs1_data, rs2_data);
    assign control_signal = {ALUOp, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, WdataSrc, RdataSrc, storeType, loadType};
    mux_2_to_1 #(12) uut29(control_signal, 12'b0, hazard, ID_EX_control);
    branch_compare uut31(Rdata1, Rdata2, Branch, funct3, en);
    assign PCsrc = en | WdataSrc;
    branch_forward uut32(Branch, Raddr1, Raddr2, MEM_Waddr, MEM_RegWrite, MEM_MemRead, EX_Waddr, EX_RegWrite, forward_1, forward_2, branch_stall);
    mux_2_to_1 #(32) uut33(rs1_data, MEM_ALUResult, forward_1, Rdata1);
    mux_2_to_1 #(32) uut34(rs2_data, MEM_ALUResult, forward_2, Rdata2);
    shifter uut12(imm, temp);
    adder uut13(ID_addr, temp, out2);
    

    forward_unit uut25(EX_Raddr1, EX_Raddr2, MEM_Waddr, WB_Waddr, MEM_RegWrite, WB_RegWrite, forward_A, forward_B);
    forward_mux uut26(EX_Rdata1, MEM_ALUResult, Wdata, forward_A, ALU_in1);
    forward_mux uut27(EX_Rdata2, MEM_ALUResult, Wdata, forward_B, in2);
    mux_2_to_1 uut8(in2, EX_imm, EX_ALUSrc, ALU_in2);
    ALUcontrol uut9(EX_ALUOp, EX_ALUin, ctrl);
    ALU uut11(ALU_in1, ALU_in2, ctrl, ALUResult, zero);



    DataMem uut14(MEM_MemWrite, MEM_MemRead, MEM_ALUResult, MEM_in, clk, MEM_storeType, MEM_loadType, Rdata);
    assign MEMsrc = (WB_Waddr != 0) & (WB_Waddr == MEM_Raddr2) & WB_MemRead & MEM_MemWrite;
    mux_2_to_1 uut30(MEM_Rdata2, Wdata, MEMsrc, MEM_in);


    mux_2_to_1 uut15(WB_ALUResult, WB_Rdata, WB_MemtoReg, Wdata);
    mux_2_to_1 uut16(Wdata, WB_out1, SelSrc, WdataReg);
    assign SelSrc = WB_WdataSrc | WB_RdataSrc;



    state_register #(96) uut17({addr, instruction, out1}, clk, IF_ID_en, IF_ID_clr, {ID_addr, ID_instruction, ID_out1});

    state_register #(96) uut18({imm, ID_addr, ID_out1}, clk, 1'b1, 1'b0, {EX_imm, EX_addr, EX_out1});
    state_register #(92) uut19({Waddr, ALUin, Rdata1, Rdata2, Raddr1, Raddr2}, clk, 1'b1, 1'b0, {EX_Waddr, EX_ALUin, EX_Rdata1, EX_Rdata2, EX_Raddr1, EX_Raddr2});
    state_register #(12) uut20(ID_EX_control, clk, 1'b1, 1'b0, {EX_ALUOp, EX_MemRead, EX_MemtoReg, EX_MemWrite, EX_ALUSrc, EX_RegWrite, EX_WdataSrc, EX_RdataSrc, EX_storeType, EX_loadType});

    state_register #(144) uut21({EX_out1, EX_Waddr, EX_Rdata1, in2, ALUResult, EX_Raddr2}, clk, 1'b1, 1'b0, {MEM_out1, MEM_Waddr, MEM_Rdata1, MEM_Rdata2, MEM_ALUResult, MEM_Raddr2});
    state_register #(4) uut22({EX_MemRead, EX_MemtoReg, EX_MemWrite, EX_RegWrite}, clk, 1'b1, 1'b0, {MEM_MemRead, MEM_MemtoReg, MEM_MemWrite, MEM_RegWrite});
    state_register #(5) uut23({EX_loadType, EX_storeType, EX_WdataSrc, EX_RdataSrc}, clk, 1'b1, 1'b0, {MEM_loadType, MEM_storeType,MEM_WdataSrc, MEM_RdataSrc});

    state_register #(109) uut24({MEM_out1, MEM_MemtoReg, MEM_WdataSrc, MEM_ALUResult, Rdata, MEM_RegWrite, MEM_Waddr, MEM_RdataSrc, MEM_MemRead}, clk, 1'b1, 1'b0, {WB_out1, WB_MemtoReg, WB_WdataSrc, WB_ALUResult, WB_Rdata, WB_RegWrite, WB_Waddr, WB_RdataSrc, WB_MemRead});
endmodule