data/full_repos/permissive/445929378/main_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/main_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/main_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/445929378/main_tb.v:35: Cannot find file containing module: \'main\'\n   main uut(\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/main\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/main.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_tb;


   reg clk;
   reg rst;
   

   reg start, finish;


   main uut(
	    .clk(clk), 
	    .rst(rst), 
	    .start(start),
	    .finish(finish)
	    );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;
      start = 1;

      #100;
      


   end
   
endmodule
module main_tb;



   reg clk;
   reg rst;
   

   reg start, finish;


   main uut(
	    .clk(clk), 
	    .rst(rst), 
	    .start(start),
	    .finish(finish)
	    );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;
      start = 1;

      #100;
      


   end
   
endmodule