data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_sim.v:16: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'EFX_LUT4\'\nmodule EFX_LUT4(\n       ^~~~~~~~\n                                                                                                : ... Top module \'EFX_ADD\'\nmodule EFX_ADD(\n       ^~~~~~~\n                                                                                                : ... Top module \'EFX_FF\'\nmodule EFX_FF(\n       ^~~~~~\n                                                                                                : ... Top module \'EFX_GBUFCE\'\nmodule EFX_GBUFCE(\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'EFX_RAM_5K\'\nmodule EFX_RAM_5K(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module EFX_LUT4(
   output O, 
   input I0,
   input I1,
   input I2,
   input I3
);
	parameter LUTMASK = 16'h0000;

	wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
	wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
	wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
	assign O = I0 ? s1[1] : s1[0];	   
endmodule
module EFX_LUT4(
   output O, 
   input I0,
   input I1,
   input I2,
   input I3
);

	parameter LUTMASK = 16'h0000;

	wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
	wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
	wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
	assign O = I0 ? s1[1] : s1[0];	   
endmodule