data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v
1: b'%Error: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:33: Cannot find file containing module: \'freq_divider\'\n  freq_divider #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/freq_divider\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/freq_divider.v\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/freq_divider.sv\n             freq_divider\n             freq_divider.v\n             freq_divider.sv\n             obj_dir/freq_divider\n             obj_dir/freq_divider.v\n             obj_dir/freq_divider.sv\n%Error: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:42: Cannot find file containing module: \'kb\'\n  kb keyboard(\n  ^~\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:53: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance kb2game\n    dataprev2<=1\'b0; \n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:54: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance kb2game\n    dataprev <=1\'b0;  \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance kb2game\n    p2 <= 4\'h0; \n       ^~\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:56: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance kb2game\n    p1 <= 4\'h0; \n       ^~\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:63: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance kb2game\n        dataprev2<=1\'b0; \n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb2game.v:64: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance kb2game\n        dataprev <=1\'b0;       \n                 ^~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module kb2game(
  input            board_clk,
  input            reset,
  input            ps2_clk,
  input            ps2_data,
  output reg [4:0] p1,
  output reg [4:0] p2
);

  wire clk50;
  reg [7:0]dataprev;
  reg [7:0]dataprev2;
  wire [7:0] data;
  wire valid ; 


  localparam P1_u = 8'h1D;
  localparam P1_d = 8'h1B;
  localparam P1_l = 8'h1C;
  localparam P1_r = 8'h23;
  localparam P1_s = 8'h3B;

  localparam P2_u = 8'h75;
  localparam P2_d = 8'h72;
  localparam P2_l = 8'h6B;
  localparam P2_r = 8'h74;
  localparam P2_s = 8'h4C;

  freq_divider #(
    .nbits(1)
  ) divider(
    .in_clk  (board_clk),
    .reset   (reset),
    .out_clk (clk50)
  );


  kb keyboard(
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .clk(clk50),
    .rx_data(data),
    .valid(valid)
  );


always @(posedge valid or posedge reset)begin
  if (reset) begin
    dataprev2<=1'b0; 
    dataprev <=1'b0;  
    p2 <= 4'h0; 
    p1 <= 4'h0; 
  end else begin
    if (dataprev  == 8'hF0 || dataprev2== 8'hF0 )  begin
      if (data == 8'hE0) begin
        dataprev2<=dataprev; 
        dataprev <=data;         
      end else begin
        dataprev2<=1'b0; 
        dataprev <=1'b0;       
      end
      case(data)
        P2_u: p2[0] <= 1'b0;
        P2_d: p2[1] <= 1'b0;
        P2_l: p2[2] <= 1'b0;
        P2_r: p2[3] <= 1'b0;
        P2_s: p2[4] <= 1'b0;
        P1_u: p1[0] <= 1'b0;
        P1_d: p1[1] <= 1'b0;
        P1_l: p1[2] <= 1'b0;
        P1_r: p1[3] <= 1'b0;
        P1_s: p1[4] <= 1'b0;      
      endcase           
    end else begin
      dataprev2<=dataprev; 
      dataprev <=data;   
      case(data)
        P2_u: p2[0] <=  1'b1;
        P2_d: p2[1] <=  1'b1;
        P2_l: p2[2] <=  1'b1;
        P2_r: p2[3] <=  1'b1;
        P2_s: p2[4] <=  1'b1;
        P1_u: p1[0] <=  1'b1;
        P1_d: p1[1] <=  1'b1;
        P1_l: p1[2] <=  1'b1;
        P1_r: p1[3] <=  1'b1;
        P1_s: p1[4] <=  1'b1;      
      endcase           
    end
  end    
end


endmodule
module kb2game(
  input            board_clk,
  input            reset,
  input            ps2_clk,
  input            ps2_data,
  output reg [4:0] p1,
  output reg [4:0] p2
);


  wire clk50;
  reg [7:0]dataprev;
  reg [7:0]dataprev2;
  wire [7:0] data;
  wire valid ; 


  localparam P1_u = 8'h1D;
  localparam P1_d = 8'h1B;
  localparam P1_l = 8'h1C;
  localparam P1_r = 8'h23;
  localparam P1_s = 8'h3B;

  localparam P2_u = 8'h75;
  localparam P2_d = 8'h72;
  localparam P2_l = 8'h6B;
  localparam P2_r = 8'h74;
  localparam P2_s = 8'h4C;

  freq_divider #(
    .nbits(1)
  ) divider(
    .in_clk  (board_clk),
    .reset   (reset),
    .out_clk (clk50)
  );


  kb keyboard(
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .clk(clk50),
    .rx_data(data),
    .valid(valid)
  );


always @(posedge valid or posedge reset)begin
  if (reset) begin
    dataprev2<=1'b0; 
    dataprev <=1'b0;  
    p2 <= 4'h0; 
    p1 <= 4'h0; 
  end else begin
    if (dataprev  == 8'hF0 || dataprev2== 8'hF0 )  begin
      if (data == 8'hE0) begin
        dataprev2<=dataprev; 
        dataprev <=data;         
      end else begin
        dataprev2<=1'b0; 
        dataprev <=1'b0;       
      end
      case(data)
        P2_u: p2[0] <= 1'b0;
        P2_d: p2[1] <= 1'b0;
        P2_l: p2[2] <= 1'b0;
        P2_r: p2[3] <= 1'b0;
        P2_s: p2[4] <= 1'b0;
        P1_u: p1[0] <= 1'b0;
        P1_d: p1[1] <= 1'b0;
        P1_l: p1[2] <= 1'b0;
        P1_r: p1[3] <= 1'b0;
        P1_s: p1[4] <= 1'b0;      
      endcase           
    end else begin
      dataprev2<=dataprev; 
      dataprev <=data;   
      case(data)
        P2_u: p2[0] <=  1'b1;
        P2_d: p2[1] <=  1'b1;
        P2_l: p2[2] <=  1'b1;
        P2_r: p2[3] <=  1'b1;
        P2_s: p2[4] <=  1'b1;
        P1_u: p1[0] <=  1'b1;
        P1_d: p1[1] <=  1'b1;
        P1_l: p1[2] <=  1'b1;
        P1_r: p1[3] <=  1'b1;
        P1_s: p1[4] <=  1'b1;      
      endcase           
    end
  end    
end


endmodule