data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test.v:17: Operator LT expects 2 bits on the RHS, but RHS\'s REPLICATE generates 1 bits.\n                                                                                                                : ... In instance reset_test\n         for (i = 0; i < {SELW{1\'b1}}; i=i+1) begin\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test.v:18: Bit extraction of var[31:0] requires 5 bit index, not 2 bits.\n                                                                                                                : ... In instance reset_test\n            dout[i*rval+:SLICE] <= 32\'hDEAD;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test.v:21: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                : ... In instance reset_test\n      dout[ctrl*sel+:SLICE] <= din;\n                            ^~\n%Error: Exiting due to 3 warning(s)\n'
module reset_test  #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire             reset,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);
   
   reg [SELW:0] 		   i;
   wire [SELW-1:0] 	   rval = {reset, {SELW-1{1'b0}}};
   localparam SLICE = WIDTH/(SELW**2);


   always @(posedge clk) begin
      if (reset) begin: reset_mask
         for (i = 0; i < {SELW{1'b1}}; i=i+1) begin
            dout[i*rval+:SLICE] <= 32'hDEAD;
         end
      end
      dout[ctrl*sel+:SLICE] <= din;
   end
endmodule
module reset_test  #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire             reset,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);

   
   reg [SELW:0] 		   i;
   wire [SELW-1:0] 	   rval = {reset, {SELW-1{1'b0}}};
   localparam SLICE = WIDTH/(SELW**2);


   always @(posedge clk) begin
      if (reset) begin: reset_mask
         for (i = 0; i < {SELW{1'b1}}; i=i+1) begin
            dout[i*rval+:SLICE] <= 32'hDEAD;
         end
      end
      dout[ctrl*sel+:SLICE] <= din;
   end
endmodule