data/full_repos/permissive/48007633/rhd2000_dm_tb.v
1: b'%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:14: Cannot find include file: llLib.v\n`include "llLib.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v.v\n             data/full_repos/permissive/48007633,data/full_repos/permissive/48007633/llLib.v.sv\n             llLib.v\n             llLib.v.v\n             llLib.v.sv\n             obj_dir/llLib.v\n             obj_dir/llLib.v.v\n             obj_dir/llLib.v.sv\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:48: syntax error, unexpected return, expecting IDENTIFIER\n  output [15:0] return;\n                ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:50: syntax error, unexpected bit, expecting "\'{"\n  reg [3:0] bit;\n            ^~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:51: syntax error, unexpected IDENTIFIER, expecting "\'{"\n  reg [15:0] temp;\n             ^~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:54: syntax error, unexpected \'=\', expecting "\'{"\n   bit = 4\'d15;\n       ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:58: syntax error, unexpected \']\', expecting "\'{"\n     mosi = command[bit];\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #20.8\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10.4;\n    ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:62: syntax error, unexpected \']\', expecting "\'{"\n     temp[bit] = miso;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #20.8\n    ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:67: syntax error, unexpected \'=\', expecting "\'{"\n    bit = bit - 4\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #41.6;\n   ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:73: syntax error, unexpected \'=\', expecting TYPE-IDENTIFIER\n   return = temp;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n   #154.0;\n   ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:86: syntax error, unexpected return, expecting IDENTIFIER or \'=\' or do or final\n   reg [15:0] return;\n              ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:87: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [15:0] dummy;\n              ^~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:92: syntax error, unexpected return, expecting \')\'\n   SPI_TRANSACTION ( channel << 8, return);  \n                                   ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:96: syntax error, unexpected return, expecting \')\'\n   SPI_TRANSACTION ( channel << 8, return);  \n                                   ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:101: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION (channel << 8, return);  \n                                   ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:104: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n    if (return != channel - 1) begin\n        ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:109: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:114: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [15:0] calibrate;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:115: syntax error, unexpected return, expecting "\'{"\n   reg [15:0] return;\n              ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:116: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [15:0] dummy;\n              ^~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:124: syntax error, unexpected return, expecting \')\'\n   SPI_TRANSACTION (calibrate, return);  \n                               ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:129: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION (dummy, return);  \n                            ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:132: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n    if (return != {1\'b1, 15\'b0}) begin\n        ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:137: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:142: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [5:0] address;\n             ^~~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:143: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [7:0] data;\n             ^~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:145: syntax error, unexpected return, expecting "\'{"\n   reg [15:0] return;\n              ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:146: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [15:0] dummy;\n              ^~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:154: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION ({ 2\'b10, address, data }, return);  \n                                               ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:156: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION ({ 2\'b11, address, 8\'b0 }, return);  \n                                               ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:158: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION (dummy, return);  \n                            ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:161: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n    if (return != { {8{1\'b1}}, data }) begin\n        ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:166: syntax error, unexpected return, expecting \')\'\n    SPI_TRANSACTION (dummy, return);  \n                            ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:170: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n     if (return != { 8\'b0, data }) begin\n         ^~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:180: syntax error, unexpected else\n    else if (address >= 40 && address <= 44) begin\n    ^~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:235: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:236: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, rhd2000_dm_tb);  \n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:252: syntax error, unexpected end\n end\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:259: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/48007633/rhd2000_dm_tb.v:269: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n'
module rhd2000_dm_tb #(
		parameter CHANNELS = 32,
		parameter REVISION = 1,
		parameter UNIPOLAR = 1,
		parameter ID = 1
	)();


	reg [511:0]	analog;
	reg 		nCs = 1;
	reg			sclk;
	wire		miso;
	reg 		mosi = 0;
	wire 		aux;
	rhd2000_dm #(
		.CHANNELS	(CHANNELS ),
		.REVISION	(REVISION ),
		.UNIPOLAR	(UNIPOLAR ),
		.ID 		(ID       )
	)
	uut	(
		.analogIn	(analog   ),
		.nCs		(nCs      ),
		.sClk 		(sclk     ),
		.mosi		(mosi     ),
		.miso		(miso     ),
		.aux		(aux      ) 	
	);


	task SPI_TRANSACTION;
		input [15:0] command;
		output [15:0] return;

		reg [3:0] bit;
		reg [15:0] temp;
		begin
			nCs = 0;
			bit = 4'd15;

			repeat (16) begin
				#20.8
					mosi = command[bit];

				#10.4;
					sclk = 1;
					temp[bit] = miso;

				#20.8
					sclk = 0;

				bit = bit - 4'd1;
			end

			#41.6;
				nCs = 1;

			return = temp;


			#154.0;
		end
	endtask



	

	task testConvert;
			reg [15:0] channel;
			reg [15:0] return;
			reg [15:0] dummy;
		begin
			channel = 0;
			dummy = { 2'b01, 6'b101010, 8'd0 };

			SPI_TRANSACTION ( channel << 8, return);

			channel = channel + 1;

			SPI_TRANSACTION ( channel << 8, return);

			repeat (32) begin
				channel = channel + 1;

				SPI_TRANSACTION (channel << 8, return);


				if (return != channel - 1) begin
					
					$display("!TEST FAILED!  Capture channel %d returned %b.", channel - 1, return);
				end				
			end
		end
	endtask


	task testCalibration;
			reg [15:0] calibrate;
			reg [15:0] return;
			reg [15:0] dummy;
			
			integer itteration;
		begin
			calibrate = { 2'b01, 6'b010101, 8'b0 };
			dummy = { 2'b01, 6'b101010, 8'b0 };
			itteration = 0;

			SPI_TRANSACTION (calibrate, return);
			
			repeat (10) begin
				itteration = itteration + 1;

				SPI_TRANSACTION (dummy, return);


				if (return != {1'b1, 15'b0}) begin
					
					$display("!TEST FAILED!  Calibration itteration %d returned %b", itteration, return);
				end
			end
		end
	endtask


	task testReadWrite;
			reg [5:0] address;
			reg [7:0] data;

			reg [15:0] return;
			reg [15:0] dummy;
		begin
			dummy = { 2'b01, 6'b101010, 8'b0 };
			address = 0;

			repeat (28) begin
				data = llLib.RANDRANGE (255, 0);
				
				SPI_TRANSACTION ({ 2'b10, address, data }, return);

				SPI_TRANSACTION ({ 2'b11, address, 8'b0 }, return);

				SPI_TRANSACTION (dummy, return);


				if (return != { {8{1'b1}}, data }) begin
					
					$display ("!TEST FAILED!  Address %d write returned incorrect value %b", address, return);
				end

				SPI_TRANSACTION (dummy, return);


				if (address >= 0 && address <= 17) begin
					if (return != { 8'b0, data }) begin
						
						$display("!TEST FAILED!  RAM %d read returned incorrect value %b", address, return);
					end

					if (address == 17) address = 40;
					else address = address + 1;
				end


				else if (address >= 40 && address <= 44) begin
					if (address == 40 && return != { 8'b0, "I" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 41 && return != { 8'b0, "N" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end
					
					else if (address == 42 && return != { 8'b0, "T" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 43 && return != { 8'b0, "A" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 44 && return != { 8'b0, "N" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					if (address == 44) address = 60;
					else address = address + 1;
				end


				else if (address >= 60 && address <= 63) begin
					if (address == 60 && return != { 8'b0, REVISION[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 61 && return != { 8'b0, UNIPOLAR[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end
					
					else if (address == 62 && return != { 8'b0, CHANNELS[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 63 && return != { 8'b0, ID[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					address = address + 1;
				end
			end
		end
	endtask
	
	

	reg [7:0] t = 16'd0;
	initial begin


		$dumpfile("test.vcd");
		$dumpvars(0, rhd2000_dm_tb);


		nCs <= 1;
		mosi <= 0;
		sclk <= 0;



		t = 16'd0;
		repeat (33) begin
			analog[(t - 1) * 16 +: 16] <= t;
			#1;
			t = t + 16'd1;
			#1;
		end
	end
	


	always begin
		$display("#--- STARTING ---# Testbench for Intan RHD2000 Data Model...");

		#`STARTDELAY;
		
		testConvert;

		testCalibration;

		testReadWrite;

		$display("#--- FINISHED ---# RHD2000 Data Model.");
		$finish;
	end

endmodule
module rhd2000_dm_tb #(
		parameter CHANNELS = 32,
		parameter REVISION = 1,
		parameter UNIPOLAR = 1,
		parameter ID = 1
	)();



	reg [511:0]	analog;
	reg 		nCs = 1;
	reg			sclk;
	wire		miso;
	reg 		mosi = 0;
	wire 		aux;
	rhd2000_dm #(
		.CHANNELS	(CHANNELS ),
		.REVISION	(REVISION ),
		.UNIPOLAR	(UNIPOLAR ),
		.ID 		(ID       )
	)
	uut	(
		.analogIn	(analog   ),
		.nCs		(nCs      ),
		.sClk 		(sclk     ),
		.mosi		(mosi     ),
		.miso		(miso     ),
		.aux		(aux      ) 	
	);


	task SPI_TRANSACTION;
		input [15:0] command;
		output [15:0] return;

		reg [3:0] bit;
		reg [15:0] temp;
		begin
			nCs = 0;
			bit = 4'd15;

			repeat (16) begin
				#20.8
					mosi = command[bit];

				#10.4;
					sclk = 1;
					temp[bit] = miso;

				#20.8
					sclk = 0;

				bit = bit - 4'd1;
			end

			#41.6;
				nCs = 1;

			return = temp;


			#154.0;
		end
	endtask



	

	task testConvert;
			reg [15:0] channel;
			reg [15:0] return;
			reg [15:0] dummy;
		begin
			channel = 0;
			dummy = { 2'b01, 6'b101010, 8'd0 };

			SPI_TRANSACTION ( channel << 8, return);

			channel = channel + 1;

			SPI_TRANSACTION ( channel << 8, return);

			repeat (32) begin
				channel = channel + 1;

				SPI_TRANSACTION (channel << 8, return);


				if (return != channel - 1) begin
					
					$display("!TEST FAILED!  Capture channel %d returned %b.", channel - 1, return);
				end				
			end
		end
	endtask


	task testCalibration;
			reg [15:0] calibrate;
			reg [15:0] return;
			reg [15:0] dummy;
			
			integer itteration;
		begin
			calibrate = { 2'b01, 6'b010101, 8'b0 };
			dummy = { 2'b01, 6'b101010, 8'b0 };
			itteration = 0;

			SPI_TRANSACTION (calibrate, return);
			
			repeat (10) begin
				itteration = itteration + 1;

				SPI_TRANSACTION (dummy, return);


				if (return != {1'b1, 15'b0}) begin
					
					$display("!TEST FAILED!  Calibration itteration %d returned %b", itteration, return);
				end
			end
		end
	endtask


	task testReadWrite;
			reg [5:0] address;
			reg [7:0] data;

			reg [15:0] return;
			reg [15:0] dummy;
		begin
			dummy = { 2'b01, 6'b101010, 8'b0 };
			address = 0;

			repeat (28) begin
				data = llLib.RANDRANGE (255, 0);
				
				SPI_TRANSACTION ({ 2'b10, address, data }, return);

				SPI_TRANSACTION ({ 2'b11, address, 8'b0 }, return);

				SPI_TRANSACTION (dummy, return);


				if (return != { {8{1'b1}}, data }) begin
					
					$display ("!TEST FAILED!  Address %d write returned incorrect value %b", address, return);
				end

				SPI_TRANSACTION (dummy, return);


				if (address >= 0 && address <= 17) begin
					if (return != { 8'b0, data }) begin
						
						$display("!TEST FAILED!  RAM %d read returned incorrect value %b", address, return);
					end

					if (address == 17) address = 40;
					else address = address + 1;
				end


				else if (address >= 40 && address <= 44) begin
					if (address == 40 && return != { 8'b0, "I" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 41 && return != { 8'b0, "N" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end
					
					else if (address == 42 && return != { 8'b0, "T" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 43 && return != { 8'b0, "A" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 44 && return != { 8'b0, "N" }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					if (address == 44) address = 60;
					else address = address + 1;
				end


				else if (address >= 60 && address <= 63) begin
					if (address == 60 && return != { 8'b0, REVISION[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 61 && return != { 8'b0, UNIPOLAR[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end
					
					else if (address == 62 && return != { 8'b0, CHANNELS[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					else if (address == 63 && return != { 8'b0, ID[7:0] }) begin
						$display("!TEST FAILED!  ROM %d read returned incorrect value %b", address, return);
					end

					address = address + 1;
				end
			end
		end
	endtask
	
	

	reg [7:0] t = 16'd0;
	initial begin


		$dumpfile("test.vcd");
		$dumpvars(0, rhd2000_dm_tb);


		nCs <= 1;
		mosi <= 0;
		sclk <= 0;



		t = 16'd0;
		repeat (33) begin
			analog[(t - 1) * 16 +: 16] <= t;
			#1;
			t = t + 16'd1;
			#1;
		end
	end
	


	always begin
		$display("#--- STARTING ---# Testbench for Intan RHD2000 Data Model...");

		#`STARTDELAY;
		
		testConvert;

		testCalibration;

		testReadWrite;

		$display("#--- FINISHED ---# RHD2000 Data Model.");
		$finish;
	end

endmodule