data/full_repos/permissive/464638001/generated/UartSpeed.v
data/verilator_xmls/0c81306e-c625-47f4-80d5-8a6bad1a5476.xml
module UartSpeed(
  input   clock,
  input   reset,
  output  io_txd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_ready;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  reg [7:0] cntReg;
  wire [5:0] _GEN_1 = 4'h1 == cntReg[3:0] ? 6'h31 : 6'h30;
  wire [5:0] _GEN_2 = 4'h2 == cntReg[3:0] ? 6'h32 : _GEN_1;
  wire [5:0] _GEN_3 = 4'h3 == cntReg[3:0] ? 6'h33 : _GEN_2;
  wire [5:0] _GEN_4 = 4'h4 == cntReg[3:0] ? 6'h34 : _GEN_3;
  wire [5:0] _GEN_5 = 4'h5 == cntReg[3:0] ? 6'h35 : _GEN_4;
  wire [5:0] _GEN_6 = 4'h6 == cntReg[3:0] ? 6'h36 : _GEN_5;
  wire [5:0] _GEN_7 = 4'h7 == cntReg[3:0] ? 6'h37 : _GEN_6;
  wire [5:0] _GEN_8 = 4'h8 == cntReg[3:0] ? 6'h38 : _GEN_7;
  wire [5:0] _GEN_9 = 4'h9 == cntReg[3:0] ? 6'h39 : _GEN_8;
  wire  _T_1 = cntReg != 8'ha;
  wire [7:0] _T_5 = cntReg + 8'h1;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_ready(tx_io_channel_ready),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = cntReg != 8'ha;
  assign tx_io_channel_bits = {{2'd0}, _GEN_9};
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 8'h0;
    end else if (tx_io_channel_ready & _T_1) begin
      cntReg <= _T_5;
    end else if (cntReg == 8'ha) begin
      cntReg <= 8'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module UartSpeed(
  input   clock,
  input   reset,
  output  io_txd
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_ready;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  reg [7:0] cntReg;
  wire [5:0] _GEN_1 = 4'h1 == cntReg[3:0] ? 6'h31 : 6'h30;
  wire [5:0] _GEN_2 = 4'h2 == cntReg[3:0] ? 6'h32 : _GEN_1;
  wire [5:0] _GEN_3 = 4'h3 == cntReg[3:0] ? 6'h33 : _GEN_2;
  wire [5:0] _GEN_4 = 4'h4 == cntReg[3:0] ? 6'h34 : _GEN_3;
  wire [5:0] _GEN_5 = 4'h5 == cntReg[3:0] ? 6'h35 : _GEN_4;
  wire [5:0] _GEN_6 = 4'h6 == cntReg[3:0] ? 6'h36 : _GEN_5;
  wire [5:0] _GEN_7 = 4'h7 == cntReg[3:0] ? 6'h37 : _GEN_6;
  wire [5:0] _GEN_8 = 4'h8 == cntReg[3:0] ? 6'h38 : _GEN_7;
  wire [5:0] _GEN_9 = 4'h9 == cntReg[3:0] ? 6'h39 : _GEN_8;
  wire  _T_1 = cntReg != 8'ha;
  wire [7:0] _T_5 = cntReg + 8'h1;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_ready(tx_io_channel_ready),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = cntReg != 8'ha;
  assign tx_io_channel_bits = {{2'd0}, _GEN_9};
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 8'h0;
    end else if (tx_io_channel_ready & _T_1) begin
      cntReg <= _T_5;
    end else if (cntReg == 8'ha) begin
      cntReg <= 8'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule