data/full_repos/permissive/467292628/mem.v
1: b'%Error: data/full_repos/permissive/467292628/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v.v\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/467292628/mem.v:9: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:9: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:14: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:18: Define or directive not defined: \'`MEMORY_SIZE\'\n reg[7:0] data[`MEMORY_SIZE-1:0];  \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:22: syntax error, unexpected assign\n assign mask[0] = 1;\n ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:65: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:65: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:70: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:71: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:73: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg hlt,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:74: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg hlt_error\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:107: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:107: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:112: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:113: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:115: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [8:0] data_in,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:117: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/467292628/mem.v:162: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:162: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:167: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:168: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:170: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [63:0] mtime,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:171: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tip,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:178: syntax error, unexpected assign\n assign tip = (mtimecmp != 0) && (mtime >= mtimecmp);\n ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:243: Unsupported: SystemVerilog 2012 reserved word not implemented: \'interconnect\'\nmodule interconnect #(\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: Define or directive not defined: \'`MEMORY_SIZE\'\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n                                                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:247: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_2_END_ADDR   = 32\'h0201_03ff,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:248: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_3_START_ADDR = 32\'h1001_3000,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:249: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_3_END_ADDR   = 32\'h1001_3fff,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:250: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_4_START_ADDR = 32\'h0200_0000,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:251: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_4_END_ADDR   = 32\'h0200_ffff\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:252: syntax error, unexpected \')\', expecting \';\'\n )\n ^\n%Error: data/full_repos/permissive/467292628/mem.v:259: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] tx_mem_size,    \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:264: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tx_mem_ready,     \n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:268: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx1_mem_addr,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:269: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:269: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:271: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg rx1_mem_w_mode,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:272: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx1_mem_w_data,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:273: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [31:0] rx1_mem_r_data,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:279: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:279: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:281: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg rx2_mem_w_mode,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:282: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx2_mem_w_data,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:283: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [31:0] rx2_mem_r_data,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:289: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx3_mem_size,\n  ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module interconnect	#(
		parameter RX_1_START_ADDR = 32'h8000_0000,
		parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,
		parameter RX_2_START_ADDR = 32'h0201_0000,
		parameter RX_2_END_ADDR   = 32'h0201_03ff,
		parameter RX_3_START_ADDR = 32'h1001_3000,
		parameter RX_3_END_ADDR   = 32'h1001_3fff,
		parameter RX_4_START_ADDR = 32'h0200_0000,
		parameter RX_4_END_ADDR   = 32'h0200_ffff
	)
	(
		input reset,
		input clock,
		

		input [31:0] tx_mem_addr,
		input [`MEMORY_ACCESS_SIZE:0] tx_mem_size,
		input tx_mem_enable,
		input tx_mem_w_mode,
		input [31:0] tx_mem_w_data,
		output reg [31:0] tx_mem_r_data,
		output tx_mem_ready,
		output reg tx_mem_error,
		

		output reg [31:0] rx1_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,
		output reg rx1_mem_enable,
		output reg rx1_mem_w_mode,
		output reg [31:0] rx1_mem_w_data,
		input [31:0] rx1_mem_r_data,
		input rx1_mem_done,
		input rx1_mem_error,
		

		output reg [31:0] rx2_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,
		output reg rx2_mem_enable,
		output reg rx2_mem_w_mode,
		output reg [31:0] rx2_mem_w_data,
		input [31:0] rx2_mem_r_data,
		input rx2_mem_done,
		input rx2_mem_error,
		

		output reg [31:0] rx3_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx3_mem_size,
		output reg rx3_mem_enable,
		output reg rx3_mem_w_mode,
		output reg [31:0] rx3_mem_w_data,
		input [31:0] rx3_mem_r_data,
		input rx3_mem_done,
		input rx3_mem_error,
		

		output reg [31:0] rx4_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx4_mem_size,
		output reg rx4_mem_enable,
		output reg rx4_mem_w_mode,
		output reg [31:0] rx4_mem_w_data,
		input [31:0] rx4_mem_r_data,
		input rx4_mem_done,
		input rx4_mem_error
	);
	
	localparam READY = 0;
	localparam BUSY_1 = 1;
	localparam BUSY_2 = 2;
	localparam BUSY_3 = 3;
	localparam BUSY_4 = 4;
	
	reg [2:0] state;
	
	assign tx_mem_ready = state == READY && !tx_mem_enable;
	
	always @(posedge clock) begin
		if (reset) begin
			state <= READY;
			tx_mem_error <= 0;
			rx1_mem_enable <= 0;
			rx2_mem_enable <= 0;
			rx3_mem_enable <= 0;
			rx4_mem_enable <= 0;
		end else begin

			rx1_mem_enable <= 0;
			rx2_mem_enable <= 0;
			rx3_mem_enable <= 0;
			rx4_mem_enable <= 0;
					
			case (state)
				READY: begin
					if (tx_mem_enable) begin
						if (tx_mem_addr >= RX_1_START_ADDR && tx_mem_addr <= RX_1_END_ADDR) begin
							rx1_mem_addr <= tx_mem_addr - RX_1_START_ADDR;
							rx1_mem_size <= tx_mem_size;
							rx1_mem_enable <= 1;
							rx1_mem_w_mode <= tx_mem_w_mode;
							rx1_mem_w_data <= tx_mem_w_data;
							state <= BUSY_1;
						end else if (tx_mem_addr >= RX_2_START_ADDR && tx_mem_addr <= RX_2_END_ADDR) begin
							rx2_mem_addr <= tx_mem_addr - RX_2_START_ADDR;
							rx2_mem_size <= tx_mem_size;
							rx2_mem_enable <= 1;
							rx2_mem_w_mode <= tx_mem_w_mode;
							rx2_mem_w_data <= tx_mem_w_data;
							state <= BUSY_2;
						end else if (tx_mem_addr >= RX_3_START_ADDR && tx_mem_addr <= RX_3_END_ADDR) begin
							rx3_mem_addr <= tx_mem_addr - RX_3_START_ADDR;
							rx3_mem_size <= tx_mem_size;
							rx3_mem_enable <= 1;
							rx3_mem_w_mode <= tx_mem_w_mode;
							rx3_mem_w_data <= tx_mem_w_data;
							state <= BUSY_3;
						end else if (tx_mem_addr >= RX_4_START_ADDR && tx_mem_addr <= RX_4_END_ADDR) begin
							rx4_mem_addr <= tx_mem_addr - RX_4_START_ADDR;
							rx4_mem_size <= tx_mem_size;
							rx4_mem_enable <= 1;
							rx4_mem_w_mode <= tx_mem_w_mode;
							rx4_mem_w_data <= tx_mem_w_data;
							state <= BUSY_4;
						end else begin
							tx_mem_error <= 1;
						end
					end
				end
				BUSY_1: begin
					tx_mem_error <= rx1_mem_error;
					tx_mem_r_data <= rx1_mem_r_data;
					if (rx1_mem_done || rx1_mem_error)
						state <= READY;
				end
				BUSY_2: begin
					tx_mem_error <= rx2_mem_error;
					tx_mem_r_data <= rx2_mem_r_data;
					if (rx2_mem_done || rx2_mem_error)
						state <= READY;
				end
				BUSY_3: begin
					tx_mem_error <= rx3_mem_error;
					tx_mem_r_data <= rx3_mem_r_data;
					if (rx3_mem_done || rx3_mem_error)
						state <= READY;
				end
				BUSY_4: begin
					tx_mem_error <= rx4_mem_error;
					tx_mem_r_data <= rx4_mem_r_data;
					if (rx4_mem_done || rx4_mem_error)
						state <= READY;
				end
				default: begin
					tx_mem_error <= 1;
				end
			endcase
		end
	end
endmodule
module interconnect	#(
		parameter RX_1_START_ADDR = 32'h8000_0000,
		parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,
		parameter RX_2_START_ADDR = 32'h0201_0000,
		parameter RX_2_END_ADDR   = 32'h0201_03ff,
		parameter RX_3_START_ADDR = 32'h1001_3000,
		parameter RX_3_END_ADDR   = 32'h1001_3fff,
		parameter RX_4_START_ADDR = 32'h0200_0000,
		parameter RX_4_END_ADDR   = 32'h0200_ffff
	)
	(
		input reset,
		input clock,
		

		input [31:0] tx_mem_addr,
		input [`MEMORY_ACCESS_SIZE:0] tx_mem_size,
		input tx_mem_enable,
		input tx_mem_w_mode,
		input [31:0] tx_mem_w_data,
		output reg [31:0] tx_mem_r_data,
		output tx_mem_ready,
		output reg tx_mem_error,
		

		output reg [31:0] rx1_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,
		output reg rx1_mem_enable,
		output reg rx1_mem_w_mode,
		output reg [31:0] rx1_mem_w_data,
		input [31:0] rx1_mem_r_data,
		input rx1_mem_done,
		input rx1_mem_error,
		

		output reg [31:0] rx2_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,
		output reg rx2_mem_enable,
		output reg rx2_mem_w_mode,
		output reg [31:0] rx2_mem_w_data,
		input [31:0] rx2_mem_r_data,
		input rx2_mem_done,
		input rx2_mem_error,
		

		output reg [31:0] rx3_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx3_mem_size,
		output reg rx3_mem_enable,
		output reg rx3_mem_w_mode,
		output reg [31:0] rx3_mem_w_data,
		input [31:0] rx3_mem_r_data,
		input rx3_mem_done,
		input rx3_mem_error,
		

		output reg [31:0] rx4_mem_addr,
		output reg [`MEMORY_ACCESS_SIZE:0] rx4_mem_size,
		output reg rx4_mem_enable,
		output reg rx4_mem_w_mode,
		output reg [31:0] rx4_mem_w_data,
		input [31:0] rx4_mem_r_data,
		input rx4_mem_done,
		input rx4_mem_error
	);

	
	localparam READY = 0;
	localparam BUSY_1 = 1;
	localparam BUSY_2 = 2;
	localparam BUSY_3 = 3;
	localparam BUSY_4 = 4;
	
	reg [2:0] state;
	
	assign tx_mem_ready = state == READY && !tx_mem_enable;
	
	always @(posedge clock) begin
		if (reset) begin
			state <= READY;
			tx_mem_error <= 0;
			rx1_mem_enable <= 0;
			rx2_mem_enable <= 0;
			rx3_mem_enable <= 0;
			rx4_mem_enable <= 0;
		end else begin

			rx1_mem_enable <= 0;
			rx2_mem_enable <= 0;
			rx3_mem_enable <= 0;
			rx4_mem_enable <= 0;
					
			case (state)
				READY: begin
					if (tx_mem_enable) begin
						if (tx_mem_addr >= RX_1_START_ADDR && tx_mem_addr <= RX_1_END_ADDR) begin
							rx1_mem_addr <= tx_mem_addr - RX_1_START_ADDR;
							rx1_mem_size <= tx_mem_size;
							rx1_mem_enable <= 1;
							rx1_mem_w_mode <= tx_mem_w_mode;
							rx1_mem_w_data <= tx_mem_w_data;
							state <= BUSY_1;
						end else if (tx_mem_addr >= RX_2_START_ADDR && tx_mem_addr <= RX_2_END_ADDR) begin
							rx2_mem_addr <= tx_mem_addr - RX_2_START_ADDR;
							rx2_mem_size <= tx_mem_size;
							rx2_mem_enable <= 1;
							rx2_mem_w_mode <= tx_mem_w_mode;
							rx2_mem_w_data <= tx_mem_w_data;
							state <= BUSY_2;
						end else if (tx_mem_addr >= RX_3_START_ADDR && tx_mem_addr <= RX_3_END_ADDR) begin
							rx3_mem_addr <= tx_mem_addr - RX_3_START_ADDR;
							rx3_mem_size <= tx_mem_size;
							rx3_mem_enable <= 1;
							rx3_mem_w_mode <= tx_mem_w_mode;
							rx3_mem_w_data <= tx_mem_w_data;
							state <= BUSY_3;
						end else if (tx_mem_addr >= RX_4_START_ADDR && tx_mem_addr <= RX_4_END_ADDR) begin
							rx4_mem_addr <= tx_mem_addr - RX_4_START_ADDR;
							rx4_mem_size <= tx_mem_size;
							rx4_mem_enable <= 1;
							rx4_mem_w_mode <= tx_mem_w_mode;
							rx4_mem_w_data <= tx_mem_w_data;
							state <= BUSY_4;
						end else begin
							tx_mem_error <= 1;
						end
					end
				end
				BUSY_1: begin
					tx_mem_error <= rx1_mem_error;
					tx_mem_r_data <= rx1_mem_r_data;
					if (rx1_mem_done || rx1_mem_error)
						state <= READY;
				end
				BUSY_2: begin
					tx_mem_error <= rx2_mem_error;
					tx_mem_r_data <= rx2_mem_r_data;
					if (rx2_mem_done || rx2_mem_error)
						state <= READY;
				end
				BUSY_3: begin
					tx_mem_error <= rx3_mem_error;
					tx_mem_r_data <= rx3_mem_r_data;
					if (rx3_mem_done || rx3_mem_error)
						state <= READY;
				end
				BUSY_4: begin
					tx_mem_error <= rx4_mem_error;
					tx_mem_r_data <= rx4_mem_r_data;
					if (rx4_mem_done || rx4_mem_error)
						state <= READY;
				end
				default: begin
					tx_mem_error <= 1;
				end
			endcase
		end
	end
endmodule