data/full_repos/permissive/521337848/Hardware/procesor/connector.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/connector.v:35: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                        : ... Top module \'connector\'\nmodule connector(\n       ^~~~~~~~~\n                                                                                        : ... Top module \'innector\'\nmodule innector(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module innector(
	input clk,
	input rst,
	
	input[31:0] in,
	output reg[15:0] out1,
	output reg[15:0] out2
);

reg[15:0] r_out1;
reg[15:0] r_out2;

always@(posedge clk or posedge rst)begin
	if(rst) out1 <= 0;
	else out1 <= r_out1;
end

always@(posedge clk or posedge rst)begin
	if(rst) out2 <= 0;
	else out2 <= r_out2;
end


always@(*)begin
	r_out1 = out1;
	
	if(in[31]) begin
		r_out1 = in[31:16];
	end
end

always@(*)begin
	r_out2 = out2;
	
	if(in[31]) begin
		r_out2 = in[15:0];
	end
end

endmodule
module innector(
	input clk,
	input rst,
	
	input[31:0] in,
	output reg[15:0] out1,
	output reg[15:0] out2
);


reg[15:0] r_out1;
reg[15:0] r_out2;

always@(posedge clk or posedge rst)begin
	if(rst) out1 <= 0;
	else out1 <= r_out1;
end

always@(posedge clk or posedge rst)begin
	if(rst) out2 <= 0;
	else out2 <= r_out2;
end


always@(*)begin
	r_out1 = out1;
	
	if(in[31]) begin
		r_out1 = in[31:16];
	end
end

always@(*)begin
	r_out2 = out2;
	
	if(in[31]) begin
		r_out2 = in[15:0];
	end
end

endmodule