data/full_repos/permissive/454159683/sum5ba/sum5ba.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454159683/sum5ba/sum5ba.v:7: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'ci\' generates 1 bits.\n                                                                      : ... In instance sum5ba\n assign {co, so} = a + b + ci;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sum5ba(input[4:0] a, b, input ci, output co, output[4:0] so);
	assign {co, so} = a + b + ci;
endmodule
module sum5ba(input[4:0] a, b, input ci, output co, output[4:0] so);

	assign {co, so} = a + b + ci;
endmodule