data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n             #10 \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n               #10\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Error: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO_tb.v:31: Cannot find file containing module: \'DECO\'\n   DECO COMP_1   (\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/DECO\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/DECO.v\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/DECO.sv\n             DECO\n             DECO.v\n             DECO.sv\n             obj_dir/DECO\n             obj_dir/DECO.v\n             obj_dir/DECO.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DECO_tb(

    );
    reg [1:0]in_tb;
   reg en_tb;
    
    wire [3:0]out_tb;
      
   DECO COMP_1   (
    .in(in_tb), 
    .en(en_tb),
    .out(out_tb)
    );
    
    initial
            begin:  TST1 
               in_tb[0] = 1'b0;
               in_tb[1] = 1'd0;
               en_tb = 0; 
             #10 
               in_tb[0] = 1'b0;
               in_tb[1] = 1'd0;
               en_tb = 1;
               #10
                in_tb[0] = 1'd1;
                in_tb[1] = 1'd0;
                en_tb = 1; 
             #10
                in_tb[0] = 1'd0;
                in_tb[1] = 1'd1;
                en_tb = 1; 
            #10
                in_tb[0] = 1'd1;
                in_tb[1] = 1'd1;
                en_tb = 1; 
            #1000
            $finish; 
            end

endmodule
module DECO_tb(

    );

    reg [1:0]in_tb;
   reg en_tb;
    
    wire [3:0]out_tb;
      
   DECO COMP_1   (
    .in(in_tb), 
    .en(en_tb),
    .out(out_tb)
    );
    
    initial
            begin:  TST1 
               in_tb[0] = 1'b0;
               in_tb[1] = 1'd0;
               en_tb = 0; 
             #10 
               in_tb[0] = 1'b0;
               in_tb[1] = 1'd0;
               en_tb = 1;
               #10
                in_tb[0] = 1'd1;
                in_tb[1] = 1'd0;
                en_tb = 1; 
             #10
                in_tb[0] = 1'd0;
                in_tb[1] = 1'd1;
                en_tb = 1; 
            #10
                in_tb[0] = 1'd1;
                in_tb[1] = 1'd1;
                en_tb = 1; 
            #1000
            $finish; 
            end

endmodule