data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/ece241_2014_q7b/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.sv\n             Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826\n             Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.v\n             Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/ece241_2014_q7b,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7b/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    output wire OneHertz,
    output wire [2:0] c_enable
);

  wire [3:0] cQ0, cQ1, cQ2;

  assign c_enable[0] = 1;
  assign c_enable[1] = cQ0 == 9;
  assign c_enable[2] = cQ0 == 9 & cQ1 == 9;

  assign OneHertz = cQ0 == 9 & cQ1 == 9 & cQ2 == 9;

  bcdcount counter0 (
      clk,
      reset,
      c_enable[0],
      cQ0
  );
  bcdcount counter1 (
      clk,
      reset,
      c_enable[1],
      cQ1
  );
  bcdcount counter2 (
      clk,
      reset,
      c_enable[2],
      cQ2
  );

endmodule
module top_module (
    input wire clk,
    input wire reset,
    output wire OneHertz,
    output wire [2:0] c_enable
);


  wire [3:0] cQ0, cQ1, cQ2;

  assign c_enable[0] = 1;
  assign c_enable[1] = cQ0 == 9;
  assign c_enable[2] = cQ0 == 9 & cQ1 == 9;

  assign OneHertz = cQ0 == 9 & cQ1 == 9 & cQ2 == 9;

  bcdcount counter0 (
      clk,
      reset,
      c_enable[0],
      cQ0
  );
  bcdcount counter1 (
      clk,
      reset,
      c_enable[1],
      cQ1
  );
  bcdcount counter2 (
      clk,
      reset,
      c_enable[2],
      cQ2
  );

endmodule