data/full_repos/permissive/441359809/src/yosys/tests/sva/extnets.sv
data/verilator_xmls/9718adf1-bd25-495b-9904-2a3765982913.xml
module B;
	wire x, y, o;
	assign y = x, o = A.y;
endmodule
module B;

	wire x, y, o;
	assign y = x, o = A.y;
endmodule