data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:17: Unsupported or unknown PLI call: $monitor\n  $monitor (\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 A  = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #2 B  = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #4 A  = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #8 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #1 c0 = ~c0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:33: Unsupported: Ignoring delay on this delayed statement.\nalways #2 c1 = ~c1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:34: Unsupported: Ignoring delay on this delayed statement.\nalways #3 c2 = ~c2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/mux_from_gates.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #4 c3 = ~c3;\n       ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_from_gates ();
reg c0,c1,c2,c3,A,B; 
wire Y; 

not (a_inv, A); 
not (b_inv, B); 

and (y0,c0,a_inv,b_inv); 
and (y1,c1,a_inv,B); 
and (y2,c2,A,b_inv); 
and (y3,c3,A,B); 

or (Y, y0,y1,y2,y3); 


initial begin
  $monitor (
   "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b",
   c0, c1, c2, c3, A, B, Y);
  c0 = 0;
  c1 = 0;
  c2 = 0;
  c3 = 0;
  A = 0;
  B = 0;
  #1 A  = 1;
  #2 B  = 1;
  #4 A  = 0;
  #8 $finish;
end

always #1 c0 = ~c0;
always #2 c1 = ~c1;
always #3 c2 = ~c2;
always #4 c3 = ~c3;
   
endmodule
module mux_from_gates ();

reg c0,c1,c2,c3,A,B; 
wire Y; 

not (a_inv, A); 
not (b_inv, B); 

and (y0,c0,a_inv,b_inv); 
and (y1,c1,a_inv,B); 
and (y2,c2,A,b_inv); 
and (y3,c3,A,B); 

or (Y, y0,y1,y2,y3); 


initial begin
  $monitor (
   "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b",
   c0, c1, c2, c3, A, B, Y);
  c0 = 0;
  c1 = 0;
  c2 = 0;
  c3 = 0;
  A = 0;
  B = 0;
  #1 A  = 1;
  #2 B  = 1;
  #4 A  = 0;
  #8 $finish;
end

always #1 c0 = ~c0;
always #2 c1 = ~c1;
always #3 c2 = ~c2;
always #4 c3 = ~c3;
   
endmodule