data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:47: Operator LTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'write_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n            data[((write_pointer)<=(1) ? 0 : (write_pointer)<=(2) ? 1 : (write_pointer)<=(4) ? 2 : (write_pointer)<=(8) ? 3 : (write_pointer)<=(16) ? 4 : (write_pointer)<=(32) ? 5 : (write_pointer)<=(64) ? 6 : (write_pointer)<=(128) ? 7 : (write_pointer)<=(256) ? 8 : (write_pointer)<=(512) ? 9 : (write_pointer)<=(1024) ? 10 : -1)] <= write_data;\n                                                                                                                                                                                                                                                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:47: Operator LTE expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'write_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n            data[((write_pointer)<=(1) ? 0 : (write_pointer)<=(2) ? 1 : (write_pointer)<=(4) ? 2 : (write_pointer)<=(8) ? 3 : (write_pointer)<=(16) ? 4 : (write_pointer)<=(32) ? 5 : (write_pointer)<=(64) ? 6 : (write_pointer)<=(128) ? 7 : (write_pointer)<=(256) ? 8 : (write_pointer)<=(512) ? 9 : (write_pointer)<=(1024) ? 10 : -1)] <= write_data;\n                                                                                                                                                                                                                                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:47: Operator LTE expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'write_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n            data[((write_pointer)<=(1) ? 0 : (write_pointer)<=(2) ? 1 : (write_pointer)<=(4) ? 2 : (write_pointer)<=(8) ? 3 : (write_pointer)<=(16) ? 4 : (write_pointer)<=(32) ? 5 : (write_pointer)<=(64) ? 6 : (write_pointer)<=(128) ? 7 : (write_pointer)<=(256) ? 8 : (write_pointer)<=(512) ? 9 : (write_pointer)<=(1024) ? 10 : -1)] <= write_data;\n                                                                                                                                                                                                                                                                                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:50: Operator LTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'read_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n    assign read_data = data[((read_pointer)<=(1) ? 0 : (read_pointer)<=(2) ? 1 : (read_pointer)<=(4) ? 2 : (read_pointer)<=(8) ? 3 : (read_pointer)<=(16) ? 4 : (read_pointer)<=(32) ? 5 : (read_pointer)<=(64) ? 6 : (read_pointer)<=(128) ? 7 : (read_pointer)<=(256) ? 8 : (read_pointer)<=(512) ? 9 : (read_pointer)<=(1024) ? 10 : -1)];\n                                                                                                                                                                                                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:50: Operator LTE expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'read_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n    assign read_data = data[((read_pointer)<=(1) ? 0 : (read_pointer)<=(2) ? 1 : (read_pointer)<=(4) ? 2 : (read_pointer)<=(8) ? 3 : (read_pointer)<=(16) ? 4 : (read_pointer)<=(32) ? 5 : (read_pointer)<=(64) ? 6 : (read_pointer)<=(128) ? 7 : (read_pointer)<=(256) ? 8 : (read_pointer)<=(512) ? 9 : (read_pointer)<=(1024) ? 10 : -1)];\n                                                                                                                                                                                                                                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/axi/axi_slice_dc/dc_data_buffer.v:50: Operator LTE expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'read_pointer\' generates 8 bits.\n                                                                                                         : ... In instance dc_data_buffer\n    assign read_data = data[((read_pointer)<=(1) ? 0 : (read_pointer)<=(2) ? 1 : (read_pointer)<=(4) ? 2 : (read_pointer)<=(8) ? 3 : (read_pointer)<=(16) ? 4 : (read_pointer)<=(32) ? 5 : (read_pointer)<=(64) ? 6 : (read_pointer)<=(128) ? 7 : (read_pointer)<=(256) ? 8 : (read_pointer)<=(512) ? 9 : (read_pointer)<=(1024) ? 10 : -1)];\n                                                                                                                                                                                                                                                                                                                        ^~\n%Error: Exiting due to 6 warning(s)\n'
module dc_data_buffer(clk, rstn, write_pointer, write_data, read_pointer, read_data);

    parameter DATA_WIDTH   = 32;
    parameter BUFFER_DEPTH = 8;











        `define log2(N) ((N)<=(1) ? 0 : (N)<=(2) ? 1 : (N)<=(4) ? 2 : (N)<=(8) ? 3 : (N)<=(16) ? 4 : (N)<=(32) ? 5 : (N)<=(64) ? 6 : (N)<=(128) ? 7 : (N)<=(256) ? 8 : (N)<=(512) ? 9 : (N)<=(1024) ? 10 : -1)


    input                          clk;
    input                          rstn;

    input  [BUFFER_DEPTH - 1 : 0]  write_pointer;
    input  [DATA_WIDTH - 1 : 0]    write_data;
    input  [BUFFER_DEPTH - 1 : 0]  read_pointer;
    output [DATA_WIDTH - 1 : 0]    read_data;

    reg [DATA_WIDTH - 1 : 0]       data[BUFFER_DEPTH - 1 : 0];

    integer loop;

    always @(posedge clk  or negedge rstn)
    begin: read_write_data
        if (rstn == 1'b0)
            for (loop = 0; loop < BUFFER_DEPTH; loop = loop + 1)
                data[loop] <= 'h0;
        else
            data[`log2(write_pointer)] <= write_data;
    end

    assign read_data = data[`log2(read_pointer)];

endmodule
module dc_data_buffer(clk, rstn, write_pointer, write_data, read_pointer, read_data);


    parameter DATA_WIDTH   = 32;
    parameter BUFFER_DEPTH = 8;











        `define log2(N) ((N)<=(1) ? 0 : (N)<=(2) ? 1 : (N)<=(4) ? 2 : (N)<=(8) ? 3 : (N)<=(16) ? 4 : (N)<=(32) ? 5 : (N)<=(64) ? 6 : (N)<=(128) ? 7 : (N)<=(256) ? 8 : (N)<=(512) ? 9 : (N)<=(1024) ? 10 : -1)


    input                          clk;
    input                          rstn;

    input  [BUFFER_DEPTH - 1 : 0]  write_pointer;
    input  [DATA_WIDTH - 1 : 0]    write_data;
    input  [BUFFER_DEPTH - 1 : 0]  read_pointer;
    output [DATA_WIDTH - 1 : 0]    read_data;

    reg [DATA_WIDTH - 1 : 0]       data[BUFFER_DEPTH - 1 : 0];

    integer loop;

    always @(posedge clk  or negedge rstn)
    begin: read_write_data
        if (rstn == 1'b0)
            for (loop = 0; loop < BUFFER_DEPTH; loop = loop + 1)
                data[loop] <= 'h0;
        else
            data[`log2(write_pointer)] <= write_data;
    end

    assign read_data = data[`log2(read_pointer)];

endmodule