data/full_repos/permissive/42434302/ivltests/pr1780480.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1780480.v:12: Unsupported: Ignoring delay on this delayed statement.\n   #70 $finish;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr1780480.v:21: Unsupported or unknown PLI call: $monitor\n    $monitor("%0t\\ta(%b)", $time, count[0]);\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top ();

reg [1:0] count;

initial begin
   count = 0;
   #70 $finish;
end

always
    count = #20 count + 1;

initial


    $monitor("%0t\ta(%b)", $time, count[0]);

endmodule
module top ();


reg [1:0] count;

initial begin
   count = 0;
   #70 $finish;
end

always
    count = #20 count + 1;

initial


    $monitor("%0t\ta(%b)", $time, count[0]);

endmodule