data/full_repos/permissive/437157208/src/cont_1s_RCO.v
data/verilator_xmls/8c4cdaed-a2de-47f9-abda-79fc6903e515.xml
module cont_1s_RCO
	(
		input mclk, reset,
		output RCO
  	);

  localparam CUENTA= 10000;
  integer conteo;
  wire w1; 
  always@ (negedge reset, posedge mclk)
	begin
	   if (reset == 1'b0 ) conteo <= 0;
	   else
				if (conteo == CUENTA) conteo <=0;

				else conteo <= conteo + 1;
		end

	assign RCO = (conteo == CUENTA) ? 1'b1 : 1'b0 ;

	
	
	endmodule
module cont_1s_RCO
	(
		input mclk, reset,
		output RCO
  	);


  localparam CUENTA= 10000;
  integer conteo;
  wire w1; 
  always@ (negedge reset, posedge mclk)
	begin
	   if (reset == 1'b0 ) conteo <= 0;
	   else
				if (conteo == CUENTA) conteo <=0;

				else conteo <= conteo + 1;
		end

	assign RCO = (conteo == CUENTA) ? 1'b1 : 1'b0 ;

	
	
	endmodule