data/full_repos/permissive/494490807/bench/ISCAS/Verilog2/s510_synth.v
data/verilator_xmls/f0596d4e-7a07-49bf-b6fb-6dc5aa8b30c1.xml
module \s510.bench (john, cnt13, cnt21, cnt284, pcnt6, cnt261, cnt44, pcnt12, pcnt17, cnt591, cnt45, cnt567, pcnt27, cnt283, cnt272, cnt10, cnt511, pcnt241, cnt509, csm, pclr, pc, cclr, vsync, cblank, csync);
input
  cnt567,
  cnt591,
  pcnt12,
  pcnt17,
  cnt261,
  pcnt27,
  cnt272,
  cnt10,
  cnt13,
  cnt283,
  cnt284,
  cnt21,
  cnt44,
  cnt45,
  cnt509,
  cnt511,
  john,
  pcnt6,
  pcnt241;
output
  vsync,
  csm,
  csync,
  pc,
  pclr,
  cclr,
  cblank;
reg
  st_0,
  st_1,
  st_2,
  st_3,
  st_4,
  st_5;
wire
  \[25] ,
  \[13] ,
  \[26] ,
  \[14] ,
  \[27] ,
  \[15] ,
  \[28] ,
  \[16] ,
  \[29] ,
  II487,
  \[17] ,
  \[18] ,
  \[19] ,
  \[42] ,
  \[43] ,
  \[44] ,
  \[20] ,
  \[6] ,
  \[45] ,
  \[21] ,
  \[7] ,
  II531,
  \[34] ,
  \[22] ,
  \[8] ,
  \[10] ,
  \[23] ,
  II2,
  \[9] ,
  II3,
  \[11] ,
  II4,
  II5,
  II6,
  II7,
  \[36] ,
  \[24] ,
  \[12] ;
assign
  \[25]  = st_1 & st_5,
  vsync = \[10] ,
  \[13]  = II2,
  \[26]  = ~st_3 & st_4,
  \[14]  = II3,
  \[27]  = ~st_0 & st_2,
  csm = \[6] ,
  \[15]  = II4,
  \[28]  = st_2 & st_3,
  \[16]  = II5,
  \[29]  = ~st_1 & ~st_5,
  II487 = ~\[20]  & (~st_1 & (~st_2 & ~st_3)),
  \[17]  = II6,
  csync = \[12] ,
  \[18]  = II7,
  \[19]  = ~st_1 | ~st_3,
  pc = \[8] ,
  pclr = \[7] ,
  \[42]  = ~\[19]  & st_4,
  \[43]  = \[21]  & ~\[20] ,
  \[44]  = st_0 & st_1,
  cclr = \[9] ,
  \[20]  = st_4 | st_5,
  \[6]  = (\[28]  & (st_0 & st_5)) | (~\[19]  & (st_2 & st_5)),
  \[45]  = II487 & ~st_0,
  cblank = \[11] ,
  \[21]  = st_0 & ~st_2,
  \[7]  = (\[26]  & (\[23]  & st_0)) | (\[43]  & ~\[19] ),
  II531 = \[28]  & ~st_4,
  \[34]  = \[25]  | ~\[19] ,
  \[22]  = ~st_0 & ~st_2,
  \[8]  = (\[42]  & (st_0 & st_2)) | ((\[43]  & \[19] ) | II487),
  \[10]  = (\[29]  & ~II487) | ((\[23]  & ~st_4) | ((\[20]  & ~st_2) | (\[45]  | (\[44]  | st_3)))),
  \[23]  = st_1 & st_2,
  II2 = (~\[26]  & (\[24]  & (\[21]  & ~st_3))) | ((~\[27]  & (~\[21]  & st_5)) | ((\[27]  & (\[25]  & ~st_3)) | ((~\[23]  & (st_3 & st_5)) | (\[44]  & \[28] )))),
  \[9]  = (~st_0 & (~st_1 & ~\[10] )) | ((\[34]  & st_0) | ((\[24]  & ~st_5) | ((st_0 & st_4) | (\[21]  | II487)))),
  II3 = (\[29]  & (\[21]  & st_3)) | ((\[43]  & ~II487) | ((~\[36]  & \[24] ) | ((~st_0 & st_4) | ((st_1 & \[6] ) | \[45] )))),
  \[11]  = (\[42]  & \[21] ) | ((\[28]  & st_5) | ((\[25]  & \[21] ) | (II531 & ~st_0))),
  II4 = (~\[28]  & (\[20]  & st_3)) | ((~st_0 & (st_3 & ~st_5)) | ((\[44]  & \[43] ) | ((\[44]  & \[25] ) | ((\[26]  & \[24] ) | (II531 & ~st_1))))),
  II5 = (st_2 & (~II4 & (\[12]  & (\[10]  & ~cnt284)))) | ((\[44]  & (\[12]  & pcnt17)) | ((\[23]  & (~st_0 & ~cnt13)) | ((\[21]  & (st_1 & ~II3)) | ((\[21]  & (~\[12]  & ~\[7] )) | ((\[36]  & \[27] ) | ((\[28]  & \[12] ) | ((st_2 & \[7] ) | (II2 & ~\[10] )))))))),
  II6 = (\[23]  & (~II531 & (~st_0 & ~cnt13))) | ((\[23]  & (st_0 & (~II2 & ~pcnt17))) | ((\[23]  & (st_0 & (~II2 & ~cnt284))) | ((\[22]  & (st_1 & (~II4 & pcnt12))) | ((\[22]  & (st_1 & (~II4 & ~cnt44))) | ((\[26]  & (st_2 & ~II3)) | ((\[24]  & (st_3 & st_4)) | ((\[22]  & (~\[19]  & pcnt27)) | ((\[22]  & (~\[19]  & ~cnt567)) | ((\[21]  & (~st_1 & st_5)) | ((\[20]  & (~st_0 & st_1)) | ((II531 & (st_1 & pcnt241)) | ((II531 & (st_1 & ~cnt511)) | ((II531 & st_0) | ((st_5 & ~II2) | \[45] )))))))))))))),
  II7 = (\[29]  & (\[22]  & (st_3 & (st_4 & cnt45)))) | ((\[29]  & (~II4 & (~II3 & (pcnt6 & cnt284)))) | ((~\[28]  & (\[24]  & (st_2 & (st_5 & ~cnt261)))) | ((\[22]  & (~\[20]  & (st_1 & (~st_3 & cnt44)))) | ((\[29]  & (\[22]  & (~II3 & cnt591))) | ((\[28]  & (~st_1 & (st_4 & cnt21))) | ((\[28]  & (st_5 & (~\[6]  & cnt509))) | ((\[27]  & (\[26]  & (~st_1 & cnt45))) | ((\[27]  & (\[25]  & (~st_3 & cnt10))) | ((\[27]  & (~\[20]  & (~\[19]  & cnt511))) | ((\[26]  & (\[23]  & (II3 & john))) | ((\[22]  & (~\[20]  & (~\[19]  & cnt567))) | ((\[22]  & (~st_1 & (st_5 & cnt45))) | ((~\[20]  & (st_0 & (~st_3 & ~II3))) | ((\[42]  & (\[27]  & cnt10)) | ((\[42]  & (\[22]  & cnt283)) | ((\[29]  & (\[11]  & cnt272)) | ((\[28]  & (\[24]  & st_4)) | ((\[26]  & (\[22]  & cnt21)) | (\[25]  & (\[22]  & cnt44)))))))))))))))))))),
  \[36]  = st_4 | II2,
  \[24]  = st_0 & ~st_1,
  \[12]  = (~\[36]  & (~\[27]  & ~II3)) | ((~\[36]  & (\[27]  & ~st_1)) | ((\[36]  & (\[21]  & ~II487)) | ((~\[44]  & \[34] ) | ((\[24]  & st_4) | II531))));
always begin
  st_0 = \[18] ;
  st_1 = \[17] ;
  st_2 = \[16] ;
  st_3 = \[15] ;
  st_4 = \[14] ;
  st_5 = \[13] ;
end
initial begin
  st_0 = 0;
  st_1 = 0;
  st_2 = 0;
  st_3 = 0;
  st_4 = 0;
  st_5 = 0;
end
endmodule
module \s510.bench (john, cnt13, cnt21, cnt284, pcnt6, cnt261, cnt44, pcnt12, pcnt17, cnt591, cnt45, cnt567, pcnt27, cnt283, cnt272, cnt10, cnt511, pcnt241, cnt509, csm, pclr, pc, cclr, vsync, cblank, csync);

input
  cnt567,
  cnt591,
  pcnt12,
  pcnt17,
  cnt261,
  pcnt27,
  cnt272,
  cnt10,
  cnt13,
  cnt283,
  cnt284,
  cnt21,
  cnt44,
  cnt45,
  cnt509,
  cnt511,
  john,
  pcnt6,
  pcnt241;
output
  vsync,
  csm,
  csync,
  pc,
  pclr,
  cclr,
  cblank;
reg
  st_0,
  st_1,
  st_2,
  st_3,
  st_4,
  st_5;
wire
  \[25] ,
  \[13] ,
  \[26] ,
  \[14] ,
  \[27] ,
  \[15] ,
  \[28] ,
  \[16] ,
  \[29] ,
  II487,
  \[17] ,
  \[18] ,
  \[19] ,
  \[42] ,
  \[43] ,
  \[44] ,
  \[20] ,
  \[6] ,
  \[45] ,
  \[21] ,
  \[7] ,
  II531,
  \[34] ,
  \[22] ,
  \[8] ,
  \[10] ,
  \[23] ,
  II2,
  \[9] ,
  II3,
  \[11] ,
  II4,
  II5,
  II6,
  II7,
  \[36] ,
  \[24] ,
  \[12] ;
assign
  \[25]  = st_1 & st_5,
  vsync = \[10] ,
  \[13]  = II2,
  \[26]  = ~st_3 & st_4,
  \[14]  = II3,
  \[27]  = ~st_0 & st_2,
  csm = \[6] ,
  \[15]  = II4,
  \[28]  = st_2 & st_3,
  \[16]  = II5,
  \[29]  = ~st_1 & ~st_5,
  II487 = ~\[20]  & (~st_1 & (~st_2 & ~st_3)),
  \[17]  = II6,
  csync = \[12] ,
  \[18]  = II7,
  \[19]  = ~st_1 | ~st_3,
  pc = \[8] ,
  pclr = \[7] ,
  \[42]  = ~\[19]  & st_4,
  \[43]  = \[21]  & ~\[20] ,
  \[44]  = st_0 & st_1,
  cclr = \[9] ,
  \[20]  = st_4 | st_5,
  \[6]  = (\[28]  & (st_0 & st_5)) | (~\[19]  & (st_2 & st_5)),
  \[45]  = II487 & ~st_0,
  cblank = \[11] ,
  \[21]  = st_0 & ~st_2,
  \[7]  = (\[26]  & (\[23]  & st_0)) | (\[43]  & ~\[19] ),
  II531 = \[28]  & ~st_4,
  \[34]  = \[25]  | ~\[19] ,
  \[22]  = ~st_0 & ~st_2,
  \[8]  = (\[42]  & (st_0 & st_2)) | ((\[43]  & \[19] ) | II487),
  \[10]  = (\[29]  & ~II487) | ((\[23]  & ~st_4) | ((\[20]  & ~st_2) | (\[45]  | (\[44]  | st_3)))),
  \[23]  = st_1 & st_2,
  II2 = (~\[26]  & (\[24]  & (\[21]  & ~st_3))) | ((~\[27]  & (~\[21]  & st_5)) | ((\[27]  & (\[25]  & ~st_3)) | ((~\[23]  & (st_3 & st_5)) | (\[44]  & \[28] )))),
  \[9]  = (~st_0 & (~st_1 & ~\[10] )) | ((\[34]  & st_0) | ((\[24]  & ~st_5) | ((st_0 & st_4) | (\[21]  | II487)))),
  II3 = (\[29]  & (\[21]  & st_3)) | ((\[43]  & ~II487) | ((~\[36]  & \[24] ) | ((~st_0 & st_4) | ((st_1 & \[6] ) | \[45] )))),
  \[11]  = (\[42]  & \[21] ) | ((\[28]  & st_5) | ((\[25]  & \[21] ) | (II531 & ~st_0))),
  II4 = (~\[28]  & (\[20]  & st_3)) | ((~st_0 & (st_3 & ~st_5)) | ((\[44]  & \[43] ) | ((\[44]  & \[25] ) | ((\[26]  & \[24] ) | (II531 & ~st_1))))),
  II5 = (st_2 & (~II4 & (\[12]  & (\[10]  & ~cnt284)))) | ((\[44]  & (\[12]  & pcnt17)) | ((\[23]  & (~st_0 & ~cnt13)) | ((\[21]  & (st_1 & ~II3)) | ((\[21]  & (~\[12]  & ~\[7] )) | ((\[36]  & \[27] ) | ((\[28]  & \[12] ) | ((st_2 & \[7] ) | (II2 & ~\[10] )))))))),
  II6 = (\[23]  & (~II531 & (~st_0 & ~cnt13))) | ((\[23]  & (st_0 & (~II2 & ~pcnt17))) | ((\[23]  & (st_0 & (~II2 & ~cnt284))) | ((\[22]  & (st_1 & (~II4 & pcnt12))) | ((\[22]  & (st_1 & (~II4 & ~cnt44))) | ((\[26]  & (st_2 & ~II3)) | ((\[24]  & (st_3 & st_4)) | ((\[22]  & (~\[19]  & pcnt27)) | ((\[22]  & (~\[19]  & ~cnt567)) | ((\[21]  & (~st_1 & st_5)) | ((\[20]  & (~st_0 & st_1)) | ((II531 & (st_1 & pcnt241)) | ((II531 & (st_1 & ~cnt511)) | ((II531 & st_0) | ((st_5 & ~II2) | \[45] )))))))))))))),
  II7 = (\[29]  & (\[22]  & (st_3 & (st_4 & cnt45)))) | ((\[29]  & (~II4 & (~II3 & (pcnt6 & cnt284)))) | ((~\[28]  & (\[24]  & (st_2 & (st_5 & ~cnt261)))) | ((\[22]  & (~\[20]  & (st_1 & (~st_3 & cnt44)))) | ((\[29]  & (\[22]  & (~II3 & cnt591))) | ((\[28]  & (~st_1 & (st_4 & cnt21))) | ((\[28]  & (st_5 & (~\[6]  & cnt509))) | ((\[27]  & (\[26]  & (~st_1 & cnt45))) | ((\[27]  & (\[25]  & (~st_3 & cnt10))) | ((\[27]  & (~\[20]  & (~\[19]  & cnt511))) | ((\[26]  & (\[23]  & (II3 & john))) | ((\[22]  & (~\[20]  & (~\[19]  & cnt567))) | ((\[22]  & (~st_1 & (st_5 & cnt45))) | ((~\[20]  & (st_0 & (~st_3 & ~II3))) | ((\[42]  & (\[27]  & cnt10)) | ((\[42]  & (\[22]  & cnt283)) | ((\[29]  & (\[11]  & cnt272)) | ((\[28]  & (\[24]  & st_4)) | ((\[26]  & (\[22]  & cnt21)) | (\[25]  & (\[22]  & cnt44)))))))))))))))))))),
  \[36]  = st_4 | II2,
  \[24]  = st_0 & ~st_1,
  \[12]  = (~\[36]  & (~\[27]  & ~II3)) | ((~\[36]  & (\[27]  & ~st_1)) | ((\[36]  & (\[21]  & ~II487)) | ((~\[44]  & \[34] ) | ((\[24]  & st_4) | II531))));
always begin
  st_0 = \[18] ;
  st_1 = \[17] ;
  st_2 = \[16] ;
  st_3 = \[15] ;
  st_4 = \[14] ;
  st_5 = \[13] ;
end
initial begin
  st_0 = 0;
  st_1 = 0;
  st_2 = 0;
  st_3 = 0;
  st_4 = 0;
  st_5 = 0;
end
endmodule