data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:86: Cannot find file containing module: \'OBUFDS\'\n    OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/OBUFDS\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/OBUFDS.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300,data/full_repos/permissive/447976230/OBUFDS.sv\n             OBUFDS\n             OBUFDS.v\n             OBUFDS.sv\n             obj_dir/OBUFDS\n             obj_dir/OBUFDS.v\n             obj_dir/OBUFDS.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:87: Cannot find file containing module: \'ODDR\'\n    ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:94: Cannot find file containing module: \'OBUFDS\'\n   OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));\n   ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:95: Cannot find file containing module: \'ODDR\'\n   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame\n   ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:100: Cannot find file containing module: \'OBUFDS\'\n   OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));\n   ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/gen_ddrlvds.v:101: Cannot find file containing module: \'ODDR\'\n   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk\n   ^~~~\n%Error: Exiting due to 6 error(s)\n'
module gen_ddrlvds
  (

   input tx_clk_1x,

   input tx_clk_2x,



   input tx_dci_clk,

   input reset,

   output tx_clk_2x_p, 
   output tx_clk_2x_n,

   output tx_frame_p, 
   output tx_frame_n,


   output [7:0] tx_d_p, 
   output [7:0] tx_d_n,

   input [15:0] i, 
   input [15:0] q,

   input sync_dacs
   );

   reg [15:0] 	i_reg, q_reg;
   reg [15:0] 	i_2x, q_2x;
   reg 		rising_edge;
   wire [15:0] 	i_and_q_2x;
   reg 		sync_2x;
   
   genvar 	z;
   wire [7:0] 	tx_int;
   wire 	tx_clk_2x_int;
   wire 	tx_frame_int;


   (* keep = "true" *) reg phase, phase_2x, sync_dacs_reg;

   wire phase_eq_phase2x = (phase == phase_2x);

   always @(posedge tx_clk_1x)
     if (reset)
       phase <= 1'b0;
     else
       phase <= ~phase;





   always @(posedge tx_clk_1x) 
     begin
	i_reg <= i;
	q_reg <= q;
	sync_dacs_reg <= sync_dacs;
     end  

   always @(posedge tx_clk_2x)
     begin


	i_2x <= i_reg;
	q_2x <= q_reg;




	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0: (sync_dacs_reg) ? 1'b1: sync_2x;
	rising_edge <= (phase_eq_phase2x && ~sync_2x);
	phase_2x <= phase;
     end


   assign i_and_q_2x = rising_edge ? q_2x : i_2x;
   
   generate	
      for(z = 0; z < 8; z = z + 1)
	begin : gen_pins
	   OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));
	   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr
	     (.Q(tx_int[z]), .C(tx_clk_2x),
	      .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0));
	end
   endgenerate


   OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame
     (.Q(tx_frame_int), .C(tx_clk_2x),
      .CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0));


   OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk
     (.Q(tx_clk_2x_int), .C(tx_dci_clk),
      .CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0));

endmodule
module gen_ddrlvds
  (

   input tx_clk_1x,

   input tx_clk_2x,



   input tx_dci_clk,

   input reset,

   output tx_clk_2x_p, 
   output tx_clk_2x_n,

   output tx_frame_p, 
   output tx_frame_n,


   output [7:0] tx_d_p, 
   output [7:0] tx_d_n,

   input [15:0] i, 
   input [15:0] q,

   input sync_dacs
   );


   reg [15:0] 	i_reg, q_reg;
   reg [15:0] 	i_2x, q_2x;
   reg 		rising_edge;
   wire [15:0] 	i_and_q_2x;
   reg 		sync_2x;
   
   genvar 	z;
   wire [7:0] 	tx_int;
   wire 	tx_clk_2x_int;
   wire 	tx_frame_int;


   (* keep = "true" *) reg phase, phase_2x, sync_dacs_reg;

   wire phase_eq_phase2x = (phase == phase_2x);

   always @(posedge tx_clk_1x)
     if (reset)
       phase <= 1'b0;
     else
       phase <= ~phase;





   always @(posedge tx_clk_1x) 
     begin
	i_reg <= i;
	q_reg <= q;
	sync_dacs_reg <= sync_dacs;
     end  

   always @(posedge tx_clk_2x)
     begin


	i_2x <= i_reg;
	q_2x <= q_reg;




	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0: (sync_dacs_reg) ? 1'b1: sync_2x;
	rising_edge <= (phase_eq_phase2x && ~sync_2x);
	phase_2x <= phase;
     end


   assign i_and_q_2x = rising_edge ? q_2x : i_2x;
   
   generate	
      for(z = 0; z < 8; z = z + 1)
	begin : gen_pins
	   OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));
	   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr
	     (.Q(tx_int[z]), .C(tx_clk_2x),
	      .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0));
	end
   endgenerate


   OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame
     (.Q(tx_frame_int), .C(tx_clk_2x),
      .CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0));


   OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk
     (.Q(tx_clk_2x_int), .C(tx_dci_clk),
      .CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0));

endmodule