data/full_repos/permissive/432564927/Lab1 (Verilog)/Lab1_Unal (Verilog)/Unal_Lab1.srcs/sources_1/new/posEdgeDFF.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab1_Unal\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.sv\n             (Verilog)/Lab1_Unal\n             (Verilog)/Lab1_Unal.v\n             (Verilog)/Lab1_Unal.sv\n             obj_dir/(Verilog)/Lab1_Unal\n             obj_dir/(Verilog)/Lab1_Unal.v\n             obj_dir/(Verilog)/Lab1_Unal.sv\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sources_1/new,data/full_repos/permissive/432564927\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sources_1/new/posEdgeDFF.v\n%Error: Exiting due to 4 error(s)\n'
module posEdgeDFF(currentState,clk,clrn,nextState);

    input [2:0] nextState;
    input clk;
    input clrn;
    output reg [2:0] currentState;
      
    always @(posedge clk or clrn)
        if(~clrn) begin
            currentState <= 3'b0;
        end else begin
            currentState <= nextState;
        end
endmodule
module posEdgeDFF(currentState,clk,clrn,nextState);


    input [2:0] nextState;
    input clk;
    input clrn;
    output reg [2:0] currentState;
      
    always @(posedge clk or clrn)
        if(~clrn) begin
            currentState <= 3'b0;
        end else begin
            currentState <= nextState;
        end
endmodule