data/full_repos/permissive/489075769/write_address_ms.v
data/verilator_xmls/f15457a1-d9ea-432a-bc7c-4eb375d05308.xml
module write_address_slave(ACLK,ARESETn, AWVALID, i_AWREADY, o_AWREADY, i_AWADDR, o_AWADDR);
	input ACLK;
	input ARESETn;
	output reg o_AWREADY;
	input i_AWREADY;
	input AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;

	
	always @(posedge ACLK) begin  
		o_AWREADY <= i_AWREADY;
		if(ARESETn) begin
		o_AWADDR <= 32'b0;
		o_AWREADY <=1'b0;
		end
		
		if (AWVALID && o_AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 32'b0;
	
	end
	


endmodule
module write_address_slave(ACLK,ARESETn, AWVALID, i_AWREADY, o_AWREADY, i_AWADDR, o_AWADDR);

	input ACLK;
	input ARESETn;
	output reg o_AWREADY;
	input i_AWREADY;
	input AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;

	
	always @(posedge ACLK) begin  
		o_AWREADY <= i_AWREADY;
		if(ARESETn) begin
		o_AWADDR <= 32'b0;
		o_AWREADY <=1'b0;
		end
		
		if (AWVALID && o_AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 32'b0;
	
	end
	


endmodule