data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:640: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_nec_ir_receiver_registers\n              wbs_dat_o[31:0]  <= 31\'b0;\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:253: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_pulse_filter\n      filter_reg <= 1\'b0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:257: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_pulse_filter\n          filter_reg <= 1\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:219: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_metastability_filter\n      meta_i <= 1\'b0;\n             ^~\n%Error: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:71: Cannot find file containing module: \'prescaler\'\n  prescaler #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.v\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:144: Cannot find file containing module: \'simple_fifo\'\n  simple_fifo #(\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module nec_ir_receiver_registers #(
  parameter PSIZE = 32 ,
  parameter DSIZE = 32
)(

  input                   rst_n           ,
  input                   clk             ,


  output reg              receiver_en     ,
  output reg              repeat_en       ,
  output reg              polarity        ,
  output reg  [PSIZE-1:0] multiplier      ,
  output reg  [PSIZE-1:0] divider         ,
  output reg  [DSIZE-1:0] reload_offset   ,
  output reg  [DSIZE-1:0] delay_mask      ,


  input  wire             wbs_cyc_i       ,
  input  wire             wbs_stb_i       ,
  input  wire [31:0]      wbs_adr_i       ,
  input  wire             wbs_we_i        ,
  input  wire [31:0]      wbs_dat_i       ,
  input  wire [ 3:0]      wbs_sel_i       ,
  output reg  [31:0]      wbs_dat_o       ,
  output wire             wbs_ack_o       ,


  input  wire             frame_new       ,
  input  wire             frame_full_n    ,
  input  wire             frame_available ,
  input  wire [7:0]       frame_addr      ,
  input  wire [7:0]       frame_data      ,
  input  wire             frame_repeat    ,
  output reg              frame_read      ,


  output reg              irq

 );

  localparam
    cmd_reg_addr        = 2'b00,
    multiplier_reg_addr = 2'b01,
    divider_reg_addr    = 2'b10,
    status_reg_addr     = 2'b11;

  wire        valid;
  wire        rstrb;
  wire [31:0] wstrb;
  wire [1:0]  addr;

  reg  [1:0]  tolerance;
  reg         frame_lost;
  reg         ready;
  reg         irq_en;

  integer i = 0;

  assign valid     = wbs_cyc_i && wbs_stb_i;
  assign wstrb     = {{8{wbs_sel_i[3]}}, {8{wbs_sel_i[2]}}, {8{wbs_sel_i[1]}}, {8{wbs_sel_i[0]}}} & {32{wbs_we_i}};
  assign rstrb     = ~wbs_we_i;
  assign addr      = wbs_adr_i[3:2];
  assign wbs_ack_o = ready;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      ready       <= 1'b0;
      wbs_dat_o   <= 32'h00000000;
      tolerance   <= 2'b01;
      multiplier  <= {PSIZE{1'b0}};
      divider     <= {PSIZE{1'b0}};
      receiver_en <= 1'b0;
      repeat_en   <= 1'b0;
      irq_en      <= 1'b0;
      polarity    <= 1'b0;
      frame_lost  <= 1'b0;
      frame_read  <= 1'b0;
      irq         <= 1'b0;
    end else begin

      if (valid && !ready) begin


        case (addr)
          cmd_reg_addr : begin
            wbs_dat_o[31] <= receiver_en  ; if (wstrb[31]) receiver_en <= wbs_dat_i[31];
            wbs_dat_o[30] <= repeat_en    ; if (wstrb[30]) repeat_en   <= wbs_dat_i[30];
            wbs_dat_o[29] <= irq_en       ; if (wstrb[29]) irq_en      <= wbs_dat_i[29];
            wbs_dat_o[28] <= polarity     ; if (wstrb[28]) polarity    <= wbs_dat_i[28];
            wbs_dat_o[27] <= tolerance[1] ; if (wstrb[27]) tolerance[1]<= wbs_dat_i[27];
            wbs_dat_o[26] <= tolerance[0] ; if (wstrb[26]) tolerance[0]<= wbs_dat_i[26];
            wbs_dat_o[25:0] <= 26'b0;
          end
          multiplier_reg_addr : begin
            for (i = 0; i < 32; i = i + 1) begin
              if (i >= PSIZE) begin
                wbs_dat_o[i] <= 1'b0 ;
              end else begin
                wbs_dat_o[i] <= multiplier[i] ; if (wstrb[i]) multiplier[i] <= wbs_dat_i[i];
              end
            end
          end
          divider_reg_addr : begin
            for (i = 0; i < 32; i = i + 1) begin
              if (i >= PSIZE) begin
                wbs_dat_o[i] <= 1'b0 ;
              end else begin
                wbs_dat_o[i] <= divider[i] ; if (wstrb[i]) divider[i] <= wbs_dat_i[i];
              end
            end
          end
          status_reg_addr : begin

            if (frame_available == 1'b1) begin
              wbs_dat_o[31]    <= 1'b1;
              wbs_dat_o[30]    <= frame_repeat;
              wbs_dat_o[29]    <= frame_lost;
              wbs_dat_o[28:16] <= 13'b0;
              wbs_dat_o[15:8]  <= frame_addr;
              wbs_dat_o[7:0]   <= frame_data;
            end else begin
              wbs_dat_o[31:0]  <= 31'b0;
            end
          end
        endcase

        ready <= 1'b1;
      end else begin
        ready <= 1'b0;
      end

      if ((frame_new == 1'b1) && (frame_full_n == 1'b0)) begin
        frame_lost <= 1'b1;
      end else if (valid && !ready && rstrb && (addr == status_reg_addr)) begin
        frame_lost <= 1'b0;
      end

      if (valid && !ready && rstrb && (addr == status_reg_addr)) begin
        frame_read <= 1'b1;
      end else begin
        frame_read <= 1'b0;
      end

      if ((irq_en == 1'b1) && (frame_new == 1'b1)) begin
        irq <= 1'b1;
      end else begin
        irq <= 1'b0;
      end

    end
  end

  always @(*) begin
    case (tolerance)
      2'b00 : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b001};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b110};
      end
      2'b01 : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b010};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b100};
      end
      default : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b100};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b000};
      end
    endcase
  end

endmodule
module nec_ir_receiver_registers #(
  parameter PSIZE = 32 ,
  parameter DSIZE = 32
)(

  input                   rst_n           ,
  input                   clk             ,


  output reg              receiver_en     ,
  output reg              repeat_en       ,
  output reg              polarity        ,
  output reg  [PSIZE-1:0] multiplier      ,
  output reg  [PSIZE-1:0] divider         ,
  output reg  [DSIZE-1:0] reload_offset   ,
  output reg  [DSIZE-1:0] delay_mask      ,


  input  wire             wbs_cyc_i       ,
  input  wire             wbs_stb_i       ,
  input  wire [31:0]      wbs_adr_i       ,
  input  wire             wbs_we_i        ,
  input  wire [31:0]      wbs_dat_i       ,
  input  wire [ 3:0]      wbs_sel_i       ,
  output reg  [31:0]      wbs_dat_o       ,
  output wire             wbs_ack_o       ,


  input  wire             frame_new       ,
  input  wire             frame_full_n    ,
  input  wire             frame_available ,
  input  wire [7:0]       frame_addr      ,
  input  wire [7:0]       frame_data      ,
  input  wire             frame_repeat    ,
  output reg              frame_read      ,


  output reg              irq

 );


  localparam
    cmd_reg_addr        = 2'b00,
    multiplier_reg_addr = 2'b01,
    divider_reg_addr    = 2'b10,
    status_reg_addr     = 2'b11;

  wire        valid;
  wire        rstrb;
  wire [31:0] wstrb;
  wire [1:0]  addr;

  reg  [1:0]  tolerance;
  reg         frame_lost;
  reg         ready;
  reg         irq_en;

  integer i = 0;

  assign valid     = wbs_cyc_i && wbs_stb_i;
  assign wstrb     = {{8{wbs_sel_i[3]}}, {8{wbs_sel_i[2]}}, {8{wbs_sel_i[1]}}, {8{wbs_sel_i[0]}}} & {32{wbs_we_i}};
  assign rstrb     = ~wbs_we_i;
  assign addr      = wbs_adr_i[3:2];
  assign wbs_ack_o = ready;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      ready       <= 1'b0;
      wbs_dat_o   <= 32'h00000000;
      tolerance   <= 2'b01;
      multiplier  <= {PSIZE{1'b0}};
      divider     <= {PSIZE{1'b0}};
      receiver_en <= 1'b0;
      repeat_en   <= 1'b0;
      irq_en      <= 1'b0;
      polarity    <= 1'b0;
      frame_lost  <= 1'b0;
      frame_read  <= 1'b0;
      irq         <= 1'b0;
    end else begin

      if (valid && !ready) begin


        case (addr)
          cmd_reg_addr : begin
            wbs_dat_o[31] <= receiver_en  ; if (wstrb[31]) receiver_en <= wbs_dat_i[31];
            wbs_dat_o[30] <= repeat_en    ; if (wstrb[30]) repeat_en   <= wbs_dat_i[30];
            wbs_dat_o[29] <= irq_en       ; if (wstrb[29]) irq_en      <= wbs_dat_i[29];
            wbs_dat_o[28] <= polarity     ; if (wstrb[28]) polarity    <= wbs_dat_i[28];
            wbs_dat_o[27] <= tolerance[1] ; if (wstrb[27]) tolerance[1]<= wbs_dat_i[27];
            wbs_dat_o[26] <= tolerance[0] ; if (wstrb[26]) tolerance[0]<= wbs_dat_i[26];
            wbs_dat_o[25:0] <= 26'b0;
          end
          multiplier_reg_addr : begin
            for (i = 0; i < 32; i = i + 1) begin
              if (i >= PSIZE) begin
                wbs_dat_o[i] <= 1'b0 ;
              end else begin
                wbs_dat_o[i] <= multiplier[i] ; if (wstrb[i]) multiplier[i] <= wbs_dat_i[i];
              end
            end
          end
          divider_reg_addr : begin
            for (i = 0; i < 32; i = i + 1) begin
              if (i >= PSIZE) begin
                wbs_dat_o[i] <= 1'b0 ;
              end else begin
                wbs_dat_o[i] <= divider[i] ; if (wstrb[i]) divider[i] <= wbs_dat_i[i];
              end
            end
          end
          status_reg_addr : begin

            if (frame_available == 1'b1) begin
              wbs_dat_o[31]    <= 1'b1;
              wbs_dat_o[30]    <= frame_repeat;
              wbs_dat_o[29]    <= frame_lost;
              wbs_dat_o[28:16] <= 13'b0;
              wbs_dat_o[15:8]  <= frame_addr;
              wbs_dat_o[7:0]   <= frame_data;
            end else begin
              wbs_dat_o[31:0]  <= 31'b0;
            end
          end
        endcase

        ready <= 1'b1;
      end else begin
        ready <= 1'b0;
      end

      if ((frame_new == 1'b1) && (frame_full_n == 1'b0)) begin
        frame_lost <= 1'b1;
      end else if (valid && !ready && rstrb && (addr == status_reg_addr)) begin
        frame_lost <= 1'b0;
      end

      if (valid && !ready && rstrb && (addr == status_reg_addr)) begin
        frame_read <= 1'b1;
      end else begin
        frame_read <= 1'b0;
      end

      if ((irq_en == 1'b1) && (frame_new == 1'b1)) begin
        irq <= 1'b1;
      end else begin
        irq <= 1'b0;
      end

    end
  end

  always @(*) begin
    case (tolerance)
      2'b00 : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b001};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b110};
      end
      2'b01 : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b010};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b100};
      end
      default : begin
        reload_offset <= {{(DSIZE-3){1'b0}}, 3'b100};
        delay_mask    <= {{(DSIZE-3){1'b1}}, 3'b000};
      end
    endcase
  end

endmodule