data/full_repos/permissive/527176783/Single/A_Single/Conunit.v
1: b'%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:23: Define or directive not defined: \'`opRFormat\'\n            `opRFormat: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:23: syntax error, unexpected \':\', expecting endcase\n            `opRFormat: begin\n                      ^\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:25: Define or directive not defined: \'`funcADD\'\n                    `funcADD: Aluc =`ALUAdd;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:25: Define or directive not defined: \'`ALUAdd\'\n                    `funcADD: Aluc =`ALUAdd;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:26: Define or directive not defined: \'`funcADDU\'\n                    `funcADDU: Aluc =`ALUAdd;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:26: Define or directive not defined: \'`ALUAdd\'\n                    `funcADDU: Aluc =`ALUAdd;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:27: Define or directive not defined: \'`funcSUB\'\n                    `funcSUB: Aluc =`ALUSub;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:27: Define or directive not defined: \'`ALUSub\'\n                    `funcSUB: Aluc =`ALUSub;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:28: Define or directive not defined: \'`funcSUBU\'\n                    `funcSUBU: Aluc =`ALUSub;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:28: Define or directive not defined: \'`ALUSub\'\n                    `funcSUBU: Aluc =`ALUSub;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:29: Define or directive not defined: \'`funcAND\'\n                    `funcAND: Aluc =`ALUAnd;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:29: Define or directive not defined: \'`ALUAnd\'\n                    `funcAND: Aluc =`ALUAnd;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:30: Define or directive not defined: \'`funcXOR\'\n                    `funcXOR: Aluc =`ALUXor;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:30: Define or directive not defined: \'`ALUXor\'\n                    `funcXOR: Aluc =`ALUXor;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:31: Define or directive not defined: \'`funcOR\'\n                    `funcOR: Aluc =`ALUOr;\n                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:31: Define or directive not defined: \'`ALUOr\'\n                    `funcOR: Aluc =`ALUOr;\n                                   ^~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:32: Define or directive not defined: \'`funcSLL\'\n                    `funcSLL: Aluc =`ALUSll;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:32: Define or directive not defined: \'`ALUSll\'\n                    `funcSLL: Aluc =`ALUSll;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:33: Define or directive not defined: \'`funcSLLV\'\n                    `funcSLLV: Aluc =`ALUSll;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:33: Define or directive not defined: \'`ALUSll\'\n                    `funcSLLV: Aluc =`ALUSll;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:34: Define or directive not defined: \'`funcSLT\'\n                    `funcSLT: Aluc =`ALUCmps;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:34: Define or directive not defined: \'`ALUCmps\'\n                    `funcSLT: Aluc =`ALUCmps;\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:35: Define or directive not defined: \'`funcSLTU\'\n                    `funcSLTU: Aluc =`ALUCmpu;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:35: Define or directive not defined: \'`ALUCmpu\'\n                    `funcSLTU: Aluc =`ALUCmpu;\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:36: Define or directive not defined: \'`funcSRLV\'\n                    `funcSRLV: Aluc =`ALUSrl;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:36: Define or directive not defined: \'`ALUSrl\'\n                    `funcSRLV: Aluc =`ALUSrl;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:37: Define or directive not defined: \'`funcSRA\'\n                    `funcSRA,`funcSRAV: Aluc =`ALUSra;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:37: Define or directive not defined: \'`funcSRAV\'\n                    `funcSRA,`funcSRAV: Aluc =`ALUSra;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:37: Define or directive not defined: \'`ALUSra\'\n                    `funcSRA,`funcSRAV: Aluc =`ALUSra;\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:38: Define or directive not defined: \'`funcSRL\'\n                    `funcSRL: Aluc =`ALUSrl;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:38: Define or directive not defined: \'`ALUSrl\'\n                    `funcSRL: Aluc =`ALUSrl;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:41: Define or directive not defined: \'`ALUAdd\'\n                    default: Aluc = `ALUAdd;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:44: Define or directive not defined: \'`opADDI\'\n            `opADDI: Aluc = `ALUAdd;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:44: Define or directive not defined: \'`ALUAdd\'\n            `opADDI: Aluc = `ALUAdd;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:45: Define or directive not defined: \'`opADDIU\'\n            `opADDIU: Aluc = `ALUAdd;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:45: Define or directive not defined: \'`ALUAdd\'\n            `opADDIU: Aluc = `ALUAdd;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:46: Define or directive not defined: \'`opANDI\'\n            `opANDI: Aluc = `ALUAnd;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:46: Define or directive not defined: \'`ALUAnd\'\n            `opANDI: Aluc = `ALUAnd;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:48: Define or directive not defined: \'`opORI\'\n            `opORI: Aluc = `ALUOr;\n            ^~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:48: Define or directive not defined: \'`ALUOr\'\n            `opORI: Aluc = `ALUOr;\n                           ^~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:49: Define or directive not defined: \'`opSLTI\'\n            `opSLTI: Aluc = `ALUCmps;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:49: Define or directive not defined: \'`ALUCmps\'\n            `opSLTI: Aluc = `ALUCmps;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:50: Define or directive not defined: \'`opSLTIU\'\n            `opSLTIU: Aluc = `ALUCmpu;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:50: Define or directive not defined: \'`ALUCmpu\'\n            `opSLTIU: Aluc = `ALUCmpu;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:51: Define or directive not defined: \'`opXORI\'\n            `opXORI: Aluc = `ALUXor; \n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:51: Define or directive not defined: \'`ALUXor\'\n            `opXORI: Aluc = `ALUXor; \n                            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:52: Define or directive not defined: \'`opSW\'\n            `opSW: Aluc = `ALUAdd;\n            ^~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:52: Define or directive not defined: \'`ALUAdd\'\n            `opSW: Aluc = `ALUAdd;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/Conunit.v:53: Define or directive not defined: \'`opLW\'\n            `opLW: Aluc = `ALUAdd;\n            ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Conunit(
    input   wire  [5:0] Func,
    input   wire  [5:0] Op,
    input   wire  [4:0] rt,
    input   wire        Zero,
    input   wire        Sign,
    output  reg   [3:0] Aluc,
    output  reg          AluSrcA,
    output  reg          AluSrcB,
    output  reg    [1:0] PcSrc,
    output  reg          Wrback,
    output  reg          RegDst,
    output  reg          ExtSe,
    output  reg          memWr,
    output  reg          regWr
);

    always @(*) begin
        case (Op)
            `opRFormat: begin
                case(Func)
                    `funcADD: Aluc =`ALUAdd;
                    `funcADDU: Aluc =`ALUAdd;
                    `funcSUB: Aluc =`ALUSub;
                    `funcSUBU: Aluc =`ALUSub;
                    `funcAND: Aluc =`ALUAnd;
                    `funcXOR: Aluc =`ALUXor;
                    `funcOR: Aluc =`ALUOr;
                    `funcSLL: Aluc =`ALUSll;
                    `funcSLLV: Aluc =`ALUSll;
                    `funcSLT: Aluc =`ALUCmps;
                    `funcSLTU: Aluc =`ALUCmpu;
                    `funcSRLV: Aluc =`ALUSrl;
                    `funcSRA,`funcSRAV: Aluc =`ALUSra;
                    `funcSRL: Aluc =`ALUSrl;


                    default: Aluc = `ALUAdd;
                endcase
            end
            `opADDI: Aluc = `ALUAdd;
            `opADDIU: Aluc = `ALUAdd;
            `opANDI: Aluc = `ALUAnd;

            `opORI: Aluc = `ALUOr;
            `opSLTI: Aluc = `ALUCmps;
            `opSLTIU: Aluc = `ALUCmpu;
            `opXORI: Aluc = `ALUXor;
            `opSW: Aluc = `ALUAdd;
            `opLW: Aluc = `ALUAdd;
            `opSB: Aluc = `ALUAdd;
            `opLB: Aluc = `ALUAdd;
            `opBEQ: Aluc =`ALUSub;
            `opBNE: Aluc =`ALUSub;
            `opBGEZ: Aluc =`ALUSubZero;
            `opBGTZ: Aluc =`ALUSubZero;
            `opBLEZ: Aluc =`ALUSubZero;
            `opBLTZ: Aluc =`ALUSubZero;
            `opLUI: Aluc = `ALUJoint;




            default: Aluc = `ALUAdd;
        endcase
    end


    always @(*) begin
        case({Op,Func})
            {`opSLL,`funcSLL},{`opSRA,`funcSRA},{`opSRL,`funcSRL}: AluSrcA = `FromSA;
            default: AluSrcA = `FromData;
        endcase
    end


    always @(*) begin
        case(Op)
            `opADDI,`opADDIU,`opSLTI,`opSLTIU: AluSrcB = `FromImmd;
            `opORI,`opLUI,`opXORI: AluSrcB = `FromImmd;
            `opSW,`opLW,`opSB,`opLB: AluSrcB = `FromImmd;
            default: AluSrcB = `FromData;
        endcase
    end


    always @(*) begin
        case(Op)
            `opJAL,`opJ: PcSrc = `Jump;
            `opJR: begin
                case (Func)
                    `funcJR: PcSrc = `Jump; 
                    default: PcSrc = `NextIns;
                endcase
            end
            `opBEQ: PcSrc = (Zero == 1) ? `Branch : `NextIns;
            `opBNE: PcSrc = (Zero == 0) ? `Branch : `NextIns;
            `opBGTZ: PcSrc = (Sign == 0 && Zero == 0) ? `Branch : `NextIns;
            `opBLTZ: begin
                case (rt)
                    5'd1: PcSrc = (Sign == 0) ? `Branch : `NextIns;
                    default: PcSrc = (Sign == 1) ? `Branch : `NextIns;
                endcase
            end


            `opBLEZ: PcSrc = (Sign == 1 || Zero == 0) ? `Branch : `NextIns;
            default:PcSrc = `NextIns;
        endcase
    end


    always @(*) begin
        case(Op)
            `opLW,`opLB: Wrback = `FromDM;
            default: Wrback = `FromALU;
        endcase
    end
    

    always @(*) begin
        case(Op)
            `opADDIU,`opSLTI,`opSLTIU: RegDst = `FromRt;
            `opLW,`opLB: RegDst = `FromRt;
            `opADDI,`opORI,`opANDI,`opXORI,`opLUI: RegDst = `FromRt;
            default: RegDst = `FromRd;
        endcase
    end


    always @(*) begin
        case(Op)
            `opORI,`opANDI,`opXORI: ExtSe = `ZeroExd;
            default: ExtSe = `SignExd;
        endcase
    end


    always @(*) begin
        case(Op)
            `opSW,`opSB: memWr = 1;
            default: memWr = 0;
        endcase
    end


    always @(*) begin
        case(Op)
            `opSW,`opSB,`opBEQ,`opBNE,`opBGTZ,`opBGEZ,`opBLTZ,`opBLEZ: regWr = 0;
            `opJ,`opJAL: regWr = 0;
            `opJR: begin
                case (Func)
                    `funcJR: regWr = 0;
                    default: regWr = 1;
                endcase
            end
            default regWr = 1;
        endcase
    end
    

endmodule
module Conunit(
    input   wire  [5:0] Func,
    input   wire  [5:0] Op,
    input   wire  [4:0] rt,
    input   wire        Zero,
    input   wire        Sign,
    output  reg   [3:0] Aluc,
    output  reg          AluSrcA,
    output  reg          AluSrcB,
    output  reg    [1:0] PcSrc,
    output  reg          Wrback,
    output  reg          RegDst,
    output  reg          ExtSe,
    output  reg          memWr,
    output  reg          regWr
);


    always @(*) begin
        case (Op)
            `opRFormat: begin
                case(Func)
                    `funcADD: Aluc =`ALUAdd;
                    `funcADDU: Aluc =`ALUAdd;
                    `funcSUB: Aluc =`ALUSub;
                    `funcSUBU: Aluc =`ALUSub;
                    `funcAND: Aluc =`ALUAnd;
                    `funcXOR: Aluc =`ALUXor;
                    `funcOR: Aluc =`ALUOr;
                    `funcSLL: Aluc =`ALUSll;
                    `funcSLLV: Aluc =`ALUSll;
                    `funcSLT: Aluc =`ALUCmps;
                    `funcSLTU: Aluc =`ALUCmpu;
                    `funcSRLV: Aluc =`ALUSrl;
                    `funcSRA,`funcSRAV: Aluc =`ALUSra;
                    `funcSRL: Aluc =`ALUSrl;


                    default: Aluc = `ALUAdd;
                endcase
            end
            `opADDI: Aluc = `ALUAdd;
            `opADDIU: Aluc = `ALUAdd;
            `opANDI: Aluc = `ALUAnd;

            `opORI: Aluc = `ALUOr;
            `opSLTI: Aluc = `ALUCmps;
            `opSLTIU: Aluc = `ALUCmpu;
            `opXORI: Aluc = `ALUXor;
            `opSW: Aluc = `ALUAdd;
            `opLW: Aluc = `ALUAdd;
            `opSB: Aluc = `ALUAdd;
            `opLB: Aluc = `ALUAdd;
            `opBEQ: Aluc =`ALUSub;
            `opBNE: Aluc =`ALUSub;
            `opBGEZ: Aluc =`ALUSubZero;
            `opBGTZ: Aluc =`ALUSubZero;
            `opBLEZ: Aluc =`ALUSubZero;
            `opBLTZ: Aluc =`ALUSubZero;
            `opLUI: Aluc = `ALUJoint;




            default: Aluc = `ALUAdd;
        endcase
    end


    always @(*) begin
        case({Op,Func})
            {`opSLL,`funcSLL},{`opSRA,`funcSRA},{`opSRL,`funcSRL}: AluSrcA = `FromSA;
            default: AluSrcA = `FromData;
        endcase
    end


    always @(*) begin
        case(Op)
            `opADDI,`opADDIU,`opSLTI,`opSLTIU: AluSrcB = `FromImmd;
            `opORI,`opLUI,`opXORI: AluSrcB = `FromImmd;
            `opSW,`opLW,`opSB,`opLB: AluSrcB = `FromImmd;
            default: AluSrcB = `FromData;
        endcase
    end


    always @(*) begin
        case(Op)
            `opJAL,`opJ: PcSrc = `Jump;
            `opJR: begin
                case (Func)
                    `funcJR: PcSrc = `Jump; 
                    default: PcSrc = `NextIns;
                endcase
            end
            `opBEQ: PcSrc = (Zero == 1) ? `Branch : `NextIns;
            `opBNE: PcSrc = (Zero == 0) ? `Branch : `NextIns;
            `opBGTZ: PcSrc = (Sign == 0 && Zero == 0) ? `Branch : `NextIns;
            `opBLTZ: begin
                case (rt)
                    5'd1: PcSrc = (Sign == 0) ? `Branch : `NextIns;
                    default: PcSrc = (Sign == 1) ? `Branch : `NextIns;
                endcase
            end


            `opBLEZ: PcSrc = (Sign == 1 || Zero == 0) ? `Branch : `NextIns;
            default:PcSrc = `NextIns;
        endcase
    end


    always @(*) begin
        case(Op)
            `opLW,`opLB: Wrback = `FromDM;
            default: Wrback = `FromALU;
        endcase
    end
    

    always @(*) begin
        case(Op)
            `opADDIU,`opSLTI,`opSLTIU: RegDst = `FromRt;
            `opLW,`opLB: RegDst = `FromRt;
            `opADDI,`opORI,`opANDI,`opXORI,`opLUI: RegDst = `FromRt;
            default: RegDst = `FromRd;
        endcase
    end


    always @(*) begin
        case(Op)
            `opORI,`opANDI,`opXORI: ExtSe = `ZeroExd;
            default: ExtSe = `SignExd;
        endcase
    end


    always @(*) begin
        case(Op)
            `opSW,`opSB: memWr = 1;
            default: memWr = 0;
        endcase
    end


    always @(*) begin
        case(Op)
            `opSW,`opSB,`opBEQ,`opBNE,`opBGTZ,`opBGEZ,`opBLTZ,`opBLEZ: regWr = 0;
            `opJ,`opJAL: regWr = 0;
            `opJR: begin
                case (Func)
                    `funcJR: regWr = 0;
                    default: regWr = 1;
                endcase
            end
            default regWr = 1;
        endcase
    end
    

endmodule