data/full_repos/permissive/423852699/verilog/Mux4.v
data/verilator_xmls/4db5f7fb-0d2f-40c1-80dd-f9f1c127a418.xml
module Mux4 (
    input wire[31:0] in0,
    input wire[31:0] in1,
    input wire[31:0] in2,
    input wire[31:0] in3,
    input wire[1:0] sel,

    output wire[31:0] out
);
    reg[31:0] temp;

    always @(*) begin
        case (sel)
            2'b00:
                temp = in0;
            2'b01:
                temp = in1;
            2'b10:
                temp = in2;
            default:
                temp = in3; 
        endcase
    end

    assign out = temp;
endmodule
module Mux4 (
    input wire[31:0] in0,
    input wire[31:0] in1,
    input wire[31:0] in2,
    input wire[31:0] in3,
    input wire[1:0] sel,

    output wire[31:0] out
);

    reg[31:0] temp;

    always @(*) begin
        case (sel)
            2'b00:
                temp = in0;
            2'b01:
                temp = in1;
            2'b10:
                temp = in2;
            default:
                temp = in3; 
        endcase
    end

    assign out = temp;
endmodule