data/full_repos/permissive/472385934/control_unit.v
data/verilator_xmls/8b0e7ebe-7d2e-4a8d-beaa-ba31b453d6b4.xml
module alu_decoder(
input [5:0]funct,
input rst_n,
input [3:0]aluop,
output mult_sel,
output [3:0]func);

reg [4:0] ctr;
assign {mult_sel,func} = ctr;

always@(*) begin
    if(!rst_n) 
        ctr = 5'b0;
    else if (aluop == 4'b1111) begin
        case(funct)
            6'b100000: ctr = 5'b01000;
            6'b100001: ctr = 5'b00000;
            6'b100010: ctr = 5'b01001;
            6'b100011: ctr = 5'b00001;
            6'b100100: ctr = 5'b00010;
            6'b100101: ctr = 5'b00011;
            6'b100110: ctr = 5'b00100;
            6'b100111: ctr = 5'b00101;
            6'b101010: ctr = 5'b01110;
            6'b101011: ctr = 5'b00110;
            6'b000111: ctr = 5'b11000;
            6'b000101: ctr = 5'b10000;
        endcase
    end
    else
        ctr = {1'b0,aluop};
end
endmodule
module alu_decoder(
input [5:0]funct,
input rst_n,
input [3:0]aluop,
output mult_sel,
output [3:0]func);


reg [4:0] ctr;
assign {mult_sel,func} = ctr;

always@(*) begin
    if(!rst_n) 
        ctr = 5'b0;
    else if (aluop == 4'b1111) begin
        case(funct)
            6'b100000: ctr = 5'b01000;
            6'b100001: ctr = 5'b00000;
            6'b100010: ctr = 5'b01001;
            6'b100011: ctr = 5'b00001;
            6'b100100: ctr = 5'b00010;
            6'b100101: ctr = 5'b00011;
            6'b100110: ctr = 5'b00100;
            6'b100111: ctr = 5'b00101;
            6'b101010: ctr = 5'b01110;
            6'b101011: ctr = 5'b00110;
            6'b000111: ctr = 5'b11000;
            6'b000101: ctr = 5'b10000;
        endcase
    end
    else
        ctr = {1'b0,aluop};
end
endmodule