data/full_repos/permissive/417163447/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/417163447/top.v:18: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                             : ... In instance two_tap_lfsr\n            lfsr[6:0] <= lfsr >> 1;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module two_tap_lfsr #(parameter tap_one = 2,
                      parameter tap_two = 4) (
                      input clk,
                      input [7:0] seed,
                      input enable,
                      input reset,
                      output reg [7:0] lfsr
                      );
           
  always @(posedge(clk)) begin
        if (reset) begin
            lfsr <= 8'b00000001;
        end
        else if (enable) begin
            lfsr <= seed;
        end
        else begin
            lfsr[6:0] <= lfsr >> 1;
            lfsr[7] <= lfsr[0] ^ lfsr[tap_one] ^ lfsr [tap_two];
        end
    end
endmodule
module two_tap_lfsr #(parameter tap_one = 2,
                      parameter tap_two = 4) (
                      input clk,
                      input [7:0] seed,
                      input enable,
                      input reset,
                      output reg [7:0] lfsr
                      );

           
  always @(posedge(clk)) begin
        if (reset) begin
            lfsr <= 8'b00000001;
        end
        else if (enable) begin
            lfsr <= seed;
        end
        else begin
            lfsr[6:0] <= lfsr >> 1;
            lfsr[7] <= lfsr[0] ^ lfsr[tap_one] ^ lfsr [tap_two];
        end
    end
endmodule