data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v
1: b"%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:7: syntax error, unexpected inside, expecting '['\n    output wire inside,\n                ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire origin_location,\n    ^~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire areaSign\n    ^~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:28: syntax error, unexpected always\n    always @(*) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:44: syntax error, unexpected IDENTIFIER\n    halfSpaceEquation Eab(Pin,Pa,Pb,outab,lt0ab,gt0ab);\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:48: syntax error, unexpected assign\n    assign antiClockInside = gt0ab && gt0bc && gt0ca;  \n    ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:74: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub1 (.control(1'b0), .subOp(1'b1), .a(xp), .b(xva), .roundingMode(`round_min), .out(sub1), .exceptionFlags());\n                                                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:75: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub2 (.control(1'b0), .subOp(1'b1), .a(yvb), .b(yva), .roundingMode(`round_min), .out(sub2), .exceptionFlags());\n                                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:76: Define or directive not defined: '`round_min'\n    mulRecFN #(8,24) fpmul1 (.control(1'b0), .a(sub1), .b(sub2), .roundingMode(`round_min), .out(mul1), .exceptionFlags());\n                                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:78: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub3 (.control(1'b0), .subOp(1'b1), .a(yp), .b(yva), .roundingMode(`round_min), .out(sub3), .exceptionFlags());\n                                                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:79: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub4 (.control(1'b0), .subOp(1'b1), .a(xvb), .b(xva), .roundingMode(`round_min), .out(sub4), .exceptionFlags());\n                                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:80: Define or directive not defined: '`round_min'\n    mulRecFN #(8,24) fpmul2 (.control(1'b0), .a(sub3), .b(sub4), .roundingMode(`round_min), .out(mul2), .exceptionFlags());\n                                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:82: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub5 (.control(1'b0), .subOp(1'b1), .a(mul1), .b(mul2), .roundingMode(`round_min), .out(out), .exceptionFlags());\n                                                                                             ^~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module pointSampler(
    input wire [65:0] Pa,
    input wire [65:0] Pb,
    input wire [65:0] Pc,
    input wire [65:0] Pin,
    output wire [65:0] Pout,
    output wire inside,
    input wire windingOrder,
    input wire origin_location,
    input wire areaSign

);

    localparam CW = 1'b1 ;
    localparam ACW = 1'b0;


    localparam TL = 1'b0;
    localparam BL = 1'b1;

    localparam FORWARDS = 1'b0;
    localparam BACKWARDS = 1'b1;

    localparam PLUS = 1'b0;
    localparam MINUS = 1'b1;

    reg for_or_back;
    always @(*) begin
        case({origin_location, windingOrder, areaSign})
            {TL, CW, PLUS}: for_or_back = FORWARDS;
            {TL, CW, MINUS}: for_or_back = BACKWARDS;
            {TL, ACW, PLUS}: for_or_back = BACKWARDS;
            {TL, ACW, MINUS}: for_or_back = FORWARDS;
            {BL, CW, PLUS}: for_or_back = BACKWARDS;
            {BL, CW, MINUS}: for_or_back = FORWARDS;
            {BL, ACW, PLUS}: for_or_back = FORWARDS;
            {BL, ACW, MINUS}: for_or_back = BACKWARDS;
        endcase
    end



    wire [32:0] outab, outbc, outca;
    halfSpaceEquation Eab(Pin,Pa,Pb,outab,lt0ab,gt0ab);
    halfSpaceEquation Ebc(Pin,Pb,Pc,outbc,lt0bc,gt0bc);
    halfSpaceEquation Eca(Pin,Pc,Pa,outca,lt0ca,gt0ca);
    wire antiClockInside, clockInside;
    assign antiClockInside = gt0ab && gt0bc && gt0ca;
    assign clockInside = lt0ab && lt0bc && lt0ca;
    assign inside = (windingOrder ^ origin_location) ^ for_or_back ? clockInside : antiClockInside;
    assign Pout = Pin;
        
        
endmodule
module pointSampler(
    input wire [65:0] Pa,
    input wire [65:0] Pb,
    input wire [65:0] Pc,
    input wire [65:0] Pin,
    output wire [65:0] Pout,
    output wire inside,
    input wire windingOrder,
    input wire origin_location,
    input wire areaSign

);


    localparam CW = 1'b1 ;
    localparam ACW = 1'b0;


    localparam TL = 1'b0;
    localparam BL = 1'b1;

    localparam FORWARDS = 1'b0;
    localparam BACKWARDS = 1'b1;

    localparam PLUS = 1'b0;
    localparam MINUS = 1'b1;

    reg for_or_back;
    always @(*) begin
        case({origin_location, windingOrder, areaSign})
            {TL, CW, PLUS}: for_or_back = FORWARDS;
            {TL, CW, MINUS}: for_or_back = BACKWARDS;
            {TL, ACW, PLUS}: for_or_back = BACKWARDS;
            {TL, ACW, MINUS}: for_or_back = FORWARDS;
            {BL, CW, PLUS}: for_or_back = BACKWARDS;
            {BL, CW, MINUS}: for_or_back = FORWARDS;
            {BL, ACW, PLUS}: for_or_back = FORWARDS;
            {BL, ACW, MINUS}: for_or_back = BACKWARDS;
        endcase
    end



    wire [32:0] outab, outbc, outca;
    halfSpaceEquation Eab(Pin,Pa,Pb,outab,lt0ab,gt0ab);
    halfSpaceEquation Ebc(Pin,Pb,Pc,outbc,lt0bc,gt0bc);
    halfSpaceEquation Eca(Pin,Pc,Pa,outca,lt0ca,gt0ca);
    wire antiClockInside, clockInside;
    assign antiClockInside = gt0ab && gt0bc && gt0ca;
    assign clockInside = lt0ab && lt0bc && lt0ca;
    assign inside = (windingOrder ^ origin_location) ^ for_or_back ? clockInside : antiClockInside;
    assign Pout = Pin;
        
        
endmodule