data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/83816707-9daa-4bf5-bc10-0e1f6445f6a9.xml
module dut_type_wrapper(
      clk,
       rst,
       din_1_busy,
       din_1_vld,
       din_1_data,
       din_2_busy,
       din_2_vld,
       din_2_data,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";
    *);

	input clk;
	input rst;
	output din_1_busy;
	input din_1_vld;
	input [7:0] din_1_data;
	output din_2_busy;
	input din_2_vld;
	input [7:0] din_2_data;
	input dout_busy;
	output dout_vld;
	output [8:0] dout_data;


endmodule
module dut_type_wrapper(
      clk,
       rst,
       din_1_busy,
       din_1_vld,
       din_1_data,
       din_2_busy,
       din_2_vld,
       din_2_data,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";

    *);

	input clk;
	input rst;
	output din_1_busy;
	input din_1_vld;
	input [7:0] din_1_data;
	output din_2_busy;
	input din_2_vld;
	input [7:0] din_2_data;
	input dout_busy;
	output dout_vld;
	output [8:0] dout_data;


endmodule