data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:82: Define or directive not defined: '`WB_VEC_VLD'\nassign read_data_y[`WB_VEC_VLD] = wb || wb_en_x && !cnt;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:82: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign read_data_y[`WB_VEC_VLD] = wb || wb_en_x && !cnt;\n                              ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:100: Define or directive not defined: '`WB_VEC_TYPE'\nassign read_data_y[`WB_VEC_TYPE] = inst_type;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:100: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign read_data_y[`WB_VEC_TYPE] = inst_type;\n                               ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:121: Define or directive not defined: '`WB_VEC_TYPE_VLSU'\n                            && (dp_wbt_bankx_dstv_type == `WB_VEC_TYPE_VLSU);\n                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:121: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n                            && (dp_wbt_bankx_dstv_type == `WB_VEC_TYPE_VLSU);\n                                                                           ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:123: Define or directive not defined: '`WB_VEC_CNT'\nassign read_data_y[`WB_VEC_CNT] = cnt;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_wbt_entry.v:123: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign read_data_y[`WB_VEC_CNT] = cnt;\n                              ^\n%Error: Exiting due to 8 error(s)\n"
module aq_vidu_vid_wbt_entry(
  cpurst_b,
  create_clk,
  create_en_x,
  dp_wbt_bankx_dstv_type,
  read_data_y,
  rtu_vidu_flush_wbt,
  rtu_yy_xx_async_flush,
  wb_clk,
  wb_debug_x,
  wb_en_x
);


input          cpurst_b;              
input          create_clk;            
input          create_en_x;           
input          dp_wbt_bankx_dstv_type; 
input          rtu_vidu_flush_wbt;    
input          rtu_yy_xx_async_flush; 
input          wb_clk;                
input          wb_en_x;               
output  [2:0]  read_data_y;           
output         wb_debug_x;            


reg            cnt;                   
reg            inst_type;             
reg            wb;                    


wire           cnt_update_val;        
wire           cpurst_b;              
wire           create_clk;            
wire           create_en_x;           
wire           dp_wbt_bankx_dstv_type; 
wire    [2:0]  read_data_y;           
wire           rtu_vidu_flush_wbt;    
wire           rtu_yy_xx_async_flush; 
wire           wb_clk;                
wire           wb_debug_x;            
wire           wb_en_x;               








always @(posedge wb_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    wb <= 1'b1;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    wb <= 1'b1;
  else if(create_en_x)
    wb <= 1'b0;
  else if(wb_en_x && !cnt)
    wb <= 1'b1;
  else
    wb <= wb;
end

assign read_data_y[`WB_VEC_VLD] = wb || wb_en_x && !cnt;
assign wb_debug_x               = wb;




always @(posedge create_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    inst_type <= 1'b0;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    inst_type <= 1'b0;
  else if(create_en_x)
    inst_type <= dp_wbt_bankx_dstv_type;
  else
    inst_type <= inst_type;
end

assign read_data_y[`WB_VEC_TYPE] = inst_type;






always @(posedge wb_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cnt <= 1'b0;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    cnt <= 1'b0;
  else if(create_en_x || wb_en_x)
    cnt <= cnt_update_val;
  else
    cnt <= cnt;
end

assign cnt_update_val = !wb && !wb_en_x
                            && create_en_x
                            && (dp_wbt_bankx_dstv_type == `WB_VEC_TYPE_VLSU);

assign read_data_y[`WB_VEC_CNT] = cnt;










endmodule
module aq_vidu_vid_wbt_entry(
  cpurst_b,
  create_clk,
  create_en_x,
  dp_wbt_bankx_dstv_type,
  read_data_y,
  rtu_vidu_flush_wbt,
  rtu_yy_xx_async_flush,
  wb_clk,
  wb_debug_x,
  wb_en_x
);



input          cpurst_b;              
input          create_clk;            
input          create_en_x;           
input          dp_wbt_bankx_dstv_type; 
input          rtu_vidu_flush_wbt;    
input          rtu_yy_xx_async_flush; 
input          wb_clk;                
input          wb_en_x;               
output  [2:0]  read_data_y;           
output         wb_debug_x;            


reg            cnt;                   
reg            inst_type;             
reg            wb;                    


wire           cnt_update_val;        
wire           cpurst_b;              
wire           create_clk;            
wire           create_en_x;           
wire           dp_wbt_bankx_dstv_type; 
wire    [2:0]  read_data_y;           
wire           rtu_vidu_flush_wbt;    
wire           rtu_yy_xx_async_flush; 
wire           wb_clk;                
wire           wb_debug_x;            
wire           wb_en_x;               








always @(posedge wb_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    wb <= 1'b1;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    wb <= 1'b1;
  else if(create_en_x)
    wb <= 1'b0;
  else if(wb_en_x && !cnt)
    wb <= 1'b1;
  else
    wb <= wb;
end

assign read_data_y[`WB_VEC_VLD] = wb || wb_en_x && !cnt;
assign wb_debug_x               = wb;




always @(posedge create_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    inst_type <= 1'b0;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    inst_type <= 1'b0;
  else if(create_en_x)
    inst_type <= dp_wbt_bankx_dstv_type;
  else
    inst_type <= inst_type;
end

assign read_data_y[`WB_VEC_TYPE] = inst_type;






always @(posedge wb_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cnt <= 1'b0;
  else if(rtu_vidu_flush_wbt || rtu_yy_xx_async_flush)
    cnt <= 1'b0;
  else if(create_en_x || wb_en_x)
    cnt <= cnt_update_val;
  else
    cnt <= cnt;
end

assign cnt_update_val = !wb && !wb_en_x
                            && create_en_x
                            && (dp_wbt_bankx_dstv_type == `WB_VEC_TYPE_VLSU);

assign read_data_y[`WB_VEC_CNT] = cnt;










endmodule