data/full_repos/permissive/47037127/RevisionB/memscheduler.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:16: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'memscheduler\'\nmodule memscheduler(\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'OUT2\'\n OUT2\n ^~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:17: Unsupported: Interfaced port on top level module\n MEMADDR,\n ^~~~~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:18: Unsupported: Interfaced port on top level module\n MEMWRI);\n ^~~~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:13: Input/output/inout declaration not found for port: \'WAIT1\'\n WAIT1,\n ^~~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:14: Input/output/inout declaration not found for port: \'WAIT2\'\n WAIT2,\n ^~~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:15: Input/output/inout declaration not found for port: \'OUT1\'\n OUT1,\n ^~~~\n%Error: data/full_repos/permissive/47037127/RevisionB/memscheduler.v:16: Cannot find file containing interface: \'OUT2\'\n OUT2\n ^~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module memscheduler(
	clk,
	rst,
	addr1,
	addr2,
	write1,
	write2,
	dat1,
	dat2,
	memdat,
	WAIT1,
	WAIT2,
	OUT1,
	OUT2
	MEMADDR,
	MEMWRI);

input clk, rst;
input [31:0] addr1;
input [31:0] addr2;
input write1, write2;
input [15:0] dat1;
input [15:0] dat2;
input [15:0] memdat;

always@(posedge clk or posedge rst) begin
end

endmodule
module memscheduler(
	clk,
	rst,
	addr1,
	addr2,
	write1,
	write2,
	dat1,
	dat2,
	memdat,
	WAIT1,
	WAIT2,
	OUT1,
	OUT2
	MEMADDR,
	MEMWRI);


input clk, rst;
input [31:0] addr1;
input [31:0] addr2;
input write1, write2;
input [15:0] dat1;
input [15:0] dat2;
input [15:0] memdat;

always@(posedge clk or posedge rst) begin
end

endmodule