data/full_repos/permissive/520695407/src/lava-lamp.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/520695407/src/lava-lamp.sv:16: Operator ADD expects 33 bits on the RHS, but RHS\'s CONST \'12\'ha11\' generates 12 bits.\n                                                                        : ... In instance lava_lamp\n  always_ff @ (posedge clk) {mov_stb, cnt} <= cnt + 12\'ha11;\n                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520695407/src/lava-lamp.sv:24: Cannot find file containing module: \'metaball\'\n  metaball mb1(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/metaball\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/metaball.v\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/metaball.sv\n             metaball\n             metaball.v\n             metaball.sv\n             obj_dir/metaball\n             obj_dir/metaball.v\n             obj_dir/metaball.sv\n%Error: data/full_repos/permissive/520695407/src/lava-lamp.sv:37: Cannot find file containing module: \'metaball\'\n  metaball mb2(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520695407/src/lava-lamp.sv:59: Cannot find file containing module: \'buffer\'\n  buffer top_buff(\n  ^~~~~~\n%Error: data/full_repos/permissive/520695407/src/lava-lamp.sv:69: Cannot find file containing module: \'buffer\'\n  buffer btm_buff(\n  ^~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module lava_lamp #(
    parameter WIDTH = 32'h000f_8000,
    parameter HEIGHT = 32'h000f_c000
  )(
    input clk,
    input rst
  );



  logic [31:0] cnt = 0;
  logic mov_stb = 0;
  always_ff @ (posedge clk) {mov_stb, cnt} <= cnt + 12'ha11;
  
  logic px_stb = 1;

  logic [31:0] p_x, p_y;

  logic mb1_vld;
  logic [31:0] mb1_out;
  metaball mb1(
    .clk(clk),
    .rst(rst),
    .mov_en(mov_stb),
    .px_stb(px_stb),
    .p_x(p_x),
    .p_y(p_y),
    .vld(mb1_vld),
    .out(mb1_out)
  );

  logic mb2_vld;
  logic [31:0] mb2_out;
  metaball mb2(
    .clk(clk),
    .rst(rst),
    .mov_en(mov_stb),
    .px_stb(px_stb),
    .p_x(p_x),
    .p_y(p_y),
    .vld(mb2_vld),
    .out(mb2_out)
  );
  
  logic [31:0] sum;
  assign sum = mb1_out + mb2_out;

  logic	en       = 1,
	swap_en  = 0,
	w_en     = 0,
	w_mask   = 0;
  logic top_w_en = w_en & ~w_mask,
	btm_w_en = w_en & w_mask;
  logic [9:0]  addr = 0;
  logic [11:0] din, dout;
  buffer top_buff(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(top_w_en),
    .addr(addr),
    .din(din),
    .dout(dout)
  );
  
  buffer btm_buff(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(btm_w_en),
    .addr(addr),
    .din(din),
    .dout(dout)
  );

  always_ff @ (posedge clk) begin
    if (rst) begin
      p_x <= '0;
      p_y <= '0;
      px_stb <= 0;
      swap_en <= 0;
      w_en <= 0;
      w_mask <= 0;
      top_w_en <= 0;
      btm_w_en <= 0;
    end else begin
      if (mb1_vld & mb2_vld) begin


	if (p_x >= WIDTH) begin
	  p_x <= '0;
	  if (p_y >= HEIGHT) begin
	    p_y <= '0;
	    swap_en <= 1;
	  end else begin
	    p_y <= p_y + 32'h0000_8000;
	  end
	end else begin
	  p_x <= p_x + 32'h0000_8000;
	  swap_en <= 0;
	end
	px_stb <= 1;

	if (sum >= 32'h0000_8000) begin
	  w_en <= 1;
	  din <= '1;
	  if (addr == 1023) w_mask <= ~w_mask;
	  addr <= addr + 1;
	end
      end else begin


	px_stb <= 0;
	swap_en <= 0;
	w_en <= 0;
      end
    end
  end
endmodule
module lava_lamp #(
    parameter WIDTH = 32'h000f_8000,
    parameter HEIGHT = 32'h000f_c000
  )(
    input clk,
    input rst
  );




  logic [31:0] cnt = 0;
  logic mov_stb = 0;
  always_ff @ (posedge clk) {mov_stb, cnt} <= cnt + 12'ha11;
  
  logic px_stb = 1;

  logic [31:0] p_x, p_y;

  logic mb1_vld;
  logic [31:0] mb1_out;
  metaball mb1(
    .clk(clk),
    .rst(rst),
    .mov_en(mov_stb),
    .px_stb(px_stb),
    .p_x(p_x),
    .p_y(p_y),
    .vld(mb1_vld),
    .out(mb1_out)
  );

  logic mb2_vld;
  logic [31:0] mb2_out;
  metaball mb2(
    .clk(clk),
    .rst(rst),
    .mov_en(mov_stb),
    .px_stb(px_stb),
    .p_x(p_x),
    .p_y(p_y),
    .vld(mb2_vld),
    .out(mb2_out)
  );
  
  logic [31:0] sum;
  assign sum = mb1_out + mb2_out;

  logic	en       = 1,
	swap_en  = 0,
	w_en     = 0,
	w_mask   = 0;
  logic top_w_en = w_en & ~w_mask,
	btm_w_en = w_en & w_mask;
  logic [9:0]  addr = 0;
  logic [11:0] din, dout;
  buffer top_buff(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(top_w_en),
    .addr(addr),
    .din(din),
    .dout(dout)
  );
  
  buffer btm_buff(
    .clk(clk),
    .en(en),
    .swap_en(swap_en),
    .w_en(btm_w_en),
    .addr(addr),
    .din(din),
    .dout(dout)
  );

  always_ff @ (posedge clk) begin
    if (rst) begin
      p_x <= '0;
      p_y <= '0;
      px_stb <= 0;
      swap_en <= 0;
      w_en <= 0;
      w_mask <= 0;
      top_w_en <= 0;
      btm_w_en <= 0;
    end else begin
      if (mb1_vld & mb2_vld) begin


	if (p_x >= WIDTH) begin
	  p_x <= '0;
	  if (p_y >= HEIGHT) begin
	    p_y <= '0;
	    swap_en <= 1;
	  end else begin
	    p_y <= p_y + 32'h0000_8000;
	  end
	end else begin
	  p_x <= p_x + 32'h0000_8000;
	  swap_en <= 0;
	end
	px_stb <= 1;

	if (sum >= 32'h0000_8000) begin
	  w_en <= 1;
	  din <= '1;
	  if (addr == 1023) w_mask <= ~w_mask;
	  addr <= addr + 1;
	end
      end else begin


	px_stb <= 0;
	swap_en <= 0;
	w_en <= 0;
      end
    end
  end
endmodule