data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv:5: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl,data/full_repos/permissive/509468557/prim_assert.sv\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl,data/full_repos/permissive/509468557/prim_assert.sv.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim_xilinx/rtl,data/full_repos/permissive/509468557/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module prim_xilinx_flop_en #(
  parameter int               Width      = 1,
  parameter logic [Width-1:0] ResetValue = 0
) (
  input clk_i,
  input rst_ni,

  (* keep = "true" *) input en_i,
  input [Width-1:0] d_i,

  (* keep = "true" *) output logic [Width-1:0] q_o
);

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      q_o <= ResetValue;
    end else if (en_i) begin
      q_o <= d_i;
    end
  end

endmodule
module prim_xilinx_flop_en #(
  parameter int               Width      = 1,
  parameter logic [Width-1:0] ResetValue = 0
) (
  input clk_i,
  input rst_ni,

  (* keep = "true" *) input en_i,
  input [Width-1:0] d_i,

  (* keep = "true" *) output logic [Width-1:0] q_o
);


  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      q_o <= ResetValue;
    end else if (en_i) begin
      q_o <= d_i;
    end
  end

endmodule