data/full_repos/permissive/524567962/designs/Mod4Counter/Mod4_Counter.sv
data/verilator_xmls/b5c47d64-640b-43a7-b96f-a2feffde785b.xml
module Mod4_Counter(
  input  logic clk, reset,

  output logic [1:0] y
);

  logic clk2, fp2_q;
  flop fp1(.d(y[0]), .clk(clk), .reset(reset), .q(clk2), .qn(y[0]));
  flop fp2(.d(y[1]), .clk(clk2), .reset(reset), .q(fp2_q), .qn(y[1]));

endmodule
module Mod4_Counter(
  input  logic clk, reset,

  output logic [1:0] y
);


  logic clk2, fp2_q;
  flop fp1(.d(y[0]), .clk(clk), .reset(reset), .q(clk2), .qn(y[0]));
  flop fp2(.d(y[1]), .clk(clk2), .reset(reset), .q(fp2_q), .qn(y[1]));

endmodule