data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:9: Unsupported or unknown PLI call: $monitor\n  $monitor (\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 read = 0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 addr = addr + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #3 repeat (16) begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 addr = addr + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #3 repeat (16) begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ansiport_example();

reg read,write = 0;
reg [7:0] data_in  = 0;
reg [3:0] addr = 0;
wire [7:0] data_v95, data_notype, data_ansi;

initial begin
  $monitor (
  "%g rd=%b wr=%b addr=%b data_in=%h data_v95=%h data_notype=%h data_ansi=%h"
  , $time, read, write, addr, data_in, data_v95, data_notype, data_ansi);
  #1 read = 0;
  #3 repeat (16) begin
    data_in = $random;
    write = 1;
    #1 addr = addr + 1;
  end
  write = 0;
  addr = 0;
  #3 repeat (16) begin
    read = 1;
    #1 addr = addr + 1;
  end
  read = 0;
  #1 $finish;
end  

memory_v95         U (read, write, data_in, addr, data_v95);
memory_ansi_notype W (read, write, data_in, addr, data_notype);
memory_ansi        V (read, write, data_in, addr, data_ansi);

endmodule
module ansiport_example();


reg read,write = 0;
reg [7:0] data_in  = 0;
reg [3:0] addr = 0;
wire [7:0] data_v95, data_notype, data_ansi;

initial begin
  $monitor (
  "%g rd=%b wr=%b addr=%b data_in=%h data_v95=%h data_notype=%h data_ansi=%h"
  , $time, read, write, addr, data_in, data_v95, data_notype, data_ansi);
  #1 read = 0;
  #3 repeat (16) begin
    data_in = $random;
    write = 1;
    #1 addr = addr + 1;
  end
  write = 0;
  addr = 0;
  #3 repeat (16) begin
    read = 1;
    #1 addr = addr + 1;
  end
  read = 0;
  #1 $finish;
end  

memory_v95         U (read, write, data_in, addr, data_v95);
memory_ansi_notype W (read, write, data_in, addr, data_notype);
memory_ansi        V (read, write, data_in, addr, data_ansi);

endmodule