data/full_repos/permissive/522095295/decode.v
1: b'%Error: data/full_repos/permissive/522095295/decode.v:1: Cannot find include file: opcode.v\n`include "opcode.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/opcode.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/opcode.v.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/opcode.v.sv\n             opcode.v\n             opcode.v.v\n             opcode.v.sv\n             obj_dir/opcode.v\n             obj_dir/opcode.v.v\n             obj_dir/opcode.v.sv\n%Error: data/full_repos/permissive/522095295/decode.v:2: Cannot find include file: itype.v\n`include "itype.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:24: Define or directive not defined: \'`DECODE_R_TYPE\'\n      if (ir_i[6:0] == `DECODE_R_TYPE) begin\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (ir_i[6:0] == `DECODE_R_TYPE) begin\n                                     ^\n%Error: data/full_repos/permissive/522095295/decode.v:27: Define or directive not defined: \'`RTYPE\'\n         itype_o <= `RTYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n         itype_o <= `RTYPE;  \n                          ^\n%Error: data/full_repos/permissive/522095295/decode.v:29: Define or directive not defined: \'`DECODE_I_TYPE\'\n      else if (ir_i[6:0] == `DECODE_I_TYPE) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:32: syntax error, unexpected <=, expecting IDENTIFIER\n            rb_o <= {~20\'b0, ir_i[31:20]};\n                 ^~\n%Error: data/full_repos/permissive/522095295/decode.v:35: syntax error, unexpected <=, expecting IDENTIFIER\n            rb_o <= {20\'b0, ir_i[31:20]};\n                 ^~\n%Error: data/full_repos/permissive/522095295/decode.v:37: syntax error, unexpected <=, expecting IDENTIFIER\n         itype_o <= `ITYPE;  \n                 ^~\n%Error: data/full_repos/permissive/522095295/decode.v:37: Define or directive not defined: \'`ITYPE\'\n         itype_o <= `ITYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:39: Define or directive not defined: \'`DECODE_S_TYPE\'\n      else if (ir_i[6:0] == `DECODE_S_TYPE) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:48: Define or directive not defined: \'`STYPE\'\n         itype_o <= `STYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:50: Define or directive not defined: \'`DECODE_B_TYPE\'\n      else if (ir_i[6:0] == `DECODE_B_TYPE) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:54: syntax error, unexpected <=, expecting IDENTIFIER\n            pass_o <= {~21\'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1\'b0};\n                   ^~\n%Error: data/full_repos/permissive/522095295/decode.v:57: syntax error, unexpected <=, expecting IDENTIFIER\n            pass_o <= {21\'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1\'b0};\n                   ^~\n%Error: data/full_repos/permissive/522095295/decode.v:59: syntax error, unexpected <=, expecting IDENTIFIER\n         itype_o <= `BTYPE;  \n                 ^~\n%Error: data/full_repos/permissive/522095295/decode.v:59: Define or directive not defined: \'`BTYPE\'\n         itype_o <= `BTYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:61: Define or directive not defined: \'`DECODE_L_TYPE\'\n      else if (ir_i[6:0] == `DECODE_L_TYPE) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:69: Define or directive not defined: \'`LTYPE\'\n         itype_o <= `LTYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:71: Define or directive not defined: \'`DECODE_U_TYPE\'\n      else if (ir_i[6:0] == `DECODE_U_TYPE) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:73: Define or directive not defined: \'`UTYPE\'\n         itype_o <= `UTYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:75: Define or directive not defined: \'`JAL_OP\'\n      else if (ir_i[6:0] == `JAL_OP) begin\n                            ^~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:76: Define or directive not defined: \'`JTYPE\'\n         itype_o <= `JTYPE;  \n                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:78: Define or directive not defined: \'`JALR_OP\'\n      else if (ir_i[6:0] == `JALR_OP) begin\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/522095295/decode.v:80: Define or directive not defined: \'`JRTYPE\'\n         itype_o <= `JRTYPE;  \n                    ^~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module decode
(
   input wire clk,
   input wire reset,

   output reg [31:0] ra_o,
   output reg [31:0] rb_o,
   output reg [31:0] pass_o,

   input wire [2:0] stage_i,

   input wire [31:0] ir_i,

   output reg [4:0] itype_o,

   input wire [31:0] wd_i,
   input wire wd_q_i
);
   
   always @ (*) begin
      if (ir_i[6:0] == `DECODE_R_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         rb_o <= rfile[ir_i[24:20]];
         itype_o <= `RTYPE;
      end
      else if (ir_i[6:0] == `DECODE_I_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         if (ir_i[31] == 1) begin
            rb_o <= {~20'b0, ir_i[31:20]};
         end
         else begin
            rb_o <= {20'b0, ir_i[31:20]};
         end
         itype_o <= `ITYPE;
      end
      else if (ir_i[6:0] == `DECODE_S_TYPE) begin
         if (ir_i[31] == 1) begin
            ra_o <= {~20'b0, ir_i[31:25], ir_i[11:7]};
         end
         else begin
            ra_o <= {20'b0, ir_i[31:25], ir_i[11:7]};
         end
         rb_o <= rfile[ir_i[19:15]];
         pass_o <= rfile[ir_i[24:20]];
         itype_o <= `STYPE;
      end
      else if (ir_i[6:0] == `DECODE_B_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         rb_o <= rfile[ir_i[24:20]];
         if (ir_i[31] == 1) begin
            pass_o <= {~21'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
         end
         else begin
            pass_o <= {21'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
         end
         itype_o <= `BTYPE;
      end
      else if (ir_i[6:0] == `DECODE_L_TYPE) begin
         if (ir_i[31] == 1) begin
            ra_o <= {~20'b0, ir_i[31:20]};
         end
         else begin
            ra_o <= {20'b0, ir_i[31:20]};
         end
         rb_o <= rfile[ir_i[19:15]];
         itype_o <= `LTYPE;
     end
      else if (ir_i[6:0] == `DECODE_U_TYPE) begin
         ra_o <= ir_i[31:12];
         itype_o <= `UTYPE;
      end
      else if (ir_i[6:0] == `JAL_OP) begin
         itype_o <= `JTYPE;
      end
      else if (ir_i[6:0] == `JALR_OP) begin
         ra_o <= rfile[ir_i[19:15]];
         itype_o <= `JRTYPE;
      end
      else begin
         ra_o <= 0;
         rb_o <= 0;
         pass_o <= 0;
      end
   end

   always @ (rfile[31]) begin

      if (rfile[31] == 57005) begin
         if (rfile[30] == 0) begin
            $display("Test passed");
            $finish;
         end
         else begin
            $display("Test failed");

            $finish;
         end
      end
   end
  
   always @ (posedge wd_q_i) begin
      case (ir_i[11:7])
         'd0: r1 = r1;
         'd1: r1 = wd_i;
         'd2: r2 = wd_i;
         'd3: r3 = wd_i;
         'd4: r4 = wd_i;
         'd5: r5 = wd_i;
         'd6: r6 = wd_i;
         'd7: r7 = wd_i;
         'd8: r8 = wd_i;
         'd10: r10 = wd_i;
         'd11: r11 = wd_i;
         'd12: r12 = wd_i;
         'd13: r13 = wd_i;
         'd14: r14 = wd_i;
         'd15: r15 = wd_i;
         'd16: r16 = wd_i;
         'd17: r17 = wd_i;
         'd18: r18 = wd_i;
         'd19: r19 = wd_i;
         'd20: r20 = wd_i;
         'd21: r21 = wd_i;
         'd22: r22 = wd_i;
         'd23: r23 = wd_i;
         'd24: r24 = wd_i;
         'd25: r25 = wd_i;
         'd26: r26 = wd_i;
         'd27: r27 = wd_i;
         'd28: r28 = wd_i;
         'd29: r29 = wd_i;
         'd30: r30 = wd_i;
         'd31: r31 = wd_i;
      endcase
   end

   initial begin
      itype_o <= 5'b0;
   end


   wire [31:0] rfile [31:0];
   assign rfile[0] = 32'b0;
   assign rfile[1] = r1;
   assign rfile[2] = r2;
   assign rfile[3] = r3;
   assign rfile[4] = r4;
   assign rfile[5] = r5;
   assign rfile[6] = r6;
   assign rfile[7] = r7;
   assign rfile[8] = r8;
   assign rfile[9] = r9;
   assign rfile[10] = r10;
   assign rfile[11] = r11;
   assign rfile[12] = r12;
   assign rfile[13] = r13;
   assign rfile[14] = r14;
   assign rfile[15] = r15;
   assign rfile[16] = r16;
   assign rfile[17] = r17;
   assign rfile[18] = r18;
   assign rfile[19] = r19;
   assign rfile[20] = r20;
   assign rfile[21] = r21;
   assign rfile[22] = r22;
   assign rfile[23] = r23;
   assign rfile[24] = r24;
   assign rfile[25] = r25;
   assign rfile[26] = r26;
   assign rfile[27] = r27;
   assign rfile[28] = r28;
   assign rfile[29] = r29;
   assign rfile[30] = r30;
   assign rfile[31] = r31;


   wire [31:0] r0;
   reg [31:0] r1;
   reg [31:0] r2;
   reg [31:0] r3;
   reg [31:0] r4;
   reg [31:0] r5;
   reg [31:0] r6;
   reg [31:0] r7;
   reg [31:0] r8;
   reg [31:0] r9;
   reg [31:0] r10;
   reg [31:0] r11;
   reg [31:0] r12;
   reg [31:0] r13;
   reg [31:0] r14;
   reg [31:0] r15;
   reg [31:0] r16;
   reg [31:0] r17;
   reg [31:0] r18;
   reg [31:0] r19;
   reg [31:0] r20;
   reg [31:0] r21;
   reg [31:0] r22;
   reg [31:0] r23;
   reg [31:0] r24;
   reg [31:0] r25;
   reg [31:0] r26;
   reg [31:0] r27;
   reg [31:0] r28;
   reg [31:0] r29;
   reg [31:0] r30;
   reg [31:0] r31;
   
   assign r0 = 32'b0;   
 
   always @ (negedge reset) begin
      r1  <= 32'b0;
      r2  <= 'h1F400;
      r3  <= 32'b0;
      r4  <= 32'b0;
      r5  <= 32'b0;
      r6  <= 32'b0;
      r7  <= 32'b0;
      r8  <= 32'b0;
      r9  <= 32'b0;
      r10 <= 32'b0;
      r11 <= 32'b0;
      r12 <= 32'b0;
      r13 <= 32'b0;
      r14 <= 32'b0;
      r15 <= 32'b0;
      r16 <= 32'b0;
      r17 <= 32'b0;
      r18 <= 32'b0;
      r19 <= 32'b0;
      r20 <= 32'b0;
      r21 <= 32'b0;
      r22 <= 32'b0;
      r23 <= 32'b0;
      r24 <= 32'b0;
      r25 <= 32'b0;
      r26 <= 32'b0;
      r27 <= 32'b0;
      r28 <= 32'b0;
      r29 <= 32'b0;
      r30 <= 32'b0;
      r31 <= 32'b0;
   end   
endmodule
module decode
(
   input wire clk,
   input wire reset,

   output reg [31:0] ra_o,
   output reg [31:0] rb_o,
   output reg [31:0] pass_o,

   input wire [2:0] stage_i,

   input wire [31:0] ir_i,

   output reg [4:0] itype_o,

   input wire [31:0] wd_i,
   input wire wd_q_i
);

   
   always @ (*) begin
      if (ir_i[6:0] == `DECODE_R_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         rb_o <= rfile[ir_i[24:20]];
         itype_o <= `RTYPE;
      end
      else if (ir_i[6:0] == `DECODE_I_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         if (ir_i[31] == 1) begin
            rb_o <= {~20'b0, ir_i[31:20]};
         end
         else begin
            rb_o <= {20'b0, ir_i[31:20]};
         end
         itype_o <= `ITYPE;
      end
      else if (ir_i[6:0] == `DECODE_S_TYPE) begin
         if (ir_i[31] == 1) begin
            ra_o <= {~20'b0, ir_i[31:25], ir_i[11:7]};
         end
         else begin
            ra_o <= {20'b0, ir_i[31:25], ir_i[11:7]};
         end
         rb_o <= rfile[ir_i[19:15]];
         pass_o <= rfile[ir_i[24:20]];
         itype_o <= `STYPE;
      end
      else if (ir_i[6:0] == `DECODE_B_TYPE) begin
         ra_o <= rfile[ir_i[19:15]];
         rb_o <= rfile[ir_i[24:20]];
         if (ir_i[31] == 1) begin
            pass_o <= {~21'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
         end
         else begin
            pass_o <= {21'b0, ir_i[7], ir_i[30:25], ir_i[11:8], 1'b0};
         end
         itype_o <= `BTYPE;
      end
      else if (ir_i[6:0] == `DECODE_L_TYPE) begin
         if (ir_i[31] == 1) begin
            ra_o <= {~20'b0, ir_i[31:20]};
         end
         else begin
            ra_o <= {20'b0, ir_i[31:20]};
         end
         rb_o <= rfile[ir_i[19:15]];
         itype_o <= `LTYPE;
     end
      else if (ir_i[6:0] == `DECODE_U_TYPE) begin
         ra_o <= ir_i[31:12];
         itype_o <= `UTYPE;
      end
      else if (ir_i[6:0] == `JAL_OP) begin
         itype_o <= `JTYPE;
      end
      else if (ir_i[6:0] == `JALR_OP) begin
         ra_o <= rfile[ir_i[19:15]];
         itype_o <= `JRTYPE;
      end
      else begin
         ra_o <= 0;
         rb_o <= 0;
         pass_o <= 0;
      end
   end

   always @ (rfile[31]) begin

      if (rfile[31] == 57005) begin
         if (rfile[30] == 0) begin
            $display("Test passed");
            $finish;
         end
         else begin
            $display("Test failed");

            $finish;
         end
      end
   end
  
   always @ (posedge wd_q_i) begin
      case (ir_i[11:7])
         'd0: r1 = r1;
         'd1: r1 = wd_i;
         'd2: r2 = wd_i;
         'd3: r3 = wd_i;
         'd4: r4 = wd_i;
         'd5: r5 = wd_i;
         'd6: r6 = wd_i;
         'd7: r7 = wd_i;
         'd8: r8 = wd_i;
         'd10: r10 = wd_i;
         'd11: r11 = wd_i;
         'd12: r12 = wd_i;
         'd13: r13 = wd_i;
         'd14: r14 = wd_i;
         'd15: r15 = wd_i;
         'd16: r16 = wd_i;
         'd17: r17 = wd_i;
         'd18: r18 = wd_i;
         'd19: r19 = wd_i;
         'd20: r20 = wd_i;
         'd21: r21 = wd_i;
         'd22: r22 = wd_i;
         'd23: r23 = wd_i;
         'd24: r24 = wd_i;
         'd25: r25 = wd_i;
         'd26: r26 = wd_i;
         'd27: r27 = wd_i;
         'd28: r28 = wd_i;
         'd29: r29 = wd_i;
         'd30: r30 = wd_i;
         'd31: r31 = wd_i;
      endcase
   end

   initial begin
      itype_o <= 5'b0;
   end


   wire [31:0] rfile [31:0];
   assign rfile[0] = 32'b0;
   assign rfile[1] = r1;
   assign rfile[2] = r2;
   assign rfile[3] = r3;
   assign rfile[4] = r4;
   assign rfile[5] = r5;
   assign rfile[6] = r6;
   assign rfile[7] = r7;
   assign rfile[8] = r8;
   assign rfile[9] = r9;
   assign rfile[10] = r10;
   assign rfile[11] = r11;
   assign rfile[12] = r12;
   assign rfile[13] = r13;
   assign rfile[14] = r14;
   assign rfile[15] = r15;
   assign rfile[16] = r16;
   assign rfile[17] = r17;
   assign rfile[18] = r18;
   assign rfile[19] = r19;
   assign rfile[20] = r20;
   assign rfile[21] = r21;
   assign rfile[22] = r22;
   assign rfile[23] = r23;
   assign rfile[24] = r24;
   assign rfile[25] = r25;
   assign rfile[26] = r26;
   assign rfile[27] = r27;
   assign rfile[28] = r28;
   assign rfile[29] = r29;
   assign rfile[30] = r30;
   assign rfile[31] = r31;


   wire [31:0] r0;
   reg [31:0] r1;
   reg [31:0] r2;
   reg [31:0] r3;
   reg [31:0] r4;
   reg [31:0] r5;
   reg [31:0] r6;
   reg [31:0] r7;
   reg [31:0] r8;
   reg [31:0] r9;
   reg [31:0] r10;
   reg [31:0] r11;
   reg [31:0] r12;
   reg [31:0] r13;
   reg [31:0] r14;
   reg [31:0] r15;
   reg [31:0] r16;
   reg [31:0] r17;
   reg [31:0] r18;
   reg [31:0] r19;
   reg [31:0] r20;
   reg [31:0] r21;
   reg [31:0] r22;
   reg [31:0] r23;
   reg [31:0] r24;
   reg [31:0] r25;
   reg [31:0] r26;
   reg [31:0] r27;
   reg [31:0] r28;
   reg [31:0] r29;
   reg [31:0] r30;
   reg [31:0] r31;
   
   assign r0 = 32'b0;   
 
   always @ (negedge reset) begin
      r1  <= 32'b0;
      r2  <= 'h1F400;
      r3  <= 32'b0;
      r4  <= 32'b0;
      r5  <= 32'b0;
      r6  <= 32'b0;
      r7  <= 32'b0;
      r8  <= 32'b0;
      r9  <= 32'b0;
      r10 <= 32'b0;
      r11 <= 32'b0;
      r12 <= 32'b0;
      r13 <= 32'b0;
      r14 <= 32'b0;
      r15 <= 32'b0;
      r16 <= 32'b0;
      r17 <= 32'b0;
      r18 <= 32'b0;
      r19 <= 32'b0;
      r20 <= 32'b0;
      r21 <= 32'b0;
      r22 <= 32'b0;
      r23 <= 32'b0;
      r24 <= 32'b0;
      r25 <= 32'b0;
      r26 <= 32'b0;
      r27 <= 32'b0;
      r28 <= 32'b0;
      r29 <= 32'b0;
      r30 <= 32'b0;
      r31 <= 32'b0;
   end   
endmodule