data/full_repos/permissive/469129654/src/xnor_primitive_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469129654/src/xnor_primitive_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b0; b=1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/xnor_primitive_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/xnor_primitive_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #50 a=1\'b1; b=1\'b1;  \n        ^\n%Error: data/full_repos/permissive/469129654/src/xnor_primitive_testbench.v:5: Cannot find file containing module: \'xnor_primitive\'\n    xnor_primitive xnor_instance0(a, b, out);\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/xnor_primitive\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/xnor_primitive.v\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/xnor_primitive.sv\n             xnor_primitive\n             xnor_primitive.v\n             xnor_primitive.sv\n             obj_dir/xnor_primitive\n             obj_dir/xnor_primitive.v\n             obj_dir/xnor_primitive.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xnor_primitive_testbench;
    reg a, b;
    wire out;

    xnor_primitive xnor_instance0(a, b, out);

    initial begin
            a=1'b0; b=1'b0;
        #50 a=1'b0; b=1'b1;
        #50 a=1'b1; b=1'b0;
        #50 a=1'b1; b=1'b1;
    end

endmodule
module xnor_primitive_testbench;

    reg a, b;
    wire out;

    xnor_primitive xnor_instance0(a, b, out);

    initial begin
            a=1'b0; b=1'b0;
        #50 a=1'b0; b=1'b1;
        #50 a=1'b1; b=1'b0;
        #50 a=1'b1; b=1'b1;
    end

endmodule