data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Adder100i/top_module.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Adder100i,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Adder100i/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module add1 (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);

  assign {cout, sum} = a + b + cin;
endmodule
module add1 (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);


  assign {cout, sum} = a + b + cin;
endmodule