data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v
1: b'%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v:27: Cannot find include file: sd_defines.h\n`include "sd_defines.h" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.v\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.sv\n             sd_defines.h\n             sd_defines.h.v\n             sd_defines.h.sv\n             obj_dir/sd_defines.h\n             obj_dir/sd_defines.h.v\n             obj_dir/sd_defines.h.sv\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v:35: Define or directive not defined: \'`INT_CMD_SIZE\'\n    input [`INT_CMD_SIZE-1:0] cmd_int_status_i,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v:66: Define or directive not defined: \'`INT_CMD_CC\'\n                if (cmd_int_status_i[`INT_CMD_CC]) state <= TRIGGER_XFER;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                if (cmd_int_status_i[`INT_CMD_CC]) state <= TRIGGER_XFER;\n                                                ^\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_xfer_trig.v:67: Define or directive not defined: \'`INT_CMD_EI\'\n                else if (cmd_int_status_i[`INT_CMD_EI]) state <= IDLE;\n                                          ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module sd_data_xfer_trig (
    input clock,
    input clock_posedge,
    input rst,
    input cmd_with_data_start_i,
    input r_w_i,
    input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
    output reg start_tx_o,
    output reg start_rx_o
);

reg r_w_reg;
parameter SIZE = 2;
reg [SIZE-1:0] state;
parameter IDLE             = 2'b00;
parameter WAIT_FOR_CMD_INT = 2'b01;
parameter TRIGGER_XFER     = 2'b10;

always @(posedge clock) begin
    if (rst) begin
        start_tx_o <= 0;
        start_rx_o <= 0;
        r_w_reg <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
                r_w_reg <= r_w_i;
                if (cmd_with_data_start_i) begin
                    state <= r_w_i ? TRIGGER_XFER : WAIT_FOR_CMD_INT;
                end
            end
            WAIT_FOR_CMD_INT: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
                if (cmd_int_status_i[`INT_CMD_CC]) state <= TRIGGER_XFER;
                else if (cmd_int_status_i[`INT_CMD_EI]) state <= IDLE;
            end
            TRIGGER_XFER: begin
                start_tx_o <= ~r_w_reg;
                start_rx_o <= r_w_reg;
                state <= IDLE;
            end
        endcase
    end
end

endmodule
module sd_data_xfer_trig (
    input clock,
    input clock_posedge,
    input rst,
    input cmd_with_data_start_i,
    input r_w_i,
    input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
    output reg start_tx_o,
    output reg start_rx_o
);


reg r_w_reg;
parameter SIZE = 2;
reg [SIZE-1:0] state;
parameter IDLE             = 2'b00;
parameter WAIT_FOR_CMD_INT = 2'b01;
parameter TRIGGER_XFER     = 2'b10;

always @(posedge clock) begin
    if (rst) begin
        start_tx_o <= 0;
        start_rx_o <= 0;
        r_w_reg <= 0;
        state <= IDLE;
    end else if (clock_posedge) begin
        case (state)
            IDLE: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
                r_w_reg <= r_w_i;
                if (cmd_with_data_start_i) begin
                    state <= r_w_i ? TRIGGER_XFER : WAIT_FOR_CMD_INT;
                end
            end
            WAIT_FOR_CMD_INT: begin
                start_tx_o <= 0;
                start_rx_o <= 0;
                if (cmd_int_status_i[`INT_CMD_CC]) state <= TRIGGER_XFER;
                else if (cmd_int_status_i[`INT_CMD_EI]) state <= IDLE;
            end
            TRIGGER_XFER: begin
                start_tx_o <= ~r_w_reg;
                start_rx_o <= r_w_reg;
                state <= IDLE;
            end
        endcase
    end
end

endmodule