data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v
1: b'%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:17: Cannot find include file: Interface0_defs.v\n`include "Interface0_defs.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v.v\n             data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64,data/full_repos/permissive/477403084/Interface0_defs.v.sv\n             Interface0_defs.v\n             Interface0_defs.v.v\n             Interface0_defs.v.sv\n             obj_dir/Interface0_defs.v\n             obj_dir/Interface0_defs.v.v\n             obj_dir/Interface0_defs.v.sv\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:158: Unsupported or unknown PLI call: $monitor\n  $monitor("t=%3d ZX CK=%b; M1=%b; MREQ=%b; IORQ=%b; RD=%b; WR=%b; ADDR=%b; DATA=%b; WAIT=%b; RESET=%b; ROMCS=%b, setZxData=%b",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:163: Unsupported or unknown PLI call: $monitor\n  $monitor("t=%3d IO_CK=%b; IO=%b; MOSI=%b; MISO=%b; misoIoBit=%b",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:199: Define or directive not defined: \'`bZX_CMD\'\n        if (ZX_ADDR == `bZX_CMD) begin\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:199: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (ZX_ADDR == `bZX_CMD) begin\n                               ^\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:212: syntax error, unexpected <=, expecting IDENTIFIER\n  piClkOld <= PI_IO_CLK;\n           ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:216: syntax error, unexpected <=, expecting IDENTIFIER\n      pi_data <= {pi_data[12:0], PI_IO};\n              ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:219: syntax error, unexpected <=, expecting IDENTIFIER\n      bitsCounter <= bitsCounter - 1;\n                  ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:223: syntax error, unexpected <=, expecting IDENTIFIER\n        miso <= 0;\n             ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:225: syntax error, unexpected <=, expecting IDENTIFIER\n          waitData <= 0;\n                   ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:233: syntax error, unexpected <=, expecting IDENTIFIER\n  mosiOld <= PI_MOSI;\n          ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:236: syntax error, unexpected <=, expecting IDENTIFIER\n    bitsCounter <= 0;\n                ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:238: syntax error, unexpected <=, expecting IDENTIFIER\n    waitReply <= 1\'b0;\n              ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:240: Define or directive not defined: \'`CMDS\'\n      if (~|(pi_data[3:0] & `CMDS)) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:240: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (~|(pi_data[3:0] & `CMDS)) begin\n                                 ^\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:241: Define or directive not defined: \'`ROMCS_CMD\'\n        romcs <= |(pi_data[3:0] & `ROMCS_CMD);\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:242: Define or directive not defined: \'`RESET_CMD\'\n        reset <= (|(pi_data[3:0] & `RESET_CMD)) ? `RESET_COUNT : 3\'d0;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:242: Define or directive not defined: \'`RESET_COUNT\'\n        reset <= (|(pi_data[3:0] & `RESET_CMD)) ? `RESET_COUNT : 3\'d0;\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:243: Define or directive not defined: \'`NMI_CMD\'\n        nmi <= |(pi_data[3:0] & `NMI_CMD);\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:247: syntax error, unexpected <=, expecting IDENTIFIER\n        ZX_DATA_reg <= pi_data[7:0];\n                    ^~\n%Error: data/full_repos/permissive/477403084/hardware/XC9572XL-VQ64/Interface0.v:252: syntax error, unexpected end\n  end  \n  ^~~\n%Error: Cannot continue\n'
module Interface0(
    input ZX_CLK,

    input ZX_M1,
    input ZX_MREQ,

    input ZX_IORQ,

    input ZX_RD,

    input ZX_WR,

    input [15:0] ZX_ADDR,
    inout [7:0] ZX_DATA,

    output ZX_INT,

    output ZX_NMI,

    output ZX_WAIT,

    output ZX_RESET,

    output ZX_BUSRQ,

    input ZX_BUSACK,


    output ZX_ROMCS,


    output ZX_ROMCS1,
    output ZX_ROMCS2,


    input ZX_DRD,
    input ZX_DWR,
    input ZX_MTR,



    input PI_MASTER_CLK,
    input PI_IO_CLK,
    inout PI_IO,
    input PI_MOSI,
    output PI_MISO,


    inout PI_GPIO1,
    inout PI_GPIO2,
    inout PI_GPIO3,
    inout PI_GPIO4,
    inout PI_GPIO5
    );

reg [7:0] ZX_DATA_reg = 8'd0;
reg setZxData         = 1'b0;

reg [13:0] pi_data    = 14'd0;
reg [4:0] bitsCounter = 5'd0;
reg [2:0] reset       = 3'd0;

reg piClk = 1'b0, piClkOld = 1'b0;
reg zxClk = 1'b0, zxClkOld = 1'b0;
reg m1    = 1'b0, m1Old    = 1'b0;
reg mosi  = 1'b0, mosiOld  = 1'b0;
reg miso  = 1'b0;

reg waitData  = 1'b0;
reg waitReply = 1'b0;
reg romcs     = 1'b0;
reg nmi       = 1'b0;
reg misoIoBit = 1'b0;

initial begin
  $monitor("t=%3d ZX CK=%b; M1=%b; MREQ=%b; IORQ=%b; RD=%b; WR=%b; ADDR=%b; DATA=%b; WAIT=%b; RESET=%b; ROMCS=%b, setZxData=%b",
            $time, ZX_CLK, ZX_M1, ZX_MREQ, ZX_IORQ, ZX_RD, ZX_WR, ZX_ADDR, ZX_DATA, ZX_WAIT, ZX_RESET, ZX_ROMCS, setZxData);



  $monitor("t=%3d IO_CK=%b; IO=%b; MOSI=%b; MISO=%b; misoIoBit=%b",
            $time, PI_IO_CLK, PI_IO, PI_MOSI, PI_MISO, misoIoBit);
end

assign ZX_ROMCS = ~|romcs;
assign ZX_WAIT  = ~|waitData;
assign ZX_RESET = ~|reset;
assign ZX_NMI   = ~|nmi;
assign ZX_DATA  = (!ZX_RD && setZxData) ? ZX_DATA_reg : 8'bZZZZZZZZ;

assign PI_MISO = miso;
assign PI_IO   = !PI_MOSI ? misoIoBit : 1'bz;

always @(posedge PI_MASTER_CLK) begin
  zxClkOld <= ZX_CLK;
  zxClk <= zxClkOld;
  if (zxClk == 1'b0 && zxClkOld == 1'b1) begin
    if (nmi) begin
      m1Old <= ZX_M1;
      m1 <= m1Old;
      if (m1 == 0 && m1Old == 1) nmi <= 0;
    end

    if (setZxData && ZX_RD) setZxData <= 0;
    if (|reset) reset <= reset - 1;

    if (!waitData && !setZxData) begin
      if (!ZX_ROMCS && !ZX_MREQ && !ZX_RD && ZX_ADDR[15:14] == 2'b00) begin
        bitsCounter <= 5'd13;
        waitData <= 1;
        pi_data <= ZX_ADDR[13:0];
        miso <= 1;
        waitReply <= 1'b1;
      end

      if (!ZX_IORQ && (!ZX_RD || !ZX_WR)) begin
        if (ZX_ADDR == `bZX_CMD) begin
          pi_data[13:5] <= {!ZX_RD, ZX_DATA};
          waitData <= !ZX_RD;
          waitReply <= !ZX_WR;
          bitsCounter <= 5'd9;
          miso <= 1;
        end
      end
    end
  end



  piClkOld <= PI_IO_CLK;
  piClk <= piClkOld;
  if (piClk == 1'b0 && piClkOld == 1'b1) begin
    if (PI_MOSI) begin
      pi_data <= {pi_data[12:0], PI_IO};
      bitsCounter <= bitsCounter + 1;
    end else begin
      bitsCounter <= bitsCounter - 1;
      misoIoBit <= pi_data[13];
      pi_data <= {pi_data[12:0], 1'b0};
      if (~|bitsCounter) begin
        miso <= 0;
        if (!waitReply) begin
          waitData <= 0;
        end
      end
    end
  end



  mosiOld <= PI_MOSI;
  mosi <= mosiOld;
  if (mosi == 1'b0 && mosiOld == 1'b1) begin
    bitsCounter <= 0;
  end else if (mosi == 1'b1 && mosiOld == 1'b0) begin
    waitReply <= 1'b0;
    if (bitsCounter == 5'd4) begin
      if (~|(pi_data[3:0] & `CMDS)) begin
        romcs <= |(pi_data[3:0] & `ROMCS_CMD);
        reset <= (|(pi_data[3:0] & `RESET_CMD)) ? `RESET_COUNT : 3'd0;
        nmi <= |(pi_data[3:0] & `NMI_CMD);
      end
    end else begin
      if (waitData && bitsCounter == 5'd8) begin
        ZX_DATA_reg <= pi_data[7:0];
        setZxData <= 1;
        waitData <= 0;
      end
    end
  end
end

endmodule
module Interface0(
    input ZX_CLK,

    input ZX_M1,
    input ZX_MREQ,

    input ZX_IORQ,

    input ZX_RD,

    input ZX_WR,

    input [15:0] ZX_ADDR,
    inout [7:0] ZX_DATA,

    output ZX_INT,

    output ZX_NMI,

    output ZX_WAIT,

    output ZX_RESET,

    output ZX_BUSRQ,

    input ZX_BUSACK,


    output ZX_ROMCS,


    output ZX_ROMCS1,
    output ZX_ROMCS2,


    input ZX_DRD,
    input ZX_DWR,
    input ZX_MTR,



    input PI_MASTER_CLK,
    input PI_IO_CLK,
    inout PI_IO,
    input PI_MOSI,
    output PI_MISO,


    inout PI_GPIO1,
    inout PI_GPIO2,
    inout PI_GPIO3,
    inout PI_GPIO4,
    inout PI_GPIO5
    );


reg [7:0] ZX_DATA_reg = 8'd0;
reg setZxData         = 1'b0;

reg [13:0] pi_data    = 14'd0;
reg [4:0] bitsCounter = 5'd0;
reg [2:0] reset       = 3'd0;

reg piClk = 1'b0, piClkOld = 1'b0;
reg zxClk = 1'b0, zxClkOld = 1'b0;
reg m1    = 1'b0, m1Old    = 1'b0;
reg mosi  = 1'b0, mosiOld  = 1'b0;
reg miso  = 1'b0;

reg waitData  = 1'b0;
reg waitReply = 1'b0;
reg romcs     = 1'b0;
reg nmi       = 1'b0;
reg misoIoBit = 1'b0;

initial begin
  $monitor("t=%3d ZX CK=%b; M1=%b; MREQ=%b; IORQ=%b; RD=%b; WR=%b; ADDR=%b; DATA=%b; WAIT=%b; RESET=%b; ROMCS=%b, setZxData=%b",
            $time, ZX_CLK, ZX_M1, ZX_MREQ, ZX_IORQ, ZX_RD, ZX_WR, ZX_ADDR, ZX_DATA, ZX_WAIT, ZX_RESET, ZX_ROMCS, setZxData);



  $monitor("t=%3d IO_CK=%b; IO=%b; MOSI=%b; MISO=%b; misoIoBit=%b",
            $time, PI_IO_CLK, PI_IO, PI_MOSI, PI_MISO, misoIoBit);
end

assign ZX_ROMCS = ~|romcs;
assign ZX_WAIT  = ~|waitData;
assign ZX_RESET = ~|reset;
assign ZX_NMI   = ~|nmi;
assign ZX_DATA  = (!ZX_RD && setZxData) ? ZX_DATA_reg : 8'bZZZZZZZZ;

assign PI_MISO = miso;
assign PI_IO   = !PI_MOSI ? misoIoBit : 1'bz;

always @(posedge PI_MASTER_CLK) begin
  zxClkOld <= ZX_CLK;
  zxClk <= zxClkOld;
  if (zxClk == 1'b0 && zxClkOld == 1'b1) begin
    if (nmi) begin
      m1Old <= ZX_M1;
      m1 <= m1Old;
      if (m1 == 0 && m1Old == 1) nmi <= 0;
    end

    if (setZxData && ZX_RD) setZxData <= 0;
    if (|reset) reset <= reset - 1;

    if (!waitData && !setZxData) begin
      if (!ZX_ROMCS && !ZX_MREQ && !ZX_RD && ZX_ADDR[15:14] == 2'b00) begin
        bitsCounter <= 5'd13;
        waitData <= 1;
        pi_data <= ZX_ADDR[13:0];
        miso <= 1;
        waitReply <= 1'b1;
      end

      if (!ZX_IORQ && (!ZX_RD || !ZX_WR)) begin
        if (ZX_ADDR == `bZX_CMD) begin
          pi_data[13:5] <= {!ZX_RD, ZX_DATA};
          waitData <= !ZX_RD;
          waitReply <= !ZX_WR;
          bitsCounter <= 5'd9;
          miso <= 1;
        end
      end
    end
  end



  piClkOld <= PI_IO_CLK;
  piClk <= piClkOld;
  if (piClk == 1'b0 && piClkOld == 1'b1) begin
    if (PI_MOSI) begin
      pi_data <= {pi_data[12:0], PI_IO};
      bitsCounter <= bitsCounter + 1;
    end else begin
      bitsCounter <= bitsCounter - 1;
      misoIoBit <= pi_data[13];
      pi_data <= {pi_data[12:0], 1'b0};
      if (~|bitsCounter) begin
        miso <= 0;
        if (!waitReply) begin
          waitData <= 0;
        end
      end
    end
  end



  mosiOld <= PI_MOSI;
  mosi <= mosiOld;
  if (mosi == 1'b0 && mosiOld == 1'b1) begin
    bitsCounter <= 0;
  end else if (mosi == 1'b1 && mosiOld == 1'b0) begin
    waitReply <= 1'b0;
    if (bitsCounter == 5'd4) begin
      if (~|(pi_data[3:0] & `CMDS)) begin
        romcs <= |(pi_data[3:0] & `ROMCS_CMD);
        reset <= (|(pi_data[3:0] & `RESET_CMD)) ? `RESET_COUNT : 3'd0;
        nmi <= |(pi_data[3:0] & `NMI_CMD);
      end
    end else begin
      if (waitData && bitsCounter == 5'd8) begin
        ZX_DATA_reg <= pi_data[7:0];
        setZxData <= 1;
        waitData <= 0;
      end
    end
  end
end

endmodule