data/full_repos/permissive/523038000/MIPS/add.v
data/verilator_xmls/e043db5e-23e2-47b0-a107-113da5ba0545.xml
module add (out,a,b);
output [31:0] out;
input [31:0] a,b;

assign out=a+b;
endmodule
module add (out,a,b);

output [31:0] out;
input [31:0] a,b;

assign out=a+b;
endmodule