data/full_repos/permissive/487568919/basic_verilog/pos2bin.sv
data/verilator_xmls/50944c6f-9cd2-4e80-a5bc-7695e261f6f1.xml
module pos2bin #( parameter
  BIN_WIDTH = 8,
  POS_WIDTH = 2**BIN_WIDTH
)(
  input [(POS_WIDTH-1):0] pos,
  output logic [(BIN_WIDTH-1):0] bin,


  output logic err_no_hot,
  output logic err_multi_hot

);


assign err_no_hot = (pos[(POS_WIDTH-1):0] == 0);

integer i;

logic found_hot;
always_comb begin
  err_multi_hot = 0;
  bin[(BIN_WIDTH-1):0] = 0;
  found_hot = 0;
  for (i=0; i<POS_WIDTH; i++) begin

    if ( ~found_hot && pos[i] ) begin
      bin[(BIN_WIDTH-1):0] = i[(BIN_WIDTH-1):0];
    end

    if ( found_hot && pos[i] ) begin
      err_multi_hot=1'b1;
    end

    if ( pos[i] ) begin
      found_hot = 1'b1;
    end

  end
end

endmodule
module pos2bin #( parameter
  BIN_WIDTH = 8,
  POS_WIDTH = 2**BIN_WIDTH
)(
  input [(POS_WIDTH-1):0] pos,
  output logic [(BIN_WIDTH-1):0] bin,


  output logic err_no_hot,
  output logic err_multi_hot

);



assign err_no_hot = (pos[(POS_WIDTH-1):0] == 0);

integer i;

logic found_hot;
always_comb begin
  err_multi_hot = 0;
  bin[(BIN_WIDTH-1):0] = 0;
  found_hot = 0;
  for (i=0; i<POS_WIDTH; i++) begin

    if ( ~found_hot && pos[i] ) begin
      bin[(BIN_WIDTH-1):0] = i[(BIN_WIDTH-1):0];
    end

    if ( found_hot && pos[i] ) begin
      err_multi_hot=1'b1;
    end

    if ( pos[i] ) begin
      found_hot = 1'b1;
    end

  end
end

endmodule