data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen/gen_padder.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen/gen_padder.v:23: Cannot find file containing module: 'gen_adder'\n gen_adder #(.IN_WIDTH(OUT_WIDTH)) ADD0 (.a(PADDER_OUT) , .b(step_correction), .s(adder_out));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen,data/full_repos/permissive/503053625/gen_adder\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen,data/full_repos/permissive/503053625/gen_adder.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/gen,data/full_repos/permissive/503053625/gen_adder.sv\n             gen_adder\n             gen_adder.v\n             gen_adder.sv\n             obj_dir/gen_adder\n             obj_dir/gen_adder.v\n             obj_dir/gen_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module gen_padder
#(
	parameter IN_WIDTH = 12,
	parameter OUT_WIDTH = 64,
	parameter L_PAD_WIDTH = 4,
	parameter R_PAD_WIDTH = 48
)
(
	input wire [IN_WIDTH - 1:0] in,
	output wire [OUT_WIDTH - 1:0] out
);



	wire [OUT_WIDTH - 1:0] PADDER_OUT;
	wire [OUT_WIDTH : 0] adder_out;


	reg [OUT_WIDTH - 1:0] step_correction = 64'h0000_0000_0000_0000;

	assign PADDER_OUT = {{4{in [IN_WIDTH - 1]}}, in, {R_PAD_WIDTH{1'b0}}};
	
	gen_adder #(.IN_WIDTH(OUT_WIDTH)) ADD0 (.a(PADDER_OUT) , .b(step_correction), .s(adder_out));

	assign out = adder_out[OUT_WIDTH -1 : 0];
	












endmodule
module gen_padder
#(
	parameter IN_WIDTH = 12,
	parameter OUT_WIDTH = 64,
	parameter L_PAD_WIDTH = 4,
	parameter R_PAD_WIDTH = 48
)
(
	input wire [IN_WIDTH - 1:0] in,
	output wire [OUT_WIDTH - 1:0] out
);




	wire [OUT_WIDTH - 1:0] PADDER_OUT;
	wire [OUT_WIDTH : 0] adder_out;


	reg [OUT_WIDTH - 1:0] step_correction = 64'h0000_0000_0000_0000;

	assign PADDER_OUT = {{4{in [IN_WIDTH - 1]}}, in, {R_PAD_WIDTH{1'b0}}};
	
	gen_adder #(.IN_WIDTH(OUT_WIDTH)) ADD0 (.a(PADDER_OUT) , .b(step_correction), .s(adder_out));

	assign out = adder_out[OUT_WIDTH -1 : 0];
	












endmodule