data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v
1: b"%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:52: Cannot find file containing module: 'control_unit'\n    control_unit con(.func(inst[5:0]),.op(inst[31:26]),.zero(zero),.sign(sign),.OF(OF_dff[0]),.CF(CF),.PF(PF),.pcwre(pcwre),.alusrca(alusrca),.alusrcb(alusrcb),\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527597746/CPU.srcs/sources_1/new,data/full_repos/permissive/527597746/control_unit\n             data/full_repos/permissive/527597746/CPU.srcs/sources_1/new,data/full_repos/permissive/527597746/control_unit.v\n             data/full_repos/permissive/527597746/CPU.srcs/sources_1/new,data/full_repos/permissive/527597746/control_unit.sv\n             control_unit\n             control_unit.v\n             control_unit.sv\n             obj_dir/control_unit\n             obj_dir/control_unit.v\n             obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:56: Cannot find file containing module: 'pc'\n    pc p(.clk(clk),.reset(reset),.next_addr(neaddr),.pc(pc),.pcwre(pcwre)); \n    ^~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:58: Cannot find file containing module: 'mem'\n    mem mem(.din(reg_rt_dff),.dout(mem_dout),.addr(mem_addr),.we(wmem),.clrn(reset),.clk(mem_clk) ); \n    ^~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:61: Cannot find file containing module: 'regfile'\n    regfile rfile( .address_rs(inst[25:21]),.address_rt(inst[20:16]),.write_reg_address(reg_addr),.write_data(reg_din),.data_rs(reg_rs),.data_rt(reg_rt),.we(regwre),.clrn(reset),.clk(clk)); \n    ^~~~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:65: Cannot find file containing module: 'extend'\n    extend extend(.imm(inst[15:0]),.flag(extsel),.q(ex_imm)); \n    ^~~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:67: Cannot find file containing module: 'alu'\n    alu alu(.a(alu_a),.b(alu_b),.aluc(aluop),.result(result),.zero(zero),.sign(sign),.OF(OF),.CF(CF),.PF(PF) ); \n    ^~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:69: Cannot find file containing module: 'dff32'\n    dff32 ir(.e(wir),.d(mem_dout),.clk(clk),.clrn(reset),.q(inst)), dr(.e(1'b1),.d(mem_dout),.clk(clk),.clrn(reset),.q(mem_dout_dff)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:70: Cannot find file containing module: 'dff32'\n    dff32 dr_rs(.e(1'b1),.d(reg_rs),.clk(clk),.clrn(reset),.q(reg_rs_dff)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:71: Cannot find file containing module: 'dff32'\n    dff32 dr_rt(.e(1'b1),.d(reg_rt),.clk(clk),.clrn(reset),.q(reg_rt_dff)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:72: Cannot find file containing module: 'dff32'\n    dff32 dr_alu(.e(1'b1),.d(result),.clk(clk),.clrn(reset),.q(alu_dff)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:73: Cannot find file containing module: 'dff32'\n    dff32 dr_OF(.e(1'b1),.d({31'b0,OF}),.clk(clk),.clrn(reset),.q(OF_dff)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:75: Cannot find file containing module: 'mux_2'\n    mux_2 mux_mem(.flag(iord),.a(pc),.b(alu_dff),.out(mem_addr)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:76: Cannot find file containing module: 'mux_2'\n    mux_2 mux_db(.flag(dbdatasrc),.a(alu_dff),.b(mem_dout_dff),.out(db)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:77: Cannot find file containing module: 'mux_2'\n    mux_2 mux_reg_din(.flag(call),.a(db),.b(pc),.out(reg_din)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:78: Cannot find file containing module: 'mux_2'\n    mux_2 mux_sa(.flag(shift),.a(reg_rs_dff),.b({{27{1'b0}},inst[10:6]}),.out(tmp_alu_a)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:79: Cannot find file containing module: 'mux_2'\n    mux_2 mux_alu_a(.flag(alusrca),.a(tmp_alu_a),.b(pc),.out(alu_a)); \n    ^~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:80: Cannot find file containing module: 'mux_2_5'\n    mux_2_5 mux_rt_or_rd(.flag(regrt),.a(inst[20:16]),.b(inst[15:11]),.out(rt_or_rd)); \n    ^~~~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:81: Cannot find file containing module: 'mux_2_5'\n    mux_2_5 mux_reg_addr(.flag(call),.a(rt_or_rd),.b(5'h1F),.out(reg_addr)); \n    ^~~~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:82: Cannot find file containing module: 'mux_4_32'\n    mux_4_32 mux_alu_b(.flag(alusrcb),.a(reg_rt_dff),.b(32'b100),.c(ex_imm),.d(ex_imm<<2),.out(alu_b)); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/527597746/CPU.srcs/sources_1/new/cpu.v:83: Cannot find file containing module: 'mux_4_32'\n    mux_4_32 mux_pc(.flag(pcsrc),.a(result),.b(alu_dff),.c(reg_rs),.d({pc[31:28],inst[25:0],2'b00}),.out(neaddr)); \n    ^~~~~~~~\n%Error: Exiting due to 20 error(s)\n"
module cpu(
    input clk,
    input mem_clk,
    input reset,
    output wire [2:0] state,
    output wire [31:0] alu_a, alu_b, result, 
    output wire [31:0] mem_addr, mem_in, mem_dout, pc, inst,
    output wire [4:0] add_rs, add_rt,
    output wire [31:0] reg_din, reg_rs, reg_rt
    );

    wire [31:0] neaddr;
    
    wire pcwre,wmem,iord,wir,regrt,call,regwre,extsel,dbdatasrc,shift,alusrca,zero,sign,OF,PF,CF;
    wire [1:0] pcsrc;
    wire [1:0] alusrcb;
    
    wire [31:0] db;
    wire [31:0] OF_dff;
    wire [4:0] rt_or_rd;
    wire [4:0] reg_addr;
    wire [31:0] reg_rs_dff;
    wire [31:0] reg_rt_dff;
    wire [31:0] tmp_alu_a;
    wire [3:0] aluop;
    wire [31:0] alu_dff;
    wire [31:0] ex_imm;    
    wire [31:0] mem_dout_dff;
    
    control_unit con(.func(inst[5:0]),.op(inst[31:26]),.zero(zero),.sign(sign),.OF(OF_dff[0]),.CF(CF),.PF(PF),.pcwre(pcwre),.alusrca(alusrca),.alusrcb(alusrcb),
    .dbdatasrc(dbdatasrc), .regwre(regwre),.call(call),.wmem(wmem),.regrt(regrt),.extsel(extsel),.pcsrc(pcsrc),.aluop(aluop),.iord(iord),
        .wir(wir),.shift(shift),.clk(clk),.clrn(reset),.state(state));
        
    pc p(.clk(clk),.reset(reset),.next_addr(neaddr),.pc(pc),.pcwre(pcwre));
    
    mem mem(.din(reg_rt_dff),.dout(mem_dout),.addr(mem_addr),.we(wmem),.clrn(reset),.clk(mem_clk) );
    assign mem_in = reg_rt_dff;
    
    regfile rfile( .address_rs(inst[25:21]),.address_rt(inst[20:16]),.write_reg_address(reg_addr),.write_data(reg_din),.data_rs(reg_rs),.data_rt(reg_rt),.we(regwre),.clrn(reset),.clk(clk));
    assign add_rs = inst[25:21];
    assign add_rt = inst[20:16];
    
    extend extend(.imm(inst[15:0]),.flag(extsel),.q(ex_imm));
    
    alu alu(.a(alu_a),.b(alu_b),.aluc(aluop),.result(result),.zero(zero),.sign(sign),.OF(OF),.CF(CF),.PF(PF) );
    
    dff32 ir(.e(wir),.d(mem_dout),.clk(clk),.clrn(reset),.q(inst)), dr(.e(1'b1),.d(mem_dout),.clk(clk),.clrn(reset),.q(mem_dout_dff));
    dff32 dr_rs(.e(1'b1),.d(reg_rs),.clk(clk),.clrn(reset),.q(reg_rs_dff));
    dff32 dr_rt(.e(1'b1),.d(reg_rt),.clk(clk),.clrn(reset),.q(reg_rt_dff));
    dff32 dr_alu(.e(1'b1),.d(result),.clk(clk),.clrn(reset),.q(alu_dff));
    dff32 dr_OF(.e(1'b1),.d({31'b0,OF}),.clk(clk),.clrn(reset),.q(OF_dff));
    
    mux_2 mux_mem(.flag(iord),.a(pc),.b(alu_dff),.out(mem_addr));
    mux_2 mux_db(.flag(dbdatasrc),.a(alu_dff),.b(mem_dout_dff),.out(db));
    mux_2 mux_reg_din(.flag(call),.a(db),.b(pc),.out(reg_din));
    mux_2 mux_sa(.flag(shift),.a(reg_rs_dff),.b({{27{1'b0}},inst[10:6]}),.out(tmp_alu_a));
    mux_2 mux_alu_a(.flag(alusrca),.a(tmp_alu_a),.b(pc),.out(alu_a));
    mux_2_5 mux_rt_or_rd(.flag(regrt),.a(inst[20:16]),.b(inst[15:11]),.out(rt_or_rd));
    mux_2_5 mux_reg_addr(.flag(call),.a(rt_or_rd),.b(5'h1F),.out(reg_addr));
    mux_4_32 mux_alu_b(.flag(alusrcb),.a(reg_rt_dff),.b(32'b100),.c(ex_imm),.d(ex_imm<<2),.out(alu_b));
    mux_4_32 mux_pc(.flag(pcsrc),.a(result),.b(alu_dff),.c(reg_rs),.d({pc[31:28],inst[25:0],2'b00}),.out(neaddr));
endmodule
module cpu(
    input clk,
    input mem_clk,
    input reset,
    output wire [2:0] state,
    output wire [31:0] alu_a, alu_b, result, 
    output wire [31:0] mem_addr, mem_in, mem_dout, pc, inst,
    output wire [4:0] add_rs, add_rt,
    output wire [31:0] reg_din, reg_rs, reg_rt
    );


    wire [31:0] neaddr;
    
    wire pcwre,wmem,iord,wir,regrt,call,regwre,extsel,dbdatasrc,shift,alusrca,zero,sign,OF,PF,CF;
    wire [1:0] pcsrc;
    wire [1:0] alusrcb;
    
    wire [31:0] db;
    wire [31:0] OF_dff;
    wire [4:0] rt_or_rd;
    wire [4:0] reg_addr;
    wire [31:0] reg_rs_dff;
    wire [31:0] reg_rt_dff;
    wire [31:0] tmp_alu_a;
    wire [3:0] aluop;
    wire [31:0] alu_dff;
    wire [31:0] ex_imm;    
    wire [31:0] mem_dout_dff;
    
    control_unit con(.func(inst[5:0]),.op(inst[31:26]),.zero(zero),.sign(sign),.OF(OF_dff[0]),.CF(CF),.PF(PF),.pcwre(pcwre),.alusrca(alusrca),.alusrcb(alusrcb),
    .dbdatasrc(dbdatasrc), .regwre(regwre),.call(call),.wmem(wmem),.regrt(regrt),.extsel(extsel),.pcsrc(pcsrc),.aluop(aluop),.iord(iord),
        .wir(wir),.shift(shift),.clk(clk),.clrn(reset),.state(state));
        
    pc p(.clk(clk),.reset(reset),.next_addr(neaddr),.pc(pc),.pcwre(pcwre));
    
    mem mem(.din(reg_rt_dff),.dout(mem_dout),.addr(mem_addr),.we(wmem),.clrn(reset),.clk(mem_clk) );
    assign mem_in = reg_rt_dff;
    
    regfile rfile( .address_rs(inst[25:21]),.address_rt(inst[20:16]),.write_reg_address(reg_addr),.write_data(reg_din),.data_rs(reg_rs),.data_rt(reg_rt),.we(regwre),.clrn(reset),.clk(clk));
    assign add_rs = inst[25:21];
    assign add_rt = inst[20:16];
    
    extend extend(.imm(inst[15:0]),.flag(extsel),.q(ex_imm));
    
    alu alu(.a(alu_a),.b(alu_b),.aluc(aluop),.result(result),.zero(zero),.sign(sign),.OF(OF),.CF(CF),.PF(PF) );
    
    dff32 ir(.e(wir),.d(mem_dout),.clk(clk),.clrn(reset),.q(inst)), dr(.e(1'b1),.d(mem_dout),.clk(clk),.clrn(reset),.q(mem_dout_dff));
    dff32 dr_rs(.e(1'b1),.d(reg_rs),.clk(clk),.clrn(reset),.q(reg_rs_dff));
    dff32 dr_rt(.e(1'b1),.d(reg_rt),.clk(clk),.clrn(reset),.q(reg_rt_dff));
    dff32 dr_alu(.e(1'b1),.d(result),.clk(clk),.clrn(reset),.q(alu_dff));
    dff32 dr_OF(.e(1'b1),.d({31'b0,OF}),.clk(clk),.clrn(reset),.q(OF_dff));
    
    mux_2 mux_mem(.flag(iord),.a(pc),.b(alu_dff),.out(mem_addr));
    mux_2 mux_db(.flag(dbdatasrc),.a(alu_dff),.b(mem_dout_dff),.out(db));
    mux_2 mux_reg_din(.flag(call),.a(db),.b(pc),.out(reg_din));
    mux_2 mux_sa(.flag(shift),.a(reg_rs_dff),.b({{27{1'b0}},inst[10:6]}),.out(tmp_alu_a));
    mux_2 mux_alu_a(.flag(alusrca),.a(tmp_alu_a),.b(pc),.out(alu_a));
    mux_2_5 mux_rt_or_rd(.flag(regrt),.a(inst[20:16]),.b(inst[15:11]),.out(rt_or_rd));
    mux_2_5 mux_reg_addr(.flag(call),.a(rt_or_rd),.b(5'h1F),.out(reg_addr));
    mux_4_32 mux_alu_b(.flag(alusrcb),.a(reg_rt_dff),.b(32'b100),.c(ex_imm),.d(ex_imm<<2),.out(alu_b));
    mux_4_32 mux_pc(.flag(pcsrc),.a(result),.b(alu_dff),.c(reg_rs),.d({pc[31:28],inst[25:0],2'b00}),.out(neaddr));
endmodule