data/full_repos/permissive/428819669/addSubCircuit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428819669/addSubCircuit.v:138: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                        : ... In instance addSubCircuit\n                        result <= {zExp, Y[14:0]};\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428819669/addSubCircuit.v:140: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                        : ... In instance addSubCircuit\n                        result <= {zExp, X[14:0]};\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/428819669/addSubCircuit.v:170: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 12 bits.\n                                                                        : ... In instance addSubCircuit\n                        zMan <= addSubManTemp >> 1;\n                             ^~\n%Error: Exiting due to 3 warning(s)\n'
module addSubCircuit (
    output reg [1:0] OFUF, output reg done, output reg [15:0] result,
    input [15:0] X, Y,
    input addSub, reset, clk
    );

    reg [3:0] state;
    reg xSign, ySign, zSign;
    reg [4:0] xExp, yExp, zExp;
    reg [10:0] xMan, yMan, zMan;

    reg xBigger;

    reg [4:0] tempExp;
    reg [10:0] tempMan;
    reg [11:0] addSubManTemp;
    
    reg [10:0] subNormTemp;
    reg [4:0] tempZExp;
    wire normalized;
    assign normalized = (subNormTemp[10] == 1'b1);

    always @ (*) begin

        if (xExp < yExp) begin
            tempExp = xExp + 1;
            tempMan = xMan >> 1;
        end else if (xExp > yExp) begin
            tempExp = yExp + 1;
            tempMan = yMan >> 1;
        end 
        

        if (xSign == ySign) begin
            addSubManTemp = xMan + yMan;
            zSign = xSign;
        end else begin
            if (xBigger) 
                addSubManTemp = xMan - yMan;
            else 
                addSubManTemp = yMan - xMan;
            zSign = (xSign == xBigger);
        end


        if (addSubManTemp[10] == 1'b0) begin
            subNormTemp = zMan << 1;
            tempZExp = zExp - 1;
        end
    end

    always @ (posedge clk or posedge reset) begin
        if (reset) begin
            state <= 0;
            xSign <= X[15];
            ySign <= Y[15];
            xExp <= X[14:10];
            yExp <= Y[14:10];
            xMan <= {1'b1, X[9:0]};
            yMan <= {1'b1, Y[9:0]};
            if (X[14:10] > Y[14:10])
                xBigger <= 1;
            else if (X[14:10] < Y[14:10])
                xBigger <= 0;
            else begin
                if (X[9:0] > Y[9:0])
                    xBigger <= 1;
                else 
                    xBigger <= 0;    
            end
            done <= 0;
            OFUF <= 2'b00;
        end
        else begin
            case (state) 
                0: begin
                    if (X == 0 || Y == 0)
                        state <= 1;
                    else begin
                        if (addSub)
                            state <= 2;
                        else begin
                            if (xExp == yExp)
                                state <= 5;
                            else
                                state <= 3;
                        end
                    end
                end
                1: begin
                    if (X != 0) begin
                        result <= X;
                    end else if (Y != 0) begin
                        if (addSub)
                            result <= {~Y[15], Y[14:0]};
                        else    
                            result <= Y;  
                    end                 
                    done <= 1;
                    state <= 1;
                end
                2: begin
                    ySign <= ~ySign;
                    if (xExp == yExp)
                        state <= 5;
                    else
                        state <= 3;
                end
                3: begin


                    if (xExp < yExp) begin
                        xExp <= tempExp;
                        xMan <= tempMan;
                        if (tempMan == 0)
                            state <= 4;
                        else begin
                            if (tempExp == yExp)
                                state <= 5;
                            else 
                                state <= 3;
                        end
                    end else if (xExp > yExp) begin
                        yExp <= tempExp;
                        yMan <= tempMan;
                        if (tempMan == 0)
                            state <= 4;
                        else begin
                            if (tempExp == xExp)
                                state <= 5;
                            else 
                                state <= 3;
                        end
                    end
                end    
                4: begin
                    if (xMan == 0)
                        result <= {zExp, Y[14:0]};
                    else if (yMan == 0) begin
                        result <= {zExp, X[14:0]};
                    end
                    done <= 1;
                    state <= 4;
                end        
                5: begin
                    zExp <= xExp;
                    zMan <= addSubManTemp[10:0];
                    if (addSubManTemp == 0) begin
                        state <= 6;
                    end else begin
                        if (addSubManTemp[11] == 1'b1)
                            state <= 7;
                        else begin
                            if (addSubManTemp[10] == 1'b0)
                                state <= 9;
                            else 
                                state <= 11;
                        end
                    end
                end    
                6: begin
                    result <= 16'b0;
                    done <= 1;
                    state <= 6;
                end
                7: begin
                    if (zExp == 5'b11110)
                        state <= 8;
                    else begin
                        zMan <= addSubManTemp >> 1;
                        zExp <= zExp + 1;
                        state <= 11;
                    end
                end
                8: begin
                    result <= 16'bz;
                    OFUF <= 2'b10;
                end
                9: begin
                    if (zExp == 5'b0)
                        state <= 10;
                    else begin
                        zMan <= subNormTemp;
                        zExp <= tempZExp;
                        if (normalized)
                            state <= 11;
                        else
                            state <= 9;
                    end
                end
                10: begin
                    OFUF <= 2'b01;
                    done <= 1;
                    state <= 10;
                end
                11: begin
                    result <= {zSign, zExp, zMan[9:0]};
                    done <= 1;
                    state <= 11;
                end
                default: state <= 0; 
            endcase
        end
    end
endmodule
module addSubCircuit (
    output reg [1:0] OFUF, output reg done, output reg [15:0] result,
    input [15:0] X, Y,
    input addSub, reset, clk
    );


    reg [3:0] state;
    reg xSign, ySign, zSign;
    reg [4:0] xExp, yExp, zExp;
    reg [10:0] xMan, yMan, zMan;

    reg xBigger;

    reg [4:0] tempExp;
    reg [10:0] tempMan;
    reg [11:0] addSubManTemp;
    
    reg [10:0] subNormTemp;
    reg [4:0] tempZExp;
    wire normalized;
    assign normalized = (subNormTemp[10] == 1'b1);

    always @ (*) begin

        if (xExp < yExp) begin
            tempExp = xExp + 1;
            tempMan = xMan >> 1;
        end else if (xExp > yExp) begin
            tempExp = yExp + 1;
            tempMan = yMan >> 1;
        end 
        

        if (xSign == ySign) begin
            addSubManTemp = xMan + yMan;
            zSign = xSign;
        end else begin
            if (xBigger) 
                addSubManTemp = xMan - yMan;
            else 
                addSubManTemp = yMan - xMan;
            zSign = (xSign == xBigger);
        end


        if (addSubManTemp[10] == 1'b0) begin
            subNormTemp = zMan << 1;
            tempZExp = zExp - 1;
        end
    end

    always @ (posedge clk or posedge reset) begin
        if (reset) begin
            state <= 0;
            xSign <= X[15];
            ySign <= Y[15];
            xExp <= X[14:10];
            yExp <= Y[14:10];
            xMan <= {1'b1, X[9:0]};
            yMan <= {1'b1, Y[9:0]};
            if (X[14:10] > Y[14:10])
                xBigger <= 1;
            else if (X[14:10] < Y[14:10])
                xBigger <= 0;
            else begin
                if (X[9:0] > Y[9:0])
                    xBigger <= 1;
                else 
                    xBigger <= 0;    
            end
            done <= 0;
            OFUF <= 2'b00;
        end
        else begin
            case (state) 
                0: begin
                    if (X == 0 || Y == 0)
                        state <= 1;
                    else begin
                        if (addSub)
                            state <= 2;
                        else begin
                            if (xExp == yExp)
                                state <= 5;
                            else
                                state <= 3;
                        end
                    end
                end
                1: begin
                    if (X != 0) begin
                        result <= X;
                    end else if (Y != 0) begin
                        if (addSub)
                            result <= {~Y[15], Y[14:0]};
                        else    
                            result <= Y;  
                    end                 
                    done <= 1;
                    state <= 1;
                end
                2: begin
                    ySign <= ~ySign;
                    if (xExp == yExp)
                        state <= 5;
                    else
                        state <= 3;
                end
                3: begin


                    if (xExp < yExp) begin
                        xExp <= tempExp;
                        xMan <= tempMan;
                        if (tempMan == 0)
                            state <= 4;
                        else begin
                            if (tempExp == yExp)
                                state <= 5;
                            else 
                                state <= 3;
                        end
                    end else if (xExp > yExp) begin
                        yExp <= tempExp;
                        yMan <= tempMan;
                        if (tempMan == 0)
                            state <= 4;
                        else begin
                            if (tempExp == xExp)
                                state <= 5;
                            else 
                                state <= 3;
                        end
                    end
                end    
                4: begin
                    if (xMan == 0)
                        result <= {zExp, Y[14:0]};
                    else if (yMan == 0) begin
                        result <= {zExp, X[14:0]};
                    end
                    done <= 1;
                    state <= 4;
                end        
                5: begin
                    zExp <= xExp;
                    zMan <= addSubManTemp[10:0];
                    if (addSubManTemp == 0) begin
                        state <= 6;
                    end else begin
                        if (addSubManTemp[11] == 1'b1)
                            state <= 7;
                        else begin
                            if (addSubManTemp[10] == 1'b0)
                                state <= 9;
                            else 
                                state <= 11;
                        end
                    end
                end    
                6: begin
                    result <= 16'b0;
                    done <= 1;
                    state <= 6;
                end
                7: begin
                    if (zExp == 5'b11110)
                        state <= 8;
                    else begin
                        zMan <= addSubManTemp >> 1;
                        zExp <= zExp + 1;
                        state <= 11;
                    end
                end
                8: begin
                    result <= 16'bz;
                    OFUF <= 2'b10;
                end
                9: begin
                    if (zExp == 5'b0)
                        state <= 10;
                    else begin
                        zMan <= subNormTemp;
                        zExp <= tempZExp;
                        if (normalized)
                            state <= 11;
                        else
                            state <= 9;
                    end
                end
                10: begin
                    OFUF <= 2'b01;
                    done <= 1;
                    state <= 10;
                end
                11: begin
                    result <= {zSign, zExp, zMan[9:0]};
                    done <= 1;
                    state <= 11;
                end
                default: state <= 0; 
            endcase
        end
    end
endmodule