data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:80: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h52\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n            tx_char[7:0] <= (r_rnw)?(7\'d82):(7\'d87);  \n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:80: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'7\'h57\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n            tx_char[7:0] <= (r_rnw)?(7\'d82):(7\'d87);  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:89: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h20\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n            tx_char[7:0] <= 7\'d32;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:320: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                            : ... In instance uart_debug_printer\n      hex2ascii[7:0] = hex[3:0] + 7\'d48;  \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:322: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                            : ... In instance uart_debug_printer\n      hex2ascii[7:0] = hex[3:0] + 7\'d55;  \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:136: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                            : ... In instance uart_debug_printer\n            tx_char[7:0] <= 7\'d95;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:182: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h20\' generates 7 bits.\n                                                                                            : ... In instance uart_debug_printer\n            tx_char[7:0] <= 7\'d32;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:228: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                            : ... In instance uart_debug_printer\n            tx_char[7:0] <= 7\'d95;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:274: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'hd\' generates 7 bits.\n                                                                                            : ... In instance uart_debug_printer\n            tx_char[7:0] <= 7\'d13;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h0\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h1\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h2\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h3\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h5\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h7\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h8\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h9\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'ha\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'hb\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'hc\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'hd\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'he\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'hf\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h10\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h11\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h12\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h13\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h14\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h15\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:76: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h16\' generates 7 bits.\n                                                                                           : ... In instance uart_debug_printer\n      case ( seq_cntr[7:0] )\n      ^~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/uart_debug_printer.sv:297: Cannot find file containing module: \'uart_tx\'\n  uart_tx #(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/uart_tx\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/uart_tx.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: Exiting due to 1 error(s), 32 warning(s)\n'
function [7:0] hex2ascii(
    input [3:0] hex
  );
    if( hex[3:0] < 4'hA ) begin
      hex2ascii[7:0] = hex[3:0] + 7'd48;
    end else begin
      hex2ascii[7:0] = hex[3:0] + 7'd55;
    end
  endfunction
function [7:0] hex2ascii(
    input [3:0] hex
  );

    if( hex[3:0] < 4'hA ) begin
      hex2ascii[7:0] = hex[3:0] + 7'd48;
    end else begin
      hex2ascii[7:0] = hex[3:0] + 7'd55;
    end
  endfunction