data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Up.v
data/verilator_xmls/459ae218-bb26-4ae7-a4df-789f645db6b0.xml
module bit3(input wire clk,reset,count,inc,output wire cout,output wire [2:0]q);
wire y[1:0];
count1 c1(clk,reset,count,inc,y[0],q[0]);
count1 c2(clk,reset,y[0],inc,y[1],q[1]);
count1 c3(clk,reset,y[1],inc,cout,q[2]);
endmodule
module bit3(input wire clk,reset,count,inc,output wire cout,output wire [2:0]q);

wire y[1:0];
count1 c1(clk,reset,count,inc,y[0],q[0]);
count1 c2(clk,reset,y[0],inc,y[1],q[1]);
count1 c3(clk,reset,y[1],inc,cout,q[2]);
endmodule