data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_dump.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_dump.v:21: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_dump.v:33: Unsupported: Ignoring delay on this delayed statement.\n   forever #418 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module playback_dump();

integer fid;
reg clk_start;
reg clk;

initial begin
   fid = $fopen("stimuli.txt","w");
   clk_start = 1'b0;
   clk = 1'b0;
   forever #418 clk = ~clk;
end


wire [156:0] input_vector = {
	cmp_top.iop.sparc0.pcx_spc_grant_px, 
	cmp_top.iop.sparc0.cpx_spc_data_rdy_cx2, 
	cmp_top.iop.sparc0.cpx_spc_data_cx2, 
	cmp_top.iop.sparc0.cluster_cken, 
	cmp_top.iop.sparc0.cmp_grst_l, 
	cmp_top.iop.sparc0.cmp_arst_l, 
	cmp_top.iop.sparc0.ctu_tst_pre_grst_l, 
	cmp_top.iop.sparc0.adbginit_l, 
	cmp_top.iop.sparc0.gdbginit_l};

wire [129:0] output_vector = {
	cmp_top.iop.sparc0.spc_pcx_req_pq, 
	cmp_top.iop.sparc0.spc_pcx_atom_pq, 
	cmp_top.iop.sparc0.spc_pcx_data_pa};

wire clock_vector = cmp_top.iop.sparc0.gclk;

always @(posedge clk) begin
  if(~clk_start) begin
    $fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
  end
end

always @(posedge clock_vector) begin
  clk_start = 1'b1;
  $fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
end

endmodule
module playback_dump();


integer fid;
reg clk_start;
reg clk;

initial begin
   fid = $fopen("stimuli.txt","w");
   clk_start = 1'b0;
   clk = 1'b0;
   forever #418 clk = ~clk;
end


wire [156:0] input_vector = {
	cmp_top.iop.sparc0.pcx_spc_grant_px, 
	cmp_top.iop.sparc0.cpx_spc_data_rdy_cx2, 
	cmp_top.iop.sparc0.cpx_spc_data_cx2, 
	cmp_top.iop.sparc0.cluster_cken, 
	cmp_top.iop.sparc0.cmp_grst_l, 
	cmp_top.iop.sparc0.cmp_arst_l, 
	cmp_top.iop.sparc0.ctu_tst_pre_grst_l, 
	cmp_top.iop.sparc0.adbginit_l, 
	cmp_top.iop.sparc0.gdbginit_l};

wire [129:0] output_vector = {
	cmp_top.iop.sparc0.spc_pcx_req_pq, 
	cmp_top.iop.sparc0.spc_pcx_atom_pq, 
	cmp_top.iop.sparc0.spc_pcx_data_pa};

wire clock_vector = cmp_top.iop.sparc0.gclk;

always @(posedge clk) begin
  if(~clk_start) begin
    $fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
  end
end

always @(posedge clock_vector) begin
  clk_start = 1'b1;
  $fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
end

endmodule