data/full_repos/permissive/452016975/src/control_unit_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/control_unit_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/452016975/src/control_unit_testbench.v:30: Unsupported or unknown PLI call: $monitor\n $monitor("time=%2d,opcode=%2d,reg_dest=%1b,alu_src=%1b,mem_to_reg=%1b,reg_write=%1b,mem_read=%1b,mem_write=%1b,branch=%1b,alu_op=%3b"\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit_testbench();
	reg [3:0] opcode;
	wire reg_dest,branch,mem_read,mem_to_reg,mem_write,alu_src,reg_write; 
	wire [2:0] alu_op;			
	control_unit my_control(reg_dest, branch, mem_read, mem_to_reg, opcode, 
																alu_op, mem_write, alu_src, reg_write);
	initial begin
	opcode = 4'b0000;
	#20;
	opcode = 4'b0001;
	#20;
	opcode = 4'b0010;
	#20;
	opcode = 4'b0011;
	#20;
	opcode = 4'b0100;
	#20;
	opcode = 4'b0101;
	#20;
	opcode = 4'b0110;
	#20; 
	opcode = 4'b0111;
	#20;
	opcode = 4'b1000;
	#20;
	opcode = 4'b1001;
	#20;
	end
	initial begin
	$monitor("time=%2d,opcode=%2d,reg_dest=%1b,alu_src=%1b,mem_to_reg=%1b,reg_write=%1b,mem_read=%1b,mem_write=%1b,branch=%1b,alu_op=%3b"
	          ,$time,opcode,reg_dest,alu_src,mem_to_reg,reg_write,mem_read,mem_write,branch,alu_op);
	end
endmodule
module control_unit_testbench();

	reg [3:0] opcode;
	wire reg_dest,branch,mem_read,mem_to_reg,mem_write,alu_src,reg_write; 
	wire [2:0] alu_op;			
	control_unit my_control(reg_dest, branch, mem_read, mem_to_reg, opcode, 
																alu_op, mem_write, alu_src, reg_write);
	initial begin
	opcode = 4'b0000;
	#20;
	opcode = 4'b0001;
	#20;
	opcode = 4'b0010;
	#20;
	opcode = 4'b0011;
	#20;
	opcode = 4'b0100;
	#20;
	opcode = 4'b0101;
	#20;
	opcode = 4'b0110;
	#20; 
	opcode = 4'b0111;
	#20;
	opcode = 4'b1000;
	#20;
	opcode = 4'b1001;
	#20;
	end
	initial begin
	$monitor("time=%2d,opcode=%2d,reg_dest=%1b,alu_src=%1b,mem_to_reg=%1b,reg_write=%1b,mem_read=%1b,mem_write=%1b,branch=%1b,alu_op=%3b"
	          ,$time,opcode,reg_dest,alu_src,mem_to_reg,reg_write,mem_read,mem_write,branch,alu_op);
	end
endmodule