data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new/tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new/tester.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #0 clk = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new/tester.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1000000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new/tester.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new/tester.v:29: Cannot find file containing module: \'main\'\n    main h(seg,an,clk);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new,data/full_repos/permissive/423958267/main\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new,data/full_repos/permissive/423958267/main.v\n             data/full_repos/permissive/423958267/lab02/lab02.srcs/sim_1/new,data/full_repos/permissive/423958267/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(
);
    wire [6:0] seg;
    wire [3:0] an;
    reg clk;
    
    main h(seg,an,clk);
    
    initial
    begin


        #0 clk = 0;
        #1000000 $finish;
    end
    
    always
    #10 clk = ~clk;

endmodule
module tester(
);

    wire [6:0] seg;
    wire [3:0] an;
    reg clk;
    
    main h(seg,an,clk);
    
    initial
    begin


        #0 clk = 0;
        #1000000 $finish;
    end
    
    always
    #10 clk = ~clk;

endmodule