data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk2x_1x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk2x_1x.v:120: Cannot find file containing module: 'phasedet_ck1x'\nphasedet_ck1x   phasedet_ck1xi\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/phasedet_ck1x.sv\n             phasedet_ck1x\n             phasedet_ck1x.v\n             phasedet_ck1x.sv\n             obj_dir/phasedet_ck1x\n             obj_dir/phasedet_ck1x.v\n             obj_dir/phasedet_ck1x.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk2x_1x.v:135: Cannot find file containing module: 'fflopx'\nfflopx #(WIDTH+1) ipp(clk2x, rst2x_, {sync2x, data2x}, {sync2xp, data2xp});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk2x_1x.v:140: Cannot find file containing module: 'fflopx'\nfflopx #(WIDTH+1) ipp1(clk2x, rst2x_, {sync2xp, data2xp}, {sync2xp1, data2xp1});\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module convclk2x_1x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     sync2x,
     data2x,
     
     sync1x,
     data1x,

     phaseout
     );

parameter WIDTH = 8;



input   rst1x_,
        rst2x_,
        clk2x,
        clk1x;

input   scanmode;

input   sync2x;
input   [WIDTH-1:0]   data2x;

output  sync1x;
output  [WIDTH-1:0]   data1x;

output                phaseout;



































































wire                  phase_one_1xr;

phasedet_ck1x   phasedet_ck1xi
    (
     .rst1x_    (rst1x_),
     .rst2x_    (rst2x_),
     .clk2x     (clk2x),
     .clk1x     (clk1x),

     .scanmode  (scanmode),

     .phaseout  (phase_one_1xr)
     );


wire    sync2xp;
wire    [WIDTH-1:0]   data2xp;
fflopx #(WIDTH+1) ipp(clk2x, rst2x_, {sync2x, data2x}, {sync2xp, data2xp});


wire    sync2xp1;
wire    [WIDTH-1:0]   data2xp1;
fflopx #(WIDTH+1) ipp1(clk2x, rst2x_, {sync2xp, data2xp}, {sync2xp1, data2xp1});


reg     selphase1;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) selphase1 <= 1'b0;
    else if(sync2xp & phase_one_1xr) selphase1 <= 1'b0;
    else if(sync2xp1 & phase_one_1xr) selphase1 <= 1'b1;
    end


reg     sync2x_1x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) sync2x_1x <= 1'b0;
    else if(selphase1)
        begin
        if(phase_one_1xr) sync2x_1x <= sync2xp1;
        end
    else
        begin
        if(phase_one_1xr) sync2x_1x <= sync2xp;
        end
    end

reg     [WIDTH-1:0]   data2x_1x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) data2x_1x <= {WIDTH{1'b0}};
    else if(selphase1)
        begin
        if(phase_one_1xr) data2x_1x <= data2xp1;
        end
    else
        begin
        if(phase_one_1xr) data2x_1x <= data2xp;
        end
    end


reg     sync1x;
always @ (posedge clk1x or negedge rst1x_)
    begin
    if(!rst1x_) sync1x <= 1'b0;
    else sync1x <= sync2x_1x;
    end

reg     [WIDTH-1:0]   data1x;
always @ (posedge clk1x or negedge rst1x_)
    begin
    if(!rst1x_) data1x <= {WIDTH{1'b0}};
    else data1x <= data2x_1x;
    end

assign phaseout = selphase1;

endmodule
module convclk2x_1x
    (
     rst1x_,
     rst2x_,
     clk2x,
     clk1x,

     scanmode,

     sync2x,
     data2x,
     
     sync1x,
     data1x,

     phaseout
     );


parameter WIDTH = 8;



input   rst1x_,
        rst2x_,
        clk2x,
        clk1x;

input   scanmode;

input   sync2x;
input   [WIDTH-1:0]   data2x;

output  sync1x;
output  [WIDTH-1:0]   data1x;

output                phaseout;



































































wire                  phase_one_1xr;

phasedet_ck1x   phasedet_ck1xi
    (
     .rst1x_    (rst1x_),
     .rst2x_    (rst2x_),
     .clk2x     (clk2x),
     .clk1x     (clk1x),

     .scanmode  (scanmode),

     .phaseout  (phase_one_1xr)
     );


wire    sync2xp;
wire    [WIDTH-1:0]   data2xp;
fflopx #(WIDTH+1) ipp(clk2x, rst2x_, {sync2x, data2x}, {sync2xp, data2xp});


wire    sync2xp1;
wire    [WIDTH-1:0]   data2xp1;
fflopx #(WIDTH+1) ipp1(clk2x, rst2x_, {sync2xp, data2xp}, {sync2xp1, data2xp1});


reg     selphase1;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) selphase1 <= 1'b0;
    else if(sync2xp & phase_one_1xr) selphase1 <= 1'b0;
    else if(sync2xp1 & phase_one_1xr) selphase1 <= 1'b1;
    end


reg     sync2x_1x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) sync2x_1x <= 1'b0;
    else if(selphase1)
        begin
        if(phase_one_1xr) sync2x_1x <= sync2xp1;
        end
    else
        begin
        if(phase_one_1xr) sync2x_1x <= sync2xp;
        end
    end

reg     [WIDTH-1:0]   data2x_1x;
always @ (posedge clk2x or negedge rst2x_)
    begin
    if(!rst2x_) data2x_1x <= {WIDTH{1'b0}};
    else if(selphase1)
        begin
        if(phase_one_1xr) data2x_1x <= data2xp1;
        end
    else
        begin
        if(phase_one_1xr) data2x_1x <= data2xp;
        end
    end


reg     sync1x;
always @ (posedge clk1x or negedge rst1x_)
    begin
    if(!rst1x_) sync1x <= 1'b0;
    else sync1x <= sync2x_1x;
    end

reg     [WIDTH-1:0]   data1x;
always @ (posedge clk1x or negedge rst1x_)
    begin
    if(!rst1x_) data1x <= {WIDTH{1'b0}};
    else data1x <= data2x_1x;
    end

assign phaseout = selphase1;

endmodule