data/full_repos/permissive/423412549/src/rtl/me.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/me.v:9: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:16: Define or directive not defined: \'`H_DISP_LEN\'\n        input  wire [       `H_DISP_LEN-1:0] req_x_addr_i,\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:17: Define or directive not defined: \'`V_DISP_LEN\'\n        input  wire [       `V_DISP_LEN-1:0] req_y_addr_i,\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:23: Define or directive not defined: \'`OBJ_X_POS_BIT_LEN\'\n        output wire [`OBJ_X_POS_BIT_LEN-1:0] x_pos_o,\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:24: Define or directive not defined: \'`OBJ_Y_POS_BIT_LEN\'\n        output wire [`OBJ_Y_POS_BIT_LEN-1:0] y_pos_o,\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:25: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n        output wire [  `COLOR_RGB_DEPTH-1:0] vga_rgb_o,\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:44: Define or directive not defined: \'`ME_SPEED\'\n    parameter SPEED = `ME_SPEED;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter SPEED = `ME_SPEED;\n                               ^\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:45: Define or directive not defined: \'`V_DISP\'\n    localparam DOWN_BOUND = `V_DISP - `ME_Y_SIZE - SPEED;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:45: Define or directive not defined: \'`ME_Y_SIZE\'\n    localparam DOWN_BOUND = `V_DISP - `ME_Y_SIZE - SPEED;\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:46: Define or directive not defined: \'`H_DISP\'\n    localparam RIGHT_BOUND = `H_DISP - `ME_X_SIZE - SPEED;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:46: Define or directive not defined: \'`ME_X_SIZE\'\n    localparam RIGHT_BOUND = `H_DISP - `ME_X_SIZE - SPEED;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:56: Define or directive not defined: \'`OBJ_X_POS_BIT_LEN\'\n    reg  [    `OBJ_X_POS_BIT_LEN-1:0] x_pos;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:57: Define or directive not defined: \'`OBJ_Y_POS_BIT_LEN\'\n    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] y_pos;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:58: Define or directive not defined: \'`OBJ_Y_POS_BIT_LEN\'\n    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] displocked_y_pos;\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:59: Define or directive not defined: \'`ME_BRAM_DEPTH_BIT_LEN\'\n    reg  [`ME_BRAM_DEPTH_BIT_LEN-1:0] bram_addr_cnt = 0;      \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:60: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_1;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:61: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_2;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:62: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_1;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:63: Define or directive not defined: \'`COLOR_GRAY_DEPTH\'\n    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_2;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:69: Define or directive not defined: \'`ME_BRAM_WIDTH\'\n    wire [        `ME_BRAM_WIDTH-1:0] bram_info;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:72: Define or directive not defined: \'`ENEMY_CNT_MAX_DOWN_BIT_LEN\'\n    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:76: Define or directive not defined: \'`ME_STATE_REG_WIDTH\'\n    reg  [   `ME_STATE_REG_WIDTH-1:0] state;\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:77: Define or directive not defined: \'`ME_STATE_REG_WIDTH\'\n    reg  [   `ME_STATE_REG_WIDTH-1:0] n_state;\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:78: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    reg  [      `COLOR_RGB_DEPTH-1:0] vga_rgb;\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:102: Define or directive not defined: \'`ENEMY_CNT_MAX_DOWN\'\n            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin\n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:122: Define or directive not defined: \'`ME_X_SIZE\'\n           && (req_x_addr_i < x_pos + `ME_X_SIZE)\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:122: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n           && (req_x_addr_i < x_pos + `ME_X_SIZE)\n                                                ^\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:124: Define or directive not defined: \'`ME_Y_SIZE\'\n           && (req_y_addr_i < displocked_y_pos + `ME_Y_SIZE); \n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:209: Define or directive not defined: \'`ME_DEFAULT_X_POS\'\n            x_pos <= `ME_DEFAULT_X_POS;\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            x_pos <= `ME_DEFAULT_X_POS;\n                                      ^\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:210: Define or directive not defined: \'`ME_DEFAULT_Y_POS\'\n            y_pos <= `ME_DEFAULT_Y_POS;\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:210: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            y_pos <= `ME_DEFAULT_Y_POS;\n                                      ^\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:215: Define or directive not defined: \'`UP\'\n                    `UP: begin\n                    ^~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:215: syntax error, unexpected \':\', expecting endcase\n                    `UP: begin\n                       ^\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:224: Define or directive not defined: \'`DOWN\'\n                    `DOWN: begin\n                    ^~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:224: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `DOWN: begin\n                           ^~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:231: syntax error, unexpected <=, expecting IDENTIFIER\n                        x_pos <= x_pos;\n                              ^~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:233: Define or directive not defined: \'`LEFT\'\n                    `LEFT: begin\n                    ^~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/me.v:242: Define or directive not defined: \'`RIGHT\'\n                    `RIGHT: begin\n                    ^~~~~~\n%Error: Cannot continue\n'
module me (
        input  wire                          clk_run,
        input  wire                          clk_vga,
        input  wire                          rst,
        input  wire                          en_i,
        input  wire                          v_sync_i,
        input  wire [       `H_DISP_LEN-1:0] req_x_addr_i,
        input  wire [       `V_DISP_LEN-1:0] req_y_addr_i,
        input  wire                          move_en_i,
        input  wire [1:0]                    direct_i,
        input  wire                          crash_me_enemy_i,


        output wire [`OBJ_X_POS_BIT_LEN-1:0] x_pos_o,
        output wire [`OBJ_Y_POS_BIT_LEN-1:0] y_pos_o,
        output wire [  `COLOR_RGB_DEPTH-1:0] vga_rgb_o,
        output wire                          vga_alpha_o

    );




    parameter SPEED = `ME_SPEED;
    localparam DOWN_BOUND = `V_DISP - `ME_Y_SIZE - SPEED;
    localparam RIGHT_BOUND = `H_DISP - `ME_X_SIZE - SPEED;
    localparam UP_BOUND = SPEED;
    localparam LEFT_BOUND = SPEED;
    localparam STATE_N1       = 3'b001;
    localparam STATE_N2       = 3'b010;
    localparam STATE_DOWN1    = 3'b011;
    localparam STATE_DOWN2    = 3'b111;
    localparam STATE_UNVISUAL = 3'b110;


    reg  [    `OBJ_X_POS_BIT_LEN-1:0] x_pos;
    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] y_pos;
    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] displocked_y_pos;
    reg  [`ME_BRAM_DEPTH_BIT_LEN-1:0] bram_addr_cnt = 0;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_1;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_2;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_1;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_2;

    wire                              bram_alpha_1;
    wire                              bram_alpha_2;
    wire                              bram_alpha_destroy_1;
    wire                              bram_alpha_destroy_2;
    wire [        `ME_BRAM_WIDTH-1:0] bram_info;


    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;
    reg                                        state_change;
    wire                              bram_clr;
    wire                              in_req_area;
    reg  [   `ME_STATE_REG_WIDTH-1:0] state;
    reg  [   `ME_STATE_REG_WIDTH-1:0] n_state;
    reg  [      `COLOR_RGB_DEPTH-1:0] vga_rgb;
    reg                               vga_alpha;


    assign x_pos_o = x_pos;
    assign y_pos_o = y_pos;


    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            displocked_y_pos <= 0;
        end else begin
            if(~v_sync_i) begin
                displocked_y_pos <= y_pos;
            end else begin
                displocked_y_pos <= displocked_y_pos;
            end
        end
    end

    always @(posedge clk_vga or posedge rst)begin
        if(rst) begin
            cnt_down <= 0;
        end else begin
            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin
                state_change <= 1;
                cnt_down <= 0;
            end else begin
                state_change <= 0;
                cnt_down <= cnt_down + 1;
            end
        end
    end

    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            state <= STATE_N1;
        end else begin
            state <= n_state;
        end
    end


    assign in_req_area = en_i && (req_x_addr_i >= x_pos)
           && (req_x_addr_i < x_pos + `ME_X_SIZE)
           && (req_y_addr_i >= displocked_y_pos)
           && (req_y_addr_i < displocked_y_pos + `ME_Y_SIZE); 


    assign bram_clr = ~v_sync_i;
    always@(posedge clk_vga or posedge rst or posedge bram_clr) begin
        if(rst | bram_clr) begin
            bram_addr_cnt <= 0;
        end
        else begin
            if(in_req_area) begin
                bram_addr_cnt <= bram_addr_cnt + 1;
            end
            else begin
                bram_addr_cnt <= bram_addr_cnt;
            end
        end
    end

    assign {bram_alpha_1, bram_gray_1, bram_alpha_2, bram_gray_2,
             bram_alpha_destroy_1, bram_gray_destroy_1,
             bram_alpha_destroy_2,bram_gray_destroy_2}
             = bram_info;

    bram_me bram_me_dut
             (
                 .clka(clk_vga),
                 .ena(1'b1),
                 .addra(bram_addr_cnt),
                 .douta(bram_info)
             );
    
    assign vga_rgb_o = vga_rgb;
    assign vga_alpha_o = vga_alpha;

    always @(*) begin
        if(in_req_area) begin
            case(state)
                STATE_N1: begin
                    vga_alpha = bram_alpha_1;
                    vga_rgb   = {3{bram_gray_1}};
                end
                STATE_N2: begin
                    vga_alpha = bram_alpha_2;
                    vga_rgb   = {3{bram_gray_2}};
                end
                STATE_DOWN1: begin
                    vga_alpha = bram_alpha_destroy_1;
                    vga_rgb   = {3{bram_gray_destroy_1}};
                end
                STATE_DOWN2: begin
                    vga_alpha = bram_alpha_destroy_2;
                    vga_rgb   = {3{bram_gray_destroy_2}};
                end
                default: begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
            endcase
        end else begin
            vga_alpha = 0;
            vga_rgb   = 0;
        end
    end

    always @(*) begin
        case(state)
            STATE_N1 :
                n_state = crash_me_enemy_i ? STATE_DOWN1 : state_change ? STATE_N2 : STATE_N1;
            STATE_N2 :
                n_state = crash_me_enemy_i ? STATE_DOWN1 : state_change ? STATE_N1 : STATE_N2;
            STATE_DOWN1 :
                n_state = state_change ? STATE_DOWN2 : STATE_DOWN1;
            STATE_DOWN2:
                n_state = state_change ? STATE_UNVISUAL : STATE_DOWN2;
            STATE_UNVISUAL :
                n_state = STATE_UNVISUAL;
            default:
                n_state = STATE_N1;
        endcase
    end



    always @(posedge clk_run or posedge rst) begin
        if(rst) begin
            x_pos <= `ME_DEFAULT_X_POS;
            y_pos <= `ME_DEFAULT_Y_POS;
        end
        else begin
            if(en_i && move_en_i) begin
                case(direct_i)
                    `UP: begin
                        if(y_pos > UP_BOUND) begin
                            y_pos <= y_pos - SPEED;
                        end
                        else begin
                            y_pos <= y_pos;
                        end
                        x_pos <= x_pos;
                    end
                    `DOWN: begin
                        if(y_pos < DOWN_BOUND) begin
                            y_pos <= y_pos + SPEED;
                        end
                        else begin
                            y_pos <= y_pos;
                        end
                        x_pos <= x_pos;
                    end
                    `LEFT: begin
                        if(x_pos > LEFT_BOUND) begin
                            x_pos <= x_pos - SPEED;
                        end
                        else begin
                            x_pos <= x_pos;
                        end
                        y_pos <= y_pos;
                    end
                    `RIGHT: begin
                        if(x_pos < RIGHT_BOUND) begin
                            x_pos <= x_pos + SPEED;
                        end
                        else begin
                            x_pos <= x_pos;
                        end
                        y_pos <= y_pos;
                    end
                endcase
            end
            else begin
                x_pos <= x_pos;
                y_pos <= y_pos;
            end
        end
    end

endmodule
module me (
        input  wire                          clk_run,
        input  wire                          clk_vga,
        input  wire                          rst,
        input  wire                          en_i,
        input  wire                          v_sync_i,
        input  wire [       `H_DISP_LEN-1:0] req_x_addr_i,
        input  wire [       `V_DISP_LEN-1:0] req_y_addr_i,
        input  wire                          move_en_i,
        input  wire [1:0]                    direct_i,
        input  wire                          crash_me_enemy_i,


        output wire [`OBJ_X_POS_BIT_LEN-1:0] x_pos_o,
        output wire [`OBJ_Y_POS_BIT_LEN-1:0] y_pos_o,
        output wire [  `COLOR_RGB_DEPTH-1:0] vga_rgb_o,
        output wire                          vga_alpha_o

    );





    parameter SPEED = `ME_SPEED;
    localparam DOWN_BOUND = `V_DISP - `ME_Y_SIZE - SPEED;
    localparam RIGHT_BOUND = `H_DISP - `ME_X_SIZE - SPEED;
    localparam UP_BOUND = SPEED;
    localparam LEFT_BOUND = SPEED;
    localparam STATE_N1       = 3'b001;
    localparam STATE_N2       = 3'b010;
    localparam STATE_DOWN1    = 3'b011;
    localparam STATE_DOWN2    = 3'b111;
    localparam STATE_UNVISUAL = 3'b110;


    reg  [    `OBJ_X_POS_BIT_LEN-1:0] x_pos;
    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] y_pos;
    reg  [    `OBJ_Y_POS_BIT_LEN-1:0] displocked_y_pos;
    reg  [`ME_BRAM_DEPTH_BIT_LEN-1:0] bram_addr_cnt = 0;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_1;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_2;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_1;
    wire [     `COLOR_GRAY_DEPTH-1:0] bram_gray_destroy_2;

    wire                              bram_alpha_1;
    wire                              bram_alpha_2;
    wire                              bram_alpha_destroy_1;
    wire                              bram_alpha_destroy_2;
    wire [        `ME_BRAM_WIDTH-1:0] bram_info;


    reg  [    `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;
    reg                                        state_change;
    wire                              bram_clr;
    wire                              in_req_area;
    reg  [   `ME_STATE_REG_WIDTH-1:0] state;
    reg  [   `ME_STATE_REG_WIDTH-1:0] n_state;
    reg  [      `COLOR_RGB_DEPTH-1:0] vga_rgb;
    reg                               vga_alpha;


    assign x_pos_o = x_pos;
    assign y_pos_o = y_pos;


    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            displocked_y_pos <= 0;
        end else begin
            if(~v_sync_i) begin
                displocked_y_pos <= y_pos;
            end else begin
                displocked_y_pos <= displocked_y_pos;
            end
        end
    end

    always @(posedge clk_vga or posedge rst)begin
        if(rst) begin
            cnt_down <= 0;
        end else begin
            if(cnt_down == `ENEMY_CNT_MAX_DOWN - 1)begin
                state_change <= 1;
                cnt_down <= 0;
            end else begin
                state_change <= 0;
                cnt_down <= cnt_down + 1;
            end
        end
    end

    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            state <= STATE_N1;
        end else begin
            state <= n_state;
        end
    end


    assign in_req_area = en_i && (req_x_addr_i >= x_pos)
           && (req_x_addr_i < x_pos + `ME_X_SIZE)
           && (req_y_addr_i >= displocked_y_pos)
           && (req_y_addr_i < displocked_y_pos + `ME_Y_SIZE); 


    assign bram_clr = ~v_sync_i;
    always@(posedge clk_vga or posedge rst or posedge bram_clr) begin
        if(rst | bram_clr) begin
            bram_addr_cnt <= 0;
        end
        else begin
            if(in_req_area) begin
                bram_addr_cnt <= bram_addr_cnt + 1;
            end
            else begin
                bram_addr_cnt <= bram_addr_cnt;
            end
        end
    end

    assign {bram_alpha_1, bram_gray_1, bram_alpha_2, bram_gray_2,
             bram_alpha_destroy_1, bram_gray_destroy_1,
             bram_alpha_destroy_2,bram_gray_destroy_2}
             = bram_info;

    bram_me bram_me_dut
             (
                 .clka(clk_vga),
                 .ena(1'b1),
                 .addra(bram_addr_cnt),
                 .douta(bram_info)
             );
    
    assign vga_rgb_o = vga_rgb;
    assign vga_alpha_o = vga_alpha;

    always @(*) begin
        if(in_req_area) begin
            case(state)
                STATE_N1: begin
                    vga_alpha = bram_alpha_1;
                    vga_rgb   = {3{bram_gray_1}};
                end
                STATE_N2: begin
                    vga_alpha = bram_alpha_2;
                    vga_rgb   = {3{bram_gray_2}};
                end
                STATE_DOWN1: begin
                    vga_alpha = bram_alpha_destroy_1;
                    vga_rgb   = {3{bram_gray_destroy_1}};
                end
                STATE_DOWN2: begin
                    vga_alpha = bram_alpha_destroy_2;
                    vga_rgb   = {3{bram_gray_destroy_2}};
                end
                default: begin
                    vga_alpha = 0;
                    vga_rgb   = 0;
                end
            endcase
        end else begin
            vga_alpha = 0;
            vga_rgb   = 0;
        end
    end

    always @(*) begin
        case(state)
            STATE_N1 :
                n_state = crash_me_enemy_i ? STATE_DOWN1 : state_change ? STATE_N2 : STATE_N1;
            STATE_N2 :
                n_state = crash_me_enemy_i ? STATE_DOWN1 : state_change ? STATE_N1 : STATE_N2;
            STATE_DOWN1 :
                n_state = state_change ? STATE_DOWN2 : STATE_DOWN1;
            STATE_DOWN2:
                n_state = state_change ? STATE_UNVISUAL : STATE_DOWN2;
            STATE_UNVISUAL :
                n_state = STATE_UNVISUAL;
            default:
                n_state = STATE_N1;
        endcase
    end



    always @(posedge clk_run or posedge rst) begin
        if(rst) begin
            x_pos <= `ME_DEFAULT_X_POS;
            y_pos <= `ME_DEFAULT_Y_POS;
        end
        else begin
            if(en_i && move_en_i) begin
                case(direct_i)
                    `UP: begin
                        if(y_pos > UP_BOUND) begin
                            y_pos <= y_pos - SPEED;
                        end
                        else begin
                            y_pos <= y_pos;
                        end
                        x_pos <= x_pos;
                    end
                    `DOWN: begin
                        if(y_pos < DOWN_BOUND) begin
                            y_pos <= y_pos + SPEED;
                        end
                        else begin
                            y_pos <= y_pos;
                        end
                        x_pos <= x_pos;
                    end
                    `LEFT: begin
                        if(x_pos > LEFT_BOUND) begin
                            x_pos <= x_pos - SPEED;
                        end
                        else begin
                            x_pos <= x_pos;
                        end
                        y_pos <= y_pos;
                    end
                    `RIGHT: begin
                        if(x_pos < RIGHT_BOUND) begin
                            x_pos <= x_pos + SPEED;
                        end
                        else begin
                            x_pos <= x_pos;
                        end
                        y_pos <= y_pos;
                    end
                endcase
            end
            else begin
                x_pos <= x_pos;
                y_pos <= y_pos;
            end
        end
    end

endmodule