data/full_repos/permissive/489994352/Image-Part/getmax.v
data/verilator_xmls/ac0a4dbc-1bea-475d-ab54-6c70ed1c1694.xml
module getmax (a,b,z);
input [15:0] a,b;
output [15:0] z;

wire [15:0] c;
assign c = a-b;
assign z = (c[15]==1'b1)? b : a;


endmodule
module getmax (a,b,z);

input [15:0] a,b;
output [15:0] z;

wire [15:0] c;
assign c = a-b;
assign z = (c[15]==1'b1)? b : a;


endmodule