data/full_repos/permissive/509691520/CU_FSMplusD.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:28: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S0\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n   PS <= S0;\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n    NS = S1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:54: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n    NS = S2;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:62: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n    NS = S3;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:72: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n    NS = S4;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:78: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S0\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n    NS = S0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:81: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S0\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n   default: NS = S0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:39: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S0\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n  case(PS)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:39: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S1\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n  case(PS)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:39: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S2\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n  case(PS)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:39: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S3\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n  case(PS)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/509691520/CU_FSMplusD.v:39: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S4\' generates 3 bits.\n                                                                     : ... In instance CU_FSMplusD\n  case(PS)\n  ^~~~\n%Error: Exiting due to 12 warning(s)\n'
module CU_FSMplusD (
	input clock, reset,
	input [3:0] a, b, c, d, e,
	output reg [3:0] PS, NS,
	output reg [1:0] sel1, sel2, sel3, 
	output reg ldR1, ldR2, ldR3
);

	localparam	S0 = 3'b000,
					S1 = 3'b001,
					S2 = 3'b010,
					S3 = 3'b011,
					S4 = 3'b100;

	always @ (posedge clock, posedge reset)
	begin
		if (reset == 1'b1) begin
			sel1 <= 0;
			sel2 <= 0;
			sel3 <= 0;
			ldR1 <= 0;
			ldR2 <= 0;
			ldR3 <= 0;
			PS <= S0;
		end
		else begin
			PS <= NS;
		end
	end
	
	always @ (*)
	begin
		NS = PS;
		
		case(PS)
		
			S0: begin
				sel1 = 2'b11;
				sel2 = 2'b10;
				ldR1 = 1'b1;
				ldR2 = 1'b1;
				NS = S1;
			end
			
			S1: begin
				sel1 = 2'b10;
				sel3 = 2'b01;
				ldR1 = 1'b1;
				ldR3 = 1'b1;
				NS = S2;
			end
			
			S2: begin
				sel2 = 2'b01;
				sel3 = 2'b10;
				ldR2 = 1'b1;
				ldR3 = 1'b1;
				NS = S3;
			end
			
			S3: begin
				sel1 = 2'b01;
				sel2 = 2'b00;
				sel3 = 2'b00;
				ldR1 = 1'b1;
				ldR2 = 1'b1;
				ldR3 = 1'b1;
				NS = S4;
			end
			
			S4: begin
				sel1 = 2'b00;
				ldR1 = 1'b1;
				NS = S0;
			end
			
			default: NS = S0;
		endcase
	end

endmodule
module CU_FSMplusD (
	input clock, reset,
	input [3:0] a, b, c, d, e,
	output reg [3:0] PS, NS,
	output reg [1:0] sel1, sel2, sel3, 
	output reg ldR1, ldR2, ldR3
);


	localparam	S0 = 3'b000,
					S1 = 3'b001,
					S2 = 3'b010,
					S3 = 3'b011,
					S4 = 3'b100;

	always @ (posedge clock, posedge reset)
	begin
		if (reset == 1'b1) begin
			sel1 <= 0;
			sel2 <= 0;
			sel3 <= 0;
			ldR1 <= 0;
			ldR2 <= 0;
			ldR3 <= 0;
			PS <= S0;
		end
		else begin
			PS <= NS;
		end
	end
	
	always @ (*)
	begin
		NS = PS;
		
		case(PS)
		
			S0: begin
				sel1 = 2'b11;
				sel2 = 2'b10;
				ldR1 = 1'b1;
				ldR2 = 1'b1;
				NS = S1;
			end
			
			S1: begin
				sel1 = 2'b10;
				sel3 = 2'b01;
				ldR1 = 1'b1;
				ldR3 = 1'b1;
				NS = S2;
			end
			
			S2: begin
				sel2 = 2'b01;
				sel3 = 2'b10;
				ldR2 = 1'b1;
				ldR3 = 1'b1;
				NS = S3;
			end
			
			S3: begin
				sel1 = 2'b01;
				sel2 = 2'b00;
				sel3 = 2'b00;
				ldR1 = 1'b1;
				ldR2 = 1'b1;
				ldR3 = 1'b1;
				NS = S4;
			end
			
			S4: begin
				sel1 = 2'b00;
				ldR1 = 1'b1;
				NS = S0;
			end
			
			default: NS = S0;
		endcase
	end

endmodule