data/full_repos/permissive/493331294/uart/uart.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/493331294/uart/uart.v:156: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'UartTx\'\nmodule UartTx\n       ^~~~~~\n                                                                       : ... Top module \'UartRx\'\nmodule UartRx\n       ^~~~~~\n%Warning-REALCVT: data/full_repos/permissive/493331294/uart/uart.v:20: Implicit conversion of real to integer\n parameter integer uart_interval = CLOCK_FREQUENCY / BAUD;  \n                                                   ^\n%Warning-REALCVT: data/full_repos/permissive/493331294/uart/uart.v:176: Implicit conversion of real to integer\n parameter integer sampling_interval = CLOCK_FREQUENCY / BAUD / SAMPLE_SIZE;  \n                                                              ^\n%Warning-REALCVT: data/full_repos/permissive/493331294/uart/uart.v:179: Implicit conversion of real to integer\n parameter integer window_size_half = (SAMPLE_SIZE / 2.0);  \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:222: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sampling_clk_counter\' generates 7 bits.\n                                                                    : ... In instance UartRx\n assign sample_strobe = !sampling_clk_counter;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:226: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                    : ... In instance UartRx\n   sampling_clk_counter <= sampling_interval - 1\'d1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:230: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                    : ... In instance UartRx\n    sampling_clk_counter <= sampling_interval - 1\'d1;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:229: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sampling_clk_counter\' generates 7 bits.\n                                                                    : ... In instance UartRx\n   if (!sampling_clk_counter) begin\n       ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:239: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'uart_clk_counter\' generates 4 bits.\n                                                                    : ... In instance UartRx\n assign rx_strobe = !uart_clk_counter & sample_strobe;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:243: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                    : ... In instance UartRx\n   uart_clk_counter <= SAMPLE_SIZE - 1\'d1;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:248: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                    : ... In instance UartRx\n     uart_clk_counter <= window_size_half - 1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:252: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                    : ... In instance UartRx\n      uart_clk_counter <= SAMPLE_SIZE - 1\'d1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:251: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'uart_clk_counter\' generates 4 bits.\n                                                                    : ... In instance UartRx\n     if (!uart_clk_counter) begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:263: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'ones_count\' generates 5 bits.\n                                                                    : ... In instance UartRx\n assign rx_filtered = ones_count >= window_size_half;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:268: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance UartRx\n   sample_window <= 1\'d0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:269: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance UartRx\n   ones_count <= 1\'d0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:276: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'rx_sample\' generates 1 bits.\n                                                                    : ... In instance UartRx\n    ones_count <= ones_count + rx_sample - sample_window[SAMPLE_SIZE - 1];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:276: Operator SUB expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance UartRx\n    ones_count <= ones_count + rx_sample - sample_window[SAMPLE_SIZE - 1];\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:277: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                    : ... In instance UartRx\n    sample_window <= {sample_window, rx_sample};\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:291: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartRx\n   pos_rx_next = BUFFER_SIZE;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:290: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_rx\' generates 4 bits.\n                                                                    : ... In instance UartRx\n  if (!pos_rx) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:300: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartRx\n   pos_read <= BUFFER_SIZE;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:305: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartRx\n     pos_read <= BUFFER_SIZE;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:304: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_read\' generates 4 bits.\n                                                                    : ... In instance UartRx\n    if (!pos_read) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:321: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartRx\n   pos_rx <= BUFFER_SIZE;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:330: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartRx\n        pos_rx <= BUFFER_SIZE;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:329: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_rx\' generates 4 bits.\n                                                                    : ... In instance UartRx\n       if (!pos_rx) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:50: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'tx_clk_counter\' generates 11 bits.\n                                                                   : ... In instance UartTx\n assign tx_strobe = !tx_clk_counter;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:54: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                   : ... In instance UartTx\n   tx_clk_counter <= uart_interval - 1\'d1;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:58: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                   : ... In instance UartTx\n    tx_clk_counter <= 1\'d1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:62: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                   : ... In instance UartTx\n     tx_clk_counter <= uart_interval - 1\'d1;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:61: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'tx_clk_counter\' generates 11 bits.\n                                                                   : ... In instance UartTx\n    if (!tx_clk_counter) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:78: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                   : ... In instance UartTx\n   pos_write_next = BUFFER_SIZE;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:77: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_write\' generates 4 bits.\n                                                                   : ... In instance UartTx\n  if (!pos_write) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:87: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                   : ... In instance UartTx\n   pos_write <= BUFFER_SIZE;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:93: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                   : ... In instance UartTx\n     pos_write <= BUFFER_SIZE;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:92: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_write\' generates 4 bits.\n                                                                   : ... In instance UartTx\n    if (!pos_write) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartTx\n   pos_tx <= BUFFER_SIZE;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:115: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                    : ... In instance UartTx\n      TX <= buffer[pos_tx][uart_state];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:118: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'BUFFER_SIZE\' generates 32 bits.\n                                                                    : ... In instance UartTx\n       pos_tx <= BUFFER_SIZE;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:117: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos_tx\' generates 4 bits.\n                                                                    : ... In instance UartTx\n      if (!pos_tx) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/493331294/uart/uart.v:144: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                    : ... In instance UartTx\n      TX <= buffer[pos_tx][uart_state];\n                          ^\n%Error: Exiting due to 42 warning(s)\n'
module UartTx
#(
	parameter real CLOCK_FREQUENCY=100000000,
	parameter real BAUD=56000,
	parameter integer BUFFER_SIZE=8
)
(
	input RST,
	input CLK,
	input [7:0] DATA,
	input WRITE,

	output WRITE_READY,
	output reg TX
);
	

	

	parameter integer uart_interval = CLOCK_FREQUENCY / BAUD;
	

	parameter integer pos_reg_size = $clog2(BUFFER_SIZE + 1);
	
	
	

	

	reg [$clog2(uart_interval) - 1'd1:0] tx_clk_counter;
	wire tx_strobe;
	

	reg [7:0] buffer [0:BUFFER_SIZE];
	reg [pos_reg_size - 1:0] pos_write;
	reg [pos_reg_size - 1:0] pos_tx;
	reg [pos_reg_size - 1:0] pos_write_next;
	wire write_ready;
	wire tx_ready;
	

	reg [3:0] uart_state;
	wire waiting;






	assign tx_strobe = !tx_clk_counter;

	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			tx_clk_counter <= uart_interval - 1'd1;
		end
		else begin
			if (waiting) begin
				tx_clk_counter <= 1'd1;
			end
			else begin
				if (!tx_clk_counter) begin
					tx_clk_counter <= uart_interval - 1'd1;
				end
				else begin
					tx_clk_counter <= tx_clk_counter - 1'd1;
				end
			end
		end
	end
	

	assign write_ready = pos_write_next != pos_tx;
	assign tx_ready = pos_write != pos_tx;
	assign WRITE_READY = write_ready;
	
	always @(*) begin
		if (!pos_write) begin
			pos_write_next = BUFFER_SIZE;
		end
		else begin
			pos_write_next = pos_write - 1'd1;
		end
	end

	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			pos_write <= BUFFER_SIZE;
		end
		else begin
			if (write_ready & WRITE) begin
				buffer[pos_write] <= DATA;
				if (!pos_write) begin
					pos_write <= BUFFER_SIZE;
				end
				else begin
					pos_write <= pos_write - 1'd1;
				end
			end
		end
	end


	assign waiting = uart_state == 4'd9;
	
	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			uart_state <= 4'd8;
			pos_tx <= BUFFER_SIZE;
			TX <= 1'd1;
		end
		else begin
			case (uart_state)
				4'd7: begin
					if (tx_strobe) begin
						TX <= buffer[pos_tx][uart_state];
						uart_state <= 4'd8;
						if (!pos_tx) begin
							pos_tx <= BUFFER_SIZE;
						end
						else begin
							pos_tx <= pos_tx - 1'd1;
						end
					end
				end
				4'd8: begin
					if (tx_strobe) begin
						TX <= 1'd1;
						uart_state <= 4'd9;
					end
				end
				4'd9: begin
					if (tx_ready) begin
						uart_state <= 4'd10;
					end
				end
				4'd10: begin
					if (tx_strobe) begin
						TX <= 1'd0;
						uart_state <= 4'd0;
					end
				end
				default: begin
					if (tx_strobe) begin
						TX <= buffer[pos_tx][uart_state];
						uart_state <= uart_state + 1'd1;
					end
				end
			endcase
		end
	end

endmodule
module UartTx
#(
	parameter real CLOCK_FREQUENCY=100000000,
	parameter real BAUD=56000,
	parameter integer BUFFER_SIZE=8
)
(
	input RST,
	input CLK,
	input [7:0] DATA,
	input WRITE,

	output WRITE_READY,
	output reg TX
);

	

	

	parameter integer uart_interval = CLOCK_FREQUENCY / BAUD;
	

	parameter integer pos_reg_size = $clog2(BUFFER_SIZE + 1);
	
	
	

	

	reg [$clog2(uart_interval) - 1'd1:0] tx_clk_counter;
	wire tx_strobe;
	

	reg [7:0] buffer [0:BUFFER_SIZE];
	reg [pos_reg_size - 1:0] pos_write;
	reg [pos_reg_size - 1:0] pos_tx;
	reg [pos_reg_size - 1:0] pos_write_next;
	wire write_ready;
	wire tx_ready;
	

	reg [3:0] uart_state;
	wire waiting;






	assign tx_strobe = !tx_clk_counter;

	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			tx_clk_counter <= uart_interval - 1'd1;
		end
		else begin
			if (waiting) begin
				tx_clk_counter <= 1'd1;
			end
			else begin
				if (!tx_clk_counter) begin
					tx_clk_counter <= uart_interval - 1'd1;
				end
				else begin
					tx_clk_counter <= tx_clk_counter - 1'd1;
				end
			end
		end
	end
	

	assign write_ready = pos_write_next != pos_tx;
	assign tx_ready = pos_write != pos_tx;
	assign WRITE_READY = write_ready;
	
	always @(*) begin
		if (!pos_write) begin
			pos_write_next = BUFFER_SIZE;
		end
		else begin
			pos_write_next = pos_write - 1'd1;
		end
	end

	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			pos_write <= BUFFER_SIZE;
		end
		else begin
			if (write_ready & WRITE) begin
				buffer[pos_write] <= DATA;
				if (!pos_write) begin
					pos_write <= BUFFER_SIZE;
				end
				else begin
					pos_write <= pos_write - 1'd1;
				end
			end
		end
	end


	assign waiting = uart_state == 4'd9;
	
	always @(posedge CLK or posedge RST) begin
		if (RST) begin
			uart_state <= 4'd8;
			pos_tx <= BUFFER_SIZE;
			TX <= 1'd1;
		end
		else begin
			case (uart_state)
				4'd7: begin
					if (tx_strobe) begin
						TX <= buffer[pos_tx][uart_state];
						uart_state <= 4'd8;
						if (!pos_tx) begin
							pos_tx <= BUFFER_SIZE;
						end
						else begin
							pos_tx <= pos_tx - 1'd1;
						end
					end
				end
				4'd8: begin
					if (tx_strobe) begin
						TX <= 1'd1;
						uart_state <= 4'd9;
					end
				end
				4'd9: begin
					if (tx_ready) begin
						uart_state <= 4'd10;
					end
				end
				4'd10: begin
					if (tx_strobe) begin
						TX <= 1'd0;
						uart_state <= 4'd0;
					end
				end
				default: begin
					if (tx_strobe) begin
						TX <= buffer[pos_tx][uart_state];
						uart_state <= uart_state + 1'd1;
					end
				end
			endcase
		end
	end

endmodule