data/full_repos/permissive/518305321/iiitb_sipo_net.v
1: b"%Error: data/full_repos/permissive/518305321/iiitb_sipo_net.v:40: Can't resolve module reference: 'sky130_fd_sc_hd__nor2b_1'\n  sky130_fd_sc_hd__nor2b_1 _16_ (\n                           ^~~~\n%Error: Exiting due to 1 error(s)\n"
module iiitb_sipo(d, rst, clk, q);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire \aa.clk ;
  wire \aa.d ;
  wire \aa.q ;
  wire \aa.rst ;
  wire \bb.clk ;
  wire \bb.d ;
  wire \bb.q ;
  wire \bb.rst ;
  wire \cc.clk ;
  wire \cc.d ;
  wire \cc.q ;
  wire \cc.rst ;
  input clk;
  input d;
  wire \dd.clk ;
  wire \dd.d ;
  wire \dd.q ;
  wire \dd.rst ;
  output [3:0] q;
  input rst;
  sky130_fd_sc_hd__nor2b_1 _16_ (
    .A(_03_),
    .B_N(_02_),
    .Y(_01_)
  );
  sky130_fd_sc_hd__dfxtp_1 _17_ (
    .CLK(\aa.clk ),
    .D(_00_),
    .Q(\aa.q )
  );
  sky130_fd_sc_hd__nor2b_1 _18_ (
    .A(_07_),
    .B_N(_06_),
    .Y(_05_)
  );
  sky130_fd_sc_hd__dfxtp_1 _19_ (
    .CLK(\bb.clk ),
    .D(_04_),
    .Q(\bb.q )
  );
  sky130_fd_sc_hd__nor2b_1 _20_ (
    .A(_11_),
    .B_N(_10_),
    .Y(_09_)
  );
  sky130_fd_sc_hd__dfxtp_1 _21_ (
    .CLK(\cc.clk ),
    .D(_08_),
    .Q(\cc.q )
  );
  sky130_fd_sc_hd__nor2b_1 _22_ (
    .A(_15_),
    .B_N(_14_),
    .Y(_13_)
  );
  sky130_fd_sc_hd__dfxtp_1 _23_ (
    .CLK(\dd.clk ),
    .D(_12_),
    .Q(\dd.q )
  );
  assign \aa.clk  = clk;
  assign \aa.d  = d;
  assign q[3] = \aa.q ;
  assign \aa.rst  = rst;
  assign _02_ = \aa.d ;
  assign _03_ = \aa.rst ;
  assign _00_ = _01_;
  assign \bb.clk  = clk;
  assign \bb.d  = q[3];
  assign q[2] = \bb.q ;
  assign \bb.rst  = rst;
  assign _06_ = \bb.d ;
  assign _07_ = \bb.rst ;
  assign _04_ = _05_;
  assign \cc.clk  = clk;
  assign \cc.d  = q[2];
  assign q[1] = \cc.q ;
  assign \cc.rst  = rst;
  assign _10_ = \cc.d ;
  assign _11_ = \cc.rst ;
  assign _08_ = _09_;
  assign \dd.clk  = clk;
  assign \dd.d  = q[1];
  assign q[0] = \dd.q ;
  assign \dd.rst  = rst;
  assign _14_ = \dd.d ;
  assign _15_ = \dd.rst ;
  assign _12_ = _13_;
endmodule
module iiitb_sipo(d, rst, clk, q);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire \aa.clk ;
  wire \aa.d ;
  wire \aa.q ;
  wire \aa.rst ;
  wire \bb.clk ;
  wire \bb.d ;
  wire \bb.q ;
  wire \bb.rst ;
  wire \cc.clk ;
  wire \cc.d ;
  wire \cc.q ;
  wire \cc.rst ;
  input clk;
  input d;
  wire \dd.clk ;
  wire \dd.d ;
  wire \dd.q ;
  wire \dd.rst ;
  output [3:0] q;
  input rst;
  sky130_fd_sc_hd__nor2b_1 _16_ (
    .A(_03_),
    .B_N(_02_),
    .Y(_01_)
  );
  sky130_fd_sc_hd__dfxtp_1 _17_ (
    .CLK(\aa.clk ),
    .D(_00_),
    .Q(\aa.q )
  );
  sky130_fd_sc_hd__nor2b_1 _18_ (
    .A(_07_),
    .B_N(_06_),
    .Y(_05_)
  );
  sky130_fd_sc_hd__dfxtp_1 _19_ (
    .CLK(\bb.clk ),
    .D(_04_),
    .Q(\bb.q )
  );
  sky130_fd_sc_hd__nor2b_1 _20_ (
    .A(_11_),
    .B_N(_10_),
    .Y(_09_)
  );
  sky130_fd_sc_hd__dfxtp_1 _21_ (
    .CLK(\cc.clk ),
    .D(_08_),
    .Q(\cc.q )
  );
  sky130_fd_sc_hd__nor2b_1 _22_ (
    .A(_15_),
    .B_N(_14_),
    .Y(_13_)
  );
  sky130_fd_sc_hd__dfxtp_1 _23_ (
    .CLK(\dd.clk ),
    .D(_12_),
    .Q(\dd.q )
  );
  assign \aa.clk  = clk;
  assign \aa.d  = d;
  assign q[3] = \aa.q ;
  assign \aa.rst  = rst;
  assign _02_ = \aa.d ;
  assign _03_ = \aa.rst ;
  assign _00_ = _01_;
  assign \bb.clk  = clk;
  assign \bb.d  = q[3];
  assign q[2] = \bb.q ;
  assign \bb.rst  = rst;
  assign _06_ = \bb.d ;
  assign _07_ = \bb.rst ;
  assign _04_ = _05_;
  assign \cc.clk  = clk;
  assign \cc.d  = q[2];
  assign q[1] = \cc.q ;
  assign \cc.rst  = rst;
  assign _10_ = \cc.d ;
  assign _11_ = \cc.rst ;
  assign _08_ = _09_;
  assign \dd.clk  = clk;
  assign \dd.d  = q[1];
  assign q[0] = \dd.q ;
  assign \dd.rst  = rst;
  assign _14_ = \dd.d ;
  assign _15_ = \dd.rst ;
  assign _12_ = _13_;
endmodule