data/full_repos/permissive/479094658/RCA8_testbench.v
1: b'%Error: data/full_repos/permissive/479094658/RCA8_testbench.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " a=%d, b=%d, sub=%b, z=%d, Cout=%b, ",a,b,sub,z,Cout);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479094658/RCA8_testbench.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, RCA8_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA8_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #0  sub=0; a=8\'h00; b=8\'h00;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA8_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #50 a <= a + 2; b <= b + 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA8_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #50 sub=1; a=8\'h00; b=8\'h00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA8_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #50 a <= a + 2; b <= b + 1;\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RCA8_testbench();
  
  reg [7:0] a, b;
  reg sub;
  wire [7:0] z;    
  wire Cout;
  
  RCA8 DUT ( .a(a), .b(b), .sub(sub), .z(z), .Cout(Cout));
  
  initial
  begin
    $monitor($time, " a=%d, b=%d, sub=%b, z=%d, Cout=%b, ",a,b,sub,z,Cout);
  end
  
  initial
  begin
    $dumpvars(1, RCA8_testbench);
    #0  sub=0; a=8'h00; b=8'h00;
    repeat (31)
    begin
      #50 a <= a + 2; b <= b + 1;
    end
    
    #50 sub=1; a=8'h00; b=8'h00;
    
    repeat (31)
    begin
      #50 a <= a + 2; b <= b + 1;
    end
  end
  
endmodule
module RCA8_testbench();

  
  reg [7:0] a, b;
  reg sub;
  wire [7:0] z;    
  wire Cout;
  
  RCA8 DUT ( .a(a), .b(b), .sub(sub), .z(z), .Cout(Cout));
  
  initial
  begin
    $monitor($time, " a=%d, b=%d, sub=%b, z=%d, Cout=%b, ",a,b,sub,z,Cout);
  end
  
  initial
  begin
    $dumpvars(1, RCA8_testbench);
    #0  sub=0; a=8'h00; b=8'h00;
    repeat (31)
    begin
      #50 a <= a + 2; b <= b + 1;
    end
    
    #50 sub=1; a=8'h00; b=8'h00;
    
    repeat (31)
    begin
      #50 a <= a + 2; b <= b + 1;
    end
  end
  
endmodule