data/full_repos/permissive/422139337/src/vga_interface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:46: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                           : ... In instance vga_interface\n       red=din[15:11]<<3;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:47: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 6 bits.\n                                                                           : ... In instance vga_interface\n       green=din[10:5]<<2;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:48: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                           : ... In instance vga_interface\n       blue=din[4:0]<<3;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:53: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                           : ... In instance vga_interface\n       red=din[15:11]<<3;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:54: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 6 bits.\n                                                                           : ... In instance vga_interface\n       green=din[10:5]<<2;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/vga_interface.v:55: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                           : ... In instance vga_interface\n       blue=din[4:0]<<3;\n                    ^~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:74: Cannot find file containing module: \'ODDRX1F\'\n  ODDRX1F ddr0_clock (.D0(tmds_clk   [0] ), .D1(tmds_clk   [1] ), .Q(gpdi_dp[3]), .SCLK(clk_5x), .RST(0));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/ODDRX1F\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/ODDRX1F.v\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/ODDRX1F.sv\n             ODDRX1F\n             ODDRX1F.v\n             ODDRX1F.sv\n             obj_dir/ODDRX1F\n             obj_dir/ODDRX1F.v\n             obj_dir/ODDRX1F.sv\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:75: Cannot find file containing module: \'ODDRX1F\'\n        ODDRX1F ddr0_red   (.D0(tmds_red   [0] ), .D1(tmds_red   [1] ), .Q(gpdi_dp[2]), .SCLK(clk_5x), .RST(0));\n        ^~~~~~~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:76: Cannot find file containing module: \'ODDRX1F\'\n        ODDRX1F ddr0_green (.D0(tmds_green [0] ), .D1(tmds_green [1] ), .Q(gpdi_dp[1]), .SCLK(clk_5x), .RST(0));\n        ^~~~~~~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:77: Cannot find file containing module: \'ODDRX1F\'\n        ODDRX1F ddr0_blue  (.D0(tmds_blue  [0] ), .D1(tmds_blue  [1] ), .Q(gpdi_dp[0]), .SCLK(clk_5x), .RST(0));\n        ^~~~~~~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:82: Cannot find file containing module: \'pll_HDMI\'\n pll_HDMI m0\n ^~~~~~~~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:89: Cannot find file containing module: \'my_vga_clk_generator\'\n my_vga_clk_generator m1\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422139337/src/vga_interface.v:100: Cannot find file containing module: \'hdmi_device\'\n hdmi_device #(.DDR_ENABLED(1\'b1)) m2\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 6 warning(s)\n'
module vga_interface(
	input wire clk,rst_n,

	input wire empty_fifo,
	input wire[15:0] din,
	output wire clk_vga,
	output reg rd_en,

	output [3:0] gpdi_dp
    );

	 localparam delay=0,
					idle=1,
					display=2;
					
	 reg[1:0] state_q,state_d;
	 wire[11:0] pixel_x,pixel_y;
	 reg[7:0] red,green,blue;
	 wire hsync,vsync,blank;
	 wire[1:0] tmds_red,tmds_green,tmds_blue,tmds_clk;
	 wire clk_5x;
	 

	 always @(posedge clk_vga,negedge rst_n) begin
		if(!rst_n) begin
			state_q<=delay;
		end
		else begin
			state_q<=state_d;
		end
	 end
	 

	 always @* begin
	 state_d=state_q;
	 rd_en=0;
	 red=0;
	 green=0;
	 blue=0;
			
		case(state_q)
		  delay: if(pixel_x==640 && pixel_y==480) state_d=idle;
			idle:  if(pixel_x==0 && pixel_y==0 && !empty_fifo) begin
							red=din[15:11]<<3;
							green=din[10:5]<<2;
							blue=din[4:0]<<3;
							rd_en=1;	
							state_d=display;
					end
		display: if(!blank) begin
							red=din[15:11]<<3;
							green=din[10:5]<<2;
							blue=din[4:0]<<3;
							rd_en=1;	
					end
		default: state_d=delay;
		endcase


	 end
 
	

		ODDRX1F ddr0_clock (.D0(tmds_clk   [0] ), .D1(tmds_clk   [1] ), .Q(gpdi_dp[3]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_red   (.D0(tmds_red   [0] ), .D1(tmds_red   [1] ), .Q(gpdi_dp[2]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_green (.D0(tmds_green [0] ), .D1(tmds_green [1] ), .Q(gpdi_dp[1]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_blue  (.D0(tmds_blue  [0] ), .D1(tmds_blue  [1] ), .Q(gpdi_dp[0]), .SCLK(clk_5x), .RST(0));
		
		
		

	pll_HDMI m0
		(
			.clkin(clk),
			.clkout0(clk_5x),
			.clkout1(clk_vga)
		);

	my_vga_clk_generator m1
		(
		   .pclk(clk_vga), 
		   .out_hsync(hsync), 
		   .out_vsync(vsync),
		   .out_blank(blank),
		   .out_hcnt(pixel_x),
		   .out_vcnt(pixel_y),
		   .reset_n(1'b1)
		);

	hdmi_device #(.DDR_ENABLED(1'b1)) m2
		(
			   .pclk(clk_vga),
			   .tmds_clk(clk_5x),

			   .in_vga_red(red),
			   .in_vga_green(green),
			   .in_vga_blue(blue),

			   .in_vga_blank(blank),
			   .in_vga_vsync(vsync),
			   .in_vga_hsync(hsync),

			   .out_tmds_red(tmds_red),
			   .out_tmds_green(tmds_green),
			   .out_tmds_blue(tmds_blue),
			   .out_tmds_clk(tmds_clk)
		   );
	 
endmodule
module vga_interface(
	input wire clk,rst_n,

	input wire empty_fifo,
	input wire[15:0] din,
	output wire clk_vga,
	output reg rd_en,

	output [3:0] gpdi_dp
    );


	 localparam delay=0,
					idle=1,
					display=2;
					
	 reg[1:0] state_q,state_d;
	 wire[11:0] pixel_x,pixel_y;
	 reg[7:0] red,green,blue;
	 wire hsync,vsync,blank;
	 wire[1:0] tmds_red,tmds_green,tmds_blue,tmds_clk;
	 wire clk_5x;
	 

	 always @(posedge clk_vga,negedge rst_n) begin
		if(!rst_n) begin
			state_q<=delay;
		end
		else begin
			state_q<=state_d;
		end
	 end
	 

	 always @* begin
	 state_d=state_q;
	 rd_en=0;
	 red=0;
	 green=0;
	 blue=0;
			
		case(state_q)
		  delay: if(pixel_x==640 && pixel_y==480) state_d=idle;
			idle:  if(pixel_x==0 && pixel_y==0 && !empty_fifo) begin
							red=din[15:11]<<3;
							green=din[10:5]<<2;
							blue=din[4:0]<<3;
							rd_en=1;	
							state_d=display;
					end
		display: if(!blank) begin
							red=din[15:11]<<3;
							green=din[10:5]<<2;
							blue=din[4:0]<<3;
							rd_en=1;	
					end
		default: state_d=delay;
		endcase


	 end
 
	

		ODDRX1F ddr0_clock (.D0(tmds_clk   [0] ), .D1(tmds_clk   [1] ), .Q(gpdi_dp[3]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_red   (.D0(tmds_red   [0] ), .D1(tmds_red   [1] ), .Q(gpdi_dp[2]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_green (.D0(tmds_green [0] ), .D1(tmds_green [1] ), .Q(gpdi_dp[1]), .SCLK(clk_5x), .RST(0));
        ODDRX1F ddr0_blue  (.D0(tmds_blue  [0] ), .D1(tmds_blue  [1] ), .Q(gpdi_dp[0]), .SCLK(clk_5x), .RST(0));
		
		
		

	pll_HDMI m0
		(
			.clkin(clk),
			.clkout0(clk_5x),
			.clkout1(clk_vga)
		);

	my_vga_clk_generator m1
		(
		   .pclk(clk_vga), 
		   .out_hsync(hsync), 
		   .out_vsync(vsync),
		   .out_blank(blank),
		   .out_hcnt(pixel_x),
		   .out_vcnt(pixel_y),
		   .reset_n(1'b1)
		);

	hdmi_device #(.DDR_ENABLED(1'b1)) m2
		(
			   .pclk(clk_vga),
			   .tmds_clk(clk_5x),

			   .in_vga_red(red),
			   .in_vga_green(green),
			   .in_vga_blue(blue),

			   .in_vga_blank(blank),
			   .in_vga_vsync(vsync),
			   .in_vga_hsync(hsync),

			   .out_tmds_red(tmds_red),
			   .out_tmds_green(tmds_green),
			   .out_tmds_blue(tmds_blue),
			   .out_tmds_clk(tmds_clk)
		   );
	 
endmodule