data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD*DUTY_CYCLE);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #OFFSET\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n%Error: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:78: syntax error, unexpected \'@\'\n  @(*)begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/43856783/crc_7/crc_7_testbench.v:85: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module crc_7_testbench;


	reg start;
	reg rst;
	reg clk;
	reg [31:0] data_in;


	wire [7:0] data_out;
	wire done;


	parameter PERIOD          = 10;
   	parameter real DUTY_CYCLE = 0.5;
   	parameter OFFSET          = 0;


	crc_7 uut (
		.start(start), 
		.rst(rst),
		.clk(clk), 
		.data_in(data_in), 
		.data_out(data_out), 
		.done(done)
	);

	initial begin

		start = 0;
		clk = 0;
		rst = 1;
		data_in = 0;
	 #OFFSET


	
    	 forever
			begin
				clk = 1'b1;
				#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
				#(PERIOD*DUTY_CYCLE);
			end	
	end
		
	initial begin

		#10;
       		  rst=0;
		  start=1;
		  data_in=32'h00A2E015;
		#10; 
			start=0;
		@(*)begin
			if (done) begin
				#10
					rst=1;
				#10
					rst=0;
			end
		end
	end
      
endmodule
module crc_7_testbench;



	reg start;
	reg rst;
	reg clk;
	reg [31:0] data_in;


	wire [7:0] data_out;
	wire done;


	parameter PERIOD          = 10;
   	parameter real DUTY_CYCLE = 0.5;
   	parameter OFFSET          = 0;


	crc_7 uut (
		.start(start), 
		.rst(rst),
		.clk(clk), 
		.data_in(data_in), 
		.data_out(data_out), 
		.done(done)
	);

	initial begin

		start = 0;
		clk = 0;
		rst = 1;
		data_in = 0;
	 #OFFSET


	
    	 forever
			begin
				clk = 1'b1;
				#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
				#(PERIOD*DUTY_CYCLE);
			end	
	end
		
	initial begin

		#10;
       		  rst=0;
		  start=1;
		  data_in=32'h00A2E015;
		#10; 
			start=0;
		@(*)begin
			if (done) begin
				#10
					rst=1;
				#10
					rst=0;
			end
		end
	end
      
endmodule