data/full_repos/permissive/472469504/src/Data_Memory.v
1: b'%Error: data/full_repos/permissive/472469504/src/Data_Memory.v:30: Extracting 14 bits from only 8 bit number\n                                                                 : ... In instance Data_Memory\nassign real_address = {2\'b0, Address_i[15:2]};\n                                      ^\n%Warning-SELRANGE: data/full_repos/permissive/472469504/src/Data_Memory.v:30: Selection index out of range: 15:2 outside 7:0\n                                                                            : ... In instance Data_Memory\nassign real_address = {2\'b0, Address_i[15:2]};\n                                      ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472469504/src/Data_Memory.v:30: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                         : ... In instance Data_Memory\nassign real_address = {2\'b0, Address_i[15:2]};\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/472469504/src/Data_Memory.v:40: Bit extraction of array[1023:0] requires 10 bit index, not 8 bits.\n                                                                         : ... In instance Data_Memory\n   ram[real_address] <= Write_Data_i;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/472469504/src/Data_Memory.v:43: Bit extraction of array[1023:0] requires 10 bit index, not 8 bits.\n                                                                         : ... In instance Data_Memory\n assign read_data_aux = ram[real_address];\n                           ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module Data_Memory 
#(	parameter DATA_WIDTH = 8,
	parameter MEMORY_DEPTH = 1024

)
(
	input clk,
	input Mem_Write_i,
	input Mem_Read_i,
	input [DATA_WIDTH-1:0] Write_Data_i,
	input [DATA_WIDTH-1:0]  Address_i,

	output  [DATA_WIDTH-1:0]  Read_Data_o
);
	
wire [DATA_WIDTH-1 : 0] real_address;	

assign real_address = {2'b0, Address_i[15:2]};
	

	reg [DATA_WIDTH-1:0] ram[MEMORY_DEPTH-1:0];
	wire [DATA_WIDTH-1:0] read_data_aux;

	always @ (posedge clk)
	begin

		if (Mem_Write_i)
			ram[real_address] <= Write_Data_i;
	end
	
	assign read_data_aux = ram[real_address];
	
  	assign Read_Data_o = { DATA_WIDTH { Mem_Read_i } } & read_data_aux;

endmodule
module Data_Memory 
#(	parameter DATA_WIDTH = 8,
	parameter MEMORY_DEPTH = 1024

)
(
	input clk,
	input Mem_Write_i,
	input Mem_Read_i,
	input [DATA_WIDTH-1:0] Write_Data_i,
	input [DATA_WIDTH-1:0]  Address_i,

	output  [DATA_WIDTH-1:0]  Read_Data_o
);

	
wire [DATA_WIDTH-1 : 0] real_address;	

assign real_address = {2'b0, Address_i[15:2]};
	

	reg [DATA_WIDTH-1:0] ram[MEMORY_DEPTH-1:0];
	wire [DATA_WIDTH-1:0] read_data_aux;

	always @ (posedge clk)
	begin

		if (Mem_Write_i)
			ram[real_address] <= Write_Data_i;
	end
	
	assign read_data_aux = ram[real_address];
	
  	assign Read_Data_o = { DATA_WIDTH { Mem_Read_i } } & read_data_aux;

endmodule