data/full_repos/permissive/439731184/example_assign.v
1: b'%Error: data/full_repos/permissive/439731184/example_assign.v:16: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b\\t%b\\t%b", a, b, c, d, y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_assign.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_assign.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #1 a = a + 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_assign.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #2 b = b + 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_assign.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways #3 c = c + 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_assign.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #4 d = d + 1;\n       ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module example_assign();

parameter N_BITS=4;

reg [N_BITS-1:0] a, b, c, d;
wire [N_BITS-1:0] y;

assign y = (a&b) | (c^d);

initial begin
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    $display("a\tb\tc\td\ty");
    $monitor("%b\t%b\t%b\t%b\t%b", a, b, c, d, y);
    #100 $finish;
end

always #1 a = a + 1;
always #2 b = b + 1;
always #3 c = c + 1;
always #4 d = d + 1;

endmodule
module example_assign();


parameter N_BITS=4;

reg [N_BITS-1:0] a, b, c, d;
wire [N_BITS-1:0] y;

assign y = (a&b) | (c^d);

initial begin
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    $display("a\tb\tc\td\ty");
    $monitor("%b\t%b\t%b\t%b\t%b", a, b, c, d, y);
    #100 $finish;
end

always #1 a = a + 1;
always #2 b = b + 1;
always #3 c = c + 1;
always #4 d = d + 1;

endmodule