data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder/ripple_carry_adder_Nb.v
1: b"%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder/ripple_carry_adder_Nb.v:52: Cannot find file containing module: 'full_adder_1b'\nfull_adder_1b FA_1b_0(opa_i[0], b_mod[0], carry[0], res_o[0], carry[1]);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder,data/full_repos/permissive/522553437/full_adder_1b\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder,data/full_repos/permissive/522553437/full_adder_1b.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder,data/full_repos/permissive/522553437/full_adder_1b.sv\n             full_adder_1b\n             full_adder_1b.v\n             full_adder_1b.sv\n             obj_dir/full_adder_1b\n             obj_dir/full_adder_1b.v\n             obj_dir/full_adder_1b.sv\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/adder/ripple_carry_adder_Nb.v:56: Cannot find file containing module: 'full_adder_1b'\n full_adder_1b FA_1b(opa_i[i], b_mod[i], carry[i], res_o[i], carry[i+1]);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ripple_carry_adder_Nb #(parameter N = 32) (
	input  carry_i,
	input  [N-1:0] opa_i,
	input  [N-1:0] opb_i,
	input  inv_b_i,
	output [N-1:0] res_o,
	output carry_o
);

wire [N:0] carry;
wire [N-1:0] b_mod;





assign b_mod  = (inv_b_i)?(~opb_i):opb_i;
assign carry[0] = (inv_b_i)?(~carry_i):carry_i;
assign carry_o = carry[N];

full_adder_1b FA_1b_0(opa_i[0], b_mod[0], carry[0], res_o[0], carry[1]);
genvar i;
generate
for (i = 1; i < N; i = i + 1) begin
	full_adder_1b FA_1b(opa_i[i], b_mod[i], carry[i], res_o[i], carry[i+1]);
end
endgenerate

endmodule
module ripple_carry_adder_Nb #(parameter N = 32) (
	input  carry_i,
	input  [N-1:0] opa_i,
	input  [N-1:0] opb_i,
	input  inv_b_i,
	output [N-1:0] res_o,
	output carry_o
);


wire [N:0] carry;
wire [N-1:0] b_mod;





assign b_mod  = (inv_b_i)?(~opb_i):opb_i;
assign carry[0] = (inv_b_i)?(~carry_i):carry_i;
assign carry_o = carry[N];

full_adder_1b FA_1b_0(opa_i[0], b_mod[0], carry[0], res_o[0], carry[1]);
genvar i;
generate
for (i = 1; i < N; i = i + 1) begin
	full_adder_1b FA_1b(opa_i[i], b_mod[i], carry[i], res_o[i], carry[i+1]);
end
endgenerate

endmodule