data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v
1: b'%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:2: Cannot find include file: ./global.vh\n`include "./global.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.sv\n             ./global.vh\n             ./global.vh.v\n             ./global.vh.sv\n             obj_dir/./global.vh\n             obj_dir/./global.vh.v\n             obj_dir/./global.vh.sv\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:35: Define or directive not defined: \'`RS_UP\'\n            `RS_UP:    seg = 8\'b0110_0011;\n            ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:35: syntax error, unexpected \':\', expecting endcase\n            `RS_UP:    seg = 8\'b0110_0011;\n                  ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:36: Define or directive not defined: \'`RS_DOWN\'\n            `RS_DOWN:  seg = 8\'b0101_1100;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:37: Define or directive not defined: \'`RS_STOP\'\n            `RS_STOP:  seg = 8\'b0100_0000;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:38: Define or directive not defined: \'`DS_OPEN\'\n            `DS_OPEN:  seg = 8\'b0011_0110;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:39: Define or directive not defined: \'`DS_CLOSE\'\n            `DS_CLOSE: seg = 8\'b0111_1111;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/signal_segMsg.v:40: Define or directive not defined: \'`INVALID\'\n            `INVALID:  seg = 8\'b0100_0000;\n            ^~~~~~~~\n%Error: Cannot continue\n'
module signal_segMsg (
    input clk380hz,
    input [15:0] dataBus,
    output reg [3:0] pos,
    output reg [7:0] seg 
);
    reg [2:0] posC;
    reg [3:0] dataP;
    always @(posedge clk380hz) begin
        case (posC)
            0: begin
                pos <= 4'b0001;
                dataP <= dataBus[3:0];
            end
            1: begin
                pos <= 4'b0010;
                dataP <= dataBus[7:4];
            end
            2: begin
                pos <= 4'b0100;
                dataP <= dataBus[11:8];
            end
            3: begin
                pos <= 4'b1000;
                dataP <= dataBus[15:12];
            end
        endcase
        posC = posC + 1;
    end

    always @(dataP) begin
        case (dataP)
            `RS_UP:    seg = 8'b0110_0011;
            `RS_DOWN:  seg = 8'b0101_1100;
            `RS_STOP:  seg = 8'b0100_0000;
            `DS_OPEN:  seg = 8'b0011_0110;
            `DS_CLOSE: seg = 8'b0111_1111;
            `INVALID:  seg = 8'b0100_0000;
            default:   seg = 8'b0100_0000;
        endcase
    end
endmodule
module signal_segMsg (
    input clk380hz,
    input [15:0] dataBus,
    output reg [3:0] pos,
    output reg [7:0] seg 
);

    reg [2:0] posC;
    reg [3:0] dataP;
    always @(posedge clk380hz) begin
        case (posC)
            0: begin
                pos <= 4'b0001;
                dataP <= dataBus[3:0];
            end
            1: begin
                pos <= 4'b0010;
                dataP <= dataBus[7:4];
            end
            2: begin
                pos <= 4'b0100;
                dataP <= dataBus[11:8];
            end
            3: begin
                pos <= 4'b1000;
                dataP <= dataBus[15:12];
            end
        endcase
        posC = posC + 1;
    end

    always @(dataP) begin
        case (dataP)
            `RS_UP:    seg = 8'b0110_0011;
            `RS_DOWN:  seg = 8'b0101_1100;
            `RS_STOP:  seg = 8'b0100_0000;
            `DS_OPEN:  seg = 8'b0011_0110;
            `DS_CLOSE: seg = 8'b0111_1111;
            `INVALID:  seg = 8'b0100_0000;
            default:   seg = 8'b0100_0000;
        endcase
    end
endmodule