data/full_repos/permissive/418819021/lab-04/rom.v
data/verilator_xmls/a022f80a-bba4-4073-b8ba-b64ae145e389.xml
module rom #(
        parameter   DATA_WIDTH = 16,
        parameter   ADDR_WIDTH = 8
    )(
        input  wire                  clk,
        input  wire [ADDR_WIDTH-1:0] addr,
        output  reg [DATA_WIDTH-1:0] data
    );

    reg [DATA_WIDTH-1:0] value;

    
    always @* begin
        case (addr)
		  

			

		

		0:	value = 16'b1110000000000101;
		

		1:		value = 16'b1110000000011111;
		

		2:		value = 16'b1001001100001111;
		

		3:		value = 16'b1001001100011111;
		

		4:		value = 16'b0010111111100000;
		

		5:		value = 16'b0001101111100001;
		

		6:		value = 16'b1111000000101001;
		

		7:		value = 16'b1111000000010010;
		

		8:		value = 16'b0001101100000001;
		

		9:		value = 16'b1100111111111010;
		

		10:		value = 16'b0001101100010000;
		

		11:		value = 16'b1100111111111000;
		

		12:		value = 16'b1001001100001111;
		

		13:		value = 16'b1001000101001111;
		

		14:		value = 16'b1001000101011111;
		

		15:		value = 16'b1001000101101111;
		
		default:		value = 16'b0000000000000000;


        endcase
    end

    always @(negedge clk) begin
        data <= value;
    end

endmodule
module rom #(
        parameter   DATA_WIDTH = 16,
        parameter   ADDR_WIDTH = 8
    )(
        input  wire                  clk,
        input  wire [ADDR_WIDTH-1:0] addr,
        output  reg [DATA_WIDTH-1:0] data
    );


    reg [DATA_WIDTH-1:0] value;

    
    always @* begin
        case (addr)
		  

			

		

		0:	value = 16'b1110000000000101;
		

		1:		value = 16'b1110000000011111;
		

		2:		value = 16'b1001001100001111;
		

		3:		value = 16'b1001001100011111;
		

		4:		value = 16'b0010111111100000;
		

		5:		value = 16'b0001101111100001;
		

		6:		value = 16'b1111000000101001;
		

		7:		value = 16'b1111000000010010;
		

		8:		value = 16'b0001101100000001;
		

		9:		value = 16'b1100111111111010;
		

		10:		value = 16'b0001101100010000;
		

		11:		value = 16'b1100111111111000;
		

		12:		value = 16'b1001001100001111;
		

		13:		value = 16'b1001000101001111;
		

		14:		value = 16'b1001000101011111;
		

		15:		value = 16'b1001000101101111;
		
		default:		value = 16'b0000000000000000;


        endcase
    end

    always @(negedge clk) begin
        data <= value;
    end

endmodule