data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD_tb.v:2: Cannot find include file: Fo_B_ADD.v\n `include "Fo_B_ADD.v" \n          ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/Fo_B_ADD.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/Fo_B_ADD.v.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/Fo_B_ADD.v.sv\n             Fo_B_ADD.v\n             Fo_B_ADD.v.v\n             Fo_B_ADD.v.sv\n             obj_dir/Fo_B_ADD.v\n             obj_dir/Fo_B_ADD.v.v\n             obj_dir/Fo_B_ADD.v.sv\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("Fo_B_ADD_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(8,Fo_B_ADD_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n     #40\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Fo_B_ADD_tb();
parameter N=5;
reg [3:0] A,B;
reg C;
wire [3:0] S;
wire D;

reg [3:0] A_array[1:N];
reg [1:N] C_array;
reg [3:0] B_array[1:N];
reg [1:N] D_array;
reg [1:N] Sum_array[1:N];
initial begin

$dumpfile("Fo_B_ADD_tb.vcd");
$dumpvars(8,Fo_B_ADD_tb);
  A_array[1]=4'b0000;
  A_array[2]=4'b0001;
  A_array[3]=4'b0010;
  A_array[4]=4'b0011;
  A_array[5]=4'b0100;

  C_array[1]=1'b0;
  C_array[2]=1'b0;
  C_array[3]=1'b0;
  C_array[4]=1'b0;
  C_array[5]=1'b1;

  B_array[1]=4'b0000;
  B_array[2]=4'b0001;
  B_array[3]=4'b0010;
  B_array[4]=4'b0011;
  B_array[5]=4'b0100;

  Sum_array[1]=4'b0000;
  Sum_array[2]=4'b0010;
  Sum_array[3]=4'b0100;
  Sum_array[4]=4'b0110;
  Sum_array[5]=4'b1001;

  D_array[1]=1'b0;
  D_array[2]=1'b0;
  D_array[3]=1'b0;
  D_array[4]=1'b0;
  D_array[5]=1'b1;



end
integer i;
always  begin
  for(i=1;i<=N;i=i+1)
   begin
    $display(i);
     A<=A_array[i];
     C<=C_array[i];
     #40
     if(!(S==Sum_array[i])&(D==D_array[i]))
     begin
     $display("WRONG");
     end
      else begin 
      $display("Correct !");
      end
  end
  $display("test Finished");
end
Fo_B_ADD uut(A,B,C,S,D);
 endmodule
module Fo_B_ADD_tb();

parameter N=5;
reg [3:0] A,B;
reg C;
wire [3:0] S;
wire D;

reg [3:0] A_array[1:N];
reg [1:N] C_array;
reg [3:0] B_array[1:N];
reg [1:N] D_array;
reg [1:N] Sum_array[1:N];
initial begin

$dumpfile("Fo_B_ADD_tb.vcd");
$dumpvars(8,Fo_B_ADD_tb);
  A_array[1]=4'b0000;
  A_array[2]=4'b0001;
  A_array[3]=4'b0010;
  A_array[4]=4'b0011;
  A_array[5]=4'b0100;

  C_array[1]=1'b0;
  C_array[2]=1'b0;
  C_array[3]=1'b0;
  C_array[4]=1'b0;
  C_array[5]=1'b1;

  B_array[1]=4'b0000;
  B_array[2]=4'b0001;
  B_array[3]=4'b0010;
  B_array[4]=4'b0011;
  B_array[5]=4'b0100;

  Sum_array[1]=4'b0000;
  Sum_array[2]=4'b0010;
  Sum_array[3]=4'b0100;
  Sum_array[4]=4'b0110;
  Sum_array[5]=4'b1001;

  D_array[1]=1'b0;
  D_array[2]=1'b0;
  D_array[3]=1'b0;
  D_array[4]=1'b0;
  D_array[5]=1'b1;



end
integer i;
always  begin
  for(i=1;i<=N;i=i+1)
   begin
    $display(i);
     A<=A_array[i];
     C<=C_array[i];
     #40
     if(!(S==Sum_array[i])&(D==D_array[i]))
     begin
     $display("WRONG");
     end
      else begin 
      $display("Correct !");
      end
  end
  $display("test Finished");
end
Fo_B_ADD uut(A,B,C,S,D);
 endmodule