data/full_repos/permissive/435885222/sources/cpu.v
1: b"%Error: data/full_repos/permissive/435885222/sources/cpu.v:75: Cannot find file containing module: 'pc_reg'\n    pc_reg pc_reg0(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435885222/sources,data/full_repos/permissive/435885222/pc_reg\n             data/full_repos/permissive/435885222/sources,data/full_repos/permissive/435885222/pc_reg.v\n             data/full_repos/permissive/435885222/sources,data/full_repos/permissive/435885222/pc_reg.sv\n             pc_reg\n             pc_reg.v\n             pc_reg.sv\n             obj_dir/pc_reg\n             obj_dir/pc_reg.v\n             obj_dir/pc_reg.sv\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:85: Cannot find file containing module: 'if_id'\n    if_id if_id0(\n    ^~~~~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:94: Cannot find file containing module: 'id'\n    id id0(\n    ^~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:122: Cannot find file containing module: 'regfile'\n    regfile regfile0(\n    ^~~~~~~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:136: Cannot find file containing module: 'id_ex'\n    id_ex id_ex0(\n    ^~~~~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:157: Cannot find file containing module: 'ex'\n    ex ex0(\n    ^~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:175: Cannot find file containing module: 'ex_mem'\n    ex_mem ex_mem0(\n    ^~~~~~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:192: Cannot find file containing module: 'mem'\n    mem mem0(\n    ^~~\n%Error: data/full_repos/permissive/435885222/sources/cpu.v:210: Cannot find file containing module: 'mem_wb'\n    mem_wb mem_wb0(\n    ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module cpu(
    input clk,
    input rst,
    input [31:0] rom_data_in,
    input [31:0] ram_data_in,
    output wire[31:0] rom_addr_out,
    output wire rom_ce_out,
    output wire[31:0] ram_addr_out,
    output wire[31:0] ram_data_out,
    output wire ram_we_out,
    output wire ram_ce_out
    );

    wire[31:0] pc;
    wire[31:0] id_pc_in;
    wire[31:0] id_inst_in;

    wire[7:0] id_aluop_out;
    wire[2:0] id_alusel_out;
    wire[31:0] id_reg1_out;
    wire[31:0] id_reg2_out;
    wire id_wreg_out;
    wire[4:0] id_wd_out;
    wire[31:0] id_link_address_out;
    wire[31:0] id_inst_out;

    wire[7:0] ex_aluop_in;
    wire[2:0] ex_alusel_in;
    wire[31:0] ex_reg1_in;
    wire[31:0] ex_reg2_in;
    wire ex_wreg_in;
    wire[4:0] ex_wd_in;
    wire[31:0] ex_link_address_in;
    wire[31:0] ex_inst_in;

    wire ex_wreg_out;
    wire[4:0] ex_wd_out;
    wire[31:0] ex_wdata_out;
    wire[7:0] ex_aluop_out;
    wire[31:0] ex_mem_addr_out;
    wire[31:0] ex_reg2_out;

    wire mem_wreg_in;
    wire[4:0] mem_wd_in;
    wire[31:0] mem_wdata_in;
    wire[7:0] mem_aluop_in;
    wire[31:0] mem_mem_addr_in;
    wire[31:0] mem_reg2_in;

    wire mem_wreg_out;
    wire[4:0] mem_wd_out;
    wire[31:0] mem_wdata_out;

    wire wb_wreg_in;
    wire[4:0] wb_wd_in;
    wire[31:0] wb_wdata_in;

    wire reg1_read;
    wire reg2_read;
    wire[31:0] reg1_data;
    wire[31:0] reg2_data;
    wire[4:0] reg1_addr;
    wire[4:0] reg2_addr;

    wire id_branch_flag_out;
    wire[31:0] branch_target_address;

    pc_reg pc_reg0(
        .clk(clk),
        .rst(rst),
        .branch_flag_in(id_branch_flag_out),
        .branch_target_address_in(branch_target_address),
        .pc(pc),
        .ce(rom_ce_out)
    );
    assign rom_addr_out=pc;

    if_id if_id0(
        .clk(clk),
        .rst(rst),
        .if_pc(pc),
        .if_inst(rom_data_in),
        .id_pc(id_pc_in),
        .id_inst(id_inst_in)
    );

    id id0(
        .rst(rst),
        .pc_in(id_pc_in),
        .inst_in(id_inst_in),
        .reg1_data_in(reg1_data),
        .reg2_data_in(reg2_data),
        .ex_wreg_in(ex_wreg_out),
        .ex_wdata_in(ex_wdata_out),
        .ex_wd_in(ex_wd_out),
        .mem_wreg_in(mem_wreg_out),
        .mem_wdata_in(mem_wdata_out),
        .mem_wd_in(mem_wd_out),
        .reg1_read_out(reg1_read),
        .reg2_read_out(reg2_read),
        .reg1_addr_out(reg1_addr),
        .reg2_addr_out(reg2_addr),
        .aluop_out(id_aluop_out),
        .alusel_out(id_alusel_out),
        .reg1_out(id_reg1_out),
        .reg2_out(id_reg2_out),
        .wd_out(id_wd_out),
        .wreg_out(id_wreg_out),
        .inst_out(id_inst_out),
        .branch_flag_out(id_branch_flag_out),
        .branch_target_address_out(branch_target_address),
        .link_addr_out(id_link_address_out)
    );

    regfile regfile0(
        .clk(clk),
        .rst(rst),
        .we(wb_wreg_in),
        .waddr(wb_wd_in),
        .wdata(wb_wdata_in),
        .re1(reg1_read),
        .raddr1(reg1_addr),
        .rdata1(reg1_data),
        .re2(reg2_read),
        .raddr2(reg2_addr),
        .rdata2(reg2_data)
    );

    id_ex id_ex0(
        .clk(clk),
        .rst(rst),
        .id_aluop(id_aluop_out),
        .id_alusel(id_alusel_out),
        .id_reg1(id_reg1_out),
        .id_reg2(id_reg2_out),
        .id_wd(id_wd_out),
        .id_wreg(id_wreg_out),
        .id_link_address(id_link_address_out),
        .id_inst(id_inst_out),
        .ex_aluop(ex_aluop_in),
        .ex_alusel(ex_alusel_in),
        .ex_reg1(ex_reg1_in),
        .ex_reg2(ex_reg2_in),
        .ex_wd(ex_wd_in),
        .ex_wreg(ex_wreg_in),
        .ex_link_address(ex_link_address_in),
        .ex_inst(ex_inst_in)
    );

    ex ex0(
        .rst(rst),
        .aluop_in(ex_aluop_in),
        .alusel_in(ex_alusel_in),
        .reg1_in(ex_reg1_in),
        .reg2_in(ex_reg2_in),
        .wd_in(ex_wd_in),
        .wreg_in(ex_wreg_in),
        .link_address_in(ex_link_address_in),
        .inst_in(ex_inst_in),
        .wd_out(ex_wd_out),
        .wreg_out(ex_wreg_out),
        .wdata_out(ex_wdata_out),
        .aluop_out(ex_aluop_out),
        .mem_addr_out(ex_mem_addr_out),
        .reg2_out(ex_reg2_out)
    );

    ex_mem ex_mem0(
        .clk(clk),
        .rst(rst),
        .ex_wd(ex_wd_out),
        .ex_wreg(ex_wreg_out),
        .ex_wdata(ex_wdata_out),
        .ex_aluop(ex_aluop_out),
        .ex_mem_addr(ex_mem_addr_out),
        .ex_reg2(ex_reg2_out),
        .mem_wd(mem_wd_in),
        .mem_wreg(mem_wreg_in),
        .mem_wdata(mem_wdata_in),
        .mem_aluop(mem_aluop_in),
        .mem_mem_addr(mem_mem_addr_in),
        .mem_reg2(mem_reg2_in)
    );

    mem mem0(
        .rst(rst),
        .wd_in(mem_wd_in),
        .wreg_in(mem_wreg_in),
        .wdata_in(mem_wdata_in),
        .aluop_in(mem_aluop_in),
        .mem_addr_in(mem_mem_addr_in),
        .reg2_in(mem_reg2_in),
        .mem_data_in(ram_data_in),
        .wd_out(mem_wd_out),
        .wreg_out(mem_wreg_out),
        .wdata_out(mem_wdata_out),
        .mem_addr_out(ram_addr_out),
        .mem_we_out(ram_we_out),
        .mem_data_out(ram_data_out),
        .mem_ce_out(ram_ce_out)
    );

    mem_wb mem_wb0(
        .clk(clk),
        .rst(rst),
        .mem_wd(mem_wd_out),
        .mem_wreg(mem_wreg_out),
        .mem_wdata(mem_wdata_out),
        .wb_wd(wb_wd_in),
        .wb_wreg(wb_wreg_in),
        .wb_wdata(wb_wdata_in)
    );
endmodule
module cpu(
    input clk,
    input rst,
    input [31:0] rom_data_in,
    input [31:0] ram_data_in,
    output wire[31:0] rom_addr_out,
    output wire rom_ce_out,
    output wire[31:0] ram_addr_out,
    output wire[31:0] ram_data_out,
    output wire ram_we_out,
    output wire ram_ce_out
    );


    wire[31:0] pc;
    wire[31:0] id_pc_in;
    wire[31:0] id_inst_in;

    wire[7:0] id_aluop_out;
    wire[2:0] id_alusel_out;
    wire[31:0] id_reg1_out;
    wire[31:0] id_reg2_out;
    wire id_wreg_out;
    wire[4:0] id_wd_out;
    wire[31:0] id_link_address_out;
    wire[31:0] id_inst_out;

    wire[7:0] ex_aluop_in;
    wire[2:0] ex_alusel_in;
    wire[31:0] ex_reg1_in;
    wire[31:0] ex_reg2_in;
    wire ex_wreg_in;
    wire[4:0] ex_wd_in;
    wire[31:0] ex_link_address_in;
    wire[31:0] ex_inst_in;

    wire ex_wreg_out;
    wire[4:0] ex_wd_out;
    wire[31:0] ex_wdata_out;
    wire[7:0] ex_aluop_out;
    wire[31:0] ex_mem_addr_out;
    wire[31:0] ex_reg2_out;

    wire mem_wreg_in;
    wire[4:0] mem_wd_in;
    wire[31:0] mem_wdata_in;
    wire[7:0] mem_aluop_in;
    wire[31:0] mem_mem_addr_in;
    wire[31:0] mem_reg2_in;

    wire mem_wreg_out;
    wire[4:0] mem_wd_out;
    wire[31:0] mem_wdata_out;

    wire wb_wreg_in;
    wire[4:0] wb_wd_in;
    wire[31:0] wb_wdata_in;

    wire reg1_read;
    wire reg2_read;
    wire[31:0] reg1_data;
    wire[31:0] reg2_data;
    wire[4:0] reg1_addr;
    wire[4:0] reg2_addr;

    wire id_branch_flag_out;
    wire[31:0] branch_target_address;

    pc_reg pc_reg0(
        .clk(clk),
        .rst(rst),
        .branch_flag_in(id_branch_flag_out),
        .branch_target_address_in(branch_target_address),
        .pc(pc),
        .ce(rom_ce_out)
    );
    assign rom_addr_out=pc;

    if_id if_id0(
        .clk(clk),
        .rst(rst),
        .if_pc(pc),
        .if_inst(rom_data_in),
        .id_pc(id_pc_in),
        .id_inst(id_inst_in)
    );

    id id0(
        .rst(rst),
        .pc_in(id_pc_in),
        .inst_in(id_inst_in),
        .reg1_data_in(reg1_data),
        .reg2_data_in(reg2_data),
        .ex_wreg_in(ex_wreg_out),
        .ex_wdata_in(ex_wdata_out),
        .ex_wd_in(ex_wd_out),
        .mem_wreg_in(mem_wreg_out),
        .mem_wdata_in(mem_wdata_out),
        .mem_wd_in(mem_wd_out),
        .reg1_read_out(reg1_read),
        .reg2_read_out(reg2_read),
        .reg1_addr_out(reg1_addr),
        .reg2_addr_out(reg2_addr),
        .aluop_out(id_aluop_out),
        .alusel_out(id_alusel_out),
        .reg1_out(id_reg1_out),
        .reg2_out(id_reg2_out),
        .wd_out(id_wd_out),
        .wreg_out(id_wreg_out),
        .inst_out(id_inst_out),
        .branch_flag_out(id_branch_flag_out),
        .branch_target_address_out(branch_target_address),
        .link_addr_out(id_link_address_out)
    );

    regfile regfile0(
        .clk(clk),
        .rst(rst),
        .we(wb_wreg_in),
        .waddr(wb_wd_in),
        .wdata(wb_wdata_in),
        .re1(reg1_read),
        .raddr1(reg1_addr),
        .rdata1(reg1_data),
        .re2(reg2_read),
        .raddr2(reg2_addr),
        .rdata2(reg2_data)
    );

    id_ex id_ex0(
        .clk(clk),
        .rst(rst),
        .id_aluop(id_aluop_out),
        .id_alusel(id_alusel_out),
        .id_reg1(id_reg1_out),
        .id_reg2(id_reg2_out),
        .id_wd(id_wd_out),
        .id_wreg(id_wreg_out),
        .id_link_address(id_link_address_out),
        .id_inst(id_inst_out),
        .ex_aluop(ex_aluop_in),
        .ex_alusel(ex_alusel_in),
        .ex_reg1(ex_reg1_in),
        .ex_reg2(ex_reg2_in),
        .ex_wd(ex_wd_in),
        .ex_wreg(ex_wreg_in),
        .ex_link_address(ex_link_address_in),
        .ex_inst(ex_inst_in)
    );

    ex ex0(
        .rst(rst),
        .aluop_in(ex_aluop_in),
        .alusel_in(ex_alusel_in),
        .reg1_in(ex_reg1_in),
        .reg2_in(ex_reg2_in),
        .wd_in(ex_wd_in),
        .wreg_in(ex_wreg_in),
        .link_address_in(ex_link_address_in),
        .inst_in(ex_inst_in),
        .wd_out(ex_wd_out),
        .wreg_out(ex_wreg_out),
        .wdata_out(ex_wdata_out),
        .aluop_out(ex_aluop_out),
        .mem_addr_out(ex_mem_addr_out),
        .reg2_out(ex_reg2_out)
    );

    ex_mem ex_mem0(
        .clk(clk),
        .rst(rst),
        .ex_wd(ex_wd_out),
        .ex_wreg(ex_wreg_out),
        .ex_wdata(ex_wdata_out),
        .ex_aluop(ex_aluop_out),
        .ex_mem_addr(ex_mem_addr_out),
        .ex_reg2(ex_reg2_out),
        .mem_wd(mem_wd_in),
        .mem_wreg(mem_wreg_in),
        .mem_wdata(mem_wdata_in),
        .mem_aluop(mem_aluop_in),
        .mem_mem_addr(mem_mem_addr_in),
        .mem_reg2(mem_reg2_in)
    );

    mem mem0(
        .rst(rst),
        .wd_in(mem_wd_in),
        .wreg_in(mem_wreg_in),
        .wdata_in(mem_wdata_in),
        .aluop_in(mem_aluop_in),
        .mem_addr_in(mem_mem_addr_in),
        .reg2_in(mem_reg2_in),
        .mem_data_in(ram_data_in),
        .wd_out(mem_wd_out),
        .wreg_out(mem_wreg_out),
        .wdata_out(mem_wdata_out),
        .mem_addr_out(ram_addr_out),
        .mem_we_out(ram_we_out),
        .mem_data_out(ram_data_out),
        .mem_ce_out(ram_ce_out)
    );

    mem_wb mem_wb0(
        .clk(clk),
        .rst(rst),
        .mem_wd(mem_wd_out),
        .mem_wreg(mem_wreg_out),
        .mem_wdata(mem_wdata_out),
        .wb_wd(wb_wd_in),
        .wb_wreg(wb_wreg_in),
        .wb_wdata(wb_wdata_in)
    );
endmodule