data/full_repos/permissive/486588912/verilog/l1mmu.v
1: b'%Error: data/full_repos/permissive/486588912/verilog/l1mmu.v:23: Cannot find file containing module: \'mmio_addr\'\n    mmio_addr mmio_addr_l1addr(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/mmio_addr\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/mmio_addr.v\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/mmio_addr.sv\n             mmio_addr\n             mmio_addr.v\n             mmio_addr.sv\n             obj_dir/mmio_addr\n             obj_dir/mmio_addr.v\n             obj_dir/mmio_addr.sv\n%Warning-WIDTH: data/full_repos/permissive/486588912/verilog/l1mmu.v:46: Operator COND expects 276 bits on the Conditional False, but Conditional False\'s REPLICATE generates 256 bits.\n                                                                       : ... In instance l1mmu\n    assign mmu_l1_read_data = addr_is_mmio ? {244\'b0, mmu_mmio_read_data} : {_dout, stage};\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486588912/verilog/l1mmu.v:46: Operator ASSIGNW expects 256 bits on the Assign RHS, but Assign RHS\'s COND generates 276 bits.\n                                                                       : ... In instance l1mmu\n    assign mmu_l1_read_data = addr_is_mmio ? {244\'b0, mmu_mmio_read_data} : {_dout, stage};\n                            ^\n%Error: data/full_repos/permissive/486588912/verilog/l1mmu.v:48: Cannot find file containing module: \'mem_fake_mig\'\n    mem_fake_mig fake_mig(\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module l1mmu(
    input sys_clk,
    input rst_n,
    
    input l1_mmu_req_read,
    input l1_mmu_req_write,
    input [31:0] l1_mmu_req_addr,
    input [255:0] l1_mmu_write_data,

    output mmu_l1_done,
    output [255:0] mmu_l1_read_data,

    output mmu_mmio_read,
    output mmu_mmio_write,
    output [31:0] mmu_mmio_addr,
    output [31:0] mmu_mmio_write_data,
    input  mmu_mmio_done,
    input  [31:0] mmu_mmio_read_data
);
    wire addr_is_mmio;

    mmio_addr mmio_addr_l1addr(
        .addr(l1_mmu_req_addr),
        .is_mmio(addr_is_mmio)
    );

    assign mmu_mmio_read = addr_is_mmio && l1_mmu_req_read;
    assign mmu_mmio_write = addr_is_mmio && l1_mmu_req_write;
    assign mmu_mmio_addr = {l1_mmu_req_addr[31:2], 2'b00};
    assign mmu_mmio_write_data = l1_mmu_write_data[31:0];
    
    reg [1:0] status;
    localparam  STATUS_IDLE     = 2'b00,
                STATUS_ACC_HI   = 2'b01,
                STATUS_DONE     = 2'b10;

    wire            acc_hi      = status == STATUS_ACC_HI || status == STATUS_DONE;
    reg     [127:0] stage;
    wire    [31:0]  _req_addr   = {4'b0, l1_mmu_req_addr[31:5], acc_hi};
    wire    [127:0] _dout;
    wire    [127:0] _wr_data    = acc_hi ? l1_mmu_write_data[255:128] : l1_mmu_write_data[127:0];
    wire            mig_write   = !addr_is_mmio && l1_mmu_req_write;

    assign mmu_l1_done = addr_is_mmio ? mmu_mmio_done : status == STATUS_DONE;
    assign mmu_l1_read_data = addr_is_mmio ? {244'b0, mmu_mmio_read_data} : {_dout, stage};

    mem_fake_mig fake_mig(
        .clka(sys_clk),
        .addra(_req_addr),
        .douta(_dout),
        .dina(_wr_data),
        .wea(mig_write)
    );

    always @(posedge sys_clk) begin
        if (!rst_n) begin
            stage <= 128'b0;
        end else begin

            if (status == STATUS_ACC_HI && l1_mmu_req_read) begin
                stage <= _dout;

            end else begin
                stage <= stage;
            end
        end
    end


    always @(posedge sys_clk) begin
        if (~rst_n) begin
            status <= STATUS_IDLE;
        end else begin
            if (addr_is_mmio && (l1_mmu_req_read || l1_mmu_req_write)) begin

                status <= STATUS_IDLE;
            end else begin
                if (l1_mmu_req_read || l1_mmu_req_write) begin
                    if (status == STATUS_IDLE) begin

                        status <= STATUS_ACC_HI;
                    end else if (status == STATUS_ACC_HI) begin

                        status <= STATUS_DONE;
                    end else if (status == STATUS_DONE) begin

                        status <= STATUS_IDLE;
                    end else begin
                        status <= status;
                    end
                end else begin
                    status <= STATUS_IDLE;
                end
            end
        end
    end
    
endmodule
module l1mmu(
    input sys_clk,
    input rst_n,
    
    input l1_mmu_req_read,
    input l1_mmu_req_write,
    input [31:0] l1_mmu_req_addr,
    input [255:0] l1_mmu_write_data,

    output mmu_l1_done,
    output [255:0] mmu_l1_read_data,

    output mmu_mmio_read,
    output mmu_mmio_write,
    output [31:0] mmu_mmio_addr,
    output [31:0] mmu_mmio_write_data,
    input  mmu_mmio_done,
    input  [31:0] mmu_mmio_read_data
);

    wire addr_is_mmio;

    mmio_addr mmio_addr_l1addr(
        .addr(l1_mmu_req_addr),
        .is_mmio(addr_is_mmio)
    );

    assign mmu_mmio_read = addr_is_mmio && l1_mmu_req_read;
    assign mmu_mmio_write = addr_is_mmio && l1_mmu_req_write;
    assign mmu_mmio_addr = {l1_mmu_req_addr[31:2], 2'b00};
    assign mmu_mmio_write_data = l1_mmu_write_data[31:0];
    
    reg [1:0] status;
    localparam  STATUS_IDLE     = 2'b00,
                STATUS_ACC_HI   = 2'b01,
                STATUS_DONE     = 2'b10;

    wire            acc_hi      = status == STATUS_ACC_HI || status == STATUS_DONE;
    reg     [127:0] stage;
    wire    [31:0]  _req_addr   = {4'b0, l1_mmu_req_addr[31:5], acc_hi};
    wire    [127:0] _dout;
    wire    [127:0] _wr_data    = acc_hi ? l1_mmu_write_data[255:128] : l1_mmu_write_data[127:0];
    wire            mig_write   = !addr_is_mmio && l1_mmu_req_write;

    assign mmu_l1_done = addr_is_mmio ? mmu_mmio_done : status == STATUS_DONE;
    assign mmu_l1_read_data = addr_is_mmio ? {244'b0, mmu_mmio_read_data} : {_dout, stage};

    mem_fake_mig fake_mig(
        .clka(sys_clk),
        .addra(_req_addr),
        .douta(_dout),
        .dina(_wr_data),
        .wea(mig_write)
    );

    always @(posedge sys_clk) begin
        if (!rst_n) begin
            stage <= 128'b0;
        end else begin

            if (status == STATUS_ACC_HI && l1_mmu_req_read) begin
                stage <= _dout;

            end else begin
                stage <= stage;
            end
        end
    end


    always @(posedge sys_clk) begin
        if (~rst_n) begin
            status <= STATUS_IDLE;
        end else begin
            if (addr_is_mmio && (l1_mmu_req_read || l1_mmu_req_write)) begin

                status <= STATUS_IDLE;
            end else begin
                if (l1_mmu_req_read || l1_mmu_req_write) begin
                    if (status == STATUS_IDLE) begin

                        status <= STATUS_ACC_HI;
                    end else if (status == STATUS_ACC_HI) begin

                        status <= STATUS_DONE;
                    end else if (status == STATUS_DONE) begin

                        status <= STATUS_IDLE;
                    end else begin
                        status <= status;
                    end
                end else begin
                    status <= STATUS_IDLE;
                end
            end
        end
    end
    
endmodule