data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:38: Signal definition not found, creating implicitly: \'write\'\n                              write, instruction, zero, clk, rst);\n                              ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_a\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_b\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_c\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:160: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_a\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:161: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_b\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_b : (sel == 2)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:162: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_c\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_c: (sel == 3)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:163: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_d\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_d : (sel == 4)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:164: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_e\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_e : \'bx;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:160: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1)\n                  ^\n%Error: Exiting due to 11 warning(s)\n'
module Program_Counter (count, data_in, Load_PC, Inc_PC, clk, rst);
  parameter word_size = 8;
  output [word_size-1: 0] 	count;
  input  [word_size-1: 0] 	data_in;
  input 			Load_PC, Inc_PC;
  input 			clk, rst;

  reg 	  [word_size-1: 0]	count;

  always @ (posedge clk or negedge rst)
    if (rst == 0) count <= 0; else if (Load_PC) count <= data_in; else if  (Inc_PC) count <= count +1;
endmodule
module Program_Counter (count, data_in, Load_PC, Inc_PC, clk, rst);

  parameter word_size = 8;
  output [word_size-1: 0] 	count;
  input  [word_size-1: 0] 	data_in;
  input 			Load_PC, Inc_PC;
  input 			clk, rst;

  reg 	  [word_size-1: 0]	count;

  always @ (posedge clk or negedge rst)
    if (rst == 0) count <= 0; else if (Load_PC) count <= data_in; else if  (Inc_PC) count <= count +1;
endmodule