data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    A=-1; B=1; S=5\'d0; L=0; #10\n                            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    A=-1; B=1; S=5\'h1; L=0; #10\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    A=-1; B=-1; S=5\'h1; L=-2; #10\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    A=-1; B=1; S=5\'h2; L=-2; #10\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    A=-1; B=-1; S=5\'h2; L=0; #10\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F0; B=32\'h0FF0_F00F; S=5\'h4; L=32\'h00F0_F000; #10\n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F0; B=32\'h0FF0_F00F; S=5\'h5; L=32\'hFFF0_F0FF; #10\n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F0; B=32\'h0FF0_F00F; S=5\'h6; L=32\'hFF00_00FF; #10\n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F7; B=32\'d2; S=5\'h7; L=32\'hC3C3_C3DC; #10\n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F7; B=32\'d3; S=5\'h8; L=32\'hFE1E_1E1E; #10\n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'hF0F0_F0F7; B=32\'d5; S=5\'h9; L=32\'h0787_8787; #10\n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n    A=-35; B=-75; S=5\'hA; L=32\'d0; CMP_T=1\'b0; #10\n                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n    A=-65510; B=-26; S=5\'hA; L=1; CMP_T=1\'b1; #10\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n    A=61; B=4294967231; S=5\'hB; L=32\'d1; CMP_T=1\'b1; #10\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n    A=928; B=741; S=5\'hB; L=0; CMP_T=1\'b0; #10\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n    A=-27650; B=-27650; S=5\'hC; CMP_T=1\'b1; #10\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n    A=928; B=741; S=5\'hC; CMP_T=1\'b0; #10\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n    A=-27650; B=0; S=5\'hD; CMP_T=1\'b1; #10\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n    A=742; B=742; S=5\'hD; CMP_T=1\'b0; #10\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n    A=-48; B=2795; S=5\'hE; CMP_T=1\'b1; #10\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n    A=928; B=741; S=5\'hE; CMP_T=1\'b0; #10\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n    A=-472543; B=-27; S=5\'hF; CMP_T=1\'b0; #10\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n    A=928; B=741; S=5\'hF; CMP_T=1\'b1; #10\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n    A=-923687; B=-923687; S=5\'hF; CMP_T=1\'b1; #10\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n    A=8; B=5298; S=5\'h10; CMP_T=1\'b1; #10\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:243: Unsupported: Ignoring delay on this delayed statement.\n    A=238; B=65298; S=5\'h11; CMP_T=1\'b0; #10\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n    A=32\'h00F0_F0F7; B=-4; S=5\'h8; L=32\'h000F_0F0F; #10\n                                                    ^\n%Error: data/full_repos/permissive/481307378/source_files/ALU/alu_tb.v:37: Cannot find file containing module: \'alu\'\nalu dut(.A(A), .B(B), .S(S), .Q(Q), .CMP(CMP));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/481307378/source_files/ALU,data/full_repos/permissive/481307378/alu\n             data/full_repos/permissive/481307378/source_files/ALU,data/full_repos/permissive/481307378/alu.v\n             data/full_repos/permissive/481307378/source_files/ALU,data/full_repos/permissive/481307378/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();
reg [31:0]A, B;
reg [4:0]S;
wire [31:0]Q;
wire CMP;
reg [31:0]L;
reg CMP_T;

alu dut(.A(A), .B(B), .S(S), .Q(Q), .CMP(CMP));
initial
begin

    A=-1; B=1; S=5'd0; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 1 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-1; B=1; S=`ADD; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 2 failed: Q=%h L=%h", Q, L);
        $finish;
    end

    A=-1; B=-1; S=`ADD; L=-2; #10
    if(Q != L)
    begin
        $display("Test pattern 3 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-1; B=1; S=`SUB; L=-2; #10
    if(Q != L)
    begin
        $display("Test pattern 4 failed: Q=%h L=%h", Q, L);
        $finish;
    end

    A=-1; B=-1; S=`SUB; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 5 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`AND; L=32'h00F0_F000; #10
    if(Q != L)
    begin
        $display("Test pattern 6 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`OR; L=32'hFFF0_F0FF; #10
    if(Q != L)
    begin
        $display("Test pattern 7 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`XOR; L=32'hFF00_00FF; #10
    if(Q != L)
    begin
        $display("Test pattern 8 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F7; B=32'd2; S=`SLL; L=32'hC3C3_C3DC; #10
    if(Q != L)
    begin
        $display("Test pattern 9 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=32'hF0F0_F0F7; B=32'd3; S=`SRA; L=32'hFE1E_1E1E; #10
    if(Q != L)
    begin
        $display("Test pattern 10 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F7; B=32'd5; S=`SRL; L=32'h0787_8787; #10
    if(Q != L )
    begin
        $display("Test pattern 11 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-35; B=-75; S=`SLT; L=32'd0; CMP_T=1'b0; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 12 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end

    A=-65510; B=-26; S=`SLT; L=1; CMP_T=1'b1; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 13 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end
    


    A=61; B=4294967231; S=`SLTU; L=32'd1; CMP_T=1'b1; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 14 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`SLTU; L=0; CMP_T=1'b0; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 15 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end
    

    


    A=-27650; B=-27650; S=`BEQ; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 16 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BEQ; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 17 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-27650; B=0; S=`BNE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 18 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=742; B=742; S=`BNE; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 19 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-48; B=2795; S=`BLT; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 20 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BLT; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 21 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-472543; B=-27; S=`BGE; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 22 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BGE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 23 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=-923687; B=-923687; S=`BGE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 24 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    

    A=8; B=5298; S=`BLTU; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 25 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    

    A=238; B=65298; S=`BGEU; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 26 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=32'h00F0_F0F7; B=-4; S=`SRA; L=32'h000F_0F0F; #10
    if(Q != L)
    begin
        $display("Test pattern 27 failed: Q=%h L=%h", Q, L);
        $finish;
     end
    
    $display("Simulation Successfull!");
end
endmodule
module alu_tb();

reg [31:0]A, B;
reg [4:0]S;
wire [31:0]Q;
wire CMP;
reg [31:0]L;
reg CMP_T;

alu dut(.A(A), .B(B), .S(S), .Q(Q), .CMP(CMP));
initial
begin

    A=-1; B=1; S=5'd0; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 1 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-1; B=1; S=`ADD; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 2 failed: Q=%h L=%h", Q, L);
        $finish;
    end

    A=-1; B=-1; S=`ADD; L=-2; #10
    if(Q != L)
    begin
        $display("Test pattern 3 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-1; B=1; S=`SUB; L=-2; #10
    if(Q != L)
    begin
        $display("Test pattern 4 failed: Q=%h L=%h", Q, L);
        $finish;
    end

    A=-1; B=-1; S=`SUB; L=0; #10
    if(Q != L)
    begin
        $display("Test pattern 5 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`AND; L=32'h00F0_F000; #10
    if(Q != L)
    begin
        $display("Test pattern 6 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`OR; L=32'hFFF0_F0FF; #10
    if(Q != L)
    begin
        $display("Test pattern 7 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F0; B=32'h0FF0_F00F; S=`XOR; L=32'hFF00_00FF; #10
    if(Q != L)
    begin
        $display("Test pattern 8 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F7; B=32'd2; S=`SLL; L=32'hC3C3_C3DC; #10
    if(Q != L)
    begin
        $display("Test pattern 9 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=32'hF0F0_F0F7; B=32'd3; S=`SRA; L=32'hFE1E_1E1E; #10
    if(Q != L)
    begin
        $display("Test pattern 10 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    

    A=32'hF0F0_F0F7; B=32'd5; S=`SRL; L=32'h0787_8787; #10
    if(Q != L )
    begin
        $display("Test pattern 11 failed: Q=%h L=%h", Q, L);
        $finish;
    end
    


    A=-35; B=-75; S=`SLT; L=32'd0; CMP_T=1'b0; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 12 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end

    A=-65510; B=-26; S=`SLT; L=1; CMP_T=1'b1; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 13 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end
    


    A=61; B=4294967231; S=`SLTU; L=32'd1; CMP_T=1'b1; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 14 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`SLTU; L=0; CMP_T=1'b0; #10
    if((Q != L) && (CMP != CMP_T))
    begin
        $display("Test pattern 15 failed: Q=%h L=%h -- CMP=%b CMP_T=%b", Q, L, CMP, CMP_T);
        $finish;
    end
    

    


    A=-27650; B=-27650; S=`BEQ; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 16 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BEQ; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 17 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-27650; B=0; S=`BNE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 18 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=742; B=742; S=`BNE; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 19 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-48; B=2795; S=`BLT; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 20 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BLT; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 21 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=-472543; B=-27; S=`BGE; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 22 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=928; B=741; S=`BGE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 23 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end

    A=-923687; B=-923687; S=`BGE; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 24 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    

    A=8; B=5298; S=`BLTU; CMP_T=1'b1; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 25 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    

    A=238; B=65298; S=`BGEU; CMP_T=1'b0; #10
    if(CMP != CMP_T)
    begin
        $display("Test pattern 26 failed: CMP=%b CMP_T=%b", CMP, CMP_T);
        $finish;
    end
    


    A=32'h00F0_F0F7; B=-4; S=`SRA; L=32'h000F_0F0F; #10
    if(Q != L)
    begin
        $display("Test pattern 27 failed: Q=%h L=%h", Q, L);
        $finish;
     end
    
    $display("Simulation Successfull!");
end
endmodule