data/full_repos/permissive/493212017/processor/sail-core/verilog/CSR.v
data/verilator_xmls/a3acf30c-94b7-4579-9e1b-210854cf7cf8.xml
module csr_file (clk, write, wrAddr_CSR, wrVal_CSR, rdAddr_CSR, rdVal_CSR);
	input clk;
	input write;
	input [11:0] wrAddr_CSR;
	input [31:0] wrVal_CSR;
	input [11:0] rdAddr_CSR;
	output reg[31:0] rdVal_CSR;

	reg [31:0] csr_file [0:2**10-1];


	always @(posedge clk) begin
		if (write) begin
			csr_file[wrAddr_CSR[9:0]] <= wrVal_CSR;
		end

		rdVal_CSR <= csr_file[rdAddr_CSR[9:0]];
	end
endmodule
module csr_file (clk, write, wrAddr_CSR, wrVal_CSR, rdAddr_CSR, rdVal_CSR);

	input clk;
	input write;
	input [11:0] wrAddr_CSR;
	input [31:0] wrVal_CSR;
	input [11:0] rdAddr_CSR;
	output reg[31:0] rdVal_CSR;

	reg [31:0] csr_file [0:2**10-1];


	always @(posedge clk) begin
		if (write) begin
			csr_file[wrAddr_CSR[9:0]] <= wrVal_CSR;
		end

		rdVal_CSR <= csr_file[rdAddr_CSR[9:0]];
	end
endmodule