data/full_repos/permissive/492213907/codes/Mode_Select.v
data/verilator_xmls/044ec466-5c43-4516-ac21-9c8f2c1a8168.xml
module Mode_Select(clk, mode_sw_3, mode_sw_4, mode_out);
	
	input clk;
	input mode_sw_3;
	input mode_sw_4;
	output [1:0] mode_out;
	
	reg [1:0] mode_select;
	
	always @ (posedge clk)
	begin
    case ({mode_sw_3, mode_sw_4})
      2'b01 : mode_select <= 2'b01;
      2'b10 : mode_select <= 2'b10;
      2'b11 : mode_select <= 2'b11;
      2'b00 : mode_select <= 2'b00;
    endcase     
	end
 
  assign mode_out = mode_select;
  
endmodule
module Mode_Select(clk, mode_sw_3, mode_sw_4, mode_out);

	
	input clk;
	input mode_sw_3;
	input mode_sw_4;
	output [1:0] mode_out;
	
	reg [1:0] mode_select;
	
	always @ (posedge clk)
	begin
    case ({mode_sw_3, mode_sw_4})
      2'b01 : mode_select <= 2'b01;
      2'b10 : mode_select <= 2'b10;
      2'b11 : mode_select <= 2'b11;
      2'b00 : mode_select <= 2'b00;
    endcase     
	end
 
  assign mode_out = mode_select;
  
endmodule