data/full_repos/permissive/507850313/rtl/core/core_ifu.v
1: b'%Error: data/full_repos/permissive/507850313/rtl/core/core_ifu.v:24: Cannot find include file: core_defines.v\n`include "core_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.sv\n             core_defines.v\n             core_defines.v.v\n             core_defines.v.sv\n             obj_dir/core_defines.v\n             obj_dir/core_defines.v.v\n             obj_dir/core_defines.v.sv\n%Error: data/full_repos/permissive/507850313/rtl/core/core_ifu.v:30: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0] pc_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_ifu.v:31: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_ifu.v:35: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0] pc_o,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core_ifu.v:36: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    output [`CPU_INSTR_SIZE-1:0] instr_o,  \n            ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module core_ifu #(

) (

    output [`CPU_PC_SIZE-1:0] pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,



    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,  





    input clk,
    input rst_n
);



endmodule
module core_ifu #(

) (

    output [`CPU_PC_SIZE-1:0] pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,



    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,  





    input clk,
    input rst_n
);




endmodule