data/full_repos/permissive/46625639/pong.v
1: b'%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:438: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_x <= value_x + speed;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:442: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_x <= value_x - speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:448: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_y <= value_y + speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:452: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_y <= value_y - speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:388: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n     value <= value - speed;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:386: Operator SUB expects 32 or 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n    if ((value - speed) > 3) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:395: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n     value <= value + speed;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:393: Operator ADD expects 32 or 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n    if ((value + speed) < (1024 - 128)) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:647: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance pong.gl\n   count_secs = 1\'b0;\n              ^\n%Error: data/full_repos/permissive/46625639/pong.v:116: Cannot find file containing module: \'pll108MHz\'\n pll108MHz pll(.inclk0(CLOCK_27), .c0(video_clock));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz.v\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz.sv\n             pll108MHz\n             pll108MHz.v\n             pll108MHz.sv\n             obj_dir/pll108MHz\n             obj_dir/pll108MHz.v\n             obj_dir/pll108MHz.sv\n%Error: data/full_repos/permissive/46625639/pong.v:203: Cannot find file containing module: \'keyboard\'\n keyboard keybd(\n ^~~~~~~~\n%Error: data/full_repos/permissive/46625639/pong.v:215: Cannot find file containing module: \'oneshot\'\n oneshot pulser(\n ^~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module vga(
	clk,
	vsync,
	hsync,
	x,
	y,
	can_draw,
	start_of_frame
	); 
	
	input clk;
	output vsync, hsync;
	output [10:0] x, y;
	output can_draw;
	output start_of_frame;

	assign x = h - `ha - `hb;
	assign y = v - `va - `vb;
	assign can_draw = (h >= (`ha + `hb)) && (h < (`ha + `hb + `hc))
				   && (v >= (`va + `vb)) && (v < (`va + `vb + `vc));
	assign vsync = vga_vsync;
	assign hsync = vga_hsync;
	assign start_of_frame = startframe;


	reg [10:0] h;
	reg [10:0] v;
	reg vga_vsync;
	reg vga_hsync;
	reg startframe;
	
	always @(posedge clk) begin

		if (h < (`ha + `hb + `hc + `hd)) begin
			h <= h + 11'd1;

		end else begin
			h <= 11'd0;
			v <= (v < (`va + `vb + `vc + `vd)) ? v + 11'd1 : 11'd0;
		end
		vga_hsync <= h > `ha;
		vga_vsync <= v > `va;
		
		startframe <= (h == 11'd0) && (v == 11'd0);
	end
endmodule
module vga(
	clk,
	vsync,
	hsync,
	x,
	y,
	can_draw,
	start_of_frame
	);
 
	
	input clk;
	output vsync, hsync;
	output [10:0] x, y;
	output can_draw;
	output start_of_frame;

	assign x = h - `ha - `hb;
	assign y = v - `va - `vb;
	assign can_draw = (h >= (`ha + `hb)) && (h < (`ha + `hb + `hc))
				   && (v >= (`va + `vb)) && (v < (`va + `vb + `vc));
	assign vsync = vga_vsync;
	assign hsync = vga_hsync;
	assign start_of_frame = startframe;


	reg [10:0] h;
	reg [10:0] v;
	reg vga_vsync;
	reg vga_hsync;
	reg startframe;
	
	always @(posedge clk) begin

		if (h < (`ha + `hb + `hc + `hd)) begin
			h <= h + 11'd1;

		end else begin
			h <= 11'd0;
			v <= (v < (`va + `vb + `vc + `vd)) ? v + 11'd1 : 11'd0;
		end
		vga_hsync <= h > `ha;
		vga_vsync <= v > `va;
		
		startframe <= (h == 11'd0) && (v == 11'd0);
	end
endmodule