data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:41: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NO_HOLD\'\n   parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:43: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:59: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NONE\'\n      if(capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:66: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NO_HOLD\'\n      `ERROR_CAPTURE_MODE_NO_HOLD:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:66: syntax error, unexpected \':\', expecting endcase\n      `ERROR_CAPTURE_MODE_NO_HOLD:\n                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:71: Define or directive not defined: \'`ERROR_CAPTURE_MODE_HOLD_FIRST\'\n      `ERROR_CAPTURE_MODE_HOLD_FIRST:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:76: Define or directive not defined: \'`ERROR_CAPTURE_MODE_HOLD_ALL\'\n      `ERROR_CAPTURE_MODE_HOLD_ALL:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_err_rpt.v:95: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 12 error(s)\n'
module c_err_rpt
  (clk, reset, active, errors_in, errors_out);
   
`include "c_constants.v"
   

   parameter num_errors = 1;
   

   parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;

   parameter reset_type = `RESET_TYPE_ASYNC;
   
   
   input clk;
   input reset;
   input active;
   

   input [0:num_errors-1] errors_in;
   

   output [0:num_errors-1] errors_out;
   wire [0:num_errors-1] errors_out;
   
   generate
      
      if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_errors-1] errors_s, errors_q;
	   
	   case(capture_mode)
	     
	     `ERROR_CAPTURE_MODE_NO_HOLD:
	       begin
		  assign errors_s = errors_in;
	       end
	     
	     `ERROR_CAPTURE_MODE_HOLD_FIRST:
	       begin
		  assign errors_s = ~|errors_q ? errors_in : errors_q;
	       end
	     
	     `ERROR_CAPTURE_MODE_HOLD_ALL:
	       begin
		  assign errors_s = errors_q | errors_in;
	       end
	     
	   endcase
	   
	   c_dff
	     #(.width(num_errors),
	       .reset_type(reset_type))
	   errorsq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(errors_s),
	      .q(errors_q));
	   
	   assign errors_out = errors_q;
	   
	end
      else
	assign errors_out = {num_errors{1'b0}};
      
   endgenerate
   
endmodule
module c_err_rpt
  (clk, reset, active, errors_in, errors_out);

   
`include "c_constants.v"
   

   parameter num_errors = 1;
   

   parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;

   parameter reset_type = `RESET_TYPE_ASYNC;
   
   
   input clk;
   input reset;
   input active;
   

   input [0:num_errors-1] errors_in;
   

   output [0:num_errors-1] errors_out;
   wire [0:num_errors-1] errors_out;
   
   generate
      
      if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_errors-1] errors_s, errors_q;
	   
	   case(capture_mode)
	     
	     `ERROR_CAPTURE_MODE_NO_HOLD:
	       begin
		  assign errors_s = errors_in;
	       end
	     
	     `ERROR_CAPTURE_MODE_HOLD_FIRST:
	       begin
		  assign errors_s = ~|errors_q ? errors_in : errors_q;
	       end
	     
	     `ERROR_CAPTURE_MODE_HOLD_ALL:
	       begin
		  assign errors_s = errors_q | errors_in;
	       end
	     
	   endcase
	   
	   c_dff
	     #(.width(num_errors),
	       .reset_type(reset_type))
	   errorsq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(errors_s),
	      .q(errors_q));
	   
	   assign errors_out = errors_q;
	   
	end
      else
	assign errors_out = {num_errors{1'b0}};
      
   endgenerate
   
endmodule