data/full_repos/permissive/427221126/src/Pooling.v
1: b'%Warning-WIDTH: data/full_repos/permissive/427221126/src/Pooling.v:316: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 28 bits.\n                                                                      : ... In instance PoolingAvg\n        out_data <= (acc_sum >>> 8);  \n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/Pooling.v:318: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 28 bits.\n                                                                      : ... In instance PoolingAvg\n        out_data <= (acc_sum >>> 4);  \n                 ^~\n%Error: data/full_repos/permissive/427221126/src/Pooling.v:330: Cannot find file containing module: \'RAM1P\'\n  RAM1P #( .DATA_WIDTH(INWIDTH), .ADDR_WIDTH(ADDR_WIDTH) ) U_ram (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM1P\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM1P.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM1P.sv\n             RAM1P\n             RAM1P.v\n             RAM1P.sv\n             obj_dir/RAM1P\n             obj_dir/RAM1P.v\n             obj_dir/RAM1P.sv\n%Error: data/full_repos/permissive/427221126/src/Pooling.v:336: Cannot find file containing module: \'AddrGenPool\'\n  AddrGenPool #( \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/Pooling.v:353: Cannot find file containing module: \'Acc\'\n  Acc #(.INWIDTH(INWIDTH), .ACC_WIDTH(ACC_WIDTH)) U_acc (\n  ^~~\n%Error: data/full_repos/permissive/427221126/src/Pooling.v:362: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/Pooling.v:375: Cannot find file containing module: \'FIFOsync_ram\'\n  FIFOsync_ram #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
function integer max(input integer a, input integer b);
    begin
      max = (a > b) ? a : b;
    end
  endfunction
function integer max(input integer a, input integer b);

    begin
      max = (a > b) ? a : b;
    end
  endfunction