data/full_repos/permissive/506186384/project-files/lab5/DataMemory.v
data/verilator_xmls/d0c96e8c-bbe7-4df7-b27f-85358d21fe99.xml
module DataMemory(
    input Clk,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    output [31:0] ReadData
    );
    
    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    
    always @ (Address)
        begin
            rd = 0;
            if(MemRead==1)
                rd = MemFile[Address];
        end
        
    assign ReadData = rd;
    
    always @ (negedge Clk)
        begin
            if(MemWrite==1)
                MemFile[Address] <= WriteData;
        end
endmodule
module DataMemory(
    input Clk,
    input [31:0] Address,
    input [31:0] WriteData,
    input MemWrite,
    input MemRead,
    output [31:0] ReadData
    );

    
    reg [31:0] MemFile[0:63];
    reg [31:0] rd;
    
    always @ (Address)
        begin
            rd = 0;
            if(MemRead==1)
                rd = MemFile[Address];
        end
        
    assign ReadData = rd;
    
    always @ (negedge Clk)
        begin
            if(MemWrite==1)
                MemFile[Address] <= WriteData;
        end
endmodule