data/full_repos/permissive/43858668/final_verilog/src/clib/c_reduce_bits.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_reduce_bits.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_reduce_bits.v:44: Define or directive not defined: \'`BINARY_OP_AND\'\n   parameter op = `BINARY_OP_AND;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_reduce_bits.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter op = `BINARY_OP_AND;\n                                ^\n%Error: Exiting due to 3 error(s)\n'
module c_reduce_bits
  (data_in, data_out);
   
`include "c_constants.v"
   

   parameter num_ports = 1;
   

   parameter width = 32;
   

   parameter op = `BINARY_OP_AND;
   

   input [0:num_ports*width-1] data_in;
   

   output [0:num_ports-1]      data_out;
   wire [0:num_ports-1]        data_out;
   
   generate
      
      genvar 		       p;
      
      for(p = 0; p < num_ports; p = p + 1)
	begin:ps
	   
	   c_binary_op
	      #(.num_ports(width),
		.width(1),
		.op(op))
	   bop
	      (.data_in(data_in[p*width:(p+1)*width-1]),
	       .data_out(data_out[p]));
	   
	end
      
   endgenerate
   
endmodule
module c_reduce_bits
  (data_in, data_out);

   
`include "c_constants.v"
   

   parameter num_ports = 1;
   

   parameter width = 32;
   

   parameter op = `BINARY_OP_AND;
   

   input [0:num_ports*width-1] data_in;
   

   output [0:num_ports-1]      data_out;
   wire [0:num_ports-1]        data_out;
   
   generate
      
      genvar 		       p;
      
      for(p = 0; p < num_ports; p = p + 1)
	begin:ps
	   
	   c_binary_op
	      #(.num_ports(width),
		.width(1),
		.op(op))
	   bop
	      (.data_in(data_in[p*width:(p+1)*width-1]),
	       .data_out(data_out[p]));
	   
	end
      
   endgenerate
   
endmodule