data/full_repos/permissive/441359809/src/yosys/manual/APPNOTE_011_Design_Investigation/example.v
data/verilator_xmls/be232262-c945-426d-8835-b0213edead98.xml
module example(input clk, a, b, c,
               output reg [1:0] y);
    always @(posedge clk)
        if (c)
            y <= c ? a + b : 2'd0;
endmodule
module example(input clk, a, b, c,
               output reg [1:0] y);

    always @(posedge clk)
        if (c)
            y <= c ? a + b : 2'd0;
endmodule