data/full_repos/permissive/435170935/002-counter/counter.v
data/verilator_xmls/9bdd0574-dd5e-46d1-8e70-f82d224c6284.xml
module counter # (
    parameter width = 4
) (
        input   clk,
        input   rstn,
        output  reg [width - 1:0]       out
);
    always @(posedge clk) begin
        if(!rstn) begin
            out <= out + 1;
        end else begin
            out <= 0;
        end
    end

endmodule
module counter # (
    parameter width = 4
) (
        input   clk,
        input   rstn,
        output  reg [width - 1:0]       out
);

    always @(posedge clk) begin
        if(!rstn) begin
            out <= out + 1;
        end else begin
            out <= 0;
        end
    end

endmodule