data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/pc.v
data/verilator_xmls/9e3d9a44-eb21-460a-bd59-4cdb0eef5b75.xml
module pc(clock, reset, en, address_in, address_out);
	input clock, reset, en;
	input[11:0] address_in;
	output[11:0] address_out;
	

	reg [11:0] address_out;
   initial
   begin
       address_out = 12'b0;
   end


   always @(posedge clock or posedge reset) begin

       if (reset) begin
           address_out <= 12'b0;

       end else if (en) begin
           address_out <= address_in;
       end
   end
endmodule
module pc(clock, reset, en, address_in, address_out);

	input clock, reset, en;
	input[11:0] address_in;
	output[11:0] address_out;
	

	reg [11:0] address_out;
   initial
   begin
       address_out = 12'b0;
   end


   always @(posedge clock or posedge reset) begin

       if (reset) begin
           address_out <= 12'b0;

       end else if (en) begin
           address_out <= address_in;
       end
   end
endmodule