data/full_repos/permissive/520811519/rtl/final_video/A5004_3.v
data/verilator_xmls/8b55d501-a719-4fcb-82fc-5dff39cae3db.xml
module A5004_3 (

    input wire SD31,
    input wire SD0,
    input wire SLD7,
    input wire SLD0,
    input wire SLD1,
    input wire SLD2,
    input wire L2D0,
    input wire L2D1,
    input wire L2D2,
    input wire i11,
    input wire SD31_r,
    input wire SD30_ANDr,

    output wire COLBANK5,
    output wire LAYER_SELA,
    output wire LAYER_SELB,
    output wire COLBANK3,
    output wire COLBANK4,
    output wire SD30_AND
);
    wire SD31_r_neg;
    wire SD31_neg;
    wire SD30_ANDr_neg;
    wire SD0_neg;
    wire SLBD7_neg;
    wire SLD7_neg;
    wire SLD0_neg;
    wire SLD1_neg;
    wire SLD2_neg;
    wire L2D2_neg;
    wire L2D1_neg;
    wire L2D0_neg;
    wire i11_neg;

    assign  SD31_r_neg    = ~SD31_r;
    assign  SD30_ANDr_neg = ~SD30_ANDr;
    assign  SLD7_neg      = ~SLD7;
    assign  SLD0_neg      = ~SLD0;
    assign  SLD1_neg      = ~SLD1;
    assign  SLD2_neg      = ~SLD2;
    assign  L2D2_neg      = ~L2D2;
    assign  L2D1_neg      = ~L2D1;
    assign  L2D0_neg      = ~L2D0;
    assign  i11_neg       = ~i11;
    assign  SD31_neg      = ~SD31;
    assign  SD0_neg       = ~SD0;
     
    assign  COLBANK5   = ~((SD30_ANDr_neg                                                                               )|
                           (               SLD7_neg & SLD0_neg & SLD1 & SLD2 &                                SD31_r_neg)|
                           (                          SLD0_neg & SLD1 & SLD2 &            L2D1 & L2D2 & i11 & SD31_r_neg)|
                           (                                     SLD1 & SLD2 & L2D0_neg & L2D1 & L2D2 & i11 & SD31_r_neg));
                                               

    assign  LAYER_SELA = ~((SLD7 & L2D1_neg & SD31_r_neg)|
                           (SLD7 & L2D2_neg & SD31_r_neg)|
                           (SLD7 & i11_neg  & SD31_r_neg)|
                           (SLD1 & SLD2     & SD31_r_neg));  

    assign  LAYER_SELB = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg));

    assign  COLBANK3   = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg)|
                           (                     LAYER_SELA & SD31_r_neg));

    assign  COLBANK4   = ~((SLD1_neg & SD31_r_neg)|
                           (SLD2_neg & SD31_r_neg)|
                           (L2D1_neg & SD31_r_neg)|
                           (L2D2_neg & SD31_r_neg)|
                           (i11_neg  & SD31_r_neg));   

    assign  SD30_AND   = ~(SD31_neg & SD0_neg);
endmodule
module A5004_3 (

    input wire SD31,
    input wire SD0,
    input wire SLD7,
    input wire SLD0,
    input wire SLD1,
    input wire SLD2,
    input wire L2D0,
    input wire L2D1,
    input wire L2D2,
    input wire i11,
    input wire SD31_r,
    input wire SD30_ANDr,

    output wire COLBANK5,
    output wire LAYER_SELA,
    output wire LAYER_SELB,
    output wire COLBANK3,
    output wire COLBANK4,
    output wire SD30_AND
);

    wire SD31_r_neg;
    wire SD31_neg;
    wire SD30_ANDr_neg;
    wire SD0_neg;
    wire SLBD7_neg;
    wire SLD7_neg;
    wire SLD0_neg;
    wire SLD1_neg;
    wire SLD2_neg;
    wire L2D2_neg;
    wire L2D1_neg;
    wire L2D0_neg;
    wire i11_neg;

    assign  SD31_r_neg    = ~SD31_r;
    assign  SD30_ANDr_neg = ~SD30_ANDr;
    assign  SLD7_neg      = ~SLD7;
    assign  SLD0_neg      = ~SLD0;
    assign  SLD1_neg      = ~SLD1;
    assign  SLD2_neg      = ~SLD2;
    assign  L2D2_neg      = ~L2D2;
    assign  L2D1_neg      = ~L2D1;
    assign  L2D0_neg      = ~L2D0;
    assign  i11_neg       = ~i11;
    assign  SD31_neg      = ~SD31;
    assign  SD0_neg       = ~SD0;
     
    assign  COLBANK5   = ~((SD30_ANDr_neg                                                                               )|
                           (               SLD7_neg & SLD0_neg & SLD1 & SLD2 &                                SD31_r_neg)|
                           (                          SLD0_neg & SLD1 & SLD2 &            L2D1 & L2D2 & i11 & SD31_r_neg)|
                           (                                     SLD1 & SLD2 & L2D0_neg & L2D1 & L2D2 & i11 & SD31_r_neg));
                                               

    assign  LAYER_SELA = ~((SLD7 & L2D1_neg & SD31_r_neg)|
                           (SLD7 & L2D2_neg & SD31_r_neg)|
                           (SLD7 & i11_neg  & SD31_r_neg)|
                           (SLD1 & SLD2     & SD31_r_neg));  

    assign  LAYER_SELB = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg));

    assign  COLBANK3   = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg)|
                           (                     LAYER_SELA & SD31_r_neg));

    assign  COLBANK4   = ~((SLD1_neg & SD31_r_neg)|
                           (SLD2_neg & SD31_r_neg)|
                           (L2D1_neg & SD31_r_neg)|
                           (L2D2_neg & SD31_r_neg)|
                           (i11_neg  & SD31_r_neg));   

    assign  SD30_AND   = ~(SD31_neg & SD0_neg);
endmodule