data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #30 din_bit = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #20 din_bit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100 $stop;\n  ^\n%Error: data/full_repos/permissive/468612001/Week06/mealy_fsm/tb_mealy_fsm.v:5: Cannot find file containing module: \'mealy_fsm\'\n mealy_fsm u0(clk, rst, din_bit, dout_bit);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week06/mealy_fsm,data/full_repos/permissive/468612001/mealy_fsm\n             data/full_repos/permissive/468612001/Week06/mealy_fsm,data/full_repos/permissive/468612001/mealy_fsm.v\n             data/full_repos/permissive/468612001/Week06/mealy_fsm,data/full_repos/permissive/468612001/mealy_fsm.sv\n             mealy_fsm\n             mealy_fsm.v\n             mealy_fsm.sv\n             obj_dir/mealy_fsm\n             obj_dir/mealy_fsm.v\n             obj_dir/mealy_fsm.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mealy_fsm();
	reg clk, rst, din_bit;
	wire dout_bit;
	
	mealy_fsm u0(clk, rst, din_bit, dout_bit);
	
	initial begin
		rst = 1;
		#15 rst = 0;
		#25 rst = 1;
	end
	
	initial begin
		clk = 0;
		forever
		#10 clk = ~clk;
	end
	
	initial begin
		din_bit = 0;
		#30 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#100 $stop;
	end
endmodule
module tb_mealy_fsm();

	reg clk, rst, din_bit;
	wire dout_bit;
	
	mealy_fsm u0(clk, rst, din_bit, dout_bit);
	
	initial begin
		rst = 1;
		#15 rst = 0;
		#25 rst = 1;
	end
	
	initial begin
		clk = 0;
		forever
		#10 clk = ~clk;
	end
	
	initial begin
		din_bit = 0;
		#30 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#20 din_bit = 1;
		#20 din_bit = 0;
		#20 din_bit = 1;
		#100 $stop;
	end
endmodule