data/full_repos/permissive/523038000/lab14/vga_initials_top.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/523038000/lab14/vga_initials_top.v:54: Little bit endian vector: MSB < LSB of bit range: 0:31\nwire [0:31] M;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/523038000/lab14/vga_initials_top.v:59: Cannot find file containing module: \'clkdiv\'\nclkdiv U1  (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/clkdiv\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/clkdiv.v\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/clkdiv.sv\n             clkdiv\n             clkdiv.v\n             clkdiv.sv\n             obj_dir/clkdiv\n             obj_dir/clkdiv.v\n             obj_dir/clkdiv.sv\n%Error: data/full_repos/permissive/523038000/lab14/vga_initials_top.v:65: Cannot find file containing module: \'vga_640x480\'\nvga_640x480 U2 (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/523038000/lab14/vga_initials_top.v:75: Cannot find file containing module: \'vga_initials\'\nvga_initials U3 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/523038000/lab14/vga_initials_top.v:88: Cannot find file containing module: \'prom_DMH\'\nprom_DMH U4 (\n^~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module vga_initials_top(
input wire clk,
input wire  reset,
input wire [7:0] key_code,
output wire hsync,
output wire vsync,
output wire [2:0] red,
output wire [2:0] green,
output wire [1:0] blue
);


wire clr, clk25,vidon;
wire [9:0] hc,vc;
wire [0:31] M;
wire [3:0] rom_addr4;

assign clr = reset;

clkdiv U1 	(
		.mclk(clk),
		.clr(clr),
		.clk25(clk25)
				);
				
vga_640x480 U2	(
		.clk(clk25),
		.clr(clr),
		.hsync(hsync),
		.vsync(vsync),
		.hc(hc),
		.vc(vc),
		.vidon(vidon)
					);
					
vga_initials U3	(
		.vidon(vidon),
		.hc(hc),
		.vc(vc),
		.M(M),
		.sw(8'b10101010),
		.rom_addr4(rom_addr4),
		.red(red),
		.green(green),
		.blue(blue)
						);
						
						
prom_DMH U4	(
		.addr(rom_addr4),
		.M(M),
		.key_code(key_code)
				);


endmodule
module vga_initials_top(
input wire clk,
input wire  reset,
input wire [7:0] key_code,
output wire hsync,
output wire vsync,
output wire [2:0] red,
output wire [2:0] green,
output wire [1:0] blue
);



wire clr, clk25,vidon;
wire [9:0] hc,vc;
wire [0:31] M;
wire [3:0] rom_addr4;

assign clr = reset;

clkdiv U1 	(
		.mclk(clk),
		.clr(clr),
		.clk25(clk25)
				);
				
vga_640x480 U2	(
		.clk(clk25),
		.clr(clr),
		.hsync(hsync),
		.vsync(vsync),
		.hc(hc),
		.vc(vc),
		.vidon(vidon)
					);
					
vga_initials U3	(
		.vidon(vidon),
		.hc(hc),
		.vc(vc),
		.M(M),
		.sw(8'b10101010),
		.rom_addr4(rom_addr4),
		.red(red),
		.green(green),
		.blue(blue)
						);
						
						
prom_DMH U4	(
		.addr(rom_addr4),
		.M(M),
		.key_code(key_code)
				);


endmodule