data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v
1: b'%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("nano_sc_system.dump");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(4, nano_sc_system);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v:30: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/nano_sc_system.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20 clock=~clock;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nano_sc_system();
wire 	[31:0]	p_address;
wire 	[31:0]	p_data;
wire	[31:0]	d_address;
wire		mem_wr;
wire	[31:0]	d_data;
reg		clock;
reg		nreset;

nanocpu	CPU(p_address,p_data,d_address,d_data,mem_wr,clock,nreset);
rom 	PROGMEM(p_data,p_address[28:2]);
memory 	DATAMEM(d_data,d_address[28:2],mem_wr,clock);

initial
begin
	$dumpfile("nano_sc_system.dump");
	$dumpvars(4, nano_sc_system);

	clock=0;
	nreset=0;
	#40;
	nreset=1;
	#2000;
	$finish;
end

always
begin : CLOCK
	#20	clock=~clock;
end


endmodule
module nano_sc_system();

wire 	[31:0]	p_address;
wire 	[31:0]	p_data;
wire	[31:0]	d_address;
wire		mem_wr;
wire	[31:0]	d_data;
reg		clock;
reg		nreset;

nanocpu	CPU(p_address,p_data,d_address,d_data,mem_wr,clock,nreset);
rom 	PROGMEM(p_data,p_address[28:2]);
memory 	DATAMEM(d_data,d_address[28:2],mem_wr,clock);

initial
begin
	$dumpfile("nano_sc_system.dump");
	$dumpvars(4, nano_sc_system);

	clock=0;
	nreset=0;
	#40;
	nreset=1;
	#2000;
	$finish;
end

always
begin : CLOCK
	#20	clock=~clock;
end


endmodule