data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/Decoder4.v
data/verilator_xmls/83e50317-43c4-484f-b7df-61ff24dbffcb.xml
module Decoder4(
    output reg [3:0] out,
    input [1:0] sel
);
    always @(sel)
    case (sel)
        2'd0 : out = 4'b0001;
        2'd1 : out = 4'b0010;
        2'd2 : out = 4'b0100;
        2'd3 : out = 4'b1000;
    endcase
endmodule
module Decoder4(
    output reg [3:0] out,
    input [1:0] sel
);

    always @(sel)
    case (sel)
        2'd0 : out = 4'b0001;
        2'd1 : out = 4'b0010;
        2'd2 : out = 4'b0100;
        2'd3 : out = 4'b1000;
    endcase
endmodule