data/full_repos/permissive/423547971/FPGA Projects/How to Control 7 Segment Display on Basys 3/top.v
1: b'%Error: Cannot find file containing module: Projects/How\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/How\n             data/full_repos/permissive/423547971/FPGA/Projects/How.v\n             data/full_repos/permissive/423547971/FPGA/Projects/How.sv\n             Projects/How\n             Projects/How.v\n             Projects/How.sv\n             obj_dir/Projects/How\n             obj_dir/Projects/How.v\n             obj_dir/Projects/How.sv\n%Error: Cannot find file containing module: to\n%Error: Cannot find file containing module: Control\n%Error: Cannot find file containing module: 7\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: 3/top.v\n%Error: Exiting due to 11 error(s)\n'
module top(
    input clk_100MHz,
    input reset,
    output [0:6] seg,
    output [3:0] digit
    );
    

    wire w_10Hz;
    wire [3:0] w_1s, w_10s, w_100s, w_1000s;
    

    tenHz_gen hz10(.clk_100MHz(clk_100MHz), .reset(reset), .clk_10Hz(w_10Hz));
    
    digits digs(.clk_10Hz(w_10Hz), .reset(reset), .ones(w_1s), 
                .tens(w_10s), .hundreds(w_100s), .thousands(w_1000s));
    
    seg7_control seg7(.clk_100MHz(clk_100MHz), .reset(reset), .ones(w_1s), .tens(w_10s),
                      .hundreds(w_100s), .thousands(w_1000s), .seg(seg), .digit(digit));
  
endmodule
module top(
    input clk_100MHz,
    input reset,
    output [0:6] seg,
    output [3:0] digit
    );

    

    wire w_10Hz;
    wire [3:0] w_1s, w_10s, w_100s, w_1000s;
    

    tenHz_gen hz10(.clk_100MHz(clk_100MHz), .reset(reset), .clk_10Hz(w_10Hz));
    
    digits digs(.clk_10Hz(w_10Hz), .reset(reset), .ones(w_1s), 
                .tens(w_10s), .hundreds(w_100s), .thousands(w_1000s));
    
    seg7_control seg7(.clk_100MHz(clk_100MHz), .reset(reset), .ones(w_1s), .tens(w_10s),
                      .hundreds(w_100s), .thousands(w_1000s), .seg(seg), .digit(digit));
  
endmodule