data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module managerx(
	input clk,
	input dclk,
	input rst,
	
	input [5:0] cmd,
	input [31:0] arg,
	input [6:0] crc,
	input sta,
	input sta40,
	input readit,
	input init,
	input closex,
	
	output rdy,
	output rdyread,
	
	output[7:0] in,
	output start,
	output csz,
	
	input[7:0] into,
	input ready
);

wire rdy_in;

wire rdyread_in;

rdyspibuffer rsbr(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	.in(rdyread_in),
	
	.out(rdyread)
);

rdyspibuffer rsb(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	.in(rdy_in),
	
	.out(rdy)
);

wire n_init;

initbuffer ibuf(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.init(init),
	.n_init(n_init)
);

wire n_close;

initbuffer iclo(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.init(closex),
	.n_init(n_close)
);

wire[4:0] p_tim;
wire[2:0] p_ttim;

wire[5:0] f_cmd;
wire[31:0] f_arg;
wire[6:0] f_crc;

wire start3;
wire[7:0] in3;
wire rdy3;

wire f_c;
wire f_answ40;

wire[3:0] f_timinit;
	
wire start2;
wire[7:0] in2;
wire rdy2;

wire start4;
wire[7:0] in4;
wire rdy4;

close clo(
	.clk(dclk),
	.rst(rst),
	
	.closex(n_close),
	
	.ready(ready),
	
	.out(into),
	
	.start4(start4),
	.in4(in4),
	
	.rdy4(rdy4)
);
	
starteri si(
	.clk(dclk),
	.rst(rst),
	
	.n_init(n_init),
	.ready(ready),
	
	.csz(csz),
	.f_timinit(f_timinit),
	
	.start2(start2),
	.in2(in2),
	.rdy2(rdy2)

);

saverx sa(
	.clk(dclk),
	.rst(rst),
	
	.arg(arg),
	.sta(sta),
	.sta40(sta40),
	.ready(ready),
	
	.start3(start3),
	.in3(in3),
	.rdy3(rdy3)

);






starter ssa(
	.clk(dclk),
	.rst(rst),
	
	.cmd(cmd),
	.arg(arg),
	.crc(crc),
	.sta(sta),
	.sta40(sta40),
	.readit(readit),
	
	.n_init(n_init),
	.f_startsave(f_startsave),
	
	.p_tim(p_tim),
	.p_ttim(p_ttim),

	.f_cmd(f_cmd),
	.f_arg(f_arg),
	.f_crc(f_crc),

	.f_answ40(f_answ40),
	.f_c(f_c),
	
	.f_timinit(f_timinit)
);

wire start1;
wire[7:0] in1;
wire rdy1;

sender sen(
	.clk(dclk),
	.rst(rst),

	.f_cmd(f_cmd),
	.f_arg(f_arg),
	.f_crc(f_crc),
	.f_c(f_c),
	.f_answ40(f_answ40),
	
	.ready(ready),
	.into(into),
	
	.p_tim(p_tim),
	.p_ttim(p_ttim),
	
	.rdyread_in(rdyread_in),
	
	.start1(start1),
	.in1(in1),
	.rdy1(rdy1)

);

assign rdy_in = rdy1 | rdy2 | rdy3 | rdy4;
assign in = in1 | in2 | in3 | in4;
assign start = start1 | start2 | start3 | start4;

endmodule
module managerx(
	input clk,
	input dclk,
	input rst,
	
	input [5:0] cmd,
	input [31:0] arg,
	input [6:0] crc,
	input sta,
	input sta40,
	input readit,
	input init,
	input closex,
	
	output rdy,
	output rdyread,
	
	output[7:0] in,
	output start,
	output csz,
	
	input[7:0] into,
	input ready
);


wire rdy_in;

wire rdyread_in;

rdyspibuffer rsbr(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	.in(rdyread_in),
	
	.out(rdyread)
);

rdyspibuffer rsb(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	.in(rdy_in),
	
	.out(rdy)
);

wire n_init;

initbuffer ibuf(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.init(init),
	.n_init(n_init)
);

wire n_close;

initbuffer iclo(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.init(closex),
	.n_init(n_close)
);

wire[4:0] p_tim;
wire[2:0] p_ttim;

wire[5:0] f_cmd;
wire[31:0] f_arg;
wire[6:0] f_crc;

wire start3;
wire[7:0] in3;
wire rdy3;

wire f_c;
wire f_answ40;

wire[3:0] f_timinit;
	
wire start2;
wire[7:0] in2;
wire rdy2;

wire start4;
wire[7:0] in4;
wire rdy4;

close clo(
	.clk(dclk),
	.rst(rst),
	
	.closex(n_close),
	
	.ready(ready),
	
	.out(into),
	
	.start4(start4),
	.in4(in4),
	
	.rdy4(rdy4)
);
	
starteri si(
	.clk(dclk),
	.rst(rst),
	
	.n_init(n_init),
	.ready(ready),
	
	.csz(csz),
	.f_timinit(f_timinit),
	
	.start2(start2),
	.in2(in2),
	.rdy2(rdy2)

);

saverx sa(
	.clk(dclk),
	.rst(rst),
	
	.arg(arg),
	.sta(sta),
	.sta40(sta40),
	.ready(ready),
	
	.start3(start3),
	.in3(in3),
	.rdy3(rdy3)

);






starter ssa(
	.clk(dclk),
	.rst(rst),
	
	.cmd(cmd),
	.arg(arg),
	.crc(crc),
	.sta(sta),
	.sta40(sta40),
	.readit(readit),
	
	.n_init(n_init),
	.f_startsave(f_startsave),
	
	.p_tim(p_tim),
	.p_ttim(p_ttim),

	.f_cmd(f_cmd),
	.f_arg(f_arg),
	.f_crc(f_crc),

	.f_answ40(f_answ40),
	.f_c(f_c),
	
	.f_timinit(f_timinit)
);

wire start1;
wire[7:0] in1;
wire rdy1;

sender sen(
	.clk(dclk),
	.rst(rst),

	.f_cmd(f_cmd),
	.f_arg(f_arg),
	.f_crc(f_crc),
	.f_c(f_c),
	.f_answ40(f_answ40),
	
	.ready(ready),
	.into(into),
	
	.p_tim(p_tim),
	.p_ttim(p_ttim),
	
	.rdyread_in(rdyread_in),
	
	.start1(start1),
	.in1(in1),
	.rdy1(rdy1)

);

assign rdy_in = rdy1 | rdy2 | rdy3 | rdy4;
assign in = in1 | in2 | in3 | in4;
assign start = start1 | start2 | start3 | start4;

endmodule