data/full_repos/permissive/518576684/test_bench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518576684/test_bench.v:14: Unsupported: Ignoring delay on this delayed statement.\ninitial repeat (260) #10 clk= ~clk;\n                     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518576684/test_bench.v:15: Unsupported: Ignoring delay on this delayed statement.\ninitial repeat (200) #12 w= $random;\n                     ^\n%Error: data/full_repos/permissive/518576684/test_bench.v:7: Cannot find file containing module: \'Top_module\'\nTop_module DUT( w,clk,p);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518576684,data/full_repos/permissive/518576684/Top_module\n             data/full_repos/permissive/518576684,data/full_repos/permissive/518576684/Top_module.v\n             data/full_repos/permissive/518576684,data/full_repos/permissive/518576684/Top_module.sv\n             Top_module\n             Top_module.v\n             Top_module.sv\n             obj_dir/Top_module\n             obj_dir/Top_module.v\n             obj_dir/Top_module.sv\n%Warning-WIDTH: data/full_repos/permissive/518576684/test_bench.v:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                    : ... In instance Top_module_tb\ninitial repeat (200) #12 w= $random;\n                          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top_module_tb();
reg w,clk;
wire p;

Top_module DUT( w,clk,p);

initial
begin
clk=0; w=0;
end

initial repeat (260) #10 clk= ~clk;
initial repeat (200) #12 w= $random;

endmodule
module Top_module_tb();

reg w,clk;
wire p;

Top_module DUT( w,clk,p);

initial
begin
clk=0; w=0;
end

initial repeat (260) #10 clk= ~clk;
initial repeat (200) #12 w= $random;

endmodule