data/full_repos/permissive/461141714/src/Single Cycle CPU/cpu_evaluation_tb.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/cpu_evaluation_tb.v\n%Error: Exiting due to 4 error(s)\n'
module tb_cpu();


  wire readM;
  wire [`WORD_SIZE-1:0] address;
  wire [`WORD_SIZE-1:0] data;
  reg inputReady;
  reg reset_n;
  reg clk;
  

  wire [`WORD_SIZE-1:0] num_inst;
  wire [`WORD_SIZE-1:0] output_port;


  reg [`WORD_SIZE-1:0] outputData;


  cpu UUT (readM, address, data, inputReady,
  			reset_n, clk, num_inst, output_port);


  initial begin
    clk = 0;
	inputReady = 0;

    reset_n = 1;
    #(`PERIOD1/4) reset_n = 0;
    #`PERIOD1 reset_n = 1;
  end


  always #(`PERIOD1/2)clk = ~clk;


  reg [`WORD_SIZE-1:0] memory [0:`MEMORY_SIZE-1];


  assign data = readM ? outputData : `WORD_SIZE'bz;
  always begin
    outputData = `WORD_SIZE'bz;
    #`PERIOD1;
    forever begin
      wait (readM == 1);
      #`READ_DELAY;
      outputData = memory[address];
	  inputReady = 1;
      #(`STABLE_TIME);
      outputData = `WORD_SIZE'bz;
	  inputReady = 0;
    end
  end
  

  initial begin
    #`PERIOD1;
	memory[0]  = 16'h6000;
	memory[1]  = 16'h6101;
 	memory[2]  = 16'h6202;
	memory[3]  = 16'h6303;
	memory[4]  = 16'hf01c;
	memory[5]  = 16'hf41c;
	memory[6]  = 16'hf81c;
	memory[7]  = 16'hfc1c;
	memory[8]  = 16'h4204;
	memory[9]  = 16'h47fc;
	memory[10] = 16'hf81c;
	memory[11] = 16'hfc1c;
	memory[12] = 16'hf6c0;
	memory[13] = 16'hf180;
	memory[14] = 16'hf81c;
	memory[15] = 16'hfc1c;
	memory[16] = 16'h9015;
	memory[17] = 16'hf01c;
	memory[18] = 16'hf180;
	memory[19] = 16'hf180;
	memory[20] = 16'hf180;
	memory[21] = 16'h6000;
	memory[22] = 16'h4000;
	memory[23] = 16'hfd80;
	memory[24] = 16'hf01c;
	memory[25] = 16'hf41c;
	memory[26] = 16'hf81c;
	memory[27] = 16'hfc1c;
	
	#(`PERIOD1*30);
   $finish();
  end
  



  always @(posedge clk) begin
     $display ("num_inst %d", num_inst);
     case (num_inst)
        16'd5:
           if (output_port == 16'd0)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd0);
        16'd6:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd7:
           if (output_port == 16'd512)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd512);
        16'd8:
           if (output_port == 16'd768)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd768);
        16'd11:
           if (output_port == 16'd4)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd4);
        16'd12:
           if (output_port == 16'd252)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd252);
        16'd15:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd16:
           if (output_port == 16'd260)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd260);
        16'd21:
           if (output_port == 16'd0)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd0);
        16'd22:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd23:
           if (output_port == 16'd516)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd516);
        16'd24:
           if (output_port == 16'd260)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd260);
     endcase
  end
endmodule
module tb_cpu();



  wire readM;
  wire [`WORD_SIZE-1:0] address;
  wire [`WORD_SIZE-1:0] data;
  reg inputReady;
  reg reset_n;
  reg clk;
  

  wire [`WORD_SIZE-1:0] num_inst;
  wire [`WORD_SIZE-1:0] output_port;


  reg [`WORD_SIZE-1:0] outputData;


  cpu UUT (readM, address, data, inputReady,
  			reset_n, clk, num_inst, output_port);


  initial begin
    clk = 0;
	inputReady = 0;

    reset_n = 1;
    #(`PERIOD1/4) reset_n = 0;
    #`PERIOD1 reset_n = 1;
  end


  always #(`PERIOD1/2)clk = ~clk;


  reg [`WORD_SIZE-1:0] memory [0:`MEMORY_SIZE-1];


  assign data = readM ? outputData : `WORD_SIZE'bz;
  always begin
    outputData = `WORD_SIZE'bz;
    #`PERIOD1;
    forever begin
      wait (readM == 1);
      #`READ_DELAY;
      outputData = memory[address];
	  inputReady = 1;
      #(`STABLE_TIME);
      outputData = `WORD_SIZE'bz;
	  inputReady = 0;
    end
  end
  

  initial begin
    #`PERIOD1;
	memory[0]  = 16'h6000;
	memory[1]  = 16'h6101;
 	memory[2]  = 16'h6202;
	memory[3]  = 16'h6303;
	memory[4]  = 16'hf01c;
	memory[5]  = 16'hf41c;
	memory[6]  = 16'hf81c;
	memory[7]  = 16'hfc1c;
	memory[8]  = 16'h4204;
	memory[9]  = 16'h47fc;
	memory[10] = 16'hf81c;
	memory[11] = 16'hfc1c;
	memory[12] = 16'hf6c0;
	memory[13] = 16'hf180;
	memory[14] = 16'hf81c;
	memory[15] = 16'hfc1c;
	memory[16] = 16'h9015;
	memory[17] = 16'hf01c;
	memory[18] = 16'hf180;
	memory[19] = 16'hf180;
	memory[20] = 16'hf180;
	memory[21] = 16'h6000;
	memory[22] = 16'h4000;
	memory[23] = 16'hfd80;
	memory[24] = 16'hf01c;
	memory[25] = 16'hf41c;
	memory[26] = 16'hf81c;
	memory[27] = 16'hfc1c;
	
	#(`PERIOD1*30);
   $finish();
  end
  



  always @(posedge clk) begin
     $display ("num_inst %d", num_inst);
     case (num_inst)
        16'd5:
           if (output_port == 16'd0)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd0);
        16'd6:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd7:
           if (output_port == 16'd512)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd512);
        16'd8:
           if (output_port == 16'd768)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd768);
        16'd11:
           if (output_port == 16'd4)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd4);
        16'd12:
           if (output_port == 16'd252)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd252);
        16'd15:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd16:
           if (output_port == 16'd260)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd260);
        16'd21:
           if (output_port == 16'd0)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd0);
        16'd22:
           if (output_port == 16'd256)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd256);
        16'd23:
           if (output_port == 16'd516)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd516);
        16'd24:
           if (output_port == 16'd260)
              $display ("PASS");
           else
              $display ("FAIL[%d/%d]",output_port, 16'd260);
     endcase
  end
endmodule