data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MUX169.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MUX169.v:180: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                                    : ... In instance MUX_169\n  Data=16\'b0;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module MUX_169 #(parameter INPUT_DATA_WIDTH =8, BITWIDTH_SEL=9)(



input [BITWIDTH_SEL-1:0] MUX_selector,


input [INPUT_DATA_WIDTH-1:0] MUX_In0,
input [INPUT_DATA_WIDTH-1:0] MUX_In1,
input [INPUT_DATA_WIDTH-1:0] MUX_In2,
input [INPUT_DATA_WIDTH-1:0] MUX_In3,
input [INPUT_DATA_WIDTH-1:0] MUX_In4,
input [INPUT_DATA_WIDTH-1:0] MUX_In5,
input [INPUT_DATA_WIDTH-1:0] MUX_In6,
input [INPUT_DATA_WIDTH-1:0] MUX_In7,
input [INPUT_DATA_WIDTH-1:0] MUX_In8,
input [INPUT_DATA_WIDTH-1:0] MUX_In9,
input [INPUT_DATA_WIDTH-1:0] MUX_In10,
input [INPUT_DATA_WIDTH-1:0] MUX_In11,
input [INPUT_DATA_WIDTH-1:0] MUX_In12,
input [INPUT_DATA_WIDTH-1:0] MUX_In13,
input [INPUT_DATA_WIDTH-1:0] MUX_In14,
input [INPUT_DATA_WIDTH-1:0] MUX_In15,
input [INPUT_DATA_WIDTH-1:0] MUX_In16,
input [INPUT_DATA_WIDTH-1:0] MUX_In17,
input [INPUT_DATA_WIDTH-1:0] MUX_In18,
input [INPUT_DATA_WIDTH-1:0] MUX_In19,
input [INPUT_DATA_WIDTH-1:0] MUX_In20,
input [INPUT_DATA_WIDTH-1:0] MUX_In21,
input [INPUT_DATA_WIDTH-1:0] MUX_In22,
input [INPUT_DATA_WIDTH-1:0] MUX_In23,
input [INPUT_DATA_WIDTH-1:0] MUX_In24,
input [INPUT_DATA_WIDTH-1:0] MUX_In25,
input [INPUT_DATA_WIDTH-1:0] MUX_In26,
input [INPUT_DATA_WIDTH-1:0] MUX_In27,
input [INPUT_DATA_WIDTH-1:0] MUX_In28,
input [INPUT_DATA_WIDTH-1:0] MUX_In29,
input [INPUT_DATA_WIDTH-1:0] MUX_In30,
input [INPUT_DATA_WIDTH-1:0] MUX_In31,
input [INPUT_DATA_WIDTH-1:0] MUX_In32,
input [INPUT_DATA_WIDTH-1:0] MUX_In33,
input [INPUT_DATA_WIDTH-1:0] MUX_In34,
input [INPUT_DATA_WIDTH-1:0] MUX_In35,



output[INPUT_DATA_WIDTH-1:0]  MUX_OUTPUT

);



reg [INPUT_DATA_WIDTH-1:0] Data;

always@(*)
begin
	case(MUX_selector)
		9'd0: Data=MUX_In0;
		9'd1: Data=MUX_In1;
		9'd2: Data=MUX_In2;
		9'd3: Data=MUX_In3;
		9'd4: Data=MUX_In4;
		9'd5: Data=MUX_In5;
		9'd6: Data=MUX_In6;
		9'd7: Data=MUX_In7;
		9'd8: Data=MUX_In8;
		9'd9: Data=MUX_In9;
		9'd10: Data=MUX_In10;
		9'd11: Data=MUX_In11;
		9'd12: Data=MUX_In12;
		9'd13: Data=MUX_In13;
		9'd14: Data=MUX_In14;
		9'd15: Data=MUX_In15;
		9'd16: Data=MUX_In16;
		9'd17: Data=MUX_In17;
		9'd18: Data=MUX_In18;
		9'd19: Data=MUX_In19;
		9'd20: Data=MUX_In20;
		9'd21: Data=MUX_In21;
		9'd22: Data=MUX_In22;
		9'd23: Data=MUX_In23;
		9'd24: Data=MUX_In24;
		9'd25: Data=MUX_In25;
		9'd26: Data=MUX_In26;
		9'd27: Data=MUX_In27;
		9'd28: Data=MUX_In28;
		9'd29: Data=MUX_In29;
		9'd30: Data=MUX_In30;
		9'd31: Data=MUX_In31;
		9'd32: Data=MUX_In32;
		9'd33: Data=MUX_In33;
		9'd34: Data=MUX_In34;
		9'd35: Data=MUX_In35;
			
	default:
		Data=16'b0;
		
	endcase
end


assign MUX_OUTPUT=Data;



endmodule
module MUX_169 #(parameter INPUT_DATA_WIDTH =8, BITWIDTH_SEL=9)(



input [BITWIDTH_SEL-1:0] MUX_selector,


input [INPUT_DATA_WIDTH-1:0] MUX_In0,
input [INPUT_DATA_WIDTH-1:0] MUX_In1,
input [INPUT_DATA_WIDTH-1:0] MUX_In2,
input [INPUT_DATA_WIDTH-1:0] MUX_In3,
input [INPUT_DATA_WIDTH-1:0] MUX_In4,
input [INPUT_DATA_WIDTH-1:0] MUX_In5,
input [INPUT_DATA_WIDTH-1:0] MUX_In6,
input [INPUT_DATA_WIDTH-1:0] MUX_In7,
input [INPUT_DATA_WIDTH-1:0] MUX_In8,
input [INPUT_DATA_WIDTH-1:0] MUX_In9,
input [INPUT_DATA_WIDTH-1:0] MUX_In10,
input [INPUT_DATA_WIDTH-1:0] MUX_In11,
input [INPUT_DATA_WIDTH-1:0] MUX_In12,
input [INPUT_DATA_WIDTH-1:0] MUX_In13,
input [INPUT_DATA_WIDTH-1:0] MUX_In14,
input [INPUT_DATA_WIDTH-1:0] MUX_In15,
input [INPUT_DATA_WIDTH-1:0] MUX_In16,
input [INPUT_DATA_WIDTH-1:0] MUX_In17,
input [INPUT_DATA_WIDTH-1:0] MUX_In18,
input [INPUT_DATA_WIDTH-1:0] MUX_In19,
input [INPUT_DATA_WIDTH-1:0] MUX_In20,
input [INPUT_DATA_WIDTH-1:0] MUX_In21,
input [INPUT_DATA_WIDTH-1:0] MUX_In22,
input [INPUT_DATA_WIDTH-1:0] MUX_In23,
input [INPUT_DATA_WIDTH-1:0] MUX_In24,
input [INPUT_DATA_WIDTH-1:0] MUX_In25,
input [INPUT_DATA_WIDTH-1:0] MUX_In26,
input [INPUT_DATA_WIDTH-1:0] MUX_In27,
input [INPUT_DATA_WIDTH-1:0] MUX_In28,
input [INPUT_DATA_WIDTH-1:0] MUX_In29,
input [INPUT_DATA_WIDTH-1:0] MUX_In30,
input [INPUT_DATA_WIDTH-1:0] MUX_In31,
input [INPUT_DATA_WIDTH-1:0] MUX_In32,
input [INPUT_DATA_WIDTH-1:0] MUX_In33,
input [INPUT_DATA_WIDTH-1:0] MUX_In34,
input [INPUT_DATA_WIDTH-1:0] MUX_In35,



output[INPUT_DATA_WIDTH-1:0]  MUX_OUTPUT

);




reg [INPUT_DATA_WIDTH-1:0] Data;

always@(*)
begin
	case(MUX_selector)
		9'd0: Data=MUX_In0;
		9'd1: Data=MUX_In1;
		9'd2: Data=MUX_In2;
		9'd3: Data=MUX_In3;
		9'd4: Data=MUX_In4;
		9'd5: Data=MUX_In5;
		9'd6: Data=MUX_In6;
		9'd7: Data=MUX_In7;
		9'd8: Data=MUX_In8;
		9'd9: Data=MUX_In9;
		9'd10: Data=MUX_In10;
		9'd11: Data=MUX_In11;
		9'd12: Data=MUX_In12;
		9'd13: Data=MUX_In13;
		9'd14: Data=MUX_In14;
		9'd15: Data=MUX_In15;
		9'd16: Data=MUX_In16;
		9'd17: Data=MUX_In17;
		9'd18: Data=MUX_In18;
		9'd19: Data=MUX_In19;
		9'd20: Data=MUX_In20;
		9'd21: Data=MUX_In21;
		9'd22: Data=MUX_In22;
		9'd23: Data=MUX_In23;
		9'd24: Data=MUX_In24;
		9'd25: Data=MUX_In25;
		9'd26: Data=MUX_In26;
		9'd27: Data=MUX_In27;
		9'd28: Data=MUX_In28;
		9'd29: Data=MUX_In29;
		9'd30: Data=MUX_In30;
		9'd31: Data=MUX_In31;
		9'd32: Data=MUX_In32;
		9'd33: Data=MUX_In33;
		9'd34: Data=MUX_In34;
		9'd35: Data=MUX_In35;
			
	default:
		Data=16'b0;
		
	endcase
end


assign MUX_OUTPUT=Data;



endmodule