data/full_repos/permissive/498129202/src/decoder.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/498129202/src/decoder.v:5: Little bit endian vector: MSB < LSB of bit range: 0:9\noutput reg [0:9] s;\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module decoder (c, s);


input [3:0] c;
output reg [0:9] s;

always @ (c) begin
    s = 10'd0;
    case (c)
        4'b0000: s[0] = 1'b1;
        4'b0001: s[1] = 1'b1;
        4'b0010: s[2] = 1'b1;
        4'b0011: s[3] = 1'b1;
        4'b0100: s[4] = 1'b1;
        4'b0101: s[5] = 1'b1;
        4'b0110: s[6] = 1'b1;
        4'b0111: s[7] = 1'b1;
        4'b1000: s[8] = 1'b1;
        4'b1001: s[9] = 1'b1;
        default: s    = 10'd0;
    endcase
end

endmodule
module decoder (c, s);



input [3:0] c;
output reg [0:9] s;

always @ (c) begin
    s = 10'd0;
    case (c)
        4'b0000: s[0] = 1'b1;
        4'b0001: s[1] = 1'b1;
        4'b0010: s[2] = 1'b1;
        4'b0011: s[3] = 1'b1;
        4'b0100: s[4] = 1'b1;
        4'b0101: s[5] = 1'b1;
        4'b0110: s[6] = 1'b1;
        4'b0111: s[7] = 1'b1;
        4'b1000: s[8] = 1'b1;
        4'b1001: s[9] = 1'b1;
        default: s    = 10'd0;
    endcase
end

endmodule