data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_cdc.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_cdc.sv:43: Unsupported: Member call on object 'VARREF 'src_req'' which is a 'REFDTYPE 'req_t''\n                                                                                                       : ... In instance reg_cdc\n        src_req.valid = 0;\n                ^~~~~\n%Error: Internal Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_cdc.sv:43: ../V3Width.cpp:2725: How can LHS be untyped?\n                                                                                                                       : ... In instance reg_cdc\n        src_req.valid = 0;\n                      ^\n                        ... See the manual and https://verilator.org for more assistance.\n"
module reg_cdc #(
    parameter type req_t = logic,
    parameter type rsp_t = logic
) (
    input  logic src_clk_i,
    input  logic src_rst_ni,
    input  req_t src_req_i,
    output rsp_t src_rsp_o,

    input  logic dst_clk_i,
    input  logic dst_rst_ni,
    output req_t dst_req_o,
    input  rsp_t dst_rsp_i
);

    typedef enum logic { Idle, Busy } state_e;
    state_e src_state_d, src_state_q, dst_state_d, dst_state_q;
    rsp_t dst_rsp_d, dst_rsp_q;
    logic src_req_valid, src_req_ready, src_rsp_valid, src_rsp_ready;
    logic dst_req_valid, dst_req_ready, dst_rsp_valid, dst_rsp_ready;

    logic src_ready_o;
    logic dst_valid_o;

    req_t src_req, dst_req;
    rsp_t src_rsp, dst_rsp;

    always_comb begin
        src_req = src_req_i;
        src_req.valid = 0;
        dst_req_o = dst_req;
        dst_req_o.valid = dst_valid_o;

        src_rsp_o = src_rsp;
        src_rsp_o.ready = src_ready_o;
        dst_rsp = dst_rsp_i;
        dst_rsp.ready = 0;
    end







    cdc_2phase #(.T(req_t)) i_cdc_req (
        .src_rst_ni  ( src_rst_ni    ),
        .src_clk_i   ( src_clk_i     ),
        .src_data_i  ( src_req       ),
        .src_valid_i ( src_req_valid ),
        .src_ready_o ( src_req_ready ),

        .dst_rst_ni  ( dst_rst_ni    ),
        .dst_clk_i   ( dst_clk_i     ),
        .dst_data_o  ( dst_req       ),
        .dst_valid_o ( dst_req_valid ),
        .dst_ready_i ( dst_req_ready )
    );


    cdc_2phase #(.T(rsp_t)) i_cdc_rsp (
        .src_rst_ni  ( dst_rst_ni    ),
        .src_clk_i   ( dst_clk_i     ),
        .src_data_i  ( dst_rsp_q     ),
        .src_valid_i ( dst_rsp_valid ),
        .src_ready_o ( dst_rsp_ready ),

        .dst_rst_ni  ( src_rst_ni    ),
        .dst_clk_i   ( src_clk_i     ),
        .dst_data_o  ( src_rsp       ),
        .dst_valid_o ( src_rsp_valid ),
        .dst_ready_i ( src_rsp_ready )
    );












    always_comb begin
        src_state_d = src_state_q;
        src_req_valid = 0;
        src_rsp_ready = 0;
        src_ready_o = 0;
        case (src_state_q)
            Idle: begin
                if (src_req_i.valid) begin
                    src_req_valid = 1;
                    if (src_req_ready) src_state_d = Busy;
                end
            end
            Busy: begin
                src_rsp_ready = 1;
                if (src_rsp_valid) begin
                    src_ready_o = 1;
                    src_state_d = Idle;
                end
            end
            default:;
        endcase
    end

    always_ff @(posedge src_clk_i, negedge src_rst_ni) begin
        if (!src_rst_ni)
            src_state_q <= Idle;
        else
            src_state_q <= src_state_d;
    end












    always_comb begin
        dst_state_d = dst_state_q;
        dst_req_ready = 0;
        dst_rsp_valid = 0;
        dst_valid_o = 0;
        dst_rsp_d = dst_rsp_q;
        case (dst_state_q)
            Idle: begin
                if (dst_req_valid) begin
                    dst_valid_o = 1;
                    if (dst_rsp_i.ready) begin
                        dst_req_ready = 1;
                        dst_rsp_d = dst_rsp;
                        dst_state_d = Busy;
                    end
                end
            end
            Busy: begin
                dst_rsp_valid = 1;
                if (dst_rsp_ready) begin
                    dst_state_d = Idle;
                end
            end
            default:;
        endcase
    end

    always_ff @(posedge dst_clk_i, negedge dst_rst_ni) begin
        if (!dst_rst_ni) begin
            dst_state_q <= Idle;
            dst_rsp_q <= '0;
        end else begin
            dst_state_q <= dst_state_d;
            dst_rsp_q <= dst_rsp_d;
        end
    end

endmodule
module reg_cdc #(
    parameter type req_t = logic,
    parameter type rsp_t = logic
) (
    input  logic src_clk_i,
    input  logic src_rst_ni,
    input  req_t src_req_i,
    output rsp_t src_rsp_o,

    input  logic dst_clk_i,
    input  logic dst_rst_ni,
    output req_t dst_req_o,
    input  rsp_t dst_rsp_i
);


    typedef enum logic { Idle, Busy } state_e;
    state_e src_state_d, src_state_q, dst_state_d, dst_state_q;
    rsp_t dst_rsp_d, dst_rsp_q;
    logic src_req_valid, src_req_ready, src_rsp_valid, src_rsp_ready;
    logic dst_req_valid, dst_req_ready, dst_rsp_valid, dst_rsp_ready;

    logic src_ready_o;
    logic dst_valid_o;

    req_t src_req, dst_req;
    rsp_t src_rsp, dst_rsp;

    always_comb begin
        src_req = src_req_i;
        src_req.valid = 0;
        dst_req_o = dst_req;
        dst_req_o.valid = dst_valid_o;

        src_rsp_o = src_rsp;
        src_rsp_o.ready = src_ready_o;
        dst_rsp = dst_rsp_i;
        dst_rsp.ready = 0;
    end







    cdc_2phase #(.T(req_t)) i_cdc_req (
        .src_rst_ni  ( src_rst_ni    ),
        .src_clk_i   ( src_clk_i     ),
        .src_data_i  ( src_req       ),
        .src_valid_i ( src_req_valid ),
        .src_ready_o ( src_req_ready ),

        .dst_rst_ni  ( dst_rst_ni    ),
        .dst_clk_i   ( dst_clk_i     ),
        .dst_data_o  ( dst_req       ),
        .dst_valid_o ( dst_req_valid ),
        .dst_ready_i ( dst_req_ready )
    );


    cdc_2phase #(.T(rsp_t)) i_cdc_rsp (
        .src_rst_ni  ( dst_rst_ni    ),
        .src_clk_i   ( dst_clk_i     ),
        .src_data_i  ( dst_rsp_q     ),
        .src_valid_i ( dst_rsp_valid ),
        .src_ready_o ( dst_rsp_ready ),

        .dst_rst_ni  ( src_rst_ni    ),
        .dst_clk_i   ( src_clk_i     ),
        .dst_data_o  ( src_rsp       ),
        .dst_valid_o ( src_rsp_valid ),
        .dst_ready_i ( src_rsp_ready )
    );












    always_comb begin
        src_state_d = src_state_q;
        src_req_valid = 0;
        src_rsp_ready = 0;
        src_ready_o = 0;
        case (src_state_q)
            Idle: begin
                if (src_req_i.valid) begin
                    src_req_valid = 1;
                    if (src_req_ready) src_state_d = Busy;
                end
            end
            Busy: begin
                src_rsp_ready = 1;
                if (src_rsp_valid) begin
                    src_ready_o = 1;
                    src_state_d = Idle;
                end
            end
            default:;
        endcase
    end

    always_ff @(posedge src_clk_i, negedge src_rst_ni) begin
        if (!src_rst_ni)
            src_state_q <= Idle;
        else
            src_state_q <= src_state_d;
    end












    always_comb begin
        dst_state_d = dst_state_q;
        dst_req_ready = 0;
        dst_rsp_valid = 0;
        dst_valid_o = 0;
        dst_rsp_d = dst_rsp_q;
        case (dst_state_q)
            Idle: begin
                if (dst_req_valid) begin
                    dst_valid_o = 1;
                    if (dst_rsp_i.ready) begin
                        dst_req_ready = 1;
                        dst_rsp_d = dst_rsp;
                        dst_state_d = Busy;
                    end
                end
            end
            Busy: begin
                dst_rsp_valid = 1;
                if (dst_rsp_ready) begin
                    dst_state_d = Idle;
                end
            end
            default:;
        endcase
    end

    always_ff @(posedge dst_clk_i, negedge dst_rst_ni) begin
        if (!dst_rst_ni) begin
            dst_state_q <= Idle;
            dst_rsp_q <= '0;
        end else begin
            dst_state_q <= dst_state_d;
            dst_rsp_q <= dst_rsp_d;
        end
    end

endmodule