data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v
1: b'%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:10: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7e\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\nassign mins_segs =   (min == 4\'b0000)? 7\'b111_1110:\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:11: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h30\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0001) ? 7\'b011_0000:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:12: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0010) ? 7\'b110_1101:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:13: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h79\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0011) ? 7\'b111_1001:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:14: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h33\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0100) ? 7\'b011_0011:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:15: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5b\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0101) ? 7\'b101_1011:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:16: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0110) ? 7\'b101_1111:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:17: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h70\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b0111) ? 7\'b111_0000:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:18: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b1000) ? 7\'b111_1111:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:19: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h73\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                    (min == 4\'b1001) ? 7\'b111_0011:\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:10: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                         : ... In instance decoder_7\nassign mins_segs =   (min == 4\'b0000)? 7\'b111_1110:\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:23: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7e\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\nassign sec_tens_segs =  (sec_tens == 4\'b0000) ? 7\'b111_1110:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:24: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h30\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0001) ? 7\'b011_0000:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:25: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0010) ? 7\'b110_1101:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:26: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h79\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0011) ? 7\'b111_1001:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:27: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h33\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0100) ? 7\'b011_0011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:28: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5b\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0101) ? 7\'b101_1011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:29: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0110) ? 7\'b101_1111:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:30: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h70\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b0111) ? 7\'b111_0000:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:31: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b1000) ? 7\'b111_1111:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:32: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h73\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_tens == 4\'b1001) ? 7\'b111_0011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:23: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                         : ... In instance decoder_7\nassign sec_tens_segs =  (sec_tens == 4\'b0000) ? 7\'b111_1110:\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:35: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7e\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\nassign sec_ones_segs =  (sec_ones == 4\'b0000) ? 7\'b111_1110:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:36: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h30\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0001) ? 7\'b011_0000:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:37: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0010) ? 7\'b110_1101:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:38: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h79\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0011) ? 7\'b111_1001:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:39: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h33\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0100) ? 7\'b011_0011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:40: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5b\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0101) ? 7\'b101_1011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:41: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0110) ? 7\'b101_1111:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:42: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h70\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b0111) ? 7\'b111_0000:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:43: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b1000) ? 7\'b111_1111:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:44: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'7\'h73\' generates 7 bits.\n                                                                                         : ... In instance decoder_7\n                        (sec_ones == 4\'b1001) ? 7\'b111_0011:\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/491294671/7_segment_decoder/hdl/decoder_7.v:35: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                         : ... In instance decoder_7\nassign sec_ones_segs =  (sec_ones == 4\'b0000) ? 7\'b111_1110:\n                     ^\n%Error: Exiting due to 33 warning(s)\n'
module decoder_7(output wire [6:0] sec_ones_segs, sec_tens_segs, mins_segs,
                input wire  [3:0] sec_ones,sec_tens,min);


assign mins_segs =   (min == 4'b0000)? 7'b111_1110:
                    (min == 4'b0001) ? 7'b011_0000:
                    (min == 4'b0010) ? 7'b110_1101:
                    (min == 4'b0011) ? 7'b111_1001:
                    (min == 4'b0100) ? 7'b011_0011:
                    (min == 4'b0101) ? 7'b101_1011:
                    (min == 4'b0110) ? 7'b101_1111:
                    (min == 4'b0111) ? 7'b111_0000:
                    (min == 4'b1000) ? 7'b111_1111:
                    (min == 4'b1001) ? 7'b111_0011:
                    8'bXXXX_XXXX;


assign sec_tens_segs =  (sec_tens == 4'b0000) ? 7'b111_1110:
                        (sec_tens == 4'b0001) ? 7'b011_0000:
                        (sec_tens == 4'b0010) ? 7'b110_1101:
                        (sec_tens == 4'b0011) ? 7'b111_1001:
                        (sec_tens == 4'b0100) ? 7'b011_0011:
                        (sec_tens == 4'b0101) ? 7'b101_1011:
                        (sec_tens == 4'b0110) ? 7'b101_1111:
                        (sec_tens == 4'b0111) ? 7'b111_0000:
                        (sec_tens == 4'b1000) ? 7'b111_1111:
                        (sec_tens == 4'b1001) ? 7'b111_0011:
                        8'bXXXX_XXXX;

assign sec_ones_segs =  (sec_ones == 4'b0000) ? 7'b111_1110:
                        (sec_ones == 4'b0001) ? 7'b011_0000:
                        (sec_ones == 4'b0010) ? 7'b110_1101:
                        (sec_ones == 4'b0011) ? 7'b111_1001:
                        (sec_ones == 4'b0100) ? 7'b011_0011:
                        (sec_ones == 4'b0101) ? 7'b101_1011:
                        (sec_ones == 4'b0110) ? 7'b101_1111:
                        (sec_ones == 4'b0111) ? 7'b111_0000:
                        (sec_ones == 4'b1000) ? 7'b111_1111:
                        (sec_ones == 4'b1001) ? 7'b111_0011:
                        8'bXXXX_XXXX;


endmodule
module decoder_7(output wire [6:0] sec_ones_segs, sec_tens_segs, mins_segs,
                input wire  [3:0] sec_ones,sec_tens,min);



assign mins_segs =   (min == 4'b0000)? 7'b111_1110:
                    (min == 4'b0001) ? 7'b011_0000:
                    (min == 4'b0010) ? 7'b110_1101:
                    (min == 4'b0011) ? 7'b111_1001:
                    (min == 4'b0100) ? 7'b011_0011:
                    (min == 4'b0101) ? 7'b101_1011:
                    (min == 4'b0110) ? 7'b101_1111:
                    (min == 4'b0111) ? 7'b111_0000:
                    (min == 4'b1000) ? 7'b111_1111:
                    (min == 4'b1001) ? 7'b111_0011:
                    8'bXXXX_XXXX;


assign sec_tens_segs =  (sec_tens == 4'b0000) ? 7'b111_1110:
                        (sec_tens == 4'b0001) ? 7'b011_0000:
                        (sec_tens == 4'b0010) ? 7'b110_1101:
                        (sec_tens == 4'b0011) ? 7'b111_1001:
                        (sec_tens == 4'b0100) ? 7'b011_0011:
                        (sec_tens == 4'b0101) ? 7'b101_1011:
                        (sec_tens == 4'b0110) ? 7'b101_1111:
                        (sec_tens == 4'b0111) ? 7'b111_0000:
                        (sec_tens == 4'b1000) ? 7'b111_1111:
                        (sec_tens == 4'b1001) ? 7'b111_0011:
                        8'bXXXX_XXXX;

assign sec_ones_segs =  (sec_ones == 4'b0000) ? 7'b111_1110:
                        (sec_ones == 4'b0001) ? 7'b011_0000:
                        (sec_ones == 4'b0010) ? 7'b110_1101:
                        (sec_ones == 4'b0011) ? 7'b111_1001:
                        (sec_ones == 4'b0100) ? 7'b011_0011:
                        (sec_ones == 4'b0101) ? 7'b101_1011:
                        (sec_ones == 4'b0110) ? 7'b101_1111:
                        (sec_ones == 4'b0111) ? 7'b111_0000:
                        (sec_ones == 4'b1000) ? 7'b111_1111:
                        (sec_ones == 4'b1001) ? 7'b111_0011:
                        8'bXXXX_XXXX;


endmodule