data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/xil_bram_sdp_2clk_wrap.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/xil_bram_sdp_2clk_wrap.v:56: Cannot find include file: xil_bram_sel_nprm.vh\n`include  "xil_bram_sel_nprm.vh" \n          ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_bram_sel_nprm.vh\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_bram_sel_nprm.vh.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_bram_sel_nprm.vh.sv\n             xil_bram_sel_nprm.vh\n             xil_bram_sel_nprm.vh.v\n             xil_bram_sel_nprm.vh.sv\n             obj_dir/xil_bram_sel_nprm.vh\n             obj_dir/xil_bram_sel_nprm.vh.v\n             obj_dir/xil_bram_sel_nprm.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module xil_bram_sdp_2clk_wrap
    (
     wclk,
     wen ,
     wad ,
     wda ,
     rclk,
     rrst,
     ren ,
     rad ,
     rda 
     
     );



parameter ADR = 10;
parameter DAT = 18;
parameter DEP = 1024;
parameter TYP = "M10K";
parameter MAX = 1024;
parameter DEL = 1  ;
parameter DIS_SMALL_RAM2MLAB = 1'b0;
parameter THDEP = 512;
parameter INIT_FILE = "";



input               wclk;
input [ADR-1:0]     wad ;
input [ADR-1:0]     rad ;
input [DAT-1:0]     wda ;
input               rclk;
input               rrst;
input               wen ;
input               ren ;
output [DAT-1:0]    rda ;



`include  "xil_bram_sel_nprm.vh"





wire [IDAT-1:0]     wda_int,rda_int;
wire [RDAT-1:0]     wda_rem,rda_rem;

generate
if(REM1==0)
    begin : no_rem
assign              wda_int = wda[DAT-1:0];
assign              rda[DAT-1:0] = rda_int;
    end
else
    begin : has_rem
    if(INT1 > 0)
        begin : has_int
assign              {wda_rem,wda_int}  = wda[DAT-1:0];
assign              rda[DAT-1:0]       = {rda_rem,rda_int};
        end
    else
        begin : no_int
assign              wda_rem     = wda[DAT-1:0];
assign              rda[DAT-1:0]= rda_rem;
        end
    end
endgenerate

generate
if((INT1 > 0) && (SELTYP==1))
    begin : int_sel_bram
    xil_bram_sdp_2clk_depth
        #(.ADR(ADR),
          .DAT(DIV),
          .DEP(IDEP),
          .DEL(DEL),
          .MAX(IMAXDEP)
          )                 xil_bram_sdp_int[INT1-1:0]
        (
         .wclk(wclk),
         .wen (wen),
         .wad ({INT1{wad[ADR-1:0]}}),
         .wda (wda_int),
         .rclk(rclk),
         .rrst(rrst),
         .ren (ren),
         .rad ({INT1{rad[ADR-1:0]}}),
         .rda (rda_int)
         
         );
    end
else if((INT1 > 0) && (SELTYP==0))
    begin : int_sel_dist
    xil_dist_sdp_2clk
        #(.ADR(ADR),
          .DAT(DIV),
          .DEP(IDEP),
          .DEL(DEL)
          )                 xil_dist_sdp_int[INT1-1:0]
        (
         .wclk(wclk),
         .wen (wen),
         .wad ({INT1{wad[ADR-1:0]}}),
         .wda (wda_int),
         .rclk(rclk),
         .rrst(rrst),
         .ren (ren),
         .rad ({INT1{rad[ADR-1:0]}}),
         .rda (rda_int)
         
         );
    end
endgenerate


generate
if((REM1 > 0) && (SELTYP==1))
    begin : rem_sel_bram
    xil_bram_sdp_2clk_depth
        #(.ADR(ADR),
          .DAT(REM1),
          .DEP(IDEP ),
          .DEL(DEL ),
          .MAX(IMAXDEP)
          )                 xil_bram_sdp_rem
         (
          .wclk(wclk),
          .wen (wen),
          .wad (wad[ADR-1:0]),
          .wda (wda_rem),
          .rclk(rclk),
          .rrst(rrst),
          .ren (ren),
          .rad (rad[ADR-1:0]),
          .rda (rda_rem)
          
          );
    
    end
else if((REM1 > 0) && (SELTYP==0))
    begin : rem_sel_dist
    xil_dist_sdp_2clk
        #(.ADR(ADR),
          .DAT(REM1),
          .DEP(IDEP ),
          .DEL(DEL )
          )                 xil_dist_sdp_rem
         (
          .wclk(wclk),
          .wen (wen),
          .wad (wad[ADR-1:0]),
          .wda (wda_rem),
          .rclk(rclk),
          .rrst(rrst),
          .ren (ren),
          .rad (rad[ADR-1:0]),
          .rda (rda_rem)
          
          );
    
    end
endgenerate



endmodule
module xil_bram_sdp_2clk_wrap
    (
     wclk,
     wen ,
     wad ,
     wda ,
     rclk,
     rrst,
     ren ,
     rad ,
     rda 
     
     );




parameter ADR = 10;
parameter DAT = 18;
parameter DEP = 1024;
parameter TYP = "M10K";
parameter MAX = 1024;
parameter DEL = 1  ;
parameter DIS_SMALL_RAM2MLAB = 1'b0;
parameter THDEP = 512;
parameter INIT_FILE = "";



input               wclk;
input [ADR-1:0]     wad ;
input [ADR-1:0]     rad ;
input [DAT-1:0]     wda ;
input               rclk;
input               rrst;
input               wen ;
input               ren ;
output [DAT-1:0]    rda ;



`include  "xil_bram_sel_nprm.vh"





wire [IDAT-1:0]     wda_int,rda_int;
wire [RDAT-1:0]     wda_rem,rda_rem;

generate
if(REM1==0)
    begin : no_rem
assign              wda_int = wda[DAT-1:0];
assign              rda[DAT-1:0] = rda_int;
    end
else
    begin : has_rem
    if(INT1 > 0)
        begin : has_int
assign              {wda_rem,wda_int}  = wda[DAT-1:0];
assign              rda[DAT-1:0]       = {rda_rem,rda_int};
        end
    else
        begin : no_int
assign              wda_rem     = wda[DAT-1:0];
assign              rda[DAT-1:0]= rda_rem;
        end
    end
endgenerate

generate
if((INT1 > 0) && (SELTYP==1))
    begin : int_sel_bram
    xil_bram_sdp_2clk_depth
        #(.ADR(ADR),
          .DAT(DIV),
          .DEP(IDEP),
          .DEL(DEL),
          .MAX(IMAXDEP)
          )                 xil_bram_sdp_int[INT1-1:0]
        (
         .wclk(wclk),
         .wen (wen),
         .wad ({INT1{wad[ADR-1:0]}}),
         .wda (wda_int),
         .rclk(rclk),
         .rrst(rrst),
         .ren (ren),
         .rad ({INT1{rad[ADR-1:0]}}),
         .rda (rda_int)
         
         );
    end
else if((INT1 > 0) && (SELTYP==0))
    begin : int_sel_dist
    xil_dist_sdp_2clk
        #(.ADR(ADR),
          .DAT(DIV),
          .DEP(IDEP),
          .DEL(DEL)
          )                 xil_dist_sdp_int[INT1-1:0]
        (
         .wclk(wclk),
         .wen (wen),
         .wad ({INT1{wad[ADR-1:0]}}),
         .wda (wda_int),
         .rclk(rclk),
         .rrst(rrst),
         .ren (ren),
         .rad ({INT1{rad[ADR-1:0]}}),
         .rda (rda_int)
         
         );
    end
endgenerate


generate
if((REM1 > 0) && (SELTYP==1))
    begin : rem_sel_bram
    xil_bram_sdp_2clk_depth
        #(.ADR(ADR),
          .DAT(REM1),
          .DEP(IDEP ),
          .DEL(DEL ),
          .MAX(IMAXDEP)
          )                 xil_bram_sdp_rem
         (
          .wclk(wclk),
          .wen (wen),
          .wad (wad[ADR-1:0]),
          .wda (wda_rem),
          .rclk(rclk),
          .rrst(rrst),
          .ren (ren),
          .rad (rad[ADR-1:0]),
          .rda (rda_rem)
          
          );
    
    end
else if((REM1 > 0) && (SELTYP==0))
    begin : rem_sel_dist
    xil_dist_sdp_2clk
        #(.ADR(ADR),
          .DAT(REM1),
          .DEP(IDEP ),
          .DEL(DEL )
          )                 xil_dist_sdp_rem
         (
          .wclk(wclk),
          .wen (wen),
          .wad (wad[ADR-1:0]),
          .wda (wda_rem),
          .rclk(rclk),
          .rrst(rrst),
          .ren (ren),
          .rad (rad[ADR-1:0]),
          .rda (rda_rem)
          
          );
    
    end
endgenerate



endmodule