data/full_repos/permissive/509809169/Circuits/Sequential Logic/Latches and Flip Flops/detect an edge.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: Flops,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Flops/detect\n%Error: Cannot find file containing module: an\n%Error: Cannot find file containing module: edge.v\n%Error: Exiting due to 8 error(s)\n'
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] temp1, temp2;
	 always @(posedge clk) begin
		temp1 <= in;
		temp2 <= temp1;
	 end
	 assign pedge = ~temp2 & temp1;

endmodule
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);

    reg [7:0] temp1, temp2;
	 always @(posedge clk) begin
		temp1 <= in;
		temp2 <= temp1;
	 end
	 assign pedge = ~temp2 & temp1;

endmodule