data/full_repos/permissive/447976230/fpga/usrp2/control_lib/ram_2port_mixed_width.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/ram_2port_mixed_width.v:44: Cannot find file containing module: 'RAMB16BWE_S36_S18'\n   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/RAMB16BWE_S36_S18\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/RAMB16BWE_S36_S18.v\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/RAMB16BWE_S36_S18.sv\n             RAMB16BWE_S36_S18\n             RAMB16BWE_S36_S18.v\n             RAMB16BWE_S36_S18.sv\n             obj_dir/RAMB16BWE_S36_S18\n             obj_dir/RAMB16BWE_S36_S18.v\n             obj_dir/RAMB16BWE_S36_S18.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/ram_2port_mixed_width.v:72: Cannot find file containing module: 'RAMB16BWE_S36_S18'\n   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),\n   ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ram_2port_mixed_width
  (input clk16,
   input en16,
   input we16,
   input [10:0] addr16,
   input [15:0] di16,
   output [15:0] do16,
   input clk32,
   input en32,
   input we32,
   input [9:0] addr32,
   input [31:0] di32,
   output [31:0] do32);

   wire 	 en32a = en32 & ~addr32[9];
   wire 	 en32b = en32 & addr32[9];
   wire 	 en16a = en16 & ~addr16[10];
   wire 	 en16b = en16 & addr16[10];

   wire [31:0] 	 do32a, do32b;
   wire [15:0] 	 do16a, do16b;
   
   assign do32 = addr32[9] ? do32b : do32a;
   assign do16 = addr16[10] ? do16b : do16a;
   
   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
		       .INIT_B(18'h00000),
		       .SIM_COLLISION_CHECK("ALL"),
		       .SRVAL_A(36'h000000000),
		       .SRVAL_B(18'h00000),
		       .WRITE_MODE_A("WRITE_FIRST"),
		       .WRITE_MODE_B("WRITE_FIRST")
		       ) 
   RAMB16BWE_S36_S18_0 (.DOA(do32a),
			.DOB(do16a),
			.DOPA(),
			.DOPB(),
			.ADDRA(addr32[8:0]),
			.ADDRB(addr16[9:0]),
			.CLKA(clk32),
			.CLKB(clk16),
			.DIA(di32),
			.DIB(di16),
			.DIPA(0),
			.DIPB(0),
			.ENA(en32a),
			.ENB(en16a),
			.SSRA(0),
			.SSRB(0),
			.WEA({4{we32}}),
			.WEB({2{we16}})
			);

   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
		       .INIT_B(18'h00000),
		       .SIM_COLLISION_CHECK("ALL"),
		       .SRVAL_A(36'h000000000),
		       .SRVAL_B(18'h00000),
		       .WRITE_MODE_A("WRITE_FIRST"),
		       .WRITE_MODE_B("WRITE_FIRST")
		       ) 
   RAMB16BWE_S36_S18_1 (.DOA(do32b),
			.DOB(do16b),
			.DOPA(),
			.DOPB(),
			.ADDRA(addr32[8:0]),
			.ADDRB(addr16[9:0]),
			.CLKA(clk32),
			.CLKB(clk16),
			.DIA(di32),
			.DIB(di16),
			.DIPA(0),
			.DIPB(0),
			.ENA(en32b),
			.ENB(en16b),
			.SSRA(0),
			.SSRB(0),
			.WEA({4{we32}}),
			.WEB({2{we16}})
			);

endmodule
module ram_2port_mixed_width
  (input clk16,
   input en16,
   input we16,
   input [10:0] addr16,
   input [15:0] di16,
   output [15:0] do16,
   input clk32,
   input en32,
   input we32,
   input [9:0] addr32,
   input [31:0] di32,
   output [31:0] do32);


   wire 	 en32a = en32 & ~addr32[9];
   wire 	 en32b = en32 & addr32[9];
   wire 	 en16a = en16 & ~addr16[10];
   wire 	 en16b = en16 & addr16[10];

   wire [31:0] 	 do32a, do32b;
   wire [15:0] 	 do16a, do16b;
   
   assign do32 = addr32[9] ? do32b : do32a;
   assign do16 = addr16[10] ? do16b : do16a;
   
   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
		       .INIT_B(18'h00000),
		       .SIM_COLLISION_CHECK("ALL"),
		       .SRVAL_A(36'h000000000),
		       .SRVAL_B(18'h00000),
		       .WRITE_MODE_A("WRITE_FIRST"),
		       .WRITE_MODE_B("WRITE_FIRST")
		       ) 
   RAMB16BWE_S36_S18_0 (.DOA(do32a),
			.DOB(do16a),
			.DOPA(),
			.DOPB(),
			.ADDRA(addr32[8:0]),
			.ADDRB(addr16[9:0]),
			.CLKA(clk32),
			.CLKB(clk16),
			.DIA(di32),
			.DIB(di16),
			.DIPA(0),
			.DIPB(0),
			.ENA(en32a),
			.ENB(en16a),
			.SSRA(0),
			.SSRB(0),
			.WEA({4{we32}}),
			.WEB({2{we16}})
			);

   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
		       .INIT_B(18'h00000),
		       .SIM_COLLISION_CHECK("ALL"),
		       .SRVAL_A(36'h000000000),
		       .SRVAL_B(18'h00000),
		       .WRITE_MODE_A("WRITE_FIRST"),
		       .WRITE_MODE_B("WRITE_FIRST")
		       ) 
   RAMB16BWE_S36_S18_1 (.DOA(do32b),
			.DOB(do16b),
			.DOPA(),
			.DOPB(),
			.ADDRA(addr32[8:0]),
			.ADDRB(addr16[9:0]),
			.CLKA(clk32),
			.CLKB(clk16),
			.DIA(di32),
			.DIB(di16),
			.DIPA(0),
			.DIPB(0),
			.ENA(en32b),
			.ENB(en16b),
			.SSRA(0),
			.SSRB(0),
			.WEA({4{we32}}),
			.WEB({2{we16}})
			);

endmodule