data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_pcs_tx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_pcs_tx.v:130: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do            (txdo)\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_pcs_tx.v:130: syntax error, unexpected '(', expecting ')'\n     .do            (txdo)\n                     ^~~~\n%Error: Exiting due to 2 error(s)\n"
module ippcsge_pcs_tx
    (
     sclk125,
     rst_,

     txen,
     txerr,


     receiving,
     xmit,
     tx_cfdata,

     col,
     crs,
     txdi,
     txdo,


     sysclk,
     sysrst_,
     pact,
     pen,
     pws,
     prs,
     pdi,
     pdo,
     prdy
     );




input               sclk125;
input               rst_;

input               txen;
input               txerr;

input               receiving;
input [1:0]         xmit;
input [15:0]        tx_cfdata;

output              col;
output              crs;
input [7:0]         txdi;
output [9:0]        txdo;

input               sysclk;
input               sysrst_;

input               pact;
input               pen;
input               pws;
input               prs;
input [15:0]        pdi;
output [15:0]       pdo;
output              prdy;

            


wire                col;
wire [9:0]          txdo;
wire                crs;

wire [15:0]         pdo;
wire                prdy;







wire                pdo_mctl;
wire                fdisp;

pconfigx #(1) main_control 
    (
     .clk           (sysclk),
     .rst_          (sysrst_),
     .upen          (pen),
     .upws          (pws),
     .updi          (pdi[0]),
     .out           (fdisp),
     .updo          (pdo_mctl)
     );


assign              pdo = pen? {15'h0,pdo_mctl}: 16'b0;
fflopx #(1)         pp_prdy(sysclk, sysrst_,(pws|prs)&pen,prdy);

wire                transmitting;
ippcsge_pcstx pcstx_inst
    (
     .clk           (sclk125),
     .rst_          (rst_),
     

     .fdisp         (fdisp),
     .disp          (1'b1),   
     

     .receiving     (receiving),
     .transmitting  (transmitting),


     .xmit          (xmit),
     .cfdata        (tx_cfdata),


     .txen          (txen),
     .txerr         (txerr),
     .col           (col),
     .di            (txdi),
     .do            (txdo)

     );

ippcsge_carr_sense carr_sense_inst
    (
     .clk           (sclk125),
     .rst_          (rst_),
     .rep_mode      (),
     .transmitting  (transmitting),
     .receiving     (receiving),
     .crs           (crs)
     );

endmodule
module ippcsge_pcs_tx
    (
     sclk125,
     rst_,

     txen,
     txerr,


     receiving,
     xmit,
     tx_cfdata,

     col,
     crs,
     txdi,
     txdo,


     sysclk,
     sysrst_,
     pact,
     pen,
     pws,
     prs,
     pdi,
     pdo,
     prdy
     );





input               sclk125;
input               rst_;

input               txen;
input               txerr;

input               receiving;
input [1:0]         xmit;
input [15:0]        tx_cfdata;

output              col;
output              crs;
input [7:0]         txdi;
output [9:0]        txdo;

input               sysclk;
input               sysrst_;

input               pact;
input               pen;
input               pws;
input               prs;
input [15:0]        pdi;
output [15:0]       pdo;
output              prdy;

            


wire                col;
wire [9:0]          txdo;
wire                crs;

wire [15:0]         pdo;
wire                prdy;







wire                pdo_mctl;
wire                fdisp;

pconfigx #(1) main_control 
    (
     .clk           (sysclk),
     .rst_          (sysrst_),
     .upen          (pen),
     .upws          (pws),
     .updi          (pdi[0]),
     .out           (fdisp),
     .updo          (pdo_mctl)
     );


assign              pdo = pen? {15'h0,pdo_mctl}: 16'b0;
fflopx #(1)         pp_prdy(sysclk, sysrst_,(pws|prs)&pen,prdy);

wire                transmitting;
ippcsge_pcstx pcstx_inst
    (
     .clk           (sclk125),
     .rst_          (rst_),
     

     .fdisp         (fdisp),
     .disp          (1'b1),   
     

     .receiving     (receiving),
     .transmitting  (transmitting),


     .xmit          (xmit),
     .cfdata        (tx_cfdata),


     .txen          (txen),
     .txerr         (txerr),
     .col           (col),
     .di            (txdi),
     .do            (txdo)

     );

ippcsge_carr_sense carr_sense_inst
    (
     .clk           (sclk125),
     .rst_          (rst_),
     .rep_mode      (),
     .transmitting  (transmitting),
     .receiving     (receiving),
     .crs           (crs)
     );

endmodule