data/full_repos/permissive/500326609/a6/control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500326609/a6/control.v:35: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n                                                                    : ... In instance control\nassign regsrc = (opcode == 7\'b0110111) ? 2\'b00 :                         \n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500326609/a6/control.v:36: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h2\' generates 2 bits.\n                                                                    : ... In instance control\n                (opcode == 7\'b1101111 || opcode == 7\'b1100111) ? 2\'b10   \n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/500326609/a6/control.v:36: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'2\'h1\' generates 2 bits.\n                                                                    : ... In instance control\n                (opcode == 7\'b1101111 || opcode == 7\'b1100111) ? 2\'b10   \n                                                               ^\n%Error: Exiting due to 3 warning(s)\n'
module control (
    input [31:0] idata,
    output [2:0] branch,
    output [2:0] regsrc,
    output  mem2reg,
    output  [5:0] ALUop,
    output alusrc,
    output regwrite,
    output [3:0] memwrite
);


wire [6:0] opcode;
wire [2:0] funct3;
assign funct3 = idata[14:12];
assign opcode = idata[6:0];


assign branch = (opcode == 7'b1100011 && (funct3 == 3'b000 || funct3 == 3'b101 || funct3 == 3'b111))? 3'b010:
					      (opcode == 7'b1100011 && (funct3 == 3'b001 || funct3 == 3'b100 || funct3 == 3'b110))? 3'b001:
    					  (opcode == 7'b1101111 )? 3'b011 :
    					  (opcode == 7'b1100111 )? 3'b100 :
                3'b000;


assign regwrite = (opcode == 7'b0000011 || opcode == 7'b0110011 || opcode == 7'b0010011 ||
                   opcode == 7'b0110111 || opcode == 7'b0010111 || opcode == 7'b1101111 ||
                   opcode == 7'b1100111 );

assign memwrite = (opcode == 7'b0100011 && funct3 == 3'b010) ? 4'b1111 :
                  (opcode == 7'b0100011 && funct3 == 3'b001) ? 4'b0011 :
                  (opcode == 7'b0100011 && funct3 == 3'b000) ? 4'b0001 : 4'b0000;


assign regsrc = (opcode == 7'b0110111) ? 2'b00 :
                (opcode == 7'b1101111 || opcode == 7'b1100111) ? 2'b10
                : 2'b01;


assign mem2reg = (opcode == 7'b0000011);



assign alusrc = (opcode == 7'b0010011 || opcode == 7'b0000011 ||
                 opcode == 7'b1100111 || opcode == 7'b0010111 );




assign ALUop = (opcode == 7'b0010111)? 6'b010000 :
                (opcode == 7'b1100011)?
                (funct3 == 3'b000 || funct3 == 3'b001 )? 6'b010001 :
                (funct3 == 3'b100 || funct3 == 3'b101 )? 6'b010101 :
                (funct3 == 3'b110 || funct3 == 3'b111 )? 6'b010111
                :{1'b0,idata[5],idata[14:12],idata[30]}
                :{1'b0,idata[5],idata[14:12],idata[30]};

endmodule
module control (
    input [31:0] idata,
    output [2:0] branch,
    output [2:0] regsrc,
    output  mem2reg,
    output  [5:0] ALUop,
    output alusrc,
    output regwrite,
    output [3:0] memwrite
);



wire [6:0] opcode;
wire [2:0] funct3;
assign funct3 = idata[14:12];
assign opcode = idata[6:0];


assign branch = (opcode == 7'b1100011 && (funct3 == 3'b000 || funct3 == 3'b101 || funct3 == 3'b111))? 3'b010:
					      (opcode == 7'b1100011 && (funct3 == 3'b001 || funct3 == 3'b100 || funct3 == 3'b110))? 3'b001:
    					  (opcode == 7'b1101111 )? 3'b011 :
    					  (opcode == 7'b1100111 )? 3'b100 :
                3'b000;


assign regwrite = (opcode == 7'b0000011 || opcode == 7'b0110011 || opcode == 7'b0010011 ||
                   opcode == 7'b0110111 || opcode == 7'b0010111 || opcode == 7'b1101111 ||
                   opcode == 7'b1100111 );

assign memwrite = (opcode == 7'b0100011 && funct3 == 3'b010) ? 4'b1111 :
                  (opcode == 7'b0100011 && funct3 == 3'b001) ? 4'b0011 :
                  (opcode == 7'b0100011 && funct3 == 3'b000) ? 4'b0001 : 4'b0000;


assign regsrc = (opcode == 7'b0110111) ? 2'b00 :
                (opcode == 7'b1101111 || opcode == 7'b1100111) ? 2'b10
                : 2'b01;


assign mem2reg = (opcode == 7'b0000011);



assign alusrc = (opcode == 7'b0010011 || opcode == 7'b0000011 ||
                 opcode == 7'b1100111 || opcode == 7'b0010111 );




assign ALUop = (opcode == 7'b0010111)? 6'b010000 :
                (opcode == 7'b1100011)?
                (funct3 == 3'b000 || funct3 == 3'b001 )? 6'b010001 :
                (funct3 == 3'b100 || funct3 == 3'b101 )? 6'b010101 :
                (funct3 == 3'b110 || funct3 == 3'b111 )? 6'b010111
                :{1'b0,idata[5],idata[14:12],idata[30]}
                :{1'b0,idata[5],idata[14:12],idata[30]};

endmodule