data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:73: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'mux_2level_tapbuf_basis_input3_mem3\'\nmodule mux_2level_tapbuf_basis_input3_mem3(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'mux_2level_tapbuf_basis_input2_mem1\'\nmodule mux_2level_tapbuf_basis_input2_mem1(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'mux_2level_basis_input4_mem4\'\nmodule mux_2level_basis_input4_mem4(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'mux_2level_basis_input3_mem3\'\nmodule mux_2level_basis_input3_mem3(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'mux_1level_tapbuf_basis_input3_mem3\'\nmodule mux_1level_tapbuf_basis_input3_mem3(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'lut4_mux_basis_input2_mem1\'\nmodule lut4_mux_basis_input2_mem1(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:310: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] in;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:332: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/TGATE\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/TGATE.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/TGATE.sv\n             TGATE\n             TGATE.v\n             TGATE.sv\n             obj_dir/TGATE\n             obj_dir/TGATE.v\n             obj_dir/TGATE.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:338: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:252: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:254: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:256: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:274: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:280: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:286: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_2_ (\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:194: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:196: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:198: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:216: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:222: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:228: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_2_ (\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:130: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:132: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] mem;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:134: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] mem_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:152: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:158: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:164: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_2_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:170: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_3_ (\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:78: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] in;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:100: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:106: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:20: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:22: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:24: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] mem_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:42: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_0_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:48: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_1_ (\n ^~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/mux_primitives.v:54: Cannot find file containing module: \'TGATE\'\n TGATE TGATE_2_ (\n ^~~~~\n%Error: Exiting due to 17 error(s), 15 warning(s)\n'
module lut4_mux_basis_input2_mem1(in,
                                  mem,
                                  mem_inv,
                                  out);

input [0:1] in;

input [0:0] mem;

input [0:0] mem_inv;

output [0:0] out;















	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem),
		.selb(mem_inv),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem_inv),
		.selb(mem),
		.out(out));

endmodule
module lut4_mux_basis_input2_mem1(in,
                                  mem,
                                  mem_inv,
                                  out);


input [0:1] in;

input [0:0] mem;

input [0:0] mem_inv;

output [0:0] out;















	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem),
		.selb(mem_inv),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem_inv),
		.selb(mem),
		.out(out));

endmodule