data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~ clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #20 $display("%d * %d = %d", a, b, p);\n   ^\n%Error: data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v:17: Cannot find file containing module: \'mulparam\'\nmulparam mul_0( .p(p), .a(a), .b(b), .clock(clock) );\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427281804/FPU/verilog/Multiplier,data/full_repos/permissive/427281804/mulparam\n             data/full_repos/permissive/427281804/FPU/verilog/Multiplier,data/full_repos/permissive/427281804/mulparam.v\n             data/full_repos/permissive/427281804/FPU/verilog/Multiplier,data/full_repos/permissive/427281804/mulparam.sv\n             mulparam\n             mulparam.v\n             mulparam.sv\n             obj_dir/mulparam\n             obj_dir/mulparam.v\n             obj_dir/mulparam.sv\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v:32: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                              : ... In instance testbench\n   a=j;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/Multiplier/test_mulparam.v:33: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 32 bits.\n                                                                                              : ... In instance testbench\n   b=k;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

parameter width = 11;

reg [width-1:0] a;
reg [width-1:0] b;
reg clock;

wire [2*width-1:0] p;

integer j, k;
integer out_file;

mulparam mul_0( .p(p), .a(a), .b(b), .clock(clock) );

initial clock = 0;
always #5 clock = ~ clock;

initial
begin

	out_file = $fopen(`out_fn, "w");

	a=0;
	b=0;
	for (j=1; j<=2**width-1; j=j+1)
		for(k=1; k<=2**width-1; k=k+1)
		begin
			a=j;
			b=k;
			#20 $display("%d * %d = %d", a, b, p);
			$fwrite(out_file, "%d * %d = %d\n", a, b, p);
		end

	$fclose(out_file);
end
endmodule
module testbench();


parameter width = 11;

reg [width-1:0] a;
reg [width-1:0] b;
reg clock;

wire [2*width-1:0] p;

integer j, k;
integer out_file;

mulparam mul_0( .p(p), .a(a), .b(b), .clock(clock) );

initial clock = 0;
always #5 clock = ~ clock;

initial
begin

	out_file = $fopen(`out_fn, "w");

	a=0;
	b=0;
	for (j=1; j<=2**width-1; j=j+1)
		for(k=1; k<=2**width-1; k=k+1)
		begin
			a=j;
			b=k;
			#20 $display("%d * %d = %d", a, b, p);
			$fwrite(out_file, "%d * %d = %d\n", a, b, p);
		end

	$fclose(out_file);
end
endmodule