data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:76: Signal definition not found, creating implicitly: \'out_step\'\n  assign out_step = step_select(mode, rpm_step, axis_step, divider_step);\n         ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:79: Operator CASE expects 32 or 2 bits on the Case expression, but Case expression\'s VARREF \'mode\' generates 1 bits.\n                                                                                                                 : ... In instance controller\n    case (mode)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:76: Operator FUNCREF \'step_select\' expects 1 bits on the Function Argument, but Function Argument\'s VARREF \'mode\' generates 2 bits.\n                                                                                                                 : ... In instance controller\n  assign out_step = step_select(mode, rpm_step, axis_step, divider_step);\n                    ^~~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module rpm_match
#(
  parameter clock_divider = 120000
)
(
  input reference_clock,
  input feedback_clock,
  input clk,
  output reg step
);
  reg[1:0] feedback_clock_delay = {1'b0,1'b0};
  reg[1:0] reference_clock_delay = {1'b0,1'b0};


  reg[31:0] fll_count = 0;
  reg[31:0] step_delay = 0;
  reg[31:0] slow_clk = 0;

  always @(posedge clk)
  begin
    feedback_clock_delay = {feedback_clock_delay[0],feedback_clock};
    reference_clock_delay = {reference_clock_delay[0],reference_clock};
    if(feedback_clock_delay[1] & ~feedback_clock_delay[0])
      fll_count = fll_count + 1;

    if(reference_clock_delay[1] & ~reference_clock_delay[0])
    begin



      if(fll_count < clock_divider)

        step_delay = step_delay + (clock_divider - fll_count) >> 4;
      else
      begin

        step_delay = step_delay - (fll_count - clock_divider) >> 4;
        fll_count = fll_count - clock_divider;
      end
    end

    slow_clk = slow_clk + 1;
    if(slow_clk >= step_delay)
    begin
      slow_clk = 0;
      step = 1;
    end
    else
      step = 0;
  end
endmodule
module rpm_match
#(
  parameter clock_divider = 120000
)
(
  input reference_clock,
  input feedback_clock,
  input clk,
  output reg step
);

  reg[1:0] feedback_clock_delay = {1'b0,1'b0};
  reg[1:0] reference_clock_delay = {1'b0,1'b0};


  reg[31:0] fll_count = 0;
  reg[31:0] step_delay = 0;
  reg[31:0] slow_clk = 0;

  always @(posedge clk)
  begin
    feedback_clock_delay = {feedback_clock_delay[0],feedback_clock};
    reference_clock_delay = {reference_clock_delay[0],reference_clock};
    if(feedback_clock_delay[1] & ~feedback_clock_delay[0])
      fll_count = fll_count + 1;

    if(reference_clock_delay[1] & ~reference_clock_delay[0])
    begin



      if(fll_count < clock_divider)

        step_delay = step_delay + (clock_divider - fll_count) >> 4;
      else
      begin

        step_delay = step_delay - (fll_count - clock_divider) >> 4;
        fll_count = fll_count - clock_divider;
      end
    end

    slow_clk = slow_clk + 1;
    if(slow_clk >= step_delay)
    begin
      slow_clk = 0;
      step = 1;
    end
    else
      step = 0;
  end
endmodule