data/full_repos/permissive/501470173/verilog/rtl/ALU.v
data/verilator_xmls/9696c10e-89d6-4a02-8a9f-fcf7e426e179.xml
module ALU(
    input [7:0] a,
    input [7:0] b,
    output [7:0] result,
    input [2:0] opalu,
	 output zero, carry
    );

reg [7:0] resu;

always@*
	case (opalu)
		0: resu <= ~a;
		1: resu <= a & b;
		2: resu <= a ^ b;
		3: resu <= a | b;
		4: resu <= a;
		5: resu <= a + b;
		6: resu <= a - b;
		default: resu <= a + 1;
	endcase
	
assign zero=(resu==0);
assign result=resu;
assign carry=(a<b);
		

endmodule
module ALU(
    input [7:0] a,
    input [7:0] b,
    output [7:0] result,
    input [2:0] opalu,
	 output zero, carry
    );


reg [7:0] resu;

always@*
	case (opalu)
		0: resu <= ~a;
		1: resu <= a & b;
		2: resu <= a ^ b;
		3: resu <= a | b;
		4: resu <= a;
		5: resu <= a + b;
		6: resu <= a - b;
		default: resu <= a + 1;
	endcase
	
assign zero=(resu==0);
assign result=resu;
assign carry=(a<b);
		

endmodule