data/full_repos/permissive/524553217/src/instr_memory.v
data/verilator_xmls/0b2ca001-d30a-40f2-ae45-070a9a5ca653.xml
module instr_memory(
    input [31:0] address,
    output reg [31:0] data
    );
    
    reg [31:0] im_addr;
    reg [7:0] memory [0:1023];
    
    initial begin
        $readmemh("instructions.txt", memory);






    end
    
    always @(*) begin
        im_addr = address - 32'h00010000;
        if (im_addr[31] == 0)
            data = {memory[im_addr], memory[im_addr+1], memory[im_addr+2], memory[im_addr+3]};
        else data = 32'b0;

    end
    
endmodule
module instr_memory(
    input [31:0] address,
    output reg [31:0] data
    );

    
    reg [31:0] im_addr;
    reg [7:0] memory [0:1023];
    
    initial begin
        $readmemh("instructions.txt", memory);






    end
    
    always @(*) begin
        im_addr = address - 32'h00010000;
        if (im_addr[31] == 0)
            data = {memory[im_addr], memory[im_addr+1], memory[im_addr+2], memory[im_addr+3]};
        else data = 32'b0;

    end
    
endmodule