data/full_repos/permissive/475937410/Ass4/InstructionRAM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/475937410/Ass4/InstructionRAM.v:43: Bit extraction of array[511:0] requires 9 bit index, not 64 bits.\n                                                                             : ... In instance InstructionRAM\n      RAM[(wild_0)] <= DATA_0[31:0];\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/475937410/Ass4/InstructionRAM.v:46: Bit extraction of array[511:0] requires 9 bit index, not 64 bits.\n                                                                             : ... In instance InstructionRAM\n      DATA <= RAM[(wild)];\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module InstructionRAM
    (
      input  CLOCK
    , input  RESET
    , input  ENABLE
    , input [31:0] FETCH_ADDRESS


    , output reg [31:0] DATA
    );

  wire signed [63:0] c$wild_app_arg;

  wire signed [63:0] c$wild_app_arg_0;

  wire [31:0] x1;

  wire signed [63:0] wild;

  wire signed [63:0] wild_0;
  wire [63:0] DATA_0;
  wire [63:0] x1_projection;

  assign c$wild_app_arg = $unsigned({{(64-32) {1'b0}},FETCH_ADDRESS});

  assign c$wild_app_arg_0 = $unsigned({{(64-32) {1'b0}},x1});

  assign DATA_0 = {64 {1'bx}};


  reg [31:0] RAM [0:512-1];

  initial begin
    $readmemb("instructions.bin",RAM);
  end

  always @( posedge CLOCK) begin : InstructionRAM_blockRamFile
    if (1'b0 & ENABLE) begin
      RAM[(wild_0)] <= DATA_0[31:0];
    end
    if (ENABLE) begin
      DATA <= RAM[(wild)];
    end
  end


  assign x1_projection = {64 {1'bx}};

  assign x1 = x1_projection[63:32];

  assign wild = $signed(c$wild_app_arg);

  assign wild_0 = $signed(c$wild_app_arg_0);


endmodule
module InstructionRAM
    (
      input  CLOCK
    , input  RESET
    , input  ENABLE
    , input [31:0] FETCH_ADDRESS


    , output reg [31:0] DATA
    );


  wire signed [63:0] c$wild_app_arg;

  wire signed [63:0] c$wild_app_arg_0;

  wire [31:0] x1;

  wire signed [63:0] wild;

  wire signed [63:0] wild_0;
  wire [63:0] DATA_0;
  wire [63:0] x1_projection;

  assign c$wild_app_arg = $unsigned({{(64-32) {1'b0}},FETCH_ADDRESS});

  assign c$wild_app_arg_0 = $unsigned({{(64-32) {1'b0}},x1});

  assign DATA_0 = {64 {1'bx}};


  reg [31:0] RAM [0:512-1];

  initial begin
    $readmemb("instructions.bin",RAM);
  end

  always @( posedge CLOCK) begin : InstructionRAM_blockRamFile
    if (1'b0 & ENABLE) begin
      RAM[(wild_0)] <= DATA_0[31:0];
    end
    if (ENABLE) begin
      DATA <= RAM[(wild)];
    end
  end


  assign x1_projection = {64 {1'bx}};

  assign x1 = x1_projection[63:32];

  assign wild = $signed(c$wild_app_arg);

  assign wild_0 = $signed(c$wild_app_arg_0);


endmodule