data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:27: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time CyclTime = 10ns;\n                             ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:28: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time ApplTime = 2ns;\n                             ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:29: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time TestTime = 8ns;\n                             ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:67: syntax error, unexpected \'@\'\n      @(posedge rst_n);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:75: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:81: syntax error, unexpected \'@\'\n      repeat ((NumInp-i)*NumReqs) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:82: syntax error, unexpected \'@\'\n      repeat (1000) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:88: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:93: syntax error, unexpected \'@\'\n      repeat ((1+i)*NumReqs) @(posedge clk);\n                             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:94: syntax error, unexpected \'@\'\n      repeat (1000) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:102: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:107: syntax error, unexpected \'@\'\n      repeat ((1+i)*NumReqs) @(posedge clk);\n                             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:108: syntax error, unexpected \'@\'\n      repeat (1000) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:115: Unsupported or unknown PLI call: $urandom_range\n        rand_wait = $urandom_range(1, 2*NumInp);\n                    ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:117: Unsupported: Ignoring delay on this delayed statement.\n          #TestTime;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:119: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:120: Unsupported: Ignoring delay on this delayed statement.\n            #TestTime;\n            ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:123: syntax error, unexpected \'@\'\n          repeat (rand_wait) @(posedge clk);\n                             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:129: Unsupported or unknown PLI call: $urandom_range\n        rand_wait = $urandom_range(0, NumInp);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:130: syntax error, unexpected \'@\'\n        repeat (rand_wait) @(posedge clk);\n                           ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:139: Unsupported or unknown PLI call: $urandom\n      new_stimuli[i] = $urandom();\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:145: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:149: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:157: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:159: Unsupported or unknown PLI call: $urandom_range\n      rand_wait = $urandom_range(2000, 20000);\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:160: syntax error, unexpected \'@\'\n      repeat (rand_wait) @(posedge clk);\n                         ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:162: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:169: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:170: Unsupported: wait statements\n    wait (&end_of_sim);\n    ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:171: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:187: syntax error, unexpected \'@\'\n      @(posedge rst_n);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:189: Unsupported: Ignoring delay on this delayed statement.\n        #TestTime;\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:204: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:227: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/rr_arb_tree_tb.sv:228: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n%Error: Exiting due to 31 error(s), 4 warning(s)\n'
module rr_arb_tree_tb #(

  parameter int unsigned NumInp    = 32'd7,

  parameter int unsigned NumReqs   = 32'd20000,

  parameter bit          AxiVldRdy = 1'b1,

  parameter bit          LockIn    = 1'b1,

  parameter bit          FairArb   = 1'b1
);

  localparam time CyclTime = 10ns;
  localparam time ApplTime = 2ns;
  localparam time TestTime = 8ns;



  localparam real error_threshold = 0.1;

  localparam int unsigned IdxWidth  = (NumInp > 32'd1) ? unsigned'($clog2(NumInp)) : 32'd1;
  localparam int unsigned DataWidth = 32'd45;
  typedef logic [IdxWidth-1:0]  idx_t;
  typedef logic [DataWidth-1:0] data_t;


  logic               clk;
  logic               rst_n;
  logic               flush;
  idx_t               rr,       idx;
  logic  [NumInp-1:0] req_inp,  gnt_inp, end_of_sim;
  data_t [NumInp-1:0] data_inp;
  logic               req_oup,  gnt_oup;
  data_t              data_oup;


  clk_rst_gen #(
    .ClkPeriod    ( CyclTime ),
    .RstClkCycles ( 5        )
  ) i_clk_rst_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );



  for (genvar i = 0; i < NumInp; i++) begin : gen_stream_gen
    initial begin : proc_stream_gen
      automatic data_t       stimuli;
      automatic int unsigned rand_wait;

      end_of_sim[i] = 1'b0;
      @(posedge rst_n);
      data_inp[i] = '0;
      req_inp[i]  = 1'b0;


      for (int unsigned j = 0; j < (i+1) * NumReqs; j++) begin
        data_inp[i] <= #ApplTime data_t'(i);
        req_inp[i]  <= #ApplTime 1'b1;
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;


      repeat ((NumInp-i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);


      for (int unsigned j = 0; j < (NumInp-i) * NumReqs; j++) begin
        data_inp[i] <= #ApplTime data_t'(i);
        req_inp[i]  <= #ApplTime 1'b1;
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;

      repeat ((1+i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);


      for (int unsigned j = 0; j < (NumInp-i) * NumReqs; j++) begin
        if ((i % 2) == 0) begin
          data_inp[i] <= #ApplTime data_t'(i);
          req_inp[i]  <= #ApplTime 1'b1;
        end
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;

      repeat ((1+i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);



      for (int unsigned j = 0; j < NumReqs; j++) begin
        data_inp[i] <= #ApplTime new_stimuli();
        req_inp[i]  <= #ApplTime 1'b1;
        rand_wait = $urandom_range(1, 2*NumInp);
        if (LockIn) begin
          #TestTime;
          while (!gnt_inp[i]) begin
            @(posedge clk);
            #TestTime;
          end
        end else begin
          repeat (rand_wait) @(posedge clk);
        end
        @(posedge clk);
        data_inp[i] <= #ApplTime '0;
        req_inp[i]  <= #ApplTime 1'b0;

        rand_wait = $urandom_range(0, NumInp);
        repeat (rand_wait) @(posedge clk);
      end

      end_of_sim[i] = 1'b1;
    end
  end

  function data_t new_stimuli();
    for (int unsigned i = 0; i < DataWidth; i++) begin
      new_stimuli[i] = $urandom();
    end
  endfunction : new_stimuli


  initial begin : proc_stream_consume
    @(posedge rst_n);
    gnt_oup = 1'b0;
    forever begin
      gnt_oup <= #ApplTime 1'b1;
      @(posedge clk);
    end
  end


  initial begin : proc_flush
    automatic int unsigned rand_wait;
    flush = 1'b0;
    @(posedge rst_n);
    forever begin
      rand_wait = $urandom_range(2000, 20000);
      repeat (rand_wait) @(posedge clk);
      flush <= #ApplTime 1'b1;
      @(posedge clk);
      flush <= #ApplTime 1'b0;
    end
  end


  initial begin : proc_sim_end
    @(posedge rst_n);
    wait (&end_of_sim);
    repeat (10) @(posedge clk);
    $stop();
  end


  for (genvar i = 0; i < NumInp; i++) begin : gen_throughput_checker
    initial begin : proc_throughput_checker
      automatic longint unsigned tot_active [NumInp:1];
      automatic longint unsigned tot_served [NumInp:1];
      automatic int     unsigned num_active;
      automatic real             throughput, exp_through, error;
      for (int unsigned j = 0; j < NumInp; j++) begin
       tot_active[j] = 0;
       tot_served[j] = 0;
      end

      @(posedge rst_n);
      while (!(&end_of_sim)) begin
        #TestTime;

        if (req_inp[i] && gnt_oup) begin
          num_active = 0;
          for (int unsigned j = 0; j < NumInp; j++) begin
            if (req_inp[j]) begin
              num_active++;
            end
          end

          tot_active[num_active] = tot_active[num_active] + 1;
          if (gnt_inp[i]) begin
            tot_served[num_active] = tot_served[num_active] + 1;
          end
        end
        @(posedge clk);
      end

      for (int unsigned j = 1; j <= NumInp; j++) begin
        if (tot_active[j] > 0) begin
          throughput  = real'(tot_served[j])/real'(tot_active[j]);
          exp_through = real'(1)/real'(j);
          error       = throughput - exp_through;
          if (FairArb && LockIn) begin
            assert(error < error_threshold && error > -error_threshold) else
                $warning("Line: %0d is unfair!", i);
          end
          $display("Line: %0d, TotActice: %0d Throughput: %0f Ideal: %0f Diff: %0f",
              i, j, throughput, exp_through, error);        end
      end
    end
  end


  initial begin : proc_check_data
    automatic data_t data_queues[NumInp-1:0][$];
    automatic data_t exp_data;
    forever begin
      @(posedge clk);
      #TestTime;

      for (int unsigned i = 0; i < NumInp; i++) begin
        if (req_inp[i] && gnt_inp[i]) begin
          data_queues[i].push_back(data_inp[i]);
        end
      end


      if (req_oup && gnt_oup) begin
        exp_data = data_queues[idx].pop_front();
        assert(exp_data === data_oup);
      end
    end
  end


  rr_arb_tree #(
    .NumIn     ( NumInp    ),
    .DataWidth ( DataWidth ),
    .ExtPrio   ( 1'b0      ),
    .AxiVldRdy ( AxiVldRdy ),
    .LockIn    ( LockIn    ),
    .FairArb   ( FairArb   )
  ) i_rr_arb_tree_dut (
    .clk_i  ( clk      ),
    .rst_ni ( rst_n    ),
    .flush_i( flush    ),
    .rr_i   ( '0       ),
    .req_i  ( req_inp  ),
    .gnt_o  ( gnt_inp  ),
    .data_i ( data_inp ),
    .gnt_i  ( gnt_oup  ),
    .req_o  ( req_oup  ),
    .data_o ( data_oup ),
    .idx_o  ( idx      )
  );
endmodule
module rr_arb_tree_tb #(

  parameter int unsigned NumInp    = 32'd7,

  parameter int unsigned NumReqs   = 32'd20000,

  parameter bit          AxiVldRdy = 1'b1,

  parameter bit          LockIn    = 1'b1,

  parameter bit          FairArb   = 1'b1
);


  localparam time CyclTime = 10ns;
  localparam time ApplTime = 2ns;
  localparam time TestTime = 8ns;



  localparam real error_threshold = 0.1;

  localparam int unsigned IdxWidth  = (NumInp > 32'd1) ? unsigned'($clog2(NumInp)) : 32'd1;
  localparam int unsigned DataWidth = 32'd45;
  typedef logic [IdxWidth-1:0]  idx_t;
  typedef logic [DataWidth-1:0] data_t;


  logic               clk;
  logic               rst_n;
  logic               flush;
  idx_t               rr,       idx;
  logic  [NumInp-1:0] req_inp,  gnt_inp, end_of_sim;
  data_t [NumInp-1:0] data_inp;
  logic               req_oup,  gnt_oup;
  data_t              data_oup;


  clk_rst_gen #(
    .ClkPeriod    ( CyclTime ),
    .RstClkCycles ( 5        )
  ) i_clk_rst_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );



  for (genvar i = 0; i < NumInp; i++) begin : gen_stream_gen
    initial begin : proc_stream_gen
      automatic data_t       stimuli;
      automatic int unsigned rand_wait;

      end_of_sim[i] = 1'b0;
      @(posedge rst_n);
      data_inp[i] = '0;
      req_inp[i]  = 1'b0;


      for (int unsigned j = 0; j < (i+1) * NumReqs; j++) begin
        data_inp[i] <= #ApplTime data_t'(i);
        req_inp[i]  <= #ApplTime 1'b1;
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;


      repeat ((NumInp-i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);


      for (int unsigned j = 0; j < (NumInp-i) * NumReqs; j++) begin
        data_inp[i] <= #ApplTime data_t'(i);
        req_inp[i]  <= #ApplTime 1'b1;
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;

      repeat ((1+i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);


      for (int unsigned j = 0; j < (NumInp-i) * NumReqs; j++) begin
        if ((i % 2) == 0) begin
          data_inp[i] <= #ApplTime data_t'(i);
          req_inp[i]  <= #ApplTime 1'b1;
        end
        @(posedge clk);
      end
      data_inp[i] <= #ApplTime '0;
      req_inp[i]  <= #ApplTime 1'b0;

      repeat ((1+i)*NumReqs) @(posedge clk);
      repeat (1000) @(posedge clk);



      for (int unsigned j = 0; j < NumReqs; j++) begin
        data_inp[i] <= #ApplTime new_stimuli();
        req_inp[i]  <= #ApplTime 1'b1;
        rand_wait = $urandom_range(1, 2*NumInp);
        if (LockIn) begin
          #TestTime;
          while (!gnt_inp[i]) begin
            @(posedge clk);
            #TestTime;
          end
        end else begin
          repeat (rand_wait) @(posedge clk);
        end
        @(posedge clk);
        data_inp[i] <= #ApplTime '0;
        req_inp[i]  <= #ApplTime 1'b0;

        rand_wait = $urandom_range(0, NumInp);
        repeat (rand_wait) @(posedge clk);
      end

      end_of_sim[i] = 1'b1;
    end
  end

  function data_t new_stimuli();
    for (int unsigned i = 0; i < DataWidth; i++) begin
      new_stimuli[i] = $urandom();
    end
  endfunction : new_stimuli


  initial begin : proc_stream_consume
    @(posedge rst_n);
    gnt_oup = 1'b0;
    forever begin
      gnt_oup <= #ApplTime 1'b1;
      @(posedge clk);
    end
  end


  initial begin : proc_flush
    automatic int unsigned rand_wait;
    flush = 1'b0;
    @(posedge rst_n);
    forever begin
      rand_wait = $urandom_range(2000, 20000);
      repeat (rand_wait) @(posedge clk);
      flush <= #ApplTime 1'b1;
      @(posedge clk);
      flush <= #ApplTime 1'b0;
    end
  end


  initial begin : proc_sim_end
    @(posedge rst_n);
    wait (&end_of_sim);
    repeat (10) @(posedge clk);
    $stop();
  end


  for (genvar i = 0; i < NumInp; i++) begin : gen_throughput_checker
    initial begin : proc_throughput_checker
      automatic longint unsigned tot_active [NumInp:1];
      automatic longint unsigned tot_served [NumInp:1];
      automatic int     unsigned num_active;
      automatic real             throughput, exp_through, error;
      for (int unsigned j = 0; j < NumInp; j++) begin
       tot_active[j] = 0;
       tot_served[j] = 0;
      end

      @(posedge rst_n);
      while (!(&end_of_sim)) begin
        #TestTime;

        if (req_inp[i] && gnt_oup) begin
          num_active = 0;
          for (int unsigned j = 0; j < NumInp; j++) begin
            if (req_inp[j]) begin
              num_active++;
            end
          end

          tot_active[num_active] = tot_active[num_active] + 1;
          if (gnt_inp[i]) begin
            tot_served[num_active] = tot_served[num_active] + 1;
          end
        end
        @(posedge clk);
      end

      for (int unsigned j = 1; j <= NumInp; j++) begin
        if (tot_active[j] > 0) begin
          throughput  = real'(tot_served[j])/real'(tot_active[j]);
          exp_through = real'(1)/real'(j);
          error       = throughput - exp_through;
          if (FairArb && LockIn) begin
            assert(error < error_threshold && error > -error_threshold) else
                $warning("Line: %0d is unfair!", i);
          end
          $display("Line: %0d, TotActice: %0d Throughput: %0f Ideal: %0f Diff: %0f",
              i, j, throughput, exp_through, error);        end
      end
    end
  end


  initial begin : proc_check_data
    automatic data_t data_queues[NumInp-1:0][$];
    automatic data_t exp_data;
    forever begin
      @(posedge clk);
      #TestTime;

      for (int unsigned i = 0; i < NumInp; i++) begin
        if (req_inp[i] && gnt_inp[i]) begin
          data_queues[i].push_back(data_inp[i]);
        end
      end


      if (req_oup && gnt_oup) begin
        exp_data = data_queues[idx].pop_front();
        assert(exp_data === data_oup);
      end
    end
  end


  rr_arb_tree #(
    .NumIn     ( NumInp    ),
    .DataWidth ( DataWidth ),
    .ExtPrio   ( 1'b0      ),
    .AxiVldRdy ( AxiVldRdy ),
    .LockIn    ( LockIn    ),
    .FairArb   ( FairArb   )
  ) i_rr_arb_tree_dut (
    .clk_i  ( clk      ),
    .rst_ni ( rst_n    ),
    .flush_i( flush    ),
    .rr_i   ( '0       ),
    .req_i  ( req_inp  ),
    .gnt_o  ( gnt_inp  ),
    .data_i ( data_inp ),
    .gnt_i  ( gnt_oup  ),
    .req_o  ( req_oup  ),
    .data_o ( data_oup ),
    .idx_o  ( idx      )
  );
endmodule