data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/MUX_2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/MUX_2.v:29: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'input1\' generates 4 bits.\n                                                                                        : ... In instance MUX_2\n    assign muxOut = SEL==select1 ? input1 : SEL==select2 ? input2 : \'bX;\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/MUX_2.v:29: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'input2\' generates 4 bits.\n                                                                                        : ... In instance MUX_2\n    assign muxOut = SEL==select1 ? input1 : SEL==select2 ? input2 : \'bX;\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/MUX_2.v:29: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                        : ... In instance MUX_2\n    assign muxOut = SEL==select1 ? input1 : SEL==select2 ? input2 : \'bX;\n                  ^\n%Error: Exiting due to 3 warning(s)\n'
module MUX_2 #(parameter WL = 4, WL_sel = 2)(
    input [WL_sel-1:0] SEL,
    input [WL_sel-1:0] select1, select2,
    input [WL-1:0] input1, input2,
    output [WL-1:0] muxOut
    );
    assign muxOut = SEL==select1 ? input1 : SEL==select2 ? input2 : 'bX;
endmodule
module MUX_2 #(parameter WL = 4, WL_sel = 2)(
    input [WL_sel-1:0] SEL,
    input [WL_sel-1:0] select1, select2,
    input [WL-1:0] input1, input2,
    output [WL-1:0] muxOut
    );

    assign muxOut = SEL==select1 ? input1 : SEL==select2 ? input2 : 'bX;
endmodule