data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cclk_inv_48x.v
data/verilator_xmls/f2e53ebc-35f0-4f74-9354-1e9010e95a15.xml
module bw_clk_cclk_inv_48x (
    clkout,
    clkin );

    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule
module bw_clk_cclk_inv_48x (
    clkout,
    clkin );


    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule