data/full_repos/permissive/489075769/read_address_ms.v
data/verilator_xmls/305d190c-6254-439f-b668-7f97aa70d8fb.xml
module read_address_master(ACLK, ARESETn, i_ARVALID, o_ARVALID, ARREADY, i_ARADDR, o_ARADDR, ARPROT);

input ACLK, ARESETn;
input i_ARVALID, ARREADY;
input [31:0] i_ARADDR;
input [2:0] ARPROT;
output reg o_ARVALID;
output reg [31:0] o_ARADDR;

always @(posedge ACLK) begin
o_ARVALID <= i_ARVALID;

if(ARESETn) begin
o_ARADDR <= 0;
o_ARVALID <= 0;
end

if(o_ARVALID && ARREADY) 
o_ARADDR <= 32'b11111111;
else  
o_ARADDR <= 32'b0;

end

endmodule
module read_address_master(ACLK, ARESETn, i_ARVALID, o_ARVALID, ARREADY, i_ARADDR, o_ARADDR, ARPROT);


input ACLK, ARESETn;
input i_ARVALID, ARREADY;
input [31:0] i_ARADDR;
input [2:0] ARPROT;
output reg o_ARVALID;
output reg [31:0] o_ARADDR;

always @(posedge ACLK) begin
o_ARVALID <= i_ARVALID;

if(ARESETn) begin
o_ARADDR <= 0;
o_ARVALID <= 0;
end

if(o_ARVALID && ARREADY) 
o_ARADDR <= 32'b11111111;
else  
o_ARADDR <= 32'b0;

end

endmodule