data/full_repos/permissive/447976230/fpga/usrp2/udp/add_onescomp.v
data/verilator_xmls/f3d5a02d-a5ee-4f10-af0b-4bd7ed179981.xml
module add_onescomp
  #(parameter WIDTH = 16)
   (input [WIDTH-1:0] A,
    input [WIDTH-1:0] B,
    output [WIDTH-1:0] SUM);

   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
   
endmodule
module add_onescomp
  #(parameter WIDTH = 16)
   (input [WIDTH-1:0] A,
    input [WIDTH-1:0] B,
    output [WIDTH-1:0] SUM);


   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
   
endmodule