data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:11: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_32f = ~clk_32f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:14: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_serial_parallel.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:19: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:22: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:24: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:26: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:31: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:34: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:36: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:38: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:43: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:46: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:48: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:50: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:55: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:58: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:60: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:62: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:67: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:71: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:73: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:75: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:77: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:79: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:81: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:83: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:86: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:88: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:90: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:92: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:94: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:96: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:98: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:100: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:103: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:105: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:107: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:109: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:111: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:113: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:115: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:117: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:120: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:122: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:124: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:126: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:131: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:135: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:137: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/serial-parallel/probador_serial_parallel.v:139: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_serial_parallel (
	output reg clk_32f,
	output reg reset,
	output reg Data_in,
	input valid_out_c,
	input [7:0] Data_out_c,
	input valid_out_e,
	input [7:0] Data_out_e
);
	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_serial_parallel.vcd");
		$dumpvars;

		reset <= 0;
		Data_in <= 0;
		@(posedge clk_32f);
		reset <= 1;
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_serial_parallel (
	output reg clk_32f,
	output reg reset,
	output reg Data_in,
	input valid_out_c,
	input [7:0] Data_out_c,
	input valid_out_e,
	input [7:0] Data_out_e
);

	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_serial_parallel.vcd");
		$dumpvars;

		reset <= 0;
		Data_in <= 0;
		@(posedge clk_32f);
		reset <= 1;
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 0;

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);

		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		Data_in <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule