data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/cluster_clock_xor2.sv
data/verilator_xmls/9c50595c-a6af-444f-81ae-a6b5c2e5d49c.xml
module cluster_clock_xor2
  (
   input  logic clk0_i,
   input  logic clk1_i,
   output logic clk_o
   );
   
   assign clk_o = clk0_i ^ clk1_i;
   
endmodule
module cluster_clock_xor2
  (
   input  logic clk0_i,
   input  logic clk1_i,
   output logic clk_o
   );

   
   assign clk_o = clk0_i ^ clk1_i;
   
endmodule