data/full_repos/permissive/520452389/source_codes/Instruction_decode.v
data/verilator_xmls/2e96dc06-b42e-437b-9353-c464005c937c.xml
module control (input [31:26]instruction,output reg RegDst,output reg  ALUSrc,output reg MemtoReg,output reg RegWrite, 
                output reg MemRead,output reg MemWrite,output reg Branch,output reg ALUOp1,output reg ALUOp0);

always @(instruction) begin 
case(instruction[31:26])

6'b000000: begin
		RegDst  =1;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 1;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 1;
		ALUOp0 = 0;
	end
6'b100011: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 0;
		RegWrite = 1;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b101011: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 1;
		RegWrite = 1;
		MemRead  = 1;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b000100: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 1;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b000101: begin
		RegDst  =0;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 1;
		ALUOp1 = 0;
		ALUOp0 = 1;

	end
default: begin
		RegDst  =1;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 1;
		ALUOp0 = 0;
	end
endcase
end

endmodule
module control (input [31:26]instruction,output reg RegDst,output reg  ALUSrc,output reg MemtoReg,output reg RegWrite, 
                output reg MemRead,output reg MemWrite,output reg Branch,output reg ALUOp1,output reg ALUOp0);


always @(instruction) begin 
case(instruction[31:26])

6'b000000: begin
		RegDst  =1;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 1;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 1;
		ALUOp0 = 0;
	end
6'b100011: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 0;
		RegWrite = 1;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b101011: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 1;
		RegWrite = 1;
		MemRead  = 1;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b000100: begin
		RegDst  =0;
		ALUSrc = 1;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 1;
		Branch = 0;
		ALUOp1 = 0;
		ALUOp0 = 0;
	end
6'b000101: begin
		RegDst  =0;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 1;
		ALUOp1 = 0;
		ALUOp0 = 1;

	end
default: begin
		RegDst  =1;
		ALUSrc = 0;
		MemtoReg = 0;
		RegWrite = 0;
		MemRead  = 0;
		MemWrite = 0;
		Branch = 0;
		ALUOp1 = 1;
		ALUOp0 = 0;
	end
endcase
end

endmodule