data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/BranchAND.v
data/verilator_xmls/6c55765a-7a45-4a3e-a4ee-62311b57a055.xml
module BranchAND(
    input Branch,
    input Zero,
    output reg PCSelOut
    );    

    
    initial PCSelOut <= 0;
    always@(*)begin
        if ((Branch&&Zero)==1)  begin
            PCSelOut <= 1;
        end
        else begin
            PCSelOut <= 0;
        end
    end
endmodule
module BranchAND(
    input Branch,
    input Zero,
    output reg PCSelOut
    );
    

    
    initial PCSelOut <= 0;
    always@(*)begin
        if ((Branch&&Zero)==1)  begin
            PCSelOut <= 1;
        end
        else begin
            PCSelOut <= 0;
        end
    end
endmodule