data/full_repos/permissive/43856783/j1_soc/hdl/LCD/clk_interruptor.v
data/verilator_xmls/959fe6ba-8b51-4a2d-99d8-46143fa88d37.xml
module clk_interruptor(
    input clk,
    input en,
    input [31:0] limit,
    input [31:0] count,
    output reg int_0
    );

	 reg [31:0] int_Count;
	 
	 always@(negedge clk) begin
		if(en) begin
			if (count < int_Count)begin
				int_0 <= 1'b0;
			end
			else begin
				int_0 <= 1'b1;
			end
			int_Count <= int_Count;
		end	
		else begin
			int_0 <= 1'b0;
			int_Count <= count+limit;
		end
	end
endmodule
module clk_interruptor(
    input clk,
    input en,
    input [31:0] limit,
    input [31:0] count,
    output reg int_0
    );


	 reg [31:0] int_Count;
	 
	 always@(negedge clk) begin
		if(en) begin
			if (count < int_Count)begin
				int_0 <= 1'b0;
			end
			else begin
				int_0 <= 1'b1;
			end
			int_Count <= int_Count;
		end	
		else begin
			int_0 <= 1'b0;
			int_Count <= count+limit;
		end
	end
endmodule