data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v:112: Cannot find file containing module: 'NV_NVDLA_CDP_slcg'\nNV_NVDLA_CDP_slcg u_slcg (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp,data/full_repos/permissive/509468557/NV_NVDLA_CDP_slcg\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp,data/full_repos/permissive/509468557/NV_NVDLA_CDP_slcg.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp,data/full_repos/permissive/509468557/NV_NVDLA_CDP_slcg.sv\n             NV_NVDLA_CDP_slcg\n             NV_NVDLA_CDP_slcg.v\n             NV_NVDLA_CDP_slcg.sv\n             obj_dir/NV_NVDLA_CDP_slcg\n             obj_dir/NV_NVDLA_CDP_slcg.v\n             obj_dir/NV_NVDLA_CDP_slcg.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v:124: Cannot find file containing module: 'NV_NVDLA_CDP_RDMA_ig'\n NV_NVDLA_CDP_RDMA_ig u_ig (\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v:155: Cannot find file containing module: 'NV_NVDLA_CDP_RDMA_cq'\n NV_NVDLA_CDP_RDMA_cq u_cq (\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v:169: Cannot find file containing module: 'NV_NVDLA_CDP_RDMA_eg'\n NV_NVDLA_CDP_RDMA_eg u_eg (\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v:197: Cannot find file containing module: 'NV_NVDLA_CDP_RDMA_reg'\n NV_NVDLA_CDP_RDMA_reg u_reg (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module NV_NVDLA_CDP_rdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cdp2cvif_rd_cdt_lat_fifo_pop
  ,cdp2cvif_rd_req_valid
  ,cdp2cvif_rd_req_ready
  ,cdp2cvif_rd_req_pd
  ,cdp2mcif_rd_cdt_lat_fifo_pop
  ,cdp2mcif_rd_req_valid
  ,cdp2mcif_rd_req_ready
  ,cdp2mcif_rd_req_pd
  ,cdp_rdma2csb_resp_valid
  ,cdp_rdma2csb_resp_pd
  ,cdp_rdma2dp_valid
  ,cdp_rdma2dp_ready
  ,cdp_rdma2dp_pd
  ,csb2cdp_rdma_req_pvld
  ,csb2cdp_rdma_req_prdy
  ,csb2cdp_rdma_req_pd
  ,cvif2cdp_rd_rsp_valid
  ,cvif2cdp_rd_rsp_ready
  ,cvif2cdp_rd_rsp_pd
  ,mcif2cdp_rd_rsp_valid
  ,mcif2cdp_rd_rsp_ready
  ,mcif2cdp_rd_rsp_pd
  ,pwrbus_ram_pd
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,tmc2slcg_disable_clock_gating
  );



 input  nvdla_core_clk;
 input  nvdla_core_rstn;

 output  cdp2cvif_rd_cdt_lat_fifo_pop;

 output        cdp2cvif_rd_req_valid;
 input         cdp2cvif_rd_req_ready;
 output [78:0] cdp2cvif_rd_req_pd;

 output  cdp2mcif_rd_cdt_lat_fifo_pop;

 output        cdp2mcif_rd_req_valid;
 input         cdp2mcif_rd_req_ready;
 output [78:0] cdp2mcif_rd_req_pd;

 output        cdp_rdma2csb_resp_valid;
 output [33:0] cdp_rdma2csb_resp_pd;

 output        cdp_rdma2dp_valid;
 input         cdp_rdma2dp_ready;
 output [86:0] cdp_rdma2dp_pd;

 input         csb2cdp_rdma_req_pvld;
 output        csb2cdp_rdma_req_prdy;
 input  [62:0] csb2cdp_rdma_req_pd;

 input          cvif2cdp_rd_rsp_valid;
 output         cvif2cdp_rd_rsp_ready;
 input  [513:0] cvif2cdp_rd_rsp_pd;

 input          mcif2cdp_rd_rsp_valid;
 output         mcif2cdp_rd_rsp_ready;
 input  [513:0] mcif2cdp_rd_rsp_pd;

 input [31:0] pwrbus_ram_pd;

input   dla_clk_ovr_on_sync;
input   global_clk_ovr_on_sync;
input   tmc2slcg_disable_clock_gating;

wire  [6:0] cq_rd_pd;
wire        cq_rd_prdy;
wire        cq_rd_pvld;
wire  [6:0] cq_wr_pd;
wire        cq_wr_prdy;
wire        cq_wr_pvld;
wire [31:0] dp2reg_d0_perf_read_stall;
wire [31:0] dp2reg_d1_perf_read_stall;
wire        dp2reg_done;
wire        eg2ig_done;
wire        nvdla_op_gated_clk;
wire [12:0] reg2dp_channel;
wire [31:0] reg2dp_cya;
wire  [0:0] reg2dp_dma_en;
wire [12:0] reg2dp_height;
wire  [1:0] reg2dp_input_data;
wire  [0:0] reg2dp_op_en;
wire [31:0] reg2dp_src_base_addr_high;
wire [26:0] reg2dp_src_base_addr_low;
wire [26:0] reg2dp_src_line_stride;
wire  [0:0] reg2dp_src_ram_type;
wire [26:0] reg2dp_src_surface_stride;
wire [12:0] reg2dp_width;
wire        slcg_op_en;




NV_NVDLA_CDP_slcg u_slcg (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.slcg_en_src                   (slcg_op_en)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk)
  );



 NV_NVDLA_CDP_RDMA_ig u_ig (
    .reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_dma_en                 (reg2dp_dma_en[0])
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_op_en                  (reg2dp_op_en[0])
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type[0])
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_d0_perf_read_stall     (dp2reg_d0_perf_read_stall[31:0])
   ,.dp2reg_d1_perf_read_stall     (dp2reg_d1_perf_read_stall[31:0])
   ,.eg2ig_done                    (eg2ig_done)
   ,.nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cdp2mcif_rd_req_valid         (cdp2mcif_rd_req_valid)
   ,.cdp2mcif_rd_req_ready         (cdp2mcif_rd_req_ready)
   ,.cdp2mcif_rd_req_pd            (cdp2mcif_rd_req_pd[78:0])
   ,.cdp2cvif_rd_req_valid         (cdp2cvif_rd_req_valid)
   ,.cdp2cvif_rd_req_ready         (cdp2cvif_rd_req_ready)
   ,.cdp2cvif_rd_req_pd            (cdp2cvif_rd_req_pd[78:0])
   ,.cq_wr_pvld                    (cq_wr_pvld)
   ,.cq_wr_prdy                    (cq_wr_prdy)
   ,.cq_wr_pd                      (cq_wr_pd[6:0])
   );




 NV_NVDLA_CDP_RDMA_cq u_cq (
    .nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cq_wr_prdy                    (cq_wr_prdy)
   ,.cq_wr_pvld                    (cq_wr_pvld)
   ,.cq_wr_pd                      (cq_wr_pd[6:0])
   ,.cq_rd_prdy                    (cq_rd_prdy)
   ,.cq_rd_pvld                    (cq_rd_pvld)
   ,.cq_rd_pd                      (cq_rd_pd[6:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );



 NV_NVDLA_CDP_RDMA_eg u_eg (
    .reg2dp_channel                (reg2dp_channel[4:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.dp2reg_done                   (dp2reg_done)
   ,.eg2ig_done                    (eg2ig_done)
   ,.nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.mcif2cdp_rd_rsp_valid         (mcif2cdp_rd_rsp_valid)
   ,.mcif2cdp_rd_rsp_ready         (mcif2cdp_rd_rsp_ready)
   ,.mcif2cdp_rd_rsp_pd            (mcif2cdp_rd_rsp_pd[513:0])
   ,.cdp2mcif_rd_cdt_lat_fifo_pop  (cdp2mcif_rd_cdt_lat_fifo_pop)
   ,.cvif2cdp_rd_rsp_valid         (cvif2cdp_rd_rsp_valid)
   ,.cvif2cdp_rd_rsp_ready         (cvif2cdp_rd_rsp_ready)
   ,.cvif2cdp_rd_rsp_pd            (cvif2cdp_rd_rsp_pd[513:0])
   ,.cdp2cvif_rd_cdt_lat_fifo_pop  (cdp2cvif_rd_cdt_lat_fifo_pop)
   ,.cdp_rdma2dp_valid             (cdp_rdma2dp_valid)
   ,.cdp_rdma2dp_ready             (cdp_rdma2dp_ready)
   ,.cdp_rdma2dp_pd                (cdp_rdma2dp_pd[86:0])
   ,.cq_rd_pvld                    (cq_rd_pvld)
   ,.cq_rd_prdy                    (cq_rd_prdy)
   ,.cq_rd_pd                      (cq_rd_pd[6:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );




 NV_NVDLA_CDP_RDMA_reg u_reg (
    .nvdla_core_clk                (nvdla_core_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.csb2cdp_rdma_req_pd           (csb2cdp_rdma_req_pd[62:0])
   ,.csb2cdp_rdma_req_pvld         (csb2cdp_rdma_req_pvld)
   ,.dp2reg_d0_perf_read_stall     (dp2reg_d0_perf_read_stall[31:0])
   ,.dp2reg_d1_perf_read_stall     (dp2reg_d1_perf_read_stall[31:0])
   ,.dp2reg_done                   (dp2reg_done)
   ,.cdp_rdma2csb_resp_pd          (cdp_rdma2csb_resp_pd[33:0])
   ,.cdp_rdma2csb_resp_valid       (cdp_rdma2csb_resp_valid)
   ,.csb2cdp_rdma_req_prdy         (csb2cdp_rdma_req_prdy)
   ,.reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_cya                    (reg2dp_cya[31:0])
   ,.reg2dp_dma_en                 (reg2dp_dma_en)
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_op_en                  (reg2dp_op_en)
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.slcg_op_en                    (slcg_op_en)
   );



endmodule
module NV_NVDLA_CDP_rdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cdp2cvif_rd_cdt_lat_fifo_pop
  ,cdp2cvif_rd_req_valid
  ,cdp2cvif_rd_req_ready
  ,cdp2cvif_rd_req_pd
  ,cdp2mcif_rd_cdt_lat_fifo_pop
  ,cdp2mcif_rd_req_valid
  ,cdp2mcif_rd_req_ready
  ,cdp2mcif_rd_req_pd
  ,cdp_rdma2csb_resp_valid
  ,cdp_rdma2csb_resp_pd
  ,cdp_rdma2dp_valid
  ,cdp_rdma2dp_ready
  ,cdp_rdma2dp_pd
  ,csb2cdp_rdma_req_pvld
  ,csb2cdp_rdma_req_prdy
  ,csb2cdp_rdma_req_pd
  ,cvif2cdp_rd_rsp_valid
  ,cvif2cdp_rd_rsp_ready
  ,cvif2cdp_rd_rsp_pd
  ,mcif2cdp_rd_rsp_valid
  ,mcif2cdp_rd_rsp_ready
  ,mcif2cdp_rd_rsp_pd
  ,pwrbus_ram_pd
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,tmc2slcg_disable_clock_gating
  );




 input  nvdla_core_clk;
 input  nvdla_core_rstn;

 output  cdp2cvif_rd_cdt_lat_fifo_pop;

 output        cdp2cvif_rd_req_valid;
 input         cdp2cvif_rd_req_ready;
 output [78:0] cdp2cvif_rd_req_pd;

 output  cdp2mcif_rd_cdt_lat_fifo_pop;

 output        cdp2mcif_rd_req_valid;
 input         cdp2mcif_rd_req_ready;
 output [78:0] cdp2mcif_rd_req_pd;

 output        cdp_rdma2csb_resp_valid;
 output [33:0] cdp_rdma2csb_resp_pd;

 output        cdp_rdma2dp_valid;
 input         cdp_rdma2dp_ready;
 output [86:0] cdp_rdma2dp_pd;

 input         csb2cdp_rdma_req_pvld;
 output        csb2cdp_rdma_req_prdy;
 input  [62:0] csb2cdp_rdma_req_pd;

 input          cvif2cdp_rd_rsp_valid;
 output         cvif2cdp_rd_rsp_ready;
 input  [513:0] cvif2cdp_rd_rsp_pd;

 input          mcif2cdp_rd_rsp_valid;
 output         mcif2cdp_rd_rsp_ready;
 input  [513:0] mcif2cdp_rd_rsp_pd;

 input [31:0] pwrbus_ram_pd;

input   dla_clk_ovr_on_sync;
input   global_clk_ovr_on_sync;
input   tmc2slcg_disable_clock_gating;

wire  [6:0] cq_rd_pd;
wire        cq_rd_prdy;
wire        cq_rd_pvld;
wire  [6:0] cq_wr_pd;
wire        cq_wr_prdy;
wire        cq_wr_pvld;
wire [31:0] dp2reg_d0_perf_read_stall;
wire [31:0] dp2reg_d1_perf_read_stall;
wire        dp2reg_done;
wire        eg2ig_done;
wire        nvdla_op_gated_clk;
wire [12:0] reg2dp_channel;
wire [31:0] reg2dp_cya;
wire  [0:0] reg2dp_dma_en;
wire [12:0] reg2dp_height;
wire  [1:0] reg2dp_input_data;
wire  [0:0] reg2dp_op_en;
wire [31:0] reg2dp_src_base_addr_high;
wire [26:0] reg2dp_src_base_addr_low;
wire [26:0] reg2dp_src_line_stride;
wire  [0:0] reg2dp_src_ram_type;
wire [26:0] reg2dp_src_surface_stride;
wire [12:0] reg2dp_width;
wire        slcg_op_en;




NV_NVDLA_CDP_slcg u_slcg (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.slcg_en_src                   (slcg_op_en)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk)
  );



 NV_NVDLA_CDP_RDMA_ig u_ig (
    .reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_dma_en                 (reg2dp_dma_en[0])
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_op_en                  (reg2dp_op_en[0])
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type[0])
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_d0_perf_read_stall     (dp2reg_d0_perf_read_stall[31:0])
   ,.dp2reg_d1_perf_read_stall     (dp2reg_d1_perf_read_stall[31:0])
   ,.eg2ig_done                    (eg2ig_done)
   ,.nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cdp2mcif_rd_req_valid         (cdp2mcif_rd_req_valid)
   ,.cdp2mcif_rd_req_ready         (cdp2mcif_rd_req_ready)
   ,.cdp2mcif_rd_req_pd            (cdp2mcif_rd_req_pd[78:0])
   ,.cdp2cvif_rd_req_valid         (cdp2cvif_rd_req_valid)
   ,.cdp2cvif_rd_req_ready         (cdp2cvif_rd_req_ready)
   ,.cdp2cvif_rd_req_pd            (cdp2cvif_rd_req_pd[78:0])
   ,.cq_wr_pvld                    (cq_wr_pvld)
   ,.cq_wr_prdy                    (cq_wr_prdy)
   ,.cq_wr_pd                      (cq_wr_pd[6:0])
   );




 NV_NVDLA_CDP_RDMA_cq u_cq (
    .nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cq_wr_prdy                    (cq_wr_prdy)
   ,.cq_wr_pvld                    (cq_wr_pvld)
   ,.cq_wr_pd                      (cq_wr_pd[6:0])
   ,.cq_rd_prdy                    (cq_rd_prdy)
   ,.cq_rd_pvld                    (cq_rd_pvld)
   ,.cq_rd_pd                      (cq_rd_pd[6:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );



 NV_NVDLA_CDP_RDMA_eg u_eg (
    .reg2dp_channel                (reg2dp_channel[4:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.dp2reg_done                   (dp2reg_done)
   ,.eg2ig_done                    (eg2ig_done)
   ,.nvdla_core_clk                (nvdla_op_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.mcif2cdp_rd_rsp_valid         (mcif2cdp_rd_rsp_valid)
   ,.mcif2cdp_rd_rsp_ready         (mcif2cdp_rd_rsp_ready)
   ,.mcif2cdp_rd_rsp_pd            (mcif2cdp_rd_rsp_pd[513:0])
   ,.cdp2mcif_rd_cdt_lat_fifo_pop  (cdp2mcif_rd_cdt_lat_fifo_pop)
   ,.cvif2cdp_rd_rsp_valid         (cvif2cdp_rd_rsp_valid)
   ,.cvif2cdp_rd_rsp_ready         (cvif2cdp_rd_rsp_ready)
   ,.cvif2cdp_rd_rsp_pd            (cvif2cdp_rd_rsp_pd[513:0])
   ,.cdp2cvif_rd_cdt_lat_fifo_pop  (cdp2cvif_rd_cdt_lat_fifo_pop)
   ,.cdp_rdma2dp_valid             (cdp_rdma2dp_valid)
   ,.cdp_rdma2dp_ready             (cdp_rdma2dp_ready)
   ,.cdp_rdma2dp_pd                (cdp_rdma2dp_pd[86:0])
   ,.cq_rd_pvld                    (cq_rd_pvld)
   ,.cq_rd_prdy                    (cq_rd_prdy)
   ,.cq_rd_pd                      (cq_rd_pd[6:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );




 NV_NVDLA_CDP_RDMA_reg u_reg (
    .nvdla_core_clk                (nvdla_core_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.csb2cdp_rdma_req_pd           (csb2cdp_rdma_req_pd[62:0])
   ,.csb2cdp_rdma_req_pvld         (csb2cdp_rdma_req_pvld)
   ,.dp2reg_d0_perf_read_stall     (dp2reg_d0_perf_read_stall[31:0])
   ,.dp2reg_d1_perf_read_stall     (dp2reg_d1_perf_read_stall[31:0])
   ,.dp2reg_done                   (dp2reg_done)
   ,.cdp_rdma2csb_resp_pd          (cdp_rdma2csb_resp_pd[33:0])
   ,.cdp_rdma2csb_resp_valid       (cdp_rdma2csb_resp_valid)
   ,.csb2cdp_rdma_req_prdy         (csb2cdp_rdma_req_prdy)
   ,.reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_cya                    (reg2dp_cya[31:0])
   ,.reg2dp_dma_en                 (reg2dp_dma_en)
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_input_data             (reg2dp_input_data[1:0])
   ,.reg2dp_op_en                  (reg2dp_op_en)
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.slcg_op_en                    (slcg_op_en)
   );



endmodule