data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:88: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:95: syntax error, unexpected \'@\'\n  @(posedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:111: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PE_tb.v:125: syntax error, unexpected \'@\'\n  @(posedge tb_clk)\n  ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE_tb();



parameter tb_px_width=9;
parameter tb_w_width=9;
parameter tb_data_out_width=9;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_reg_set;
reg tb_reset;
reg tb_fifo_set;
reg [tb_data_out_width-1:0] tb_is;
reg [tb_px_width-1:0]tb_if_px;
reg [tb_w_width-1:0] tb_w;


wire [tb_data_out_width-1:0] tb_out;
reg  [tb_data_out_width-1:0] tb_expected_out;



PE #(.PX_WIDTH(tb_px_width),.W_WIDTH(tb_w_width),.DATA_OUT_WIDTH(tb_data_out_width)) Pe(

.PE_Clk(tb_clk),
.PE_Out_Reg_Set(tb_reg_set),
.PE_Reset(tb_reset),
.PE_Fifo_Set(tb_fifo_set),
.PE_Is(tb_is),
.PE_If_Px(tb_if_px),
.PE_w(tb_w),
.PE_Out(tb_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	$display($time, " << Starting the Simulation >>");

	tb_reset<=0;
	tb_reg_set<=0;
	tb_fifo_set<=0;
	tb_is<=4;
	tb_if_px<=5;
	tb_w<=-2;
	tb_expected_out<=0;
	

	
	for (i=0; i<5;i=i+1)begin
	
		@(negedge tb_clk)
		tb_reset<=1;
		tb_reg_set<=1;
		tb_fifo_set<=0;
		verify_output(tb_out,tb_expected_out);
		
	
		@(posedge tb_clk)
		tb_reg_set<=0;
		tb_reset<=1;
		tb_fifo_set<=0;
		tb_expected_out<= (tb_if_px*tb_w) + tb_is;
		verify_output(tb_out,tb_expected_out);
		tb_if_px<=tb_if_px+1;
		tb_is<=tb_is+1;
		
	end
	
	

	
	for (i=0; i<5;i=i+1)begin
	
		@(negedge tb_clk)
		tb_reset<=1;
		tb_reg_set<=1;
		
		if((i%2)==0)
			begin
				tb_fifo_set<=1;
				tb_expected_out<=(tb_if_px*tb_w) + tb_is;
				verify_output(tb_out,tb_expected_out);
			end
	
		else
			tb_fifo_set<=0;
	
		@(posedge tb_clk)
		tb_reg_set<=0;
		tb_reset<=1;
		tb_fifo_set<=0;
		tb_expected_out<= (tb_if_px*tb_w) + tb_is;
		verify_output(tb_out,tb_expected_out);
		tb_if_px<=tb_if_px+1;
		tb_is<=tb_is+1;
		
	end
	
	$display($time," << Test passed >> ");
	
	$stop;

end


task verify_output;
	input [tb_data_out_width-1:0] out;
	input [tb_data_out_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask

endmodule
module PE_tb();




parameter tb_px_width=9;
parameter tb_w_width=9;
parameter tb_data_out_width=9;
parameter tb_clk_period=20;
integer i;


reg tb_clk;
reg tb_reg_set;
reg tb_reset;
reg tb_fifo_set;
reg [tb_data_out_width-1:0] tb_is;
reg [tb_px_width-1:0]tb_if_px;
reg [tb_w_width-1:0] tb_w;


wire [tb_data_out_width-1:0] tb_out;
reg  [tb_data_out_width-1:0] tb_expected_out;



PE #(.PX_WIDTH(tb_px_width),.W_WIDTH(tb_w_width),.DATA_OUT_WIDTH(tb_data_out_width)) Pe(

.PE_Clk(tb_clk),
.PE_Out_Reg_Set(tb_reg_set),
.PE_Reset(tb_reset),
.PE_Fifo_Set(tb_fifo_set),
.PE_Is(tb_is),
.PE_If_Px(tb_if_px),
.PE_w(tb_w),
.PE_Out(tb_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin

	$display($time, " << Starting the Simulation >>");

	tb_reset<=0;
	tb_reg_set<=0;
	tb_fifo_set<=0;
	tb_is<=4;
	tb_if_px<=5;
	tb_w<=-2;
	tb_expected_out<=0;
	

	
	for (i=0; i<5;i=i+1)begin
	
		@(negedge tb_clk)
		tb_reset<=1;
		tb_reg_set<=1;
		tb_fifo_set<=0;
		verify_output(tb_out,tb_expected_out);
		
	
		@(posedge tb_clk)
		tb_reg_set<=0;
		tb_reset<=1;
		tb_fifo_set<=0;
		tb_expected_out<= (tb_if_px*tb_w) + tb_is;
		verify_output(tb_out,tb_expected_out);
		tb_if_px<=tb_if_px+1;
		tb_is<=tb_is+1;
		
	end
	
	

	
	for (i=0; i<5;i=i+1)begin
	
		@(negedge tb_clk)
		tb_reset<=1;
		tb_reg_set<=1;
		
		if((i%2)==0)
			begin
				tb_fifo_set<=1;
				tb_expected_out<=(tb_if_px*tb_w) + tb_is;
				verify_output(tb_out,tb_expected_out);
			end
	
		else
			tb_fifo_set<=0;
	
		@(posedge tb_clk)
		tb_reg_set<=0;
		tb_reset<=1;
		tb_fifo_set<=0;
		tb_expected_out<= (tb_if_px*tb_w) + tb_is;
		verify_output(tb_out,tb_expected_out);
		tb_if_px<=tb_if_px+1;
		tb_is<=tb_is+1;
		
	end
	
	$display($time," << Test passed >> ");
	
	$stop;

end


task verify_output;
	input [tb_data_out_width-1:0] out;
	input [tb_data_out_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
endtask

endmodule