data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/black_box.v
data/verilator_xmls/97479240-2f82-4875-9bd2-688cc810ba94.xml
module black_box(
	input a,b,c,d,
	output x,y
    );
	 
assign x=a|(b&c);
assign y=b&d;
	 
endmodule
module black_box(
	input a,b,c,d,
	output x,y
    );

	 
assign x=a|(b&c);
assign y=b&d;
	 
endmodule