data/full_repos/permissive/520452389/source_codes/mips.v
1: b"%Error: data/full_repos/permissive/520452389/source_codes/mips.v:35: Duplicate declaration of signal: 'write_data_s4'\n                                                                   : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire [31:0] pc_out1_s2, extended_32_s2,read_data1_s2, read_data2_s2,write_data_s4;\n                                                                    ^~~~~~~~~~~~~\n        data/full_repos/permissive/520452389/source_codes/mips.v:21: ... Location of original declaration\nmodule pipelined_mipstest(input clk,input reset,output write_data_s4);\n                                                       ^~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module mux3 (input [31:0]read_data,input [31:0]ALU_output,input MemtoReg,output [31:0]write_data);
assign write_data = (MemtoReg)?read_data:ALU_output;
endmodule
module mux3 (input [31:0]read_data,input [31:0]ALU_output,input MemtoReg,output [31:0]write_data);

assign write_data = (MemtoReg)?read_data:ALU_output;
endmodule