data/full_repos/permissive/425966734/verilog/rtl/multiplier.v
data/verilator_xmls/d7e723d4-e36c-468d-83a2-0bc32375775e.xml
module multiplier   #(parameter n =16)  (data_i, amplify, multiplier_o);
  
  input   wire [n-1:0]   data_i;
  input   wire [7:0]     amplify; 
  output  wire [n-1:0]   multiplier_o;
    
  assign multiplier_o = data_i <<< amplify; 
  
endmodule
module multiplier   #(parameter n =16)  (data_i, amplify, multiplier_o);

  
  input   wire [n-1:0]   data_i;
  input   wire [7:0]     amplify; 
  output  wire [n-1:0]   multiplier_o;
    
  assign multiplier_o = data_i <<< amplify; 
  
endmodule