data/full_repos/permissive/460600765/rtl/fifo.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:55: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_empty_o     <= (tail == ADDR_LEN\'(head + 1));\n                                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:56: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 2)) || (tail == ADDR_LEN\'(head + 1));\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:56: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 2)) || (tail == ADDR_LEN\'(head + 1));\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:59: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 10 bits.\n                                                                   : ... In instance fifo\n            reader_alm_empty_o <= (tail == ADDR_LEN\'(head + 1)) || (tail == head);\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:65: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_full_o     <= (head == ADDR_LEN\'(tail + 2));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:66: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 3)) || (head == ADDR_LEN\'(tail + 2));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:66: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 3)) || (head == ADDR_LEN\'(tail + 2));\n                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:68: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_full_o     <= (head == ADDR_LEN\'(tail + 1));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:69: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 2)) || (head == ADDR_LEN\'(tail + 1));\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/460600765/rtl/fifo.sv:69: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 10 bits.\n                                                                   : ... In instance fifo\n            writer_alm_full_o <= (head == ADDR_LEN\'(tail + 2)) || (head == ADDR_LEN\'(tail + 1));\n                                                                                          ^\n%Error: Exiting due to 10 warning(s)\n'
module fifo #(
    parameter ADDR_LEN = 10,
    parameter DATA_WIDTH = 32
) (
    input  wire logic                  clk,
    input  wire logic                  reset_i,
    

    output      logic [DATA_WIDTH-1:0] reader_q_o,
    input  wire logic                  reader_deq_i,
    output      logic                  reader_empty_o,
    output      logic                  reader_alm_empty_o,


    input  wire logic [DATA_WIDTH-1:0] writer_d_i,
    input  wire logic                  writer_enq_i,
    output      logic                  writer_full_o,
    output      logic                  writer_alm_full_o
);

    localparam MEM_SIZE = 2 ** ADDR_LEN;

    logic [ADDR_LEN-1:0] head;
    logic [ADDR_LEN-1:0] tail;


    always_ff @(posedge clk) begin
        if (reset_i) begin
            head <= 0;
        end else begin
            if (!reader_empty_o && reader_deq_i) begin
                head <= head == (MEM_SIZE - 1) ? 0 : head + 1;
            end
        end
    end


    always_ff @(posedge clk) begin
        if (reset_i) begin
            tail <= 0;
        end else begin
            if (!writer_full_o && writer_enq_i)
                tail <= tail == (MEM_SIZE - 1) ? 0 : tail + 1;
        end
    end

    always_ff @(posedge clk) begin
        if (reader_deq_i && !reader_empty_o) begin
            reader_empty_o     <= (tail == ADDR_LEN'(head + 1));
            reader_alm_empty_o <= (tail == ADDR_LEN'(head + 2)) || (tail == ADDR_LEN'(head + 1));
        end else begin
            reader_empty_o     <= (tail == head);
            reader_alm_empty_o <= (tail == ADDR_LEN'(head + 1)) || (tail == head);
        end
    end

    always_ff @(posedge clk) begin
        if (writer_enq_i && !writer_full_o) begin
            writer_full_o     <= (head == ADDR_LEN'(tail + 2));
            writer_alm_full_o <= (head == ADDR_LEN'(tail + 3)) || (head == ADDR_LEN'(tail + 2));
        end else begin
            writer_full_o     <= (head == ADDR_LEN'(tail + 1));
            writer_alm_full_o <= (head == ADDR_LEN'(tail + 2)) || (head == ADDR_LEN'(tail + 1));
        end
    end

    logic ram_we;
    assign ram_we = writer_enq_i && !writer_full_o;
    bram2 #(
        .W_A(ADDR_LEN),
        .W_D(DATA_WIDTH)
    ) ram (
        .clk(clk),
        .addr0_i(head), .d0_i('h0), .we0_i(1'b0), .q0_o(reader_q_o),
        .addr1_i(tail), .d1_i(writer_d_i), .we1_i(ram_we), .q1_o()
    );

endmodule
module fifo #(
    parameter ADDR_LEN = 10,
    parameter DATA_WIDTH = 32
) (
    input  wire logic                  clk,
    input  wire logic                  reset_i,
    

    output      logic [DATA_WIDTH-1:0] reader_q_o,
    input  wire logic                  reader_deq_i,
    output      logic                  reader_empty_o,
    output      logic                  reader_alm_empty_o,


    input  wire logic [DATA_WIDTH-1:0] writer_d_i,
    input  wire logic                  writer_enq_i,
    output      logic                  writer_full_o,
    output      logic                  writer_alm_full_o
);


    localparam MEM_SIZE = 2 ** ADDR_LEN;

    logic [ADDR_LEN-1:0] head;
    logic [ADDR_LEN-1:0] tail;


    always_ff @(posedge clk) begin
        if (reset_i) begin
            head <= 0;
        end else begin
            if (!reader_empty_o && reader_deq_i) begin
                head <= head == (MEM_SIZE - 1) ? 0 : head + 1;
            end
        end
    end


    always_ff @(posedge clk) begin
        if (reset_i) begin
            tail <= 0;
        end else begin
            if (!writer_full_o && writer_enq_i)
                tail <= tail == (MEM_SIZE - 1) ? 0 : tail + 1;
        end
    end

    always_ff @(posedge clk) begin
        if (reader_deq_i && !reader_empty_o) begin
            reader_empty_o     <= (tail == ADDR_LEN'(head + 1));
            reader_alm_empty_o <= (tail == ADDR_LEN'(head + 2)) || (tail == ADDR_LEN'(head + 1));
        end else begin
            reader_empty_o     <= (tail == head);
            reader_alm_empty_o <= (tail == ADDR_LEN'(head + 1)) || (tail == head);
        end
    end

    always_ff @(posedge clk) begin
        if (writer_enq_i && !writer_full_o) begin
            writer_full_o     <= (head == ADDR_LEN'(tail + 2));
            writer_alm_full_o <= (head == ADDR_LEN'(tail + 3)) || (head == ADDR_LEN'(tail + 2));
        end else begin
            writer_full_o     <= (head == ADDR_LEN'(tail + 1));
            writer_alm_full_o <= (head == ADDR_LEN'(tail + 2)) || (head == ADDR_LEN'(tail + 1));
        end
    end

    logic ram_we;
    assign ram_we = writer_enq_i && !writer_full_o;
    bram2 #(
        .W_A(ADDR_LEN),
        .W_D(DATA_WIDTH)
    ) ram (
        .clk(clk),
        .addr0_i(head), .d0_i('h0), .we0_i(1'b0), .q0_o(reader_q_o),
        .addr1_i(tail), .d1_i(writer_d_i), .we1_i(ram_we), .q1_o()
    );

endmodule