data/full_repos/permissive/462122681/mdmux.v
data/verilator_xmls/7f7575b5-afdc-4f64-b299-d75682001b1b.xml
module MDMUX (
	output reg [31:0] MDMuxOut,
	input wire[31:0] BusMuxOut,
	input wire[31:0] MDataIn,
	input wire Read
);

	always@(*) begin
		if(Read) begin
			MDMuxOut[31:0] = MDataIn[31:0];
		end
		else begin
			MDMuxOut[31:0] = BusMuxOut[31:0];
		end
	end
endmodule
module MDMUX (
	output reg [31:0] MDMuxOut,
	input wire[31:0] BusMuxOut,
	input wire[31:0] MDataIn,
	input wire Read
);


	always@(*) begin
		if(Read) begin
			MDMuxOut[31:0] = MDataIn[31:0];
		end
		else begin
			MDMuxOut[31:0] = BusMuxOut[31:0];
		end
	end
endmodule