data/full_repos/permissive/437141606/MIPS.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/437141606/MIPS.v:259: Signal definition not found, creating implicitly: \'zero\'\n controller controller(instrD[31:26], instrD[5:0], zero,\n                                                   ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:313: Unsized numbers/parameters not allowed in concatenations.\n                                                                     : ... In instance mips.decode.rf\n    rf[{0,wa3[3:0]}] <= wd3;\n        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:313: Unsized numbers/parameters not allowed in replications.\n                                                                     : ... In instance mips.decode.rf\n    rf[{0,wa3[3:0]}] <= wd3;\n         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:315: Unsized numbers/parameters not allowed in concatenations.\n                                                                     : ... In instance mips.decode.rf\n    rf[{1,wa3[3:0]}] <= wd3;\n        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:315: Unsized numbers/parameters not allowed in replications.\n                                                                     : ... In instance mips.decode.rf\n    rf[{1,wa3[3:0]}] <= wd3;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:179: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                               : ... In instance mips.excute.alu\n assign sum = a + b2 + alucont[2];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:180: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                               : ... In instance mips.excute.alu\n assign slt = sum[31];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:134: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                               : ... In instance mips.memory.dmem\n   ram[n] = 8\'hFF;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:136: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n                                                               : ... In instance mips.memory.dmem\n assign dOut = ram[addr[31:2]];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:140: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n                                                               : ... In instance mips.memory.dmem\n   ram[addr[31:2]] = dIn; \n      ^\n%Error: Exiting due to 10 warning(s)\n'
module mips(input         clk, reset, 
				output [31:0] rd2D, aluoutM,
				output        memwriteD,
				input  [ 4:0] dispSel,
				output [31:0] dispDat, pcF, instrF);

	wire 		memtoregD, alusrcD, regdstD, regwriteD;
	wire		wlhD, memloD, memhiD, jalD;
	wire		memtoregE, memwriteE, alusrcE, regdstE, regwriteE,  wlhE, memloE, memhiE,  jalE;
	wire		regwriteM, memtoregM, memwriteM, wlhM, memloM, memhiM,  jalM;
	wire		regwriteW, memtoregW, memloW, memhiW, jalW;
	wire[2:0] 	alucontrolD, alucontrolE;
	wire[4:0]	resultAddW, rsE, rtE,rdE, writeregE, writeregM, writeregW;
	wire[31:0] 	resultW, pcplus4F, pcplus4D, instrD, rd1D, pcnextD;
	wire[31:0]	rd1E, rd2E,pcplus4E, signimmD, signimmE, aluoutE, loE, hiE;
	wire[31:0]	rd2M, loM, hiM, pcplus4M,readataM, loMout, hiMout;
	wire[31:0]	aluoutW, readataW, loW, hiW, pcplus4W;
	

	flopr #(32) pcreg(clk, reset, pcnextD,
					  pcF);
	fetch fetch (pcF, 
				 pcplus4F, instrF);
	

	flopr #(64) Dreg (clk, reset, {pcplus4F, instrF},
					  {pcplus4D, instrD});
	decode decode (clk, pcplus4F, pcplus4D, instrD, resultW,
				   resultAddW,
				   regwriteW,
				   memtoregD, memwriteD, alusrcD, regdstD, regwriteD, wlhD, memloD, memhiD, jalD,
				   alucontrolD,
				   rd1D, rd2D, signimmD, pcnextD,
				   dispSel, dispDat);
	

	flopr #(155) Ereg (clk, reset, {memtoregD, memwriteD, alusrcD, regdstD, regwriteD,  wlhD, memloD, memhiD,  jalD,
								   alucontrolD,
								   instrD[25:21], instrD[20:16], instrD[15:11],
								   rd1D, rd2D, signimmD, pcplus4D},
					  {memtoregE, memwriteE, alusrcE, regdstE, regwriteE,  wlhE, memloE, memhiE,  jalE,
						alucontrolE,
						rsE, rtE,rdE,
						rd1E, rd2E, signimmE, pcplus4E});
	excute	excute	(regdstE, alusrcE,
					 alucontrolE,
					 rtE, rdE,
					 rd1E, rd2E, signimmE,
					 writeregE,
					 aluoutE, loE, hiE);
	

	flopr #(172) Mreg (clk, reset, {regwriteE, memtoregE, memwriteE, wlhE, memloE, memhiE,  jalE,
								 writeregE,
								 aluoutE, rd2E, loE, hiE, pcplus4E},
								{regwriteM, memtoregM, memwriteM, wlhM, memloM, memhiM,  jalM,
								 writeregM,
								 aluoutM, rd2M, loM, hiM, pcplus4M});
	memory	memory	(clk, memwriteM, wlhM,
					 aluoutM, rd2M, loM, hiM,
					 readataM, loMout, hiMout);
	

	flopr #(170)	Wreg (clk, reset, {regwriteM, memtoregM, memloM, memhiM, jalM,
									writeregM,
									aluoutM, readataM, loMout, hiMout, pcplus4M},
								   {regwriteW, memtoregW, memloW, memhiW, jalW,
									writeregW,
									aluoutW, readataW, loW, hiW, pcplus4W});
	writeback writeback (memtoregW, memloW, memhiW, jalW,
						 writeregW,
						 aluoutW, readataW, loW, hiW, pcplus4W,
						 resultAddW,
						 resultW);

endmodule
module mips(input         clk, reset, 
				output [31:0] rd2D, aluoutM,
				output        memwriteD,
				input  [ 4:0] dispSel,
				output [31:0] dispDat, pcF, instrF);


	wire 		memtoregD, alusrcD, regdstD, regwriteD;
	wire		wlhD, memloD, memhiD, jalD;
	wire		memtoregE, memwriteE, alusrcE, regdstE, regwriteE,  wlhE, memloE, memhiE,  jalE;
	wire		regwriteM, memtoregM, memwriteM, wlhM, memloM, memhiM,  jalM;
	wire		regwriteW, memtoregW, memloW, memhiW, jalW;
	wire[2:0] 	alucontrolD, alucontrolE;
	wire[4:0]	resultAddW, rsE, rtE,rdE, writeregE, writeregM, writeregW;
	wire[31:0] 	resultW, pcplus4F, pcplus4D, instrD, rd1D, pcnextD;
	wire[31:0]	rd1E, rd2E,pcplus4E, signimmD, signimmE, aluoutE, loE, hiE;
	wire[31:0]	rd2M, loM, hiM, pcplus4M,readataM, loMout, hiMout;
	wire[31:0]	aluoutW, readataW, loW, hiW, pcplus4W;
	

	flopr #(32) pcreg(clk, reset, pcnextD,
					  pcF);
	fetch fetch (pcF, 
				 pcplus4F, instrF);
	

	flopr #(64) Dreg (clk, reset, {pcplus4F, instrF},
					  {pcplus4D, instrD});
	decode decode (clk, pcplus4F, pcplus4D, instrD, resultW,
				   resultAddW,
				   regwriteW,
				   memtoregD, memwriteD, alusrcD, regdstD, regwriteD, wlhD, memloD, memhiD, jalD,
				   alucontrolD,
				   rd1D, rd2D, signimmD, pcnextD,
				   dispSel, dispDat);
	

	flopr #(155) Ereg (clk, reset, {memtoregD, memwriteD, alusrcD, regdstD, regwriteD,  wlhD, memloD, memhiD,  jalD,
								   alucontrolD,
								   instrD[25:21], instrD[20:16], instrD[15:11],
								   rd1D, rd2D, signimmD, pcplus4D},
					  {memtoregE, memwriteE, alusrcE, regdstE, regwriteE,  wlhE, memloE, memhiE,  jalE,
						alucontrolE,
						rsE, rtE,rdE,
						rd1E, rd2E, signimmE, pcplus4E});
	excute	excute	(regdstE, alusrcE,
					 alucontrolE,
					 rtE, rdE,
					 rd1E, rd2E, signimmE,
					 writeregE,
					 aluoutE, loE, hiE);
	

	flopr #(172) Mreg (clk, reset, {regwriteE, memtoregE, memwriteE, wlhE, memloE, memhiE,  jalE,
								 writeregE,
								 aluoutE, rd2E, loE, hiE, pcplus4E},
								{regwriteM, memtoregM, memwriteM, wlhM, memloM, memhiM,  jalM,
								 writeregM,
								 aluoutM, rd2M, loM, hiM, pcplus4M});
	memory	memory	(clk, memwriteM, wlhM,
					 aluoutM, rd2M, loM, hiM,
					 readataM, loMout, hiMout);
	

	flopr #(170)	Wreg (clk, reset, {regwriteM, memtoregM, memloM, memhiM, jalM,
									writeregM,
									aluoutM, readataM, loMout, hiMout, pcplus4M},
								   {regwriteW, memtoregW, memloW, memhiW, jalW,
									writeregW,
									aluoutW, readataW, loW, hiW, pcplus4W});
	writeback writeback (memtoregW, memloW, memhiW, jalW,
						 writeregW,
						 aluoutW, readataW, loW, hiW, pcplus4W,
						 resultAddW,
						 resultW);

endmodule