data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/ALU_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/ALU_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/ALU_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/ALU_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/09_ALU/ALU_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_test(t1, t2, t3, p1);

output      t1, t2;
output [1:0]    t3;
input           p1;


reg        t1, t2;
reg   [1:0]    t3;

initial begin
   t1 <= 1'b0;    t2 <= 1'b1;
   t3 <= 2'b00;

   #100;
   t3 <= 2'b01;

    #100;
   t3 <= 2'b10;

    #100;
   t3 <= 2'b11;

   #100;
   $finish;
end

endmodule
module ALU_test(t1, t2, t3, p1);


output      t1, t2;
output [1:0]    t3;
input           p1;


reg        t1, t2;
reg   [1:0]    t3;

initial begin
   t1 <= 1'b0;    t2 <= 1'b1;
   t3 <= 2'b00;

   #100;
   t3 <= 2'b01;

    #100;
   t3 <= 2'b10;

    #100;
   t3 <= 2'b11;

   #100;
   $finish;
end

endmodule