data/full_repos/permissive/489306513/logiana_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #5 OSC_CLK = ~OSC_CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n always #20 CLK24 = ~CLK24;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #97;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #800;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:188: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:207: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:214: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:220: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:243: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:246: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:250: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:252: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:254: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:256: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:263: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:267: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:269: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:271: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:273: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:275: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:277: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:280: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:282: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:284: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:286: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:288: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:290: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:292: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:294: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:297: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:299: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:301: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:303: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:305: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:307: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:309: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489306513/logiana_test.v:311: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/489306513/logiana_test.v:39: Cannot find file containing module: \'logiana\'\n logiana uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489306513,data/full_repos/permissive/489306513/logiana\n             data/full_repos/permissive/489306513,data/full_repos/permissive/489306513/logiana.v\n             data/full_repos/permissive/489306513,data/full_repos/permissive/489306513/logiana.sv\n             logiana\n             logiana.v\n             logiana.sv\n             obj_dir/logiana\n             obj_dir/logiana.v\n             obj_dir/logiana.sv\n%Error: Exiting due to 1 error(s), 110 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module logiana_test;


	reg CLK24;
	reg OSC_CLK;
	reg EXT_CLK;
	reg [31:0] PROBE;
	
	reg H_nRD;
	reg H_nWR;
	reg H_MODE;
	reg ST_STP;


	wire [16:0] RAM_ADDR;
	wire RAM_nCE3;
	wire RAM_nOE;
	wire RAM_nGW;
	wire RAM_nADSC;
	wire RAM_CLK;
	wire RUNNING;
	wire [7:0] USER;
    wire CN1_40;
	

	reg [31:0] RAM_DATA_REG;
   wire [31:0] RAM_DATA;
	assign RAM_DATA = (RAM_nGW == 0 ? 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : RAM_DATA_REG);
	
	reg [7:0] H_DATA_REG;
	wire [7:0] H_DATA;
	assign H_DATA = (H_nWR == 0 ? H_DATA_REG : 8'bzzzzzzzz);




	logiana uut (
		.USER(USER),
        .CN1_40(CN1_40),
		.OSC_CLK(OSC_CLK), 
		.EXT_CLK(EXT_CLK), 
		.CLK24(CLK24),
		.PROBE(PROBE),
		.H_nRD(H_nRD),
		.H_nWR(H_nWR),
		.H_MODE(H_MODE),
		.H_DATA(H_DATA),
		.ST_STP(ST_STP), 
		.RAM_ADDR(RAM_ADDR),
		.RAM_DATA(RAM_DATA),
		.RAM_nCE3(RAM_nCE3), 
		.RAM_nOE(RAM_nOE), 
		.RAM_nGW(RAM_nGW), 
		.RAM_nADSC(RAM_nADSC), 
		.RAM_CLK(RAM_CLK),
		.RUNNING(RUNNING)
	);
	
	always #5 OSC_CLK = ~OSC_CLK;
	always #20 CLK24 = ~CLK24;

	initial begin

		OSC_CLK = 0;
		EXT_CLK = 0;
		CLK24 = 0;
		ST_STP = 0;
		H_nWR = 1;
		H_nRD = 1;
		H_MODE = 0;
		PROBE = 0;


		#100;
		ST_STP = 0;
		

		#50
		H_MODE = 0;
		H_DATA_REG = 8'h12;
		#10;
		H_nWR = 0;
		#10;
		H_nWR = 1;
		#10;

		
		#50;
		H_MODE = 1;		
		H_DATA_REG = 8'h00;
		#10;
		H_nWR = 0;
		#10;
		H_nWR = 1;

		#97;
		H_MODE = 0;		
		ST_STP = 1;

		#200;
		PROBE[0] = 1;
		
		#800;
		H_MODE = 1;
		#20;
		
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;


		
	end
      
endmodule
module logiana_test;



	reg CLK24;
	reg OSC_CLK;
	reg EXT_CLK;
	reg [31:0] PROBE;
	
	reg H_nRD;
	reg H_nWR;
	reg H_MODE;
	reg ST_STP;


	wire [16:0] RAM_ADDR;
	wire RAM_nCE3;
	wire RAM_nOE;
	wire RAM_nGW;
	wire RAM_nADSC;
	wire RAM_CLK;
	wire RUNNING;
	wire [7:0] USER;
    wire CN1_40;
	

	reg [31:0] RAM_DATA_REG;
   wire [31:0] RAM_DATA;
	assign RAM_DATA = (RAM_nGW == 0 ? 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : RAM_DATA_REG);
	
	reg [7:0] H_DATA_REG;
	wire [7:0] H_DATA;
	assign H_DATA = (H_nWR == 0 ? H_DATA_REG : 8'bzzzzzzzz);




	logiana uut (
		.USER(USER),
        .CN1_40(CN1_40),
		.OSC_CLK(OSC_CLK), 
		.EXT_CLK(EXT_CLK), 
		.CLK24(CLK24),
		.PROBE(PROBE),
		.H_nRD(H_nRD),
		.H_nWR(H_nWR),
		.H_MODE(H_MODE),
		.H_DATA(H_DATA),
		.ST_STP(ST_STP), 
		.RAM_ADDR(RAM_ADDR),
		.RAM_DATA(RAM_DATA),
		.RAM_nCE3(RAM_nCE3), 
		.RAM_nOE(RAM_nOE), 
		.RAM_nGW(RAM_nGW), 
		.RAM_nADSC(RAM_nADSC), 
		.RAM_CLK(RAM_CLK),
		.RUNNING(RUNNING)
	);
	
	always #5 OSC_CLK = ~OSC_CLK;
	always #20 CLK24 = ~CLK24;

	initial begin

		OSC_CLK = 0;
		EXT_CLK = 0;
		CLK24 = 0;
		ST_STP = 0;
		H_nWR = 1;
		H_nRD = 1;
		H_MODE = 0;
		PROBE = 0;


		#100;
		ST_STP = 0;
		

		#50
		H_MODE = 0;
		H_DATA_REG = 8'h12;
		#10;
		H_nWR = 0;
		#10;
		H_nWR = 1;
		#10;

		
		#50;
		H_MODE = 1;		
		H_DATA_REG = 8'h00;
		#10;
		H_nWR = 0;
		#10;
		H_nWR = 1;

		#97;
		H_MODE = 0;		
		ST_STP = 1;

		#200;
		PROBE[0] = 1;
		
		#800;
		H_MODE = 1;
		#20;
		
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;

		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;
		H_nRD = 0;
		#20;
		H_nRD = 1;
		#20;


		
	end
      
endmodule