data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_bscl1.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_bscl1.v:34: Cannot find file containing module: 'bw_u1_inv_2x'\nbw_u1_inv_2x up_inv2x (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_inv_2x.sv\n             bw_u1_inv_2x\n             bw_u1_inv_2x.v\n             bw_u1_inv_2x.sv\n             obj_dir/bw_u1_inv_2x\n             obj_dir/bw_u1_inv_2x.v\n             obj_dir/bw_u1_inv_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_bscl1.v:37: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x nand1 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_bscl1.v:41: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x nand2 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_bscl1.v:45: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x up_inv1x (\n^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module bw_io_dtl_bscl1(intest_oe ,intest_d ,q_dn_pad ,q25_dn_pad ,
     q_up_pad );
output		intest_oe ;
output		intest_d ;
input		q_dn_pad ;
input		q25_dn_pad ;
input		q_up_pad ;
 
wire		net016 ;
wire		n1 ;
 
 
bw_u1_inv_2x up_inv2x (
     .z               (intest_d ),
     .a               (net016 ) );
bw_u1_nand2_1x nand1 (
     .z               (n1 ),
     .a               (q_up_pad ),
     .b               (q25_dn_pad ) );
bw_u1_nand2_1x nand2 (
     .z               (intest_oe ),
     .a               (q_dn_pad ),
     .b               (n1 ) );
bw_u1_inv_1x up_inv1x (
     .z               (net016 ),
     .a               (q_up_pad ) );
endmodule
module bw_io_dtl_bscl1(intest_oe ,intest_d ,q_dn_pad ,q25_dn_pad ,
     q_up_pad );

output		intest_oe ;
output		intest_d ;
input		q_dn_pad ;
input		q25_dn_pad ;
input		q_up_pad ;
 
wire		net016 ;
wire		n1 ;
 
 
bw_u1_inv_2x up_inv2x (
     .z               (intest_d ),
     .a               (net016 ) );
bw_u1_nand2_1x nand1 (
     .z               (n1 ),
     .a               (q_up_pad ),
     .b               (q25_dn_pad ) );
bw_u1_nand2_1x nand2 (
     .z               (intest_oe ),
     .a               (q_dn_pad ),
     .b               (n1 ) );
bw_u1_inv_1x up_inv1x (
     .z               (net016 ),
     .a               (q_up_pad ) );
endmodule