data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v
1: b"%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v:74: Cannot find file containing module: 'ahb_to_ssram'\n   ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_to_ssram\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_to_ssram.v\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_to_ssram.sv\n             ahb_to_ssram\n             ahb_to_ssram.v\n             ahb_to_ssram.sv\n             obj_dir/ahb_to_ssram\n             obj_dir/ahb_to_ssram.v\n             obj_dir/ahb_to_ssram.sv\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v:142: Cannot find file containing module: 'sync_ram_wf'\n   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v:155: Cannot find file containing module: 'sync_ram_wf'\n   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v:166: Cannot find file containing module: 'sync_ram_wf'\n   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/chip.v:177: Cannot find file containing module: 'sync_ram_wf'\n   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))\n   ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module chip (

   HRDATA, HREADYOUT, HRESP,

   HADDR, HCLK, HREADY, HRESETn, HSEL, HSIZE, HTRANS, HWDATA, HWRITE
   );

   parameter AW = 12;



   input [AW-1:0]       HADDR;
   input                HCLK;
   input                HREADY;
   input                HRESETn;
   input                HSEL;
   input [2:0]          HSIZE;
   input [1:0]          HTRANS;
   input [31:0]         HWDATA;
   input                HWRITE;

   output [31:0]        HRDATA;
   output               HREADYOUT;
   output               HRESP;









   wire [AW-1:0]        ahb_sram_addr;
   wire [31:0]          ahb_sram_din;
   wire [3:0]           ahb_sram_enb;
   wire [3:0]           ahb_sram_wb;
   wire [31:0]          sram_ahb_dout;



   ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM
  (
   .ahb_sram_we                         (),
   .ahb_sram_en                         (),









   .HREADYOUT                           (HREADYOUT),
   .HRDATA                              (HRDATA[31:0]),
   .HRESP                               (HRESP),
   .ahb_sram_addr                       (ahb_sram_addr[AW-1:0]),
   .ahb_sram_enb                        (ahb_sram_enb[3:0]),
   .ahb_sram_wb                         (ahb_sram_wb[3:0]),
   .ahb_sram_din                        (ahb_sram_din[31:0]),

   .HCLK                                (HCLK),
   .HRESETn                             (HRESETn),
   .HSEL                                (HSEL),
   .HADDR                               (HADDR[AW-1:0]),
   .HTRANS                              (HTRANS[1:0]),
   .HSIZE                               (HSIZE[2:0]),
   .HWRITE                              (HWRITE),
   .HWDATA                              (HWDATA[31:0]),
   .HREADY                              (HREADY),
   .sram_ahb_dout                       (sram_ahb_dout[31:0]));



`ifdef USE_32BIT_RAM


   sync_ram_wf_x32 #(.ADDR_WIDTH(AW-2))
   U_RAM(

         .dout                          (sram_ahb_dout[31:0]),

         .clk                           (HCLK),
         .web                           (ahb_sram_wb[3:0]),
         .enb                           (ahb_sram_enb[3:0]),
         .addr                          (ahb_sram_addr[11:2]),
         .din                           (ahb_sram_din[31:0]));


`else


   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM0 (


           .dout                        (sram_ahb_dout[7:0]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[0]),
           .en                          (ahb_sram_enb[0]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[7:0]));


   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM1 (

           .dout                        (sram_ahb_dout[15:8]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[1]),
           .en                          (ahb_sram_enb[1]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[15:8]));

   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM2 (

           .dout                        (sram_ahb_dout[23:16]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[2]),
           .en                          (ahb_sram_enb[2]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[23:16]));

   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM3 (

           .dout                        (sram_ahb_dout[31:24]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[3]),
           .en                          (ahb_sram_enb[3]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[31:24]));



`endif



endmodule
module chip (

   HRDATA, HREADYOUT, HRESP,

   HADDR, HCLK, HREADY, HRESETn, HSEL, HSIZE, HTRANS, HWDATA, HWRITE
   );


   parameter AW = 12;



   input [AW-1:0]       HADDR;
   input                HCLK;
   input                HREADY;
   input                HRESETn;
   input                HSEL;
   input [2:0]          HSIZE;
   input [1:0]          HTRANS;
   input [31:0]         HWDATA;
   input                HWRITE;

   output [31:0]        HRDATA;
   output               HREADYOUT;
   output               HRESP;









   wire [AW-1:0]        ahb_sram_addr;
   wire [31:0]          ahb_sram_din;
   wire [3:0]           ahb_sram_enb;
   wire [3:0]           ahb_sram_wb;
   wire [31:0]          sram_ahb_dout;



   ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM
  (
   .ahb_sram_we                         (),
   .ahb_sram_en                         (),









   .HREADYOUT                           (HREADYOUT),
   .HRDATA                              (HRDATA[31:0]),
   .HRESP                               (HRESP),
   .ahb_sram_addr                       (ahb_sram_addr[AW-1:0]),
   .ahb_sram_enb                        (ahb_sram_enb[3:0]),
   .ahb_sram_wb                         (ahb_sram_wb[3:0]),
   .ahb_sram_din                        (ahb_sram_din[31:0]),

   .HCLK                                (HCLK),
   .HRESETn                             (HRESETn),
   .HSEL                                (HSEL),
   .HADDR                               (HADDR[AW-1:0]),
   .HTRANS                              (HTRANS[1:0]),
   .HSIZE                               (HSIZE[2:0]),
   .HWRITE                              (HWRITE),
   .HWDATA                              (HWDATA[31:0]),
   .HREADY                              (HREADY),
   .sram_ahb_dout                       (sram_ahb_dout[31:0]));



`ifdef USE_32BIT_RAM


   sync_ram_wf_x32 #(.ADDR_WIDTH(AW-2))
   U_RAM(

         .dout                          (sram_ahb_dout[31:0]),

         .clk                           (HCLK),
         .web                           (ahb_sram_wb[3:0]),
         .enb                           (ahb_sram_enb[3:0]),
         .addr                          (ahb_sram_addr[11:2]),
         .din                           (ahb_sram_din[31:0]));


`else


   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM0 (


           .dout                        (sram_ahb_dout[7:0]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[0]),
           .en                          (ahb_sram_enb[0]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[7:0]));


   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM1 (

           .dout                        (sram_ahb_dout[15:8]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[1]),
           .en                          (ahb_sram_enb[1]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[15:8]));

   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM2 (

           .dout                        (sram_ahb_dout[23:16]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[2]),
           .en                          (ahb_sram_enb[2]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[23:16]));

   sync_ram_wf #(.WORD_WIDTH(8),.ADDR_WIDTH(AW-2))
   U_RAM3 (

           .dout                        (sram_ahb_dout[31:24]),

           .clk                         (HCLK),
           .we                          (ahb_sram_wb[3]),
           .en                          (ahb_sram_enb[3]),
           .addr                        (ahb_sram_addr[11:2]),
           .din                         (ahb_sram_din[31:24]));



`endif



endmodule