data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module.v:23: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                    : ... In instance top_module\n        pos = i;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module (
    input [3:0] in,
    output reg [1:0] pos
);

  integer i;
  reg bitfound;
  always @(*) begin
    pos = 0;
    bitfound = 0;
    for (i = 0; i < 4; i = i + 1) begin
      if (in[i] && !bitfound) begin
        bitfound = 1'b1;
        pos = i;
      end
    end
  end

endmodule
module top_module (
    input [3:0] in,
    output reg [1:0] pos
);


  integer i;
  reg bitfound;
  always @(*) begin
    pos = 0;
    bitfound = 0;
    for (i = 0; i < 4; i = i + 1) begin
      if (in[i] && !bitfound) begin
        bitfound = 1'b1;
        pos = i;
      end
    end
  end

endmodule