data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:15: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:29: Unsupported: Ignoring delay on this delayed statement.\n        #2 rst_n = 0;\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:30: syntax error, unexpected \'@\'\n        @(posedge clk);  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:45: Unsupported: Ignoring delay on this delayed statement.\n        #2 rst_n = 1;\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:49: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:57: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:65: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:73: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:82: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:91: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:126: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:131: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:135: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:141: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:145: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:150: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:154: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab4/task5/tb_rtl_dot.sv:158: syntax error, unexpected \'@\'\n        slave_writedata = 32\'bx; @(negedge clk);\n                                 ^\n%Error: Exiting due to 15 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_dot();

    logic clk, rst_n, slave_waitrequest, slave_read, slave_write, err;
    logic [3:0] slave_address;
    logic [31:0] slave_readdata, slave_writedata;
    logic master_waitrequest, master_read, master_readdatavalid, master_write;
    logic [31:0] master_address, master_readdata, master_writedata;

    logic [63:0] mul;

    dot dut(.*);

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    `define IDLE    3'b000
    `define READ_W  3'b001
    `define WAIT_W  3'b010
    `define READ_V  3'b011
    `define WAIT_V  3'b100
    `define CALC    3'b101
    `define DONE    3'b110

    initial begin
        err = 1'b0;

        #2 rst_n = 0;
        @(posedge clk);
        @(negedge clk);
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b1) begin
            $display("ERROR 1: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b1, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.slave_readdata !== 32'b0) begin
            $display("ERROR 2: Expected slave_readdata is %d, actual slave_readdata is %d", 32'b0, tb_rtl_dot.dut.slave_readdata);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.state !== `IDLE) begin
            $display("ERROR 3: Expected state is %d, actual state is %d", `IDLE, tb_rtl_dot.dut.state);
            err = 1'b1;
        end

        #2 rst_n = 1;
        master_waitrequest = 1'bx;


        @(negedge clk);
        @(negedge clk);

        slave_write = 1;


        slave_address = 4'd2;
        slave_writedata = 32'h03;
        @(negedge clk);
        if (tb_rtl_dot.dut.weight_addr !== 32'h03) begin
            $display("ERROR 4: Expected weight_addr is %d, actual weight_addr is %d", 32'h03, tb_rtl_dot.dut.weight_addr);
            err = 1'b1;
        end

        slave_write = 0;
        slave_writedata = 32'bx;
        @(negedge clk);
        @(negedge clk);

        slave_write = 1;


        slave_address = 4'd3;
        slave_writedata = 32'h12;
        @(negedge clk);
        if (tb_rtl_dot.dut.vector_addr !== 32'h12) begin
            $display("ERROR 5: Expected vector_addr is %d, actual vector_addr is %d", 32'h12, tb_rtl_dot.dut.vector_addr);
            err = 1'b1;
        end


        slave_address = 4'd5;
        slave_writedata = 32'h3;
        @(negedge clk);
        if (tb_rtl_dot.dut.vector_length !== 32'h3) begin
            $display("ERROR 6: Expected vector_length is %d, actual vector_length is %d", 32'h3, tb_rtl_dot.dut.vector_length);
            err = 1'b1;
        end
        

        slave_address = 4'd0;
        slave_writedata = 32'haa;
        @(negedge clk);
        if (tb_rtl_dot.dut.start_dot !== 1'b1) begin
            $display("ERROR 7: Expected start_dot is %d, actual start_dot is %d", 1'b1, tb_rtl_dot.dut.start_dot);
            err = 1'b1;
        end

        slave_write = 0;
        slave_writedata = 32'bx;

        slave_read = 1;
        slave_address = 4'd0;
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b1) begin
            $display("ERROR 8: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b1, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end


        master_waitrequest = 1'b0;
        if (tb_rtl_dot.dut.state !== `READ_W) begin
            $display("ERROR 9: Expected state is %d, actual state is %d", `READ_W, tb_rtl_dot.dut.state);
            err = 1'b1;
        end













        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        master_readdata = 32'd102236;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = 32'd81265;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);

        master_readdata = 32'd65536;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = -163185;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        master_readdata = -370934;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = 122552;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);

        slave_write = 0;
        slave_writedata = 32'bx; @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        

        if (tb_rtl_dot.dut.slave_readdata !== -11) begin
            $display("ERROR 9: Expected slave_readdata is %d, actual slave_readdata is %d", -11, tb_rtl_dot.dut.slave_readdata);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b0) begin
            $display("ERROR 10: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b0, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_rtl_dot();


    logic clk, rst_n, slave_waitrequest, slave_read, slave_write, err;
    logic [3:0] slave_address;
    logic [31:0] slave_readdata, slave_writedata;
    logic master_waitrequest, master_read, master_readdatavalid, master_write;
    logic [31:0] master_address, master_readdata, master_writedata;

    logic [63:0] mul;

    dot dut(.*);

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    `define IDLE    3'b000
    `define READ_W  3'b001
    `define WAIT_W  3'b010
    `define READ_V  3'b011
    `define WAIT_V  3'b100
    `define CALC    3'b101
    `define DONE    3'b110

    initial begin
        err = 1'b0;

        #2 rst_n = 0;
        @(posedge clk);
        @(negedge clk);
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b1) begin
            $display("ERROR 1: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b1, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.slave_readdata !== 32'b0) begin
            $display("ERROR 2: Expected slave_readdata is %d, actual slave_readdata is %d", 32'b0, tb_rtl_dot.dut.slave_readdata);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.state !== `IDLE) begin
            $display("ERROR 3: Expected state is %d, actual state is %d", `IDLE, tb_rtl_dot.dut.state);
            err = 1'b1;
        end

        #2 rst_n = 1;
        master_waitrequest = 1'bx;


        @(negedge clk);
        @(negedge clk);

        slave_write = 1;


        slave_address = 4'd2;
        slave_writedata = 32'h03;
        @(negedge clk);
        if (tb_rtl_dot.dut.weight_addr !== 32'h03) begin
            $display("ERROR 4: Expected weight_addr is %d, actual weight_addr is %d", 32'h03, tb_rtl_dot.dut.weight_addr);
            err = 1'b1;
        end

        slave_write = 0;
        slave_writedata = 32'bx;
        @(negedge clk);
        @(negedge clk);

        slave_write = 1;


        slave_address = 4'd3;
        slave_writedata = 32'h12;
        @(negedge clk);
        if (tb_rtl_dot.dut.vector_addr !== 32'h12) begin
            $display("ERROR 5: Expected vector_addr is %d, actual vector_addr is %d", 32'h12, tb_rtl_dot.dut.vector_addr);
            err = 1'b1;
        end


        slave_address = 4'd5;
        slave_writedata = 32'h3;
        @(negedge clk);
        if (tb_rtl_dot.dut.vector_length !== 32'h3) begin
            $display("ERROR 6: Expected vector_length is %d, actual vector_length is %d", 32'h3, tb_rtl_dot.dut.vector_length);
            err = 1'b1;
        end
        

        slave_address = 4'd0;
        slave_writedata = 32'haa;
        @(negedge clk);
        if (tb_rtl_dot.dut.start_dot !== 1'b1) begin
            $display("ERROR 7: Expected start_dot is %d, actual start_dot is %d", 1'b1, tb_rtl_dot.dut.start_dot);
            err = 1'b1;
        end

        slave_write = 0;
        slave_writedata = 32'bx;

        slave_read = 1;
        slave_address = 4'd0;
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b1) begin
            $display("ERROR 8: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b1, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end


        master_waitrequest = 1'b0;
        if (tb_rtl_dot.dut.state !== `READ_W) begin
            $display("ERROR 9: Expected state is %d, actual state is %d", `READ_W, tb_rtl_dot.dut.state);
            err = 1'b1;
        end













        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        master_readdata = 32'd102236;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = 32'd81265;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);

        master_readdata = 32'd65536;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = -163185;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        master_readdata = -370934;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);
        master_readdata = 122552;
        master_readdatavalid = 1;
        @(negedge clk);
        @(negedge clk);

        slave_write = 0;
        slave_writedata = 32'bx; @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        

        if (tb_rtl_dot.dut.slave_readdata !== -11) begin
            $display("ERROR 9: Expected slave_readdata is %d, actual slave_readdata is %d", -11, tb_rtl_dot.dut.slave_readdata);
            err = 1'b1;
        end
        if (tb_rtl_dot.dut.slave_waitrequest !== 1'b0) begin
            $display("ERROR 10: Expected slave_waitrequest is %d, actual slave_waitrequest is %d", 1'b0, tb_rtl_dot.dut.slave_waitrequest);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule