data/full_repos/permissive/418819021/lab-01/task2/test_sram.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:34: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("waves.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:35: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test_sram);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-01/task2/test_sram.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_sram();

    reg       clk;
    reg       oe;
    reg       cs;
    reg       we;
    reg       reset;
    reg [6:0] address;
    reg [7:0] data_in;



    wire [7:0] data_out;



    sram single_memory_chip(
        .clk(clk),
        .reset(reset),
        .oe(oe),
        .cs(cs),
        .we(we),
        .address(address),
        .data_in(data_in),
        .data_out(data_out)
    );

    always #1 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, test_sram);


        clk = 0;
        reset = 1;
        we = 0;
        oe = 0;
        #2;

        cs = 1;
        reset = 0;
        address = 7'b0001000;
        we = 1;
        oe = 0;
        data_in = 8'b10000001;
        #2;

        we = 0;
        oe = 1;
        #2;

        address = 7'b0;
        #2;

        reset = 1;
        #1;
        reset = 0;
        #1;
        $finish();
    end
endmodule
module test_sram();


    reg       clk;
    reg       oe;
    reg       cs;
    reg       we;
    reg       reset;
    reg [6:0] address;
    reg [7:0] data_in;



    wire [7:0] data_out;



    sram single_memory_chip(
        .clk(clk),
        .reset(reset),
        .oe(oe),
        .cs(cs),
        .we(we),
        .address(address),
        .data_in(data_in),
        .data_out(data_out)
    );

    always #1 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, test_sram);


        clk = 0;
        reset = 1;
        we = 0;
        oe = 0;
        #2;

        cs = 1;
        reset = 0;
        address = 7'b0001000;
        we = 1;
        oe = 0;
        data_in = 8'b10000001;
        #2;

        we = 0;
        oe = 1;
        #2;

        address = 7'b0;
        #2;

        reset = 1;
        #1;
        reset = 0;
        #1;
        $finish();
    end
endmodule