data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:28: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ;\n                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:37: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:40: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench2.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:41: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench2);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench2.v:43: Unsupported or unknown PLI call: $monitor\n $monitor("Rn=%4h,Rm=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,SR=%3d,S=%3d,ALUSTORE=%3d",Rn,Rm,opcode,Out,FLAGS_OUT,SR,S,ALUSTORE);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench2;

parameter sim_time = 750*2;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

always@(IR or CU)
begin
	RSLCT = {CU,IR[15:8],IR[3:1], IR[19:16]};
end

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

reg S;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ; SR =0; IR = 0 ;
	#1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0; #1 IR[3:0] = 0; #1 IR[11:8] = 0; #1 IR[15:12] = 0;
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench2.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench2);
	$display(" Test Results" );
	$monitor("Rn=%4h,Rm=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,SR=%3d,S=%3d,ALUSTORE=%3d",Rn,Rm,opcode,Out,FLAGS_OUT,SR,S,ALUSTORE);
end

endmodule
module ARM_CU_ALU_TestBench2;


parameter sim_time = 750*2;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

always@(IR or CU)
begin
	RSLCT = {CU,IR[15:8],IR[3:1], IR[19:16]};
end

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

reg S;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ; SR =0; IR = 0 ;
	#1 MFC = 1;#1 Reset=0 ;#1  #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0; #1 IR[3:0] = 0; #1 IR[11:8] = 0; #1 IR[15:12] = 0;
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench2.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench2);
	$display(" Test Results" );
	$monitor("Rn=%4h,Rm=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,SR=%3d,S=%3d,ALUSTORE=%3d",Rn,Rm,opcode,Out,FLAGS_OUT,SR,S,ALUSTORE);
end

endmodule