data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v
1: b'%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:27: Unsupported: event data types\n   event reset_trigger;\n   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n     #OFFSET;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1\'b1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n         #(PERIOD*DUTY_CYCLE);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:48: syntax error, unexpected \'@\'\n        @ (reset_trigger);\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:51: syntax error, unexpected \'@\'\n        @ (posedge clk);\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:55: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:63: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:71: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:79: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:87: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:100: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("peripheral_div_TB.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:101: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(-1, uut);\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:103: syntax error, unexpected ->\n     #10 -> reset_trigger;\n         ^~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:103: Unsupported: Ignoring delay on this delayed statement.\n     #10 -> reset_trigger;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/divider/peripheral_div_TB.v:104: Unsupported: Ignoring delay on this delayed statement.\n     #((PERIOD*DUTY_CYCLE)*200) $finish;\n     ^\n%Error: Exiting due to 11 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module peripheral_div_TB;

  
   reg clk;
   reg rst;
   reg  reset;
   reg  start;
   reg [15:0]d_in;
   reg cs;
   reg [3:0]addr;
   reg rd;
   reg wr;
   wire [15:0]d_out;

   peripheral_div uut (.clk(clk) , .rst(rst) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );


   parameter PERIOD          = 20;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;
   reg [20:0] i;
   event reset_trigger;




   initial begin
      clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
   end

   initial  begin
     #OFFSET;
     forever
       begin
         clk = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
         #(PERIOD*DUTY_CYCLE);
       end
   end

   initial begin
      forever begin 
        @ (reset_trigger);
        @ (posedge clk);
        start = 0;
        @ (posedge clk);
        start = 1;

       for(i=0; i<2; i=i+1) begin
         @ (posedge clk);
       end
          start = 0;




       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0010;
	addr = 16'h6800;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0004;
	addr = 16'h6802;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0001;
	addr = 16'h6804;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0000;
	addr = 16'h6806;
	cs=1; rd=1; wr=0;


      end
   end
	 

   initial begin: TEST_CASE
     $dumpfile("peripheral_div_TB.vcd");
     $dumpvars(-1, uut);
	
     #10 -> reset_trigger;
     #((PERIOD*DUTY_CYCLE)*200) $finish;
   end

endmodule
module peripheral_div_TB;


  
   reg clk;
   reg rst;
   reg  reset;
   reg  start;
   reg [15:0]d_in;
   reg cs;
   reg [3:0]addr;
   reg rd;
   reg wr;
   wire [15:0]d_out;

   peripheral_div uut (.clk(clk) , .rst(rst) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );


   parameter PERIOD          = 20;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET          = 0;
   reg [20:0] i;
   event reset_trigger;




   initial begin
      clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
   end

   initial  begin
     #OFFSET;
     forever
       begin
         clk = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
         #(PERIOD*DUTY_CYCLE);
       end
   end

   initial begin
      forever begin 
        @ (reset_trigger);
        @ (posedge clk);
        start = 0;
        @ (posedge clk);
        start = 1;

       for(i=0; i<2; i=i+1) begin
         @ (posedge clk);
       end
          start = 0;




       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0010;
	addr = 16'h6800;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0004;
	addr = 16'h6802;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0001;
	addr = 16'h6804;
	cs=1; rd=0; wr=1;

       for(i=0; i<4; i=i+1) begin
         @ (posedge clk);
       end

	d_in = 16'd0000;
	addr = 16'h6806;
	cs=1; rd=1; wr=0;


      end
   end
	 

   initial begin: TEST_CASE
     $dumpfile("peripheral_div_TB.vcd");
     $dumpvars(-1, uut);
	
     #10 -> reset_trigger;
     #((PERIOD*DUTY_CYCLE)*200) $finish;
   end

endmodule