data/full_repos/permissive/455421905/src/fifo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/455421905/src/fifo.v:57: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'ONE_ENTRY_FIFO\'\nmodule ONE_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'DFIFO\'\nmodule DFIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~\n                                                                     : ... Top module \'BS_FIFO\'\nmodule BS_FIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~~~\n                                                                     : ... Top module \'RAM_LAYER_FIFO\'\nmodule RAM_LAYER_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'MULTI_CHANNEL_TWOENTRY_FIFO\'\nmodule MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:375: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.sv\n             BRAM\n             BRAM.v\n             BRAM.sv\n             obj_dir/BRAM\n             obj_dir/BRAM.v\n             obj_dir/BRAM.sv\n%Error: data/full_repos/permissive/455421905/src/fifo.v:127: Cannot find file containing module: \'BRAM\'\n  BRAM #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:332: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module BS_FIFO #(parameter                    FIFO_SIZE  =  4,
                 parameter                    FIFO_WIDTH = 32,
                 parameter                    USE_IPCORE = "INTEL")
                (input  wire                  CLK,
                 input  wire                  RST,
                 input  wire                  enq,
                 input  wire                  deq,
                 input  wire [FIFO_WIDTH-1:0] din,
                 output wire [FIFO_WIDTH-1:0] dot,
                 output wire                  emp,
                 output wire                  full,
                 output reg  [FIFO_SIZE:0]    cnt);

  wire                  ibuf_enq;
  wire                  ibuf_deq;
  wire [FIFO_WIDTH-1:0] ibuf_din;
  wire [FIFO_WIDTH-1:0] ibuf_dot;
  wire                  ibuf_emp;
  wire                  ibuf_ful;
  wire [FIFO_SIZE:0]    ibuf_cnt;

  wire                  obuf_enq;
  wire                  obuf_deq;
  wire [FIFO_WIDTH-1:0] obuf_din;
  wire [FIFO_WIDTH-1:0] obuf_dot;
  wire                  obuf_emp;
  wire                  obuf_ful;
  wire [3:0]            obuf_cnt;


  integer               p;
  reg  [2:0]            valid;

  assign ibuf_enq = enq;
  assign ibuf_deq = ~|{(obuf_cnt > 4), ibuf_emp};
  assign ibuf_din = din;

  assign obuf_enq = valid[2];
  assign obuf_deq = deq;
  assign obuf_din = ibuf_dot;

  always @(posedge CLK) begin
    if (RST) begin
      valid <= 0;
    end else begin
      valid[0] <= ibuf_deq;
      for (p=1; p<3; p=p+1) begin
        valid[p] <= valid[p-1];
      end
    end
  end

  always @(posedge CLK) begin
    if (RST) cnt <= 0;
    else begin
      case ({enq, deq})
        2'b01: cnt <= cnt - 1;
        2'b10: cnt <= cnt + 1;
      endcase
    end
  end

  BFIFO #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)
  ibuf(CLK, RST, ibuf_enq, ibuf_deq, ibuf_din,
       ibuf_dot, ibuf_emp, ibuf_ful, ibuf_cnt);

  SRL_FIFO #(3, FIFO_WIDTH)
  obuf(CLK, RST, obuf_enq, obuf_deq, obuf_din,
       obuf_dot, obuf_emp, obuf_ful, obuf_cnt);

  assign dot  = obuf_dot;
  assign emp  = obuf_emp;
  assign full = cnt[FIFO_SIZE];

endmodule
module BS_FIFO #(parameter                    FIFO_SIZE  =  4,
                 parameter                    FIFO_WIDTH = 32,
                 parameter                    USE_IPCORE = "INTEL")
                (input  wire                  CLK,
                 input  wire                  RST,
                 input  wire                  enq,
                 input  wire                  deq,
                 input  wire [FIFO_WIDTH-1:0] din,
                 output wire [FIFO_WIDTH-1:0] dot,
                 output wire                  emp,
                 output wire                  full,
                 output reg  [FIFO_SIZE:0]    cnt);


  wire                  ibuf_enq;
  wire                  ibuf_deq;
  wire [FIFO_WIDTH-1:0] ibuf_din;
  wire [FIFO_WIDTH-1:0] ibuf_dot;
  wire                  ibuf_emp;
  wire                  ibuf_ful;
  wire [FIFO_SIZE:0]    ibuf_cnt;

  wire                  obuf_enq;
  wire                  obuf_deq;
  wire [FIFO_WIDTH-1:0] obuf_din;
  wire [FIFO_WIDTH-1:0] obuf_dot;
  wire                  obuf_emp;
  wire                  obuf_ful;
  wire [3:0]            obuf_cnt;


  integer               p;
  reg  [2:0]            valid;

  assign ibuf_enq = enq;
  assign ibuf_deq = ~|{(obuf_cnt > 4), ibuf_emp};
  assign ibuf_din = din;

  assign obuf_enq = valid[2];
  assign obuf_deq = deq;
  assign obuf_din = ibuf_dot;

  always @(posedge CLK) begin
    if (RST) begin
      valid <= 0;
    end else begin
      valid[0] <= ibuf_deq;
      for (p=1; p<3; p=p+1) begin
        valid[p] <= valid[p-1];
      end
    end
  end

  always @(posedge CLK) begin
    if (RST) cnt <= 0;
    else begin
      case ({enq, deq})
        2'b01: cnt <= cnt - 1;
        2'b10: cnt <= cnt + 1;
      endcase
    end
  end

  BFIFO #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)
  ibuf(CLK, RST, ibuf_enq, ibuf_deq, ibuf_din,
       ibuf_dot, ibuf_emp, ibuf_ful, ibuf_cnt);

  SRL_FIFO #(3, FIFO_WIDTH)
  obuf(CLK, RST, obuf_enq, obuf_deq, obuf_din,
       obuf_dot, obuf_emp, obuf_ful, obuf_cnt);

  assign dot  = obuf_dot;
  assign emp  = obuf_emp;
  assign full = cnt[FIFO_SIZE];

endmodule