data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk_i <= ~clk_i;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:74: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:74: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:75: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:75: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:76: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:76: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:90: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:90: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:100: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:100: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:110: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:110: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:124: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:124: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:138: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:138: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:148: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:148: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:158: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:158: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:182: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:182: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:183: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:183: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:186: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:186: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:187: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:187: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:190: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:190: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:191: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:191: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:194: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:194: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:195: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:195: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:198: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:198: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:199: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:199: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:202: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:202: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:203: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:203: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:206: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:206: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:207: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:207: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:210: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n  ^~~~\n%Error: data/full_repos/permissive/51711917/cores/VRAM16K/bench/verilog/TEST_VRAM16K.v:210: Unsupported: wait statements\n  wait(clk_i); wait(~clk_i);\n               ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module TEST_VRAM16K();
	reg [15:0] story;


	
	reg clk_i;
	

	
	wire				a_ack_i;
	reg	[13:1]	a_adr_o;
	reg				a_cyc_o;
	wire	[15:0]	a_dat_i;
	reg	[15:0]	a_dat_o;
	reg	[1:0]		a_sel_o;
	reg				a_stb_o;
	reg				a_we_o;


	
	wire				b_ack_i;
	reg	[13:1]	b_adr_o;
	reg				b_cyc_o;
	wire	[15:0]	b_dat_i;
	reg	[15:0]	b_dat_o;
	reg	[1:0]		b_sel_o;
	reg				b_stb_o;
	reg				b_we_o;

	VRAM16K vram(
		.CLK_I(clk_i),
		
		.A_ACK_O(a_ack_i),
		.A_ADR_I(a_adr_o),
		.A_CYC_I(a_cyc_o),
		.A_DAT_O(a_dat_i),
		.A_DAT_I(a_dat_o),
		.A_SEL_I(a_sel_o),
		.A_STB_I(a_stb_o),
		.A_WE_I(a_we_o),

		.B_ACK_O(b_ack_i),
		.B_ADR_I(b_adr_o),
		.B_CYC_I(b_cyc_o),
		.B_DAT_O(b_dat_i),
		.B_DAT_I(b_dat_o),
		.B_SEL_I(b_sel_o),
		.B_STB_I(b_stb_o),
		.B_WE_I(b_we_o)
	);

	always begin
		#10 clk_i <= ~clk_i;
	end

	initial begin
		clk_i <= 1;
		a_stb_o <= 0;  b_stb_o <= 0;
		a_cyc_o <= 0;  b_cyc_o <= 0;
		











		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		story <= 16'h0000;
		a_adr_o <= 13'h0000;
		a_cyc_o <= 1;
		a_sel_o <= 2'b11;
		a_stb_o <= 1;
		a_we_o <= 0;
		
		b_adr_o <= 16'h0000;
		b_cyc_o <= 0;
		b_sel_o <= 2'b00;
		b_stb_o <= 0;
		b_we_o <= 0;
		
		wait(clk_i); wait(~clk_i);

		if(~a_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and has updated its data pins."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(a_ack_i) begin
			$display("Previous cycle terminated by ACK; new address not latched yet."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?!"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(~a_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and has updated its data pins."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?"); $stop;
		end





		wait(clk_i); wait(~clk_i);
		story <= 16'h0001;
		b_adr_o <= 13'h00FF;
		b_cyc_o <= 1;
		b_sel_o <= 2'b11;
		b_stb_o <= 1;
		b_we_o <= 0;
		
		a_adr_o <= 13'h0000;
		a_cyc_o <= 0;
		a_sel_o <= 2'b00;
		a_stb_o <= 0;
		a_we_o <= 0;
		
		wait(clk_i); wait(~clk_i);

		if(~b_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and is presenting data."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(b_ack_i) begin
			$display("Wait-state.  We don't pipeline."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?!"); $stop;
		end
		
		wait(clk_i); wait(~clk_i);

		if(~b_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and is presenting data."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?"); $stop;
		end

		b_cyc_o <= 0;
		b_stb_o <= 0;
		



		
		story <= 16'h0003;
		a_adr_o <= 13'h0000;
		a_cyc_o <= 1;
		a_stb_o <= 1;
		a_we_o <= 1;
		a_sel_o <= 2'b11;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0002;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0800;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0802;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1000;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1002;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1800;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1802;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_stb_o <= 0;
		b_adr_o <= 13'h0000;
		b_cyc_o <= 1;
		b_stb_o <= 1;
		b_we_o <= 0;
		b_sel_o <= 2'b11;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0002;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0800;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0802;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1000;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1002;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1800;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1802;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);




		
		story <= 16'hFFFF;
		$stop;
	end
endmodule
module TEST_VRAM16K();

	reg [15:0] story;


	
	reg clk_i;
	

	
	wire				a_ack_i;
	reg	[13:1]	a_adr_o;
	reg				a_cyc_o;
	wire	[15:0]	a_dat_i;
	reg	[15:0]	a_dat_o;
	reg	[1:0]		a_sel_o;
	reg				a_stb_o;
	reg				a_we_o;


	
	wire				b_ack_i;
	reg	[13:1]	b_adr_o;
	reg				b_cyc_o;
	wire	[15:0]	b_dat_i;
	reg	[15:0]	b_dat_o;
	reg	[1:0]		b_sel_o;
	reg				b_stb_o;
	reg				b_we_o;

	VRAM16K vram(
		.CLK_I(clk_i),
		
		.A_ACK_O(a_ack_i),
		.A_ADR_I(a_adr_o),
		.A_CYC_I(a_cyc_o),
		.A_DAT_O(a_dat_i),
		.A_DAT_I(a_dat_o),
		.A_SEL_I(a_sel_o),
		.A_STB_I(a_stb_o),
		.A_WE_I(a_we_o),

		.B_ACK_O(b_ack_i),
		.B_ADR_I(b_adr_o),
		.B_CYC_I(b_cyc_o),
		.B_DAT_O(b_dat_i),
		.B_DAT_I(b_dat_o),
		.B_SEL_I(b_sel_o),
		.B_STB_I(b_stb_o),
		.B_WE_I(b_we_o)
	);

	always begin
		#10 clk_i <= ~clk_i;
	end

	initial begin
		clk_i <= 1;
		a_stb_o <= 0;  b_stb_o <= 0;
		a_cyc_o <= 0;  b_cyc_o <= 0;
		











		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		story <= 16'h0000;
		a_adr_o <= 13'h0000;
		a_cyc_o <= 1;
		a_sel_o <= 2'b11;
		a_stb_o <= 1;
		a_we_o <= 0;
		
		b_adr_o <= 16'h0000;
		b_cyc_o <= 0;
		b_sel_o <= 2'b00;
		b_stb_o <= 0;
		b_we_o <= 0;
		
		wait(clk_i); wait(~clk_i);

		if(~a_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and has updated its data pins."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(a_ack_i) begin
			$display("Previous cycle terminated by ACK; new address not latched yet."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?!"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(~a_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and has updated its data pins."); $stop;
		end

		if(b_ack_i) begin
			$display("What is B bus doing?"); $stop;
		end





		wait(clk_i); wait(~clk_i);
		story <= 16'h0001;
		b_adr_o <= 13'h00FF;
		b_cyc_o <= 1;
		b_sel_o <= 2'b11;
		b_stb_o <= 1;
		b_we_o <= 0;
		
		a_adr_o <= 13'h0000;
		a_cyc_o <= 0;
		a_sel_o <= 2'b00;
		a_stb_o <= 0;
		a_we_o <= 0;
		
		wait(clk_i); wait(~clk_i);

		if(~b_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and is presenting data."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?"); $stop;
		end

		wait(clk_i); wait(~clk_i);

		if(b_ack_i) begin
			$display("Wait-state.  We don't pipeline."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?!"); $stop;
		end
		
		wait(clk_i); wait(~clk_i);

		if(~b_ack_i) begin
			$display("Expecting an ACK now.  RAM just now got the address, and is presenting data."); $stop;
		end

		if(a_ack_i) begin
			$display("What is A bus doing?"); $stop;
		end

		b_cyc_o <= 0;
		b_stb_o <= 0;
		



		
		story <= 16'h0003;
		a_adr_o <= 13'h0000;
		a_cyc_o <= 1;
		a_stb_o <= 1;
		a_we_o <= 1;
		a_sel_o <= 2'b11;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0002;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0800;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h0802;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1000;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1002;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1800;
		a_dat_o <= 16'hFFFF;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_adr_o <= 13'h1802;
		a_dat_o <= 16'hAAAA;
		wait(clk_i); wait(~clk_i);
		wait(clk_i); wait(~clk_i);
		a_stb_o <= 0;
		b_adr_o <= 13'h0000;
		b_cyc_o <= 1;
		b_stb_o <= 1;
		b_we_o <= 0;
		b_sel_o <= 2'b11;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0002;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0800;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h0802;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1000;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1002;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1800;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hFFFF) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);
		b_adr_o <= 13'h1802;
		wait(clk_i); wait(~clk_i);
		if(b_dat_i != 16'hAAAA) begin
			$display("Expected pixels to display at $0000"); $stop;
		end
		wait(clk_i); wait(~clk_i);




		
		story <= 16'hFFFF;
		$stop;
	end
endmodule