data/full_repos/permissive/42434302/ivltests/pr1861212a.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr1861212a.v:2: syntax error, unexpected real, expecting IDENTIFIER or \'=\' or do or final\n  reg real vo;\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1861212a.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #1000 vo = 4.5776;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1861212a.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #1000 vo = -4;\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module top2;
  reg real vo;

  initial begin
    vo = 3.3;
    #1000 vo = 4.5776;
    #1000 vo = -4;
  end

  always @(vo)
    $display("Real value is %f at %g", vo, $time);
endmodule
module top2;

  reg real vo;

  initial begin
    vo = 3.3;
    #1000 vo = 4.5776;
    #1000 vo = -4;
  end

  always @(vo)
    $display("Real value is %f at %g", vo, $time);
endmodule