data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_full_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_full_adder.v:24: Unsupported: Ignoring delay on this delayed statement.\n repeat (7) #10 D = D + 3\'b001;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_full_adder.v:29: Unsupported or unknown PLI call: $monitor\n $monitor("x = %d y = %d z = %d S = %d C = %d", D[2], D[1], D[0], S, C);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_full_adder ;

reg [2:0] D;
wire S, C;

full_adder DUT  ( .S(S),
				.C(C),
				.x(D[2]),
				.y(D[1]),
				.c(D[0]));

initial begin

	D = 3'b000;
	repeat (7) #10 D = D + 3'b001;

end

initial 
	$monitor("x = %d y = %d z = %d S = %d C = %d", D[2], D[1], D[0], S, C);

endmodule
module t_full_adder ;


reg [2:0] D;
wire S, C;

full_adder DUT  ( .S(S),
				.C(C),
				.x(D[2]),
				.y(D[1]),
				.c(D[0]));

initial begin

	D = 3'b000;
	repeat (7) #10 D = D + 3'b001;

end

initial 
	$monitor("x = %d y = %d z = %d S = %d C = %d", D[2], D[1], D[0], S, C);

endmodule