data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_sctag_3inv.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_sctag_3inv.v:33: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x xcmp_sctag (\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_192x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_192x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_192x.sv\n             bw_clk_gclk_inv_192x\n             bw_clk_gclk_inv_192x.v\n             bw_clk_gclk_inv_192x.sv\n             obj_dir/bw_clk_gclk_inv_192x\n             obj_dir/bw_clk_gclk_inv_192x.v\n             obj_dir/bw_clk_gclk_inv_192x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_sctag_3inv.v:36: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x xddr_sctag (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_sctag_3inv.v:39: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x xjbus_sctag (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bw_clk_gclk_sctag_3inv(jbus_out ,ddr_out ,cmp_out ,jbus_in ,
     ddr_in ,cmp_in );
output		jbus_out ;
output		ddr_out ;
output		cmp_out ;
input		jbus_in ;
input		ddr_in ;
input		cmp_in ;
 
 
 
bw_clk_gclk_inv_192x xcmp_sctag (
     .clkout          (cmp_out ),
     .clkin           (cmp_in ) );
bw_clk_gclk_inv_192x xddr_sctag (
     .clkout          (ddr_out ),
     .clkin           (ddr_in ) );
bw_clk_gclk_inv_192x xjbus_sctag (
     .clkout          (jbus_out ),
     .clkin           (jbus_in ) );
endmodule
module bw_clk_gclk_sctag_3inv(jbus_out ,ddr_out ,cmp_out ,jbus_in ,
     ddr_in ,cmp_in );

output		jbus_out ;
output		ddr_out ;
output		cmp_out ;
input		jbus_in ;
input		ddr_in ;
input		cmp_in ;
 
 
 
bw_clk_gclk_inv_192x xcmp_sctag (
     .clkout          (cmp_out ),
     .clkin           (cmp_in ) );
bw_clk_gclk_inv_192x xddr_sctag (
     .clkout          (ddr_out ),
     .clkin           (ddr_in ) );
bw_clk_gclk_inv_192x xjbus_sctag (
     .clkout          (jbus_out ),
     .clkin           (jbus_in ) );
endmodule