data/full_repos/permissive/425573648/fpga/seven_segment_negative.v
data/verilator_xmls/b5e05bba-0d4a-4843-b2f3-d83a42ca444e.xml
module seven_segment_negative(i,o);

input i;
output reg [6:0]o;

always @(*)
begin
if (i == 1'b1)
		o = 7'b1111110;
	else
		o = 7'b1111111;
end
endmodule
module seven_segment_negative(i,o);


input i;
output reg [6:0]o;

always @(*)
begin
if (i == 1'b1)
		o = 7'b1111110;
	else
		o = 7'b1111111;
end
endmodule