data/full_repos/permissive/426864978/lab1/task4/reg4.sv
data/verilator_xmls/6b948469-d19f-4eba-b27f-f0607d0acc4d.xml
module reg4(input clock, input load, input resetb, input[3:0] in, output reg[3:0] out);
    always @(posedge clock) begin
        if (!resetb) out <= 4'b0;
        else if (load) out <= in;
    end
endmodule
module reg4(input clock, input load, input resetb, input[3:0] in, output reg[3:0] out);

    always @(posedge clock) begin
        if (!resetb) out <= 4'b0;
        else if (load) out <= in;
    end
endmodule