data/full_repos/permissive/436575447/v2/inv_shift_row.v
data/verilator_xmls/baa6ee4e-a332-4707-832a-10693595354f.xml
module inv_shift_row(
	input [127:0] inputData,
	input startTransition,
	output reg [127:0] outputData
);
reg [31:0] word1,word2,word3,word4,word1s,word2s,word3s,word4s;


always @(posedge startTransition) begin 

word1=inputData[127:96];
word2=inputData[95:64];
word3=inputData[63:32];
word4=inputData[31:0];

word1s={word1[31:24],word4[23:16],word3[15:8],word2[7:0]};
word2s={word2[31:24],word1[23:16],word4[15:8],word3[7:0]};
word3s={word3[31:24],word2[23:16],word1[15:8],word4[7:0]};
word4s={word4[31:24],word3[23:16],word2[15:8],word1[7:0]};


outputData={word1s,word2s,word3s,word4s};

end		  
endmodule
module inv_shift_row(
	input [127:0] inputData,
	input startTransition,
	output reg [127:0] outputData
);

reg [31:0] word1,word2,word3,word4,word1s,word2s,word3s,word4s;


always @(posedge startTransition) begin 

word1=inputData[127:96];
word2=inputData[95:64];
word3=inputData[63:32];
word4=inputData[31:0];

word1s={word1[31:24],word4[23:16],word3[15:8],word2[7:0]};
word2s={word2[31:24],word1[23:16],word4[15:8],word3[7:0]};
word3s={word3[31:24],word2[23:16],word1[15:8],word4[7:0]};
word4s={word4[31:24],word3[23:16],word2[15:8],word1[7:0]};


outputData={word1s,word2s,word3s,word4s};

end		  
endmodule