data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #6\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n                #2\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n                #4\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n            #2\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n            #4\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:201: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("rgb_sbit2wrd_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:202: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, rgb_sbit2wrd_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n        #(DURATION)\n        ^\n%Error: Exiting due to 2 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rgb_sbit2wrd_tb();


    wire [31:0] rgb_wr_word;
    wire        rgb_wr_strobe;
    wire        rgb_wr_fifo_overflow;


    reg             clk = 1'b0;
    reg             rst = 1'b0;
    reg             rgb_sbit_strobe = 1'b0;
    reg             rgb_sbit_value = 1'b0;
    reg             rgb_sbit_stream_reset = 1'b0;
    reg             rgb_wr_fifo_full = 1'b0;

    reg             bit_first  = 1'b1;
    reg             bit_second = 1'b0;
    reg  [5:0]      where_am_i = 6'd0;


    integer                     i = 0;
    integer                     j = 0;


    localparam DURATION = 25000;
    localparam STREAM_RESET_CLKS = 4800;
    localparam COUNTER_MAX = STREAM_RESET_CLKS+200;
    localparam SAMPLE_TIME_CLKS = 57;


    always begin
        #1
        clk = ~clk;
    end
    

    rgb_sbit2wrduut (

        .clk(clk),
        .rst(rst),
        .in_strobe(rgb_sbit_strobe),
        .in_sbit_value(rgb_sbit_value),
        .in_stream_reset(rgb_sbit_stream_reset),
        .in_wr_fifo_full(rgb_wr_fifo_full),

        .out_word(rgb_wr_word),
        .out_strobe(rgb_wr_strobe),
        .out_wr_fifo_overflow(rgb_wr_fifo_overflow)
    );


    initial begin
    

        #10
        rst = 1'b1;
        #5
        rst = 1'b0;
        

        #100
        where_am_i = 6'd1;
        

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b0;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #6
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b0;
        #8
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        #2
        where_am_i = 6'd2;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        for (j = 0; j < 4; j = j + 1) begin
            if (3 == j) rgb_wr_fifo_full = 1'b1;
            for (i = 0; i < 24; i = i + 1) begin
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
            end
            rgb_wr_fifo_full = 1'b0;
        end
        

        #2
        where_am_i = where_am_i + 6'd1;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_first;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        

        #2
        where_am_i = where_am_i + 6'd1;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_second;
        rgb_sbit_stream_reset = 1'b0;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        where_am_i = where_am_i + 6'd1;
        for (i = 0; i < 23; i = i + 1) begin
            #2
            rgb_sbit_strobe = 1'b1;
            rgb_sbit_value = bit_first;
            rgb_sbit_stream_reset = 1'b0;
            #4
            rgb_sbit_strobe = 1'b0;
            rgb_sbit_value = 1'b0;
            rgb_sbit_stream_reset = 1'b0;
            bit_first = ~bit_first;
        end
        #2
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_first;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        where_am_i = where_am_i + 6'd1;
        
        #100
        bit_first = ~bit_first;
        where_am_i = where_am_i + 6'd1;



    end
    

    initial begin
    

        $dumpfile("rgb_sbit2wrd_tb.vcd");
        $dumpvars(0, rgb_sbit2wrd_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end
    
endmodule
module rgb_sbit2wrd_tb();



    wire [31:0] rgb_wr_word;
    wire        rgb_wr_strobe;
    wire        rgb_wr_fifo_overflow;


    reg             clk = 1'b0;
    reg             rst = 1'b0;
    reg             rgb_sbit_strobe = 1'b0;
    reg             rgb_sbit_value = 1'b0;
    reg             rgb_sbit_stream_reset = 1'b0;
    reg             rgb_wr_fifo_full = 1'b0;

    reg             bit_first  = 1'b1;
    reg             bit_second = 1'b0;
    reg  [5:0]      where_am_i = 6'd0;


    integer                     i = 0;
    integer                     j = 0;


    localparam DURATION = 25000;
    localparam STREAM_RESET_CLKS = 4800;
    localparam COUNTER_MAX = STREAM_RESET_CLKS+200;
    localparam SAMPLE_TIME_CLKS = 57;


    always begin
        #1
        clk = ~clk;
    end
    

    rgb_sbit2wrduut (

        .clk(clk),
        .rst(rst),
        .in_strobe(rgb_sbit_strobe),
        .in_sbit_value(rgb_sbit_value),
        .in_stream_reset(rgb_sbit_stream_reset),
        .in_wr_fifo_full(rgb_wr_fifo_full),

        .out_word(rgb_wr_word),
        .out_strobe(rgb_wr_strobe),
        .out_wr_fifo_overflow(rgb_wr_fifo_overflow)
    );


    initial begin
    

        #10
        rst = 1'b1;
        #5
        rst = 1'b0;
        

        #100
        where_am_i = 6'd1;
        

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b0;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #6
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2

        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b0;
        #8
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        #2
        where_am_i = 6'd2;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        for (j = 0; j < 4; j = j + 1) begin
            if (3 == j) rgb_wr_fifo_full = 1'b1;
            for (i = 0; i < 24; i = i + 1) begin
                #2
                where_am_i = where_am_i + 6'd1;
                rgb_sbit_strobe = 1'b1;
                rgb_sbit_value = bit_first;
                rgb_sbit_stream_reset = 1'b0;
                #4
                rgb_sbit_strobe = 1'b0;
                rgb_sbit_value = 1'b0;
                rgb_sbit_stream_reset = 1'b0;
            end
            rgb_wr_fifo_full = 1'b0;
        end
        

        #2
        where_am_i = where_am_i + 6'd1;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_first;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        

        #2
        where_am_i = where_am_i + 6'd1;
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_second;
        rgb_sbit_stream_reset = 1'b0;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        #2
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = 1'b1;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;


        where_am_i = where_am_i + 6'd1;
        for (i = 0; i < 23; i = i + 1) begin
            #2
            rgb_sbit_strobe = 1'b1;
            rgb_sbit_value = bit_first;
            rgb_sbit_stream_reset = 1'b0;
            #4
            rgb_sbit_strobe = 1'b0;
            rgb_sbit_value = 1'b0;
            rgb_sbit_stream_reset = 1'b0;
            bit_first = ~bit_first;
        end
        #2
        rgb_sbit_strobe = 1'b1;
        rgb_sbit_value = bit_first;
        rgb_sbit_stream_reset = 1'b1;
        #4
        rgb_sbit_strobe = 1'b0;
        rgb_sbit_value = 1'b0;
        rgb_sbit_stream_reset = 1'b0;
        where_am_i = where_am_i + 6'd1;
        
        #100
        bit_first = ~bit_first;
        where_am_i = where_am_i + 6'd1;



    end
    

    initial begin
    

        $dumpfile("rgb_sbit2wrd_tb.vcd");
        $dumpvars(0, rgb_sbit2wrd_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end
    
endmodule