data/full_repos/permissive/510938582/rtl/dr.v
data/verilator_xmls/4b627ada-139f-443f-8471-76a66bc59435.xml
module dr(din, clk,rst, drload, dout);
input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or negedge rst)
	if(!rst)
	dout<=0;
	else if(drload)
	dout<=din;

endmodule
module dr(din, clk,rst, drload, dout);

input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or negedge rst)
	if(!rst)
	dout<=0;
	else if(drload)
	dout<=din;

endmodule