data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/INCORRECT/bm_DL_D_latch.v
data/verilator_xmls/7f67d845-1ab3-41c2-b8b6-f1c28a632e15.xml
module bm_DL_D_latch(D, Clk, Q);
	input D, Clk;
	output Q;
	reg Q;
	
	always @(D or Clk)
		if (Clk)
			Q = D;
endmodule
module bm_DL_D_latch(D, Clk, Q);

	input D, Clk;
	output Q;
	reg Q;
	
	always @(D or Clk)
		if (Clk)
			Q = D;
endmodule