data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v
data/verilator_xmls/329679cb-8bc6-4a3e-8aaf-fb6ed72ebecf.xml
module d_latch_gates(d,clk,q,q_bar);
input d,clk;
output q, q_bar;

wire n1,n2,n3;

not (n1,d);

nand (n2,d,clk);
nand (n3,n1,clk);

nand (q,q_bar,n2);
nand (q_bar,q,n3);

endmodule
module d_latch_gates(d,clk,q,q_bar);

input d,clk;
output q, q_bar;

wire n1,n2,n3;

not (n1,d);

nand (n2,d,clk);
nand (n3,n1,clk);

nand (q,q_bar,n2);
nand (q_bar,q,n3);

endmodule