data/full_repos/permissive/492140037/OJ/dmemory32.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/492140037/OJ/dmemory32.v:13: Signal definition not found, creating implicitly: \'clk\'\n                                                                         : ... Suggested alternative: \'clock\'\n    assign clk = !clock;\n           ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492140037/OJ/dmemory32.v:15: Cannot find file containing module: \'RAM\'\n    RAM ram(.clka(clk), .wea(memWrite), .addra(address[15:2]), .dina(writeData), .douta(readData));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/RAM\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/RAM.v\n             data/full_repos/permissive/492140037/OJ,data/full_repos/permissive/492140037/RAM.sv\n             RAM\n             RAM.v\n             RAM.sv\n             obj_dir/RAM\n             obj_dir/RAM.v\n             obj_dir/RAM.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module dmemory32(clock,memWrite,address,writeData,readData);

    input clock, memWrite;

    input [31:0] address;

    input [31:0] writeData;

    output[31:0] readData;

    assign clk = !clock;

    RAM ram(.clka(clk), .wea(memWrite), .addra(address[15:2]), .dina(writeData), .douta(readData));

endmodule
module dmemory32(clock,memWrite,address,writeData,readData);


    input clock, memWrite;

    input [31:0] address;

    input [31:0] writeData;

    output[31:0] readData;

    assign clk = !clock;

    RAM ram(.clka(clk), .wea(memWrite), .addra(address[15:2]), .dina(writeData), .douta(readData));

endmodule