data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v:45: Cannot find include file: ../regmap/power_regs_regmap_utils.vh\n  `include "../regmap/power_regs_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/power_regs_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/power_regs_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/power_regs_regmap_utils.vh.sv\n             ../regmap/power_regs_regmap_utils.vh\n             ../regmap/power_regs_regmap_utils.vh.v\n             ../regmap/power_regs_regmap_utils.vh.sv\n             obj_dir/../regmap/power_regs_regmap_utils.vh\n             obj_dir/../regmap/power_regs_regmap_utils.vh.v\n             obj_dir/../regmap/power_regs_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/power_regs.v:46: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module power_regs #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  output wire        enable_tx_7v0,
  output wire        enable_rx_7v0,
  output wire        enable_3v3,


  input  wire        p7v_pg_b,
  input  wire        p7v_pg_a,


  output reg         pll_ref_clk_enable = 1'b0
);

  `include "../regmap/power_regs_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg    enable_3v3_reg = {ENABLE_3V3_SIZE    {1'b0}};
  reg enable_rx_7v0_reg = {ENABLE_RX_7V0_SIZE {1'b0}};
  reg enable_tx_7v0_reg = {ENABLE_TX_7V0_SIZE {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

      enable_3v3_reg          <= {ENABLE_3V3_SIZE    {1'b0}};
      enable_rx_7v0_reg       <= {ENABLE_RX_7V0_SIZE {1'b0}};
      enable_tx_7v0_reg       <= {ENABLE_TX_7V0_SIZE {1'b0}};

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RF_POWER_CONTROL: begin
            enable_3v3_reg    <= s_ctrlport_req_data[ENABLE_3V3];
            enable_rx_7v0_reg <= s_ctrlport_req_data[ENABLE_RX_7V0];
            enable_tx_7v0_reg <= s_ctrlport_req_data[ENABLE_TX_7V0];
          end

          BASE_ADDRESS + PRC_CONTROL: begin
            pll_ref_clk_enable <= s_ctrlport_req_data[PLL_REF_CLOCK_ENABLE];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RF_POWER_CONTROL: begin
            s_ctrlport_resp_data[ENABLE_3V3]    <= enable_3v3_reg;
            s_ctrlport_resp_data[ENABLE_RX_7V0] <= enable_rx_7v0_reg;
            s_ctrlport_resp_data[ENABLE_TX_7V0] <= enable_tx_7v0_reg;
          end

          BASE_ADDRESS + RF_POWER_STATUS: begin
            s_ctrlport_resp_data[P7V_A_STATUS] <= p7v_pg_a;
            s_ctrlport_resp_data[P7V_B_STATUS] <= p7v_pg_b;
          end

          BASE_ADDRESS + PRC_CONTROL: begin
            s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLE] <= pll_ref_clk_enable;
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end

  assign enable_tx_7v0 = enable_tx_7v0_reg;
  assign enable_rx_7v0 = enable_rx_7v0_reg;
  assign enable_3v3    = enable_3v3_reg;

endmodule
module power_regs #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  output wire        enable_tx_7v0,
  output wire        enable_rx_7v0,
  output wire        enable_3v3,


  input  wire        p7v_pg_b,
  input  wire        p7v_pg_a,


  output reg         pll_ref_clk_enable = 1'b0
);


  `include "../regmap/power_regs_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg    enable_3v3_reg = {ENABLE_3V3_SIZE    {1'b0}};
  reg enable_rx_7v0_reg = {ENABLE_RX_7V0_SIZE {1'b0}};
  reg enable_tx_7v0_reg = {ENABLE_TX_7V0_SIZE {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

      enable_3v3_reg          <= {ENABLE_3V3_SIZE    {1'b0}};
      enable_rx_7v0_reg       <= {ENABLE_RX_7V0_SIZE {1'b0}};
      enable_tx_7v0_reg       <= {ENABLE_TX_7V0_SIZE {1'b0}};

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RF_POWER_CONTROL: begin
            enable_3v3_reg    <= s_ctrlport_req_data[ENABLE_3V3];
            enable_rx_7v0_reg <= s_ctrlport_req_data[ENABLE_RX_7V0];
            enable_tx_7v0_reg <= s_ctrlport_req_data[ENABLE_TX_7V0];
          end

          BASE_ADDRESS + PRC_CONTROL: begin
            pll_ref_clk_enable <= s_ctrlport_req_data[PLL_REF_CLOCK_ENABLE];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RF_POWER_CONTROL: begin
            s_ctrlport_resp_data[ENABLE_3V3]    <= enable_3v3_reg;
            s_ctrlport_resp_data[ENABLE_RX_7V0] <= enable_rx_7v0_reg;
            s_ctrlport_resp_data[ENABLE_TX_7V0] <= enable_tx_7v0_reg;
          end

          BASE_ADDRESS + RF_POWER_STATUS: begin
            s_ctrlport_resp_data[P7V_A_STATUS] <= p7v_pg_a;
            s_ctrlport_resp_data[P7V_B_STATUS] <= p7v_pg_b;
          end

          BASE_ADDRESS + PRC_CONTROL: begin
            s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLE] <= pll_ref_clk_enable;
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end

  assign enable_tx_7v0 = enable_tx_7v0_reg;
  assign enable_rx_7v0 = enable_rx_7v0_reg;
  assign enable_3v3    = enable_3v3_reg;

endmodule