data/full_repos/permissive/524567962/designs/ClockDivider/Clock_Divider.sv
1: b"%Error: data/full_repos/permissive/524567962/designs/ClockDivider/Clock_Divider.sv:4: syntax error, unexpected ';', expecting ')' or ','\n  output logic  CLK_2, CLK_4, CLK_8;\n                                   ^\n%Error: data/full_repos/permissive/524567962/designs/ClockDivider/Clock_Divider.sv:9: syntax error, unexpected IDENTIFIER\n  fp1 (.D(q_fp1), .CLK(CLK)), .Q(CLK_2), .QN(qn_fp1)) flopr;\n  ^~~\n%Error: Exiting due to 2 error(s)\n"
module flopr(
  input logic   D,CLK,reset,

  output logic  Q, QN
);

  always_ff @(posedge CLK, posedge reset)
  begin
    if (reset)
    begin
      Q <= 0;
      QN <= 1;
    end
    else
    begin
      Q <= D;
      QN <= ~D;
    end
  end

endmodule
module flopr(
  input logic   D,CLK,reset,

  output logic  Q, QN
);


  always_ff @(posedge CLK, posedge reset)
  begin
    if (reset)
    begin
      Q <= 0;
      QN <= 1;
    end
    else
    begin
      Q <= D;
      QN <= ~D;
    end
  end

endmodule