data/full_repos/permissive/40580763/zpu_core.v
1: b'%Error: data/full_repos/permissive/40580763/zpu_core.v:2: Cannot find include file: zpu_core_defines.v\n`include "zpu_core_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v.v\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v.sv\n             zpu_core_defines.v\n             zpu_core_defines.v.v\n             zpu_core_defines.v.sv\n             obj_dir/zpu_core_defines.v\n             obj_dir/zpu_core_defines.v.v\n             obj_dir/zpu_core_defines.v.sv\n%Error: data/full_repos/permissive/40580763/zpu_core.v:178: Define or directive not defined: \'`MC_MEM_BITS\'\nreg [`MC_MEM_BITS-1:0]  mc_pc;   \n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:179: Define or directive not defined: \'`MC_ADDR_RESET\'\ninitial mc_pc <= `MC_ADDR_RESET-1;\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:180: Define or directive not defined: \'`MC_BITS\'\nwire    [`MC_BITS-1:0] mc_op;   \n         ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:183: Define or directive not defined: \'`SEL_ADDR_SP\'\nassign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:183: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :\n                                           ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:184: Define or directive not defined: \'`SEL_ADDR_A\'\n         (sel_addr == `SEL_ADDR_A)  ? a  : \n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:185: Define or directive not defined: \'`SEL_ADDR_B\'\n         (sel_addr == `SEL_ADDR_B)  ? b  : pc;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:192: Define or directive not defined: \'`ALU_OP_WIDTH\'\nwire [`ALU_OP_WIDTH-1:0] alu_op;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:197: Define or directive not defined: \'`SEL_READ_DATA\'\nassign alu_a =  (sel_read == `SEL_READ_DATA)   ? mem_data_read_int : mem_addr;\n                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:197: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign alu_a =  (sel_read == `SEL_READ_DATA)   ? mem_data_read_int : mem_addr;\n                                           ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:198: Define or directive not defined: \'`SEL_ALU_MC_CONST\'\nassign alu_b =  (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :  \n                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:198: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign alu_b =  (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :  \n                                             ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:198: Define or directive not defined: \'`P_ADDR\'\nassign alu_b =  (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :  \n                                                             ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:198: Define or directive not defined: \'`P_ADDR\'\nassign alu_b =  (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :  \n                                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:198: Define or directive not defined: \'`P_ADDR\'\nassign alu_b =  (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :  \n                                                                                            ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:199: Define or directive not defined: \'`SEL_ALU_A\'\n    (sel_alu == `SEL_ALU_A)     ? a :\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:200: Define or directive not defined: \'`SEL_ALU_B\'\n    (sel_alu == `SEL_ALU_B)        ? b : { {24{1\'b0}} , opcode };  \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:283: Define or directive not defined: \'`P_SEL_READ\'\nassign sel_read  = mc_op[`P_SEL_READ];  \n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:283: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign sel_read  = mc_op[`P_SEL_READ];  \n                                    ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:284: Define or directive not defined: \'`P_SEL_ALU\'\nassign sel_alu   = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:284: Define or directive not defined: \'`P_SEL_ALU\'\nassign sel_alu   = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:284: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign sel_alu   = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];\n                                                ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:285: Define or directive not defined: \'`P_SEL_ADDR\'\nassign sel_addr  = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:285: Define or directive not defined: \'`P_SEL_ADDR\'\nassign sel_addr  = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:285: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign sel_addr  = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];\n                                                  ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:286: Define or directive not defined: \'`P_ALU\'\nassign alu_op    = mc_op[`P_ALU+3:`P_ALU];\n                         ^~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:286: Define or directive not defined: \'`P_ALU\'\nassign alu_op    = mc_op[`P_ALU+3:`P_ALU];\n                                  ^~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:286: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign alu_op    = mc_op[`P_ALU+3:`P_ALU];\n                                        ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:287: Define or directive not defined: \'`P_W_SP\'\nassign w_sp      = mc_op[`P_W_SP] & ~busy;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:287: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_sp      = mc_op[`P_W_SP] & ~busy;\n                                ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:288: Define or directive not defined: \'`P_W_PC\'\nassign w_pc      = mc_op[`P_W_PC] & ~busy;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:288: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_pc      = mc_op[`P_W_PC] & ~busy;\n                                ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:289: Define or directive not defined: \'`P_W_A\'\nassign w_a       = mc_op[`P_W_A] & ~busy;\n                         ^~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:289: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_a       = mc_op[`P_W_A] & ~busy;\n                               ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:290: Define or directive not defined: \'`P_W_A_MEM\'\nassign w_a_mem   = mc_op[`P_W_A_MEM] & ~busy;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:290: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_a_mem   = mc_op[`P_W_A_MEM] & ~busy;\n                                   ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:291: Define or directive not defined: \'`P_W_B\'\nassign w_b    = mc_op[`P_W_B] & ~busy;\n                      ^~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:291: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_b    = mc_op[`P_W_B] & ~busy;\n                            ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:292: Define or directive not defined: \'`P_W_OPCODE\'\nassign w_op      = mc_op[`P_W_OPCODE] & ~busy;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:292: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign w_op      = mc_op[`P_W_OPCODE] & ~busy;\n                                    ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:293: Define or directive not defined: \'`P_MEM_R\'\nassign mem_read  = mc_op[`P_MEM_R];\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:293: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign mem_read  = mc_op[`P_MEM_R];\n                                 ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:294: Define or directive not defined: \'`P_MEM_W\'\nassign mem_write = mc_op[`P_MEM_W];\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:294: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign mem_write = mc_op[`P_MEM_W];\n                                 ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:295: Define or directive not defined: \'`P_SET_IDIM\'\nassign set_idim  = mc_op[`P_SET_IDIM] & ~busy;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:295: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign set_idim  = mc_op[`P_SET_IDIM] & ~busy;\n                                    ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:296: Define or directive not defined: \'`P_CLEAR_IDIM\'\nassign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core.v:296: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;\n                                      ^\n%Error: data/full_repos/permissive/40580763/zpu_core.v:309: Define or directive not defined: \'`P_OP_NOT_CACHED\'\nwire   cond_op_not_cached = mc_op[`P_OP_NOT_CACHED];  \n                                  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module zpu_core_alu(
	alu_a,
	alu_b,
	alu_r,
	flag_idim,
	alu_op,
	clk,
	done
);

input [31:0]				alu_a;
input [31:0]				alu_b;
input [`ALU_OP_WIDTH-1:0]	alu_op;
input						flag_idim;
output [31:0]				alu_r;
input						clk;
output						done;

wire [31:0]					alu_a;
wire [31:0]					alu_b;
wire [`ALU_OP_WIDTH-1:0]	alu_op;
wire						flag_idim;
reg  [31:0]					alu_r;
wire						clk;
reg							done;

`ifdef ENABLE_MULT

reg			mul_running;
reg	[2:0]	mul_counter;
wire		mul_done = (mul_counter == 3);
reg	[31:0]	mul_result, mul_tmp1;
reg	[31:0]	a_in, b_in;

always@(posedge clk)
begin
  a_in		  <= 0;
  b_in		  <= 0;
  mul_tmp1	  <= 0;
  mul_result  <= 0;
  mul_counter <= 0;
  if(mul_running)
  begin
    a_in		<= alu_a;
    b_in		<= alu_b;
    mul_tmp1	<= a_in * b_in;
    mul_result	<= mul_tmp1;
    mul_counter <= mul_counter + 1;
  end
end
`endif

`ifdef ENABLE_DIV





reg  [63:0]	  qr;
wire [33:0]	  diff;
wire [31:0]   quotient;
wire [31:0]   dividend;
wire [31:0]   divider; 	
reg  [6:0]    bit;
wire          div_done;
reg			  div_running;
reg			  divide_sign;
reg			  negative_output;

assign div_done = !bit;
assign diff = qr[63:31] - {1'b0, divider};
assign quotient  = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
assign dividend  = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
assign divider   = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
   
always@(posedge clk)
begin
	bit <= 7'b1_000000;
	if(div_running)
	begin
	  if(bit[6])
	  begin
		  bit             <= 7'd32;
		  qr              <= { 32'd0, dividend };
          negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
      end
      else
	  begin
        if( diff[32] ) 	qr <= { qr[62:0], 1'd0 };
        else 			qr <= { diff[31:0], qr[30:0], 1'd1 };
        bit <= bit - 1;
      end
   end
end
`endif

`ifdef ENABLE_BARREL



reg			  bs_running;
reg [31:0]	  bs_result;
reg  [4:0]	  bs_counter;
wire		  bs_left 	 = alu_b[6];
wire		  bs_logical = alu_b[5];
wire [4:0]	  bs_moves 	 = alu_b[4:0];
wire		  bs_done	 = (bs_counter == bs_moves);

always @(posedge clk)
begin
  bs_counter <= 0;
  bs_result  <= alu_a;
  if(bs_running)
  begin
	if(bs_left) 	 bs_result <= { bs_result[30:0], 1'b0 };
	else
	begin
	  if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] };
	  else			 bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };
	end	  
	bs_counter <= bs_counter + 1;
  end
end
`endif


reg [31:0] alu_b_tmp;
always @(alu_b or alu_op)
begin
  alu_b_tmp <= alu_b;
  if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 };
end

reg [31:0] alu_r_addsub;
always @(alu_a or alu_b_tmp or alu_op)
begin
`ifdef ENABLE_CMP  
  if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED)
  begin
    alu_r_addsub <= alu_a - alu_b_tmp;
  end
  else
`endif
  begin
    alu_r_addsub <= alu_a + alu_b_tmp;
  end
end

`ifdef ENABLE_CMP

reg cmp_exception;
always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
begin
  cmp_exception <= 0;
  if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
	  (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
end
`endif


always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
`ifdef ENABLE_CMP
		or cmp_exception
`endif
`ifdef ENABLE_MULT
		or mul_done or mul_result
`endif
`ifdef ENABLE_BARREL
		or bs_done or bs_result
`endif
`ifdef ENABLE_DIV
		or div_done or div_result
`endif
)
begin
  done <= 1;
`ifdef ENABLE_MULT
  mul_running <= 0;
`endif
`ifdef ENABLE_BARREL
  bs_running <= 0;
`endif
`ifdef ENABLE_DIV
  div_running <= 0;
`endif  
  alu_r <= alu_r_addsub;
  case(alu_op)
    `ALU_NOP		: alu_r <= alu_a;
    `ALU_NOP_B		: alu_r <= alu_b;   
    `ALU_AND		: alu_r <= alu_a & alu_b;
    `ALU_OR			: alu_r <= alu_a | alu_b;
    `ALU_NOT		: alu_r <= ~alu_a;
    `ALU_FLIP		: alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7], 
				     	alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
				     	alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
				     	alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
    `ALU_IM			: if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
			  		  else 		    alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
`ifdef ENABLE_CMP
	`ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) || 
						  (alu_a[31] != alu_b[31] && ~cmp_exception) )
				      begin
				        alu_r[31] <= ~alu_r_addsub[31];
				      end
	`ALU_CMP_SIGNED	: if(cmp_exception)
				      begin
				      	alu_r[31] <= ~alu_r_addsub[31];
				      end
`endif
`ifdef ENABLE_XOR
	`ALU_XOR		: alu_r <= alu_a ^ alu_b;
`endif
`ifdef ENABLE_A_SHIFT
	`ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] };
`endif
`ifdef ENABLE_MULT
	`ALU_MULT 		: begin
					    mul_running <= ~mul_done;
					    done 		<= mul_done;
					    alu_r 		<= mul_result;
					  end
`endif
`ifdef ENABLE_BARREL
	`ALU_BARREL		: begin
					    bs_running <= ~bs_done;
					    done 	   <= bs_done;
					    alu_r 	   <= bs_result;
					  end
`endif
`ifdef ENABLE_DIV
	`ALU_DIV		: begin
					    div_running<= ~div_done;
					    done 	   <= div_done;
					    alu_r 	   <= quotient;
					  end
	`ALU_MOD		: begin
					    div_running<= ~div_done;
					    done 	   <= div_done;
					    alu_r 	   <= qr[31:0];
					  end
`endif
  endcase
end

endmodule
module zpu_core_alu(
	alu_a,
	alu_b,
	alu_r,
	flag_idim,
	alu_op,
	clk,
	done
);


input [31:0]				alu_a;
input [31:0]				alu_b;
input [`ALU_OP_WIDTH-1:0]	alu_op;
input						flag_idim;
output [31:0]				alu_r;
input						clk;
output						done;

wire [31:0]					alu_a;
wire [31:0]					alu_b;
wire [`ALU_OP_WIDTH-1:0]	alu_op;
wire						flag_idim;
reg  [31:0]					alu_r;
wire						clk;
reg							done;

`ifdef ENABLE_MULT

reg			mul_running;
reg	[2:0]	mul_counter;
wire		mul_done = (mul_counter == 3);
reg	[31:0]	mul_result, mul_tmp1;
reg	[31:0]	a_in, b_in;

always@(posedge clk)
begin
  a_in		  <= 0;
  b_in		  <= 0;
  mul_tmp1	  <= 0;
  mul_result  <= 0;
  mul_counter <= 0;
  if(mul_running)
  begin
    a_in		<= alu_a;
    b_in		<= alu_b;
    mul_tmp1	<= a_in * b_in;
    mul_result	<= mul_tmp1;
    mul_counter <= mul_counter + 1;
  end
end
`endif

`ifdef ENABLE_DIV





reg  [63:0]	  qr;
wire [33:0]	  diff;
wire [31:0]   quotient;
wire [31:0]   dividend;
wire [31:0]   divider; 	
reg  [6:0]    bit;
wire          div_done;
reg			  div_running;
reg			  divide_sign;
reg			  negative_output;

assign div_done = !bit;
assign diff = qr[63:31] - {1'b0, divider};
assign quotient  = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
assign dividend  = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
assign divider   = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
   
always@(posedge clk)
begin
	bit <= 7'b1_000000;
	if(div_running)
	begin
	  if(bit[6])
	  begin
		  bit             <= 7'd32;
		  qr              <= { 32'd0, dividend };
          negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
      end
      else
	  begin
        if( diff[32] ) 	qr <= { qr[62:0], 1'd0 };
        else 			qr <= { diff[31:0], qr[30:0], 1'd1 };
        bit <= bit - 1;
      end
   end
end
`endif

`ifdef ENABLE_BARREL



reg			  bs_running;
reg [31:0]	  bs_result;
reg  [4:0]	  bs_counter;
wire		  bs_left 	 = alu_b[6];
wire		  bs_logical = alu_b[5];
wire [4:0]	  bs_moves 	 = alu_b[4:0];
wire		  bs_done	 = (bs_counter == bs_moves);

always @(posedge clk)
begin
  bs_counter <= 0;
  bs_result  <= alu_a;
  if(bs_running)
  begin
	if(bs_left) 	 bs_result <= { bs_result[30:0], 1'b0 };
	else
	begin
	  if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] };
	  else			 bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };
	end	  
	bs_counter <= bs_counter + 1;
  end
end
`endif


reg [31:0] alu_b_tmp;
always @(alu_b or alu_op)
begin
  alu_b_tmp <= alu_b;
  if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 };
end

reg [31:0] alu_r_addsub;
always @(alu_a or alu_b_tmp or alu_op)
begin
`ifdef ENABLE_CMP  
  if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED)
  begin
    alu_r_addsub <= alu_a - alu_b_tmp;
  end
  else
`endif
  begin
    alu_r_addsub <= alu_a + alu_b_tmp;
  end
end

`ifdef ENABLE_CMP

reg cmp_exception;
always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
begin
  cmp_exception <= 0;
  if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
	  (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
end
`endif


always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
`ifdef ENABLE_CMP
		or cmp_exception
`endif
`ifdef ENABLE_MULT
		or mul_done or mul_result
`endif
`ifdef ENABLE_BARREL
		or bs_done or bs_result
`endif
`ifdef ENABLE_DIV
		or div_done or div_result
`endif
)
begin
  done <= 1;
`ifdef ENABLE_MULT
  mul_running <= 0;
`endif
`ifdef ENABLE_BARREL
  bs_running <= 0;
`endif
`ifdef ENABLE_DIV
  div_running <= 0;
`endif  
  alu_r <= alu_r_addsub;
  case(alu_op)
    `ALU_NOP		: alu_r <= alu_a;
    `ALU_NOP_B		: alu_r <= alu_b;   
    `ALU_AND		: alu_r <= alu_a & alu_b;
    `ALU_OR			: alu_r <= alu_a | alu_b;
    `ALU_NOT		: alu_r <= ~alu_a;
    `ALU_FLIP		: alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7], 
				     	alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
				     	alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
				     	alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
    `ALU_IM			: if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
			  		  else 		    alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
`ifdef ENABLE_CMP
	`ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) || 
						  (alu_a[31] != alu_b[31] && ~cmp_exception) )
				      begin
				        alu_r[31] <= ~alu_r_addsub[31];
				      end
	`ALU_CMP_SIGNED	: if(cmp_exception)
				      begin
				      	alu_r[31] <= ~alu_r_addsub[31];
				      end
`endif
`ifdef ENABLE_XOR
	`ALU_XOR		: alu_r <= alu_a ^ alu_b;
`endif
`ifdef ENABLE_A_SHIFT
	`ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] };
`endif
`ifdef ENABLE_MULT
	`ALU_MULT 		: begin
					    mul_running <= ~mul_done;
					    done 		<= mul_done;
					    alu_r 		<= mul_result;
					  end
`endif
`ifdef ENABLE_BARREL
	`ALU_BARREL		: begin
					    bs_running <= ~bs_done;
					    done 	   <= bs_done;
					    alu_r 	   <= bs_result;
					  end
`endif
`ifdef ENABLE_DIV
	`ALU_DIV		: begin
					    div_running<= ~div_done;
					    done 	   <= div_done;
					    alu_r 	   <= quotient;
					  end
	`ALU_MOD		: begin
					    div_running<= ~div_done;
					    done 	   <= div_done;
					    alu_r 	   <= qr[31:0];
					  end
`endif
  endcase
end

endmodule