data/full_repos/permissive/494117590/hdl_src/design/dsp48_inferred.v
data/verilator_xmls/7905cc75-c9c5-4fb9-ba47-4c3c00144ff6.xml
module DSP48_inferred (
  clk ,
  rst_n,

  i_sel,

  i_s18_X,
  i_s18_Y,
  i_s48_C,
  o_s48_XY_plus_C 
);
  
  input                 i_sel;
  input                 clk,rst_n;
  input  signed  [17:0] i_s18_X, i_s18_Y;
  input  signed  [47:0] i_s48_C;
 
  output signed  [47:0] o_s48_XY_plus_C;


  reg    signed  [17:0] s18_X_reg;
  reg    signed  [17:0] s18_Y_reg;


  reg    signed  [47:0] s48_post_mlt_reg;
  reg    signed  [47:0] s48_post_acc_reg;

  assign o_s48_XY_plus_C = s48_post_acc_reg;



  always @(posedge clk ) begin
    if (!rst_n) begin

      s18_X_reg <= 0 ;
      s18_Y_reg <= 0 ;
      s48_post_mlt_reg <= 0 ;
      s48_post_acc_reg <= 0 ;

    end else begin 






      s48_post_mlt_reg <= i_s18_X * i_s18_Y;

      if (i_sel) begin
        s48_post_acc_reg <= s48_post_mlt_reg + i_s48_C;  
      end else begin

        s48_post_acc_reg <= s48_post_mlt_reg + s48_post_acc_reg;  
      end

    end
  end

endmodule
module DSP48_inferred (
  clk ,
  rst_n,

  i_sel,

  i_s18_X,
  i_s18_Y,
  i_s48_C,
  o_s48_XY_plus_C 
);

  
  input                 i_sel;
  input                 clk,rst_n;
  input  signed  [17:0] i_s18_X, i_s18_Y;
  input  signed  [47:0] i_s48_C;
 
  output signed  [47:0] o_s48_XY_plus_C;


  reg    signed  [17:0] s18_X_reg;
  reg    signed  [17:0] s18_Y_reg;


  reg    signed  [47:0] s48_post_mlt_reg;
  reg    signed  [47:0] s48_post_acc_reg;

  assign o_s48_XY_plus_C = s48_post_acc_reg;



  always @(posedge clk ) begin
    if (!rst_n) begin

      s18_X_reg <= 0 ;
      s18_Y_reg <= 0 ;
      s48_post_mlt_reg <= 0 ;
      s48_post_acc_reg <= 0 ;

    end else begin 






      s48_post_mlt_reg <= i_s18_X * i_s18_Y;

      if (i_sel) begin
        s48_post_acc_reg <= s48_post_mlt_reg + i_s48_C;  
      end else begin

        s48_post_acc_reg <= s48_post_mlt_reg + s48_post_acc_reg;  
      end

    end
  end

endmodule