data/full_repos/permissive/504762811/ram.v
1: b'%Error: data/full_repos/permissive/504762811/ram.v:1: Cannot find include file: minicpu.h\n`include "minicpu.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.v\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.sv\n             minicpu.h\n             minicpu.h.v\n             minicpu.h.sv\n             obj_dir/minicpu.h\n             obj_dir/minicpu.h.v\n             obj_dir/minicpu.h.sv\n%Error: data/full_repos/permissive/504762811/ram.v:6: Define or directive not defined: \'`AddrBus\'\n input wire [`AddrBus] addr,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`AddrBus] addr,\n                     ^\n%Error: data/full_repos/permissive/504762811/ram.v:7: Define or directive not defined: \'`DataBus\'\n output reg [`DataBus] d_out,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:8: Define or directive not defined: \'`DataBus\'\n input wire [`DataBus] d_in,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire wr_,\n ^~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire clk\n ^~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:13: Define or directive not defined: \'`DataBus\'\n reg [`DataBus] mem [255:0];\n      ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`DataBus] mem [255:0];\n              ^\n%Error: data/full_repos/permissive/504762811/ram.v:17: syntax error, unexpected always\n always @(*)\n ^~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:18: Define or directive not defined: \'`ENABLE_\'\n  if(rd_==`ENABLE_) begin \n          ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:29: Define or directive not defined: \'`ENABLE_\'\n  if(wr_==`ENABLE_) begin \n          ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/ram.v:40: syntax error, unexpected initial\n initial            \n ^~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module ram (
	input wire [`AddrBus] addr,
	output reg [`DataBus] d_out,
	input wire [`DataBus] d_in,
	input wire rd_, 
	input wire wr_,
	input wire clk
);
	reg [`DataBus] mem [255:0];
	parameter BYTES = 256;
	integer j;

	always @(*)
		if(rd_==`ENABLE_) begin 
			d_out = mem[addr];
			$write("!%-5d: !READ_: ", $time);	
			$write("%x", addr);
			$write("   ");
			$write("%x", d_out);
			$write("\n");	
		end
		else d_out = 8'hxx;

	always @(posedge clk)
		if(wr_==`ENABLE_) begin 
			mem[addr] <= d_in;
			$write("!%-5d: !WRITE_: ", $time);	
			$write("%x", addr);
			$write("   ");
			$write("%x", d_in);
			$write("\n");	
			end
			
	
	integer i;
	initial
		$readmemh("ram.txt", mem, 0, BYTES-1);
	always @(negedge clk) begin
		$write("%3d: ", $time);
		for(i=0;i<48;i=i+1)
			if(mem[i]!==8'hxx) $write(" %x ", mem[i]);
			else $write(" . ");
		$write("\n");
	end	
			

endmodule
module ram (
	input wire [`AddrBus] addr,
	output reg [`DataBus] d_out,
	input wire [`DataBus] d_in,
	input wire rd_, 
	input wire wr_,
	input wire clk
);

	reg [`DataBus] mem [255:0];
	parameter BYTES = 256;
	integer j;

	always @(*)
		if(rd_==`ENABLE_) begin 
			d_out = mem[addr];
			$write("!%-5d: !READ_: ", $time);	
			$write("%x", addr);
			$write("   ");
			$write("%x", d_out);
			$write("\n");	
		end
		else d_out = 8'hxx;

	always @(posedge clk)
		if(wr_==`ENABLE_) begin 
			mem[addr] <= d_in;
			$write("!%-5d: !WRITE_: ", $time);	
			$write("%x", addr);
			$write("   ");
			$write("%x", d_in);
			$write("\n");	
			end
			
	
	integer i;
	initial
		$readmemh("ram.txt", mem, 0, BYTES-1);
	always @(negedge clk) begin
		$write("%3d: ", $time);
		for(i=0;i<48;i=i+1)
			if(mem[i]!==8'hxx) $write(" %x ", mem[i]);
			else $write(" . ");
		$write("\n");
	end	
			

endmodule