data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #50  clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:34: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:35: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10000 \n  ^\n%Error: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:50: syntax error, unexpected \'@\'\n        @(posedge clk)  #10;\n        ^\n%Error: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:52: syntax error, unexpected \'@\'\n        @(posedge clk)  #10;\n        ^\n%Error: data/full_repos/permissive/529469310/RSA/Mod_Func_tb.v:54: syntax error, unexpected \'@\'\n    while (busy==1) @(posedge clk);\n                    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Moulo_test;

reg [`Bit*3-1:0] mem [0:9];
reg [`Bit-1:0] Expect;

reg clk, start;
reg [`Bit:0] Hreg;
reg [`Bit-1:0] Lreg;
reg [`Bit-1:0] C;
wire busy;
wire [`Bit-1:0] M;

integer i;

Modulo mod(clk, start, busy, C, Hreg, Lreg, M);

always #50  clk = ~clk;

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 
  $finish;
end

initial begin
  mem[0] = {16'h1,`Bit'h1};
  mem[1] = {16'h1111,`Bit'haa};
  mem[2] = {16'haaaa,`Bit'hff};
  mem[3] = {16'hffff,`Bit'hff}; 
    clk=1;
    for(i=0;i<10;i=i+1)begin
        start = 0;
        {{Hreg, Lreg},C} = mem[i];
        Expect = {Hreg, Lreg} % C;
        @(posedge clk)  #`delay;
        start = 1;
        @(posedge clk)  #`delay;

    while (busy==1) @(posedge clk);

    if(Expect==M) begin
        $display("Match M=%h Expect=%h",M,Expect);
    end else begin
        $display("Error M=%h Expect=%h",M,Expect);
    end
        
    end
$finish;
end

endmodule
module Moulo_test;


reg [`Bit*3-1:0] mem [0:9];
reg [`Bit-1:0] Expect;

reg clk, start;
reg [`Bit:0] Hreg;
reg [`Bit-1:0] Lreg;
reg [`Bit-1:0] C;
wire busy;
wire [`Bit-1:0] M;

integer i;

Modulo mod(clk, start, busy, C, Hreg, Lreg, M);

always #50  clk = ~clk;

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 
  $finish;
end

initial begin
  mem[0] = {16'h1,`Bit'h1};
  mem[1] = {16'h1111,`Bit'haa};
  mem[2] = {16'haaaa,`Bit'hff};
  mem[3] = {16'hffff,`Bit'hff}; 
    clk=1;
    for(i=0;i<10;i=i+1)begin
        start = 0;
        {{Hreg, Lreg},C} = mem[i];
        Expect = {Hreg, Lreg} % C;
        @(posedge clk)  #`delay;
        start = 1;
        @(posedge clk)  #`delay;

    while (busy==1) @(posedge clk);

    if(Expect==M) begin
        $display("Match M=%h Expect=%h",M,Expect);
    end else begin
        $display("Error M=%h Expect=%h",M,Expect);
    end
        
    end
$finish;
end

endmodule