data/full_repos/permissive/469273213/multiplier/rtl/adder.v
1: b'%Error: data/full_repos/permissive/469273213/multiplier/rtl/adder.v:27: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024\n                                                                      : ... In instance adder\n                for (j = 0; j <= WIDTH-1-i; j = j+1) begin\n                ^~~\n%Error: Exiting due to 1 error(s)\n'
module adder #(parameter WIDTH = 32, CWIDTH = 9) (   
    input wire  [WIDTH-1:0] in_a,
    input wire  [WIDTH-1:0] in_b,
    input wire  c_in,
    output wire c_out,
    output wire [WIDTH-1:0] s 
);

    wire [CWIDTH-1:0] c;
    assign c[0] = c_in;
    genvar i, j;
    generate
        for (i = 0; i <= WIDTH; i = i+4) begin
            if(WIDTH-i >= 4) begin
                claAdder4 cla4i (.in_a(in_a[i +:4]), .in_b(in_b[i +:4]), .c_in(c[i/4]), .s(s[i +:4]), .c_out(c[i/4+1]));
            end else begin
                for (j = 0; j <= WIDTH-1-i; j = j+1) begin
                    fullAdder faj (.a(in_a[j+i]), .b(in_b[j+i]), .c_in(c[i/4+j]), .s(s[j+i]), .c_out(c[i/4+j+1]));
                end
            end
        end
    endgenerate
    assign c_out = c[CWIDTH-1];

endmodule
module adder #(parameter WIDTH = 32, CWIDTH = 9) (   
    input wire  [WIDTH-1:0] in_a,
    input wire  [WIDTH-1:0] in_b,
    input wire  c_in,
    output wire c_out,
    output wire [WIDTH-1:0] s 
);


    wire [CWIDTH-1:0] c;
    assign c[0] = c_in;
    genvar i, j;
    generate
        for (i = 0; i <= WIDTH; i = i+4) begin
            if(WIDTH-i >= 4) begin
                claAdder4 cla4i (.in_a(in_a[i +:4]), .in_b(in_b[i +:4]), .c_in(c[i/4]), .s(s[i +:4]), .c_out(c[i/4+1]));
            end else begin
                for (j = 0; j <= WIDTH-1-i; j = j+1) begin
                    fullAdder faj (.a(in_a[j+i]), .b(in_b[j+i]), .c_in(c[i/4+j]), .s(s[j+i]), .c_out(c[i/4+j+1]));
                end
            end
        end
    endgenerate
    assign c_out = c[CWIDTH-1];

endmodule