data/full_repos/permissive/444327372/divider.v
data/verilator_xmls/31791d63-8c81-4915-8129-90b751013704.xml
module divider(
    input               clk,
    input               rst,
    input [31:0]        a,
    input [31:0]        b,
    input               valid,
    input               sign,


    output wire         div_stall,
    output [63:0]       result
    );

    reg [31:0] a_save, b_save;
    reg [63:0] SR;
    reg [32 :0] NEG_DIVISOR;
    wire [31:0] REMAINER, QUOTIENT;
    assign REMAINER = SR[63:32];
    assign QUOTIENT = SR[31: 0];

    wire [31:0] divident_abs;
    wire [32:0] divisor_abs;
    wire [31:0] remainer, quotient;

    assign divident_abs = (sign & a[31]) ? ~a + 1'b1 : a;

    assign remainer = (sign & a_save[31]) ? ~REMAINER + 1'b1 : REMAINER;
    assign quotient = sign & (a_save[31] ^ b_save[31]) ? ~QUOTIENT + 1'b1 : QUOTIENT;
    assign result = {remainer,quotient};

    wire CO;
    wire [32:0] sub_result;
    wire [32:0] mux_result;

    assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR;

    assign mux_result = CO ? sub_result : {1'b0,REMAINER};


    reg [5:0] cnt;
    reg start_cnt;
    always @(posedge clk, posedge rst) begin
        if(rst) begin
            cnt <= 0;
            start_cnt <= 0;
        end
        else if(!start_cnt & valid) begin
            cnt <= 1;
            start_cnt <= 1;

            a_save <= a;
            b_save <= b;


            SR[63:0] <= {31'b0,divident_abs,1'b0};
            NEG_DIVISOR <= (sign & b[31]) ? {1'b1,b} : ~{1'b0,b} + 1'b1;
        end
        else if(start_cnt) begin
            if(cnt==32) begin
                cnt <= 0;
                start_cnt <= 0;
                

                SR[63:32] <= mux_result[31:0];
                SR[0] <= CO;
            end
            else begin
                cnt <= cnt + 1;

                SR[63:0] <= {mux_result[30:0],SR[31:1],CO,1'b0};
            end
        end
    end
    
    assign div_stall = |cnt;
endmodule
module divider(
    input               clk,
    input               rst,
    input [31:0]        a,
    input [31:0]        b,
    input               valid,
    input               sign,


    output wire         div_stall,
    output [63:0]       result
    );


    reg [31:0] a_save, b_save;
    reg [63:0] SR;
    reg [32 :0] NEG_DIVISOR;
    wire [31:0] REMAINER, QUOTIENT;
    assign REMAINER = SR[63:32];
    assign QUOTIENT = SR[31: 0];

    wire [31:0] divident_abs;
    wire [32:0] divisor_abs;
    wire [31:0] remainer, quotient;

    assign divident_abs = (sign & a[31]) ? ~a + 1'b1 : a;

    assign remainer = (sign & a_save[31]) ? ~REMAINER + 1'b1 : REMAINER;
    assign quotient = sign & (a_save[31] ^ b_save[31]) ? ~QUOTIENT + 1'b1 : QUOTIENT;
    assign result = {remainer,quotient};

    wire CO;
    wire [32:0] sub_result;
    wire [32:0] mux_result;

    assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR;

    assign mux_result = CO ? sub_result : {1'b0,REMAINER};


    reg [5:0] cnt;
    reg start_cnt;
    always @(posedge clk, posedge rst) begin
        if(rst) begin
            cnt <= 0;
            start_cnt <= 0;
        end
        else if(!start_cnt & valid) begin
            cnt <= 1;
            start_cnt <= 1;

            a_save <= a;
            b_save <= b;


            SR[63:0] <= {31'b0,divident_abs,1'b0};
            NEG_DIVISOR <= (sign & b[31]) ? {1'b1,b} : ~{1'b0,b} + 1'b1;
        end
        else if(start_cnt) begin
            if(cnt==32) begin
                cnt <= 0;
                start_cnt <= 0;
                

                SR[63:32] <= mux_result[31:0];
                SR[0] <= CO;
            end
            else begin
                cnt <= cnt + 1;

                SR[63:0] <= {mux_result[30:0],SR[31:1],CO,1'b0};
            end
        end
    end
    
    assign div_stall = |cnt;
endmodule