data/full_repos/permissive/449807379/CPU_design/mux_2x1_32bit.v
data/verilator_xmls/97bb67a9-3e83-493e-8a02-11a54cd02e22.xml
module mux_2x1_32bit(LDR_sel, register_data, ram_in, alu_result);

input [31:0] ram_in, alu_result;
input  LDR_sel;
output reg [31:0] register_data;

always @(*)
begin
case (LDR_sel)
1'b1: register_data = ram_in;
1'b0: register_data = alu_result;
endcase

end
endmodule
module mux_2x1_32bit(LDR_sel, register_data, ram_in, alu_result);


input [31:0] ram_in, alu_result;
input  LDR_sel;
output reg [31:0] register_data;

always @(*)
begin
case (LDR_sel)
1'b1: register_data = ram_in;
1'b0: register_data = alu_result;
endcase

end
endmodule