data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v
1: b"%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:325: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;\n                                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:392: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin\n                                       ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module MemoryController(
    input clk,
    input read_a,
    input read_b,
    input write,
    input [21:0] addr,
    input [7:0] din,
    output reg [7:0] dout_a,
    output reg [7:0] dout_b,
    output reg busy
);











wire is_internal_ram = addr[21:16] == 'b11_1000;
wire is_vram = addr[21:16] == 'b11_0000;
wire is_prg_ram = addr[21:17] == 'b11_110;
wire is_hole = addr[21:20] == 'b01 || (addr[21:20] == 'b11 && !is_prg_ram && !is_internal_ram && !is_vram);
wire [17:0] ram_addr = is_prg_ram ? {'b0, addr[16:0]}:
                       is_internal_ram ? {'b10, addr[15:0]} :
                       is_vram ? {'b11, addr[15:0]} :
                       {addr[21], addr[19:3]};
wire [3:0] ram_offset = (is_vram || is_internal_ram || is_prg_ram) ? 'b1000 : {'b0, addr[2:0]};
wire [8:0] ram_we = is_hole ? 0 : framwe(ram_offset, write);
wire [71:0] edin= ram_offset == 0 ? din :
                  ram_offset == 1 ? din << 8 :
                  ram_offset == 2 ? din << 16 :
                  ram_offset == 3 ? din << 24 :
                  ram_offset == 4 ? {'h00_00_00_00, din, 'h00_00_00_00} :
                  ram_offset == 5 ? {'h00_00_00, din, 'h00_00_00_00_00} :
                  ram_offset == 6 ? {'h00_00, din, 'h00_00_00_00_00_00} :
                  ram_offset == 7 ? {'h00, din, 'h00_00_00_00_00_00_00} :
                  {din, 'h00_00_00_00_00_00_00_00};
wire [71:0] edout;

function [8:0] framwe(input [3:0] offset, input write);
    case(offset)
    0:  framwe = write ? 'b0_0000_0001 : 0;
    1:  framwe = write ? 'b0_0000_0010 : 0;
    2:  framwe = write ? 'b0_0000_0100 : 0;
    3:  framwe = write ? 'b0_0000_1000 : 0;
    4:  framwe = write ? 'b0_0001_0000 : 0;
    5:  framwe = write ? 'b0_0010_0000 : 0;
    6:  framwe = write ? 'b0_0100_0000 : 0;
    7:  framwe = write ? 'b0_1000_0000 : 0;
    default: framwe = write ? 'b1_0000_0000 : 0;
    endcase
endfunction

function [7:0] fdout(input [3:0] offset, input [71:0] edout);
    case(offset)
    0: fdout = edout[7:0];
    1: fdout = edout[15:8];
    2: fdout = edout[23:16];
    3: fdout = edout[31:24];
    4: fdout = edout[39:32];
    5: fdout = edout[47:40];
    6: fdout = edout[55:48];
    7: fdout = edout[63:56];
    default: fdout = edout[71:64];
    endcase
endfunction

bytewrite_ram_1b ram(clk, ram_we, ram_addr, edin, edout);

reg r_read_a, r_read_b;
reg [3:0] r_ram_offset;

always @(posedge clk) begin
    busy <= 0;
    r_read_a <= read_a;
    r_read_b <= read_b;
    r_ram_offset <= ram_offset;
    if (r_read_a) begin
        dout_a <= fdout(r_ram_offset, edout);
    end else if (r_read_b) begin
        dout_b <= fdout(r_ram_offset, edout);
    end
end

endmodule
module MemoryController(
    input clk,
    input read_a,
    input read_b,
    input write,
    input [21:0] addr,
    input [7:0] din,
    output reg [7:0] dout_a,
    output reg [7:0] dout_b,
    output reg busy
);












wire is_internal_ram = addr[21:16] == 'b11_1000;
wire is_vram = addr[21:16] == 'b11_0000;
wire is_prg_ram = addr[21:17] == 'b11_110;
wire is_hole = addr[21:20] == 'b01 || (addr[21:20] == 'b11 && !is_prg_ram && !is_internal_ram && !is_vram);
wire [17:0] ram_addr = is_prg_ram ? {'b0, addr[16:0]}:
                       is_internal_ram ? {'b10, addr[15:0]} :
                       is_vram ? {'b11, addr[15:0]} :
                       {addr[21], addr[19:3]};
wire [3:0] ram_offset = (is_vram || is_internal_ram || is_prg_ram) ? 'b1000 : {'b0, addr[2:0]};
wire [8:0] ram_we = is_hole ? 0 : framwe(ram_offset, write);
wire [71:0] edin= ram_offset == 0 ? din :
                  ram_offset == 1 ? din << 8 :
                  ram_offset == 2 ? din << 16 :
                  ram_offset == 3 ? din << 24 :
                  ram_offset == 4 ? {'h00_00_00_00, din, 'h00_00_00_00} :
                  ram_offset == 5 ? {'h00_00_00, din, 'h00_00_00_00_00} :
                  ram_offset == 6 ? {'h00_00, din, 'h00_00_00_00_00_00} :
                  ram_offset == 7 ? {'h00, din, 'h00_00_00_00_00_00_00} :
                  {din, 'h00_00_00_00_00_00_00_00};
wire [71:0] edout;

function [8:0] framwe(input [3:0] offset, input write);
    case(offset)
    0:  framwe = write ? 'b0_0000_0001 : 0;
    1:  framwe = write ? 'b0_0000_0010 : 0;
    2:  framwe = write ? 'b0_0000_0100 : 0;
    3:  framwe = write ? 'b0_0000_1000 : 0;
    4:  framwe = write ? 'b0_0001_0000 : 0;
    5:  framwe = write ? 'b0_0010_0000 : 0;
    6:  framwe = write ? 'b0_0100_0000 : 0;
    7:  framwe = write ? 'b0_1000_0000 : 0;
    default: framwe = write ? 'b1_0000_0000 : 0;
    endcase
endfunction

function [7:0] fdout(input [3:0] offset, input [71:0] edout);
    case(offset)
    0: fdout = edout[7:0];
    1: fdout = edout[15:8];
    2: fdout = edout[23:16];
    3: fdout = edout[31:24];
    4: fdout = edout[39:32];
    5: fdout = edout[47:40];
    6: fdout = edout[55:48];
    7: fdout = edout[63:56];
    default: fdout = edout[71:64];
    endcase
endfunction

bytewrite_ram_1b ram(clk, ram_we, ram_addr, edin, edout);

reg r_read_a, r_read_b;
reg [3:0] r_ram_offset;

always @(posedge clk) begin
    busy <= 0;
    r_read_a <= read_a;
    r_read_b <= read_b;
    r_ram_offset <= ram_offset;
    if (r_read_a) begin
        dout_a <= fdout(r_ram_offset, edout);
    end else if (r_read_b) begin
        dout_b <= fdout(r_ram_offset, edout);
    end
end

endmodule