data/full_repos/permissive/501791642/sim/uart_rx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK = ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #4 CE = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #5 RST = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 DI = 0;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100 DI = 0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #4000 $stop;\n    ^\n%Error: data/full_repos/permissive/501791642/sim/uart_rx_tb.v:18: Cannot find file containing module: \'uart_rx\'\nuart_rx #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/uart_rx\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/uart_rx.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_rx_tb;

reg CLK, CE, RST, DI;
wire DV;
wire [7:0] PO;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
    DI = 1;
end

always #1 CLK = ~CLK;

uart_rx #(
    .CLKS_PER_BIT(50),
    .CLKS_PER_BIT_W(6)
)
uart_receiver
(
    .CLK(CLK),
    .CE(CE),
    .RST(RST),
    .DI(DI),
    .DV(DV),
    .PO(PO)
);

initial begin
    #4 CE = 1;
    #5 RST = 0;
    #10 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;

    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 0;

    #4000 $stop;
end

endmodule
module uart_rx_tb;


reg CLK, CE, RST, DI;
wire DV;
wire [7:0] PO;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
    DI = 1;
end

always #1 CLK = ~CLK;

uart_rx #(
    .CLKS_PER_BIT(50),
    .CLKS_PER_BIT_W(6)
)
uart_receiver
(
    .CLK(CLK),
    .CE(CE),
    .RST(RST),
    .DI(DI),
    .DV(DV),
    .PO(PO)
);

initial begin
    #4 CE = 1;
    #5 RST = 0;
    #10 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;

    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 1;
    #100 DI = 0;
    #100 DI = 0;

    #4000 $stop;
end

endmodule