data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_ifu_ras_entry.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_ifu_ras_entry.v:65: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_ras_entry_icg_cell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418750043/gated_clk_cell\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/ifu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: Exiting due to 1 error(s)\n"
module aq_ifu_ras_entry(
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  ras_entry_pc,
  ras_entry_upd,
  ras_upd_pc
);


input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           cpurst_b;          
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input           ras_entry_upd;     
input   [23:0]  ras_upd_pc;        
output  [23:0]  ras_entry_pc;      


reg     [23:0]  entry_pc;          


wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            cpurst_b;          
wire            entry_clk;         
wire            entry_clk_en;      
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [23:0]  ras_entry_pc;      
wire            ras_entry_upd;     
wire    [23:0]  ras_upd_pc;        











assign entry_clk_en = ras_entry_upd;

gated_clk_cell  x_ras_entry_icg_cell (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (entry_clk         ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (entry_clk_en      ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge entry_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    entry_pc[23:0] <= 24'b0;
  end
  else if(ras_entry_upd)
  begin
    entry_pc[23:0] <= ras_upd_pc[23:0];
  end
  else
  begin
    entry_pc[23:0] <= entry_pc[23:0];
  end
end





assign ras_entry_pc[23:0] = entry_pc[23:0];



endmodule
module aq_ifu_ras_entry(
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  ras_entry_pc,
  ras_entry_upd,
  ras_upd_pc
);



input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           cpurst_b;          
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input           ras_entry_upd;     
input   [23:0]  ras_upd_pc;        
output  [23:0]  ras_entry_pc;      


reg     [23:0]  entry_pc;          


wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            cpurst_b;          
wire            entry_clk;         
wire            entry_clk_en;      
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [23:0]  ras_entry_pc;      
wire            ras_entry_upd;     
wire    [23:0]  ras_upd_pc;        











assign entry_clk_en = ras_entry_upd;

gated_clk_cell  x_ras_entry_icg_cell (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (entry_clk         ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (entry_clk_en      ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge entry_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    entry_pc[23:0] <= 24'b0;
  end
  else if(ras_entry_upd)
  begin
    entry_pc[23:0] <= ras_upd_pc[23:0];
  end
  else
  begin
    entry_pc[23:0] <= entry_pc[23:0];
  end
end





assign ras_entry_pc[23:0] = entry_pc[23:0];



endmodule