data/full_repos/permissive/465580112/DLPRV32/shift.v
data/verilator_xmls/48da1d71-5b20-45ea-be13-75e917585dcb.xml
module shift(
  input [31:0]  op1,op2,
  input clk,
  input     cs_shift,
  input [3:0]   dec_val,
  output  reg [31:0] rslt3
);
  always@(posedge clk)
    begin
      if(cs_shift)
        case(dec_val)
          2:rslt3=op1<<op2;
          3:rslt3=(op1<op2)?32'd1:32'd0;
          4:rslt3=(op1<op2)?32'd1:32'd0;
          7:rslt3=op1>>op2;
          8:rslt3=op1>>>op2;
        endcase
    end
endmodule
module shift(
  input [31:0]  op1,op2,
  input clk,
  input     cs_shift,
  input [3:0]   dec_val,
  output  reg [31:0] rslt3
);

  always@(posedge clk)
    begin
      if(cs_shift)
        case(dec_val)
          2:rslt3=op1<<op2;
          3:rslt3=(op1<op2)?32'd1:32'd0;
          4:rslt3=(op1<op2)?32'd1:32'd0;
          7:rslt3=op1>>op2;
          8:rslt3=op1>>>op2;
        endcase
    end
endmodule