data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp13anon6/reference/MultiClockSpecanonfun22anonfunapplymcVsp13anon6.v
data/verilator_xmls/b839b058-7aa8-40d3-86d3-f7663e9f38e0.xml
module BITS(y, in);
    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule
module BITS(y, in);

    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule