data/full_repos/permissive/503053625/fpga_projects/SPGD/src/DAC_OUT.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/DAC_OUT.v:26: Cannot find file containing module: 'gen_mult'\n    gen_mult #(.DATA_WIDTH(FP_WIDTH)) cal_mult(.a(IN_VOLTAGE), .b(DAC_CAL_GAIN), .p(DAC_CAL_MUL_OUT));\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/gen_mult\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/gen_mult.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/gen_mult.sv\n             gen_mult\n             gen_mult.v\n             gen_mult.sv\n             obj_dir/gen_mult\n             obj_dir/gen_mult.v\n             obj_dir/gen_mult.sv\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/DAC_OUT.v:27: Cannot find file containing module: 'gen_subber'\n    gen_subber #(.IN_WIDTH(FP_WIDTH)) cal_sub(.a(DAC_CAL_MUL_OUT[FP_WIDTH*2-1-INT_WIDTH:FP_WIDTH-INT_WIDTH]), .b(DAC_CAL_OFFSET), .s(DAC_CAL_SUB_OUT));\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/DAC_OUT.v:28: Cannot find file containing module: 'my_mult'\n    my_mult #(\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module DAC_OUT
#(
    parameter FP_WIDTH = 64,
    parameter DAC_WIDTH = 14,
    parameter INT_WIDTH = 16
)
(
    input   [FP_WIDTH  - 1 : 0] IN_VOLTAGE,
    input   [FP_WIDTH  - 1 : 0] DAC_CAL_GAIN,
    input   [FP_WIDTH  - 1 : 0] DAC_CAL_OFFSET,
    output  [DAC_WIDTH  - 1 : 0] DAC_CODE_OUT
);

    reg [FP_WIDTH    - 1 : 0] N_SIXTEEN_K_OVER_TWENTY = {{16'hFCCC}, {((FP_WIDTH-INT_WIDTH)/4){4'hC}}};




    wire [INT_WIDTH      - 1 : 0] DAC_CODE_OUT_MUL;



    wire [2*FP_WIDTH - 1: 0] DAC_CAL_MUL_OUT;
    wire [FP_WIDTH : 0] DAC_CAL_SUB_OUT;

    gen_mult #(.DATA_WIDTH(FP_WIDTH)) cal_mult(.a(IN_VOLTAGE), .b(DAC_CAL_GAIN), .p(DAC_CAL_MUL_OUT));
    gen_subber #(.IN_WIDTH(FP_WIDTH)) cal_sub(.a(DAC_CAL_MUL_OUT[FP_WIDTH*2-1-INT_WIDTH:FP_WIDTH-INT_WIDTH]), .b(DAC_CAL_OFFSET), .s(DAC_CAL_SUB_OUT));
    my_mult #(
        .DATA_WIDTH(FP_WIDTH),
        .OUT_WIDTH(DAC_WIDTH),
        .INT_FORMAT(INT_WIDTH-DAC_WIDTH),
        .DEC_FORMAT(FP_WIDTH-INT_WIDTH)
    ) MULT0 (
        .a(DAC_CAL_SUB_OUT[FP_WIDTH - 1:0]),
        .b(N_SIXTEEN_K_OVER_TWENTY),
        .p(DAC_CODE_OUT)
    );



endmodule
module DAC_OUT
#(
    parameter FP_WIDTH = 64,
    parameter DAC_WIDTH = 14,
    parameter INT_WIDTH = 16
)
(
    input   [FP_WIDTH  - 1 : 0] IN_VOLTAGE,
    input   [FP_WIDTH  - 1 : 0] DAC_CAL_GAIN,
    input   [FP_WIDTH  - 1 : 0] DAC_CAL_OFFSET,
    output  [DAC_WIDTH  - 1 : 0] DAC_CODE_OUT
);


    reg [FP_WIDTH    - 1 : 0] N_SIXTEEN_K_OVER_TWENTY = {{16'hFCCC}, {((FP_WIDTH-INT_WIDTH)/4){4'hC}}};




    wire [INT_WIDTH      - 1 : 0] DAC_CODE_OUT_MUL;



    wire [2*FP_WIDTH - 1: 0] DAC_CAL_MUL_OUT;
    wire [FP_WIDTH : 0] DAC_CAL_SUB_OUT;

    gen_mult #(.DATA_WIDTH(FP_WIDTH)) cal_mult(.a(IN_VOLTAGE), .b(DAC_CAL_GAIN), .p(DAC_CAL_MUL_OUT));
    gen_subber #(.IN_WIDTH(FP_WIDTH)) cal_sub(.a(DAC_CAL_MUL_OUT[FP_WIDTH*2-1-INT_WIDTH:FP_WIDTH-INT_WIDTH]), .b(DAC_CAL_OFFSET), .s(DAC_CAL_SUB_OUT));
    my_mult #(
        .DATA_WIDTH(FP_WIDTH),
        .OUT_WIDTH(DAC_WIDTH),
        .INT_FORMAT(INT_WIDTH-DAC_WIDTH),
        .DEC_FORMAT(FP_WIDTH-INT_WIDTH)
    ) MULT0 (
        .a(DAC_CAL_SUB_OUT[FP_WIDTH - 1:0]),
        .b(N_SIXTEEN_K_OVER_TWENTY),
        .p(DAC_CODE_OUT)
    );



endmodule