data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:9: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:10: Cannot find include file: mod_ids.vh\n    ,`include "mod_ids.vh" \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:10: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:12: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                                               OUTPORT_QUANT               = 1,     \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:13: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                                               INSTANCE_NAME               = "R1",\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                                               MODULES_PER_ROUTER          = 1,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:15: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter                                               LINKS_PER_ROUTER            = OUTPORT_QUANT-1-MODULES_PER_ROUTER,    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:16: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter   [LUT_SIZE*LINKS_PER_ROUTER-1:0]             LUT_RESET_VALUE             = 0,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:17: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter   [MOD_X_COORD_SIZE-1:0]                      DIRECTION_ADD_X             = 0,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:18: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter   [MOD_Y_COORD_SIZE-1:0]                      DIRECTION_ADD_Y             = 0\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:19: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                            rstq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire    [NOC_CHIPID_SIZE-1:0]                   home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire    [NOC_HEADER_SIZE-1:0]                   header_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                            flitReady_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                            burst_active_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         rin_routing_lut_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         r_routing_lut_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                            lut_update_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire    [OUTPORT_QUANT-1:0]                     candidateList_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:32: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/tTrgPortCandidateCalc_OnOff_lut.v:77: syntax error, unexpected assign\n    assign trg_mod_z  = header_i[MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1:CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];\n    ^~~~~~\n%Error: Exiting due to 22 error(s)\n'
module tTrgPortCandidateCalc_OnOff_lut #(
    `include "noc_parameter.vh"
    ,`include "mod_ids.vh"
    ,parameter                                              INPORT_ID                   = 1,
    parameter                                               OUTPORT_QUANT               = 1,
    parameter                                               INSTANCE_NAME               = "R1",
    parameter                                               MODULES_PER_ROUTER          = 1,
    parameter                                               LINKS_PER_ROUTER            = OUTPORT_QUANT-1-MODULES_PER_ROUTER,
    parameter   [LUT_SIZE*LINKS_PER_ROUTER-1:0]             LUT_RESET_VALUE             = 0,
    parameter   [MOD_X_COORD_SIZE-1:0]                      DIRECTION_ADD_X             = 0,
    parameter   [MOD_Y_COORD_SIZE-1:0]                      DIRECTION_ADD_Y             = 0
)
(
    input   wire                                            clk_i,
    input   wire                                            rstq_i,
    input   wire    [NOC_CHIPID_SIZE-1:0]                   home_chipid_i,

    input   wire    [NOC_HEADER_SIZE-1:0]                   header_i,
    input   wire                                            flitReady_i,
    input   wire                                            burst_active_i,
    input   wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         rin_routing_lut_i,
    output  wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         r_routing_lut_o,
    input   wire                                            lut_update_en_i,
    output  wire    [OUTPORT_QUANT-1:0]                     candidateList_o
);


    reg     [OUTPORT_QUANT-1:0]                             rin_candidateList;
    reg     [OUTPORT_QUANT-1:0]                             r_candidateList_stored, r_candidateList_out;
    reg     [OUTPORT_QUANT-1:0]                             rin_candidateList_stored;

    reg     [LUT_SIZE*LINKS_PER_ROUTER-1:0]                 r_routing_lut;
    reg     [LUT_SIZE-1:0]                                  routing_lut_array [0:LINKS_PER_ROUTER-1];

    wire    [MOD_X_COORD_SIZE-1:0]                          trg_mod_x;
    wire    [MOD_Y_COORD_SIZE-1:0]                          trg_mod_y;
    wire    [MOD_Z_COORD_SIZE-1:0]                          trg_mod_z;
    wire    [MOD_X_COORD_SIZE-1:0]                          trg_mod_x_OffChip;
    wire    [MOD_Y_COORD_SIZE-1:0]                          trg_mod_y_OffChip;
    wire    [MOD_Z_COORD_SIZE-1:0]                          trg_mod_z_OffChip;

    wire    [NOC_CHIPID_SIZE-1:0]                           trg_chipID;


    reg     go_home;
    reg     go_left;
    reg     go_right;
    reg     go_up;
    reg     go_down;
    reg     go_OnTemp_offchip;
    reg     go_OnTemp_left;
    reg     go_OnTemp_right;
    reg     go_OnTemp_up;
    reg     go_OnTemp_down;
    reg     go_OffTemp_left;
    reg     go_OffTemp_right;
    reg     go_OffTemp_up;
    reg     go_OffTemp_down;

    reg     [2:0] routing_lut_bit_sel;



    assign trg_mod_z  = header_i[MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1:CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];

    assign r_routing_lut_o  = r_routing_lut;
    assign candidateList_o  = r_candidateList_out;

    always @* begin
        if( burst_active_i) begin
            r_candidateList_out      = r_candidateList_stored;
        end else begin
            r_candidateList_out      = rin_candidateList & {OUTPORT_QUANT{flitReady_i}};
        end
    end

    always @(posedge clk_i, negedge rstq_i) begin
        if(rstq_i == 1'b0) begin
            r_candidateList_stored  <= {OUTPORT_QUANT{1'b0}};
        end else begin
            r_candidateList_stored  <= rin_candidateList_stored;
        end
    end

    always @* begin
        rin_candidateList_stored   = r_candidateList_stored;
        if(burst_active_i==0) begin
            rin_candidateList_stored      = rin_candidateList;
        end else begin
            rin_candidateList_stored      = r_candidateList_stored;
        end
    end

    always @(posedge clk_i, negedge rstq_i) begin: routing_lut_register
        if (rstq_i == 1'b0) begin
            r_routing_lut   <=  LUT_RESET_VALUE;
        end else begin
            if (lut_update_en_i == 1'b1) begin
                r_routing_lut   <=  rin_routing_lut_i;
            end
        end
    end


    assign trg_chipID   = header_i[CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1:0];

    assign trg_mod_x    = header_i[MOD_X_COORD_SIZE+MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1 : MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];
    assign trg_mod_y    = header_i[MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1 : MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];


    assign trg_mod_x_OffChip = MODID_ETH[MOD_X_COORD_SIZE+MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE-1 : MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE];
    assign trg_mod_y_OffChip = MODID_ETH[MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE-1 : MOD_Z_COORD_SIZE];
    assign trg_mod_z_OffChip = MODID_ETH[MOD_Z_COORD_SIZE-1 : 0];


    always @* begin: tempOff_xy_set_direction
        if (trg_chipID == home_chipid_i) begin
            go_OffTemp_left     = 1'b0;
            go_OffTemp_right    = 1'b0;
            go_OffTemp_up       = 1'b0;
            go_OffTemp_down     = 1'b0;
        end else begin
            if (trg_mod_x_OffChip < DIRECTION_ADD_X) begin
                go_OffTemp_left     = 1'b1;
                go_OffTemp_right    = 1'b0;
            end else if (trg_mod_x_OffChip > DIRECTION_ADD_X) begin
                go_OffTemp_left     = 1'b0;
                go_OffTemp_right    = 1'b1;
            end else begin
                go_OffTemp_left     = 1'b0;
                go_OffTemp_right    = 1'b0;
            end
            if (trg_mod_y_OffChip < DIRECTION_ADD_Y) begin
                go_OffTemp_up       = 1'b0;
                go_OffTemp_down     = 1'b1;
            end else if (trg_mod_y_OffChip > DIRECTION_ADD_Y) begin
                go_OffTemp_up       = 1'b1;
                go_OffTemp_down     = 1'b0;
            end else begin
                go_OffTemp_up       = 1'b0;
                go_OffTemp_down     = 1'b0;
            end
        end
    end


    always @* begin: OnChip_set_direction
        if (trg_chipID != home_chipid_i) begin
            go_OnTemp_offchip   = 1'b1;
            go_OnTemp_left      = 1'b0;
            go_OnTemp_right     = 1'b0;
            go_OnTemp_up        = 1'b0;
            go_OnTemp_down      = 1'b0;
        end else begin
            go_OnTemp_offchip = 1'b0;
            if (trg_mod_x < DIRECTION_ADD_X) begin
                go_OnTemp_left      = 1'b1;
                go_OnTemp_right = 1'b0;
            end else if (trg_mod_x > DIRECTION_ADD_X) begin
                go_OnTemp_left      = 1'b0;
                go_OnTemp_right = 1'b1;
            end else begin
                go_OnTemp_left      = 1'b0;
                go_OnTemp_right = 1'b0;
            end
            if (trg_mod_y < DIRECTION_ADD_Y) begin
                go_OnTemp_up        = 1'b0;
                go_OnTemp_down      = 1'b1;
            end else if (trg_mod_y > DIRECTION_ADD_Y) begin
                go_OnTemp_up        = 1'b1;
                go_OnTemp_down      = 1'b0;
            end else begin
                go_OnTemp_up        = 1'b0;
                go_OnTemp_down      = 1'b0;
            end
        end
    end

    always @* begin: Final_set_direction
        if (trg_chipID == home_chipid_i) begin
            go_left    = go_OnTemp_left;
            go_right   = go_OnTemp_right;
            go_up      = go_OnTemp_up;
            go_down    = go_OnTemp_down;
            go_home    = ~ (go_OnTemp_left | go_OnTemp_right | go_OnTemp_up | go_OnTemp_down);
        end else begin
            go_left    = go_OffTemp_left;
            go_right   = go_OffTemp_right;
            go_up      = go_OffTemp_up;
            go_down    = go_OffTemp_down;
            go_home    = ~ (go_OffTemp_left | go_OffTemp_right | go_OffTemp_up | go_OffTemp_down);
        end
    end



    always @* begin: set_lut_addr
        case ({go_left, go_right, go_up, go_down})
            4'b0010:    routing_lut_bit_sel = 3'd7;
            4'b0110:    routing_lut_bit_sel = 3'd6;
            4'b0100:    routing_lut_bit_sel = 3'd5;
            4'b0101:    routing_lut_bit_sel = 3'd4;
            4'b0001:    routing_lut_bit_sel = 3'd3;
            4'b1001:    routing_lut_bit_sel = 3'd2;
            4'b1000:    routing_lut_bit_sel = 3'd1;
            4'b1010:    routing_lut_bit_sel = 3'd0;
            default:    routing_lut_bit_sel = 3'd0;
        endcase
    end

    genvar i;
    generate
        for (i=0; i<OUTPORT_QUANT; i=i+1) begin: set_possible_outPort_remote
            always @* begin
                rin_candidateList[i] = 1'b0;


                if (i < MODULES_PER_ROUTER) begin
                    if (go_home == 1'b1) begin
                        if (go_OnTemp_offchip == 1'b1) begin
                            if (i == trg_mod_z_OffChip) begin
                                rin_candidateList[i] = 1'b1;
                            end
                        end else if (i == trg_mod_z) begin
                            rin_candidateList[i] = 1'b1;
                        end
                    end
                end


                else if (i < (OUTPORT_QUANT-1)) begin
                    if (go_home == 1'b0) begin
                        rin_candidateList[i] = routing_lut_array[i-MODULES_PER_ROUTER][routing_lut_bit_sel];
                    end
                end


                else begin
                    if ((go_home == 1'b1) && (trg_mod_z == {MOD_Z_COORD_SIZE{1'b1}})) begin
                        rin_candidateList[i] = 1'b1;
                    end
                end
            end
        end
    endgenerate


    genvar j;
    generate
        for (j=0; j<LINKS_PER_ROUTER; j=j+1) begin: lut_vector2array
            always @* begin
                routing_lut_array [j]   = r_routing_lut [LUT_SIZE*(j+1)-1:LUT_SIZE*j];
            end
        end
    endgenerate

endmodule
module tTrgPortCandidateCalc_OnOff_lut #(
    `include "noc_parameter.vh"
    ,`include "mod_ids.vh"
    ,parameter                                              INPORT_ID                   = 1,
    parameter                                               OUTPORT_QUANT               = 1,
    parameter                                               INSTANCE_NAME               = "R1",
    parameter                                               MODULES_PER_ROUTER          = 1,
    parameter                                               LINKS_PER_ROUTER            = OUTPORT_QUANT-1-MODULES_PER_ROUTER,
    parameter   [LUT_SIZE*LINKS_PER_ROUTER-1:0]             LUT_RESET_VALUE             = 0,
    parameter   [MOD_X_COORD_SIZE-1:0]                      DIRECTION_ADD_X             = 0,
    parameter   [MOD_Y_COORD_SIZE-1:0]                      DIRECTION_ADD_Y             = 0
)
(
    input   wire                                            clk_i,
    input   wire                                            rstq_i,
    input   wire    [NOC_CHIPID_SIZE-1:0]                   home_chipid_i,

    input   wire    [NOC_HEADER_SIZE-1:0]                   header_i,
    input   wire                                            flitReady_i,
    input   wire                                            burst_active_i,
    input   wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         rin_routing_lut_i,
    output  wire    [LUT_SIZE*LINKS_PER_ROUTER-1:0]         r_routing_lut_o,
    input   wire                                            lut_update_en_i,
    output  wire    [OUTPORT_QUANT-1:0]                     candidateList_o
);



    reg     [OUTPORT_QUANT-1:0]                             rin_candidateList;
    reg     [OUTPORT_QUANT-1:0]                             r_candidateList_stored, r_candidateList_out;
    reg     [OUTPORT_QUANT-1:0]                             rin_candidateList_stored;

    reg     [LUT_SIZE*LINKS_PER_ROUTER-1:0]                 r_routing_lut;
    reg     [LUT_SIZE-1:0]                                  routing_lut_array [0:LINKS_PER_ROUTER-1];

    wire    [MOD_X_COORD_SIZE-1:0]                          trg_mod_x;
    wire    [MOD_Y_COORD_SIZE-1:0]                          trg_mod_y;
    wire    [MOD_Z_COORD_SIZE-1:0]                          trg_mod_z;
    wire    [MOD_X_COORD_SIZE-1:0]                          trg_mod_x_OffChip;
    wire    [MOD_Y_COORD_SIZE-1:0]                          trg_mod_y_OffChip;
    wire    [MOD_Z_COORD_SIZE-1:0]                          trg_mod_z_OffChip;

    wire    [NOC_CHIPID_SIZE-1:0]                           trg_chipID;


    reg     go_home;
    reg     go_left;
    reg     go_right;
    reg     go_up;
    reg     go_down;
    reg     go_OnTemp_offchip;
    reg     go_OnTemp_left;
    reg     go_OnTemp_right;
    reg     go_OnTemp_up;
    reg     go_OnTemp_down;
    reg     go_OffTemp_left;
    reg     go_OffTemp_right;
    reg     go_OffTemp_up;
    reg     go_OffTemp_down;

    reg     [2:0] routing_lut_bit_sel;



    assign trg_mod_z  = header_i[MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1:CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];

    assign r_routing_lut_o  = r_routing_lut;
    assign candidateList_o  = r_candidateList_out;

    always @* begin
        if( burst_active_i) begin
            r_candidateList_out      = r_candidateList_stored;
        end else begin
            r_candidateList_out      = rin_candidateList & {OUTPORT_QUANT{flitReady_i}};
        end
    end

    always @(posedge clk_i, negedge rstq_i) begin
        if(rstq_i == 1'b0) begin
            r_candidateList_stored  <= {OUTPORT_QUANT{1'b0}};
        end else begin
            r_candidateList_stored  <= rin_candidateList_stored;
        end
    end

    always @* begin
        rin_candidateList_stored   = r_candidateList_stored;
        if(burst_active_i==0) begin
            rin_candidateList_stored      = rin_candidateList;
        end else begin
            rin_candidateList_stored      = r_candidateList_stored;
        end
    end

    always @(posedge clk_i, negedge rstq_i) begin: routing_lut_register
        if (rstq_i == 1'b0) begin
            r_routing_lut   <=  LUT_RESET_VALUE;
        end else begin
            if (lut_update_en_i == 1'b1) begin
                r_routing_lut   <=  rin_routing_lut_i;
            end
        end
    end


    assign trg_chipID   = header_i[CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1:0];

    assign trg_mod_x    = header_i[MOD_X_COORD_SIZE+MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1 : MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];
    assign trg_mod_y    = header_i[MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE-1 : MOD_Z_COORD_SIZE+CHIP_X_COORD_SIZE+CHIP_Y_COORD_SIZE+CHIP_Z_COORD_SIZE];


    assign trg_mod_x_OffChip = MODID_ETH[MOD_X_COORD_SIZE+MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE-1 : MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE];
    assign trg_mod_y_OffChip = MODID_ETH[MOD_Y_COORD_SIZE+MOD_Z_COORD_SIZE-1 : MOD_Z_COORD_SIZE];
    assign trg_mod_z_OffChip = MODID_ETH[MOD_Z_COORD_SIZE-1 : 0];


    always @* begin: tempOff_xy_set_direction
        if (trg_chipID == home_chipid_i) begin
            go_OffTemp_left     = 1'b0;
            go_OffTemp_right    = 1'b0;
            go_OffTemp_up       = 1'b0;
            go_OffTemp_down     = 1'b0;
        end else begin
            if (trg_mod_x_OffChip < DIRECTION_ADD_X) begin
                go_OffTemp_left     = 1'b1;
                go_OffTemp_right    = 1'b0;
            end else if (trg_mod_x_OffChip > DIRECTION_ADD_X) begin
                go_OffTemp_left     = 1'b0;
                go_OffTemp_right    = 1'b1;
            end else begin
                go_OffTemp_left     = 1'b0;
                go_OffTemp_right    = 1'b0;
            end
            if (trg_mod_y_OffChip < DIRECTION_ADD_Y) begin
                go_OffTemp_up       = 1'b0;
                go_OffTemp_down     = 1'b1;
            end else if (trg_mod_y_OffChip > DIRECTION_ADD_Y) begin
                go_OffTemp_up       = 1'b1;
                go_OffTemp_down     = 1'b0;
            end else begin
                go_OffTemp_up       = 1'b0;
                go_OffTemp_down     = 1'b0;
            end
        end
    end


    always @* begin: OnChip_set_direction
        if (trg_chipID != home_chipid_i) begin
            go_OnTemp_offchip   = 1'b1;
            go_OnTemp_left      = 1'b0;
            go_OnTemp_right     = 1'b0;
            go_OnTemp_up        = 1'b0;
            go_OnTemp_down      = 1'b0;
        end else begin
            go_OnTemp_offchip = 1'b0;
            if (trg_mod_x < DIRECTION_ADD_X) begin
                go_OnTemp_left      = 1'b1;
                go_OnTemp_right = 1'b0;
            end else if (trg_mod_x > DIRECTION_ADD_X) begin
                go_OnTemp_left      = 1'b0;
                go_OnTemp_right = 1'b1;
            end else begin
                go_OnTemp_left      = 1'b0;
                go_OnTemp_right = 1'b0;
            end
            if (trg_mod_y < DIRECTION_ADD_Y) begin
                go_OnTemp_up        = 1'b0;
                go_OnTemp_down      = 1'b1;
            end else if (trg_mod_y > DIRECTION_ADD_Y) begin
                go_OnTemp_up        = 1'b1;
                go_OnTemp_down      = 1'b0;
            end else begin
                go_OnTemp_up        = 1'b0;
                go_OnTemp_down      = 1'b0;
            end
        end
    end

    always @* begin: Final_set_direction
        if (trg_chipID == home_chipid_i) begin
            go_left    = go_OnTemp_left;
            go_right   = go_OnTemp_right;
            go_up      = go_OnTemp_up;
            go_down    = go_OnTemp_down;
            go_home    = ~ (go_OnTemp_left | go_OnTemp_right | go_OnTemp_up | go_OnTemp_down);
        end else begin
            go_left    = go_OffTemp_left;
            go_right   = go_OffTemp_right;
            go_up      = go_OffTemp_up;
            go_down    = go_OffTemp_down;
            go_home    = ~ (go_OffTemp_left | go_OffTemp_right | go_OffTemp_up | go_OffTemp_down);
        end
    end



    always @* begin: set_lut_addr
        case ({go_left, go_right, go_up, go_down})
            4'b0010:    routing_lut_bit_sel = 3'd7;
            4'b0110:    routing_lut_bit_sel = 3'd6;
            4'b0100:    routing_lut_bit_sel = 3'd5;
            4'b0101:    routing_lut_bit_sel = 3'd4;
            4'b0001:    routing_lut_bit_sel = 3'd3;
            4'b1001:    routing_lut_bit_sel = 3'd2;
            4'b1000:    routing_lut_bit_sel = 3'd1;
            4'b1010:    routing_lut_bit_sel = 3'd0;
            default:    routing_lut_bit_sel = 3'd0;
        endcase
    end

    genvar i;
    generate
        for (i=0; i<OUTPORT_QUANT; i=i+1) begin: set_possible_outPort_remote
            always @* begin
                rin_candidateList[i] = 1'b0;


                if (i < MODULES_PER_ROUTER) begin
                    if (go_home == 1'b1) begin
                        if (go_OnTemp_offchip == 1'b1) begin
                            if (i == trg_mod_z_OffChip) begin
                                rin_candidateList[i] = 1'b1;
                            end
                        end else if (i == trg_mod_z) begin
                            rin_candidateList[i] = 1'b1;
                        end
                    end
                end


                else if (i < (OUTPORT_QUANT-1)) begin
                    if (go_home == 1'b0) begin
                        rin_candidateList[i] = routing_lut_array[i-MODULES_PER_ROUTER][routing_lut_bit_sel];
                    end
                end


                else begin
                    if ((go_home == 1'b1) && (trg_mod_z == {MOD_Z_COORD_SIZE{1'b1}})) begin
                        rin_candidateList[i] = 1'b1;
                    end
                end
            end
        end
    endgenerate


    genvar j;
    generate
        for (j=0; j<LINKS_PER_ROUTER; j=j+1) begin: lut_vector2array
            always @* begin
                routing_lut_array [j]   = r_routing_lut [LUT_SIZE*(j+1)-1:LUT_SIZE*j];
            end
        end
    endgenerate

endmodule