data/full_repos/permissive/421450529/ADD4.v
data/verilator_xmls/bf49de0c-05af-4238-81a8-4345d30eeba0.xml
module ADD(
     input[31:0] pc,
	  input[31:0] num,
	  output[31:0] PCplus
    );

   assign PCplus=pc+num;
endmodule
module ADD(
     input[31:0] pc,
	  input[31:0] num,
	  output[31:0] PCplus
    );


   assign PCplus=pc+num;
endmodule