data/full_repos/permissive/486598419/6.6/pcreg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   # 100 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/486598419/6.6/pcreg_tb.v:30: Cannot find file containing module: \'pcreg\'\npcreg uut(clk,rst,ena,data_in,data_out);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/pcreg\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/pcreg.v\n             data/full_repos/permissive/486598419/6.6,data/full_repos/permissive/486598419/pcreg.sv\n             pcreg\n             pcreg.v\n             pcreg.sv\n             obj_dir/pcreg\n             obj_dir/pcreg.v\n             obj_dir/pcreg.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pcreg_tb();
    reg clk;
    reg rst;
    reg ena;
    reg [31:0] data_in;
    wire [31:0] data_out;

pcreg uut(clk,rst,ena,data_in,data_out);
always
begin
   # 100 clk = ~clk;
end

initial
    begin
    clk=1;
    rst=1;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=1;
    ena=0;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
     
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
      
    rst=0;
    ena=0;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    end
    
endmodule
module pcreg_tb();

    reg clk;
    reg rst;
    reg ena;
    reg [31:0] data_in;
    wire [31:0] data_out;

pcreg uut(clk,rst,ena,data_in,data_out);
always
begin
   # 100 clk = ~clk;
end

initial
    begin
    clk=1;
    rst=1;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=1;
    ena=0;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
     
    rst=0;
    ena=1;
    data_in=32'b00000000_00000000_00000000_00000011;
    #100;
      
    rst=0;
    ena=0;
    data_in=32'b00000000_00000000_00000000_00000111;
    #100;
    end
    
endmodule