data/full_repos/permissive/504677412/src/stream_downsizer.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/stream_downsizer.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input [DW_OUT*SCALE-1:0]          s_data_i,\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/stream_downsizer.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output [DW_OUT-1:0]               m_data_o,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/stream_downsizer.v:20: Little bit endian vector: MSB < LSB of bit range: -1:0\n  reg  [$clog2(DW_OUT*SCALE)-1:0]   idx;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/504677412/src/stream_downsizer.v:21: Little bit endian vector: MSB < LSB of bit range: -1:0\n  reg  [DW_OUT*SCALE-1:0]           data;\n       ^\n%Error: Internal Error: data/full_repos/permissive/504677412/src/stream_downsizer.v:33: ../V3Width.cpp:3809: Under node SEL has no expected width?? Missing Visitor func?\n                                                                                      : ... In instance stream_downsizer\n  assign m_data_o = data[idx*DW_OUT+:DW_OUT];\n                        ^\n'
module stream_downsizer #(
  parameter                         DW_OUT = 0,
  parameter                         SCALE = 0
)(
  input                             clk,
  input                             rst,

  input [DW_OUT*SCALE-1:0]          s_data_i,
  input                             s_valid_i,
  output                            s_ready_o,

  output [DW_OUT-1:0]               m_data_o,
  output                            m_valid_o,
  input                             m_ready_i
);

  reg                               rst_r;
  
  reg                               full;
  reg  [$clog2(DW_OUT*SCALE)-1:0]   idx;
  reg  [DW_OUT*SCALE-1:0]           data;
  
  wire                              wr;
  wire                              rd;
  wire                              wrap;
  
  assign wr = s_valid_i & s_ready_o;
  assign rd = m_valid_o & m_ready_i;
  assign wrap = (idx == SCALE-1) & rd;
  
  assign s_ready_o = (((idx == 0) & !full) | (wrap)) & !rst_r;
  
  assign m_data_o = data[idx*DW_OUT+:DW_OUT];
  assign m_valid_o = full;
  
   always @(posedge clk) begin
     if (wr & !rd)
       full <= 1'b1;
     else if (!wr & rd & wrap)
       full <= 1'b0;

     if (wr)
       data <= s_data_i;
     
     if (rd) begin
       if(wrap)
         idx <= 0;
       else
         idx <= idx + 1'b1;
     end
     
     rst_r <= 1'b0;
     
     if (rst) begin
       idx <= 0;
       full <= 1'b0;
       rst_r <= 1'b1;

     end
   end
endmodule
module stream_downsizer #(
  parameter                         DW_OUT = 0,
  parameter                         SCALE = 0
)(
  input                             clk,
  input                             rst,

  input [DW_OUT*SCALE-1:0]          s_data_i,
  input                             s_valid_i,
  output                            s_ready_o,

  output [DW_OUT-1:0]               m_data_o,
  output                            m_valid_o,
  input                             m_ready_i
);


  reg                               rst_r;
  
  reg                               full;
  reg  [$clog2(DW_OUT*SCALE)-1:0]   idx;
  reg  [DW_OUT*SCALE-1:0]           data;
  
  wire                              wr;
  wire                              rd;
  wire                              wrap;
  
  assign wr = s_valid_i & s_ready_o;
  assign rd = m_valid_o & m_ready_i;
  assign wrap = (idx == SCALE-1) & rd;
  
  assign s_ready_o = (((idx == 0) & !full) | (wrap)) & !rst_r;
  
  assign m_data_o = data[idx*DW_OUT+:DW_OUT];
  assign m_valid_o = full;
  
   always @(posedge clk) begin
     if (wr & !rd)
       full <= 1'b1;
     else if (!wr & rd & wrap)
       full <= 1'b0;

     if (wr)
       data <= s_data_i;
     
     if (rd) begin
       if(wrap)
         idx <= 0;
       else
         idx <= idx + 1'b1;
     end
     
     rst_r <= 1'b0;
     
     if (rst) begin
       idx <= 0;
       full <= 1'b0;
       rst_r <= 1'b1;

     end
   end
endmodule