data/full_repos/permissive/435516446/MIPS/EM_MEM_Register.v
data/verilator_xmls/8fbc0baa-a544-45f7-81a1-0458c9e5099f.xml
module EM_MEM_Register(
    input clock,
    input wire hit,
    input [31:0] branchTarget,
    input zeroFlag,
    input [31:0] ALUResult,
    input [31:0] readData2,
    input [4:0] writeReg,
    input MemRead,
    input MemWrite,
    input Branch,
    input RegWrite,
    input MemToReg,
    input jumpSignal,
    output reg [31:0] branchTargetOut,
    output reg zeroFlagOut,
    output reg [31:0] ALUResultOut,
    output reg [31:0] readData2Out,
    output reg [4:0] writeRegOut,
    output reg MemReadOut,
    output reg MemWriteOut,
    output reg BranchOut,
    output reg RegWriteOut,
    output reg MemToRegOut,
    output wire hitOut,
    output reg jumpSignalOut
    );

always @(negedge clock) begin
	if (hit) begin
		branchTargetOut = branchTarget;
		zeroFlagOut = zeroFlag;
		ALUResultOut = ALUResult;
		readData2Out = readData2;
		writeRegOut = writeReg;
		MemReadOut = MemRead;
		MemWriteOut = MemWrite;
		BranchOut = Branch;
		RegWriteOut = RegWrite;
		MemToRegOut = MemToReg;
		jumpSignalOut = jumpSignal;
	end
end
assign hitOut = hit;




endmodule
module EM_MEM_Register(
    input clock,
    input wire hit,
    input [31:0] branchTarget,
    input zeroFlag,
    input [31:0] ALUResult,
    input [31:0] readData2,
    input [4:0] writeReg,
    input MemRead,
    input MemWrite,
    input Branch,
    input RegWrite,
    input MemToReg,
    input jumpSignal,
    output reg [31:0] branchTargetOut,
    output reg zeroFlagOut,
    output reg [31:0] ALUResultOut,
    output reg [31:0] readData2Out,
    output reg [4:0] writeRegOut,
    output reg MemReadOut,
    output reg MemWriteOut,
    output reg BranchOut,
    output reg RegWriteOut,
    output reg MemToRegOut,
    output wire hitOut,
    output reg jumpSignalOut
    );


always @(negedge clock) begin
	if (hit) begin
		branchTargetOut = branchTarget;
		zeroFlagOut = zeroFlag;
		ALUResultOut = ALUResult;
		readData2Out = readData2;
		writeRegOut = writeReg;
		MemReadOut = MemRead;
		MemWriteOut = MemWrite;
		BranchOut = Branch;
		RegWriteOut = RegWrite;
		MemToRegOut = MemToReg;
		jumpSignalOut = jumpSignal;
	end
end
assign hitOut = hit;




endmodule