data/full_repos/permissive/486812922/src/pc.v
data/verilator_xmls/07ee4942-1602-47a1-8d14-603ede29e041.xml
module pc(NPC, Clk, Reset, PC);

input [31: 0] NPC;

input Clk;

input Reset;

output reg [31: 0] PC;


initial begin
    PC = 32'h0000_3000;
end

always @ (posedge Clk or posedge Reset) begin
    if (Reset == 1'b1) begin

        PC <= 32'h0000_3000;
    end
    else begin

        PC <= NPC;
    end
end

endmodule
module pc(NPC, Clk, Reset, PC);


input [31: 0] NPC;

input Clk;

input Reset;

output reg [31: 0] PC;


initial begin
    PC = 32'h0000_3000;
end

always @ (posedge Clk or posedge Reset) begin
    if (Reset == 1'b1) begin

        PC <= 32'h0000_3000;
    end
    else begin

        PC <= NPC;
    end
end

endmodule