data/full_repos/permissive/451577625/system/system.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/system.v:197: Unsupported: Ignoring delay on this delayed statement.\n   #10 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/451577625/system/system.v:63: Cannot find file containing module: \'datapath\'\n datapath path (.clk (w_clk),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/datapath\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/datapath.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/451577625/system/system.v:98: Cannot find file containing module: \'memory\'\n memory RAM (.clock (w_clk),\n ^~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:105: Cannot find file containing module: \'select_encode_logic\'\n select_encode_logic sel_enc_logic(.in_gra (w_gra),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:116: Cannot find file containing module: \'con_ff_logic\'\n con_ff_logic CON_FF(.clk (w_clk),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:122: Cannot find file containing module: \'control_unit\'\n control_unit control (.clk (w_clk),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:161: Cannot find file containing module: \'seven_segment_display\'\n seven_segment_display ssd_0 (.clk (w_clk),\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:165: Cannot find file containing module: \'seven_segment_display\'\n seven_segment_display ssd_1 (.clk (w_clk),\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/system.v:169: Cannot find file containing module: \'clock_divider\'\n clock_divider clk_div(.in_clock (clk),\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/system.v:187: Input port connection \'inport_data\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'inport_data\' generates 32 bits.\n                                                                        : ... In instance system_tb\n  .inport_data (inport_data),\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/system.v:189: Output port connection \'outport_data\' expects 14 bits on the pin connection, but pin connection\'s VARREF \'outport_data\' generates 32 bits.\n                                                                        : ... In instance system_tb\n  .outport_data (outport_data));\n   ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module system_tb;
	reg clk, reset, stop;
	reg [31:0] inport_data;
	
	wire run;
	wire [31:0] outport_data;
	
	system DUT (.clk (clk),
		.reset (reset),
		.stop (stop),
		.inport_data (inport_data),
		.run (run),
		.outport_data (outport_data));
	
	initial begin
		clk = 0;
		reset = 0;
		stop = 1;
		inport_data = 32'h88;
		forever begin 
			#10 clk = ~clk;
		end
	end
	
	always @(posedge clk) begin
		reset = 1;
	end
endmodule
module system_tb;

	reg clk, reset, stop;
	reg [31:0] inport_data;
	
	wire run;
	wire [31:0] outport_data;
	
	system DUT (.clk (clk),
		.reset (reset),
		.stop (stop),
		.inport_data (inport_data),
		.run (run),
		.outport_data (outport_data));
	
	initial begin
		clk = 0;
		reset = 0;
		stop = 1;
		inport_data = 32'h88;
		forever begin 
			#10 clk = ~clk;
		end
	end
	
	always @(posedge clk) begin
		reset = 1;
	end
endmodule