data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #(4*T);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(4*T);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #(T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #(9*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #(T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #(8*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #(8*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #(15*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #(6*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #(2*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #(11*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #(16*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #(15*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #(1*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #(2*T)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #(T*70);\n  ^\n%Error: data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00/SimTest.v:17: Cannot find file containing module: \'DualEdgeMoore\'\n DualEdgeMoore dualEdge( clk, reset, sig, anyEdge );\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00,data/full_repos/permissive/472097485/DualEdgeMoore\n             data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00,data/full_repos/permissive/472097485/DualEdgeMoore.v\n             data/full_repos/permissive/472097485/Chu05/DualEdgeMoore_00,data/full_repos/permissive/472097485/DualEdgeMoore.sv\n             DualEdgeMoore\n             DualEdgeMoore.v\n             DualEdgeMoore.sv\n             obj_dir/DualEdgeMoore\n             obj_dir/DualEdgeMoore.v\n             obj_dir/DualEdgeMoore.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SimTest();

	localparam T = 1;


	reg clk, reset, sig;


	wire anyEdge;


	DualEdgeMoore dualEdge( clk, reset, sig, anyEdge );

	always
	begin
		clk = 1'b1;
		#(4*T);
		clk = 1'b0;
		#(4*T);
	end

	initial begin

		reset = 1'b1;
		sig = 1'b0;
		#(T)
		reset = 1'b0;
		#(T)
		

		#(9*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(6*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;
		

		#(11*T)
		sig = ~sig;
		

		#(16*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;


		#(T*70);
        

		$stop;
	end
      
endmodule
module SimTest();


	localparam T = 1;


	reg clk, reset, sig;


	wire anyEdge;


	DualEdgeMoore dualEdge( clk, reset, sig, anyEdge );

	always
	begin
		clk = 1'b1;
		#(4*T);
		clk = 1'b0;
		#(4*T);
	end

	initial begin

		reset = 1'b1;
		sig = 1'b0;
		#(T)
		reset = 1'b0;
		#(T)
		

		#(9*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;
		

		#(8*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(6*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;
		

		#(11*T)
		sig = ~sig;
		

		#(16*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		

		#(15*T)
		sig = ~sig;
		
		#(1*T)
		sig = ~sig;
		
		#(2*T)
		sig = ~sig;


		#(T*70);
        

		$stop;
	end
      
endmodule