data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, fn_sw_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=0;b<=0;sel<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=0;b<=1;sel<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=0;b<=1;sel<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=1;b<=0;sel<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=1;b<=0;sel<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=1;b<=1;sel<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 a<=1;b<=1;sel<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw/fn_sw_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fn_sw_tb;
reg a,b,sel;
wire y;
fn_sw fn_sw(
    .a(a),
    .b(b),
    .sel(sel),
    .y(y)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, fn_sw_tb);
    end


initial begin
        a<=0;b<=0;sel<=0;
    #10 a<=0;b<=0;sel<=1;
    #10 a<=0;b<=1;sel<=0;
    #10 a<=0;b<=1;sel<=1;
    #10 a<=1;b<=0;sel<=0;
    #10 a<=1;b<=0;sel<=1;
    #10 a<=1;b<=1;sel<=0;
    #10 a<=1;b<=1;sel<=1;
    #10 $finish;
end

endmodule
module fn_sw_tb;

reg a,b,sel;
wire y;
fn_sw fn_sw(
    .a(a),
    .b(b),
    .sel(sel),
    .y(y)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, fn_sw_tb);
    end


initial begin
        a<=0;b<=0;sel<=0;
    #10 a<=0;b<=0;sel<=1;
    #10 a<=0;b<=1;sel<=0;
    #10 a<=0;b<=1;sel<=1;
    #10 a<=1;b<=0;sel<=0;
    #10 a<=1;b<=0;sel<=1;
    #10 a<=1;b<=1;sel<=0;
    #10 a<=1;b<=1;sel<=1;
    #10 $finish;
end

endmodule