data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/proc_02.v
data/verilator_xmls/7bbce1ae-11c7-4d38-a639-8973039cdf0d.xml
module test(input D, C, R, RV,
            output reg Q);
    always @(posedge C, posedge R)
        if (R)
	    Q <= RV;
	else
	    Q <= D;
endmodule
module test(input D, C, R, RV,
            output reg Q);

    always @(posedge C, posedge R)
        if (R)
	    Q <= RV;
	else
	    Q <= D;
endmodule