data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/VectorMul_wrapper.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/VectorMul_wrapper.v:58: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'pol_64bit_address\' generates 7 bits.\n                                                                                                                    : ... In instance VectorMul_wrapper\nassign read_address1 = vec1_pol_base + pol_64bit_address;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/VectorMul_wrapper.v:63: Cannot find file containing module: \'VectorMul\'\nVectorMul VMUL(clk, rst, \n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/VectorMul\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/VectorMul.v\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/VectorMul.sv\n             VectorMul\n             VectorMul.v\n             VectorMul.sv\n             obj_dir/VectorMul\n             obj_dir/VectorMul.v\n             obj_dir/VectorMul.sv\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/VectorMul_wrapper.v:71: Cannot find file containing module: \'poly_mul256_parallel_in2\'\npoly_mul256_parallel_in2 PMUL0(clk, rst_pol_mul, pol_acc_clear, pol_load_coeff4x,\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module VectorMul_wrapper(clk, rst, pol_load_coeff4x,
								s_load_happens_now, read_address, ram_data_out,

								write_address, coeff4x_out, PolMem_wen, 
								vector_mul_done);
input clk, rst;
input pol_load_coeff4x;
output s_load_happens_now;
output [8:0] read_address;
input [63:0] ram_data_out;

output [8:0] write_address;
output [63:0] coeff4x_out;
output PolMem_wen;
output vector_mul_done;

wire rst_pol_mul, pol_acc_clear;
wire [1:0] pol_base_sel;
wire pol_mul_done;	 
wire result_pol_read;
wire [63:0] coeff4x_out;
wire result_pol_read64;
wire [63:0] result_coeff_out64;
wire [7:0] s_address;
wire [6:0] pol_64bit_address;
wire [5:0] PolMem_address;
wire [8:0] read_address1, read_address2;
wire [63:0] pol_64bit_in, s_vec_64;


wire [8:0] vec1_pol_base, vec1_pol_base_coeff4x, vec1_pol_base_64bit, vec2_pol_base;

assign vec1_pol_base_64bit = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd52 : 9'd104; 
assign vec1_pol_base_coeff4x = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd64 : 9'd128; 
assign vec1_pol_base = (pol_load_coeff4x) ? vec1_pol_base_coeff4x : vec1_pol_base_64bit;

assign vec2_pol_base = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd16 : 9'd32;


assign read_address1 = vec1_pol_base + pol_64bit_address;
assign read_address2 = vec2_pol_base + s_address;
assign read_address = (s_load_happens_now) ? read_address2 : read_address1;
assign write_address = {3'd0,PolMem_address};

VectorMul	VMUL(clk, rst, 
						rst_pol_mul, pol_acc_clear, pol_base_sel, 
						pol_mul_done, result_pol_read,
						PolMem_address, PolMem_wen, vector_mul_done);

assign pol_64bit_in = ram_data_out;
assign s_vec_64 = ram_data_out;

poly_mul256_parallel_in2 PMUL0(clk, rst_pol_mul, pol_acc_clear, pol_load_coeff4x,
								pol_64bit_address, pol_64bit_in,  
								s_address, s_vec_64, s_load_happens_now,
								result_pol_read, coeff4x_out, pol_mul_done);

								
endmodule
module VectorMul_wrapper(clk, rst, pol_load_coeff4x,
								s_load_happens_now, read_address, ram_data_out,

								write_address, coeff4x_out, PolMem_wen, 
								vector_mul_done);

input clk, rst;
input pol_load_coeff4x;
output s_load_happens_now;
output [8:0] read_address;
input [63:0] ram_data_out;

output [8:0] write_address;
output [63:0] coeff4x_out;
output PolMem_wen;
output vector_mul_done;

wire rst_pol_mul, pol_acc_clear;
wire [1:0] pol_base_sel;
wire pol_mul_done;	 
wire result_pol_read;
wire [63:0] coeff4x_out;
wire result_pol_read64;
wire [63:0] result_coeff_out64;
wire [7:0] s_address;
wire [6:0] pol_64bit_address;
wire [5:0] PolMem_address;
wire [8:0] read_address1, read_address2;
wire [63:0] pol_64bit_in, s_vec_64;


wire [8:0] vec1_pol_base, vec1_pol_base_coeff4x, vec1_pol_base_64bit, vec2_pol_base;

assign vec1_pol_base_64bit = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd52 : 9'd104; 
assign vec1_pol_base_coeff4x = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd64 : 9'd128; 
assign vec1_pol_base = (pol_load_coeff4x) ? vec1_pol_base_coeff4x : vec1_pol_base_64bit;

assign vec2_pol_base = (pol_base_sel==2'd0) ? 9'd0 : (pol_base_sel==2'd1) ? 9'd16 : 9'd32;


assign read_address1 = vec1_pol_base + pol_64bit_address;
assign read_address2 = vec2_pol_base + s_address;
assign read_address = (s_load_happens_now) ? read_address2 : read_address1;
assign write_address = {3'd0,PolMem_address};

VectorMul	VMUL(clk, rst, 
						rst_pol_mul, pol_acc_clear, pol_base_sel, 
						pol_mul_done, result_pol_read,
						PolMem_address, PolMem_wen, vector_mul_done);

assign pol_64bit_in = ram_data_out;
assign s_vec_64 = ram_data_out;

poly_mul256_parallel_in2 PMUL0(clk, rst_pol_mul, pol_acc_clear, pol_load_coeff4x,
								pol_64bit_address, pol_64bit_in,  
								s_address, s_vec_64, s_load_happens_now,
								result_pol_read, coeff4x_out, pol_mul_done);

								
endmodule