data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/gen_syn.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/gen_syn.v:60: Cannot find file containing module: 'fflopxe'\nfflopxe #(1)    linsyn(iclk4d86,rst_,synref,1'b1,insyn);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: Exiting due to 1 error(s)\n"
module gen_syn
    (
     rst_,

     iclk155,
     
     iclk4d86,
     iclk38,

     osyn

     );





input rst_;
input iclk155;

input       iclk4d86;
input       iclk38;
output      osyn;



reg         osyn;



reg [2:0]   shfdet4d86;

wire        pos4d86;
assign      pos4d86 = (shfdet4d86 == 3'b011);

always @(posedge iclk155 or negedge rst_)
    if(!rst_)   shfdet4d86 <= 3'd0;
    else        shfdet4d86 <= {shfdet4d86[1:0],iclk4d86};
       
reg         synref;
always @(posedge iclk155 or negedge rst_)
    if(!rst_)    synref <= 1'b0;
    else if(pos4d86 & ~synref)  synref <= 1'b1;
    else if(pos4d86)            synref <= 1'b0;

wire        insyn;
fflopxe #(1)    linsyn(iclk4d86,rst_,synref,1'b1,insyn);

reg [2:0]   cntph;
always @(posedge iclk38 or negedge rst_)
    if(!rst_)   cntph <= 3'd0;
    else if(insyn)                      cntph <= cntph + 1'b1;
    else if(synref & (cntph == 3'd0))   cntph <= 3'd0;


always @(posedge iclk38 or negedge rst_)
    if(!rst_)   osyn <= 1'b0;
    else if(&cntph)     osyn <= 1'b1;
    else                osyn <= 1'b0;          

endmodule
module gen_syn
    (
     rst_,

     iclk155,
     
     iclk4d86,
     iclk38,

     osyn

     );






input rst_;
input iclk155;

input       iclk4d86;
input       iclk38;
output      osyn;



reg         osyn;



reg [2:0]   shfdet4d86;

wire        pos4d86;
assign      pos4d86 = (shfdet4d86 == 3'b011);

always @(posedge iclk155 or negedge rst_)
    if(!rst_)   shfdet4d86 <= 3'd0;
    else        shfdet4d86 <= {shfdet4d86[1:0],iclk4d86};
       
reg         synref;
always @(posedge iclk155 or negedge rst_)
    if(!rst_)    synref <= 1'b0;
    else if(pos4d86 & ~synref)  synref <= 1'b1;
    else if(pos4d86)            synref <= 1'b0;

wire        insyn;
fflopxe #(1)    linsyn(iclk4d86,rst_,synref,1'b1,insyn);

reg [2:0]   cntph;
always @(posedge iclk38 or negedge rst_)
    if(!rst_)   cntph <= 3'd0;
    else if(insyn)                      cntph <= cntph + 1'b1;
    else if(synref & (cntph == 3'd0))   cntph <= 3'd0;


always @(posedge iclk38 or negedge rst_)
    if(!rst_)   osyn <= 1'b0;
    else if(&cntph)     osyn <= 1'b1;
    else                osyn <= 1'b0;          

endmodule