data/full_repos/permissive/509468557/tools/dsptools/src/main/resources/BBFASinh.v
data/verilator_xmls/af7baaba-2c6b-42a5-bce8-9711316f00b8.xml
module BBFASinh(
    input  [63:0] in,
    output reg [63:0] out
);
  always @* begin
  out = $realtobits($asinh($bitstoreal(in)));
  end
endmodule
module BBFASinh(
    input  [63:0] in,
    output reg [63:0] out
);

  always @* begin
  out = $realtobits($asinh($bitstoreal(in)));
  end
endmodule