data/full_repos/permissive/429737743/sources_1/new/PCIF.v
data/verilator_xmls/012bd750-0f46-4cfd-ae4e-72f609829043.xml
module PCIF(pc_out, 
    enable, npc, init, rst
);
output [31 : 0] pc_out;
input [31 : 0] npc, init;
input enable, rst;
reg [31 : 0] pc_out;
always @(posedge rst) begin
    pc_out <= init;
end
always@(*) begin
    if (enable) begin
        pc_out = npc;
    end
end
endmodule
module PCIF(pc_out, 
    enable, npc, init, rst
);

output [31 : 0] pc_out;
input [31 : 0] npc, init;
input enable, rst;
reg [31 : 0] pc_out;
always @(posedge rst) begin
    pc_out <= init;
end
always@(*) begin
    if (enable) begin
        pc_out = npc;
    end
end
endmodule