data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:244: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/typedef.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/typedef.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/typedef.svh.sv\n             axi/typedef.svh\n             axi/typedef.svh.v\n             axi/typedef.svh.sv\n             obj_dir/axi/typedef.svh\n             obj_dir/axi/typedef.svh.v\n             obj_dir/axi/typedef.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:352: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:260: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    axi_pkg::prot_t pprot;    \n    ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:266: syntax error, unexpected \'}\'\n  } apb_req_t;\n  ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:274: Define or directive not defined: \'`AXI_LITE_TYPEDEF_AW_CHAN_T\'\n  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:274: syntax error, unexpected \'(\'\n  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:275: Define or directive not defined: \'`AXI_LITE_TYPEDEF_W_CHAN_T\'\n  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:276: Define or directive not defined: \'`AXI_LITE_TYPEDEF_B_CHAN_T\'\n  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:277: Define or directive not defined: \'`AXI_LITE_TYPEDEF_AR_CHAN_T\'\n  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:278: Define or directive not defined: \'`AXI_LITE_TYPEDEF_R_CHAN_T\'\n  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:279: Define or directive not defined: \'`AXI_LITE_TYPEDEF_REQ_T\'\n  `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:280: Define or directive not defined: \'`AXI_LITE_TYPEDEF_RESP_T\'\n  `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)\n  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:284: syntax error, unexpected \'[\', expecting IDENTIFIER\n  apb_req_t  [NoApbSlaves-1:0] apb_req;\n             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:287: syntax error, unexpected ::, expecting IDENTIFIER\n  axi_pkg::xbar_rule_32_t [NoApbSlaves-1:0] addr_map;\n         ^~\n                                                                                                  : ... Perhaps \'axi_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:298: syntax error, unexpected ::\n    .rule_t          ( axi_pkg::xbar_rule_32_t )\n                              ^~\n%Error: Internal Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/axi_synth_bench.sv:246: ../V3ParseSym.h:114: Symbols suggest ending STRUCTDTYPE but parser thinks ending MODULE \'synth_axi_lite_to_apb\'\nmodule synth_axi_lite_to_apb #(\n       ^~~~~~~~~~~~~~~~~~~~~\n'
module synth_axi_lite_mailbox #(
  parameter int unsigned MAILBOX_DEPTH = 32'd1,
  parameter bit          IRQ_EDGE_TRIG = 1'b0,
  parameter bit          IRQ_ACT_HIGH  = 1'b0
) (
  input logic clk_i,
  input logic rst_ni
);
  typedef logic [32'd32-1:0]   addr_t;

  AXI_LITE #(
    .AXI_ADDR_WIDTH (32'd32),
    .AXI_DATA_WIDTH (32'd32)
  ) slv [1:0] ();

  logic        test;
  logic  [1:0] irq;
  addr_t [1:0] base_addr;

  axi_lite_mailbox_intf #(
    .MAILBOX_DEPTH  ( MAILBOX_DEPTH  ),
    .IRQ_EDGE_TRIG  ( IRQ_EDGE_TRIG  ),
    .IRQ_ACT_HIGH   ( IRQ_ACT_HIGH   ),
    .AXI_ADDR_WIDTH ( 32'd32         ),
    .AXI_DATA_WIDTH ( 32'd32         )
  ) i_axi_lite_mailbox (
    .clk_i       ( clk_i     ),
    .rst_ni      ( rst_ni    ),
    .test_i      ( test      ),

    .slv         ( slv       ),
    .irq_o       ( irq       ),
    .base_addr_i ( base_addr )
  );
endmodule
module synth_axi_lite_mailbox #(
  parameter int unsigned MAILBOX_DEPTH = 32'd1,
  parameter bit          IRQ_EDGE_TRIG = 1'b0,
  parameter bit          IRQ_ACT_HIGH  = 1'b0
) (
  input logic clk_i,
  input logic rst_ni
);

  typedef logic [32'd32-1:0]   addr_t;

  AXI_LITE #(
    .AXI_ADDR_WIDTH (32'd32),
    .AXI_DATA_WIDTH (32'd32)
  ) slv [1:0] ();

  logic        test;
  logic  [1:0] irq;
  addr_t [1:0] base_addr;

  axi_lite_mailbox_intf #(
    .MAILBOX_DEPTH  ( MAILBOX_DEPTH  ),
    .IRQ_EDGE_TRIG  ( IRQ_EDGE_TRIG  ),
    .IRQ_ACT_HIGH   ( IRQ_ACT_HIGH   ),
    .AXI_ADDR_WIDTH ( 32'd32         ),
    .AXI_DATA_WIDTH ( 32'd32         )
  ) i_axi_lite_mailbox (
    .clk_i       ( clk_i     ),
    .rst_ni      ( rst_ni    ),
    .test_i      ( test      ),

    .slv         ( slv       ),
    .irq_o       ( irq       ),
    .base_addr_i ( base_addr )
  );
endmodule