data/full_repos/permissive/459421171/Pipelined/execute_new.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:416: Little bit endian vector: MSB < LSB of bit range: 0:63\ninput[0:63] x,y;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:417: Little bit endian vector: MSB < LSB of bit range: 0:63\noutput[0:63]z;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module twocomp(x ,y);
input signed[63:0] x;
output signed[63:0] y;
wire signed[63:0] w;
wire c_out;
genvar i;
generate 
for(i=0 ; i<64 ; i = i+1) 
begin
not (w[i] , x[i]);
end
endgenerate
ADD twocomp1(w,64'b1,y,c_out);
endmodule
module twocomp(x ,y);

input signed[63:0] x;
output signed[63:0] y;
wire signed[63:0] w;
wire c_out;
genvar i;
generate 
for(i=0 ; i<64 ; i = i+1) 
begin
not (w[i] , x[i]);
end
endgenerate
ADD twocomp1(w,64'b1,y,c_out);
endmodule