data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:26: Cannot find include file: ../../../../lib/axi4lite_sv/axi_lite.vh\n  `include "../../../../lib/axi4lite_sv/axi_lite.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd,data/full_repos/permissive/447976230/../../../../lib/axi4lite_sv/axi_lite.vh.sv\n             ../../../../lib/axi4lite_sv/axi_lite.vh\n             ../../../../lib/axi4lite_sv/axi_lite.vh.v\n             ../../../../lib/axi4lite_sv/axi_lite.vh.sv\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh.v\n             obj_dir/../../../../lib/axi4lite_sv/axi_lite.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:37: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:37: syntax error, unexpected \',\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end\n                                                 ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:38: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:39: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:40: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:41: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:42: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:43: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:44: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:45: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:46: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:47: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:48: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:49: Define or directive not defined: \'`AXI4LITE_ASSIGN\'\n  always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:53: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:56: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:59: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:62: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:66: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:69: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:72: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:75: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:79: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:82: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:85: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:88: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3])\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv:92: Define or directive not defined: \'`AXI4LITE_PORT_ASSIGN_NR\'\n        `AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v)\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module axi_interconnect_eth (

  AxiLiteIf.master  m_axi_dma[3:0],
  AxiLiteIf.master  m_axi_misc[3:0],

  AxiLiteIf.master  m_axi_mac[3:0],

  AxiLiteIf.slave   s_axi_eth
);




  `include "../../../../lib/axi4lite_sv/axi_lite.vh"
  AxiLiteIf_v #(32,40)
    m_axi_dma_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    m_axi_misc_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    m_axi_mac_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    s_axi_eth_v(.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));


  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end

  axi_interconnect_eth_bd axi_interconnect_eth_bd_i
       (
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0])
        .m_axi_dma0_arprot(),
        .m_axi_dma0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1])
        .m_axi_dma1_arprot(),
        .m_axi_dma1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2])
        .m_axi_dma2_arprot(),
        .m_axi_dma2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3])
        .m_axi_dma3_arprot(),
        .m_axi_dma3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0])
        .m_axi_mac0_arprot(),
        .m_axi_mac0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1])
        .m_axi_mac1_arprot(),
        .m_axi_mac1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2])
        .m_axi_mac2_arprot(),
        .m_axi_mac2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3])
        .m_axi_mac3_arprot(),
        .m_axi_mac3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0])
        .m_axi_misc0_arprot(),
        .m_axi_misc0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1])
        .m_axi_misc1_arprot(),
        .m_axi_misc1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2])
        .m_axi_misc2_arprot(),
        .m_axi_misc2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3])
        .m_axi_misc3_arprot(),
        .m_axi_misc3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v)
        .s_axi_eth_arprot(3'b0),
        .s_axi_eth_awprot(3'b0),
        .clk40(s_axi_eth.clk),
        .clk40_rstn(!s_axi_eth.rst));

endmodule
module axi_interconnect_eth (

  AxiLiteIf.master  m_axi_dma[3:0],
  AxiLiteIf.master  m_axi_misc[3:0],

  AxiLiteIf.master  m_axi_mac[3:0],

  AxiLiteIf.slave   s_axi_eth
);





  `include "../../../../lib/axi4lite_sv/axi_lite.vh"
  AxiLiteIf_v #(32,40)
    m_axi_dma_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    m_axi_misc_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    m_axi_mac_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
  AxiLiteIf_v #(32,40)
    s_axi_eth_v(.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));


  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end
  always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end
  always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end

  axi_interconnect_eth_bd axi_interconnect_eth_bd_i
       (
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0])
        .m_axi_dma0_arprot(),
        .m_axi_dma0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1])
        .m_axi_dma1_arprot(),
        .m_axi_dma1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2])
        .m_axi_dma2_arprot(),
        .m_axi_dma2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3])
        .m_axi_dma3_arprot(),
        .m_axi_dma3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0])
        .m_axi_mac0_arprot(),
        .m_axi_mac0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1])
        .m_axi_mac1_arprot(),
        .m_axi_mac1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2])
        .m_axi_mac2_arprot(),
        .m_axi_mac2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3])
        .m_axi_mac3_arprot(),
        .m_axi_mac3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0])
        .m_axi_misc0_arprot(),
        .m_axi_misc0_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1])
        .m_axi_misc1_arprot(),
        .m_axi_misc1_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2])
        .m_axi_misc2_arprot(),
        .m_axi_misc2_awprot(),
        `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3])
        .m_axi_misc3_arprot(),
        .m_axi_misc3_awprot(),

        `AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v)
        .s_axi_eth_arprot(3'b0),
        .s_axi_eth_awprot(3'b0),
        .clk40(s_axi_eth.clk),
        .clk40_rstn(!s_axi_eth.rst));

endmodule