data/full_repos/permissive/509809169/Verilog Language/Basics/declaring wires.v
1: b'%Error: Cannot find file containing module: Language/Basics,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Basics,data/full_repos/permissive/509809169.sv\n             Language/Basics,data/full_repos/permissive/509809169\n             Language/Basics,data/full_repos/permissive/509809169.v\n             Language/Basics,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Basics,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Basics/declaring\n%Error: Cannot find file containing module: wires.v\n%Error: Exiting due to 4 error(s)\n'
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
	wire w1,w2;
    assign w1=a&b;
    assign w2=c&d;
    assign out=w1|w2;
    assign out_n=!out;
endmodule
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );
 
	wire w1,w2;
    assign w1=a&b;
    assign w2=c&d;
    assign out=w1|w2;
    assign out_n=!out;
endmodule