data/full_repos/permissive/418819021/lab-05/rom.v
data/verilator_xmls/89302ac3-30a3-4d29-a83a-13c06d2a72e3.xml
module rom #(
    parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 8
) (
    input  wire                      clk ,
    input  wire     [ADDR_WIDTH-1:0] addr,
    output      reg [DATA_WIDTH-1:0] data
);

    reg [DATA_WIDTH-1:0] value;

    always @* begin
        case (addr)

            0: value = 16'b1110000000000101;

            1: value = 16'b1100000000000010;

            2: value = 16'b1110000000011111;

            3: value = 16'b1001010100001000;

            4: value = 16'b1110000000011010;

            5: value = 16'b1101111111111100;

            6: value = 16'b1110000100100100;
            default: value = 16'b0000000000000000;
        endcase
    end

    always @(negedge clk) begin
        data <= value;
    end

endmodule
module rom #(
    parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 8
) (
    input  wire                      clk ,
    input  wire     [ADDR_WIDTH-1:0] addr,
    output      reg [DATA_WIDTH-1:0] data
);


    reg [DATA_WIDTH-1:0] value;

    always @* begin
        case (addr)

            0: value = 16'b1110000000000101;

            1: value = 16'b1100000000000010;

            2: value = 16'b1110000000011111;

            3: value = 16'b1001010100001000;

            4: value = 16'b1110000000011010;

            5: value = 16'b1101111111111100;

            6: value = 16'b1110000100100100;
            default: value = 16'b0000000000000000;
        endcase
    end

    always @(negedge clk) begin
        data <= value;
    end

endmodule