data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Q8_ design a mealy FSM.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Q8_\n%Error: Cannot find file containing module: design\n%Error: Cannot find file containing module: a\n%Error: Cannot find file containing module: mealy\n%Error: Cannot find file containing module: FSM.v\n%Error: Exiting due to 9 error(s)\n'
module top_module (
    input clk,
    input aresetn,
    input x,
    output z ); 

    parameter a=0,b=1,c=2,d=3;
    reg [1:0] state,next;
    always @(*) begin
        case(state)
            a: next = x?b:a;
            b: next = x?b:c;
            c: next = x?d:a;
            d: next = x?b:c;
        endcase
    end
    
    always @(posedge clk or negedge aresetn) begin
        if(!aresetn) state<=a;
        else state<=next;
    end
    
    assign z = (state==c)&& x;
    
endmodule
module top_module (
    input clk,
    input aresetn,
    input x,
    output z );
 

    parameter a=0,b=1,c=2,d=3;
    reg [1:0] state,next;
    always @(*) begin
        case(state)
            a: next = x?b:a;
            b: next = x?b:c;
            c: next = x?d:a;
            d: next = x?b:c;
        endcase
    end
    
    always @(posedge clk or negedge aresetn) begin
        if(!aresetn) state<=a;
        else state<=next;
    end
    
    assign z = (state==c)&& x;
    
endmodule