data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:22: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time         CyclTime  = 10ns,\n                                     ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:23: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time         ApplTime  = 2ns,\n                                     ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:24: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time         TestTime  = 8ns\n                                     ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:31: syntax error, unexpected IDENTIFIER\n  clk_rst_gen #(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:59: syntax error, unexpected for\n  for (genvar i = 0; i < NumPorts; i++) begin : gen_stimuli\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:66: syntax error, unexpected IDENTIFIER\n      done[i]  <= 1\'b0;\n      ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:76: syntax error, unexpected IDENTIFIER\n      for (int unsigned j = 0; j < NoReq; j++) begin\n                               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:77: Unsupported or unknown PLI call: $urandom\n        stim_write = bit\'($urandom());\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:78: syntax error, unexpected IDENTIFIER\n        for (int unsigned k = 0; k < AddrWidth; k++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:79: Unsupported or unknown PLI call: $urandom\n          stim_addr[k] = bit\'($urandom());\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:83: syntax error, unexpected IDENTIFIER\n          for (int unsigned k = 0; k < AddrWidth; k++) begin\n                                   ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:84: Unsupported or unknown PLI call: $urandom\n            stim_addr[k] = bit\'($urandom());\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:87: syntax error, unexpected IDENTIFIER\n        for (int unsigned k = 0; k < DataWidth; k++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:88: Unsupported or unknown PLI call: $urandom\n          stim_data[k] = bit\'($urandom());\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:90: syntax error, unexpected IDENTIFIER\n        for (int unsigned k = 0; k < BeWidth; k++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:91: Unsupported or unknown PLI call: $urandom\n          stim_be[k] = bit\'($urandom());\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:106: Unsupported or unknown PLI call: $urandom_range\n        repeat ($urandom_range(0,5)) @(posedge clk);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:119: syntax error, unexpected IDENTIFIER\n    for (int unsigned i = 0; i < NumWords; i++) begin\n                             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:120: syntax error, unexpected IDENTIFIER\n      for (int unsigned j = 0; j < DataWidth; j++) begin\n                               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:134: syntax error, unexpected IDENTIFIER\n      for (int unsigned i = 0; i < NumPorts; i++) begin\n                               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:136: syntax error, unexpected IDENTIFIER\n          for (int unsigned j = 0; j < DataWidth; j++) begin\n                                   ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:147: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < NumPorts; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:161: syntax error, unexpected \'@\'\n        repeat (Latency) @(posedge clk);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:162: Unsupported: Ignoring delay on this delayed statement.\n        #TestTime;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/test/tb_tc_sram.sv:178: syntax error, unexpected initial\n  initial begin : proc_stop\n  ^~~~~~~\n%Error: Exiting due to 24 error(s), 1 warning(s)\n'
module tb_tc_sram #(
  parameter int unsigned NumPorts  = 32'd2,
  parameter int unsigned Latency   = 32'd1,
  parameter int unsigned NumWords  = 32'd1024,
  parameter int unsigned DataWidth = 32'd64,
  parameter int unsigned ByteWidth = 32'd8,
  parameter int unsigned NoReq     = 32'd200000,
  parameter string       SimInit   = "zeros",
  parameter time         CyclTime  = 10ns,
  parameter time         ApplTime  = 2ns,
  parameter time         TestTime  = 8ns
);




  logic clk, rst_n;
  clk_rst_gen #(
    .ClkPeriod   ( CyclTime ),
    .RstClkCycles( 5        )
  ) i_clk_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );

  logic [NumPorts-1:0] done;

  localparam int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1;
  localparam int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth;

  typedef logic [AddrWidth-1:0] addr_t;
  typedef logic [DataWidth-1:0] data_t;
  typedef logic [BeWidth-1:0]   be_t;


  logic  [NumPorts-1:0] req,   we;
  addr_t [NumPorts-1:0] addr;
  data_t [NumPorts-1:0] wdata, rdata;
  be_t   [NumPorts-1:0] be;


  data_t           memory [NumWords-1:0];
  longint unsigned failed_test;


  for (genvar i = 0; i < NumPorts; i++) begin : gen_stimuli
    initial begin : proc_drive_port
      automatic logic  stim_write;
      automatic addr_t stim_addr;
      automatic data_t stim_data;
      automatic be_t   stim_be;

      done[i]  <= 1'b0;
      req[i]   <= 1'b0;
      we[i]    <= 1'b0;
      addr[i]  <= addr_t'(0);
      wdata[i] <= data_t'(0);
      be[i]    <= be_t'(0);

      @(posedge rst_n);
      repeat (10) @(posedge clk);

      for (int unsigned j = 0; j < NoReq; j++) begin
        stim_write = bit'($urandom());
        for (int unsigned k = 0; k < AddrWidth; k++) begin
          stim_addr[k] = bit'($urandom());
        end

        while (stim_addr >= NumWords) begin
          for (int unsigned k = 0; k < AddrWidth; k++) begin
            stim_addr[k] = bit'($urandom());
          end
        end
        for (int unsigned k = 0; k < DataWidth; k++) begin
          stim_data[k] = bit'($urandom());
        end
        for (int unsigned k = 0; k < BeWidth; k++) begin
          stim_be[k] = bit'($urandom());
        end

        req[i]   <= #ApplTime 1'b1;
        we[i]    <= #ApplTime stim_write;
        addr[i]  <= #ApplTime stim_addr;
        wdata[i] <= #ApplTime stim_data;
        be[i]    <= #ApplTime stim_be;
        @(posedge clk);
        req[i]   <= #ApplTime 1'b0;
        we[i]    <= #ApplTime 1'b0;
        addr[i]  <= #ApplTime addr_t'(0);
        wdata[i] <= #ApplTime data_t'(0);
        be[i]    <= #ApplTime be_t'(0);

        repeat ($urandom_range(0,5)) @(posedge clk);
      end
      done[i] <= 1'b1;
    end
  end






  initial begin: proc_golden_model
    failed_test = 0;
    for (int unsigned i = 0; i < NumWords; i++) begin
      for (int unsigned j = 0; j < DataWidth; j++) begin
        case (SimInit)
          "zeros": memory[i][j] = 1'b0;
          "ones":  memory[i][j] = 1'b1;
          default: memory[i][j] = 1'bx;
        endcase
      end
    end

    @(posedge rst_n);

    forever begin
      @(posedge clk);

      for (int unsigned i = 0; i < NumPorts; i++) begin
        if (req[i] && we[i]) begin
          for (int unsigned j = 0; j < DataWidth; j++) begin
            if (be[i][j/ByteWidth]) begin
              memory[addr[i]][j] = wdata[i][j];
            end
          end
        end
      end


      #TestTime;
      fork
        for (int unsigned i = 0; i < NumPorts; i++) begin
          check_read(i, addr[i]);
        end
      join_none
    end
  end


  task automatic check_read(input int unsigned port, input addr_t read_addr);

    if (req[port] && !we[port]) begin
      data_t exp_data = memory[read_addr];

      if (Latency > 0) begin
        repeat (Latency) @(posedge clk);
        #TestTime;
      end

      for (int unsigned i = 0; i < DataWidth; i++) begin
        if (!$isunknown(exp_data[i])) begin
          assert(exp_data[i] === rdata[port][i]) else begin
            $warning("Port: %0d unexpected bit[%0h], Addr: %0h expected: %0h, measured: %0h",
                port, i, read_addr, exp_data[i], rdata[port][i]);
            failed_test++;
          end
        end
      end
    end
  endtask : check_read


  initial begin : proc_stop
    @(posedge rst_n);
    wait (&done);
    repeat (10) @(posedge clk);
    $info("Simulation done, errors: %0d", failed_test);
    $stop();
  end

  tc_sram #(
    .NumWords    ( NumWords  ),
    .DataWidth   ( DataWidth ),
    .ByteWidth   ( ByteWidth ),
    .NumPorts    ( NumPorts  ),
    .Latency     ( Latency   ),
    .SimInit     ( SimInit   ),
    .PrintSimCfg ( 1'b1      )
  ) i_tc_sram_dut (
    .clk_i   ( clk   ),
    .rst_ni  ( rst_n ),
    .req_i   ( req   ),
    .we_i    ( we    ),
    .addr_i  ( addr  ),
    .wdata_i ( wdata ),
    .be_i    ( be    ),
    .rdata_o ( rdata )
  );
endmodule
module tb_tc_sram #(
  parameter int unsigned NumPorts  = 32'd2,
  parameter int unsigned Latency   = 32'd1,
  parameter int unsigned NumWords  = 32'd1024,
  parameter int unsigned DataWidth = 32'd64,
  parameter int unsigned ByteWidth = 32'd8,
  parameter int unsigned NoReq     = 32'd200000,
  parameter string       SimInit   = "zeros",
  parameter time         CyclTime  = 10ns,
  parameter time         ApplTime  = 2ns,
  parameter time         TestTime  = 8ns
);





  logic clk, rst_n;
  clk_rst_gen #(
    .ClkPeriod   ( CyclTime ),
    .RstClkCycles( 5        )
  ) i_clk_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );

  logic [NumPorts-1:0] done;

  localparam int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1;
  localparam int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth;

  typedef logic [AddrWidth-1:0] addr_t;
  typedef logic [DataWidth-1:0] data_t;
  typedef logic [BeWidth-1:0]   be_t;


  logic  [NumPorts-1:0] req,   we;
  addr_t [NumPorts-1:0] addr;
  data_t [NumPorts-1:0] wdata, rdata;
  be_t   [NumPorts-1:0] be;


  data_t           memory [NumWords-1:0];
  longint unsigned failed_test;


  for (genvar i = 0; i < NumPorts; i++) begin : gen_stimuli
    initial begin : proc_drive_port
      automatic logic  stim_write;
      automatic addr_t stim_addr;
      automatic data_t stim_data;
      automatic be_t   stim_be;

      done[i]  <= 1'b0;
      req[i]   <= 1'b0;
      we[i]    <= 1'b0;
      addr[i]  <= addr_t'(0);
      wdata[i] <= data_t'(0);
      be[i]    <= be_t'(0);

      @(posedge rst_n);
      repeat (10) @(posedge clk);

      for (int unsigned j = 0; j < NoReq; j++) begin
        stim_write = bit'($urandom());
        for (int unsigned k = 0; k < AddrWidth; k++) begin
          stim_addr[k] = bit'($urandom());
        end

        while (stim_addr >= NumWords) begin
          for (int unsigned k = 0; k < AddrWidth; k++) begin
            stim_addr[k] = bit'($urandom());
          end
        end
        for (int unsigned k = 0; k < DataWidth; k++) begin
          stim_data[k] = bit'($urandom());
        end
        for (int unsigned k = 0; k < BeWidth; k++) begin
          stim_be[k] = bit'($urandom());
        end

        req[i]   <= #ApplTime 1'b1;
        we[i]    <= #ApplTime stim_write;
        addr[i]  <= #ApplTime stim_addr;
        wdata[i] <= #ApplTime stim_data;
        be[i]    <= #ApplTime stim_be;
        @(posedge clk);
        req[i]   <= #ApplTime 1'b0;
        we[i]    <= #ApplTime 1'b0;
        addr[i]  <= #ApplTime addr_t'(0);
        wdata[i] <= #ApplTime data_t'(0);
        be[i]    <= #ApplTime be_t'(0);

        repeat ($urandom_range(0,5)) @(posedge clk);
      end
      done[i] <= 1'b1;
    end
  end






  initial begin: proc_golden_model
    failed_test = 0;
    for (int unsigned i = 0; i < NumWords; i++) begin
      for (int unsigned j = 0; j < DataWidth; j++) begin
        case (SimInit)
          "zeros": memory[i][j] = 1'b0;
          "ones":  memory[i][j] = 1'b1;
          default: memory[i][j] = 1'bx;
        endcase
      end
    end

    @(posedge rst_n);

    forever begin
      @(posedge clk);

      for (int unsigned i = 0; i < NumPorts; i++) begin
        if (req[i] && we[i]) begin
          for (int unsigned j = 0; j < DataWidth; j++) begin
            if (be[i][j/ByteWidth]) begin
              memory[addr[i]][j] = wdata[i][j];
            end
          end
        end
      end


      #TestTime;
      fork
        for (int unsigned i = 0; i < NumPorts; i++) begin
          check_read(i, addr[i]);
        end
      join_none
    end
  end


  task automatic check_read(input int unsigned port, input addr_t read_addr);

    if (req[port] && !we[port]) begin
      data_t exp_data = memory[read_addr];

      if (Latency > 0) begin
        repeat (Latency) @(posedge clk);
        #TestTime;
      end

      for (int unsigned i = 0; i < DataWidth; i++) begin
        if (!$isunknown(exp_data[i])) begin
          assert(exp_data[i] === rdata[port][i]) else begin
            $warning("Port: %0d unexpected bit[%0h], Addr: %0h expected: %0h, measured: %0h",
                port, i, read_addr, exp_data[i], rdata[port][i]);
            failed_test++;
          end
        end
      end
    end
  endtask : check_read


  initial begin : proc_stop
    @(posedge rst_n);
    wait (&done);
    repeat (10) @(posedge clk);
    $info("Simulation done, errors: %0d", failed_test);
    $stop();
  end

  tc_sram #(
    .NumWords    ( NumWords  ),
    .DataWidth   ( DataWidth ),
    .ByteWidth   ( ByteWidth ),
    .NumPorts    ( NumPorts  ),
    .Latency     ( Latency   ),
    .SimInit     ( SimInit   ),
    .PrintSimCfg ( 1'b1      )
  ) i_tc_sram_dut (
    .clk_i   ( clk   ),
    .rst_ni  ( rst_n ),
    .req_i   ( req   ),
    .we_i    ( we    ),
    .addr_i  ( addr  ),
    .wdata_i ( wdata ),
    .be_i    ( be    ),
    .rdata_o ( rdata )
  );
endmodule