data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:84: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s SEL generates 25 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n                get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_DATA_BYTES];\n                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:86: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n                get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_DATA_BYTES];\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:85: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n            end else if (len == 4\'b1111) begin\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:83: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h7\' generates 4 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n            end else if (len == 4\'b111) begin\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:81: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n            end else if (len == 4\'b11) begin\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:79: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                                             : ... In instance axi4_mem_bridge\n            if (len == 4\'b1) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:106: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'base_len\' generates 8 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n            upper_wrap_boundary = wrap_boundary + ((base_len + \'h1) << LOG_DATA_BYTES);\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:107: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'tmp_len\' generates 8 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n            cons_addr = aligned_address + (tmp_len << LOG_DATA_BYTES);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:127: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'tmp_len\' generates 8 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        get_new_addr = base_addr + ((tmp_len - base_len) << LOG_DATA_BYTES);\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:127: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'base_len\' generates 8 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        get_new_addr = base_addr + ((tmp_len - base_len) << LOG_DATA_BYTES);\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:176: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_IDLE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n            state <= S_AXI4_IDLE;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:266: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_READ_ABORT\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_READ_ABORT;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:271: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_READ\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_READ;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:265: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'axi4_ar_size_i\' generates 3 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        if ((axi4_ar_size_i != LOG_DATA_BYTES) && (axi4_ar_len_i != 8\'h0)) begin\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:289: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE_ABORT\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        next_state = S_AXI4_WRITE_ABORT;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:304: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE_ACK\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                                next_state = S_AXI4_WRITE_ACK;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:306: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                                next_state = S_AXI4_WRITE;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:312: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WAIT_WVALID\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_WAIT_WVALID;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:318: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WAIT_WVALID\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        next_state = S_AXI4_WAIT_WVALID;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:288: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'axi4_aw_size_i\' generates 3 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                    if ((axi4_aw_size_i != LOG_DATA_BYTES) && (axi4_aw_len_i != 8\'h0)) begin\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:338: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE_ACK\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_WRITE_ACK;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:340: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_WRITE;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:361: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_IDLE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                        next_state = S_AXI4_IDLE;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:396: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_WRITE_ACK\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                            next_state = S_AXI4_WRITE_ACK;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:409: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_IDLE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                    next_state = S_AXI4_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:421: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_IDLE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                    next_state = S_AXI4_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:434: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_AXI4_IDLE\' generates 4 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n                    next_state = S_AXI4_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/463204869/units/axi_bridge/source/rtl/verilog/axi4_mem_bridge.v:244: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n                                                                                                              : ... In instance axi4_mem_bridge\n        case (state)\n        ^~~~\n%Error: Exiting due to 28 warning(s)\n'
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
        input [AXI_ADDR_WIDTH-1:0] unaligned_address;
        input [7:0] len;
        begin
            get_wrap_boundary = {AXI_ADDR_WIDTH{1'b0}};


            if (len == 4'b1) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_DATA_BYTES];
            end else if (len == 4'b11) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_DATA_BYTES];
            end else if (len == 4'b111) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_DATA_BYTES];
            end else if (len == 4'b1111) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_DATA_BYTES];
            end
        end
    endfunction
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;

        input [AXI_ADDR_WIDTH-1:0] unaligned_address;
        input [7:0] len;
        begin
            get_wrap_boundary = {AXI_ADDR_WIDTH{1'b0}};


            if (len == 4'b1) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_DATA_BYTES];
            end else if (len == 4'b11) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_DATA_BYTES];
            end else if (len == 4'b111) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_DATA_BYTES];
            end else if (len == 4'b1111) begin
                get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_DATA_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_DATA_BYTES];
            end
        end
    endfunction