data/full_repos/permissive/485295380/counter/counter_tb.v
1: b'%Error: data/full_repos/permissive/485295380/counter/counter_tb.v:9: Unsupported or unknown PLI call: $monitor\n$monitor(rst, clk, en, count);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485295380/counter/counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485295380/counter/counter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/485295380/counter/counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#200;\n^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb();
reg rst, clk, en;
wire [3:0] count;

Counter_fsm counter(.rst(rst), .clk(clk),  .en(en), .count(count));

initial
begin 
$monitor(rst, clk, en, count);
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
rst=1'b1;
en = 1'b0;
#20;
rst=1'b0;

#200;
en = 1'b1;
end
endmodule
module counter_tb();

reg rst, clk, en;
wire [3:0] count;

Counter_fsm counter(.rst(rst), .clk(clk),  .en(en), .count(count));

initial
begin 
$monitor(rst, clk, en, count);
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
rst=1'b1;
en = 1'b0;
#20;
rst=1'b0;

#200;
en = 1'b1;
end
endmodule