data/full_repos/permissive/476296842/rtl/core/trans.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:8: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:14: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]  w_reg_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`reg_addr_bus]  w_reg_addr_i,\n                             ^\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:15: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]  w_reg_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`csr_addr_bus]  w_csr_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:17: Define or directive not defined: \'`csr_addr_bus\'\n    input wire [`csr_addr_bus]  w_csr_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:18: Define or directive not defined: \'`csr_data_bus\'\n    input wire [`csr_data_bus]  w_csr_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:20: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]  r_reg_addr_1_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:21: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]  r_reg_addr_2_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:22: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]  r_reg_data_1_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:23: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]  r_reg_data_2_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:24: Define or directive not defined: \'`csr_addr_bus\'\n    input wire [`csr_addr_bus]  r_csr_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:25: Define or directive not defined: \'`csr_data_bus\'\n    input wire [`csr_data_bus]  r_csr_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:27: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus] r_reg_data_1_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:28: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus] r_reg_data_2_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:29: Define or directive not defined: \'`csr_data_bus\'\n    output wire [`csr_data_bus] r_csr_data_o\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:34: Define or directive not defined: \'`write_reg_req_enable\'\n        (r_reg_addr_1_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_1_i != 0) ? \n                                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:39: Define or directive not defined: \'`write_reg_req_enable\'\n        (r_reg_addr_2_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_2_i != 0) ? \n                                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/trans.v:44: Define or directive not defined: \'`write_reg_req_enable\'\n        (r_csr_addr_i == w_csr_addr_i && w_csr_req_i == `write_reg_req_enable) ? \n                                                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module trans (

    input wire                  w_reg_req_i,
    input wire [`reg_addr_bus]  w_reg_addr_i,
    input wire [`reg_data_bus]  w_reg_data_i,
    input wire                  w_csr_req_i,
    input wire [`csr_addr_bus]  w_csr_addr_i,
    input wire [`csr_data_bus]  w_csr_data_i,

    input wire [`reg_addr_bus]  r_reg_addr_1_i,
    input wire [`reg_addr_bus]  r_reg_addr_2_i,
    input wire [`reg_data_bus]  r_reg_data_1_i,
    input wire [`reg_data_bus]  r_reg_data_2_i,
    input wire [`csr_addr_bus]  r_csr_addr_i,
    input wire [`csr_data_bus]  r_csr_data_i,

    output wire [`reg_data_bus] r_reg_data_1_o,
    output wire [`reg_data_bus] r_reg_data_2_o,
    output wire [`csr_data_bus] r_csr_data_o
);
    

    assign r_reg_data_1_o = (
        (r_reg_addr_1_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_1_i != 0) ? 
        w_reg_data_i : r_reg_data_1_i 
    );

    assign r_reg_data_2_o = (
        (r_reg_addr_2_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_2_i != 0) ? 
        w_reg_data_i : r_reg_data_2_i 
    ); 

    assign r_csr_data_o = (
        (r_csr_addr_i == w_csr_addr_i && w_csr_req_i == `write_reg_req_enable) ? 
        w_csr_data_i : r_csr_data_i
    );

endmodule
module trans (

    input wire                  w_reg_req_i,
    input wire [`reg_addr_bus]  w_reg_addr_i,
    input wire [`reg_data_bus]  w_reg_data_i,
    input wire                  w_csr_req_i,
    input wire [`csr_addr_bus]  w_csr_addr_i,
    input wire [`csr_data_bus]  w_csr_data_i,

    input wire [`reg_addr_bus]  r_reg_addr_1_i,
    input wire [`reg_addr_bus]  r_reg_addr_2_i,
    input wire [`reg_data_bus]  r_reg_data_1_i,
    input wire [`reg_data_bus]  r_reg_data_2_i,
    input wire [`csr_addr_bus]  r_csr_addr_i,
    input wire [`csr_data_bus]  r_csr_data_i,

    output wire [`reg_data_bus] r_reg_data_1_o,
    output wire [`reg_data_bus] r_reg_data_2_o,
    output wire [`csr_data_bus] r_csr_data_o
);

    

    assign r_reg_data_1_o = (
        (r_reg_addr_1_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_1_i != 0) ? 
        w_reg_data_i : r_reg_data_1_i 
    );

    assign r_reg_data_2_o = (
        (r_reg_addr_2_i == w_reg_addr_i && w_reg_req_i == `write_reg_req_enable && r_reg_addr_2_i != 0) ? 
        w_reg_data_i : r_reg_data_2_i 
    ); 

    assign r_csr_data_o = (
        (r_csr_addr_i == w_csr_addr_i && w_csr_req_i == `write_reg_req_enable) ? 
        w_csr_data_i : r_csr_data_i
    );

endmodule