data/full_repos/permissive/484799296/verilog/program_counter/program_counter.v
data/verilator_xmls/338fa644-0730-404e-8bf7-60b7d8b8a3ee.xml
module program_counter(
    input clk,
    input enable,
    input reset,
    input load,
    input [11:0] pre_load,
    output reg [11:0] pc
);

    always @(posedge clk, posedge reset)
    begin

        if (load) begin
            pc = pre_load;
        end

        if (enable) begin
            pc = pc + 1;
        end

        if (reset) begin
            pc = 0;
        end
    end
endmodule
module program_counter(
    input clk,
    input enable,
    input reset,
    input load,
    input [11:0] pre_load,
    output reg [11:0] pc
);


    always @(posedge clk, posedge reset)
    begin

        if (load) begin
            pc = pre_load;
        end

        if (enable) begin
            pc = pc + 1;
        end

        if (reset) begin
            pc = 0;
        end
    end
endmodule