data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:30: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s FUNCREF \'led_on\' generates 1 bits.\n                                                                                            : ... In instance main\nassign led_row = led_on(counter) << row_index;\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:90: Cannot find file containing module: \'uart\'\nuart uart(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src,data/full_repos/permissive/456436315/uart\n             data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src,data/full_repos/permissive/456436315/uart.v\n             data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src,data/full_repos/permissive/456436315/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Warning-WIDTH: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:126: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                             : ... In instance main\n    recv_data <= 10\'d0;\n              ^~\n%Error: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:152: Cannot find file containing module: \'Gowin_SDPB\'\nGowin_SDPB prog_mem(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:167: Cannot find file containing module: \'Gowin_SDPB_Data\'\nGowin_SDPB_Data data_mem(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/456436315/src/cpu/board/tangnano9k/src/main.sv:182: Cannot find file containing module: \'cpu\'\ncpu cpu(\n^~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module main(
  input sys_clk,
  input rst_n_raw,
  input uart_rx,
  output uart_tx,
  output [7:0] led_col,
  output [8:0] led_row
);

parameter PERIOD = 16'd27000;
parameter GAP = 16'd500;


logic rst_n;
logic [15:0] counter;
logic [2:0] row_index;
logic [7:0] uart_rx_data, uart_tx_data;
logic uart_tx_en, uart_rx_data_wr;

logic [15:0] recv_data, insn;
logic [9:0] recv_addr, pc;
logic recv_phase, recv_data_v, recv_compl;

logic [7:0] cpu_reg0;
logic cpu_reg0_wr;
logic [7:0] cpu_mem_addr, cpu_rd_data, cpu_wr_data;
logic cpu_mem_wr;


assign led_row = led_on(counter) << row_index;
assign led_col = led_pattern(row_index);


assign recv_compl = recv_data == 16'hffff;

always @(posedge sys_clk) begin
  rst_n <= rst_n_raw;
end


function [7:0] led_pattern(input [2:0] row_index);
  case (row_index)
    3'd0:    led_pattern = 8'b10101010;
    3'd1:    led_pattern = cpu_reg0;
    3'd2:    led_pattern = recv_data[15:8];
    3'd3:    led_pattern = recv_data[7:0];
    default: led_pattern = 8'b00000000;
  endcase
endfunction


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    counter <= 16'd0;
  else if (counter >= PERIOD - 1)
    counter <= 16'd0;
  else
    counter <= counter + 16'd1;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    row_index <= 3'd0;
  else if (counter == 0)
    row_index <= row_index + 3'd1;
end


function led_on(input [15:0] counter);
  led_on = (GAP <= counter) && (counter < PERIOD - GAP);
endfunction

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    uart_tx_data <= 8'd0;
  else if (cpu_reg0_wr)
    uart_tx_data <= cpu_reg0;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    uart_tx_en <= 1'd0;
  else if (cpu_reg0_wr)
    uart_tx_en <= 1'd1;
  else
    uart_tx_en <= 1'd0;
end

uart uart(
  .*,
  .rx_data(uart_rx_data),
  .rx_data_wr(uart_rx_data_wr),
  .tx_data(uart_tx_data),
  .tx_en(uart_tx_en)
);




always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_phase <= 1'b0;
  else if (uart_rx_data_wr)
    recv_phase <= ~recv_phase;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_data <= 10'd0;
  else if (uart_rx_data_wr)
    recv_data <= {recv_data[7:0], uart_rx_data};
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_data_v <= 1'b0;
  else if (uart_rx_data_wr & recv_phase)
    recv_data_v <= 1'b1;
  else
    recv_data_v <= 1'b0;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_addr <= 10'd0;
  else if (recv_data_v & ~recv_compl)
    recv_addr <= recv_addr + 10'd1;
  else if (uart_rx_data_wr && recv_compl)
    recv_addr <= 10'd0;
end


Gowin_SDPB prog_mem(
  .clka(sys_clk),
  .cea(1'b1),
  .reseta(!rst_n),
  .clkb(sys_clk),
  .ceb(1'b1),
  .resetb(!rst_n),
  .oce(1'b0),
  .ada(recv_addr),
  .din(recv_data),
  .adb(pc),
  .dout(insn)
);


Gowin_SDPB_Data data_mem(
  .clka(sys_clk),
  .cea(cpu_mem_wr),
  .reseta(!rst_n),
  .clkb(sys_clk),
  .ceb(1'b1),
  .resetb(!rst_n),
  .oce(1'b0),
  .ada(cpu_mem_addr),
  .din(cpu_wr_data),
  .adb(cpu_mem_addr),
  .dout(cpu_rd_data)
);


cpu cpu(
  .rst(~rst_n | ~recv_compl),
  .clk(sys_clk),
  .insn(insn),
  .reg0(cpu_reg0),
  .reg0_wr(cpu_reg0_wr),
  .pc(pc),
  .mem_addr(cpu_mem_addr),
  .mem_wr(cpu_mem_wr),
  .rd_data(cpu_rd_data),
  .wr_data(cpu_wr_data)
);

endmodule
module main(
  input sys_clk,
  input rst_n_raw,
  input uart_rx,
  output uart_tx,
  output [7:0] led_col,
  output [8:0] led_row
);


parameter PERIOD = 16'd27000;
parameter GAP = 16'd500;


logic rst_n;
logic [15:0] counter;
logic [2:0] row_index;
logic [7:0] uart_rx_data, uart_tx_data;
logic uart_tx_en, uart_rx_data_wr;

logic [15:0] recv_data, insn;
logic [9:0] recv_addr, pc;
logic recv_phase, recv_data_v, recv_compl;

logic [7:0] cpu_reg0;
logic cpu_reg0_wr;
logic [7:0] cpu_mem_addr, cpu_rd_data, cpu_wr_data;
logic cpu_mem_wr;


assign led_row = led_on(counter) << row_index;
assign led_col = led_pattern(row_index);


assign recv_compl = recv_data == 16'hffff;

always @(posedge sys_clk) begin
  rst_n <= rst_n_raw;
end


function [7:0] led_pattern(input [2:0] row_index);
  case (row_index)
    3'd0:    led_pattern = 8'b10101010;
    3'd1:    led_pattern = cpu_reg0;
    3'd2:    led_pattern = recv_data[15:8];
    3'd3:    led_pattern = recv_data[7:0];
    default: led_pattern = 8'b00000000;
  endcase
endfunction


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    counter <= 16'd0;
  else if (counter >= PERIOD - 1)
    counter <= 16'd0;
  else
    counter <= counter + 16'd1;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    row_index <= 3'd0;
  else if (counter == 0)
    row_index <= row_index + 3'd1;
end


function led_on(input [15:0] counter);
  led_on = (GAP <= counter) && (counter < PERIOD - GAP);
endfunction

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    uart_tx_data <= 8'd0;
  else if (cpu_reg0_wr)
    uart_tx_data <= cpu_reg0;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    uart_tx_en <= 1'd0;
  else if (cpu_reg0_wr)
    uart_tx_en <= 1'd1;
  else
    uart_tx_en <= 1'd0;
end

uart uart(
  .*,
  .rx_data(uart_rx_data),
  .rx_data_wr(uart_rx_data_wr),
  .tx_data(uart_tx_data),
  .tx_en(uart_tx_en)
);




always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_phase <= 1'b0;
  else if (uart_rx_data_wr)
    recv_phase <= ~recv_phase;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_data <= 10'd0;
  else if (uart_rx_data_wr)
    recv_data <= {recv_data[7:0], uart_rx_data};
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_data_v <= 1'b0;
  else if (uart_rx_data_wr & recv_phase)
    recv_data_v <= 1'b1;
  else
    recv_data_v <= 1'b0;
end


always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    recv_addr <= 10'd0;
  else if (recv_data_v & ~recv_compl)
    recv_addr <= recv_addr + 10'd1;
  else if (uart_rx_data_wr && recv_compl)
    recv_addr <= 10'd0;
end


Gowin_SDPB prog_mem(
  .clka(sys_clk),
  .cea(1'b1),
  .reseta(!rst_n),
  .clkb(sys_clk),
  .ceb(1'b1),
  .resetb(!rst_n),
  .oce(1'b0),
  .ada(recv_addr),
  .din(recv_data),
  .adb(pc),
  .dout(insn)
);


Gowin_SDPB_Data data_mem(
  .clka(sys_clk),
  .cea(cpu_mem_wr),
  .reseta(!rst_n),
  .clkb(sys_clk),
  .ceb(1'b1),
  .resetb(!rst_n),
  .oce(1'b0),
  .ada(cpu_mem_addr),
  .din(cpu_wr_data),
  .adb(cpu_mem_addr),
  .dout(cpu_rd_data)
);


cpu cpu(
  .rst(~rst_n | ~recv_compl),
  .clk(sys_clk),
  .insn(insn),
  .reg0(cpu_reg0),
  .reg0_wr(cpu_reg0_wr),
  .pc(pc),
  .mem_addr(cpu_mem_addr),
  .mem_wr(cpu_mem_wr),
  .rd_data(cpu_rd_data),
  .wr_data(cpu_wr_data)
);

endmodule