data/full_repos/permissive/418819021/lab-06/state_machine.v
1: b'%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:6: Define or directive not defined: \'`STAGE_COUNT\'\n    output      reg [`STAGE_COUNT-1:0] pipeline_stage,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:11: Define or directive not defined: \'`STAGE_COUNT\'\n    reg [`STAGE_COUNT-1:0] next_stage;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:15: Define or directive not defined: \'`STAGE_RESET\'\n            pipeline_stage <= `STAGE_RESET;\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            pipeline_stage <= `STAGE_RESET;\n                                          ^\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:21: Define or directive not defined: \'`STAGE_RESET\'\n            `STAGE_RESET :\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:21: syntax error, unexpected \':\', expecting endcase\n            `STAGE_RESET :\n                         ^\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:22: Define or directive not defined: \'`STAGE_IF\'\n            next_stage = `STAGE_IF;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:23: Define or directive not defined: \'`STAGE_IF\'\n            `STAGE_IF    :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:24: Define or directive not defined: \'`STAGE_ID\'\n            next_stage = `STAGE_ID;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:25: Define or directive not defined: \'`STAGE_ID\'\n            `STAGE_ID    :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:26: Define or directive not defined: \'`STAGE_EX\'\n            next_stage = `STAGE_EX;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:27: Define or directive not defined: \'`STAGE_EX\'\n            `STAGE_EX    :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:28: Define or directive not defined: \'`STAGE_MEM\'\n            next_stage = `STAGE_MEM;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:29: Define or directive not defined: \'`STAGE_MEM\'\n            `STAGE_MEM   :\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:30: Define or directive not defined: \'`STAGE_WB\'\n            next_stage = `STAGE_WB;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:31: Define or directive not defined: \'`STAGE_WB\'\n            `STAGE_WB    :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:32: Define or directive not defined: \'`STAGE_IF\'\n            next_stage = `STAGE_IF;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/state_machine.v:35: Define or directive not defined: \'`STAGE_RESET\'\n                next_stage = `STAGE_RESET;\n                             ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module state_machine (
    output      reg [`STAGE_COUNT-1:0] pipeline_stage,
    input  wire                        clk           ,
    input  wire                        reset
);

    reg [`STAGE_COUNT-1:0] next_stage;

    always @(posedge clk, posedge reset)
        if (reset)
            pipeline_stage <= `STAGE_RESET;
        else
            pipeline_stage <= next_stage;

    always @* begin
        case (pipeline_stage)
            `STAGE_RESET :
            next_stage = `STAGE_IF;
            `STAGE_IF    :
            next_stage = `STAGE_ID;
            `STAGE_ID    :
            next_stage = `STAGE_EX;
            `STAGE_EX    :
            next_stage = `STAGE_MEM;
            `STAGE_MEM   :
            next_stage = `STAGE_WB;
            `STAGE_WB    :
            next_stage = `STAGE_IF;

            default      :
                next_stage = `STAGE_RESET;
        endcase
    end

endmodule
module state_machine (
    output      reg [`STAGE_COUNT-1:0] pipeline_stage,
    input  wire                        clk           ,
    input  wire                        reset
);


    reg [`STAGE_COUNT-1:0] next_stage;

    always @(posedge clk, posedge reset)
        if (reset)
            pipeline_stage <= `STAGE_RESET;
        else
            pipeline_stage <= next_stage;

    always @* begin
        case (pipeline_stage)
            `STAGE_RESET :
            next_stage = `STAGE_IF;
            `STAGE_IF    :
            next_stage = `STAGE_ID;
            `STAGE_ID    :
            next_stage = `STAGE_EX;
            `STAGE_EX    :
            next_stage = `STAGE_MEM;
            `STAGE_MEM   :
            next_stage = `STAGE_WB;
            `STAGE_WB    :
            next_stage = `STAGE_IF;

            default      :
                next_stage = `STAGE_RESET;
        endcase
    end

endmodule