data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:20: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:21: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgAxiStreamBfm::*;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:117: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  TestExec test = new();\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:118: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =\n                                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:127: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);\n                                                  ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:128: Unsupported: wait statements\n    wait(!rst);\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:129: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:133: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;\n                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:134: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;\n                            ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:137: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task automatic check_lbus(AxisPacket_t packets[$]);\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:144: syntax error, unexpected foreach\n    foreach(packets[i]) begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:153: syntax error, unexpected int, expecting IDENTIFIER or genvar\n            for (int s=0; s < NUM_SEG; s++) begin\n                 ^~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:155: syntax error, unexpected int, expecting IDENTIFIER or genvar\n              for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin\n                   ^~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:161: syntax error, unexpected \'(\', expecting \'#\' or final or property\n              assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch");\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:164: syntax error, unexpected \'(\', expecting \'#\' or final or property\n                  assert (lbus_out[s].sop == 1) else $error("Sop not set");\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:166: syntax error, unexpected \'(\', expecting \'#\' or final or property\n                  assert (lbus_out[s].sop == 0) else $error("Sop Set");\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:168: syntax error, unexpected \'(\', expecting \'#\' or final or property\n                assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch");\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:172: syntax error, unexpected \'(\', expecting \'#\' or final or property\n                assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled");\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:196: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic AxisPacket_t send[$];\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:200: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test({TEST_NAME,"Test Transfer"}, 200us);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:203: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n      automatic raw_pkt_t    pay;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:217: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:271: Unsupported or unknown PLI call: $urandom_range\n     random_value = $urandom_range(64,512);\n                    ^~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv:13: ../V3ParseSym.h:114: Symbols suggest ending TASK \'check_lbus\' but parser thinks ending MODULE \'axi_lbus_tb\'\nmodule axi_lbus_tb #(\n       ^~~~~~~~~~~\n'
module axi_lbus_tb #(
  parameter TEST_NAME  = ""
)(

);

  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiStreamBfm::*;
  import PkgEthernet::*;
  import PkgTestExec::*;
  import PkgEth100gLbus::*;

  localparam DATA_WIDTH      = 512;
  localparam USER_WIDTH      = $clog2(DATA_WIDTH/8)+1;
  localparam NUM_SEG         = 4;
  localparam SEG_DATA_WIDTH  = DATA_WIDTH/NUM_SEG;
  localparam SEG_BYTES       = SEG_DATA_WIDTH/8;




  logic clk;
  logic rst;

  sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
    clk_gen (.clk(clk), .rst(rst));




  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axis    (clk, rst);




  lbus_t lbus_out [NUM_SEG-1:0];
  lbus_t lbus_g   [NUM_SEG-1:0];
  logic lbus_rdy = 1;

  eth_100g_axi2lbus #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
    .axis(axis),
    .lbus_rdy(lbus_rdy),
    .lbus_out(lbus_out)
  );













  TestExec test = new();
  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
    new(.slave(null),.master(axis));






  task test_reset();
    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
    wait(!rst);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset

  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;


  task automatic check_lbus(AxisPacket_t packets[$]);

    int idle_insert = 0;
    int byte_count = 0;
    int first_clk   = 1;


    foreach(packets[i]) begin
      automatic raw_pkt_t pay;
      pay = packets[i].dump_bytes;

      first_clk=1;
      while (pay.size() > 0) begin
        @(posedge clk);
        if (lbus_rdy) begin
          if (lbus_out[0].ena) begin
            for (int s=0; s < NUM_SEG; s++) begin
              byte_count = 0;
              for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin
                if (pay.size() > 0) begin
                  assert (lbus_out[s].data[b*8 +: 8]  == pay.pop_front()) else $error("Data Mismatch");
                  byte_count++;
                end
              end
              assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch");
              if (lbus_out[s].ena) begin
                if (first_clk && s==0) begin
                  assert (lbus_out[s].sop == 1) else $error("Sop not set");
                end else begin
                  assert (lbus_out[s].sop == 0) else $error("Sop Set");
                end
                assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch");
                assert (lbus_out[s].eop != (pay.size() > 0) ) else $error("Eop Mismatch");
                assert (lbus_out[s].err == 0) else $error("Err Mismatch");
              end else begin
                assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled");
                assert (lbus_out[s].mty == 0) else $error("Mty set while disabled");
                assert (lbus_out[s].eop == 0) else $error("Eop set while disabled");
                assert (lbus_out[s].err == 0) else $error("Err set while disabled");
              end
            end
            first_clk=0;
          end

        end else begin
           for (int s=0; s < NUM_SEG; s++) begin
             assert (lbus_out[s].ena == 0) else $error("Idle Ena set");
             assert (lbus_out[s].err == 0) else $error("Idle Err set");
             assert (lbus_out[s].sop == 0) else $error("Idle Sop set");
             assert (lbus_out[s].eop == 0) else $error("Idle Eop set");
             assert (lbus_out[s].mty == 0) else $error("Idle Mty non zero");
           end
        end
      end
    end

  endtask : check_lbus;

  task automatic test_transfers(int num_samples[$]);
    automatic AxisPacket_t send[$];
    automatic AxisPacket_t expected[$];
    automatic int sample_sum = 0;

    test.start_test({TEST_NAME,"Test Transfer"}, 200us);

    foreach (num_samples[i]) begin
      automatic raw_pkt_t    pay;

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
                       .ramp_inc(1),.pkt(pay),.SWIDTH(8));
      sample_sum += num_samples[i];
      send[i].push_bytes(pay);


      expected[i].push_bytes(pay);
    end

    fork
      begin
        foreach (send[i]) begin
          axi.put(send[i]);
        end
      end
      begin
        check_lbus(expected);
      end
    join

    test.end_test();
  endtask : test_transfers




  initial begin : tb_main
   automatic int num_samples[$];
   automatic int random_value;
   clk_gen.reset();



   axi.set_master_stall_prob(0);
   axi.run();
   test_reset();

   $display("Fixed Sequences");
   num_samples = {64,65,66,67,68,69,70,71};
   test_transfers(num_samples);
   num_samples = {64,128,256,512,256,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,64,64,64,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,80,80,80,80,80,80};
   test_transfers(num_samples);
   num_samples = {64,64,96,80,96,80,96,80};
   test_transfers(num_samples);
   $display("Tons of 64");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(64);
   end
   test_transfers(num_samples);
   $display("Tons of 65");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(65);
   end
   test_transfers(num_samples);
   $display("Tons of Random");
   num_samples.delete();
   repeat(1000) begin
     random_value = $urandom_range(64,512);
     num_samples.push_back(random_value);
   end
   test_transfers(num_samples);




   test.end_tb(0);


   clk_gen.kill();
  end

endmodule
module axi_lbus_tb #(
  parameter TEST_NAME  = ""
)(

);


  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiStreamBfm::*;
  import PkgEthernet::*;
  import PkgTestExec::*;
  import PkgEth100gLbus::*;

  localparam DATA_WIDTH      = 512;
  localparam USER_WIDTH      = $clog2(DATA_WIDTH/8)+1;
  localparam NUM_SEG         = 4;
  localparam SEG_DATA_WIDTH  = DATA_WIDTH/NUM_SEG;
  localparam SEG_BYTES       = SEG_DATA_WIDTH/8;




  logic clk;
  logic rst;

  sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
    clk_gen (.clk(clk), .rst(rst));




  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axis    (clk, rst);




  lbus_t lbus_out [NUM_SEG-1:0];
  lbus_t lbus_g   [NUM_SEG-1:0];
  logic lbus_rdy = 1;

  eth_100g_axi2lbus #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
    .axis(axis),
    .lbus_rdy(lbus_rdy),
    .lbus_out(lbus_out)
  );













  TestExec test = new();
  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
    new(.slave(null),.master(axis));






  task test_reset();
    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
    wait(!rst);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset

  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;


  task automatic check_lbus(AxisPacket_t packets[$]);

    int idle_insert = 0;
    int byte_count = 0;
    int first_clk   = 1;


    foreach(packets[i]) begin
      automatic raw_pkt_t pay;
      pay = packets[i].dump_bytes;

      first_clk=1;
      while (pay.size() > 0) begin
        @(posedge clk);
        if (lbus_rdy) begin
          if (lbus_out[0].ena) begin
            for (int s=0; s < NUM_SEG; s++) begin
              byte_count = 0;
              for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin
                if (pay.size() > 0) begin
                  assert (lbus_out[s].data[b*8 +: 8]  == pay.pop_front()) else $error("Data Mismatch");
                  byte_count++;
                end
              end
              assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch");
              if (lbus_out[s].ena) begin
                if (first_clk && s==0) begin
                  assert (lbus_out[s].sop == 1) else $error("Sop not set");
                end else begin
                  assert (lbus_out[s].sop == 0) else $error("Sop Set");
                end
                assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch");
                assert (lbus_out[s].eop != (pay.size() > 0) ) else $error("Eop Mismatch");
                assert (lbus_out[s].err == 0) else $error("Err Mismatch");
              end else begin
                assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled");
                assert (lbus_out[s].mty == 0) else $error("Mty set while disabled");
                assert (lbus_out[s].eop == 0) else $error("Eop set while disabled");
                assert (lbus_out[s].err == 0) else $error("Err set while disabled");
              end
            end
            first_clk=0;
          end

        end else begin
           for (int s=0; s < NUM_SEG; s++) begin
             assert (lbus_out[s].ena == 0) else $error("Idle Ena set");
             assert (lbus_out[s].err == 0) else $error("Idle Err set");
             assert (lbus_out[s].sop == 0) else $error("Idle Sop set");
             assert (lbus_out[s].eop == 0) else $error("Idle Eop set");
             assert (lbus_out[s].mty == 0) else $error("Idle Mty non zero");
           end
        end
      end
    end

  endtask : check_lbus;

  task automatic test_transfers(int num_samples[$]);
    automatic AxisPacket_t send[$];
    automatic AxisPacket_t expected[$];
    automatic int sample_sum = 0;

    test.start_test({TEST_NAME,"Test Transfer"}, 200us);

    foreach (num_samples[i]) begin
      automatic raw_pkt_t    pay;

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
                       .ramp_inc(1),.pkt(pay),.SWIDTH(8));
      sample_sum += num_samples[i];
      send[i].push_bytes(pay);


      expected[i].push_bytes(pay);
    end

    fork
      begin
        foreach (send[i]) begin
          axi.put(send[i]);
        end
      end
      begin
        check_lbus(expected);
      end
    join

    test.end_test();
  endtask : test_transfers




  initial begin : tb_main
   automatic int num_samples[$];
   automatic int random_value;
   clk_gen.reset();



   axi.set_master_stall_prob(0);
   axi.run();
   test_reset();

   $display("Fixed Sequences");
   num_samples = {64,65,66,67,68,69,70,71};
   test_transfers(num_samples);
   num_samples = {64,128,256,512,256,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,64,64,64,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,80,80,80,80,80,80};
   test_transfers(num_samples);
   num_samples = {64,64,96,80,96,80,96,80};
   test_transfers(num_samples);
   $display("Tons of 64");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(64);
   end
   test_transfers(num_samples);
   $display("Tons of 65");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(65);
   end
   test_transfers(num_samples);
   $display("Tons of Random");
   num_samples.delete();
   repeat(1000) begin
     random_value = $urandom_range(64,512);
     num_samples.push_back(random_value);
   end
   test_transfers(num_samples);




   test.end_tb(0);


   clk_gen.kill();
  end

endmodule