data/full_repos/permissive/487568919/basic_verilog/reverse_bytes.sv
data/verilator_xmls/dabd01e7-46dd-43d3-98ca-24f9bb50284f.xml
module reverse_bytes #( parameter
  BYTES = 8
)(
  input [(BYTES*8-1):0] in,
  output logic [(BYTES*8-1):0] out
);


logic [BYTES-1:0][7:0] byte_data;
assign byte_data = in;

logic [BYTES-1:0][7:0] rev_byte_data;

genvar i;
generate
  for (i = 0; i < BYTES ; i++) begin : gen_reverse
    always_comb begin
      rev_byte_data[i] = byte_data[(BYTES-1)-i];
    end
  end
endgenerate

assign out = rev_byte_data;

endmodule
module reverse_bytes #( parameter
  BYTES = 8
)(
  input [(BYTES*8-1):0] in,
  output logic [(BYTES*8-1):0] out
);



logic [BYTES-1:0][7:0] byte_data;
assign byte_data = in;

logic [BYTES-1:0][7:0] rev_byte_data;

genvar i;
generate
  for (i = 0; i < BYTES ; i++) begin : gen_reverse
    always_comb begin
      rev_byte_data[i] = byte_data[(BYTES-1)-i];
    end
  end
endgenerate

assign out = rev_byte_data;

endmodule