data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v
1: b'%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:16: Define or directive not defined: \'`WORD_ADDR_BITS\'\ninput [`WORD_ADDR_BITS-1:0] data_total;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:23: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       WB_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:24: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        WB_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:25: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        WB_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:26: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        WB_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:27: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       A_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:28: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        A_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:29: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        A_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:30: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        A_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:31: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       B_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:32: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        B_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:33: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        B_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:34: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        B_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:39: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_WB_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:40: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_WB_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:41: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_WB_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:42: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_WB_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:43: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_A_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:44: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_A_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:45: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_A_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:46: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_A_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:47: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_B_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:48: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_B_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:49: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_B_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:50: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_B_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:56: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_uni_A_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:57: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_A_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:58: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_A_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:59: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_A_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:60: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_uni_B_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:61: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_B_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:62: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_B_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:63: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_uni_B_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:68: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_sys_uni_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:69: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_uni_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:70: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_uni_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:71: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_uni_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:72: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_sys_wei_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:73: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_wei_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:74: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_wei_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:75: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_sys_wei_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:81: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       main_ctrl_wb_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:82: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_wb_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:83: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_wb_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:84: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        main_ctrl_wb_col;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:91: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire    [`WORD_ADDR_BITS-1:0]       unibuf_A_src_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:92: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        unibuf_A_channel;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:93: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        unibuf_A_row;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top.v:94: Define or directive not defined: \'`DATA_MAX_BITS\'\nwire    [`DATA_MAX_BITS-1:0]        unibuf_A_col;\n         ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Decoder(
    instr_valid,
    instr,
    valid,
    op,
    WB_src_addr,
    WB_channel,
    WB_row,
    WB_col,
    A_src_addr,
    A_channel,
    A_row,
    A_col,
    B_src_addr,
    B_channel,
    B_row,
    B_col
);

input                               instr_valid;
input [104:0]                       instr;

output                              valid;
output     [2:0]                    op;
output     [`WORD_ADDR_BITS-1:0]    WB_src_addr;
output     [`DATA_MAX_BITS-1:0]     WB_channel;
output     [`DATA_MAX_BITS-1:0]     WB_row;
output     [`DATA_MAX_BITS-1:0]     WB_col;
output     [`WORD_ADDR_BITS-1:0]    A_src_addr;
output     [`DATA_MAX_BITS-1:0]     A_channel;
output     [`DATA_MAX_BITS-1:0]     A_row;
output     [`DATA_MAX_BITS-1:0]     A_col;
output     [`WORD_ADDR_BITS-1:0]    B_src_addr;
output     [`DATA_MAX_BITS-1:0]     B_channel;
output     [`DATA_MAX_BITS-1:0]     B_row;
output     [`DATA_MAX_BITS-1:0]     B_col;



assign valid        = instr_valid;
assign op           = instr[104:102];
assign WB_src_addr  = instr[101:92];
assign WB_channel   = instr[91:84];
assign WB_row       = instr[83:76];
assign WB_col       = instr[75:68];
assign A_src_addr   = instr[67:58];
assign A_channel    = instr[57:50];
assign A_row        = instr[49:42];
assign A_col        = instr[41:34];
assign B_src_addr   = instr[33:24];
assign B_channel    = instr[23:16];
assign B_row        = instr[15:8];
assign B_col        = instr[7:0];


endmodule
module Decoder(
    instr_valid,
    instr,
    valid,
    op,
    WB_src_addr,
    WB_channel,
    WB_row,
    WB_col,
    A_src_addr,
    A_channel,
    A_row,
    A_col,
    B_src_addr,
    B_channel,
    B_row,
    B_col
);


input                               instr_valid;
input [104:0]                       instr;

output                              valid;
output     [2:0]                    op;
output     [`WORD_ADDR_BITS-1:0]    WB_src_addr;
output     [`DATA_MAX_BITS-1:0]     WB_channel;
output     [`DATA_MAX_BITS-1:0]     WB_row;
output     [`DATA_MAX_BITS-1:0]     WB_col;
output     [`WORD_ADDR_BITS-1:0]    A_src_addr;
output     [`DATA_MAX_BITS-1:0]     A_channel;
output     [`DATA_MAX_BITS-1:0]     A_row;
output     [`DATA_MAX_BITS-1:0]     A_col;
output     [`WORD_ADDR_BITS-1:0]    B_src_addr;
output     [`DATA_MAX_BITS-1:0]     B_channel;
output     [`DATA_MAX_BITS-1:0]     B_row;
output     [`DATA_MAX_BITS-1:0]     B_col;



assign valid        = instr_valid;
assign op           = instr[104:102];
assign WB_src_addr  = instr[101:92];
assign WB_channel   = instr[91:84];
assign WB_row       = instr[83:76];
assign WB_col       = instr[75:68];
assign A_src_addr   = instr[67:58];
assign A_channel    = instr[57:50];
assign A_row        = instr[49:42];
assign A_col        = instr[41:34];
assign B_src_addr   = instr[33:24];
assign B_channel    = instr[23:16];
assign B_row        = instr[15:8];
assign B_col        = instr[7:0];


endmodule