data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5 clktq = ~clktq;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n           #10 \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n           #100  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n           #100 \n           ^\n%Error: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/top_tb.v:16: Cannot find file containing module: \'top\'\n   top COMP(\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/top\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/top.v\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb(

    );
    reg clktq;
    reg rsttq;
    
    reg [4:0] SW1q;
    reg udtq;
    wire segq;
    wire [6:0] Cnode1q;
    wire [7:0] AN1q;
    
   top COMP(
    .clkt(clktq),
    .rstt(rsttq),
    
    .SW1(SW1q),
    .udt(udtq),
    .seg(segq),
    .Cnode1(Cnode1q),
    .AN1(AN1q )
    
   
   );
   
    initial 
        begin
        clktq = 1;
        udtq =1;
        end
        
    always   
        begin
        #5 clktq = ~clktq;

        end
    initial 
        begin 
            rsttq = 1;
            
           #10 
            rsttq = 0;
           #100  
            SW1q = 4;
           #100 
           $finish;
        end 
   
    
endmodule
module top_tb(

    );

    reg clktq;
    reg rsttq;
    
    reg [4:0] SW1q;
    reg udtq;
    wire segq;
    wire [6:0] Cnode1q;
    wire [7:0] AN1q;
    
   top COMP(
    .clkt(clktq),
    .rstt(rsttq),
    
    .SW1(SW1q),
    .udt(udtq),
    .seg(segq),
    .Cnode1(Cnode1q),
    .AN1(AN1q )
    
   
   );
   
    initial 
        begin
        clktq = 1;
        udtq =1;
        end
        
    always   
        begin
        #5 clktq = ~clktq;

        end
    initial 
        begin 
            rsttq = 1;
            
           #10 
            rsttq = 0;
           #100  
            SW1q = 4;
           #100 
           $finish;
        end 
   
    
endmodule