data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_first_trivial_design/bdw_work/modules/dut/BASIC/v_rtl/dut_Mul_8Ux3U_11U_1.v
data/verilator_xmls/11ce25b3-51ec-4020-9660-23cd5fb9b549.xml
module dut_Mul_8Ux3U_11U_1 (
	in2,
	in1,
	out1
	);
input [7:0] in2;
input [2:0] in1;
output [10:0] out1;
wire [10:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule
module dut_Mul_8Ux3U_11U_1 (
	in2,
	in1,
	out1
	);

input [7:0] in2;
input [2:0] in1;
output [10:0] out1;
wire [10:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule