data/full_repos/permissive/496266817/tb/tb_romix.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_romix.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #(HALF_PERIOD_CLOCK) clk <= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_romix.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2*num_delay)  reset_n <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_romix.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2)    init <= 1\'b1;\n   ^\n%Error: data/full_repos/permissive/496266817/tb/tb_romix.v:23: Cannot find file containing module: \'romix\'\n romix new_romix(\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/romix\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/romix.v\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/romix.sv\n             romix\n             romix.v\n             romix.sv\n             obj_dir/romix\n             obj_dir/romix.v\n             obj_dir/romix.sv\n%Error: data/full_repos/permissive/496266817/tb/tb_romix.v:33: Cannot find file containing module: \'romix_dpct_1m\'\n romix_dpct_1m old_romix(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_romix.v:58: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                     : ... In instance tb_romix\n   i = $time;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_romix.v:63: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'start_time\' generates 32 bits.\n                                                                     : ... In instance tb_romix\n   $display("Output old romix: %x cycle: %f", old_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_romix.v:83: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                     : ... In instance tb_romix\n   start_time = $time;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_romix.v:90: Operator TASKREF \'reset_task\' expects 8 bits on the Function Argument, but Function Argument\'s CONST \'3\'h5\' generates 3 bits.\n                                                                     : ... In instance tb_romix\n  reset_task(3\'d5);\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_romix();
		reg					clk			;
		reg					init		;
		reg					reset_n		;


		reg		[1023:0] 	in			;



		
	parameter HALF_PERIOD_CLOCK = 10;
		
	wire					keep_input	;
	wire 	[1023: 0] 		out			;	
	wire 	[1023: 0] 		old_out		;
	wire					valid		;
	wire					old_valid	;
	wire					pbk_en		;
	wire					w_done		;
	wire					r_done		;
	romix	new_romix(
		.clk			(clk)				,
		.init			(init)				,
		.reset_n		(reset_n)			,
		.in				(in)				,
		.out			(out)				,
		.keep_input		(keep_input) 		,
		.valid			(valid)
	);
	
	romix_dpct_1m	old_romix(
		.in				(in)				, 
		.out			(old_out)			, 
		.rm_clock		(clk)				, 
		.RST_N			(reset_n)			,
		.rm_start		(init)				, 
		.rm_done		(old_valid)			,
		.pbk_en			(pbk_en)			,
		.w_start		(1'b1)				, 
		.r_start		(1'b1)				, 
		.w_done			(w_done)			, 
		.r_done			(r_done)
	);
	

	integer i;
	integer start_time;
	integer check = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid, old_valid) 
	begin
		if(valid == 1'd1 && check == 1) begin
			i = $time;
			check = 0;
		end
		if(valid == 1'd1 && old_valid == 1'd1) begin
			$display("Output new romix: %x cycle: %f", out, (i-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Output old romix: %x cycle: %f", old_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  	= 1'b0;
			init 	= 1'b0;
			reset_n = 1'b0;
			in		= 1024'he9ff2138b950b9c69e197995cfee0c57f8ebe1798ff3599e9b2117d93a797793b1674ca303fb7309cea97827825d83b2d15e60cc38f6f8b6e5afdc59ac35c677cffc5cfc662e0df12d41e9c2fcf3112a3ae53e26746c2516b18a74531e3391d9f823fa1bac62b14f79013e3321311ff86c9c735267cc92a8c7b61ff535fc2dcf;


		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;
			start_time = $time;
		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule
module tb_romix();

		reg					clk			;
		reg					init		;
		reg					reset_n		;


		reg		[1023:0] 	in			;



		
	parameter HALF_PERIOD_CLOCK = 10;
		
	wire					keep_input	;
	wire 	[1023: 0] 		out			;	
	wire 	[1023: 0] 		old_out		;
	wire					valid		;
	wire					old_valid	;
	wire					pbk_en		;
	wire					w_done		;
	wire					r_done		;
	romix	new_romix(
		.clk			(clk)				,
		.init			(init)				,
		.reset_n		(reset_n)			,
		.in				(in)				,
		.out			(out)				,
		.keep_input		(keep_input) 		,
		.valid			(valid)
	);
	
	romix_dpct_1m	old_romix(
		.in				(in)				, 
		.out			(old_out)			, 
		.rm_clock		(clk)				, 
		.RST_N			(reset_n)			,
		.rm_start		(init)				, 
		.rm_done		(old_valid)			,
		.pbk_en			(pbk_en)			,
		.w_start		(1'b1)				, 
		.r_start		(1'b1)				, 
		.w_done			(w_done)			, 
		.r_done			(r_done)
	);
	

	integer i;
	integer start_time;
	integer check = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid, old_valid) 
	begin
		if(valid == 1'd1 && check == 1) begin
			i = $time;
			check = 0;
		end
		if(valid == 1'd1 && old_valid == 1'd1) begin
			$display("Output new romix: %x cycle: %f", out, (i-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Output old romix: %x cycle: %f", old_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  	= 1'b0;
			init 	= 1'b0;
			reset_n = 1'b0;
			in		= 1024'he9ff2138b950b9c69e197995cfee0c57f8ebe1798ff3599e9b2117d93a797793b1674ca303fb7309cea97827825d83b2d15e60cc38f6f8b6e5afdc59ac35c677cffc5cfc662e0df12d41e9c2fcf3112a3ae53e26746c2516b18a74531e3391d9f823fa1bac62b14f79013e3321311ff86c9c735267cc92a8c7b61ff535fc2dcf;


		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;
			start_time = $time;
		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule