data/full_repos/permissive/518460376/verilog/rtl/rtl/components/cluster_clock_mux2.v
data/verilator_xmls/ceb25efe-c3d1-4b6c-9466-83b33c55eb96.xml
module cluster_clock_mux2 (
	clk0_i,
	clk1_i,
	clk_sel_i,
	clk_o
);
	input wire clk0_i;
	input wire clk1_i;
	input wire clk_sel_i;
	output reg clk_o;
	always @(*)
		if (clk_sel_i == 1'b0)
			clk_o = clk0_i;
		else
			clk_o = clk1_i;
endmodule
module cluster_clock_mux2 (
	clk0_i,
	clk1_i,
	clk_sel_i,
	clk_o
);

	input wire clk0_i;
	input wire clk1_i;
	input wire clk_sel_i;
	output reg clk_o;
	always @(*)
		if (clk_sel_i == 1'b0)
			clk_o = clk0_i;
		else
			clk_o = clk1_i;
endmodule