data/full_repos/permissive/505761772/code/InOutStuff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/InOutStuff.v:30: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'SPI\'\nmodule SPI( input       CLK,\n       ^~~\n                                                                            : ... Top module \'DAC\'\nmodule DAC( input               SCK,\n       ^~~\n                                                                            : ... Top module \'GAIN\'\nmodule GAIN(input       SCK,\n       ^~~~\n                                                                            : ... Top module \'ADC\'\nmodule ADC( input       SCK,\n       ^~~\n                                                                            : ... Top module \'SERIAL_TX\'\nmodule SERIAL_TX (input [7:0]  DATA,\n       ^~~~~~~~~\n                                                                            : ... Top module \'SERIAL_RX\'\nmodule SERIAL_RX (input         CLK,\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'gain\' generates 4 bits.\n                                                                         : ... In instance GAIN\nreg [7:0] data = gain;\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:58: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'AorB\' generates 1 bits.\n                                                                         : ... In instance DAC\n      dataReg <= {8\'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};\n                        ^\n%Error: Exiting due to 3 warning(s)\n'
module SERIAL_TX (input [7:0]  DATA,
                  input        CLK,
                  input        EN,
                  output reg   TX);


parameter baudRate = 13'd5208;

reg [12:0] cnt;
reg EN_old;
reg [7:0] dataReg;
reg [3:0] stateReg;

initial begin
  cnt = 0;
  TX = 1;
  stateReg = 0;
end

always @(posedge CLK) begin
  if(stateReg == 0) begin
    if(EN & !EN_old) begin
      stateReg <= 4'hC;
      cnt <= baudRate;
      dataReg <= DATA;
      TX <= 0;
    end else begin
      TX <= 1;
    end
  end else begin
    if(cnt > 0) cnt <= cnt - 1;
    else begin
      cnt <= baudRate;
      stateReg <= stateReg - 1;
      TX <= dataReg[0];
      dataReg <= {1'bX, dataReg[7:1]};
    end
  end

  EN_old <= EN;
end

endmodule
module SERIAL_TX (input [7:0]  DATA,
                  input        CLK,
                  input        EN,
                  output reg   TX);



parameter baudRate = 13'd5208;

reg [12:0] cnt;
reg EN_old;
reg [7:0] dataReg;
reg [3:0] stateReg;

initial begin
  cnt = 0;
  TX = 1;
  stateReg = 0;
end

always @(posedge CLK) begin
  if(stateReg == 0) begin
    if(EN & !EN_old) begin
      stateReg <= 4'hC;
      cnt <= baudRate;
      dataReg <= DATA;
      TX <= 0;
    end else begin
      TX <= 1;
    end
  end else begin
    if(cnt > 0) cnt <= cnt - 1;
    else begin
      cnt <= baudRate;
      stateReg <= stateReg - 1;
      TX <= dataReg[0];
      dataReg <= {1'bX, dataReg[7:1]};
    end
  end

  EN_old <= EN;
end

endmodule