data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/03_Shift_Registers/08_Shift_register.v
data/verilator_xmls/c34f5633-790e-488c-8d85-abb51028cb61.xml
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output reg [3:0] LEDR
);
    
    MUXDFF my_mux_dff [3:0] (
        .clk({4{KEY[0]}}),
        .w({KEY[3], LEDR[3:1]}),
        .R(SW[3:0]),
        .E({4{KEY[1]}}),
        .L({4{KEY[2]}}),
        .Q(LEDR[3:0])
    );

endmodule
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output reg [3:0] LEDR
);

    
    MUXDFF my_mux_dff [3:0] (
        .clk({4{KEY[0]}}),
        .w({KEY[3], LEDR[3:1]}),
        .R(SW[3:0]),
        .E({4{KEY[1]}}),
        .L({4{KEY[2]}}),
        .Q(LEDR[3:0])
    );

endmodule