data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter ARQ_BUFFER_SIZE = MAX_BURST_LENGTH_MSG\n    ^\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:5: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        reset_q_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mod_tx_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_HEADER_SIZE-1:0] mod_tx_header_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [NOC_PAYLOAD_SIZE-1:0] mod_tx_payload_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mod_tx_stall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        noc_tx_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_HEADER_SIZE-1:0] noc_tx_header_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NOC_PAYLOAD_SIZE-1:0] noc_tx_payload_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        noc_tx_stall_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        noc_rx_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_HEADER_SIZE-1:0] noc_rx_header_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [NOC_PAYLOAD_SIZE-1:0] noc_rx_payload_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        noc_rx_stall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                        mod_rx_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_HEADER_SIZE-1:0] mod_rx_header_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NOC_PAYLOAD_SIZE-1:0] mod_rx_payload_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                        mod_rx_stall_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq.v:67: syntax error, unexpected IDENTIFIER\n    noc_arq_regfile i_noc_arq_regfile (\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module noc_arq #(
    `include "noc_parameter.vh"
    ,parameter ARQ_BUFFER_SIZE = MAX_BURST_LENGTH_MSG
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        mod_tx_wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] mod_tx_header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] mod_tx_payload_i,
    output wire                        mod_tx_stall_o,
    output wire                        noc_tx_wrreq_o,
    output wire  [NOC_HEADER_SIZE-1:0] noc_tx_header_o,
    output wire [NOC_PAYLOAD_SIZE-1:0] noc_tx_payload_o,
    input  wire                        noc_tx_stall_i,


    input  wire                        noc_rx_wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] noc_rx_header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] noc_rx_payload_i,
    output wire                        noc_rx_stall_o,
    output wire                        mod_rx_wrreq_o,
    output wire  [NOC_HEADER_SIZE-1:0] mod_rx_header_o,
    output wire [NOC_PAYLOAD_SIZE-1:0] mod_rx_payload_o,
    input  wire                        mod_rx_stall_i
);



    localparam ARQ_BUFFER_ADDR_WIDTH = $clog2(ARQ_BUFFER_SIZE);

    wire                        reg_tx_wrreq, reg_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] reg_tx_header, reg_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] reg_tx_payload, reg_rx_payload;
    wire                        reg_tx_stall, reg_rx_stall;

    wire                        reg_tx_mux_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] reg_tx_mux_header;
    wire [NOC_PAYLOAD_SIZE-1:0] reg_tx_mux_payload;
    wire                        reg_tx_mux_stall;

    wire                        arq_tx_wrreq, arq_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] arq_tx_header, arq_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] arq_tx_payload, arq_rx_payload;
    wire                        arq_tx_stall, arq_rx_stall;

    wire                        ack_tx_wrreq, ack_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] ack_tx_header, ack_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] ack_tx_payload, ack_rx_payload;
    wire                        ack_tx_stall, ack_rx_stall;

    wire                  [1:0] arq_enable;
    wire                 [31:0] arq_timeout_rx_cycles;
    wire                 [31:0] noc_rx_count;
    wire                 [31:0] noc_rx_drop;

    wire                 [31:0] arq_tx_bvt_mod_wr_ptr;
    wire                 [31:0] arq_tx_bvt_ack_wr_ptr;
    wire                 [31:0] arq_tx_bvt_occ_ptr;
    wire                 [31:0] arq_tx_bvt_rd_ptr;

    wire                 [31:0] arq_rx_status;


    noc_arq_regfile i_noc_arq_regfile (
        .clk_i                   (clk_i),
        .reset_q_i               (reset_q_i),


        .wrreq_i                 (reg_rx_wrreq),
        .header_i                (reg_rx_header),
        .payload_i               (reg_rx_payload),
        .stall_o                 (reg_rx_stall),


        .wrreq_o                 (reg_tx_wrreq),
        .header_o                (reg_tx_header),
        .payload_o               (reg_tx_payload),
        .stall_i                 (reg_tx_stall),


        .arq_enable_o            (arq_enable),
        .arq_timeout_rx_cycles_o (arq_timeout_rx_cycles),
        .noc_rx_count_i          (noc_rx_count),
        .noc_rx_drop_i           (noc_rx_drop),
        .arq_tx_bvt_mod_wr_ptr_i (arq_tx_bvt_mod_wr_ptr),
        .arq_tx_bvt_ack_wr_ptr_i (arq_tx_bvt_ack_wr_ptr),
        .arq_tx_bvt_occ_ptr_i    (arq_tx_bvt_occ_ptr),
        .arq_tx_bvt_rd_ptr_i     (arq_tx_bvt_rd_ptr),
        .arq_rx_status_i         (arq_rx_status)
    );


    noc_arq_2to1mux i_noc_arq_reg_tx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq1_i      (mod_tx_wrreq_i),
        .header1_i     (mod_tx_header_i),
        .payload1_i    (mod_tx_payload_i),
        .stall1_o      (mod_tx_stall_o),


        .wrreq2_i      (reg_tx_wrreq),
        .header2_i     (reg_tx_header),
        .payload2_i    (reg_tx_payload),
        .stall2_o      (reg_tx_stall),


        .wrreq_o       (reg_tx_mux_wrreq),
        .header_o      (reg_tx_mux_header),
        .payload_o     (reg_tx_mux_payload),
        .stall_i       (reg_tx_mux_stall)
    );


    noc_arq_tx #(
        .ARQ_TX_BUFFER_ADDR_WIDTH (ARQ_BUFFER_ADDR_WIDTH+1)
    ) i_noc_arq_tx (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .mod_wrreq_i   (reg_tx_mux_wrreq),
        .mod_header_i  (reg_tx_mux_header),
        .mod_payload_i (reg_tx_mux_payload),
        .mod_stall_o   (reg_tx_mux_stall),
        .noc_wrreq_o   (arq_tx_wrreq),
        .noc_header_o  (arq_tx_header),
        .noc_payload_o (arq_tx_payload),
        .noc_stall_i   (arq_tx_stall),


        .ack_wrreq_i   (ack_rx_wrreq),
        .ack_header_i  (ack_rx_header),
        .ack_payload_i (ack_rx_payload),
        .ack_stall_o   (ack_rx_stall),


        .arq_enable_i            (arq_enable),
        .arq_tx_bvt_mod_wr_ptr_o (arq_tx_bvt_mod_wr_ptr),
        .arq_tx_bvt_ack_wr_ptr_o (arq_tx_bvt_ack_wr_ptr),
        .arq_tx_bvt_occ_ptr_o    (arq_tx_bvt_occ_ptr),
        .arq_tx_bvt_rd_ptr_o     (arq_tx_bvt_rd_ptr)
    );


    noc_arq_2to1mux i_noc_arq_ack_tx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq1_i      (ack_tx_wrreq),
        .header1_i     (ack_tx_header),
        .payload1_i    (ack_tx_payload),
        .stall1_o      (ack_tx_stall),


        .wrreq2_i      (arq_tx_wrreq),
        .header2_i     (arq_tx_header),
        .payload2_i    (arq_tx_payload),
        .stall2_o      (arq_tx_stall),


        .wrreq_o       (noc_tx_wrreq_o),
        .header_o      (noc_tx_header_o),
        .payload_o     (noc_tx_payload_o),
        .stall_i       (noc_tx_stall_i)
    );


    noc_arq_rx #(
        .ARQ_RX_BUFFER_ADDR_WIDTH (ARQ_BUFFER_ADDR_WIDTH)
    ) i_noc_arq_rx (
        .clk_i                   (clk_i),
        .reset_q_i               (reset_q_i),


        .noc_wrreq_i             (arq_rx_wrreq),
        .noc_header_i            (arq_rx_header),
        .noc_payload_i           (arq_rx_payload),
        .noc_stall_o             (arq_rx_stall),
        .mod_wrreq_o             (mod_rx_wrreq_o),
        .mod_header_o            (mod_rx_header_o),
        .mod_payload_o           (mod_rx_payload_o),
        .mod_stall_i             (mod_rx_stall_i),


        .ack_wrreq_o             (ack_tx_wrreq),
        .ack_header_o            (ack_tx_header),
        .ack_payload_o           (ack_tx_payload),
        .ack_stall_i             (ack_tx_stall),


        .reg_wrreq_o             (reg_rx_wrreq),
        .reg_header_o            (reg_rx_header),
        .reg_payload_o           (reg_rx_payload),
        .reg_stall_i             (reg_rx_stall),

        .arq_timeout_rx_cycles_i (arq_timeout_rx_cycles),
        .noc_rx_count_o          (noc_rx_count),
        .noc_rx_drop_o           (noc_rx_drop),
        .arq_rx_status_o         (arq_rx_status)
    );


    noc_arq_1to2mux i_noc_arq_rx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq_i       (noc_rx_wrreq_i),
        .header_i      (noc_rx_header_i),
        .payload_i     (noc_rx_payload_i),
        .stall_o       (noc_rx_stall_o),


        .ack_wrreq_o   (ack_rx_wrreq),
        .ack_header_o  (ack_rx_header),
        .ack_payload_o (ack_rx_payload),
        .ack_stall_i   (ack_rx_stall),


        .wrreq_o       (arq_rx_wrreq),
        .header_o      (arq_rx_header),
        .payload_o     (arq_rx_payload),
        .stall_i       (arq_rx_stall)
    );



endmodule
module noc_arq #(
    `include "noc_parameter.vh"
    ,parameter ARQ_BUFFER_SIZE = MAX_BURST_LENGTH_MSG
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        mod_tx_wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] mod_tx_header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] mod_tx_payload_i,
    output wire                        mod_tx_stall_o,
    output wire                        noc_tx_wrreq_o,
    output wire  [NOC_HEADER_SIZE-1:0] noc_tx_header_o,
    output wire [NOC_PAYLOAD_SIZE-1:0] noc_tx_payload_o,
    input  wire                        noc_tx_stall_i,


    input  wire                        noc_rx_wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] noc_rx_header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] noc_rx_payload_i,
    output wire                        noc_rx_stall_o,
    output wire                        mod_rx_wrreq_o,
    output wire  [NOC_HEADER_SIZE-1:0] mod_rx_header_o,
    output wire [NOC_PAYLOAD_SIZE-1:0] mod_rx_payload_o,
    input  wire                        mod_rx_stall_i
);




    localparam ARQ_BUFFER_ADDR_WIDTH = $clog2(ARQ_BUFFER_SIZE);

    wire                        reg_tx_wrreq, reg_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] reg_tx_header, reg_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] reg_tx_payload, reg_rx_payload;
    wire                        reg_tx_stall, reg_rx_stall;

    wire                        reg_tx_mux_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] reg_tx_mux_header;
    wire [NOC_PAYLOAD_SIZE-1:0] reg_tx_mux_payload;
    wire                        reg_tx_mux_stall;

    wire                        arq_tx_wrreq, arq_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] arq_tx_header, arq_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] arq_tx_payload, arq_rx_payload;
    wire                        arq_tx_stall, arq_rx_stall;

    wire                        ack_tx_wrreq, ack_rx_wrreq;
    wire  [NOC_HEADER_SIZE-1:0] ack_tx_header, ack_rx_header;
    wire [NOC_PAYLOAD_SIZE-1:0] ack_tx_payload, ack_rx_payload;
    wire                        ack_tx_stall, ack_rx_stall;

    wire                  [1:0] arq_enable;
    wire                 [31:0] arq_timeout_rx_cycles;
    wire                 [31:0] noc_rx_count;
    wire                 [31:0] noc_rx_drop;

    wire                 [31:0] arq_tx_bvt_mod_wr_ptr;
    wire                 [31:0] arq_tx_bvt_ack_wr_ptr;
    wire                 [31:0] arq_tx_bvt_occ_ptr;
    wire                 [31:0] arq_tx_bvt_rd_ptr;

    wire                 [31:0] arq_rx_status;


    noc_arq_regfile i_noc_arq_regfile (
        .clk_i                   (clk_i),
        .reset_q_i               (reset_q_i),


        .wrreq_i                 (reg_rx_wrreq),
        .header_i                (reg_rx_header),
        .payload_i               (reg_rx_payload),
        .stall_o                 (reg_rx_stall),


        .wrreq_o                 (reg_tx_wrreq),
        .header_o                (reg_tx_header),
        .payload_o               (reg_tx_payload),
        .stall_i                 (reg_tx_stall),


        .arq_enable_o            (arq_enable),
        .arq_timeout_rx_cycles_o (arq_timeout_rx_cycles),
        .noc_rx_count_i          (noc_rx_count),
        .noc_rx_drop_i           (noc_rx_drop),
        .arq_tx_bvt_mod_wr_ptr_i (arq_tx_bvt_mod_wr_ptr),
        .arq_tx_bvt_ack_wr_ptr_i (arq_tx_bvt_ack_wr_ptr),
        .arq_tx_bvt_occ_ptr_i    (arq_tx_bvt_occ_ptr),
        .arq_tx_bvt_rd_ptr_i     (arq_tx_bvt_rd_ptr),
        .arq_rx_status_i         (arq_rx_status)
    );


    noc_arq_2to1mux i_noc_arq_reg_tx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq1_i      (mod_tx_wrreq_i),
        .header1_i     (mod_tx_header_i),
        .payload1_i    (mod_tx_payload_i),
        .stall1_o      (mod_tx_stall_o),


        .wrreq2_i      (reg_tx_wrreq),
        .header2_i     (reg_tx_header),
        .payload2_i    (reg_tx_payload),
        .stall2_o      (reg_tx_stall),


        .wrreq_o       (reg_tx_mux_wrreq),
        .header_o      (reg_tx_mux_header),
        .payload_o     (reg_tx_mux_payload),
        .stall_i       (reg_tx_mux_stall)
    );


    noc_arq_tx #(
        .ARQ_TX_BUFFER_ADDR_WIDTH (ARQ_BUFFER_ADDR_WIDTH+1)
    ) i_noc_arq_tx (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .mod_wrreq_i   (reg_tx_mux_wrreq),
        .mod_header_i  (reg_tx_mux_header),
        .mod_payload_i (reg_tx_mux_payload),
        .mod_stall_o   (reg_tx_mux_stall),
        .noc_wrreq_o   (arq_tx_wrreq),
        .noc_header_o  (arq_tx_header),
        .noc_payload_o (arq_tx_payload),
        .noc_stall_i   (arq_tx_stall),


        .ack_wrreq_i   (ack_rx_wrreq),
        .ack_header_i  (ack_rx_header),
        .ack_payload_i (ack_rx_payload),
        .ack_stall_o   (ack_rx_stall),


        .arq_enable_i            (arq_enable),
        .arq_tx_bvt_mod_wr_ptr_o (arq_tx_bvt_mod_wr_ptr),
        .arq_tx_bvt_ack_wr_ptr_o (arq_tx_bvt_ack_wr_ptr),
        .arq_tx_bvt_occ_ptr_o    (arq_tx_bvt_occ_ptr),
        .arq_tx_bvt_rd_ptr_o     (arq_tx_bvt_rd_ptr)
    );


    noc_arq_2to1mux i_noc_arq_ack_tx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq1_i      (ack_tx_wrreq),
        .header1_i     (ack_tx_header),
        .payload1_i    (ack_tx_payload),
        .stall1_o      (ack_tx_stall),


        .wrreq2_i      (arq_tx_wrreq),
        .header2_i     (arq_tx_header),
        .payload2_i    (arq_tx_payload),
        .stall2_o      (arq_tx_stall),


        .wrreq_o       (noc_tx_wrreq_o),
        .header_o      (noc_tx_header_o),
        .payload_o     (noc_tx_payload_o),
        .stall_i       (noc_tx_stall_i)
    );


    noc_arq_rx #(
        .ARQ_RX_BUFFER_ADDR_WIDTH (ARQ_BUFFER_ADDR_WIDTH)
    ) i_noc_arq_rx (
        .clk_i                   (clk_i),
        .reset_q_i               (reset_q_i),


        .noc_wrreq_i             (arq_rx_wrreq),
        .noc_header_i            (arq_rx_header),
        .noc_payload_i           (arq_rx_payload),
        .noc_stall_o             (arq_rx_stall),
        .mod_wrreq_o             (mod_rx_wrreq_o),
        .mod_header_o            (mod_rx_header_o),
        .mod_payload_o           (mod_rx_payload_o),
        .mod_stall_i             (mod_rx_stall_i),


        .ack_wrreq_o             (ack_tx_wrreq),
        .ack_header_o            (ack_tx_header),
        .ack_payload_o           (ack_tx_payload),
        .ack_stall_i             (ack_tx_stall),


        .reg_wrreq_o             (reg_rx_wrreq),
        .reg_header_o            (reg_rx_header),
        .reg_payload_o           (reg_rx_payload),
        .reg_stall_i             (reg_rx_stall),

        .arq_timeout_rx_cycles_i (arq_timeout_rx_cycles),
        .noc_rx_count_o          (noc_rx_count),
        .noc_rx_drop_o           (noc_rx_drop),
        .arq_rx_status_o         (arq_rx_status)
    );


    noc_arq_1to2mux i_noc_arq_rx_mux (
        .clk_i         (clk_i),
        .reset_q_i     (reset_q_i),


        .wrreq_i       (noc_rx_wrreq_i),
        .header_i      (noc_rx_header_i),
        .payload_i     (noc_rx_payload_i),
        .stall_o       (noc_rx_stall_o),


        .ack_wrreq_o   (ack_rx_wrreq),
        .ack_header_o  (ack_rx_header),
        .ack_payload_o (ack_rx_payload),
        .ack_stall_i   (ack_rx_stall),


        .wrreq_o       (arq_rx_wrreq),
        .header_o      (arq_rx_header),
        .payload_o     (arq_rx_payload),
        .stall_i       (arq_rx_stall)
    );



endmodule