data/full_repos/permissive/46132596/processor/SingleCycleDatapath/InstructionMemory.v
data/verilator_xmls/b775b698-4d6b-4fd1-83db-e2fdd08ffc91.xml
module InstructionMemory(input clock,
		input clear,
		input[31:0] address,
		output [31:0] instr);

	reg[31:0] content[255:0];
	integer i;
	
	always @(posedge clear, negedge clock)
		if (clear) begin


			for (i = 0; i < 256; i = i + 1)
				content[i] = 0;



		

			content[0] = 32'h00220018;
			content[1] = 32'h0041001A;
			content[2] = 32'h00001810;
			content[3] = 32'h00002012;
		end


	assign instr = address >= 32'h400000 && address < 32'h4004000 ?
			content[(address - 32'h400000) >> 2] : 0;


	always @(instr)
		$display("Fetch at PC %08x: instruction %08x", address, instr);
	
endmodule
module InstructionMemory(input clock,
		input clear,
		input[31:0] address,
		output [31:0] instr);


	reg[31:0] content[255:0];
	integer i;
	
	always @(posedge clear, negedge clock)
		if (clear) begin


			for (i = 0; i < 256; i = i + 1)
				content[i] = 0;



		

			content[0] = 32'h00220018;
			content[1] = 32'h0041001A;
			content[2] = 32'h00001810;
			content[3] = 32'h00002012;
		end


	assign instr = address >= 32'h400000 && address < 32'h4004000 ?
			content[(address - 32'h400000) >> 2] : 0;


	always @(instr)
		$display("Fetch at PC %08x: instruction %08x", address, instr);
	
endmodule