data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_monitor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_monitor.v:64: Unsupported: Ignoring delay on this delayed statement.\n     #500;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_monitor.v:72: Unsupported: Ignoring delay on this delayed statement.\n     #500;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pcx_monitor (
	rclk,
	spc_pcx_req_pq, 
	spc_pcx_data_pa 
	);

    input rclk;
    input [4:0] spc_pcx_req_pq;
    input [123:0] spc_pcx_data_pa;

    parameter GOOD_TRAP_1 = 40'h1000122000;
    parameter GOOD_TRAP_2 = 40'h0000082000;
    parameter GOOD_TRAP_3 = 40'h1A00122000;
    parameter BAD_TRAP_1  = 40'h1000122020;
    parameter BAD_TRAP_2  = 40'h0000082020;
    parameter BAD_TRAP_3  = 40'h1A00122020;

    reg any_req_pa;


    always @(posedge rclk) begin
	any_req_pa <= | spc_pcx_req_pq;
    end




    always @(posedge rclk) begin
	if (any_req_pa && spc_pcx_data_pa[123] &&
	    spc_pcx_data_pa[122:118] == 5'b10000) begin
	    $display("PCX:  %t : I-fetch from address  0x%h", $time,
		spc_pcx_data_pa[103:64]);

	    if (spc_pcx_data_pa[103:64] === GOOD_TRAP_1 ||
		spc_pcx_data_pa[103:64] === GOOD_TRAP_2 ||
		spc_pcx_data_pa[103:64] === GOOD_TRAP_3) begin
	    $display("PCX:  %t : Reached good trap:  Diag Passed\n", $time);
	    #500;
	    $finish;
	    end

	    if (spc_pcx_data_pa[103:64] === BAD_TRAP_1 ||
		spc_pcx_data_pa[103:64] === BAD_TRAP_2 ||
		spc_pcx_data_pa[103:64] === BAD_TRAP_3) begin
	    $display( "PCX:  %t : Reached bad trap: Diag Failed\n", $time);
	    #500;
	    $finish;
	    end
	end
    end

endmodule
module pcx_monitor (
	rclk,
	spc_pcx_req_pq, 
	spc_pcx_data_pa 
	);


    input rclk;
    input [4:0] spc_pcx_req_pq;
    input [123:0] spc_pcx_data_pa;

    parameter GOOD_TRAP_1 = 40'h1000122000;
    parameter GOOD_TRAP_2 = 40'h0000082000;
    parameter GOOD_TRAP_3 = 40'h1A00122000;
    parameter BAD_TRAP_1  = 40'h1000122020;
    parameter BAD_TRAP_2  = 40'h0000082020;
    parameter BAD_TRAP_3  = 40'h1A00122020;

    reg any_req_pa;


    always @(posedge rclk) begin
	any_req_pa <= | spc_pcx_req_pq;
    end




    always @(posedge rclk) begin
	if (any_req_pa && spc_pcx_data_pa[123] &&
	    spc_pcx_data_pa[122:118] == 5'b10000) begin
	    $display("PCX:  %t : I-fetch from address  0x%h", $time,
		spc_pcx_data_pa[103:64]);

	    if (spc_pcx_data_pa[103:64] === GOOD_TRAP_1 ||
		spc_pcx_data_pa[103:64] === GOOD_TRAP_2 ||
		spc_pcx_data_pa[103:64] === GOOD_TRAP_3) begin
	    $display("PCX:  %t : Reached good trap:  Diag Passed\n", $time);
	    #500;
	    $finish;
	    end

	    if (spc_pcx_data_pa[103:64] === BAD_TRAP_1 ||
		spc_pcx_data_pa[103:64] === BAD_TRAP_2 ||
		spc_pcx_data_pa[103:64] === BAD_TRAP_3) begin
	    $display( "PCX:  %t : Reached bad trap: Diag Failed\n", $time);
	    #500;
	    $finish;
	    end
	end
    end

endmodule