data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   always #25 aux_clk = ~aux_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:36: syntax error, unexpected \'@\'\n @(negedge proc_rst);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #1003 clock_ready <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   always #7 clk_fpga = ~clk_fpga;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:43: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("system_control_tb.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:44: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,system_control_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   initial #10000 $finish;\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:51: syntax error, unexpected \'@\'\n @(negedge rl_rst);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1325 rl_done <= 1\'b1;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:58: syntax error, unexpected \'@\'\n @(negedge proc_rst);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/system_control_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #327 clock_ready <= 1\'b1;\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module system_control_tb();
   
   reg 	aux_clk, clk_fpga;
   wire wb_clk, dsp_clk;
   wire wb_rst, dsp_rst, rl_rst, proc_rst;

   reg 	rl_done, clock_ready;
   
   initial aux_clk = 1'b0;
   always #25 aux_clk = ~aux_clk;

   initial clk_fpga = 1'b0;

   initial clock_ready = 1'b0;
   initial
     begin
	@(negedge proc_rst);
	#1003 clock_ready <= 1'b1;
     end

   always #7 clk_fpga = ~clk_fpga;
      
   initial begin
      $dumpfile("system_control_tb.vcd");
      $dumpvars(0,system_control_tb);
   end

   initial #10000 $finish;

   initial
     begin
	@(negedge rl_rst);
	rl_done <= 1'b0;
	#1325 rl_done <= 1'b1;
     end

   initial
     begin
	@(negedge proc_rst);
	clock_ready <= 1'b0;
	#327 clock_ready <= 1'b1;
     end
     
   system_control 
     system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
		    .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
		    .ram_loader_rst_o(rl_rst),
		    .processor_rst_o(proc_rst),
		    .wb_rst_o(wb_rst),
		    .dsp_rst_o(dsp_rst),
		    .ram_loader_done_i(rl_done),
		    .clock_ready_i(clock_ready),
		    .debug_o());
   
endmodule
module system_control_tb();

   
   reg 	aux_clk, clk_fpga;
   wire wb_clk, dsp_clk;
   wire wb_rst, dsp_rst, rl_rst, proc_rst;

   reg 	rl_done, clock_ready;
   
   initial aux_clk = 1'b0;
   always #25 aux_clk = ~aux_clk;

   initial clk_fpga = 1'b0;

   initial clock_ready = 1'b0;
   initial
     begin
	@(negedge proc_rst);
	#1003 clock_ready <= 1'b1;
     end

   always #7 clk_fpga = ~clk_fpga;
      
   initial begin
      $dumpfile("system_control_tb.vcd");
      $dumpvars(0,system_control_tb);
   end

   initial #10000 $finish;

   initial
     begin
	@(negedge rl_rst);
	rl_done <= 1'b0;
	#1325 rl_done <= 1'b1;
     end

   initial
     begin
	@(negedge proc_rst);
	clock_ready <= 1'b0;
	#327 clock_ready <= 1'b1;
     end
     
   system_control 
     system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
		    .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
		    .ram_loader_rst_o(rl_rst),
		    .processor_rst_o(proc_rst),
		    .wb_rst_o(wb_rst),
		    .dsp_rst_o(dsp_rst),
		    .ram_loader_done_i(rl_done),
		    .clock_ready_i(clock_ready),
		    .debug_o());
   
endmodule