data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:19: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time  ApplDelay = 0ps,\n                              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:21: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time  AcqDelay = 0ps,\n                             ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:24: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:26: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:28: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  data_t   data_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:29: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    valid_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:30: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic    ready_o\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_slv.sv:35: syntax error, unexpected always\n    always @(posedge clk_i, negedge rst_ni) begin\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module rand_stream_slv #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps,

  parameter time  AcqDelay = 0ps,

  parameter bit   Enqueue = 1'b0
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  input  data_t   data_i,
  input  logic    valid_i,
  output logic    ready_o
);

  if (Enqueue) begin: gen_queue
    data_t queue[$];
    always @(posedge clk_i, negedge rst_ni) begin
      if (!rst_ni) begin
        queue = {};
      end else begin
        #(AcqDelay);
        if (valid_i && ready_o) begin
          queue.push_back(data_i);
        end
      end
    end
  end

  rand_synch_driver #(
    .data_t         (logic),
    .MinWaitCycles  (MinWaitCycles),
    .MaxWaitCycles  (MaxWaitCycles),
    .ApplDelay      (ApplDelay)
  ) i_ready_driver (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),
    .data_o (ready_o)
  );

`ifndef VERILATOR
  initial begin: validate_params
    assert (AcqDelay > 0ps)
      else $fatal("The acquisition delay must be greater than 0!");
    assert (AcqDelay > ApplDelay)
      else $fatal("The acquisition delay must be greater than the application delay!");
  end
`endif

endmodule
module rand_stream_slv #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps,

  parameter time  AcqDelay = 0ps,

  parameter bit   Enqueue = 1'b0
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  input  data_t   data_i,
  input  logic    valid_i,
  output logic    ready_o
);


  if (Enqueue) begin: gen_queue
    data_t queue[$];
    always @(posedge clk_i, negedge rst_ni) begin
      if (!rst_ni) begin
        queue = {};
      end else begin
        #(AcqDelay);
        if (valid_i && ready_o) begin
          queue.push_back(data_i);
        end
      end
    end
  end

  rand_synch_driver #(
    .data_t         (logic),
    .MinWaitCycles  (MinWaitCycles),
    .MaxWaitCycles  (MaxWaitCycles),
    .ApplDelay      (ApplDelay)
  ) i_ready_driver (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),
    .data_o (ready_o)
  );

`ifndef VERILATOR
  initial begin: validate_params
    assert (AcqDelay > 0ps)
      else $fatal("The acquisition delay must be greater than 0!");
    assert (AcqDelay > ApplDelay)
      else $fatal("The acquisition delay must be greater than the application delay!");
  end
`endif

endmodule