data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:41: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                             : ... In instance RISC_V\n  assign la_dram_select[3:0] = la_data_in[41:37];\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:98: Cannot find file containing module: \'control\'\n control control(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522668124/verilog/rtl,data/full_repos/permissive/522668124/control\n             data/full_repos/permissive/522668124/verilog/rtl,data/full_repos/permissive/522668124/control.v\n             data/full_repos/permissive/522668124/verilog/rtl,data/full_repos/permissive/522668124/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:114: Cannot find file containing module: \'pc\'\n pc pc_module (\n ^~\n%Error: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:129: Cannot find file containing module: \'IMemory\'\n IMemory IMemory (\n ^~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:151: Cannot find file containing module: \'DMemory\'\n DMemory DMemory (\n ^~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/rtl/RISC_V.sv:167: Cannot find file containing module: \'ALU\'\n ALU ALU (\n ^~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module RISC_V 

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif


  input  logic [127:0] la_data_in,
  output logic [127:0] la_data_out,  
  input  logic [127:0] la_oenb,
  
  input  logic clk

);

  logic rst_n;


  
  assign la_data_out[127:96] = 0;
  

  logic [3:0] la_dram_select;
  logic [31:0] la_read_dram_data;
  
  assign la_dram_select[3:0] = la_data_in[41:37];
  assign la_data_out[63:32] = la_read_dram_data[31:0];
  

  logic la_instruction_write;
  logic [3:0] la_instruction_select;
  logic [31:0] la_instruction_input;
  logic [31:0] la_read_iram_data;
  
  assign la_instruction_write = la_data_in[36];
  assign la_instruction_select[3:0] = la_data_in[35:32];
  assign la_instruction_input[31:0] = la_data_in[31:0];
  
  assign la_data_out[31:0] = la_read_iram_data[31:0];
  

  
  logic [4:0] la_reg_select;
  logic [31:0] la_read_reg_data;
  
  assign la_reg_select[4:0] = la_data_in[46:42];
  assign la_data_out[95:64] = la_read_reg_data[31:0];  
  

  assign rst_n = la_data_in[47];
    

	logic mem_write;
	logic reg_write;
	logic jump_jal;
	logic jump_jalr;
	logic branch;
  logic immediate_sel;
	

	logic [31:0] pc;
	

	logic [5:0] instruction_type;
	logic [6:0] opcode;
	logic [4:0] rd;
	logic [4:0] rs1;
	logic [4:0] rs2;
	logic [2:0] funct3;
	logic [6:0] funct7;
	logic [31:0] immediate;
	

	
	logic [31:0] read_data;
	logic [31:0] rs1_data;
	logic [31:0] rs2_data;
	

	
	logic [31:0] alu_output;

	control control(
  

	.clk(clk),
	.rst_n(rst_n),
	.instruction_type(instruction_type),
	.opcode(opcode),

	.mem_write_output(mem_write),
	.reg_write_output(reg_write),
	.jump_jal_output(jump_jal),
	.jump_jalr_output(jump_jalr),
	.branch_output(branch),
  .immediate_sel_output(immediate_sel)
	);

	pc pc_module (
  

	.clk(clk),
	.rst_n(rst_n),
	.rs1_data(rs1_data),
	.immediate(immediate),
	.jump_jal(jump_jal),
	.jump_jalr(jump_jalr),
	.branch(branch),
	.alu_branch(alu_output[0]),

	.pc_out(pc)
	);

	IMemory IMemory (
  

	.clk(clk),
	.rst_n(rst_n),
	.pc(pc),
  .la_instruction_input(la_instruction_input),
  .la_instruction_select(la_instruction_select),
  .la_instruction_write(la_instruction_write),

	.instruction_type_output(instruction_type),
	.opcode(opcode),
	.rd(rd),
	.rs1(rs1),
	.rs2(rs2),
	.funct3(funct3),
	.funct7(funct7),
	.immediate(immediate),
  .la_instruction_read(la_read_iram_data)

	);

	DMemory DMemory (
  

	.clk(clk),
	.rst_n(rst_n),
	.mem_write(mem_write),
	.rd(rd),
	.funct3(funct3),
	.memory_address(alu_output),
	.write_data(rs2_data),
  .la_dram_select(la_dram_select),

	.read_data(read_data),
  .la_read_data(la_read_dram_data)
	);

	ALU ALU (
  

	.clk(clk),
	.rst_n(rst_n),
	.pc(pc),
	.reg_write(reg_write),
	.instruction_type(instruction_type),
	.opcode(opcode),
	.rd(rd),
	.rs1(rs1),
	.rs2(rs2),
	.funct3(funct3),
	.funct7(funct7),
	.immediate(immediate),
  .immediate_sel(immediate_sel),
	.read_data(read_data),
  .la_reg_select(la_reg_select),  
  
		

	.alu_output(alu_output),
	.rs1_data(rs1_data),
	.rs2_data(rs2_data),
  .la_read_data(la_read_reg_data)  
	);
  
 endmodule
module RISC_V 

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif


  input  logic [127:0] la_data_in,
  output logic [127:0] la_data_out,  
  input  logic [127:0] la_oenb,
  
  input  logic clk

);


  logic rst_n;


  
  assign la_data_out[127:96] = 0;
  

  logic [3:0] la_dram_select;
  logic [31:0] la_read_dram_data;
  
  assign la_dram_select[3:0] = la_data_in[41:37];
  assign la_data_out[63:32] = la_read_dram_data[31:0];
  

  logic la_instruction_write;
  logic [3:0] la_instruction_select;
  logic [31:0] la_instruction_input;
  logic [31:0] la_read_iram_data;
  
  assign la_instruction_write = la_data_in[36];
  assign la_instruction_select[3:0] = la_data_in[35:32];
  assign la_instruction_input[31:0] = la_data_in[31:0];
  
  assign la_data_out[31:0] = la_read_iram_data[31:0];
  

  
  logic [4:0] la_reg_select;
  logic [31:0] la_read_reg_data;
  
  assign la_reg_select[4:0] = la_data_in[46:42];
  assign la_data_out[95:64] = la_read_reg_data[31:0];  
  

  assign rst_n = la_data_in[47];
    

	logic mem_write;
	logic reg_write;
	logic jump_jal;
	logic jump_jalr;
	logic branch;
  logic immediate_sel;
	

	logic [31:0] pc;
	

	logic [5:0] instruction_type;
	logic [6:0] opcode;
	logic [4:0] rd;
	logic [4:0] rs1;
	logic [4:0] rs2;
	logic [2:0] funct3;
	logic [6:0] funct7;
	logic [31:0] immediate;
	

	
	logic [31:0] read_data;
	logic [31:0] rs1_data;
	logic [31:0] rs2_data;
	

	
	logic [31:0] alu_output;

	control control(
  

	.clk(clk),
	.rst_n(rst_n),
	.instruction_type(instruction_type),
	.opcode(opcode),

	.mem_write_output(mem_write),
	.reg_write_output(reg_write),
	.jump_jal_output(jump_jal),
	.jump_jalr_output(jump_jalr),
	.branch_output(branch),
  .immediate_sel_output(immediate_sel)
	);

	pc pc_module (
  

	.clk(clk),
	.rst_n(rst_n),
	.rs1_data(rs1_data),
	.immediate(immediate),
	.jump_jal(jump_jal),
	.jump_jalr(jump_jalr),
	.branch(branch),
	.alu_branch(alu_output[0]),

	.pc_out(pc)
	);

	IMemory IMemory (
  

	.clk(clk),
	.rst_n(rst_n),
	.pc(pc),
  .la_instruction_input(la_instruction_input),
  .la_instruction_select(la_instruction_select),
  .la_instruction_write(la_instruction_write),

	.instruction_type_output(instruction_type),
	.opcode(opcode),
	.rd(rd),
	.rs1(rs1),
	.rs2(rs2),
	.funct3(funct3),
	.funct7(funct7),
	.immediate(immediate),
  .la_instruction_read(la_read_iram_data)

	);

	DMemory DMemory (
  

	.clk(clk),
	.rst_n(rst_n),
	.mem_write(mem_write),
	.rd(rd),
	.funct3(funct3),
	.memory_address(alu_output),
	.write_data(rs2_data),
  .la_dram_select(la_dram_select),

	.read_data(read_data),
  .la_read_data(la_read_dram_data)
	);

	ALU ALU (
  

	.clk(clk),
	.rst_n(rst_n),
	.pc(pc),
	.reg_write(reg_write),
	.instruction_type(instruction_type),
	.opcode(opcode),
	.rd(rd),
	.rs1(rs1),
	.rs2(rs2),
	.funct3(funct3),
	.funct7(funct7),
	.immediate(immediate),
  .immediate_sel(immediate_sel),
	.read_data(read_data),
  .la_reg_select(la_reg_select),  
  
		

	.alu_output(alu_output),
	.rs1_data(rs1_data),
	.rs2_data(rs2_data),
  .la_read_data(la_read_reg_data)  
	);
  
 endmodule