data/full_repos/permissive/425175279/MIPS_Multi_Cycle/PC_Counter.v
data/verilator_xmls/410a00bd-533e-4767-b05b-7ebab08e9c2b.xml
module PC_Counter(

    input                       clk,
    input                       rst_n,


    input                       PCEn,
    input                       IorD,
    input               [1:0]   PCSrc,
    input               [25:0]  Jump_low_26Bit,
    input               [31:0]  ALUOut,
    input               [31:0]  ALUResult,
    output              [31:0]  Adr,
    output  reg         [31:0]  PC
);
    reg                 [31:0]  PC_Next;



    assign Adr = IorD ? ALUOut : PC;

    always @(*) begin
        case(PCSrc)
            2'b00: PC_Next = ALUResult;
            2'b01: PC_Next = ALUOut;
            2'b10: PC_Next = {{PC[31:28]}, {Jump_low_26Bit}, 2'b00};
        endcase
    end

    always @(posedge clk) begin
        if(~rst_n)begin
            PC <= 32'b0;
        end
        else if (PCEn) begin

            PC <= PC_Next;
        end
    end

endmodule
module PC_Counter(

    input                       clk,
    input                       rst_n,


    input                       PCEn,
    input                       IorD,
    input               [1:0]   PCSrc,
    input               [25:0]  Jump_low_26Bit,
    input               [31:0]  ALUOut,
    input               [31:0]  ALUResult,
    output              [31:0]  Adr,
    output  reg         [31:0]  PC
);

    reg                 [31:0]  PC_Next;



    assign Adr = IorD ? ALUOut : PC;

    always @(*) begin
        case(PCSrc)
            2'b00: PC_Next = ALUResult;
            2'b01: PC_Next = ALUOut;
            2'b10: PC_Next = {{PC[31:28]}, {Jump_low_26Bit}, 2'b00};
        endcase
    end

    always @(posedge clk) begin
        if(~rst_n)begin
            PC <= 32'b0;
        end
        else if (PCEn) begin

            PC <= PC_Next;
        end
    end

endmodule