data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v:71: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v:79: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/PEDC_tb.v:84: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PEDC_tb();



parameter clk_period = 20;
integer i;


reg tb_clk;
reg tb_start_routine;
reg tb_stop_routine;


wire tb_OuReg_set;
wire tb_pe_reset;



PEDC Pedc(


.PEDC_Clk(tb_clk),
.PEDC_Start_Routine(tb_start_routine),
.PEDC_Stop_Routine(tb_stop_routine),


.PEDC_OutReg_Set(tb_OuReg_set),
.PEDC_Reset(tb_pe_reset)

);



always
begin
		tb_clk=1'b1;
		#(clk_period/2);
		tb_clk=1'b0;
		#(clk_period/2);
end


initial
begin
	tb_start_routine<=0;
	tb_stop_routine<=0;
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_start_routine<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_start_routine<=0;
	
	for(i=0;i<5;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
	end
	
	tb_stop_routine<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_stop_routine<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	
	$stop;
	
	
end




endmodule
module PEDC_tb();




parameter clk_period = 20;
integer i;


reg tb_clk;
reg tb_start_routine;
reg tb_stop_routine;


wire tb_OuReg_set;
wire tb_pe_reset;



PEDC Pedc(


.PEDC_Clk(tb_clk),
.PEDC_Start_Routine(tb_start_routine),
.PEDC_Stop_Routine(tb_stop_routine),


.PEDC_OutReg_Set(tb_OuReg_set),
.PEDC_Reset(tb_pe_reset)

);



always
begin
		tb_clk=1'b1;
		#(clk_period/2);
		tb_clk=1'b0;
		#(clk_period/2);
end


initial
begin
	tb_start_routine<=0;
	tb_stop_routine<=0;
	
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_start_routine<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_start_routine<=0;
	
	for(i=0;i<5;i=i+1)begin
		@(negedge tb_clk)
		@(posedge tb_clk);
	end
	
	tb_stop_routine<=1;
	@(negedge tb_clk)
	@(posedge tb_clk)
	tb_stop_routine<=0;
	@(negedge tb_clk)
	@(posedge tb_clk)
	@(negedge tb_clk)
	@(posedge tb_clk)
	
	
	$stop;
	
	
end




endmodule