data/full_repos/permissive/455940806/designs/silice_vga_test.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/455940806/designs/silice_vga_test.v:57: Cell has missing pin: \'out_done\'\nM_main __main(\n       ^~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/455940806/designs/silice_vga_test.v:57: Cell has missing pin: \'out_clock\'\nM_main __main(\n       ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/455940806/designs/silice_vga_test.v:369: Cell has missing pin: \'out_clock\'\nM_vga__vga_driver vga_driver (\n                  ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/455940806/designs/silice_vga_test.v:378: Cell has missing pin: \'out_clock\'\nM_frame_display__display display (\n                         ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n'
module M_frame_display__display (
in_pix_x,
in_pix_y,
in_pix_active,
in_pix_vblank,
out_pix_red,
out_pix_green,
out_pix_blue,
out_done,
reset,
out_clock,
clock
);
input  [9:0] in_pix_x;
input  [9:0] in_pix_y;
input  [0:0] in_pix_active;
input  [0:0] in_pix_vblank;
output  [5:0] out_pix_red;
output  [5:0] out_pix_green;
output  [5:0] out_pix_blue;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
reg  [5:0] _t_pix_red;
reg  [5:0] _t_pix_green;
reg  [5:0] _t_pix_blue;

reg  [2:0] _d_index,_q_index = 5;
reg  _autorun = 0;
assign out_pix_red = _t_pix_red;
assign out_pix_green = _t_pix_green;
assign out_pix_blue = _t_pix_blue;
assign out_done = (_q_index == 5) & _autorun;



`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (out_done));
`endif
always @* begin
_d_index = _q_index;

_t_pix_red = 0;
_t_pix_green = 0;
_t_pix_blue = 0;
(* full_case *)
case (_q_index)
0: begin

_d_index = 1;
end
1: begin

if (1) begin


_d_index = 3;
end else begin
_d_index = 2;
end
end
3: begin

if (in_pix_vblank==0) begin


if (in_pix_active) begin


_t_pix_blue = in_pix_x[4+:6];
_t_pix_green = in_pix_y[4+:6];
_t_pix_red = in_pix_x[1+:6];

end else begin

end


_d_index = 3;
end else begin
_d_index = 4;
end
end
2: begin

_d_index = 5;
end
4: begin

if (in_pix_vblank==1) begin



_d_index = 4;
end else begin
_d_index = 1;
end
end
5: begin
end
default: begin 
_d_index = {3{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase

end

always @(posedge clock) begin
_q_index <= reset ? 5 : ( ~_autorun ? 0 : _d_index);
_autorun <= reset ? 0 : 1;
end

endmodule
module M_frame_display__display (
in_pix_x,
in_pix_y,
in_pix_active,
in_pix_vblank,
out_pix_red,
out_pix_green,
out_pix_blue,
out_done,
reset,
out_clock,
clock
);

input  [9:0] in_pix_x;
input  [9:0] in_pix_y;
input  [0:0] in_pix_active;
input  [0:0] in_pix_vblank;
output  [5:0] out_pix_red;
output  [5:0] out_pix_green;
output  [5:0] out_pix_blue;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
reg  [5:0] _t_pix_red;
reg  [5:0] _t_pix_green;
reg  [5:0] _t_pix_blue;

reg  [2:0] _d_index,_q_index = 5;
reg  _autorun = 0;
assign out_pix_red = _t_pix_red;
assign out_pix_green = _t_pix_green;
assign out_pix_blue = _t_pix_blue;
assign out_done = (_q_index == 5) & _autorun;



`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (out_done));
`endif
always @* begin
_d_index = _q_index;

_t_pix_red = 0;
_t_pix_green = 0;
_t_pix_blue = 0;
(* full_case *)
case (_q_index)
0: begin

_d_index = 1;
end
1: begin

if (1) begin


_d_index = 3;
end else begin
_d_index = 2;
end
end
3: begin

if (in_pix_vblank==0) begin


if (in_pix_active) begin


_t_pix_blue = in_pix_x[4+:6];
_t_pix_green = in_pix_y[4+:6];
_t_pix_red = in_pix_x[1+:6];

end else begin

end


_d_index = 3;
end else begin
_d_index = 4;
end
end
2: begin

_d_index = 5;
end
4: begin

if (in_pix_vblank==1) begin



_d_index = 4;
end else begin
_d_index = 1;
end
end
5: begin
end
default: begin 
_d_index = {3{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase

end

always @(posedge clock) begin
_q_index <= reset ? 5 : ( ~_autorun ? 0 : _d_index);
_autorun <= reset ? 0 : 1;
end

endmodule