data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/intfmux6.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/intfmux6.v:128: Cannot find file containing module: 'gen_syn'\ngen_syn igen_syn\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/gen_syn\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/gen_syn.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/gen_syn.sv\n             gen_syn\n             gen_syn.v\n             gen_syn.sv\n             obj_dir/gen_syn\n             obj_dir/gen_syn.v\n             obj_dir/gen_syn.sv\n%Error: Exiting due to 1 error(s)\n"
module intfmux6
    (
     rst_,
     iclk155,
     iclk38,
     iclk4d86,
     
     idat,
          
     odat,
     osyn
     );




parameter   LINEBIT = 12;
parameter   MUX     = 6;
parameter   BITTS   = 3;
parameter   MAXTS   = 4;


parameter   DATABIT = LINEBIT*MUX;
parameter   NULL    = (9-MUX)*LINEBIT;



input                rst_;
input                iclk155,iclk38,iclk4d86;

input [DATABIT-1:0]  idat;

output [LINEBIT-1:0] odat;
output               osyn;


wire                 osyn_gen;
gen_syn igen_syn
    (
     .rst_      (rst_),

     .iclk155   (iclk155),
     .iclk4d86  (iclk4d86),
     .iclk38    (iclk38),

     .osyn      (osyn_gen)

     );







reg [2:0] cntph;
wire      endcntph;
assign    endcntph = (cntph == (MUX-1));

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_)   cntph <= 3'd0;
    else if(osyn_gen)   cntph <= 3'd1;

    else                cntph <= cntph + 1'b1;
    end

wire [9*LINEBIT-1:0] idatpro;
assign               idatpro = {idat,{NULL{1'b0}}};

reg [LINEBIT-1:0] odat;
always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) odat <= {LINEBIT{1'b0}};

    else    
        begin

        if(cntph == 3'd1)       odat <= idatpro[(9*LINEBIT-1):(8*LINEBIT)];
        else if(cntph == 3'd2)  odat <= idatpro[(8*LINEBIT-1):(7*LINEBIT)];
        else if(cntph == 3'd3)  odat <= idatpro[(7*LINEBIT-1):(6*LINEBIT)];
        else if(cntph == 3'd4)  odat <= idatpro[(6*LINEBIT-1):(5*LINEBIT)];
        else if(cntph == 3'd5)  odat <= idatpro[(5*LINEBIT-1):(4*LINEBIT)];
        else if(cntph == 3'd6)  odat <= idatpro[(4*LINEBIT-1):(3*LINEBIT)];
        else if(cntph == 3'd7)  odat <= idatpro[(3*LINEBIT-1):(2*LINEBIT)];
        else if(cntph == 3'd0)  odat <= idatpro[(2*LINEBIT-1):(1*LINEBIT)];
        end
    end

reg     osyn;
always @(posedge iclk38 or negedge rst_)
    if(!rst_)   osyn <= 1'b0;
    else        osyn <= (cntph == 3'd1);


endmodule
module intfmux6
    (
     rst_,
     iclk155,
     iclk38,
     iclk4d86,
     
     idat,
          
     odat,
     osyn
     );





parameter   LINEBIT = 12;
parameter   MUX     = 6;
parameter   BITTS   = 3;
parameter   MAXTS   = 4;


parameter   DATABIT = LINEBIT*MUX;
parameter   NULL    = (9-MUX)*LINEBIT;



input                rst_;
input                iclk155,iclk38,iclk4d86;

input [DATABIT-1:0]  idat;

output [LINEBIT-1:0] odat;
output               osyn;


wire                 osyn_gen;
gen_syn igen_syn
    (
     .rst_      (rst_),

     .iclk155   (iclk155),
     .iclk4d86  (iclk4d86),
     .iclk38    (iclk38),

     .osyn      (osyn_gen)

     );







reg [2:0] cntph;
wire      endcntph;
assign    endcntph = (cntph == (MUX-1));

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_)   cntph <= 3'd0;
    else if(osyn_gen)   cntph <= 3'd1;

    else                cntph <= cntph + 1'b1;
    end

wire [9*LINEBIT-1:0] idatpro;
assign               idatpro = {idat,{NULL{1'b0}}};

reg [LINEBIT-1:0] odat;
always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) odat <= {LINEBIT{1'b0}};

    else    
        begin

        if(cntph == 3'd1)       odat <= idatpro[(9*LINEBIT-1):(8*LINEBIT)];
        else if(cntph == 3'd2)  odat <= idatpro[(8*LINEBIT-1):(7*LINEBIT)];
        else if(cntph == 3'd3)  odat <= idatpro[(7*LINEBIT-1):(6*LINEBIT)];
        else if(cntph == 3'd4)  odat <= idatpro[(6*LINEBIT-1):(5*LINEBIT)];
        else if(cntph == 3'd5)  odat <= idatpro[(5*LINEBIT-1):(4*LINEBIT)];
        else if(cntph == 3'd6)  odat <= idatpro[(4*LINEBIT-1):(3*LINEBIT)];
        else if(cntph == 3'd7)  odat <= idatpro[(3*LINEBIT-1):(2*LINEBIT)];
        else if(cntph == 3'd0)  odat <= idatpro[(2*LINEBIT-1):(1*LINEBIT)];
        end
    end

reg     osyn;
always @(posedge iclk38 or negedge rst_)
    if(!rst_)   osyn <= 1'b0;
    else        osyn <= (cntph == 3'd1);


endmodule