data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v
1: b'%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:28: Cannot find include file: hub.v\n `include "hub.v" \n          ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.v\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.sv\n             hub.v\n             hub.v.v\n             hub.v.sv\n             obj_dir/hub.v\n             obj_dir/hub.v.v\n             obj_dir/hub.v.sv\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:63: syntax error, unexpected \'@\'\n         @( clk_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:87: syntax error, unexpected \'@\'\n         @( clk_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:91: Unsupported: Ignoring delay on this delayed statement.\n         #clk_firstHalf;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:103: Unsupported: Ignoring delay on this delayed statement.\n         #clk_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:134: syntax error, unexpected \'@\'\n         @( rst_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:158: syntax error, unexpected \'@\'\n         @( rst_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:162: Unsupported: Ignoring delay on this delayed statement.\n         #rst_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:174: Unsupported: Ignoring delay on this delayed statement.\n         #rst_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:205: syntax error, unexpected \'@\'\n         @( add_one_x_vld_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:229: syntax error, unexpected \'@\'\n         @( add_one_x_vld_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:233: Unsupported: Ignoring delay on this delayed statement.\n         #add_one_x_vld_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:245: Unsupported: Ignoring delay on this delayed statement.\n         #add_one_x_vld_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:276: syntax error, unexpected \'@\'\n         @( add_one_return_busy_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:300: syntax error, unexpected \'@\'\n         @( add_one_return_busy_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:304: Unsupported: Ignoring delay on this delayed statement.\n         #add_one_return_busy_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/add_one_cosim.v:316: Unsupported: Ignoring delay on this delayed statement.\n         #add_one_return_busy_secondHalf;\n         ^\n%Error: Exiting due to 9 error(s), 8 warning(s)\n'
module add_one_cosim;

	reg clk;
	reg rst;
	wire add_one_x_busy;
	reg add_one_x_vld;
	reg[31:0] add_one_x_data;
	reg add_one_return_busy;
	wire add_one_return_vld;
	wire[31:0] add_one_return_data;


	`include "hub.v"

	add_one add_one0( .clk(clk),
	 .rst(rst),
	 .add_one_x_busy(add_one_x_busy),
	 .add_one_x_vld(add_one_x_vld),
	 .add_one_x_data(add_one_x_data),
	 .add_one_return_busy(add_one_return_busy),
	 .add_one_return_vld(add_one_return_vld),
	 .add_one_return_data(add_one_return_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( add_one0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( add_one0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg add_one_x_vld_firstEdge;
	reg add_one_x_vld_initialized;
	reg add_one_x_vld_started;
	real add_one_x_vld_startTime;
	real add_one_x_vld_firstHalf;
	real add_one_x_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    add_one_x_vld_firstEdge = 1'b1;
	    add_one_x_vld_startTime = 0.000;
	    add_one_x_vld_firstHalf = 5.000;
	    add_one_x_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( add_one_x_vld_initialized !== 1'b1 )
	        @( add_one_x_vld_initialized );
	
	    if ( add_one_x_vld_startTime > 0.0 ) begin
	        add_one_x_vld_started = #add_one_x_vld_startTime 1;
	    end
	    else begin
	        add_one_x_vld_started = 1;
	    end
	end
	

	always @( add_one0.add_one_x_vld ) begin
	    if ( add_one_x_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( add_one_x_vld_started !== 1'b1 )
	        @( add_one_x_vld_started );
	
	    add_one_x_vld <= add_one_x_vld_firstEdge;
	    if ( add_one_x_vld_firstHalf > 0.0 ) begin
	        #add_one_x_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        add_one_x_vld = ~add_one_x_vld_firstEdge;
	    end
	    else begin
	        add_one_x_vld = ~add_one_x_vld_firstEdge;
	    end
	    if ( add_one_x_vld_secondHalf > 0.0 ) begin
	        #add_one_x_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg add_one_return_busy_firstEdge;
	reg add_one_return_busy_initialized;
	reg add_one_return_busy_started;
	real add_one_return_busy_startTime;
	real add_one_return_busy_firstHalf;
	real add_one_return_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    add_one_return_busy_firstEdge = 1'b1;
	    add_one_return_busy_startTime = 0.000;
	    add_one_return_busy_firstHalf = 5.000;
	    add_one_return_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( add_one_return_busy_initialized !== 1'b1 )
	        @( add_one_return_busy_initialized );
	
	    if ( add_one_return_busy_startTime > 0.0 ) begin
	        add_one_return_busy_started = #add_one_return_busy_startTime 1;
	    end
	    else begin
	        add_one_return_busy_started = 1;
	    end
	end
	

	always @( add_one0.add_one_return_busy ) begin
	    if ( add_one_return_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( add_one_return_busy_started !== 1'b1 )
	        @( add_one_return_busy_started );
	
	    add_one_return_busy <= add_one_return_busy_firstEdge;
	    if ( add_one_return_busy_firstHalf > 0.0 ) begin
	        #add_one_return_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        add_one_return_busy = ~add_one_return_busy_firstEdge;
	    end
	    else begin
	        add_one_return_busy = ~add_one_return_busy_firstEdge;
	    end
	    if ( add_one_return_busy_secondHalf > 0.0 ) begin
	        #add_one_return_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule
module add_one_cosim;


	reg clk;
	reg rst;
	wire add_one_x_busy;
	reg add_one_x_vld;
	reg[31:0] add_one_x_data;
	reg add_one_return_busy;
	wire add_one_return_vld;
	wire[31:0] add_one_return_data;


	`include "hub.v"

	add_one add_one0( .clk(clk),
	 .rst(rst),
	 .add_one_x_busy(add_one_x_busy),
	 .add_one_x_vld(add_one_x_vld),
	 .add_one_x_data(add_one_x_data),
	 .add_one_return_busy(add_one_return_busy),
	 .add_one_return_vld(add_one_return_vld),
	 .add_one_return_data(add_one_return_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( add_one0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( add_one0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg add_one_x_vld_firstEdge;
	reg add_one_x_vld_initialized;
	reg add_one_x_vld_started;
	real add_one_x_vld_startTime;
	real add_one_x_vld_firstHalf;
	real add_one_x_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    add_one_x_vld_firstEdge = 1'b1;
	    add_one_x_vld_startTime = 0.000;
	    add_one_x_vld_firstHalf = 5.000;
	    add_one_x_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( add_one_x_vld_initialized !== 1'b1 )
	        @( add_one_x_vld_initialized );
	
	    if ( add_one_x_vld_startTime > 0.0 ) begin
	        add_one_x_vld_started = #add_one_x_vld_startTime 1;
	    end
	    else begin
	        add_one_x_vld_started = 1;
	    end
	end
	

	always @( add_one0.add_one_x_vld ) begin
	    if ( add_one_x_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( add_one_x_vld_started !== 1'b1 )
	        @( add_one_x_vld_started );
	
	    add_one_x_vld <= add_one_x_vld_firstEdge;
	    if ( add_one_x_vld_firstHalf > 0.0 ) begin
	        #add_one_x_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        add_one_x_vld = ~add_one_x_vld_firstEdge;
	    end
	    else begin
	        add_one_x_vld = ~add_one_x_vld_firstEdge;
	    end
	    if ( add_one_x_vld_secondHalf > 0.0 ) begin
	        #add_one_x_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg add_one_return_busy_firstEdge;
	reg add_one_return_busy_initialized;
	reg add_one_return_busy_started;
	real add_one_return_busy_startTime;
	real add_one_return_busy_firstHalf;
	real add_one_return_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    add_one_return_busy_firstEdge = 1'b1;
	    add_one_return_busy_startTime = 0.000;
	    add_one_return_busy_firstHalf = 5.000;
	    add_one_return_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( add_one_return_busy_initialized !== 1'b1 )
	        @( add_one_return_busy_initialized );
	
	    if ( add_one_return_busy_startTime > 0.0 ) begin
	        add_one_return_busy_started = #add_one_return_busy_startTime 1;
	    end
	    else begin
	        add_one_return_busy_started = 1;
	    end
	end
	

	always @( add_one0.add_one_return_busy ) begin
	    if ( add_one_return_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( add_one_return_busy_started !== 1'b1 )
	        @( add_one_return_busy_started );
	
	    add_one_return_busy <= add_one_return_busy_firstEdge;
	    if ( add_one_return_busy_firstHalf > 0.0 ) begin
	        #add_one_return_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        add_one_return_busy = ~add_one_return_busy_firstEdge;
	    end
	    else begin
	        add_one_return_busy = ~add_one_return_busy_firstEdge;
	    end
	    if ( add_one_return_busy_secondHalf > 0.0 ) begin
	        #add_one_return_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule