data/full_repos/permissive/518304758/iiitb_apb.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/518304758/iiitb_apb.v:213: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'apb_master\'\nmodule apb_master(\n       ^~~~~~~~~~\n                                                                       : ... Top module \'apb_slave\'\nmodule apb_slave(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:243: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance apb_slave\n  reg [31:0]apb_rdata=1\'b0;\n                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:338: Bit extraction of array[31:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance apb_slave\n                 apb_rdata = mem[apb_addr];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:342: Bit extraction of array[31:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance apb_slave\n                 mem[apb_addr] = apb_wdata;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:82: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                   : ... In instance apb_master\n       present_state<=IDLE;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:88: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                   : ... In instance apb_master\n    if( (present_state == ACCESS) && (apb_ready != 1))\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:106: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state=IDLE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:110: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'SETUP\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = SETUP;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:114: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n               next_state=IDLE;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:126: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n            next_state = ACCESS;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:148: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n               next_state = IDLE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:154: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = IDLE;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:158: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = ACCESS;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:178: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n           next_state=IDLE;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'SETUP\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:186: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      present_state <= IDLE;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:194: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n    if( (present_state == ACCESS) && (apb_ready == 1) )\n                       ^~\n%Error: Exiting due to 19 warning(s)\n'
module apb_slave(
                 apb_clk,
                 apb_reset,
                 apb_addr,
                 apb_write,
                 apb_en,
                 apb_wdata,
                 apb_rdata,
                 apb_selx,
                 apb_ready,
                 apb_slverr,
  				 wait_cycle
                );
 

 
  input apb_clk;
  input apb_reset;
  input [7:0]apb_addr;
  input [31:0]apb_wdata;
  input apb_en;
  output [31:0]apb_rdata;
  output apb_ready;
  output apb_slverr;
  input apb_selx;
  input apb_write;
  input [31:0]wait_cycle;
 

   
  reg [31:0]apb_rdata=1'b0;
  reg [1:0]present_state;
  reg [1:0]next_state;
  reg [31:0]mem[31:0];
  reg apb_ready;
  reg apb_slverr;
 

 
  parameter [1:0]IDLE=2'b00;
  parameter [1:0]SETUP=2'b01;
  parameter [1:0]ACCESS=2'b10;


 
  reg  [31:0] l_cnt;
 
  initial
  begin

      l_cnt = 0;
  end
 

 
  always@(posedge apb_clk) begin
    if(apb_reset)
      present_state<=IDLE;
    else
      present_state<=next_state;
   
    if( (present_state == IDLE) && (apb_selx == 1))
    begin
       l_cnt <= l_cnt + 1;    
    end
    else
    begin
       l_cnt <= 0;    
    end
  end


 
  always@(*) begin
    case(present_state)      
      IDLE:
      begin
          if( (apb_selx == 1) && (l_cnt >= wait_cycle))
          begin          
              next_state = SETUP;          
          end
          else
          begin
            next_state = IDLE;            
          end
 
          apb_ready  = 0;  
          apb_slverr = 0;    
         
      end
      SETUP:
      begin
         apb_ready = 0;
         apb_slverr = 0;    
         next_state = ACCESS;
         
         if(apb_selx == 0)
         begin
             next_state = IDLE;
         end        
      end      
      ACCESS:
      begin
          if( (apb_selx == 1) && (apb_en == 1))
          begin
              next_state = IDLE;
          end
          else if((apb_selx == 1) && (apb_en == 0))
          begin
            next_state = ACCESS;
          end
          else
          begin
            next_state = IDLE;
          end

          apb_ready = 1;          
          if( (apb_selx == 1) && (apb_en == 1))
          begin
             if(apb_addr > 31)
             begin
                apb_slverr = 1;
             end
             else if(apb_write == 0)
             begin
                 apb_rdata = mem[apb_addr];
             end
             else if(apb_write == 1)
             begin
                 mem[apb_addr] = apb_wdata;
             end
             else
             begin
                apb_slverr = 1;
             end
          end
      end
      default :
      begin
        next_state=IDLE;
      end

    endcase
  end    
endmodule
module apb_slave(
                 apb_clk,
                 apb_reset,
                 apb_addr,
                 apb_write,
                 apb_en,
                 apb_wdata,
                 apb_rdata,
                 apb_selx,
                 apb_ready,
                 apb_slverr,
  				 wait_cycle
                );

 

 
  input apb_clk;
  input apb_reset;
  input [7:0]apb_addr;
  input [31:0]apb_wdata;
  input apb_en;
  output [31:0]apb_rdata;
  output apb_ready;
  output apb_slverr;
  input apb_selx;
  input apb_write;
  input [31:0]wait_cycle;
 

   
  reg [31:0]apb_rdata=1'b0;
  reg [1:0]present_state;
  reg [1:0]next_state;
  reg [31:0]mem[31:0];
  reg apb_ready;
  reg apb_slverr;
 

 
  parameter [1:0]IDLE=2'b00;
  parameter [1:0]SETUP=2'b01;
  parameter [1:0]ACCESS=2'b10;


 
  reg  [31:0] l_cnt;
 
  initial
  begin

      l_cnt = 0;
  end
 

 
  always@(posedge apb_clk) begin
    if(apb_reset)
      present_state<=IDLE;
    else
      present_state<=next_state;
   
    if( (present_state == IDLE) && (apb_selx == 1))
    begin
       l_cnt <= l_cnt + 1;    
    end
    else
    begin
       l_cnt <= 0;    
    end
  end


 
  always@(*) begin
    case(present_state)      
      IDLE:
      begin
          if( (apb_selx == 1) && (l_cnt >= wait_cycle))
          begin          
              next_state = SETUP;          
          end
          else
          begin
            next_state = IDLE;            
          end
 
          apb_ready  = 0;  
          apb_slverr = 0;    
         
      end
      SETUP:
      begin
         apb_ready = 0;
         apb_slverr = 0;    
         next_state = ACCESS;
         
         if(apb_selx == 0)
         begin
             next_state = IDLE;
         end        
      end      
      ACCESS:
      begin
          if( (apb_selx == 1) && (apb_en == 1))
          begin
              next_state = IDLE;
          end
          else if((apb_selx == 1) && (apb_en == 0))
          begin
            next_state = ACCESS;
          end
          else
          begin
            next_state = IDLE;
          end

          apb_ready = 1;          
          if( (apb_selx == 1) && (apb_en == 1))
          begin
             if(apb_addr > 31)
             begin
                apb_slverr = 1;
             end
             else if(apb_write == 0)
             begin
                 apb_rdata = mem[apb_addr];
             end
             else if(apb_write == 1)
             begin
                 mem[apb_addr] = apb_wdata;
             end
             else
             begin
                apb_slverr = 1;
             end
          end
      end
      default :
      begin
        next_state=IDLE;
      end

    endcase
  end    
endmodule