data/full_repos/permissive/504482123/ahbmaster.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/504482123/ahbmaster.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504482123/ahbmaster.v:39: syntax error, unexpected \'@\'\n   @(posedge HCLK);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/504482123/ahbmaster.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/504482123/ahbmaster.v:45: syntax error, unexpected \'@\'\n    @(posedge HCLK)\n    ^\n%Error: data/full_repos/permissive/504482123/ahbmaster.v:67: syntax error, unexpected \'@\'\n    @(posedge HCLK)\n    ^\n%Error: data/full_repos/permissive/504482123/ahbmaster.v:73: syntax error, unexpected end\nend\n^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module ahbmaster(
                    HCLK,
                    HRESETn,
                    HWRITE,
                    HREADYin,
                    HADDR,
                    HWDATA,
                    HRDATA,
                    HRESP,
                    HREADYout,
                    HTRANS
                );

parameter NONSEQ=2'b10,   SEQ=2'b11,
	      IDLE=2'b00,	  WAIT=2'b01;


input HCLK,HRESETn;
input HREADYout;
input [1:0]HRESP;
input [31:0] HRDATA;


output reg HREADYin,HWRITE;
output reg [1:0]HTRANS;
output reg [31:0] HADDR,HWDATA;


task delay();
begin
    #1;
end
endtask



task singleread();
begin
   @(posedge HCLK);
   #1;
    HADDR=32'h8000_0001;
    HWRITE=1'b0;
    HTRANS=NONSEQ;
    HREADYin=1'b1;
    @(posedge HCLK)
    #1
    begin

        HTRANS=IDLE;
    end
end
endtask




task singlewrite();
begin
    @(posedge HCLK)
    #1;
    begin
    HADDR=31'h8000_1100;
    HWRITE=1'b1;
    HTRANS=NONSEQ;
    HREADYin=1'b1;
    end
    @(posedge HCLK)
    #1
    begin
        HTRANS=IDLE;
        HWDATA=$random()%100;
    end
end
endtask

endmodule
module ahbmaster(
                    HCLK,
                    HRESETn,
                    HWRITE,
                    HREADYin,
                    HADDR,
                    HWDATA,
                    HRDATA,
                    HRESP,
                    HREADYout,
                    HTRANS
                );


parameter NONSEQ=2'b10,   SEQ=2'b11,
	      IDLE=2'b00,	  WAIT=2'b01;


input HCLK,HRESETn;
input HREADYout;
input [1:0]HRESP;
input [31:0] HRDATA;


output reg HREADYin,HWRITE;
output reg [1:0]HTRANS;
output reg [31:0] HADDR,HWDATA;


task delay();
begin
    #1;
end
endtask



task singleread();
begin
   @(posedge HCLK);
   #1;
    HADDR=32'h8000_0001;
    HWRITE=1'b0;
    HTRANS=NONSEQ;
    HREADYin=1'b1;
    @(posedge HCLK)
    #1
    begin

        HTRANS=IDLE;
    end
end
endtask




task singlewrite();
begin
    @(posedge HCLK)
    #1;
    begin
    HADDR=31'h8000_1100;
    HWRITE=1'b1;
    HTRANS=NONSEQ;
    HREADYin=1'b1;
    end
    @(posedge HCLK)
    #1
    begin
        HTRANS=IDLE;
        HWDATA=$random()%100;
    end
end
endtask

endmodule