data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Q2a FSM(1).v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Q2a\n%Error: Cannot find file containing module: FSM(1).v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output [3:1] g
); 
	parameter A=0,B=1,C=2,D=3;
    reg [2:0] state,next;
    always @(*) begin
        case(state)
            A: begin
                casex(r)
                    3'bxx1:next=B;
                    3'bx10:next=C;
                    3'b100:next=D;
                    default: next=A;
                endcase
            end
            B: next = r[1] ? B:A;
            C: next = r[2] ? C:A;
            D: next = r[3] ? D:A;
        endcase
    end
    
    always @(posedge clk)
        begin
            if(!resetn) state<=A;
            else state<=next;
        end
    
    assign g = {state==D,state==C,state==B}; 
    
endmodule
module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output [3:1] g
);
 
	parameter A=0,B=1,C=2,D=3;
    reg [2:0] state,next;
    always @(*) begin
        case(state)
            A: begin
                casex(r)
                    3'bxx1:next=B;
                    3'bx10:next=C;
                    3'b100:next=D;
                    default: next=A;
                endcase
            end
            B: next = r[1] ? B:A;
            C: next = r[2] ? C:A;
            D: next = r[3] ? D:A;
        endcase
    end
    
    always @(posedge clk)
        begin
            if(!resetn) state<=A;
            else state<=next;
        end
    
    assign g = {state==D,state==C,state==B}; 
    
endmodule