data/full_repos/permissive/406635962/src/rtl/exu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:13: Define or directive not defined: \'`INSTR_SIZE\'\n    input [`INSTR_SIZE-1:0] i_ir,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:14: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] i_pc,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:18: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] i_rs1idx,  \n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:19: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] i_rs2idx,  \n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:24: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] pipe_flush_add_op1,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:25: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] pipe_flush_add_op2,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:30: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] lsu_wbck_i_data,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:31: Define or directive not defined: \'`ITAG_WIDTH\'\n    input [`ITAG_WIDTH-1:0] lsu_wbck_i_itag,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:34: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] rf2ifu_x1,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:35: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] rf2ifu_rs1,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:39: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:49: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:51: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] agu_cmd_itag,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:54: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] agu_cmd_wdata,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:55: Define or directive not defined: \'`XLEN\'\n    output [`XLEN/8-1:0] agu_cmd_wmask,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:55: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    output [`XLEN/8-1:0] agu_cmd_wmask,\n                 ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:59: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] agu_rsp_rdata,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:66: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf_read_src1_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:67: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf_read_src2_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:68: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:70: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf_wbck_o_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:71: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf_x1_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:72: syntax error, unexpected assign\nassign rf2ifu_rs1 = rf_read_src1_data;\n^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:87: Define or directive not defined: \'`DECINFO_WIDTH\'\nwire [`DECINFO_WIDTH-1:0] dec_info;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:88: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] dec_imm;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:90: Define or directive not defined: \'`PC_SIZE\'\nwire [`PC_SIZE-1:0] dec_pc;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:92: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] dec_rs1idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:93: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] dec_rs2idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:94: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] dec_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:97: syntax error, unexpected assign\nassign dec2ifu_rden = dec_rdwen;\n^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:128: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:129: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:130: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] disp_oitf_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:133: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] disp_o_alu_rs1;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:134: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] disp_o_alu_rs2;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:136: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:137: Define or directive not defined: \'`DECINFO_WIDTH\'\nwire [`DECINFO_WIDTH-1:0] disp_o_alu_info;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:138: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] disp_o_alu_imm;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:139: Define or directive not defined: \'`PC_SIZE\'\nwire [`PC_SIZE-1:0] disp_o_alu_pc;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:140: Define or directive not defined: \'`ITAG_WIDTH\'\nwire [`ITAG_WIDTH-1:0] disp_o_alu_itag;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:147: Define or directive not defined: \'`ITAG_WIDTH\'\nwire [`ITAG_WIDTH-1:0] disp_oitf_ptr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:151: syntax error, unexpected IDENTIFIER\nexu_disp u_exu_disp (\n^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:197: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] alu_cmt_i_imm;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:203: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] alu_wbck_i_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:204: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:207: Define or directive not defined: \'`PC_SIZE\'\nwire [`PC_SIZE-1:0] alu_cmt_i_pc;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:209: syntax error, unexpected IDENTIFIER\nexu_alu u_exu_alu (\n^~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:278: Define or directive not defined: \'`ITAG_WIDTH\'\nwire [`ITAG_WIDTH-1:0] oitf_ret_ptr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu.v:280: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] oitf_ret_rdidx;\n      ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module exu (


    input i_valid,
    output i_ready,
    input [`INSTR_SIZE-1:0] i_ir,
    input [`PC_SIZE-1:0] i_pc,

    input i_prdt_taken, 

    input [`RFIDX_WIDTH-1:0] i_rs1idx,
    input [`RFIDX_WIDTH-1:0] i_rs2idx,


    input pipe_flush_ack,
    output pipe_flush_req,
    output [`PC_SIZE-1:0] pipe_flush_add_op1,
    output [`PC_SIZE-1:0] pipe_flush_add_op2,


    input lsu_wbck_i_valid,
    output lsu_wbck_i_ready,
    input [`XLEN-1:0] lsu_wbck_i_data,
    input [`ITAG_WIDTH-1:0] lsu_wbck_i_itag,
    
    output oitf_empty,
    output [`XLEN-1:0] rf2ifu_x1,
    output [`XLEN-1:0] rf2ifu_rs1,

    output dec2ifu_rden,
    output dec2ifu_rs1en,
    output [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,







    output agu_cmd_valid,
    input agu_cmd_ready,
    output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    output agu_cmd_read,
    output [`ITAG_WIDTH-1:0] agu_cmd_itag,
    output [1:0] agu_cmd_size,
    output agu_cmd_usign,
    output [`XLEN-1:0] agu_cmd_wdata,
    output [`XLEN/8-1:0] agu_cmd_wmask,
    
    input agu_rsp_valid,
    output agu_rsp_ready,
    input [`XLEN-1:0] agu_rsp_rdata,

    input clk,
    input rst_n
);


wire [`XLEN-1:0] rf_read_src1_data;
wire [`XLEN-1:0] rf_read_src2_data;
wire [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx;
wire rf_wbck_o_ena;
wire [`XLEN-1:0] rf_wbck_o_data;
wire [`XLEN-1:0] rf_x1_data;
assign rf2ifu_rs1 = rf_read_src1_data;
exu_regfile u_exu_regfile (
    .read_src1_idx(i_rs1idx),
    .read_src2_idx(i_rs2idx),
    .read_src1_data(rf_read_src1_data),
    .read_src2_data(rf_read_src2_data),
    .wbck_dest_idx(rf_wbck_o_rdidx),
    .wbck_dest_data(rf_wbck_o_data),
    .wbck_dest_ena(rf_wbck_o_ena),
    .x1_data(rf2ifu_x1),
    .clk(clk),
    .rst_n(rst_n)
);  


wire [`DECINFO_WIDTH-1:0] dec_info;
wire [`XLEN-1:0] dec_imm;
wire dec_rdwen;
wire [`PC_SIZE-1:0] dec_pc;
wire dec_illegal;
wire [`RFIDX_WIDTH-1:0] dec_rs1idx;
wire [`RFIDX_WIDTH-1:0] dec_rs2idx;
wire [`RFIDX_WIDTH-1:0] dec_rdidx;
wire dec_rs1en;
wire dec_rs2en;
assign dec2ifu_rden = dec_rdwen;
assign dec2ifu_rs1en = dec_rs1en;
assign dec2ifu_rdidx = dec_rdidx;

exu_decode u_exu_decode (
    .i_instr(i_ir),
    .i_pc(i_pc),
    .i_prdt_taken(i_prdt_taken),
    .dec_rs1en(dec_rs1en),
    .dec_rs2en(dec_rs2en),
    .dec_rdwen(dec_rdwen),
    .dec_rs1idx(),
    .dec_rs2idx(),
    .dec_rdidx(dec_rdidx),
    .dec_info(dec_info),
    .dec_imm(dec_imm),
    .dec_pc(dec_pc),
    .dec_illegal(dec_illegal),
    .dec_bjp(),
    .dec_jal(),
    .dec_jalr(),
    .dec_bxx(),
    .dec_jalr_rs1idx(),
    .dec_bjp_imm()
);


wire disp_oitf_ena;
wire disp_oitf_rs1en;
wire disp_oitf_rs2en;
wire disp_oitf_rdwen;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rdidx;

wire disp_o_alu_valid;
wire [`XLEN-1:0] disp_o_alu_rs1;
wire [`XLEN-1:0] disp_o_alu_rs2;
wire disp_o_alu_rdwen;
wire [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx;
wire [`DECINFO_WIDTH-1:0] disp_o_alu_info;
wire [`XLEN-1:0] disp_o_alu_imm;
wire [`PC_SIZE-1:0] disp_o_alu_pc;
wire [`ITAG_WIDTH-1:0] disp_o_alu_itag;
wire disp_o_alu_ilegl;

wire oitfrd_match_disprs1;
wire oitfrd_match_disprs2;
wire oitfrd_match_disprd;
wire disp_oitf_ready;
wire [`ITAG_WIDTH-1:0] disp_oitf_ptr;
wire disp_o_alu_ready;
wire disp_o_alu_longpipe;

exu_disp u_exu_disp (
    .oitf_empty(oitf_empty),
    .disp_i_valid(i_valid),
    .disp_i_ready(i_ready),
    .disp_i_rs1idx(i_rs1idx),
    .disp_i_rs2idx(i_rs2idx),
    .disp_i_rs1en(dec_rs1en),
    .disp_i_rs2en(dec_rs2en),
    .disp_i_rdwen(dec_rdwen),
    .disp_i_rdidx(dec_rdidx),
    .disp_i_rs1(rf_read_src1_data),
    .disp_i_rs2(rf_read_src2_data),
    .disp_i_info(dec_info),
    .disp_i_imm(dec_imm),
    .disp_i_pc(dec_pc),
    .disp_ilegl(dec_illegal),

    .disp_o_alu_valid(disp_o_alu_valid),
    .disp_o_alu_ready(disp_o_alu_ready),
    .disp_o_alu_longpipe(disp_o_alu_longpipe),
    .disp_o_alu_rs1(disp_o_alu_rs1),
    .disp_o_alu_rs2(disp_o_alu_rs2),
    .disp_o_alu_rdwen(disp_o_alu_rdwen),
    .disp_o_alu_rdidx(disp_o_alu_rdidx),
    .disp_o_alu_info(disp_o_alu_info),
    .disp_o_alu_imm(disp_o_alu_imm),
    .disp_o_alu_pc(disp_o_alu_pc),
    .disp_o_alu_itag(disp_o_alu_itag),
    .disp_o_alu_ilegl(disp_o_alu_ilegl),

    .oitfrd_match_disprs1(oitfrd_match_disprs1),
    .oitfrd_match_disprs2(oitfrd_match_disprs2),
    .oitfrd_match_disprd(oitfrd_match_disprd),
    .disp_oitf_ptr(disp_oitf_ptr),
    .disp_oitf_ena(disp_oitf_ena),
    .disp_oitf_ready(disp_oitf_ready),
    .disp_oitf_rs1en(disp_oitf_rs1en),
    .disp_oitf_rs2en(disp_oitf_rs2en),
    .disp_oitf_rdwen(disp_oitf_rdwen),
    .disp_oitf_rs1idx(disp_oitf_rs1idx),
    .disp_oitf_rs2idx(disp_oitf_rs2idx),
    .disp_oitf_rdidx(disp_oitf_rdidx)
);


wire alu_cmt_i_valid;
wire [`XLEN-1:0] alu_cmt_i_imm;
wire alu_cmt_i_bjp;
wire alu_cmt_i_ilegl;
wire alu_cmt_i_bjp_prdt;
wire alu_cmt_i_bjp_rslv;
wire alu_wbck_i_valid;
wire [`XLEN-1:0] alu_wbck_i_data;
wire [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx;
wire alu_cmt_i_ready;
wire alu_wbck_i_ready;
wire [`PC_SIZE-1:0] alu_cmt_i_pc;

exu_alu u_exu_alu (
    .i_valid(disp_o_alu_valid),
    .i_ready(disp_o_alu_ready),
    .i_longpipe(disp_o_alu_longpipe),
    .i_itag(disp_o_alu_itag),
    .i_rs1(disp_o_alu_rs1),
    .i_rs2(disp_o_alu_rs2),
    .i_imm(disp_o_alu_imm),
    .i_info(disp_o_alu_info),
    .i_pc(disp_o_alu_pc),

    .i_pc_vld(),
    .i_rdidx(disp_o_alu_rdidx),
    .i_rdwen(disp_o_alu_rdwen),
    .i_ilegl(disp_o_alu_ilegl),


    .cmt_o_valid(alu_cmt_i_valid),
    .cmt_o_ready(alu_cmt_i_ready),
    .cmt_o_pc(alu_cmt_i_pc),
    .cmt_o_imm(alu_cmt_i_imm),
    .cmt_o_bjp(alu_cmt_i_bjp),
    .cmt_o_ifu_ilegl(alu_cmt_i_ilegl),
    .cmt_o_bjp_prdt(alu_cmt_i_bjp_prdt),
    .cmt_o_bjp_rslv(alu_cmt_i_bjp_rslv),
    
    .wbck_o_valid(alu_wbck_i_valid),
    .wbck_o_ready(alu_wbck_i_ready),
    .wbck_o_wdat(alu_wbck_i_data),
    .wbck_o_rdidx(alu_wbck_i_rdidx),

    .mdv_nob2b(),
    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_size(agu_cmd_size),
    .agu_cmd_usign(agu_cmd_usign),

    .agu_cmd_itag(agu_cmd_itag),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .agu_rsp_rdata(agu_rsp_rdata),

    .clk(clk),
    .rst_n(rst_n)
);



exu_commit u_exu_commit (
    .nonflush_cmt_ena(),
    .alu_cmt_i_valid(alu_cmt_i_valid),
    .alu_cmt_i_ready(alu_cmt_i_ready),
    .alu_cmt_i_imm(alu_cmt_i_imm),
    .alu_cmt_i_bjp(alu_cmt_i_bjp),
    .alu_cmt_i_bjp_prdt(alu_cmt_i_bjp_prdt),
    .alu_cmt_i_bjp_rslv(alu_cmt_i_bjp_rslv),
    .alu_cmt_i_pc(alu_cmt_i_pc),
    .alu_cmt_i_ilegl(alu_cmt_i_ilegl),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2)
);


wire [`ITAG_WIDTH-1:0] oitf_ret_ptr;
wire oitf_ret_ena;
wire [`RFIDX_WIDTH-1:0] oitf_ret_rdidx;
wire oitf_ret_rdwen;
exu_oitf u_exu_oitf (
    .disp_ready(disp_oitf_ready),
    .disp_ena(disp_oitf_ena),
    .dis_ptr(disp_oitf_ptr),
    .ret_ena(oitf_ret_ena),
    .ret_ptr(oitf_ret_ptr),
    .ret_rdidx(oitf_ret_rdidx),
    .ret_rdwen(oitf_ret_rdwen),
    .disp_i_rs1en(disp_oitf_rs1en),
    .disp_i_rs2en(disp_oitf_rs2en),
    .disp_i_rdwen(disp_oitf_rdwen),
    .disp_i_rs1idx(disp_oitf_rs1idx),
    .disp_i_rs2idx(disp_oitf_rs2idx),
    .disp_i_rdidx(disp_oitf_rdidx),
    .oitfrd_match_disprs1(oitfrd_match_disprs1),
    .oitfrd_match_disprs2(oitfrd_match_disprs2),
    .oitfrd_match_disprd(oitfrd_match_disprd),
    .oitf_empty(oitf_empty),
    .clk(clk),
    .rst_n(rst_n)
);


wire longp_wbck_o_valid;
wire [`XLEN-1:0] longp_wbck_o_data;
wire [`RFIDX_WIDTH-1:0] longp_wbck_o_rdidx;
wire longp_wbck_o_ready;

exu_longpwbck u_exu_longpwbck (
    .lsu_wbck_i_valid(lsu_wbck_i_valid),
    .lsu_wbck_i_ready(lsu_wbck_i_ready),
    .lsu_wbck_i_data(lsu_wbck_i_data),
    .lsu_wbck_i_itag(lsu_wbck_i_itag),
    .longp_wbck_o_valid(longp_wbck_o_valid),
    .longp_wbck_o_ready(longp_wbck_o_ready),
    .longp_wbck_o_data(longp_wbck_o_data),
    .longp_wbck_o_rdidx(longp_wbck_o_rdidx),
    .oitf_empty(oitf_empty),
    .oitf_ret_ptr(oitf_ret_ptr),
    .oitf_ret_rdwen(oitf_ret_rdwen),
    .oitf_ret_ena(oitf_ret_ena),
    .oitf_ret_rdidx(oitf_ret_rdidx)
);



exu_wbck u_exu_wbck (
    .alu_wbck_i_valid(alu_wbck_i_valid),
    .alu_wbck_i_ready(alu_wbck_i_ready),
    .alu_wbck_i_data(alu_wbck_i_data),
    .alu_wbck_i_rdidx(alu_wbck_i_rdidx),

    .longp_wbck_i_valid(longp_wbck_o_valid),
    .longp_wbck_i_ready(longp_wbck_o_ready),
    .longp_wbck_i_data(longp_wbck_o_data),
    .longp_wbck_i_rdidx(longp_wbck_o_rdidx),

    .rf_wbck_o_ena(rf_wbck_o_ena),
    .rf_wbck_o_data(rf_wbck_o_data),
    .rf_wbck_o_rdidx(rf_wbck_o_rdidx)
);
    
endmodule
module exu (


    input i_valid,
    output i_ready,
    input [`INSTR_SIZE-1:0] i_ir,
    input [`PC_SIZE-1:0] i_pc,

    input i_prdt_taken, 

    input [`RFIDX_WIDTH-1:0] i_rs1idx,
    input [`RFIDX_WIDTH-1:0] i_rs2idx,


    input pipe_flush_ack,
    output pipe_flush_req,
    output [`PC_SIZE-1:0] pipe_flush_add_op1,
    output [`PC_SIZE-1:0] pipe_flush_add_op2,


    input lsu_wbck_i_valid,
    output lsu_wbck_i_ready,
    input [`XLEN-1:0] lsu_wbck_i_data,
    input [`ITAG_WIDTH-1:0] lsu_wbck_i_itag,
    
    output oitf_empty,
    output [`XLEN-1:0] rf2ifu_x1,
    output [`XLEN-1:0] rf2ifu_rs1,

    output dec2ifu_rden,
    output dec2ifu_rs1en,
    output [`RFIDX_WIDTH-1:0] dec2ifu_rdidx,







    output agu_cmd_valid,
    input agu_cmd_ready,
    output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    output agu_cmd_read,
    output [`ITAG_WIDTH-1:0] agu_cmd_itag,
    output [1:0] agu_cmd_size,
    output agu_cmd_usign,
    output [`XLEN-1:0] agu_cmd_wdata,
    output [`XLEN/8-1:0] agu_cmd_wmask,
    
    input agu_rsp_valid,
    output agu_rsp_ready,
    input [`XLEN-1:0] agu_rsp_rdata,

    input clk,
    input rst_n
);



wire [`XLEN-1:0] rf_read_src1_data;
wire [`XLEN-1:0] rf_read_src2_data;
wire [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx;
wire rf_wbck_o_ena;
wire [`XLEN-1:0] rf_wbck_o_data;
wire [`XLEN-1:0] rf_x1_data;
assign rf2ifu_rs1 = rf_read_src1_data;
exu_regfile u_exu_regfile (
    .read_src1_idx(i_rs1idx),
    .read_src2_idx(i_rs2idx),
    .read_src1_data(rf_read_src1_data),
    .read_src2_data(rf_read_src2_data),
    .wbck_dest_idx(rf_wbck_o_rdidx),
    .wbck_dest_data(rf_wbck_o_data),
    .wbck_dest_ena(rf_wbck_o_ena),
    .x1_data(rf2ifu_x1),
    .clk(clk),
    .rst_n(rst_n)
);  


wire [`DECINFO_WIDTH-1:0] dec_info;
wire [`XLEN-1:0] dec_imm;
wire dec_rdwen;
wire [`PC_SIZE-1:0] dec_pc;
wire dec_illegal;
wire [`RFIDX_WIDTH-1:0] dec_rs1idx;
wire [`RFIDX_WIDTH-1:0] dec_rs2idx;
wire [`RFIDX_WIDTH-1:0] dec_rdidx;
wire dec_rs1en;
wire dec_rs2en;
assign dec2ifu_rden = dec_rdwen;
assign dec2ifu_rs1en = dec_rs1en;
assign dec2ifu_rdidx = dec_rdidx;

exu_decode u_exu_decode (
    .i_instr(i_ir),
    .i_pc(i_pc),
    .i_prdt_taken(i_prdt_taken),
    .dec_rs1en(dec_rs1en),
    .dec_rs2en(dec_rs2en),
    .dec_rdwen(dec_rdwen),
    .dec_rs1idx(),
    .dec_rs2idx(),
    .dec_rdidx(dec_rdidx),
    .dec_info(dec_info),
    .dec_imm(dec_imm),
    .dec_pc(dec_pc),
    .dec_illegal(dec_illegal),
    .dec_bjp(),
    .dec_jal(),
    .dec_jalr(),
    .dec_bxx(),
    .dec_jalr_rs1idx(),
    .dec_bjp_imm()
);


wire disp_oitf_ena;
wire disp_oitf_rs1en;
wire disp_oitf_rs2en;
wire disp_oitf_rdwen;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rs1idx;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rs2idx;
wire [`RFIDX_WIDTH-1:0] disp_oitf_rdidx;

wire disp_o_alu_valid;
wire [`XLEN-1:0] disp_o_alu_rs1;
wire [`XLEN-1:0] disp_o_alu_rs2;
wire disp_o_alu_rdwen;
wire [`RFIDX_WIDTH-1:0] disp_o_alu_rdidx;
wire [`DECINFO_WIDTH-1:0] disp_o_alu_info;
wire [`XLEN-1:0] disp_o_alu_imm;
wire [`PC_SIZE-1:0] disp_o_alu_pc;
wire [`ITAG_WIDTH-1:0] disp_o_alu_itag;
wire disp_o_alu_ilegl;

wire oitfrd_match_disprs1;
wire oitfrd_match_disprs2;
wire oitfrd_match_disprd;
wire disp_oitf_ready;
wire [`ITAG_WIDTH-1:0] disp_oitf_ptr;
wire disp_o_alu_ready;
wire disp_o_alu_longpipe;

exu_disp u_exu_disp (
    .oitf_empty(oitf_empty),
    .disp_i_valid(i_valid),
    .disp_i_ready(i_ready),
    .disp_i_rs1idx(i_rs1idx),
    .disp_i_rs2idx(i_rs2idx),
    .disp_i_rs1en(dec_rs1en),
    .disp_i_rs2en(dec_rs2en),
    .disp_i_rdwen(dec_rdwen),
    .disp_i_rdidx(dec_rdidx),
    .disp_i_rs1(rf_read_src1_data),
    .disp_i_rs2(rf_read_src2_data),
    .disp_i_info(dec_info),
    .disp_i_imm(dec_imm),
    .disp_i_pc(dec_pc),
    .disp_ilegl(dec_illegal),

    .disp_o_alu_valid(disp_o_alu_valid),
    .disp_o_alu_ready(disp_o_alu_ready),
    .disp_o_alu_longpipe(disp_o_alu_longpipe),
    .disp_o_alu_rs1(disp_o_alu_rs1),
    .disp_o_alu_rs2(disp_o_alu_rs2),
    .disp_o_alu_rdwen(disp_o_alu_rdwen),
    .disp_o_alu_rdidx(disp_o_alu_rdidx),
    .disp_o_alu_info(disp_o_alu_info),
    .disp_o_alu_imm(disp_o_alu_imm),
    .disp_o_alu_pc(disp_o_alu_pc),
    .disp_o_alu_itag(disp_o_alu_itag),
    .disp_o_alu_ilegl(disp_o_alu_ilegl),

    .oitfrd_match_disprs1(oitfrd_match_disprs1),
    .oitfrd_match_disprs2(oitfrd_match_disprs2),
    .oitfrd_match_disprd(oitfrd_match_disprd),
    .disp_oitf_ptr(disp_oitf_ptr),
    .disp_oitf_ena(disp_oitf_ena),
    .disp_oitf_ready(disp_oitf_ready),
    .disp_oitf_rs1en(disp_oitf_rs1en),
    .disp_oitf_rs2en(disp_oitf_rs2en),
    .disp_oitf_rdwen(disp_oitf_rdwen),
    .disp_oitf_rs1idx(disp_oitf_rs1idx),
    .disp_oitf_rs2idx(disp_oitf_rs2idx),
    .disp_oitf_rdidx(disp_oitf_rdidx)
);


wire alu_cmt_i_valid;
wire [`XLEN-1:0] alu_cmt_i_imm;
wire alu_cmt_i_bjp;
wire alu_cmt_i_ilegl;
wire alu_cmt_i_bjp_prdt;
wire alu_cmt_i_bjp_rslv;
wire alu_wbck_i_valid;
wire [`XLEN-1:0] alu_wbck_i_data;
wire [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx;
wire alu_cmt_i_ready;
wire alu_wbck_i_ready;
wire [`PC_SIZE-1:0] alu_cmt_i_pc;

exu_alu u_exu_alu (
    .i_valid(disp_o_alu_valid),
    .i_ready(disp_o_alu_ready),
    .i_longpipe(disp_o_alu_longpipe),
    .i_itag(disp_o_alu_itag),
    .i_rs1(disp_o_alu_rs1),
    .i_rs2(disp_o_alu_rs2),
    .i_imm(disp_o_alu_imm),
    .i_info(disp_o_alu_info),
    .i_pc(disp_o_alu_pc),

    .i_pc_vld(),
    .i_rdidx(disp_o_alu_rdidx),
    .i_rdwen(disp_o_alu_rdwen),
    .i_ilegl(disp_o_alu_ilegl),


    .cmt_o_valid(alu_cmt_i_valid),
    .cmt_o_ready(alu_cmt_i_ready),
    .cmt_o_pc(alu_cmt_i_pc),
    .cmt_o_imm(alu_cmt_i_imm),
    .cmt_o_bjp(alu_cmt_i_bjp),
    .cmt_o_ifu_ilegl(alu_cmt_i_ilegl),
    .cmt_o_bjp_prdt(alu_cmt_i_bjp_prdt),
    .cmt_o_bjp_rslv(alu_cmt_i_bjp_rslv),
    
    .wbck_o_valid(alu_wbck_i_valid),
    .wbck_o_ready(alu_wbck_i_ready),
    .wbck_o_wdat(alu_wbck_i_data),
    .wbck_o_rdidx(alu_wbck_i_rdidx),

    .mdv_nob2b(),
    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_size(agu_cmd_size),
    .agu_cmd_usign(agu_cmd_usign),

    .agu_cmd_itag(agu_cmd_itag),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .agu_rsp_rdata(agu_rsp_rdata),

    .clk(clk),
    .rst_n(rst_n)
);



exu_commit u_exu_commit (
    .nonflush_cmt_ena(),
    .alu_cmt_i_valid(alu_cmt_i_valid),
    .alu_cmt_i_ready(alu_cmt_i_ready),
    .alu_cmt_i_imm(alu_cmt_i_imm),
    .alu_cmt_i_bjp(alu_cmt_i_bjp),
    .alu_cmt_i_bjp_prdt(alu_cmt_i_bjp_prdt),
    .alu_cmt_i_bjp_rslv(alu_cmt_i_bjp_rslv),
    .alu_cmt_i_pc(alu_cmt_i_pc),
    .alu_cmt_i_ilegl(alu_cmt_i_ilegl),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2)
);


wire [`ITAG_WIDTH-1:0] oitf_ret_ptr;
wire oitf_ret_ena;
wire [`RFIDX_WIDTH-1:0] oitf_ret_rdidx;
wire oitf_ret_rdwen;
exu_oitf u_exu_oitf (
    .disp_ready(disp_oitf_ready),
    .disp_ena(disp_oitf_ena),
    .dis_ptr(disp_oitf_ptr),
    .ret_ena(oitf_ret_ena),
    .ret_ptr(oitf_ret_ptr),
    .ret_rdidx(oitf_ret_rdidx),
    .ret_rdwen(oitf_ret_rdwen),
    .disp_i_rs1en(disp_oitf_rs1en),
    .disp_i_rs2en(disp_oitf_rs2en),
    .disp_i_rdwen(disp_oitf_rdwen),
    .disp_i_rs1idx(disp_oitf_rs1idx),
    .disp_i_rs2idx(disp_oitf_rs2idx),
    .disp_i_rdidx(disp_oitf_rdidx),
    .oitfrd_match_disprs1(oitfrd_match_disprs1),
    .oitfrd_match_disprs2(oitfrd_match_disprs2),
    .oitfrd_match_disprd(oitfrd_match_disprd),
    .oitf_empty(oitf_empty),
    .clk(clk),
    .rst_n(rst_n)
);


wire longp_wbck_o_valid;
wire [`XLEN-1:0] longp_wbck_o_data;
wire [`RFIDX_WIDTH-1:0] longp_wbck_o_rdidx;
wire longp_wbck_o_ready;

exu_longpwbck u_exu_longpwbck (
    .lsu_wbck_i_valid(lsu_wbck_i_valid),
    .lsu_wbck_i_ready(lsu_wbck_i_ready),
    .lsu_wbck_i_data(lsu_wbck_i_data),
    .lsu_wbck_i_itag(lsu_wbck_i_itag),
    .longp_wbck_o_valid(longp_wbck_o_valid),
    .longp_wbck_o_ready(longp_wbck_o_ready),
    .longp_wbck_o_data(longp_wbck_o_data),
    .longp_wbck_o_rdidx(longp_wbck_o_rdidx),
    .oitf_empty(oitf_empty),
    .oitf_ret_ptr(oitf_ret_ptr),
    .oitf_ret_rdwen(oitf_ret_rdwen),
    .oitf_ret_ena(oitf_ret_ena),
    .oitf_ret_rdidx(oitf_ret_rdidx)
);



exu_wbck u_exu_wbck (
    .alu_wbck_i_valid(alu_wbck_i_valid),
    .alu_wbck_i_ready(alu_wbck_i_ready),
    .alu_wbck_i_data(alu_wbck_i_data),
    .alu_wbck_i_rdidx(alu_wbck_i_rdidx),

    .longp_wbck_i_valid(longp_wbck_o_valid),
    .longp_wbck_i_ready(longp_wbck_o_ready),
    .longp_wbck_i_data(longp_wbck_o_data),
    .longp_wbck_i_rdidx(longp_wbck_o_rdidx),

    .rf_wbck_o_ena(rf_wbck_o_ena),
    .rf_wbck_o_data(rf_wbck_o_data),
    .rf_wbck_o_rdidx(rf_wbck_o_rdidx)
);
    
endmodule