data/full_repos/permissive/496266817/tb/tb_scrypt_new.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #(HALF_PERIOD_CLOCK) clk <= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2*num_delay)  reset_n <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2)    init <= 1\'b1;\n   ^\n%Error: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:10: Cannot find file containing module: \'scrypt_new\'\n scrypt_new scrypt_new_ip(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new.v\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new.sv\n             scrypt_new\n             scrypt_new.v\n             scrypt_new.sv\n             obj_dir/scrypt_new\n             obj_dir/scrypt_new.v\n             obj_dir/scrypt_new.sv\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:46: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'start_time\' generates 32 bits.\n                                                                          : ... In instance tb_scrypt_new\n   $display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:67: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                          : ... In instance tb_scrypt_new\n   start_time = $time;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new.v:75: Operator TASKREF \'reset_task\' expects 8 bits on the Function Argument, but Function Argument\'s CONST \'3\'h5\' generates 3 bits.\n                                                                          : ... In instance tb_scrypt_new\n  reset_task(3\'d5);\n  ^~~~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_scrypt_new();
    reg                clk           ;
    reg                reset_n       ;
    reg                init          ;
    reg    [639:0]     in            ;
    wire   [255:0]     out_scrypt    ;
    wire               valid         ;

	scrypt_new	scrypt_new_ip(
				.clk       	(clk        ) ,
				.reset_n   	(reset_n    ) ,
				.init      	(init       ) ,
				.in        	(in         ) ,
				.out_scrypt	(out_scrypt ) ,
				.valid	    (valid      )
	);
	










	parameter HALF_PERIOD_CLOCK = 10;
	integer i;
	integer start_time;
	integer display_pbdkf2 = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid) 
	begin






		if(valid== 1'b1) begin
			$display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  		= 1'b0;
			init 		= 1'b0;
			reset_n 	= 1'b0;

			in			= 640'h0000002056efd1943684c1fdc247d4759cc43b29afa1cac7ad14579de5f6abcbc6bdf448ee3de4c7b45e9496ab41ecde73d1a299ddbcc7a81aa52776e6c067e214233af097b6885c97df011aa004090e;

		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;

			start_time = $time;

		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule
module tb_scrypt_new();

    reg                clk           ;
    reg                reset_n       ;
    reg                init          ;
    reg    [639:0]     in            ;
    wire   [255:0]     out_scrypt    ;
    wire               valid         ;

	scrypt_new	scrypt_new_ip(
				.clk       	(clk        ) ,
				.reset_n   	(reset_n    ) ,
				.init      	(init       ) ,
				.in        	(in         ) ,
				.out_scrypt	(out_scrypt ) ,
				.valid	    (valid      )
	);
	










	parameter HALF_PERIOD_CLOCK = 10;
	integer i;
	integer start_time;
	integer display_pbdkf2 = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid) 
	begin






		if(valid== 1'b1) begin
			$display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  		= 1'b0;
			init 		= 1'b0;
			reset_n 	= 1'b0;

			in			= 640'h0000002056efd1943684c1fdc247d4759cc43b29afa1cac7ad14579de5f6abcbc6bdf448ee3de4c7b45e9496ab41ecde73d1a299ddbcc7a81aa52776e6c067e214233af097b6885c97df011aa004090e;

		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;

			start_time = $time;

		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule