data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v
1: b"%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:19: Cannot find file containing module: 'pcLogic'\npcLogic pcl (.clk(clk), .reset(reset), .PCIn(PCNext), .PCOut(PC));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor,data/full_repos/permissive/451853158/pcLogic\n             data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor,data/full_repos/permissive/451853158/pcLogic.v\n             data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor,data/full_repos/permissive/451853158/pcLogic.sv\n             pcLogic\n             pcLogic.v\n             pcLogic.sv\n             obj_dir/pcLogic\n             obj_dir/pcLogic.v\n             obj_dir/pcLogic.sv\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:20: Cannot find file containing module: 'adder'\nadder pcPlus4 (.a(PC), .b(32'h4), .y(PCPlus4));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:23: Cannot find file containing module: 'instrMem'\ninstrMem imem1 (.a(PC[7:2]), .instr(Instr));\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:28: Cannot find file containing module: 'mux21'\nmux21 jmux (.a(PCNextBr), .b({PCPlus4[31:28],Instr[25:0],2'b00}), .sel(Jump), .y(PCNext));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:29: Cannot find file containing module: 'mux21'\nmux21 pcmux (.a(PCPlus4), .b(PCBranch), .sel(PCSrc), .y(PCNextBr));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:32: Cannot find file containing module: 'signExt'\nsignExt signext1 (.a(Instr[15:0]), .y(SignImm));\n^~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:35: Cannot find file containing module: 'reg_file'\nreg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:40: Cannot find file containing module: 'shftl2'\nshftl2 sl1 (.a(SignImm), .y(SignImmShft));\n^~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:41: Cannot find file containing module: 'adder'\nadder pcBranchadder (.a(SignImmShft), .b(PCPlus4), .y(PCBranch));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:44: Cannot find file containing module: 'mux21'\nmux21 #(5) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:47: Cannot find file containing module: 'mux21'\nmux21 aluSrcBmux (.a(wrDataOut), .b(SignImm), .sel(ALUSrc), .y(SrcB));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:50: Cannot find file containing module: 'alu'\nalu alu1 (.srcA(SrcA), .srcB(SrcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));\n^~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:53: Cannot find file containing module: 'dataMem'\ndataMem dmem1 (.clk(clk), .wrEn(MemWrite), .addr(ALUResult), .wrData(wrDataOut), .rdData(readData));\n^~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/datapath.v:56: Cannot find file containing module: 'mux21'\nmux21 resmux (.a(ALUResult), .b(readData), .sel(MemtoReg), .y(Result));\n^~~~~\n%Error: Exiting due to 14 error(s)\n"
module datapath (
  input clk, reset,
  input Jump, PCSrc, MemtoReg, MemWrite, ALUSrc, RegDst, RegWr,
  input [2:0] ALUCtrl,
  output wire [5:0] OPCode, Funct,
  output      Z
);




wire [31:0] PC, PCNext, PCNextBr, PCPlus4, PCBranch;
wire [31:0] Instr;
wire [4:0] wrReg;
wire [31:0] Result, SrcA, wrDataOut, SignImm, SrcB, ALUResult, readData;
wire [31:0] SignImmShft;


pcLogic pcl (.clk(clk), .reset(reset), .PCIn(PCNext), .PCOut(PC));
adder pcPlus4 (.a(PC), .b(32'h4), .y(PCPlus4));


instrMem imem1 (.a(PC[7:2]), .instr(Instr));
assign OPCode = Instr[31:26];
assign Funct = Instr[5:0];


mux21 jmux (.a(PCNextBr), .b({PCPlus4[31:28],Instr[25:0],2'b00}), .sel(Jump), .y(PCNext));
mux21 pcmux (.a(PCPlus4), .b(PCBranch), .sel(PCSrc), .y(PCNextBr));


signExt signext1 (.a(Instr[15:0]), .y(SignImm));


reg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),
             .wrAddr(wrReg), .regWrite(RegWr), .wrData(Result),
             .rdData1(SrcA), .rdData2(wrDataOut));


shftl2 sl1 (.a(SignImm), .y(SignImmShft));
adder pcBranchadder (.a(SignImmShft), .b(PCPlus4), .y(PCBranch));
             

mux21 #(5) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));


mux21 aluSrcBmux (.a(wrDataOut), .b(SignImm), .sel(ALUSrc), .y(SrcB));


alu alu1 (.srcA(SrcA), .srcB(SrcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));


dataMem dmem1 (.clk(clk), .wrEn(MemWrite), .addr(ALUResult), .wrData(wrDataOut), .rdData(readData));


mux21 resmux (.a(ALUResult), .b(readData), .sel(MemtoReg), .y(Result));

endmodule
module datapath (
  input clk, reset,
  input Jump, PCSrc, MemtoReg, MemWrite, ALUSrc, RegDst, RegWr,
  input [2:0] ALUCtrl,
  output wire [5:0] OPCode, Funct,
  output      Z
);





wire [31:0] PC, PCNext, PCNextBr, PCPlus4, PCBranch;
wire [31:0] Instr;
wire [4:0] wrReg;
wire [31:0] Result, SrcA, wrDataOut, SignImm, SrcB, ALUResult, readData;
wire [31:0] SignImmShft;


pcLogic pcl (.clk(clk), .reset(reset), .PCIn(PCNext), .PCOut(PC));
adder pcPlus4 (.a(PC), .b(32'h4), .y(PCPlus4));


instrMem imem1 (.a(PC[7:2]), .instr(Instr));
assign OPCode = Instr[31:26];
assign Funct = Instr[5:0];


mux21 jmux (.a(PCNextBr), .b({PCPlus4[31:28],Instr[25:0],2'b00}), .sel(Jump), .y(PCNext));
mux21 pcmux (.a(PCPlus4), .b(PCBranch), .sel(PCSrc), .y(PCNextBr));


signExt signext1 (.a(Instr[15:0]), .y(SignImm));


reg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),
             .wrAddr(wrReg), .regWrite(RegWr), .wrData(Result),
             .rdData1(SrcA), .rdData2(wrDataOut));


shftl2 sl1 (.a(SignImm), .y(SignImmShft));
adder pcBranchadder (.a(SignImmShft), .b(PCPlus4), .y(PCBranch));
             

mux21 #(5) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));


mux21 aluSrcBmux (.a(wrDataOut), .b(SignImm), .sel(ALUSrc), .y(SrcB));


alu alu1 (.srcA(SrcA), .srcB(SrcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));


dataMem dmem1 (.clk(clk), .wrEn(MemWrite), .addr(ALUResult), .wrData(wrDataOut), .rdData(readData));


mux21 resmux (.a(ALUResult), .b(readData), .sel(MemtoReg), .y(Result));

endmodule