data/full_repos/permissive/445357518/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445357518/cpu.v:43: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                             : ... In instance cpu\n assign pc = {8\'b0, PC};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445357518/cpu.v:45: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.sv\n             vDFF1\n             vDFF1.v\n             vDFF1.sv\n             obj_dir/vDFF1\n             obj_dir/vDFF1.v\n             obj_dir/vDFF1.sv\n%Error: data/full_repos/permissive/445357518/cpu.v:54: Cannot find file containing module: \'datapath\'\n datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)\n ^~~~~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:64: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);\n ^~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:73: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);\n ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module instruction_decoder(instruction,nsel,ALUop,sixmm5,sixmm8,shift,readnum,writenum,opcode,op);
	input[15:0] instruction;
 	input[2:0] nsel;
 	output[1:0] ALUop,shift,op;
 	output[2:0] readnum,writenum,opcode;
 	output[15:0] sixmm5,sixmm8;
	wire [2:0] rd;
	wire [2:0] rn;
	wire [2:0] rm;
	reg [2:0] multOut;


	assign rd = instruction[7:5];

	assign rn = instruction[10:8];

	assign rm = instruction[2:0];
	
	assign ALUop = instruction[12:11];
 	assign shift = instruction[4:3];


 	assign sixmm5 = (instruction[4]==0) ? {{11{1'b0}},instruction[4:0]}:{{11{1'b1}},instruction[4:0]};

 	assign sixmm8 = (instruction[7]==0) ? {{8{1'b0}},instruction[7:0]}:{{8{1'b1}},instruction[7:0]};


	always @* begin
                
		case (nsel)
			3'b001: multOut = rn;
			3'b010: multOut = rd;
			3'b100: multOut = rm;

			default: multOut = 3'b000;
		endcase
	end


	assign readnum = multOut;

	assign writenum = multOut;


	assign opcode = instruction[15:13];

	assign op = instruction[12:11];

endmodule
module instruction_decoder(instruction,nsel,ALUop,sixmm5,sixmm8,shift,readnum,writenum,opcode,op);

	input[15:0] instruction;
 	input[2:0] nsel;
 	output[1:0] ALUop,shift,op;
 	output[2:0] readnum,writenum,opcode;
 	output[15:0] sixmm5,sixmm8;
	wire [2:0] rd;
	wire [2:0] rn;
	wire [2:0] rm;
	reg [2:0] multOut;


	assign rd = instruction[7:5];

	assign rn = instruction[10:8];

	assign rm = instruction[2:0];
	
	assign ALUop = instruction[12:11];
 	assign shift = instruction[4:3];


 	assign sixmm5 = (instruction[4]==0) ? {{11{1'b0}},instruction[4:0]}:{{11{1'b1}},instruction[4:0]};

 	assign sixmm8 = (instruction[7]==0) ? {{8{1'b0}},instruction[7:0]}:{{8{1'b1}},instruction[7:0]};


	always @* begin
                
		case (nsel)
			3'b001: multOut = rn;
			3'b010: multOut = rd;
			3'b100: multOut = rm;

			default: multOut = 3'b000;
		endcase
	end


	assign readnum = multOut;

	assign writenum = multOut;


	assign opcode = instruction[15:13];

	assign op = instruction[12:11];

endmodule