data/full_repos/permissive/458737381/src/verilog-parser/tests/sctag_cpx_rptr_1.v
data/verilator_xmls/c0e1d869-625d-423a-840a-b6e4d0e5f1d1.xml
module sctag_cpx_rptr_1 (

   sig_buf, 

   sig
   );



output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule
module sctag_cpx_rptr_1 (

   sig_buf, 

   sig
   );




output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule