data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_tx_glue.v
data/verilator_xmls/404e83c6-b1ae-4fa6-8759-ee05539cbda6.xml
module dsp_tx_glue
#(

    parameter DSPNO = 0,


    parameter WIDTH = 24
)
(

    input clock, input reset, input clear, input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output [WIDTH-1:0] frontend_i,
    output [WIDTH-1:0] frontend_q,


    input [WIDTH-1:0] duc_out_i,
    input [WIDTH-1:0] duc_out_q,


    output [31:0] duc_in_sample,
    input duc_in_strobe,
    output duc_in_enable,


    input [31:0] bb_sample,
    output bb_strobe,


    output [31:0] debug
);

    generate
        if (DSPNO==0) begin
            `ifndef TX_DSP0_MODULE
            assign frontend_i = duc_out_i;
            assign frontend_q = duc_out_q;
            assign duc_in_sample = bb_sample;
            assign bb_strobe = duc_in_strobe;
            assign duc_in_enable = enable;
            `else
            `TX_DSP0_MODULE #(.WIDTH(WIDTH)) tx_dsp0_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
        else begin
            `ifndef TX_DSP1_MODULE
            assign frontend_i = duc_out_i;
            assign frontend_q = duc_out_q;
            assign duc_in_sample = bb_sample;
            assign bb_strobe = duc_in_strobe;
            assign duc_in_enable = enable;
            `else
            `TX_DSP1_MODULE #(.WIDTH(WIDTH)) tx_dsp1_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
    endgenerate

endmodule
module dsp_tx_glue
#(

    parameter DSPNO = 0,


    parameter WIDTH = 24
)
(

    input clock, input reset, input clear, input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    output [WIDTH-1:0] frontend_i,
    output [WIDTH-1:0] frontend_q,


    input [WIDTH-1:0] duc_out_i,
    input [WIDTH-1:0] duc_out_q,


    output [31:0] duc_in_sample,
    input duc_in_strobe,
    output duc_in_enable,


    input [31:0] bb_sample,
    output bb_strobe,


    output [31:0] debug
);


    generate
        if (DSPNO==0) begin
            `ifndef TX_DSP0_MODULE
            assign frontend_i = duc_out_i;
            assign frontend_q = duc_out_q;
            assign duc_in_sample = bb_sample;
            assign bb_strobe = duc_in_strobe;
            assign duc_in_enable = enable;
            `else
            `TX_DSP0_MODULE #(.WIDTH(WIDTH)) tx_dsp0_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
        else begin
            `ifndef TX_DSP1_MODULE
            assign frontend_i = duc_out_i;
            assign frontend_q = duc_out_q;
            assign duc_in_sample = bb_sample;
            assign bb_strobe = duc_in_strobe;
            assign duc_in_enable = enable;
            `else
            `TX_DSP1_MODULE #(.WIDTH(WIDTH)) tx_dsp1_custom
            (
                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                .frontend_i(frontend_i), .frontend_q(frontend_q),
                .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
                .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), .duc_in_enable(duc_in_enable),
                .bb_sample(bb_sample), .bb_strobe(bb_strobe)
            );
            `endif
        end
    endgenerate

endmodule