data/full_repos/permissive/445216371/IFID.v
data/verilator_xmls/89459d7d-d945-4d50-82bf-5b11616ca891.xml
module IFID (
    output reg [31:0]pco,pc4o,insto,
    output reg bubbleo,
    input [31:0]pc,pc4,inst,
    input bubble,
    input clk,rst,stall
);
    always @(posedge clk, negedge rst) begin
        if(!rst)begin
            pco<=0;
            pc4o<=0;
            insto<=0;
            bubbleo<=0;
        end
        else begin
            if(stall)begin
                pco<=pco;
                pc4o<=pc4o;
                insto<=insto;
                bubbleo<=bubbleo;
            end else begin
                pco<=pc;
                pc4o<=pc4;
                insto<=inst;
                bubbleo<=bubble;
            end
        end
    end
endmodule
module IFID (
    output reg [31:0]pco,pc4o,insto,
    output reg bubbleo,
    input [31:0]pc,pc4,inst,
    input bubble,
    input clk,rst,stall
);

    always @(posedge clk, negedge rst) begin
        if(!rst)begin
            pco<=0;
            pc4o<=0;
            insto<=0;
            bubbleo<=0;
        end
        else begin
            if(stall)begin
                pco<=pco;
                pc4o<=pc4o;
                insto<=insto;
                bubbleo<=bubbleo;
            end else begin
                pco<=pc;
                pc4o<=pc4;
                insto<=inst;
                bubbleo<=bubble;
            end
        end
    end
endmodule