data/full_repos/permissive/425816165/rtl/kbdhandler.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/kbdhandler.v:193: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s SEL generates 5 bits.\n                                                                         : ... In instance kbdhandler.scan2ascii\n assign ascii = ctrl ? base[4:0] : base[6:0];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425816165/rtl/kbdhandler.v:15: Cannot find file containing module: \'edgedet\'\n edgedet data_edge(clk, reset, newdata, scanpulse);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet.v\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet.sv\n             edgedet\n             edgedet.v\n             edgedet.sv\n             obj_dir/edgedet\n             obj_dir/edgedet.v\n             obj_dir/edgedet.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module scan2ascii(
	input wire [7:0] scan,
	input wire shift,
	input wire ctrl,
	output wire [6:0] ascii,
	output reg invalid
);
	reg [7:0] base;
	always @(*) begin
		invalid <= 0;
		base <= 0;
		if(shift) begin
			case(scan)
			8'h0E: base <= 8'h7E;
			8'h4E: base <= 8'h5F;
			8'h55: base <= 8'h2B;
			8'h66: base <= 8'h7F;
			8'h0D: base <= 8'h09;
			8'h54: base <= 8'h7B;
			8'h5B: base <= 8'h7D;
			8'h5D: base <= 8'h7C;
			8'h4C: base <= 8'h3A;
			8'h52: base <= 8'h22;
			8'h5A: base <= 8'h0D;
			8'h41: base <= 8'h2C;
			8'h49: base <= 8'h2E;
			8'h4A: base <= 8'h2F;
			8'h76: base <= 8'h1B;
			8'h29: base <= 8'h20;

			8'h45: base <= 8'h30;
			8'h16: base <= 8'h31;
			8'h1E: base <= 8'h32;
			8'h26: base <= 8'h33;
			8'h25: base <= 8'h34;
			8'h2E: base <= 8'h35;
			8'h36: base <= 8'h36;
			8'h3D: base <= 8'h37;
			8'h3E: base <= 8'h38;
			8'h46: base <= 8'h39;

			8'h1C: base <= 8'h61;
			8'h32: base <= 8'h62;
			8'h21: base <= 8'h63;
			8'h23: base <= 8'h64;
			8'h24: base <= 8'h65;
			8'h2B: base <= 8'h66;
			8'h34: base <= 8'h67;
			8'h33: base <= 8'h68;
			8'h43: base <= 8'h69;
			8'h3B: base <= 8'h6A;
			8'h42: base <= 8'h6B;
			8'h4B: base <= 8'h6C;
			8'h3A: base <= 8'h6D;
			8'h31: base <= 8'h6E;
			8'h44: base <= 8'h6F;
			8'h4D: base <= 8'h70;
			8'h15: base <= 8'h71;
			8'h2D: base <= 8'h72;
			8'h1B: base <= 8'h73;
			8'h2C: base <= 8'h74;
			8'h3C: base <= 8'h75;
			8'h2A: base <= 8'h76;
			8'h1D: base <= 8'h77;
			8'h22: base <= 8'h78;
			8'h35: base <= 8'h79;
			8'h1A: base <= 8'h7A;
			default:
				invalid <= 1;
			endcase
		end
	end
	assign ascii = ctrl ? base[4:0] : base[6:0];
endmodule
module scan2ascii(
	input wire [7:0] scan,
	input wire shift,
	input wire ctrl,
	output wire [6:0] ascii,
	output reg invalid
);

	reg [7:0] base;
	always @(*) begin
		invalid <= 0;
		base <= 0;
		if(shift) begin
			case(scan)
			8'h0E: base <= 8'h7E;
			8'h4E: base <= 8'h5F;
			8'h55: base <= 8'h2B;
			8'h66: base <= 8'h7F;
			8'h0D: base <= 8'h09;
			8'h54: base <= 8'h7B;
			8'h5B: base <= 8'h7D;
			8'h5D: base <= 8'h7C;
			8'h4C: base <= 8'h3A;
			8'h52: base <= 8'h22;
			8'h5A: base <= 8'h0D;
			8'h41: base <= 8'h2C;
			8'h49: base <= 8'h2E;
			8'h4A: base <= 8'h2F;
			8'h76: base <= 8'h1B;
			8'h29: base <= 8'h20;

			8'h45: base <= 8'h30;
			8'h16: base <= 8'h31;
			8'h1E: base <= 8'h32;
			8'h26: base <= 8'h33;
			8'h25: base <= 8'h34;
			8'h2E: base <= 8'h35;
			8'h36: base <= 8'h36;
			8'h3D: base <= 8'h37;
			8'h3E: base <= 8'h38;
			8'h46: base <= 8'h39;

			8'h1C: base <= 8'h61;
			8'h32: base <= 8'h62;
			8'h21: base <= 8'h63;
			8'h23: base <= 8'h64;
			8'h24: base <= 8'h65;
			8'h2B: base <= 8'h66;
			8'h34: base <= 8'h67;
			8'h33: base <= 8'h68;
			8'h43: base <= 8'h69;
			8'h3B: base <= 8'h6A;
			8'h42: base <= 8'h6B;
			8'h4B: base <= 8'h6C;
			8'h3A: base <= 8'h6D;
			8'h31: base <= 8'h6E;
			8'h44: base <= 8'h6F;
			8'h4D: base <= 8'h70;
			8'h15: base <= 8'h71;
			8'h2D: base <= 8'h72;
			8'h1B: base <= 8'h73;
			8'h2C: base <= 8'h74;
			8'h3C: base <= 8'h75;
			8'h2A: base <= 8'h76;
			8'h1D: base <= 8'h77;
			8'h22: base <= 8'h78;
			8'h35: base <= 8'h79;
			8'h1A: base <= 8'h7A;
			default:
				invalid <= 1;
			endcase
		end
	end
	assign ascii = ctrl ? base[4:0] : base[6:0];
endmodule