data/full_repos/permissive/482848318/DPU_testbench.v
1: b'%Error: data/full_repos/permissive/482848318/DPU_testbench.v:17: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " din=%d, dsel=%b, seg=%b, dout=%d", din,dsel,seg,dout);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/482848318/DPU_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("DPU.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482848318/DPU_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, DPU_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482848318/DPU_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #0 din=0; dsel=0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482848318/DPU_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #50 din <= din + stepSize; dsel <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/482848318/DPU_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n       #50 dsel <= dsel + 1;\n       ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DPU_testbench();
  
  reg [15:0] din;
  reg [1:0] dsel;
  wire [7:0] seg, dout;
  
  DPU DUT (.din(din), .dsel(dsel), .seg(seg), .dout(dout));
  
  initial
  begin
    $monitor($time, " din=%d, dsel=%b, seg=%b, dout=%d", din,dsel,seg,dout);
  end
  
  integer stepSize = 100;
  
  initial
  begin
    $dumpfile("DPU.vcd");
    $dumpvars(1, DPU_testbench);
    
    #0 din=0; dsel=0;
    
    repeat (1023 / stepSize)
    begin
      #50 din <= din + stepSize; dsel <= 0;
      repeat (3)
      begin
      	#50 dsel <= dsel + 1;
      end
    end
    
  end
  
endmodule
module DPU_testbench();

  
  reg [15:0] din;
  reg [1:0] dsel;
  wire [7:0] seg, dout;
  
  DPU DUT (.din(din), .dsel(dsel), .seg(seg), .dout(dout));
  
  initial
  begin
    $monitor($time, " din=%d, dsel=%b, seg=%b, dout=%d", din,dsel,seg,dout);
  end
  
  integer stepSize = 100;
  
  initial
  begin
    $dumpfile("DPU.vcd");
    $dumpvars(1, DPU_testbench);
    
    #0 din=0; dsel=0;
    
    repeat (1023 / stepSize)
    begin
      #50 din <= din + stepSize; dsel <= 0;
      repeat (3)
      begin
      	#50 dsel <= dsel + 1;
      end
    end
    
  end
  
endmodule