data/full_repos/permissive/426072575/labs/lab3 Gate circuit design - familiarity with experimental environment and development board/codes/block design/mux3_2_1.v
1: b'%Error: Invalid Option: -\n'
module mux2_1(f,in0,in1,cntrl);
input[2:0] in0,in1;
input cntrl;
output reg[2:0] f;
always@ (in0, in1, cntrl)
    f=cntrl?in1:in0;
endmodule
module mux2_1(f,in0,in1,cntrl);

input[2:0] in0,in1;
input cntrl;
output reg[2:0] f;
always@ (in0, in1, cntrl)
    f=cntrl?in1:in0;
endmodule