data/full_repos/permissive/514992586/1_Verilog_language/Modules/25_Module_add.v
1: b"%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/25_Module_add.v:9: Cannot find file containing module: 'add16'\n    add16 instance1(.a(a[15:0]),\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16.v\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/25_Module_add.v:14: Cannot find file containing module: 'add16'\n    add16 instance2(.a(a[31:16]),\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
	wire w1;
    wire w2;
    assign w1 = 1'b0;
    add16 instance1(.a(a[15:0]),
                    .b(b[15:0]),
                    .cin(w1),
                    .sum(sum[15:0]),
                    .cout(w2));
    add16 instance2(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(w2),
                    .sum(sum[31:16]));
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

	wire w1;
    wire w2;
    assign w1 = 1'b0;
    add16 instance1(.a(a[15:0]),
                    .b(b[15:0]),
                    .cin(w1),
                    .sum(sum[15:0]),
                    .cout(w2));
    add16 instance2(.a(a[31:16]),
                    .b(b[31:16]),
                    .cin(w2),
                    .sum(sum[31:16]));
endmodule