data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:149: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_1[1]<=d1[1]+d1[9]; ra1_1[3]<=d1[3]+d1[7];ra1_1[5]<=d1[5];\n                                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:152: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_2[1]<=d2[1]+d2[9]; ra1_2[3]<=d2[3]+d2[7];ra1_2[5]<=d2[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:155: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_3[1]<=d3[1]+d3[9]; ra1_3[3]<=d3[3]+d3[7];ra1_3[5]<=d3[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:158: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_4[1]<=d4[1]+d4[9]; ra1_4[3]<=d4[3]+d4[7];ra1_4[5]<=d4[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:161: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_5[1]<=d5[1]+d5[9]; ra1_5[3]<=d5[3]+d5[7];ra1_5[5]<=d5[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:164: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_6[1]<=d6[1]+d6[9]; ra1_6[3]<=d6[3]+d6[7];ra1_6[5]<=d6[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:167: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_7[1]<=d7[1]+d7[9]; ra1_7[3]<=d7[3]+d7[7];ra1_7[5]<=d7[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:170: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_8[1]<=d8[1]+d8[9]; ra1_8[3]<=d8[3]+d8[7];ra1_8[5]<=d8[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:173: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_9[1]<=d9[1]+d9[9]; ra1_9[3]<=d9[3]+d9[7];ra1_9[5]<=d9[5];\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:176: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_10[1]<=d10[1]+d10[9]; ra1_10[3]<=d10[3]+d10[7];ra1_10[5]<=d10[5];\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:179: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                           : ... In instance CONV\n   ra1_11[1]<=d11[1]+d11[9]; ra1_11[3]<=d11[3]+d11[7];ra1_11[5]<=d11[5];\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:196: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[0]<=ra1_6[0];ra2_6[2]<=ra1_6[2];ra2_6[4]<=ra1_6[4];\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:196: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[0]<=ra1_6[0];ra2_6[2]<=ra1_6[2];ra2_6[4]<=ra1_6[4];\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:196: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[0]<=ra1_6[0];ra2_6[2]<=ra1_6[2];ra2_6[4]<=ra1_6[4];\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:197: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[1]<=ra1_6[1];ra2_6[3]<=ra1_6[3];ra2_6[5]<=ra1_6[5];   \n           ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:197: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[1]<=ra1_6[1];ra2_6[3]<=ra1_6[3];ra2_6[5]<=ra1_6[5];   \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:197: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                           : ... In instance CONV\n   ra2_6[1]<=ra1_6[1];ra2_6[3]<=ra1_6[3];ra2_6[5]<=ra1_6[5];   \n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:203: Operator ASSIGNDLY expects 22 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 21 bits.\n                                                                                           : ... In instance CONV\n   r1_2[2]<=r1_1[2]; \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:205: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 22 bits.\n                                                                                           : ... In instance CONV\n   r1_3[1]<=r1_2[2];\n          ^~\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:213: Cannot find file containing module: \'cov\'\n cov cov1_1(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/cov\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/cov.v\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/cov.sv\n             cov\n             cov.v\n             cov.sv\n             obj_dir/cov\n             obj_dir/cov.v\n             obj_dir/cov.sv\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:226: Cannot find file containing module: \'cov\'\n cov cov1_2(\n ^~~\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:238: Cannot find file containing module: \'cov\'\n cov cov1_3(   \n ^~~\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:252: Cannot find file containing module: \'cov\'\n cov cov1_4(\n ^~~\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/CONV.v:265: Cannot find file containing module: \'cov\'\n cov cov1_5(\n ^~~\n%Error: Exiting due to 5 error(s), 19 warning(s)\n'
module CONV(clk, rst, din1, din2, din3, din4, din5, din6, din7, din8, din9, din10, din11, 
				  df1_1, df1_2, df1_3, df1_4, df1_5, df1_6, df1_7, df1_8, df1_9, df1_10, df1_11,
				  dout,out_en);
    input clk;
    input rst;
    input [87:0] din1;
    input [87:0] din2;
    input [87:0] din3;
    input [87:0] din4;
    input [87:0] din5;
    input [87:0] din6;
    input [87:0] din7;
    input [87:0] din8;
    input [87:0] din9;
    input [87:0] din10;
    input [87:0] din11;
	 
	input [47:0] df1_1;
	input [47:0] df1_2;
	input [47:0] df1_3;
	input [47:0] df1_4;
	input [47:0] df1_5;
	input [47:0] df1_6;
	input [47:0] df1_7;
	input [47:0] df1_8;
	input [47:0] df1_9;
	input [47:0] df1_10;
	input [47:0] df1_11;
	 
    output [17:0] dout;
    output out_en;
	 

	reg [23:0] dout1;
	wire [17:0] dout;  reg [4:0] cnt_out_en; reg out_en;
	assign dout=dout1[17:0];
	
	always @(posedge clk or negedge rst)
	begin
	if(!rst)
	begin
		out_en<=0;
		cnt_out_en<=0;
	end
	else
	begin
		if(cnt_out_en>=10)
			out_en<=1;
		else
		begin
			cnt_out_en<=cnt_out_en+1;
			out_en<=0;
		end
	end
	end
	

	wire [7:0] d1[10:0];wire [7:0] d2[10:0];wire [7:0] d3[10:0];wire [7:0] d4[10:0];wire [7:0] d5[10:0];
	wire [7:0] d6[10:0];wire [7:0] d7[10:0];wire [7:0] d8[10:0];wire [7:0] d9[10:0];wire [7:0] d10[10:0];
	wire [7:0] d11[10:0];


	wire [7:0] k1_1[5:0];wire [7:0] k1_2[5:0];wire [7:0] k1_3[5:0];wire [7:0] k1_4[5:0];wire [7:0] k1_5[5:0];
	wire [7:0] k1_6[5:0];wire [7:0] k1_7[5:0];wire [7:0] k1_8[5:0];wire [7:0] k1_9[5:0];wire [7:0] k1_10[5:0];
	wire [7:0] k1_11[5:0];


	assign {d1[10],d1[9],d1[8],d1[7],d1[6],d1[5],d1[4],d1[3],d1[2],d1[1],d1[0]}=din1;
	assign {d2[10],d2[9],d2[8],d2[7],d2[6],d2[5],d2[4],d2[3],d2[2],d2[1],d2[0]}=din2;
	assign {d3[10],d3[9],d3[8],d3[7],d3[6],d3[5],d3[4],d3[3],d3[2],d3[1],d3[0]}=din3;
	assign {d4[10],d4[9],d4[8],d4[7],d4[6],d4[5],d4[4],d4[3],d4[2],d4[1],d4[0]}=din4;
	assign {d5[10],d5[9],d5[8],d5[7],d5[6],d5[5],d5[4],d5[3],d5[2],d5[1],d5[0]}=din5;
	assign {d6[10],d6[9],d6[8],d6[7],d6[6],d6[5],d6[4],d6[3],d6[2],d6[1],d6[0]}=din6;
	assign {d7[10],d7[9],d7[8],d7[7],d7[6],d7[5],d7[4],d7[3],d7[2],d7[1],d7[0]}=din7;
	assign {d8[10],d8[9],d8[8],d8[7],d8[6],d8[5],d8[4],d8[3],d8[2],d8[1],d8[0]}=din8;
	assign {d9[10],d9[9],d9[8],d9[7],d9[6],d9[5],d9[4],d9[3],d9[2],d9[1],d9[0]}=din9;
	assign {d10[10],d10[9],d10[8],d10[7],d10[6],d10[5],d10[4],d10[3],d10[2],d10[1],d10[0]}=din10;
	assign {d11[10],d11[9],d11[8],d11[7],d11[6],d11[5],d11[4],d11[3],d11[2],d11[1],d11[0]}=din11;


	assign {k1_1[5],k1_1[4],k1_1[3],k1_1[2],k1_1[1],k1_1[0]}=df1_1;
	assign {k1_2[5],k1_2[4],k1_2[3],k1_2[2],k1_2[1],k1_2[0]}=df1_2;
	assign {k1_3[5],k1_3[4],k1_3[3],k1_3[2],k1_3[1],k1_3[0]}=df1_3;
	assign {k1_4[5],k1_4[4],k1_4[3],k1_4[2],k1_4[1],k1_4[0]}=df1_4;
	assign {k1_5[5],k1_5[4],k1_5[3],k1_5[2],k1_5[1],k1_5[0]}=df1_5;
	assign {k1_6[5],k1_6[4],k1_6[3],k1_6[2],k1_6[1],k1_6[0]}=df1_6;
	assign {k1_7[5],k1_7[4],k1_7[3],k1_7[2],k1_7[1],k1_7[0]}=df1_7;
	assign {k1_8[5],k1_8[4],k1_8[3],k1_8[2],k1_8[1],k1_8[0]}=df1_8;
	assign {k1_9[5],k1_9[4],k1_9[3],k1_9[2],k1_9[1],k1_9[0]}=df1_9;
	assign {k1_10[5],k1_10[4],k1_10[3],k1_10[2],k1_10[1],k1_10[0]}=df1_10;
	assign {k1_11[5],k1_11[4],k1_11[3],k1_11[2],k1_11[1],k1_11[0]}=df1_11;

	

	wire [20:0] r1_1[4:0];
	reg [21:0] r1_2[2:0];
	reg [22:0] r1_3[1:0];

	reg [8:0] ra1_1[5:0];
	reg [8:0] ra1_2[5:0];
	reg [8:0] ra1_3[5:0];
	reg [8:0] ra1_4[5:0];
	reg [8:0] ra1_5[5:0];
	reg [8:0] ra1_6[5:0];
	reg [8:0] ra1_7[5:0];
	reg [8:0] ra1_8[5:0];
	reg [8:0] ra1_9[5:0];
	reg [8:0] ra1_10[5:0];
	reg [8:0] ra1_11[5:0];
	
	reg [9:0] ra2_1[5:0];
	reg [9:0] ra2_2[5:0];
	reg [9:0] ra2_3[5:0];
	reg [9:0] ra2_4[5:0];
	reg [9:0] ra2_5[5:0];
	reg [9:0] ra2_6[5:0];
	 

	always @(posedge clk,negedge rst)
	begin
		if(!rst)
		begin
			dout1 <= 'd0;
		end
		else
		begin

	cov cov1_1(
		.clk(clk), .rst(rst), 
		
		.din1(ra2_1[0]), .din2(ra2_1[1]), .din3(ra2_1[2]), .din4(ra2_1[3]), 
		.din5(ra2_1[4]), .din6(ra2_1[5]),.din7(ra2_2[0]), .din8(ra2_2[1]),
	
		.k1(k1_1[5]), .k2(k1_1[4]), .k3(k1_1[3]),.k4(k1_1[2]),.k5(k1_1[1]), 
		.k6(k1_1[0]), .k7(k1_2[5]), .k8(k1_2[4]),
		.dout(r1_1[0])
	);
	
	
				  
	cov cov1_2(
		.clk(clk), .rst(rst),  
		
		.din1(ra2_2[2]), .din2(ra2_2[3]), .din3(ra2_2[4]), .din4(ra2_2[5]), 
		.din5(ra2_3[0]), .din6(ra2_3[1]), .din7(ra2_3[2]), .din8(ra2_3[3]),
		
		.k1(k1_2[3]), .k2(k1_2[2]), .k3(k1_2[1]),.k4(k1_2[0]),.k5(k1_3[5]), 
		.k6(k1_3[4]), .k7(k1_3[3]), .k8(k1_3[2]),
		.dout(r1_1[1])
	);
				  
				  
	cov cov1_3(	  
		.clk(clk), .rst(rst),  
		
		.din1(ra2_3[4]), .din2(ra2_3[5]), .din3(ra2_4[0]), .din4(ra2_4[1]),
		.din5(ra2_4[2]), .din6(ra2_4[3]), .din7(ra2_4[4]), .din8(ra2_4[5]),
				  
		.k1(k1_3[1]), .k2(k1_3[0]), .k3(k1_4[5]),.k4(k1_4[4]),.k5(k1_4[3]),
		.k6(k1_4[2]), .k7(k1_4[1]), .k8(k1_4[0]),
				  
		.dout(r1_1[2])
	);
				  
				  
				  
	cov cov1_4(
		.clk(clk), .rst(rst), 
	
		.din1(ra2_5[0]), .din2(ra2_5[1]), .din3(ra2_5[2]), .din4(ra2_5[3]),
		.din5(ra2_5[4]), .din6(ra2_5[5]),.din7(ra2_6[0]), .din8(ra2_6[1]),
				  
		.k1(k1_5[5]), .k2(k1_5[4]), .k3(k1_5[3]),.k4(k1_5[2]),.k5(k1_5[1]),
		.k6(k1_5[0]), .k7(k1_6[5]), .k8(k1_6[4]),
				  
		.dout(r1_1[3])
	);
				  
				  		  
	cov cov1_5(
		.clk(clk), .rst(rst), 
		
		.din1(ra2_6[2]), .din2(ra2_6[3]), .din3(ra2_6[4]), .din4(ra2_6[5]),
		.din5(0), .din6(0),.din7(0), .din8(0),
		
		.k1(k1_6[3]), .k2(k1_6[2]), .k3(k1_6[1]),.k4(k1_6[0]),.k5(0),
		.k6(0), .k7(0), .k8(0),

		.dout(r1_1[4])
	);
				  

	
endmodule
module CONV(clk, rst, din1, din2, din3, din4, din5, din6, din7, din8, din9, din10, din11, 
				  df1_1, df1_2, df1_3, df1_4, df1_5, df1_6, df1_7, df1_8, df1_9, df1_10, df1_11,
				  dout,out_en);

    input clk;
    input rst;
    input [87:0] din1;
    input [87:0] din2;
    input [87:0] din3;
    input [87:0] din4;
    input [87:0] din5;
    input [87:0] din6;
    input [87:0] din7;
    input [87:0] din8;
    input [87:0] din9;
    input [87:0] din10;
    input [87:0] din11;
	 
	input [47:0] df1_1;
	input [47:0] df1_2;
	input [47:0] df1_3;
	input [47:0] df1_4;
	input [47:0] df1_5;
	input [47:0] df1_6;
	input [47:0] df1_7;
	input [47:0] df1_8;
	input [47:0] df1_9;
	input [47:0] df1_10;
	input [47:0] df1_11;
	 
    output [17:0] dout;
    output out_en;
	 

	reg [23:0] dout1;
	wire [17:0] dout;  reg [4:0] cnt_out_en; reg out_en;
	assign dout=dout1[17:0];
	
	always @(posedge clk or negedge rst)
	begin
	if(!rst)
	begin
		out_en<=0;
		cnt_out_en<=0;
	end
	else
	begin
		if(cnt_out_en>=10)
			out_en<=1;
		else
		begin
			cnt_out_en<=cnt_out_en+1;
			out_en<=0;
		end
	end
	end
	

	wire [7:0] d1[10:0];wire [7:0] d2[10:0];wire [7:0] d3[10:0];wire [7:0] d4[10:0];wire [7:0] d5[10:0];
	wire [7:0] d6[10:0];wire [7:0] d7[10:0];wire [7:0] d8[10:0];wire [7:0] d9[10:0];wire [7:0] d10[10:0];
	wire [7:0] d11[10:0];


	wire [7:0] k1_1[5:0];wire [7:0] k1_2[5:0];wire [7:0] k1_3[5:0];wire [7:0] k1_4[5:0];wire [7:0] k1_5[5:0];
	wire [7:0] k1_6[5:0];wire [7:0] k1_7[5:0];wire [7:0] k1_8[5:0];wire [7:0] k1_9[5:0];wire [7:0] k1_10[5:0];
	wire [7:0] k1_11[5:0];


	assign {d1[10],d1[9],d1[8],d1[7],d1[6],d1[5],d1[4],d1[3],d1[2],d1[1],d1[0]}=din1;
	assign {d2[10],d2[9],d2[8],d2[7],d2[6],d2[5],d2[4],d2[3],d2[2],d2[1],d2[0]}=din2;
	assign {d3[10],d3[9],d3[8],d3[7],d3[6],d3[5],d3[4],d3[3],d3[2],d3[1],d3[0]}=din3;
	assign {d4[10],d4[9],d4[8],d4[7],d4[6],d4[5],d4[4],d4[3],d4[2],d4[1],d4[0]}=din4;
	assign {d5[10],d5[9],d5[8],d5[7],d5[6],d5[5],d5[4],d5[3],d5[2],d5[1],d5[0]}=din5;
	assign {d6[10],d6[9],d6[8],d6[7],d6[6],d6[5],d6[4],d6[3],d6[2],d6[1],d6[0]}=din6;
	assign {d7[10],d7[9],d7[8],d7[7],d7[6],d7[5],d7[4],d7[3],d7[2],d7[1],d7[0]}=din7;
	assign {d8[10],d8[9],d8[8],d8[7],d8[6],d8[5],d8[4],d8[3],d8[2],d8[1],d8[0]}=din8;
	assign {d9[10],d9[9],d9[8],d9[7],d9[6],d9[5],d9[4],d9[3],d9[2],d9[1],d9[0]}=din9;
	assign {d10[10],d10[9],d10[8],d10[7],d10[6],d10[5],d10[4],d10[3],d10[2],d10[1],d10[0]}=din10;
	assign {d11[10],d11[9],d11[8],d11[7],d11[6],d11[5],d11[4],d11[3],d11[2],d11[1],d11[0]}=din11;


	assign {k1_1[5],k1_1[4],k1_1[3],k1_1[2],k1_1[1],k1_1[0]}=df1_1;
	assign {k1_2[5],k1_2[4],k1_2[3],k1_2[2],k1_2[1],k1_2[0]}=df1_2;
	assign {k1_3[5],k1_3[4],k1_3[3],k1_3[2],k1_3[1],k1_3[0]}=df1_3;
	assign {k1_4[5],k1_4[4],k1_4[3],k1_4[2],k1_4[1],k1_4[0]}=df1_4;
	assign {k1_5[5],k1_5[4],k1_5[3],k1_5[2],k1_5[1],k1_5[0]}=df1_5;
	assign {k1_6[5],k1_6[4],k1_6[3],k1_6[2],k1_6[1],k1_6[0]}=df1_6;
	assign {k1_7[5],k1_7[4],k1_7[3],k1_7[2],k1_7[1],k1_7[0]}=df1_7;
	assign {k1_8[5],k1_8[4],k1_8[3],k1_8[2],k1_8[1],k1_8[0]}=df1_8;
	assign {k1_9[5],k1_9[4],k1_9[3],k1_9[2],k1_9[1],k1_9[0]}=df1_9;
	assign {k1_10[5],k1_10[4],k1_10[3],k1_10[2],k1_10[1],k1_10[0]}=df1_10;
	assign {k1_11[5],k1_11[4],k1_11[3],k1_11[2],k1_11[1],k1_11[0]}=df1_11;

	

	wire [20:0] r1_1[4:0];
	reg [21:0] r1_2[2:0];
	reg [22:0] r1_3[1:0];

	reg [8:0] ra1_1[5:0];
	reg [8:0] ra1_2[5:0];
	reg [8:0] ra1_3[5:0];
	reg [8:0] ra1_4[5:0];
	reg [8:0] ra1_5[5:0];
	reg [8:0] ra1_6[5:0];
	reg [8:0] ra1_7[5:0];
	reg [8:0] ra1_8[5:0];
	reg [8:0] ra1_9[5:0];
	reg [8:0] ra1_10[5:0];
	reg [8:0] ra1_11[5:0];
	
	reg [9:0] ra2_1[5:0];
	reg [9:0] ra2_2[5:0];
	reg [9:0] ra2_3[5:0];
	reg [9:0] ra2_4[5:0];
	reg [9:0] ra2_5[5:0];
	reg [9:0] ra2_6[5:0];
	 

	always @(posedge clk,negedge rst)
	begin
		if(!rst)
		begin
			dout1 <= 'd0;
		end
		else
		begin

	cov cov1_1(
		.clk(clk), .rst(rst), 
		
		.din1(ra2_1[0]), .din2(ra2_1[1]), .din3(ra2_1[2]), .din4(ra2_1[3]), 
		.din5(ra2_1[4]), .din6(ra2_1[5]),.din7(ra2_2[0]), .din8(ra2_2[1]),
	
		.k1(k1_1[5]), .k2(k1_1[4]), .k3(k1_1[3]),.k4(k1_1[2]),.k5(k1_1[1]), 
		.k6(k1_1[0]), .k7(k1_2[5]), .k8(k1_2[4]),
		.dout(r1_1[0])
	);
	
	
				  
	cov cov1_2(
		.clk(clk), .rst(rst),  
		
		.din1(ra2_2[2]), .din2(ra2_2[3]), .din3(ra2_2[4]), .din4(ra2_2[5]), 
		.din5(ra2_3[0]), .din6(ra2_3[1]), .din7(ra2_3[2]), .din8(ra2_3[3]),
		
		.k1(k1_2[3]), .k2(k1_2[2]), .k3(k1_2[1]),.k4(k1_2[0]),.k5(k1_3[5]), 
		.k6(k1_3[4]), .k7(k1_3[3]), .k8(k1_3[2]),
		.dout(r1_1[1])
	);
				  
				  
	cov cov1_3(	  
		.clk(clk), .rst(rst),  
		
		.din1(ra2_3[4]), .din2(ra2_3[5]), .din3(ra2_4[0]), .din4(ra2_4[1]),
		.din5(ra2_4[2]), .din6(ra2_4[3]), .din7(ra2_4[4]), .din8(ra2_4[5]),
				  
		.k1(k1_3[1]), .k2(k1_3[0]), .k3(k1_4[5]),.k4(k1_4[4]),.k5(k1_4[3]),
		.k6(k1_4[2]), .k7(k1_4[1]), .k8(k1_4[0]),
				  
		.dout(r1_1[2])
	);
				  
				  
				  
	cov cov1_4(
		.clk(clk), .rst(rst), 
	
		.din1(ra2_5[0]), .din2(ra2_5[1]), .din3(ra2_5[2]), .din4(ra2_5[3]),
		.din5(ra2_5[4]), .din6(ra2_5[5]),.din7(ra2_6[0]), .din8(ra2_6[1]),
				  
		.k1(k1_5[5]), .k2(k1_5[4]), .k3(k1_5[3]),.k4(k1_5[2]),.k5(k1_5[1]),
		.k6(k1_5[0]), .k7(k1_6[5]), .k8(k1_6[4]),
				  
		.dout(r1_1[3])
	);
				  
				  		  
	cov cov1_5(
		.clk(clk), .rst(rst), 
		
		.din1(ra2_6[2]), .din2(ra2_6[3]), .din3(ra2_6[4]), .din4(ra2_6[5]),
		.din5(0), .din6(0),.din7(0), .din8(0),
		
		.k1(k1_6[3]), .k2(k1_6[2]), .k3(k1_6[1]),.k4(k1_6[0]),.k5(0),
		.k6(0), .k7(0), .k8(0),

		.dout(r1_1[4])
	);
				  

	
endmodule