data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/addshift_test.v
data/verilator_xmls/c385b775-4bca-4c7e-a466-dff75c6055df.xml
module test (A, B, X, Y);
input [7:0] A, B;
output [7:0] X = A + B;
output [7:0] Y = A + A;
endmodule
module test (A, B, X, Y);

input [7:0] A, B;
output [7:0] X = A + B;
output [7:0] Y = A + A;
endmodule