data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:288: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb } + { 1\'b0, inpa} + cin:\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:289: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb } - { 1\'b0, inpa} - cin;\n                                       ^\n%Error: Exiting due to 16 warning(s)\n'
module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
	output logic [4:0] aluOp);
	
	always_comb begin
		aluOp = 'X;
		unique case( col)  
		1:   aluOp = OP_AND;
		5:   aluOp = OP_EXT;

		default:
			unique case( 1'b1)
				row[1]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_SUBC;
					4,6: aluOp = OP_SLAA;
					endcase
				
				row[2]:
					unique case( col)
					2: aluOp = OP_ADD;
					3: aluOp = OP_ADDC;
					4: aluOp = OP_ASR;
					endcase

				row[3]:
					unique case( col)
					2: aluOp = OP_ADDX;
					3: aluOp = isCorf ? OP_ABCD : OP_ADD;
					4: aluOp = OP_ASL;
					endcase
                  
				row[4]:
					aluOp = ( col == 4) ? OP_LSL : OP_AND;
				
				row[5],
				row[6]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_SUBC;
					4: aluOp = OP_LSR;
					endcase
				
				row[7]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_ADD;
					4: aluOp = OP_ROXR;
					endcase
               
				row[8]:


					unique case( col)
					2: aluOp = OP_EXT;
					3: aluOp = OP_AND;
					4: aluOp = OP_ROXR;
					endcase
               
				row[9]:
					unique case( col)
					2: aluOp = OP_SUBX;
					3: aluOp = OP_SBCD;
					4: aluOp = OP_ROL;
					endcase

				row[10]:
					unique case( col)
					2: aluOp = OP_SUBX;
					3: aluOp = OP_SUBC;
					4: aluOp = OP_ROR;
					endcase
                
				row[11]:
					unique case( col)
					2: aluOp = OP_SUB0;
					3: aluOp = OP_SUB0;
					4: aluOp = OP_ROXL;
					endcase
                
				row[12]:	aluOp = OP_ADDX;               
				row[13]:	aluOp = OP_EOR;
				row[14]:	aluOp = (col == 4) ? OP_EOR : OP_OR;
				row[15]:	aluOp = (col == 3) ? OP_ADD : OP_OR;
				
			endcase         
		endcase
	end
endmodule
module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
	output logic [4:0] aluOp);

	
	always_comb begin
		aluOp = 'X;
		unique case( col)  
		1:   aluOp = OP_AND;
		5:   aluOp = OP_EXT;

		default:
			unique case( 1'b1)
				row[1]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_SUBC;
					4,6: aluOp = OP_SLAA;
					endcase
				
				row[2]:
					unique case( col)
					2: aluOp = OP_ADD;
					3: aluOp = OP_ADDC;
					4: aluOp = OP_ASR;
					endcase

				row[3]:
					unique case( col)
					2: aluOp = OP_ADDX;
					3: aluOp = isCorf ? OP_ABCD : OP_ADD;
					4: aluOp = OP_ASL;
					endcase
                  
				row[4]:
					aluOp = ( col == 4) ? OP_LSL : OP_AND;
				
				row[5],
				row[6]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_SUBC;
					4: aluOp = OP_LSR;
					endcase
				
				row[7]:
					unique case( col)
					2: aluOp = OP_SUB;
					3: aluOp = OP_ADD;
					4: aluOp = OP_ROXR;
					endcase
               
				row[8]:


					unique case( col)
					2: aluOp = OP_EXT;
					3: aluOp = OP_AND;
					4: aluOp = OP_ROXR;
					endcase
               
				row[9]:
					unique case( col)
					2: aluOp = OP_SUBX;
					3: aluOp = OP_SBCD;
					4: aluOp = OP_ROL;
					endcase

				row[10]:
					unique case( col)
					2: aluOp = OP_SUBX;
					3: aluOp = OP_SUBC;
					4: aluOp = OP_ROR;
					endcase
                
				row[11]:
					unique case( col)
					2: aluOp = OP_SUB0;
					3: aluOp = OP_SUB0;
					4: aluOp = OP_ROXL;
					endcase
                
				row[12]:	aluOp = OP_ADDX;               
				row[13]:	aluOp = OP_EOR;
				row[14]:	aluOp = (col == 4) ? OP_EOR : OP_OR;
				row[15]:	aluOp = (col == 3) ? OP_ADD : OP_OR;
				
			endcase         
		endcase
	end
endmodule