data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/my_fifo256.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/my_fifo256.v:104: Operator NEQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 9 bits.\n                                                                                                  : ... In instance my_fifo256\n   1: if(cnt!=(size-1)) cnt<=cnt+1;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/my_fifo256.v:117: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 9 bits.\n                                                                                                  : ... In instance my_fifo256\n  if(cnt==(size-2))\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module my_fifo256(clk, rst, rd_en, wr_en, din, dout, empty, full, cnt);
    input clk;
    input rst;
    input rd_en;
    input wr_en;
    input [7:0] din;
    output [7:0] dout;
    output empty;
    output full;
	 output cnt; 
	
	 parameter size=512;
	 parameter deep=9;

	 reg[7:0] ram[0:size-1];
	 reg[7:0] dout;
	 reg empty;
	 reg full;
	 reg [(deep-1):0] rd_ptr,wr_ptr,cnt;

	 always @(posedge clk)
	 begin
	 	if(!rst)
			begin
				dout<=8'bzzzzzzzz;

			end
		else if(rd_en==1&&empty==0)
		begin
			dout<=ram[rd_ptr];
		end

	 end

	 always@(posedge clk)
	 begin
	 	if(rst&&wr_en)
		begin
			ram[wr_ptr]<=din;
		end
	 end

	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			wr_ptr<=0;
		end
		else
		begin
			if(wr_en)
			begin
				wr_ptr<=wr_ptr+1;
			end
		end
	 end

	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			rd_ptr<=0;
		end
		else
		begin
			if(rd_en&&!empty)
			begin
				rd_ptr<=rd_ptr+1;
			end
		end
	 end


	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			cnt<=0;
		end
		else
		begin
		case({rd_en,wr_en})
			0:	cnt<=cnt;
			1:	if(cnt!=(size-1)) cnt<=cnt+1;
			2:	if(cnt!=0) cnt<=cnt-1;
			3:	cnt<=cnt;
		endcase
		end
	 end

	 always @ (cnt)
	 begin
	 	if(cnt==0)
			empty<=1;
		else
			empty<=0;
		if(cnt==(size-2))
			full<=1;
		else
			full<=0;
	 end






endmodule
module my_fifo256(clk, rst, rd_en, wr_en, din, dout, empty, full, cnt);

    input clk;
    input rst;
    input rd_en;
    input wr_en;
    input [7:0] din;
    output [7:0] dout;
    output empty;
    output full;
	 output cnt; 
	
	 parameter size=512;
	 parameter deep=9;

	 reg[7:0] ram[0:size-1];
	 reg[7:0] dout;
	 reg empty;
	 reg full;
	 reg [(deep-1):0] rd_ptr,wr_ptr,cnt;

	 always @(posedge clk)
	 begin
	 	if(!rst)
			begin
				dout<=8'bzzzzzzzz;

			end
		else if(rd_en==1&&empty==0)
		begin
			dout<=ram[rd_ptr];
		end

	 end

	 always@(posedge clk)
	 begin
	 	if(rst&&wr_en)
		begin
			ram[wr_ptr]<=din;
		end
	 end

	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			wr_ptr<=0;
		end
		else
		begin
			if(wr_en)
			begin
				wr_ptr<=wr_ptr+1;
			end
		end
	 end

	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			rd_ptr<=0;
		end
		else
		begin
			if(rd_en&&!empty)
			begin
				rd_ptr<=rd_ptr+1;
			end
		end
	 end


	 always@(posedge clk)
	 begin
	 	if(!rst)
		begin
			cnt<=0;
		end
		else
		begin
		case({rd_en,wr_en})
			0:	cnt<=cnt;
			1:	if(cnt!=(size-1)) cnt<=cnt+1;
			2:	if(cnt!=0) cnt<=cnt-1;
			3:	cnt<=cnt;
		endcase
		end
	 end

	 always @ (cnt)
	 begin
	 	if(cnt==0)
			empty<=1;
		else
			empty<=0;
		if(cnt==(size-2))
			full<=1;
		else
			full<=0;
	 end






endmodule