data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v
1: b'%Warning-MODDUP: data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v:47: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v:2: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module( 
    input [7:0] in,
    output [7:0] out
);
    
    always @(*) begin
        for(integer i = 0; i < 8; i = i + 1)
            out[i] = in[7 - i];
    end

endmodule
module top_module( 
    input [7:0] in,
    output [7:0] out
);

    
    always @(*) begin
        for(integer i = 0; i < 8; i = i + 1)
            out[i] = in[7 - i];
    end

endmodule