data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:49: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance Single_Cycle_CPU\n    assign stall = 1\'b0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:54: Cannot find file containing module: \'PC\'\n    PC              pc          (clk, stall, pc_in, pc_out);\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/490649362/single-cycle/src,data/full_repos/permissive/490649362/PC\n             data/full_repos/permissive/490649362/single-cycle/src,data/full_repos/permissive/490649362/PC.v\n             data/full_repos/permissive/490649362/single-cycle/src,data/full_repos/permissive/490649362/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:55: Cannot find file containing module: \'IM\'\n    IM      #(64)   im          (pc_out, inst);\n    ^~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:56: Cannot find file containing module: \'Control\'\n    Control         control     (inst[31:26], RegDst, Jump, BranchEq, BranchNe, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite);\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:57: Cannot find file containing module: \'MUX2_1\'\n    MUX2_1  #(5)    mux_RegDst  (inst[20:16], inst[15:11], RegDst, reg_write_addr);\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:58: Cannot find file containing module: \'RegFile\'\n    RegFile         reg_file    (clk, RegWrite, inst[25:21], inst[20:16], reg_write_addr, reg_write_data, reg_read_data_1, reg_read_data_2);\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:59: Cannot find file containing module: \'SignExt\'\n    SignExt         sign_ext    (inst[15:0], sign_ext_out);\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:60: Cannot find file containing module: \'MUX2_1\'\n    MUX2_1  #(32)   mux_ALUSrc  (reg_read_data_2, sign_ext_out, ALUSrc, alu_in_2);\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:61: Cannot find file containing module: \'ALUCtrl\'\n    ALUCtrl         alu_control (ALUOp, inst[5:0], alu_ctrl);\n    ^~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:62: Cannot find file containing module: \'ALU\'\n    ALU             alu         (alu_ctrl, reg_read_data_1, alu_in_2, alu_zero, alu_result);\n    ^~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:63: Cannot find file containing module: \'DM\'\n    DM      #(64)   dm          (clk, alu_result, reg_read_data_2, mem_read_data, MemWrite, MemRead);\n    ^~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:64: Cannot find file containing module: \'MUX2_1\'\n    MUX2_1  #(32)   mux_Mem2Reg (alu_result, mem_read_data, MemtoReg, reg_write_data);\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:65: Cannot find file containing module: \'Adder4\'\n    Adder4          adder4      (pc_out, pc_plus_4);\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:66: Cannot find file containing module: \'LeftShift2\'\n    LeftShift2      ls2         (sign_ext_out, imm_left_shift_2);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:67: Cannot find file containing module: \'Adder2_1\'\n    Adder2_1        adder2_1    (pc_plus_4, imm_left_shift_2, branch_addr);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:68: Cannot find file containing module: \'MUX2_1\'\n    MUX2_1  #(32)   mux_branch  (pc_plus_4, branch_addr, Branch, mux_branch_to_jump);\n    ^~~~~~\n%Error: data/full_repos/permissive/490649362/single-cycle/src/Single_Cycle_CPU.v:69: Cannot find file containing module: \'MUX2_1\'\n    MUX2_1  #(32)   mux_jump    (mux_branch_to_jump, jump_addr, Jump, pc_in);\n    ^~~~~~\n%Error: Exiting due to 16 error(s), 1 warning(s)\n'
module Single_Cycle_CPU(clk);

    input clk;


    wire [31:0] pc_in,
                pc_out,
                pc_plus_4,
                inst,
                stall;


    wire        RegDst,
                Jump,
                BranchEq,
                BranchNe,
                MemRead,
                MemtoReg,
                MemWrite,
                ALUSrc,
                RegWrite;
    wire [1:0]  ALUOp;


    wire [4:0]  reg_write_addr;
    wire [31:0] reg_write_data,
                reg_read_data_1,
                reg_read_data_2;


    wire        alu_zero;
    wire [3:0]  alu_ctrl;
    wire [31:0] sign_ext_out,
                alu_in_2,
                alu_result;

    wire [31:0] mem_read_data;


    wire        Branch;
    wire [31:0] imm_left_shift_2,
                mux_branch_to_jump,
                branch_addr,
                jump_addr;

    assign stall = 1'b0;
    assign jump_addr = {pc_plus_4[31:28], inst[25:0], 2'b0};
    assign Branch = (BranchEq & alu_zero) | (BranchNe & ~alu_zero);


    PC              pc          (clk, stall, pc_in, pc_out);
    IM      #(64)   im          (pc_out, inst);
    Control         control     (inst[31:26], RegDst, Jump, BranchEq, BranchNe, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite);
    MUX2_1  #(5)    mux_RegDst  (inst[20:16], inst[15:11], RegDst, reg_write_addr);
    RegFile         reg_file    (clk, RegWrite, inst[25:21], inst[20:16], reg_write_addr, reg_write_data, reg_read_data_1, reg_read_data_2);
    SignExt         sign_ext    (inst[15:0], sign_ext_out);
    MUX2_1  #(32)   mux_ALUSrc  (reg_read_data_2, sign_ext_out, ALUSrc, alu_in_2);
    ALUCtrl         alu_control (ALUOp, inst[5:0], alu_ctrl);
    ALU             alu         (alu_ctrl, reg_read_data_1, alu_in_2, alu_zero, alu_result);
    DM      #(64)   dm          (clk, alu_result, reg_read_data_2, mem_read_data, MemWrite, MemRead);
    MUX2_1  #(32)   mux_Mem2Reg (alu_result, mem_read_data, MemtoReg, reg_write_data);
    Adder4          adder4      (pc_out, pc_plus_4);
    LeftShift2      ls2         (sign_ext_out, imm_left_shift_2);
    Adder2_1        adder2_1    (pc_plus_4, imm_left_shift_2, branch_addr);
    MUX2_1  #(32)   mux_branch  (pc_plus_4, branch_addr, Branch, mux_branch_to_jump);
    MUX2_1  #(32)   mux_jump    (mux_branch_to_jump, jump_addr, Jump, pc_in);

endmodule
module Single_Cycle_CPU(clk);


    input clk;


    wire [31:0] pc_in,
                pc_out,
                pc_plus_4,
                inst,
                stall;


    wire        RegDst,
                Jump,
                BranchEq,
                BranchNe,
                MemRead,
                MemtoReg,
                MemWrite,
                ALUSrc,
                RegWrite;
    wire [1:0]  ALUOp;


    wire [4:0]  reg_write_addr;
    wire [31:0] reg_write_data,
                reg_read_data_1,
                reg_read_data_2;


    wire        alu_zero;
    wire [3:0]  alu_ctrl;
    wire [31:0] sign_ext_out,
                alu_in_2,
                alu_result;

    wire [31:0] mem_read_data;


    wire        Branch;
    wire [31:0] imm_left_shift_2,
                mux_branch_to_jump,
                branch_addr,
                jump_addr;

    assign stall = 1'b0;
    assign jump_addr = {pc_plus_4[31:28], inst[25:0], 2'b0};
    assign Branch = (BranchEq & alu_zero) | (BranchNe & ~alu_zero);


    PC              pc          (clk, stall, pc_in, pc_out);
    IM      #(64)   im          (pc_out, inst);
    Control         control     (inst[31:26], RegDst, Jump, BranchEq, BranchNe, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite);
    MUX2_1  #(5)    mux_RegDst  (inst[20:16], inst[15:11], RegDst, reg_write_addr);
    RegFile         reg_file    (clk, RegWrite, inst[25:21], inst[20:16], reg_write_addr, reg_write_data, reg_read_data_1, reg_read_data_2);
    SignExt         sign_ext    (inst[15:0], sign_ext_out);
    MUX2_1  #(32)   mux_ALUSrc  (reg_read_data_2, sign_ext_out, ALUSrc, alu_in_2);
    ALUCtrl         alu_control (ALUOp, inst[5:0], alu_ctrl);
    ALU             alu         (alu_ctrl, reg_read_data_1, alu_in_2, alu_zero, alu_result);
    DM      #(64)   dm          (clk, alu_result, reg_read_data_2, mem_read_data, MemWrite, MemRead);
    MUX2_1  #(32)   mux_Mem2Reg (alu_result, mem_read_data, MemtoReg, reg_write_data);
    Adder4          adder4      (pc_out, pc_plus_4);
    LeftShift2      ls2         (sign_ext_out, imm_left_shift_2);
    Adder2_1        adder2_1    (pc_plus_4, imm_left_shift_2, branch_addr);
    MUX2_1  #(32)   mux_branch  (pc_plus_4, branch_addr, Branch, mux_branch_to_jump);
    MUX2_1  #(32)   mux_jump    (mux_branch_to_jump, jump_addr, Jump, pc_in);

endmodule