data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:311: syntax error, unexpected ')', expecting '['\nmodule delay_element #(parameter REG_WIDTH = 8) (clk,a_n_1,b_n_1,a_n,b_n,);\n                                                                         ^\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:317: syntax error, unexpected output\n    output reg [REG_WIDTH-1:0] b_n;  \n    ^~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:319: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module systolic_module(clk,
	input_top_1,
	input_top_2,
	input_top_3,
	input_top_4,
	input_top_5,
	input_left_1,
	input_left_2,
	input_left_3,
	input_left_4,
	input_left_5,
	input_diag_top_0,
	input_diag_top_1,
	input_diag_top_2,
	input_diag_left_1,
	input_diag_left_2,
	output_bottom_5,
	output_bottom_4,
	output_bottom_3,
	output_right_4,
	output_right_3);
    
    input clk;
    
    parameter MATRIX_SIZE = 3;
    parameter ARRAY_SIZE = 2 * MATRIX_SIZE - 1;
    parameter REG_WIDTH = 8;
   

    wire [REG_WIDTH-1:0] array_input_top [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_input_left [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0]  c_in_left [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0]  c_in_top [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] c_out_right [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] c_out_bottom [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_output_bottom [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_output_right [ARRAY_SIZE-1:0];
    
    
    

    wire [REG_WIDTH-1:0] horizontal_wires [ARRAY_SIZE-1:0][ARRAY_SIZE-2:0];
    wire [REG_WIDTH-1:0] vertical_wires [ARRAY_SIZE-2:0][ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] diagonal_wires [ARRAY_SIZE-2:0][ARRAY_SIZE-2:0];
    

    input [REG_WIDTH-1:0] input_top_1;
    input [REG_WIDTH-1:0] input_top_2;
    input [REG_WIDTH-1:0] input_top_3;
    input [REG_WIDTH-1:0] input_top_4;
    input [REG_WIDTH-1:0] input_top_5;
    input [REG_WIDTH-1:0] input_left_1;
    input [REG_WIDTH-1:0] input_left_2;
    input [REG_WIDTH-1:0] input_left_3;
    input [REG_WIDTH-1:0] input_left_4;
    input [REG_WIDTH-1:0] input_left_5;
    input [REG_WIDTH-1:0] input_diag_top_0;
    input [REG_WIDTH-1:0] input_diag_top_1;
    input [REG_WIDTH-1:0] input_diag_top_2;
    input [REG_WIDTH-1:0] input_diag_left_1;
    input [REG_WIDTH-1:0] input_diag_left_2;
    output [REG_WIDTH-1:0] output_bottom_5;
    output [REG_WIDTH-1:0] output_bottom_4;
    output [REG_WIDTH-1:0] output_bottom_3;
    output [REG_WIDTH-1:0] output_right_4;
    output [REG_WIDTH-1:0] output_right_3;
    
    assign array_input_top[0] = input_top_1;
    assign array_input_top[1] = input_top_2;
    assign array_input_top[2] = input_top_3;
    assign array_input_top[3] = input_top_4;
    assign array_input_top[4] = input_top_5;
    assign array_input_left[0] = input_left_1; 
    assign array_input_left[1] = input_left_2;
    assign array_input_left[2] = input_left_3;
    assign array_input_left[3] = input_left_4;
    assign array_input_left[4] = input_left_5;
    assign c_in_top[0] = input_diag_top_0;
    assign c_in_top[1] = input_diag_top_1;
    assign c_in_top[2] = input_diag_top_2;
    assign c_in_left[1] = input_diag_left_1;
    assign c_in_left[2] = input_diag_left_2;
    
    assign output_bottom_5 = c_out_bottom[4];
    assign output_bottom_4 = c_out_bottom[3];
    assign output_bottom_3 = c_out_bottom[2];
    assign output_right_4 = c_out_right[3];
    assign output_right_3 = c_out_right[2];
    
    

    
    

    generate
        genvar row_index;
        genvar column_index;
        
        for(row_index = 0;row_index < ARRAY_SIZE; row_index = row_index + 1) begin
            for(column_index = 0;column_index < ARRAY_SIZE; column_index = column_index + 1) begin                 

                

            
            

                 if(row_index < MATRIX_SIZE -1) begin
                    if(column_index < MATRIX_SIZE+row_index) begin     
                        if(row_index == 0 && column_index==0)  begin
                            PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(array_input_top[column_index]),.c_n_1(c_in_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else if(column_index == 0) begin
                            PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(c_in_left[row_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else if(row_index == 0) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.c_n_1(c_in_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else begin 
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end

                    end
                    else begin
                        if(row_index == 0 && column_index==ARRAY_SIZE-1)  begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else if(column_index == ARRAY_SIZE-1) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else if(row_index == 0) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else begin 
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end                    

                    end
                end
                else if(row_index == MATRIX_SIZE-1) begin
                    if(column_index == 0) begin
                       PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(c_in_left[row_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                    end
                    else if(column_index == ARRAY_SIZE-1) begin
                       PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(c_out_right[row_index]));                    
                    end
                    else begin
                       PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));                        
                    end

                end
                else begin
                    if(column_index < MATRIX_SIZE+row_index-ARRAY_SIZE) begin
                        if((row_index == ARRAY_SIZE-1) && (column_index == 0)) begin
                            delay_element element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else if(column_index == 0) begin
                            delay_element element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else if(row_index == ARRAY_SIZE - 1) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end

                    end
                    else begin
                        if((row_index == ARRAY_SIZE-1) && (column_index == ARRAY_SIZE-1)) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(array_output_bottom[column_index]),.c_ab(c_out_bottom[column_index]));  
                        end
                        else if(column_index == ARRAY_SIZE-1) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(c_out_right[row_index]));  
                        end
                        else if(row_index == ARRAY_SIZE - 1) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]),.c_ab(c_out_bottom[column_index]));  
                        end
                        else begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));   
                        end
                        

                    end
                end           
            end
            
        end
    
    endgenerate

endmodule
module systolic_module(clk,
	input_top_1,
	input_top_2,
	input_top_3,
	input_top_4,
	input_top_5,
	input_left_1,
	input_left_2,
	input_left_3,
	input_left_4,
	input_left_5,
	input_diag_top_0,
	input_diag_top_1,
	input_diag_top_2,
	input_diag_left_1,
	input_diag_left_2,
	output_bottom_5,
	output_bottom_4,
	output_bottom_3,
	output_right_4,
	output_right_3);

    
    input clk;
    
    parameter MATRIX_SIZE = 3;
    parameter ARRAY_SIZE = 2 * MATRIX_SIZE - 1;
    parameter REG_WIDTH = 8;
   

    wire [REG_WIDTH-1:0] array_input_top [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_input_left [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0]  c_in_left [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0]  c_in_top [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] c_out_right [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] c_out_bottom [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_output_bottom [ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] array_output_right [ARRAY_SIZE-1:0];
    
    
    

    wire [REG_WIDTH-1:0] horizontal_wires [ARRAY_SIZE-1:0][ARRAY_SIZE-2:0];
    wire [REG_WIDTH-1:0] vertical_wires [ARRAY_SIZE-2:0][ARRAY_SIZE-1:0];
    wire [REG_WIDTH-1:0] diagonal_wires [ARRAY_SIZE-2:0][ARRAY_SIZE-2:0];
    

    input [REG_WIDTH-1:0] input_top_1;
    input [REG_WIDTH-1:0] input_top_2;
    input [REG_WIDTH-1:0] input_top_3;
    input [REG_WIDTH-1:0] input_top_4;
    input [REG_WIDTH-1:0] input_top_5;
    input [REG_WIDTH-1:0] input_left_1;
    input [REG_WIDTH-1:0] input_left_2;
    input [REG_WIDTH-1:0] input_left_3;
    input [REG_WIDTH-1:0] input_left_4;
    input [REG_WIDTH-1:0] input_left_5;
    input [REG_WIDTH-1:0] input_diag_top_0;
    input [REG_WIDTH-1:0] input_diag_top_1;
    input [REG_WIDTH-1:0] input_diag_top_2;
    input [REG_WIDTH-1:0] input_diag_left_1;
    input [REG_WIDTH-1:0] input_diag_left_2;
    output [REG_WIDTH-1:0] output_bottom_5;
    output [REG_WIDTH-1:0] output_bottom_4;
    output [REG_WIDTH-1:0] output_bottom_3;
    output [REG_WIDTH-1:0] output_right_4;
    output [REG_WIDTH-1:0] output_right_3;
    
    assign array_input_top[0] = input_top_1;
    assign array_input_top[1] = input_top_2;
    assign array_input_top[2] = input_top_3;
    assign array_input_top[3] = input_top_4;
    assign array_input_top[4] = input_top_5;
    assign array_input_left[0] = input_left_1; 
    assign array_input_left[1] = input_left_2;
    assign array_input_left[2] = input_left_3;
    assign array_input_left[3] = input_left_4;
    assign array_input_left[4] = input_left_5;
    assign c_in_top[0] = input_diag_top_0;
    assign c_in_top[1] = input_diag_top_1;
    assign c_in_top[2] = input_diag_top_2;
    assign c_in_left[1] = input_diag_left_1;
    assign c_in_left[2] = input_diag_left_2;
    
    assign output_bottom_5 = c_out_bottom[4];
    assign output_bottom_4 = c_out_bottom[3];
    assign output_bottom_3 = c_out_bottom[2];
    assign output_right_4 = c_out_right[3];
    assign output_right_3 = c_out_right[2];
    
    

    
    

    generate
        genvar row_index;
        genvar column_index;
        
        for(row_index = 0;row_index < ARRAY_SIZE; row_index = row_index + 1) begin
            for(column_index = 0;column_index < ARRAY_SIZE; column_index = column_index + 1) begin                 

                

            
            

                 if(row_index < MATRIX_SIZE -1) begin
                    if(column_index < MATRIX_SIZE+row_index) begin     
                        if(row_index == 0 && column_index==0)  begin
                            PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(array_input_top[column_index]),.c_n_1(c_in_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else if(column_index == 0) begin
                            PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(c_in_left[row_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else if(row_index == 0) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.c_n_1(c_in_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end
                        else begin 
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                        end

                    end
                    else begin
                        if(row_index == 0 && column_index==ARRAY_SIZE-1)  begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else if(column_index == ARRAY_SIZE-1) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else if(row_index == 0) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(array_input_top[column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end
                        else begin 
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end                    

                    end
                end
                else if(row_index == MATRIX_SIZE-1) begin
                    if(column_index == 0) begin
                       PE element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(c_in_left[row_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));
                    end
                    else if(column_index == ARRAY_SIZE-1) begin
                       PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(c_out_right[row_index]));                    
                    end
                    else begin
                       PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));                        
                    end

                end
                else begin
                    if(column_index < MATRIX_SIZE+row_index-ARRAY_SIZE) begin
                        if((row_index == ARRAY_SIZE-1) && (column_index == 0)) begin
                            delay_element element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else if(column_index == 0) begin
                            delay_element element(.clk(clk),.a_n_1(array_input_left[row_index]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else if(row_index == ARRAY_SIZE - 1) begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]));
                        end
                        else begin
                            delay_element element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]));
                        end

                    end
                    else begin
                        if((row_index == ARRAY_SIZE-1) && (column_index == ARRAY_SIZE-1)) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(array_output_bottom[column_index]),.c_ab(c_out_bottom[column_index]));  
                        end
                        else if(column_index == ARRAY_SIZE-1) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(array_output_right[row_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(c_out_right[row_index]));  
                        end
                        else if(row_index == ARRAY_SIZE - 1) begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(array_output_bottom[column_index]),.c_ab(c_out_bottom[column_index]));  
                        end
                        else begin
                            PE element(.clk(clk),.a_n_1(horizontal_wires[row_index][column_index-1]),.b_n_1(vertical_wires[row_index-1][column_index]),.c_n_1(diagonal_wires[row_index-1][column_index-1]),.a_n(horizontal_wires[row_index][column_index]),.b_n(vertical_wires[row_index][column_index]),.c_ab(diagonal_wires[row_index][column_index]));   
                        end
                        

                    end
                end           
            end
            
        end
    
    endgenerate

endmodule