data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/WREG.v
data/verilator_xmls/71d36bef-0c7c-43f4-939a-d5853ff66d25.xml
module WREG #(parameter WREG_DATA_WIDTH=16)(

WREG_Clk,
WREG_Reset,
WREG_Set,
WREG_Input_Data,

WREG_Output_Data
);




input WREG_Clk;
input WREG_Reset;
input WREG_Set;
input signed [WREG_DATA_WIDTH-1:0] WREG_Input_Data; 
output signed [WREG_DATA_WIDTH-1:0] WREG_Output_Data;





reg signed[WREG_DATA_WIDTH-1:0] Internal_Register;




always @(negedge WREG_Clk or negedge WREG_Reset)
begin	
	if(!WREG_Reset)
		Internal_Register<=0;
	else if(WREG_Set)
		Internal_Register<=WREG_Input_Data;
end





assign WREG_Output_Data=Internal_Register;

endmodule
module WREG #(parameter WREG_DATA_WIDTH=16)(

WREG_Clk,
WREG_Reset,
WREG_Set,
WREG_Input_Data,

WREG_Output_Data
);





input WREG_Clk;
input WREG_Reset;
input WREG_Set;
input signed [WREG_DATA_WIDTH-1:0] WREG_Input_Data; 
output signed [WREG_DATA_WIDTH-1:0] WREG_Output_Data;





reg signed[WREG_DATA_WIDTH-1:0] Internal_Register;




always @(negedge WREG_Clk or negedge WREG_Reset)
begin	
	if(!WREG_Reset)
		Internal_Register<=0;
	else if(WREG_Set)
		Internal_Register<=WREG_Input_Data;
end





assign WREG_Output_Data=Internal_Register;

endmodule