data/full_repos/permissive/464638001/generated/UartBlink.v
data/verilator_xmls/a285465c-e567-49e4-9ea4-f9e2f7ab9ba3.xml
module BufferedTx(
  input        clock,
  input        reset,
  output       io_txd,
  input        io_channel_valid,
  input  [7:0] io_channel_bits
);
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_ready;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  wire  buf__clock;
  wire  buf__reset;
  wire  buf__io_in_valid;
  wire [7:0] buf__io_in_bits;
  wire  buf__io_out_ready;
  wire  buf__io_out_valid;
  wire [7:0] buf__io_out_bits;
  Tx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_ready(tx_io_channel_ready),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  Buffer buf_ (
    .clock(buf__clock),
    .reset(buf__reset),
    .io_in_valid(buf__io_in_valid),
    .io_in_bits(buf__io_in_bits),
    .io_out_ready(buf__io_out_ready),
    .io_out_valid(buf__io_out_valid),
    .io_out_bits(buf__io_out_bits)
  );
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = buf__io_out_valid;
  assign tx_io_channel_bits = buf__io_out_bits;
  assign buf__clock = clock;
  assign buf__reset = reset;
  assign buf__io_in_valid = io_channel_valid;
  assign buf__io_in_bits = io_channel_bits;
  assign buf__io_out_ready = tx_io_channel_ready;
endmodule
module BufferedTx(
  input        clock,
  input        reset,
  output       io_txd,
  input        io_channel_valid,
  input  [7:0] io_channel_bits
);

  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_txd;
  wire  tx_io_channel_ready;
  wire  tx_io_channel_valid;
  wire [7:0] tx_io_channel_bits;
  wire  buf__clock;
  wire  buf__reset;
  wire  buf__io_in_valid;
  wire [7:0] buf__io_in_bits;
  wire  buf__io_out_ready;
  wire  buf__io_out_valid;
  wire [7:0] buf__io_out_bits;
  Tx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_txd(tx_io_txd),
    .io_channel_ready(tx_io_channel_ready),
    .io_channel_valid(tx_io_channel_valid),
    .io_channel_bits(tx_io_channel_bits)
  );
  Buffer buf_ (
    .clock(buf__clock),
    .reset(buf__reset),
    .io_in_valid(buf__io_in_valid),
    .io_in_bits(buf__io_in_bits),
    .io_out_ready(buf__io_out_ready),
    .io_out_valid(buf__io_out_valid),
    .io_out_bits(buf__io_out_bits)
  );
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_channel_valid = buf__io_out_valid;
  assign tx_io_channel_bits = buf__io_out_bits;
  assign buf__clock = clock;
  assign buf__reset = reset;
  assign buf__io_in_valid = io_channel_valid;
  assign buf__io_in_bits = io_channel_bits;
  assign buf__io_out_ready = tx_io_channel_ready;
endmodule