data/full_repos/permissive/461141714/src/Single Cycle CPU/ALU.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/ALU.v\n%Error: Exiting due to 4 error(s)\n'
module ALU(
    input [15:0] A,
    input [15:0] B,
    input [5:0] OP,
    output [15:0] C
    );
    
    reg [15:0] result;
    assign C = result;
    
    always @(*)
    begin
        case(OP)
        `FUNC_ADD:
            result = A + B;
        `FUNC_SUB:
            result = A - B;
        `FUNC_AND:
            result = A & B;
        `FUNC_ORR:
            result = A | B;
        `FUNC_NOT:
            result = ~A;
        `FUNC_TCP:
            result = ~A+1;
        `FUNC_SHL:
            result = {A[14:0], 1'b0};
        `FUNC_SHR:
            result = {A[15], A[15:1]};
        endcase
    end
endmodule
module ALU(
    input [15:0] A,
    input [15:0] B,
    input [5:0] OP,
    output [15:0] C
    );

    
    reg [15:0] result;
    assign C = result;
    
    always @(*)
    begin
        case(OP)
        `FUNC_ADD:
            result = A + B;
        `FUNC_SUB:
            result = A - B;
        `FUNC_AND:
            result = A & B;
        `FUNC_ORR:
            result = A | B;
        `FUNC_NOT:
            result = ~A;
        `FUNC_TCP:
            result = ~A+1;
        `FUNC_SHL:
            result = {A[14:0], 1'b0};
        `FUNC_SHR:
            result = {A[15], A[15:1]};
        endcase
    end
endmodule