data/full_repos/permissive/423539813/source_files/BasicStructure.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/423539813/source_files/BasicStructure.v:147: Cell has missing pin: \'instruction_type\'\n Control_Unit controller(.opcode(instruction[6:0]) , .func3(instruction[14:12]) , .func7(instruction[31:25]), .ZeroOut(ZeroOut), .CarryOut(CarryOut),\n              ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:136: Cannot find file containing module: \'adder\'\n adder pcplus4ins(.a(pc),.b(32\'h4),.y(PCPlus4));\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder.v\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:138: Cannot find file containing module: \'adder\'\n adder pctargetins(.a(pc),.b(immext),.y(PCTarget));\n ^~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:142: Cannot find file containing module: \'instruction_memory\'\n instruction_memory instructionmemory(.pc(pc),.instruction(instruction));\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:152: Cannot find file containing module: \'extend\'\n     extend ext(.instruction(instruction[31:7]), .immsrc(immsrc), .immext(immext));\n     ^~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:154: Cannot find file containing module: \'register_file\'\n     register_file registerfile(.Port_A(Port_A), .Port_B(Port_B),.hardwire(hardwire), .RESULT(RESULT), .Addr_A(instruction[19:15]), .Addr_B(instruction[24:20]), .Addr_Wr(instruction[11:7]), .wr(RegWrite), .clk(clk),.rst(rst));\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:156: Cannot find file containing module: \'alu\'\n     alu alu( .A(Port_A),.B(B),.ALU_Sel(ALUControl),.ALU_Out(ALU_Out),.CarryOut(CarryOut), .ZeroOut(ZeroOut));\n     ^~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:158: Cannot find file containing module: \'address_gen\'\n     address_gen AddressGenerator(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:162: Cannot find file containing module: \'Data_Memory\'\n     Data_Memory datamemory(.Data_Out(Data_Out),.Data_In(Port_B),.D_Addr(ALU_Out), .wr(MemWrite), .rst(rst),.clk(clk));\n     ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module main(rst, clk, alu_z, Anode_Activate, LED_out);
input rst, clk;
output alu_z;
output reg[7:0] Anode_Activate;
output reg [6:0] LED_out;
wire [31:0] pc;

wire [31:0] Result;


reg [31:0] counter;
reg toggle = 0;

always @(posedge clk)
    begin
            if(counter>=100000) begin
                 counter <= 0;
				 toggle = ~toggle; end
            else begin
                counter <= counter + 1;
				end
    end 


    always @(*)
    begin
        case(toggle)
        1'b0: begin
            Anode_Activate = 8'b01111111; 

              end
        1'b1: begin
            Anode_Activate = 8'b10111111; 

               end
        endcase
    end

    wire [31:0]hardwire;
    assign Result= hardwire;
    
    always @(*)
    begin
	if (toggle) begin
        case(Result)
        32'b0000: LED_out = 7'b0000001;
        32'b0001: LED_out = 7'b1001111;
        32'b0010: LED_out = 7'b0010010;
        32'b0011: LED_out = 7'b0000110;
        32'b0100: LED_out = 7'b1001100;
        32'b0101: LED_out = 7'b0100100;
        32'b0110: LED_out = 7'b0100000;
        32'b0111: LED_out = 7'b0001111;
        32'b1000: LED_out = 7'b0000000;
        32'b1001: LED_out = 7'b0000100;
		32'b1010: LED_out = 7'b0001000;
        32'b1011: LED_out = 7'b1100000;
        32'b1100: LED_out = 7'b0110001;
        32'b1101: LED_out = 7'b1000010;
        32'b1110: LED_out = 7'b0110000;
        32'b1111: LED_out = 7'b0111000;
        
        default: LED_out = 7'b0000001;
        endcase
		end
    


if(!toggle) begin	
        case(Result[7:4])
        4'b0000: LED_out = 7'b0000001;
        4'b0001: LED_out = 7'b1001111;
        4'b0010: LED_out = 7'b0010010;
        4'b0011: LED_out = 7'b0000110;
        4'b0100: LED_out = 7'b1001100;
        4'b0101: LED_out = 7'b0100100;
        4'b0110: LED_out = 7'b0100000;
        4'b0111: LED_out = 7'b0001111;
        4'b1000: LED_out = 7'b0000000;
        4'b1001: LED_out = 7'b0000100;
		4'b1010: LED_out = 7'b0001000;
        4'b1011: LED_out = 7'b1100000;
        4'b1100: LED_out = 7'b0110001;
        4'b1101: LED_out = 7'b1000010;
        4'b1110: LED_out = 7'b0110000;
        4'b1111: LED_out = 7'b0111000;
        
        default: LED_out = 7'b0000001;
        endcase
    end
end
    
    

	wire [31:0] PCNext,PCPlus4,PCTarget,immext;
	wire [6:0] opcode;
	wire [2:0] func3;
	wire [6:0] func7;
    wire PCSrc, MemWrite, ALUSrc, RegWrite, Btype,ZeroOut, CarryOut;
    wire ResultSrc;
    wire [3:0] ALUControl;
    wire [1:0]  immsrc;
    wire [31:0] Port_A, Port_B; 
    wire [31:0] Din; 
    wire [4:0] Addr_A, Addr_B, Addr_Wr; 
    wire wr, clk, rst; 
    wire [31:0] RESULT;
    wire [31:0] A,B;
    wire [3:0] ALU_Sel;
    wire [31:0] ALU_Out;
    wire [31:0] Data_Out;
    wire [31:0] Data_In;
    wire [31:0] D_Addr;
    wire [31:0] instruction;
    
	adder pcplus4ins(.a(pc),.b(32'h4),.y(PCPlus4));
	
	adder pctargetins(.a(pc),.b(immext),.y(PCTarget));
	
	mux2x1 pcmux(.sel(PCSrc),.b(PCPlus4),.a(PCTarget),.o(PCNext));
	
	instruction_memory instructionmemory(.pc(pc),.instruction(instruction));
	
	
	mux2x1 middle(.sel(ALUSrc),.b(Port_B),.a(immext),.o(B));
	
	Control_Unit controller(.opcode(instruction[6:0]) , .func3(instruction[14:12]) , .func7(instruction[31:25]), .ZeroOut(ZeroOut), .CarryOut(CarryOut),
                        .PCSrc(PCSrc), .ResultSrc(ResultSrc), .MemWrite(MemWrite), .ALUSrc(ALUSrc), .RegWrite(RegWrite),
                        .ALUControl(ALUControl),
                        .ImmSrc(immsrc));
                        
     extend ext(.instruction(instruction[31:7]), .immsrc(immsrc), .immext(immext));
     
     register_file registerfile(.Port_A(Port_A), .Port_B(Port_B),.hardwire(hardwire), .RESULT(RESULT), .Addr_A(instruction[19:15]), .Addr_B(instruction[24:20]), .Addr_Wr(instruction[11:7]), .wr(RegWrite), .clk(clk),.rst(rst));
     
     alu alu( .A(Port_A),.B(B),.ALU_Sel(ALUControl),.ALU_Out(ALU_Out),.CarryOut(CarryOut), .ZeroOut(ZeroOut));
     
     address_gen AddressGenerator(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));
     
     mux2x1 muxatend(.o(RESULT),.b(ALU_Out),.a(Data_Out),.sel(ResultSrc));

     Data_Memory datamemory(.Data_Out(Data_Out),.Data_In(Port_B),.D_Addr(ALU_Out), .wr(MemWrite), .rst(rst),.clk(clk));
     
endmodule
module main(rst, clk, alu_z, Anode_Activate, LED_out);

input rst, clk;
output alu_z;
output reg[7:0] Anode_Activate;
output reg [6:0] LED_out;
wire [31:0] pc;

wire [31:0] Result;


reg [31:0] counter;
reg toggle = 0;

always @(posedge clk)
    begin
            if(counter>=100000) begin
                 counter <= 0;
				 toggle = ~toggle; end
            else begin
                counter <= counter + 1;
				end
    end 


    always @(*)
    begin
        case(toggle)
        1'b0: begin
            Anode_Activate = 8'b01111111; 

              end
        1'b1: begin
            Anode_Activate = 8'b10111111; 

               end
        endcase
    end

    wire [31:0]hardwire;
    assign Result= hardwire;
    
    always @(*)
    begin
	if (toggle) begin
        case(Result)
        32'b0000: LED_out = 7'b0000001;
        32'b0001: LED_out = 7'b1001111;
        32'b0010: LED_out = 7'b0010010;
        32'b0011: LED_out = 7'b0000110;
        32'b0100: LED_out = 7'b1001100;
        32'b0101: LED_out = 7'b0100100;
        32'b0110: LED_out = 7'b0100000;
        32'b0111: LED_out = 7'b0001111;
        32'b1000: LED_out = 7'b0000000;
        32'b1001: LED_out = 7'b0000100;
		32'b1010: LED_out = 7'b0001000;
        32'b1011: LED_out = 7'b1100000;
        32'b1100: LED_out = 7'b0110001;
        32'b1101: LED_out = 7'b1000010;
        32'b1110: LED_out = 7'b0110000;
        32'b1111: LED_out = 7'b0111000;
        
        default: LED_out = 7'b0000001;
        endcase
		end
    


if(!toggle) begin	
        case(Result[7:4])
        4'b0000: LED_out = 7'b0000001;
        4'b0001: LED_out = 7'b1001111;
        4'b0010: LED_out = 7'b0010010;
        4'b0011: LED_out = 7'b0000110;
        4'b0100: LED_out = 7'b1001100;
        4'b0101: LED_out = 7'b0100100;
        4'b0110: LED_out = 7'b0100000;
        4'b0111: LED_out = 7'b0001111;
        4'b1000: LED_out = 7'b0000000;
        4'b1001: LED_out = 7'b0000100;
		4'b1010: LED_out = 7'b0001000;
        4'b1011: LED_out = 7'b1100000;
        4'b1100: LED_out = 7'b0110001;
        4'b1101: LED_out = 7'b1000010;
        4'b1110: LED_out = 7'b0110000;
        4'b1111: LED_out = 7'b0111000;
        
        default: LED_out = 7'b0000001;
        endcase
    end
end
    
    

	wire [31:0] PCNext,PCPlus4,PCTarget,immext;
	wire [6:0] opcode;
	wire [2:0] func3;
	wire [6:0] func7;
    wire PCSrc, MemWrite, ALUSrc, RegWrite, Btype,ZeroOut, CarryOut;
    wire ResultSrc;
    wire [3:0] ALUControl;
    wire [1:0]  immsrc;
    wire [31:0] Port_A, Port_B; 
    wire [31:0] Din; 
    wire [4:0] Addr_A, Addr_B, Addr_Wr; 
    wire wr, clk, rst; 
    wire [31:0] RESULT;
    wire [31:0] A,B;
    wire [3:0] ALU_Sel;
    wire [31:0] ALU_Out;
    wire [31:0] Data_Out;
    wire [31:0] Data_In;
    wire [31:0] D_Addr;
    wire [31:0] instruction;
    
	adder pcplus4ins(.a(pc),.b(32'h4),.y(PCPlus4));
	
	adder pctargetins(.a(pc),.b(immext),.y(PCTarget));
	
	mux2x1 pcmux(.sel(PCSrc),.b(PCPlus4),.a(PCTarget),.o(PCNext));
	
	instruction_memory instructionmemory(.pc(pc),.instruction(instruction));
	
	
	mux2x1 middle(.sel(ALUSrc),.b(Port_B),.a(immext),.o(B));
	
	Control_Unit controller(.opcode(instruction[6:0]) , .func3(instruction[14:12]) , .func7(instruction[31:25]), .ZeroOut(ZeroOut), .CarryOut(CarryOut),
                        .PCSrc(PCSrc), .ResultSrc(ResultSrc), .MemWrite(MemWrite), .ALUSrc(ALUSrc), .RegWrite(RegWrite),
                        .ALUControl(ALUControl),
                        .ImmSrc(immsrc));
                        
     extend ext(.instruction(instruction[31:7]), .immsrc(immsrc), .immext(immext));
     
     register_file registerfile(.Port_A(Port_A), .Port_B(Port_B),.hardwire(hardwire), .RESULT(RESULT), .Addr_A(instruction[19:15]), .Addr_B(instruction[24:20]), .Addr_Wr(instruction[11:7]), .wr(RegWrite), .clk(clk),.rst(rst));
     
     alu alu( .A(Port_A),.B(B),.ALU_Sel(ALUControl),.ALU_Out(ALU_Out),.CarryOut(CarryOut), .ZeroOut(ZeroOut));
     
     address_gen AddressGenerator(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));
     
     mux2x1 muxatend(.o(RESULT),.b(ALU_Out),.a(Data_Out),.sel(ResultSrc));

     Data_Memory datamemory(.Data_Out(Data_Out),.Data_In(Port_B),.D_Addr(ALU_Out), .wr(MemWrite), .rst(rst),.clk(clk));
     
endmodule