data/full_repos/permissive/456528918/RTL/intc.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:99: Unsupported: Ignoring delay on this delayed statement.\n   INTC_A: #0.1 INTC[7:0] <= din[7:0];\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:100: Unsupported: Ignoring delay on this delayed statement.\n   INT0_A: #0.1 INT0 <= din;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:101: Unsupported: Ignoring delay on this delayed statement.\n   INT1_A: #0.1 INT1 <= din;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:106: Unsupported: Ignoring delay on this delayed statement.\n   INTC_A: #0.1 dout <= INTC;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:107: Unsupported: Ignoring delay on this delayed statement.\n   INT0_A: #0.1 dout <= INT0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/intc.v:108: Unsupported: Ignoring delay on this delayed statement.\n   INT1_A: #0.1 dout <= INT1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:74: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                  : ... In instance intc\nwire [31:0]INTA={INT1,INT0};\n               ^\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:93: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                  : ... In instance intc\n INT1 <= 16\'h0;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:101: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                   : ... In instance intc\n   INT1_A: #0.1 INT1 <= din;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:98: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INTC_A\' generates 12 bits.\n                                                                  : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:98: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INT0_A\' generates 12 bits.\n                                                                  : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:98: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INT1_A\' generates 12 bits.\n                                                                  : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:106: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'INTC\' generates 11 bits.\n                                                                   : ... In instance intc\n   INTC_A: #0.1 dout <= INTC;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:108: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'INT1\' generates 17 bits.\n                                                                   : ... In instance intc\n   INT1_A: #0.1 dout <= INT1;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:105: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INTC_A\' generates 12 bits.\n                                                                   : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:105: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INT0_A\' generates 12 bits.\n                                                                   : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:105: Operator CASE expects 13 bits on the Case Item, but Case Item\'s VARREF \'INT1_A\' generates 12 bits.\n                                                                   : ... In instance intc\n  case (addr) \n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:125: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                   : ... In instance intc\n intp_i_r <= 16\'h0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/456528918/RTL/intc.v:126: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                   : ... In instance intc\n intp_i_rr <= 16\'h0;\n           ^~\n%Error: Exiting due to 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module intc
#(
	parameter DW = 16,
	parameter AW = 13 
)(
	input			clk,
	input			 rst,
	input [DW-1:0]	din,
	input [AW-1:0]	addr,
	input			we,
	output reg[DW-1:0] dout,
	input wire[7:0]intp_i,
	input wire int_rdy,
	output reg int_vld
);

localparam INTC_A=12'h0;
localparam INT0_A=12'h1;
localparam INT1_A=12'h2;

reg [10:0]INTC;


reg [15:0]INT0;

reg [16:0]INT1;


wire [31:0]INTA={INT1,INT0};


reg [7:0]intp_i_r;
reg [7:0]intp_i_rr;
reg [7:0]intp_c;
reg [7:0]intp_tg;
reg [7:0]intp_h;
reg intp_ht;
reg [2:0]intp_hn;
reg [7:0]intp_l;
reg intp_lt;
reg [2:0]intp_ln;


always @(posedge clk) begin
if(rst) begin
	INTC[7:0] <= 8'h0;
	INT0 <= 16'h0;
	INT1 <= 16'h0;
	dout <= 16'h0;
	end	
else begin
	if(we)
		case (addr)
			INTC_A: #0.1 INTC[7:0] <= din[7:0];
			INT0_A: #0.1 INT0 <= din;
			INT1_A: #0.1 INT1 <= din;
			default: ;
		endcase
	else begin
		case (addr)
			INTC_A: #0.1 dout <= INTC;
			INT0_A: #0.1 dout <= INT0;
			INT1_A: #0.1 dout <= INT1;
			default: dout <= 16'h0;
		endcase
		end
	end
end


integer j;
always @(*) begin
	for(j=0;j<=7;j=j+1)
		intp_c[j]=INTA[4*j]?intp_i[j]:1'b0;
end


always @(posedge clk) begin
if(rst) begin
	intp_i_r <= 16'h0;
	intp_i_rr <= 16'h0;
	end	
else begin
	intp_i_r <= intp_c;
	intp_i_rr <= intp_i_r;
	end
end


always @(*) begin
	for(j=0;j<=7;j=j+1) begin
		case ({INTA[4*j+3],INTA[4*j+2]})
			2'b00: intp_tg[j]=intp_i_r[j];
			2'b01: intp_tg[j]=~intp_i_r[j];
			2'b10: intp_tg[j]=(intp_i_r[j] && ~intp_i_rr[j])?1'b1:1'b0;
			2'b11: intp_tg[j]=(~intp_i_r[j] && intp_i_rr[j])?1'b1:1'b0;
		endcase
		end
end


always @(*) begin
	for(j=0;j<=7;j=j+1) begin
		if(INTA[4*j+1]) begin
			intp_h[j]=1'b0;
			intp_l[j]=intp_tg[j];
			end
		else begin
			intp_h[j]=intp_tg[j];
			intp_l[j]=1'b0;
			end
		end
end



always @(*) begin
	if(intp_h[0]) begin
		intp_ht=1'b1;
		intp_hn=3'h0;
		end
	else if(intp_h[1]) begin
		intp_ht=1'b1;
		intp_hn=3'h1;
		end
	else if(intp_h[2]) begin
		intp_ht=1'b1;
		intp_hn=3'h2;
		end
	else if(intp_h[3]) begin
		intp_ht=1'b1;
		intp_hn=3'h3;
		end
	else if(intp_h[4]) begin
		intp_ht=1'b1;
		intp_hn=3'h4;
		end
	else if(intp_h[5]) begin
		intp_ht=1'b1;
		intp_hn=3'h5;
		end
	else if(intp_h[6]) begin
		intp_ht=1'b1;
		intp_hn=3'h6;
		end
	else if(intp_h[7]) begin
		intp_ht=1'b1;
		intp_hn=3'h7;
		end
	else begin
		intp_ht=1'b0;
		intp_hn=3'h0;
		end
end

always @(*) begin
	if(intp_l[0]) begin
		intp_lt=1'b1;
		intp_ln=3'h0;
		end
	else if(intp_h[1]) begin
		intp_lt=1'b1;
		intp_ln=3'h1;
		end
	else if(intp_h[2]) begin
		intp_lt=1'b1;
		intp_ln=3'h2;
		end
	else if(intp_h[3]) begin
		intp_lt=1'b1;
		intp_ln=3'h3;
		end
	else if(intp_h[4]) begin
		intp_lt=1'b1;
		intp_ln=3'h4;
		end
	else if(intp_h[5]) begin
		intp_lt=1'b1;
		intp_ln=3'h5;
		end
	else if(intp_h[6]) begin
		intp_lt=1'b1;
		intp_ln=3'h6;
		end
	else if(intp_h[7]) begin
		intp_lt=1'b1;
		intp_ln=3'h7;
		end
	else begin
		intp_lt=1'b0;
		intp_ln=3'h0;
		end
end


always @(posedge clk) begin
	if(rst) begin
		int_vld <= 1'b0;
		INTC[10:8] <= 3'h0;
		end 
	else begin
		if(INTC[0]) begin
			if(intp_ht) begin
				int_vld <= 1'b1;
				INTC[10:8] <= intp_hn;
				end
			else if(intp_lt) begin
				int_vld <= 1'b1;
				INTC[10:8] <= intp_ln;
				end
			else begin
				int_vld <= 1'b0;
				INTC[10:8] <= 3'h0;
				end
			end
		else begin
			int_vld <= 1'b0;
			INTC[10:8] <= 3'h0;
			end
		end
end

endmodule
module intc
#(
	parameter DW = 16,
	parameter AW = 13 
)(
	input			clk,
	input			 rst,
	input [DW-1:0]	din,
	input [AW-1:0]	addr,
	input			we,
	output reg[DW-1:0] dout,
	input wire[7:0]intp_i,
	input wire int_rdy,
	output reg int_vld
);


localparam INTC_A=12'h0;
localparam INT0_A=12'h1;
localparam INT1_A=12'h2;

reg [10:0]INTC;


reg [15:0]INT0;

reg [16:0]INT1;


wire [31:0]INTA={INT1,INT0};


reg [7:0]intp_i_r;
reg [7:0]intp_i_rr;
reg [7:0]intp_c;
reg [7:0]intp_tg;
reg [7:0]intp_h;
reg intp_ht;
reg [2:0]intp_hn;
reg [7:0]intp_l;
reg intp_lt;
reg [2:0]intp_ln;


always @(posedge clk) begin
if(rst) begin
	INTC[7:0] <= 8'h0;
	INT0 <= 16'h0;
	INT1 <= 16'h0;
	dout <= 16'h0;
	end	
else begin
	if(we)
		case (addr)
			INTC_A: #0.1 INTC[7:0] <= din[7:0];
			INT0_A: #0.1 INT0 <= din;
			INT1_A: #0.1 INT1 <= din;
			default: ;
		endcase
	else begin
		case (addr)
			INTC_A: #0.1 dout <= INTC;
			INT0_A: #0.1 dout <= INT0;
			INT1_A: #0.1 dout <= INT1;
			default: dout <= 16'h0;
		endcase
		end
	end
end


integer j;
always @(*) begin
	for(j=0;j<=7;j=j+1)
		intp_c[j]=INTA[4*j]?intp_i[j]:1'b0;
end


always @(posedge clk) begin
if(rst) begin
	intp_i_r <= 16'h0;
	intp_i_rr <= 16'h0;
	end	
else begin
	intp_i_r <= intp_c;
	intp_i_rr <= intp_i_r;
	end
end


always @(*) begin
	for(j=0;j<=7;j=j+1) begin
		case ({INTA[4*j+3],INTA[4*j+2]})
			2'b00: intp_tg[j]=intp_i_r[j];
			2'b01: intp_tg[j]=~intp_i_r[j];
			2'b10: intp_tg[j]=(intp_i_r[j] && ~intp_i_rr[j])?1'b1:1'b0;
			2'b11: intp_tg[j]=(~intp_i_r[j] && intp_i_rr[j])?1'b1:1'b0;
		endcase
		end
end


always @(*) begin
	for(j=0;j<=7;j=j+1) begin
		if(INTA[4*j+1]) begin
			intp_h[j]=1'b0;
			intp_l[j]=intp_tg[j];
			end
		else begin
			intp_h[j]=intp_tg[j];
			intp_l[j]=1'b0;
			end
		end
end



always @(*) begin
	if(intp_h[0]) begin
		intp_ht=1'b1;
		intp_hn=3'h0;
		end
	else if(intp_h[1]) begin
		intp_ht=1'b1;
		intp_hn=3'h1;
		end
	else if(intp_h[2]) begin
		intp_ht=1'b1;
		intp_hn=3'h2;
		end
	else if(intp_h[3]) begin
		intp_ht=1'b1;
		intp_hn=3'h3;
		end
	else if(intp_h[4]) begin
		intp_ht=1'b1;
		intp_hn=3'h4;
		end
	else if(intp_h[5]) begin
		intp_ht=1'b1;
		intp_hn=3'h5;
		end
	else if(intp_h[6]) begin
		intp_ht=1'b1;
		intp_hn=3'h6;
		end
	else if(intp_h[7]) begin
		intp_ht=1'b1;
		intp_hn=3'h7;
		end
	else begin
		intp_ht=1'b0;
		intp_hn=3'h0;
		end
end

always @(*) begin
	if(intp_l[0]) begin
		intp_lt=1'b1;
		intp_ln=3'h0;
		end
	else if(intp_h[1]) begin
		intp_lt=1'b1;
		intp_ln=3'h1;
		end
	else if(intp_h[2]) begin
		intp_lt=1'b1;
		intp_ln=3'h2;
		end
	else if(intp_h[3]) begin
		intp_lt=1'b1;
		intp_ln=3'h3;
		end
	else if(intp_h[4]) begin
		intp_lt=1'b1;
		intp_ln=3'h4;
		end
	else if(intp_h[5]) begin
		intp_lt=1'b1;
		intp_ln=3'h5;
		end
	else if(intp_h[6]) begin
		intp_lt=1'b1;
		intp_ln=3'h6;
		end
	else if(intp_h[7]) begin
		intp_lt=1'b1;
		intp_ln=3'h7;
		end
	else begin
		intp_lt=1'b0;
		intp_ln=3'h0;
		end
end


always @(posedge clk) begin
	if(rst) begin
		int_vld <= 1'b0;
		INTC[10:8] <= 3'h0;
		end 
	else begin
		if(INTC[0]) begin
			if(intp_ht) begin
				int_vld <= 1'b1;
				INTC[10:8] <= intp_hn;
				end
			else if(intp_lt) begin
				int_vld <= 1'b1;
				INTC[10:8] <= intp_ln;
				end
			else begin
				int_vld <= 1'b0;
				INTC[10:8] <= 3'h0;
				end
			end
		else begin
			int_vld <= 1'b0;
			INTC[10:8] <= 3'h0;
			end
		end
end

endmodule