data/full_repos/permissive/476412093/Top.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:45: Little bit endian vector: MSB < LSB of bit range: 0:127\n            input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:46: Little bit endian vector: MSB < LSB of bit range: 0:127\n   input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:47: Little bit endian vector: MSB < LSB of bit range: 0:127\n   input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:48: Little bit endian vector: MSB < LSB of bit range: 0:127\n   input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:58: Little bit endian vector: MSB < LSB of bit range: 0:127\n   output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:59: Little bit endian vector: MSB < LSB of bit range: 0:127\n   output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:60: Little bit endian vector: MSB < LSB of bit range: 0:127\n   output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:61: Little bit endian vector: MSB < LSB of bit range: 0:127\n   output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:86: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] WOUT;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:87: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] EOUT;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:88: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] SOUT;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:89: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] NOUT;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:90: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] WIN;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:91: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] EIN;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:92: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] SIN;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Top.v:93: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire[0:ARRAY_DIM*TILE_DIM*8-1] NIN;\n    ^\n%Error: data/full_repos/permissive/476412093/Top.v:114: Cannot find file containing module: \'Controller\'\nController #(MAX_WORD_LENGTH) FSM\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller.v\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller.sv\n             Controller\n             Controller.v\n             Controller.sv\n             obj_dir/Controller\n             obj_dir/Controller.v\n             obj_dir/Controller.sv\n%Error: data/full_repos/permissive/476412093/Top.v:151: Cannot find file containing module: \'PSC_Tile_Array\'\nPSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) WEST_IO\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476412093/Top.v:165: Cannot find file containing module: \'PSC_Tile_Array\'\nPSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) EAST_IO\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476412093/Top.v:179: Cannot find file containing module: \'PSC_Tile_Array\'\nPSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) NORTH_IO\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476412093/Top.v:193: Cannot find file containing module: \'PSC_Tile_Array\'\nPSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) SOUTH_IO\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476412093/Top.v:210: Cannot find file containing module: \'Tile\'\n  Tile #(TILE_DIM) tile(\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/476412093/Top.v:352: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Top\nassign DOA = wDOA[Tile_i][Tile_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Top.v:352: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Top\nassign DOA = wDOA[Tile_i][Tile_j];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Top.v:353: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Top\nassign DOB = wDOB[Tile_i][Tile_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Top.v:353: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Top\nassign DOB = wDOB[Tile_i][Tile_j];\n                         ^\n%Error: Exiting due to 6 error(s), 20 warning(s)\n'
module Top #(parameter[7:0] ARRAY_DIM = 8'h01, parameter[7:0] TILE_DIM = 8'h01, parameter MAX_WORD_LENGTH = 32)
		(
			input clk,
			input reset,
			input start,
			input[31:0] instruction,
			input external,
			input[7:0] Tile_i,
			input[7:0] Tile_j,
			input[7:0] Block_i,
			input[7:0] Block_j,
			input WEA,
            input WEB,
			input[9:0] ADDRA,
            input[9:0] ADDRB,
            input[15:0] DIA,
			input[15:0] DIB,
			output[15:0] DOA,
            output[15:0] DOB,
            input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I,








			
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O








			
		);
	







wire[(TILE_DIM*8)-1:0] EtoW_WtoE[ARRAY_DIM-1:0][ARRAY_DIM-1:0][3:0];
wire[(TILE_DIM*8)-1:0] NtoS_StoN[ARRAY_DIM-1:0][ARRAY_DIM-1:0][3:0];

wire[15:0] wDOA[ARRAY_DIM-1:0][ARRAY_DIM-1:0];
wire[15:0] wDOB[ARRAY_DIM-1:0][ARRAY_DIM-1:0];

wire[0:ARRAY_DIM*TILE_DIM*8-1] WOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] EOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] SOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] NOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] WIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] EIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] SIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] NIN;

wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;
wire[4:0] num_shift;

wire[3:0] alu_op;

wire[7:0] count;
wire[2:0] state;
wire finish_W, finish_E, finish_N, finish_S;

generate

genvar gi;
genvar gj;

Controller #(MAX_WORD_LENGTH) FSM
		(
        clk, 
        reset,
        start,

		instruction,
		

        alu_op,


        wea,
		web,
		addra, 
		addrb,


		east, 
		west, 
		south, 
		north,
		east_mode,
		west_mode,
		south_mode,
		north_mode,
		num_shift,
		

		count,



		state
			
		);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) WEST_IO

(
	clk,  
	reset, 
    west_mode,
    start,
    finish_W,
    WOUT,
    WEST_I,
    WIN,
    WEST_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) EAST_IO

(
	clk,  
	reset, 
    east_mode,
    start,
    finish_E,
    EOUT,
    EAST_I,
    EIN,
    EAST_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) NORTH_IO

(
	clk,  
	reset, 
    north_mode,
    start,
    finish_N,
    NOUT,
    NORTH_I,
    NIN,
    NORTH_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) SOUTH_IO

(
	clk,  
	reset, 
    south_mode,
    start,
    finish_S,
    SOUT,
    SOUTH_I,
    SIN,
    SOUTH_O
);

for (gi=0; gi<ARRAY_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<ARRAY_DIM; gj=gj+1) begin : COL

		Tile #(TILE_DIM) tile(
				clk, 
				reset,
				start,
				instruction,
				external,
				Block_i,
				Block_j,
				(gi==Tile_i && gj==Tile_j? (external? WEA : wea) : wea),
				(gi==Tile_i && gj==Tile_j? (external? WEB : web) : web),
				(gi==Tile_i && gj==Tile_j? (external? ADDRA : addra) : addra),
				(gi==Tile_i && gj==Tile_j? (external? ADDRB : addrb) : addrb),
				gi==Tile_i && gj==Tile_j? DIA : 16'hzzzz,
				gi==Tile_i && gj==Tile_j? DIB : 16'hzzzz,
				wDOA[gi][gj],
            	wDOB[gi][gj],




				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][1]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][3]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][2]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][2]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][0]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][1]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][3]:8'bz
				:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][2]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][2]:8'bz
				:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][0]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][2]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj][0]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][3]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][3]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][0]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][1]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][2]:
								  (south)?NtoS_StoN[gi][gj][0]:8'bz
				:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][3]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][3]:8'bz
				:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][1]:
								  (south)?(gi==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][1]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][3]:
								  (east)?EtoW_WtoE[gi][gj][1]:8'bz
				:(num_shift == 2)?(west)?(gj==TILE_DIM-1)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][0]:
								  (east)?EtoW_WtoE[gi][gj][0]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][2]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][2]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][3]:
								  (south)?NtoS_StoN[gi][gj][1]:8'bz
				:(num_shift == 2)?(north)?(gi==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][0]:							  
								  (south)?NtoS_StoN[gi][gj][0]:8'bz
				:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][2]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?(gj==TILE_DIM-1)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][0]:
								  (east)?EtoW_WtoE[gi][gj][2]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][1]:
								  (east)?(gj==TILE_DIM-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][1]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][3]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


				(num_shift == 1)? (north)?(gj==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][0]:
								  (south)?NtoS_StoN[gi][gj][2]:8'bz
				:(num_shift == 2)?(north)?(gj==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][1]:
								  (south)?NtoS_StoN[gi][gj][1]:8'bz
				:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][3]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][3]:8'bz:8'bz,

				




				EtoW_WtoE[gi][gj][0],
				NtoS_StoN[gi][gj][0],
				
				EtoW_WtoE[gi][gj][1],
				NtoS_StoN[gi][gj][1],
				
				EtoW_WtoE[gi][gj][2],
				NtoS_StoN[gi][gj][2],
				
				EtoW_WtoE[gi][gj][3],
				NtoS_StoN[gi][gj][3]
								
		);




		
		assign EOUT[8*TILE_DIM*gi+:8*TILE_DIM] = EtoW_WtoE[gi][ARRAY_DIM-1][3];
		assign WOUT[8*TILE_DIM*gi+:8*TILE_DIM] = EtoW_WtoE[gi][0][0];
		assign SOUT[8*TILE_DIM*gj+:8*TILE_DIM] = NtoS_StoN[ARRAY_DIM-1][gj][3];
		assign NOUT[8*TILE_DIM*gj+:8*TILE_DIM] = NtoS_StoN[0][gj][0];
		








		

	end
  end
  

  
endgenerate

assign DOA = wDOA[Tile_i][Tile_j];
assign DOB = wDOB[Tile_i][Tile_j];


endmodule
module Top #(parameter[7:0] ARRAY_DIM = 8'h01, parameter[7:0] TILE_DIM = 8'h01, parameter MAX_WORD_LENGTH = 32)
		(
			input clk,
			input reset,
			input start,
			input[31:0] instruction,
			input external,
			input[7:0] Tile_i,
			input[7:0] Tile_j,
			input[7:0] Block_i,
			input[7:0] Block_j,
			input WEA,
            input WEB,
			input[9:0] ADDRA,
            input[9:0] ADDRB,
            input[15:0] DIA,
			input[15:0] DIB,
			output[15:0] DOA,
            output[15:0] DOB,
            input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I,
			input[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I,








			
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O,
			output[0:4*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O








			
		);

	







wire[(TILE_DIM*8)-1:0] EtoW_WtoE[ARRAY_DIM-1:0][ARRAY_DIM-1:0][3:0];
wire[(TILE_DIM*8)-1:0] NtoS_StoN[ARRAY_DIM-1:0][ARRAY_DIM-1:0][3:0];

wire[15:0] wDOA[ARRAY_DIM-1:0][ARRAY_DIM-1:0];
wire[15:0] wDOB[ARRAY_DIM-1:0][ARRAY_DIM-1:0];

wire[0:ARRAY_DIM*TILE_DIM*8-1] WOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] EOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] SOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] NOUT;
wire[0:ARRAY_DIM*TILE_DIM*8-1] WIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] EIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] SIN;
wire[0:ARRAY_DIM*TILE_DIM*8-1] NIN;

wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;
wire[4:0] num_shift;

wire[3:0] alu_op;

wire[7:0] count;
wire[2:0] state;
wire finish_W, finish_E, finish_N, finish_S;

generate

genvar gi;
genvar gj;

Controller #(MAX_WORD_LENGTH) FSM
		(
        clk, 
        reset,
        start,

		instruction,
		

        alu_op,


        wea,
		web,
		addra, 
		addrb,


		east, 
		west, 
		south, 
		north,
		east_mode,
		west_mode,
		south_mode,
		north_mode,
		num_shift,
		

		count,



		state
			
		);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) WEST_IO

(
	clk,  
	reset, 
    west_mode,
    start,
    finish_W,
    WOUT,
    WEST_I,
    WIN,
    WEST_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) EAST_IO

(
	clk,  
	reset, 
    east_mode,
    start,
    finish_E,
    EOUT,
    EAST_I,
    EIN,
    EAST_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) NORTH_IO

(
	clk,  
	reset, 
    north_mode,
    start,
    finish_N,
    NOUT,
    NORTH_I,
    NIN,
    NORTH_O
);

PSC_Tile_Array #(MAX_WORD_LENGTH, ARRAY_DIM, TILE_DIM) SOUTH_IO

(
	clk,  
	reset, 
    south_mode,
    start,
    finish_S,
    SOUT,
    SOUTH_I,
    SIN,
    SOUTH_O
);

for (gi=0; gi<ARRAY_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<ARRAY_DIM; gj=gj+1) begin : COL

		Tile #(TILE_DIM) tile(
				clk, 
				reset,
				start,
				instruction,
				external,
				Block_i,
				Block_j,
				(gi==Tile_i && gj==Tile_j? (external? WEA : wea) : wea),
				(gi==Tile_i && gj==Tile_j? (external? WEB : web) : web),
				(gi==Tile_i && gj==Tile_j? (external? ADDRA : addra) : addra),
				(gi==Tile_i && gj==Tile_j? (external? ADDRB : addrb) : addrb),
				gi==Tile_i && gj==Tile_j? DIA : 16'hzzzz,
				gi==Tile_i && gj==Tile_j? DIB : 16'hzzzz,
				wDOA[gi][gj],
            	wDOB[gi][gj],




				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][1]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][3]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][2]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][2]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][0]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][1]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][3]:8'bz
				:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][2]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][2]:8'bz
				:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][0]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][2]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj][0]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][3]:
								  (east)?(gj==0)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-1][3]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][0]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][1]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][2]:
								  (south)?NtoS_StoN[gi][gj][0]:8'bz
				:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][3]:
								  (south)?(gi==0)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-1][gj][3]:8'bz
				:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][1]:
								  (south)?(gi==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][1]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][3]:
								  (east)?EtoW_WtoE[gi][gj][1]:8'bz
				:(num_shift == 2)?(west)?(gj==TILE_DIM-1)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][0]:
								  (east)?EtoW_WtoE[gi][gj][0]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][2]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][2]:8'bz:8'bz,


				(num_shift == 1)? (north)?NtoS_StoN[gi][gj][3]:
								  (south)?NtoS_StoN[gi][gj][1]:8'bz
				:(num_shift == 2)?(north)?(gi==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][0]:							  
								  (south)?NtoS_StoN[gi][gj][0]:8'bz
				:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][2]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
										 
				
				(num_shift == 1)? (west)?(gj==TILE_DIM-1)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][0]:
								  (east)?EtoW_WtoE[gi][gj][2]:8'bz
				:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][1]:
								  (east)?(gj==TILE_DIM-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+1][1]:8'bz
				:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?EIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj+num_shift/4][3]:
								  (east)?(gj==num_shift/4-1)?WIN[8*TILE_DIM*gi+:8*TILE_DIM]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


				(num_shift == 1)? (north)?(gj==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][0]:
								  (south)?NtoS_StoN[gi][gj][2]:8'bz
				:(num_shift == 2)?(north)?(gj==TILE_DIM-1)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+1][gj][1]:
								  (south)?NtoS_StoN[gi][gj][1]:8'bz
				:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?SIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi+num_shift/4][gj][3]:
								  (south)?(gj==num_shift/4-1)?NIN[8*TILE_DIM*gj+:8*TILE_DIM]:NtoS_StoN[gi-num_shift/4][gj][3]:8'bz:8'bz,

				




				EtoW_WtoE[gi][gj][0],
				NtoS_StoN[gi][gj][0],
				
				EtoW_WtoE[gi][gj][1],
				NtoS_StoN[gi][gj][1],
				
				EtoW_WtoE[gi][gj][2],
				NtoS_StoN[gi][gj][2],
				
				EtoW_WtoE[gi][gj][3],
				NtoS_StoN[gi][gj][3]
								
		);




		
		assign EOUT[8*TILE_DIM*gi+:8*TILE_DIM] = EtoW_WtoE[gi][ARRAY_DIM-1][3];
		assign WOUT[8*TILE_DIM*gi+:8*TILE_DIM] = EtoW_WtoE[gi][0][0];
		assign SOUT[8*TILE_DIM*gj+:8*TILE_DIM] = NtoS_StoN[ARRAY_DIM-1][gj][3];
		assign NOUT[8*TILE_DIM*gj+:8*TILE_DIM] = NtoS_StoN[0][gj][0];
		








		

	end
  end
  

  
endgenerate

assign DOA = wDOA[Tile_i][Tile_j];
assign DOB = wDOB[Tile_i][Tile_j];


endmodule