data/full_repos/permissive/502764644/z8420/z8420.v
1: b"%Error: data/full_repos/permissive/502764644/z8420/z8420.v:225: syntax error, unexpected ':'\ngenerate : INTSEL\n         ^\n%Error: Cannot continue\n"
module z8420
(

    input        RST_n,


    input        CLK,
    input        ENA,
    input        BASEL,
    input        CDSEL,
    input        CE,
    input        RD_n,
    input        WR_n,
    input        IORQ_n,
    input        M1_n,
    input  [7:0] DI,
    output [7:0] DO,
    input        IEI,
    output       IEO,

    output       INT_n,
    

    output [7:0] A,
    input  [7:0] B
);


wire SELAD;
wire SELBD;
wire SELAC;
wire SELBC;


reg  [7:0] AREG;
reg  [7:0] DIRA;
wire       DDWA;
reg  [7:0] IMWA;
wire       MFA;
reg  [7:0] VECTA;
reg  [1:0] MODEA;
wire       HLA;
wire       AOA;
reg  [7:0] DIRB;
wire       DDWB;
reg  [7:0] IMWB;
wire       MFB;
reg  [7:0] VECTB;
reg  [1:0] MODEB;
wire       HLB;
wire       AOB;



wire       EIA;


wire       VECTENB;
wire       EIB;
reg  [7:0] MINTB;
wire       INTB;






















INT1 Interrupt
(

    .RESET(RST_n),


    .DI(DI),
    .IORQ_n(IORQ_n),
    .RD_n(RD_n),
    .M1_n(M1_n),
    .IEI(IEI),
    .IEO(IEO),
    .INTO_n(INT_n),


    .VECTEN(VECTENB),
    .INTI(INTB),
    .INTEN(EIB)
);


always @* begin : portSelect
    SELAD <= 0;
    SELBD <= 0;
    SELAC <= 0;
    SELBC <= 0;
    if (~BASEL && ~CDSEL) begin
        SELAD <= 1;
    end
    if (BASEL && ~CDSEL) begin
        SELBD <= 1;
    end
    if (~BASEL && CDSEL) begin
        SELAC <= 1;
    end
    if (BASEL && CDSEL) begin
        SELBC <= 1;
    end
end


always @(posedge CLK or posedge RST_n or posedge ENA) begin
    if (~RST_n) begin
        AREG  <= {8{8'b0}};
        MODEA <= 2'b01;
        DDWA  <= 0;
        MFA   <= 0;
        EIA   <= 0;

        MODEB <= 2'b01;
        DDWB  <= 0;
        MFB   <= 0;
        EIB   <= 0;
    end else if (~CLK) begin
        if (ENA) begin
            if (~CE && ~WR_n) begin
                if (SELAD) begin
                    AREG <= DI;
                end



                else if (SELAC) begin
                    if (DDWA) begin
                        DIRA <= DI;
                        DDWA <= 0;
                    end else if (MFA) begin
                        IMWA <= DI;
                        MFA  <= 0;
                    end else if (DI[0] == 0) begin
                        VECTA <= DI;
                    end else if (DI[3:0] == 4'b1111) begin
                        MODEA <= DI[7:6];
                        DDWA  <= (DI[7] && DI[6]);
                    end else if (DI[3:0] == 4'b0111) begin
                        MFA <= DI[4];
                        HLA <= DI[5];
                        AOA <= DI[6];
                        EIA <= DI[7];
                    end else if (DI[3:0] == 4'b0011) begin
                        EIA <= DI[7];
                    end
                end
                if (SELBC) begin
                    if (DDWB) begin
                        DIRB <= DI;
                        DDWB <= 0;
                    end else if (MFB) begin
                        IMWB <= DI;
                        MFB  <= 0;
                    end else if (DI[0] == 0) begin
                        VECTB <= DI;
                    end else if (DI[3:0] == 4'b1111) begin
                        MODEB <= DI[7:6];
                        DDWB  <= (DI[7] && DI[6]);
                    end else if (DI[3:0] == 4'b0111) begin
                        MFB <= DI[4];
                        HLB <= DI[5];
                        AOB <= DI[6];
                        EIB <= DI[7];
                    end else if (DI[3:0] == 4'b0011) begin
                        EIB <= DI[7];
                    end
                end
            end
        end
    end
end

assign A = AREG;


always @* begin
    if (~RD_n && ~CE && SELAD) begin
        DO <= AREG;
    end else if (~RD_n && ~CE && SELBD) begin
        DO <= B;


    end else if (VECTENB == 1'b1) begin
        DO <= VECTB;
    end
end


genvar i;
generate : INTSEL




    for (i = 0; i < 7; i = i + 1 ) begin : INTMASKB
        assign MINTB[i] = AOB ? (B[i] ~^ HLB) | IMWB[i] :
                                (B[I] ~^ HLB) & ((~IMWB[I]));
    end : INTMASKB
endgenerate : INTSEL




assign INTB = AOB ? (MINTB[7] && MINTB[6] && MINTB[5] && MINTB[4] && MINTB[3] && MINTB[2] && MINTB[1] && MINTB[0]) :
                    (MINTB[7] || MINTB[6] || MINTB[5] || MINTB[4] || MINTB[3] || MINTB[2] || MINTB[1] || MINTB[0]);

endmodule
module z8420
(

    input        RST_n,


    input        CLK,
    input        ENA,
    input        BASEL,
    input        CDSEL,
    input        CE,
    input        RD_n,
    input        WR_n,
    input        IORQ_n,
    input        M1_n,
    input  [7:0] DI,
    output [7:0] DO,
    input        IEI,
    output       IEO,

    output       INT_n,
    

    output [7:0] A,
    input  [7:0] B
);



wire SELAD;
wire SELBD;
wire SELAC;
wire SELBC;


reg  [7:0] AREG;
reg  [7:0] DIRA;
wire       DDWA;
reg  [7:0] IMWA;
wire       MFA;
reg  [7:0] VECTA;
reg  [1:0] MODEA;
wire       HLA;
wire       AOA;
reg  [7:0] DIRB;
wire       DDWB;
reg  [7:0] IMWB;
wire       MFB;
reg  [7:0] VECTB;
reg  [1:0] MODEB;
wire       HLB;
wire       AOB;



wire       EIA;


wire       VECTENB;
wire       EIB;
reg  [7:0] MINTB;
wire       INTB;






















INT1 Interrupt
(

    .RESET(RST_n),


    .DI(DI),
    .IORQ_n(IORQ_n),
    .RD_n(RD_n),
    .M1_n(M1_n),
    .IEI(IEI),
    .IEO(IEO),
    .INTO_n(INT_n),


    .VECTEN(VECTENB),
    .INTI(INTB),
    .INTEN(EIB)
);


always @* begin : portSelect
    SELAD <= 0;
    SELBD <= 0;
    SELAC <= 0;
    SELBC <= 0;
    if (~BASEL && ~CDSEL) begin
        SELAD <= 1;
    end
    if (BASEL && ~CDSEL) begin
        SELBD <= 1;
    end
    if (~BASEL && CDSEL) begin
        SELAC <= 1;
    end
    if (BASEL && CDSEL) begin
        SELBC <= 1;
    end
end


always @(posedge CLK or posedge RST_n or posedge ENA) begin
    if (~RST_n) begin
        AREG  <= {8{8'b0}};
        MODEA <= 2'b01;
        DDWA  <= 0;
        MFA   <= 0;
        EIA   <= 0;

        MODEB <= 2'b01;
        DDWB  <= 0;
        MFB   <= 0;
        EIB   <= 0;
    end else if (~CLK) begin
        if (ENA) begin
            if (~CE && ~WR_n) begin
                if (SELAD) begin
                    AREG <= DI;
                end



                else if (SELAC) begin
                    if (DDWA) begin
                        DIRA <= DI;
                        DDWA <= 0;
                    end else if (MFA) begin
                        IMWA <= DI;
                        MFA  <= 0;
                    end else if (DI[0] == 0) begin
                        VECTA <= DI;
                    end else if (DI[3:0] == 4'b1111) begin
                        MODEA <= DI[7:6];
                        DDWA  <= (DI[7] && DI[6]);
                    end else if (DI[3:0] == 4'b0111) begin
                        MFA <= DI[4];
                        HLA <= DI[5];
                        AOA <= DI[6];
                        EIA <= DI[7];
                    end else if (DI[3:0] == 4'b0011) begin
                        EIA <= DI[7];
                    end
                end
                if (SELBC) begin
                    if (DDWB) begin
                        DIRB <= DI;
                        DDWB <= 0;
                    end else if (MFB) begin
                        IMWB <= DI;
                        MFB  <= 0;
                    end else if (DI[0] == 0) begin
                        VECTB <= DI;
                    end else if (DI[3:0] == 4'b1111) begin
                        MODEB <= DI[7:6];
                        DDWB  <= (DI[7] && DI[6]);
                    end else if (DI[3:0] == 4'b0111) begin
                        MFB <= DI[4];
                        HLB <= DI[5];
                        AOB <= DI[6];
                        EIB <= DI[7];
                    end else if (DI[3:0] == 4'b0011) begin
                        EIB <= DI[7];
                    end
                end
            end
        end
    end
end

assign A = AREG;


always @* begin
    if (~RD_n && ~CE && SELAD) begin
        DO <= AREG;
    end else if (~RD_n && ~CE && SELBD) begin
        DO <= B;


    end else if (VECTENB == 1'b1) begin
        DO <= VECTB;
    end
end


genvar i;
generate : INTSEL




    for (i = 0; i < 7; i = i + 1 ) begin : INTMASKB
        assign MINTB[i] = AOB ? (B[i] ~^ HLB) | IMWB[i] :
                                (B[I] ~^ HLB) & ((~IMWB[I]));
    end : INTMASKB
endgenerate : INTSEL




assign INTB = AOB ? (MINTB[7] && MINTB[6] && MINTB[5] && MINTB[4] && MINTB[3] && MINTB[2] && MINTB[1] && MINTB[0]) :
                    (MINTB[7] || MINTB[6] || MINTB[5] || MINTB[4] || MINTB[3] || MINTB[2] || MINTB[1] || MINTB[0]);

endmodule