data/full_repos/permissive/475231219/multiplexers/mux2to1v.v
data/verilator_xmls/34fe68ea-6aff-4dce-b563-b59b1139dc04.xml
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	assign out = sel?b:a;
endmodule
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

	assign out = sel?b:a;
endmodule