data/full_repos/permissive/515100461/sequential/pcupdate.v
data/verilator_xmls/5b618f92-151f-4739-b883-a43f292017f3.xml
module pcupdate(clk,valP,valC,valM,cnd,icode,PC);
input clk,cnd;
input [3:0] icode;
input [63:0] valP,valC,valM;
output reg[63:0] PC;

always@(*)
begin
    if (icode == 4'b0111)
    begin
        if(cnd)
        PC = valC;
        else 
        PC = valP;
    end

    else if (icode == 4'b1000)
    PC = valC;

    else if(icode == 4'b1001)
    PC = valM;

    else
    PC = valP;

end
endmodule
module pcupdate(clk,valP,valC,valM,cnd,icode,PC);

input clk,cnd;
input [3:0] icode;
input [63:0] valP,valC,valM;
output reg[63:0] PC;

always@(*)
begin
    if (icode == 4'b0111)
    begin
        if(cnd)
        PC = valC;
        else 
        PC = valP;
    end

    else if (icode == 4'b1000)
    PC = valC;

    else if(icode == 4'b1001)
    PC = valM;

    else
    PC = valP;

end
endmodule