data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/UPDOWN.v
data/verilator_xmls/c3db2c37-72ba-43c7-821c-4c87afcb6f11.xml
module UPDOWN(
    input clk1,
    input rst1,
    input load,
    input ud,
    input [3:0] a,
    output reg [3:0] tmp=0
    );
   
    always@(posedge clk1)
    begin
    if(load)
       begin 
       tmp=a;
       end
     else
     begin 
        if(rst1)
            begin
                if(ud)
                tmp<= 4'd9;
                else
                tmp<= 4'd0;    
             end                
        else
            begin
                if(ud)
                    if(tmp==4'd0)
                        tmp <= 4'd9;
                    else    
                        tmp <= tmp-1;
                else
                    if(tmp==4'd9)
                        tmp <= 4'd0;
                    else
                        tmp <= tmp+1;
             end  
        end  
    end
 
 
           
endmodule
module UPDOWN(
    input clk1,
    input rst1,
    input load,
    input ud,
    input [3:0] a,
    output reg [3:0] tmp=0
    );

   
    always@(posedge clk1)
    begin
    if(load)
       begin 
       tmp=a;
       end
     else
     begin 
        if(rst1)
            begin
                if(ud)
                tmp<= 4'd9;
                else
                tmp<= 4'd0;    
             end                
        else
            begin
                if(ud)
                    if(tmp==4'd0)
                        tmp <= 4'd9;
                    else    
                        tmp <= tmp-1;
                else
                    if(tmp==4'd9)
                        tmp <= 4'd0;
                    else
                        tmp <= tmp+1;
             end  
        end  
    end
 
 
           
endmodule