data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v
1: b'%Error: data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v:43: Unsupported or unknown PLI call: $monitor\n        $monitor ("a=0x%0h b=0x%0h c_in=0x%0h c_out=0x%0h sum=0x%0h", a, b, c_in, c_out, sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n            #10 a <= $random;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v:52: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("fulladder_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, fulladder_tb);  \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435170935/001-fulladder/fulladder_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #50 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fulladder_tb;
    localparam width = 2;

    reg [width:0] a;
    reg [width:0] b;
    reg c_in;
    wire [width:0] sum;
    integer i;


    fulladder #(
        .width (width)
    ) FULLADDER (
        .a (a),
        .b (b),
        .c_in (c_in),
        .c_out (c_out),
        .sum (sum)
    );


   initial begin
        a <= 0;
        b <= 0;
        c_in <= 0;

        $monitor ("a=0x%0h b=0x%0h c_in=0x%0h c_out=0x%0h sum=0x%0h", a, b, c_in, c_out, sum);


        for (i = 0; i < 5; i = i+1) begin
            #10 a <= $random;
                b <= $random;
                    c_in <= $random;
        end

        $dumpfile("fulladder_tb.vcd");
        $dumpvars(0, fulladder_tb);

        #50 $finish;
    end
endmodule
module fulladder_tb;

    localparam width = 2;

    reg [width:0] a;
    reg [width:0] b;
    reg c_in;
    wire [width:0] sum;
    integer i;


    fulladder #(
        .width (width)
    ) FULLADDER (
        .a (a),
        .b (b),
        .c_in (c_in),
        .c_out (c_out),
        .sum (sum)
    );


   initial begin
        a <= 0;
        b <= 0;
        c_in <= 0;

        $monitor ("a=0x%0h b=0x%0h c_in=0x%0h c_out=0x%0h sum=0x%0h", a, b, c_in, c_out, sum);


        for (i = 0; i < 5; i = i+1) begin
            #10 a <= $random;
                b <= $random;
                    c_in <= $random;
        end

        $dumpfile("fulladder_tb.vcd");
        $dumpvars(0, fulladder_tb);

        #50 $finish;
    end
endmodule