data/full_repos/permissive/423547971/College Coursework/Advanced Computer Architecture Final Project/verilog CPU/ALU.v
1: b'%Error: Cannot find file containing module: Coursework/Advanced\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Advanced\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.v\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.sv\n             Coursework/Advanced\n             Coursework/Advanced.v\n             Coursework/Advanced.sv\n             obj_dir/Coursework/Advanced\n             obj_dir/Coursework/Advanced.v\n             obj_dir/Coursework/Advanced.sv\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Architecture\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project/verilog\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: CPU/ALU.v\n%Error: Exiting due to 8 error(s)\n'
module alu(x, y, opcode, result, CCR);

  parameter WIDTH = 16;  

  input  [WIDTH-1:0]    x;
  input  [WIDTH-1:0]    y;
  input  [2:0] 	   	opcode;
  output reg	   	result;
  output reg [7:0] 	CCR;

  reg    [WIDTH:0]	sub_result;

always @*
  begin
    case
	if( opcode == 3'b000 ) sub_result <=    !x;
	if( opcode == 3'b001 ) sub_result <= x & y;
	if( opcode == 3'b000 ) sub_result <= x | y;
	if( opcode == 3'b001 ) sub_result <= x ^ y;
	if( opcode == 3'b010 ) sub_result <= x + y;
	if( opcode == 3'b011 ) sub_result <= x - y;
    endcase
		
	CCR[0] = sub_result[WIDTH];
	CCR[1] = result[WIDTH-1];
        CCR[2] = result==0 ? 1 : 0;
	CCR[3] = x > y  ? 1 : 0;
	CCR[4] = x < y  ? 1 : 0;
	CCR[6] = x >= y ? 1 : 0;
	
	result 	= sub_result[WIDTH-1:0];

  end
endmodule
module alu(x, y, opcode, result, CCR);


  parameter WIDTH = 16;  

  input  [WIDTH-1:0]    x;
  input  [WIDTH-1:0]    y;
  input  [2:0] 	   	opcode;
  output reg	   	result;
  output reg [7:0] 	CCR;

  reg    [WIDTH:0]	sub_result;

always @*
  begin
    case
	if( opcode == 3'b000 ) sub_result <=    !x;
	if( opcode == 3'b001 ) sub_result <= x & y;
	if( opcode == 3'b000 ) sub_result <= x | y;
	if( opcode == 3'b001 ) sub_result <= x ^ y;
	if( opcode == 3'b010 ) sub_result <= x + y;
	if( opcode == 3'b011 ) sub_result <= x - y;
    endcase
		
	CCR[0] = sub_result[WIDTH];
	CCR[1] = result[WIDTH-1];
        CCR[2] = result==0 ? 1 : 0;
	CCR[3] = x > y  ? 1 : 0;
	CCR[4] = x < y  ? 1 : 0;
	CCR[6] = x >= y ? 1 : 0;
	
	result 	= sub_result[WIDTH-1:0];

  end
endmodule