data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n always #100 spi_clock <= ~spi_clock;\n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:112: syntax error, unexpected \'@\'\n         @(posedge clock);\n         ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:117: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("actuator_driver_test1.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:118: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, actuator_driver_test1_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:122: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:143: syntax error, unexpected \'@\'\n          @(negedge spi_clock);\n          ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:147: syntax error, unexpected \'@\'\n          @(posedge spi_clock)\n          ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:152: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:162: syntax error, unexpected \'@\'\n        @(posedge clock); \n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:179: syntax error, unexpected \'@\'\n        @(posedge clock); \n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:414: syntax error, unexpected \'@\'\n        @(posedge clock); \n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:440: syntax error, unexpected \'@\'\n        @(posedge clock); \n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:453: syntax error, unexpected \'@\'\n        @(negedge trigger_out_n);\n        ^\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:492: Unsupported: wait statements\n  wait(core_to_tb === 1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:501: Unsupported: wait statements\n  wait(core_to_tb === 1\'b0);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:503: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:510: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:512: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:519: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/469300759/verilog/dv/actuator_driver_test1/actuator_driver_test1_tb.v:521: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: Exiting due to 14 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hbrige(
  output reg line,
  input wire p,
  input wire n
);
  always@(*)
  begin
    case({p,n})
        2'b00: line = 1'b0;
        2'b11: line = 1'b1;
        2'b10: line = 1'bz;
        2'b01: line = 1'bx;
    endcase
  end
endmodule
module hbrige(
  output reg line,
  input wire p,
  input wire n
);

  always@(*)
  begin
    case({p,n})
        2'b00: line = 1'b0;
        2'b11: line = 1'b1;
        2'b10: line = 1'bz;
        2'b01: line = 1'bx;
    endcase
  end
endmodule