data/full_repos/permissive/469804105/RTL/Project_files/mux_2.v
data/verilator_xmls/f3ab97de-9501-4351-b19e-9962608efce8.xml
module mux_2(
a_in , b_in, sel_1 , out
    );
input  a_in , b_in ;
input sel_1 ;
output  out;

assign out = sel_1? b_in : a_in ;   
   
endmodule
module mux_2(
a_in , b_in, sel_1 , out
    );

input  a_in , b_in ;
input sel_1 ;
output  out;

assign out = sel_1? b_in : a_in ;   
   
endmodule