data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module RegFile(clk, rs, rt, qa, qb, wrn, wbmuxOut);
    input clk;
    input [31:0] wbmuxOut;
    input [4:0] rs, rt, wrn;
    reg [31:0] regs [0:31];

    output reg [31:0] qa, qb;

    initial begin
        {regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7],
        regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15],
        regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23],
        regs[24], regs[25], regs[26], regs[27], regs[28], regs[29], regs[30], regs[31]} = 0;
    end
    
    always @(posedge clk) begin
        if(wrn != 0) begin
            regs[wrn] <= wbmuxOut;
        end
    end
    
    always @(rs, rt) begin
        qa <= regs[rs];
        qb <= regs[rt];
    end
endmodule
module RegFile(clk, rs, rt, qa, qb, wrn, wbmuxOut);

    input clk;
    input [31:0] wbmuxOut;
    input [4:0] rs, rt, wrn;
    reg [31:0] regs [0:31];

    output reg [31:0] qa, qb;

    initial begin
        {regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7],
        regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15],
        regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23],
        regs[24], regs[25], regs[26], regs[27], regs[28], regs[29], regs[30], regs[31]} = 0;
    end
    
    always @(posedge clk) begin
        if(wrn != 0) begin
            regs[wrn] <= wbmuxOut;
        end
    end
    
    always @(rs, rt) begin
        qa <= regs[rs];
        qb <= regs[rt];
    end
endmodule