data/full_repos/permissive/527578197/v1/testbench/mac_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #2 rst_n   <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #5 mac_in <= {2\'d1,2\'d2,2\'d3};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #20 mac_in <= {2\'d1,2\'d1,2\'d1};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #40 mac_in <= {2\'d0,2\'d0,2\'d0};\n    ^\n%Error: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:63: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("wave.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:64: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars("+all");\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/mac_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#1000000 $finish;\n^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mac_tb ();
reg             clk;
reg             rst_n;

reg     [1:0]   mac_in[2:0];
wire    [9:0]   mac_out[1:2];
reg             mac_done;

always #10 clk = ~clk;
initial begin
    clk     <= 0;
    rst_n   <= 0;
    #2 rst_n   <= 1;





    #5 mac_in <= {2'd1,2'd2,2'd3};
    #20 mac_in <= {2'd1,2'd1,2'd1};
    #40 mac_in <= {2'd0,2'd0,2'd0};
end
















      




mac mac_u1(
        .clk          (clk),
        .rst_n        (rst_n),
        .mac_in       (mac_in),
        .mac_out      (mac_out),
        .mac_done     (mac_done)    
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

endmodule
module mac_tb ();

reg             clk;
reg             rst_n;

reg     [1:0]   mac_in[2:0];
wire    [9:0]   mac_out[1:2];
reg             mac_done;

always #10 clk = ~clk;
initial begin
    clk     <= 0;
    rst_n   <= 0;
    #2 rst_n   <= 1;





    #5 mac_in <= {2'd1,2'd2,2'd3};
    #20 mac_in <= {2'd1,2'd1,2'd1};
    #40 mac_in <= {2'd0,2'd0,2'd0};
end
















      




mac mac_u1(
        .clk          (clk),
        .rst_n        (rst_n),
        .mac_in       (mac_in),
        .mac_out      (mac_out),
        .mac_done     (mac_done)    
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

endmodule