data/full_repos/permissive/441359809/src/yosys/manual/APPNOTE_011_Design_Investigation/splice.v
data/verilator_xmls/f019f35a-da31-4932-b5c6-5620cb35b3cd.xml
module splice_demo(a, b, c, d, e, f, x, y);

input [1:0] a, b, c, d, e, f;
output [1:0] x = {a[0], a[1]};

output [11:0] y;
assign {y[11:4], y[1:0], y[3:2]} =
                {a, b, -{c, d}, ~{e, f}};

endmodule
module splice_demo(a, b, c, d, e, f, x, y);


input [1:0] a, b, c, d, e, f;
output [1:0] x = {a[0], a[1]};

output [11:0] y;
assign {y[11:4], y[1:0], y[3:2]} =
                {a, b, -{c, d}, ~{e, f}};

endmodule