data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb/tb_iir_LA.v
1: b"%Error: data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb/tb_iir_LA.v:18: Cannot find file containing module: 'clk_gen'\n   clk_gen CG(.END_SIM(END_SIM_i),\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb,data/full_repos/permissive/430179659/clk_gen\n             data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb,data/full_repos/permissive/430179659/clk_gen.v\n             data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb,data/full_repos/permissive/430179659/clk_gen.sv\n             clk_gen\n             clk_gen.v\n             clk_gen.sv\n             obj_dir/clk_gen\n             obj_dir/clk_gen.v\n             obj_dir/clk_gen.sv\n%Error: data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb/tb_iir_LA.v:22: Cannot find file containing module: 'data_maker_LA'\n   data_maker_LA SM(.CLK(CLK_i),\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb/tb_iir_LA.v:32: Cannot find file containing module: 'IIR_filter_LA'\n   IIR_filter_LA UUT(.CLK(CLK_i),\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB1/Look-Ahead/tb/tb_iir_LA.v:44: Cannot find file containing module: 'data_sink'\n   data_sink DS(.CLK(CLK_i),\n   ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module tb_iir_LA ();

   wire CLK_i;
   wire RST_n_i;
   wire [13:0] DIN_i;
   wire VIN_i;
   wire [13:0] B0_i;
   wire [13:0] B1_i;
   wire [13:0] A1_i;

   wire [13:0] DOUT_i;
   wire VOUT_i;
   wire END_SIM_i;


   clk_gen CG(.END_SIM(END_SIM_i),
  	      .CLK(CLK_i),
	      .RST_n(RST_n_i));

   data_maker_LA SM(.CLK(CLK_i),
   .RST_n(RST_n_i),
	 .VOUT(VIN_i),
	 .DOUT(DIN_i),
	 .B0(B0_i),
	 .B1(B1_i),
	 .A1(A1_i),

	 .END_SIM(END_SIM_i));

   IIR_filter_LA UUT(.CLK(CLK_i),
   .RST_n(RST_n_i),
	 .VIN(VIN_i),
	 .VOUT(VOUT_i),
   .DIN(DIN_i),
   .B0(B0_i),
   .B1(B1_i),
   .A1(A1_i),

   .DOUT(DOUT_i));


   data_sink DS(.CLK(CLK_i),
  	.RST_n(RST_n_i),
  	.VIN(VOUT_i),
  	.DIN(DOUT_i));

endmodule
module tb_iir_LA ();


   wire CLK_i;
   wire RST_n_i;
   wire [13:0] DIN_i;
   wire VIN_i;
   wire [13:0] B0_i;
   wire [13:0] B1_i;
   wire [13:0] A1_i;

   wire [13:0] DOUT_i;
   wire VOUT_i;
   wire END_SIM_i;


   clk_gen CG(.END_SIM(END_SIM_i),
  	      .CLK(CLK_i),
	      .RST_n(RST_n_i));

   data_maker_LA SM(.CLK(CLK_i),
   .RST_n(RST_n_i),
	 .VOUT(VIN_i),
	 .DOUT(DIN_i),
	 .B0(B0_i),
	 .B1(B1_i),
	 .A1(A1_i),

	 .END_SIM(END_SIM_i));

   IIR_filter_LA UUT(.CLK(CLK_i),
   .RST_n(RST_n_i),
	 .VIN(VIN_i),
	 .VOUT(VOUT_i),
   .DIN(DIN_i),
   .B0(B0_i),
   .B1(B1_i),
   .A1(A1_i),

   .DOUT(DOUT_i));


   data_sink DS(.CLK(CLK_i),
  	.RST_n(RST_n_i),
  	.VIN(VOUT_i),
  	.DIN(DOUT_i));

endmodule