data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_clksw.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_clkgn_clksw.v:26: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_clsp_clkgn_clksw(

cmp_tst_clk, cmp_clk_sel, dram_tst_clk, dram_clk_sel, jbus_tst_clk, 
jbus_clk_sel, 

io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_jbus, 
jtag_clock_dr_dram, capture_l, jtag_clsp_sel_cpu, jtag_clsp_sel_dram, 
jtag_clsp_sel_jbus, jbus_alt_bypsel_l,  
cmp_div_bypass, cmp_gclk_bypass, jbus_div_bypass, jbus_gclk_bypass, 
dram_gclk_bypass, testmode_l, cmp_nstep_sel, jbus_nstep_sel, 
dram_nstep_sel
);


input io_pwron_rst_l;
input jtag_clock_dr_cmp;   
input jtag_clock_dr_jbus;   
input jtag_clock_dr_dram;   
input capture_l;

input [2:0] jtag_clsp_sel_cpu;
input [2:0] jtag_clsp_sel_dram;
input [2:0] jtag_clsp_sel_jbus;
input jbus_alt_bypsel_l;

input cmp_div_bypass;
input cmp_gclk_bypass;
input jbus_div_bypass;
input jbus_gclk_bypass;
input dram_gclk_bypass;
input testmode_l;

input cmp_nstep_sel;
input jbus_nstep_sel;
input dram_nstep_sel;

output cmp_tst_clk;
output cmp_clk_sel;

output dram_tst_clk;
output dram_clk_sel;

output jbus_tst_clk;
output jbus_clk_sel;         






   ctu_clsp_clkgn_clksel u_cmp(

			       .clkout	(cmp_tst_clk),
			       .sysclk_sel(cmp_clk_sel),

			       .io_pwron_rst_l(io_pwron_rst_l),
			       .sel	(jtag_clsp_sel_cpu[2:0]),
			       .testmode_l(testmode_l),
			       .sysclk	(cmp_gclk_bypass),
			       .divbypclk(cmp_div_bypass),
			       .byp_mult_sel_l(1'b0),
			       .nstepsel(cmp_nstep_sel),
			       .jtag_clock_dr(jtag_clock_dr_cmp),
			       .capture_l(capture_l),
			       .bypmode	(1'b0));



   
   ctu_clsp_clkgn_clksel u_jbus(

				.clkout	(jbus_tst_clk),
				.sysclk_sel(jbus_clk_sel),

				.io_pwron_rst_l(io_pwron_rst_l),
				.sel	(jtag_clsp_sel_jbus[2:0]),
				.testmode_l(testmode_l),
				.sysclk	(jbus_gclk_bypass),
				.divbypclk(jbus_div_bypass),
				.byp_mult_sel_l(jbus_alt_bypsel_l),
				.nstepsel(jbus_nstep_sel),
				.jtag_clock_dr(jtag_clock_dr_jbus),
				.capture_l(capture_l),
				.bypmode(jtag_clsp_sel_jbus[2]));




    ctu_clsp_clkgn_clksel u_dram (

				  .clkout(dram_tst_clk),
				  .sysclk_sel(dram_clk_sel),

				  .io_pwron_rst_l(io_pwron_rst_l),
				  .sel	(jtag_clsp_sel_dram[2:0]),
				  .testmode_l(testmode_l),
				  .sysclk(dram_gclk_bypass),
				  .divbypclk(1'b0),
				  .byp_mult_sel_l(1'b1),
				  .nstepsel(dram_nstep_sel),
				  .jtag_clock_dr(jtag_clock_dr_dram),
				  .capture_l(capture_l),
				  .bypmode(1'b0));




endmodule
module ctu_clsp_clkgn_clksw(

cmp_tst_clk, cmp_clk_sel, dram_tst_clk, dram_clk_sel, jbus_tst_clk, 
jbus_clk_sel, 

io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_jbus, 
jtag_clock_dr_dram, capture_l, jtag_clsp_sel_cpu, jtag_clsp_sel_dram, 
jtag_clsp_sel_jbus, jbus_alt_bypsel_l,  
cmp_div_bypass, cmp_gclk_bypass, jbus_div_bypass, jbus_gclk_bypass, 
dram_gclk_bypass, testmode_l, cmp_nstep_sel, jbus_nstep_sel, 
dram_nstep_sel
);



input io_pwron_rst_l;
input jtag_clock_dr_cmp;   
input jtag_clock_dr_jbus;   
input jtag_clock_dr_dram;   
input capture_l;

input [2:0] jtag_clsp_sel_cpu;
input [2:0] jtag_clsp_sel_dram;
input [2:0] jtag_clsp_sel_jbus;
input jbus_alt_bypsel_l;

input cmp_div_bypass;
input cmp_gclk_bypass;
input jbus_div_bypass;
input jbus_gclk_bypass;
input dram_gclk_bypass;
input testmode_l;

input cmp_nstep_sel;
input jbus_nstep_sel;
input dram_nstep_sel;

output cmp_tst_clk;
output cmp_clk_sel;

output dram_tst_clk;
output dram_clk_sel;

output jbus_tst_clk;
output jbus_clk_sel;         






   ctu_clsp_clkgn_clksel u_cmp(

			       .clkout	(cmp_tst_clk),
			       .sysclk_sel(cmp_clk_sel),

			       .io_pwron_rst_l(io_pwron_rst_l),
			       .sel	(jtag_clsp_sel_cpu[2:0]),
			       .testmode_l(testmode_l),
			       .sysclk	(cmp_gclk_bypass),
			       .divbypclk(cmp_div_bypass),
			       .byp_mult_sel_l(1'b0),
			       .nstepsel(cmp_nstep_sel),
			       .jtag_clock_dr(jtag_clock_dr_cmp),
			       .capture_l(capture_l),
			       .bypmode	(1'b0));



   
   ctu_clsp_clkgn_clksel u_jbus(

				.clkout	(jbus_tst_clk),
				.sysclk_sel(jbus_clk_sel),

				.io_pwron_rst_l(io_pwron_rst_l),
				.sel	(jtag_clsp_sel_jbus[2:0]),
				.testmode_l(testmode_l),
				.sysclk	(jbus_gclk_bypass),
				.divbypclk(jbus_div_bypass),
				.byp_mult_sel_l(jbus_alt_bypsel_l),
				.nstepsel(jbus_nstep_sel),
				.jtag_clock_dr(jtag_clock_dr_jbus),
				.capture_l(capture_l),
				.bypmode(jtag_clsp_sel_jbus[2]));




    ctu_clsp_clkgn_clksel u_dram (

				  .clkout(dram_tst_clk),
				  .sysclk_sel(dram_clk_sel),

				  .io_pwron_rst_l(io_pwron_rst_l),
				  .sel	(jtag_clsp_sel_dram[2:0]),
				  .testmode_l(testmode_l),
				  .sysclk(dram_gclk_bypass),
				  .divbypclk(1'b0),
				  .byp_mult_sel_l(1'b1),
				  .nstepsel(dram_nstep_sel),
				  .jtag_clock_dr(jtag_clock_dr_dram),
				  .capture_l(capture_l),
				  .bypmode(1'b0));




endmodule