data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v
1: b'%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:41: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("results.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:42: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #5 sim_rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #5 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n            #10 sim_clk_gen = ~sim_clk_gen;\n            ^\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:85: Define or directive not defined: \'`MAX_CLOCKS\'\n            if (CLOCK_LIMIT === `MAX_CLOCKS)\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if (CLOCK_LIMIT === `MAX_CLOCKS)\n                                           ^\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:94: syntax error, unexpected <=, expecting IDENTIFIER\n                test_progress <= ip_test_top.testregs.test_progress;\n                              ^~\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:101: syntax error, unexpected \'#\'\n                #20;\n                ^\n%Error: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:109: syntax error, unexpected \'#\'\n                #20;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51896788/projects/ip_test/testbench/rtl/testbench.v:124: Unsupported: Ignoring delay on this delayed statement.\n            #33 sim_clk_slow_gen = ~sim_clk_slow_gen;\n            ^\n%Error: Exiting due to 7 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg sim_rst;
    reg sim_clk;
    reg sim_clk_gen;
    integer cycle_count;

    initial
    begin
        sim_rst = 1;
        sim_clk_gen = 0;
        $dumpfile("results.vcd");
        $dumpvars(0);
        cycle_count = 0;
        #10 sim_rst = 0;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #5 sim_rst = 1;
        #5 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;
        while (1)
        begin
            #10 sim_clk_gen = ~sim_clk_gen;
            cycle_count = (sim_clk_gen) ? cycle_count : cycle_count + 1;
        end
    end

    always @ (sim_clk_gen)
        sim_clk <= sim_clk_gen;

    integer CLOCK_LIMIT;
    wire [4:0] user_leds;
    reg [31:0] test_progress;

    always @ (posedge sim_clk or posedge sim_rst)
        if (sim_rst)
        begin
            CLOCK_LIMIT <= 32'd0;
            test_progress <= ip_test_top.testregs.test_progress;
        end
        else
        begin
            CLOCK_LIMIT <= CLOCK_LIMIT + 32'd1;
            if (CLOCK_LIMIT === `MAX_CLOCKS)
            begin
                #20;
                $display(" ****** MAX CLOCKS - ENDING SIMULATION *****");
                $finish();
            end

            if (ip_test_top.testregs.test_progress != test_progress)
            begin
                test_progress <= ip_test_top.testregs.test_progress;
                $display(" ****** TEST PROGRESS %X *****",
                ip_test_top.testregs.test_progress);
            end

            if (ip_test_top.testregs.test_fail != 32'd0)
            begin
                #20;
                $display(" ****** TEST FAILED  %08X *****" ,
                ip_test_top.testregs.test_fail);
                $finish();
            end

            if (ip_test_top.testregs.test_pass != 32'd0)
            begin
                #20;
                $display(" ****** TEST PASSED  %08X *****" ,
                ip_test_top.testregs.test_pass);
                $finish();
            end
        end

    reg sim_clk_slow;
    reg sim_clk_slow_gen;

    initial
    begin
        sim_clk_slow_gen = 0;
        while (1)
        begin
            #33 sim_clk_slow_gen = ~sim_clk_slow_gen;
        end
    end

    always @ (sim_clk_slow_gen)
        sim_clk_slow <= sim_clk_slow_gen;

    wire uart_tx;
    wire uart_rx;

    ip_test_top ip_test_top
    (
        .clk_50(sim_clk),
        .clk_slow(sim_clk_slow),
        .fpga_reset_n(!sim_rst),

        .qspi_clk(),
        .qspi_io(),
        .qspi_csn(),

        .uart_0_rx(uart_rx),
        .uart_0_tx(uart_tx),

        .uart_1_rx(uart_tx),
        .uart_1_tx(uart_rx),

        .user_led(user_leds),
        .user_pb(4'b1111)
    );

endmodule
module testbench();


    reg sim_rst;
    reg sim_clk;
    reg sim_clk_gen;
    integer cycle_count;

    initial
    begin
        sim_rst = 1;
        sim_clk_gen = 0;
        $dumpfile("results.vcd");
        $dumpvars(0);
        cycle_count = 0;
        #10 sim_rst = 0;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #5 sim_rst = 1;
        #5 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen;
        #10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;
        while (1)
        begin
            #10 sim_clk_gen = ~sim_clk_gen;
            cycle_count = (sim_clk_gen) ? cycle_count : cycle_count + 1;
        end
    end

    always @ (sim_clk_gen)
        sim_clk <= sim_clk_gen;

    integer CLOCK_LIMIT;
    wire [4:0] user_leds;
    reg [31:0] test_progress;

    always @ (posedge sim_clk or posedge sim_rst)
        if (sim_rst)
        begin
            CLOCK_LIMIT <= 32'd0;
            test_progress <= ip_test_top.testregs.test_progress;
        end
        else
        begin
            CLOCK_LIMIT <= CLOCK_LIMIT + 32'd1;
            if (CLOCK_LIMIT === `MAX_CLOCKS)
            begin
                #20;
                $display(" ****** MAX CLOCKS - ENDING SIMULATION *****");
                $finish();
            end

            if (ip_test_top.testregs.test_progress != test_progress)
            begin
                test_progress <= ip_test_top.testregs.test_progress;
                $display(" ****** TEST PROGRESS %X *****",
                ip_test_top.testregs.test_progress);
            end

            if (ip_test_top.testregs.test_fail != 32'd0)
            begin
                #20;
                $display(" ****** TEST FAILED  %08X *****" ,
                ip_test_top.testregs.test_fail);
                $finish();
            end

            if (ip_test_top.testregs.test_pass != 32'd0)
            begin
                #20;
                $display(" ****** TEST PASSED  %08X *****" ,
                ip_test_top.testregs.test_pass);
                $finish();
            end
        end

    reg sim_clk_slow;
    reg sim_clk_slow_gen;

    initial
    begin
        sim_clk_slow_gen = 0;
        while (1)
        begin
            #33 sim_clk_slow_gen = ~sim_clk_slow_gen;
        end
    end

    always @ (sim_clk_slow_gen)
        sim_clk_slow <= sim_clk_slow_gen;

    wire uart_tx;
    wire uart_rx;

    ip_test_top ip_test_top
    (
        .clk_50(sim_clk),
        .clk_slow(sim_clk_slow),
        .fpga_reset_n(!sim_rst),

        .qspi_clk(),
        .qspi_io(),
        .qspi_csn(),

        .uart_0_rx(uart_rx),
        .uart_0_tx(uart_tx),

        .uart_1_rx(uart_tx),
        .uart_1_tx(uart_rx),

        .user_led(user_leds),
        .user_pb(4'b1111)
    );

endmodule