data/full_repos/permissive/486907441/HA.v
data/verilator_xmls/cfb2ffb2-7611-4c4f-9598-12a42335036a.xml
module HA(a,b,sum,carry);
input a,b;
output sum,carry;
wire sum,carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
module HA(a,b,sum,carry);

input a,b;
output sum,carry;
wire sum,carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule