data/full_repos/permissive/419273451/lab1/codes/Control.v
1: b"%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:25: Can't find definition of scope/variable: 'CPU'\nassign RegWrite_o = ~NoOp_i && ~(Op_i == CPU.OP_STORE || Op_i == CPU.OP_BRANCH);\n                                         ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:25: Can't find definition of scope/variable: 'CPU'\nassign RegWrite_o = ~NoOp_i && ~(Op_i == CPU.OP_STORE || Op_i == CPU.OP_BRANCH);\n                                                                 ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:26: Can't find definition of scope/variable: 'CPU'\nassign MemtoReg_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_ITYPE);\n                                         ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:26: Can't find definition of scope/variable: 'CPU'\nassign MemtoReg_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_ITYPE);\n                                                                 ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:27: Can't find definition of scope/variable: 'CPU'\nassign MemRead_o = ~NoOp_i && (Op_i == CPU.OP_LOAD);\n                                       ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:28: Can't find definition of scope/variable: 'CPU'\nassign MemWrite_o = ~NoOp_i && (Op_i == CPU.OP_STORE);\n                                        ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:31: Can't find definition of scope/variable: 'CPU'\n    (Op_i == CPU.OP_RTYPE) ? ALU_Control.ALUOp_RType :\n             ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:31: Can't find definition of scope/variable: 'ALU_Control'\n    (Op_i == CPU.OP_RTYPE) ? ALU_Control.ALUOp_RType :\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:32: Can't find definition of scope/variable: 'CPU'\n    (Op_i == CPU.OP_ITYPE) ? ALU_Control.ALUOp_IType :\n             ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:32: Can't find definition of scope/variable: 'ALU_Control'\n    (Op_i == CPU.OP_ITYPE) ? ALU_Control.ALUOp_IType :\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:33: Can't find definition of scope/variable: 'CPU'\n    (Op_i == CPU.OP_BRANCH) ? ALU_Control.ALUOp_Subtract :\n             ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:33: Can't find definition of scope/variable: 'ALU_Control'\n    (Op_i == CPU.OP_BRANCH) ? ALU_Control.ALUOp_Subtract :\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:34: Can't find definition of scope/variable: 'ALU_Control'\n    ALU_Control.ALUOp_Add;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:35: Can't find definition of scope/variable: 'CPU'\nassign ALUSrc_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_BRANCH);\n                                       ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:35: Can't find definition of scope/variable: 'CPU'\nassign ALUSrc_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_BRANCH);\n                                                               ^~~\n%Error: data/full_repos/permissive/419273451/lab1/codes/Control.v:36: Can't find definition of scope/variable: 'CPU'\nassign Branch_o = ~NoOp_i && (Op_i == CPU.OP_BRANCH);\n                                      ^~~\n%Error: Exiting due to 16 error(s)\n"
module Control
(
    NoOp_i,
    Op_i, 
    RegWrite_o,
    MemtoReg_o,
    MemRead_o,
    MemWrite_o,
    ALUOp_o,
    ALUSrc_o,
    Branch_o
);


input               NoOp_i;
input   [6:0]       Op_i;
output              RegWrite_o;
output              MemtoReg_o;
output              MemRead_o;
output              MemWrite_o;
output  [1:0]       ALUOp_o;
output              ALUSrc_o;
output              Branch_o;

assign RegWrite_o = ~NoOp_i && ~(Op_i == CPU.OP_STORE || Op_i == CPU.OP_BRANCH);
assign MemtoReg_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_ITYPE);
assign MemRead_o = ~NoOp_i && (Op_i == CPU.OP_LOAD);
assign MemWrite_o = ~NoOp_i && (Op_i == CPU.OP_STORE);
assign ALUOp_o = 
    (NoOp_i) ? 2'b00 :
    (Op_i == CPU.OP_RTYPE) ? ALU_Control.ALUOp_RType :
    (Op_i == CPU.OP_ITYPE) ? ALU_Control.ALUOp_IType :
    (Op_i == CPU.OP_BRANCH) ? ALU_Control.ALUOp_Subtract :
    ALU_Control.ALUOp_Add;
assign ALUSrc_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_BRANCH);
assign Branch_o = ~NoOp_i && (Op_i == CPU.OP_BRANCH);

endmodule
module Control
(
    NoOp_i,
    Op_i, 
    RegWrite_o,
    MemtoReg_o,
    MemRead_o,
    MemWrite_o,
    ALUOp_o,
    ALUSrc_o,
    Branch_o
);



input               NoOp_i;
input   [6:0]       Op_i;
output              RegWrite_o;
output              MemtoReg_o;
output              MemRead_o;
output              MemWrite_o;
output  [1:0]       ALUOp_o;
output              ALUSrc_o;
output              Branch_o;

assign RegWrite_o = ~NoOp_i && ~(Op_i == CPU.OP_STORE || Op_i == CPU.OP_BRANCH);
assign MemtoReg_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_ITYPE);
assign MemRead_o = ~NoOp_i && (Op_i == CPU.OP_LOAD);
assign MemWrite_o = ~NoOp_i && (Op_i == CPU.OP_STORE);
assign ALUOp_o = 
    (NoOp_i) ? 2'b00 :
    (Op_i == CPU.OP_RTYPE) ? ALU_Control.ALUOp_RType :
    (Op_i == CPU.OP_ITYPE) ? ALU_Control.ALUOp_IType :
    (Op_i == CPU.OP_BRANCH) ? ALU_Control.ALUOp_Subtract :
    ALU_Control.ALUOp_Add;
assign ALUSrc_o = ~NoOp_i && ~(Op_i == CPU.OP_RTYPE || Op_i == CPU.OP_BRANCH);
assign Branch_o = ~NoOp_i && (Op_i == CPU.OP_BRANCH);

endmodule