data/full_repos/permissive/475928601/Counters/Up Counter/UC.v
1: b'%Error: Cannot find file containing module: Counter,data/full_repos/permissive/475928601\n        ... Looked in:\n             data/full_repos/permissive/475928601/Counters/Up/Counter,data/full_repos/permissive/475928601\n             data/full_repos/permissive/475928601/Counters/Up/Counter,data/full_repos/permissive/475928601.v\n             data/full_repos/permissive/475928601/Counters/Up/Counter,data/full_repos/permissive/475928601.sv\n             Counter,data/full_repos/permissive/475928601\n             Counter,data/full_repos/permissive/475928601.v\n             Counter,data/full_repos/permissive/475928601.sv\n             obj_dir/Counter,data/full_repos/permissive/475928601\n             obj_dir/Counter,data/full_repos/permissive/475928601.v\n             obj_dir/Counter,data/full_repos/permissive/475928601.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/475928601/Counters/Up\n%Error: Cannot find file containing module: Counter/UC.v\n%Error: Exiting due to 3 error(s)\n'
module UpCounter(
  input T,
  input clk,
  input reset,
  output reg [2:0] out
);

  initial out = 3'b000;
  

  always @(posedge clk or reset) begin
    if (reset)
      out <= 3'b000;
    else if (T)
      out = out + 3'b001;
  end
endmodule
module UpCounter(
  input T,
  input clk,
  input reset,
  output reg [2:0] out
);


  initial out = 3'b000;
  

  always @(posedge clk or reset) begin
    if (reset)
      out <= 3'b000;
    else if (T)
      out = out + 3'b001;
  end
endmodule