data/full_repos/permissive/513306128/ECEN248/top_level.v
1: b"%Error: data/full_repos/permissive/513306128/ECEN248/top_level.v:20: Cannot find file containing module: 'up_counter'\n    up_counter UCI(LEDs[2:0], LEDs[3], BTNs[0], SlowClk, BTNs[1]);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/up_counter\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/up_counter.v\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/up_counter.sv\n             up_counter\n             up_counter.v\n             up_counter.sv\n             obj_dir/up_counter\n             obj_dir/up_counter.v\n             obj_dir/up_counter.sv\n%Error: data/full_repos/permissive/513306128/ECEN248/top_level.v:22: Cannot find file containing module: 'clock_divider'\n    clock_divider clk_div0(.ClkOut(Clocks), .ClkIn(FastClk));\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_level(LEDs, SWs, BTNs, FastClk);
    output wire [3:0] LEDs;
    input wire [1:0] SWs;
    input wire [1:0] BTNs;
    input wire FastClk;
    
    wire [3:0] Clocks;
    reg SlowClk;
    
    always@(*)
        case(SWs)
            2'b00: SlowClk = Clocks[0];
            2'b01: SlowClk = Clocks[1];
            2'b10: SlowClk = Clocks[2];
            2'b11: SlowClk = Clocks[3];
        endcase
    up_counter UCI(LEDs[2:0], LEDs[3], BTNs[0], SlowClk, BTNs[1]);
    
    clock_divider clk_div0(.ClkOut(Clocks), .ClkIn(FastClk));
            
endmodule
module top_level(LEDs, SWs, BTNs, FastClk);

    output wire [3:0] LEDs;
    input wire [1:0] SWs;
    input wire [1:0] BTNs;
    input wire FastClk;
    
    wire [3:0] Clocks;
    reg SlowClk;
    
    always@(*)
        case(SWs)
            2'b00: SlowClk = Clocks[0];
            2'b01: SlowClk = Clocks[1];
            2'b10: SlowClk = Clocks[2];
            2'b11: SlowClk = Clocks[3];
        endcase
    up_counter UCI(LEDs[2:0], LEDs[3], BTNs[0], SlowClk, BTNs[1]);
    
    clock_divider clk_div0(.ClkOut(Clocks), .ClkIn(FastClk));
            
endmodule