data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v
1: b"%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:17: Define or directive not defined: '`IO_PINS'\n   input [`IO_PINS-1:0] data,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:18: Define or directive not defined: '`IO_PINS'\n   input [`IO_PINS-1:0] mask,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:19: Define or directive not defined: '`IO_PINS'\n   output [`IO_PINS-1:0] result\n           ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:23: Define or directive not defined: '`IO_PINS'\n   for (layer=0; layer<`IO_PINS; layer=layer+1) begin:comp\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   for (layer=0; layer<`IO_PINS; layer=layer+1) begin:comp\n                               ^\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:24: Define or directive not defined: '`IO_PINS'\n      wire [`IO_PINS-1:0] sd;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:26: Define or directive not defined: '`IO_PINS'\n         assign sd = {{(`IO_PINS-1){1'b0}}, data[`IO_PINS-1] & mask[`IO_PINS-1]};\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:26: Define or directive not defined: '`IO_PINS'\n         assign sd = {{(`IO_PINS-1){1'b0}}, data[`IO_PINS-1] & mask[`IO_PINS-1]};\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:26: Define or directive not defined: '`IO_PINS'\n         assign sd = {{(`IO_PINS-1){1'b0}}, data[`IO_PINS-1] & mask[`IO_PINS-1]};\n                                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:28: Define or directive not defined: '`IO_PINS'\n         wire [`IO_PINS-1:0] sdp = comp[layer-1].sd;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:29: Define or directive not defined: '`IO_PINS'\n         assign sd = mask[`IO_PINS-1-layer] ? {sdp[`IO_PINS-2:0], data[`IO_PINS-1-layer]} : sdp;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:29: Define or directive not defined: '`IO_PINS'\n         assign sd = mask[`IO_PINS-1-layer] ? {sdp[`IO_PINS-2:0], data[`IO_PINS-1-layer]} : sdp;\n                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:29: Define or directive not defined: '`IO_PINS'\n         assign sd = mask[`IO_PINS-1-layer] ? {sdp[`IO_PINS-2:0], data[`IO_PINS-1-layer]} : sdp;\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:31: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/pin_compress.v:32: Define or directive not defined: '`IO_PINS'\n   assign result = comp[`IO_PINS-1].sd;\n                        ^~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module pin_compress (
   input [`IO_PINS-1:0] data,
   input [`IO_PINS-1:0] mask,
   output [`IO_PINS-1:0] result
);

generate genvar layer;
   for (layer=0; layer<`IO_PINS; layer=layer+1) begin:comp
      wire [`IO_PINS-1:0] sd;
      if (layer == 0) begin:i_first
         assign sd = {{(`IO_PINS-1){1'b0}}, data[`IO_PINS-1] & mask[`IO_PINS-1]};
      end else begin:i_nfirst
         wire [`IO_PINS-1:0] sdp = comp[layer-1].sd;
         assign sd = mask[`IO_PINS-1-layer] ? {sdp[`IO_PINS-2:0], data[`IO_PINS-1-layer]} : sdp;
      end
   end
   assign result = comp[`IO_PINS-1].sd;
endgenerate

endmodule
module pin_compress (
   input [`IO_PINS-1:0] data,
   input [`IO_PINS-1:0] mask,
   output [`IO_PINS-1:0] result
);


generate genvar layer;
   for (layer=0; layer<`IO_PINS; layer=layer+1) begin:comp
      wire [`IO_PINS-1:0] sd;
      if (layer == 0) begin:i_first
         assign sd = {{(`IO_PINS-1){1'b0}}, data[`IO_PINS-1] & mask[`IO_PINS-1]};
      end else begin:i_nfirst
         wire [`IO_PINS-1:0] sdp = comp[layer-1].sd;
         assign sd = mask[`IO_PINS-1-layer] ? {sdp[`IO_PINS-2:0], data[`IO_PINS-1-layer]} : sdp;
      end
   end
   assign result = comp[`IO_PINS-1].sd;
endgenerate

endmodule