data/full_repos/permissive/494657797/verilog/rtl/dff.v
data/verilator_xmls/73bf0030-4def-4fab-89b8-2724cf0ccec5.xml
module dff ( input wire d,
              input wire rst,
              input wire clk,
              output reg q,
              output wire qn);
	
      initial begin
        q <= 0;
      end

      always @ (posedge clk or posedge rst)
            if (rst)
                  q <= 0;
            else
                  q <= d;
      
      assign qn = ~q;

endmodule
module dff ( input wire d,
              input wire rst,
              input wire clk,
              output reg q,
              output wire qn);

	
      initial begin
        q <= 0;
      end

      always @ (posedge clk or posedge rst)
            if (rst)
                  q <= 0;
            else
                  q <= d;
      
      assign qn = ~q;

endmodule