data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v
1: b'%Error: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:34: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n        s = $fopen("outputsine.txt");\n            ^~~~~~\n%Error: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:35: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n        c = $fopen("outputcosine.txt");\n            ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 CLK = ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 RST = 0; i = 0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 1; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 2; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 3; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 4; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 5; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 6; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 7; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 8; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 i = 9; $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/482974019/CORDIC.srcs/sim_1/new/tb_CORDIC.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10 $fwrite(s, "%b\\n", sin); $fwrite(c, "%b\\n", cos); $fclose(s); $fclose(c); $finish;\n    ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_CORDIC();
    parameter WLI = 5, WLF = 5, WLI2 = 9, WLF2 = 9; 
    parameter WIO = 2, WFO = 8; 
    reg CLK, RST;
    reg [3:0] i;
    reg signed [(WLI2+WLF2)-1:0] angle;
    wire [(WLI+WLF)-1:0] sin, cos;
    integer s,c;
    
    CORDIC #(.WLI(WLI),.WLF(WLF),.WLI2(WLI2),.WLF2(WLF2),.WIO(WIO),.WFO(WFO)) UUT (.CLK(CLK), .RST(RST), .i(i), .angle(angle), .sin(sin), .cos(cos));
    
    initial begin
        CLK = 0;
        s = $fopen("outputsine.txt");
        c = $fopen("outputcosine.txt");
    end
    
    always begin
        #5 CLK = ~CLK;
    end
    
    initial begin
        RST = 1; angle = {9'd30, 9'd0};
    #10 RST = 0; i = 0;
    #10 i = 1; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 2; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 3; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); 
    #10 i = 4; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 5; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 6; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 7; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 8; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 9; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); 
    #10 $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); $fclose(s); $fclose(c); $finish;
    end
endmodule
module tb_CORDIC();

    parameter WLI = 5, WLF = 5, WLI2 = 9, WLF2 = 9; 
    parameter WIO = 2, WFO = 8; 
    reg CLK, RST;
    reg [3:0] i;
    reg signed [(WLI2+WLF2)-1:0] angle;
    wire [(WLI+WLF)-1:0] sin, cos;
    integer s,c;
    
    CORDIC #(.WLI(WLI),.WLF(WLF),.WLI2(WLI2),.WLF2(WLF2),.WIO(WIO),.WFO(WFO)) UUT (.CLK(CLK), .RST(RST), .i(i), .angle(angle), .sin(sin), .cos(cos));
    
    initial begin
        CLK = 0;
        s = $fopen("outputsine.txt");
        c = $fopen("outputcosine.txt");
    end
    
    always begin
        #5 CLK = ~CLK;
    end
    
    initial begin
        RST = 1; angle = {9'd30, 9'd0};
    #10 RST = 0; i = 0;
    #10 i = 1; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 2; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 3; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); 
    #10 i = 4; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 5; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 6; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 7; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 8; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos);
    #10 i = 9; $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); 
    #10 $fwrite(s, "%b\n", sin); $fwrite(c, "%b\n", cos); $fclose(s); $fclose(c); $finish;
    end
endmodule