data/full_repos/permissive/470392519/tests/sub/ControlUnit.v
1: b'%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:1: Cannot find include file: ControlUnit.v\n`include "ControlUnit.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ControlUnit.v\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ControlUnit.v.v\n             data/full_repos/permissive/470392519/tests/sub,data/full_repos/permissive/470392519/ControlUnit.v.sv\n             ControlUnit.v\n             ControlUnit.v.v\n             ControlUnit.v.sv\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.v.v\n             obj_dir/ControlUnit.v.sv\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:27: Define or directive not defined: \'`OPCODE\'\n            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:27: Define or directive not defined: \'`R\'\n            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };\n                                       ^~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:27: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };\n                                               ^\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:27: Define or directive not defined: \'`R_CTRL\'\n            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };\n                                                                        ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:28: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `I_JUMP ) test_gold_vector[i] = {`I_JUMP_CTRL    };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:28: Define or directive not defined: \'`I_JUMP\'\n            else if (`OPCODE(instr) == `I_JUMP ) test_gold_vector[i] = {`I_JUMP_CTRL    };\n                                       ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:28: Define or directive not defined: \'`I_JUMP_CTRL\'\n            else if (`OPCODE(instr) == `I_JUMP ) test_gold_vector[i] = {`I_JUMP_CTRL    };\n                                                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:29: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `I_LOAD ) test_gold_vector[i] = {`I_LOAD_CTRL    };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:29: Define or directive not defined: \'`I_LOAD\'\n            else if (`OPCODE(instr) == `I_LOAD ) test_gold_vector[i] = {`I_LOAD_CTRL    };\n                                       ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:29: Define or directive not defined: \'`I_LOAD_CTRL\'\n            else if (`OPCODE(instr) == `I_LOAD ) test_gold_vector[i] = {`I_LOAD_CTRL    };\n                                                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:30: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `I_ARITH) test_gold_vector[i] = {`I_ARITH_CTRL   };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:30: Define or directive not defined: \'`I_ARITH\'\n            else if (`OPCODE(instr) == `I_ARITH) test_gold_vector[i] = {`I_ARITH_CTRL   };\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:30: Define or directive not defined: \'`I_ARITH_CTRL\'\n            else if (`OPCODE(instr) == `I_ARITH) test_gold_vector[i] = {`I_ARITH_CTRL   };\n                                                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:31: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `I_SYS  ) test_gold_vector[i] = {`I_SYS_CTRL     };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:31: Define or directive not defined: \'`I_SYS\'\n            else if (`OPCODE(instr) == `I_SYS  ) test_gold_vector[i] = {`I_SYS_CTRL     };\n                                       ^~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:31: Define or directive not defined: \'`I_SYS_CTRL\'\n            else if (`OPCODE(instr) == `I_SYS  ) test_gold_vector[i] = {`I_SYS_CTRL     };\n                                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:32: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `I_FENCE) test_gold_vector[i] = {`I_FENCE_CTRL   };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:32: Define or directive not defined: \'`I_FENCE\'\n            else if (`OPCODE(instr) == `I_FENCE) test_gold_vector[i] = {`I_FENCE_CTRL   };\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:32: Define or directive not defined: \'`I_FENCE_CTRL\'\n            else if (`OPCODE(instr) == `I_FENCE) test_gold_vector[i] = {`I_FENCE_CTRL   };\n                                                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:33: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `S      ) test_gold_vector[i] = {`S_CTRL         };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:33: Define or directive not defined: \'`S\'\n            else if (`OPCODE(instr) == `S      ) test_gold_vector[i] = {`S_CTRL         };\n                                       ^~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:33: Define or directive not defined: \'`S_CTRL\'\n            else if (`OPCODE(instr) == `S      ) test_gold_vector[i] = {`S_CTRL         };\n                                                                        ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:34: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `B      ) test_gold_vector[i] = {`B_CTRL         };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:34: Define or directive not defined: \'`B\'\n            else if (`OPCODE(instr) == `B      ) test_gold_vector[i] = {`B_CTRL         };\n                                       ^~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:34: Define or directive not defined: \'`B_CTRL\'\n            else if (`OPCODE(instr) == `B      ) test_gold_vector[i] = {`B_CTRL         };\n                                                                        ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:35: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `U_LUI  ) test_gold_vector[i] = {`U_LUI_CTRL     };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:35: Define or directive not defined: \'`U_LUI\'\n            else if (`OPCODE(instr) == `U_LUI  ) test_gold_vector[i] = {`U_LUI_CTRL     };\n                                       ^~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:35: Define or directive not defined: \'`U_LUI_CTRL\'\n            else if (`OPCODE(instr) == `U_LUI  ) test_gold_vector[i] = {`U_LUI_CTRL     };\n                                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:36: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `U_AUIPC) test_gold_vector[i] = {`U_AUIPC_CTRL   };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:36: Define or directive not defined: \'`U_AUIPC\'\n            else if (`OPCODE(instr) == `U_AUIPC) test_gold_vector[i] = {`U_AUIPC_CTRL   };\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:36: Define or directive not defined: \'`U_AUIPC_CTRL\'\n            else if (`OPCODE(instr) == `U_AUIPC) test_gold_vector[i] = {`U_AUIPC_CTRL   };\n                                                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:37: Define or directive not defined: \'`OPCODE\'\n            else if (`OPCODE(instr) == `J      ) test_gold_vector[i] = {`J_CTRL         };\n                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:37: Define or directive not defined: \'`J\'\n            else if (`OPCODE(instr) == `J      ) test_gold_vector[i] = {`J_CTRL         };\n                                       ^~\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:37: Define or directive not defined: \'`J_CTRL\'\n            else if (`OPCODE(instr) == `J      ) test_gold_vector[i] = {`J_CTRL         };\n                                                                        ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:51: Define or directive not defined: \'`OPCODE\'\n            i_opcode    = `OPCODE(instr);\n                          ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/470392519/tests/sub/ControlUnit.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Error: Exiting due to 36 error(s), 2 warning(s)\n'
module ControlUnit_tb;
    reg     [6:0]   i_opcode;
    wire    [3:0]   o_aluOp;
    wire            o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp;

    ControlUnit ControlUnit_dut(.*);

`ifdef DUMP_VCD
    initial begin
        $dumpfile("obj_dir/sub/ControlUnit.vcd");
        $dumpvars;
    end
`endif


    reg [31:0]  test_vector         [0:39];
    reg [12:0]  test_gold_vector    [0:39];
    initial begin
        $readmemh("obj_dir/sub/sub_ControlUnit.mem", test_vector);
    end
    reg [31:0]  instr;
    initial begin
        for (i=0; i<40; i=i+1) begin
            instr = test_vector[i];
            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };
            else if (`OPCODE(instr) == `I_JUMP ) test_gold_vector[i] = {`I_JUMP_CTRL    };
            else if (`OPCODE(instr) == `I_LOAD ) test_gold_vector[i] = {`I_LOAD_CTRL    };
            else if (`OPCODE(instr) == `I_ARITH) test_gold_vector[i] = {`I_ARITH_CTRL   };
            else if (`OPCODE(instr) == `I_SYS  ) test_gold_vector[i] = {`I_SYS_CTRL     };
            else if (`OPCODE(instr) == `I_FENCE) test_gold_vector[i] = {`I_FENCE_CTRL   };
            else if (`OPCODE(instr) == `S      ) test_gold_vector[i] = {`S_CTRL         };
            else if (`OPCODE(instr) == `B      ) test_gold_vector[i] = {`B_CTRL         };
            else if (`OPCODE(instr) == `U_LUI  ) test_gold_vector[i] = {`U_LUI_CTRL     };
            else if (`OPCODE(instr) == `U_AUIPC) test_gold_vector[i] = {`U_AUIPC_CTRL   };
            else if (`OPCODE(instr) == `J      ) test_gold_vector[i] = {`J_CTRL         };
        end
    end


    reg     [39:0]  resultStr;
    reg     [12:0]  ctrlSignals;
    integer i = 0, errs = 0;
    initial begin
        $display("Running ControlUnit tests...\n");
        i_opcode   = 'd0;
        #20;
        for (i=0; i<40; i=i+1) begin
            instr       = test_vector[i];
            i_opcode    = `OPCODE(instr);
            #20;
            ctrlSignals = {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp};
            if (ctrlSignals != test_gold_vector[i]) resultStr = "ERROR";
            else                                    resultStr = "PASS ";
            $display("Test[ %2d ]: instr = 0x%8h || ctrlSigs = %b ... %s",
                i, instr, ctrlSignals, resultStr
            );
            if (resultStr == "ERROR") errs = errs + 1;
        end
        if (errs > 0)   $display("\nFAILED: %0d", errs);
        else            $display("\nPASSED");

    end

endmodule
module ControlUnit_tb;

    reg     [6:0]   i_opcode;
    wire    [3:0]   o_aluOp;
    wire            o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp;

    ControlUnit ControlUnit_dut(.*);

`ifdef DUMP_VCD
    initial begin
        $dumpfile("obj_dir/sub/ControlUnit.vcd");
        $dumpvars;
    end
`endif


    reg [31:0]  test_vector         [0:39];
    reg [12:0]  test_gold_vector    [0:39];
    initial begin
        $readmemh("obj_dir/sub/sub_ControlUnit.mem", test_vector);
    end
    reg [31:0]  instr;
    initial begin
        for (i=0; i<40; i=i+1) begin
            instr = test_vector[i];
            if      (`OPCODE(instr) == `R      ) test_gold_vector[i] = {`R_CTRL         };
            else if (`OPCODE(instr) == `I_JUMP ) test_gold_vector[i] = {`I_JUMP_CTRL    };
            else if (`OPCODE(instr) == `I_LOAD ) test_gold_vector[i] = {`I_LOAD_CTRL    };
            else if (`OPCODE(instr) == `I_ARITH) test_gold_vector[i] = {`I_ARITH_CTRL   };
            else if (`OPCODE(instr) == `I_SYS  ) test_gold_vector[i] = {`I_SYS_CTRL     };
            else if (`OPCODE(instr) == `I_FENCE) test_gold_vector[i] = {`I_FENCE_CTRL   };
            else if (`OPCODE(instr) == `S      ) test_gold_vector[i] = {`S_CTRL         };
            else if (`OPCODE(instr) == `B      ) test_gold_vector[i] = {`B_CTRL         };
            else if (`OPCODE(instr) == `U_LUI  ) test_gold_vector[i] = {`U_LUI_CTRL     };
            else if (`OPCODE(instr) == `U_AUIPC) test_gold_vector[i] = {`U_AUIPC_CTRL   };
            else if (`OPCODE(instr) == `J      ) test_gold_vector[i] = {`J_CTRL         };
        end
    end


    reg     [39:0]  resultStr;
    reg     [12:0]  ctrlSignals;
    integer i = 0, errs = 0;
    initial begin
        $display("Running ControlUnit tests...\n");
        i_opcode   = 'd0;
        #20;
        for (i=0; i<40; i=i+1) begin
            instr       = test_vector[i];
            i_opcode    = `OPCODE(instr);
            #20;
            ctrlSignals = {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp};
            if (ctrlSignals != test_gold_vector[i]) resultStr = "ERROR";
            else                                    resultStr = "PASS ";
            $display("Test[ %2d ]: instr = 0x%8h || ctrlSigs = %b ... %s",
                i, instr, ctrlSignals, resultStr
            );
            if (resultStr == "ERROR") errs = errs + 1;
        end
        if (errs > 0)   $display("\nFAILED: %0d", errs);
        else            $display("\nPASSED");

    end

endmodule