data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v
1: b'%Error: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:51: Cannot find file containing module: \'vga_sync\'\n    vga_sync vga_sync_unit (.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/vga_sync\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/vga_sync.v\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/vga_sync.sv\n             vga_sync\n             vga_sync.v\n             vga_sync.sv\n             obj_dir/vga_sync\n             obj_dir/vga_sync.v\n             obj_dir/vga_sync.sv\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:69: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];\n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:69: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:69: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:69: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:70: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:70: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:70: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:70: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:71: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:71: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:71: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];\n                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:71: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:74: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:74: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:74: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:74: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:75: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:75: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:75: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:75: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:76: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:76: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:76: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/vga_test.v:76: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 10 bits.\n                                                                                                 : ... In instance vga_test\n            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];\n                          ^~\n%Error: Exiting due to 1 error(s), 24 warning(s)\n'
module vga_test #(
    parameter WIDTH = 640,
    parameter HEIGHT = 480
)
(
    input wire clk,
    input wire [11:0] sw,
    input wire btnU,
    input wire btnD,
    input wire btnL,
    input wire btnR,
    output wire hsync, vsync,
    output wire [11:0] rgb
);

    wire p_tick;
    wire [9:0] x, y;
	

	reg [11:0] rgb_reg;
    reg [11:0] first_color, second_color;
	

	wire video_on;
    reg reset;
    reg mode;


    vga_sync vga_sync_unit (.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
                            .video_on(video_on), .p_tick(p_tick), .x(x), .y(y));

    initial begin
        reset <= 0;
        mode <= 0;
        first_color <= 12'hFFF;
        second_color <= 12'h000;
    end

    always @(posedge clk) begin
        if(btnU) mode <= !mode;
        if(btnL) first_color <= sw;
        if(btnR) second_color <= sw;
    end

    always @(posedge p_tick) begin
        if(mode) begin
            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];
            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];
            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];
        end
        else begin
            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];
            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];
            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];
        end
    end
    

    assign rgb = (video_on) ? rgb_reg : 12'b0;
endmodule
module vga_test #(
    parameter WIDTH = 640,
    parameter HEIGHT = 480
)
(
    input wire clk,
    input wire [11:0] sw,
    input wire btnU,
    input wire btnD,
    input wire btnL,
    input wire btnR,
    output wire hsync, vsync,
    output wire [11:0] rgb
);


    wire p_tick;
    wire [9:0] x, y;
	

	reg [11:0] rgb_reg;
    reg [11:0] first_color, second_color;
	

	wire video_on;
    reg reset;
    reg mode;


    vga_sync vga_sync_unit (.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
                            .video_on(video_on), .p_tick(p_tick), .x(x), .y(y));

    initial begin
        reset <= 0;
        mode <= 0;
        first_color <= 12'hFFF;
        second_color <= 12'h000;
    end

    always @(posedge clk) begin
        if(btnU) mode <= !mode;
        if(btnL) first_color <= sw;
        if(btnR) second_color <= sw;
    end

    always @(posedge p_tick) begin
        if(mode) begin
            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (x / WIDTH)) + first_color[3:0];
            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (x / WIDTH)) + first_color[7:4];
            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (x / WIDTH)) + first_color[11:8];
        end
        else begin
            rgb_reg[3:0] <= ((second_color[3:0] - first_color[3:0]) * (y / HEIGHT)) + first_color[3:0];
            rgb_reg[7:4] <= ((second_color[7:4] - first_color[7:4]) * (y / HEIGHT)) + first_color[7:4];
            rgb_reg[11:8] <= ((second_color[11:8] - first_color[11:8]) * (y / HEIGHT)) + first_color[11:8];
        end
    end
    

    assign rgb = (video_on) ? rgb_reg : 12'b0;
endmodule