data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:9: Unsupported or unknown PLI call: $monitor\n  $monitor("%g a = %b b = %b c = %b", $time, a, b, c);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/test_tri.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_tri();

tri a;
reg b, c;

assign a = (b) ? c : 1'bz;

initial begin
  $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
  b  = 0;
  c  = 0;
  #1 b = 1;
  #1 b = 0;
  #1 c = 1;
  #1 b = 1;
  #1 b = 0;
  #1 $finish;
end

endmodule
module test_tri();


tri a;
reg b, c;

assign a = (b) ? c : 1'bz;

initial begin
  $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
  b  = 0;
  c  = 0;
  #1 b = 1;
  #1 b = 0;
  #1 c = 1;
  #1 b = 1;
  #1 b = 0;
  #1 $finish;
end

endmodule