data/full_repos/permissive/511535464/src/BranchJudge.v
data/verilator_xmls/a583d022-c96e-4449-8691-7254603c772b.xml
module BranchJudge(
    input wire [5:0] OpCode,
    input wire [31:0] data1_ID,
    input wire [31:0] data2_ID,
    input wire Branch,
    output reg Zero
);

    always@(*) begin
        if(Branch) begin
            if(OpCode == 6'h04) begin
                Zero <= data1_ID == data2_ID;
            end
            else if(OpCode == 6'h05) begin
                Zero <= data1_ID != data2_ID;
            end
            else if(OpCode == 6'h06) begin
                Zero <= (data1_ID <= data2_ID);
            end
            else if(OpCode == 6'h07) begin
                Zero <= (data1_ID > data2_ID);
            end
            else if(OpCode == 6'h01) begin
                Zero <= (data1_ID < data2_ID);
            end
            else begin
                Zero <= Zero;
            end
        end
        else begin
            Zero <= 0;
        end
    end

endmodule
module BranchJudge(
    input wire [5:0] OpCode,
    input wire [31:0] data1_ID,
    input wire [31:0] data2_ID,
    input wire Branch,
    output reg Zero
);


    always@(*) begin
        if(Branch) begin
            if(OpCode == 6'h04) begin
                Zero <= data1_ID == data2_ID;
            end
            else if(OpCode == 6'h05) begin
                Zero <= data1_ID != data2_ID;
            end
            else if(OpCode == 6'h06) begin
                Zero <= (data1_ID <= data2_ID);
            end
            else if(OpCode == 6'h07) begin
                Zero <= (data1_ID > data2_ID);
            end
            else if(OpCode == 6'h01) begin
                Zero <= (data1_ID < data2_ID);
            end
            else begin
                Zero <= Zero;
            end
        end
        else begin
            Zero <= 0;
        end
    end

endmodule