data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/alu.v:30: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                                                         : ... In instance alu\n default: {Cout,S}=A+B+Cin; \n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu(S,z,Cout,A,B,Cin,alu_ops);
output reg [31:0] S;
output z;
output reg Cout;
input [31:0] A;
input [31:0] B;
input Cin;
input [2:0] alu_ops;

assign z=~|S;

always @(A or B or alu_ops)
begin
	case (alu_ops)
	3'b001: {Cout,S}=A-B;
	3'b010: begin S=A|B; Cout=0; end
	3'b011: begin S=A&B; Cout=0; end
	3'b100: begin S=A^B; Cout=0; end
	3'b101: begin {Cout,S}=32'd0-A; end
	3'b110: begin S=~A; Cout=0; end
	3'b111: begin S=~B; Cout=0; end
	default: {Cout,S}=A+B+Cin;	
	endcase
end

endmodule
module alu(S,z,Cout,A,B,Cin,alu_ops);

output reg [31:0] S;
output z;
output reg Cout;
input [31:0] A;
input [31:0] B;
input Cin;
input [2:0] alu_ops;

assign z=~|S;

always @(A or B or alu_ops)
begin
	case (alu_ops)
	3'b001: {Cout,S}=A-B;
	3'b010: begin S=A|B; Cout=0; end
	3'b011: begin S=A&B; Cout=0; end
	3'b100: begin S=A^B; Cout=0; end
	3'b101: begin {Cout,S}=32'd0-A; end
	3'b110: begin S=~A; Cout=0; end
	3'b111: begin S=~B; Cout=0; end
	default: {Cout,S}=A+B+Cin;	
	endcase
end

endmodule