data/full_repos/permissive/529984920/src/pos_add.v
1: b'%Error: data/full_repos/permissive/529984920/src/pos_add.v:21: Unknown verilator comment: /*verilator split_var*/\n    wire [N_BITS-1:0] carry /*verilator split_var*/ ;\n                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/529984920/src/pos_add.v:22: Unknown verilator comment: /*verilator split_var*/\n    wire [N_BITS-1:1] sum_and_carry /*verilator split_var*/ ,\n                                    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module pos_add #(parameter N_BITS = 4) (a, b, c);


    input wire [N_BITS-1:0] a, b;
    output wire [N_BITS:0] c;
   

    wire [N_BITS-1:0] carry;
    wire [N_BITS-1:1] sum_and_carry,
                      a_and_b, sum;
   

    xor (c[0], a[0], b[0]);
    and (carry[0], a[0], b[0]);
   

    genvar i;
    generate
        for (i=1; i<N_BITS; i=i+1) begin


            xor(sum[i], a[i], b[i]);
            

            xor(c[i], sum[i], carry[i-1]);


            and(a_and_b[i], a[i], b[i]);
            and(sum_and_carry[i], sum[i], carry[i-1]);
            or(carry[i], a_and_b[i], sum_and_carry[i]);
        end
    endgenerate
    

    buf (c[N_BITS], carry[N_BITS-1]);

endmodule
module pos_add #(parameter N_BITS = 4) (a, b, c);



    input wire [N_BITS-1:0] a, b;
    output wire [N_BITS:0] c;
   

    wire [N_BITS-1:0] carry;
    wire [N_BITS-1:1] sum_and_carry,
                      a_and_b, sum;
   

    xor (c[0], a[0], b[0]);
    and (carry[0], a[0], b[0]);
   

    genvar i;
    generate
        for (i=1; i<N_BITS; i=i+1) begin


            xor(sum[i], a[i], b[i]);
            

            xor(c[i], sum[i], carry[i-1]);


            and(a_and_b[i], a[i], b[i]);
            and(sum_and_carry[i], sum[i], carry[i-1]);
            or(carry[i], a_and_b[i], sum_and_carry[i]);
        end
    endgenerate
    

    buf (c[N_BITS], carry[N_BITS-1]);

endmodule