data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:161: Signal definition not found, creating implicitly: \'cur_chk4mpa1maddr0_state\'\nassign spu_mald_done = cur_chk4mpa1maddr0_state & ~len_neqz;\n                       ^~~~~~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:166: Signal definition not found, creating implicitly: \'cur_idle_state\'\n                         (cur_idle_state & ~start_ldop));\n                          ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:163: Signal definition not found, creating implicitly: \'nxt_idle_state\'\n                                                                                               : ... Suggested alternative: \'cur_idle_state\'\nassign  nxt_idle_state = (\n        ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:175: Signal definition not found, creating implicitly: \'cur_ldreq_state\'\n                                                                                               : ... Suggested alternative: \'cur_idle_state\'\n                        (cur_ldreq_state & ~ldreq_ack));\n                         ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:172: Signal definition not found, creating implicitly: \'nxt_ldreq_state\'\n                                                                                               : ... Suggested alternative: \'cur_ldreq_state\'\nassign  nxt_ldreq_state = (\n        ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:177: Signal definition not found, creating implicitly: \'cur_mamemwr_state\'\n                                                                                               : ... Suggested alternative: \'cur_idle_state\'\nassign spu_mald_rstln = (cur_mamemwr_state & ld_inprog & len_neqz) | local_stxa_abort |\n                         ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:188: Signal definition not found, creating implicitly: \'cur_wait4ln_state\'\n                                                                                               : ... Suggested alternative: \'cur_idle_state\'\n                        (cur_wait4ln_state & ~ln_received));\n                         ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:186: Signal definition not found, creating implicitly: \'nxt_wait4ln_state\'\n                                                                                               : ... Suggested alternative: \'cur_wait4ln_state\'\nassign nxt_wait4ln_state = (\n       ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:207: Signal definition not found, creating implicitly: \'nxt_mamemwr_state\'\n                                                                                               : ... Suggested alternative: \'cur_mamemwr_state\'\nassign nxt_mamemwr_state = ( mald_memwen_dly );\n       ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:214: Signal definition not found, creating implicitly: \'nxt_chk4mpa1maddr0_state\'\n                                                                                               : ... Suggested alternative: \'cur_chk4mpa1maddr0_state\'\nassign nxt_chk4mpa1maddr0_state = (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:112: Cannot find file containing module: \'dffre_s\'\ndffre_s    #(1) spu_mald_done_ff (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffre_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffre_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffre_s.sv\n             dffre_s\n             dffre_s.v\n             dffre_s.sv\n             obj_dir/dffre_s\n             obj_dir/dffre_s.v\n             obj_dir/dffre_s.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:128: Cannot find file containing module: \'dff_s\'\ndff_s    #(1) idle_state_ff (\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:133: Cannot find file containing module: \'dffr_s\'\ndffr_s  #(1) ldreq_state_ff (\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:138: Cannot find file containing module: \'dffr_s\'\ndffr_s  #(1) wait4ln_state_ff (\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:143: Cannot find file containing module: \'dffr_s\'\ndffr_s  #(1) mamemwr_state_ff (\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:148: Cannot find file containing module: \'dffr_s\'\ndffr_s  #(1) chk4mpa1maddr0_state_ff (\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/spu_mald.v:201: Cannot find file containing module: \'dffr_s\'\ndffr_s    #(1) wen_dly_ff (\n^~~~~~\n%Error: Exiting due to 7 error(s), 10 warning(s)\n'
module spu_mald (


spu_mald_rstln,
spu_mald_maaddr_addrinc,
spu_mald_memwen,
spu_mald_mpa_addrinc,
spu_mald_ldreq,
spu_mald_done,
spu_mald_force_mpa_add16,

spu_mald_done_set,


ld_inprog,
ldreq_ack,
ln_received,
len_neqz,
mactl_ldop,
spu_maaddr_mpa1maddr0,
spu_mactl_iss_pulse_dly,

spu_wen_ma_unc_err_pulse,

spu_mactl_stxa_force_abort,

se,
reset,
rclk);


input reset;
input rclk;
input se;

input ld_inprog;
input ldreq_ack;
input ln_received;
input len_neqz;
input mactl_ldop;
input spu_maaddr_mpa1maddr0;
input spu_mactl_iss_pulse_dly;

input spu_wen_ma_unc_err_pulse;

input spu_mactl_stxa_force_abort;

output spu_mald_rstln;
output spu_mald_maaddr_addrinc;
output spu_mald_memwen;
output spu_mald_mpa_addrinc;

output spu_mald_ldreq;
output spu_mald_done;
output spu_mald_force_mpa_add16;

output spu_mald_done_set;



wire tr2wait4ln_frm_ldreq;



wire local_stxa_abort;



wire spu_mald_done_wen = (spu_mald_done | spu_wen_ma_unc_err_pulse | local_stxa_abort) & 
					mactl_ldop;
wire spu_mald_done_rst = reset | spu_mactl_iss_pulse_dly;

dffre_s    #(1) spu_mald_done_ff (
        .din(1'b1) , 
        .q(spu_mald_done_set),
        .en(spu_mald_done_wen),
        .rst(spu_mald_done_rst), .clk (rclk), .se(se), .si(), .so()); 







wire state_reset = reset | spu_mald_done | spu_wen_ma_unc_err_pulse |
					local_stxa_abort; 


dff_s    #(1) idle_state_ff (
        .din(nxt_idle_state) , 
        .q(cur_idle_state),
        .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) ldreq_state_ff (
        .din(nxt_ldreq_state) , 
        .q(cur_ldreq_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) wait4ln_state_ff (
        .din(nxt_wait4ln_state) , 
        .q(cur_wait4ln_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) mamemwr_state_ff (
        .din(nxt_mamemwr_state) , 
        .q(cur_mamemwr_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) chk4mpa1maddr0_state_ff (
        .din(nxt_chk4mpa1maddr0_state) , 
        .q(cur_chk4mpa1maddr0_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 




wire start_ldop = spu_mactl_iss_pulse_dly & mactl_ldop;




assign spu_mald_done = cur_chk4mpa1maddr0_state & ~len_neqz;

assign  nxt_idle_state = (
                         state_reset |
			 (spu_mald_done) |
                         (cur_idle_state & ~start_ldop));





assign  nxt_ldreq_state = (
			(cur_chk4mpa1maddr0_state & ~spu_maaddr_mpa1maddr0 & len_neqz) |
                        (cur_idle_state & start_ldop) |
                        (cur_ldreq_state & ~ldreq_ack));

assign spu_mald_rstln = (cur_mamemwr_state & ld_inprog & len_neqz) | local_stxa_abort |
						spu_wen_ma_unc_err_pulse;





assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack ;

assign nxt_wait4ln_state = (
                        (tr2wait4ln_frm_ldreq) |
                        (cur_wait4ln_state & ~ln_received));




wire tr2mamemwr_frm_wait4ln = cur_wait4ln_state & ln_received;
wire tr2mamemwr_frm_chk4mpa1maddr0 = cur_chk4mpa1maddr0_state & spu_maaddr_mpa1maddr0 & len_neqz;

wire mald_memwen = ( tr2mamemwr_frm_wait4ln |
		     tr2mamemwr_frm_chk4mpa1maddr0) & len_neqz;


wire mald_memwen_dly;
dffr_s    #(1) wen_dly_ff (
        .din(mald_memwen) ,
        .q(mald_memwen_dly),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so());


assign nxt_mamemwr_state = ( mald_memwen_dly );

assign local_stxa_abort = mald_memwen_dly & spu_mactl_stxa_force_abort;




assign nxt_chk4mpa1maddr0_state = (
                        (cur_mamemwr_state) );





assign spu_mald_memwen = nxt_mamemwr_state;

assign spu_mald_maaddr_addrinc = cur_mamemwr_state;

assign spu_mald_mpa_addrinc = cur_mamemwr_state ;

assign spu_mald_force_mpa_add16 = 1'b0 ;

assign spu_mald_ldreq = cur_ldreq_state ;



endmodule
module spu_mald (


spu_mald_rstln,
spu_mald_maaddr_addrinc,
spu_mald_memwen,
spu_mald_mpa_addrinc,
spu_mald_ldreq,
spu_mald_done,
spu_mald_force_mpa_add16,

spu_mald_done_set,


ld_inprog,
ldreq_ack,
ln_received,
len_neqz,
mactl_ldop,
spu_maaddr_mpa1maddr0,
spu_mactl_iss_pulse_dly,

spu_wen_ma_unc_err_pulse,

spu_mactl_stxa_force_abort,

se,
reset,
rclk);



input reset;
input rclk;
input se;

input ld_inprog;
input ldreq_ack;
input ln_received;
input len_neqz;
input mactl_ldop;
input spu_maaddr_mpa1maddr0;
input spu_mactl_iss_pulse_dly;

input spu_wen_ma_unc_err_pulse;

input spu_mactl_stxa_force_abort;

output spu_mald_rstln;
output spu_mald_maaddr_addrinc;
output spu_mald_memwen;
output spu_mald_mpa_addrinc;

output spu_mald_ldreq;
output spu_mald_done;
output spu_mald_force_mpa_add16;

output spu_mald_done_set;



wire tr2wait4ln_frm_ldreq;



wire local_stxa_abort;



wire spu_mald_done_wen = (spu_mald_done | spu_wen_ma_unc_err_pulse | local_stxa_abort) & 
					mactl_ldop;
wire spu_mald_done_rst = reset | spu_mactl_iss_pulse_dly;

dffre_s    #(1) spu_mald_done_ff (
        .din(1'b1) , 
        .q(spu_mald_done_set),
        .en(spu_mald_done_wen),
        .rst(spu_mald_done_rst), .clk (rclk), .se(se), .si(), .so()); 







wire state_reset = reset | spu_mald_done | spu_wen_ma_unc_err_pulse |
					local_stxa_abort; 


dff_s    #(1) idle_state_ff (
        .din(nxt_idle_state) , 
        .q(cur_idle_state),
        .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) ldreq_state_ff (
        .din(nxt_ldreq_state) , 
        .q(cur_ldreq_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) wait4ln_state_ff (
        .din(nxt_wait4ln_state) , 
        .q(cur_wait4ln_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) mamemwr_state_ff (
        .din(nxt_mamemwr_state) , 
        .q(cur_mamemwr_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 

dffr_s  #(1) chk4mpa1maddr0_state_ff (
        .din(nxt_chk4mpa1maddr0_state) , 
        .q(cur_chk4mpa1maddr0_state),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so()); 




wire start_ldop = spu_mactl_iss_pulse_dly & mactl_ldop;




assign spu_mald_done = cur_chk4mpa1maddr0_state & ~len_neqz;

assign  nxt_idle_state = (
                         state_reset |
			 (spu_mald_done) |
                         (cur_idle_state & ~start_ldop));





assign  nxt_ldreq_state = (
			(cur_chk4mpa1maddr0_state & ~spu_maaddr_mpa1maddr0 & len_neqz) |
                        (cur_idle_state & start_ldop) |
                        (cur_ldreq_state & ~ldreq_ack));

assign spu_mald_rstln = (cur_mamemwr_state & ld_inprog & len_neqz) | local_stxa_abort |
						spu_wen_ma_unc_err_pulse;





assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack ;

assign nxt_wait4ln_state = (
                        (tr2wait4ln_frm_ldreq) |
                        (cur_wait4ln_state & ~ln_received));




wire tr2mamemwr_frm_wait4ln = cur_wait4ln_state & ln_received;
wire tr2mamemwr_frm_chk4mpa1maddr0 = cur_chk4mpa1maddr0_state & spu_maaddr_mpa1maddr0 & len_neqz;

wire mald_memwen = ( tr2mamemwr_frm_wait4ln |
		     tr2mamemwr_frm_chk4mpa1maddr0) & len_neqz;


wire mald_memwen_dly;
dffr_s    #(1) wen_dly_ff (
        .din(mald_memwen) ,
        .q(mald_memwen_dly),
        .rst(state_reset), .clk (rclk), .se(se), .si(), .so());


assign nxt_mamemwr_state = ( mald_memwen_dly );

assign local_stxa_abort = mald_memwen_dly & spu_mactl_stxa_force_abort;




assign nxt_chk4mpa1maddr0_state = (
                        (cur_mamemwr_state) );





assign spu_mald_memwen = nxt_mamemwr_state;

assign spu_mald_maaddr_addrinc = cur_mamemwr_state;

assign spu_mald_mpa_addrinc = cur_mamemwr_state ;

assign spu_mald_force_mpa_add16 = 1'b0 ;

assign spu_mald_ldreq = cur_ldreq_state ;



endmodule