data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module mysrlatch (
  output reg Q
, input      clk
, input      H
, input      L
, input      rst
);

  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Q = 1'b0;
    else if( H == 1'b1 )
      Q = 1'b1;
    else if( L == 1'b1 )
      Q = 1'b0;
    else
      Q = Q;

endmodule
module mysrlatch (
  output reg Q
, input      clk
, input      H
, input      L
, input      rst
);


  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      Q = 1'b0;
    else if( H == 1'b1 )
      Q = 1'b1;
    else if( L == 1'b1 )
      Q = 1'b0;
    else
      Q = Q;

endmodule