data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/Xnorgate.v
data/verilator_xmls/45dd7240-1190-4b62-945e-253014d7e2fe.xml
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a ^ b);


endmodule
module top_module( 
    input a, 
    input b, 
    output out );


    assign out = ~(a ^ b);


endmodule