data/full_repos/permissive/514437299/digital/rtl/servant_top.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:79: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  wire [MAX_RANDBITS_LEN-1:0] i_msk_randbits,\n              ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:80: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  wire [XTR_RANDBITS_LEN-1:0] i_xtr_randbits,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:243: Little bit endian vector: MSB < LSB of bit range: -1:0\n  wire [CMO_RANDBITS_LEN-1:0] msk_randbits_cmo;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:244: Little bit endian vector: MSB < LSB of bit range: -1:0\n  wire [DLO_RANDBITS_LEN-1:0] msk_randbits_dlo;\n       ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:328: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign cmo_rf_rdata_enc      = cmo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:329: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign cmo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:330: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:330: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:331: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:331: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:335: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign dlo_rf_rdata_enc      = dlo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:336: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign dlo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:337: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:337: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:338: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:338: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:341: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_CMO(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant.sv\n             servant\n             servant.v\n             servant.sv\n             obj_dir/servant\n             obj_dir/servant.v\n             obj_dir/servant.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:374: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_DLO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:437: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_PLN(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:454: Cannot find file containing module: \'mux\'\n  mux U_MUX(\n  ^~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:562: Cannot find file containing module: \'ram\'\n  ram U_RAM(\n  ^~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:573: Cannot find file containing module: \'rf\'\n  rf U_RF(\n  ^~\n%Error: Exiting due to 18 error(s), 4 warning(s)\n'
module servant_top #(parameter CMO_RANDBITS_LEN = 0,
                     parameter DLO_RANDBITS_LEN = 0,
                     parameter MAX_RANDBITS_LEN = 0,
                     parameter XTR_RANDBITS_LEN = 0) (
  input  wire                        clk_mem,
  input  wire                        clk_cmo,
  input  wire                        clk_dlo,
  input  wire                        clk_pch,
  input  wire                        clk_pln,
  input  wire                        rst_n,
  input  wire                        i_clk_cmo_en,
  input  wire                        i_clk_dlo_en,
  input  wire                        i_clk_pln_en,
  input  wire [MAX_RANDBITS_LEN-1:0] i_msk_randbits,
  input  wire [XTR_RANDBITS_LEN-1:0] i_xtr_randbits,
  input  wire [31:0]                 i_key_enc_ram,
  input  wire [1:0]                  i_key_enc_rf,
  input  wire [31:0]                 i_key_scr_ram,
  input  wire [8:0]                  i_key_scr_rf,
  input  wire [8:0]                  i_tst_rf_addr,
  input  wire [1:0]                  i_tst_rf_wdat,
  input  wire                        i_tst_rf_we,
  output wire [1:0]                  o_tst_rf_rdata,
  input  wire [9:0]                  i_tst_ram_adr,
  input  wire                        i_tst_ram_cyc,
  input  wire                        i_tst_ram_we,
  input  wire [3:0]                  i_tst_ram_sel,
  input  wire [31:0]                 i_tst_ram_dat,
  output wire [31:0]                 o_tst_ram_rdt,
  output wire                        o_tst_ram_ack,
  output wire [1:0]                  o_q);

  wire [1:0]  cmo_q;
  wire [1:0]  dlo_q;
  wire [1:0]  pln_q;

`ifndef RTL
  wire [1:0]  cmo_q_s1;
  wire [1:0]  dlo_q_s1;
`endif

  wire [8:0]  cmo_rf_waddr_scr;
  wire [8:0]  cmo_rf_raddr_scr;
  wire [31:0] cmo_wb_mem_adr_scr;

  wire [1:0]  cmo_rf_wdata_enc;
  wire [1:0]  cmo_rf_rdata_enc;
  wire [31:0] cmo_wb_mem_dat_enc;
  wire [31:0] cmo_wb_mem_rdt_enc;

  wire [8:0]  dlo_rf_waddr_scr;
  wire [8:0]  dlo_rf_raddr_scr;
  wire [31:0] dlo_wb_mem_adr_scr;

  wire [1:0]  dlo_rf_wdata_enc;
  wire [1:0]  dlo_rf_rdata_enc;
  wire [31:0] dlo_wb_mem_dat_enc;
  wire [31:0] dlo_wb_mem_rdt_enc;

`ifndef RTL
  wire [8:0]  cmo_rf_waddr_scr_s1;
  wire [8:0]  cmo_rf_raddr_scr_s1;
  wire [31:0] cmo_wb_mem_adr_scr_s1;

  wire [1:0]  cmo_rf_wdata_enc_s1;
  wire [1:0]  cmo_rf_rdata_enc_s1;
  wire [31:0] cmo_wb_mem_dat_enc_s1;
  wire [31:0] cmo_wb_mem_rdt_enc_s1;

  wire [8:0]  dlo_rf_waddr_scr_s1;
  wire [8:0]  dlo_rf_raddr_scr_s1;
  wire [31:0] dlo_wb_mem_adr_scr_s1;

  wire [1:0]  dlo_rf_wdata_enc_s1;
  wire [1:0]  dlo_rf_rdata_enc_s1;
  wire [31:0] dlo_wb_mem_dat_enc_s1;
  wire [31:0] dlo_wb_mem_rdt_enc_s1;
`endif

  wire [31:0] cmo_wb_mem_adr;
  wire        cmo_wb_mem_cyc;
  wire        cmo_wb_mem_we;
  wire [3:0]  cmo_wb_mem_sel;
  wire [31:0] cmo_wb_mem_dat;
  wire [31:0] cmo_wb_mem_rdt;
  wire        cmo_wb_mem_ack;

  wire [31:0] dlo_wb_mem_adr;
  wire        dlo_wb_mem_cyc;
  wire        dlo_wb_mem_we;
  wire [3:0]  dlo_wb_mem_sel;
  wire [31:0] dlo_wb_mem_dat;
  wire [31:0] dlo_wb_mem_rdt;
  wire        dlo_wb_mem_ack;

`ifndef RTL
  wire [31:0] cmo_wb_mem_adr_s1;
  wire        cmo_wb_mem_cyc_s1;
  wire        cmo_wb_mem_we_s1;
  wire [3:0]  cmo_wb_mem_sel_s1;
  wire [31:0] cmo_wb_mem_dat_s1;
  wire [31:0] cmo_wb_mem_rdt_s1;
  wire        cmo_wb_mem_ack_s1;

  wire [31:0] dlo_wb_mem_adr_s1;
  wire        dlo_wb_mem_cyc_s1;
  wire        dlo_wb_mem_we_s1;
  wire [3:0]  dlo_wb_mem_sel_s1;
  wire [31:0] dlo_wb_mem_dat_s1;
  wire [31:0] dlo_wb_mem_rdt_s1;
  wire        dlo_wb_mem_ack_s1;
`endif

  wire [31:0] pln_wb_mem_adr;
  wire        pln_wb_mem_cyc;
  wire        pln_wb_mem_we;
  wire [3:0]  pln_wb_mem_sel;
  wire [31:0] pln_wb_mem_dat;
  wire [31:0] pln_wb_mem_rdt;
  wire        pln_wb_mem_ack;

  wire [8:0] cmo_rf_waddr;
  wire [1:0] cmo_rf_wdata;
  wire       cmo_rf_wen;
  wire [8:0] cmo_rf_raddr;
  wire [1:0] cmo_rf_rdata;

  wire [8:0] dlo_rf_waddr;
  wire [1:0] dlo_rf_wdata;
  wire       dlo_rf_wen;
  wire [8:0] dlo_rf_raddr;
  wire [1:0] dlo_rf_rdata;

`ifndef RTL
  wire [8:0] cmo_rf_waddr_s1;
  wire [1:0] cmo_rf_wdata_s1;
  wire       cmo_rf_wen_s1;
  wire [8:0] cmo_rf_raddr_s1;
  wire [1:0] cmo_rf_rdata_s1;

  wire [8:0] dlo_rf_waddr_s1;
  wire [1:0] dlo_rf_wdata_s1;
  wire       dlo_rf_wen_s1;
  wire [8:0] dlo_rf_raddr_s1;
  wire [1:0] dlo_rf_rdata_s1;
`endif

  wire [8:0] pln_rf_waddr;
  wire [1:0] pln_rf_wdata;
  wire       pln_rf_wen;
  wire [8:0] pln_rf_raddr;
  wire [1:0] pln_rf_rdata;

  wire [8:0] rf_waddr;
  wire [1:0] rf_wdata;
  wire       rf_wen;
  wire [8:0] rf_raddr;
  wire [1:0] rf_rdata;

  wire [9:0]  wb_mem_adr;
  wire        wb_mem_cyc;
  wire        wb_mem_we;
  wire [3:0]  wb_mem_sel;
  wire [31:0] wb_mem_dat;
  wire [31:0] wb_mem_rdt;
  wire        wb_mem_ack;

`ifndef RTL
  wire [1:0]  cmo_rf_rdata_enc_nsh;
  wire [31:0] cmo_wb_mem_rdt_enc_nsh;
  wire        cmo_wb_mem_ack_nsh;

  wire [1:0]  dlo_rf_rdata_enc_nsh;
  wire [31:0] dlo_wb_mem_rdt_enc_nsh;
  wire        dlo_wb_mem_ack_nsh;
`endif

  wire [CMO_RANDBITS_LEN-1:0] msk_randbits_cmo;
  wire [DLO_RANDBITS_LEN-1:0] msk_randbits_dlo;

  assign msk_randbits_cmo = i_msk_randbits[CMO_RANDBITS_LEN-1:0];
  assign msk_randbits_dlo = i_msk_randbits[DLO_RANDBITS_LEN-1:0];

  sec U_SEC_CMO(
    .i_key_enc_rf        ( i_key_enc_rf          ) ,
    .i_key_enc_ram       ( i_key_enc_ram         ) ,
    .i_key_scr_rf        ( i_key_scr_rf          ) ,
    .i_key_scr_ram       ( i_key_scr_ram         ) ,
`ifndef RTL
    .i_rf_waddr_s1       ( cmo_rf_waddr_s1       ) ,
    .i_rf_raddr_s1       ( cmo_rf_raddr_s1       ) ,
    .i_rf_wdata_s1       ( cmo_rf_wdata_s1       ) ,
    .i_rf_rdata_enc_s1   ( cmo_rf_rdata_enc_s1   ) ,
    .o_rf_waddr_scr_s1   ( cmo_rf_waddr_scr_s1   ) ,
    .o_rf_raddr_scr_s1   ( cmo_rf_raddr_scr_s1   ) ,
    .o_rf_wdata_enc_s1   ( cmo_rf_wdata_enc_s1   ) ,
    .o_rf_rdata_s1       ( cmo_rf_rdata_s1       ) ,
    .i_wb_mem_adr_s1     ( cmo_wb_mem_adr_s1     ) ,
    .i_wb_mem_dat_s1     ( cmo_wb_mem_dat_s1     ) ,
    .i_wb_mem_rdt_enc_s1 ( cmo_wb_mem_rdt_enc_s1 ) ,
    .o_wb_mem_adr_scr_s1 ( cmo_wb_mem_adr_scr_s1 ) ,
    .o_wb_mem_dat_enc_s1 ( cmo_wb_mem_dat_enc_s1 ) ,
    .o_wb_mem_rdt_s1     ( cmo_wb_mem_rdt_s1     ) ,
`endif
    .i_rf_waddr          ( cmo_rf_waddr          ) ,
    .i_rf_raddr          ( cmo_rf_raddr          ) ,
    .i_rf_wdata          ( cmo_rf_wdata          ) ,
    .i_rf_rdata_enc      ( cmo_rf_rdata_enc      ) ,
    .o_rf_waddr_scr      ( cmo_rf_waddr_scr      ) ,
    .o_rf_raddr_scr      ( cmo_rf_raddr_scr      ) ,
    .o_rf_wdata_enc      ( cmo_rf_wdata_enc      ) ,
    .o_rf_rdata          ( cmo_rf_rdata          ) ,
    .i_wb_mem_adr        ( cmo_wb_mem_adr        ) ,
    .i_wb_mem_dat        ( cmo_wb_mem_dat        ) ,
    .i_wb_mem_rdt_enc    ( cmo_wb_mem_rdt_enc    ) ,
    .o_wb_mem_adr_scr    ( cmo_wb_mem_adr_scr    ) ,
    .o_wb_mem_dat_enc    ( cmo_wb_mem_dat_enc    ) ,
    .o_wb_mem_rdt        ( cmo_wb_mem_rdt        ) );

  sec U_SEC_DLO(
    .i_key_enc_rf        ( i_key_enc_rf          ) ,
    .i_key_enc_ram       ( i_key_enc_ram         ) ,
    .i_key_scr_rf        ( i_key_scr_rf          ) ,
    .i_key_scr_ram       ( i_key_scr_ram         ) ,
`ifndef RTL
    .i_rf_waddr_s1       ( dlo_rf_waddr_s1       ) ,
    .i_rf_raddr_s1       ( dlo_rf_raddr_s1       ) ,
    .i_rf_wdata_s1       ( dlo_rf_wdata_s1       ) ,
    .i_rf_rdata_enc_s1   ( dlo_rf_rdata_enc_s1   ) ,
    .o_rf_waddr_scr_s1   ( dlo_rf_waddr_scr_s1   ) ,
    .o_rf_raddr_scr_s1   ( dlo_rf_raddr_scr_s1   ) ,
    .o_rf_wdata_enc_s1   ( dlo_rf_wdata_enc_s1   ) ,
    .o_rf_rdata_s1       ( dlo_rf_rdata_s1       ) ,
    .i_wb_mem_adr_s1     ( dlo_wb_mem_adr_s1     ) ,
    .i_wb_mem_dat_s1     ( dlo_wb_mem_dat_s1     ) ,
    .i_wb_mem_rdt_enc_s1 ( dlo_wb_mem_rdt_enc_s1 ) ,
    .o_wb_mem_adr_scr_s1 ( dlo_wb_mem_adr_scr_s1 ) ,
    .o_wb_mem_dat_enc_s1 ( dlo_wb_mem_dat_enc_s1 ) ,
    .o_wb_mem_rdt_s1     ( dlo_wb_mem_rdt_s1     ) ,
`endif
    .i_rf_waddr          ( dlo_rf_waddr          ) ,
    .i_rf_raddr          ( dlo_rf_raddr          ) ,
    .i_rf_wdata          ( dlo_rf_wdata          ) ,
    .i_rf_rdata_enc      ( dlo_rf_rdata_enc      ) ,
    .o_rf_waddr_scr      ( dlo_rf_waddr_scr      ) ,
    .o_rf_raddr_scr      ( dlo_rf_raddr_scr      ) ,
    .o_rf_wdata_enc      ( dlo_rf_wdata_enc      ) ,
    .o_rf_rdata          ( dlo_rf_rdata          ) ,
    .i_wb_mem_adr        ( dlo_wb_mem_adr        ) ,
    .i_wb_mem_dat        ( dlo_wb_mem_dat        ) ,
    .i_wb_mem_rdt_enc    ( dlo_wb_mem_rdt_enc    ) ,
    .o_wb_mem_adr_scr    ( dlo_wb_mem_adr_scr    ) ,
    .o_wb_mem_dat_enc    ( dlo_wb_mem_dat_enc    ) ,
    .o_wb_mem_rdt        ( dlo_wb_mem_rdt        ) );

`ifndef RTL

  assign cmo_wb_mem_ack        = cmo_wb_mem_ack_nsh      ^ i_xtr_randbits[1];
  assign cmo_wb_mem_ack_s1     =                           i_xtr_randbits[1];
  assign cmo_rf_rdata_enc      = cmo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];
  assign cmo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];
  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];
  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];

  assign dlo_wb_mem_ack        = dlo_wb_mem_ack_nsh      ^ i_xtr_randbits[1];
  assign dlo_wb_mem_ack_s1     =                           i_xtr_randbits[1];
  assign dlo_rf_rdata_enc      = dlo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];
  assign dlo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];
  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];
  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];
`endif

  servant U_SERVANT_CMO(
    .clk             ( clk_cmo           ) ,
    .rst_n           ( rst_n             ) ,
`ifndef RTL
    .randbits        ( msk_randbits_cmo  ) ,
    .o_q_s1          ( cmo_q_s1          ) ,
    .o_rf_waddr_s1   ( cmo_rf_waddr_s1   ) ,
    .o_rf_wdata_s1   ( cmo_rf_wdata_s1   ) ,
    .o_rf_wen_s1     ( cmo_rf_wen_s1     ) ,
    .o_rf_raddr_s1   ( cmo_rf_raddr_s1   ) ,
    .i_rf_rdata_s1   ( cmo_rf_rdata_s1   ) ,
    .o_wb_mem_adr_s1 ( cmo_wb_mem_adr_s1 ) ,
    .o_wb_mem_cyc_s1 ( cmo_wb_mem_cyc_s1 ) ,
    .o_wb_mem_we_s1  ( cmo_wb_mem_we_s1  ) ,
    .o_wb_mem_sel_s1 ( cmo_wb_mem_sel_s1 ) ,
    .o_wb_mem_dat_s1 ( cmo_wb_mem_dat_s1 ) ,
    .i_wb_mem_rdt_s1 ( cmo_wb_mem_rdt_s1 ) ,
    .i_wb_mem_ack_s1 ( cmo_wb_mem_ack_s1 ) ,
`endif
    .o_q             ( cmo_q             ) ,
    .o_rf_waddr      ( cmo_rf_waddr      ) ,
    .o_rf_wdata      ( cmo_rf_wdata      ) ,
    .o_rf_wen        ( cmo_rf_wen        ) ,
    .o_rf_raddr      ( cmo_rf_raddr      ) ,
    .i_rf_rdata      ( cmo_rf_rdata      ) ,
    .o_wb_mem_adr    ( cmo_wb_mem_adr    ) ,
    .o_wb_mem_cyc    ( cmo_wb_mem_cyc    ) ,
    .o_wb_mem_we     ( cmo_wb_mem_we     ) ,
    .o_wb_mem_sel    ( cmo_wb_mem_sel    ) ,
    .o_wb_mem_dat    ( cmo_wb_mem_dat    ) ,
    .i_wb_mem_rdt    ( cmo_wb_mem_rdt    ) ,
    .i_wb_mem_ack    ( cmo_wb_mem_ack    ) );

  servant U_SERVANT_DLO(
    .clk                 ( clk_dlo            ) ,
    .rst_n               ( rst_n              ) ,
`ifndef RTL
    .randbits            ( msk_randbits_dlo   ) ,
    .clk_pch             ( clk_pch            ) ,

    .o_q_not             (                    ) ,
    .o_rf_waddr_not      (                    ) ,
    .o_rf_wdata_not      (                    ) ,
    .o_rf_wen_not        (                    ) ,
    .o_rf_raddr_not      (                    ) ,
    .i_rf_rdata_not      ( ~dlo_rf_rdata      ) ,
    .o_wb_mem_adr_not    (                    ) ,
    .o_wb_mem_cyc_not    (                    ) ,
    .o_wb_mem_we_not     (                    ) ,
    .o_wb_mem_sel_not    (                    ) ,
    .o_wb_mem_dat_not    (                    ) ,
    .i_wb_mem_rdt_not    ( ~dlo_wb_mem_rdt    ) ,
    .i_wb_mem_ack_not    ( ~dlo_wb_mem_ack    ) ,

    .o_q_s1              ( dlo_q_s1           ) ,
    .o_rf_waddr_s1       ( dlo_rf_waddr_s1    ) ,
    .o_rf_wdata_s1       ( dlo_rf_wdata_s1    ) ,
    .o_rf_wen_s1         ( dlo_rf_wen_s1      ) ,
    .o_rf_raddr_s1       ( dlo_rf_raddr_s1    ) ,
    .i_rf_rdata_s1       ( dlo_rf_rdata_s1    ) ,
    .o_wb_mem_adr_s1     ( dlo_wb_mem_adr_s1  ) ,
    .o_wb_mem_cyc_s1     ( dlo_wb_mem_cyc_s1  ) ,
    .o_wb_mem_we_s1      ( dlo_wb_mem_we_s1   ) ,
    .o_wb_mem_sel_s1     ( dlo_wb_mem_sel_s1  ) ,
    .o_wb_mem_dat_s1     ( dlo_wb_mem_dat_s1  ) ,
    .i_wb_mem_rdt_s1     ( dlo_wb_mem_rdt_s1  ) ,
    .i_wb_mem_ack_s1     ( dlo_wb_mem_ack_s1  ) ,

    .o_q_s1_not          (                    ) ,
    .o_rf_waddr_s1_not   (                    ) ,
    .o_rf_wdata_s1_not   (                    ) ,
    .o_rf_wen_s1_not     (                    ) ,
    .o_rf_raddr_s1_not   (                    ) ,
    .i_rf_rdata_s1_not   ( ~dlo_rf_rdata_s1   ) ,
    .o_wb_mem_adr_s1_not (                    ) ,
    .o_wb_mem_cyc_s1_not (                    ) ,
    .o_wb_mem_we_s1_not  (                    ) ,
    .o_wb_mem_sel_s1_not (                    ) ,
    .o_wb_mem_dat_s1_not (                    ) ,
    .i_wb_mem_rdt_s1_not ( ~dlo_wb_mem_rdt_s1 ) ,
    .i_wb_mem_ack_s1_not ( ~dlo_wb_mem_ack_s1 ) ,
`endif
    .o_q                 ( dlo_q              ) ,
    .o_rf_waddr          ( dlo_rf_waddr       ) ,
    .o_rf_wdata          ( dlo_rf_wdata       ) ,
    .o_rf_wen            ( dlo_rf_wen         ) ,
    .o_rf_raddr          ( dlo_rf_raddr       ) ,
    .i_rf_rdata          ( dlo_rf_rdata       ) ,
    .o_wb_mem_adr        ( dlo_wb_mem_adr     ) ,
    .o_wb_mem_cyc        ( dlo_wb_mem_cyc     ) ,
    .o_wb_mem_we         ( dlo_wb_mem_we      ) ,
    .o_wb_mem_sel        ( dlo_wb_mem_sel     ) ,
    .o_wb_mem_dat        ( dlo_wb_mem_dat     ) ,
    .i_wb_mem_rdt        ( dlo_wb_mem_rdt     ) ,
    .i_wb_mem_ack        ( dlo_wb_mem_ack     ) );

  servant U_SERVANT_PLN(
    .clk          ( clk_pln          ) ,
    .rst_n        ( rst_n            ) ,
    .o_rf_waddr   ( pln_rf_waddr     ) ,
    .o_rf_wdata   ( pln_rf_wdata     ) ,
    .o_rf_wen     ( pln_rf_wen       ) ,
    .o_rf_raddr   ( pln_rf_raddr     ) ,
    .i_rf_rdata   ( pln_rf_rdata     ) ,
    .o_wb_mem_adr ( pln_wb_mem_adr   ) ,
    .o_wb_mem_cyc ( pln_wb_mem_cyc   ) ,
    .o_wb_mem_we  ( pln_wb_mem_we    ) ,
    .o_wb_mem_sel ( pln_wb_mem_sel   ) ,
    .o_wb_mem_dat ( pln_wb_mem_dat   ) ,
    .i_wb_mem_rdt ( pln_wb_mem_rdt   ) ,
    .i_wb_mem_ack ( pln_wb_mem_ack   ) ,
    .o_q          ( pln_q            ) );

  mux U_MUX(
    .i_clk_cmo_en     ( i_clk_cmo_en                                             ) ,
    .i_clk_dlo_en     ( i_clk_dlo_en                                             ) ,
    .i_clk_pln_en     ( i_clk_pln_en                                             ) ,

    .i_tst_rf_addr    ( i_tst_rf_addr                                            ) ,
    .i_tst_rf_wdat    ( i_tst_rf_wdat                                            ) ,
    .i_tst_rf_we      ( i_tst_rf_we                                              ) ,
    .o_tst_rf_rdata   ( o_tst_rf_rdata                                           ) ,
    .i_tst_ram_adr    ( i_tst_ram_adr                                            ) ,
    .i_tst_ram_cyc    ( i_tst_ram_cyc                                            ) ,
    .i_tst_ram_we     ( i_tst_ram_we                                             ) ,
    .i_tst_ram_sel    ( i_tst_ram_sel                                            ) ,
    .i_tst_ram_dat    ( i_tst_ram_dat                                            ) ,
    .o_tst_ram_rdt    ( o_tst_ram_rdt                                            ) ,
    .o_tst_ram_ack    ( o_tst_ram_ack                                            ) ,

`ifdef RTL
    .i_cmo_q          ( cmo_q                                                    ) ,
    .i_cmo_rf_waddr   ( cmo_rf_waddr_scr                                         ) ,
    .i_cmo_rf_wdata   ( cmo_rf_wdata_enc                                         ) ,
    .i_cmo_rf_wen     ( cmo_rf_wen                                               ) ,
    .i_cmo_rf_raddr   ( cmo_rf_raddr_scr                                         ) ,
    .o_cmo_rf_rdata   ( cmo_rf_rdata_enc                                         ) ,
    .i_cmo_wb_mem_adr ( cmo_wb_mem_adr_scr[11:2]                                 ) ,
    .i_cmo_wb_mem_cyc ( cmo_wb_mem_cyc                                           ) ,
    .i_cmo_wb_mem_we  ( cmo_wb_mem_we                                            ) ,
    .i_cmo_wb_mem_sel ( cmo_wb_mem_sel                                           ) ,
    .i_cmo_wb_mem_dat ( cmo_wb_mem_dat_enc                                       ) ,
    .o_cmo_wb_mem_rdt ( cmo_wb_mem_rdt_enc                                       ) ,
    .o_cmo_wb_mem_ack ( cmo_wb_mem_ack                                           ) ,
`else
    .i_cmo_q          ( cmo_q_s1                    ^ cmo_q                      ) ,
    .i_cmo_rf_waddr   ( cmo_rf_waddr_scr_s1         ^ cmo_rf_waddr_scr           ) ,
    .i_cmo_rf_wdata   ( cmo_rf_wdata_enc_s1         ^ cmo_rf_wdata_enc           ) ,
    .i_cmo_rf_wen     ( cmo_rf_wen_s1               ^ cmo_rf_wen                 ) ,
    .i_cmo_rf_raddr   ( cmo_rf_raddr_scr_s1         ^ cmo_rf_raddr_scr           ) ,
    .o_cmo_rf_rdata   ( cmo_rf_rdata_enc_nsh                                     ) ,
    .i_cmo_wb_mem_adr ( cmo_wb_mem_adr_scr_s1[11:2] ^ cmo_wb_mem_adr_scr[11:2]   ) ,
    .i_cmo_wb_mem_cyc ( cmo_wb_mem_cyc_s1           ^ cmo_wb_mem_cyc             ) ,
    .i_cmo_wb_mem_we  ( cmo_wb_mem_we_s1            ^ cmo_wb_mem_we              ) ,
    .i_cmo_wb_mem_sel ( cmo_wb_mem_sel_s1           ^ cmo_wb_mem_sel             ) ,
    .i_cmo_wb_mem_dat ( cmo_wb_mem_dat_enc_s1       ^ cmo_wb_mem_dat_enc         ) ,
    .o_cmo_wb_mem_rdt ( cmo_wb_mem_rdt_enc_nsh                                   ) ,
    .o_cmo_wb_mem_ack ( cmo_wb_mem_ack_nsh                                       ) ,
`endif

`ifdef RTL
    .i_dlo_q          ( dlo_q                                                    ) ,
    .i_dlo_rf_waddr   ( dlo_rf_waddr_scr                                         ) ,
    .i_dlo_rf_wdata   ( dlo_rf_wdata_enc                                         ) ,
    .i_dlo_rf_wen     ( dlo_rf_wen                                               ) ,
    .i_dlo_rf_raddr   ( dlo_rf_raddr_scr                                         ) ,
    .o_dlo_rf_rdata   ( dlo_rf_rdata_enc                                         ) ,
    .i_dlo_wb_mem_adr ( dlo_wb_mem_adr_scr[11:2]                                 ) ,
    .i_dlo_wb_mem_cyc ( dlo_wb_mem_cyc                                           ) ,
    .i_dlo_wb_mem_we  ( dlo_wb_mem_we                                            ) ,
    .i_dlo_wb_mem_sel ( dlo_wb_mem_sel                                           ) ,
    .i_dlo_wb_mem_dat ( dlo_wb_mem_dat_enc                                       ) ,
    .o_dlo_wb_mem_rdt ( dlo_wb_mem_rdt_enc                                       ) ,
    .o_dlo_wb_mem_ack ( dlo_wb_mem_ack                                           ) ,
`else
    .i_dlo_q          (   dlo_q_s1                    ^ dlo_q                    ) ,
    .i_dlo_rf_waddr   (   dlo_rf_waddr_scr_s1         ^ dlo_rf_waddr_scr         ) ,
    .i_dlo_rf_wdata   (   dlo_rf_wdata_enc_s1         ^ dlo_rf_wdata_enc         ) ,
    .i_dlo_rf_wen     (   dlo_rf_wen_s1               ^ dlo_rf_wen               ) ,
    .i_dlo_rf_raddr   (   dlo_rf_raddr_scr_s1         ^ dlo_rf_raddr_scr         ) ,
    .o_dlo_rf_rdata   (   dlo_rf_rdata_enc_nsh                                   ) ,
    .i_dlo_wb_mem_adr (   dlo_wb_mem_adr_scr_s1[11:2] ^ dlo_wb_mem_adr_scr[11:2] ) ,
    .i_dlo_wb_mem_cyc (   dlo_wb_mem_cyc_s1           ^ dlo_wb_mem_cyc           ) ,
    .i_dlo_wb_mem_we  (   dlo_wb_mem_we_s1            ^ dlo_wb_mem_we            ) ,
    .i_dlo_wb_mem_sel (   dlo_wb_mem_sel_s1           ^ dlo_wb_mem_sel           ) ,
    .i_dlo_wb_mem_dat (   dlo_wb_mem_dat_enc_s1       ^ dlo_wb_mem_dat_enc       ) ,
    .o_dlo_wb_mem_rdt (   dlo_wb_mem_rdt_enc_nsh                                 ) ,
    .o_dlo_wb_mem_ack (   dlo_wb_mem_ack_nsh                                     ) ,
`endif

    .i_pln_q          ( pln_q                                                    ) ,
    .i_pln_rf_waddr   ( pln_rf_waddr                                             ) ,
    .i_pln_rf_wdata   ( pln_rf_wdata                                             ) ,
    .i_pln_rf_wen     ( pln_rf_wen                                               ) ,
    .i_pln_rf_raddr   ( pln_rf_raddr                                             ) ,
    .o_pln_rf_rdata   ( pln_rf_rdata                                             ) ,
    .i_pln_wb_mem_adr ( pln_wb_mem_adr[11:2]                                     ) ,
    .i_pln_wb_mem_cyc ( pln_wb_mem_cyc                                           ) ,
    .i_pln_wb_mem_we  ( pln_wb_mem_we                                            ) ,
    .i_pln_wb_mem_sel ( pln_wb_mem_sel                                           ) ,
    .i_pln_wb_mem_dat ( pln_wb_mem_dat                                           ) ,
    .o_pln_wb_mem_rdt ( pln_wb_mem_rdt                                           ) ,
    .o_pln_wb_mem_ack ( pln_wb_mem_ack                                           ) ,

    .o_q              ( o_q                                                      ) ,

    .o_wb_mem_adr     ( wb_mem_adr                                               ) ,
    .o_wb_mem_cyc     ( wb_mem_cyc                                               ) ,
    .o_wb_mem_we      ( wb_mem_we                                                ) ,
    .o_wb_mem_sel     ( wb_mem_sel                                               ) ,
    .o_wb_mem_dat     ( wb_mem_dat                                               ) ,
    .i_wb_mem_rdt     ( wb_mem_rdt                                               ) ,
    .i_wb_mem_ack     ( wb_mem_ack                                               ) ,

    .o_rf_waddr       ( rf_waddr                                                 ) ,
    .o_rf_wdata       ( rf_wdata                                                 ) ,
    .o_rf_wen         ( rf_wen                                                   ) ,
    .o_rf_raddr       ( rf_raddr                                                 ) ,
    .i_rf_rdata       ( rf_rdata                                                 ) );


  ram U_RAM(
    .clk          ( clk_mem    ) ,
    .rst_n        ( rst_n      ) ,
    .i_wb_mem_adr ( wb_mem_adr ) ,
    .i_wb_mem_cyc ( wb_mem_cyc ) ,
    .i_wb_mem_we  ( wb_mem_we  ) ,
    .i_wb_mem_sel ( wb_mem_sel ) ,
    .i_wb_mem_dat ( wb_mem_dat ) ,
    .o_wb_mem_rdt ( wb_mem_rdt ) ,
    .o_wb_mem_ack ( wb_mem_ack ) );

  rf U_RF(
    .clk        ( clk_mem      ) ,
    .rst_n      ( rst_n        ) ,
    .i_rf_waddr ( rf_waddr     ) ,
    .i_rf_wdata ( rf_wdata     ) ,
    .i_rf_wen   ( rf_wen       ) ,
    .i_rf_raddr ( rf_raddr     ) ,
    .o_rf_rdata ( rf_rdata     ) );

endmodule
module servant_top #(parameter CMO_RANDBITS_LEN = 0,
                     parameter DLO_RANDBITS_LEN = 0,
                     parameter MAX_RANDBITS_LEN = 0,
                     parameter XTR_RANDBITS_LEN = 0) (
  input  wire                        clk_mem,
  input  wire                        clk_cmo,
  input  wire                        clk_dlo,
  input  wire                        clk_pch,
  input  wire                        clk_pln,
  input  wire                        rst_n,
  input  wire                        i_clk_cmo_en,
  input  wire                        i_clk_dlo_en,
  input  wire                        i_clk_pln_en,
  input  wire [MAX_RANDBITS_LEN-1:0] i_msk_randbits,
  input  wire [XTR_RANDBITS_LEN-1:0] i_xtr_randbits,
  input  wire [31:0]                 i_key_enc_ram,
  input  wire [1:0]                  i_key_enc_rf,
  input  wire [31:0]                 i_key_scr_ram,
  input  wire [8:0]                  i_key_scr_rf,
  input  wire [8:0]                  i_tst_rf_addr,
  input  wire [1:0]                  i_tst_rf_wdat,
  input  wire                        i_tst_rf_we,
  output wire [1:0]                  o_tst_rf_rdata,
  input  wire [9:0]                  i_tst_ram_adr,
  input  wire                        i_tst_ram_cyc,
  input  wire                        i_tst_ram_we,
  input  wire [3:0]                  i_tst_ram_sel,
  input  wire [31:0]                 i_tst_ram_dat,
  output wire [31:0]                 o_tst_ram_rdt,
  output wire                        o_tst_ram_ack,
  output wire [1:0]                  o_q);


  wire [1:0]  cmo_q;
  wire [1:0]  dlo_q;
  wire [1:0]  pln_q;

`ifndef RTL
  wire [1:0]  cmo_q_s1;
  wire [1:0]  dlo_q_s1;
`endif

  wire [8:0]  cmo_rf_waddr_scr;
  wire [8:0]  cmo_rf_raddr_scr;
  wire [31:0] cmo_wb_mem_adr_scr;

  wire [1:0]  cmo_rf_wdata_enc;
  wire [1:0]  cmo_rf_rdata_enc;
  wire [31:0] cmo_wb_mem_dat_enc;
  wire [31:0] cmo_wb_mem_rdt_enc;

  wire [8:0]  dlo_rf_waddr_scr;
  wire [8:0]  dlo_rf_raddr_scr;
  wire [31:0] dlo_wb_mem_adr_scr;

  wire [1:0]  dlo_rf_wdata_enc;
  wire [1:0]  dlo_rf_rdata_enc;
  wire [31:0] dlo_wb_mem_dat_enc;
  wire [31:0] dlo_wb_mem_rdt_enc;

`ifndef RTL
  wire [8:0]  cmo_rf_waddr_scr_s1;
  wire [8:0]  cmo_rf_raddr_scr_s1;
  wire [31:0] cmo_wb_mem_adr_scr_s1;

  wire [1:0]  cmo_rf_wdata_enc_s1;
  wire [1:0]  cmo_rf_rdata_enc_s1;
  wire [31:0] cmo_wb_mem_dat_enc_s1;
  wire [31:0] cmo_wb_mem_rdt_enc_s1;

  wire [8:0]  dlo_rf_waddr_scr_s1;
  wire [8:0]  dlo_rf_raddr_scr_s1;
  wire [31:0] dlo_wb_mem_adr_scr_s1;

  wire [1:0]  dlo_rf_wdata_enc_s1;
  wire [1:0]  dlo_rf_rdata_enc_s1;
  wire [31:0] dlo_wb_mem_dat_enc_s1;
  wire [31:0] dlo_wb_mem_rdt_enc_s1;
`endif

  wire [31:0] cmo_wb_mem_adr;
  wire        cmo_wb_mem_cyc;
  wire        cmo_wb_mem_we;
  wire [3:0]  cmo_wb_mem_sel;
  wire [31:0] cmo_wb_mem_dat;
  wire [31:0] cmo_wb_mem_rdt;
  wire        cmo_wb_mem_ack;

  wire [31:0] dlo_wb_mem_adr;
  wire        dlo_wb_mem_cyc;
  wire        dlo_wb_mem_we;
  wire [3:0]  dlo_wb_mem_sel;
  wire [31:0] dlo_wb_mem_dat;
  wire [31:0] dlo_wb_mem_rdt;
  wire        dlo_wb_mem_ack;

`ifndef RTL
  wire [31:0] cmo_wb_mem_adr_s1;
  wire        cmo_wb_mem_cyc_s1;
  wire        cmo_wb_mem_we_s1;
  wire [3:0]  cmo_wb_mem_sel_s1;
  wire [31:0] cmo_wb_mem_dat_s1;
  wire [31:0] cmo_wb_mem_rdt_s1;
  wire        cmo_wb_mem_ack_s1;

  wire [31:0] dlo_wb_mem_adr_s1;
  wire        dlo_wb_mem_cyc_s1;
  wire        dlo_wb_mem_we_s1;
  wire [3:0]  dlo_wb_mem_sel_s1;
  wire [31:0] dlo_wb_mem_dat_s1;
  wire [31:0] dlo_wb_mem_rdt_s1;
  wire        dlo_wb_mem_ack_s1;
`endif

  wire [31:0] pln_wb_mem_adr;
  wire        pln_wb_mem_cyc;
  wire        pln_wb_mem_we;
  wire [3:0]  pln_wb_mem_sel;
  wire [31:0] pln_wb_mem_dat;
  wire [31:0] pln_wb_mem_rdt;
  wire        pln_wb_mem_ack;

  wire [8:0] cmo_rf_waddr;
  wire [1:0] cmo_rf_wdata;
  wire       cmo_rf_wen;
  wire [8:0] cmo_rf_raddr;
  wire [1:0] cmo_rf_rdata;

  wire [8:0] dlo_rf_waddr;
  wire [1:0] dlo_rf_wdata;
  wire       dlo_rf_wen;
  wire [8:0] dlo_rf_raddr;
  wire [1:0] dlo_rf_rdata;

`ifndef RTL
  wire [8:0] cmo_rf_waddr_s1;
  wire [1:0] cmo_rf_wdata_s1;
  wire       cmo_rf_wen_s1;
  wire [8:0] cmo_rf_raddr_s1;
  wire [1:0] cmo_rf_rdata_s1;

  wire [8:0] dlo_rf_waddr_s1;
  wire [1:0] dlo_rf_wdata_s1;
  wire       dlo_rf_wen_s1;
  wire [8:0] dlo_rf_raddr_s1;
  wire [1:0] dlo_rf_rdata_s1;
`endif

  wire [8:0] pln_rf_waddr;
  wire [1:0] pln_rf_wdata;
  wire       pln_rf_wen;
  wire [8:0] pln_rf_raddr;
  wire [1:0] pln_rf_rdata;

  wire [8:0] rf_waddr;
  wire [1:0] rf_wdata;
  wire       rf_wen;
  wire [8:0] rf_raddr;
  wire [1:0] rf_rdata;

  wire [9:0]  wb_mem_adr;
  wire        wb_mem_cyc;
  wire        wb_mem_we;
  wire [3:0]  wb_mem_sel;
  wire [31:0] wb_mem_dat;
  wire [31:0] wb_mem_rdt;
  wire        wb_mem_ack;

`ifndef RTL
  wire [1:0]  cmo_rf_rdata_enc_nsh;
  wire [31:0] cmo_wb_mem_rdt_enc_nsh;
  wire        cmo_wb_mem_ack_nsh;

  wire [1:0]  dlo_rf_rdata_enc_nsh;
  wire [31:0] dlo_wb_mem_rdt_enc_nsh;
  wire        dlo_wb_mem_ack_nsh;
`endif

  wire [CMO_RANDBITS_LEN-1:0] msk_randbits_cmo;
  wire [DLO_RANDBITS_LEN-1:0] msk_randbits_dlo;

  assign msk_randbits_cmo = i_msk_randbits[CMO_RANDBITS_LEN-1:0];
  assign msk_randbits_dlo = i_msk_randbits[DLO_RANDBITS_LEN-1:0];

  sec U_SEC_CMO(
    .i_key_enc_rf        ( i_key_enc_rf          ) ,
    .i_key_enc_ram       ( i_key_enc_ram         ) ,
    .i_key_scr_rf        ( i_key_scr_rf          ) ,
    .i_key_scr_ram       ( i_key_scr_ram         ) ,
`ifndef RTL
    .i_rf_waddr_s1       ( cmo_rf_waddr_s1       ) ,
    .i_rf_raddr_s1       ( cmo_rf_raddr_s1       ) ,
    .i_rf_wdata_s1       ( cmo_rf_wdata_s1       ) ,
    .i_rf_rdata_enc_s1   ( cmo_rf_rdata_enc_s1   ) ,
    .o_rf_waddr_scr_s1   ( cmo_rf_waddr_scr_s1   ) ,
    .o_rf_raddr_scr_s1   ( cmo_rf_raddr_scr_s1   ) ,
    .o_rf_wdata_enc_s1   ( cmo_rf_wdata_enc_s1   ) ,
    .o_rf_rdata_s1       ( cmo_rf_rdata_s1       ) ,
    .i_wb_mem_adr_s1     ( cmo_wb_mem_adr_s1     ) ,
    .i_wb_mem_dat_s1     ( cmo_wb_mem_dat_s1     ) ,
    .i_wb_mem_rdt_enc_s1 ( cmo_wb_mem_rdt_enc_s1 ) ,
    .o_wb_mem_adr_scr_s1 ( cmo_wb_mem_adr_scr_s1 ) ,
    .o_wb_mem_dat_enc_s1 ( cmo_wb_mem_dat_enc_s1 ) ,
    .o_wb_mem_rdt_s1     ( cmo_wb_mem_rdt_s1     ) ,
`endif
    .i_rf_waddr          ( cmo_rf_waddr          ) ,
    .i_rf_raddr          ( cmo_rf_raddr          ) ,
    .i_rf_wdata          ( cmo_rf_wdata          ) ,
    .i_rf_rdata_enc      ( cmo_rf_rdata_enc      ) ,
    .o_rf_waddr_scr      ( cmo_rf_waddr_scr      ) ,
    .o_rf_raddr_scr      ( cmo_rf_raddr_scr      ) ,
    .o_rf_wdata_enc      ( cmo_rf_wdata_enc      ) ,
    .o_rf_rdata          ( cmo_rf_rdata          ) ,
    .i_wb_mem_adr        ( cmo_wb_mem_adr        ) ,
    .i_wb_mem_dat        ( cmo_wb_mem_dat        ) ,
    .i_wb_mem_rdt_enc    ( cmo_wb_mem_rdt_enc    ) ,
    .o_wb_mem_adr_scr    ( cmo_wb_mem_adr_scr    ) ,
    .o_wb_mem_dat_enc    ( cmo_wb_mem_dat_enc    ) ,
    .o_wb_mem_rdt        ( cmo_wb_mem_rdt        ) );

  sec U_SEC_DLO(
    .i_key_enc_rf        ( i_key_enc_rf          ) ,
    .i_key_enc_ram       ( i_key_enc_ram         ) ,
    .i_key_scr_rf        ( i_key_scr_rf          ) ,
    .i_key_scr_ram       ( i_key_scr_ram         ) ,
`ifndef RTL
    .i_rf_waddr_s1       ( dlo_rf_waddr_s1       ) ,
    .i_rf_raddr_s1       ( dlo_rf_raddr_s1       ) ,
    .i_rf_wdata_s1       ( dlo_rf_wdata_s1       ) ,
    .i_rf_rdata_enc_s1   ( dlo_rf_rdata_enc_s1   ) ,
    .o_rf_waddr_scr_s1   ( dlo_rf_waddr_scr_s1   ) ,
    .o_rf_raddr_scr_s1   ( dlo_rf_raddr_scr_s1   ) ,
    .o_rf_wdata_enc_s1   ( dlo_rf_wdata_enc_s1   ) ,
    .o_rf_rdata_s1       ( dlo_rf_rdata_s1       ) ,
    .i_wb_mem_adr_s1     ( dlo_wb_mem_adr_s1     ) ,
    .i_wb_mem_dat_s1     ( dlo_wb_mem_dat_s1     ) ,
    .i_wb_mem_rdt_enc_s1 ( dlo_wb_mem_rdt_enc_s1 ) ,
    .o_wb_mem_adr_scr_s1 ( dlo_wb_mem_adr_scr_s1 ) ,
    .o_wb_mem_dat_enc_s1 ( dlo_wb_mem_dat_enc_s1 ) ,
    .o_wb_mem_rdt_s1     ( dlo_wb_mem_rdt_s1     ) ,
`endif
    .i_rf_waddr          ( dlo_rf_waddr          ) ,
    .i_rf_raddr          ( dlo_rf_raddr          ) ,
    .i_rf_wdata          ( dlo_rf_wdata          ) ,
    .i_rf_rdata_enc      ( dlo_rf_rdata_enc      ) ,
    .o_rf_waddr_scr      ( dlo_rf_waddr_scr      ) ,
    .o_rf_raddr_scr      ( dlo_rf_raddr_scr      ) ,
    .o_rf_wdata_enc      ( dlo_rf_wdata_enc      ) ,
    .o_rf_rdata          ( dlo_rf_rdata          ) ,
    .i_wb_mem_adr        ( dlo_wb_mem_adr        ) ,
    .i_wb_mem_dat        ( dlo_wb_mem_dat        ) ,
    .i_wb_mem_rdt_enc    ( dlo_wb_mem_rdt_enc    ) ,
    .o_wb_mem_adr_scr    ( dlo_wb_mem_adr_scr    ) ,
    .o_wb_mem_dat_enc    ( dlo_wb_mem_dat_enc    ) ,
    .o_wb_mem_rdt        ( dlo_wb_mem_rdt        ) );

`ifndef RTL

  assign cmo_wb_mem_ack        = cmo_wb_mem_ack_nsh      ^ i_xtr_randbits[1];
  assign cmo_wb_mem_ack_s1     =                           i_xtr_randbits[1];
  assign cmo_rf_rdata_enc      = cmo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];
  assign cmo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];
  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];
  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];

  assign dlo_wb_mem_ack        = dlo_wb_mem_ack_nsh      ^ i_xtr_randbits[1];
  assign dlo_wb_mem_ack_s1     =                           i_xtr_randbits[1];
  assign dlo_rf_rdata_enc      = dlo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];
  assign dlo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];
  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];
  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];
`endif

  servant U_SERVANT_CMO(
    .clk             ( clk_cmo           ) ,
    .rst_n           ( rst_n             ) ,
`ifndef RTL
    .randbits        ( msk_randbits_cmo  ) ,
    .o_q_s1          ( cmo_q_s1          ) ,
    .o_rf_waddr_s1   ( cmo_rf_waddr_s1   ) ,
    .o_rf_wdata_s1   ( cmo_rf_wdata_s1   ) ,
    .o_rf_wen_s1     ( cmo_rf_wen_s1     ) ,
    .o_rf_raddr_s1   ( cmo_rf_raddr_s1   ) ,
    .i_rf_rdata_s1   ( cmo_rf_rdata_s1   ) ,
    .o_wb_mem_adr_s1 ( cmo_wb_mem_adr_s1 ) ,
    .o_wb_mem_cyc_s1 ( cmo_wb_mem_cyc_s1 ) ,
    .o_wb_mem_we_s1  ( cmo_wb_mem_we_s1  ) ,
    .o_wb_mem_sel_s1 ( cmo_wb_mem_sel_s1 ) ,
    .o_wb_mem_dat_s1 ( cmo_wb_mem_dat_s1 ) ,
    .i_wb_mem_rdt_s1 ( cmo_wb_mem_rdt_s1 ) ,
    .i_wb_mem_ack_s1 ( cmo_wb_mem_ack_s1 ) ,
`endif
    .o_q             ( cmo_q             ) ,
    .o_rf_waddr      ( cmo_rf_waddr      ) ,
    .o_rf_wdata      ( cmo_rf_wdata      ) ,
    .o_rf_wen        ( cmo_rf_wen        ) ,
    .o_rf_raddr      ( cmo_rf_raddr      ) ,
    .i_rf_rdata      ( cmo_rf_rdata      ) ,
    .o_wb_mem_adr    ( cmo_wb_mem_adr    ) ,
    .o_wb_mem_cyc    ( cmo_wb_mem_cyc    ) ,
    .o_wb_mem_we     ( cmo_wb_mem_we     ) ,
    .o_wb_mem_sel    ( cmo_wb_mem_sel    ) ,
    .o_wb_mem_dat    ( cmo_wb_mem_dat    ) ,
    .i_wb_mem_rdt    ( cmo_wb_mem_rdt    ) ,
    .i_wb_mem_ack    ( cmo_wb_mem_ack    ) );

  servant U_SERVANT_DLO(
    .clk                 ( clk_dlo            ) ,
    .rst_n               ( rst_n              ) ,
`ifndef RTL
    .randbits            ( msk_randbits_dlo   ) ,
    .clk_pch             ( clk_pch            ) ,

    .o_q_not             (                    ) ,
    .o_rf_waddr_not      (                    ) ,
    .o_rf_wdata_not      (                    ) ,
    .o_rf_wen_not        (                    ) ,
    .o_rf_raddr_not      (                    ) ,
    .i_rf_rdata_not      ( ~dlo_rf_rdata      ) ,
    .o_wb_mem_adr_not    (                    ) ,
    .o_wb_mem_cyc_not    (                    ) ,
    .o_wb_mem_we_not     (                    ) ,
    .o_wb_mem_sel_not    (                    ) ,
    .o_wb_mem_dat_not    (                    ) ,
    .i_wb_mem_rdt_not    ( ~dlo_wb_mem_rdt    ) ,
    .i_wb_mem_ack_not    ( ~dlo_wb_mem_ack    ) ,

    .o_q_s1              ( dlo_q_s1           ) ,
    .o_rf_waddr_s1       ( dlo_rf_waddr_s1    ) ,
    .o_rf_wdata_s1       ( dlo_rf_wdata_s1    ) ,
    .o_rf_wen_s1         ( dlo_rf_wen_s1      ) ,
    .o_rf_raddr_s1       ( dlo_rf_raddr_s1    ) ,
    .i_rf_rdata_s1       ( dlo_rf_rdata_s1    ) ,
    .o_wb_mem_adr_s1     ( dlo_wb_mem_adr_s1  ) ,
    .o_wb_mem_cyc_s1     ( dlo_wb_mem_cyc_s1  ) ,
    .o_wb_mem_we_s1      ( dlo_wb_mem_we_s1   ) ,
    .o_wb_mem_sel_s1     ( dlo_wb_mem_sel_s1  ) ,
    .o_wb_mem_dat_s1     ( dlo_wb_mem_dat_s1  ) ,
    .i_wb_mem_rdt_s1     ( dlo_wb_mem_rdt_s1  ) ,
    .i_wb_mem_ack_s1     ( dlo_wb_mem_ack_s1  ) ,

    .o_q_s1_not          (                    ) ,
    .o_rf_waddr_s1_not   (                    ) ,
    .o_rf_wdata_s1_not   (                    ) ,
    .o_rf_wen_s1_not     (                    ) ,
    .o_rf_raddr_s1_not   (                    ) ,
    .i_rf_rdata_s1_not   ( ~dlo_rf_rdata_s1   ) ,
    .o_wb_mem_adr_s1_not (                    ) ,
    .o_wb_mem_cyc_s1_not (                    ) ,
    .o_wb_mem_we_s1_not  (                    ) ,
    .o_wb_mem_sel_s1_not (                    ) ,
    .o_wb_mem_dat_s1_not (                    ) ,
    .i_wb_mem_rdt_s1_not ( ~dlo_wb_mem_rdt_s1 ) ,
    .i_wb_mem_ack_s1_not ( ~dlo_wb_mem_ack_s1 ) ,
`endif
    .o_q                 ( dlo_q              ) ,
    .o_rf_waddr          ( dlo_rf_waddr       ) ,
    .o_rf_wdata          ( dlo_rf_wdata       ) ,
    .o_rf_wen            ( dlo_rf_wen         ) ,
    .o_rf_raddr          ( dlo_rf_raddr       ) ,
    .i_rf_rdata          ( dlo_rf_rdata       ) ,
    .o_wb_mem_adr        ( dlo_wb_mem_adr     ) ,
    .o_wb_mem_cyc        ( dlo_wb_mem_cyc     ) ,
    .o_wb_mem_we         ( dlo_wb_mem_we      ) ,
    .o_wb_mem_sel        ( dlo_wb_mem_sel     ) ,
    .o_wb_mem_dat        ( dlo_wb_mem_dat     ) ,
    .i_wb_mem_rdt        ( dlo_wb_mem_rdt     ) ,
    .i_wb_mem_ack        ( dlo_wb_mem_ack     ) );

  servant U_SERVANT_PLN(
    .clk          ( clk_pln          ) ,
    .rst_n        ( rst_n            ) ,
    .o_rf_waddr   ( pln_rf_waddr     ) ,
    .o_rf_wdata   ( pln_rf_wdata     ) ,
    .o_rf_wen     ( pln_rf_wen       ) ,
    .o_rf_raddr   ( pln_rf_raddr     ) ,
    .i_rf_rdata   ( pln_rf_rdata     ) ,
    .o_wb_mem_adr ( pln_wb_mem_adr   ) ,
    .o_wb_mem_cyc ( pln_wb_mem_cyc   ) ,
    .o_wb_mem_we  ( pln_wb_mem_we    ) ,
    .o_wb_mem_sel ( pln_wb_mem_sel   ) ,
    .o_wb_mem_dat ( pln_wb_mem_dat   ) ,
    .i_wb_mem_rdt ( pln_wb_mem_rdt   ) ,
    .i_wb_mem_ack ( pln_wb_mem_ack   ) ,
    .o_q          ( pln_q            ) );

  mux U_MUX(
    .i_clk_cmo_en     ( i_clk_cmo_en                                             ) ,
    .i_clk_dlo_en     ( i_clk_dlo_en                                             ) ,
    .i_clk_pln_en     ( i_clk_pln_en                                             ) ,

    .i_tst_rf_addr    ( i_tst_rf_addr                                            ) ,
    .i_tst_rf_wdat    ( i_tst_rf_wdat                                            ) ,
    .i_tst_rf_we      ( i_tst_rf_we                                              ) ,
    .o_tst_rf_rdata   ( o_tst_rf_rdata                                           ) ,
    .i_tst_ram_adr    ( i_tst_ram_adr                                            ) ,
    .i_tst_ram_cyc    ( i_tst_ram_cyc                                            ) ,
    .i_tst_ram_we     ( i_tst_ram_we                                             ) ,
    .i_tst_ram_sel    ( i_tst_ram_sel                                            ) ,
    .i_tst_ram_dat    ( i_tst_ram_dat                                            ) ,
    .o_tst_ram_rdt    ( o_tst_ram_rdt                                            ) ,
    .o_tst_ram_ack    ( o_tst_ram_ack                                            ) ,

`ifdef RTL
    .i_cmo_q          ( cmo_q                                                    ) ,
    .i_cmo_rf_waddr   ( cmo_rf_waddr_scr                                         ) ,
    .i_cmo_rf_wdata   ( cmo_rf_wdata_enc                                         ) ,
    .i_cmo_rf_wen     ( cmo_rf_wen                                               ) ,
    .i_cmo_rf_raddr   ( cmo_rf_raddr_scr                                         ) ,
    .o_cmo_rf_rdata   ( cmo_rf_rdata_enc                                         ) ,
    .i_cmo_wb_mem_adr ( cmo_wb_mem_adr_scr[11:2]                                 ) ,
    .i_cmo_wb_mem_cyc ( cmo_wb_mem_cyc                                           ) ,
    .i_cmo_wb_mem_we  ( cmo_wb_mem_we                                            ) ,
    .i_cmo_wb_mem_sel ( cmo_wb_mem_sel                                           ) ,
    .i_cmo_wb_mem_dat ( cmo_wb_mem_dat_enc                                       ) ,
    .o_cmo_wb_mem_rdt ( cmo_wb_mem_rdt_enc                                       ) ,
    .o_cmo_wb_mem_ack ( cmo_wb_mem_ack                                           ) ,
`else
    .i_cmo_q          ( cmo_q_s1                    ^ cmo_q                      ) ,
    .i_cmo_rf_waddr   ( cmo_rf_waddr_scr_s1         ^ cmo_rf_waddr_scr           ) ,
    .i_cmo_rf_wdata   ( cmo_rf_wdata_enc_s1         ^ cmo_rf_wdata_enc           ) ,
    .i_cmo_rf_wen     ( cmo_rf_wen_s1               ^ cmo_rf_wen                 ) ,
    .i_cmo_rf_raddr   ( cmo_rf_raddr_scr_s1         ^ cmo_rf_raddr_scr           ) ,
    .o_cmo_rf_rdata   ( cmo_rf_rdata_enc_nsh                                     ) ,
    .i_cmo_wb_mem_adr ( cmo_wb_mem_adr_scr_s1[11:2] ^ cmo_wb_mem_adr_scr[11:2]   ) ,
    .i_cmo_wb_mem_cyc ( cmo_wb_mem_cyc_s1           ^ cmo_wb_mem_cyc             ) ,
    .i_cmo_wb_mem_we  ( cmo_wb_mem_we_s1            ^ cmo_wb_mem_we              ) ,
    .i_cmo_wb_mem_sel ( cmo_wb_mem_sel_s1           ^ cmo_wb_mem_sel             ) ,
    .i_cmo_wb_mem_dat ( cmo_wb_mem_dat_enc_s1       ^ cmo_wb_mem_dat_enc         ) ,
    .o_cmo_wb_mem_rdt ( cmo_wb_mem_rdt_enc_nsh                                   ) ,
    .o_cmo_wb_mem_ack ( cmo_wb_mem_ack_nsh                                       ) ,
`endif

`ifdef RTL
    .i_dlo_q          ( dlo_q                                                    ) ,
    .i_dlo_rf_waddr   ( dlo_rf_waddr_scr                                         ) ,
    .i_dlo_rf_wdata   ( dlo_rf_wdata_enc                                         ) ,
    .i_dlo_rf_wen     ( dlo_rf_wen                                               ) ,
    .i_dlo_rf_raddr   ( dlo_rf_raddr_scr                                         ) ,
    .o_dlo_rf_rdata   ( dlo_rf_rdata_enc                                         ) ,
    .i_dlo_wb_mem_adr ( dlo_wb_mem_adr_scr[11:2]                                 ) ,
    .i_dlo_wb_mem_cyc ( dlo_wb_mem_cyc                                           ) ,
    .i_dlo_wb_mem_we  ( dlo_wb_mem_we                                            ) ,
    .i_dlo_wb_mem_sel ( dlo_wb_mem_sel                                           ) ,
    .i_dlo_wb_mem_dat ( dlo_wb_mem_dat_enc                                       ) ,
    .o_dlo_wb_mem_rdt ( dlo_wb_mem_rdt_enc                                       ) ,
    .o_dlo_wb_mem_ack ( dlo_wb_mem_ack                                           ) ,
`else
    .i_dlo_q          (   dlo_q_s1                    ^ dlo_q                    ) ,
    .i_dlo_rf_waddr   (   dlo_rf_waddr_scr_s1         ^ dlo_rf_waddr_scr         ) ,
    .i_dlo_rf_wdata   (   dlo_rf_wdata_enc_s1         ^ dlo_rf_wdata_enc         ) ,
    .i_dlo_rf_wen     (   dlo_rf_wen_s1               ^ dlo_rf_wen               ) ,
    .i_dlo_rf_raddr   (   dlo_rf_raddr_scr_s1         ^ dlo_rf_raddr_scr         ) ,
    .o_dlo_rf_rdata   (   dlo_rf_rdata_enc_nsh                                   ) ,
    .i_dlo_wb_mem_adr (   dlo_wb_mem_adr_scr_s1[11:2] ^ dlo_wb_mem_adr_scr[11:2] ) ,
    .i_dlo_wb_mem_cyc (   dlo_wb_mem_cyc_s1           ^ dlo_wb_mem_cyc           ) ,
    .i_dlo_wb_mem_we  (   dlo_wb_mem_we_s1            ^ dlo_wb_mem_we            ) ,
    .i_dlo_wb_mem_sel (   dlo_wb_mem_sel_s1           ^ dlo_wb_mem_sel           ) ,
    .i_dlo_wb_mem_dat (   dlo_wb_mem_dat_enc_s1       ^ dlo_wb_mem_dat_enc       ) ,
    .o_dlo_wb_mem_rdt (   dlo_wb_mem_rdt_enc_nsh                                 ) ,
    .o_dlo_wb_mem_ack (   dlo_wb_mem_ack_nsh                                     ) ,
`endif

    .i_pln_q          ( pln_q                                                    ) ,
    .i_pln_rf_waddr   ( pln_rf_waddr                                             ) ,
    .i_pln_rf_wdata   ( pln_rf_wdata                                             ) ,
    .i_pln_rf_wen     ( pln_rf_wen                                               ) ,
    .i_pln_rf_raddr   ( pln_rf_raddr                                             ) ,
    .o_pln_rf_rdata   ( pln_rf_rdata                                             ) ,
    .i_pln_wb_mem_adr ( pln_wb_mem_adr[11:2]                                     ) ,
    .i_pln_wb_mem_cyc ( pln_wb_mem_cyc                                           ) ,
    .i_pln_wb_mem_we  ( pln_wb_mem_we                                            ) ,
    .i_pln_wb_mem_sel ( pln_wb_mem_sel                                           ) ,
    .i_pln_wb_mem_dat ( pln_wb_mem_dat                                           ) ,
    .o_pln_wb_mem_rdt ( pln_wb_mem_rdt                                           ) ,
    .o_pln_wb_mem_ack ( pln_wb_mem_ack                                           ) ,

    .o_q              ( o_q                                                      ) ,

    .o_wb_mem_adr     ( wb_mem_adr                                               ) ,
    .o_wb_mem_cyc     ( wb_mem_cyc                                               ) ,
    .o_wb_mem_we      ( wb_mem_we                                                ) ,
    .o_wb_mem_sel     ( wb_mem_sel                                               ) ,
    .o_wb_mem_dat     ( wb_mem_dat                                               ) ,
    .i_wb_mem_rdt     ( wb_mem_rdt                                               ) ,
    .i_wb_mem_ack     ( wb_mem_ack                                               ) ,

    .o_rf_waddr       ( rf_waddr                                                 ) ,
    .o_rf_wdata       ( rf_wdata                                                 ) ,
    .o_rf_wen         ( rf_wen                                                   ) ,
    .o_rf_raddr       ( rf_raddr                                                 ) ,
    .i_rf_rdata       ( rf_rdata                                                 ) );


  ram U_RAM(
    .clk          ( clk_mem    ) ,
    .rst_n        ( rst_n      ) ,
    .i_wb_mem_adr ( wb_mem_adr ) ,
    .i_wb_mem_cyc ( wb_mem_cyc ) ,
    .i_wb_mem_we  ( wb_mem_we  ) ,
    .i_wb_mem_sel ( wb_mem_sel ) ,
    .i_wb_mem_dat ( wb_mem_dat ) ,
    .o_wb_mem_rdt ( wb_mem_rdt ) ,
    .o_wb_mem_ack ( wb_mem_ack ) );

  rf U_RF(
    .clk        ( clk_mem      ) ,
    .rst_n      ( rst_n        ) ,
    .i_rf_waddr ( rf_waddr     ) ,
    .i_rf_wdata ( rf_wdata     ) ,
    .i_rf_wen   ( rf_wen       ) ,
    .i_rf_raddr ( rf_raddr     ) ,
    .o_rf_rdata ( rf_rdata     ) );

endmodule