data/full_repos/permissive/447223480/01_add/cpu.v
data/verilator_xmls/129a3714-4632-494b-881a-1dcf02d4c0b9.xml
module cpu(clock, reset);
	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

	wire [15:0] inst;
	pmem pmem(.addr(pc), .data(inst));

	wire [4:0] select = inst[11:7];
	wire [31:0] immediate_value = {{27{inst[12]}}, inst[6:2]};

	wire [31:0] current_value;
	wire [31:0] new_value = current_value + immediate_value;

	regs regs(.clock(clock), .reset(reset), .select(select), .in_data(new_value), .out_data(current_value));

endmodule
module cpu(clock, reset);

	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

	wire [15:0] inst;
	pmem pmem(.addr(pc), .data(inst));

	wire [4:0] select = inst[11:7];
	wire [31:0] immediate_value = {{27{inst[12]}}, inst[6:2]};

	wire [31:0] current_value;
	wire [31:0] new_value = current_value + immediate_value;

	regs regs(.clock(clock), .reset(reset), .select(select), .in_data(new_value), .out_data(current_value));

endmodule