data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/PipelineRegEXEMEM.v
data/verilator_xmls/12f22c50-e51c-4f2a-96ab-b8aac45846f2.xml
module PipelineRegEXEMEM (
    input [4:0] erd,
    input [63:0] er, eqb,
    input ewmem,
    input [2:0] efunc3,
    input em2reg, ewreg,
    input clk,

    output reg [4:0] mrd,
    output reg [63:0] mr, mqb,
    output reg mwmem,
    output reg [2:0] mfunc3,
    output reg mm2reg, mwreg
);

    always @(posedge clk) begin
        mrd <= erd;
        mr <= er;
        mqb <= eqb;
        mwmem <= ewmem;
        mfunc3 <= efunc3;
        mm2reg <= em2reg;
        mwreg <= ewreg;
    end

endmodule
module PipelineRegEXEMEM (
    input [4:0] erd,
    input [63:0] er, eqb,
    input ewmem,
    input [2:0] efunc3,
    input em2reg, ewreg,
    input clk,

    output reg [4:0] mrd,
    output reg [63:0] mr, mqb,
    output reg mwmem,
    output reg [2:0] mfunc3,
    output reg mm2reg, mwreg
);


    always @(posedge clk) begin
        mrd <= erd;
        mr <= er;
        mqb <= eqb;
        mwmem <= ewmem;
        mfunc3 <= efunc3;
        mm2reg <= em2reg;
        mwreg <= ewreg;
    end

endmodule