data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/Andgate.v
data/verilator_xmls/0cc8d763-aa35-4909-87eb-0351fc7bc904.xml
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a & b;
endmodule
module top_module( 
    input a, 
    input b, 
    output out );


    assign out = a & b;
endmodule