data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src/and4ff.v
1: b"%Error: data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src/and4ff.v:46: Cannot find file containing module: 'andgate4'\n       andgate4 inst(\n       ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src,data/full_repos/permissive/530501842/andgate4\n             data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src,data/full_repos/permissive/530501842/andgate4.v\n             data/full_repos/permissive/530501842/AND_FF/AND_FF/rtl_src,data/full_repos/permissive/530501842/andgate4.sv\n             andgate4\n             andgate4.v\n             andgate4.sv\n             obj_dir/andgate4\n             obj_dir/andgate4.v\n             obj_dir/andgate4.sv\n%Error: Exiting due to 1 error(s)\n"
module and4ff #(

    parameter NO_OF_GATES = 1
    
        )
      (
    input clock0,
    input [NO_OF_GATES-1:0] in0,
    input [NO_OF_GATES-1:0] in1,
    input [NO_OF_GATES-1:0] in2,
    input [NO_OF_GATES-1:0] in3,

   output reg [NO_OF_GATES-1:0]out1
    );

    wire [NO_OF_GATES-1:0]and_result;
    genvar i;
    
    generate
    for(i=0;i<NO_OF_GATES;i=i+1)
    begin

       andgate4 inst(
       .in0(in0[i]),
       .in1(in1[i]),
       .in2(in2[i]),
       .in3(in3[i]),
       .out1(and_result[i])
       );
    end
    endgenerate
    
    always@(posedge clock0)
    begin
      out1	<=	and_result;
    end

endmodule
module and4ff #(

    parameter NO_OF_GATES = 1
    
        )
      (
    input clock0,
    input [NO_OF_GATES-1:0] in0,
    input [NO_OF_GATES-1:0] in1,
    input [NO_OF_GATES-1:0] in2,
    input [NO_OF_GATES-1:0] in3,

   output reg [NO_OF_GATES-1:0]out1
    );


    wire [NO_OF_GATES-1:0]and_result;
    genvar i;
    
    generate
    for(i=0;i<NO_OF_GATES;i=i+1)
    begin

       andgate4 inst(
       .in0(in0[i]),
       .in1(in1[i]),
       .in2(in2[i]),
       .in3(in3[i]),
       .out1(and_result[i])
       );
    end
    endgenerate
    
    always@(posedge clock0)
    begin
      out1	<=	and_result;
    end

endmodule