data/full_repos/permissive/454159683/cont4b/cont4b.v
data/verilator_xmls/7ea96a5c-aa56-4e4d-9f6e-404d1339de71.xml
module cont4b(input clk, rst, ctrl, output reg[3:0] count);
	always @(posedge clk)
	begin
		if (rst)
			count = 0;
		else if (ctrl)
			count = count - 1;
		else
			count = count + 1;
	end
endmodule
module cont4b(input clk, rst, ctrl, output reg[3:0] count);

	always @(posedge clk)
	begin
		if (rst)
			count = 0;
		else if (ctrl)
			count = count - 1;
		else
			count = count + 1;
	end
endmodule