data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:50: Cannot find file containing module: \'setting_reg\'\n   setting_reg #(.my_addr(BASE+0)) sr_0\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/setting_reg.sv\n             setting_reg\n             setting_reg.v\n             setting_reg.sv\n             obj_dir/setting_reg\n             obj_dir/setting_reg.v\n             obj_dir/setting_reg.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:54: Cannot find file containing module: \'setting_reg\'\n   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:58: Cannot find file containing module: \'setting_reg\'\n   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:68: Cannot find file containing module: \'cic_strober\'\n   cic_strober #(.WIDTH(8))\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:71: Cannot find file containing module: \'cic_strober\'\n   cic_strober #(.WIDTH(2))\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:74: Cannot find file containing module: \'cic_strober\'\n   cic_strober #(.WIDTH(2))\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:100: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'interp_rate\' generates 8 bits.\n                                                                                       : ... In instance duc_chain\n   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1\'b0}) : interp_rate;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:100: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n                                                                                       : ... In instance duc_chain\n   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1\'b0}) : interp_rate;\n                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:104: Cannot find file containing module: \'hb_interp\'\n   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:106: Cannot find file containing module: \'hb_interp\'\n   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:109: Cannot find file containing module: \'small_hb_int\'\n   small_hb_int #(.WIDTH(18)) small_hb_interp_i\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:112: Cannot find file containing module: \'small_hb_int\'\n   small_hb_int #(.WIDTH(18)) small_hb_interp_q\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:116: Cannot find file containing module: \'cic_interp\'\n   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:121: Cannot find file containing module: \'cic_interp\'\n   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:131: Cannot find file containing module: \'cordic_z24\'\n   cordic_z24 #(.bitwidth(cwidth))\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:137: Cannot find file containing module: \'MULT18X18S\'\n   MULT18X18S MULT18X18S_inst \n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:146: Cannot find file containing module: \'MULT18X18S\'\n   MULT18X18S MULT18X18S_inst_2 \n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:155: Cannot find file containing module: \'dsp_tx_glue\'\n   dsp_tx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) dsp_tx_glue(\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/duc_chain.v:163: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                       : ... In instance duc_chain\n   assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};\n                     ^\n%Error: Exiting due to 16 error(s), 3 warning(s)\n'
module duc_chain
  #(
    parameter BASE = 0,
    parameter DSPNO = 0,
    parameter WIDTH = 24
  )
  (input clk, input rst, input clr,
   input set_stb, input [7:0] set_addr, input [31:0] set_data,
   input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,


   output [WIDTH-1:0] tx_fe_i,
   output [WIDTH-1:0] tx_fe_q,


   input [31:0] sample,
   input run,
   output strobe,
   output [31:0] debug
   );

   wire duc_enb;
   wire [17:0] scale_factor;
   wire [31:0] phase_inc;
   reg [31:0]  phase;
   wire [7:0]  interp_rate;
   wire [3:0]  tx_femux_a, tx_femux_b;
   wire        enable_hb1, enable_hb2;
   wire        rate_change;
   
   setting_reg #(.my_addr(BASE+0)) sr_0
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(phase_inc),.changed());

   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(scale_factor),.changed());
   
   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));


   wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
   reg 	       strobe_cic = 1;
   reg 	       strobe_hb1 = 1;
   reg 	       strobe_hb2 = 1;
   
   cic_strober #(.WIDTH(8))
     cic_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		 .strobe_fast(1),.strobe_slow(strobe_cic_pre) );
   cic_strober #(.WIDTH(2))
     hb2_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb2 ? 2 : 1),
		 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
   cic_strober #(.WIDTH(2))
     hb1_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb1 ? 2 : 1),
		 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
   
   always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
   always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
   always @(posedge clk) strobe_cic <= strobe_cic_pre;


   always @(posedge clk)
     if(rst)
       phase <= 0;
     else if(~duc_enb)
       phase <= 0;
     else
       phase <= phase + phase_inc;
   
   wire        signed [17:0] da, db;
   wire        signed [35:0] prod_i, prod_q;

   wire [15:0] bb_i;
   wire [15:0] bb_q;
   wire [17:0] i_interp, q_interp;

   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;

   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;


   
   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
   
   small_hb_int #(.WIDTH(18)) small_hb_interp_i
     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
   small_hb_int #(.WIDTH(18)) small_hb_interp_q
     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
   
   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
     cic_interp_i(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		  .strobe_in(strobe_cic),.strobe_out(1),
		  .signal_in(hb2_i),.signal_out(i_interp));
   
   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
     cic_interp_q(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		  .strobe_in(strobe_cic),.strobe_out(1),
		  .signal_in(hb2_q),.signal_out(q_interp));

   localparam  cwidth = WIDTH;
   localparam  zwidth = 24;

   wire [cwidth-1:0] da_c, db_c;
   
   cordic_z24 #(.bitwidth(cwidth))
     cordic(.clock(clk), .reset(rst), .enable(duc_enb),
	    .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
	    .zi(phase[31:32-zwidth]),
	    .xo(da_c),.yo(db_c),.zo() );
   
   MULT18X18S MULT18X18S_inst 
     (.P(prod_i),
      .A(da_c[cwidth-1:cwidth-18]),
      .B(scale_factor),
      .C(clk),
      .CE(1),
      .R(rst)
      );
   
   MULT18X18S MULT18X18S_inst_2 
     (.P(prod_q),
      .A(db_c[cwidth-1:cwidth-18]),
      .B(scale_factor),
      .C(clk),
      .CE(1),
      .R(rst)
      );

   dsp_tx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) dsp_tx_glue(
    .clock(clk), .reset(rst), .clear(clr), .enable(run),
    .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
    .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
    .duc_out_i(prod_i[33:34-WIDTH]), .duc_out_q(prod_q[33:34-WIDTH]),
    .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1), .duc_in_enable(duc_enb),
    .bb_sample(sample), .bb_strobe(strobe));

   assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};

endmodule
module duc_chain
  #(
    parameter BASE = 0,
    parameter DSPNO = 0,
    parameter WIDTH = 24
  )
  (input clk, input rst, input clr,
   input set_stb, input [7:0] set_addr, input [31:0] set_data,
   input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,


   output [WIDTH-1:0] tx_fe_i,
   output [WIDTH-1:0] tx_fe_q,


   input [31:0] sample,
   input run,
   output strobe,
   output [31:0] debug
   );


   wire duc_enb;
   wire [17:0] scale_factor;
   wire [31:0] phase_inc;
   reg [31:0]  phase;
   wire [7:0]  interp_rate;
   wire [3:0]  tx_femux_a, tx_femux_b;
   wire        enable_hb1, enable_hb2;
   wire        rate_change;
   
   setting_reg #(.my_addr(BASE+0)) sr_0
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(phase_inc),.changed());

   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out(scale_factor),.changed());
   
   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
      .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));


   wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
   reg 	       strobe_cic = 1;
   reg 	       strobe_hb1 = 1;
   reg 	       strobe_hb2 = 1;
   
   cic_strober #(.WIDTH(8))
     cic_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		 .strobe_fast(1),.strobe_slow(strobe_cic_pre) );
   cic_strober #(.WIDTH(2))
     hb2_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb2 ? 2 : 1),
		 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
   cic_strober #(.WIDTH(2))
     hb1_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb1 ? 2 : 1),
		 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
   
   always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
   always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
   always @(posedge clk) strobe_cic <= strobe_cic_pre;


   always @(posedge clk)
     if(rst)
       phase <= 0;
     else if(~duc_enb)
       phase <= 0;
     else
       phase <= phase + phase_inc;
   
   wire        signed [17:0] da, db;
   wire        signed [35:0] prod_i, prod_q;

   wire [15:0] bb_i;
   wire [15:0] bb_q;
   wire [17:0] i_interp, q_interp;

   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;

   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;


   
   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
   
   small_hb_int #(.WIDTH(18)) small_hb_interp_i
     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
   small_hb_int #(.WIDTH(18)) small_hb_interp_q
     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
   
   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
     cic_interp_i(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		  .strobe_in(strobe_cic),.strobe_out(1),
		  .signal_in(hb2_i),.signal_out(i_interp));
   
   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
     cic_interp_q(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
		  .strobe_in(strobe_cic),.strobe_out(1),
		  .signal_in(hb2_q),.signal_out(q_interp));

   localparam  cwidth = WIDTH;
   localparam  zwidth = 24;

   wire [cwidth-1:0] da_c, db_c;
   
   cordic_z24 #(.bitwidth(cwidth))
     cordic(.clock(clk), .reset(rst), .enable(duc_enb),
	    .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
	    .zi(phase[31:32-zwidth]),
	    .xo(da_c),.yo(db_c),.zo() );
   
   MULT18X18S MULT18X18S_inst 
     (.P(prod_i),
      .A(da_c[cwidth-1:cwidth-18]),
      .B(scale_factor),
      .C(clk),
      .CE(1),
      .R(rst)
      );
   
   MULT18X18S MULT18X18S_inst_2 
     (.P(prod_q),
      .A(db_c[cwidth-1:cwidth-18]),
      .B(scale_factor),
      .C(clk),
      .CE(1),
      .R(rst)
      );

   dsp_tx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) dsp_tx_glue(
    .clock(clk), .reset(rst), .clear(clr), .enable(run),
    .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
    .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
    .duc_out_i(prod_i[33:34-WIDTH]), .duc_out_q(prod_q[33:34-WIDTH]),
    .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1), .duc_in_enable(duc_enb),
    .bb_sample(sample), .bb_strobe(strobe));

   assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};

endmodule