data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:57: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("peripheralsPWM.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:62: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, peripheralsPWM_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:63: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(2, peripheralsPWM_tb.uut.mprj);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:68: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:82: Unsupported or unknown PLI call: $timeformat\n  $timeformat(-6, 3, "us", 8);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:85: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:121: syntax error, unexpected \'@\'\n  @(posedge pwmOutputs[0]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:130: syntax error, unexpected \'@\'\n  @(negedge pwmOutputs[0]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:138: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:147: syntax error, unexpected \'@\'\n  @(posedge pwmOutputs[1]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:156: syntax error, unexpected \'@\'\n  @(negedge pwmOutputs[1]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:164: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:173: syntax error, unexpected \'@\'\n  @(posedge pwmOutputs[2]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:182: syntax error, unexpected \'@\'\n  @(negedge pwmOutputs[2]);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:191: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);\n  ^\n%Error: Exiting due to 15 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module peripheralsPWM_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire[2:0] pwmOutputs = {mprj_io[16], mprj_io[15], mprj_io[14]};
	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	reg timingValid = 1'b1;

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[37:17] = 24'b0;

	initial begin
		clock = 0;
		timingValid = 1'b1;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$dumpfile("peripheralsPWM.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsPWM_tb);
`else
		$dumpvars(1, peripheralsPWM_tb);
		$dumpvars(2, peripheralsPWM_tb.uut.mprj);
`endif


		repeat (750) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals PWM Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals PWM Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		$timeformat(-6, 3, "us", 8);
		

		@(posedge nextTestOutput);
		

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);




		@(negedge pwmOutputs[0]);
		timerStart = $realtime;


		@(posedge pwmOutputs[0]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 2 Low Time: %t", timerLength);
		if (timerLength < 499800 || timerLength > 500200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 499.800us and 500200us");
		end


		@(negedge pwmOutputs[0]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 2 Period: %t", timerLength);
		if (timerLength < 999800 || timerLength > 1000200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.800us and 1000.200us");
		end

		@(posedge nextTestOutput);




		@(negedge pwmOutputs[1]);
		timerStart = $realtime;


		@(posedge pwmOutputs[1]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 3 Low Time: %t", timerLength);
		if (timerLength < 699800 || timerLength > 700200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 699.800us and 700.200us");
		end


		@(negedge pwmOutputs[1]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 3 Period: %t", timerLength);
		if (timerLength < 999800 || timerLength > 1000200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.800us and 1000.200us");
		end

		@(posedge nextTestOutput);




		@(negedge pwmOutputs[2]);
		timerStart = $realtime;


		@(posedge pwmOutputs[2]);
		timerLength = $realtime - timerStart;
		$display("Device 1 Output 0 Low Time: %t", timerLength);
		if (timerLength < 199900 || timerLength > 200100) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 199.900us and 200.100us");
		end


		@(negedge pwmOutputs[2]);
		timerLength = $realtime - timerStart;
		$display("Device 1 Output 0 Period: %t", timerLength);
		if (timerLength < 999900 || timerLength > 1000100) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.900us and 1000.100us");
		end


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals PWM Timing (GL) Failed");
			`else
				$display ("Monitor: Peripherals PWM Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals PWM Test (GL) Passed");
			`else
				$display("Monitor: Peripherals PWM Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals PWM Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals PWM Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsPWM.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module peripheralsPWM_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire[2:0] pwmOutputs = {mprj_io[16], mprj_io[15], mprj_io[14]};
	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	reg timingValid = 1'b1;

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[37:17] = 24'b0;

	initial begin
		clock = 0;
		timingValid = 1'b1;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$dumpfile("peripheralsPWM.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsPWM_tb);
`else
		$dumpvars(1, peripheralsPWM_tb);
		$dumpvars(2, peripheralsPWM_tb.uut.mprj);
`endif


		repeat (750) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals PWM Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals PWM Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		$timeformat(-6, 3, "us", 8);
		

		@(posedge nextTestOutput);
		

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);




		@(negedge pwmOutputs[0]);
		timerStart = $realtime;


		@(posedge pwmOutputs[0]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 2 Low Time: %t", timerLength);
		if (timerLength < 499800 || timerLength > 500200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 499.800us and 500200us");
		end


		@(negedge pwmOutputs[0]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 2 Period: %t", timerLength);
		if (timerLength < 999800 || timerLength > 1000200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.800us and 1000.200us");
		end

		@(posedge nextTestOutput);




		@(negedge pwmOutputs[1]);
		timerStart = $realtime;


		@(posedge pwmOutputs[1]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 3 Low Time: %t", timerLength);
		if (timerLength < 699800 || timerLength > 700200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 699.800us and 700.200us");
		end


		@(negedge pwmOutputs[1]);
		timerLength = $realtime - timerStart;
		$display("Device 0 Output 3 Period: %t", timerLength);
		if (timerLength < 999800 || timerLength > 1000200) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.800us and 1000.200us");
		end

		@(posedge nextTestOutput);




		@(negedge pwmOutputs[2]);
		timerStart = $realtime;


		@(posedge pwmOutputs[2]);
		timerLength = $realtime - timerStart;
		$display("Device 1 Output 0 Low Time: %t", timerLength);
		if (timerLength < 199900 || timerLength > 200100) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 199.900us and 200.100us");
		end


		@(negedge pwmOutputs[2]);
		timerLength = $realtime - timerStart;
		$display("Device 1 Output 0 Period: %t", timerLength);
		if (timerLength < 999900 || timerLength > 1000100) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 999.900us and 1000.100us");
		end


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals PWM Timing (GL) Failed");
			`else
				$display ("Monitor: Peripherals PWM Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals PWM Test (GL) Passed");
			`else
				$display("Monitor: Peripherals PWM Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals PWM Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals PWM Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsPWM.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule