data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/Comparator.v
data/verilator_xmls/a420d9ad-608e-4007-a608-296417bb904e.xml
module Comparator (
    input [63:0] eqa, eqb,
    input esignedComp,

    output reg eq, lt
);

    always @(*) begin

        eq = (eqa == eqb);

        if (esignedComp == 1'b1)

            lt = ($signed(eqa) < $signed(eqb));
        else

            lt = (eqa < eqb);
    end
endmodule
module Comparator (
    input [63:0] eqa, eqb,
    input esignedComp,

    output reg eq, lt
);


    always @(*) begin

        eq = (eqa == eqb);

        if (esignedComp == 1'b1)

            lt = ($signed(eqa) < $signed(eqb));
        else

            lt = (eqa < eqb);
    end
endmodule