data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:30: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:32: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:34: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:11: Cannot find file containing module: \'D_Flip_Flop_eight_bit\'\nD_Flip_Flop_eight_bit port_map(\n^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/D_Flip_Flop_eight_bit\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/D_Flip_Flop_eight_bit.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/D_Flip_Flop_eight_bit.sv\n             D_Flip_Flop_eight_bit\n             D_Flip_Flop_eight_bit.v\n             D_Flip_Flop_eight_bit.sv\n             obj_dir/D_Flip_Flop_eight_bit\n             obj_dir/D_Flip_Flop_eight_bit.v\n             obj_dir/D_Flip_Flop_eight_bit.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_D_Flip_Flop_eight_bit.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'count1\' generates 32 bits.\n                                                                                  : ... In instance tb_D_Flip_Flop_eight_bit\n  D_test = count1;\n         ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_D_Flip_Flop_eight_bit();

reg [7:0] D_test;
reg Rst_test,Clk_test,set_test;
wire [7:0] Q_test;

integer count1;



D_Flip_Flop_eight_bit port_map(
.D(D_test),
.Rst(Rst_test),
.Clk(Clk_test),
.set(set_test),
.Q(Q_test)

);


initial begin
D_test = 8'b0;
Rst_test = 0;
Clk_test = 0;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;
Rst_test = 1;
#5;
Rst_test = 0;
#5;
end

always begin 

	for(count1 = 0; count1  < 256; count1 = count1 + 1) begin
		D_test = count1;
		Clk_test = 0;
		#5;
		Clk_test = 1;
		#5;
	end

end

endmodule
module tb_D_Flip_Flop_eight_bit();


reg [7:0] D_test;
reg Rst_test,Clk_test,set_test;
wire [7:0] Q_test;

integer count1;



D_Flip_Flop_eight_bit port_map(
.D(D_test),
.Rst(Rst_test),
.Clk(Clk_test),
.set(set_test),
.Q(Q_test)

);


initial begin
D_test = 8'b0;
Rst_test = 0;
Clk_test = 0;
set_test = 0;
#5;
set_test = 1;
#5;
set_test = 0;
#5;
Rst_test = 1;
#5;
Rst_test = 0;
#5;
end

always begin 

	for(count1 = 0; count1  < 256; count1 = count1 + 1) begin
		D_test = count1;
		Clk_test = 0;
		#5;
		Clk_test = 1;
		#5;
	end

end

endmodule