data/full_repos/permissive/42434302/ivltests/pr1587669.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr1587669.v:12: Unsupported or unknown PLI call: $monitor\n      $monitor("time=%0t", $time,": em=", em, ", pz=", pz, ", p=%b", p);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1587669.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 p = p+1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1587669.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1;  \n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fail ();
   reg pz;
   reg [4:0] p;
   wire      em, net0102;

   initial begin
      p = 0;
      pz = 0;

      $monitor("time=%0t", $time,": em=", em, ", pz=", pz, ", p=%b", p);

      while (p < 5'b11111)
	#10 p = p+1;

      #1;
      $finish;
   end

   nr1 I1 (em, net0102, pz, p[0]);
   nr2 I2 (net0102, p[1], p[2], p[3], p[4]);
endmodule
module fail ();

   reg pz;
   reg [4:0] p;
   wire      em, net0102;

   initial begin
      p = 0;
      pz = 0;

      $monitor("time=%0t", $time,": em=", em, ", pz=", pz, ", p=%b", p);

      while (p < 5'b11111)
	#10 p = p+1;

      #1;
      $finish;
   end

   nr1 I1 (em, net0102, pz, p[0]);
   nr2 I2 (net0102, p[1], p[2], p[3], p[4]);
endmodule