data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v
1: b'%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:5: Cannot find include file: fixedpt.vh\n`include "fixedpt.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.v\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.sv\n             fixedpt.vh\n             fixedpt.vh.v\n             fixedpt.vh.sv\n             obj_dir/fixedpt.vh\n             obj_dir/fixedpt.vh.v\n             obj_dir/fixedpt.vh.sv\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:9: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_px,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:10: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_py,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:11: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_x1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:12: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_y1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:13: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_x2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:14: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_y2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:15: Define or directive not defined: \'`FIXPT\'\n  output reg `FIXPT o_function,\n             ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:18: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT s0 = `FIXPT_MUL(i_px - i_x1, i_y2 - i_y1);\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:18: Define or directive not defined: \'`FIXPT_MUL\'\n  wire `FIXPT s0 = `FIXPT_MUL(i_px - i_x1, i_y2 - i_y1);\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:18: syntax error, unexpected \',\'\n  wire `FIXPT s0 = `FIXPT_MUL(i_px - i_x1, i_y2 - i_y1);\n                                         ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:19: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT s1 = `FIXPT_MUL(i_py - i_y1, i_x2 - i_x1);\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:19: Define or directive not defined: \'`FIXPT_MUL\'\n  wire `FIXPT s1 = `FIXPT_MUL(i_py - i_y1, i_x2 - i_x1);\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:19: syntax error, unexpected \',\'\n  wire `FIXPT s1 = `FIXPT_MUL(i_py - i_y1, i_x2 - i_x1);\n                                         ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:31: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_px,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:32: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_py,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:33: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_x1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:34: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_y1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:35: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_x2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:36: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT      i_y2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:37: Define or directive not defined: \'`FIXPT\'\n  output reg `FIXPT o_function,\n             ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:41: Define or directive not defined: \'`FIXPT\'\n  reg `FIXPT s0_a_pipe [0:1];\n      ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:42: Define or directive not defined: \'`FIXPT\'\n  reg `FIXPT s0_b_q;\n      ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:43: Define or directive not defined: \'`FIXPT\'\n  reg `FIXPT s1_a_pipe [0:1];\n      ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:44: Define or directive not defined: \'`FIXPT\'\n  reg `FIXPT s1_b_q;\n      ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:47: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT sq = s0_a_pipe[1] - s1_a_pipe[1];\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:57: Define or directive not defined: \'`FIXPT_MUL\'\n    s0_a_pipe[1]  <= `FIXPT_MUL(s0_a_pipe[0], s0_b_q);\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:57: syntax error, unexpected \',\'\n    s0_a_pipe[1]  <= `FIXPT_MUL(s0_a_pipe[0], s0_b_q);\n                                            ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:58: Define or directive not defined: \'`FIXPT_MUL\'\n    s1_a_pipe[1]  <= `FIXPT_MUL(s1_a_pipe[0], s1_b_q);\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/edge_function.v:58: syntax error, unexpected \',\'\n    s1_a_pipe[1]  <= `FIXPT_MUL(s1_a_pipe[0], s1_b_q);\n                                            ^\n%Error: Exiting due to 30 error(s)\n'
module EdgeFunctionTest(
  input             i_clk,
  input `FIXPT      i_px,
  input `FIXPT      i_py,
  input `FIXPT      i_x1,
  input `FIXPT      i_y1,
  input `FIXPT      i_x2,
  input `FIXPT      i_y2,
  output reg `FIXPT o_function,
  output reg        o_inside
);  
  wire `FIXPT s0 = `FIXPT_MUL(i_px - i_x1, i_y2 - i_y1);
  wire `FIXPT s1 = `FIXPT_MUL(i_py - i_y1, i_x2 - i_x1);

  always @(posedge i_clk)
  begin
    o_function  <= (s0 - s1);
    o_inside    <= (s0 - s1) >= 0;
  end

endmodule
module EdgeFunctionTest(
  input             i_clk,
  input `FIXPT      i_px,
  input `FIXPT      i_py,
  input `FIXPT      i_x1,
  input `FIXPT      i_y1,
  input `FIXPT      i_x2,
  input `FIXPT      i_y2,
  output reg `FIXPT o_function,
  output reg        o_inside
);
  
  wire `FIXPT s0 = `FIXPT_MUL(i_px - i_x1, i_y2 - i_y1);
  wire `FIXPT s1 = `FIXPT_MUL(i_py - i_y1, i_x2 - i_x1);

  always @(posedge i_clk)
  begin
    o_function  <= (s0 - s1);
    o_inside    <= (s0 - s1) >= 0;
  end

endmodule