data/full_repos/permissive/418819021/lab-06/test_ldi.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:12: Define or directive not defined: \'`STAGE_IF\'\n            `STAGE_IF : TEST_LDI = 1\'b1;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:12: syntax error, unexpected \':\', expecting endcase\n            `STAGE_IF : TEST_LDI = 1\'b1;\n                      ^\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:13: Define or directive not defined: \'`STAGE_ID\'\n            `STAGE_ID :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:14: Define or directive not defined: \'`GROUP_REGISTER\'\n            if(uut.control.opcode_group[`GROUP_REGISTER]\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:15: Define or directive not defined: \'`TYPE_LDI\'\n                && uut.control.opcode_type == `TYPE_LDI\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:21: syntax error, unexpected else\n            else\n            ^~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:25: syntax error, unexpected end\n                end\n                ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:26: Define or directive not defined: \'`STAGE_EX\'\n            `STAGE_EX  : TEST_LDI = 1\'b1;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:27: Define or directive not defined: \'`STAGE_MEM\'\n            `STAGE_MEM : TEST_LDI = 1\'b1;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:28: Define or directive not defined: \'`STAGE_WB\'\n            `STAGE_WB  :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:30: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n                && (uut.control.signals[`CONTROL_REG_RD_WRITE])\n                                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:39: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_ldi.vh:48: syntax error, unexpected end\n                end\n                ^~~\n%Error: Cannot continue\n'
function TEST_LDI;
    input integer rd_addr;
    input integer value;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF : TEST_LDI = 1'b1;
            `STAGE_ID :
            if(uut.control.opcode_group[`GROUP_REGISTER]
                && uut.control.opcode_type == `TYPE_LDI
                && uut.control.opcode_imd == value)
            begin
                TEST_LDI = 1'b1;
                $display("LDI R%2d, %3d - ID: OK", uut.control.opcode_rd, uut.control.opcode_imd);
            end
            else
                begin
                    TEST_LDI = 1'bx;
                    $display("LDI R%2d, %3d - ID: FAILED", uut.control.opcode_rd, uut.control.opcode_imd);
                end
            `STAGE_EX  : TEST_LDI = 1'b1;
            `STAGE_MEM : TEST_LDI = 1'b1;
            `STAGE_WB  :
            if((uut.control.writeback_value == value)
                && (uut.control.signals[`CONTROL_REG_RD_WRITE])
                && (uut.rd_addr == rd_addr))
            begin
                TEST_LDI = 1'b1;
                $display("LDI R%2d, %3d - WB: OK (R%2d = %3d)",
                    uut.rd_addr,
                    uut.control.opcode_imd,
                    uut.rd_addr,
                    value);
            end
            else
                begin
                    TEST_LDI = 1'bx;
                    $display("LDI R%2d, %3d - WB: FAILED => (%3d) vs (%3d)",
                        rd_addr,
                        value,
                        uut.control.writeback_value,
                        value);
                end
        endcase
    end

endfunction
function TEST_LDI;

    input integer rd_addr;
    input integer value;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF : TEST_LDI = 1'b1;
            `STAGE_ID :
            if(uut.control.opcode_group[`GROUP_REGISTER]
                && uut.control.opcode_type == `TYPE_LDI
                && uut.control.opcode_imd == value)
            begin
                TEST_LDI = 1'b1;
                $display("LDI R%2d, %3d - ID: OK", uut.control.opcode_rd, uut.control.opcode_imd);
            end
            else
                begin
                    TEST_LDI = 1'bx;
                    $display("LDI R%2d, %3d - ID: FAILED", uut.control.opcode_rd, uut.control.opcode_imd);
                end
            `STAGE_EX  : TEST_LDI = 1'b1;
            `STAGE_MEM : TEST_LDI = 1'b1;
            `STAGE_WB  :
            if((uut.control.writeback_value == value)
                && (uut.control.signals[`CONTROL_REG_RD_WRITE])
                && (uut.rd_addr == rd_addr))
            begin
                TEST_LDI = 1'b1;
                $display("LDI R%2d, %3d - WB: OK (R%2d = %3d)",
                    uut.rd_addr,
                    uut.control.opcode_imd,
                    uut.rd_addr,
                    value);
            end
            else
                begin
                    TEST_LDI = 1'bx;
                    $display("LDI R%2d, %3d - WB: FAILED => (%3d) vs (%3d)",
                        rd_addr,
                        value,
                        uut.control.writeback_value,
                        value);
                end
        endcase
    end

endfunction