data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1.v
data/verilator_xmls/91841408-e348-42c9-ad78-f5bdf143bae4.xml
module mux_2to1 (input SEL, D0, D1, output reg OUT);

    always @(SEL or D0 or D1) begin

        if (SEL)
            OUT = D1;
        else
            OUT = D0;
        
    end
    
endmodule
module mux_2to1 (input SEL, D0, D1, output reg OUT);


    always @(SEL or D0 or D1) begin

        if (SEL)
            OUT = D1;
        else
            OUT = D0;
        
    end
    
endmodule