data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_throughout.sv
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_throughout.sv:8: syntax error, unexpected |=>, expecting ')'\n  a |=> b throughout (c ##1 d)\n    ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_throughout.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: 'throughout'\n  a |=> b throughout (c ##1 d)\n          ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top (
	input clk,
	input a, b, c, d
);
	default clocking @(posedge clk); endclocking

	assert property (
		a |=> b throughout (c ##1 d)
	);

`ifndef FAIL
	assume property (
		a |=> b && c
	);
	assume property (
		b && c |=> b && d
	);
`endif
endmodule
module top (
	input clk,
	input a, b, c, d
);

	default clocking @(posedge clk); endclocking

	assert property (
		a |=> b throughout (c ##1 d)
	);

`ifndef FAIL
	assume property (
		a |=> b && c
	);
	assume property (
		b && c |=> b && d
	);
`endif
endmodule