data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:191: Signal definition not found, creating implicitly: \'pt_blk_new_openbank_d1\'\n                                                                                              : ... Suggested alternative: \'pt_blk_new_openbank\'\nassign pt_ch0_blk_new_openbank = pt_blk_new_openbank_d1;\n                                 ^~~~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:115: Cannot find file containing module: \'dffsl_async_ns\'\ndffsl_async_ns #(17)   ff_max_banks_open(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffsl_async_ns\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffsl_async_ns.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffsl_async_ns.sv\n             dffsl_async_ns\n             dffsl_async_ns.v\n             dffsl_async_ns.sv\n             obj_dir/dffsl_async_ns\n             obj_dir/dffsl_async_ns.v\n             obj_dir/dffsl_async_ns.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:137: Cannot find file containing module: \'dffsl_async_ns\'\ndffsl_async_ns #(16)   ff_max_time(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:160: Cannot find file containing module: \'dffrle_ns\'\ndffrle_ns #(17) ff_banks_open(\n^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:174: Cannot find file containing module: \'dffrl_ns\'\ndffrl_ns #(16) ff_time_cntr(\n^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_pt.v:186: Cannot find file containing module: \'dff_ns\'\ndff_ns #(1)       ff_blk_openbank(\n^~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module dram_pt(

   pt_ch0_blk_new_openbank, pt_ch1_blk_new_openbank, 
   pt_max_banks_open, pt_max_time, dram_pt_max_banks_open_valid, 
   dram_pt_max_time_valid, dram_pt_ucb_data, 

   clk, rst_l, dram_local_pt0_opened_bank, 
   dram_local_pt1_opened_bank, dram_other_pt0_opened_bank, 
   dram_other_pt1_opened_bank, que_max_banks_open_valid0, 
   que_max_banks_open_valid1, que_max_banks_open0, 
   que_max_banks_open1, que_max_time_valid0, que_max_time_valid1, 
   arst_l, 
   dram_other_pt_max_banks_open_valid, dram_other_pt_max_time_valid, 
   dram_other_pt_ucb_data
   );




output		pt_ch0_blk_new_openbank;
output		pt_ch1_blk_new_openbank;


output [16:0]	pt_max_banks_open;
output [15:0]	pt_max_time;


output 		dram_pt_max_banks_open_valid;
output 		dram_pt_max_time_valid;
output [16:0]	dram_pt_ucb_data;




input		clk;
input		rst_l;
input		dram_local_pt0_opened_bank;
input		dram_local_pt1_opened_bank;
input		dram_other_pt0_opened_bank;
input		dram_other_pt1_opened_bank;


input          	que_max_banks_open_valid0;
input          	que_max_banks_open_valid1;
input [16:0]	que_max_banks_open0;
input [16:0]	que_max_banks_open1;

input          	que_max_time_valid0;
input          	que_max_time_valid1;

input		arst_l;


input 		dram_other_pt_max_banks_open_valid;
input 		dram_other_pt_max_time_valid;
input [16:0]	dram_other_pt_ucb_data;




wire [15:0]	pt_time_cntr_in;
wire [15:0]	pt_time_cntr;








wire pt_other_pt0_opened_bank = dram_other_pt0_opened_bank;
wire pt_other_pt1_opened_bank = dram_other_pt1_opened_bank;



assign dram_pt_max_banks_open_valid = que_max_banks_open_valid0 | que_max_banks_open_valid1;
assign dram_pt_max_time_valid = que_max_time_valid0 | que_max_time_valid1;
assign dram_pt_ucb_data = que_max_banks_open_valid0 ? que_max_banks_open0[16:0] : 
				que_max_banks_open_valid1 ? que_max_banks_open1[16:0] :
		que_max_time_valid0 ? {1'b0, que_max_banks_open0[15:0]} : {1'b0, que_max_banks_open1[15:0]};






wire [16:0]     pt_max_banks_open_in;

assign pt_max_banks_open_in =  ~rst_l ? pt_max_banks_open[16:0] : 
				dram_other_pt_max_banks_open_valid ? dram_other_pt_ucb_data :
				que_max_banks_open_valid0 ? que_max_banks_open0[16:0] : 
				que_max_banks_open_valid1 ? que_max_banks_open1[16:0] :
				pt_max_banks_open[16:0];

dffsl_async_ns #(17)   ff_max_banks_open(
                .din(pt_max_banks_open_in[16:0]),
                .q(pt_max_banks_open[16:0]),
                .set_l(arst_l),
                .clk(clk));







wire            pt_max_time_en;
wire [15:0]     pt_max_time_in;

assign pt_max_time_en = ~rst_l | que_max_time_valid0 | que_max_time_valid1 | dram_other_pt_max_time_valid;
assign pt_max_time_in =  ~rst_l ? pt_max_time[15:0] : 
				dram_other_pt_max_time_valid ? dram_other_pt_ucb_data[15:0] :
				que_max_time_valid0 ? que_max_banks_open0[15:0] : 
				que_max_time_valid1 ? que_max_banks_open1[15:0] :
				pt_max_time[15:0];

dffsl_async_ns #(16)   ff_max_time(
                .din(pt_max_time_in[15:0]),
                .q(pt_max_time[15:0]),
                .set_l(arst_l),
                .clk(clk));






wire            pt_banks_open_en;
wire [16:0]     pt_banks_open_in;
wire [16:0]     pt_banks_open;

assign pt_banks_open_en = dram_local_pt0_opened_bank | dram_local_pt1_opened_bank |
				pt_other_pt0_opened_bank | pt_other_pt1_opened_bank;
assign pt_banks_open_in = pt_banks_open[16:0] + {16'h0,dram_local_pt0_opened_bank} + 
				{16'h0, dram_local_pt1_opened_bank} +
				{16'h0, pt_other_pt0_opened_bank} + 
				{16'h0, pt_other_pt1_opened_bank}; 
wire pt_banks_open_rst_l = rst_l & ~(pt_max_time[15:0] == pt_time_cntr[15:0]);

dffrle_ns #(17) ff_banks_open(
                .din(pt_banks_open_in[16:0]),
                .q(pt_banks_open[16:0]),
		.rst_l(pt_banks_open_rst_l),
                .en(pt_banks_open_en),
                .clk(clk));





assign pt_time_cntr_in[15:0] = pt_time_cntr[15:0] + 16'b1;
wire pt_time_cntr_rst_l = rst_l & ~(pt_time_cntr[15:0] >= pt_max_time[15:0]);

dffrl_ns #(16) ff_time_cntr(
                .din(pt_time_cntr_in[15:0]),
                .q(pt_time_cntr[15:0]),
		.rst_l(pt_time_cntr_rst_l),
                .clk(clk));





wire pt_blk_new_openbank = (pt_banks_open_in[16:0] >= pt_max_banks_open[16:0]);

dff_ns #(1)       ff_blk_openbank(
                .din(pt_blk_new_openbank),
                .q(pt_blk_new_openbank_d1),
                .clk(clk));

assign pt_ch0_blk_new_openbank = pt_blk_new_openbank_d1;
assign pt_ch1_blk_new_openbank = pt_blk_new_openbank_d1;

endmodule
module dram_pt(

   pt_ch0_blk_new_openbank, pt_ch1_blk_new_openbank, 
   pt_max_banks_open, pt_max_time, dram_pt_max_banks_open_valid, 
   dram_pt_max_time_valid, dram_pt_ucb_data, 

   clk, rst_l, dram_local_pt0_opened_bank, 
   dram_local_pt1_opened_bank, dram_other_pt0_opened_bank, 
   dram_other_pt1_opened_bank, que_max_banks_open_valid0, 
   que_max_banks_open_valid1, que_max_banks_open0, 
   que_max_banks_open1, que_max_time_valid0, que_max_time_valid1, 
   arst_l, 
   dram_other_pt_max_banks_open_valid, dram_other_pt_max_time_valid, 
   dram_other_pt_ucb_data
   );





output		pt_ch0_blk_new_openbank;
output		pt_ch1_blk_new_openbank;


output [16:0]	pt_max_banks_open;
output [15:0]	pt_max_time;


output 		dram_pt_max_banks_open_valid;
output 		dram_pt_max_time_valid;
output [16:0]	dram_pt_ucb_data;




input		clk;
input		rst_l;
input		dram_local_pt0_opened_bank;
input		dram_local_pt1_opened_bank;
input		dram_other_pt0_opened_bank;
input		dram_other_pt1_opened_bank;


input          	que_max_banks_open_valid0;
input          	que_max_banks_open_valid1;
input [16:0]	que_max_banks_open0;
input [16:0]	que_max_banks_open1;

input          	que_max_time_valid0;
input          	que_max_time_valid1;

input		arst_l;


input 		dram_other_pt_max_banks_open_valid;
input 		dram_other_pt_max_time_valid;
input [16:0]	dram_other_pt_ucb_data;




wire [15:0]	pt_time_cntr_in;
wire [15:0]	pt_time_cntr;








wire pt_other_pt0_opened_bank = dram_other_pt0_opened_bank;
wire pt_other_pt1_opened_bank = dram_other_pt1_opened_bank;



assign dram_pt_max_banks_open_valid = que_max_banks_open_valid0 | que_max_banks_open_valid1;
assign dram_pt_max_time_valid = que_max_time_valid0 | que_max_time_valid1;
assign dram_pt_ucb_data = que_max_banks_open_valid0 ? que_max_banks_open0[16:0] : 
				que_max_banks_open_valid1 ? que_max_banks_open1[16:0] :
		que_max_time_valid0 ? {1'b0, que_max_banks_open0[15:0]} : {1'b0, que_max_banks_open1[15:0]};






wire [16:0]     pt_max_banks_open_in;

assign pt_max_banks_open_in =  ~rst_l ? pt_max_banks_open[16:0] : 
				dram_other_pt_max_banks_open_valid ? dram_other_pt_ucb_data :
				que_max_banks_open_valid0 ? que_max_banks_open0[16:0] : 
				que_max_banks_open_valid1 ? que_max_banks_open1[16:0] :
				pt_max_banks_open[16:0];

dffsl_async_ns #(17)   ff_max_banks_open(
                .din(pt_max_banks_open_in[16:0]),
                .q(pt_max_banks_open[16:0]),
                .set_l(arst_l),
                .clk(clk));







wire            pt_max_time_en;
wire [15:0]     pt_max_time_in;

assign pt_max_time_en = ~rst_l | que_max_time_valid0 | que_max_time_valid1 | dram_other_pt_max_time_valid;
assign pt_max_time_in =  ~rst_l ? pt_max_time[15:0] : 
				dram_other_pt_max_time_valid ? dram_other_pt_ucb_data[15:0] :
				que_max_time_valid0 ? que_max_banks_open0[15:0] : 
				que_max_time_valid1 ? que_max_banks_open1[15:0] :
				pt_max_time[15:0];

dffsl_async_ns #(16)   ff_max_time(
                .din(pt_max_time_in[15:0]),
                .q(pt_max_time[15:0]),
                .set_l(arst_l),
                .clk(clk));






wire            pt_banks_open_en;
wire [16:0]     pt_banks_open_in;
wire [16:0]     pt_banks_open;

assign pt_banks_open_en = dram_local_pt0_opened_bank | dram_local_pt1_opened_bank |
				pt_other_pt0_opened_bank | pt_other_pt1_opened_bank;
assign pt_banks_open_in = pt_banks_open[16:0] + {16'h0,dram_local_pt0_opened_bank} + 
				{16'h0, dram_local_pt1_opened_bank} +
				{16'h0, pt_other_pt0_opened_bank} + 
				{16'h0, pt_other_pt1_opened_bank}; 
wire pt_banks_open_rst_l = rst_l & ~(pt_max_time[15:0] == pt_time_cntr[15:0]);

dffrle_ns #(17) ff_banks_open(
                .din(pt_banks_open_in[16:0]),
                .q(pt_banks_open[16:0]),
		.rst_l(pt_banks_open_rst_l),
                .en(pt_banks_open_en),
                .clk(clk));





assign pt_time_cntr_in[15:0] = pt_time_cntr[15:0] + 16'b1;
wire pt_time_cntr_rst_l = rst_l & ~(pt_time_cntr[15:0] >= pt_max_time[15:0]);

dffrl_ns #(16) ff_time_cntr(
                .din(pt_time_cntr_in[15:0]),
                .q(pt_time_cntr[15:0]),
		.rst_l(pt_time_cntr_rst_l),
                .clk(clk));





wire pt_blk_new_openbank = (pt_banks_open_in[16:0] >= pt_max_banks_open[16:0]);

dff_ns #(1)       ff_blk_openbank(
                .din(pt_blk_new_openbank),
                .q(pt_blk_new_openbank_d1),
                .clk(clk));

assign pt_ch0_blk_new_openbank = pt_blk_new_openbank_d1;
assign pt_ch1_blk_new_openbank = pt_blk_new_openbank_d1;

endmodule