data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.v:42: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.v:65: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;\n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.v:71: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg [WIDTH-1:0] do;\n                ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/iramrwpx.v:89: syntax error, unexpected <=\n            do  <= ram[ra];\n                ^~\n%Error: Cannot continue\n"
module iramrwpx
    (
     wclk,
     wa,
     we,
     di,
     
     rclk,
     ra,
     re,
     do,
     
     test,
     mask
     );

parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter DISPLAY_ERR_RAM_WR = "ON";
parameter DISPLAY_ERR_RAM_RD = "ON";
parameter ERR_RAM_WR_X  = "ON";
parameter ERR_RAM_RD_X  = "ON";

input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;
input               mask;
input               test;

reg [WIDTH-1:0] ram [DEPTH-1:0];

reg [WIDTH-1:0] do;

integer i;
initial begin for(i=0;i<DEPTH;i=i+1) ram[i] = {WIDTH{1'b0}}; end

always @ (posedge wclk)
    begin
    if (we)
            begin
            ram[wa] <= di;
            end
         
    end

always @ (posedge rclk)
    begin
    if (re)
            begin
            do  <= ram[ra];
            end
    else    do  <= {WIDTH{1'bx}};
    end


endmodule
module iramrwpx
    (
     wclk,
     wa,
     we,
     di,
     
     rclk,
     ra,
     re,
     do,
     
     test,
     mask
     );


parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter DISPLAY_ERR_RAM_WR = "ON";
parameter DISPLAY_ERR_RAM_RD = "ON";
parameter ERR_RAM_WR_X  = "ON";
parameter ERR_RAM_RD_X  = "ON";

input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;
input               mask;
input               test;

reg [WIDTH-1:0] ram [DEPTH-1:0];

reg [WIDTH-1:0] do;

integer i;
initial begin for(i=0;i<DEPTH;i=i+1) ram[i] = {WIDTH{1'b0}}; end

always @ (posedge wclk)
    begin
    if (we)
            begin
            ram[wa] <= di;
            end
         
    end

always @ (posedge rclk)
    begin
    if (re)
            begin
            do  <= ram[ra];
            end
    else    do  <= {WIDTH{1'bx}};
    end


endmodule