data/full_repos/permissive/501138203/verilog/rtl/ChalShiftReg.v
1: b'%Error: data/full_repos/permissive/501138203/verilog/rtl/ChalShiftReg.v:5: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module ChalShiftReg
(
  input wire  clk,
  input wire si,
  input wire rstn,
  output [127:0] c,
  output wire so
);

  reg [127:0] c;


  always @ (posedge clk or negedge rstn) begin
    if (~rstn) begin
      c[127:0] <= 0;
    end else begin
      c[127:0] <= {c[126:0], si};
    end
  end

  assign so = c[127];

endmodule
module ChalShiftReg
(
  input wire  clk,
  input wire si,
  input wire rstn,
  output [127:0] c,
  output wire so
);


  reg [127:0] c;


  always @ (posedge clk or negedge rstn) begin
    if (~rstn) begin
      c[127:0] <= 0;
    end else begin
      c[127:0] <= {c[126:0], si};
    end
  end

  assign so = c[127];

endmodule