data/full_repos/permissive/409594175/made/ShiftLeft26.v
data/verilator_xmls/2d38b4ad-1bc9-4ceb-b347-c144f9f59a38.xml
module ShiftLeft26(
    input  wire [25:0] data_in,
    output wire [27:0] shift_left_26_out
);

    wire [27:0] data;

    assign data = {{2{1'b0}}, data_in};
    assign shift_left_26_out = data << 2;

endmodule
module ShiftLeft26(
    input  wire [25:0] data_in,
    output wire [27:0] shift_left_26_out
);


    wire [27:0] data;

    assign data = {{2{1'b0}}, data_in};
    assign shift_left_26_out = data << 2;

endmodule