data/full_repos/permissive/46981098/cpu_eda.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46981098/cpu_eda.v:277: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'mux5_2to1\'\nmodule mux5_2to1(out, in0, in1, sel);\n       ^~~~~~~~~\n                                                                    : ... Top module \'cpu\'\nmodule cpu (\n       ^~~\n%Error: data/full_repos/permissive/46981098/cpu_eda.v:298: Duplicate declaration of signal: \'pc\'\n    reg[31:0] pc;\n              ^~\n        data/full_repos/permissive/46981098/cpu_eda.v:280: ... Location of original declaration\n     output reg [31:0] pc,\n                       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/46981098/cpu_eda.v:354: Signal definition not found, creating implicitly: \'mux05_result\'\n                                                                    : ... Suggested alternative: \'mux04_result\'\n   mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);\n                     ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module mux32_3to1 (out, in0, in1, in2, sel);
  	output reg  [31:0] out;
	input [31:0] in0;
	input [31:0] in1;
	input [31:0] in2;
  	input [1:0] sel;

  	always @(sel)
    begin
		case (sel)
			2'b00: out = in0;
			2'b01: out = in1;
			2'b10: out = in2;
		endcase
    end
endmodule
module mux32_3to1 (out, in0, in1, in2, sel);

  	output reg  [31:0] out;
	input [31:0] in0;
	input [31:0] in1;
	input [31:0] in2;
  	input [1:0] sel;

  	always @(sel)
    begin
		case (sel)
			2'b00: out = in0;
			2'b01: out = in1;
			2'b10: out = in2;
		endcase
    end
endmodule