data/full_repos/permissive/448780010/code/mycpu_core.v
1: b'%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:1: Cannot find include file: mycpu.h\n`include "mycpu.h" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.v\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.sv\n             mycpu.h\n             mycpu.h.v\n             mycpu.h.sv\n             obj_dir/mycpu.h\n             obj_dir/mycpu.h.v\n             obj_dir/mycpu.h.sv\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:46: Define or directive not defined: \'`FS_TO_DS_BUS_WD\'\nwire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:47: Define or directive not defined: \'`DS_TO_ES_BUS_WD\'\nwire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:48: Define or directive not defined: \'`ES_TO_MS_BUS_WD\'\nwire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:49: Define or directive not defined: \'`MS_TO_WS_BUS_WD\'\nwire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:50: Define or directive not defined: \'`WS_TO_RF_BUS_WD\'\nwire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:51: Define or directive not defined: \'`BR_BUS_WD\'\nwire [`BR_BUS_WD       -1:0] br_bus;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:52: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_es_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:53: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_ms_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:54: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_ws_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:57: Define or directive not defined: \'`ES_REFLUSH_FS_WD\'\nwire [`ES_REFLUSH_FS_WD -1:0]es_reflush_fs_bus;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:61: Define or directive not defined: \'`PFS_TO_FS_BUS_WD\'\nwire [`PFS_TO_FS_BUS_WD - 1:0] pfs_to_fs_bus;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:128: Define or directive not defined: \'`ES_TO_FS_BUS_WD\'\nwire [`ES_TO_FS_BUS_WD - 1 :0] es_to_fs_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module mycpu_core
#(
    parameter TLBNUM = 16
)
(
    input         clk,
    input         resetn,

    output        inst_sram_req,
    output        inst_sram_wr,
    output [ 1:0] inst_sram_size,
    output [ 3:0] inst_sram_wstrb,
    output [31:0] inst_sram_addr,
    output [31:0] inst_sram_wdata,
    input         inst_sram_addr_ok,
    input         inst_sram_data_ok,
    input  [31:0] inst_sram_rdata,

    output        data_sram_req,
    output        data_sram_wr,
    output [ 1:0] data_sram_size,
    output [ 3:0] data_sram_wstrb,
    output [31:0] data_sram_addr,
    output [31:0] data_sram_wdata,
    input         data_sram_addr_ok,
    input         data_sram_data_ok,
    input  [31:0] data_sram_rdata,

    output [31:0] debug_wb_pc,
    output [ 3:0] debug_wb_rf_wen,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
);
reg         reset;
always @(posedge clk) reset <= ~resetn; 

wire         ds_allowin;
wire         es_allowin;
wire         ms_allowin;
wire         ws_allowin;
wire         fs_to_ds_valid;
wire         ds_to_es_valid;
wire         es_to_ms_valid;
wire         ms_to_ws_valid;
wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [`BR_BUS_WD       -1:0] br_bus;
wire [`RAW_BUS_WD      -1:0] raw_es_bus;
wire [`RAW_BUS_WD      -1:0] raw_ms_bus;
wire [`RAW_BUS_WD      -1:0] raw_ws_bus;
wire                         blk_es_load;
wire                         es_reflush_ds;
wire [`ES_REFLUSH_FS_WD -1:0]es_reflush_fs_bus;
wire                         ms_to_es_valid;
wire                         ws_to_es_valid;
wire                         has_int;
wire [`PFS_TO_FS_BUS_WD - 1:0] pfs_to_fs_bus;
wire                         pfs_to_fs_valid;
wire                         fs_allow_in;
wire                         fs_inst_unable;
wire                         blk_ms_load;

wire [              18:0]    s0_vppn;
wire                         s0_va_bit12;
wire [               9:0]    s0_asid;
wire                         s0_found;
wire [$clog2(TLBNUM)-1:0]    s0_index;
wire [              19:0]    s0_ppn;
wire [               5:0]    s0_ps;
wire [               1:0]    s0_plv;
wire [               1:0]    s0_mat;
wire                         s0_d;
wire                         s0_v;

wire  [              18:0]   s1_vppn;
wire                         s1_va_bit12;
wire  [               9:0]   s1_asid;
wire                         s1_found;
wire [$clog2(TLBNUM)-1:0]    s1_index;
wire [              19:0]    s1_ppn;
wire [               5:0]    s1_ps;
wire [               1:0]    s1_plv;
wire [               1:0]    s1_mat;
wire                         s1_d;
wire                         s1_v;

wire                         invtlb_valid;
wire  [               4:0]   invtlb_op;

wire                         we;
wire  [$clog2(TLBNUM)-1:0]   w_index;
wire                         w_e;
wire  [               5:0]   w_ps;
wire  [              18:0]   w_vppn;
wire  [               9:0]   w_asid;
wire                         w_g;
wire  [              19:0]   w_ppn0;
wire  [               1:0]   w_plv0;
wire  [               1:0]   w_mat0;
wire                         w_d0;
wire                         w_v0;
wire  [              19:0]   w_ppn1;
wire  [               1:0]   w_plv1;
wire  [               1:0]   w_mat1;
wire                         w_d1;
wire                         w_v1;

wire  [$clog2(TLBNUM)-1:0]   r_index;
wire                         r_e;
wire [              18:0]    r_vppn;
wire [               5:0]    r_ps;
wire [               9:0]    r_asid;
wire                         r_g;
wire [              19:0]    r_ppn0;
wire [               1:0]    r_plv0;
wire [               1:0]    r_mat0;
wire                         r_d0;
wire                         r_v0;
wire [              19:0]    r_ppn1;     
wire [               1:0]    r_plv1;
wire [               1:0]    r_mat1;
wire                         r_d1;
wire                         r_v1;
wire [`ES_TO_FS_BUS_WD - 1 :0] es_to_fs_bus;



if_stage if_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ds_allowin     (ds_allowin     ),

    .br_bus         (br_bus         ),
    

    .fs_to_ds_valid (fs_to_ds_valid ),
    .fs_to_ds_bus   (fs_to_ds_bus   ),
    .es_to_fs_bus   (es_to_fs_bus   ),

    .es_reflush_fs_bus(es_reflush_fs_bus),

    .inst_sram_req  (inst_sram_req  ),
    .inst_sram_wr   (inst_sram_wr   ),
    .inst_sram_size (inst_sram_size ),
    .inst_sram_wstrb(inst_sram_wstrb),
    .inst_sram_addr (inst_sram_addr ),
    .inst_sram_wdata(inst_sram_wdata),
    .inst_sram_addr_ok(inst_sram_addr_ok),
    .inst_sram_data_ok(inst_sram_data_ok),
    .inst_sram_rdata(inst_sram_rdata),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           )
);

id_stage id_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .es_allowin     (es_allowin     ),
    .ds_allowin     (ds_allowin     ),

    .fs_to_ds_valid (fs_to_ds_valid ),
    .fs_to_ds_bus   (fs_to_ds_bus   ),

    .ds_to_es_valid (ds_to_es_valid ),
    .ds_to_es_bus   (ds_to_es_bus   ),

    .br_bus         (br_bus         ),

    .ws_to_rf_bus   (ws_to_rf_bus   ),

    .raw_es_bus     (raw_es_bus     ),
    .raw_ms_bus     (raw_ms_bus     ),
    .raw_ws_bus     (raw_ws_bus     ),

    .es_reflush_ds  (es_reflush_ds  ),

    .has_int        (has_int        ),

    .blk_es_load    (blk_es_load    ),
    .blk_ms_load    (blk_ms_load    )
);

exe_stage exe_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ms_allowin     (ms_allowin     ),
    .es_allowin     (es_allowin     ),

    .ds_to_es_valid (ds_to_es_valid ),
    .ds_to_es_bus   (ds_to_es_bus   ),

    .ms_to_es_valid (ms_to_es_valid ),

    .ws_to_es_valid (ws_to_es_valid ),

    .es_to_ms_valid (es_to_ms_valid ),
    .es_to_ms_bus   (es_to_ms_bus   ),

    .data_sram_req  (data_sram_req  ),
    .data_sram_wr   (data_sram_wr   ),
    .data_sram_size (data_sram_size ),
    .data_sram_wstrb(data_sram_wstrb),
    .data_sram_addr (data_sram_addr ),
    .data_sram_wdata(data_sram_wdata),
    .data_sram_addr_ok(data_sram_addr_ok),

    .raw_es_bus     (raw_es_bus     ),

    .es_reflush_fs_bus(es_reflush_fs_bus),
    .es_reflush_ds  (es_reflush_ds  ),

    .has_int        (has_int        ),

    .blk_es_load    (blk_es_load    ),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           ),

    .s1_vppn       (s1_vppn        ),
    .s1_va_bit12   (s1_va_bit12    ),
    .s1_asid       (s1_asid        ),
    .s1_found      (s1_found       ),
    .s1_index      (s1_index       ),
    .s1_ppn        (s1_ppn         ),
    .s1_ps         (s1_ps          ),
    .s1_plv        (s1_plv         ),
    .s1_mat        (s1_mat         ),
    .s1_d          (s1_d           ),
    .s1_v          (s1_v           ),

    .invtlb_valid  (invtlb_valid   ),
    .invtlb_op     (invtlb_op      ),

    .we            (we             ),
    .w_index       (w_index        ),
    .w_e           (w_e            ),
    .w_ps          (w_ps           ),
    .w_vppn        (w_vppn         ),
    .w_asid        (w_asid         ),
    .w_g           (w_g            ),
    .w_ppn0        (w_ppn0         ),
    .w_plv0        (w_plv0         ),
    .w_mat0        (w_mat0         ),
    .w_d0          (w_d0           ),
    .w_v0          (w_v0           ),
    .w_ppn1        (w_ppn1         ),
    .w_plv1        (w_plv1         ),
    .w_mat1        (w_mat1         ),
    .w_d1          (w_d1           ),
    .w_v1          (w_v1           ),

    .r_index       (r_index        ),
    .r_e           (r_e            ),
    .r_vppn        (r_vppn         ),
    .r_ps          (r_ps           ),
    .r_asid        (r_asid         ),
    .r_g           (r_g            ),
    .r_ppn0        (r_ppn0         ),
    .r_plv0        (r_plv0         ),
    .r_mat0        (r_mat0         ),
    .r_d0          (r_d0           ),
    .r_v0          (r_v0           ),
    .r_ppn1        (r_ppn1         ),     
    .r_plv1        (r_plv1         ),
    .r_mat1        (r_mat1         ),
    .r_d1          (r_d1           ),
    .r_v1          (r_v1           ),
    .es_to_fs_bus  (es_to_fs_bus   )
);

mem_stage mem_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ws_allowin     (ws_allowin     ),
    .ms_allowin     (ms_allowin     ),

    .es_to_ms_valid (es_to_ms_valid ),
    .es_to_ms_bus   (es_to_ms_bus   ),

    .ms_to_ws_valid (ms_to_ws_valid ),
    .ms_to_ws_bus   (ms_to_ws_bus   ),

    .ms_to_es_valid (ms_to_es_valid ),

    .data_sram_data_ok(data_sram_data_ok),
    .data_sram_rdata(data_sram_rdata),

    .raw_ms_bus     (raw_ms_bus     ),
    .blk_ms_load    (blk_ms_load    )
);

wb_stage wb_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ws_allowin     (ws_allowin     ),

    .ms_to_ws_valid (ms_to_ws_valid ),
    .ms_to_ws_bus   (ms_to_ws_bus   ),

    .ws_to_rf_bus   (ws_to_rf_bus   ),

    .ws_to_es_valid (ws_to_es_valid ),

    .raw_ws_bus     (raw_ws_bus     ),

    .debug_wb_pc      (debug_wb_pc      ),
    .debug_wb_rf_wen  (debug_wb_rf_wen  ),
    .debug_wb_rf_wnum (debug_wb_rf_wnum ),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);


tlb tlb(
    .clk           (clk            ),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           ),

    .s1_vppn       (s1_vppn        ),
    .s1_va_bit12   (s1_va_bit12    ),
    .s1_asid       (s1_asid        ),
    .s1_found      (s1_found       ),
    .s1_index      (s1_index       ),
    .s1_ppn        (s1_ppn         ),
    .s1_ps         (s1_ps          ),
    .s1_plv        (s1_plv         ),
    .s1_mat        (s1_mat         ),
    .s1_d          (s1_d           ),
    .s1_v          (s1_v           ),

    .invtlb_valid  (invtlb_valid   ),
    .invtlb_op     (invtlb_op      ),

    .we            (we             ),
    .w_index       (w_index        ),
    .w_e           (w_e            ),
    .w_ps          (w_ps           ),
    .w_vppn        (w_vppn         ),
    .w_asid        (w_asid         ),
    .w_g           (w_g            ),
    .w_ppn0        (w_ppn0         ),
    .w_plv0        (w_plv0         ),
    .w_mat0        (w_mat0         ),
    .w_d0          (w_d0           ),
    .w_v0          (w_v0           ),
    .w_ppn1        (w_ppn1         ),
    .w_plv1        (w_plv1         ),
    .w_mat1        (w_mat1         ),
    .w_d1          (w_d1           ),
    .w_v1          (w_v1           ),

    .r_index       (r_index        ),
    .r_e           (r_e            ),
    .r_vppn        (r_vppn         ),
    .r_ps          (r_ps           ),
    .r_asid        (r_asid         ),
    .r_g           (r_g            ),
    .r_ppn0        (r_ppn0         ),
    .r_plv0        (r_plv0         ),
    .r_mat0        (r_mat0         ),
    .r_d0          (r_d0           ),
    .r_v0          (r_v0           ),
    .r_ppn1        (r_ppn1         ),     
    .r_plv1        (r_plv1         ),
    .r_mat1        (r_mat1         ),
    .r_d1          (r_d1           ),
    .r_v1          (r_v1           )
);
endmodule
module mycpu_core
#(
    parameter TLBNUM = 16
)
(
    input         clk,
    input         resetn,

    output        inst_sram_req,
    output        inst_sram_wr,
    output [ 1:0] inst_sram_size,
    output [ 3:0] inst_sram_wstrb,
    output [31:0] inst_sram_addr,
    output [31:0] inst_sram_wdata,
    input         inst_sram_addr_ok,
    input         inst_sram_data_ok,
    input  [31:0] inst_sram_rdata,

    output        data_sram_req,
    output        data_sram_wr,
    output [ 1:0] data_sram_size,
    output [ 3:0] data_sram_wstrb,
    output [31:0] data_sram_addr,
    output [31:0] data_sram_wdata,
    input         data_sram_addr_ok,
    input         data_sram_data_ok,
    input  [31:0] data_sram_rdata,

    output [31:0] debug_wb_pc,
    output [ 3:0] debug_wb_rf_wen,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
);

reg         reset;
always @(posedge clk) reset <= ~resetn; 

wire         ds_allowin;
wire         es_allowin;
wire         ms_allowin;
wire         ws_allowin;
wire         fs_to_ds_valid;
wire         ds_to_es_valid;
wire         es_to_ms_valid;
wire         ms_to_ws_valid;
wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [`BR_BUS_WD       -1:0] br_bus;
wire [`RAW_BUS_WD      -1:0] raw_es_bus;
wire [`RAW_BUS_WD      -1:0] raw_ms_bus;
wire [`RAW_BUS_WD      -1:0] raw_ws_bus;
wire                         blk_es_load;
wire                         es_reflush_ds;
wire [`ES_REFLUSH_FS_WD -1:0]es_reflush_fs_bus;
wire                         ms_to_es_valid;
wire                         ws_to_es_valid;
wire                         has_int;
wire [`PFS_TO_FS_BUS_WD - 1:0] pfs_to_fs_bus;
wire                         pfs_to_fs_valid;
wire                         fs_allow_in;
wire                         fs_inst_unable;
wire                         blk_ms_load;

wire [              18:0]    s0_vppn;
wire                         s0_va_bit12;
wire [               9:0]    s0_asid;
wire                         s0_found;
wire [$clog2(TLBNUM)-1:0]    s0_index;
wire [              19:0]    s0_ppn;
wire [               5:0]    s0_ps;
wire [               1:0]    s0_plv;
wire [               1:0]    s0_mat;
wire                         s0_d;
wire                         s0_v;

wire  [              18:0]   s1_vppn;
wire                         s1_va_bit12;
wire  [               9:0]   s1_asid;
wire                         s1_found;
wire [$clog2(TLBNUM)-1:0]    s1_index;
wire [              19:0]    s1_ppn;
wire [               5:0]    s1_ps;
wire [               1:0]    s1_plv;
wire [               1:0]    s1_mat;
wire                         s1_d;
wire                         s1_v;

wire                         invtlb_valid;
wire  [               4:0]   invtlb_op;

wire                         we;
wire  [$clog2(TLBNUM)-1:0]   w_index;
wire                         w_e;
wire  [               5:0]   w_ps;
wire  [              18:0]   w_vppn;
wire  [               9:0]   w_asid;
wire                         w_g;
wire  [              19:0]   w_ppn0;
wire  [               1:0]   w_plv0;
wire  [               1:0]   w_mat0;
wire                         w_d0;
wire                         w_v0;
wire  [              19:0]   w_ppn1;
wire  [               1:0]   w_plv1;
wire  [               1:0]   w_mat1;
wire                         w_d1;
wire                         w_v1;

wire  [$clog2(TLBNUM)-1:0]   r_index;
wire                         r_e;
wire [              18:0]    r_vppn;
wire [               5:0]    r_ps;
wire [               9:0]    r_asid;
wire                         r_g;
wire [              19:0]    r_ppn0;
wire [               1:0]    r_plv0;
wire [               1:0]    r_mat0;
wire                         r_d0;
wire                         r_v0;
wire [              19:0]    r_ppn1;     
wire [               1:0]    r_plv1;
wire [               1:0]    r_mat1;
wire                         r_d1;
wire                         r_v1;
wire [`ES_TO_FS_BUS_WD - 1 :0] es_to_fs_bus;



if_stage if_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ds_allowin     (ds_allowin     ),

    .br_bus         (br_bus         ),
    

    .fs_to_ds_valid (fs_to_ds_valid ),
    .fs_to_ds_bus   (fs_to_ds_bus   ),
    .es_to_fs_bus   (es_to_fs_bus   ),

    .es_reflush_fs_bus(es_reflush_fs_bus),

    .inst_sram_req  (inst_sram_req  ),
    .inst_sram_wr   (inst_sram_wr   ),
    .inst_sram_size (inst_sram_size ),
    .inst_sram_wstrb(inst_sram_wstrb),
    .inst_sram_addr (inst_sram_addr ),
    .inst_sram_wdata(inst_sram_wdata),
    .inst_sram_addr_ok(inst_sram_addr_ok),
    .inst_sram_data_ok(inst_sram_data_ok),
    .inst_sram_rdata(inst_sram_rdata),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           )
);

id_stage id_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .es_allowin     (es_allowin     ),
    .ds_allowin     (ds_allowin     ),

    .fs_to_ds_valid (fs_to_ds_valid ),
    .fs_to_ds_bus   (fs_to_ds_bus   ),

    .ds_to_es_valid (ds_to_es_valid ),
    .ds_to_es_bus   (ds_to_es_bus   ),

    .br_bus         (br_bus         ),

    .ws_to_rf_bus   (ws_to_rf_bus   ),

    .raw_es_bus     (raw_es_bus     ),
    .raw_ms_bus     (raw_ms_bus     ),
    .raw_ws_bus     (raw_ws_bus     ),

    .es_reflush_ds  (es_reflush_ds  ),

    .has_int        (has_int        ),

    .blk_es_load    (blk_es_load    ),
    .blk_ms_load    (blk_ms_load    )
);

exe_stage exe_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ms_allowin     (ms_allowin     ),
    .es_allowin     (es_allowin     ),

    .ds_to_es_valid (ds_to_es_valid ),
    .ds_to_es_bus   (ds_to_es_bus   ),

    .ms_to_es_valid (ms_to_es_valid ),

    .ws_to_es_valid (ws_to_es_valid ),

    .es_to_ms_valid (es_to_ms_valid ),
    .es_to_ms_bus   (es_to_ms_bus   ),

    .data_sram_req  (data_sram_req  ),
    .data_sram_wr   (data_sram_wr   ),
    .data_sram_size (data_sram_size ),
    .data_sram_wstrb(data_sram_wstrb),
    .data_sram_addr (data_sram_addr ),
    .data_sram_wdata(data_sram_wdata),
    .data_sram_addr_ok(data_sram_addr_ok),

    .raw_es_bus     (raw_es_bus     ),

    .es_reflush_fs_bus(es_reflush_fs_bus),
    .es_reflush_ds  (es_reflush_ds  ),

    .has_int        (has_int        ),

    .blk_es_load    (blk_es_load    ),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           ),

    .s1_vppn       (s1_vppn        ),
    .s1_va_bit12   (s1_va_bit12    ),
    .s1_asid       (s1_asid        ),
    .s1_found      (s1_found       ),
    .s1_index      (s1_index       ),
    .s1_ppn        (s1_ppn         ),
    .s1_ps         (s1_ps          ),
    .s1_plv        (s1_plv         ),
    .s1_mat        (s1_mat         ),
    .s1_d          (s1_d           ),
    .s1_v          (s1_v           ),

    .invtlb_valid  (invtlb_valid   ),
    .invtlb_op     (invtlb_op      ),

    .we            (we             ),
    .w_index       (w_index        ),
    .w_e           (w_e            ),
    .w_ps          (w_ps           ),
    .w_vppn        (w_vppn         ),
    .w_asid        (w_asid         ),
    .w_g           (w_g            ),
    .w_ppn0        (w_ppn0         ),
    .w_plv0        (w_plv0         ),
    .w_mat0        (w_mat0         ),
    .w_d0          (w_d0           ),
    .w_v0          (w_v0           ),
    .w_ppn1        (w_ppn1         ),
    .w_plv1        (w_plv1         ),
    .w_mat1        (w_mat1         ),
    .w_d1          (w_d1           ),
    .w_v1          (w_v1           ),

    .r_index       (r_index        ),
    .r_e           (r_e            ),
    .r_vppn        (r_vppn         ),
    .r_ps          (r_ps           ),
    .r_asid        (r_asid         ),
    .r_g           (r_g            ),
    .r_ppn0        (r_ppn0         ),
    .r_plv0        (r_plv0         ),
    .r_mat0        (r_mat0         ),
    .r_d0          (r_d0           ),
    .r_v0          (r_v0           ),
    .r_ppn1        (r_ppn1         ),     
    .r_plv1        (r_plv1         ),
    .r_mat1        (r_mat1         ),
    .r_d1          (r_d1           ),
    .r_v1          (r_v1           ),
    .es_to_fs_bus  (es_to_fs_bus   )
);

mem_stage mem_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ws_allowin     (ws_allowin     ),
    .ms_allowin     (ms_allowin     ),

    .es_to_ms_valid (es_to_ms_valid ),
    .es_to_ms_bus   (es_to_ms_bus   ),

    .ms_to_ws_valid (ms_to_ws_valid ),
    .ms_to_ws_bus   (ms_to_ws_bus   ),

    .ms_to_es_valid (ms_to_es_valid ),

    .data_sram_data_ok(data_sram_data_ok),
    .data_sram_rdata(data_sram_rdata),

    .raw_ms_bus     (raw_ms_bus     ),
    .blk_ms_load    (blk_ms_load    )
);

wb_stage wb_stage(
    .clk            (clk            ),
    .reset          (reset          ),

    .ws_allowin     (ws_allowin     ),

    .ms_to_ws_valid (ms_to_ws_valid ),
    .ms_to_ws_bus   (ms_to_ws_bus   ),

    .ws_to_rf_bus   (ws_to_rf_bus   ),

    .ws_to_es_valid (ws_to_es_valid ),

    .raw_ws_bus     (raw_ws_bus     ),

    .debug_wb_pc      (debug_wb_pc      ),
    .debug_wb_rf_wen  (debug_wb_rf_wen  ),
    .debug_wb_rf_wnum (debug_wb_rf_wnum ),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);


tlb tlb(
    .clk           (clk            ),

    .s0_vppn       (s0_vppn        ),
    .s0_va_bit12   (s0_va_bit12    ),
    .s0_asid       (s0_asid        ),
    .s0_found      (s0_fount       ),
    .s0_index      (s0_index       ),
    .s0_ppn        (s0_ppn         ),  
    .s0_ps         (s0_ps          ),
    .s0_plv        (s0_plv         ),
    .s0_mat        (s0_mat         ),
    .s0_d          (s0_d           ),
    .s0_v          (s0_v           ),

    .s1_vppn       (s1_vppn        ),
    .s1_va_bit12   (s1_va_bit12    ),
    .s1_asid       (s1_asid        ),
    .s1_found      (s1_found       ),
    .s1_index      (s1_index       ),
    .s1_ppn        (s1_ppn         ),
    .s1_ps         (s1_ps          ),
    .s1_plv        (s1_plv         ),
    .s1_mat        (s1_mat         ),
    .s1_d          (s1_d           ),
    .s1_v          (s1_v           ),

    .invtlb_valid  (invtlb_valid   ),
    .invtlb_op     (invtlb_op      ),

    .we            (we             ),
    .w_index       (w_index        ),
    .w_e           (w_e            ),
    .w_ps          (w_ps           ),
    .w_vppn        (w_vppn         ),
    .w_asid        (w_asid         ),
    .w_g           (w_g            ),
    .w_ppn0        (w_ppn0         ),
    .w_plv0        (w_plv0         ),
    .w_mat0        (w_mat0         ),
    .w_d0          (w_d0           ),
    .w_v0          (w_v0           ),
    .w_ppn1        (w_ppn1         ),
    .w_plv1        (w_plv1         ),
    .w_mat1        (w_mat1         ),
    .w_d1          (w_d1           ),
    .w_v1          (w_v1           ),

    .r_index       (r_index        ),
    .r_e           (r_e            ),
    .r_vppn        (r_vppn         ),
    .r_ps          (r_ps           ),
    .r_asid        (r_asid         ),
    .r_g           (r_g            ),
    .r_ppn0        (r_ppn0         ),
    .r_plv0        (r_plv0         ),
    .r_mat0        (r_mat0         ),
    .r_d0          (r_d0           ),
    .r_v0          (r_v0           ),
    .r_ppn1        (r_ppn1         ),     
    .r_plv1        (r_plv1         ),
    .r_mat1        (r_mat1         ),
    .r_d1          (r_d1           ),
    .r_v1          (r_v1           )
);
endmodule