data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare/less_than_sign_Nb.v
1: b"%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare/less_than_sign_Nb.v:41: Cannot find file containing module: 'less_than_unsign_Nb'\nless_than_unsign_Nb #(.N(31)) less_than_unsign_31b_inst ( a[N-2:0], b[N-2:0], res_abs);\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare,data/full_repos/permissive/522553437/less_than_unsign_Nb\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare,data/full_repos/permissive/522553437/less_than_unsign_Nb.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare,data/full_repos/permissive/522553437/less_than_unsign_Nb.sv\n             less_than_unsign_Nb\n             less_than_unsign_Nb.v\n             less_than_unsign_Nb.sv\n             obj_dir/less_than_unsign_Nb\n             obj_dir/less_than_unsign_Nb.v\n             obj_dir/less_than_unsign_Nb.sv\n%Error: Exiting due to 1 error(s)\n"
module less_than_sign_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output reg [N-1:0] r
);

wire [N-2:0]  res_abs;


less_than_unsign_Nb #(.N(31)) less_than_unsign_31b_inst ( a[N-2:0], b[N-2:0], res_abs);

always@ (*)
begin
	case ({a[N-1], b[N-1]})
		2'b00 	: r = {1'b0, res_abs};
		2'b10 	: r = 32'b1;
		2'b01	: r = 32'b0;
		default : r = {1'b0, res_abs};
	endcase
end

endmodule
module less_than_sign_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output reg [N-1:0] r
);


wire [N-2:0]  res_abs;


less_than_unsign_Nb #(.N(31)) less_than_unsign_31b_inst ( a[N-2:0], b[N-2:0], res_abs);

always@ (*)
begin
	case ({a[N-1], b[N-1]})
		2'b00 	: r = {1'b0, res_abs};
		2'b10 	: r = 32'b1;
		2'b01	: r = 32'b0;
		default : r = {1'b0, res_abs};
	endcase
end

endmodule