data/full_repos/permissive/46804359/0_cpu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46804359/0_cpu_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46804359/0_cpu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/46804359/0_cpu_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: data/full_repos/permissive/46804359/0_cpu_tb.v:19: Cannot find file containing module: \'processor\'\nprocessor DUT(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor.v\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor.sv\n             processor\n             processor.v\n             processor.sv\n             obj_dir/processor\n             obj_dir/processor.v\n             obj_dir/processor.sv\n%Error: data/full_repos/permissive/46804359/0_cpu_tb.v:33: Cannot find file containing module: \'Memory\'\nMemory mem(\n^~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module processor_tb;

reg clk;
reg pc_reset;
reg pc_enable;




wire [31:0] instr;
wire [31:0] data_out;
wire [31:0] data_in;
wire [31:0] inst_addr;
wire [31:0] data_addr;
wire mem_read_ctrlsig;
wire mem_write_ctrlsig;

processor DUT(
	.clk,
	.pc_reset,
	.pc_enable,
	.instr,
	.data_out,
	.data_in,
	.inst_addr,
	.data_addr,
	.mem_read_ctrlsig,
	.mem_write_ctrlsig
	);


Memory mem(
	.inst_addr,
	.instr,
	.data_addr,
	.data_in,
	.mem_read (mem_read_ctrlsig),
	.mem_write (mem_write_ctrlsig),
	.data_out
	);


initial begin
    clk=0;
    pc_reset=0;
    pc_enable=1;

end


always #5 clk=~clk;




initial begin
#50
pc_reset=1;
#50
pc_reset=0;



end

endmodule
module processor_tb;


reg clk;
reg pc_reset;
reg pc_enable;




wire [31:0] instr;
wire [31:0] data_out;
wire [31:0] data_in;
wire [31:0] inst_addr;
wire [31:0] data_addr;
wire mem_read_ctrlsig;
wire mem_write_ctrlsig;

processor DUT(
	.clk,
	.pc_reset,
	.pc_enable,
	.instr,
	.data_out,
	.data_in,
	.inst_addr,
	.data_addr,
	.mem_read_ctrlsig,
	.mem_write_ctrlsig
	);


Memory mem(
	.inst_addr,
	.instr,
	.data_addr,
	.data_in,
	.mem_read (mem_read_ctrlsig),
	.mem_write (mem_write_ctrlsig),
	.data_out
	);


initial begin
    clk=0;
    pc_reset=0;
    pc_enable=1;

end


always #5 clk=~clk;




initial begin
#50
pc_reset=1;
#50
pc_reset=0;



end

endmodule