data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFourBitRippleCarryAdder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFourBitRippleCarryAdder.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #160 a <= a + 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFourBitRippleCarryAdder.v:12: Unsupported: Ignoring delay on this delayed statement.\n     #10 b <= b + 1;\n     ^\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFourBitRippleCarryAdder.v:4: Cannot find file containing module: \'FourBitRippleCarryAdder\'\n   FourBitRippleCarryAdder fbrca(a,b,1\'b0,S);\n   ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder.v\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FourBitRippleCarryAdder.sv\n             FourBitRippleCarryAdder\n             FourBitRippleCarryAdder.v\n             FourBitRippleCarryAdder.sv\n             obj_dir/FourBitRippleCarryAdder\n             obj_dir/FourBitRippleCarryAdder.v\n             obj_dir/FourBitRippleCarryAdder.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchFourBitRippleCarryAdder;
   reg [3:0] a,b;
   wire [4:0] S;
   FourBitRippleCarryAdder fbrca(a,b,1'b0,S);
   initial begin
     a = 4'b0000;
     b = 4'b0000;
   end
   always
     #160 a <= a + 1;
   always
     #10 b <= b + 1;
endmodule
module TestBenchFourBitRippleCarryAdder;

   reg [3:0] a,b;
   wire [4:0] S;
   FourBitRippleCarryAdder fbrca(a,b,1'b0,S);
   initial begin
     a = 4'b0000;
     b = 4'b0000;
   end
   always
     #160 a <= a + 1;
   always
     #10 b <= b + 1;
endmodule