data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx/clkgen_xil7series.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx/clkgen_xil7series.sv:19: Cannot find file containing module: 'IBUF'\n  IBUF io_clk_ibuf(\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx,data/full_repos/permissive/509468557/IBUF\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx,data/full_repos/permissive/509468557/IBUF.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx,data/full_repos/permissive/509468557/IBUF.sv\n             IBUF\n             IBUF.v\n             IBUF.sv\n             obj_dir/IBUF\n             obj_dir/IBUF.v\n             obj_dir/IBUF.sv\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx/clkgen_xil7series.sv:24: Cannot find file containing module: 'PLLE2_ADV'\n  PLLE2_ADV #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx/clkgen_xil7series.sv:64: Cannot find file containing module: 'BUFG'\n  BUFG clk_fb_bufg (\n  ^~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/shared/rtl/fpga/xilinx/clkgen_xil7series.sv:69: Cannot find file containing module: 'BUFG'\n  BUFG clk_50_bufg (\n  ^~~~\n%Error: Exiting due to 4 error(s)\n"
module clkgen_xil7series (
    input IO_CLK,
    input IO_RST_N,
    output clk_sys,
    output rst_sys_n
);
  logic locked_pll;
  logic io_clk_buf;
  logic clk_50_buf;
  logic clk_50_unbuf;
  logic clk_fb_buf;
  logic clk_fb_unbuf;


  IBUF io_clk_ibuf(
    .I (IO_CLK),
    .O (io_clk_buf)
  );

  PLLE2_ADV #(
    .BANDWIDTH            ("OPTIMIZED"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT        (12),
    .CLKFBOUT_PHASE       (0.000),
    .CLKOUT0_DIVIDE       (24),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKIN1_PERIOD        (10)
  ) pll (
    .CLKFBOUT            (clk_fb_unbuf),
    .CLKOUT0             (clk_50_unbuf),
    .CLKOUT1             (),
    .CLKOUT2             (),
    .CLKOUT3             (),
    .CLKOUT4             (),
    .CLKOUT5             (),

    .CLKFBIN             (clk_fb_buf),
    .CLKIN1              (io_clk_buf),
    .CLKIN2              (1'b0),

    .CLKINSEL            (1'b1),

    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (),
    .DRDY                (),
    .DWE                 (1'b0),

    .LOCKED              (locked_pll),
    .PWRDWN              (1'b0),

    .RST                 (1'b0));


  BUFG clk_fb_bufg (
    .I (clk_fb_unbuf),
    .O (clk_fb_buf)
  );

  BUFG clk_50_bufg (
    .I (clk_50_unbuf),
    .O (clk_50_buf)
  );



  assign clk_sys = clk_50_buf;


  assign rst_sys_n = locked_pll & IO_RST_N;
endmodule
module clkgen_xil7series (
    input IO_CLK,
    input IO_RST_N,
    output clk_sys,
    output rst_sys_n
);

  logic locked_pll;
  logic io_clk_buf;
  logic clk_50_buf;
  logic clk_50_unbuf;
  logic clk_fb_buf;
  logic clk_fb_unbuf;


  IBUF io_clk_ibuf(
    .I (IO_CLK),
    .O (io_clk_buf)
  );

  PLLE2_ADV #(
    .BANDWIDTH            ("OPTIMIZED"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT        (12),
    .CLKFBOUT_PHASE       (0.000),
    .CLKOUT0_DIVIDE       (24),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKIN1_PERIOD        (10)
  ) pll (
    .CLKFBOUT            (clk_fb_unbuf),
    .CLKOUT0             (clk_50_unbuf),
    .CLKOUT1             (),
    .CLKOUT2             (),
    .CLKOUT3             (),
    .CLKOUT4             (),
    .CLKOUT5             (),

    .CLKFBIN             (clk_fb_buf),
    .CLKIN1              (io_clk_buf),
    .CLKIN2              (1'b0),

    .CLKINSEL            (1'b1),

    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (),
    .DRDY                (),
    .DWE                 (1'b0),

    .LOCKED              (locked_pll),
    .PWRDWN              (1'b0),

    .RST                 (1'b0));


  BUFG clk_fb_bufg (
    .I (clk_fb_unbuf),
    .O (clk_fb_buf)
  );

  BUFG clk_50_bufg (
    .I (clk_50_unbuf),
    .O (clk_50_buf)
  );



  assign clk_sys = clk_50_buf;


  assign rst_sys_n = locked_pll & IO_RST_N;
endmodule