data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv
1: b'%Error: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:19: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("risc_v.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:22: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, RISC_V_tb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:25: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.IMemory.iram[i]);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:29: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.DMemory.dram[i]);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:33: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.ALU.Data_Registers[i]);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:41: Unsupported: Ignoring delay on this delayed statement.\n    #2 la_data_in[50] = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:45: Unsupported: Ignoring delay on this delayed statement.\n    #1 la_data_in[51] = ~la_data_in[51];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:49: Unsupported: Ignoring delay on this delayed statement.\n  #500\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:55: Unsupported: Ignoring delay on this delayed statement.\n      #2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:62: Unsupported: Ignoring delay on this delayed statement.\n  #550\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522668124/verilog/dv/risc_v/risc_v_tb.sv:70: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISC_V_tb;

  reg  [127:0] la_data_in = 0;
  wire  [127:0] la_data_out;
  reg  [127:0] la_oenb = 0;

 user_project_wrapper user_project_wrapper (
  .la_data_in(la_data_in),
  .la_data_out(la_data_out),
  .la_oenb(la_oenb)
  );
  
  integer i;
  integer f;

  initial 
  
  begin
    $dumpfile("risc_v.vcd");
    f = $fopen("output.txt","w");

    $dumpvars(0, RISC_V_tb);

    for(i = 0; i < 16; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.IMemory.iram[i]);


    for(i = 0; i < 16; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.DMemory.dram[i]);


    for(i = 0; i < 32; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.ALU.Data_Registers[i]);
	
    

    la_data_in[51] = 0;
    la_data_in[50] = 0;
    la_data_in[36] = 0;
    la_data_in[45] = 1;
    #2 la_data_in[50] = 1;
  end

  always
    #1 la_data_in[51] = ~la_data_in[51];
    
  initial begin
  
  #500
  la_data_in[50] = 0;
  la_data_in[51] = 1;
  for (i = 0; i < 15; i = i + 1) begin
      la_data_in[35:32] = i;
      la_data_in[31:0] = 32'b 000000000001_00001_000_00001_0010011;
      #2;
  end
 
  end  
  
  initial begin
  
  #550
  la_data_in[50] = 1;
  la_data_in[51] = 0;

  end

  initial begin

    #1000 $finish;
  end
endmodule
module RISC_V_tb;


  reg  [127:0] la_data_in = 0;
  wire  [127:0] la_data_out;
  reg  [127:0] la_oenb = 0;

 user_project_wrapper user_project_wrapper (
  .la_data_in(la_data_in),
  .la_data_out(la_data_out),
  .la_oenb(la_oenb)
  );
  
  integer i;
  integer f;

  initial 
  
  begin
    $dumpfile("risc_v.vcd");
    f = $fopen("output.txt","w");

    $dumpvars(0, RISC_V_tb);

    for(i = 0; i < 16; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.IMemory.iram[i]);


    for(i = 0; i < 16; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.DMemory.dram[i]);


    for(i = 0; i < 32; i = i + 1)
      $dumpvars(0, RISC_V_tb.user_project_wrapper.RISC_V.ALU.Data_Registers[i]);
	
    

    la_data_in[51] = 0;
    la_data_in[50] = 0;
    la_data_in[36] = 0;
    la_data_in[45] = 1;
    #2 la_data_in[50] = 1;
  end

  always
    #1 la_data_in[51] = ~la_data_in[51];
    
  initial begin
  
  #500
  la_data_in[50] = 0;
  la_data_in[51] = 1;
  for (i = 0; i < 15; i = i + 1) begin
      la_data_in[35:32] = i;
      la_data_in[31:0] = 32'b 000000000001_00001_000_00001_0010011;
      #2;
  end
 
  end  
  
  initial begin
  
  #550
  la_data_in[50] = 1;
  la_data_in[51] = 0;

  end

  initial begin

    #1000 $finish;
  end
endmodule