data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleDspModule/reference/SimpleDspModule.v
data/verilator_xmls/ba81de7e-1e64-4b1a-8e3c-76f2700dc68d.xml
module ASSINT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule
module ASSINT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule