data/full_repos/permissive/500128826/HDLBits/Circuits/Building Larger Circuits/review2015_shiftcount/top_module.v
1: b'%Error: Cannot find file containing module: Larger\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.sv\n             Larger\n             Larger.v\n             Larger.sv\n             obj_dir/Larger\n             obj_dir/Larger.v\n             obj_dir/Larger.sv\n%Error: Cannot find file containing module: Circuits/review2015_shiftcount,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Building\n%Error: Cannot find file containing module: Circuits/review2015_shiftcount/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire clk,
    input wire shift_ena,
    input wire count_ena,
    input wire data,
    output wire [3:0] q
);

  reg [3:0] qr = 4'b0;
  assign q = qr;

  always @(posedge clk) begin
    if (shift_ena) begin
      qr <= {qr[2:0], data};
    end

    if (count_ena) begin
      qr <= qr - 1'b1;
    end
  end

endmodule
module top_module (
    input wire clk,
    input wire shift_ena,
    input wire count_ena,
    input wire data,
    output wire [3:0] q
);


  reg [3:0] qr = 4'b0;
  assign q = qr;

  always @(posedge clk) begin
    if (shift_ena) begin
      qr <= {qr[2:0], data};
    end

    if (count_ena) begin
      qr <= qr - 1'b1;
    end
  end

endmodule