data/full_repos/permissive/427578563/blinky/blinky.v
data/verilator_xmls/ffac413d-35d7-492e-ac86-48fccd8aae64.xml
module blinky (
            input wire clk,
            input wire reset,
            output wire led_blue,
            output wire led_green,
            output wire led_red);

    parameter N = 27;
    reg [N:0] counter;


    assign led_blue = counter[N];
    assign led_green = counter[N-1];
    assign led_red = counter[N-2];


    always @(posedge clk) begin
        if (reset)
            counter <= 0;
        else
            counter <= counter + 1;
    end
endmodule
module blinky (
            input wire clk,
            input wire reset,
            output wire led_blue,
            output wire led_green,
            output wire led_red);


    parameter N = 27;
    reg [N:0] counter;


    assign led_blue = counter[N];
    assign led_green = counter[N-1];
    assign led_red = counter[N-2];


    always @(posedge clk) begin
        if (reset)
            counter <= 0;
        else
            counter <= counter + 1;
    end
endmodule