data/full_repos/permissive/439087417/mux_sel1.v
data/verilator_xmls/e56c1b15-cd9a-4bb2-8611-abd0b058ff40.xml
module mux_sel1 #(parameter dw='h10)
(  input [dw-1:0] IN_0, IN_1,
	input sel,
	output [dw-1:0] OUT
    );

assign OUT = sel ? IN_1 : IN_0;

endmodule
module mux_sel1 #(parameter dw='h10)
(  input [dw-1:0] IN_0, IN_1,
	input sel,
	output [dw-1:0] OUT
    );


assign OUT = sel ? IN_1 : IN_0;

endmodule