data/full_repos/permissive/527249789/src/id_ex.v
1: b'%Error: data/full_repos/permissive/527249789/src/id_ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:9: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]                  pc_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstAddrBus]                  pc_i,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:10: Define or directive not defined: \'`InstBus\'\n    input   [`InstBus]                      inst_i,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:11: Define or directive not defined: \'`AluSelBus\'\n    input   [`AluSelBus]                    alusel_i,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:12: Define or directive not defined: \'`AluOpBus\'\n    input   [`AluOpBus]                     aluop_i,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:14: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:15: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       rdata1_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:16: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       rdata2_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:17: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       link_addr_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:18: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       exception_type_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:22: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]               pc_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:23: Define or directive not defined: \'`InstBus\'\n    output  reg[`InstBus]                   inst_o,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:24: Define or directive not defined: \'`AluSelBus\'\n    output  reg[`AluSelBus]                 alusel_o,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:25: Define or directive not defined: \'`AluOpBus\'\n    output  reg[`AluOpBus]                  aluop_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]                waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:27: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]                waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:28: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    rdata1_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:29: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    rdata2_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:30: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    link_addr_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:31: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    exception_type_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg                             next_inst_in_delayslot_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:35: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                                   branch_flag_i,\n    ^~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:36: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]                  branch_addr_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:38: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]               branch_addr_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:45: syntax error, unexpected assign\nassign branch_flag_o = watch_branch_flag && do_inst_flag;\n^~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:48: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:49: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:50: Define or directive not defined: \'`ZeroWord\'\n        inst_o <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:51: Define or directive not defined: \'`EXE_RES_NOP\'\n        alusel_o <= `EXE_RES_NOP;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:52: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:53: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:54: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:55: Define or directive not defined: \'`ZeroWord\'\n        rdata1_o <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:56: Define or directive not defined: \'`ZeroWord\'\n        rdata2_o <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:57: Define or directive not defined: \'`ZeroWord\'\n        link_addr_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:58: Define or directive not defined: \'`ZeroWord\'\n        exception_type_o <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:59: Define or directive not defined: \'`NotInDelaySlot\'\n        is_in_delayslot_o <= `NotInDelaySlot;\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:60: Define or directive not defined: \'`FlushEnable\'\n    end else if (flush == `FlushEnable) begin\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:61: Define or directive not defined: \'`ZeroWord\'\n        pc_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:62: Define or directive not defined: \'`ZeroWord\'\n        inst_o <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:63: Define or directive not defined: \'`EXE_RES_NOP\'\n        alusel_o <= `EXE_RES_NOP;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:64: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:65: Define or directive not defined: \'`WriteDisable\'\n        wen_o <= `WriteDisable;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:66: Define or directive not defined: \'`ZeroRegAddr\'\n        waddr_o <= `ZeroRegAddr;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:67: Define or directive not defined: \'`ZeroWord\'\n        rdata1_o <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:68: Define or directive not defined: \'`ZeroWord\'\n        rdata2_o <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:69: Define or directive not defined: \'`ZeroWord\'\n        link_addr_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:70: Define or directive not defined: \'`ZeroWord\'\n        exception_type_o <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/id_ex.v:71: Define or directive not defined: \'`NotInDelaySlot\'\n        is_in_delayslot_o <= `NotInDelaySlot;\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id_ex(
    input                                   clk,
    input                                   resetn,

    input                                   do_inst_flag,

    input   [`InstAddrBus]                  pc_i,
    input   [`InstBus]                      inst_i,
    input   [`AluSelBus]                    alusel_i,
    input   [`AluOpBus]                     aluop_i,
    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       rdata1_i,
    input   [`RegBus]                       rdata2_i,
    input   [`RegBus]                       link_addr_i,
    input   [`RegBus]                       exception_type_i,
    input                                   is_in_delayslot_i,
    input                                   next_inst_in_delayslot_i,

    output  reg[`InstAddrBus]               pc_o,
    output  reg[`InstBus]                   inst_o,
    output  reg[`AluSelBus]                 alusel_o,
    output  reg[`AluOpBus]                  aluop_o,
    output  reg                             wen_o,
    output  reg[`RegAddrBus]                waddr_o,
    output  reg[`RegBus]                    rdata1_o,
    output  reg[`RegBus]                    rdata2_o,
    output  reg[`RegBus]                    link_addr_o,
    output  reg[`RegBus]                    exception_type_o,
    output  reg                             is_in_delayslot_o,
    output  reg                             next_inst_in_delayslot_o,

    input                                   branch_flag_i,
    input   [`InstAddrBus]                  branch_addr_i,
    output                                  branch_flag_o,
    output  reg[`InstAddrBus]               branch_addr_o,

    input                                   flush,
    input   [3:0]                           stall_i
);

reg watch_branch_flag;
assign branch_flag_o = watch_branch_flag && do_inst_flag;

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if ((stall_i[1] == `Stop) && (stall_i[2] == `NoStop)) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (stall_i[1] == `NoStop) begin
        pc_o <= pc_i;
        inst_o <= inst_i;
        alusel_o <= alusel_i;
        aluop_o <= aluop_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        rdata1_o <= rdata1_i;
        rdata2_o <= rdata2_i;
        link_addr_o <= link_addr_i;
        exception_type_o <= exception_type_i;
        is_in_delayslot_o <= is_in_delayslot_i;
    end
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               next_inst_in_delayslot_o <= `NotInDelaySlot;
    else if (flush == `FlushEnable)                         next_inst_in_delayslot_o <= `NotInDelaySlot;
    else if (next_inst_in_delayslot_i == `InDelaySlot)      next_inst_in_delayslot_o <= `InDelaySlot;
    else if (do_inst_flag == `True_v)                       next_inst_in_delayslot_o <= `NotInDelaySlot;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               watch_branch_flag <= `False_v;
    else if (flush == `FlushEnable)                         watch_branch_flag <= `False_v;
    else if (branch_flag_i && (stall_i[1] == `NoStop))      watch_branch_flag <= `True_v;
    else if (do_inst_flag == `True_v)                       watch_branch_flag <= `False_v;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               branch_addr_o <= `ZeroWord;
    else if (flush == `FlushEnable)                         branch_addr_o <= `ZeroWord;
    else if (branch_flag_i)                                 branch_addr_o <= branch_addr_i;
    else if (do_inst_flag == `True_v)                       branch_addr_o <= `ZeroWord;
end

endmodule
module id_ex(
    input                                   clk,
    input                                   resetn,

    input                                   do_inst_flag,

    input   [`InstAddrBus]                  pc_i,
    input   [`InstBus]                      inst_i,
    input   [`AluSelBus]                    alusel_i,
    input   [`AluOpBus]                     aluop_i,
    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       rdata1_i,
    input   [`RegBus]                       rdata2_i,
    input   [`RegBus]                       link_addr_i,
    input   [`RegBus]                       exception_type_i,
    input                                   is_in_delayslot_i,
    input                                   next_inst_in_delayslot_i,

    output  reg[`InstAddrBus]               pc_o,
    output  reg[`InstBus]                   inst_o,
    output  reg[`AluSelBus]                 alusel_o,
    output  reg[`AluOpBus]                  aluop_o,
    output  reg                             wen_o,
    output  reg[`RegAddrBus]                waddr_o,
    output  reg[`RegBus]                    rdata1_o,
    output  reg[`RegBus]                    rdata2_o,
    output  reg[`RegBus]                    link_addr_o,
    output  reg[`RegBus]                    exception_type_o,
    output  reg                             is_in_delayslot_o,
    output  reg                             next_inst_in_delayslot_o,

    input                                   branch_flag_i,
    input   [`InstAddrBus]                  branch_addr_i,
    output                                  branch_flag_o,
    output  reg[`InstAddrBus]               branch_addr_o,

    input                                   flush,
    input   [3:0]                           stall_i
);


reg watch_branch_flag;
assign branch_flag_o = watch_branch_flag && do_inst_flag;

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (flush == `FlushEnable) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if ((stall_i[1] == `Stop) && (stall_i[2] == `NoStop)) begin
        pc_o <= `ZeroWord;
        inst_o <= `ZeroWord;
        alusel_o <= `EXE_RES_NOP;
        aluop_o <= `EXE_NOP_OP;
        wen_o <= `WriteDisable;
        waddr_o <= `ZeroRegAddr;
        rdata1_o <= `ZeroWord;
        rdata2_o <= `ZeroWord;
        link_addr_o <= `ZeroWord;
        exception_type_o <= `ZeroWord;
        is_in_delayslot_o <= `NotInDelaySlot;
    end else if (stall_i[1] == `NoStop) begin
        pc_o <= pc_i;
        inst_o <= inst_i;
        alusel_o <= alusel_i;
        aluop_o <= aluop_i;
        wen_o <= wen_i;
        waddr_o <= waddr_i;
        rdata1_o <= rdata1_i;
        rdata2_o <= rdata2_i;
        link_addr_o <= link_addr_i;
        exception_type_o <= exception_type_i;
        is_in_delayslot_o <= is_in_delayslot_i;
    end
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               next_inst_in_delayslot_o <= `NotInDelaySlot;
    else if (flush == `FlushEnable)                         next_inst_in_delayslot_o <= `NotInDelaySlot;
    else if (next_inst_in_delayslot_i == `InDelaySlot)      next_inst_in_delayslot_o <= `InDelaySlot;
    else if (do_inst_flag == `True_v)                       next_inst_in_delayslot_o <= `NotInDelaySlot;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               watch_branch_flag <= `False_v;
    else if (flush == `FlushEnable)                         watch_branch_flag <= `False_v;
    else if (branch_flag_i && (stall_i[1] == `NoStop))      watch_branch_flag <= `True_v;
    else if (do_inst_flag == `True_v)                       watch_branch_flag <= `False_v;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                               branch_addr_o <= `ZeroWord;
    else if (flush == `FlushEnable)                         branch_addr_o <= `ZeroWord;
    else if (branch_flag_i)                                 branch_addr_o <= branch_addr_i;
    else if (do_inst_flag == `True_v)                       branch_addr_o <= `ZeroWord;
end

endmodule