data/full_repos/permissive/502544928/core_interface.v
data/verilator_xmls/ccbc9307-ccfa-4399-843b-529da652115e.xml
module core_interface  #(parameter FLIT_WIDTH = 32, IN_PORTS  = 1, 
						 OUT_PORTS  = 1, VC_PER_IN_PORTS = 2)(
  input  clk, reset, WEn, REn, 
  input  [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit,
  input  [IN_PORTS-1: 0] v_from_core,
  
  output [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit,
  output [OUT_PORTS-1: 0] v_to_core,
  output [(FLIT_WIDTH * OUT_PORTS) -1:0] to_router_flit,
  output [OUT_PORTS-1: 0] v_to_router,
  
  input  [(FLIT_WIDTH * IN_PORTS) -1:0] from_router_flit,
  input  [IN_PORTS-1: 0] v_from_router,
  
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_router_empty,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_router_full,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_core_empty,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_core_full, 
 
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_router_empty,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_router_full,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_core_empty,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_core_full	 
); 
  
  wire [FLIT_WIDTH -1:0] t_from_core_flit[0:IN_PORTS-1];
  wire t_v_from_core  [0:IN_PORTS-1];
  wire [FLIT_WIDTH -1:0] t_from_router_flit[0:IN_PORTS-1];
  wire t_v_from_router  [0:IN_PORTS-1];
 
  reg [FLIT_WIDTH -1:0] t_to_core_flit[0:OUT_PORTS-1];
  reg t_v_to_core[0:OUT_PORTS-1];
  reg [FLIT_WIDTH -1:0] t_to_router_flit[0:OUT_PORTS-1];
  reg t_v_to_router[0:OUT_PORTS-1];
    
  reg  [FLIT_WIDTH -1:0] c_buffers[0:IN_PORTS-1];
  reg  [FLIT_WIDTH -1:0] s_buffers[0:IN_PORTS-1];
  reg  c_valid[0:IN_PORTS-1];
  reg  s_valid[0:IN_PORTS-1];
    
  integer i; 
  
  genvar j;
  generate
      	for (j = 0; j < IN_PORTS; j = j+1) begin : CPORTS
      	 	assign t_from_core_flit[j]   = from_core_flit[((FLIT_WIDTH *(j + 1))-1) -: FLIT_WIDTH];
      	 	assign t_v_from_core[j]      = v_from_core[j];
      	 	assign t_from_router_flit[j] = from_router_flit[((FLIT_WIDTH *(j + 1))-1) -: FLIT_WIDTH]; 
      	 	assign t_v_from_router[j]    = v_from_router[j]; 
      	end  	
  endgenerate 
  

  always @ (posedge clk) begin
  if (reset) begin
    for (i = 0; i < OUT_PORTS; i = i+1) begin
       t_v_to_core[i]   <= 0;  
       t_v_to_router[i] <= 0;
    end
  end 
  else begin

      for (i = 0; i < IN_PORTS; i = i+1) begin
      	c_valid[i] <=  (REn & t_v_from_core[i])? 1: (WEn & c_valid[i])? 0: c_valid[i]; 
      	s_valid[i] <=  (REn & t_v_from_router[i])? 1: (WEn & s_valid[i])? 0: s_valid[i]; 
      end 
      
      if(REn)
      	for (i = 0; i < IN_PORTS; i = i+1) begin
      	   if(t_v_from_core[i]) begin
      	        c_buffers[i] <= t_from_core_flit[i];
      	   end
      	   if(t_v_from_router[i]) begin
      	       s_buffers[i]  <= t_from_router_flit[i];
      	   end  
      	end   
          
      if(WEn)
      	for (i = 0; i < OUT_PORTS; i = i+1) begin
           if(s_valid[i]) begin
           		t_v_to_core[i]    <= 1; 
           		t_to_core_flit[i] <= s_buffers[i];
           end   
           else t_v_to_core[i]    <= 0;
           
           if(c_valid[i]) begin
           		t_v_to_router[i]    <= 1; 
           		t_to_router_flit[i] <= c_buffers[i]; 
           end 
           else  t_v_to_router[i]   <= 0;     	     
      	end 
      else 
      	for (i = 0; i < OUT_PORTS; i = i+1) begin
          t_v_to_core[i]   <= 0;
          t_v_to_router[i] <= 0;     	     
      	end 
  end 
  end
  
  



  generate
      	for (j = 0; j < OUT_PORTS; j = j+1) begin : C_OUT
           	assign to_core_flit[(((j + 1) *(FLIT_WIDTH))-1) -: FLIT_WIDTH] = t_to_core_flit[j];
           	assign v_to_core[j] = t_v_to_core[j]; 
           	assign to_router_flit[(((j + 1) *(FLIT_WIDTH))-1) -: FLIT_WIDTH] = t_to_router_flit[j];
           	assign v_to_router[j] = t_v_to_router[j];
      	end  	
  endgenerate 
  
  assign to_core_empty = from_router_empty;
  assign to_core_full = from_router_full;
  assign to_router_empty = from_core_empty;
  assign to_router_full =  from_core_full;
           		
endmodule
module core_interface  #(parameter FLIT_WIDTH = 32, IN_PORTS  = 1, 
						 OUT_PORTS  = 1, VC_PER_IN_PORTS = 2)(
  input  clk, reset, WEn, REn, 
  input  [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit,
  input  [IN_PORTS-1: 0] v_from_core,
  
  output [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit,
  output [OUT_PORTS-1: 0] v_to_core,
  output [(FLIT_WIDTH * OUT_PORTS) -1:0] to_router_flit,
  output [OUT_PORTS-1: 0] v_to_router,
  
  input  [(FLIT_WIDTH * IN_PORTS) -1:0] from_router_flit,
  input  [IN_PORTS-1: 0] v_from_router,
  
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_router_empty,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_router_full,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_core_empty,
  input  [(VC_PER_IN_PORTS * IN_PORTS) -1:0] from_core_full, 
 
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_router_empty,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_router_full,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_core_empty,
  output [(VC_PER_IN_PORTS * IN_PORTS) -1:0] to_core_full	 
);
 
  
  wire [FLIT_WIDTH -1:0] t_from_core_flit[0:IN_PORTS-1];
  wire t_v_from_core  [0:IN_PORTS-1];
  wire [FLIT_WIDTH -1:0] t_from_router_flit[0:IN_PORTS-1];
  wire t_v_from_router  [0:IN_PORTS-1];
 
  reg [FLIT_WIDTH -1:0] t_to_core_flit[0:OUT_PORTS-1];
  reg t_v_to_core[0:OUT_PORTS-1];
  reg [FLIT_WIDTH -1:0] t_to_router_flit[0:OUT_PORTS-1];
  reg t_v_to_router[0:OUT_PORTS-1];
    
  reg  [FLIT_WIDTH -1:0] c_buffers[0:IN_PORTS-1];
  reg  [FLIT_WIDTH -1:0] s_buffers[0:IN_PORTS-1];
  reg  c_valid[0:IN_PORTS-1];
  reg  s_valid[0:IN_PORTS-1];
    
  integer i; 
  
  genvar j;
  generate
      	for (j = 0; j < IN_PORTS; j = j+1) begin : CPORTS
      	 	assign t_from_core_flit[j]   = from_core_flit[((FLIT_WIDTH *(j + 1))-1) -: FLIT_WIDTH];
      	 	assign t_v_from_core[j]      = v_from_core[j];
      	 	assign t_from_router_flit[j] = from_router_flit[((FLIT_WIDTH *(j + 1))-1) -: FLIT_WIDTH]; 
      	 	assign t_v_from_router[j]    = v_from_router[j]; 
      	end  	
  endgenerate 
  

  always @ (posedge clk) begin
  if (reset) begin
    for (i = 0; i < OUT_PORTS; i = i+1) begin
       t_v_to_core[i]   <= 0;  
       t_v_to_router[i] <= 0;
    end
  end 
  else begin

      for (i = 0; i < IN_PORTS; i = i+1) begin
      	c_valid[i] <=  (REn & t_v_from_core[i])? 1: (WEn & c_valid[i])? 0: c_valid[i]; 
      	s_valid[i] <=  (REn & t_v_from_router[i])? 1: (WEn & s_valid[i])? 0: s_valid[i]; 
      end 
      
      if(REn)
      	for (i = 0; i < IN_PORTS; i = i+1) begin
      	   if(t_v_from_core[i]) begin
      	        c_buffers[i] <= t_from_core_flit[i];
      	   end
      	   if(t_v_from_router[i]) begin
      	       s_buffers[i]  <= t_from_router_flit[i];
      	   end  
      	end   
          
      if(WEn)
      	for (i = 0; i < OUT_PORTS; i = i+1) begin
           if(s_valid[i]) begin
           		t_v_to_core[i]    <= 1; 
           		t_to_core_flit[i] <= s_buffers[i];
           end   
           else t_v_to_core[i]    <= 0;
           
           if(c_valid[i]) begin
           		t_v_to_router[i]    <= 1; 
           		t_to_router_flit[i] <= c_buffers[i]; 
           end 
           else  t_v_to_router[i]   <= 0;     	     
      	end 
      else 
      	for (i = 0; i < OUT_PORTS; i = i+1) begin
          t_v_to_core[i]   <= 0;
          t_v_to_router[i] <= 0;     	     
      	end 
  end 
  end
  
  



  generate
      	for (j = 0; j < OUT_PORTS; j = j+1) begin : C_OUT
           	assign to_core_flit[(((j + 1) *(FLIT_WIDTH))-1) -: FLIT_WIDTH] = t_to_core_flit[j];
           	assign v_to_core[j] = t_v_to_core[j]; 
           	assign to_router_flit[(((j + 1) *(FLIT_WIDTH))-1) -: FLIT_WIDTH] = t_to_router_flit[j];
           	assign v_to_router[j] = t_v_to_router[j];
      	end  	
  endgenerate 
  
  assign to_core_empty = from_router_empty;
  assign to_core_full = from_router_full;
  assign to_router_empty = from_core_empty;
  assign to_router_full =  from_core_full;
           		
endmodule