data/full_repos/permissive/40656238/altera/de0_nano_sdram/hardcaml_lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/40656238/altera/de0_nano_sdram/hardcaml_lib.v:10: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'hardcaml_lib_add\'\nmodule hardcaml_lib_add #(parameter b=1) \n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_sub\'\nmodule hardcaml_lib_sub #(parameter b=1) \n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_mulu\'\nmodule hardcaml_lib_mulu\n       ^~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_muls\'\nmodule hardcaml_lib_muls\n       ^~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_and\'\nmodule hardcaml_lib_and #(parameter b=1) \n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_or\'\nmodule hardcaml_lib_or #(parameter b=1) \n       ^~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_xor\'\nmodule hardcaml_lib_xor #(parameter b=1) \n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_not\'\nmodule hardcaml_lib_not #(parameter b=1) \n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_eq\'\nmodule hardcaml_lib_eq #(parameter b=1) \n       ^~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_lt\'\nmodule hardcaml_lib_lt #(parameter b=1) \n       ^~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_gnd\'\nmodule hardcaml_lib_gnd\n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_vdd\'\nmodule hardcaml_lib_vdd\n       ^~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_z\'\nmodule hardcaml_lib_z\n       ^~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_concat2\'\nmodule hardcaml_lib_concat2 \n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_mux2\'\nmodule hardcaml_lib_mux2 #(parameter b=1) \n       ^~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_lib_select\'\nmodule hardcaml_lib_select \n       ^~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hardcaml_tristate_buffer\'\nmodule hardcaml_tristate_buffer\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module hardcaml_lib_mulu
#(
    parameter w0=1, 
    parameter w1=1
) 
(
    input [w0-1:0] i0,
    input [w1-1:0] i1,
    output [w0+w1-1:0] o
);
    assign o = i0 * i1;
endmodule
module hardcaml_lib_mulu
#(
    parameter w0=1, 
    parameter w1=1
) 
(
    input [w0-1:0] i0,
    input [w1-1:0] i1,
    output [w0+w1-1:0] o
);

    assign o = i0 * i1;
endmodule