data/full_repos/permissive/472097485/Lang0/Not01/TestMe.v
data/verilator_xmls/4485d74b-e481-48df-90ec-167b13fe9bbc.xml
module TestMe( input wire A, output wire B );

	assign B=!A;

endmodule
module TestMe( input wire A, output wire B );


	assign B=!A;

endmodule