data/full_repos/permissive/420518472/testbenches/mock_pll.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/mock_pll.v:13: Unsupported: Ignoring delay on this delayed statement.\n  while(1) #1 new_clock = ~new_clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/420518472/testbenches/mock_pll.v:13: Infinite loop (condition always true)\n                                                                                     : ... In instance pll\n  while(1) #1 new_clock = ~new_clock;\n  ^~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pll(								
	input  clock_in,						
	output clock_out,						
	output locked = 1'b0					
);		
	reg new_clock = 1'b0;				
	assign clock_out = new_clock;		
									
	initial begin
		while(1) #1 new_clock = ~new_clock;
	end
endmodule
module pll(								
	input  clock_in,						
	output clock_out,						
	output locked = 1'b0					
);
		
	reg new_clock = 1'b0;				
	assign clock_out = new_clock;		
									
	initial begin
		while(1) #1 new_clock = ~new_clock;
	end
endmodule