data/full_repos/permissive/431550602/sim_1/tb_uartTX.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:30: Unsupported: Ignoring delay on this delayed statement.\n always begin clk <= ~clk; #5; end\n                           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Error: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:39: Unsupported: wait statements\n  wait(tx_done);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/431550602/sim_1/tb_uartTX.v:47: Unsupported: wait statements\n  wait(tx_done);\n  ^~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_uartTX;

    reg clk; 
    reg reset;
    wire tx;
    reg [7:0] t_data;
    wire tx_done;
    reg tx_start;
    wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(.clk(clk), .reset(reset), .uart_tick(baud_tick));
	
	uart_tx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uut(.clk(clk), .reset(reset), .tx_start(tx_start), .tx(tx), .s_tick(baud_tick), .tx_done_tick(tx_done), .data_in(t_data));
	
	initial begin	
		clk = 1'b0;       
                reset=1'b0;
                tx_start=1'b0;
		t_data=8'b0;		
	end
	
	always begin clk <= ~clk; #5; end
	
	always begin
	
		#50;
		t_data = 8'b00110010;		
		tx_start = 1'b1;
		#50;
		tx_start = 1'b0;
		wait(tx_done);
		
		#20;
		t_data = 8'b11101101;
		#20;
		tx_start = 1'b1;
		#10;
		tx_start = 1'b0;
		wait(tx_done);
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end	

endmodule
module tb_uartTX;


    reg clk; 
    reg reset;
    wire tx;
    reg [7:0] t_data;
    wire tx_done;
    reg tx_start;
    wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(.clk(clk), .reset(reset), .uart_tick(baud_tick));
	
	uart_tx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uut(.clk(clk), .reset(reset), .tx_start(tx_start), .tx(tx), .s_tick(baud_tick), .tx_done_tick(tx_done), .data_in(t_data));
	
	initial begin	
		clk = 1'b0;       
                reset=1'b0;
                tx_start=1'b0;
		t_data=8'b0;		
	end
	
	always begin clk <= ~clk; #5; end
	
	always begin
	
		#50;
		t_data = 8'b00110010;		
		tx_start = 1'b1;
		#50;
		tx_start = 1'b0;
		wait(tx_done);
		
		#20;
		t_data = 8'b11101101;
		#20;
		tx_start = 1'b1;
		#10;
		tx_start = 1'b0;
		wait(tx_done);
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end	

endmodule