data/full_repos/permissive/449807379/CPU_design/ram.v
data/verilator_xmls/fd5dfb1c-416e-402c-9cb6-b2af6ac65c47.xml
module RAM (Enable,ReadWrite,Address,DataIn,DataOut);
input Enable,ReadWrite;
input [31:0] DataIn;
input [15:0] Address;
output reg[31:0] DataOut;

reg [31:0] RAM [0:65535];

always @*
	if (Enable)
		if (ReadWrite)
			DataOut = RAM[Address];
		else
			RAM[Address] = DataIn;
	else 
		DataOut = 32'bz;
endmodule
module RAM (Enable,ReadWrite,Address,DataIn,DataOut);

input Enable,ReadWrite;
input [31:0] DataIn;
input [15:0] Address;
output reg[31:0] DataOut;

reg [31:0] RAM [0:65535];

always @*
	if (Enable)
		if (ReadWrite)
			DataOut = RAM[Address];
		else
			RAM[Address] = DataIn;
	else 
		DataOut = 32'bz;
endmodule