data/full_repos/permissive/441359809/src/yosys/examples/mimas2/example.v
data/verilator_xmls/9a35d1e9-90ef-4e6c-8b0e-9a4063236831.xml
module example(
	input wire CLK,
	output wire [7:0] LED
);

reg [27:0] ctr;
initial ctr = 0;

always @(posedge CLK)
	ctr <= ctr + 1;

assign LED = ctr[27:20];

endmodule
module example(
	input wire CLK,
	output wire [7:0] LED
);


reg [27:0] ctr;
initial ctr = 0;

always @(posedge CLK)
	ctr <= ctr + 1;

assign LED = ctr[27:20];

endmodule