data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:121: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   default next = S_LOAD_X;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:128: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   now <= S_LOAD_X;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:90: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    X_Coordinates <= temp_x + Counter[1:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:91: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    Y_Coordinates <= temp_y + Counter[3:2];\n                            ^\n%Error: Exiting due to 22 warning(s)\n'
module datapath(Clock, Resetn, XYCoordinates, Color, Plot, Black, X_enable, Y_enable, X_Coordinates, Y_Coordinates, Counter_enable, Color_enable, Color_Out);
	
	input Clock, Resetn, Plot, Black, X_enable, Y_enable, Color_enable, Counter_enable;
	input [6:0] XYCoordinates;
	input [2:0] Color;
	
	reg [3:0] Counter;
	reg [2:0] temp_color;
	reg [7:0] temp_x; 
	reg [6:0] temp_y;
	
	output reg [7:0] X_Coordinates;
	output reg [6:0] Y_Coordinates;
	output reg [2:0] Color_Out;

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			Counter <= 4'b0;
		else if(Counter == 4'b1111)
			Counter <= 4'b0;
		else if(Counter_enable == 1'b1)
			Counter <= Counter + 1; 
	end
	
	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_x <= 8'b0;	
		else if (X_enable == 1'b1)
			temp_x <= {1'b0, XYCoordinates};
	end
	

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_y <= 7'b0;
		else if (Y_enable == 1'b1)
			temp_y <= XYCoordinates;
	end	

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_color <= 3'b0;
		else if(Black == 1)
			temp_color <= 3'b0;
		else if (Color_enable == 1'b1)
			temp_color <= Color;
	end	
		
	always @(posedge Clock)
	begin
		if(Resetn == 1'b0)
			begin
				X_Coordinates <= 0;
				Y_Coordinates <= 0;
				Color_Out <= 0;
			end
		else if(Plot == 1'b1)
			begin
				X_Coordinates <= temp_x + Counter[1:0];
				Y_Coordinates <= temp_y + Counter[3:2];
				Color_Out <= temp_color;
			end
	end

endmodule
module datapath(Clock, Resetn, XYCoordinates, Color, Plot, Black, X_enable, Y_enable, X_Coordinates, Y_Coordinates, Counter_enable, Color_enable, Color_Out);

	
	input Clock, Resetn, Plot, Black, X_enable, Y_enable, Color_enable, Counter_enable;
	input [6:0] XYCoordinates;
	input [2:0] Color;
	
	reg [3:0] Counter;
	reg [2:0] temp_color;
	reg [7:0] temp_x; 
	reg [6:0] temp_y;
	
	output reg [7:0] X_Coordinates;
	output reg [6:0] Y_Coordinates;
	output reg [2:0] Color_Out;

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			Counter <= 4'b0;
		else if(Counter == 4'b1111)
			Counter <= 4'b0;
		else if(Counter_enable == 1'b1)
			Counter <= Counter + 1; 
	end
	
	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_x <= 8'b0;	
		else if (X_enable == 1'b1)
			temp_x <= {1'b0, XYCoordinates};
	end
	

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_y <= 7'b0;
		else if (Y_enable == 1'b1)
			temp_y <= XYCoordinates;
	end	

	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			temp_color <= 3'b0;
		else if(Black == 1)
			temp_color <= 3'b0;
		else if (Color_enable == 1'b1)
			temp_color <= Color;
	end	
		
	always @(posedge Clock)
	begin
		if(Resetn == 1'b0)
			begin
				X_Coordinates <= 0;
				Y_Coordinates <= 0;
				Color_Out <= 0;
			end
		else if(Plot == 1'b1)
			begin
				X_Coordinates <= temp_x + Counter[1:0];
				Y_Coordinates <= temp_y + Counter[3:2];
				Color_Out <= temp_color;
			end
	end

endmodule