data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #(CLOCK_PERIOD/2) clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #0;\n    ^\n%Error: data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v:31: syntax error, unexpected \'@\'\n    repeat(2) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v:38: syntax error, unexpected \'@\'\n    repeat(1000) @(posedge clk); #1;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32I/sim/tb_basic.v:38: Unsupported: Ignoring delay on this delayed statement.\n    repeat(1000) @(posedge clk); #1;\n                                 ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_basic();
  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;

  z1top #(
    .IMEM_HEX("firmware.hex")
  ) DUT(
    .CLK100MHZ(clk),
    .ck_rst(rst),
    
    
    .sw(),
    .led(),
    .btn()
  );
    
  initial begin
    #0;
    rst = 0;
    
    $display("[TEST]\tRESET pulled LOW.");
    
    repeat(2) @(posedge clk);
    
    @(negedge clk);
    rst = 1;
    
    $display("[TEST]\tRESET pulled HIGH.");
    
    repeat(1000) @(posedge clk); #1;
    
    
    $finish();
  end 

endmodule
module tb_basic();

  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;

  z1top #(
    .IMEM_HEX("firmware.hex")
  ) DUT(
    .CLK100MHZ(clk),
    .ck_rst(rst),
    
    
    .sw(),
    .led(),
    .btn()
  );
    
  initial begin
    #0;
    rst = 0;
    
    $display("[TEST]\tRESET pulled LOW.");
    
    repeat(2) @(posedge clk);
    
    @(negedge clk);
    rst = 1;
    
    $display("[TEST]\tRESET pulled HIGH.");
    
    repeat(1000) @(posedge clk); #1;
    
    
    $finish();
  end 

endmodule