data/full_repos/permissive/413345709/Project/PixelClock.v
data/verilator_xmls/fad349aa-8e66-46f5-b76d-a43413b15e68.xml
module clock_divider(reset, clk, vga_clk);
  input reset, clk;
  output reg vga_clk = 0;
  
  integer counter = 0;

  always@ (posedge reset or posedge clk)
  begin
    if (reset) 
      begin
        counter = 0;
      end
    else if(counter == 1)
      begin
			counter = 0;
			vga_clk <= ~vga_clk;
      end
    else
      begin
			counter = counter + 1;
      end
  end
endmodule
module clock_divider(reset, clk, vga_clk);

  input reset, clk;
  output reg vga_clk = 0;
  
  integer counter = 0;

  always@ (posedge reset or posedge clk)
  begin
    if (reset) 
      begin
        counter = 0;
      end
    else if(counter == 1)
      begin
			counter = 0;
			vga_clk <= ~vga_clk;
      end
    else
      begin
			counter = counter + 1;
      end
  end
endmodule