data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_wb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_wb.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'wb_dat_i\' generates 8 bits.\n                                                                                          : ... In instance sd_spi_wb\n  ADDR_STATUS : cs_reg <= wb_dat_i;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/sd_spi_wb.v:88: Cannot find file containing module: \'sd_spi\'\n   sd_spi sd_spi(.clk(clk),.rst(rst),\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/sd_spi\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/sd_spi.v\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/sd_spi.sv\n             sd_spi\n             sd_spi.v\n             sd_spi.sv\n             obj_dir/sd_spi\n             obj_dir/sd_spi.v\n             obj_dir/sd_spi.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module sd_spi_wb
  (input clk,
   input rst,
   

   output sd_clk,
   output sd_csn,
   output sd_mosi,
   input sd_miso,

   input wb_cyc_i,
   input wb_stb_i,
   input wb_we_i,
   input [1:0] wb_adr_i,
   input [7:0] wb_dat_i,
   output reg [7:0] wb_dat_o,
   output reg wb_ack_o);

   localparam ADDR_STATUS = 0;
   localparam ADDR_CLKDIV = 1;
   localparam ADDR_WRITE = 2;
   localparam ADDR_READ = 3;

   wire [7:0] status, rcv_dat;
   reg [7:0]  clkdiv;
   wire       ready;
   reg 	      ack_d1;

   reg 	      cs_reg;
   assign     sd_csn = ~cs_reg;
   
   always @(posedge clk)
     if(rst) ack_d1 <= 0;
     else ack_d1 <= wb_ack_o;
   
   always @(posedge clk)
     if(rst) wb_ack_o <= 0;
     else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
   
   always @(posedge clk)
     case(wb_adr_i)
       ADDR_STATUS : wb_dat_o <= {7'd0,ready};
       ADDR_CLKDIV : wb_dat_o <= clkdiv;
       ADDR_READ : wb_dat_o <= rcv_dat;
       default : wb_dat_o <= 0;
     endcase

   always @(posedge clk)
     if(rst)
       begin
	  clkdiv <= 200;
	  cs_reg <= 0;
       end
     else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
       case(wb_adr_i)
	 ADDR_STATUS : cs_reg <= wb_dat_i;
	 ADDR_CLKDIV : clkdiv <= wb_dat_i;
       endcase

   wire       go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE);
   
   sd_spi sd_spi(.clk(clk),.rst(rst),
		 .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
		 .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
		 .go(go),.ready(ready) );

endmodule
module sd_spi_wb
  (input clk,
   input rst,
   

   output sd_clk,
   output sd_csn,
   output sd_mosi,
   input sd_miso,

   input wb_cyc_i,
   input wb_stb_i,
   input wb_we_i,
   input [1:0] wb_adr_i,
   input [7:0] wb_dat_i,
   output reg [7:0] wb_dat_o,
   output reg wb_ack_o);


   localparam ADDR_STATUS = 0;
   localparam ADDR_CLKDIV = 1;
   localparam ADDR_WRITE = 2;
   localparam ADDR_READ = 3;

   wire [7:0] status, rcv_dat;
   reg [7:0]  clkdiv;
   wire       ready;
   reg 	      ack_d1;

   reg 	      cs_reg;
   assign     sd_csn = ~cs_reg;
   
   always @(posedge clk)
     if(rst) ack_d1 <= 0;
     else ack_d1 <= wb_ack_o;
   
   always @(posedge clk)
     if(rst) wb_ack_o <= 0;
     else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
   
   always @(posedge clk)
     case(wb_adr_i)
       ADDR_STATUS : wb_dat_o <= {7'd0,ready};
       ADDR_CLKDIV : wb_dat_o <= clkdiv;
       ADDR_READ : wb_dat_o <= rcv_dat;
       default : wb_dat_o <= 0;
     endcase

   always @(posedge clk)
     if(rst)
       begin
	  clkdiv <= 200;
	  cs_reg <= 0;
       end
     else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
       case(wb_adr_i)
	 ADDR_STATUS : cs_reg <= wb_dat_i;
	 ADDR_CLKDIV : clkdiv <= wb_dat_i;
       endcase

   wire       go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE);
   
   sd_spi sd_spi(.clk(clk),.rst(rst),
		 .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
		 .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
		 .go(go),.ready(ready) );

endmodule