data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v
1: b'%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:64: Cannot find include file: brams_init_20.vh\n  `include "brams_init_20.vh" \n           ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/brams_init_20.vh\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/brams_init_20.vh.v\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/brams_init_20.vh.sv\n             brams_init_20.vh\n             brams_init_20.vh.v\n             brams_init_20.vh.sv\n             obj_dir/brams_init_20.vh\n             obj_dir/brams_init_20.vh.v\n             obj_dir/brams_init_20.vh.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:142: Cannot find include file: brams_init_40.vh\n  `include "brams_init_40.vh" \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:252: Cannot find include file: brams_init_20.vh\n   `include "brams_init_20.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:363: Cannot find include file: brams_init_40.vh\n   `include "brams_init_40.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:449: Cannot find include file: brams_init_40.vh\n   `include "brams_init_40.vh" // INIT_80 .. INIT_FF \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/brams_map.v:487: Cannot find include file: brams_init_40.vh\n   `include "brams_init_40.vh" // INIT_00 .. INIT_7F \n            ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 15;
	parameter CFG_DBITS = 80;
	parameter CFG_ENABLE_A = 1;
	parameter CFG_ENABLE_B = 1;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;


	parameter [40959:0] INIT = 40960'b0;

	input CLK2;
	input CLK3;


	input [15:0] A1ADDR;
	input [79:0] A1DATA;
	input [79:0] A1EN;


	input [15:0] B1ADDR;
	output [79:0] B1DATA;
	input [0:0] B1EN;


	wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;


	wire [15:0] ADDRA = {A1ADDR, 7'b0};
	wire [15:0] ADDRB = {B1ADDR, 7'b0};

	localparam INIT_CHUNK_SIZE = 320;

	function [319:0] permute_init;
		input [INIT_CHUNK_SIZE-1:0] chunk;
		integer i;
		begin
			permute_init = chunk;
		end
	endfunction

	CC_BRAM_40K #(
		`define INIT_LOWER
		`include "brams_init_40.vh"
		`undef INIT_LOWER
		.LOC("UNPLACED"),
		.CAS("NONE"),
		.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
		.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
		.RAM_MODE("SDP"),
		.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
		.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
		.A_EN_INV(1'b0), .B_EN_INV(1'b0),
		.A_WE_INV(1'b0), .B_WE_INV(1'b0),
		.A_DO_REG(1'b0), .B_DO_REG(1'b0),
		.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
	) _TECHMAP_REPLACE_ (
		.A_DO(B1DATA[39:0]),
		.B_DO(B1DATA[79:40]),
		.A_ECC_1B_ERR(A_ECC_1B_ERR),
		.B_ECC_1B_ERR(B_ECC_1B_ERR),
		.A_ECC_2B_ERR(A_ECC_2B_ERR),
		.B_ECC_2B_ERR(B_ECC_2B_ERR),
		.A_CLK(CLK2),
		.B_CLK(CLK3),
		.A_EN(1'b1),
		.B_EN(B1EN),
		.A_WE(|A1EN),
		.B_WE(1'b0),
		.A_ADDR(ADDRA),
		.B_ADDR(ADDRB),
		.A_DI(A1DATA[39:0]),
		.B_DI(A1DATA[79:40]),
		.A_BM(A1EN[39:0]),
		.B_BM(A1EN[79:40])
	);

endmodule
module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);


	parameter CFG_ABITS = 15;
	parameter CFG_DBITS = 80;
	parameter CFG_ENABLE_A = 1;
	parameter CFG_ENABLE_B = 1;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;


	parameter [40959:0] INIT = 40960'b0;

	input CLK2;
	input CLK3;


	input [15:0] A1ADDR;
	input [79:0] A1DATA;
	input [79:0] A1EN;


	input [15:0] B1ADDR;
	output [79:0] B1DATA;
	input [0:0] B1EN;


	wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;


	wire [15:0] ADDRA = {A1ADDR, 7'b0};
	wire [15:0] ADDRB = {B1ADDR, 7'b0};

	localparam INIT_CHUNK_SIZE = 320;

	function [319:0] permute_init;
		input [INIT_CHUNK_SIZE-1:0] chunk;
		integer i;
		begin
			permute_init = chunk;
		end
	endfunction

	CC_BRAM_40K #(
		`define INIT_LOWER
		`include "brams_init_40.vh"
		`undef INIT_LOWER
		.LOC("UNPLACED"),
		.CAS("NONE"),
		.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
		.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
		.RAM_MODE("SDP"),
		.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
		.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
		.A_EN_INV(1'b0), .B_EN_INV(1'b0),
		.A_WE_INV(1'b0), .B_WE_INV(1'b0),
		.A_DO_REG(1'b0), .B_DO_REG(1'b0),
		.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
	) _TECHMAP_REPLACE_ (
		.A_DO(B1DATA[39:0]),
		.B_DO(B1DATA[79:40]),
		.A_ECC_1B_ERR(A_ECC_1B_ERR),
		.B_ECC_1B_ERR(B_ECC_1B_ERR),
		.A_ECC_2B_ERR(A_ECC_2B_ERR),
		.B_ECC_2B_ERR(B_ECC_2B_ERR),
		.A_CLK(CLK2),
		.B_CLK(CLK3),
		.A_EN(1'b1),
		.B_EN(B1EN),
		.A_WE(|A1EN),
		.B_WE(1'b0),
		.A_ADDR(ADDRA),
		.B_ADDR(ADDRB),
		.A_DI(A1DATA[39:0]),
		.B_DI(A1DATA[79:40]),
		.A_BM(A1EN[39:0]),
		.B_BM(A1EN[79:40])
	);

endmodule