data/full_repos/permissive/487082250/sources/randomLFSR.v
data/verilator_xmls/63fb0764-7635-45a6-a9e0-3cf22567fa04.xml
module randomLFSR(
    input clk,
	output [4:0] d
	);

	reg [7:0] lfsr = 8'b10000001;
	reg [3:0] out;
	reg [7:0] temp;
	always @ (posedge clk) begin
	temp = (lfsr ^ (lfsr >> 1) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1;
	lfsr = (lfsr >> 1) | (temp << 7);
	if (lfsr[5:2] < 15) begin
	out = lfsr[5:2];
	end
	end
	assign d[4] = 0;
	assign d[3:0] = out;

endmodule
module randomLFSR(
    input clk,
	output [4:0] d
	);


	reg [7:0] lfsr = 8'b10000001;
	reg [3:0] out;
	reg [7:0] temp;
	always @ (posedge clk) begin
	temp = (lfsr ^ (lfsr >> 1) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1;
	lfsr = (lfsr >> 1) | (temp << 7);
	if (lfsr[5:2] < 15) begin
	out = lfsr[5:2];
	end
	end
	assign d[4] = 0;
	assign d[3:0] = out;

endmodule