data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("vita_rx_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,vita_rx_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:110: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:182: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:186: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rx_dsp_model
  (input clk, input reset,
   input run,
   input [7:0] decim,
   output strobe,
   output [31:0] sample);
   
   reg [15:0] 	  pktnum = 0;
   reg [15:0] 	 counter = 0;

   reg 		 run_d1;
   always @(posedge clk) run_d1 <= run;
   
   always @(posedge clk)
     if(run & ~run_d1)
       begin
	  counter 		<= 0;
	  pktnum 		<= pktnum + 1;
       end
     else if(run & strobe)
       counter 			<= counter + 1;
       
   assign sample 		 = {pktnum,counter};

   reg [7:0] stb_ctr = 0;
   
   always @(posedge clk)
     if(reset)
       stb_ctr 	 <= 0;
     else if(run & ~run_d1)
       stb_ctr 	 <= 1;
     else if(run)
       if(stb_ctr == decim-1)
	 stb_ctr <= 0;
       else
	 stb_ctr <= stb_ctr + 1;

   assign strobe  = stb_ctr == decim-1;
   
endmodule
module rx_dsp_model
  (input clk, input reset,
   input run,
   input [7:0] decim,
   output strobe,
   output [31:0] sample);

   
   reg [15:0] 	  pktnum = 0;
   reg [15:0] 	 counter = 0;

   reg 		 run_d1;
   always @(posedge clk) run_d1 <= run;
   
   always @(posedge clk)
     if(run & ~run_d1)
       begin
	  counter 		<= 0;
	  pktnum 		<= pktnum + 1;
       end
     else if(run & strobe)
       counter 			<= counter + 1;
       
   assign sample 		 = {pktnum,counter};

   reg [7:0] stb_ctr = 0;
   
   always @(posedge clk)
     if(reset)
       stb_ctr 	 <= 0;
     else if(run & ~run_d1)
       stb_ctr 	 <= 1;
     else if(run)
       if(stb_ctr == decim-1)
	 stb_ctr <= 0;
       else
	 stb_ctr <= stb_ctr + 1;

   assign strobe  = stb_ctr == decim-1;
   
endmodule