data/full_repos/permissive/500345502/verilog/rtl/snn-accelerator/properties/src/out_neuron.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500345502/verilog/rtl/snn-accelerator/properties/src/out_neuron.v:43: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                               : ... In instance out_neuron.num_ones0\n            ones = ones + A[i];  \n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module out_neuron (
    input wire              clk,
    input wire              reset,
    input wire [127:0]      fan_in,
    output reg              spike,
    output reg [7:0]        state
);

    reg [7:0] threshold;
    wire [7:0] post_synaptic, state_hist;

    num_ones num_ones0 (.A(fan_in), .ones(post_synaptic));
    assign state_hist = post_synaptic + (spike ? 0 : (state >> 1));

    integer i;
    always @(posedge clk) begin
        if (reset) begin
            threshold <= 32;
            state <= 0;
            spike <= 0;
        end else begin
            state <= state_hist;
            spike <= (state >= threshold);
        end
    end

endmodule
module out_neuron (
    input wire              clk,
    input wire              reset,
    input wire [127:0]      fan_in,
    output reg              spike,
    output reg [7:0]        state
);


    reg [7:0] threshold;
    wire [7:0] post_synaptic, state_hist;

    num_ones num_ones0 (.A(fan_in), .ones(post_synaptic));
    assign state_hist = post_synaptic + (spike ? 0 : (state >> 1));

    integer i;
    always @(posedge clk) begin
        if (reset) begin
            threshold <= 32;
            state <= 0;
            spike <= 0;
        end else begin
            state <= state_hist;
            spike <= (state >= threshold);
        end
    end

endmodule