data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_ctl_edgelogic.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_ctl_edgelogic.v:53: Cannot find file containing module: 'dffrl_s'\ndffrl_s #(1) flop_data(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffrl_s.sv\n             dffrl_s\n             dffrl_s.v\n             dffrl_s.sv\n             obj_dir/dffrl_s\n             obj_dir/dffrl_s.v\n             obj_dir/dffrl_s.sv\n%Error: Exiting due to 1 error(s)\n"
module dram_ctl_edgelogic(

   ctl_pad_clk_so, to_pad, 

   clk, rst_l, ctl_pad_clk_se, ctl_pad_clk_si, data, testmode_l
   );




input			clk;
input			rst_l;
input			testmode_l;
input			ctl_pad_clk_se;
input			ctl_pad_clk_si;
input			data;




output			ctl_pad_clk_so;
output			to_pad;






wire tclk = testmode_l ? ~clk : clk;



dffrl_s #(1) flop_data(
		.din(data),
		.q(to_pad),
		.rst_l(rst_l),
		.clk(tclk), .si(ctl_pad_clk_si), .so(ctl_pad_clk_so), .se(ctl_pad_clk_se));

endmodule
module dram_ctl_edgelogic(

   ctl_pad_clk_so, to_pad, 

   clk, rst_l, ctl_pad_clk_se, ctl_pad_clk_si, data, testmode_l
   );





input			clk;
input			rst_l;
input			testmode_l;
input			ctl_pad_clk_se;
input			ctl_pad_clk_si;
input			data;




output			ctl_pad_clk_so;
output			to_pad;






wire tclk = testmode_l ? ~clk : clk;



dffrl_s #(1) flop_data(
		.din(data),
		.q(to_pad),
		.rst_l(rst_l),
		.clk(tclk), .si(ctl_pad_clk_si), .so(ctl_pad_clk_so), .se(ctl_pad_clk_se));

endmodule