data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #clk_h_period;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #wait_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #wait_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #wait_period;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/ADC_filter_tb.v:9: Cannot find file containing module: \'ADC_filter\'\n ADC_filter #(.ADC_WIDTH(12)) filter0 (.ADC_in(ADC_in), .ADC_clk(ADC_clk), .ADC_out(ADC_out));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/ADC_filter\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/ADC_filter.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/ADC_filter.sv\n             ADC_filter\n             ADC_filter.v\n             ADC_filter.sv\n             obj_dir/ADC_filter\n             obj_dir/ADC_filter.v\n             obj_dir/ADC_filter.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ADC_filter_tb;
	
	reg [11:0] ADC_in = 12'h000;
	reg ADC_clk = 1'b0;
	wire [11:0] ADC_out;

	localparam clk_h_period = 2;
	localparam wait_period = clk_h_period * 32;
	ADC_filter #(.ADC_WIDTH(12)) filter0 (.ADC_in(ADC_in), .ADC_clk(ADC_clk), .ADC_out(ADC_out));

	always
	begin
		ADC_clk = 1'b0;
		#clk_h_period;
		ADC_clk = 1'b1;
		#clk_h_period;
	end

	initial
	begin
		#clk_h_period;
		ADC_in = 12'hAAA;
		#wait_period;
		#clk_h_period;
		#clk_h_period;
		ADC_in = 12'h555;
		#wait_period;
		#wait_period;
		$finish;
	end
endmodule
module ADC_filter_tb;

	
	reg [11:0] ADC_in = 12'h000;
	reg ADC_clk = 1'b0;
	wire [11:0] ADC_out;

	localparam clk_h_period = 2;
	localparam wait_period = clk_h_period * 32;
	ADC_filter #(.ADC_WIDTH(12)) filter0 (.ADC_in(ADC_in), .ADC_clk(ADC_clk), .ADC_out(ADC_out));

	always
	begin
		ADC_clk = 1'b0;
		#clk_h_period;
		ADC_clk = 1'b1;
		#clk_h_period;
	end

	initial
	begin
		#clk_h_period;
		ADC_in = 12'hAAA;
		#wait_period;
		#clk_h_period;
		#clk_h_period;
		ADC_in = 12'h555;
		#wait_period;
		#wait_period;
		$finish;
	end
endmodule