data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/DAC/DAC_OR_CHECK.v
data/verilator_xmls/5543b53f-6ec9-43c9-bc7e-c25f28f928b6.xml
module DAC_OR_CHECK
#(
	parameter DAC_WIDTH = 14
)
(
	input [DAC_WIDTH - 1:0] DAC_in,
	output [DAC_WIDTH - 1:0] DAC_out
);
	reg [DAC_WIDTH - 1:0] int_DAC_reg = 14'h0000;
	assign DAC_out = int_DAC_reg;
	always @(DAC_in)
	begin
		if(~DAC_in[DAC_WIDTH-1])
			int_DAC_reg = 14'h0000;
		else
			int_DAC_reg = DAC_in;
	end
endmodule
module DAC_OR_CHECK
#(
	parameter DAC_WIDTH = 14
)
(
	input [DAC_WIDTH - 1:0] DAC_in,
	output [DAC_WIDTH - 1:0] DAC_out
);

	reg [DAC_WIDTH - 1:0] int_DAC_reg = 14'h0000;
	assign DAC_out = int_DAC_reg;
	always @(DAC_in)
	begin
		if(~DAC_in[DAC_WIDTH-1])
			int_DAC_reg = 14'h0000;
		else
			int_DAC_reg = DAC_in;
	end
endmodule