data/full_repos/permissive/441359809/src/yosys/backends/simplec/test00_uut.v
data/verilator_xmls/b7b6ca9c-4710-4090-895c-7527aecfe29b.xml
module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
  unit_x unit_x_inst (.a(a), .b(b), .c(c), .x(x));
  unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
  assign z = a ^ b ^ c, w = z;
endmodule
module test(input [31:0] a, b, c, output [31:0] x, y, z, w);

  unit_x unit_x_inst (.a(a), .b(b), .c(c), .x(x));
  unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
  assign z = a ^ b ^ c, w = z;
endmodule