data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:13: Unsupported or unknown PLI call: $monitor\n  $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 0;\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:22: syntax error, unexpected \'@\'\n  @ (negedge clk);\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:27: syntax error, unexpected \'@\'\n     @ (negedge clk);\n     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:30: syntax error, unexpected \'@\'\n  @ (negedge clk);\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:34: syntax error, unexpected \'@\'\n     @ (negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fifo_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;\n       ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_tb ();
parameter DATA_WIDTH = 8;

parameter ADDR_WIDTH = 3; 

reg clk, rst, rd_en, wr_en;
reg [DATA_WIDTH-1:0] data_in ;
wire [DATA_WIDTH-1:0] data_out ;
wire empty, full;
integer i;

initial begin
  $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", 
    $time, wr_en, data_in,  rd_en, data_out);
  clk = 0;
  rst = 0;
  rd_en = 0;
  wr_en = 0;
  data_in = 0;
  #5 rst = 1;
  #5 rst = 0;
  @ (negedge clk);
  wr_en = 1;

  for (i = 0 ; i < 10; i = i + 1) begin
     data_in  = i;
     @ (negedge clk);
  end
  wr_en  = 0;
  @ (negedge clk);
  rd_en = 1;

  for (i = 0 ; i < 10; i = i + 1) begin
     @ (negedge clk);
  end
  rd_en = 0;
  #100 $finish;
end  

always #1 clk = !clk;

syn_fifo #(DATA_WIDTH,ADDR_WIDTH) fifo(
.clk      (clk)     ,
.rst      (rst)     ,
.wr_cs    (1'b1)    ,
.rd_cs    (1'b1)    ,
.data_in  (data_in) ,
.rd_en    (rd_en)   ,
.wr_en    (wr_en)   ,
.data_out (data_out),
.empty    (empty)   ,
.full     (full)
);   

endmodule
module fifo_tb ();

parameter DATA_WIDTH = 8;

parameter ADDR_WIDTH = 3; 

reg clk, rst, rd_en, wr_en;
reg [DATA_WIDTH-1:0] data_in ;
wire [DATA_WIDTH-1:0] data_out ;
wire empty, full;
integer i;

initial begin
  $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", 
    $time, wr_en, data_in,  rd_en, data_out);
  clk = 0;
  rst = 0;
  rd_en = 0;
  wr_en = 0;
  data_in = 0;
  #5 rst = 1;
  #5 rst = 0;
  @ (negedge clk);
  wr_en = 1;

  for (i = 0 ; i < 10; i = i + 1) begin
     data_in  = i;
     @ (negedge clk);
  end
  wr_en  = 0;
  @ (negedge clk);
  rd_en = 1;

  for (i = 0 ; i < 10; i = i + 1) begin
     @ (negedge clk);
  end
  rd_en = 0;
  #100 $finish;
end  

always #1 clk = !clk;

syn_fifo #(DATA_WIDTH,ADDR_WIDTH) fifo(
.clk      (clk)     ,
.rst      (rst)     ,
.wr_cs    (1'b1)    ,
.rd_cs    (1'b1)    ,
.data_in  (data_in) ,
.rd_en    (rd_en)   ,
.wr_en    (wr_en)   ,
.data_out (data_out),
.empty    (empty)   ,
.full     (full)
);   

endmodule