data/full_repos/permissive/435890256/my_riscv/floprc.sv
data/verilator_xmls/5868e9de-323b-495a-a38d-9e4ef1dd8025.xml
module floprc 
#(parameter WIDTH = 8) (
	input logic clk,
  input logic rst_n,
  input logic clear,
	input logic [WIDTH-1:0] d,
	output logic [WIDTH-1:0] q
);

always @(posedge clk) begin
  if(~rst_n) begin
    q <= 0;
  end else if(clear) begin
    q <= 0;
  end else begin
    q <= d;
  end
end

endmodule
module floprc 
#(parameter WIDTH = 8) (
	input logic clk,
  input logic rst_n,
  input logic clear,
	input logic [WIDTH-1:0] d,
	output logic [WIDTH-1:0] q
);


always @(posedge clk) begin
  if(~rst_n) begin
    q <= 0;
  end else if(clear) begin
    q <= 0;
  end else begin
    q <= d;
  end
end

endmodule