data/full_repos/permissive/424292861/guia9/clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/clock.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #12 clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/clock.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #3 signal = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/clock.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #3 signal = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/clock.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #3 signal = 1\'b0;\n      ^\n%Error: data/full_repos/permissive/424292861/guia9/clock.v:34: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n   always @(posedge clock & on) begin\n                          ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock(output clk);
   reg clk;

   initial
   begin
      clk = 1'b0;
   end

   always
   begin
      #12 clk = ~clk;
   end

endmodule
module clock(output clk);

   reg clk;

   initial
   begin
      clk = 1'b0;
   end

   always
   begin
      #12 clk = ~clk;
   end

endmodule