data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v
1: b"%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:71: syntax error, unexpected output, expecting ')' or ','\nmodule nor5 (input wire i0, i1, i2, i3, i4 output wire o);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:73: syntax error, unexpected IDENTIFIER\n   or2 or2_0 (i0, i1, t0);\n   ^~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:387: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n pc_inc = load_ir\n ^~~~~~\n%Error: Cannot continue\n"
module _reg_file_2_1 (input wire clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in, output wire d_out_a, d_out_b);
  wire l0, l1, o0, o1;
  dfsl dfsl_0 (clk, reset, l0, d_in, o0);
  dfrl dfrl_1 (clk, reset, l1, d_in, o1);
  mux2 mux2_a (o0, o1, rd_addr_a, d_out_a);
  mux2 mux2_b (o0, o1, rd_addr_b, d_out_b);
  demux2 demux2_0 (wr, wr_addr, l0, l1);
endmodule
module _reg_file_2_1 (input wire clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in, output wire d_out_a, d_out_b);

  wire l0, l1, o0, o1;
  dfsl dfsl_0 (clk, reset, l0, d_in, o0);
  dfrl dfrl_1 (clk, reset, l1, d_in, o1);
  mux2 mux2_a (o0, o1, rd_addr_a, d_out_a);
  mux2 mux2_b (o0, o1, rd_addr_b, d_out_b);
  demux2 demux2_0 (wr, wr_addr, l0, l1);
endmodule