data/full_repos/permissive/515672768/test.v
1: b'%Error: data/full_repos/permissive/515672768/test.v:2: Cannot find include file: LFSR.v\n`include "LFSR.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515672768,data/full_repos/permissive/515672768/LFSR.v\n             data/full_repos/permissive/515672768,data/full_repos/permissive/515672768/LFSR.v.v\n             data/full_repos/permissive/515672768,data/full_repos/permissive/515672768/LFSR.v.sv\n             LFSR.v\n             LFSR.v.v\n             LFSR.v.sv\n             obj_dir/LFSR.v\n             obj_dir/LFSR.v.v\n             obj_dir/LFSR.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/515672768/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n  always #2 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515672768/test.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20 seed_en=0;\n        ^\n%Error: data/full_repos/permissive/515672768/test.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("LFSR.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515672768/test.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515672768/test.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module test;
  reg clk,Enable,seed_en;
  reg [7:0] Seed_Data;
  wire [7:0] RandNum;
  wire Gen_done;
  LFSR m1(.clk(clk),.Enable(Enable),.Seed_Data(Seed_Data),.seed_en(seed_en),.RandNum(RandNum),.Gen_done(Gen_done)); 
    

  initial 
  begin
  clk=0;
  end
  always #2 clk=~clk;
    
  initial 
    begin
        seed_en=1;
        Enable=1;      
        Seed_Data=8'b11010101;
        #20 seed_en=0;
  end
  
  initial 
  begin
    $dumpfile("LFSR.vcd");
    $dumpvars(0,test);
    
    #500 $finish;
  end

endmodule
module test;

  reg clk,Enable,seed_en;
  reg [7:0] Seed_Data;
  wire [7:0] RandNum;
  wire Gen_done;
  LFSR m1(.clk(clk),.Enable(Enable),.Seed_Data(Seed_Data),.seed_en(seed_en),.RandNum(RandNum),.Gen_done(Gen_done)); 
    

  initial 
  begin
  clk=0;
  end
  always #2 clk=~clk;
    
  initial 
    begin
        seed_en=1;
        Enable=1;      
        Seed_Data=8'b11010101;
        #20 seed_en=0;
  end
  
  initial 
  begin
    $dumpfile("LFSR.vcd");
    $dumpvars(0,test);
    
    #500 $finish;
  end

endmodule