data/full_repos/permissive/455421905/freq/freq_input_buffer/freq_input_buffer.v
1: b"%Error: data/full_repos/permissive/455421905/freq/freq_input_buffer/freq_input_buffer.v:41: Cannot find file containing module: 'MULTI_CHANNEL_TWOENTRY_FIFO'\n  MULTI_CHANNEL_TWOENTRY_FIFO #(\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/freq/freq_input_buffer,data/full_repos/permissive/455421905/MULTI_CHANNEL_TWOENTRY_FIFO\n             data/full_repos/permissive/455421905/freq/freq_input_buffer,data/full_repos/permissive/455421905/MULTI_CHANNEL_TWOENTRY_FIFO.v\n             data/full_repos/permissive/455421905/freq/freq_input_buffer,data/full_repos/permissive/455421905/MULTI_CHANNEL_TWOENTRY_FIFO.sv\n             MULTI_CHANNEL_TWOENTRY_FIFO\n             MULTI_CHANNEL_TWOENTRY_FIFO.v\n             MULTI_CHANNEL_TWOENTRY_FIFO.sv\n             obj_dir/MULTI_CHANNEL_TWOENTRY_FIFO\n             obj_dir/MULTI_CHANNEL_TWOENTRY_FIFO.v\n             obj_dir/MULTI_CHANNEL_TWOENTRY_FIFO.sv\n%Error: Exiting due to 1 error(s)\n"
module freq_input_buffer(
                         input  wire                   CLK,
                         input  wire                   RST,
                         input  wire                   enq,
                         input  wire [`C_LOG-1:0]      enq_idx,
                         input  wire                   deq,
                         input  wire [`C_LOG-1:0]      deq_idx,
                         input  wire [`FIFO_WIDTH-1:0] din,
                         output wire [`FIFO_WIDTH-1:0] dot,
                         output wire [(1<<`C_LOG)-1:0] emp,
                         output wire [(1<<`C_LOG)-1:0] rdy
                         );

  MULTI_CHANNEL_TWOENTRY_FIFO #(
                                (`E_LOG+`W_LOG),
                                (`DATW<<`P_LOG),
                                `USE_IPCORE
                                )
  input_buffer(
               CLK,
               RST,
               enq,
               enq_idx,
               deq,
               deq_idx,
               din,
               dot,
               emp,
               rdy
               );

endmodule
module freq_input_buffer(
                         input  wire                   CLK,
                         input  wire                   RST,
                         input  wire                   enq,
                         input  wire [`C_LOG-1:0]      enq_idx,
                         input  wire                   deq,
                         input  wire [`C_LOG-1:0]      deq_idx,
                         input  wire [`FIFO_WIDTH-1:0] din,
                         output wire [`FIFO_WIDTH-1:0] dot,
                         output wire [(1<<`C_LOG)-1:0] emp,
                         output wire [(1<<`C_LOG)-1:0] rdy
                         );


  MULTI_CHANNEL_TWOENTRY_FIFO #(
                                (`E_LOG+`W_LOG),
                                (`DATW<<`P_LOG),
                                `USE_IPCORE
                                )
  input_buffer(
               CLK,
               RST,
               enq,
               enq_idx,
               deq,
               deq_idx,
               din,
               dot,
               emp,
               rdy
               );

endmodule