data/full_repos/permissive/413582930/reg_file_tb/reg_file_wrapper.v
1: b"%Error: data/full_repos/permissive/413582930/reg_file_tb/reg_file_wrapper.v:31: Cannot find file containing module: 'reg_file'\n    reg_file real_DUT (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413582930/reg_file_tb,data/full_repos/permissive/413582930/reg_file\n             data/full_repos/permissive/413582930/reg_file_tb,data/full_repos/permissive/413582930/reg_file.v\n             data/full_repos/permissive/413582930/reg_file_tb,data/full_repos/permissive/413582930/reg_file.sv\n             reg_file\n             reg_file.v\n             reg_file.sv\n             obj_dir/reg_file\n             obj_dir/reg_file.v\n             obj_dir/reg_file.sv\n%Error: Exiting due to 1 error(s)\n"
module reg_file_wrapper(
    rst_n,
    clk,
    rs1,
    rs2,
    rd,
    rs1_v,
    rs2_v,
    rd_v,
    we,
    clk_h
);
    
    input wire        rst_n;
    input wire        clk;
    input wire [4:0]  rs1;
    input wire [4:0]  rs2;
    input wire [4:0]  rd; 
    output wire [31:0] rs1_v;
    output wire [31:0] rs2_v;
    input wire [31:0] rd_v;
    input wire        we;

    output reg clk_h = 1'b0;
    always @(negedge rst_n, posedge clk)
        if (!rst_n) clk_h <= 1'b0;
        else clk_h <= !clk_h;
    
    reg_file real_DUT (
        .rst_n(rst_n),
        .clk(clk),
        .rs1(rs1),
        .rs2(rs2),
        .rd(rd),
        .rs1_v(rs1_v),
        .rs2_v(rs2_v),
        .rd_v(rd_v),
        .we(we)
    );

`ifdef COCOTB_SIM
initial begin
  $dumpfile ("reg_file_wrapper.vcd");
  $dumpvars (0, reg_file_wrapper);
  #1;
end
`endif

endmodule
module reg_file_wrapper(
    rst_n,
    clk,
    rs1,
    rs2,
    rd,
    rs1_v,
    rs2_v,
    rd_v,
    we,
    clk_h
);

    
    input wire        rst_n;
    input wire        clk;
    input wire [4:0]  rs1;
    input wire [4:0]  rs2;
    input wire [4:0]  rd; 
    output wire [31:0] rs1_v;
    output wire [31:0] rs2_v;
    input wire [31:0] rd_v;
    input wire        we;

    output reg clk_h = 1'b0;
    always @(negedge rst_n, posedge clk)
        if (!rst_n) clk_h <= 1'b0;
        else clk_h <= !clk_h;
    
    reg_file real_DUT (
        .rst_n(rst_n),
        .clk(clk),
        .rs1(rs1),
        .rs2(rs2),
        .rd(rd),
        .rs1_v(rs1_v),
        .rs2_v(rs2_v),
        .rd_v(rd_v),
        .we(we)
    );

`ifdef COCOTB_SIM
initial begin
  $dumpfile ("reg_file_wrapper.vcd");
  $dumpvars (0, reg_file_wrapper);
  #1;
end
`endif

endmodule