data/full_repos/permissive/463439324/decap/barrett.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463439324/decap/barrett.v:45: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s SUB generates 28 bits.\n                                                                       : ... In instance barrett\n    assign r0 = dividend - { { M0LEN {1\'b0} }, q0 } * { { M0LEN {1\'b0} }, m0 };\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module barrett ( dividend, m0, m0_inverse, quotient, remainder ) ;

    parameter M0LEN = 14;
    parameter SHIFT = 27;

    localparam M0LEN2 = M0LEN * 2;

    input   [M0LEN2-1:0]    dividend;
    input   [M0LEN-1:0]     m0;
    input   [SHIFT-1:0]     m0_inverse;
    output  [M0LEN-1:0]     quotient;
    output  [M0LEN-1:0]     remainder;

    wire    [M0LEN2+SHIFT-1:0]  quo2;
    wire    [M0LEN-1:0]         q0;
    wire    [M0LEN-1:0]         q1;
    wire    [M0LEN-1:0]         r0;
    wire    [M0LEN:0]           r1;

    assign quo2 = { { SHIFT {1'b0} }, dividend } * { { M0LEN2 {1'b0} }, m0_inverse };

    assign q0 = quo2[SHIFT +: M0LEN];
    assign q1 = q0 + { { (M0LEN - 1) {1'b0} }, {1'b1} };
    assign r0 = dividend - { { M0LEN {1'b0} }, q0 } * { { M0LEN {1'b0} }, m0 };
    assign r1 = { 1'b0, r0 } - { 1'b0, m0 };

    assign quotient = r1[M0LEN] ? q0 : q1;
    assign remainder = r1[M0LEN] ? r0 : r1[M0LEN-1:0];

endmodule
module barrett ( dividend, m0, m0_inverse, quotient, remainder ) ;


    parameter M0LEN = 14;
    parameter SHIFT = 27;

    localparam M0LEN2 = M0LEN * 2;

    input   [M0LEN2-1:0]    dividend;
    input   [M0LEN-1:0]     m0;
    input   [SHIFT-1:0]     m0_inverse;
    output  [M0LEN-1:0]     quotient;
    output  [M0LEN-1:0]     remainder;

    wire    [M0LEN2+SHIFT-1:0]  quo2;
    wire    [M0LEN-1:0]         q0;
    wire    [M0LEN-1:0]         q1;
    wire    [M0LEN-1:0]         r0;
    wire    [M0LEN:0]           r1;

    assign quo2 = { { SHIFT {1'b0} }, dividend } * { { M0LEN2 {1'b0} }, m0_inverse };

    assign q0 = quo2[SHIFT +: M0LEN];
    assign q1 = q0 + { { (M0LEN - 1) {1'b0} }, {1'b1} };
    assign r0 = dividend - { { M0LEN {1'b0} }, q0 } * { { M0LEN {1'b0} }, m0 };
    assign r1 = { 1'b0, r0 } - { 1'b0, m0 };

    assign quotient = r1[M0LEN] ? q0 : q1;
    assign remainder = r1[M0LEN] ? r0 : r1[M0LEN-1:0];

endmodule