data/full_repos/permissive/474294847/rtl-src/arithmetic-logic/max-compare.v
data/verilator_xmls/44ce32bf-e913-4fb3-b3dd-bf4ebe7cfea7.xml
module max_compare (compare_a, compare_b, max_val);


    parameter WIDTH = 8;


    input signed [WIDTH-1:0] compare_a, compare_b;
    output signed [WIDTH-1:0] max_val;

assign max_val = (compare_a > compare_b) ? (compare_a) : (compare_b);

endmodule
module max_compare (compare_a, compare_b, max_val);



    parameter WIDTH = 8;


    input signed [WIDTH-1:0] compare_a, compare_b;
    output signed [WIDTH-1:0] max_val;

assign max_val = (compare_a > compare_b) ? (compare_a) : (compare_b);

endmodule