data/full_repos/permissive/445455582/single/tb/alu_tb.v
1: b'%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:23: Cannot find include file: RiSC16_alu.v\n`include "RiSC16_alu.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:31: Define or directive not defined: \'`ALU_FUNCT_LEN\'\n    reg [`ALU_FUNCT_LEN - 1:0] funct;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:49: Unsupported or unknown PLI call: $monitor\n        $monitor("%g : src1 %h O src2 %h (%h funct) => ( %h state, %h result)", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("alu_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, alu_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/alu_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10     src1    <= 16\'h1111;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:56: Define or directive not defined: \'`ALU_ADD\'\n                funct   <= `ALU_ADD;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                funct   <= `ALU_ADD;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/alu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10     src1    <= 16\'h2222;\n        ^\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:60: Define or directive not defined: \'`ALU_SUB\'\n                funct   <= `ALU_SUB;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/alu_tb.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                funct   <= `ALU_SUB;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/alu_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10     $finish;\n        ^\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module alu_tb;


    reg [15:0] src1;
    reg [15:0] src2;
    reg [`ALU_FUNCT_LEN - 1:0] funct;

    wire [15:0] result;
    wire state;


    RiSC16_alu #(      
        .WORD_LENGTH(16)
    ) alu (
        .src1(src1), 
        .src2(src2), 
        .result(result), 
        .state(state), 
        .funct(funct)
    );

    initial begin
        
        $monitor("%g : src1 %h O src2 %h (%h funct) => ( %h state, %h result)", 
            $time, src1, src2, funct, state, result );
        $dumpfile("alu_tb.vcd");
        $dumpvars(0, alu_tb);

        #10     src1    <= 16'h1111;
                src2    <= 16'heaaa;
                funct   <= `ALU_ADD;

        #10     src1    <= 16'h2222;
                src2    <= 16'h2222;
                funct   <= `ALU_SUB;


        #10     $finish;

    end

endmodule
module alu_tb;



    reg [15:0] src1;
    reg [15:0] src2;
    reg [`ALU_FUNCT_LEN - 1:0] funct;

    wire [15:0] result;
    wire state;


    RiSC16_alu #(      
        .WORD_LENGTH(16)
    ) alu (
        .src1(src1), 
        .src2(src2), 
        .result(result), 
        .state(state), 
        .funct(funct)
    );

    initial begin
        
        $monitor("%g : src1 %h O src2 %h (%h funct) => ( %h state, %h result)", 
            $time, src1, src2, funct, state, result );
        $dumpfile("alu_tb.vcd");
        $dumpvars(0, alu_tb);

        #10     src1    <= 16'h1111;
                src2    <= 16'heaaa;
                funct   <= `ALU_ADD;

        #10     src1    <= 16'h2222;
                src2    <= 16'h2222;
                funct   <= `ALU_SUB;


        #10     $finish;

    end

endmodule