data/full_repos/permissive/517127224/fpga/hdl/nes_fb.v
data/verilator_xmls/c6060a79-e6c0-40a3-bed6-7281f8db92ae.xml
module nes_fb(
    input clk_r,
    input ren,
    input [15:0] raddr,
    output reg [5:0] dout,
    
    input clk_w,
    input wen,
    input [15:0] waddr,
    input [5:0] din);
    
(* ram_style = "block" *) reg [5:0] fb [256*240-1:0];

always @(posedge clk_r) begin
    if (ren) begin
        dout <= fb[raddr]; 
    end
end
    
always @(posedge clk_w) begin
    if (wen) begin
        fb[waddr] <= din;
    end
end

endmodule
module nes_fb(
    input clk_r,
    input ren,
    input [15:0] raddr,
    output reg [5:0] dout,
    
    input clk_w,
    input wen,
    input [15:0] waddr,
    input [5:0] din);

    
(* ram_style = "block" *) reg [5:0] fb [256*240-1:0];

always @(posedge clk_r) begin
    if (ren) begin
        dout <= fb[raddr]; 
    end
end
    
always @(posedge clk_w) begin
    if (wen) begin
        fb[waddr] <= din;
    end
end

endmodule