data/full_repos/permissive/435638697/DAM 1.0/DMS.v
1: b'%Error: Cannot find file containing module: 1.0,data/full_repos/permissive/435638697\n        ... Looked in:\n             data/full_repos/permissive/435638697/DAM/1.0,data/full_repos/permissive/435638697\n             data/full_repos/permissive/435638697/DAM/1.0,data/full_repos/permissive/435638697.v\n             data/full_repos/permissive/435638697/DAM/1.0,data/full_repos/permissive/435638697.sv\n             1.0,data/full_repos/permissive/435638697\n             1.0,data/full_repos/permissive/435638697.v\n             1.0,data/full_repos/permissive/435638697.sv\n             obj_dir/1.0,data/full_repos/permissive/435638697\n             obj_dir/1.0,data/full_repos/permissive/435638697.v\n             obj_dir/1.0,data/full_repos/permissive/435638697.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/435638697/DAM\n%Error: Cannot find file containing module: 1.0/DMS.v\n%Error: Exiting due to 3 error(s)\n'
module SAM (str, mode, clk, reset, msg, frame);
	

	input str;
	input mode;
	input clk;
	input reset;
	

	output reg msg;
	output reg frame;
	
	reg [3:0] n = 4'b0000;
	reg [31:0] d = 32'b00;
	reg [31:0] capsN = 32'b0;
	
	reg[2:0] counter0 = 3'b100;
	reg[15:0] counter1 = 16'b0;
	reg[15:0] counter2 = 16'b0;


	always @(posedge clk, negedge reset) begin
     
		if (!reset) begin msg <= 0; frame <=0; end
		else if (mode) begin 				
				if(counter0) 
					begin  
						n[counter0-1] <= str; 
						counter0 <= counter0-1; 
						if(counter0==3'b001) begin
							#1 counter1 <= 2**n;
							#1 counter2 <= 2**n;
						end
					end
				else if(counter1) 
					begin  
						d[counter1-1]<= str; 
						counter1<= counter1-1; 
					end
				else if(counter2) 
					begin  
						capsN[counter2-1]<= str; 
						counter2<= counter2-1; 
					end
					
				
				

			

		end
		
   
	
	end

endmodule
module SAM (str, mode, clk, reset, msg, frame);

	

	input str;
	input mode;
	input clk;
	input reset;
	

	output reg msg;
	output reg frame;
	
	reg [3:0] n = 4'b0000;
	reg [31:0] d = 32'b00;
	reg [31:0] capsN = 32'b0;
	
	reg[2:0] counter0 = 3'b100;
	reg[15:0] counter1 = 16'b0;
	reg[15:0] counter2 = 16'b0;


	always @(posedge clk, negedge reset) begin
     
		if (!reset) begin msg <= 0; frame <=0; end
		else if (mode) begin 				
				if(counter0) 
					begin  
						n[counter0-1] <= str; 
						counter0 <= counter0-1; 
						if(counter0==3'b001) begin
							#1 counter1 <= 2**n;
							#1 counter2 <= 2**n;
						end
					end
				else if(counter1) 
					begin  
						d[counter1-1]<= str; 
						counter1<= counter1-1; 
					end
				else if(counter2) 
					begin  
						capsN[counter2-1]<= str; 
						counter2<= counter2-1; 
					end
					
				
				

			

		end
		
   
	
	end

endmodule