data/full_repos/permissive/523038000/lab1/3.FA_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/523038000/lab1/3.FA_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #10 {a, b, cin} = i;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab1/3.FA_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 $stop;\n  ^\n%Error: data/full_repos/permissive/523038000/lab1/3.FA_tb.v:15: Cannot find file containing module: \'fulladder\'\n fulladder uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/fulladder\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/fulladder.v\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/fulladder.sv\n             fulladder\n             fulladder.v\n             fulladder.sv\n             obj_dir/fulladder\n             obj_dir/fulladder.v\n             obj_dir/fulladder.sv\n%Warning-WIDTH: data/full_repos/permissive/523038000/lab1/3.FA_tb.v:36: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                      : ... In instance test\n   #10 {a, b, cin} = i;\n                   ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg a;
	reg b;
	reg cin;


	wire s;
	wire cout;

	integer i;
	

	fulladder uut (
		.a(a), 
		.b(b), 
		.cin(cin), 
		.s(s), 
		.cout(cout)
	);

	initial begin

		a = 0;
		b = 0;
		cin = 0;
	end

	always @ ( a, b, cin )
		begin
       

		for ( i = 0; i < 8; i = i + 1 )

			#10 {a, b, cin} = i;
			

		#10 $stop;
		end

      
endmodule
module test;



	reg a;
	reg b;
	reg cin;


	wire s;
	wire cout;

	integer i;
	

	fulladder uut (
		.a(a), 
		.b(b), 
		.cin(cin), 
		.s(s), 
		.cout(cout)
	);

	initial begin

		a = 0;
		b = 0;
		cin = 0;
	end

	always @ ( a, b, cin )
		begin
       

		for ( i = 0; i < 8; i = i + 1 )

			#10 {a, b, cin} = i;
			

		#10 $stop;
		end

      
endmodule