data/full_repos/permissive/46981098/sign_extend/sign_extended.v
data/verilator_xmls/7f691fec-3dc1-4c69-bc60-acd1a4f666cf.xml
module sign_extended (out, in);
  output reg [31:0] out;
  input [15:0] in;

  always@ (in)
    begin
      out={16'b0000_0000_0000_0000,in};
    end
endmodule
module sign_extended (out, in);

  output reg [31:0] out;
  input [15:0] in;

  always@ (in)
    begin
      out={16'b0000_0000_0000_0000,in};
    end
endmodule