data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_bus_if_wb32.v
1: b'%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_bus_if_wb32.v:28: Cannot find include file: or1k_defines.v\n`include "or1k_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.sv\n             or1k_defines.v\n             or1k_defines.v.v\n             or1k_defines.v.sv\n             obj_dir/or1k_defines.v\n             obj_dir/or1k_defines.v.v\n             obj_dir/or1k_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module or1k_marocchino_bus_if_wb32
#(
  parameter DRIVER_TYPE         = "D_CACHE",
  parameter BURST_LENGTH        = 8,
  parameter OPTION_DCACHE_SNOOP = "NONE"
)
(

  input             wb_clk,
  input             wb_rst,


  input             cpu_clk,
  input             cpu_rst,

  input             pipeline_flush_i,


  output reg        cpu_err_o,
  output reg        cpu_ack_o,
  output reg [31:0] cpu_dat_o,
  output reg        cpu_burst_last_o,
  input      [31:0] cpu_adr_i,
  input      [31:0] cpu_dat_i,
  input             cpu_req_i,
  input       [3:0] cpu_bsel_i,
  input             cpu_lwa_cmd_i,
  input             cpu_stna_cmd_i,
  input             cpu_swa_cmd_i,
  input             cpu_burst_i,

  output            cpu_atomic_flg_o,

  output     [31:0] cpu_snoop_adr_o,
  output            cpu_snoop_en_o,


  output     [31:0] wbm_adr_o,
  output            wbm_stb_o,
  output            wbm_cyc_o,
  output      [3:0] wbm_sel_o,
  output            wbm_we_o,
  output      [2:0] wbm_cti_o,
  output      [1:0] wbm_bte_o,
  output     [31:0] wbm_dat_o,
  input             wbm_err_i,
  input             wbm_ack_i,
  input      [31:0] wbm_dat_i,
  input             wbm_rty_i,

  input      [31:0] snoop_adr_i,
  input             snoop_en_i
);

  localparam [1:0] BTE_ID = (BURST_LENGTH ==  4) ? 2'b01 :
                            (BURST_LENGTH ==  8) ? 2'b10 :
                            (BURST_LENGTH == 16) ? 2'b11 :
                                                   2'b00;















  wire        lwa_cmd;
  wire        stna_cmd;
  wire        swa_cmd;



  wire        atomic_flg;



  wire        snoop_en_l;
  wire [29:0] snoop_adr_l;



  wire        cpu_snoop_inv_ack;










  reg   cpu_req_r1;
  reg   cpu_req_r2;
  wire  cpu_req_pulse;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      cpu_req_r2 <= 1'b0;
      cpu_req_r1 <= 1'b0;
    end
    else begin
      cpu_req_r2 <= cpu_req_r1;
      cpu_req_r1 <= cpu_req_i;
    end
  end

  assign cpu_req_pulse = cpu_req_r1 ^ cpu_req_r2;





  reg  [31:0] cpu_adr_r1;
  reg  [31:0] cpu_dat_r1;
  reg   [3:0] cpu_bsel_r1;
  reg         cpu_burst_r1;

  always @(posedge wb_clk) begin
    cpu_adr_r1   <= cpu_adr_i;
    cpu_dat_r1   <= cpu_dat_i;
    cpu_bsel_r1  <= cpu_bsel_i;
    cpu_burst_r1 <= cpu_burst_i;
  end







  reg  [2:0] to_wbm_cti_r;
  reg  [1:0] to_wbm_bte_r;


  reg [31:0] to_wbm_adr_r;


  reg   [(BURST_LENGTH-1):0] burst_done_r;
  wire                       burst_proc;
  wire                       burst_keep;
  wire                [31:0] burst_next_adr;


  assign burst_proc = to_wbm_cti_r[1];
  assign burst_keep = burst_proc & (~burst_done_r[0]);


  always @(posedge wb_clk) begin
    if (wb_rst) begin
      to_wbm_cti_r <=  3'd0;
      to_wbm_bte_r <=  2'd0;

      burst_done_r <= {BURST_LENGTH{1'b0}};
    end
    else if (wbm_err_i) begin
      to_wbm_cti_r <=  3'd0;
      to_wbm_bte_r <=  2'd0;

      burst_done_r <= {BURST_LENGTH{1'b0}};
    end
    else if (wbm_ack_i) begin
      to_wbm_cti_r <= (burst_proc ? (burst_done_r[1] ? 3'b111 : 3'b010) : 3'b000);
      to_wbm_bte_r <= burst_keep ? to_wbm_bte_r : 2'd0;

      burst_done_r <= {1'b0, burst_done_r[(BURST_LENGTH-1):1]};
    end
    else if (cpu_req_pulse) begin
      to_wbm_cti_r <= {1'b0, cpu_burst_r1, 1'b0};
      to_wbm_bte_r <= cpu_burst_r1 ? BTE_ID : 2'd0;

      burst_done_r <= {cpu_burst_r1, {(BURST_LENGTH-1){1'b0}}};
    end
  end





  assign burst_next_adr = (BURST_LENGTH == 8) ?
    {to_wbm_adr_r[31:5], to_wbm_adr_r[4:0] + 5'd4} :
    {to_wbm_adr_r[31:4], to_wbm_adr_r[3:0] + 4'd4};

  always @(posedge wb_clk) begin
    if (wbm_ack_i & burst_keep) begin


      to_wbm_adr_r <= burst_next_adr;
    end
    else if (cpu_req_pulse) begin
      to_wbm_adr_r <= cpu_adr_r1;
    end
  end



  assign wbm_adr_o = to_wbm_adr_r;
  assign wbm_cti_o = to_wbm_cti_r;
  assign wbm_bte_o = to_wbm_bte_r;






  reg  to_wbm_stb_r;
  reg  to_wbm_cyc_r;







  localparam [2:0] DBUS_WAITING_CPU_REQ = 3'b001,
                   DBUS_WAITING_WBM_ACQ = 3'b010,
                   DBUS_PENDING_WBM_REQ = 3'b100;

  generate
  if (DRIVER_TYPE == "D_CACHE") begin: dbus_specific


    reg  cpu_lwa_cmd_r1;
    reg  cpu_stna_cmd_r1;
    reg  cpu_swa_cmd_r1;


    always @(posedge wb_clk) begin
      if (wb_rst) begin
        cpu_lwa_cmd_r1  <= 1'b0;
        cpu_stna_cmd_r1 <= 1'b0;
        cpu_swa_cmd_r1  <= 1'b0;
      end
      else begin
        cpu_lwa_cmd_r1  <= cpu_lwa_cmd_i;
        cpu_stna_cmd_r1 <= cpu_stna_cmd_i;
        cpu_swa_cmd_r1  <= cpu_swa_cmd_i;
      end
    end


    assign lwa_cmd  = cpu_lwa_cmd_r1;
    assign stna_cmd = cpu_stna_cmd_r1;
    assign swa_cmd  = cpu_swa_cmd_r1;


    wire snoop_en_any = snoop_en_i | ((~cpu_snoop_inv_ack) & snoop_en_l);


    reg  [2:0] dbus_state_r;

    reg  [3:0] to_wbm_sel_r;
    reg        to_wbm_we_r;
    reg [31:0] to_wbm_dat_r;


    always @(posedge wb_clk) begin
      if (wb_rst) begin
        to_wbm_we_r  <= 1'b0;
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
        dbus_state_r <= DBUS_WAITING_CPU_REQ;
      end
      else begin
        (* parallel_case *)
        case (dbus_state_r)




          DBUS_WAITING_CPU_REQ: begin
            if (cpu_req_pulse) begin
              if (snoop_en_any) begin
                to_wbm_we_r  <= 1'b0;
                to_wbm_stb_r <= 1'b0;
                to_wbm_cyc_r <= 1'b0;
                dbus_state_r <= DBUS_PENDING_WBM_REQ;
              end
              else begin
                to_wbm_we_r  <= stna_cmd;
                to_wbm_stb_r <= (~swa_cmd);
                to_wbm_cyc_r <= (~swa_cmd);
                dbus_state_r <= swa_cmd ? DBUS_PENDING_WBM_REQ : DBUS_WAITING_WBM_ACQ;
              end
            end
          end




          DBUS_WAITING_WBM_ACQ: begin
            if (wbm_err_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= 1'b0;
              to_wbm_cyc_r <= 1'b0;
              dbus_state_r <= DBUS_WAITING_CPU_REQ;
            end
            else if (wbm_ack_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= burst_keep;
              to_wbm_cyc_r <= burst_keep;
              dbus_state_r <= burst_keep ? DBUS_WAITING_WBM_ACQ : DBUS_WAITING_CPU_REQ;
            end
            else if (snoop_en_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= 1'b0;
              to_wbm_cyc_r <= 1'b0;
              dbus_state_r <= DBUS_PENDING_WBM_REQ;
            end
          end





          DBUS_PENDING_WBM_REQ: begin
            if (~snoop_en_any) begin
              to_wbm_we_r  <= stna_cmd | (swa_cmd & atomic_flg);
              to_wbm_stb_r <= 1'b1;
              to_wbm_cyc_r <= 1'b1;
              dbus_state_r <= DBUS_WAITING_WBM_ACQ;
            end
          end


          default:;
        endcase
      end
    end


    always @(posedge wb_clk) begin
      to_wbm_sel_r <= cpu_bsel_r1;
      to_wbm_dat_r <= cpu_dat_r1;
    end


    assign wbm_stb_o = to_wbm_stb_r;
    assign wbm_cyc_o = to_wbm_cyc_r;
    assign wbm_we_o  = to_wbm_we_r;
    assign wbm_sel_o = to_wbm_sel_r;
    assign wbm_dat_o = to_wbm_dat_r;

  end
  else begin : ibus_specific

    always @(posedge wb_clk) begin
      if (wb_rst) begin
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
      end
      else if (wbm_err_i) begin
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
      end
      else if (wbm_ack_i) begin
        to_wbm_stb_r <= burst_keep;
        to_wbm_cyc_r <= burst_keep;
      end
      else if (cpu_req_pulse) begin
        to_wbm_stb_r <= 1'b1;
        to_wbm_cyc_r <= 1'b1;
      end
    end


    assign wbm_stb_o = to_wbm_stb_r;
    assign wbm_cyc_o = to_wbm_cyc_r;
    assign wbm_we_o  =  1'b0;
    assign wbm_sel_o =  4'hf;
    assign wbm_dat_o = 32'd0;

  end
  endgenerate







  reg         wbm_err_r;
  reg         wbm_ack_r;
  reg         wbm_burst_last_r;
  reg  [31:0] wbm_dat_r;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      wbm_err_r        <= 1'b0;
      wbm_ack_r        <= 1'b0;
      wbm_burst_last_r <= 1'b0;
    end
    else if (wbm_cyc_o & (wbm_err_i | wbm_ack_i)) begin
      wbm_err_r        <= wbm_err_i;
      wbm_ack_r        <= wbm_ack_i;
      wbm_burst_last_r <= (burst_proc & burst_done_r[0]);
    end
    else begin
      wbm_err_r        <= 1'b0;
      wbm_ack_r        <= 1'b0;
      wbm_burst_last_r <= 1'b0;
    end
  end

  always @(posedge wb_clk) begin
    wbm_dat_r <= wbm_dat_i;
  end


  reg   wbm2cpu_toggle_r;

  always @(posedge wb_clk) begin
    if (wb_rst)
      wbm2cpu_toggle_r <= 1'b0;
    else if (wbm_cyc_o & (wbm_err_i | wbm_ack_i))
      wbm2cpu_toggle_r <= ~wbm2cpu_toggle_r;
  end







  reg   wbm2cpu_rdy_r1;
  wire  wbm2cpu_rdy_pulse = wbm2cpu_rdy_r1 ^ wbm2cpu_toggle_r;

  always @(posedge cpu_clk) begin
    if (cpu_rst)
      wbm2cpu_rdy_r1 <= 1'b0;
    else
      wbm2cpu_rdy_r1 <= wbm2cpu_toggle_r;
  end


  always @(posedge cpu_clk) begin
    if (cpu_rst) begin
      cpu_err_o        <= 1'b0;
      cpu_ack_o        <= 1'b0;
      cpu_burst_last_o <= 1'b0;
    end
    else if (wbm2cpu_rdy_pulse) begin
      cpu_err_o        <= wbm_err_r;
      cpu_ack_o        <= wbm_ack_r;
      cpu_burst_last_o <= wbm_burst_last_r;
    end
    else begin
      cpu_err_o        <= 1'b0;
      cpu_ack_o        <= 1'b0;
      cpu_burst_last_o <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    cpu_dat_o <= wbm_dat_r;
  end







  generate
  if ((DRIVER_TYPE == "D_CACHE") && (OPTION_DCACHE_SNOOP != "NONE")) begin: dbus_multi_core




    wire       snoop_en_f = snoop_en_i & (~wbm_ack_i) & (~wbm_err_i);
    reg        snoop_en_r;
    reg [31:0] snoop_adr_r;






    always @(posedge wb_clk) begin
      if (wb_rst)
        snoop_en_r <= 1'b0;
      else if (snoop_en_f)
        snoop_en_r <= 1'b1;
      else
        snoop_en_r <= (~cpu_snoop_inv_ack) & snoop_en_r;
    end



    always @(posedge wb_clk) begin
      snoop_adr_r <= snoop_adr_i;
    end



    assign snoop_en_l  = snoop_en_r;
    assign snoop_adr_l = snoop_adr_r[31:2];










    reg  snoop_en_toggle_r;

    always @(posedge wb_clk) begin
      if (wb_rst)
        snoop_en_toggle_r <= 1'b0;
      else if (snoop_en_f)
        snoop_en_toggle_r <= ~snoop_en_toggle_r;
    end

    reg  wbm2cpu_snoop_en_r;
    wire wbm2cpu_snoop_en_pulse = wbm2cpu_snoop_en_r ^ snoop_en_toggle_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        wbm2cpu_snoop_en_r <= 1'b0;
      else
        wbm2cpu_snoop_en_r <= snoop_en_toggle_r;
    end

    reg         cpu_snoop_en_r;
    reg  [31:0] cpu_snoop_adr_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        cpu_snoop_en_r <= 1'b0;
      else
        cpu_snoop_en_r <= wbm2cpu_snoop_en_pulse;
    end

    always @(posedge cpu_clk) begin
      cpu_snoop_adr_r <= snoop_adr_r;
    end

    assign cpu_snoop_adr_o = cpu_snoop_adr_r;
    assign cpu_snoop_en_o  = cpu_snoop_en_r;


















    reg  dc_snoop_inv_ack_toggle_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        dc_snoop_inv_ack_toggle_r <= 1'b0;
      else if (cpu_snoop_en_o)
        dc_snoop_inv_ack_toggle_r <= ~dc_snoop_inv_ack_toggle_r;
    end

    reg    cpu_snoop_inv_ack_r1, cpu_snoop_inv_ack_r2;
    assign cpu_snoop_inv_ack = cpu_snoop_inv_ack_r1 ^ cpu_snoop_inv_ack_r2;

    always @(posedge wb_clk) begin
      if (wb_rst) begin
        cpu_snoop_inv_ack_r2 <= 1'b0;
        cpu_snoop_inv_ack_r1 <= 1'b0;
      end
      else begin
        cpu_snoop_inv_ack_r2 <= cpu_snoop_inv_ack_r1;
        cpu_snoop_inv_ack_r1 <= dc_snoop_inv_ack_toggle_r;
      end
    end

  end
  else begin: dbus_single_core

    assign snoop_en_l  =  1'b0;
    assign snoop_adr_l = 30'd0;

    assign cpu_snoop_adr_o = 32'd0;
    assign cpu_snoop_en_o  =  1'b0;

    assign cpu_snoop_inv_ack = 1'b1;

  end
  endgenerate







  generate
  if (DRIVER_TYPE == "D_CACHE") begin: dbus_with_atomics








    reg  pipeline_flush_toggle_r;
    reg  pipeline_flush_state_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst) begin
        pipeline_flush_toggle_r <= 1'b0;
        pipeline_flush_state_r  <= 1'b0;
      end
      else if (pipeline_flush_state_r) begin
        pipeline_flush_toggle_r <= pipeline_flush_toggle_r;
        pipeline_flush_state_r  <= pipeline_flush_i;
      end
      else if (pipeline_flush_i) begin
        pipeline_flush_toggle_r <= ~pipeline_flush_toggle_r;
        pipeline_flush_state_r  <= 1'b1;
      end
    end

    reg  pipeline_flush_r1;
    wire pipeline_flush_pulse = pipeline_flush_toggle_r ^ pipeline_flush_r1;

    always @(posedge wb_clk) begin
      if (wb_rst)
        pipeline_flush_r1 <= 1'b0;
      else
        pipeline_flush_r1 <= pipeline_flush_toggle_r;
    end



    reg  flush_r;

    always @(posedge wb_clk) begin
      if (wb_rst)
        flush_r <= 1'b0;
      else if (wbm_err_r | wbm_ack_r)
        flush_r <= 1'b0;
      else if (pipeline_flush_pulse)
        flush_r <= wbm_cyc_o;
    end



    reg         atomic_flg_r;
    reg  [29:0] atomic_adr_r;



    always @(posedge wb_clk) begin
      if (wb_rst)
        atomic_adr_r <= 30'd0;
      else if (lwa_cmd & wbm_ack_r)
        atomic_adr_r <= cpu_adr_r1[31:2];
    end



    wire deassert_atomic_flg =
      pipeline_flush_pulse | flush_r |
      (stna_cmd   & atomic_flg_r & (atomic_adr_r == cpu_adr_r1[31:2])) |
      (swa_cmd    & atomic_flg_r & (atomic_adr_r != cpu_adr_r1[31:2])) |
      (snoop_en_l & atomic_flg_r & (atomic_adr_r == snoop_adr_l))      |
      (swa_cmd & (wbm_err_r | wbm_ack_r));

    always @(posedge wb_clk) begin
      if (wb_rst)
        atomic_flg_r <= 1'b0;
      else if (deassert_atomic_flg)
        atomic_flg_r <= 1'b0;
      else if (lwa_cmd & wbm_ack_r)
        atomic_flg_r <= ~atomic_flg_r;
    end

    assign atomic_flg = atomic_flg_r;



    reg to_cpu_atomic_flg_r1;

    always @(posedge cpu_clk) begin
      if (wbm2cpu_rdy_pulse)
        to_cpu_atomic_flg_r1 <= atomic_flg_r;
    end


    assign cpu_atomic_flg_o = to_cpu_atomic_flg_r1;

  end
  else begin : ibus_without_atomics


    assign lwa_cmd          =  1'b0;
    assign stna_cmd         =  1'b0;
    assign swa_cmd          =  1'b0;


    assign atomic_flg       =  1'b0;

    assign cpu_atomic_flg_o =  1'b0;

  end
  endgenerate

endmodule
module or1k_marocchino_bus_if_wb32
#(
  parameter DRIVER_TYPE         = "D_CACHE",
  parameter BURST_LENGTH        = 8,
  parameter OPTION_DCACHE_SNOOP = "NONE"
)
(

  input             wb_clk,
  input             wb_rst,


  input             cpu_clk,
  input             cpu_rst,

  input             pipeline_flush_i,


  output reg        cpu_err_o,
  output reg        cpu_ack_o,
  output reg [31:0] cpu_dat_o,
  output reg        cpu_burst_last_o,
  input      [31:0] cpu_adr_i,
  input      [31:0] cpu_dat_i,
  input             cpu_req_i,
  input       [3:0] cpu_bsel_i,
  input             cpu_lwa_cmd_i,
  input             cpu_stna_cmd_i,
  input             cpu_swa_cmd_i,
  input             cpu_burst_i,

  output            cpu_atomic_flg_o,

  output     [31:0] cpu_snoop_adr_o,
  output            cpu_snoop_en_o,


  output     [31:0] wbm_adr_o,
  output            wbm_stb_o,
  output            wbm_cyc_o,
  output      [3:0] wbm_sel_o,
  output            wbm_we_o,
  output      [2:0] wbm_cti_o,
  output      [1:0] wbm_bte_o,
  output     [31:0] wbm_dat_o,
  input             wbm_err_i,
  input             wbm_ack_i,
  input      [31:0] wbm_dat_i,
  input             wbm_rty_i,

  input      [31:0] snoop_adr_i,
  input             snoop_en_i
);


  localparam [1:0] BTE_ID = (BURST_LENGTH ==  4) ? 2'b01 :
                            (BURST_LENGTH ==  8) ? 2'b10 :
                            (BURST_LENGTH == 16) ? 2'b11 :
                                                   2'b00;















  wire        lwa_cmd;
  wire        stna_cmd;
  wire        swa_cmd;



  wire        atomic_flg;



  wire        snoop_en_l;
  wire [29:0] snoop_adr_l;



  wire        cpu_snoop_inv_ack;










  reg   cpu_req_r1;
  reg   cpu_req_r2;
  wire  cpu_req_pulse;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      cpu_req_r2 <= 1'b0;
      cpu_req_r1 <= 1'b0;
    end
    else begin
      cpu_req_r2 <= cpu_req_r1;
      cpu_req_r1 <= cpu_req_i;
    end
  end

  assign cpu_req_pulse = cpu_req_r1 ^ cpu_req_r2;





  reg  [31:0] cpu_adr_r1;
  reg  [31:0] cpu_dat_r1;
  reg   [3:0] cpu_bsel_r1;
  reg         cpu_burst_r1;

  always @(posedge wb_clk) begin
    cpu_adr_r1   <= cpu_adr_i;
    cpu_dat_r1   <= cpu_dat_i;
    cpu_bsel_r1  <= cpu_bsel_i;
    cpu_burst_r1 <= cpu_burst_i;
  end







  reg  [2:0] to_wbm_cti_r;
  reg  [1:0] to_wbm_bte_r;


  reg [31:0] to_wbm_adr_r;


  reg   [(BURST_LENGTH-1):0] burst_done_r;
  wire                       burst_proc;
  wire                       burst_keep;
  wire                [31:0] burst_next_adr;


  assign burst_proc = to_wbm_cti_r[1];
  assign burst_keep = burst_proc & (~burst_done_r[0]);


  always @(posedge wb_clk) begin
    if (wb_rst) begin
      to_wbm_cti_r <=  3'd0;
      to_wbm_bte_r <=  2'd0;

      burst_done_r <= {BURST_LENGTH{1'b0}};
    end
    else if (wbm_err_i) begin
      to_wbm_cti_r <=  3'd0;
      to_wbm_bte_r <=  2'd0;

      burst_done_r <= {BURST_LENGTH{1'b0}};
    end
    else if (wbm_ack_i) begin
      to_wbm_cti_r <= (burst_proc ? (burst_done_r[1] ? 3'b111 : 3'b010) : 3'b000);
      to_wbm_bte_r <= burst_keep ? to_wbm_bte_r : 2'd0;

      burst_done_r <= {1'b0, burst_done_r[(BURST_LENGTH-1):1]};
    end
    else if (cpu_req_pulse) begin
      to_wbm_cti_r <= {1'b0, cpu_burst_r1, 1'b0};
      to_wbm_bte_r <= cpu_burst_r1 ? BTE_ID : 2'd0;

      burst_done_r <= {cpu_burst_r1, {(BURST_LENGTH-1){1'b0}}};
    end
  end





  assign burst_next_adr = (BURST_LENGTH == 8) ?
    {to_wbm_adr_r[31:5], to_wbm_adr_r[4:0] + 5'd4} :
    {to_wbm_adr_r[31:4], to_wbm_adr_r[3:0] + 4'd4};

  always @(posedge wb_clk) begin
    if (wbm_ack_i & burst_keep) begin


      to_wbm_adr_r <= burst_next_adr;
    end
    else if (cpu_req_pulse) begin
      to_wbm_adr_r <= cpu_adr_r1;
    end
  end



  assign wbm_adr_o = to_wbm_adr_r;
  assign wbm_cti_o = to_wbm_cti_r;
  assign wbm_bte_o = to_wbm_bte_r;






  reg  to_wbm_stb_r;
  reg  to_wbm_cyc_r;







  localparam [2:0] DBUS_WAITING_CPU_REQ = 3'b001,
                   DBUS_WAITING_WBM_ACQ = 3'b010,
                   DBUS_PENDING_WBM_REQ = 3'b100;

  generate
  if (DRIVER_TYPE == "D_CACHE") begin: dbus_specific


    reg  cpu_lwa_cmd_r1;
    reg  cpu_stna_cmd_r1;
    reg  cpu_swa_cmd_r1;


    always @(posedge wb_clk) begin
      if (wb_rst) begin
        cpu_lwa_cmd_r1  <= 1'b0;
        cpu_stna_cmd_r1 <= 1'b0;
        cpu_swa_cmd_r1  <= 1'b0;
      end
      else begin
        cpu_lwa_cmd_r1  <= cpu_lwa_cmd_i;
        cpu_stna_cmd_r1 <= cpu_stna_cmd_i;
        cpu_swa_cmd_r1  <= cpu_swa_cmd_i;
      end
    end


    assign lwa_cmd  = cpu_lwa_cmd_r1;
    assign stna_cmd = cpu_stna_cmd_r1;
    assign swa_cmd  = cpu_swa_cmd_r1;


    wire snoop_en_any = snoop_en_i | ((~cpu_snoop_inv_ack) & snoop_en_l);


    reg  [2:0] dbus_state_r;

    reg  [3:0] to_wbm_sel_r;
    reg        to_wbm_we_r;
    reg [31:0] to_wbm_dat_r;


    always @(posedge wb_clk) begin
      if (wb_rst) begin
        to_wbm_we_r  <= 1'b0;
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
        dbus_state_r <= DBUS_WAITING_CPU_REQ;
      end
      else begin
        (* parallel_case *)
        case (dbus_state_r)




          DBUS_WAITING_CPU_REQ: begin
            if (cpu_req_pulse) begin
              if (snoop_en_any) begin
                to_wbm_we_r  <= 1'b0;
                to_wbm_stb_r <= 1'b0;
                to_wbm_cyc_r <= 1'b0;
                dbus_state_r <= DBUS_PENDING_WBM_REQ;
              end
              else begin
                to_wbm_we_r  <= stna_cmd;
                to_wbm_stb_r <= (~swa_cmd);
                to_wbm_cyc_r <= (~swa_cmd);
                dbus_state_r <= swa_cmd ? DBUS_PENDING_WBM_REQ : DBUS_WAITING_WBM_ACQ;
              end
            end
          end




          DBUS_WAITING_WBM_ACQ: begin
            if (wbm_err_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= 1'b0;
              to_wbm_cyc_r <= 1'b0;
              dbus_state_r <= DBUS_WAITING_CPU_REQ;
            end
            else if (wbm_ack_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= burst_keep;
              to_wbm_cyc_r <= burst_keep;
              dbus_state_r <= burst_keep ? DBUS_WAITING_WBM_ACQ : DBUS_WAITING_CPU_REQ;
            end
            else if (snoop_en_i) begin
              to_wbm_we_r  <= 1'b0;
              to_wbm_stb_r <= 1'b0;
              to_wbm_cyc_r <= 1'b0;
              dbus_state_r <= DBUS_PENDING_WBM_REQ;
            end
          end





          DBUS_PENDING_WBM_REQ: begin
            if (~snoop_en_any) begin
              to_wbm_we_r  <= stna_cmd | (swa_cmd & atomic_flg);
              to_wbm_stb_r <= 1'b1;
              to_wbm_cyc_r <= 1'b1;
              dbus_state_r <= DBUS_WAITING_WBM_ACQ;
            end
          end


          default:;
        endcase
      end
    end


    always @(posedge wb_clk) begin
      to_wbm_sel_r <= cpu_bsel_r1;
      to_wbm_dat_r <= cpu_dat_r1;
    end


    assign wbm_stb_o = to_wbm_stb_r;
    assign wbm_cyc_o = to_wbm_cyc_r;
    assign wbm_we_o  = to_wbm_we_r;
    assign wbm_sel_o = to_wbm_sel_r;
    assign wbm_dat_o = to_wbm_dat_r;

  end
  else begin : ibus_specific

    always @(posedge wb_clk) begin
      if (wb_rst) begin
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
      end
      else if (wbm_err_i) begin
        to_wbm_stb_r <= 1'b0;
        to_wbm_cyc_r <= 1'b0;
      end
      else if (wbm_ack_i) begin
        to_wbm_stb_r <= burst_keep;
        to_wbm_cyc_r <= burst_keep;
      end
      else if (cpu_req_pulse) begin
        to_wbm_stb_r <= 1'b1;
        to_wbm_cyc_r <= 1'b1;
      end
    end


    assign wbm_stb_o = to_wbm_stb_r;
    assign wbm_cyc_o = to_wbm_cyc_r;
    assign wbm_we_o  =  1'b0;
    assign wbm_sel_o =  4'hf;
    assign wbm_dat_o = 32'd0;

  end
  endgenerate







  reg         wbm_err_r;
  reg         wbm_ack_r;
  reg         wbm_burst_last_r;
  reg  [31:0] wbm_dat_r;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      wbm_err_r        <= 1'b0;
      wbm_ack_r        <= 1'b0;
      wbm_burst_last_r <= 1'b0;
    end
    else if (wbm_cyc_o & (wbm_err_i | wbm_ack_i)) begin
      wbm_err_r        <= wbm_err_i;
      wbm_ack_r        <= wbm_ack_i;
      wbm_burst_last_r <= (burst_proc & burst_done_r[0]);
    end
    else begin
      wbm_err_r        <= 1'b0;
      wbm_ack_r        <= 1'b0;
      wbm_burst_last_r <= 1'b0;
    end
  end

  always @(posedge wb_clk) begin
    wbm_dat_r <= wbm_dat_i;
  end


  reg   wbm2cpu_toggle_r;

  always @(posedge wb_clk) begin
    if (wb_rst)
      wbm2cpu_toggle_r <= 1'b0;
    else if (wbm_cyc_o & (wbm_err_i | wbm_ack_i))
      wbm2cpu_toggle_r <= ~wbm2cpu_toggle_r;
  end







  reg   wbm2cpu_rdy_r1;
  wire  wbm2cpu_rdy_pulse = wbm2cpu_rdy_r1 ^ wbm2cpu_toggle_r;

  always @(posedge cpu_clk) begin
    if (cpu_rst)
      wbm2cpu_rdy_r1 <= 1'b0;
    else
      wbm2cpu_rdy_r1 <= wbm2cpu_toggle_r;
  end


  always @(posedge cpu_clk) begin
    if (cpu_rst) begin
      cpu_err_o        <= 1'b0;
      cpu_ack_o        <= 1'b0;
      cpu_burst_last_o <= 1'b0;
    end
    else if (wbm2cpu_rdy_pulse) begin
      cpu_err_o        <= wbm_err_r;
      cpu_ack_o        <= wbm_ack_r;
      cpu_burst_last_o <= wbm_burst_last_r;
    end
    else begin
      cpu_err_o        <= 1'b0;
      cpu_ack_o        <= 1'b0;
      cpu_burst_last_o <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    cpu_dat_o <= wbm_dat_r;
  end







  generate
  if ((DRIVER_TYPE == "D_CACHE") && (OPTION_DCACHE_SNOOP != "NONE")) begin: dbus_multi_core




    wire       snoop_en_f = snoop_en_i & (~wbm_ack_i) & (~wbm_err_i);
    reg        snoop_en_r;
    reg [31:0] snoop_adr_r;






    always @(posedge wb_clk) begin
      if (wb_rst)
        snoop_en_r <= 1'b0;
      else if (snoop_en_f)
        snoop_en_r <= 1'b1;
      else
        snoop_en_r <= (~cpu_snoop_inv_ack) & snoop_en_r;
    end



    always @(posedge wb_clk) begin
      snoop_adr_r <= snoop_adr_i;
    end



    assign snoop_en_l  = snoop_en_r;
    assign snoop_adr_l = snoop_adr_r[31:2];










    reg  snoop_en_toggle_r;

    always @(posedge wb_clk) begin
      if (wb_rst)
        snoop_en_toggle_r <= 1'b0;
      else if (snoop_en_f)
        snoop_en_toggle_r <= ~snoop_en_toggle_r;
    end

    reg  wbm2cpu_snoop_en_r;
    wire wbm2cpu_snoop_en_pulse = wbm2cpu_snoop_en_r ^ snoop_en_toggle_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        wbm2cpu_snoop_en_r <= 1'b0;
      else
        wbm2cpu_snoop_en_r <= snoop_en_toggle_r;
    end

    reg         cpu_snoop_en_r;
    reg  [31:0] cpu_snoop_adr_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        cpu_snoop_en_r <= 1'b0;
      else
        cpu_snoop_en_r <= wbm2cpu_snoop_en_pulse;
    end

    always @(posedge cpu_clk) begin
      cpu_snoop_adr_r <= snoop_adr_r;
    end

    assign cpu_snoop_adr_o = cpu_snoop_adr_r;
    assign cpu_snoop_en_o  = cpu_snoop_en_r;


















    reg  dc_snoop_inv_ack_toggle_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst)
        dc_snoop_inv_ack_toggle_r <= 1'b0;
      else if (cpu_snoop_en_o)
        dc_snoop_inv_ack_toggle_r <= ~dc_snoop_inv_ack_toggle_r;
    end

    reg    cpu_snoop_inv_ack_r1, cpu_snoop_inv_ack_r2;
    assign cpu_snoop_inv_ack = cpu_snoop_inv_ack_r1 ^ cpu_snoop_inv_ack_r2;

    always @(posedge wb_clk) begin
      if (wb_rst) begin
        cpu_snoop_inv_ack_r2 <= 1'b0;
        cpu_snoop_inv_ack_r1 <= 1'b0;
      end
      else begin
        cpu_snoop_inv_ack_r2 <= cpu_snoop_inv_ack_r1;
        cpu_snoop_inv_ack_r1 <= dc_snoop_inv_ack_toggle_r;
      end
    end

  end
  else begin: dbus_single_core

    assign snoop_en_l  =  1'b0;
    assign snoop_adr_l = 30'd0;

    assign cpu_snoop_adr_o = 32'd0;
    assign cpu_snoop_en_o  =  1'b0;

    assign cpu_snoop_inv_ack = 1'b1;

  end
  endgenerate







  generate
  if (DRIVER_TYPE == "D_CACHE") begin: dbus_with_atomics








    reg  pipeline_flush_toggle_r;
    reg  pipeline_flush_state_r;

    always @(posedge cpu_clk) begin
      if (cpu_rst) begin
        pipeline_flush_toggle_r <= 1'b0;
        pipeline_flush_state_r  <= 1'b0;
      end
      else if (pipeline_flush_state_r) begin
        pipeline_flush_toggle_r <= pipeline_flush_toggle_r;
        pipeline_flush_state_r  <= pipeline_flush_i;
      end
      else if (pipeline_flush_i) begin
        pipeline_flush_toggle_r <= ~pipeline_flush_toggle_r;
        pipeline_flush_state_r  <= 1'b1;
      end
    end

    reg  pipeline_flush_r1;
    wire pipeline_flush_pulse = pipeline_flush_toggle_r ^ pipeline_flush_r1;

    always @(posedge wb_clk) begin
      if (wb_rst)
        pipeline_flush_r1 <= 1'b0;
      else
        pipeline_flush_r1 <= pipeline_flush_toggle_r;
    end



    reg  flush_r;

    always @(posedge wb_clk) begin
      if (wb_rst)
        flush_r <= 1'b0;
      else if (wbm_err_r | wbm_ack_r)
        flush_r <= 1'b0;
      else if (pipeline_flush_pulse)
        flush_r <= wbm_cyc_o;
    end



    reg         atomic_flg_r;
    reg  [29:0] atomic_adr_r;



    always @(posedge wb_clk) begin
      if (wb_rst)
        atomic_adr_r <= 30'd0;
      else if (lwa_cmd & wbm_ack_r)
        atomic_adr_r <= cpu_adr_r1[31:2];
    end



    wire deassert_atomic_flg =
      pipeline_flush_pulse | flush_r |
      (stna_cmd   & atomic_flg_r & (atomic_adr_r == cpu_adr_r1[31:2])) |
      (swa_cmd    & atomic_flg_r & (atomic_adr_r != cpu_adr_r1[31:2])) |
      (snoop_en_l & atomic_flg_r & (atomic_adr_r == snoop_adr_l))      |
      (swa_cmd & (wbm_err_r | wbm_ack_r));

    always @(posedge wb_clk) begin
      if (wb_rst)
        atomic_flg_r <= 1'b0;
      else if (deassert_atomic_flg)
        atomic_flg_r <= 1'b0;
      else if (lwa_cmd & wbm_ack_r)
        atomic_flg_r <= ~atomic_flg_r;
    end

    assign atomic_flg = atomic_flg_r;



    reg to_cpu_atomic_flg_r1;

    always @(posedge cpu_clk) begin
      if (wbm2cpu_rdy_pulse)
        to_cpu_atomic_flg_r1 <= atomic_flg_r;
    end


    assign cpu_atomic_flg_o = to_cpu_atomic_flg_r1;

  end
  else begin : ibus_without_atomics


    assign lwa_cmd          =  1'b0;
    assign stna_cmd         =  1'b0;
    assign swa_cmd          =  1'b0;


    assign atomic_flg       =  1'b0;

    assign cpu_atomic_flg_o =  1'b0;

  end
  endgenerate

endmodule