data/full_repos/permissive/500345502/verilog/rtl/wrapped_PrimitiveCalculator/PrimitiveCalculator_/src/RotaryEncoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500345502/verilog/rtl/wrapped_PrimitiveCalculator/PrimitiveCalculator_/src/RotaryEncoder.v:28: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'ADD_SUB\' generates 1 bits.\n                                                                                                                                        : ... In instance RotaryEncoder\n                4\'b0111 : out <= out + ADD_SUB;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500345502/verilog/rtl/wrapped_PrimitiveCalculator/PrimitiveCalculator_/src/RotaryEncoder.v:31: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'ADD_SUB\' generates 1 bits.\n                                                                                                                                        : ... In instance RotaryEncoder\n                4\'b1101 : out <= out - ADD_SUB;\n                                     ^\n%Error: Exiting due to 2 warning(s)\n'
module RotaryEncoder #(
    parameter REG_LEN = 8,
    parameter ADD_SUB = 1'b1
) (
    input wire clk,
    input wire rst,
    input wire a,
    input wire b,
    output reg [REG_LEN-1:0] out
);

    reg a_d1, b_d1;

    always @(posedge clk) begin
        if (rst) begin 
            out <= 0;
            a_d1 <= 1'b0;
            b_d1 <= 1'b0;
        end else begin 
            a_d1 <= a;
            b_d1 <= b;

            case ({a, a_d1, b, b_d1})
                4'b1000, 
                4'b0111 : out <= out + ADD_SUB;
                
                4'b0010,
                4'b1101 : out <= out - ADD_SUB;

                default : out <= out; 
            endcase
        end
    end

endmodule
module RotaryEncoder #(
    parameter REG_LEN = 8,
    parameter ADD_SUB = 1'b1
) (
    input wire clk,
    input wire rst,
    input wire a,
    input wire b,
    output reg [REG_LEN-1:0] out
);


    reg a_d1, b_d1;

    always @(posedge clk) begin
        if (rst) begin 
            out <= 0;
            a_d1 <= 1'b0;
            b_d1 <= 1'b0;
        end else begin 
            a_d1 <= a;
            b_d1 <= b;

            case ({a, a_d1, b, b_d1})
                4'b1000, 
                4'b0111 : out <= out + ADD_SUB;
                
                4'b0010,
                4'b1101 : out <= out - ADD_SUB;

                default : out <= out; 
            endcase
        end
    end

endmodule