data/full_repos/permissive/484316383/rtl/common/cga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cga.v:139: Operator EQ expects 20 bits on the LHS, but LHS\'s VARREF \'bus_a\' generates 16 bits.\n                                                                         : ... In instance cga\n    assign status_cs = (bus_a == IO_BASE_ADDR + 20\'hA) & ~bus_aen;\n                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cga.v:139: Operator ADD expects 20 bits on the LHS, but LHS\'s VARREF \'IO_BASE_ADDR\' generates 16 bits.\n                                                                         : ... In instance cga\n    assign status_cs = (bus_a == IO_BASE_ADDR + 20\'hA) & ~bus_aen;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cga.v:141: Operator EQ expects 20 bits on the LHS, but LHS\'s VARREF \'bus_a\' generates 16 bits.\n                                                                         : ... In instance cga\n    assign colorsel_cs = (bus_a == IO_BASE_ADDR + 20\'h9) & ~bus_aen;  \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cga.v:141: Operator ADD expects 20 bits on the LHS, but LHS\'s VARREF \'IO_BASE_ADDR\' generates 16 bits.\n                                                                         : ... In instance cga\n    assign colorsel_cs = (bus_a == IO_BASE_ADDR + 20\'h9) & ~bus_aen;  \n                                                ^\n%Error: data/full_repos/permissive/484316383/rtl/common/cga.v:249: Cannot find file containing module: \'crtc6845\'\n    crtc6845 crtc (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/crtc6845\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/crtc6845.v\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/crtc6845.sv\n             crtc6845\n             crtc6845.v\n             crtc6845.sv\n             obj_dir/crtc6845\n             obj_dir/crtc6845.v\n             obj_dir/crtc6845.sv\n%Error: data/full_repos/permissive/484316383/rtl/common/cga.v:297: Cannot find file containing module: \'cga_sequencer\'\n    cga_sequencer sequencer (\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484316383/rtl/common/cga.v:314: Cannot find file containing module: \'cga_pixel\'\n    cga_pixel pixel (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/484316383/rtl/common/cga.v:351: Cannot find file containing module: \'cga_scandoubler\'\n    cga_scandoubler scandoubler (\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module cga(

    input clk,


    input[15:0] bus_a,
    input bus_ior_l,
    input bus_iow_l,
    input bus_memr_l,
    input bus_memw_l,
	 input word,
    input[15:0] bus_d,
    output[7:0] bus_out,
    output bus_dir,
    input bus_aen,
    output bus_rdy,


    output ram_we_l,
    output[18:0] ram_a,
    input[7:0] ram_d,
	 

    output hsync,
    output dbl_hsync,
    output vsync,

    output hdisp,
    output vdisp,

    output[3:0] video,
    output[3:0] dbl_video,
    output[6:0] comp_video,

    input thin_font
    );

    parameter MDA_70HZ = 0;
    parameter BLINK_MAX = 0;


    parameter USE_BUS_WAIT = 0;
    parameter NO_DISPLAY_DISABLE = 1;

    parameter IO_BASE_ADDR = 16'h3d0;


    wire crtc_cs;
    wire status_cs;
    wire colorsel_cs;
    wire control_cs;


    reg[7:0] bus_int_out;
    wire[7:0] bus_out_crtc;
    wire[7:0] bus_out_mem;
    wire[7:0] cga_status_reg;

	 reg[7:0] cga_control_reg = 8'b0010_1010;
    reg[7:0] cga_color_reg = 8'b0000_0000;
    wire hres_mode;
    wire grph_mode;
    wire bw_mode;
    wire mode_640;
    wire tandy_16_mode;
    wire video_enabled; 
    wire blink_enabled;

    wire hsync_int;
    wire vsync_l;
    wire cursor;

    wire display_enable;


    wire hclk;
    wire lclk;

    wire[13:0] crtc_addr;
    wire[4:0] row_addr;
    wire line_reset;
    wire pixel_addr13;
    wire pixel_addr14;

    wire charrom_read;
    wire disp_pipeline;
    wire isa_op_enable;
    wire vram_read_char;
    wire vram_read_att;
    wire vram_read;
    wire vram_read_a0;
    wire[4:0] clkdiv;
    wire crtc_clk;
    wire[7:0] ram_1_d;

    reg[23:0] blink_counter = 24'd0;
    reg blink = 0;

    reg bus_memw_synced_l;
    reg bus_memr_synced_l;
    reg bus_ior_synced_l;
    reg bus_iow_synced_l;




	 
	 assign ram_a = {4'b0001, pixel_addr14, pixel_addr13, crtc_addr[11:0],
                    vram_read_a0};
						  
	 assign ram_1_d = ram_d;

	 assign ram_we_l = vram_read;
	 


    always @ (posedge clk)
    begin


        bus_ior_synced_l <= bus_ior_l;
        bus_iow_synced_l <= bus_iow_l;
    end


    assign vsync = ~vsync_l;


    assign crtc_cs = (bus_a[15:3] == IO_BASE_ADDR[15:3]) & ~bus_aen;
    assign status_cs = (bus_a == IO_BASE_ADDR + 20'hA) & ~bus_aen;
	 assign control_cs = (bus_a == IO_BASE_ADDR + 16'h8) & ~bus_aen;
    assign colorsel_cs = (bus_a == IO_BASE_ADDR + 20'h9) & ~bus_aen;	 



	 

    always @ (*)
    begin


        if (status_cs & ~bus_ior_l) begin
            bus_int_out <= cga_status_reg;
        end else if (crtc_cs & ~bus_ior_l & (bus_a[0] == 1)) begin
            bus_int_out <= bus_out_crtc;




        end else begin
            bus_int_out <= 8'h00;
        end
    end


    assign bus_dir = (crtc_cs | status_cs) & ~bus_ior_l;


    assign bus_out = bus_int_out;










    assign cga_status_reg = {4'b1111, vsync_l, 2'b10, ~display_enable};



    assign hres_mode = cga_control_reg[0];
    assign grph_mode = cga_control_reg[1];
    assign bw_mode = cga_control_reg[2];




        assign video_enabled = cga_control_reg[3];


    assign mode_640 = cga_control_reg[4];
    assign blink_enabled = cga_control_reg[5];


    assign tandy_16_mode = cga_control_reg[6];

    assign hsync = hsync_int;


    always @ (posedge clk)
    begin
        if (~bus_iow_synced_l) begin
            if (control_cs) begin
                cga_control_reg <= bus_d[7:0];
            end else if (colorsel_cs) begin
                cga_color_reg <= bus_d[7:0];
            end
        end
    end


    crtc6845 crtc (
        .clk(clk),
        .divclk(crtc_clk),
        .cs(crtc_cs),
        .a0(bus_a[0]),
		.word(word),
        .write(~bus_iow_synced_l),
        .read(~bus_ior_synced_l),
        .bus(bus_d),
        .bus_out(bus_out_crtc),
        .lock(1'b0),
        .hsync(hsync_int),
        .vsync(vsync_l),


        .hdisp(hdisp),
        .vdisp(vdisp),

        .display_enable(display_enable),
        .cursor(cursor),
        .mem_addr(crtc_addr),
        .row_addr(row_addr),
        .line_reset(line_reset)
    );


    defparam crtc.H_TOTAL = 8'd56;
    defparam crtc.H_DISP = 8'd40;
    defparam crtc.H_SYNCPOS = 8'd45;
    defparam crtc.H_SYNCWIDTH = 4'd10;
    defparam crtc.V_TOTAL = 7'd31;
    defparam crtc.V_TOTALADJ = 5'd6;
    defparam crtc.V_DISP = 7'd25;
    defparam crtc.V_SYNCPOS = 7'd28;
    defparam crtc.V_MAXSCAN = 5'd7;
    defparam crtc.C_START = 7'd6;
    defparam crtc.C_END = 5'd7;



    assign pixel_addr13 = grph_mode ? row_addr[0] : crtc_addr[12];


    assign pixel_addr14 = grph_mode ? row_addr[1] : 1'b0;
	 



    cga_sequencer sequencer (
        .clk(clk),
        .clk_seq(clkdiv),
        .vram_read(vram_read),
        .vram_read_a0(vram_read_a0),
        .vram_read_char(vram_read_char),
        .vram_read_att(vram_read_att),
        .hres_mode(hres_mode),
        .crtc_clk(crtc_clk),
        .charrom_read(charrom_read),
        .disp_pipeline(disp_pipeline),
        .isa_op_enable(isa_op_enable),
        .hclk(hclk),
        .lclk(lclk)
    );


    cga_pixel pixel (
        .clk(clk),
        .clk_seq(clkdiv),
        .hres_mode(hres_mode),
        .grph_mode(grph_mode),
        .bw_mode(bw_mode),
        .mode_640(mode_640),
        .tandy_16_mode(tandy_16_mode),
        .thin_font(thin_font),
        .vram_data(ram_1_d),
        .vram_read_char(vram_read_char),
        .vram_read_att(vram_read_att),
        .disp_pipeline(disp_pipeline),
        .charrom_read(charrom_read),
        .display_enable(display_enable),
        .cursor(cursor),
        .row_addr(row_addr),
        .blink_enabled(blink_enabled),
        .blink(blink),
        .hsync(hsync_int),
        .vsync(vsync_l),
        .video_enabled(video_enabled),
        .cga_color_reg(cga_color_reg),
        .video(video)
    );


    always @ (posedge clk)
    begin
        if (blink_counter == BLINK_MAX) begin
            blink_counter <= 0;
            blink <= ~blink;
        end else begin
            blink_counter <= blink_counter + 1;
        end
    end

    cga_scandoubler scandoubler (
        .clk(clk),
        .line_reset(line_reset),
        .video(video),		  
        .dbl_hsync(dbl_hsync),
        .dbl_video(dbl_video)
    );

endmodule
module cga(

    input clk,


    input[15:0] bus_a,
    input bus_ior_l,
    input bus_iow_l,
    input bus_memr_l,
    input bus_memw_l,
	 input word,
    input[15:0] bus_d,
    output[7:0] bus_out,
    output bus_dir,
    input bus_aen,
    output bus_rdy,


    output ram_we_l,
    output[18:0] ram_a,
    input[7:0] ram_d,
	 

    output hsync,
    output dbl_hsync,
    output vsync,

    output hdisp,
    output vdisp,

    output[3:0] video,
    output[3:0] dbl_video,
    output[6:0] comp_video,

    input thin_font
    );


    parameter MDA_70HZ = 0;
    parameter BLINK_MAX = 0;


    parameter USE_BUS_WAIT = 0;
    parameter NO_DISPLAY_DISABLE = 1;

    parameter IO_BASE_ADDR = 16'h3d0;


    wire crtc_cs;
    wire status_cs;
    wire colorsel_cs;
    wire control_cs;


    reg[7:0] bus_int_out;
    wire[7:0] bus_out_crtc;
    wire[7:0] bus_out_mem;
    wire[7:0] cga_status_reg;

	 reg[7:0] cga_control_reg = 8'b0010_1010;
    reg[7:0] cga_color_reg = 8'b0000_0000;
    wire hres_mode;
    wire grph_mode;
    wire bw_mode;
    wire mode_640;
    wire tandy_16_mode;
    wire video_enabled; 
    wire blink_enabled;

    wire hsync_int;
    wire vsync_l;
    wire cursor;

    wire display_enable;


    wire hclk;
    wire lclk;

    wire[13:0] crtc_addr;
    wire[4:0] row_addr;
    wire line_reset;
    wire pixel_addr13;
    wire pixel_addr14;

    wire charrom_read;
    wire disp_pipeline;
    wire isa_op_enable;
    wire vram_read_char;
    wire vram_read_att;
    wire vram_read;
    wire vram_read_a0;
    wire[4:0] clkdiv;
    wire crtc_clk;
    wire[7:0] ram_1_d;

    reg[23:0] blink_counter = 24'd0;
    reg blink = 0;

    reg bus_memw_synced_l;
    reg bus_memr_synced_l;
    reg bus_ior_synced_l;
    reg bus_iow_synced_l;




	 
	 assign ram_a = {4'b0001, pixel_addr14, pixel_addr13, crtc_addr[11:0],
                    vram_read_a0};
						  
	 assign ram_1_d = ram_d;

	 assign ram_we_l = vram_read;
	 


    always @ (posedge clk)
    begin


        bus_ior_synced_l <= bus_ior_l;
        bus_iow_synced_l <= bus_iow_l;
    end


    assign vsync = ~vsync_l;


    assign crtc_cs = (bus_a[15:3] == IO_BASE_ADDR[15:3]) & ~bus_aen;
    assign status_cs = (bus_a == IO_BASE_ADDR + 20'hA) & ~bus_aen;
	 assign control_cs = (bus_a == IO_BASE_ADDR + 16'h8) & ~bus_aen;
    assign colorsel_cs = (bus_a == IO_BASE_ADDR + 20'h9) & ~bus_aen;	 



	 

    always @ (*)
    begin


        if (status_cs & ~bus_ior_l) begin
            bus_int_out <= cga_status_reg;
        end else if (crtc_cs & ~bus_ior_l & (bus_a[0] == 1)) begin
            bus_int_out <= bus_out_crtc;




        end else begin
            bus_int_out <= 8'h00;
        end
    end


    assign bus_dir = (crtc_cs | status_cs) & ~bus_ior_l;


    assign bus_out = bus_int_out;










    assign cga_status_reg = {4'b1111, vsync_l, 2'b10, ~display_enable};



    assign hres_mode = cga_control_reg[0];
    assign grph_mode = cga_control_reg[1];
    assign bw_mode = cga_control_reg[2];




        assign video_enabled = cga_control_reg[3];


    assign mode_640 = cga_control_reg[4];
    assign blink_enabled = cga_control_reg[5];


    assign tandy_16_mode = cga_control_reg[6];

    assign hsync = hsync_int;


    always @ (posedge clk)
    begin
        if (~bus_iow_synced_l) begin
            if (control_cs) begin
                cga_control_reg <= bus_d[7:0];
            end else if (colorsel_cs) begin
                cga_color_reg <= bus_d[7:0];
            end
        end
    end


    crtc6845 crtc (
        .clk(clk),
        .divclk(crtc_clk),
        .cs(crtc_cs),
        .a0(bus_a[0]),
		.word(word),
        .write(~bus_iow_synced_l),
        .read(~bus_ior_synced_l),
        .bus(bus_d),
        .bus_out(bus_out_crtc),
        .lock(1'b0),
        .hsync(hsync_int),
        .vsync(vsync_l),


        .hdisp(hdisp),
        .vdisp(vdisp),

        .display_enable(display_enable),
        .cursor(cursor),
        .mem_addr(crtc_addr),
        .row_addr(row_addr),
        .line_reset(line_reset)
    );


    defparam crtc.H_TOTAL = 8'd56;
    defparam crtc.H_DISP = 8'd40;
    defparam crtc.H_SYNCPOS = 8'd45;
    defparam crtc.H_SYNCWIDTH = 4'd10;
    defparam crtc.V_TOTAL = 7'd31;
    defparam crtc.V_TOTALADJ = 5'd6;
    defparam crtc.V_DISP = 7'd25;
    defparam crtc.V_SYNCPOS = 7'd28;
    defparam crtc.V_MAXSCAN = 5'd7;
    defparam crtc.C_START = 7'd6;
    defparam crtc.C_END = 5'd7;



    assign pixel_addr13 = grph_mode ? row_addr[0] : crtc_addr[12];


    assign pixel_addr14 = grph_mode ? row_addr[1] : 1'b0;
	 



    cga_sequencer sequencer (
        .clk(clk),
        .clk_seq(clkdiv),
        .vram_read(vram_read),
        .vram_read_a0(vram_read_a0),
        .vram_read_char(vram_read_char),
        .vram_read_att(vram_read_att),
        .hres_mode(hres_mode),
        .crtc_clk(crtc_clk),
        .charrom_read(charrom_read),
        .disp_pipeline(disp_pipeline),
        .isa_op_enable(isa_op_enable),
        .hclk(hclk),
        .lclk(lclk)
    );


    cga_pixel pixel (
        .clk(clk),
        .clk_seq(clkdiv),
        .hres_mode(hres_mode),
        .grph_mode(grph_mode),
        .bw_mode(bw_mode),
        .mode_640(mode_640),
        .tandy_16_mode(tandy_16_mode),
        .thin_font(thin_font),
        .vram_data(ram_1_d),
        .vram_read_char(vram_read_char),
        .vram_read_att(vram_read_att),
        .disp_pipeline(disp_pipeline),
        .charrom_read(charrom_read),
        .display_enable(display_enable),
        .cursor(cursor),
        .row_addr(row_addr),
        .blink_enabled(blink_enabled),
        .blink(blink),
        .hsync(hsync_int),
        .vsync(vsync_l),
        .video_enabled(video_enabled),
        .cga_color_reg(cga_color_reg),
        .video(video)
    );


    always @ (posedge clk)
    begin
        if (blink_counter == BLINK_MAX) begin
            blink_counter <= 0;
            blink <= ~blink;
        end else begin
            blink_counter <= blink_counter + 1;
        end
    end

    cga_scandoubler scandoubler (
        .clk(clk),
        .line_reset(line_reset),
        .video(video),		  
        .dbl_hsync(dbl_hsync),
        .dbl_video(dbl_video)
    );

endmodule