data/full_repos/permissive/51918867/verilog/shift32.v
1: b'%Error: data/full_repos/permissive/51918867/verilog/shift32.v:103: Cannot find file containing module: \'mult16x16\'\nmult16x16 mult16x16_hi_inst(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51918867/verilog,data/full_repos/permissive/51918867/mult16x16\n             data/full_repos/permissive/51918867/verilog,data/full_repos/permissive/51918867/mult16x16.v\n             data/full_repos/permissive/51918867/verilog,data/full_repos/permissive/51918867/mult16x16.sv\n             mult16x16\n             mult16x16.v\n             mult16x16.sv\n             obj_dir/mult16x16\n             obj_dir/mult16x16.v\n             obj_dir/mult16x16.sv\n%Error: data/full_repos/permissive/51918867/verilog/shift32.v:109: Cannot find file containing module: \'mult16x16\'\nmult16x16 mult16x16_lo_inst(\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:121: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d0 :decode_dout = 16\'h0001;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:122: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d1 :decode_dout = 16\'h0002;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:123: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d2 :decode_dout = 16\'h0004;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:124: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d3 :decode_dout = 16\'h0008;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:125: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h10\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d4 :decode_dout = 16\'h0010;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:126: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h20\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d5 :decode_dout = 16\'h0020;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:127: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h40\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d6 :decode_dout = 16\'h0040;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:128: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h80\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d7 :decode_dout = 16\'h0080;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:129: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h100\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d8 :decode_dout = 16\'h0100;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:130: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h200\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d9 :decode_dout = 16\'h0200;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:131: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h400\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d10:decode_dout = 16\'h0400;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:132: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h800\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d11:decode_dout = 16\'h0800;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:133: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1000\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d12:decode_dout = 16\'h1000;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:134: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2000\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d13:decode_dout = 16\'h2000;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:135: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4000\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d14:decode_dout = 16\'h4000;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:136: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8000\' generates 16 bits.\n                                                                         : ... In instance shift32\n        4\'d15:decode_dout = 16\'h8000;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/51918867/verilog/shift32.v:148: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'decode_dout\' generates 17 bits.\n                                                                         : ... In instance shift32\nassign mul_b = decode_dout;\n             ^\n%Error: Exiting due to 2 error(s), 17 warning(s)\n'
module shift32(





    input[5:0]   shift_n,
    input        shift_left,
    input[31:0]  v,
    output[31:0] q
);





























































wire[15:0] mul_b;
wire[31:0] hi;
wire[31:0] lo;

wire[31:0] res_shl16;
wire[31:0] res_shr16;
wire[31:0] res_shl32;
wire[31:0] res_shr32;
reg[31:0]  res;

mult16x16 mult16x16_hi_inst(
    .a(v[31:16]),
    .b(mul_b),
    .p(hi)
);

mult16x16 mult16x16_lo_inst(
    .a(v[15:0]),
    .b(mul_b),
    .p(lo)
);


reg[3:0]  decode_din;
reg[16:0] decode_dout;
always@(*)
begin
    case (decode_din)
        4'd0 :decode_dout = 16'h0001;
        4'd1 :decode_dout = 16'h0002;
        4'd2 :decode_dout = 16'h0004;
        4'd3 :decode_dout = 16'h0008;
        4'd4 :decode_dout = 16'h0010;
        4'd5 :decode_dout = 16'h0020;
        4'd6 :decode_dout = 16'h0040;
        4'd7 :decode_dout = 16'h0080;
        4'd8 :decode_dout = 16'h0100;
        4'd9 :decode_dout = 16'h0200;
        4'd10:decode_dout = 16'h0400;
        4'd11:decode_dout = 16'h0800;
        4'd12:decode_dout = 16'h1000;
        4'd13:decode_dout = 16'h2000;
        4'd14:decode_dout = 16'h4000;
        4'd15:decode_dout = 16'h8000;
    endcase
end

always@(*)
begin
    if (shift_left)
        decode_din = shift_n[3:0];
    else
        decode_din = ~shift_n[3:0] + 4'b0001;
end

assign mul_b = decode_dout;


assign res_shl16[31:0] = {hi[15:0], 16'h0000} | lo[31:0];
assign res_shr16[31:0] =  hi[31:0]            | {16'h0000, lo[31:16]};
assign res_shl32[31:0] = {lo[15:0], 16'h00};
assign res_shr32[31:0] = {16'h00,   hi[31:16]};

always@(*)
begin
    if (shift_n == 6'd32)
        res = 32'h0;
    else if (shift_n == 6'd0)
        res = v;
    else if (shift_n[4] == 0)
        if (shift_left)
            res = res_shl16;
        else
            res = res_shr16;
    else
        if (shift_left)
            res = res_shl32;
        else
            res = res_shr32;
end

assign q = res;


endmodule
module shift32(





    input[5:0]   shift_n,
    input        shift_left,
    input[31:0]  v,
    output[31:0] q
);






























































wire[15:0] mul_b;
wire[31:0] hi;
wire[31:0] lo;

wire[31:0] res_shl16;
wire[31:0] res_shr16;
wire[31:0] res_shl32;
wire[31:0] res_shr32;
reg[31:0]  res;

mult16x16 mult16x16_hi_inst(
    .a(v[31:16]),
    .b(mul_b),
    .p(hi)
);

mult16x16 mult16x16_lo_inst(
    .a(v[15:0]),
    .b(mul_b),
    .p(lo)
);


reg[3:0]  decode_din;
reg[16:0] decode_dout;
always@(*)
begin
    case (decode_din)
        4'd0 :decode_dout = 16'h0001;
        4'd1 :decode_dout = 16'h0002;
        4'd2 :decode_dout = 16'h0004;
        4'd3 :decode_dout = 16'h0008;
        4'd4 :decode_dout = 16'h0010;
        4'd5 :decode_dout = 16'h0020;
        4'd6 :decode_dout = 16'h0040;
        4'd7 :decode_dout = 16'h0080;
        4'd8 :decode_dout = 16'h0100;
        4'd9 :decode_dout = 16'h0200;
        4'd10:decode_dout = 16'h0400;
        4'd11:decode_dout = 16'h0800;
        4'd12:decode_dout = 16'h1000;
        4'd13:decode_dout = 16'h2000;
        4'd14:decode_dout = 16'h4000;
        4'd15:decode_dout = 16'h8000;
    endcase
end

always@(*)
begin
    if (shift_left)
        decode_din = shift_n[3:0];
    else
        decode_din = ~shift_n[3:0] + 4'b0001;
end

assign mul_b = decode_dout;


assign res_shl16[31:0] = {hi[15:0], 16'h0000} | lo[31:0];
assign res_shr16[31:0] =  hi[31:0]            | {16'h0000, lo[31:16]};
assign res_shl32[31:0] = {lo[15:0], 16'h00};
assign res_shr32[31:0] = {16'h00,   hi[31:16]};

always@(*)
begin
    if (shift_n == 6'd32)
        res = 32'h0;
    else if (shift_n == 6'd0)
        res = v;
    else if (shift_n[4] == 0)
        if (shift_left)
            res = res_shl16;
        else
            res = res_shr16;
    else
        if (shift_left)
            res = res_shl32;
        else
            res = res_shr32;
end

assign q = res;


endmodule