data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:51: Cannot find include file: ../opl3.vh\n`include "../opl3.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.sv\n             ../opl3.vh\n             ../opl3.vh.v\n             ../opl3.vh.sv\n             obj_dir/../opl3.vh\n             obj_dir/../opl3.vh.v\n             obj_dir/../opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:57: Define or directive not defined: \'`BANK_NUM_WIDTH\'\n    input wire [`BANK_NUM_WIDTH-1:0] bank_num,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:58: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,  \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:59: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:60: Define or directive not defined: \'`REG_WS_WIDTH\'\n    input wire [`REG_WS_WIDTH-1:0] ws,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:61: Define or directive not defined: \'`ENV_WIDTH\'\n    input wire [`ENV_WIDTH-1:0] env,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:63: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    input wire [`OP_OUT_WIDTH-1:0] modulation,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:65: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    output reg signed [`OP_OUT_WIDTH-1:0] out = 0\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:73: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:73: Define or directive not defined: \'`NUM_BANKS\'\n    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:73: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:74: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-1:0] final_phase [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:74: Define or directive not defined: \'`NUM_BANKS\'\n    reg [`PHASE_ACC_WIDTH-1:0] final_phase [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:74: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [`PHASE_ACC_WIDTH-1:0] final_phase [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:75: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:77: Define or directive not defined: \'`NUM_BANKS\'\n    reg is_odd_period [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0]; \n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:77: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg is_odd_period [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0]; \n                                       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:78: Define or directive not defined: \'`NUM_BANKS\'\n    wire phase_acc_msb_pos_edge_pulse [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:78: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    wire phase_acc_msb_pos_edge_pulse [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                                       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:82: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire [`OP_OUT_WIDTH-1:0] tmp_out0;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:83: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:84: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:85: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:86: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws4;  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:88: Define or directive not defined: \'`REG_WS_WIDTH\'\n    wire [`REG_WS_WIDTH-1:0] ws_post_opl;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:147: Define or directive not defined: \'`NUM_BANKS\'\n    for (i = 0; i < `NUM_BANKS; i = i+1) begin: detecti\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:147: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for (i = 0; i < `NUM_BANKS; i = i+1) begin: detecti\n                              ^\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:148: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n        for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j+1) begin: detectj\n                        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:162: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:212: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n        3: tmp_out2 = final_phase[bank_num][op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;\n                                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:215: Define or directive not defined: \'`OP_OUT_WIDTH\'\n        6: tmp_out2 = tmp_out1 > 0 ? 2**(`OP_OUT_WIDTH-1) - 1 : -2**(`OP_OUT_WIDTH-1);\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:215: Define or directive not defined: \'`OP_OUT_WIDTH\'\n        6: tmp_out2 = tmp_out1 > 0 ? 2**(`OP_OUT_WIDTH-1) - 1 : -2**(`OP_OUT_WIDTH-1);\n                                                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:221: Define or directive not defined: \'`OP_NORMAL\'\n        `OP_NORMAL:    out <= tmp_out2;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:221: syntax error, unexpected \':\', expecting endcase\n        `OP_NORMAL:    out <= tmp_out2;\n                  ^\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/phase_generator.v:222: Define or directive not defined: \'`OP_BASS_DRUM\'\n        `OP_BASS_DRUM: out <= tmp_out2;\n        ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module phase_generator (
    input wire clk,
    input wire sample_clk_en,
    input wire is_new,    
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,  
    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire [`ENV_WIDTH-1:0] env,
    input wire key_on_pulse,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire [2:0] op_type,    
    output reg signed [`OP_OUT_WIDTH-1:0] out = 0
);	
    localparam LOG_SIN_OUT_WIDTH = 12;
    localparam EXP_OUT_WIDTH = 10;
    localparam LOG_SIN_PLUS_GAIN_WIDTH = 13;
    localparam PIPELINE_DELAY = 2;     
    
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed = 0;
    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg [`PHASE_ACC_WIDTH-1:0] final_phase [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;
    
    reg is_odd_period [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire phase_acc_msb_pos_edge_pulse [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [LOG_SIN_OUT_WIDTH-1:0] log_sin_out; 
    wire [LOG_SIN_PLUS_GAIN_WIDTH-1:0] log_sin_plus_gain;     
    wire [EXP_OUT_WIDTH-1:0] exp_out;
    wire [`OP_OUT_WIDTH-1:0] tmp_out0;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws4;  
    reg [LOG_SIN_OUT_WIDTH-1:0] tmp_ws7;
    wire [`REG_WS_WIDTH-1:0] ws_post_opl;
    

    assign ws_post_opl = ws & (is_new ? 'h7 : 'h3);
    

    always @(posedge clk) begin
        sample_clk_en_delayed <= sample_clk_en_delayed << 1;
        sample_clk_en_delayed[0] <= sample_clk_en;
    end
    

    calc_rhythm_phase calc_rhythm_phase (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),
        .phase_acc(phase_acc[bank_num][op_num]),
        .phase_acc_17(phase_acc[0][17]),
        .phase_acc_13(phase_acc[0][13]),
        .op_type(op_type),    
        .rhythm_phase(rhythm_phase)
    );


    always @(posedge clk)
        if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (key_on_pulse) begin
                phase_acc[bank_num][op_num] <= 0;
                final_phase[bank_num][op_num] <= 0;
            end
            else if (ws_post_opl == 4 || ws_post_opl == 5) begin

                phase_acc[bank_num][op_num] <= phase_acc[bank_num][op_num] + (phase_inc << 1);
                final_phase[bank_num][op_num] <= rhythm_phase + (phase_inc << 1)
                 + (modulation << 10);
            end    
            else begin
                phase_acc[bank_num][op_num] <= phase_acc[bank_num][op_num] + phase_inc;
                final_phase[bank_num][op_num] <= rhythm_phase + phase_inc
                 + (modulation << 10);
            end    
        
    assign tmp_ws2 = tmp_out1 < 0 ? ~tmp_out1 : tmp_out1;
    assign tmp_ws4 = is_odd_period[bank_num][op_num] ? tmp_out1 : 0;
    
    genvar i, j;
    generate
    for (i = 0; i < `NUM_BANKS; i = i+1) begin: detecti
        for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j+1) begin: detectj
            edge_detector #(
                .EDGE_LEVEL(0),
                .CLK_DLY(0)
            ) phase_acc_msb_edge_detect (
                .clk(clk),
                .clk_en(1'b1),
                .in(final_phase[bank_num][op_num][19]),
                .edge_detected(phase_acc_msb_pos_edge_pulse[i][j])
            );   
    
            always @(posedge clk)
                if (phase_acc_msb_pos_edge_pulse[i][j])
                    is_odd_period[i][j] <= !is_odd_period[i][j]; 
        end
      end
    endgenerate
	
    opl3_log_sine_lut log_sine_lut_inst (
        .theta(final_phase[bank_num][op_num][18] ? ~final_phase[bank_num][op_num][17:10]
         : final_phase[bank_num][op_num][17:10]),
        .out(log_sin_out),
        .clk(clk)
    );
    

    always @ *
        case (final_phase[bank_num][op_num][19:18])
        0: tmp_ws7[11] = 0;
        1: tmp_ws7[11] = 1;
        2: tmp_ws7[11] = 1;
        3: tmp_ws7[11] = 0;
        endcase
        
    always @ * 
        tmp_ws7[10:0] = final_phase[bank_num][op_num][19] ?
         ~final_phase[bank_num][op_num][17:10] << 3 : final_phase[bank_num][op_num][17:10] << 3;        
    
    assign log_sin_plus_gain = (ws_post_opl == 7 ? tmp_ws7 : log_sin_out) + (env << 3);
        
    opl3_exp_lut exp_lut_inst (
        .in(~log_sin_plus_gain[7:0]),
        .out(exp_out),
        .clk(clk)
    );
    
    assign tmp_out0 = (2**10 + exp_out) << 1;
        
    always @ *
        if (final_phase[bank_num][op_num][19])
            tmp_out1 = ~(tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]);
        else
            tmp_out1 = tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]; 
        

    always @ *
        case (ws_post_opl)
        0: tmp_out2 = tmp_out1;
        1: tmp_out2 = tmp_out1 < 0 ? 0 : tmp_out1;
        2: tmp_out2 = tmp_ws2;
        3: tmp_out2 = final_phase[bank_num][op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;
        4: tmp_out2 = tmp_ws4;
        5: tmp_out2 = tmp_ws4 < 0 ? ~tmp_ws4 : tmp_ws4;
        6: tmp_out2 = tmp_out1 > 0 ? 2**(`OP_OUT_WIDTH-1) - 1 : -2**(`OP_OUT_WIDTH-1);
        7: tmp_out2 = tmp_out1;
        endcase 
            
    always @(posedge clk)
        case (op_type)
        `OP_NORMAL:    out <= tmp_out2;
        `OP_BASS_DRUM: out <= tmp_out2;
        default:      out <= tmp_out2 << 1;
        endcase      
endmodule
module phase_generator (
    input wire clk,
    input wire sample_clk_en,
    input wire is_new,    
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,  
    input wire [`PHASE_ACC_WIDTH-1:0] phase_inc,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire [`ENV_WIDTH-1:0] env,
    input wire key_on_pulse,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire [2:0] op_type,    
    output reg signed [`OP_OUT_WIDTH-1:0] out = 0
);
	
    localparam LOG_SIN_OUT_WIDTH = 12;
    localparam EXP_OUT_WIDTH = 10;
    localparam LOG_SIN_PLUS_GAIN_WIDTH = 13;
    localparam PIPELINE_DELAY = 2;     
    
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed = 0;
    reg [`PHASE_ACC_WIDTH-1:0] phase_acc [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg [`PHASE_ACC_WIDTH-1:0] final_phase [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`PHASE_ACC_WIDTH-1:0] rhythm_phase;
    
    reg is_odd_period [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire phase_acc_msb_pos_edge_pulse [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [LOG_SIN_OUT_WIDTH-1:0] log_sin_out; 
    wire [LOG_SIN_PLUS_GAIN_WIDTH-1:0] log_sin_plus_gain;     
    wire [EXP_OUT_WIDTH-1:0] exp_out;
    wire [`OP_OUT_WIDTH-1:0] tmp_out0;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out1;
    reg signed [`OP_OUT_WIDTH-1:0] tmp_out2;    
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws2;
    wire signed [`OP_OUT_WIDTH-1:0] tmp_ws4;  
    reg [LOG_SIN_OUT_WIDTH-1:0] tmp_ws7;
    wire [`REG_WS_WIDTH-1:0] ws_post_opl;
    

    assign ws_post_opl = ws & (is_new ? 'h7 : 'h3);
    

    always @(posedge clk) begin
        sample_clk_en_delayed <= sample_clk_en_delayed << 1;
        sample_clk_en_delayed[0] <= sample_clk_en;
    end
    

    calc_rhythm_phase calc_rhythm_phase (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),
        .phase_acc(phase_acc[bank_num][op_num]),
        .phase_acc_17(phase_acc[0][17]),
        .phase_acc_13(phase_acc[0][13]),
        .op_type(op_type),    
        .rhythm_phase(rhythm_phase)
    );


    always @(posedge clk)
        if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (key_on_pulse) begin
                phase_acc[bank_num][op_num] <= 0;
                final_phase[bank_num][op_num] <= 0;
            end
            else if (ws_post_opl == 4 || ws_post_opl == 5) begin

                phase_acc[bank_num][op_num] <= phase_acc[bank_num][op_num] + (phase_inc << 1);
                final_phase[bank_num][op_num] <= rhythm_phase + (phase_inc << 1)
                 + (modulation << 10);
            end    
            else begin
                phase_acc[bank_num][op_num] <= phase_acc[bank_num][op_num] + phase_inc;
                final_phase[bank_num][op_num] <= rhythm_phase + phase_inc
                 + (modulation << 10);
            end    
        
    assign tmp_ws2 = tmp_out1 < 0 ? ~tmp_out1 : tmp_out1;
    assign tmp_ws4 = is_odd_period[bank_num][op_num] ? tmp_out1 : 0;
    
    genvar i, j;
    generate
    for (i = 0; i < `NUM_BANKS; i = i+1) begin: detecti
        for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j+1) begin: detectj
            edge_detector #(
                .EDGE_LEVEL(0),
                .CLK_DLY(0)
            ) phase_acc_msb_edge_detect (
                .clk(clk),
                .clk_en(1'b1),
                .in(final_phase[bank_num][op_num][19]),
                .edge_detected(phase_acc_msb_pos_edge_pulse[i][j])
            );   
    
            always @(posedge clk)
                if (phase_acc_msb_pos_edge_pulse[i][j])
                    is_odd_period[i][j] <= !is_odd_period[i][j]; 
        end
      end
    endgenerate
	
    opl3_log_sine_lut log_sine_lut_inst (
        .theta(final_phase[bank_num][op_num][18] ? ~final_phase[bank_num][op_num][17:10]
         : final_phase[bank_num][op_num][17:10]),
        .out(log_sin_out),
        .clk(clk)
    );
    

    always @ *
        case (final_phase[bank_num][op_num][19:18])
        0: tmp_ws7[11] = 0;
        1: tmp_ws7[11] = 1;
        2: tmp_ws7[11] = 1;
        3: tmp_ws7[11] = 0;
        endcase
        
    always @ * 
        tmp_ws7[10:0] = final_phase[bank_num][op_num][19] ?
         ~final_phase[bank_num][op_num][17:10] << 3 : final_phase[bank_num][op_num][17:10] << 3;        
    
    assign log_sin_plus_gain = (ws_post_opl == 7 ? tmp_ws7 : log_sin_out) + (env << 3);
        
    opl3_exp_lut exp_lut_inst (
        .in(~log_sin_plus_gain[7:0]),
        .out(exp_out),
        .clk(clk)
    );
    
    assign tmp_out0 = (2**10 + exp_out) << 1;
        
    always @ *
        if (final_phase[bank_num][op_num][19])
            tmp_out1 = ~(tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]);
        else
            tmp_out1 = tmp_out0 >> log_sin_plus_gain[LOG_SIN_PLUS_GAIN_WIDTH-1:8]; 
        

    always @ *
        case (ws_post_opl)
        0: tmp_out2 = tmp_out1;
        1: tmp_out2 = tmp_out1 < 0 ? 0 : tmp_out1;
        2: tmp_out2 = tmp_ws2;
        3: tmp_out2 = final_phase[bank_num][op_num][`PHASE_ACC_WIDTH-2] ? 0 : tmp_ws2;
        4: tmp_out2 = tmp_ws4;
        5: tmp_out2 = tmp_ws4 < 0 ? ~tmp_ws4 : tmp_ws4;
        6: tmp_out2 = tmp_out1 > 0 ? 2**(`OP_OUT_WIDTH-1) - 1 : -2**(`OP_OUT_WIDTH-1);
        7: tmp_out2 = tmp_out1;
        endcase 
            
    always @(posedge clk)
        case (op_type)
        `OP_NORMAL:    out <= tmp_out2;
        `OP_BASS_DRUM: out <= tmp_out2;
        default:      out <= tmp_out2 << 1;
        endcase      
endmodule