data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_first_trivial_design/bdw_work/modules/dut/BASIC/v_rtl/dut_Not_1U_1U_4.v
data/verilator_xmls/68ba4e0e-9268-4148-8feb-04b20fa01ee6.xml
module dut_Not_1U_1U_4 (
	in1,
	out1
	);
input  in1;
output  out1;
wire  asc001;

assign asc001 = 
	((~in1));

assign out1 = asc001;
endmodule
module dut_Not_1U_1U_4 (
	in1,
	out1
	);

input  in1;
output  out1;
wire  asc001;

assign asc001 = 
	((~in1));

assign out1 = asc001;
endmodule