data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:23: Cannot find include file: genericIOSateliteEnv.v\n`include "genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA,data/full_repos/permissive/429196919/genericIOSateliteEnv.v.sv\n             genericIOSateliteEnv.v\n             genericIOSateliteEnv.v.v\n             genericIOSateliteEnv.v.sv\n             obj_dir/genericIOSateliteEnv.v\n             obj_dir/genericIOSateliteEnv.v.v\n             obj_dir/genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:24: Cannot find include file: pulse/pulse.v\n`include "pulse/pulse.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:25: Cannot find include file: pwm/pwm.v\n`include "pwm/pwm.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:26: Cannot find include file: latchReg/latchReg.v\n`include "latchReg/latchReg.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:27: Cannot find include file: shiftReg/shiftReg.v\n`include "shiftReg/shiftReg.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:28: Cannot find include file: ws2811Decoder/ws2811Decoder.v\n`include "ws2811Decoder/ws2811Decoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:29: Cannot find include file: ws2811Encoder/ws2811Encoder.v\n`include "ws2811Encoder/ws2811Encoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:30: Cannot find include file: crc4/crc4.v\n`include "crc4/crc4.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:75: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;\n             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n reg[($clog2(`WATCHDOG_TIMEOUT_CYC))-1:0] watchdogReg = 0;\n                                  ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`CRC_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`FEEDBACK_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`COMMAND_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`MODE_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`ACTUATOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:101: Define or directive not defined: \'`SENSOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:106: Define or directive not defined: \'`CRC_WD\'\n   if(rxCnt>`CRC_WD + 1\'b1) begin        \n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:110: Define or directive not defined: \'`CRC_WD\'\n   else if(rxCnt == `CRC_WD + 1\'b1) begin      \n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:115: Define or directive not defined: \'`CRC_WD\'\n   else if( rxCnt < `CRC_WD + 1\'b1 && rxCnt > 7\'b0) begin\n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`CRC_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`FEEDBACK_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`COMMAND_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`MODE_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`NO_ACTUATORS\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`ACTUATOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:132: Define or directive not defined: \'`SENSOR_WD\'\n   rxCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`CRC_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`FEEDBACK_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`COMMAND_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`NO_ACTUATORS\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`MODE_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`NO_ACTUATORS\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`ACTUATOR_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:142: Define or directive not defined: \'`SENSOR_WD\'\n   txCnt <= `CRC_WD + `FEEDBACK_WD + `COMMAND_WD + `NO_ACTUATORS*`MODE_WD + `NO_ACTUATORS*`ACTUATOR_WD + `SENSOR_WD;\n                                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:149: Define or directive not defined: \'`CRC_WD\'\n   if(txCnt>`CRC_WD + 1\'b1) begin        \n            ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:153: Define or directive not defined: \'`CRC_WD\'\n   else if(txCnt == `CRC_WD + 1\'b1 && firstSatShift) begin  \n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:158: Define or directive not defined: \'`CRC_WD\'\n   else if( txCnt < `CRC_WD + 1\'b1 && txCnt > 7\'b0) begin\n                    ^~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:174: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n  else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)\n                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:174: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(watchdogReg<`WATCHDOG_TIMEOUT_CYC)\n                                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:176: Define or directive not defined: \'`WATCHDOG_TIMEOUT_CYC\'\n  else if(watchdogReg>=`WATCHDOG_TIMEOUT_CYC)\n                       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:184: Define or directive not defined: \'`FEEDBACK_REMOTECRCERR\'\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b1;\n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:184: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b1;\n                                   ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:186: Define or directive not defined: \'`FEEDBACK_REMOTECRCERR\'\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b0;\n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSatelite.v:186: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    feedback[`FEEDBACK_REMOTECRCERR] <= 1\'b0;\n                                   ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module actuators(input serialDataIn,
				 input serialClk,
				 input enableShift,
				 input masterClk,
				 input disableActuators,
				 output wire[3:0] actuator,
				 output wire serialDataOut);
	wire serial_1;
	wire serial_2;
	wire serial_3;
	wire serial_4;
	wire serial_5;
	wire[3:0] modeRegHalfByte_0;
	wire[7:0] modeRegByte_1;
	wire[2:0] mode_0;
	wire[2:0] mode_1;
	wire[2:0] mode_2;
	wire[2:0] mode_3;

	assign mode_0 = modeRegHalfByte_0[2:0];
	assign mode_1 = {modeRegByte_1[1:0], modeRegHalfByte_0[3]};
	assign mode_2 = modeRegByte_1[4:2];
	assign mode_3 = modeRegByte_1[7:5];

	shiftReg #(.WIDTH(4)) modeReg_0(.serialInput (serialDataIn), .clk (serialClk), .load (1'b0), .loaded (), .enableShift (enableShift | disableActuators), .masterClk (masterClk), .parallelInput (4'b0), .parallelOutput (modeRegHalfByte_0), .serialOutput (serial_1));
	shiftReg #(.WIDTH(8)) modeReg_1(.serialInput (serial_1), .clk (serialClk), .load (1'b0), .loaded (), .enableShift (enableShift | disableActuators), .masterClk (masterClk), .parallelInput (8'b0), .parallelOutput (modeRegByte_1), .serialOutput (serial_2));
	actuatorPin actuator_0(.serialIn (serial_2), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_0), .masterClk (masterClk), .actuator (actuator[0]), .serialOut (serial_3));
	actuatorPin actuator_1(.serialIn (serial_3), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_1), .masterClk (masterClk), .actuator (actuator[1]), .serialOut (serial_4));
	actuatorPin actuator_2(.serialIn (serial_4), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_2), .masterClk (masterClk), .actuator (actuator[2]), .serialOut (serial_5));
	actuatorPin actuator_3(.serialIn (serial_5), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_3), .masterClk (masterClk), .actuator (actuator[3]), .serialOut (serialDataOut));
endmodule
module actuators(input serialDataIn,
				 input serialClk,
				 input enableShift,
				 input masterClk,
				 input disableActuators,
				 output wire[3:0] actuator,
				 output wire serialDataOut);

	wire serial_1;
	wire serial_2;
	wire serial_3;
	wire serial_4;
	wire serial_5;
	wire[3:0] modeRegHalfByte_0;
	wire[7:0] modeRegByte_1;
	wire[2:0] mode_0;
	wire[2:0] mode_1;
	wire[2:0] mode_2;
	wire[2:0] mode_3;

	assign mode_0 = modeRegHalfByte_0[2:0];
	assign mode_1 = {modeRegByte_1[1:0], modeRegHalfByte_0[3]};
	assign mode_2 = modeRegByte_1[4:2];
	assign mode_3 = modeRegByte_1[7:5];

	shiftReg #(.WIDTH(4)) modeReg_0(.serialInput (serialDataIn), .clk (serialClk), .load (1'b0), .loaded (), .enableShift (enableShift | disableActuators), .masterClk (masterClk), .parallelInput (4'b0), .parallelOutput (modeRegHalfByte_0), .serialOutput (serial_1));
	shiftReg #(.WIDTH(8)) modeReg_1(.serialInput (serial_1), .clk (serialClk), .load (1'b0), .loaded (), .enableShift (enableShift | disableActuators), .masterClk (masterClk), .parallelInput (8'b0), .parallelOutput (modeRegByte_1), .serialOutput (serial_2));
	actuatorPin actuator_0(.serialIn (serial_2), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_0), .masterClk (masterClk), .actuator (actuator[0]), .serialOut (serial_3));
	actuatorPin actuator_1(.serialIn (serial_3), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_1), .masterClk (masterClk), .actuator (actuator[1]), .serialOut (serial_4));
	actuatorPin actuator_2(.serialIn (serial_4), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_2), .masterClk (masterClk), .actuator (actuator[2]), .serialOut (serial_5));
	actuatorPin actuator_3(.serialIn (serial_5), .serialClk (serialClk), .enableShift (enableShift | disableActuators), .mode (mode_3), .masterClk (masterClk), .actuator (actuator[3]), .serialOut (serialDataOut));
endmodule