data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Arithmetic_Circuits/66_Hadd.v
data/verilator_xmls/9179b59a-1746-4256-b6bb-0aa357c9228d.xml
module top_module( 
    input a, b,
    output cout, sum );

    assign cout = a & b;
    assign sum = a ^ b;
endmodule
module top_module( 
    input a, b,
    output cout, sum );


    assign cout = a & b;
    assign sum = a ^ b;
endmodule