data/full_repos/permissive/429850924/modules.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/429850924/modules.v:52: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'dfrl\'\nmodule dfrl (input wire clk, reset, load, in, output wire out);\n       ^~~~\n                                                                    : ... Top module \'fulladder\'\nmodule fulladder (input wire i0, i1, cin, output wire sum, cout);  \n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module fulladder (input wire i0, i1, cin, output wire sum, cout);
wire t0, t1, t2;
  xor3 _i0 (i0, i1, cin, sum);
  and2 _i1 (i0, i1, t0);
  and2 _i2 (i1, cin, t1);
  and2 _i3 (cin, i0, t2);
  or3 _i4 (t0, t1, t2, cout);
endmodule
module fulladder (input wire i0, i1, cin, output wire sum, cout);

wire t0, t1, t2;
  xor3 _i0 (i0, i1, cin, sum);
  and2 _i1 (i0, i1, t0);
  and2 _i2 (i1, cin, t1);
  and2 _i3 (cin, i0, t2);
  or3 _i4 (t0, t1, t2, cout);
endmodule