data/full_repos/permissive/460468583/data/verilog/rndswitch.v
1: b"%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:2: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\ninput [`BITMAP_NB_SEGMENTS-1:0] s;\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:3: Define or directive not defined: '`RNDSIZE'\ninput [`RNDSIZE*(`RNDSIZE-1)/2-1:0] r;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:3: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\ninput [`RNDSIZE*(`RNDSIZE-1)/2-1:0] r;\n               ^\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:3: Define or directive not defined: '`RNDSIZE'\ninput [`RNDSIZE*(`RNDSIZE-1)/2-1:0] r;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:5: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\noutput [`BITMAP_NB_SEGMENTS-1:0] o;\n        ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:6: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\nwire [`BITMAP_NB_SEGMENTS-1:0] t;\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:9: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\nfor (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:9: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nfor (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin\n                               ^\n%Error: data/full_repos/permissive/460468583/data/verilog/rndswitch.v:12: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\nfor (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n"
module rndswitch ( s , r , z , o );
input [`BITMAP_NB_SEGMENTS-1:0] s;
input [`RNDSIZE*(`RNDSIZE-1)/2-1:0] r;
input z;
output [`BITMAP_NB_SEGMENTS-1:0] o;
wire [`BITMAP_NB_SEGMENTS-1:0] t;

genvar i;
for (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin
    assign t[i] = s[i] & r[i];
end
for (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin
    assign o[i] = t[i] ^ z;
end
endmodule
module rndswitch ( s , r , z , o );

input [`BITMAP_NB_SEGMENTS-1:0] s;
input [`RNDSIZE*(`RNDSIZE-1)/2-1:0] r;
input z;
output [`BITMAP_NB_SEGMENTS-1:0] o;
wire [`BITMAP_NB_SEGMENTS-1:0] t;

genvar i;
for (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin
    assign t[i] = s[i] & r[i];
end
for (i=0; i<`BITMAP_NB_SEGMENTS; i=i+1) begin
    assign o[i] = t[i] ^ z;
end
endmodule