data/full_repos/permissive/504762811/minicpu.v
1: b'%Error: data/full_repos/permissive/504762811/minicpu.v:1: Cannot find include file: minicpu.h\n`include "minicpu.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.v\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.sv\n             minicpu.h\n             minicpu.h.v\n             minicpu.h.sv\n             obj_dir/minicpu.h\n             obj_dir/minicpu.h.v\n             obj_dir/minicpu.h.sv\n%Error: data/full_repos/permissive/504762811/minicpu.v:11: Define or directive not defined: \'`AddrBus\'\n output wire [`AddrBus] ram_addr,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output wire [`AddrBus] ram_addr,\n                      ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:12: Define or directive not defined: \'`DataBus\'\n output wire [`DataBus] ram_d_in,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:13: Define or directive not defined: \'`DataBus\'\n input  wire [`DataBus] ram_d_out,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire [`AddrBus] rom_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:16: Define or directive not defined: \'`AddrBus\'\n output wire [`AddrBus] rom_addr,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:17: Define or directive not defined: \'`Rom_Bus\'\n input  wire [`Rom_Bus] rom_data,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire rst_\n ^~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:22: Define or directive not defined: \'`AddrBus\'\n reg  [`AddrBus] valP;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg  [`AddrBus] valP;\n               ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:23: Define or directive not defined: \'`DataBus\'\n wire [`DataBus] valA, valB, valE;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`DataBus] valA, valB, valE;\n               ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:25: Define or directive not defined: \'`DataBus\'\n reg  [`DataBus] aluB;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg  [`DataBus] aluB;\n               ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:26: Define or directive not defined: \'`DataBus\'\n reg  [`DataBus] aluA;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg  [`DataBus] aluA;\n               ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:31: Define or directive not defined: \'`AddrBus\'\n reg  [`AddrBus] new_pc; \n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg  [`AddrBus] new_pc; \n               ^\n%Error: data/full_repos/permissive/504762811/minicpu.v:42: Define or directive not defined: \'`HLT\'\n  valP = rom_addr + ((rom_data[23:20]==`HLT)? 0: (rom_data[23:20]==`NOP||rom_data[23:20]==`RET)? 1: 3);\n                                       ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:42: Define or directive not defined: \'`NOP\'\n  valP = rom_addr + ((rom_data[23:20]==`HLT)? 0: (rom_data[23:20]==`NOP||rom_data[23:20]==`RET)? 1: 3);\n                                                                   ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:42: Define or directive not defined: \'`RET\'\n  valP = rom_addr + ((rom_data[23:20]==`HLT)? 0: (rom_data[23:20]==`NOP||rom_data[23:20]==`RET)? 1: 3);\n                                                                                          ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:44: Define or directive not defined: \'`POP\'\n  dstM = (rom_data[23:20]==`POP)? rom_data[14:12] : (rom_data[23:20]==`LD )? rom_data[10: 8]: `R0;\n                           ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:44: Define or directive not defined: \'`LD\'\n  dstM = (rom_data[23:20]==`POP)? rom_data[14:12] : (rom_data[23:20]==`LD )? rom_data[10: 8]: `R0;\n                                                                      ^~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:44: Define or directive not defined: \'`R0\'\n  dstM = (rom_data[23:20]==`POP)? rom_data[14:12] : (rom_data[23:20]==`LD )? rom_data[10: 8]: `R0;\n                                                                                              ^~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`PUSH\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                           ^~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`POP\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                   ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`CALL\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                          ^~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`RET\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                  ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`RSP\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                         ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`OPR\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                                                  ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`OPI\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                                                                                            ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`IRMOV\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                                                                                                                   ^~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`RRMOV\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                                                                                                                                            ^~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:46: Define or directive not defined: \'`R0\'\n  dstE = (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP : (rom_data[23:20]==`OPR)? rom_data[ 6: 4]: (rom_data[23:20]==`OPI||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RRMOV)? rom_data[10: 8]: `R0;\n                                                                                                                                                                                                                                                      ^~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:51: Define or directive not defined: \'`POP\'\n .srcA ((rom_data[23:20]==`POP||rom_data[23:20]==`RET)? `RSP:rom_data[14:12]),\n                          ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:51: Define or directive not defined: \'`RET\'\n .srcA ((rom_data[23:20]==`POP||rom_data[23:20]==`RET)? `RSP:rom_data[14:12]),\n                                                 ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:51: Define or directive not defined: \'`RSP\'\n .srcA ((rom_data[23:20]==`POP||rom_data[23:20]==`RET)? `RSP:rom_data[14:12]),\n                                                        ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:52: Define or directive not defined: \'`PUSH\'\n .srcB ( (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP:rom_data[10: 8] ),\n                           ^~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:52: Define or directive not defined: \'`POP\'\n .srcB ( (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP:rom_data[10: 8] ),\n                                                   ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:52: Define or directive not defined: \'`CALL\'\n .srcB ( (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP:rom_data[10: 8] ),\n                                                                          ^~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:52: Define or directive not defined: \'`RET\'\n .srcB ( (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP:rom_data[10: 8] ),\n                                                                                                  ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:52: Define or directive not defined: \'`RSP\'\n .srcB ( (rom_data[23:20]==`PUSH||rom_data[23:20]==`POP||rom_data[23:20]==`CALL||rom_data[23:20]==`RET)? `RSP:rom_data[10: 8] ),\n                                                                                                         ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`RRMOV\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                           ^~~~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`LD\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                           ^~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`ST\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                                                 ^~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`OPI\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                                                                       ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`JMP\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                                                                                                                  ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`BNG\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                                                                                                                        ^~~~\n%Error: data/full_repos/permissive/504762811/minicpu.v:64: Define or directive not defined: \'`IRMOV\'\n  aluB = (rom_data[23:20]==`RRMOV)? valA:(rom_data[23:20]==`LD||rom_data[23:20]==`ST||rom_data[23:20]==`OPI||{rom_data[23:20], rom_data[19:16]}=={`JMP, `BNG}||rom_data[23:20]==`IRMOV||rom_data[23:20]==`RMMOV)? rom_data[ 7: 0]: valB;\n                                                                                                                                                                                ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module minicpu (
	output wire [`AddrBus] ram_addr,
	output wire [`DataBus] ram_d_in,
	input  wire [`DataBus] ram_d_out,
	output reg ram_rd_, ram_wr_,

	output wire [`AddrBus] rom_addr,
	input  wire [`Rom_Bus] rom_data,

	input  wire clk,
	input  wire rst_
);
	reg  [`AddrBus] valP;
	wire [`DataBus] valA, valB, valE;
	reg  [2:0] dstM, dstE;
	reg  [`DataBus] aluB;
	reg  [`DataBus] aluA;
	reg  [2:0] regA;
	reg  [2:0] regB;
	reg  [3:0] op;
	wire [1:0] cc;
	reg  [`AddrBus] new_pc;	
	

	PC PC (
	.new_pc (new_pc),
	.pc     (rom_addr),
	.clk    (clk),
	.rst_   (rst_)
	);
	
	always @(*) begin
		valP = rom_addr + ((`ins==`HLT)? 0: (`ins==`NOP||`ins==`RET)? 1: 3);

		dstM = (`ins==`POP)? `rA : (`ins==`LD )? `rB: `R0;

		dstE = (`ins==`PUSH||`ins==`POP||`ins==`CALL||`ins==`RET)? `RSP : (`ins==`OPR)? `rC: (`ins==`OPI||`ins==`IRMOV||`ins==`RRMOV)? `rB: `R0;
		end


	regfile regfile (
	.srcA ((`ins==`POP||`ins==`RET)? `RSP:`rA),
	.srcB ( (`ins==`PUSH||`ins==`POP||`ins==`CALL||`ins==`RET)? `RSP:`rB ),
	.valA (valA),
	.valB (valB),
	.dstM (dstM),
	.dstE (dstE),	
	.valM (ram_d_out),
	.valE (valE),
	.clk  (clk),
	.we_  (~rst_)
	);

	always @(*) begin
		aluB = (`ins==`RRMOV)? valA:(`ins==`LD||`ins==`ST||`ins==`OPI||{`ins, `fun}=={`JMP, `BNG}||`ins==`IRMOV||`ins==`RMMOV)? `valC: valB;
		op = (`ins==`POP||`ins==`RET)? 4'h4 : (`ins==`PUSH||`ins==`CALL)? 4'h3: (`ins==`IRMOV||`ins==`RMMOV||`ins==`RRMOV)? `ADD : (`ins==`OPR||`ins==`OPI)? `fun : (`ins==`JMP&&`fun!=`BNG)? `SUB: `ADD;
		end



	ALU ALU (
    .A  ((`ins==`RRMOV)? 8'h0: (`ins==`RMMOV) ? valB : valA),
    .B  (aluB),
    .E  (valE),
	.op (op),
    .cc (cc)
	);

	assign ram_addr = (`ins==`POP||`ins==`RET) ? valA : valE;
	assign ram_d_in = (`ins==`CALL)? valP:(`ins==`RMMOV||`ins==`PUSH)? valA : valB;

	always @(*) begin
		ram_rd_ = (`ins==`LD||`ins==`POP||`ins==`RET)? `ENABLE_: `DISABLE_;
		ram_wr_ = (rst_&& (`ins==`ST||`ins==`PUSH||`ins==`RMMOV||`ins==`CALL))? `ENABLE_: `DISABLE_;
		end
		
	always @(*) begin
		new_pc = (`ins==`CALL)? `valC: (`ins==`RET)? ram_d_out:valP;
		if(`ins==`CALL) begin
			$write("----------!!CALL: %x\n",`valC);
		end
		if(`ins==`RET) begin
			$write("----------!!RET: %x\n",ram_d_out);
		end
		case ({`ins, `fun})
			{`JMP, `BNG} : new_pc = valE;
			{`JMP, `BEQ} : if( cc[1:1]) new_pc = `valC;
			{`JMP, `BNE} : if(~cc[1:1]) new_pc = `valC;
			{`JMP, `BLT} : if(~cc[1:1]&~cc[0:0]) new_pc = `valC;
			{`JMP, `BGT} : if(~cc[1:1]& cc[0:0]) new_pc = `valC;
			{`JMP, `BLE} : if( cc[1:1]|~cc[0:0]) new_pc = `valC;
			{`JMP, `BGE} : if( cc[1:1]| cc[0:0]) new_pc = `valC;
			endcase
		end
endmodule
module minicpu (
	output wire [`AddrBus] ram_addr,
	output wire [`DataBus] ram_d_in,
	input  wire [`DataBus] ram_d_out,
	output reg ram_rd_, ram_wr_,

	output wire [`AddrBus] rom_addr,
	input  wire [`Rom_Bus] rom_data,

	input  wire clk,
	input  wire rst_
);

	reg  [`AddrBus] valP;
	wire [`DataBus] valA, valB, valE;
	reg  [2:0] dstM, dstE;
	reg  [`DataBus] aluB;
	reg  [`DataBus] aluA;
	reg  [2:0] regA;
	reg  [2:0] regB;
	reg  [3:0] op;
	wire [1:0] cc;
	reg  [`AddrBus] new_pc;	
	

	PC PC (
	.new_pc (new_pc),
	.pc     (rom_addr),
	.clk    (clk),
	.rst_   (rst_)
	);
	
	always @(*) begin
		valP = rom_addr + ((`ins==`HLT)? 0: (`ins==`NOP||`ins==`RET)? 1: 3);

		dstM = (`ins==`POP)? `rA : (`ins==`LD )? `rB: `R0;

		dstE = (`ins==`PUSH||`ins==`POP||`ins==`CALL||`ins==`RET)? `RSP : (`ins==`OPR)? `rC: (`ins==`OPI||`ins==`IRMOV||`ins==`RRMOV)? `rB: `R0;
		end


	regfile regfile (
	.srcA ((`ins==`POP||`ins==`RET)? `RSP:`rA),
	.srcB ( (`ins==`PUSH||`ins==`POP||`ins==`CALL||`ins==`RET)? `RSP:`rB ),
	.valA (valA),
	.valB (valB),
	.dstM (dstM),
	.dstE (dstE),	
	.valM (ram_d_out),
	.valE (valE),
	.clk  (clk),
	.we_  (~rst_)
	);

	always @(*) begin
		aluB = (`ins==`RRMOV)? valA:(`ins==`LD||`ins==`ST||`ins==`OPI||{`ins, `fun}=={`JMP, `BNG}||`ins==`IRMOV||`ins==`RMMOV)? `valC: valB;
		op = (`ins==`POP||`ins==`RET)? 4'h4 : (`ins==`PUSH||`ins==`CALL)? 4'h3: (`ins==`IRMOV||`ins==`RMMOV||`ins==`RRMOV)? `ADD : (`ins==`OPR||`ins==`OPI)? `fun : (`ins==`JMP&&`fun!=`BNG)? `SUB: `ADD;
		end



	ALU ALU (
    .A  ((`ins==`RRMOV)? 8'h0: (`ins==`RMMOV) ? valB : valA),
    .B  (aluB),
    .E  (valE),
	.op (op),
    .cc (cc)
	);

	assign ram_addr = (`ins==`POP||`ins==`RET) ? valA : valE;
	assign ram_d_in = (`ins==`CALL)? valP:(`ins==`RMMOV||`ins==`PUSH)? valA : valB;

	always @(*) begin
		ram_rd_ = (`ins==`LD||`ins==`POP||`ins==`RET)? `ENABLE_: `DISABLE_;
		ram_wr_ = (rst_&& (`ins==`ST||`ins==`PUSH||`ins==`RMMOV||`ins==`CALL))? `ENABLE_: `DISABLE_;
		end
		
	always @(*) begin
		new_pc = (`ins==`CALL)? `valC: (`ins==`RET)? ram_d_out:valP;
		if(`ins==`CALL) begin
			$write("----------!!CALL: %x\n",`valC);
		end
		if(`ins==`RET) begin
			$write("----------!!RET: %x\n",ram_d_out);
		end
		case ({`ins, `fun})
			{`JMP, `BNG} : new_pc = valE;
			{`JMP, `BEQ} : if( cc[1:1]) new_pc = `valC;
			{`JMP, `BNE} : if(~cc[1:1]) new_pc = `valC;
			{`JMP, `BLT} : if(~cc[1:1]&~cc[0:0]) new_pc = `valC;
			{`JMP, `BGT} : if(~cc[1:1]& cc[0:0]) new_pc = `valC;
			{`JMP, `BLE} : if( cc[1:1]|~cc[0:0]) new_pc = `valC;
			{`JMP, `BGE} : if( cc[1:1]| cc[0:0]) new_pc = `valC;
			endcase
		end
endmodule