data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/shift/mux2x1.v
data/verilator_xmls/c29bcbbd-2ca5-4fb9-ac88-541204ceeddb.xml
module mux2x1(
    input in0,
    input in1,
    input sel,
    output out
);

    assign out = (sel)?in1:in0;

endmodule
module mux2x1(
    input in0,
    input in1,
    input sel,
    output out
);


    assign out = (sel)?in1:in0;

endmodule