data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_packet_demux36.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_packet_demux36.v:70: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                            : ... In instance vita_packet_demux36\n                sid <= in_data[31:0] - SID_BASE;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module vita_packet_demux36
#(
    parameter NUMCHAN = 1,
    parameter SID_BASE = 0
)
(
    input clk, input rst,

    input [35:0] in_data,
    input in_src_rdy,
    output in_dst_rdy,

    output [35:0] out_data,
    output [NUMCHAN-1:0] out_src_rdy,
    input [NUMCHAN-1:0] out_dst_rdy
);

    reg [1:0] state;
    localparam STATE_WAIT_HDR = 0;
    localparam STATE_PROC_SID = 1;
    localparam STATE_WRITE_HDR = 2;
    localparam STATE_FORWARD = 3;

    reg [31:0] hdr;
    reg [NUMCHAN-1:0] sid;
    wire has_sid = in_data[28];
    reg has_sid_reg;

    wire my_out_dst_rdy = out_dst_rdy[sid];
    wire my_out_src_rdy = out_src_rdy[sid];

    always @(posedge clk) begin
        if (rst) begin
            state <= STATE_WAIT_HDR;
        end
        else case(state)

        STATE_WAIT_HDR: begin
            if (in_src_rdy && in_dst_rdy && in_data[32]) begin
                state <= (has_sid)? STATE_PROC_SID : STATE_WRITE_HDR;
            end
            sid <= 0;
            hdr <= in_data[31:0];
            has_sid_reg <= has_sid;
        end

        STATE_PROC_SID: begin
            if (in_src_rdy && in_dst_rdy) begin
                state <= STATE_WRITE_HDR;
                sid <= in_data[31:0] - SID_BASE;
                hdr[28] <= 1'b0;
                hdr[15:0] <= hdr[15:0] - 1'b1;
            end
        end

        STATE_WRITE_HDR: begin
            if (my_out_src_rdy && my_out_dst_rdy) begin
                state <= STATE_FORWARD;
            end
        end

        STATE_FORWARD: begin
            if (my_out_src_rdy && my_out_dst_rdy && out_data[33]) begin
                state <= STATE_WAIT_HDR;
            end
        end

        endcase
    end

    assign out_data = (state == STATE_WRITE_HDR)? {4'b0001, hdr} : in_data;
    wire out_src_rdy_i = (state == STATE_WRITE_HDR)? 1'b1 : ((state == STATE_FORWARD)? in_src_rdy : 1'b0);
    assign in_dst_rdy = (state == STATE_WAIT_HDR || state == STATE_PROC_SID)? 1'b1 : ((state == STATE_FORWARD)? my_out_dst_rdy : 1'b0);

    genvar i;
    generate
    for(i = 0; i < NUMCHAN; i = i + 1) begin:valid_assign
        assign out_src_rdy[i] = (i == sid)? out_src_rdy_i : 1'b0;
    end
    endgenerate

endmodule
module vita_packet_demux36
#(
    parameter NUMCHAN = 1,
    parameter SID_BASE = 0
)
(
    input clk, input rst,

    input [35:0] in_data,
    input in_src_rdy,
    output in_dst_rdy,

    output [35:0] out_data,
    output [NUMCHAN-1:0] out_src_rdy,
    input [NUMCHAN-1:0] out_dst_rdy
);


    reg [1:0] state;
    localparam STATE_WAIT_HDR = 0;
    localparam STATE_PROC_SID = 1;
    localparam STATE_WRITE_HDR = 2;
    localparam STATE_FORWARD = 3;

    reg [31:0] hdr;
    reg [NUMCHAN-1:0] sid;
    wire has_sid = in_data[28];
    reg has_sid_reg;

    wire my_out_dst_rdy = out_dst_rdy[sid];
    wire my_out_src_rdy = out_src_rdy[sid];

    always @(posedge clk) begin
        if (rst) begin
            state <= STATE_WAIT_HDR;
        end
        else case(state)

        STATE_WAIT_HDR: begin
            if (in_src_rdy && in_dst_rdy && in_data[32]) begin
                state <= (has_sid)? STATE_PROC_SID : STATE_WRITE_HDR;
            end
            sid <= 0;
            hdr <= in_data[31:0];
            has_sid_reg <= has_sid;
        end

        STATE_PROC_SID: begin
            if (in_src_rdy && in_dst_rdy) begin
                state <= STATE_WRITE_HDR;
                sid <= in_data[31:0] - SID_BASE;
                hdr[28] <= 1'b0;
                hdr[15:0] <= hdr[15:0] - 1'b1;
            end
        end

        STATE_WRITE_HDR: begin
            if (my_out_src_rdy && my_out_dst_rdy) begin
                state <= STATE_FORWARD;
            end
        end

        STATE_FORWARD: begin
            if (my_out_src_rdy && my_out_dst_rdy && out_data[33]) begin
                state <= STATE_WAIT_HDR;
            end
        end

        endcase
    end

    assign out_data = (state == STATE_WRITE_HDR)? {4'b0001, hdr} : in_data;
    wire out_src_rdy_i = (state == STATE_WRITE_HDR)? 1'b1 : ((state == STATE_FORWARD)? in_src_rdy : 1'b0);
    assign in_dst_rdy = (state == STATE_WAIT_HDR || state == STATE_PROC_SID)? 1'b1 : ((state == STATE_FORWARD)? my_out_dst_rdy : 1'b0);

    genvar i;
    generate
    for(i = 0; i < NUMCHAN; i = i + 1) begin:valid_assign
        assign out_src_rdy[i] = (i == sid)? out_src_rdy_i : 1'b0;
    end
    endgenerate

endmodule