data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v:84: Operator XOR expects 2 bits on the RHS, but RHS\'s VARREF \'temp3\' generates 1 bits.\n                                                                                                                                    : ... In instance bm_dag3_lpm_log_mod.top_b\n temp2 <= seventh | eight ^ temp3;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module a(clock,
		fifth,
		sixth,
		out2);

input	clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0]    out2;
reg [`BITS-1:0]    out2;
wire [`BITS-1:0] temp1;

d mya_d(clock, fifth[0], sixth[0], temp1[0]);
d mya_d2(clock, fifth[0], sixth[1], temp1[1]);

always @(posedge clock)
begin
	out2 <= fifth & sixth & temp1;
end

endmodule
module a(clock,
		fifth,
		sixth,
		out2);


input	clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0]    out2;
reg [`BITS-1:0]    out2;
wire [`BITS-1:0] temp1;

d mya_d(clock, fifth[0], sixth[0], temp1[0]);
d mya_d2(clock, fifth[0], sixth[1], temp1[1]);

always @(posedge clock)
begin
	out2 <= fifth & sixth & temp1;
end

endmodule