data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v:119: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE_1,ADDR_WIDTH) ram0(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.sv\n             fpga_ram\n             fpga_ram.v\n             fpga_ram.sv\n             obj_dir/fpga_ram\n             obj_dir/fpga_ram.v\n             obj_dir/fpga_ram.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v:126: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram1(\n^~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v:133: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram2(\n^~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v:140: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram3(\n^~~~~~~~\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x196.v:147: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram4(\n^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ct_f_spsram_256x196(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);


input   [7  :0]  A;           
input            CEN;         
input            CLK;         
input   [195:0]  D;           
input            GWEN;        
input   [195:0]  WEN;         
output  [195:0]  Q;           


reg     [7  :0]  addr_holding; 


wire    [7  :0]  A;           
wire             CEN;         
wire             CLK;         
wire    [195:0]  D;           
wire             GWEN;        
wire    [195:0]  Q;           
wire    [195:0]  WEN;         
wire    [7  :0]  addr;        
wire    [3  :0]  ram0_din;    
wire    [3  :0]  ram0_dout;   
wire             ram0_wen;    
wire    [47 :0]  ram1_din;    
wire    [47 :0]  ram1_dout;   
wire             ram1_wen;    
wire    [47 :0]  ram2_din;    
wire    [47 :0]  ram2_dout;   
wire             ram2_wen;    
wire    [47 :0]  ram3_din;    
wire    [47 :0]  ram3_dout;   
wire             ram3_wen;    
wire    [47 :0]  ram4_din;    
wire    [47 :0]  ram4_dout;   
wire             ram4_wen;    


parameter ADDR_WIDTH   = 8;
parameter WRAP_SIZE_1  = 4;
parameter WRAP_SIZE_2  = 48;








assign ram0_wen = !CEN && !WEN[195] && !GWEN;
assign ram1_wen = !CEN && !WEN[191] && !GWEN;
assign ram2_wen = !CEN && !WEN[143] && !GWEN;
assign ram3_wen = !CEN && !WEN[ 95] && !GWEN;
assign ram4_wen = !CEN && !WEN[ 47] && !GWEN;








assign ram0_din[WRAP_SIZE_1-1:0] = D[WRAP_SIZE_1+4*WRAP_SIZE_2-1:4*WRAP_SIZE_2];
assign ram1_din[WRAP_SIZE_2-1:0] = D[4*WRAP_SIZE_2-1:3*WRAP_SIZE_2];
assign ram2_din[WRAP_SIZE_2-1:0] = D[3*WRAP_SIZE_2-1:2*WRAP_SIZE_2];
assign ram3_din[WRAP_SIZE_2-1:0] = D[2*WRAP_SIZE_2-1:1*WRAP_SIZE_2];
assign ram4_din[WRAP_SIZE_2-1:0] = D[1*WRAP_SIZE_2-1:0*WRAP_SIZE_2];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];







assign Q[WRAP_SIZE_1+4*WRAP_SIZE_2-1:4*WRAP_SIZE_2] = ram0_dout[WRAP_SIZE_1-1:0];
assign Q[4*WRAP_SIZE_2-1:3*WRAP_SIZE_2]             = ram1_dout[WRAP_SIZE_2-1:0];
assign Q[3*WRAP_SIZE_2-1:2*WRAP_SIZE_2]             = ram2_dout[WRAP_SIZE_2-1:0];
assign Q[2*WRAP_SIZE_2-1:1*WRAP_SIZE_2]             = ram3_dout[WRAP_SIZE_2-1:0];
assign Q[1*WRAP_SIZE_2-1:0*WRAP_SIZE_2]             = ram4_dout[WRAP_SIZE_2-1:0];


fpga_ram #(WRAP_SIZE_1,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram1_din),
  .PortAWriteEnable(ram1_wen),
  .PortADataOut(ram1_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram2(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram2_din),
  .PortAWriteEnable(ram2_wen),
  .PortADataOut(ram2_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram3(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram3_din),
  .PortAWriteEnable(ram3_wen),
  .PortADataOut(ram3_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram4(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram4_din),
  .PortAWriteEnable(ram4_wen),
  .PortADataOut(ram4_dout));


endmodule
module ct_f_spsram_256x196(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);



input   [7  :0]  A;           
input            CEN;         
input            CLK;         
input   [195:0]  D;           
input            GWEN;        
input   [195:0]  WEN;         
output  [195:0]  Q;           


reg     [7  :0]  addr_holding; 


wire    [7  :0]  A;           
wire             CEN;         
wire             CLK;         
wire    [195:0]  D;           
wire             GWEN;        
wire    [195:0]  Q;           
wire    [195:0]  WEN;         
wire    [7  :0]  addr;        
wire    [3  :0]  ram0_din;    
wire    [3  :0]  ram0_dout;   
wire             ram0_wen;    
wire    [47 :0]  ram1_din;    
wire    [47 :0]  ram1_dout;   
wire             ram1_wen;    
wire    [47 :0]  ram2_din;    
wire    [47 :0]  ram2_dout;   
wire             ram2_wen;    
wire    [47 :0]  ram3_din;    
wire    [47 :0]  ram3_dout;   
wire             ram3_wen;    
wire    [47 :0]  ram4_din;    
wire    [47 :0]  ram4_dout;   
wire             ram4_wen;    


parameter ADDR_WIDTH   = 8;
parameter WRAP_SIZE_1  = 4;
parameter WRAP_SIZE_2  = 48;








assign ram0_wen = !CEN && !WEN[195] && !GWEN;
assign ram1_wen = !CEN && !WEN[191] && !GWEN;
assign ram2_wen = !CEN && !WEN[143] && !GWEN;
assign ram3_wen = !CEN && !WEN[ 95] && !GWEN;
assign ram4_wen = !CEN && !WEN[ 47] && !GWEN;








assign ram0_din[WRAP_SIZE_1-1:0] = D[WRAP_SIZE_1+4*WRAP_SIZE_2-1:4*WRAP_SIZE_2];
assign ram1_din[WRAP_SIZE_2-1:0] = D[4*WRAP_SIZE_2-1:3*WRAP_SIZE_2];
assign ram2_din[WRAP_SIZE_2-1:0] = D[3*WRAP_SIZE_2-1:2*WRAP_SIZE_2];
assign ram3_din[WRAP_SIZE_2-1:0] = D[2*WRAP_SIZE_2-1:1*WRAP_SIZE_2];
assign ram4_din[WRAP_SIZE_2-1:0] = D[1*WRAP_SIZE_2-1:0*WRAP_SIZE_2];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];







assign Q[WRAP_SIZE_1+4*WRAP_SIZE_2-1:4*WRAP_SIZE_2] = ram0_dout[WRAP_SIZE_1-1:0];
assign Q[4*WRAP_SIZE_2-1:3*WRAP_SIZE_2]             = ram1_dout[WRAP_SIZE_2-1:0];
assign Q[3*WRAP_SIZE_2-1:2*WRAP_SIZE_2]             = ram2_dout[WRAP_SIZE_2-1:0];
assign Q[2*WRAP_SIZE_2-1:1*WRAP_SIZE_2]             = ram3_dout[WRAP_SIZE_2-1:0];
assign Q[1*WRAP_SIZE_2-1:0*WRAP_SIZE_2]             = ram4_dout[WRAP_SIZE_2-1:0];


fpga_ram #(WRAP_SIZE_1,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram1_din),
  .PortAWriteEnable(ram1_wen),
  .PortADataOut(ram1_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram2(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram2_din),
  .PortAWriteEnable(ram2_wen),
  .PortADataOut(ram2_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram3(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram3_din),
  .PortAWriteEnable(ram3_wen),
  .PortADataOut(ram3_dout));

fpga_ram #(WRAP_SIZE_2,ADDR_WIDTH) ram4(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram4_din),
  .PortAWriteEnable(ram4_wen),
  .PortADataOut(ram4_dout));


endmodule