data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:197: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'Y_Cont\' generates 16 bits.\n                                                                                                          : ... In instance DE0_D5M\nassign LEDG     = Y_Cont;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:208: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                                                          : ... In instance DE0_D5M\nassign VGA_R  = oVGA_R[9:0];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:209: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                                                          : ... In instance DE0_D5M\nassign VGA_G  = oVGA_G[9:0];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:210: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                                                          : ... In instance DE0_D5M\nassign VGA_B  = oVGA_B[9:0];\n              ^\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:232: Cannot find file containing module: \'VGA_Controller\'\nVGA_Controller  u1 (  \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE,data/full_repos/permissive/52881156/VGA_Controller\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE,data/full_repos/permissive/52881156/VGA_Controller.v\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE,data/full_repos/permissive/52881156/VGA_Controller.sv\n             VGA_Controller\n             VGA_Controller.v\n             VGA_Controller.sv\n             obj_dir/VGA_Controller\n             obj_dir/VGA_Controller.v\n             obj_dir/VGA_Controller.sv\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:256: Cannot find file containing module: \'Reset_Delay\'\nReset_Delay   u2 ( \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:264: Cannot find file containing module: \'CCD_Capture\'\nCCD_Capture   u3 ( \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:279: Cannot find file containing module: \'RAW2RGB\'\nRAW2RGB    u4 ( \n^~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:292: Cannot find file containing module: \'SEG7_LUT_8\'\nSEG7_LUT_8    u5 ( \n^~~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:304: Cannot find file containing module: \'sdram_pll\'\nsdram_pll    u6 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:312: Cannot find file containing module: \'Sdram_Control_4Port\'\nSdram_Control_4Port u7 (  \n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v:368: Cannot find file containing module: \'I2C_CCD_Config\'\nI2C_CCD_Config   u8 (  \n^~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 4 warning(s)\n'
module DE0_D5M
	(

		CLOCK_50,

		KEY,



		LEDG,

		HEX0,
		HEX1,
		HEX2,
		HEX3,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,
		VGA_CLK,
		VGA_X,
		VGA_Y,
		VGA_ACTIVE,


		GPIO_1_CLKIN,
		GPIO_1_CLKOUT,
		GPIO_1
	);


input			CLOCK_50;

input	[2:0]	KEY;



output	[9:0]	LEDG;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;

inout	[15:0]	DRAM_DQ;
output[11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;
output         VGA_CLK;
output	[11:0]		VGA_X;
output	[11:0]		VGA_Y;
output         VGA_ACTIVE;


input	[1:0]	   GPIO_1_CLKIN;
output [1:0]	GPIO_1_CLKOUT;
inout	[31:0]	GPIO_1;






wire	[11:0]	CCD_DATA;
wire				CCD_SDAT;
wire				CCD_SCLK;
wire				CCD_FLASH;
wire				CCD_FVAL;
wire				CCD_LVAL;
wire				CCD_PIXCLK;
wire				CCD_MCLK;

wire	[15:0]	Read_DATA1;
wire	[15:0]	Read_DATA2;
wire				VGA_CTRL_CLK;
wire	[11:0]	mCCD_DATA;
wire				mCCD_DVAL;
wire				mCCD_DVAL_d;
wire	[15:0]	X_Cont;
wire	[15:0]	Y_Cont;
wire	[9:0]		X_ADDR;
wire	[31:0]	Frame_Cont;
wire				DLY_RST_0;
wire				DLY_RST_1;
wire				DLY_RST_2;
wire				Read;
reg	[11:0]	rCCD_DATA;
reg				rCCD_LVAL;
reg				rCCD_FVAL;
wire	[11:0]	sCCD_R;
wire	[11:0]	sCCD_G;
wire	[11:0]	sCCD_B;
wire				sCCD_DVAL;
wire	[9:0]		VGA_R;
wire	[9:0]		VGA_G;
wire	[9:0]		VGA_B;
wire	[11:0]		VGA_X;
wire	[11:0]		VGA_Y;
wire				VGA_ACTIVE;
reg	[1:0]		rClk;
wire				sdram_ctrl_clk;




assign	CCD_DATA[0]	=	GPIO_1[11];
assign	CCD_DATA[1]	=	GPIO_1[10];
assign	CCD_DATA[2]	=	GPIO_1[9];
assign	CCD_DATA[3]	=	GPIO_1[8];
assign	CCD_DATA[4]	=	GPIO_1[7];
assign	CCD_DATA[5]	=	GPIO_1[6];
assign	CCD_DATA[6]	=	GPIO_1[5];
assign	CCD_DATA[7]	=	GPIO_1[4];
assign	CCD_DATA[8]	=	GPIO_1[3];
assign	CCD_DATA[9]	=	GPIO_1[2];
assign	CCD_DATA[10]=	GPIO_1[1];
assign	CCD_DATA[11]=	GPIO_1[0];
assign	GPIO_1_CLKOUT[0]	= CLOCK_50;
assign	CCD_FVAL	   =	GPIO_1[18];
assign	CCD_LVAL	   =	GPIO_1[17];
assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
assign	GPIO_1[15]	=	1'b1;
assign	GPIO_1[14]	=	DLY_RST_1;

assign	LEDG		   =	Y_Cont;

assign	VGA_CTRL_CLK=	rClk[0];
assign	VGA_CLK		=	~rClk[0];

always@(posedge CLOCK_50)	rClk	<=	rClk+1;


wire	[9:0]	oVGA_R;
wire	[9:0]	oVGA_G;
wire	[9:0]	oVGA_B;
assign	VGA_R		=	oVGA_R[9:0];
assign	VGA_G		=	oVGA_G[9:0];
assign	VGA_B		=	oVGA_B[9:0];


wire	[11:0]	oVGA_X;
wire	[11:0]	oVGA_Y;
assign	VGA_X		=	oVGA_Y;
assign	VGA_Y		=	oVGA_X;


wire 	oVGA_ACTIVE;
assign VGA_ACTIVE = oVGA_ACTIVE;




always@(posedge CCD_PIXCLK)
begin
	rCCD_DATA	<=	CCD_DATA;
	rCCD_LVAL	<=	CCD_LVAL;
	rCCD_FVAL	<=	CCD_FVAL;
end

VGA_Controller		u1	(
							.oRequest   (Read),



							.iRed       (Read_DATA2[9:0]),
							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
							.iBlue      (Read_DATA1[9:0]),

							.oVGA_R     (oVGA_R),
							.oVGA_G     (oVGA_G),
							.oVGA_B     (oVGA_B),
							.oVGA_H_SYNC(VGA_HS),
							.oVGA_V_SYNC(VGA_VS),

							.oVGA_X(oVGA_X),
							.oVGA_Y(oVGA_Y),
							.oVGA_ACTIVE(oVGA_ACTIVE),

							.iCLK       (VGA_CTRL_CLK),
							.iRST_N     (DLY_RST_2)
						);


Reset_Delay			u2	(	
							.iCLK  (CLOCK_50),
							.iRST  (KEY[0]),
							.oRST_0(DLY_RST_0),
							.oRST_1(DLY_RST_1),
							.oRST_2(DLY_RST_2)
						);

CCD_Capture			u3	(	
							.oDATA      (mCCD_DATA),
							.oDVAL      (mCCD_DVAL),
							.oX_Cont    (X_Cont),
							.oY_Cont    (Y_Cont),
							.oFrame_Cont(Frame_Cont),
							.iDATA      (rCCD_DATA),
							.iFVAL      (rCCD_FVAL),
							.iLVAL      (rCCD_LVAL),
							.iSTART     (!KEY[1]),
							.iEND       (!KEY[2]),
							.iCLK       (CCD_PIXCLK),
							.iRST       (DLY_RST_2)
						);

RAW2RGB				u4	(	
						   .iCLK   (CCD_PIXCLK),
							.iRST   (DLY_RST_1),
							.iDATA  (mCCD_DATA),
							.iDVAL  (mCCD_DVAL),
							.oRed   (sCCD_R),
							.oGreen (sCCD_G),
							.oBlue  (sCCD_B),
							.oDVAL  (sCCD_DVAL),
							.iX_Cont(X_Cont),
							.iY_Cont(Y_Cont)
						);

SEG7_LUT_8 			u5	(	
							.oSEG0(HEX0),
							.oSEG1(HEX1),
							.oSEG2(HEX2),
							.oSEG3(HEX3),
							.oSEG4(),
							.oSEG5(),
							.oSEG6(),
							.oSEG7(),
							.iDIG (Frame_Cont[31:0])
						);

sdram_pll 			u6	(
							.inclk0(CLOCK_50),
							.c0    (sdram_ctrl_clk),
							.c1    (DRAM_CLK)
						);

assign CCD_MCLK = rClk[0];

Sdram_Control_4Port	u7	(
								 .REF_CLK     (CLOCK_50),
						       .RESET_N     (1'b1),
							    .CLK    	  (sdram_ctrl_clk),


							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
							    .WR1     	  (sCCD_DVAL),
								 .WR1_ADDR	  (0),
								 .WR1_MAX_ADDR(640*480),
								 .WR1_LENGTH  (9'h100),
								 .WR1_LOAD	  (!DLY_RST_0),
								 .WR1_CLK	  (~CCD_PIXCLK),


								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
								 .WR2			  (sCCD_DVAL),
								 .WR2_ADDR    (22'h100000),
								 .WR2_MAX_ADDR(22'h100000+640*480),
								 .WR2_LENGTH  (9'h100),
								 .WR2_LOAD    (!DLY_RST_0),
								 .WR2_CLK     (~CCD_PIXCLK),



						       .RD1_DATA	  (Read_DATA1),
								 .RD1			  (Read),
				        	    .RD1_ADDR    (0),
								 .RD1_MAX_ADDR(640*480),
								 .RD1_LENGTH  (9'h100),
								 .RD1_LOAD	  (!DLY_RST_0),
								 .RD1_CLK	  (~VGA_CTRL_CLK),
							

						       .RD2_DATA	  (Read_DATA2),
								 .RD2         (Read),
								 .RD2_ADDR    (22'h100000),
								 .RD2_MAX_ADDR(22'h100000+640*480),
								 .RD2_LENGTH  (9'h100),
								 .RD2_LOAD    (!DLY_RST_0),
								 .RD2_CLK     (~VGA_CTRL_CLK),
							

						       .SA			  (DRAM_ADDR),
						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
								 .CS_N		  (DRAM_CS_N),
        					    .CKE			  (DRAM_CKE),
								 .RAS_N		  (DRAM_RAS_N),
								 .CAS_N		  (DRAM_CAS_N),
								 .WE_N		  (DRAM_WE_N),
								 .DQ			  (DRAM_DQ),
								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
						       );



I2C_CCD_Config 		u8	(
								 .iCLK			  (CLOCK_50),
								 .iRST_N         (DLY_RST_2),
								 .iZOOM_MODE_SW  (0),
								 .iEXPOSURE_ADJ  (1),
								 .iEXPOSURE_DEC_p(1),

								 .I2C_SCLK		  (GPIO_1[20]),
								 .I2C_SDAT		  (GPIO_1[19])
							   );

endmodule
module DE0_D5M
	(

		CLOCK_50,

		KEY,



		LEDG,

		HEX0,
		HEX1,
		HEX2,
		HEX3,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,
		VGA_CLK,
		VGA_X,
		VGA_Y,
		VGA_ACTIVE,


		GPIO_1_CLKIN,
		GPIO_1_CLKOUT,
		GPIO_1
	);



input			CLOCK_50;

input	[2:0]	KEY;



output	[9:0]	LEDG;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;

inout	[15:0]	DRAM_DQ;
output[11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;
output         VGA_CLK;
output	[11:0]		VGA_X;
output	[11:0]		VGA_Y;
output         VGA_ACTIVE;


input	[1:0]	   GPIO_1_CLKIN;
output [1:0]	GPIO_1_CLKOUT;
inout	[31:0]	GPIO_1;






wire	[11:0]	CCD_DATA;
wire				CCD_SDAT;
wire				CCD_SCLK;
wire				CCD_FLASH;
wire				CCD_FVAL;
wire				CCD_LVAL;
wire				CCD_PIXCLK;
wire				CCD_MCLK;

wire	[15:0]	Read_DATA1;
wire	[15:0]	Read_DATA2;
wire				VGA_CTRL_CLK;
wire	[11:0]	mCCD_DATA;
wire				mCCD_DVAL;
wire				mCCD_DVAL_d;
wire	[15:0]	X_Cont;
wire	[15:0]	Y_Cont;
wire	[9:0]		X_ADDR;
wire	[31:0]	Frame_Cont;
wire				DLY_RST_0;
wire				DLY_RST_1;
wire				DLY_RST_2;
wire				Read;
reg	[11:0]	rCCD_DATA;
reg				rCCD_LVAL;
reg				rCCD_FVAL;
wire	[11:0]	sCCD_R;
wire	[11:0]	sCCD_G;
wire	[11:0]	sCCD_B;
wire				sCCD_DVAL;
wire	[9:0]		VGA_R;
wire	[9:0]		VGA_G;
wire	[9:0]		VGA_B;
wire	[11:0]		VGA_X;
wire	[11:0]		VGA_Y;
wire				VGA_ACTIVE;
reg	[1:0]		rClk;
wire				sdram_ctrl_clk;




assign	CCD_DATA[0]	=	GPIO_1[11];
assign	CCD_DATA[1]	=	GPIO_1[10];
assign	CCD_DATA[2]	=	GPIO_1[9];
assign	CCD_DATA[3]	=	GPIO_1[8];
assign	CCD_DATA[4]	=	GPIO_1[7];
assign	CCD_DATA[5]	=	GPIO_1[6];
assign	CCD_DATA[6]	=	GPIO_1[5];
assign	CCD_DATA[7]	=	GPIO_1[4];
assign	CCD_DATA[8]	=	GPIO_1[3];
assign	CCD_DATA[9]	=	GPIO_1[2];
assign	CCD_DATA[10]=	GPIO_1[1];
assign	CCD_DATA[11]=	GPIO_1[0];
assign	GPIO_1_CLKOUT[0]	= CLOCK_50;
assign	CCD_FVAL	   =	GPIO_1[18];
assign	CCD_LVAL	   =	GPIO_1[17];
assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
assign	GPIO_1[15]	=	1'b1;
assign	GPIO_1[14]	=	DLY_RST_1;

assign	LEDG		   =	Y_Cont;

assign	VGA_CTRL_CLK=	rClk[0];
assign	VGA_CLK		=	~rClk[0];

always@(posedge CLOCK_50)	rClk	<=	rClk+1;


wire	[9:0]	oVGA_R;
wire	[9:0]	oVGA_G;
wire	[9:0]	oVGA_B;
assign	VGA_R		=	oVGA_R[9:0];
assign	VGA_G		=	oVGA_G[9:0];
assign	VGA_B		=	oVGA_B[9:0];


wire	[11:0]	oVGA_X;
wire	[11:0]	oVGA_Y;
assign	VGA_X		=	oVGA_Y;
assign	VGA_Y		=	oVGA_X;


wire 	oVGA_ACTIVE;
assign VGA_ACTIVE = oVGA_ACTIVE;




always@(posedge CCD_PIXCLK)
begin
	rCCD_DATA	<=	CCD_DATA;
	rCCD_LVAL	<=	CCD_LVAL;
	rCCD_FVAL	<=	CCD_FVAL;
end

VGA_Controller		u1	(
							.oRequest   (Read),



							.iRed       (Read_DATA2[9:0]),
							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
							.iBlue      (Read_DATA1[9:0]),

							.oVGA_R     (oVGA_R),
							.oVGA_G     (oVGA_G),
							.oVGA_B     (oVGA_B),
							.oVGA_H_SYNC(VGA_HS),
							.oVGA_V_SYNC(VGA_VS),

							.oVGA_X(oVGA_X),
							.oVGA_Y(oVGA_Y),
							.oVGA_ACTIVE(oVGA_ACTIVE),

							.iCLK       (VGA_CTRL_CLK),
							.iRST_N     (DLY_RST_2)
						);


Reset_Delay			u2	(	
							.iCLK  (CLOCK_50),
							.iRST  (KEY[0]),
							.oRST_0(DLY_RST_0),
							.oRST_1(DLY_RST_1),
							.oRST_2(DLY_RST_2)
						);

CCD_Capture			u3	(	
							.oDATA      (mCCD_DATA),
							.oDVAL      (mCCD_DVAL),
							.oX_Cont    (X_Cont),
							.oY_Cont    (Y_Cont),
							.oFrame_Cont(Frame_Cont),
							.iDATA      (rCCD_DATA),
							.iFVAL      (rCCD_FVAL),
							.iLVAL      (rCCD_LVAL),
							.iSTART     (!KEY[1]),
							.iEND       (!KEY[2]),
							.iCLK       (CCD_PIXCLK),
							.iRST       (DLY_RST_2)
						);

RAW2RGB				u4	(	
						   .iCLK   (CCD_PIXCLK),
							.iRST   (DLY_RST_1),
							.iDATA  (mCCD_DATA),
							.iDVAL  (mCCD_DVAL),
							.oRed   (sCCD_R),
							.oGreen (sCCD_G),
							.oBlue  (sCCD_B),
							.oDVAL  (sCCD_DVAL),
							.iX_Cont(X_Cont),
							.iY_Cont(Y_Cont)
						);

SEG7_LUT_8 			u5	(	
							.oSEG0(HEX0),
							.oSEG1(HEX1),
							.oSEG2(HEX2),
							.oSEG3(HEX3),
							.oSEG4(),
							.oSEG5(),
							.oSEG6(),
							.oSEG7(),
							.iDIG (Frame_Cont[31:0])
						);

sdram_pll 			u6	(
							.inclk0(CLOCK_50),
							.c0    (sdram_ctrl_clk),
							.c1    (DRAM_CLK)
						);

assign CCD_MCLK = rClk[0];

Sdram_Control_4Port	u7	(
								 .REF_CLK     (CLOCK_50),
						       .RESET_N     (1'b1),
							    .CLK    	  (sdram_ctrl_clk),


							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
							    .WR1     	  (sCCD_DVAL),
								 .WR1_ADDR	  (0),
								 .WR1_MAX_ADDR(640*480),
								 .WR1_LENGTH  (9'h100),
								 .WR1_LOAD	  (!DLY_RST_0),
								 .WR1_CLK	  (~CCD_PIXCLK),


								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
								 .WR2			  (sCCD_DVAL),
								 .WR2_ADDR    (22'h100000),
								 .WR2_MAX_ADDR(22'h100000+640*480),
								 .WR2_LENGTH  (9'h100),
								 .WR2_LOAD    (!DLY_RST_0),
								 .WR2_CLK     (~CCD_PIXCLK),



						       .RD1_DATA	  (Read_DATA1),
								 .RD1			  (Read),
				        	    .RD1_ADDR    (0),
								 .RD1_MAX_ADDR(640*480),
								 .RD1_LENGTH  (9'h100),
								 .RD1_LOAD	  (!DLY_RST_0),
								 .RD1_CLK	  (~VGA_CTRL_CLK),
							

						       .RD2_DATA	  (Read_DATA2),
								 .RD2         (Read),
								 .RD2_ADDR    (22'h100000),
								 .RD2_MAX_ADDR(22'h100000+640*480),
								 .RD2_LENGTH  (9'h100),
								 .RD2_LOAD    (!DLY_RST_0),
								 .RD2_CLK     (~VGA_CTRL_CLK),
							

						       .SA			  (DRAM_ADDR),
						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
								 .CS_N		  (DRAM_CS_N),
        					    .CKE			  (DRAM_CKE),
								 .RAS_N		  (DRAM_RAS_N),
								 .CAS_N		  (DRAM_CAS_N),
								 .WE_N		  (DRAM_WE_N),
								 .DQ			  (DRAM_DQ),
								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
						       );



I2C_CCD_Config 		u8	(
								 .iCLK			  (CLOCK_50),
								 .iRST_N         (DLY_RST_2),
								 .iZOOM_MODE_SW  (0),
								 .iEXPOSURE_ADJ  (1),
								 .iEXPOSURE_DEC_p(1),

								 .I2C_SCLK		  (GPIO_1[20]),
								 .I2C_SDAT		  (GPIO_1[19])
							   );

endmodule