data/full_repos/permissive/46804359/Shift_left2_26b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/46804359/Shift_left2_26b.v:10: Operator SHIFTL expects 28 bits on the LHS, but LHS\'s VARREF \'in\' generates 26 bits.\n                                                                        : ... In instance Shift_left2_26b\n        out <= in << 2;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Shift_left2_26b(in, out, clk);

    input wire [25:0] in;
    input wire clk;

    output reg [27:0] out;

    always@(posedge clk)
    begin
        out <= in << 2;
    end
endmodule
module Shift_left2_26b(in, out, clk);


    input wire [25:0] in;
    input wire clk;

    output reg [27:0] out;

    always@(posedge clk)
    begin
        out <= in << 2;
    end
endmodule