data/full_repos/permissive/469509877/rtl/V5.v
data/verilator_xmls/d5ed73b6-2a98-4c56-91c6-66002b1e9604.xml
module V5(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );
    
    assign Red[3] = ((~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & Hcount[0]) |
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & ~Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & ~Hcount[1] & Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & Hcount[1] & Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & Hcount[2] & ~Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & Hcount[2] & ~Hcount[1] & Hcount[0])) & 
                    ((Vcount[9] | Vcount[8] | Vcount[7] | Vcount[6] | Vcount[5] | Vcount[4] | Vcount[3]) & 
                    (~(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];  
    
endmodule
module V5(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );

    
    assign Red[3] = ((~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & Hcount[0]) |
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & ~Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & ~Hcount[1] & Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & ~Hcount[2] & Hcount[1] & Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & Hcount[2] & ~Hcount[1] & ~Hcount[0]) | 
                    (~Hcount[9] & Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & ~Hcount[4] & Hcount [3] & Hcount[2] & ~Hcount[1] & Hcount[0])) & 
                    ((Vcount[9] | Vcount[8] | Vcount[7] | Vcount[6] | Vcount[5] | Vcount[4] | Vcount[3]) & 
                    (~(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])));
    assign Red[2] = Red[3];  
    assign Red[1] = Red[3];
    assign Red[0] = Red[3];  
    
endmodule