data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:42: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'CC_IBUF\'\nmodule CC_IBUF #(\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_OBUF\'\nmodule CC_OBUF #(\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_TOBUF\'\nmodule CC_TOBUF #(\n       ^~~~~~~~\n                                                                                          : ... Top module \'CC_IOBUF\'\nmodule CC_IOBUF #(\n       ^~~~~~~~\n                                                                                          : ... Top module \'CC_LVDS_IBUF\'\nmodule CC_LVDS_IBUF #(\n       ^~~~~~~~~~~~\n                                                                                          : ... Top module \'CC_LVDS_OBUF\'\nmodule CC_LVDS_OBUF #(\n       ^~~~~~~~~~~~\n                                                                                          : ... Top module \'CC_LVDS_TOBUF\'\nmodule CC_LVDS_TOBUF #(\n       ^~~~~~~~~~~~~\n                                                                                          : ... Top module \'CC_LVDS_IOBUF\'\nmodule CC_LVDS_IOBUF #(\n       ^~~~~~~~~~~~~\n                                                                                          : ... Top module \'CC_IDDR\'\nmodule CC_IDDR #(\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_ODDR\'\nmodule CC_ODDR #(\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_DFF\'\nmodule CC_DFF #(\n       ^~~~~~\n                                                                                          : ... Top module \'CC_DLT\'\nmodule CC_DLT #(\n       ^~~~~~\n                                                                                          : ... Top module \'CC_LUT1\'\nmodule CC_LUT1 (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_LUT2\'\nmodule CC_LUT2 (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_LUT3\'\nmodule CC_LUT3 (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_LUT4\'\nmodule CC_LUT4 (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_MX2\'\nmodule CC_MX2 (\n       ^~~~~~\n                                                                                          : ... Top module \'CC_MX4\'\nmodule CC_MX4 (\n       ^~~~~~\n                                                                                          : ... Top module \'CC_MX8\'\nmodule CC_MX8 (\n       ^~~~~~\n                                                                                          : ... Top module \'CC_ADDF\'\nmodule CC_ADDF (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_MULT\'\nmodule CC_MULT #(\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_BUFG\'\nmodule CC_BUFG (\n       ^~~~~~~\n                                                                                          : ... Top module \'CC_BRAM_20K\'\nmodule CC_BRAM_20K (\n       ^~~~~~~~~~~\n                                                                                          : ... Top module \'CC_BRAM_40K\'\nmodule CC_BRAM_40K (\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:30: Operator VAR \'DELAY_IBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                       : ... In instance CC_IBUF\n parameter [3:0] DELAY_IBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:48: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                       : ... In instance CC_OBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:69: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                       : ... In instance CC_TOBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:91: Operator VAR \'DELAY_IBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                       : ... In instance CC_IOBUF\n parameter [3:0] DELAY_IBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:92: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                       : ... In instance CC_IOBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:113: Operator VAR \'DELAY_IBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                        : ... In instance CC_LVDS_IBUF\n parameter [3:0] DELAY_IBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:131: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                        : ... In instance CC_LVDS_OBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:150: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                        : ... In instance CC_LVDS_TOBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:170: Operator VAR \'DELAY_IBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                        : ... In instance CC_LVDS_IOBUF\n parameter [3:0] DELAY_IBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:171: Operator VAR \'DELAY_OBF\' expects 4 bits on the Initial value, but Initial value\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                        : ... In instance CC_LVDS_IOBUF\n parameter [3:0] DELAY_OBF = 1\'bx,\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1015: Operator NEQ expects 104 bits on the LHS, but LHS\'s VARREF \'A_WR_MODE\' generates 72 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n  if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1019: Operator EQ expects 104 bits on the LHS, but LHS\'s VARREF \'A_WR_MODE\' generates 72 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n  if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1265: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addra\' generates 16 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n      if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1268: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addra\' generates 16 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n      if (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1278: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addrb\' generates 16 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n      if (enb && !wea) A_DO_out[k] <= memory[addrb+k];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:1281: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addrb\' generates 16 bits.\n                                                                                         : ... In instance CC_BRAM_40K\n      if (enb && !wea) B_DO_out[k-40] <= memory[addrb+k];\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:552: Operator NEQ expects 104 bits on the LHS, but LHS\'s VARREF \'A_WR_MODE\' generates 72 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n  if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:556: Operator EQ expects 104 bits on the LHS, but LHS\'s VARREF \'A_WR_MODE\' generates 72 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n  if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:724: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addra\' generates 16 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n      if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:727: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addra\' generates 16 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n      if (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:737: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addrb\' generates 16 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n      if (enb && !wea) A_DO_out[k] <= memory[addrb+k];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:740: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addrb\' generates 16 bits.\n                                                                                        : ... In instance CC_BRAM_20K\n      if (enb && !wea) B_DO_out[k-20] <= memory[addrb+k];\n                                                     ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:402: Little bit endian vector: MSB < LSB of bit range: -1:0\n input signed [A_WIDTH-1:0] A,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:403: Little bit endian vector: MSB < LSB of bit range: -1:0\n input signed [B_WIDTH-1:0] B,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_sim.v:404: Little bit endian vector: MSB < LSB of bit range: -1:0\n output reg signed [P_WIDTH-1:0] P\n                   ^\n%Error: Exiting due to 26 warning(s)\n'
module CC_LVDS_OBUF #(
	parameter PIN_NAME_P = "UNPLACED",
	parameter PIN_NAME_N = "UNPLACED",
	parameter V_IO = "UNDEFINED",
	parameter [0:0] LVDS_BOOST = 1'bx,

	parameter [3:0] DELAY_OBF = 1'bx,
	parameter [0:0] FF_OBF = 1'bx
)(
	input  A,
	(* iopad_external_pin *)
	output OP, ON
);
	assign OP = A;
	assign ON = ~A;

endmodule
module CC_LVDS_OBUF #(
	parameter PIN_NAME_P = "UNPLACED",
	parameter PIN_NAME_N = "UNPLACED",
	parameter V_IO = "UNDEFINED",
	parameter [0:0] LVDS_BOOST = 1'bx,

	parameter [3:0] DELAY_OBF = 1'bx,
	parameter [0:0] FF_OBF = 1'bx
)(
	input  A,
	(* iopad_external_pin *)
	output OP, ON
);

	assign OP = A;
	assign ON = ~A;

endmodule