data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:5: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:12: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 In1 = 1; #1 In2 = 2; #1 IR_CU = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 In1 = 1; #1 In2 = 2; #1 IR_CU = 0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 In1 = 1; #1 In2 = 2; #1 IR_CU = 0;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #2 In1 = 1; #2 In2 = 2; #2 IR_CU = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #2 In1 = 1; #2 In2 = 2; #2 IR_CU = 1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #2 In1 = 1; #2 In2 = 2; #2 IR_CU = 1;\n                          ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("MultiplexerTestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,MultiplexerTestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Multiplexer2x1_32b/MultiplexerTestBench.v:22: Unsupported or unknown PLI call: $monitor\n $monitor("Time = %3d,IN1 = %32b,IN2 = %32b, IR_CU = %1b, Out = %32b",$time,In1,In2,IR_CU,out);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MultiplexerTestBench;

parameter sim_time = 750*2;

initial #sim_time $finish;

reg [31:0] In1,In2;
reg IR_CU;
wire [31:0] out;
Multiplexer mult(.IN1(In1),.IN2(In2),.IR_CU(IR_CU),.OUT(out));

initial fork
	 In1 = 1; In2 = 2; IR_CU = 0;
	 #1 In1 = 1; #1 In2 = 2; #1 IR_CU = 0;
	 #2 In1 = 1; #2 In2 = 2; #2 IR_CU = 1;
join

initial begin
	$dumpfile("MultiplexerTestBench.vcd");
	$dumpvars(0,MultiplexerTestBench);
	$display(" Test Results" );
	$monitor("Time = %3d,IN1 = %32b,IN2 = %32b, IR_CU = %1b, Out = %32b",$time,In1,In2,IR_CU,out);
end

endmodule
module MultiplexerTestBench;


parameter sim_time = 750*2;

initial #sim_time $finish;

reg [31:0] In1,In2;
reg IR_CU;
wire [31:0] out;
Multiplexer mult(.IN1(In1),.IN2(In2),.IR_CU(IR_CU),.OUT(out));

initial fork
	 In1 = 1; In2 = 2; IR_CU = 0;
	 #1 In1 = 1; #1 In2 = 2; #1 IR_CU = 0;
	 #2 In1 = 1; #2 In2 = 2; #2 IR_CU = 1;
join

initial begin
	$dumpfile("MultiplexerTestBench.vcd");
	$dumpvars(0,MultiplexerTestBench);
	$display(" Test Results" );
	$monitor("Time = %3d,IN1 = %32b,IN2 = %32b, IR_CU = %1b, Out = %32b",$time,In1,In2,IR_CU,out);
end

endmodule