data/full_repos/permissive/463481430/RTL/core/exu_mdu.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:6: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:7: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:21: Define or directive not defined: \'`decinfo_grplen_def\'\n    input wire[`decinfo_grplen_def] i_decinfo_grp,\n               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`decinfo_grplen_def] i_decinfo_grp,\n                                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:22: Define or directive not defined: \'`decinfolen_def\'\n    input wire[`decinfolen_def] i_mduinfo,\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_mdu_rdidx, \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:24: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_mdu_rdidx, \n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:25: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_mdu_op1, \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:26: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_mdu_op2, \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_will_rdwen,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`rfidxlen_def] o_will_rdidx,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:32: Define or directive not defined: \'`rfidxlen_def\'\n    output wire[`rfidxlen_def] o_will_rdidx,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`rfidxlen_def] o_mdu_rdidx,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:36: Define or directive not defined: \'`rfidxlen_def\'\n    output wire[`rfidxlen_def] o_mdu_rdidx,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:37: Define or directive not defined: \'`xlen_def\'\n    output wire[`xlen_def] o_mdu_rdwdata\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:47: Define or directive not defined: \'`decinfo_grp_mdu\'\n    wire mdu_vld = i_decinfo_grp[`decinfo_grp_mdu] & (~o_working) & i_vld;\n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire mdu_vld = i_decinfo_grp[`decinfo_grp_mdu] & (~o_working) & i_vld;\n                                                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:49: Define or directive not defined: \'`rfidxlen_def\'\n    reg[`rfidxlen_def] rdidx;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`rfidxlen_def] rdidx;\n                     ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:50: Define or directive not defined: \'`decinfolen_def\'\n    reg[`decinfolen_def] mduinfo;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`decinfolen_def] mduinfo;\n                       ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:64: Define or directive not defined: \'`xlen\'\n            rem_op1_sym<=i_mdu_op1[`xlen-1];\n                                   ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:87: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] op1;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] op1;\n                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:88: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] op2;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] op2;\n                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:94: Define or directive not defined: \'`mduinfo_mul\'\n    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:94: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);\n                           ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:94: Define or directive not defined: \'`mduinfo_mulh\'\n    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:94: Define or directive not defined: \'`mduinfo_mulhu\'\n    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);\n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:94: Define or directive not defined: \'`mduinfo_mulhsu\'\n    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);\n                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:125: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] div_signed_quo;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] div_signed_quo;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:126: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] div_signed_rem;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] div_signed_rem;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:127: Define or directive not defined: \'`mduinfo_div\'\n    wire div_signed_start = mdu_vld & (i_mduinfo[`mduinfo_div] | i_mduinfo[`mduinfo_rem]);\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:127: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire div_signed_start = mdu_vld & (i_mduinfo[`mduinfo_div] | i_mduinfo[`mduinfo_rem]);\n                                                             ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:127: Define or directive not defined: \'`mduinfo_rem\'\n    wire div_signed_start = mdu_vld & (i_mduinfo[`mduinfo_div] | i_mduinfo[`mduinfo_rem]);\n                                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:140: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] div_unsigned_quo;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:140: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] div_unsigned_quo;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:141: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] div_unsigned_rem;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:141: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] div_unsigned_rem;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:142: Define or directive not defined: \'`mduinfo_divu\'\n    wire div_unsigned_start = mdu_vld & (i_mduinfo[`mduinfo_divu] | i_mduinfo[`mduinfo_remu]);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:142: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire div_unsigned_start = mdu_vld & (i_mduinfo[`mduinfo_divu] | i_mduinfo[`mduinfo_remu]);\n                                                                ^\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:142: Define or directive not defined: \'`mduinfo_remu\'\n    wire div_unsigned_start = mdu_vld & (i_mduinfo[`mduinfo_divu] | i_mduinfo[`mduinfo_remu]);\n                                                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:154: syntax error, unexpected assign\n    assign mdu_finish = mul_finish|div_finish;\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:159: Define or directive not defined: \'`mduinfo_mul\'\n    assign o_mdu_rdwdata =  mduinfo[`mduinfo_mul] ? mul_ss[31:0] : \n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:160: Define or directive not defined: \'`mduinfo_mulh\'\n                            mduinfo[`mduinfo_mulh] ? mul_ss[63:32] :\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:161: Define or directive not defined: \'`mduinfo_mulhu\'\n                            mduinfo[`mduinfo_mulhu] ? mul_uu[63:32] :\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/exu_mdu.v:162: Define or directive not defined: \'`mduinfo_mulhsu\'\n                            mduinfo[`mduinfo_mulhsu] ? mul_su[63:32] :\n                                    ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module EXU_MDU (
    input wire i_clk,
    input wire i_rstn,

    input wire i_vld,
    input wire i_flush,

    input wire[`decinfo_grplen_def] i_decinfo_grp,
    input wire[`decinfolen_def] i_mduinfo,
    input wire i_mdu_rdwen,
    input wire[`rfidxlen_def] i_mdu_rdidx,
    input wire[`xlen_def] i_mdu_op1,
    input wire[`xlen_def] i_mdu_op2,


    output wire o_working,

    output wire o_will_rdwen,
    output wire[`rfidxlen_def] o_will_rdidx,


    output wire o_mdu_rdwen,
    output wire[`rfidxlen_def] o_mdu_rdidx,
    output wire[`xlen_def] o_mdu_rdwdata
);


    wire mdu_finish;
    


    reg rem_op1_sym;
    reg working;
    wire mdu_vld = i_decinfo_grp[`decinfo_grp_mdu] & (~o_working) & i_vld;
    reg rdwen;
    reg[`rfidxlen_def] rdidx;
    reg[`decinfolen_def] mduinfo;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            rdwen<=0; 
            working<=0;
            rem_op1_sym<=0;
        end
        else if(mdu_vld) begin

            rdwen   <= i_mdu_rdwen;
            rdidx   <= i_mdu_rdidx;
            working <= 1;
            mduinfo <= i_mduinfo;

            rem_op1_sym<=i_mdu_op1[`xlen-1];
        end
        else if(mdu_finish)begin
            rdwen<= 0;
            working<=0;
            rem_op1_sym<=0;
        end
        else if(i_flush)begin
            rdwen<=0;
        end
    end

    assign o_working = working & (~mdu_finish);

    assign o_will_rdwen = rdwen;
    assign o_will_rdidx = rdidx;





    reg[7:0] cnt;
    reg mul_vld;
    reg[`xlen_def] op1;
    reg[`xlen_def] op2;
    reg mul_finish;
    wire[63:0] mul_ss = $signed(op1) * $signed(op2);
    wire[63:0] mul_uu = op1 * op2;
    wire[63:0] mul_su = $signed(op1) * $signed({1'b0,op2});
    wire mul_start = mdu_vld & 
    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            mul_vld<=0;
            cnt<=0;
            mul_finish<=0;
        end
        else if(mul_start) begin
            mul_vld<=1;
            op1<= i_mdu_op1;
            op2<= i_mdu_op2;
            cnt<=0;
            mul_finish<=0;
        end
        else if(mul_vld) begin
            if(cnt==1) begin
                mul_finish<=1;
                mul_vld<=0;
                cnt<=0;
            end
            else begin
                cnt<=cnt+1;
            end
        end
        else begin
            mul_finish<=0;
        end
    end


    wire div_signed_finish;
    wire[`xlen_def] div_signed_quo;
    wire[`xlen_def] div_signed_rem;
    wire div_signed_start = mdu_vld & (i_mduinfo[`mduinfo_div] | i_mduinfo[`mduinfo_rem]);
    DIV_SIGNED u_DIV_SIGNED(
        .clk    ( i_clk    ),
        .den    ( mdu_vld ?  i_mdu_op2 : 0   ),
        .num    ( mdu_vld ? i_mdu_op1  : 0  ),
        .rst    ( ~i_rstn    ),
        .start  ( div_signed_start  ),
        .finish ( div_signed_finish ),
        .quo    ( div_signed_quo    ),
        .rem    ( div_signed_rem    )
    );

    wire div_unsigned_finish;
    wire[`xlen_def] div_unsigned_quo;
    wire[`xlen_def] div_unsigned_rem;
    wire div_unsigned_start = mdu_vld & (i_mduinfo[`mduinfo_divu] | i_mduinfo[`mduinfo_remu]);
    DIV_UNSIGNED u_DIV_UNSIGNED(
        .clk    ( i_clk    ),
        .den    ( mdu_vld ?  i_mdu_op2 : 0    ),
        .num    ( mdu_vld ? i_mdu_op1  : 0     ),
        .rst    ( ~i_rstn    ),
        .start  ( div_unsigned_start  ),
        .finish ( div_unsigned_finish ),
        .quo    ( div_unsigned_quo    ),
        .rem    ( div_unsigned_rem    )
    );
    wire div_finish = div_unsigned_finish|div_signed_finish;
    assign mdu_finish = mul_finish|div_finish;

    assign o_mdu_rdwen =  mdu_finish & rdwen;
    assign o_mdu_rdidx = rdidx;

    assign o_mdu_rdwdata =  mduinfo[`mduinfo_mul] ? mul_ss[31:0] : 
                            mduinfo[`mduinfo_mulh] ? mul_ss[63:32] :
                            mduinfo[`mduinfo_mulhu] ? mul_uu[63:32] :
                            mduinfo[`mduinfo_mulhsu] ? mul_su[63:32] :
                            mduinfo[`mduinfo_div] ? div_signed_quo:
                            mduinfo[`mduinfo_divu] ? div_unsigned_quo:
                            mduinfo[`mduinfo_rem] ? (rem_op1_sym ? (-div_signed_rem) : div_signed_rem):
                            mduinfo[`mduinfo_remu] ? div_unsigned_rem:0;










    
endmodule
module EXU_MDU (
    input wire i_clk,
    input wire i_rstn,

    input wire i_vld,
    input wire i_flush,

    input wire[`decinfo_grplen_def] i_decinfo_grp,
    input wire[`decinfolen_def] i_mduinfo,
    input wire i_mdu_rdwen,
    input wire[`rfidxlen_def] i_mdu_rdidx,
    input wire[`xlen_def] i_mdu_op1,
    input wire[`xlen_def] i_mdu_op2,


    output wire o_working,

    output wire o_will_rdwen,
    output wire[`rfidxlen_def] o_will_rdidx,


    output wire o_mdu_rdwen,
    output wire[`rfidxlen_def] o_mdu_rdidx,
    output wire[`xlen_def] o_mdu_rdwdata
);



    wire mdu_finish;
    


    reg rem_op1_sym;
    reg working;
    wire mdu_vld = i_decinfo_grp[`decinfo_grp_mdu] & (~o_working) & i_vld;
    reg rdwen;
    reg[`rfidxlen_def] rdidx;
    reg[`decinfolen_def] mduinfo;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            rdwen<=0; 
            working<=0;
            rem_op1_sym<=0;
        end
        else if(mdu_vld) begin

            rdwen   <= i_mdu_rdwen;
            rdidx   <= i_mdu_rdidx;
            working <= 1;
            mduinfo <= i_mduinfo;

            rem_op1_sym<=i_mdu_op1[`xlen-1];
        end
        else if(mdu_finish)begin
            rdwen<= 0;
            working<=0;
            rem_op1_sym<=0;
        end
        else if(i_flush)begin
            rdwen<=0;
        end
    end

    assign o_working = working & (~mdu_finish);

    assign o_will_rdwen = rdwen;
    assign o_will_rdidx = rdidx;





    reg[7:0] cnt;
    reg mul_vld;
    reg[`xlen_def] op1;
    reg[`xlen_def] op2;
    reg mul_finish;
    wire[63:0] mul_ss = $signed(op1) * $signed(op2);
    wire[63:0] mul_uu = op1 * op2;
    wire[63:0] mul_su = $signed(op1) * $signed({1'b0,op2});
    wire mul_start = mdu_vld & 
    (i_mduinfo[`mduinfo_mul] | i_mduinfo[`mduinfo_mulh] | i_mduinfo[`mduinfo_mulhu] | i_mduinfo[`mduinfo_mulhsu]);
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            mul_vld<=0;
            cnt<=0;
            mul_finish<=0;
        end
        else if(mul_start) begin
            mul_vld<=1;
            op1<= i_mdu_op1;
            op2<= i_mdu_op2;
            cnt<=0;
            mul_finish<=0;
        end
        else if(mul_vld) begin
            if(cnt==1) begin
                mul_finish<=1;
                mul_vld<=0;
                cnt<=0;
            end
            else begin
                cnt<=cnt+1;
            end
        end
        else begin
            mul_finish<=0;
        end
    end


    wire div_signed_finish;
    wire[`xlen_def] div_signed_quo;
    wire[`xlen_def] div_signed_rem;
    wire div_signed_start = mdu_vld & (i_mduinfo[`mduinfo_div] | i_mduinfo[`mduinfo_rem]);
    DIV_SIGNED u_DIV_SIGNED(
        .clk    ( i_clk    ),
        .den    ( mdu_vld ?  i_mdu_op2 : 0   ),
        .num    ( mdu_vld ? i_mdu_op1  : 0  ),
        .rst    ( ~i_rstn    ),
        .start  ( div_signed_start  ),
        .finish ( div_signed_finish ),
        .quo    ( div_signed_quo    ),
        .rem    ( div_signed_rem    )
    );

    wire div_unsigned_finish;
    wire[`xlen_def] div_unsigned_quo;
    wire[`xlen_def] div_unsigned_rem;
    wire div_unsigned_start = mdu_vld & (i_mduinfo[`mduinfo_divu] | i_mduinfo[`mduinfo_remu]);
    DIV_UNSIGNED u_DIV_UNSIGNED(
        .clk    ( i_clk    ),
        .den    ( mdu_vld ?  i_mdu_op2 : 0    ),
        .num    ( mdu_vld ? i_mdu_op1  : 0     ),
        .rst    ( ~i_rstn    ),
        .start  ( div_unsigned_start  ),
        .finish ( div_unsigned_finish ),
        .quo    ( div_unsigned_quo    ),
        .rem    ( div_unsigned_rem    )
    );
    wire div_finish = div_unsigned_finish|div_signed_finish;
    assign mdu_finish = mul_finish|div_finish;

    assign o_mdu_rdwen =  mdu_finish & rdwen;
    assign o_mdu_rdidx = rdidx;

    assign o_mdu_rdwdata =  mduinfo[`mduinfo_mul] ? mul_ss[31:0] : 
                            mduinfo[`mduinfo_mulh] ? mul_ss[63:32] :
                            mduinfo[`mduinfo_mulhu] ? mul_uu[63:32] :
                            mduinfo[`mduinfo_mulhsu] ? mul_su[63:32] :
                            mduinfo[`mduinfo_div] ? div_signed_quo:
                            mduinfo[`mduinfo_divu] ? div_unsigned_quo:
                            mduinfo[`mduinfo_rem] ? (rem_op1_sym ? (-div_signed_rem) : div_signed_rem):
                            mduinfo[`mduinfo_remu] ? div_unsigned_rem:0;










    
endmodule