data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v
1: b'%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v:54: Unsupported or unknown PLI call: $from_myhdl\n    $from_myhdl(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v:61: Unsupported or unknown PLI call: $to_myhdl\n    $to_myhdl(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v:68: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test_arbiter_rr.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/tb/test_arbiter_rr.v:69: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test_arbiter_rr);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_arbiter_rr;


localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";


reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;


wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;

initial begin

    $from_myhdl(
        clk,
        rst,
        current_test,
        request,
        acknowledge
    );
    $to_myhdl(
        grant,
        grant_valid,
        grant_encoded
    );


    $dumpfile("test_arbiter_rr.lxt");
    $dumpvars(0, test_arbiter_rr);
end

arbiter #(
    .PORTS(PORTS),
    .TYPE(TYPE),
    .BLOCK(BLOCK)
)
UUT (
    .clk(clk),
    .rst(rst),
    .request(request),
    .acknowledge(acknowledge),
    .grant(grant),
    .grant_valid(grant_valid),
    .grant_encoded(grant_encoded)
);

endmodule
module test_arbiter_rr;



localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";


reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;


wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;

initial begin

    $from_myhdl(
        clk,
        rst,
        current_test,
        request,
        acknowledge
    );
    $to_myhdl(
        grant,
        grant_valid,
        grant_encoded
    );


    $dumpfile("test_arbiter_rr.lxt");
    $dumpvars(0, test_arbiter_rr);
end

arbiter #(
    .PORTS(PORTS),
    .TYPE(TYPE),
    .BLOCK(BLOCK)
)
UUT (
    .clk(clk),
    .rst(rst),
    .request(request),
    .acknowledge(acknowledge),
    .grant(grant),
    .grant_valid(grant_valid),
    .grant_encoded(grant_encoded)
);

endmodule