data/full_repos/permissive/412297935/hdl/xe_host_tb.v
1: b'%Error: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:77: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("/tmp/wave.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:78: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0, xe_host_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #558  a8_rst_n = 1\'b0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n   #558  a8_rst_n = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n            #245\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n   #136\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n            #245\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n   #136\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n            #245\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n   #136\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n            #381\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n   #177\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n            #381\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n            #558  $finish;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n            #381\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n         #5   clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/412297935/hdl/xe_host_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n   #279 a8_clk = ~a8_clk;\n   ^\n%Error: Exiting due to 3 error(s), 20 warning(s)\n'
module xe_host_tb;

	reg clk, a8_clk;
	



	reg		[15:0]	a8_addr;
	reg		[7:0]	a8_data;
	reg				a8_rw_n;
	reg				a8_halt_n;
	reg				a8_rst_n;
	reg				a8_rd5;
	reg				a8_rd4;
	reg				a8_ref_n;
	
	wire			a8_irq_n;
	wire			a8_mpd_n;
	wire			a8_extsel_n;
	
	wire			mpd;
	
    wire            xio_rts;
    reg             xio_cts;
    
	xe_host dut
		(
		.sysclk(clk),
		.a8_clk(a8_clk),
		.a8_rw_IN(a8_rw_n),
		.a8_halt_n_IN(a8_halt_n),
		.a8_irq_n(a8_irq_n),
		.a8_a_IN(a8_addr),
		.a8_d_IN(a8_data),
		.a8_rst_n_IN(a8_rst_n),
		.a8_rd5(a8_rd5),
		.a8_rd4(a8_rd4),
		.a8_ref_n_IN(a8_ref_n),
		.a8_mpd_n(a8_mpd_n),
		.a8_extsel_n(a8_extsel_n),
        .xio_host_rts(xio_rts),
        .xio_host_cts(xio_cts)
		);
	



    initial
        begin
            $dumpfile("/tmp/wave.vcd");
            $dumpvars(0, xe_host_tb);
                
            		clk 		= 1'b0;
            		a8_clk 		= 1'b0;
					a8_rw_n		= 1'b1;
            		a8_rst_n   	= 1'b1;
            		a8_halt_n	= 1'b1;
            		a8_addr	 	= 16'h0;
            		a8_data	 	= 16'h0;
            		a8_rd5		= 1'b0;
            		a8_rd4		= 1'b0;
            		a8_ref_n	= 1'b1;
            		

			#558 	a8_rst_n	= 1'b0;
			
			#558 	a8_rst_n	= 1'b1;
			
			

			#177
				 	a8_addr		= 16'hd604;
             		a8_rw_n		= 1'b0;
            #245
            		a8_data		= 8'h05;
			#136
			
			

			#177
				 	a8_addr		= 16'hd605;
            #245
            		a8_data		= 8'h10;
			#136
			

			#177
				 	a8_addr		= 16'hd601;
             		a8_rw_n		= 1'b0;
            #245
            		a8_data		= 8'h01;
			#136



			#177
				 	a8_rw_n		= 1'b1;
					a8_addr		= 16'hd604;
            #381


					

			#177
					a8_addr		= 16'h607;
            #381
					

			#177
					a8_addr		= 16'h639;
            #381


            #558 	$finish;
		end




    always @ (posedge clk)
        begin
            xio_cts <= xio_rts;
        end
        
        
        



    always 
        	#5 		clk = ~clk;
    always 
			#279	a8_clk = ~a8_clk;
			
endmodule
module xe_host_tb;


	reg clk, a8_clk;
	



	reg		[15:0]	a8_addr;
	reg		[7:0]	a8_data;
	reg				a8_rw_n;
	reg				a8_halt_n;
	reg				a8_rst_n;
	reg				a8_rd5;
	reg				a8_rd4;
	reg				a8_ref_n;
	
	wire			a8_irq_n;
	wire			a8_mpd_n;
	wire			a8_extsel_n;
	
	wire			mpd;
	
    wire            xio_rts;
    reg             xio_cts;
    
	xe_host dut
		(
		.sysclk(clk),
		.a8_clk(a8_clk),
		.a8_rw_IN(a8_rw_n),
		.a8_halt_n_IN(a8_halt_n),
		.a8_irq_n(a8_irq_n),
		.a8_a_IN(a8_addr),
		.a8_d_IN(a8_data),
		.a8_rst_n_IN(a8_rst_n),
		.a8_rd5(a8_rd5),
		.a8_rd4(a8_rd4),
		.a8_ref_n_IN(a8_ref_n),
		.a8_mpd_n(a8_mpd_n),
		.a8_extsel_n(a8_extsel_n),
        .xio_host_rts(xio_rts),
        .xio_host_cts(xio_cts)
		);
	



    initial
        begin
            $dumpfile("/tmp/wave.vcd");
            $dumpvars(0, xe_host_tb);
                
            		clk 		= 1'b0;
            		a8_clk 		= 1'b0;
					a8_rw_n		= 1'b1;
            		a8_rst_n   	= 1'b1;
            		a8_halt_n	= 1'b1;
            		a8_addr	 	= 16'h0;
            		a8_data	 	= 16'h0;
            		a8_rd5		= 1'b0;
            		a8_rd4		= 1'b0;
            		a8_ref_n	= 1'b1;
            		

			#558 	a8_rst_n	= 1'b0;
			
			#558 	a8_rst_n	= 1'b1;
			
			

			#177
				 	a8_addr		= 16'hd604;
             		a8_rw_n		= 1'b0;
            #245
            		a8_data		= 8'h05;
			#136
			
			

			#177
				 	a8_addr		= 16'hd605;
            #245
            		a8_data		= 8'h10;
			#136
			

			#177
				 	a8_addr		= 16'hd601;
             		a8_rw_n		= 1'b0;
            #245
            		a8_data		= 8'h01;
			#136



			#177
				 	a8_rw_n		= 1'b1;
					a8_addr		= 16'hd604;
            #381


					

			#177
					a8_addr		= 16'h607;
            #381
					

			#177
					a8_addr		= 16'h639;
            #381


            #558 	$finish;
		end




    always @ (posedge clk)
        begin
            xio_cts <= xio_rts;
        end
        
        
        



    always 
        	#5 		clk = ~clk;
    always 
			#279	a8_clk = ~a8_clk;
			
endmodule