data/full_repos/permissive/423547971/Modules with Simulations/Verilog Switch Level Modeling/sim_cmos.v
1: b'%Error: Cannot find file containing module: with\n        ... Looked in:\n             data/full_repos/permissive/423547971/Modules/with\n             data/full_repos/permissive/423547971/Modules/with.v\n             data/full_repos/permissive/423547971/Modules/with.sv\n             with\n             with.v\n             with.sv\n             obj_dir/with\n             obj_dir/with.v\n             obj_dir/with.sv\n%Error: Cannot find file containing module: Simulations/Verilog\n%Error: Cannot find file containing module: Switch\n%Error: Cannot find file containing module: Level\n%Error: Cannot find file containing module: Modeling,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Modules\n%Error: Cannot find file containing module: Modeling/sim_cmos.v\n%Error: Exiting due to 7 error(s)\n'
module sim_cmos;

    reg a, b, c, d, e;
    wire x, y, z;
    
    cmos_gates DUT(.a(a), .b(b), .c(c), .d(d), .e(e), .x(x), .y(y), .z(z));

    initial begin
        a = 0;
        b = 0;
        c = 0;
        d = 0;
        e = 0;
        #1
        a = 0;
        b = 1;
        c = 0;
        d = 1;
        #1
        a = 1;
        b = 0;
        c = 1;
        d = 0;
        e = 1;
        #1
        a = 1;
        b = 1;
        c = 1;
        d = 1;
        #1   
        
        $finish;
    end

endmodule
module sim_cmos;


    reg a, b, c, d, e;
    wire x, y, z;
    
    cmos_gates DUT(.a(a), .b(b), .c(c), .d(d), .e(e), .x(x), .y(y), .z(z));

    initial begin
        a = 0;
        b = 0;
        c = 0;
        d = 0;
        e = 0;
        #1
        a = 0;
        b = 1;
        c = 0;
        d = 1;
        #1
        a = 1;
        b = 0;
        c = 1;
        d = 0;
        e = 1;
        #1
        a = 1;
        b = 1;
        c = 1;
        d = 1;
        #1   
        
        $finish;
    end

endmodule