data/full_repos/permissive/435012493/BoothMultiplication_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nRST = 1; GO = 1;#10; RST =0; #5; m = 32\'hfffffffD;  \n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nRST = 1; GO = 1;#10; RST =0; #5; m = 32\'hfffffffD;  \n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nclk = 0; #5;\n         ^\n%Error: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:15: syntax error, unexpected always\nalways begin\n^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\neResult = 64\'h000000000000000C;#5  \n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  clk <= ~clk; #5; \n               ^\n%Error: data/full_repos/permissive/435012493/BoothMultiplication_tb.v:24: syntax error, unexpected end, expecting \';\'\n    end\n    ^~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BoothMultiplication_tb;

reg GO, clk, RST;
reg [31:0] m, r;

wire done, cntOut; wire [1:0] pOut, CS; wire [63:0] result;
reg [63:0] eResult;
BoothMultiplication DUT(GO,clk,RST,m,r,done,cntOut,pOut,CS,result);
initial begin
RST = 1; GO = 1;#10; RST =0; #5; m = 32'hfffffffD;
r = 32'hfffffffC;
clk = 0; #5;
eResult = 64'h000000000000000C;#5
always begin
  clk <= ~clk; #5; 
end
always@(negedge clk) begin
if(CS == 2'b11)
begin
  if(eResult == result) 
    begin
    $display("successful: expected %b = result %b\n", eResult, result); $stop
    end
  else
    begin
    $display("ERROR: expected != result\n"); $stop;
    end 
end
end
endmodule
module BoothMultiplication_tb;


reg GO, clk, RST;
reg [31:0] m, r;

wire done, cntOut; wire [1:0] pOut, CS; wire [63:0] result;
reg [63:0] eResult;
BoothMultiplication DUT(GO,clk,RST,m,r,done,cntOut,pOut,CS,result);
initial begin
RST = 1; GO = 1;#10; RST =0; #5; m = 32'hfffffffD;
r = 32'hfffffffC;
clk = 0; #5;
eResult = 64'h000000000000000C;#5
always begin
  clk <= ~clk; #5; 
end
always@(negedge clk) begin
if(CS == 2'b11)
begin
  if(eResult == result) 
    begin
    $display("successful: expected %b = result %b\n", eResult, result); $stop
    end
  else
    begin
    $display("ERROR: expected != result\n"); $stop;
    end 
end
end
endmodule