data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v:167: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                     : ... In instance SmallOdds5.smalls.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v:167: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                     : ... In instance SmallOdds5.odds.u_pad_34\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module Queue(
    input clock,
    input reset,
    output io_enq_ready,
    input io_enq_valid,
    input [31:0] io_enq_bits,
    input io_deq_ready,
    output io_deq_valid,
    output [31:0] io_deq_bits,
    output [1:0] io_count
);
    wire [31:0] ram__T_50_data;
    wire ram__T_50_clk;
    wire ram__T_50_en;
    wire ram__T_50_addr;
    wire ram__T_36_clk;
    wire ram__T_36_en;
    wire ram__T_36_mask;
    wire ram__T_36_addr;
    wire [31:0] ram__T_36_data;
    RAMMEM #(.depth(2), .addrbits(1), .width(32), .isSyncRead(0)) ram (
        .read_data(ram__T_50_data),
        .read_clk(ram__T_50_clk),
        .read_en(ram__T_50_en),
        .read_addr(ram__T_50_addr),
        .write_clk(ram__T_36_clk),
        .write_en(ram__T_36_en),
        .write_mask(ram__T_36_mask),
        .write_addr(ram__T_36_addr),
        .write_data(ram__T_36_data)
    );
    wire _value__q;
    wire _value__d;
    DFF_POSCLK #(.width(1)) value (
        .q(_value__q),
        .d(_value__d),
        .clk(clock)
    );
    wire _value_1__q;
    wire _value_1__d;
    DFF_POSCLK #(.width(1)) value_1 (
        .q(_value_1__q),
        .d(_value_1__d),
        .clk(clock)
    );
    wire _maybe_full__q;
    wire _maybe_full__d;
    DFF_POSCLK #(.width(1)) maybe_full (
        .q(_maybe_full__q),
        .d(_maybe_full__d),
        .clk(clock)
    );
    wire _T_28;
    EQ_UNSIGNED #(.width(1)) u_eq_7 (
        .y(_T_28),
        .a(_value__q),
        .b(_value_1__q)
    );
    wire _T_30;
    EQ_UNSIGNED #(.width(1)) u_eq_8 (
        .y(_T_30),
        .a(_maybe_full__q),
        .b(1'h0)
    );
    wire empty;
    BITWISEAND #(.width(1)) bitwiseand_9 (
        .y(empty),
        .a(_T_28),
        .b(_T_30)
    );
    wire _T_31;
    BITWISEAND #(.width(1)) bitwiseand_10 (
        .y(_T_31),
        .a(_T_28),
        .b(_maybe_full__q)
    );
    wire _T_32;
    BITWISEAND #(.width(1)) bitwiseand_11 (
        .y(_T_32),
        .a(io_enq_ready),
        .b(io_enq_valid)
    );
    wire do_enq;
    wire _T_34;
    BITWISEAND #(.width(1)) bitwiseand_12 (
        .y(_T_34),
        .a(io_deq_ready),
        .b(io_deq_valid)
    );
    wire do_deq;
    wire wrap;
    EQ_UNSIGNED #(.width(1)) u_eq_13 (
        .y(wrap),
        .a(_value__q),
        .b(1'h1)
    );
    wire [1:0] _T_39;
    ADD_UNSIGNED #(.width(1)) u_add_14 (
        .y(_T_39),
        .a(_value__q),
        .b(1'h1)
    );
    wire _T_40;
    TAIL #(.width(2), .n(1)) tail_15 (
        .y(_T_40),
        .in(_T_39)
    );
    wire _GEN_0;
    assign _GEN_0 = _value__q;
    wire _GEN_1;
    assign _GEN_1 = clock;
    wire _GEN_2;
    MUX_UNSIGNED #(.width(1)) u_mux_16 (
        .y(_GEN_2),
        .sel(do_enq),
        .a(1'h1),
        .b(1'h0)
    );
    wire [31:0] _GEN_3;
    assign _GEN_3 = io_enq_bits;
    wire _GEN_4;
    MUX_UNSIGNED #(.width(1)) u_mux_17 (
        .y(_GEN_4),
        .sel(do_enq),
        .a(_T_40),
        .b(_value__q)
    );
    wire wrap_1;
    EQ_UNSIGNED #(.width(1)) u_eq_18 (
        .y(wrap_1),
        .a(_value_1__q),
        .b(1'h1)
    );
    wire [1:0] _T_43;
    ADD_UNSIGNED #(.width(1)) u_add_19 (
        .y(_T_43),
        .a(_value_1__q),
        .b(1'h1)
    );
    wire _T_44;
    TAIL #(.width(2), .n(1)) tail_20 (
        .y(_T_44),
        .in(_T_43)
    );
    wire _GEN_5;
    MUX_UNSIGNED #(.width(1)) u_mux_21 (
        .y(_GEN_5),
        .sel(do_deq),
        .a(_T_44),
        .b(_value_1__q)
    );
    wire _T_45;
    NEQ_UNSIGNED #(.width(1)) u_neq_22 (
        .y(_T_45),
        .a(do_enq),
        .b(do_deq)
    );
    wire _GEN_6;
    MUX_UNSIGNED #(.width(1)) u_mux_23 (
        .y(_GEN_6),
        .sel(_T_45),
        .a(do_enq),
        .b(_maybe_full__q)
    );
    wire _T_47;
    EQ_UNSIGNED #(.width(1)) u_eq_24 (
        .y(_T_47),
        .a(empty),
        .b(1'h0)
    );
    wire _T_49;
    EQ_UNSIGNED #(.width(1)) u_eq_25 (
        .y(_T_49),
        .a(_T_31),
        .b(1'h0)
    );
    wire [1:0] _T_51;
    SUB_UNSIGNED #(.width(1)) u_sub_26 (
        .y(_T_51),
        .a(_value__q),
        .b(_value_1__q)
    );
    wire [1:0] _T_52;
    ASUINT #(.width(2)) asuint_27 (
        .y(_T_52),
        .in(_T_51)
    );
    wire _T_53;
    TAIL #(.width(2), .n(1)) tail_28 (
        .y(_T_53),
        .in(_T_52)
    );
    wire _T_54;
    BITWISEAND #(.width(1)) bitwiseand_29 (
        .y(_T_54),
        .a(_maybe_full__q),
        .b(_T_28)
    );
    wire [1:0] _T_55;
    CAT #(.width_a(1), .width_b(1)) cat_30 (
        .y(_T_55),
        .a(_T_54),
        .b(_T_53)
    );
    assign do_deq = _T_34;
    assign do_enq = _T_32;
    assign io_count = _T_55;
    assign io_deq_bits = ram__T_50_data;
    assign io_deq_valid = _T_47;
    assign io_enq_ready = _T_49;
    MUX_UNSIGNED #(.width(1)) u_mux_31 (
        .y(_maybe_full__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_6)
    );
    assign ram__T_36_addr = _GEN_0;
    assign ram__T_36_clk = _GEN_1;
    assign ram__T_36_data = _GEN_3;
    assign ram__T_36_en = _GEN_2;
    assign ram__T_36_mask = _GEN_2;
    assign ram__T_50_addr = _value_1__q;
    assign ram__T_50_clk = clock;
    assign ram__T_50_en = 1'h1;
    MUX_UNSIGNED #(.width(1)) u_mux_32 (
        .y(_value__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_4)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_33 (
        .y(_value_1__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_5)
    );
endmodule
module Queue(
    input clock,
    input reset,
    output io_enq_ready,
    input io_enq_valid,
    input [31:0] io_enq_bits,
    input io_deq_ready,
    output io_deq_valid,
    output [31:0] io_deq_bits,
    output [1:0] io_count
);

    wire [31:0] ram__T_50_data;
    wire ram__T_50_clk;
    wire ram__T_50_en;
    wire ram__T_50_addr;
    wire ram__T_36_clk;
    wire ram__T_36_en;
    wire ram__T_36_mask;
    wire ram__T_36_addr;
    wire [31:0] ram__T_36_data;
    RAMMEM #(.depth(2), .addrbits(1), .width(32), .isSyncRead(0)) ram (
        .read_data(ram__T_50_data),
        .read_clk(ram__T_50_clk),
        .read_en(ram__T_50_en),
        .read_addr(ram__T_50_addr),
        .write_clk(ram__T_36_clk),
        .write_en(ram__T_36_en),
        .write_mask(ram__T_36_mask),
        .write_addr(ram__T_36_addr),
        .write_data(ram__T_36_data)
    );
    wire _value__q;
    wire _value__d;
    DFF_POSCLK #(.width(1)) value (
        .q(_value__q),
        .d(_value__d),
        .clk(clock)
    );
    wire _value_1__q;
    wire _value_1__d;
    DFF_POSCLK #(.width(1)) value_1 (
        .q(_value_1__q),
        .d(_value_1__d),
        .clk(clock)
    );
    wire _maybe_full__q;
    wire _maybe_full__d;
    DFF_POSCLK #(.width(1)) maybe_full (
        .q(_maybe_full__q),
        .d(_maybe_full__d),
        .clk(clock)
    );
    wire _T_28;
    EQ_UNSIGNED #(.width(1)) u_eq_7 (
        .y(_T_28),
        .a(_value__q),
        .b(_value_1__q)
    );
    wire _T_30;
    EQ_UNSIGNED #(.width(1)) u_eq_8 (
        .y(_T_30),
        .a(_maybe_full__q),
        .b(1'h0)
    );
    wire empty;
    BITWISEAND #(.width(1)) bitwiseand_9 (
        .y(empty),
        .a(_T_28),
        .b(_T_30)
    );
    wire _T_31;
    BITWISEAND #(.width(1)) bitwiseand_10 (
        .y(_T_31),
        .a(_T_28),
        .b(_maybe_full__q)
    );
    wire _T_32;
    BITWISEAND #(.width(1)) bitwiseand_11 (
        .y(_T_32),
        .a(io_enq_ready),
        .b(io_enq_valid)
    );
    wire do_enq;
    wire _T_34;
    BITWISEAND #(.width(1)) bitwiseand_12 (
        .y(_T_34),
        .a(io_deq_ready),
        .b(io_deq_valid)
    );
    wire do_deq;
    wire wrap;
    EQ_UNSIGNED #(.width(1)) u_eq_13 (
        .y(wrap),
        .a(_value__q),
        .b(1'h1)
    );
    wire [1:0] _T_39;
    ADD_UNSIGNED #(.width(1)) u_add_14 (
        .y(_T_39),
        .a(_value__q),
        .b(1'h1)
    );
    wire _T_40;
    TAIL #(.width(2), .n(1)) tail_15 (
        .y(_T_40),
        .in(_T_39)
    );
    wire _GEN_0;
    assign _GEN_0 = _value__q;
    wire _GEN_1;
    assign _GEN_1 = clock;
    wire _GEN_2;
    MUX_UNSIGNED #(.width(1)) u_mux_16 (
        .y(_GEN_2),
        .sel(do_enq),
        .a(1'h1),
        .b(1'h0)
    );
    wire [31:0] _GEN_3;
    assign _GEN_3 = io_enq_bits;
    wire _GEN_4;
    MUX_UNSIGNED #(.width(1)) u_mux_17 (
        .y(_GEN_4),
        .sel(do_enq),
        .a(_T_40),
        .b(_value__q)
    );
    wire wrap_1;
    EQ_UNSIGNED #(.width(1)) u_eq_18 (
        .y(wrap_1),
        .a(_value_1__q),
        .b(1'h1)
    );
    wire [1:0] _T_43;
    ADD_UNSIGNED #(.width(1)) u_add_19 (
        .y(_T_43),
        .a(_value_1__q),
        .b(1'h1)
    );
    wire _T_44;
    TAIL #(.width(2), .n(1)) tail_20 (
        .y(_T_44),
        .in(_T_43)
    );
    wire _GEN_5;
    MUX_UNSIGNED #(.width(1)) u_mux_21 (
        .y(_GEN_5),
        .sel(do_deq),
        .a(_T_44),
        .b(_value_1__q)
    );
    wire _T_45;
    NEQ_UNSIGNED #(.width(1)) u_neq_22 (
        .y(_T_45),
        .a(do_enq),
        .b(do_deq)
    );
    wire _GEN_6;
    MUX_UNSIGNED #(.width(1)) u_mux_23 (
        .y(_GEN_6),
        .sel(_T_45),
        .a(do_enq),
        .b(_maybe_full__q)
    );
    wire _T_47;
    EQ_UNSIGNED #(.width(1)) u_eq_24 (
        .y(_T_47),
        .a(empty),
        .b(1'h0)
    );
    wire _T_49;
    EQ_UNSIGNED #(.width(1)) u_eq_25 (
        .y(_T_49),
        .a(_T_31),
        .b(1'h0)
    );
    wire [1:0] _T_51;
    SUB_UNSIGNED #(.width(1)) u_sub_26 (
        .y(_T_51),
        .a(_value__q),
        .b(_value_1__q)
    );
    wire [1:0] _T_52;
    ASUINT #(.width(2)) asuint_27 (
        .y(_T_52),
        .in(_T_51)
    );
    wire _T_53;
    TAIL #(.width(2), .n(1)) tail_28 (
        .y(_T_53),
        .in(_T_52)
    );
    wire _T_54;
    BITWISEAND #(.width(1)) bitwiseand_29 (
        .y(_T_54),
        .a(_maybe_full__q),
        .b(_T_28)
    );
    wire [1:0] _T_55;
    CAT #(.width_a(1), .width_b(1)) cat_30 (
        .y(_T_55),
        .a(_T_54),
        .b(_T_53)
    );
    assign do_deq = _T_34;
    assign do_enq = _T_32;
    assign io_count = _T_55;
    assign io_deq_bits = ram__T_50_data;
    assign io_deq_valid = _T_47;
    assign io_enq_ready = _T_49;
    MUX_UNSIGNED #(.width(1)) u_mux_31 (
        .y(_maybe_full__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_6)
    );
    assign ram__T_36_addr = _GEN_0;
    assign ram__T_36_clk = _GEN_1;
    assign ram__T_36_data = _GEN_3;
    assign ram__T_36_en = _GEN_2;
    assign ram__T_36_mask = _GEN_2;
    assign ram__T_50_addr = _value_1__q;
    assign ram__T_50_clk = clock;
    assign ram__T_50_en = 1'h1;
    MUX_UNSIGNED #(.width(1)) u_mux_32 (
        .y(_value__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_4)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_33 (
        .y(_value_1__d),
        .sel(reset),
        .a(1'h0),
        .b(_GEN_5)
    );
endmodule