data/full_repos/permissive/470816788/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/470816788/verilog/rtl/user_project_wrapper.v:50: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470816788/verilog/rtl/user_project_wrapper.v:51: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470816788/verilog/rtl/user_project_wrapper.v:52: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470816788/verilog/rtl/user_project_wrapper.v:58: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);







wire [31:0] active = la_data_in[31:0];
wire [31:0] la1_data_in = la_data_in[63:32];
wire [31:0] la1_data_out = la_data_out[63:32];
wire [31:0] la1_oenb = la_oenb[63:32];

wrapped_hack_soc_dffram hack_soc (
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif
    
    .wb_clk_i (wb_clk_i),


    .active (active[11]),
    
    .la1_data_in (la1_data_in[31:0]),
    .la1_data_out (la1_data_out[31:0]),
    .la1_oenb (la1_oenb[31:0]),

    .io_in (io_in[37:0]),
    .io_out (io_out[37:0]),
    .io_oeb (io_oeb[37:0])
);



endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);








wire [31:0] active = la_data_in[31:0];
wire [31:0] la1_data_in = la_data_in[63:32];
wire [31:0] la1_data_out = la_data_out[63:32];
wire [31:0] la1_oenb = la_oenb[63:32];

wrapped_hack_soc_dffram hack_soc (
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif
    
    .wb_clk_i (wb_clk_i),


    .active (active[11]),
    
    .la1_data_in (la1_data_in[31:0]),
    .la1_data_out (la1_data_out[31:0]),
    .la1_oenb (la1_oenb[31:0]),

    .io_in (io_in[37:0]),
    .io_out (io_out[37:0]),
    .io_oeb (io_oeb[37:0])
);



endmodule