data/full_repos/permissive/460468583/data/verilog/adder.v
data/verilator_xmls/85e4a4ee-a347-4f37-aa35-a660e5f27190.xml
module full_add(a,b,cin,sum,cout);
  input a,b,cin;
  output sum,cout;
  wire x,y,z;


  half_add h1(.a(a),.b(b),.s(x),.c(y));
  half_add h2(.a(x),.b(cin),.s(sum),.c(z));
  or o1(cout,y,z);
endmodule
module full_add(a,b,cin,sum,cout);

  input a,b,cin;
  output sum,cout;
  wire x,y,z;


  half_add h1(.a(a),.b(b),.s(x),.c(y));
  half_add h2(.a(x),.b(cin),.s(sum),.c(z));
  or o1(cout,y,z);
endmodule