data/full_repos/permissive/427329267/src/both.v
1: b"%Error: data/full_repos/permissive/427329267/src/both.v:41: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  wire [`MPRJ_IO_PADS-1:0] io_in,   \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427329267/src/both.v:42: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_out,  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427329267/src/both.v:43: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_oeb,  \n                 ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module both(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,
`endif


`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);


    keyvalue_3 keyvalue3(
		       .sys_clk   (wb_clk_i),
		       .sys_rst_1   (wb_rst_i),
		       .STB_i     (wbs_stb_i),
		       .CYC_i     (wbs_cyc_i),
		       .WE_i      (wbs_we_i),

			 .ADR_IS_KEY_i (wbs_sel_i[0]),
 			 .DAT_IS_KEY_i (wbs_sel_i[1]),
		       .DAT_i     (wbs_dat_i),
		       .ADR_i     (wbs_adr_i),
		       .DAT_o     (wbs_dat_o[15:0]),
		       .DUP_o     (wbs_dat_o[16]),
		       .LA_o      (la_data_out)
		       );
   



    keyvalue_4 keyvalue4(
		       .ACK_o     (io_out[8]),
		       .sys_clk   (io_in[35]),
		       .sys_rst_1 (wb_rst_i),
		       .STB_i     (io_in[10]),
		       .WE_i      (io_in[11]),
		       .ADR_IS_KEY_i (io_in[19]),
 		       .DAT_IS_KEY_i (io_in[27]),			 
		       .DAT_i     (io_in[18:12]),
		       .ADR_i     (io_in[26:20]),
		       .DAT_o     (io_out[34:28]),


		       );
   

endmodule
module both(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,
`endif


`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);



    keyvalue_3 keyvalue3(
		       .sys_clk   (wb_clk_i),
		       .sys_rst_1   (wb_rst_i),
		       .STB_i     (wbs_stb_i),
		       .CYC_i     (wbs_cyc_i),
		       .WE_i      (wbs_we_i),

			 .ADR_IS_KEY_i (wbs_sel_i[0]),
 			 .DAT_IS_KEY_i (wbs_sel_i[1]),
		       .DAT_i     (wbs_dat_i),
		       .ADR_i     (wbs_adr_i),
		       .DAT_o     (wbs_dat_o[15:0]),
		       .DUP_o     (wbs_dat_o[16]),
		       .LA_o      (la_data_out)
		       );
   



    keyvalue_4 keyvalue4(
		       .ACK_o     (io_out[8]),
		       .sys_clk   (io_in[35]),
		       .sys_rst_1 (wb_rst_i),
		       .STB_i     (io_in[10]),
		       .WE_i      (io_in[11]),
		       .ADR_IS_KEY_i (io_in[19]),
 		       .DAT_IS_KEY_i (io_in[27]),			 
		       .DAT_i     (io_in[18:12]),
		       .ADR_i     (io_in[26:20]),
		       .DAT_o     (io_out[34:28]),


		       );
   

endmodule