data/full_repos/permissive/418692101/EnhancedSuperTestbench.sv
1: b'%Error: data/full_repos/permissive/418692101/EnhancedSuperTestbench.sv:2: Cannot find include file: TOP.v\n`include "TOP.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v.v\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v.sv\n             TOP.v\n             TOP.v.v\n             TOP.v.sv\n             obj_dir/TOP.v\n             obj_dir/TOP.v.v\n             obj_dir/TOP.v.sv\n%Error: Exiting due to 1 error(s)\n'
module EnhancedSuperTestbench;
    reg ini;
    reg clk;
    reg WR;
    reg CS;
    reg [9:0] ADDR;
    reg PassClock;
    reg [3:0] PassNumber;
    wire [31:0] DATA;
    EnhancedSRAM ES(clk, WR, CS, ADDR, PassClock, PassNumber, DATA);
    initial begin
        PassClock = 1'b1;
        PassNumber = 4'b0;
        ini = 1'b0;
    end
    always #(100 * `cycle) PassClock = ~PassClock;
    always @(negedge PassClock) begin
        if (ini == 1'b0) begin
            ini = 1'b1;
        end else begin
            PassNumber = PassNumber + 4'b1;
        end
    end
endmodule
module EnhancedSuperTestbench;

    reg ini;
    reg clk;
    reg WR;
    reg CS;
    reg [9:0] ADDR;
    reg PassClock;
    reg [3:0] PassNumber;
    wire [31:0] DATA;
    EnhancedSRAM ES(clk, WR, CS, ADDR, PassClock, PassNumber, DATA);
    initial begin
        PassClock = 1'b1;
        PassNumber = 4'b0;
        ini = 1'b0;
    end
    always #(100 * `cycle) PassClock = ~PassClock;
    always @(negedge PassClock) begin
        if (ini == 1'b0) begin
            ini = 1'b1;
        end else begin
            PassNumber = PassNumber + 4'b1;
        end
    end
endmodule