data/full_repos/permissive/504478691/PCF8591/integer_display.v
1: b'%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:31: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[31:28] = n / 10000000 % 10;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:32: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[27:24] = n / 1000000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:33: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[23:20] = n / 100000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:34: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[19:16] = n / 10000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:35: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[15:12] = n / 1000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:36: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[11:8] =  n / 100 % 10;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:37: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[7:4] =   n / 10 % 10;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:38: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[3:0] =   n / 1 % 10;\n                   ^\n%Error: Exiting due to 8 warning(s)\n'
module display7(input [3:0] iData, input cathode_ena, output reg [6:0] oData);
always @(iData)
begin
    if (cathode_ena == 1)
    case (iData)
        4'd0: oData = 7'b1000000;
        4'd1: oData = 7'b1111001;
        4'd2: oData = 7'b0100100;
        4'd3: oData = 7'b0110000;
        4'd4: oData = 7'b0011001;
        4'd5: oData = 7'b0010010;
        4'd6: oData = 7'b0000010;
        4'd7: oData = 7'b1111000;
        4'd8: oData = 7'b0000000;
        4'd9: oData = 7'b0010000;
        default: oData = 7'b1111111;
    endcase
    else
        oData = 7'b1111111;
end
endmodule
module display7(input [3:0] iData, input cathode_ena, output reg [6:0] oData);

always @(iData)
begin
    if (cathode_ena == 1)
    case (iData)
        4'd0: oData = 7'b1000000;
        4'd1: oData = 7'b1111001;
        4'd2: oData = 7'b0100100;
        4'd3: oData = 7'b0110000;
        4'd4: oData = 7'b0011001;
        4'd5: oData = 7'b0010010;
        4'd6: oData = 7'b0000010;
        4'd7: oData = 7'b1111000;
        4'd8: oData = 7'b0000000;
        4'd9: oData = 7'b0010000;
        default: oData = 7'b1111111;
    endcase
    else
        oData = 7'b1111111;
end
endmodule