data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v
1: b'%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:32: Cannot find include file: or1k_defines.v\n`include "or1k_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.sv\n             or1k_defines.v\n             or1k_defines.v.v\n             or1k_defines.v.sv\n             obj_dir/or1k_defines.v\n             obj_dir/or1k_defines.v.v\n             obj_dir/or1k_defines.v.sv\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:124: Define or directive not defined: \'`OR1K_SPR_PIC_BASE\'\n  wire spr_pic_cs = spr_pic_stb_r & (spr_bus_addr_r1[14:11] == `OR1K_SPR_PIC_BASE);  \n                                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:124: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire spr_pic_cs = spr_pic_stb_r & (spr_bus_addr_r1[14:11] == `OR1K_SPR_PIC_BASE);  \n                                                                                 ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:153: Define or directive not defined: \'`SPR_OFFSET\'\n            spr_picmr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:153: Define or directive not defined: \'`SPR_OFFSET\'\n            spr_picmr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));\n                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:153: Define or directive not defined: \'`OR1K_SPR_PICMR_ADDR\'\n            spr_picmr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));\n                                                                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:153: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            spr_picmr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));\n                                                                                                         ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:154: Define or directive not defined: \'`SPR_OFFSET\'\n            spr_picsr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:154: Define or directive not defined: \'`SPR_OFFSET\'\n            spr_picsr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));\n                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:154: Define or directive not defined: \'`OR1K_SPR_PICSR_ADDR\'\n            spr_picsr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));\n                                                                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v:154: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            spr_picsr_cs_r <= (`SPR_OFFSET(({1\'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));\n                                                                                                         ^\n%Error: Exiting due to 11 error(s)\n'
module or1k_marocchino_pic
#(
  parameter OPTION_PIC_TRIGGER    = "LEVEL",
  parameter OPTION_PIC_NMI_WIDTH  = 0
 )
(

  input             wb_clk,
  input             wb_rst,

  input             cpu_clk,
  input             cpu_rst,

  input      [31:0] irq_i,

  output reg        pic_rdy_o,


  input      [15:0] spr_bus_addr_i,
  input             spr_bus_we_i,
  input             spr_bus_stb_i,
  input             spr_bus_toggle_i,
  input      [31:0] spr_bus_dat_i,

  output reg [31:0] spr_bus_dat_pic_o,
  output reg        spr_bus_ack_pic_o
);


  reg [31:0] spr_picmr;
  reg [31:0] spr_picsr;

















  reg         spr_bus_stb_r1;
  reg         spr_bus_we_r1;
  reg  [14:0] spr_bus_addr_r1;
  reg  [31:0] spr_bus_dat_r1;

  always @(posedge wb_clk) begin
    spr_bus_stb_r1  <= spr_bus_stb_i;
    spr_bus_we_r1   <= spr_bus_we_i;
    spr_bus_addr_r1 <= spr_bus_addr_i[14:0];
    spr_bus_dat_r1  <= spr_bus_dat_i;
  end


  reg  cpu2pic_r1;
  reg  cpu2pic_r2;
  wire cpu2pic_pulse = cpu2pic_r2 ^ cpu2pic_r1;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      cpu2pic_r2 <= 1'b0;
      cpu2pic_r1 <= 1'b0;
    end
    else begin
      cpu2pic_r2 <= cpu2pic_r1;
      cpu2pic_r1 <= spr_bus_toggle_i;
    end
  end


  reg   spr_pic_stb_r;
  wire  spr_pic_ack;

  always @(posedge wb_clk) begin
    if (wb_rst)
      spr_pic_stb_r <= 1'b0;
    else if (spr_pic_ack)
      spr_pic_stb_r <= 1'b0;
    else if (cpu2pic_pulse)
      spr_pic_stb_r <= spr_bus_stb_r1;
  end


  wire spr_pic_cs = spr_pic_stb_r & (spr_bus_addr_r1[14:11] == `OR1K_SPR_PIC_BASE);
  reg  spr_picmr_cs_r;
  reg  spr_picsr_cs_r;


  wire [3:0] SPR_PIC_WAIT = 4'b0001,
             SPR_PIC_WE   = 4'b0010,
             SPR_PIC_RE   = 4'b0100,
             SPR_PIC_ACK  = 4'b1000;


  reg  [3:0] spr_pic_state;
  wire       spr_pic_we  = spr_pic_state[1];
  wire       spr_pic_re  = spr_pic_state[2];
  assign     spr_pic_ack = spr_pic_state[3];


  always @(posedge wb_clk) begin
    if (wb_rst) begin
      spr_picmr_cs_r <= 1'b0;
      spr_picsr_cs_r <= 1'b0;
      spr_pic_state  <= SPR_PIC_WAIT;
    end
    else begin
      (* parallel_case *)
      case (spr_pic_state)

        SPR_PIC_WAIT: begin
          if (spr_pic_cs) begin
            spr_picmr_cs_r <= (`SPR_OFFSET(({1'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));
            spr_picsr_cs_r <= (`SPR_OFFSET(({1'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));
            spr_pic_state  <= spr_bus_we_r1 ? SPR_PIC_WE : SPR_PIC_RE;
          end
        end

        SPR_PIC_WE,
        SPR_PIC_RE: begin
          spr_picmr_cs_r <= 1'b0;
          spr_picsr_cs_r <= 1'b0;
          spr_pic_state  <= SPR_PIC_ACK;
        end

        SPR_PIC_ACK: begin
          spr_pic_state  <= SPR_PIC_WAIT;
        end

        default: begin
        end
      endcase
    end
  end


  reg  [31:0] pic_dato_r;

  always @(posedge wb_clk) begin
    if (spr_pic_re)
      pic_dato_r <= spr_picmr_cs_r ? spr_picmr :
                     (spr_picsr_cs_r ? spr_picsr : 32'd0);
  end





  reg  pic2cpu_ack_r1;
  reg  pic2cpu_ack_r2;
  wire pic2cpu_ack_pulse = (~pic2cpu_ack_r2) & pic2cpu_ack_r1;

  always @(posedge cpu_clk) begin
    if (cpu_rst) begin
      pic2cpu_ack_r2 <= 1'b0;
      pic2cpu_ack_r1 <= 1'b0;
    end
    else begin
      pic2cpu_ack_r2 <= pic2cpu_ack_r1;
      pic2cpu_ack_r1 <= spr_pic_ack;
    end
  end


  reg  [31:0] pic2cpu_dato_r1;

  always @(posedge cpu_clk) begin
    pic2cpu_dato_r1 <= pic_dato_r;
  end


  always @(posedge cpu_clk) begin
    if (cpu_rst)
      spr_bus_ack_pic_o <= 1'b0;
    else
      spr_bus_ack_pic_o <= pic2cpu_ack_pulse;
  end

  always @(posedge cpu_clk) begin
    if (pic2cpu_ack_pulse)
      spr_bus_dat_pic_o <= pic2cpu_dato_r1;
    else
      spr_bus_dat_pic_o <= 32'd0;
  end



  reg  [31:0] spr_picsr_r1;

  always @(posedge cpu_clk) begin
    spr_picsr_r1 <= spr_picsr;
  end

  always @(posedge cpu_clk) begin
    if (cpu_rst)
      pic_rdy_o <= 1'b0;
    else
      pic_rdy_o <= (|spr_picsr_r1);
  end







  wire [31:0] irq_unmasked = spr_picmr & irq_i;


  wire [31:0] spr_pic_mask = {spr_bus_dat_r1[31:OPTION_PIC_NMI_WIDTH],
                              {OPTION_PIC_NMI_WIDTH{1'b1}}};


  always @(posedge wb_clk) begin
    if (wb_rst)
      spr_picmr <= {{(32-OPTION_PIC_NMI_WIDTH){1'b0}},
                    {OPTION_PIC_NMI_WIDTH{1'b1}}};
    else if (spr_picmr_cs_r & spr_pic_we)
      spr_picmr <= spr_pic_mask;
  end


  generate
  genvar  irqline;
  if (OPTION_PIC_TRIGGER == "EDGE") begin : edge_triggered

    reg  [31:0] irq_unmasked_r;
    wire [31:0] irq_unmasked_edge;

    always @(posedge wb_clk) begin
      if (wb_rst)
        irq_unmasked_r <= 32'd0;
      else
        irq_unmasked_r <= irq_unmasked;
    end

    for(irqline=0; irqline<32; irqline=irqline+1)  begin : picgenerate
      assign irq_unmasked_edge[irqline] = irq_unmasked[irqline] &
                                           ~irq_unmasked_r[irqline];


      always @(posedge wb_clk) begin
        if (wb_rst)
          spr_picsr[irqline] <= 1'b0;

        else if (irq_unmasked_edge[irqline])
          spr_picsr[irqline] <= 1'b1;

        else if (spr_picsr_cs_r & spr_pic_we & spr_bus_addr_r1[irqline])
          spr_picsr[irqline] <= 1'b0;
      end
    end

  end
  else if (OPTION_PIC_TRIGGER == "LEVEL") begin : level_triggered

    always @(irq_unmasked) begin
      spr_picsr = irq_unmasked;
    end

  end
  else if (OPTION_PIC_TRIGGER == "LATCHED_LEVEL") begin : latched_level

    always @(posedge wb_clk) begin
      if (wb_rst)
        spr_picsr <= 32'd0;
      else if (spr_picmr_cs_r & spr_pic_we)
        spr_picsr <= spr_pic_mask & spr_picsr;
      else if (spr_picsr_cs_r & spr_pic_we)
        spr_picsr <= irq_unmasked | spr_bus_addr_r1;
      else
        spr_picsr <= irq_unmasked | spr_picsr;
    end

  end
  else begin : invalid

    initial begin
      $display("Error - invalid PIC level detection option %s",
                OPTION_PIC_TRIGGER);
      $finish;
    end

  end
  endgenerate

endmodule
module or1k_marocchino_pic
#(
  parameter OPTION_PIC_TRIGGER    = "LEVEL",
  parameter OPTION_PIC_NMI_WIDTH  = 0
 )
(

  input             wb_clk,
  input             wb_rst,

  input             cpu_clk,
  input             cpu_rst,

  input      [31:0] irq_i,

  output reg        pic_rdy_o,


  input      [15:0] spr_bus_addr_i,
  input             spr_bus_we_i,
  input             spr_bus_stb_i,
  input             spr_bus_toggle_i,
  input      [31:0] spr_bus_dat_i,

  output reg [31:0] spr_bus_dat_pic_o,
  output reg        spr_bus_ack_pic_o
);



  reg [31:0] spr_picmr;
  reg [31:0] spr_picsr;

















  reg         spr_bus_stb_r1;
  reg         spr_bus_we_r1;
  reg  [14:0] spr_bus_addr_r1;
  reg  [31:0] spr_bus_dat_r1;

  always @(posedge wb_clk) begin
    spr_bus_stb_r1  <= spr_bus_stb_i;
    spr_bus_we_r1   <= spr_bus_we_i;
    spr_bus_addr_r1 <= spr_bus_addr_i[14:0];
    spr_bus_dat_r1  <= spr_bus_dat_i;
  end


  reg  cpu2pic_r1;
  reg  cpu2pic_r2;
  wire cpu2pic_pulse = cpu2pic_r2 ^ cpu2pic_r1;

  always @(posedge wb_clk) begin
    if (wb_rst) begin
      cpu2pic_r2 <= 1'b0;
      cpu2pic_r1 <= 1'b0;
    end
    else begin
      cpu2pic_r2 <= cpu2pic_r1;
      cpu2pic_r1 <= spr_bus_toggle_i;
    end
  end


  reg   spr_pic_stb_r;
  wire  spr_pic_ack;

  always @(posedge wb_clk) begin
    if (wb_rst)
      spr_pic_stb_r <= 1'b0;
    else if (spr_pic_ack)
      spr_pic_stb_r <= 1'b0;
    else if (cpu2pic_pulse)
      spr_pic_stb_r <= spr_bus_stb_r1;
  end


  wire spr_pic_cs = spr_pic_stb_r & (spr_bus_addr_r1[14:11] == `OR1K_SPR_PIC_BASE);
  reg  spr_picmr_cs_r;
  reg  spr_picsr_cs_r;


  wire [3:0] SPR_PIC_WAIT = 4'b0001,
             SPR_PIC_WE   = 4'b0010,
             SPR_PIC_RE   = 4'b0100,
             SPR_PIC_ACK  = 4'b1000;


  reg  [3:0] spr_pic_state;
  wire       spr_pic_we  = spr_pic_state[1];
  wire       spr_pic_re  = spr_pic_state[2];
  assign     spr_pic_ack = spr_pic_state[3];


  always @(posedge wb_clk) begin
    if (wb_rst) begin
      spr_picmr_cs_r <= 1'b0;
      spr_picsr_cs_r <= 1'b0;
      spr_pic_state  <= SPR_PIC_WAIT;
    end
    else begin
      (* parallel_case *)
      case (spr_pic_state)

        SPR_PIC_WAIT: begin
          if (spr_pic_cs) begin
            spr_picmr_cs_r <= (`SPR_OFFSET(({1'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));
            spr_picsr_cs_r <= (`SPR_OFFSET(({1'b0, spr_bus_addr_r1})) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));
            spr_pic_state  <= spr_bus_we_r1 ? SPR_PIC_WE : SPR_PIC_RE;
          end
        end

        SPR_PIC_WE,
        SPR_PIC_RE: begin
          spr_picmr_cs_r <= 1'b0;
          spr_picsr_cs_r <= 1'b0;
          spr_pic_state  <= SPR_PIC_ACK;
        end

        SPR_PIC_ACK: begin
          spr_pic_state  <= SPR_PIC_WAIT;
        end

        default: begin
        end
      endcase
    end
  end


  reg  [31:0] pic_dato_r;

  always @(posedge wb_clk) begin
    if (spr_pic_re)
      pic_dato_r <= spr_picmr_cs_r ? spr_picmr :
                     (spr_picsr_cs_r ? spr_picsr : 32'd0);
  end





  reg  pic2cpu_ack_r1;
  reg  pic2cpu_ack_r2;
  wire pic2cpu_ack_pulse = (~pic2cpu_ack_r2) & pic2cpu_ack_r1;

  always @(posedge cpu_clk) begin
    if (cpu_rst) begin
      pic2cpu_ack_r2 <= 1'b0;
      pic2cpu_ack_r1 <= 1'b0;
    end
    else begin
      pic2cpu_ack_r2 <= pic2cpu_ack_r1;
      pic2cpu_ack_r1 <= spr_pic_ack;
    end
  end


  reg  [31:0] pic2cpu_dato_r1;

  always @(posedge cpu_clk) begin
    pic2cpu_dato_r1 <= pic_dato_r;
  end


  always @(posedge cpu_clk) begin
    if (cpu_rst)
      spr_bus_ack_pic_o <= 1'b0;
    else
      spr_bus_ack_pic_o <= pic2cpu_ack_pulse;
  end

  always @(posedge cpu_clk) begin
    if (pic2cpu_ack_pulse)
      spr_bus_dat_pic_o <= pic2cpu_dato_r1;
    else
      spr_bus_dat_pic_o <= 32'd0;
  end



  reg  [31:0] spr_picsr_r1;

  always @(posedge cpu_clk) begin
    spr_picsr_r1 <= spr_picsr;
  end

  always @(posedge cpu_clk) begin
    if (cpu_rst)
      pic_rdy_o <= 1'b0;
    else
      pic_rdy_o <= (|spr_picsr_r1);
  end







  wire [31:0] irq_unmasked = spr_picmr & irq_i;


  wire [31:0] spr_pic_mask = {spr_bus_dat_r1[31:OPTION_PIC_NMI_WIDTH],
                              {OPTION_PIC_NMI_WIDTH{1'b1}}};


  always @(posedge wb_clk) begin
    if (wb_rst)
      spr_picmr <= {{(32-OPTION_PIC_NMI_WIDTH){1'b0}},
                    {OPTION_PIC_NMI_WIDTH{1'b1}}};
    else if (spr_picmr_cs_r & spr_pic_we)
      spr_picmr <= spr_pic_mask;
  end


  generate
  genvar  irqline;
  if (OPTION_PIC_TRIGGER == "EDGE") begin : edge_triggered

    reg  [31:0] irq_unmasked_r;
    wire [31:0] irq_unmasked_edge;

    always @(posedge wb_clk) begin
      if (wb_rst)
        irq_unmasked_r <= 32'd0;
      else
        irq_unmasked_r <= irq_unmasked;
    end

    for(irqline=0; irqline<32; irqline=irqline+1)  begin : picgenerate
      assign irq_unmasked_edge[irqline] = irq_unmasked[irqline] &
                                           ~irq_unmasked_r[irqline];


      always @(posedge wb_clk) begin
        if (wb_rst)
          spr_picsr[irqline] <= 1'b0;

        else if (irq_unmasked_edge[irqline])
          spr_picsr[irqline] <= 1'b1;

        else if (spr_picsr_cs_r & spr_pic_we & spr_bus_addr_r1[irqline])
          spr_picsr[irqline] <= 1'b0;
      end
    end

  end
  else if (OPTION_PIC_TRIGGER == "LEVEL") begin : level_triggered

    always @(irq_unmasked) begin
      spr_picsr = irq_unmasked;
    end

  end
  else if (OPTION_PIC_TRIGGER == "LATCHED_LEVEL") begin : latched_level

    always @(posedge wb_clk) begin
      if (wb_rst)
        spr_picsr <= 32'd0;
      else if (spr_picmr_cs_r & spr_pic_we)
        spr_picsr <= spr_pic_mask & spr_picsr;
      else if (spr_picsr_cs_r & spr_pic_we)
        spr_picsr <= irq_unmasked | spr_bus_addr_r1;
      else
        spr_picsr <= irq_unmasked | spr_picsr;
    end

  end
  else begin : invalid

    initial begin
      $display("Error - invalid PIC level detection option %s",
                OPTION_PIC_TRIGGER);
      $finish;
    end

  end
  endgenerate

endmodule