data/full_repos/permissive/493694849/rtl/AES_128_Encipher_Block.v
data/verilator_xmls/89c7a316-fdaf-416d-b2dc-4d38e9b56c10.xml
function [127:0] shiftrows;
    input [127:0] data;
    
    reg [31:0] w0, w1, w2, w3;
    reg [31:0] ws0, ws1, ws2, ws3;

    begin
        w0 = data[127:96];
        w1 = data[95:64];
        w2 = data[63:32];
        w3 = data[31:0];

        ws0 = {w0[31:24], w1[23:16], w2[15:8], w3[7:0]};
        ws1 = {w1[31:24], w2[23:16], w3[15:8], w0[7:0]};
        ws2 = {w2[31:24], w3[23:16], w0[15:8], w1[7:0]};
        ws3 = {w3[31:24], w0[23:16], w1[15:8], w2[7:0]};

        shiftrows = {ws0, ws1, ws2, ws3};
    end 
endfunction
function [127:0] shiftrows;

    input [127:0] data;
    
    reg [31:0] w0, w1, w2, w3;
    reg [31:0] ws0, ws1, ws2, ws3;

    begin
        w0 = data[127:96];
        w1 = data[95:64];
        w2 = data[63:32];
        w3 = data[31:0];

        ws0 = {w0[31:24], w1[23:16], w2[15:8], w3[7:0]};
        ws1 = {w1[31:24], w2[23:16], w3[15:8], w0[7:0]};
        ws2 = {w2[31:24], w3[23:16], w0[15:8], w1[7:0]};
        ws3 = {w3[31:24], w0[23:16], w1[15:8], w2[7:0]};

        shiftrows = {ws0, ws1, ws2, ws3};
    end 
endfunction