data/full_repos/permissive/505451992/E_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1;#125 \n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        reset = 0;#125;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        reset = 0;#125;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n       forever #125 CLK=~CLK;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    forever #2500 A=~A;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #2500\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    forever #2500 B=~B;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #3750\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n       forever #2500 D=~D;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n       #2500\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n       forever #2500 C=~C;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/E_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n       #3750\n       ^\n%Error: data/full_repos/permissive/505451992/E_tb.v:38: Cannot find file containing module: \'E_TOP\'\n       E_TOP utt(.reset(reset),\n       ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/E_TOP\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/E_TOP.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/E_TOP.sv\n             E_TOP\n             E_TOP.v\n             E_TOP.sv\n             obj_dir/E_TOP\n             obj_dir/E_TOP.v\n             obj_dir/E_TOP.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module E_tb(

    );
    
       reg reset;
       reg CLK;
       reg A;
       reg B;
       reg C;
       reg D;
       reg[2:0] R;
       reg[3:0] PR;
       wire PWM_CD;
       wire PWM_AB;
       
       E_TOP utt(.reset(reset),
       .clk(CLK),
       .PR(PR),
       .R(R),
       .A(A),
       .B(B),
       .C(C),
       .D(D),
       
       .PWM_AB(PWM_AB),
       .PWM_CD(PWM_CD));

           
           
        
        
        
        initial begin

         PR = 4'b1111;
        R=3'b000;
        reset = 1;#125 
        reset = 0;#125;
        reset = 0;#125;
        end
        
       initial begin
       CLK=0;
       forever #125 CLK=~CLK;
       end
    
    
    


             initial begin
    A=0;
    #2500
    forever #2500 A=~A;
    end

    initial begin
    B=0;
    #3750
    forever #2500 B=~B;
    end  
    
    
             initial begin
       D=0;
       #2500
       forever #2500 D=~D;
       end
       
       initial begin
       C=0;
       #3750
       forever #2500 C=~C;
       end  
     
        

  
          
  
    
    
    
    
    
    
endmodule
module E_tb(

    );

    
       reg reset;
       reg CLK;
       reg A;
       reg B;
       reg C;
       reg D;
       reg[2:0] R;
       reg[3:0] PR;
       wire PWM_CD;
       wire PWM_AB;
       
       E_TOP utt(.reset(reset),
       .clk(CLK),
       .PR(PR),
       .R(R),
       .A(A),
       .B(B),
       .C(C),
       .D(D),
       
       .PWM_AB(PWM_AB),
       .PWM_CD(PWM_CD));

           
           
        
        
        
        initial begin

         PR = 4'b1111;
        R=3'b000;
        reset = 1;#125 
        reset = 0;#125;
        reset = 0;#125;
        end
        
       initial begin
       CLK=0;
       forever #125 CLK=~CLK;
       end
    
    
    


             initial begin
    A=0;
    #2500
    forever #2500 A=~A;
    end

    initial begin
    B=0;
    #3750
    forever #2500 B=~B;
    end  
    
    
             initial begin
       D=0;
       #2500
       forever #2500 D=~D;
       end
       
       initial begin
       C=0;
       #3750
       forever #2500 C=~C;
       end  
     
        

  
          
  
    
    
    
    
    
    
endmodule