data/full_repos/permissive/516532406/New folder/New folder/control.v
1: b'%Error: Cannot find file containing module: folder/New\n        ... Looked in:\n             data/full_repos/permissive/516532406/New/folder/New\n             data/full_repos/permissive/516532406/New/folder/New.v\n             data/full_repos/permissive/516532406/New/folder/New.sv\n             folder/New\n             folder/New.v\n             folder/New.sv\n             obj_dir/folder/New\n             obj_dir/folder/New.v\n             obj_dir/folder/New.sv\n%Error: Cannot find file containing module: folder,data/full_repos/permissive/516532406\n%Error: Cannot find file containing module: data/full_repos/permissive/516532406/New\n%Error: Cannot find file containing module: folder/control.v\n%Error: Exiting due to 4 error(s)\n'
module Controlunit(input [5:0] Opcode, 
               input [5:0] Func,
               input Zero,
               output reg MemtoReg,
               output reg  MemWrite,
               output reg  ALUSrc,
               output reg  RegDst,
               output reg  RegWrite,
               output reg  Jump,
               output PCSrc,
               output reg  [3:0] ALUControl
               );
               
reg [7:0] temp;
reg Branch,B;

always @(*) begin 

    case (Opcode) 
        6'b000000: begin
                    temp <= 8'b11000000;        

                    case (Func)
                    6'b100000: ALUControl <= 4'b0000;
                    6'b100001: ALUControl <= 4'b0000;
                    6'b100010: ALUControl <= 4'b0001;
                    6'b100011: ALUControl <= 4'b0001;
                    6'b100100: ALUControl <= 4'b0010;
                    6'b100101: ALUControl <= 4'b0011;
                    6'b100110: ALUControl <= 4'b0100;
                    6'b100111: ALUControl <= 4'b1010;
                    6'b101010: ALUControl <= 4'b1000;
                    6'b101011: ALUControl <= 4'b1001;
                    6'b000000: ALUControl <= 4'b0101;
                    6'b000010: ALUControl <= 4'b0110;
                    6'b000011: ALUControl <= 4'b0111;
                    6'b000100: ALUControl <= 4'b1011;
                    6'b000110: ALUControl <= 4'b1100;
                    6'b000111: ALUControl <= 4'b1101;
                endcase

            end

        6'b100011: begin
                        temp <= 8'b10100100;     
                        ALUControl <= 4'b0000;
                    end

        6'b101011: begin
                         temp <= 8'b00101000;      
                         ALUControl <= 4'b0000;
                    end  

        6'b000100: begin
                         temp <= 8'b00010000;      
                        ALUControl <= 4'b0001; 
                    end      

        6'b000101: begin
                        temp <= 8'b00010001;  
                        ALUControl <= 4'b0001; 
                    end

        6'b001000: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0000; 
                    end  

        6'b001001: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0000; 
                    end  

        6'b001100: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0010; 
                    end 

        6'b001101: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0011; 
                    end  

        6'b001110: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0100; 
                    end       

        6'b001010: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1000; 
                    end 

        6'b001011: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1001; 
                    end  

        6'b000010: begin
                        temp <= 8'b00000010;  
                        ALUControl <= 4'b0010; 
                    end 
                        
        6'b001111:  begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1110; 
                    end          
        default:   temp <= 12'bxxxxxxxxxxxx;
    endcase
   

    
    {RegWrite,RegDst,ALUSrc,Branch,MemWrite,MemtoReg,Jump,B} = temp;

end 

assign PCSrc = Branch & (Zero ^ B);

endmodule
module Controlunit(input [5:0] Opcode, 
               input [5:0] Func,
               input Zero,
               output reg MemtoReg,
               output reg  MemWrite,
               output reg  ALUSrc,
               output reg  RegDst,
               output reg  RegWrite,
               output reg  Jump,
               output PCSrc,
               output reg  [3:0] ALUControl
               );

               
reg [7:0] temp;
reg Branch,B;

always @(*) begin 

    case (Opcode) 
        6'b000000: begin
                    temp <= 8'b11000000;        

                    case (Func)
                    6'b100000: ALUControl <= 4'b0000;
                    6'b100001: ALUControl <= 4'b0000;
                    6'b100010: ALUControl <= 4'b0001;
                    6'b100011: ALUControl <= 4'b0001;
                    6'b100100: ALUControl <= 4'b0010;
                    6'b100101: ALUControl <= 4'b0011;
                    6'b100110: ALUControl <= 4'b0100;
                    6'b100111: ALUControl <= 4'b1010;
                    6'b101010: ALUControl <= 4'b1000;
                    6'b101011: ALUControl <= 4'b1001;
                    6'b000000: ALUControl <= 4'b0101;
                    6'b000010: ALUControl <= 4'b0110;
                    6'b000011: ALUControl <= 4'b0111;
                    6'b000100: ALUControl <= 4'b1011;
                    6'b000110: ALUControl <= 4'b1100;
                    6'b000111: ALUControl <= 4'b1101;
                endcase

            end

        6'b100011: begin
                        temp <= 8'b10100100;     
                        ALUControl <= 4'b0000;
                    end

        6'b101011: begin
                         temp <= 8'b00101000;      
                         ALUControl <= 4'b0000;
                    end  

        6'b000100: begin
                         temp <= 8'b00010000;      
                        ALUControl <= 4'b0001; 
                    end      

        6'b000101: begin
                        temp <= 8'b00010001;  
                        ALUControl <= 4'b0001; 
                    end

        6'b001000: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0000; 
                    end  

        6'b001001: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0000; 
                    end  

        6'b001100: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0010; 
                    end 

        6'b001101: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0011; 
                    end  

        6'b001110: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b0100; 
                    end       

        6'b001010: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1000; 
                    end 

        6'b001011: begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1001; 
                    end  

        6'b000010: begin
                        temp <= 8'b00000010;  
                        ALUControl <= 4'b0010; 
                    end 
                        
        6'b001111:  begin
                        temp <= 8'b10100000;  
                        ALUControl <= 4'b1110; 
                    end          
        default:   temp <= 12'bxxxxxxxxxxxx;
    endcase
   

    
    {RegWrite,RegDst,ALUSrc,Branch,MemWrite,MemtoReg,Jump,B} = temp;

end 

assign PCSrc = Branch & (Zero ^ B);

endmodule