data/full_repos/permissive/430260837/segmentDisplay.v
data/verilator_xmls/3e088ea8-5607-49a9-bb14-78a696128c16.xml
module segmentDisplay (input [3:0] a, output [6:0] b);





	





	

	assign b[0] = (~a[3] & ~a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & ~a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & a[0]);


	



	assign b[1] = (~a[3] & a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & a[1] & ~a[0]) | (a[3] & a[1] & a[0]) | (a[3] & a[2] & ~a[0]);


	



	assign b[6] = (~a[3] & ~a[2] & ~a[1]) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & ~a[0]);







	assign b[5] = ( (~a[3] & ~a[2]) & ( (~a[1] & a[0]) | a[1] ) ) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & a[0]);


	



	assign b[2] = (~a[3] & ~a[2] & a[1] & ~a[0]) | (a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & a[2] & a[1]);


	



	assign b[3] = (~a[3] & ~a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & ~a[2] & a[1] & ~a[0]) | (a[2] & a[1] & a[0]);

	



	assign b[4] = (~a[3] & ~a[2] & a[0]) | (~a[3] & a[2] & ~a[1]) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & ~a[2] & ~a[1] & a[0]);

endmodule
module segmentDisplay (input [3:0] a, output [6:0] b);






	





	

	assign b[0] = (~a[3] & ~a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & ~a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & a[0]);


	



	assign b[1] = (~a[3] & a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & a[1] & ~a[0]) | (a[3] & a[1] & a[0]) | (a[3] & a[2] & ~a[0]);


	



	assign b[6] = (~a[3] & ~a[2] & ~a[1]) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & ~a[0]);







	assign b[5] = ( (~a[3] & ~a[2]) & ( (~a[1] & a[0]) | a[1] ) ) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & a[2] & ~a[1] & a[0]);


	



	assign b[2] = (~a[3] & ~a[2] & a[1] & ~a[0]) | (a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & a[2] & a[1]);


	



	assign b[3] = (~a[3] & ~a[2] & ~a[1] & a[0]) | (~a[3] & a[2] & ~a[1] & ~a[0]) | (a[3] & ~a[2] & a[1] & ~a[0]) | (a[2] & a[1] & a[0]);

	



	assign b[4] = (~a[3] & ~a[2] & a[0]) | (~a[3] & a[2] & ~a[1]) | (~a[3] & a[2] & a[1] & a[0]) | (a[3] & ~a[2] & ~a[1] & a[0]);

endmodule