data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:34: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:47: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:48: Unsupported: Ignoring delay on this delayed statement.\n               #2 \n               ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:44: Unsupported: Ignoring delay on this delayed statement.\n        #40\n        ^\n%Error: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:57: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:58: Unsupported: Ignoring delay on this delayed statement.\n       #2 wrreq = 1\'b0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/SynFifo_tb.sv:60: Unsupported: Ignoring delay on this delayed statement.\n       #200 $finish;\n       ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SynFifo_tb;
bit clk;
bit arstn;
bit [7:0]data_in;
bit wrreq;
bit rdreq;
wire [7:0]data_out;
wire [7:0]usedw;
wire empty;
wire full;

always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        wrreq = 1'b0;
        rdreq = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        #40
        for(int i = 1;i<40;i=i+1)
            begin
                @(posedge clk);
               #2 
                wrreq = 1'b1;
                data_in = i;
                
                if(i == 20)
                    begin
                        rdreq = 1'b1;
                    end
            end
       @(posedge clk);
       #2 wrreq = 1'b0;
       
       #200 $finish;
    end

SynFifo #
(
    .DATA_WIDTH(8),
    .FIFO_DEPTH(256)
)DUT
(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .wrreq(wrreq),
    .rdreq(rdreq),
    .data_out(data_out),
    .usedw(usedw),
    .empty(empty),
    .full(full)
);
endmodule
module SynFifo_tb;

bit clk;
bit arstn;
bit [7:0]data_in;
bit wrreq;
bit rdreq;
wire [7:0]data_out;
wire [7:0]usedw;
wire empty;
wire full;

always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        wrreq = 1'b0;
        rdreq = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        #40
        for(int i = 1;i<40;i=i+1)
            begin
                @(posedge clk);
               #2 
                wrreq = 1'b1;
                data_in = i;
                
                if(i == 20)
                    begin
                        rdreq = 1'b1;
                    end
            end
       @(posedge clk);
       #2 wrreq = 1'b0;
       
       #200 $finish;
    end

SynFifo #
(
    .DATA_WIDTH(8),
    .FIFO_DEPTH(256)
)DUT
(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .wrreq(wrreq),
    .rdreq(rdreq),
    .data_out(data_out),
    .usedw(usedw),
    .empty(empty),
    .full(full)
);
endmodule