data/full_repos/permissive/443520440/testbench/sccb_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/443520440/testbench/sccb_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/443520440/testbench/sccb_tb.v:9: Cannot find file containing module: \'ov2640_sccb_cfg_init\'\n    ov2640_sccb_cfg_init ov2640_sccb_cfg_init_0(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/ov2640_sccb_cfg_init\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/ov2640_sccb_cfg_init.v\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/ov2640_sccb_cfg_init.sv\n             ov2640_sccb_cfg_init\n             ov2640_sccb_cfg_init.v\n             ov2640_sccb_cfg_init.sv\n             obj_dir/ov2640_sccb_cfg_init\n             obj_dir/ov2640_sccb_cfg_init.v\n             obj_dir/ov2640_sccb_cfg_init.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ov2640_sccb_cfg_init_tb();
    reg clk;
    reg ctl;
    reg rst;
    wire sio_c;
    wire sio_d;
    wire reset,pwdn,xclk;
    wire camera_init_done;
    ov2640_sccb_cfg_init ov2640_sccb_cfg_init_0(
        clk,
        rst,
        sio_c,
        sio_d,
        reset,
        pwdn,
        xclk,
        4'b0,
        camera_init_done
    );
    initial begin
        clk = 0; rst = 0;ctl = 0;
    end
    always #1 clk = ~clk;
endmodule
module ov2640_sccb_cfg_init_tb();

    reg clk;
    reg ctl;
    reg rst;
    wire sio_c;
    wire sio_d;
    wire reset,pwdn,xclk;
    wire camera_init_done;
    ov2640_sccb_cfg_init ov2640_sccb_cfg_init_0(
        clk,
        rst,
        sio_c,
        sio_d,
        reset,
        pwdn,
        xclk,
        4'b0,
        camera_init_done
    );
    initial begin
        clk = 0; rst = 0;ctl = 0;
    end
    always #1 clk = ~clk;
endmodule