data/full_repos/permissive/447976230/fpga/usrp3/top/x400/qsfp_led_controller.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/qsfp_led_controller.v:53: Cannot find file containing module: 'synchronizer'\n  synchronizer #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/synchronizer\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/synchronizer.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: Exiting due to 1 error(s)\n"
module qsfp_led_controller #(
  parameter LED_REGISTER_ADDRESS = 0
) (

  input wire ctrlport_clk,
  input wire ctrlport_rst,


  output reg         m_ctrlport_req_wr,
  output wire        m_ctrlport_req_rd,
  output wire [19:0] m_ctrlport_req_addr,
  output wire [31:0] m_ctrlport_req_data,
  output wire [ 3:0] m_ctrlport_req_byte_en,


  input wire        m_ctrlport_resp_ack,
  input wire [ 1:0] m_ctrlport_resp_status,
  input wire [31:0] m_ctrlport_resp_data,


  input wire [3:0] qsfp0_led_active,
  input wire [3:0] qsfp0_led_link,
  input wire [3:0] qsfp1_led_active,
  input wire [3:0] qsfp1_led_link
);





  wire [15:0] led_combined;

  synchronizer #(
    .WIDTH            (16),
    .STAGES           (2),
    .INITIAL_VAL      (0),
    .FALSE_PATH_TO_IN (1)
  ) synchronizer_i (
    .clk (ctrlport_clk),
    .rst (ctrlport_rst),
    .in  ({qsfp1_led_active, qsfp1_led_link, qsfp0_led_active, qsfp0_led_link}),
    .out (led_combined)
  );





  reg transfer_in_progress;
  reg [15:0] led_combined_delayed;

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr <= 1'b0;
      transfer_in_progress <= 1'b0;
      led_combined_delayed <= 16'b0;
    end else begin

      m_ctrlport_req_wr <= 1'b0;


      if (led_combined != led_combined_delayed && ~transfer_in_progress) begin
        transfer_in_progress <= 1'b1;
        m_ctrlport_req_wr <= 1'b1;
        led_combined_delayed <= led_combined;
      end


      if (m_ctrlport_resp_ack) begin
        transfer_in_progress <= 1'b0;
      end
    end
  end





  assign m_ctrlport_req_rd      = 0;
  assign m_ctrlport_req_byte_en = 4'b0011;
  assign m_ctrlport_req_addr    = LED_REGISTER_ADDRESS;
  assign m_ctrlport_req_data    = {16'b0, led_combined_delayed};

endmodule
module qsfp_led_controller #(
  parameter LED_REGISTER_ADDRESS = 0
) (

  input wire ctrlport_clk,
  input wire ctrlport_rst,


  output reg         m_ctrlport_req_wr,
  output wire        m_ctrlport_req_rd,
  output wire [19:0] m_ctrlport_req_addr,
  output wire [31:0] m_ctrlport_req_data,
  output wire [ 3:0] m_ctrlport_req_byte_en,


  input wire        m_ctrlport_resp_ack,
  input wire [ 1:0] m_ctrlport_resp_status,
  input wire [31:0] m_ctrlport_resp_data,


  input wire [3:0] qsfp0_led_active,
  input wire [3:0] qsfp0_led_link,
  input wire [3:0] qsfp1_led_active,
  input wire [3:0] qsfp1_led_link
);






  wire [15:0] led_combined;

  synchronizer #(
    .WIDTH            (16),
    .STAGES           (2),
    .INITIAL_VAL      (0),
    .FALSE_PATH_TO_IN (1)
  ) synchronizer_i (
    .clk (ctrlport_clk),
    .rst (ctrlport_rst),
    .in  ({qsfp1_led_active, qsfp1_led_link, qsfp0_led_active, qsfp0_led_link}),
    .out (led_combined)
  );





  reg transfer_in_progress;
  reg [15:0] led_combined_delayed;

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr <= 1'b0;
      transfer_in_progress <= 1'b0;
      led_combined_delayed <= 16'b0;
    end else begin

      m_ctrlport_req_wr <= 1'b0;


      if (led_combined != led_combined_delayed && ~transfer_in_progress) begin
        transfer_in_progress <= 1'b1;
        m_ctrlport_req_wr <= 1'b1;
        led_combined_delayed <= led_combined;
      end


      if (m_ctrlport_resp_ack) begin
        transfer_in_progress <= 1'b0;
      end
    end
  end





  assign m_ctrlport_req_rd      = 0;
  assign m_ctrlport_req_byte_en = 4'b0011;
  assign m_ctrlport_req_addr    = LED_REGISTER_ADDRESS;
  assign m_ctrlport_req_data    = {16'b0, led_combined_delayed};

endmodule