data/full_repos/permissive/445455582/single/tb/memory_tb.v
1: b'%Error: data/full_repos/permissive/445455582/single/tb/memory_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/tb/memory_tb.v:23: Cannot find include file: RiSC16_memory.v\n`include "RiSC16_memory.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/memory_tb.v:49: Unsupported or unknown PLI call: $monitor\n        $monitor("%g: writeEn %h, rst %h, address %h, dataIn %h, dataOut %h", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/memory_tb.v:52: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("memory_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/memory_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, memory_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/memory_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10         address     <= 15\'h1222;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/memory_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #10         rst         <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/memory_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10         $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/memory_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    always #7 clk <= ~clk;\n           ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module memory_tb;

    wire [15:0] dataOut;
    
    reg [15:0] address = 16'b0000;
    reg [15:0] dataIn = 16'b0000;
    reg clk = 0;
    reg writeEn = 0;
    reg rst = 0;

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(65536)
    ) mem (
        .dataOut(dataOut),
        .address(address), 
        .dataIn(dataIn), 
        .clk(clk), 
        .writeEn(writeEn),
        .rst(rst)
    );

    initial begin
        $monitor("%g: writeEn %h, rst %h, address %h, dataIn %h, dataOut %h", 
            $time, writeEn, rst, address, dataIn, dataOut);

        $dumpfile("memory_tb.vcd");
        $dumpvars(0, memory_tb);

        #10         address     <= 15'h1222;
                    dataIn      <= 15'h2000;
                    writeEn     <= 1;
                    rst         <= 0;
        
        #10         rst         <= 1;
                    writeEn     <= 0;

        #10         $finish;
    end

    always #7 clk <= ~clk;

endmodule
module memory_tb;


    wire [15:0] dataOut;
    
    reg [15:0] address = 16'b0000;
    reg [15:0] dataIn = 16'b0000;
    reg clk = 0;
    reg writeEn = 0;
    reg rst = 0;

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(65536)
    ) mem (
        .dataOut(dataOut),
        .address(address), 
        .dataIn(dataIn), 
        .clk(clk), 
        .writeEn(writeEn),
        .rst(rst)
    );

    initial begin
        $monitor("%g: writeEn %h, rst %h, address %h, dataIn %h, dataOut %h", 
            $time, writeEn, rst, address, dataIn, dataOut);

        $dumpfile("memory_tb.vcd");
        $dumpvars(0, memory_tb);

        #10         address     <= 15'h1222;
                    dataIn      <= 15'h2000;
                    writeEn     <= 1;
                    rst         <= 0;
        
        #10         rst         <= 1;
                    writeEn     <= 0;

        #10         $finish;
    end

    always #7 clk <= ~clk;

endmodule