data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v
1: b'%Error: data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v:12: Unsupported or unknown PLI call: $monitor\n  $monitor("%b (%d) -> %b (%d)", Ain, Ain_signed, Aout, Aout_signed);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 Ain = 255;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 Ain = 127;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 Ain = 128;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/474721296/twos_comp/twos_comp_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 Ain = 0;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module twos_comp_tb;
	reg[7:0] Ain;
	wire[7:0] Aout;
	wire signed[7:0] Ain_signed = Ain;
	wire signed[7:0] Aout_signed = Aout;

	twos_comp test(Ain, Aout);

	initial begin
		$monitor("%b (%d) -> %b (%d)", Ain, Ain_signed, Aout, Aout_signed);
	end

	initial begin
		Ain = 9;
		#1 Ain = 255;
		#1 Ain = 127;
		#1 Ain = 128;
		#1 Ain = 0;
	end
endmodule
module twos_comp_tb;

	reg[7:0] Ain;
	wire[7:0] Aout;
	wire signed[7:0] Ain_signed = Ain;
	wire signed[7:0] Aout_signed = Aout;

	twos_comp test(Ain, Aout);

	initial begin
		$monitor("%b (%d) -> %b (%d)", Ain, Ain_signed, Aout, Aout_signed);
	end

	initial begin
		Ain = 9;
		#1 Ain = 255;
		#1 Ain = 127;
		#1 Ain = 128;
		#1 Ain = 0;
	end
endmodule