data/full_repos/permissive/518305937/iiitb_gc_Physical_Design/src/iiitb_gc.v
data/verilator_xmls/14327bba-6863-4f9b-8d54-2edd5969d971.xml
module iiitb_gc ( clk, enable, reset, gray_count);
  
 
  input clk, reset, enable; 
  output [ 7:0] gray_count;
  reg [7:0] count;
  
  always @ (posedge clk) 
  if (reset) 
    count <= 0; 
  else if (enable) 
    count <= count + 1; 
    
  assign gray_count = { count[7], (count[7] ^ count[6]),(count[6] ^ 
               count[5]),(count[5] ^ count[4]), (count[4] ^ 
               count[3]),(count[3] ^ count[2]), (count[2] ^ 
               count[1]),(count[1] ^ count[0]) };
    
endmodule
module iiitb_gc ( clk, enable, reset, gray_count);

  
 
  input clk, reset, enable; 
  output [ 7:0] gray_count;
  reg [7:0] count;
  
  always @ (posedge clk) 
  if (reset) 
    count <= 0; 
  else if (enable) 
    count <= count + 1; 
    
  assign gray_count = { count[7], (count[7] ^ count[6]),(count[6] ^ 
               count[5]),(count[5] ^ count[4]), (count[4] ^ 
               count[3]),(count[3] ^ count[2]), (count[2] ^ 
               count[1]),(count[1] ^ count[0]) };
    
endmodule