data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlmultiple.v
data/verilator_xmls/cbeb622d-9a92-488d-9726-b126f9a1c9c5.xml
module at6rtlmultiple
    (
     clk,
     rst,

     vali,
     a,
     b,

     valo,
     c
     );




parameter BITA = 32;
parameter BITB = 16;
parameter BITC = BITA + BITB;




input               clk;
input               rst;

input               vali;
input [BITA-1:0]    a;
input [BITB-1:0]    b;

output              valo;
output [BITC-1:0]   c;




reg [BITC-1:0] ashift;
reg [BITB-1:0] bshift;
reg [BITB:0]   position;
reg [BITC-1:0] c;

always @(posedge clk)
    begin
    if(rst)
        begin
        ashift <= {BITC{1'b0}};
        bshift <= {BITB{1'b0}};
        position <= {(BITB+1){1'b0}};
        c <= {BITC{1'b0}};
        end
    else if(vali)
        begin
        ashift <= {{BITB{1'b0}},a};
        bshift <= b;
        position <= {{BITB{1'b0}},1'b1};
        c <= {BITC{1'b0}};
        end
    else
        begin
        ashift <= {ashift[BITC-2:0],1'b0};
        bshift <= {1'b0,bshift[BITB-1:1]};
        position <= {position[BITB-1:0],1'b0};
        if(bshift[0]) c <= c + ashift;
        end
    end

wire        valo;
assign      valo = position[BITB];

endmodule
module at6rtlmultiple
    (
     clk,
     rst,

     vali,
     a,
     b,

     valo,
     c
     );





parameter BITA = 32;
parameter BITB = 16;
parameter BITC = BITA + BITB;




input               clk;
input               rst;

input               vali;
input [BITA-1:0]    a;
input [BITB-1:0]    b;

output              valo;
output [BITC-1:0]   c;




reg [BITC-1:0] ashift;
reg [BITB-1:0] bshift;
reg [BITB:0]   position;
reg [BITC-1:0] c;

always @(posedge clk)
    begin
    if(rst)
        begin
        ashift <= {BITC{1'b0}};
        bshift <= {BITB{1'b0}};
        position <= {(BITB+1){1'b0}};
        c <= {BITC{1'b0}};
        end
    else if(vali)
        begin
        ashift <= {{BITB{1'b0}},a};
        bshift <= b;
        position <= {{BITB{1'b0}},1'b1};
        c <= {BITC{1'b0}};
        end
    else
        begin
        ashift <= {ashift[BITC-2:0],1'b0};
        bshift <= {1'b0,bshift[BITB-1:1]};
        position <= {position[BITB-1:0],1'b0};
        if(bshift[0]) c <= c + ashift;
        end
    end

wire        valo;
assign      valo = position[BITB];

endmodule