data/full_repos/permissive/522145661/Test_F_Master.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:47: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK=~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:50: Unsupported: Ignoring delay on this delayed statement.\n #593 RST = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:51: Unsupported: Ignoring delay on this delayed statement.\n #40 RST = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #100 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'b0; U_WDATA = 32\'bx; U_SLAVE = 2\'b00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12\'d3; U_WDATA = $random; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #40 HGRANT = 1; HRESP = 2\'b00; #20 HREADY = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #40 HGRANT = 1; HRESP = 2\'b00; #20 HREADY = 1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'b0; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'b0; U_SLAVE = 2\'b01;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:82: Unsupported: Ignoring delay on this delayed statement.\n     HGRANT = 0; HRESP = 2\'b00; #40 HREADY = 1\'bz;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12\'d3; U_WDATA = $random; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #100 HGRANT = 1; HRESP = 2\'b00; #20 HREADY = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #100 HGRANT = 1; HRESP = 2\'b00; #20 HREADY = 1;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'b0; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'b0; U_SLAVE = 2\'b01;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:89: Unsupported: Ignoring delay on this delayed statement.\n     HGRANT = 0; HRESP = 2\'b00; #40 HREADY = 1\'bz;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100 U_REQ = 1; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'d3; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:93: Unsupported: Ignoring delay on this delayed statement.\n    HRESP = 2\'b00; #40 HGRANT = 1; #20 HREADY = 1;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:93: Unsupported: Ignoring delay on this delayed statement.\n    HRESP = 2\'b00; #40 HGRANT = 1; #20 HREADY = 1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #40 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'d3; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12\'d3; U_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #70 HGRANT = 0; #20 HRDATA = 32\'bx; HREADY = 1\'bz;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_F_Master.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #70 HGRANT = 0; #20 HRDATA = 32\'bx; HREADY = 1\'bz;\n                  ^\n%Error: data/full_repos/permissive/522145661/Test_F_Master.v:27: Cannot find file containing module: \'Master\'\n Master uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Master\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Master.v\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Master.sv\n             Master\n             Master.v\n             Master.sv\n             obj_dir/Master\n             obj_dir/Master.v\n             obj_dir/Master.sv\n%Warning-WIDTH: data/full_repos/permissive/522145661/Test_F_Master.v:65: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bxxxxxxxxxxxxxxxx\' generates 16 bits.\n                                                                       : ... In instance Test_F_Master\n  U_ADDR = 16\'bx;\n         ^\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_F_Master;


	reg CLK;
	reg RST;
	reg HGRANT;
	reg HREADY;
	reg [1:0] HRESP;
	reg [31:0] HRDATA;
	reg U_REQ;
	reg U_LOCK;
	reg U_WRITE;
	reg [11:0] U_ADDR;
	reg [31:0] U_WDATA;
	reg [1:0] U_SLAVE;


	wire HREQ;
	wire HLOCK;
	wire [15:0] HADDR;
	wire [31:0] HWDATA;
	wire AB;


	Master uut (
		.CLK(CLK), 
		.RST(RST), 
		.HGRANT(HGRANT), 
		.HREADY(HREADY), 
		.HRESP(HRESP), 
		.HRDATA(HRDATA), 
		.HREQ(HREQ), 
		.HLOCK(HLOCK), 
		.HADDR(HADDR), 
		.HWDATA(HWDATA), 
		.AB(AB), 
		.U_REQ(U_REQ), 
		.U_LOCK(U_LOCK), 
		.U_WRITE(U_WRITE), 
		.U_ADDR(U_ADDR), 
		.U_WDATA(U_WDATA), 
		.U_SLAVE(U_SLAVE)
	);
	
	always #10 CLK=~CLK;
	
	initial begin
	#593 RST = 1;
	#40 RST = 0;
	end

	initial begin

		CLK = 0;
		RST = 0;
		HGRANT = 0;
		HREADY = 1'bz;
		HRESP = 0;
		HRDATA = 32'bx;
		U_REQ = 0;
		U_LOCK = 0;
		U_WRITE = 0;
		U_ADDR = 16'bx;
		U_WDATA = 32'bx;
		U_SLAVE = 0;


		#100;
        

		
		#100 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_WDATA = 32'bx; U_SLAVE = 2'b00;
				HGRANT = 0; HRESP = 2'b00; HREADY = 1'bz;
		

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12'd3; U_WDATA = $random; U_SLAVE = 2'b01;
				#40 HGRANT = 1; HRESP = 2'b00; #20 HREADY = 1;
				
		#40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_SLAVE = 2'b01;
				 HGRANT = 0; HRESP = 2'b00; #40 HREADY = 1'bz;
				 

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12'd3; U_WDATA = $random; U_SLAVE = 2'b01;
				#100 HGRANT = 1; HRESP = 2'b00; #20 HREADY = 1;
				
		#40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_SLAVE = 2'b01;
				 HGRANT = 0; HRESP = 2'b00; #40 HREADY = 1'bz;
		

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; #40 HGRANT = 1; #20 HREADY = 1;
				
		#40 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; HRDATA = U_WDATA;
				
		#10 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; HREADY = 1; 
				
		#70 HGRANT = 0; #20 HRDATA = 32'bx; HREADY = 1'bz;


		

	end
      
endmodule
module Test_F_Master;



	reg CLK;
	reg RST;
	reg HGRANT;
	reg HREADY;
	reg [1:0] HRESP;
	reg [31:0] HRDATA;
	reg U_REQ;
	reg U_LOCK;
	reg U_WRITE;
	reg [11:0] U_ADDR;
	reg [31:0] U_WDATA;
	reg [1:0] U_SLAVE;


	wire HREQ;
	wire HLOCK;
	wire [15:0] HADDR;
	wire [31:0] HWDATA;
	wire AB;


	Master uut (
		.CLK(CLK), 
		.RST(RST), 
		.HGRANT(HGRANT), 
		.HREADY(HREADY), 
		.HRESP(HRESP), 
		.HRDATA(HRDATA), 
		.HREQ(HREQ), 
		.HLOCK(HLOCK), 
		.HADDR(HADDR), 
		.HWDATA(HWDATA), 
		.AB(AB), 
		.U_REQ(U_REQ), 
		.U_LOCK(U_LOCK), 
		.U_WRITE(U_WRITE), 
		.U_ADDR(U_ADDR), 
		.U_WDATA(U_WDATA), 
		.U_SLAVE(U_SLAVE)
	);
	
	always #10 CLK=~CLK;
	
	initial begin
	#593 RST = 1;
	#40 RST = 0;
	end

	initial begin

		CLK = 0;
		RST = 0;
		HGRANT = 0;
		HREADY = 1'bz;
		HRESP = 0;
		HRDATA = 32'bx;
		U_REQ = 0;
		U_LOCK = 0;
		U_WRITE = 0;
		U_ADDR = 16'bx;
		U_WDATA = 32'bx;
		U_SLAVE = 0;


		#100;
        

		
		#100 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_WDATA = 32'bx; U_SLAVE = 2'b00;
				HGRANT = 0; HRESP = 2'b00; HREADY = 1'bz;
		

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12'd3; U_WDATA = $random; U_SLAVE = 2'b01;
				#40 HGRANT = 1; HRESP = 2'b00; #20 HREADY = 1;
				
		#40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_SLAVE = 2'b01;
				 HGRANT = 0; HRESP = 2'b00; #40 HREADY = 1'bz;
				 

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 1; U_ADDR = 12'd3; U_WDATA = $random; U_SLAVE = 2'b01;
				#100 HGRANT = 1; HRESP = 2'b00; #20 HREADY = 1;
				
		#40 U_REQ = 0; #60 U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'b0; U_SLAVE = 2'b01;
				 HGRANT = 0; HRESP = 2'b00; #40 HREADY = 1'bz;
		

		#100 U_REQ = 1; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; #40 HGRANT = 1; #20 HREADY = 1;
				
		#40 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; HRDATA = U_WDATA;
				
		#10 U_REQ = 0; U_LOCK = 0; U_WRITE = 0; U_ADDR = 12'd3; U_SLAVE = 2'b01;
				HRESP = 2'b00; HREADY = 1; 
				
		#70 HGRANT = 0; #20 HRDATA = 32'bx; HREADY = 1'bz;


		

	end
      
endmodule