data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/common/rtl/compressor_32.v
data/verilator_xmls/a051cdc9-92be-4843-81d0-41dd85fef607.xml
module compressor_32(a,b,c,s,ca);
parameter B_SIZE = 8;
input  [B_SIZE-1:0] a;
input  [B_SIZE-1:0] b;
input  [B_SIZE-1:0] c;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;

wire [B_SIZE-1:0] s;
wire [B_SIZE-1:0]ca;

assign s[B_SIZE-1:0]  = a[B_SIZE-1:0]^b[B_SIZE-1:0]^c[B_SIZE-1:0];
assign ca[B_SIZE-1:0] = (a[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (c[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (a[B_SIZE-1:0]&c[B_SIZE-1:0]);











endmodule
module compressor_32(a,b,c,s,ca);

parameter B_SIZE = 8;
input  [B_SIZE-1:0] a;
input  [B_SIZE-1:0] b;
input  [B_SIZE-1:0] c;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;

wire [B_SIZE-1:0] s;
wire [B_SIZE-1:0]ca;

assign s[B_SIZE-1:0]  = a[B_SIZE-1:0]^b[B_SIZE-1:0]^c[B_SIZE-1:0];
assign ca[B_SIZE-1:0] = (a[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (c[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (a[B_SIZE-1:0]&c[B_SIZE-1:0]);











endmodule