data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v
1: b'%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:4: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.v\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.sv\n             parse_init.vh\n             parse_init.vh.v\n             parse_init.vh.sv\n             obj_dir/parse_init.vh\n             obj_dir/parse_init.vh.v\n             obj_dir/parse_init.vh.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:182: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:365: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module OXIDE_DSP_REG #(
	parameter W = 18,
	parameter USED = "REGISTER",
	parameter RESETMODE = "SYNC"
) (
	input CLK, CE, RST,
	input [W-1:0] D,
	output reg [W-1:0] Q
);
	generate
		if (USED == "BYPASS")
			always @* Q = D;
		else if (USED == "REGISTER") begin
			initial Q = 0;
			if (RESETMODE == "ASYNC")
				always @(posedge CLK, posedge RST) begin
					if (RST)
						Q <= 0;
					else if (CE)
						Q <= D;
				end
			else if (RESETMODE == "SYNC")
				always @(posedge CLK) begin
					if (RST)
						Q <= 0;
					else if (CE)
						Q <= D;
				end
		end
	endgenerate
endmodule
module OXIDE_DSP_REG #(
	parameter W = 18,
	parameter USED = "REGISTER",
	parameter RESETMODE = "SYNC"
) (
	input CLK, CE, RST,
	input [W-1:0] D,
	output reg [W-1:0] Q
);

	generate
		if (USED == "BYPASS")
			always @* Q = D;
		else if (USED == "REGISTER") begin
			initial Q = 0;
			if (RESETMODE == "ASYNC")
				always @(posedge CLK, posedge RST) begin
					if (RST)
						Q <= 0;
					else if (CE)
						Q <= D;
				end
			else if (RESETMODE == "SYNC")
				always @(posedge CLK) begin
					if (RST)
						Q <= 0;
					else if (CE)
						Q <= D;
				end
		end
	endgenerate
endmodule