data/full_repos/permissive/470158975/rtl/outbond_header_crc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:101: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n         checksum_int <= checksum_int + header[15:0] + header[31:16];\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:101: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n         checksum_int <= checksum_int + header[15:0] + header[31:16];\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:105: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n   assign checksum = ~(summ[15:0] + summ[16]);\n                                  ^\n%Error: Exiting due to 3 warning(s)\n'
module checksum_acc(
   input          clk,
   output[15:0]   checksum,
   input [31:0]   header,
   output         valid,
   input          reset
);

   reg [31:0] checksum_int;
   reg [2:0] header_count;
   
   always @(posedge clk)
   if (reset) begin
      checksum_int <= 0;
      header_count <= 0;
   end
   else
      if (header_count != 5)
      begin
         header_count <= header_count + 1'b1;
         checksum_int <= checksum_int + header[15:0] + header[31:16];
      end

   wire [16:0]  summ = checksum_int[31:16] + checksum_int[15:0];
   assign checksum = ~(summ[15:0] + summ[16]);
   
   assign valid = (header_count==5);
endmodule
module checksum_acc(
   input          clk,
   output[15:0]   checksum,
   input [31:0]   header,
   output         valid,
   input          reset
);


   reg [31:0] checksum_int;
   reg [2:0] header_count;
   
   always @(posedge clk)
   if (reset) begin
      checksum_int <= 0;
      header_count <= 0;
   end
   else
      if (header_count != 5)
      begin
         header_count <= header_count + 1'b1;
         checksum_int <= checksum_int + header[15:0] + header[31:16];
      end

   wire [16:0]  summ = checksum_int[31:16] + checksum_int[15:0];
   assign checksum = ~(summ[15:0] + summ[16]);
   
   assign valid = (header_count==5);
endmodule