data/full_repos/permissive/514437299/digital/rtl/clkg.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514437299/digital/rtl/clkg.v:151: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'mux8\'\nmodule mux8(input  wire [2:0] i_sel,\n       ^~~~\n                                                                              : ... Top module \'clkg\'\nmodule clkg #(parameter NINVERTER = 66) (\n       ^~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:65: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:217: Cannot find file containing module: \'INVLONG_OSC37\'\n  INVLONG_OSC37 U_CLK_OSC(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:223: Cannot find file containing module: \'INVD2\'\n  INVD2 U_CLK_OSC_DRV(\n  ^~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:227: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_OSC(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:233: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_FCK(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:364: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_MEM(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:370: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_RNG(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:376: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_SMP(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:382: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_CMO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:397: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_DLO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:407: Cannot find file containing module: \'CKLHQD1\'\n  CKLHQD1 U_CLK_GATE_PCH(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:413: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_PLN(\n  ^~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module clkdiv(input  wire       clk,
              input  wire       rst_n,
              input  wire       i_en,
              input  wire [2:0] i_div,
              output reg        o_clk_div,
              output wire [7:0] o_clk_all);
  wire clk_pre;

  wire clk_div2;
  wire clk_div4;
  wire clk_div8;
  wire clk_div16;
  wire clk_div32;
  wire clk_div64;
  wire clk_div128;
  wire clk_div256;

  CKLNQD1 U_CLK_GATE(
    .TE ( 1'b0    ) ,
    .E  ( i_en    ) ,
    .CP ( clk     ) ,
    .Q  ( clk_pre ) );

  clkdiv256 U_CLK_DIV(
    .clk          ( clk_pre    ) ,
    .rst_n        ( rst_n      ) ,
    .o_clk_div2   ( clk_div2   ) ,
    .o_clk_div4   ( clk_div4   ) ,
    .o_clk_div8   ( clk_div8   ) ,
    .o_clk_div16  ( clk_div16  ) ,
    .o_clk_div32  ( clk_div32  ) ,
    .o_clk_div64  ( clk_div64  ) ,
    .o_clk_div128 ( clk_div128 ) ,
    .o_clk_div256 ( clk_div256 ) );

  always @*
    case (i_div)
      3'd0: o_clk_div = clk_div2;
      3'd1: o_clk_div = clk_div4;
      3'd2: o_clk_div = clk_div8;
      3'd3: o_clk_div = clk_div16;
      3'd4: o_clk_div = clk_div32;
      3'd5: o_clk_div = clk_div64;
      3'd6: o_clk_div = clk_div128;
      3'd7: o_clk_div = clk_div256;
      default: o_clk_div = clk_div2;
    endcase

  assign o_clk_all = { clk_div256,
                       clk_div128,
                       clk_div64,
                       clk_div32,
                       clk_div16,
                       clk_div8,
                       clk_div4,
                       clk_div2 };

endmodule
module clkdiv(input  wire       clk,
              input  wire       rst_n,
              input  wire       i_en,
              input  wire [2:0] i_div,
              output reg        o_clk_div,
              output wire [7:0] o_clk_all);

  wire clk_pre;

  wire clk_div2;
  wire clk_div4;
  wire clk_div8;
  wire clk_div16;
  wire clk_div32;
  wire clk_div64;
  wire clk_div128;
  wire clk_div256;

  CKLNQD1 U_CLK_GATE(
    .TE ( 1'b0    ) ,
    .E  ( i_en    ) ,
    .CP ( clk     ) ,
    .Q  ( clk_pre ) );

  clkdiv256 U_CLK_DIV(
    .clk          ( clk_pre    ) ,
    .rst_n        ( rst_n      ) ,
    .o_clk_div2   ( clk_div2   ) ,
    .o_clk_div4   ( clk_div4   ) ,
    .o_clk_div8   ( clk_div8   ) ,
    .o_clk_div16  ( clk_div16  ) ,
    .o_clk_div32  ( clk_div32  ) ,
    .o_clk_div64  ( clk_div64  ) ,
    .o_clk_div128 ( clk_div128 ) ,
    .o_clk_div256 ( clk_div256 ) );

  always @*
    case (i_div)
      3'd0: o_clk_div = clk_div2;
      3'd1: o_clk_div = clk_div4;
      3'd2: o_clk_div = clk_div8;
      3'd3: o_clk_div = clk_div16;
      3'd4: o_clk_div = clk_div32;
      3'd5: o_clk_div = clk_div64;
      3'd6: o_clk_div = clk_div128;
      3'd7: o_clk_div = clk_div256;
      default: o_clk_div = clk_div2;
    endcase

  assign o_clk_all = { clk_div256,
                       clk_div128,
                       clk_div64,
                       clk_div32,
                       clk_div16,
                       clk_div8,
                       clk_div4,
                       clk_div2 };

endmodule