data/full_repos/permissive/42581625/PersonalComputer/Timer.v
data/verilator_xmls/70c2c11e-3050-47dc-bbfc-512e27140272.xml
module Timer(
input clk,
output TimerInte
    );
reg[31:0] count = 1;
assign TimerInte = (count == 0);

always@(posedge clk) begin
	if(count == 32'd50000000) begin
		count <= 0;
	end
	else begin
		count <= count+1;
	end
end


endmodule
module Timer(
input clk,
output TimerInte
    );

reg[31:0] count = 1;
assign TimerInte = (count == 0);

always@(posedge clk) begin
	if(count == 32'd50000000) begin
		count <= 0;
	end
	else begin
		count <= count+1;
	end
end


endmodule