data/full_repos/permissive/430337995/tpu_tb/src/pe.v
1: b'%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/tpu_tb/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/tpu_tb/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/tpu_tb/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:16: Define or directive not defined: \'`BYTES_SIZE\'\ninput      [`BYTES_SIZE-1:0]   left_in;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:17: Define or directive not defined: \'`BYTES_SIZE\'\ninput      [`BYTES_SIZE-1:0]   up_in;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:18: Define or directive not defined: \'`BYTES_SIZE\'\noutput reg [`BYTES_SIZE-1:0]    right_out;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:19: Define or directive not defined: \'`BYTES_SIZE\'\noutput reg [`BYTES_SIZE-1:0]    down_out;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:20: Define or directive not defined: \'`BYTES_SIZE\'\noutput reg [`BYTES_SIZE-1:0]    sum;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:53: Define or directive not defined: \'`BYTES_SIZE\'\ninput  [`BYTES_SIZE-1:0]    left_in;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/tpu_tb/src/pe.v:58: Define or directive not defined: \'`BYTES_SIZE\'\nwire   [`BYTES_SIZE-1:0]     right_out [0:15];\n        ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module PE(
    clk,
    rst,
    zero,
    left_in,
    up_in,
    right_out,
    down_out,
    sum
);

input                          clk;
input                          rst;
input                          zero;
input      [`BYTES_SIZE-1:0]   left_in;
input      [`BYTES_SIZE-1:0]   up_in;
output reg [`BYTES_SIZE-1:0]    right_out;
output reg [`BYTES_SIZE-1:0]    down_out;
output reg [`BYTES_SIZE-1:0]    sum;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        sum <= 8'd0;
        right_out <= 8'd0;
        down_out <= 8'd0;
    end else begin
        if(zero) begin
            sum <= 8'd0;
        end else begin
            sum <= sum + left_in * up_in;
        end
        right_out <= left_in;
        down_out <= up_in;
    end
end

endmodule
module PE(
    clk,
    rst,
    zero,
    left_in,
    up_in,
    right_out,
    down_out,
    sum
);


input                          clk;
input                          rst;
input                          zero;
input      [`BYTES_SIZE-1:0]   left_in;
input      [`BYTES_SIZE-1:0]   up_in;
output reg [`BYTES_SIZE-1:0]    right_out;
output reg [`BYTES_SIZE-1:0]    down_out;
output reg [`BYTES_SIZE-1:0]    sum;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        sum <= 8'd0;
        right_out <= 8'd0;
        down_out <= 8'd0;
    end else begin
        if(zero) begin
            sum <= 8'd0;
        end else begin
            sum <= sum + left_in * up_in;
        end
        right_out <= left_in;
        down_out <= up_in;
    end
end

endmodule