data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_clk_div.v
data/verilator_xmls/385e9d30-dd34-4a21-a4f1-1f6543f1843f.xml
module clk_div (clk_in, enable,reset, clk_out);

 input               clk_in                   ;
 input               reset                    ;
 input               enable                   ;
 output              clk_out                  ;

 wire                 clk_in                  ;
 wire                 enable                  ;

reg                   clk_out                 ;

always @ (posedge clk_in) 
if (reset) begin 
  clk_out <= 1'b0;
end else if (enable) begin
  clk_out <= !clk_out ; 
end

endmodule
module clk_div (clk_in, enable,reset, clk_out);


 input               clk_in                   ;
 input               reset                    ;
 input               enable                   ;
 output              clk_out                  ;

 wire                 clk_in                  ;
 wire                 enable                  ;

reg                   clk_out                 ;

always @ (posedge clk_in) 
if (reset) begin 
  clk_out <= 1'b0;
end else if (enable) begin
  clk_out <= !clk_out ; 
end

endmodule