data/full_repos/permissive/440792992/hardware/decode_backup.v
1: b'%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:8: Cannot find include file: configure.h\n`include "configure.h" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.v\n             data/full_repos/permissive/440792992/hardware,data/full_repos/permissive/440792992/configure.h.sv\n             configure.h\n             configure.h.v\n             configure.h.sv\n             obj_dir/configure.h\n             obj_dir/configure.h.v\n             obj_dir/configure.h.sv\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:55: Define or directive not defined: \'`I_type\'\n        inst_type     = `I_type;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        inst_type     = `I_type;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:56: Define or directive not defined: \'`SRC1_RS1\'\n        src1_sel    = `SRC1_RS1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        src1_sel    = `SRC1_RS1;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:57: Define or directive not defined: \'`SRC2_IMM\'\n        src2_sel    = `SRC2_IMM;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        src2_sel    = `SRC2_IMM;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:64: Define or directive not defined: \'`RS_ALU\'\n        rs_type       = `RS_ALU;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rs_type       = `RS_ALU;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:65: Define or directive not defined: \'`ALU_ADD\'\n        alu_op       = `ALU_ADD;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        alu_op       = `ALU_ADD;\n                               ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:68: Define or directive not defined: \'`RV32_LOAD\'\n         `RV32_LOAD : begin\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:68: syntax error, unexpected \':\', expecting endcase\n         `RV32_LOAD : begin\n                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:71: Define or directive not defined: \'`RS_LDST\'\n             rs_type        = `RS_LDST;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n             rs_type        = `RS_LDST;\n                                      ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:74: Define or directive not defined: \'`STORE\'\n            `STORE : begin\n            ^~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:74: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `STORE : begin\n                     ^~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:76: Define or directive not defined: \'`S_type\'\n                inst_type      = `S_type;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                inst_type      = `S_type;\n                                        ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:79: Define or directive not defined: \'`RS_LDST\'\n             rs_type        = `RS_LDST;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n             rs_type        = `RS_LDST;\n                                      ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:81: Define or directive not defined: \'`BRANCH\'\n            `BRANCH : begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:81: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BRANCH : begin\n                      ^~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:84: Define or directive not defined: \'`SRC2_RS2\'\n                src2_sel = `SRC2_RS2;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src2_sel = `SRC2_RS2;\n                                    ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:86: Define or directive not defined: \'`FUNCT3_BEQ\'\n                    `FUNCT3_BEQ  : alu_op = `ALU_SEQ;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:86: syntax error, unexpected \':\', expecting endcase\n                    `FUNCT3_BEQ  : alu_op = `ALU_SEQ;\n                                 ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:86: Define or directive not defined: \'`ALU_SEQ\'\n                    `FUNCT3_BEQ  : alu_op = `ALU_SEQ;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:87: Define or directive not defined: \'`FUNCT3_BNE\'\n                    `FUNCT3_BNE  : alu_op = `ALU_SNE;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:87: Define or directive not defined: \'`ALU_SNE\'\n                    `FUNCT3_BNE  : alu_op = `ALU_SNE;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:88: Define or directive not defined: \'`FUNCT3_BLT\'\n                    `FUNCT3_BLT  : alu_op = `ALU_SLT;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:88: Define or directive not defined: \'`ALU_SLT\'\n                    `FUNCT3_BLT  : alu_op = `ALU_SLT;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:89: Define or directive not defined: \'`FUNCT3_BLTU\'\n                    `FUNCT3_BLTU : alu_op = `ALU_SLTU;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:89: Define or directive not defined: \'`ALU_SLTU\'\n                    `FUNCT3_BLTU : alu_op = `ALU_SLTU;\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:90: Define or directive not defined: \'`FUNCT3_BGE\'\n                    `FUNCT3_BGE  : alu_op = `ALU_SGE;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:90: Define or directive not defined: \'`ALU_SGE\'\n                    `FUNCT3_BGE  : alu_op = `ALU_SGE;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:91: Define or directive not defined: \'`FUNCT3_BGEU\'\n                    `FUNCT3_BGEU : alu_op = `ALU_SGEU;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:91: Define or directive not defined: \'`ALU_SGEU\'\n                    `FUNCT3_BGEU : alu_op = `ALU_SGEU;\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:94: Define or directive not defined: \'`RS_BRANCH\'\n             rs_type = `RS_BRANCH;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:96: Define or directive not defined: \'`JAL\'\n            `JAL : begin\n            ^~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:96: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `JAL : begin\n                   ^~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:99: Define or directive not defined: \'`SRC1_PC\'\n                src1_sel     = `SRC1_PC;\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src1_sel     = `SRC1_PC;\n                                       ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:100: Define or directive not defined: \'`SRC2_FOUR\'\n                src2_sel     = `SRC2_FOUR;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                src2_sel     = `SRC2_FOUR;\n                                         ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:102: Define or directive not defined: \'`RS_JAL\'\n             rs_type        = `RS_JAL;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n             rs_type        = `RS_JAL;\n                                     ^\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:104: Define or directive not defined: \'`JALR\'\n            `JALR : begin\n            ^~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:104: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `JALR : begin\n                    ^~~~~\n%Error: data/full_repos/permissive/440792992/hardware/decode_backup.v:107: Define or directive not defined: \'`SRC1_PC\'\n                src1_sel     = `SRC1_PC;\n                               ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Decoder
(
    input      [31:0]             inst,
    output reg [1:0]   inst_type,
    output     [4:0]          rs1,
    output     [4:0]          rs2,
    output     [4:0]          rd,
    output reg [1:0]  src1_sel,
    output reg [1:0]  src2_sel,
    output reg                         rd_valid,
	       
    output reg                         rs1_valid,
    output reg                         rs2_valid,
    output reg                         ill_inst,
    output reg [3:0]     alu_op,
    output reg [2:0]       rs_type,


    output     [2:0] 	               dmem_size,
    output     [2:0]   dmem_type, 
    output reg [1:0]      muldiv_op,
    output reg                         muldiv_rs1_signed,
    output reg                         muldiv_rs2_signed,
    output reg [1:0] muldiv_out_sel
);

    wire [3:0]           srl_or_sra;
    wire [3:0]           add_or_sub;
    wire [2:0]             rs_type_md;
   
    wire [6:0] 		    opcode  = inst[6:0];
    wire [6:0] 		    funct7  = inst[31:25];
    wire [11:0]         funct12 = inst[31:20];
    wire [2:0] 		    funct3  = inst[14:12];

    reg [3:0]  alu_op_arith;
   
    assign rd  = inst[11:7];
    assign rs1 = inst[19:15];
    assign rs2 = inst[24:20];
 
    assign dmem_size = {1'b0,funct3[1:0]};
    assign dmem_type = funct3;
   
    always @(*) begin
        inst_type     = `I_type;
        src1_sel    = `SRC1_RS1;
        src2_sel    = `SRC2_IMM;
        rd_valid       = 1'b0;
        rs1_valid     = 1'b1;
        rs2_valid     = 1'b0;
        ill_inst = 1'b0;


        rs_type       = `RS_ALU;
        alu_op       = `ALU_ADD;
      
        case (opcode)
	        `RV32_LOAD : begin

                rd_valid        = 1'b1;
	            rs_type        = `RS_LDST;

            end
            `STORE : begin
                rs2_valid      = 1'b1;
                inst_type      = `S_type;


	            rs_type        = `RS_LDST;
            end
            `BRANCH : begin
                rs2_valid = 1'b1;

                src2_sel = `SRC2_RS2;
                case (funct3)
                    `FUNCT3_BEQ  : alu_op = `ALU_SEQ;
                    `FUNCT3_BNE  : alu_op = `ALU_SNE;
                    `FUNCT3_BLT  : alu_op = `ALU_SLT;
                    `FUNCT3_BLTU : alu_op = `ALU_SLTU;
                    `FUNCT3_BGE  : alu_op = `ALU_SGE;
                    `FUNCT3_BGEU : alu_op = `ALU_SGEU;
                    default :     ill_inst = 1'b1;
                endcase
	            rs_type = `RS_BRANCH;
            end
            `JAL : begin

                rs1_valid      = 1'b0;
                src1_sel     = `SRC1_PC;
                src2_sel     = `SRC2_FOUR;
                rd_valid        = 1'b1;
	            rs_type        = `RS_JAL;
            end
            `JALR : begin
                ill_inst  = (funct3 != 0);

                src1_sel     = `SRC1_PC;
                src2_sel     = `SRC2_FOUR;
                rd_valid        = 1'b1;
	            rs_type        = `RS_JALR;
            end

            `RV32_OP_IMM : begin
                alu_op    = alu_op_arith;
                rd_valid    = 1'b1;
            end
            `RV32_OP  : begin
                rs2_valid  = 1'b1;
                src2_sel = `SRC2_RS2;
                alu_op    = alu_op_arith;
                rd_valid    = 1'b1;
                if (funct7 == `RV32_FUNCT7_MUL_DIV) begin

	                rs_type = rs_type_md;

                end
            end

            `AUIPC : begin
                rs1_valid  = 1'b0;
                src1_sel = `SRC1_PC;
                inst_type  = `U_type;
                rd_valid    = 1'b1;
            end
            `LUI : begin
                rs1_valid  = 1'b0;
                src1_sel = `SRC1_ZERO;
                inst_type  = `U_type;
                rd_valid    = 1'b1;
            end
            default : begin
                ill_inst = 1'b1;
            end
        endcase
    end

    assign add_or_sub = ((opcode == `RV32_OP) && (funct7[5])) ? `ALU_SUB : `ALU_ADD;
    assign srl_or_sra = (funct7[5]) ? `ALU_SRA : `ALU_SRL;

    always @(*) begin
        case (funct3)
            `RV32_FUNCT3_ADD_SUB : alu_op_arith = add_or_sub;
            `RV32_FUNCT3_SLL     : alu_op_arith = `ALU_SLL;
            `RV32_FUNCT3_SLT     : alu_op_arith = `ALU_SLT;
            `RV32_FUNCT3_SLTU    : alu_op_arith = `ALU_SLTU;
            `RV32_FUNCT3_XOR     : alu_op_arith = `ALU_XOR;
            `RV32_FUNCT3_SRA_SRL : alu_op_arith = srl_or_sra;
            `RV32_FUNCT3_OR      : alu_op_arith = `ALU_OR;
            `RV32_FUNCT3_AND     : alu_op_arith = `ALU_AND;
            default              : alu_op_arith = `ALU_ADD;
        endcase
    end



    assign rs_type_md = ( (funct3 == `RV32_FUNCT3_MUL)    ||
		                 (funct3 == `RV32_FUNCT3_MULH)   ||
		                 (funct3 == `RV32_FUNCT3_MULHSU) ||
		                 (funct3 == `RV32_FUNCT3_MULHU)
		               ) ? `RS_MUL : `RS_DIV;
   
    always @(*) begin
        muldiv_op = `MUL;
        muldiv_rs1_signed = 0;
        muldiv_rs2_signed = 0;
        muldiv_out_sel = `OUT_LOW;
        case (funct3)
            `RV32_FUNCT3_MUL : begin
            end
            `RV32_FUNCT3_MULH : begin
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_MULHSU : begin
                muldiv_rs1_signed = 1;
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_MULHU : begin
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_DIV : begin
                muldiv_op = `DIV;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
            end
            `RV32_FUNCT3_DIVU : begin
                muldiv_op = `DIV;
            end
            `RV32_FUNCT3_REM : begin
                muldiv_op = `REM;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel = `OUT_REM;
            end
            `RV32_FUNCT3_REMU : begin
                muldiv_op = `REM;
                muldiv_out_sel = `OUT_REM;
            end
        endcase
    end

   
endmodule
module Decoder
(
    input      [31:0]             inst,
    output reg [1:0]   inst_type,
    output     [4:0]          rs1,
    output     [4:0]          rs2,
    output     [4:0]          rd,
    output reg [1:0]  src1_sel,
    output reg [1:0]  src2_sel,
    output reg                         rd_valid,
	       
    output reg                         rs1_valid,
    output reg                         rs2_valid,
    output reg                         ill_inst,
    output reg [3:0]     alu_op,
    output reg [2:0]       rs_type,


    output     [2:0] 	               dmem_size,
    output     [2:0]   dmem_type, 
    output reg [1:0]      muldiv_op,
    output reg                         muldiv_rs1_signed,
    output reg                         muldiv_rs2_signed,
    output reg [1:0] muldiv_out_sel
);


    wire [3:0]           srl_or_sra;
    wire [3:0]           add_or_sub;
    wire [2:0]             rs_type_md;
   
    wire [6:0] 		    opcode  = inst[6:0];
    wire [6:0] 		    funct7  = inst[31:25];
    wire [11:0]         funct12 = inst[31:20];
    wire [2:0] 		    funct3  = inst[14:12];

    reg [3:0]  alu_op_arith;
   
    assign rd  = inst[11:7];
    assign rs1 = inst[19:15];
    assign rs2 = inst[24:20];
 
    assign dmem_size = {1'b0,funct3[1:0]};
    assign dmem_type = funct3;
   
    always @(*) begin
        inst_type     = `I_type;
        src1_sel    = `SRC1_RS1;
        src2_sel    = `SRC2_IMM;
        rd_valid       = 1'b0;
        rs1_valid     = 1'b1;
        rs2_valid     = 1'b0;
        ill_inst = 1'b0;


        rs_type       = `RS_ALU;
        alu_op       = `ALU_ADD;
      
        case (opcode)
	        `RV32_LOAD : begin

                rd_valid        = 1'b1;
	            rs_type        = `RS_LDST;

            end
            `STORE : begin
                rs2_valid      = 1'b1;
                inst_type      = `S_type;


	            rs_type        = `RS_LDST;
            end
            `BRANCH : begin
                rs2_valid = 1'b1;

                src2_sel = `SRC2_RS2;
                case (funct3)
                    `FUNCT3_BEQ  : alu_op = `ALU_SEQ;
                    `FUNCT3_BNE  : alu_op = `ALU_SNE;
                    `FUNCT3_BLT  : alu_op = `ALU_SLT;
                    `FUNCT3_BLTU : alu_op = `ALU_SLTU;
                    `FUNCT3_BGE  : alu_op = `ALU_SGE;
                    `FUNCT3_BGEU : alu_op = `ALU_SGEU;
                    default :     ill_inst = 1'b1;
                endcase
	            rs_type = `RS_BRANCH;
            end
            `JAL : begin

                rs1_valid      = 1'b0;
                src1_sel     = `SRC1_PC;
                src2_sel     = `SRC2_FOUR;
                rd_valid        = 1'b1;
	            rs_type        = `RS_JAL;
            end
            `JALR : begin
                ill_inst  = (funct3 != 0);

                src1_sel     = `SRC1_PC;
                src2_sel     = `SRC2_FOUR;
                rd_valid        = 1'b1;
	            rs_type        = `RS_JALR;
            end

            `RV32_OP_IMM : begin
                alu_op    = alu_op_arith;
                rd_valid    = 1'b1;
            end
            `RV32_OP  : begin
                rs2_valid  = 1'b1;
                src2_sel = `SRC2_RS2;
                alu_op    = alu_op_arith;
                rd_valid    = 1'b1;
                if (funct7 == `RV32_FUNCT7_MUL_DIV) begin

	                rs_type = rs_type_md;

                end
            end

            `AUIPC : begin
                rs1_valid  = 1'b0;
                src1_sel = `SRC1_PC;
                inst_type  = `U_type;
                rd_valid    = 1'b1;
            end
            `LUI : begin
                rs1_valid  = 1'b0;
                src1_sel = `SRC1_ZERO;
                inst_type  = `U_type;
                rd_valid    = 1'b1;
            end
            default : begin
                ill_inst = 1'b1;
            end
        endcase
    end

    assign add_or_sub = ((opcode == `RV32_OP) && (funct7[5])) ? `ALU_SUB : `ALU_ADD;
    assign srl_or_sra = (funct7[5]) ? `ALU_SRA : `ALU_SRL;

    always @(*) begin
        case (funct3)
            `RV32_FUNCT3_ADD_SUB : alu_op_arith = add_or_sub;
            `RV32_FUNCT3_SLL     : alu_op_arith = `ALU_SLL;
            `RV32_FUNCT3_SLT     : alu_op_arith = `ALU_SLT;
            `RV32_FUNCT3_SLTU    : alu_op_arith = `ALU_SLTU;
            `RV32_FUNCT3_XOR     : alu_op_arith = `ALU_XOR;
            `RV32_FUNCT3_SRA_SRL : alu_op_arith = srl_or_sra;
            `RV32_FUNCT3_OR      : alu_op_arith = `ALU_OR;
            `RV32_FUNCT3_AND     : alu_op_arith = `ALU_AND;
            default              : alu_op_arith = `ALU_ADD;
        endcase
    end



    assign rs_type_md = ( (funct3 == `RV32_FUNCT3_MUL)    ||
		                 (funct3 == `RV32_FUNCT3_MULH)   ||
		                 (funct3 == `RV32_FUNCT3_MULHSU) ||
		                 (funct3 == `RV32_FUNCT3_MULHU)
		               ) ? `RS_MUL : `RS_DIV;
   
    always @(*) begin
        muldiv_op = `MUL;
        muldiv_rs1_signed = 0;
        muldiv_rs2_signed = 0;
        muldiv_out_sel = `OUT_LOW;
        case (funct3)
            `RV32_FUNCT3_MUL : begin
            end
            `RV32_FUNCT3_MULH : begin
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_MULHSU : begin
                muldiv_rs1_signed = 1;
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_MULHU : begin
                muldiv_out_sel = `OUT_HIGH;
            end
            `RV32_FUNCT3_DIV : begin
                muldiv_op = `DIV;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
            end
            `RV32_FUNCT3_DIVU : begin
                muldiv_op = `DIV;
            end
            `RV32_FUNCT3_REM : begin
                muldiv_op = `REM;
                muldiv_rs1_signed = 1;
                muldiv_rs2_signed = 1;
                muldiv_out_sel = `OUT_REM;
            end
            `RV32_FUNCT3_REMU : begin
                muldiv_op = `REM;
                muldiv_out_sel = `OUT_REM;
            end
        endcase
    end

   
endmodule