data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #0 clock = 0; in = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #50 in = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #40 in = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #50 in = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new/singlepulser_tester.v:28: Cannot find file containing module: \'SinglePulser\'\n    SinglePulser c(out,in,clock);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new,data/full_repos/permissive/423958267/SinglePulser\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new,data/full_repos/permissive/423958267/SinglePulser.v\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_2/new,data/full_repos/permissive/423958267/SinglePulser.sv\n             SinglePulser\n             SinglePulser.v\n             SinglePulser.sv\n             obj_dir/SinglePulser\n             obj_dir/SinglePulser.v\n             obj_dir/SinglePulser.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module singlepulser_tester(

);
    wire out;
    reg in, clock;
    SinglePulser c(out,in,clock);

    always #10 clock = ~clock;

    initial
    begin
        #0 clock = 0; in = 1;
        #50 in = 0;
        #40 in = 1;
        #50 in = 0;
        #100 $finish;
    end
endmodule
module singlepulser_tester(

);

    wire out;
    reg in, clock;
    SinglePulser c(out,in,clock);

    always #10 clock = ~clock;

    initial
    begin
        #0 clock = 0; in = 1;
        #50 in = 0;
        #40 in = 1;
        #50 in = 0;
        #100 $finish;
    end
endmodule