data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module control_unit (
  input            clk
, input            clr
, input            carry
, input            zero
, input      [7:0] instruction
, input      [7:0] regR0

, output reg [2:0] pstate
, output wire      ld_r0
, output wire      ld_r1
, output wire      ld_r2
, output wire      ld_r3
, output reg       ld_pc
, output reg       inc_pc
, output reg       ld_ir
, output reg       ld_address_reg
, output reg       ld_reg_y
, output reg       ld_reg_z
, output reg       write
, output reg       read
, output reg       sig_halt
, output reg [2:0] sel_dbus_mux
, output reg [1:0] sel_bus2_mux
);

parameter opcode_size = 4;
parameter src_size    = 2;
parameter dest_size   = 2;


parameter STATE_IDLE     = 3'b000;
parameter STATE_FETCH1   = 3'b001;
parameter STATE_FETCH2   = 3'b010;
parameter STATE_DECODE   = 3'b011;
parameter STATE_EXECUTE  = 3'b100;
parameter STATE_STATE1   = 3'b101;
parameter STATE_STATE2   = 3'b110;
parameter STATE_HALT     = 3'b111;

parameter     REG_R0     = 2'b00;
parameter     REG_R1     = 2'b01;
parameter     REG_R2     = 2'b10;
parameter     REG_R3     = 2'b11;
parameter SEL_BUS_ALU    = 2'b00;
parameter SEL_BUS_DB     = 2'b01;
parameter SEL_BUS_MEM    = 2'b10;
parameter SEL_BUS_R0     = 3'b000;
parameter SEL_BUS_R1     = 3'b001;
parameter SEL_BUS_R2     = 3'b010;
parameter SEL_BUS_R3     = 3'b011;
parameter SEL_BUS_PC     = 3'b100;



reg       ld_reg = 0;
reg [2:0] nstate = 0;

assign ld_r0 = (dest == 2'b00) ? ld_reg : 1'b0;
assign ld_r1 = (dest == 2'b01) ? ld_reg : 1'b0;
assign ld_r2 = (dest == 2'b10) ? ld_reg : 1'b0;
assign ld_r3 = (dest == 2'b11) ? ld_reg : 1'b0;

wire [3:0] opcode = instruction [7:4];
wire [3:0] cond   = instruction [3:0]; 
wire [1:0] src    = instruction [3:2];
wire [1:0] dest   = instruction [1:0];

always @ (posedge clk or negedge clr)
  begin
    if(!clr)
        pstate <= STATE_IDLE;
    else
        pstate <= nstate;
  end

always @*
  begin
    ld_reg = 0;
    ld_pc = 0;
    ld_ir = 0;
    ld_address_reg = 0;
    ld_reg_y = 0;
    ld_reg_z = 0;
    inc_pc = 0;

    read  = 0;
    write = 0;

    case(pstate)
        STATE_IDLE   : begin 
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 0;
            write          = 0;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_DB; 
            sig_halt       = 0;
            nstate         = STATE_FETCH1; 
        end
        
        STATE_FETCH1 : begin
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 0;
            write          = 0;
            ld_address_reg = 1;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_DB; 
            nstate         = STATE_FETCH2;
        end
        
        STATE_FETCH2 : begin
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 1;
            write          = 0;
            ld_ir          = 1;
            inc_pc         = 1;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_MEM;
            nstate         = STATE_DECODE;
        end
        
        STATE_DECODE : case (opcode)
                    `OPNOP     : begin
                      sig_halt       = 0;
                      ld_reg         = 0;
                      nstate         = STATE_FETCH1;
                    end
                    `OPADD, `OPADC, `OPSUB, `OPAND, `OPEOR, `OPIOR : begin
                                sig_halt     = 0;
                                ld_reg       = 0;
                                ld_reg_y     = 1;
                                sel_dbus_mux = {1'b0, src};
                                sel_bus2_mux = SEL_BUS_DB; 
                                nstate       = STATE_EXECUTE;
                    end
                    `OPNOT     : begin
                                sig_halt       = 0;
                                ld_reg         = 1;
                                ld_reg_z       = 1;
                                sel_dbus_mux   = {1'b0, src};
                                sel_bus2_mux   = SEL_BUS_ALU; 
                                nstate         = STATE_FETCH1;
                    end
                    `OPRD      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPWR      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPLD      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPSTO     : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = {1'b0, dest};
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPBR      : begin
                                  case( cond )
                                    `BRA  : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end
                                    `BRN  : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 0;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRC  : if(carry == 1'b1) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRZ  : if(zero == 1'b1) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRNC : if(carry == 1'b0) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRNZ : if(zero == 1'b0) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRRJ : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             ld_pc          = 1;
                                             sel_dbus_mux   = SEL_BUS_R3;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_FETCH1;
                                           end
                                    default : begin
                                                sig_halt       = 0;
                                                ld_reg         = 0;
                                                ld_address_reg = 0;
                                                sel_dbus_mux   = SEL_BUS_PC;
                                                sel_bus2_mux   = SEL_BUS_DB;
                                                nstate         = STATE_FETCH1;
                                              end
                                  endcase
                                end
                    `OPBIT     : begin
                                  case( cond[2:0] )
                                    3'b000 : begin
                                               if(regR0[0] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b001 : begin
                                               if(regR0[1] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b010 : begin
                                               if(regR0[2] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b011 : begin
                                               if(regR0[3] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b100 : begin
                                               if(regR0[4] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b101 : begin
                                               if(regR0[5] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b110 : begin
                                               if(regR0[6] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b111 : begin
                                               if(regR0[7] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                  endcase
                                end
                    `OPBRC     : if(carry == 1) begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                              end else begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                inc_pc         = 1;
                                nstate         = STATE_FETCH1;
                    end
                    `OPHALT    : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                nstate         = STATE_HALT;
                    end
                    default : begin 
                                sig_halt       = 0;
                                ld_reg         = 0;
                                nstate = STATE_HALT;
                    end
                endcase

        STATE_EXECUTE : begin
            sig_halt     = 0;
            ld_reg       = 1;
            ld_reg_z     = 1;
            sel_dbus_mux = {1'b0, dest};
            sel_bus2_mux = SEL_BUS_ALU;
            nstate       = STATE_FETCH1;
        end
        
        STATE_STATE1 : begin
          case(opcode)
            `OPRD : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_address_reg = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_STATE2;
            end
            `OPWR : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_address_reg = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_STATE2;
            end
            `OPLD : begin
              sig_halt       = 0;
              ld_reg         = 1;
              read           = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_FETCH1;
            end
            `OPSTO : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 0;
              write          = 1;
              sel_dbus_mux   = {1'b0, src};
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
            `OPBR, `OPBRC, `OPBIT: begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_pc          = 1;
              sel_dbus_mux   = SEL_BUS_PC;
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
          endcase
        end
        
        STATE_STATE2 : begin
          case(opcode)
            `OPRD : begin
              sig_halt       = 0;
              ld_reg         = 1;
              read           = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_FETCH1;
            end
            `OPWR : begin
              sig_halt       = 0;
              ld_reg         = 0;
              write          = 1;
              sel_dbus_mux   = {1'b0, src};
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
          endcase
        end
        
        STATE_HALT: begin
            ld_reg           = 0;
            sig_halt         = 1;
            nstate           = STATE_HALT;
        end
        default: nstate      = STATE_IDLE;
    endcase
  end

endmodule
module control_unit (
  input            clk
, input            clr
, input            carry
, input            zero
, input      [7:0] instruction
, input      [7:0] regR0

, output reg [2:0] pstate
, output wire      ld_r0
, output wire      ld_r1
, output wire      ld_r2
, output wire      ld_r3
, output reg       ld_pc
, output reg       inc_pc
, output reg       ld_ir
, output reg       ld_address_reg
, output reg       ld_reg_y
, output reg       ld_reg_z
, output reg       write
, output reg       read
, output reg       sig_halt
, output reg [2:0] sel_dbus_mux
, output reg [1:0] sel_bus2_mux
);


parameter opcode_size = 4;
parameter src_size    = 2;
parameter dest_size   = 2;


parameter STATE_IDLE     = 3'b000;
parameter STATE_FETCH1   = 3'b001;
parameter STATE_FETCH2   = 3'b010;
parameter STATE_DECODE   = 3'b011;
parameter STATE_EXECUTE  = 3'b100;
parameter STATE_STATE1   = 3'b101;
parameter STATE_STATE2   = 3'b110;
parameter STATE_HALT     = 3'b111;

parameter     REG_R0     = 2'b00;
parameter     REG_R1     = 2'b01;
parameter     REG_R2     = 2'b10;
parameter     REG_R3     = 2'b11;
parameter SEL_BUS_ALU    = 2'b00;
parameter SEL_BUS_DB     = 2'b01;
parameter SEL_BUS_MEM    = 2'b10;
parameter SEL_BUS_R0     = 3'b000;
parameter SEL_BUS_R1     = 3'b001;
parameter SEL_BUS_R2     = 3'b010;
parameter SEL_BUS_R3     = 3'b011;
parameter SEL_BUS_PC     = 3'b100;



reg       ld_reg = 0;
reg [2:0] nstate = 0;

assign ld_r0 = (dest == 2'b00) ? ld_reg : 1'b0;
assign ld_r1 = (dest == 2'b01) ? ld_reg : 1'b0;
assign ld_r2 = (dest == 2'b10) ? ld_reg : 1'b0;
assign ld_r3 = (dest == 2'b11) ? ld_reg : 1'b0;

wire [3:0] opcode = instruction [7:4];
wire [3:0] cond   = instruction [3:0]; 
wire [1:0] src    = instruction [3:2];
wire [1:0] dest   = instruction [1:0];

always @ (posedge clk or negedge clr)
  begin
    if(!clr)
        pstate <= STATE_IDLE;
    else
        pstate <= nstate;
  end

always @*
  begin
    ld_reg = 0;
    ld_pc = 0;
    ld_ir = 0;
    ld_address_reg = 0;
    ld_reg_y = 0;
    ld_reg_z = 0;
    inc_pc = 0;

    read  = 0;
    write = 0;

    case(pstate)
        STATE_IDLE   : begin 
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 0;
            write          = 0;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_DB; 
            sig_halt       = 0;
            nstate         = STATE_FETCH1; 
        end
        
        STATE_FETCH1 : begin
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 0;
            write          = 0;
            ld_address_reg = 1;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_DB; 
            nstate         = STATE_FETCH2;
        end
        
        STATE_FETCH2 : begin
            sig_halt       = 0;
            ld_reg         = 0;
            read           = 1;
            write          = 0;
            ld_ir          = 1;
            inc_pc         = 1;
            sel_dbus_mux   = SEL_BUS_PC;
            sel_bus2_mux   = SEL_BUS_MEM;
            nstate         = STATE_DECODE;
        end
        
        STATE_DECODE : case (opcode)
                    `OPNOP     : begin
                      sig_halt       = 0;
                      ld_reg         = 0;
                      nstate         = STATE_FETCH1;
                    end
                    `OPADD, `OPADC, `OPSUB, `OPAND, `OPEOR, `OPIOR : begin
                                sig_halt     = 0;
                                ld_reg       = 0;
                                ld_reg_y     = 1;
                                sel_dbus_mux = {1'b0, src};
                                sel_bus2_mux = SEL_BUS_DB; 
                                nstate       = STATE_EXECUTE;
                    end
                    `OPNOT     : begin
                                sig_halt       = 0;
                                ld_reg         = 1;
                                ld_reg_z       = 1;
                                sel_dbus_mux   = {1'b0, src};
                                sel_bus2_mux   = SEL_BUS_ALU; 
                                nstate         = STATE_FETCH1;
                    end
                    `OPRD      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPWR      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPLD      : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPSTO     : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = {1'b0, dest};
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                    end
                    `OPBR      : begin
                                  case( cond )
                                    `BRA  : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end
                                    `BRN  : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 0;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRC  : if(carry == 1'b1) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRZ  : if(zero == 1'b1) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRNC : if(carry == 1'b0) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRNZ : if(zero == 1'b0) begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             sel_dbus_mux   = SEL_BUS_PC;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_STATE1;
                                           end else begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             inc_pc         = 1;
                                             nstate         = STATE_FETCH1;
                                           end
                                    `BRRJ : begin
                                             sig_halt       = 0;
                                             ld_reg         = 0;
                                             ld_address_reg = 1;
                                             ld_pc          = 1;
                                             sel_dbus_mux   = SEL_BUS_R3;
                                             sel_bus2_mux   = SEL_BUS_DB;
                                             nstate         = STATE_FETCH1;
                                           end
                                    default : begin
                                                sig_halt       = 0;
                                                ld_reg         = 0;
                                                ld_address_reg = 0;
                                                sel_dbus_mux   = SEL_BUS_PC;
                                                sel_bus2_mux   = SEL_BUS_DB;
                                                nstate         = STATE_FETCH1;
                                              end
                                  endcase
                                end
                    `OPBIT     : begin
                                  case( cond[2:0] )
                                    3'b000 : begin
                                               if(regR0[0] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b001 : begin
                                               if(regR0[1] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b010 : begin
                                               if(regR0[2] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b011 : begin
                                               if(regR0[3] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b100 : begin
                                               if(regR0[4] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b101 : begin
                                               if(regR0[5] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b110 : begin
                                               if(regR0[6] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                    3'b111 : begin
                                               if(regR0[7] == cond[3]) begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 ld_address_reg = 1;
                                                 sel_dbus_mux   = SEL_BUS_PC;
                                                 sel_bus2_mux   = SEL_BUS_DB;
                                                 nstate         = STATE_STATE1;
                                               end else begin
                                                 sig_halt       = 0;
                                                 ld_reg         = 0;
                                                 inc_pc         = 1;
                                                 nstate         = STATE_FETCH1;
                                               end
                                             end
                                  endcase
                                end
                    `OPBRC     : if(carry == 1) begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                ld_address_reg = 1;
                                sel_dbus_mux   = SEL_BUS_PC;
                                sel_bus2_mux   = SEL_BUS_DB;
                                nstate         = STATE_STATE1;
                              end else begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                inc_pc         = 1;
                                nstate         = STATE_FETCH1;
                    end
                    `OPHALT    : begin
                                sig_halt       = 0;
                                ld_reg         = 0;
                                nstate         = STATE_HALT;
                    end
                    default : begin 
                                sig_halt       = 0;
                                ld_reg         = 0;
                                nstate = STATE_HALT;
                    end
                endcase

        STATE_EXECUTE : begin
            sig_halt     = 0;
            ld_reg       = 1;
            ld_reg_z     = 1;
            sel_dbus_mux = {1'b0, dest};
            sel_bus2_mux = SEL_BUS_ALU;
            nstate       = STATE_FETCH1;
        end
        
        STATE_STATE1 : begin
          case(opcode)
            `OPRD : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_address_reg = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_STATE2;
            end
            `OPWR : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_address_reg = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_STATE2;
            end
            `OPLD : begin
              sig_halt       = 0;
              ld_reg         = 1;
              read           = 1;
              inc_pc         = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_FETCH1;
            end
            `OPSTO : begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 0;
              write          = 1;
              sel_dbus_mux   = {1'b0, src};
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
            `OPBR, `OPBRC, `OPBIT: begin
              sig_halt       = 0;
              ld_reg         = 0;
              read           = 1;
              ld_pc          = 1;
              sel_dbus_mux   = SEL_BUS_PC;
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
          endcase
        end
        
        STATE_STATE2 : begin
          case(opcode)
            `OPRD : begin
              sig_halt       = 0;
              ld_reg         = 1;
              read           = 1;
              sel_bus2_mux   = SEL_BUS_MEM;
              sel_dbus_mux   = SEL_BUS_PC;
              nstate         = STATE_FETCH1;
            end
            `OPWR : begin
              sig_halt       = 0;
              ld_reg         = 0;
              write          = 1;
              sel_dbus_mux   = {1'b0, src};
              sel_bus2_mux   = SEL_BUS_MEM;
              nstate         = STATE_FETCH1;
            end
          endcase
        end
        
        STATE_HALT: begin
            ld_reg           = 0;
            sig_halt         = 1;
            nstate           = STATE_HALT;
        end
        default: nstate      = STATE_IDLE;
    endcase
  end

endmodule