data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v:127: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module noc_arq_1to2mux #(
    `include "noc_parameter.vh"
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload_i,
    output reg                         stall_o,


    output reg                         ack_wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] ack_header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] ack_payload_o,
    input  wire                        ack_stall_i,


    output reg                         wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] payload_o,
    input  wire                        stall_i
);

    localparam OUT0 = 2'h0;
    localparam OUT1 = 2'h1;
    localparam OUT2 = 2'h2;

    reg  [1:0] r_arbiter_result, rin_arbiter_result;
    reg        r_burst_active, rin_burst_active;

    wire                     noc_burst_in = header_i[NOC_HEADER_SIZE-1];
    wire [NOC_MODE_SIZE-1:0] noc_mode_in = payload_i[NOC_PAYLOAD_SIZE-1:NOC_PAYLOAD_SIZE-NOC_MODE_SIZE];
    


    always @(posedge clk_i or negedge reset_q_i) begin
        if (reset_q_i == 1'b0) begin
            r_arbiter_result <= OUT0;
            r_burst_active <= 1'b0;
        end
        else begin
            r_arbiter_result <= rin_arbiter_result;
            r_burst_active <= rin_burst_active;
        end
    end



    always @* begin
        rin_arbiter_result = r_arbiter_result;


        if (!r_burst_active) begin
            if (wrreq_i) begin
                if (noc_mode_in == MODE_ARQ_ACK) begin
                    rin_arbiter_result = OUT1;
                end else begin
                    rin_arbiter_result = OUT2;
                end
            end
            else begin
                rin_arbiter_result = OUT0;
            end
        end
    end



    always @* begin
        case(rin_arbiter_result)
            OUT1: begin
                ack_wrreq_o = wrreq_i;
                ack_header_o = header_i;
                ack_payload_o = payload_i;

                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                stall_o = ack_stall_i;
            end

            OUT2: begin
                ack_wrreq_o = 1'b0;
                ack_header_o = {NOC_HEADER_SIZE{1'b0}};
                ack_payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                wrreq_o = wrreq_i;
                header_o = header_i;
                payload_o = payload_i;

                stall_o = stall_i;
            end

            default: begin
                ack_wrreq_o = 1'b0;
                ack_header_o = {NOC_HEADER_SIZE{1'b0}};
                ack_payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                stall_o = 1'b1;
            end
        endcase
    end



    always @* begin
        rin_burst_active = r_burst_active;
        if (!stall_o && wrreq_i) begin
            if (noc_burst_in) begin
                rin_burst_active = 1'b1;
            end else begin
                rin_burst_active = 1'b0;
            end
        end
    end


endmodule
module noc_arq_1to2mux #(
    `include "noc_parameter.vh"
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        wrreq_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload_i,
    output reg                         stall_o,


    output reg                         ack_wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] ack_header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] ack_payload_o,
    input  wire                        ack_stall_i,


    output reg                         wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] payload_o,
    input  wire                        stall_i
);


    localparam OUT0 = 2'h0;
    localparam OUT1 = 2'h1;
    localparam OUT2 = 2'h2;

    reg  [1:0] r_arbiter_result, rin_arbiter_result;
    reg        r_burst_active, rin_burst_active;

    wire                     noc_burst_in = header_i[NOC_HEADER_SIZE-1];
    wire [NOC_MODE_SIZE-1:0] noc_mode_in = payload_i[NOC_PAYLOAD_SIZE-1:NOC_PAYLOAD_SIZE-NOC_MODE_SIZE];
    


    always @(posedge clk_i or negedge reset_q_i) begin
        if (reset_q_i == 1'b0) begin
            r_arbiter_result <= OUT0;
            r_burst_active <= 1'b0;
        end
        else begin
            r_arbiter_result <= rin_arbiter_result;
            r_burst_active <= rin_burst_active;
        end
    end



    always @* begin
        rin_arbiter_result = r_arbiter_result;


        if (!r_burst_active) begin
            if (wrreq_i) begin
                if (noc_mode_in == MODE_ARQ_ACK) begin
                    rin_arbiter_result = OUT1;
                end else begin
                    rin_arbiter_result = OUT2;
                end
            end
            else begin
                rin_arbiter_result = OUT0;
            end
        end
    end



    always @* begin
        case(rin_arbiter_result)
            OUT1: begin
                ack_wrreq_o = wrreq_i;
                ack_header_o = header_i;
                ack_payload_o = payload_i;

                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                stall_o = ack_stall_i;
            end

            OUT2: begin
                ack_wrreq_o = 1'b0;
                ack_header_o = {NOC_HEADER_SIZE{1'b0}};
                ack_payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                wrreq_o = wrreq_i;
                header_o = header_i;
                payload_o = payload_i;

                stall_o = stall_i;
            end

            default: begin
                ack_wrreq_o = 1'b0;
                ack_header_o = {NOC_HEADER_SIZE{1'b0}};
                ack_payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};

                stall_o = 1'b1;
            end
        endcase
    end



    always @* begin
        rin_burst_active = r_burst_active;
        if (!stall_o && wrreq_i) begin
            if (noc_burst_in) begin
                rin_burst_active = 1'b1;
            end else begin
                rin_burst_active = 1'b0;
            end
        end
    end


endmodule