data/full_repos/permissive/522534105/RTL_files/Top_design.v
1: b"%Error: data/full_repos/permissive/522534105/RTL_files/Top_design.v:41: Cannot find file containing module: 'Datapath_unit'\n Datapath_unit DU(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Datapath_unit\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Datapath_unit.v\n             data/full_repos/permissive/522534105/RTL_files,data/full_repos/permissive/522534105/Datapath_unit.sv\n             Datapath_unit\n             Datapath_unit.v\n             Datapath_unit.sv\n             obj_dir/Datapath_unit\n             obj_dir/Datapath_unit.v\n             obj_dir/Datapath_unit.sv\n%Error: data/full_repos/permissive/522534105/RTL_files/Top_design.v:62: Cannot find file containing module: 'Controller'\n  Controller CU(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Top_design(
input i_clk , 
input start , 
input i_rst_n , 
input [`N_WIDTH_DATA-1:0] op_1 , 
input [`N_WIDTH_Q-1:0] op_2 , 
output wire [`N_WIDTH_DATA-1:0] o_Q_out , 
output wire [`N_WIDTH_DATA-1:0] o_ACC_out , 
output o_assert_done ,
output C_o 
   );
   

   wire load_Acc , load_Q, load_M, add_sub_en  , sel_Mux , c_enable , i_clr_q   ; 
   wire Q_n , Q ;
   
 Datapath_unit DU(
i_clk , 
i_rst_n ,
load_Acc , 
load_Q , 
load_M , 
load_Qn ,
add_sub_en ,
sel_Mux ,
c_enable ,  
i_clr_q  ,  
op_1, 
op_2, 
o_Q_out, 
o_ACC_out , 
Q_n, 
Q ,  
C_o , 
o_assert_done  
 );
  
  Controller CU(
i_clk , 
start  , 
i_rst_n ,
Q  , 
Q_n, 
o_assert_done , 
load_Acc , 
load_Q , 
load_M , 
add_sub_en ,
sel_Mux  , 
c_enable, 
i_clr_q  
);  
    
    
endmodule
module Top_design(
input i_clk , 
input start , 
input i_rst_n , 
input [`N_WIDTH_DATA-1:0] op_1 , 
input [`N_WIDTH_Q-1:0] op_2 , 
output wire [`N_WIDTH_DATA-1:0] o_Q_out , 
output wire [`N_WIDTH_DATA-1:0] o_ACC_out , 
output o_assert_done ,
output C_o 
   );

   

   wire load_Acc , load_Q, load_M, add_sub_en  , sel_Mux , c_enable , i_clr_q   ; 
   wire Q_n , Q ;
   
 Datapath_unit DU(
i_clk , 
i_rst_n ,
load_Acc , 
load_Q , 
load_M , 
load_Qn ,
add_sub_en ,
sel_Mux ,
c_enable ,  
i_clr_q  ,  
op_1, 
op_2, 
o_Q_out, 
o_ACC_out , 
Q_n, 
Q ,  
C_o , 
o_assert_done  
 );
  
  Controller CU(
i_clk , 
start  , 
i_rst_n ,
Q  , 
Q_n, 
o_assert_done , 
load_Acc , 
load_Q , 
load_M , 
add_sub_en ,
sel_Mux  , 
c_enable, 
i_clr_q  
);  
    
    
endmodule