data/full_repos/permissive/503053625/resources/unused/pulse_counter.v
data/verilator_xmls/ab73a775-3fed-49c9-b7c4-690a30fbcd3e.xml
module pulse_counter
#(
	parameter DATA_WIDTH = 32
)
(
	input  clk,
	input  en,
	output  [DATA_WIDTH - 1 : 0] count_val
);

	reg [DATA_WIDTH - 1 : 0] count = 0;
	assign count_val = count;

always @ (posedge clk)
	begin
	if (!en)
	begin
		count <= 0;
	end
	else
	begin
		count = count + 1;
	end
	end
endmodule
module pulse_counter
#(
	parameter DATA_WIDTH = 32
)
(
	input  clk,
	input  en,
	output  [DATA_WIDTH - 1 : 0] count_val
);


	reg [DATA_WIDTH - 1 : 0] count = 0;
	assign count_val = count;

always @ (posedge clk)
	begin
	if (!en)
	begin
		count <= 0;
	end
	else
	begin
		count = count + 1;
	end
	end
endmodule