data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_comb.v
1: b"%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_comb.v:57: Cannot find file containing module: 'jtopl_pm'\njtopl_pm u_pm(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_pm\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_pm.v\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_pm.sv\n             jtopl_pm\n             jtopl_pm.v\n             jtopl_pm.sv\n             obj_dir/jtopl_pm\n             obj_dir/jtopl_pm.v\n             obj_dir/jtopl_pm.sv\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_comb.v:65: Cannot find file containing module: 'jtopl_pg_inc'\njtopl_pg_inc u_inc(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_comb.v:74: Cannot find file containing module: 'jtopl_pg_sum'\njtopl_pg_sum u_sum(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_comb.v:83: Cannot find file containing module: 'jtopl_pg_rhy'\njtopl_pg_rhy u_rhy(\n^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module jtopl_pg_comb (
    input wire      [ 2:0]  block,
    input wire      [ 9:0]  fnum,

    input wire      [ 2:0]  vib_cnt,
    input wire              vib_dep,
    input wire              viben,

    output wire      [ 3:0]  keycode,

    output wire     [16:0]  phinc_out,

    input wire      [ 3:0]  mul,
    input wire      [18:0]  phase_in,
    input wire              pg_rst,

    input wire       [16:0]  phinc_in,

    input wire              noise,
    input wire      [ 9:0]  hh,
    input wire              hh_en,
    input wire              tc_en,
    input wire              sd_en,
    input wire              rm_xor,

    output wire      [18:0]  phase_out,
    output wire     [ 9:0]  phase_op
);

wire signed [3:0] pm_offset;
wire        [9:0] phase_pre;

assign keycode = { block, fnum[9] };


jtopl_pm u_pm(
    .vib_cnt    ( vib_cnt   ),
    .fnum       ( fnum      ),
    .vib_dep    ( vib_dep   ),
    .viben      ( viben     ),
    .pm_offset  ( pm_offset )
);

jtopl_pg_inc u_inc(
    .block      ( block     ),
    .fnum       ( fnum      ),
    .pm_offset  ( pm_offset ),
    .phinc_pure ( phinc_out )
);



jtopl_pg_sum u_sum(
    .mul        ( mul           ),
    .phase_in   ( phase_in      ),
    .pg_rst     ( pg_rst        ),
    .phinc_pure ( phinc_in      ),
    .phase_out  ( phase_out     ),
    .phase_op   ( phase_pre     )
);

jtopl_pg_rhy u_rhy(
    .phase_pre  ( phase_pre ),

    .noise      ( noise     ),
    .hh         ( hh        ),
    .hh_en      ( hh_en     ),
    .tc_en      ( tc_en     ),
    .sd_en      ( sd_en     ),
    .rm_xor     ( rm_xor    ),
    .phase_op   ( phase_op  )
);

endmodule
module jtopl_pg_comb (
    input wire      [ 2:0]  block,
    input wire      [ 9:0]  fnum,

    input wire      [ 2:0]  vib_cnt,
    input wire              vib_dep,
    input wire              viben,

    output wire      [ 3:0]  keycode,

    output wire     [16:0]  phinc_out,

    input wire      [ 3:0]  mul,
    input wire      [18:0]  phase_in,
    input wire              pg_rst,

    input wire       [16:0]  phinc_in,

    input wire              noise,
    input wire      [ 9:0]  hh,
    input wire              hh_en,
    input wire              tc_en,
    input wire              sd_en,
    input wire              rm_xor,

    output wire      [18:0]  phase_out,
    output wire     [ 9:0]  phase_op
);


wire signed [3:0] pm_offset;
wire        [9:0] phase_pre;

assign keycode = { block, fnum[9] };


jtopl_pm u_pm(
    .vib_cnt    ( vib_cnt   ),
    .fnum       ( fnum      ),
    .vib_dep    ( vib_dep   ),
    .viben      ( viben     ),
    .pm_offset  ( pm_offset )
);

jtopl_pg_inc u_inc(
    .block      ( block     ),
    .fnum       ( fnum      ),
    .pm_offset  ( pm_offset ),
    .phinc_pure ( phinc_out )
);



jtopl_pg_sum u_sum(
    .mul        ( mul           ),
    .phase_in   ( phase_in      ),
    .pg_rst     ( pg_rst        ),
    .phinc_pure ( phinc_in      ),
    .phase_out  ( phase_out     ),
    .phase_op   ( phase_pre     )
);

jtopl_pg_rhy u_rhy(
    .phase_pre  ( phase_pre ),

    .noise      ( noise     ),
    .hh         ( hh        ),
    .hh_en      ( hh_en     ),
    .tc_en      ( tc_en     ),
    .sd_en      ( sd_en     ),
    .rm_xor     ( rm_xor    ),
    .phase_op   ( phase_op  )
);

endmodule