data/full_repos/permissive/481044442/BDCDrv/rx_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/rx_fifo.v:27: Bit extraction of array[9:0] requires 4 bit index, not 8 bits.\n                                                                        : ... In instance rx_fifo\n         array[used]<=put_byte;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rx_fifo(clk,reset,put_pulse,put_byte,full,empty);
input clk;
input reset;
input put_pulse;
input [7:0] put_byte;
output full;
output empty;


reg [7:0] array [0:9];

reg [7:0] used;


assign full=(used==8'd10)?1'b1:1'b0;

assign empty=(used==8'd0)?1'b1:1'b0;

reg [7:0] i;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				used<=8'd0;			
	          end
	else begin
			if(put_pulse && !full) begin
									array[used]<=put_byte;
									used<=used+1'b1;
			                       end
		 end
end
endmodule
module rx_fifo(clk,reset,put_pulse,put_byte,full,empty);

input clk;
input reset;
input put_pulse;
input [7:0] put_byte;
output full;
output empty;


reg [7:0] array [0:9];

reg [7:0] used;


assign full=(used==8'd10)?1'b1:1'b0;

assign empty=(used==8'd0)?1'b1:1'b0;

reg [7:0] i;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				used<=8'd0;			
	          end
	else begin
			if(put_pulse && !full) begin
									array[used]<=put_byte;
									used<=used+1'b1;
			                       end
		 end
end
endmodule