data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/rom.v
data/verilator_xmls/dcbbb60f-3640-49f7-b0f9-673aed7cd1e5.xml
module rom(data,address);
parameter DATA_WIDTH=32;
parameter ADDR_WIDTH=27;

output	[DATA_WIDTH-1:0] data;
input	[ADDR_WIDTH-1:0] address;

reg	[DATA_WIDTH-1:0]	mem[0:1 << ADDR_WIDTH-1];

assign data=mem[address];

initial begin
	$readmemb("prog.list",mem);
end

endmodule
module rom(data,address);

parameter DATA_WIDTH=32;
parameter ADDR_WIDTH=27;

output	[DATA_WIDTH-1:0] data;
input	[ADDR_WIDTH-1:0] address;

reg	[DATA_WIDTH-1:0]	mem[0:1 << ADDR_WIDTH-1];

assign data=mem[address];

initial begin
	$readmemb("prog.list",mem);
end

endmodule