data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montinvp2.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montinvp2.v:62: Cannot find file containing module: 'cla'\ncla #(WIDTH) icla\n^~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/cla\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/cla.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/cla.sv\n             cla\n             cla.v\n             cla.sv\n             obj_dir/cla\n             obj_dir/cla.v\n             obj_dir/cla.sv\n%Error: Exiting due to 1 error(s)\n"
module montinvp2
    (
     clk,
     rst,
     ainv,
     mod,
     exp,
     en,
     inv,
     vld
     );




parameter WIDTH = 256;
parameter CWID  = 10;
parameter INIT  = 0;




input     clk;
input     rst;
input [WIDTH-1:0] ainv;
input [WIDTH-1:0] mod;
input [CWID-1:0]  exp;
input             en;

output [WIDTH-1:0] inv;
output             vld;





reg                vld;




reg [CWID-1:0]     cnt;
reg [WIDTH-1:0]    r;
reg [WIDTH-1:0]    p;

wire [WIDTH-1:0]   pr;
wire               carry;

cla #(WIDTH) icla
    (
     .a(p),
     .b(r),
     .sum(pr),
     .c(carry)
     );
reg                stop;

always @(posedge clk)
    begin
    if (rst)
        begin
        cnt <= INIT;
        r   <= INIT;
        p   <= INIT;
        vld <= INIT;
        stop    <= 1'b1;
        end
    else if (en)
        begin
        cnt <= exp - WIDTH;
        r   <= ainv;
        p   <= mod;
        vld <= INIT;
        stop    <= INIT;
        end
    else if (cnt > 0)
        begin
        cnt <= cnt - 1;
        stop    <= INIT;
        if (r[0])
            begin
            r   <= {carry, pr[WIDTH-1:1]};
            end
        else
            begin
            r   <= {1'b0, r[WIDTH-1:1]};
            end
        end
    else if (!stop) 
        begin
        vld     <= 1'b1;
        stop    <= 1'b1;
        end
    else
        begin
        vld <= INIT;
        end
    end

assign inv = r;

endmodule
module montinvp2
    (
     clk,
     rst,
     ainv,
     mod,
     exp,
     en,
     inv,
     vld
     );





parameter WIDTH = 256;
parameter CWID  = 10;
parameter INIT  = 0;




input     clk;
input     rst;
input [WIDTH-1:0] ainv;
input [WIDTH-1:0] mod;
input [CWID-1:0]  exp;
input             en;

output [WIDTH-1:0] inv;
output             vld;





reg                vld;




reg [CWID-1:0]     cnt;
reg [WIDTH-1:0]    r;
reg [WIDTH-1:0]    p;

wire [WIDTH-1:0]   pr;
wire               carry;

cla #(WIDTH) icla
    (
     .a(p),
     .b(r),
     .sum(pr),
     .c(carry)
     );
reg                stop;

always @(posedge clk)
    begin
    if (rst)
        begin
        cnt <= INIT;
        r   <= INIT;
        p   <= INIT;
        vld <= INIT;
        stop    <= 1'b1;
        end
    else if (en)
        begin
        cnt <= exp - WIDTH;
        r   <= ainv;
        p   <= mod;
        vld <= INIT;
        stop    <= INIT;
        end
    else if (cnt > 0)
        begin
        cnt <= cnt - 1;
        stop    <= INIT;
        if (r[0])
            begin
            r   <= {carry, pr[WIDTH-1:1]};
            end
        else
            begin
            r   <= {1'b0, r[WIDTH-1:1]};
            end
        end
    else if (!stop) 
        begin
        vld     <= 1'b1;
        stop    <= 1'b1;
        end
    else
        begin
        vld <= INIT;
        end
    end

assign inv = r;

endmodule