data/full_repos/permissive/49832463/rtl/UART.v
1: b"%Error: data/full_repos/permissive/49832463/rtl/UART.v:29: Cannot find file containing module: 'uart_rx'\n uart_rx RX0 (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49832463/rtl,data/full_repos/permissive/49832463/uart_rx\n             data/full_repos/permissive/49832463/rtl,data/full_repos/permissive/49832463/uart_rx.v\n             data/full_repos/permissive/49832463/rtl,data/full_repos/permissive/49832463/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/49832463/rtl/UART.v:40: Cannot find file containing module: 'uart_tx'\n uart_tx TX0 (\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module UART(

	   input CLK,
	   input RESET,
	   input RX,

	   input START,
	   input [7:0] DATA_TX,

	   input [11:0] WORK_FR,
		
	   output TX,
	   output [7:0] DATA_RX,
	   output PARITY_RX,
		
	   output READY_TX,
	   output READY
		
	  );


	uart_rx RX0 (
			.PCLK(CLK),
			.RESET(RESET),
			.RX_I(RX),
			.DATA_RX_O(DATA_RX),
			.WORK_FR(WORK_FR),
			.READY(READY),
			.PARITY_RX(PARITY_RX)
		      );


	uart_tx TX0 (
			.PCLK(CLK),
			.RESET(RESET),
			.START(START),
			.WORK_FR(WORK_FR),
			.DATA_TX_I(DATA_TX),
			.READY_TX(READY_TX),
			.TX_O(TX)
		    );

endmodule
module UART(

	   input CLK,
	   input RESET,
	   input RX,

	   input START,
	   input [7:0] DATA_TX,

	   input [11:0] WORK_FR,
		
	   output TX,
	   output [7:0] DATA_RX,
	   output PARITY_RX,
		
	   output READY_TX,
	   output READY
		
	  );



	uart_rx RX0 (
			.PCLK(CLK),
			.RESET(RESET),
			.RX_I(RX),
			.DATA_RX_O(DATA_RX),
			.WORK_FR(WORK_FR),
			.READY(READY),
			.PARITY_RX(PARITY_RX)
		      );


	uart_tx TX0 (
			.PCLK(CLK),
			.RESET(RESET),
			.START(START),
			.WORK_FR(WORK_FR),
			.DATA_TX_I(DATA_TX),
			.READY_TX(READY_TX),
			.TX_O(TX)
		    );

endmodule