data/full_repos/permissive/512700783/ALU_control_unit.v
data/verilator_xmls/e19b2f3d-6495-4a2a-a61d-604440c2a858.xml
module ALU_control_unit(ALU_Op, Function, ALU_control);
	input [1:0] ALU_Op;
	input [5:0] Function;
	output reg[2:0] ALU_control;

	always @(ALU_Op or Function)
	begin
		if(ALU_Op==0) begin
			ALU_control=2;
		end
		if(ALU_Op==1) begin
			ALU_control=3;
		end
		if(ALU_Op==2) begin
			if(Function==32) begin
				ALU_control=2;
			end
			if(Function==34) begin
				ALU_control=3;
			end
			if(Function==36) begin
				ALU_control=0;
			end
			if(Function==37) begin
				ALU_control=1;
			end
			if(Function==42) begin
				ALU_control=4;
			end
		end
	end
endmodule
module ALU_control_unit(ALU_Op, Function, ALU_control);

	input [1:0] ALU_Op;
	input [5:0] Function;
	output reg[2:0] ALU_control;

	always @(ALU_Op or Function)
	begin
		if(ALU_Op==0) begin
			ALU_control=2;
		end
		if(ALU_Op==1) begin
			ALU_control=3;
		end
		if(ALU_Op==2) begin
			if(Function==32) begin
				ALU_control=2;
			end
			if(Function==34) begin
				ALU_control=3;
			end
			if(Function==36) begin
				ALU_control=0;
			end
			if(Function==37) begin
				ALU_control=1;
			end
			if(Function==42) begin
				ALU_control=4;
			end
		end
	end
endmodule