data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:214: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sub_counter\' generates 9 bits.\n                                                                              : ... In instance opl2_intf.timer1\n        if (!sub_counter) begin\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:79: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 8 bits.\n                                                                             : ... In instance opl2_intf\n        reg_num <= din;\n                ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/opl2_intf.sv:183: Cannot find file containing module: \'opl2\'\nopl2 opl2\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2.v\n             data/full_repos/permissive/452215364/rtl/opl2,data/full_repos/permissive/452215364/opl2.sv\n             opl2\n             opl2.v\n             opl2.sv\n             obj_dir/opl2\n             obj_dir/opl2.v\n             obj_dir/opl2.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module timer #(parameter RES)
(
    input         ce_1us,
	input   [7:0] preset,
	input         active,
	output reg    overflow_pulse
);

always @(posedge ce_1us) begin
    reg [7:0] counter;
	reg [8:0] sub_counter;

	overflow_pulse <= 0;

	if (active) begin
        sub_counter <= sub_counter - 1'd1;
        if (!sub_counter) begin
            sub_counter <= RES[8:0];
            counter <= counter + 1'd1;
            if (&counter) begin
                overflow_pulse <= 1;
                counter <= preset;
            end
        end
	end else begin
		counter <= preset;
		sub_counter <= RES[8:0];
	end
end

endmodule
module timer #(parameter RES)
(
    input         ce_1us,
	input   [7:0] preset,
	input         active,
	output reg    overflow_pulse
);


always @(posedge ce_1us) begin
    reg [7:0] counter;
	reg [8:0] sub_counter;

	overflow_pulse <= 0;

	if (active) begin
        sub_counter <= sub_counter - 1'd1;
        if (!sub_counter) begin
            sub_counter <= RES[8:0];
            counter <= counter + 1'd1;
            if (&counter) begin
                overflow_pulse <= 1;
                counter <= preset;
            end
        end
	end else begin
		counter <= preset;
		sub_counter <= RES[8:0];
	end
end

endmodule