data/full_repos/permissive/479923049/regfile.v
data/verilator_xmls/9a051aab-0a08-474f-86c0-6f526d9aee71.xml
module regfile(data_in,writenum,write,readnum,clk,data_out);
    input   [15:0] data_in;
    input   [2:0] writenum, readnum;
    input   write, clk;
    output  [15:0] data_out;
    
    reg [15:0] data_out;
    
    wire [7:0] writenum_decoded, and_out, readnum_decoded;
    wire [15:0] R0, R1, R2, R3, R4, R5, R6, R7;
    

    three_eight_dec writedec (writenum, writenum_decoded);

    assign and_out = {write & writenum_decoded[7], 
                       write & writenum_decoded[6],
                       write & writenum_decoded[5],
                       write & writenum_decoded[4],
                       write & writenum_decoded[3],
                       write & writenum_decoded[2],
                       write & writenum_decoded[1],
                       write & writenum_decoded[0]
                    };

    vDFFE register0 (clk, and_out[0], data_in, R0);
    vDFFE register1 (clk, and_out[1], data_in, R1);
    vDFFE register2 (clk, and_out[2], data_in, R2);
    vDFFE register3 (clk, and_out[3], data_in, R3);
    vDFFE register4 (clk, and_out[4], data_in, R4);
    vDFFE register5 (clk, and_out[5], data_in, R5);
    vDFFE register6 (clk, and_out[6], data_in, R6);
    vDFFE register7 (clk, and_out[7], data_in, R7);

    three_eight_dec readdec (readnum, readnum_decoded);

    always @(*) begin 
        case(readnum_decoded)
            8'b00000001: data_out = R0; 
            8'b00000010: data_out = R1;
            8'b00000100: data_out = R2; 
            8'b00001000: data_out = R3; 
            8'b00010000: data_out = R4; 
            8'b00100000: data_out = R5;
            8'b01000000: data_out = R6; 
            8'b10000000: data_out = R7; 
            default: data_out = {(16){1'bx}};
        endcase
    end
endmodule
module regfile(data_in,writenum,write,readnum,clk,data_out);

    input   [15:0] data_in;
    input   [2:0] writenum, readnum;
    input   write, clk;
    output  [15:0] data_out;
    
    reg [15:0] data_out;
    
    wire [7:0] writenum_decoded, and_out, readnum_decoded;
    wire [15:0] R0, R1, R2, R3, R4, R5, R6, R7;
    

    three_eight_dec writedec (writenum, writenum_decoded);

    assign and_out = {write & writenum_decoded[7], 
                       write & writenum_decoded[6],
                       write & writenum_decoded[5],
                       write & writenum_decoded[4],
                       write & writenum_decoded[3],
                       write & writenum_decoded[2],
                       write & writenum_decoded[1],
                       write & writenum_decoded[0]
                    };

    vDFFE register0 (clk, and_out[0], data_in, R0);
    vDFFE register1 (clk, and_out[1], data_in, R1);
    vDFFE register2 (clk, and_out[2], data_in, R2);
    vDFFE register3 (clk, and_out[3], data_in, R3);
    vDFFE register4 (clk, and_out[4], data_in, R4);
    vDFFE register5 (clk, and_out[5], data_in, R5);
    vDFFE register6 (clk, and_out[6], data_in, R6);
    vDFFE register7 (clk, and_out[7], data_in, R7);

    three_eight_dec readdec (readnum, readnum_decoded);

    always @(*) begin 
        case(readnum_decoded)
            8'b00000001: data_out = R0; 
            8'b00000010: data_out = R1;
            8'b00000100: data_out = R2; 
            8'b00001000: data_out = R3; 
            8'b00010000: data_out = R4; 
            8'b00100000: data_out = R5;
            8'b01000000: data_out = R6; 
            8'b10000000: data_out = R7; 
            default: data_out = {(16){1'bx}};
        endcase
    end
endmodule