data/full_repos/permissive/503973366/SIM/acc_v2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:74: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:78: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:87: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:96: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:105: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:115: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:128: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:135: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:142: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:154: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:168: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:175: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:182: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:194: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_v2_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: Exiting due to 14 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ACC_v2_TB #(

    

    parameter PE_SIZE           = 14,
    parameter DATA_WIDTH        = 8,
    parameter PSUM_WIDTH        = 32,

    parameter SLICING_IDX       = 32,

    parameter WEIGHT_ROW_NUM    = 70,
    parameter WEIGHT_COL_NUM    = 294
    )
    (


    );
    

    reg   clk;
    reg   rst_n;
    

    reg    [PE_SIZE-1:0]   psum_en_row_i;
    

    reg    [PSUM_WIDTH*PE_SIZE-1:0]     psum_row_i;
    wire   [DATA_WIDTH*PE_SIZE-1:0]     ofmap_row_o;
    wire                                ofmap_valid_o;
    
    reg [PSUM_WIDTH-1:0]    test_num;
    
    

    ACC_v2 #(
        .PE_SIZE        ( PE_SIZE ),
        .DATA_WIDTH     ( DATA_WIDTH ),
        .PSUM_WIDTH     ( PSUM_WIDTH ),
        .SLICING_IDX    ( SLICING_IDX ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_v2(
        .clk            ( clk            ),
        .rst_n          ( rst_n          ),
        .psum_en_row_i  ( psum_en_row_i  ),
        .psum_row_i     ( psum_row_i     ),
        .ofmap_row_o    ( ofmap_row_o    ),
        .ofmap_valid_o  ( ofmap_valid_o  )
    );


    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;


    initial begin

        rst_n = 1'b1;
        psum_en_row_i = {(PE_SIZE){1'b0}};
        psum_row_i = {(DATA_WIDTH){1'b0}};
        


        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;       

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;       
        
        test_num = 'h0000_0100;
        


        for (i=0; i < PE_SIZE; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'h0000_0100;
        
        for (i=0; i < PE_SIZE*4; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b1}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'h0000_0100;
        
        for (i=0; i < PE_SIZE-1; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'd0;
        

        repeat (5) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b0}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
        

        
        repeat (19) begin
            
            test_num = 'h0100_0000;
            
            for (i=0; i < PE_SIZE; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            for (i=0; i < PE_SIZE*4; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i = {(PE_SIZE){1'b1}};
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            for (i=0; i < PE_SIZE; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            

            
            test_num = 0;
            
            repeat (5) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i = {(PE_SIZE){1'b0}};
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
        end
        
        

        
        test_num = 'h0100_0000;
        
        for (i=0; i < PE_SIZE; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
            psum_row_i[(PE_SIZE-i)*PSUM_WIDTH-1 -: PSUM_WIDTH] = test_num;
        end
            
        for (i=0; i < PE_SIZE*4; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b1}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
            
        for (i=0; i < PE_SIZE-1; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
            psum_row_i[(PE_SIZE-i)*PSUM_WIDTH-1 -: PSUM_WIDTH] = {(PSUM_WIDTH){1'b0}};
        end
        
        


        
        test_num = 0;
        repeat (5) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b0}};
            psum_row_i = {(PE_SIZE){test_num}};
        end

    end


endmodule
module ACC_v2_TB #(

    

    parameter PE_SIZE           = 14,
    parameter DATA_WIDTH        = 8,
    parameter PSUM_WIDTH        = 32,

    parameter SLICING_IDX       = 32,

    parameter WEIGHT_ROW_NUM    = 70,
    parameter WEIGHT_COL_NUM    = 294
    )
    (


    );

    

    reg   clk;
    reg   rst_n;
    

    reg    [PE_SIZE-1:0]   psum_en_row_i;
    

    reg    [PSUM_WIDTH*PE_SIZE-1:0]     psum_row_i;
    wire   [DATA_WIDTH*PE_SIZE-1:0]     ofmap_row_o;
    wire                                ofmap_valid_o;
    
    reg [PSUM_WIDTH-1:0]    test_num;
    
    

    ACC_v2 #(
        .PE_SIZE        ( PE_SIZE ),
        .DATA_WIDTH     ( DATA_WIDTH ),
        .PSUM_WIDTH     ( PSUM_WIDTH ),
        .SLICING_IDX    ( SLICING_IDX ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_v2(
        .clk            ( clk            ),
        .rst_n          ( rst_n          ),
        .psum_en_row_i  ( psum_en_row_i  ),
        .psum_row_i     ( psum_row_i     ),
        .ofmap_row_o    ( ofmap_row_o    ),
        .ofmap_valid_o  ( ofmap_valid_o  )
    );


    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;


    initial begin

        rst_n = 1'b1;
        psum_en_row_i = {(PE_SIZE){1'b0}};
        psum_row_i = {(DATA_WIDTH){1'b0}};
        


        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;       

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;       
        
        test_num = 'h0000_0100;
        


        for (i=0; i < PE_SIZE; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'h0000_0100;
        
        for (i=0; i < PE_SIZE*4; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b1}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'h0000_0100;
        
        for (i=0; i < PE_SIZE-1; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
            psum_row_i = {(PE_SIZE){test_num}};
        end
        
        test_num = 'd0;
        

        repeat (5) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b0}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
        

        
        repeat (19) begin
            
            test_num = 'h0100_0000;
            
            for (i=0; i < PE_SIZE; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            for (i=0; i < PE_SIZE*4; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i = {(PE_SIZE){1'b1}};
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            for (i=0; i < PE_SIZE; i=i+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
            

            
            test_num = 0;
            
            repeat (5) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_row_i = {(PE_SIZE){1'b0}};
                psum_row_i = {(PE_SIZE){test_num}};
            end
            
        end
        
        

        
        test_num = 'h0100_0000;
        
        for (i=0; i < PE_SIZE; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b1;
            psum_row_i[(PE_SIZE-i)*PSUM_WIDTH-1 -: PSUM_WIDTH] = test_num;
        end
            
        for (i=0; i < PE_SIZE*4; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b1}};
            psum_row_i = {(PE_SIZE){test_num}};
        end
            
        for (i=0; i < PE_SIZE-1; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i[(PE_SIZE-i)-1] = 1'b0;
            psum_row_i[(PE_SIZE-i)*PSUM_WIDTH-1 -: PSUM_WIDTH] = {(PSUM_WIDTH){1'b0}};
        end
        
        


        
        test_num = 0;
        repeat (5) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_row_i = {(PE_SIZE){1'b0}};
            psum_row_i = {(PE_SIZE){test_num}};
        end

    end


endmodule