data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #14;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #14;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #14;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #7\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #7\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #7\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #7\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #7\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/IMem_TB.v:11: Cannot find file containing module: \'IMem\'\n    IMem DUT (.clk(clk),.rd(rd),.addr_in(addr_in), .instr_out(instr_out));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/IMem\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/IMem.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/IMem.sv\n             IMem\n             IMem.v\n             IMem.sv\n             obj_dir/IMem\n             obj_dir/IMem.v\n             obj_dir/IMem.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IMem_TB(

    );
    reg  clk;
    reg  rd;
    reg  [31:0] addr_in;
    wire [31:0] instr_out;
    
    IMem DUT (.clk(clk),.rd(rd),.addr_in(addr_in), .instr_out(instr_out));
    
    initial begin: CLK_GEN
        forever begin
            clk <=1;
            #5;
            clk <=0;
            #5;
        end
    end
    
    initial begin:TEST_PROCESS
        rd=1'b0;
        #1;
        if(instr_out!=32'h00000000) $fatal("The Instruction memory or ROM is IDLE, no operation");
        #14;
        
        rd=1'b0;
        #1;
        if(addr_in!=32'h01000000) $fatal("Reset(active_low) has been invoked and the PC which is input to ROM has not reset to starting address");
        #14;
        
        rd=1'b1;
        #1;
        if(addr_in!=32'h01000000) $fatal("Reset(active_low) has been invoked and the PC which is input to ROM has not reset to starting address");
        #14;
        
        rd=1'b1;
        #1;
        addr_in=32'h01000000;
        #7
        if(instr_out!=32'h00100093) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #2
         addr_in=32'h01000004;
        #7
        if(instr_out!=32'h00200113) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h01000008;
        #7
        if(instr_out!=32'h002080b3) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h0100000c;
        #7
        if(instr_out!=32'hffdff06f) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h01000010;
        #7
        if(instr_out!=32'h00001117) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
        
     
        $display("All tests passed");
        $finish;
    end 
    
endmodule
module IMem_TB(

    );

    reg  clk;
    reg  rd;
    reg  [31:0] addr_in;
    wire [31:0] instr_out;
    
    IMem DUT (.clk(clk),.rd(rd),.addr_in(addr_in), .instr_out(instr_out));
    
    initial begin: CLK_GEN
        forever begin
            clk <=1;
            #5;
            clk <=0;
            #5;
        end
    end
    
    initial begin:TEST_PROCESS
        rd=1'b0;
        #1;
        if(instr_out!=32'h00000000) $fatal("The Instruction memory or ROM is IDLE, no operation");
        #14;
        
        rd=1'b0;
        #1;
        if(addr_in!=32'h01000000) $fatal("Reset(active_low) has been invoked and the PC which is input to ROM has not reset to starting address");
        #14;
        
        rd=1'b1;
        #1;
        if(addr_in!=32'h01000000) $fatal("Reset(active_low) has been invoked and the PC which is input to ROM has not reset to starting address");
        #14;
        
        rd=1'b1;
        #1;
        addr_in=32'h01000000;
        #7
        if(instr_out!=32'h00100093) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #2
         addr_in=32'h01000004;
        #7
        if(instr_out!=32'h00200113) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h01000008;
        #7
        if(instr_out!=32'h002080b3) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h0100000c;
        #7
        if(instr_out!=32'hffdff06f) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
         addr_in=32'h01000010;
        #7
        if(instr_out!=32'h00001117) $fatal("The Instruction memory or ROM is not reading the value at desired address correctly");
        #3
        
     
        $display("All tests passed");
        $finish;
    end 
    
endmodule