data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:51: Cannot find file containing module: 'bw_u1_soff_4x'\nbw_u1_soff_4x I257 (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_4x.sv\n             bw_u1_soff_4x\n             bw_u1_soff_4x.v\n             bw_u1_soff_4x.sv\n             obj_dir/bw_u1_soff_4x\n             obj_dir/bw_u1_soff_4x.v\n             obj_dir/bw_u1_soff_4x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:58: Cannot find file containing module: 'bw_u1_soffr_4x'\nbw_u1_soffr_4x I260 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:66: Cannot find file containing module: 'bw_u1_soffr_4x'\nbw_u1_soffr_4x I263 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:74: Cannot find file containing module: 'bw_u1_inv_4x'\nbw_u1_inv_4x I268 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:77: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I269 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:81: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I270 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:85: Cannot find file containing module: 'bw_u1_nand2_4x'\nbw_u1_nand2_4x I271 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:89: Cannot find file containing module: 'bw_u1_inv_4x'\nbw_u1_inv_4x I304 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:92: Cannot find file containing module: 'bw_u1_inv_4x'\nbw_u1_inv_4x I305 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:95: Cannot find file containing module: 'bw_io_ddr_pad_txrx_zctl'\nbw_io_ddr_pad_txrx_zctl I309 (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_ddr_uprcn.v:105: Cannot find file containing module: 'bw_io_ddr_rptr_vddcom'\nbw_io_ddr_rptr_vddcom I319 (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module bw_io_impctl_ddr_uprcn(oe ,vdd18 ,si_l ,so_l ,pad ,sclk ,cbu ,
     above ,clk ,se ,global_reset_n );
input [8:1]	cbu ;
output		so_l ;
output		pad ;
output		above ;
input		oe ;
input		vdd18 ;
input		si_l ;
input		sclk ;
input		clk ;
input		se ;
input		global_reset_n ;
supply1		vdd ;
supply0		vss ;
 
wire		net76 ;
wire		net77 ;
wire		sclk1 ;
wire		sclk2 ;
wire		scan1 ;
wire		vf ;
wire		net55 ;
wire		net59 ;
wire		net62 ;
wire		abvref ;
wire		net65 ;
wire		net68 ;
 
 
bw_u1_soff_4x I257 (
     .q               (sclk1 ),
     .so              (net76 ),
     .ck              (clk ),
     .d               (sclk ),
     .se              (se ),
     .sd              (net55 ) );
bw_u1_soffr_4x I260 (
     .q               (sclk2 ),
     .so              (scan1 ),
     .ck              (clk ),
     .d               (sclk1 ),
     .se              (se ),
     .sd              (net76 ),
     .r_l             (global_reset_n ) );
bw_u1_soffr_4x I263 (
     .q               (above ),
     .so              (net77 ),
     .ck              (clk ),
     .d               (net62 ),
     .se              (se ),
     .sd              (scan1 ),
     .r_l             (global_reset_n ) );
bw_u1_inv_4x I268 (
     .z               (net59 ),
     .a               (sclk2 ) );
bw_u1_nand2_4x I269 (
     .z               (net62 ),
     .a               (net68 ),
     .b               (net65 ) );
bw_u1_nand2_4x I270 (
     .z               (net65 ),
     .a               (net59 ),
     .b               (above ) );
bw_u1_nand2_4x I271 (
     .z               (net68 ),
     .a               (abvref ),
     .b               (sclk2 ) );
bw_u1_inv_4x I304 (
     .z               (net55 ),
     .a               (si_l ) );
bw_u1_inv_4x I305 (
     .z               (so_l ),
     .a               (net77 ) );
bw_io_ddr_pad_txrx_zctl I309 (
     .vrefcode        ({{4 {vf }} ,vss ,vss ,vss ,vss } ),
     .cbu             ({cbu } ),
     .cbd             ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
     .out             (abvref ),
     .pad             (pad ),
     .vdd_h           (vdd18 ),
     .data            (vdd ),
     .oe              (oe ),
     .odt_enable      (vss ) );
bw_io_ddr_rptr_vddcom I319 (
     .vdd18           (vdd18 ),
     .vdd_com         (vf ) );
endmodule
module bw_io_impctl_ddr_uprcn(oe ,vdd18 ,si_l ,so_l ,pad ,sclk ,cbu ,
     above ,clk ,se ,global_reset_n );

input [8:1]	cbu ;
output		so_l ;
output		pad ;
output		above ;
input		oe ;
input		vdd18 ;
input		si_l ;
input		sclk ;
input		clk ;
input		se ;
input		global_reset_n ;
supply1		vdd ;
supply0		vss ;
 
wire		net76 ;
wire		net77 ;
wire		sclk1 ;
wire		sclk2 ;
wire		scan1 ;
wire		vf ;
wire		net55 ;
wire		net59 ;
wire		net62 ;
wire		abvref ;
wire		net65 ;
wire		net68 ;
 
 
bw_u1_soff_4x I257 (
     .q               (sclk1 ),
     .so              (net76 ),
     .ck              (clk ),
     .d               (sclk ),
     .se              (se ),
     .sd              (net55 ) );
bw_u1_soffr_4x I260 (
     .q               (sclk2 ),
     .so              (scan1 ),
     .ck              (clk ),
     .d               (sclk1 ),
     .se              (se ),
     .sd              (net76 ),
     .r_l             (global_reset_n ) );
bw_u1_soffr_4x I263 (
     .q               (above ),
     .so              (net77 ),
     .ck              (clk ),
     .d               (net62 ),
     .se              (se ),
     .sd              (scan1 ),
     .r_l             (global_reset_n ) );
bw_u1_inv_4x I268 (
     .z               (net59 ),
     .a               (sclk2 ) );
bw_u1_nand2_4x I269 (
     .z               (net62 ),
     .a               (net68 ),
     .b               (net65 ) );
bw_u1_nand2_4x I270 (
     .z               (net65 ),
     .a               (net59 ),
     .b               (above ) );
bw_u1_nand2_4x I271 (
     .z               (net68 ),
     .a               (abvref ),
     .b               (sclk2 ) );
bw_u1_inv_4x I304 (
     .z               (net55 ),
     .a               (si_l ) );
bw_u1_inv_4x I305 (
     .z               (so_l ),
     .a               (net77 ) );
bw_io_ddr_pad_txrx_zctl I309 (
     .vrefcode        ({{4 {vf }} ,vss ,vss ,vss ,vss } ),
     .cbu             ({cbu } ),
     .cbd             ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
     .out             (abvref ),
     .pad             (pad ),
     .vdd_h           (vdd18 ),
     .data            (vdd ),
     .oe              (oe ),
     .odt_enable      (vss ) );
bw_io_ddr_rptr_vddcom I319 (
     .vdd18           (vdd18 ),
     .vdd_com         (vf ) );
endmodule