data/full_repos/permissive/503053625/fpga_projects/SPGD/src/ADC_IN.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/ADC_IN.v:30: Cannot find file containing module: 'ADC_AVERAGE'\n    ADC_AVERAGE  #(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/ADC_AVERAGE\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/ADC_AVERAGE.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src,data/full_repos/permissive/503053625/ADC_AVERAGE.sv\n             ADC_AVERAGE\n             ADC_AVERAGE.v\n             ADC_AVERAGE.sv\n             obj_dir/ADC_AVERAGE\n             obj_dir/ADC_AVERAGE.v\n             obj_dir/ADC_AVERAGE.sv\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/ADC_IN.v:43: Cannot find file containing module: 'FSM'\n    FSM FSM0 (\n    ^~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/ADC_IN.v:52: Cannot find file containing module: 'gen_padder'\n    gen_padder #(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/ADC_IN.v:62: Cannot find file containing module: 'my_mult'\n    my_mult #(\n    ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ADC_IN
#(
    parameter FP_WIDTH = 64,
    parameter ADC_WIDTH = 12,
    parameter NUM_SAMPS = 1023,
    parameter INT_WIDTH = 16
)
(
    input   ADC_CLK,
    input   [ADC_WIDTH      - 1 : 0] ADC_DATA_IN,


    input   enable,
    output  DONE,
    output  [FP_WIDTH    - 1 : 0] ADC_16QM_OUT,
    output REG_WRITE,
    output REG_RST
);
    reg [FP_WIDTH    - 1 : 0] GAIN_MUL_IN = {{16'h0014}, {FP_WIDTH-INT_WIDTH{1'b0}}};

    wire RST;
    wire VALID;
    wire in_REG_RST;
    wire [ADC_WIDTH   - 1 : 0] ADC_AVERAGE_OUT;
    wire [FP_WIDTH   - 1 : 0] ADC_MUL_INPUT;

    assign REG_RST = in_REG_RST;
    assign REG_WRITE = VALID;

    ADC_AVERAGE  #(
        .ADC_WIDTH(ADC_WIDTH),
        .NUM_SAMPS(NUM_SAMPS)
    ) ADC_AVERAGE0 (
        .DATA_IN(ADC_DATA_IN),
        .DATA_OUT(ADC_AVERAGE_OUT),
        .CLK(ADC_CLK),
        .DONE(DONE),
        .EN(!RST)


    );

    FSM FSM0 (
        .done(DONE),
        .enable(enable),
		.adc_clk(ADC_CLK),
        .REG_RST(in_REG_RST),
        .REG_WRITE(VALID),
        .ADC_RST(RST)
    );
    
    gen_padder #(
        .IN_WIDTH(ADC_WIDTH),
        .OUT_WIDTH(FP_WIDTH),
        .L_PAD_WIDTH(4),
        .R_PAD_WIDTH(FP_WIDTH-16)
    ) PAD0 (
        .in(ADC_AVERAGE_OUT),
        .out(ADC_MUL_INPUT)
    );

    my_mult #(
        .DATA_WIDTH(FP_WIDTH),
        .BIT_SHIFT(11)
    ) MULT1 (
        .a(ADC_MUL_INPUT),
        .b(GAIN_MUL_IN),
        .p(ADC_16QM_OUT)
    );
endmodule
module ADC_IN
#(
    parameter FP_WIDTH = 64,
    parameter ADC_WIDTH = 12,
    parameter NUM_SAMPS = 1023,
    parameter INT_WIDTH = 16
)
(
    input   ADC_CLK,
    input   [ADC_WIDTH      - 1 : 0] ADC_DATA_IN,


    input   enable,
    output  DONE,
    output  [FP_WIDTH    - 1 : 0] ADC_16QM_OUT,
    output REG_WRITE,
    output REG_RST
);

    reg [FP_WIDTH    - 1 : 0] GAIN_MUL_IN = {{16'h0014}, {FP_WIDTH-INT_WIDTH{1'b0}}};

    wire RST;
    wire VALID;
    wire in_REG_RST;
    wire [ADC_WIDTH   - 1 : 0] ADC_AVERAGE_OUT;
    wire [FP_WIDTH   - 1 : 0] ADC_MUL_INPUT;

    assign REG_RST = in_REG_RST;
    assign REG_WRITE = VALID;

    ADC_AVERAGE  #(
        .ADC_WIDTH(ADC_WIDTH),
        .NUM_SAMPS(NUM_SAMPS)
    ) ADC_AVERAGE0 (
        .DATA_IN(ADC_DATA_IN),
        .DATA_OUT(ADC_AVERAGE_OUT),
        .CLK(ADC_CLK),
        .DONE(DONE),
        .EN(!RST)


    );

    FSM FSM0 (
        .done(DONE),
        .enable(enable),
		.adc_clk(ADC_CLK),
        .REG_RST(in_REG_RST),
        .REG_WRITE(VALID),
        .ADC_RST(RST)
    );
    
    gen_padder #(
        .IN_WIDTH(ADC_WIDTH),
        .OUT_WIDTH(FP_WIDTH),
        .L_PAD_WIDTH(4),
        .R_PAD_WIDTH(FP_WIDTH-16)
    ) PAD0 (
        .in(ADC_AVERAGE_OUT),
        .out(ADC_MUL_INPUT)
    );

    my_mult #(
        .DATA_WIDTH(FP_WIDTH),
        .BIT_SHIFT(11)
    ) MULT1 (
        .a(ADC_MUL_INPUT),
        .b(GAIN_MUL_IN),
        .p(ADC_16QM_OUT)
    );
endmodule