data/full_repos/permissive/472097485/Chu04/StopWatch_06/DispHexMux.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/DispHexMux.v:34: Operator CASE expects 3 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n                                                                                       : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/DispHexMux.v:34: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                       : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/DispHexMux.v:34: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                       : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module DispHexMux ( input wire clk, reset, input wire [4:0] hex2, hex1, hex0, input wire [2:0] dp_in, input wire [2:0] en_in,
    output wire [2:0] an_out, output wire [7:0] sseg_out );



   localparam N = 18;

   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;
   reg [4:0] hex_in;
   reg dp;
	reg en;
   reg [2:0] an;
   reg [7:0] sseg;



   always @(posedge clk, posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         3'b00:
            begin
               an =  3'b110;
               hex_in = hex0;
               dp = dp_in[0];
					en = en_in[0];
            end
         2'b01:
            begin
               an =  3'b101;
               hex_in = hex1;
               dp = dp_in[1];
					en = en_in[1];
            end
         2'b10:
            begin
               an =  3'b011;
               hex_in = hex2;
               dp = dp_in[2];
					en = en_in[2];
            end
         default:
				begin
					an = 3'b111;
               hex_in = 5'b00000;
               dp = 1'b0;
					en = 1'b0;
				end
       endcase


   always @*
   begin
		if( en )
			case(hex_in)
				5'b00000: sseg[6:0] = 7'b0000001;
				5'b00001: sseg[6:0] = 7'b1001111;
				5'b00010: sseg[6:0] = 7'b0010010;
				5'b00011: sseg[6:0] = 7'b0000110;
				5'b00100: sseg[6:0] = 7'b1001100;
				5'b00101: sseg[6:0] = 7'b0100100;
				5'b00110: sseg[6:0] = 7'b0100000;
				5'b00111: sseg[6:0] = 7'b0001111;
				5'b01000: sseg[6:0] = 7'b0000000;
				5'b01001: sseg[6:0] = 7'b0000100;
				5'b01010: sseg[6:0] = 7'b0001000;
				5'b01011: sseg[6:0] = 7'b1100000;
				5'b01100: sseg[6:0] = 7'b0110001;
				5'b01101: sseg[6:0] = 7'b1000010;
				5'b01110: sseg[6:0] = 7'b0110000;
				5'b01111: sseg[6:0] = 7'b0111000;

				5'b10000: sseg[6:0] = 7'b1000001;
				5'b10001: sseg[6:0] = 7'b1111110;
				5'b10010: sseg[6:0] = 7'b1111111;
				5'b10011: sseg[6:0] = 7'b0001001;
				5'b10100: sseg[6:0] = 7'b1100010;
				5'b10101: sseg[6:0] = 7'b0011100;
				5'b10110: sseg[6:0] = 7'b1111001;
				5'b10111: sseg[6:0] = 7'b1001001;
				default: sseg[6:0] = 7'b1111100;
		  endcase
		else
			sseg[6:0] = 7'b1111111;
     sseg[7] = ~dp;
   end

	assign an_out = an;
	assign sseg_out = sseg;

endmodule
module DispHexMux ( input wire clk, reset, input wire [4:0] hex2, hex1, hex0, input wire [2:0] dp_in, input wire [2:0] en_in,
    output wire [2:0] an_out, output wire [7:0] sseg_out );




   localparam N = 18;

   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;
   reg [4:0] hex_in;
   reg dp;
	reg en;
   reg [2:0] an;
   reg [7:0] sseg;



   always @(posedge clk, posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         3'b00:
            begin
               an =  3'b110;
               hex_in = hex0;
               dp = dp_in[0];
					en = en_in[0];
            end
         2'b01:
            begin
               an =  3'b101;
               hex_in = hex1;
               dp = dp_in[1];
					en = en_in[1];
            end
         2'b10:
            begin
               an =  3'b011;
               hex_in = hex2;
               dp = dp_in[2];
					en = en_in[2];
            end
         default:
				begin
					an = 3'b111;
               hex_in = 5'b00000;
               dp = 1'b0;
					en = 1'b0;
				end
       endcase


   always @*
   begin
		if( en )
			case(hex_in)
				5'b00000: sseg[6:0] = 7'b0000001;
				5'b00001: sseg[6:0] = 7'b1001111;
				5'b00010: sseg[6:0] = 7'b0010010;
				5'b00011: sseg[6:0] = 7'b0000110;
				5'b00100: sseg[6:0] = 7'b1001100;
				5'b00101: sseg[6:0] = 7'b0100100;
				5'b00110: sseg[6:0] = 7'b0100000;
				5'b00111: sseg[6:0] = 7'b0001111;
				5'b01000: sseg[6:0] = 7'b0000000;
				5'b01001: sseg[6:0] = 7'b0000100;
				5'b01010: sseg[6:0] = 7'b0001000;
				5'b01011: sseg[6:0] = 7'b1100000;
				5'b01100: sseg[6:0] = 7'b0110001;
				5'b01101: sseg[6:0] = 7'b1000010;
				5'b01110: sseg[6:0] = 7'b0110000;
				5'b01111: sseg[6:0] = 7'b0111000;

				5'b10000: sseg[6:0] = 7'b1000001;
				5'b10001: sseg[6:0] = 7'b1111110;
				5'b10010: sseg[6:0] = 7'b1111111;
				5'b10011: sseg[6:0] = 7'b0001001;
				5'b10100: sseg[6:0] = 7'b1100010;
				5'b10101: sseg[6:0] = 7'b0011100;
				5'b10110: sseg[6:0] = 7'b1111001;
				5'b10111: sseg[6:0] = 7'b1001001;
				default: sseg[6:0] = 7'b1111100;
		  endcase
		else
			sseg[6:0] = 7'b1111111;
     sseg[7] = ~dp;
   end

	assign an_out = an;
	assign sseg_out = sseg;

endmodule