data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/ifid_pipeline_register.v
data/verilator_xmls/2a10eed6-9698-4113-a875-a1ace6be6119.xml
module ifid_pipeline_register(
    input [31:0] inst_out,
    input clk,
    output reg [31:0] d_inst_out
    );
    
    always @(posedge clk) begin
    d_inst_out <= inst_out;
    end
endmodule
module ifid_pipeline_register(
    input [31:0] inst_out,
    input clk,
    output reg [31:0] d_inst_out
    );

    
    always @(posedge clk) begin
    d_inst_out <= inst_out;
    end
endmodule