data/full_repos/permissive/469669161/verilog/rtl/yazmac_obegi.v
1: b"%Error: data/full_repos/permissive/469669161/verilog/rtl/yazmac_obegi.v:24: Define or directive not defined: '`HY_BIT'\n    input         [`HY_BIT-1:0]     ky1_adres_g                 ,\n                   ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/yazmac_obegi.v:25: Define or directive not defined: '`HY_BIT'\n    input         [`HY_BIT-1:0]     ky2_adres_g                 ,\n                   ^~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/yazmac_obegi.v:26: Define or directive not defined: '`HY_BIT'\n    input         [`HY_BIT-1:0]     hy_adres_g                  ,\n                   ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module yazmac_obegi(
    `ifdef BASYS3
    output        [15:0]            fpga_demo_signal            ,
    `endif

    input                           clk_g                       ,
    input                           rst_g                       ,
    input         [`HY_BIT-1:0]     ky1_adres_g                 ,
    input         [`HY_BIT-1:0]     ky2_adres_g                 ,
    input         [`HY_BIT-1:0]     hy_adres_g                  ,
    input         [31:0]            hy_deger_g                  ,
    input                           yaz_g                       ,
    output reg    [31:0]            ky1_deger_c                 ,
    output reg    [31:0]            ky2_deger_c
    );
    
    reg           [31:0]    y_obek[31:0]                        ;
    
    `ifdef BASYS3

    assign fpga_demo_signal = {y_obek[10][7:0], y_obek[17][7:0]};
    `endif

    always@* begin
        ky1_deger_c            = y_obek[ky1_adres_g]            ;
        ky2_deger_c            = y_obek[ky2_adres_g]            ;
    end
    integer i = 0;
    always@(posedge clk_g) begin
        if (rst_g) begin
            for(i = 0; i < 32; i = i + 1)
                y_obek[i]           <=  0                           ;
        end
        else if(yaz_g) begin
            y_obek[hy_adres_g]  <=  hy_deger_g                  ;
        end
    end
endmodule
module yazmac_obegi(
    `ifdef BASYS3
    output        [15:0]            fpga_demo_signal            ,
    `endif

    input                           clk_g                       ,
    input                           rst_g                       ,
    input         [`HY_BIT-1:0]     ky1_adres_g                 ,
    input         [`HY_BIT-1:0]     ky2_adres_g                 ,
    input         [`HY_BIT-1:0]     hy_adres_g                  ,
    input         [31:0]            hy_deger_g                  ,
    input                           yaz_g                       ,
    output reg    [31:0]            ky1_deger_c                 ,
    output reg    [31:0]            ky2_deger_c
    );

    
    reg           [31:0]    y_obek[31:0]                        ;
    
    `ifdef BASYS3

    assign fpga_demo_signal = {y_obek[10][7:0], y_obek[17][7:0]};
    `endif

    always@* begin
        ky1_deger_c            = y_obek[ky1_adres_g]            ;
        ky2_deger_c            = y_obek[ky2_adres_g]            ;
    end
    integer i = 0;
    always@(posedge clk_g) begin
        if (rst_g) begin
            for(i = 0; i < 32; i = i + 1)
                y_obek[i]           <=  0                           ;
        end
        else if(yaz_g) begin
            y_obek[hy_adres_g]  <=  hy_deger_g                  ;
        end
    end
endmodule