data/full_repos/permissive/516830490/RTL/counter.v
data/verilator_xmls/8f673a9c-3022-47ee-a2ab-cfd1eb351ad3.xml
module counter(
    input i_clk,
    output count_out
    );
    
    reg  temp_cnt = 0;
    always @(posedge i_clk)
           begin
                      begin
              temp_cnt <= ~temp_cnt ;                          
                       end
          end      
			 assign count_out = temp_cnt ;             
endmodule
module counter(
    input i_clk,
    output count_out
    );

    
    reg  temp_cnt = 0;
    always @(posedge i_clk)
           begin
                      begin
              temp_cnt <= ~temp_cnt ;                          
                       end
          end      
			 assign count_out = temp_cnt ;             
endmodule