data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:12: Signal definition not found, creating implicitly: \'clk_idx\'\nfreq_div#(22) M1 (clk,reset,clk_idx);\n                            ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:13: Signal definition not found, creating implicitly: \'clk_row\'\nfreq_div#(12) M2 (clk,reset,clk_row);\n                            ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:163: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                             : ... In instance lab4_2.M4\n  idx_cnt =idx+cnt;    \n              ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:14: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nidx_gen M3 (clk_idx,reset,idx); \n                          ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                                     ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:16: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrom_char M5 (idx_cnt, column_out);\n             ^~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module rom_char(addr, data);
input[6:0]addr;
output[7:0]data;
reg[7:0]data;
always@(addr) begin
case(addr)
7'd0: 	data=8'b00000000;		
7'd1: 	data=8'b00000000;	
7'd2: 	data=8'b00000000; 	
7'd3: 	data=8'b00000000;
7'd4: 	data=8'b00000000;		
7'd5: 	data=8'b00000000;	
7'd6: 	data=8'b00000000;		
7'd7: 	data=8'b00000000;

7'd8: 	data=8'b00111100;		
7'd9: 	data=8'b01000010;	
7'd10: 	data=8'b01000110; 	
7'd11: 	data=8'b01001010;
7'd12: 	data=8'b01010010;	
7'd13: 	data=8'b01100010;
7'd14: 	data=8'b00111100;	
7'd15: 	data=8'b00000000;


7'd16: 	data=8'b00001000;	
7'd17: 	data=8'b00011000;
7'd18: 	data=8'b00001000;	
7'd19: 	data=8'b00001000;
7'd20: 	data=8'b00001000;	
7'd21: 	data=8'b00001000;
7'd22: 	data=8'b00011100;	
7'd23: 	data=8'b00000000;

7'd24: 	data=8'b00111100;	
7'd25: 	data=8'b01000010;
7'd26: 	data=8'b01000010;	
7'd27: 	data=8'b00000100;
7'd28: 	data=8'b00001000;	
7'd29: 	data=8'b00010000;
7'd30: 	data=8'b01111110;	
7'd31: 	data=8'b00000000;

7'd32: 	data=8'b00111100; 	
7'd33: 	data=8'b01000010;
7'd34: 	data=8'b00000010;	
7'd35: 	data=8'b00111100;
7'd36: 	data=8'b00000010;	
7'd37: 	data=8'b01000010;
7'd38: 	data=8'b00111100;	
7'd39: 	data=8'b00000000;

7'd40: 	data=8'b00011100; 	
7'd41: 	data=8'b00100100;
7'd42: 	data=8'b01000100;	
7'd43: 	data=8'b01000100;
7'd44: 	data=8'b01000100;	
7'd45: 	data=8'b01111110;
7'd46: 	data=8'b00000100;	
7'd47: 	data=8'b00000000;

7'd48: 	data=8'b01111110;	
7'd49: 	data=8'b01000000;
7'd50: 	data=8'b01000000;	
7'd51: 	data=8'b01111100;
7'd52: 	data=8'b00000010;	
7'd53: 	data=8'b01000010;
7'd54: 	data=8'b00111100;	
7'd55: 	data=8'b00000000;

7'd56:	data=8'b00111100;
7'd57:	data=8'b01000000;
7'd58:	data=8'b01000000;
7'd59:	data=8'b01111100;
7'd60:	data=8'b01000010;
7'd61:	data=8'b01000010;
7'd62:	data=8'b00111100;
7'd63:	data=8'b00000000;

7'd64:	data=8'b00111100;
7'd65:	data=8'b01000010;
7'd66:	data=8'b01000010;
7'd67:	data=8'b00000010;
7'd68:	data=8'b00000100;
7'd69:	data=8'b00000100;
7'd70:	data=8'b00000100;
7'd71:	data=8'b00000000;

7'd72:	data=8'b00111100;
7'd73:	data=8'b01000010;
7'd74:	data=8'b01000010;
7'd75:	data=8'b00111100;
7'd76:	data=8'b01000010;
7'd77:	data=8'b01000010;
7'd78:	data=8'b00111100;
7'd79:	data=8'b00000000;

7'd80:	data=8'b00111100;
7'd81:	data=8'b01000010;
7'd82:	data=8'b01000010;
7'd83:	data=8'b00111100;
7'd84:	data=8'b00000010;
7'd85:	data=8'b00000010;
7'd86:	data=8'b00000010;
7'd87:	data=8'b00000000;
endcase
end
endmodule
module rom_char(addr, data);

input[6:0]addr;
output[7:0]data;
reg[7:0]data;
always@(addr) begin
case(addr)
7'd0: 	data=8'b00000000;		
7'd1: 	data=8'b00000000;	
7'd2: 	data=8'b00000000; 	
7'd3: 	data=8'b00000000;
7'd4: 	data=8'b00000000;		
7'd5: 	data=8'b00000000;	
7'd6: 	data=8'b00000000;		
7'd7: 	data=8'b00000000;

7'd8: 	data=8'b00111100;		
7'd9: 	data=8'b01000010;	
7'd10: 	data=8'b01000110; 	
7'd11: 	data=8'b01001010;
7'd12: 	data=8'b01010010;	
7'd13: 	data=8'b01100010;
7'd14: 	data=8'b00111100;	
7'd15: 	data=8'b00000000;


7'd16: 	data=8'b00001000;	
7'd17: 	data=8'b00011000;
7'd18: 	data=8'b00001000;	
7'd19: 	data=8'b00001000;
7'd20: 	data=8'b00001000;	
7'd21: 	data=8'b00001000;
7'd22: 	data=8'b00011100;	
7'd23: 	data=8'b00000000;

7'd24: 	data=8'b00111100;	
7'd25: 	data=8'b01000010;
7'd26: 	data=8'b01000010;	
7'd27: 	data=8'b00000100;
7'd28: 	data=8'b00001000;	
7'd29: 	data=8'b00010000;
7'd30: 	data=8'b01111110;	
7'd31: 	data=8'b00000000;

7'd32: 	data=8'b00111100; 	
7'd33: 	data=8'b01000010;
7'd34: 	data=8'b00000010;	
7'd35: 	data=8'b00111100;
7'd36: 	data=8'b00000010;	
7'd37: 	data=8'b01000010;
7'd38: 	data=8'b00111100;	
7'd39: 	data=8'b00000000;

7'd40: 	data=8'b00011100; 	
7'd41: 	data=8'b00100100;
7'd42: 	data=8'b01000100;	
7'd43: 	data=8'b01000100;
7'd44: 	data=8'b01000100;	
7'd45: 	data=8'b01111110;
7'd46: 	data=8'b00000100;	
7'd47: 	data=8'b00000000;

7'd48: 	data=8'b01111110;	
7'd49: 	data=8'b01000000;
7'd50: 	data=8'b01000000;	
7'd51: 	data=8'b01111100;
7'd52: 	data=8'b00000010;	
7'd53: 	data=8'b01000010;
7'd54: 	data=8'b00111100;	
7'd55: 	data=8'b00000000;

7'd56:	data=8'b00111100;
7'd57:	data=8'b01000000;
7'd58:	data=8'b01000000;
7'd59:	data=8'b01111100;
7'd60:	data=8'b01000010;
7'd61:	data=8'b01000010;
7'd62:	data=8'b00111100;
7'd63:	data=8'b00000000;

7'd64:	data=8'b00111100;
7'd65:	data=8'b01000010;
7'd66:	data=8'b01000010;
7'd67:	data=8'b00000010;
7'd68:	data=8'b00000100;
7'd69:	data=8'b00000100;
7'd70:	data=8'b00000100;
7'd71:	data=8'b00000000;

7'd72:	data=8'b00111100;
7'd73:	data=8'b01000010;
7'd74:	data=8'b01000010;
7'd75:	data=8'b00111100;
7'd76:	data=8'b01000010;
7'd77:	data=8'b01000010;
7'd78:	data=8'b00111100;
7'd79:	data=8'b00000000;

7'd80:	data=8'b00111100;
7'd81:	data=8'b01000010;
7'd82:	data=8'b01000010;
7'd83:	data=8'b00111100;
7'd84:	data=8'b00000010;
7'd85:	data=8'b00000010;
7'd86:	data=8'b00000010;
7'd87:	data=8'b00000000;
endcase
end
endmodule