data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/PC.v
data/verilator_xmls/f6668264-bd95-48d3-81d3-c324b50019e3.xml
module PC(
    input clk,
    input PCWE,
    input [31:0] PCIn,
    output reg [31:0] PCOut
    );
    
    initial begin
        PCOut = 500;
    end
    
    always@(posedge clk) begin
        if (PCWE) begin
            PCOut <= PCIn;
        end
    end 
endmodule
module PC(
    input clk,
    input PCWE,
    input [31:0] PCIn,
    output reg [31:0] PCOut
    );

    
    initial begin
        PCOut = 500;
    end
    
    always@(posedge clk) begin
        if (PCWE) begin
            PCOut <= PCIn;
        end
    end 
endmodule