data/full_repos/permissive/511535464/src/ImmProcess.v
data/verilator_xmls/32948048-52a0-42dc-966c-9993f3a1366b.xml
module ImmProcess(ExtOp, LuiOp, Immediate, ImmExtOut, ImmExtShift); 

    input ExtOp;
    input LuiOp;

    input [15:0] Immediate;

    output [31:0] ImmExtOut;
    output [31:0] ImmExtShift;

    wire [31:0] ImmExt;
    
    assign ImmExt = {ExtOp? {16{Immediate[15]}}: 16'h0000, Immediate};
    assign ImmExtShift = ImmExt << 2;
    assign ImmExtOut = LuiOp? {Immediate, 16'h0000}: ImmExt;

endmodule
module ImmProcess(ExtOp, LuiOp, Immediate, ImmExtOut, ImmExtShift);
 

    input ExtOp;
    input LuiOp;

    input [15:0] Immediate;

    output [31:0] ImmExtOut;
    output [31:0] ImmExtShift;

    wire [31:0] ImmExt;
    
    assign ImmExt = {ExtOp? {16{Immediate[15]}}: 16'h0000, Immediate};
    assign ImmExtShift = ImmExt << 2;
    assign ImmExtOut = LuiOp? {Immediate, 16'h0000}: ImmExt;

endmodule