data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:1: Cannot find include file: first_counter.v\n`include "first_counter.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/first_counter.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/first_counter.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/first_counter.v.sv\n             first_counter.v\n             first_counter.v.v\n             first_counter.v.sv\n             obj_dir/first_counter.v\n             obj_dir/first_counter.v.v\n             obj_dir/first_counter.v.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:10: Unsupported or unknown PLI call: $monitor\n  $monitor ("%g\\t %b   %b     %b      %b", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 1;     \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable = 1;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #100 enable = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/first_counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock = ~clock;  \n  ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module first_counter_tb();

reg clock, reset, enable;
wire [3:0] counter_out;


initial begin        
  $display ("time\t clk reset enable counter");	
  $monitor ("%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out);	
  clock = 1;
  reset = 0;
  enable = 0;
  #5 reset = 1;
  #10 reset = 0;
  #10 enable = 1;
  #100 enable = 0;
  #5 $finish;
end


always begin
  #5 clock = ~clock;
end


first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule
module first_counter_tb();


reg clock, reset, enable;
wire [3:0] counter_out;


initial begin        
  $display ("time\t clk reset enable counter");	
  $monitor ("%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out);	
  clock = 1;
  reset = 0;
  enable = 0;
  #5 reset = 1;
  #10 reset = 0;
  #10 enable = 1;
  #100 enable = 0;
  #5 $finish;
end


always begin
  #5 clock = ~clock;
end


first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule