data/full_repos/permissive/441359809/src/yosys/examples/smtbmc/demo1.v
data/verilator_xmls/5695c72b-2254-4292-8577-b22bd1432bea.xml
module demo1(input clk, input addtwo, output iseven);
	reg [3:0] cnt;
	wire [3:0] next_cnt;

	inc inc_inst (addtwo, iseven, cnt, next_cnt);

	always @(posedge clk)
		cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt;

`ifdef FORMAL
	assert property (cnt != 15);
	initial assume (!cnt[2]);
`endif
endmodule
module demo1(input clk, input addtwo, output iseven);

	reg [3:0] cnt;
	wire [3:0] next_cnt;

	inc inc_inst (addtwo, iseven, cnt, next_cnt);

	always @(posedge clk)
		cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt;

`ifdef FORMAL
	assert property (cnt != 15);
	initial assume (!cnt[2]);
`endif
endmodule