data/full_repos/permissive/527249789/src/InstBuffer.v
1: b'%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:7: Define or directive not defined: \'`InstBus\'\n    input   [`InstBus]              inst_i,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstBus]              inst_i,\n                     ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:8: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]          pc_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:14: Define or directive not defined: \'`InstBus\'\n    output  reg[`InstBus]           inst_o,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:15: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]       pc_o,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output                          ibuffer_full\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:20: Define or directive not defined: \'`InstBus\'\nreg[`InstBus] FIFO_data[`InstBufferSize:0];\n    ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstBus] FIFO_data[`InstBufferSize:0];\n            ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:20: Define or directive not defined: \'`InstBufferSize\'\nreg[`InstBus] FIFO_data[`InstBufferSize:0];\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:21: Define or directive not defined: \'`InstAddrBus\'\nreg[`InstAddrBus] FIFO_addr[`InstBufferSize:0];\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstAddrBus] FIFO_addr[`InstBufferSize:0];\n                ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:21: Define or directive not defined: \'`InstBufferSize\'\nreg[`InstAddrBus] FIFO_addr[`InstBufferSize:0];\n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:22: Define or directive not defined: \'`InstBufferSize\'\nreg[`InstBufferSize:0] FIFO_valid;\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:22: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg[`InstBufferSize:0] FIFO_valid;\n                   ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:23: Define or directive not defined: \'`InstBufferAddrBus\'\nreg[`InstBufferAddrBus] head;\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstBufferAddrBus] head;\n                      ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:24: Define or directive not defined: \'`InstBufferAddrBus\'\nreg[`InstBufferAddrBus] tail;\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstBufferAddrBus] tail;\n                      ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:25: Define or directive not defined: \'`InstBus\'\nreg[`InstBus] req_addr;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstBus] req_addr;\n            ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:28: Define or directive not defined: \'`SignedInstBufferAddrBus\'\nwire[`SignedInstBufferAddrBus] head_negative = ~{1\'b0, head} + 1;\n     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`SignedInstBufferAddrBus] head_negative = ~{1\'b0, head} + 1;\n                             ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:29: Define or directive not defined: \'`SignedInstBufferAddrBus\'\nwire[`SignedInstBufferAddrBus] tail_minus_head = {1\'b0, tail} + head_negative;\n     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`SignedInstBufferAddrBus] tail_minus_head = {1\'b0, tail} + head_negative;\n                             ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:30: Define or directive not defined: \'`SignedInstBufferAddrBus\'\nwire[`SignedInstBufferAddrBus] tail_minus_head_plus = tail_minus_head + `InstBufferSize + 1;\n     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`SignedInstBufferAddrBus] tail_minus_head_plus = tail_minus_head + `InstBufferSize + 1;\n                             ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:30: Define or directive not defined: \'`InstBufferSize\'\nwire[`SignedInstBufferAddrBus] tail_minus_head_plus = tail_minus_head + `InstBufferSize + 1;\n                                                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:31: Define or directive not defined: \'`InstBufferAddrBus\'\nwire[`InstBufferAddrBus] ibuffer_num = (tail_minus_head[6] == 0) ?\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstBufferAddrBus] ibuffer_num = (tail_minus_head[6] == 0) ?\n                       ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:34: Define or directive not defined: \'`InstBufferSize\'\nassign ibuffer_full = (ibuffer_num == `InstBufferSize);\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:36: Define or directive not defined: \'`InstBufferAddrBus\'\nwire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);\n                       ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:36: Define or directive not defined: \'`InstBufferSize\'\nwire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:36: Define or directive not defined: \'`ZeroInstBufferAddr\'\nwire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);\n                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:37: Define or directive not defined: \'`InstBufferAddrBus\'\nwire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);\n                       ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:37: Define or directive not defined: \'`InstBufferSize\'\nwire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:37: Define or directive not defined: \'`ZeroInstBufferAddr\'\nwire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);\n                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:38: Define or directive not defined: \'`NoStop\'\nwire send_inst_to_id_flag = ((stall_i == `NoStop) && (ibuffer_empty == 1\'b0) && (branch_flag == `NoBranch) && (FIFO_valid[new_head] == 1\'b1));\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:38: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire send_inst_to_id_flag = ((stall_i == `NoStop) && (ibuffer_empty == 1\'b0) && (branch_flag == `NoBranch) && (FIFO_valid[new_head] == 1\'b1));\n                                                ^\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:38: Define or directive not defined: \'`NoBranch\'\nwire send_inst_to_id_flag = ((stall_i == `NoStop) && (ibuffer_empty == 1\'b0) && (branch_flag == `NoBranch) && (FIFO_valid[new_head] == 1\'b1));\n                                                                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:41: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable)                                           head <= `ZeroInstBufferAddr;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:41: Define or directive not defined: \'`ZeroInstBufferAddr\'\n    if (resetn == `RstEnable)                                           head <= `ZeroInstBufferAddr;\n                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:42: Define or directive not defined: \'`FlushEnable\'\n    else if (flush == `FlushEnable)                                     head <= `ZeroInstBufferAddr;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:42: Define or directive not defined: \'`ZeroInstBufferAddr\'\n    else if (flush == `FlushEnable)                                     head <= `ZeroInstBufferAddr;\n                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:43: Define or directive not defined: \'`ZeroInstBufferAddr\'\n    else if (flush_for_exception)                                       head <= `ZeroInstBufferAddr;\n                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:44: Define or directive not defined: \'`Branch\'\n    else if (branch_flag == `Branch)                                    head <= `ZeroInstBufferAddr;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:44: Define or directive not defined: \'`ZeroInstBufferAddr\'\n    else if (branch_flag == `Branch)                                    head <= `ZeroInstBufferAddr;\n                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/InstBuffer.v:45: Define or directive not defined: \'`ZeroInstBufferAddr\'\n    else if (flush_for_branch)                                          head <= `ZeroInstBufferAddr;\n                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module InstBuffer(
    input                           clk,
    input                           resetn,
    input                           flush,
    input   [`InstBus]              inst_i,
    input   [`InstAddrBus]          pc_i,
    input                           inst_data_ok,
    input                           inst_req_success,
    input                           stall_i,
    input                           branch_flag,

    output  reg[`InstBus]           inst_o,
    output  reg[`InstAddrBus]       pc_o,
    output  reg                     do_inst_flag,
    output                          ibuffer_full
);

reg[`InstBus] FIFO_data[`InstBufferSize:0];
reg[`InstAddrBus] FIFO_addr[`InstBufferSize:0];
reg[`InstBufferSize:0] FIFO_valid;
reg[`InstBufferAddrBus] head;
reg[`InstBufferAddrBus] tail;
reg[`InstBus] req_addr;
reg flush_for_branch;
reg flush_for_exception;
wire[`SignedInstBufferAddrBus] head_negative = ~{1'b0, head} + 1;
wire[`SignedInstBufferAddrBus] tail_minus_head = {1'b0, tail} + head_negative;
wire[`SignedInstBufferAddrBus] tail_minus_head_plus = tail_minus_head + `InstBufferSize + 1;
wire[`InstBufferAddrBus] ibuffer_num = (tail_minus_head[6] == 0) ?
                                       (tail_minus_head[5:0]) :
                                       (tail_minus_head_plus[5:0]);
assign ibuffer_full = (ibuffer_num == `InstBufferSize);
assign ibuffer_empty = (ibuffer_num == 0);
wire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);
wire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);
wire send_inst_to_id_flag = ((stall_i == `NoStop) && (ibuffer_empty == 1'b0) && (branch_flag == `NoBranch) && (FIFO_valid[new_head] == 1'b1));

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           head <= `ZeroInstBufferAddr;
    else if (flush == `FlushEnable)                                     head <= `ZeroInstBufferAddr;
    else if (flush_for_exception)                                       head <= `ZeroInstBufferAddr;
    else if (branch_flag == `Branch)                                    head <= `ZeroInstBufferAddr;
    else if (flush_for_branch)                                          head <= `ZeroInstBufferAddr;
    else if (send_inst_to_id_flag)                                      head <= new_head;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           tail <= `ZeroInstBufferAddr;
    else if (flush == `FlushEnable)                                     tail <= `ZeroInstBufferAddr;
    else if (flush_for_exception)                                       tail <= `ZeroInstBufferAddr;
    else if (branch_flag == `Branch)                                    tail <= `ZeroInstBufferAddr;
    else if (flush_for_branch)                                          tail <= `ZeroInstBufferAddr;
    else if (inst_data_ok == `DataOK)                                   tail <= new_tail;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush == `FlushEnable)                                     FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush_for_exception)                                       FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (branch_flag == `Branch)                                    FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush_for_branch)                                          FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (inst_data_ok == `DataOK)                                   FIFO_valid[new_tail] <= `True_v;
    else if (send_inst_to_id_flag)                                      FIFO_valid[new_head] <= `False_v;
end

always @(posedge clk) begin
    if (inst_data_ok == `DataOK)                                        FIFO_addr[new_tail] <= req_addr;
end

always @(posedge clk) begin
    if (inst_data_ok == `DataOK)                                        FIFO_data[new_tail] <= inst_i;
end

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end else if (flush == `FlushEnable || flush_for_exception) begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end else if (send_inst_to_id_flag) begin
        inst_o <= FIFO_data[new_head];
        pc_o <= FIFO_addr[new_head];
        do_inst_flag <= 1'b1;
    end else if ((do_inst_flag == 1'b1) && (stall_i == `Stop)) begin

        inst_o <= inst_o;
        pc_o <= pc_o;
        do_inst_flag <= do_inst_flag;
    end else begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           req_addr <= `ZeroWord;
    else if (inst_req_success)                                          req_addr <= pc_i;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           flush_for_exception <= `FlushDisable;
    else if (flush == `FlushEnable)                                     flush_for_exception <= `FlushEnable;
    else if (inst_req_success)                                          flush_for_exception <= `FlushDisable;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           flush_for_branch <= `FlushDisable;
    else if (branch_flag)                                               flush_for_branch <= `FlushEnable;
    else if (inst_req_success)                                          flush_for_branch <= `FlushDisable;
end

endmodule
module InstBuffer(
    input                           clk,
    input                           resetn,
    input                           flush,
    input   [`InstBus]              inst_i,
    input   [`InstAddrBus]          pc_i,
    input                           inst_data_ok,
    input                           inst_req_success,
    input                           stall_i,
    input                           branch_flag,

    output  reg[`InstBus]           inst_o,
    output  reg[`InstAddrBus]       pc_o,
    output  reg                     do_inst_flag,
    output                          ibuffer_full
);


reg[`InstBus] FIFO_data[`InstBufferSize:0];
reg[`InstAddrBus] FIFO_addr[`InstBufferSize:0];
reg[`InstBufferSize:0] FIFO_valid;
reg[`InstBufferAddrBus] head;
reg[`InstBufferAddrBus] tail;
reg[`InstBus] req_addr;
reg flush_for_branch;
reg flush_for_exception;
wire[`SignedInstBufferAddrBus] head_negative = ~{1'b0, head} + 1;
wire[`SignedInstBufferAddrBus] tail_minus_head = {1'b0, tail} + head_negative;
wire[`SignedInstBufferAddrBus] tail_minus_head_plus = tail_minus_head + `InstBufferSize + 1;
wire[`InstBufferAddrBus] ibuffer_num = (tail_minus_head[6] == 0) ?
                                       (tail_minus_head[5:0]) :
                                       (tail_minus_head_plus[5:0]);
assign ibuffer_full = (ibuffer_num == `InstBufferSize);
assign ibuffer_empty = (ibuffer_num == 0);
wire[`InstBufferAddrBus] new_tail = (tail == `InstBufferSize) ? `ZeroInstBufferAddr : (tail + 1);
wire[`InstBufferAddrBus] new_head = (head == `InstBufferSize) ? `ZeroInstBufferAddr : (head + 1);
wire send_inst_to_id_flag = ((stall_i == `NoStop) && (ibuffer_empty == 1'b0) && (branch_flag == `NoBranch) && (FIFO_valid[new_head] == 1'b1));

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           head <= `ZeroInstBufferAddr;
    else if (flush == `FlushEnable)                                     head <= `ZeroInstBufferAddr;
    else if (flush_for_exception)                                       head <= `ZeroInstBufferAddr;
    else if (branch_flag == `Branch)                                    head <= `ZeroInstBufferAddr;
    else if (flush_for_branch)                                          head <= `ZeroInstBufferAddr;
    else if (send_inst_to_id_flag)                                      head <= new_head;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           tail <= `ZeroInstBufferAddr;
    else if (flush == `FlushEnable)                                     tail <= `ZeroInstBufferAddr;
    else if (flush_for_exception)                                       tail <= `ZeroInstBufferAddr;
    else if (branch_flag == `Branch)                                    tail <= `ZeroInstBufferAddr;
    else if (flush_for_branch)                                          tail <= `ZeroInstBufferAddr;
    else if (inst_data_ok == `DataOK)                                   tail <= new_tail;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush == `FlushEnable)                                     FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush_for_exception)                                       FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (branch_flag == `Branch)                                    FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (flush_for_branch)                                          FIFO_valid <= `InstBufferSizePlus1'd0;
    else if (inst_data_ok == `DataOK)                                   FIFO_valid[new_tail] <= `True_v;
    else if (send_inst_to_id_flag)                                      FIFO_valid[new_head] <= `False_v;
end

always @(posedge clk) begin
    if (inst_data_ok == `DataOK)                                        FIFO_addr[new_tail] <= req_addr;
end

always @(posedge clk) begin
    if (inst_data_ok == `DataOK)                                        FIFO_data[new_tail] <= inst_i;
end

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end else if (flush == `FlushEnable || flush_for_exception) begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end else if (send_inst_to_id_flag) begin
        inst_o <= FIFO_data[new_head];
        pc_o <= FIFO_addr[new_head];
        do_inst_flag <= 1'b1;
    end else if ((do_inst_flag == 1'b1) && (stall_i == `Stop)) begin

        inst_o <= inst_o;
        pc_o <= pc_o;
        do_inst_flag <= do_inst_flag;
    end else begin
        inst_o <= `ZeroWord;
        pc_o <= `ZeroWord;
        do_inst_flag <= 1'b0;
    end
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           req_addr <= `ZeroWord;
    else if (inst_req_success)                                          req_addr <= pc_i;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           flush_for_exception <= `FlushDisable;
    else if (flush == `FlushEnable)                                     flush_for_exception <= `FlushEnable;
    else if (inst_req_success)                                          flush_for_exception <= `FlushDisable;
end

always @(posedge clk) begin
    if (resetn == `RstEnable)                                           flush_for_branch <= `FlushDisable;
    else if (branch_flag)                                               flush_for_branch <= `FlushEnable;
    else if (inst_req_success)                                          flush_for_branch <= `FlushDisable;
end

endmodule