data/full_repos/permissive/488739248/rtl/ttl/ttl_74273_sync.v
data/verilator_xmls/f621ed42-0a04-4f9a-905a-63ecb5a12704.xml
module ttl_74273_sync
(
    input wire RESETn,
    input wire CLRn,
    input wire Clk,
    input wire Cen,
    input wire [7:0] D,
    output wire [7:0] Q
);

    reg [7:0] Q_current;
    reg last_cen;
    
    always @(posedge Clk)
    begin
        
        if (!RESETn) begin
            Q_current <= 0;
            last_cen <= 1'b1;
        end
        else 
        begin
            last_cen <= Cen;
            if (!CLRn) Q_current <= 0;
            else if(Cen && !last_cen) Q_current <= D;
        end
    end

    assign Q = Q_current;
endmodule
module ttl_74273_sync
(
    input wire RESETn,
    input wire CLRn,
    input wire Clk,
    input wire Cen,
    input wire [7:0] D,
    output wire [7:0] Q
);


    reg [7:0] Q_current;
    reg last_cen;
    
    always @(posedge Clk)
    begin
        
        if (!RESETn) begin
            Q_current <= 0;
            last_cen <= 1'b1;
        end
        else 
        begin
            last_cen <= Cen;
            if (!CLRn) Q_current <= 0;
            else if(Cen && !last_cen) Q_current <= D;
        end
    end

    assign Q = Q_current;
endmodule