data/full_repos/permissive/458134463/Modules/control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0001;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b0111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/control_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20 Opcode = 4\'b1001;\n^\n%Error: data/full_repos/permissive/458134463/Modules/control_tb.v:29: Unsupported or unknown PLI call: $monitor\n$monitor("Time: %3d | Opcode: %4b\\nRegDst: %1b | ALUSrc: %1b | MemtoReg: %1b | RegWrite: %1b | MemRead: %1b | MemWrite: %1b | Branch: %1b | ALUOp: %4b\\n", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_tb();

reg [3:0] Opcode;

wire [2:0] ALUOp;
wire RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch;


control c(Opcode, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp);


initial begin
		  Opcode = 4'b0000;
#`DELAY Opcode = 4'b0001;
#`DELAY Opcode = 4'b0010;
#`DELAY Opcode = 4'b0011;
#`DELAY Opcode = 4'b0100;
#`DELAY Opcode = 4'b0101;
#`DELAY Opcode = 4'b0110;
#`DELAY Opcode = 4'b0111;
#`DELAY Opcode = 4'b1000;
#`DELAY Opcode = 4'b1001;

end


initial begin
$monitor("Time: %3d | Opcode: %4b\nRegDst: %1b | ALUSrc: %1b | MemtoReg: %1b | RegWrite: %1b | MemRead: %1b | MemWrite: %1b | Branch: %1b | ALUOp: %4b\n", 
			$time, Opcode,
			RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp);
end

endmodule
module control_tb();


reg [3:0] Opcode;

wire [2:0] ALUOp;
wire RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch;


control c(Opcode, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp);


initial begin
		  Opcode = 4'b0000;
#`DELAY Opcode = 4'b0001;
#`DELAY Opcode = 4'b0010;
#`DELAY Opcode = 4'b0011;
#`DELAY Opcode = 4'b0100;
#`DELAY Opcode = 4'b0101;
#`DELAY Opcode = 4'b0110;
#`DELAY Opcode = 4'b0111;
#`DELAY Opcode = 4'b1000;
#`DELAY Opcode = 4'b1001;

end


initial begin
$monitor("Time: %3d | Opcode: %4b\nRegDst: %1b | ALUSrc: %1b | MemtoReg: %1b | RegWrite: %1b | MemRead: %1b | MemWrite: %1b | Branch: %1b | ALUOp: %4b\n", 
			$time, Opcode,
			RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp);
end

endmodule