data/full_repos/permissive/445929378/mult_32_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_32_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #10 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_32_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_32_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/445929378/mult_32_tb.v:43: Cannot find file containing module: \'mult_32_pipeline_2\'\n mult_32_pipeline_2 uut(\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_32_pipeline_2\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_32_pipeline_2.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_32_pipeline_2.sv\n             mult_32_pipeline_2\n             mult_32_pipeline_2.v\n             mult_32_pipeline_2.sv\n             obj_dir/mult_32_pipeline_2\n             obj_dir/mult_32_pipeline_2.v\n             obj_dir/mult_32_pipeline_2.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mult_32_pipeline_2_tb;


	reg clk;
	reg rst;
	reg [15:0] input_a_tdata;
	reg input_a_tvalid;
	reg [15:0] input_b_tdata;
	reg input_b_tvalid;
	reg output_tready;


	wire input_a_tready;
	wire input_b_tready;
	wire [31:0] output_tdata;
	wire output_tvalid;


	mult_32_pipeline_2 uut(
		.clk(clk), 
		.rst(rst), 
		.input_a_tdata(input_a_tdata), 
		.input_a_tvalid(input_a_tvalid), 
		.input_a_tready(input_a_tready), 
		.input_b_tdata(input_b_tdata), 
		.input_b_tvalid(input_b_tvalid), 
		.input_b_tready(input_b_tready), 
		.output_tdata(output_tdata), 
		.output_tvalid(output_tvalid), 
		.output_tready(output_tready)
	);
	
	initial begin
		clk = 0;
		forever begin
			#10 clk = ~clk;
		end
	end

	initial begin

		rst = 0;
		input_a_tdata = 16'd690;
		input_a_tvalid = 1;
		input_b_tdata = 16'd2137;
		input_b_tvalid = 1;
		output_tready = 0;
		#5;
		output_tready = 1;	

		

		#100;
        


	end
      
endmodule
module mult_32_pipeline_2_tb;



	reg clk;
	reg rst;
	reg [15:0] input_a_tdata;
	reg input_a_tvalid;
	reg [15:0] input_b_tdata;
	reg input_b_tvalid;
	reg output_tready;


	wire input_a_tready;
	wire input_b_tready;
	wire [31:0] output_tdata;
	wire output_tvalid;


	mult_32_pipeline_2 uut(
		.clk(clk), 
		.rst(rst), 
		.input_a_tdata(input_a_tdata), 
		.input_a_tvalid(input_a_tvalid), 
		.input_a_tready(input_a_tready), 
		.input_b_tdata(input_b_tdata), 
		.input_b_tvalid(input_b_tvalid), 
		.input_b_tready(input_b_tready), 
		.output_tdata(output_tdata), 
		.output_tvalid(output_tvalid), 
		.output_tready(output_tready)
	);
	
	initial begin
		clk = 0;
		forever begin
			#10 clk = ~clk;
		end
	end

	initial begin

		rst = 0;
		input_a_tdata = 16'd690;
		input_a_tvalid = 1;
		input_b_tdata = 16'd2137;
		input_b_tvalid = 1;
		output_tready = 0;
		#5;
		output_tready = 1;	

		

		#100;
        


	end
      
endmodule