data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv
1: b'%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv:2: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm,data/full_repos/permissive/489980666/uvm_macros.svh\n             data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm,data/full_repos/permissive/489980666/uvm_macros.svh.v\n             data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm,data/full_repos/permissive/489980666/uvm_macros.svh.sv\n             uvm_macros.svh\n             uvm_macros.svh.v\n             uvm_macros.svh.sv\n             obj_dir/uvm_macros.svh\n             obj_dir/uvm_macros.svh.v\n             obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n       ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 axi4_if.clk = ~axi4_if.clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv:21: syntax error, unexpected \'@\'\n    repeat (1) @(posedge axi4_if.clk);\n               ^\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/tb.sv:26: syntax error, unexpected \'#\'\n    uvm_config_db#(virtual dut_if)::set( null, "uvm_test_top", "vif", axi4_if);\n                 ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module tb;
  logic        clk;
  logic        rst;

  dut_if axi4_if();
  axi4_slave dut(.dif(axi4_if));

  initial begin
    axi4_if.clk=0;
  end

  always begin
    #10 axi4_if.clk = ~axi4_if.clk;
  end

  initial begin
    axi4_if.rst=0;
    repeat (1) @(posedge axi4_if.clk);
    axi4_if.rst=1;
  end

  initial begin
    uvm_config_db#(virtual dut_if)::set( null, "uvm_test_top", "vif", axi4_if);
    run_test();
  end

endmodule
module tb;

  logic        clk;
  logic        rst;

  dut_if axi4_if();
  axi4_slave dut(.dif(axi4_if));

  initial begin
    axi4_if.clk=0;
  end

  always begin
    #10 axi4_if.clk = ~axi4_if.clk;
  end

  initial begin
    axi4_if.rst=0;
    repeat (1) @(posedge axi4_if.clk);
    axi4_if.rst=1;
  end

  initial begin
    uvm_config_db#(virtual dut_if)::set( null, "uvm_test_top", "vif", axi4_if);
    run_test();
  end

endmodule