data/full_repos/permissive/468612001/Week04/fulladder_4bit/fulladder_4bit.v
data/verilator_xmls/69bdae6e-bdf6-4671-ae76-afda1c98ee9c.xml
module fulladder_1bit(a, b, cin, sum, cout);
    input a, b, cin;
    output sum, cout;
    wire s1, c1, c2;
    
    xor g1(s1, a, b);
    and g2(c1, a, b);
    and g3(c2, s1, cin);
    xor g4(sum, s1, cin);
    xor g5(cout, c1, c2);
    
endmodule
module fulladder_1bit(a, b, cin, sum, cout);

    input a, b, cin;
    output sum, cout;
    wire s1, c1, c2;
    
    xor g1(s1, a, b);
    and g2(c1, a, b);
    and g3(c2, s1, cin);
    xor g4(sum, s1, cin);
    xor g5(cout, c1, c2);
    
endmodule