data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:332: Signal definition not found, creating implicitly: \'jtag_c0_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdi_o\'\n        assign jtag_c0_tdo = (tunnel_sel0 && jtag_c0_tdo_en_i) ? jtag_c0_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:333: Signal definition not found, creating implicitly: \'jtag_c1_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c1_tdo = (tunnel_sel1 && jtag_c1_tdo_en_i) ? jtag_c1_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:334: Signal definition not found, creating implicitly: \'jtag_c2_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c2_tdo = (tunnel_sel2 && jtag_c2_tdo_en_i) ? jtag_c2_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:335: Signal definition not found, creating implicitly: \'jtag_c3_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c3_tdo = (tunnel_sel3 && jtag_c3_tdo_en_i) ? jtag_c3_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:336: Signal definition not found, creating implicitly: \'jtag_c4_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c4_tdo = (tunnel_sel4 && jtag_c4_tdo_en_i) ? jtag_c4_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:337: Signal definition not found, creating implicitly: \'jtag_c5_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c5_tdo = (tunnel_sel5 && jtag_c5_tdo_en_i) ? jtag_c5_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:338: Signal definition not found, creating implicitly: \'jtag_c6_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c6_tdo = (tunnel_sel6 && jtag_c6_tdo_en_i) ? jtag_c6_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:339: Signal definition not found, creating implicitly: \'jtag_c7_tdo\'\n                                                                                                           : ... Suggested alternative: \'jtag_c0_tdo\'\n        assign jtag_c7_tdo = (tunnel_sel7 && jtag_c7_tdo_en_i) ? jtag_c7_tdo_i : 1\'b1;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:90: Cannot find file containing module: \'BSCANE2\'\n        BSCANE2 #( \n        ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog,data/full_repos/permissive/463204869/BSCANE2\n             data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog,data/full_repos/permissive/463204869/BSCANE2.v\n             data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog,data/full_repos/permissive/463204869/BSCANE2.sv\n             BSCANE2\n             BSCANE2.v\n             BSCANE2.sv\n             obj_dir/BSCANE2\n             obj_dir/BSCANE2.v\n             obj_dir/BSCANE2.sv\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:152: Cannot find file containing module: \'BSCANE2\'\n        BSCANE2 #( \n        ^~~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:263: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_0 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:269: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_1 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:275: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_2 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:281: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_3 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:287: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_4 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:293: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_5 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:299: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_6 ( \n        ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/jtag/source/rtl/verilog/jtag_tunnel_mc8.v:305: Cannot find file containing module: \'BUFGCE\'\n        BUFGCE clkbuf_7 ( \n        ^~~~~~\n%Error: Exiting due to 10 error(s), 8 warning(s)\n'
module jtag_tunnel_mc8( 
        output wire jtag_c0_tck_o, 
        output wire jtag_c0_tms_o, 
        output wire jtag_c0_tdi_o, 
        input  wire jtag_c0_tdo_i,
        input  wire jtag_c0_tdo_en_i,
        output wire jtag_c0_sel_o,

        output wire jtag_c1_tck_o, 
        output wire jtag_c1_tms_o, 
        output wire jtag_c1_tdi_o, 
        input  wire jtag_c1_tdo_i,
        input  wire jtag_c1_tdo_en_i,
        output wire jtag_c1_sel_o,

        output wire jtag_c2_tck_o, 
        output wire jtag_c2_tms_o, 
        output wire jtag_c2_tdi_o, 
        input  wire jtag_c2_tdo_i,
        input  wire jtag_c2_tdo_en_i,
        output wire jtag_c2_sel_o,

        output wire jtag_c3_tck_o, 
        output wire jtag_c3_tms_o, 
        output wire jtag_c3_tdi_o, 
        input  wire jtag_c3_tdo_i,
        input  wire jtag_c3_tdo_en_i,
        output wire jtag_c3_sel_o,
       
	output wire jtag_c4_tck_o, 
        output wire jtag_c4_tms_o, 
        output wire jtag_c4_tdi_o, 
        input  wire jtag_c4_tdo_i,
        input  wire jtag_c4_tdo_en_i,
        output wire jtag_c4_sel_o,
	
        output wire jtag_c5_tck_o, 
        output wire jtag_c5_tms_o, 
        output wire jtag_c5_tdi_o, 
        input  wire jtag_c5_tdo_i,
        input  wire jtag_c5_tdo_en_i,
        output wire jtag_c5_sel_o,

        output wire jtag_c6_tck_o, 
        output wire jtag_c6_tms_o, 
        output wire jtag_c6_tdi_o, 
        input  wire jtag_c6_tdo_i,
        input  wire jtag_c6_tdo_en_i,
        output wire jtag_c6_sel_o,
        
	output wire jtag_c7_tck_o, 
        output wire jtag_c7_tms_o, 
        output wire jtag_c7_tdi_o, 
        input  wire jtag_c7_tdo_i,
        input  wire jtag_c7_tdo_en_i,
        output wire jtag_c7_sel_o
 
); 
        
      parameter JTAG_TUNNEL_USER_CHAIN=4;
      parameter JTAG_CONFIG_USER_CHAIN=3;
      
        wire [3:0] debug_o;





        reg [7:0] tunnel_addr;
        reg [7:0] tunnel_addr_shiftreg;



        wire cfg_capture;
        wire cfg_reset;
        wire cfg_drck; 
        wire cfg_sel; 
        wire cfg_shift; 
        wire cfg_update;
        wire cfg_tck;
        wire cfg_tdi;
        wire cfg_tdo;

        BSCANE2 #( 
          .JTAG_CHAIN(JTAG_CONFIG_USER_CHAIN)
        ) 
        BSCANE2_config_inst ( 
          .CAPTURE(cfg_capture),
          .DRCK(cfg_drck),

            .RESET(cfg_reset),
            .RUNTEST(),
            .SEL(cfg_sel),
            .SHIFT(cfg_shift),
            .TCK(cfg_tck),
            .TDI(cfg_tdi),
            .TMS(),
            .UPDATE(cfg_update),
            .TDO(cfg_tdo)
          ); 
        
        assign cfg_tdo = tunnel_addr_shiftreg[0];

        always @ (posedge cfg_drck) begin
                if (cfg_reset) begin
                        tunnel_addr_shiftreg <= 8'd0;        
                end else begin
                         if (cfg_shift) begin
                                tunnel_addr_shiftreg <= {cfg_tdi, tunnel_addr_shiftreg[7:1]};
                        end else if (cfg_capture) begin
                                tunnel_addr_shiftreg <= tunnel_addr;
                        end                    
                end
        end

        always @ (negedge cfg_tck) begin
                tunnel_addr <= tunnel_addr;
                if (cfg_sel && cfg_update) begin
                        tunnel_addr <= tunnel_addr_shiftreg;
                end
        end








        reg  jtag_tms;
        wire jtag_tdi;
        wire jtag_tdo;
        wire jtag_tdo_en;

        wire TCK;  
        wire SEL; 
        wire SHIFT; 
        wire TDI;
        wire TDO; 

        reg [6:0] shiftreg_cnt; 
        reg [7:0] counter_neg; 
        reg [7:0] counter_pos; 
        reg         TDI_REG; 
        
        BSCANE2 #( 
          .JTAG_CHAIN(JTAG_TUNNEL_USER_CHAIN)
        ) 
        BSCANE2_inst ( 
          .CAPTURE(),
          .DRCK(),

            .RESET(),
            .RUNTEST(),
            .SEL(SEL),
            .SHIFT(SHIFT),
            .TCK(TCK),
            .TDI(TDI),
            .TMS(),
            .UPDATE(),
            .TDO(TDO)
          ); 
      
        
        assign jtag_tdi = TDI; 
        assign TDO = jtag_tdo; 
        
        always@(*) begin 
                if (counter_neg == 8'h04) begin 
                        jtag_tms = TDI_REG; 
                end else if (counter_neg == 8'h05) begin 
                        jtag_tms = 1'b1; 
                end else if ((counter_neg == (8'h08 + shiftreg_cnt)) || (counter_neg == (8'h08 + shiftreg_cnt - 8'h01))) begin 
                        jtag_tms = 1'b1; 
                end else begin 
                        jtag_tms = 1'b0; 
                end 
        end 
        
        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        shiftreg_cnt <= 7'b0000000; 
                end else if ((counter_pos >= 8'h01) && (counter_pos <= 8'h07))  begin 
                        shiftreg_cnt <= {{TDI, shiftreg_cnt[6:1]}}; 
                end else begin 
                        shiftreg_cnt <= shiftreg_cnt; 
                end 
        end 
        
        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        TDI_REG <= 1'b0; 
                end else if (counter_pos == 8'h00) begin 
                        TDI_REG <= ~TDI; 
                end else begin 
                        TDI_REG <= TDI_REG; 
                end 
        end 
        
        always@(negedge TCK) begin 
                if (~SHIFT) begin 
                        counter_neg <= 8'b00000000; 
                end else begin 
                        counter_neg <= counter_neg + 1; 
                end 
        end 

        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        counter_pos <= 8'b00000000; 
                end else begin 
                        counter_pos <= counter_pos + 1; 
                end 
        end





        wire [2:0] tunnel_sel;
        reg [7:0] tunnel_sel_oh;
        assign tunnel_sel = tunnel_addr[2:0];

        always @* begin
                case (tunnel_sel) 
                       3'b000: begin tunnel_sel_oh = 8'b00000001; end
                       3'b001: begin tunnel_sel_oh = 8'b00000010; end
                       3'b010: begin tunnel_sel_oh = 8'b00000100; end
                       3'b011: begin tunnel_sel_oh = 8'b00001000; end
                       3'b100: begin tunnel_sel_oh = 8'b00010000; end
                       3'b101: begin tunnel_sel_oh = 8'b00100000; end
                       3'b110: begin tunnel_sel_oh = 8'b01000000; end
                       3'b111: begin tunnel_sel_oh = 8'b10000000; end
                endcase
        end

        wire tunnel_sel0;
        wire tunnel_sel1;
        wire tunnel_sel2;
        wire tunnel_sel3;
        wire tunnel_sel4;
        wire tunnel_sel5;
        wire tunnel_sel6;
        wire tunnel_sel7;


        assign tunnel_sel0 = tunnel_sel_oh[0];
        assign tunnel_sel1 = tunnel_sel_oh[1];
        assign tunnel_sel2 = tunnel_sel_oh[2];
        assign tunnel_sel3 = tunnel_sel_oh[3];
        assign tunnel_sel4 = tunnel_sel_oh[4];
        assign tunnel_sel5 = tunnel_sel_oh[5];
        assign tunnel_sel6 = tunnel_sel_oh[6];
        assign tunnel_sel7 = tunnel_sel_oh[7];


        BUFGCE clkbuf_0 ( 
          .O(jtag_c0_tck_o),
          .CE(tunnel_sel0 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_1 ( 
          .O(jtag_c1_tck_o),
          .CE(tunnel_sel1 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_2 ( 
          .O(jtag_c2_tck_o),
          .CE(tunnel_sel2 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_3 ( 
          .O(jtag_c3_tck_o),
          .CE(tunnel_sel3 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_4 ( 
          .O(jtag_c4_tck_o),
          .CE(tunnel_sel4 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_5 ( 
          .O(jtag_c5_tck_o),
          .CE(tunnel_sel5 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_6 ( 
          .O(jtag_c6_tck_o),
          .CE(tunnel_sel6 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_7 ( 
          .O(jtag_c7_tck_o),
          .CE(tunnel_sel7 & SEL),
          .I(TCK)
        ); 
        

        assign jtag_c0_tms_o = (tunnel_sel0) ? jtag_tms : 1'b1;
        assign jtag_c1_tms_o = (tunnel_sel1) ? jtag_tms : 1'b1;
        assign jtag_c2_tms_o = (tunnel_sel2) ? jtag_tms : 1'b1;
        assign jtag_c3_tms_o = (tunnel_sel3) ? jtag_tms : 1'b1;
        assign jtag_c4_tms_o = (tunnel_sel4) ? jtag_tms : 1'b1;
        assign jtag_c5_tms_o = (tunnel_sel5) ? jtag_tms : 1'b1;
        assign jtag_c6_tms_o = (tunnel_sel6) ? jtag_tms : 1'b1;
        assign jtag_c7_tms_o = (tunnel_sel7) ? jtag_tms : 1'b1;


        assign jtag_c0_tdi_o = (tunnel_sel0) ? jtag_tdi : 1'b1;
        assign jtag_c1_tdi_o = (tunnel_sel1) ? jtag_tdi : 1'b1;
        assign jtag_c2_tdi_o = (tunnel_sel2) ? jtag_tdi : 1'b1;
        assign jtag_c3_tdi_o = (tunnel_sel3) ? jtag_tdi : 1'b1;
        assign jtag_c4_tdi_o = (tunnel_sel4) ? jtag_tdi : 1'b1;
        assign jtag_c5_tdi_o = (tunnel_sel5) ? jtag_tdi : 1'b1;
        assign jtag_c6_tdi_o = (tunnel_sel6) ? jtag_tdi : 1'b1;
        assign jtag_c7_tdi_o = (tunnel_sel7) ? jtag_tdi : 1'b1;


        assign jtag_c0_tdo = (tunnel_sel0 && jtag_c0_tdo_en_i) ? jtag_c0_tdo_i : 1'b1;
        assign jtag_c1_tdo = (tunnel_sel1 && jtag_c1_tdo_en_i) ? jtag_c1_tdo_i : 1'b1;
        assign jtag_c2_tdo = (tunnel_sel2 && jtag_c2_tdo_en_i) ? jtag_c2_tdo_i : 1'b1;
        assign jtag_c3_tdo = (tunnel_sel3 && jtag_c3_tdo_en_i) ? jtag_c3_tdo_i : 1'b1;
        assign jtag_c4_tdo = (tunnel_sel4 && jtag_c4_tdo_en_i) ? jtag_c4_tdo_i : 1'b1;
        assign jtag_c5_tdo = (tunnel_sel5 && jtag_c5_tdo_en_i) ? jtag_c5_tdo_i : 1'b1;
        assign jtag_c6_tdo = (tunnel_sel6 && jtag_c6_tdo_en_i) ? jtag_c6_tdo_i : 1'b1;
        assign jtag_c7_tdo = (tunnel_sel7 && jtag_c7_tdo_en_i) ? jtag_c7_tdo_i : 1'b1;

        assign jtag_tdo = jtag_c0_tdo & jtag_c1_tdo & jtag_c2_tdo & jtag_c3_tdo & jtag_c4_tdo & jtag_c5_tdo & jtag_c6_tdo & jtag_c7_tdo;


        assign jtag_c0_sel_o = tunnel_sel0;
        assign jtag_c1_sel_o = tunnel_sel1;
        assign jtag_c2_sel_o = tunnel_sel2;
        assign jtag_c3_sel_o = SEL;

endmodule
module jtag_tunnel_mc8( 
        output wire jtag_c0_tck_o, 
        output wire jtag_c0_tms_o, 
        output wire jtag_c0_tdi_o, 
        input  wire jtag_c0_tdo_i,
        input  wire jtag_c0_tdo_en_i,
        output wire jtag_c0_sel_o,

        output wire jtag_c1_tck_o, 
        output wire jtag_c1_tms_o, 
        output wire jtag_c1_tdi_o, 
        input  wire jtag_c1_tdo_i,
        input  wire jtag_c1_tdo_en_i,
        output wire jtag_c1_sel_o,

        output wire jtag_c2_tck_o, 
        output wire jtag_c2_tms_o, 
        output wire jtag_c2_tdi_o, 
        input  wire jtag_c2_tdo_i,
        input  wire jtag_c2_tdo_en_i,
        output wire jtag_c2_sel_o,

        output wire jtag_c3_tck_o, 
        output wire jtag_c3_tms_o, 
        output wire jtag_c3_tdi_o, 
        input  wire jtag_c3_tdo_i,
        input  wire jtag_c3_tdo_en_i,
        output wire jtag_c3_sel_o,
       
	output wire jtag_c4_tck_o, 
        output wire jtag_c4_tms_o, 
        output wire jtag_c4_tdi_o, 
        input  wire jtag_c4_tdo_i,
        input  wire jtag_c4_tdo_en_i,
        output wire jtag_c4_sel_o,
	
        output wire jtag_c5_tck_o, 
        output wire jtag_c5_tms_o, 
        output wire jtag_c5_tdi_o, 
        input  wire jtag_c5_tdo_i,
        input  wire jtag_c5_tdo_en_i,
        output wire jtag_c5_sel_o,

        output wire jtag_c6_tck_o, 
        output wire jtag_c6_tms_o, 
        output wire jtag_c6_tdi_o, 
        input  wire jtag_c6_tdo_i,
        input  wire jtag_c6_tdo_en_i,
        output wire jtag_c6_sel_o,
        
	output wire jtag_c7_tck_o, 
        output wire jtag_c7_tms_o, 
        output wire jtag_c7_tdi_o, 
        input  wire jtag_c7_tdo_i,
        input  wire jtag_c7_tdo_en_i,
        output wire jtag_c7_sel_o
 
);
 
        
      parameter JTAG_TUNNEL_USER_CHAIN=4;
      parameter JTAG_CONFIG_USER_CHAIN=3;
      
        wire [3:0] debug_o;





        reg [7:0] tunnel_addr;
        reg [7:0] tunnel_addr_shiftreg;



        wire cfg_capture;
        wire cfg_reset;
        wire cfg_drck; 
        wire cfg_sel; 
        wire cfg_shift; 
        wire cfg_update;
        wire cfg_tck;
        wire cfg_tdi;
        wire cfg_tdo;

        BSCANE2 #( 
          .JTAG_CHAIN(JTAG_CONFIG_USER_CHAIN)
        ) 
        BSCANE2_config_inst ( 
          .CAPTURE(cfg_capture),
          .DRCK(cfg_drck),

            .RESET(cfg_reset),
            .RUNTEST(),
            .SEL(cfg_sel),
            .SHIFT(cfg_shift),
            .TCK(cfg_tck),
            .TDI(cfg_tdi),
            .TMS(),
            .UPDATE(cfg_update),
            .TDO(cfg_tdo)
          ); 
        
        assign cfg_tdo = tunnel_addr_shiftreg[0];

        always @ (posedge cfg_drck) begin
                if (cfg_reset) begin
                        tunnel_addr_shiftreg <= 8'd0;        
                end else begin
                         if (cfg_shift) begin
                                tunnel_addr_shiftreg <= {cfg_tdi, tunnel_addr_shiftreg[7:1]};
                        end else if (cfg_capture) begin
                                tunnel_addr_shiftreg <= tunnel_addr;
                        end                    
                end
        end

        always @ (negedge cfg_tck) begin
                tunnel_addr <= tunnel_addr;
                if (cfg_sel && cfg_update) begin
                        tunnel_addr <= tunnel_addr_shiftreg;
                end
        end








        reg  jtag_tms;
        wire jtag_tdi;
        wire jtag_tdo;
        wire jtag_tdo_en;

        wire TCK;  
        wire SEL; 
        wire SHIFT; 
        wire TDI;
        wire TDO; 

        reg [6:0] shiftreg_cnt; 
        reg [7:0] counter_neg; 
        reg [7:0] counter_pos; 
        reg         TDI_REG; 
        
        BSCANE2 #( 
          .JTAG_CHAIN(JTAG_TUNNEL_USER_CHAIN)
        ) 
        BSCANE2_inst ( 
          .CAPTURE(),
          .DRCK(),

            .RESET(),
            .RUNTEST(),
            .SEL(SEL),
            .SHIFT(SHIFT),
            .TCK(TCK),
            .TDI(TDI),
            .TMS(),
            .UPDATE(),
            .TDO(TDO)
          ); 
      
        
        assign jtag_tdi = TDI; 
        assign TDO = jtag_tdo; 
        
        always@(*) begin 
                if (counter_neg == 8'h04) begin 
                        jtag_tms = TDI_REG; 
                end else if (counter_neg == 8'h05) begin 
                        jtag_tms = 1'b1; 
                end else if ((counter_neg == (8'h08 + shiftreg_cnt)) || (counter_neg == (8'h08 + shiftreg_cnt - 8'h01))) begin 
                        jtag_tms = 1'b1; 
                end else begin 
                        jtag_tms = 1'b0; 
                end 
        end 
        
        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        shiftreg_cnt <= 7'b0000000; 
                end else if ((counter_pos >= 8'h01) && (counter_pos <= 8'h07))  begin 
                        shiftreg_cnt <= {{TDI, shiftreg_cnt[6:1]}}; 
                end else begin 
                        shiftreg_cnt <= shiftreg_cnt; 
                end 
        end 
        
        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        TDI_REG <= 1'b0; 
                end else if (counter_pos == 8'h00) begin 
                        TDI_REG <= ~TDI; 
                end else begin 
                        TDI_REG <= TDI_REG; 
                end 
        end 
        
        always@(negedge TCK) begin 
                if (~SHIFT) begin 
                        counter_neg <= 8'b00000000; 
                end else begin 
                        counter_neg <= counter_neg + 1; 
                end 
        end 

        always@(posedge TCK) begin 
                if (~SHIFT) begin 
                        counter_pos <= 8'b00000000; 
                end else begin 
                        counter_pos <= counter_pos + 1; 
                end 
        end





        wire [2:0] tunnel_sel;
        reg [7:0] tunnel_sel_oh;
        assign tunnel_sel = tunnel_addr[2:0];

        always @* begin
                case (tunnel_sel) 
                       3'b000: begin tunnel_sel_oh = 8'b00000001; end
                       3'b001: begin tunnel_sel_oh = 8'b00000010; end
                       3'b010: begin tunnel_sel_oh = 8'b00000100; end
                       3'b011: begin tunnel_sel_oh = 8'b00001000; end
                       3'b100: begin tunnel_sel_oh = 8'b00010000; end
                       3'b101: begin tunnel_sel_oh = 8'b00100000; end
                       3'b110: begin tunnel_sel_oh = 8'b01000000; end
                       3'b111: begin tunnel_sel_oh = 8'b10000000; end
                endcase
        end

        wire tunnel_sel0;
        wire tunnel_sel1;
        wire tunnel_sel2;
        wire tunnel_sel3;
        wire tunnel_sel4;
        wire tunnel_sel5;
        wire tunnel_sel6;
        wire tunnel_sel7;


        assign tunnel_sel0 = tunnel_sel_oh[0];
        assign tunnel_sel1 = tunnel_sel_oh[1];
        assign tunnel_sel2 = tunnel_sel_oh[2];
        assign tunnel_sel3 = tunnel_sel_oh[3];
        assign tunnel_sel4 = tunnel_sel_oh[4];
        assign tunnel_sel5 = tunnel_sel_oh[5];
        assign tunnel_sel6 = tunnel_sel_oh[6];
        assign tunnel_sel7 = tunnel_sel_oh[7];


        BUFGCE clkbuf_0 ( 
          .O(jtag_c0_tck_o),
          .CE(tunnel_sel0 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_1 ( 
          .O(jtag_c1_tck_o),
          .CE(tunnel_sel1 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_2 ( 
          .O(jtag_c2_tck_o),
          .CE(tunnel_sel2 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_3 ( 
          .O(jtag_c3_tck_o),
          .CE(tunnel_sel3 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_4 ( 
          .O(jtag_c4_tck_o),
          .CE(tunnel_sel4 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_5 ( 
          .O(jtag_c5_tck_o),
          .CE(tunnel_sel5 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_6 ( 
          .O(jtag_c6_tck_o),
          .CE(tunnel_sel6 & SEL),
          .I(TCK)
        ); 

        BUFGCE clkbuf_7 ( 
          .O(jtag_c7_tck_o),
          .CE(tunnel_sel7 & SEL),
          .I(TCK)
        ); 
        

        assign jtag_c0_tms_o = (tunnel_sel0) ? jtag_tms : 1'b1;
        assign jtag_c1_tms_o = (tunnel_sel1) ? jtag_tms : 1'b1;
        assign jtag_c2_tms_o = (tunnel_sel2) ? jtag_tms : 1'b1;
        assign jtag_c3_tms_o = (tunnel_sel3) ? jtag_tms : 1'b1;
        assign jtag_c4_tms_o = (tunnel_sel4) ? jtag_tms : 1'b1;
        assign jtag_c5_tms_o = (tunnel_sel5) ? jtag_tms : 1'b1;
        assign jtag_c6_tms_o = (tunnel_sel6) ? jtag_tms : 1'b1;
        assign jtag_c7_tms_o = (tunnel_sel7) ? jtag_tms : 1'b1;


        assign jtag_c0_tdi_o = (tunnel_sel0) ? jtag_tdi : 1'b1;
        assign jtag_c1_tdi_o = (tunnel_sel1) ? jtag_tdi : 1'b1;
        assign jtag_c2_tdi_o = (tunnel_sel2) ? jtag_tdi : 1'b1;
        assign jtag_c3_tdi_o = (tunnel_sel3) ? jtag_tdi : 1'b1;
        assign jtag_c4_tdi_o = (tunnel_sel4) ? jtag_tdi : 1'b1;
        assign jtag_c5_tdi_o = (tunnel_sel5) ? jtag_tdi : 1'b1;
        assign jtag_c6_tdi_o = (tunnel_sel6) ? jtag_tdi : 1'b1;
        assign jtag_c7_tdi_o = (tunnel_sel7) ? jtag_tdi : 1'b1;


        assign jtag_c0_tdo = (tunnel_sel0 && jtag_c0_tdo_en_i) ? jtag_c0_tdo_i : 1'b1;
        assign jtag_c1_tdo = (tunnel_sel1 && jtag_c1_tdo_en_i) ? jtag_c1_tdo_i : 1'b1;
        assign jtag_c2_tdo = (tunnel_sel2 && jtag_c2_tdo_en_i) ? jtag_c2_tdo_i : 1'b1;
        assign jtag_c3_tdo = (tunnel_sel3 && jtag_c3_tdo_en_i) ? jtag_c3_tdo_i : 1'b1;
        assign jtag_c4_tdo = (tunnel_sel4 && jtag_c4_tdo_en_i) ? jtag_c4_tdo_i : 1'b1;
        assign jtag_c5_tdo = (tunnel_sel5 && jtag_c5_tdo_en_i) ? jtag_c5_tdo_i : 1'b1;
        assign jtag_c6_tdo = (tunnel_sel6 && jtag_c6_tdo_en_i) ? jtag_c6_tdo_i : 1'b1;
        assign jtag_c7_tdo = (tunnel_sel7 && jtag_c7_tdo_en_i) ? jtag_c7_tdo_i : 1'b1;

        assign jtag_tdo = jtag_c0_tdo & jtag_c1_tdo & jtag_c2_tdo & jtag_c3_tdo & jtag_c4_tdo & jtag_c5_tdo & jtag_c6_tdo & jtag_c7_tdo;


        assign jtag_c0_sel_o = tunnel_sel0;
        assign jtag_c1_sel_o = tunnel_sel1;
        assign jtag_c2_sel_o = tunnel_sel2;
        assign jtag_c3_sel_o = SEL;

endmodule