data/full_repos/permissive/513628330/Gateware/src/polyosc.v
1: b"%Error: data/full_repos/permissive/513628330/Gateware/src/polyosc.v:45: Cannot find file containing module: 'SB_PLL40_2F_PAD'\n SB_PLL40_2F_PAD #(\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/SB_PLL40_2F_PAD\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/SB_PLL40_2F_PAD.v\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/SB_PLL40_2F_PAD.sv\n             SB_PLL40_2F_PAD\n             SB_PLL40_2F_PAD.v\n             SB_PLL40_2F_PAD.sv\n             obj_dir/SB_PLL40_2F_PAD\n             obj_dir/SB_PLL40_2F_PAD.v\n             obj_dir/SB_PLL40_2F_PAD.sv\n%Error: data/full_repos/permissive/513628330/Gateware/src/polyosc.v:115: Cannot find file containing module: 'spi_slave'\n spi_slave\n ^~~~~~~~~\n%Error: data/full_repos/permissive/513628330/Gateware/src/polyosc.v:156: Cannot find file containing module: 'system'\n system u_riscv(\n ^~~~~~\n%Error: data/full_repos/permissive/513628330/Gateware/src/polyosc.v:209: Cannot find file containing module: 'SB_RGBA_DRV'\n SB_RGBA_DRV #(\n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module polyosc(

	input clk_12MHz,
	

	input rx,
	output tx,
	

	inout	spi0_mosi,
			spi0_miso,
			spi0_sclk,
			spi0_cs0,
	output	spi0_nwp,
			spi0_nhld,
			

    output RGB0, RGB1, RGB2,
	

	input SPI_CSL,
	input SPI_MOSI,
	output SPI_MISO,
	input SPI_SCLK,
	

	output PMOD1_1, PMOD1_3, PMOD1_5,
	output PMOD3_1, PMOD3_3, PMOD3_5
);

	parameter DESIGN_ID = 32'hC1EF0000;





	wire clk, clk24, pll_lock;
	SB_PLL40_2F_PAD #(
		.DIVR(4'b0000),
		.DIVF(7'b0111111),
		.DIVQ(3'b100),
		.FILTER_RANGE(3'b001),
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.FDA_FEEDBACK(4'b0000),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.FDA_RELATIVE(4'b0000),
		.SHIFTREG_DIV_MODE(2'b00),
		.PLLOUT_SELECT_PORTA("GENCLK_HALF"),
		.PLLOUT_SELECT_PORTB("GENCLK"),
		.ENABLE_ICEGATE_PORTA(1'b0),
		.ENABLE_ICEGATE_PORTB(1'b0)
	)
	pll_inst (
		.PACKAGEPIN(clk_12MHz),
		.PLLOUTCOREA(),
		.PLLOUTGLOBALA(clk24),
		.PLLOUTCOREB(),
		.PLLOUTGLOBALB(clk),
		.EXTFEEDBACK(),
		.DYNAMICDELAY(8'h00),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.LATCHINPUTVALUE(),
		.LOCK(pll_lock),
		.SDI(),
		.SDO(),
		.SCLK()
	);
	



	reg [9:0] reset_cnt;
	reg reset, reset24;    
	always @(posedge clk or negedge pll_lock)
	begin
		if(!pll_lock)
		begin
			reset_cnt <= 10'h000;
			reset <= 1'b1;
		end
		else
		begin
			if(reset_cnt != 10'h3ff)
			begin
				reset_cnt <= reset_cnt + 10'h001;
				reset <= 1'b1;
			end
			else
				reset <= 1'b0;
		end
	end
	
	always @(posedge clk24 or negedge pll_lock)
		if(!pll_lock)
			reset24 <= 1'b1;
		else
			reset24 <= reset;
	



	wire [31:0] wdat;
	reg [31:0] rdat;
	wire [6:0] addr;
	wire re, we;
	spi_slave
		uspi(.clk(clk), .reset(reset),
			.spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
			.spimiso(SPI_MISO), .spicsl(SPI_CSL),
			.we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
		



	reg [31:0] gpio_torisc;
	always @(posedge clk)
	begin
		if(reset)
		begin
			gpio_torisc <= 32'd0;
		end
		else if(we)
		begin
			case(addr)
				7'h02: gpio_torisc <= wdat;
			endcase
		end
	end




	wire [31:0] gpio_fromrisc;
	always @(*)
	begin
		case(addr)
			7'h00: rdat = DESIGN_ID;
			7'h01: rdat = gpio_fromrisc;
			7'h02: rdat = gpio_torisc;
			default: rdat = 32'd0;
		endcase
	end
	

	wire [1:0] pdm;
	wire [7:0] red, grn, blu;
	system u_riscv(
		.clk24(clk24),
		.reset(reset24),
		.RX(rx),
		.TX(tx),
		.spi0_mosi(spi0_mosi),
		.spi0_miso(spi0_miso),
		.spi0_sclk(spi0_sclk),
		.spi0_cs0(spi0_cs0),
		.pdm(pdm),
		.gp_in0(gpio_torisc),
		.gp_in1(32'h0),
		.gp_in2(32'h0),
		.gp_in3(32'h0),
		.gp_out0(gpio_fromrisc),
		.gp_out1({red,grn,blu}),
		.gp_out2(),
		.gp_out3()
	);
	

	assign spi0_nwp = 1'b1;
	assign spi0_nhld = 1'b1;
		

	assign PMOD1_1 = pdm[0];
	assign PMOD1_3 = pdm[1];
	assign PMOD1_5 = 1'b1;
	assign PMOD3_1 = pdm[0];
	assign PMOD3_3 = pdm[1];
	assign PMOD3_5 = 1'b1;
	



	reg [7:0] pwm_cnt;
	reg r_pwm, g_pwm, b_pwm;
	always @(posedge clk)
		if(reset)
		begin
			pwm_cnt <= 8'd0;
		end
		else
		begin
			pwm_cnt <= pwm_cnt + 1;
			r_pwm <= pwm_cnt < red;
			g_pwm <= pwm_cnt < grn;
			b_pwm <= pwm_cnt < blu;
		end
	



	SB_RGBA_DRV #(
		.CURRENT_MODE("0b1"),
		.RGB0_CURRENT("0b000001"),
		.RGB1_CURRENT("0b000001"),
		.RGB2_CURRENT("0b000001")
	) RGBA_DRIVER (
		.CURREN(1'b1),
		.RGBLEDEN(1'b1),
		.RGB0PWM(r_pwm),
		.RGB1PWM(g_pwm),
		.RGB2PWM(b_pwm),
		.RGB0(RGB0),
		.RGB1(RGB1),
		.RGB2(RGB2)
	);
endmodule
module polyosc(

	input clk_12MHz,
	

	input rx,
	output tx,
	

	inout	spi0_mosi,
			spi0_miso,
			spi0_sclk,
			spi0_cs0,
	output	spi0_nwp,
			spi0_nhld,
			

    output RGB0, RGB1, RGB2,
	

	input SPI_CSL,
	input SPI_MOSI,
	output SPI_MISO,
	input SPI_SCLK,
	

	output PMOD1_1, PMOD1_3, PMOD1_5,
	output PMOD3_1, PMOD3_3, PMOD3_5
);


	parameter DESIGN_ID = 32'hC1EF0000;





	wire clk, clk24, pll_lock;
	SB_PLL40_2F_PAD #(
		.DIVR(4'b0000),
		.DIVF(7'b0111111),
		.DIVQ(3'b100),
		.FILTER_RANGE(3'b001),
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.FDA_FEEDBACK(4'b0000),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.FDA_RELATIVE(4'b0000),
		.SHIFTREG_DIV_MODE(2'b00),
		.PLLOUT_SELECT_PORTA("GENCLK_HALF"),
		.PLLOUT_SELECT_PORTB("GENCLK"),
		.ENABLE_ICEGATE_PORTA(1'b0),
		.ENABLE_ICEGATE_PORTB(1'b0)
	)
	pll_inst (
		.PACKAGEPIN(clk_12MHz),
		.PLLOUTCOREA(),
		.PLLOUTGLOBALA(clk24),
		.PLLOUTCOREB(),
		.PLLOUTGLOBALB(clk),
		.EXTFEEDBACK(),
		.DYNAMICDELAY(8'h00),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.LATCHINPUTVALUE(),
		.LOCK(pll_lock),
		.SDI(),
		.SDO(),
		.SCLK()
	);
	



	reg [9:0] reset_cnt;
	reg reset, reset24;    
	always @(posedge clk or negedge pll_lock)
	begin
		if(!pll_lock)
		begin
			reset_cnt <= 10'h000;
			reset <= 1'b1;
		end
		else
		begin
			if(reset_cnt != 10'h3ff)
			begin
				reset_cnt <= reset_cnt + 10'h001;
				reset <= 1'b1;
			end
			else
				reset <= 1'b0;
		end
	end
	
	always @(posedge clk24 or negedge pll_lock)
		if(!pll_lock)
			reset24 <= 1'b1;
		else
			reset24 <= reset;
	



	wire [31:0] wdat;
	reg [31:0] rdat;
	wire [6:0] addr;
	wire re, we;
	spi_slave
		uspi(.clk(clk), .reset(reset),
			.spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
			.spimiso(SPI_MISO), .spicsl(SPI_CSL),
			.we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
		



	reg [31:0] gpio_torisc;
	always @(posedge clk)
	begin
		if(reset)
		begin
			gpio_torisc <= 32'd0;
		end
		else if(we)
		begin
			case(addr)
				7'h02: gpio_torisc <= wdat;
			endcase
		end
	end




	wire [31:0] gpio_fromrisc;
	always @(*)
	begin
		case(addr)
			7'h00: rdat = DESIGN_ID;
			7'h01: rdat = gpio_fromrisc;
			7'h02: rdat = gpio_torisc;
			default: rdat = 32'd0;
		endcase
	end
	

	wire [1:0] pdm;
	wire [7:0] red, grn, blu;
	system u_riscv(
		.clk24(clk24),
		.reset(reset24),
		.RX(rx),
		.TX(tx),
		.spi0_mosi(spi0_mosi),
		.spi0_miso(spi0_miso),
		.spi0_sclk(spi0_sclk),
		.spi0_cs0(spi0_cs0),
		.pdm(pdm),
		.gp_in0(gpio_torisc),
		.gp_in1(32'h0),
		.gp_in2(32'h0),
		.gp_in3(32'h0),
		.gp_out0(gpio_fromrisc),
		.gp_out1({red,grn,blu}),
		.gp_out2(),
		.gp_out3()
	);
	

	assign spi0_nwp = 1'b1;
	assign spi0_nhld = 1'b1;
		

	assign PMOD1_1 = pdm[0];
	assign PMOD1_3 = pdm[1];
	assign PMOD1_5 = 1'b1;
	assign PMOD3_1 = pdm[0];
	assign PMOD3_3 = pdm[1];
	assign PMOD3_5 = 1'b1;
	



	reg [7:0] pwm_cnt;
	reg r_pwm, g_pwm, b_pwm;
	always @(posedge clk)
		if(reset)
		begin
			pwm_cnt <= 8'd0;
		end
		else
		begin
			pwm_cnt <= pwm_cnt + 1;
			r_pwm <= pwm_cnt < red;
			g_pwm <= pwm_cnt < grn;
			b_pwm <= pwm_cnt < blu;
		end
	



	SB_RGBA_DRV #(
		.CURRENT_MODE("0b1"),
		.RGB0_CURRENT("0b000001"),
		.RGB1_CURRENT("0b000001"),
		.RGB2_CURRENT("0b000001")
	) RGBA_DRIVER (
		.CURREN(1'b1),
		.RGBLEDEN(1'b1),
		.RGB0PWM(r_pwm),
		.RGB1PWM(g_pwm),
		.RGB2PWM(b_pwm),
		.RGB0(RGB0),
		.RGB1(RGB1),
		.RGB2(RGB2)
	);
endmodule