data/full_repos/permissive/458134463/Modules/adder_32bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_32bit_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'b10000000000000000000000000000000; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_32bit_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'h12345678; \n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/adder_32bit_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20 value1   = 32\'h7FFFFFFF; \n^\n%Error: data/full_repos/permissive/458134463/Modules/adder_32bit_tb.v:36: Unsupported or unknown PLI call: $monitor\n$monitor("\\nTime  : %1d\\nvalue1: %32b (%8h) (%11d)\\nvalue2: %32b (%8h) (%11d)\\nsum   : %32b (%8h) (%11d) \\ncarry_in : %1b carry_out: %1b  overflow: %1b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_32bit_tb();

reg signed [31:0] value1;
reg signed [31:0] value2;
reg carry_in;

wire signed [31:0] sum;
wire carry_out;
wire overflow;


adder_32bit add(value1, value2, sum, carry_out, carry_in, overflow);


initial begin
        value1   = 32'd100000; 
	     value2   = 32'd200000; 
	     carry_in = 1'b1;
	 
#`DELAY value1   = 32'b10000000000000000000000000000000; 
	     value2   = 32'b01111111111111111111111111111111; 
	     carry_in = 1'b1;
 
#`DELAY value1   = 32'h12345678; 
	     value2   = 32'h87654321; 
	     carry_in = 1'b0;

#`DELAY value1   = 32'h7FFFFFFF; 
	     value2   = 32'h00000001; 
	     carry_in = 1'b0;

end

initial begin
$monitor("\nTime  : %1d\nvalue1: %32b (%8h) (%11d)\nvalue2: %32b (%8h) (%11d)\nsum   : %32b (%8h) (%11d) \ncarry_in : %1b carry_out: %1b  overflow: %1b", 
			$time, 
			value1, value1, value1, 
			value2, value2, value2,
			sum, sum, sum,
			carry_in, 
			carry_out,
			overflow);
end

endmodule
module adder_32bit_tb();


reg signed [31:0] value1;
reg signed [31:0] value2;
reg carry_in;

wire signed [31:0] sum;
wire carry_out;
wire overflow;


adder_32bit add(value1, value2, sum, carry_out, carry_in, overflow);


initial begin
        value1   = 32'd100000; 
	     value2   = 32'd200000; 
	     carry_in = 1'b1;
	 
#`DELAY value1   = 32'b10000000000000000000000000000000; 
	     value2   = 32'b01111111111111111111111111111111; 
	     carry_in = 1'b1;
 
#`DELAY value1   = 32'h12345678; 
	     value2   = 32'h87654321; 
	     carry_in = 1'b0;

#`DELAY value1   = 32'h7FFFFFFF; 
	     value2   = 32'h00000001; 
	     carry_in = 1'b0;

end

initial begin
$monitor("\nTime  : %1d\nvalue1: %32b (%8h) (%11d)\nvalue2: %32b (%8h) (%11d)\nsum   : %32b (%8h) (%11d) \ncarry_in : %1b carry_out: %1b  overflow: %1b", 
			$time, 
			value1, value1, value1, 
			value2, value2, value2,
			sum, sum, sum,
			carry_in, 
			carry_out,
			overflow);
end

endmodule