data/full_repos/permissive/502764644/dpram/dpram.sv
1: b"%Error: data/full_repos/permissive/502764644/dpram/dpram.sv:21: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/502764644/dpram/dpram.sv:29: syntax error, unexpected always\nalways @(posedge clk_a) begin\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module dpram #(parameter dWidth = 8, parameter aWidth = 10)
(

    input  logic              clk_a,
    input  logic              we_a,
    input  logic [aWidth-1:0] addr_a,
    input  logic [dWidth-1:0] d_a,
    output logic [dWidth-1:0] q_a,


    input  logic              clk_b,
    input  logic              we_b,
    input  logic [aWidth-1:0] addr_b,
    input  logic [dWidth-1:0] d_b,
    output logic [dWidth-1:0] q_b,
);


logic [dWidth-1:0] ram [2 ** aWidth-1:0];
logic [aWidth-1:0] addr_a_reg;
logic [aWidth-1:0] addr_b_reg;


always @(posedge clk_a) begin
    q_a <= ram[addr_a];
    if (we_a) begin
        ram[addr_a] <= d_a;
        q_a <= d_a;
    end
end


always @(posedge clk_b) begin
    q_b <= ram[addr_b];
    if (we_b) begin
        ram[addr_b] <= d_b;
        q_b <= d_b;
    end
end

endmodule
module dpram #(parameter dWidth = 8, parameter aWidth = 10)
(

    input  logic              clk_a,
    input  logic              we_a,
    input  logic [aWidth-1:0] addr_a,
    input  logic [dWidth-1:0] d_a,
    output logic [dWidth-1:0] q_a,


    input  logic              clk_b,
    input  logic              we_b,
    input  logic [aWidth-1:0] addr_b,
    input  logic [dWidth-1:0] d_b,
    output logic [dWidth-1:0] q_b,
);



logic [dWidth-1:0] ram [2 ** aWidth-1:0];
logic [aWidth-1:0] addr_a_reg;
logic [aWidth-1:0] addr_b_reg;


always @(posedge clk_a) begin
    q_a <= ram[addr_a];
    if (we_a) begin
        ram[addr_a] <= d_a;
        q_a <= d_a;
    end
end


always @(posedge clk_b) begin
    q_b <= ram[addr_b];
    if (we_b) begin
        ram[addr_b] <= d_b;
        q_b <= d_b;
    end
end

endmodule