data/full_repos/permissive/517918128/dualport_sram.v
data/verilator_xmls/48a7cd75-8af5-4c90-8611-e4fdf146aa59.xml
module dualport_sram(input clk,wr,rd,
                    input [31:0] din, 
                    input [2:0] addr,
                    output reg [31:0] dout
);

reg [31:0] mem [7:0]; 
always @(posedge clk) 
begin
   if(wr && !rd)
   mem[addr]=din;
   else if(!wr && rd)
   dout=mem[addr]; 
   else
   begin
   dout=dout;
   mem[addr]=mem[addr];
   end
end
endmodule
module dualport_sram(input clk,wr,rd,
                    input [31:0] din, 
                    input [2:0] addr,
                    output reg [31:0] dout
);


reg [31:0] mem [7:0]; 
always @(posedge clk) 
begin
   if(wr && !rd)
   mem[addr]=din;
   else if(!wr && rd)
   dout=mem[addr]; 
   else
   begin
   dout=dout;
   mem[addr]=mem[addr];
   end
end
endmodule