data/full_repos/permissive/479997390/src/FullAdder32Bits.v
data/verilator_xmls/2371e7e6-6257-4ed9-bbf6-096a2072327e.xml
module oneBitAdder(
    a, b, carryIn, carryOut, sum
);
    input a, b, carryIn;
    output carryOut, sum;
    wire carryOut, sum;
    assign sum = a ^ b ^ carryIn;
    assign carryOut = (b & carryIn) | (a & carryIn) | (a & b);
endmodule
module oneBitAdder(
    a, b, carryIn, carryOut, sum
);

    input a, b, carryIn;
    output carryOut, sum;
    wire carryOut, sum;
    assign sum = a ^ b ^ carryIn;
    assign carryOut = (b & carryIn) | (a & carryIn) | (a & b);
endmodule