data/full_repos/permissive/506984841/stack_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #2 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20 top_in = 16\'b1100110011001100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10 top_in = 16\'b0011001100110011;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 top_in = 16\'b0011100110100101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 top_in = 16\'b1011001110001111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 w_tos = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 next_in = 16\'b1111111100000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506984841/stack_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = 0;\n  ^\n%Error: data/full_repos/permissive/506984841/stack_tb.v:19: Cannot find file containing module: \'stack\'\n stack uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/stack\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/stack.v\n             data/full_repos/permissive/506984841,data/full_repos/permissive/506984841/stack.sv\n             stack\n             stack.v\n             stack.sv\n             obj_dir/stack\n             obj_dir/stack.v\n             obj_dir/stack.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stack_tb;


	reg [15:0] top_in;
	reg [15:0] next_in;
	reg pop;
	reg push;
	reg w_tos;
	reg w_next;
	reg clk;
	reg rst;


	wire [15:0] top_out;
	wire [15:0] next_out;

	stack uut (
		.top_out(top_out), 
		.next_out(next_out), 
		.top_in(top_in), 
		.next_in(next_in), 
		.pop(pop), 
		.push(push), 
		.w_tos(w_tos), 
		.w_next(w_next), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		top_in = 0;
		next_in = 0;
		pop = 0;
		push = 0;
		w_tos = 0;
		w_next = 0;
		clk = 0;
		rst = 0;

		#2 rst = 1;
		#1 rst = 0;
		#20 top_in = 16'b1100110011001100;
		w_tos = 1;
		#10 top_in = 16'b0011001100110011;
		push = 1;
		#10 top_in = 16'b0011100110100101;
		#10 top_in = 16'b1011001110001111;
		#10 w_tos = 0;
		pop = 1;
		#10 next_in = 16'b1111111100000000;
		w_next = 1;
		pop = 0;
	end
	
	always begin
		#5 clk = 1;
		#5 clk = 0;
	end
      
endmodule
module stack_tb;



	reg [15:0] top_in;
	reg [15:0] next_in;
	reg pop;
	reg push;
	reg w_tos;
	reg w_next;
	reg clk;
	reg rst;


	wire [15:0] top_out;
	wire [15:0] next_out;

	stack uut (
		.top_out(top_out), 
		.next_out(next_out), 
		.top_in(top_in), 
		.next_in(next_in), 
		.pop(pop), 
		.push(push), 
		.w_tos(w_tos), 
		.w_next(w_next), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		top_in = 0;
		next_in = 0;
		pop = 0;
		push = 0;
		w_tos = 0;
		w_next = 0;
		clk = 0;
		rst = 0;

		#2 rst = 1;
		#1 rst = 0;
		#20 top_in = 16'b1100110011001100;
		w_tos = 1;
		#10 top_in = 16'b0011001100110011;
		push = 1;
		#10 top_in = 16'b0011100110100101;
		#10 top_in = 16'b1011001110001111;
		#10 w_tos = 0;
		pop = 1;
		#10 next_in = 16'b1111111100000000;
		w_next = 1;
		pop = 0;
	end
	
	always begin
		#5 clk = 1;
		#5 clk = 0;
	end
      
endmodule