data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:41: syntax error, unexpected \'@\'\n   @(posedge clock);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:46: syntax error, unexpected \'@\'\n   @(posedge clock);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clock = ~clock;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   initial #2000 enable = 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   initial #500000 signal_in = 16\'h7fff;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000000 signal_in = 16\'h8000;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n   initial #1500000 signal_in = 16\'hffff;\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("decim.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,cic_decim_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/justinterp_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   initial #10000000 $finish;\n           ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n'
module cic_decim_tb;

cic_decim #(.bitwidth(16),.stages(4))
   decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
	
   reg clock;
   reg reset;
   reg enable;
   wire strobe;
   reg [15:0] signal_in;
   wire [15:0] signal_out;

   assign      strobe_in = 1'b1;
   reg 	       strobe_out;

   always @(posedge clock)
     while(1)
       begin
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  strobe_out <= 1'b1;
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  strobe_out <= 1'b0;
       end
   
   initial clock = 0;
   always #50 clock = ~clock;
   
   initial reset = 1;
   initial #1000 reset = 0;

   initial enable = 0;
   initial #2000 enable = 1;
   
   initial signal_in = 16'h1;
   initial #500000 signal_in = 16'h7fff;
   initial #1000000 signal_in = 16'h8000;
   initial #1500000 signal_in = 16'hffff;

   
   initial $dumpfile("decim.vcd");
   initial $dumpvars(0,cic_decim_tb);

   initial #10000000 $finish;
   
endmodule
module cic_decim_tb;


cic_decim #(.bitwidth(16),.stages(4))
   decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
	
   reg clock;
   reg reset;
   reg enable;
   wire strobe;
   reg [15:0] signal_in;
   wire [15:0] signal_out;

   assign      strobe_in = 1'b1;
   reg 	       strobe_out;

   always @(posedge clock)
     while(1)
       begin
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  strobe_out <= 1'b1;
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  @(posedge clock);
	  strobe_out <= 1'b0;
       end
   
   initial clock = 0;
   always #50 clock = ~clock;
   
   initial reset = 1;
   initial #1000 reset = 0;

   initial enable = 0;
   initial #2000 enable = 1;
   
   initial signal_in = 16'h1;
   initial #500000 signal_in = 16'h7fff;
   initial #1000000 signal_in = 16'h8000;
   initial #1500000 signal_in = 16'hffff;

   
   initial $dumpfile("decim.vcd");
   initial $dumpvars(0,cic_decim_tb);

   initial #10000000 $finish;
   
endmodule