data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/conv_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/conv_sim.v:30: Unsupported: Ignoring delay on this delayed statement.\n#1000 $finish;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/conv_sim.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #1 num=num+1;\n       ^\n%Error: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/conv_sim.v:26: Cannot find file containing module: \'converter\'\nconverter cvt(num,seg1,seg2,seg3,seg4);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/converter\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/converter.v\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/converter.sv\n             converter\n             converter.v\n             converter.sv\n             obj_dir/converter\n             obj_dir/converter.v\n             obj_dir/converter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module conv_sim();
reg [9:0]num;
wire[7:0]seg1,seg2,seg3,seg4;
converter cvt(num,seg1,seg2,seg3,seg4);
initial
begin
num=0;
#1000 $finish;
end
always #1 num=num+1;
endmodule
module conv_sim();

reg [9:0]num;
wire[7:0]seg1,seg2,seg3,seg4;
converter cvt(num,seg1,seg2,seg3,seg4);
initial
begin
num=0;
#1000 $finish;
end
always #1 num=num+1;
endmodule