data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_DL_Dff_w_synch_reset.v
data/verilator_xmls/ce85e086-6b56-4bb8-9a58-7005279b3e88.xml
module bm_DL_Dff_w_synch_reset(D, Clock, Resetn, Q);
	input D, Clock, Resetn;
	output Q;
	reg Q;
	
	always @(posedge Clock)
		if (!Resetn)
			Q <= 0;
		else 
			Q <= D;
	
endmodule
module bm_DL_Dff_w_synch_reset(D, Clock, Resetn, Q);

	input D, Clock, Resetn;
	output Q;
	reg Q;
	
	always @(posedge Clock)
		if (!Resetn)
			Q <= 0;
		else 
			Q <= D;
	
endmodule