data/full_repos/permissive/499494419/cao.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/cao.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Error: data/full_repos/permissive/499494419/cao.v:52: Cannot find file containing module: \'try\'\n try uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/try\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/try.v\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/try.sv\n             try\n             try.v\n             try.sv\n             obj_dir/try\n             obj_dir/try.v\n             obj_dir/try.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cao;


	reg in;
	reg in1;
	reg sys_rst_n;


	wire k1;
	wire k2;
	wire a;
	wire zhuan1;
	wire zhuan2;
	wire zhuan3;
	wire p1;
	wire p2;
	wire h;
	wire c;
	wire d;
	wire p3;
	wire p4;
	wire p5;
	wire p6;
	wire p7;
	wire p8;


	try uut (
		.in(in), 
		.in1(in1), 
		.sys_rst_n(sys_rst_n), 
		.k1(k1), 
		.k2(k2), 
		.a(a),
		.zhuan1(zhuan1),
		.zhuan2(zhuan2),
		.zhuan3(zhuan3),
		.p1(p1), 
		.p2(p2), 
		.h(h),
		.c(c),
		.d(d),
		.p3(p3), 
		.p4(p4), 
		.p5(p5), 
		.p6(p6), 
		.p7(p7), 
		.p8(p8)
	);

	initial begin

		in = 0;
		in1 = 0;
		sys_rst_n = 0;


		#100;
        

		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;

	end
      
endmodule
module cao;



	reg in;
	reg in1;
	reg sys_rst_n;


	wire k1;
	wire k2;
	wire a;
	wire zhuan1;
	wire zhuan2;
	wire zhuan3;
	wire p1;
	wire p2;
	wire h;
	wire c;
	wire d;
	wire p3;
	wire p4;
	wire p5;
	wire p6;
	wire p7;
	wire p8;


	try uut (
		.in(in), 
		.in1(in1), 
		.sys_rst_n(sys_rst_n), 
		.k1(k1), 
		.k2(k2), 
		.a(a),
		.zhuan1(zhuan1),
		.zhuan2(zhuan2),
		.zhuan3(zhuan3),
		.p1(p1), 
		.p2(p2), 
		.h(h),
		.c(c),
		.d(d),
		.p3(p3), 
		.p4(p4), 
		.p5(p5), 
		.p6(p6), 
		.p7(p7), 
		.p8(p8)
	);

	initial begin

		in = 0;
		in1 = 0;
		sys_rst_n = 0;


		#100;
        

		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=1;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;
		#40;
		in=0;
		in1=1;
		#40;
		in=1;
		in1=0;

	end
      
endmodule