data/full_repos/permissive/52714256/GYRACC/src/ACC/slaveselect.v
data/verilator_xmls/50a89dd7-cadf-4f7a-b06d-d50f8b023724.xml
module slaveSelect(
		rst,
		clk,
		transmit,
		done,
		ss
);




   input   rst;
   input   clk;
   input   transmit;
   input   done;
   output  ss;
   reg     ss = 1'b1;
   
   



   
   



		always @(posedge clk)
		begin: ssprocess
			
			begin

				if (rst == 1'b1)
					ss <= 1'b1;

				else if (transmit == 1'b1)
					ss <= 1'b0;

				else if (done == 1'b1)
					ss <= 1'b1;
			end
		end
   
endmodule
module slaveSelect(
		rst,
		clk,
		transmit,
		done,
		ss
);





   input   rst;
   input   clk;
   input   transmit;
   input   done;
   output  ss;
   reg     ss = 1'b1;
   
   



   
   



		always @(posedge clk)
		begin: ssprocess
			
			begin

				if (rst == 1'b1)
					ss <= 1'b1;

				else if (transmit == 1'b1)
					ss <= 1'b0;

				else if (done == 1'b1)
					ss <= 1'b1;
			end
		end
   
endmodule