data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp13anon6/reference/MultiClockSpecanonfun22anonfunapplymcVsp13anon6.v
data/verilator_xmls/b839b058-7aa8-40d3-86d3-f7663e9f38e0.xml
module TAIL(y, in);
    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule
module TAIL(y, in);

    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule