data/full_repos/permissive/519759804/test_delayslot/ForwardingUnit.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/519759804/test_delayslot/ForwardingUnit.v:29: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'RAW_Forwarding\'\nmodule RAW_Forwarding(IDEX_Rs, IDEX_Rt, EXMEM_RegWr, EXMEM_RegWrAddr, MEMWB_RegWr, MEMWB_RegWrAddr, ForwardA, ForwardB);\n       ^~~~~~~~~~~~~~\n                                                                                          : ... Top module \'SAL_Forwarding\'\nmodule SAL_Forwarding(EXMEM_MemWr, EXMEM_Rt, MEMWB_MemRead, MEMWB_RegWrAddr, Forward);\n       ^~~~~~~~~~~~~~\n                                                                                          : ... Top module \'JAW_Forwarding\'\nmodule JAW_Forwarding(ID_OpCode, ID_Funct, ID_Rs, IDEX_RegWr, IDEX_RegWrAddr, EXMEM_MemtoReg, EXMEM_RegWr, EXMEM_RegWrAddr, Forward);\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module SAL_Forwarding(EXMEM_MemWr, EXMEM_Rt, MEMWB_MemRead, MEMWB_RegWrAddr, Forward);
	input EXMEM_MemWr;
	input [4:0] EXMEM_Rt;
	input MEMWB_MemRead;
	input [4:0] MEMWB_RegWrAddr;
	output Forward;
	
	wire condition=EXMEM_Rt != 0 && EXMEM_MemWr && MEMWB_MemRead && MEMWB_RegWrAddr == EXMEM_Rt;
	assign Forward=condition?1'b1:1'b0;
endmodule
module SAL_Forwarding(EXMEM_MemWr, EXMEM_Rt, MEMWB_MemRead, MEMWB_RegWrAddr, Forward);

	input EXMEM_MemWr;
	input [4:0] EXMEM_Rt;
	input MEMWB_MemRead;
	input [4:0] MEMWB_RegWrAddr;
	output Forward;
	
	wire condition=EXMEM_Rt != 0 && EXMEM_MemWr && MEMWB_MemRead && MEMWB_RegWrAddr == EXMEM_Rt;
	assign Forward=condition?1'b1:1'b0;
endmodule