data/full_repos/permissive/440170309/src/uart_reciver.v
1: b'%Error: data/full_repos/permissive/440170309/src/uart_reciver.v:13: syntax error, unexpected byte, expecting IDENTIFIER or do or final\n    wire [7: 0] byte;\n                ^~~~\n%Error: data/full_repos/permissive/440170309/src/uart_reciver.v:22: syntax error, unexpected byte\n        .byte(byte)\n         ^~~~\n%Error: data/full_repos/permissive/440170309/src/uart_reciver.v:36: syntax error, unexpected \';\', expecting "\'{"\n            frame_cube[byte_cnt] <= byte;\n                                        ^\n%Error: Exiting due to 3 error(s)\n'
module uart_reciver (
    input wire clk,
    input wire rst,
    input wire en,
    input wire rx,

    output wire tx,
    output wire [8*64-1: 0] frame_cube_flat,
    output reg frame_valid
);
    assign tx = 1'b1;

    wire [7: 0] byte;
    wire byte_valid;
    uart_rx uart_rx(
        .clk_100M(clk),
        .rst(rst),
        .en(en),
        .rx(rx),

        .byte_valid(byte_valid),
        .byte(byte)
    );

    reg [5: 0] byte_cnt;
    always @(posedge clk) begin

        byte_cnt <= rst                ? 0 :
                    byte_valid         ? byte_cnt + 1 : byte_cnt;
    end


    reg [7:0] frame_cube [63:0];
    always @(posedge clk) begin
        if(byte_valid) begin
            frame_cube[byte_cnt] <= byte;
        end
    end


    always @(posedge clk) begin
        frame_valid <= rst ? 0 :
                       ~frame_valid & byte_valid & (byte_cnt==63) ? 1 : 0;
    end

    genvar i;
    generate
        for(i = 0; i < 64; i = i + 1)
        begin : gen_frame
            assign frame_cube_flat[(i<<3) + 7 -: 8] = frame_cube[i];
        end
    endgenerate
    
endmodule
module uart_reciver (
    input wire clk,
    input wire rst,
    input wire en,
    input wire rx,

    output wire tx,
    output wire [8*64-1: 0] frame_cube_flat,
    output reg frame_valid
);

    assign tx = 1'b1;

    wire [7: 0] byte;
    wire byte_valid;
    uart_rx uart_rx(
        .clk_100M(clk),
        .rst(rst),
        .en(en),
        .rx(rx),

        .byte_valid(byte_valid),
        .byte(byte)
    );

    reg [5: 0] byte_cnt;
    always @(posedge clk) begin

        byte_cnt <= rst                ? 0 :
                    byte_valid         ? byte_cnt + 1 : byte_cnt;
    end


    reg [7:0] frame_cube [63:0];
    always @(posedge clk) begin
        if(byte_valid) begin
            frame_cube[byte_cnt] <= byte;
        end
    end


    always @(posedge clk) begin
        frame_valid <= rst ? 0 :
                       ~frame_valid & byte_valid & (byte_cnt==63) ? 1 : 0;
    end

    genvar i;
    generate
        for(i = 0; i < 64; i = i + 1)
        begin : gen_frame
            assign frame_cube_flat[(i<<3) + 7 -: 8] = frame_cube[i];
        end
    endgenerate
    
endmodule