data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:30: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_p1_sequence_d, M_p1_sequence_q = 1\'h0;\n                                                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_p2_sequence_d, M_p2_sequence_q = 1\'h0;\n                                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:32: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_sequence_count_d, M_sequence_count_q = 1\'h0;\n                                                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:33: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_p1_score_d, M_p1_score_q = 1\'h0;\n                                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:34: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_p2_score_d, M_p2_score_q = 1\'h0;\n                                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_round_d, M_round_q = 1\'h0;\n                                    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:36: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_is_p1_d, M_is_p1_q = 1\'h0;\n                                    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_literal_out_d, M_literal_out_q = 1\'h0;\n                                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:38: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_temp_var1_d, M_temp_var1_q = 1\'h0;\n                                            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:39: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_temp_var2_d, M_temp_var2_q = 1\'h0;\n                                            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:40: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_addvalue_d, M_addvalue_q = 1\'h0;\n                                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:41: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n  reg [15:0] M_loop_var_d, M_loop_var_q = 1\'h0;\n                                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:96: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance game_miniRegfile_5\n        out_a = 1\'h0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:138: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n        out_b = 1\'h0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:248: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_p1_sequence_q <= 1\'h0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:249: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_p2_sequence_q <= 1\'h0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:250: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_sequence_count_q <= 1\'h0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:251: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_p1_score_q <= 1\'h0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:252: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_p2_score_q <= 1\'h0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:253: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_round_q <= 1\'h0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:254: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_is_p1_q <= 1\'h0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:255: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_literal_out_q <= 1\'h0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:256: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_temp_var1_q <= 1\'h0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:257: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_temp_var2_q <= 1\'h0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:258: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_addvalue_q <= 1\'h0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/game_miniRegfile_5.v:259: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance game_miniRegfile_5\n      M_loop_var_q <= 1\'h0;\n                   ^~\n%Error: Exiting due to 26 warning(s)\n'
module game_miniRegfile_5 (
    input clk,
    input rst,
    input [3:0] rc,
    input we,
    input [15:0] data,
    input [3:0] ra,
    input [3:0] rb,
    output reg [15:0] out_a,
    output reg [15:0] out_b,
    output reg [15:0] literal,
    output reg [15:0] isP1,
    output reg [15:0] sequenceCount,
    output reg [15:0] p1Sequence,
    output reg [15:0] p2Sequence,
    output reg [15:0] tempvar1,
    output reg [15:0] tempvar2,
    output reg [15:0] addValue,
    output reg [15:0] loopVar
  );
  
  
  
  reg [15:0] M_p1_sequence_d, M_p1_sequence_q = 1'h0;
  reg [15:0] M_p2_sequence_d, M_p2_sequence_q = 1'h0;
  reg [15:0] M_sequence_count_d, M_sequence_count_q = 1'h0;
  reg [15:0] M_p1_score_d, M_p1_score_q = 1'h0;
  reg [15:0] M_p2_score_d, M_p2_score_q = 1'h0;
  reg [15:0] M_round_d, M_round_q = 1'h0;
  reg [15:0] M_is_p1_d, M_is_p1_q = 1'h0;
  reg [15:0] M_literal_out_d, M_literal_out_q = 1'h0;
  reg [15:0] M_temp_var1_d, M_temp_var1_q = 1'h0;
  reg [15:0] M_temp_var2_d, M_temp_var2_q = 1'h0;
  reg [15:0] M_addvalue_d, M_addvalue_q = 1'h0;
  reg [15:0] M_loop_var_d, M_loop_var_q = 1'h0;
  
  always @* begin
    M_sequence_count_d = M_sequence_count_q;
    M_p1_score_d = M_p1_score_q;
    M_literal_out_d = M_literal_out_q;
    M_addvalue_d = M_addvalue_q;
    M_round_d = M_round_q;
    M_p2_sequence_d = M_p2_sequence_q;
    M_temp_var1_d = M_temp_var1_q;
    M_temp_var2_d = M_temp_var2_q;
    M_is_p1_d = M_is_p1_q;
    M_p1_sequence_d = M_p1_sequence_q;
    M_p2_score_d = M_p2_score_q;
    M_loop_var_d = M_loop_var_q;
    
    
    case (ra)
      4'h0: begin
        out_a = M_p1_sequence_q;
      end
      4'h1: begin
        out_a = M_p2_sequence_q;
      end
      4'h2: begin
        out_a = M_sequence_count_q;
      end
      4'h3: begin
        out_a = M_p1_score_q;
      end
      4'h4: begin
        out_a = M_p2_score_q;
      end
      4'h5: begin
        out_a = M_round_q;
      end
      4'h6: begin
        out_a = M_is_p1_q;
      end
      4'h7: begin
        out_a = M_temp_var1_q;
      end
      4'h8: begin
        out_a = M_temp_var2_q;
      end
      4'h9: begin
        out_a = M_addvalue_q;
      end
      4'ha: begin
        out_a = M_literal_out_q;
      end
      4'hb: begin
        out_a = M_loop_var_q;
      end
      default: begin
        out_a = 1'h0;
      end
    endcase
    
    case (rb)
      4'h0: begin
        out_b = M_p1_sequence_q;
      end
      4'h1: begin
        out_b = M_p2_sequence_q;
      end
      4'h2: begin
        out_b = M_sequence_count_q;
      end
      4'h3: begin
        out_b = M_p1_score_q;
      end
      4'h4: begin
        out_b = M_p2_score_q;
      end
      4'h5: begin
        out_b = M_round_q;
      end
      4'h6: begin
        out_b = M_is_p1_q;
      end
      4'h7: begin
        out_b = M_temp_var1_q;
      end
      4'h8: begin
        out_b = M_temp_var2_q;
      end
      4'h9: begin
        out_b = M_addvalue_q;
      end
      4'ha: begin
        out_b = M_literal_out_q;
      end
      4'hb: begin
        out_b = M_loop_var_q;
      end
      default: begin
        out_b = 1'h0;
      end
    endcase
    if (we) begin
      
      case (rc)
        4'h0: begin
          M_p1_sequence_d = data;
        end
        4'h1: begin
          M_p2_sequence_d = data;
        end
        4'h2: begin
          M_sequence_count_d = data;
        end
        4'h3: begin
          M_p1_score_d = data;
        end
        4'h4: begin
          M_p2_score_d = data;
        end
        4'h5: begin
          M_round_d = data;
        end
        4'h6: begin
          M_is_p1_d = data;
        end
        4'h7: begin
          M_temp_var1_d = data;
        end
        4'h8: begin
          M_temp_var2_d = data;
        end
        4'h9: begin
          
          case (M_sequence_count_q)
            16'h0000: begin
              M_addvalue_d = 16'h0001;
            end
            16'h0001: begin
              M_addvalue_d = 16'h0002;
            end
            16'h0002: begin
              M_addvalue_d = 16'h0004;
            end
            16'h0003: begin
              M_addvalue_d = 16'h0008;
            end
            16'h0004: begin
              M_addvalue_d = 16'h0010;
            end
            16'h0005: begin
              M_addvalue_d = 16'h0020;
            end
            16'h0006: begin
              M_addvalue_d = 16'h0040;
            end
            16'h0007: begin
              M_addvalue_d = 16'h0080;
            end
            16'h0008: begin
              M_addvalue_d = 16'h0100;
            end
            16'h0009: begin
              M_addvalue_d = 16'h0200;
            end
            16'h000a: begin
              M_addvalue_d = 16'h0400;
            end
            16'h000b: begin
              M_addvalue_d = 16'h0800;
            end
            16'h000c: begin
              M_addvalue_d = 16'h1000;
            end
            16'h000d: begin
              M_addvalue_d = 16'h2000;
            end
            16'h000e: begin
              M_addvalue_d = 16'h4000;
            end
            16'h000f: begin
              M_addvalue_d = 16'h8000;
            end
            default: begin
              M_addvalue_d = 16'h0000;
            end
          endcase
        end
        4'ha: begin
          M_literal_out_d = data;
        end
        4'hb: begin
          M_loop_var_d = data;
        end
      endcase
    end
    literal = M_literal_out_q;
    isP1 = M_is_p1_q;
    tempvar1 = M_temp_var1_q;
    tempvar2 = M_temp_var2_q;
    sequenceCount = M_sequence_count_q;
    p1Sequence = M_p1_sequence_q;
    p2Sequence = M_p2_sequence_q;
    addValue = M_addvalue_q;
    loopVar = M_loop_var_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_p1_sequence_q <= 1'h0;
      M_p2_sequence_q <= 1'h0;
      M_sequence_count_q <= 1'h0;
      M_p1_score_q <= 1'h0;
      M_p2_score_q <= 1'h0;
      M_round_q <= 1'h0;
      M_is_p1_q <= 1'h0;
      M_literal_out_q <= 1'h0;
      M_temp_var1_q <= 1'h0;
      M_temp_var2_q <= 1'h0;
      M_addvalue_q <= 1'h0;
      M_loop_var_q <= 1'h0;
    end else begin
      M_p1_sequence_q <= M_p1_sequence_d;
      M_p2_sequence_q <= M_p2_sequence_d;
      M_sequence_count_q <= M_sequence_count_d;
      M_p1_score_q <= M_p1_score_d;
      M_p2_score_q <= M_p2_score_d;
      M_round_q <= M_round_d;
      M_is_p1_q <= M_is_p1_d;
      M_literal_out_q <= M_literal_out_d;
      M_temp_var1_q <= M_temp_var1_d;
      M_temp_var2_q <= M_temp_var2_d;
      M_addvalue_q <= M_addvalue_d;
      M_loop_var_q <= M_loop_var_d;
    end
  end
  
endmodule
module game_miniRegfile_5 (
    input clk,
    input rst,
    input [3:0] rc,
    input we,
    input [15:0] data,
    input [3:0] ra,
    input [3:0] rb,
    output reg [15:0] out_a,
    output reg [15:0] out_b,
    output reg [15:0] literal,
    output reg [15:0] isP1,
    output reg [15:0] sequenceCount,
    output reg [15:0] p1Sequence,
    output reg [15:0] p2Sequence,
    output reg [15:0] tempvar1,
    output reg [15:0] tempvar2,
    output reg [15:0] addValue,
    output reg [15:0] loopVar
  );

  
  
  
  reg [15:0] M_p1_sequence_d, M_p1_sequence_q = 1'h0;
  reg [15:0] M_p2_sequence_d, M_p2_sequence_q = 1'h0;
  reg [15:0] M_sequence_count_d, M_sequence_count_q = 1'h0;
  reg [15:0] M_p1_score_d, M_p1_score_q = 1'h0;
  reg [15:0] M_p2_score_d, M_p2_score_q = 1'h0;
  reg [15:0] M_round_d, M_round_q = 1'h0;
  reg [15:0] M_is_p1_d, M_is_p1_q = 1'h0;
  reg [15:0] M_literal_out_d, M_literal_out_q = 1'h0;
  reg [15:0] M_temp_var1_d, M_temp_var1_q = 1'h0;
  reg [15:0] M_temp_var2_d, M_temp_var2_q = 1'h0;
  reg [15:0] M_addvalue_d, M_addvalue_q = 1'h0;
  reg [15:0] M_loop_var_d, M_loop_var_q = 1'h0;
  
  always @* begin
    M_sequence_count_d = M_sequence_count_q;
    M_p1_score_d = M_p1_score_q;
    M_literal_out_d = M_literal_out_q;
    M_addvalue_d = M_addvalue_q;
    M_round_d = M_round_q;
    M_p2_sequence_d = M_p2_sequence_q;
    M_temp_var1_d = M_temp_var1_q;
    M_temp_var2_d = M_temp_var2_q;
    M_is_p1_d = M_is_p1_q;
    M_p1_sequence_d = M_p1_sequence_q;
    M_p2_score_d = M_p2_score_q;
    M_loop_var_d = M_loop_var_q;
    
    
    case (ra)
      4'h0: begin
        out_a = M_p1_sequence_q;
      end
      4'h1: begin
        out_a = M_p2_sequence_q;
      end
      4'h2: begin
        out_a = M_sequence_count_q;
      end
      4'h3: begin
        out_a = M_p1_score_q;
      end
      4'h4: begin
        out_a = M_p2_score_q;
      end
      4'h5: begin
        out_a = M_round_q;
      end
      4'h6: begin
        out_a = M_is_p1_q;
      end
      4'h7: begin
        out_a = M_temp_var1_q;
      end
      4'h8: begin
        out_a = M_temp_var2_q;
      end
      4'h9: begin
        out_a = M_addvalue_q;
      end
      4'ha: begin
        out_a = M_literal_out_q;
      end
      4'hb: begin
        out_a = M_loop_var_q;
      end
      default: begin
        out_a = 1'h0;
      end
    endcase
    
    case (rb)
      4'h0: begin
        out_b = M_p1_sequence_q;
      end
      4'h1: begin
        out_b = M_p2_sequence_q;
      end
      4'h2: begin
        out_b = M_sequence_count_q;
      end
      4'h3: begin
        out_b = M_p1_score_q;
      end
      4'h4: begin
        out_b = M_p2_score_q;
      end
      4'h5: begin
        out_b = M_round_q;
      end
      4'h6: begin
        out_b = M_is_p1_q;
      end
      4'h7: begin
        out_b = M_temp_var1_q;
      end
      4'h8: begin
        out_b = M_temp_var2_q;
      end
      4'h9: begin
        out_b = M_addvalue_q;
      end
      4'ha: begin
        out_b = M_literal_out_q;
      end
      4'hb: begin
        out_b = M_loop_var_q;
      end
      default: begin
        out_b = 1'h0;
      end
    endcase
    if (we) begin
      
      case (rc)
        4'h0: begin
          M_p1_sequence_d = data;
        end
        4'h1: begin
          M_p2_sequence_d = data;
        end
        4'h2: begin
          M_sequence_count_d = data;
        end
        4'h3: begin
          M_p1_score_d = data;
        end
        4'h4: begin
          M_p2_score_d = data;
        end
        4'h5: begin
          M_round_d = data;
        end
        4'h6: begin
          M_is_p1_d = data;
        end
        4'h7: begin
          M_temp_var1_d = data;
        end
        4'h8: begin
          M_temp_var2_d = data;
        end
        4'h9: begin
          
          case (M_sequence_count_q)
            16'h0000: begin
              M_addvalue_d = 16'h0001;
            end
            16'h0001: begin
              M_addvalue_d = 16'h0002;
            end
            16'h0002: begin
              M_addvalue_d = 16'h0004;
            end
            16'h0003: begin
              M_addvalue_d = 16'h0008;
            end
            16'h0004: begin
              M_addvalue_d = 16'h0010;
            end
            16'h0005: begin
              M_addvalue_d = 16'h0020;
            end
            16'h0006: begin
              M_addvalue_d = 16'h0040;
            end
            16'h0007: begin
              M_addvalue_d = 16'h0080;
            end
            16'h0008: begin
              M_addvalue_d = 16'h0100;
            end
            16'h0009: begin
              M_addvalue_d = 16'h0200;
            end
            16'h000a: begin
              M_addvalue_d = 16'h0400;
            end
            16'h000b: begin
              M_addvalue_d = 16'h0800;
            end
            16'h000c: begin
              M_addvalue_d = 16'h1000;
            end
            16'h000d: begin
              M_addvalue_d = 16'h2000;
            end
            16'h000e: begin
              M_addvalue_d = 16'h4000;
            end
            16'h000f: begin
              M_addvalue_d = 16'h8000;
            end
            default: begin
              M_addvalue_d = 16'h0000;
            end
          endcase
        end
        4'ha: begin
          M_literal_out_d = data;
        end
        4'hb: begin
          M_loop_var_d = data;
        end
      endcase
    end
    literal = M_literal_out_q;
    isP1 = M_is_p1_q;
    tempvar1 = M_temp_var1_q;
    tempvar2 = M_temp_var2_q;
    sequenceCount = M_sequence_count_q;
    p1Sequence = M_p1_sequence_q;
    p2Sequence = M_p2_sequence_q;
    addValue = M_addvalue_q;
    loopVar = M_loop_var_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_p1_sequence_q <= 1'h0;
      M_p2_sequence_q <= 1'h0;
      M_sequence_count_q <= 1'h0;
      M_p1_score_q <= 1'h0;
      M_p2_score_q <= 1'h0;
      M_round_q <= 1'h0;
      M_is_p1_q <= 1'h0;
      M_literal_out_q <= 1'h0;
      M_temp_var1_q <= 1'h0;
      M_temp_var2_q <= 1'h0;
      M_addvalue_q <= 1'h0;
      M_loop_var_q <= 1'h0;
    end else begin
      M_p1_sequence_q <= M_p1_sequence_d;
      M_p2_sequence_q <= M_p2_sequence_d;
      M_sequence_count_q <= M_sequence_count_d;
      M_p1_score_q <= M_p1_score_d;
      M_p2_score_q <= M_p2_score_d;
      M_round_q <= M_round_d;
      M_is_p1_q <= M_is_p1_d;
      M_literal_out_q <= M_literal_out_d;
      M_temp_var1_q <= M_temp_var1_d;
      M_temp_var2_q <= M_temp_var2_d;
      M_addvalue_q <= M_addvalue_d;
      M_loop_var_q <= M_loop_var_d;
    end
  end
  
endmodule