data/full_repos/permissive/47209311/hdl/timing_generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:69: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'pixel_counter\' generates 7 bits.\n                                                                             : ... In instance timing_generator\nwire last_pixel = (pixel_counter >= (C_LED_WIDTH * C_LED_CHAIN_LENGTH) - 1);\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:71: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'bank_counter\' generates 4 bits.\n                                                                             : ... In instance timing_generator\nwire last_line = (bank_counter >= C_LED_NBANKS - 1);\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:73: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'subframe_counter\' generates 4 bits.\n                                                                             : ... In instance timing_generator\nwire last_subframe = (subframe_counter >= C_BPC - 1);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:117: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                              : ... In instance timing_generator\n                divider_counter <= C_LED_CLKDIV - 1;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:137: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                              : ... In instance timing_generator\n                    divider_counter <= C_LED_CLKDIV - 1;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:147: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'divider_counter\' generates 5 bits.\n                                                                              : ... In instance timing_generator\n                if (divider_counter >= (C_LED_CLKDIV / 2))\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:163: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'divider_counter\' generates 5 bits.\n                                                                              : ... In instance timing_generator\n                if (divider_counter < ((C_LED_CLKDIV >> 1) + (C_LED_CLKDIV >> 2)))\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/47209311/hdl/timing_generator.v:235: Operator SHIFTR expects 25 bits on the LHS, but LHS\'s VARREF \'subframe_calibration_delay\' generates 13 bits.\n                                                                              : ... In instance timing_generator\n                    subframe_delay <= ((subframe_calibration_delay>>1) << subframe_counter);\n                                                                  ^~\n%Error: Exiting due to 8 warning(s)\n'
module timing_generator #(

    parameter integer C_LED_CHAIN_LENGTH = 4,

    parameter integer C_LED_NBANKS = 16,

    parameter integer C_LED_WIDTH = 32,

    parameter integer C_LED_CLKDIV = 32,

    parameter integer C_BPC = 12
)
(


    
    input sys_en,
    input sys_clk,
    input sys_rst,
    
    output reg led_clk,
    output reg led_stb,
    output reg led_oe,
    output [$clog2(C_LED_NBANKS)-1 : 0] led_bank,
    
    output [$clog2(C_LED_WIDTH * C_LED_CHAIN_LENGTH)-1 : 0] ctl_cur_x,
    output [$clog2(C_LED_NBANKS)-1 : 0] ctl_cur_y,
    output [$clog2(C_BPC)-1 : 0] ctl_cur_bit,
    output ctl_vsync
);    



reg [$clog2(C_LED_WIDTH * C_LED_CHAIN_LENGTH)-1 : 0] pixel_counter;
assign ctl_cur_x = pixel_counter;

reg [$clog2(C_LED_NBANKS)-1 : 0] bank_counter;
assign led_bank = bank_counter;
assign ctl_cur_y = bank_counter;

reg [$clog2(C_LED_CLKDIV)-1 : 0] divider_counter;

reg [$clog2(C_BPC)-1 : 0] subframe_counter;
assign ctl_cur_bit = subframe_counter;



wire last_pixel = (pixel_counter >= (C_LED_WIDTH * C_LED_CHAIN_LENGTH) - 1);

wire last_line = (bank_counter >= C_LED_NBANKS - 1);

wire last_subframe = (subframe_counter >= C_BPC - 1);



`define LINE_IDLE 3'b000

`define LINE_PREPARE_FOR_BURST 3'b001

`define LINE_BURST 3'b010

`define LINE_WAIT_FOR_CONFIRMATION 3'b011

`define LINE_LATCH 3'b100
reg [2:0] line_fsm_state;
wire line_fsm_start;
reg line_fsm_busy;

always @(posedge sys_clk or negedge sys_rst)
begin
    if (~sys_rst) begin


        divider_counter <= 0;

        pixel_counter <= 0;
        
        line_fsm_busy <= 0;
        line_fsm_state <= `LINE_IDLE;
    end else begin
        case (line_fsm_state)
            `LINE_IDLE: begin

                if (~line_fsm_busy) begin
                    if (line_fsm_start) begin
                        line_fsm_busy <= 1;
                    end else begin
                        line_fsm_busy <= 0;
                    end
                end else begin
                    line_fsm_state <= `LINE_PREPARE_FOR_BURST;
                end
            end
            `LINE_PREPARE_FOR_BURST: begin

                divider_counter <= C_LED_CLKDIV - 1;

                pixel_counter <= 0;
                

                led_clk <= 0;
                led_stb <= 0;
                
                line_fsm_state <= `LINE_BURST;
            end
            `LINE_BURST: begin

                if (divider_counter == 0) begin

                    if (last_pixel) begin
                        pixel_counter <= 0;
                        line_fsm_state <= `LINE_LATCH;
                    end else begin
                        pixel_counter <= pixel_counter + 1;
                    end
                    divider_counter <= C_LED_CLKDIV - 1;
                end else begin
                    divider_counter <= divider_counter - 1;
                end






                if (divider_counter >= (C_LED_CLKDIV / 2))
                    led_clk <= 0;
                else
                    led_clk <= 1;
            end
            `LINE_LATCH: begin

                led_clk <= 0;
                
                if (divider_counter == 0) begin
                    line_fsm_state <= `LINE_IDLE;
                    line_fsm_busy <= 0;
                end else begin
                    divider_counter <= divider_counter - 1;
                end
                
                if (divider_counter < ((C_LED_CLKDIV >> 1) + (C_LED_CLKDIV >> 2)))
                    led_stb <= 0;
                else
                    led_stb <= 1;
            end
        endcase
    end
end


`define SUBFRAME_IDLE 3'b000
`define SUBFRAME_CALIBRATE 3'b001
`define SUBFRAME_CALIBRATE2 3'b010
`define SUBFRAME_WAIT 3'b011
`define SUBFRAME_WAIT2 3'b100
`define SUBFRAME_VSYNC1 3'b101
`define SUBFRAME_VSYNC2 3'b110
reg [2:0] subframe_fsm_state;


reg subframe_line_start;
assign line_fsm_start = subframe_line_start;








reg [$clog2(2**C_BPC  * (C_LED_WIDTH * C_LED_CHAIN_LENGTH) * C_LED_CLKDIV * 2)-1: 0] subframe_delay;
reg [$clog2((C_LED_WIDTH * C_LED_CHAIN_LENGTH) * C_LED_CLKDIV * 2)-1: 0] subframe_calibration_delay;

reg vsync;
assign ctl_vsync = vsync;
always @(posedge sys_clk or negedge sys_rst)
begin
    if (~sys_rst) begin
        subframe_counter <= 0;
        subframe_calibration_delay <= 0;
        subframe_delay <= 0;
        bank_counter <= 0;
        vsync <= 0;
        
        subframe_line_start <= 0;
        subframe_fsm_state <= `SUBFRAME_IDLE;
    end else begin
        case (subframe_fsm_state)
            `SUBFRAME_IDLE: begin
                led_oe <= 1;
                if (!line_fsm_busy) begin
                    subframe_line_start <= 1;





                        subframe_fsm_state <= `SUBFRAME_WAIT;
                        subframe_delay <= (8 << subframe_counter); 

                end else begin
                end
            end
            `SUBFRAME_CALIBRATE: begin
                subframe_line_start <= 0;
                subframe_calibration_delay <= 0;
                subframe_fsm_state <= `SUBFRAME_CALIBRATE2;
            end
            `SUBFRAME_CALIBRATE2: begin
                if (!line_fsm_busy) begin

                    subframe_calibration_delay <= 1;
                    subframe_delay <= ((subframe_calibration_delay>>1) << subframe_counter);
                    subframe_fsm_state <= `SUBFRAME_WAIT2;
                end else begin
                    subframe_calibration_delay <= subframe_calibration_delay + 1;
                end
            end
            `SUBFRAME_WAIT: begin
                subframe_line_start <= 0;
                subframe_fsm_state <= `SUBFRAME_WAIT2;
            end
            `SUBFRAME_WAIT2: begin
                if (!line_fsm_busy) begin
                    led_oe <= 0;
                    if (subframe_delay == 0) begin
                        
                        
                        if (last_subframe) begin
                            subframe_counter <= 0;
                            if (last_line) begin
                                bank_counter <= 0;
                                subframe_fsm_state <= `SUBFRAME_VSYNC1;
                                subframe_delay = 10;
                            end else begin
                                bank_counter <= bank_counter + 1;
                                subframe_fsm_state <= `SUBFRAME_IDLE;
                            end
                        end else begin
                            subframe_counter <= subframe_counter + 1;
                            subframe_fsm_state <= `SUBFRAME_IDLE;
                        end
                    end else begin
                        subframe_delay <= subframe_delay - 1;
                    end
                end else begin
                    led_oe <= 1;
                end
            end
            `SUBFRAME_VSYNC1: begin
                led_oe <= 1;
                vsync <= 1;
                if (subframe_delay == 0) begin
                    subframe_fsm_state <= `SUBFRAME_VSYNC2;
                    subframe_delay <= 50;
                end else begin
                    subframe_delay <= subframe_delay - 1;
                end
            end
            `SUBFRAME_VSYNC2: begin
                vsync <= 0;
                if (subframe_delay == 0) begin
                    subframe_fsm_state <= `SUBFRAME_IDLE;
                end else begin
                    subframe_delay <= subframe_delay - 1;
                end
            end
        endcase
    end
end

endmodule
module timing_generator #(

    parameter integer C_LED_CHAIN_LENGTH = 4,

    parameter integer C_LED_NBANKS = 16,

    parameter integer C_LED_WIDTH = 32,

    parameter integer C_LED_CLKDIV = 32,

    parameter integer C_BPC = 12
)
(


    
    input sys_en,
    input sys_clk,
    input sys_rst,
    
    output reg led_clk,
    output reg led_stb,
    output reg led_oe,
    output [$clog2(C_LED_NBANKS)-1 : 0] led_bank,
    
    output [$clog2(C_LED_WIDTH * C_LED_CHAIN_LENGTH)-1 : 0] ctl_cur_x,
    output [$clog2(C_LED_NBANKS)-1 : 0] ctl_cur_y,
    output [$clog2(C_BPC)-1 : 0] ctl_cur_bit,
    output ctl_vsync
);
    



reg [$clog2(C_LED_WIDTH * C_LED_CHAIN_LENGTH)-1 : 0] pixel_counter;
assign ctl_cur_x = pixel_counter;

reg [$clog2(C_LED_NBANKS)-1 : 0] bank_counter;
assign led_bank = bank_counter;
assign ctl_cur_y = bank_counter;

reg [$clog2(C_LED_CLKDIV)-1 : 0] divider_counter;

reg [$clog2(C_BPC)-1 : 0] subframe_counter;
assign ctl_cur_bit = subframe_counter;



wire last_pixel = (pixel_counter >= (C_LED_WIDTH * C_LED_CHAIN_LENGTH) - 1);

wire last_line = (bank_counter >= C_LED_NBANKS - 1);

wire last_subframe = (subframe_counter >= C_BPC - 1);



`define LINE_IDLE 3'b000

`define LINE_PREPARE_FOR_BURST 3'b001

`define LINE_BURST 3'b010

`define LINE_WAIT_FOR_CONFIRMATION 3'b011

`define LINE_LATCH 3'b100
reg [2:0] line_fsm_state;
wire line_fsm_start;
reg line_fsm_busy;

always @(posedge sys_clk or negedge sys_rst)
begin
    if (~sys_rst) begin


        divider_counter <= 0;

        pixel_counter <= 0;
        
        line_fsm_busy <= 0;
        line_fsm_state <= `LINE_IDLE;
    end else begin
        case (line_fsm_state)
            `LINE_IDLE: begin

                if (~line_fsm_busy) begin
                    if (line_fsm_start) begin
                        line_fsm_busy <= 1;
                    end else begin
                        line_fsm_busy <= 0;
                    end
                end else begin
                    line_fsm_state <= `LINE_PREPARE_FOR_BURST;
                end
            end
            `LINE_PREPARE_FOR_BURST: begin

                divider_counter <= C_LED_CLKDIV - 1;

                pixel_counter <= 0;
                

                led_clk <= 0;
                led_stb <= 0;
                
                line_fsm_state <= `LINE_BURST;
            end
            `LINE_BURST: begin

                if (divider_counter == 0) begin

                    if (last_pixel) begin
                        pixel_counter <= 0;
                        line_fsm_state <= `LINE_LATCH;
                    end else begin
                        pixel_counter <= pixel_counter + 1;
                    end
                    divider_counter <= C_LED_CLKDIV - 1;
                end else begin
                    divider_counter <= divider_counter - 1;
                end






                if (divider_counter >= (C_LED_CLKDIV / 2))
                    led_clk <= 0;
                else
                    led_clk <= 1;
            end
            `LINE_LATCH: begin

                led_clk <= 0;
                
                if (divider_counter == 0) begin
                    line_fsm_state <= `LINE_IDLE;
                    line_fsm_busy <= 0;
                end else begin
                    divider_counter <= divider_counter - 1;
                end
                
                if (divider_counter < ((C_LED_CLKDIV >> 1) + (C_LED_CLKDIV >> 2)))
                    led_stb <= 0;
                else
                    led_stb <= 1;
            end
        endcase
    end
end


`define SUBFRAME_IDLE 3'b000
`define SUBFRAME_CALIBRATE 3'b001
`define SUBFRAME_CALIBRATE2 3'b010
`define SUBFRAME_WAIT 3'b011
`define SUBFRAME_WAIT2 3'b100
`define SUBFRAME_VSYNC1 3'b101
`define SUBFRAME_VSYNC2 3'b110
reg [2:0] subframe_fsm_state;


reg subframe_line_start;
assign line_fsm_start = subframe_line_start;








reg [$clog2(2**C_BPC  * (C_LED_WIDTH * C_LED_CHAIN_LENGTH) * C_LED_CLKDIV * 2)-1: 0] subframe_delay;
reg [$clog2((C_LED_WIDTH * C_LED_CHAIN_LENGTH) * C_LED_CLKDIV * 2)-1: 0] subframe_calibration_delay;

reg vsync;
assign ctl_vsync = vsync;
always @(posedge sys_clk or negedge sys_rst)
begin
    if (~sys_rst) begin
        subframe_counter <= 0;
        subframe_calibration_delay <= 0;
        subframe_delay <= 0;
        bank_counter <= 0;
        vsync <= 0;
        
        subframe_line_start <= 0;
        subframe_fsm_state <= `SUBFRAME_IDLE;
    end else begin
        case (subframe_fsm_state)
            `SUBFRAME_IDLE: begin
                led_oe <= 1;
                if (!line_fsm_busy) begin
                    subframe_line_start <= 1;





                        subframe_fsm_state <= `SUBFRAME_WAIT;
                        subframe_delay <= (8 << subframe_counter); 

                end else begin
                end
            end
            `SUBFRAME_CALIBRATE: begin
                subframe_line_start <= 0;
                subframe_calibration_delay <= 0;
                subframe_fsm_state <= `SUBFRAME_CALIBRATE2;
            end
            `SUBFRAME_CALIBRATE2: begin
                if (!line_fsm_busy) begin

                    subframe_calibration_delay <= 1;
                    subframe_delay <= ((subframe_calibration_delay>>1) << subframe_counter);
                    subframe_fsm_state <= `SUBFRAME_WAIT2;
                end else begin
                    subframe_calibration_delay <= subframe_calibration_delay + 1;
                end
            end
            `SUBFRAME_WAIT: begin
                subframe_line_start <= 0;
                subframe_fsm_state <= `SUBFRAME_WAIT2;
            end
            `SUBFRAME_WAIT2: begin
                if (!line_fsm_busy) begin
                    led_oe <= 0;
                    if (subframe_delay == 0) begin
                        
                        
                        if (last_subframe) begin
                            subframe_counter <= 0;
                            if (last_line) begin
                                bank_counter <= 0;
                                subframe_fsm_state <= `SUBFRAME_VSYNC1;
                                subframe_delay = 10;
                            end else begin
                                bank_counter <= bank_counter + 1;
                                subframe_fsm_state <= `SUBFRAME_IDLE;
                            end
                        end else begin
                            subframe_counter <= subframe_counter + 1;
                            subframe_fsm_state <= `SUBFRAME_IDLE;
                        end
                    end else begin
                        subframe_delay <= subframe_delay - 1;
                    end
                end else begin
                    led_oe <= 1;
                end
            end
            `SUBFRAME_VSYNC1: begin
                led_oe <= 1;
                vsync <= 1;
                if (subframe_delay == 0) begin
                    subframe_fsm_state <= `SUBFRAME_VSYNC2;
                    subframe_delay <= 50;
                end else begin
                    subframe_delay <= subframe_delay - 1;
                end
            end
            `SUBFRAME_VSYNC2: begin
                vsync <= 0;
                if (subframe_delay == 0) begin
                    subframe_fsm_state <= `SUBFRAME_IDLE;
                end else begin
                    subframe_delay <= subframe_delay - 1;
                end
            end
        endcase
    end
end

endmodule