data/full_repos/permissive/431682734/LabN/LabN4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431682734/LabN/LabN4.v:51: Unsupported: Ignoring delay on this delayed statement.\n        entryPoint = 16\'h28; #1;\n                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabN/LabN4.v:56: Unsupported: Ignoring delay on this delayed statement.\n            clk = 1; #1;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabN/LabN4.v:60: Unsupported: Ignoring delay on this delayed statement.\n            clk = 0; #1;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabN/LabN4.v:63: Unsupported: Ignoring delay on this delayed statement.\n            #4 $display("%8h: rd1=%d rd2=%d imm=%d jTarget=%d z=%d zero=%b wb=%d ALUop=%b funct3=%b op=%b", ins, rd1, rd2, imm, jTarget, z, zero, wb, ALUop, funct3, op);\n            ^\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:16: Cannot find file containing module: \'yIF\'\n    yIF myIF(ins, PC, PCp4, PCin, clk);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/431682734/LabN,data/full_repos/permissive/431682734/yIF\n             data/full_repos/permissive/431682734/LabN,data/full_repos/permissive/431682734/yIF.v\n             data/full_repos/permissive/431682734/LabN,data/full_repos/permissive/431682734/yIF.sv\n             yIF\n             yIF.v\n             yIF.sv\n             obj_dir/yIF\n             obj_dir/yIF.v\n             obj_dir/yIF.sv\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:17: Cannot find file containing module: \'yID\'\n    yID myID(rd1, rd2, imm, jTarget, branch, ins, wd, RegWrite, clk);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:18: Cannot find file containing module: \'yEX\'\n    yEX myEx(z, zero, rd1, rd2, imm, op, ALUSrc);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:19: Cannot find file containing module: \'yDM\'\n    yDM myDM(memOut, z, rd2, clk, MemRead, MemWrite);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:20: Cannot find file containing module: \'yWB\'\n    yWB myWB(wb, z, memOut, Mem2Reg);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:23: Cannot find file containing module: \'yPC\'\n    yPC myPC(PCin, PC, PCp4, INT, entryPoint, branch, jTarget, zero, isbranch, isjump);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:26: Cannot find file containing module: \'yC1\'\n    yC1 myC1(isStype, isRtype, isItype, isLw, isjump, isbranch, opCode);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:27: Cannot find file containing module: \'yC2\'\n    yC2 myC2(RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg, isStype, isRtype, isItype, isLw, isjump, isbranch);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:29: Cannot find file containing module: \'yC3\'\n    yC3 myC3(ALUop, isRtype, isbranch);\n    ^~~\n%Error: data/full_repos/permissive/431682734/LabN/LabN4.v:31: Cannot find file containing module: \'yC4\'\n    yC4 myC4(op, ALUop, funct3);\n    ^~~\n%Warning-WIDTH: data/full_repos/permissive/431682734/LabN/LabN4.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h28\' generates 16 bits.\n                                                                    : ... In instance labM\n        entryPoint = 16\'h28; #1;\n                   ^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labM;
    wire [31:0] PCin, PC;
    reg clk, INT;
    wire [2:0] op, funct3;
    reg [31:0] entryPoint;

    wire [31:0] wd, rd1, rd2, imm, ins, PCp4, z, branch;
    wire [31:0] jTarget;
    wire [31:0] memOut, wb;
    wire zero;
    wire [6:0] opCode;
    wire isStype, isRtype, isItype, isLw, isjump, isbranch;
    wire RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg;
    wire [1:0] ALUop;

    yIF myIF(ins, PC, PCp4, PCin, clk);
    yID myID(rd1, rd2, imm, jTarget, branch, ins, wd, RegWrite, clk);
    yEX myEx(z, zero, rd1, rd2, imm, op, ALUSrc);
    yDM myDM(memOut, z, rd2, clk, MemRead, MemWrite);
    yWB myWB(wb, z, memOut, Mem2Reg);

    assign wd = wb; 
    yPC myPC(PCin, PC, PCp4, INT, entryPoint, branch, jTarget, zero, isbranch, isjump);

    assign opCode = ins[6:0];
    yC1 myC1(isStype, isRtype, isItype, isLw, isjump, isbranch, opCode);
    yC2 myC2(RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg, isStype, isRtype, isItype, isLw, isjump, isbranch);

    yC3 myC3(ALUop, isRtype, isbranch);
    assign funct3=ins[14:12];
    yC4 myC4(op, ALUop, funct3);


    wire [15:0] z16;
    wire [7:0] z8;
    wire [3:0] z4;
    wire [1:0] z2;
    wire z1, exp_zero;

    or or16[15:0] (z16, z[15:0], z[31:16]);
    or or8[7:0] (z8, z16[7:0], z16[15:8]);
    or or4[3:0] (z4, z8[3:0], z8[7:4]);
    or or2[1:0] (z2, z4[1:0], z4[3:2]);
    or or1 (z1, z2[1], z2[0]);
    not zero_not(exp_zero, z1);

    initial
    begin

        INT = 1;
        entryPoint = 16'h28; #1;

        repeat (43)
        begin

            clk = 1; #1;
            INT = 0;
            

            clk = 0; #1;


            #4 $display("%8h: rd1=%d rd2=%d imm=%d jTarget=%d z=%d zero=%b wb=%d ALUop=%b funct3=%b op=%b", ins, rd1, rd2, imm, jTarget, z, zero, wb, ALUop, funct3, op);

        end
        $finish;
    end
endmodule
module labM;

    wire [31:0] PCin, PC;
    reg clk, INT;
    wire [2:0] op, funct3;
    reg [31:0] entryPoint;

    wire [31:0] wd, rd1, rd2, imm, ins, PCp4, z, branch;
    wire [31:0] jTarget;
    wire [31:0] memOut, wb;
    wire zero;
    wire [6:0] opCode;
    wire isStype, isRtype, isItype, isLw, isjump, isbranch;
    wire RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg;
    wire [1:0] ALUop;

    yIF myIF(ins, PC, PCp4, PCin, clk);
    yID myID(rd1, rd2, imm, jTarget, branch, ins, wd, RegWrite, clk);
    yEX myEx(z, zero, rd1, rd2, imm, op, ALUSrc);
    yDM myDM(memOut, z, rd2, clk, MemRead, MemWrite);
    yWB myWB(wb, z, memOut, Mem2Reg);

    assign wd = wb; 
    yPC myPC(PCin, PC, PCp4, INT, entryPoint, branch, jTarget, zero, isbranch, isjump);

    assign opCode = ins[6:0];
    yC1 myC1(isStype, isRtype, isItype, isLw, isjump, isbranch, opCode);
    yC2 myC2(RegWrite, ALUSrc, MemRead, MemWrite, Mem2Reg, isStype, isRtype, isItype, isLw, isjump, isbranch);

    yC3 myC3(ALUop, isRtype, isbranch);
    assign funct3=ins[14:12];
    yC4 myC4(op, ALUop, funct3);


    wire [15:0] z16;
    wire [7:0] z8;
    wire [3:0] z4;
    wire [1:0] z2;
    wire z1, exp_zero;

    or or16[15:0] (z16, z[15:0], z[31:16]);
    or or8[7:0] (z8, z16[7:0], z16[15:8]);
    or or4[3:0] (z4, z8[3:0], z8[7:4]);
    or or2[1:0] (z2, z4[1:0], z4[3:2]);
    or or1 (z1, z2[1], z2[0]);
    not zero_not(exp_zero, z1);

    initial
    begin

        INT = 1;
        entryPoint = 16'h28; #1;

        repeat (43)
        begin

            clk = 1; #1;
            INT = 0;
            

            clk = 0; #1;


            #4 $display("%8h: rd1=%d rd2=%d imm=%d jTarget=%d z=%d zero=%b wb=%d ALUop=%b funct3=%b op=%b", ins, rd1, rd2, imm, jTarget, z, zero, wb, ALUop, funct3, op);

        end
        $finish;
    end
endmodule