data/full_repos/permissive/524553217/testbench/cpu_im_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_im_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset_pc = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_im_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_im_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #20 $stop;\n        ^\n%Error: data/full_repos/permissive/524553217/testbench/cpu_im_tb.v:33: Cannot find file containing module: \'cpu\'\n    cpu _cpu(clk, reset_pc, im_data, im_addr);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/cpu\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/cpu.v\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/524553217/testbench/cpu_im_tb.v:34: Cannot find file containing module: \'instr_memory\'\n    instr_memory _im(im_addr, im_data);\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_im_tb(

    );

    reg clk;
    reg reset_pc;

    wire [31:0] im_addr;
    wire [31:0] im_data;

    cpu _cpu(clk, reset_pc, im_data, im_addr);
    instr_memory _im(im_addr, im_data);

    initial begin
        clk = 0; reset_pc = 1;
        #1 reset_pc = 0;
        forever begin
            #1 clk = ~clk;
        end
    end

    initial begin
        #20 $stop;
    end


endmodule
module cpu_im_tb(

    );


    reg clk;
    reg reset_pc;

    wire [31:0] im_addr;
    wire [31:0] im_data;

    cpu _cpu(clk, reset_pc, im_data, im_addr);
    instr_memory _im(im_addr, im_data);

    initial begin
        clk = 0; reset_pc = 1;
        #1 reset_pc = 0;
        forever begin
            #1 clk = ~clk;
        end
    end

    initial begin
        #20 $stop;
    end


endmodule