data/full_repos/permissive/509783883/alu/aluTester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/509783883/alu/aluTester.v:27: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509783883/alu/aluTester.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/509783883/alu/aluTester.v:13: Cannot find file containing module: \'eightBitAlu\'\neightBitAlu uut\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509783883/alu,data/full_repos/permissive/509783883/eightBitAlu\n             data/full_repos/permissive/509783883/alu,data/full_repos/permissive/509783883/eightBitAlu.v\n             data/full_repos/permissive/509783883/alu,data/full_repos/permissive/509783883/eightBitAlu.sv\n             eightBitAlu\n             eightBitAlu.v\n             eightBitAlu.sv\n             obj_dir/eightBitAlu\n             obj_dir/eightBitAlu.v\n             obj_dir/eightBitAlu.sv\n%Warning-WIDTH: data/full_repos/permissive/509783883/alu/aluTester.v:32: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'count\' generates 3 bits.\n                                                                       : ... In instance aluTester\n for(count = 0; count < 8; count = count + 1\'b1)\n                      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module aluTester;

reg [2:0] op;
reg [7:0] A;
reg [7:0] B;

wire [7:0] C;

reg [2:0] count = 3'd0;

eightBitAlu uut
(
.op(op),
.A(A),
.B(B),
.C(C)
);

initial
begin
	op = 3'b0;
	A  = 8'd0;
	B  = 8'd0;
	
	#100;
	
	A  = 8'h3B;
	B  = 8'hC2;
	
	for(count = 0; count < 8; count = count + 1'b1)
	begin
		op = count;
		#20;
	end
end

endmodule
module aluTester;


reg [2:0] op;
reg [7:0] A;
reg [7:0] B;

wire [7:0] C;

reg [2:0] count = 3'd0;

eightBitAlu uut
(
.op(op),
.A(A),
.B(B),
.C(C)
);

initial
begin
	op = 3'b0;
	A  = 8'd0;
	B  = 8'd0;
	
	#100;
	
	A  = 8'h3B;
	B  = 8'hC2;
	
	for(count = 0; count < 8; count = count + 1'b1)
	begin
		op = count;
		#20;
	end
end

endmodule