data/full_repos/permissive/525152535/DFFSE.v
data/verilator_xmls/e96a1e75-ce7c-4ae8-b52e-bf4eca5a1452.xml
module DFFSE
#(
    parameter INIT = 1'b1
)
(
    input  CLK,
    input  CE,
    input  SET,
    input  D,
    output Q
);

    reg _r_Q;

    initial begin
        _r_Q = INIT;
    end

    always @(posedge CLK) begin
    
        if (SET) begin
            _r_Q <= 1'b1;
        end
        else if (CE) begin
            _r_Q <= D;
        end
    end

    assign Q = _r_Q;

endmodule
module DFFSE
#(
    parameter INIT = 1'b1
)
(
    input  CLK,
    input  CE,
    input  SET,
    input  D,
    output Q
);


    reg _r_Q;

    initial begin
        _r_Q = INIT;
    end

    always @(posedge CLK) begin
    
        if (SET) begin
            _r_Q <= 1'b1;
        end
        else if (CE) begin
            _r_Q <= D;
        end
    end

    assign Q = _r_Q;

endmodule