data/full_repos/permissive/528287433/NValuesAdder.v
data/verilator_xmls/924a0bc4-42da-4fab-8fd8-e9578c607037.xml
module DecoupledAdder(
  input         clock,
  input         reset,
  input  [31:0] input_bits_op1,
  input  [31:0] input_bits_op2,
  output [31:0] output_bits_res
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [31:0] x;
  reg [31:0] y;
  reg  busy;
  assign output_bits_res = x + y;
  always @(posedge clock) begin
    if (!(busy)) begin
      x <= input_bits_op1;
    end
    if (!(busy)) begin
      y <= input_bits_op2;
    end
    if (reset) begin
      busy <= 1'h0;
    end else if (!(busy)) begin
      busy <= 1'h1;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  busy = _RAND_2[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module DecoupledAdder(
  input         clock,
  input         reset,
  input  [31:0] input_bits_op1,
  input  [31:0] input_bits_op2,
  output [31:0] output_bits_res
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [31:0] x;
  reg [31:0] y;
  reg  busy;
  assign output_bits_res = x + y;
  always @(posedge clock) begin
    if (!(busy)) begin
      x <= input_bits_op1;
    end
    if (!(busy)) begin
      y <= input_bits_op2;
    end
    if (reset) begin
      busy <= 1'h0;
    end else if (!(busy)) begin
      busy <= 1'h1;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  busy = _RAND_2[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule