data/full_repos/permissive/530250155/verilog/rtl/DFFRAM/wrapper/RAM32.v
data/verilator_xmls/e329dc9a-abd2-4dc3-a799-e008297b11a5.xml
module RAM32 (CLK,
    EN0,
    VGND,
    VPWR,
    A0,
    Di0,
    Do0,
    WE0);
 input CLK;
 input EN0;
 input VGND;
 input VPWR;
 input [4:0] A0;
 input [31:0] Di0;
 output [31:0] Do0;
 input [3:0] WE0;
endmodule
module RAM32 (CLK,
    EN0,
    VGND,
    VPWR,
    A0,
    Di0,
    Do0,
    WE0);

 input CLK;
 input EN0;
 input VGND;
 input VPWR;
 input [4:0] A0;
 input [31:0] Di0;
 output [31:0] Do0;
 input [3:0] WE0;
endmodule