data/full_repos/permissive/46343463/src/Registers.v
data/verilator_xmls/0f09af91-0e18-4424-ab8b-acbfa6e2b66c.xml
module Registers #(parameter width=32, size=32) (
    input					clk,
	input		[4:0]		Rs_addr, Rt_addr,
	output reg	[width-1:0]	Rs_data, Rt_data,
	input					we,
	input		[4:0]		Rd_addr,
	input		[width-1:0]	Rd_data
);
	
	integer i;


	reg     [31:0]      register        [0:31];


	initial begin
		for(i = 0; i < size; i = i+1)
			register[i] = {width{1'b0}};
	end
	

	always @ (posedge clk) begin  
		Rs_data <= register[Rs_addr];
		Rt_data <= register[Rt_addr];
	end


	always @ (posedge clk) begin
    	if(we)
    	    register[Rd_addr] = Rd_data;
	end
   
endmodule
module Registers #(parameter width=32, size=32) (
    input					clk,
	input		[4:0]		Rs_addr, Rt_addr,
	output reg	[width-1:0]	Rs_data, Rt_data,
	input					we,
	input		[4:0]		Rd_addr,
	input		[width-1:0]	Rd_data
);

	
	integer i;


	reg     [31:0]      register        [0:31];


	initial begin
		for(i = 0; i < size; i = i+1)
			register[i] = {width{1'b0}};
	end
	

	always @ (posedge clk) begin  
		Rs_data <= register[Rs_addr];
		Rt_data <= register[Rt_addr];
	end


	always @ (posedge clk) begin
    	if(we)
    	    register[Rd_addr] = Rd_data;
	end
   
endmodule