data/full_repos/permissive/441359809/src/yosys/tests/simple/values.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/values.v:33: Too many digits for 16 bit number: 16\'h123abc\n  4\'b1001: y = 16\'h123abc;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/values.v:34: Too many digits for 16 bit number: 16\'o1234567\n  4\'b1010: y = 16\'o1234567;\n               ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/values.v:35: Value too large for 16 bit number: 3456789\n  4\'b1011: y = 16\'d3456789;\n               ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module test_signed(a, b, c, d, y);

input [3:0] a, b, c;
input signed [3:0] d;
output reg [7:0] y;

always @* begin
	if (a && b)
		y = c;
	else
		y = d;
end

endmodule
module test_signed(a, b, c, d, y);


input [3:0] a, b, c;
input signed [3:0] d;
output reg [7:0] y;

always @* begin
	if (a && b)
		y = c;
	else
		y = d;
end

endmodule