data/full_repos/permissive/448780010/code/wb_stage.v
1: b'%Error: data/full_repos/permissive/448780010/code/wb_stage.v:1: Cannot find include file: mycpu.h\n`include "mycpu.h" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.v\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.sv\n             mycpu.h\n             mycpu.h.v\n             mycpu.h.sv\n             obj_dir/mycpu.h\n             obj_dir/mycpu.h.v\n             obj_dir/mycpu.h.sv\n%Error: data/full_repos/permissive/448780010/code/wb_stage.v:10: Define or directive not defined: \'`MS_TO_WS_BUS_WD\'\n    input  [`MS_TO_WS_BUS_WD -1:0]  ms_to_ws_bus  ,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/wb_stage.v:12: Define or directive not defined: \'`WS_TO_RF_BUS_WD\'\n    output [`WS_TO_RF_BUS_WD -1:0]  ws_to_rf_bus  ,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/wb_stage.v:16: Define or directive not defined: \'`RAW_BUS_WD\'\n    output  [`RAW_BUS_WD      -1:0] raw_ws_bus     ,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/wb_stage.v:27: Define or directive not defined: \'`MS_TO_WS_BUS_WD\'\nreg [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r;\n     ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module wb_stage(
    input                           clk           ,
    input                           reset         ,

    output                          ws_allowin    ,

    input                           ms_to_ws_valid,
    input  [`MS_TO_WS_BUS_WD -1:0]  ms_to_ws_bus  ,

    output [`WS_TO_RF_BUS_WD -1:0]  ws_to_rf_bus  ,

    output                          ws_to_es_valid,

    output  [`RAW_BUS_WD      -1:0] raw_ws_bus     ,

    output [31:0] debug_wb_pc     ,
    output [ 3:0] debug_wb_rf_wen ,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
);

reg         ws_valid;
wire        ws_ready_go;

reg [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r;
wire        ws_gr_we;
wire [ 4:0] ws_dest;
wire [31:0] ws_final_result;
wire [31:0] ws_pc;
assign {ws_gr_we       ,
        ws_dest        ,
        ws_final_result,
        ws_pc
       } = ms_to_ws_bus_r;

wire        rf_we;
wire [4 :0] rf_waddr;
wire [31:0] rf_wdata;
assign ws_to_rf_bus = {rf_we   ,
                       rf_waddr,
                       rf_wdata
                      };

wire   raw_ws_valid;
assign raw_ws_valid = ws_gr_we & ws_valid;
assign raw_ws_bus = {raw_ws_valid   ,
                     ws_dest        ,
                     ws_final_result
                    };
assign ws_to_es_valid = ws_valid;
assign ws_ready_go = 1'b1;
assign ws_allowin  = !ws_valid || ws_ready_go;
always @(posedge clk) begin
    if (reset) begin
        ws_valid <= 1'b0;
    end
    else if (ws_allowin) begin
        ws_valid <= ms_to_ws_valid;
    end

    if (ms_to_ws_valid && ws_allowin) begin
        ms_to_ws_bus_r <= ms_to_ws_bus;
    end
end

assign rf_we    = ws_gr_we&&ws_valid;
assign rf_waddr = ws_dest;
assign rf_wdata = ws_final_result;


assign debug_wb_pc       = ws_pc;
assign debug_wb_rf_wen   = {4{rf_we}};
assign debug_wb_rf_wnum  = ws_dest;
assign debug_wb_rf_wdata = ws_final_result;

endmodule
module wb_stage(
    input                           clk           ,
    input                           reset         ,

    output                          ws_allowin    ,

    input                           ms_to_ws_valid,
    input  [`MS_TO_WS_BUS_WD -1:0]  ms_to_ws_bus  ,

    output [`WS_TO_RF_BUS_WD -1:0]  ws_to_rf_bus  ,

    output                          ws_to_es_valid,

    output  [`RAW_BUS_WD      -1:0] raw_ws_bus     ,

    output [31:0] debug_wb_pc     ,
    output [ 3:0] debug_wb_rf_wen ,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
);


reg         ws_valid;
wire        ws_ready_go;

reg [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r;
wire        ws_gr_we;
wire [ 4:0] ws_dest;
wire [31:0] ws_final_result;
wire [31:0] ws_pc;
assign {ws_gr_we       ,
        ws_dest        ,
        ws_final_result,
        ws_pc
       } = ms_to_ws_bus_r;

wire        rf_we;
wire [4 :0] rf_waddr;
wire [31:0] rf_wdata;
assign ws_to_rf_bus = {rf_we   ,
                       rf_waddr,
                       rf_wdata
                      };

wire   raw_ws_valid;
assign raw_ws_valid = ws_gr_we & ws_valid;
assign raw_ws_bus = {raw_ws_valid   ,
                     ws_dest        ,
                     ws_final_result
                    };
assign ws_to_es_valid = ws_valid;
assign ws_ready_go = 1'b1;
assign ws_allowin  = !ws_valid || ws_ready_go;
always @(posedge clk) begin
    if (reset) begin
        ws_valid <= 1'b0;
    end
    else if (ws_allowin) begin
        ws_valid <= ms_to_ws_valid;
    end

    if (ms_to_ws_valid && ws_allowin) begin
        ms_to_ws_bus_r <= ms_to_ws_bus;
    end
end

assign rf_we    = ws_gr_we&&ws_valid;
assign rf_waddr = ws_dest;
assign rf_wdata = ws_final_result;


assign debug_wb_pc       = ws_pc;
assign debug_wb_rf_wen   = {4{rf_we}};
assign debug_wb_rf_wnum  = ws_dest;
assign debug_wb_rf_wdata = ws_final_result;

endmodule