data/full_repos/permissive/463439324/decap/f0_adds_g0.v
data/verilator_xmls/5e2be2c6-46a0-4ea4-a13c-c2f0b92cb93a.xml
module f0_adds_g0(f0,f1,g0,g1,c0,c1);

input f0;
input f1;
input g0;
input g1;

output c0;
output c1;




assign c0 = (f0 ^ g0) | (f1 & g1) | ((!f1) & f0 & (!g1));
assign c1 = ((!f0) & g1) | ((!f1) & f0 & (!g1) & g0) | (f1 & (!g0));

endmodule
module f0_adds_g0(f0,f1,g0,g1,c0,c1);


input f0;
input f1;
input g0;
input g1;

output c0;
output c1;




assign c0 = (f0 ^ g0) | (f1 & g1) | ((!f1) & f0 & (!g1));
assign c1 = ((!f0) & g1) | ((!f1) & f0 & (!g1) & g0) | (f1 & (!g0));

endmodule