data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/circular_fifo_rev1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/circular_fifo_rev1.v:46: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                            : ... In instance circular_fifo_rev1\nassign  empty       =   ( data_counter == 1\'b0 ) ? 1\'b1 : 1\'b0;            \n                                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/circular_fifo_rev1.v:114: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                             : ... In instance circular_fifo_rev1\n        data_out <= \'hx; \n                 ^~\n%Error: Exiting due to 2 warning(s)\n'
module circular_fifo_rev1
    #(  parameter   DATA_WIDTH  =   8,
        parameter   ADDR_WIDTH  =   2,
        parameter   RAM_DEPTH   =   1<< ADDR_WIDTH )
(



    input                               clk,
    input                               reset,
    input                               wr_cs,
    input                               rd_cs,
    input           [DATA_WIDTH-1:0]    data_in,
    input										rd_en,
    input                               wr_en,




    output  reg     [DATA_WIDTH-1:0]    data_out,
    output  wire                        full,
    output  wire                        empty,
	 

	 output wire [ADDR_WIDTH:0]			 data_counter_out,
	 output wire [ADDR_WIDTH-1:0]   		 wr_pointer_out, 
	 output wire [ADDR_WIDTH-1:0]   		 rd_pointer_out 	
);




reg     [ADDR_WIDTH-1:0]    wr_pointer;
reg     [ADDR_WIDTH-1:0]    rd_pointer;
reg     [DATA_WIDTH-1:0]    memory [0:RAM_DEPTH-1];
reg     [ADDR_WIDTH:0]      data_counter;






assign  full        =   ( data_counter == ( RAM_DEPTH ) ) ? 1'b1 : 1'b0;
assign  empty       =   ( data_counter == 1'b0 ) ? 1'b1 : 1'b0;



assign data_counter_out = data_counter;
assign wr_pointer_out = wr_pointer;
assign rd_pointer_out = rd_pointer;



always @ ( posedge clk or posedge reset )
begin: WRITE_POINTER
    if ( reset )
    begin
        wr_pointer  <=  'd0;

    end
    else 
    begin
        if ( wr_cs && wr_en && !full)
            wr_pointer  <=  wr_pointer + 'd1;
        else 
        	wr_pointer 	<=	wr_pointer;
			

    end
end


always @ ( posedge clk or posedge reset )
begin: READ_POINTER
    if ( reset )
    begin
        rd_pointer  <=  'd0;
    end
    else
    begin
        if ( rd_cs && rd_en && !empty)
            rd_pointer  <=  rd_pointer + 'd1;
        else 
        	rd_pointer 	<=	rd_pointer;
    end
end


always @ ( posedge clk )
begin: DATA_WRITE
    if ( wr_cs && wr_en && (  data_counter != RAM_DEPTH  ))


		memory[wr_pointer] <= data_in;
    else 
    	memory[wr_pointer] <= memory[wr_pointer]; 
end


always @ ( posedge clk )
begin: DATA_READ
    if ( rd_cs && rd_en ) 


        data_out <= memory[rd_pointer];
    else
        data_out <= 'hx; 
end


always @ ( posedge clk or posedge reset )
begin: DATA_COUNTER
    if ( reset )
    begin
        data_counter    <=  'd0;
    end
    else
    begin
        if (!( wr_cs && wr_en ) && ( rd_cs && rd_en ) && !empty)



            data_counter <= data_counter - 1;
        else if ( ( wr_cs && wr_en ) && ! ( rd_cs && rd_en ) && ( data_counter != RAM_DEPTH  ))


            data_counter <= data_counter + 1;
        else

            data_counter <= data_counter;
    end
end

endmodule
module circular_fifo_rev1
    #(  parameter   DATA_WIDTH  =   8,
        parameter   ADDR_WIDTH  =   2,
        parameter   RAM_DEPTH   =   1<< ADDR_WIDTH )
(



    input                               clk,
    input                               reset,
    input                               wr_cs,
    input                               rd_cs,
    input           [DATA_WIDTH-1:0]    data_in,
    input										rd_en,
    input                               wr_en,




    output  reg     [DATA_WIDTH-1:0]    data_out,
    output  wire                        full,
    output  wire                        empty,
	 

	 output wire [ADDR_WIDTH:0]			 data_counter_out,
	 output wire [ADDR_WIDTH-1:0]   		 wr_pointer_out, 
	 output wire [ADDR_WIDTH-1:0]   		 rd_pointer_out 	
);





reg     [ADDR_WIDTH-1:0]    wr_pointer;
reg     [ADDR_WIDTH-1:0]    rd_pointer;
reg     [DATA_WIDTH-1:0]    memory [0:RAM_DEPTH-1];
reg     [ADDR_WIDTH:0]      data_counter;






assign  full        =   ( data_counter == ( RAM_DEPTH ) ) ? 1'b1 : 1'b0;
assign  empty       =   ( data_counter == 1'b0 ) ? 1'b1 : 1'b0;



assign data_counter_out = data_counter;
assign wr_pointer_out = wr_pointer;
assign rd_pointer_out = rd_pointer;



always @ ( posedge clk or posedge reset )
begin: WRITE_POINTER
    if ( reset )
    begin
        wr_pointer  <=  'd0;

    end
    else 
    begin
        if ( wr_cs && wr_en && !full)
            wr_pointer  <=  wr_pointer + 'd1;
        else 
        	wr_pointer 	<=	wr_pointer;
			

    end
end


always @ ( posedge clk or posedge reset )
begin: READ_POINTER
    if ( reset )
    begin
        rd_pointer  <=  'd0;
    end
    else
    begin
        if ( rd_cs && rd_en && !empty)
            rd_pointer  <=  rd_pointer + 'd1;
        else 
        	rd_pointer 	<=	rd_pointer;
    end
end


always @ ( posedge clk )
begin: DATA_WRITE
    if ( wr_cs && wr_en && (  data_counter != RAM_DEPTH  ))


		memory[wr_pointer] <= data_in;
    else 
    	memory[wr_pointer] <= memory[wr_pointer]; 
end


always @ ( posedge clk )
begin: DATA_READ
    if ( rd_cs && rd_en ) 


        data_out <= memory[rd_pointer];
    else
        data_out <= 'hx; 
end


always @ ( posedge clk or posedge reset )
begin: DATA_COUNTER
    if ( reset )
    begin
        data_counter    <=  'd0;
    end
    else
    begin
        if (!( wr_cs && wr_en ) && ( rd_cs && rd_en ) && !empty)



            data_counter <= data_counter - 1;
        else if ( ( wr_cs && wr_en ) && ! ( rd_cs && rd_en ) && ( data_counter != RAM_DEPTH  ))


            data_counter <= data_counter + 1;
        else

            data_counter <= data_counter;
    end
end

endmodule