data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module mainCKT(x,a,b,c,d,y,PP1,PP2,PP3,PP4,PP5,PP6,PP11,PP22,PP33,PP44,Cin0,S01,C01,Cin1,S11,C11,Cin2,S21,C21,out01,c01,Cin3,S31,C31,Cin4,S41,C41,out11,cout1,Cout1,c11,Cx01,Cx11,Cx21,Cx31,Cx41,Sout1,Sout2,Sout3,P1,Q1,R1,S1,P2,Q2,R2,S2,P3,Q3,R3,S3,p,l);
  input [7:0]x,y;
  input [8:0]d;
  input Cin0,Cin1,Cin2,Cin3,Cin4;
  inout [9:0]PP1;
  inout [8:0]PP2,PP3,PP4;
  inout [9:0]PP11,PP22;
  inout [8:0]PP33,PP44;
  inout [10:0]PP5,PP6;
  inout [8:0]Sout1;
  inout [9:0]Sout2;
  inout [10:0]Sout3;
  inout Cout1,Cout2,Cout3;
  inout C01,C11,C21,C31,C41;
  inout C02,C12,C22,C32,C42;
  inout C03,C13,C23,C33,C43;
  inout [1:0]S01;
  inout [2:0]S11,S21;
  inout [3:0]S31,S41;
  inout [2:0]S02;
  inout [2:0]S12,S22;
  inout [3:0]S32,S42;
  inout [2:0]S03;
  inout [3:0]S13,S23;
  inout [3:0]S33,S43;
  inout [3:0]out01;
  inout [4:0]out11;
  inout [3:0]out02;
  inout [4:0]out12;
  inout [4:0]out03;
  inout [4:0]out13;
  output [8:0]l;
  inout cout1,cout2,cout3;
  inout c01,c11,c02,c12,c03,c13;
  output [2:0]Cx01;
  output [3:0]Cx11,Cx21;
  output [4:0]Cx31,Cx41;
  output [3:0]Cx02;
  output [3:0]Cx12,Cx22;
  output [4:0]Cx32,Cx42;
  output [3:0]Cx03;
  output [4:0]Cx13,Cx23;
  output [4:0]Cx33,Cx43;
  output [8:0]a,c;
  output [8:0]b;
  output [8:0]P1,Q1,R1,S1;
  output [8:0]P2,Q2,R2,S2;
  output [8:0]P3,Q3,R3,S3;
  output [14:0]p;
  B2C1 a1(x,b);
  assign l={x[7],x};
  assign a=l<<<1;
  assign c=b<<<1;
  mux4x1 a2(d,l,c,b,y[0],y[1],PP1);
  assign PP11={{2{PP1[9]}},PP1[9:2]};
  assign p[1:0]= {PP1[1],PP1[0]};
  mainckt b1(y[1],y[2],y[3],P1,Q1,R1,S1,x,a,b,c,PP2,l);
  mainckt b2(y[3],y[4],y[5],P2,Q2,R2,S2,x,a,b,c,PP3,l);
  mainckt b3(y[5],y[6],y[7],P3,Q3,R3,S3,x,a,b,c,PP4,l);
  assign PP22={{1{PP2[8]}},PP2};
  assign PP33={{2{PP3[8]}},PP3[8:2]};
  assign PP44=PP4[8:0];
  
  mainckt1 d1(PP44[1:0],PP33[1:0],Cin0,S01,C01,PP44[4:2],PP33[4:2],Cin1,S11,C11,PP44[4:2],PP33[4:2],Cin2,S21,C21,out01,c01,PP44[8:5],PP33[8:5],Cin3,S31,C31,PP44[8:5],PP33[8:5],Cin4,S41,C41,out11,cout1,Sout1,Cout1,c11,Cx01,Cx11,Cx21,Cx31,Cx41);
  
  mainckt2 d2(PP22[2:0],PP11[2:0],Cin0,S02,C02,PP22[5:3],PP11[5:3],Cin1,S12,C12,PP22[5:3],PP11[5:3],Cin2,S22,C22,out02,c02,PP22[9:6],PP11[9:6],Cin3,S32,C32,PP22[9:6],PP11[9:6],Cin4,S42,C42,out12,cout2,Sout2,Cout2,c12,Cx02,Cx12,Cx22,Cx32,Cx42);
  
  assign p[3:2]=Sout2[1:0];
  assign PP5={Sout1,PP3[1:0]};
  assign PP6={{3{Sout2[9]}},Sout2[9:2]};
  
  mainckt3 d3(PP5[2:0],PP6[2:0],Cin0,S03,C03,PP5[6:3],PP6[6:3],Cin1,S13,C13,PP5[6:3],PP6[6:3],Cin2,S23,C23,out03,c03,PP5[10:7],PP6[10:7],Cin3,S33,C33,PP5[10:7],PP6[10:7],Cin4,S43,C43,out13,cout3,Sout3,Cout3,c13,Cx03,Cx13,Cx23,Cx33,Cx43);
  
 assign p[14:4]=Sout3;
  
endmodule
module mainCKT(x,a,b,c,d,y,PP1,PP2,PP3,PP4,PP5,PP6,PP11,PP22,PP33,PP44,Cin0,S01,C01,Cin1,S11,C11,Cin2,S21,C21,out01,c01,Cin3,S31,C31,Cin4,S41,C41,out11,cout1,Cout1,c11,Cx01,Cx11,Cx21,Cx31,Cx41,Sout1,Sout2,Sout3,P1,Q1,R1,S1,P2,Q2,R2,S2,P3,Q3,R3,S3,p,l);

  input [7:0]x,y;
  input [8:0]d;
  input Cin0,Cin1,Cin2,Cin3,Cin4;
  inout [9:0]PP1;
  inout [8:0]PP2,PP3,PP4;
  inout [9:0]PP11,PP22;
  inout [8:0]PP33,PP44;
  inout [10:0]PP5,PP6;
  inout [8:0]Sout1;
  inout [9:0]Sout2;
  inout [10:0]Sout3;
  inout Cout1,Cout2,Cout3;
  inout C01,C11,C21,C31,C41;
  inout C02,C12,C22,C32,C42;
  inout C03,C13,C23,C33,C43;
  inout [1:0]S01;
  inout [2:0]S11,S21;
  inout [3:0]S31,S41;
  inout [2:0]S02;
  inout [2:0]S12,S22;
  inout [3:0]S32,S42;
  inout [2:0]S03;
  inout [3:0]S13,S23;
  inout [3:0]S33,S43;
  inout [3:0]out01;
  inout [4:0]out11;
  inout [3:0]out02;
  inout [4:0]out12;
  inout [4:0]out03;
  inout [4:0]out13;
  output [8:0]l;
  inout cout1,cout2,cout3;
  inout c01,c11,c02,c12,c03,c13;
  output [2:0]Cx01;
  output [3:0]Cx11,Cx21;
  output [4:0]Cx31,Cx41;
  output [3:0]Cx02;
  output [3:0]Cx12,Cx22;
  output [4:0]Cx32,Cx42;
  output [3:0]Cx03;
  output [4:0]Cx13,Cx23;
  output [4:0]Cx33,Cx43;
  output [8:0]a,c;
  output [8:0]b;
  output [8:0]P1,Q1,R1,S1;
  output [8:0]P2,Q2,R2,S2;
  output [8:0]P3,Q3,R3,S3;
  output [14:0]p;
  B2C1 a1(x,b);
  assign l={x[7],x};
  assign a=l<<<1;
  assign c=b<<<1;
  mux4x1 a2(d,l,c,b,y[0],y[1],PP1);
  assign PP11={{2{PP1[9]}},PP1[9:2]};
  assign p[1:0]= {PP1[1],PP1[0]};
  mainckt b1(y[1],y[2],y[3],P1,Q1,R1,S1,x,a,b,c,PP2,l);
  mainckt b2(y[3],y[4],y[5],P2,Q2,R2,S2,x,a,b,c,PP3,l);
  mainckt b3(y[5],y[6],y[7],P3,Q3,R3,S3,x,a,b,c,PP4,l);
  assign PP22={{1{PP2[8]}},PP2};
  assign PP33={{2{PP3[8]}},PP3[8:2]};
  assign PP44=PP4[8:0];
  
  mainckt1 d1(PP44[1:0],PP33[1:0],Cin0,S01,C01,PP44[4:2],PP33[4:2],Cin1,S11,C11,PP44[4:2],PP33[4:2],Cin2,S21,C21,out01,c01,PP44[8:5],PP33[8:5],Cin3,S31,C31,PP44[8:5],PP33[8:5],Cin4,S41,C41,out11,cout1,Sout1,Cout1,c11,Cx01,Cx11,Cx21,Cx31,Cx41);
  
  mainckt2 d2(PP22[2:0],PP11[2:0],Cin0,S02,C02,PP22[5:3],PP11[5:3],Cin1,S12,C12,PP22[5:3],PP11[5:3],Cin2,S22,C22,out02,c02,PP22[9:6],PP11[9:6],Cin3,S32,C32,PP22[9:6],PP11[9:6],Cin4,S42,C42,out12,cout2,Sout2,Cout2,c12,Cx02,Cx12,Cx22,Cx32,Cx42);
  
  assign p[3:2]=Sout2[1:0];
  assign PP5={Sout1,PP3[1:0]};
  assign PP6={{3{Sout2[9]}},Sout2[9:2]};
  
  mainckt3 d3(PP5[2:0],PP6[2:0],Cin0,S03,C03,PP5[6:3],PP6[6:3],Cin1,S13,C13,PP5[6:3],PP6[6:3],Cin2,S23,C23,out03,c03,PP5[10:7],PP6[10:7],Cin3,S33,C33,PP5[10:7],PP6[10:7],Cin4,S43,C43,out13,cout3,Sout3,Cout3,c13,Cx03,Cx13,Cx23,Cx33,Cx43);
  
 assign p[14:4]=Sout3;
  
endmodule