data/full_repos/permissive/52900389/Universal_Binary_Counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52900389/Universal_Binary_Counter.v:33: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                 : ... In instance Universal_Binary_Counter\n  out <= 8\'b0;\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52900389/Universal_Binary_Counter.v:39: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'out\' generates 4 bits.\n                                                                                 : ... In instance Universal_Binary_Counter\n if (out==16) out <=4 \'b0;\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module Universal_Binary_Counter(	
out     ,
clk     ,
rst
);

output reg [3:0] out;
input  clk, rst;
reg bandera;
	 
always @(posedge clk, posedge rst)
if (rst) begin
  out <= 8'b0;
  bandera = 0;
end 
else if (bandera == 0) 
	begin
	out <= out + 4'b1;
	if (out==16) out <=4 'b0;
	end
else if (bandera==1)
	begin
	out <= out - 4'b1;
	if(out==0) bandera =1;
	end

endmodule
module Universal_Binary_Counter(	
out     ,
clk     ,
rst
);


output reg [3:0] out;
input  clk, rst;
reg bandera;
	 
always @(posedge clk, posedge rst)
if (rst) begin
  out <= 8'b0;
  bandera = 0;
end 
else if (bandera == 0) 
	begin
	out <= out + 4'b1;
	if (out==16) out <=4 'b0;
	end
else if (bandera==1)
	begin
	out <= out - 4'b1;
	if(out==0) bandera =1;
	end

endmodule