data/full_repos/permissive/460328193/ipa_proj_pipe/alu.v
data/verilator_xmls/5b9d9e13-a42f-48bd-be1d-2eece74cde62.xml
module add(sum,carry_overflow,A,B,cin);
	input signed [63:0] A,B;
	input cin;
	output signed [63:0] sum;
	output signed carry_overflow;
	wire [18:0] carry;
	wire [2:0] t1,t2,t3;
	genvar i;
	CLA_FULL c1(sum[3:0],carry[0],A[3:0],B[3:0],cin);
	generate for(i=0;i<14;i=i+1)
		CLA_FULL c2(sum[7+4*i:4+4*i],carry[1+i],A[7+4*i:4+4*i],B[7+4*i:4+4*i],carry[0+i]);
	endgenerate
	CLA_FULL c16(sum[63:60],carry[18],A[63:60],B[63:60],carry[14]);
	generate for(i=0;i<3;i=i+1)
	begin
    		and gate2(t1[i],A[i+60],B[i+60]);
    		and gate3(t2[i],B[i+60],carry[i+14]);
    		and gate4(t3[i],A[i+60],carry[i+14]);
    		or gate5(carry[i+1+14],t1[i],t2[i],t3[i]);
	end
	endgenerate
       	xor(carry_overflow,carry[17],carry[18]);
endmodule
module add(sum,carry_overflow,A,B,cin);

	input signed [63:0] A,B;
	input cin;
	output signed [63:0] sum;
	output signed carry_overflow;
	wire [18:0] carry;
	wire [2:0] t1,t2,t3;
	genvar i;
	CLA_FULL c1(sum[3:0],carry[0],A[3:0],B[3:0],cin);
	generate for(i=0;i<14;i=i+1)
		CLA_FULL c2(sum[7+4*i:4+4*i],carry[1+i],A[7+4*i:4+4*i],B[7+4*i:4+4*i],carry[0+i]);
	endgenerate
	CLA_FULL c16(sum[63:60],carry[18],A[63:60],B[63:60],carry[14]);
	generate for(i=0;i<3;i=i+1)
	begin
    		and gate2(t1[i],A[i+60],B[i+60]);
    		and gate3(t2[i],B[i+60],carry[i+14]);
    		and gate4(t3[i],A[i+60],carry[i+14]);
    		or gate5(carry[i+1+14],t1[i],t2[i],t3[i]);
	end
	endgenerate
       	xor(carry_overflow,carry[17],carry[18]);
endmodule