data/full_repos/permissive/42434302/ivltests/casesynth8.v
data/verilator_xmls/b59db2fd-e4f1-4039-bfa0-1951c9f3bcd4.xml
module mux(

input wire [2:0] sel,
input wire [2:0] i1,
input wire [2:0] i2,
input wire [2:0] i3,
input wire [2:0] i4,
input wire [2:0] i5,
output reg [2:0] o

);

always @* begin
  case (sel)
    0 : o = 0;
    1 : o = i1;
    2 : o = i2;
    3 : o = i3;
   i5 : o = i4;
   default:
     o = 3'bx;
  endcase
end

endmodule
module mux(

input wire [2:0] sel,
input wire [2:0] i1,
input wire [2:0] i2,
input wire [2:0] i3,
input wire [2:0] i4,
input wire [2:0] i5,
output reg [2:0] o

);


always @* begin
  case (sel)
    0 : o = 0;
    1 : o = i1;
    2 : o = i2;
    3 : o = i3;
   i5 : o = i4;
   default:
     o = 3'bx;
  endcase
end

endmodule