data/full_repos/permissive/479997390/src/PipelineRegisters.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/479997390/src/PipelineRegisters.v:28: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'IF_ID\'\nmodule IF_ID (\n       ^~~~~\n                                                                                  : ... Top module \'ID_EX\'\nmodule ID_EX (\n       ^~~~~\n                                                                                  : ... Top module \'EX_MEM\'\nmodule EX_MEM (\n       ^~~~~~\n                                                                                  : ... Top module \'MEM_WB\'\nmodule MEM_WB (\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ID_EX (
  clk,
  Flush,

  RegData1In, RegData2In, Imm32In, 
  FunctIn, RsIn, RtIn, ShamtIn, 

  ALUSrcIn, ALUOpIn, 

  WriteRegAddrIn,


  MemReadIn, MemWriteIn,
  MemToRegIn, RegWriteIn,

  RegData1Out, RegData2Out, Imm32Out, 
  FunctOut, RsOut, RtOut, ShamtOut, 

  ALUSrcOut, ALUOpOut, 

  WriteRegAddrOut,


  MemReadOut, MemWriteOut,
  MemToRegOut, RegWriteOut
);

  input clk, Flush;
  input [31:0] RegData1In, RegData2In, Imm32In;
  input [5:0] FunctIn;
  input [4:0] RsIn, RtIn, ShamtIn;
  input ALUSrcIn;
  input [4:0] ALUOpIn, WriteRegAddrIn;
  input MemReadIn, MemWriteIn, MemToRegIn, RegWriteIn;

  output reg [31:0] RegData1Out, RegData2Out, Imm32Out;
  output reg [5:0] FunctOut;
  output reg [4:0] RsOut, RtOut, ShamtOut;
  output reg ALUSrcOut;
  output reg [4:0] ALUOpOut, WriteRegAddrOut;
  output reg MemReadOut, MemWriteOut, MemToRegOut, RegWriteOut;

  always @(posedge clk) begin
    if (Flush) begin
      RegData1Out <= 0;
      RegData2Out <= 0;
      Imm32Out <= 0;
      FunctOut <= 0;
      RsOut <= 0;
      RtOut <= 0;
      ShamtOut <= 0;
      ALUSrcOut <= 0;
      ALUOpOut <= 0;

      WriteRegAddrOut <= 0;

      MemReadOut <= 0;
      MemWriteOut <= 0;
      MemToRegOut <= 0;
      RegWriteOut <= 0;
    end else begin
      RegData1Out <= RegData1In;
      RegData2Out <= RegData2In;
      Imm32Out <= Imm32In;
      FunctOut <= FunctIn;
      RsOut <= RsIn;
      RtOut <= RtIn;
      ShamtOut <= ShamtIn;
      ALUSrcOut <= ALUSrcIn;
      ALUOpOut <= ALUOpIn;

      WriteRegAddrOut <= WriteRegAddrIn;

      MemReadOut <= MemReadIn;
      MemWriteOut <= MemWriteIn;
      MemToRegOut <= MemToRegIn;
      RegWriteOut <= RegWriteIn;
    end
  end
endmodule
module ID_EX (
  clk,
  Flush,

  RegData1In, RegData2In, Imm32In, 
  FunctIn, RsIn, RtIn, ShamtIn, 

  ALUSrcIn, ALUOpIn, 

  WriteRegAddrIn,


  MemReadIn, MemWriteIn,
  MemToRegIn, RegWriteIn,

  RegData1Out, RegData2Out, Imm32Out, 
  FunctOut, RsOut, RtOut, ShamtOut, 

  ALUSrcOut, ALUOpOut, 

  WriteRegAddrOut,


  MemReadOut, MemWriteOut,
  MemToRegOut, RegWriteOut
);


  input clk, Flush;
  input [31:0] RegData1In, RegData2In, Imm32In;
  input [5:0] FunctIn;
  input [4:0] RsIn, RtIn, ShamtIn;
  input ALUSrcIn;
  input [4:0] ALUOpIn, WriteRegAddrIn;
  input MemReadIn, MemWriteIn, MemToRegIn, RegWriteIn;

  output reg [31:0] RegData1Out, RegData2Out, Imm32Out;
  output reg [5:0] FunctOut;
  output reg [4:0] RsOut, RtOut, ShamtOut;
  output reg ALUSrcOut;
  output reg [4:0] ALUOpOut, WriteRegAddrOut;
  output reg MemReadOut, MemWriteOut, MemToRegOut, RegWriteOut;

  always @(posedge clk) begin
    if (Flush) begin
      RegData1Out <= 0;
      RegData2Out <= 0;
      Imm32Out <= 0;
      FunctOut <= 0;
      RsOut <= 0;
      RtOut <= 0;
      ShamtOut <= 0;
      ALUSrcOut <= 0;
      ALUOpOut <= 0;

      WriteRegAddrOut <= 0;

      MemReadOut <= 0;
      MemWriteOut <= 0;
      MemToRegOut <= 0;
      RegWriteOut <= 0;
    end else begin
      RegData1Out <= RegData1In;
      RegData2Out <= RegData2In;
      Imm32Out <= Imm32In;
      FunctOut <= FunctIn;
      RsOut <= RsIn;
      RtOut <= RtIn;
      ShamtOut <= ShamtIn;
      ALUSrcOut <= ALUSrcIn;
      ALUOpOut <= ALUOpIn;

      WriteRegAddrOut <= WriteRegAddrIn;

      MemReadOut <= MemReadIn;
      MemWriteOut <= MemWriteIn;
      MemToRegOut <= MemToRegIn;
      RegWriteOut <= RegWriteIn;
    end
  end
endmodule