data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv
1: b"%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:89: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));  \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500947188/rtl/back1,data/full_repos/permissive/500947188/ttl_74273_sync\n             data/full_repos/permissive/500947188/rtl/back1,data/full_repos/permissive/500947188/ttl_74273_sync.v\n             data/full_repos/permissive/500947188/rtl/back1,data/full_repos/permissive/500947188/ttl_74273_sync.sv\n             ttl_74273_sync\n             ttl_74273_sync.v\n             ttl_74273_sync.sv\n             obj_dir/ttl_74273_sync\n             obj_dir/ttl_74273_sync.v\n             obj_dir/ttl_74273_sync.sv\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:96: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        ); \n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:115: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync d13\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:128: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync d12\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:147: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));  \n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:169: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:172: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:175: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:178: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:202: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(12)) L3\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:235: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(12)) L4\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:275: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync H2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D0reg), .Q(H2_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:279: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync G2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H2_Q), .Q(G2_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:282: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync F2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G2_Q), .Q(F2_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:286: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync H3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D1reg), .Q(H3_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:290: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync G3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H3_Q), .Q(G3_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:293: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync F3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G3_Q), .Q(F3_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:332: Cannot find file containing module: 'eprom_32K'\n        eprom_32K BACK1_ROM\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:348: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync B1(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:402: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync B2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(ROM_DATA), .Q(B2_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/back1/TNKIIICore_Back1_sync.sv:447: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) A2 (.Enable_bar(1'b0), .Select((swap_px ? ~A2_S : A2_S)),\n    ^~~~~~~~~\n%Error: Exiting due to 21 error(s)\n"
module TNKIIICore_Back1_sync(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,
    input wire RESET,

    input wire INV,
    input wire INVn,

    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire B1SY,
    input wire B1SX,


    input wire [7:0] hack_settings,
    input wire [3:0] dbg_B1Voffset, 
    input wire swap_px,

    input wire B1Y8,
    input wire B1X8,


    input wire V_C,


    input wire H8,
    input wire [4:0] Y,
    input wire H2,
    input wire H1,
    input wire H0,
    input wire [7:0] X, 

    input wire [12:0] VA,
    input wire BACK1_VRAM_CSn,
    

    input wire VFLGn,


    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,


    input wire CK1n,
    input wire LA,
    input wire VLK,



    input wire B1_COLBK,
    input wire JMP_B1D7,
    output logic [7:0] B1D
);


    logic B1B0,B1B1;


    assign B1B0 = (!VA[0] && !BACK1_VRAM_CSn) ? 1'b0 : 1'b1;
    assign B1B1 = ( VA[0] && !BACK1_VRAM_CSn) ? 1'b0 : 1'b1;


    logic [2:0] XOR_YSR;
    logic [7:0] B1Y;
    assign XOR_YSR[2] = VD_in[2] ^ INVn;
    assign XOR_YSR[1] = VD_in[1] ^ INVn;
    assign XOR_YSR[0] = VD_in[0] ^ INVn;


    reg [7:0] vdin_r;
    always @(posedge clk) begin
        vdin_r <= {VD_in[7:3],XOR_YSR};
    end

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));

    logic [8:0] B1H;
    logic [2:0] B1Hn;
    logic c14_dum3;
    logic [1:0] c12_dum;

    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        );






    logic [5:0] const_plus1d;  
    assign const_plus1d = (hack_settings[0]) ? 6'b00_0001 : 6'b00_0000;
    assign B1H[8:3] = {B1Y8,B1Y[7:3]} + {H8,Y} + const_plus1d;


    assign B1Hn[0] = ~B1H[0];
    assign B1Hn[1] = ~B1H[1];
    assign B1Hn[2] = ~B1H[2];

    logic [8:0] B1HQ;

    logic [5:0] d13_q;
    ttl_74174_sync d13
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),

        .Clr_n(1'b1),
        .D({3'b111,B1Hn}),
        .Q(d13_q)
    );
    assign B1HQ[2:0] = d13_q[2:0];

    logic [5:0] d12_q;
    ttl_74174_sync d12
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),

        .Clr_n(1'b1),
        .D(B1H[8:3]),
        .Q(d12_q)
    );
    assign B1HQ[8:3] = d12_q[5:0];


    reg [7:0] vdinX_r;
     always @(posedge clk) begin
        vdinX_r <= VD_in;
    end

    logic [7:0] B1X;
    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));
    logic [8:0] B1V;







    logic [8:0] const_minus40d;
    assign const_minus40d = (hack_settings[0]) ? 9'b1_1101_1000 : 9'b0_0000_0000;
    assign B1V = {B1X8,B1X} + {1'b0,X} + const_minus40d;





    logic L4_CSn, L3_CSn;
    logic [12:0] A;
    logic dum1;


    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({1'b1,1'b1,VA[12],B1HQ[8],VA[11],B1HQ[7],VA[10],B1HQ[6]}), .Y(A[12:9]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[9],B1HQ[5],VA[8],B1HQ[4],VA[7],B1HQ[3],VA[6],B1V[8]}), .Y(A[8:5]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[5],B1V[7],VA[4],B1V[6],VA[3],B1V[5],VA[2],B1V[4]}), .Y(A[4:1]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[1],B1V[3],B1B0,VFLGn,B1B1,VFLGn,1'b1,1'b1}), .Y({A[0],L3_CSn,L4_CSn,dum1}));

    logic BACK1_SEL0, BACK1_SEL1;
    assign BACK1_SEL0 = ~(B1B0 | VDG);
    assign BACK1_SEL1 = ~(B1B1 | VDG);


    logic [7:0] D0, D1, Din0, Din1;
    assign Din0 = (BACK1_SEL0 && VRD) ?  VD_in : 8'hFF;
    assign Din1 = (BACK1_SEL1 && VRD) ?  VD_in : 8'hFF;


    logic [7:0] back1_0_Q, back1_1_Q;
    logic [7:0] D0reg, D1reg;
    logic L4_CS, L3_CS;

    assign L3_CS = ~L3_CSn;
    assign L4_CS = ~L4_CSn;

    logic [11:0] h12_addr1;
    assign h12_addr1 = {B1HQ[8:3],B1V[8:3]};


    SRAM_dual_sync #(.ADDR_WIDTH(12)) L3
    (
        .ADDR0({VA[12:1]}), 
        .clk0(clk), 
        .cen0(L3_CS), 
        .we0(~VWE), 
        .DATA0(Din0), 
        .Q0(back1_0_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(D0reg)
    );
	 

















    SRAM_dual_sync #(.ADDR_WIDTH(12)) L4
    (
        .ADDR0({VA[12:1]}), 
        .clk0(clk), 
        .cen0(L4_CS), 
        .we0(~VWE), 
        .DATA0(Din1), 
        .Q0(back1_1_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(D1reg)
    );















    assign D0 = (!VOE) ? back1_0_Q : 8'hff;
    assign D1 = (!VOE) ? back1_1_Q : 8'hff;
    assign VD_out = (BACK1_SEL0 && !VRD) ? D0 : ((BACK1_SEL1 && !VRD) ? D1 : 8'hff);






    logic [7:0] H2_Q;
    ttl_74273_sync H2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D0reg), .Q(H2_Q));


    logic [7:0] G2_Q;
    ttl_74273_sync G2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H2_Q), .Q(G2_Q));

    logic [7:0] F2_Q;
    ttl_74273_sync F2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G2_Q), .Q(F2_Q));


    logic [7:0] H3_Q;
    ttl_74273_sync H3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D1reg), .Q(H3_Q));


    logic [7:0] G3_Q;
    ttl_74273_sync G3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H3_Q), .Q(G3_Q));

    logic [7:0] F3_Q;
    ttl_74273_sync F3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G3_Q), .Q(F3_Q));

    logic CE3_A0;
    logic CE3_A1;
    assign CE3_A0 = B1HQ[1] ^ INV;
    assign CE3_A1 = B1HQ[2] ^ INV;





    wire BACK1_ROM_cs = (ioctl_addr >= 25'h40_000) && (ioctl_addr < 25'h48_000);
    

























    logic [7:0] ROM_DATA;
        eprom_32K BACK1_ROM
    (
        .ADDR({F3_Q[5],F3_Q[4], F2_Q[7:0], B1V[2:0], CE3_A1, CE3_A0}),
        .CLK(clk),
        .DATA(ROM_DATA),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(BACK1_ROM_cs),
        .WR(ioctl_wr)
    );
    


    logic [1:0] a3_dummy;
    logic [3:0] A3_Q;
    ttl_74174_sync B1(
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(B1HQ[0]),
        .Clr_n(1'b1),
        .D({2'b11,F3_Q[3:0]}),
        .Q({a3_dummy,A3_Q[3:0]})
    );

    logic [3:0] A3bis_Q,A3bis2_Q,A3bis3_Q,A3bis4_Q,A3bis5_Q,A3bis6_Q,A3bis7_Q,A3bis8_Q,A3bis9_Q,A3bis10_Q,A3bis11_Q,A3bis12_Q,A3bis13_Q,A3bis14_Q,A3bis15_Q;

    always @(posedge clk) begin
        A3bis2_Q <= A3_Q;
        A3bis3_Q <= A3bis2_Q;
        A3bis4_Q <= A3bis3_Q;
        A3bis5_Q <= A3bis4_Q;
        A3bis6_Q <= A3bis5_Q;
        A3bis7_Q <= A3bis6_Q;
        A3bis8_Q <= A3bis7_Q;
        A3bis9_Q <= A3bis8_Q;
        A3bis10_Q <= A3bis9_Q;
        A3bis11_Q <= A3bis10_Q;
        A3bis12_Q <= A3bis11_Q;
        A3bis13_Q <= A3bis12_Q;
        A3bis14_Q <= A3bis13_Q;
        A3bis15_Q <= A3bis14_Q;
    end

    always_comb begin
        case (dbg_B1Voffset)
            4'b0000:  A3bis_Q = A3_Q;
            4'b0001:  A3bis_Q = A3bis2_Q;
            4'b0010:  A3bis_Q = A3bis3_Q;
            4'b0011:  A3bis_Q = A3bis4_Q;
            4'b0100:  A3bis_Q = A3bis5_Q;
            4'b0101:  A3bis_Q = A3bis6_Q;
            4'b0110:  A3bis_Q = A3bis7_Q;
            4'b0111:  A3bis_Q = A3bis8_Q;
            4'b1000:  A3bis_Q = A3bis9_Q;
            4'b1001:  A3bis_Q = A3bis10_Q;
            4'b1010:  A3bis_Q = A3bis11_Q;
            4'b1011:  A3bis_Q = A3bis12_Q;
            4'b1100:  A3bis_Q = A3bis13_Q;
            4'b1101:  A3bis_Q = A3bis14_Q;
            4'b1110:  A3bis_Q = A3bis15_Q;
            default: A3bis_Q = A3_Q;    
        endcase
    end


    assign B1D[7] = (JMP_B1D7) ? B1_COLBK : A3bis_Q[3];
    assign {B1D[6],B1D[5],B1D[4]} = {A3bis_Q[2],A3bis_Q[1],A3bis_Q[0]};

    logic [7:0] B2_Q;
    ttl_74273_sync B2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(ROM_DATA), .Q(B2_Q));
    logic [7:0] B2bis_Q,B2bis2_Q,B2bis3_Q,B2bis4_Q,B2bis5_Q,B2bis6_Q,B2bis7_Q,B2bis8_Q,B2bis9_Q,B2bis10_Q,B2bis11_Q,B2bis12_Q,B2bis13_Q,B2bis14_Q,B2bis15_Q;

    always @(posedge clk) begin
        B2bis2_Q <= B2_Q;
        B2bis3_Q <= B2bis2_Q;
        B2bis4_Q <= B2bis3_Q;
        B2bis5_Q <= B2bis4_Q;
        B2bis6_Q <= B2bis5_Q;
        B2bis7_Q <= B2bis6_Q;
        B2bis8_Q <= B2bis7_Q;
        B2bis9_Q <= B2bis8_Q;
        B2bis10_Q <= B2bis9_Q;
        B2bis11_Q <= B2bis10_Q;
        B2bis12_Q <= B2bis11_Q;
        B2bis13_Q <= B2bis12_Q;
        B2bis14_Q <= B2bis13_Q;
        B2bis15_Q <= B2bis14_Q;
    end

    always_comb begin
        case (dbg_B1Voffset)
            4'b0000:  B2bis_Q = B2_Q;
            4'b0001:  B2bis_Q = B2bis2_Q;
            4'b0010:  B2bis_Q = B2bis3_Q;
            4'b0011:  B2bis_Q = B2bis4_Q;
            4'b0100:  B2bis_Q = B2bis5_Q;
            4'b0101:  B2bis_Q = B2bis6_Q;
            4'b0110:  B2bis_Q = B2bis7_Q;
            4'b0111:  B2bis_Q = B2bis8_Q;
            4'b1000:  B2bis_Q = B2bis9_Q;
            4'b1001:  B2bis_Q = B2bis10_Q;
            4'b1010:  B2bis_Q = B2bis11_Q;
            4'b1011:  B2bis_Q = B2bis12_Q;
            4'b1100:  B2bis_Q = B2bis13_Q;
            4'b1101:  B2bis_Q = B2bis14_Q;
            4'b1110:  B2bis_Q = B2bis15_Q;
            default: B2bis_Q = B2_Q;    
        endcase
    end



    logic A2_S;
    assign A2_S = B1HQ[0] ^ INV;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) A2 (.Enable_bar(1'b0), .Select((swap_px ? ~A2_S : A2_S)),
                .A_2D({B2bis_Q[7],B2bis_Q[3],B2bis_Q[6],B2bis_Q[2],B2bis_Q[5],B2bis_Q[1],B2bis_Q[4],B2bis_Q[0]}), .Y(B1D[3:0]));
endmodule
module TNKIIICore_Back1_sync(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,
    input wire RESET,

    input wire INV,
    input wire INVn,

    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire B1SY,
    input wire B1SX,


    input wire [7:0] hack_settings,
    input wire [3:0] dbg_B1Voffset, 
    input wire swap_px,

    input wire B1Y8,
    input wire B1X8,


    input wire V_C,


    input wire H8,
    input wire [4:0] Y,
    input wire H2,
    input wire H1,
    input wire H0,
    input wire [7:0] X, 

    input wire [12:0] VA,
    input wire BACK1_VRAM_CSn,
    

    input wire VFLGn,


    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,


    input wire CK1n,
    input wire LA,
    input wire VLK,



    input wire B1_COLBK,
    input wire JMP_B1D7,
    output logic [7:0] B1D
);



    logic B1B0,B1B1;


    assign B1B0 = (!VA[0] && !BACK1_VRAM_CSn) ? 1'b0 : 1'b1;
    assign B1B1 = ( VA[0] && !BACK1_VRAM_CSn) ? 1'b0 : 1'b1;


    logic [2:0] XOR_YSR;
    logic [7:0] B1Y;
    assign XOR_YSR[2] = VD_in[2] ^ INVn;
    assign XOR_YSR[1] = VD_in[1] ^ INVn;
    assign XOR_YSR[0] = VD_in[0] ^ INVn;


    reg [7:0] vdin_r;
    always @(posedge clk) begin
        vdin_r <= {VD_in[7:3],XOR_YSR};
    end

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));

    logic [8:0] B1H;
    logic [2:0] B1Hn;
    logic c14_dum3;
    logic [1:0] c12_dum;

    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        );






    logic [5:0] const_plus1d;  
    assign const_plus1d = (hack_settings[0]) ? 6'b00_0001 : 6'b00_0000;
    assign B1H[8:3] = {B1Y8,B1Y[7:3]} + {H8,Y} + const_plus1d;


    assign B1Hn[0] = ~B1H[0];
    assign B1Hn[1] = ~B1H[1];
    assign B1Hn[2] = ~B1H[2];

    logic [8:0] B1HQ;

    logic [5:0] d13_q;
    ttl_74174_sync d13
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),

        .Clr_n(1'b1),
        .D({3'b111,B1Hn}),
        .Q(d13_q)
    );
    assign B1HQ[2:0] = d13_q[2:0];

    logic [5:0] d12_q;
    ttl_74174_sync d12
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),

        .Clr_n(1'b1),
        .D(B1H[8:3]),
        .Q(d12_q)
    );
    assign B1HQ[8:3] = d12_q[5:0];


    reg [7:0] vdinX_r;
     always @(posedge clk) begin
        vdinX_r <= VD_in;
    end

    logic [7:0] B1X;
    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));
    logic [8:0] B1V;







    logic [8:0] const_minus40d;
    assign const_minus40d = (hack_settings[0]) ? 9'b1_1101_1000 : 9'b0_0000_0000;
    assign B1V = {B1X8,B1X} + {1'b0,X} + const_minus40d;





    logic L4_CSn, L3_CSn;
    logic [12:0] A;
    logic dum1;


    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({1'b1,1'b1,VA[12],B1HQ[8],VA[11],B1HQ[7],VA[10],B1HQ[6]}), .Y(A[12:9]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[9],B1HQ[5],VA[8],B1HQ[4],VA[7],B1HQ[3],VA[6],B1V[8]}), .Y(A[8:5]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[5],B1V[7],VA[4],B1V[6],VA[3],B1V[5],VA[2],B1V[4]}), .Y(A[4:1]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[1],B1V[3],B1B0,VFLGn,B1B1,VFLGn,1'b1,1'b1}), .Y({A[0],L3_CSn,L4_CSn,dum1}));

    logic BACK1_SEL0, BACK1_SEL1;
    assign BACK1_SEL0 = ~(B1B0 | VDG);
    assign BACK1_SEL1 = ~(B1B1 | VDG);


    logic [7:0] D0, D1, Din0, Din1;
    assign Din0 = (BACK1_SEL0 && VRD) ?  VD_in : 8'hFF;
    assign Din1 = (BACK1_SEL1 && VRD) ?  VD_in : 8'hFF;


    logic [7:0] back1_0_Q, back1_1_Q;
    logic [7:0] D0reg, D1reg;
    logic L4_CS, L3_CS;

    assign L3_CS = ~L3_CSn;
    assign L4_CS = ~L4_CSn;

    logic [11:0] h12_addr1;
    assign h12_addr1 = {B1HQ[8:3],B1V[8:3]};


    SRAM_dual_sync #(.ADDR_WIDTH(12)) L3
    (
        .ADDR0({VA[12:1]}), 
        .clk0(clk), 
        .cen0(L3_CS), 
        .we0(~VWE), 
        .DATA0(Din0), 
        .Q0(back1_0_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(D0reg)
    );
	 

















    SRAM_dual_sync #(.ADDR_WIDTH(12)) L4
    (
        .ADDR0({VA[12:1]}), 
        .clk0(clk), 
        .cen0(L4_CS), 
        .we0(~VWE), 
        .DATA0(Din1), 
        .Q0(back1_1_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(D1reg)
    );















    assign D0 = (!VOE) ? back1_0_Q : 8'hff;
    assign D1 = (!VOE) ? back1_1_Q : 8'hff;
    assign VD_out = (BACK1_SEL0 && !VRD) ? D0 : ((BACK1_SEL1 && !VRD) ? D1 : 8'hff);






    logic [7:0] H2_Q;
    ttl_74273_sync H2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D0reg), .Q(H2_Q));


    logic [7:0] G2_Q;
    ttl_74273_sync G2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H2_Q), .Q(G2_Q));

    logic [7:0] F2_Q;
    ttl_74273_sync F2ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G2_Q), .Q(F2_Q));


    logic [7:0] H3_Q;
    ttl_74273_sync H3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(D1reg), .Q(H3_Q));


    logic [7:0] G3_Q;
    ttl_74273_sync G3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(H3_Q), .Q(G3_Q));

    logic [7:0] F3_Q;
    ttl_74273_sync F3ic(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(G3_Q), .Q(F3_Q));

    logic CE3_A0;
    logic CE3_A1;
    assign CE3_A0 = B1HQ[1] ^ INV;
    assign CE3_A1 = B1HQ[2] ^ INV;





    wire BACK1_ROM_cs = (ioctl_addr >= 25'h40_000) && (ioctl_addr < 25'h48_000);
    

























    logic [7:0] ROM_DATA;
        eprom_32K BACK1_ROM
    (
        .ADDR({F3_Q[5],F3_Q[4], F2_Q[7:0], B1V[2:0], CE3_A1, CE3_A0}),
        .CLK(clk),
        .DATA(ROM_DATA),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(BACK1_ROM_cs),
        .WR(ioctl_wr)
    );
    


    logic [1:0] a3_dummy;
    logic [3:0] A3_Q;
    ttl_74174_sync B1(
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(B1HQ[0]),
        .Clr_n(1'b1),
        .D({2'b11,F3_Q[3:0]}),
        .Q({a3_dummy,A3_Q[3:0]})
    );

    logic [3:0] A3bis_Q,A3bis2_Q,A3bis3_Q,A3bis4_Q,A3bis5_Q,A3bis6_Q,A3bis7_Q,A3bis8_Q,A3bis9_Q,A3bis10_Q,A3bis11_Q,A3bis12_Q,A3bis13_Q,A3bis14_Q,A3bis15_Q;

    always @(posedge clk) begin
        A3bis2_Q <= A3_Q;
        A3bis3_Q <= A3bis2_Q;
        A3bis4_Q <= A3bis3_Q;
        A3bis5_Q <= A3bis4_Q;
        A3bis6_Q <= A3bis5_Q;
        A3bis7_Q <= A3bis6_Q;
        A3bis8_Q <= A3bis7_Q;
        A3bis9_Q <= A3bis8_Q;
        A3bis10_Q <= A3bis9_Q;
        A3bis11_Q <= A3bis10_Q;
        A3bis12_Q <= A3bis11_Q;
        A3bis13_Q <= A3bis12_Q;
        A3bis14_Q <= A3bis13_Q;
        A3bis15_Q <= A3bis14_Q;
    end

    always_comb begin
        case (dbg_B1Voffset)
            4'b0000:  A3bis_Q = A3_Q;
            4'b0001:  A3bis_Q = A3bis2_Q;
            4'b0010:  A3bis_Q = A3bis3_Q;
            4'b0011:  A3bis_Q = A3bis4_Q;
            4'b0100:  A3bis_Q = A3bis5_Q;
            4'b0101:  A3bis_Q = A3bis6_Q;
            4'b0110:  A3bis_Q = A3bis7_Q;
            4'b0111:  A3bis_Q = A3bis8_Q;
            4'b1000:  A3bis_Q = A3bis9_Q;
            4'b1001:  A3bis_Q = A3bis10_Q;
            4'b1010:  A3bis_Q = A3bis11_Q;
            4'b1011:  A3bis_Q = A3bis12_Q;
            4'b1100:  A3bis_Q = A3bis13_Q;
            4'b1101:  A3bis_Q = A3bis14_Q;
            4'b1110:  A3bis_Q = A3bis15_Q;
            default: A3bis_Q = A3_Q;    
        endcase
    end


    assign B1D[7] = (JMP_B1D7) ? B1_COLBK : A3bis_Q[3];
    assign {B1D[6],B1D[5],B1D[4]} = {A3bis_Q[2],A3bis_Q[1],A3bis_Q[0]};

    logic [7:0] B2_Q;
    ttl_74273_sync B2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(ROM_DATA), .Q(B2_Q));
    logic [7:0] B2bis_Q,B2bis2_Q,B2bis3_Q,B2bis4_Q,B2bis5_Q,B2bis6_Q,B2bis7_Q,B2bis8_Q,B2bis9_Q,B2bis10_Q,B2bis11_Q,B2bis12_Q,B2bis13_Q,B2bis14_Q,B2bis15_Q;

    always @(posedge clk) begin
        B2bis2_Q <= B2_Q;
        B2bis3_Q <= B2bis2_Q;
        B2bis4_Q <= B2bis3_Q;
        B2bis5_Q <= B2bis4_Q;
        B2bis6_Q <= B2bis5_Q;
        B2bis7_Q <= B2bis6_Q;
        B2bis8_Q <= B2bis7_Q;
        B2bis9_Q <= B2bis8_Q;
        B2bis10_Q <= B2bis9_Q;
        B2bis11_Q <= B2bis10_Q;
        B2bis12_Q <= B2bis11_Q;
        B2bis13_Q <= B2bis12_Q;
        B2bis14_Q <= B2bis13_Q;
        B2bis15_Q <= B2bis14_Q;
    end

    always_comb begin
        case (dbg_B1Voffset)
            4'b0000:  B2bis_Q = B2_Q;
            4'b0001:  B2bis_Q = B2bis2_Q;
            4'b0010:  B2bis_Q = B2bis3_Q;
            4'b0011:  B2bis_Q = B2bis4_Q;
            4'b0100:  B2bis_Q = B2bis5_Q;
            4'b0101:  B2bis_Q = B2bis6_Q;
            4'b0110:  B2bis_Q = B2bis7_Q;
            4'b0111:  B2bis_Q = B2bis8_Q;
            4'b1000:  B2bis_Q = B2bis9_Q;
            4'b1001:  B2bis_Q = B2bis10_Q;
            4'b1010:  B2bis_Q = B2bis11_Q;
            4'b1011:  B2bis_Q = B2bis12_Q;
            4'b1100:  B2bis_Q = B2bis13_Q;
            4'b1101:  B2bis_Q = B2bis14_Q;
            4'b1110:  B2bis_Q = B2bis15_Q;
            default: B2bis_Q = B2_Q;    
        endcase
    end



    logic A2_S;
    assign A2_S = B1HQ[0] ^ INV;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) A2 (.Enable_bar(1'b0), .Select((swap_px ? ~A2_S : A2_S)),
                .A_2D({B2bis_Q[7],B2bis_Q[3],B2bis_Q[6],B2bis_Q[2],B2bis_Q[5],B2bis_Q[1],B2bis_Q[4],B2bis_Q[0]}), .Y(B1D[3:0]));
endmodule