data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:11: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n   assign rval = {reset, 1\'b0 };\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:53: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:17] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:55: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:18] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:57: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:19] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:59: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:20] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:61: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:21] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:63: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:22] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:65: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:23] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:67: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:24] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:69: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:25] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:71: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:26] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:73: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:27] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:75: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:28] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:77: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:29] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:79: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:30] <= 57005;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:81: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shdead\' generates 32 or 16 bits.\n                                                                                                                     : ... In instance reset_test_gate\n                   dout[31:31] <= 57005;\n                               ^~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:17: Unsized numbers/parameters not allowed in replications.\n                                                                                                                           : ... In instance reset_test_gate\n               case (({(0)*(rval)})+(0))\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:88: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:0] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:90: Operator ASSIGNDLY expects 31 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:1] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:92: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:2] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:94: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:3] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:96: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:4] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:98: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                     : ... In instance reset_test_gate\n            dout[31:5] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:100: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:6] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:102: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:7] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:104: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:8] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:106: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:9] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:108: Operator ASSIGNDLY expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:10] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:110: Operator ASSIGNDLY expects 21 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:11] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:112: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:12] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:114: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:13] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:116: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:14] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:118: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:15] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:120: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:16] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:122: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:17] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:124: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:18] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:126: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:19] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:128: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:20] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:130: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:21] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:132: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:22] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:134: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:23] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:136: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:24] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:138: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:25] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:140: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:26] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:142: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:27] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:28] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:146: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:29] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/reset_test_gate.v:150: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance reset_test_gate\n            dout[31:31] <= din;\n                        ^~\n%Error: Exiting due to 48 warning(s)\n'
module reset_test_gate (clk, reset, ctrl, din, sel, dout);
   input wire clk;
   input wire reset;
   input wire [4:0] ctrl;
   input wire [1:0] din;
   input wire [0:0] sel;
   output reg [31:0] dout;
   reg [1:0] 	     i;
   wire [0:0] 	     rval;
   assign rval = {reset, 1'b0 };
   always @(posedge clk)
     begin
        case (|(reset))
          1'b 1:
            begin
               case (({(0)*(rval)})+(0))
                 0:
                   dout[31:0] <= 57005;
                 1:
                   dout[31:1] <= 57005;
                 2:
                   dout[31:2] <= 57005;
                 3:
                   dout[31:3] <= 57005;
                 4:
                   dout[31:4] <= 57005;
                 5:
                   dout[31:5] <= 57005;
                 6:
                   dout[31:6] <= 57005;
                 7:
                   dout[31:7] <= 57005;
                 8:
                   dout[31:8] <= 57005;
                 9:
                   dout[31:9] <= 57005;
                 10:
                   dout[31:10] <= 57005;
                 11:
                   dout[31:11] <= 57005;
                 12:
                   dout[31:12] <= 57005;
                 13:
                   dout[31:13] <= 57005;
                 14:
                   dout[31:14] <= 57005;
                 15:
                   dout[31:15] <= 57005;
                 16:
                   dout[31:16] <= 57005;
                 17:
                   dout[31:17] <= 57005;
                 18:
                   dout[31:18] <= 57005;
                 19:
                   dout[31:19] <= 57005;
                 20:
                   dout[31:20] <= 57005;
                 21:
                   dout[31:21] <= 57005;
                 22:
                   dout[31:22] <= 57005;
                 23:
                   dout[31:23] <= 57005;
                 24:
                   dout[31:24] <= 57005;
                 25:
                   dout[31:25] <= 57005;
                 26:
                   dout[31:26] <= 57005;
                 27:
                   dout[31:27] <= 57005;
                 28:
                   dout[31:28] <= 57005;
                 29:
                   dout[31:29] <= 57005;
                 30:
                   dout[31:30] <= 57005;
                 31:
                   dout[31:31] <= 57005;
               endcase
               i = 1;
            end
        endcase
        case (({(ctrl)*(sel)})+(0))
          0:
            dout[31:0] <= din;
          1:
            dout[31:1] <= din;
          2:
            dout[31:2] <= din;
          3:
            dout[31:3] <= din;
          4:
            dout[31:4] <= din;
          5:
            dout[31:5] <= din;
          6:
            dout[31:6] <= din;
          7:
            dout[31:7] <= din;
          8:
            dout[31:8] <= din;
          9:
            dout[31:9] <= din;
          10:
            dout[31:10] <= din;
          11:
            dout[31:11] <= din;
          12:
            dout[31:12] <= din;
          13:
            dout[31:13] <= din;
          14:
            dout[31:14] <= din;
          15:
            dout[31:15] <= din;
          16:
            dout[31:16] <= din;
          17:
            dout[31:17] <= din;
          18:
            dout[31:18] <= din;
          19:
            dout[31:19] <= din;
          20:
            dout[31:20] <= din;
          21:
            dout[31:21] <= din;
          22:
            dout[31:22] <= din;
          23:
            dout[31:23] <= din;
          24:
            dout[31:24] <= din;
          25:
            dout[31:25] <= din;
          26:
            dout[31:26] <= din;
          27:
            dout[31:27] <= din;
          28:
            dout[31:28] <= din;
          29:
            dout[31:29] <= din;
          30:
            dout[31:30] <= din;
          31:
            dout[31:31] <= din;
        endcase
     end
endmodule
module reset_test_gate (clk, reset, ctrl, din, sel, dout);

   input wire clk;
   input wire reset;
   input wire [4:0] ctrl;
   input wire [1:0] din;
   input wire [0:0] sel;
   output reg [31:0] dout;
   reg [1:0] 	     i;
   wire [0:0] 	     rval;
   assign rval = {reset, 1'b0 };
   always @(posedge clk)
     begin
        case (|(reset))
          1'b 1:
            begin
               case (({(0)*(rval)})+(0))
                 0:
                   dout[31:0] <= 57005;
                 1:
                   dout[31:1] <= 57005;
                 2:
                   dout[31:2] <= 57005;
                 3:
                   dout[31:3] <= 57005;
                 4:
                   dout[31:4] <= 57005;
                 5:
                   dout[31:5] <= 57005;
                 6:
                   dout[31:6] <= 57005;
                 7:
                   dout[31:7] <= 57005;
                 8:
                   dout[31:8] <= 57005;
                 9:
                   dout[31:9] <= 57005;
                 10:
                   dout[31:10] <= 57005;
                 11:
                   dout[31:11] <= 57005;
                 12:
                   dout[31:12] <= 57005;
                 13:
                   dout[31:13] <= 57005;
                 14:
                   dout[31:14] <= 57005;
                 15:
                   dout[31:15] <= 57005;
                 16:
                   dout[31:16] <= 57005;
                 17:
                   dout[31:17] <= 57005;
                 18:
                   dout[31:18] <= 57005;
                 19:
                   dout[31:19] <= 57005;
                 20:
                   dout[31:20] <= 57005;
                 21:
                   dout[31:21] <= 57005;
                 22:
                   dout[31:22] <= 57005;
                 23:
                   dout[31:23] <= 57005;
                 24:
                   dout[31:24] <= 57005;
                 25:
                   dout[31:25] <= 57005;
                 26:
                   dout[31:26] <= 57005;
                 27:
                   dout[31:27] <= 57005;
                 28:
                   dout[31:28] <= 57005;
                 29:
                   dout[31:29] <= 57005;
                 30:
                   dout[31:30] <= 57005;
                 31:
                   dout[31:31] <= 57005;
               endcase
               i = 1;
            end
        endcase
        case (({(ctrl)*(sel)})+(0))
          0:
            dout[31:0] <= din;
          1:
            dout[31:1] <= din;
          2:
            dout[31:2] <= din;
          3:
            dout[31:3] <= din;
          4:
            dout[31:4] <= din;
          5:
            dout[31:5] <= din;
          6:
            dout[31:6] <= din;
          7:
            dout[31:7] <= din;
          8:
            dout[31:8] <= din;
          9:
            dout[31:9] <= din;
          10:
            dout[31:10] <= din;
          11:
            dout[31:11] <= din;
          12:
            dout[31:12] <= din;
          13:
            dout[31:13] <= din;
          14:
            dout[31:14] <= din;
          15:
            dout[31:15] <= din;
          16:
            dout[31:16] <= din;
          17:
            dout[31:17] <= din;
          18:
            dout[31:18] <= din;
          19:
            dout[31:19] <= din;
          20:
            dout[31:20] <= din;
          21:
            dout[31:21] <= din;
          22:
            dout[31:22] <= din;
          23:
            dout[31:23] <= din;
          24:
            dout[31:24] <= din;
          25:
            dout[31:25] <= din;
          26:
            dout[31:26] <= din;
          27:
            dout[31:27] <= din;
          28:
            dout[31:28] <= din;
          29:
            dout[31:29] <= din;
          30:
            dout[31:30] <= din;
          31:
            dout[31:31] <= din;
        endcase
     end
endmodule