data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_sop.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_sop.v:13: Multiple top level modules\n                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                     : ... Top module \'f1_test\'\nmodule f1_test(input [1:0] in, input select, output reg out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f2_test\'\nmodule f2_test(input [3:0] in, input [1:0] select, output reg out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f3_test\'\nmodule f3_test(input [7:0] in, input [2:0] select, output reg out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f4_test\'\nmodule f4_test(input [7:0] in, output out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f5_test\'\nmodule f5_test(input in, output out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f6_test\'\nmodule f6_test(input in, output out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f7_test\'\nmodule f7_test(output out);\n       ^~~~~~~\n                                                                                                     : ... Top module \'f8_test\'\nmodule f8_test(input in, output out);\n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module f3_test(input [7:0] in, input [2:0] select, output reg out);

always @( in or select)
    case (select)
	    0: out = in[0];
	    1: out = in[1];
	    2: out = in[2];
	    3: out = in[3];
	    4: out = in[4];
	    5: out = in[5];
	    6: out = in[6];
	    7: out = in[7];
	endcase
endmodule
module f3_test(input [7:0] in, input [2:0] select, output reg out);


always @( in or select)
    case (select)
	    0: out = in[0];
	    1: out = in[1];
	    2: out = in[2];
	    3: out = in[3];
	    4: out = in[4];
	    5: out = in[5];
	    6: out = in[6];
	    7: out = in[7];
	endcase
endmodule