data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv:44: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv:103: Define or directive not defined: \'`ADDR_OFFSET\'\n  localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv:193: Define or directive not defined: \'`log2\'\n              .TO_SCM_BIT ( ADDR_MEM_WIDTH + `log2(N_SLAVE-1) + ADDR_OFFSET - 1),\n                                             ^~~~~\n%Error: Exiting due to 3 error(s)\n'
module XBAR_TCDM_WRAPPER 
#(
    parameter N_CH0           = 8,
    parameter N_CH1           = 2,
    parameter N_SLAVE         = 8,
    parameter ID_WIDTH        = N_CH0+N_CH1,


    parameter ADDR_WIDTH      = 32,
    parameter DATA_WIDTH      = 32,
    parameter BE_WIDTH        = DATA_WIDTH/8,
    parameter TEST_SET_BIT    = 20,


    parameter ADDR_MEM_WIDTH  = 11,
    parameter ADDR_SRAM_WIDTH = 10,
    parameter ADDR_SCM_WIDTH  = 8,
    
    parameter DEBUG_PARAMS    = "ENABLE"
)
(

    input  logic [N_CH0+N_CH1-1:0]                         data_req_i,
    input  logic [N_CH0+N_CH1-1:0][ADDR_WIDTH-1:0]         data_add_i,
    input  logic [N_CH0+N_CH1-1:0]                         data_wen_i,
    input  logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]         data_wdata_i,
    input  logic [N_CH0+N_CH1-1:0][BE_WIDTH-1:0]           data_be_i,
    output logic [N_CH0+N_CH1-1:0]                         data_gnt_o,
    output logic [N_CH0+N_CH1-1:0]                         data_r_valid_o,
    output logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]         data_r_rdata_o,


    output  logic [N_SLAVE-1:0]                            data_req_SCM_o,
    output  logic [N_SLAVE-1:0][ADDR_SCM_WIDTH-1:0]        data_add_SCM_o,
    output  logic [N_SLAVE-1:0]                            data_wen_SCM_o,
    output  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_wdata_SCM_o,
    output  logic [N_SLAVE-1:0][BE_WIDTH-1:0]              data_be_SCM_o,
    input   logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_r_rdata_SCM_i,

    output  logic [N_SLAVE-1:0]                            data_req_SRAM_o,
    output  logic [N_SLAVE-1:0][ADDR_SRAM_WIDTH-1:0]       data_add_SRAM_o,
    output  logic [N_SLAVE-1:0]                            data_wen_SRAM_o,
    output  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_wdata_SRAM_o,
    output  logic [N_SLAVE-1:0][BE_WIDTH-1:0]              data_be_SRAM_o,
    input   logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_r_rdata_SRAM_i,

    input  logic                                           clk,
    input  logic                                           rst_n,
    
    input   logic [1:0]                                    TCDM_arb_policy_i,

    input  logic [N_SLAVE-1:0]                             enable_req_pipe_i,
    input  logic [N_SLAVE-1:0]                             enable_resp_pipe_i
);

  localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);

  logic [N_SLAVE-1:0]                                    data_req_int;
  logic [N_SLAVE-1:0]                                    data_ts_set_int;
  logic [N_SLAVE-1:0][ADDR_MEM_WIDTH-1:0]                data_add_int;
  logic [N_SLAVE-1:0]                                    data_wen_int;
  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]                    data_wdata_int;
  logic [N_SLAVE-1:0][BE_WIDTH-1:0]                      data_be_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_int;
  logic [N_SLAVE-1:0]                                    data_gnt_int;
  
  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]                    data_r_rdata_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_r_ID_int;
  logic [N_SLAVE-1:0]                                    data_r_valid_int;
      

  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_SCM_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_SRAM_int;
      

  logic [N_CH0+N_CH1-1:0]                                data_req_post_gmask;
  logic [N_CH0+N_CH1-1:0][ADDR_WIDTH-1:0]                data_add_post_gmask;
  logic [N_CH0+N_CH1-1:0]                                data_wen_post_gmask;
  logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]                data_wdata_post_gmask;
  logic [N_CH0+N_CH1-1:0][BE_WIDTH-1:0]                  data_be_post_gmask;
  logic [N_CH0+N_CH1-1:0]                                data_gnt_post_gmask;


  logic [N_SLAVE-1:0]                                    data_ts_set_SRAM;
  logic [N_SLAVE-1:0]                                    data_ts_set_SCM;
  logic [N_SLAVE-1:0]                                    send_back_rvalid;


  XBAR_TCDM 
  #(
      .N_CH0          (N_CH0             ),
      .N_CH1          (N_CH1             ),
      .N_SLAVE        (N_SLAVE           ),
      .ID_WIDTH       (ID_WIDTH          ),

      .ADDR_WIDTH     ( ADDR_WIDTH       ),
      .DATA_WIDTH     ( DATA_WIDTH       ),
      .BE_WIDTH       ( BE_WIDTH         ),

      .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH   ),
      .TEST_SET_BIT   ( TEST_SET_BIT     )
   )
   i_XBAR_TCDM
   (

      .data_req_i     (  data_req_post_gmask       ),
      .data_add_i     (  data_add_post_gmask       ),
      .data_wen_i     (  data_wen_post_gmask       ),
      .data_wdata_i   (  data_wdata_post_gmask     ),
      .data_be_i      (  data_be_post_gmask        ),
      .data_gnt_o     (  data_gnt_post_gmask       ), 

      .data_r_valid_o (                            ),
      .data_r_rdata_o (  data_r_rdata_o            ),


      .data_req_o     (  data_req_int              ),
      .data_ts_set_o  (  data_ts_set_int           ),
      .data_add_o     (  data_add_int              ),
      .data_wen_o     (  data_wen_int              ),
      .data_wdata_o   (  data_wdata_int            ),
      .data_be_o      (  data_be_int               ), 
      .data_ID_o      (  data_ID_int               ),
      .data_gnt_i     (  data_gnt_int              ),

      .data_r_rdata_i (  data_r_rdata_int          ),
      .data_r_valid_i (  data_r_valid_int          ),
      .data_r_ID_i    (  data_r_ID_int             ),

      .TCDM_arb_policy_i( TCDM_arb_policy_i        ),

      .clk            (  clk                       ),
      .rst_n          (  rst_n                     )
   );


genvar i;


generate
    for(i=0; i<N_CH0+N_CH1; i++)
    begin  : GRANT_MASK_BLOCK
          grant_mask
          #(
              .N_SLAVE    ( N_SLAVE       ),
              .TO_SCM_BIT ( ADDR_MEM_WIDTH + `log2(N_SLAVE-1) + ADDR_OFFSET - 1),
              .ADDR_WIDTH ( ADDR_WIDTH    ),
              .DATA_WIDTH ( DATA_WIDTH    ),
              .BE_WIDTH   ( BE_WIDTH      )
          )
          i_grant_mask
          (
              .data_req_i         ( data_req_i[i]           ),
              .data_add_i         ( data_add_i[i]           ),
              .data_wen_i         ( data_wen_i[i]           ),
              .data_wdata_i       ( data_wdata_i[i]         ),
              .data_be_i          ( data_be_i[i]            ),
              .data_gnt_o         ( data_gnt_o[i]           ),
              .data_r_valid_o     ( data_r_valid_o[i]       ),

              .data_req_o         ( data_req_post_gmask[i]  ),
              .data_add_o         ( data_add_post_gmask[i]  ),
              .data_wen_o         ( data_wen_post_gmask[i]  ),
              .data_wdata_o       ( data_wdata_post_gmask[i]),
              .data_be_o          ( data_be_post_gmask[i]   ),
              .data_gnt_i         ( data_gnt_post_gmask[i]  ),

              .enable_PIPE_req_i  ( enable_req_pipe_i       ),
              .enable_PIPE_resp_i ( enable_resp_pipe_i      ),

              .clk(clk), 
              .rst_n(rst_n)
          );
    end


    for(i=0; i<N_SLAVE; i++)
    begin : PIPE_REQ
          TCDM_PIPE_REQ 
          #(
              .MEM_WIDTH          ( ADDR_MEM_WIDTH       ),
              .SCM_MEM_WIDTH      ( ADDR_SCM_WIDTH       ),
              .SRAM_MEM_WIDTH     ( ADDR_SRAM_WIDTH      ),
              .ID_WIDTH           ( ID_WIDTH             ),
              .DATA_WIDTH         ( DATA_WIDTH           ),
              .BE_WIDTH           ( BE_WIDTH             )
          )
          i_TCDM_PIPE_REQ
          (
              .clk                ( clk                  ),
              .rst_n              ( rst_n                ),

              .data_req_i         ( data_req_int[i]      ),
              .data_ts_set_i      ( data_ts_set_int[i]   ),
              .data_add_i         ( data_add_int[i]      ),
              .data_wen_i         ( data_wen_int[i]      ),
              .data_wdata_i       ( data_wdata_int[i]    ),
              .data_be_i          ( data_be_int[i]       ),
              .data_ID_i          ( data_ID_int[i]       ),
              .data_gnt_o         ( data_gnt_int[i]      ),

              .data_req_SCM_o     ( data_req_SCM_o[i]    ),
              .data_ts_set_SCM_o  ( data_ts_set_SCM[i]   ),
              .data_add_SCM_o     ( data_add_SCM_o[i]    ),
              .data_wen_SCM_o     ( data_wen_SCM_o[i]    ),
              .data_wdata_SCM_o   ( data_wdata_SCM_o[i]  ),
              .data_be_SCM_o      ( data_be_SCM_o[i]     ),
              .data_ID_SCM_o      ( data_ID_SCM_int[i]   ),

              .data_req_SRAM_o    ( data_req_SRAM_o[i]   ),
              .data_ts_set_SRAM_o ( data_ts_set_SRAM[i]  ),
              .data_add_SRAM_o    ( data_add_SRAM_o[i]   ),
              .data_wen_SRAM_o    ( data_wen_SRAM_o[i]   ),
              .data_wdata_SRAM_o  ( data_wdata_SRAM_o[i] ),
              .data_be_SRAM_o     ( data_be_SRAM_o[i]    ),
              .data_ID_SRAM_o     ( data_ID_SRAM_int[i]  ),

              .enable_pipe_req_i  ( enable_req_pipe_i[i] ),
              .enable_pipe_resp_i ( enable_resp_pipe_i[i])
          );
    end

    for(i=0; i<N_SLAVE; i++)
    begin : SEND_BACK_RVALID_BIND
          assign send_back_rvalid[i] = (data_req_SRAM_o[i] & ~data_ts_set_SRAM[i]) | (data_req_SCM_o[i] & ~data_ts_set_SCM[i]);
    end

    for(i=0; i<N_SLAVE; i++)
    begin : PIPE_RESP
          TCDM_PIPE_RESP 
          #(
                .ID_WIDTH             ( ID_WIDTH   ),
                .DATA_WIDTH           ( DATA_WIDTH )
          )
          i_TCDM_PIPE_RESP
          (
                .clk                  ( clk                                     ),
                .rst_n                ( rst_n                                   ),

                .data_r_rdata_SCM_i   ( data_r_rdata_SCM_i[i]                   ),
                .data_r_rdata_SRAM_i  ( data_r_rdata_SRAM_i[i]                  ),

                .SEL_i                (  data_req_SRAM_o[i]                     ),
                .req_i                (  send_back_rvalid[i]                    ),
                .data_ID_SCM_i        (  data_ID_SCM_int[i]                     ),
                .data_ID_SRAM_i       (  data_ID_SRAM_int[i]                    ),

                .data_r_rdata_o       ( data_r_rdata_int[i]                     ),
                .data_r_valid_o       ( data_r_valid_int[i]                     ), 
                .data_r_ID_o          ( data_r_ID_int[i]                        ), 

                .enable_pipe_i        ( enable_resp_pipe_i[i]                   )
          );
    end 
endgenerate


`ifdef DEBUG_INFO

initial
begin
    if(DEBUG_PARAMS == "ENABLE")
    begin
        $display("**********************************",);
        $display(">>>> XBAR_TCDM_WRAPPER_PARAMS <<<<",);
        $display("**********************************",);
        $display("N_CH0           = %d", N_CH0   );
        $display("N_CH1           = %d",N_CH1   );
        $display("N_SLAVE         = %d",N_SLAVE );
        $display("ID_WIDTH        = %d",ID_WIDTH);
        $display("ADDR_WIDTH      = %d",ADDR_WIDTH  );
        $display("DATA_WIDTH      = %d",DATA_WIDTH  );
        $display("BE_WIDTH        = %d",BE_WIDTH    );
        $display("TEST_SET_BIT    = %d",TEST_SET_BIT);
        $display("ADDR_MEM_WIDTH  = %d",ADDR_MEM_WIDTH  );
        $display("ADDR_SRAM_WIDTH = %d",ADDR_SRAM_WIDTH );
        $display("ADDR_SCM_WIDTH  = %d",ADDR_SCM_WIDTH  );
        $display("ADDR_OFFSET     = %d",ADDR_OFFSET);
        $display("**********************************",);
    end
end                           

`endif











































































endmodule
module XBAR_TCDM_WRAPPER 
#(
    parameter N_CH0           = 8,
    parameter N_CH1           = 2,
    parameter N_SLAVE         = 8,
    parameter ID_WIDTH        = N_CH0+N_CH1,


    parameter ADDR_WIDTH      = 32,
    parameter DATA_WIDTH      = 32,
    parameter BE_WIDTH        = DATA_WIDTH/8,
    parameter TEST_SET_BIT    = 20,


    parameter ADDR_MEM_WIDTH  = 11,
    parameter ADDR_SRAM_WIDTH = 10,
    parameter ADDR_SCM_WIDTH  = 8,
    
    parameter DEBUG_PARAMS    = "ENABLE"
)
(

    input  logic [N_CH0+N_CH1-1:0]                         data_req_i,
    input  logic [N_CH0+N_CH1-1:0][ADDR_WIDTH-1:0]         data_add_i,
    input  logic [N_CH0+N_CH1-1:0]                         data_wen_i,
    input  logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]         data_wdata_i,
    input  logic [N_CH0+N_CH1-1:0][BE_WIDTH-1:0]           data_be_i,
    output logic [N_CH0+N_CH1-1:0]                         data_gnt_o,
    output logic [N_CH0+N_CH1-1:0]                         data_r_valid_o,
    output logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]         data_r_rdata_o,


    output  logic [N_SLAVE-1:0]                            data_req_SCM_o,
    output  logic [N_SLAVE-1:0][ADDR_SCM_WIDTH-1:0]        data_add_SCM_o,
    output  logic [N_SLAVE-1:0]                            data_wen_SCM_o,
    output  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_wdata_SCM_o,
    output  logic [N_SLAVE-1:0][BE_WIDTH-1:0]              data_be_SCM_o,
    input   logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_r_rdata_SCM_i,

    output  logic [N_SLAVE-1:0]                            data_req_SRAM_o,
    output  logic [N_SLAVE-1:0][ADDR_SRAM_WIDTH-1:0]       data_add_SRAM_o,
    output  logic [N_SLAVE-1:0]                            data_wen_SRAM_o,
    output  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_wdata_SRAM_o,
    output  logic [N_SLAVE-1:0][BE_WIDTH-1:0]              data_be_SRAM_o,
    input   logic [N_SLAVE-1:0][DATA_WIDTH-1:0]            data_r_rdata_SRAM_i,

    input  logic                                           clk,
    input  logic                                           rst_n,
    
    input   logic [1:0]                                    TCDM_arb_policy_i,

    input  logic [N_SLAVE-1:0]                             enable_req_pipe_i,
    input  logic [N_SLAVE-1:0]                             enable_resp_pipe_i
);


  localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);

  logic [N_SLAVE-1:0]                                    data_req_int;
  logic [N_SLAVE-1:0]                                    data_ts_set_int;
  logic [N_SLAVE-1:0][ADDR_MEM_WIDTH-1:0]                data_add_int;
  logic [N_SLAVE-1:0]                                    data_wen_int;
  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]                    data_wdata_int;
  logic [N_SLAVE-1:0][BE_WIDTH-1:0]                      data_be_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_int;
  logic [N_SLAVE-1:0]                                    data_gnt_int;
  
  logic [N_SLAVE-1:0][DATA_WIDTH-1:0]                    data_r_rdata_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_r_ID_int;
  logic [N_SLAVE-1:0]                                    data_r_valid_int;
      

  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_SCM_int;
  logic [N_SLAVE-1:0][ID_WIDTH-1:0]                      data_ID_SRAM_int;
      

  logic [N_CH0+N_CH1-1:0]                                data_req_post_gmask;
  logic [N_CH0+N_CH1-1:0][ADDR_WIDTH-1:0]                data_add_post_gmask;
  logic [N_CH0+N_CH1-1:0]                                data_wen_post_gmask;
  logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0]                data_wdata_post_gmask;
  logic [N_CH0+N_CH1-1:0][BE_WIDTH-1:0]                  data_be_post_gmask;
  logic [N_CH0+N_CH1-1:0]                                data_gnt_post_gmask;


  logic [N_SLAVE-1:0]                                    data_ts_set_SRAM;
  logic [N_SLAVE-1:0]                                    data_ts_set_SCM;
  logic [N_SLAVE-1:0]                                    send_back_rvalid;


  XBAR_TCDM 
  #(
      .N_CH0          (N_CH0             ),
      .N_CH1          (N_CH1             ),
      .N_SLAVE        (N_SLAVE           ),
      .ID_WIDTH       (ID_WIDTH          ),

      .ADDR_WIDTH     ( ADDR_WIDTH       ),
      .DATA_WIDTH     ( DATA_WIDTH       ),
      .BE_WIDTH       ( BE_WIDTH         ),

      .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH   ),
      .TEST_SET_BIT   ( TEST_SET_BIT     )
   )
   i_XBAR_TCDM
   (

      .data_req_i     (  data_req_post_gmask       ),
      .data_add_i     (  data_add_post_gmask       ),
      .data_wen_i     (  data_wen_post_gmask       ),
      .data_wdata_i   (  data_wdata_post_gmask     ),
      .data_be_i      (  data_be_post_gmask        ),
      .data_gnt_o     (  data_gnt_post_gmask       ), 

      .data_r_valid_o (                            ),
      .data_r_rdata_o (  data_r_rdata_o            ),


      .data_req_o     (  data_req_int              ),
      .data_ts_set_o  (  data_ts_set_int           ),
      .data_add_o     (  data_add_int              ),
      .data_wen_o     (  data_wen_int              ),
      .data_wdata_o   (  data_wdata_int            ),
      .data_be_o      (  data_be_int               ), 
      .data_ID_o      (  data_ID_int               ),
      .data_gnt_i     (  data_gnt_int              ),

      .data_r_rdata_i (  data_r_rdata_int          ),
      .data_r_valid_i (  data_r_valid_int          ),
      .data_r_ID_i    (  data_r_ID_int             ),

      .TCDM_arb_policy_i( TCDM_arb_policy_i        ),

      .clk            (  clk                       ),
      .rst_n          (  rst_n                     )
   );


genvar i;


generate
    for(i=0; i<N_CH0+N_CH1; i++)
    begin  : GRANT_MASK_BLOCK
          grant_mask
          #(
              .N_SLAVE    ( N_SLAVE       ),
              .TO_SCM_BIT ( ADDR_MEM_WIDTH + `log2(N_SLAVE-1) + ADDR_OFFSET - 1),
              .ADDR_WIDTH ( ADDR_WIDTH    ),
              .DATA_WIDTH ( DATA_WIDTH    ),
              .BE_WIDTH   ( BE_WIDTH      )
          )
          i_grant_mask
          (
              .data_req_i         ( data_req_i[i]           ),
              .data_add_i         ( data_add_i[i]           ),
              .data_wen_i         ( data_wen_i[i]           ),
              .data_wdata_i       ( data_wdata_i[i]         ),
              .data_be_i          ( data_be_i[i]            ),
              .data_gnt_o         ( data_gnt_o[i]           ),
              .data_r_valid_o     ( data_r_valid_o[i]       ),

              .data_req_o         ( data_req_post_gmask[i]  ),
              .data_add_o         ( data_add_post_gmask[i]  ),
              .data_wen_o         ( data_wen_post_gmask[i]  ),
              .data_wdata_o       ( data_wdata_post_gmask[i]),
              .data_be_o          ( data_be_post_gmask[i]   ),
              .data_gnt_i         ( data_gnt_post_gmask[i]  ),

              .enable_PIPE_req_i  ( enable_req_pipe_i       ),
              .enable_PIPE_resp_i ( enable_resp_pipe_i      ),

              .clk(clk), 
              .rst_n(rst_n)
          );
    end


    for(i=0; i<N_SLAVE; i++)
    begin : PIPE_REQ
          TCDM_PIPE_REQ 
          #(
              .MEM_WIDTH          ( ADDR_MEM_WIDTH       ),
              .SCM_MEM_WIDTH      ( ADDR_SCM_WIDTH       ),
              .SRAM_MEM_WIDTH     ( ADDR_SRAM_WIDTH      ),
              .ID_WIDTH           ( ID_WIDTH             ),
              .DATA_WIDTH         ( DATA_WIDTH           ),
              .BE_WIDTH           ( BE_WIDTH             )
          )
          i_TCDM_PIPE_REQ
          (
              .clk                ( clk                  ),
              .rst_n              ( rst_n                ),

              .data_req_i         ( data_req_int[i]      ),
              .data_ts_set_i      ( data_ts_set_int[i]   ),
              .data_add_i         ( data_add_int[i]      ),
              .data_wen_i         ( data_wen_int[i]      ),
              .data_wdata_i       ( data_wdata_int[i]    ),
              .data_be_i          ( data_be_int[i]       ),
              .data_ID_i          ( data_ID_int[i]       ),
              .data_gnt_o         ( data_gnt_int[i]      ),

              .data_req_SCM_o     ( data_req_SCM_o[i]    ),
              .data_ts_set_SCM_o  ( data_ts_set_SCM[i]   ),
              .data_add_SCM_o     ( data_add_SCM_o[i]    ),
              .data_wen_SCM_o     ( data_wen_SCM_o[i]    ),
              .data_wdata_SCM_o   ( data_wdata_SCM_o[i]  ),
              .data_be_SCM_o      ( data_be_SCM_o[i]     ),
              .data_ID_SCM_o      ( data_ID_SCM_int[i]   ),

              .data_req_SRAM_o    ( data_req_SRAM_o[i]   ),
              .data_ts_set_SRAM_o ( data_ts_set_SRAM[i]  ),
              .data_add_SRAM_o    ( data_add_SRAM_o[i]   ),
              .data_wen_SRAM_o    ( data_wen_SRAM_o[i]   ),
              .data_wdata_SRAM_o  ( data_wdata_SRAM_o[i] ),
              .data_be_SRAM_o     ( data_be_SRAM_o[i]    ),
              .data_ID_SRAM_o     ( data_ID_SRAM_int[i]  ),

              .enable_pipe_req_i  ( enable_req_pipe_i[i] ),
              .enable_pipe_resp_i ( enable_resp_pipe_i[i])
          );
    end

    for(i=0; i<N_SLAVE; i++)
    begin : SEND_BACK_RVALID_BIND
          assign send_back_rvalid[i] = (data_req_SRAM_o[i] & ~data_ts_set_SRAM[i]) | (data_req_SCM_o[i] & ~data_ts_set_SCM[i]);
    end

    for(i=0; i<N_SLAVE; i++)
    begin : PIPE_RESP
          TCDM_PIPE_RESP 
          #(
                .ID_WIDTH             ( ID_WIDTH   ),
                .DATA_WIDTH           ( DATA_WIDTH )
          )
          i_TCDM_PIPE_RESP
          (
                .clk                  ( clk                                     ),
                .rst_n                ( rst_n                                   ),

                .data_r_rdata_SCM_i   ( data_r_rdata_SCM_i[i]                   ),
                .data_r_rdata_SRAM_i  ( data_r_rdata_SRAM_i[i]                  ),

                .SEL_i                (  data_req_SRAM_o[i]                     ),
                .req_i                (  send_back_rvalid[i]                    ),
                .data_ID_SCM_i        (  data_ID_SCM_int[i]                     ),
                .data_ID_SRAM_i       (  data_ID_SRAM_int[i]                    ),

                .data_r_rdata_o       ( data_r_rdata_int[i]                     ),
                .data_r_valid_o       ( data_r_valid_int[i]                     ), 
                .data_r_ID_o          ( data_r_ID_int[i]                        ), 

                .enable_pipe_i        ( enable_resp_pipe_i[i]                   )
          );
    end 
endgenerate


`ifdef DEBUG_INFO

initial
begin
    if(DEBUG_PARAMS == "ENABLE")
    begin
        $display("**********************************",);
        $display(">>>> XBAR_TCDM_WRAPPER_PARAMS <<<<",);
        $display("**********************************",);
        $display("N_CH0           = %d", N_CH0   );
        $display("N_CH1           = %d",N_CH1   );
        $display("N_SLAVE         = %d",N_SLAVE );
        $display("ID_WIDTH        = %d",ID_WIDTH);
        $display("ADDR_WIDTH      = %d",ADDR_WIDTH  );
        $display("DATA_WIDTH      = %d",DATA_WIDTH  );
        $display("BE_WIDTH        = %d",BE_WIDTH    );
        $display("TEST_SET_BIT    = %d",TEST_SET_BIT);
        $display("ADDR_MEM_WIDTH  = %d",ADDR_MEM_WIDTH  );
        $display("ADDR_SRAM_WIDTH = %d",ADDR_SRAM_WIDTH );
        $display("ADDR_SCM_WIDTH  = %d",ADDR_SCM_WIDTH  );
        $display("ADDR_OFFSET     = %d",ADDR_OFFSET);
        $display("**********************************",);
    end
end                           

`endif











































































endmodule