data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v:28: Cannot find file containing module: \'vgaHdmi\'\nvgaHdmi UUT (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench,data/full_repos/permissive/506081587/vgaHdmi\n             data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench,data/full_repos/permissive/506081587/vgaHdmi.v\n             data/full_repos/permissive/506081587/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench,data/full_repos/permissive/506081587/vgaHdmi.sv\n             vgaHdmi\n             vgaHdmi.v\n             vgaHdmi.sv\n             obj_dir/vgaHdmi\n             obj_dir/vgaHdmi.v\n             obj_dir/vgaHdmi.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vgaHdmi_tb;


reg clock, clock50;
reg reset;
reg switchR, switchG, switchB;
wire hsync;
wire vsync;
wire dataEnable;
wire vgaClock;
wire [23:0] RGBchannel;


vgaHdmi UUT (

  .clock  (clock),
  .clock50(clock50),
	.reset  (reset),
	.hsync  (hsync),
	.vsync  (vsync),


  .switchR   (switchR),
  .switchG   (switchG),
  .switchB   (switchB),
	.dataEnable(dataEnable),
  .vgaClock  (vgaClock),
  .RGBchannel(RGBchannel)
  );

initial begin
  clock   = 0;
  reset   = 1;
  switchR = 0;
  switchG = 0;
  switchB = 0;
  #10;
  reset = 0;
  forever begin
    clock = ~clock;
    #10;
  end
end

initial begin
  clock50 = 0;
  #10;
  forever begin
    clock50 = ~clock50;
    #5;
  end
end

endmodule
module vgaHdmi_tb;



reg clock, clock50;
reg reset;
reg switchR, switchG, switchB;
wire hsync;
wire vsync;
wire dataEnable;
wire vgaClock;
wire [23:0] RGBchannel;


vgaHdmi UUT (

  .clock  (clock),
  .clock50(clock50),
	.reset  (reset),
	.hsync  (hsync),
	.vsync  (vsync),


  .switchR   (switchR),
  .switchG   (switchG),
  .switchB   (switchB),
	.dataEnable(dataEnable),
  .vgaClock  (vgaClock),
  .RGBchannel(RGBchannel)
  );

initial begin
  clock   = 0;
  reset   = 1;
  switchR = 0;
  switchG = 0;
  switchB = 0;
  #10;
  reset = 0;
  forever begin
    clock = ~clock;
    #10;
  end
end

initial begin
  clock50 = 0;
  #10;
  forever begin
    clock50 = ~clock50;
    #5;
  end
end

endmodule