data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:8: Cannot find include file: addbit.v\n`include "addbit.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v.sv\n             addbit.v\n             addbit.v.v\n             addbit.v.sv\n             obj_dir/addbit.v\n             obj_dir/addbit.v.v\n             obj_dir/addbit.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 r1 = 10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10 r2 = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 ci = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display("+--------------------------------------------------------+");\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:73: Unsupported or unknown PLI call: $monitor\n  $monitor("|  %h   |  %h   |  %h   |    %h    |   %h   |   %h    |   %h    |",\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module tb();

reg [3:0] r1,r2;
reg  ci;
wire [3:0] result;
wire  carry;


initial begin
  r1 = 0;
  r2 = 0;
  ci = 0;
  #10 r1 = 10;
  #10 r2 = 2;
  #10 ci = 1;
  #10 $display("+--------------------------------------------------------+");
  $finish;
end


adder_hier U (result,carry,r1,r2,ci);


initial begin
  $display("+--------------------------------------------------------+");
  $display("|  r1  |  r2  |  ci  | u0.sum | u1.sum | u2.sum | u3.sum |");
  $display("+--------------------------------------------------------+");
  $monitor("|  %h   |  %h   |  %h   |    %h    |   %h   |   %h    |   %h    |",
  r1,r2,ci, tb.U.u0.sum, tb.U.u1.sum, tb.U.u2.sum, tb.U.u3.sum); 
end

endmodule
module tb();


reg [3:0] r1,r2;
reg  ci;
wire [3:0] result;
wire  carry;


initial begin
  r1 = 0;
  r2 = 0;
  ci = 0;
  #10 r1 = 10;
  #10 r2 = 2;
  #10 ci = 1;
  #10 $display("+--------------------------------------------------------+");
  $finish;
end


adder_hier U (result,carry,r1,r2,ci);


initial begin
  $display("+--------------------------------------------------------+");
  $display("|  r1  |  r2  |  ci  | u0.sum | u1.sum | u2.sum | u3.sum |");
  $display("+--------------------------------------------------------+");
  $monitor("|  %h   |  %h   |  %h   |    %h    |   %h   |   %h    |   %h    |",
  r1,r2,ci, tb.U.u0.sum, tb.U.u1.sum, tb.U.u2.sum, tb.U.u3.sum); 
end

endmodule