data/full_repos/permissive/523043017/Verilog microcontroller/sum_unit.v
1: b'%Error: Cannot find file containing module: microcontroller,data/full_repos/permissive/523043017\n        ... Looked in:\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.v\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.sv\n             microcontroller,data/full_repos/permissive/523043017\n             microcontroller,data/full_repos/permissive/523043017.v\n             microcontroller,data/full_repos/permissive/523043017.sv\n             obj_dir/microcontroller,data/full_repos/permissive/523043017\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.v\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/523043017/Verilog\n%Error: Cannot find file containing module: microcontroller/sum_unit.v\n%Error: Exiting due to 3 error(s)\n'
module sum_unit(inp_0, inp_1, out_0, out_1);
  input [7:0] inp_0;
  input [7:0] inp_1;
  output [7:0] out_0;
  output out_1;
  assign {out_1, out_0} = inp_0 + inp_1;
endmodule
module sum_unit(inp_0, inp_1, out_0, out_1);

  input [7:0] inp_0;
  input [7:0] inp_1;
  output [7:0] out_0;
  output out_1;
  assign {out_1, out_0} = inp_0 + inp_1;
endmodule