data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_rtl.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_rtl.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/tcam_rtl.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module tcam_rtl
#(
   parameter   ADDR_WIDTH   =  4,
   parameter   DATA_WIDTH   =  32
)
(
   input                               CLK,

   input                               WR,
   input          [ADDR_WIDTH-1:0]     ADDR_WR,
   input          [DATA_WIDTH-1:0]     DIN,
   input          [DATA_WIDTH-1:0]     DIN_MASK,

`ifdef EN_TCAM_RD
   input                               RD,
   input          [ADDR_WIDTH-1:0]     ADDR_RD,
   output         [DATA_WIDTH-1:0]     DOUT,
`endif

   input          [DATA_WIDTH-1:0]     CAM_IN,
   output   reg                        MATCH,
   output   reg   [ADDR_WIDTH-1:0]     MATCH_ADDR
);

(* RAM_STYLE = "DISTRIBUTED" *)
reg   [DATA_WIDTH-1:0]  mem[0:(2**ADDR_WIDTH)-1];
reg   [DATA_WIDTH-1:0]  mask[0:(2**ADDR_WIDTH)-1];

`ifdef EN_TCAM_RD
reg   [DATA_WIDTH-1:0]  rd_data;
`endif

always @(posedge CLK)
   if (WR)  begin
      mem[ADDR_WR]   <= DIN;
      mask[ADDR_WR]  <= DIN_MASK;
   end
`ifdef EN_TCAM_RD
   else if (RD)  rd_data   <= mem[ADDR_RD]; 

assign   DOUT  =  rd_data;
`endif

reg   [ADDR_WIDTH-1:0]  rMatchAddr;
reg   rMatch;

integer i;

always @(CAM_IN) begin
   rMatch = 0;
   rMatchAddr = 0;
   for (i=0; i<(2**ADDR_WIDTH); i=i+1) begin
      if (|((CAM_IN & mask[i]) ^ (mem[i] & mask[i])) == 0) begin rMatch = 1;   rMatchAddr = i; end
   end
end

always @(posedge CLK) MATCH_ADDR <= rMatchAddr;

always @(posedge CLK) MATCH <= rMatch; 

endmodule
module tcam_rtl
#(
   parameter   ADDR_WIDTH   =  4,
   parameter   DATA_WIDTH   =  32
)
(
   input                               CLK,

   input                               WR,
   input          [ADDR_WIDTH-1:0]     ADDR_WR,
   input          [DATA_WIDTH-1:0]     DIN,
   input          [DATA_WIDTH-1:0]     DIN_MASK,

`ifdef EN_TCAM_RD
   input                               RD,
   input          [ADDR_WIDTH-1:0]     ADDR_RD,
   output         [DATA_WIDTH-1:0]     DOUT,
`endif

   input          [DATA_WIDTH-1:0]     CAM_IN,
   output   reg                        MATCH,
   output   reg   [ADDR_WIDTH-1:0]     MATCH_ADDR
);


(* RAM_STYLE = "DISTRIBUTED" *)
reg   [DATA_WIDTH-1:0]  mem[0:(2**ADDR_WIDTH)-1];
reg   [DATA_WIDTH-1:0]  mask[0:(2**ADDR_WIDTH)-1];

`ifdef EN_TCAM_RD
reg   [DATA_WIDTH-1:0]  rd_data;
`endif

always @(posedge CLK)
   if (WR)  begin
      mem[ADDR_WR]   <= DIN;
      mask[ADDR_WR]  <= DIN_MASK;
   end
`ifdef EN_TCAM_RD
   else if (RD)  rd_data   <= mem[ADDR_RD]; 

assign   DOUT  =  rd_data;
`endif

reg   [ADDR_WIDTH-1:0]  rMatchAddr;
reg   rMatch;

integer i;

always @(CAM_IN) begin
   rMatch = 0;
   rMatchAddr = 0;
   for (i=0; i<(2**ADDR_WIDTH); i=i+1) begin
      if (|((CAM_IN & mask[i]) ^ (mem[i] & mask[i])) == 0) begin rMatch = 1;   rMatchAddr = i; end
   end
end

always @(posedge CLK) MATCH_ADDR <= rMatchAddr;

always @(posedge CLK) MATCH <= rMatch; 

endmodule