data/full_repos/permissive/495709021/NRPolarEncode/Stage_9_block.v
1: b"%Error: data/full_repos/permissive/495709021/NRPolarEncode/Stage_9_block.v:28: Cannot find file containing module: 'Stage_9'\n  Stage_9 u_Stage_9 (.clk(clk),\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/495709021/NRPolarEncode,data/full_repos/permissive/495709021/Stage_9\n             data/full_repos/permissive/495709021/NRPolarEncode,data/full_repos/permissive/495709021/Stage_9.v\n             data/full_repos/permissive/495709021/NRPolarEncode,data/full_repos/permissive/495709021/Stage_9.sv\n             Stage_9\n             Stage_9.v\n             Stage_9.sv\n             obj_dir/Stage_9\n             obj_dir/Stage_9.v\n             obj_dir/Stage_9.sv\n%Error: Exiting due to 1 error(s)\n"
module Stage_9_block
          (clk,
           reset,
           enb,
           dataIn,
           validIn,
           dataOut,
           validOut);


  input   clk;
  input   reset;
  input   enb;
  input   dataIn;
  input   validIn;
  output  dataOut;
  output  validOut;


  wire Stage_9_out1;
  wire Stage_9_out2;


  Stage_9 u_Stage_9 (.clk(clk),
                     .reset(reset),
                     .enb(enb),
                     .dataIn(dataIn),
                     .validIn(validIn),
                     .dataOut(Stage_9_out1),
                     .validOut(Stage_9_out2)
                     );

  assign dataOut = Stage_9_out1;

  assign validOut = Stage_9_out2;

endmodule
module Stage_9_block
          (clk,
           reset,
           enb,
           dataIn,
           validIn,
           dataOut,
           validOut);



  input   clk;
  input   reset;
  input   enb;
  input   dataIn;
  input   validIn;
  output  dataOut;
  output  validOut;


  wire Stage_9_out1;
  wire Stage_9_out2;


  Stage_9 u_Stage_9 (.clk(clk),
                     .reset(reset),
                     .enb(enb),
                     .dataIn(dataIn),
                     .validIn(validIn),
                     .dataOut(Stage_9_out1),
                     .validOut(Stage_9_out2)
                     );

  assign dataOut = Stage_9_out1;

  assign validOut = Stage_9_out2;

endmodule