data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/signExt.v
data/verilator_xmls/67cedc36-44c5-41a3-97c4-e419836e3ae2.xml
module signExt (
  input       [15:0] a,
  output wire [31:0] y
);



assign y = {{16{a[15]}},a};

endmodule
module signExt (
  input       [15:0] a,
  output wire [31:0] y
);




assign y = {{16{a[15]}},a};

endmodule