data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v
1: b"%Error: data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v:103: Cannot find file containing module: 'MultiCycleCpu'\nMultiCycleCpu MCC (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/MultiCycleCpu\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/MultiCycleCpu.v\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/MultiCycleCpu.sv\n             MultiCycleCpu\n             MultiCycleCpu.v\n             MultiCycleCpu.sv\n             obj_dir/MultiCycleCpu\n             obj_dir/MultiCycleCpu.v\n             obj_dir/MultiCycleCpu.sv\n%Error: data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v:152: Cannot find file containing module: 'MemoryManagerUnit'\nMemoryManagerUnit MMU (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v:177: Cannot find file containing module: 'VHDControler'\nVHDControler vhd (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v:193: Cannot find file containing module: 'Timer'\nTimer t(\n^~~~~\n%Error: data/full_repos/permissive/42581625/PersonalComputer/MainBoard.v:206: Cannot find file containing module: 'KeyBoardControler'\nKeyBoardControler kbc (\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module MainBoard(
`ifndef SIMULATION

input clk,
input clk_50M,


input[4:0] RegNum,
`endif
output[31:0] RegData,
output[31:0] ProgramCounter,
output[31:0] ExtraOut,
output[31:0] IR,


output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b,

`ifndef SIMULATION

input PS2C,
input PS2D,
`endif


input RxD,
output TxD
    );
`ifdef SIMULATION
reg clk;
reg clk_50M;
reg[4:0] RegNum;
reg PS2C;
reg PS2D;
initial begin

    RegNum = 8;
    clk = 0;
    clk_50M = 0;
    clk = 0;
    PS2C = 0;
    PS2D = 0;

    #100;
       

end

always#10 begin
    clk_50M = ~clk_50M;
end
always#10 begin
    clk = ~clk;
end
always #200 begin
	PS2C = ~PS2C;
end
always #330 begin
	PS2D = ~PS2D;
end
`endif


reg[31:0] MemReadData;
reg MemOK;
initial begin
    MemReadData <= 0;
    MemOK <= 0;
end
wire OutINTE;
wire[31:0] OutCause;
wire[31:0] RequestedMemAddr;
wire RequestedMemWrite;
wire RequestedMemRead;
wire RequestedSaveHalf;
wire RequestedLoadHalf;
wire[31:0] RequestedMemWriteData;
wire InteAccept;
wire[31:0] MMCExtraOut;
MultiCycleCpu MCC (

    .clk(clk), 

    .MemOK(MemOK),
    .MemReadData(MemReadData),
    .OutINTE(OutINTE),
    .OutCause(OutCause),
     

    .MemAddr(RequestedMemAddr), 
    .MemWrite(RequestedMemWrite), 
    .MemRead(RequestedMemRead), 
    .SaveHalf(RequestedSaveHalf), 
    .LoadHalf(RequestedLoadHalf), 
    .MemWriteData(RequestedMemWriteData), 
    .InteAccept(InteAccept),
     

    .RegNum(RegNum), 
    .ProgramCounter(ProgramCounter), 
    .IR(IR),
    .ExtraOut(MMCExtraOut),
	 .RegData(RegData)
    );
reg[31:0] MemAddr;
reg MemWrite;
reg MemRead;
reg SaveHalf;
reg LoadHalf;
reg[31:0] MemWriteData;
reg[1:0] state;
initial begin
    MemAddr <= 0;
    MemWrite <= 0;
    MemRead <= 0;
    SaveHalf <= 0;
    LoadHalf <= 0;
    MemWriteData <= 0;
    state <= 0;
end

assign ExtraOut = MemAddr;


wire BlockMemChipSelect;
wire BlockMemOK;
wire[31:0] BlockMemReadData;
assign BlockMemChipSelect = (0 <= MemAddr) && (MemAddr < 16'h5000);
MemoryManagerUnit MMU (
    .clk(clk), 
    .clk_50M(clk_50M), 
    .MemAddr(MemAddr[14:0]), 
    .MemWrite(MemWrite), 
    .MemRead(MemRead), 
    .SaveHalf(SaveHalf), 
    .LoadHalf(LoadHalf), 
    .MemWriteData(MemWriteData), 
    .ChipSelect(BlockMemChipSelect),
    .MemReadData(BlockMemReadData), 
    .MemOK(BlockMemOK), 
     
    .hsync(hsync), 
    .vsync(vsync), 
    .vga_r(vga_r), 
    .vga_g(vga_g), 
    .vga_b(vga_b)
    );


wire VHDChipSelect;
wire VHDMemOK;
wire[31:0] VHDMemReadData;
assign VHDChipSelect = (MemAddr >= 32'h50FC) && (MemAddr < 32'h5200);
VHDControler vhd (
    .clk(clk), 
    .RxD(RxD), 
    .TxD(TxD), 
    .VHDControlerAddr(MemAddr[8:0]),
    .ChipSelect(VHDChipSelect), 
    .WriteData(MemWriteData),
    .SaveHalf(SaveHalf), 
    .LoadHalf(LoadHalf), 
    .MemWrite(MemWrite), 
    .MemRead(MemRead), 
    .MemReadData(VHDMemReadData),
    .MemOK(VHDMemOK)
    );

wire TimerInte;
Timer t(
	.clk(clk_50M),
	.TimerInte(TimerInte)
    );
	 

wire[15:0] KeyBoardReadData;
wire KeyBoardChipSelect;
wire KeyBoardOK;
wire KeyBoardInte;
wire KeyBoardInteAccept;
assign KeyBoardChipSelect = (MemAddr==32'h5000);
assign KeyBoardOK = 1;
KeyBoardControler kbc (
    .clk(clk_50M), 
    .PS2C(PS2C), 
    .PS2D(PS2D), 
    .InteAccept(KeyBoardInteAccept),
    .scanCode(KeyBoardReadData), 
    .KeyBoardInte(KeyBoardInte)
    );
	 
assign OutINTE = KeyBoardInte | TimerInte;
assign OutCause= {32{KeyBoardInte}} & 32'h1 | {32{(~KeyBoardInte) & TimerInte}} & 32'h2;
assign KeyBoardInteAccept = InteAccept & KeyBoardInte;

always@(posedge clk) begin
    case(state)
    0: begin
        if(RequestedMemRead | RequestedMemWrite) begin
            state <= 1;
            MemAddr <= RequestedMemAddr;
            MemWrite <= RequestedMemWrite;
            MemRead <= RequestedMemRead;
            SaveHalf <= RequestedSaveHalf;
            LoadHalf <= RequestedLoadHalf;
            MemWriteData <= RequestedMemWriteData;
        end
        else begin
            state <= 0;
        end
    end
    
    1: begin
        if( BlockMemOK & BlockMemChipSelect | 
            KeyBoardChipSelect & KeyBoardOK |
				VHDChipSelect & VHDMemOK
            ) begin
            state <= 2;
            MemOK <= 1;
            MemReadData <= 
					{32{BlockMemChipSelect}} & BlockMemReadData |
					{32{KeyBoardChipSelect}} & {16'h0,KeyBoardReadData} |
					{32{VHDChipSelect}} & VHDMemReadData ;
            MemWrite <= 0;
            MemRead <= 0;
        end
    end
    
    2: begin
        state <= 0;
        MemOK <= 0;
    end
	 
    default: begin
        MemAddr <= 0;
        MemWrite <= 0;
        MemRead <= 0;
        SaveHalf <= 0;
        LoadHalf <= 0;
        MemWriteData <= 0;
        state <= 0;
    end
    endcase
end
endmodule
module MainBoard(
`ifndef SIMULATION

input clk,
input clk_50M,


input[4:0] RegNum,
`endif
output[31:0] RegData,
output[31:0] ProgramCounter,
output[31:0] ExtraOut,
output[31:0] IR,


output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b,

`ifndef SIMULATION

input PS2C,
input PS2D,
`endif


input RxD,
output TxD
    );

`ifdef SIMULATION
reg clk;
reg clk_50M;
reg[4:0] RegNum;
reg PS2C;
reg PS2D;
initial begin

    RegNum = 8;
    clk = 0;
    clk_50M = 0;
    clk = 0;
    PS2C = 0;
    PS2D = 0;

    #100;
       

end

always#10 begin
    clk_50M = ~clk_50M;
end
always#10 begin
    clk = ~clk;
end
always #200 begin
	PS2C = ~PS2C;
end
always #330 begin
	PS2D = ~PS2D;
end
`endif


reg[31:0] MemReadData;
reg MemOK;
initial begin
    MemReadData <= 0;
    MemOK <= 0;
end
wire OutINTE;
wire[31:0] OutCause;
wire[31:0] RequestedMemAddr;
wire RequestedMemWrite;
wire RequestedMemRead;
wire RequestedSaveHalf;
wire RequestedLoadHalf;
wire[31:0] RequestedMemWriteData;
wire InteAccept;
wire[31:0] MMCExtraOut;
MultiCycleCpu MCC (

    .clk(clk), 

    .MemOK(MemOK),
    .MemReadData(MemReadData),
    .OutINTE(OutINTE),
    .OutCause(OutCause),
     

    .MemAddr(RequestedMemAddr), 
    .MemWrite(RequestedMemWrite), 
    .MemRead(RequestedMemRead), 
    .SaveHalf(RequestedSaveHalf), 
    .LoadHalf(RequestedLoadHalf), 
    .MemWriteData(RequestedMemWriteData), 
    .InteAccept(InteAccept),
     

    .RegNum(RegNum), 
    .ProgramCounter(ProgramCounter), 
    .IR(IR),
    .ExtraOut(MMCExtraOut),
	 .RegData(RegData)
    );
reg[31:0] MemAddr;
reg MemWrite;
reg MemRead;
reg SaveHalf;
reg LoadHalf;
reg[31:0] MemWriteData;
reg[1:0] state;
initial begin
    MemAddr <= 0;
    MemWrite <= 0;
    MemRead <= 0;
    SaveHalf <= 0;
    LoadHalf <= 0;
    MemWriteData <= 0;
    state <= 0;
end

assign ExtraOut = MemAddr;


wire BlockMemChipSelect;
wire BlockMemOK;
wire[31:0] BlockMemReadData;
assign BlockMemChipSelect = (0 <= MemAddr) && (MemAddr < 16'h5000);
MemoryManagerUnit MMU (
    .clk(clk), 
    .clk_50M(clk_50M), 
    .MemAddr(MemAddr[14:0]), 
    .MemWrite(MemWrite), 
    .MemRead(MemRead), 
    .SaveHalf(SaveHalf), 
    .LoadHalf(LoadHalf), 
    .MemWriteData(MemWriteData), 
    .ChipSelect(BlockMemChipSelect),
    .MemReadData(BlockMemReadData), 
    .MemOK(BlockMemOK), 
     
    .hsync(hsync), 
    .vsync(vsync), 
    .vga_r(vga_r), 
    .vga_g(vga_g), 
    .vga_b(vga_b)
    );


wire VHDChipSelect;
wire VHDMemOK;
wire[31:0] VHDMemReadData;
assign VHDChipSelect = (MemAddr >= 32'h50FC) && (MemAddr < 32'h5200);
VHDControler vhd (
    .clk(clk), 
    .RxD(RxD), 
    .TxD(TxD), 
    .VHDControlerAddr(MemAddr[8:0]),
    .ChipSelect(VHDChipSelect), 
    .WriteData(MemWriteData),
    .SaveHalf(SaveHalf), 
    .LoadHalf(LoadHalf), 
    .MemWrite(MemWrite), 
    .MemRead(MemRead), 
    .MemReadData(VHDMemReadData),
    .MemOK(VHDMemOK)
    );

wire TimerInte;
Timer t(
	.clk(clk_50M),
	.TimerInte(TimerInte)
    );
	 

wire[15:0] KeyBoardReadData;
wire KeyBoardChipSelect;
wire KeyBoardOK;
wire KeyBoardInte;
wire KeyBoardInteAccept;
assign KeyBoardChipSelect = (MemAddr==32'h5000);
assign KeyBoardOK = 1;
KeyBoardControler kbc (
    .clk(clk_50M), 
    .PS2C(PS2C), 
    .PS2D(PS2D), 
    .InteAccept(KeyBoardInteAccept),
    .scanCode(KeyBoardReadData), 
    .KeyBoardInte(KeyBoardInte)
    );
	 
assign OutINTE = KeyBoardInte | TimerInte;
assign OutCause= {32{KeyBoardInte}} & 32'h1 | {32{(~KeyBoardInte) & TimerInte}} & 32'h2;
assign KeyBoardInteAccept = InteAccept & KeyBoardInte;

always@(posedge clk) begin
    case(state)
    0: begin
        if(RequestedMemRead | RequestedMemWrite) begin
            state <= 1;
            MemAddr <= RequestedMemAddr;
            MemWrite <= RequestedMemWrite;
            MemRead <= RequestedMemRead;
            SaveHalf <= RequestedSaveHalf;
            LoadHalf <= RequestedLoadHalf;
            MemWriteData <= RequestedMemWriteData;
        end
        else begin
            state <= 0;
        end
    end
    
    1: begin
        if( BlockMemOK & BlockMemChipSelect | 
            KeyBoardChipSelect & KeyBoardOK |
				VHDChipSelect & VHDMemOK
            ) begin
            state <= 2;
            MemOK <= 1;
            MemReadData <= 
					{32{BlockMemChipSelect}} & BlockMemReadData |
					{32{KeyBoardChipSelect}} & {16'h0,KeyBoardReadData} |
					{32{VHDChipSelect}} & VHDMemReadData ;
            MemWrite <= 0;
            MemRead <= 0;
        end
    end
    
    2: begin
        state <= 0;
        MemOK <= 0;
    end
	 
    default: begin
        MemAddr <= 0;
        MemWrite <= 0;
        MemRead <= 0;
        SaveHalf <= 0;
        LoadHalf <= 0;
        MemWriteData <= 0;
        state <= 0;
    end
    endcase
end
endmodule