data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_device_if_memory.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_device_if_memory.v:65: Cannot find include file: uart_device_if_defines.v\n`include "uart_device_if_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/uart_device_if_defines.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/uart_device_if_defines.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/uart_device_if_defines.v.sv\n             uart_device_if_defines.v\n             uart_device_if_defines.v.v\n             uart_device_if_defines.v.sv\n             obj_dir/uart_device_if_defines.v\n             obj_dir/uart_device_if_defines.v.v\n             obj_dir/uart_device_if_defines.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_device_if_memory.v:78: Define or directive not defined: \'`MEM_DEPTH\'\nreg [35:0] mem [0:`MEM_DEPTH-1];\n                  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module uart_device_if_memory (adr, data_in, data_out, read, write);

parameter DATA_WIDTH = 36;

input   [31:0]            adr;
input                     read, write;
input   [DATA_WIDTH-1:0]  data_in;

output  [DATA_WIDTH-1:0]  data_out;
reg     [DATA_WIDTH-1:0]  data_out;

reg [35:0] mem [0:`MEM_DEPTH-1];

always @ (adr)
begin
  data_out = mem[adr];
end

initial
begin
  $readmemh("vapi.log", mem);
end

endmodule
module uart_device_if_memory (adr, data_in, data_out, read, write);


parameter DATA_WIDTH = 36;

input   [31:0]            adr;
input                     read, write;
input   [DATA_WIDTH-1:0]  data_in;

output  [DATA_WIDTH-1:0]  data_out;
reg     [DATA_WIDTH-1:0]  data_out;

reg [35:0] mem [0:`MEM_DEPTH-1];

always @ (adr)
begin
  data_out = mem[adr];
end

initial
begin
  $readmemh("vapi.log", mem);
end

endmodule