data/full_repos/permissive/503973366/SIM/data_mover_core7/result_writer4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503973366/SIM/data_mover_core7/result_writer4.v:61: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'capture_success\' generates 3 bits.\n                                                                                             : ... In instance result_writer4\n    assign next_row_trigger = (capture_success == (DWIDTH / IN_DATA_WIDTH));\n                                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module result_writer4
# (
    parameter DWIDTH        = 32,
    parameter AWIDTH        = 2,
    parameter IN_DATA_WIDTH = 8
)
(
    input clk,
    input reset_n,


    input calc_done_i,


    input [IN_DATA_WIDTH - 1 : 0] calc_result_i,


    input [DWIDTH - 1 : 0] q_b_i,


    output [AWIDTH - 1 : 0] addr_b_o,
    output ce_b_o,
    output we_b_o,
    output [DWIDTH - 1 : 0] d_b_o
);


    reg [IN_DATA_WIDTH - 1 : 0] result_capture;
    reg [$clog2(DWIDTH / IN_DATA_WIDTH) : 0] capture_success; 

    wire next_row_trigger;
    assign next_row_trigger = (capture_success == (DWIDTH / IN_DATA_WIDTH));

    always@(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            result_capture  <= 0;
            capture_success <= 0;
        end else if(calc_done_i) begin
            result_capture  <= calc_result_i;
            capture_success <= capture_success + 1;
        end else if(next_row_trigger) begin
            result_capture  <= 0;
            capture_success <= 0;
        end
    end
    
    reg [DWIDTH - 1 : 0] temp_d;
    always@(*) begin
        case (capture_success)
            4: begin
                temp_d[1*(IN_DATA_WIDTH) - 1 : 0*(IN_DATA_WIDTH)] = result_capture;
            end
            3: begin
                temp_d[2*(IN_DATA_WIDTH) - 1 : 1*(IN_DATA_WIDTH)] = result_capture;
            end
            2: begin
                temp_d[3*(IN_DATA_WIDTH) - 1 : 2*(IN_DATA_WIDTH)] = result_capture;
            end
            1: begin
                temp_d[4*(IN_DATA_WIDTH) - 1 : 3*(IN_DATA_WIDTH)] = result_capture;
            end
            default: begin
                temp_d = 0;
            end
        endcase
    end

    reg [AWIDTH - 1 : 0] addr;
    always@(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            addr <= 0;
        end else if(next_row_trigger) begin
            addr <= addr + 1;
        end
    end

    assign addr_b_o = addr;
    assign ce_b_o   = next_row_trigger;
    assign we_b_o   = next_row_trigger;
    assign d_b_o    = temp_d;
endmodule
module result_writer4
# (
    parameter DWIDTH        = 32,
    parameter AWIDTH        = 2,
    parameter IN_DATA_WIDTH = 8
)
(
    input clk,
    input reset_n,


    input calc_done_i,


    input [IN_DATA_WIDTH - 1 : 0] calc_result_i,


    input [DWIDTH - 1 : 0] q_b_i,


    output [AWIDTH - 1 : 0] addr_b_o,
    output ce_b_o,
    output we_b_o,
    output [DWIDTH - 1 : 0] d_b_o
);



    reg [IN_DATA_WIDTH - 1 : 0] result_capture;
    reg [$clog2(DWIDTH / IN_DATA_WIDTH) : 0] capture_success; 

    wire next_row_trigger;
    assign next_row_trigger = (capture_success == (DWIDTH / IN_DATA_WIDTH));

    always@(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            result_capture  <= 0;
            capture_success <= 0;
        end else if(calc_done_i) begin
            result_capture  <= calc_result_i;
            capture_success <= capture_success + 1;
        end else if(next_row_trigger) begin
            result_capture  <= 0;
            capture_success <= 0;
        end
    end
    
    reg [DWIDTH - 1 : 0] temp_d;
    always@(*) begin
        case (capture_success)
            4: begin
                temp_d[1*(IN_DATA_WIDTH) - 1 : 0*(IN_DATA_WIDTH)] = result_capture;
            end
            3: begin
                temp_d[2*(IN_DATA_WIDTH) - 1 : 1*(IN_DATA_WIDTH)] = result_capture;
            end
            2: begin
                temp_d[3*(IN_DATA_WIDTH) - 1 : 2*(IN_DATA_WIDTH)] = result_capture;
            end
            1: begin
                temp_d[4*(IN_DATA_WIDTH) - 1 : 3*(IN_DATA_WIDTH)] = result_capture;
            end
            default: begin
                temp_d = 0;
            end
        endcase
    end

    reg [AWIDTH - 1 : 0] addr;
    always@(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            addr <= 0;
        end else if(next_row_trigger) begin
            addr <= addr + 1;
        end
    end

    assign addr_b_o = addr;
    assign ce_b_o   = next_row_trigger;
    assign we_b_o   = next_row_trigger;
    assign d_b_o    = temp_d;
endmodule