data/full_repos/permissive/511502298/Testbenches/test_transmitter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/test_transmitter.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/511502298/Testbenches/test_transmitter.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/511502298/Testbenches/test_transmitter.v:38: Cannot find file containing module: \'transmitter\'\n transmitter uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/transmitter\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/transmitter.v\n             data/full_repos/permissive/511502298/Testbenches,data/full_repos/permissive/511502298/transmitter.sv\n             transmitter\n             transmitter.v\n             transmitter.sv\n             obj_dir/transmitter\n             obj_dir/transmitter.v\n             obj_dir/transmitter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_transmitter;


	reg clk;
	reg rst;
	reg [7:0] data_in;
	reg tx_start;


	wire tx;
	wire busy;


	transmitter uut (
		.tx(tx), 
		.clk(clk), 
		.rst(rst), 
		.data_in(data_in), 
		.busy(busy), 
		.tx_start(tx_start)
	);

	initial begin
	
	clk = 0;
	forever
		#5 clk = !clk;
	
	
	end

	initial begin

		
		rst = 0;
		data_in = 0;
		tx_start = 0;


		#100;
		
		data_in = 8'b10101010;
		tx_start = 1;
		rst = 1;
		
      


	end
      
endmodule
module test_transmitter;



	reg clk;
	reg rst;
	reg [7:0] data_in;
	reg tx_start;


	wire tx;
	wire busy;


	transmitter uut (
		.tx(tx), 
		.clk(clk), 
		.rst(rst), 
		.data_in(data_in), 
		.busy(busy), 
		.tx_start(tx_start)
	);

	initial begin
	
	clk = 0;
	forever
		#5 clk = !clk;
	
	
	end

	initial begin

		
		rst = 0;
		data_in = 0;
		tx_start = 0;


		#100;
		
		data_in = 8'b10101010;
		tx_start = 1;
		rst = 1;
		
      


	end
      
endmodule