data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v:1: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/ram.v\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/ram.v.v\n             data/full_repos/permissive/474294847/rtl-tests/memories,data/full_repos/permissive/474294847/ram.v.sv\n             ram.v\n             ram.v.v\n             ram.v.sv\n             obj_dir/ram.v\n             obj_dir/ram.v.v\n             obj_dir/ram.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v:21: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/ram.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v:22: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/memories/ram-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module ram_tb;

reg clk, en;
reg [4:0] r_addr, w_addr;
reg [7:0] data_in; 
wire [7:0] data_out;
integer i;

ram dut 
(
    clk, en, r_addr, w_addr, data_in, data_out
);
defparam dut.ADDR_WIDTH = 5;
defparam dut.DATA_WIDTH = 8;


initial
begin
    $dumpfile("./build/rtl-sim/vcd/ram.vcd");
    $dumpvars;
end

initial
begin
    en = 1;
    clk = 0;
    r_addr = 0;
    w_addr = 0;
    data_in = 45;
    for (i = 0; i < 64; i = i + 1)
    begin
        if (((i%4) == 0) && i != 0)
            w_addr = w_addr + 1;

        data_in = i;
        r_addr = i;
        clk = ~clk;
        #100;
        clk = ~clk;
        #100;
    end
end

endmodule
module ram_tb;


reg clk, en;
reg [4:0] r_addr, w_addr;
reg [7:0] data_in; 
wire [7:0] data_out;
integer i;

ram dut 
(
    clk, en, r_addr, w_addr, data_in, data_out
);
defparam dut.ADDR_WIDTH = 5;
defparam dut.DATA_WIDTH = 8;


initial
begin
    $dumpfile("./build/rtl-sim/vcd/ram.vcd");
    $dumpvars;
end

initial
begin
    en = 1;
    clk = 0;
    r_addr = 0;
    w_addr = 0;
    data_in = 45;
    for (i = 0; i < 64; i = i + 1)
    begin
        if (((i%4) == 0) && i != 0)
            w_addr = w_addr + 1;

        data_in = i;
        r_addr = i;
        clk = ~clk;
        #100;
        clk = ~clk;
        #100;
    end
end

endmodule