data/full_repos/permissive/477367510/impl1/source/testbench_count.v
1: b'%Error: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:11: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: include\ninclude "count.v";\n^~~~~~~\n%Error: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:11: syntax error, unexpected STRING\ninclude "count.v";\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:19: Unsupported or unknown PLI call: $monitor\n  $monitor("%g %b %b %x", $time, clock, reset, count_out);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/477367510/impl1/source/testbench_count.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock = ~clock;\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module first_counter_tb();

 reg clock, reset;
 wire [31:0] count_out;
 initial begin
  $display("time\t clk reset counter");
  $monitor("%g %b %b %x", $time, clock, reset, count_out);
  clock = 1;
  reset = 0;
  #5 reset = 1;
  #10 reset = 0;
  #100 $finish;
 end

 always begin
  #5 clock = ~clock;
 end

 first_counter U_counter(
 clock,
 reset,
 count_out
 );
endmodule
module first_counter_tb();


 reg clock, reset;
 wire [31:0] count_out;
 initial begin
  $display("time\t clk reset counter");
  $monitor("%g %b %b %x", $time, clock, reset, count_out);
  clock = 1;
  reset = 0;
  #5 reset = 1;
  #10 reset = 0;
  #100 $finish;
 end

 always begin
  #5 clock = ~clock;
 end

 first_counter U_counter(
 clock,
 reset,
 count_out
 );
endmodule