data/full_repos/permissive/516359259/APB_top.v
1: b'%Error: data/full_repos/permissive/516359259/APB_top.v:1: Cannot find include file: APB_master.v\n`include "APB_master.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516359259,data/full_repos/permissive/516359259/APB_master.v\n             data/full_repos/permissive/516359259,data/full_repos/permissive/516359259/APB_master.v.v\n             data/full_repos/permissive/516359259,data/full_repos/permissive/516359259/APB_master.v.sv\n             APB_master.v\n             APB_master.v.v\n             APB_master.v.sv\n             obj_dir/APB_master.v\n             obj_dir/APB_master.v.v\n             obj_dir/APB_master.v.sv\n%Error: data/full_repos/permissive/516359259/APB_top.v:2: Cannot find include file: APB_slave.v\n`include "APB_slave.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module APB_top(input PCLK,
               input PRESETn,
               input Transfer,
               input Wr_Rd,
               input [4:0] Address,
               input [31:0] write_data,
               output [31:0] read_data);
    
    wire [4:0] PADDR;
    wire [31:0] PWDATA,PRDATA;
    wire PSELx,PENABLE,PWRITE,PREADY,PSLVERR;
    
    APB_master Design_master(Transfer,Wr_Rd,Address,write_data,read_data,PCLK,PRESETn,PREADY,PRDATA,PSLVERR,PADDR,PSELx,PENABLE,PWRITE,PWDATA);
    APB_slave Design_slave(PCLK,PRESETn,PADDR,PSELx,PENABLE,PWRITE,PWDATA,PREADY,PRDATA,PSLVERR);
    
endmodule
module APB_top(input PCLK,
               input PRESETn,
               input Transfer,
               input Wr_Rd,
               input [4:0] Address,
               input [31:0] write_data,
               output [31:0] read_data);

    
    wire [4:0] PADDR;
    wire [31:0] PWDATA,PRDATA;
    wire PSELx,PENABLE,PWRITE,PREADY,PSLVERR;
    
    APB_master Design_master(Transfer,Wr_Rd,Address,write_data,read_data,PCLK,PRESETn,PREADY,PRDATA,PSLVERR,PADDR,PSELx,PENABLE,PWRITE,PWDATA);
    APB_slave Design_slave(PCLK,PRESETn,PADDR,PSELx,PENABLE,PWRITE,PWDATA,PREADY,PRDATA,PSLVERR);
    
endmodule