data/full_repos/permissive/494353034/rtl/src_top/relu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/src_top/relu.v:41: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                          : ... In instance relu\n   dout <= (dout_delay >>> 10);\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/src_top/relu.v:43: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                          : ... In instance relu\n   dout <= (dout_r >>> 10); \n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module relu
(
    input clk,
    input signed [31:0] din,  
    input ivalid,
    input state,
    output reg ovalid,   
    output reg signed [7:0] dout
);

	reg wren;
	reg [31:0] dout_r;
	reg [31:0] dout_delay;
	

	always@(posedge clk)begin
		if(ivalid)
			wren <= 1'b1;
		else
			wren <= 1'b0;
	end


	always@(posedge clk)begin
		if(din[31])
			dout_r <= 0;
		else
			dout_r <= din;
	end

	always@(posedge clk)begin
		dout_delay <= dout_r;
	end
	

	always@(posedge clk)begin
		if(state)
			dout <= (dout_delay >>> 10);
		else
			dout <= (dout_r >>> 10); 
	end
	
	always@(posedge clk)begin
		ovalid <= wren;
	end
	
endmodule
module relu
(
    input clk,
    input signed [31:0] din,  
    input ivalid,
    input state,
    output reg ovalid,   
    output reg signed [7:0] dout
);


	reg wren;
	reg [31:0] dout_r;
	reg [31:0] dout_delay;
	

	always@(posedge clk)begin
		if(ivalid)
			wren <= 1'b1;
		else
			wren <= 1'b0;
	end


	always@(posedge clk)begin
		if(din[31])
			dout_r <= 0;
		else
			dout_r <= din;
	end

	always@(posedge clk)begin
		dout_delay <= dout_r;
	end
	

	always@(posedge clk)begin
		if(state)
			dout <= (dout_delay >>> 10);
		else
			dout <= (dout_r >>> 10); 
	end
	
	always@(posedge clk)begin
		ovalid <= wren;
	end
	
endmodule