data/full_repos/permissive/437157208/src/Memory_system.v
1: b"%Error: data/full_repos/permissive/437157208/src/Memory_system.v:20: Cannot find file containing module: 'Data_Memory'\n Data_Memory RAM(.clk(clock), .Write_Enable_i(write_enable_i), .Write_Data_i(Write_Data), .Address_i(Address_i), .Read_Data_o(RAM_o));\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Memory\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Memory.v\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Memory.sv\n             Data_Memory\n             Data_Memory.v\n             Data_Memory.sv\n             obj_dir/Data_Memory\n             obj_dir/Data_Memory.v\n             obj_dir/Data_Memory.sv\n%Error: data/full_repos/permissive/437157208/src/Memory_system.v:21: Cannot find file containing module: 'Program_Memory'\n Program_Memory ROM(.Address_i(Address_i), .Instruction_o(ROM_o));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Memory_system.v:22: Cannot find file containing module: 'MUX2_1'\n MUX2_1 M1(.data_1(ROM_o), .data_2(RAM_o), .selector(selection), .data_o(Instruction_o));\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Memory_system
#
(
	parameter MEMORY_DEPTH 	= 64,
	parameter WIDTH 			= 32
)
(
	input write_enable_i, clock,
	input [WIDTH-1:0] Write_Data,
	input [WIDTH-1:0] Address_i,
	
	output [WIDTH-1:0] Instruction_o
);

	wire [WIDTH-1:0] ROM_o, RAM_o;
	wire selection;
	reg [WIDTH-1:0] data_1 = 32'h10000000;
	
	assign selection = (Address_i < data_1) ? 1'b1 : 1'b0;
	Data_Memory RAM(.clk(clock), .Write_Enable_i(write_enable_i), .Write_Data_i(Write_Data), .Address_i(Address_i), .Read_Data_o(RAM_o));
	Program_Memory ROM(.Address_i(Address_i), .Instruction_o(ROM_o));
	MUX2_1 M1(.data_1(ROM_o), .data_2(RAM_o), .selector(selection), .data_o(Instruction_o));
	
endmodule
module Memory_system
#
(
	parameter MEMORY_DEPTH 	= 64,
	parameter WIDTH 			= 32
)
(
	input write_enable_i, clock,
	input [WIDTH-1:0] Write_Data,
	input [WIDTH-1:0] Address_i,
	
	output [WIDTH-1:0] Instruction_o
);


	wire [WIDTH-1:0] ROM_o, RAM_o;
	wire selection;
	reg [WIDTH-1:0] data_1 = 32'h10000000;
	
	assign selection = (Address_i < data_1) ? 1'b1 : 1'b0;
	Data_Memory RAM(.clk(clock), .Write_Enable_i(write_enable_i), .Write_Data_i(Write_Data), .Address_i(Address_i), .Read_Data_o(RAM_o));
	Program_Memory ROM(.Address_i(Address_i), .Instruction_o(ROM_o));
	MUX2_1 M1(.data_1(ROM_o), .data_2(RAM_o), .selector(selection), .data_o(Instruction_o));
	
endmodule