data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/cachelib/v_rtl/dut_Add2Mul2u8u8Mul2u8u8_1.v
data/verilator_xmls/1e7eeb91-a328-430f-ace8-e96a2f78b22c.xml
module dut_Add2Mul2u8u8Mul2u8u8_1 (
	in4,
	in3,
	in2,
	in1,
	out1
	);
input [7:0] in4,
	in3,
	in2,
	in1;
output [16:0] out1;
wire [16:0] asc001;

wire [16:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in3 * in4);
assign asc001 = asc001_tmp_0
	+(in1 * in2);

assign out1 = asc001;
endmodule
module dut_Add2Mul2u8u8Mul2u8u8_1 (
	in4,
	in3,
	in2,
	in1,
	out1
	);

input [7:0] in4,
	in3,
	in2,
	in1;
output [16:0] out1;
wire [16:0] asc001;

wire [16:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in3 * in4);
assign asc001 = asc001_tmp_0
	+(in1 * in2);

assign out1 = asc001;
endmodule