data/full_repos/permissive/508266496/sources/RegisterFile.v
data/verilator_xmls/44d5aa21-3f97-45b5-b03b-1ea796c6fc38.xml
module RegisterFile(
input[2:0] RS,
input[2:0] RT,
input[2:0] RD,
input[15:0] WriteData,
output[15:0] ReadRS,
output[15:0] ReadRT,
input RegWrite,
input Clock);

reg [15:0] Registers[7:0];

always @(posedge Clock)
begin  

if(RegWrite)
begin
Registers[RD] <= WriteData;
end

end

assign ReadRS = Registers[RS];
assign ReadRT = Registers[RT];
endmodule
module RegisterFile(
input[2:0] RS,
input[2:0] RT,
input[2:0] RD,
input[15:0] WriteData,
output[15:0] ReadRS,
output[15:0] ReadRT,
input RegWrite,
input Clock);


reg [15:0] Registers[7:0];

always @(posedge Clock)
begin  

if(RegWrite)
begin
Registers[RD] <= WriteData;
end

end

assign ReadRS = Registers[RS];
assign ReadRT = Registers[RT];
endmodule