data/full_repos/permissive/450962776/processor/src/m21.v
data/verilator_xmls/6406b6ed-781e-4dcf-9f01-52d61380f0e8.xml
module m21(Y, D0, D1, S);

output Y;
input D0, D1, S;
wire T1, T2, Sbar;

and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);

endmodule
module m21(Y, D0, D1, S);


output Y;
input D0, D1, S;
wire T1, T2, Sbar;

and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);

endmodule