data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:41: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:49: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:57: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:65: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 19 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:12] = {19{in[31]}};   \n                       ^\n%Error: Exiting due to 4 warning(s)\n'
module registers(input clk, reg_write,
                 input [4:0] read_reg1, read_reg2, write_reg,
                 input [31:0] write_data,
                 output [31:0] read_data1, read_data2);
    integer i;
    reg [31:0] registers[31:0];
    reg [31:0] reg_read_data1, reg_read_data2;
   
    initial begin    
        for(i = 0; i < 32; i = i + 1) 
            registers[i] = i;
    end
    
    always@(posedge clk) begin
        if(reg_write)
            registers[write_reg] = write_data;
    end
    always@(read_reg1 or read_reg2) begin
        reg_read_data1 = registers[read_reg1];
        reg_read_data2 = registers[read_reg2];
    end
    
    assign read_data1 = reg_read_data1;
    assign read_data2 = reg_read_data2;
endmodule
module registers(input clk, reg_write,
                 input [4:0] read_reg1, read_reg2, write_reg,
                 input [31:0] write_data,
                 output [31:0] read_data1, read_data2);

    integer i;
    reg [31:0] registers[31:0];
    reg [31:0] reg_read_data1, reg_read_data2;
   
    initial begin    
        for(i = 0; i < 32; i = i + 1) 
            registers[i] = i;
    end
    
    always@(posedge clk) begin
        if(reg_write)
            registers[write_reg] = write_data;
    end
    always@(read_reg1 or read_reg2) begin
        reg_read_data1 = registers[read_reg1];
        reg_read_data2 = registers[read_reg2];
    end
    
    assign read_data1 = reg_read_data1;
    assign read_data2 = reg_read_data2;
endmodule