data/full_repos/permissive/460328193/ipa_proj_pipe/Memory.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/460328193/ipa_proj_pipe/Memory.v:16: Little bit endian vector: MSB < LSB of bit range: 0:63\nreg [0:63]data_memory[127:0];\n    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/460328193/ipa_proj_pipe/Memory.v:63: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                              : ... In instance Memory\n        valM<=data_memory[mem_addr];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/460328193/ipa_proj_pipe/Memory.v:78: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                              : ... In instance Memory\n        data_memory[mem_addr]<=mem_data;\n                   ^\n%Error: Exiting due to 3 warning(s)\n'
module Memory(icode,valE,valA,instr_valid,imem_error,valM,clock,stat); 

input [3:0] icode;
input [63:0] valE;
input [63:0] valA;
input instr_valid;
input imem_error;
input clock;
output reg [63:0] valM;
output reg [1:0] stat;

reg [63:0] mem_addr,mem_data;
reg mem_read=1'b0;
reg mem_write=1'b0;
reg [0:63]data_memory[127:0];

reg dmem_error=1'b0;

initial 
    begin
		$readmemh("DATA_MEM.txt", data_memory, 0, 127);
	end

always @(*)     
begin
	if(icode==4'h4)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end	
	else if(icode==4'h5)
	begin
		mem_read<=1'b1;
		mem_addr<=valE;
	end
	else if(icode==4'h8)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end
	else if(icode==4'h9)
	begin
		mem_read<=1'b1;
		mem_addr<=valA;
	end
	else if(icode==4'hA)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end
	else if(icode==4'hB)
	begin
		mem_read<=1'b1;
		mem_addr<=valA;
	end
	if(mem_addr>127)
		dmem_error<=1'b1;
    else if(mem_read==1'b1)
        valM<=data_memory[mem_addr];
	if(icode==4'h0)
		stat<=2'b01;
	else if(imem_error==1'b1 || dmem_error==1'b1)
		stat<=2'b10;
	else if(instr_valid==0)
		stat<=2'b11;
	else
		stat<=2'b00;
end

always @(clock)
begin
    if((mem_write==1'b1)&& mem_addr<127)
    begin
        data_memory[mem_addr]<=mem_data;
        $writememh("DATA_MEM.txt", data_memory, 0,127);
    end
end

endmodule
module Memory(icode,valE,valA,instr_valid,imem_error,valM,clock,stat);
 

input [3:0] icode;
input [63:0] valE;
input [63:0] valA;
input instr_valid;
input imem_error;
input clock;
output reg [63:0] valM;
output reg [1:0] stat;

reg [63:0] mem_addr,mem_data;
reg mem_read=1'b0;
reg mem_write=1'b0;
reg [0:63]data_memory[127:0];

reg dmem_error=1'b0;

initial 
    begin
		$readmemh("DATA_MEM.txt", data_memory, 0, 127);
	end

always @(*)     
begin
	if(icode==4'h4)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end	
	else if(icode==4'h5)
	begin
		mem_read<=1'b1;
		mem_addr<=valE;
	end
	else if(icode==4'h8)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end
	else if(icode==4'h9)
	begin
		mem_read<=1'b1;
		mem_addr<=valA;
	end
	else if(icode==4'hA)
	begin
		mem_write<=1'b1;
		mem_addr<=valE;
		mem_data<=valA;
	end
	else if(icode==4'hB)
	begin
		mem_read<=1'b1;
		mem_addr<=valA;
	end
	if(mem_addr>127)
		dmem_error<=1'b1;
    else if(mem_read==1'b1)
        valM<=data_memory[mem_addr];
	if(icode==4'h0)
		stat<=2'b01;
	else if(imem_error==1'b1 || dmem_error==1'b1)
		stat<=2'b10;
	else if(instr_valid==0)
		stat<=2'b11;
	else
		stat<=2'b00;
end

always @(clock)
begin
    if((mem_write==1'b1)&& mem_addr<127)
    begin
        data_memory[mem_addr]<=mem_data;
        $writememh("DATA_MEM.txt", data_memory, 0,127);
    end
end

endmodule