data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module ic1_tags(input [5:0]addra,
                input [5:0]addrb,
                input clka,
                input clkb,
                input [43:0]dina,
                input [43:0]dinb,
                output [43:0]douta,
                output [43:0]doutb,
		input wea,
		input web);

	reg 	[44-1:0]mem[0:63];


        reg [6-1:0]r_addra;
        reg [6-1:0]r_addrb;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clkb)
		r_addrb <= addrb;
	always @(posedge clka)
	if (wea)
		mem[addra] <= dina;


	always @(posedge clkb)
	if (web)
		mem[addrb] <= dinb;

	reg [44-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];

	reg [44-1:0]outb;
	assign doutb = outb;
	always @(*)
	if (clkb)
		outb = mem[r_addrb];

endmodule
module ic1_tags(input [5:0]addra,
                input [5:0]addrb,
                input clka,
                input clkb,
                input [43:0]dina,
                input [43:0]dinb,
                output [43:0]douta,
                output [43:0]doutb,
		input wea,
		input web);


	reg 	[44-1:0]mem[0:63];


        reg [6-1:0]r_addra;
        reg [6-1:0]r_addrb;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clkb)
		r_addrb <= addrb;
	always @(posedge clka)
	if (wea)
		mem[addra] <= dina;


	always @(posedge clkb)
	if (web)
		mem[addrb] <= dinb;

	reg [44-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];

	reg [44-1:0]outb;
	assign doutb = outb;
	always @(*)
	if (clkb)
		outb = mem[r_addrb];

endmodule