data/full_repos/permissive/461249624/sample_project/src/testbench.v
1: b'%Error: data/full_repos/permissive/461249624/sample_project/src/testbench.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("mux41bus_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/461249624/sample_project/src/testbench.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, mux_4a1bus_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461249624/sample_project/src/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #5 \n        ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_4a1bus_tb;
    reg [3:0] dato0, dato1, dato2, dato3;
    reg [1:0] seleccion;
    wire [3:0] salida;
    mux4a1Bus DUT (
        .D0(dato0),
        .D1(dato1),
        .D2(dato2),
        .D3(dato3),
        .S(seleccion),
        .Q(salida)
    );

    initial begin
        $dumpfile("mux41bus_tb.vcd");
        $dumpvars(0, mux_4a1bus_tb);
    end 

    initial begin 
        dato0 = 0;
        dato1 = 0;
        dato2 = 0;
        seleccion = 0;
        dato3 = 0;
        #10
        dato0 = 1;
        #5
        dato0 = 0;
        #5
        dato0 = 1;
        #5
        dato0 = 0;
        #5
        dato1 = 1;
        #5
        dato1 = 0;
        #5
        seleccion = 1;
        #10
        dato0 = 1;
        #5 
        dato0 = 0;
        $finish;
    end
endmodule
module mux_4a1bus_tb;

    reg [3:0] dato0, dato1, dato2, dato3;
    reg [1:0] seleccion;
    wire [3:0] salida;
    mux4a1Bus DUT (
        .D0(dato0),
        .D1(dato1),
        .D2(dato2),
        .D3(dato3),
        .S(seleccion),
        .Q(salida)
    );

    initial begin
        $dumpfile("mux41bus_tb.vcd");
        $dumpvars(0, mux_4a1bus_tb);
    end 

    initial begin 
        dato0 = 0;
        dato1 = 0;
        dato2 = 0;
        seleccion = 0;
        dato3 = 0;
        #10
        dato0 = 1;
        #5
        dato0 = 0;
        #5
        dato0 = 1;
        #5
        dato0 = 0;
        #5
        dato1 = 1;
        #5
        dato1 = 0;
        #5
        seleccion = 1;
        #10
        dato0 = 1;
        #5 
        dato0 = 0;
        $finish;
    end
endmodule