data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv
1: b'%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:12: Cannot find include file: chip_ids.vh\n    `include "chip_ids.vh" \n             ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog,data/full_repos/permissive/463204869/chip_ids.vh\n             data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog,data/full_repos/permissive/463204869/chip_ids.vh.v\n             data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog,data/full_repos/permissive/463204869/chip_ids.vh.sv\n             chip_ids.vh\n             chip_ids.vh.v\n             chip_ids.vh.sv\n             obj_dir/chip_ids.vh\n             obj_dir/chip_ids.vh.v\n             obj_dir/chip_ids.vh.sv\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:13: Cannot find include file: mod_ids.vh\n    ,`include "mod_ids.vh" \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:14: Cannot find include file: noc_parameter.vh\n    ,`include "noc_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:15: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:224: Cannot find include file: tb_ethernet.v\n`include "tb_ethernet.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:229: Cannot find include file: testcase.v\n`include "testcase.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:13: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/fpga_top/source/tb/systemverilog/tb_fpga_top.sv:67: syntax error, unexpected IDENTIFIER\nfpga_top #(\n^~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module short(in1, in1);
        inout in1;
    endmodule
module short(in1, in1);

        inout in1;
    endmodule