data/full_repos/permissive/507312280/rtl/core/sctr.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:11: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus] mem_wdata_i,        \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`MemBus] mem_wdata_i,        \n                       ^\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:12: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus] mem_addr_i,     \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [3:0] mem_wem_i,              \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire mem_en_i,                     \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [`MemBus] mem_rdata_o,        \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:16: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus] mem_rdata_o,        \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg csr_we_o,                     \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg iram_rd_o,       \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:24: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire div_start_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire div_ready_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire mult_inst_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire iram_rstn_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire halt_req_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire trap_in_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire trap_jump_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_mret_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg trap_stat_o, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemAddrBus]    sctr_axi_awaddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:38: Define or directive not defined: \'`MemAddrBus\'\n    output reg [`MemAddrBus]    sctr_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  sctr_axi_awvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:41: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                 sctr_axi_awready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [`MemBus]        sctr_axi_wdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:43: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        sctr_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  sctr_axi_wvalid , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:46: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  sctr_axi_wready , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [1:0]            sctr_axi_bresp  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:49: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  sctr_axi_bvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:50: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sctr_axi_bready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:52: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemAddrBus]    sctr_axi_araddr , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:52: Define or directive not defined: \'`MemAddrBus\'\n    output reg [`MemAddrBus]    sctr_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:54: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                  sctr_axi_arvalid, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:55: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                 sctr_axi_arready, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`MemBus]        sctr_axi_rdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:57: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus]        sctr_axi_rdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:59: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  sctr_axi_rvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:60: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sctr_axi_rready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:65: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg hx_valid \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/sctr.v:75: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin \n^~~~~~\n%Error: Exiting due to 40 error(s)\n'
module sctr (
    input clk,
    input rst_n,


    input wire  reg_we_i,
    input wire  csr_we_i,

    input wire [`MemBus] mem_wdata_i,
    input wire [`MemAddrBus] mem_addr_i,
    input wire mem_we_i,
    input wire [3:0] mem_wem_i,
    input wire mem_en_i,
    output reg [`MemBus] mem_rdata_o,


    output reg reg_we_o,
    output reg csr_we_o,
    output reg iram_rd_o,


    input wire div_start_i,
    input wire div_ready_i,
    input wire mult_inst_i,
    input wire iram_rstn_i,
    input wire halt_req_i,


    input wire trap_in_i,
    input wire trap_jump_i,
    input wire idex_mret_i,
    output reg trap_stat_o,



    output reg [`MemAddrBus]    sctr_axi_awaddr ,
    output reg [2:0]            sctr_axi_awprot ,
    output reg                  sctr_axi_awvalid,
    input  wire                 sctr_axi_awready,

    output reg [`MemBus]        sctr_axi_wdata  ,
    output reg [3:0]            sctr_axi_wstrb  ,
    output reg                  sctr_axi_wvalid ,
    input wire                  sctr_axi_wready ,

    input wire [1:0]            sctr_axi_bresp  ,
    input wire                  sctr_axi_bvalid ,
    output reg                  sctr_axi_bready ,

    output reg [`MemAddrBus]    sctr_axi_araddr ,
    output reg [2:0]            sctr_axi_arprot ,
    output reg                  sctr_axi_arvalid,
    input  wire                 sctr_axi_arready,

    input wire [`MemBus]        sctr_axi_rdata  ,
    input wire [1:0]            sctr_axi_rresp  ,
    input wire                  sctr_axi_rvalid ,
    output reg                  sctr_axi_rready ,




    output reg hx_valid


);




reg sta_p;
reg sta_n;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n)
        sta_p <= 1'b0;
    else
        sta_p <= sta_n;
end

always @(*) begin
    if (sta_p == 1'b0) begin
        if( ~trap_in_i & ~halt_req_i & (div_start_i | mult_inst_i | ((~mem_we_i) & sctr_axi_arvalid & sctr_axi_arready)))
            sta_n = 1'b1;
        else
            sta_n = 1'b0;
    end 
    else begin
        if( div_ready_i | mult_inst_i | trap_in_i | halt_req_i | (sctr_axi_rvalid & sctr_axi_rready & sctr_axi_rresp==2'b00))
            sta_n = 1'b0;
        else
            sta_n = 1'b1;
    end
end

always @(*) begin
    if (sta_p == 1'b0) begin
        if( div_start_i | mult_inst_i | iram_rstn_i | trap_in_i | halt_req_i | (mem_en_i & (~mem_we_i)) | (mem_en_i & mem_we_i & ~(sctr_axi_wready | sctr_axi_awready)))
            hx_valid = 1'b0;
        else
            hx_valid = 1'b1;
    end
    else begin
        if( ~trap_in_i & ~halt_req_i & (div_ready_i | mult_inst_i | (sctr_axi_rvalid & sctr_axi_rready & sctr_axi_rresp==2'b00 )))
            hx_valid = 1'b1;
        else
            hx_valid = 1'b0;
    end
end


always @(*) begin
    if(hx_valid) begin
        reg_we_o = reg_we_i;
        csr_we_o = csr_we_i;
        iram_rd_o = 1'b1;
    end
    else begin
        reg_we_o = 1'b0;
        csr_we_o = 1'b0;
        if(trap_jump_i)
            iram_rd_o = 1'b1;
        else
            iram_rd_o = 1'b0;
    end
end

always @(*) begin
    sctr_axi_awprot  = 0;
    sctr_axi_arprot  = 0;
    sctr_axi_bready  = 1;
    sctr_axi_rready  = 1'b1;
    if(sta_p == 1'b0) begin
        mem_rdata_o      = 0;
        sctr_axi_awaddr  = {mem_addr_i[31:2], 2'b00};
        sctr_axi_awvalid = mem_en_i & ~trap_in_i & ~halt_req_i;
        sctr_axi_wdata   = mem_wdata_i;
        sctr_axi_wstrb   = mem_wem_i;
        sctr_axi_wvalid  = mem_en_i & mem_we_i & ~trap_in_i & ~halt_req_i;
        sctr_axi_araddr  = {mem_addr_i[31:2], 2'b00};
        sctr_axi_arvalid = mem_en_i & ~mem_we_i & ~trap_in_i & ~halt_req_i;
    end
    else begin
        mem_rdata_o      = sctr_axi_rdata;
        sctr_axi_awaddr  = 0;
        sctr_axi_awvalid = 0;
        sctr_axi_wdata   = 0;
        sctr_axi_wstrb   = 0;
        sctr_axi_wvalid  = 0;
        sctr_axi_araddr  = 0;
        sctr_axi_arvalid = 0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        trap_stat_o <= 0;
    end 
    else begin
        if(~trap_stat_o)
            if(trap_jump_i)
                trap_stat_o <= 1;
            else begin end
        else
            if(idex_mret_i & hx_valid)
                trap_stat_o <= 0;
            else begin end
    end
end

endmodule
module sctr (
    input clk,
    input rst_n,


    input wire  reg_we_i,
    input wire  csr_we_i,

    input wire [`MemBus] mem_wdata_i,
    input wire [`MemAddrBus] mem_addr_i,
    input wire mem_we_i,
    input wire [3:0] mem_wem_i,
    input wire mem_en_i,
    output reg [`MemBus] mem_rdata_o,


    output reg reg_we_o,
    output reg csr_we_o,
    output reg iram_rd_o,


    input wire div_start_i,
    input wire div_ready_i,
    input wire mult_inst_i,
    input wire iram_rstn_i,
    input wire halt_req_i,


    input wire trap_in_i,
    input wire trap_jump_i,
    input wire idex_mret_i,
    output reg trap_stat_o,



    output reg [`MemAddrBus]    sctr_axi_awaddr ,
    output reg [2:0]            sctr_axi_awprot ,
    output reg                  sctr_axi_awvalid,
    input  wire                 sctr_axi_awready,

    output reg [`MemBus]        sctr_axi_wdata  ,
    output reg [3:0]            sctr_axi_wstrb  ,
    output reg                  sctr_axi_wvalid ,
    input wire                  sctr_axi_wready ,

    input wire [1:0]            sctr_axi_bresp  ,
    input wire                  sctr_axi_bvalid ,
    output reg                  sctr_axi_bready ,

    output reg [`MemAddrBus]    sctr_axi_araddr ,
    output reg [2:0]            sctr_axi_arprot ,
    output reg                  sctr_axi_arvalid,
    input  wire                 sctr_axi_arready,

    input wire [`MemBus]        sctr_axi_rdata  ,
    input wire [1:0]            sctr_axi_rresp  ,
    input wire                  sctr_axi_rvalid ,
    output reg                  sctr_axi_rready ,




    output reg hx_valid


);





reg sta_p;
reg sta_n;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n)
        sta_p <= 1'b0;
    else
        sta_p <= sta_n;
end

always @(*) begin
    if (sta_p == 1'b0) begin
        if( ~trap_in_i & ~halt_req_i & (div_start_i | mult_inst_i | ((~mem_we_i) & sctr_axi_arvalid & sctr_axi_arready)))
            sta_n = 1'b1;
        else
            sta_n = 1'b0;
    end 
    else begin
        if( div_ready_i | mult_inst_i | trap_in_i | halt_req_i | (sctr_axi_rvalid & sctr_axi_rready & sctr_axi_rresp==2'b00))
            sta_n = 1'b0;
        else
            sta_n = 1'b1;
    end
end

always @(*) begin
    if (sta_p == 1'b0) begin
        if( div_start_i | mult_inst_i | iram_rstn_i | trap_in_i | halt_req_i | (mem_en_i & (~mem_we_i)) | (mem_en_i & mem_we_i & ~(sctr_axi_wready | sctr_axi_awready)))
            hx_valid = 1'b0;
        else
            hx_valid = 1'b1;
    end
    else begin
        if( ~trap_in_i & ~halt_req_i & (div_ready_i | mult_inst_i | (sctr_axi_rvalid & sctr_axi_rready & sctr_axi_rresp==2'b00 )))
            hx_valid = 1'b1;
        else
            hx_valid = 1'b0;
    end
end


always @(*) begin
    if(hx_valid) begin
        reg_we_o = reg_we_i;
        csr_we_o = csr_we_i;
        iram_rd_o = 1'b1;
    end
    else begin
        reg_we_o = 1'b0;
        csr_we_o = 1'b0;
        if(trap_jump_i)
            iram_rd_o = 1'b1;
        else
            iram_rd_o = 1'b0;
    end
end

always @(*) begin
    sctr_axi_awprot  = 0;
    sctr_axi_arprot  = 0;
    sctr_axi_bready  = 1;
    sctr_axi_rready  = 1'b1;
    if(sta_p == 1'b0) begin
        mem_rdata_o      = 0;
        sctr_axi_awaddr  = {mem_addr_i[31:2], 2'b00};
        sctr_axi_awvalid = mem_en_i & ~trap_in_i & ~halt_req_i;
        sctr_axi_wdata   = mem_wdata_i;
        sctr_axi_wstrb   = mem_wem_i;
        sctr_axi_wvalid  = mem_en_i & mem_we_i & ~trap_in_i & ~halt_req_i;
        sctr_axi_araddr  = {mem_addr_i[31:2], 2'b00};
        sctr_axi_arvalid = mem_en_i & ~mem_we_i & ~trap_in_i & ~halt_req_i;
    end
    else begin
        mem_rdata_o      = sctr_axi_rdata;
        sctr_axi_awaddr  = 0;
        sctr_axi_awvalid = 0;
        sctr_axi_wdata   = 0;
        sctr_axi_wstrb   = 0;
        sctr_axi_wvalid  = 0;
        sctr_axi_araddr  = 0;
        sctr_axi_arvalid = 0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        trap_stat_o <= 0;
    end 
    else begin
        if(~trap_stat_o)
            if(trap_jump_i)
                trap_stat_o <= 1;
            else begin end
        else
            if(idex_mret_i & hx_valid)
                trap_stat_o <= 0;
            else begin end
    end
end

endmodule