data/full_repos/permissive/439731184/4_bit_counter_test.v
1: b'%Error: data/full_repos/permissive/439731184/4_bit_counter_test.v:1: Cannot find include file: 4_bit_counter.v\n`include "4_bit_counter.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/4_bit_counter.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/4_bit_counter.v.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/4_bit_counter.v.sv\n             4_bit_counter.v\n             4_bit_counter.v.v\n             4_bit_counter.v.sv\n             obj_dir/4_bit_counter.v\n             obj_dir/4_bit_counter.v.v\n             obj_dir/4_bit_counter.v.sv\n%Error: data/full_repos/permissive/439731184/4_bit_counter_test.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g\\t%b\\t%b\\t%b\\t%b", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/4_bit_counter_test.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/439731184/4_bit_counter_test.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, clock, reset, enable, counter_out);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #5 enable = 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #100 enable = 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/4_bit_counter_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock;  \n    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module four_bit_counter_tb();


reg clock, reset, enable;
wire [3:0] counter_out;


initial begin
    $display ("time\tclk\treset\tenable\tcounter");
    $monitor ("%g\t%b\t%b\t%b\t%b", 
              $time, clock, reset, enable, counter_out);
    $dumpfile("test.vcd");
    $dumpvars(0, clock, reset, enable, counter_out);
    clock = 1;
    reset = 0;
    enable = 0;
    #5 reset = 1;
    #10 reset = 0;
    #5 enable = 1;
    #100 enable = 1;
    #10 $finish;
end


always begin
    #5 clock = ~clock;
end


four_bit_counter U_counter(
    clock, 
    reset,
    enable, 
    counter_out
);

endmodule
module four_bit_counter_tb();



reg clock, reset, enable;
wire [3:0] counter_out;


initial begin
    $display ("time\tclk\treset\tenable\tcounter");
    $monitor ("%g\t%b\t%b\t%b\t%b", 
              $time, clock, reset, enable, counter_out);
    $dumpfile("test.vcd");
    $dumpvars(0, clock, reset, enable, counter_out);
    clock = 1;
    reset = 0;
    enable = 0;
    #5 reset = 1;
    #10 reset = 0;
    #5 enable = 1;
    #100 enable = 1;
    #10 $finish;
end


always begin
    #5 clock = ~clock;
end


four_bit_counter U_counter(
    clock, 
    reset,
    enable, 
    counter_out
);

endmodule