data/full_repos/permissive/439635488/TRY_BEEP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/439635488/TRY_BEEP.v:10: Signal definition not found, creating implicitly: \'clk_div\'\ndivfreq_bp dd0 (clk, clk_div);\n                     ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/439635488/TRY_BEEP.v:40: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                  : ... In instance TRY_BEEP.dd0\n          Count <= 25\'b0;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module TRY_BEEP(clk, life_change, beep);
input  clk;
input  life_change;
output beep;
reg  beep_r;
reg[1:0]count;

assign beep = beep_r;

divfreq_bp dd0 (clk, clk_div);

always @(posedge clk_div or negedge life_change)
	if (!life_change) begin
		count <= count + 1'b1;
	end
	else begin
		count <= count + 1'b1;
		beep_r <= 1'b1;
		if(count == 2'b11) begin
		  count <= 2'b0;
		  beep_r <= !beep_r;
		end
	end

endmodule
module TRY_BEEP(clk, life_change, beep);

input  clk;
input  life_change;
output beep;
reg  beep_r;
reg[1:0]count;

assign beep = beep_r;

divfreq_bp dd0 (clk, clk_div);

always @(posedge clk_div or negedge life_change)
	if (!life_change) begin
		count <= count + 1'b1;
	end
	else begin
		count <= count + 1'b1;
		beep_r <= 1'b1;
		if(count == 2'b11) begin
		  count <= 2'b0;
		  beep_r <= !beep_r;
		end
	end

endmodule