data/full_repos/permissive/52682338/Cartridge/mvs_prog.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:67: Signal definition not found, creating implicitly: \'nPORTOE\'\n                                                                              : ... Suggested alternative: \'nPORTOEL\'\n assign nPORTOE = nPORTOEL & nPORTOEU;\n        ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:68: Signal definition not found, creating implicitly: \'nP1OE\'\n                                                                              : ... Suggested alternative: \'nPORTOE\'\n assign nP1OE = nROMOE & nPORTOE;\n        ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:81: Signal definition not found, creating implicitly: \'nV1_OE\'\n                                                                              : ... Suggested alternative: \'nP1OE\'\n assign nV1_OE = (V_ADDR[22:21] == 2\'b00) ? 1\'b0 : 1\'b1;\n        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:82: Signal definition not found, creating implicitly: \'nV2_OE\'\n                                                                              : ... Suggested alternative: \'nV1_OE\'\n assign nV2_OE = (V_ADDR[22:21] == 2\'b01) ? 1\'b0 : 1\'b1;\n        ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:59: Cannot find file containing module: \'pcm\'\n pcm PCM(CLK_68KCLKB, nSDROE, RMPX, nSDPOE, PMPX, RAD, RA_L, RA_U, PAD, PA, V_DATA, V_ADDR);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/pcm\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/pcm.v\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/pcm.sv\n             pcm\n             pcm.v\n             pcm.sv\n             obj_dir/pcm\n             obj_dir/pcm.v\n             obj_dir/pcm.sv\n%Error: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:64: Cannot find file containing module: \'rom_p1\'\n rom_p1 P1({nPORTADRS, M68K_ADDR[19:1]}, M68K_DATA, 1\'b0, nP1OE);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:77: Cannot find file containing module: \'rom_v1\'\n rom_v1 V1(V_ADDR[21:0], V_DATA, nV1_OE);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/mvs_prog.v:78: Cannot find file containing module: \'rom_v2\'\n rom_v2 V2(V_ADDR[21:0], V_DATA, nV2_OE);\n ^~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module mvs_prog(
	input nSDROE, RMPX,
	input [23:20] RA_U,
	input [9:8] RA_L,
	
	input nSDPOE, PMPX,
	input [11:8] PA,
	
	input nSLOTCS,
	input nPORTADRS, nPORTWEL, nPORTWEU, nPORTOEL, nPORTOEU,
	input nROMOEL, nROMOEU,
	
	input nAS, M68K_RW,
	inout [15:0] M68K_DATA,
	input [19:1] M68K_ADDR,
	input CLK_68KCLKB,
	output nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	input nROMOE,
	
	input CLK_4MB, nRESET,

	inout [7:0] PAD,
	inout [7:0] RAD
);


	reg [23:0] V1_ADDR;
	reg [23:0] V2_ADDR;
	wire [23:0] V_ADDR;
	wire [7:0] V_DATA;
	

	

	assign nROMWAIT = 1'b1;
	assign nPWAIT0 = 1'b1;
	assign nPWAIT1 = 1'b1;
	assign PDTACK = 1'b1;
	

	pcm PCM(CLK_68KCLKB, nSDROE, RMPX, nSDPOE, PMPX, RAD, RA_L, RA_U, PAD, PA, V_DATA, V_ADDR);
	



	rom_p1 P1({nPORTADRS, M68K_ADDR[19:1]}, M68K_DATA, 1'b0, nP1OE);
	

	assign nPORTOE = nPORTOEL & nPORTOEU;
	assign nP1OE = nROMOE & nPORTOE;
	


	




	rom_v1 V1(V_ADDR[21:0], V_DATA, nV1_OE);
	rom_v2 V2(V_ADDR[21:0], V_DATA, nV2_OE);
	

	assign nV1_OE = (V_ADDR[22:21] == 2'b00) ? 1'b0 : 1'b1;
	assign nV2_OE = (V_ADDR[22:21] == 2'b01) ? 1'b0 : 1'b1;
	


	
endmodule
module mvs_prog(
	input nSDROE, RMPX,
	input [23:20] RA_U,
	input [9:8] RA_L,
	
	input nSDPOE, PMPX,
	input [11:8] PA,
	
	input nSLOTCS,
	input nPORTADRS, nPORTWEL, nPORTWEU, nPORTOEL, nPORTOEU,
	input nROMOEL, nROMOEU,
	
	input nAS, M68K_RW,
	inout [15:0] M68K_DATA,
	input [19:1] M68K_ADDR,
	input CLK_68KCLKB,
	output nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	input nROMOE,
	
	input CLK_4MB, nRESET,

	inout [7:0] PAD,
	inout [7:0] RAD
);



	reg [23:0] V1_ADDR;
	reg [23:0] V2_ADDR;
	wire [23:0] V_ADDR;
	wire [7:0] V_DATA;
	

	

	assign nROMWAIT = 1'b1;
	assign nPWAIT0 = 1'b1;
	assign nPWAIT1 = 1'b1;
	assign PDTACK = 1'b1;
	

	pcm PCM(CLK_68KCLKB, nSDROE, RMPX, nSDPOE, PMPX, RAD, RA_L, RA_U, PAD, PA, V_DATA, V_ADDR);
	



	rom_p1 P1({nPORTADRS, M68K_ADDR[19:1]}, M68K_DATA, 1'b0, nP1OE);
	

	assign nPORTOE = nPORTOEL & nPORTOEU;
	assign nP1OE = nROMOE & nPORTOE;
	


	




	rom_v1 V1(V_ADDR[21:0], V_DATA, nV1_OE);
	rom_v2 V2(V_ADDR[21:0], V_DATA, nV2_OE);
	

	assign nV1_OE = (V_ADDR[22:21] == 2'b00) ? 1'b0 : 1'b1;
	assign nV2_OE = (V_ADDR[22:21] == 2'b01) ? 1'b0 : 1'b1;
	


	
endmodule