data/full_repos/permissive/505451992/serial_output.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h0\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h1\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h3\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h4\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h5\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h6\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h7\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h8\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h9\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'ha\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'hb\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'hc\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505451992/serial_output.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'hd\' generates 6 bits.\n                                                                       : ... In instance serial_output\n      case(SD_counter)\n      ^~~~\n%Error: Exiting due to 14 warning(s)\n'
module serial_output(
input clk,
input reset,
input [9:0] Position,
output SCL,
output SDA
    );
    
    wire [9:0] P;
    reg read_enable;
    reg [2:0] current_state;
    reg [2:0] next_state;
    reg SCL_R;
    reg SDA_A;
    reg Go;
    reg[9:0] counter;
    reg [6:0] SD_counter;
    
    assign P = read_enable ? Position : P;

  
    always@(posedge clk) begin
    if (counter < 100) begin
    counter <= counter + 1;
    Go <= 1;
    end
    else begin
    counter <= 0;
    Go <= 0;
    end
    end
    
    

    
    
    always@(posedge clk or posedge reset) begin
        
        if (reset)
            SD_counter <= 0;
        else begin
           if (!Go)
              SD_counter <= 0;
           else if (SD_counter < 14)
              SD_counter <= SD_counter +1;
              
        
        end    
    end
    
 
    
    
    always@ (posedge clk or posedge reset) begin

     if (reset)
       begin
          SCL_R <= 1;
          SDA_A <= 1;
          read_enable <=1;
       end
     else begin
      case(SD_counter)
       6'd0: begin
           read_enable <= 0;
            SCL_R <= 0;
            SDA_A <= 0;
       end

       6'd1: SDA_A <= P[0];  
       6'd2: SDA_A <= P[1];  
       6'd3: SDA_A <= P[2];  
       6'd4: SDA_A <= P[3];
       6'd5: SDA_A<= P[4];
       6'd6: SDA_A <= P[5];
       6'd7: SDA_A <= P[6];
       6'd8: SDA_A <= P[7];
       6'd9: SDA_A <= P[8];
       6'd10: SDA_A <= P[9];
       6'd11: SDA_A <= 1'bz;

       6'd12 : begin
           SCL_R <= 1;
           SDA_A <= 0;
       end
       
       6'd13: begin 
       SDA_A <= 1;
       read_enable <=1;
       end
       endcase
    end
   end
   
    assign SDA = SDA_A;
    assign SCL = ((SD_counter>=1)&&(SD_counter<=13)) ? clk:SCL_R;
   
   
   
   
   

endmodule
module serial_output(
input clk,
input reset,
input [9:0] Position,
output SCL,
output SDA
    );

    
    wire [9:0] P;
    reg read_enable;
    reg [2:0] current_state;
    reg [2:0] next_state;
    reg SCL_R;
    reg SDA_A;
    reg Go;
    reg[9:0] counter;
    reg [6:0] SD_counter;
    
    assign P = read_enable ? Position : P;

  
    always@(posedge clk) begin
    if (counter < 100) begin
    counter <= counter + 1;
    Go <= 1;
    end
    else begin
    counter <= 0;
    Go <= 0;
    end
    end
    
    

    
    
    always@(posedge clk or posedge reset) begin
        
        if (reset)
            SD_counter <= 0;
        else begin
           if (!Go)
              SD_counter <= 0;
           else if (SD_counter < 14)
              SD_counter <= SD_counter +1;
              
        
        end    
    end
    
 
    
    
    always@ (posedge clk or posedge reset) begin

     if (reset)
       begin
          SCL_R <= 1;
          SDA_A <= 1;
          read_enable <=1;
       end
     else begin
      case(SD_counter)
       6'd0: begin
           read_enable <= 0;
            SCL_R <= 0;
            SDA_A <= 0;
       end

       6'd1: SDA_A <= P[0];  
       6'd2: SDA_A <= P[1];  
       6'd3: SDA_A <= P[2];  
       6'd4: SDA_A <= P[3];
       6'd5: SDA_A<= P[4];
       6'd6: SDA_A <= P[5];
       6'd7: SDA_A <= P[6];
       6'd8: SDA_A <= P[7];
       6'd9: SDA_A <= P[8];
       6'd10: SDA_A <= P[9];
       6'd11: SDA_A <= 1'bz;

       6'd12 : begin
           SCL_R <= 1;
           SDA_A <= 0;
       end
       
       6'd13: begin 
       SDA_A <= 1;
       read_enable <=1;
       end
       endcase
    end
   end
   
    assign SDA = SDA_A;
    assign SCL = ((SD_counter>=1)&&(SD_counter<=13)) ? clk:SCL_R;
   
   
   
   
   

endmodule