data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv
1: b"%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:15: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport ariane_pkg::*;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:29: syntax error, unexpected IDENTIFIER, expecting ')' or ','\n    input  scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,      \n                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:33: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    l1_icache_miss_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:34: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    l1_dcache_miss_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:36: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    itlb_miss_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:37: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    dtlb_miss_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:39: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    sb_full_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:41: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                                    if_empty_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:43: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  exception_t                              ex_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:45: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  branchpredict_t                          resolved_branch_i\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:48: syntax error, unexpected ::, expecting ':'\n    logic [riscv::CSR_IF_EMPTY[4:0] : riscv::CSR_L1_ICACHE_MISS[4:0]][63:0] perf_counter_d, perf_counter_q;\n                ^~\n                                                                                          : ... Perhaps 'riscv' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/perf_counters.sv:72: syntax error, unexpected IDENTIFIER\n            for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin\n                                     ^\n%Error: Exiting due to 12 error(s)\n"
module perf_counters #(
    int unsigned NR_EXTERNAL_COUNTERS = 1
)(
    input  logic                                    clk_i,
    input  logic                                    rst_ni,
    input  logic                                    debug_mode_i,

    input  logic [4:0]                              addr_i,
    input  logic                                    we_i,
    input  logic [63:0]                             data_i,
    output logic [63:0]                             data_o,

    input  scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
    input  logic [NR_COMMIT_PORTS-1:0]              commit_ack_i,


    input  logic                                    l1_icache_miss_i,
    input  logic                                    l1_dcache_miss_i,

    input  logic                                    itlb_miss_i,
    input  logic                                    dtlb_miss_i,

    input  logic                                    sb_full_i,

    input  logic                                    if_empty_i,

    input  exception_t                              ex_i,
    input  logic                                    eret_i,
    input  branchpredict_t                          resolved_branch_i
);

    logic [riscv::CSR_IF_EMPTY[4:0] : riscv::CSR_L1_ICACHE_MISS[4:0]][63:0] perf_counter_d, perf_counter_q;

    always_comb begin : perf_counters
        perf_counter_d = perf_counter_q;
        data_o = 'b0;


        if (!debug_mode_i) begin



            if (l1_icache_miss_i)
                perf_counter_d[riscv::CSR_L1_ICACHE_MISS[4:0]] = perf_counter_q[riscv::CSR_L1_ICACHE_MISS[4:0]] + 1'b1;

            if (l1_dcache_miss_i)
                perf_counter_d[riscv::CSR_L1_DCACHE_MISS[4:0]] = perf_counter_q[riscv::CSR_L1_DCACHE_MISS[4:0]] + 1'b1;

            if (itlb_miss_i)
                perf_counter_d[riscv::CSR_ITLB_MISS[4:0]] = perf_counter_q[riscv::CSR_ITLB_MISS[4:0]] + 1'b1;

            if (dtlb_miss_i)
                perf_counter_d[riscv::CSR_DTLB_MISS[4:0]] = perf_counter_q[riscv::CSR_DTLB_MISS[4:0]] + 1'b1;


            for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin
                if (commit_ack_i[i]) begin
                    if (commit_instr_i[i].fu == LOAD)
                        perf_counter_d[riscv::CSR_LOAD[4:0]] = perf_counter_q[riscv::CSR_LOAD[4:0]] + 1'b1;

                    if (commit_instr_i[i].fu == STORE)
                        perf_counter_d[riscv::CSR_STORE[4:0]] = perf_counter_q[riscv::CSR_STORE[4:0]] + 1'b1;

                    if (commit_instr_i[i].fu == CTRL_FLOW)
                        perf_counter_d[riscv::CSR_BRANCH_JUMP[4:0]] = perf_counter_q[riscv::CSR_BRANCH_JUMP[4:0]] + 1'b1;



                    if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 && commit_instr_i[i].rd == 'b1)
                        perf_counter_d[riscv::CSR_CALL[4:0]] = perf_counter_q[riscv::CSR_CALL[4:0]] + 1'b1;


                    if (commit_instr_i[i].op == JALR && commit_instr_i[i].rs1 == 'b1)
                        perf_counter_d[riscv::CSR_RET[4:0]] = perf_counter_q[riscv::CSR_RET[4:0]] + 1'b1;
                end
            end

            if (ex_i.valid)
                perf_counter_d[riscv::CSR_EXCEPTION[4:0]] = perf_counter_q[riscv::CSR_EXCEPTION[4:0]] + 1'b1;

            if (eret_i)
                perf_counter_d[riscv::CSR_EXCEPTION_RET[4:0]] = perf_counter_q[riscv::CSR_EXCEPTION_RET[4:0]] + 1'b1;

            if (resolved_branch_i.valid && resolved_branch_i.is_mispredict)
                perf_counter_d[riscv::CSR_MIS_PREDICT[4:0]] = perf_counter_q[riscv::CSR_MIS_PREDICT[4:0]] + 1'b1;

            if (sb_full_i) begin
                perf_counter_d[riscv::CSR_SB_FULL[4:0]] = perf_counter_q[riscv::CSR_SB_FULL[4:0]] + 1'b1;
            end

            if (if_empty_i) begin
                perf_counter_d[riscv::CSR_IF_EMPTY[4:0]] = perf_counter_q[riscv::CSR_IF_EMPTY[4:0]] + 1'b1;
            end
        end


        data_o = perf_counter_q[addr_i];
        if (we_i) begin
            perf_counter_d[addr_i] = data_i;
        end
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
           perf_counter_q <= '0;
        end else begin
           perf_counter_q <= perf_counter_d;
        end
    end

endmodule
module perf_counters #(
    int unsigned NR_EXTERNAL_COUNTERS = 1
)(
    input  logic                                    clk_i,
    input  logic                                    rst_ni,
    input  logic                                    debug_mode_i,

    input  logic [4:0]                              addr_i,
    input  logic                                    we_i,
    input  logic [63:0]                             data_i,
    output logic [63:0]                             data_o,

    input  scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
    input  logic [NR_COMMIT_PORTS-1:0]              commit_ack_i,


    input  logic                                    l1_icache_miss_i,
    input  logic                                    l1_dcache_miss_i,

    input  logic                                    itlb_miss_i,
    input  logic                                    dtlb_miss_i,

    input  logic                                    sb_full_i,

    input  logic                                    if_empty_i,

    input  exception_t                              ex_i,
    input  logic                                    eret_i,
    input  branchpredict_t                          resolved_branch_i
);


    logic [riscv::CSR_IF_EMPTY[4:0] : riscv::CSR_L1_ICACHE_MISS[4:0]][63:0] perf_counter_d, perf_counter_q;

    always_comb begin : perf_counters
        perf_counter_d = perf_counter_q;
        data_o = 'b0;


        if (!debug_mode_i) begin



            if (l1_icache_miss_i)
                perf_counter_d[riscv::CSR_L1_ICACHE_MISS[4:0]] = perf_counter_q[riscv::CSR_L1_ICACHE_MISS[4:0]] + 1'b1;

            if (l1_dcache_miss_i)
                perf_counter_d[riscv::CSR_L1_DCACHE_MISS[4:0]] = perf_counter_q[riscv::CSR_L1_DCACHE_MISS[4:0]] + 1'b1;

            if (itlb_miss_i)
                perf_counter_d[riscv::CSR_ITLB_MISS[4:0]] = perf_counter_q[riscv::CSR_ITLB_MISS[4:0]] + 1'b1;

            if (dtlb_miss_i)
                perf_counter_d[riscv::CSR_DTLB_MISS[4:0]] = perf_counter_q[riscv::CSR_DTLB_MISS[4:0]] + 1'b1;


            for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin
                if (commit_ack_i[i]) begin
                    if (commit_instr_i[i].fu == LOAD)
                        perf_counter_d[riscv::CSR_LOAD[4:0]] = perf_counter_q[riscv::CSR_LOAD[4:0]] + 1'b1;

                    if (commit_instr_i[i].fu == STORE)
                        perf_counter_d[riscv::CSR_STORE[4:0]] = perf_counter_q[riscv::CSR_STORE[4:0]] + 1'b1;

                    if (commit_instr_i[i].fu == CTRL_FLOW)
                        perf_counter_d[riscv::CSR_BRANCH_JUMP[4:0]] = perf_counter_q[riscv::CSR_BRANCH_JUMP[4:0]] + 1'b1;



                    if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 && commit_instr_i[i].rd == 'b1)
                        perf_counter_d[riscv::CSR_CALL[4:0]] = perf_counter_q[riscv::CSR_CALL[4:0]] + 1'b1;


                    if (commit_instr_i[i].op == JALR && commit_instr_i[i].rs1 == 'b1)
                        perf_counter_d[riscv::CSR_RET[4:0]] = perf_counter_q[riscv::CSR_RET[4:0]] + 1'b1;
                end
            end

            if (ex_i.valid)
                perf_counter_d[riscv::CSR_EXCEPTION[4:0]] = perf_counter_q[riscv::CSR_EXCEPTION[4:0]] + 1'b1;

            if (eret_i)
                perf_counter_d[riscv::CSR_EXCEPTION_RET[4:0]] = perf_counter_q[riscv::CSR_EXCEPTION_RET[4:0]] + 1'b1;

            if (resolved_branch_i.valid && resolved_branch_i.is_mispredict)
                perf_counter_d[riscv::CSR_MIS_PREDICT[4:0]] = perf_counter_q[riscv::CSR_MIS_PREDICT[4:0]] + 1'b1;

            if (sb_full_i) begin
                perf_counter_d[riscv::CSR_SB_FULL[4:0]] = perf_counter_q[riscv::CSR_SB_FULL[4:0]] + 1'b1;
            end

            if (if_empty_i) begin
                perf_counter_d[riscv::CSR_IF_EMPTY[4:0]] = perf_counter_q[riscv::CSR_IF_EMPTY[4:0]] + 1'b1;
            end
        end


        data_o = perf_counter_q[addr_i];
        if (we_i) begin
            perf_counter_d[addr_i] = data_i;
        end
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
           perf_counter_q <= '0;
        end else begin
           perf_counter_q <= perf_counter_d;
        end
    end

endmodule