data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/corexxx/auc_mmulinit.v
data/verilator_xmls/5e489f58-5c99-4e23-8f7e-b9efb30e3241.xml
module auc_mmulinit
    (
     clk,
     rst,


     init_en,
     

     init_done,



     init_auvld,
     init_audat,

     init_opcode,
     init_auen,
     init_carry,
     

     init_ra,
     init_wa,
     init_we,
     init_wd
     );



parameter           WID   = 256;
parameter           CURWID = 256;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam          ZERO   = 0;
localparam          A24VL  = 256'd121665;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam          X2    = 7;
localparam          Z2    = 8;
localparam          X3    = 9;
localparam          Z3    = 10;

localparam          ACCIDENT   = 30;
localparam          A24   = 31;

localparam          X2VL   = 1;
localparam          Z2VL   = 0;
localparam          Z3VL   = 1;


localparam          ISWID    = 4;
localparam          I_IDLE   = 4'd0;
localparam          I_INITX2 = 4'd1;
localparam          I_INITZ2 = 4'd2;
localparam          I_INITX3 = 4'd3;
localparam          I_INITX32 = 4'd4;
localparam          I_INITZ3 = 4'd5;
localparam          I_INITA24= 4'd6;
localparam          I_INITK1 = 4'd7;
localparam          I_INITK2 = 4'd8;
localparam          I_INITK3 = 4'd9;




input     clk;
input     rst;
     

input     init_en;


output          init_done;



output [OPWID-1:0] init_opcode;
output             init_auen;
output             init_carry;

input [WID-1:0]    init_audat;
input              init_auvld;


output [AWID-1:0] init_ra;
output [AWID-1:0] init_wa;
output            init_we;
output [WID-1:0]  init_wd;





reg               init_done;

reg [ISWID-1:0] init_state;

wire      initisidle;

assign    initisidle = init_state == I_IDLE;

wire      initisinitx2; 

assign    initisinitx2 = init_state == I_INITX2;

wire      initisinitz2; 

assign    initisinitz2 = init_state == I_INITZ2;

wire      initisinitx3; 

assign    initisinitx3 = init_state == I_INITX3;

wire      initisinitx32; 

assign    initisinitx32 = init_state == I_INITX32;

wire      initisinitx32vld;

assign    initisinitx32vld = initisinitx32 & init_auvld;

wire      initisinitz3;

assign    initisinitz3 = init_state == I_INITZ3;

wire      initisinita24;

assign    initisinita24 = init_state == I_INITA24;

wire      initisinitk1;

assign    initisinitk1 = init_state == I_INITK1;

wire      initisinitk2;

assign    initisinitk2 = init_state == I_INITK2;

wire      initisinitk2vld;

assign    initisinitk2vld = initisinitk2 & init_auvld;

wire      initisinitk3;

assign    initisinitk3 = init_state == I_INITK3;

always@(posedge clk)
    begin
    if(rst)
        begin
        init_state <= I_IDLE;
        init_done <= 1'b0;
        end
    else
        begin
        if(init_en & initisidle)
            begin
            init_state <= I_INITX2;
            init_done <= 1'b0;
            end
        else if(initisinitx2)
            begin
            init_state <= I_INITZ2;
            init_done <= 1'b0;
            end        
        else if(initisinitz2)
            begin
            init_state <= I_INITX3;
            init_done <= 1'b0;
            end
        else if(initisinitx3)
            begin
            init_state <= I_INITX32;
            init_done <= 1'b0;
            end
        else if(initisinitx32vld)
            begin
            init_state <= I_INITZ3;
            init_done <= 1'b0;
            end
        else if(initisinitz3)
            begin
            init_state <= I_INITA24;
            init_done <= 1'b0;
            end
        else if(initisinita24)
            begin
            init_state <= I_INITK1;
            init_done <= 1'b0;
            end
        else if(initisinitk1)
            begin
            init_state <= I_INITK2;
            init_done <= 1'b0;
            end
        else if(initisinitk2vld)
            begin
            init_state <= I_INITK3;
            init_done <= 1'b0;
            end
        else if(initisinitk3)
            begin
            init_state <= I_IDLE;
            init_done <= 1'b1;
            end
        else
            begin
            init_state <= init_state;
            init_done <= 1'b0;
            end
        end
    end


reg [WID-1:0] kdecode;

always@(posedge clk)
    begin
    if(rst)
        begin
        kdecode <= 256'd0;
        end
    else
        begin
        if(initisinitk2vld)
            begin
            kdecode <= {1'b0,1'b1,init_audat[253:3],3'b0};
            end
        end
    end

reg [WID-1:0] init_wd;

always@(posedge clk)
    begin
    init_wd <= initisinitx2? X2VL:
               initisinitz2? Z2VL:
               initisinitx32? init_audat:
               initisinitz3? Z3VL:
               initisinita24? A24VL:
               initisinitk3? kdecode:
               ZRRAM;
    end

reg [AWID-1:0] init_wa;

always@(posedge clk)
    begin
    init_wa <= initisinitx2? X2:
               initisinitz2? Z2:
               initisinitx32? X3:
               initisinitz3? Z3:
               initisinita24? A24:
               initisinitk3? K_NUM:
               ACCIDENT;
    end

reg init_we;

always@(posedge clk)
    begin
    init_we <= initisinitx2
               | initisinitz2
               | initisinitx32vld
               | initisinitz3
               | initisinita24 
               | initisinitk3;
    end

reg [AWID-1:0] init_ra;

always@(posedge clk)
    begin
    init_ra <= initisinitk1? K_NUM:
               initisinitk2? ZRRAM:
               initisinitx3? X_G:
               initisinitx32? ZRRAM:
               ZRRAM; 
    end


assign init_carry = 1'b0;
assign init_opcode = 4'b0100;

reg    init_auen;

always@(posedge clk)
    begin
    if(rst)
        begin
        init_auen <= 1'b0;
        end
    else
        begin
        if(initisinitx3)
            begin
            init_auen <= 1'b1;
            end
        else if(initisinitk1)
            begin
            init_auen <= 1'b1;
            end
        else
            begin
            init_auen <= 1'b0;
            end
        end
    end

endmodule
module auc_mmulinit
    (
     clk,
     rst,


     init_en,
     

     init_done,



     init_auvld,
     init_audat,

     init_opcode,
     init_auen,
     init_carry,
     

     init_ra,
     init_wa,
     init_we,
     init_wd
     );




parameter           WID   = 256;
parameter           CURWID = 256;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam          ZERO   = 0;
localparam          A24VL  = 256'd121665;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam          X2    = 7;
localparam          Z2    = 8;
localparam          X3    = 9;
localparam          Z3    = 10;

localparam          ACCIDENT   = 30;
localparam          A24   = 31;

localparam          X2VL   = 1;
localparam          Z2VL   = 0;
localparam          Z3VL   = 1;


localparam          ISWID    = 4;
localparam          I_IDLE   = 4'd0;
localparam          I_INITX2 = 4'd1;
localparam          I_INITZ2 = 4'd2;
localparam          I_INITX3 = 4'd3;
localparam          I_INITX32 = 4'd4;
localparam          I_INITZ3 = 4'd5;
localparam          I_INITA24= 4'd6;
localparam          I_INITK1 = 4'd7;
localparam          I_INITK2 = 4'd8;
localparam          I_INITK3 = 4'd9;




input     clk;
input     rst;
     

input     init_en;


output          init_done;



output [OPWID-1:0] init_opcode;
output             init_auen;
output             init_carry;

input [WID-1:0]    init_audat;
input              init_auvld;


output [AWID-1:0] init_ra;
output [AWID-1:0] init_wa;
output            init_we;
output [WID-1:0]  init_wd;





reg               init_done;

reg [ISWID-1:0] init_state;

wire      initisidle;

assign    initisidle = init_state == I_IDLE;

wire      initisinitx2; 

assign    initisinitx2 = init_state == I_INITX2;

wire      initisinitz2; 

assign    initisinitz2 = init_state == I_INITZ2;

wire      initisinitx3; 

assign    initisinitx3 = init_state == I_INITX3;

wire      initisinitx32; 

assign    initisinitx32 = init_state == I_INITX32;

wire      initisinitx32vld;

assign    initisinitx32vld = initisinitx32 & init_auvld;

wire      initisinitz3;

assign    initisinitz3 = init_state == I_INITZ3;

wire      initisinita24;

assign    initisinita24 = init_state == I_INITA24;

wire      initisinitk1;

assign    initisinitk1 = init_state == I_INITK1;

wire      initisinitk2;

assign    initisinitk2 = init_state == I_INITK2;

wire      initisinitk2vld;

assign    initisinitk2vld = initisinitk2 & init_auvld;

wire      initisinitk3;

assign    initisinitk3 = init_state == I_INITK3;

always@(posedge clk)
    begin
    if(rst)
        begin
        init_state <= I_IDLE;
        init_done <= 1'b0;
        end
    else
        begin
        if(init_en & initisidle)
            begin
            init_state <= I_INITX2;
            init_done <= 1'b0;
            end
        else if(initisinitx2)
            begin
            init_state <= I_INITZ2;
            init_done <= 1'b0;
            end        
        else if(initisinitz2)
            begin
            init_state <= I_INITX3;
            init_done <= 1'b0;
            end
        else if(initisinitx3)
            begin
            init_state <= I_INITX32;
            init_done <= 1'b0;
            end
        else if(initisinitx32vld)
            begin
            init_state <= I_INITZ3;
            init_done <= 1'b0;
            end
        else if(initisinitz3)
            begin
            init_state <= I_INITA24;
            init_done <= 1'b0;
            end
        else if(initisinita24)
            begin
            init_state <= I_INITK1;
            init_done <= 1'b0;
            end
        else if(initisinitk1)
            begin
            init_state <= I_INITK2;
            init_done <= 1'b0;
            end
        else if(initisinitk2vld)
            begin
            init_state <= I_INITK3;
            init_done <= 1'b0;
            end
        else if(initisinitk3)
            begin
            init_state <= I_IDLE;
            init_done <= 1'b1;
            end
        else
            begin
            init_state <= init_state;
            init_done <= 1'b0;
            end
        end
    end


reg [WID-1:0] kdecode;

always@(posedge clk)
    begin
    if(rst)
        begin
        kdecode <= 256'd0;
        end
    else
        begin
        if(initisinitk2vld)
            begin
            kdecode <= {1'b0,1'b1,init_audat[253:3],3'b0};
            end
        end
    end

reg [WID-1:0] init_wd;

always@(posedge clk)
    begin
    init_wd <= initisinitx2? X2VL:
               initisinitz2? Z2VL:
               initisinitx32? init_audat:
               initisinitz3? Z3VL:
               initisinita24? A24VL:
               initisinitk3? kdecode:
               ZRRAM;
    end

reg [AWID-1:0] init_wa;

always@(posedge clk)
    begin
    init_wa <= initisinitx2? X2:
               initisinitz2? Z2:
               initisinitx32? X3:
               initisinitz3? Z3:
               initisinita24? A24:
               initisinitk3? K_NUM:
               ACCIDENT;
    end

reg init_we;

always@(posedge clk)
    begin
    init_we <= initisinitx2
               | initisinitz2
               | initisinitx32vld
               | initisinitz3
               | initisinita24 
               | initisinitk3;
    end

reg [AWID-1:0] init_ra;

always@(posedge clk)
    begin
    init_ra <= initisinitk1? K_NUM:
               initisinitk2? ZRRAM:
               initisinitx3? X_G:
               initisinitx32? ZRRAM:
               ZRRAM; 
    end


assign init_carry = 1'b0;
assign init_opcode = 4'b0100;

reg    init_auen;

always@(posedge clk)
    begin
    if(rst)
        begin
        init_auen <= 1'b0;
        end
    else
        begin
        if(initisinitx3)
            begin
            init_auen <= 1'b1;
            end
        else if(initisinitk1)
            begin
            init_auen <= 1'b1;
            end
        else
            begin
            init_auen <= 1'b0;
            end
        end
    end

endmodule