data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v
1: b'%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:67: Cannot find file containing module: \'local_gau_rom\'\n local_gau_rom U_local_coe (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/local_gau_rom\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/local_gau_rom.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/local_gau_rom.sv\n             local_gau_rom\n             local_gau_rom.v\n             local_gau_rom.sv\n             obj_dir/local_gau_rom\n             obj_dir/local_gau_rom.v\n             obj_dir/local_gau_rom.sv\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:73: Cannot find file containing module: \'mul_desc\'\n  mul_desc U_mag_mul(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:91: Cannot find file containing module: \'dir36to8\'\n dir36to8 U_dir_trans(\n ^~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:99: Cannot find file containing module: \'window_rotate\'\n window_rotate U_window_rotate(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:196: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist0[0]<=hist0[0]+mul_tmp;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:197: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist0[1]<=hist0[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:198: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist0[2]<=hist0[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:199: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist0[3]<=hist0[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:200: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist0[4]<=hist0[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:201: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist0[5]<=hist0[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:202: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist0[6]<=hist0[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:203: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist0[7]<=hist0[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:208: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist1[0]<=hist1[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:209: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist1[1]<=hist1[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:210: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist1[2]<=hist1[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:211: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist1[3]<=hist1[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:212: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist1[4]<=hist1[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:213: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist1[5]<=hist1[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:214: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist1[6]<=hist1[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:215: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist1[7]<=hist1[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:220: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist2[0]<=hist2[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:221: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist2[1]<=hist2[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:222: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist2[2]<=hist2[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:223: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist2[3]<=hist2[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:224: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist2[4]<=hist2[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:225: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist2[5]<=hist2[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:226: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist2[6]<=hist2[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:227: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist2[7]<=hist2[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:232: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist3[0]<=hist3[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:233: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist3[1]<=hist3[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:234: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist3[2]<=hist3[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:235: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist3[3]<=hist3[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:236: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist3[4]<=hist3[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:237: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist3[5]<=hist3[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:238: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist3[6]<=hist3[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:239: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist3[7]<=hist3[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:244: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist4[0]<=hist4[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:245: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist4[1]<=hist4[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:246: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist4[2]<=hist4[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:247: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist4[3]<=hist4[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:248: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist4[4]<=hist4[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:249: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist4[5]<=hist4[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:250: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist4[6]<=hist4[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:251: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist4[7]<=hist4[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:256: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist5[0]<=hist5[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:257: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist5[1]<=hist5[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:258: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist5[2]<=hist5[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:259: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist5[3]<=hist5[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:260: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist5[4]<=hist5[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:261: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist5[5]<=hist5[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:262: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist5[6]<=hist5[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:263: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist5[7]<=hist5[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:268: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist6[0]<=hist6[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:269: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist6[1]<=hist6[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:270: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist6[2]<=hist6[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:271: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist6[3]<=hist6[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:272: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist6[4]<=hist6[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:273: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist6[5]<=hist6[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:274: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist6[6]<=hist6[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:275: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist6[7]<=hist6[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:280: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist7[0]<=hist7[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:281: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist7[1]<=hist7[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:282: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist7[2]<=hist7[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:283: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist7[3]<=hist7[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:284: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist7[4]<=hist7[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:285: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist7[5]<=hist7[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:286: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist7[6]<=hist7[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:287: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist7[7]<=hist7[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:292: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist8[0]<=hist8[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:293: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist8[1]<=hist8[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:294: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist8[2]<=hist8[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:295: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist8[3]<=hist8[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:296: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist8[4]<=hist8[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:297: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist8[5]<=hist8[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:298: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist8[6]<=hist8[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:299: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist8[7]<=hist8[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:304: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist9[0]<=hist9[0]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:305: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist9[1]<=hist9[1]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:306: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist9[2]<=hist9[2]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:307: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist9[3]<=hist9[3]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:308: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist9[4]<=hist9[4]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:309: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist9[5]<=hist9[5]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:310: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist9[6]<=hist9[6]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:311: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist9[7]<=hist9[7]+mul_tmp;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:316: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist10[0]<=hist10[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:317: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist10[1]<=hist10[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:318: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist10[2]<=hist10[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:319: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist10[3]<=hist10[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:320: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist10[4]<=hist10[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:321: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist10[5]<=hist10[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:322: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist10[6]<=hist10[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:323: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist10[7]<=hist10[7]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:328: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist11[0]<=hist11[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:329: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist11[1]<=hist11[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:330: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist11[2]<=hist11[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:331: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist11[3]<=hist11[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:332: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist11[4]<=hist11[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:333: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist11[5]<=hist11[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:334: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist11[6]<=hist11[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:335: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist11[7]<=hist11[7]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:340: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist12[0]<=hist12[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:341: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist12[1]<=hist12[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:342: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist12[2]<=hist12[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:343: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist12[3]<=hist12[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:344: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist12[4]<=hist12[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:345: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist12[5]<=hist12[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:346: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist12[6]<=hist12[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:347: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist12[7]<=hist12[7]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:352: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist13[0]<=hist13[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:353: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist13[1]<=hist13[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:354: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist13[2]<=hist13[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:355: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist13[3]<=hist13[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:356: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist13[4]<=hist13[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:357: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist13[5]<=hist13[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:358: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist13[6]<=hist13[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:359: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist13[7]<=hist13[7]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:364: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist14[0]<=hist14[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:365: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist14[1]<=hist14[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:366: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist14[2]<=hist14[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:367: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist14[3]<=hist14[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:368: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist14[4]<=hist14[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:369: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist14[5]<=hist14[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:370: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist14[6]<=hist14[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:371: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist14[7]<=hist14[7]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:376: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        0:hist15[0]<=hist15[0]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:377: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        1:hist15[1]<=hist15[1]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:378: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        2:hist15[2]<=hist15[2]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:379: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        3:hist15[3]<=hist15[3]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:380: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        4:hist15[4]<=hist15[4]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:381: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        5:hist15[5]<=hist15[5]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:382: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        6:hist15[6]<=hist15[6]+mul_tmp;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/local_desc.v:383: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'mul_tmp\' generates 14 bits.\n                                                                                                  : ... In instance local_desc\n        7:hist15[7]<=hist15[7]+mul_tmp;\n                              ^\n%Error: Exiting due to 4 error(s), 128 warning(s)\n'
module local_desc(
		input clk,
		input rst,
		input [17:0] addr_kp,
		input [7:0] mag,
		input [5:0] dir,
		input [5:0] main_dir,
		input complete1,
		output [17:0] local_desc_addr,
		output [63:0] tdesc1,
		output [63:0] tdesc2,
		output [63:0] tdesc3,
		output [63:0] tdesc4,
		output [63:0] tdesc5, 
		output [63:0] tdesc6,
		output [63:0] tdesc7,
		output [63:0] tdesc8,
		output [63:0] tdesc9,
		output [63:0] tdesc10,
		output [63:0] tdesc11,
		output [63:0] tdesc12,
		output [63:0] tdesc13,
		output [63:0] tdesc14,
		output [63:0] tdesc15,
		output [63:0] tdesc16,
		output reg out_en
    );
	  
	reg [7:0] cnt_init;
	reg [7:0] cnt;
	reg [7:0] cnt_d1;
	reg [7:0] cnt_d2;
	reg [7:0] cnt_d3;
	
	wire [7:0] spo;
	wire [2:0] dir_r;
	reg [2:0] dir_d1;
	reg [2:0] dir_d2;
	
	
	wire [15:0] t1;
	wire [13:0] mul_tmp;
	
	wire [3:0] cnt1;
	wire [3:0] cnt2;
	wire rg1,rg2,rg3,rg4;
	
	assign mul_tmp=t1[13:0];
	

	local_gau_rom U_local_coe (
			.a(cnt_d3),
			.spo(spo)
	);


	 mul_desc U_mag_mul(
		.clk		(clk), 
		.rstn		(rst),
		.r			(t1), 
		.al			(mag), 
		.cl			(spo)
	);


	assign cnt1=cnt_d3[3:0];
	assign cnt2=cnt_d3[7:4];
	
	assign rg1=(cnt2>7);  assign rg2=((cnt2>3)&&(cnt2<8))||((cnt2>11)&&(cnt2<=15));
	assign rg3=(cnt1>7);  assign rg4=((cnt1>3)&&(cnt1<8))||((cnt1>11)&&(cnt1<=15));

	


	dir36to8 U_dir_trans(
		.dir_in(dir),
		.dir_main(main_dir),
		.dir_out(dir_r)
	);
	
	

	window_rotate U_window_rotate(
		.clk(clk),
		.rst(rst),
		.main_dir(main_dir),
		.kp_addr(addr_kp),
		.cnt(cnt_init),
		.complete1(complete1),
		.addr_out(local_desc_addr)
    );
	

	reg [17:0] hist0[7:0];
	reg [17:0] hist1[7:0];
	reg [17:0] hist2[7:0];
	reg [17:0] hist3[7:0];
	reg [17:0] hist4[7:0];
	reg [17:0] hist5[7:0];
	reg [17:0] hist6[7:0];
	reg [17:0] hist7[7:0];
	reg [17:0] hist8[7:0];
	reg [17:0] hist9[7:0];
	reg [17:0] hist10[7:0];
	reg [17:0] hist11[7:0];
	reg [17:0] hist12[7:0];
	reg [17:0] hist13[7:0];
	reg [17:0] hist14[7:0];
	reg [17:0] hist15[7:0];
	
	reg [17:0] max;
	
	always@(posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			out_en<=0;
			cnt_init<=0;
			cnt<=0;
			cnt_d1<=0;
			cnt_d2<=0;
			cnt_d3<=0;
			hist0[0]<=0;hist1[0]<=0;hist2[0]<=0;hist3[0]<=0;
			hist4[0]<=0;hist5[0]<=0;hist6[0]<=0;hist7[0]<=0;
			hist8[0]<=0;hist9[0]<=0;hist10[0]<=0;hist11[0]<=0;
			hist12[0]<=0;hist13[0]<=0;hist14[0]<=0;hist15[0]<=0;
			
			hist0[1]<=0;hist1[1]<=0;hist2[1]<=0;hist3[1]<=0;
			hist4[1]<=0;hist5[1]<=0;hist6[1]<=0;hist7[1]<=0;
			hist8[1]<=0;hist9[1]<=0;hist10[1]<=0;hist11[1]<=0;
			hist12[1]<=0;hist13[1]<=0;hist14[1]<=0;hist15[1]<=0;
			
			hist0[2]<=0;hist1[2]<=0;hist2[2]<=0;hist3[2]<=0;
			hist4[2]<=0;hist5[2]<=0;hist6[2]<=0;hist7[2]<=0;
			hist8[2]<=0;hist9[2]<=0;hist10[2]<=0;hist11[2]<=0;
			hist12[2]<=0;hist13[2]<=0;hist14[2]<=0;hist15[2]<=0;
			
			hist0[3]<=0;hist1[3]<=0;hist2[3]<=0;hist3[3]<=0;
			hist4[3]<=0;hist5[3]<=0;hist6[3]<=0;hist7[3]<=0;
			hist8[3]<=0;hist9[3]<=0;hist10[3]<=0;hist11[3]<=0;
			hist12[3]<=0;hist13[3]<=0;hist14[3]<=0;hist15[3]<=0;
			
			hist0[4]<=0;hist1[4]<=0;hist2[4]<=0;hist3[4]<=0;
			hist4[4]<=0;hist5[4]<=0;hist6[4]<=0;hist7[4]<=0;
			hist8[4]<=0;hist9[4]<=0;hist10[4]<=0;hist11[4]<=0;
			hist12[4]<=0;hist13[4]<=0;hist14[4]<=0;hist15[4]<=0;
			
			hist0[5]<=0;hist1[5]<=0;hist2[5]<=0;hist3[5]<=0;
			hist4[5]<=0;hist5[5]<=0;hist6[5]<=0;hist7[5]<=0;
			hist8[5]<=0;hist9[5]<=0;hist10[5]<=0;hist11[5]<=0;
			hist12[5]<=0;hist13[5]<=0;hist14[5]<=0;hist15[5]<=0;
			
			hist0[6]<=0;hist1[6]<=0;hist2[6]<=0;hist3[6]<=0;
			hist4[6]<=0;hist5[6]<=0;hist6[6]<=0;hist7[6]<=0;
			hist8[6]<=0;hist9[6]<=0;hist10[6]<=0;hist11[6]<=0;
			hist12[6]<=0;hist13[6]<=0;hist14[6]<=0;hist15[6]<=0;
			
			hist0[7]<=0;hist1[7]<=0;hist2[7]<=0;hist3[7]<=0;
			hist4[7]<=0;hist5[7]<=0;hist6[7]<=0;hist7[7]<=0;
			hist8[7]<=0;hist9[7]<=0;hist10[7]<=0;hist11[7]<=0;
			hist12[7]<=0;hist13[7]<=0;hist14[7]<=0;hist15[7]<=0;
		end
		else
		begin

			dir_d1<=dir_r;
			dir_d2<=dir_d1;
			
			cnt<=cnt_init;
			cnt_d1<=cnt;
			cnt_d2<=cnt_d1;
			cnt_d3<=cnt_d2;
			
			if(cnt_init<255)
			begin
				cnt_init<=cnt_init+1;
				case({rg1,rg2,rg3,rg4})
					4'b0000:begin
							case(dir_d1)
								0:hist0[0]<=hist0[0]+mul_tmp;
								1:hist0[1]<=hist0[1]+mul_tmp;
								2:hist0[2]<=hist0[2]+mul_tmp;
								3:hist0[3]<=hist0[3]+mul_tmp;
								4:hist0[4]<=hist0[4]+mul_tmp;
								5:hist0[5]<=hist0[5]+mul_tmp;
								6:hist0[6]<=hist0[6]+mul_tmp;
								7:hist0[7]<=hist0[7]+mul_tmp;
							endcase
						end
					4'b0001:begin
							case(dir_d1)
								0:hist1[0]<=hist1[0]+mul_tmp;
								1:hist1[1]<=hist1[1]+mul_tmp;
								2:hist1[2]<=hist1[2]+mul_tmp;
								3:hist1[3]<=hist1[3]+mul_tmp;
								4:hist1[4]<=hist1[4]+mul_tmp;
								5:hist1[5]<=hist1[5]+mul_tmp;
								6:hist1[6]<=hist1[6]+mul_tmp;
								7:hist1[7]<=hist1[7]+mul_tmp;
							endcase
						end
					4'b0010:begin
							case(dir_d1)
								0:hist2[0]<=hist2[0]+mul_tmp;
								1:hist2[1]<=hist2[1]+mul_tmp;
								2:hist2[2]<=hist2[2]+mul_tmp;
								3:hist2[3]<=hist2[3]+mul_tmp;
								4:hist2[4]<=hist2[4]+mul_tmp;
								5:hist2[5]<=hist2[5]+mul_tmp;
								6:hist2[6]<=hist2[6]+mul_tmp;
								7:hist2[7]<=hist2[7]+mul_tmp;
							endcase
						end
					4'b0011:begin
							case(dir_d1)
								0:hist3[0]<=hist3[0]+mul_tmp;
								1:hist3[1]<=hist3[1]+mul_tmp;
								2:hist3[2]<=hist3[2]+mul_tmp;
								3:hist3[3]<=hist3[3]+mul_tmp;
								4:hist3[4]<=hist3[4]+mul_tmp;
								5:hist3[5]<=hist3[5]+mul_tmp;
								6:hist3[6]<=hist3[6]+mul_tmp;
								7:hist3[7]<=hist3[7]+mul_tmp;
							endcase
						end
					4'b0100:begin
							case(dir_d1)
								0:hist4[0]<=hist4[0]+mul_tmp;
								1:hist4[1]<=hist4[1]+mul_tmp;
								2:hist4[2]<=hist4[2]+mul_tmp;
								3:hist4[3]<=hist4[3]+mul_tmp;
								4:hist4[4]<=hist4[4]+mul_tmp;
								5:hist4[5]<=hist4[5]+mul_tmp;
								6:hist4[6]<=hist4[6]+mul_tmp;
								7:hist4[7]<=hist4[7]+mul_tmp;
							endcase
						end
					4'b0101:begin
							case(dir_d1)
								0:hist5[0]<=hist5[0]+mul_tmp;
								1:hist5[1]<=hist5[1]+mul_tmp;
								2:hist5[2]<=hist5[2]+mul_tmp;
								3:hist5[3]<=hist5[3]+mul_tmp;
								4:hist5[4]<=hist5[4]+mul_tmp;
								5:hist5[5]<=hist5[5]+mul_tmp;
								6:hist5[6]<=hist5[6]+mul_tmp;
								7:hist5[7]<=hist5[7]+mul_tmp;
							endcase
						end
					4'b0110:begin
							case(dir_d1)
								0:hist6[0]<=hist6[0]+mul_tmp;
								1:hist6[1]<=hist6[1]+mul_tmp;
								2:hist6[2]<=hist6[2]+mul_tmp;
								3:hist6[3]<=hist6[3]+mul_tmp;
								4:hist6[4]<=hist6[4]+mul_tmp;
								5:hist6[5]<=hist6[5]+mul_tmp;
								6:hist6[6]<=hist6[6]+mul_tmp;
								7:hist6[7]<=hist6[7]+mul_tmp;
							endcase
						end
					4'b0111:begin
							case(dir_d1)
								0:hist7[0]<=hist7[0]+mul_tmp;
								1:hist7[1]<=hist7[1]+mul_tmp;
								2:hist7[2]<=hist7[2]+mul_tmp;
								3:hist7[3]<=hist7[3]+mul_tmp;
								4:hist7[4]<=hist7[4]+mul_tmp;
								5:hist7[5]<=hist7[5]+mul_tmp;
								6:hist7[6]<=hist7[6]+mul_tmp;
								7:hist7[7]<=hist7[7]+mul_tmp;
							endcase
						end
					4'b1000:begin
							case(dir_d1)
								0:hist8[0]<=hist8[0]+mul_tmp;
								1:hist8[1]<=hist8[1]+mul_tmp;
								2:hist8[2]<=hist8[2]+mul_tmp;
								3:hist8[3]<=hist8[3]+mul_tmp;
								4:hist8[4]<=hist8[4]+mul_tmp;
								5:hist8[5]<=hist8[5]+mul_tmp;
								6:hist8[6]<=hist8[6]+mul_tmp;
								7:hist8[7]<=hist8[7]+mul_tmp;
							endcase
						end
					4'b1001:begin
							case(dir_d1)
								0:hist9[0]<=hist9[0]+mul_tmp;
								1:hist9[1]<=hist9[1]+mul_tmp;
								2:hist9[2]<=hist9[2]+mul_tmp;
								3:hist9[3]<=hist9[3]+mul_tmp;
								4:hist9[4]<=hist9[4]+mul_tmp;
								5:hist9[5]<=hist9[5]+mul_tmp;
								6:hist9[6]<=hist9[6]+mul_tmp;
								7:hist9[7]<=hist9[7]+mul_tmp;
							endcase
						end
					4'b1010:begin
							case(dir_d1)
								0:hist10[0]<=hist10[0]+mul_tmp;
								1:hist10[1]<=hist10[1]+mul_tmp;
								2:hist10[2]<=hist10[2]+mul_tmp;
								3:hist10[3]<=hist10[3]+mul_tmp;
								4:hist10[4]<=hist10[4]+mul_tmp;
								5:hist10[5]<=hist10[5]+mul_tmp;
								6:hist10[6]<=hist10[6]+mul_tmp;
								7:hist10[7]<=hist10[7]+mul_tmp;
							endcase
						end
					4'b1011:begin
							case(dir_d1)
								0:hist11[0]<=hist11[0]+mul_tmp;
								1:hist11[1]<=hist11[1]+mul_tmp;
								2:hist11[2]<=hist11[2]+mul_tmp;
								3:hist11[3]<=hist11[3]+mul_tmp;
								4:hist11[4]<=hist11[4]+mul_tmp;
								5:hist11[5]<=hist11[5]+mul_tmp;
								6:hist11[6]<=hist11[6]+mul_tmp;
								7:hist11[7]<=hist11[7]+mul_tmp;
							endcase
						end
					4'b1100:begin
							case(dir_d1)
								0:hist12[0]<=hist12[0]+mul_tmp;
								1:hist12[1]<=hist12[1]+mul_tmp;
								2:hist12[2]<=hist12[2]+mul_tmp;
								3:hist12[3]<=hist12[3]+mul_tmp;
								4:hist12[4]<=hist12[4]+mul_tmp;
								5:hist12[5]<=hist12[5]+mul_tmp;
								6:hist12[6]<=hist12[6]+mul_tmp;
								7:hist12[7]<=hist12[7]+mul_tmp;
							endcase
						end
					4'b1101:begin
							case(dir_d1)
								0:hist13[0]<=hist13[0]+mul_tmp;
								1:hist13[1]<=hist13[1]+mul_tmp;
								2:hist13[2]<=hist13[2]+mul_tmp;
								3:hist13[3]<=hist13[3]+mul_tmp;
								4:hist13[4]<=hist13[4]+mul_tmp;
								5:hist13[5]<=hist13[5]+mul_tmp;
								6:hist13[6]<=hist13[6]+mul_tmp;
								7:hist13[7]<=hist13[7]+mul_tmp;
							endcase
						end
					4'b1110:begin
							case(dir_d1)
								0:hist14[0]<=hist14[0]+mul_tmp;
								1:hist14[1]<=hist14[1]+mul_tmp;
								2:hist14[2]<=hist14[2]+mul_tmp;
								3:hist14[3]<=hist14[3]+mul_tmp;
								4:hist14[4]<=hist14[4]+mul_tmp;
								5:hist14[5]<=hist14[5]+mul_tmp;
								6:hist14[6]<=hist14[6]+mul_tmp;
								7:hist14[7]<=hist14[7]+mul_tmp;
							endcase
						end
					4'b1111:begin
							case(dir_d1)
								0:hist15[0]<=hist15[0]+mul_tmp;
								1:hist15[1]<=hist15[1]+mul_tmp;
								2:hist15[2]<=hist15[2]+mul_tmp;
								3:hist15[3]<=hist15[3]+mul_tmp;
								4:hist15[4]<=hist15[4]+mul_tmp;
								5:hist15[5]<=hist15[5]+mul_tmp;
								6:hist15[6]<=hist15[6]+mul_tmp;
								7:hist15[7]<=hist15[7]+mul_tmp;
							endcase
						end
				endcase
			end
			else
			begin
				cnt_init<=255;
				out_en<=1;
				
			end
		end
	end

	 assign tdesc1={hist0[0][9:2],hist0[1][9:2],hist0[2][9:2],hist0[3][9:2],hist0[4][9:2],hist0[5][9:2],hist0[6][9:2],hist0[7][9:2]};
	 assign tdesc2={hist1[0][9:2],hist1[1][9:2],hist1[2][9:2],hist1[3][9:2],hist1[4][9:2],hist1[5][9:2],hist1[6][9:2],hist1[7][9:2]};
	 assign tdesc3={hist2[0][9:2],hist2[1][9:2],hist2[2][9:2],hist2[3][9:2],hist2[4][9:2],hist2[5][9:2],hist2[6][9:2],hist2[7][9:2]};
	 assign tdesc4={hist3[0][9:2],hist3[1][9:2],hist3[2][9:2],hist3[3][9:2],hist3[4][9:2],hist3[5][9:2],hist3[6][9:2],hist3[7][9:2]};
	 assign tdesc5={hist4[0][9:2],hist4[1][9:2],hist4[2][9:2],hist4[3][9:2],hist4[4][9:2],hist4[5][9:2],hist4[6][9:2],hist4[7][9:2]};
	 assign tdesc6={hist5[0][9:2],hist5[1][9:2],hist5[2][9:2],hist5[3][9:2],hist5[4][9:2],hist5[5][9:2],hist5[6][9:2],hist5[7][9:2]};
	 assign tdesc7={hist6[0][9:2],hist6[1][9:2],hist6[2][9:2],hist6[3][9:2],hist6[4][9:2],hist6[5][9:2],hist6[6][9:2],hist6[7][9:2]};
	 assign tdesc8={hist7[0][9:2],hist7[1][9:2],hist7[2][9:2],hist7[3][9:2],hist7[4][9:2],hist7[5][9:2],hist7[6][9:2],hist7[7][9:2]};
	 assign tdesc9={hist8[0][9:2],hist8[1][9:2],hist8[2][9:2],hist8[3][9:2],hist8[4][9:2],hist8[5][9:2],hist8[6][9:2],hist8[7][9:2]};
	 assign tdesc10={hist9[0][9:2],hist9[1][9:2],hist9[2][9:2],hist9[3][9:2],hist9[4][9:2],hist9[5][9:2],hist9[6][9:2],hist9[7][9:2]};
	 assign tdesc11={hist10[0][9:2],hist10[1][9:2],hist10[2][9:2],hist10[3][9:2],hist10[4][9:2],hist10[5][9:2],hist10[6][9:2],hist10[7][9:2]};
	 assign tdesc12={hist11[0][9:2],hist11[1][9:2],hist11[2][9:2],hist11[3][9:2],hist11[4][9:2],hist11[5][9:2],hist11[6][9:2],hist11[7][9:2]};
	 assign tdesc13={hist12[0][9:2],hist12[1][9:2],hist12[2][9:2],hist12[3][9:2],hist12[4][9:2],hist12[5][9:2],hist12[6][9:2],hist12[7][9:2]};
	 assign tdesc14={hist13[0][9:2],hist13[1][9:2],hist13[2][9:2],hist13[3][9:2],hist13[4][9:2],hist13[5][9:2],hist13[6][9:2],hist13[7][9:2]};
	 assign tdesc15={hist14[0][9:2],hist14[1][9:2],hist14[2][9:2],hist14[3][9:2],hist14[4][9:2],hist14[5][9:2],hist14[6][9:2],hist14[7][9:2]};
	 assign tdesc16={hist15[0][9:2],hist15[1][9:2],hist15[2][9:2],hist15[3][9:2],hist15[4][9:2],hist15[5][9:2],hist15[6][9:2],hist15[7][9:2]};



endmodule
module local_desc(
		input clk,
		input rst,
		input [17:0] addr_kp,
		input [7:0] mag,
		input [5:0] dir,
		input [5:0] main_dir,
		input complete1,
		output [17:0] local_desc_addr,
		output [63:0] tdesc1,
		output [63:0] tdesc2,
		output [63:0] tdesc3,
		output [63:0] tdesc4,
		output [63:0] tdesc5, 
		output [63:0] tdesc6,
		output [63:0] tdesc7,
		output [63:0] tdesc8,
		output [63:0] tdesc9,
		output [63:0] tdesc10,
		output [63:0] tdesc11,
		output [63:0] tdesc12,
		output [63:0] tdesc13,
		output [63:0] tdesc14,
		output [63:0] tdesc15,
		output [63:0] tdesc16,
		output reg out_en
    );

	  
	reg [7:0] cnt_init;
	reg [7:0] cnt;
	reg [7:0] cnt_d1;
	reg [7:0] cnt_d2;
	reg [7:0] cnt_d3;
	
	wire [7:0] spo;
	wire [2:0] dir_r;
	reg [2:0] dir_d1;
	reg [2:0] dir_d2;
	
	
	wire [15:0] t1;
	wire [13:0] mul_tmp;
	
	wire [3:0] cnt1;
	wire [3:0] cnt2;
	wire rg1,rg2,rg3,rg4;
	
	assign mul_tmp=t1[13:0];
	

	local_gau_rom U_local_coe (
			.a(cnt_d3),
			.spo(spo)
	);


	 mul_desc U_mag_mul(
		.clk		(clk), 
		.rstn		(rst),
		.r			(t1), 
		.al			(mag), 
		.cl			(spo)
	);


	assign cnt1=cnt_d3[3:0];
	assign cnt2=cnt_d3[7:4];
	
	assign rg1=(cnt2>7);  assign rg2=((cnt2>3)&&(cnt2<8))||((cnt2>11)&&(cnt2<=15));
	assign rg3=(cnt1>7);  assign rg4=((cnt1>3)&&(cnt1<8))||((cnt1>11)&&(cnt1<=15));

	


	dir36to8 U_dir_trans(
		.dir_in(dir),
		.dir_main(main_dir),
		.dir_out(dir_r)
	);
	
	

	window_rotate U_window_rotate(
		.clk(clk),
		.rst(rst),
		.main_dir(main_dir),
		.kp_addr(addr_kp),
		.cnt(cnt_init),
		.complete1(complete1),
		.addr_out(local_desc_addr)
    );
	

	reg [17:0] hist0[7:0];
	reg [17:0] hist1[7:0];
	reg [17:0] hist2[7:0];
	reg [17:0] hist3[7:0];
	reg [17:0] hist4[7:0];
	reg [17:0] hist5[7:0];
	reg [17:0] hist6[7:0];
	reg [17:0] hist7[7:0];
	reg [17:0] hist8[7:0];
	reg [17:0] hist9[7:0];
	reg [17:0] hist10[7:0];
	reg [17:0] hist11[7:0];
	reg [17:0] hist12[7:0];
	reg [17:0] hist13[7:0];
	reg [17:0] hist14[7:0];
	reg [17:0] hist15[7:0];
	
	reg [17:0] max;
	
	always@(posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			out_en<=0;
			cnt_init<=0;
			cnt<=0;
			cnt_d1<=0;
			cnt_d2<=0;
			cnt_d3<=0;
			hist0[0]<=0;hist1[0]<=0;hist2[0]<=0;hist3[0]<=0;
			hist4[0]<=0;hist5[0]<=0;hist6[0]<=0;hist7[0]<=0;
			hist8[0]<=0;hist9[0]<=0;hist10[0]<=0;hist11[0]<=0;
			hist12[0]<=0;hist13[0]<=0;hist14[0]<=0;hist15[0]<=0;
			
			hist0[1]<=0;hist1[1]<=0;hist2[1]<=0;hist3[1]<=0;
			hist4[1]<=0;hist5[1]<=0;hist6[1]<=0;hist7[1]<=0;
			hist8[1]<=0;hist9[1]<=0;hist10[1]<=0;hist11[1]<=0;
			hist12[1]<=0;hist13[1]<=0;hist14[1]<=0;hist15[1]<=0;
			
			hist0[2]<=0;hist1[2]<=0;hist2[2]<=0;hist3[2]<=0;
			hist4[2]<=0;hist5[2]<=0;hist6[2]<=0;hist7[2]<=0;
			hist8[2]<=0;hist9[2]<=0;hist10[2]<=0;hist11[2]<=0;
			hist12[2]<=0;hist13[2]<=0;hist14[2]<=0;hist15[2]<=0;
			
			hist0[3]<=0;hist1[3]<=0;hist2[3]<=0;hist3[3]<=0;
			hist4[3]<=0;hist5[3]<=0;hist6[3]<=0;hist7[3]<=0;
			hist8[3]<=0;hist9[3]<=0;hist10[3]<=0;hist11[3]<=0;
			hist12[3]<=0;hist13[3]<=0;hist14[3]<=0;hist15[3]<=0;
			
			hist0[4]<=0;hist1[4]<=0;hist2[4]<=0;hist3[4]<=0;
			hist4[4]<=0;hist5[4]<=0;hist6[4]<=0;hist7[4]<=0;
			hist8[4]<=0;hist9[4]<=0;hist10[4]<=0;hist11[4]<=0;
			hist12[4]<=0;hist13[4]<=0;hist14[4]<=0;hist15[4]<=0;
			
			hist0[5]<=0;hist1[5]<=0;hist2[5]<=0;hist3[5]<=0;
			hist4[5]<=0;hist5[5]<=0;hist6[5]<=0;hist7[5]<=0;
			hist8[5]<=0;hist9[5]<=0;hist10[5]<=0;hist11[5]<=0;
			hist12[5]<=0;hist13[5]<=0;hist14[5]<=0;hist15[5]<=0;
			
			hist0[6]<=0;hist1[6]<=0;hist2[6]<=0;hist3[6]<=0;
			hist4[6]<=0;hist5[6]<=0;hist6[6]<=0;hist7[6]<=0;
			hist8[6]<=0;hist9[6]<=0;hist10[6]<=0;hist11[6]<=0;
			hist12[6]<=0;hist13[6]<=0;hist14[6]<=0;hist15[6]<=0;
			
			hist0[7]<=0;hist1[7]<=0;hist2[7]<=0;hist3[7]<=0;
			hist4[7]<=0;hist5[7]<=0;hist6[7]<=0;hist7[7]<=0;
			hist8[7]<=0;hist9[7]<=0;hist10[7]<=0;hist11[7]<=0;
			hist12[7]<=0;hist13[7]<=0;hist14[7]<=0;hist15[7]<=0;
		end
		else
		begin

			dir_d1<=dir_r;
			dir_d2<=dir_d1;
			
			cnt<=cnt_init;
			cnt_d1<=cnt;
			cnt_d2<=cnt_d1;
			cnt_d3<=cnt_d2;
			
			if(cnt_init<255)
			begin
				cnt_init<=cnt_init+1;
				case({rg1,rg2,rg3,rg4})
					4'b0000:begin
							case(dir_d1)
								0:hist0[0]<=hist0[0]+mul_tmp;
								1:hist0[1]<=hist0[1]+mul_tmp;
								2:hist0[2]<=hist0[2]+mul_tmp;
								3:hist0[3]<=hist0[3]+mul_tmp;
								4:hist0[4]<=hist0[4]+mul_tmp;
								5:hist0[5]<=hist0[5]+mul_tmp;
								6:hist0[6]<=hist0[6]+mul_tmp;
								7:hist0[7]<=hist0[7]+mul_tmp;
							endcase
						end
					4'b0001:begin
							case(dir_d1)
								0:hist1[0]<=hist1[0]+mul_tmp;
								1:hist1[1]<=hist1[1]+mul_tmp;
								2:hist1[2]<=hist1[2]+mul_tmp;
								3:hist1[3]<=hist1[3]+mul_tmp;
								4:hist1[4]<=hist1[4]+mul_tmp;
								5:hist1[5]<=hist1[5]+mul_tmp;
								6:hist1[6]<=hist1[6]+mul_tmp;
								7:hist1[7]<=hist1[7]+mul_tmp;
							endcase
						end
					4'b0010:begin
							case(dir_d1)
								0:hist2[0]<=hist2[0]+mul_tmp;
								1:hist2[1]<=hist2[1]+mul_tmp;
								2:hist2[2]<=hist2[2]+mul_tmp;
								3:hist2[3]<=hist2[3]+mul_tmp;
								4:hist2[4]<=hist2[4]+mul_tmp;
								5:hist2[5]<=hist2[5]+mul_tmp;
								6:hist2[6]<=hist2[6]+mul_tmp;
								7:hist2[7]<=hist2[7]+mul_tmp;
							endcase
						end
					4'b0011:begin
							case(dir_d1)
								0:hist3[0]<=hist3[0]+mul_tmp;
								1:hist3[1]<=hist3[1]+mul_tmp;
								2:hist3[2]<=hist3[2]+mul_tmp;
								3:hist3[3]<=hist3[3]+mul_tmp;
								4:hist3[4]<=hist3[4]+mul_tmp;
								5:hist3[5]<=hist3[5]+mul_tmp;
								6:hist3[6]<=hist3[6]+mul_tmp;
								7:hist3[7]<=hist3[7]+mul_tmp;
							endcase
						end
					4'b0100:begin
							case(dir_d1)
								0:hist4[0]<=hist4[0]+mul_tmp;
								1:hist4[1]<=hist4[1]+mul_tmp;
								2:hist4[2]<=hist4[2]+mul_tmp;
								3:hist4[3]<=hist4[3]+mul_tmp;
								4:hist4[4]<=hist4[4]+mul_tmp;
								5:hist4[5]<=hist4[5]+mul_tmp;
								6:hist4[6]<=hist4[6]+mul_tmp;
								7:hist4[7]<=hist4[7]+mul_tmp;
							endcase
						end
					4'b0101:begin
							case(dir_d1)
								0:hist5[0]<=hist5[0]+mul_tmp;
								1:hist5[1]<=hist5[1]+mul_tmp;
								2:hist5[2]<=hist5[2]+mul_tmp;
								3:hist5[3]<=hist5[3]+mul_tmp;
								4:hist5[4]<=hist5[4]+mul_tmp;
								5:hist5[5]<=hist5[5]+mul_tmp;
								6:hist5[6]<=hist5[6]+mul_tmp;
								7:hist5[7]<=hist5[7]+mul_tmp;
							endcase
						end
					4'b0110:begin
							case(dir_d1)
								0:hist6[0]<=hist6[0]+mul_tmp;
								1:hist6[1]<=hist6[1]+mul_tmp;
								2:hist6[2]<=hist6[2]+mul_tmp;
								3:hist6[3]<=hist6[3]+mul_tmp;
								4:hist6[4]<=hist6[4]+mul_tmp;
								5:hist6[5]<=hist6[5]+mul_tmp;
								6:hist6[6]<=hist6[6]+mul_tmp;
								7:hist6[7]<=hist6[7]+mul_tmp;
							endcase
						end
					4'b0111:begin
							case(dir_d1)
								0:hist7[0]<=hist7[0]+mul_tmp;
								1:hist7[1]<=hist7[1]+mul_tmp;
								2:hist7[2]<=hist7[2]+mul_tmp;
								3:hist7[3]<=hist7[3]+mul_tmp;
								4:hist7[4]<=hist7[4]+mul_tmp;
								5:hist7[5]<=hist7[5]+mul_tmp;
								6:hist7[6]<=hist7[6]+mul_tmp;
								7:hist7[7]<=hist7[7]+mul_tmp;
							endcase
						end
					4'b1000:begin
							case(dir_d1)
								0:hist8[0]<=hist8[0]+mul_tmp;
								1:hist8[1]<=hist8[1]+mul_tmp;
								2:hist8[2]<=hist8[2]+mul_tmp;
								3:hist8[3]<=hist8[3]+mul_tmp;
								4:hist8[4]<=hist8[4]+mul_tmp;
								5:hist8[5]<=hist8[5]+mul_tmp;
								6:hist8[6]<=hist8[6]+mul_tmp;
								7:hist8[7]<=hist8[7]+mul_tmp;
							endcase
						end
					4'b1001:begin
							case(dir_d1)
								0:hist9[0]<=hist9[0]+mul_tmp;
								1:hist9[1]<=hist9[1]+mul_tmp;
								2:hist9[2]<=hist9[2]+mul_tmp;
								3:hist9[3]<=hist9[3]+mul_tmp;
								4:hist9[4]<=hist9[4]+mul_tmp;
								5:hist9[5]<=hist9[5]+mul_tmp;
								6:hist9[6]<=hist9[6]+mul_tmp;
								7:hist9[7]<=hist9[7]+mul_tmp;
							endcase
						end
					4'b1010:begin
							case(dir_d1)
								0:hist10[0]<=hist10[0]+mul_tmp;
								1:hist10[1]<=hist10[1]+mul_tmp;
								2:hist10[2]<=hist10[2]+mul_tmp;
								3:hist10[3]<=hist10[3]+mul_tmp;
								4:hist10[4]<=hist10[4]+mul_tmp;
								5:hist10[5]<=hist10[5]+mul_tmp;
								6:hist10[6]<=hist10[6]+mul_tmp;
								7:hist10[7]<=hist10[7]+mul_tmp;
							endcase
						end
					4'b1011:begin
							case(dir_d1)
								0:hist11[0]<=hist11[0]+mul_tmp;
								1:hist11[1]<=hist11[1]+mul_tmp;
								2:hist11[2]<=hist11[2]+mul_tmp;
								3:hist11[3]<=hist11[3]+mul_tmp;
								4:hist11[4]<=hist11[4]+mul_tmp;
								5:hist11[5]<=hist11[5]+mul_tmp;
								6:hist11[6]<=hist11[6]+mul_tmp;
								7:hist11[7]<=hist11[7]+mul_tmp;
							endcase
						end
					4'b1100:begin
							case(dir_d1)
								0:hist12[0]<=hist12[0]+mul_tmp;
								1:hist12[1]<=hist12[1]+mul_tmp;
								2:hist12[2]<=hist12[2]+mul_tmp;
								3:hist12[3]<=hist12[3]+mul_tmp;
								4:hist12[4]<=hist12[4]+mul_tmp;
								5:hist12[5]<=hist12[5]+mul_tmp;
								6:hist12[6]<=hist12[6]+mul_tmp;
								7:hist12[7]<=hist12[7]+mul_tmp;
							endcase
						end
					4'b1101:begin
							case(dir_d1)
								0:hist13[0]<=hist13[0]+mul_tmp;
								1:hist13[1]<=hist13[1]+mul_tmp;
								2:hist13[2]<=hist13[2]+mul_tmp;
								3:hist13[3]<=hist13[3]+mul_tmp;
								4:hist13[4]<=hist13[4]+mul_tmp;
								5:hist13[5]<=hist13[5]+mul_tmp;
								6:hist13[6]<=hist13[6]+mul_tmp;
								7:hist13[7]<=hist13[7]+mul_tmp;
							endcase
						end
					4'b1110:begin
							case(dir_d1)
								0:hist14[0]<=hist14[0]+mul_tmp;
								1:hist14[1]<=hist14[1]+mul_tmp;
								2:hist14[2]<=hist14[2]+mul_tmp;
								3:hist14[3]<=hist14[3]+mul_tmp;
								4:hist14[4]<=hist14[4]+mul_tmp;
								5:hist14[5]<=hist14[5]+mul_tmp;
								6:hist14[6]<=hist14[6]+mul_tmp;
								7:hist14[7]<=hist14[7]+mul_tmp;
							endcase
						end
					4'b1111:begin
							case(dir_d1)
								0:hist15[0]<=hist15[0]+mul_tmp;
								1:hist15[1]<=hist15[1]+mul_tmp;
								2:hist15[2]<=hist15[2]+mul_tmp;
								3:hist15[3]<=hist15[3]+mul_tmp;
								4:hist15[4]<=hist15[4]+mul_tmp;
								5:hist15[5]<=hist15[5]+mul_tmp;
								6:hist15[6]<=hist15[6]+mul_tmp;
								7:hist15[7]<=hist15[7]+mul_tmp;
							endcase
						end
				endcase
			end
			else
			begin
				cnt_init<=255;
				out_en<=1;
				
			end
		end
	end

	 assign tdesc1={hist0[0][9:2],hist0[1][9:2],hist0[2][9:2],hist0[3][9:2],hist0[4][9:2],hist0[5][9:2],hist0[6][9:2],hist0[7][9:2]};
	 assign tdesc2={hist1[0][9:2],hist1[1][9:2],hist1[2][9:2],hist1[3][9:2],hist1[4][9:2],hist1[5][9:2],hist1[6][9:2],hist1[7][9:2]};
	 assign tdesc3={hist2[0][9:2],hist2[1][9:2],hist2[2][9:2],hist2[3][9:2],hist2[4][9:2],hist2[5][9:2],hist2[6][9:2],hist2[7][9:2]};
	 assign tdesc4={hist3[0][9:2],hist3[1][9:2],hist3[2][9:2],hist3[3][9:2],hist3[4][9:2],hist3[5][9:2],hist3[6][9:2],hist3[7][9:2]};
	 assign tdesc5={hist4[0][9:2],hist4[1][9:2],hist4[2][9:2],hist4[3][9:2],hist4[4][9:2],hist4[5][9:2],hist4[6][9:2],hist4[7][9:2]};
	 assign tdesc6={hist5[0][9:2],hist5[1][9:2],hist5[2][9:2],hist5[3][9:2],hist5[4][9:2],hist5[5][9:2],hist5[6][9:2],hist5[7][9:2]};
	 assign tdesc7={hist6[0][9:2],hist6[1][9:2],hist6[2][9:2],hist6[3][9:2],hist6[4][9:2],hist6[5][9:2],hist6[6][9:2],hist6[7][9:2]};
	 assign tdesc8={hist7[0][9:2],hist7[1][9:2],hist7[2][9:2],hist7[3][9:2],hist7[4][9:2],hist7[5][9:2],hist7[6][9:2],hist7[7][9:2]};
	 assign tdesc9={hist8[0][9:2],hist8[1][9:2],hist8[2][9:2],hist8[3][9:2],hist8[4][9:2],hist8[5][9:2],hist8[6][9:2],hist8[7][9:2]};
	 assign tdesc10={hist9[0][9:2],hist9[1][9:2],hist9[2][9:2],hist9[3][9:2],hist9[4][9:2],hist9[5][9:2],hist9[6][9:2],hist9[7][9:2]};
	 assign tdesc11={hist10[0][9:2],hist10[1][9:2],hist10[2][9:2],hist10[3][9:2],hist10[4][9:2],hist10[5][9:2],hist10[6][9:2],hist10[7][9:2]};
	 assign tdesc12={hist11[0][9:2],hist11[1][9:2],hist11[2][9:2],hist11[3][9:2],hist11[4][9:2],hist11[5][9:2],hist11[6][9:2],hist11[7][9:2]};
	 assign tdesc13={hist12[0][9:2],hist12[1][9:2],hist12[2][9:2],hist12[3][9:2],hist12[4][9:2],hist12[5][9:2],hist12[6][9:2],hist12[7][9:2]};
	 assign tdesc14={hist13[0][9:2],hist13[1][9:2],hist13[2][9:2],hist13[3][9:2],hist13[4][9:2],hist13[5][9:2],hist13[6][9:2],hist13[7][9:2]};
	 assign tdesc15={hist14[0][9:2],hist14[1][9:2],hist14[2][9:2],hist14[3][9:2],hist14[4][9:2],hist14[5][9:2],hist14[6][9:2],hist14[7][9:2]};
	 assign tdesc16={hist15[0][9:2],hist15[1][9:2],hist15[2][9:2],hist15[3][9:2],hist15[4][9:2],hist15[5][9:2],hist15[6][9:2],hist15[7][9:2]};



endmodule