data/full_repos/permissive/415491487/sim_src/main_check.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/415491487/sim_src/main_check.v:18: Unsupported: Ignoring delay on this delayed statement.\n    always #(clkp / 2.0) begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/415491487/sim_src/main_check.v:45: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/415491487/sim_src/main_check.v:47: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/415491487/sim_src/main_check.v:49: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_check();
    reg clk, rst;

    wire [23:0] iaddr;
    wire [23:0] idata;
    
    wire [23:0] dwaddr;
    wire [23:0] dwdata;
    wire [23:0] draddr;
    wire [23:0] drdata;
    
    reg [24:0] imem[3:0];
    
    parameter clkp = 1;
    
    always #(clkp / 2.0) begin
        clk = ~clk;
    end
    
    initial clk = 1'b0;
    initial rst = 1'b0;
    







    

    


    

    imem #(.mem_size(128)) tm(.clk(clk), .addr(iaddr), .data(idata));
    dpdmem #(.mem_size(128)) tm2(.clk(clk), .waddr(dwaddr), .wdata(dwdata), .raddr(draddr), .rdata(drdata), .wen(1'b1));
    
    proc p0(.clk(clk), .rst(rst), .idata(idata), .iaddr(iaddr), .dwaddr(dwaddr), .dwdata(dwdata), .draddr(draddr), .drdata(drdata));
    
    initial begin
        @(posedge clk);
        rst = 1'b1;
        @(negedge clk);
        rst = 1'b0;
        @(posedge clk);
    end
    
endmodule
module main_check();

    reg clk, rst;

    wire [23:0] iaddr;
    wire [23:0] idata;
    
    wire [23:0] dwaddr;
    wire [23:0] dwdata;
    wire [23:0] draddr;
    wire [23:0] drdata;
    
    reg [24:0] imem[3:0];
    
    parameter clkp = 1;
    
    always #(clkp / 2.0) begin
        clk = ~clk;
    end
    
    initial clk = 1'b0;
    initial rst = 1'b0;
    







    

    


    

    imem #(.mem_size(128)) tm(.clk(clk), .addr(iaddr), .data(idata));
    dpdmem #(.mem_size(128)) tm2(.clk(clk), .waddr(dwaddr), .wdata(dwdata), .raddr(draddr), .rdata(drdata), .wen(1'b1));
    
    proc p0(.clk(clk), .rst(rst), .idata(idata), .iaddr(iaddr), .dwaddr(dwaddr), .dwdata(dwdata), .draddr(draddr), .drdata(drdata));
    
    initial begin
        @(posedge clk);
        rst = 1'b1;
        @(negedge clk);
        rst = 1'b0;
        @(posedge clk);
    end
    
endmodule