data/full_repos/permissive/493441306/Verilog Language/basics/00_wire.v
1: b'%Error: Cannot find file containing module: Language/basics,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/basics,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/basics,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/basics,data/full_repos/permissive/493441306.sv\n             Language/basics,data/full_repos/permissive/493441306\n             Language/basics,data/full_repos/permissive/493441306.v\n             Language/basics,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/basics,data/full_repos/permissive/493441306\n             obj_dir/Language/basics,data/full_repos/permissive/493441306.v\n             obj_dir/Language/basics,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/basics/00_wire.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( input in, output out );
    
    assign out = in ;
    
endmodule
module top_module ( input in, output out );

    
    assign out = in ;
    
endmodule