data/full_repos/permissive/418819021/lab-01/task3/sram.v
data/verilator_xmls/e3ca88f4-243d-471b-a4de-0d5be0135ac6.xml
module sram(
    input       clk,
    input       reset,
    input       oe,
    input       cs,
    input       we,
    input [6:0] address,
    inout [7:0] data
);


    integer i;
    reg [7:0] buffer;
    reg [7:0] memory [0:127];

    always @(posedge clk) begin
        if (reset) begin
            buffer <= 8'bz;
            for (i = 0; i < 128; i++) begin

                memory[i] <= 8'b0;

            end
        end if (cs) begin
            if (we && !oe) begin
                memory[address] <= data;
            end else if (!we && oe) begin
                buffer <= memory[address];
            end
        end
    end

    assign data = (cs && oe && !we && !reset) ? buffer : 8'bz;
endmodule
module sram(
    input       clk,
    input       reset,
    input       oe,
    input       cs,
    input       we,
    input [6:0] address,
    inout [7:0] data
);



    integer i;
    reg [7:0] buffer;
    reg [7:0] memory [0:127];

    always @(posedge clk) begin
        if (reset) begin
            buffer <= 8'bz;
            for (i = 0; i < 128; i++) begin

                memory[i] <= 8'b0;

            end
        end if (cs) begin
            if (we && !oe) begin
                memory[address] <= data;
            end else if (!we && oe) begin
                buffer <= memory[address];
            end
        end
    end

    assign data = (cs && oe && !we && !reset) ? buffer : 8'bz;
endmodule