data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:113: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$23  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:114: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$25  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/503970840/ad9874iq/verilog/ssi.v:115: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_cnt\' generates 6 bits.\n                                                                               : ... In instance AD9874SSIReceiver\n  assign \\$27  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;\n                 ^\n%Error: Exiting due to 3 warning(s)\n'
module AD9874SSIReceiver(frame_start_in, serial_data_in, iq_data_out, iq_strobe_out, clk, rst, serial_clock_in);
  reg \$auto$verilog_backend.cc:2083:dump_module$1  = 0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$1 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$13 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$15 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$19 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$21 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$23 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$25 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$27 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *)
  wire [6:0] \$29 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$3 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *)
  wire [6:0] \$30 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$7 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$9 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:66" *)
  wire bit_clock_fell;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:65" *)
  wire bit_clock_rose;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:60" *)
  wire bit_clock_synchronizer_bit_clock;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg delayed = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$11  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$11$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$17  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$17$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$5  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$5$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire edge_detected;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$12 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$18 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$6 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:72" *)
  wire frame_clock_fell;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:71" *)
  wire frame_clock_rose;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
  wire frame_clock_synchronizer_frame_clock;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:50" *)
  input frame_start_in;
  wire frame_start_in;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
  reg [1:0] \fsm_state$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:52" *)
  output [31:0] iq_data_out;
  reg [31:0] iq_data_out = 32'd0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:52" *)
  reg [31:0] \iq_data_out$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:53" *)
  output iq_strobe_out;
  reg iq_strobe_out = 1'h0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:53" *)
  reg \iq_strobe_out$next ;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:78" *)
  reg [31:0] rx_buf = 32'd0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:78" *)
  reg [31:0] \rx_buf$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:79" *)
  reg [5:0] rx_cnt = 6'h00;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:79" *)
  reg [5:0] \rx_cnt$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:48" *)
  input serial_clock_in;
  wire serial_clock_in;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:49" *)
  input serial_data_in;
  wire serial_data_in;
  assign \$9  = \delayed$5  & (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) \$7 ;
  assign \$13  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) \delayed$11 ;
  assign \$15  = \$13  & (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) frame_clock_synchronizer_frame_clock;
  assign \$1  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) delayed;
  assign \$19  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) frame_clock_synchronizer_frame_clock;
  assign \$21  = \delayed$17  & (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) \$19 ;
  assign \$23  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$25  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$27  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$30  = rx_cnt - (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *) 1'h1;
  always @(posedge clk)
    delayed <= \delayed$next ;
  always @(posedge clk)
    \delayed$5  <= \delayed$5$next ;
  always @(posedge clk)
    \delayed$11  <= \delayed$11$next ;
  always @(posedge clk)
    \delayed$17  <= \delayed$17$next ;
  always @(posedge clk)
    iq_strobe_out <= \iq_strobe_out$next ;
  always @(posedge clk)
    rx_buf <= \rx_buf$next ;
  always @(posedge clk)
    fsm_state <= \fsm_state$next ;
  always @(posedge clk)
    rx_cnt <= \rx_cnt$next ;
  assign \$3  = \$1  & (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) bit_clock_synchronizer_bit_clock;
  always @(posedge clk)
    iq_data_out <= \iq_data_out$next ;
  assign \$7  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) bit_clock_synchronizer_bit_clock;
  bit_clock_synchronizer bit_clock_synchronizer (
    .bit_clock(bit_clock_synchronizer_bit_clock),
    .clk(clk),
    .rst(rst),
    .serial_clock_in(serial_clock_in)
  );
  frame_clock_synchronizer frame_clock_synchronizer (
    .clk(clk),
    .frame_clock(frame_clock_synchronizer_frame_clock),
    .frame_start_in(frame_start_in),
    .rst(rst)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$next  = bit_clock_synchronizer_bit_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \iq_strobe_out$next  = iq_strobe_out;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          \iq_strobe_out$next  = 1'h0;


      2'h1:
;


      2'h2:
;


      2'h3:
          \iq_strobe_out$next  = 1'h1;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \iq_strobe_out$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \rx_buf$next  = rx_buf;
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          \rx_buf$next  = 32'd0;


      2'h1:
;


      2'h2:
          (* full_case = 32'd1 *)
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$23 )

            1'h1:
;

            default:
                (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:99" *)
                casez (bit_clock_fell)

                  1'h1:
                      \rx_buf$next  = { rx_buf[30:0], serial_data_in };
                endcase
          endcase
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \rx_buf$next  = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \fsm_state$next  = fsm_state;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:87" *)
          casez (frame_clock_rose)

            1'h1:
                \fsm_state$next  = 2'h1;
          endcase


      2'h1:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:92" *)
          casez (frame_clock_fell)

            1'h1:
                \fsm_state$next  = 2'h2;
          endcase


      2'h2:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$25 )

            1'h1:
                \fsm_state$next  = 2'h3;
          endcase


      2'h3:
          \fsm_state$next  = 2'h0;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \fsm_state$next  = 2'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \rx_cnt$next  = rx_cnt;
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
;


      2'h1:
          \rx_cnt$next  = 6'h20;


      2'h2:
          (* full_case = 32'd1 *)
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$27 )

            1'h1:
;

            default:
                (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:99" *)
                casez (bit_clock_fell)

                  1'h1:
                      \rx_cnt$next  = \$30 [5:0];
                endcase
          endcase
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \rx_cnt$next  = 6'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \iq_data_out$next  = iq_data_out;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
;


      2'h1:
;


      2'h2:
;


      2'h3:
          \iq_data_out$next  = rx_buf;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \iq_data_out$next  = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$5$next  = bit_clock_synchronizer_bit_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$5$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$11$next  = frame_clock_synchronizer_frame_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$11$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$17$next  = frame_clock_synchronizer_frame_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$17$next  = 1'h0;
    endcase
  end
  assign \$29  = \$30 ;
  assign frame_clock_fell = \edge_detected$18 ;
  assign frame_clock_rose = \edge_detected$12 ;
  assign \edge_detected$18  = \$21 ;
  assign \edge_detected$12  = \$15 ;
  assign bit_clock_fell = \edge_detected$6 ;
  assign bit_clock_rose = edge_detected;
  assign \edge_detected$6  = \$9 ;
  assign edge_detected = \$3 ;
endmodule
module AD9874SSIReceiver(frame_start_in, serial_data_in, iq_data_out, iq_strobe_out, clk, rst, serial_clock_in);

  reg \$auto$verilog_backend.cc:2083:dump_module$1  = 0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$1 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$13 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$15 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$19 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$21 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$23 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$25 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
  wire \$27 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *)
  wire [6:0] \$29 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *)
  wire \$3 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *)
  wire [6:0] \$30 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$7 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *)
  wire \$9 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:66" *)
  wire bit_clock_fell;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:65" *)
  wire bit_clock_rose;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:60" *)
  wire bit_clock_synchronizer_bit_clock;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg delayed = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$11  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$11$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$17  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$17$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$5  = 1'h0;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$5$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:35" *)
  reg \delayed$next ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire edge_detected;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$12 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$18 ;
  (* src = "/home/git/amlib/amlib/utils/__init__.py:39" *)
  wire \edge_detected$6 ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:72" *)
  wire frame_clock_fell;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:71" *)
  wire frame_clock_rose;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
  wire frame_clock_synchronizer_frame_clock;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:50" *)
  input frame_start_in;
  wire frame_start_in;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
  reg [1:0] \fsm_state$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:52" *)
  output [31:0] iq_data_out;
  reg [31:0] iq_data_out = 32'd0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:52" *)
  reg [31:0] \iq_data_out$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:53" *)
  output iq_strobe_out;
  reg iq_strobe_out = 1'h0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:53" *)
  reg \iq_strobe_out$next ;
  (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:78" *)
  reg [31:0] rx_buf = 32'd0;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:78" *)
  reg [31:0] \rx_buf$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:79" *)
  reg [5:0] rx_cnt = 6'h00;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:79" *)
  reg [5:0] \rx_cnt$next ;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:48" *)
  input serial_clock_in;
  wire serial_clock_in;
  (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:49" *)
  input serial_data_in;
  wire serial_data_in;
  assign \$9  = \delayed$5  & (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) \$7 ;
  assign \$13  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) \delayed$11 ;
  assign \$15  = \$13  & (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) frame_clock_synchronizer_frame_clock;
  assign \$1  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) delayed;
  assign \$19  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) frame_clock_synchronizer_frame_clock;
  assign \$21  = \delayed$17  & (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) \$19 ;
  assign \$23  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$25  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$27  = ! (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *) rx_cnt;
  assign \$30  = rx_cnt - (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:102" *) 1'h1;
  always @(posedge clk)
    delayed <= \delayed$next ;
  always @(posedge clk)
    \delayed$5  <= \delayed$5$next ;
  always @(posedge clk)
    \delayed$11  <= \delayed$11$next ;
  always @(posedge clk)
    \delayed$17  <= \delayed$17$next ;
  always @(posedge clk)
    iq_strobe_out <= \iq_strobe_out$next ;
  always @(posedge clk)
    rx_buf <= \rx_buf$next ;
  always @(posedge clk)
    fsm_state <= \fsm_state$next ;
  always @(posedge clk)
    rx_cnt <= \rx_cnt$next ;
  assign \$3  = \$1  & (* src = "/home/git/amlib/amlib/utils/__init__.py:43" *) bit_clock_synchronizer_bit_clock;
  always @(posedge clk)
    iq_data_out <= \iq_data_out$next ;
  assign \$7  = ~ (* src = "/home/git/amlib/amlib/utils/__init__.py:41" *) bit_clock_synchronizer_bit_clock;
  bit_clock_synchronizer bit_clock_synchronizer (
    .bit_clock(bit_clock_synchronizer_bit_clock),
    .clk(clk),
    .rst(rst),
    .serial_clock_in(serial_clock_in)
  );
  frame_clock_synchronizer frame_clock_synchronizer (
    .clk(clk),
    .frame_clock(frame_clock_synchronizer_frame_clock),
    .frame_start_in(frame_start_in),
    .rst(rst)
  );
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$next  = bit_clock_synchronizer_bit_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \iq_strobe_out$next  = iq_strobe_out;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          \iq_strobe_out$next  = 1'h0;


      2'h1:
;


      2'h2:
;


      2'h3:
          \iq_strobe_out$next  = 1'h1;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \iq_strobe_out$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \rx_buf$next  = rx_buf;
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          \rx_buf$next  = 32'd0;


      2'h1:
;


      2'h2:
          (* full_case = 32'd1 *)
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$23 )

            1'h1:
;

            default:
                (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:99" *)
                casez (bit_clock_fell)

                  1'h1:
                      \rx_buf$next  = { rx_buf[30:0], serial_data_in };
                endcase
          endcase
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \rx_buf$next  = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \fsm_state$next  = fsm_state;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:87" *)
          casez (frame_clock_rose)

            1'h1:
                \fsm_state$next  = 2'h1;
          endcase


      2'h1:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:92" *)
          casez (frame_clock_fell)

            1'h1:
                \fsm_state$next  = 2'h2;
          endcase


      2'h2:
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$25 )

            1'h1:
                \fsm_state$next  = 2'h3;
          endcase


      2'h3:
          \fsm_state$next  = 2'h0;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \fsm_state$next  = 2'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \rx_cnt$next  = rx_cnt;
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
;


      2'h1:
          \rx_cnt$next  = 6'h20;


      2'h2:
          (* full_case = 32'd1 *)
          (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:96" *)
          casez (\$27 )

            1'h1:
;

            default:
                (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:99" *)
                casez (bit_clock_fell)

                  1'h1:
                      \rx_cnt$next  = \$30 [5:0];
                endcase
          endcase
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \rx_cnt$next  = 6'h00;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \iq_data_out$next  = iq_data_out;
    (* full_case = 32'd1 *)
    (* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:81" *)
    casez (fsm_state)


      2'h0:
;


      2'h1:
;


      2'h2:
;


      2'h3:
          \iq_data_out$next  = rx_buf;
    endcase
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \iq_data_out$next  = 32'd0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$5$next  = bit_clock_synchronizer_bit_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$5$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$11$next  = frame_clock_synchronizer_frame_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$11$next  = 1'h0;
    endcase
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \delayed$17$next  = frame_clock_synchronizer_frame_clock;
    (* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \delayed$17$next  = 1'h0;
    endcase
  end
  assign \$29  = \$30 ;
  assign frame_clock_fell = \edge_detected$18 ;
  assign frame_clock_rose = \edge_detected$12 ;
  assign \edge_detected$18  = \$21 ;
  assign \edge_detected$12  = \$15 ;
  assign bit_clock_fell = \edge_detected$6 ;
  assign bit_clock_rose = edge_detected;
  assign \edge_detected$6  = \$9 ;
  assign edge_detected = \$3 ;
endmodule