data/full_repos/permissive/490649362/single-cycle/src/PC.v
data/verilator_xmls/3ff0886a-c029-4305-80e0-3ce0f4e8b41c.xml
module PC(clk, stall, in, out);

    input         clk;
    input         stall;
    input  [31:0] in;
    output [31:0] out;

    reg    [31:0] out;


    initial begin
        out = 32'b0;
    end


    always@(posedge clk) begin
        if (!stall) begin
            out = in;
        end
    end

endmodule
module PC(clk, stall, in, out);


    input         clk;
    input         stall;
    input  [31:0] in;
    output [31:0] out;

    reg    [31:0] out;


    initial begin
        out = 32'b0;
    end


    always@(posedge clk) begin
        if (!stall) begin
            out = in;
        end
    end

endmodule