data/full_repos/permissive/467771222/water.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/467771222/water.v:81: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dfr'\n                                                                   : ... In instance top_module\n            dfr = 1'b0;\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/467771222/water.v:83: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'dfr'\n                                                                   : ... In instance top_module\n            dfr = 1'b1;\n            ^~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 

    parameter IDLE = 2'd0, SENSOR_1 = 2'd1, SENSOR_2 = 2'd2, SENSOR_3 = 2'd3;
    reg[1:0] current_state, next_state;
    

    always@(*) begin
        case(current_state)
            IDLE : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_1 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_2 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_3 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            default: next_state = IDLE;
        endcase
    end
    

    always@(posedge clk) begin
        if(reset)
            current_state = IDLE;
        else
            current_state = next_state;
    end
    

    assign fr1 = (current_state == IDLE | current_state == SENSOR_1 | current_state == SENSOR_2);
    assign fr2 = (current_state == IDLE | current_state == SENSOR_1);
    assign fr3 = (current_state == IDLE);
    

    reg fr1_reg, fr2_reg, fr3_reg;
    always@(posedge clk) begin
        fr1_reg <= fr1;
    end
    always@(posedge clk) begin
        fr2_reg <= fr2;
    end
    always@(posedge clk) begin
        fr3_reg <= fr3;
    end
    
    
    always@(*) begin
        if(~fr1 & fr1_reg | ~fr2 & fr2_reg | ~fr3 & fr3_reg)
            dfr = 1'b0;
        else if(fr1 & ~fr1_reg | fr2 & ~fr2_reg | fr3 & ~fr3_reg)
            dfr = 1'b1;
    end

endmodule
module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
);
 

    parameter IDLE = 2'd0, SENSOR_1 = 2'd1, SENSOR_2 = 2'd2, SENSOR_3 = 2'd3;
    reg[1:0] current_state, next_state;
    

    always@(*) begin
        case(current_state)
            IDLE : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_1 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_2 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            SENSOR_3 : begin
                case(s)
                    3'b001 : next_state = SENSOR_1;
                    3'b011 : next_state = SENSOR_2;
                    3'b111 : next_state = SENSOR_3;
                    default : next_state = IDLE;
                endcase
            end
            default: next_state = IDLE;
        endcase
    end
    

    always@(posedge clk) begin
        if(reset)
            current_state = IDLE;
        else
            current_state = next_state;
    end
    

    assign fr1 = (current_state == IDLE | current_state == SENSOR_1 | current_state == SENSOR_2);
    assign fr2 = (current_state == IDLE | current_state == SENSOR_1);
    assign fr3 = (current_state == IDLE);
    

    reg fr1_reg, fr2_reg, fr3_reg;
    always@(posedge clk) begin
        fr1_reg <= fr1;
    end
    always@(posedge clk) begin
        fr2_reg <= fr2;
    end
    always@(posedge clk) begin
        fr3_reg <= fr3;
    end
    
    
    always@(*) begin
        if(~fr1 & fr1_reg | ~fr2 & fr2_reg | ~fr3 & fr3_reg)
            dfr = 1'b0;
        else if(fr1 & ~fr1_reg | fr2 & ~fr2_reg | fr3 & ~fr3_reg)
            dfr = 1'b1;
    end

endmodule