data/full_repos/permissive/429462627/mips_pipeline.v
1: b'%Error: data/full_repos/permissive/429462627/mips_pipeline.v:138: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " :A = %b,\\n\\t B = %b,\\n\\t ALU_ctrlerartion = %b,\\n\\t Result = %b,\\n\\t Carry Out = %b,\\n\\t Zero = %b.", A, B, ALU_ctrl, result, carry_out, zero);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #0  A = 32\'ha5a5a5a5; B = 32\'h5a5a5a5a; ALU_ctrl = 4\'b0000;      \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0001;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0010;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0110;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10  A = 32\'hA5A5A5A5; B = 32\'hA5A5A5A5; ALU_ctrl = 4\'b0110;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b0111;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b1100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #20  $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1090: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1096: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1098: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module EX_MEM_reg (
    input clk, reset,


    input EX_flush, 


    input RegWrite_in, MemtoReg_in, 


    input Branch_in, MemRead_in, MemWrite_in, Jump_in,
 

    input [31:0] jump_addr_in, branch_addr_in,
    input ALU_zero_in, 
    input [31:0] ALU_result_in, reg_read_data2_in,
    input [4:0] ID_EX_register_rd_in, 


    output reg RegWrite_out, MemtoReg_out, 
    output reg Branch_out, MemRead_out, MemWrite_out, Jump_out,  
    output reg [31:0] jump_addr_out, branch_addr_out, 
    output reg ALU_zero_out,  
    output reg [31:0] ALU_result_out, reg_read_data2_out, 
    output reg [4:0] EX_MEM_register_rd_out);

    always @(posedge clk or posedge reset)
    begin


        if (reset == 1)
        begin
            RegWrite_out <= 1'b0;
            MemtoReg_out <= 1'b0;
            Branch_out <= 1'b0;
            MemRead_out <= 1'b0;
            MemWrite_out <= 1'b0;
            Jump_out <= 1'b0;
            jump_addr_out <= 32'b0;
            branch_addr_out <= 32'b0;
            ALU_zero_out <= 1'b0;
            ALU_result_out <= 32'b0;
            reg_read_data2_out <= 32'b0;
            EX_MEM_register_rd_out <= 5'b0; 
        end



        else if (EX_flush == 1)
        begin
            RegWrite_out <= 1'b0;
            MemtoReg_out <= 1'b0;
            Branch_out <= 1'b0;
            MemRead_out <= 1'b0;
            MemWrite_out <= 1'b0;
            Jump_out <= 1'b0;
        end


        else 
            begin
                RegWrite_out <= RegWrite_in;
                MemtoReg_out <= MemtoReg_in;
                Branch_out <= Branch_in;
                MemRead_out <= MemRead_in;
                MemWrite_out <= MemWrite_in;
                Jump_out <= Jump_in;
                jump_addr_out <= jump_addr_in;
                branch_addr_out <= branch_addr_in;
                ALU_zero_out <= ALU_zero_in;
                ALU_result_out <= ALU_result_in;
                reg_read_data2_out <= reg_read_data2_in;
                EX_MEM_register_rd_out <= ID_EX_register_rd_in;
            end
        end
endmodule
module EX_MEM_reg (
    input clk, reset,


    input EX_flush, 


    input RegWrite_in, MemtoReg_in, 


    input Branch_in, MemRead_in, MemWrite_in, Jump_in,
 

    input [31:0] jump_addr_in, branch_addr_in,
    input ALU_zero_in, 
    input [31:0] ALU_result_in, reg_read_data2_in,
    input [4:0] ID_EX_register_rd_in, 


    output reg RegWrite_out, MemtoReg_out, 
    output reg Branch_out, MemRead_out, MemWrite_out, Jump_out,  
    output reg [31:0] jump_addr_out, branch_addr_out, 
    output reg ALU_zero_out,  
    output reg [31:0] ALU_result_out, reg_read_data2_out, 
    output reg [4:0] EX_MEM_register_rd_out);


    always @(posedge clk or posedge reset)
    begin


        if (reset == 1)
        begin
            RegWrite_out <= 1'b0;
            MemtoReg_out <= 1'b0;
            Branch_out <= 1'b0;
            MemRead_out <= 1'b0;
            MemWrite_out <= 1'b0;
            Jump_out <= 1'b0;
            jump_addr_out <= 32'b0;
            branch_addr_out <= 32'b0;
            ALU_zero_out <= 1'b0;
            ALU_result_out <= 32'b0;
            reg_read_data2_out <= 32'b0;
            EX_MEM_register_rd_out <= 5'b0; 
        end



        else if (EX_flush == 1)
        begin
            RegWrite_out <= 1'b0;
            MemtoReg_out <= 1'b0;
            Branch_out <= 1'b0;
            MemRead_out <= 1'b0;
            MemWrite_out <= 1'b0;
            Jump_out <= 1'b0;
        end


        else 
            begin
                RegWrite_out <= RegWrite_in;
                MemtoReg_out <= MemtoReg_in;
                Branch_out <= Branch_in;
                MemRead_out <= MemRead_in;
                MemWrite_out <= MemWrite_in;
                Jump_out <= Jump_in;
                jump_addr_out <= jump_addr_in;
                branch_addr_out <= branch_addr_in;
                ALU_zero_out <= ALU_zero_in;
                ALU_result_out <= ALU_result_in;
                reg_read_data2_out <= reg_read_data2_in;
                EX_MEM_register_rd_out <= ID_EX_register_rd_in;
            end
        end
endmodule