data/full_repos/permissive/507506290/RTL_Files/Program_counter.v
data/verilator_xmls/75ed2720-83d8-4ef8-bcfe-8856a3a0d6d8.xml
module Program_counter(
i_clk , 
i_rst_n ,
i_PC , 
o_PC  
);

input i_clk ;
input i_rst_n ;
input [`WIDTH_PC-1:0] i_PC;
output reg [`WIDTH_PC-1:0] o_PC ;

always @(posedge i_clk , negedge i_rst_n)
  begin
     if (~i_rst_n)
        begin
         o_PC <= 32'b0;
         end
      else
         begin
         o_PC = i_PC ;
         end
       end      
endmodule
module Program_counter(
i_clk , 
i_rst_n ,
i_PC , 
o_PC  
);


input i_clk ;
input i_rst_n ;
input [`WIDTH_PC-1:0] i_PC;
output reg [`WIDTH_PC-1:0] o_PC ;

always @(posedge i_clk , negedge i_rst_n)
  begin
     if (~i_rst_n)
        begin
         o_PC <= 32'b0;
         end
      else
         begin
         o_PC = i_PC ;
         end
       end      
endmodule