data/full_repos/permissive/417288846/List_1/Task_1/JK_latch.v
data/verilator_xmls/b67a8e9c-17d2-48b4-a686-700d01dd3610.xml
module jk_latch(input clk, j, k, output q);
   wire nq, buf_d;
   mux_4 mux1(.i1(q), .i2(1'b0), .i3(1'b1), .i4(nq), .s1(j), .s2(k), .out(buf_d));
   d_latch d1(.d(buf_d), .clk(clk), .q(q), .nq(nq));
endmodule
module jk_latch(input clk, j, k, output q);

   wire nq, buf_d;
   mux_4 mux1(.i1(q), .i2(1'b0), .i3(1'b1), .i4(nq), .s1(j), .s2(k), .out(buf_d));
   d_latch d1(.d(buf_d), .clk(clk), .q(q), .nq(nq));
endmodule