data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/tb_testbench.v
1: b'%Error: data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/tb_testbench.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/tb_testbench.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire [3:0] data;
wire [1:0] sel;
wire       out;
mux4x1_test tester(.t1(data),.t2(sel), .p(out));


mux4x1        dut (.in(data), .sel(sel), .out(out));

always @( data, sel, out )
begin
    $display("%4b %2b %b",data,sel,out);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire [3:0] data;
wire [1:0] sel;
wire       out;
mux4x1_test tester(.t1(data),.t2(sel), .p(out));


mux4x1        dut (.in(data), .sel(sel), .out(out));

always @( data, sel, out )
begin
    $display("%4b %2b %b",data,sel,out);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule