data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v
1: b'%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:20: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422178762/verilog/dv/i2c_test,data/full_repos/permissive/422178762/uprj_netlists.v\n             data/full_repos/permissive/422178762/verilog/dv/i2c_test,data/full_repos/permissive/422178762/uprj_netlists.v.v\n             data/full_repos/permissive/422178762/verilog/dv/i2c_test,data/full_repos/permissive/422178762/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:21: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:22: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:24: Cannot find include file: W25Q32JVxxIM.v\n`include "W25Q32JVxxIM.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:25: Cannot find include file: 24AA64.v\n`include "24AA64.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:38: Unsupported: wand\n        wand WPn,HOLDn;\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:62: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("i2c_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:63: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, i2c_test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:68: syntax error, unexpected \'@\'\n   repeat (1500) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:83: Unsupported: wait statements\n     wait(mprj_io[19:0] == 20\'hABCDE);   \n     ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n     #1 $display("GPIO state = %b ", mprj_io[19:0]);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/422178762/verilog/dv/i2c_test/i2c_test_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("GPO state = %h ", mprj_io[19:0]);\n  ^\n%Error: Exiting due to 10 error(s), 9 warning(s)\n'
module i2c_test_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

    	wire gpio;
    	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
        
        wand WPn,HOLDn;
	assign WPn  = 1'b1;
  	assign  HOLDn = 1'b1;



	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

	






	always #12.5 clock <= (clock === 1'b0);

        

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("i2c_test.vcd");
		$dumpvars(0, i2c_test_tb);



		repeat (30) begin
			repeat (1500) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

	    wait(mprj_io[19:0] == 20'hABCDE);
	    
	    #1 $display("GPIO state = %b ", mprj_io[19:0]);
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("GPO state = %h ", mprj_io[19:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("i2c_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);


wire spi_ssel;
wire spi_clk;
wire spi_mosi;
wire spi_miso;

assign spi_ssel = mprj_io[20];
assign spi_clk  = mprj_io[22];
assign mprj_io[23] = spi_miso;
assign spi_mosi  = mprj_io[24];

W25Q32JVxxIM user_spi_flash (
.CSn(spi_ssel),
.CLK(spi_clk),
.DIO(spi_mosi),
.DO(spi_miso),
.WPn(WPn),
.HOLDn(HOLDn),
.RESETn(RSTB)

);


M24AA64 user_i2c_eeprom (

.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.WP(1'b0),
.SDA(mprj_io[26]),
.SCL(mprj_io[25]),
.RESET(1'b0)




);




endmodule
module i2c_test_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

    	wire gpio;
    	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
        
        wand WPn,HOLDn;
	assign WPn  = 1'b1;
  	assign  HOLDn = 1'b1;



	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

	






	always #12.5 clock <= (clock === 1'b0);

        

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("i2c_test.vcd");
		$dumpvars(0, i2c_test_tb);



		repeat (30) begin
			repeat (1500) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

	    wait(mprj_io[19:0] == 20'hABCDE);
	    
	    #1 $display("GPIO state = %b ", mprj_io[19:0]);
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("GPO state = %h ", mprj_io[19:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("i2c_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);


wire spi_ssel;
wire spi_clk;
wire spi_mosi;
wire spi_miso;

assign spi_ssel = mprj_io[20];
assign spi_clk  = mprj_io[22];
assign mprj_io[23] = spi_miso;
assign spi_mosi  = mprj_io[24];

W25Q32JVxxIM user_spi_flash (
.CSn(spi_ssel),
.CLK(spi_clk),
.DIO(spi_mosi),
.DO(spi_miso),
.WPn(WPn),
.HOLDn(HOLDn),
.RESETn(RSTB)

);


M24AA64 user_i2c_eeprom (

.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.WP(1'b0),
.SDA(mprj_io[26]),
.SCL(mprj_io[25]),
.RESET(1'b0)




);




endmodule