data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v
1: b'%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:58: syntax error, unexpected \'.\'\n        .A          (bht_data_idx[LOCAL_DATA_ADDR_WIDTH-1:0]  ),\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #(10/2) bht_data_clk = ~bht_data_clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #(10/2) forever_clk    = ~forever_clk;\n  ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:85: syntax error, unexpected \'@\'\nrepeat(50)@(posedge bht_data_clk)\n          ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:94: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:100: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:104: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:109: syntax error, unexpected \'@\'\n        repeat(10)@(posedge bht_data_clk)\n                  ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:115: syntax error, unexpected \'=\', expecting IDENTIFIER\nbht_data_cen = 1;\n             ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:122: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:150: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:179: syntax error, unexpected \'@\'\n    @(posedge bht_data_clk)\n    ^\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:193: syntax error, unexpected $display\n        $display("bht array read/write test fail when addr is %d\\n", i);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/418753455/smart_run/impl/mem_validate/e906_bht_mem_test.v:198: syntax error, unexpected \'=\', expecting IDENTIFIER\n        bht_mem_test_pass = 1;\n                          ^\n%Error: Cannot continue\n'
module e906_bht_mem_test(bht_mem_test_pass);

output bht_mem_test_pass;
`ifdef BHT_2K
    parameter LOCAL_DATA_ADDR_WIDTH  = 7;
`elsif BHT_4K
    parameter LOCAL_DATA_ADDR_WIDTH  = 8;
`elsif BHT_8K
    parameter LOCAL_DATA_ADDR_WIDTH  = 9;
`elsif BHT_16K
    parameter LOCAL_DATA_ADDR_WIDTH  = 10;
`endif
    
parameter LOCAL_DATA_DATA_WIDTH = 16;
parameter LOCAL_DATA_WE_WIDTH   = 16;

reg                               forever_clk;

reg  [LOCAL_DATA_ADDR_WIDTH-1:0]  bht_data_idx;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  bht_data_din;
wire  [LOCAL_DATA_DATA_WIDTH-1:0]  bht_data_dout;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  data_mask;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  data_mask_ff;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  golden_data;
reg                               bht_data_gwen;
reg  [LOCAL_DATA_WE_WIDTH-1:0]    bht_data_wen;
reg                               bht_data_cen;
reg                               bht_data_clk;

reg                               bht_mem_test_pass;

`ifdef BHT_2K
    pa_spsram_128x16 x_bht_array(
`elsif BHT_4K
    pa_spsram_256x16 x_bht_array(
`elsif BHT_8K
    pa_spsram_512x16 x_bht_array(
`elsif BHT_16K
    pa_spsram_1024x16 x_bht_array(
`endif
        .A          (bht_data_idx[LOCAL_DATA_ADDR_WIDTH-1:0]  ),
        .CEN        (bht_data_cen                             ),
        .CLK        (bht_data_clk                             ),
        .D          (bht_data_din[LOCAL_DATA_DATA_WIDTH-1:0]  ),
        .GWEN       (bht_data_gwen                            ),
        .Q          (bht_data_dout[LOCAL_DATA_DATA_WIDTH-1:0] ),
        .WEN        (bht_data_wen[LOCAL_DATA_WE_WIDTH-1:0]    )
    );


always
  #(`CLK_PERIOD/2) bht_data_clk = ~bht_data_clk;
always
  #(`CLK_PERIOD/2) forever_clk    = ~forever_clk;

always@(posedge bht_data_clk)
begin
    data_mask <= bht_data_wen[LOCAL_DATA_WE_WIDTH-1:0];
end

integer i;

initial
begin
bht_data_clk = 0;
forever_clk = 0;
bht_mem_test_pass = 0;
repeat(50)@(posedge bht_data_clk)

bht_data_cen = 1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_gwen = 1'b1;
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<10;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen <= 0;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(bht_data_dout != golden_data)
    begin
        $display("bht array cen == 0 test fail when i is %d!!!\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end


bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=10;i<20;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen <= 1;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(bht_data_dout == golden_data)
    begin
        $display("bht array cen == 1 test fail when i is %d!!!\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end


bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<LOCAL_DATA_WE_WIDTH;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_idx  <= 20;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b1}} >> i;
    bht_data_din  <= {LOCAL_DATA_DATA_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    data_mask_ff  <= data_mask;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(golden_data != bht_data_dout & (~data_mask_ff))
    begin
        $display("bht array wen test fail when i is %d, golden_data is 0x%h, data out is 0x%h\n", i, golden_data, bht_data_dout);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end



bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<={LOCAL_DATA_ADDR_WIDTH{1'b1}};i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen  <= 0;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx  <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din  <= {LOCAL_DATA_DATA_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    bht_data_gwen <=1'b1;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    bht_data_idx  <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i + 1;
    if(bht_data_dout != {LOCAL_DATA_DATA_WIDTH{1'b1}})
    begin
        $display("bht array read/write test fail when addr is %d\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end
        bht_mem_test_pass = 1;
end





endmodule
module e906_bht_mem_test(bht_mem_test_pass);


output bht_mem_test_pass;
`ifdef BHT_2K
    parameter LOCAL_DATA_ADDR_WIDTH  = 7;
`elsif BHT_4K
    parameter LOCAL_DATA_ADDR_WIDTH  = 8;
`elsif BHT_8K
    parameter LOCAL_DATA_ADDR_WIDTH  = 9;
`elsif BHT_16K
    parameter LOCAL_DATA_ADDR_WIDTH  = 10;
`endif
    
parameter LOCAL_DATA_DATA_WIDTH = 16;
parameter LOCAL_DATA_WE_WIDTH   = 16;

reg                               forever_clk;

reg  [LOCAL_DATA_ADDR_WIDTH-1:0]  bht_data_idx;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  bht_data_din;
wire  [LOCAL_DATA_DATA_WIDTH-1:0]  bht_data_dout;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  data_mask;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  data_mask_ff;
reg  [LOCAL_DATA_DATA_WIDTH-1:0]  golden_data;
reg                               bht_data_gwen;
reg  [LOCAL_DATA_WE_WIDTH-1:0]    bht_data_wen;
reg                               bht_data_cen;
reg                               bht_data_clk;

reg                               bht_mem_test_pass;

`ifdef BHT_2K
    pa_spsram_128x16 x_bht_array(
`elsif BHT_4K
    pa_spsram_256x16 x_bht_array(
`elsif BHT_8K
    pa_spsram_512x16 x_bht_array(
`elsif BHT_16K
    pa_spsram_1024x16 x_bht_array(
`endif
        .A          (bht_data_idx[LOCAL_DATA_ADDR_WIDTH-1:0]  ),
        .CEN        (bht_data_cen                             ),
        .CLK        (bht_data_clk                             ),
        .D          (bht_data_din[LOCAL_DATA_DATA_WIDTH-1:0]  ),
        .GWEN       (bht_data_gwen                            ),
        .Q          (bht_data_dout[LOCAL_DATA_DATA_WIDTH-1:0] ),
        .WEN        (bht_data_wen[LOCAL_DATA_WE_WIDTH-1:0]    )
    );


always
  #(`CLK_PERIOD/2) bht_data_clk = ~bht_data_clk;
always
  #(`CLK_PERIOD/2) forever_clk    = ~forever_clk;

always@(posedge bht_data_clk)
begin
    data_mask <= bht_data_wen[LOCAL_DATA_WE_WIDTH-1:0];
end

integer i;

initial
begin
bht_data_clk = 0;
forever_clk = 0;
bht_mem_test_pass = 0;
repeat(50)@(posedge bht_data_clk)

bht_data_cen = 1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_gwen = 1'b1;
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<10;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen <= 0;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(bht_data_dout != golden_data)
    begin
        $display("bht array cen == 0 test fail when i is %d!!!\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end


bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=10;i<20;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen <= 1;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(bht_data_dout == golden_data)
    begin
        $display("bht array cen == 1 test fail when i is %d!!!\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end


bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<LOCAL_DATA_WE_WIDTH;i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_idx  <= 20;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b1}} >> i;
    bht_data_din  <= {LOCAL_DATA_DATA_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    bht_data_gwen <= 1'b1;
    bht_data_wen  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    golden_data   <= bht_data_din;
    data_mask_ff  <= data_mask;
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    if(golden_data != bht_data_dout & (~data_mask_ff))
    begin
        $display("bht array wen test fail when i is %d, golden_data is 0x%h, data out is 0x%h\n", i, golden_data, bht_data_dout);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end



bht_data_cen = 1;
bht_data_gwen = 1'b1;
bht_data_wen = {LOCAL_DATA_WE_WIDTH{1'b1}};
bht_data_idx = 0;
bht_data_din = 0;
for(i=0;i<={LOCAL_DATA_ADDR_WIDTH{1'b1}};i=i+1)
begin
    @(posedge bht_data_clk)
    bht_data_cen  <= 0;
    bht_data_gwen <= 1'b0;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b0}};
    bht_data_idx  <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
    bht_data_din  <= {LOCAL_DATA_DATA_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    bht_data_gwen <=1'b1;
    bht_data_wen <= {LOCAL_DATA_WE_WIDTH{1'b1}};
    @(posedge bht_data_clk)
    @(posedge bht_data_clk)
    bht_data_idx  <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i + 1;
    if(bht_data_dout != {LOCAL_DATA_DATA_WIDTH{1'b1}})
    begin
        $display("bht array read/write test fail when addr is %d\n", i);
        repeat(10)@(posedge bht_data_clk)
        $finish;
    end
end
        bht_mem_test_pass = 1;
end





endmodule