data/full_repos/permissive/495276914/Read.v
1: b'%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 21 bits.\n                                                              : ... In instance Read\n       imm2 = $signed({ins_dec_in[31],ins_dec_in[19:12],ins_dec_in[20],ins_dec_in[30:21],1\'b0});        \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:65: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 13 bits.\n                                                              : ... In instance Read\n       imm3 = $signed({ins_dec_in[31],ins_dec_in[7],ins_dec_in[30:25],ins_dec_in[11:8],1\'b0});   \n            ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:66: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                              : ... In instance Read\n       imm4 = $signed(ins_dec_in[31:20]);         \n            ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/Read.v:67: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                              : ... In instance Read\n       imm5 = $signed({ins_dec_in[31:25],ins_dec_in[11:7]});          \n            ^\n%Error: Exiting due to 4 warning(s)\n'
module Read(clk,PC,br_ctrl,rst,ins_dec_in,
            alu_out,alu_reg_w_en,alu_rd,
            wb_val,wb_en,wb_reg,
            alu_in1,alu_in2,alu_in3,ins_dec_out,pc2
            );
    input clk,rst,wb_en,alu_reg_w_en,br_ctrl;
    input [31:0]ins_dec_in,alu_out,wb_val,PC;
    input[4:0] wb_reg,alu_rd;
    output reg[31:0] ins_dec_out,alu_in3,pc2, alu_in1,alu_in2;
    
    wire[4:0] rs1,rs2;
    
    assign rs1=ins_dec_in[19:15];
    assign rs2=ins_dec_in[24:20]; 
    wire[31:0] rso1,rso2;
    regf regfile(clk,rst,wb_en,br_ctrl,
        rs1,rs2,wb_reg,
        wb_val,
        rso1,rso2);
    
    reg[31:0] nop;
    initial begin
        nop=32'h000033; 
    end
    reg[31:0] hz1,hz2;
    reg[4:0] d1,d2,r1,r2;  
    integer i;
    reg en1,en2,z;   
    reg[31:0] v1,v2,ro1,ro2,pc1,ins;      
    reg[6:0] op;
    reg [31:0] imm1,imm2,imm3,imm4,imm5;
    always@(posedge clk) begin
        ins_dec_out <= br_ctrl == 1 ? nop : ins_dec_in;
        v2 <=wb_val;
        d2 <=wb_reg;  
        pc2 <= PC;
        en2 <= wb_en;
        r1 <= ins_dec_in[19:15];
        r2 <= ins_dec_in[24:20];
        en1 <= alu_reg_w_en;
       imm1 = {ins_dec_in[31:12],12'b0};
       imm2 = $signed({ins_dec_in[31],ins_dec_in[19:12],ins_dec_in[20],ins_dec_in[30:21],1'b0});
       imm3 = $signed({ins_dec_in[31],ins_dec_in[7],ins_dec_in[30:25],ins_dec_in[11:8],1'b0});
       imm4 = $signed(ins_dec_in[31:20]);
       imm5 = $signed({ins_dec_in[31:25],ins_dec_in[11:7]});
    end
    
    always@(*)begin
        casez(ins_dec_out[6:0])                
            7'b0110011:begin alu_in3 = 0 ; end
            7'b0010011:begin alu_in3 = imm4 ; end
            7'b0000011:begin alu_in3 = imm4 ; end
            7'b0100011:begin alu_in3 = imm5 ; end
            7'b0110111:begin alu_in3 = imm1 ;  end
            7'b1101111:begin alu_in3 = imm2 ;  end
            7'b0010111:begin alu_in3 = imm4 ; end
            7'b1100011:begin alu_in3 = imm3 ; end
            default: begin  
                alu_in3 = 0;
            end
        endcase
     hz1  = r1 == 0 ? 0: (wb_en == 1 ? (wb_reg == r1 ? wb_val : rso1) : rso1 );
     hz2  = r2 == 0 ? 0: (wb_en == 1 ? (wb_reg == r2 ? wb_val : rso2) : rso2 );
     if(br_ctrl == 1)begin
        alu_in1=0;
        alu_in2=0;
     end
     else begin    
         alu_in1 = r1 == 0 ? 0 :(alu_reg_w_en == 1 ? (alu_rd == r1 ? alu_out : hz1) : hz1 );
         alu_in2 = r2 == 0 ? 0 :(alu_reg_w_en == 1 ? (alu_rd == r2 ? alu_out : hz2) : hz2 );
     end   
    end


endmodule
module Read(clk,PC,br_ctrl,rst,ins_dec_in,
            alu_out,alu_reg_w_en,alu_rd,
            wb_val,wb_en,wb_reg,
            alu_in1,alu_in2,alu_in3,ins_dec_out,pc2
            );

    input clk,rst,wb_en,alu_reg_w_en,br_ctrl;
    input [31:0]ins_dec_in,alu_out,wb_val,PC;
    input[4:0] wb_reg,alu_rd;
    output reg[31:0] ins_dec_out,alu_in3,pc2, alu_in1,alu_in2;
    
    wire[4:0] rs1,rs2;
    
    assign rs1=ins_dec_in[19:15];
    assign rs2=ins_dec_in[24:20]; 
    wire[31:0] rso1,rso2;
    regf regfile(clk,rst,wb_en,br_ctrl,
        rs1,rs2,wb_reg,
        wb_val,
        rso1,rso2);
    
    reg[31:0] nop;
    initial begin
        nop=32'h000033; 
    end
    reg[31:0] hz1,hz2;
    reg[4:0] d1,d2,r1,r2;  
    integer i;
    reg en1,en2,z;   
    reg[31:0] v1,v2,ro1,ro2,pc1,ins;      
    reg[6:0] op;
    reg [31:0] imm1,imm2,imm3,imm4,imm5;
    always@(posedge clk) begin
        ins_dec_out <= br_ctrl == 1 ? nop : ins_dec_in;
        v2 <=wb_val;
        d2 <=wb_reg;  
        pc2 <= PC;
        en2 <= wb_en;
        r1 <= ins_dec_in[19:15];
        r2 <= ins_dec_in[24:20];
        en1 <= alu_reg_w_en;
       imm1 = {ins_dec_in[31:12],12'b0};
       imm2 = $signed({ins_dec_in[31],ins_dec_in[19:12],ins_dec_in[20],ins_dec_in[30:21],1'b0});
       imm3 = $signed({ins_dec_in[31],ins_dec_in[7],ins_dec_in[30:25],ins_dec_in[11:8],1'b0});
       imm4 = $signed(ins_dec_in[31:20]);
       imm5 = $signed({ins_dec_in[31:25],ins_dec_in[11:7]});
    end
    
    always@(*)begin
        casez(ins_dec_out[6:0])                
            7'b0110011:begin alu_in3 = 0 ; end
            7'b0010011:begin alu_in3 = imm4 ; end
            7'b0000011:begin alu_in3 = imm4 ; end
            7'b0100011:begin alu_in3 = imm5 ; end
            7'b0110111:begin alu_in3 = imm1 ;  end
            7'b1101111:begin alu_in3 = imm2 ;  end
            7'b0010111:begin alu_in3 = imm4 ; end
            7'b1100011:begin alu_in3 = imm3 ; end
            default: begin  
                alu_in3 = 0;
            end
        endcase
     hz1  = r1 == 0 ? 0: (wb_en == 1 ? (wb_reg == r1 ? wb_val : rso1) : rso1 );
     hz2  = r2 == 0 ? 0: (wb_en == 1 ? (wb_reg == r2 ? wb_val : rso2) : rso2 );
     if(br_ctrl == 1)begin
        alu_in1=0;
        alu_in2=0;
     end
     else begin    
         alu_in1 = r1 == 0 ? 0 :(alu_reg_w_en == 1 ? (alu_rd == r1 ? alu_out : hz1) : hz1 );
         alu_in2 = r2 == 0 ? 0 :(alu_reg_w_en == 1 ? (alu_rd == r2 ? alu_out : hz2) : hz2 );
     end   
    end


endmodule