data/full_repos/permissive/522534105/RTL_files/Mux_2_1.v
data/verilator_xmls/0bdc82b0-a0b7-45cb-aba0-5a91be2bd359.xml
module Mux_2_1(
input [`WIDTH_OP-1:0]i_op_1, 
input [`WIDTH_OP-1:0]i_op_2 ,
input i_sel , 
output [`WIDTH_OP-1:0] o_out_Mux  
    );
    
  assign o_out_Mux = i_sel ? i_op_2 : i_op_1 ;
endmodule
module Mux_2_1(
input [`WIDTH_OP-1:0]i_op_1, 
input [`WIDTH_OP-1:0]i_op_2 ,
input i_sel , 
output [`WIDTH_OP-1:0] o_out_Mux  
    );

    
  assign o_out_Mux = i_sel ? i_op_2 : i_op_1 ;
endmodule