data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src/counter_7_seg.v
1: b"%Error: data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src/counter_7_seg.v:10: Cannot find file containing module: 'debouncer'\ndebouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src,data/full_repos/permissive/52871302/debouncer\n             data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src,data/full_repos/permissive/52871302/debouncer.v\n             data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src,data/full_repos/permissive/52871302/debouncer.sv\n             debouncer\n             debouncer.v\n             debouncer.sv\n             obj_dir/debouncer\n             obj_dir/debouncer.v\n             obj_dir/debouncer.sv\n%Error: data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src/counter_7_seg.v:11: Cannot find file containing module: 'debouncer'\ndebouncer d2(.CLK (CLK), .switch_input (switch_clear), .trans_dn (s_clear));\n^~~~~~~~~\n%Error: data/full_repos/permissive/52871302/elbert2/ch05_counter_7_seg/src/counter_7_seg.v:15: Cannot find file containing module: 'display_7_seg'\ndisplay_7_seg display(.CLK (CLK), \n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module counter_7_seg(
    input CLK,
    input switch_up,
    input switch_clear,
    output [7:0] SEG,
    output [2:0] DIGIT
    );

wire s_up, s_clear;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_clear), .trans_dn (s_clear));

reg [3:0] units, tens, hundreds;

display_7_seg display(.CLK (CLK), 
		.units (units), .tens (tens), .hundreds (hundreds),
		.SEG (SEG), .DIGIT (DIGIT));

always @(posedge CLK)
begin
  if (s_up)
  begin
	 units <= units + 1;
    if (units == 9) 
    begin
      units <= 0;
      tens <= tens + 1;
      if (tens == 9) 
      begin
        tens <= 0;
        hundreds <= hundreds + 1;
      end
    end		
  end
  if (s_clear)
  begin
    units <= 0;
    tens <= 0;
    hundreds <= 0;
  end
end

endmodule
module counter_7_seg(
    input CLK,
    input switch_up,
    input switch_clear,
    output [7:0] SEG,
    output [2:0] DIGIT
    );


wire s_up, s_clear;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_clear), .trans_dn (s_clear));

reg [3:0] units, tens, hundreds;

display_7_seg display(.CLK (CLK), 
		.units (units), .tens (tens), .hundreds (hundreds),
		.SEG (SEG), .DIGIT (DIGIT));

always @(posedge CLK)
begin
  if (s_up)
  begin
	 units <= units + 1;
    if (units == 9) 
    begin
      units <= 0;
      tens <= tens + 1;
      if (tens == 9) 
      begin
        tens <= 0;
        hundreds <= hundreds + 1;
      end
    end		
  end
  if (s_clear)
  begin
    units <= 0;
    tens <= 0;
    hundreds <= 0;
  end
end

endmodule