data/full_repos/permissive/501791642/ISE_devel/vsynth_test.v
1: b"%Error: data/full_repos/permissive/501791642/ISE_devel/vsynth_test.v:20: Cannot find file containing module: 'uart_rx'\nuart_rx uart (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx.v\n             data/full_repos/permissive/501791642/ISE_devel,data/full_repos/permissive/501791642/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/501791642/ISE_devel/vsynth_test.v:29: Cannot find file containing module: 'midi'\nmidi midi1(\n^~~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/vsynth_test.v:41: Cannot find file containing module: 'nco'\nnco osc (\n^~~\n%Error: data/full_repos/permissive/501791642/ISE_devel/vsynth_test.v:50: Cannot find file containing module: 'seg_8bit'\nseg_8bit disp (\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module vsynth_test (
	input CLK,
	input DI,
	input	 [3:0] CHANNEL,
	output [3:0] CHANNEL_LED,
	output [7:0] SAMPLE_OUT,
	output [7:0] SEG,
	output [3:0] AN
);

wire dv;
wire [7:0] uart_out;

wire [6:0] NOTE_NUM;
wire [6:0] NOTE_VEL;
wire [6:0] PROGRAM;

assign CHANNEL_LED = CHANNEL;

uart_rx uart (
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.DI(DI),
	.DV(dv),
	.PO(uart_out)
);

midi midi1(
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.CHANNEL(CHANNEL),
	.DATA(uart_out),
	.DV(dv),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM)
);

nco osc (
	.CLK(CLK),
	.CE(1'd1),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM),
	.SAMPLE_OUT(SAMPLE_OUT)
);

seg_8bit disp (
	.CLK(CLK),
	.CE(1'd1),
	.BIN_IN(PROGRAM),
	.SEG(SEG),
	.AN(AN)
);

endmodule
module vsynth_test (
	input CLK,
	input DI,
	input	 [3:0] CHANNEL,
	output [3:0] CHANNEL_LED,
	output [7:0] SAMPLE_OUT,
	output [7:0] SEG,
	output [3:0] AN
);


wire dv;
wire [7:0] uart_out;

wire [6:0] NOTE_NUM;
wire [6:0] NOTE_VEL;
wire [6:0] PROGRAM;

assign CHANNEL_LED = CHANNEL;

uart_rx uart (
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.DI(DI),
	.DV(dv),
	.PO(uart_out)
);

midi midi1(
	.CLK(CLK),
	.CE(1'd1),
	.RST(1'd0),
	.CHANNEL(CHANNEL),
	.DATA(uart_out),
	.DV(dv),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM)
);

nco osc (
	.CLK(CLK),
	.CE(1'd1),
	.NOTE_NUM(NOTE_NUM),
	.NOTE_VEL(NOTE_VEL),
	.PROGRAM(PROGRAM),
	.SAMPLE_OUT(SAMPLE_OUT)
);

seg_8bit disp (
	.CLK(CLK),
	.CE(1'd1),
	.BIN_IN(PROGRAM),
	.SEG(SEG),
	.AN(AN)
);

endmodule