data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:38: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:39: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:40: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:41: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:89: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n   parameter connectivity = `CONNECTIVITY_LINE;\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter connectivity = `CONNECTIVITY_LINE;\n                                              ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:93: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:94: Define or directive not defined: \'`CONNECTIVITY_RING\'\n (connectivity == `CONNECTIVITY_RING)) ?\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:96: Define or directive not defined: \'`CONNECTIVITY_FULL\'\n       (connectivity == `CONNECTIVITY_FULL) ?\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:108: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:111: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:111: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:115: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:115: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:138: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:138: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:140: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:142: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:162: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:162: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:166: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:166: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:175: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:175: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:177: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:179: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:184: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:184: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:187: Define or directive not defined: \'`REGFILE_TYPE_FF_2D\'\n   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:187: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;\n                                                  ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:190: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:190: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:206: Define or directive not defined: \'`ELIG_MASK_NONE\'\n   parameter elig_mask = `ELIG_MASK_NONE;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:206: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter elig_mask = `ELIG_MASK_NONE;\n                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:209: Define or directive not defined: \'`ELIG_MASK_USED\'\n   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);\n                                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:209: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);\n                                                                  ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:212: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NO_HOLD\'\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:212: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:217: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:217: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:347: Define or directive not defined: \'`ELIG_MASK_NONE\'\n    if(elig_mask == `ELIG_MASK_NONE)\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:347: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(elig_mask == `ELIG_MASK_NONE)\n                                   ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:700: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NONE\'\n      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:700: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                                                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ip_ctrl_mac.v:718: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 47 error(s)\n'
module vcr_ip_ctrl_mac
  (clk, reset, router_address, channel_in, route_ivc_op, route_ivc_orc, 
   allocated_ivc, flit_valid_ivc, flit_head_ivc, flit_tail_ivc, 
   free_nonspec_ivc, vc_gnt_ivc, vc_sel_ivc_ovc, sw_gnt, sw_sel_ivc, sw_gnt_op, 
   almost_full_op_ovc, full_op_ovc, flit_data, flow_ctrl_out, error);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter buffer_size = 32;
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam resource_class_idx_width = clogb(num_resource_classes);
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   parameter num_routers_per_dim = 4;
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   parameter num_dimensions = 2;
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   parameter num_nodes_per_router = 1;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);


   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   



   parameter restrict_turns = 1;
   

   localparam lar_info_width = port_idx_width + resource_class_idx_width;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam route_info_width = lar_info_width + dest_info_width + 1;
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter fb_fast_peek = 1;
   

   parameter explicit_pipeline_register = 0;
   


   parameter gate_buffer_write = 0;
   

   parameter sw_alloc_spec = 1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
      
   input clk;
   input reset;
   

   input [0:router_addr_width-1] router_address;
   

   input [0:channel_width-1] 	 channel_in;
   

   output [0:num_vcs*num_ports-1] route_ivc_op;
   wire [0:num_vcs*num_ports-1]   route_ivc_op;
   

   output [0:num_vcs*num_resource_classes-1] route_ivc_orc;
   wire [0:num_vcs*num_resource_classes-1]   route_ivc_orc;
   

   output [0:num_vcs-1] 		     allocated_ivc;
   wire [0:num_vcs-1] 			     allocated_ivc;
   

   output [0:num_vcs-1] 		     flit_valid_ivc;
   wire [0:num_vcs-1] 			     flit_valid_ivc;
   

   output [0:num_vcs-1] 		     flit_head_ivc;
   wire [0:num_vcs-1] 			     flit_head_ivc;
   

   output [0:num_vcs-1] 		     flit_tail_ivc;
   wire [0:num_vcs-1] 			     flit_tail_ivc;
   

   output [0:num_vcs-1] 		     free_nonspec_ivc;
   wire [0:num_vcs-1] 			     free_nonspec_ivc;
   

   input [0:num_vcs-1] 			     vc_gnt_ivc;
   

   input [0:num_vcs*num_vcs-1] 		     vc_sel_ivc_ovc;
   

   input 				     sw_gnt;
   

   input [0:num_vcs-1] 			     sw_sel_ivc;
   

   input [0:num_ports-1] 		     sw_gnt_op;
   

   input [0:num_ports*num_vcs-1] 	     almost_full_op_ovc;
   

   input [0:num_ports*num_vcs-1] 	     full_op_ovc;
   

   output [0:flit_data_width-1] 	     flit_data;
   wire [0:flit_data_width-1] 		     flit_data;
   

   output [0:flow_ctrl_width-1] 	     flow_ctrl_out;
   wire [0:flow_ctrl_width-1] 		     flow_ctrl_out;
   

   output 				     error;
   wire 				     error;
   
   



   
   wire 				     fb_full;
   
   wire 				     input_stage_active;
   assign input_stage_active = ~fb_full;
   
   wire 				     flit_valid_in;
   wire 				     flit_head_in;
   wire [0:num_vcs-1] 			     flit_head_in_ivc;
   wire 				     flit_tail_in;
   wire [0:num_vcs-1] 			     flit_tail_in_ivc;
   wire [0:flit_data_width-1] 		     flit_data_in;
   wire [0:num_vcs-1] 			     flit_sel_in_ivc;
   rtr_channel_input
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .max_payload_length(max_payload_length),
       .min_payload_length(min_payload_length),
       .route_info_width(route_info_width),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   chi
     (.clk(clk),
      .reset(reset),
      .active(input_stage_active),
      .channel_in(channel_in),
      .flit_valid_out(flit_valid_in),
      .flit_head_out(flit_head_in),
      .flit_head_out_ivc(flit_head_in_ivc),
      .flit_tail_out(flit_tail_in),
      .flit_tail_out_ivc(flit_tail_in_ivc),
      .flit_data_out(flit_data_in),
      .flit_sel_out_ivc(flit_sel_in_ivc));
   
   wire [0:header_info_width-1] 	     header_info_in;
   assign header_info_in = flit_data_in[0:header_info_width-1];
   
   



   
   wire [0:num_vcs-1] 			     free_spec_ivc;
   
   wire 				     flit_sent;
   
   generate
      
      if(sw_alloc_spec)
	begin
	   
	   wire [0:num_vcs-1] spec_mask_ivc;
	   
	   if(elig_mask == `ELIG_MASK_NONE)
	     assign spec_mask_ivc
	       = allocated_ivc | (vc_gnt_ivc & free_spec_ivc);
	   else
	     assign spec_mask_ivc = allocated_ivc | vc_gnt_ivc;
	   
	   wire 	      spec_mask;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   spec_mask_sel
	     (.select(sw_sel_ivc),
	      .data_in(spec_mask_ivc),
	      .data_out(spec_mask));
	   
	   assign flit_sent = sw_gnt & spec_mask;
	   
	end
      else
	assign flit_sent = sw_gnt;
      
   endgenerate
   
   



   
   wire [0:num_vcs-1] 	      fb_pop_tail_ivc;
   wire [0:header_info_width-1] fb_pop_next_header_info;
   wire [0:num_vcs-1] 		    fb_almost_empty_ivc;
   wire [0:num_vcs-1] 		    fb_empty_ivc;
   
   wire [0:num_vcs*lar_info_width-1] next_lar_info_ivc;
   wire [0:num_vcs*3-1] 	     ivcc_errors_ivc;
   



   genvar 			     ivc;
   
   generate
      
      for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
	begin:ivcs
	   



	   
	   wire flit_sel_in;
	   assign flit_sel_in = flit_sel_in_ivc[ivc];
	   
	   wire flit_head_in;
	   assign flit_head_in = flit_head_in_ivc[ivc];
	   
	   wire flit_tail_in;
	   assign flit_tail_in = flit_tail_in_ivc[ivc];
	   
	   wire vc_gnt;
	   assign vc_gnt = vc_gnt_ivc[ivc];
	   
	   wire [0:num_vcs-1] vc_sel_ovc;
	   assign vc_sel_ovc = vc_sel_ivc_ovc[ivc*num_vcs:(ivc+1)*num_vcs-1];
	   
	   wire 	      sw_sel;
	   assign sw_sel = sw_sel_ivc[ivc];
	   
	   wire 	      fb_pop_tail;
	   assign fb_pop_tail = fb_pop_tail_ivc[ivc];
	   
	   wire 	      fb_almost_empty;
	   assign fb_almost_empty = fb_almost_empty_ivc[ivc];
	   
	   



	   
	   wire 			    fb_empty;
	   assign fb_empty = fb_empty_ivc[ivc];
	   
	   wire [0:num_ports-1] 	    route_op;
	   wire [0:num_resource_classes-1]  route_orc;
	   wire 			    flit_valid;
	   wire 			    flit_head;
	   wire 			    flit_tail;
	   wire [0:lar_info_width-1] 	    next_lar_info;
	   wire 			    allocated;
	   wire 			    free_nonspec;
	   wire 			    free_spec;
	   wire [0:2] 			    ivcc_errors;
	   vcr_ivc_ctrl
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_routers_per_dim(num_routers_per_dim),
	       .num_dimensions(num_dimensions),
	       .num_nodes_per_router(num_nodes_per_router),
	       .connectivity(connectivity),
	       .packet_format(packet_format),
	       .max_payload_length(max_payload_length),
	       .min_payload_length(min_payload_length),
	       .restrict_turns(restrict_turns),
	       .routing_type(routing_type),
	       .dim_order(dim_order),
	       .elig_mask(elig_mask),
	       .sw_alloc_spec(sw_alloc_spec),
	       .fb_mgmt_type(fb_mgmt_type),
	       .explicit_pipeline_register(explicit_pipeline_register),
	       .vc_id(ivc),
	       .port_id(port_id),
	       .reset_type(reset_type))
	   ivcc
	     (.clk(clk),
	      .reset(reset),
	      .router_address(router_address),
	      .flit_valid_in(flit_valid_in),
	      .flit_head_in(flit_head_in),
	      .flit_tail_in(flit_tail_in),
	      .flit_sel_in(flit_sel_in),
	      .header_info_in(header_info_in),
	      .fb_pop_tail(fb_pop_tail),
	      .fb_pop_next_header_info(fb_pop_next_header_info),
	      .almost_full_op_ovc(almost_full_op_ovc),
	      .full_op_ovc(full_op_ovc),
	      .route_op(route_op),
	      .route_orc(route_orc),
	      .vc_gnt(vc_gnt),
	      .vc_sel_ovc(vc_sel_ovc),
	      .sw_gnt(sw_gnt),
	      .sw_sel(sw_sel),
	      .sw_gnt_op(sw_gnt_op),
	      .flit_valid(flit_valid),
	      .flit_head(flit_head),
	      .flit_tail(flit_tail),
	      .next_lar_info(next_lar_info),
	      .fb_almost_empty(fb_almost_empty),
	      .fb_empty(fb_empty),
	      .allocated(allocated),
	      .free_nonspec(free_nonspec),
	      .free_spec(free_spec),
	      .errors(ivcc_errors));
	   
	   



	   
	   assign route_ivc_op[ivc*num_ports:(ivc+1)*num_ports-1] = route_op;
	   assign route_ivc_orc[ivc*num_resource_classes:
				(ivc+1)*num_resource_classes-1] = route_orc;
	   assign flit_valid_ivc[ivc] = (ivc != 0 && flit_valid_ivc[0]) ? 0 : flit_valid;
	   assign flit_head_ivc[ivc] = flit_head;
	   assign flit_tail_ivc[ivc] = flit_tail;
	   assign next_lar_info_ivc[ivc*lar_info_width:(ivc+1)*lar_info_width-1]
	     = next_lar_info;
	   assign allocated_ivc[ivc] = allocated;
	   assign free_nonspec_ivc[ivc] = free_nonspec;
	   assign free_spec_ivc[ivc] = free_spec;
	   assign ivcc_errors_ivc[ivc*3:(ivc+1)*3-1] = ivcc_errors;
	   
	end
      
   endgenerate
   
   



   
   wire 				    fb_push_active;
   assign fb_push_active = flit_valid_in;
   
   wire 				    fb_push_valid;
   assign fb_push_valid = flit_valid_in;
   
   wire 				    fb_push_head;
   assign fb_push_head = flit_head_in;
   
   wire 				    fb_push_tail;
   assign fb_push_tail = flit_tail_in;
   
   wire [0:num_vcs-1] 			    fb_push_sel_ivc;
   assign fb_push_sel_ivc = flit_sel_in_ivc;
   
   wire [0:flit_data_width-1] 		    fb_push_data;
   assign fb_push_data = flit_data_in;
   
   wire 				    alloc_active;
   assign alloc_active = flit_valid_in | ~&fb_empty_ivc;
   
   wire 				    fb_pop_active;
   assign fb_pop_active = alloc_active;
   
   wire 				    fb_pop_valid;
   assign fb_pop_valid = flit_sent;
   
   wire [0:num_vcs-1] 			    fb_pop_sel_ivc;
   assign fb_pop_sel_ivc = sw_sel_ivc;
   
   wire [0:flit_data_width-1] 		    fb_pop_data;
   wire [0:num_vcs*2-1] 		    fb_errors_ivc;
   rtr_flit_buffer
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flit_data_width(flit_data_width),
       .header_info_width(header_info_width),
       .regfile_type(fb_regfile_type),
       .mgmt_type(fb_mgmt_type),
       .fast_peek(fb_fast_peek),
       .explicit_pipeline_register(explicit_pipeline_register),
       .gate_buffer_write(gate_buffer_write),
       .atomic_vc_allocation(atomic_vc_allocation),
       .enable_bypass(1),
       .reset_type(reset_type))
   fb
     (.clk(clk),
      .reset(reset),
      .push_active(fb_push_active),
      .push_valid(fb_push_valid),
      .push_head(fb_push_head),
      .push_tail(fb_push_tail),
      .push_sel_ivc(fb_push_sel_ivc),
      .push_data(fb_push_data),
      .pop_active(fb_pop_active),
      .pop_valid(fb_pop_valid),
      .pop_sel_ivc(fb_pop_sel_ivc),
      .pop_data(fb_pop_data),
      .pop_tail_ivc(fb_pop_tail_ivc),
      .pop_next_header_info(fb_pop_next_header_info),
      .almost_empty_ivc(fb_almost_empty_ivc),
      .empty_ivc(fb_empty_ivc),
      .full(fb_full),
      .errors_ivc(fb_errors_ivc));
   
   



   
   wire [0:lar_info_width-1] 	      next_lar_info;
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(lar_info_width))
   netx_lar_info_sel
     (.select(sw_sel_ivc),
      .data_in(next_lar_info_ivc),
      .data_out(next_lar_info));
   
   wire 			      flit_head;
   
   wire [0:lar_info_width-1] 	      lar_info_s, lar_info_q;
   assign lar_info_s = flit_head ? next_lar_info : lar_info_q;
   c_dff
     #(.width(lar_info_width),
       .reset_type(reset_type))
   lar_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(alloc_active),
      .d(lar_info_s),
      .q(lar_info_q));
   
   wire 			      flit_head_prev;
   
   assign flit_data[0:lar_info_width-1]
     = flit_head_prev ? lar_info_q : fb_pop_data[0:lar_info_width-1];
   assign flit_data[lar_info_width:flit_data_width-1]
     = fb_pop_data[lar_info_width:flit_data_width-1];
   
   



   











   
   wire 			      flit_sent_prev;
   
   wire 			      flit_valid_active;
   assign flit_valid_active = alloc_active | flit_sent_prev;
   
   wire 			      flit_valid_s, flit_valid_q;
   assign flit_valid_s = flit_sent;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   flit_validq
     (.clk(clk),
      .reset(reset),
      .active(flit_valid_active),
      .d(flit_valid_s),
      .q(flit_valid_q));
   
   assign flit_sent_prev = flit_valid_q;
   
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(1))
   flit_head_sel
     (.select(sw_sel_ivc),
      .data_in(flit_head_ivc),
      .data_out(flit_head));
   
   wire 			      flit_head_s, flit_head_q;
   assign flit_head_s = flit_head;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   flit_headq
     (.clk(clk),
      .reset(1'b0),
      .active(alloc_active),
      .d(flit_head_s),
      .q(flit_head_q));
   
   assign flit_head_prev = flit_head_q;
   
   



   
   rtr_flow_ctrl_output
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fco
     (.clk(clk),
      .reset(reset),
      .active(alloc_active),
      .fc_event_valid_in(flit_sent),
      .fc_event_sel_in_ivc(sw_sel_ivc),
      .flow_ctrl_out(flow_ctrl_out));
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_vcs*3+num_vcs*2-1] errors_s, errors_q;
	   assign errors_s = {ivcc_errors_ivc, fb_errors_ivc};
	   c_err_rpt
	     #(.num_errors(num_vcs*3+num_vcs*2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule
module vcr_ip_ctrl_mac
  (clk, reset, router_address, channel_in, route_ivc_op, route_ivc_orc, 
   allocated_ivc, flit_valid_ivc, flit_head_ivc, flit_tail_ivc, 
   free_nonspec_ivc, vc_gnt_ivc, vc_sel_ivc_ovc, sw_gnt, sw_sel_ivc, sw_gnt_op, 
   almost_full_op_ovc, full_op_ovc, flit_data, flow_ctrl_out, error);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter buffer_size = 32;
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam resource_class_idx_width = clogb(num_resource_classes);
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   parameter num_routers_per_dim = 4;
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   parameter num_dimensions = 2;
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   parameter num_nodes_per_router = 1;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);


   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   



   parameter restrict_turns = 1;
   

   localparam lar_info_width = port_idx_width + resource_class_idx_width;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam route_info_width = lar_info_width + dest_info_width + 1;
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter fb_fast_peek = 1;
   

   parameter explicit_pipeline_register = 0;
   


   parameter gate_buffer_write = 0;
   

   parameter sw_alloc_spec = 1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
      
   input clk;
   input reset;
   

   input [0:router_addr_width-1] router_address;
   

   input [0:channel_width-1] 	 channel_in;
   

   output [0:num_vcs*num_ports-1] route_ivc_op;
   wire [0:num_vcs*num_ports-1]   route_ivc_op;
   

   output [0:num_vcs*num_resource_classes-1] route_ivc_orc;
   wire [0:num_vcs*num_resource_classes-1]   route_ivc_orc;
   

   output [0:num_vcs-1] 		     allocated_ivc;
   wire [0:num_vcs-1] 			     allocated_ivc;
   

   output [0:num_vcs-1] 		     flit_valid_ivc;
   wire [0:num_vcs-1] 			     flit_valid_ivc;
   

   output [0:num_vcs-1] 		     flit_head_ivc;
   wire [0:num_vcs-1] 			     flit_head_ivc;
   

   output [0:num_vcs-1] 		     flit_tail_ivc;
   wire [0:num_vcs-1] 			     flit_tail_ivc;
   

   output [0:num_vcs-1] 		     free_nonspec_ivc;
   wire [0:num_vcs-1] 			     free_nonspec_ivc;
   

   input [0:num_vcs-1] 			     vc_gnt_ivc;
   

   input [0:num_vcs*num_vcs-1] 		     vc_sel_ivc_ovc;
   

   input 				     sw_gnt;
   

   input [0:num_vcs-1] 			     sw_sel_ivc;
   

   input [0:num_ports-1] 		     sw_gnt_op;
   

   input [0:num_ports*num_vcs-1] 	     almost_full_op_ovc;
   

   input [0:num_ports*num_vcs-1] 	     full_op_ovc;
   

   output [0:flit_data_width-1] 	     flit_data;
   wire [0:flit_data_width-1] 		     flit_data;
   

   output [0:flow_ctrl_width-1] 	     flow_ctrl_out;
   wire [0:flow_ctrl_width-1] 		     flow_ctrl_out;
   

   output 				     error;
   wire 				     error;
   
   



   
   wire 				     fb_full;
   
   wire 				     input_stage_active;
   assign input_stage_active = ~fb_full;
   
   wire 				     flit_valid_in;
   wire 				     flit_head_in;
   wire [0:num_vcs-1] 			     flit_head_in_ivc;
   wire 				     flit_tail_in;
   wire [0:num_vcs-1] 			     flit_tail_in_ivc;
   wire [0:flit_data_width-1] 		     flit_data_in;
   wire [0:num_vcs-1] 			     flit_sel_in_ivc;
   rtr_channel_input
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .max_payload_length(max_payload_length),
       .min_payload_length(min_payload_length),
       .route_info_width(route_info_width),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   chi
     (.clk(clk),
      .reset(reset),
      .active(input_stage_active),
      .channel_in(channel_in),
      .flit_valid_out(flit_valid_in),
      .flit_head_out(flit_head_in),
      .flit_head_out_ivc(flit_head_in_ivc),
      .flit_tail_out(flit_tail_in),
      .flit_tail_out_ivc(flit_tail_in_ivc),
      .flit_data_out(flit_data_in),
      .flit_sel_out_ivc(flit_sel_in_ivc));
   
   wire [0:header_info_width-1] 	     header_info_in;
   assign header_info_in = flit_data_in[0:header_info_width-1];
   
   



   
   wire [0:num_vcs-1] 			     free_spec_ivc;
   
   wire 				     flit_sent;
   
   generate
      
      if(sw_alloc_spec)
	begin
	   
	   wire [0:num_vcs-1] spec_mask_ivc;
	   
	   if(elig_mask == `ELIG_MASK_NONE)
	     assign spec_mask_ivc
	       = allocated_ivc | (vc_gnt_ivc & free_spec_ivc);
	   else
	     assign spec_mask_ivc = allocated_ivc | vc_gnt_ivc;
	   
	   wire 	      spec_mask;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   spec_mask_sel
	     (.select(sw_sel_ivc),
	      .data_in(spec_mask_ivc),
	      .data_out(spec_mask));
	   
	   assign flit_sent = sw_gnt & spec_mask;
	   
	end
      else
	assign flit_sent = sw_gnt;
      
   endgenerate
   
   



   
   wire [0:num_vcs-1] 	      fb_pop_tail_ivc;
   wire [0:header_info_width-1] fb_pop_next_header_info;
   wire [0:num_vcs-1] 		    fb_almost_empty_ivc;
   wire [0:num_vcs-1] 		    fb_empty_ivc;
   
   wire [0:num_vcs*lar_info_width-1] next_lar_info_ivc;
   wire [0:num_vcs*3-1] 	     ivcc_errors_ivc;
   



   genvar 			     ivc;
   
   generate
      
      for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
	begin:ivcs
	   



	   
	   wire flit_sel_in;
	   assign flit_sel_in = flit_sel_in_ivc[ivc];
	   
	   wire flit_head_in;
	   assign flit_head_in = flit_head_in_ivc[ivc];
	   
	   wire flit_tail_in;
	   assign flit_tail_in = flit_tail_in_ivc[ivc];
	   
	   wire vc_gnt;
	   assign vc_gnt = vc_gnt_ivc[ivc];
	   
	   wire [0:num_vcs-1] vc_sel_ovc;
	   assign vc_sel_ovc = vc_sel_ivc_ovc[ivc*num_vcs:(ivc+1)*num_vcs-1];
	   
	   wire 	      sw_sel;
	   assign sw_sel = sw_sel_ivc[ivc];
	   
	   wire 	      fb_pop_tail;
	   assign fb_pop_tail = fb_pop_tail_ivc[ivc];
	   
	   wire 	      fb_almost_empty;
	   assign fb_almost_empty = fb_almost_empty_ivc[ivc];
	   
	   



	   
	   wire 			    fb_empty;
	   assign fb_empty = fb_empty_ivc[ivc];
	   
	   wire [0:num_ports-1] 	    route_op;
	   wire [0:num_resource_classes-1]  route_orc;
	   wire 			    flit_valid;
	   wire 			    flit_head;
	   wire 			    flit_tail;
	   wire [0:lar_info_width-1] 	    next_lar_info;
	   wire 			    allocated;
	   wire 			    free_nonspec;
	   wire 			    free_spec;
	   wire [0:2] 			    ivcc_errors;
	   vcr_ivc_ctrl
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_routers_per_dim(num_routers_per_dim),
	       .num_dimensions(num_dimensions),
	       .num_nodes_per_router(num_nodes_per_router),
	       .connectivity(connectivity),
	       .packet_format(packet_format),
	       .max_payload_length(max_payload_length),
	       .min_payload_length(min_payload_length),
	       .restrict_turns(restrict_turns),
	       .routing_type(routing_type),
	       .dim_order(dim_order),
	       .elig_mask(elig_mask),
	       .sw_alloc_spec(sw_alloc_spec),
	       .fb_mgmt_type(fb_mgmt_type),
	       .explicit_pipeline_register(explicit_pipeline_register),
	       .vc_id(ivc),
	       .port_id(port_id),
	       .reset_type(reset_type))
	   ivcc
	     (.clk(clk),
	      .reset(reset),
	      .router_address(router_address),
	      .flit_valid_in(flit_valid_in),
	      .flit_head_in(flit_head_in),
	      .flit_tail_in(flit_tail_in),
	      .flit_sel_in(flit_sel_in),
	      .header_info_in(header_info_in),
	      .fb_pop_tail(fb_pop_tail),
	      .fb_pop_next_header_info(fb_pop_next_header_info),
	      .almost_full_op_ovc(almost_full_op_ovc),
	      .full_op_ovc(full_op_ovc),
	      .route_op(route_op),
	      .route_orc(route_orc),
	      .vc_gnt(vc_gnt),
	      .vc_sel_ovc(vc_sel_ovc),
	      .sw_gnt(sw_gnt),
	      .sw_sel(sw_sel),
	      .sw_gnt_op(sw_gnt_op),
	      .flit_valid(flit_valid),
	      .flit_head(flit_head),
	      .flit_tail(flit_tail),
	      .next_lar_info(next_lar_info),
	      .fb_almost_empty(fb_almost_empty),
	      .fb_empty(fb_empty),
	      .allocated(allocated),
	      .free_nonspec(free_nonspec),
	      .free_spec(free_spec),
	      .errors(ivcc_errors));
	   
	   



	   
	   assign route_ivc_op[ivc*num_ports:(ivc+1)*num_ports-1] = route_op;
	   assign route_ivc_orc[ivc*num_resource_classes:
				(ivc+1)*num_resource_classes-1] = route_orc;
	   assign flit_valid_ivc[ivc] = (ivc != 0 && flit_valid_ivc[0]) ? 0 : flit_valid;
	   assign flit_head_ivc[ivc] = flit_head;
	   assign flit_tail_ivc[ivc] = flit_tail;
	   assign next_lar_info_ivc[ivc*lar_info_width:(ivc+1)*lar_info_width-1]
	     = next_lar_info;
	   assign allocated_ivc[ivc] = allocated;
	   assign free_nonspec_ivc[ivc] = free_nonspec;
	   assign free_spec_ivc[ivc] = free_spec;
	   assign ivcc_errors_ivc[ivc*3:(ivc+1)*3-1] = ivcc_errors;
	   
	end
      
   endgenerate
   
   



   
   wire 				    fb_push_active;
   assign fb_push_active = flit_valid_in;
   
   wire 				    fb_push_valid;
   assign fb_push_valid = flit_valid_in;
   
   wire 				    fb_push_head;
   assign fb_push_head = flit_head_in;
   
   wire 				    fb_push_tail;
   assign fb_push_tail = flit_tail_in;
   
   wire [0:num_vcs-1] 			    fb_push_sel_ivc;
   assign fb_push_sel_ivc = flit_sel_in_ivc;
   
   wire [0:flit_data_width-1] 		    fb_push_data;
   assign fb_push_data = flit_data_in;
   
   wire 				    alloc_active;
   assign alloc_active = flit_valid_in | ~&fb_empty_ivc;
   
   wire 				    fb_pop_active;
   assign fb_pop_active = alloc_active;
   
   wire 				    fb_pop_valid;
   assign fb_pop_valid = flit_sent;
   
   wire [0:num_vcs-1] 			    fb_pop_sel_ivc;
   assign fb_pop_sel_ivc = sw_sel_ivc;
   
   wire [0:flit_data_width-1] 		    fb_pop_data;
   wire [0:num_vcs*2-1] 		    fb_errors_ivc;
   rtr_flit_buffer
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flit_data_width(flit_data_width),
       .header_info_width(header_info_width),
       .regfile_type(fb_regfile_type),
       .mgmt_type(fb_mgmt_type),
       .fast_peek(fb_fast_peek),
       .explicit_pipeline_register(explicit_pipeline_register),
       .gate_buffer_write(gate_buffer_write),
       .atomic_vc_allocation(atomic_vc_allocation),
       .enable_bypass(1),
       .reset_type(reset_type))
   fb
     (.clk(clk),
      .reset(reset),
      .push_active(fb_push_active),
      .push_valid(fb_push_valid),
      .push_head(fb_push_head),
      .push_tail(fb_push_tail),
      .push_sel_ivc(fb_push_sel_ivc),
      .push_data(fb_push_data),
      .pop_active(fb_pop_active),
      .pop_valid(fb_pop_valid),
      .pop_sel_ivc(fb_pop_sel_ivc),
      .pop_data(fb_pop_data),
      .pop_tail_ivc(fb_pop_tail_ivc),
      .pop_next_header_info(fb_pop_next_header_info),
      .almost_empty_ivc(fb_almost_empty_ivc),
      .empty_ivc(fb_empty_ivc),
      .full(fb_full),
      .errors_ivc(fb_errors_ivc));
   
   



   
   wire [0:lar_info_width-1] 	      next_lar_info;
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(lar_info_width))
   netx_lar_info_sel
     (.select(sw_sel_ivc),
      .data_in(next_lar_info_ivc),
      .data_out(next_lar_info));
   
   wire 			      flit_head;
   
   wire [0:lar_info_width-1] 	      lar_info_s, lar_info_q;
   assign lar_info_s = flit_head ? next_lar_info : lar_info_q;
   c_dff
     #(.width(lar_info_width),
       .reset_type(reset_type))
   lar_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(alloc_active),
      .d(lar_info_s),
      .q(lar_info_q));
   
   wire 			      flit_head_prev;
   
   assign flit_data[0:lar_info_width-1]
     = flit_head_prev ? lar_info_q : fb_pop_data[0:lar_info_width-1];
   assign flit_data[lar_info_width:flit_data_width-1]
     = fb_pop_data[lar_info_width:flit_data_width-1];
   
   



   











   
   wire 			      flit_sent_prev;
   
   wire 			      flit_valid_active;
   assign flit_valid_active = alloc_active | flit_sent_prev;
   
   wire 			      flit_valid_s, flit_valid_q;
   assign flit_valid_s = flit_sent;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   flit_validq
     (.clk(clk),
      .reset(reset),
      .active(flit_valid_active),
      .d(flit_valid_s),
      .q(flit_valid_q));
   
   assign flit_sent_prev = flit_valid_q;
   
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(1))
   flit_head_sel
     (.select(sw_sel_ivc),
      .data_in(flit_head_ivc),
      .data_out(flit_head));
   
   wire 			      flit_head_s, flit_head_q;
   assign flit_head_s = flit_head;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   flit_headq
     (.clk(clk),
      .reset(1'b0),
      .active(alloc_active),
      .d(flit_head_s),
      .q(flit_head_q));
   
   assign flit_head_prev = flit_head_q;
   
   



   
   rtr_flow_ctrl_output
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fco
     (.clk(clk),
      .reset(reset),
      .active(alloc_active),
      .fc_event_valid_in(flit_sent),
      .fc_event_sel_in_ivc(sw_sel_ivc),
      .flow_ctrl_out(flow_ctrl_out));
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_vcs*3+num_vcs*2-1] errors_s, errors_q;
	   assign errors_s = {ivcc_errors_ivc, fb_errors_ivc};
	   c_err_rpt
	     #(.num_errors(num_vcs*3+num_vcs*2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule