data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk_in = ~clk_in;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1980;  \n ^\n%Error: data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/419538859/lab1_1/freq_div_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,testbench);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench();

parameter	exp = 8;   
reg			clk_in, reset;
wire		clk_out;

freq_div freq_div_instance(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));


parameter	clkper = 10;

initial
begin
	clk_in = 1;
end

always 
begin
	#(clkper / 2)  clk_in = ~clk_in;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980;		
end

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end
endmodule
module 	testbench();


parameter	exp = 8;   
reg			clk_in, reset;
wire		clk_out;

freq_div freq_div_instance(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));


parameter	clkper = 10;

initial
begin
	clk_in = 1;
end

always 
begin
	#(clkper / 2)  clk_in = ~clk_in;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980;		
end

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end
endmodule