data/full_repos/permissive/40581558/fpga_sim/model_rec/receive_top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/40581558/fpga_sim/model_rec/receive_top_module_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #400;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/receive_top_module_tb.v:24: Cannot find file containing module: \'receive_top_module\'\n    receive_top_module   receive_top_module  (\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/receive_top_module\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/receive_top_module.v\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/receive_top_module.sv\n             receive_top_module\n             receive_top_module.v\n             receive_top_module.sv\n             obj_dir/receive_top_module\n             obj_dir/receive_top_module.v\n             obj_dir/receive_top_module.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  receive_top_module_tb  ;


   
       reg           clk_50M   ;

       reg           clk_100M  ;

       reg           reset_n   ;




       wire  [7:0]   Trans_Data ;





   


    receive_top_module   receive_top_module  (


     
              .clk_50M   (clk_50M),
  
             .clk_100M   (clk_100M),

             .reset_n    (reset_n) ,


    
            .Trans_Data (Trans_Data)

     );





   
  
     initial
             clk_100M   = 1'b0;
   always
              clk_100M   = #5 ~clk_100M;



    initial
             clk_50M   = 1'b0;
   always
              clk_50M   = #10 ~clk_50M;



    


   initial 
	begin
          reset_n   = 1'b0;
        #400;
          reset_n   = 1'b1;
   end










   endmodule
module  receive_top_module_tb  ;



   
       reg           clk_50M   ;

       reg           clk_100M  ;

       reg           reset_n   ;




       wire  [7:0]   Trans_Data ;





   


    receive_top_module   receive_top_module  (


     
              .clk_50M   (clk_50M),
  
             .clk_100M   (clk_100M),

             .reset_n    (reset_n) ,


    
            .Trans_Data (Trans_Data)

     );





   
  
     initial
             clk_100M   = 1'b0;
   always
              clk_100M   = #5 ~clk_100M;



    initial
             clk_50M   = 1'b0;
   always
              clk_50M   = #10 ~clk_50M;



    


   initial 
	begin
          reset_n   = 1'b0;
        #400;
          reset_n   = 1'b1;
   end










   endmodule