data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ctrlport_spi_master.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ctrlport_spi_master.v:64: Cannot find include file: ../../lib/rfnoc/core/ctrlport.vh\n  `include "../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/../../lib/rfnoc/core/ctrlport.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/../../lib/rfnoc/core/ctrlport.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/../../lib/rfnoc/core/ctrlport.vh.sv\n             ../../lib/rfnoc/core/ctrlport.vh\n             ../../lib/rfnoc/core/ctrlport.vh.v\n             ../../lib/rfnoc/core/ctrlport.vh.sv\n             obj_dir/../../lib/rfnoc/core/ctrlport.vh\n             obj_dir/../../lib/rfnoc/core/ctrlport.vh.v\n             obj_dir/../../lib/rfnoc/core/ctrlport.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ctrlport_spi_master #(
  parameter CPLD_ADDRESS_WIDTH     = 15,
  parameter MB_CPLD_BASE_ADDRESS   = 20'h8000,
  parameter DB_0_CPLD_BASE_ADDRESS = 20'h10000,
  parameter DB_1_CPLD_BASE_ADDRESS = 20'h18000
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input wire        s_ctrlport_req_wr,
  input wire        s_ctrlport_req_rd,
  input wire [19:0] s_ctrlport_req_addr,
  input wire [31:0] s_ctrlport_req_data,


  output reg        s_ctrlport_resp_ack     = 1'b0,
  output reg [ 1:0] s_ctrlport_resp_status  = 2'b0,
  output reg [31:0] s_ctrlport_resp_data    = 32'b0,


  output wire [1:0] ss,
  output wire       sclk,
  output wire       mosi,
  input  wire       miso,


  input wire [15:0] mb_clock_divider,
  input wire [15:0] db_clock_divider
);

  `include "../../lib/rfnoc/core/ctrlport.vh"


  reg  [31:0] set_data = 0;
  reg  [ 7:0] set_addr = 0;
  reg         set_stb  = 1'b0;

  wire [63:0] readback;
  wire        readback_stb;






  localparam [19:0] BASE_ADDRESS_MASK = {20{1'b1}} << CPLD_ADDRESS_WIDTH;


  wire mb_cpld_access   = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == MB_CPLD_BASE_ADDRESS;
  wire db_0_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_0_CPLD_BASE_ADDRESS;
  wire db_1_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_1_CPLD_BASE_ADDRESS;





  localparam IDLE            = 3'd0;
  localparam SET_DIVIDER     = 3'd1;
  localparam WRITE_SPI_MSB   = 3'd2;
  localparam WRITE_SPI_LSB   = 3'd3;
  localparam CONFIG_TRANSFER = 3'd4;
  localparam WAIT_SPI        = 3'd5;

  localparam DIVIDER_ADDRESS    = 8'd0;
  localparam CTRL_ADDRESS       = 8'd1;
  localparam DATA_UPPER_ADDRESS = 8'd2;
  localparam DATA_LOWER_ADDRESS = 8'd3;





  localparam CTRL_VALUE = 32'h40000000;

  reg [ 2:0] state = IDLE;
  reg [31:0] data_cache;
  reg [19:0] address_cache;
  reg        wr_cache;
  reg [15:0] divider;
  reg [ 1:0] cs;

  always @ (posedge ctrlport_clk) begin



    s_ctrlport_resp_ack <= 1'b0;
    set_stb <= 1'b0;

    case (state)
      IDLE: begin

        if (s_ctrlport_req_wr | s_ctrlport_req_rd) begin

          if (mb_cpld_access | db_0_cpld_access | db_1_cpld_access) begin
            state <= CONFIG_TRANSFER;
          end
        end


        if (mb_cpld_access) begin
          divider <= mb_clock_divider;
          cs      <= 2'b00;
        end else begin
          divider <= db_clock_divider;
          if (db_0_cpld_access) begin
            cs <= 2'b10;
          end else begin
            cs <= 2'b01;
          end
        end


        data_cache    <= s_ctrlport_req_data;
        address_cache <= s_ctrlport_req_addr;
        wr_cache      <= s_ctrlport_req_wr;
      end


      CONFIG_TRANSFER: begin
        state    <= SET_DIVIDER;

        set_stb  <= 1'b1;
        set_addr <= CTRL_ADDRESS;



        set_data <= CTRL_VALUE | {30'b0, ~cs};
      end


      SET_DIVIDER: begin
        state    <= WRITE_SPI_LSB;

        set_stb  <= 1'b1;
        set_addr <= DIVIDER_ADDRESS;
        set_data <= {16'b0, divider};
      end


      WRITE_SPI_LSB: begin
        state    <= WRITE_SPI_MSB;

        set_stb  <= 1'b1;
        set_addr <= DATA_LOWER_ADDRESS;
        set_data <= {data_cache[15:0], 16'bx};
      end


      WRITE_SPI_MSB: begin
        state    <= WAIT_SPI;

        set_stb  <= 1'b1;
        set_addr <= DATA_UPPER_ADDRESS;
        set_data <= {wr_cache, address_cache[14:0], data_cache[31:16]};
      end


      WAIT_SPI: begin
        s_ctrlport_resp_status <= readback[2] ? readback[1:0] : CTRL_STS_CMDERR;
        s_ctrlport_resp_data   <= wr_cache ? {CTRLPORT_DATA_W {1'b0}} : readback[39:8];
        s_ctrlport_resp_ack    <= readback_stb;

        if (readback_stb) begin
          state <= IDLE;
        end
      end

      default: begin
        state <= IDLE;
      end
    endcase


    if (ctrlport_rst) begin
      state <= IDLE;
      s_ctrlport_resp_ack <= 1'b0;
      set_stb <= 1'b0;
    end
  end





  simple_spi_core_64bit #(
    .BASE     (0),
    .WIDTH    (2),
    .CLK_IDLE (0),
    .SEN_IDLE (2'b11),
    .MAX_BITS (64)
  ) simple_spi_core_64bit_i (
    .clock        (ctrlport_clk),
    .reset        (ctrlport_rst),
    .set_stb      (set_stb),
    .set_addr     (set_addr),
    .set_data     (set_data),
    .readback     (readback),
    .readback_stb (readback_stb),
    .ready        (),
    .sen          (ss),
    .sclk         (sclk),
    .mosi         (mosi),
    .miso         (miso),
    .debug        ()
  );

endmodule
module ctrlport_spi_master #(
  parameter CPLD_ADDRESS_WIDTH     = 15,
  parameter MB_CPLD_BASE_ADDRESS   = 20'h8000,
  parameter DB_0_CPLD_BASE_ADDRESS = 20'h10000,
  parameter DB_1_CPLD_BASE_ADDRESS = 20'h18000
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input wire        s_ctrlport_req_wr,
  input wire        s_ctrlport_req_rd,
  input wire [19:0] s_ctrlport_req_addr,
  input wire [31:0] s_ctrlport_req_data,


  output reg        s_ctrlport_resp_ack     = 1'b0,
  output reg [ 1:0] s_ctrlport_resp_status  = 2'b0,
  output reg [31:0] s_ctrlport_resp_data    = 32'b0,


  output wire [1:0] ss,
  output wire       sclk,
  output wire       mosi,
  input  wire       miso,


  input wire [15:0] mb_clock_divider,
  input wire [15:0] db_clock_divider
);


  `include "../../lib/rfnoc/core/ctrlport.vh"


  reg  [31:0] set_data = 0;
  reg  [ 7:0] set_addr = 0;
  reg         set_stb  = 1'b0;

  wire [63:0] readback;
  wire        readback_stb;






  localparam [19:0] BASE_ADDRESS_MASK = {20{1'b1}} << CPLD_ADDRESS_WIDTH;


  wire mb_cpld_access   = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == MB_CPLD_BASE_ADDRESS;
  wire db_0_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_0_CPLD_BASE_ADDRESS;
  wire db_1_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_1_CPLD_BASE_ADDRESS;





  localparam IDLE            = 3'd0;
  localparam SET_DIVIDER     = 3'd1;
  localparam WRITE_SPI_MSB   = 3'd2;
  localparam WRITE_SPI_LSB   = 3'd3;
  localparam CONFIG_TRANSFER = 3'd4;
  localparam WAIT_SPI        = 3'd5;

  localparam DIVIDER_ADDRESS    = 8'd0;
  localparam CTRL_ADDRESS       = 8'd1;
  localparam DATA_UPPER_ADDRESS = 8'd2;
  localparam DATA_LOWER_ADDRESS = 8'd3;





  localparam CTRL_VALUE = 32'h40000000;

  reg [ 2:0] state = IDLE;
  reg [31:0] data_cache;
  reg [19:0] address_cache;
  reg        wr_cache;
  reg [15:0] divider;
  reg [ 1:0] cs;

  always @ (posedge ctrlport_clk) begin



    s_ctrlport_resp_ack <= 1'b0;
    set_stb <= 1'b0;

    case (state)
      IDLE: begin

        if (s_ctrlport_req_wr | s_ctrlport_req_rd) begin

          if (mb_cpld_access | db_0_cpld_access | db_1_cpld_access) begin
            state <= CONFIG_TRANSFER;
          end
        end


        if (mb_cpld_access) begin
          divider <= mb_clock_divider;
          cs      <= 2'b00;
        end else begin
          divider <= db_clock_divider;
          if (db_0_cpld_access) begin
            cs <= 2'b10;
          end else begin
            cs <= 2'b01;
          end
        end


        data_cache    <= s_ctrlport_req_data;
        address_cache <= s_ctrlport_req_addr;
        wr_cache      <= s_ctrlport_req_wr;
      end


      CONFIG_TRANSFER: begin
        state    <= SET_DIVIDER;

        set_stb  <= 1'b1;
        set_addr <= CTRL_ADDRESS;



        set_data <= CTRL_VALUE | {30'b0, ~cs};
      end


      SET_DIVIDER: begin
        state    <= WRITE_SPI_LSB;

        set_stb  <= 1'b1;
        set_addr <= DIVIDER_ADDRESS;
        set_data <= {16'b0, divider};
      end


      WRITE_SPI_LSB: begin
        state    <= WRITE_SPI_MSB;

        set_stb  <= 1'b1;
        set_addr <= DATA_LOWER_ADDRESS;
        set_data <= {data_cache[15:0], 16'bx};
      end


      WRITE_SPI_MSB: begin
        state    <= WAIT_SPI;

        set_stb  <= 1'b1;
        set_addr <= DATA_UPPER_ADDRESS;
        set_data <= {wr_cache, address_cache[14:0], data_cache[31:16]};
      end


      WAIT_SPI: begin
        s_ctrlport_resp_status <= readback[2] ? readback[1:0] : CTRL_STS_CMDERR;
        s_ctrlport_resp_data   <= wr_cache ? {CTRLPORT_DATA_W {1'b0}} : readback[39:8];
        s_ctrlport_resp_ack    <= readback_stb;

        if (readback_stb) begin
          state <= IDLE;
        end
      end

      default: begin
        state <= IDLE;
      end
    endcase


    if (ctrlport_rst) begin
      state <= IDLE;
      s_ctrlport_resp_ack <= 1'b0;
      set_stb <= 1'b0;
    end
  end





  simple_spi_core_64bit #(
    .BASE     (0),
    .WIDTH    (2),
    .CLK_IDLE (0),
    .SEN_IDLE (2'b11),
    .MAX_BITS (64)
  ) simple_spi_core_64bit_i (
    .clock        (ctrlport_clk),
    .reset        (ctrlport_rst),
    .set_stb      (set_stb),
    .set_addr     (set_addr),
    .set_data     (set_data),
    .readback     (readback),
    .readback_stb (readback_stb),
    .ready        (),
    .sen          (ss),
    .sclk         (sclk),
    .mosi         (mosi),
    .miso         (miso),
    .debug        ()
  );

endmodule