data/full_repos/permissive/510938582/rtl/ir.v
data/verilator_xmls/e5fa74e0-a6ed-4897-b5b3-79f8b5afac89.xml
module ir(din,clk,rst,irload,dout);
input [7:0]din;
input clk, rst, irload;
output [7:0]dout;
reg [7:0]dout;
always @(negedge clk or negedge rst )
	if(!rst) dout<=0;
	else if(irload) dout<=din;

endmodule
module ir(din,clk,rst,irload,dout);

input [7:0]din;
input clk, rst, irload;
output [7:0]dout;
reg [7:0]dout;
always @(negedge clk or negedge rst )
	if(!rst) dout<=0;
	else if(irload) dout<=din;

endmodule