data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("uut_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, uut_test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:63: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/512649487/verilog/dv/uut_test/uut_test_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO state = %b ", mprj_io[25:0]);\n  ^\n%Error: Exiting due to 3 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uut_test_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

    wire gpio;
    wire[37:0] mprj_io;
    reg [1:0] sel;
    reg [1:0] ad;

    reg [20:0] dat2;





    assign mprj_io[26:25]=sel;
    assign mprj_io[23:22]=ad;

    assign mprj_io[20:0]=dat2;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("uut_test.vcd");
		$dumpvars(0, uut_test_tb);


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

        
        sel<=2'b00;
        ad<=0;
 
        dat2=50;
        
        #500;
        
        sel<=2'b00;
        ad<=1;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b00;
        ad<=2;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b00;
        ad<=3;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b01;
        ad<=0;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b01;
        ad<=1;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b01;
        ad<=2;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b01;
        ad<=3;
        dat2<=10'b1010101010;
        
        #500;
        
        
        
        sel<=2'b10;
        ad<=0;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        sel<=2'b10;
        ad<=1;
        dat2<=20'b11111010101010101010;
        
        #500;
        
        
        sel<=2'b10;
        ad<=2;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        sel<=2'b10;
        ad<=3;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        
        
        
        
        
        
        
        
        









         

        





        
        






        
        
		
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[25:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("uut_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module uut_test_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

    wire gpio;
    wire[37:0] mprj_io;
    reg [1:0] sel;
    reg [1:0] ad;

    reg [20:0] dat2;





    assign mprj_io[26:25]=sel;
    assign mprj_io[23:22]=ad;

    assign mprj_io[20:0]=dat2;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("uut_test.vcd");
		$dumpvars(0, uut_test_tb);


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

        
        sel<=2'b00;
        ad<=0;
 
        dat2=50;
        
        #500;
        
        sel<=2'b00;
        ad<=1;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b00;
        ad<=2;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b00;
        ad<=3;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b01;
        ad<=0;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b01;
        ad<=1;
        dat2<=10'b1010101010;
        
        #500;
        
        
        sel<=2'b01;
        ad<=2;
        dat2<=10'b1010101010;
        
        #500;
        
        sel<=2'b01;
        ad<=3;
        dat2<=10'b1010101010;
        
        #500;
        
        
        
        sel<=2'b10;
        ad<=0;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        sel<=2'b10;
        ad<=1;
        dat2<=20'b11111010101010101010;
        
        #500;
        
        
        sel<=2'b10;
        ad<=2;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        sel<=2'b10;
        ad<=3;
        dat2<=20'b10101010101010101010;
        
        #500;
        
        
        
        
        
        
        
        
        
        









         

        





        
        






        
        
		
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[25:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("uut_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule