data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:7: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'TX\'\nmodule TX (Z, A, E);\n       ^~\n                                                                                   : ... Top module \'IV\'\nmodule IV (Z, A);\n       ^~\n                                                                                   : ... Top module \'BU\'\nmodule BU (Z, A);\n       ^~\n                                                                                   : ... Top module \'AN4\'\nmodule AN4 (Z, A, B, C, D);\n       ^~~\n                                                                                   : ... Top module \'AN3\'\nmodule AN3 (Z, A, B, C);\n       ^~~\n                                                                                   : ... Top module \'AN2\'\nmodule AN2 (Z, A, B);\n       ^~~\n                                                                                   : ... Top module \'ND4\'\nmodule ND4 (Z, A, B, C, D);\n       ^~~\n                                                                                   : ... Top module \'ND3\'\nmodule ND3 (Z, A, B, C);\n       ^~~\n                                                                                   : ... Top module \'ND2\'\nmodule ND2 (Z, A, B);\n       ^~~\n                                                                                   : ... Top module \'OR4\'\nmodule OR4 (Z, A, B, C, D);\n       ^~~\n                                                                                   : ... Top module \'OR3\'\nmodule OR3 (Z, A, B, C);\n       ^~~\n                                                                                   : ... Top module \'OR2\'\nmodule OR2 (Z, A, B);\n       ^~~\n                                                                                   : ... Top module \'NR4\'\nmodule NR4 (Z, A, B, C, D);\n       ^~~\n                                                                                   : ... Top module \'NR3\'\nmodule NR3 (Z, A, B, C);\n       ^~~\n                                                                                   : ... Top module \'NR2\'\nmodule NR2 (Z, A, B);\n       ^~~\n                                                                                   : ... Top module \'EO\'\nmodule EO (Z, A, B);\n       ^~\n                                                                                   : ... Top module \'MUX21H\'\nmodule MUX21H (Z, A, S, B);\n       ^~~~~~\n                                                                                   : ... Top module \'FDMASK\'\nmodule FDMASK (CP, Z, D, MASK);\n       ^~~~~~\n                                                                                   : ... Top module \'FD1\'\nmodule FD1 (CP, Z, D);\n       ^~~\n                                                                                   : ... Top module \'FD1S\'\nmodule FD1S (Z, QN, D, TI, CP, TE);\n       ^~~~\n                                                                                   : ... Top module \'FD1S2\'\nmodule FD1S2 (Z, QN, D, TI, CP, TE, MASK);\n       ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:134: Signal definition not found, creating implicitly: \'TEN\'\n                                                                                     : ... Suggested alternative: \'TE\'\nnot (TEN, TE);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:135: Signal definition not found, creating implicitly: \'NA1\'\nand (NA1, D, TEN);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:136: Signal definition not found, creating implicitly: \'NA2\'\n                                                                                     : ... Suggested alternative: \'NA1\'\nand (NA2, TI, TE);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:137: Signal definition not found, creating implicitly: \'MUX_D_TI\'\nor (MUX_D_TI, NA1, NA2);\n    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:140: Signal definition not found, creating implicitly: \'ZINT\'\nand (Z, ZINT, MASK);\n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:123: Signal definition not found, creating implicitly: \'TEN\'\n                                                                                     : ... Suggested alternative: \'TE\'\nnot (TEN, TE);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:124: Signal definition not found, creating implicitly: \'NA1\'\nand (NA1, D, TEN);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:125: Signal definition not found, creating implicitly: \'NA2\'\n                                                                                     : ... Suggested alternative: \'NA1\'\nand (NA2, TI, TE);\n     ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:126: Signal definition not found, creating implicitly: \'ZK\'\n                                                                                     : ... Suggested alternative: \'Z\'\nor (ZK, NA1, NA2);\n    ^~\n%Warning-IMPLICIT: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:111: Signal definition not found, creating implicitly: \'ZINT\'\nand (Z, ZINT, MASK);\n        ^~~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:139: Cannot find file containing module: \'DFF\'\nDFF I1 (.Q(ZINT), .D(MUX_D_TI), .CK(CP));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/DFF\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/DFF.v\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/DFF.sv\n             DFF\n             DFF.v\n             DFF.sv\n             obj_dir/DFF\n             obj_dir/DFF.v\n             obj_dir/DFF.sv\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:127: Cannot find file containing module: \'DFF\'\nDFF I1 (.Q(Z), .D(ZK), .CK(CP));\n^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:117: Cannot find file containing module: \'DFF\'\nDFF I1 (.Q(Z), .D(D), .CK(CP));\n^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/lib.v:110: Cannot find file containing module: \'DFF\'\nDFF I1 (.Q(ZINT), .D(D), .CK(CP));\n^~~\n%Error: Exiting due to 4 error(s), 11 warning(s)\n'
module ND2 (Z, A, B);
output Z;
input A, B;
nand (Z, A, B);
endmodule
module ND2 (Z, A, B);

output Z;
input A, B;
nand (Z, A, B);
endmodule