data/full_repos/permissive/479844313/Patterns/verilog/2x2_trojan1_location2_node2.v
1: b'%Error: data/full_repos/permissive/479844313/Patterns/verilog/2x2_trojan1_location2_node2.v:9: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule 2x2_ved (a0,b0,a1,b1,q0,q1,q2,q3);\n       ^\n%Error: data/full_repos/permissive/479844313/Patterns/verilog/2x2_trojan1_location2_node2.v:17: syntax error, unexpected and\nand AND2_1 (q0, a0, b0);\n^~~\n%Error: Exiting due to 2 error(s)\n'
module 2x2_ved (a0,b0,a1,b1,q0,q1,q2,q3);

input a0,b0,a1,b1;

output q0,q1,q2,q3;

wire n1,n2,n3,n4,n5,n6,n7;

and AND2_1 (q0, a0, b0);
and AND2_2 (n1, a1, b0);
and AND2_3 (n2, a0, b1);
and AND2_4 (n3, a1, b1);
not NOT1_1 (n5, n2);
xor XOR2_1 (n6, n2, n5);
or OR2_1 (n7, n5, n6);
xor XOR2_5 (q1, n1, n7);
and AND2_6 (n4, n1, n7);
xor XOR2_7 (q2, n3, n4);
and AND2_8 (q3, n3, n4);

endmodule
module 2x2_ved (a0,b0,a1,b1,q0,q1,q2,q3);


input a0,b0,a1,b1;

output q0,q1,q2,q3;

wire n1,n2,n3,n4,n5,n6,n7;

and AND2_1 (q0, a0, b0);
and AND2_2 (n1, a1, b0);
and AND2_3 (n2, a0, b1);
and AND2_4 (n3, a1, b1);
not NOT1_1 (n5, n2);
xor XOR2_1 (n6, n2, n5);
or OR2_1 (n7, n5, n6);
xor XOR2_5 (q1, n1, n7);
and AND2_6 (n4, n1, n7);
xor XOR2_7 (q2, n3, n4);
and AND2_8 (q3, n3, n4);

endmodule