data/full_repos/permissive/426889244/verilog/WallaceMult.v
1: b"%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:31: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/FullAdder\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/FullAdder.v\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/FullAdder.sv\n             FullAdder\n             FullAdder.v\n             FullAdder.sv\n             obj_dir/FullAdder\n             obj_dir/FullAdder.v\n             obj_dir/FullAdder.sv\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:40: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:60: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:69: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:87: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:96: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:113: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:122: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:140: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:149: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:168: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:177: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:197: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:206: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:223: Cannot find file containing module: 'FullAdder'\n                FullAdder fa_inst(\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/426889244/verilog/WallaceMult.v:232: Cannot find file containing module: 'FullAdder'\n            FullAdder fa_inst_31(\n            ^~~~~~~~~\n%Error: Exiting due to 16 error(s)\n"
module WallaceMult (
    input wire[31:0] opr1,
    input wire[31:0] opr2,

    output wire[31:0] result
);
    wire[31:0] stage_0_result[31:0];

    genvar i;
    genvar j;
    generate
        for (i = 0; i < 32; i = i + 1) begin: GEN_I_0
            for (j = 0; j < i; j = j + 1) begin: GEN_J_0_LESS
                assign stage_0_result[i][j] = 0;
            end

            for (j = i; j < 32; j = j + 1) begin: GEN_J_0_GREATER
                assign stage_0_result[i][j] = opr2[i] & opr1[j - i];
            end
        end
    endgenerate

    wire[31:0] stage_1_result[21:0];

    generate
        for (i = 0; i < 10; i = i + 1) begin: GEN_I_1_FA
            assign stage_1_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_1_FA
                FullAdder fa_inst(
                    .in1(stage_0_result[3 * i + 0][j]),
                    .in2(stage_0_result[3 * i + 1][j]),
                    .in3(stage_0_result[3 * i + 2][j]),
                    .out(stage_1_result[2 * i + 0][j]),
                    .carry(stage_1_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_0_result[3 * i + 0][31]),
                .in2(stage_0_result[3 * i + 1][31]),
                .in3(stage_0_result[3 * i + 2][31]),
                .out(stage_1_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_1_result[20] = stage_0_result[30];
    assign stage_1_result[21] = stage_0_result[31];


    wire[31:0] stage_2_result[14:0];

    generate
        for (i = 0; i < 7; i = i + 1) begin: GEN_I_2_FA
            assign stage_2_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_2_FA
                FullAdder fa_inst(
                    .in1(stage_1_result[3 * i + 0][j]),
                    .in2(stage_1_result[3 * i + 1][j]),
                    .in3(stage_1_result[3 * i + 2][j]),
                    .out(stage_2_result[2 * i + 0][j]),
                    .carry(stage_2_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_1_result[3 * i + 0][31]),
                .in2(stage_1_result[3 * i + 1][31]),
                .in3(stage_1_result[3 * i + 2][31]),
                .out(stage_2_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_2_result[14] = stage_1_result[21];

    
    wire[31:0] stage_3_result[9:0];

    generate
        for (i = 0; i < 5; i = i + 1) begin: GEN_I_3_FA
            assign stage_3_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_3_FA
                FullAdder fa_inst(
                    .in1(stage_2_result[3 * i + 0][j]),
                    .in2(stage_2_result[3 * i + 1][j]),
                    .in3(stage_2_result[3 * i + 2][j]),
                    .out(stage_3_result[2 * i + 0][j]),
                    .carry(stage_3_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_2_result[3 * i + 0][31]),
                .in2(stage_2_result[3 * i + 1][31]),
                .in3(stage_2_result[3 * i + 2][31]),
                .out(stage_3_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate


    wire[31:0] stage_4_result[6:0];

    generate
        for (i = 0; i < 3; i = i + 1) begin: GEN_I_4_FA
            assign stage_4_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_4_FA
                FullAdder fa_inst(
                    .in1(stage_3_result[3 * i + 0][j]),
                    .in2(stage_3_result[3 * i + 1][j]),
                    .in3(stage_3_result[3 * i + 2][j]),
                    .out(stage_4_result[2 * i + 0][j]),
                    .carry(stage_4_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_3_result[3 * i + 0][31]),
                .in2(stage_3_result[3 * i + 1][31]),
                .in3(stage_3_result[3 * i + 2][31]),
                .out(stage_4_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_4_result[6] = stage_3_result[9];


    wire[31:0] stage_5_result[4:0];
    generate
        for (i = 0; i < 2; i = i + 1) begin: GEN_I_5_FA
            assign stage_5_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_5_FA
                FullAdder fa_inst(
                    .in1(stage_4_result[3 * i + 0][j]),
                    .in2(stage_4_result[3 * i + 1][j]),
                    .in3(stage_4_result[3 * i + 2][j]),
                    .out(stage_5_result[2 * i + 0][j]),
                    .carry(stage_5_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_4_result[3 * i + 0][31]),
                .in2(stage_4_result[3 * i + 1][31]),
                .in3(stage_4_result[3 * i + 2][31]),
                .out(stage_5_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_5_result[4] = stage_4_result[6];


    wire[31:0] stage_6_result[3:0];

    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_6_FA
            assign stage_6_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_6_FA
                FullAdder fa_inst(
                    .in1(stage_5_result[3 * i + 0][j]),
                    .in2(stage_5_result[3 * i + 1][j]),
                    .in3(stage_5_result[3 * i + 2][j]),
                    .out(stage_6_result[2 * i + 0][j]),
                    .carry(stage_6_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_5_result[3 * i + 0][31]),
                .in2(stage_5_result[3 * i + 1][31]),
                .in3(stage_5_result[3 * i + 2][31]),
                .out(stage_6_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_6_result[2] = stage_5_result[3];
    assign stage_6_result[3] = stage_5_result[4];



    wire[31:0] stage_7_result[2:0];

    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_7_FA
            assign stage_7_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_7_FA
                FullAdder fa_inst(
                    .in1(stage_6_result[3 * i + 0][j]),
                    .in2(stage_6_result[3 * i + 1][j]),
                    .in3(stage_6_result[3 * i + 2][j]),
                    .out(stage_7_result[2 * i + 0][j]),
                    .carry(stage_7_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_6_result[3 * i + 0][31]),
                .in2(stage_6_result[3 * i + 1][31]),
                .in3(stage_6_result[3 * i + 2][31]),
                .out(stage_7_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_7_result[2] = stage_6_result[3];


    wire[31:0] stage_8_result[1:0];
    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_8_FA
            assign stage_8_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_8_FA
                FullAdder fa_inst(
                    .in1(stage_7_result[3 * i + 0][j]),
                    .in2(stage_7_result[3 * i + 1][j]),
                    .in3(stage_7_result[3 * i + 2][j]),
                    .out(stage_8_result[2 * i + 0][j]),
                    .carry(stage_8_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_7_result[3 * i + 0][31]),
                .in2(stage_7_result[3 * i + 1][31]),
                .in3(stage_7_result[3 * i + 2][31]),
                .out(stage_8_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign result = stage_8_result[0] + stage_8_result[1];
endmodule
module WallaceMult (
    input wire[31:0] opr1,
    input wire[31:0] opr2,

    output wire[31:0] result
);

    wire[31:0] stage_0_result[31:0];

    genvar i;
    genvar j;
    generate
        for (i = 0; i < 32; i = i + 1) begin: GEN_I_0
            for (j = 0; j < i; j = j + 1) begin: GEN_J_0_LESS
                assign stage_0_result[i][j] = 0;
            end

            for (j = i; j < 32; j = j + 1) begin: GEN_J_0_GREATER
                assign stage_0_result[i][j] = opr2[i] & opr1[j - i];
            end
        end
    endgenerate

    wire[31:0] stage_1_result[21:0];

    generate
        for (i = 0; i < 10; i = i + 1) begin: GEN_I_1_FA
            assign stage_1_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_1_FA
                FullAdder fa_inst(
                    .in1(stage_0_result[3 * i + 0][j]),
                    .in2(stage_0_result[3 * i + 1][j]),
                    .in3(stage_0_result[3 * i + 2][j]),
                    .out(stage_1_result[2 * i + 0][j]),
                    .carry(stage_1_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_0_result[3 * i + 0][31]),
                .in2(stage_0_result[3 * i + 1][31]),
                .in3(stage_0_result[3 * i + 2][31]),
                .out(stage_1_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_1_result[20] = stage_0_result[30];
    assign stage_1_result[21] = stage_0_result[31];


    wire[31:0] stage_2_result[14:0];

    generate
        for (i = 0; i < 7; i = i + 1) begin: GEN_I_2_FA
            assign stage_2_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_2_FA
                FullAdder fa_inst(
                    .in1(stage_1_result[3 * i + 0][j]),
                    .in2(stage_1_result[3 * i + 1][j]),
                    .in3(stage_1_result[3 * i + 2][j]),
                    .out(stage_2_result[2 * i + 0][j]),
                    .carry(stage_2_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_1_result[3 * i + 0][31]),
                .in2(stage_1_result[3 * i + 1][31]),
                .in3(stage_1_result[3 * i + 2][31]),
                .out(stage_2_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_2_result[14] = stage_1_result[21];

    
    wire[31:0] stage_3_result[9:0];

    generate
        for (i = 0; i < 5; i = i + 1) begin: GEN_I_3_FA
            assign stage_3_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_3_FA
                FullAdder fa_inst(
                    .in1(stage_2_result[3 * i + 0][j]),
                    .in2(stage_2_result[3 * i + 1][j]),
                    .in3(stage_2_result[3 * i + 2][j]),
                    .out(stage_3_result[2 * i + 0][j]),
                    .carry(stage_3_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_2_result[3 * i + 0][31]),
                .in2(stage_2_result[3 * i + 1][31]),
                .in3(stage_2_result[3 * i + 2][31]),
                .out(stage_3_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate


    wire[31:0] stage_4_result[6:0];

    generate
        for (i = 0; i < 3; i = i + 1) begin: GEN_I_4_FA
            assign stage_4_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_4_FA
                FullAdder fa_inst(
                    .in1(stage_3_result[3 * i + 0][j]),
                    .in2(stage_3_result[3 * i + 1][j]),
                    .in3(stage_3_result[3 * i + 2][j]),
                    .out(stage_4_result[2 * i + 0][j]),
                    .carry(stage_4_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_3_result[3 * i + 0][31]),
                .in2(stage_3_result[3 * i + 1][31]),
                .in3(stage_3_result[3 * i + 2][31]),
                .out(stage_4_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_4_result[6] = stage_3_result[9];


    wire[31:0] stage_5_result[4:0];
    generate
        for (i = 0; i < 2; i = i + 1) begin: GEN_I_5_FA
            assign stage_5_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_5_FA
                FullAdder fa_inst(
                    .in1(stage_4_result[3 * i + 0][j]),
                    .in2(stage_4_result[3 * i + 1][j]),
                    .in3(stage_4_result[3 * i + 2][j]),
                    .out(stage_5_result[2 * i + 0][j]),
                    .carry(stage_5_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_4_result[3 * i + 0][31]),
                .in2(stage_4_result[3 * i + 1][31]),
                .in3(stage_4_result[3 * i + 2][31]),
                .out(stage_5_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign stage_5_result[4] = stage_4_result[6];


    wire[31:0] stage_6_result[3:0];

    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_6_FA
            assign stage_6_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_6_FA
                FullAdder fa_inst(
                    .in1(stage_5_result[3 * i + 0][j]),
                    .in2(stage_5_result[3 * i + 1][j]),
                    .in3(stage_5_result[3 * i + 2][j]),
                    .out(stage_6_result[2 * i + 0][j]),
                    .carry(stage_6_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_5_result[3 * i + 0][31]),
                .in2(stage_5_result[3 * i + 1][31]),
                .in3(stage_5_result[3 * i + 2][31]),
                .out(stage_6_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_6_result[2] = stage_5_result[3];
    assign stage_6_result[3] = stage_5_result[4];



    wire[31:0] stage_7_result[2:0];

    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_7_FA
            assign stage_7_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_7_FA
                FullAdder fa_inst(
                    .in1(stage_6_result[3 * i + 0][j]),
                    .in2(stage_6_result[3 * i + 1][j]),
                    .in3(stage_6_result[3 * i + 2][j]),
                    .out(stage_7_result[2 * i + 0][j]),
                    .carry(stage_7_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_6_result[3 * i + 0][31]),
                .in2(stage_6_result[3 * i + 1][31]),
                .in3(stage_6_result[3 * i + 2][31]),
                .out(stage_7_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate
    assign stage_7_result[2] = stage_6_result[3];


    wire[31:0] stage_8_result[1:0];
    generate
        for (i = 0; i < 1; i = i + 1) begin: GEN_I_8_FA
            assign stage_8_result[2 * i + 1][0] = 0;
            for (j = 0; j < 31; j = j + 1) begin: GEN_J_8_FA
                FullAdder fa_inst(
                    .in1(stage_7_result[3 * i + 0][j]),
                    .in2(stage_7_result[3 * i + 1][j]),
                    .in3(stage_7_result[3 * i + 2][j]),
                    .out(stage_8_result[2 * i + 0][j]),
                    .carry(stage_8_result[2 * i + 1][j + 1])
                );
            end

            FullAdder fa_inst_31(
                .in1(stage_7_result[3 * i + 0][31]),
                .in2(stage_7_result[3 * i + 1][31]),
                .in3(stage_7_result[3 * i + 2][31]),
                .out(stage_8_result[2 * i + 0][31]),
                .carry()
            );
        end
    endgenerate

    assign result = stage_8_result[0] + stage_8_result[1];
endmodule