data/full_repos/permissive/425063349/Counter.v
data/verilator_xmls/32e7f477-e27a-4128-b36f-6d8d6571286a.xml
module Counter (output reg Done, output reg [3:0] Count, input [3:0] N, input Up, Clear, Clock);
	always @ (posedge Clock or posedge Clear) begin
		if (Up)
			Count <= Count + 1;
		else if (Clear)
			Count <= 4'b0000;
			
		if (Count == N) 
			assign Done = 1'b1;
		else
			assign Done = 1'b0;
	end
endmodule
module Counter (output reg Done, output reg [3:0] Count, input [3:0] N, input Up, Clear, Clock);

	always @ (posedge Clock or posedge Clear) begin
		if (Up)
			Count <= Count + 1;
		else if (Clear)
			Count <= 4'b0000;
			
		if (Count == N) 
			assign Done = 1'b1;
		else
			assign Done = 1'b0;
	end
endmodule