data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:186: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 6 bits.\n                                                                                                               : ... In instance BinaryRepr.u_pad_20\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:186: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 10 bits.\n                                                                                                               : ... In instance BinaryRepr.u_pad_21\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:179: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                               : ... In instance BinaryRepr.s_pad_16\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:179: Operator COND expects 20 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 12 bits.\n                                                                                                               : ... In instance BinaryRepr.s_pad_17\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:179: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 6 bits.\n                                                                                                               : ... In instance BinaryRepr.s_pad_18\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:179: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 10 bits.\n                                                                                                               : ... In instance BinaryRepr.s_pad_19\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:163: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                               : ... In instance BinaryRepr.s_shr_6\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:163: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                               : ... In instance BinaryRepr.s_shr_7\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:163: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                               : ... In instance BinaryRepr.s_shr_10\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:163: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                               : ... In instance BinaryRepr.s_shr_11\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/BinaryRepr/reference/BinaryRepr.v:141: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                               : ... In instance BinaryRepr.u_shr_3\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Error: Exiting due to 11 warning(s)\n'
module PAD_SIGNED(y, in);
    parameter width = 4;
    parameter n = 4;
    output [(n > width ? n : width)-1:0] y;
    input [width-1:0] in;
    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;
endmodule
module PAD_SIGNED(y, in);

    parameter width = 4;
    parameter n = 4;
    output [(n > width ? n : width)-1:0] y;
    input [width-1:0] in;
    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;
endmodule