data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v
1: b"%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:24: Cannot find file containing module: 'reset_en_ff'\nreset_en_ff pcFF (.clk(clk), .reset(reset), .en(PCEn), .d(PCNext), .q(PC));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/reset_en_ff\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/reset_en_ff.v\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/reset_en_ff.sv\n             reset_en_ff\n             reset_en_ff.v\n             reset_en_ff.sv\n             obj_dir/reset_en_ff\n             obj_dir/reset_en_ff.v\n             obj_dir/reset_en_ff.sv\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:27: Cannot find file containing module: 'mux21'\nmux21 pcmux (.a(PC), .b(ALUOut), .sel(IorD), .y(Adr));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:30: Cannot find file containing module: 'instrdataMem'\ninstrdataMem idmem (.clk(clk), .wrEn(MemWrite), .addr(Adr), .wrData(rd2_reg), .rdData(IRData));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:33: Cannot find file containing module: 'reset_en_ff'\nreset_en_ff instr_reg (.clk(clk), .reset(reset), .en(IRWrite), .d(IRData), .q(Instr));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:38: Cannot find file containing module: 'reset_ff'\nreset_ff data_reg (.clk(clk), .reset(reset), .d(IRData), .q(Data));\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:41: Cannot find file containing module: 'mux21'\nmux21 #(.WIDTH(5)) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:44: Cannot find file containing module: 'mux21'\nmux21 memtoRegmux (.a(ALUOut), .b(Data), .sel(MemtoReg), .y(wrData));\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:47: Cannot find file containing module: 'reg_file'\nreg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:52: Cannot find file containing module: 'reset_ff'\nreset_ff rfd1_reg (.clk(clk), .reset(reset), .d(rdData1), .q(rd1_reg));\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:55: Cannot find file containing module: 'reset_ff'\nreset_ff rfd2_reg (.clk(clk), .reset(reset), .d(rdData2), .q(rd2_reg));\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:58: Cannot find file containing module: 'signExt'\nsignExt signext1 (.a(Instr[15:0]), .y(SignImm));\n^~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:61: Cannot find file containing module: 'shftl2'\nshftl2 sl1 (.a(SignImm), .y(SignImmShft));\n^~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:64: Cannot find file containing module: 'mux21'\nmux21 srcAmux (.a(PC), .b(rd1_reg), .sel(ALUSrcA), .y(srcA)); \n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:67: Cannot find file containing module: 'mux41'\nmux41 srcBmux (.a(rd2_reg), .b(32'h4), .c(SignImm), .d(SignImmShft),\n^~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:71: Cannot find file containing module: 'alu'\nalu alu1 (.srcA(srcA), .srcB(srcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));\n^~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:74: Cannot find file containing module: 'reset_ff'\nreset_ff aluRes_reg (.clk(clk), .reset(reset), .d(ALUResult), .q(ALUOut));\n^~~~~~~~\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/datapath.v:77: Cannot find file containing module: 'mux41'\nmux41 resmux (.a(ALUResult), .b(ALUOut), .c({PC[31:28], Instr[25:0], 2'b00}), .d(),.sel(PCSrc), .y(PCNext));\n^~~~~\n%Error: Exiting due to 17 error(s)\n"
module datapath (
  input             clk, reset,
  input             PCEn, IorD, MemWrite, IRWrite, RegDst, 
  input             MemtoReg, RegWrite, ALUSrcA,
  input       [1:0] PCSrc, ALUSrcB,
  input       [2:0] ALUCtrl,
  output wire [5:0] OPCode, Funct,
  output            Z
);




wire [31:0] PC, Adr;
wire [31:0] IRData, Instr;
wire [31:0] Data;
wire [4:0]  wrReg;
wire [31:0] ALUOut, wrData, rdData1, rdData2;
wire [31:0] rd1_reg, rd2_reg;
wire [31:0] SignImm, SignImmShft;
wire [31:0] srcA, srcB, ALUResult;
wire [31:0] PCNext;

reset_en_ff pcFF (.clk(clk), .reset(reset), .en(PCEn), .d(PCNext), .q(PC));


mux21 pcmux (.a(PC), .b(ALUOut), .sel(IorD), .y(Adr));


instrdataMem idmem (.clk(clk), .wrEn(MemWrite), .addr(Adr), .wrData(rd2_reg), .rdData(IRData));


reset_en_ff instr_reg (.clk(clk), .reset(reset), .en(IRWrite), .d(IRData), .q(Instr));
assign OPCode = Instr[31:26];
assign Funct = Instr[5:0];


reset_ff data_reg (.clk(clk), .reset(reset), .d(IRData), .q(Data));


mux21 #(.WIDTH(5)) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));


mux21 memtoRegmux (.a(ALUOut), .b(Data), .sel(MemtoReg), .y(wrData));


reg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),
             .wrAddr(wrReg), .regWrite(RegWrite), .wrData(wrData),
             .rdData1(rdData1), .rdData2(rdData2));
             

reset_ff rfd1_reg (.clk(clk), .reset(reset), .d(rdData1), .q(rd1_reg));


reset_ff rfd2_reg (.clk(clk), .reset(reset), .d(rdData2), .q(rd2_reg));


signExt signext1 (.a(Instr[15:0]), .y(SignImm));


shftl2 sl1 (.a(SignImm), .y(SignImmShft));


mux21 srcAmux (.a(PC), .b(rd1_reg), .sel(ALUSrcA), .y(srcA)); 


mux41 srcBmux (.a(rd2_reg), .b(32'h4), .c(SignImm), .d(SignImmShft),
                            .sel(ALUSrcB), .y(srcB));


alu alu1 (.srcA(srcA), .srcB(srcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));


reset_ff aluRes_reg (.clk(clk), .reset(reset), .d(ALUResult), .q(ALUOut));


mux41 resmux (.a(ALUResult), .b(ALUOut), .c({PC[31:28], Instr[25:0], 2'b00}), .d(),.sel(PCSrc), .y(PCNext));

endmodule
module datapath (
  input             clk, reset,
  input             PCEn, IorD, MemWrite, IRWrite, RegDst, 
  input             MemtoReg, RegWrite, ALUSrcA,
  input       [1:0] PCSrc, ALUSrcB,
  input       [2:0] ALUCtrl,
  output wire [5:0] OPCode, Funct,
  output            Z
);





wire [31:0] PC, Adr;
wire [31:0] IRData, Instr;
wire [31:0] Data;
wire [4:0]  wrReg;
wire [31:0] ALUOut, wrData, rdData1, rdData2;
wire [31:0] rd1_reg, rd2_reg;
wire [31:0] SignImm, SignImmShft;
wire [31:0] srcA, srcB, ALUResult;
wire [31:0] PCNext;

reset_en_ff pcFF (.clk(clk), .reset(reset), .en(PCEn), .d(PCNext), .q(PC));


mux21 pcmux (.a(PC), .b(ALUOut), .sel(IorD), .y(Adr));


instrdataMem idmem (.clk(clk), .wrEn(MemWrite), .addr(Adr), .wrData(rd2_reg), .rdData(IRData));


reset_en_ff instr_reg (.clk(clk), .reset(reset), .en(IRWrite), .d(IRData), .q(Instr));
assign OPCode = Instr[31:26];
assign Funct = Instr[5:0];


reset_ff data_reg (.clk(clk), .reset(reset), .d(IRData), .q(Data));


mux21 #(.WIDTH(5)) regDstmux (.a(Instr[20:16]), .b(Instr[15:11]), .sel(RegDst), .y(wrReg));


mux21 memtoRegmux (.a(ALUOut), .b(Data), .sel(MemtoReg), .y(wrData));


reg_file rf (.clk(clk), .rdAddr1(Instr[25:21]), .rdAddr2(Instr[20:16]),
             .wrAddr(wrReg), .regWrite(RegWrite), .wrData(wrData),
             .rdData1(rdData1), .rdData2(rdData2));
             

reset_ff rfd1_reg (.clk(clk), .reset(reset), .d(rdData1), .q(rd1_reg));


reset_ff rfd2_reg (.clk(clk), .reset(reset), .d(rdData2), .q(rd2_reg));


signExt signext1 (.a(Instr[15:0]), .y(SignImm));


shftl2 sl1 (.a(SignImm), .y(SignImmShft));


mux21 srcAmux (.a(PC), .b(rd1_reg), .sel(ALUSrcA), .y(srcA)); 


mux41 srcBmux (.a(rd2_reg), .b(32'h4), .c(SignImm), .d(SignImmShft),
                            .sel(ALUSrcB), .y(srcB));


alu alu1 (.srcA(srcA), .srcB(srcB), .ALUCtrl(ALUCtrl), .ALUResult(ALUResult), .Z(Z));


reset_ff aluRes_reg (.clk(clk), .reset(reset), .d(ALUResult), .q(ALUOut));


mux41 resmux (.a(ALUResult), .b(ALUOut), .c({PC[31:28], Instr[25:0], 2'b00}), .d(),.sel(PCSrc), .y(PCNext));

endmodule