data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v
1: b"%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:121: Cannot find file containing module: 'ControlUnit'\n    ControlUnit controlUnit(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore,data/full_repos/permissive/423012938/ControlUnit\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore,data/full_repos/permissive/423012938/ControlUnit.v\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore,data/full_repos/permissive/423012938/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:129: Cannot find file containing module: 'ProgramCounter'\n    ProgramCounter programCounter(nextPc, clk, pcStall, pc);\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:130: Cannot find file containing module: 'HardInstructionMemory'\n    HardInstructionMemory hardInstructionMemory(pc, imOut);\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:131: Cannot find file containing module: 'Gp2to1Mux'\n    Gp2to1Mux #(32) instMux (imOut, nop, instNop, inst);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:132: Cannot find file containing module: 'GpAdder'\n    GpAdder #(64) pcAdder (64'h4, pc, pc4);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:133: Cannot find file containing module: 'Gp2to1Mux'\n    Gp2to1Mux #(64) pcSelMux (pc4, alur, pcSel, nextPc);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:136: Cannot find file containing module: 'PipelineRegIFID'\n    PipelineRegIFID pipelineRegIFID (pc, inst, clk, ifidStall, dpc, dinst);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:137: Cannot find file containing module: 'RegisterFile'\n    RegisterFile registerFile (rs1, rs2, wrd, wbData, wwreg, clk, rqa, rqb);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:138: Cannot find file containing module: 'ImmediateDecoder'\n    ImmediateDecoder immediateDecoder (dinst[31:7], immType, imm64);\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:139: Cannot find file containing module: 'Gp4to1Mux'\n    Gp4to1Mux #(64) fwdaMux (rqa, er, mr, md, qaSel, qa);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:140: Cannot find file containing module: 'Gp4to1Mux'\n    Gp4to1Mux #(64) fwdbMux (rqb, er, mr, md, qbSel, qb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:143: Cannot find file containing module: 'PipelineRegIDEXE'\n    PipelineRegIDEXE pipelineRegIDEXE (\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:149: Cannot find file containing module: 'Gp2to1Mux'\n    Gp2to1Mux #(64) exeAMux (eqa, epc, eaSel, ea);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:150: Cannot find file containing module: 'Gp2to1Mux'\n    Gp2to1Mux #(64) exeBMux (eqb, eimm64, ebSel, eb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:151: Cannot find file containing module: 'ALU'\n    ALU alu (ea, eb, ealuc, alur);\n    ^~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:152: Cannot find file containing module: 'Comparator'\n    Comparator comparator (eqa, eqb, esignedComp, eq, lt);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:153: Cannot find file containing module: 'GpAdder'\n    GpAdder #(64) jalAdder (64'h4, epc, epc4);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:154: Cannot find file containing module: 'Gp4to1Mux'\n    Gp4to1Mux #(64) exeRMux (alur, {63'h0, lt}, epc4, epc4, erSel, er);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:157: Cannot find file containing module: 'PipelineRegEXEMEM'\n    PipelineRegEXEMEM pipelineRegEXEMEM (\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:161: Cannot find file containing module: 'DataMemoryMapper'\n    DataMemoryMapper dataMemoryMapper (mr, mqb, mwmem, mfunct3, clk, md);\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:164: Cannot find file containing module: 'PipelineRegMEMWB'\n    PipelineRegMEMWB pipelineRegMEMWB (\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/CoreDatapath.v:168: Cannot find file containing module: 'Gp2to1Mux'\n    Gp2to1Mux #(64) wbMux (wr, wd, wm2reg, wbData);\n    ^~~~~~~~~\n%Error: Exiting due to 22 error(s)\n"
module CoreDatapath(
    input clk


);
    


    wire        pcSel;
    wire        pcStall;
    wire [63:0] pc;
    wire [63:0] nextPc;
    wire [63:0] pc4;
    
    wire [31:0] imOut;
    wire [31:0] inst;
    wire [31:0] nop;
    wire        instNop;

    assign nop = 32'b10011;



    wire [31:0] dinst;
    wire [63:0] dpc;
    wire        ifidStall;
    wire [4:0]  rs1;
    wire [4:0]  rs2;
    wire [4:0]  rd;
    wire [2:0]  funct3;
    wire [6:0]  funct7;
    wire [6:0]  opcode;
    wire [63:0] rqa;
    wire [63:0] rqb;
    wire [63:0] qa;
    wire [63:0] qb;
    wire [63:0] imm64;
    wire [63:0] jalpc;

    assign rs1    = dinst[19:15];
    assign rs2    = dinst[24:20];
    assign rd     = dinst[11:7];
    assign funct3 = dinst[14:12];
    assign funct7 = dinst[31:25];
    assign opcode = dinst[6:0];


    wire [2:0]  immType;
    wire [1:0]  qaSel;
    wire [1:0]  qbSel;
    wire        isJal;
    wire        signedComp;
    wire        aSel;
    wire        bSel;
    wire [3:0]  aluc;
    wire [1:0]  rSel;
    wire        wmem;
    wire        m2reg;
    wire        wreg;
    wire [2:0]  bType;



    wire [4:0]  erd;
    wire [63:0] epc;
    wire [63:0] eqa;
    wire        esignedComp;
    wire [63:0] eqb;
    wire [63:0] eimm64;
    wire        eaSel;
    wire        ebSel;
    wire [3:0]  ealuc;
    wire [1:0]  erSel;
    wire        ewmem;
    wire [2:0]  efunct3;
    wire        em2reg;
    wire        ewreg;
    wire [2:0]  ebType;
    wire        eisJal;


    wire [63:0] ea;
    wire [63:0] eb;
    wire [63:0] epc4;
    wire [63:0] alur;
    wire        lt;
    wire        eq;
    wire [63:0] er;



    wire [4:0]  mrd;
    wire [63:0] mr;
    wire [63:0] mqb;
    wire        mwmem;
    wire [2:0]  mfunct3;
    wire        mm2reg;
    wire        mwreg;
    wire [63:0] md;



    wire [4:0]  wrd;
    wire [63:0] wr;
    wire [63:0] wd;
    wire        wm2reg;
    wire        wwreg;
    wire [63:0] wbData;


    ControlUnit controlUnit(
        funct7, rs2, rs1, funct3, opcode, eq, lt, erd, mrd, rd, ewreg, mwreg,
        em2reg, mm2reg, ebType, eisJal,
        aSel, bSel, aluc, rSel, wmem, m2reg, wreg, immType, bType, isJal,
        signedComp, qaSel, qbSel, pcSel, pcStall, ifidStall, instNop
    );


    ProgramCounter programCounter(nextPc, clk, pcStall, pc);
    HardInstructionMemory hardInstructionMemory(pc, imOut);
    Gp2to1Mux #(32) instMux (imOut, nop, instNop, inst);
    GpAdder #(64) pcAdder (64'h4, pc, pc4);
    Gp2to1Mux #(64) pcSelMux (pc4, alur, pcSel, nextPc);


    PipelineRegIFID pipelineRegIFID (pc, inst, clk, ifidStall, dpc, dinst);
    RegisterFile registerFile (rs1, rs2, wrd, wbData, wwreg, clk, rqa, rqb);
    ImmediateDecoder immediateDecoder (dinst[31:7], immType, imm64);
    Gp4to1Mux #(64) fwdaMux (rqa, er, mr, md, qaSel, qa);
    Gp4to1Mux #(64) fwdbMux (rqb, er, mr, md, qbSel, qb);


    PipelineRegIDEXE pipelineRegIDEXE (
        rd, dpc, qa, qb, imm64, signedComp, funct3, aSel, bSel, aluc, rSel,
        wmem, m2reg, wreg, bType, isJal, clk,
        erd, epc, eqa, eqb, eimm64, esignedComp, efunct3, eaSel, ebSel, ealuc,
        erSel, ewmem, em2reg, ewreg, ebType, eisJal
    );
    Gp2to1Mux #(64) exeAMux (eqa, epc, eaSel, ea);
    Gp2to1Mux #(64) exeBMux (eqb, eimm64, ebSel, eb);
    ALU alu (ea, eb, ealuc, alur);
    Comparator comparator (eqa, eqb, esignedComp, eq, lt);
    GpAdder #(64) jalAdder (64'h4, epc, epc4);
    Gp4to1Mux #(64) exeRMux (alur, {63'h0, lt}, epc4, epc4, erSel, er);


    PipelineRegEXEMEM pipelineRegEXEMEM (
        erd, er, eqb, ewmem, efunct3, em2reg, ewreg, clk,
        mrd, mr, mqb, mwmem, mfunct3, mm2reg, mwreg
    );
    DataMemoryMapper dataMemoryMapper (mr, mqb, mwmem, mfunct3, clk, md);


    PipelineRegMEMWB pipelineRegMEMWB (
        mrd, mr, md, mm2reg, mwreg, clk,
        wrd, wr, wd, wm2reg, wwreg
    );
    Gp2to1Mux #(64) wbMux (wr, wd, wm2reg, wbData);

endmodule
module CoreDatapath(
    input clk


);

    


    wire        pcSel;
    wire        pcStall;
    wire [63:0] pc;
    wire [63:0] nextPc;
    wire [63:0] pc4;
    
    wire [31:0] imOut;
    wire [31:0] inst;
    wire [31:0] nop;
    wire        instNop;

    assign nop = 32'b10011;



    wire [31:0] dinst;
    wire [63:0] dpc;
    wire        ifidStall;
    wire [4:0]  rs1;
    wire [4:0]  rs2;
    wire [4:0]  rd;
    wire [2:0]  funct3;
    wire [6:0]  funct7;
    wire [6:0]  opcode;
    wire [63:0] rqa;
    wire [63:0] rqb;
    wire [63:0] qa;
    wire [63:0] qb;
    wire [63:0] imm64;
    wire [63:0] jalpc;

    assign rs1    = dinst[19:15];
    assign rs2    = dinst[24:20];
    assign rd     = dinst[11:7];
    assign funct3 = dinst[14:12];
    assign funct7 = dinst[31:25];
    assign opcode = dinst[6:0];


    wire [2:0]  immType;
    wire [1:0]  qaSel;
    wire [1:0]  qbSel;
    wire        isJal;
    wire        signedComp;
    wire        aSel;
    wire        bSel;
    wire [3:0]  aluc;
    wire [1:0]  rSel;
    wire        wmem;
    wire        m2reg;
    wire        wreg;
    wire [2:0]  bType;



    wire [4:0]  erd;
    wire [63:0] epc;
    wire [63:0] eqa;
    wire        esignedComp;
    wire [63:0] eqb;
    wire [63:0] eimm64;
    wire        eaSel;
    wire        ebSel;
    wire [3:0]  ealuc;
    wire [1:0]  erSel;
    wire        ewmem;
    wire [2:0]  efunct3;
    wire        em2reg;
    wire        ewreg;
    wire [2:0]  ebType;
    wire        eisJal;


    wire [63:0] ea;
    wire [63:0] eb;
    wire [63:0] epc4;
    wire [63:0] alur;
    wire        lt;
    wire        eq;
    wire [63:0] er;



    wire [4:0]  mrd;
    wire [63:0] mr;
    wire [63:0] mqb;
    wire        mwmem;
    wire [2:0]  mfunct3;
    wire        mm2reg;
    wire        mwreg;
    wire [63:0] md;



    wire [4:0]  wrd;
    wire [63:0] wr;
    wire [63:0] wd;
    wire        wm2reg;
    wire        wwreg;
    wire [63:0] wbData;


    ControlUnit controlUnit(
        funct7, rs2, rs1, funct3, opcode, eq, lt, erd, mrd, rd, ewreg, mwreg,
        em2reg, mm2reg, ebType, eisJal,
        aSel, bSel, aluc, rSel, wmem, m2reg, wreg, immType, bType, isJal,
        signedComp, qaSel, qbSel, pcSel, pcStall, ifidStall, instNop
    );


    ProgramCounter programCounter(nextPc, clk, pcStall, pc);
    HardInstructionMemory hardInstructionMemory(pc, imOut);
    Gp2to1Mux #(32) instMux (imOut, nop, instNop, inst);
    GpAdder #(64) pcAdder (64'h4, pc, pc4);
    Gp2to1Mux #(64) pcSelMux (pc4, alur, pcSel, nextPc);


    PipelineRegIFID pipelineRegIFID (pc, inst, clk, ifidStall, dpc, dinst);
    RegisterFile registerFile (rs1, rs2, wrd, wbData, wwreg, clk, rqa, rqb);
    ImmediateDecoder immediateDecoder (dinst[31:7], immType, imm64);
    Gp4to1Mux #(64) fwdaMux (rqa, er, mr, md, qaSel, qa);
    Gp4to1Mux #(64) fwdbMux (rqb, er, mr, md, qbSel, qb);


    PipelineRegIDEXE pipelineRegIDEXE (
        rd, dpc, qa, qb, imm64, signedComp, funct3, aSel, bSel, aluc, rSel,
        wmem, m2reg, wreg, bType, isJal, clk,
        erd, epc, eqa, eqb, eimm64, esignedComp, efunct3, eaSel, ebSel, ealuc,
        erSel, ewmem, em2reg, ewreg, ebType, eisJal
    );
    Gp2to1Mux #(64) exeAMux (eqa, epc, eaSel, ea);
    Gp2to1Mux #(64) exeBMux (eqb, eimm64, ebSel, eb);
    ALU alu (ea, eb, ealuc, alur);
    Comparator comparator (eqa, eqb, esignedComp, eq, lt);
    GpAdder #(64) jalAdder (64'h4, epc, epc4);
    Gp4to1Mux #(64) exeRMux (alur, {63'h0, lt}, epc4, epc4, erSel, er);


    PipelineRegEXEMEM pipelineRegEXEMEM (
        erd, er, eqb, ewmem, efunct3, em2reg, ewreg, clk,
        mrd, mr, mqb, mwmem, mfunct3, mm2reg, mwreg
    );
    DataMemoryMapper dataMemoryMapper (mr, mqb, mwmem, mfunct3, clk, md);


    PipelineRegMEMWB pipelineRegMEMWB (
        mrd, mr, md, mm2reg, mwreg, clk,
        wrd, wr, wd, wm2reg, wwreg
    );
    Gp2to1Mux #(64) wbMux (wr, wd, wm2reg, wbData);

endmodule