data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:30: Unsupported: event data types\nevent reset_enable;\n^~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:31: Unsupported: event data types\nevent terminate_sim;\n^~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:34: Define or directive not defined: \'`outfile\'\n file = $fopen(`outfile);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n file = $fopen(`outfile);\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:40: syntax error, unexpected \'@\'\n@ (terminate_sim)  begin\n^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:43: syntax error, unexpected $fdisplay\n   $fdisplay (file, "Simulation Result : PASSED");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:46: syntax error, unexpected $fdisplay\n   $fdisplay (file, "Simulation Result : FAILED");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:58: syntax error, unexpected \'@\'\n @ (reset_enable);\n ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:62: syntax error, unexpected \'@\'\n @ (negedge clk)\n ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:65: syntax error, unexpected ->\n -> reset_done;\n ^~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:69: syntax error, unexpected ->\n  #10 -> reset_enable;\n      ^~\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 -> reset_enable;\n  ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:75: syntax error, unexpected \'@\'\n   @ (negedge clk);\n   ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:78: syntax error, unexpected ->\n  #5 -> terminate_sim;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #5 -> terminate_sim;\n  ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:97: syntax error, unexpected ->\n  #5 -> terminate_sim;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #5 -> terminate_sim;\n  ^\n%Error: Exiting due to 14 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

integer file;
reg clk = 0, reset = 0, enable = 0;
wire [3:0] count;
reg dut_error = 0;

counter U0 (
.clk    (clk),
.reset  (reset),
.enable (enable),
.count  (count)
);

event reset_enable;
event terminate_sim;

initial
 file = $fopen(`outfile);

always
  #5 clk = !clk;

initial
@ (terminate_sim)  begin
 $fdisplay (file, "Terminating simulation");
 if (dut_error == 0) begin
   $fdisplay (file, "Simulation Result : PASSED");
 end
 else begin
   $fdisplay (file, "Simulation Result : FAILED");
 end
 $fdisplay (file, "###################################################");
 #1 $finish;
end



event reset_done;

initial
forever begin
 @ (reset_enable);
 @ (negedge clk)
 $fdisplay (file, "Applying reset");
   reset = 1;
 @ (negedge clk)
   reset = 0;
 $fdisplay (file, "Came out of Reset");
 -> reset_done;
end

initial begin
  #10 -> reset_enable;
  @ (reset_done);
  @ (negedge clk);
  enable = 1;
  repeat (5)
  begin
   @ (negedge clk);
  end
  enable = 0;
  #5 -> terminate_sim;
end


reg [3:0] count_compare;

always @ (posedge clk)
if (reset == 1'b1)
 count_compare <= 0;
else if ( enable == 1'b1)
 count_compare <= count_compare + 1;



always @ (negedge clk)
if (count_compare != count) begin
  $fdisplay (file, "DUT ERROR AT TIME%d",$time);
  $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);
  dut_error = 1;
  #5 -> terminate_sim;
end

endmodule
module testbench;


integer file;
reg clk = 0, reset = 0, enable = 0;
wire [3:0] count;
reg dut_error = 0;

counter U0 (
.clk    (clk),
.reset  (reset),
.enable (enable),
.count  (count)
);

event reset_enable;
event terminate_sim;

initial
 file = $fopen(`outfile);

always
  #5 clk = !clk;

initial
@ (terminate_sim)  begin
 $fdisplay (file, "Terminating simulation");
 if (dut_error == 0) begin
   $fdisplay (file, "Simulation Result : PASSED");
 end
 else begin
   $fdisplay (file, "Simulation Result : FAILED");
 end
 $fdisplay (file, "###################################################");
 #1 $finish;
end



event reset_done;

initial
forever begin
 @ (reset_enable);
 @ (negedge clk)
 $fdisplay (file, "Applying reset");
   reset = 1;
 @ (negedge clk)
   reset = 0;
 $fdisplay (file, "Came out of Reset");
 -> reset_done;
end

initial begin
  #10 -> reset_enable;
  @ (reset_done);
  @ (negedge clk);
  enable = 1;
  repeat (5)
  begin
   @ (negedge clk);
  end
  enable = 0;
  #5 -> terminate_sim;
end


reg [3:0] count_compare;

always @ (posedge clk)
if (reset == 1'b1)
 count_compare <= 0;
else if ( enable == 1'b1)
 count_compare <= count_compare + 1;



always @ (negedge clk)
if (count_compare != count) begin
  $fdisplay (file, "DUT ERROR AT TIME%d",$time);
  $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);
  dut_error = 1;
  #5 -> terminate_sim;
end

endmodule