data/full_repos/permissive/488739248/rtl/POR.v
data/verilator_xmls/18083c52-1732-4380-9561-4db18b956316.xml
module POR(
      input reset_a,
      input clk,    
      output reset_s
);
 reg q0,q1,q2;
 
always@(posedge clk, negedge reset_a)
begin
 if (!reset_a) 
 begin
     q0 <= 1'b0;
     q1 <= 1'b0;
     q2 <= 1'b0;
 end    
 else 
 begin
     q0 <= reset_a;
     q1 <= q0;
     q2 <= q1;
 end    
end

assign reset_s = !(q0 & q1 & q2);
endmodule
module POR(
      input reset_a,
      input clk,    
      output reset_s
);

 reg q0,q1,q2;
 
always@(posedge clk, negedge reset_a)
begin
 if (!reset_a) 
 begin
     q0 <= 1'b0;
     q1 <= 1'b0;
     q2 <= 1'b0;
 end    
 else 
 begin
     q0 <= reset_a;
     q1 <= q0;
     q2 <= q1;
 end    
end

assign reset_s = !(q0 & q1 & q2);
endmodule