data/full_repos/permissive/529706848/verilog/tb_core.v
1: b'%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:27: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:32: syntax error, unexpected \'@\'\n    repeat(5) @(posedge clock);\n              ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:34: syntax error, unexpected \'@\'\n    repeat(5) @(posedge clock);\n              ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:37: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:40: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:43: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:47: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:51: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:55: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/529706848/verilog/tb_core.v:59: syntax error, unexpected \'@\'\n    @(posedge clock);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_core.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10 clock = ~clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 10 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_core();

reg clock;
reg reset;
reg [2:0] sym;
reg sym_valid;

wire [2:0] new_sym;
wire direction;
wire [2:0] encoded_next_state;

utm_core_PROJECT_ID core(
    .clock(clock),
    .reset(reset),
    .mode(1'b1),
    .encoded_state_in(3'b0),
    .sym_in(sym),
    .sym_in_valid(sym_valid),
    .new_sym(new_sym),
    .direction(direction),
    .encoded_next_state(encoded_next_state)
);

initial begin
    $dumpvars;
    clock = 0;
    reset = 1;
    sym_valid = 0;
    sym = 3'b001;
    repeat(5) @(posedge clock);
    reset = 0;
    repeat(5) @(posedge clock);
    @(negedge clock);
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;
    repeat(10) @(posedge clock);
    @(negedge clock);
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    repeat(10) @(posedge clock);
    @(negedge clock);
    sym = 3'b010;
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    repeat(10) @(posedge clock);
    @(negedge clock);
    sym = 3'b010;
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    $finish;
end

always begin
    #10 clock = ~clock;
end

endmodule
module tb_core();


reg clock;
reg reset;
reg [2:0] sym;
reg sym_valid;

wire [2:0] new_sym;
wire direction;
wire [2:0] encoded_next_state;

utm_core_PROJECT_ID core(
    .clock(clock),
    .reset(reset),
    .mode(1'b1),
    .encoded_state_in(3'b0),
    .sym_in(sym),
    .sym_in_valid(sym_valid),
    .new_sym(new_sym),
    .direction(direction),
    .encoded_next_state(encoded_next_state)
);

initial begin
    $dumpvars;
    clock = 0;
    reset = 1;
    sym_valid = 0;
    sym = 3'b001;
    repeat(5) @(posedge clock);
    reset = 0;
    repeat(5) @(posedge clock);
    @(negedge clock);
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;
    repeat(10) @(posedge clock);
    @(negedge clock);
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    repeat(10) @(posedge clock);
    @(negedge clock);
    sym = 3'b010;
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    repeat(10) @(posedge clock);
    @(negedge clock);
    sym = 3'b010;
    sym_valid = 1;
    @(posedge clock);
    @(negedge clock);
    sym_valid = 0;

    $finish;
end

always begin
    #10 clock = ~clock;
end

endmodule