data/full_repos/permissive/408955603/Sesion9/biestableTHold.v
data/verilator_xmls/e9703a80-c3af-438f-a45c-76497bae6a7d.xml
module Thold(output wire Q, output wire nQ, input wire T, input wire nPRESET, input wire nCLEAR, input wire nHOLD);
	wire a1s, a2s, o1s, o2s;

	T t1(Q, nQ, T, a2s, a1s);

	or(o1s, nHOLD, Q);
	or(o2s, nHOLD, nQ);
	and(a1s, o1s, nCLEAR);
	and(a2s, o2s, nPRESET);
endmodule
module Thold(output wire Q, output wire nQ, input wire T, input wire nPRESET, input wire nCLEAR, input wire nHOLD);

	wire a1s, a2s, o1s, o2s;

	T t1(Q, nQ, T, a2s, a1s);

	or(o1s, nHOLD, Q);
	or(o2s, nHOLD, nQ);
	and(a1s, o1s, nCLEAR);
	and(a2s, o2s, nPRESET);
endmodule