data/full_repos/permissive/511241767/barrel_shifter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/511241767/barrel_shifter.v:352: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                         : ... In instance barrel_shifter.cl\n    assign a2 = {a[4],a[3],a[2],a[0],a[7],a[6],a[5]};\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux21(a,b,s,o);
    input a,b,s;
    output reg o;
    always@(*)
    begin
        o = (a&~s) | (b&s);
    end
endmodule
module mux21(a,b,s,o);

    input a,b,s;
    output reg o;
    always@(*)
    begin
        o = (a&~s) | (b&s);
    end
endmodule