data/full_repos/permissive/485189979/ledBlink/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/485189979/ledBlink/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #2.5 clk = ~clk;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/485189979/ledBlink/testbench.v:11: Cannot find file containing module: \'clock_divider\'\n clock_divider uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485189979/ledBlink,data/full_repos/permissive/485189979/clock_divider\n             data/full_repos/permissive/485189979/ledBlink,data/full_repos/permissive/485189979/clock_divider.v\n             data/full_repos/permissive/485189979/ledBlink,data/full_repos/permissive/485189979/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


	reg clk = 0;
  
  wire divided_clk;


	clock_divider uut (
		.clk(clk),
    .divided_clk(divided_clk)
	);

	always #2.5 clk = ~clk;
  
  
      
endmodule
module testbench;



	reg clk = 0;
  
  wire divided_clk;


	clock_divider uut (
		.clk(clk),
    .divided_clk(divided_clk)
	);

	always #2.5 clk = ~clk;
  
  
      
endmodule