data/full_repos/permissive/420518472/src/uart_comm.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/420518472/src/uart_comm.v:158: Signal definition not found, creating implicitly: \'is_receive_timeout\'\n                                                                           : ... Suggested alternative: \'is_receiving_timeout\'\n    else if (is_receive_timeout) begin  \n             ^~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:74: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                       : ... In instance uart_comm\n reg [3:0] state = STATE_IDLE;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/420518472/src/uart_comm.v:81: Cannot find file containing module: \'uart\'\n uart #(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/uart\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/uart.v\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:101: Operator EQ expects 4 bits on the RHS, but RHS\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n wire crc_reset = (state == STATE_IDLE);\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:102: Operator EQ expects 4 bits on the RHS, but RHS\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n wire crc_received = received & (state == STATE_IDLE || state == STATE_READ);  \n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:102: Operator EQ expects 4 bits on the RHS, but RHS\'s VARREF \'STATE_READ\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n wire crc_received = received & (state == STATE_IDLE || state == STATE_READ);  \n                                                              ^~\n%Error: data/full_repos/permissive/420518472/src/uart_comm.v:105: Cannot find file containing module: \'CRC32\'\n CRC32 crc_calc (\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:132: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_READ\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n      state <= STATE_READ;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:155: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_PARSE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n      state <= STATE_PARSE;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:163: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n     state <= STATE_IDLE;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:174: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n     state <= STATE_IDLE;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:188: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'msg_length\' generates 8 bits.\n                                                                        : ... In instance uart_comm\n     else if (msg_type == MSG_PUSH_JOB && msg_length == (JOB_SIZE/8 + 8))  \n                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:114: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE_IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n        case (state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:114: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE_READ\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n        case (state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/420518472/src/uart_comm.v:114: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE_PARSE\' generates 3 bits.\n                                                                        : ... In instance uart_comm\n        case (state)\n        ^~~~\n%Error: Exiting due to 2 error(s), 13 warning(s)\n'
module uart_comm (
	input wire comm_clk,
	input wire hash_clk,
	input wire rx_serial,
	input wire [31:0] golden_nonce,
	input wire new_golden_nonce,
	output wire tx_serial,
    output wire error_led,
    output wire status_led1,
    output wire status_led2,
    output wire status_led3,
    output wire status_led4,
	output reg [95:0] work_data = 96'd0,
	output reg [31:0] nonce_min = 32'd0,
	output reg [31:0] nonce_max = 32'd0,
	output reg [255:0] midstate = 256'd0,
	output reg new_work = 1'b0
);

	localparam STATE_IDLE = 3'b001;
	localparam STATE_READ = 3'b010;
	localparam STATE_PARSE = 3'b100;


	localparam MSG_BUF_LEN = 60;


	localparam MSG_INFO = 0;
	localparam MSG_INVALID = 1;
	localparam MSG_PUSH_JOB = 2;
	localparam MSG_NONCE = 3;
	localparam MSG_ACK = 4;
	localparam MSG_RESEND = 5;


	localparam JOB_SIZE = 256 + 96 + 32 + 32;

	reg [JOB_SIZE-1:0] current_job = {JOB_SIZE{1'b0}};
	reg new_work_flag = 1'b0;

	reg [63:0] system_info = 64'hDEADBEEF13370D13;

	wire reset = 0;
	reg transmit;
    reg transmit_packet;
	reg [7:0] tx_byte;
	wire received;
	wire [7:0] rx_byte;
	wire is_receiving;
	wire is_receiving_timeout;
	wire is_transmitting;
	wire recv_error;


	reg [63:0] outgoing_msg;
	reg [7:0] outgoing_msg_type;
	reg [MSG_BUF_LEN*8-1:0] msg_data;
	reg [7:0] msg_length;
    reg [7:0] length;
    reg [7:0] msg_type;
	reg [3:0] state = STATE_IDLE;

	assign error_led = recv_error;

    parameter baud_rate = 9600;
    parameter sys_clk_freq = 12000000;
	
	uart #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq)
	)
	uart0(
		.clk(comm_clk),
		.rst(reset),
		.rx(rx_serial),
		.tx(tx_serial),
		.transmit(transmit),
		.tx_byte(tx_byte),
		.received(received),
		.rx_byte(rx_byte),
		.is_receiving(is_receiving),
		.is_transmitting(is_transmitting),
		.recv_error(recv_error),
		.is_receive_timeout(is_receive_timeout)
	);


	wire crc_reset = (state == STATE_IDLE);
	wire crc_received = received & (state == STATE_IDLE || state == STATE_READ);
	wire [31:0] crc;

	CRC32 crc_calc (
		.clk (comm_clk),
		.reset (crc_reset),
		.received (crc_received),
		.rx_byte (rx_byte),
		.tx_crc (crc)
	);

	always @(posedge comm_clk) begin
        case (state)

			STATE_IDLE: begin
				if (received) begin
					if (rx_byte == 0) begin
						length <= 8'd1;
						msg_length <= 8'h1;
						transmit_packet <= 1;
					end
					else if (rx_byte < 8) begin
						length <= 8'd1;
						msg_length <= 8'h8;
						msg_type <= MSG_INVALID;
						transmit_packet <= 1;
					end
					else begin
						length <= 8'd2;
						msg_length <= rx_byte;
						state <= STATE_READ;
					end
				end
				else if (meta_new_golden_nonce) begin
					length <= 8'd1;
					msg_length <= 8'd8;
					msg_data[(MSG_BUF_LEN*8)-1:(MSG_BUF_LEN*8)-1-31] <= meta_golden_nonce;
					transmit_packet <= 1;
					msg_type <= MSG_NONCE;
				end
			end


			STATE_READ: begin
				if (received) begin
					msg_data <= {rx_byte, msg_data[MSG_BUF_LEN*8-1:8]};
					length <= length + 8'd1;

					if (length == 8'd4) begin
						msg_type <= rx_byte;
					end

					if (length == msg_length) begin
						state <= STATE_PARSE;
					end
				end
				else if (is_receive_timeout) begin
					length <= 8'd1;
					msg_length <= 8'd8;
					msg_type <= MSG_INVALID;
					transmit_packet <= 1;
					state <= STATE_IDLE;
				end
			end


			STATE_PARSE: begin
				if (!transmit_packet) begin


					length <= 8'd1;
					msg_length <= 8'd8;
					state <= STATE_IDLE;
					transmit_packet <= 1;

					if (crc != 32'd0) begin
						`ifdef SIM
						$display("CRC is incorrect: %8h", crc);
						`endif
						msg_type <= MSG_RESEND;
					end
					else if (msg_type == MSG_INFO && msg_length == 8) begin
						msg_type <= MSG_INFO;
						msg_data[(MSG_BUF_LEN*8)-1:(MSG_BUF_LEN*8)-1-63] <= system_info;
						msg_length <= 8'd16;
					end
					else if (msg_type == MSG_PUSH_JOB && msg_length == (JOB_SIZE/8 + 8))
					begin
						current_job <= msg_data[8*4 +: JOB_SIZE];
						new_work_flag <= ~new_work_flag;

						msg_type <= MSG_ACK;
						msg_length <= 8'd1;
					end
					else begin
						`ifdef SIM
						$display("Invalid command received!");
						`endif
						msg_type <= MSG_INVALID;
					end
				end
			end
        endcase



        transmit <= 1'b0;  
        if (transmit_packet && !is_transmitting) begin
            transmit <= 1'b1;
            length <= length + 8'd1;

            if (length == 8'd1)
                tx_byte <= msg_length;
            else if (length == 8'd2 || length == 8'd3)
                tx_byte <= 8'h00;
            else if (length == 8'd4)
                tx_byte <= msg_type;
            else if (length <= msg_length)
            begin
                tx_byte <= msg_data[((MSG_BUF_LEN*8)-1):((MSG_BUF_LEN-1)*8)]; 
				msg_data <= msg_data << 8;
            end

            if (length == msg_length)
                transmit_packet <= 0;
        end
    end



	reg [JOB_SIZE-1:0] meta_job;
	reg [2:0] meta_new_work_flag = 3'd0;


	reg [2:0] meta_golden_nonce_flag = 3'd0;
	reg meta_new_golden_nonce = 1'd0;
	reg [31:0] meta_golden_nonce = 32'd0;

	always @ (posedge hash_clk) begin
		meta_job <= current_job;
		meta_new_work_flag <= {new_work_flag, meta_new_work_flag[2:1]};
		new_work <= meta_new_work_flag[1] ^ meta_new_work_flag[0] || meta_new_work_flag[2] ^ meta_new_work_flag[1];
		{midstate, work_data, nonce_min, nonce_max} <= meta_job;

		meta_golden_nonce_flag <= {new_golden_nonce, meta_golden_nonce_flag[2:1]};
		if (meta_golden_nonce_flag[1] ^ meta_golden_nonce_flag[0]) begin
			meta_new_golden_nonce <= 1'b1;
		end

		if (new_golden_nonce) begin
			meta_golden_nonce <= golden_nonce;
		end

		if (msg_type == MSG_NONCE) begin
			meta_new_golden_nonce <= 0;
		end
	end
endmodule
module uart_comm (
	input wire comm_clk,
	input wire hash_clk,
	input wire rx_serial,
	input wire [31:0] golden_nonce,
	input wire new_golden_nonce,
	output wire tx_serial,
    output wire error_led,
    output wire status_led1,
    output wire status_led2,
    output wire status_led3,
    output wire status_led4,
	output reg [95:0] work_data = 96'd0,
	output reg [31:0] nonce_min = 32'd0,
	output reg [31:0] nonce_max = 32'd0,
	output reg [255:0] midstate = 256'd0,
	output reg new_work = 1'b0
);


	localparam STATE_IDLE = 3'b001;
	localparam STATE_READ = 3'b010;
	localparam STATE_PARSE = 3'b100;


	localparam MSG_BUF_LEN = 60;


	localparam MSG_INFO = 0;
	localparam MSG_INVALID = 1;
	localparam MSG_PUSH_JOB = 2;
	localparam MSG_NONCE = 3;
	localparam MSG_ACK = 4;
	localparam MSG_RESEND = 5;


	localparam JOB_SIZE = 256 + 96 + 32 + 32;

	reg [JOB_SIZE-1:0] current_job = {JOB_SIZE{1'b0}};
	reg new_work_flag = 1'b0;

	reg [63:0] system_info = 64'hDEADBEEF13370D13;

	wire reset = 0;
	reg transmit;
    reg transmit_packet;
	reg [7:0] tx_byte;
	wire received;
	wire [7:0] rx_byte;
	wire is_receiving;
	wire is_receiving_timeout;
	wire is_transmitting;
	wire recv_error;


	reg [63:0] outgoing_msg;
	reg [7:0] outgoing_msg_type;
	reg [MSG_BUF_LEN*8-1:0] msg_data;
	reg [7:0] msg_length;
    reg [7:0] length;
    reg [7:0] msg_type;
	reg [3:0] state = STATE_IDLE;

	assign error_led = recv_error;

    parameter baud_rate = 9600;
    parameter sys_clk_freq = 12000000;
	
	uart #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq)
	)
	uart0(
		.clk(comm_clk),
		.rst(reset),
		.rx(rx_serial),
		.tx(tx_serial),
		.transmit(transmit),
		.tx_byte(tx_byte),
		.received(received),
		.rx_byte(rx_byte),
		.is_receiving(is_receiving),
		.is_transmitting(is_transmitting),
		.recv_error(recv_error),
		.is_receive_timeout(is_receive_timeout)
	);


	wire crc_reset = (state == STATE_IDLE);
	wire crc_received = received & (state == STATE_IDLE || state == STATE_READ);
	wire [31:0] crc;

	CRC32 crc_calc (
		.clk (comm_clk),
		.reset (crc_reset),
		.received (crc_received),
		.rx_byte (rx_byte),
		.tx_crc (crc)
	);

	always @(posedge comm_clk) begin
        case (state)

			STATE_IDLE: begin
				if (received) begin
					if (rx_byte == 0) begin
						length <= 8'd1;
						msg_length <= 8'h1;
						transmit_packet <= 1;
					end
					else if (rx_byte < 8) begin
						length <= 8'd1;
						msg_length <= 8'h8;
						msg_type <= MSG_INVALID;
						transmit_packet <= 1;
					end
					else begin
						length <= 8'd2;
						msg_length <= rx_byte;
						state <= STATE_READ;
					end
				end
				else if (meta_new_golden_nonce) begin
					length <= 8'd1;
					msg_length <= 8'd8;
					msg_data[(MSG_BUF_LEN*8)-1:(MSG_BUF_LEN*8)-1-31] <= meta_golden_nonce;
					transmit_packet <= 1;
					msg_type <= MSG_NONCE;
				end
			end


			STATE_READ: begin
				if (received) begin
					msg_data <= {rx_byte, msg_data[MSG_BUF_LEN*8-1:8]};
					length <= length + 8'd1;

					if (length == 8'd4) begin
						msg_type <= rx_byte;
					end

					if (length == msg_length) begin
						state <= STATE_PARSE;
					end
				end
				else if (is_receive_timeout) begin
					length <= 8'd1;
					msg_length <= 8'd8;
					msg_type <= MSG_INVALID;
					transmit_packet <= 1;
					state <= STATE_IDLE;
				end
			end


			STATE_PARSE: begin
				if (!transmit_packet) begin


					length <= 8'd1;
					msg_length <= 8'd8;
					state <= STATE_IDLE;
					transmit_packet <= 1;

					if (crc != 32'd0) begin
						`ifdef SIM
						$display("CRC is incorrect: %8h", crc);
						`endif
						msg_type <= MSG_RESEND;
					end
					else if (msg_type == MSG_INFO && msg_length == 8) begin
						msg_type <= MSG_INFO;
						msg_data[(MSG_BUF_LEN*8)-1:(MSG_BUF_LEN*8)-1-63] <= system_info;
						msg_length <= 8'd16;
					end
					else if (msg_type == MSG_PUSH_JOB && msg_length == (JOB_SIZE/8 + 8))
					begin
						current_job <= msg_data[8*4 +: JOB_SIZE];
						new_work_flag <= ~new_work_flag;

						msg_type <= MSG_ACK;
						msg_length <= 8'd1;
					end
					else begin
						`ifdef SIM
						$display("Invalid command received!");
						`endif
						msg_type <= MSG_INVALID;
					end
				end
			end
        endcase



        transmit <= 1'b0;  
        if (transmit_packet && !is_transmitting) begin
            transmit <= 1'b1;
            length <= length + 8'd1;

            if (length == 8'd1)
                tx_byte <= msg_length;
            else if (length == 8'd2 || length == 8'd3)
                tx_byte <= 8'h00;
            else if (length == 8'd4)
                tx_byte <= msg_type;
            else if (length <= msg_length)
            begin
                tx_byte <= msg_data[((MSG_BUF_LEN*8)-1):((MSG_BUF_LEN-1)*8)]; 
				msg_data <= msg_data << 8;
            end

            if (length == msg_length)
                transmit_packet <= 0;
        end
    end



	reg [JOB_SIZE-1:0] meta_job;
	reg [2:0] meta_new_work_flag = 3'd0;


	reg [2:0] meta_golden_nonce_flag = 3'd0;
	reg meta_new_golden_nonce = 1'd0;
	reg [31:0] meta_golden_nonce = 32'd0;

	always @ (posedge hash_clk) begin
		meta_job <= current_job;
		meta_new_work_flag <= {new_work_flag, meta_new_work_flag[2:1]};
		new_work <= meta_new_work_flag[1] ^ meta_new_work_flag[0] || meta_new_work_flag[2] ^ meta_new_work_flag[1];
		{midstate, work_data, nonce_min, nonce_max} <= meta_job;

		meta_golden_nonce_flag <= {new_golden_nonce, meta_golden_nonce_flag[2:1]};
		if (meta_golden_nonce_flag[1] ^ meta_golden_nonce_flag[0]) begin
			meta_new_golden_nonce <= 1'b1;
		end

		if (new_golden_nonce) begin
			meta_golden_nonce <= golden_nonce;
		end

		if (msg_type == MSG_NONCE) begin
			meta_new_golden_nonce <= 0;
		end
	end
endmodule