data/full_repos/permissive/515186003/univ_shift_reg.v
data/verilator_xmls/f3975291-df1a-4817-9745-d6873736f923.xml
module DFF(
    input D,
    input clk,
    input clr,
    output reg Q
    );
   initial Q=0;
   always@(posedge clk or posedge clr) begin
       if (clr==1)
           begin
           Q=0;
           end
       else if (clr==0)
           begin
           case(D)
                    1'b0:Q=0;
                    1'b1:Q=1;
           endcase
       end   
   end 
endmodule
module DFF(
    input D,
    input clk,
    input clr,
    output reg Q
    );

   initial Q=0;
   always@(posedge clk or posedge clr) begin
       if (clr==1)
           begin
           Q=0;
           end
       else if (clr==0)
           begin
           case(D)
                    1'b0:Q=0;
                    1'b1:Q=1;
           endcase
       end   
   end 
endmodule