data/full_repos/permissive/486216880/ROM.v
data/verilator_xmls/1f9a54e7-f59f-4d03-9676-008e753a1624.xml
module ROM(
    input clk,
    input [31:0] address_i,    
    output [31:0] data_o
);
    reg [31:0] memory [12:0];

    assign data_o = memory[address_i];

    always @(posedge clk) begin
        memory[0] <= 32'h00000013;
        memory[1] <= 32'h00100093;

        memory[2] <= 32'h00100313;
        memory[3] <= 32'h0060A023;
        memory[4] <= 32'h00300313;



        memory[5] <= 32'h0000A303;
        memory[6] <= 32'h00130313;


        memory[7] <= 32'h0060A023;
        memory[8] <= 32'hFEC34FE3;




        memory[9] <= 32'h03700413;
        memory[10] <= 32'h00800433;
        memory[11] <= 32'h00140413;
        memory[12] <= 32'h00000013;
    end
endmodule
module ROM(
    input clk,
    input [31:0] address_i,    
    output [31:0] data_o
);

    reg [31:0] memory [12:0];

    assign data_o = memory[address_i];

    always @(posedge clk) begin
        memory[0] <= 32'h00000013;
        memory[1] <= 32'h00100093;

        memory[2] <= 32'h00100313;
        memory[3] <= 32'h0060A023;
        memory[4] <= 32'h00300313;



        memory[5] <= 32'h0000A303;
        memory[6] <= 32'h00130313;


        memory[7] <= 32'h0060A023;
        memory[8] <= 32'hFEC34FE3;




        memory[9] <= 32'h03700413;
        memory[10] <= 32'h00800433;
        memory[11] <= 32'h00140413;
        memory[12] <= 32'h00000013;
    end
endmodule