data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:23: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1  \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 Load[0]=1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #3 for(j=0;j<=15;j=j+1)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #4 Load[1]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 In=2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:47: Unsupported: Ignoring delay on this delayed statement.\n #6 Load[2]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #6 In=3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:49: Unsupported: Ignoring delay on this delayed statement.\n #7  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #8 Load[3]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:55: Unsupported: Ignoring delay on this delayed statement.\n #8 In=4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:56: Unsupported: Ignoring delay on this delayed statement.\n #9  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 Load[4]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 In=5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:63: Unsupported: Ignoring delay on this delayed statement.\n #11  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:68: Unsupported: Ignoring delay on this delayed statement.\n #12 Load[5]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:69: Unsupported: Ignoring delay on this delayed statement.\n #12 In=6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:70: Unsupported: Ignoring delay on this delayed statement.\n #13  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:75: Unsupported: Ignoring delay on this delayed statement.\n #14 Load[6]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:76: Unsupported: Ignoring delay on this delayed statement.\n #14 In=7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:77: Unsupported: Ignoring delay on this delayed statement.\n #15  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:82: Unsupported: Ignoring delay on this delayed statement.\n #16 Load[7]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:83: Unsupported: Ignoring delay on this delayed statement.\n #16 In=8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:84: Unsupported: Ignoring delay on this delayed statement.\n #17  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:89: Unsupported: Ignoring delay on this delayed statement.\n #18 Load[8]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:90: Unsupported: Ignoring delay on this delayed statement.\n #18 In=9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:91: Unsupported: Ignoring delay on this delayed statement.\n #19  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:96: Unsupported: Ignoring delay on this delayed statement.\n #20 Load[9]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:97: Unsupported: Ignoring delay on this delayed statement.\n #20 In=10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:98: Unsupported: Ignoring delay on this delayed statement.\n #21  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:103: Unsupported: Ignoring delay on this delayed statement.\n #22 Load[10]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:104: Unsupported: Ignoring delay on this delayed statement.\n #22 In=11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:105: Unsupported: Ignoring delay on this delayed statement.\n #23  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:110: Unsupported: Ignoring delay on this delayed statement.\n #24 Load[11]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:111: Unsupported: Ignoring delay on this delayed statement.\n #24 In=12;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:112: Unsupported: Ignoring delay on this delayed statement.\n #25  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:117: Unsupported: Ignoring delay on this delayed statement.\n #26 Load[12]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:118: Unsupported: Ignoring delay on this delayed statement.\n #26 In=13;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:119: Unsupported: Ignoring delay on this delayed statement.\n #27  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:124: Unsupported: Ignoring delay on this delayed statement.\n #28 Load[13]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:125: Unsupported: Ignoring delay on this delayed statement.\n #28 In=14;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:126: Unsupported: Ignoring delay on this delayed statement.\n #29  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:131: Unsupported: Ignoring delay on this delayed statement.\n #30 Load[14]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:132: Unsupported: Ignoring delay on this delayed statement.\n #30 In=15;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:133: Unsupported: Ignoring delay on this delayed statement.\n #31  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:138: Unsupported: Ignoring delay on this delayed statement.\n #32 Load[15]=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:139: Unsupported: Ignoring delay on this delayed statement.\n #32 In=16;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:143: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:145: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:150: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("RegisterTestBench2.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:151: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,RegisterTestBench2);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register/RegisterTestBench2.v:153: Unsupported or unknown PLI call: $monitor\n%Error: Exiting due to 4 error(s), 50 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterTestBench2;

parameter sim_time = 750*2;

reg [31:0] In;
reg Clk,Reset;
reg[15:0] Load;
wire[31:0] Out[15:0];

generate
  genvar i;
  for (i=0; i<=15; i=i+1) begin : registers
    Register test_reg(.IN(In),
				  .Clk(Clk),
				  .Reset(Reset),
				  .Load(Load[i]),
				  .OUT(Out[i]));
  end
endgenerate

integer j=0;

initial fork


	In=0;Reset=1;Clk = 0;
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#1
	In=1;
	#1 Reset=0;
	#1 Load[0]=1;

	#3 for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#4 Load[1]=1;
	#5 In=2;
	#5
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#6 Load[2]=1;
	#6 In=3;
	#7
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#8 Load[3]=1;
	#8 In=4;
	#9
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#10 Load[4]=1;
	#10 In=5;
	#11
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#12 Load[5]=1;
	#12 In=6;
	#13
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#14 Load[6]=1;
	#14 In=7;
	#15
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#16 Load[7]=1;
	#16 In=8;
	#17
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#18 Load[8]=1;
	#18 In=9;
	#19
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#20 Load[9]=1;
	#20 In=10;
	#21
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#22 Load[10]=1;
	#22 In=11;
	#23
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#24 Load[11]=1;
	#24 In=12;
	#25
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#26 Load[12]=1;
	#26 In=13;
	#27
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#28 Load[13]=1;
	#28 In=14;
	#29
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#30 Load[14]=1;
	#30 In=15;
	#31
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#32 Load[15]=1;
	#32 In=16;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench2.vcd");
	$dumpvars(0,RegisterTestBench2);
	$display(" Test Results" );
	$monitor("T = %3d,Clk = %3d,In = %3d,Reset = %3d,Load[0] = %3d,Load[1] = %3d,Load[2] = %3d,Load[3] = %3d,Load[4] = %3d,Load[5] = %3d,Load[6] = %3d,Load[7] = %3d,Load[8] = %3d,Load[9] = %3d,Load[10] = %3d,Load[11] = %3d,Load[12] = %3d,Load[13] = %3d,Load[14] = %3d,Load[15] = %3d,Out[0] = %3d,Out[1] = %3d,Out[2] = %3d,Out[3] = %3d,Out[4] = %3d,Out[5] = %3d,Out[6] = %3d,Out[7] = %3d,Out[8] = %3d,Out[9] = %3d,Out[10] = %3d,Out[11] = %3d,Out[12] = %3d,Out[13] = %3d,Out[14] = %3d,Out[15] = %3d",$time,Clk,In,Reset,Load[0],Load[1],Load[2],Load[3],Load[4],Load[5],Load[6],Load[7],Load[8],Load[9],Load[10],Load[11],Load[12],Load[13],Load[14],Load[15],Out[0],Out[1],Out[2],Out[3],Out[4],Out[5],Out[6],Out[7],Out[8],Out[9],Out[10],Out[11],Out[12],Out[13],Out[14],Out[15]);
end

endmodule
module RegisterTestBench2;


parameter sim_time = 750*2;

reg [31:0] In;
reg Clk,Reset;
reg[15:0] Load;
wire[31:0] Out[15:0];

generate
  genvar i;
  for (i=0; i<=15; i=i+1) begin : registers
    Register test_reg(.IN(In),
				  .Clk(Clk),
				  .Reset(Reset),
				  .Load(Load[i]),
				  .OUT(Out[i]));
  end
endgenerate

integer j=0;

initial fork


	In=0;Reset=1;Clk = 0;
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#1
	In=1;
	#1 Reset=0;
	#1 Load[0]=1;

	#3 for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#4 Load[1]=1;
	#5 In=2;
	#5
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#6 Load[2]=1;
	#6 In=3;
	#7
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#8 Load[3]=1;
	#8 In=4;
	#9
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#10 Load[4]=1;
	#10 In=5;
	#11
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#12 Load[5]=1;
	#12 In=6;
	#13
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#14 Load[6]=1;
	#14 In=7;
	#15
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#16 Load[7]=1;
	#16 In=8;
	#17
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#18 Load[8]=1;
	#18 In=9;
	#19
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#20 Load[9]=1;
	#20 In=10;
	#21
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#22 Load[10]=1;
	#22 In=11;
	#23
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#24 Load[11]=1;
	#24 In=12;
	#25
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#26 Load[12]=1;
	#26 In=13;
	#27
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#28 Load[13]=1;
	#28 In=14;
	#29
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#30 Load[14]=1;
	#30 In=15;
	#31
	for(j=0;j<=15;j=j+1)
	begin
		Load[j]=0;
	end
	#32 Load[15]=1;
	#32 In=16;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench2.vcd");
	$dumpvars(0,RegisterTestBench2);
	$display(" Test Results" );
	$monitor("T = %3d,Clk = %3d,In = %3d,Reset = %3d,Load[0] = %3d,Load[1] = %3d,Load[2] = %3d,Load[3] = %3d,Load[4] = %3d,Load[5] = %3d,Load[6] = %3d,Load[7] = %3d,Load[8] = %3d,Load[9] = %3d,Load[10] = %3d,Load[11] = %3d,Load[12] = %3d,Load[13] = %3d,Load[14] = %3d,Load[15] = %3d,Out[0] = %3d,Out[1] = %3d,Out[2] = %3d,Out[3] = %3d,Out[4] = %3d,Out[5] = %3d,Out[6] = %3d,Out[7] = %3d,Out[8] = %3d,Out[9] = %3d,Out[10] = %3d,Out[11] = %3d,Out[12] = %3d,Out[13] = %3d,Out[14] = %3d,Out[15] = %3d",$time,Clk,In,Reset,Load[0],Load[1],Load[2],Load[3],Load[4],Load[5],Load[6],Load[7],Load[8],Load[9],Load[10],Load[11],Load[12],Load[13],Load[14],Load[15],Out[0],Out[1],Out[2],Out[3],Out[4],Out[5],Out[6],Out[7],Out[8],Out[9],Out[10],Out[11],Out[12],Out[13],Out[14],Out[15]);
end

endmodule