data/full_repos/permissive/486598419/6.7/Counter8.v
data/verilator_xmls/e27f036a-a689-40d8-a165-0360f7dcfb52.xml
module Divider(
    input I_CLK,
    input rst,
    output reg O_CLK=0
    );
    parameter times=100000000;
    reg [31:0] counter=32'b0;    
    always @(posedge I_CLK )
        if(rst)
            begin
            counter = 32'b0;
            O_CLK=1'b0;
            end
        else if(counter<times/2-1)
            begin
            counter = counter+1'b1;
            O_CLK=O_CLK;
            end
        else
            begin
            counter =32'b0;
            O_CLK=~O_CLK;
            end
endmodule
module Divider(
    input I_CLK,
    input rst,
    output reg O_CLK=0
    );

    parameter times=100000000;
    reg [31:0] counter=32'b0;    
    always @(posedge I_CLK )
        if(rst)
            begin
            counter = 32'b0;
            O_CLK=1'b0;
            end
        else if(counter<times/2-1)
            begin
            counter = counter+1'b1;
            O_CLK=O_CLK;
            end
        else
            begin
            counter =32'b0;
            O_CLK=~O_CLK;
            end
endmodule