data/full_repos/permissive/507203156/03-源代码/sift_tb/tf_main_rom.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_main_rom.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_main_rom.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5 clka=~clka;\n ^\n%Error: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_main_rom.v:14: Cannot find file containing module: \'main_ori_rom\'\n main_ori_rom uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/main_ori_rom\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/main_ori_rom.v\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/main_ori_rom.sv\n             main_ori_rom\n             main_ori_rom.v\n             main_ori_rom.sv\n             obj_dir/main_ori_rom\n             obj_dir/main_ori_rom.v\n             obj_dir/main_ori_rom.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_main_rom;


	reg clka;
	reg [6:0] addra;


	wire [5:0] douta;


	main_ori_rom uut (
		.clka(clka), 
		.addra(addra), 
		.douta(douta)
	);

	initial begin

		clka = 0;
		addra = 0;


		#100;
        


	end
	
	always 
	#5 clka=~clka;
	
	always@(posedge clka)
	addra<=addra+1;
      
endmodule
module tf_main_rom;



	reg clka;
	reg [6:0] addra;


	wire [5:0] douta;


	main_ori_rom uut (
		.clka(clka), 
		.addra(addra), 
		.douta(douta)
	);

	initial begin

		clka = 0;
		addra = 0;


		#100;
        


	end
	
	always 
	#5 clka=~clka;
	
	always@(posedge clka)
	addra<=addra+1;
      
endmodule