data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:37: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'example\'\nmodule example (\n       ^~~~~~~\n                                                                                              : ... Top module \'seg7enc\'\nmodule seg7enc (\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:21: Operator ADD expects 32 or 30 bits on the RHS, but RHS\'s VARREF \'SW1\' generates 1 bits.\n                                                                                           : ... In instance example\n  counter <= counter + SW1 + SW2 + 1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:21: Operator ADD expects 32 or 30 bits on the RHS, but RHS\'s VARREF \'SW2\' generates 1 bits.\n                                                                                           : ... In instance example\n  counter <= counter + SW1 + SW2 + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:22: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 30 bits.\n                                                                                           : ... In instance example\n  outcnt <= counter >> LOG2DELAY;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:25: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                                           : ... In instance example\n assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);\n                                 ^\n%Error: Exiting due to 5 warning(s)\n'
module example (
	input  clk,
	input  SW1,
	input  SW2,
	output LED1,
	output LED2,
	output LED3,
	output LED4,

	output AA, AB, AC, AD,
	output AE, AF, AG, CA
);

	localparam BITS = 8;
	localparam LOG2DELAY = 22;

	reg [BITS+LOG2DELAY-1:0] counter = 0;
	reg [BITS-1:0] outcnt;

	always @(posedge clk) begin
		counter <= counter + SW1 + SW2 + 1;
		outcnt <= counter >> LOG2DELAY;
	end

	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);







	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
	assign CA = outcnt[7];
endmodule
module example (
	input  clk,
	input  SW1,
	input  SW2,
	output LED1,
	output LED2,
	output LED3,
	output LED4,

	output AA, AB, AC, AD,
	output AE, AF, AG, CA
);


	localparam BITS = 8;
	localparam LOG2DELAY = 22;

	reg [BITS+LOG2DELAY-1:0] counter = 0;
	reg [BITS-1:0] outcnt;

	always @(posedge clk) begin
		counter <= counter + SW1 + SW2 + 1;
		outcnt <= counter >> LOG2DELAY;
	end

	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);







	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
	assign CA = outcnt[7];
endmodule