data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:24: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h0: begin s = (cs && wr) ? 5\'b00001 : 5\'b00000 ;end  \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:24: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h0: begin s = (cs && wr) ? 5\'b00001 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:25: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h2: begin s = (cs && wr) ? 5\'b00010 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:25: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h2: begin s = (cs && wr) ? 5\'b00010 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:26: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'5\'h4\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h4: begin s = (cs && wr) ? 5\'b00100 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:26: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h4: begin s = (cs && wr) ? 5\'b00100 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:27: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'5\'h8\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h6: begin s = (cs && wr) ? 5\'b01000 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:27: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h6: begin s = (cs && wr) ? 5\'b01000 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:29: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'5\'h10\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h8: begin s = (cs && rd) ? 5\'b10000 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:29: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   4\'h8: begin s = (cs && rd) ? 5\'b10000 : 5\'b00000 ;end  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:30: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                       : ... In instance peripheral_pwm\n   default:begin s = 5\'b00000 ; end\n                   ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:46: Cannot find file containing module: \'pwm\'\n pwm pwm1 ( .clk(clk), .rst_n(rst_n), .number(number_1), pwm(pwm [0]) );\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/pwm\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/pwm.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:47: Cannot find file containing module: \'pwm\'\n pwm pwm2 ( .clk(clk), .rst_n(rst_n), .number(number_2), pwm(pwm [1]) );\n ^~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/peripherial_pwm.v:48: Cannot find file containing module: \'pwm\'\n pwm pwm3 ( .clk(clk), .rst_n(rst_n), .number(number_3), pwm(pwm [2]) );\n ^~~\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module peripheral_pwm (
	input clk, 
	input rst, 
	input [15:0] d_in, 
	input cs,
	input [3:0]addr,
	input rd,
	input wr, 
	output [2:0] pwm ,
	output reg [2:0] d_out
	);


	reg [5:0] 	s;
	reg 		rst_n = 0;
	reg [9:0]	number_1;
	reg [9:0]	number_2;
	reg [9:0]	number_3;
	


	always @(*) begin
		case (addr)
			4'h0:	begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end
			4'h2:	begin s = (cs && wr) ? 5'b00010 : 5'b00000 ;end
			4'h4:	begin s = (cs && wr) ? 5'b00100 : 5'b00000 ;end
			4'h6:	begin s = (cs && wr) ? 5'b01000 : 5'b00000 ;end
				
			4'h8:	begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end
			default:begin s = 5'b00000 ; end
		endcase
	end

	always @(negedge clk) begin
		rst_n 		<= ~s[0] ;
		number_1	<= (s[1]) ? d_in [9:0] : number_1 ;
		number_2	<= (s[2]) ? d_in [9:0] : number_2 ;
		number_3	<= (s[3]) ? d_in [9:0] : number_3 ;
	end

	always @(negedge clk) begin
		if ( s[4] ) 
			d_out <= pwm ;
	end

	pwm pwm1 ( .clk(clk), .rst_n(rst_n), .number(number_1), pwm(pwm [0]) );
	pwm pwm2 ( .clk(clk), .rst_n(rst_n), .number(number_2), pwm(pwm [1]) );
	pwm pwm3 ( .clk(clk), .rst_n(rst_n), .number(number_3), pwm(pwm [2]) );
	
endmodule
module peripheral_pwm (
	input clk, 
	input rst, 
	input [15:0] d_in, 
	input cs,
	input [3:0]addr,
	input rd,
	input wr, 
	output [2:0] pwm ,
	output reg [2:0] d_out
	);



	reg [5:0] 	s;
	reg 		rst_n = 0;
	reg [9:0]	number_1;
	reg [9:0]	number_2;
	reg [9:0]	number_3;
	


	always @(*) begin
		case (addr)
			4'h0:	begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end
			4'h2:	begin s = (cs && wr) ? 5'b00010 : 5'b00000 ;end
			4'h4:	begin s = (cs && wr) ? 5'b00100 : 5'b00000 ;end
			4'h6:	begin s = (cs && wr) ? 5'b01000 : 5'b00000 ;end
				
			4'h8:	begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end
			default:begin s = 5'b00000 ; end
		endcase
	end

	always @(negedge clk) begin
		rst_n 		<= ~s[0] ;
		number_1	<= (s[1]) ? d_in [9:0] : number_1 ;
		number_2	<= (s[2]) ? d_in [9:0] : number_2 ;
		number_3	<= (s[3]) ? d_in [9:0] : number_3 ;
	end

	always @(negedge clk) begin
		if ( s[4] ) 
			d_out <= pwm ;
	end

	pwm pwm1 ( .clk(clk), .rst_n(rst_n), .number(number_1), pwm(pwm [0]) );
	pwm pwm2 ( .clk(clk), .rst_n(rst_n), .number(number_2), pwm(pwm [1]) );
	pwm pwm3 ( .clk(clk), .rst_n(rst_n), .number(number_3), pwm(pwm [2]) );
	
endmodule