data/full_repos/permissive/472469504/src/PC_Register.v
data/verilator_xmls/5b8bf3a8-fe78-47c9-a642-2cb48b6b8322.xml
module PC_Register
#(
	parameter N=32
)
(
	input clk,
	input reset,
	input  [N-1:0] Next_PC,
	
	
	output reg [N-1:0] PC_Value
);

always@(negedge reset or posedge clk) begin
	if(reset==0)
		PC_Value <= 32'h400000;
	else	
		PC_Value<= Next_PC;
end

endmodule
module PC_Register
#(
	parameter N=32
)
(
	input clk,
	input reset,
	input  [N-1:0] Next_PC,
	
	
	output reg [N-1:0] PC_Value
);


always@(negedge reset or posedge clk) begin
	if(reset==0)
		PC_Value <= 32'h400000;
	else	
		PC_Value<= Next_PC;
end

endmodule