data/full_repos/permissive/433621701/generic_RB_array/generic_RB_array.v
data/verilator_xmls/f286a25c-41cd-4fb2-9dca-4e8b4365cf08.xml
module two_in_and_gate(input a, b, output reg z);
    always @(a or b)
    begin
        z = a & b;
    end
endmodule
module two_in_and_gate(input a, b, output reg z);

    always @(a or b)
    begin
        z = a & b;
    end
endmodule