data/full_repos/permissive/479997390/src/ID.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479997390/src/ID.v:97: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'5\'h0\' generates 5 bits.\n                                                                : ... In instance ID\n  assign RegData1 = RegDistDist ? 5\'d0  : ForwardedRegOut1;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/479997390/src/ID.v:100: Cannot find file containing module: \'mux4\'\n  mux4 #(.WIDTH(32)) U_FORWARD1 (\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux4\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux4.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/mux4.sv\n             mux4\n             mux4.v\n             mux4.sv\n             obj_dir/mux4\n             obj_dir/mux4.v\n             obj_dir/mux4.sv\n%Error: data/full_repos/permissive/479997390/src/ID.v:109: Cannot find file containing module: \'mux4\'\n  mux4 #(.WIDTH(32)) U_FORWARD2 (\n  ^~~~\n%Error: data/full_repos/permissive/479997390/src/ID.v:118: Cannot find file containing module: \'RegFile\'\n  RegFile U_REGFILE (\n  ^~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ID.v:129: Cannot find file containing module: \'Control\'\n  Control U_CONTROL (\n  ^~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ID.v:147: Cannot find file containing module: \'Extender\'\n  Extender U_EXTENDER (\n  ^~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module ID (
  clk, 
  NPCIn, Instr, RegWriteIn, WriteRegAddrIn, WriteRegData,
  Forward1, Forward2,
  DataFromEX, DataFromMEM, DataFromWB,

  NPCOut, 
  RegData1, RegData2, Imm32, 
  Funct, Rs, Rt,Shamt, 
  Branch, NPCCtrl, PCNew,
  ALUSrc, ALUOp, 

  WriteRegAddrOut,

  MemRead, MemWrite,
  MemToReg, RegWriteOut
);

  input clk;
  input [31:0] NPCIn, Instr, WriteRegData;
  input [4:0] WriteRegAddrIn;
  input RegWriteIn;
  input [1:0] Forward1, Forward2;
  input [31:0] DataFromEX, DataFromMEM, DataFromWB;
  output [31:0] NPCOut, RegData1, RegData2, Imm32;
  output [5:0] Funct;
  output [4:0] Rs, Rt,Shamt;

  output Branch;
  output [1:0] NPCCtrl;
  output [31:0] PCNew;
  output ALUSrc;


  output [4:0] ALUOp, WriteRegAddrOut;
  output MemRead, MemWrite;
  output MemToReg;
  output RegWriteOut;





  wire [1:0] ExtOp;
  wire Equal, BranchEql;


  wire [5:0]  OpCode;

  wire [25:0] PCNewFromInstr;
  wire [31:0] PCNewFromReg;
  wire [31:0] RegOut1, RegOut2, ForwardedRegOut1, ForwardedRegOut2;
  wire [4:0] Rd, Rj;

  wire [15:0] Imm16;
  wire PCDist, RegDistDist, RegDist;

  assign NPCOut = NPCIn;

  assign OpCode = Instr[31:26];
  assign Funct = Instr[5:0];
  assign Rs = Instr[25:21];
  assign Rt = Instr[20:16];
  assign Rd = Instr[15:11];
  assign Imm16 = Instr[15:0];
  assign Shamt = Instr[10:6];
  assign PCNewFromInstr = Instr[25:0];
  assign PCNewFromReg = RegData1;

  assign Equal = ~(|(RegData1 ^ RegData2));
  assign Branch = ~(BranchEql ^ Equal);







  assign PCNew = PCDist ? PCNewFromReg : {6'b000000, PCNewFromInstr};







  assign Rj = RegDistDist ? 5'd31 : Rd;







  assign WriteRegAddrOut = RegDist ? Rj : Rt;

  assign RegData1 = RegDistDist ? 5'd0  : ForwardedRegOut1;
  assign RegData2 = RegDistDist ? NPCIn : ForwardedRegOut2;

  mux4 #(.WIDTH(32)) U_FORWARD1 (
    .d0(RegOut1),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(DataFromEX),
    .s(Forward1),
    .y(ForwardedRegOut1)
  );

  mux4 #(.WIDTH(32)) U_FORWARD2 (
    .d0(RegOut2),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(DataFromEX),
    .s(Forward2),
    .y(ForwardedRegOut2)
  );

  RegFile U_REGFILE (
    .ReadAddr1(Rs),
    .ReadAddr2(Rt),
    .WriteAddr(WriteRegAddrIn),
    .WriteData(WriteRegData),
    .clk(clk),
    .RFWr(RegWriteIn),
    .ReadData1(RegOut1),
    .ReadData2(RegOut2)
  );

  Control U_CONTROL (
    .OpCode(OpCode),
    .Funct(Funct),

    .PCDist(PCDist),
    .NPCCtrl(NPCCtrl),
    .BranchEql(BranchEql),
    .MemRead(MemRead),
    .MemWrite(MemWrite),
    .MemToReg(MemToReg),
    .RegWrite(RegWriteOut),
    .ALUSrc(ALUSrc),
    .ALUOp(ALUOp),
    .RegDist(RegDist),
    .RegDistDist(RegDistDist),
    .ExtOp(ExtOp)
  );

  Extender U_EXTENDER (
    .Imm16(Imm16),
    .ExtOp(ExtOp),
    .Imm32(Imm32)
  );
























































  
endmodule
module ID (
  clk, 
  NPCIn, Instr, RegWriteIn, WriteRegAddrIn, WriteRegData,
  Forward1, Forward2,
  DataFromEX, DataFromMEM, DataFromWB,

  NPCOut, 
  RegData1, RegData2, Imm32, 
  Funct, Rs, Rt,Shamt, 
  Branch, NPCCtrl, PCNew,
  ALUSrc, ALUOp, 

  WriteRegAddrOut,

  MemRead, MemWrite,
  MemToReg, RegWriteOut
);


  input clk;
  input [31:0] NPCIn, Instr, WriteRegData;
  input [4:0] WriteRegAddrIn;
  input RegWriteIn;
  input [1:0] Forward1, Forward2;
  input [31:0] DataFromEX, DataFromMEM, DataFromWB;
  output [31:0] NPCOut, RegData1, RegData2, Imm32;
  output [5:0] Funct;
  output [4:0] Rs, Rt,Shamt;

  output Branch;
  output [1:0] NPCCtrl;
  output [31:0] PCNew;
  output ALUSrc;


  output [4:0] ALUOp, WriteRegAddrOut;
  output MemRead, MemWrite;
  output MemToReg;
  output RegWriteOut;





  wire [1:0] ExtOp;
  wire Equal, BranchEql;


  wire [5:0]  OpCode;

  wire [25:0] PCNewFromInstr;
  wire [31:0] PCNewFromReg;
  wire [31:0] RegOut1, RegOut2, ForwardedRegOut1, ForwardedRegOut2;
  wire [4:0] Rd, Rj;

  wire [15:0] Imm16;
  wire PCDist, RegDistDist, RegDist;

  assign NPCOut = NPCIn;

  assign OpCode = Instr[31:26];
  assign Funct = Instr[5:0];
  assign Rs = Instr[25:21];
  assign Rt = Instr[20:16];
  assign Rd = Instr[15:11];
  assign Imm16 = Instr[15:0];
  assign Shamt = Instr[10:6];
  assign PCNewFromInstr = Instr[25:0];
  assign PCNewFromReg = RegData1;

  assign Equal = ~(|(RegData1 ^ RegData2));
  assign Branch = ~(BranchEql ^ Equal);







  assign PCNew = PCDist ? PCNewFromReg : {6'b000000, PCNewFromInstr};







  assign Rj = RegDistDist ? 5'd31 : Rd;







  assign WriteRegAddrOut = RegDist ? Rj : Rt;

  assign RegData1 = RegDistDist ? 5'd0  : ForwardedRegOut1;
  assign RegData2 = RegDistDist ? NPCIn : ForwardedRegOut2;

  mux4 #(.WIDTH(32)) U_FORWARD1 (
    .d0(RegOut1),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(DataFromEX),
    .s(Forward1),
    .y(ForwardedRegOut1)
  );

  mux4 #(.WIDTH(32)) U_FORWARD2 (
    .d0(RegOut2),
    .d1(DataFromWB),
    .d2(DataFromMEM),
    .d3(DataFromEX),
    .s(Forward2),
    .y(ForwardedRegOut2)
  );

  RegFile U_REGFILE (
    .ReadAddr1(Rs),
    .ReadAddr2(Rt),
    .WriteAddr(WriteRegAddrIn),
    .WriteData(WriteRegData),
    .clk(clk),
    .RFWr(RegWriteIn),
    .ReadData1(RegOut1),
    .ReadData2(RegOut2)
  );

  Control U_CONTROL (
    .OpCode(OpCode),
    .Funct(Funct),

    .PCDist(PCDist),
    .NPCCtrl(NPCCtrl),
    .BranchEql(BranchEql),
    .MemRead(MemRead),
    .MemWrite(MemWrite),
    .MemToReg(MemToReg),
    .RegWrite(RegWriteOut),
    .ALUSrc(ALUSrc),
    .ALUOp(ALUOp),
    .RegDist(RegDist),
    .RegDistDist(RegDistDist),
    .ExtOp(ExtOp)
  );

  Extender U_EXTENDER (
    .Imm16(Imm16),
    .ExtOp(ExtOp),
    .Imm32(Imm32)
  );
























































  
endmodule