data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/rtl/ibex_register_file_fpga.sv
data/verilator_xmls/10f7e59b-e755-4e76-b468-ec1c9c4ae184.xml
module ibex_register_file_fpga #(
  parameter bit          RV32E             = 0,
  parameter int unsigned DataWidth         = 32,
  parameter bit          DummyInstructions = 0
) (

  input  logic                 clk_i,
  input  logic                 rst_ni,

  input  logic                 test_en_i,
  input  logic                 dummy_instr_id_i,


  input  logic [          4:0] raddr_a_i,
  output logic [DataWidth-1:0] rdata_a_o,

  input  logic [          4:0] raddr_b_i,
  output logic [DataWidth-1:0] rdata_b_o,

  input  logic [          4:0] waddr_a_i,
  input  logic [DataWidth-1:0] wdata_a_i,
  input  logic                 we_a_i
);

  localparam int ADDR_WIDTH = RV32E ? 4 : 5;
  localparam int NUM_WORDS  = 2**ADDR_WIDTH;

  logic [DataWidth-1:0] mem[NUM_WORDS];
  logic we;


  assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];


  assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];


  assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i;

  always_ff @(posedge clk_i) begin : sync_write
    if (we == 1'b1) begin
      mem[waddr_a_i] <= wdata_a_i;
    end
  end : sync_write


  logic unused_rst_ni;
  assign unused_rst_ni = rst_ni;


  logic unused_dummy_instr;
  assign unused_dummy_instr = dummy_instr_id_i;

  logic unused_test_en;
  assign unused_test_en = test_en_i;

endmodule
module ibex_register_file_fpga #(
  parameter bit          RV32E             = 0,
  parameter int unsigned DataWidth         = 32,
  parameter bit          DummyInstructions = 0
) (

  input  logic                 clk_i,
  input  logic                 rst_ni,

  input  logic                 test_en_i,
  input  logic                 dummy_instr_id_i,


  input  logic [          4:0] raddr_a_i,
  output logic [DataWidth-1:0] rdata_a_o,

  input  logic [          4:0] raddr_b_i,
  output logic [DataWidth-1:0] rdata_b_o,

  input  logic [          4:0] waddr_a_i,
  input  logic [DataWidth-1:0] wdata_a_i,
  input  logic                 we_a_i
);


  localparam int ADDR_WIDTH = RV32E ? 4 : 5;
  localparam int NUM_WORDS  = 2**ADDR_WIDTH;

  logic [DataWidth-1:0] mem[NUM_WORDS];
  logic we;


  assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];


  assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];


  assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i;

  always_ff @(posedge clk_i) begin : sync_write
    if (we == 1'b1) begin
      mem[waddr_a_i] <= wdata_a_i;
    end
  end : sync_write


  logic unused_rst_ni;
  assign unused_rst_ni = rst_ni;


  logic unused_dummy_instr;
  assign unused_dummy_instr = dummy_instr_id_i;

  logic unused_test_en;
  assign unused_test_en = test_en_i;

endmodule