data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/pconfigpx.v
data/verilator_xmls/c0ff9a31-f15f-4348-8d18-e34e52ef0ff8.xml
module pconfigpx
    (
     clk,
     rst,
     upen,
     upws,
     updi,
     out,
     par_dis,
     par_err,
     updo
     );

parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk,
        rst,
        upen,
        upws;
        
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] out;

output  [WIDTH-1:0] updo;

input               par_dis;
output              par_err;


wire    [WIDTH-1:0] out;
reg     [WIDTH-1:0] xxxfpcfg = RESET_VALUE;
assign              out = xxxfpcfg;

assign updo = upen ? xxxfpcfg : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if(rst) xxxfpcfg <= RESET_VALUE;
    else if(upen & upws) xxxfpcfg <= updi;
    end

reg                 xxxpar;
always @ (posedge clk)
    begin
    if (rst) xxxpar <= ^RESET_VALUE;
    else if(upen & upws & (!par_dis)) xxxpar <= ^updi;
    end
wire par_err;
assign par_err = xxxpar ^ (^xxxfpcfg);

endmodule
module pconfigpx
    (
     clk,
     rst,
     upen,
     upws,
     updi,
     out,
     par_dis,
     par_err,
     updo
     );


parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk,
        rst,
        upen,
        upws;
        
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] out;

output  [WIDTH-1:0] updo;

input               par_dis;
output              par_err;


wire    [WIDTH-1:0] out;
reg     [WIDTH-1:0] xxxfpcfg = RESET_VALUE;
assign              out = xxxfpcfg;

assign updo = upen ? xxxfpcfg : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if(rst) xxxfpcfg <= RESET_VALUE;
    else if(upen & upws) xxxfpcfg <= updi;
    end

reg                 xxxpar;
always @ (posedge clk)
    begin
    if (rst) xxxpar <= ^RESET_VALUE;
    else if(upen & upws & (!par_dis)) xxxpar <= ^updi;
    end
wire par_err;
assign par_err = xxxpar ^ (^xxxfpcfg);

endmodule