data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v
1: b'%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:55: Cannot find include file: ahb_params.v\n`include "ahb_params.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_params.v\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_params.v.v\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/ahb_params.v.sv\n             ahb_params.v\n             ahb_params.v.v\n             ahb_params.v.sv\n             obj_dir/ahb_params.v\n             obj_dir/ahb_params.v.v\n             obj_dir/ahb_params.v.sv\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:85: syntax error, unexpected \'@\'\n         @(posedge HCLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:86: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:89: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:110: syntax error, unexpected \'@\'\n         @(posedge HCLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:111: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:114: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:153: syntax error, unexpected \'@\'\n         @(posedge HCLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:154: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:161: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:162: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:183: syntax error, unexpected \'@\'\n         @(posedge HCLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:184: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:209: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:210: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:232: syntax error, unexpected \'@\'\n         @(posedge HCLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:233: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:240: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:245: syntax error, unexpected \'@\'\n           @(posedge HCLK);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/ahb_driver.v:246: Unsupported: Ignoring delay on this delayed statement.\n         #5;\n         ^\n%Error: Exiting due to 12 error(s), 8 warning(s)\n'
module ahb_driver (

   HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY,

   HCLK, HRESETn, HREADYOUT, HRDATA, HRESP
   );
   parameter AW = 12;

   input   HCLK;
   input   HRESETn;
   output  HSEL;
   output [AW-1:0] HADDR;
   output [1:0]    HTRANS;
   output [2:0]    HSIZE;
   output          HWRITE;
   output [31:0]   HWDATA;
   output          HREADY;
   input           HREADYOUT;
   input [31:0]    HRDATA;
   input           HRESP;


`include "ahb_params.v"






   reg  [AW-1:0] HADDR;
   reg           HWRITE;
   reg           HSIZE;
   reg           HTRANS;
   reg           HREADY;
   reg           HSEL;
   reg [31:0]    HWDATA;




   task t_read32bits_non_seq;
      input [AW-1:0] address;
      output [31:0]  data;

      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         data = HRDATA;
         HSEL = 1'b0;


      end
   endtask

   task t_read8bits_non_seq;
      input [AW-1:0] address;
      output [7:0]  data;

      begin

         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_8BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         case(HADDR[1:0])
           0 : begin
              data = HRDATA[7:0];
           end
           1 : begin
              data = HRDATA[15:8];
           end
           2 : begin
              data = HRDATA[23:16];
           end
           3 : begin
              data = HRDATA[31:24];
           end
           default: begin
           end

         endcase

         HSEL = 1'b0;


      end
   endtask

   task t_write32bits_non_seq;
      input [AW-1:0] address;
      input [31:0]   data;


      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b1;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;


         @(posedge HCLK);
         #5;

         HWDATA = data;


         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;

      end
   endtask

   task t_write8bits_non_seq;
      input [AW-1:0] address;
      input [7:0]   data;
      reg [31:0]    word_to_be_written;
      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b1;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_8BITS;
         HREADY = 1'b1;




         @(posedge HCLK);
         #5;

         case(HADDR[1:0])
           0 : begin
              word_to_be_written = {24'b0,data};
           end
           1 : begin
              word_to_be_written = {16'b0,data,8'b0};
           end
           2 : begin
              word_to_be_written = {8'b0,data,16'b0};
           end
           3 : begin
              word_to_be_written = {data,24'b0};
           end
           default: begin
           end

         endcase


         HWDATA = word_to_be_written;

         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;

      end
   endtask



   task t_read_then_write_32bits;
      input [AW-1:0] address1;
      output [31:0]  data1;
      input [AW-1:0] address2;
      input [31:0]  data2;

      begin
         HSEL   = 1'b1;
         HADDR = address1;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HADDR = address2;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;
         HWRITE = 1'b1;
         while(!HREADYOUT)
           @(posedge HCLK);
         data1 = HRDATA;
         HWDATA = data2;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;


      end
   endtask




endmodule
module ahb_driver (

   HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY,

   HCLK, HRESETn, HREADYOUT, HRDATA, HRESP
   );

   parameter AW = 12;

   input   HCLK;
   input   HRESETn;
   output  HSEL;
   output [AW-1:0] HADDR;
   output [1:0]    HTRANS;
   output [2:0]    HSIZE;
   output          HWRITE;
   output [31:0]   HWDATA;
   output          HREADY;
   input           HREADYOUT;
   input [31:0]    HRDATA;
   input           HRESP;


`include "ahb_params.v"






   reg  [AW-1:0] HADDR;
   reg           HWRITE;
   reg           HSIZE;
   reg           HTRANS;
   reg           HREADY;
   reg           HSEL;
   reg [31:0]    HWDATA;




   task t_read32bits_non_seq;
      input [AW-1:0] address;
      output [31:0]  data;

      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         data = HRDATA;
         HSEL = 1'b0;


      end
   endtask

   task t_read8bits_non_seq;
      input [AW-1:0] address;
      output [7:0]  data;

      begin

         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_8BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         case(HADDR[1:0])
           0 : begin
              data = HRDATA[7:0];
           end
           1 : begin
              data = HRDATA[15:8];
           end
           2 : begin
              data = HRDATA[23:16];
           end
           3 : begin
              data = HRDATA[31:24];
           end
           default: begin
           end

         endcase

         HSEL = 1'b0;


      end
   endtask

   task t_write32bits_non_seq;
      input [AW-1:0] address;
      input [31:0]   data;


      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b1;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;


         @(posedge HCLK);
         #5;

         HWDATA = data;


         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;

      end
   endtask

   task t_write8bits_non_seq;
      input [AW-1:0] address;
      input [7:0]   data;
      reg [31:0]    word_to_be_written;
      begin
         HSEL   = 1'b1;
         HADDR = address;
         HWRITE = 1'b1;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_8BITS;
         HREADY = 1'b1;




         @(posedge HCLK);
         #5;

         case(HADDR[1:0])
           0 : begin
              word_to_be_written = {24'b0,data};
           end
           1 : begin
              word_to_be_written = {16'b0,data,8'b0};
           end
           2 : begin
              word_to_be_written = {8'b0,data,16'b0};
           end
           3 : begin
              word_to_be_written = {data,24'b0};
           end
           default: begin
           end

         endcase


         HWDATA = word_to_be_written;

         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;

      end
   endtask



   task t_read_then_write_32bits;
      input [AW-1:0] address1;
      output [31:0]  data1;
      input [AW-1:0] address2;
      input [31:0]  data2;

      begin
         HSEL   = 1'b1;
         HADDR = address1;
         HWRITE = 1'b0;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;

         @(posedge HCLK);
         #5;
         HADDR = address2;
         HTRANS = AMBA_AHB_HTRANS_NON_SEQ;
         HSIZE  = AMBA_AHB_HSIZE_32BITS;
         HREADY = 1'b1;
         HWRITE = 1'b1;
         while(!HREADYOUT)
           @(posedge HCLK);
         data1 = HRDATA;
         HWDATA = data2;
         HWRITE = 1'b0;
         while(!HREADYOUT)
           @(posedge HCLK);
         #5;
         HSEL = 1'b0;


      end
   endtask




endmodule