data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v:12: Unsupported or unknown PLI call: $monitor\n  $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #3 D = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #3 D = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #3 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_from_nand.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #2 CLK = ~CLK;\n       ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff_from_nand();
wire Q,Q_BAR;
reg D,CLK;

nand U1 (X,D,CLK) ;
nand U2 (Y,X,CLK) ;
nand U3 (Q,Q_BAR,X);
nand U4 (Q_BAR,Q,Y);


initial begin
  $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
  CLK = 0;
  D = 0;
  #3 D = 1;
  #3 D = 0;
  #3 $finish;
end	

always #2 CLK = ~CLK;

endmodule
module dff_from_nand();

wire Q,Q_BAR;
reg D,CLK;

nand U1 (X,D,CLK) ;
nand U2 (Y,X,CLK) ;
nand U3 (Q,Q_BAR,X);
nand U4 (Q_BAR,Q,Y);


initial begin
  $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
  CLK = 0;
  D = 0;
  #3 D = 1;
  #3 D = 0;
  #3 $finish;
end	

always #2 CLK = ~CLK;

endmodule