data/full_repos/permissive/471941633/MIPS32/mipstb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/471941633/MIPS32/mipstb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/471941633/MIPS32/mipstb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 clk1 = ~clk1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/471941633/MIPS32/mipstb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5 clk2 = ~clk2;\n ^\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:51: Can\'t find definition of \'Reg\' in dotted variable: \'riscv.Reg\'\nriscv.Reg[k] = k;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:52: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[0] = 32\'h2801000a;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:53: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[1] = 32\'h28020014;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:54: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[2] = 32\'h28030019;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:55: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[3] = 32\'h0ce77800;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:56: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[4] = 32\'h0ce77800;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:57: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[5] = 32\'h00222000;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:58: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[6] = 32\'h0ce77800;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:59: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[7] = 32\'h00832800;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:60: Can\'t find definition of \'mem\' in dotted variable: \'riscv.mem\'\nriscv.mem[8] = 32\'hfe000000;\n      ^~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:62: Can\'t find definition of \'HALTED\' in dotted variable: \'riscv.HALTED\'\nriscv.HALTED = 0;\n      ^~~~~~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:63: Can\'t find definition of \'pc\' in dotted variable: \'riscv.pc\'\nriscv.pc = 0;\n      ^~\n%Error: data/full_repos/permissive/471941633/MIPS32/mipstb.v:64: Can\'t find definition of \'TAKEN_BRANCH\' in dotted variable: \'riscv.TAKEN_BRANCH\'\nriscv.TAKEN_BRANCH = 0;\n      ^~~~~~~~~~~~\n%Error: Exiting due to 13 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mipstb;


	reg clk1;
	reg clk2;
integer k;

	mips riscv (
		.clk1(clk1), 
		.clk2(clk2)
	);

	initial begin

		clk1 = 0;
		clk2 = 0;
		#10;
	end
	always
	begin
	#5 clk1 = ~clk1;
	#5 clk2 = ~clk2;
	end
	initial
begin
for(k=0;k<31;k=k+1)
riscv.Reg[k] = k;
riscv.mem[0] = 32'h2801000a;
riscv.mem[1] = 32'h28020014;
riscv.mem[2] = 32'h28030019;
riscv.mem[3] = 32'h0ce77800;
riscv.mem[4] = 32'h0ce77800;
riscv.mem[5] = 32'h00222000;
riscv.mem[6] = 32'h0ce77800;
riscv.mem[7] = 32'h00832800;
riscv.mem[8] = 32'hfe000000;

riscv.HALTED = 0;
riscv.pc = 0;
riscv.TAKEN_BRANCH = 0;
	end
      
endmodule
module mipstb;



	reg clk1;
	reg clk2;
integer k;

	mips riscv (
		.clk1(clk1), 
		.clk2(clk2)
	);

	initial begin

		clk1 = 0;
		clk2 = 0;
		#10;
	end
	always
	begin
	#5 clk1 = ~clk1;
	#5 clk2 = ~clk2;
	end
	initial
begin
for(k=0;k<31;k=k+1)
riscv.Reg[k] = k;
riscv.mem[0] = 32'h2801000a;
riscv.mem[1] = 32'h28020014;
riscv.mem[2] = 32'h28030019;
riscv.mem[3] = 32'h0ce77800;
riscv.mem[4] = 32'h0ce77800;
riscv.mem[5] = 32'h00222000;
riscv.mem[6] = 32'h0ce77800;
riscv.mem[7] = 32'h00832800;
riscv.mem[8] = 32'hfe000000;

riscv.HALTED = 0;
riscv.pc = 0;
riscv.TAKEN_BRANCH = 0;
	end
      
endmodule