data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/encoder/encoder.v
data/verilator_xmls/238aa246-af09-4f43-8f19-b503ff329ba7.xml
module encoder
#(
	parameter logS=4
)
(
	g_input,
  e_input,
	o
);
	
	localparam S = 2**logS;
	input [S/2-1:0] g_input;
  input [S/2-1:0] e_input;
	output [logS-1:0] o;

  wire [S-1:0] in;

  assign in[S/2-1:0] = g_input;
  assign in[S-1:S/2] = e_input;

  encoder_
  #(
    .logS(logS)
  )
  encoder0
  (
    .in(in),
    .o(o)
  );

endmodule
module encoder
#(
	parameter logS=4
)
(
	g_input,
  e_input,
	o
);

	
	localparam S = 2**logS;
	input [S/2-1:0] g_input;
  input [S/2-1:0] e_input;
	output [logS-1:0] o;

  wire [S-1:0] in;

  assign in[S/2-1:0] = g_input;
  assign in[S-1:S/2] = e_input;

  encoder_
  #(
    .logS(logS)
  )
  encoder0
  (
    .in(in),
    .o(o)
  );

endmodule