data/full_repos/permissive/481307378/source_files/TrafficLight/timer.v
data/verilator_xmls/cb3199b1-9cbe-4d80-bfad-37af02a00c9d.xml
module timer(
    input RES,
    input CLK,
    
    output TICK
);


    parameter CLOCK_SIGNALS = 32'd500000000;
   
    reg [ 31 : 0 ] count = 32'd0;
    reg tick_val = 1'b0;
     
    always @(posedge CLK, posedge RES)
    begin
    
        if(RES == 1'b1) begin
            tick_val = 1'b0;
            count = 32'd0;
        end    
            
        else begin
        
            if(count == (CLOCK_SIGNALS - 1))
                tick_val = 1'b1;
           
            else 
                count = count + 1;
                
        end
        
    end
    
    assign TICK = tick_val;
    

endmodule
module timer(
    input RES,
    input CLK,
    
    output TICK
);



    parameter CLOCK_SIGNALS = 32'd500000000;
   
    reg [ 31 : 0 ] count = 32'd0;
    reg tick_val = 1'b0;
     
    always @(posedge CLK, posedge RES)
    begin
    
        if(RES == 1'b1) begin
            tick_val = 1'b0;
            count = 32'd0;
        end    
            
        else begin
        
            if(count == (CLOCK_SIGNALS - 1))
                tick_val = 1'b1;
           
            else 
                count = count + 1;
                
        end
        
    end
    
    assign TICK = tick_val;
    

endmodule