data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/intfdemux6.v
data/verilator_xmls/c0fca6d8-d40d-4603-87d2-120559a063a3.xml
module intfdemux6
    (
     rst_,
     iclk38, 
     
     idat,
     isyn,

     odat
     );




parameter LINEBIT = 12;
parameter DEMUX   = 6;
parameter BITTS   = 3;
parameter MAXTS   = 4;
parameter DATABIT = DEMUX*LINEBIT;




input                rst_;
input                iclk38;

input [LINEBIT-1:0]  idat;
input                isyn;

output [DATABIT-1:0] odat;




reg [2:0] cntph;
wire      endcntph;
assign    endcntph = (cntph == (DEMUX-1));

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) cntph <= 3'd0;
    else if(isyn)       cntph <= 3'd1;

    else                cntph <= cntph + 1'b1;
    end
       
reg [DATABIT-1:0] dashf;
wire [DATABIT+LINEBIT-1:0] dacap;
assign                     dacap = {dashf,idat};

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_)   dashf <= {DATABIT{1'b0}};
    else        dashf <= dacap[DATABIT-1:0];
    end



reg [DATABIT-1:0] odat;
wire              latch_dat;
assign            latch_dat = (cntph == (DEMUX-1));
always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) odat <= {DATABIT{1'b0}};
    else if(latch_dat) odat <= dacap[DATABIT-1:0];
    end

endmodule
module intfdemux6
    (
     rst_,
     iclk38, 
     
     idat,
     isyn,

     odat
     );





parameter LINEBIT = 12;
parameter DEMUX   = 6;
parameter BITTS   = 3;
parameter MAXTS   = 4;
parameter DATABIT = DEMUX*LINEBIT;




input                rst_;
input                iclk38;

input [LINEBIT-1:0]  idat;
input                isyn;

output [DATABIT-1:0] odat;




reg [2:0] cntph;
wire      endcntph;
assign    endcntph = (cntph == (DEMUX-1));

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) cntph <= 3'd0;
    else if(isyn)       cntph <= 3'd1;

    else                cntph <= cntph + 1'b1;
    end
       
reg [DATABIT-1:0] dashf;
wire [DATABIT+LINEBIT-1:0] dacap;
assign                     dacap = {dashf,idat};

always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_)   dashf <= {DATABIT{1'b0}};
    else        dashf <= dacap[DATABIT-1:0];
    end



reg [DATABIT-1:0] odat;
wire              latch_dat;
assign            latch_dat = (cntph == (DEMUX-1));
always @(posedge iclk38 or negedge rst_)
    begin
    if(!rst_) odat <= {DATABIT{1'b0}};
    else if(latch_dat) odat <= dacap[DATABIT-1:0];
    end

endmodule