data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:10: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_32f = ~clk_32f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:13: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_parallel_serial.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:14: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:19: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:21: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:31: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:40: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:49: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:58: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:68: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:77: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:106: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg checker; \n     ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:106: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg checker; \n            ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:108: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_c == Data_out_e) checker = 1;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:108: syntax error, unexpected \'=\'\n  if (Data_out_c == Data_out_e) checker = 1;\n                                        ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/parallel-serial/probador_parallel_serial.v:109: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker = 0;\n       ^~~~~~~\n%Error: Exiting due to 15 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_parallel_serial (
	output reg clk_32f,
	output reg reset,
	output reg valid_in,
	output reg [7:0] Data_in,
	input Data_out_c,
	input Data_out_e
);
	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_parallel_serial.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'b0;
		@(posedge clk_32f);
		reset <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hFF;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hEE;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hAA;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hCC;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish; 
	end



	reg checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker = 1;
		else checker = 0;
	end
endmodule
module probador_parallel_serial (
	output reg clk_32f,
	output reg reset,
	output reg valid_in,
	output reg [7:0] Data_in,
	input Data_out_c,
	input Data_out_e
);

	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_parallel_serial.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'b0;
		@(posedge clk_32f);
		reset <= 1;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hFF;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hEE;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hAA;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hCC;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish; 
	end



	reg checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker = 1;
		else checker = 0;
	end
endmodule