data/full_repos/permissive/418749135/fulladder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n            a = 0;b = 0;cin = 0; #20;\n                                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n            a = 0;b = 0;cin = 1; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n            a = 0;b = 1;cin = 0; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n            a = 0;b = 1;cin = 1; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n            a = 1;b = 0;cin = 0; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n            a = 1;b = 0;cin = 1; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n            a = 1;b = 1;cin = 0; #20;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/fulladder_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n            a = 1;b = 1;cin = 1; #20;\n                                 ^\n%Error: data/full_repos/permissive/418749135/fulladder_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/fulladder_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_tb;

    reg a, b, cin;
    wire cout, sum;

    full_adder out (a,b,cin,cout,sum);
    
    initial 
        begin
            
            a = 0;b = 0;cin = 0; #20;
            a = 0;b = 0;cin = 1; #20;
            a = 0;b = 1;cin = 0; #20;
            a = 0;b = 1;cin = 1; #20;
            a = 1;b = 0;cin = 0; #20;
            a = 1;b = 0;cin = 1; #20;
            a = 1;b = 1;cin = 0; #20;
            a = 1;b = 1;cin = 1; #20;
         end
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule
module full_adder_tb;


    reg a, b, cin;
    wire cout, sum;

    full_adder out (a,b,cin,cout,sum);
    
    initial 
        begin
            
            a = 0;b = 0;cin = 0; #20;
            a = 0;b = 0;cin = 1; #20;
            a = 0;b = 1;cin = 0; #20;
            a = 0;b = 1;cin = 1; #20;
            a = 1;b = 0;cin = 0; #20;
            a = 1;b = 0;cin = 1; #20;
            a = 1;b = 1;cin = 0; #20;
            a = 1;b = 1;cin = 1; #20;
         end
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule