data/full_repos/permissive/507564148/code/basic/count.v
data/verilator_xmls/7367e606-cedd-4568-9bcc-eade11894710.xml
module count (
    input clk,
    input start,
    input pause,
    input rst_n,
    output reg[15:0] Q,
    output reg out_time

);



reg[3:0] Q1;
reg[3:0] Q2;
reg[3:0] Q3;
reg[3:0] Q4;
reg flag;

always @(posedge clk) begin
    if((start == 1'b1) || (rst_n == 1'b0))
    begin
        Q1 <= 4'd0;
        Q2 <= 4'd0;
        Q3 <= 4'd0;
        Q4 <= 4'd0;
        out_time <= 1'b0;
    end
    else if(Q4 == 4'd9) begin
        Q4 <= 4'd0;
        if(Q3 == 4'd9)begin
            Q3 <= 4'd0;
            if(Q2 == 4'd9)begin
                Q2 <= 4'd0;
                if(Q1 == 4'd9)begin
                    Q1 <= 4'd9;
                    Q2 <= 4'd9;
                    Q3 <= 4'd9;
                    Q4 <= 4'd9;
                    out_time <= 1'b1;
                end
                else
                    Q1 <= Q1+4'd1;
            end
            else
                Q2 <= Q2+4'd1;
        end
        else
            Q3 <= Q3+4'd1;
    end
    else
        Q4 <= Q4+4'd1;
end


always @(posedge clk) begin
    if(!rst_n) begin
        flag <= 1'b0; 
    end
    else if(pause) begin
        flag <= 1'b1;
    end
    else begin
        flag <= flag;
    end
end


always @(posedge clk) begin
if(~flag) begin
    Q[3:0] <= Q4;
    Q[7:4] <= Q3;
    Q[11:8] <= Q2;
    Q[15:12] <= Q1;
end
else begin
    Q <= Q;
end

end
endmodule
module count (
    input clk,
    input start,
    input pause,
    input rst_n,
    output reg[15:0] Q,
    output reg out_time

);




reg[3:0] Q1;
reg[3:0] Q2;
reg[3:0] Q3;
reg[3:0] Q4;
reg flag;

always @(posedge clk) begin
    if((start == 1'b1) || (rst_n == 1'b0))
    begin
        Q1 <= 4'd0;
        Q2 <= 4'd0;
        Q3 <= 4'd0;
        Q4 <= 4'd0;
        out_time <= 1'b0;
    end
    else if(Q4 == 4'd9) begin
        Q4 <= 4'd0;
        if(Q3 == 4'd9)begin
            Q3 <= 4'd0;
            if(Q2 == 4'd9)begin
                Q2 <= 4'd0;
                if(Q1 == 4'd9)begin
                    Q1 <= 4'd9;
                    Q2 <= 4'd9;
                    Q3 <= 4'd9;
                    Q4 <= 4'd9;
                    out_time <= 1'b1;
                end
                else
                    Q1 <= Q1+4'd1;
            end
            else
                Q2 <= Q2+4'd1;
        end
        else
            Q3 <= Q3+4'd1;
    end
    else
        Q4 <= Q4+4'd1;
end


always @(posedge clk) begin
    if(!rst_n) begin
        flag <= 1'b0; 
    end
    else if(pause) begin
        flag <= 1'b1;
    end
    else begin
        flag <= flag;
    end
end


always @(posedge clk) begin
if(~flag) begin
    Q[3:0] <= Q4;
    Q[7:4] <= Q3;
    Q[11:8] <= Q2;
    Q[15:12] <= Q1;
end
else begin
    Q <= Q;
end

end
endmodule