data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/More Circuits/Rule110/top_module.v
1: b'%Error: Cannot find file containing module: Logic/More\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.sv\n             Logic/More\n             Logic/More.v\n             Logic/More.sv\n             obj_dir/Logic/More\n             obj_dir/Logic/More.v\n             obj_dir/Logic/More.sv\n%Error: Cannot find file containing module: Circuits/Rule110,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Circuits/Rule110/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire clk,
    input wire load,
    input wire [511:0] data,
    output reg [511:0] q
);

  integer i;

  always @(posedge clk) begin
    if (load) q <= data;
    else begin
      for (i = 0; i < $bits(q); i = i + 1) begin
        if (i == 0) begin
          case ({
            q[i+1], q[i]
          })
            2'b10:   q[i] <= 1'b0;
            2'b00:   q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end else if (i == $bits(q) - 1) begin
          case ({
            q[i], q[i-1]
          })
            2'b00:   q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end else begin
          case ({
            q[i+1], q[i], q[i-1]
          })
            3'b111:  q[i] <= 1'b0;
            3'b100:  q[i] <= 1'b0;
            3'b000:  q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end
      end
    end
  end

endmodule
module top_module (
    input wire clk,
    input wire load,
    input wire [511:0] data,
    output reg [511:0] q
);


  integer i;

  always @(posedge clk) begin
    if (load) q <= data;
    else begin
      for (i = 0; i < $bits(q); i = i + 1) begin
        if (i == 0) begin
          case ({
            q[i+1], q[i]
          })
            2'b10:   q[i] <= 1'b0;
            2'b00:   q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end else if (i == $bits(q) - 1) begin
          case ({
            q[i], q[i-1]
          })
            2'b00:   q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end else begin
          case ({
            q[i+1], q[i], q[i-1]
          })
            3'b111:  q[i] <= 1'b0;
            3'b100:  q[i] <= 1'b0;
            3'b000:  q[i] <= 1'b0;
            default: q[i] <= 1'b1;
          endcase
        end
      end
    end
  end

endmodule