data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU.v:38: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                   : ... In instance VerySimpleCPU\n   pc_current   <= 10\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU.v:110: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 14 bits.\n                                                                                    : ... In instance VerySimpleCPU\n      r2_next = iw_current[13:0];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU.v:196: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                    : ... In instance VerySimpleCPU\n       pc_next   = r1_current + r2_current;\n                 ^\n%Error: Exiting due to 3 warning(s)\n'
module VerySimpleCPU(clk, rst, debug_en, debug_pc_out, data_fromRAM, wrEn, addr_toRAM, data_toRAM, mem_req, mem_vld, done);

	parameter SIZE = 14;

	input clk, rst;

	input debug_en;
	output [SIZE-1:0] debug_pc_out;

	input wire [31:0] data_fromRAM;
	output reg wrEn;
	output reg [13:0] addr_toRAM;
	output reg [31:0] data_toRAM;
	input mem_vld;
	output reg mem_req;
	output done;

	`define reset 0
	`define fetch 1
	`define decode_0 2
	`define decode_1 3
	`define decode_2 4
	`define decode_3 5
	`define execute 6

	reg [6:0] state_current, state_next;
	reg [SIZE-1:0] pc_current, pc_next, pc_last;
	reg [31:0] iw_current, iw_next;
	reg [31:0] r1_current, r1_next;
	reg [31:0] r2_current, r2_next;

	assign done = (pc_current == pc_last) ? 1'b1 : 1'b0;


	always@(posedge clk) begin
		if(rst) begin
			state_current	<= `reset;
			pc_current 		<= 10'b0;
			iw_current 		<= 32'b0;
			r1_current 		<= 32'b0;
			r2_current 		<= 32'b0;
		end
		else begin
			state_current 	<= state_next;
			pc_current 		<= pc_next;
			pc_last 		<= (state_current == `execute) ? pc_current : pc_last;
			iw_current 		<= iw_next;
			r1_current 		<= r1_next;
			r2_current 		<= r2_next;
		end
	end

	always@(*) begin
		state_next = state_current;
		pc_next = pc_current;
		iw_next = iw_current;
		r1_next = r1_current;
		r2_next = r2_current;
		wrEn = 0;
		addr_toRAM = 0;
		data_toRAM = 0;
		mem_req = 0;
		case(state_current)

			`reset: begin
				pc_next = 0;
				iw_next = 0;
				r1_next = 0;
				r2_next = 0;
				state_next = `fetch;
			end

			`fetch: begin
				if(mem_vld) begin
					mem_req = 1'b1;
					addr_toRAM = pc_current;
					if(debug_en) begin
						state_next = `decode_0;
					end
				end
			end

			`decode_0: begin
				if(mem_vld) begin
					iw_next = data_fromRAM;
					if(data_fromRAM[31:29] == 3'b100) begin
						state_next = `decode_2;
					end
					else begin
						state_next = `decode_1;
					end
				end
			end

			`decode_1: begin
				mem_req = 1;
				if(iw_current[31:28] == 4'b1010) begin
					addr_toRAM = iw_current[13:0];
				end
				else begin
					addr_toRAM = iw_current[27:14];
				end
				state_next = `decode_2;
			end

			`decode_2: begin
				if(mem_vld) begin
					if((iw_current[31:29] != 3'b101) && iw_current[28]) begin
						r1_next = data_fromRAM;
						r2_next = iw_current[13:0];
						state_next = `execute;
					end
					else begin
						mem_req = 1;
						if(iw_current[31:28] == 4'b1010) begin
							addr_toRAM = data_fromRAM[13:0];
						end
						else begin
							r1_next = data_fromRAM;
							addr_toRAM = iw_current[13:0];
						end
						state_next = `decode_3;
					end
				end
			end
			`decode_3: begin
				if(mem_vld) begin
					r2_next = data_fromRAM;
					state_next = `execute;
				end
			end

			`execute: begin
				if(mem_vld) begin
					casex(iw_current[31:28])
						{3'b000,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current + r2_current);
						end
						{3'b001,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= ~(r1_current & r2_current);
						end
						{3'b010,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r2_current < 32) ? (r1_current >> r2_current) : (r1_current << (r2_current-32));
						end
						{3'b011,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current < r2_current) ? 1 : 0;
						end
						{3'b111,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current * r2_current);
						end
						{3'b100,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= r2_current;
						end
						{3'b101,1'b0}: begin
							wrEn			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= r2_current;
						end
						{3'b101,1'b1}: begin
							wrEn			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= r1_current[13:0];
							data_toRAM 	= r2_current;
						end
						{3'b110,1'b0}: begin
							pc_next 		= (r2_current == 0) ? r1_current[13:0] : (pc_current + 1'b1);
						end
						{3'b110,1'b1}: begin
							pc_next 		= r1_current + r2_current;
						end
					endcase
					state_next = `fetch;
				end
			end
		endcase
	end

	assign debug_pc_out = pc_current;

endmodule
module VerySimpleCPU(clk, rst, debug_en, debug_pc_out, data_fromRAM, wrEn, addr_toRAM, data_toRAM, mem_req, mem_vld, done);


	parameter SIZE = 14;

	input clk, rst;

	input debug_en;
	output [SIZE-1:0] debug_pc_out;

	input wire [31:0] data_fromRAM;
	output reg wrEn;
	output reg [13:0] addr_toRAM;
	output reg [31:0] data_toRAM;
	input mem_vld;
	output reg mem_req;
	output done;

	`define reset 0
	`define fetch 1
	`define decode_0 2
	`define decode_1 3
	`define decode_2 4
	`define decode_3 5
	`define execute 6

	reg [6:0] state_current, state_next;
	reg [SIZE-1:0] pc_current, pc_next, pc_last;
	reg [31:0] iw_current, iw_next;
	reg [31:0] r1_current, r1_next;
	reg [31:0] r2_current, r2_next;

	assign done = (pc_current == pc_last) ? 1'b1 : 1'b0;


	always@(posedge clk) begin
		if(rst) begin
			state_current	<= `reset;
			pc_current 		<= 10'b0;
			iw_current 		<= 32'b0;
			r1_current 		<= 32'b0;
			r2_current 		<= 32'b0;
		end
		else begin
			state_current 	<= state_next;
			pc_current 		<= pc_next;
			pc_last 		<= (state_current == `execute) ? pc_current : pc_last;
			iw_current 		<= iw_next;
			r1_current 		<= r1_next;
			r2_current 		<= r2_next;
		end
	end

	always@(*) begin
		state_next = state_current;
		pc_next = pc_current;
		iw_next = iw_current;
		r1_next = r1_current;
		r2_next = r2_current;
		wrEn = 0;
		addr_toRAM = 0;
		data_toRAM = 0;
		mem_req = 0;
		case(state_current)

			`reset: begin
				pc_next = 0;
				iw_next = 0;
				r1_next = 0;
				r2_next = 0;
				state_next = `fetch;
			end

			`fetch: begin
				if(mem_vld) begin
					mem_req = 1'b1;
					addr_toRAM = pc_current;
					if(debug_en) begin
						state_next = `decode_0;
					end
				end
			end

			`decode_0: begin
				if(mem_vld) begin
					iw_next = data_fromRAM;
					if(data_fromRAM[31:29] == 3'b100) begin
						state_next = `decode_2;
					end
					else begin
						state_next = `decode_1;
					end
				end
			end

			`decode_1: begin
				mem_req = 1;
				if(iw_current[31:28] == 4'b1010) begin
					addr_toRAM = iw_current[13:0];
				end
				else begin
					addr_toRAM = iw_current[27:14];
				end
				state_next = `decode_2;
			end

			`decode_2: begin
				if(mem_vld) begin
					if((iw_current[31:29] != 3'b101) && iw_current[28]) begin
						r1_next = data_fromRAM;
						r2_next = iw_current[13:0];
						state_next = `execute;
					end
					else begin
						mem_req = 1;
						if(iw_current[31:28] == 4'b1010) begin
							addr_toRAM = data_fromRAM[13:0];
						end
						else begin
							r1_next = data_fromRAM;
							addr_toRAM = iw_current[13:0];
						end
						state_next = `decode_3;
					end
				end
			end
			`decode_3: begin
				if(mem_vld) begin
					r2_next = data_fromRAM;
					state_next = `execute;
				end
			end

			`execute: begin
				if(mem_vld) begin
					casex(iw_current[31:28])
						{3'b000,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current + r2_current);
						end
						{3'b001,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= ~(r1_current & r2_current);
						end
						{3'b010,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r2_current < 32) ? (r1_current >> r2_current) : (r1_current << (r2_current-32));
						end
						{3'b011,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current < r2_current) ? 1 : 0;
						end
						{3'b111,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= (r1_current * r2_current);
						end
						{3'b100,1'bx}: begin
							wrEn 			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= r2_current;
						end
						{3'b101,1'b0}: begin
							wrEn			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= iw_current[27:14];
							data_toRAM 	= r2_current;
						end
						{3'b101,1'b1}: begin
							wrEn			= 1'b1;
							mem_req 		= 1'b1;
							pc_next 		= pc_current + 1;
							addr_toRAM 	= r1_current[13:0];
							data_toRAM 	= r2_current;
						end
						{3'b110,1'b0}: begin
							pc_next 		= (r2_current == 0) ? r1_current[13:0] : (pc_current + 1'b1);
						end
						{3'b110,1'b1}: begin
							pc_next 		= r1_current + r2_current;
						end
					endcase
					state_next = `fetch;
				end
			end
		endcase
	end

	assign debug_pc_out = pc_current;

endmodule