data/full_repos/permissive/497819211/04/Clk.v
data/verilator_xmls/bbb90746-e974-456a-80ae-9e4ae2092f83.xml
module Clk(
	input wire in,
	output reg out = 1'b0
);


parameter NUM_DIV = 5;
reg [15:0] cnt = 16'd0;


always @(posedge in)
   if(cnt < NUM_DIV) begin
        cnt     <= cnt + 1'b1;
        out    <= out;
    end
    else begin
        cnt     <= 16'd0;
        out    <= ~out;
    end

endmodule
module Clk(
	input wire in,
	output reg out = 1'b0
);



parameter NUM_DIV = 5;
reg [15:0] cnt = 16'd0;


always @(posedge in)
   if(cnt < NUM_DIV) begin
        cnt     <= cnt + 1'b1;
        out    <= out;
    end
    else begin
        cnt     <= 16'd0;
        out    <= ~out;
    end

endmodule