data/full_repos/permissive/434837003/test/event.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #d r = \'h35;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #d r = \'hE2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #d r = \'h00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #d r = \'hF7;\n    ^\n%Error: data/full_repos/permissive/434837003/test/event.v:11: syntax error, unexpected ->\n    #d -> end_wave;  \n       ^~\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #d -> end_wave;  \n    ^\n%Error: data/full_repos/permissive/434837003/test/event.v:15: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #50 r = \'h35;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100 r = \'hE2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #150 r = \'h00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #200 r = \'hF7;\n    ^\n%Error: data/full_repos/permissive/434837003/test/event.v:20: syntax error, unexpected ->\n    #250 -> end_wave[2];\n         ^~\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/event.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #250 -> end_wave[2];\n    ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

parameter d = 50;
reg [7:0] r;

initial begin
    #d r = 'h35;
    #d r = 'hE2;
    #d r = 'h00;
    #d r = 'hF7;
    #d -> end_wave;
end


initial fork
    #50 r = 'h35;
    #100 r = 'hE2;
    #150 r = 'h00;
    #200 r = 'hF7;
    #250 -> end_wave[2];
join

endmodule
module test;


parameter d = 50;
reg [7:0] r;

initial begin
    #d r = 'h35;
    #d r = 'hE2;
    #d r = 'h00;
    #d r = 'hF7;
    #d -> end_wave;
end


initial fork
    #50 r = 'h35;
    #100 r = 'hE2;
    #150 r = 'h00;
    #200 r = 'hF7;
    #250 -> end_wave[2];
join

endmodule