data/full_repos/permissive/507564148/code/basic/randout.v
1: b"%Error: data/full_repos/permissive/507564148/code/basic/randout.v:4: syntax error, unexpected new, expecting '['\n    input new,         \n             ^\n%Error: data/full_repos/permissive/507564148/code/basic/randout.v:7: syntax error, unexpected ')', expecting ',' or ';'\n    );\n    ^\n%Error: data/full_repos/permissive/507564148/code/basic/randout.v:15: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: data/full_repos/permissive/507564148/code/basic/randout.v:26: syntax error, unexpected always\nalways @(posedge clk ) begin\n^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module randout(
    input clk,
    input rst_n,
    input new,
    
    output wire  [12:0] rand_num
    );
parameter seed = 13'b1010001001011;
parameter feedback = 13'd4761;
wire [12:0] temp;
reg  [12:0] rand_code;
reg  [12:0] rand_num_temp;

reg new_pre;
always @(posedge clk) begin
    if(!rst_n) begin
        new_pre <= 1'b0;
    end
    else begin
        new_pre <= new;
    end
end


wire feedback_item = ^(feedback & rand_code);
always @(posedge clk ) begin
    if(!rst_n) begin
        rand_code <= seed;
    end

    else if( rand_code == 13'd0) begin
        rand_code <= seed;
    end
    else begin
        rand_code <= {feedback_item,rand_code[12:1]};
    end
end

always @(posedge clk) begin
    if(!rst_n) begin
        rand_num_temp <= seed;
    end
    else if(~new_pre & new) begin
        rand_num_temp <= rand_code;
    end
    else begin
        rand_num_temp <= rand_num_temp;
    end
end


assign temp = (rand_num_temp > 13'd5000) ? (rand_num_temp - 13'd5000) : rand_num_temp;
assign rand_num = (temp < 13'd500) ? (temp + 13'd500) : temp;

endmodule
module randout(
    input clk,
    input rst_n,
    input new,
    
    output wire  [12:0] rand_num
    );

parameter seed = 13'b1010001001011;
parameter feedback = 13'd4761;
wire [12:0] temp;
reg  [12:0] rand_code;
reg  [12:0] rand_num_temp;

reg new_pre;
always @(posedge clk) begin
    if(!rst_n) begin
        new_pre <= 1'b0;
    end
    else begin
        new_pre <= new;
    end
end


wire feedback_item = ^(feedback & rand_code);
always @(posedge clk ) begin
    if(!rst_n) begin
        rand_code <= seed;
    end

    else if( rand_code == 13'd0) begin
        rand_code <= seed;
    end
    else begin
        rand_code <= {feedback_item,rand_code[12:1]};
    end
end

always @(posedge clk) begin
    if(!rst_n) begin
        rand_num_temp <= seed;
    end
    else if(~new_pre & new) begin
        rand_num_temp <= rand_code;
    end
    else begin
        rand_num_temp <= rand_num_temp;
    end
end


assign temp = (rand_num_temp > 13'd5000) ? (rand_num_temp - 13'd5000) : rand_num_temp;
assign rand_num = (temp < 13'd500) ? (temp + 13'd500) : temp;

endmodule