data/full_repos/permissive/418749135/alu_8_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/alu_8_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n     #10 s=s+1\'b1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/alu_8_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n       #50 $finish;\n       ^\n%Error: data/full_repos/permissive/418749135/alu_8_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/alu_8_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_8_tb;
   reg [3:0] a;
   reg [3:0] b;
   reg [2:0] s;
   wire [4:0] out;

   alu_8 m1(.out(out),.a(a),.b(b),.s(s));

   initial begin
       a=4'b1010;
       b=4'b1111;
       s=3'b000;
   end
   always
     #10 s=s+1'b1;
   initial begin
       #50 $finish;
   end  
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule
module alu_8_tb;

   reg [3:0] a;
   reg [3:0] b;
   reg [2:0] s;
   wire [4:0] out;

   alu_8 m1(.out(out),.a(a),.b(b),.s(s));

   initial begin
       a=4'b1010;
       b=4'b1111;
       s=3'b000;
   end
   always
     #10 s=s+1'b1;
   initial begin
       #50 $finish;
   end  
initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule