data/full_repos/permissive/411838135/rv/plic.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:96: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s REPLICATE generates 17 bits.\n                                                                  : ... In instance plic\n   assign   c_pending_mux = (addr[11:3]!=0?64\'b0: {1\'b0,pending});\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:101: Operator ASSIGNW expects 63 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                   : ... In instance plic\n    wire [63:1]t = {1\'b0,r_int_enable[H]};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:115: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'w\' generates 63 bits.\n                                                                   : ... In instance plic\n     r_int_enable[H] <= w;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:114: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 15 bits.\n                                                                   : ... In instance plic\n    if (addr_req && sel && !read && addr[21:7] == (32\'h40+H) && addr[7:3] == 0) begin\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:122: Bit extraction of array[0:0] requires 1 bit index, not 5 bits.\n                                                                   : ... In instance plic\n   assign    c_enabled_mux = (addr[11:7] >= (NHART) || addr[6:3]!=0?64\'b0: {1\'b0,r_int_enable[addr[11:7]]});\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:122: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s REPLICATE generates 16 bits.\n                                                                   : ... In instance plic\n   assign    c_enabled_mux = (addr[11:7] >= (NHART) || addr[6:3]!=0?64\'b0: {1\'b0,r_int_enable[addr[11:7]]});\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:173: Bit extraction of array[0:0] requires 1 bit index, not 9 bits.\n                                                                   : ... In instance plic\n  wire [7:0]c_claim = addr[20:12] < NHART ?int_id_1[addr[20:12]]: 8\'b0;\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:180: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                   : ... In instance plic\n  wire freed = addr_req && sel && !read && addr[21]&&mask[7:4]==4\'b1111&&addr[20:12]<NHART&&enabled[wdata[39:32]][addr[20:12]];\n                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:180: Bit extraction of var[0:0] requires 1 bit index, not 9 bits.\n                                                                   : ... In instance plic\n  wire freed = addr_req && sel && !read && addr[21]&&mask[7:4]==4\'b1111&&addr[20:12]<NHART&&enabled[wdata[39:32]][addr[20:12]];\n                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:190: Bit extraction of array[7:0] requires 3 bit index, not 9 bits.\n                                                                   : ... In instance plic\n     c_rdata = {21\'b0,r_priority_1[addr[11:3]], 32\'b0};\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:192: Bit extraction of array[7:0] requires 3 bit index, not 9 bits.\n                                                                   : ... In instance plic\n     c_rdata = {21\'b0,r_priority_1[addr[11:3]], 21\'b0,r_priority_0[addr[11:3]]};\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/411838135/rv/plic.sv:201: Bit extraction of array[0:0] requires 1 bit index, not 9 bits.\n                                                                   : ... In instance plic\n     c_rdata = {24\'b0,c_claim, 21\'b0,r_threshold[addr[20:12]]};\n                                                ^\n%Error: Exiting due to 12 warning(s)\n'
module plic_slice(
		input		clk,
		input		reset,
		input		lock,
		input		irq,
		input		claimed,
		input		freed,
		output		pending,
		input [NHART-1:0]ie,
		input [10:0]prio,
		input	[10:0]prio_in_0,
		input  [7:0]id_in_0,

		output  [10:0]prio_out_0,
		output  [7:0]id_out_0
		);

	parameter ID=0;
	parameter NHART=1;

	reg r_claim;
	reg r_irq;
	assign pending = r_irq && !r_claim && prio != 0;
	always @(posedge clk) 
	if (reset||claimed) begin
		r_irq <= 0;
	end else
	if (!lock) begin
		r_irq <= irq;
	end

	always @(posedge clk)
	if (reset || freed) begin
		r_claim <= 0;
	end else
	if (claimed) begin
		r_claim <= 1;
	end

	wire [7:0]id_out[0:NHART-1];
	wire [10:0]prio_out[0:NHART-1];
	wire [7:0]id_in[0:NHART-1];
	wire [10:0]prio_in[0:NHART-1];
	assign prio_out_0 = prio_out[0];
	assign id_out_0 = id_out[0];
	assign prio_in[0] = prio_in_0;
	assign id_in[0] = id_in_0;

	genvar H;
	generate

		for (H=0; H < NHART; H=H+1) begin
			wire win = ie[H] && pending  && prio >= prio_in[H];
			assign id_out[H]   = (win ? ID   : id_in[H]);
			assign prio_out[H] = (win ? prio : prio_in[H]);
		end
	endgenerate

endmodule
module plic_slice(
		input		clk,
		input		reset,
		input		lock,
		input		irq,
		input		claimed,
		input		freed,
		output		pending,
		input [NHART-1:0]ie,
		input [10:0]prio,
		input	[10:0]prio_in_0,
		input  [7:0]id_in_0,

		output  [10:0]prio_out_0,
		output  [7:0]id_out_0
		);


	parameter ID=0;
	parameter NHART=1;

	reg r_claim;
	reg r_irq;
	assign pending = r_irq && !r_claim && prio != 0;
	always @(posedge clk) 
	if (reset||claimed) begin
		r_irq <= 0;
	end else
	if (!lock) begin
		r_irq <= irq;
	end

	always @(posedge clk)
	if (reset || freed) begin
		r_claim <= 0;
	end else
	if (claimed) begin
		r_claim <= 1;
	end

	wire [7:0]id_out[0:NHART-1];
	wire [10:0]prio_out[0:NHART-1];
	wire [7:0]id_in[0:NHART-1];
	wire [10:0]prio_in[0:NHART-1];
	assign prio_out_0 = prio_out[0];
	assign id_out_0 = id_out[0];
	assign prio_in[0] = prio_in_0;
	assign id_in[0] = id_in_0;

	genvar H;
	generate

		for (H=0; H < NHART; H=H+1) begin
			wire win = ie[H] && pending  && prio >= prio_in[H];
			assign id_out[H]   = (win ? ID   : id_in[H]);
			assign prio_out[H] = (win ? prio : prio_in[H]);
		end
	endgenerate

endmodule