data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_DL_2_4_encoder.v
data/verilator_xmls/7c351aef-31aa-40f0-b289-85d5e27c5f5b.xml
module bm_DL_2_4_encoder (W, Y, En);
	input [1:0] W;
	input En;
	output [3:0] Y;
	reg [3:0] Y;
	
	always @(W or En)
		case ({En, W})
			3'b100: Y = 4'b1000;
			3'b101: Y = 4'b0100;
			3'b110: Y = 4'b0010;
			3'b111: Y = 4'b0001;
			default: Y = 4'b0000;
		endcase
	
endmodule
module bm_DL_2_4_encoder (W, Y, En);

	input [1:0] W;
	input En;
	output [3:0] Y;
	reg [3:0] Y;
	
	always @(W or En)
		case ({En, W})
			3'b100: Y = 4'b1000;
			3'b101: Y = 4'b0100;
			3'b110: Y = 4'b0010;
			3'b111: Y = 4'b0001;
			default: Y = 4'b0000;
		endcase
	
endmodule