data/full_repos/permissive/439345921/PLL.v
data/verilator_xmls/e13b8272-17f3-4670-a20a-386b348ab6fb.xml
module PLL (
	input  wire clk,
	output wire clk_cpu,
	output wire clk_ram,
	output wire clk_wren,
	output wire clk_srom,
	output wire clk_vga
);

	reg [4:0] count;
	initial begin
		count = 5'd0;
	end
	
	always @(posedge clk) begin
		count <= count + 5'd1;
	end

	assign clk_cpu = count[3];
	assign clk_ram = !count[2];
	assign clk_wren = (count[2] ^ count[3]);

	assign clk_srom = count[0];
	assign clk_vga = count[0];

endmodule
module PLL (
	input  wire clk,
	output wire clk_cpu,
	output wire clk_ram,
	output wire clk_wren,
	output wire clk_srom,
	output wire clk_vga
);


	reg [4:0] count;
	initial begin
		count = 5'd0;
	end
	
	always @(posedge clk) begin
		count <= count + 5'd1;
	end

	assign clk_cpu = count[3];
	assign clk_ram = !count[2];
	assign clk_wren = (count[2] ^ count[3]);

	assign clk_srom = count[0];
	assign clk_vga = count[0];

endmodule