data/full_repos/permissive/472196771/verilog/rtl/src/vram_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472196771/verilog/rtl/src/vram_ctrl.v:30: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'gpu_raster_addr_i\' generates 18 bits.\n                                                                                   : ... In instance vram_ctrl\nassign  vram_addr_o   = gpu_active_i ? gpu_raster_addr_i : wbs_adr_i;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472196771/verilog/rtl/src/vram_ctrl.v:30: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                   : ... In instance vram_ctrl\nassign  vram_addr_o   = gpu_active_i ? gpu_raster_addr_i : wbs_adr_i;\n                      ^\n%Error: Exiting due to 2 warning(s)\n'
module vram_ctrl(
  input         wb_clk_i,
  input         wb_rst_i,
  input         wbs_stb_i,
  input         wbs_cyc_i,
  input         wbs_we_i,
  input [1:0]   wbs_sel_i,
  input [31:0]  wbs_dat_i,
  input [31:0]  wbs_adr_i,
  output reg    wbs_ack_o,

  input         gpu_active_i,
  input         gpu_write_pixel_i,
  input [17:0]  gpu_raster_addr_i,
  input [15:0]  gpu_raster_color_i,

  output        vram_enable_o,
  output [17:0] vram_addr_o,
  output [15:0] vram_data_o,
  output        vram_wr_en_o
);

wire vram_bus_enable = wbs_sel_i == 2'b01;

assign  vram_enable_o = gpu_active_i ? 1'b1 : vram_bus_enable && wbs_stb_i;
assign  vram_addr_o   = gpu_active_i ? gpu_raster_addr_i : wbs_adr_i;
assign  vram_wr_en_o  = gpu_active_i ? gpu_write_pixel_i : vram_bus_enable && wbs_we_i;
assign  vram_data_o   = gpu_active_i ? gpu_raster_color_i : wbs_dat_i[15:0];


always @(posedge wb_clk_i) begin
  if(vram_bus_enable & wbs_stb_i & ~gpu_active_i) begin
    wbs_ack_o <= 1'b1;
  end else begin
    wbs_ack_o <= 1'b0;
  end
end




endmodule
module vram_ctrl(
  input         wb_clk_i,
  input         wb_rst_i,
  input         wbs_stb_i,
  input         wbs_cyc_i,
  input         wbs_we_i,
  input [1:0]   wbs_sel_i,
  input [31:0]  wbs_dat_i,
  input [31:0]  wbs_adr_i,
  output reg    wbs_ack_o,

  input         gpu_active_i,
  input         gpu_write_pixel_i,
  input [17:0]  gpu_raster_addr_i,
  input [15:0]  gpu_raster_color_i,

  output        vram_enable_o,
  output [17:0] vram_addr_o,
  output [15:0] vram_data_o,
  output        vram_wr_en_o
);


wire vram_bus_enable = wbs_sel_i == 2'b01;

assign  vram_enable_o = gpu_active_i ? 1'b1 : vram_bus_enable && wbs_stb_i;
assign  vram_addr_o   = gpu_active_i ? gpu_raster_addr_i : wbs_adr_i;
assign  vram_wr_en_o  = gpu_active_i ? gpu_write_pixel_i : vram_bus_enable && wbs_we_i;
assign  vram_data_o   = gpu_active_i ? gpu_raster_color_i : wbs_dat_i[15:0];


always @(posedge wb_clk_i) begin
  if(vram_bus_enable & wbs_stb_i & ~gpu_active_i) begin
    wbs_ack_o <= 1'b1;
  end else begin
    wbs_ack_o <= 1'b0;
  end
end




endmodule