data/full_repos/permissive/426889244/verilog/MemAddrCalc.v
data/verilator_xmls/9e39ec41-1d2d-4faf-9616-df36987f6aac.xml
module MemAddrCalc (
    input wire[31:0] rs_data,
    input wire[31:0] imm_ext_result,

    output wire[31:0] mem_addr
);
    assign mem_addr = rs_data + imm_ext_result;
endmodule
module MemAddrCalc (
    input wire[31:0] rs_data,
    input wire[31:0] imm_ext_result,

    output wire[31:0] mem_addr
);

    assign mem_addr = rs_data + imm_ext_result;
endmodule