data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/mux21.v
data/verilator_xmls/cf1aa6e0-c4ea-4479-b6d7-718ea968feb0.xml
module mux21 #(
  parameter WIDTH = 32)
(
  input       [WIDTH-1:0] a, b,
  input                   sel,
  output wire [WIDTH-1:0] y
);



assign y = sel ? b : a;

endmodule
module mux21 #(
  parameter WIDTH = 32)
(
  input       [WIDTH-1:0] a, b,
  input                   sel,
  output wire [WIDTH-1:0] y
);




assign y = sel ? b : a;

endmodule