data/full_repos/permissive/513398397/verilog/control.v
data/verilator_xmls/7a31be84-8ae8-4bd5-bc7a-7af51a7eacad.xml
module control(
    output PCsel, RegWEn, BrUn,
    output [2:0] ImmSel, WordSizeSel,
    output BSel, ASel,  MemRW, 
    output [3:0] ALUSel,
    output [1:0] WBSel,
    input  [31:0] instruction, 
    input  BrEq, BrLT
);











wire [8:0] inst_opcode = {instruction[30], instruction[14:12], instruction[6:2]};
wire JAL, JALR;
wire BrJal;
wire BeQ, BnE;
wire BLT, BGE;
wire I_cond, B_cond, U_cond, J_cond, S_cond;
wire AUIPC;
wire ALU_cond_I, ALU_cond_R;
wire RegNWRT;
wire WBMEM_cond, WBp4_cond;
wire SaveLoad;


assign BrJal = (inst_opcode[4:2] == 3'b110);
assign JAL = BrJal & (inst_opcode[1:0] == 2'b11);
assign JALR = BrJal & (inst_opcode[1:0] == 2'b01);
assign BeQ = (inst_opcode[7:5] == 3'b000) & BrJal & (inst_opcode[1:0] == 2'b00);
assign BnE = (inst_opcode[7:5] == 3'b001) & BrJal & (inst_opcode[1:0] == 2'b00);
assign BLT = ({inst_opcode[7], inst_opcode[5]} == 2'b10) & BrJal;
assign BGE = ({inst_opcode[7], inst_opcode[5]} == 2'b11) & BrJal;

assign PCsel = JAL | JALR | (BeQ & BrEq) | (BnE & (~BrEq)) | (BLT & BrLT) | (BGE & (~BrLT));


assign U_cond = {inst_opcode[4], inst_opcode[2:0]} == 4'b0101;
assign J_cond = JAL;
assign B_cond = inst_opcode[4:0] == 5'b11000;
assign S_cond = inst_opcode[4:0] == 5'b01000;
assign I_cond = ({inst_opcode[4:3], inst_opcode[1:0]} == 4'b0000) | JALR;

enc3b ENCODE1(ImmSel, {S_cond, J_cond, U_cond, B_cond, I_cond});


assign BrUn = BrJal & inst_opcode[6];


assign AUIPC = (inst_opcode[4:0] == 5'b00101);
assign ASel = AUIPC | JAL | BeQ | BLT | BGE | BnE;


assign BSel = ~(inst_opcode[4:0] == 5'b01100);


assign ALU_cond_I = (inst_opcode[4:0] == 5'b00100);
assign ALU_cond_R = (inst_opcode[4:0] == 5'b01100);
assign ALUSel = ALU_cond_R ? inst_opcode[8 -: 4] : ((ALU_cond_I) ? {1'b0, inst_opcode[7:5]} : 4'b0);


assign MemRW = (inst_opcode[4:0] == 5'b01000);


assign RegNWRT = (inst_opcode[3:0] == 4'b1000);
assign RegWEn = RegNWRT ? 1'b0 : 1'b1;


assign WBMEM_cond = (inst_opcode[4:0] == 5'b00000);
assign WBp4_cond  = JAL | JALR;
assign WBSel = WBp4_cond ? 2'b10 : ((WBMEM_cond) ? 2'b00: 2'b01);


assign SaveLoad = {inst_opcode[4], inst_opcode[2:0]} == 4'b0000;
assign WordSizeSel = (SaveLoad) ? inst_opcode[7:5] : 3'b010;

endmodule
module control(
    output PCsel, RegWEn, BrUn,
    output [2:0] ImmSel, WordSizeSel,
    output BSel, ASel,  MemRW, 
    output [3:0] ALUSel,
    output [1:0] WBSel,
    input  [31:0] instruction, 
    input  BrEq, BrLT
);












wire [8:0] inst_opcode = {instruction[30], instruction[14:12], instruction[6:2]};
wire JAL, JALR;
wire BrJal;
wire BeQ, BnE;
wire BLT, BGE;
wire I_cond, B_cond, U_cond, J_cond, S_cond;
wire AUIPC;
wire ALU_cond_I, ALU_cond_R;
wire RegNWRT;
wire WBMEM_cond, WBp4_cond;
wire SaveLoad;


assign BrJal = (inst_opcode[4:2] == 3'b110);
assign JAL = BrJal & (inst_opcode[1:0] == 2'b11);
assign JALR = BrJal & (inst_opcode[1:0] == 2'b01);
assign BeQ = (inst_opcode[7:5] == 3'b000) & BrJal & (inst_opcode[1:0] == 2'b00);
assign BnE = (inst_opcode[7:5] == 3'b001) & BrJal & (inst_opcode[1:0] == 2'b00);
assign BLT = ({inst_opcode[7], inst_opcode[5]} == 2'b10) & BrJal;
assign BGE = ({inst_opcode[7], inst_opcode[5]} == 2'b11) & BrJal;

assign PCsel = JAL | JALR | (BeQ & BrEq) | (BnE & (~BrEq)) | (BLT & BrLT) | (BGE & (~BrLT));


assign U_cond = {inst_opcode[4], inst_opcode[2:0]} == 4'b0101;
assign J_cond = JAL;
assign B_cond = inst_opcode[4:0] == 5'b11000;
assign S_cond = inst_opcode[4:0] == 5'b01000;
assign I_cond = ({inst_opcode[4:3], inst_opcode[1:0]} == 4'b0000) | JALR;

enc3b ENCODE1(ImmSel, {S_cond, J_cond, U_cond, B_cond, I_cond});


assign BrUn = BrJal & inst_opcode[6];


assign AUIPC = (inst_opcode[4:0] == 5'b00101);
assign ASel = AUIPC | JAL | BeQ | BLT | BGE | BnE;


assign BSel = ~(inst_opcode[4:0] == 5'b01100);


assign ALU_cond_I = (inst_opcode[4:0] == 5'b00100);
assign ALU_cond_R = (inst_opcode[4:0] == 5'b01100);
assign ALUSel = ALU_cond_R ? inst_opcode[8 -: 4] : ((ALU_cond_I) ? {1'b0, inst_opcode[7:5]} : 4'b0);


assign MemRW = (inst_opcode[4:0] == 5'b01000);


assign RegNWRT = (inst_opcode[3:0] == 4'b1000);
assign RegWEn = RegNWRT ? 1'b0 : 1'b1;


assign WBMEM_cond = (inst_opcode[4:0] == 5'b00000);
assign WBp4_cond  = JAL | JALR;
assign WBSel = WBp4_cond ? 2'b10 : ((WBMEM_cond) ? 2'b00: 2'b01);


assign SaveLoad = {inst_opcode[4], inst_opcode[2:0]} == 4'b0000;
assign WordSizeSel = (SaveLoad) ? inst_opcode[7:5] : 3'b010;

endmodule