data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:43: Unsupported: Ignoring delay on this delayed statement.\nalways #5 i_clk = ~i_clk ;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #10 i_addr = 5\'b00000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #10  i_addr = 5\'b00001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #10 i_addr = 5\'b00010;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10  i_addr = 5\'b00011;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n     #10 i_addr = 5\'b00100;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10  i_addr = 5\'b00101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #10 i_addr = 5\'b00110;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #10  i_addr = 5\'b00111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n     #40;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n       #10 i_data = 32\'d45;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n       #10 i_data = 32\'d55; \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n       #14 i_data = 32\'d560;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n       #14 i_data = 32\'d567;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #2  i_read = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #300 $stop ;\n        ^\n%Error: data/full_repos/permissive/507506290/RTL_Files/data_memory_test.v:33: Cannot find file containing module: \'DATA_MEM\'\nDATA_MEM DUT(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/DATA_MEM\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/DATA_MEM.v\n             data/full_repos/permissive/507506290/RTL_Files,data/full_repos/permissive/507506290/DATA_MEM.sv\n             DATA_MEM\n             DATA_MEM.v\n             DATA_MEM.sv\n             obj_dir/DATA_MEM\n             obj_dir/DATA_MEM.v\n             obj_dir/DATA_MEM.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_memory_test();
reg i_clk , i_rst_n , i_write , i_read ;
reg [`ADDR_WIDTH-1:0] i_addr ;
reg [`D_WIDTH-1:0] i_data ;
wire [`D_WIDTH-1:0] o_data ;



DATA_MEM DUT(
 i_clk ,
 i_rst_n , 
 i_addr , 
 i_write , 
 i_data , 
 i_read, 
 o_data);


always #5 i_clk = ~i_clk ;

initial
  begin
   i_clk = 1'b0;
   i_rst_n = 1'b0;
   end
   

 initial
   begin
   #10 i_addr = 5'b00000;
    #10  i_addr = 5'b00001;
   #10 i_addr = 5'b00010;
    #10  i_addr = 5'b00011;
     #10 i_addr = 5'b00100;
    #10  i_addr = 5'b00101;
   #10 i_addr = 5'b00110;
    #10  i_addr = 5'b00111;
   end
   
   
   initial
    begin
     i_rst_n = 1'b1 ;
     #40;
     end 
     
     
   initial
      begin
       #10 i_data = 32'd45;
          i_write = 1'b1;
          i_read = 1'b1;
       #10 i_data = 32'd55; 
          i_write = 1'b1 ;
          i_read = 1'b0;
       #14 i_data = 32'd560;
           i_write = 1'b1 ;
           i_read = 1'b1;
       #14 i_data = 32'd567;
          i_write = 1'b1;
        #2  i_read = 1'b1;
        #300 $stop ;
        end
                    

endmodule
module data_memory_test();

reg i_clk , i_rst_n , i_write , i_read ;
reg [`ADDR_WIDTH-1:0] i_addr ;
reg [`D_WIDTH-1:0] i_data ;
wire [`D_WIDTH-1:0] o_data ;



DATA_MEM DUT(
 i_clk ,
 i_rst_n , 
 i_addr , 
 i_write , 
 i_data , 
 i_read, 
 o_data);


always #5 i_clk = ~i_clk ;

initial
  begin
   i_clk = 1'b0;
   i_rst_n = 1'b0;
   end
   

 initial
   begin
   #10 i_addr = 5'b00000;
    #10  i_addr = 5'b00001;
   #10 i_addr = 5'b00010;
    #10  i_addr = 5'b00011;
     #10 i_addr = 5'b00100;
    #10  i_addr = 5'b00101;
   #10 i_addr = 5'b00110;
    #10  i_addr = 5'b00111;
   end
   
   
   initial
    begin
     i_rst_n = 1'b1 ;
     #40;
     end 
     
     
   initial
      begin
       #10 i_data = 32'd45;
          i_write = 1'b1;
          i_read = 1'b1;
       #10 i_data = 32'd55; 
          i_write = 1'b1 ;
          i_read = 1'b0;
       #14 i_data = 32'd560;
           i_write = 1'b1 ;
           i_read = 1'b1;
       #14 i_data = 32'd567;
          i_write = 1'b1;
        #2  i_read = 1'b1;
        #300 $stop ;
        end
                    

endmodule