data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v:282: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'manager\'\nmodule manager(\n       ^~~~~~~\n                                                                                             : ... Top module \'uiconv\'\nmodule uiconv(\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v:165: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n                                                                                          : ... In instance manager\n    addr = {n, 1\'d0};\n         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v:171: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n                                                                                          : ... In instance manager\n     addr = {n, 1\'d1};\n          ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v:239: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                          : ... In instance manager\n      if(mrelY[3:1] == 2\'b0) colors1 = fromRAM;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/SpriteManager.v:269: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                          : ... In instance manager\n  addr = {1\'b1,uiin,ccy[3:2]};\n       ^\n%Error: Exiting due to 5 warning(s)\n'
module uiconv(
	input clk,
	input dclk,
	input rst,
	
	input[9:0] cx,
	input[8:0] cy,
	
	input[31:0] fromRAM,
	
	output reg[1:0] uicol

);

reg[1:0] tim;
reg[1:0] f_tim;

reg[1:0] f_uicol;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		f_uicol <= 0;
	end else
	begin
		f_tim <= tim;
		f_uicol <= uicol;
	end
end


always@(*)begin
	tim = f_tim +1;
	uicol = f_uicol;

	
	if(cx[9:6] != 0) begin
	
		if(tim == 1) begin
			if(~cy[1])begin
				case(cx[3:1])
					
					2: uicol = fromRAM[31:30];
					3: uicol = fromRAM[29:28];
					4: uicol = fromRAM[27:26];
					5: uicol = fromRAM[25:24];
					6: uicol = fromRAM[23:22];
					7: uicol = fromRAM[21:20];
					0: uicol = fromRAM[19:18];
					1: uicol = fromRAM[17:16];
					default: uicol =0;
				endcase
			end else
			begin
				case(cx[3:1])
					
					2: uicol = fromRAM[15:14];
					3: uicol = fromRAM[13:12];
					4: uicol = fromRAM[11:10];
					5: uicol = fromRAM[9:8];
					6: uicol = fromRAM[7:6];
					7: uicol = fromRAM[5:4];
					0: uicol = fromRAM[3:2];
					1: uicol = fromRAM[1:0];
					default: uicol =0;
				endcase
			end
		end 
	end else
	begin
		uicol = 0;
	end
end

endmodule
module uiconv(
	input clk,
	input dclk,
	input rst,
	
	input[9:0] cx,
	input[8:0] cy,
	
	input[31:0] fromRAM,
	
	output reg[1:0] uicol

);


reg[1:0] tim;
reg[1:0] f_tim;

reg[1:0] f_uicol;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		f_uicol <= 0;
	end else
	begin
		f_tim <= tim;
		f_uicol <= uicol;
	end
end


always@(*)begin
	tim = f_tim +1;
	uicol = f_uicol;

	
	if(cx[9:6] != 0) begin
	
		if(tim == 1) begin
			if(~cy[1])begin
				case(cx[3:1])
					
					2: uicol = fromRAM[31:30];
					3: uicol = fromRAM[29:28];
					4: uicol = fromRAM[27:26];
					5: uicol = fromRAM[25:24];
					6: uicol = fromRAM[23:22];
					7: uicol = fromRAM[21:20];
					0: uicol = fromRAM[19:18];
					1: uicol = fromRAM[17:16];
					default: uicol =0;
				endcase
			end else
			begin
				case(cx[3:1])
					
					2: uicol = fromRAM[15:14];
					3: uicol = fromRAM[13:12];
					4: uicol = fromRAM[11:10];
					5: uicol = fromRAM[9:8];
					6: uicol = fromRAM[7:6];
					7: uicol = fromRAM[5:4];
					0: uicol = fromRAM[3:2];
					1: uicol = fromRAM[1:0];
					default: uicol =0;
				endcase
			end
		end 
	end else
	begin
		uicol = 0;
	end
end

endmodule