data/full_repos/permissive/435170935/001-fulladder/fulladder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435170935/001-fulladder/fulladder.v:27: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'c_in\' generates 1 bits.\n                                                                                 : ... In instance fulladder\n    assign { c_out, sum } = a + b + c_in;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module fulladder #(
    parameter width = 2
) (
    input [width:0] a,
    input [width:0] b,
    input c_in,
    output c_out,
    output [width:0] sum
);

    assign { c_out, sum } = a + b + c_in;

endmodule
module fulladder #(
    parameter width = 2
) (
    input [width:0] a,
    input [width:0] b,
    input c_in,
    output c_out,
    output [width:0] sum
);


    assign { c_out, sum } = a + b + c_in;

endmodule