data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:640: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_nec_ir_receiver_registers\n              wbs_dat_o[31:0]  <= 31\'b0;\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:253: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_pulse_filter\n      filter_reg <= 1\'b0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:257: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_pulse_filter\n          filter_reg <= 1\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:219: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance nec_ir_receiver.i_metastability_filter\n      meta_i <= 1\'b0;\n             ^~\n%Error: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:71: Cannot find file containing module: \'prescaler\'\n  prescaler #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.v\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: data/full_repos/permissive/468755927/verilog/rtl/nec_ir_receiver.v:144: Cannot find file containing module: \'simple_fifo\'\n  simple_fifo #(\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module event_catcher #(
  parameter DBITS = 32
)(
  input  wire             rst_n         ,
  input  wire             clk           ,
  input  wire             clear_n       ,
  input  wire [DBITS-1:0] reload_offset ,

  input  wire             i_value       ,
  input  wire             i_valid       ,

  output reg              event_new     ,
  output reg              event_type    ,
  output reg  [DBITS-1:0] event_delay   ,
  output reg              event_timeout
);

  wire detect_event;
  wire [DBITS-1:0] next_cnt;
  wire full_cnt;

  reg last_value;
  reg [DBITS-1:0] cnt;

  assign detect_event = (i_value != last_value);
  assign next_cnt     = cnt + 1'b1;
  assign full_cnt     = (cnt == {DBITS{1'b1}});


  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      last_value    <= 1'b0;
      cnt           <= {DBITS{1'b1}};
      event_new     <= 1'b0;
      event_type    <= 1'b0;
      event_delay   <= {DBITS{1'b0}};
      event_timeout <= 1'b0;
    end else begin

    if (clear_n == 1'b0) begin
        last_value    <= 1'b0;
        cnt           <= {DBITS{1'b1}};
        event_new     <= 1'b0;
        event_type    <= 1'b0;
        event_delay   <= {DBITS{1'b0}};
        event_timeout <= 1'b0;
    end else begin

        if (i_valid == 1'b1) begin


          last_value <= i_value;


          if (detect_event == 1'b1) begin
            cnt <= reload_offset;
          end else if (!full_cnt) begin
            cnt <= next_cnt;
          end
        end


        if ((i_valid == 1'b1) && (detect_event == 1'b1)) begin
          event_new     <= 1'b1;
          event_type    <= i_value;
          event_delay   <= next_cnt;
          event_timeout <= full_cnt;
        end else begin
          event_new     <= 1'b0;
        end

    end

    end
  end

endmodule
module event_catcher #(
  parameter DBITS = 32
)(
  input  wire             rst_n         ,
  input  wire             clk           ,
  input  wire             clear_n       ,
  input  wire [DBITS-1:0] reload_offset ,

  input  wire             i_value       ,
  input  wire             i_valid       ,

  output reg              event_new     ,
  output reg              event_type    ,
  output reg  [DBITS-1:0] event_delay   ,
  output reg              event_timeout
);


  wire detect_event;
  wire [DBITS-1:0] next_cnt;
  wire full_cnt;

  reg last_value;
  reg [DBITS-1:0] cnt;

  assign detect_event = (i_value != last_value);
  assign next_cnt     = cnt + 1'b1;
  assign full_cnt     = (cnt == {DBITS{1'b1}});


  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      last_value    <= 1'b0;
      cnt           <= {DBITS{1'b1}};
      event_new     <= 1'b0;
      event_type    <= 1'b0;
      event_delay   <= {DBITS{1'b0}};
      event_timeout <= 1'b0;
    end else begin

    if (clear_n == 1'b0) begin
        last_value    <= 1'b0;
        cnt           <= {DBITS{1'b1}};
        event_new     <= 1'b0;
        event_type    <= 1'b0;
        event_delay   <= {DBITS{1'b0}};
        event_timeout <= 1'b0;
    end else begin

        if (i_valid == 1'b1) begin


          last_value <= i_value;


          if (detect_event == 1'b1) begin
            cnt <= reload_offset;
          end else if (!full_cnt) begin
            cnt <= next_cnt;
          end
        end


        if ((i_valid == 1'b1) && (detect_event == 1'b1)) begin
          event_new     <= 1'b1;
          event_type    <= i_value;
          event_delay   <= next_cnt;
          event_timeout <= full_cnt;
        end else begin
          event_new     <= 1'b0;
        end

    end

    end
  end

endmodule