data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v
1: b'%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:2: Cannot find include file: Parameter.v\n`include "Parameter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v.v\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v.sv\n             Parameter.v\n             Parameter.v.v\n             Parameter.v.sv\n             obj_dir/Parameter.v\n             obj_dir/Parameter.v.v\n             obj_dir/Parameter.v.sv\n%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:3: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:4: Cannot find include file: Risc_16_bit.v\n`include "Risc_16_bit.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test_Risc_16_bit.vcd");  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test_Risc_16_bit);     \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:31: Define or directive not defined: \'`simulation_time\'\n    `simulation_time;\n    ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/433336136/16bit_risc/test_Risc_16_bit.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module test_Risc_16_bit;


reg clk;


Risc_16_bit uut (
                .clk(clk)
            );


initial
begin
    $dumpfile("test_Risc_16_bit.vcd");
    $dumpvars(0, test_Risc_16_bit);
end



initial
begin
    clk <=0;
    `simulation_time;
    $finish;
end

always
begin
    #5 clk = ~clk;
end

endmodule
module test_Risc_16_bit;



reg clk;


Risc_16_bit uut (
                .clk(clk)
            );


initial
begin
    $dumpfile("test_Risc_16_bit.vcd");
    $dumpvars(0, test_Risc_16_bit);
end



initial
begin
    clk <=0;
    `simulation_time;
    $finish;
end

always
begin
    #5 clk = ~clk;
end

endmodule