data/full_repos/permissive/515445239/shift_register.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515445239/shift_register.v:22: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'sel\' generates 2 bits.\n                                                                        : ... In instance shift_reg\n           case (sel)\n           ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module shift_reg(op,clk,rst, load,sel,ip);
  output reg [3:0] op;
  input load;
  input [1:0] sel;
  input [3:0] ip;
  input clk, rst;
  
  always @(posedge clk or posedge rst)
   begin
     if (rst)
       
       op = 0;
      
     else    
       case(load)
         1'b1: 
          begin
            op = ip;
          end
          
         1'b0:
           case (sel)
            3'b000:  op = op<<1;
            3'b001:  op = op>>1;
            3'b010:  op = {op[2:0],op[3]};
            3'b011:  op = {op[0], op[3:1]};
          endcase                                     
       endcase
   
   end 
    
  endmodule
module shift_reg(op,clk,rst, load,sel,ip);

  output reg [3:0] op;
  input load;
  input [1:0] sel;
  input [3:0] ip;
  input clk, rst;
  
  always @(posedge clk or posedge rst)
   begin
     if (rst)
       
       op = 0;
      
     else    
       case(load)
         1'b1: 
          begin
            op = ip;
          end
          
         1'b0:
           case (sel)
            3'b000:  op = op<<1;
            3'b001:  op = op>>1;
            3'b010:  op = {op[2:0],op[3]};
            3'b011:  op = {op[0], op[3:1]};
          endcase                                     
       endcase
   
   end 
    
  endmodule