data/full_repos/permissive/434837003/test/generate.v
1: b"%Error: data/full_repos/permissive/434837003/test/generate.v:20: syntax error, unexpected bit, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nfor (i=0; i<SIZE; i=i+1) begin : bit\n                                 ^~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:57: syntax error, unexpected bit, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nfor(i=0; i<SIZE; i=i+1) begin:bit\n                              ^~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:164: syntax error, unexpected byte, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n        for (i=0; i<8; i=i+1) begin:byte\n                                    ^~~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:178: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\n            byte[7].p.read_mem(address, data[63:56]);\n                ^\n%Error: Exiting due to 4 error(s)\n"
module addergen1 (co, sum, a, b, ci);

parameter SIZE = 4;

output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;

wire [SIZE :0] c;
wire [SIZE-1:0] t [1:3];

genvar i;

assign c[0] = ci;











for(i=0; i<SIZE; i=i+1) begin:bit
    xor g1 (t[1][i], a[i], b[i]);
    xor g2 (sum[i], t[1][i], c[i]);
    and g3 (t[2][i], a[i], b[i]);
    and g4 (t[3][i], t[1][i], c[i]);
    or g5 (c[i+1], t[2][i], t[3][i]);
end

assign co = c[SIZE];

endmodule
module addergen1 (co, sum, a, b, ci);


parameter SIZE = 4;

output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;

wire [SIZE :0] c;
wire [SIZE-1:0] t [1:3];

genvar i;

assign c[0] = ci;











for(i=0; i<SIZE; i=i+1) begin:bit
    xor g1 (t[1][i], a[i], b[i]);
    xor g2 (sum[i], t[1][i], c[i]);
    and g3 (t[2][i], a[i], b[i]);
    and g4 (t[3][i], t[1][i], c[i]);
    or g5 (c[i+1], t[2][i], t[3][i]);
end

assign co = c[SIZE];

endmodule