data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                          : ... In instance top\n0 : data = 'h4;\n    ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\n1 : data = 'h9;\n    ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\n2 : data = 'h1;\n    ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\n15 : data = 'h8;\n     ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\n16 : data = 'h1;\n     ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:14: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\n17 : data = 'h0;\n     ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/441359809/src/yosys/tests/arch/ecp5/rom.v:15: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data'\n                                                                                           : ... In instance top\ndefault : data = 'h0;\n          ^~~~\n%Error: Exiting due to 7 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top(data, addr);
output [3:0] data;
input [4:0] addr;
always @(addr) begin
case (addr)
0 : data = 'h4;
1 : data = 'h9;
2 : data = 'h1;
15 : data = 'h8;
16 : data = 'h1;
17 : data = 'h0;
default : data = 'h0;
endcase
end
endmodule
module top(data, addr);

output [3:0] data;
input [4:0] addr;
always @(addr) begin
case (addr)
0 : data = 'h4;
1 : data = 'h9;
2 : data = 'h1;
15 : data = 'h8;
16 : data = 'h1;
17 : data = 'h0;
default : data = 'h0;
endcase
end
endmodule