data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:236: Signal definition not found, creating implicitly: \'mprs\'\nassign           mprs = prors;\n                 ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:237: Signal definition not found, creating implicitly: \'mpvld\'\n                                                                                                                                          : ... Suggested alternative: \'vld\'\nassign           mpvld = provld;\n                 ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:128: Operator EQ expects 3 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                                                                       : ... In instance aluwrap\n        recc <= (opcode[1:0] == INV)? 256\'d1 :\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:236: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'prors\' generates 256 bits.\n                                                                                                                                       : ... In instance aluwrap\nassign           mprs = prors;\n                      ^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:377: Cannot find file containing module: \'modfa\'\nmodfa imodfa\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/modfa\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/modfa.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/modfa.sv\n             modfa\n             modfa.v\n             modfa.sv\n             obj_dir/modfa\n             obj_dir/modfa.v\n             obj_dir/modfa.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:391: Cannot find file containing module: \'montprowrap\'\nmontprowrap imontprowrap\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:406: Cannot find file containing module: \'montinv\'\nmontinv imontinv\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/aluwrap.v:418: Cannot find file containing module: \'cswap\'\ncswap icswap\n^~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module aluwrap
    (
     clk,
     rst,

     status,

     a,
     b,
     c,
     en,
     swapop,
     swapvl,
     opcode,



     r,
     rswap,
     vld
     );



parameter WID  = 256;
parameter IDLE = 3'b000;
parameter FA   = 3'b001;
parameter INV  = 3'b010;
parameter MUL  = 3'b011;
parameter NOR  = 3'b100;
parameter EXP  = 3'b101;
parameter SWAP = 3'b110;
parameter MVALP256 = 256'd115792089210356248762697446949407573530086143415290314195533631308867097853951;
parameter RPVLP256 = 256'd134799733323198995502561713907086292154532538166959272814710328655875;
parameter RNVLP256 = 256'd46533765739406314298121036767150998762426774378559716911348521029833835802274;
parameter NVALP256 = 256'd115792089210356248762697446949407573529996955224135760342422259061068512044369;
parameter MVALX255 = 256'd57896044618658097711785492504343953926634992332820282019728792003956564819949;
parameter RPVLX255 = 256'd1444;
parameter RNVLX255 = 256'd1627715501170711445284395025044413883736156588369414752970002579683115011841;
parameter NVALX255 = 256'd7237005577332262213973186563042994240857116359379907606001950938285454250989;

parameter P256EXPK  = 256'd26959946660873538059280334323183841250350249843923952699046031785985;
parameter P256EXP2K = 256'd134799733323198995502561713907086292154532538166959272814710328655875;
parameter X255EXPK  = 256'd38;
parameter X255EXP2K = 256'd1444;




input clk;
input rst;

output [1:0] status;

input [WID-1:0] a;
input [WID-1:0] b;
input           c;
input           swapop;
input           swapvl;
input           en;
input [3:0] opcode;
                
output [WID-1:0] r;
output [WID-1:0] rswap;
output           vld;








reg [WID-1:0]    tempnor;
reg [2:0]        state;
wire             isidle,isinv,ismul,isfa,isnor,isswap;


wire             enidle;

assign           enidle = isidle & en;




reg [WID-1:0]   mecc;
always@(posedge clk)
    begin
    if(enidle)
        mecc <= (opcode[3:2] == 2'b00)? MVALP256 :
                (opcode[3:2] == 2'b01)? MVALX255 :
                (opcode[3:2] == 2'b10)? NVALP256 :
                NVALX255;
    end

reg [WID-1:0] recc;

always@(posedge clk)
    begin
    if(enidle)
        recc <= (opcode[1:0] == INV)? 256'd1 :
                (opcode[3:2] == 2'b00)? RPVLP256 :
                (opcode[3:2] == 2'b01)? RPVLX255 :
                (opcode[3:2] == 2'b10)? RNVLP256 :
                RNVLX255;

    end







reg [WID-1:0] areg;
reg [WID-1:0] breg;

always@(posedge clk)
    begin
    if(rst)
        begin
        areg <= 256'd0;
        end
    else
        begin
        if(enidle)
            begin
            areg <= a;
            end
        end
    end

always@(posedge clk)
    begin
    if(rst)
        begin
        breg <= 256'd0;
        end
    else
        begin
        if(enidle)
            begin
            breg <= b;
            end
        end
    end




wire [WID-1:0]   fars;
wire             favld;


wire [WID-1:0]   prors;
wire             provld;
wire [WID-1:0]   proa;
wire [WID-1:0]   prob;



wire [WID-1:0]   invrs;
wire             invvld;


wire [WID-1:0]   swaprsa;
wire [WID-1:0]   swaprsb;
wire             swapvld;






reg              faen;
reg              proen;
reg              inven;

reg              swapen;

assign           mprs = prors;
assign           mpvld = provld;



assign           proa =
                 isnor? tempnor : areg;
assign           prob =
                 isnor? recc : breg;







assign           isidle = state == IDLE;
assign           isinv = state == INV;
assign           ismul = state == MUL;
assign           isfa = state == FA;
assign           isnor = state == NOR;
assign           isswap = state == SWAP;


wire             isfavld;
wire             isnorvld;
wire             isswapvld;


assign           isfavld = (isfa & favld);
assign           isnorvld = (isnor & provld);
assign           isswapvld = (isswap & swapvld);



wire             norcond;

assign           norcond = (ismul & provld) | (isinv & invvld);



assign           vld = isfavld | isnorvld | isswapvld;


assign status = isidle? 2'b00 :
       vld? 2'b10 : 2'b01;


assign r = isfavld? fars :
       isswapvld? swaprsa:

       prors;

assign rswap = swaprsb;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        tempnor <= 0;
        faen <= 1'b0;
        proen <= 1'b0;
        inven <= 1'b0;

        swapen <= 1'b0;
        end
    else
        begin
        if(enidle)
            begin
            if(swapop)
                begin
                state <= SWAP;
                swapen <= 1'b1;
                end
            else
                begin
                case(opcode[1:0])
                    2'b00:
                        begin
                        state <= FA;
                        faen <= 1'b1;
                        end
                    2'b01:
                        begin
                        state <= MUL;
                        proen <= 1'b1;
                        end
                    2'b10:
                        begin
                        state <= INV;
                        inven <= 1'b1;
                        end





                    default:
                        begin
                        state <= IDLE;
                        end
                endcase
                end
            end
        else if(norcond)
            begin
            tempnor <= provld? prors : invrs;
            state <= NOR;
            proen <= 1'b1;
            end
        else if(isfavld)
            begin
            state <= IDLE;
            end
        else if(isnorvld)
            begin
            state <= IDLE;
            end




        else if(isswapvld)
            begin
            state <= IDLE;
            end
        else
            begin
            state <= state;
            faen <= 1'b0;
            proen <= 1'b0;
            inven <= 1'b0;

            swapen <= 1'b0;
            end
        end
    end
            

modfa imodfa
    (
     .clk(clk),
     .rst(rst),
     .op1(areg),
     .op2(breg),
     .mod(mecc),
     .cin(c),
     .en(faen),
     .sum(fars),
     .vld(favld)
     );


montprowrap imontprowrap
    (
     .clk(clk),
     .rst(rst),
     
     .a(proa),
     .b(prob),
     .m(mecc),
     .r(prors),
     
     .start(proen),
     .vld(provld)
     );


montinv imontinv
    (
     .clk(clk),
     .rst(rst),
     .din(areg),
     .mod(mecc),
     .en(inven),
     .inv(invrs),
     .vld(invvld)
     );


cswap icswap
    (
     .clk(clk),
     .rst(rst),

     .swap(swapvl),
     .a(areg),
     .b(breg),
     .en(swapen),

     .aswap(swaprsa),
     .bswap(swaprsb),
     .vld(swapvld)
     );

endmodule
module aluwrap
    (
     clk,
     rst,

     status,

     a,
     b,
     c,
     en,
     swapop,
     swapvl,
     opcode,



     r,
     rswap,
     vld
     );




parameter WID  = 256;
parameter IDLE = 3'b000;
parameter FA   = 3'b001;
parameter INV  = 3'b010;
parameter MUL  = 3'b011;
parameter NOR  = 3'b100;
parameter EXP  = 3'b101;
parameter SWAP = 3'b110;
parameter MVALP256 = 256'd115792089210356248762697446949407573530086143415290314195533631308867097853951;
parameter RPVLP256 = 256'd134799733323198995502561713907086292154532538166959272814710328655875;
parameter RNVLP256 = 256'd46533765739406314298121036767150998762426774378559716911348521029833835802274;
parameter NVALP256 = 256'd115792089210356248762697446949407573529996955224135760342422259061068512044369;
parameter MVALX255 = 256'd57896044618658097711785492504343953926634992332820282019728792003956564819949;
parameter RPVLX255 = 256'd1444;
parameter RNVLX255 = 256'd1627715501170711445284395025044413883736156588369414752970002579683115011841;
parameter NVALX255 = 256'd7237005577332262213973186563042994240857116359379907606001950938285454250989;

parameter P256EXPK  = 256'd26959946660873538059280334323183841250350249843923952699046031785985;
parameter P256EXP2K = 256'd134799733323198995502561713907086292154532538166959272814710328655875;
parameter X255EXPK  = 256'd38;
parameter X255EXP2K = 256'd1444;




input clk;
input rst;

output [1:0] status;

input [WID-1:0] a;
input [WID-1:0] b;
input           c;
input           swapop;
input           swapvl;
input           en;
input [3:0] opcode;
                
output [WID-1:0] r;
output [WID-1:0] rswap;
output           vld;








reg [WID-1:0]    tempnor;
reg [2:0]        state;
wire             isidle,isinv,ismul,isfa,isnor,isswap;


wire             enidle;

assign           enidle = isidle & en;




reg [WID-1:0]   mecc;
always@(posedge clk)
    begin
    if(enidle)
        mecc <= (opcode[3:2] == 2'b00)? MVALP256 :
                (opcode[3:2] == 2'b01)? MVALX255 :
                (opcode[3:2] == 2'b10)? NVALP256 :
                NVALX255;
    end

reg [WID-1:0] recc;

always@(posedge clk)
    begin
    if(enidle)
        recc <= (opcode[1:0] == INV)? 256'd1 :
                (opcode[3:2] == 2'b00)? RPVLP256 :
                (opcode[3:2] == 2'b01)? RPVLX255 :
                (opcode[3:2] == 2'b10)? RNVLP256 :
                RNVLX255;

    end







reg [WID-1:0] areg;
reg [WID-1:0] breg;

always@(posedge clk)
    begin
    if(rst)
        begin
        areg <= 256'd0;
        end
    else
        begin
        if(enidle)
            begin
            areg <= a;
            end
        end
    end

always@(posedge clk)
    begin
    if(rst)
        begin
        breg <= 256'd0;
        end
    else
        begin
        if(enidle)
            begin
            breg <= b;
            end
        end
    end




wire [WID-1:0]   fars;
wire             favld;


wire [WID-1:0]   prors;
wire             provld;
wire [WID-1:0]   proa;
wire [WID-1:0]   prob;



wire [WID-1:0]   invrs;
wire             invvld;


wire [WID-1:0]   swaprsa;
wire [WID-1:0]   swaprsb;
wire             swapvld;






reg              faen;
reg              proen;
reg              inven;

reg              swapen;

assign           mprs = prors;
assign           mpvld = provld;



assign           proa =
                 isnor? tempnor : areg;
assign           prob =
                 isnor? recc : breg;







assign           isidle = state == IDLE;
assign           isinv = state == INV;
assign           ismul = state == MUL;
assign           isfa = state == FA;
assign           isnor = state == NOR;
assign           isswap = state == SWAP;


wire             isfavld;
wire             isnorvld;
wire             isswapvld;


assign           isfavld = (isfa & favld);
assign           isnorvld = (isnor & provld);
assign           isswapvld = (isswap & swapvld);



wire             norcond;

assign           norcond = (ismul & provld) | (isinv & invvld);



assign           vld = isfavld | isnorvld | isswapvld;


assign status = isidle? 2'b00 :
       vld? 2'b10 : 2'b01;


assign r = isfavld? fars :
       isswapvld? swaprsa:

       prors;

assign rswap = swaprsb;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        tempnor <= 0;
        faen <= 1'b0;
        proen <= 1'b0;
        inven <= 1'b0;

        swapen <= 1'b0;
        end
    else
        begin
        if(enidle)
            begin
            if(swapop)
                begin
                state <= SWAP;
                swapen <= 1'b1;
                end
            else
                begin
                case(opcode[1:0])
                    2'b00:
                        begin
                        state <= FA;
                        faen <= 1'b1;
                        end
                    2'b01:
                        begin
                        state <= MUL;
                        proen <= 1'b1;
                        end
                    2'b10:
                        begin
                        state <= INV;
                        inven <= 1'b1;
                        end





                    default:
                        begin
                        state <= IDLE;
                        end
                endcase
                end
            end
        else if(norcond)
            begin
            tempnor <= provld? prors : invrs;
            state <= NOR;
            proen <= 1'b1;
            end
        else if(isfavld)
            begin
            state <= IDLE;
            end
        else if(isnorvld)
            begin
            state <= IDLE;
            end




        else if(isswapvld)
            begin
            state <= IDLE;
            end
        else
            begin
            state <= state;
            faen <= 1'b0;
            proen <= 1'b0;
            inven <= 1'b0;

            swapen <= 1'b0;
            end
        end
    end
            

modfa imodfa
    (
     .clk(clk),
     .rst(rst),
     .op1(areg),
     .op2(breg),
     .mod(mecc),
     .cin(c),
     .en(faen),
     .sum(fars),
     .vld(favld)
     );


montprowrap imontprowrap
    (
     .clk(clk),
     .rst(rst),
     
     .a(proa),
     .b(prob),
     .m(mecc),
     .r(prors),
     
     .start(proen),
     .vld(provld)
     );


montinv imontinv
    (
     .clk(clk),
     .rst(rst),
     .din(areg),
     .mod(mecc),
     .en(inven),
     .inv(invrs),
     .vld(invvld)
     );


cswap icswap
    (
     .clk(clk),
     .rst(rst),

     .swap(swapvl),
     .a(areg),
     .b(breg),
     .en(swapen),

     .aswap(swaprsa),
     .bswap(swaprsb),
     .vld(swapvld)
     );

endmodule