data/full_repos/permissive/492462267/ex_mem.v
1: b'%Error: data/full_repos/permissive/492462267/ex_mem.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/ex_mem.v:13: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   ex_result,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegDataBus]   ex_result,\n                            ^\n%Error: data/full_repos/permissive/492462267/ex_mem.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]   ex_waddr,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:15: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   ex_waddr,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:16: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   ex_hi,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:17: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   ex_lo,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[5:0]           stall,  \n    ^~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  reg[`RegDataBus]   mem_result,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:22: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]   mem_result,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]   mem_waddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:24: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]   mem_waddr,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:25: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]   mem_hi,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:26: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]   mem_lo,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:32: Define or directive not defined: \'`ZeroWord\'\n        mem_result <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:33: Define or directive not defined: \'`Disable\'\n        mem_we     <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:34: Define or directive not defined: \'`RegAddr_0\'\n        mem_waddr  <= `RegAddr_0;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:35: Define or directive not defined: \'`ZeroWord\'\n        mem_hi     <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:36: Define or directive not defined: \'`ZeroWord\'\n        mem_lo     <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:37: Define or directive not defined: \'`Disable\'\n        mem_whilo  <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:43: Define or directive not defined: \'`ZeroWord\'\n        mem_result <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:44: Define or directive not defined: \'`Disable\'\n        mem_we     <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:45: Define or directive not defined: \'`RegAddr_0\'\n        mem_waddr  <= `RegAddr_0;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:46: Define or directive not defined: \'`ZeroWord\'\n        mem_hi     <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:47: Define or directive not defined: \'`ZeroWord\'\n        mem_lo     <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/ex_mem.v:48: Define or directive not defined: \'`Disable\'\n        mem_whilo  <= `Disable;\n                      ^~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module ex_mem (
    input   wire    clk,
    input   wire    rst,


    input   wire[`RegDataBus]   ex_result,
    input   wire                ex_we,
    input   wire[`RegAddrBus]   ex_waddr,
    input   wire[`RegDataBus]   ex_hi,
    input   wire[`RegDataBus]   ex_lo,
    input   wire                ex_whilo,
    input   wire[5:0]           stall,  


    output  reg[`RegDataBus]   mem_result,
    output  reg                mem_we,
    output  reg[`RegAddrBus]   mem_waddr,
    output  reg[`RegDataBus]   mem_hi,
    output  reg[`RegDataBus]   mem_lo,
    output  reg                mem_whilo
);

always @(posedge clk) begin
    if(rst) begin
        mem_result <= `ZeroWord;
        mem_we     <= `Disable;
        mem_waddr  <= `RegAddr_0;
        mem_hi     <= `ZeroWord;
        mem_lo     <= `ZeroWord;
        mem_whilo  <= `Disable;
    end 

    else if(stall[3] && !stall[4]) begin
        mem_result <= `ZeroWord;
        mem_we     <= `Disable;
        mem_waddr  <= `RegAddr_0;
        mem_hi     <= `ZeroWord;
        mem_lo     <= `ZeroWord;
        mem_whilo  <= `Disable;
    end

    else if(!stall[3]) begin
        mem_result <= ex_result;
        mem_we     <= ex_we;
        mem_waddr  <= ex_waddr;
        mem_hi     <= ex_hi;
        mem_lo     <= ex_lo;
        mem_whilo  <= ex_whilo;
    end 
    
    else begin
        mem_result <= mem_result;
        mem_we     <= mem_we;
        mem_waddr  <= mem_waddr;
        mem_hi     <= mem_hi;
        mem_lo     <= mem_lo;
        mem_whilo  <= mem_whilo;
    end
end

endmodule
module ex_mem (
    input   wire    clk,
    input   wire    rst,


    input   wire[`RegDataBus]   ex_result,
    input   wire                ex_we,
    input   wire[`RegAddrBus]   ex_waddr,
    input   wire[`RegDataBus]   ex_hi,
    input   wire[`RegDataBus]   ex_lo,
    input   wire                ex_whilo,
    input   wire[5:0]           stall,  


    output  reg[`RegDataBus]   mem_result,
    output  reg                mem_we,
    output  reg[`RegAddrBus]   mem_waddr,
    output  reg[`RegDataBus]   mem_hi,
    output  reg[`RegDataBus]   mem_lo,
    output  reg                mem_whilo
);


always @(posedge clk) begin
    if(rst) begin
        mem_result <= `ZeroWord;
        mem_we     <= `Disable;
        mem_waddr  <= `RegAddr_0;
        mem_hi     <= `ZeroWord;
        mem_lo     <= `ZeroWord;
        mem_whilo  <= `Disable;
    end 

    else if(stall[3] && !stall[4]) begin
        mem_result <= `ZeroWord;
        mem_we     <= `Disable;
        mem_waddr  <= `RegAddr_0;
        mem_hi     <= `ZeroWord;
        mem_lo     <= `ZeroWord;
        mem_whilo  <= `Disable;
    end

    else if(!stall[3]) begin
        mem_result <= ex_result;
        mem_we     <= ex_we;
        mem_waddr  <= ex_waddr;
        mem_hi     <= ex_hi;
        mem_lo     <= ex_lo;
        mem_whilo  <= ex_whilo;
    end 
    
    else begin
        mem_result <= mem_result;
        mem_we     <= mem_we;
        mem_waddr  <= mem_waddr;
        mem_hi     <= mem_hi;
        mem_lo     <= mem_lo;
        mem_whilo  <= mem_whilo;
    end
end

endmodule