data/full_repos/permissive/445216371/coprocessor0.v
1: b'%Error: data/full_repos/permissive/445216371/coprocessor0.v:11: Cannot find include file: parameters.vh\n    `include "parameters.vh" \n             ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.v\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.sv\n             parameters.vh\n             parameters.vh.v\n             parameters.vh.sv\n             obj_dir/parameters.vh\n             obj_dir/parameters.vh.v\n             obj_dir/parameters.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module cop0 (
    output reg [31:0] ans,
    output stall,
    input [31:0] a,b,
    input [2:0] Mulfnc3,
    input sel,clk,rst
);
    `include "parameters.vh"

    wire [63:0] mulans;
    reg sig_a,sig_b;
    wire ok;
    reg prevOk;
    reg start;
    assign stall = start&&(!((prevOk==0)&&ok==1));
    always @(posedge clk) begin
        prevOk=ok;
    end
    multiplier m1(mulans,a,b,sig_a,sig_b);

    wire [31:0] D,R;
    

    always @(*) case (Mulfnc3)
        MULf3: begin
            ans = mulans[31:0];
            sig_a=0;
            sig_b=0;
            start=0;
        end
        MULHf3: begin
            ans = mulans[63:31];
            sig_a=1;
            sig_b=1;
            start=0;
        end
        MULHSUf3: begin
            ans = mulans[63:31];
            sig_a=1;
            sig_b=0;
            start=0;
        end
        MULHUf3: begin
            ans = mulans[63:31];
            sig_a=0;
            sig_b=0;
            start=0;
        end
        DIVf3: begin
            ans = D;
            sig_a=1;
            sig_b=1;
            start=sel;
        end
        DIVUf3: begin
            ans = D;
            sig_a=0;
            sig_b=0;
            start=sel;
        end
        REMf3: begin
            ans = R;
            sig_a=1;
            sig_b=1;
            start=sel;
        end
        REMUf3: begin
            ans = R;
            sig_a=0;
            sig_b=0;
            start=sel;
        end
        default: begin
            ans = mulans[31:0];
            sig_a=0;
            sig_b=0;
            start=sel;
        end
    endcase 


    








    Divide d1(clk,rst,stall,a,b,D,R,ok,err);  
   
endmodule
module cop0 (
    output reg [31:0] ans,
    output stall,
    input [31:0] a,b,
    input [2:0] Mulfnc3,
    input sel,clk,rst
);

    `include "parameters.vh"

    wire [63:0] mulans;
    reg sig_a,sig_b;
    wire ok;
    reg prevOk;
    reg start;
    assign stall = start&&(!((prevOk==0)&&ok==1));
    always @(posedge clk) begin
        prevOk=ok;
    end
    multiplier m1(mulans,a,b,sig_a,sig_b);

    wire [31:0] D,R;
    

    always @(*) case (Mulfnc3)
        MULf3: begin
            ans = mulans[31:0];
            sig_a=0;
            sig_b=0;
            start=0;
        end
        MULHf3: begin
            ans = mulans[63:31];
            sig_a=1;
            sig_b=1;
            start=0;
        end
        MULHSUf3: begin
            ans = mulans[63:31];
            sig_a=1;
            sig_b=0;
            start=0;
        end
        MULHUf3: begin
            ans = mulans[63:31];
            sig_a=0;
            sig_b=0;
            start=0;
        end
        DIVf3: begin
            ans = D;
            sig_a=1;
            sig_b=1;
            start=sel;
        end
        DIVUf3: begin
            ans = D;
            sig_a=0;
            sig_b=0;
            start=sel;
        end
        REMf3: begin
            ans = R;
            sig_a=1;
            sig_b=1;
            start=sel;
        end
        REMUf3: begin
            ans = R;
            sig_a=0;
            sig_b=0;
            start=sel;
        end
        default: begin
            ans = mulans[31:0];
            sig_a=0;
            sig_b=0;
            start=sel;
        end
    endcase 


    








    Divide d1(clk,rst,stall,a,b,D,R,ok,err);  
   
endmodule