data/full_repos/permissive/46981098/cpu_eda.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46981098/cpu_eda.v:277: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'mux5_2to1\'\nmodule mux5_2to1(out, in0, in1, sel);\n       ^~~~~~~~~\n                                                                    : ... Top module \'cpu\'\nmodule cpu (\n       ^~~\n%Error: data/full_repos/permissive/46981098/cpu_eda.v:298: Duplicate declaration of signal: \'pc\'\n    reg[31:0] pc;\n              ^~\n        data/full_repos/permissive/46981098/cpu_eda.v:280: ... Location of original declaration\n     output reg [31:0] pc,\n                       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/46981098/cpu_eda.v:354: Signal definition not found, creating implicitly: \'mux05_result\'\n                                                                    : ... Suggested alternative: \'mux04_result\'\n   mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);\n                     ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module cpu (
  	  input clk,
  	  output reg [31:0] addr,
  	  output reg [31:0] pc,
	  output [31:0] instruction,
	  output [1:0] cu_regdst,
	  output cu_jump, cu_branch, cu_memread,
	  output [1:0] cu_memtoreg,
	  output [1:0] cu_aluop,
	  output cu_memwrite, cu_aluscr, cu_regwrite,
	  output [4:0] mux1_regwrite,
	  output [31:0] mux3_writedata,
	  output [31:0] reg_readdata1, reg_readdata2,
	  output [31:0] signext_out,
	  output [31:0] mux2_out,
	  output [31:0] alu_out,
	  output alu_zero,
	  output [3:0] aluctrl_out,
	  output [31:0] dmem_readdata,
	  output bBranch
	  );
  		reg[31:0] pc;
  		initial begin
          addr = 32'b0000_0000_0000_0000_0000_0000_0010_1000;
        end


  		reg [31:0] ra;
  		parameter ra_addr = 5'b11111;

	    instr_mem instrmem (addr,instruction);

	    control_unit contrlu (instruction[31:26],
                              cu_regdst, cu_regwrite, cu_branch,
	                          cu_jump, cu_memread, cu_memtoreg,
	                          cu_memwrite, cu_aluop, cu_aluscr );

  		mux5_3to1 mux01 (mux1_regwrite, instruction[20:16], instruction[15:11], ra_addr, cu_regdst[1:0]);

	  	registerMemory regmem ( .reg_read1(instruction[25:21]),
								.reg_read2(instruction[20:16]),
	                           	.reg_write(mux1_regwrite[4:0]),
	                          	.regwrite_con(cu_regwrite),
	                          	.write_data(mux3_writedata),
	                          	.data1(reg_readdata1),
	                          	.data2(reg_readdata2));

	  	sign_extended signext (signext_out[31:0], instruction[15:0]);

	  	mux32_2to1 mux02 (mux2_out, reg_readdata2, signext_out, cu_aluscr);

	    alu_control aluctrl (cu_aluop, instruction[5:0], aluctrl_out);

	    alu ALU (aluctrl_out, reg_readdata1, mux2_out, alu_out, alu_zero);

	    datamem data_mem (dmem_readdata, alu_out, reg_readdata2, cu_memread, cu_memwrite);

    always @(posedge clk) begin
       pc <= addr + 4;

    end

  		mux32_3to1 mux03(mux3_writedata, alu_out, dmem_readdata, pc, cu_memtoreg);

	    and AND1(bBranch, cu_branch, alu_zero );

	  	reg[31:0] branch_shiftl2_result;
	  	assign branch_shiftl2_result = signext_out << 2;

	  	reg[31:0] j_addr;
	  	assign j_addr = {pc[31:28],(instruction[25:0] << 2)};

	  reg[31:0] b_addr;
	  assign b_addr = pc + branch_shiftl2_result;
	  reg[31:0] mux04_result;

	  mux32_2to1 mux04 (mux04_result, pc, b_addr, bBranch);
	  mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);





endmodule
module cpu (
  	  input clk,
  	  output reg [31:0] addr,
  	  output reg [31:0] pc,
	  output [31:0] instruction,
	  output [1:0] cu_regdst,
	  output cu_jump, cu_branch, cu_memread,
	  output [1:0] cu_memtoreg,
	  output [1:0] cu_aluop,
	  output cu_memwrite, cu_aluscr, cu_regwrite,
	  output [4:0] mux1_regwrite,
	  output [31:0] mux3_writedata,
	  output [31:0] reg_readdata1, reg_readdata2,
	  output [31:0] signext_out,
	  output [31:0] mux2_out,
	  output [31:0] alu_out,
	  output alu_zero,
	  output [3:0] aluctrl_out,
	  output [31:0] dmem_readdata,
	  output bBranch
	  );

  		reg[31:0] pc;
  		initial begin
          addr = 32'b0000_0000_0000_0000_0000_0000_0010_1000;
        end


  		reg [31:0] ra;
  		parameter ra_addr = 5'b11111;

	    instr_mem instrmem (addr,instruction);

	    control_unit contrlu (instruction[31:26],
                              cu_regdst, cu_regwrite, cu_branch,
	                          cu_jump, cu_memread, cu_memtoreg,
	                          cu_memwrite, cu_aluop, cu_aluscr );

  		mux5_3to1 mux01 (mux1_regwrite, instruction[20:16], instruction[15:11], ra_addr, cu_regdst[1:0]);

	  	registerMemory regmem ( .reg_read1(instruction[25:21]),
								.reg_read2(instruction[20:16]),
	                           	.reg_write(mux1_regwrite[4:0]),
	                          	.regwrite_con(cu_regwrite),
	                          	.write_data(mux3_writedata),
	                          	.data1(reg_readdata1),
	                          	.data2(reg_readdata2));

	  	sign_extended signext (signext_out[31:0], instruction[15:0]);

	  	mux32_2to1 mux02 (mux2_out, reg_readdata2, signext_out, cu_aluscr);

	    alu_control aluctrl (cu_aluop, instruction[5:0], aluctrl_out);

	    alu ALU (aluctrl_out, reg_readdata1, mux2_out, alu_out, alu_zero);

	    datamem data_mem (dmem_readdata, alu_out, reg_readdata2, cu_memread, cu_memwrite);

    always @(posedge clk) begin
       pc <= addr + 4;

    end

  		mux32_3to1 mux03(mux3_writedata, alu_out, dmem_readdata, pc, cu_memtoreg);

	    and AND1(bBranch, cu_branch, alu_zero );

	  	reg[31:0] branch_shiftl2_result;
	  	assign branch_shiftl2_result = signext_out << 2;

	  	reg[31:0] j_addr;
	  	assign j_addr = {pc[31:28],(instruction[25:0] << 2)};

	  reg[31:0] b_addr;
	  assign b_addr = pc + branch_shiftl2_result;
	  reg[31:0] mux04_result;

	  mux32_2to1 mux04 (mux04_result, pc, b_addr, bBranch);
	  mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);





endmodule