data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/edge_propagator.sv
1: b"%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/edge_propagator.sv:40: Cannot find file containing module: 'pulp_sync_wedge'\n    pulp_sync_wedge i_sync_clkb (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/pulp_sync_wedge\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/pulp_sync_wedge.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/pulp_sync_wedge.sv\n             pulp_sync_wedge\n             pulp_sync_wedge.v\n             pulp_sync_wedge.sv\n             obj_dir/pulp_sync_wedge\n             obj_dir/pulp_sync_wedge.v\n             obj_dir/pulp_sync_wedge.sv\n%Error: Exiting due to 1 error(s)\n"
module edge_propagator (
    input  logic clk_tx_i,
    input  logic rstn_tx_i,
    input  logic edge_i,
    input  logic clk_rx_i,
    input  logic rstn_rx_i,
    output logic edge_o
);

    logic [1:0] sync_a;
    logic       sync_b;

    logic r_input_reg;
    logic s_input_reg_next;

    assign s_input_reg_next = edge_i | (r_input_reg & (~sync_a[0]));

    always @(negedge rstn_tx_i or posedge clk_tx_i) begin
        if (~rstn_tx_i) begin
            r_input_reg <= 1'b0;
            sync_a      <= 2'b00;
        end else begin
            r_input_reg <= s_input_reg_next;
            sync_a      <= {sync_b,sync_a[1]};
        end
    end

    pulp_sync_wedge i_sync_clkb (
        .clk_i    ( clk_rx_i     ),
        .rstn_i   ( rstn_rx_i    ),
        .en_i     ( 1'b1         ),
        .serial_i ( r_input_reg  ),
        .r_edge_o ( edge_o       ),
        .f_edge_o (              ),
        .serial_o ( sync_b       )
    );

endmodule
module edge_propagator (
    input  logic clk_tx_i,
    input  logic rstn_tx_i,
    input  logic edge_i,
    input  logic clk_rx_i,
    input  logic rstn_rx_i,
    output logic edge_o
);


    logic [1:0] sync_a;
    logic       sync_b;

    logic r_input_reg;
    logic s_input_reg_next;

    assign s_input_reg_next = edge_i | (r_input_reg & (~sync_a[0]));

    always @(negedge rstn_tx_i or posedge clk_tx_i) begin
        if (~rstn_tx_i) begin
            r_input_reg <= 1'b0;
            sync_a      <= 2'b00;
        end else begin
            r_input_reg <= s_input_reg_next;
            sync_a      <= {sync_b,sync_a[1]};
        end
    end

    pulp_sync_wedge i_sync_clkb (
        .clk_i    ( clk_rx_i     ),
        .rstn_i   ( rstn_rx_i    ),
        .en_i     ( 1'b1         ),
        .serial_i ( r_input_reg  ),
        .r_edge_o ( edge_o       ),
        .f_edge_o (              ),
        .serial_o ( sync_b       )
    );

endmodule