data/full_repos/permissive/514992586/1_Verilog_language/Vectors/17_Vectorrr.v
data/verilator_xmls/8b497e87-5677-4d0e-aef9-347b76421696.xml
module top_module (
    input [7:0] in,
    output [31:0] out );


    assign out = {{24{in[7]}}, in};

endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );



    assign out = {{24{in[7]}}, in};

endmodule