data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:6: Cannot find file containing module: \'g_halfsub\'\n    g_halfsub g(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412284801/adders/halfsubtractor,data/full_repos/permissive/412284801/g_halfsub\n             data/full_repos/permissive/412284801/adders/halfsubtractor,data/full_repos/permissive/412284801/g_halfsub.v\n             data/full_repos/permissive/412284801/adders/halfsubtractor,data/full_repos/permissive/412284801/g_halfsub.sv\n             g_halfsub\n             g_halfsub.v\n             g_halfsub.sv\n             obj_dir/g_halfsub\n             obj_dir/g_halfsub.v\n             obj_dir/g_halfsub.sv\n%Error: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:12: Cannot find file containing module: \'b_halfsub\'\n    b_halfsub B(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/412284801/adders/halfsubtractor/halfsub_tb.v:18: Cannot find file containing module: \'d_halfsub\'\n    d_halfsub d(\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module halfsub_tb;
    reg a,b;
    wire ds,bs,gs;
    wire dc,bc,gc;

    g_halfsub g(
        .a(a),
        .b(b),
        .d(gs),
        .bo(gc)
    );
    b_halfsub B(
        .a(a),
        .b(b),
        .d(bs),
        .bo(bc)
    );
    d_halfsub d(
        .a(a),
        .b(b),
        .d(ds),
        .bo(dc)
    );

    initial
    begin
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
    end
endmodule
module halfsub_tb;

    reg a,b;
    wire ds,bs,gs;
    wire dc,bc,gc;

    g_halfsub g(
        .a(a),
        .b(b),
        .d(gs),
        .bo(gc)
    );
    b_halfsub B(
        .a(a),
        .b(b),
        .d(bs),
        .bo(bc)
    );
    d_halfsub d(
        .a(a),
        .b(b),
        .d(ds),
        .bo(dc)
    );

    initial
    begin
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
    end
endmodule