data/full_repos/permissive/458208177/testbench_template.v
1: b'%Error: data/full_repos/permissive/458208177/testbench_template.v:2: syntax error, unexpected \'.\', expecting IDENTIFIER or \'=\' or do or final\n    reg ...;             \n        ^\n%Error: data/full_repos/permissive/458208177/testbench_template.v:7: syntax error, unexpected IDENTIFIER, expecting \')\'\n    UUT_name M1_isntance_name(UUT ports go here);\n                                  ^~~~~\n%Error: data/full_repos/permissive/458208177/testbench_template.v:8: Unsupported or unknown PLI call: $monitor\n    initial $monitor();          \n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458208177/testbench_template.v:10: Unsupported: Ignoring delay on this delayed statement.\n    initial #time_out $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module t_DUTB_name();
    reg ...;

    wire ...;
    
    parameter time_out = 0;
    UUT_name M1_isntance_name(UUT ports go here);
    initial $monitor();

    initial #time_out $finish;
    initial


    begin





    end
endmodule
module t_DUTB_name();

    reg ...;

    wire ...;
    
    parameter time_out = 0;
    UUT_name M1_isntance_name(UUT ports go here);
    initial $monitor();

    initial #time_out $finish;
    initial


    begin





    end
endmodule