data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:10: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:14: Define or directive not defined: \'`PC_SIZE\'\n  input  [`PC_SIZE-1:0] ifu_req_pc,  \n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:18: Define or directive not defined: \'`INSTR_SIZE\'\n  output [`INSTR_SIZE-1:0] ifu_rsp_instr,  \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:22: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,  \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:25: Define or directive not defined: \'`ITCM_RAM_DW\'\n  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/ifu_ifu2itcm.v:30: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n  assign ifu2itcm_cmd_addr = ifu_req_pc[`ITCM_ADDR_WIDTH-1:0]; \n                                        ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module ifu_ifu2itcm(
  input  ifu_req_valid,
  output ifu_req_ready,
  input  [`PC_SIZE-1:0] ifu_req_pc,

  output ifu_rsp_valid,
  input  ifu_rsp_ready,
  output [`INSTR_SIZE-1:0] ifu_rsp_instr,
  
  output ifu2itcm_cmd_valid,
  input  ifu2itcm_cmd_ready,
  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,
  input  ifu2itcm_rsp_valid,
  output ifu2itcm_rsp_ready,
  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata
);
  
  assign ifu2itcm_cmd_valid = ifu_req_valid;
  assign ifu_req_ready = ifu2itcm_cmd_ready;
  assign ifu2itcm_cmd_addr = ifu_req_pc[`ITCM_ADDR_WIDTH-1:0];
  assign ifu_rsp_valid = ifu2itcm_rsp_valid;
  assign ifu2itcm_rsp_ready = ifu_rsp_ready;
  assign ifu_rsp_instr = ifu2itcm_rsp_rdata;
endmodule
module ifu_ifu2itcm(
  input  ifu_req_valid,
  output ifu_req_ready,
  input  [`PC_SIZE-1:0] ifu_req_pc,

  output ifu_rsp_valid,
  input  ifu_rsp_ready,
  output [`INSTR_SIZE-1:0] ifu_rsp_instr,
  
  output ifu2itcm_cmd_valid,
  input  ifu2itcm_cmd_ready,
  output [`ITCM_ADDR_WIDTH-1:0]   ifu2itcm_cmd_addr,
  input  ifu2itcm_rsp_valid,
  output ifu2itcm_rsp_ready,
  input  [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata
);

  
  assign ifu2itcm_cmd_valid = ifu_req_valid;
  assign ifu_req_ready = ifu2itcm_cmd_ready;
  assign ifu2itcm_cmd_addr = ifu_req_pc[`ITCM_ADDR_WIDTH-1:0];
  assign ifu_rsp_valid = ifu2itcm_rsp_valid;
  assign ifu2itcm_rsp_ready = ifu_rsp_ready;
  assign ifu_rsp_instr = ifu2itcm_rsp_rdata;
endmodule