data/full_repos/permissive/490649362/single-cycle/src/MUX2_1.v
1: b'%Error: data/full_repos/permissive/490649362/single-cycle/src/MUX2_1.v:6: syntax error, unexpected \'=\', expecting IDENTIFIER\n    parameter bit = 32;\n                  ^\n%Error: data/full_repos/permissive/490649362/single-cycle/src/MUX2_1.v:9: syntax error, unexpected \'-\', expecting "\'{"\n    input  [bit-1:0] in_0, in_1;\n               ^\n%Error: data/full_repos/permissive/490649362/single-cycle/src/MUX2_1.v:10: syntax error, unexpected \'-\', expecting "\'{"\n    output [bit-1:0] out;\n               ^\n%Error: Exiting due to 3 error(s)\n'
module MUX2_1(in_0, in_1, sel, out);

    parameter bit = 32;

    input            sel;
    input  [bit-1:0] in_0, in_1;
    output [bit-1:0] out;

    assign out = (sel == 0) ? in_0 : in_1;

endmodule
module MUX2_1(in_0, in_1, sel, out);


    parameter bit = 32;

    input            sel;
    input  [bit-1:0] in_0, in_1;
    output [bit-1:0] out;

    assign out = (sel == 0) ? in_0 : in_1;

endmodule