data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/reorder_queue_output.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/reorder_queue_output.v:57: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module reorder_queue_output #(
    parameter C_PCI_DATA_WIDTH = 9'd128,
    parameter C_NUM_CHNL = 4'd12,
    parameter C_TAG_WIDTH = 5,
    parameter C_TAG_DW_COUNT_WIDTH = 8,
    parameter C_DATA_ADDR_STRIDE_WIDTH = 5,
    parameter C_DATA_ADDR_WIDTH = 10,

    parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
    parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
    parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
    parameter C_NUM_TAGS = 2**C_TAG_WIDTH
    )
   (
    input 					     CLK,
    input 					     RST,
    output [C_DATA_ADDR_WIDTH-1:0] 		     DATA_ADDR,
    input [C_PCI_DATA_WIDTH-1:0] 		     DATA,
    input [C_NUM_TAGS-1:0] 			     TAG_FINISHED,
    output [C_NUM_TAGS-1:0] 			     TAG_CLEAR,
    output [C_TAG_WIDTH-1:0] 			     TAG,
    input [5:0] 				     TAG_MAPPED,
    input [C_TAG_DW_COUNT_WIDTH-1:0] 		     PKT_WORDS,
    input 					     PKT_WORDS_LTE1,
    input 					     PKT_WORDS_LTE2,
    input 					     PKT_DONE,
    input 					     PKT_ERR,

    output [C_PCI_DATA_WIDTH-1:0] 		     ENG_DATA,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     MAIN_DONE,
    output [C_NUM_CHNL-1:0] 			     MAIN_ERR,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     SG_RX_DONE,
    output [C_NUM_CHNL-1:0] 			     SG_RX_ERR,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     SG_TX_DONE,
    output [C_NUM_CHNL-1:0] 			     SG_TX_ERR
    );


   reg [1:0] 					     rState=0;
   reg [C_DATA_ADDR_WIDTH-1:0] 			     rDataAddr=0;
   reg [C_PCI_DATA_WIDTH-1:0] 			     rData=0;

   reg 						     rTagFinished=0;
   reg [C_NUM_TAGS-1:0] 			     rClear=0;

   reg [C_TAG_WIDTH-1:0] 			     rTag=0;
   reg [C_TAG_WIDTH-1:0] 			     rTagCurr=0;
   wire [C_TAG_WIDTH-1:0] 			     wTagNext = rTag + 1'd1;

   reg [5:0] 					     rShift;
   reg 						     rDone=0;
   reg 						     rDoneLast=0;
   reg 						     rErr=0;
   reg 						     rErrLast=0;
   reg [C_PCI_DATA_COUNT_WIDTH-1:0] 		     rDE=0;
   reg [C_TAG_DW_COUNT_WIDTH-1:0] 		     rWords=0;
   reg 						     rLTE2Pkts=0;

   reg [C_PCI_DATA_WIDTH-1:0] 			     rDataOut={C_PCI_DATA_WIDTH{1'b0}};
   reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] 	     rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
   reg [(3*16)-1:0] 				     rDoneOut={3*16{1'd0}};
   reg [(3*16)-1:0] 				     rErrOut={3*16{1'd0}};


   assign DATA_ADDR = rDataAddr;
   assign TAG = rTag;
   assign TAG_CLEAR = rClear;

   assign ENG_DATA = rDataOut;

   assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
   assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];

   assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
   assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];

   assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
   assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];



   always @ (posedge CLK) begin
      if (RST) begin
	      rState <= #1 0;
	      rTag <= #1 0;
	      rDataAddr <= #1 0;
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 0;
	      rClear <= #1 0;
	      rTagFinished <= #1 0;
          rShift <= 0;
      end
      else begin
	 rTagFinished <= #1 TAG_FINISHED[rTag];
	 case (rState)
	   
	   2'd0: begin
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 0;
	      rClear <= #1 0;
	      if (rTagFinished) begin
		 rTag <= #1 wTagNext;
		 rTagCurr <= #1 rTag;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd2;
	      end
	      else begin
		 rState <= #1 2'd0;
	      end
	   end

	   2'd1: begin
	      rDone <= #1 rDoneLast;
	      rErr <= #1 rErrLast;
	      rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
	      rClear <= #1 1<<rTagCurr;
	      if (rTagFinished) begin
		 rTag <= #1 wTagNext;
		 rTagCurr <= #1 rTag;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd2;
	      end
	      else begin
		 rState <= #1 2'd0;
	      end
	   end

	   2'd2: begin
	      rShift <= #1 TAG_MAPPED;
	      rDoneLast <= #1 PKT_DONE;
	      rErrLast <= #1 PKT_ERR;
	      rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
	      if (PKT_WORDS_LTE1) begin
		 rDone <= #1 PKT_DONE;
		 rErr <= #1 PKT_ERR;
		 rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
		 rClear <= #1 1<<rTagCurr;
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd0;
	      end
	      else if (PKT_WORDS_LTE2) begin
		 rDone <= #1 0;
		 rErr <= #1 0;
		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
		 rClear <= #1 0;
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd1;
	      end
	      else begin
		 rDone <= #1 0;
		 rErr <= #1 0;
		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
		 rClear <= #1 0;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd3;
	      end
	   end

	   2'd3: begin
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
	      if (rLTE2Pkts) begin
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd1;
	      end
	      else begin
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd3;
	      end
	   end

	 endcase
      end
   end



   always @ (posedge CLK) begin
      rData <= #1 DATA;
      rDataOut <= #1 rData;
      if (RST) begin
	 rDEOut <= #1 0;
	 rDoneOut <= #1 0;
	 rErrOut <= #1 0;
      end
      else begin
	 rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
	 rDoneOut <= #1 (rDone | rErr)<<rShift;
	 rErrOut <= #1 rErr<<rShift;
      end
   end




endmodule
module reorder_queue_output #(
    parameter C_PCI_DATA_WIDTH = 9'd128,
    parameter C_NUM_CHNL = 4'd12,
    parameter C_TAG_WIDTH = 5,
    parameter C_TAG_DW_COUNT_WIDTH = 8,
    parameter C_DATA_ADDR_STRIDE_WIDTH = 5,
    parameter C_DATA_ADDR_WIDTH = 10,

    parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
    parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
    parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
    parameter C_NUM_TAGS = 2**C_TAG_WIDTH
    )
   (
    input 					     CLK,
    input 					     RST,
    output [C_DATA_ADDR_WIDTH-1:0] 		     DATA_ADDR,
    input [C_PCI_DATA_WIDTH-1:0] 		     DATA,
    input [C_NUM_TAGS-1:0] 			     TAG_FINISHED,
    output [C_NUM_TAGS-1:0] 			     TAG_CLEAR,
    output [C_TAG_WIDTH-1:0] 			     TAG,
    input [5:0] 				     TAG_MAPPED,
    input [C_TAG_DW_COUNT_WIDTH-1:0] 		     PKT_WORDS,
    input 					     PKT_WORDS_LTE1,
    input 					     PKT_WORDS_LTE2,
    input 					     PKT_DONE,
    input 					     PKT_ERR,

    output [C_PCI_DATA_WIDTH-1:0] 		     ENG_DATA,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     MAIN_DONE,
    output [C_NUM_CHNL-1:0] 			     MAIN_ERR,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     SG_RX_DONE,
    output [C_NUM_CHNL-1:0] 			     SG_RX_ERR,
    output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN,
    output [C_NUM_CHNL-1:0] 			     SG_TX_DONE,
    output [C_NUM_CHNL-1:0] 			     SG_TX_ERR
    );



   reg [1:0] 					     rState=0;
   reg [C_DATA_ADDR_WIDTH-1:0] 			     rDataAddr=0;
   reg [C_PCI_DATA_WIDTH-1:0] 			     rData=0;

   reg 						     rTagFinished=0;
   reg [C_NUM_TAGS-1:0] 			     rClear=0;

   reg [C_TAG_WIDTH-1:0] 			     rTag=0;
   reg [C_TAG_WIDTH-1:0] 			     rTagCurr=0;
   wire [C_TAG_WIDTH-1:0] 			     wTagNext = rTag + 1'd1;

   reg [5:0] 					     rShift;
   reg 						     rDone=0;
   reg 						     rDoneLast=0;
   reg 						     rErr=0;
   reg 						     rErrLast=0;
   reg [C_PCI_DATA_COUNT_WIDTH-1:0] 		     rDE=0;
   reg [C_TAG_DW_COUNT_WIDTH-1:0] 		     rWords=0;
   reg 						     rLTE2Pkts=0;

   reg [C_PCI_DATA_WIDTH-1:0] 			     rDataOut={C_PCI_DATA_WIDTH{1'b0}};
   reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] 	     rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
   reg [(3*16)-1:0] 				     rDoneOut={3*16{1'd0}};
   reg [(3*16)-1:0] 				     rErrOut={3*16{1'd0}};


   assign DATA_ADDR = rDataAddr;
   assign TAG = rTag;
   assign TAG_CLEAR = rClear;

   assign ENG_DATA = rDataOut;

   assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
   assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];

   assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
   assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];

   assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
   assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
   assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];



   always @ (posedge CLK) begin
      if (RST) begin
	      rState <= #1 0;
	      rTag <= #1 0;
	      rDataAddr <= #1 0;
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 0;
	      rClear <= #1 0;
	      rTagFinished <= #1 0;
          rShift <= 0;
      end
      else begin
	 rTagFinished <= #1 TAG_FINISHED[rTag];
	 case (rState)
	   
	   2'd0: begin
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 0;
	      rClear <= #1 0;
	      if (rTagFinished) begin
		 rTag <= #1 wTagNext;
		 rTagCurr <= #1 rTag;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd2;
	      end
	      else begin
		 rState <= #1 2'd0;
	      end
	   end

	   2'd1: begin
	      rDone <= #1 rDoneLast;
	      rErr <= #1 rErrLast;
	      rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
	      rClear <= #1 1<<rTagCurr;
	      if (rTagFinished) begin
		 rTag <= #1 wTagNext;
		 rTagCurr <= #1 rTag;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd2;
	      end
	      else begin
		 rState <= #1 2'd0;
	      end
	   end

	   2'd2: begin
	      rShift <= #1 TAG_MAPPED;
	      rDoneLast <= #1 PKT_DONE;
	      rErrLast <= #1 PKT_ERR;
	      rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
	      if (PKT_WORDS_LTE1) begin
		 rDone <= #1 PKT_DONE;
		 rErr <= #1 PKT_ERR;
		 rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
		 rClear <= #1 1<<rTagCurr;
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd0;
	      end
	      else if (PKT_WORDS_LTE2) begin
		 rDone <= #1 0;
		 rErr <= #1 0;
		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
		 rClear <= #1 0;
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd1;
	      end
	      else begin
		 rDone <= #1 0;
		 rErr <= #1 0;
		 rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
		 rClear <= #1 0;
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd3;
	      end
	   end

	   2'd3: begin
	      rDone <= #1 0;
	      rErr <= #1 0;
	      rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
	      rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
	      if (rLTE2Pkts) begin
		 rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH;
		 rState <= #1 2'd1;
	      end
	      else begin
		 rDataAddr <= #1 rDataAddr + 1'd1;
		 rState <= #1 2'd3;
	      end
	   end

	 endcase
      end
   end



   always @ (posedge CLK) begin
      rData <= #1 DATA;
      rDataOut <= #1 rData;
      if (RST) begin
	 rDEOut <= #1 0;
	 rDoneOut <= #1 0;
	 rErrOut <= #1 0;
      end
      else begin
	 rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
	 rDoneOut <= #1 (rDone | rErr)<<rShift;
	 rErrOut <= #1 rErr<<rShift;
      end
   end




endmodule