data/full_repos/permissive/423547971/University Senior Class Design Project/shift_reg376.v
1: b'%Error: Cannot find file containing module: Senior\n        ... Looked in:\n             data/full_repos/permissive/423547971/University/Senior\n             data/full_repos/permissive/423547971/University/Senior.v\n             data/full_repos/permissive/423547971/University/Senior.sv\n             Senior\n             Senior.v\n             Senior.sv\n             obj_dir/Senior\n             obj_dir/Senior.v\n             obj_dir/Senior.sv\n%Error: Cannot find file containing module: Class\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/University\n%Error: Cannot find file containing module: Project/shift_reg376.v\n%Error: Exiting due to 6 error(s)\n'
module shift_reg376(
    input data_in,
    input reset,
    input latch,
    output [183:0] data_out,
    output reg sig542c
    );
    
    reg [375:0] data_packet;
    
    always @(posedge latch or posedge reset) begin
        if(reset)
            data_packet <= 376'd0;
        else
            data_packet[0] <= data_in;
            data_packet[375:1] <= data_packet[374:0];
    end
    
    always @(posedge latch) begin
        if(data_packet[375:360] == 16'h542c)
            sig542c <= 1'b1;
        else
            sig542c <= 1'b0;
    end
    


    assign data_out[167:160] = data_packet[351:344];
    assign data_out[159:152] = data_packet[359:352];
    assign data_out[151:144] = data_packet[335:328];
    assign data_out[143:136] = data_packet[343:336];
    assign data_out[135:128] = data_packet[327:320];
    assign data_out[127:120] = data_packet[303:296];
    assign data_out[119:112] = data_packet[279:272];
    assign data_out[111:104] = data_packet[255:248];
    assign data_out[103:96]  = data_packet[231:224];
    assign data_out[95:88]   = data_packet[207:200];
    assign data_out[87:80]   = data_packet[183:176];
    assign data_out[79:72]   = data_packet[159:152];
    assign data_out[71:64]   = data_packet[135:128];
    assign data_out[63:56]   = data_packet[111:104];
    assign data_out[55:48]   = data_packet[87:80];
    assign data_out[47:40]   = data_packet[63:56];
    assign data_out[39:32]   = data_packet[31:24];
    assign data_out[31:24]   = data_packet[39:32];
    assign data_out[23:16]   = data_packet[15:8];
    assign data_out[15:8]    = data_packet[23:16];
    assign data_out[7:0]     = data_packet[7:0];
    
endmodule
module shift_reg376(
    input data_in,
    input reset,
    input latch,
    output [183:0] data_out,
    output reg sig542c
    );

    
    reg [375:0] data_packet;
    
    always @(posedge latch or posedge reset) begin
        if(reset)
            data_packet <= 376'd0;
        else
            data_packet[0] <= data_in;
            data_packet[375:1] <= data_packet[374:0];
    end
    
    always @(posedge latch) begin
        if(data_packet[375:360] == 16'h542c)
            sig542c <= 1'b1;
        else
            sig542c <= 1'b0;
    end
    


    assign data_out[167:160] = data_packet[351:344];
    assign data_out[159:152] = data_packet[359:352];
    assign data_out[151:144] = data_packet[335:328];
    assign data_out[143:136] = data_packet[343:336];
    assign data_out[135:128] = data_packet[327:320];
    assign data_out[127:120] = data_packet[303:296];
    assign data_out[119:112] = data_packet[279:272];
    assign data_out[111:104] = data_packet[255:248];
    assign data_out[103:96]  = data_packet[231:224];
    assign data_out[95:88]   = data_packet[207:200];
    assign data_out[87:80]   = data_packet[183:176];
    assign data_out[79:72]   = data_packet[159:152];
    assign data_out[71:64]   = data_packet[135:128];
    assign data_out[63:56]   = data_packet[111:104];
    assign data_out[55:48]   = data_packet[87:80];
    assign data_out[47:40]   = data_packet[63:56];
    assign data_out[39:32]   = data_packet[31:24];
    assign data_out[31:24]   = data_packet[39:32];
    assign data_out[23:16]   = data_packet[15:8];
    assign data_out[15:8]    = data_packet[23:16];
    assign data_out[7:0]     = data_packet[7:0];
    
endmodule