data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:36: Little bit endian vector: MSB < LSB of bit range: 0:7\ninout [0:7] gfpga_pad_GPIO_PAD;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:54: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:56: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] wl;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:88: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/logical_tile_io_mode_io_\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/logical_tile_io_mode_io_.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/logical_tile_io_mode_io_.sv\n             logical_tile_io_mode_io_\n             logical_tile_io_mode_io_.v\n             logical_tile_io_mode_io_.sv\n             obj_dir/logical_tile_io_mode_io_\n             obj_dir/logical_tile_io_mode_io_.v\n             obj_dir/logical_tile_io_mode_io_.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:95: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:102: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:109: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:116: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:123: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:130: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/grid_io_right.v:137: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module grid_io_right(gfpga_pad_GPIO_PAD,
                     left_width_0_height_0_subtile_0__pin_outpad_0_,
                     left_width_0_height_0_subtile_1__pin_outpad_0_,
                     left_width_0_height_0_subtile_2__pin_outpad_0_,
                     left_width_0_height_0_subtile_3__pin_outpad_0_,
                     left_width_0_height_0_subtile_4__pin_outpad_0_,
                     left_width_0_height_0_subtile_5__pin_outpad_0_,
                     left_width_0_height_0_subtile_6__pin_outpad_0_,
                     left_width_0_height_0_subtile_7__pin_outpad_0_,
                     bl,
                     wl,
                     left_width_0_height_0_subtile_0__pin_inpad_0_,
                     left_width_0_height_0_subtile_1__pin_inpad_0_,
                     left_width_0_height_0_subtile_2__pin_inpad_0_,
                     left_width_0_height_0_subtile_3__pin_inpad_0_,
                     left_width_0_height_0_subtile_4__pin_inpad_0_,
                     left_width_0_height_0_subtile_5__pin_inpad_0_,
                     left_width_0_height_0_subtile_6__pin_inpad_0_,
                     left_width_0_height_0_subtile_7__pin_inpad_0_);

inout [0:7] gfpga_pad_GPIO_PAD;

input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;

input [0:7] bl;

input [0:7] wl;

output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;















	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
		.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
		.bl(bl[0]),
		.wl(wl[0]),
		.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
		.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
		.bl(bl[1]),
		.wl(wl[1]),
		.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
		.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
		.bl(bl[2]),
		.wl(wl[2]),
		.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
		.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
		.bl(bl[3]),
		.wl(wl[3]),
		.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
		.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
		.bl(bl[4]),
		.wl(wl[4]),
		.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
		.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
		.bl(bl[5]),
		.wl(wl[5]),
		.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
		.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
		.bl(bl[6]),
		.wl(wl[6]),
		.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
		.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
		.bl(bl[7]),
		.wl(wl[7]),
		.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_));

endmodule
module grid_io_right(gfpga_pad_GPIO_PAD,
                     left_width_0_height_0_subtile_0__pin_outpad_0_,
                     left_width_0_height_0_subtile_1__pin_outpad_0_,
                     left_width_0_height_0_subtile_2__pin_outpad_0_,
                     left_width_0_height_0_subtile_3__pin_outpad_0_,
                     left_width_0_height_0_subtile_4__pin_outpad_0_,
                     left_width_0_height_0_subtile_5__pin_outpad_0_,
                     left_width_0_height_0_subtile_6__pin_outpad_0_,
                     left_width_0_height_0_subtile_7__pin_outpad_0_,
                     bl,
                     wl,
                     left_width_0_height_0_subtile_0__pin_inpad_0_,
                     left_width_0_height_0_subtile_1__pin_inpad_0_,
                     left_width_0_height_0_subtile_2__pin_inpad_0_,
                     left_width_0_height_0_subtile_3__pin_inpad_0_,
                     left_width_0_height_0_subtile_4__pin_inpad_0_,
                     left_width_0_height_0_subtile_5__pin_inpad_0_,
                     left_width_0_height_0_subtile_6__pin_inpad_0_,
                     left_width_0_height_0_subtile_7__pin_inpad_0_);


inout [0:7] gfpga_pad_GPIO_PAD;

input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;

input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;

input [0:7] bl;

input [0:7] wl;

output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;

output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;















	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
		.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
		.bl(bl[0]),
		.wl(wl[0]),
		.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
		.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
		.bl(bl[1]),
		.wl(wl[1]),
		.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
		.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
		.bl(bl[2]),
		.wl(wl[2]),
		.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
		.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
		.bl(bl[3]),
		.wl(wl[3]),
		.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
		.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
		.bl(bl[4]),
		.wl(wl[4]),
		.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
		.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
		.bl(bl[5]),
		.wl(wl[5]),
		.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
		.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
		.bl(bl[6]),
		.wl(wl[6]),
		.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
		.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
		.bl(bl[7]),
		.wl(wl[7]),
		.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_));

endmodule