data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/02_Multiplexers/02_2-to-1_bus_multiplexer.v
data/verilator_xmls/888b4042-b1b4-4c18-af26-371a79779d81.xml
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out
);
    
    assign out = sel ? b : a;

endmodule
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out
);

    
    assign out = sel ? b : a;

endmodule