data/full_repos/permissive/472097485/Chu03/BcdInc_03/SsegMux.v
data/verilator_xmls/f6bb9968-89b4-4501-b1b0-ddc59fcc1e19.xml
module SsegMux( input wire clk, reset, input [7:0] in2, in1, in0, output reg [2:0] an, output reg [7:0] sseg );



   localparam N = 18;


   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;



   always @(posedge clk,  posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         2'b00:
            begin
               an = 3'b110;
               sseg = in0;
            end
         2'b01:
            begin
               an =  3'b101;
               sseg = in1;
            end
         default:
            begin
               an =  3'b011;
               sseg = in2;
            end
       endcase

endmodule
module SsegMux( input wire clk, reset, input [7:0] in2, in1, in0, output reg [2:0] an, output reg [7:0] sseg );




   localparam N = 18;


   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;



   always @(posedge clk,  posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         2'b00:
            begin
               an = 3'b110;
               sseg = in0;
            end
         2'b01:
            begin
               an =  3'b101;
               sseg = in1;
            end
         default:
            begin
               an =  3'b011;
               sseg = in2;
            end
       endcase

endmodule