data/full_repos/permissive/412289941/even16_div.v
1: b'%Warning-WIDTH: data/full_repos/permissive/412289941/even16_div.v:13: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance even16_div\n        count<=1\'b0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/412289941/even16_div.v:20: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance even16_div\n            count<=1\'b0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/412289941/even16_div.v:17: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'count\' generates 4 bits.\n                                                                    : ... In instance even16_div\n        if(count<N/2-1) count <=count+1\'b1;\n                ^\n%Error: Exiting due to 3 warning(s)\n'
module even16_div(clk,rst,clk_out);
    
input clk,rst;
output clk_out;
reg clk_out;
reg[3:0] count;

parameter N=16;

always @(posedge clk or negedge rst)
    if(!rst) begin

        count<=1'b0;
        clk_out<=1'b0;
    end
    else if(N%2==0)begin
        if(count<N/2-1) count <=count+1'b1;
        else begin

            count<=1'b0;
            clk_out<=~clk_out;
        end
    end

endmodule
module even16_div(clk,rst,clk_out);

    
input clk,rst;
output clk_out;
reg clk_out;
reg[3:0] count;

parameter N=16;

always @(posedge clk or negedge rst)
    if(!rst) begin

        count<=1'b0;
        clk_out<=1'b0;
    end
    else if(N%2==0)begin
        if(count<N/2-1) count <=count+1'b1;
        else begin

            count<=1'b0;
            clk_out<=~clk_out;
        end
    end

endmodule