data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v:11: Pin not found: '__pinNumber3'\n    );\n    ^\n%Error: Exiting due to 1 error(s)\n"
module DisplayDriver_341457494561784402(
  input  [3:0] io_in,
  input        io_dot,
  output [7:0] io_out
);
  wire [6:0] _display_T_1 = 4'h0 == io_in ? 7'h3f : 7'h0;
  wire [6:0] _display_T_3 = 4'h1 == io_in ? 7'h6 : _display_T_1;
  wire [6:0] _display_T_5 = 4'h2 == io_in ? 7'h5b : _display_T_3;
  wire [6:0] _display_T_7 = 4'h3 == io_in ? 7'h4f : _display_T_5;
  wire [6:0] _display_T_9 = 4'h4 == io_in ? 7'h6e : _display_T_7;
  wire [6:0] _display_T_11 = 4'h5 == io_in ? 7'h6d : _display_T_9;
  wire [6:0] _display_T_13 = 4'h6 == io_in ? 7'h7d : _display_T_11;
  wire [6:0] _display_T_15 = 4'h7 == io_in ? 7'h7 : _display_T_13;
  wire [6:0] _display_T_17 = 4'h8 == io_in ? 7'h7f : _display_T_15;
  wire [6:0] display = 4'h9 == io_in ? 7'h6f : _display_T_17;
  assign io_out = {io_dot,display};
endmodule
module DisplayDriver_341457494561784402(
  input  [3:0] io_in,
  input        io_dot,
  output [7:0] io_out
);

  wire [6:0] _display_T_1 = 4'h0 == io_in ? 7'h3f : 7'h0;
  wire [6:0] _display_T_3 = 4'h1 == io_in ? 7'h6 : _display_T_1;
  wire [6:0] _display_T_5 = 4'h2 == io_in ? 7'h5b : _display_T_3;
  wire [6:0] _display_T_7 = 4'h3 == io_in ? 7'h4f : _display_T_5;
  wire [6:0] _display_T_9 = 4'h4 == io_in ? 7'h6e : _display_T_7;
  wire [6:0] _display_T_11 = 4'h5 == io_in ? 7'h6d : _display_T_9;
  wire [6:0] _display_T_13 = 4'h6 == io_in ? 7'h7d : _display_T_11;
  wire [6:0] _display_T_15 = 4'h7 == io_in ? 7'h7 : _display_T_13;
  wire [6:0] _display_T_17 = 4'h8 == io_in ? 7'h7f : _display_T_15;
  wire [6:0] display = 4'h9 == io_in ? 7'h6f : _display_T_17;
  assign io_out = {io_dot,display};
endmodule