data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb.v:22: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                      : ... In instance kb\n        keycode[31:0]<=31\'h00000000;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502126697/verilog/rtl/shooting_game/kb.v:27: Cannot find file containing module: \'debouncer\'\ndebouncer debounce(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/debouncer\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/debouncer.v\n             data/full_repos/permissive/502126697/verilog/rtl/shooting_game,data/full_repos/permissive/502126697/debouncer.sv\n             debouncer\n             debouncer.v\n             debouncer.sv\n             obj_dir/debouncer\n             obj_dir/debouncer.v\n             obj_dir/debouncer.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module kb(
    input ps2_clk,
    input ps2_data,
    input clk,
    output  [7:0] rx_data,
    output        valid
);
    
    
    wire kclkf, kdataf;
    reg [7:0]datacur;
    reg [3:0]cnt;
    reg [31:0]keycode;
    reg flag;
    
    initial begin
        keycode[31:0]<=31'h00000000;
        cnt<=4'b0000;
        flag<=1'b0;
    end
    
debouncer debounce(
    .clk(clk),
    .I0(ps2_clk),
    .I1(ps2_data),
    .O0(kclkf),
    .O1(kdataf)
);
    
always@(negedge(kclkf))begin
    case(cnt)
    0:;
    1:datacur[0]<=kdataf;
    2:datacur[1]<=kdataf;
    3:datacur[2]<=kdataf;
    4:datacur[3]<=kdataf;
    5:datacur[4]<=kdataf;
    6:datacur[5]<=kdataf;
    7:datacur[6]<=kdataf;
    8:datacur[7]<=kdataf;
    9:flag<=1'b1;
    10:flag<=1'b0;
    
    endcase
        if(cnt<=9) cnt<=cnt+1;
        else if(cnt==10) cnt<=0;
        
end

assign rx_data = datacur;  
assign valid = flag;  



endmodule
module kb(
    input ps2_clk,
    input ps2_data,
    input clk,
    output  [7:0] rx_data,
    output        valid
);

    
    
    wire kclkf, kdataf;
    reg [7:0]datacur;
    reg [3:0]cnt;
    reg [31:0]keycode;
    reg flag;
    
    initial begin
        keycode[31:0]<=31'h00000000;
        cnt<=4'b0000;
        flag<=1'b0;
    end
    
debouncer debounce(
    .clk(clk),
    .I0(ps2_clk),
    .I1(ps2_data),
    .O0(kclkf),
    .O1(kdataf)
);
    
always@(negedge(kclkf))begin
    case(cnt)
    0:;
    1:datacur[0]<=kdataf;
    2:datacur[1]<=kdataf;
    3:datacur[2]<=kdataf;
    4:datacur[3]<=kdataf;
    5:datacur[4]<=kdataf;
    6:datacur[5]<=kdataf;
    7:datacur[6]<=kdataf;
    8:datacur[7]<=kdataf;
    9:flag<=1'b1;
    10:flag<=1'b0;
    
    endcase
        if(cnt<=9) cnt<=cnt+1;
        else if(cnt==10) cnt<=0;
        
end

assign rx_data = datacur;  
assign valid = flag;  



endmodule