data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:10: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh.sv\n             sim_clks_rsts.vh\n             sim_clks_rsts.vh.v\n             sim_clks_rsts.vh.sv\n             obj_dir/sim_clks_rsts.vh\n             obj_dir/sim_clks_rsts.vh.v\n             obj_dir/sim_clks_rsts.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:11: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:12: Cannot find include file: sim_cvita_lib.svh\n`include "sim_cvita_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:13: Cannot find include file: sim_axis_lib.svh\n`include "sim_axis_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:14: Cannot find include file: sim_axi4_lib.svh\n`include "sim_axi4_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:15: Cannot find include file: sim_set_rb_lib.svh\n`include "sim_set_rb_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:18: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",13,1)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:18: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",13,1)\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:21: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50)   \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:22: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(GSR, 0, 100)               \n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:119: Unsupported: Ignoring delay on this delayed statement.\n      #2.5;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:121: Unsupported: Ignoring delay on this delayed statement.\n      #2.5;\n      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:335: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:335: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for reset");\n                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:339: syntax error, unexpected \'@\'\n    while (GSR) @(posedge XG_CLK_P);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:340: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE((~GSR));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:340: syntax error, unexpected \';\'\n    `TEST_CASE_DONE((~GSR));\n                           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:347: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for master channel to come up");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:347: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for master channel to come up");\n                                                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:348: syntax error, unexpected \'@\'\n    while (m_channel_up !== 1\'b1) @(posedge m_user_clk);\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:349: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1\'b1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:349: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1\'b1);\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:351: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for slave channel to come up");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:351: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for slave channel to come up");\n                                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:352: syntax error, unexpected \'@\'\n    while (s_channel_up !== 1\'b1) @(posedge s_user_clk);\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:353: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1\'b1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:353: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1\'b1);\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:371: syntax error, unexpected \'@\'\n   repeat(2000) @(posedge m_user_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:438: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:438: syntax error, unexpected \';\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");\n                                                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:443: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:443: syntax error, unexpected \',\'\n      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:444: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:444: syntax error, unexpected \',\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:445: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:445: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:447: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:447: syntax error, unexpected \';\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");\n                                                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:452: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:452: syntax error, unexpected \',\'\n      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:453: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:453: syntax error, unexpected \',\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:454: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:454: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:460: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Concurrent read and write (single packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:460: syntax error, unexpected \';\'\n    `TEST_CASE_START("Concurrent read and write (single packet)");\n                                                                 ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:462: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:471: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:471: syntax error, unexpected \',\'\n    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:472: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:472: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv:474: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Concurrent read and write (multiple packets)");\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ten_gig_eth_loopback_tb();
  `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50)
  `DEFINE_RESET(GSR, 0, 100)

  wire XG_CLK_N = ~XG_CLK_P;
  wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N;


  localparam PORTNUM = 8'd0;












  wire xgige_refclk, xgige_clk156, xgige_dclk;
  wire m_user_clk, s_user_clk;
  wire m_channel_up, s_channel_up;

  wire [63:0] m_xgmii_txd;
  wire [7:0]  m_xgmii_txc;
  wire [63:0] m_xgmii_rxd;
  wire [7:0]  m_xgmii_rxc;
  wire [63:0] s_xgmii_txd;
  wire [7:0]  s_xgmii_txc;
  wire [63:0] s_xgmii_rxd;
  wire [7:0]  s_xgmii_rxc;
  wire [7:0]  m_xgmii_status;
  wire [7:0]  s_xgmii_status;
  wire        m_xge_phy_resetdone;
  wire        s_xge_phy_resetdone;
  wire        m_mdc, m_mdio_in, m_mdio_out;
  wire        s_mdc, s_mdio_in, s_mdio_out;
  wire        sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable;


  wire [15:0] m_phy_status;
  wire [15:0] s_phy_status;
  wire [63:0] loop_tdata;
  wire [3:0]  loop_tuser;
  wire        loop_tlast, loop_tvalid, loop_tready;

  wire [7:0]      wb_adr_i;
  wire            wb_cyc_i;
  wire [31:0]     wb_dat_i;
  wire            wb_stb_i;
  wire            wb_we_i;
  wire            wb_ack_o;
  wire [31:0]     wb_dat_o;
  wire            wb_int_o;













  reg independent_clock;
  assign m_channel_up = m_phy_status[0];
  assign s_channel_up = s_phy_status[0];


  assign m_user_clk = independent_clock;
  assign s_user_clk = independent_clock;

   ten_gige_phy_clk_gen xgige_clk_gen_i (
      .areset(GSR),
      .refclk_p(XG_CLK_P),
      .refclk_n(XG_CLK_N),
      .refclk(xgige_refclk),
      .clk156(xgige_clk156),
      .dclk(xgige_dclk)
   );

  cvita_master m_tx_chdr (.clk(m_user_clk));
  cvita_slave s_rx_chdr (.clk(s_user_clk));





  initial
  begin
    independent_clock <= 1'b0;
    forever
    begin
      independent_clock <= 1'b0;
      #2.5;
      independent_clock <= 1'b1;
      #2.5;
    end
  end

  assign sfpp_rxlos = 1'b0;
  assign sfpp_tx_fault = 1'b0;


  ten_gig_eth_pcs_pma_gt_common # (
      .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") )
  ten_gig_eth_pcs_pma_gt_common_block
    (
     .refclk(xgige_refclk),
     .qpllreset(qpllreset),
     .qplllock(qplllock),
     .qplloutclk(qplloutclk),
     .qplloutrefclk(qplloutrefclk),
     .qpllrefclksel(3'b001)
    );

      ten_gige_phy ten_gige_phy_master_i
      (

         .areset(GSR),
         .refclk(xgige_refclk),
         .clk156(xgige_clk156),
         .dclk(xgige_dclk),
         .sim_speedup_control(~GSR),

         .xgmii_txd(m_xgmii_txd),
         .xgmii_txc(m_xgmii_txc),
         .xgmii_rxd(m_xgmii_rxd),
         .xgmii_rxc(m_xgmii_rxc),

         .txp(SFP_LN0_P),
         .txn(SFP_LN0_N),
         .rxp(SFP_LN1_P),
         .rxn(SFP_LN1_N),

         .mdc(m_mdc),
         .mdio_in(m_mdio_in),
         .mdio_out(m_mdio_out),
         .mdio_tri(),
         .prtad(5'd4),

         .core_status(m_xgmii_status),
         .resetdone(m_xge_phy_resetdone),
         .signal_detect(~sfpp_rxlos),
         .tx_fault(sfpp_tx_fault),
         .tx_disable(),
         .qpllreset(qpllreset1),
         .qplllock(qplllock),
         .qplloutclk(qplloutclk),
         .qplloutrefclk(qplloutrefclk)

      );

      n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i
      (

         .xgmii_clk(xgige_clk156),
         .xgmii_txd(m_xgmii_txd),
         .xgmii_txc(m_xgmii_txc),
         .xgmii_rxd(m_xgmii_rxd),
         .xgmii_rxc(m_xgmii_rxc),

         .sys_clk(m_user_clk),
         .sys_rst(GSR),












         .rx_tdata(s_rx_chdr.axis.tdata),
         .rx_tuser(),
         .rx_tlast(s_rx_chdr.axis.tlast),
         .rx_tvalid(s_rx_chdr.axis.tvalid),
         .rx_tready(s_rx_chdr.axis.tready),
         .tx_tdata(m_tx_chdr.axis.tdata),
         .tx_tuser(4'd4),
         .tx_tlast(m_tx_chdr.axis.tlast),
         .tx_tvalid(m_tx_chdr.axis.tvalid),
         .tx_tready(m_tx_chdr.axis.tready),

         .phy_ready(m_xge_phy_resetdone),
         .ctrl_tx_enable         (1'b1),
         .status_crc_error       (),
         .status_fragment_error  (),
         .status_txdfifo_ovflow  (),
         .status_txdfifo_udflow  (),
         .status_rxdfifo_ovflow  (),
         .status_rxdfifo_udflow  (),
         .status_pause_frame_rx  (),
         .status_local_fault     (),
         .status_remote_fault    ()
      );

      assign m_phy_status  = {8'h00, m_xgmii_status};



























     ten_gige_phy ten_gige_phy_slave_i
      (

         .areset(GSR),
         .refclk(xgige_refclk),
         .clk156(xgige_clk156),
         .dclk(xgige_dclk),
         .sim_speedup_control(~GSR),

         .xgmii_txd(s_xgmii_txd),
         .xgmii_txc(s_xgmii_txc),
         .xgmii_rxd(s_xgmii_rxd),
         .xgmii_rxc(s_xgmii_rxc),

         .txp(SFP_LN1_P),
         .txn(SFP_LN1_N),
         .rxp(SFP_LN0_P),
         .rxn(SFP_LN0_N),

         .mdc(s_mdc),
         .mdio_in(s_mdio_in),
         .mdio_out(s_mdio_out),
         .mdio_tri(),
         .prtad(5'd4),

         .core_status(s_xgmii_status),
         .resetdone(s_xge_phy_resetdone),
         .signal_detect(~sfpp_rxlos),
         .tx_fault(sfpp_tx_fault),
         .tx_disable(),
         .qpllreset(qpllreset2),
         .qplllock(qplllock),
         .qplloutclk(qplloutclk),
         .qplloutrefclk(qplloutrefclk)
      );

      n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i
      (

         .xgmii_clk(xgige_clk156),
         .xgmii_txd(s_xgmii_txd),
         .xgmii_txc(s_xgmii_txc),
         .xgmii_rxd(s_xgmii_rxd),
         .xgmii_rxc(s_xgmii_rxc),

         .sys_clk(s_user_clk),
         .sys_rst(GSR),
         .rx_tdata(loop_tdata),
         .rx_tuser(loop_tuser),
         .rx_tlast(loop_tlast),
         .rx_tvalid(loop_tvalid),
         .rx_tready(loop_tready),
         .tx_tdata(loop_tdata),
         .tx_tuser(loop_tuser),
         .tx_tlast(loop_tlast),
         .tx_tvalid(loop_tvalid),
         .tx_tready(loop_tready),

         .phy_ready(s_xge_phy_resetdone),
         .ctrl_tx_enable         (1'b1),
         .status_crc_error       (),
         .status_fragment_error  (),
         .status_txdfifo_ovflow  (),
         .status_txdfifo_udflow  (),
         .status_rxdfifo_ovflow  (),
         .status_rxdfifo_udflow  (),
         .status_pause_frame_rx  (),
         .status_local_fault     (),
         .status_remote_fault    ()
      );

      assign s_phy_status  = {8'h00, s_xgmii_status};


  cvita_hdr_t   header, header_out;
  cvita_stats_t stats;
  logic [63:0]  crc_cache;




  initial begin : tb_main
    `TEST_CASE_START("Wait for reset");



    while (GSR) @(posedge XG_CLK_P);
    `TEST_CASE_DONE((~GSR));

    m_tx_chdr.push_bubble();




    `TEST_CASE_START("Wait for master channel to come up");
    while (m_channel_up !== 1'b1) @(posedge m_user_clk);
    `TEST_CASE_DONE(1'b1);

    `TEST_CASE_START("Wait for slave channel to come up");
    while (s_channel_up !== 1'b1) @(posedge s_user_clk);
    `TEST_CASE_DONE(1'b1);

















   repeat(2000) @(posedge m_user_clk);






























































    header = '{
      pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    header = '{
      pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Concurrent read and write (single packet)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header);
        end
        begin
          s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
        end
      join
    crc_cache = stats.crc;
    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Concurrent read and write (multiple packets)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          repeat (20) begin
            m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header);
            m_tx_chdr.push_bubble();
          end
        end
        begin
          repeat (20) begin
            s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
            `ASSERT_ERROR(stats.count==20,      "Bad packet: Length mismatch");
            `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC");
          end
        end
      join
    `TEST_CASE_DONE(1);

































  end

endmodule
module ten_gig_eth_loopback_tb();

  `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50)
  `DEFINE_RESET(GSR, 0, 100)

  wire XG_CLK_N = ~XG_CLK_P;
  wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N;


  localparam PORTNUM = 8'd0;












  wire xgige_refclk, xgige_clk156, xgige_dclk;
  wire m_user_clk, s_user_clk;
  wire m_channel_up, s_channel_up;

  wire [63:0] m_xgmii_txd;
  wire [7:0]  m_xgmii_txc;
  wire [63:0] m_xgmii_rxd;
  wire [7:0]  m_xgmii_rxc;
  wire [63:0] s_xgmii_txd;
  wire [7:0]  s_xgmii_txc;
  wire [63:0] s_xgmii_rxd;
  wire [7:0]  s_xgmii_rxc;
  wire [7:0]  m_xgmii_status;
  wire [7:0]  s_xgmii_status;
  wire        m_xge_phy_resetdone;
  wire        s_xge_phy_resetdone;
  wire        m_mdc, m_mdio_in, m_mdio_out;
  wire        s_mdc, s_mdio_in, s_mdio_out;
  wire        sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable;


  wire [15:0] m_phy_status;
  wire [15:0] s_phy_status;
  wire [63:0] loop_tdata;
  wire [3:0]  loop_tuser;
  wire        loop_tlast, loop_tvalid, loop_tready;

  wire [7:0]      wb_adr_i;
  wire            wb_cyc_i;
  wire [31:0]     wb_dat_i;
  wire            wb_stb_i;
  wire            wb_we_i;
  wire            wb_ack_o;
  wire [31:0]     wb_dat_o;
  wire            wb_int_o;













  reg independent_clock;
  assign m_channel_up = m_phy_status[0];
  assign s_channel_up = s_phy_status[0];


  assign m_user_clk = independent_clock;
  assign s_user_clk = independent_clock;

   ten_gige_phy_clk_gen xgige_clk_gen_i (
      .areset(GSR),
      .refclk_p(XG_CLK_P),
      .refclk_n(XG_CLK_N),
      .refclk(xgige_refclk),
      .clk156(xgige_clk156),
      .dclk(xgige_dclk)
   );

  cvita_master m_tx_chdr (.clk(m_user_clk));
  cvita_slave s_rx_chdr (.clk(s_user_clk));





  initial
  begin
    independent_clock <= 1'b0;
    forever
    begin
      independent_clock <= 1'b0;
      #2.5;
      independent_clock <= 1'b1;
      #2.5;
    end
  end

  assign sfpp_rxlos = 1'b0;
  assign sfpp_tx_fault = 1'b0;


  ten_gig_eth_pcs_pma_gt_common # (
      .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") )
  ten_gig_eth_pcs_pma_gt_common_block
    (
     .refclk(xgige_refclk),
     .qpllreset(qpllreset),
     .qplllock(qplllock),
     .qplloutclk(qplloutclk),
     .qplloutrefclk(qplloutrefclk),
     .qpllrefclksel(3'b001)
    );

      ten_gige_phy ten_gige_phy_master_i
      (

         .areset(GSR),
         .refclk(xgige_refclk),
         .clk156(xgige_clk156),
         .dclk(xgige_dclk),
         .sim_speedup_control(~GSR),

         .xgmii_txd(m_xgmii_txd),
         .xgmii_txc(m_xgmii_txc),
         .xgmii_rxd(m_xgmii_rxd),
         .xgmii_rxc(m_xgmii_rxc),

         .txp(SFP_LN0_P),
         .txn(SFP_LN0_N),
         .rxp(SFP_LN1_P),
         .rxn(SFP_LN1_N),

         .mdc(m_mdc),
         .mdio_in(m_mdio_in),
         .mdio_out(m_mdio_out),
         .mdio_tri(),
         .prtad(5'd4),

         .core_status(m_xgmii_status),
         .resetdone(m_xge_phy_resetdone),
         .signal_detect(~sfpp_rxlos),
         .tx_fault(sfpp_tx_fault),
         .tx_disable(),
         .qpllreset(qpllreset1),
         .qplllock(qplllock),
         .qplloutclk(qplloutclk),
         .qplloutrefclk(qplloutrefclk)

      );

      n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i
      (

         .xgmii_clk(xgige_clk156),
         .xgmii_txd(m_xgmii_txd),
         .xgmii_txc(m_xgmii_txc),
         .xgmii_rxd(m_xgmii_rxd),
         .xgmii_rxc(m_xgmii_rxc),

         .sys_clk(m_user_clk),
         .sys_rst(GSR),












         .rx_tdata(s_rx_chdr.axis.tdata),
         .rx_tuser(),
         .rx_tlast(s_rx_chdr.axis.tlast),
         .rx_tvalid(s_rx_chdr.axis.tvalid),
         .rx_tready(s_rx_chdr.axis.tready),
         .tx_tdata(m_tx_chdr.axis.tdata),
         .tx_tuser(4'd4),
         .tx_tlast(m_tx_chdr.axis.tlast),
         .tx_tvalid(m_tx_chdr.axis.tvalid),
         .tx_tready(m_tx_chdr.axis.tready),

         .phy_ready(m_xge_phy_resetdone),
         .ctrl_tx_enable         (1'b1),
         .status_crc_error       (),
         .status_fragment_error  (),
         .status_txdfifo_ovflow  (),
         .status_txdfifo_udflow  (),
         .status_rxdfifo_ovflow  (),
         .status_rxdfifo_udflow  (),
         .status_pause_frame_rx  (),
         .status_local_fault     (),
         .status_remote_fault    ()
      );

      assign m_phy_status  = {8'h00, m_xgmii_status};



























     ten_gige_phy ten_gige_phy_slave_i
      (

         .areset(GSR),
         .refclk(xgige_refclk),
         .clk156(xgige_clk156),
         .dclk(xgige_dclk),
         .sim_speedup_control(~GSR),

         .xgmii_txd(s_xgmii_txd),
         .xgmii_txc(s_xgmii_txc),
         .xgmii_rxd(s_xgmii_rxd),
         .xgmii_rxc(s_xgmii_rxc),

         .txp(SFP_LN1_P),
         .txn(SFP_LN1_N),
         .rxp(SFP_LN0_P),
         .rxn(SFP_LN0_N),

         .mdc(s_mdc),
         .mdio_in(s_mdio_in),
         .mdio_out(s_mdio_out),
         .mdio_tri(),
         .prtad(5'd4),

         .core_status(s_xgmii_status),
         .resetdone(s_xge_phy_resetdone),
         .signal_detect(~sfpp_rxlos),
         .tx_fault(sfpp_tx_fault),
         .tx_disable(),
         .qpllreset(qpllreset2),
         .qplllock(qplllock),
         .qplloutclk(qplloutclk),
         .qplloutrefclk(qplloutrefclk)
      );

      n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i
      (

         .xgmii_clk(xgige_clk156),
         .xgmii_txd(s_xgmii_txd),
         .xgmii_txc(s_xgmii_txc),
         .xgmii_rxd(s_xgmii_rxd),
         .xgmii_rxc(s_xgmii_rxc),

         .sys_clk(s_user_clk),
         .sys_rst(GSR),
         .rx_tdata(loop_tdata),
         .rx_tuser(loop_tuser),
         .rx_tlast(loop_tlast),
         .rx_tvalid(loop_tvalid),
         .rx_tready(loop_tready),
         .tx_tdata(loop_tdata),
         .tx_tuser(loop_tuser),
         .tx_tlast(loop_tlast),
         .tx_tvalid(loop_tvalid),
         .tx_tready(loop_tready),

         .phy_ready(s_xge_phy_resetdone),
         .ctrl_tx_enable         (1'b1),
         .status_crc_error       (),
         .status_fragment_error  (),
         .status_txdfifo_ovflow  (),
         .status_txdfifo_udflow  (),
         .status_rxdfifo_ovflow  (),
         .status_rxdfifo_udflow  (),
         .status_pause_frame_rx  (),
         .status_local_fault     (),
         .status_remote_fault    ()
      );

      assign s_phy_status  = {8'h00, s_xgmii_status};


  cvita_hdr_t   header, header_out;
  cvita_stats_t stats;
  logic [63:0]  crc_cache;




  initial begin : tb_main
    `TEST_CASE_START("Wait for reset");



    while (GSR) @(posedge XG_CLK_P);
    `TEST_CASE_DONE((~GSR));

    m_tx_chdr.push_bubble();




    `TEST_CASE_START("Wait for master channel to come up");
    while (m_channel_up !== 1'b1) @(posedge m_user_clk);
    `TEST_CASE_DONE(1'b1);

    `TEST_CASE_START("Wait for slave channel to come up");
    while (s_channel_up !== 1'b1) @(posedge s_user_clk);
    `TEST_CASE_DONE(1'b1);

















   repeat(2000) @(posedge m_user_clk);






























































    header = '{
      pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    header = '{
      pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Concurrent read and write (single packet)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header);
        end
        begin
          s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
        end
      join
    crc_cache = stats.crc;
    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Concurrent read and write (multiple packets)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          repeat (20) begin
            m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header);
            m_tx_chdr.push_bubble();
          end
        end
        begin
          repeat (20) begin
            s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
            `ASSERT_ERROR(stats.count==20,      "Bad packet: Length mismatch");
            `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC");
          end
        end
      join
    `TEST_CASE_DONE(1);

































  end

endmodule