data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv
139: b"%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:5: Unsupported: classes\nclass dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:5: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;\n                                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:23: syntax error, unexpected rand\n  rand bit zero_delays;\n  ^~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: 'constraint'\n  constraint zero_delays_c {\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:26: syntax error, unexpected IDENTIFIER\n  constraint zero_delays_c {\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n    zero_delays dist {1'b0 := 6, 1'b1 := 4};\n                ^~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:32: syntax error, unexpected IDENTIFIER\n  dv_base_reg_block                 ral_models[string];\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:39: Unsupported: Hierarchical class references\n  string ral_model_names[$] = {RAL_T::type_name};\n                                    ^~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv:39: Unsupported: scoped class reference\n  string ral_model_names[$] = {RAL_T::type_name};\n                                      ^~~~~~~~~\nSegmentation fault\n%Error: Command Failed /usr/bin/verilator_bin --xml-output data/verilator_xmls/7c61ae06-6a70-44d7-8abe-b3d3bf6710ff.xml --y data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib\\,data/full_repos/permissive/509468557 data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv\n"
function void create_ral_models(bit [bus_params_pkg::BUS_AW-1:0] csr_base_addr = '1);

    foreach (ral_model_names[i]) begin
      string ral_name = ral_model_names[i];
      uvm_reg_addr_t base_addr;
      dv_base_reg_block reg_blk = create_ral_by_name(ral_name);

      if (reg_blk.get_name() == RAL_T::type_name) `downcast(ral, reg_blk)



      reg_blk.build(.base_addr(0), .csr_excl(null));
      apply_ral_fixes();
      reg_blk.lock_model();







      base_addr = (&csr_base_addr ?
                   {`UVM_REG_ADDR_WIDTH{1'b1}} :
                   {{(`UVM_REG_ADDR_WIDTH - bus_params_pkg::BUS_AW){1'b0}}, csr_base_addr});
      reg_blk.set_base_addr(base_addr);


      reg_blk.compute_mapped_addr_ranges();
      reg_blk.compute_unmapped_addr_ranges();
      `uvm_info(msg_id,
                $sformatf("RAL[%0s] mapped addresses: %0p",
                          ral_name, reg_blk.mapped_addr_ranges),
                UVM_HIGH)
      `uvm_info(msg_id,
                $sformatf("RAL[%0s] unmapped addresses: %0p",
                          ral_name, reg_blk.unmapped_addr_ranges),
                UVM_HIGH)
      ral_models[ral_name] = reg_blk;
    end

    if (ral_model_names.size > 0) begin
      `DV_CHECK_FATAL(ral_models.exists(RAL_T::type_name))
    end
  endfunction
function void create_ral_models(bit [bus_params_pkg::BUS_AW-1:0] csr_base_addr = '1);


    foreach (ral_model_names[i]) begin
      string ral_name = ral_model_names[i];
      uvm_reg_addr_t base_addr;
      dv_base_reg_block reg_blk = create_ral_by_name(ral_name);

      if (reg_blk.get_name() == RAL_T::type_name) `downcast(ral, reg_blk)



      reg_blk.build(.base_addr(0), .csr_excl(null));
      apply_ral_fixes();
      reg_blk.lock_model();







      base_addr = (&csr_base_addr ?
                   {`UVM_REG_ADDR_WIDTH{1'b1}} :
                   {{(`UVM_REG_ADDR_WIDTH - bus_params_pkg::BUS_AW){1'b0}}, csr_base_addr});
      reg_blk.set_base_addr(base_addr);


      reg_blk.compute_mapped_addr_ranges();
      reg_blk.compute_unmapped_addr_ranges();
      `uvm_info(msg_id,
                $sformatf("RAL[%0s] mapped addresses: %0p",
                          ral_name, reg_blk.mapped_addr_ranges),
                UVM_HIGH)
      `uvm_info(msg_id,
                $sformatf("RAL[%0s] unmapped addresses: %0p",
                          ral_name, reg_blk.unmapped_addr_ranges),
                UVM_HIGH)
      ral_models[ral_name] = reg_blk;
    end

    if (ral_model_names.size > 0) begin
      `DV_CHECK_FATAL(ral_models.exists(RAL_T::type_name))
    end
  endfunction