data/full_repos/permissive/521748416/functional_netlisting/clk_gate.v
1: b'%Error: data/full_repos/permissive/521748416/functional_netlisting/clk_gate.v:25: Cannot find include file: sp_verilog.vh\n`include "sp_verilog.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521748416/functional_netlisting,data/full_repos/permissive/521748416/sp_verilog.vh\n             data/full_repos/permissive/521748416/functional_netlisting,data/full_repos/permissive/521748416/sp_verilog.vh.v\n             data/full_repos/permissive/521748416/functional_netlisting,data/full_repos/permissive/521748416/sp_verilog.vh.sv\n             sp_verilog.vh\n             sp_verilog.vh.v\n             sp_verilog.vh.sv\n             obj_dir/sp_verilog.vh\n             obj_dir/sp_verilog.vh.v\n             obj_dir/sp_verilog.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);

   assign gated_clk = free_clk;
endmodule
module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);


   assign gated_clk = free_clk;
endmodule