data/full_repos/permissive/436253691/hardware/rtl/RAM_SIMUL.v
1: b'%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/rtl/RAM_SIMUL.v:84: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Q_temp\' generates 8 bits.\n                                                                                : ... In instance RAM_SIMUL\nassign RAM_SIM_Data_Out = RAM_SIM_Oe == 1\'b1 ? Q_temp : \'hz;\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/rtl/RAM_SIMUL.v:84: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                : ... In instance RAM_SIMUL\nassign RAM_SIM_Data_Out = RAM_SIM_Oe == 1\'b1 ? Q_temp : \'hz;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module RAM_SIMUL #(parameter DATA_WIDTH = 8, MEM_SIZE=1024  ,ADDR_WIDTH = 10, IFPATH="")
(

RAM_SIM_Clk,
RAM_SIM_We,
RAM_SIM_Oe,
RAM_SIM_Address, 
RAM_SIM_Data_In,


RAM_SIM_Data_Out
);





input RAM_SIM_Clk;
input RAM_SIM_We;
input RAM_SIM_Oe;
input [ADDR_WIDTH-1:0] RAM_SIM_Address;
input [DATA_WIDTH-1:0] RAM_SIM_Data_In;
output [DATA_WIDTH-1:0] RAM_SIM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [DATA_WIDTH-1:0] Q_temp;





initial 
begin
	$display("Loading Ram...");
	$readmemh(IFPATH,Ram_Array);
	$display("Ram successfully loaded.");
end





always@(posedge RAM_SIM_Clk)
begin
	
	if(RAM_SIM_We) begin
		Ram_Array[RAM_SIM_Address]<=RAM_SIM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_SIM_Address];
	
end





assign RAM_SIM_Data_Out = RAM_SIM_Oe == 1'b1 ? Q_temp : 'hz;



endmodule
module RAM_SIMUL #(parameter DATA_WIDTH = 8, MEM_SIZE=1024  ,ADDR_WIDTH = 10, IFPATH="")
(

RAM_SIM_Clk,
RAM_SIM_We,
RAM_SIM_Oe,
RAM_SIM_Address, 
RAM_SIM_Data_In,


RAM_SIM_Data_Out
);






input RAM_SIM_Clk;
input RAM_SIM_We;
input RAM_SIM_Oe;
input [ADDR_WIDTH-1:0] RAM_SIM_Address;
input [DATA_WIDTH-1:0] RAM_SIM_Data_In;
output [DATA_WIDTH-1:0] RAM_SIM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [DATA_WIDTH-1:0] Q_temp;





initial 
begin
	$display("Loading Ram...");
	$readmemh(IFPATH,Ram_Array);
	$display("Ram successfully loaded.");
end





always@(posedge RAM_SIM_Clk)
begin
	
	if(RAM_SIM_We) begin
		Ram_Array[RAM_SIM_Address]<=RAM_SIM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_SIM_Address];
	
end





assign RAM_SIM_Data_Out = RAM_SIM_Oe == 1'b1 ? Q_temp : 'hz;



endmodule