data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v
1: b"%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v:100: Cannot find file containing module: 'my_fifo2'\n  my_fifo2 fifo2(.clk(clk),.rst(rst),.rd_en(rd_en2),.wr_en(wr_en2),\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/my_fifo2\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/my_fifo2.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/my_fifo2.sv\n             my_fifo2\n             my_fifo2.v\n             my_fifo2.sv\n             obj_dir/my_fifo2\n             obj_dir/my_fifo2.v\n             obj_dir/my_fifo2.sv\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v:104: Cannot find file containing module: 'my_fifo2'\n  my_fifo2 fifo1(.clk(clk),.rst(rst),.rd_en(rd_en1),.wr_en(wr_en1),\n  ^~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v:108: Cannot find file containing module: 'shift_register_3'\n  shift_register_3 sr1(.clk(clk),.din(test1),.rst(rst),.dout0(dout3),.dout1(dout2),.dout2(dout1));\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v:110: Cannot find file containing module: 'shift_register_3'\n  shift_register_3 sr2(.clk(clk),.din(test2),.rst(rst),.dout0(dout6),.dout1(dout5),.dout2(dout4));\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/block3x3_2.v:112: Cannot find file containing module: 'shift_register_3'\n  shift_register_3 sr3(.clk(clk),.din(din2),.rst(rst),.dout0(dout9),.dout1(dout8),.dout2(dout7));\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module block3x3_2(clk, rst, din, dout1, dout2, dout3, dout4, dout5, dout6, dout7, 
                   dout8, dout9, start_flag); 
    input clk;
    input rst;
	input  [7:0] din;
    output [7:0] dout1;
    output [7:0] dout2;
    output [7:0] dout3;
    output [7:0] dout4;
    output [7:0] dout5;
    output [7:0] dout6;
    output [7:0] dout7;
    output [7:0] dout8;
    output [7:0] dout9;

	 output start_flag;
										  
	 wire [7:0] test1;
	 wire [7:0] test2;

	 wire [7:0] dout1;
	 wire [7:0] dout2;
	 wire [7:0] dout3;
	 wire [7:0] dout4;
	 wire [7:0] dout5;
	 wire [7:0] dout6;
	 wire [7:0] dout7;
	 wire [7:0] dout8;
	 wire [7:0] dout9;
	
	 reg [9:0] cnt;

	 reg full2_flag;
	 reg full1_flag;

	 reg wr_en2;
	 wire rd_en2;
	 wire wr_en1;
	 wire rd_en1;

	 reg[7:0] din1;
	 reg[7:0] din2;

	 wire empty2,full2;
	 wire empty1,full1;

	 always@(posedge clk or negedge rst)
	 begin
	 	if(!rst)
		begin
			cnt<=0;
			din1<=0;
		    din2<=0;

			wr_en2<=0;

			full2_flag<=0;
			full1_flag<=0;
		end

		else
		begin
			begin
				wr_en2<=1;
				din2<=din;
				if(full2)
					full2_flag<=1;

				if(full1)
					full1_flag<=1;
				
				if(cnt<1000)
					cnt<=cnt+1;
			end
		end
	 end
	
	 
	 assign rd_en1=full1_flag;
	 assign rd_en2=full2_flag;
	 assign wr_en1=full2_flag;
	 assign start_flag=(cnt>514);


	 my_fifo2 fifo2(.clk(clk),.rst(rst),.rd_en(rd_en2),.wr_en(wr_en2),
	 						 .din(din2),.dout(test2),.empty(empty2),.full(full2));


	 my_fifo2 fifo1(.clk(clk),.rst(rst),.rd_en(rd_en1),.wr_en(wr_en1),
	 						 .din(test2),.dout(test1),.empty(empty1),.full(full1));


	 shift_register_3 sr1(.clk(clk),.din(test1),.rst(rst),.dout0(dout3),.dout1(dout2),.dout2(dout1));

	 shift_register_3 sr2(.clk(clk),.din(test2),.rst(rst),.dout0(dout6),.dout1(dout5),.dout2(dout4));

	 shift_register_3 sr3(.clk(clk),.din(din2),.rst(rst),.dout0(dout9),.dout1(dout8),.dout2(dout7));


endmodule
module block3x3_2(clk, rst, din, dout1, dout2, dout3, dout4, dout5, dout6, dout7, 
                   dout8, dout9, start_flag);
 
    input clk;
    input rst;
	input  [7:0] din;
    output [7:0] dout1;
    output [7:0] dout2;
    output [7:0] dout3;
    output [7:0] dout4;
    output [7:0] dout5;
    output [7:0] dout6;
    output [7:0] dout7;
    output [7:0] dout8;
    output [7:0] dout9;

	 output start_flag;
										  
	 wire [7:0] test1;
	 wire [7:0] test2;

	 wire [7:0] dout1;
	 wire [7:0] dout2;
	 wire [7:0] dout3;
	 wire [7:0] dout4;
	 wire [7:0] dout5;
	 wire [7:0] dout6;
	 wire [7:0] dout7;
	 wire [7:0] dout8;
	 wire [7:0] dout9;
	
	 reg [9:0] cnt;

	 reg full2_flag;
	 reg full1_flag;

	 reg wr_en2;
	 wire rd_en2;
	 wire wr_en1;
	 wire rd_en1;

	 reg[7:0] din1;
	 reg[7:0] din2;

	 wire empty2,full2;
	 wire empty1,full1;

	 always@(posedge clk or negedge rst)
	 begin
	 	if(!rst)
		begin
			cnt<=0;
			din1<=0;
		    din2<=0;

			wr_en2<=0;

			full2_flag<=0;
			full1_flag<=0;
		end

		else
		begin
			begin
				wr_en2<=1;
				din2<=din;
				if(full2)
					full2_flag<=1;

				if(full1)
					full1_flag<=1;
				
				if(cnt<1000)
					cnt<=cnt+1;
			end
		end
	 end
	
	 
	 assign rd_en1=full1_flag;
	 assign rd_en2=full2_flag;
	 assign wr_en1=full2_flag;
	 assign start_flag=(cnt>514);


	 my_fifo2 fifo2(.clk(clk),.rst(rst),.rd_en(rd_en2),.wr_en(wr_en2),
	 						 .din(din2),.dout(test2),.empty(empty2),.full(full2));


	 my_fifo2 fifo1(.clk(clk),.rst(rst),.rd_en(rd_en1),.wr_en(wr_en1),
	 						 .din(test2),.dout(test1),.empty(empty1),.full(full1));


	 shift_register_3 sr1(.clk(clk),.din(test1),.rst(rst),.dout0(dout3),.dout1(dout2),.dout2(dout1));

	 shift_register_3 sr2(.clk(clk),.din(test2),.rst(rst),.dout0(dout6),.dout1(dout5),.dout2(dout4));

	 shift_register_3 sr3(.clk(clk),.din(din2),.rst(rst),.dout0(dout9),.dout1(dout8),.dout2(dout7));


endmodule