data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:30: Unsupported: Ignoring delay on this delayed statement.\n#0 Clock=1\'b0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:31: Unsupported: Ignoring delay on this delayed statement.\n#5 RD=4\'d8; WriteData = 16\'d5; RegWrite=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:32: Unsupported: Ignoring delay on this delayed statement.\n#5 Clock=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:33: Unsupported: Ignoring delay on this delayed statement.\n#5 Clock=1\'b0;RegWrite = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:34: Unsupported: Ignoring delay on this delayed statement.\n#5 RD=4\'d9; WriteData = 16\'d7; RegWrite=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:35: Unsupported: Ignoring delay on this delayed statement.\n#5 Clock=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:36: Unsupported: Ignoring delay on this delayed statement.\n#5 Clock=1\'b0; RegWrite=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5 RS=4\'d8; RT=4\'d9;\n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:38: Unsupported: Ignoring delay on this delayed statement.\n#5 $stop;\n^\n%Error: data/full_repos/permissive/508266496/simulation/RegisterFile_Test.v:40: Cannot find file containing module: \'RegisterFile\'\nRegisterFile RF(RS, RT, RD, WriteData, ReadRS, ReadRT, RegWrite, Clock);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/RegisterFile\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/RegisterFile.v\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/RegisterFile.sv\n             RegisterFile\n             RegisterFile.v\n             RegisterFile.sv\n             obj_dir/RegisterFile\n             obj_dir/RegisterFile.v\n             obj_dir/RegisterFile.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFile_Test();
reg[3:0] RS, RT, RD;
reg RegWrite, Clock;
reg[15:0] WriteData;
wire[15:0] ReadRS, ReadRT;
initial
begin
#0 Clock=1'b0;
#5 RD=4'd8; WriteData = 16'd5; RegWrite=1'b1;
#5 Clock=1'b1;
#5 Clock=1'b0;RegWrite = 1'b1;
#5 RD=4'd9; WriteData = 16'd7; RegWrite=1'b1;
#5 Clock=1'b1;
#5 Clock=1'b0; RegWrite=0;
#5 RS=4'd8; RT=4'd9;
#5 $stop;
end
RegisterFile RF(RS, RT, RD, WriteData, ReadRS, ReadRT, RegWrite, Clock);
endmodule
module RegisterFile_Test();

reg[3:0] RS, RT, RD;
reg RegWrite, Clock;
reg[15:0] WriteData;
wire[15:0] ReadRS, ReadRT;
initial
begin
#0 Clock=1'b0;
#5 RD=4'd8; WriteData = 16'd5; RegWrite=1'b1;
#5 Clock=1'b1;
#5 Clock=1'b0;RegWrite = 1'b1;
#5 RD=4'd9; WriteData = 16'd7; RegWrite=1'b1;
#5 Clock=1'b1;
#5 Clock=1'b0; RegWrite=0;
#5 RS=4'd8; RT=4'd9;
#5 $stop;
end
RegisterFile RF(RS, RT, RD, WriteData, ReadRS, ReadRT, RegWrite, Clock);
endmodule