data/full_repos/permissive/429196919/FPGA/pulse/pulse.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:34: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/pulse,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/pulse,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/pulse,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:43: Define or directive not defined: \'`MASTER_CLK_CYC_PER_MS\'\n reg [$clog2(`MASTER_CLK_CYC_PER_MS)-1:0] cnt1k = 0;         \n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n reg [$clog2(`MASTER_CLK_CYC_PER_MS)-1:0] cnt1k = 0;         \n                                   ^\n%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:69: Define or directive not defined: \'`MASTER_CLK_CYC_PER_MS\'\n  else if(cnt1k >= `MASTER_CLK_CYC_PER_MS) begin         \n                   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:69: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(cnt1k >= `MASTER_CLK_CYC_PER_MS) begin         \n                                         ^\n%Error: data/full_repos/permissive/429196919/FPGA/pulse/pulse.v:78: syntax error, unexpected else\n  else begin\n  ^~~~\n%Error: Cannot continue\n'
module pulse (input wire[7:0] pulseLength,
			  input trigger,
			  input masterClk,
			  output reg pulse,
			  output reg pulseInv);
 
	reg [$clog2(`MASTER_CLK_CYC_PER_MS)-1:0] cnt1k = 0;
	reg [7:0] pulseCnt = 0;
	reg active = 0;




	reg prevTrigger = 0;
	always @ (posedge masterClk) begin
		prevTrigger <= trigger;
	end
	`define PULSE_TRIGGER_POSEDGE (trigger && !prevTrigger)
	`define PULSE_TRIGGER_NEGEDGE (!trigger && prevTrigger)





	always @ (posedge masterClk) begin
		if(`PULSE_TRIGGER_POSEDGE && !active && pulseLength!=8'h00) begin
			pulse <= 1'b1;
			pulseInv <= 1'b0;
			cnt1k <= 0;
			pulseCnt <= pulseLength;
			active <= 1'b1;
		end
		else if(cnt1k >= `MASTER_CLK_CYC_PER_MS) begin
			cnt1k <= 0;
			pulseCnt <= pulseCnt - 1'b1;
			if (pulseCnt <= 8'h01) begin
				pulse <= 1'b0;
				pulseInv <= 1'b1;
				active <= 1'b0;
			end
		end
		else begin
			cnt1k <= cnt1k + 1'b1;
		end
	end

endmodule
module pulse (input wire[7:0] pulseLength,
			  input trigger,
			  input masterClk,
			  output reg pulse,
			  output reg pulseInv);

 
	reg [$clog2(`MASTER_CLK_CYC_PER_MS)-1:0] cnt1k = 0;
	reg [7:0] pulseCnt = 0;
	reg active = 0;




	reg prevTrigger = 0;
	always @ (posedge masterClk) begin
		prevTrigger <= trigger;
	end
	`define PULSE_TRIGGER_POSEDGE (trigger && !prevTrigger)
	`define PULSE_TRIGGER_NEGEDGE (!trigger && prevTrigger)





	always @ (posedge masterClk) begin
		if(`PULSE_TRIGGER_POSEDGE && !active && pulseLength!=8'h00) begin
			pulse <= 1'b1;
			pulseInv <= 1'b0;
			cnt1k <= 0;
			pulseCnt <= pulseLength;
			active <= 1'b1;
		end
		else if(cnt1k >= `MASTER_CLK_CYC_PER_MS) begin
			cnt1k <= 0;
			pulseCnt <= pulseCnt - 1'b1;
			if (pulseCnt <= 8'h01) begin
				pulse <= 1'b0;
				pulseInv <= 1'b1;
				active <= 1'b0;
			end
		end
		else begin
			cnt1k <= cnt1k + 1'b1;
		end
	end

endmodule