data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n   forever #50 t1 = ~t1;    \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #95;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #300;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #300;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-INFINITELOOP: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/LIGHT_test.v:12: Infinite loop (condition always true)\n                                                                                                          : ... In instance LIGHT_test\n   forever #50 t1 = ~t1;    \n   ^~~~~~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LIGHT_test(t1, t2, t3, t4, p1, p2, p3, p4);

input  p1,  p2,  p3, p4;


output   t1, t2,  t3, t4;   

reg t1, t2, t3, t4;


initial begin
   forever #50 t1 = ~t1;
end


initial begin
   t1 <= 1'b1;
   t2 <= 1'b1;

   t3 <= 1'b1;
   t4 <= 1'b0;

   #20;
   t2 <= 1'b0;

   #100;
   t2 <= 1'b1;

   #95;
   t4 <= 1'b1;
   
   #100;
   t3 <= 1'b0;

   #300;
   t3 <= 1'b1;
   t4 <= 1'b0;
   
   #300;
   t3 <= 1'b0;

   #100;
   $finish;
end

endmodule
module LIGHT_test(t1, t2, t3, t4, p1, p2, p3, p4);


input  p1,  p2,  p3, p4;


output   t1, t2,  t3, t4;   

reg t1, t2, t3, t4;


initial begin
   forever #50 t1 = ~t1;
end


initial begin
   t1 <= 1'b1;
   t2 <= 1'b1;

   t3 <= 1'b1;
   t4 <= 1'b0;

   #20;
   t2 <= 1'b0;

   #100;
   t2 <= 1'b1;

   #95;
   t4 <= 1'b1;
   
   #100;
   t3 <= 1'b0;

   #300;
   t3 <= 1'b1;
   t4 <= 1'b0;
   
   #300;
   t3 <= 1'b0;

   #100;
   $finish;
end

endmodule