data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v:20: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v:29: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v:31: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v:35: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_wait_timer.v:38: syntax error, unexpected \'@\'\n    repeat(50 * 1000 * 11) @(posedge clk);\n                           ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_wait_timer();

  reg         clk;
  reg         rsth;
  reg         mod_sel;
  reg         req;
  reg [7:0]   w_wdata;
  wire        ack;


  timer_wait uut (
    .clk(clk),
    .rsth(rsth),
    .mod_sel(mod_sel),
    .req(req),
    .w_wdata(w_wdata),
    .ack(ack)
  );

  always #10 clk = ~clk;

  initial begin
    clk = 0;
    rsth = 1;
    mod_sel = 0;
    req = 0;
    w_wdata = 0;

    repeat(10) @(posedge clk);
    rsth = 0;
    repeat(10) @(posedge clk);


    w_wdata = 10;
    @(posedge clk);
    mod_sel <= 1;
    req <= 1;
    repeat(50 * 1000 * 11) @(posedge clk);

    $finish;
  end

endmodule
module sim_wait_timer();


  reg         clk;
  reg         rsth;
  reg         mod_sel;
  reg         req;
  reg [7:0]   w_wdata;
  wire        ack;


  timer_wait uut (
    .clk(clk),
    .rsth(rsth),
    .mod_sel(mod_sel),
    .req(req),
    .w_wdata(w_wdata),
    .ack(ack)
  );

  always #10 clk = ~clk;

  initial begin
    clk = 0;
    rsth = 1;
    mod_sel = 0;
    req = 0;
    w_wdata = 0;

    repeat(10) @(posedge clk);
    rsth = 0;
    repeat(10) @(posedge clk);


    w_wdata = 10;
    @(posedge clk);
    mod_sel <= 1;
    req <= 1;
    repeat(50 * 1000 * 11) @(posedge clk);

    $finish;
  end

endmodule