data/full_repos/permissive/449071180/tb_move_to_position.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_to_position.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449071180/tb_move_to_position.v:8: Cannot find file containing module: \'move_to_position\'\nmove_to_position port_map(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_to_position\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_to_position.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_to_position.sv\n             move_to_position\n             move_to_position.v\n             move_to_position.sv\n             obj_dir/move_to_position\n             obj_dir/move_to_position.v\n             obj_dir/move_to_position.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_move_to_position.v:21: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'integer_test\' generates 32 bits.\n                                                                             : ... In instance tb_move_to_position\n  bcd_test = integer_test;\n           ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_move_to_position();

reg [2:0] bcd_test;
wire l_test,r_test,u_test,d_test;

integer integer_test;

move_to_position port_map(

.bcd(bcd_test),
.l(l_test),
.r(r_test),
.u(u_test),
.d(d_test)

);

always begin 

	for(integer_test = 0; integer_test < 8; integer_test = integer_test + 1) begin
		bcd_test = integer_test;
		#5;
	end

end

endmodule
module tb_move_to_position();


reg [2:0] bcd_test;
wire l_test,r_test,u_test,d_test;

integer integer_test;

move_to_position port_map(

.bcd(bcd_test),
.l(l_test),
.r(r_test),
.u(u_test),
.d(d_test)

);

always begin 

	for(integer_test = 0; integer_test < 8; integer_test = integer_test + 1) begin
		bcd_test = integer_test;
		#5;
	end

end

endmodule