data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_pl.v
1: b'%Error: data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_pl.v:64: Cannot find include file: usb1d_defines.v\n`include "usb1d_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v.v\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v.sv\n             usb1d_defines.v\n             usb1d_defines.v.v\n             usb1d_defines.v.sv\n             obj_dir/usb1d_defines.v\n             obj_dir/usb1d_defines.v.v\n             obj_dir/usb1d_defines.v.sv\n%Error: data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_pl.v:270: Define or directive not defined: \'`USBF_HMS_DEL\'\n hms_clk <= #1 (hms_cnt == `USBF_HMS_DEL);\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_pl.v:270: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n hms_clk <= #1 (hms_cnt == `USBF_HMS_DEL);\n                                        ^\n%Error: Exiting due to 3 error(s)\n'
module usb1d_pl(	clk, rst,


		rx_data, rx_valid, rx_active, rx_err,
		tx_data, tx_valid, tx_valid_last, tx_ready,
		tx_first, tx_valid_out,

		token_valid,


		fa,
		ep_sel, 
		x_busy,
		int_crc16_set, int_to_set, int_seqerr_set,


		frm_nat,
		pid_cs_err, nse_err,
		crc5_err,
		rx_size, rx_done,
		ctrl_setup, ctrl_in, ctrl_out,


		ep_bf_en, ep_bf_size,
		dropped_frame, misaligned_frame,


		csr,
		tx_data_st, 
		rx_ctrl_data, 
		rx_ctrl_data_d, 
		rx_ctrl_dvalid,
		rx_ctrl_ddone,
		idma_re, idma_we,
		ep_empty, ep_full, send_stall

		);


input		clk, rst;
input	[7:0]	rx_data;
input		rx_valid, rx_active, rx_err;
output	[7:0]	tx_data;
output		tx_valid;
output		tx_valid_last;
input		tx_ready;
output		tx_first;
input		tx_valid_out;

output		token_valid;


input	[6:0]	fa;
output	[3:0]	ep_sel;
output		x_busy;

output		int_crc16_set;
output		int_to_set;
output		int_seqerr_set;


output		pid_cs_err;
output		crc5_err;
output	[31:0]	frm_nat;
output		nse_err;
output	[7:0]	rx_size;
output		rx_done;
output		ctrl_setup;
output		ctrl_in;
output		ctrl_out;
input		ep_bf_en;
input	[6:0]	ep_bf_size;
output		dropped_frame, misaligned_frame;


input	[13:0]	csr;	
input	[7:0]	tx_data_st;
output	[7:0]	rx_ctrl_data;
output	[7:0]	rx_ctrl_data_d;
output		rx_ctrl_dvalid;
output		rx_ctrl_ddone;
output		idma_re, idma_we;
input		ep_empty;
input		ep_full;

input		send_stall;







wire		clk, rst;
wire	[7:0]	rx_data;
wire		pid_OUT, pid_IN, pid_SOF, pid_SETUP;
wire		pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
wire		pid_ACK, pid_NACK, pid_STALL, pid_NYET;
wire		pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
wire	[6:0]	token_fadr;
wire		token_valid;
wire		crc5_err;
wire	[10:0]	frame_no;
wire	[7:0]	rx_ctrl_data;
reg	[7:0]	rx_ctrl_data_d;
wire		rx_ctrl_dvalid;
wire		rx_ctrl_ddone;
wire		crc16_err;
wire		rx_seq_err;


wire		send_token;
wire	[1:0]	token_pid_sel;
wire		send_data;
wire	[1:0]	data_pid_sel;
wire	[7:0]	tx_data_st;
wire	[7:0]	tx_data_st_o;
wire		rd_next;


wire		rx_dma_en;
wire		tx_dma_en;
wire		abort;
wire		idma_done;


wire		idma_we;
wire		idma_re;


wire		pid_bad;

reg		hms_clk;
reg	[4:0]	hms_cnt;
reg	[10:0]	frame_no_r;
wire		frame_no_we;
reg	[11:0]	sof_time;
reg		clr_sof_time;
wire		fsel;
wire		match_o;

reg		frame_no_we_r;
reg		ctrl_setup;
reg		ctrl_in;
reg		ctrl_out;

wire		idma_we_d;
wire		ep_empty_int;
wire		rx_busy;
wire		tx_busy;






assign x_busy = tx_busy | rx_busy;


assign pid_bad = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
			pid_ERR | pid_SPLIT |  pid_PING;

assign match_o = !pid_bad & token_valid & !crc5_err;


always @(posedge clk)
	ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);

always @(posedge clk)
	ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);

always @(posedge clk)
	ctrl_out <= #1 token_valid & pid_OUT & (ep_sel==4'h0);


assign frame_no_we = token_valid & !crc5_err & pid_SOF;

always @(posedge clk)
	frame_no_we_r <= #1 frame_no_we;

always @(posedge clk or negedge rst)
	if(!rst)		frame_no_r <= #1 11'h0;
	else
	if(frame_no_we_r)	frame_no_r <= #1 frame_no;


always @(posedge clk)
	clr_sof_time <= #1 frame_no_we;

always @(posedge clk)
	if(clr_sof_time)	sof_time <= #1 12'h0;
	else
	if(hms_clk)		sof_time <= #1 sof_time + 12'h1;

assign frm_nat = {4'h0, 1'b0, frame_no_r, 4'h0, sof_time};


always @(posedge clk or negedge rst)
	if(!rst)				hms_cnt <= #1 5'h0;
	else
	if(hms_clk | frame_no_we_r)		hms_cnt <= #1 5'h0;
	else					hms_cnt <= #1 hms_cnt + 5'h1;

always @(posedge clk)
	hms_clk <= #1 (hms_cnt == `USBF_HMS_DEL);

always @(posedge clk)
	rx_ctrl_data_d <= rx_ctrl_data;




assign fsel = (token_fadr == fa);


assign idma_we = idma_we_d & fsel;







usb1d_pd	u0(	.clk(		clk		),
		.rst(		rst		),

		.rx_data(	rx_data		),
		.rx_valid(	rx_valid	),
		.rx_active(	rx_active	),
		.rx_err(	rx_err		),
		.pid_OUT(	pid_OUT		),
		.pid_IN(	pid_IN		),
		.pid_SOF(	pid_SOF		),
		.pid_SETUP(	pid_SETUP	),
		.pid_DATA0(	pid_DATA0	),
		.pid_DATA1(	pid_DATA1	),
		.pid_DATA2(	pid_DATA2	),
		.pid_MDATA(	pid_MDATA	),
		.pid_ACK(	pid_ACK		),
		.pid_NACK(	pid_NACK	),
		.pid_STALL(	pid_STALL	),
		.pid_NYET(	pid_NYET	),
		.pid_PRE(	pid_PRE		),
		.pid_ERR(	pid_ERR		),
		.pid_SPLIT(	pid_SPLIT	),
		.pid_PING(	pid_PING	),
		.pid_cks_err(	pid_cs_err	),
		.token_fadr(	token_fadr	),
		.token_endp(	ep_sel		),
		.token_valid(	token_valid	),
		.crc5_err(	crc5_err	),
		.frame_no(	frame_no	),
		.rx_data_st(	rx_ctrl_data	),
		.rx_data_valid(	rx_ctrl_dvalid	),
		.rx_data_done(	rx_ctrl_ddone	),
		.crc16_err(	crc16_err	),
		.seq_err(	rx_seq_err	),
		.rx_busy(	rx_busy		)
		);


usb1d_pa	u1(	.clk(		clk		),
		.rst(		rst		),
		.tx_data(	tx_data		),
		.tx_valid(	tx_valid	),
		.tx_valid_last(	tx_valid_last	),
		.tx_ready(	tx_ready	),
		.tx_first(	tx_first	),
		.send_token(	send_token	),
		.token_pid_sel(	token_pid_sel	),
		.send_data(	send_data	),
		.data_pid_sel(	data_pid_sel	),
		.tx_data_st(	tx_data_st_o	),
		.rd_next(	rd_next		),
		.ep_empty(	ep_empty_int)
		);


usb1d_idma
	u2(	.clk(		clk		),
		.rst(		rst		),

		.tx_valid(	tx_valid	),
		.rx_data_valid(	rx_ctrl_dvalid	),
		.rx_data_done(	rx_ctrl_ddone	),
		.send_data(	send_data	),
		.rd_next(	rd_next		),

		.tx_data_st_i(	tx_data_st	),
		.tx_data_st_o(	tx_data_st_o	),
		.ep_sel(	ep_sel		),

		.ep_bf_en(	ep_bf_en	),
		.ep_bf_size(	ep_bf_size	),
		.dropped_frame(dropped_frame	),
		.misaligned_frame(misaligned_frame),

		.tx_busy(	tx_busy		),

		.tx_dma_en(	tx_dma_en	),
		.rx_dma_en(	rx_dma_en	),
		.idma_done(	idma_done	),
		.size(		csr[8:0]	),
		.rx_cnt(	rx_size		),
		.rx_done(	rx_done		),
		.mwe(		idma_we_d	),
		.mre(		idma_re		),
		.ep_empty(	ep_empty	),
		.ep_empty_int(	ep_empty_int	),
		.ep_full(	ep_full		)
		);


usb1d_pe
	u3(	.clk(			clk			),
		.rst(			rst			),

		.tx_valid(		tx_valid_out		),
		.rx_active(		rx_active		),
		.pid_OUT(		pid_OUT			),
		.pid_IN(		pid_IN			),
		.pid_SOF(		pid_SOF			),
		.pid_SETUP(		pid_SETUP		),
		.pid_DATA0(		pid_DATA0		),
		.pid_DATA1(		pid_DATA1		),
		.pid_DATA2(		pid_DATA2		),
		.pid_MDATA(		pid_MDATA		),
		.pid_ACK(		pid_ACK			),
		.pid_PING(		pid_PING		),
		.token_valid(		token_valid		),
		.rx_data_done(		rx_ctrl_ddone		),
		.crc16_err(		crc16_err		),
		.send_token(		send_token		),
		.token_pid_sel(		token_pid_sel		),
		.data_pid_sel(		data_pid_sel		),
		.rx_dma_en(		rx_dma_en		),
		.tx_dma_en(		tx_dma_en		),
		.abort(			abort			),
		.idma_done(		idma_done		),
		.fsel(			fsel			),
		.ep_sel(		ep_sel			),
		.ep_full(		ep_full			),
		.ep_empty(		ep_empty		),
		.match(			match_o			),
		.nse_err(		nse_err			),
		.int_upid_set(		         		),
		.int_crc16_set(		int_crc16_set		),
		.int_to_set(		int_to_set		),
		.int_seqerr_set(	int_seqerr_set		),
		.csr(			csr			),
		.send_stall(		send_stall		)
		);

endmodule
module usb1d_pl(	clk, rst,


		rx_data, rx_valid, rx_active, rx_err,
		tx_data, tx_valid, tx_valid_last, tx_ready,
		tx_first, tx_valid_out,

		token_valid,


		fa,
		ep_sel, 
		x_busy,
		int_crc16_set, int_to_set, int_seqerr_set,


		frm_nat,
		pid_cs_err, nse_err,
		crc5_err,
		rx_size, rx_done,
		ctrl_setup, ctrl_in, ctrl_out,


		ep_bf_en, ep_bf_size,
		dropped_frame, misaligned_frame,


		csr,
		tx_data_st, 
		rx_ctrl_data, 
		rx_ctrl_data_d, 
		rx_ctrl_dvalid,
		rx_ctrl_ddone,
		idma_re, idma_we,
		ep_empty, ep_full, send_stall

		);



input		clk, rst;
input	[7:0]	rx_data;
input		rx_valid, rx_active, rx_err;
output	[7:0]	tx_data;
output		tx_valid;
output		tx_valid_last;
input		tx_ready;
output		tx_first;
input		tx_valid_out;

output		token_valid;


input	[6:0]	fa;
output	[3:0]	ep_sel;
output		x_busy;

output		int_crc16_set;
output		int_to_set;
output		int_seqerr_set;


output		pid_cs_err;
output		crc5_err;
output	[31:0]	frm_nat;
output		nse_err;
output	[7:0]	rx_size;
output		rx_done;
output		ctrl_setup;
output		ctrl_in;
output		ctrl_out;
input		ep_bf_en;
input	[6:0]	ep_bf_size;
output		dropped_frame, misaligned_frame;


input	[13:0]	csr;	
input	[7:0]	tx_data_st;
output	[7:0]	rx_ctrl_data;
output	[7:0]	rx_ctrl_data_d;
output		rx_ctrl_dvalid;
output		rx_ctrl_ddone;
output		idma_re, idma_we;
input		ep_empty;
input		ep_full;

input		send_stall;







wire		clk, rst;
wire	[7:0]	rx_data;
wire		pid_OUT, pid_IN, pid_SOF, pid_SETUP;
wire		pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
wire		pid_ACK, pid_NACK, pid_STALL, pid_NYET;
wire		pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
wire	[6:0]	token_fadr;
wire		token_valid;
wire		crc5_err;
wire	[10:0]	frame_no;
wire	[7:0]	rx_ctrl_data;
reg	[7:0]	rx_ctrl_data_d;
wire		rx_ctrl_dvalid;
wire		rx_ctrl_ddone;
wire		crc16_err;
wire		rx_seq_err;


wire		send_token;
wire	[1:0]	token_pid_sel;
wire		send_data;
wire	[1:0]	data_pid_sel;
wire	[7:0]	tx_data_st;
wire	[7:0]	tx_data_st_o;
wire		rd_next;


wire		rx_dma_en;
wire		tx_dma_en;
wire		abort;
wire		idma_done;


wire		idma_we;
wire		idma_re;


wire		pid_bad;

reg		hms_clk;
reg	[4:0]	hms_cnt;
reg	[10:0]	frame_no_r;
wire		frame_no_we;
reg	[11:0]	sof_time;
reg		clr_sof_time;
wire		fsel;
wire		match_o;

reg		frame_no_we_r;
reg		ctrl_setup;
reg		ctrl_in;
reg		ctrl_out;

wire		idma_we_d;
wire		ep_empty_int;
wire		rx_busy;
wire		tx_busy;






assign x_busy = tx_busy | rx_busy;


assign pid_bad = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
			pid_ERR | pid_SPLIT |  pid_PING;

assign match_o = !pid_bad & token_valid & !crc5_err;


always @(posedge clk)
	ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);

always @(posedge clk)
	ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);

always @(posedge clk)
	ctrl_out <= #1 token_valid & pid_OUT & (ep_sel==4'h0);


assign frame_no_we = token_valid & !crc5_err & pid_SOF;

always @(posedge clk)
	frame_no_we_r <= #1 frame_no_we;

always @(posedge clk or negedge rst)
	if(!rst)		frame_no_r <= #1 11'h0;
	else
	if(frame_no_we_r)	frame_no_r <= #1 frame_no;


always @(posedge clk)
	clr_sof_time <= #1 frame_no_we;

always @(posedge clk)
	if(clr_sof_time)	sof_time <= #1 12'h0;
	else
	if(hms_clk)		sof_time <= #1 sof_time + 12'h1;

assign frm_nat = {4'h0, 1'b0, frame_no_r, 4'h0, sof_time};


always @(posedge clk or negedge rst)
	if(!rst)				hms_cnt <= #1 5'h0;
	else
	if(hms_clk | frame_no_we_r)		hms_cnt <= #1 5'h0;
	else					hms_cnt <= #1 hms_cnt + 5'h1;

always @(posedge clk)
	hms_clk <= #1 (hms_cnt == `USBF_HMS_DEL);

always @(posedge clk)
	rx_ctrl_data_d <= rx_ctrl_data;




assign fsel = (token_fadr == fa);


assign idma_we = idma_we_d & fsel;







usb1d_pd	u0(	.clk(		clk		),
		.rst(		rst		),

		.rx_data(	rx_data		),
		.rx_valid(	rx_valid	),
		.rx_active(	rx_active	),
		.rx_err(	rx_err		),
		.pid_OUT(	pid_OUT		),
		.pid_IN(	pid_IN		),
		.pid_SOF(	pid_SOF		),
		.pid_SETUP(	pid_SETUP	),
		.pid_DATA0(	pid_DATA0	),
		.pid_DATA1(	pid_DATA1	),
		.pid_DATA2(	pid_DATA2	),
		.pid_MDATA(	pid_MDATA	),
		.pid_ACK(	pid_ACK		),
		.pid_NACK(	pid_NACK	),
		.pid_STALL(	pid_STALL	),
		.pid_NYET(	pid_NYET	),
		.pid_PRE(	pid_PRE		),
		.pid_ERR(	pid_ERR		),
		.pid_SPLIT(	pid_SPLIT	),
		.pid_PING(	pid_PING	),
		.pid_cks_err(	pid_cs_err	),
		.token_fadr(	token_fadr	),
		.token_endp(	ep_sel		),
		.token_valid(	token_valid	),
		.crc5_err(	crc5_err	),
		.frame_no(	frame_no	),
		.rx_data_st(	rx_ctrl_data	),
		.rx_data_valid(	rx_ctrl_dvalid	),
		.rx_data_done(	rx_ctrl_ddone	),
		.crc16_err(	crc16_err	),
		.seq_err(	rx_seq_err	),
		.rx_busy(	rx_busy		)
		);


usb1d_pa	u1(	.clk(		clk		),
		.rst(		rst		),
		.tx_data(	tx_data		),
		.tx_valid(	tx_valid	),
		.tx_valid_last(	tx_valid_last	),
		.tx_ready(	tx_ready	),
		.tx_first(	tx_first	),
		.send_token(	send_token	),
		.token_pid_sel(	token_pid_sel	),
		.send_data(	send_data	),
		.data_pid_sel(	data_pid_sel	),
		.tx_data_st(	tx_data_st_o	),
		.rd_next(	rd_next		),
		.ep_empty(	ep_empty_int)
		);


usb1d_idma
	u2(	.clk(		clk		),
		.rst(		rst		),

		.tx_valid(	tx_valid	),
		.rx_data_valid(	rx_ctrl_dvalid	),
		.rx_data_done(	rx_ctrl_ddone	),
		.send_data(	send_data	),
		.rd_next(	rd_next		),

		.tx_data_st_i(	tx_data_st	),
		.tx_data_st_o(	tx_data_st_o	),
		.ep_sel(	ep_sel		),

		.ep_bf_en(	ep_bf_en	),
		.ep_bf_size(	ep_bf_size	),
		.dropped_frame(dropped_frame	),
		.misaligned_frame(misaligned_frame),

		.tx_busy(	tx_busy		),

		.tx_dma_en(	tx_dma_en	),
		.rx_dma_en(	rx_dma_en	),
		.idma_done(	idma_done	),
		.size(		csr[8:0]	),
		.rx_cnt(	rx_size		),
		.rx_done(	rx_done		),
		.mwe(		idma_we_d	),
		.mre(		idma_re		),
		.ep_empty(	ep_empty	),
		.ep_empty_int(	ep_empty_int	),
		.ep_full(	ep_full		)
		);


usb1d_pe
	u3(	.clk(			clk			),
		.rst(			rst			),

		.tx_valid(		tx_valid_out		),
		.rx_active(		rx_active		),
		.pid_OUT(		pid_OUT			),
		.pid_IN(		pid_IN			),
		.pid_SOF(		pid_SOF			),
		.pid_SETUP(		pid_SETUP		),
		.pid_DATA0(		pid_DATA0		),
		.pid_DATA1(		pid_DATA1		),
		.pid_DATA2(		pid_DATA2		),
		.pid_MDATA(		pid_MDATA		),
		.pid_ACK(		pid_ACK			),
		.pid_PING(		pid_PING		),
		.token_valid(		token_valid		),
		.rx_data_done(		rx_ctrl_ddone		),
		.crc16_err(		crc16_err		),
		.send_token(		send_token		),
		.token_pid_sel(		token_pid_sel		),
		.data_pid_sel(		data_pid_sel		),
		.rx_dma_en(		rx_dma_en		),
		.tx_dma_en(		tx_dma_en		),
		.abort(			abort			),
		.idma_done(		idma_done		),
		.fsel(			fsel			),
		.ep_sel(		ep_sel			),
		.ep_full(		ep_full			),
		.ep_empty(		ep_empty		),
		.match(			match_o			),
		.nse_err(		nse_err			),
		.int_upid_set(		         		),
		.int_crc16_set(		int_crc16_set		),
		.int_to_set(		int_to_set		),
		.int_seqerr_set(	int_seqerr_set		),
		.csr(			csr			),
		.send_stall(		send_stall		)
		);

endmodule