data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_READ_ig.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_READ_ig.v:9: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module NV_NVDLA_MCIF_READ_ig (
   bdma2mcif_rd_cdt_lat_fifo_pop
  ,bdma2mcif_rd_req_pd
  ,bdma2mcif_rd_req_valid
  ,cdma_dat2mcif_rd_req_pd
  ,cdma_dat2mcif_rd_req_valid
  ,cdma_wt2mcif_rd_req_pd
  ,cdma_wt2mcif_rd_req_valid
  ,cdp2mcif_rd_cdt_lat_fifo_pop
  ,cdp2mcif_rd_req_pd
  ,cdp2mcif_rd_req_valid
  ,cq_wr_prdy
  ,eg2ig_axi_vld
  ,mcif2noc_axi_ar_arready
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2mcif_rd_cdt_lat_fifo_pop
  ,pdp2mcif_rd_req_pd
  ,pdp2mcif_rd_req_valid
  ,rbk2mcif_rd_cdt_lat_fifo_pop
  ,rbk2mcif_rd_req_pd
  ,rbk2mcif_rd_req_valid
  ,reg2dp_rd_os_cnt
  ,reg2dp_rd_weight_bdma
  ,reg2dp_rd_weight_cdma_dat
  ,reg2dp_rd_weight_cdma_wt
  ,reg2dp_rd_weight_cdp
  ,reg2dp_rd_weight_pdp
  ,reg2dp_rd_weight_rbk
  ,reg2dp_rd_weight_sdp
  ,reg2dp_rd_weight_sdp_b
  ,reg2dp_rd_weight_sdp_e
  ,reg2dp_rd_weight_sdp_n
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp_b2mcif_rd_cdt_lat_fifo_pop
  ,sdp_b2mcif_rd_req_pd
  ,sdp_b2mcif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_n2mcif_rd_cdt_lat_fifo_pop
  ,sdp_n2mcif_rd_req_pd
  ,sdp_n2mcif_rd_req_valid
  ,bdma2mcif_rd_req_ready
  ,cdma_dat2mcif_rd_req_ready
  ,cdma_wt2mcif_rd_req_ready
  ,cdp2mcif_rd_req_ready
  ,cq_wr_pd
  ,cq_wr_pvld
  ,cq_wr_thread_id
  ,mcif2noc_axi_ar_araddr
  ,mcif2noc_axi_ar_arid
  ,mcif2noc_axi_ar_arlen
  ,mcif2noc_axi_ar_arvalid
  ,pdp2mcif_rd_req_ready
  ,rbk2mcif_rd_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp_b2mcif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_n2mcif_rd_req_ready
  );











input nvdla_core_clk;
input nvdla_core_rstn;
input bdma2mcif_rd_cdt_lat_fifo_pop;
input bdma2mcif_rd_req_valid;
output bdma2mcif_rd_req_ready;
input [78:0] bdma2mcif_rd_req_pd;
input cdma_dat2mcif_rd_req_valid;
output cdma_dat2mcif_rd_req_ready;
input [78:0] cdma_dat2mcif_rd_req_pd;
input cdma_wt2mcif_rd_req_valid;
output cdma_wt2mcif_rd_req_ready;
input [78:0] cdma_wt2mcif_rd_req_pd;
input cdp2mcif_rd_cdt_lat_fifo_pop;
input cdp2mcif_rd_req_valid;
output cdp2mcif_rd_req_ready;
input [78:0] cdp2mcif_rd_req_pd;
output cq_wr_pvld;
input cq_wr_prdy;
output [3:0] cq_wr_thread_id;
output [6:0] cq_wr_pd;
output mcif2noc_axi_ar_arvalid;
input mcif2noc_axi_ar_arready;
output [7:0] mcif2noc_axi_ar_arid;
output [3:0] mcif2noc_axi_ar_arlen;
output [63:0] mcif2noc_axi_ar_araddr;
input pdp2mcif_rd_cdt_lat_fifo_pop;
input pdp2mcif_rd_req_valid;
output pdp2mcif_rd_req_ready;
input [78:0] pdp2mcif_rd_req_pd;
input rbk2mcif_rd_cdt_lat_fifo_pop;
input rbk2mcif_rd_req_valid;
output rbk2mcif_rd_req_ready;
input [78:0] rbk2mcif_rd_req_pd;
input sdp2mcif_rd_cdt_lat_fifo_pop;
input sdp2mcif_rd_req_valid;
output sdp2mcif_rd_req_ready;
input [78:0] sdp2mcif_rd_req_pd;
input sdp_b2mcif_rd_cdt_lat_fifo_pop;
input sdp_b2mcif_rd_req_valid;
output sdp_b2mcif_rd_req_ready;
input [78:0] sdp_b2mcif_rd_req_pd;
input sdp_e2mcif_rd_cdt_lat_fifo_pop;
input sdp_e2mcif_rd_req_valid;
output sdp_e2mcif_rd_req_ready;
input [78:0] sdp_e2mcif_rd_req_pd;
input sdp_n2mcif_rd_cdt_lat_fifo_pop;
input sdp_n2mcif_rd_req_valid;
output sdp_n2mcif_rd_req_ready;
input [78:0] sdp_n2mcif_rd_req_pd;
input eg2ig_axi_vld;
input [7:0] reg2dp_rd_os_cnt;
input [7:0] reg2dp_rd_weight_bdma;
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_rbk;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_sdp_n;
wire [74:0] arb2spt_req_pd;
wire arb2spt_req_ready;
wire arb2spt_req_valid;
wire [74:0] bpt2arb_req0_pd;
wire bpt2arb_req0_ready;
wire bpt2arb_req0_valid;
wire [74:0] bpt2arb_req1_pd;
wire bpt2arb_req1_ready;
wire bpt2arb_req1_valid;
wire [74:0] bpt2arb_req2_pd;
wire bpt2arb_req2_ready;
wire bpt2arb_req2_valid;
wire [74:0] bpt2arb_req3_pd;
wire bpt2arb_req3_ready;
wire bpt2arb_req3_valid;
wire [74:0] bpt2arb_req4_pd;
wire bpt2arb_req4_ready;
wire bpt2arb_req4_valid;
wire [74:0] bpt2arb_req5_pd;
wire bpt2arb_req5_ready;
wire bpt2arb_req5_valid;
wire [74:0] bpt2arb_req6_pd;
wire bpt2arb_req6_ready;
wire bpt2arb_req6_valid;
wire [74:0] bpt2arb_req7_pd;
wire bpt2arb_req7_ready;
wire bpt2arb_req7_valid;
wire [74:0] bpt2arb_req8_pd;
wire bpt2arb_req8_ready;
wire bpt2arb_req8_valid;
wire [74:0] bpt2arb_req9_pd;
wire bpt2arb_req9_ready;
wire bpt2arb_req9_valid;
wire [74:0] spt2cvt_req_pd;
wire spt2cvt_req_ready;
wire spt2cvt_req_valid;
NV_NVDLA_MCIF_READ_IG_bpt u_bpt0 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (bdma2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (bdma2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (bdma2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req0_valid)
  ,.bpt2arb_req_ready (bpt2arb_req0_ready)
  ,.bpt2arb_req_pd (bpt2arb_req0_pd[74:0])
  ,.tieoff_axid (4'd0)
  ,.tieoff_lat_fifo_depth (8'd245)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt1 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req1_valid)
  ,.bpt2arb_req_ready (bpt2arb_req1_ready)
  ,.bpt2arb_req_pd (bpt2arb_req1_pd[74:0])
  ,.tieoff_axid (4'd1)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt2 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (pdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (pdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (pdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req2_valid)
  ,.bpt2arb_req_ready (bpt2arb_req2_ready)
  ,.bpt2arb_req_pd (bpt2arb_req2_pd[74:0])
  ,.tieoff_axid (4'd2)
  ,.tieoff_lat_fifo_depth (8'd61)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt3 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req3_valid)
  ,.bpt2arb_req_ready (bpt2arb_req3_ready)
  ,.bpt2arb_req_pd (bpt2arb_req3_pd[74:0])
  ,.tieoff_axid (4'd3)
  ,.tieoff_lat_fifo_depth (8'd61)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt4 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (rbk2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (rbk2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (rbk2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (rbk2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req4_valid)
  ,.bpt2arb_req_ready (bpt2arb_req4_ready)
  ,.bpt2arb_req_pd (bpt2arb_req4_pd[74:0])
  ,.tieoff_axid (4'd4)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt5 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_b2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_b2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_b2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req5_valid)
  ,.bpt2arb_req_ready (bpt2arb_req5_ready)
  ,.bpt2arb_req_pd (bpt2arb_req5_pd[74:0])
  ,.tieoff_axid (4'd5)
  ,.tieoff_lat_fifo_depth (8'd160)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt6 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_n2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_n2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_n2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req6_valid)
  ,.bpt2arb_req_ready (bpt2arb_req6_ready)
  ,.bpt2arb_req_pd (bpt2arb_req6_pd[74:0])
  ,.tieoff_axid (4'd6)
  ,.tieoff_lat_fifo_depth (8'd160)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt7 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_e2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_e2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_e2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req7_valid)
  ,.bpt2arb_req_ready (bpt2arb_req7_ready)
  ,.bpt2arb_req_pd (bpt2arb_req7_pd[74:0])
  ,.tieoff_axid (4'd7)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt8 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdma_dat2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdma_dat2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdma_dat2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop ({1{1'b0}})
  ,.bpt2arb_req_valid (bpt2arb_req8_valid)
  ,.bpt2arb_req_ready (bpt2arb_req8_ready)
  ,.bpt2arb_req_pd (bpt2arb_req8_pd[74:0])
  ,.tieoff_axid (4'd8)
  ,.tieoff_lat_fifo_depth (8'd0)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt9 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdma_wt2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdma_wt2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdma_wt2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop ({1{1'b0}})
  ,.bpt2arb_req_valid (bpt2arb_req9_valid)
  ,.bpt2arb_req_ready (bpt2arb_req9_ready)
  ,.bpt2arb_req_pd (bpt2arb_req9_pd[74:0])
  ,.tieoff_axid (4'd9)
  ,.tieoff_lat_fifo_depth (8'd0)
  );
NV_NVDLA_MCIF_READ_IG_arb u_arb (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bpt2arb_req0_valid (bpt2arb_req0_valid)
  ,.bpt2arb_req0_ready (bpt2arb_req0_ready)
  ,.bpt2arb_req0_pd (bpt2arb_req0_pd[74:0])
  ,.bpt2arb_req1_valid (bpt2arb_req1_valid)
  ,.bpt2arb_req1_ready (bpt2arb_req1_ready)
  ,.bpt2arb_req1_pd (bpt2arb_req1_pd[74:0])
  ,.bpt2arb_req2_valid (bpt2arb_req2_valid)
  ,.bpt2arb_req2_ready (bpt2arb_req2_ready)
  ,.bpt2arb_req2_pd (bpt2arb_req2_pd[74:0])
  ,.bpt2arb_req3_valid (bpt2arb_req3_valid)
  ,.bpt2arb_req3_ready (bpt2arb_req3_ready)
  ,.bpt2arb_req3_pd (bpt2arb_req3_pd[74:0])
  ,.bpt2arb_req4_valid (bpt2arb_req4_valid)
  ,.bpt2arb_req4_ready (bpt2arb_req4_ready)
  ,.bpt2arb_req4_pd (bpt2arb_req4_pd[74:0])
  ,.bpt2arb_req5_valid (bpt2arb_req5_valid)
  ,.bpt2arb_req5_ready (bpt2arb_req5_ready)
  ,.bpt2arb_req5_pd (bpt2arb_req5_pd[74:0])
  ,.bpt2arb_req6_valid (bpt2arb_req6_valid)
  ,.bpt2arb_req6_ready (bpt2arb_req6_ready)
  ,.bpt2arb_req6_pd (bpt2arb_req6_pd[74:0])
  ,.bpt2arb_req7_valid (bpt2arb_req7_valid)
  ,.bpt2arb_req7_ready (bpt2arb_req7_ready)
  ,.bpt2arb_req7_pd (bpt2arb_req7_pd[74:0])
  ,.bpt2arb_req8_valid (bpt2arb_req8_valid)
  ,.bpt2arb_req8_ready (bpt2arb_req8_ready)
  ,.bpt2arb_req8_pd (bpt2arb_req8_pd[74:0])
  ,.bpt2arb_req9_valid (bpt2arb_req9_valid)
  ,.bpt2arb_req9_ready (bpt2arb_req9_ready)
  ,.bpt2arb_req9_pd (bpt2arb_req9_pd[74:0])
  ,.arb2spt_req_valid (arb2spt_req_valid)
  ,.arb2spt_req_ready (arb2spt_req_ready)
  ,.arb2spt_req_pd (arb2spt_req_pd[74:0])
  ,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma[7:0])
  ,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0])
  ,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0])
  ,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp[7:0])
  ,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp[7:0])
  ,.reg2dp_rd_weight_rbk (reg2dp_rd_weight_rbk[7:0])
  ,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp[7:0])
  ,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0])
  ,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0])
  ,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0])
  );
NV_NVDLA_MCIF_READ_IG_spt u_spt (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.arb2spt_req_valid (arb2spt_req_valid)
  ,.arb2spt_req_ready (arb2spt_req_ready)
  ,.arb2spt_req_pd (arb2spt_req_pd[74:0])
  ,.spt2cvt_req_valid (spt2cvt_req_valid)
  ,.spt2cvt_req_ready (spt2cvt_req_ready)
  ,.spt2cvt_req_pd (spt2cvt_req_pd[74:0])
  );
NV_NVDLA_MCIF_READ_IG_cvt u_cvt (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.spt2cvt_req_valid (spt2cvt_req_valid)
  ,.spt2cvt_req_ready (spt2cvt_req_ready)
  ,.spt2cvt_req_pd (spt2cvt_req_pd[74:0])
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_thread_id (cq_wr_thread_id[3:0])
  ,.cq_wr_pd (cq_wr_pd[6:0])
  ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid)
  ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready)
  ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0])
  ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0])
  ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[63:0])
  ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
endmodule
module NV_NVDLA_MCIF_READ_ig (
   bdma2mcif_rd_cdt_lat_fifo_pop
  ,bdma2mcif_rd_req_pd
  ,bdma2mcif_rd_req_valid
  ,cdma_dat2mcif_rd_req_pd
  ,cdma_dat2mcif_rd_req_valid
  ,cdma_wt2mcif_rd_req_pd
  ,cdma_wt2mcif_rd_req_valid
  ,cdp2mcif_rd_cdt_lat_fifo_pop
  ,cdp2mcif_rd_req_pd
  ,cdp2mcif_rd_req_valid
  ,cq_wr_prdy
  ,eg2ig_axi_vld
  ,mcif2noc_axi_ar_arready
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2mcif_rd_cdt_lat_fifo_pop
  ,pdp2mcif_rd_req_pd
  ,pdp2mcif_rd_req_valid
  ,rbk2mcif_rd_cdt_lat_fifo_pop
  ,rbk2mcif_rd_req_pd
  ,rbk2mcif_rd_req_valid
  ,reg2dp_rd_os_cnt
  ,reg2dp_rd_weight_bdma
  ,reg2dp_rd_weight_cdma_dat
  ,reg2dp_rd_weight_cdma_wt
  ,reg2dp_rd_weight_cdp
  ,reg2dp_rd_weight_pdp
  ,reg2dp_rd_weight_rbk
  ,reg2dp_rd_weight_sdp
  ,reg2dp_rd_weight_sdp_b
  ,reg2dp_rd_weight_sdp_e
  ,reg2dp_rd_weight_sdp_n
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp_b2mcif_rd_cdt_lat_fifo_pop
  ,sdp_b2mcif_rd_req_pd
  ,sdp_b2mcif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_n2mcif_rd_cdt_lat_fifo_pop
  ,sdp_n2mcif_rd_req_pd
  ,sdp_n2mcif_rd_req_valid
  ,bdma2mcif_rd_req_ready
  ,cdma_dat2mcif_rd_req_ready
  ,cdma_wt2mcif_rd_req_ready
  ,cdp2mcif_rd_req_ready
  ,cq_wr_pd
  ,cq_wr_pvld
  ,cq_wr_thread_id
  ,mcif2noc_axi_ar_araddr
  ,mcif2noc_axi_ar_arid
  ,mcif2noc_axi_ar_arlen
  ,mcif2noc_axi_ar_arvalid
  ,pdp2mcif_rd_req_ready
  ,rbk2mcif_rd_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp_b2mcif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_n2mcif_rd_req_ready
  );












input nvdla_core_clk;
input nvdla_core_rstn;
input bdma2mcif_rd_cdt_lat_fifo_pop;
input bdma2mcif_rd_req_valid;
output bdma2mcif_rd_req_ready;
input [78:0] bdma2mcif_rd_req_pd;
input cdma_dat2mcif_rd_req_valid;
output cdma_dat2mcif_rd_req_ready;
input [78:0] cdma_dat2mcif_rd_req_pd;
input cdma_wt2mcif_rd_req_valid;
output cdma_wt2mcif_rd_req_ready;
input [78:0] cdma_wt2mcif_rd_req_pd;
input cdp2mcif_rd_cdt_lat_fifo_pop;
input cdp2mcif_rd_req_valid;
output cdp2mcif_rd_req_ready;
input [78:0] cdp2mcif_rd_req_pd;
output cq_wr_pvld;
input cq_wr_prdy;
output [3:0] cq_wr_thread_id;
output [6:0] cq_wr_pd;
output mcif2noc_axi_ar_arvalid;
input mcif2noc_axi_ar_arready;
output [7:0] mcif2noc_axi_ar_arid;
output [3:0] mcif2noc_axi_ar_arlen;
output [63:0] mcif2noc_axi_ar_araddr;
input pdp2mcif_rd_cdt_lat_fifo_pop;
input pdp2mcif_rd_req_valid;
output pdp2mcif_rd_req_ready;
input [78:0] pdp2mcif_rd_req_pd;
input rbk2mcif_rd_cdt_lat_fifo_pop;
input rbk2mcif_rd_req_valid;
output rbk2mcif_rd_req_ready;
input [78:0] rbk2mcif_rd_req_pd;
input sdp2mcif_rd_cdt_lat_fifo_pop;
input sdp2mcif_rd_req_valid;
output sdp2mcif_rd_req_ready;
input [78:0] sdp2mcif_rd_req_pd;
input sdp_b2mcif_rd_cdt_lat_fifo_pop;
input sdp_b2mcif_rd_req_valid;
output sdp_b2mcif_rd_req_ready;
input [78:0] sdp_b2mcif_rd_req_pd;
input sdp_e2mcif_rd_cdt_lat_fifo_pop;
input sdp_e2mcif_rd_req_valid;
output sdp_e2mcif_rd_req_ready;
input [78:0] sdp_e2mcif_rd_req_pd;
input sdp_n2mcif_rd_cdt_lat_fifo_pop;
input sdp_n2mcif_rd_req_valid;
output sdp_n2mcif_rd_req_ready;
input [78:0] sdp_n2mcif_rd_req_pd;
input eg2ig_axi_vld;
input [7:0] reg2dp_rd_os_cnt;
input [7:0] reg2dp_rd_weight_bdma;
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_rbk;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_sdp_n;
wire [74:0] arb2spt_req_pd;
wire arb2spt_req_ready;
wire arb2spt_req_valid;
wire [74:0] bpt2arb_req0_pd;
wire bpt2arb_req0_ready;
wire bpt2arb_req0_valid;
wire [74:0] bpt2arb_req1_pd;
wire bpt2arb_req1_ready;
wire bpt2arb_req1_valid;
wire [74:0] bpt2arb_req2_pd;
wire bpt2arb_req2_ready;
wire bpt2arb_req2_valid;
wire [74:0] bpt2arb_req3_pd;
wire bpt2arb_req3_ready;
wire bpt2arb_req3_valid;
wire [74:0] bpt2arb_req4_pd;
wire bpt2arb_req4_ready;
wire bpt2arb_req4_valid;
wire [74:0] bpt2arb_req5_pd;
wire bpt2arb_req5_ready;
wire bpt2arb_req5_valid;
wire [74:0] bpt2arb_req6_pd;
wire bpt2arb_req6_ready;
wire bpt2arb_req6_valid;
wire [74:0] bpt2arb_req7_pd;
wire bpt2arb_req7_ready;
wire bpt2arb_req7_valid;
wire [74:0] bpt2arb_req8_pd;
wire bpt2arb_req8_ready;
wire bpt2arb_req8_valid;
wire [74:0] bpt2arb_req9_pd;
wire bpt2arb_req9_ready;
wire bpt2arb_req9_valid;
wire [74:0] spt2cvt_req_pd;
wire spt2cvt_req_ready;
wire spt2cvt_req_valid;
NV_NVDLA_MCIF_READ_IG_bpt u_bpt0 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (bdma2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (bdma2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (bdma2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req0_valid)
  ,.bpt2arb_req_ready (bpt2arb_req0_ready)
  ,.bpt2arb_req_pd (bpt2arb_req0_pd[74:0])
  ,.tieoff_axid (4'd0)
  ,.tieoff_lat_fifo_depth (8'd245)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt1 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req1_valid)
  ,.bpt2arb_req_ready (bpt2arb_req1_ready)
  ,.bpt2arb_req_pd (bpt2arb_req1_pd[74:0])
  ,.tieoff_axid (4'd1)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt2 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (pdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (pdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (pdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req2_valid)
  ,.bpt2arb_req_ready (bpt2arb_req2_ready)
  ,.bpt2arb_req_pd (bpt2arb_req2_pd[74:0])
  ,.tieoff_axid (4'd2)
  ,.tieoff_lat_fifo_depth (8'd61)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt3 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdp2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdp2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdp2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req3_valid)
  ,.bpt2arb_req_ready (bpt2arb_req3_ready)
  ,.bpt2arb_req_pd (bpt2arb_req3_pd[74:0])
  ,.tieoff_axid (4'd3)
  ,.tieoff_lat_fifo_depth (8'd61)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt4 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (rbk2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (rbk2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (rbk2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (rbk2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req4_valid)
  ,.bpt2arb_req_ready (bpt2arb_req4_ready)
  ,.bpt2arb_req_pd (bpt2arb_req4_pd[74:0])
  ,.tieoff_axid (4'd4)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt5 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_b2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_b2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_b2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req5_valid)
  ,.bpt2arb_req_ready (bpt2arb_req5_ready)
  ,.bpt2arb_req_pd (bpt2arb_req5_pd[74:0])
  ,.tieoff_axid (4'd5)
  ,.tieoff_lat_fifo_depth (8'd160)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt6 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_n2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_n2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_n2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req6_valid)
  ,.bpt2arb_req_ready (bpt2arb_req6_ready)
  ,.bpt2arb_req_pd (bpt2arb_req6_pd[74:0])
  ,.tieoff_axid (4'd6)
  ,.tieoff_lat_fifo_depth (8'd160)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt7 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (sdp_e2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (sdp_e2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (sdp_e2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.bpt2arb_req_valid (bpt2arb_req7_valid)
  ,.bpt2arb_req_ready (bpt2arb_req7_ready)
  ,.bpt2arb_req_pd (bpt2arb_req7_pd[74:0])
  ,.tieoff_axid (4'd7)
  ,.tieoff_lat_fifo_depth (8'd80)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt8 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdma_dat2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdma_dat2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdma_dat2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop ({1{1'b0}})
  ,.bpt2arb_req_valid (bpt2arb_req8_valid)
  ,.bpt2arb_req_ready (bpt2arb_req8_ready)
  ,.bpt2arb_req_pd (bpt2arb_req8_pd[74:0])
  ,.tieoff_axid (4'd8)
  ,.tieoff_lat_fifo_depth (8'd0)
  );
NV_NVDLA_MCIF_READ_IG_bpt u_bpt9 (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dma2bpt_req_valid (cdma_wt2mcif_rd_req_valid)
  ,.dma2bpt_req_ready (cdma_wt2mcif_rd_req_ready)
  ,.dma2bpt_req_pd (cdma_wt2mcif_rd_req_pd[78:0])
  ,.dma2bpt_cdt_lat_fifo_pop ({1{1'b0}})
  ,.bpt2arb_req_valid (bpt2arb_req9_valid)
  ,.bpt2arb_req_ready (bpt2arb_req9_ready)
  ,.bpt2arb_req_pd (bpt2arb_req9_pd[74:0])
  ,.tieoff_axid (4'd9)
  ,.tieoff_lat_fifo_depth (8'd0)
  );
NV_NVDLA_MCIF_READ_IG_arb u_arb (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bpt2arb_req0_valid (bpt2arb_req0_valid)
  ,.bpt2arb_req0_ready (bpt2arb_req0_ready)
  ,.bpt2arb_req0_pd (bpt2arb_req0_pd[74:0])
  ,.bpt2arb_req1_valid (bpt2arb_req1_valid)
  ,.bpt2arb_req1_ready (bpt2arb_req1_ready)
  ,.bpt2arb_req1_pd (bpt2arb_req1_pd[74:0])
  ,.bpt2arb_req2_valid (bpt2arb_req2_valid)
  ,.bpt2arb_req2_ready (bpt2arb_req2_ready)
  ,.bpt2arb_req2_pd (bpt2arb_req2_pd[74:0])
  ,.bpt2arb_req3_valid (bpt2arb_req3_valid)
  ,.bpt2arb_req3_ready (bpt2arb_req3_ready)
  ,.bpt2arb_req3_pd (bpt2arb_req3_pd[74:0])
  ,.bpt2arb_req4_valid (bpt2arb_req4_valid)
  ,.bpt2arb_req4_ready (bpt2arb_req4_ready)
  ,.bpt2arb_req4_pd (bpt2arb_req4_pd[74:0])
  ,.bpt2arb_req5_valid (bpt2arb_req5_valid)
  ,.bpt2arb_req5_ready (bpt2arb_req5_ready)
  ,.bpt2arb_req5_pd (bpt2arb_req5_pd[74:0])
  ,.bpt2arb_req6_valid (bpt2arb_req6_valid)
  ,.bpt2arb_req6_ready (bpt2arb_req6_ready)
  ,.bpt2arb_req6_pd (bpt2arb_req6_pd[74:0])
  ,.bpt2arb_req7_valid (bpt2arb_req7_valid)
  ,.bpt2arb_req7_ready (bpt2arb_req7_ready)
  ,.bpt2arb_req7_pd (bpt2arb_req7_pd[74:0])
  ,.bpt2arb_req8_valid (bpt2arb_req8_valid)
  ,.bpt2arb_req8_ready (bpt2arb_req8_ready)
  ,.bpt2arb_req8_pd (bpt2arb_req8_pd[74:0])
  ,.bpt2arb_req9_valid (bpt2arb_req9_valid)
  ,.bpt2arb_req9_ready (bpt2arb_req9_ready)
  ,.bpt2arb_req9_pd (bpt2arb_req9_pd[74:0])
  ,.arb2spt_req_valid (arb2spt_req_valid)
  ,.arb2spt_req_ready (arb2spt_req_ready)
  ,.arb2spt_req_pd (arb2spt_req_pd[74:0])
  ,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma[7:0])
  ,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0])
  ,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0])
  ,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp[7:0])
  ,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp[7:0])
  ,.reg2dp_rd_weight_rbk (reg2dp_rd_weight_rbk[7:0])
  ,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp[7:0])
  ,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0])
  ,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0])
  ,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0])
  );
NV_NVDLA_MCIF_READ_IG_spt u_spt (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.arb2spt_req_valid (arb2spt_req_valid)
  ,.arb2spt_req_ready (arb2spt_req_ready)
  ,.arb2spt_req_pd (arb2spt_req_pd[74:0])
  ,.spt2cvt_req_valid (spt2cvt_req_valid)
  ,.spt2cvt_req_ready (spt2cvt_req_ready)
  ,.spt2cvt_req_pd (spt2cvt_req_pd[74:0])
  );
NV_NVDLA_MCIF_READ_IG_cvt u_cvt (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.spt2cvt_req_valid (spt2cvt_req_valid)
  ,.spt2cvt_req_ready (spt2cvt_req_ready)
  ,.spt2cvt_req_pd (spt2cvt_req_pd[74:0])
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_thread_id (cq_wr_thread_id[3:0])
  ,.cq_wr_pd (cq_wr_pd[6:0])
  ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid)
  ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready)
  ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0])
  ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0])
  ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[63:0])
  ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
endmodule