data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:516: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                         : ... In instance lab7_2self.u7.M4\n  cnt  =4\'d0;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:27: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer1\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b100 )? timer1 :\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:29: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer3\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b010 )? timer3 :4\'b0;\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module 	row_gen(clk, reset, row, cnt);
input 	clk, reset;

output	[7:0]row;
output	[6:0]cnt;
reg		[7:0]row;

reg		[6:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset) begin
		row		=8'b1000_0000;
		cnt		=4'd0;

		end
	else 
		if(cnt==7'd80)
			cnt=7'd0;
		else begin
			row		={row[0],row[7:1]} ;
			cnt		=cnt+7'd1;

			end
end
endmodule
module 	row_gen(clk, reset, row, cnt);

input 	clk, reset;

output	[7:0]row;
output	[6:0]cnt;
reg		[7:0]row;

reg		[6:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset) begin
		row		=8'b1000_0000;
		cnt		=4'd0;

		end
	else 
		if(cnt==7'd80)
			cnt=7'd0;
		else begin
			row		={row[0],row[7:1]} ;
			cnt		=cnt+7'd1;

			end
end
endmodule