data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 stim = stim + 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();

  wire out_and;
  wire out_or;
  wire out_xor;

  reg [3:0] stim = 3'd0;

  localparam ITERATIONS = 16;

  always begin
    #1 stim = stim + 1;
  end

  top_module uut (
      .in(stim),
      .out_and(out_and),
      .out_or(out_or),
      .out_xor(out_xor)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  wire out_and;
  wire out_or;
  wire out_xor;

  reg [3:0] stim = 3'd0;

  localparam ITERATIONS = 16;

  always begin
    #1 stim = stim + 1;
  end

  top_module uut (
      .in(stim),
      .out_and(out_and),
      .out_or(out_or),
      .out_xor(out_xor)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule