data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK = ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #5 CE = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #5 RST = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #200 $stop;\n    ^\n%Error: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:19: Cannot find file containing module: \'up_cnt_mod\'\nup_cnt_mod #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/up_cnt_mod\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/up_cnt_mod.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/up_cnt_mod.sv\n             up_cnt_mod\n             up_cnt_mod.v\n             up_cnt_mod.sv\n             obj_dir/up_cnt_mod\n             obj_dir/up_cnt_mod.v\n             obj_dir/up_cnt_mod.sv\n%Error: data/full_repos/permissive/501791642/sim/up_cnt_mod_tb.v:32: Cannot find file containing module: \'up_cnt_mod\'\nup_cnt_mod #(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module up_cnt_mod_tb;

reg CLK, CE, RST;
wire CO0, CO1;
wire [3:0] Q0;
wire [3:0] Q1;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
end

always #1 CLK = ~CLK;

up_cnt_mod #(
    .MODULO(10),
    .W(4)
)
dekada0
(
    .CLK(CLK),
    .CE(CE),
    .CLR(RST),
    .Q(Q0),
    .CO(CO0)
);

up_cnt_mod #(
    .MODULO(10),
    .W(4)
)
dekada1
(
    .CLK(CLK),
    .CE(CO0),
    .CLR(RST),
    .Q(Q1),
    .CO(CO1)
);

initial begin
    #5 CE = 1;
    #5 RST = 0;
    #200 $stop;
end




endmodule
module up_cnt_mod_tb;


reg CLK, CE, RST;
wire CO0, CO1;
wire [3:0] Q0;
wire [3:0] Q1;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
end

always #1 CLK = ~CLK;

up_cnt_mod #(
    .MODULO(10),
    .W(4)
)
dekada0
(
    .CLK(CLK),
    .CE(CE),
    .CLR(RST),
    .Q(Q0),
    .CO(CO0)
);

up_cnt_mod #(
    .MODULO(10),
    .W(4)
)
dekada1
(
    .CLK(CLK),
    .CE(CO0),
    .CLR(RST),
    .Q(Q1),
    .CO(CO1)
);

initial begin
    #5 CE = 1;
    #5 RST = 0;
    #200 $stop;
end




endmodule