data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:86: Little bit endian vector: MSB < LSB of bit range: 0:168\noutput [0:LENGTHBUS-1] RBUS_Om_SetEn,\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:87: Little bit endian vector: MSB < LSB of bit range: 0:168\noutput [0:LENGTHBUS-1] RBUS_Om_OEn,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:88: Little bit endian vector: MSB < LSB of bit range: 0:168\noutput [0:LENGTHBUS-1] RBUS_Om_Wptclr,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:89: Little bit endian vector: MSB < LSB of bit range: 0:168\noutput [0:LENGTHBUS-1] RBUS_Om_Rptclr,\n       ^\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:162: Cannot find file containing module: \'SIMPLE_COUNTER\'\nSIMPLE_COUNTER  #(.BITWIDTH(8)) Counter_Bus(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER.sv\n             SIMPLE_COUNTER\n             SIMPLE_COUNTER.v\n             SIMPLE_COUNTER.sv\n             obj_dir/SIMPLE_COUNTER\n             obj_dir/SIMPLE_COUNTER.v\n             obj_dir/SIMPLE_COUNTER.sv\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:176: Cannot find file containing module: \'SIMPLE_COUNTER\'\nSIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_W_SIZE)) Counter_W_Size(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:191: Cannot find file containing module: \'COUNTER_POS\'\nCOUNTER_POS #(.BITWIDTH(BITWIDTH_W_COLUMS)) Counter_W_Col(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:206: Cannot find file containing module: \'COUNTER_POS\'\nCOUNTER_POS #(.BITWIDTH(4)) Counter_Input(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RBUS.v:222: Cannot find file containing module: \'RBUS_STATEMACHINE\'\nRBUS_STATEMACHINE Rbus_Statemachine\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module RBUS #( parameter LENGTHBUS=169,BITWIDTH_W_COLUMS=4, BITWIDTH_MAX_W_SIZE=9)(


input RBUS_Clk,
input RBUS_Reset,
input RBUS_Set_Conf,
input RBUS_Set_Conf_Already_Ok,
input [BITWIDTH_W_COLUMS-1:0] RBUS_W_Colums,
input [BITWIDTH_MAX_W_SIZE-1:0] RBUS_W_ROXCL,

input RBUS_SetEn0,
input RBUS_SetEn1,
input RBUS_SetEn2,
input RBUS_SetEn3,
input RBUS_SetEn4,
input RBUS_SetEn5,
input RBUS_SetEn6,
input RBUS_SetEn7,
input RBUS_SetEn8,
input RBUS_SetEn9,
input RBUS_SetEn10,
input RBUS_SetEn11,
input RBUS_SetEn12,
input RBUS_OEn0,
input RBUS_OEn1,
input RBUS_OEn2,
input RBUS_OEn3,
input RBUS_OEn4,
input RBUS_OEn5,
input RBUS_OEn6,
input RBUS_OEn7,
input RBUS_OEn8,
input RBUS_OEn9,
input RBUS_OEn10,
input RBUS_OEn11,
input RBUS_OEn12,
input RBUS_Wptclr0,
input RBUS_Wptclr1,
input RBUS_Wptclr2,
input RBUS_Wptclr3,
input RBUS_Wptclr4,
input RBUS_Wptclr5,
input RBUS_Wptclr6,
input RBUS_Wptclr7,
input RBUS_Wptclr8,
input RBUS_Wptclr9,
input RBUS_Wptclr10,
input RBUS_Wptclr11,
input RBUS_Wptclr12,
input RBUS_Rptclr0,
input RBUS_Rptclr1,
input RBUS_Rptclr2,
input RBUS_Rptclr3,
input RBUS_Rptclr4,
input RBUS_Rptclr5,
input RBUS_Rptclr6,
input RBUS_Rptclr7,
input RBUS_Rptclr8,
input RBUS_Rptclr9,
input RBUS_Rptclr10,
input RBUS_Rptclr11,
input RBUS_Rptclr12,


output [0:LENGTHBUS-1] RBUS_Om_SetEn,
output [0:LENGTHBUS-1] RBUS_Om_OEn,
output [0:LENGTHBUS-1] RBUS_Om_Wptclr,
output [0:LENGTHBUS-1] RBUS_Om_Rptclr,
output RBUS_Set_Conf_Already
);





localparam [BITWIDTH_W_COLUMS-1:0] data1_4= 4'd1;
localparam [7:0] Counter_Bus_Number = LENGTHBUS[7:0] -8'b1;
localparam [3:0] maxInput=4'd13;






wire Counter_W_Size_Eqn_Flag;
wire [BITWIDTH_MAX_W_SIZE-1:0] Counter_W_Size_Out;
wire Counter_Input_Eqn_Flag;
wire [3:0] Counter_Input_Out;

wire [BITWIDTH_W_COLUMS-1:0] Counter_W_Col_Out;
wire Counter_W_Col_Eqn_Flag;
wire Counter_W_Col_Load;

wire Rbus_Statemachine_Counter_W_Size_En;
wire Rbus_Statemachine_Counter_W_Size_Clr;
wire Rbus_Statemachine_Counter_W_Col_En;
wire Rbus_Statemachine_Counter_W_Col_Load;
wire Rbus_Statemachine_Counter_W_Col_Clr;
wire Rbus_Statemachine_Counter_Input_Clr;
wire Rbus_Statemachine_Counter_Input_Load;
wire Rbus_Statemachine_Bus_En;
wire Rbus_Statemachine_Conf_Rutine;
wire Rbus_Statemachine_Counter_Bus_En;
wire Rbus_Statemachine_Counter_Bus_Clr;
wire [7:0] Counter_Bus_Out;
wire Counter_Bus_Eqn_Flag;

reg Counter_W_Col_Load_1;
reg [3:0] Select[0:LENGTHBUS-1];






always@(negedge RBUS_Clk)
begin

 if(Rbus_Statemachine_Conf_Rutine)
	begin
		
		if(Counter_W_Col_Eqn_Flag) begin
			Select[Counter_Bus_Out]<=Counter_Input_Out;
			Counter_W_Col_Load_1<=1'b1;	
		end
	
		else
		begin
			Select[Counter_Bus_Out]<=4'b0;
			Counter_W_Col_Load_1<=1'b0;
		end
		
	end
end






SIMPLE_COUNTER  #(.BITWIDTH(8)) Counter_Bus(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_Bus_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_Bus_En),
.COUNTER_Number(Counter_Bus_Number),


.COUNTER_Out(Counter_Bus_Out),
.COUNTER_Eqn_Flag(Counter_Bus_Eqn_Flag)

);


SIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_W_SIZE)) Counter_W_Size(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_W_Size_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_W_Size_En),
.COUNTER_Number(RBUS_W_ROXCL),


.COUNTER_Out(Counter_W_Size_Out),
.COUNTER_Eqn_Flag(Counter_W_Size_Eqn_Flag)

);



COUNTER_POS #(.BITWIDTH(BITWIDTH_W_COLUMS)) Counter_W_Col(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_W_Col_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_W_Col_En),
.COUNTER_load(Counter_W_Col_Load),
.COUNTER_Data(data1_4),
.COUNTER_Number(RBUS_W_Colums),


.COUNTER_Out(Counter_W_Col_Out),
.COUNTER_Eqn_Flag(Counter_W_Col_Eqn_Flag)
);


COUNTER_POS #(.BITWIDTH(4)) Counter_Input(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_Input_Clr),
.COUNTER_En(Counter_W_Col_Eqn_Flag),
.COUNTER_load(Rbus_Statemachine_Counter_Input_Load),
.COUNTER_Data(data1_4),
.COUNTER_Number(maxInput),


.COUNTER_Out(Counter_Input_Out),
.COUNTER_Eqn_Flag(Counter_Input_Eqn_Flag)

);


RBUS_STATEMACHINE Rbus_Statemachine
(

.RBUS_STATEMACHINE_Clk(RBUS_Clk),
.RBUS_STATEMACHINE_Reset(RBUS_Reset),
.RBUS_STATEMACHINE_Start_Conf(RBUS_Set_Conf),
.RBUS_STATEMACHINE_Conf_Already_Ok(RBUS_Set_Conf_Already_Ok),
.RBUS_STATEMACHINE_Counter_Bus_Flag(Counter_Bus_Eqn_Flag),
.RBUS_STATEMACHINE_Counter_W_Size_Flag(Counter_W_Size_Eqn_Flag),

.RBUS_STATEMACHINE_Set_Conf_Already(RBUS_Set_Conf_Already),
.RBUS_STATEMACHINE_Counter_W_Size_En(Rbus_Statemachine_Counter_W_Size_En),
.RBUS_STATEMACHINE_Counter_W_Size_Clr(Rbus_Statemachine_Counter_W_Size_Clr),
.RBUS_STATEMACHINE_Counter_W_Col_En(Rbus_Statemachine_Counter_W_Col_En),
.RBUS_STATEMACHINE_Counter_W_Col_Load(Rbus_Statemachine_Counter_W_Col_Load),
.RBUS_STATEMACHINE_Counter_W_Col_Clr(Rbus_Statemachine_Counter_W_Col_Clr),
.RBUS_STATEMACHINE_Counter_Input_Clr(Rbus_Statemachine_Counter_Input_Clr),
.RBUS_STATEMACHINE_Counter_Input_Load(Rbus_Statemachine_Counter_Input_Load),
.RBUS_STATEMACHINE_Counter_Bus_En(Rbus_Statemachine_Counter_Bus_En),
.RBUS_STATEMACHINE_Counter_Bus_Clr(Rbus_Statemachine_Counter_Bus_Clr),
.RBUS_STATEMACHINE_Conf_Rutine(Rbus_Statemachine_Conf_Rutine),
.RBUS_STATEMACHINE_Bus_En(Rbus_Statemachine_Bus_En)
);







genvar i;
generate

	for (i = 0; i < LENGTHBUS ; i=i+1)   
	begin:bus
	
		assign RBUS_Om_SetEn[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
										 (Select[i] == 4'd1) ? RBUS_SetEn0 :
								       (Select[i] == 4'd2) ? RBUS_SetEn1 :
								       (Select[i] == 4'd3) ? RBUS_SetEn2 :
								       (Select[i] == 4'd4) ? RBUS_SetEn3 :
								       (Select[i] == 4'd5) ? RBUS_SetEn4 :
								       (Select[i] == 4'd6) ? RBUS_SetEn5 :
								       (Select[i] == 4'd7) ? RBUS_SetEn6 :
								       (Select[i] == 4'd8) ? RBUS_SetEn7 :
								       (Select[i] == 4'd9) ? RBUS_SetEn8 :
								       (Select[i] == 4'd10) ? RBUS_SetEn9 :
								       (Select[i] == 4'd11) ? RBUS_SetEn10 :
								       (Select[i] == 4'd12) ? RBUS_SetEn11 :
								       (Select[i] == 4'd13) ? RBUS_SetEn12 : 1'b0 :1'b0;
							
		assign RBUS_Om_OEn[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
									  (Select[i] == 4'd1) ? RBUS_OEn0 :
									  (Select[i] == 4'd2) ? RBUS_OEn1 :
								     (Select[i] == 4'd3) ? RBUS_OEn2 :
								     (Select[i] == 4'd4) ? RBUS_OEn3 :
								     (Select[i] == 4'd5) ? RBUS_OEn4 :
								     (Select[i] == 4'd6) ? RBUS_OEn5 :
								     (Select[i] == 4'd7) ? RBUS_OEn6 :
								     (Select[i] == 4'd8) ? RBUS_OEn7 :
								     (Select[i] == 4'd9) ? RBUS_OEn8 :
								     (Select[i] == 4'd10) ? RBUS_OEn9 :
								     (Select[i] == 4'd11) ? RBUS_OEn10 :
								     (Select[i] == 4'd12) ? RBUS_OEn11 :
								     (Select[i] == 4'd13) ? RBUS_OEn12 : 1'b0 :1'b0;
								 
      assign RBUS_Om_Wptclr[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
								        (Select[i] == 4'd1) ? RBUS_Wptclr0 :
								        (Select[i] == 4'd2) ? RBUS_Wptclr1 :
								        (Select[i] == 4'd3) ? RBUS_Wptclr2 :
								        (Select[i] == 4'd4) ? RBUS_Wptclr3 :
								        (Select[i] == 4'd5) ? RBUS_Wptclr4 :
								        (Select[i] == 4'd6) ? RBUS_Wptclr5 :
								        (Select[i] == 4'd7) ? RBUS_Wptclr6 :
								        (Select[i] == 4'd8) ? RBUS_Wptclr7 :
								        (Select[i] == 4'd9) ? RBUS_Wptclr8 :
								        (Select[i] == 4'd10) ? RBUS_Wptclr9 :
								        (Select[i] == 4'd11) ? RBUS_Wptclr10 :
								        (Select[i] == 4'd12) ? RBUS_Wptclr11 :
								        (Select[i] == 4'd13) ? RBUS_Wptclr12 : 1'b0 :1'b0;
								 
								 
		assign RBUS_Om_Rptclr[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
								        (Select[i] == 4'd1) ? RBUS_Rptclr0 :
								        (Select[i] == 4'd2) ? RBUS_Rptclr1 :
								        (Select[i] == 4'd3) ? RBUS_Rptclr2 :
								        (Select[i] == 4'd4) ? RBUS_Rptclr3 :
							           (Select[i] == 4'd5) ? RBUS_Rptclr4 :
								        (Select[i] == 4'd6) ? RBUS_Rptclr5 :
								        (Select[i] == 4'd7) ? RBUS_Rptclr6 :
								        (Select[i] == 4'd8) ? RBUS_Rptclr7 :
								        (Select[i] == 4'd9) ? RBUS_Rptclr8 :
								        (Select[i] == 4'd10) ? RBUS_Rptclr9 :
								        (Select[i] == 4'd11) ? RBUS_Rptclr10 :
								        (Select[i] == 4'd12) ? RBUS_Rptclr11 :
								        (Select[i] == 4'd13) ? RBUS_Rptclr12 : 1'b0 :1'b0;				 
	end
	
endgenerate 


assign Counter_W_Col_Load =(Counter_W_Col_Load_1 | Rbus_Statemachine_Counter_W_Col_Load);


endmodule
module RBUS #( parameter LENGTHBUS=169,BITWIDTH_W_COLUMS=4, BITWIDTH_MAX_W_SIZE=9)(


input RBUS_Clk,
input RBUS_Reset,
input RBUS_Set_Conf,
input RBUS_Set_Conf_Already_Ok,
input [BITWIDTH_W_COLUMS-1:0] RBUS_W_Colums,
input [BITWIDTH_MAX_W_SIZE-1:0] RBUS_W_ROXCL,

input RBUS_SetEn0,
input RBUS_SetEn1,
input RBUS_SetEn2,
input RBUS_SetEn3,
input RBUS_SetEn4,
input RBUS_SetEn5,
input RBUS_SetEn6,
input RBUS_SetEn7,
input RBUS_SetEn8,
input RBUS_SetEn9,
input RBUS_SetEn10,
input RBUS_SetEn11,
input RBUS_SetEn12,
input RBUS_OEn0,
input RBUS_OEn1,
input RBUS_OEn2,
input RBUS_OEn3,
input RBUS_OEn4,
input RBUS_OEn5,
input RBUS_OEn6,
input RBUS_OEn7,
input RBUS_OEn8,
input RBUS_OEn9,
input RBUS_OEn10,
input RBUS_OEn11,
input RBUS_OEn12,
input RBUS_Wptclr0,
input RBUS_Wptclr1,
input RBUS_Wptclr2,
input RBUS_Wptclr3,
input RBUS_Wptclr4,
input RBUS_Wptclr5,
input RBUS_Wptclr6,
input RBUS_Wptclr7,
input RBUS_Wptclr8,
input RBUS_Wptclr9,
input RBUS_Wptclr10,
input RBUS_Wptclr11,
input RBUS_Wptclr12,
input RBUS_Rptclr0,
input RBUS_Rptclr1,
input RBUS_Rptclr2,
input RBUS_Rptclr3,
input RBUS_Rptclr4,
input RBUS_Rptclr5,
input RBUS_Rptclr6,
input RBUS_Rptclr7,
input RBUS_Rptclr8,
input RBUS_Rptclr9,
input RBUS_Rptclr10,
input RBUS_Rptclr11,
input RBUS_Rptclr12,


output [0:LENGTHBUS-1] RBUS_Om_SetEn,
output [0:LENGTHBUS-1] RBUS_Om_OEn,
output [0:LENGTHBUS-1] RBUS_Om_Wptclr,
output [0:LENGTHBUS-1] RBUS_Om_Rptclr,
output RBUS_Set_Conf_Already
);






localparam [BITWIDTH_W_COLUMS-1:0] data1_4= 4'd1;
localparam [7:0] Counter_Bus_Number = LENGTHBUS[7:0] -8'b1;
localparam [3:0] maxInput=4'd13;






wire Counter_W_Size_Eqn_Flag;
wire [BITWIDTH_MAX_W_SIZE-1:0] Counter_W_Size_Out;
wire Counter_Input_Eqn_Flag;
wire [3:0] Counter_Input_Out;

wire [BITWIDTH_W_COLUMS-1:0] Counter_W_Col_Out;
wire Counter_W_Col_Eqn_Flag;
wire Counter_W_Col_Load;

wire Rbus_Statemachine_Counter_W_Size_En;
wire Rbus_Statemachine_Counter_W_Size_Clr;
wire Rbus_Statemachine_Counter_W_Col_En;
wire Rbus_Statemachine_Counter_W_Col_Load;
wire Rbus_Statemachine_Counter_W_Col_Clr;
wire Rbus_Statemachine_Counter_Input_Clr;
wire Rbus_Statemachine_Counter_Input_Load;
wire Rbus_Statemachine_Bus_En;
wire Rbus_Statemachine_Conf_Rutine;
wire Rbus_Statemachine_Counter_Bus_En;
wire Rbus_Statemachine_Counter_Bus_Clr;
wire [7:0] Counter_Bus_Out;
wire Counter_Bus_Eqn_Flag;

reg Counter_W_Col_Load_1;
reg [3:0] Select[0:LENGTHBUS-1];






always@(negedge RBUS_Clk)
begin

 if(Rbus_Statemachine_Conf_Rutine)
	begin
		
		if(Counter_W_Col_Eqn_Flag) begin
			Select[Counter_Bus_Out]<=Counter_Input_Out;
			Counter_W_Col_Load_1<=1'b1;	
		end
	
		else
		begin
			Select[Counter_Bus_Out]<=4'b0;
			Counter_W_Col_Load_1<=1'b0;
		end
		
	end
end






SIMPLE_COUNTER  #(.BITWIDTH(8)) Counter_Bus(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_Bus_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_Bus_En),
.COUNTER_Number(Counter_Bus_Number),


.COUNTER_Out(Counter_Bus_Out),
.COUNTER_Eqn_Flag(Counter_Bus_Eqn_Flag)

);


SIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_W_SIZE)) Counter_W_Size(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_W_Size_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_W_Size_En),
.COUNTER_Number(RBUS_W_ROXCL),


.COUNTER_Out(Counter_W_Size_Out),
.COUNTER_Eqn_Flag(Counter_W_Size_Eqn_Flag)

);



COUNTER_POS #(.BITWIDTH(BITWIDTH_W_COLUMS)) Counter_W_Col(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_W_Col_Clr),
.COUNTER_En(Rbus_Statemachine_Counter_W_Col_En),
.COUNTER_load(Counter_W_Col_Load),
.COUNTER_Data(data1_4),
.COUNTER_Number(RBUS_W_Colums),


.COUNTER_Out(Counter_W_Col_Out),
.COUNTER_Eqn_Flag(Counter_W_Col_Eqn_Flag)
);


COUNTER_POS #(.BITWIDTH(4)) Counter_Input(

.COUNTER_Clk(RBUS_Clk),
.COUNTER_Clr(Rbus_Statemachine_Counter_Input_Clr),
.COUNTER_En(Counter_W_Col_Eqn_Flag),
.COUNTER_load(Rbus_Statemachine_Counter_Input_Load),
.COUNTER_Data(data1_4),
.COUNTER_Number(maxInput),


.COUNTER_Out(Counter_Input_Out),
.COUNTER_Eqn_Flag(Counter_Input_Eqn_Flag)

);


RBUS_STATEMACHINE Rbus_Statemachine
(

.RBUS_STATEMACHINE_Clk(RBUS_Clk),
.RBUS_STATEMACHINE_Reset(RBUS_Reset),
.RBUS_STATEMACHINE_Start_Conf(RBUS_Set_Conf),
.RBUS_STATEMACHINE_Conf_Already_Ok(RBUS_Set_Conf_Already_Ok),
.RBUS_STATEMACHINE_Counter_Bus_Flag(Counter_Bus_Eqn_Flag),
.RBUS_STATEMACHINE_Counter_W_Size_Flag(Counter_W_Size_Eqn_Flag),

.RBUS_STATEMACHINE_Set_Conf_Already(RBUS_Set_Conf_Already),
.RBUS_STATEMACHINE_Counter_W_Size_En(Rbus_Statemachine_Counter_W_Size_En),
.RBUS_STATEMACHINE_Counter_W_Size_Clr(Rbus_Statemachine_Counter_W_Size_Clr),
.RBUS_STATEMACHINE_Counter_W_Col_En(Rbus_Statemachine_Counter_W_Col_En),
.RBUS_STATEMACHINE_Counter_W_Col_Load(Rbus_Statemachine_Counter_W_Col_Load),
.RBUS_STATEMACHINE_Counter_W_Col_Clr(Rbus_Statemachine_Counter_W_Col_Clr),
.RBUS_STATEMACHINE_Counter_Input_Clr(Rbus_Statemachine_Counter_Input_Clr),
.RBUS_STATEMACHINE_Counter_Input_Load(Rbus_Statemachine_Counter_Input_Load),
.RBUS_STATEMACHINE_Counter_Bus_En(Rbus_Statemachine_Counter_Bus_En),
.RBUS_STATEMACHINE_Counter_Bus_Clr(Rbus_Statemachine_Counter_Bus_Clr),
.RBUS_STATEMACHINE_Conf_Rutine(Rbus_Statemachine_Conf_Rutine),
.RBUS_STATEMACHINE_Bus_En(Rbus_Statemachine_Bus_En)
);







genvar i;
generate

	for (i = 0; i < LENGTHBUS ; i=i+1)   
	begin:bus
	
		assign RBUS_Om_SetEn[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
										 (Select[i] == 4'd1) ? RBUS_SetEn0 :
								       (Select[i] == 4'd2) ? RBUS_SetEn1 :
								       (Select[i] == 4'd3) ? RBUS_SetEn2 :
								       (Select[i] == 4'd4) ? RBUS_SetEn3 :
								       (Select[i] == 4'd5) ? RBUS_SetEn4 :
								       (Select[i] == 4'd6) ? RBUS_SetEn5 :
								       (Select[i] == 4'd7) ? RBUS_SetEn6 :
								       (Select[i] == 4'd8) ? RBUS_SetEn7 :
								       (Select[i] == 4'd9) ? RBUS_SetEn8 :
								       (Select[i] == 4'd10) ? RBUS_SetEn9 :
								       (Select[i] == 4'd11) ? RBUS_SetEn10 :
								       (Select[i] == 4'd12) ? RBUS_SetEn11 :
								       (Select[i] == 4'd13) ? RBUS_SetEn12 : 1'b0 :1'b0;
							
		assign RBUS_Om_OEn[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
									  (Select[i] == 4'd1) ? RBUS_OEn0 :
									  (Select[i] == 4'd2) ? RBUS_OEn1 :
								     (Select[i] == 4'd3) ? RBUS_OEn2 :
								     (Select[i] == 4'd4) ? RBUS_OEn3 :
								     (Select[i] == 4'd5) ? RBUS_OEn4 :
								     (Select[i] == 4'd6) ? RBUS_OEn5 :
								     (Select[i] == 4'd7) ? RBUS_OEn6 :
								     (Select[i] == 4'd8) ? RBUS_OEn7 :
								     (Select[i] == 4'd9) ? RBUS_OEn8 :
								     (Select[i] == 4'd10) ? RBUS_OEn9 :
								     (Select[i] == 4'd11) ? RBUS_OEn10 :
								     (Select[i] == 4'd12) ? RBUS_OEn11 :
								     (Select[i] == 4'd13) ? RBUS_OEn12 : 1'b0 :1'b0;
								 
      assign RBUS_Om_Wptclr[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
								        (Select[i] == 4'd1) ? RBUS_Wptclr0 :
								        (Select[i] == 4'd2) ? RBUS_Wptclr1 :
								        (Select[i] == 4'd3) ? RBUS_Wptclr2 :
								        (Select[i] == 4'd4) ? RBUS_Wptclr3 :
								        (Select[i] == 4'd5) ? RBUS_Wptclr4 :
								        (Select[i] == 4'd6) ? RBUS_Wptclr5 :
								        (Select[i] == 4'd7) ? RBUS_Wptclr6 :
								        (Select[i] == 4'd8) ? RBUS_Wptclr7 :
								        (Select[i] == 4'd9) ? RBUS_Wptclr8 :
								        (Select[i] == 4'd10) ? RBUS_Wptclr9 :
								        (Select[i] == 4'd11) ? RBUS_Wptclr10 :
								        (Select[i] == 4'd12) ? RBUS_Wptclr11 :
								        (Select[i] == 4'd13) ? RBUS_Wptclr12 : 1'b0 :1'b0;
								 
								 
		assign RBUS_Om_Rptclr[i]= (Rbus_Statemachine_Bus_En == 1'b1) ?  
								        (Select[i] == 4'd1) ? RBUS_Rptclr0 :
								        (Select[i] == 4'd2) ? RBUS_Rptclr1 :
								        (Select[i] == 4'd3) ? RBUS_Rptclr2 :
								        (Select[i] == 4'd4) ? RBUS_Rptclr3 :
							           (Select[i] == 4'd5) ? RBUS_Rptclr4 :
								        (Select[i] == 4'd6) ? RBUS_Rptclr5 :
								        (Select[i] == 4'd7) ? RBUS_Rptclr6 :
								        (Select[i] == 4'd8) ? RBUS_Rptclr7 :
								        (Select[i] == 4'd9) ? RBUS_Rptclr8 :
								        (Select[i] == 4'd10) ? RBUS_Rptclr9 :
								        (Select[i] == 4'd11) ? RBUS_Rptclr10 :
								        (Select[i] == 4'd12) ? RBUS_Rptclr11 :
								        (Select[i] == 4'd13) ? RBUS_Rptclr12 : 1'b0 :1'b0;				 
	end
	
endgenerate 


assign Counter_W_Col_Load =(Counter_W_Col_Load_1 | Rbus_Statemachine_Counter_W_Col_Load);


endmodule