data/full_repos/permissive/486598419/6.2/transmission8_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=0;B=0;C=1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=0;B=1;C=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=0;B=1;C=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=1;B=0;C=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=1;B=0;C=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=1;B=1;C=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=1;B=1;C=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #40 A=0;B=0;C=0;\n      ^\n%Error: data/full_repos/permissive/486598419/6.2/transmission8_tb.v:44: Cannot find file containing module: \'transmission8\'\n   transmission8\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.2,data/full_repos/permissive/486598419/transmission8\n             data/full_repos/permissive/486598419/6.2,data/full_repos/permissive/486598419/transmission8.v\n             data/full_repos/permissive/486598419/6.2,data/full_repos/permissive/486598419/transmission8.sv\n             transmission8\n             transmission8.v\n             transmission8.sv\n             obj_dir/transmission8\n             obj_dir/transmission8.v\n             obj_dir/transmission8.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module transmission8_tb();
   reg[7:0]iData;
   reg A;
   reg B;
   reg C;
   wire [7:0]oData;
   initial
   begin
      iData=8'b00000000;
      A=0;
      B=0;
      C=0;
      #40 A=0;B=0;C=1;
      #40 A=0;B=1;C=0;
      #40 A=0;B=1;C=1;
      #40 A=1;B=0;C=0;
      #40 A=1;B=0;C=1;
      #40 A=1;B=1;C=0;
      #40 A=1;B=1;C=1;
      #40 A=0;B=0;C=0;
   end
   transmission8
   transmission8_inst(
      .iData(iData),
      .A(A),
      .B(B),
      .C(C),
      .oData(oData)
      );
      
endmodule
module transmission8_tb();

   reg[7:0]iData;
   reg A;
   reg B;
   reg C;
   wire [7:0]oData;
   initial
   begin
      iData=8'b00000000;
      A=0;
      B=0;
      C=0;
      #40 A=0;B=0;C=1;
      #40 A=0;B=1;C=0;
      #40 A=0;B=1;C=1;
      #40 A=1;B=0;C=0;
      #40 A=1;B=0;C=1;
      #40 A=1;B=1;C=0;
      #40 A=1;B=1;C=1;
      #40 A=0;B=0;C=0;
   end
   transmission8
   transmission8_inst(
      .iData(iData),
      .A(A),
      .B(B),
      .C(C),
      .oData(oData)
      );
      
endmodule