data/full_repos/permissive/423547971/FPGA Projects/Nexys to Basys Test 1(ROM to RAM)/Basys3 part/ram.v
1: b'%Error: Cannot find file containing module: Projects/Nexys\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.sv\n             Projects/Nexys\n             Projects/Nexys.v\n             Projects/Nexys.sv\n             obj_dir/Projects/Nexys\n             obj_dir/Projects/Nexys.v\n             obj_dir/Projects/Nexys.sv\n%Error: Cannot find file containing module: to\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: Test\n%Error: Cannot find file containing module: 1(ROM\n%Error: Cannot find file containing module: RAM)/Basys3\n%Error: Cannot find file containing module: part,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: part/ram.v\n%Error: Exiting due to 9 error(s)\n'
module ram(
    input sync_in,
    input wr_en,
    input [3:0] addr,
    input [3:0] data_in,
    output [3:0] data_out
    );
    
    reg [3:0] ram [15:0];
    
    always @(posedge sync_in)
        if(wr_en)
            ram[addr] <= data_in;
            
    assign data_out = ram[addr];
    
endmodule
module ram(
    input sync_in,
    input wr_en,
    input [3:0] addr,
    input [3:0] data_in,
    output [3:0] data_out
    );

    
    reg [3:0] ram [15:0];
    
    always @(posedge sync_in)
        if(wr_en)
            ram[addr] <= data_in;
            
    assign data_out = ram[addr];
    
endmodule