data/full_repos/permissive/429641629/sources_1/new/clk_div.v
1: b'%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/clk_div.v:36: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                               : ... In instance clk_div\nreg [10:0] cnt_5M = 6\'b0;\n                    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/clk_div.v:44: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance clk_div\n            cnt_seg <= 1\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/clk_div.v:55: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance clk_div\n            cnt_5M <= 1\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/clk_div.v:52: Operator GTE expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cnt_5M\' generates 11 bits.\n                                                                               : ... In instance clk_div\n        if(cnt_5M >= (50000000/(freqz*4096*2)))  \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/clk_div.v:66: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance clk_div\n            cnt_16u <= 1\'b0;\n                    ^~\n%Error: Exiting due to 5 warning(s)\n'
module clk_div (
	input	clk,
	input   [7:0]freqz,
	output reg clk_5M =1'b0,
	output reg clk_16u = 1'b0,
	output reg clk_seg = 1'b0

	);
	

reg [7:0] cnt_16u = 8'b0;
reg [2:0]       cnt_1=3'b0;
reg [14:0] cnt_seg = 15'b0;
reg [10:0] cnt_5M = 6'b0;

    
always @ (posedge clk)
    begin
        if(cnt_seg >= 15'd25000)
        begin
            clk_seg <= ~clk_seg;
            cnt_seg <= 1'b0;
        end
        else
            cnt_seg <= cnt_seg + 1'b1;
    end
    
always @ (posedge clk)
    begin
        if(cnt_5M >= (50000000/(freqz*4096*2)))
        begin
            clk_5M <= ~clk_5M;
            cnt_5M <= 1'b0;
        end
        else
            cnt_5M <= cnt_5M + 1'b1;
    end
    
always @ (posedge clk)
    begin
        if(cnt_16u >= 8'd163)
        begin
            clk_16u <= ~clk_16u;
            cnt_16u <= 1'b0;
        end
        else
            cnt_16u <= cnt_16u + 1'b1;
    end
endmodule
module clk_div (
	input	clk,
	input   [7:0]freqz,
	output reg clk_5M =1'b0,
	output reg clk_16u = 1'b0,
	output reg clk_seg = 1'b0

	);

	

reg [7:0] cnt_16u = 8'b0;
reg [2:0]       cnt_1=3'b0;
reg [14:0] cnt_seg = 15'b0;
reg [10:0] cnt_5M = 6'b0;

    
always @ (posedge clk)
    begin
        if(cnt_seg >= 15'd25000)
        begin
            clk_seg <= ~clk_seg;
            cnt_seg <= 1'b0;
        end
        else
            cnt_seg <= cnt_seg + 1'b1;
    end
    
always @ (posedge clk)
    begin
        if(cnt_5M >= (50000000/(freqz*4096*2)))
        begin
            clk_5M <= ~clk_5M;
            cnt_5M <= 1'b0;
        end
        else
            cnt_5M <= cnt_5M + 1'b1;
    end
    
always @ (posedge clk)
    begin
        if(cnt_16u >= 8'd163)
        begin
            clk_16u <= ~clk_16u;
            cnt_16u <= 1'b0;
        end
        else
            cnt_16u <= cnt_16u + 1'b1;
    end
endmodule