data/full_repos/permissive/503053625/resources/verilog_source/gen_l_padder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503053625/resources/verilog_source/gen_l_padder.v:15: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                               : ... In instance gen_l_padder\n assign out = {left_pad, in};\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module gen_l_padder
#(
	parameter IN_WIDTH = 12,
	parameter OUT_WIDTH = 32,
	parameter L_PAD_WIDTH = 4
)
(
	input wire [IN_WIDTH - 1:0] in,
	output wire [OUT_WIDTH - 1:0] out
);
	reg [L_PAD_WIDTH - 1 :0] left_pad;
	wire [L_PAD_WIDTH - 1:0] left_zeros_pad = {L_PAD_WIDTH{1'b0}};
	wire [L_PAD_WIDTH - 1:0] left_ones_pad = {L_PAD_WIDTH{1'b1}};

	assign out = {left_pad, in};
	always @(in)
	begin
		if (in[IN_WIDTH-1])
		begin
			left_pad = left_ones_pad;
		end
		else
		begin
			left_pad = left_zeros_pad;
		end
	end

endmodule
module gen_l_padder
#(
	parameter IN_WIDTH = 12,
	parameter OUT_WIDTH = 32,
	parameter L_PAD_WIDTH = 4
)
(
	input wire [IN_WIDTH - 1:0] in,
	output wire [OUT_WIDTH - 1:0] out
);

	reg [L_PAD_WIDTH - 1 :0] left_pad;
	wire [L_PAD_WIDTH - 1:0] left_zeros_pad = {L_PAD_WIDTH{1'b0}};
	wire [L_PAD_WIDTH - 1:0] left_ones_pad = {L_PAD_WIDTH{1'b1}};

	assign out = {left_pad, in};
	always @(in)
	begin
		if (in[IN_WIDTH-1])
		begin
			left_pad = left_ones_pad;
		end
		else
		begin
			left_pad = left_zeros_pad;
		end
	end

endmodule