data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new/CPU_Test.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sim_1/new/CPU_Test.v\n%Error: Exiting due to 3 error(s)\n'
module CPU_Test();

    reg clk, rst;
    reg [31:0] pcin;
    wire [31:0] pcout;



    wire [31:0] dowire;




    wire [5:0] opwire;
    wire [5:0] funcwire;
    wire [4:0] rdwire, rtwire, rswire;
    wire [15:0] immwire;




    wire wregwire, m2regwire, wmemwire, aluimmwire;
    wire regrtwire;
    wire [3:0] alucwire;


    reg wewire;

    wire [4:0] wnwire;
    wire [4:0] dwire;
    wire [31:0] qawire, qbwire;




    wire [4:0] muxwire;



    wire [31:0] longwire;








    wire ewregwire, em2regwire, ewmemwire, ealuimmwire;
    wire [3:0] ealucwire;
    wire [31:0] eqbwire, eqawire, Extenderwire;
    wire [4:0] emuxwire;



    PC pc(clk,rst,pcin, pcout);
    InstructMem instmem(pcin, dowire);
    IFID ifid(clk, dowire, opwire, funcwire, rdwire, rswire, rtwire, immwire);
    ControlUnit ctrunit(opwire, funcwire, wregwire, m2regwire, wmemwire, 
                        aluimmwire, regrtwire, alucwire);
    RegFile regfile(wewire, rswire, rtwire, wnwire, dwire, qawire, qbwire);
    ControlMux ctrmux(regrtwire, rdwire, rtwire,muxwire);
    SignExtend extender(immwire, longwire);
    IDEXE idexe(clk, wregwire, m2regwire, wmemwire, aluimmwire, alucwire,
                qawire, qbwire, muxwire, longwire, ewregwire, em2regwire,
                ewmemwire, ealuimmwire, ealucwire, eqawire, eqbwire, 
                emuxwire, Extenderwire);

    initial begin
        clk = 1;
        pcin = 100;
        rst = 1;
        #1 rst = 0;     
    end

    always begin
        #5 clk = !clk;
    end
endmodule
module CPU_Test();


    reg clk, rst;
    reg [31:0] pcin;
    wire [31:0] pcout;



    wire [31:0] dowire;




    wire [5:0] opwire;
    wire [5:0] funcwire;
    wire [4:0] rdwire, rtwire, rswire;
    wire [15:0] immwire;




    wire wregwire, m2regwire, wmemwire, aluimmwire;
    wire regrtwire;
    wire [3:0] alucwire;


    reg wewire;

    wire [4:0] wnwire;
    wire [4:0] dwire;
    wire [31:0] qawire, qbwire;




    wire [4:0] muxwire;



    wire [31:0] longwire;








    wire ewregwire, em2regwire, ewmemwire, ealuimmwire;
    wire [3:0] ealucwire;
    wire [31:0] eqbwire, eqawire, Extenderwire;
    wire [4:0] emuxwire;



    PC pc(clk,rst,pcin, pcout);
    InstructMem instmem(pcin, dowire);
    IFID ifid(clk, dowire, opwire, funcwire, rdwire, rswire, rtwire, immwire);
    ControlUnit ctrunit(opwire, funcwire, wregwire, m2regwire, wmemwire, 
                        aluimmwire, regrtwire, alucwire);
    RegFile regfile(wewire, rswire, rtwire, wnwire, dwire, qawire, qbwire);
    ControlMux ctrmux(regrtwire, rdwire, rtwire,muxwire);
    SignExtend extender(immwire, longwire);
    IDEXE idexe(clk, wregwire, m2regwire, wmemwire, aluimmwire, alucwire,
                qawire, qbwire, muxwire, longwire, ewregwire, em2regwire,
                ewmemwire, ealuimmwire, ealucwire, eqawire, eqbwire, 
                emuxwire, Extenderwire);

    initial begin
        clk = 1;
        pcin = 100;
        rst = 1;
        #1 rst = 0;     
    end

    always begin
        #5 clk = !clk;
    end
endmodule