data/full_repos/permissive/423216890/src_v/enet_dp_ram.v
data/verilator_xmls/da4c5bef-f041-4061-98b4-2ecdb6ecd49e.xml
module enet_dp_ram
#(
    parameter WIDTH   = 32
   ,parameter ADDR_W  = 5
)
(

     input                clk0_i
    ,input  [ADDR_W-1:0]  addr0_i
    ,input  [WIDTH-1:0]   data0_i
    ,input                wr0_i
    ,input                clk1_i
    ,input  [ADDR_W-1:0]  addr1_i
    ,input  [WIDTH-1:0]   data1_i
    ,input                wr1_i


    ,output [WIDTH-1:0]  data0_o
    ,output [WIDTH-1:0]  data1_o
);


reg [WIDTH-1:0]   ram [(2**ADDR_W)-1:0];


reg [WIDTH-1:0] ram_read0_q;
reg [WIDTH-1:0] ram_read1_q;


always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module enet_dp_ram
#(
    parameter WIDTH   = 32
   ,parameter ADDR_W  = 5
)
(

     input                clk0_i
    ,input  [ADDR_W-1:0]  addr0_i
    ,input  [WIDTH-1:0]   data0_i
    ,input                wr0_i
    ,input                clk1_i
    ,input  [ADDR_W-1:0]  addr1_i
    ,input  [WIDTH-1:0]   data1_i
    ,input                wr1_i


    ,output [WIDTH-1:0]  data0_o
    ,output [WIDTH-1:0]  data1_o
);



reg [WIDTH-1:0]   ram [(2**ADDR_W)-1:0];


reg [WIDTH-1:0] ram_read0_q;
reg [WIDTH-1:0] ram_read1_q;


always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule