data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:39: syntax error, unexpected ',', expecting IDENTIFIER or do or final\nmodule memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);\n                                           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:45: syntax error, unexpected output\noutput y3, y4;\n^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:52: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module memtest12 (
   input clk,
   input [1:0] adr,
   input [1:0] din,
   output reg [1:0] q
);
   reg [1:0] ram [3:0];
   always@(posedge clk)
     {ram[adr], q} <= {din, ram[adr]};
endmodule
module memtest12 (
   input clk,
   input [1:0] adr,
   input [1:0] din,
   output reg [1:0] q
);

   reg [1:0] ram [3:0];
   always@(posedge clk)
     {ram[adr], q} <= {din, ram[adr]};
endmodule