data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #3 Address_w = i[7:0];\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #10 Data_I = {ssin,ccos};\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:83: Unsupported: Ignoring delay on this delayed statement.\n   #10 W = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:84: Unsupported: Ignoring delay on this delayed statement.\n   #10 W = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:85: Unsupported: Ignoring delay on this delayed statement.\n   #10 Address = i[7:0];\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:86: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:97: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_tst.v:44: Cannot find file containing module: \'RAM_Block\'\n RAM_Block uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/RAM_Block\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/RAM_Block.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/RAM_Block.sv\n             RAM_Block\n             RAM_Block.v\n             RAM_Block.sv\n             obj_dir/RAM_Block\n             obj_dir/RAM_Block.v\n             obj_dir/RAM_Block.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RAM_tst;


	reg clk;
	reg [7:0] Address_w;
	reg [7:0] Address;
	reg W_ref;
	reg W;
	reg [31:0] Data_I;


	wire [31:0] Data_O;
	wire [15:0] Ref;
	
	reg [8:0] i;
	reg [15:0] ssin;
	reg [15:0] ccos;


	RAM_Block uut (
		.clk(clk),
		.Address(Address), 
		.Address_w(Address_w), 
		.W(W),
		.W_ref(W_ref),
		.Data_I(Data_I), 
		.Data_O(Data_O), 
		.Ref(Ref)
	);

	initial begin

		clk = 0;
		Address_w = 0;
		Address = 0;
		W = 0;
		W_ref = 0;
		Data_I = 0;
		i = 0;
		ssin = 16'd143;
		ccos = 16'd8191;

		#100;

		for(i = 0; i <= 255; i = i+1) begin
			ssin = ssin+1;
			if(i == 13) ccos = 16'd8190;
			if(i == 55) ccos = 16'd8189;
			if(i == 89) ccos = 16'd8188;
			if(i == 118) ccos = 16'd8187;
			if(i == 145) ccos = 16'd8186;
			if(i == 169) ccos = 16'd8185;
			if(i == 191) ccos = 16'd8184;
			if(i == 212) ccos = 16'd8183;
			if(i == 231) ccos = 16'd8182;
			if(i == 250) ccos = 16'd8181;
			#3 Address_w = i[7:0];
			#10 Data_I = {ssin,ccos};
			#10 W = 1;
			#10 W = 0;
			#10 Address = i[7:0];
			#10;
		end
		Data_I = 32'd259;
		#10;
		W_ref = 1;
		#10;
		W_ref = 0;
		#100;
		Address = 128;
	end
	
	always #5 clk = !clk;
	
endmodule
module RAM_tst;



	reg clk;
	reg [7:0] Address_w;
	reg [7:0] Address;
	reg W_ref;
	reg W;
	reg [31:0] Data_I;


	wire [31:0] Data_O;
	wire [15:0] Ref;
	
	reg [8:0] i;
	reg [15:0] ssin;
	reg [15:0] ccos;


	RAM_Block uut (
		.clk(clk),
		.Address(Address), 
		.Address_w(Address_w), 
		.W(W),
		.W_ref(W_ref),
		.Data_I(Data_I), 
		.Data_O(Data_O), 
		.Ref(Ref)
	);

	initial begin

		clk = 0;
		Address_w = 0;
		Address = 0;
		W = 0;
		W_ref = 0;
		Data_I = 0;
		i = 0;
		ssin = 16'd143;
		ccos = 16'd8191;

		#100;

		for(i = 0; i <= 255; i = i+1) begin
			ssin = ssin+1;
			if(i == 13) ccos = 16'd8190;
			if(i == 55) ccos = 16'd8189;
			if(i == 89) ccos = 16'd8188;
			if(i == 118) ccos = 16'd8187;
			if(i == 145) ccos = 16'd8186;
			if(i == 169) ccos = 16'd8185;
			if(i == 191) ccos = 16'd8184;
			if(i == 212) ccos = 16'd8183;
			if(i == 231) ccos = 16'd8182;
			if(i == 250) ccos = 16'd8181;
			#3 Address_w = i[7:0];
			#10 Data_I = {ssin,ccos};
			#10 W = 1;
			#10 W = 0;
			#10 Address = i[7:0];
			#10;
		end
		Data_I = 32'd259;
		#10;
		W_ref = 1;
		#10;
		W_ref = 0;
		#100;
		Address = 128;
	end
	
	always #5 clk = !clk;
	
endmodule