data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/tb_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/tb_testbench.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/13_fsm_gate/tb_testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire clk, resetb;
wire ta, tb, la1, la0, lb1, lb0;   

LIGHT_test tester (.t1(clk), .t2(resetb), .t3(ta), .t4(tb), .p1(la1), .p2(la0), .p3(lb1), .p4(lb0));


LIGHT      dut (.CLK(clk), .RESETB(resetb), .TA(ta), .TB(tb), .LA1(la1), .LA0(la0), .LB1(lb1), .LB0(lb0));  



always @(clk or resetb or ta or tb or la1 or la0 or lb1 or lb0 )

begin
    #1;
    $display("%b %b %b %b %b%b %b%b", clk, resetb, ta, tb, la1, la0, lb1, lb0);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire clk, resetb;
wire ta, tb, la1, la0, lb1, lb0;   

LIGHT_test tester (.t1(clk), .t2(resetb), .t3(ta), .t4(tb), .p1(la1), .p2(la0), .p3(lb1), .p4(lb0));


LIGHT      dut (.CLK(clk), .RESETB(resetb), .TA(ta), .TB(tb), .LA1(la1), .LA0(la0), .LB1(lb1), .LB0(lb0));  



always @(clk or resetb or ta or tb or la1 or la0 or lb1 or lb0 )

begin
    #1;
    $display("%b %b %b %b %b%b %b%b", clk, resetb, ta, tb, la1, la0, lb1, lb0);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule