data/full_repos/permissive/505451992/encoder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n     reset = 1;#5\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n     reset = 0;#5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n     reset = 0;#5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 CLK=~CLK;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 B=~B;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 A=~A;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/encoder_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #75\n        ^\n%Error: data/full_repos/permissive/505451992/encoder_tb.v:35: Cannot find file containing module: \'encoder\'\n    encoder utt(.reset(reset),\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder.sv\n             encoder\n             encoder.v\n             encoder.sv\n             obj_dir/encoder\n             obj_dir/encoder.v\n             obj_dir/encoder.sv\n%Error: data/full_repos/permissive/505451992/encoder_tb.v:39: Cannot find file containing module: \'Converters\'\n        Converters uyy(.PPR(PPR),.P(P),.Position(Position));\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/encoder_tb.v:41: Cannot find file containing module: \'PWM_Generator\'\n        PWM_Generator pga(\n        ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module encoder_tb(

    );
    
    reg reset;
    reg CLK;
    reg A;
    reg B;
    reg[9:0] PPR;
    wire [9:0] P;
       wire [9:0] Position;
    
    encoder utt(.reset(reset),
     .CLK(CLK),.A(A),.B(B),.PPR(PPR),.P(P));
     
       
        Converters uyy(.PPR(PPR),.P(P),.Position(Position));
        
        PWM_Generator pga(
        .reset(reset),
        .CLK(CLK),

        .Position(Position),

        .pwm(PWM_AB)
            );    
     
     
     
     initial begin
     PPR = 599;
     reset = 1;#5
     reset = 0;#5;
     reset = 0;#5;
     end
     
    initial begin
    CLK=0;
    forever #5 CLK=~CLK;
    end
 
 
 



        initial begin
        B=0;
        #50
        forever #50 B=~B;
        end
        
        initial begin
        A=0;
        #75
        forever #50 A=~A;
        end
       
  
     
endmodule
module encoder_tb(

    );

    
    reg reset;
    reg CLK;
    reg A;
    reg B;
    reg[9:0] PPR;
    wire [9:0] P;
       wire [9:0] Position;
    
    encoder utt(.reset(reset),
     .CLK(CLK),.A(A),.B(B),.PPR(PPR),.P(P));
     
       
        Converters uyy(.PPR(PPR),.P(P),.Position(Position));
        
        PWM_Generator pga(
        .reset(reset),
        .CLK(CLK),

        .Position(Position),

        .pwm(PWM_AB)
            );    
     
     
     
     initial begin
     PPR = 599;
     reset = 1;#5
     reset = 0;#5;
     reset = 0;#5;
     end
     
    initial begin
    CLK=0;
    forever #5 CLK=~CLK;
    end
 
 
 



        initial begin
        B=0;
        #50
        forever #50 B=~B;
        end
        
        initial begin
        A=0;
        #75
        forever #50 A=~A;
        end
       
  
     
endmodule