data/full_repos/permissive/492462267/mem.v
1: b'%Error: data/full_repos/permissive/492462267/mem.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/mem.v:11: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   result_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegDataBus]   result_i,\n                            ^\n%Error: data/full_repos/permissive/492462267/mem.v:12: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   waddr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegDataBus]   hi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:14: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   hi_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:15: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   lo_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  reg[`RegDataBus]    result_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:19: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    result_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:20: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegDataBus]    hi_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:22: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    hi_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:23: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    lo_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:29: Define or directive not defined: \'`ZeroWord\'\n        result_o = `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:30: Define or directive not defined: \'`RegAddr_0\'\n        waddr_o  = `RegAddr_0;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:31: Define or directive not defined: \'`Disable\'\n        we_o     = `Disable;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:32: Define or directive not defined: \'`ZeroWord\'\n        hi_o     = `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:33: Define or directive not defined: \'`ZeroWord\'\n        lo_o     = `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem.v:34: Define or directive not defined: \'`Disable\'\n        whilo_o  = `Disable;\n                   ^~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module mem (
    input   wire    rst,


    input   wire[`RegDataBus]   result_i,
    input   wire[`RegAddrBus]   waddr_i,
    input   wire                we_i,
    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,
    input   wire                whilo_i,


    output  reg[`RegDataBus]    result_o,
    output  reg[`RegAddrBus]    waddr_o,
    output  reg                 we_o,
    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o,
    output  reg                 whilo_o
);

always @(*) begin
    if (rst) begin
        result_o = `ZeroWord;
        waddr_o  = `RegAddr_0;
        we_o     = `Disable;
        hi_o     = `ZeroWord;
        lo_o     = `ZeroWord;
        whilo_o  = `Disable;
    end else begin
        result_o = result_i;
        waddr_o  = waddr_i;
        we_o     = we_i;
        hi_o     = hi_i;
        lo_o     = lo_i;
        whilo_o  = whilo_i;
    end
end

endmodule
module mem (
    input   wire    rst,


    input   wire[`RegDataBus]   result_i,
    input   wire[`RegAddrBus]   waddr_i,
    input   wire                we_i,
    input   wire[`RegDataBus]   hi_i,
    input   wire[`RegDataBus]   lo_i,
    input   wire                whilo_i,


    output  reg[`RegDataBus]    result_o,
    output  reg[`RegAddrBus]    waddr_o,
    output  reg                 we_o,
    output  reg[`RegDataBus]    hi_o,
    output  reg[`RegDataBus]    lo_o,
    output  reg                 whilo_o
);


always @(*) begin
    if (rst) begin
        result_o = `ZeroWord;
        waddr_o  = `RegAddr_0;
        we_o     = `Disable;
        hi_o     = `ZeroWord;
        lo_o     = `ZeroWord;
        whilo_o  = `Disable;
    end else begin
        result_o = result_i;
        waddr_o  = waddr_i;
        we_o     = we_i;
        hi_o     = hi_i;
        lo_o     = lo_i;
        whilo_o  = whilo_i;
    end
end

endmodule