data/full_repos/permissive/439087417/cordicctrl.v
data/verilator_xmls/49a27085-f061-4757-9ee3-a856f1853e27.xml
module cordicctrl #(parameter rndw = 4)
(	input bgn, clk,
	input [rndw-1:0] itr,
	output reg init, ld, fin
    );
localparam S_WAIT = 2'b00;
localparam S_EXEC = 2'b01;
localparam S_END = 2'b10;

reg[1:0] state, state_next;

initial begin
	state = S_WAIT;
end

always @(posedge clk) begin

	state <= state_next;
end

always @(state, bgn, itr) begin
	ld = 1'b0;
	init = 1'b0;
	fin = 1'b0;
	case(state)
		S_WAIT: 
			if(bgn) begin
				ld <= 1'b1;
				init <= 1'b1;
				state_next <= S_EXEC;
			end
			else begin
				state_next <= S_WAIT;
			end
		S_EXEC:
			if(itr == 15) begin
				ld <= 1'b1;
				state_next <= S_END;
			end
			else begin
				ld <= 1'b1;
				state_next <= S_EXEC;
			end
		S_END:
			begin
				fin <= 1'b1;
				state_next <= S_WAIT;
			end
		endcase
end
	
endmodule
module cordicctrl #(parameter rndw = 4)
(	input bgn, clk,
	input [rndw-1:0] itr,
	output reg init, ld, fin
    );

localparam S_WAIT = 2'b00;
localparam S_EXEC = 2'b01;
localparam S_END = 2'b10;

reg[1:0] state, state_next;

initial begin
	state = S_WAIT;
end

always @(posedge clk) begin

	state <= state_next;
end

always @(state, bgn, itr) begin
	ld = 1'b0;
	init = 1'b0;
	fin = 1'b0;
	case(state)
		S_WAIT: 
			if(bgn) begin
				ld <= 1'b1;
				init <= 1'b1;
				state_next <= S_EXEC;
			end
			else begin
				state_next <= S_WAIT;
			end
		S_EXEC:
			if(itr == 15) begin
				ld <= 1'b1;
				state_next <= S_END;
			end
			else begin
				ld <= 1'b1;
				state_next <= S_EXEC;
			end
		S_END:
			begin
				fin <= 1'b1;
				state_next <= S_WAIT;
			end
		endcase
end
	
endmodule