data/full_repos/permissive/475150805/testbench.v
1: b'%Error: data/full_repos/permissive/475150805/testbench.v:9: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("dump.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/475150805/testbench.v:10: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,tb);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/475150805/testbench.v:15: Unsupported or unknown PLI call: $monitor\n            $monitor($time,"       ",a," *",b," = ", z);\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/475150805/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    wire signed [15:0] z;
    reg signed [7:0] a,b;   

    boothmul my_booth(.a(a),.b(b),.c(z));

    initial 
        begin
            $dumpfile("dump.vcd");
            $dumpvars(0,tb);
        end

    initial
        begin
            $monitor($time,"       ",a," *",b," = ", z);
            a = 8'b10101110;
            b = 8'b100111;
            #1
            a = 8'b11110000;
            b = 8'b11010000;
            #1
            a = 8'b10011101;
            b = 8'b10000;
            #1
            a = 8'b0111;
            b = 8'b01100101;
            #1
            b = 8'b10;
            a = 8'b111;
            #1
            a = 8'b0011100;
            b = 8'b0101;
            #1
            a = 8'b010001;
            b = 8'b1100;
            #1
            a = 8'b10010;
            b = 8'b1011111;
        end
endmodule
module tb;

    wire signed [15:0] z;
    reg signed [7:0] a,b;   

    boothmul my_booth(.a(a),.b(b),.c(z));

    initial 
        begin
            $dumpfile("dump.vcd");
            $dumpvars(0,tb);
        end

    initial
        begin
            $monitor($time,"       ",a," *",b," = ", z);
            a = 8'b10101110;
            b = 8'b100111;
            #1
            a = 8'b11110000;
            b = 8'b11010000;
            #1
            a = 8'b10011101;
            b = 8'b10000;
            #1
            a = 8'b0111;
            b = 8'b01100101;
            #1
            b = 8'b10;
            a = 8'b111;
            #1
            a = 8'b0011100;
            b = 8'b0101;
            #1
            a = 8'b010001;
            b = 8'b1100;
            #1
            a = 8'b10010;
            b = 8'b1011111;
        end
endmodule