data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:24: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2)  clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD*2) rst  =  0;\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:45: syntax error, unexpected \'@\'\n    @(negedge rst);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:46: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:51: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:53: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:58: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:60: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:65: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:67: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:72: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:74: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:79: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/515455663/multiplier/mult_basic/tb/tb_mult_basic.v:81: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: Exiting due to 12 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mult_pipe;


parameter PERIOD = 10;
parameter M  = 5;
parameter N  = 4;


reg   clk                                  = 0 ;
reg   rst                                  = 1 ;
reg   mult_enable                        = 0 ;
reg   [M-1:0]  mult_in_a                   = 0 ;
reg   [N-1:0]  mult_in_b                   = 0 ;


wire  mult_out_valid                       ;
wire  [M+N-1:0]  mult_out                  ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst  =  0;
end
    mult_basic#(
        .M            ( M ),
        .N            ( N )
    )u_mult_basic(
        .clk          ( clk          ),
        .rst          ( rst          ),
        .mult_enable  ( mult_enable  ),
        .mult_in_a    ( mult_in_a    ),
        .mult_in_b    ( mult_in_b    ),
        .mult_out     ( mult_out     ),
        .mult_out_valid  ( mult_out_valid  )
    );

initial begin
    @(negedge rst);
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = 4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = -5'd12;
    mult_in_b = 4'd4;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = -5'd12;
    mult_in_b = -4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = -4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = 4'd5;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    
end

endmodule
module tb_mult_pipe;



parameter PERIOD = 10;
parameter M  = 5;
parameter N  = 4;


reg   clk                                  = 0 ;
reg   rst                                  = 1 ;
reg   mult_enable                        = 0 ;
reg   [M-1:0]  mult_in_a                   = 0 ;
reg   [N-1:0]  mult_in_b                   = 0 ;


wire  mult_out_valid                       ;
wire  [M+N-1:0]  mult_out                  ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst  =  0;
end
    mult_basic#(
        .M            ( M ),
        .N            ( N )
    )u_mult_basic(
        .clk          ( clk          ),
        .rst          ( rst          ),
        .mult_enable  ( mult_enable  ),
        .mult_in_a    ( mult_in_a    ),
        .mult_in_b    ( mult_in_b    ),
        .mult_out     ( mult_out     ),
        .mult_out_valid  ( mult_out_valid  )
    );

initial begin
    @(negedge rst);
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = 4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = -5'd12;
    mult_in_b = 4'd4;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = -5'd12;
    mult_in_b = -4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = -4'd3;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    mult_enable = 1'b1;
    mult_in_a = 5'd12;
    mult_in_b = 4'd5;
    @(posedge clk);
    mult_enable = 1'b0;
    repeat(100) @(posedge clk);

    
end

endmodule