data/full_repos/permissive/512700783/Control_unit.v
data/verilator_xmls/2335a3cb-b07c-47ef-871a-b265d7c6213b.xml
module Control_unit(Op, Mem_reg, Mem_write, Branch, ALU_Op, ALU_src, Reg_dst, Reg_write, Jump, Clk);
	input [5:0] Op;
    	input Clk;
    	output reg Mem_reg, Mem_write, Branch, ALU_src, Reg_dst, Reg_write, Jump;
    	output reg [1:0] ALU_Op;
	
    	always @(Op or posedge Clk)



	begin					
        case(Op)
        6'b000000:
        begin
            	Reg_dst=1;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=0;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=2;
            	Jump=0;
        end
        6'b001000:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=0;
            	Reg_write=0;
            	Mem_write=0;
           	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b100011:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=1;
            	Reg_write=0;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b101011:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=1;
            	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b000100:
        begin
            	Reg_dst=0;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=1;
            	Branch=1;
            	ALU_Op=1;
            	Jump=0;
        end
        6'b000010:
        begin
            	Reg_dst=0;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=0;
            	Jump=1;
        end
        endcase
    end
endmodule
module Control_unit(Op, Mem_reg, Mem_write, Branch, ALU_Op, ALU_src, Reg_dst, Reg_write, Jump, Clk);

	input [5:0] Op;
    	input Clk;
    	output reg Mem_reg, Mem_write, Branch, ALU_src, Reg_dst, Reg_write, Jump;
    	output reg [1:0] ALU_Op;
	
    	always @(Op or posedge Clk)



	begin					
        case(Op)
        6'b000000:
        begin
            	Reg_dst=1;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=0;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=2;
            	Jump=0;
        end
        6'b001000:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=0;
            	Reg_write=0;
            	Mem_write=0;
           	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b100011:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=1;
            	Reg_write=0;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b101011:
        begin
            	Reg_dst=0;
            	ALU_src=1;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=1;
            	Branch=0;
            	ALU_Op=0;
            	Jump=0;
        end
        6'b000100:
        begin
            	Reg_dst=0;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=1;
            	Branch=1;
            	ALU_Op=1;
            	Jump=0;
        end
        6'b000010:
        begin
            	Reg_dst=0;
            	ALU_src=0;
            	Mem_reg=0;
            	Reg_write=1;
            	Mem_write=0;
            	Branch=0;
            	ALU_Op=0;
            	Jump=1;
        end
        endcase
    end
endmodule