data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp13anon6/reference/MultiClockSpecanonfun22anonfunapplymcVsp13anon6.v
data/verilator_xmls/b839b058-7aa8-40d3-86d3-f7663e9f38e0.xml
module DFF_POSCLK(q, d, clk);
    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule
module DFF_POSCLK(q, d, clk);

    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule