data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v
1: b'%Error: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:78: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(11)) u_extratext_line (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517390617/modules/raizing_video,data/full_repos/permissive/517390617/jtframe_linebuf\n             data/full_repos/permissive/517390617/modules/raizing_video,data/full_repos/permissive/517390617/jtframe_linebuf.v\n             data/full_repos/permissive/517390617/modules/raizing_video,data/full_repos/permissive/517390617/jtframe_linebuf.sv\n             jtframe_linebuf\n             jtframe_linebuf.v\n             jtframe_linebuf.sv\n             obj_dir/jtframe_linebuf\n             obj_dir/jtframe_linebuf.v\n             obj_dir/jtframe_linebuf.sv\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:97: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x\' generates 9 bits.\n                                                                                                 : ... In instance raizing_extratext\nwire signed [9:0] buf_code = (x<<3) - offset + tx;\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:97: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 9 bits.\n                                                                                                 : ... In instance raizing_extratext\nwire signed [9:0] buf_code = (x<<3) - offset + tx;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:97: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                                 : ... In instance raizing_extratext\nwire signed [9:0] buf_code = (x<<3) - offset + tx;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:161: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'extratoffs\' generates 6 bits.\n                                                                                                  : ... In instance raizing_extratext\n                    offset<=(TEXTSCROLL_DATA+extratoffs);\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:162: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'extratoffs\' generates 6 bits.\n                                                                                                  : ... In instance raizing_extratext\n                    startx<=((TEXTSCROLL_DATA+extratoffs)>>3) & 8\'h3F;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:162: Operator AND expects 16 bits on the RHS, but RHS\'s CONST \'8\'h3f\' generates 8 bits.\n                                                                                                  : ... In instance raizing_extratext\n                    startx<=((TEXTSCROLL_DATA+extratoffs)>>3) & 8\'h3F;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:166: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s CONST \'8\'h1f\' generates 8 bits.\n                                                                                                  : ... In instance raizing_extratext\n                    tilerow_start<=(line & (8\'h1F<<3))<<3;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:173: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'x\' generates 9 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        TEXTVRAM_ADDR<=(tilerow_start) + ((x+startx) & 8\'h3F);\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:173: Operator AND expects 16 bits on the RHS, but RHS\'s CONST \'8\'h3f\' generates 8 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        TEXTVRAM_ADDR<=(tilerow_start) + ((x+startx) & 8\'h3F);\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:173: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        TEXTVRAM_ADDR<=(tilerow_start) + ((x+startx) & 8\'h3F);\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:176: Operator AND expects 32 or 16 bits on the RHS, but RHS\'s CONST \'12\'h3ff\' generates 12 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        tile_data_pointer<=(((TEXTVRAM_DATA & 12\'h3FF) << 5) + ((line & 7) << 2))>>1;\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:177: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'textpal_offs\' generates 12 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        tile_palette_pointer<=(textpal_offs+(((TEXTVRAM_DATA >> 6) & 16\'h03F0)<<1))>>1;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:178: Operator AND expects 32 or 16 bits on the RHS, but RHS\'s CONST \'12\'h3ff\' generates 12 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        TEXTROM_ADDR<=(((TEXTVRAM_DATA & 12\'h3FF) << 5) + ((line & 7) << 2))>>1;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:178: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 16 bits.\n                                                                                                  : ... In instance raizing_extratext\n                        TEXTROM_ADDR<=(((TEXTVRAM_DATA & 12\'h3FF) << 5) + ((line & 7) << 2))>>1;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:180: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                                  : ... In instance raizing_extratext\n                    7: TEXTROM_ADDR<=tile_data_pointer+1;\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:196: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 10 bits.\n                                                                                                  : ... In instance raizing_extratext\n                                    buf_addr<=FLIPX ? 319-buf_code : buf_code;  \n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:197: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tile_palette_pointer\' generates 16 bits.\n                                                                                                  : ... In instance raizing_extratext\n                                    buf_data<=tile_palette_pointer+(((tile_data >> ((7-tx)*4)) & 8\'h0F));\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:197: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hf\' generates 8 bits.\n                                                                                                  : ... In instance raizing_extratext\n                                    buf_data<=tile_palette_pointer+(((tile_data >> ((7-tx)*4)) & 8\'h0F));\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:197: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                                  : ... In instance raizing_extratext\n                                    buf_data<=tile_palette_pointer+(((tile_data >> ((7-tx)*4)) & 8\'h0F));\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:199: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 10 bits.\n                                                                                                  : ... In instance raizing_extratext\n                                buf_addr<=FLIPX ? 319-buf_code : buf_code;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:195: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hf\' generates 8 bits.\n                                                                                                  : ... In instance raizing_extratext\n                            if((((tile_data >> ((7-tx)*4)) & 8\'h0F)) > 0) begin\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/517390617/modules/raizing_video/raizing_extratext.v:170: Operator LT expects 9 bits on the RHS, but RHS\'s VARREF \'tile_max\' generates 6 bits.\n                                                                                                  : ... In instance raizing_extratext\n            if(x<tile_max) begin\n                ^\n%Error: Exiting due to 1 error(s), 22 warning(s)\n'
module raizing_extratext (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    output reg [10:0] EXTRATEXT_PIXEL,
    input FLIPX,


    output reg [13:0] TEXTROM_ADDR,
    input  [15:0] TEXTROM_DATA,


    output reg [11:0] TEXTVRAM_ADDR,
    input  [15:0] TEXTVRAM_DATA,


    output reg [7:0] TEXTSELECT_ADDR,
    input [15:0] TEXTSELECT_DATA,


    output reg [7:0] TEXTSCROLL_ADDR,
    input [15:0] TEXTSCROLL_DATA,

    input [7:0] GAME
);

localparam GAREGGA = 'h0, KINGDMGP = 'h2, SSTRIKER = 'h1;

reg [10:0] buf_data = 0;
reg [8:0] buf_addr = 0;
reg buf_we = 1'b0;
wire [10:0] pretext_pxl;

reg [15:0] line, offset, startx, tilerow_start, ptile, tile_data_pointer, tile_palette_pointer;
reg [31:0] tile_data;
reg [8:0] xpos;
reg [7:0] st = 0;

wire [5:0] extratoffs = GAME == SSTRIKER ? 6'h2B : 6'h2C;
wire [11:0] textpal_offs = 12'h800;

wire [5:0] tile_max=6'd41;

reg [8:0] x=0;

wire [8:0] buf_addr_out = H;

wire [10:0] rd_gated;

jtframe_linebuf #(.DW(11)) u_extratext_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(buf_data),
    .we(buf_we),
    .rd_addr(buf_addr_out),
    .rd_data(pretext_pxl),
    .rd_gated()
);

reg last_HB, start, last_start;
wire pedg_HB = !HB && last_HB;
reg busy = 1'b0;
wire [8:0] y = VRENDER;

reg [8:0] tx = 0;

wire signed [9:0] buf_code = (x<<3) - offset + tx;
always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
        st<=0;
        x<=0;

        start<=1'b0;
        busy<=1'b0;
        tx<=0;
        line<=0;
        offset<=0;
        startx<=0;
        tilerow_start<=0;
        ptile<=0;
        tile_data_pointer<=0;
        tile_palette_pointer<=0;
        tile_data<=0;
        xpos<=0;
        st <= 0;
        TEXTROM_ADDR<=0;
        TEXTVRAM_ADDR<=0;
        TEXTSELECT_ADDR<=0;
        TEXTSCROLL_ADDR<=0;
    end
    else begin

        if(PIXEL_CEN && ACTIVE) begin
            EXTRATEXT_PIXEL<=pretext_pxl;
        end

        last_HB    <= HB;

        if( (pedg_HB && !VB)  || (((!FLIPX && VRENDER == 0) || (FLIPX && VRENDER == 239)) && pedg_HB)) begin
            start <= 1'b1;
        end

        if(start && !busy) begin
            start<=1'b0;
            busy<=1'b1;
            tx<=0;
            line<=0;
            offset<=0;
            startx<=0;
            tilerow_start<=0;
            ptile<=0;
            tile_data_pointer<=0;
            tile_palette_pointer<=0;
            tile_data<=0;
            xpos<=0;
            st <= 0;
            TEXTROM_ADDR<=0;
            TEXTVRAM_ADDR<=0;
            TEXTSELECT_ADDR<=0;
            TEXTSCROLL_ADDR<=0;
            x<=0;
        end else if(busy) begin
            st<=st+1'b1;
            case(st)
                0: begin
                    TEXTSELECT_ADDR<=y[7:0];
                    TEXTSCROLL_ADDR<=y[7:0];
                end
                2: begin
                    line<=TEXTSELECT_DATA;
                    offset<=(TEXTSCROLL_DATA+extratoffs);
                    startx<=((TEXTSCROLL_DATA+extratoffs)>>3) & 8'h3F;
                    
                end
                3: begin
                    tilerow_start<=(line & (8'h1F<<3))<<3;
                    offset<=offset&7;
                end
            endcase
            if(x<tile_max) begin
                case(st)
                    4: begin
                        TEXTVRAM_ADDR<=(tilerow_start) + ((x+startx) & 8'h3F);
                    end
                    6: begin
                        tile_data_pointer<=(((TEXTVRAM_DATA & 12'h3FF) << 5) + ((line & 7) << 2))>>1;
                        tile_palette_pointer<=(textpal_offs+(((TEXTVRAM_DATA >> 6) & 16'h03F0)<<1))>>1;
                        TEXTROM_ADDR<=(((TEXTVRAM_DATA & 12'h3FF) << 5) + ((line & 7) << 2))>>1;
                    end
                    7: TEXTROM_ADDR<=tile_data_pointer+1;
                    8: begin
                        tile_data[31:16]<=TEXTROM_DATA;
                    end
                    9: begin
                        tile_data[15:0]<=TEXTROM_DATA;
                        buf_we<=1'b1;
                        tx<=0;
                    end
                    10: begin
                        if(tx==7) st<=st+1;
                        else st<=st;

                        tx<=tx+1;
                        if(buf_code >= 0 && buf_code < 320) begin
                            if((((tile_data >> ((7-tx)*4)) & 8'h0F)) > 0) begin
                                    buf_addr<=FLIPX ? 319-buf_code : buf_code;
                                    buf_data<=tile_palette_pointer+(((tile_data >> ((7-tx)*4)) & 8'h0F));
                            end else begin
                                buf_addr<=FLIPX ? 319-buf_code : buf_code;
                                buf_data<=0;
                            end
                        end
                    end
                    11: begin
                        x<=x+1;
                        st<=4;
                    end
                endcase
            end else begin
                busy<=1'b0;
                start<=1'b0;
                st<=0;
                x<=0;
                tx<=0;
            end
        end else busy<=1'b0;
    end
end

endmodule
module raizing_extratext (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    output reg [10:0] EXTRATEXT_PIXEL,
    input FLIPX,


    output reg [13:0] TEXTROM_ADDR,
    input  [15:0] TEXTROM_DATA,


    output reg [11:0] TEXTVRAM_ADDR,
    input  [15:0] TEXTVRAM_DATA,


    output reg [7:0] TEXTSELECT_ADDR,
    input [15:0] TEXTSELECT_DATA,


    output reg [7:0] TEXTSCROLL_ADDR,
    input [15:0] TEXTSCROLL_DATA,

    input [7:0] GAME
);


localparam GAREGGA = 'h0, KINGDMGP = 'h2, SSTRIKER = 'h1;

reg [10:0] buf_data = 0;
reg [8:0] buf_addr = 0;
reg buf_we = 1'b0;
wire [10:0] pretext_pxl;

reg [15:0] line, offset, startx, tilerow_start, ptile, tile_data_pointer, tile_palette_pointer;
reg [31:0] tile_data;
reg [8:0] xpos;
reg [7:0] st = 0;

wire [5:0] extratoffs = GAME == SSTRIKER ? 6'h2B : 6'h2C;
wire [11:0] textpal_offs = 12'h800;

wire [5:0] tile_max=6'd41;

reg [8:0] x=0;

wire [8:0] buf_addr_out = H;

wire [10:0] rd_gated;

jtframe_linebuf #(.DW(11)) u_extratext_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(buf_data),
    .we(buf_we),
    .rd_addr(buf_addr_out),
    .rd_data(pretext_pxl),
    .rd_gated()
);

reg last_HB, start, last_start;
wire pedg_HB = !HB && last_HB;
reg busy = 1'b0;
wire [8:0] y = VRENDER;

reg [8:0] tx = 0;

wire signed [9:0] buf_code = (x<<3) - offset + tx;
always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
        st<=0;
        x<=0;

        start<=1'b0;
        busy<=1'b0;
        tx<=0;
        line<=0;
        offset<=0;
        startx<=0;
        tilerow_start<=0;
        ptile<=0;
        tile_data_pointer<=0;
        tile_palette_pointer<=0;
        tile_data<=0;
        xpos<=0;
        st <= 0;
        TEXTROM_ADDR<=0;
        TEXTVRAM_ADDR<=0;
        TEXTSELECT_ADDR<=0;
        TEXTSCROLL_ADDR<=0;
    end
    else begin

        if(PIXEL_CEN && ACTIVE) begin
            EXTRATEXT_PIXEL<=pretext_pxl;
        end

        last_HB    <= HB;

        if( (pedg_HB && !VB)  || (((!FLIPX && VRENDER == 0) || (FLIPX && VRENDER == 239)) && pedg_HB)) begin
            start <= 1'b1;
        end

        if(start && !busy) begin
            start<=1'b0;
            busy<=1'b1;
            tx<=0;
            line<=0;
            offset<=0;
            startx<=0;
            tilerow_start<=0;
            ptile<=0;
            tile_data_pointer<=0;
            tile_palette_pointer<=0;
            tile_data<=0;
            xpos<=0;
            st <= 0;
            TEXTROM_ADDR<=0;
            TEXTVRAM_ADDR<=0;
            TEXTSELECT_ADDR<=0;
            TEXTSCROLL_ADDR<=0;
            x<=0;
        end else if(busy) begin
            st<=st+1'b1;
            case(st)
                0: begin
                    TEXTSELECT_ADDR<=y[7:0];
                    TEXTSCROLL_ADDR<=y[7:0];
                end
                2: begin
                    line<=TEXTSELECT_DATA;
                    offset<=(TEXTSCROLL_DATA+extratoffs);
                    startx<=((TEXTSCROLL_DATA+extratoffs)>>3) & 8'h3F;
                    
                end
                3: begin
                    tilerow_start<=(line & (8'h1F<<3))<<3;
                    offset<=offset&7;
                end
            endcase
            if(x<tile_max) begin
                case(st)
                    4: begin
                        TEXTVRAM_ADDR<=(tilerow_start) + ((x+startx) & 8'h3F);
                    end
                    6: begin
                        tile_data_pointer<=(((TEXTVRAM_DATA & 12'h3FF) << 5) + ((line & 7) << 2))>>1;
                        tile_palette_pointer<=(textpal_offs+(((TEXTVRAM_DATA >> 6) & 16'h03F0)<<1))>>1;
                        TEXTROM_ADDR<=(((TEXTVRAM_DATA & 12'h3FF) << 5) + ((line & 7) << 2))>>1;
                    end
                    7: TEXTROM_ADDR<=tile_data_pointer+1;
                    8: begin
                        tile_data[31:16]<=TEXTROM_DATA;
                    end
                    9: begin
                        tile_data[15:0]<=TEXTROM_DATA;
                        buf_we<=1'b1;
                        tx<=0;
                    end
                    10: begin
                        if(tx==7) st<=st+1;
                        else st<=st;

                        tx<=tx+1;
                        if(buf_code >= 0 && buf_code < 320) begin
                            if((((tile_data >> ((7-tx)*4)) & 8'h0F)) > 0) begin
                                    buf_addr<=FLIPX ? 319-buf_code : buf_code;
                                    buf_data<=tile_palette_pointer+(((tile_data >> ((7-tx)*4)) & 8'h0F));
                            end else begin
                                buf_addr<=FLIPX ? 319-buf_code : buf_code;
                                buf_data<=0;
                            end
                        end
                    end
                    11: begin
                        x<=x+1;
                        st<=4;
                    end
                endcase
            end else begin
                busy<=1'b0;
                start<=1'b0;
                st<=0;
                x<=0;
                tx<=0;
            end
        end else busy<=1'b0;
    end
end

endmodule