data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100;    \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_fa_tb.v:29: Cannot find file containing module: \'el_fa_fl\'\nel_fa_fl DUT\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_fa_fl\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_fa_fl.v\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_fa_fl.sv\n             el_fa_fl\n             el_fa_fl.v\n             el_fa_fl.sv\n             obj_dir/el_fa_fl\n             obj_dir/el_fa_fl.v\n             obj_dir/el_fa_fl.sv\n%Error: Exiting due to 1 error(s), 33 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module el_fa_tb();

parameter						RAIL_NUM = 2;
parameter						IN_NUM = 3;
parameter						OUT_NUM = 2;

wire ack_a_o_tb;
wire ack_b_o_tb;
wire ack_c_o_tb;

reg ack_s_i_tb = 0;
reg ack_c_i_tb = 0;

reg [1:0] in_a_tb = 0;
reg [1:0] in_b_tb = 0;
reg [1:0] in_c_tb = 0;

wire [1:0] out_s_tb;
wire [1:0] out_c_tb;



reg rst_tb;


el_fa_fl DUT
(

	.rst(rst_tb),

	.ack_a_o(ack_a_o_tb),
	.in_a(in_a_tb),

	.ack_b_o(ack_b_o_tb),
	.in_b(in_b_tb),

	.ack_c_o(ack_c_o_tb),
	.in_c(in_c_tb),

	.ack_s_i(ack_s_i_tb),
	.out_s(out_s_tb),

	.ack_c_i(ack_c_i_tb),
	.out_c(out_c_tb)

);

initial
begin

    rst_tb = 1;
    #100;    
    rst_tb = 0;
    #1000;
	

	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[0] = !in_c_tb[0]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
	
	

    in_a_tb[1] = !in_a_tb[1];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[1] = !in_b_tb[1]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	

    in_a_tb[1] = !in_a_tb[1];
    #100;  

    in_b_tb[1] = !in_b_tb[1]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
    
    #1000;
    $finish;  
    
    
    
end

endmodule
module el_fa_tb();


parameter						RAIL_NUM = 2;
parameter						IN_NUM = 3;
parameter						OUT_NUM = 2;

wire ack_a_o_tb;
wire ack_b_o_tb;
wire ack_c_o_tb;

reg ack_s_i_tb = 0;
reg ack_c_i_tb = 0;

reg [1:0] in_a_tb = 0;
reg [1:0] in_b_tb = 0;
reg [1:0] in_c_tb = 0;

wire [1:0] out_s_tb;
wire [1:0] out_c_tb;



reg rst_tb;


el_fa_fl DUT
(

	.rst(rst_tb),

	.ack_a_o(ack_a_o_tb),
	.in_a(in_a_tb),

	.ack_b_o(ack_b_o_tb),
	.in_b(in_b_tb),

	.ack_c_o(ack_c_o_tb),
	.in_c(in_c_tb),

	.ack_s_i(ack_s_i_tb),
	.out_s(out_s_tb),

	.ack_c_i(ack_c_i_tb),
	.out_c(out_c_tb)

);

initial
begin

    rst_tb = 1;
    #100;    
    rst_tb = 0;
    #1000;
	

	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[0] = !in_c_tb[0]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
	
	

    in_a_tb[1] = !in_a_tb[1];
    #100;  

    in_b_tb[0] = !in_b_tb[0]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	

    in_a_tb[0] = !in_a_tb[0];
    #100;  

    in_b_tb[1] = !in_b_tb[1]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	

    in_a_tb[1] = !in_a_tb[1];
    #100;  

    in_b_tb[1] = !in_b_tb[1]; 
    #100;  

    in_c_tb[1] = !in_c_tb[1]; 
    #100;  
	

    #2000;
	ack_s_i_tb = !ack_s_i_tb;
	#100; 
	ack_c_i_tb = !ack_c_i_tb;
	#2000;
	
    
    #1000;
    $finish;  
    
    
    
end

endmodule