data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl/aq_f_spsram_64x88.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl/aq_f_spsram_64x88.v:91: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418750043/fpga_ram\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418750043/fpga_ram.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418750043/fpga_ram.sv\n             fpga_ram\n             fpga_ram.v\n             fpga_ram.sv\n             obj_dir/fpga_ram\n             obj_dir/fpga_ram.v\n             obj_dir/fpga_ram.sv\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/fpga/rtl/aq_f_spsram_64x88.v:98: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module aq_f_spsram_64x88(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);


input   [5 :0]  A;           
input           CEN;         
input           CLK;         
input   [87:0]  D;           
input           GWEN;        
input   [87:0]  WEN;         
output  [87:0]  Q;           


reg     [5 :0]  addr_holding; 


wire    [5 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [87:0]  D;           
wire            GWEN;        
wire    [87:0]  Q;           
wire    [87:0]  WEN;         
wire    [5 :0]  addr;        
wire    [43:0]  ram0_din;    
wire    [43:0]  ram0_dout;   
wire            ram0_wen;    
wire    [43:0]  ram1_din;    
wire    [43:0]  ram1_dout;   
wire            ram1_wen;    


parameter ADDR_WIDTH = 6;
parameter WRAP_SIZE  = 44;





assign ram0_wen = !CEN && !WEN[43] && !GWEN;
assign ram1_wen = !CEN && !WEN[87] && !GWEN;





assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram1_din[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];




assign Q[WRAP_SIZE-1:0]             = ram0_dout[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE]   = ram1_dout[WRAP_SIZE-1:0];


fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram1_din),
  .PortAWriteEnable(ram1_wen),
  .PortADataOut(ram1_dout));


endmodule
module aq_f_spsram_64x88(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);



input   [5 :0]  A;           
input           CEN;         
input           CLK;         
input   [87:0]  D;           
input           GWEN;        
input   [87:0]  WEN;         
output  [87:0]  Q;           


reg     [5 :0]  addr_holding; 


wire    [5 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [87:0]  D;           
wire            GWEN;        
wire    [87:0]  Q;           
wire    [87:0]  WEN;         
wire    [5 :0]  addr;        
wire    [43:0]  ram0_din;    
wire    [43:0]  ram0_dout;   
wire            ram0_wen;    
wire    [43:0]  ram1_din;    
wire    [43:0]  ram1_dout;   
wire            ram1_wen;    


parameter ADDR_WIDTH = 6;
parameter WRAP_SIZE  = 44;





assign ram0_wen = !CEN && !WEN[43] && !GWEN;
assign ram1_wen = !CEN && !WEN[87] && !GWEN;





assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram1_din[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];




assign Q[WRAP_SIZE-1:0]             = ram0_dout[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE]   = ram1_dout[WRAP_SIZE-1:0];


fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));

fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram1_din),
  .PortAWriteEnable(ram1_wen),
  .PortADataOut(ram1_dout));


endmodule