data/full_repos/permissive/514992586/1_Verilog_language/Basics/08_Xnorgate.v
data/verilator_xmls/31d2293a-14c9-4977-97cd-e0e19d424d27.xml
module top_module( 
    input a, 
    input b, 
    output out );
	assign out = a ~^ b;
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

	assign out = a ~^ b;
endmodule