data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_half_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_half_adder.v:60: Unsupported: Ignoring delay on this delayed statement.\n repeat (3) #10 D = D + 1\'b1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_half_adder.v:64: Unsupported or unknown PLI call: $monitor\n $monitor("xy = %b S = %b C = %b", D, S, C); \n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_half_adder ;
	reg [1:0] D;
	wire S, C;

half_adder DUT (S, C, D[1], D[0]);

initial begin
	D = 2'b00;
	repeat (3) #10 D = D + 1'b1;
end

initial
	$monitor("xy = %b S = %b C = %b", D, S, C); 

endmodule
module t_half_adder ;

	reg [1:0] D;
	wire S, C;

half_adder DUT (S, C, D[1], D[0]);

initial begin
	D = 2'b00;
	repeat (3) #10 D = D + 1'b1;
end

initial
	$monitor("xy = %b S = %b C = %b", D, S, C); 

endmodule