data/full_repos/permissive/493265923/03_INTEGRATOR_BACK/INTEGRATOR_BACK.v
data/verilator_xmls/0e5092f6-af55-402a-b23b-2938bfa5c53f.xml
module INTEGRATOR_BACK(
    CLK_I,
    DATA_I,
    DATA_O,
    OFDET_O,
    UFDET_O
);

    parameter DATA_Bit_Length = 32;



    input  wire CLK_I;
    input  wire signed [DATA_Bit_Length-1:0] DATA_I;

    output wire signed [DATA_Bit_Length-1:0] DATA_O;
    output wire                              UFDET_O;
    output wire                              OFDET_O;



    reg  signed [DATA_Bit_Length-1:0] DATA_REG_POS = {DATA_Bit_Length{1'b0}};
    reg  signed [DATA_Bit_Length-1:0] DATA_REG_NEG = {DATA_Bit_Length{1'b0}};

    wire signed [DATA_Bit_Length:0] SUM_DATA;
    

    assign SUM_DATA = DATA_I + DATA_REG_NEG;


    always @ (posedge CLK_I) begin
        DATA_REG_POS <= DATA_O;
    end

    always @ (negedge CLK_I) begin
        DATA_REG_NEG <= DATA_REG_POS;
    end


    assign {UFDET_O, OFDET_O, DATA_O} = assign_out(SUM_DATA);
    


    function [DATA_Bit_Length+1:0] assign_out;
        input [DATA_Bit_Length:0] SUM_DATA;
    begin
        case(SUM_DATA[DATA_Bit_Length:DATA_Bit_Length-1])
            2'b01:
                begin


                    assign_out = {1'b0, 1'b1, 1'b0, {(DATA_Bit_Length-1){1'b1}}};
                end

            2'b10:
                begin


                    assign_out = {1'b1, 1'b0, 1'b1, {(DATA_Bit_Length-1){1'b0}}};
                end

            default:
                begin

                    assign_out = {1'b0, 1'b0, SUM_DATA[DATA_Bit_Length], SUM_DATA[DATA_Bit_Length-2:0]};
                end
        endcase
    end
    endfunction

endmodule
module INTEGRATOR_BACK(
    CLK_I,
    DATA_I,
    DATA_O,
    OFDET_O,
    UFDET_O
);


    parameter DATA_Bit_Length = 32;



    input  wire CLK_I;
    input  wire signed [DATA_Bit_Length-1:0] DATA_I;

    output wire signed [DATA_Bit_Length-1:0] DATA_O;
    output wire                              UFDET_O;
    output wire                              OFDET_O;



    reg  signed [DATA_Bit_Length-1:0] DATA_REG_POS = {DATA_Bit_Length{1'b0}};
    reg  signed [DATA_Bit_Length-1:0] DATA_REG_NEG = {DATA_Bit_Length{1'b0}};

    wire signed [DATA_Bit_Length:0] SUM_DATA;
    

    assign SUM_DATA = DATA_I + DATA_REG_NEG;


    always @ (posedge CLK_I) begin
        DATA_REG_POS <= DATA_O;
    end

    always @ (negedge CLK_I) begin
        DATA_REG_NEG <= DATA_REG_POS;
    end


    assign {UFDET_O, OFDET_O, DATA_O} = assign_out(SUM_DATA);
    


    function [DATA_Bit_Length+1:0] assign_out;
        input [DATA_Bit_Length:0] SUM_DATA;
    begin
        case(SUM_DATA[DATA_Bit_Length:DATA_Bit_Length-1])
            2'b01:
                begin


                    assign_out = {1'b0, 1'b1, 1'b0, {(DATA_Bit_Length-1){1'b1}}};
                end

            2'b10:
                begin


                    assign_out = {1'b1, 1'b0, 1'b1, {(DATA_Bit_Length-1){1'b0}}};
                end

            default:
                begin

                    assign_out = {1'b0, 1'b0, SUM_DATA[DATA_Bit_Length], SUM_DATA[DATA_Bit_Length-2:0]};
                end
        endcase
    end
    endfunction

endmodule