data/full_repos/permissive/490649362/pipeline/src/Shift_Left_2.v
data/verilator_xmls/7e3a709d-784d-4590-bee1-dee66fbd1aa2.xml
module Shift_Left_2 (in, out);

    parameter input_size = 32, output_size = 32;

    input [input_size-1:0] in;
    output [output_size-1:0] out;

    wire [output_size-1:0] out;

    assign out = in * 4;

endmodule
module Shift_Left_2 (in, out);


    parameter input_size = 32, output_size = 32;

    input [input_size-1:0] in;
    output [output_size-1:0] out;

    wire [output_size-1:0] out;

    assign out = in * 4;

endmodule