data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/sbt/ExampleTopModuleWithBB.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/sbt/ExampleTopModuleWithBB.v:20: Cannot find file containing module: 'BB'\n  BB bb (  \n  ^~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/sbt,data/full_repos/permissive/493019833/BB\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/sbt,data/full_repos/permissive/493019833/BB.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/ExampleTopModuleWithBB/sbt,data/full_repos/permissive/493019833/BB.sv\n             BB\n             BB.v\n             BB.sv\n             obj_dir/BB\n             obj_dir/BB.v\n             obj_dir/BB.sv\n%Error: Exiting due to 1 error(s)\n"
module ExampleTopModuleWithBB(
  input         clock,
  input         reset,
  input  [14:0] io_a,
  input  [14:0] io_b,
  input  [13:0] io_c,
  output [15:0] io_x,
  output [15:0] io_y,
  output [15:0] io_z,
  inout  [2:0]  io_analog1,
  inout  [2:0]  io_analog2,
  output [4:0]  io_v_0,
  output [4:0]  io_v_1,
  output [4:0]  io_v_2
);
  wire [15:0] bb_z;
  wire [13:0] bb_c;
  wire [14:0] _T_25 = io_a + 15'h1;
  wire [14:0] _T_29 = io_b - 15'h1;
  BB bb (
    .analog2(io_analog2),
    .analog1(io_analog1),
    .z(bb_z),
    .c(bb_c)
  );
  assign io_x = {{1'd0}, _T_25};
  assign io_y = {{1'd0}, _T_29};
  assign io_z = bb_z;
  assign io_v_0 = io_a[4:0];
  assign io_v_1 = io_a[4:0];
  assign io_v_2 = io_a[4:0];
  assign bb_c = io_c;
endmodule
module ExampleTopModuleWithBB(
  input         clock,
  input         reset,
  input  [14:0] io_a,
  input  [14:0] io_b,
  input  [13:0] io_c,
  output [15:0] io_x,
  output [15:0] io_y,
  output [15:0] io_z,
  inout  [2:0]  io_analog1,
  inout  [2:0]  io_analog2,
  output [4:0]  io_v_0,
  output [4:0]  io_v_1,
  output [4:0]  io_v_2
);

  wire [15:0] bb_z;
  wire [13:0] bb_c;
  wire [14:0] _T_25 = io_a + 15'h1;
  wire [14:0] _T_29 = io_b - 15'h1;
  BB bb (
    .analog2(io_analog2),
    .analog1(io_analog1),
    .z(bb_z),
    .c(bb_c)
  );
  assign io_x = {{1'd0}, _T_25};
  assign io_y = {{1'd0}, _T_29};
  assign io_z = bb_z;
  assign io_v_0 = io_a[4:0];
  assign io_v_1 = io_a[4:0];
  assign io_v_2 = io_a[4:0];
  assign bb_c = io_c;
endmodule