data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn/counterdown16_4clk_posedge_async_resetn.v
1: b"%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn/counterdown16_4clk_posedge_async_resetn.v:14: Cannot find file containing module: 'counterdown16'\n counterdown16 u_cnt0(.clk(clock0), .reset(reset), .count(cnt0_16));\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn,data/full_repos/permissive/451270484/counterdown16\n             data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn,data/full_repos/permissive/451270484/counterdown16.v\n             data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn,data/full_repos/permissive/451270484/counterdown16.sv\n             counterdown16\n             counterdown16.v\n             counterdown16.sv\n             obj_dir/counterdown16\n             obj_dir/counterdown16.v\n             obj_dir/counterdown16.sv\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn/counterdown16_4clk_posedge_async_resetn.v:15: Cannot find file containing module: 'counterdown16'\n counterdown16 u_cnt1(.clk(clock1), .reset(reset), .count(cnt1_16));\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn/counterdown16_4clk_posedge_async_resetn.v:16: Cannot find file containing module: 'counterdown16'\n counterdown16 u_cnt2(.clk(clock2), .reset(reset), .count(cnt2_16));\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counterdown16_4clk_posedge_async_resetn/counterdown16_4clk_posedge_async_resetn.v:17: Cannot find file containing module: 'counterdown16'\n counterdown16 u_cnt3(.clk(clock3), .reset(reset), .count(cnt3_16));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module counterdown16_4clk_posedge_async_resetn (clock0, clock1, clock2, clock3, reset, cnt0_16, cnt1_16, cnt2_16, cnt3_16);
	input clock0, clock1, clock2, clock3;
	input reset;
	output [15:0] cnt0_16;
	output [15:0] cnt1_16;
	output [15:0] cnt2_16;
	output [15:0] cnt3_16;

	counterdown16 u_cnt0(.clk(clock0), .reset(reset), .count(cnt0_16));
	counterdown16 u_cnt1(.clk(clock1), .reset(reset), .count(cnt1_16));
	counterdown16 u_cnt2(.clk(clock2), .reset(reset), .count(cnt2_16));
	counterdown16 u_cnt3(.clk(clock3), .reset(reset), .count(cnt3_16));

endmodule
module counterdown16_4clk_posedge_async_resetn (clock0, clock1, clock2, clock3, reset, cnt0_16, cnt1_16, cnt2_16, cnt3_16);

	input clock0, clock1, clock2, clock3;
	input reset;
	output [15:0] cnt0_16;
	output [15:0] cnt1_16;
	output [15:0] cnt2_16;
	output [15:0] cnt3_16;

	counterdown16 u_cnt0(.clk(clock0), .reset(reset), .count(cnt0_16));
	counterdown16 u_cnt1(.clk(clock1), .reset(reset), .count(cnt1_16));
	counterdown16 u_cnt2(.clk(clock2), .reset(reset), .count(cnt2_16));
	counterdown16 u_cnt3(.clk(clock3), .reset(reset), .count(cnt3_16));

endmodule