data/full_repos/permissive/488093047/Verilog Codes/TB_Mux_2x1.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_Mux_2x1.v\n%Error: Exiting due to 3 error(s)\n'
module TB_Mux_2x1();
parameter N=32;
reg [N-1:0]A,B;
wire [N-1:0]C;
reg s;
Mux_2x1 #(.N(N)) DUT(.a(A),.b(B),.s(s),.y(C));
initial begin
A=32'd312;B=32'd521;s=1'b0;
#10 A=32'd312;B=32'd521;s=1'b1;


end


endmodule
module TB_Mux_2x1();

parameter N=32;
reg [N-1:0]A,B;
wire [N-1:0]C;
reg s;
Mux_2x1 #(.N(N)) DUT(.a(A),.b(B),.s(s),.y(C));
initial begin
A=32'd312;B=32'd521;s=1'b0;
#10 A=32'd312;B=32'd521;s=1'b1;


end


endmodule