data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v
1: b'%Error: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:2: Cannot find include file: saed32nm_hvt.v\n`include "saed32nm_hvt.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516245365/VSDBabySoC/src/module1,data/full_repos/permissive/516245365/saed32nm_hvt.v\n             data/full_repos/permissive/516245365/VSDBabySoC/src/module1,data/full_repos/permissive/516245365/saed32nm_hvt.v.v\n             data/full_repos/permissive/516245365/VSDBabySoC/src/module1,data/full_repos/permissive/516245365/saed32nm_hvt.v.sv\n             saed32nm_hvt.v\n             saed32nm_hvt.v.v\n             saed32nm_hvt.v.sv\n             obj_dir/saed32nm_hvt.v\n             obj_dir/saed32nm_hvt.v.v\n             obj_dir/saed32nm_hvt.v.sv\n%Error: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:3: Cannot find include file: avsddac.v\n`include "avsddac.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:4: Cannot find include file: avsdpll.v\n`include "avsdpll.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:27: syntax error, unexpected real, expecting IDENTIFIER or \'=\' or do or final\n   reg  real VREFL;\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #20 reset = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #100 reset = 0;\n      ^\n%Error: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:59: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, vsdbabysoc_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n         #100 REF = ~REF;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/516245365/VSDBabySoC/src/module1/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n         #(83.33/2) VCO_IN = ~VCO_IN;\n         ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module vsdbabysoc_tb;
   reg       reset;
   reg       VCO_IN;
   reg       ENb_CP;
   reg       ENb_VCO;
   reg       REF;
   reg  real VREFL;
   reg  real VREFH;
   wire real OUT;

   vsdbabysoc uut (
      .OUT(OUT),
      .reset(reset),
      .VCO_IN(VCO_IN),
      .ENb_CP(ENb_CP),
      .ENb_VCO(ENb_VCO),
      .REF(REF),

      .VREFH(VREFH)
   );

   initial begin
      reset = 0;
      VREFL = 0.0;
      VREFH = 3.3;
      {REF, ENb_VCO} = 0;
      VCO_IN = 1'b0 ;
      
      #20 reset = 1;
      #100 reset = 0;
   end
   
   initial begin
`ifdef PRE_SYNTH_SIM
      $dumpfile("pre_synth_sim.vcd");
`elsif POST_SYNTH_SIM
      $dumpfile("post_synth_sim.vcd");
`endif
      $dumpvars(0, vsdbabysoc_tb);
   end
 
   initial begin
      repeat(600) begin
         ENb_VCO = 1;
         #100 REF = ~REF;
         #(83.33/2) VCO_IN = ~VCO_IN;
      end
      $finish;
   end
   
endmodule
module vsdbabysoc_tb;

   reg       reset;
   reg       VCO_IN;
   reg       ENb_CP;
   reg       ENb_VCO;
   reg       REF;
   reg  real VREFL;
   reg  real VREFH;
   wire real OUT;

   vsdbabysoc uut (
      .OUT(OUT),
      .reset(reset),
      .VCO_IN(VCO_IN),
      .ENb_CP(ENb_CP),
      .ENb_VCO(ENb_VCO),
      .REF(REF),

      .VREFH(VREFH)
   );

   initial begin
      reset = 0;
      VREFL = 0.0;
      VREFH = 3.3;
      {REF, ENb_VCO} = 0;
      VCO_IN = 1'b0 ;
      
      #20 reset = 1;
      #100 reset = 0;
   end
   
   initial begin
`ifdef PRE_SYNTH_SIM
      $dumpfile("pre_synth_sim.vcd");
`elsif POST_SYNTH_SIM
      $dumpfile("post_synth_sim.vcd");
`endif
      $dumpvars(0, vsdbabysoc_tb);
   end
 
   initial begin
      repeat(600) begin
         ENb_VCO = 1;
         #100 REF = ~REF;
         #(83.33/2) VCO_IN = ~VCO_IN;
      end
      $finish;
   end
   
endmodule