data/full_repos/permissive/464367715/Design Sources/d_ff.v
1: b'%Error: Cannot find file containing module: Sources,data/full_repos/permissive/464367715\n        ... Looked in:\n             data/full_repos/permissive/464367715/Design/Sources,data/full_repos/permissive/464367715\n             data/full_repos/permissive/464367715/Design/Sources,data/full_repos/permissive/464367715.v\n             data/full_repos/permissive/464367715/Design/Sources,data/full_repos/permissive/464367715.sv\n             Sources,data/full_repos/permissive/464367715\n             Sources,data/full_repos/permissive/464367715.v\n             Sources,data/full_repos/permissive/464367715.sv\n             obj_dir/Sources,data/full_repos/permissive/464367715\n             obj_dir/Sources,data/full_repos/permissive/464367715.v\n             obj_dir/Sources,data/full_repos/permissive/464367715.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/464367715/Design\n%Error: Cannot find file containing module: Sources/d_ff.v\n%Error: Exiting due to 3 error(s)\n'
module d_latch(
input D ,
input C ,
output Q
) ;

wire R , S , Qn ;
wire R_g , S_g;

assign S = D ;
assign R = ~ D ;
and ( R_g , R , C ) ;
and ( S_g , S , C ) ;
nor (Q , R_g , Qn ) ;
nor ( Qn , S_g , Q ) ;
endmodule
module d_latch(
input D ,
input C ,
output Q
) ;


wire R , S , Qn ;
wire R_g , S_g;

assign S = D ;
assign R = ~ D ;
and ( R_g , R , C ) ;
and ( S_g , S , C ) ;
nor (Q , R_g , Qn ) ;
nor ( Qn , S_g , Q ) ;
endmodule