data/full_repos/permissive/461141714/src/Pipelined CPU supporting DMA/dma_controller.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: supporting\n%Error: Cannot find file containing module: DMA,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: DMA/dma_controller.v\n%Error: Exiting due to 5 error(s)\n'
module DMA_MANAGER(
        input clk,
        input reset_n,
        input if_memoryWait,
        input mem_memoryWait,
        input dma_begin,
        output reg [`WORD_SIZE-1:0] dma_command,
        input bus_request,
        output reg dma_using,
        output reg bus_grant,
        input dma_end
    );
    
    reg [1:0] state;
    initial dma_command = `WORD_SIZE'bz;
    
    always @(posedge clk) begin
        if(reset_n == 0) begin
            state = `WAIT_DMA_BEGIN;
            dma_command = `WORD_SIZE'bz;
            dma_using = 0;
            bus_grant = 0;
        end
        else begin
            case(state)
                `WAIT_DMA_BEGIN: begin
                    if(dma_begin == 1) begin
                        state = `WAIT_BUS_REQUEST_START;
                        dma_command = `DMA_ADDRESS;
                    end
                end
                `WAIT_BUS_REQUEST_START: begin
                    if(bus_request == 1 && if_memoryWait == 0 && mem_memoryWait == 0) begin
                        state = `WAIT_BUS_REQUEST_END;
                        dma_command = `WORD_SIZE'bz;
                        dma_using = 1;
                    end
                end
                `WAIT_BUS_REQUEST_END: begin
                    bus_grant = 1;
                    if(bus_request == 0) begin
                        state = `WAIT_DMA_END;
                        bus_grant = 0;
                    end
                end
                `WAIT_DMA_END: begin
                    if(dma_end) begin
                        state = `WAIT_DMA_BEGIN;
                        dma_command = `WORD_SIZE'bz;
                        dma_using = 0;
                        bus_grant = 0;
                    end
                end
            endcase
        end
    end
endmodule
module DMA_MANAGER(
        input clk,
        input reset_n,
        input if_memoryWait,
        input mem_memoryWait,
        input dma_begin,
        output reg [`WORD_SIZE-1:0] dma_command,
        input bus_request,
        output reg dma_using,
        output reg bus_grant,
        input dma_end
    );

    
    reg [1:0] state;
    initial dma_command = `WORD_SIZE'bz;
    
    always @(posedge clk) begin
        if(reset_n == 0) begin
            state = `WAIT_DMA_BEGIN;
            dma_command = `WORD_SIZE'bz;
            dma_using = 0;
            bus_grant = 0;
        end
        else begin
            case(state)
                `WAIT_DMA_BEGIN: begin
                    if(dma_begin == 1) begin
                        state = `WAIT_BUS_REQUEST_START;
                        dma_command = `DMA_ADDRESS;
                    end
                end
                `WAIT_BUS_REQUEST_START: begin
                    if(bus_request == 1 && if_memoryWait == 0 && mem_memoryWait == 0) begin
                        state = `WAIT_BUS_REQUEST_END;
                        dma_command = `WORD_SIZE'bz;
                        dma_using = 1;
                    end
                end
                `WAIT_BUS_REQUEST_END: begin
                    bus_grant = 1;
                    if(bus_request == 0) begin
                        state = `WAIT_DMA_END;
                        bus_grant = 0;
                    end
                end
                `WAIT_DMA_END: begin
                    if(dma_end) begin
                        state = `WAIT_DMA_BEGIN;
                        dma_command = `WORD_SIZE'bz;
                        dma_using = 0;
                        bus_grant = 0;
                    end
                end
            endcase
        end
    end
endmodule