data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:17: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl,data/full_repos/permissive/509468557/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:93: Define or directive not defined: \'`ASSERT\'\n    `ASSERT(SyncReqAckDataHoldSrc2Dst, !$stable(data_i) |->\n    ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:93: syntax error, unexpected \'(\'\n    `ASSERT(SyncReqAckDataHoldSrc2Dst, !$stable(data_i) |->\n            ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:93: Unsupported or unknown PLI call: $stable\n    `ASSERT(SyncReqAckDataHoldSrc2Dst, !$stable(data_i) |->\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:98: Define or directive not defined: \'`ASSERT_INIT\'\n    `ASSERT_INIT(SyncReqAckDataReg, DataSrc2Dst && !DataReg)\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:105: Define or directive not defined: \'`ASSERT\'\n    `ASSERT(SyncReqAckDataHoldDst2Src,\n    ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv:106: Unsupported or unknown PLI call: $stable\n        src_req_i && src_ack_o |-> $past(data_o,2) == data_o && $stable(data_o) [*2],\n                                                                ^~~~~~~\n%Error: Cannot continue\n'
module prim_sync_reqack_data #(
  parameter int unsigned Width       = 1,
  parameter bit          DataSrc2Dst = 1'b1,

  parameter bit          DataReg     = 1'b0

) (
  input  clk_src_i,
  input  rst_src_ni,
  input  clk_dst_i,
  input  rst_dst_ni,

  input  logic req_chk_i,

  input  logic src_req_i,
  output logic src_ack_o,
  output logic dst_req_o,
  input  logic dst_ack_i,

  input  logic [Width-1:0] data_i,
  output logic [Width-1:0] data_o
);




  prim_sync_reqack u_prim_sync_reqack (
    .clk_src_i,
    .rst_src_ni,
    .clk_dst_i,
    .rst_dst_ni,

    .req_chk_i,

    .src_req_i,
    .src_ack_o,
    .dst_req_o,
    .dst_ack_i
  );









  if (DataSrc2Dst == 1'b0 && DataReg == 1'b1) begin : gen_data_reg
    logic             data_we;
    logic [Width-1:0] data_d, data_q;


    assign data_we = dst_req_o & dst_ack_i;
    assign data_d  = data_i;
    always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
      if (!rst_dst_ni) begin
        data_q <= '0;
      end else if (data_we) begin
        data_q <= data_d;
      end
    end
    assign data_o = data_q;

  end else begin : gen_no_data_reg

    assign data_o = data_i;
  end




  if (DataSrc2Dst == 1'b1) begin : gen_assert_data_src2dst

    `ASSERT(SyncReqAckDataHoldSrc2Dst, !$stable(data_i) |->
        (!src_req_i || (src_req_i && src_ack_o)),
        clk_src_i, !rst_src_ni)


    `ASSERT_INIT(SyncReqAckDataReg, DataSrc2Dst && !DataReg)

  end else if (DataSrc2Dst == 1'b0 && DataReg == 1'b0) begin : gen_assert_data_dst2src




    `ASSERT(SyncReqAckDataHoldDst2Src,
        src_req_i && src_ack_o |-> $past(data_o,2) == data_o && $stable(data_o) [*2],
        clk_src_i, !rst_src_ni)
  end

endmodule
module prim_sync_reqack_data #(
  parameter int unsigned Width       = 1,
  parameter bit          DataSrc2Dst = 1'b1,

  parameter bit          DataReg     = 1'b0

) (
  input  clk_src_i,
  input  rst_src_ni,
  input  clk_dst_i,
  input  rst_dst_ni,

  input  logic req_chk_i,

  input  logic src_req_i,
  output logic src_ack_o,
  output logic dst_req_o,
  input  logic dst_ack_i,

  input  logic [Width-1:0] data_i,
  output logic [Width-1:0] data_o
);





  prim_sync_reqack u_prim_sync_reqack (
    .clk_src_i,
    .rst_src_ni,
    .clk_dst_i,
    .rst_dst_ni,

    .req_chk_i,

    .src_req_i,
    .src_ack_o,
    .dst_req_o,
    .dst_ack_i
  );









  if (DataSrc2Dst == 1'b0 && DataReg == 1'b1) begin : gen_data_reg
    logic             data_we;
    logic [Width-1:0] data_d, data_q;


    assign data_we = dst_req_o & dst_ack_i;
    assign data_d  = data_i;
    always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
      if (!rst_dst_ni) begin
        data_q <= '0;
      end else if (data_we) begin
        data_q <= data_d;
      end
    end
    assign data_o = data_q;

  end else begin : gen_no_data_reg

    assign data_o = data_i;
  end




  if (DataSrc2Dst == 1'b1) begin : gen_assert_data_src2dst

    `ASSERT(SyncReqAckDataHoldSrc2Dst, !$stable(data_i) |->
        (!src_req_i || (src_req_i && src_ack_o)),
        clk_src_i, !rst_src_ni)


    `ASSERT_INIT(SyncReqAckDataReg, DataSrc2Dst && !DataReg)

  end else if (DataSrc2Dst == 1'b0 && DataReg == 1'b0) begin : gen_assert_data_dst2src




    `ASSERT(SyncReqAckDataHoldDst2Src,
        src_req_i && src_ack_o |-> $past(data_o,2) == data_o && $stable(data_o) [*2],
        clk_src_i, !rst_src_ni)
  end

endmodule