data/full_repos/permissive/52703097/subtractor.test.v
1: b'%Error: data/full_repos/permissive/52703097/subtractor.test.v:1: Cannot find include file: adder.v\n`include "adder.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/adder.v.sv\n             adder.v\n             adder.v.v\n             adder.v.sv\n             obj_dir/adder.v\n             obj_dir/adder.v.v\n             obj_dir/adder.v.sv\n%Error: data/full_repos/permissive/52703097/subtractor.test.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/52703097/subtractor.test.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/subtractor.test.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk_reg <= ~clk_reg;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/52703097/subtractor.test.v:39: Unsupported or unknown PLI call: $strobe\n            $strobe("Strobe Incorrect Result! %d - %d = %d, correct = %d", a, b, result, corr_res);\n            ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/subtractor.test.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #1 corr_res <= a-b;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/subtractor.test.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #10 $finish;\n            ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module test;

    reg [31:0] a, b, corr_res;
    reg cin;
    
    wire [31:0] result;
    wire cout;

    integer i;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        cin = 1;
        i = 0;
    end

    adder uut(
        .i_a(a),
        .i_b(~b),
        .i_cin(cin),
        .o_result(result),
        .o_cout(cout)
    );
   
    wire clk;
    reg clk_reg = 1'b0;
    assign clk = clk_reg;

    always #5 clk_reg <= ~clk_reg;

    always @(negedge clk_reg) begin
        if (corr_res != result)
            $strobe("Strobe Incorrect Result! %d - %d = %d, correct = %d", a, b, result, corr_res);
    end
    
    always @(posedge clk_reg) begin
        a <= $random;
        b <= $random;
        #1 corr_res <= a-b;
        
        i = i + 1;
        if (i >= `TESTS)
            #10 $finish;
    end
endmodule
module test;


    reg [31:0] a, b, corr_res;
    reg cin;
    
    wire [31:0] result;
    wire cout;

    integer i;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        cin = 1;
        i = 0;
    end

    adder uut(
        .i_a(a),
        .i_b(~b),
        .i_cin(cin),
        .o_result(result),
        .o_cout(cout)
    );
   
    wire clk;
    reg clk_reg = 1'b0;
    assign clk = clk_reg;

    always #5 clk_reg <= ~clk_reg;

    always @(negedge clk_reg) begin
        if (corr_res != result)
            $strobe("Strobe Incorrect Result! %d - %d = %d, correct = %d", a, b, result, corr_res);
    end
    
    always @(posedge clk_reg) begin
        a <= $random;
        b <= $random;
        #1 corr_res <= a-b;
        
        i = i + 1;
        if (i >= `TESTS)
            #10 $finish;
    end
endmodule