data/full_repos/permissive/491573622/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/491573622/alu.v:60: Operator SHIFTR expects 65 bits on the LHS, but LHS\'s REPLICATE generates 64 bits.\n                                                             : ... In instance alu\n                    temp = shiftsel ? {{32{b[31]}}, b} >> a[4:0] : {{32{b[31]}}, b} >> shift;\n                                                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/491573622/alu.v:60: Operator SHIFTR expects 65 bits on the LHS, but LHS\'s REPLICATE generates 64 bits.\n                                                             : ... In instance alu\n                    temp = shiftsel ? {{32{b[31]}}, b} >> a[4:0] : {{32{b[31]}}, b} >> shift;\n                                                                                    ^~\n%Warning-UNSIGNED: data/full_repos/permissive/491573622/alu.v:67: Comparison is constant due to unsigned arithmetic\n                                                                : ... In instance alu\n        negative = (result < 0) ? 1 : 0;\n                           ^\n%Error: Exiting due to 3 warning(s)\n'
module alu(
    input [31:0] a,
    input [31:0] b,
    input [3:0] alu_ctr,
    input [4:0] shift,
    input shiftsel,
    output reg [31:0] result,
    output reg zero,
    output reg negative
    );
    parameter alu_add = 4'b0000,
              alu_sub = 4'b0001,
              alu_or = 4'b0010,
              alu_neg = 4'b0011,
              alu_and = 4'b0100,
              alu_xor = 4'b0101,
              alu_nor = 4'b0110,
              alu_sl = 4'b0111,
              alu_sr = 4'b1000,
              alu_sra = 4'b1001,
              alu_da = 4'b1010,
              alu_db = 4'b1011;
    reg [64:0] temp;
    always@(*)
    begin
        case(alu_ctr)
            alu_add: result = a + b;
            alu_sub: result = a - b;
            alu_or: result = a | b;
            alu_neg: result = (a < b) ? 1 : 0;
            alu_and: result = a & b;
            alu_xor: result = a ^ b;
            alu_nor: result = ~(a | b);
            alu_sl: result = shiftsel ? b << a[4:0] : b << shift;
            alu_sr: result = shiftsel ? b >> a[4:0] : b >> shift;
            alu_sra:
                begin
                    temp = shiftsel ? {{32{b[31]}}, b} >> a[4:0] : {{32{b[31]}}, b} >> shift;
                    result = temp[31:0];
                end
            alu_da: result = a;
            alu_db: result = b;
        endcase
        zero = (result == 0) ? 1 : 0;
        negative = (result < 0) ? 1 : 0;
    end
endmodule
module alu(
    input [31:0] a,
    input [31:0] b,
    input [3:0] alu_ctr,
    input [4:0] shift,
    input shiftsel,
    output reg [31:0] result,
    output reg zero,
    output reg negative
    );

    parameter alu_add = 4'b0000,
              alu_sub = 4'b0001,
              alu_or = 4'b0010,
              alu_neg = 4'b0011,
              alu_and = 4'b0100,
              alu_xor = 4'b0101,
              alu_nor = 4'b0110,
              alu_sl = 4'b0111,
              alu_sr = 4'b1000,
              alu_sra = 4'b1001,
              alu_da = 4'b1010,
              alu_db = 4'b1011;
    reg [64:0] temp;
    always@(*)
    begin
        case(alu_ctr)
            alu_add: result = a + b;
            alu_sub: result = a - b;
            alu_or: result = a | b;
            alu_neg: result = (a < b) ? 1 : 0;
            alu_and: result = a & b;
            alu_xor: result = a ^ b;
            alu_nor: result = ~(a | b);
            alu_sl: result = shiftsel ? b << a[4:0] : b << shift;
            alu_sr: result = shiftsel ? b >> a[4:0] : b >> shift;
            alu_sra:
                begin
                    temp = shiftsel ? {{32{b[31]}}, b} >> a[4:0] : {{32{b[31]}}, b} >> shift;
                    result = temp[31:0];
                end
            alu_da: result = a;
            alu_db: result = b;
        endcase
        zero = (result == 0) ? 1 : 0;
        negative = (result < 0) ? 1 : 0;
    end
endmodule