data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'in'\n                                                                                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire in, rst, nrst, out, s0, s1, s2;\n     ^~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                      ^~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'rst'\nwire in, rst, nrst, out, s0, s1, s2;\n         ^~~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                          ^~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'out'\nwire in, rst, nrst, out, s0, s1, s2;\n                    ^~~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                                      ^~~\n%Error: Exiting due to 3 error(s)\n"
module user_module_340067262721426004(
  input [7:0] io_in, 
  output [7:0] io_out
);

  wire out;

  assign io_out[0] = out;

  div3_340067262721426004 div3_core(
    .rst(io_in[1]),
    .in(io_in[0]),
    .out(out)
  );

endmodule
module user_module_340067262721426004(
  input [7:0] io_in, 
  output [7:0] io_out
);


  wire out;

  assign io_out[0] = out;

  div3_340067262721426004 div3_core(
    .rst(io_in[1]),
    .in(io_in[0]),
    .out(out)
  );

endmodule