data/full_repos/permissive/512077043/all_tb/all_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n                        #T1H_min\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n                        #T1L_min\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n                        #T0H_max\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n                        #T0L_min\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n                #RGB_rst  \n                ^\n%Error: data/full_repos/permissive/512077043/all_tb/all_tb.v:230: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("all_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/512077043/all_tb/all_tb.v:231: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, all_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/512077043/all_tb/all_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n        #(DURATION)\n        ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module all_tb();


    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;



    

    localparam RGBW_T0H = 16;
    localparam RGBW_T0L = 74;
    localparam RGBW_T1H = 45;
    localparam RGBW_T1L = 45;
    localparam RGBW_STR_RST = 7681;
    localparam SOTP_COUNTER_MAX = 7800;

    localparam SINP_COUNTER_MAX = 5000;
    localparam STREAM_RESET_CLKS = 4800;
    localparam SAMPLE_TIME_CLKS   = 57;



    localparam T0H_min = 48;
    localparam T0H_max = 105;
    localparam T1H_min = 124;
    localparam T1H_max = 182;
    localparam T1L_min = 57;
    localparam T1L_max = 115;
    localparam T0L_min = 134;
    localparam T0L_max = 192;
    localparam RGB_rst = 9600;



    wire                    r_en;
    wire    [DATA_SIZE-1:0] r_data;
    wire                    r_empty;
    wire                    w_full;
    wire                    w_en;
    wire    [DATA_SIZE-1:0] w_data;
    wire                    s2wd_wr_fifo_overflow;


    reg                     si_clk = 1'b0;
    reg                     si_rst = 1'b0;
    reg                     si_inp_serial = 1'b0;
    wire                    si_2_s2wd_strobe;
    wire                    si_2_s2wd_stream_reset;
    wire                    si_2_s2wd_value;
    

    reg                     s2wd_clk = 1'b0;
    reg                     s2wd_rst = 1'b0;


    reg                     r_clk = 1'b0;
    reg                     r_rst = 1'b0;
    reg                     w_clk = 1'b0;
    reg                     w_rst = 1'b0;


    reg                     so_clk = 1'b0;
    reg                     so_rst = 1'b0;
    wire                    so_out_serial;


    reg                     bit_first  = 1'b1;
    reg  [5:0]              where_am_i = 6'd0;
    reg [31:0]              file_data = 32'd0;
        $finish;
    end

endmodule
module all_tb();



    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;



    

    localparam RGBW_T0H = 16;
    localparam RGBW_T0L = 74;
    localparam RGBW_T1H = 45;
    localparam RGBW_T1L = 45;
    localparam RGBW_STR_RST = 7681;
    localparam SOTP_COUNTER_MAX = 7800;

    localparam SINP_COUNTER_MAX = 5000;
    localparam STREAM_RESET_CLKS = 4800;
    localparam SAMPLE_TIME_CLKS   = 57;



    localparam T0H_min = 48;
    localparam T0H_max = 105;
    localparam T1H_min = 124;
    localparam T1H_max = 182;
    localparam T1L_min = 57;
    localparam T1L_max = 115;
    localparam T0L_min = 134;
    localparam T0L_max = 192;
    localparam RGB_rst = 9600;



    wire                    r_en;
    wire    [DATA_SIZE-1:0] r_data;
    wire                    r_empty;
    wire                    w_full;
    wire                    w_en;
    wire    [DATA_SIZE-1:0] w_data;
    wire                    s2wd_wr_fifo_overflow;


    reg                     si_clk = 1'b0;
    reg                     si_rst = 1'b0;
    reg                     si_inp_serial = 1'b0;
    wire                    si_2_s2wd_strobe;
    wire                    si_2_s2wd_stream_reset;
    wire                    si_2_s2wd_value;
    

    reg                     s2wd_clk = 1'b0;
    reg                     s2wd_rst = 1'b0;


    reg                     r_clk = 1'b0;
    reg                     r_rst = 1'b0;
    reg                     w_clk = 1'b0;
    reg                     w_rst = 1'b0;


    reg                     so_clk = 1'b0;
    reg                     so_rst = 1'b0;
    wire                    so_out_serial;


    reg                     bit_first  = 1'b1;
    reg  [5:0]              where_am_i = 6'd0;
    reg [31:0]              file_data = 32'd0;
        $finish;
    end

endmodule