data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                         : ... In instance OpShift.u_pad_10\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                         : ... In instance OpShift.s_pad_9\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: [7:8] Range extract has backward bit ordering, perhaps you wanted [8:7]\n                                                                                                 : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Selection index out of range: 9:8 outside 7:0\n                                                                                                            : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                         : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                         : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: [7:8] Range extract has backward bit ordering, perhaps you wanted [8:7]\n                                                                                                : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Selection index out of range: 9:8 outside 7:0\n                                                                                                           : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                        : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                        : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n             ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module SHL_SIGNED(y, in);
    parameter width = 4;
    parameter n = 4;
    output [width+n-1:0] y;
    input [width-1:0] in;
    wire [width+n-1:0] temp;
    assign temp = {{n{in[width-1]}}, in};
    assign y = $signed(temp) << n;
endmodule
module SHL_SIGNED(y, in);

    parameter width = 4;
    parameter n = 4;
    output [width+n-1:0] y;
    input [width-1:0] in;
    wire [width+n-1:0] temp;
    assign temp = {{n{in[width-1]}}, in};
    assign y = $signed(temp) << n;
endmodule