data/full_repos/permissive/51625123/src/analinput.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51625123/src/analinput.v:73: Operator FUNCREF \'paddlelimiter\' expects 10 bits on the Function Argument, but Function Argument\'s SEL generates 9 bits.\n                                                                      : ... In instance analinput\n    pay <= paddlelimiter(datain[11:3]);\n           ^~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/analinput.v:75: Operator FUNCREF \'paddlelimiter\' expects 10 bits on the Function Argument, but Function Argument\'s SEL generates 9 bits.\n                                                                      : ... In instance analinput\n    pby <= paddlelimiter(datain[11:3]);\n           ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/analinput.v:86: Operator OR expects 12 bits on the RHS, but RHS\'s VARREF \'miso\' generates 1 bits.\n                                                                      : ... In instance analinput\n  datain <= (datain << 1) | miso; \n                          ^\n%Warning-UNSIGNED: data/full_repos/permissive/51625123/src/analinput.v:98: Comparison is constant due to unsigned arithmetic\n                                                                         : ... In instance analinput\n if (py < PADDLESIZE/2) \n        ^\n%Error: Exiting due to 4 warning(s)\n'
module analinput(clk, pay, pby, miso, mosi, cs, sck);
parameter PADDLESIZE = 0;
parameter SCREENHEIGHT = 0;
input clk;
output reg[9:0] pay;
output reg[9:0] pby;
input miso;
output reg mosi;
output reg cs;
output sck;

parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3;

reg [1:0] state;

reg [4:0] sckcount;
reg [11:0] datain;

reg ab;

assign sck = clk;

always @(posedge sck) begin
	case(state)
	state0:
		begin
			ab <= 1;
			state <= state1;
		end
	state1: 
		begin
			ab <= !ab;
			cs <= 0;
			mosi <= !ab;
			sckcount <= 15;
			state <= state2;
		end
	state2:
		begin
			if (sckcount != 0) 
				sckcount <= sckcount - 1'b1;
			else 
				state <= state3;
		end
	state3:
		begin
			cs <= 1;
			mosi <= 0;
			if (ab == 0) begin
				pay <= paddlelimiter(datain[11:3]);
			end else begin
				pby <= paddlelimiter(datain[11:3]);
			end
			state <= state1;
		end
	default:
		state <= state0;
	endcase
end

always @(negedge sck) begin
	if (state == state2)
		datain <= (datain << 1) | miso; 
	else if (state == state1)
		datain <= 0;
end





function [9:0] paddlelimiter;
input [9:0] py;
begin
	if (py < PADDLESIZE/2) 
		paddlelimiter = PADDLESIZE/2;
	else 
	if (py > SCREENHEIGHT-96/2)
		paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
	else
		paddlelimiter = py;
end
endfunction


endmodule
module analinput(clk, pay, pby, miso, mosi, cs, sck);

parameter PADDLESIZE = 0;
parameter SCREENHEIGHT = 0;
input clk;
output reg[9:0] pay;
output reg[9:0] pby;
input miso;
output reg mosi;
output reg cs;
output sck;

parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3;

reg [1:0] state;

reg [4:0] sckcount;
reg [11:0] datain;

reg ab;

assign sck = clk;

always @(posedge sck) begin
	case(state)
	state0:
		begin
			ab <= 1;
			state <= state1;
		end
	state1: 
		begin
			ab <= !ab;
			cs <= 0;
			mosi <= !ab;
			sckcount <= 15;
			state <= state2;
		end
	state2:
		begin
			if (sckcount != 0) 
				sckcount <= sckcount - 1'b1;
			else 
				state <= state3;
		end
	state3:
		begin
			cs <= 1;
			mosi <= 0;
			if (ab == 0) begin
				pay <= paddlelimiter(datain[11:3]);
			end else begin
				pby <= paddlelimiter(datain[11:3]);
			end
			state <= state1;
		end
	default:
		state <= state0;
	endcase
end

always @(negedge sck) begin
	if (state == state2)
		datain <= (datain << 1) | miso; 
	else if (state == state1)
		datain <= 0;
end





function [9:0] paddlelimiter;
input [9:0] py;
begin
	if (py < PADDLESIZE/2) 
		paddlelimiter = PADDLESIZE/2;
	else 
	if (py > SCREENHEIGHT-96/2)
		paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
	else
		paddlelimiter = py;
end
endfunction


endmodule