data/full_repos/permissive/406635962/src/general/sim_ram.v
data/verilator_xmls/a6459cfe-ab37-4e6a-8654-f125c679a9a7.xml
module sim_ram#(
    parameter DP = 512,
    parameter DW = 32,
    parameter MW= 4,
    parameter AW = 32,
    parameter FORCE_X2ZERO = 0,
    parameter ITCM = 0,
    parameter DTCM = 0
) (
    input  clk,
    input[DW-1:0] din,
    input[AW-1:0] addr,
    input we,
    input[MW-1:0] wem,
    output[DW-1:0] dout
);
    reg [DW-1:0] mem_r[0:DP-1];
    reg [AW-1:0] addr_r;
    wire [MW-1:0] wen;
    wire ren;
    wire [DW-1:0] dout_pre;
    integer j;

    assign ren = ~we;
    assign wen = ({MW{we}} & wem);


    always @(posedge clk ) begin
        if(ren) begin
            addr_r <= addr;
        end
    end
  
    genvar i;
    generate 
        for(i = 0; i<MW; i = i + 1) begin: simramloop
            if((8*i+8) > DW) begin: lastbyte
                always @(posedge clk) begin
                    if (wen[i]) begin: maskenabled
                        mem_r[addr][DW-1:8*i] <= din[DW-1:8*i];
                    end
                end
            end
            else begin: nonlastbytes
                always @(posedge clk) begin
                    if (wen[i]) begin: maskdisabeled
                        mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
                    end
                end
            end
        end
    endgenerate
    
    assign dout = mem_r[addr_r];
        
    generate
        if(FORCE_X2ZERO == 1) begin: force_x_to_zero
          for (i = 0; i < DW; i = i+1) begin:force_x_gen 
              `ifndef SYNTHESIS
             assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
              `else
             assign dout[i] = dout_pre[i];
              `endif
          end
        end
        else begin:no_force_x_to_zero
         assign dout = dout_pre;
        end
    endgenerate
            

endmodule
module sim_ram#(
    parameter DP = 512,
    parameter DW = 32,
    parameter MW= 4,
    parameter AW = 32,
    parameter FORCE_X2ZERO = 0,
    parameter ITCM = 0,
    parameter DTCM = 0
) (
    input  clk,
    input[DW-1:0] din,
    input[AW-1:0] addr,
    input we,
    input[MW-1:0] wem,
    output[DW-1:0] dout
);

    reg [DW-1:0] mem_r[0:DP-1];
    reg [AW-1:0] addr_r;
    wire [MW-1:0] wen;
    wire ren;
    wire [DW-1:0] dout_pre;
    integer j;

    assign ren = ~we;
    assign wen = ({MW{we}} & wem);


    always @(posedge clk ) begin
        if(ren) begin
            addr_r <= addr;
        end
    end
  
    genvar i;
    generate 
        for(i = 0; i<MW; i = i + 1) begin: simramloop
            if((8*i+8) > DW) begin: lastbyte
                always @(posedge clk) begin
                    if (wen[i]) begin: maskenabled
                        mem_r[addr][DW-1:8*i] <= din[DW-1:8*i];
                    end
                end
            end
            else begin: nonlastbytes
                always @(posedge clk) begin
                    if (wen[i]) begin: maskdisabeled
                        mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
                    end
                end
            end
        end
    endgenerate
    
    assign dout = mem_r[addr_r];
        
    generate
        if(FORCE_X2ZERO == 1) begin: force_x_to_zero
          for (i = 0; i < DW; i = i+1) begin:force_x_gen 
              `ifndef SYNTHESIS
             assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
              `else
             assign dout[i] = dout_pre[i];
              `endif
          end
        end
        else begin:no_force_x_to_zero
         assign dout = dout_pre;
        end
    endgenerate
            

endmodule