data/full_repos/permissive/467394306/rtl/core_input_ctrl.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/core_input_ctrl.sv:12: Little bit endian vector: MSB < LSB of bit range: 0:7\n    output [0 : ROWS-1] aemptys,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/core_input_ctrl.sv:13: Little bit endian vector: MSB < LSB of bit range: 0:7\n    output [0 : ROWS-1] wemptys,\n           ^\n%Error: data/full_repos/permissive/467394306/rtl/core_input_ctrl.sv:31: Cannot find file containing module: \'INBUF\'\n        INBUF #(.PADDING(i)) ainbuf (.clk(clk), .rstn(rstn),\n        ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/INBUF\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/INBUF.v\n             data/full_repos/permissive/467394306/rtl,data/full_repos/permissive/467394306/INBUF.sv\n             INBUF\n             INBUF.v\n             INBUF.sv\n             obj_dir/INBUF\n             obj_dir/INBUF.v\n             obj_dir/INBUF.sv\n%Error: data/full_repos/permissive/467394306/rtl/core_input_ctrl.sv:38: Cannot find file containing module: \'INBUF\'\n        INBUF #(.PADDING(i)) winbuf (.clk(clk), .rstn(rstn),\n        ^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module CORE_INPUT_CTRL #(
    parameter ROWS=8,
    parameter INWIDTH=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,
    input [INWIDTH-1 : 0] ainport [0 : ROWS-1],
    input [INWIDTH-1 : 0] winport [0 : ROWS-1],
    input write,
    input read,
    output [0 : ROWS-1] aemptys,
    output [0 : ROWS-1] wemptys,
    output [INWIDTH-1 : 0] ws [0 : ROWS-1],
    output [INWIDTH-1 : 0] as [0 : ROWS-1]);


    wire [INWIDTH-1 : 0] abufdins [0 : ROWS-1];
    wire [INWIDTH-1 : 0] wbufdins [0 : ROWS-1];
    wire [INWIDTH-1 : 0] abufouts [0 : ROWS-1];
    wire [INWIDTH-1 : 0] wbufouts [0 : ROWS-1];
    
    assign abufdins = ainport;
    assign wbufdins = winport;
    assign as = abufouts;
    assign ws = wbufouts;

    genvar i, j;
    generate
    for (i=0; i<ROWS; i=i+1) begin
        INBUF #(.PADDING(i)) ainbuf (.clk(clk), .rstn(rstn),
            .read(read),
            .write(write),
            .din(abufdins[i]),
            .empty(aemptys[i]),
            .dout(abufouts[i]));

        INBUF #(.PADDING(i)) winbuf (.clk(clk), .rstn(rstn),
            .read(read),
            .write(write),
            .din(wbufdins[i]),
            .empty(wemptys[i]),
            .dout(wbufouts[i]));
    end
    endgenerate
    
















endmodule
module CORE_INPUT_CTRL #(
    parameter ROWS=8,
    parameter INWIDTH=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,
    input [INWIDTH-1 : 0] ainport [0 : ROWS-1],
    input [INWIDTH-1 : 0] winport [0 : ROWS-1],
    input write,
    input read,
    output [0 : ROWS-1] aemptys,
    output [0 : ROWS-1] wemptys,
    output [INWIDTH-1 : 0] ws [0 : ROWS-1],
    output [INWIDTH-1 : 0] as [0 : ROWS-1]);



    wire [INWIDTH-1 : 0] abufdins [0 : ROWS-1];
    wire [INWIDTH-1 : 0] wbufdins [0 : ROWS-1];
    wire [INWIDTH-1 : 0] abufouts [0 : ROWS-1];
    wire [INWIDTH-1 : 0] wbufouts [0 : ROWS-1];
    
    assign abufdins = ainport;
    assign wbufdins = winport;
    assign as = abufouts;
    assign ws = wbufouts;

    genvar i, j;
    generate
    for (i=0; i<ROWS; i=i+1) begin
        INBUF #(.PADDING(i)) ainbuf (.clk(clk), .rstn(rstn),
            .read(read),
            .write(write),
            .din(abufdins[i]),
            .empty(aemptys[i]),
            .dout(abufouts[i]));

        INBUF #(.PADDING(i)) winbuf (.clk(clk), .rstn(rstn),
            .read(read),
            .write(write),
            .din(wbufdins[i]),
            .empty(wemptys[i]),
            .dout(wbufouts[i]));
    end
    endgenerate
    
















endmodule