data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:265: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:274: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:278: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:264: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:290: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:299: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:303: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:289: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:322: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 8 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 16 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:326: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b010: mem_out6 = {16\'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:313: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n  if ((core_l15_rqtype == 4\'b0000) & (l15_core_val == 1)) begin\n                       ^~\n%Error: Exiting due to 15 warning(s)\n'
function automatic signed [31:0] sv2v_cast_32_signed;
		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction
function automatic signed [31:0] sv2v_cast_32_signed;

		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction