data/full_repos/permissive/504677412/src/fifo_top/dist_afifo_fwft_4x8.v
1: b'%Error: data/full_repos/permissive/504677412/src/fifo_top/dist_afifo_fwft_4x8.v:23: syntax error, unexpected IDENTIFIER\noUx9+MiVNvr815jR1ObIVfEQvBkNpUHpUjcJr7NhnFefxICVvFHsGkTLfJ1uNhKnPy6ttJPzO14v\n^~~~\n%Error: Exiting due to 1 error(s)\n'
module dist_afifo_fwft_4x8 (
  Data,
  WrReset,
  RdReset,
  WrClk,
  RdClk,
  WrEn,
  RdEn,
  Almost_Empty,
  Almost_Full,
  Q,
  Empty,
  Full
)
;
input [3:0] Data;
input WrReset;
input RdReset;
input WrClk;
input RdClk;
input WrEn;
input RdEn;
output Almost_Empty;
output Almost_Full;
output [3:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo.dist_afifo_fwft_4x8  fifo_inst (
    .RdClk(RdClk),
    .RdReset(RdReset),
    .WrClk(WrClk),
    .WrReset(WrReset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[3:0]),
    .Full(Full),
    .Almost_Empty(Almost_Empty),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Q(Q[3:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule
module dist_afifo_fwft_4x8 (
  Data,
  WrReset,
  RdReset,
  WrClk,
  RdClk,
  WrEn,
  RdEn,
  Almost_Empty,
  Almost_Full,
  Q,
  Empty,
  Full
)
;

input [3:0] Data;
input WrReset;
input RdReset;
input WrClk;
input RdClk;
input WrEn;
input RdEn;
output Almost_Empty;
output Almost_Full;
output [3:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo.dist_afifo_fwft_4x8  fifo_inst (
    .RdClk(RdClk),
    .RdReset(RdReset),
    .WrClk(WrClk),
    .WrReset(WrReset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[3:0]),
    .Full(Full),
    .Almost_Empty(Almost_Empty),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Q(Q[3:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule