data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/2012_q2fsm/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/2012_q2fsm,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/2012_q2fsm/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire w,
    output reg  z
);

  parameter STATE_A = 3'b000;
  parameter STATE_B = 3'b001;
  parameter STATE_C = 3'b010;
  parameter STATE_D = 3'b011;
  parameter STATE_E = 3'b100;
  parameter STATE_F = 3'b101;
  parameter STATE_ILLEGAL = 3'b111;

  reg [2:0] state = STATE_A, next_state = STATE_A;


  always @(*) begin
    case ({
      w, state
    })
      {1'b0, STATE_A} : next_state = STATE_A;
      {1'b1, STATE_A} : next_state = STATE_B;
      {1'b0, STATE_B} : next_state = STATE_D;
      {1'b1, STATE_B} : next_state = STATE_C;
      {1'b0, STATE_C} : next_state = STATE_D;
      {1'b1, STATE_C} : next_state = STATE_E;
      {1'b0, STATE_D} : next_state = STATE_A;
      {1'b1, STATE_D} : next_state = STATE_F;
      {1'b0, STATE_E} : next_state = STATE_D;
      {1'b1, STATE_E} : next_state = STATE_E;
      {1'b0, STATE_F} : next_state = STATE_D;
      {1'b1, STATE_F} : next_state = STATE_C;
      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_A;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case (state)
      STATE_A, STATE_B, STATE_C, STATE_D: z = 1'b0;
      STATE_E, STATE_F: z = 1'b1;
      default: z = 1'bx;
    endcase
  end

endmodule
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire w,
    output reg  z
);


  parameter STATE_A = 3'b000;
  parameter STATE_B = 3'b001;
  parameter STATE_C = 3'b010;
  parameter STATE_D = 3'b011;
  parameter STATE_E = 3'b100;
  parameter STATE_F = 3'b101;
  parameter STATE_ILLEGAL = 3'b111;

  reg [2:0] state = STATE_A, next_state = STATE_A;


  always @(*) begin
    case ({
      w, state
    })
      {1'b0, STATE_A} : next_state = STATE_A;
      {1'b1, STATE_A} : next_state = STATE_B;
      {1'b0, STATE_B} : next_state = STATE_D;
      {1'b1, STATE_B} : next_state = STATE_C;
      {1'b0, STATE_C} : next_state = STATE_D;
      {1'b1, STATE_C} : next_state = STATE_E;
      {1'b0, STATE_D} : next_state = STATE_A;
      {1'b1, STATE_D} : next_state = STATE_F;
      {1'b0, STATE_E} : next_state = STATE_D;
      {1'b1, STATE_E} : next_state = STATE_E;
      {1'b0, STATE_F} : next_state = STATE_D;
      {1'b1, STATE_F} : next_state = STATE_C;
      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_A;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case (state)
      STATE_A, STATE_B, STATE_C, STATE_D: z = 1'b0;
      STATE_E, STATE_F: z = 1'b1;
      default: z = 1'bx;
    endcase
  end

endmodule