data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pl_cpld_regs.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pl_cpld_regs.v:48: Cannot find include file: regmap/constants_regmap_utils.vh\n  `include "regmap/constants_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh.sv\n             regmap/constants_regmap_utils.vh\n             regmap/constants_regmap_utils.vh.v\n             regmap/constants_regmap_utils.vh.sv\n             obj_dir/regmap/constants_regmap_utils.vh\n             obj_dir/regmap/constants_regmap_utils.vh.v\n             obj_dir/regmap/constants_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pl_cpld_regs.v:49: Cannot find include file: regmap/pl_cpld_base_regmap_utils.vh\n  `include "regmap/pl_cpld_base_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/pl_cpld_regs.v:50: Cannot find include file: ../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module pl_cpld_regs #(
  parameter BASE_ADDRESS = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,



  output wire [ 3:0] qsfp0_led_active,
  output wire [ 3:0] qsfp0_led_link,

  output wire [ 3:0] qsfp1_led_active,
  output wire [ 3:0] qsfp1_led_link,


  output wire [ 1:0] ipass_cable_present
);

  `include "regmap/constants_regmap_utils.vh"
  `include "regmap/pl_cpld_base_regmap_utils.vh"
  `include "../../../lib/rfnoc/core/ctrlport.vh"





  localparam NUM_ADDRESSES = 64;
  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





  reg [SCRATCH_REGISTER_SIZE-1:0]  scratch_reg;
  reg [LED_REGISTER_SIZE-1:0]      led_reg;
  reg [CABLE_PRESENT_REG_SIZE-1:0] ipass_reg;





  assign qsfp0_led_active = led_reg[QSFP0_LED_ACTIVE+:QSFP0_LED_ACTIVE_SIZE];
  assign qsfp0_led_link   = led_reg[QSFP0_LED_LINK+:QSFP0_LED_LINK_SIZE];

  assign qsfp1_led_active = led_reg[QSFP1_LED_ACTIVE+:QSFP1_LED_ACTIVE_SIZE];
  assign qsfp1_led_link   = led_reg[QSFP1_LED_LINK+:QSFP1_LED_LINK_SIZE];

  assign ipass_cable_present = ipass_reg;





  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      scratch_reg <= 0;
      led_reg <= 0;
      ipass_reg <= 0;
      s_ctrlport_resp_ack <= 1'b0;


    end else if (s_ctrlport_req_wr) begin

      s_ctrlport_resp_ack    <= 1'b1;
      s_ctrlport_resp_data   <= {CTRLPORT_DATA_W {1'bx}};
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SCRATCH_REGISTER:
          scratch_reg <= s_ctrlport_req_data;

        BASE_ADDRESS + LED_REGISTER:
          led_reg <= s_ctrlport_req_data[LED_REGISTER_SIZE-1:0];

        BASE_ADDRESS + CABLE_PRESENT_REG: begin
          ipass_reg[0] <= s_ctrlport_req_data[IPASS0_CABLE_PRESENT];
          ipass_reg[1] <= s_ctrlport_req_data[IPASS1_CABLE_PRESENT];
        end


        default: begin
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else if (s_ctrlport_req_rd) begin

      s_ctrlport_resp_ack <= 1'b1;
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SIGNATURE_REGISTER:
          s_ctrlport_resp_data <= PL_CPLD_SIGNATURE;

        BASE_ADDRESS + REVISION_REGISTER:
          s_ctrlport_resp_data <= CPLD_REVISION;

        BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
          s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;

        BASE_ADDRESS + SCRATCH_REGISTER:
          s_ctrlport_resp_data <= scratch_reg;

        BASE_ADDRESS + GIT_HASH_REGISTER:
            `ifdef GIT_HASH
              s_ctrlport_resp_data <= `GIT_HASH;
            `else
              s_ctrlport_resp_data <= 32'hDEADBEEF;
            `endif

        BASE_ADDRESS + LED_REGISTER:
          s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - LED_REGISTER_SIZE){1'b0}}, led_reg};

        BASE_ADDRESS + CABLE_PRESENT_REG: begin
          s_ctrlport_resp_data                       <= {CTRLPORT_DATA_W {1'b0}};
          s_ctrlport_resp_data[IPASS0_CABLE_PRESENT] <= ipass_reg[0];
          s_ctrlport_resp_data[IPASS1_CABLE_PRESENT] <= ipass_reg[1];
        end


        default: begin
          s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end

endmodule
module pl_cpld_regs #(
  parameter BASE_ADDRESS = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,



  output wire [ 3:0] qsfp0_led_active,
  output wire [ 3:0] qsfp0_led_link,

  output wire [ 3:0] qsfp1_led_active,
  output wire [ 3:0] qsfp1_led_link,


  output wire [ 1:0] ipass_cable_present
);


  `include "regmap/constants_regmap_utils.vh"
  `include "regmap/pl_cpld_base_regmap_utils.vh"
  `include "../../../lib/rfnoc/core/ctrlport.vh"





  localparam NUM_ADDRESSES = 64;
  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





  reg [SCRATCH_REGISTER_SIZE-1:0]  scratch_reg;
  reg [LED_REGISTER_SIZE-1:0]      led_reg;
  reg [CABLE_PRESENT_REG_SIZE-1:0] ipass_reg;





  assign qsfp0_led_active = led_reg[QSFP0_LED_ACTIVE+:QSFP0_LED_ACTIVE_SIZE];
  assign qsfp0_led_link   = led_reg[QSFP0_LED_LINK+:QSFP0_LED_LINK_SIZE];

  assign qsfp1_led_active = led_reg[QSFP1_LED_ACTIVE+:QSFP1_LED_ACTIVE_SIZE];
  assign qsfp1_led_link   = led_reg[QSFP1_LED_LINK+:QSFP1_LED_LINK_SIZE];

  assign ipass_cable_present = ipass_reg;





  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      scratch_reg <= 0;
      led_reg <= 0;
      ipass_reg <= 0;
      s_ctrlport_resp_ack <= 1'b0;


    end else if (s_ctrlport_req_wr) begin

      s_ctrlport_resp_ack    <= 1'b1;
      s_ctrlport_resp_data   <= {CTRLPORT_DATA_W {1'bx}};
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SCRATCH_REGISTER:
          scratch_reg <= s_ctrlport_req_data;

        BASE_ADDRESS + LED_REGISTER:
          led_reg <= s_ctrlport_req_data[LED_REGISTER_SIZE-1:0];

        BASE_ADDRESS + CABLE_PRESENT_REG: begin
          ipass_reg[0] <= s_ctrlport_req_data[IPASS0_CABLE_PRESENT];
          ipass_reg[1] <= s_ctrlport_req_data[IPASS1_CABLE_PRESENT];
        end


        default: begin
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else if (s_ctrlport_req_rd) begin

      s_ctrlport_resp_ack <= 1'b1;
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SIGNATURE_REGISTER:
          s_ctrlport_resp_data <= PL_CPLD_SIGNATURE;

        BASE_ADDRESS + REVISION_REGISTER:
          s_ctrlport_resp_data <= CPLD_REVISION;

        BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
          s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;

        BASE_ADDRESS + SCRATCH_REGISTER:
          s_ctrlport_resp_data <= scratch_reg;

        BASE_ADDRESS + GIT_HASH_REGISTER:
            `ifdef GIT_HASH
              s_ctrlport_resp_data <= `GIT_HASH;
            `else
              s_ctrlport_resp_data <= 32'hDEADBEEF;
            `endif

        BASE_ADDRESS + LED_REGISTER:
          s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - LED_REGISTER_SIZE){1'b0}}, led_reg};

        BASE_ADDRESS + CABLE_PRESENT_REG: begin
          s_ctrlport_resp_data                       <= {CTRLPORT_DATA_W {1'b0}};
          s_ctrlport_resp_data[IPASS0_CABLE_PRESENT] <= ipass_reg[0];
          s_ctrlport_resp_data[IPASS1_CABLE_PRESENT] <= ipass_reg[1];
        end


        default: begin
          s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end

endmodule