data/full_repos/permissive/476296842/rtl/core/ex_memwb.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:8: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:15: Define or directive not defined: \'`holdpip_bus\'\n    input wire [`holdpip_bus]   hold_flag_i,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`holdpip_bus]   hold_flag_i,\n                            ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  mem_w_reg_enable_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`reg_addr_bus]  w_reg_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:20: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]  w_reg_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:21: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]  ex_w_reg_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:25: Define or directive not defined: \'`mem_addr_bus\'\n    input wire [`mem_addr_bus]  w_mem_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`mem_data_bus]  w_mem_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:27: Define or directive not defined: \'`mem_data_bus\'\n    input wire [`mem_data_bus]  w_mem_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:29: Define or directive not defined: \'`mem_addr_bus\'\n    input wire [`mem_addr_bus]  r_mem_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`data_type_bus] data_type_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:33: Define or directive not defined: \'`data_type_bus\'\n    input wire [`data_type_bus] data_type_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                 mem_w_reg_enable_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`reg_addr_bus] w_reg_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:39: Define or directive not defined: \'`reg_addr_bus\'\n    output wire [`reg_addr_bus] w_reg_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:40: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus] ex_w_reg_data_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:44: Define or directive not defined: \'`mem_addr_bus\'\n    output wire [`mem_addr_bus] w_mem_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`mem_data_bus] w_mem_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:46: Define or directive not defined: \'`mem_data_bus\'\n    output wire [`mem_data_bus] w_mem_data_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:48: Define or directive not defined: \'`mem_addr_bus\'\n    output wire [`mem_addr_bus] r_mem_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:52: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`data_type_bus] data_type_o\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:52: Define or directive not defined: \'`data_type_bus\'\n    output wire [`data_type_bus] data_type_o\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:64: Define or directive not defined: \'`hold_flush\'\n    wire hold_flush = (hold_flag_i == `hold_flush);\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:64: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire hold_flush = (hold_flag_i == `hold_flush);\n                                                 ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:65: Define or directive not defined: \'`hold_wait\'\n    wire hold_wait = (hold_flag_i == `hold_wait);\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire hold_wait = (hold_flag_i == `hold_wait);\n                                               ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:74: Define or directive not defined: \'`write_disable\'\n        .default_data_i (`write_disable     ),\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:86: Define or directive not defined: \'`write_disable\'\n        .default_data_i (`write_disable     ),\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:92: Define or directive not defined: \'`reg_addr_bus_width\'\n        .dw (`reg_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:98: Define or directive not defined: \'`reg_zero\'\n        .default_data_i (`reg_zero          ),\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:104: Define or directive not defined: \'`reg_data_bus_width\'\n        .dw (`reg_data_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:110: Define or directive not defined: \'`data_zero\'\n        .default_data_i (`data_zero         ),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:116: Define or directive not defined: \'`mem_addr_bus_width\'\n        .dw (`mem_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:122: Define or directive not defined: \'`mem_addr_zero\'\n        .default_data_i (`mem_addr_zero     ),\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:134: Define or directive not defined: \'`mem_disable\'\n        .default_data_i (`mem_disable       ),\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:140: Define or directive not defined: \'`mem_data_bus_width\'\n        .dw (`mem_data_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:146: Define or directive not defined: \'`data_zero\'\n        .default_data_i (`data_zero         ),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:152: Define or directive not defined: \'`mem_addr_bus_width\'\n        .dw (`mem_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:158: Define or directive not defined: \'`mem_addr_zero\'\n        .default_data_i (`mem_addr_zero     ),\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:170: Define or directive not defined: \'`mem_disable\'\n        .default_data_i (`mem_disable       ),\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:176: Define or directive not defined: \'`data_type_bus_width\'\n        .dw (`data_type_bus_width)\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ex_memwb.v:182: Define or directive not defined: \'`datatype_no\'\n        .default_data_i (`datatype_no       ),\n                         ^~~~~~~~~~~~\n%Error: Exiting due to 43 error(s)\n'
module ex_memwb (
    input wire                  clk,
    input wire                  rst_n,

    input wire [`holdpip_bus]   hold_flag_i,


    input wire                  ex_w_reg_enable_i,
    input wire                  mem_w_reg_enable_i,
    input wire [`reg_addr_bus]  w_reg_addr_i,
    input wire [`reg_data_bus]  ex_w_reg_data_i,



    input wire [`mem_addr_bus]  w_mem_addr_i,
    input wire                  w_mem_enable_i,
    input wire [`mem_data_bus]  w_mem_data_i,

    input wire [`mem_addr_bus]  r_mem_addr_i,
    input wire                  r_mem_enable_i,


    input wire [`data_type_bus] data_type_i,



    output wire                 ex_w_reg_enable_o,
    output wire                 mem_w_reg_enable_o,
    output wire [`reg_addr_bus] w_reg_addr_o,
    output wire [`reg_data_bus] ex_w_reg_data_o,



    output wire [`mem_addr_bus] w_mem_addr_o,
    output wire                 w_mem_enable_o,
    output wire [`mem_data_bus] w_mem_data_o,

    output wire [`mem_addr_bus] r_mem_addr_o,
    output wire                 r_mem_enable_o,


    output wire [`data_type_bus] data_type_o


);

    wire hold_flush = (hold_flag_i == `hold_flush);
    wire hold_wait = (hold_flag_i == `hold_wait);

    pipe_reg_s #(
        .dw (1)
    ) pipe_ex_w_reg_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`write_disable     ),
        .data_i         (ex_w_reg_enable_i  ),
        .data_o         (ex_w_reg_enable_o  )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_mem_w_reg_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`write_disable     ),
        .data_i         (mem_w_reg_enable_i ),
        .data_o         (mem_w_reg_enable_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_w_reg_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`reg_zero          ),
        .data_i         (w_reg_addr_i       ),
        .data_o         (w_reg_addr_o       )
    );

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_ex_w_reg_data (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`data_zero         ),
        .data_i         (ex_w_reg_data_i    ),
        .data_o         (ex_w_reg_data_o    )
    );

    pipe_reg_s #(
        .dw (`mem_addr_bus_width)
    ) pipe_w_mem_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_addr_zero     ),
        .data_i         (w_mem_addr_i       ),
        .data_o         (w_mem_addr_o       )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_w_mem_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_disable       ),
        .data_i         (w_mem_enable_i     ),
        .data_o         (w_mem_enable_o     )
    );

    pipe_reg_s #(
        .dw (`mem_data_bus_width)
    ) pipe_w_mem_data (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`data_zero         ),
        .data_i         (w_mem_data_i       ),
        .data_o         (w_mem_data_o       )
    );

    pipe_reg_s #(
        .dw (`mem_addr_bus_width)
    ) pipe_r_mem_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_addr_zero     ),
        .data_i         (r_mem_addr_i       ),
        .data_o         (r_mem_addr_o       )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_r_mem_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_disable       ),
        .data_i         (r_mem_enable_i     ),
        .data_o         (r_mem_enable_o     )
    );
    
    pipe_reg_s #(
        .dw (`data_type_bus_width)
    ) pipe_data_type (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`datatype_no       ),
        .data_i         (data_type_i        ),
        .data_o         (data_type_o        )
    );



    
    `ifdef __DEBUG__


    `endif
    
endmodule
module ex_memwb (
    input wire                  clk,
    input wire                  rst_n,

    input wire [`holdpip_bus]   hold_flag_i,


    input wire                  ex_w_reg_enable_i,
    input wire                  mem_w_reg_enable_i,
    input wire [`reg_addr_bus]  w_reg_addr_i,
    input wire [`reg_data_bus]  ex_w_reg_data_i,



    input wire [`mem_addr_bus]  w_mem_addr_i,
    input wire                  w_mem_enable_i,
    input wire [`mem_data_bus]  w_mem_data_i,

    input wire [`mem_addr_bus]  r_mem_addr_i,
    input wire                  r_mem_enable_i,


    input wire [`data_type_bus] data_type_i,



    output wire                 ex_w_reg_enable_o,
    output wire                 mem_w_reg_enable_o,
    output wire [`reg_addr_bus] w_reg_addr_o,
    output wire [`reg_data_bus] ex_w_reg_data_o,



    output wire [`mem_addr_bus] w_mem_addr_o,
    output wire                 w_mem_enable_o,
    output wire [`mem_data_bus] w_mem_data_o,

    output wire [`mem_addr_bus] r_mem_addr_o,
    output wire                 r_mem_enable_o,


    output wire [`data_type_bus] data_type_o


);


    wire hold_flush = (hold_flag_i == `hold_flush);
    wire hold_wait = (hold_flag_i == `hold_wait);

    pipe_reg_s #(
        .dw (1)
    ) pipe_ex_w_reg_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`write_disable     ),
        .data_i         (ex_w_reg_enable_i  ),
        .data_o         (ex_w_reg_enable_o  )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_mem_w_reg_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`write_disable     ),
        .data_i         (mem_w_reg_enable_i ),
        .data_o         (mem_w_reg_enable_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_w_reg_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`reg_zero          ),
        .data_i         (w_reg_addr_i       ),
        .data_o         (w_reg_addr_o       )
    );

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_ex_w_reg_data (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`data_zero         ),
        .data_i         (ex_w_reg_data_i    ),
        .data_o         (ex_w_reg_data_o    )
    );

    pipe_reg_s #(
        .dw (`mem_addr_bus_width)
    ) pipe_w_mem_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_addr_zero     ),
        .data_i         (w_mem_addr_i       ),
        .data_o         (w_mem_addr_o       )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_w_mem_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_disable       ),
        .data_i         (w_mem_enable_i     ),
        .data_o         (w_mem_enable_o     )
    );

    pipe_reg_s #(
        .dw (`mem_data_bus_width)
    ) pipe_w_mem_data (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`data_zero         ),
        .data_i         (w_mem_data_i       ),
        .data_o         (w_mem_data_o       )
    );

    pipe_reg_s #(
        .dw (`mem_addr_bus_width)
    ) pipe_r_mem_addr (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_addr_zero     ),
        .data_i         (r_mem_addr_i       ),
        .data_o         (r_mem_addr_o       )
    );

    pipe_reg_s #(
        .dw (1)
    ) pipe_r_mem_enable (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`mem_disable       ),
        .data_i         (r_mem_enable_i     ),
        .data_o         (r_mem_enable_o     )
    );
    
    pipe_reg_s #(
        .dw (`data_type_bus_width)
    ) pipe_data_type (
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .set_default    (hold_flush         ),
        .hold_en        (hold_wait          ),
        .default_data_i (`datatype_no       ),
        .data_i         (data_type_i        ),
        .data_o         (data_type_o        )
    );



    
    `ifdef __DEBUG__


    `endif
    
endmodule