data/full_repos/permissive/531257706/src/sampleClockGen.v
data/verilator_xmls/62c4f5cd-49b1-47b3-b9d0-653008cda2a1.xml
module sampleClockGen #(parameter CLK_DIV = 2,  CLK_TOTAL=127)(
            input CLOCK, RESET,
            output [6:0] COUNT,
            output SAMP, SHIFT
            );

    reg sample, shift;
    reg [6:0] pulseCount;

    assign COUNT = pulseCount;
    assign SAMP  = sample;
    assign SHIFT = shift;


    always @(posedge CLOCK)
        begin
            if(RESET)
            begin
                pulseCount <= 0;
                sample     <=  0;
                shift      <=  0;
            end
            else
            begin
                if(pulseCount == CLK_TOTAL-1)
                begin
                    pulseCount <= 0;
                    sample     <=  1;
                    shift      <=  0;
                end
                else
                begin
                    pulseCount <= pulseCount + 1'b1;
                    sample     <=  0;
                    shift      <=  1;
                end
            end
        end

endmodule
module sampleClockGen #(parameter CLK_DIV = 2,  CLK_TOTAL=127)(
            input CLOCK, RESET,
            output [6:0] COUNT,
            output SAMP, SHIFT
            );


    reg sample, shift;
    reg [6:0] pulseCount;

    assign COUNT = pulseCount;
    assign SAMP  = sample;
    assign SHIFT = shift;


    always @(posedge CLOCK)
        begin
            if(RESET)
            begin
                pulseCount <= 0;
                sample     <=  0;
                shift      <=  0;
            end
            else
            begin
                if(pulseCount == CLK_TOTAL-1)
                begin
                    pulseCount <= 0;
                    sample     <=  1;
                    shift      <=  0;
                end
                else
                begin
                    pulseCount <= pulseCount + 1'b1;
                    sample     <=  0;
                    shift      <=  1;
                end
            end
        end

endmodule