data/full_repos/permissive/461141714/src/Single Cycle CPU/cpu.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/cpu.v\n%Error: Exiting due to 4 error(s)\n'
module cpu (
  output readM,
  output [`WORD_SIZE-1:0] address,
  inout [`WORD_SIZE-1:0] data,
  input inputReady,
  input reset_n,
  input clk,


  output [15:0] num_inst,
  output [15:0] output_port
);


wire isR;
wire [5:0] aluFunc;
wire isADI;
wire isLHI;
wire isJMP;
wire isOUT;
wire regWrite;


reg readM;
wire addr_wire;
reg [`WORD_SIZE-1:0] instruction;
reg [`WORD_SIZE-1:0] num_inst;


DataPath DP(
    clk, reset_n, instruction, isR, aluFunc, isADI, isLHI, isJMP, isOUT, regWrite, address, output_port
);

ControlUnit CU(
    instruction[15:12], instruction[5:0], isR, aluFunc, isADI, isLHI, isJMP, isOUT, regWrite
);


initial begin
    num_inst = 0;
end
always @(reset_n) begin
    num_inst = 0;
end


always @(posedge clk) begin
    num_inst = num_inst+1;
    readM = 1;
end

always @(inputReady) begin
    if(inputReady == 1) begin
        instruction = data;
        readM = 0;
    end
end



endmodule
module cpu (
  output readM,
  output [`WORD_SIZE-1:0] address,
  inout [`WORD_SIZE-1:0] data,
  input inputReady,
  input reset_n,
  input clk,


  output [15:0] num_inst,
  output [15:0] output_port
);



wire isR;
wire [5:0] aluFunc;
wire isADI;
wire isLHI;
wire isJMP;
wire isOUT;
wire regWrite;


reg readM;
wire addr_wire;
reg [`WORD_SIZE-1:0] instruction;
reg [`WORD_SIZE-1:0] num_inst;


DataPath DP(
    clk, reset_n, instruction, isR, aluFunc, isADI, isLHI, isJMP, isOUT, regWrite, address, output_port
);

ControlUnit CU(
    instruction[15:12], instruction[5:0], isR, aluFunc, isADI, isLHI, isJMP, isOUT, regWrite
);


initial begin
    num_inst = 0;
end
always @(reset_n) begin
    num_inst = 0;
end


always @(posedge clk) begin
    num_inst = num_inst+1;
    readM = 1;
end

always @(inputReady) begin
    if(inputReady == 1) begin
        instruction = data;
        readM = 0;
    end
end



endmodule