data/full_repos/permissive/455706578/bondmachine-src/bondmachine.sv
data/verilator_xmls/30d9174f-0823-424c-b6a5-d9529d98a82f.xml
module p0ram(clk, rst, din, dout, addr, wren, en);


	input clk;
	input rst;
	input [7:0] addr;
	input [7:0] din;
	input wren;
	input en;


	output [7:0] dout;


	reg [7:0] mem [0:255];

	reg [7:0] dout_i;



	always @ (posedge clk) 
	begin : MEM_WRITE 
		integer k; 
		if (rst)
		begin 
			for(k=0;k<256;k=k+1) 
				mem[k] <= #1 8'b0; 
		end 
		else if (wren)
			mem[addr] <= #1 din;
	end 



	always @ (posedge clk) 
	begin : MEM_READ 
		if (!wren)
			dout_i <= #1 mem[addr];
	end

	assign dout = dout_i;

endmodule
module p0ram(clk, rst, din, dout, addr, wren, en);



	input clk;
	input rst;
	input [7:0] addr;
	input [7:0] din;
	input wren;
	input en;


	output [7:0] dout;


	reg [7:0] mem [0:255];

	reg [7:0] dout_i;



	always @ (posedge clk) 
	begin : MEM_WRITE 
		integer k; 
		if (rst)
		begin 
			for(k=0;k<256;k=k+1) 
				mem[k] <= #1 8'b0; 
		end 
		else if (wren)
			mem[addr] <= #1 din;
	end 



	always @ (posedge clk) 
	begin : MEM_READ 
		if (!wren)
			dout_i <= #1 mem[addr];
	end

	assign dout = dout_i;

endmodule