data/full_repos/permissive/513199821/spi-bus.v
1: b'%Error: data/full_repos/permissive/513199821/spi-bus.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module spi_bus #(
    parameter SPI_MODE		= 0,
    parameter CLKS_PER_HALF_BIT = 8,
    parameter CS_INACTIVE_CLKS	= 1
  ) (

   input	i_Rst_L,
   input	i_Clk,


   input [6:0]	i_TX_Count,
   input [7:0]	i_TX_Byte,
   input	i_TX_DV,
   output	o_TX_Ready,


   output reg  [6:0] o_RX_Count,
   output wire	     o_RX_DV,
   output wire [7:0] o_RX_Byte,


   output o_SPI_Clk,
   input  i_SPI_MISO,
   output o_SPI_MOSI,
   output o_SPI_CS_n
);

localparam IDLE        = 2'b00;
localparam TRANSFER    = 2'b01;
localparam CS_INACTIVE = 2'b10;

reg [1:0] r_SM_CS;
reg r_CS_n;
reg [$clog2(CS_INACTIVE_CLKS)	- 1:0] r_CS_Inactive_Count;
reg [6:0] r_TX_Count;
wire w_Master_Ready;

assign o_SPI_CS_n = r_CS_n;
assign o_TX_Ready = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;


spi_master #(
    .SPI_MODE (SPI_MODE),
    .CLKS_PER_HALF_BIT (CLKS_PER_HALF_BIT)
  ) spi_master (

    .i_Rst_L (i_Rst_L),
    .i_Clk (i_Clk),


    .i_TX_Byte (i_TX_Byte),
    .i_TX_DV (i_TX_DV),
    .o_TX_Ready (w_Master_Ready),


    .o_RX_DV   (o_RX_DV),
    .o_RX_Byte (o_RX_Byte),


    .o_SPI_Clk (o_SPI_Clk),
    .i_SPI_MISO (i_SPI_MISO),
    .o_SPI_MOSI (o_SPI_MOSI)
);


always @(posedge i_Clk) begin
  if (r_CS_n) begin
    o_RX_Count <= 0;
  end else if (o_RX_DV) begin
    o_RX_Count <= o_RX_Count + 1'b1;
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    r_SM_CS		<= IDLE;
    r_CS_n		<= 1'b1;
    r_TX_Count		<= 0;
    r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
  end else begin
    case (r_SM_CS)
      IDLE: begin
	if (r_CS_n & i_TX_DV) begin
	  r_TX_Count <= i_TX_Count - 1;
	  r_CS_n     <= 1'b0;
	  r_SM_CS    <= TRANSFER;
`ifdef SPI_TEST
	  $display ("spibus begin %t count %x", $time, i_TX_Count);
`endif
	end
      end

      TRANSFER: begin

	if (w_Master_Ready) begin
	  if (|r_TX_Count) begin
	    if (i_TX_DV) begin
	      r_TX_Count <= r_TX_Count - 1;
`ifdef SPI_TEST
	      $display ("spibus loop  %t count %x", $time, r_TX_Count);
`endif
	    end
	  end else begin
	    r_CS_n		<= 1'b1;
	    r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
	    r_SM_CS		<= CS_INACTIVE;
`ifdef SPI_TEST
	  $display ("spibus done  %t", $time);
`endif
	  end
	end
      end

      CS_INACTIVE: begin
	if (r_CS_Inactive_Count > 0) begin
	  r_CS_Inactive_Count <= r_CS_Inactive_Count - 1'b1;
	end else begin
	  r_SM_CS <= IDLE;
	end
      end

      default: begin
	r_CS_n	<= 1'b1;
	r_SM_CS <= IDLE;
      end
    endcase
  end
end

endmodule
module spi_bus #(
    parameter SPI_MODE		= 0,
    parameter CLKS_PER_HALF_BIT = 8,
    parameter CS_INACTIVE_CLKS	= 1
  ) (

   input	i_Rst_L,
   input	i_Clk,


   input [6:0]	i_TX_Count,
   input [7:0]	i_TX_Byte,
   input	i_TX_DV,
   output	o_TX_Ready,


   output reg  [6:0] o_RX_Count,
   output wire	     o_RX_DV,
   output wire [7:0] o_RX_Byte,


   output o_SPI_Clk,
   input  i_SPI_MISO,
   output o_SPI_MOSI,
   output o_SPI_CS_n
);


localparam IDLE        = 2'b00;
localparam TRANSFER    = 2'b01;
localparam CS_INACTIVE = 2'b10;

reg [1:0] r_SM_CS;
reg r_CS_n;
reg [$clog2(CS_INACTIVE_CLKS)	- 1:0] r_CS_Inactive_Count;
reg [6:0] r_TX_Count;
wire w_Master_Ready;

assign o_SPI_CS_n = r_CS_n;
assign o_TX_Ready = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;


spi_master #(
    .SPI_MODE (SPI_MODE),
    .CLKS_PER_HALF_BIT (CLKS_PER_HALF_BIT)
  ) spi_master (

    .i_Rst_L (i_Rst_L),
    .i_Clk (i_Clk),


    .i_TX_Byte (i_TX_Byte),
    .i_TX_DV (i_TX_DV),
    .o_TX_Ready (w_Master_Ready),


    .o_RX_DV   (o_RX_DV),
    .o_RX_Byte (o_RX_Byte),


    .o_SPI_Clk (o_SPI_Clk),
    .i_SPI_MISO (i_SPI_MISO),
    .o_SPI_MOSI (o_SPI_MOSI)
);


always @(posedge i_Clk) begin
  if (r_CS_n) begin
    o_RX_Count <= 0;
  end else if (o_RX_DV) begin
    o_RX_Count <= o_RX_Count + 1'b1;
  end
end


always @(posedge i_Clk) begin
  if (~i_Rst_L) begin
    r_SM_CS		<= IDLE;
    r_CS_n		<= 1'b1;
    r_TX_Count		<= 0;
    r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
  end else begin
    case (r_SM_CS)
      IDLE: begin
	if (r_CS_n & i_TX_DV) begin
	  r_TX_Count <= i_TX_Count - 1;
	  r_CS_n     <= 1'b0;
	  r_SM_CS    <= TRANSFER;
`ifdef SPI_TEST
	  $display ("spibus begin %t count %x", $time, i_TX_Count);
`endif
	end
      end

      TRANSFER: begin

	if (w_Master_Ready) begin
	  if (|r_TX_Count) begin
	    if (i_TX_DV) begin
	      r_TX_Count <= r_TX_Count - 1;
`ifdef SPI_TEST
	      $display ("spibus loop  %t count %x", $time, r_TX_Count);
`endif
	    end
	  end else begin
	    r_CS_n		<= 1'b1;
	    r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
	    r_SM_CS		<= CS_INACTIVE;
`ifdef SPI_TEST
	  $display ("spibus done  %t", $time);
`endif
	  end
	end
      end

      CS_INACTIVE: begin
	if (r_CS_Inactive_Count > 0) begin
	  r_CS_Inactive_Count <= r_CS_Inactive_Count - 1'b1;
	end else begin
	  r_SM_CS <= IDLE;
	end
      end

      default: begin
	r_CS_n	<= 1'b1;
	r_SM_CS <= IDLE;
      end
    endcase
  end
end

endmodule