data/full_repos/permissive/497337299/basics/src/comp.v
data/verilator_xmls/c1830a9a-5420-4b19-b870-272a288e8434.xml
module comp(
    input [3:0] A,B ,
    output reg Lt,Eq,Gt

);
    assign Lt = A < B; 
    assign Eq = A == B; 
    assign Gt = A > B; 
endmodule
module comp(
    input [3:0] A,B ,
    output reg Lt,Eq,Gt

);

    assign Lt = A < B; 
    assign Eq = A == B; 
    assign Gt = A > B; 
endmodule