data/full_repos/permissive/518304758/iiitb_apb.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/518304758/iiitb_apb.v:213: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'apb_master\'\nmodule apb_master(\n       ^~~~~~~~~~\n                                                                       : ... Top module \'apb_slave\'\nmodule apb_slave(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:243: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance apb_slave\n  reg [31:0]apb_rdata=1\'b0;\n                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:338: Bit extraction of array[31:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance apb_slave\n                 apb_rdata = mem[apb_addr];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:342: Bit extraction of array[31:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance apb_slave\n                 mem[apb_addr] = apb_wdata;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:82: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                   : ... In instance apb_master\n       present_state<=IDLE;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:88: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                   : ... In instance apb_master\n    if( (present_state == ACCESS) && (apb_ready != 1))\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:106: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state=IDLE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:110: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'SETUP\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = SETUP;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:114: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n               next_state=IDLE;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:126: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n            next_state = ACCESS;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:148: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n               next_state = IDLE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:154: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = IDLE;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:158: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n                next_state = ACCESS;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:178: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n           next_state=IDLE;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'SETUP\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:101: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      case(present_state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:186: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                    : ... In instance apb_master\n      present_state <= IDLE;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/518304758/iiitb_apb.v:194: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'ACCESS\' generates 2 bits.\n                                                                    : ... In instance apb_master\n    if( (present_state == ACCESS) && (apb_ready == 1) )\n                       ^~\n%Error: Exiting due to 19 warning(s)\n'
module apb_master(


                  addr,
                  data_valid,
                  data,
                  data_dir,
             read_out_data,
             transaction_done,


                  apb_clk,
                  apb_reset,
                  apb_write,
                  apb_selx,
                  apb_en,
                  apb_wdata,
                  apb_rdata,
                  apb_ready,
                  apb_addr,
  				  apb_tranerr
                 );
 



  input     [7:0]       addr;
  input                 data_valid;  
  input     [31:0]      data;
  input                 data_dir;
  output [31:0]      read_out_data;
  output            transaction_done;


  input                 apb_clk;
  input                 apb_reset;
  output                apb_write;
  output                apb_selx;
  output                apb_en;
  output   [31:0]       apb_wdata;
  input    [31:0]       apb_rdata;
  input                 apb_ready;
  output   [7:0]        apb_addr;
  output   				apb_tranerr;
                 

  reg [31:0]      read_out_data;
  reg            transaction_done;
 
  reg                apb_write;
  reg                apb_selx;
  reg                apb_en;
  reg 				 apb_tranerr;
  reg   [31:0]       apb_wdata;
  reg   [7:0]        apb_addr;
  reg   [31:0]		 timeout_cnt;
  initial 
    begin
      timeout_cnt=0;
    end
  reg	[31:0]		 timeout_limit;
  initial 
    begin
      timeout_limit=20;
    end

 

 
  parameter [1:0]IDLE=2'b00;
  parameter [1:0]SETUP=2'b01;
  parameter [1:0]ACCESS=2'b10;
 

  reg [2:0] present_state, next_state;
 

  always@(posedge apb_clk)
  begin
      if(apb_reset)
        begin
       present_state<=IDLE;
    end
        else
        begin
          present_state<=next_state;
      end
    if( (present_state == ACCESS) && (apb_ready != 1))
    begin
       timeout_cnt <= timeout_cnt+1;    
    end
    else
    begin
       timeout_cnt <= 0;    
    end
  end
 

  always@(*)
  begin
      case(present_state)
        IDLE:
        begin
       if(apb_reset)
            begin
                next_state=IDLE;
            end
            else if(data_valid == 1)
            begin
                next_state = SETUP;
            end
            else
            begin      
               next_state=IDLE;
            end        
 
           
            apb_selx = 0;
            apb_write = 0;
            apb_en = 0;
            apb_wdata = 0;
          	apb_tranerr = 0;
        end
        SETUP:
        begin
            next_state = ACCESS;
            apb_selx = 1;
            apb_tranerr = 0;
            begin
            apb_addr = addr;
            if(data_dir == 1)
            begin
                apb_wdata = data;
                apb_write = 1;
            end
            else
            begin
               apb_wdata = 0;
               apb_write = 0;
            end
            end
        end
        ACCESS:
        begin
          if((apb_ready!=1) && (timeout_cnt>=timeout_limit))
             begin
               apb_tranerr = 1; 
               next_state = IDLE;
               
             end
            
            else if(apb_ready == 1)
             begin
                next_state = IDLE;
             end
             else
             begin
                next_state = ACCESS;
             end

             apb_selx = 1;
             apb_addr = addr;
             if(data_dir == 1)
             begin
                 apb_wdata = data;
                 apb_write = 1;
             end
             else
             begin
                apb_wdata = 0;
                apb_write = 0;
             end
             apb_en = 1;
           
        end
        default:
        begin
           next_state=IDLE;
        end
      endcase
  end

  always @(posedge apb_clk)
  begin
    if(apb_reset == 1)
      present_state <= IDLE;
    else
      present_state <= next_state;    
  end
 

  always @(posedge apb_clk)
  begin
    if( (present_state == ACCESS) && (apb_ready == 1) )
    begin
       transaction_done <=1;
       
      if(data_dir == 0)
      begin
        read_out_data <= apb_rdata;
      end
    end
    else
    begin
        transaction_done <= 0;
        read_out_data <= 0;
    end
  end
 
endmodule
module apb_master(


                  addr,
                  data_valid,
                  data,
                  data_dir,
             read_out_data,
             transaction_done,


                  apb_clk,
                  apb_reset,
                  apb_write,
                  apb_selx,
                  apb_en,
                  apb_wdata,
                  apb_rdata,
                  apb_ready,
                  apb_addr,
  				  apb_tranerr
                 );

 



  input     [7:0]       addr;
  input                 data_valid;  
  input     [31:0]      data;
  input                 data_dir;
  output [31:0]      read_out_data;
  output            transaction_done;


  input                 apb_clk;
  input                 apb_reset;
  output                apb_write;
  output                apb_selx;
  output                apb_en;
  output   [31:0]       apb_wdata;
  input    [31:0]       apb_rdata;
  input                 apb_ready;
  output   [7:0]        apb_addr;
  output   				apb_tranerr;
                 

  reg [31:0]      read_out_data;
  reg            transaction_done;
 
  reg                apb_write;
  reg                apb_selx;
  reg                apb_en;
  reg 				 apb_tranerr;
  reg   [31:0]       apb_wdata;
  reg   [7:0]        apb_addr;
  reg   [31:0]		 timeout_cnt;
  initial 
    begin
      timeout_cnt=0;
    end
  reg	[31:0]		 timeout_limit;
  initial 
    begin
      timeout_limit=20;
    end

 

 
  parameter [1:0]IDLE=2'b00;
  parameter [1:0]SETUP=2'b01;
  parameter [1:0]ACCESS=2'b10;
 

  reg [2:0] present_state, next_state;
 

  always@(posedge apb_clk)
  begin
      if(apb_reset)
        begin
       present_state<=IDLE;
    end
        else
        begin
          present_state<=next_state;
      end
    if( (present_state == ACCESS) && (apb_ready != 1))
    begin
       timeout_cnt <= timeout_cnt+1;    
    end
    else
    begin
       timeout_cnt <= 0;    
    end
  end
 

  always@(*)
  begin
      case(present_state)
        IDLE:
        begin
       if(apb_reset)
            begin
                next_state=IDLE;
            end
            else if(data_valid == 1)
            begin
                next_state = SETUP;
            end
            else
            begin      
               next_state=IDLE;
            end        
 
           
            apb_selx = 0;
            apb_write = 0;
            apb_en = 0;
            apb_wdata = 0;
          	apb_tranerr = 0;
        end
        SETUP:
        begin
            next_state = ACCESS;
            apb_selx = 1;
            apb_tranerr = 0;
            begin
            apb_addr = addr;
            if(data_dir == 1)
            begin
                apb_wdata = data;
                apb_write = 1;
            end
            else
            begin
               apb_wdata = 0;
               apb_write = 0;
            end
            end
        end
        ACCESS:
        begin
          if((apb_ready!=1) && (timeout_cnt>=timeout_limit))
             begin
               apb_tranerr = 1; 
               next_state = IDLE;
               
             end
            
            else if(apb_ready == 1)
             begin
                next_state = IDLE;
             end
             else
             begin
                next_state = ACCESS;
             end

             apb_selx = 1;
             apb_addr = addr;
             if(data_dir == 1)
             begin
                 apb_wdata = data;
                 apb_write = 1;
             end
             else
             begin
                apb_wdata = 0;
                apb_write = 0;
             end
             apb_en = 1;
           
        end
        default:
        begin
           next_state=IDLE;
        end
      endcase
  end

  always @(posedge apb_clk)
  begin
    if(apb_reset == 1)
      present_state <= IDLE;
    else
      present_state <= next_state;    
  end
 

  always @(posedge apb_clk)
  begin
    if( (present_state == ACCESS) && (apb_ready == 1) )
    begin
       transaction_done <=1;
       
      if(data_dir == 0)
      begin
        read_out_data <= apb_rdata;
      end
    end
    else
    begin
        transaction_done <= 0;
        read_out_data <= 0;
    end
  end
 
endmodule