data/full_repos/permissive/510755552/proj/accel/cfu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:65: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im0 <= im[7:0]  + 9\'d128; \n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:66: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im1 <= im[15:8] + 9\'d128;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:67: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im2 <= im[23:16] + 9\'d128; \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:68: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im3 <= im[31:24] + 9\'d128; \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:188: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n            tile_mem[mem_ctr]         <= cfu0[31:0];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:212: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:216: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr + 3; \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:220: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr + 6;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:305: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m00(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a00]),  .p(out[0])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:306: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m01(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a01]),  .p(out[1])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:307: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m02(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a02]),  .p(out[2])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:308: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m03(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a03]),  .p(out[3])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:309: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m04(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a04]),  .p(out[4])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:310: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m05(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a05]),  .p(out[5])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:311: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m06(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a06]),  .p(out[6])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:312: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m07(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a07]),  .p(out[7])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:313: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m08(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a08]),  .p(out[8])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:314: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m09(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a09]),  .p(out[9])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:315: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m10(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a10]),  .p(out[10])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:316: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m11(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a11]),  .p(out[11])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:317: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m12(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a12]),  .p(out[12])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:318: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m13(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a13]),  .p(out[13])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:319: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m14(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a14]),  .p(out[14]));     \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:320: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m15(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a15]),  .p(out[15]));\n                                                                                                ^\n%Error: Exiting due to 24 warning(s)\n'
module Cfu (
    input               cmd_valid,
    output              cmd_ready,
    input      [9:0]    cmd_payload_function_id,
    input      [31:0]   cmd_payload_inputs_0,
    input      [31:0]   cmd_payload_inputs_1,
    output              rsp_valid,
    input               rsp_ready,
    output     [31:0]   rsp_payload_outputs_0,
    input               clk,
    input               reset
);
    
    reg [31:0] output_0;
    reg [31:0] tile_mem_w;
    reg [31:0] tile_mem [0:63];
    

    reg [7:0] a00, a01, a02, a03, a04, a05, a06, a07, a08, a09, a10, a11, a12, a13, a14, a15; 
    
    reg [7:0] mem_ctr;
    reg [7:0] id;
    reg [3:0] ctr;
    reg rsp_valid_reg;
    reg mode;
     
    wire [31:0] cfu0, cfu1;
    wire [31:0] out [0:15];
    wire [2:0] func;
    wire [2:0] sel;
    wire ctr_reset;
    wire cfu_reset;
    wire wr_en;
    

    assign cmd_ready = ~rsp_valid;
    assign rsp_valid = rsp_valid_reg; 
    assign rsp_payload_outputs_0 = output_0[31:0];  
    assign func = cmd_payload_function_id[5:3]; 
    assign wr_en = cmd_valid && (func == 3'b101); 
    assign cfu0 = cmd_payload_inputs_0[31:0]; 
    assign cfu1 = cmd_payload_inputs_1[31:0];
    assign ctr_reset = ((func == 3'b101) || (func == 3'b010) || (func == 3'b100)) && cmd_valid; 
    assign cfu_reset = ((func == 3'b011) || reset) && cmd_valid; 
    

    integer i; 
    initial begin
        for(i = 0; i < 64; i = i + 1)
            tile_mem[i] = 32'h80808080; 
    end

    integer j; 
    always @(posedge clk) begin 
        if(reset) begin 
            for(j = 0; j < 64; j = j + 1)
               tile_mem[j] <= 0; 
            mem_ctr <= 0; 
        end 
        else if(wr_en) begin           
            tile_mem[mem_ctr]         <= cfu0[31:0];
            tile_mem[mem_ctr + 1]     <= cfu1[31:0];
            mem_ctr <= mem_ctr + 2;
       end    	
       else if((func == 3'b100) && cmd_valid)
           mem_ctr <= 0; 
    end
    


    always @(posedge clk) begin
        if(ctr_reset || reset || cfu_reset)
            ctr <= 0;  
        else if (ctr < 12 && cmd_valid)
            ctr <= ctr + 1; 
        else 
            ctr <= ctr; 
    end
    


    always @(*) begin 
        if ((func == 3'b001) && cmd_valid) begin 
            if(ctr < 3) begin 
                id = ctr; 
                mode = 1;  
            end 
            else if(ctr < 6) begin 
                id = ctr + 3; 
                mode = 1;
            end 
            else if(ctr < 9) begin 
                id = ctr + 6;
                mode = 1; 
            end 
            else if(ctr < 12) begin 
                id = 36; 
                mode = 1; 
            end 
            else begin 
                id = 0; 
                mode = 0;
            end 
        end 
        else begin
            id = 0; 
            mode = 0; 
        end 
    end 



    always @(posedge clk) begin
        if (reset) begin
            output_0 <= 32'b0;
            rsp_valid_reg <= 1'b0;
        end 
        else if (rsp_valid_reg) begin
            rsp_valid_reg <= ~rsp_ready;
        end 
        else if (cmd_valid) begin
            case(func) 
                3'b101:    begin 
                    rsp_valid_reg <= 1'b1;
                    output_0 <= 0;
                end
                3'b010:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= out[cfu0]; 
                end
                3'b001:    begin   
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0;
                end 
                3'b011:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
                3'b100:    begin  
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
                default:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
            endcase   
        end
    end


    always @ (posedge clk) begin 
        if(cmd_valid) begin 
            a00 <= id;
            a01 <= id + 1; 
            a02 <= id + 2;           
            a03 <= id + 3; 
            a04 <= id + 6;
            a05 <= id + 7; 
            a06 <= id + 8;
            a07 <= id + 9; 
            a08 <= id + 12;
            a09 <= id + 13; 
            a10 <= id + 14;
            a11 <= id + 15; 
            a12 <= id + 18;
            a13 <= id + 19; 
            a14 <= id + 20;
            a15 <= id + 21; 
            tile_mem_w <= (func == 3'b001) ? cfu0[31:0] : 32'd0;   
        end	  		
    end 
      
    assign sel = (func == 3'b001 || func == 3'b010) ? cfu1[2:0] : 3'd0;
    
    

    mac  m00(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a00]),  .p(out[0])); 
    mac  m01(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a01]),  .p(out[1])); 
    mac  m02(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a02]),  .p(out[2])); 
    mac  m03(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a03]),  .p(out[3])); 
    mac  m04(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a04]),  .p(out[4])); 
    mac  m05(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a05]),  .p(out[5])); 
    mac  m06(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a06]),  .p(out[6])); 
    mac  m07(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a07]),  .p(out[7])); 
    mac  m08(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a08]),  .p(out[8])); 
    mac  m09(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a09]),  .p(out[9])); 
    mac  m10(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a10]),  .p(out[10])); 
    mac  m11(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a11]),  .p(out[11])); 
    mac  m12(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a12]),  .p(out[12])); 
    mac  m13(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a13]),  .p(out[13])); 
    mac  m14(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a14]),  .p(out[14]));     
    mac  m15(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a15]),  .p(out[15]));

endmodule
module Cfu (
    input               cmd_valid,
    output              cmd_ready,
    input      [9:0]    cmd_payload_function_id,
    input      [31:0]   cmd_payload_inputs_0,
    input      [31:0]   cmd_payload_inputs_1,
    output              rsp_valid,
    input               rsp_ready,
    output     [31:0]   rsp_payload_outputs_0,
    input               clk,
    input               reset
);

    
    reg [31:0] output_0;
    reg [31:0] tile_mem_w;
    reg [31:0] tile_mem [0:63];
    

    reg [7:0] a00, a01, a02, a03, a04, a05, a06, a07, a08, a09, a10, a11, a12, a13, a14, a15; 
    
    reg [7:0] mem_ctr;
    reg [7:0] id;
    reg [3:0] ctr;
    reg rsp_valid_reg;
    reg mode;
     
    wire [31:0] cfu0, cfu1;
    wire [31:0] out [0:15];
    wire [2:0] func;
    wire [2:0] sel;
    wire ctr_reset;
    wire cfu_reset;
    wire wr_en;
    

    assign cmd_ready = ~rsp_valid;
    assign rsp_valid = rsp_valid_reg; 
    assign rsp_payload_outputs_0 = output_0[31:0];  
    assign func = cmd_payload_function_id[5:3]; 
    assign wr_en = cmd_valid && (func == 3'b101); 
    assign cfu0 = cmd_payload_inputs_0[31:0]; 
    assign cfu1 = cmd_payload_inputs_1[31:0];
    assign ctr_reset = ((func == 3'b101) || (func == 3'b010) || (func == 3'b100)) && cmd_valid; 
    assign cfu_reset = ((func == 3'b011) || reset) && cmd_valid; 
    

    integer i; 
    initial begin
        for(i = 0; i < 64; i = i + 1)
            tile_mem[i] = 32'h80808080; 
    end

    integer j; 
    always @(posedge clk) begin 
        if(reset) begin 
            for(j = 0; j < 64; j = j + 1)
               tile_mem[j] <= 0; 
            mem_ctr <= 0; 
        end 
        else if(wr_en) begin           
            tile_mem[mem_ctr]         <= cfu0[31:0];
            tile_mem[mem_ctr + 1]     <= cfu1[31:0];
            mem_ctr <= mem_ctr + 2;
       end    	
       else if((func == 3'b100) && cmd_valid)
           mem_ctr <= 0; 
    end
    


    always @(posedge clk) begin
        if(ctr_reset || reset || cfu_reset)
            ctr <= 0;  
        else if (ctr < 12 && cmd_valid)
            ctr <= ctr + 1; 
        else 
            ctr <= ctr; 
    end
    


    always @(*) begin 
        if ((func == 3'b001) && cmd_valid) begin 
            if(ctr < 3) begin 
                id = ctr; 
                mode = 1;  
            end 
            else if(ctr < 6) begin 
                id = ctr + 3; 
                mode = 1;
            end 
            else if(ctr < 9) begin 
                id = ctr + 6;
                mode = 1; 
            end 
            else if(ctr < 12) begin 
                id = 36; 
                mode = 1; 
            end 
            else begin 
                id = 0; 
                mode = 0;
            end 
        end 
        else begin
            id = 0; 
            mode = 0; 
        end 
    end 



    always @(posedge clk) begin
        if (reset) begin
            output_0 <= 32'b0;
            rsp_valid_reg <= 1'b0;
        end 
        else if (rsp_valid_reg) begin
            rsp_valid_reg <= ~rsp_ready;
        end 
        else if (cmd_valid) begin
            case(func) 
                3'b101:    begin 
                    rsp_valid_reg <= 1'b1;
                    output_0 <= 0;
                end
                3'b010:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= out[cfu0]; 
                end
                3'b001:    begin   
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0;
                end 
                3'b011:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
                3'b100:    begin  
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
                default:    begin 
                    rsp_valid_reg <= 1'b1; 
                    output_0 <= 0; 
                end 
            endcase   
        end
    end


    always @ (posedge clk) begin 
        if(cmd_valid) begin 
            a00 <= id;
            a01 <= id + 1; 
            a02 <= id + 2;           
            a03 <= id + 3; 
            a04 <= id + 6;
            a05 <= id + 7; 
            a06 <= id + 8;
            a07 <= id + 9; 
            a08 <= id + 12;
            a09 <= id + 13; 
            a10 <= id + 14;
            a11 <= id + 15; 
            a12 <= id + 18;
            a13 <= id + 19; 
            a14 <= id + 20;
            a15 <= id + 21; 
            tile_mem_w <= (func == 3'b001) ? cfu0[31:0] : 32'd0;   
        end	  		
    end 
      
    assign sel = (func == 3'b001 || func == 3'b010) ? cfu1[2:0] : 3'd0;
    
    

    mac  m00(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a00]),  .p(out[0])); 
    mac  m01(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a01]),  .p(out[1])); 
    mac  m02(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a02]),  .p(out[2])); 
    mac  m03(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a03]),  .p(out[3])); 
    mac  m04(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a04]),  .p(out[4])); 
    mac  m05(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a05]),  .p(out[5])); 
    mac  m06(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a06]),  .p(out[6])); 
    mac  m07(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a07]),  .p(out[7])); 
    mac  m08(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a08]),  .p(out[8])); 
    mac  m09(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a09]),  .p(out[9])); 
    mac  m10(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a10]),  .p(out[10])); 
    mac  m11(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a11]),  .p(out[11])); 
    mac  m12(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a12]),  .p(out[12])); 
    mac  m13(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a13]),  .p(out[13])); 
    mac  m14(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a14]),  .p(out[14]));     
    mac  m15(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a15]),  .p(out[15]));

endmodule