data/full_repos/permissive/425166201/03_testzx/adapter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425166201/03_testzx/adapter.v:41: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                           : ... In instance adapter\nwire [8:0] x = (X - 10\'h070 + 10\'h10);\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425166201/03_testzx/adapter.v:42: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 10 bits.\n                                                                           : ... In instance adapter\nwire [8:0] y = (Y - 10\'h050);\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module adapter
(
    input  wire        clock_25,
    output wire        vga_hs,
    output wire        vga_vs,
    output wire [ 3:0] vga_r,
    output wire [ 3:0] vga_g,
    output wire [ 3:0] vga_b,
    input  wire [ 3:0] bgcolor,
    output wire [15:0] address,
    input  wire [ 7:0] data_in
);


reg [9:0] X;
reg [9:0] Y;
reg [5:0] fcnt;
reg [7:0] masktmp;
reg [7:0] mask;
reg [7:0] attr;




assign vga_hs  = X < 10'h2C0;
assign vga_vs  = Y > 10'h20A;



assign address = xon_e ? address_char : address_attr;

wire   xmax   = X == 10'h31f;
wire   ymax   = Y == 10'h20c;
wire   fmax   = fcnt == 49;


wire visible = (X > 10'h02F) && (X < 10'h2B0) && (Y > 10'h020) && (Y < 10'h201);
wire vspaper = (X > 10'h06F) && (X < 10'h270) && (Y > 10'h04F) && (Y < 10'h1D0);


wire [8:0] x = (X - 10'h070 + 10'h10);
wire [8:0] y = (Y - 10'h050);






wire [ 2:0] bitn  = ~x[3:1];


wire        flash = attr[7] & (fcnt > 24);


wire xon_e = x[3:0] == 4'hE;
wire xon_f = x[3:0] == 4'hF;


wire [15:0] address_char = {3'b010,    y[8:7], y[3:1], y[6:4], x[8:4]};
wire [15:0] address_attr = {6'b010110, y[8:4], x[8:4]};


wire [ 3:0] paper = {attr[6], mask[bitn] ^ flash ? attr[2:0] : attr[5:3]};


wire [ 3:0] color = visible ? (vspaper ? paper : bgcolor) : 4'b0000;



assign vga_r = {color[1] & color[3], {3{color[1]}}};
assign vga_g = {color[2] & color[3], {3{color[2]}}};
assign vga_b = {color[0] & color[3], {3{color[0]}}};


always @(posedge clock_25) begin

    X <= xmax ? 0 : (X + 1);
    Y <= xmax ? (ymax ? 0 : Y + 1) : Y;


    fcnt    <= (xmax && ymax) ? (fmax ? 0 : fcnt + 1) : fcnt;


    masktmp <= xon_e ? data_in : masktmp;


    mask    <= xon_f ? masktmp : mask;
    attr    <= xon_f ? data_in : attr;

end

endmodule
module adapter
(
    input  wire        clock_25,
    output wire        vga_hs,
    output wire        vga_vs,
    output wire [ 3:0] vga_r,
    output wire [ 3:0] vga_g,
    output wire [ 3:0] vga_b,
    input  wire [ 3:0] bgcolor,
    output wire [15:0] address,
    input  wire [ 7:0] data_in
);



reg [9:0] X;
reg [9:0] Y;
reg [5:0] fcnt;
reg [7:0] masktmp;
reg [7:0] mask;
reg [7:0] attr;




assign vga_hs  = X < 10'h2C0;
assign vga_vs  = Y > 10'h20A;



assign address = xon_e ? address_char : address_attr;

wire   xmax   = X == 10'h31f;
wire   ymax   = Y == 10'h20c;
wire   fmax   = fcnt == 49;


wire visible = (X > 10'h02F) && (X < 10'h2B0) && (Y > 10'h020) && (Y < 10'h201);
wire vspaper = (X > 10'h06F) && (X < 10'h270) && (Y > 10'h04F) && (Y < 10'h1D0);


wire [8:0] x = (X - 10'h070 + 10'h10);
wire [8:0] y = (Y - 10'h050);






wire [ 2:0] bitn  = ~x[3:1];


wire        flash = attr[7] & (fcnt > 24);


wire xon_e = x[3:0] == 4'hE;
wire xon_f = x[3:0] == 4'hF;


wire [15:0] address_char = {3'b010,    y[8:7], y[3:1], y[6:4], x[8:4]};
wire [15:0] address_attr = {6'b010110, y[8:4], x[8:4]};


wire [ 3:0] paper = {attr[6], mask[bitn] ^ flash ? attr[2:0] : attr[5:3]};


wire [ 3:0] color = visible ? (vspaper ? paper : bgcolor) : 4'b0000;



assign vga_r = {color[1] & color[3], {3{color[1]}}};
assign vga_g = {color[2] & color[3], {3{color[2]}}};
assign vga_b = {color[0] & color[3], {3{color[0]}}};


always @(posedge clock_25) begin

    X <= xmax ? 0 : (X + 1);
    Y <= xmax ? (ymax ? 0 : Y + 1) : Y;


    fcnt    <= (xmax && ymax) ? (fmax ? 0 : fcnt + 1) : fcnt;


    masktmp <= xon_e ? data_in : masktmp;


    mask    <= xon_f ? masktmp : mask;
    attr    <= xon_f ? data_in : attr;

end

endmodule