data/full_repos/permissive/516830490/RTL/Multiplexer_circuit.v
1: b"%Error: data/full_repos/permissive/516830490/RTL/Multiplexer_circuit.v:57: Cannot find file containing module: 'counter'\n counter COUNTER(.i_clk(i_clk), .count_out(o_cnt));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/counter\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/counter.v\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s)\n"
module Multiplexer_circuit(
input i_clk ,  
input [`WIDTH_SEG-1:0]o_seg1 ,
input [`WIDTH_SEG-1:0]o_seg2 , 
output reg [`WIDTH_EN-1:0] o_en  , 
output reg [`WIDTH_SEG-1:0] o_seg
 );
 wire o_cnt;
 
 counter COUNTER(.i_clk(i_clk), .count_out(o_cnt));
    
 always @(*)
    begin
          case (o_cnt)
          1'b0: begin
                    o_seg = o_seg1 ;
                    o_en = 2'b10;
                     end 
         1'b1: begin
                    o_seg = o_seg2 ;
                    o_en = 2'b01;
                     end                  
        endcase
          end                              
endmodule
module Multiplexer_circuit(
input i_clk ,  
input [`WIDTH_SEG-1:0]o_seg1 ,
input [`WIDTH_SEG-1:0]o_seg2 , 
output reg [`WIDTH_EN-1:0] o_en  , 
output reg [`WIDTH_SEG-1:0] o_seg
 );

 wire o_cnt;
 
 counter COUNTER(.i_clk(i_clk), .count_out(o_cnt));
    
 always @(*)
    begin
          case (o_cnt)
          1'b0: begin
                    o_seg = o_seg1 ;
                    o_en = 2'b10;
                     end 
         1'b1: begin
                    o_seg = o_seg2 ;
                    o_en = 2'b01;
                     end                  
        endcase
          end                              
endmodule