data/full_repos/permissive/460468583/data/yosys/quicklogic/pp3_cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/quicklogic/pp3_cells_sim.v:12: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'inpad\'\nmodule inpad (\n       ^~~~~\n                                                                                                : ... Top module \'outpad\'\nmodule outpad (\n       ^~~~~~\n                                                                                                : ... Top module \'ckpad\'\nmodule ckpad (\n       ^~~~~\n                                                                                                : ... Top module \'bipad\'\nmodule bipad (\n       ^~~~~\n                                                                                                : ... Top module \'dff\'\nmodule dff (\n       ^~~\n                                                                                                : ... Top module \'dffc\'\nmodule dffc (\n       ^~~~\n                                                                                                : ... Top module \'dffp\'\nmodule dffp (\n       ^~~~\n                                                                                                : ... Top module \'dffpc\'\nmodule dffpc (\n       ^~~~~\n                                                                                                : ... Top module \'dffe\'\nmodule dffe (\n       ^~~~\n                                                                                                : ... Top module \'dffec\'\nmodule dffec (\n       ^~~~~\n                                                                                                : ... Top module \'dffepc\'\nmodule dffepc (\n       ^~~~~~\n                                                                                                : ... Top module \'AND2I0\'\nmodule AND2I0 (\n       ^~~~~~\n                                                                                                : ... Top module \'mux2x0\'\nmodule mux2x0 (\n       ^~~~~~\n                                                                                                : ... Top module \'mux2x1\'\nmodule mux2x1 (\n       ^~~~~~\n                                                                                                : ... Top module \'mux4x0\'\nmodule mux4x0 (\n       ^~~~~~\n                                                                                                : ... Top module \'mux8x0\'\nmodule mux8x0 (\n       ^~~~~~\n                                                                                                : ... Top module \'qlal4s3b_cell_macro\'\nmodule qlal4s3b_cell_macro (\n       ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module AND2I0 (
  output Q,
  input A, B
);
  specify
    (A => Q) = 698;
    (B => Q) = 639;
  endspecify

  assign Q = A ? B : 0;
endmodule
module AND2I0 (
  output Q,
  input A, B
);

  specify
    (A => Q) = 698;
    (B => Q) = 639;
  endspecify

  assign Q = A ? B : 0;
endmodule