data/full_repos/permissive/407937031/mul-booth-wallace/testbench/mul_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/407937031/mul-booth-wallace/testbench/mul_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/407937031/mul-booth-wallace/testbench/mul_tb.v:14: Cannot find file containing module: \'mul_top\'\n    mul_top test_mul(.src1(x), .src2(y), .res(res));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/407937031/mul-booth-wallace/testbench,data/full_repos/permissive/407937031/mul_top\n             data/full_repos/permissive/407937031/mul-booth-wallace/testbench,data/full_repos/permissive/407937031/mul_top.v\n             data/full_repos/permissive/407937031/mul-booth-wallace/testbench,data/full_repos/permissive/407937031/mul_top.sv\n             mul_top\n             mul_top.v\n             mul_top.sv\n             obj_dir/mul_top\n             obj_dir/mul_top.v\n             obj_dir/mul_top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mul_tb();

    reg [31:0] x;
    reg [31:0] y;
    wire[63:0] res;
    wire[63:0] ref_res;

    reg clk;

    assign ref_res = $signed(x) * $signed(y);

    mul_top test_mul(.src1(x), .src2(y), .res(res));

    initial begin
        clk = 1'b0;
    end

    always #10 clk = ~clk;

    always @(posedge clk) begin
        x <= $random();
        y <= $random();
    end


endmodule
module mul_tb();


    reg [31:0] x;
    reg [31:0] y;
    wire[63:0] res;
    wire[63:0] ref_res;

    reg clk;

    assign ref_res = $signed(x) * $signed(y);

    mul_top test_mul(.src1(x), .src2(y), .res(res));

    initial begin
        clk = 1'b0;
    end

    always #10 clk = ~clk;

    always @(posedge clk) begin
        x <= $random();
        y <= $random();
    end


endmodule