data/full_repos/permissive/528677531/LAB-3/Q1/q1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/528677531/LAB-3/Q1/q1.v:4: Signal definition not found, creating implicitly: \'g\'\nassign g=(A~&(B~&B))~&(C~&(D~&D));\n       ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module q1(A,B,C,D,f);
input A,B,C,D;
output f;
assign g=(A~&(B~&B))~&(C~&(D~&D));
assign f=(g~&g);
endmodule
module q1(A,B,C,D,f);

input A,B,C,D;
output f;
assign g=(A~&(B~&B))~&(C~&(D~&D));
assign f=(g~&g);
endmodule