data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv
1: b'%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:3: Unsupported: classes\nclass riscv_monitor_before extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:3: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass riscv_monitor_before extends uvm_monitor;\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:4: Define or directive not defined: \'`uvm_component_utils\'\n  `uvm_component_utils(riscv_monitor_before)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:8: Unsupported: virtual data type\n  virtual control_if ctrl_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:9: Unsupported: virtual data type\n  virtual dualport_bus instr_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:10: Unsupported: virtual data type\n  virtual dualport_bus mem_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:12: Unsupported: new constructor\n  function new(string name, uvm_component parent);\n           ^~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:12: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function new(string name, uvm_component parent);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:16: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void build_phase(uvm_phase phase);\n                                      ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:19: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual control_if)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:21: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:23: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task run_phase(uvm_phase phase);\n                           ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:32: syntax error, unexpected IDENTIFIER\n    riscv_transaction rv_tx;\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:54: Unsupported: classes\nclass riscv_monitor_after extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:54: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass riscv_monitor_after extends uvm_monitor;\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:55: Define or directive not defined: \'`uvm_component_utils\'\n  `uvm_component_utils(riscv_monitor_after)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:59: Unsupported: virtual data type\n  virtual control_if ctrl_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:60: Unsupported: virtual data type\n  virtual dualport_bus instr_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:61: Unsupported: virtual data type\n  virtual dualport_bus mem_vif;\n  ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:63: syntax error, unexpected IDENTIFIER\n  riscv_transaction rv_tx;\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:68: syntax error, unexpected IDENTIFIER\n  mem_rd_t mem_rd_delay[0:4] = \'{\'{0,0},\'{0,0},\'{0,0},\'{0,0},\'{0,0}};\n  ^~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:81: syntax error, unexpected IDENTIFIER\n  riscv_transaction rv_tx_cg;\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n  covergroup riscv_cg;\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          rs1_cp:     coverpoint rv_tx_cg.rs1;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          rs2_cp:     coverpoint rv_tx_cg.rs2;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:87: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          rd_cp:     coverpoint rv_tx_cg.rd;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          instr_cp:     coverpoint rv_tx_cg.instr;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:89: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          imm_cp:     coverpoint rv_tx_cg.imm;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:90: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          imm_jal_cp:     coverpoint rv_tx_cg.imm_jal[20:12];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n          mem_rd_data_cp:     coverpoint rv_tx_cg.mem_rd_data;\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:92: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n    cross rs1_cp, rs2_cp, rd_cp, instr_cp, imm_cp, imm_jal_cp, mem_rd_data_cp;\n    ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n  endgroup: riscv_cg\n  ^~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:96: Unsupported: new constructor\n  function new(string name, uvm_component parent);\n           ^~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:96: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function new(string name, uvm_component parent);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void build_phase(uvm_phase phase);\n                                      ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:104: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual control_if)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:106: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:108: Unsupported: virtual data type\n    void\'(uvm_resource_db#(virtual dualport_bus)::read_by_name\n                           ^~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:114: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task run_phase(uvm_phase phase);\n                           ^~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:147: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_mon_after", $sformatf("accept right after HAZARD!"), UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:164: syntax error, unexpected IDENTIFIER\n          for (int i = 3; i > -1; --i) begin\n                          ^\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:171: Define or directive not defined: \'`uvm_info\'\n                `uvm_info("rv_mon_after", \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:176: Define or directive not defined: \'`uvm_info\'\n                `uvm_info("rv_mon_after", \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:181: Define or directive not defined: \'`uvm_info\'\n                `uvm_info("rv_mon_after", \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:209: Define or directive not defined: \'`uvm_info\'\n          `uvm_info("rv_mon_after", "REJECT because of HAZARD!", UVM_LOW);\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:214: Define or directive not defined: \'`uvm_info\'\n            `uvm_info("rv_mon_after", "prepare for chain HAZARD!", UVM_LOW);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:221: Define or directive not defined: \'`uvm_info\'\n          `uvm_info("rv_mon_after", "REJECT because of previous JAL or BEQ!", UVM_LOW);\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:229: Define or directive not defined: \'`uvm_info\'\n        `uvm_info("rv_mon_after", \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/435890256/riscv_uvm/riscv_monitor.sv:274: syntax error, unexpected virtual\n  virtual function void instr_decode();\n          ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
function void delay_mem();
    mem_rd_delay[0] = mem_rd_delay[1];
    mem_rd_delay[1] = mem_rd_delay[2];
    mem_rd_delay[2] = mem_rd_delay[3];
    mem_rd_delay[3] = mem_rd_delay[4];
    mem_rd_delay[4] = '{0,0};

    mem_wr_delay[0] = mem_wr_delay[1];
    mem_wr_delay[1] = mem_wr_delay[2];
    mem_wr_delay[2] = mem_wr_delay[3];
    mem_wr_delay[3] = mem_wr_delay[4];
    mem_wr_delay[4] = '{0,0,0};
  endfunction
function void delay_mem();

    mem_rd_delay[0] = mem_rd_delay[1];
    mem_rd_delay[1] = mem_rd_delay[2];
    mem_rd_delay[2] = mem_rd_delay[3];
    mem_rd_delay[3] = mem_rd_delay[4];
    mem_rd_delay[4] = '{0,0};

    mem_wr_delay[0] = mem_wr_delay[1];
    mem_wr_delay[1] = mem_wr_delay[2];
    mem_wr_delay[2] = mem_wr_delay[3];
    mem_wr_delay[3] = mem_wr_delay[4];
    mem_wr_delay[4] = '{0,0,0};
  endfunction