data/full_repos/permissive/510695465/RegisterFile.v
1: b'%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[0] = 32\'h0000_0000;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:42: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[1] = 32\'h0000_0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[2] = 32\'h0000_0002;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:44: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[3] = 32\'h0000_0003;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:45: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h4\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[4] = 32\'h0000_0004;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h5\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[5] = 32\'h0000_0005;   \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:47: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h6\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[6] = 32\'h0000_0006;   \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/510695465/RegisterFile.v:48: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h7\' generates 32 bits.\n                                                                      : ... In instance RegisterFile\n        RegMemory[7] = 32\'h0000_0007;   \n                     ^\n%Error: Exiting due to 8 warning(s)\n'
module RegisterFile(
input [2:0] Read_Reg_Num_1,
input [2:0] Read_Reg_Num_2,
input [2:0] Write_Reg_Num_1,
input [7:0] Write_Data,
output [7:0] Read_Data_1,
output [7:0] Read_Data_2,
input RegWrite,
input Clk,
input Reset
);

reg [7:0] RegMemory [7:0];
integer i;
always @ (*)
begin  
    if (Reset == 0)
    begin
        RegMemory[0] = 32'h0000_0000;
        RegMemory[1] = 32'h0000_0001;
        RegMemory[2] = 32'h0000_0002;
        RegMemory[3] = 32'h0000_0003;
        RegMemory[4] = 32'h0000_0004;
        RegMemory[5] = 32'h0000_0005;   
        RegMemory[6] = 32'h0000_0006;   
        RegMemory[7] = 32'h0000_0007;   
    end
    else
    if ( RegWrite == 1 )
    begin   
         RegMemory[Write_Reg_Num_1] = Write_Data;
    end
end

assign Read_Data_1 = RegMemory[Read_Reg_Num_1];
assign Read_Data_2 = RegMemory[Read_Reg_Num_2];

endmodule
module RegisterFile(
input [2:0] Read_Reg_Num_1,
input [2:0] Read_Reg_Num_2,
input [2:0] Write_Reg_Num_1,
input [7:0] Write_Data,
output [7:0] Read_Data_1,
output [7:0] Read_Data_2,
input RegWrite,
input Clk,
input Reset
);


reg [7:0] RegMemory [7:0];
integer i;
always @ (*)
begin  
    if (Reset == 0)
    begin
        RegMemory[0] = 32'h0000_0000;
        RegMemory[1] = 32'h0000_0001;
        RegMemory[2] = 32'h0000_0002;
        RegMemory[3] = 32'h0000_0003;
        RegMemory[4] = 32'h0000_0004;
        RegMemory[5] = 32'h0000_0005;   
        RegMemory[6] = 32'h0000_0006;   
        RegMemory[7] = 32'h0000_0007;   
    end
    else
    if ( RegWrite == 1 )
    begin   
         RegMemory[Write_Reg_Num_1] = Write_Data;
    end
end

assign Read_Data_1 = RegMemory[Read_Reg_Num_1];
assign Read_Data_2 = RegMemory[Read_Reg_Num_2];

endmodule