data/full_repos/permissive/51918867/verilog/shift32_left7.v
data/verilator_xmls/8c5e9424-14c8-448e-b607-b474a973c112.xml
module shift32_left7(
    input[31:0]  v,
    output[31:0] q
);

assign q[31:0] = {v[24:0], 7'h0};


endmodule
module shift32_left7(
    input[31:0]  v,
    output[31:0] q
);


assign q[31:0] = {v[24:0], 7'h0};


endmodule