data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/ext_fifo.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/ext_fifo.v:50: Cannot find file containing module: 'dpram'\n   dpram #(.depth(10),.width(width),.size(1024))\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: Exiting due to 1 error(s)\n"
module bin2gray(bin_val,gray_val);
   parameter width = 8;
   input [width-1:0] bin_val;
   output reg [width-1:0] gray_val;
   
   integer i;

   always @*
     begin
	gray_val[width-1] = bin_val[width-1];
	for(i=0;i<width-1;i=i+1)
	  gray_val[i] = bin_val[i] ^ bin_val[i+1];
     end
endmodule
module bin2gray(bin_val,gray_val);

   parameter width = 8;
   input [width-1:0] bin_val;
   output reg [width-1:0] gray_val;
   
   integer i;

   always @*
     begin
	gray_val[width-1] = bin_val[width-1];
	for(i=0;i<width-1;i=i+1)
	  gray_val[i] = bin_val[i] ^ bin_val[i+1];
     end
endmodule