data/full_repos/permissive/509335294/pc_add.v
data/verilator_xmls/e75fd900-b3f7-4d1b-bc26-89b146b24931.xml
module pc_add(	input[12:0] a, b,
						output[12:0] sum
						);
	assign sum = a + b;
endmodule
module pc_add(	input[12:0] a, b,
						output[12:0] sum
						);

	assign sum = a + b;
endmodule