data/full_repos/permissive/445929378/main.v
1: b"%Error: data/full_repos/permissive/445929378/main.v:14: Cannot find file containing module: 'mult_128'\n   mult_128 test(\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128.sv\n             mult_128\n             mult_128.v\n             mult_128.sv\n             obj_dir/mult_128\n             obj_dir/mult_128.v\n             obj_dir/mult_128.sv\n%Error: Exiting due to 1 error(s)\n"
module main(
	    input wire 	clk, rst,
	    input wire 	start,
	    output wire finish
	    );
   
   reg [63:0] 		input_a_tdata;
   reg [63:0] 		input_b_tdata;
   wire [127:0] 	result;
   reg [127:0] 		result_reg;

   assign result = result_reg;

   mult_128 test(
		 .clk(clk),
		 .rst(rst),
		 .input_a_tdata(input_a_tdata),
		 .input_b_tdata(input_b_tdata),
		 .input_a_tvalid(start),
		 .input_b_tvalid(start),


		 .output_tdata(result),
		 .output_tvalid(finish),
		 .output_tready(start)
		 );
   
   always @(posedge clk) begin
      if(start) begin
	 input_a_tdata <= 64'd123123124443096802;
	 input_b_tdata <= 64'd314141255378583275;
      end
   end
endmodule
module main(
	    input wire 	clk, rst,
	    input wire 	start,
	    output wire finish
	    );

   
   reg [63:0] 		input_a_tdata;
   reg [63:0] 		input_b_tdata;
   wire [127:0] 	result;
   reg [127:0] 		result_reg;

   assign result = result_reg;

   mult_128 test(
		 .clk(clk),
		 .rst(rst),
		 .input_a_tdata(input_a_tdata),
		 .input_b_tdata(input_b_tdata),
		 .input_a_tvalid(start),
		 .input_b_tvalid(start),


		 .output_tdata(result),
		 .output_tvalid(finish),
		 .output_tready(start)
		 );
   
   always @(posedge clk) begin
      if(start) begin
	 input_a_tdata <= 64'd123123124443096802;
	 input_b_tdata <= 64'd314141255378583275;
      end
   end
endmodule