data/full_repos/permissive/496903659/141 exams#ece241_2014_q5b.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/141\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/141\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/141.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/141.sv\n             data/full_repos/permissive/496903659/141\n             data/full_repos/permissive/496903659/141.v\n             data/full_repos/permissive/496903659/141.sv\n             obj_dir/data/full_repos/permissive/496903659/141\n             obj_dir/data/full_repos/permissive/496903659/141.v\n             obj_dir/data/full_repos/permissive/496903659/141.sv\n%Error: Cannot find file containing module: exams#ece241_2014_q5b.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input clk,
    input areset,
    input x,
    output reg z
); 

    reg [1:0] state, next_state;
    always @(*) begin
        if (state == 1 << 0) begin
            if (x) begin
                next_state <= 1 << 1;

            end
            else begin
                next_state <= 1 << 0;

            end
        end
        else begin
            if (x) begin
                next_state <= 1 << 1;

            end
            else begin
                next_state <= 1 << 1;

            end
        end
    end
    
    always @(posedge clk, posedge areset) begin
        if (areset) begin
            state <= 1 << 0;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign z = (state == 1) & (x == 1) | (state == 2) & (x == 0);
    
endmodule
module top_module (
    input clk,
    input areset,
    input x,
    output reg z
);
 

    reg [1:0] state, next_state;
    always @(*) begin
        if (state == 1 << 0) begin
            if (x) begin
                next_state <= 1 << 1;

            end
            else begin
                next_state <= 1 << 0;

            end
        end
        else begin
            if (x) begin
                next_state <= 1 << 1;

            end
            else begin
                next_state <= 1 << 1;

            end
        end
    end
    
    always @(posedge clk, posedge areset) begin
        if (areset) begin
            state <= 1 << 0;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign z = (state == 1) & (x == 1) | (state == 2) & (x == 0);
    
endmodule