data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_rapid_non_pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_rapid_non_pipelined.v:135: Multiple top level modules\n                                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                          : ... Top module \'skinny_sbox8_dom1_rapid_non_pipelined\'\nmodule skinny_sbox8_dom1_rapid_non_pipelined ( \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'dom1_rpd_sbox8_cfn_fr_ne\'\nmodule dom1_rpd_sbox8_cfn_fr_ne ( \n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and4_dom1_ne\'\nmodule and4_dom1_ne ( \n       ^~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and3_dom1_ne\'\nmodule and3_dom1_ne ( \n       ^~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and2_dom1_ne\'\nmodule and2_dom1_ne ( \n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module and4_dom1_ne (

		     z,

		     a, b, c, d, r, clk
		  ) ;

   (*equivalent_register_removal = "no" *)output [1:0]  z;

   (*equivalent_register_removal = "no" *)input [1:0]   a, b, c, d;

   (*equivalent_register_removal = "no" *)input [6:0]    r;

   (*equivalent_register_removal = "no" *)input         clk;


   (*equivalent_register_removal = "no" *)reg [15:0]    comp;

   always @ (negedge clk) begin
      comp[ 0] <= (a[0] & b[0] & c[0] & d[0]);
      
      comp[ 1] <= (a[0] & b[0] & c[0] & d[1]) ^ r[0];

      comp[ 2] <= (a[0] & b[0] & c[1] & d[0]) ^ r[1];

      comp[ 3] <= (a[0] & b[0] & c[1] & d[1]) ^ r[2];

      comp[ 4] <= (a[0] & b[1] & c[0] & d[0]) ^ r[3];

      comp[ 5] <= (a[0] & b[1] & c[0] & d[1]) ^ r[4];

      comp[ 6] <= (a[0] & b[1] & c[1] & d[0]) ^ r[5];

      comp[ 7] <= (a[0] & b[1] & c[1] & d[1]) ^ r[6];

      comp[ 8] <= (a[1] & b[0] & c[0] & d[0]) ^ r[6];

      comp[ 9] <= (a[1] & b[0] & c[0] & d[1]) ^ r[5];

      comp[10] <= (a[1] & b[0] & c[1] & d[0]) ^ r[4];

      comp[11] <= (a[1] & b[0] & c[1] & d[1]) ^ r[3];

      comp[12] <= (a[1] & b[1] & c[0] & d[0]) ^ r[2];

      comp[13] <= (a[1] & b[1] & c[0] & d[1]) ^ r[1];

      comp[14] <= (a[1] & b[1] & c[1] & d[0]) ^ r[0];

      comp[15] <= (a[1] & b[1] & c[1] & d[1]);
      
   end
   
   assign z[0] = comp[ 0] ^ comp[ 1] ^ comp[ 2] ^ comp[ 3] ^
		 comp[ 4] ^ comp[ 5] ^ comp[ 6] ^ comp[ 7];

   assign z[1] = comp[ 8] ^ comp[ 9] ^ comp[10] ^ comp[11] ^
		 comp[12] ^ comp[13] ^ comp[14] ^ comp[15];


endmodule
module and4_dom1_ne (

		     z,

		     a, b, c, d, r, clk
		  ) ;


   (*equivalent_register_removal = "no" *)output [1:0]  z;

   (*equivalent_register_removal = "no" *)input [1:0]   a, b, c, d;

   (*equivalent_register_removal = "no" *)input [6:0]    r;

   (*equivalent_register_removal = "no" *)input         clk;


   (*equivalent_register_removal = "no" *)reg [15:0]    comp;

   always @ (negedge clk) begin
      comp[ 0] <= (a[0] & b[0] & c[0] & d[0]);
      
      comp[ 1] <= (a[0] & b[0] & c[0] & d[1]) ^ r[0];

      comp[ 2] <= (a[0] & b[0] & c[1] & d[0]) ^ r[1];

      comp[ 3] <= (a[0] & b[0] & c[1] & d[1]) ^ r[2];

      comp[ 4] <= (a[0] & b[1] & c[0] & d[0]) ^ r[3];

      comp[ 5] <= (a[0] & b[1] & c[0] & d[1]) ^ r[4];

      comp[ 6] <= (a[0] & b[1] & c[1] & d[0]) ^ r[5];

      comp[ 7] <= (a[0] & b[1] & c[1] & d[1]) ^ r[6];

      comp[ 8] <= (a[1] & b[0] & c[0] & d[0]) ^ r[6];

      comp[ 9] <= (a[1] & b[0] & c[0] & d[1]) ^ r[5];

      comp[10] <= (a[1] & b[0] & c[1] & d[0]) ^ r[4];

      comp[11] <= (a[1] & b[0] & c[1] & d[1]) ^ r[3];

      comp[12] <= (a[1] & b[1] & c[0] & d[0]) ^ r[2];

      comp[13] <= (a[1] & b[1] & c[0] & d[1]) ^ r[1];

      comp[14] <= (a[1] & b[1] & c[1] & d[0]) ^ r[0];

      comp[15] <= (a[1] & b[1] & c[1] & d[1]);
      
   end
   
   assign z[0] = comp[ 0] ^ comp[ 1] ^ comp[ 2] ^ comp[ 3] ^
		 comp[ 4] ^ comp[ 5] ^ comp[ 6] ^ comp[ 7];

   assign z[1] = comp[ 8] ^ comp[ 9] ^ comp[10] ^ comp[11] ^
		 comp[12] ^ comp[13] ^ comp[14] ^ comp[15];


endmodule