data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v
1: b"%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:91: Cannot find file containing module: 'DEMUX_1_3'\nDEMUX_1_3 #(.INPUT_DATA_WIDTH(DATA_WIDTH)) Demux_Data (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/DEMUX_1_3\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/DEMUX_1_3.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/DEMUX_1_3.sv\n             DEMUX_1_3\n             DEMUX_1_3.v\n             DEMUX_1_3.sv\n             obj_dir/DEMUX_1_3\n             obj_dir/DEMUX_1_3.v\n             obj_dir/DEMUX_1_3.sv\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:105: Cannot find file containing module: 'DEMUX_1_3'\nDEMUX_1_3 #(.INPUT_DATA_WIDTH(1'b1)) Demux_We (\n^~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:121: Cannot find file containing module: 'COUNTER_CH'\nCOUNTER_CH Counter_Ch(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:135: Cannot find file containing module: 'CHANNEL_MEM'\nCHANNEL_MEM #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:155: Cannot find file containing module: 'CHANNEL_MEM'\nCHANNEL_MEM #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:176: Cannot find file containing module: 'CHANNEL_MEM'\nCHANNEL_MEM #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MEMORIES_CHANNEL.v:197: Cannot find file containing module: 'MEMCH_STATEMACHINE'\nMEMCH_STATEMACHINE Memch_Statemachine(\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module MEMORIES_CHANNEL #(parameter DATA_WIDTH = 16, MEMORIES_SIZE=16384 ,ADDR_WIDTH = 14) (


MEMORIES_CHANNEL_Clk,
MEMORIES_CHANNEL_Start,
MEMORIES_CHANNEL_Reset,
MEMORIES_CHANNEL_Select_En,
MEMORIES_CHANNEL_In_Output_Rutine,
MEMORIES_CHANNEL_New_Channel_Flag,
MEMORIES_CHANNEL_Re,
MEMORIES_CHANNEL_Input_Data,


MEMORIES_CHANNEL_Out_Mem1,
MEMORIES_CHANNEL_Out_Mem2,
MEMORIES_CHANNEL_Out_Mem3

);





input MEMORIES_CHANNEL_Clk;
input MEMORIES_CHANNEL_Start;
input MEMORIES_CHANNEL_Reset;
input MEMORIES_CHANNEL_Select_En;
input MEMORIES_CHANNEL_In_Output_Rutine;
input MEMORIES_CHANNEL_New_Channel_Flag;
input MEMORIES_CHANNEL_Re;
input [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Input_Data;

output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem1;
output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem2;
output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem3;




localparam CHMEM_Rdinc=1'b1;
localparam CHMEM_Wrinc=1'b1;





wire[DATA_WIDTH-1:0] Demux_Data_Out0;
wire[DATA_WIDTH-1:0] Demux_Data_Out1;
wire[DATA_WIDTH-1:0] Demux_Data_Out2;

wire Demux_We_Out0;
wire Demux_We_Out1;
wire Demux_We_Out2;

wire [1:0] Counter_Ch_Out;

wire Memch_Statemachine_Counter_Ch_Clr;
wire Memch_Statemachine_Chmem1_Clr;
wire Memch_Statemachine_Chmem2_Clr;
wire Memch_Statemachine_Chmem3_Clr;
wire Memch_Statemachine_Counter_En;








DEMUX_1_3 #(.INPUT_DATA_WIDTH(DATA_WIDTH)) Demux_Data (


.DEMUX_Data_in(MEMORIES_CHANNEL_Input_Data),
.DEMUX_selector(Counter_Ch_Out),
.DEMUX_En(MEMORIES_CHANNEL_Select_En),

.DEMUX_out0(Demux_Data_Out0),
.DEMUX_out1(Demux_Data_Out1),
.DEMUX_out2(Demux_Data_Out2)

);


DEMUX_1_3 #(.INPUT_DATA_WIDTH(1'b1)) Demux_We (


.DEMUX_Data_in(1'b1),
.DEMUX_selector(Counter_Ch_Out),
.DEMUX_En(MEMORIES_CHANNEL_Select_En),

.DEMUX_out0(Demux_We_Out0),
.DEMUX_out1(Demux_We_Out1),
.DEMUX_out2(Demux_We_Out2)

);




COUNTER_CH Counter_Ch(


.COUNTER_Clk(MEMORIES_CHANNEL_Clk),
.COUNTER_Clr(Memch_Statemachine_Counter_Ch_Clr),
.COUNTER_En(Memch_Statemachine_Counter_En),


.COUNTER_Out(Counter_Ch_Out)

);



CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem1
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out0),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem1_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem1_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out0),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem1)
);



CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem2
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out1),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem2_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem2_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out1),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem2)
);




CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem3
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out2),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem3_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem3_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out2),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem3)
);




MEMCH_STATEMACHINE Memch_Statemachine(


.MEMCH_STATEMACHINE_Clk(MEMORIES_CHANNEL_Clk),
.MEMCH_STATEMACHINE_Reset(MEMORIES_CHANNEL_Reset),
.MEMCH_STATEMACHINE_Start(MEMORIES_CHANNEL_Start),
.MEMCH_STATEMACHINE_New_Channel_Flag(MEMORIES_CHANNEL_New_Channel_Flag),
.MEMCH_STATEMACHINE_In_Output_Routine(MEMORIES_CHANNEL_In_Output_Rutine),


.MEMCH_STATEMACHINE_Counter_Ch_Clr(Memch_Statemachine_Counter_Ch_Clr),
.MEMCH_STATEMACHINE_Chmem1_Clr(Memch_Statemachine_Chmem1_Clr),
.MEMCH_STATEMACHINE_Chmem2_Clr(Memch_Statemachine_Chmem2_Clr),
.MEMCH_STATEMACHINE_Chmem3_Clr(Memch_Statemachine_Chmem3_Clr),
.MEMCH_STATEMACHINE_Counter_En(Memch_Statemachine_Counter_En)

);





endmodule
module MEMORIES_CHANNEL #(parameter DATA_WIDTH = 16, MEMORIES_SIZE=16384 ,ADDR_WIDTH = 14) (


MEMORIES_CHANNEL_Clk,
MEMORIES_CHANNEL_Start,
MEMORIES_CHANNEL_Reset,
MEMORIES_CHANNEL_Select_En,
MEMORIES_CHANNEL_In_Output_Rutine,
MEMORIES_CHANNEL_New_Channel_Flag,
MEMORIES_CHANNEL_Re,
MEMORIES_CHANNEL_Input_Data,


MEMORIES_CHANNEL_Out_Mem1,
MEMORIES_CHANNEL_Out_Mem2,
MEMORIES_CHANNEL_Out_Mem3

);






input MEMORIES_CHANNEL_Clk;
input MEMORIES_CHANNEL_Start;
input MEMORIES_CHANNEL_Reset;
input MEMORIES_CHANNEL_Select_En;
input MEMORIES_CHANNEL_In_Output_Rutine;
input MEMORIES_CHANNEL_New_Channel_Flag;
input MEMORIES_CHANNEL_Re;
input [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Input_Data;

output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem1;
output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem2;
output [DATA_WIDTH-1:0] MEMORIES_CHANNEL_Out_Mem3;




localparam CHMEM_Rdinc=1'b1;
localparam CHMEM_Wrinc=1'b1;





wire[DATA_WIDTH-1:0] Demux_Data_Out0;
wire[DATA_WIDTH-1:0] Demux_Data_Out1;
wire[DATA_WIDTH-1:0] Demux_Data_Out2;

wire Demux_We_Out0;
wire Demux_We_Out1;
wire Demux_We_Out2;

wire [1:0] Counter_Ch_Out;

wire Memch_Statemachine_Counter_Ch_Clr;
wire Memch_Statemachine_Chmem1_Clr;
wire Memch_Statemachine_Chmem2_Clr;
wire Memch_Statemachine_Chmem3_Clr;
wire Memch_Statemachine_Counter_En;








DEMUX_1_3 #(.INPUT_DATA_WIDTH(DATA_WIDTH)) Demux_Data (


.DEMUX_Data_in(MEMORIES_CHANNEL_Input_Data),
.DEMUX_selector(Counter_Ch_Out),
.DEMUX_En(MEMORIES_CHANNEL_Select_En),

.DEMUX_out0(Demux_Data_Out0),
.DEMUX_out1(Demux_Data_Out1),
.DEMUX_out2(Demux_Data_Out2)

);


DEMUX_1_3 #(.INPUT_DATA_WIDTH(1'b1)) Demux_We (


.DEMUX_Data_in(1'b1),
.DEMUX_selector(Counter_Ch_Out),
.DEMUX_En(MEMORIES_CHANNEL_Select_En),

.DEMUX_out0(Demux_We_Out0),
.DEMUX_out1(Demux_We_Out1),
.DEMUX_out2(Demux_We_Out2)

);




COUNTER_CH Counter_Ch(


.COUNTER_Clk(MEMORIES_CHANNEL_Clk),
.COUNTER_Clr(Memch_Statemachine_Counter_Ch_Clr),
.COUNTER_En(Memch_Statemachine_Counter_En),


.COUNTER_Out(Counter_Ch_Out)

);



CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem1
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out0),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem1_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem1_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out0),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem1)
);



CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem2
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out1),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem2_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem2_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out1),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem2)
);




CHANNEL_MEM #(
.DATA_WIDTH(DATA_WIDTH), 
.MEM_SIZE(MEMORIES_SIZE),
.ADDR_WIDTH(ADDR_WIDTH)) Chmem3
(

.CHANNEL_MEM_Clk(MEMORIES_CHANNEL_Clk),
.CHANNEL_MEM_We(Demux_We_Out2),
.CHANNEL_MEM_Oe(MEMORIES_CHANNEL_Re),
.CHANNEL_MEM_Rdinc(CHMEM_Rdinc),
.CHANNEL_MEM_Wrinc(CHMEM_Wrinc),
.CHANNEL_MEM_Wptclr(Memch_Statemachine_Chmem3_Clr),
.CHANNEL_MEM_Rptclr(Memch_Statemachine_Chmem3_Clr),
.CHANNEL_MEM_Data_In(Demux_Data_Out2),

.CHANNEL_MEM_Data_Out(MEMORIES_CHANNEL_Out_Mem3)
);




MEMCH_STATEMACHINE Memch_Statemachine(


.MEMCH_STATEMACHINE_Clk(MEMORIES_CHANNEL_Clk),
.MEMCH_STATEMACHINE_Reset(MEMORIES_CHANNEL_Reset),
.MEMCH_STATEMACHINE_Start(MEMORIES_CHANNEL_Start),
.MEMCH_STATEMACHINE_New_Channel_Flag(MEMORIES_CHANNEL_New_Channel_Flag),
.MEMCH_STATEMACHINE_In_Output_Routine(MEMORIES_CHANNEL_In_Output_Rutine),


.MEMCH_STATEMACHINE_Counter_Ch_Clr(Memch_Statemachine_Counter_Ch_Clr),
.MEMCH_STATEMACHINE_Chmem1_Clr(Memch_Statemachine_Chmem1_Clr),
.MEMCH_STATEMACHINE_Chmem2_Clr(Memch_Statemachine_Chmem2_Clr),
.MEMCH_STATEMACHINE_Chmem3_Clr(Memch_Statemachine_Chmem3_Clr),
.MEMCH_STATEMACHINE_Counter_En(Memch_Statemachine_Counter_En)

);





endmodule