data/full_repos/permissive/410821791/Read_16x8.v
data/verilator_xmls/7273e82f-7268-465b-9284-462713e4bb69.xml
module bout (
    output bout,
    input a, b, bin, app
);
    assign bout = app ? (~a&bin | ~a&b | b&bin) : ((~(a&b)&bin) | b);
endmodule
module bout (
    output bout,
    input a, b, bin, app
);

    assign bout = app ? (~a&bin | ~a&b | b&bin) : ((~(a&b)&bin) | b);
endmodule