data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_encoder_4to2_gates.v
data/verilator_xmls/daf472d9-75e0-432a-9073-cbab07e67dbb.xml
module encoder_4to2_gates (i0,i1,i2,i3,y);
input i0,i1,i2,i3;
output [1:0] y;

or o1 (y[0],i1,i3);
or o2 (y[1],i2,i3);

endmodule
module encoder_4to2_gates (i0,i1,i2,i3,y);

input i0,i1,i2,i3;
output [1:0] y;

or o1 (y[0],i1,i3);
or o2 (y[1],i2,i3);

endmodule