data/full_repos/permissive/419984230/rtl/boothPP.v
data/verilator_xmls/fd2323d2-a8cc-49b8-95d1-071d6e28fa0b.xml
module boothPP #(parameter WIDTH = 14) (
    input   [WIDTH-1:0] in,
    output  [WIDTH:0] out_in,
    output  [WIDTH:0] out_in_n,
    output  [WIDTH:0] out_in_2,
    output  [WIDTH:0] out_in_2n,
    output  [WIDTH:0] out_zero
);

    wire [WIDTH:0] onesComp;


    assign onesComp     = ~{1'b0, in};
    assign out_in       = {1'b0, in};
    assign out_in_n     = onesComp;
    assign out_in_2     = {in, 1'b0};
    assign out_in_2n    = {onesComp[WIDTH-1:0], 1'b1};
    assign out_zero     = 0;

endmodule
module boothPP #(parameter WIDTH = 14) (
    input   [WIDTH-1:0] in,
    output  [WIDTH:0] out_in,
    output  [WIDTH:0] out_in_n,
    output  [WIDTH:0] out_in_2,
    output  [WIDTH:0] out_in_2n,
    output  [WIDTH:0] out_zero
);


    wire [WIDTH:0] onesComp;


    assign onesComp     = ~{1'b0, in};
    assign out_in       = {1'b0, in};
    assign out_in_n     = onesComp;
    assign out_in_2     = {in, 1'b0};
    assign out_in_2n    = {onesComp[WIDTH-1:0], 1'b1};
    assign out_zero     = 0;

endmodule