data/full_repos/permissive/493514142/verilog/rtl/FPU/FPU_Fclass.v
data/verilator_xmls/f0e21a11-842b-4365-b85f-10f04cf7219d.xml
module FPU_Fclass (Classification_Input,rst_l,Classification_Output,opcode);
  
  

  parameter Std = 15;
  parameter Man = 9;
  

  input [Std:0] Classification_Input;
  input rst_l;
  input opcode;


   output [31:0] Classification_Output;


  wire Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output; 




  assign Classification_Output = (rst_l & opcode ) ? { {22{1'b0}},  Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output} : {32{1'b0}};
  
  

  assign Classification_Neg_Infinity_Output = Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0])); 
  
  

  assign Classification_Pos_Infinity_Output = ~Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0]));
  
  

  assign Classification_Neg_Zero_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
  
  

  assign Classification_Pos_Zero_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
  
  

  assign Classification_Snan_Output = &(Classification_Input[Std-1:Man+1]) & (~Classification_Input[Man]) & (|(Classification_Input[Man-1:0]));
  
  

  assign Classification_Qnan_Output = &(Classification_Input[Std-1:Man+1]) & Classification_Input[Man] ;
  
  

  assign Classification_Pos_Normal_Output = ( (~Classification_Input[Std]) & ( |(Classification_Input[Std-1:Man+1]) )   ) & (~(& Classification_Input[Std-1:Man+1]))  ;

  

  assign Classification_Neg_Normal_Output =  ( (Classification_Input[Std]) & (|(Classification_Input[Std-1:Man+1]))  ) & (~(& Classification_Input[Std-1:Man+1])) ;
  
  

  assign Classification_Pos_Subnormal_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
  
  

  assign Classification_Neg_Subnormal_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
  
endmodule
module FPU_Fclass (Classification_Input,rst_l,Classification_Output,opcode);

  
  

  parameter Std = 15;
  parameter Man = 9;
  

  input [Std:0] Classification_Input;
  input rst_l;
  input opcode;


   output [31:0] Classification_Output;


  wire Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output; 




  assign Classification_Output = (rst_l & opcode ) ? { {22{1'b0}},  Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output} : {32{1'b0}};
  
  

  assign Classification_Neg_Infinity_Output = Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0])); 
  
  

  assign Classification_Pos_Infinity_Output = ~Classification_Input[Std] & (&(Classification_Input[Std-1:Man+1])) & (&(~Classification_Input[Man:0]));
  
  

  assign Classification_Neg_Zero_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
  
  

  assign Classification_Pos_Zero_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
  
  

  assign Classification_Snan_Output = &(Classification_Input[Std-1:Man+1]) & (~Classification_Input[Man]) & (|(Classification_Input[Man-1:0]));
  
  

  assign Classification_Qnan_Output = &(Classification_Input[Std-1:Man+1]) & Classification_Input[Man] ;
  
  

  assign Classification_Pos_Normal_Output = ( (~Classification_Input[Std]) & ( |(Classification_Input[Std-1:Man+1]) )   ) & (~(& Classification_Input[Std-1:Man+1]))  ;

  

  assign Classification_Neg_Normal_Output =  ( (Classification_Input[Std]) & (|(Classification_Input[Std-1:Man+1]))  ) & (~(& Classification_Input[Std-1:Man+1])) ;
  
  

  assign Classification_Pos_Subnormal_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
  
  

  assign Classification_Neg_Subnormal_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:Man+1])) & (|(Classification_Input[Man:0]));
  
endmodule