data/full_repos/permissive/478970138/4-8/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/478970138/4-8/user/sim/tb.v:6: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/478970138/4-8/user/sim/tb.v:7: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-8/user/sim/tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n        #2000 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-8/user/sim/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100 numInput = $random();\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (
);
    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb);
        #2000 $finish;
    end

    reg [6:0]   numInput = 7'b0;

    always begin
        #100 numInput = $random();
        while (numInput > 100) begin
            numInput = $random();
        end
    end

    wire [11:0]	numOutput;

    Convert_6BCD u_Convert_6BCD(

        .numInput  		( numInput  		),
        .numOutput 		( numOutput 		)
    );

endmodule
module tb (
);

    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, tb);
        #2000 $finish;
    end

    reg [6:0]   numInput = 7'b0;

    always begin
        #100 numInput = $random();
        while (numInput > 100) begin
            numInput = $random();
        end
    end

    wire [11:0]	numOutput;

    Convert_6BCD u_Convert_6BCD(

        .numInput  		( numInput  		),
        .numOutput 		( numOutput 		)
    );

endmodule