data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:1: Cannot find include file: VX_tex_define.vh\n`include "VX_tex_define.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.v\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.sv\n             VX_tex_define.vh\n             VX_tex_define.vh.v\n             VX_tex_define.vh.sv\n             obj_dir/VX_tex_define.vh\n             obj_dir/VX_tex_define.vh.v\n             obj_dir/VX_tex_define.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:16: Define or directive not defined: \'`TEX_FORMAT_BITS\'\n    input wire [`TEX_FORMAT_BITS-1:0]   req_format,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:17: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    input wire [`TEX_FILTER_BITS-1:0]   req_filter,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:18: Define or directive not defined: \'`TEX_WRAP_BITS\'\n    input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:19: Define or directive not defined: \'`TEX_ADDR_BITS\'\n    input wire [`TEX_ADDR_BITS-1:0]     req_baseaddr,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:20: Define or directive not defined: \'`TEX_MIPOFF_BITS\'\n    input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,    \n                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:21: Define or directive not defined: \'`TEX_DIM_BITS\'\n    input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:29: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    output wire [`TEX_FILTER_BITS-1:0]  rsp_filter,\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:30: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    output wire [`TEX_STRIDE_BITS-1:0]  rsp_stride,\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:32: Define or directive not defined: \'`BLEND_FRAC\'\n    output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:37: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (CORE_ID)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:37: syntax error, unexpected \'(\'\n    `UNUSED_PARAM (CORE_ID)\n                   ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`MAX\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                            ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`TEX_DIM_BITS\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:39: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;\n                                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: Define or directive not defined: \'`FIXED_INT\'\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;\n                                                         ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:41: Define or directive not defined: \'`FIXED_INT\'\n    localparam SCALED_X_W = (2 * `FIXED_INT);\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:41: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    localparam SCALED_X_W = (2 * `FIXED_INT);\n                                           ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:42: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;\n                                                         ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:46: Define or directive not defined: \'`TEX_FILTER_BITS\'\n    wire [`TEX_FILTER_BITS-1:0] filter_s0;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:48: Define or directive not defined: \'`FIXED_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:49: Define or directive not defined: \'`FIXED_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:50: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:52: Define or directive not defined: \'`TEX_DIM_BITS\'\n    wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0;\n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: Define or directive not defined: \'`FIXED_FRAC\'\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: Define or directive not defined: \'`FIXED_HALF\'\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:70: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\n            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);\n                                                        ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_FILTER_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`TEX_DIM_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: Define or directive not defined: \'`FIXED_FRAC\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:95: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),\n                                                                                                                                                       ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:107: Define or directive not defined: \'`FIXED_INT\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_lo;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:108: Define or directive not defined: \'`FIXED_INT\'\n    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_hi;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:109: Define or directive not defined: \'`BLEND_FRAC\'\n    wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] blends;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: Define or directive not defined: \'`BLEND_FRAC\'\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: Define or directive not defined: \'`BLEND_FRAC\'\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:116: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\n            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC\'(0);\n                                                                                                ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:120: Define or directive not defined: \'`UNUSED_VAR\'\n    `UNUSED_VAR (log_pitch_s0)\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:120: syntax error, unexpected \'(\'\n    `UNUSED_VAR (log_pitch_s0)\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:136: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`TEX_FILTER_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: Define or directive not defined: \'`BLEND_FRAC\'\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:141: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),\n                                                                                                                       ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:169: Define or directive not defined: \'`FIXED_INT\'\nfunction logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_addr.sv:169: Define or directive not defined: \'`FIXED_FRAC\'\nfunction logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, \n                                                           ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module VX_tex_addr #(
    parameter CORE_ID   = 0,
    parameter REQ_INFOW = 1,
    parameter NUM_REQS  = 1
) (
    input wire clk,
    input wire reset,



    input wire                          req_valid,    
    input wire [NUM_REQS-1:0]           req_tmask,
    input wire [1:0][NUM_REQS-1:0][31:0] req_coords,    
    input wire [`TEX_FORMAT_BITS-1:0]   req_format,
    input wire [`TEX_FILTER_BITS-1:0]   req_filter,
    input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,
    input wire [`TEX_ADDR_BITS-1:0]     req_baseaddr,
    input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,    
    input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,
    input wire [REQ_INFOW-1:0]          req_info,    
    output wire                         req_ready,



    output wire                         rsp_valid, 
    output wire [NUM_REQS-1:0]          rsp_tmask,
    output wire [`TEX_FILTER_BITS-1:0]  rsp_filter,
    output wire [`TEX_STRIDE_BITS-1:0]  rsp_stride,
    output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
    output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,
    output wire [REQ_INFOW-1:0]         rsp_info,  
    input wire                          rsp_ready
);

    `UNUSED_PARAM (CORE_ID)

    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;
    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;
    localparam SCALED_X_W = (2 * `FIXED_INT);
    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;

    wire                valid_s0;   
    wire [NUM_REQS-1:0] tmask_s0; 
    wire [`TEX_FILTER_BITS-1:0] filter_s0;
    wire [REQ_INFOW-1:0] req_info_s0;
    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;
    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;
    wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;
    wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0;
    wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0;
    wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0;

    wire stall_out;



    VX_tex_stride #(
        .CORE_ID (CORE_ID)
    ) tex_stride (
        .format     (req_format),
        .log_stride (log_stride)
    );



    for (genvar i = 0; i < NUM_REQS; ++i) begin
        for (genvar j = 0; j < 2; ++j) begin
            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);
            wire [31:0] coord_lo = req_filter ? (req_coords[j][i] - 32'(delta)) : req_coords[j][i];
            wire [31:0] coord_hi = req_filter ? (req_coords[j][i] + 32'(delta)) : req_coords[j][i];

            VX_tex_wrap #(
                .CORE_ID (CORE_ID)
            ) tex_wrap_lo (
                .wrap_i  (req_wraps[j]),
                .coord_i (coord_lo),
                .coord_o (clamped_lo[i][j])
            );

            VX_tex_wrap #(
                .CORE_ID (CORE_ID)
            ) tex_wrap_hi (
                .wrap_i  (req_wraps[j]),
                .coord_i (coord_hi),
                .coord_o (clamped_hi[i][j])
            );
        end
        assign log_pitch[i] = PITCH_BITS'(req_logdims[i][0]) + PITCH_BITS'(log_stride);        
        assign mip_addr[i]  = req_baseaddr + 32'(req_mipoff[i]);
    end

    VX_pipe_register #(
        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),
        .RESETW (1)
    ) pipe_reg0 (
        .clk      (clk),
        .reset    (reset),
        .enable   (~stall_out),
        .data_in  ({req_valid, req_tmask, req_filter, log_stride,    req_info,    log_pitch,    req_logdims, mip_addr,    clamped_lo,    clamped_hi}),
        .data_out ({valid_s0,  tmask_s0,  filter_s0,  log_stride_s0, req_info_s0, log_pitch_s0, log_dims_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0})
    );
    


    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_lo;
    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_hi;
    wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] blends;
    wire [NUM_REQS-1:0][3:0][31:0] addr;

    for (genvar i = 0; i < NUM_REQS; ++i) begin
        for (genvar j = 0; j < 2; ++j) begin  
            assign scaled_lo[i][j] = scale_to_dim(clamped_lo_s0[i][j], log_dims_s0[i][j]);
            assign scaled_hi[i][j] = scale_to_dim(clamped_hi_s0[i][j], log_dims_s0[i][j]);          
            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0);
        end
    end

    `UNUSED_VAR (log_pitch_s0)

    for (genvar i = 0; i < NUM_REQS; ++i) begin
        wire [SCALED_U_W-1:0] offset_u_lo = SCALED_U_W'(scaled_lo[i][0]) << log_stride_s0;
        wire [SCALED_U_W-1:0] offset_u_hi = SCALED_U_W'(scaled_hi[i][0]) << log_stride_s0;
        
        wire [SCALED_V_W-1:0] offset_v_lo = SCALED_V_W'(scaled_lo[i][1]) << log_pitch_s0[i];
        wire [SCALED_V_W-1:0] offset_v_hi = SCALED_V_W'(scaled_hi[i][1]) << log_pitch_s0[i];

        wire [31:0] base_addr_lo = mip_addr_s0[i] + 32'(offset_v_lo);
        wire [31:0] base_addr_hi = mip_addr_s0[i] + 32'(offset_v_hi);

        assign addr[i][0] = base_addr_lo + 32'(offset_u_lo);
        assign addr[i][1] = base_addr_lo + 32'(offset_u_hi);
        assign addr[i][2] = base_addr_hi + 32'(offset_u_lo);
        assign addr[i][3] = base_addr_hi + 32'(offset_u_hi);
    end

    assign stall_out = rsp_valid && ~rsp_ready;

    VX_pipe_register #(
        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),
        .RESETW (1)
    ) pipe_reg1 (
        .clk      (clk),
        .reset    (reset),
        .enable   (~stall_out),
        .data_in  ({valid_s0,  tmask_s0,  filter_s0,  log_stride_s0, addr,     blends,     req_info_s0}),
        .data_out ({rsp_valid, rsp_tmask, rsp_filter, rsp_stride,    rsp_addr, rsp_blends, rsp_info})
    );

    assign req_ready = ~stall_out;

`ifdef DBG_TRACE_TEX
    wire [`NW_BITS-1:0] rsp_wid;
    wire [31:0]         rsp_PC;

    assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0];
    
    always @(posedge clk) begin
        if (rsp_valid && rsp_ready) begin
            dpi_trace("%d: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, tride=%0d, addr=", 
                    $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride);
            `TRACE_ARRAY2D(rsp_addr, 4, NUM_REQS);
            dpi_trace("\n");
        end
    end
`endif

function logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, 
                                              input logic [`TEX_DIM_BITS-1:0] dim);
`IGNORE_WARNINGS_BEGIN
    logic [`FIXED_BITS-1:0] out;
`IGNORE_WARNINGS_END
    out = `FIXED_BITS'(src) << dim;
    return out[`FIXED_FRAC +: `FIXED_INT];
endfunction

endmodule
module VX_tex_addr #(
    parameter CORE_ID   = 0,
    parameter REQ_INFOW = 1,
    parameter NUM_REQS  = 1
) (
    input wire clk,
    input wire reset,



    input wire                          req_valid,    
    input wire [NUM_REQS-1:0]           req_tmask,
    input wire [1:0][NUM_REQS-1:0][31:0] req_coords,    
    input wire [`TEX_FORMAT_BITS-1:0]   req_format,
    input wire [`TEX_FILTER_BITS-1:0]   req_filter,
    input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,
    input wire [`TEX_ADDR_BITS-1:0]     req_baseaddr,
    input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,    
    input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,
    input wire [REQ_INFOW-1:0]          req_info,    
    output wire                         req_ready,



    output wire                         rsp_valid, 
    output wire [NUM_REQS-1:0]          rsp_tmask,
    output wire [`TEX_FILTER_BITS-1:0]  rsp_filter,
    output wire [`TEX_STRIDE_BITS-1:0]  rsp_stride,
    output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
    output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,
    output wire [REQ_INFOW-1:0]         rsp_info,  
    input wire                          rsp_ready
);


    `UNUSED_PARAM (CORE_ID)

    localparam PITCH_BITS = `MAX(`TEX_DIM_BITS, `TEX_STRIDE_BITS) + 1;
    localparam SCALED_U_W = `FIXED_INT + `TEX_STRIDE_BITS;
    localparam SCALED_X_W = (2 * `FIXED_INT);
    localparam SCALED_V_W = SCALED_X_W + `TEX_STRIDE_BITS;

    wire                valid_s0;   
    wire [NUM_REQS-1:0] tmask_s0; 
    wire [`TEX_FILTER_BITS-1:0] filter_s0;
    wire [REQ_INFOW-1:0] req_info_s0;
    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;
    wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;
    wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;
    wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0;
    wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0;
    wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0;

    wire stall_out;



    VX_tex_stride #(
        .CORE_ID (CORE_ID)
    ) tex_stride (
        .format     (req_format),
        .log_stride (log_stride)
    );



    for (genvar i = 0; i < NUM_REQS; ++i) begin
        for (genvar j = 0; j < 2; ++j) begin
            wire [`FIXED_FRAC-1:0] delta = (`FIXED_HALF >> req_logdims[i][j]);
            wire [31:0] coord_lo = req_filter ? (req_coords[j][i] - 32'(delta)) : req_coords[j][i];
            wire [31:0] coord_hi = req_filter ? (req_coords[j][i] + 32'(delta)) : req_coords[j][i];

            VX_tex_wrap #(
                .CORE_ID (CORE_ID)
            ) tex_wrap_lo (
                .wrap_i  (req_wraps[j]),
                .coord_i (coord_lo),
                .coord_o (clamped_lo[i][j])
            );

            VX_tex_wrap #(
                .CORE_ID (CORE_ID)
            ) tex_wrap_hi (
                .wrap_i  (req_wraps[j]),
                .coord_i (coord_hi),
                .coord_o (clamped_hi[i][j])
            );
        end
        assign log_pitch[i] = PITCH_BITS'(req_logdims[i][0]) + PITCH_BITS'(log_stride);        
        assign mip_addr[i]  = req_baseaddr + 32'(req_mipoff[i]);
    end

    VX_pipe_register #(
        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),
        .RESETW (1)
    ) pipe_reg0 (
        .clk      (clk),
        .reset    (reset),
        .enable   (~stall_out),
        .data_in  ({req_valid, req_tmask, req_filter, log_stride,    req_info,    log_pitch,    req_logdims, mip_addr,    clamped_lo,    clamped_hi}),
        .data_out ({valid_s0,  tmask_s0,  filter_s0,  log_stride_s0, req_info_s0, log_pitch_s0, log_dims_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0})
    );
    


    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_lo;
    wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_hi;
    wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] blends;
    wire [NUM_REQS-1:0][3:0][31:0] addr;

    for (genvar i = 0; i < NUM_REQS; ++i) begin
        for (genvar j = 0; j < 2; ++j) begin  
            assign scaled_lo[i][j] = scale_to_dim(clamped_lo_s0[i][j], log_dims_s0[i][j]);
            assign scaled_hi[i][j] = scale_to_dim(clamped_hi_s0[i][j], log_dims_s0[i][j]);          
            assign blends[i][j] = filter_s0 ? clamped_lo_s0[i][j][`BLEND_FRAC-1:0] : `BLEND_FRAC'(0);
        end
    end

    `UNUSED_VAR (log_pitch_s0)

    for (genvar i = 0; i < NUM_REQS; ++i) begin
        wire [SCALED_U_W-1:0] offset_u_lo = SCALED_U_W'(scaled_lo[i][0]) << log_stride_s0;
        wire [SCALED_U_W-1:0] offset_u_hi = SCALED_U_W'(scaled_hi[i][0]) << log_stride_s0;
        
        wire [SCALED_V_W-1:0] offset_v_lo = SCALED_V_W'(scaled_lo[i][1]) << log_pitch_s0[i];
        wire [SCALED_V_W-1:0] offset_v_hi = SCALED_V_W'(scaled_hi[i][1]) << log_pitch_s0[i];

        wire [31:0] base_addr_lo = mip_addr_s0[i] + 32'(offset_v_lo);
        wire [31:0] base_addr_hi = mip_addr_s0[i] + 32'(offset_v_hi);

        assign addr[i][0] = base_addr_lo + 32'(offset_u_lo);
        assign addr[i][1] = base_addr_lo + 32'(offset_u_hi);
        assign addr[i][2] = base_addr_hi + 32'(offset_u_lo);
        assign addr[i][3] = base_addr_hi + 32'(offset_u_hi);
    end

    assign stall_out = rsp_valid && ~rsp_ready;

    VX_pipe_register #(
        .DATAW  (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),
        .RESETW (1)
    ) pipe_reg1 (
        .clk      (clk),
        .reset    (reset),
        .enable   (~stall_out),
        .data_in  ({valid_s0,  tmask_s0,  filter_s0,  log_stride_s0, addr,     blends,     req_info_s0}),
        .data_out ({rsp_valid, rsp_tmask, rsp_filter, rsp_stride,    rsp_addr, rsp_blends, rsp_info})
    );

    assign req_ready = ~stall_out;

`ifdef DBG_TRACE_TEX
    wire [`NW_BITS-1:0] rsp_wid;
    wire [31:0]         rsp_PC;

    assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0];
    
    always @(posedge clk) begin
        if (rsp_valid && rsp_ready) begin
            dpi_trace("%d: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, tride=%0d, addr=", 
                    $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride);
            `TRACE_ARRAY2D(rsp_addr, 4, NUM_REQS);
            dpi_trace("\n");
        end
    end
`endif

function logic [`FIXED_INT-1:0] scale_to_dim (input logic [`FIXED_FRAC-1:0] src, 
                                              input logic [`TEX_DIM_BITS-1:0] dim);
`IGNORE_WARNINGS_BEGIN
    logic [`FIXED_BITS-1:0] out;
`IGNORE_WARNINGS_END
    out = `FIXED_BITS'(src) << dim;
    return out[`FIXED_FRAC +: `FIXED_INT];
endfunction

endmodule