data/full_repos/permissive/505761772/code/InOutStuff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/InOutStuff.v:30: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'SPI\'\nmodule SPI( input       CLK,\n       ^~~\n                                                                            : ... Top module \'DAC\'\nmodule DAC( input               SCK,\n       ^~~\n                                                                            : ... Top module \'GAIN\'\nmodule GAIN(input       SCK,\n       ^~~~\n                                                                            : ... Top module \'ADC\'\nmodule ADC( input       SCK,\n       ^~~\n                                                                            : ... Top module \'SERIAL_TX\'\nmodule SERIAL_TX (input [7:0]  DATA,\n       ^~~~~~~~~\n                                                                            : ... Top module \'SERIAL_RX\'\nmodule SERIAL_RX (input         CLK,\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'gain\' generates 4 bits.\n                                                                         : ... In instance GAIN\nreg [7:0] data = gain;\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:58: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'AorB\' generates 1 bits.\n                                                                         : ... In instance DAC\n      dataReg <= {8\'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};\n                        ^\n%Error: Exiting due to 3 warning(s)\n'
module SPI( input       CLK,
            output reg  AorB,
            input       MOSI_A,
            input       MOSI_B,
            output      MOSI,
            output      SCK);

reg [7:0]  BootCnt;
always @(posedge SCK) begin
  if(BootCnt == 8'hFF)
    AorB <= 1;
  else begin
    BootCnt <= BootCnt + 1;
    AorB <= 0;
  end
end

reg [2:0]  cnt;
always @(posedge CLK)
	cnt <= cnt + 1;

assign SCK = cnt[2];
assign MOSI = AorB ? MOSI_A : MOSI_B;

endmodule
module SPI( input       CLK,
            output reg  AorB,
            input       MOSI_A,
            input       MOSI_B,
            output      MOSI,
            output      SCK);


reg [7:0]  BootCnt;
always @(posedge SCK) begin
  if(BootCnt == 8'hFF)
    AorB <= 1;
  else begin
    BootCnt <= BootCnt + 1;
    AorB <= 0;
  end
end

reg [2:0]  cnt;
always @(posedge CLK)
	cnt <= cnt + 1;

assign SCK = cnt[2];
assign MOSI = AorB ? MOSI_A : MOSI_B;

endmodule