data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:9: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:11: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:13: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Alu_Control.v:22: Unsupported or unknown PLI call: $monitor\n$monitor("ALUop2=%1b,ALUop1=%1b,ALUop0=%1b,Func=%3b,C2=%1b,C1=%1b,C0=%1b",\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_Alu_Control();
reg ALUop0,ALUop1,ALUop2;
reg [2:0]Func;
wire C2,C1,C0;
Alu_Control ahmet(ALUop2,ALUop1,ALUop0,Func,C2,C1,C0);
initial begin
ALUop2=1'b1; ALUop1=1'b1; ALUop0=1'b1; Func=3'b000;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b1; ALUop0=1'b1; Func=3'b001;
#`DELAY;
ALUop2=1'b0; ALUop1=1'b0; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b0; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b0; ALUop1=1'b1; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b0; ALUop0=1'b1;
#`DELAY;
end
initial begin
$monitor("ALUop2=%1b,ALUop1=%1b,ALUop0=%1b,Func=%3b,C2=%1b,C1=%1b,C0=%1b",
					ALUop2,ALUop1,ALUop0,Func,C2,C1,C0);


end

endmodule
module test_bench_Alu_Control();

reg ALUop0,ALUop1,ALUop2;
reg [2:0]Func;
wire C2,C1,C0;
Alu_Control ahmet(ALUop2,ALUop1,ALUop0,Func,C2,C1,C0);
initial begin
ALUop2=1'b1; ALUop1=1'b1; ALUop0=1'b1; Func=3'b000;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b1; ALUop0=1'b1; Func=3'b001;
#`DELAY;
ALUop2=1'b0; ALUop1=1'b0; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b0; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b0; ALUop1=1'b1; ALUop0=1'b0;
#`DELAY;
ALUop2=1'b1; ALUop1=1'b0; ALUop0=1'b1;
#`DELAY;
end
initial begin
$monitor("ALUop2=%1b,ALUop1=%1b,ALUop0=%1b,Func=%3b,C2=%1b,C1=%1b,C0=%1b",
					ALUop2,ALUop1,ALUop0,Func,C2,C1,C0);


end

endmodule