data/full_repos/permissive/485467282/RAM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/485467282/RAM.v:18: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'tmp_data\' generates 16 bits.\n                                                             : ... In instance RAM\n    assign data = oe & !we ? tmp_data : \'hz;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/485467282/RAM.v:18: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                             : ... In instance RAM\n    assign data = oe & !we ? tmp_data : \'hz;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module RAM(
        inout [15:0] data,
        input [3:0] addr,
        input we, clk, oe
        );

    reg [15:0] ram [15:0];
    reg [15:0] tmp_data;

    always @ (posedge clk)
    begin
        if(we)
            ram[addr] <= data;  
        else
            tmp_data <= data;
    end

    assign data = oe & !we ? tmp_data : 'hz;

endmodule
module RAM(
        inout [15:0] data,
        input [3:0] addr,
        input we, clk, oe
        );


    reg [15:0] ram [15:0];
    reg [15:0] tmp_data;

    always @ (posedge clk)
    begin
        if(we)
            ram[addr] <= data;  
        else
            tmp_data <= data;
    end

    assign data = oe & !we ? tmp_data : 'hz;

endmodule