data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:29: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;\n                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;\n                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;\n                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #1 test_clk = ~test_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:48: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:53: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("RegisterTestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:54: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,RegisterTestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Register2/RegisterTestBench.v:56: Unsupported or unknown PLI call: $monitor\n $monitor("T = %d,test_out = %d,test_in = %d,test_in2 = %d,test_clk = %d,test_reset = %d,test_load = %d,test_load2 = %d",$time,test_out,test_in,test_in2,test_clk,test_reset,test_load,test_load2 );   \n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 62 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterTestBench;

parameter sim_time = 750*2;
reg [31:0] test_in,test_in2;
reg test_clk,test_reset,test_load,test_load2;
wire  [31:0] test_out;

Register2 test_reg(.IN(test_in),
				   .IN2(test_in2),
				  .Clk(test_clk),
				  .Reset(test_reset),
				  .Load(test_load),
				  .Load2(test_load2),
				  .OUT(test_out));

reg Clk,Reset;

initial fork
	test_in=0 ; test_in2=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ; test_load2=0 ;
	#1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;
	#2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;
	#3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;
	#4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;
	#5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;
	#6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;
	#7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;
	#8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;
	#9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;
	#10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;
	#11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;
	#12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;
join

always 
	#1 test_clk = ~test_clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench.vcd");
	$dumpvars(0,RegisterTestBench);
	$display(" Test Results" );
	$monitor("T = %d,test_out = %d,test_in = %d,test_in2 = %d,test_clk = %d,test_reset = %d,test_load = %d,test_load2 = %d",$time,test_out,test_in,test_in2,test_clk,test_reset,test_load,test_load2 );
end

endmodule
module RegisterTestBench;


parameter sim_time = 750*2;
reg [31:0] test_in,test_in2;
reg test_clk,test_reset,test_load,test_load2;
wire  [31:0] test_out;

Register2 test_reg(.IN(test_in),
				   .IN2(test_in2),
				  .Clk(test_clk),
				  .Reset(test_reset),
				  .Load(test_load),
				  .Load2(test_load2),
				  .OUT(test_out));

reg Clk,Reset;

initial fork
	test_in=0 ; test_in2=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ; test_load2=0 ;
	#1 test_in=1;#1 test_in2=0;  #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;
	#2 test_in=1;#2 test_in2=0;  #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;
	#3 test_in=0;#3 test_in2=0;  #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;
	#4 test_in=0;#4 test_in2=1;  #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;
	#5 test_in=0;#5 test_in2=1;  #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;
	#6 test_in=0;#6 test_in2=1;  #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;
	#7 test_in=1;#7 test_in2=0;  #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;
	#8 test_in=1;#8 test_in2=0;  #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;
	#9 test_in=0;#9 test_in2=0;  #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;
	#10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;
	#11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;
	#12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;
join

always 
	#1 test_clk = ~test_clk;
	
initial #sim_time $finish;



initial begin
	$dumpfile("RegisterTestBench.vcd");
	$dumpvars(0,RegisterTestBench);
	$display(" Test Results" );
	$monitor("T = %d,test_out = %d,test_in = %d,test_in2 = %d,test_clk = %d,test_reset = %d,test_load = %d,test_load2 = %d",$time,test_out,test_in,test_in2,test_clk,test_reset,test_load,test_load2 );
end

endmodule