data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_div_entry.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_div_entry.v:80: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_div_entry0_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_div_entry.v:100: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_div_entry1_gated_clk (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ct_iu_div_entry(
  cp0_iu_div_entry_disable_clr,
  cp0_iu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  div_clk,
  div_entry0_read_data,
  div_entry0_read_vld,
  div_entry1_read_data,
  div_entry1_read_vld,
  div_entry_write_data,
  div_entry_write_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);


input            cp0_iu_div_entry_disable_clr; 
input            cp0_iu_icg_en;               
input            cp0_yy_clk_en;               
input            cpurst_b;                    
input            div_clk;                     
input            div_entry0_read_vld;         
input            div_entry1_read_vld;         
input   [257:0]  div_entry_write_data;        
input            div_entry_write_en;          
input            forever_cpuclk;              
input            pad_yy_icg_scan_en;          
output  [257:0]  div_entry0_read_data;        
output  [257:0]  div_entry1_read_data;        


reg     [257:0]  div_entry0_data;             
reg              div_entry0_older;            
reg     [257:0]  div_entry1_data;             


wire             cp0_iu_div_entry_disable_clr; 
wire             cp0_iu_icg_en;               
wire             cp0_yy_clk_en;               
wire             cpurst_b;                    
wire             div_clk;                     
wire             div_entry0_clk;              
wire             div_entry0_clk_en;           
wire    [257:0]  div_entry0_read_data;        
wire             div_entry0_read_vld;         
wire             div_entry1_clk;              
wire             div_entry1_clk_en;           
wire    [257:0]  div_entry1_read_data;        
wire             div_entry1_read_vld;         
wire    [257:0]  div_entry_write_data;        
wire             div_entry_write_en;          
wire             forever_cpuclk;              
wire             pad_yy_icg_scan_en;          






assign div_entry0_clk_en = div_entry_write_en && div_entry0_older
                           || cp0_iu_div_entry_disable_clr;

gated_clk_cell  x_div_entry0_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (div_entry0_clk    ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (div_entry0_clk_en ),
  .module_en          (cp0_iu_icg_en     ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








assign div_entry1_clk_en = div_entry_write_en && !div_entry0_older
                           || cp0_iu_div_entry_disable_clr;

gated_clk_cell  x_div_entry1_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (div_entry1_clk    ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (div_entry1_clk_en ),
  .module_en          (cp0_iu_icg_en     ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge div_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    div_entry0_older <= 1'b0;
  else if(cp0_iu_div_entry_disable_clr)
    div_entry0_older <= 1'b0;
  else if(div_entry0_read_vld)
    div_entry0_older <= 1'b0;
  else if(div_entry1_read_vld)
    div_entry0_older <= 1'b1;
  else if(div_entry_write_en)
    div_entry0_older <= !div_entry0_older;
  else
    div_entry0_older <= div_entry0_older;
end




always @(posedge div_entry0_clk or negedge cpurst_b)
begin
  if(!cpurst_b)

    div_entry0_data[257:0] <= {1'b0, 1'b0,
                               64'b0, 64'hffffffffffffffff,
                               64'b1, 64'hffffffffffffffff};
  else if(cp0_iu_div_entry_disable_clr)

    div_entry0_data[257:0] <= {1'b0, 1'b0,
                               64'b0, 64'hffffffffffffffff,
                               64'b1, 64'hffffffffffffffff};
  else if(div_entry_write_en && div_entry0_older)
    div_entry0_data[257:0] <= div_entry_write_data[257:0];
  else
    div_entry0_data[257:0] <= div_entry0_data[257:0];
end

assign div_entry0_read_data[257:0] = div_entry0_data[257:0];




always @(posedge div_entry1_clk or negedge cpurst_b)
begin
  if(!cpurst_b)

    div_entry1_data[257:0] <= {1'b0, 1'b1,
                               64'b0, 64'h7fffffffffffffff,
                               64'b1, 64'h7fffffffffffffff};
  else if(cp0_iu_div_entry_disable_clr)

    div_entry1_data[257:0] <= {1'b0, 1'b1,
                               64'b0, 64'h7fffffffffffffff,
                               64'b1, 64'h7fffffffffffffff};
  else if(div_entry_write_en && !div_entry0_older)
    div_entry1_data[257:0] <= div_entry_write_data[257:0];
  else
    div_entry1_data[257:0] <= div_entry1_data[257:0];
end

assign div_entry1_read_data[257:0] = div_entry1_data[257:0];



endmodule
module ct_iu_div_entry(
  cp0_iu_div_entry_disable_clr,
  cp0_iu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  div_clk,
  div_entry0_read_data,
  div_entry0_read_vld,
  div_entry1_read_data,
  div_entry1_read_vld,
  div_entry_write_data,
  div_entry_write_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);



input            cp0_iu_div_entry_disable_clr; 
input            cp0_iu_icg_en;               
input            cp0_yy_clk_en;               
input            cpurst_b;                    
input            div_clk;                     
input            div_entry0_read_vld;         
input            div_entry1_read_vld;         
input   [257:0]  div_entry_write_data;        
input            div_entry_write_en;          
input            forever_cpuclk;              
input            pad_yy_icg_scan_en;          
output  [257:0]  div_entry0_read_data;        
output  [257:0]  div_entry1_read_data;        


reg     [257:0]  div_entry0_data;             
reg              div_entry0_older;            
reg     [257:0]  div_entry1_data;             


wire             cp0_iu_div_entry_disable_clr; 
wire             cp0_iu_icg_en;               
wire             cp0_yy_clk_en;               
wire             cpurst_b;                    
wire             div_clk;                     
wire             div_entry0_clk;              
wire             div_entry0_clk_en;           
wire    [257:0]  div_entry0_read_data;        
wire             div_entry0_read_vld;         
wire             div_entry1_clk;              
wire             div_entry1_clk_en;           
wire    [257:0]  div_entry1_read_data;        
wire             div_entry1_read_vld;         
wire    [257:0]  div_entry_write_data;        
wire             div_entry_write_en;          
wire             forever_cpuclk;              
wire             pad_yy_icg_scan_en;          






assign div_entry0_clk_en = div_entry_write_en && div_entry0_older
                           || cp0_iu_div_entry_disable_clr;

gated_clk_cell  x_div_entry0_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (div_entry0_clk    ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (div_entry0_clk_en ),
  .module_en          (cp0_iu_icg_en     ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








assign div_entry1_clk_en = div_entry_write_en && !div_entry0_older
                           || cp0_iu_div_entry_disable_clr;

gated_clk_cell  x_div_entry1_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (div_entry1_clk    ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (div_entry1_clk_en ),
  .module_en          (cp0_iu_icg_en     ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);












always @(posedge div_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    div_entry0_older <= 1'b0;
  else if(cp0_iu_div_entry_disable_clr)
    div_entry0_older <= 1'b0;
  else if(div_entry0_read_vld)
    div_entry0_older <= 1'b0;
  else if(div_entry1_read_vld)
    div_entry0_older <= 1'b1;
  else if(div_entry_write_en)
    div_entry0_older <= !div_entry0_older;
  else
    div_entry0_older <= div_entry0_older;
end




always @(posedge div_entry0_clk or negedge cpurst_b)
begin
  if(!cpurst_b)

    div_entry0_data[257:0] <= {1'b0, 1'b0,
                               64'b0, 64'hffffffffffffffff,
                               64'b1, 64'hffffffffffffffff};
  else if(cp0_iu_div_entry_disable_clr)

    div_entry0_data[257:0] <= {1'b0, 1'b0,
                               64'b0, 64'hffffffffffffffff,
                               64'b1, 64'hffffffffffffffff};
  else if(div_entry_write_en && div_entry0_older)
    div_entry0_data[257:0] <= div_entry_write_data[257:0];
  else
    div_entry0_data[257:0] <= div_entry0_data[257:0];
end

assign div_entry0_read_data[257:0] = div_entry0_data[257:0];




always @(posedge div_entry1_clk or negedge cpurst_b)
begin
  if(!cpurst_b)

    div_entry1_data[257:0] <= {1'b0, 1'b1,
                               64'b0, 64'h7fffffffffffffff,
                               64'b1, 64'h7fffffffffffffff};
  else if(cp0_iu_div_entry_disable_clr)

    div_entry1_data[257:0] <= {1'b0, 1'b1,
                               64'b0, 64'h7fffffffffffffff,
                               64'b1, 64'h7fffffffffffffff};
  else if(div_entry_write_en && !div_entry0_older)
    div_entry1_data[257:0] <= div_entry_write_data[257:0];
  else
    div_entry1_data[257:0] <= div_entry1_data[257:0];
end

assign div_entry1_read_data[257:0] = div_entry1_data[257:0];



endmodule