data/full_repos/permissive/493019833/test/testcase/firrtl/TopOfVisualizer/sbt/TopOfVisualizer.v
data/verilator_xmls/813e058b-fbc1-47aa-85d8-1ce68668ad52.xml
module TopOfVisualizer(
  input         clock,
  input         reset,
  input  [31:0] io_in1,
  input  [31:0] io_in2,
  input         io_select,
  output [31:0] io_out,
  output [31:0] io_memOut
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [31:0] myMem [0:15];
  wire  myMem__T_16_en;
  wire [3:0] myMem__T_16_addr;
  wire [31:0] myMem__T_16_data;
  wire [31:0] myMem__T_12_data;
  wire [3:0] myMem__T_12_addr;
  wire  myMem__T_12_mask;
  wire  myMem__T_12_en;
  wire [31:0] modA_io_in;
  wire [15:0] modA_io_out;
  reg [31:0] x;
  reg [31:0] y;
  wire  _T_14 = ~io_select;
  wire [31:0] _GEN_11 = {{16'd0}, modA_io_out};
  VizModA modA (
    .io_in(modA_io_in),
    .io_out(modA_io_out)
  );
  assign myMem__T_16_en = ~io_select;
  assign myMem__T_16_addr = io_in1[3:0];
  assign myMem__T_16_data = myMem[myMem__T_16_addr];
  assign myMem__T_12_data = io_in2;
  assign myMem__T_12_addr = io_in1[3:0];
  assign myMem__T_12_mask = 1'h1;
  assign myMem__T_12_en = io_select;
  assign io_out = y;
  assign io_memOut = myMem__T_16_data;
  assign modA_io_in = x;
  always @(posedge clock) begin
    if (myMem__T_12_en & myMem__T_12_mask) begin
      myMem[myMem__T_12_addr] <= myMem__T_12_data;
    end
    if (_T_14) begin
      x <= io_in2;
    end else if (io_select) begin
      x <= io_in1;
    end
    y <= _GEN_11 + io_in2;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    myMem[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  x = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  y = _RAND_2[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module TopOfVisualizer(
  input         clock,
  input         reset,
  input  [31:0] io_in1,
  input  [31:0] io_in2,
  input         io_select,
  output [31:0] io_out,
  output [31:0] io_memOut
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [31:0] myMem [0:15];
  wire  myMem__T_16_en;
  wire [3:0] myMem__T_16_addr;
  wire [31:0] myMem__T_16_data;
  wire [31:0] myMem__T_12_data;
  wire [3:0] myMem__T_12_addr;
  wire  myMem__T_12_mask;
  wire  myMem__T_12_en;
  wire [31:0] modA_io_in;
  wire [15:0] modA_io_out;
  reg [31:0] x;
  reg [31:0] y;
  wire  _T_14 = ~io_select;
  wire [31:0] _GEN_11 = {{16'd0}, modA_io_out};
  VizModA modA (
    .io_in(modA_io_in),
    .io_out(modA_io_out)
  );
  assign myMem__T_16_en = ~io_select;
  assign myMem__T_16_addr = io_in1[3:0];
  assign myMem__T_16_data = myMem[myMem__T_16_addr];
  assign myMem__T_12_data = io_in2;
  assign myMem__T_12_addr = io_in1[3:0];
  assign myMem__T_12_mask = 1'h1;
  assign myMem__T_12_en = io_select;
  assign io_out = y;
  assign io_memOut = myMem__T_16_data;
  assign modA_io_in = x;
  always @(posedge clock) begin
    if (myMem__T_12_en & myMem__T_12_mask) begin
      myMem[myMem__T_12_addr] <= myMem__T_12_data;
    end
    if (_T_14) begin
      x <= io_in2;
    end else if (io_select) begin
      x <= io_in1;
    end
    y <= _GEN_11 + io_in2;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    myMem[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  x = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  y = _RAND_2[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule