data/full_repos/permissive/423547971/FPGA Projects/VGA Projects/Pong pt2/timer.v
1: b'%Error: Cannot find file containing module: Projects/VGA\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.v\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.sv\n             Projects/VGA\n             Projects/VGA.v\n             Projects/VGA.sv\n             obj_dir/Projects/VGA\n             obj_dir/Projects/VGA.v\n             obj_dir/Projects/VGA.sv\n%Error: Cannot find file containing module: Projects/Pong\n%Error: Cannot find file containing module: pt2,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: pt2/timer.v\n%Error: Exiting due to 5 error(s)\n'
module timer(
    input clk,
    input reset,
    input timer_start, timer_tick,
    output timer_up
    );
    

    reg [6:0] timer_reg, timer_next;
    

    always @(posedge clk or posedge reset)
        if(reset)
            timer_reg <= 7'b1111111;
        else
            timer_reg <= timer_next;
    

    always @*
        if(timer_start)
            timer_next = 7'b1111111;
        else if((timer_tick) && (timer_reg != 0))
            timer_next = timer_reg - 1;
        else
            timer_next = timer_reg;
            

    assign timer_up = (timer_reg == 0);
    
endmodule
module timer(
    input clk,
    input reset,
    input timer_start, timer_tick,
    output timer_up
    );

    

    reg [6:0] timer_reg, timer_next;
    

    always @(posedge clk or posedge reset)
        if(reset)
            timer_reg <= 7'b1111111;
        else
            timer_reg <= timer_next;
    

    always @*
        if(timer_start)
            timer_next = 7'b1111111;
        else if((timer_tick) && (timer_reg != 0))
            timer_next = timer_reg - 1;
        else
            timer_next = timer_reg;
            

    assign timer_up = (timer_reg == 0);
    
endmodule