data/full_repos/permissive/411457613/Pyverilog/verilogcode/decimal_signed.v
data/verilator_xmls/f7770b10-4495-4580-896d-6b381fab515d.xml
module TOP(CLK, RST);
  input CLK, RST;
  reg [7:0] cnt;

  always @(posedge CLK or negedge RST) begin
    if(RST) begin
      cnt <= 'd0;
    end else begin
      cnt <= cnt + 1'sd1;
    end
  end

endmodule
module TOP(CLK, RST);

  input CLK, RST;
  reg [7:0] cnt;

  always @(posedge CLK or negedge RST) begin
    if(RST) begin
      cnt <= 'd0;
    end else begin
      cnt <= cnt + 1'sd1;
    end
  end

endmodule