data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v:119: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wb_dat_i\' generates 32 bits.\n                                                                                                  : ... In instance simple_gemac_wb\n         MIICOMMAND <= wb_dat_i;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v:146: Cannot find file containing module: \'eth_miim\'\n   eth_miim eth_miim\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_miim\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_miim.v\n             data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac,data/full_repos/permissive/447976230/eth_miim.sv\n             eth_miim\n             eth_miim.v\n             eth_miim.sv\n             obj_dir/eth_miim\n             obj_dir/eth_miim.v\n             obj_dir/eth_miim.sv\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v:172: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MIICOMMAND\' generates 3 bits.\n                                                                                                  : ... In instance simple_gemac_wb\n       8 : wb_dat_o <= MIICOMMAND;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v:173: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MIISTATUS\' generates 3 bits.\n                                                                                                  : ... In instance simple_gemac_wb\n       9 : wb_dat_o <= MIISTATUS;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/simple_gemac/simple_gemac_wb.v:174: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'MIIRX_DATA\' generates 16 bits.\n                                                                                                  : ... In instance simple_gemac_wb\n       10: wb_dat_o <= MIIRX_DATA;\n                    ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module wb_reg
  #(parameter ADDR=0,
    parameter DEFAULT=0,
    parameter WIDTH=32)
   (input clk, input rst, 
    input [5:0] adr, input wr_acc,
    input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);

   always @(posedge clk)
     if(rst)
       dat_o <= DEFAULT;
     else if(wr_acc & (adr == ADDR))
       dat_o <= dat_i[WIDTH-1:0];
   
endmodule
module wb_reg
  #(parameter ADDR=0,
    parameter DEFAULT=0,
    parameter WIDTH=32)
   (input clk, input rst, 
    input [5:0] adr, input wr_acc,
    input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);


   always @(posedge clk)
     if(rst)
       dat_o <= DEFAULT;
     else if(wr_acc & (adr == ADDR))
       dat_o <= dat_i[WIDTH-1:0];
   
endmodule