data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/wb_artemis_pcie_platform.v
1: b'%Error: data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl/wb_artemis_pcie_platform.v:65: Cannot find include file: project_defines.v\n`include "project_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/project_defines.v\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/project_defines.v.v\n             data/full_repos/permissive/48339973/artemis_pcie/slave/wb_artemis_pcie_platform/rtl,data/full_repos/permissive/48339973/project_defines.v.sv\n             project_defines.v\n             project_defines.v.v\n             project_defines.v.sv\n             obj_dir/project_defines.v\n             obj_dir/project_defines.v.v\n             obj_dir/project_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module wb_artemis_pcie_platform #(
  parameter           DATA_INGRESS_FIFO_DEPTH = 10,
  parameter           DATA_EGRESS_FIFO_DEPTH  = 6,
  parameter           CONTROL_FIFO_DEPTH = 7
) (
  input               clk,
  input               rst,
  output              o_sys_rst,




  input               i_wbs_we,
  input               i_wbs_cyc,
  input       [3:0]   i_wbs_sel,
  input       [31:0]  i_wbs_dat,
  input               i_wbs_stb,
  output  reg         o_wbs_ack,
  output  reg [31:0]  o_wbs_dat,
  input       [31:0]  i_wbs_adr,

  output      [31:0]  o_debug_data,

  output  reg         o_wbs_int,


  output              o_pcie_reset,
  output              o_pcie_per_fifo_sel,
  output              o_pcie_mem_fifo_sel,
  output              o_pcie_dma_fifo_sel,

  input               i_pcie_write_fin,
  input               i_pcie_read_fin,

  output      [31:0]  o_pcie_data_size,
  output      [31:0]  o_pcie_data_address,
  output              o_pcie_data_fifo_flg,
  output              o_pcie_data_read_flg,
  output              o_pcie_data_write_flg,

  input               i_pcie_interrupt_stb,
  input       [31:0]  i_pcie_interrupt_value,

  input               i_pcie_data_clk,
  output              o_pcie_ingress_fifo_rdy,
  input               i_pcie_ingress_fifo_act,
  output      [23:0]  o_pcie_ingress_fifo_size,
  input               i_pcie_ingress_fifo_stb,
  output      [31:0]  o_pcie_ingress_fifo_data,
  output              o_pcie_ingress_fifo_idle,

  output      [1:0]   o_pcie_egress_fifo_rdy,
  input       [1:0]   i_pcie_egress_fifo_act,
  output      [23:0]  o_pcie_egress_fifo_size,
  input               i_pcie_egress_fifo_stb,
  input       [31:0]  i_pcie_egress_fifo_data,


  output      [3:0]   o_sm_state,


  input               i_clk_100mhz_gtp_p,
  input               i_clk_100mhz_gtp_n,

  output              o_pcie_phy_tx_p,
  output              o_pcie_phy_tx_n,

  input               i_pcie_phy_rx_p,
  input               i_pcie_phy_rx_n,

  input               i_pcie_reset_n,
  output              o_pcie_wake_n
);


localparam  CONTROL             = 32'h00;
localparam  STATUS              = 32'h01;
localparam  CFG_READ_EXEC       = 32'h02;
localparam  CFG_SM_STATE        = 32'h03;
localparam  CTR_SM_STATE        = 32'h04;
localparam  INGRESS_COUNT       = 32'h05;
localparam  INGRESS_STATE       = 32'h06;
localparam  INGRESS_RI_COUNT    = 32'h07;
localparam  INGRESS_CI_COUNT    = 32'h08;
localparam  INGRESS_ADDR        = 32'h09;
localparam  INGRESS_CMPLT_COUNT = 32'h0A;
localparam  IH_STATE            = 32'h0B;
localparam  OH_STATE            = 32'h0C;
localparam  BRAM_NUM_READS      = 32'h0D;
localparam  LOCAL_BUFFER_SIZE   = 32'h0E;
localparam  DBG_ID_VALUE        = 32'h0F;
localparam  DBG_COMMAND_VALUE   = 32'h10;
localparam  DBG_COUNT_VALUE     = 32'h11;
localparam  DBG_ADDRESS_VALUE   = 32'h12;

localparam  CONTROL_BUFFER_SIZE = 2 ** CONTROL_FIFO_DEPTH;


reg               r_mem_2_ppfifo_stb;
reg               r_snk_en;


wire              w_out_en;
wire  [31:0]      w_out_status;
wire  [31:0]      w_out_address;
wire  [31:0]      w_out_data;
wire  [27:0]      w_out_data_count;
wire              w_master_ready;

wire              w_in_ready;
wire  [31:0]      w_in_command;
wire  [31:0]      w_in_address;
wire  [31:0]      w_in_data;
wire  [27:0]      w_in_data_count;
wire              w_out_ready;
wire              w_ih_reset;









wire                  w_lcl_mem_en;

wire      [31:0]      w_id_value;
wire      [31:0]      w_command_value;
wire      [31:0]      w_count_value;
wire      [31:0]      w_address_value;






artemis_pcie_controller #(
  .DATA_INGRESS_FIFO_DEPTH           (10                           ),
  .DATA_EGRESS_FIFO_DEPTH            (6                            ),
  .SERIAL_NUMBER                     (64'h000000000000C594         )
)api (
  .clk                               (clk                          ),
  .rst                               (rst                          ),
  .o_sys_rst                         (o_sys_rst                    ),


  .gtp_clk_p                         (i_clk_100mhz_gtp_p           ),
  .gtp_clk_n                         (i_clk_100mhz_gtp_n           ),

  .pci_exp_txp                       (o_pcie_phy_tx_p              ),
  .pci_exp_txn                       (o_pcie_phy_tx_n              ),
  .pci_exp_rxp                       (i_pcie_phy_rx_p              ),
  .pci_exp_rxn                       (i_pcie_phy_rx_n              ),


  .o_pcie_reset                      (o_pcie_reset                 ),
  .user_lnk_up                       (user_lnk_up                  ),
  .clk_62p5                          (clk_62p5                     ),
  .i_pcie_reset                      (!i_pcie_reset_n              ),


  .o_per_fifo_sel                    (o_pcie_per_fifo_sel          ),
  .o_mem_fifo_sel                    (o_pcie_mem_fifo_sel          ),
  .o_dma_fifo_sel                    (o_pcie_dma_fifo_sel          ),

  .i_write_fin                       (i_pcie_write_fin             ),
  .i_read_fin                        (i_pcie_read_fin              ),

  .i_usr_interrupt_stb               (i_pcie_interrupt             ),
  .i_usr_interrupt_value             (i_pcie_interrupt_value       ),

  .o_data_size                       (o_pcie_data_size             ),
  .o_data_address                    (o_pcie_data_address          ),
  .o_data_fifo_flg                   (o_pcie_data_fifo_flg         ),
  .o_data_read_flg                   (o_pcie_data_read_flg         ),
  .o_data_write_flg                  (o_pcie_data_write_flg        ),


  .i_data_clk                        (i_pcie_data_clk              ),
  .o_ingress_fifo_rdy                (o_pcie_ingress_fifo_rdy      ),
  .i_ingress_fifo_act                (i_pcie_ingress_fifo_act      ),
  .o_ingress_fifo_size               (o_pcie_ingress_fifo_size     ),
  .i_ingress_fifo_stb                (i_pcie_ingress_fifo_stb      ),
  .o_ingress_fifo_data               (o_pcie_ingress_fifo_data     ),
  .o_ingress_fifo_idle               (o_pcie_ingress_fifo_idle     ),


  .o_egress_fifo_rdy                 (o_pcie_egress_fifo_rdy       ),
  .i_egress_fifo_act                 (i_pcie_egress_fifo_act       ),
  .o_egress_fifo_size                (o_pcie_egress_fifo_size      ),
  .i_egress_fifo_stb                 (i_pcie_egress_fifo_stb       ),
  .i_egress_fifo_data                (i_pcie_egress_fifo_data      ),


  .cfg_turnoff_ok                    (1'b0                         ),
  .cfg_pm_wake                       (1'b0                         ),








  .rx_equalizer_ctrl                 (2'b11                        ),

  .tx_diff_ctrl                      (4'h9                         ),
  .tx_pre_emphasis                   (3'b00                        ),




  .o_sm_state                        (o_sm_state                   ),









  .cfg_err_ur                        (1'b0                         ),
  .cfg_err_cor                       (1'b0                         ),
  .cfg_err_ecrc                      (1'b0                         ),
  .cfg_err_cpl_timeout               (1'b0                         ),
  .cfg_err_cpl_abort                 (1'b0                         ),
  .cfg_err_posted                    (1'b0                         ),
  .cfg_err_locked                    (1'b0                         ),
  .cfg_err_tlp_cpl_header            (48'b0                        )

);


assign  o_pcie_wake_n = 1'b1;

always @ (posedge clk) begin



  if (rst) begin
    o_wbs_dat             <= 32'h0;
    o_wbs_ack             <= 0;
    o_wbs_int             <= 0;


    r_snk_en              <= 1;
  end
  else begin

    if (o_wbs_ack && ~i_wbs_stb)begin
      o_wbs_ack <= 0;
    end

    if (i_wbs_stb && i_wbs_cyc) begin

      if (!o_wbs_ack) begin
        if (i_wbs_we) begin

          case (i_wbs_adr)
            CONTROL: begin
              $display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);


              r_snk_en                            <=  i_wbs_dat[`CTRL_BIT_SINK_EN];
            end
            default: begin


            end
          endcase
          o_wbs_ack                                 <= 1;
        end
        else begin

          case (i_wbs_adr)
            CONTROL: begin
              o_wbs_dat <= 0;


              o_wbs_dat[`CTRL_BIT_SINK_EN]        <= r_snk_en;

            end
            STATUS: begin
              o_wbs_dat <= 0;





            end


            default: begin

            end
          endcase

            o_wbs_ack             <=  1;

        end
      end
    end
  end
end

endmodule
module wb_artemis_pcie_platform #(
  parameter           DATA_INGRESS_FIFO_DEPTH = 10,
  parameter           DATA_EGRESS_FIFO_DEPTH  = 6,
  parameter           CONTROL_FIFO_DEPTH = 7
) (
  input               clk,
  input               rst,
  output              o_sys_rst,




  input               i_wbs_we,
  input               i_wbs_cyc,
  input       [3:0]   i_wbs_sel,
  input       [31:0]  i_wbs_dat,
  input               i_wbs_stb,
  output  reg         o_wbs_ack,
  output  reg [31:0]  o_wbs_dat,
  input       [31:0]  i_wbs_adr,

  output      [31:0]  o_debug_data,

  output  reg         o_wbs_int,


  output              o_pcie_reset,
  output              o_pcie_per_fifo_sel,
  output              o_pcie_mem_fifo_sel,
  output              o_pcie_dma_fifo_sel,

  input               i_pcie_write_fin,
  input               i_pcie_read_fin,

  output      [31:0]  o_pcie_data_size,
  output      [31:0]  o_pcie_data_address,
  output              o_pcie_data_fifo_flg,
  output              o_pcie_data_read_flg,
  output              o_pcie_data_write_flg,

  input               i_pcie_interrupt_stb,
  input       [31:0]  i_pcie_interrupt_value,

  input               i_pcie_data_clk,
  output              o_pcie_ingress_fifo_rdy,
  input               i_pcie_ingress_fifo_act,
  output      [23:0]  o_pcie_ingress_fifo_size,
  input               i_pcie_ingress_fifo_stb,
  output      [31:0]  o_pcie_ingress_fifo_data,
  output              o_pcie_ingress_fifo_idle,

  output      [1:0]   o_pcie_egress_fifo_rdy,
  input       [1:0]   i_pcie_egress_fifo_act,
  output      [23:0]  o_pcie_egress_fifo_size,
  input               i_pcie_egress_fifo_stb,
  input       [31:0]  i_pcie_egress_fifo_data,


  output      [3:0]   o_sm_state,


  input               i_clk_100mhz_gtp_p,
  input               i_clk_100mhz_gtp_n,

  output              o_pcie_phy_tx_p,
  output              o_pcie_phy_tx_n,

  input               i_pcie_phy_rx_p,
  input               i_pcie_phy_rx_n,

  input               i_pcie_reset_n,
  output              o_pcie_wake_n
);



localparam  CONTROL             = 32'h00;
localparam  STATUS              = 32'h01;
localparam  CFG_READ_EXEC       = 32'h02;
localparam  CFG_SM_STATE        = 32'h03;
localparam  CTR_SM_STATE        = 32'h04;
localparam  INGRESS_COUNT       = 32'h05;
localparam  INGRESS_STATE       = 32'h06;
localparam  INGRESS_RI_COUNT    = 32'h07;
localparam  INGRESS_CI_COUNT    = 32'h08;
localparam  INGRESS_ADDR        = 32'h09;
localparam  INGRESS_CMPLT_COUNT = 32'h0A;
localparam  IH_STATE            = 32'h0B;
localparam  OH_STATE            = 32'h0C;
localparam  BRAM_NUM_READS      = 32'h0D;
localparam  LOCAL_BUFFER_SIZE   = 32'h0E;
localparam  DBG_ID_VALUE        = 32'h0F;
localparam  DBG_COMMAND_VALUE   = 32'h10;
localparam  DBG_COUNT_VALUE     = 32'h11;
localparam  DBG_ADDRESS_VALUE   = 32'h12;

localparam  CONTROL_BUFFER_SIZE = 2 ** CONTROL_FIFO_DEPTH;


reg               r_mem_2_ppfifo_stb;
reg               r_snk_en;


wire              w_out_en;
wire  [31:0]      w_out_status;
wire  [31:0]      w_out_address;
wire  [31:0]      w_out_data;
wire  [27:0]      w_out_data_count;
wire              w_master_ready;

wire              w_in_ready;
wire  [31:0]      w_in_command;
wire  [31:0]      w_in_address;
wire  [31:0]      w_in_data;
wire  [27:0]      w_in_data_count;
wire              w_out_ready;
wire              w_ih_reset;









wire                  w_lcl_mem_en;

wire      [31:0]      w_id_value;
wire      [31:0]      w_command_value;
wire      [31:0]      w_count_value;
wire      [31:0]      w_address_value;






artemis_pcie_controller #(
  .DATA_INGRESS_FIFO_DEPTH           (10                           ),
  .DATA_EGRESS_FIFO_DEPTH            (6                            ),
  .SERIAL_NUMBER                     (64'h000000000000C594         )
)api (
  .clk                               (clk                          ),
  .rst                               (rst                          ),
  .o_sys_rst                         (o_sys_rst                    ),


  .gtp_clk_p                         (i_clk_100mhz_gtp_p           ),
  .gtp_clk_n                         (i_clk_100mhz_gtp_n           ),

  .pci_exp_txp                       (o_pcie_phy_tx_p              ),
  .pci_exp_txn                       (o_pcie_phy_tx_n              ),
  .pci_exp_rxp                       (i_pcie_phy_rx_p              ),
  .pci_exp_rxn                       (i_pcie_phy_rx_n              ),


  .o_pcie_reset                      (o_pcie_reset                 ),
  .user_lnk_up                       (user_lnk_up                  ),
  .clk_62p5                          (clk_62p5                     ),
  .i_pcie_reset                      (!i_pcie_reset_n              ),


  .o_per_fifo_sel                    (o_pcie_per_fifo_sel          ),
  .o_mem_fifo_sel                    (o_pcie_mem_fifo_sel          ),
  .o_dma_fifo_sel                    (o_pcie_dma_fifo_sel          ),

  .i_write_fin                       (i_pcie_write_fin             ),
  .i_read_fin                        (i_pcie_read_fin              ),

  .i_usr_interrupt_stb               (i_pcie_interrupt             ),
  .i_usr_interrupt_value             (i_pcie_interrupt_value       ),

  .o_data_size                       (o_pcie_data_size             ),
  .o_data_address                    (o_pcie_data_address          ),
  .o_data_fifo_flg                   (o_pcie_data_fifo_flg         ),
  .o_data_read_flg                   (o_pcie_data_read_flg         ),
  .o_data_write_flg                  (o_pcie_data_write_flg        ),


  .i_data_clk                        (i_pcie_data_clk              ),
  .o_ingress_fifo_rdy                (o_pcie_ingress_fifo_rdy      ),
  .i_ingress_fifo_act                (i_pcie_ingress_fifo_act      ),
  .o_ingress_fifo_size               (o_pcie_ingress_fifo_size     ),
  .i_ingress_fifo_stb                (i_pcie_ingress_fifo_stb      ),
  .o_ingress_fifo_data               (o_pcie_ingress_fifo_data     ),
  .o_ingress_fifo_idle               (o_pcie_ingress_fifo_idle     ),


  .o_egress_fifo_rdy                 (o_pcie_egress_fifo_rdy       ),
  .i_egress_fifo_act                 (i_pcie_egress_fifo_act       ),
  .o_egress_fifo_size                (o_pcie_egress_fifo_size      ),
  .i_egress_fifo_stb                 (i_pcie_egress_fifo_stb       ),
  .i_egress_fifo_data                (i_pcie_egress_fifo_data      ),


  .cfg_turnoff_ok                    (1'b0                         ),
  .cfg_pm_wake                       (1'b0                         ),








  .rx_equalizer_ctrl                 (2'b11                        ),

  .tx_diff_ctrl                      (4'h9                         ),
  .tx_pre_emphasis                   (3'b00                        ),




  .o_sm_state                        (o_sm_state                   ),









  .cfg_err_ur                        (1'b0                         ),
  .cfg_err_cor                       (1'b0                         ),
  .cfg_err_ecrc                      (1'b0                         ),
  .cfg_err_cpl_timeout               (1'b0                         ),
  .cfg_err_cpl_abort                 (1'b0                         ),
  .cfg_err_posted                    (1'b0                         ),
  .cfg_err_locked                    (1'b0                         ),
  .cfg_err_tlp_cpl_header            (48'b0                        )

);


assign  o_pcie_wake_n = 1'b1;

always @ (posedge clk) begin



  if (rst) begin
    o_wbs_dat             <= 32'h0;
    o_wbs_ack             <= 0;
    o_wbs_int             <= 0;


    r_snk_en              <= 1;
  end
  else begin

    if (o_wbs_ack && ~i_wbs_stb)begin
      o_wbs_ack <= 0;
    end

    if (i_wbs_stb && i_wbs_cyc) begin

      if (!o_wbs_ack) begin
        if (i_wbs_we) begin

          case (i_wbs_adr)
            CONTROL: begin
              $display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);


              r_snk_en                            <=  i_wbs_dat[`CTRL_BIT_SINK_EN];
            end
            default: begin


            end
          endcase
          o_wbs_ack                                 <= 1;
        end
        else begin

          case (i_wbs_adr)
            CONTROL: begin
              o_wbs_dat <= 0;


              o_wbs_dat[`CTRL_BIT_SINK_EN]        <= r_snk_en;

            end
            STATUS: begin
              o_wbs_dat <= 0;





            end


            default: begin

            end
          endcase

            o_wbs_ack             <=  1;

        end
      end
    end
  end
end

endmodule