data/full_repos/permissive/456762006/rtl/ImageCounter.v
data/verilator_xmls/d798a12c-7455-4185-9b73-d6b86c742d0a.xml
module ImageCounter #
(
    parameter IW = 640,
    parameter IH = 480,
    parameter DW = 8,
    parameter IW_DW = 12,
    parameter IH_DW = 12
)
(clk,arstn,vsync,hsync,dvalid,line_counter,column_counter);


input clk;
input arstn;
input vsync;
input hsync;
input dvalid;

output reg [IH_DW-1:0]line_counter;
output reg [IW_DW-1:0]column_counter;


reg rst_all;
always@(posedge clk or negedge arstn)
    begin
        if(~arstn)
            rst_all <= 1'b1;
        else
        begin
            if(vsync == 1'b1)
                rst_all <= 1'b1;
            else
                rst_all <= 1'b0;
        end
    end
    
wire dvalid_rise;
reg dvalid_r;
always@(posedge clk or negedge arstn)
    begin
        if(~arstn)
            dvalid_r <= 1'b0;
        else
            dvalid_r <= dvalid;
    end

assign dvalid_rise = (~dvalid_r) & dvalid;



always@(posedge clk)
    begin
        if(rst_all)
            line_counter[IH_DW-1:0] <= {IH_DW{1'b0}};
        else
            if(dvalid_rise)
            begin
                line_counter[IH_DW-1:0] <= line_counter[IH_DW-1:0] + {{IH_DW-1{1'b0}},1'b1};
            end
    end


always@(posedge clk)
    begin
        if(rst_all)
            line_counter[IW_DW-1:0]<= {IW_DW{1'b0}};
        else
            begin
                if(dvalid_rise)
                    column_counter[IW_DW-1:0] <= {{IW_DW-1{1'b0}},1'b1};
                else
                    begin
                        if(dvalid)
                            column_counter[IW_DW-1:0] <= column_counter[IW_DW-1:0] + {{IW_DW-1{1'b0}},1'b1};
                    end 
            end
    end
endmodule
module ImageCounter #
(
    parameter IW = 640,
    parameter IH = 480,
    parameter DW = 8,
    parameter IW_DW = 12,
    parameter IH_DW = 12
)
(clk,arstn,vsync,hsync,dvalid,line_counter,column_counter);



input clk;
input arstn;
input vsync;
input hsync;
input dvalid;

output reg [IH_DW-1:0]line_counter;
output reg [IW_DW-1:0]column_counter;


reg rst_all;
always@(posedge clk or negedge arstn)
    begin
        if(~arstn)
            rst_all <= 1'b1;
        else
        begin
            if(vsync == 1'b1)
                rst_all <= 1'b1;
            else
                rst_all <= 1'b0;
        end
    end
    
wire dvalid_rise;
reg dvalid_r;
always@(posedge clk or negedge arstn)
    begin
        if(~arstn)
            dvalid_r <= 1'b0;
        else
            dvalid_r <= dvalid;
    end

assign dvalid_rise = (~dvalid_r) & dvalid;



always@(posedge clk)
    begin
        if(rst_all)
            line_counter[IH_DW-1:0] <= {IH_DW{1'b0}};
        else
            if(dvalid_rise)
            begin
                line_counter[IH_DW-1:0] <= line_counter[IH_DW-1:0] + {{IH_DW-1{1'b0}},1'b1};
            end
    end


always@(posedge clk)
    begin
        if(rst_all)
            line_counter[IW_DW-1:0]<= {IW_DW{1'b0}};
        else
            begin
                if(dvalid_rise)
                    column_counter[IW_DW-1:0] <= {{IW_DW-1{1'b0}},1'b1};
                else
                    begin
                        if(dvalid)
                            column_counter[IW_DW-1:0] <= column_counter[IW_DW-1:0] + {{IW_DW-1{1'b0}},1'b1};
                    end 
            end
    end
endmodule