data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_reg_mux.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_reg_mux.v:13: Cannot find include file: tcu_parameter.vh\n    `include "tcu_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.sv\n             tcu_parameter.vh\n             tcu_parameter.vh.v\n             tcu_parameter.vh.sv\n             obj_dir/tcu_parameter.vh\n             obj_dir/tcu_parameter.vh.v\n             obj_dir/tcu_parameter.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module tcu_reg_mux #(
    `include "tcu_parameter.vh"
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                    [2:0] reg_in1_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] reg_in1_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in1_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in1_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in1_rdata_o,
    output wire                          reg_in1_stall_o,



    input  wire                    [2:0] reg_in2_en_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in2_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_rdata_o,
    output wire                          reg_in2_stall_o,



    input  wire                    [2:0] reg_in3_en_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in3_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_rdata_o,
    output wire                          reg_in3_stall_o,



    output wire                    [2:0] reg_out_en_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_out_wben_o,
    output wire  [TCU_REG_ADDR_SIZE-1:0] reg_out_addr_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_out_wdata_o,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_out_rdata_i,
    input  wire                          reg_out_stall_i
);

    integer i;


`ifdef REGISTERED

    reg                   [2:0] r_reg_out_en, rin_reg_out_en;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_out_wben, rin_reg_out_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] r_reg_out_addr, rin_reg_out_addr;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_out_wdata, rin_reg_out_wdata;





    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_reg_out_en    <= 3'h0;
            r_reg_out_wben  <= {TCU_REG_DATA_SIZE{1'b0}};
            r_reg_out_addr  <= {TCU_REG_ADDR_SIZE{1'b0}};
            r_reg_out_wdata <= {TCU_REG_DATA_SIZE{1'b0}};
        end else begin
            r_reg_out_en    <= rin_reg_out_en;
            r_reg_out_wben  <= rin_reg_out_wben;
            r_reg_out_addr  <= rin_reg_out_addr;
            r_reg_out_wdata <= rin_reg_out_wdata;
        end
    end


    always @* begin
        rin_reg_out_en    = 3'h0;
        rin_reg_out_wben  = {TCU_REG_DATA_SIZE{1'b0}};
        rin_reg_out_addr  = r_reg_out_addr;
        rin_reg_out_wdata = r_reg_out_wdata;


        if (reg_in1_en_i[0]) begin
            rin_reg_out_en = reg_in1_en_i;
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                rin_reg_out_wben[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = {TCU_REG_BSEL_SIZE{reg_in1_wben_i[i]}};
            end
            rin_reg_out_addr = reg_in1_addr_i;
            rin_reg_out_wdata = reg_in1_wdata_i;
        end

        else if (reg_in2_en_i[0]) begin
            rin_reg_out_en = reg_in2_en_i;
            rin_reg_out_wben = reg_in2_wben_i;
            rin_reg_out_addr = reg_in2_addr_i;
            rin_reg_out_wdata = reg_in2_wdata_i;
        end

        else if (reg_in3_en_i[0]) begin
            rin_reg_out_en = reg_in3_en_i;
            rin_reg_out_wben = reg_in3_wben_i;
            rin_reg_out_addr = reg_in3_addr_i;
            rin_reg_out_wdata = reg_in3_wdata_i;
        end
    end

    assign reg_out_en_o = r_reg_out_en;
    assign reg_out_wben_o = r_reg_out_wben;
    assign reg_out_addr_o = r_reg_out_addr;
    assign reg_out_wdata_o = r_reg_out_wdata;

    assign reg_in1_rdata_o = reg_out_rdata_i;

    assign reg_in1_stall_o = 1'b0;

    assign reg_in2_rdata_o = reg_out_rdata_i;

    assign reg_in2_stall_o = reg_in1_en_i;

    assign reg_in3_rdata_o = reg_out_rdata_i;

    assign reg_in3_stall_o = reg_in1_en_i || reg_in2_en_i;



`else

    reg                   [2:0] rin_reg_out_en;
    reg [TCU_REG_DATA_SIZE-1:0] rin_reg_out_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] rin_reg_out_addr;
    reg [TCU_REG_DATA_SIZE-1:0] rin_reg_out_wdata;

    always @* begin
        rin_reg_out_en    = 3'h0;
        rin_reg_out_wben  = {TCU_REG_DATA_SIZE{1'b0}};
        rin_reg_out_addr  = {TCU_REG_ADDR_SIZE{1'b0}};
        rin_reg_out_wdata = {TCU_REG_DATA_SIZE{1'b0}};


        if (reg_in1_en_i[0]) begin
            rin_reg_out_en = reg_in1_en_i;
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                rin_reg_out_wben[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = {TCU_REG_BSEL_SIZE{reg_in1_wben_i[i]}};
            end
            rin_reg_out_addr = reg_in1_addr_i;
            rin_reg_out_wdata = reg_in1_wdata_i;
        end

        else if (reg_in2_en_i[0]) begin
            rin_reg_out_en = reg_in2_en_i;
            rin_reg_out_wben = reg_in2_wben_i;
            rin_reg_out_addr = reg_in2_addr_i;
            rin_reg_out_wdata = reg_in2_wdata_i;
        end

        else if (reg_in3_en_i[0]) begin
            rin_reg_out_en = reg_in3_en_i;
            rin_reg_out_wben = reg_in3_wben_i;
            rin_reg_out_addr = reg_in3_addr_i;
            rin_reg_out_wdata = reg_in3_wdata_i;
        end
    end

    assign reg_out_en_o = rin_reg_out_en;
    assign reg_out_wben_o = rin_reg_out_wben;
    assign reg_out_addr_o = rin_reg_out_addr;
    assign reg_out_wdata_o = rin_reg_out_wdata;

    assign reg_in1_rdata_o = reg_out_rdata_i;

    assign reg_in1_stall_o = 1'b0;

    assign reg_in2_rdata_o = reg_out_rdata_i;

    assign reg_in2_stall_o = reg_in1_en_i;

    assign reg_in3_rdata_o = reg_out_rdata_i;

    assign reg_in3_stall_o = reg_in1_en_i || reg_in2_en_i;


`endif

endmodule
module tcu_reg_mux #(
    `include "tcu_parameter.vh"
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    input  wire                    [2:0] reg_in1_en_i,
    input  wire  [TCU_REG_BSEL_SIZE-1:0] reg_in1_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in1_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in1_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in1_rdata_o,
    output wire                          reg_in1_stall_o,



    input  wire                    [2:0] reg_in2_en_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in2_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in2_rdata_o,
    output wire                          reg_in2_stall_o,



    input  wire                    [2:0] reg_in3_en_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_wben_i,
    input  wire  [TCU_REG_ADDR_SIZE-1:0] reg_in3_addr_i,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_wdata_i,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_in3_rdata_o,
    output wire                          reg_in3_stall_o,



    output wire                    [2:0] reg_out_en_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_out_wben_o,
    output wire  [TCU_REG_ADDR_SIZE-1:0] reg_out_addr_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] reg_out_wdata_o,
    input  wire  [TCU_REG_DATA_SIZE-1:0] reg_out_rdata_i,
    input  wire                          reg_out_stall_i
);


    integer i;


`ifdef REGISTERED

    reg                   [2:0] r_reg_out_en, rin_reg_out_en;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_out_wben, rin_reg_out_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] r_reg_out_addr, rin_reg_out_addr;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_out_wdata, rin_reg_out_wdata;





    always @(posedge clk_i or negedge reset_n_i) begin
        if (reset_n_i == 1'b0) begin
            r_reg_out_en    <= 3'h0;
            r_reg_out_wben  <= {TCU_REG_DATA_SIZE{1'b0}};
            r_reg_out_addr  <= {TCU_REG_ADDR_SIZE{1'b0}};
            r_reg_out_wdata <= {TCU_REG_DATA_SIZE{1'b0}};
        end else begin
            r_reg_out_en    <= rin_reg_out_en;
            r_reg_out_wben  <= rin_reg_out_wben;
            r_reg_out_addr  <= rin_reg_out_addr;
            r_reg_out_wdata <= rin_reg_out_wdata;
        end
    end


    always @* begin
        rin_reg_out_en    = 3'h0;
        rin_reg_out_wben  = {TCU_REG_DATA_SIZE{1'b0}};
        rin_reg_out_addr  = r_reg_out_addr;
        rin_reg_out_wdata = r_reg_out_wdata;


        if (reg_in1_en_i[0]) begin
            rin_reg_out_en = reg_in1_en_i;
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                rin_reg_out_wben[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = {TCU_REG_BSEL_SIZE{reg_in1_wben_i[i]}};
            end
            rin_reg_out_addr = reg_in1_addr_i;
            rin_reg_out_wdata = reg_in1_wdata_i;
        end

        else if (reg_in2_en_i[0]) begin
            rin_reg_out_en = reg_in2_en_i;
            rin_reg_out_wben = reg_in2_wben_i;
            rin_reg_out_addr = reg_in2_addr_i;
            rin_reg_out_wdata = reg_in2_wdata_i;
        end

        else if (reg_in3_en_i[0]) begin
            rin_reg_out_en = reg_in3_en_i;
            rin_reg_out_wben = reg_in3_wben_i;
            rin_reg_out_addr = reg_in3_addr_i;
            rin_reg_out_wdata = reg_in3_wdata_i;
        end
    end

    assign reg_out_en_o = r_reg_out_en;
    assign reg_out_wben_o = r_reg_out_wben;
    assign reg_out_addr_o = r_reg_out_addr;
    assign reg_out_wdata_o = r_reg_out_wdata;

    assign reg_in1_rdata_o = reg_out_rdata_i;

    assign reg_in1_stall_o = 1'b0;

    assign reg_in2_rdata_o = reg_out_rdata_i;

    assign reg_in2_stall_o = reg_in1_en_i;

    assign reg_in3_rdata_o = reg_out_rdata_i;

    assign reg_in3_stall_o = reg_in1_en_i || reg_in2_en_i;



`else

    reg                   [2:0] rin_reg_out_en;
    reg [TCU_REG_DATA_SIZE-1:0] rin_reg_out_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] rin_reg_out_addr;
    reg [TCU_REG_DATA_SIZE-1:0] rin_reg_out_wdata;

    always @* begin
        rin_reg_out_en    = 3'h0;
        rin_reg_out_wben  = {TCU_REG_DATA_SIZE{1'b0}};
        rin_reg_out_addr  = {TCU_REG_ADDR_SIZE{1'b0}};
        rin_reg_out_wdata = {TCU_REG_DATA_SIZE{1'b0}};


        if (reg_in1_en_i[0]) begin
            rin_reg_out_en = reg_in1_en_i;
            for (i=0; i<TCU_REG_BSEL_SIZE; i=i+1) begin
                rin_reg_out_wben[i*TCU_REG_BSEL_SIZE +: TCU_REG_BSEL_SIZE] = {TCU_REG_BSEL_SIZE{reg_in1_wben_i[i]}};
            end
            rin_reg_out_addr = reg_in1_addr_i;
            rin_reg_out_wdata = reg_in1_wdata_i;
        end

        else if (reg_in2_en_i[0]) begin
            rin_reg_out_en = reg_in2_en_i;
            rin_reg_out_wben = reg_in2_wben_i;
            rin_reg_out_addr = reg_in2_addr_i;
            rin_reg_out_wdata = reg_in2_wdata_i;
        end

        else if (reg_in3_en_i[0]) begin
            rin_reg_out_en = reg_in3_en_i;
            rin_reg_out_wben = reg_in3_wben_i;
            rin_reg_out_addr = reg_in3_addr_i;
            rin_reg_out_wdata = reg_in3_wdata_i;
        end
    end

    assign reg_out_en_o = rin_reg_out_en;
    assign reg_out_wben_o = rin_reg_out_wben;
    assign reg_out_addr_o = rin_reg_out_addr;
    assign reg_out_wdata_o = rin_reg_out_wdata;

    assign reg_in1_rdata_o = reg_out_rdata_i;

    assign reg_in1_stall_o = 1'b0;

    assign reg_in2_rdata_o = reg_out_rdata_i;

    assign reg_in2_stall_o = reg_in1_en_i;

    assign reg_in3_rdata_o = reg_out_rdata_i;

    assign reg_in3_stall_o = reg_in1_en_i || reg_in2_en_i;


`endif

endmodule