data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_dummy_instr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_dummy_instr.v:49: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                           : ... In instance ibex_dummy_instr\n   dummy_instr_seed_q <= 1\'sb0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_dummy_instr.v:52: Cannot find file containing module: \'prim_lfsr\'\n prim_lfsr #(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_lfsr\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_lfsr.v\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_lfsr.sv\n             prim_lfsr\n             prim_lfsr.v\n             prim_lfsr.sv\n             obj_dir/prim_lfsr\n             obj_dir/prim_lfsr.v\n             obj_dir/prim_lfsr.sv\n%Warning-WIDTH: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_dummy_instr.v:78: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                           : ... In instance ibex_dummy_instr\n   dummy_cnt_q <= 1\'sb0;\n               ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
function automatic [16:0] sv2v_cast_B5B52;
		input reg [16:0] inp;
		sv2v_cast_B5B52 = inp;
	endfunction
function automatic [16:0] sv2v_cast_B5B52;

		input reg [16:0] inp;
		sv2v_cast_B5B52 = inp;
	endfunction