data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:61: Cannot find file containing module: 'and_cell'\n  and_cell gate1 (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.v\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.sv\n             and_cell\n             and_cell.v\n             and_cell.sv\n             obj_dir/and_cell\n             obj_dir/and_cell.v\n             obj_dir/and_cell.sv\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:64: Cannot find file containing module: 'or_cell'\n  or_cell gate2 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:67: Cannot find file containing module: 'xor_cell'\n  xor_cell gate3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:70: Cannot find file containing module: 'nand_cell'\n  nand_cell gate4 (\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:73: Cannot find file containing module: 'not_cell'\n  not_cell gate5 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:76: Cannot find file containing module: 'buffer_cell'\n  buffer_cell gate6 (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:79: Cannot find file containing module: 'mux_cell'\n  mux_cell mux1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:82: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:88: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop2 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:94: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:100: Cannot find file containing module: 'mux_cell'\n  mux_cell mux2 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:106: Cannot find file containing module: 'not_cell'\n  not_cell gate7 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:110: Cannot find file containing module: 'mux_cell'\n  mux_cell mux3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:116: Cannot find file containing module: 'mux_cell'\n  mux_cell mux4 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:122: Cannot find file containing module: 'mux_cell'\n  mux_cell mux5 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:128: Cannot find file containing module: 'mux_cell'\n  mux_cell mux6 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:134: Cannot find file containing module: 'mux_cell'\n  mux_cell mux7 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:140: Cannot find file containing module: 'mux_cell'\n  mux_cell mux8 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:146: Cannot find file containing module: 'mux_cell'\n  mux_cell mux9 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:152: Cannot find file containing module: 'mux_cell'\n  mux_cell mux10 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:158: Cannot find file containing module: 'mux_cell'\n  mux_cell mux11 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:164: Cannot find file containing module: 'mux_cell'\n  mux_cell mux12 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:169: Cannot find file containing module: 'mux_cell'\n  mux_cell mux13 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:175: Cannot find file containing module: 'mux_cell'\n  mux_cell mux14 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:181: Cannot find file containing module: 'mux_cell'\n  mux_cell mux15 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:187: Cannot find file containing module: 'mux_cell'\n  mux_cell mux16 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:193: Cannot find file containing module: 'mux_cell'\n  mux_cell mux17 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:199: Cannot find file containing module: 'mux_cell'\n  mux_cell mux18 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:205: Cannot find file containing module: 'mux_cell'\n  mux_cell mux19 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:211: Cannot find file containing module: 'mux_cell'\n  mux_cell mux20 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:217: Cannot find file containing module: 'mux_cell'\n  mux_cell mux22 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:223: Cannot find file containing module: 'mux_cell'\n  mux_cell mux21 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341359404107432531.v:229: Cannot find file containing module: 'mux_cell'\n  mux_cell mux23 (\n  ^~~~~~~~\n%Error: Exiting due to 33 error(s)\n"
module user_module_341359404107432531(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = 1'b0;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10 = 1'b0;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19 = 1'b0;
  wire net20;
  wire net21;
  wire net22 = 1'b0;
  wire net23 = 1'b1;
  wire net24;
  wire net25;
  wire net26 = 1'b0;
  wire net27 = 1'b1;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33 = 1'b0;
  wire net34;
  wire net35;
  wire net36;
  wire net37 = 1'b1;
  wire net38;
  wire net39;
  wire net40;
  wire net41;
  wire net42 = 1'b1;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;
  assign io_out[6] = net8;
  assign io_out[7] = net9;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net13),
    .clk (net1),
    .q (net14),
    .notq (net13)
  );
  dff_cell flipflop2 (
    .d (net15),
    .clk (net13),
    .q (net16),
    .notq (net15)
  );
  dff_cell flipflop3 (
    .d (net17),
    .clk (net15),
    .q (net18),
    .notq (net17)
  );
  mux_cell mux2 (
    .a (net19),
    .b (net20),
    .sel (net18),
    .out (net9)
  );
  not_cell gate7 (
    .in (net14),
    .out (net20)
  );
  mux_cell mux3 (
    .a (net21),
    .b (net20),
    .sel (net18),
    .out (net8)
  );
  mux_cell mux4 (
    .a (net22),
    .b (net23),
    .sel (net14),
    .out (net24)
  );
  mux_cell mux5 (
    .a (net23),
    .b (net22),
    .sel (net14),
    .out (net25)
  );
  mux_cell mux6 (
    .a (net25),
    .b (net24),
    .sel (net16),
    .out (net21)
  );
  mux_cell mux7 (
    .a (net26),
    .b (net27),
    .sel (net14),
    .out (net28)
  );
  mux_cell mux8 (
    .a (net27),
    .b (net26),
    .sel (net14),
    .out (net29)
  );
  mux_cell mux9 (
    .a (net28),
    .b (net29),
    .sel (net16),
    .out (net30)
  );
  mux_cell mux10 (
    .a (net23),
    .b (net22),
    .sel (net16),
    .out (net31)
  );
  mux_cell mux11 (
    .a (net30),
    .b (net31),
    .sel (net18),
    .out (net7)
  );
  mux_cell mux12 (
    .a (net32),
    .sel (net18),
    .out (net6)
  );
  mux_cell mux13 (
    .a (net33),
    .b (net34),
    .sel (net16),
    .out (net32)
  );
  mux_cell mux14 (
    .a (net27),
    .b (net33),
    .sel (net14),
    .out (net34)
  );
  mux_cell mux15 (
    .a (net35),
    .b (net36),
    .sel (net18),
    .out (net5)
  );
  mux_cell mux16 (
    .a (net37),
    .b (net38),
    .sel (net16),
    .out (net35)
  );
  mux_cell mux17 (
    .a (net33),
    .b (net39),
    .sel (net16),
    .out (net36)
  );
  mux_cell mux18 (
    .a (net33),
    .b (net37),
    .sel (net14),
    .out (net38)
  );
  mux_cell mux19 (
    .a (net37),
    .b (net33),
    .sel (net14),
    .out (net39)
  );
  mux_cell mux20 (
    .a (net33),
    .b (net37),
    .sel (net14),
    .out (net40)
  );
  mux_cell mux22 (
    .a (net33),
    .b (net40),
    .sel (net16),
    .out (net4)
  );
  mux_cell mux21 (
    .a (net37),
    .b (net41),
    .sel (net16),
    .out (net3)
  );
  mux_cell mux23 (
    .a (net42),
    .b (net2),
    .sel (net14),
    .out (net41)
  );
endmodule
module user_module_341359404107432531(
  input [7:0] io_in,
  output [7:0] io_out
);

  wire net1 = io_in[0];
  wire net2 = 1'b0;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10 = 1'b0;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19 = 1'b0;
  wire net20;
  wire net21;
  wire net22 = 1'b0;
  wire net23 = 1'b1;
  wire net24;
  wire net25;
  wire net26 = 1'b0;
  wire net27 = 1'b1;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33 = 1'b0;
  wire net34;
  wire net35;
  wire net36;
  wire net37 = 1'b1;
  wire net38;
  wire net39;
  wire net40;
  wire net41;
  wire net42 = 1'b1;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;
  assign io_out[6] = net8;
  assign io_out[7] = net9;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net13),
    .clk (net1),
    .q (net14),
    .notq (net13)
  );
  dff_cell flipflop2 (
    .d (net15),
    .clk (net13),
    .q (net16),
    .notq (net15)
  );
  dff_cell flipflop3 (
    .d (net17),
    .clk (net15),
    .q (net18),
    .notq (net17)
  );
  mux_cell mux2 (
    .a (net19),
    .b (net20),
    .sel (net18),
    .out (net9)
  );
  not_cell gate7 (
    .in (net14),
    .out (net20)
  );
  mux_cell mux3 (
    .a (net21),
    .b (net20),
    .sel (net18),
    .out (net8)
  );
  mux_cell mux4 (
    .a (net22),
    .b (net23),
    .sel (net14),
    .out (net24)
  );
  mux_cell mux5 (
    .a (net23),
    .b (net22),
    .sel (net14),
    .out (net25)
  );
  mux_cell mux6 (
    .a (net25),
    .b (net24),
    .sel (net16),
    .out (net21)
  );
  mux_cell mux7 (
    .a (net26),
    .b (net27),
    .sel (net14),
    .out (net28)
  );
  mux_cell mux8 (
    .a (net27),
    .b (net26),
    .sel (net14),
    .out (net29)
  );
  mux_cell mux9 (
    .a (net28),
    .b (net29),
    .sel (net16),
    .out (net30)
  );
  mux_cell mux10 (
    .a (net23),
    .b (net22),
    .sel (net16),
    .out (net31)
  );
  mux_cell mux11 (
    .a (net30),
    .b (net31),
    .sel (net18),
    .out (net7)
  );
  mux_cell mux12 (
    .a (net32),
    .sel (net18),
    .out (net6)
  );
  mux_cell mux13 (
    .a (net33),
    .b (net34),
    .sel (net16),
    .out (net32)
  );
  mux_cell mux14 (
    .a (net27),
    .b (net33),
    .sel (net14),
    .out (net34)
  );
  mux_cell mux15 (
    .a (net35),
    .b (net36),
    .sel (net18),
    .out (net5)
  );
  mux_cell mux16 (
    .a (net37),
    .b (net38),
    .sel (net16),
    .out (net35)
  );
  mux_cell mux17 (
    .a (net33),
    .b (net39),
    .sel (net16),
    .out (net36)
  );
  mux_cell mux18 (
    .a (net33),
    .b (net37),
    .sel (net14),
    .out (net38)
  );
  mux_cell mux19 (
    .a (net37),
    .b (net33),
    .sel (net14),
    .out (net39)
  );
  mux_cell mux20 (
    .a (net33),
    .b (net37),
    .sel (net14),
    .out (net40)
  );
  mux_cell mux22 (
    .a (net33),
    .b (net40),
    .sel (net16),
    .out (net4)
  );
  mux_cell mux21 (
    .a (net37),
    .b (net41),
    .sel (net16),
    .out (net3)
  );
  mux_cell mux23 (
    .a (net42),
    .b (net2),
    .sel (net14),
    .out (net41)
  );
endmodule