data/full_repos/permissive/46989236/fifo/queue_tb.v
1: b'%Error: data/full_repos/permissive/46989236/fifo/queue_tb.v:10: Cannot find include file: attributes.v\n`include "attributes.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46989236/fifo,data/full_repos/permissive/46989236/attributes.v\n             data/full_repos/permissive/46989236/fifo,data/full_repos/permissive/46989236/attributes.v.v\n             data/full_repos/permissive/46989236/fifo,data/full_repos/permissive/46989236/attributes.v.sv\n             attributes.v\n             attributes.v.v\n             attributes.v.sv\n             obj_dir/attributes.v\n             obj_dir/attributes.v.v\n             obj_dir/attributes.v.sv\n%Error: data/full_repos/permissive/46989236/fifo/queue_tb.v:3: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1:0]d_in;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/fifo/queue_tb.v:4: Define or directive not defined: \'`INSTR_WIDTH\'\nwire [`INSTR_WIDTH-1:0]d_out;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/46989236/fifo/queue_tb.v:11: Unsupported or unknown PLI call: $monitor\n$monitor("flush=%b,put=%b,d_in=%b,get=%b,d_out=%b,empty=%b,full=%b",flush,put,d_in,get,d_out,empty,full);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46989236/fifo/queue_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 clk <= !clk;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46989236/fifo/queue_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#2 put <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/fifo/queue_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#2 put <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46989236/fifo/queue_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2 get <= 1\'b0;\n^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module queue_tb;
reg put,get,clk,flush;
reg [`INSTR_WIDTH-1:0]d_in;
wire [`INSTR_WIDTH-1:0]d_out;
wire empty,full;


initial
begin
`include "attributes.v"
$monitor("flush=%b,put=%b,d_in=%b,get=%b,d_out=%b,empty=%b,full=%b",flush,put,d_in,get,d_out,empty,full);
flush = 1'b1;
d_in = 12'd1024;
put = 1'b1;
d_in = 12'd2013;
end

always begin
#5 clk <= !clk;
d_in <= d_in + 12'd1;
put <= 1'b1;
#2 put <= 1'b0;
put <= 1'b1;
#2 put <= 1'b0;
get <= 1'b1;
#2 get <= 1'b0;
if (d_in == 12'd10)
$finish;
end
queue q(
.put (put),
.get (get),
.clk (clk),
.flush (flush),
.d_in (d_in),
.d_out (d_out),
.empty (empty),
.full (full)
);
endmodule
module queue_tb;

reg put,get,clk,flush;
reg [`INSTR_WIDTH-1:0]d_in;
wire [`INSTR_WIDTH-1:0]d_out;
wire empty,full;


initial
begin
`include "attributes.v"
$monitor("flush=%b,put=%b,d_in=%b,get=%b,d_out=%b,empty=%b,full=%b",flush,put,d_in,get,d_out,empty,full);
flush = 1'b1;
d_in = 12'd1024;
put = 1'b1;
d_in = 12'd2013;
end

always begin
#5 clk <= !clk;
d_in <= d_in + 12'd1;
put <= 1'b1;
#2 put <= 1'b0;
put <= 1'b1;
#2 put <= 1'b0;
get <= 1'b1;
#2 get <= 1'b0;
if (d_in == 12'd10)
$finish;
end
queue q(
.put (put),
.get (get),
.clk (clk),
.flush (flush),
.d_in (d_in),
.d_out (d_out),
.empty (empty),
.full (full)
);
endmodule