data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:145: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'bcgman\'\nmodule bcgman(\n       ^~~~~~\n                                                                                          : ... Top module \'paletteBcg\'\nmodule paletteBcg(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:57: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'palette\' generates 4 bits.\n                                                                                      : ... In instance bcgman\n  f_palette <= palette;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:72: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'f_palette\' generates 2 bits.\n                                                                                      : ... In instance bcgman\n palette = f_palette;\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module bcgman(
	input clk,
	input rst,
	
	input[9:0] cx,
	input[8:0] cy,
	
	input[9:0] x,
	input[8:0] y,
	
	input[7:0] fromRAM,
	
	output reg[12:0] addrRAM,
	output reg[3:0] ui,
	
	output reg[1:0] color,
	output reg[3:0] palette
	
);

reg[1:0] f_s=0;
reg[1:0] s=0;

reg[1:0] f_color = 0;
reg[1:0] f_palette = 0;

reg[1:0] f_ncolor = 0;
reg[1:0] f_npalette = 0;

reg[1:0] ncolor = 0;
reg[3:0] npalette = 0;

reg[3:0] nui = 0;
reg[3:0] f_nui = 0;
reg[3:0] f_ui;

reg[8:0] ccx;
reg[8:0] f_ccx;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_s <= 0;
		f_palette <= 0;
		f_color <= 0;

		f_ncolor <= 0;
		f_ccx <= 0;
		
		f_nui = 0;
		f_ui = 0;
	end else
	begin
		f_s <= s;
		f_palette <= palette;
		f_color <= color;

		f_ncolor <= ncolor;
		f_ccx <= ccx;
		
		f_nui = nui;
		f_ui = ui;
	end
end

always@(*)begin
	s = f_s;
	addrRAM = 0;
	
	palette = f_palette;
	color = f_color;
	
	ncolor = f_ncolor;
	
	nui = f_nui;
	ui = f_ui;
	
	ccx = f_ccx;
	
	case(f_s)
		0: begin
			addrRAM = {2'b10,cx[9:4],cy[8:4]};
			ccx = cx[9:1];
			
			if(cy[4]) nui = fromRAM[3:0];
			else nui = fromRAM[7:4]; 
			
			s=1;
		end
		
		1: begin
			 case(fromRAM[7:6])
				2'b11:
					if(f_ccx[2])
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b1,cy[3:2],1'b1};
					else
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b1,cy[3:2],1'b0};
				2'b10:
					if(f_ccx[2])
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b0,cy[3:2] ,1'b1};
					else
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b0,cy[3:2] ,1'b0};

				default:
					if(f_ccx[2])
						addrRAM = {2'b01,fromRAM[6:0],cy[3:1],1'b1};
					else
						addrRAM = {2'b01,fromRAM[6:0],cy[3:1],1'b0};
				
			 endcase
	
				
			s=2;
		end
		2: begin
			addrRAM = {3'b111,f_ccx[8:3],cy[8:5]};
			case(f_ccx[1:0])
			
				3: ncolor = fromRAM[1:0];
				2: ncolor = fromRAM[3:2];
				1: ncolor = fromRAM[5:4];
				0: ncolor = fromRAM[7:6];
				default:;
			endcase
			s=3;
		end
		3: begin
		
			addrRAM = {3'b110,f_ccx[8:3],y[8:5]};
		
			if(cy[4]) palette = fromRAM[3:0];
			else palette = fromRAM[7:4];
			
			ui = f_nui;
			color = f_ncolor;
			s=0;
		end
	endcase
end

endmodule
module bcgman(
	input clk,
	input rst,
	
	input[9:0] cx,
	input[8:0] cy,
	
	input[9:0] x,
	input[8:0] y,
	
	input[7:0] fromRAM,
	
	output reg[12:0] addrRAM,
	output reg[3:0] ui,
	
	output reg[1:0] color,
	output reg[3:0] palette
	
);


reg[1:0] f_s=0;
reg[1:0] s=0;

reg[1:0] f_color = 0;
reg[1:0] f_palette = 0;

reg[1:0] f_ncolor = 0;
reg[1:0] f_npalette = 0;

reg[1:0] ncolor = 0;
reg[3:0] npalette = 0;

reg[3:0] nui = 0;
reg[3:0] f_nui = 0;
reg[3:0] f_ui;

reg[8:0] ccx;
reg[8:0] f_ccx;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_s <= 0;
		f_palette <= 0;
		f_color <= 0;

		f_ncolor <= 0;
		f_ccx <= 0;
		
		f_nui = 0;
		f_ui = 0;
	end else
	begin
		f_s <= s;
		f_palette <= palette;
		f_color <= color;

		f_ncolor <= ncolor;
		f_ccx <= ccx;
		
		f_nui = nui;
		f_ui = ui;
	end
end

always@(*)begin
	s = f_s;
	addrRAM = 0;
	
	palette = f_palette;
	color = f_color;
	
	ncolor = f_ncolor;
	
	nui = f_nui;
	ui = f_ui;
	
	ccx = f_ccx;
	
	case(f_s)
		0: begin
			addrRAM = {2'b10,cx[9:4],cy[8:4]};
			ccx = cx[9:1];
			
			if(cy[4]) nui = fromRAM[3:0];
			else nui = fromRAM[7:4]; 
			
			s=1;
		end
		
		1: begin
			 case(fromRAM[7:6])
				2'b11:
					if(f_ccx[2])
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b1,cy[3:2],1'b1};
					else
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b1,cy[3:2],1'b0};
				2'b10:
					if(f_ccx[2])
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b0,cy[3:2] ,1'b1};
					else
						addrRAM = {2'b01,1'b1,fromRAM[5:0],1'b0,cy[3:2] ,1'b0};

				default:
					if(f_ccx[2])
						addrRAM = {2'b01,fromRAM[6:0],cy[3:1],1'b1};
					else
						addrRAM = {2'b01,fromRAM[6:0],cy[3:1],1'b0};
				
			 endcase
	
				
			s=2;
		end
		2: begin
			addrRAM = {3'b111,f_ccx[8:3],cy[8:5]};
			case(f_ccx[1:0])
			
				3: ncolor = fromRAM[1:0];
				2: ncolor = fromRAM[3:2];
				1: ncolor = fromRAM[5:4];
				0: ncolor = fromRAM[7:6];
				default:;
			endcase
			s=3;
		end
		3: begin
		
			addrRAM = {3'b110,f_ccx[8:3],y[8:5]};
		
			if(cy[4]) palette = fromRAM[3:0];
			else palette = fromRAM[7:4];
			
			ui = f_nui;
			color = f_ncolor;
			s=0;
		end
	endcase
end

endmodule