data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleCMemMRROM/reference/SimpleCMemMRROM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleCMemMRROM/reference/SimpleCMemMRROM.v:121: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                         : ... In instance SimpleCMemMRROM.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module SimpleCMemMRROM(
    input clock,
    input reset,
    input [3:0] io_rdAddr,
    output [7:0] io_rdData,
    input [3:0] io_rdAddr2,
    output [7:0] io_rdData2
);
    wire [7:0] mem__T_15_data;
    wire mem__T_15_clk;
    wire mem__T_15_en;
    wire [5:0] mem__T_15_addr;
    wire [7:0] mem__T_16_data;
    wire mem__T_16_clk;
    wire mem__T_16_en;
    wire [5:0] mem__T_16_addr;
    wire [15:0] mem_read_datas;
    wire [1:0] mem_read_clks;
    wire [1:0] mem_read_ens;
    wire [11:0] mem_read_addrs;
    BITS #(.width(16), .high(7), .low(0)) bits_1 (
        .y(mem__T_15_data),
        .in(mem_read_datas)
    );
    BITS #(.width(16), .high(15), .low(8)) bits_2 (
        .y(mem__T_16_data),
        .in(mem_read_datas)
    );
    CAT #(.width_a(1), .width_b(1)) cat_3 (
        .y(mem_read_clks),
        .a(mem__T_16_clk),
        .b(mem__T_15_clk)
    );
    CAT #(.width_a(1), .width_b(1)) cat_4 (
        .y(mem_read_ens),
        .a(mem__T_16_en),
        .b(mem__T_15_en)
    );
    CAT #(.width_a(6), .width_b(6)) cat_5 (
        .y(mem_read_addrs),
        .a(mem__T_16_addr),
        .b(mem__T_15_addr)
    );
    MRROMMEM #(.depth(64), .addrbits(6), .width(8), .readernum(2), .isSyncRead(0)) mem (
        .read_datas(mem_read_datas),
        .read_clks(mem_read_clks),
        .read_ens(mem_read_ens),
        .read_addrs(mem_read_addrs)
    );
    PAD_UNSIGNED #(.width(4), .n(6)) u_pad_6 (
        .y(mem__T_15_addr),
        .in(io_rdAddr)
    );
    assign mem__T_15_en = 1'h1;
    assign mem__T_15_clk = clock;
    PAD_UNSIGNED #(.width(4), .n(6)) u_pad_7 (
        .y(mem__T_16_addr),
        .in(io_rdAddr2)
    );
    assign mem__T_16_en = 1'h1;
    assign mem__T_16_clk = clock;
    assign io_rdData = mem__T_15_data;
    assign io_rdData2 = mem__T_16_data;
endmodule
module SimpleCMemMRROM(
    input clock,
    input reset,
    input [3:0] io_rdAddr,
    output [7:0] io_rdData,
    input [3:0] io_rdAddr2,
    output [7:0] io_rdData2
);

    wire [7:0] mem__T_15_data;
    wire mem__T_15_clk;
    wire mem__T_15_en;
    wire [5:0] mem__T_15_addr;
    wire [7:0] mem__T_16_data;
    wire mem__T_16_clk;
    wire mem__T_16_en;
    wire [5:0] mem__T_16_addr;
    wire [15:0] mem_read_datas;
    wire [1:0] mem_read_clks;
    wire [1:0] mem_read_ens;
    wire [11:0] mem_read_addrs;
    BITS #(.width(16), .high(7), .low(0)) bits_1 (
        .y(mem__T_15_data),
        .in(mem_read_datas)
    );
    BITS #(.width(16), .high(15), .low(8)) bits_2 (
        .y(mem__T_16_data),
        .in(mem_read_datas)
    );
    CAT #(.width_a(1), .width_b(1)) cat_3 (
        .y(mem_read_clks),
        .a(mem__T_16_clk),
        .b(mem__T_15_clk)
    );
    CAT #(.width_a(1), .width_b(1)) cat_4 (
        .y(mem_read_ens),
        .a(mem__T_16_en),
        .b(mem__T_15_en)
    );
    CAT #(.width_a(6), .width_b(6)) cat_5 (
        .y(mem_read_addrs),
        .a(mem__T_16_addr),
        .b(mem__T_15_addr)
    );
    MRROMMEM #(.depth(64), .addrbits(6), .width(8), .readernum(2), .isSyncRead(0)) mem (
        .read_datas(mem_read_datas),
        .read_clks(mem_read_clks),
        .read_ens(mem_read_ens),
        .read_addrs(mem_read_addrs)
    );
    PAD_UNSIGNED #(.width(4), .n(6)) u_pad_6 (
        .y(mem__T_15_addr),
        .in(io_rdAddr)
    );
    assign mem__T_15_en = 1'h1;
    assign mem__T_15_clk = clock;
    PAD_UNSIGNED #(.width(4), .n(6)) u_pad_7 (
        .y(mem__T_16_addr),
        .in(io_rdAddr2)
    );
    assign mem__T_16_en = 1'h1;
    assign mem__T_16_clk = clock;
    assign io_rdData = mem__T_15_data;
    assign io_rdData2 = mem__T_16_data;
endmodule