data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new/Testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new/Testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new/Testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #2000;  \n        ^\n%Error: data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new/Testbench.v:7: Cannot find file containing module: \'Top\'\n    Top #(.WL(WL)) UUT (.clk(clk));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new,data/full_repos/permissive/482975152/Top\n             data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new,data/full_repos/permissive/482975152/Top.v\n             data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sim_1/new,data/full_repos/permissive/482975152/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Testbench;
    parameter WL = 32;
    reg clk;
    
    Top #(.WL(WL)) UUT (.clk(clk));
    
    initial clk <= 0;
    always #5 clk <= ~clk;
    
    initial begin
        #2000;
        $finish;
    end
endmodule
module Testbench;

    parameter WL = 32;
    reg clk;
    
    Top #(.WL(WL)) UUT (.clk(clk));
    
    initial clk <= 0;
    always #5 clk <= ~clk;
    
    initial begin
        #2000;
        $finish;
    end
endmodule