data/full_repos/permissive/422650017/verilog/rtl/elpis/forwardingunit.v
1: b'%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/forwardingunit.v:17: Cannot find include file: /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n    `include "/project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module forwardingunit_st(
	input mem_we,
	input[4:0] ex_reg_b_in,
	input[4:0] mem_reg_b_in,
	input[1:0] forwarding_y,
	output reg[1:0] forwarding_regb
);
  
  	always@(*) begin
		if (mem_we && forwarding_y) 
			forwarding_regb <= 2'b01;
		else if (mem_we && (ex_reg_b_in == mem_reg_b_in)) 
			forwarding_regb <= 2'b10;
		else 
			forwarding_regb <= 2'b00;
	end

endmodule
module forwardingunit_st(
	input mem_we,
	input[4:0] ex_reg_b_in,
	input[4:0] mem_reg_b_in,
	input[1:0] forwarding_y,
	output reg[1:0] forwarding_regb
);

  
  	always@(*) begin
		if (mem_we && forwarding_y) 
			forwarding_regb <= 2'b01;
		else if (mem_we && (ex_reg_b_in == mem_reg_b_in)) 
			forwarding_regb <= 2'b10;
		else 
			forwarding_regb <= 2'b00;
	end

endmodule