data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/shftl2.v
data/verilator_xmls/5a699aa4-2ef7-4cdb-aa58-cfe96516c1f4.xml
module shftl2 (
  input [31:0] a,
  output wire [31:0] y
);

assign y = {a[29:0], 2'b00};

endmodule
module shftl2 (
  input [31:0] a,
  output wire [31:0] y
);


assign y = {a[29:0], 2'b00};

endmodule