data/full_repos/permissive/431487364/sim/ex_tb.v
1: b'%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:1: Cannot find include file: ../src/headers/buceros_header.v\n`include "../src/headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v.sv\n             ../src/headers/buceros_header.v\n             ../src/headers/buceros_header.v.v\n             ../src/headers/buceros_header.v.sv\n             obj_dir/../src/headers/buceros_header.v\n             obj_dir/../src/headers/buceros_header.v.v\n             obj_dir/../src/headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:19: Define or directive not defined: \'`InstAddrBus\'\n  reg [`InstAddrBus] pc_i;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [`InstAddrBus] pc_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:22: Define or directive not defined: \'`OpcodeBus\'\n  reg [  `OpcodeBus] opcode_i;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [  `OpcodeBus] opcode_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:23: Define or directive not defined: \'`Funct3Bus\'\n  reg [  `Funct3Bus] funct3_i;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [  `Funct3Bus] funct3_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:24: Define or directive not defined: \'`Funct7Bus\'\n  reg [  `Funct7Bus] funct7_i;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [  `Funct7Bus] funct7_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:25: Define or directive not defined: \'`ImmBus\'\n  reg [     `ImmBus] imm_i;\n            ^~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [     `ImmBus] imm_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:27: Define or directive not defined: \'`RegAddrBus\'\n  reg [ `RegAddrBus] wreg_addr_i;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [ `RegAddrBus] wreg_addr_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:28: Define or directive not defined: \'`RegDataBus\'\n  reg [ `RegDataBus] rs1_data_i;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [ `RegDataBus] rs1_data_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:29: Define or directive not defined: \'`RegDataBus\'\n  reg [ `RegDataBus] rs2_data_i;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [ `RegDataBus] rs2_data_i;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:32: Define or directive not defined: \'`MemAddrBus\'\n  wire [`MemAddrBus] mem_addr_o;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [`MemAddrBus] mem_addr_o;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:33: Define or directive not defined: \'`Funct3Bus\'\n  wire [ `Funct3Bus] funct3_o;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [ `Funct3Bus] funct3_o;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:35: Define or directive not defined: \'`RegAddrBus\'\n  wire [`RegAddrBus] wreg_addr_o;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [`RegAddrBus] wreg_addr_o;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:36: Define or directive not defined: \'`RegDataBus\'\n  wire [`RegDataBus] wreg_data_o;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ex_tb.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [`RegDataBus] wreg_data_o;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #5 pc_i = $random;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_LUI;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_AUIPC;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_JAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_JALR;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_B_TYPE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_LOAD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_STORE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_ARITHI;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_ARITH;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_FENCE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = OP_ENV;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ex_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #5 opcode_i = $random;\n        ^\n%Error: Exiting due to 25 error(s), 13 warning(s)\n'
module ex_tb;


  localparam  OP_LUI    = 7'b0110111;
  localparam  OP_AUIPC  = 7'b0010111;
  localparam  OP_JAL    = 7'b1101111;
  localparam  OP_JALR   = 7'b1100111;
  localparam  OP_B_TYPE = 7'b1100011;
  localparam  OP_LOAD   = 7'b0000011;
  localparam  OP_STORE  = 7'b0100011;
  localparam  OP_ARITHI = 7'b0010011;
  localparam  OP_ARITH  = 7'b0110011;
  localparam  OP_FENCE  = 7'b0001111;
  localparam  OP_ENV    = 7'b1110011;


  reg [`InstAddrBus] pc_i;
  reg  wmem_en_i = 0;
  reg  rmem_en_i = 0;
  reg [  `OpcodeBus] opcode_i;
  reg [  `Funct3Bus] funct3_i;
  reg [  `Funct7Bus] funct7_i;
  reg [     `ImmBus] imm_i;
  reg  wreg_en_i = 0;
  reg [ `RegAddrBus] wreg_addr_i;
  reg [ `RegDataBus] rs1_data_i;
  reg [ `RegDataBus] rs2_data_i;
  wire  wmem_en_o;
  wire  rmem_en_o;
  wire [`MemAddrBus] mem_addr_o;
  wire [ `Funct3Bus] funct3_o;
  wire  wreg_en_o;
  wire [`RegAddrBus] wreg_addr_o;
  wire [`RegDataBus] wreg_data_o;

  ex 
  ex_dut (
    .pc_i (pc_i ),
    .wmem_en_i (wmem_en_i ),
    .rmem_en_i (rmem_en_i ),
    .opcode_i (opcode_i ),
    .funct3_i (funct3_i ),
    .funct7_i (funct7_i ),
    .imm_i (imm_i ),
    .wreg_en_i (wreg_en_i ),
    .wreg_addr_i (wreg_addr_i ),
    .rs1_data_i (rs1_data_i ),
    .rs2_data_i (rs2_data_i ),
    .wmem_en_o (wmem_en_o ),
    .rmem_en_o (rmem_en_o ),
    .mem_addr_o (mem_addr_o ),
    .funct3_o (funct3_o ),
    .wreg_en_o (wreg_en_o ),
    .wreg_addr_o (wreg_addr_o ),
    .wreg_data_o  ( wreg_data_o)
  );

  initial begin
    begin
      wmem_en_i = 0;
      rmem_en_i = 0;
      wreg_en_i = 0;
      repeat(100000) begin
        #5 pc_i = $random;
        wmem_en_i = $random;
        rmem_en_i = $random;
        opcode_i = $random;
        funct3_i = $random;
        funct7_i = $random;
        imm_i = $random;
        wreg_en_i = $random;
        wreg_addr_i = $random;
        rs1_data_i = $random;
        rs2_data_i = $random;
        #5 opcode_i = OP_LUI;
        #5 opcode_i = OP_AUIPC;
        #5 opcode_i = OP_JAL;
        #5 opcode_i = OP_JALR;
        #5 opcode_i = OP_B_TYPE;
        #5 opcode_i = OP_LOAD;
        #5 opcode_i = OP_STORE;
        #5 opcode_i = OP_ARITHI;
        #5 opcode_i = OP_ARITH;
        #5 opcode_i = OP_FENCE;
        #5 opcode_i = OP_ENV;
        #5 opcode_i = $random;
      end
    end
  end


endmodule
module ex_tb;



  localparam  OP_LUI    = 7'b0110111;
  localparam  OP_AUIPC  = 7'b0010111;
  localparam  OP_JAL    = 7'b1101111;
  localparam  OP_JALR   = 7'b1100111;
  localparam  OP_B_TYPE = 7'b1100011;
  localparam  OP_LOAD   = 7'b0000011;
  localparam  OP_STORE  = 7'b0100011;
  localparam  OP_ARITHI = 7'b0010011;
  localparam  OP_ARITH  = 7'b0110011;
  localparam  OP_FENCE  = 7'b0001111;
  localparam  OP_ENV    = 7'b1110011;


  reg [`InstAddrBus] pc_i;
  reg  wmem_en_i = 0;
  reg  rmem_en_i = 0;
  reg [  `OpcodeBus] opcode_i;
  reg [  `Funct3Bus] funct3_i;
  reg [  `Funct7Bus] funct7_i;
  reg [     `ImmBus] imm_i;
  reg  wreg_en_i = 0;
  reg [ `RegAddrBus] wreg_addr_i;
  reg [ `RegDataBus] rs1_data_i;
  reg [ `RegDataBus] rs2_data_i;
  wire  wmem_en_o;
  wire  rmem_en_o;
  wire [`MemAddrBus] mem_addr_o;
  wire [ `Funct3Bus] funct3_o;
  wire  wreg_en_o;
  wire [`RegAddrBus] wreg_addr_o;
  wire [`RegDataBus] wreg_data_o;

  ex 
  ex_dut (
    .pc_i (pc_i ),
    .wmem_en_i (wmem_en_i ),
    .rmem_en_i (rmem_en_i ),
    .opcode_i (opcode_i ),
    .funct3_i (funct3_i ),
    .funct7_i (funct7_i ),
    .imm_i (imm_i ),
    .wreg_en_i (wreg_en_i ),
    .wreg_addr_i (wreg_addr_i ),
    .rs1_data_i (rs1_data_i ),
    .rs2_data_i (rs2_data_i ),
    .wmem_en_o (wmem_en_o ),
    .rmem_en_o (rmem_en_o ),
    .mem_addr_o (mem_addr_o ),
    .funct3_o (funct3_o ),
    .wreg_en_o (wreg_en_o ),
    .wreg_addr_o (wreg_addr_o ),
    .wreg_data_o  ( wreg_data_o)
  );

  initial begin
    begin
      wmem_en_i = 0;
      rmem_en_i = 0;
      wreg_en_i = 0;
      repeat(100000) begin
        #5 pc_i = $random;
        wmem_en_i = $random;
        rmem_en_i = $random;
        opcode_i = $random;
        funct3_i = $random;
        funct7_i = $random;
        imm_i = $random;
        wreg_en_i = $random;
        wreg_addr_i = $random;
        rs1_data_i = $random;
        rs2_data_i = $random;
        #5 opcode_i = OP_LUI;
        #5 opcode_i = OP_AUIPC;
        #5 opcode_i = OP_JAL;
        #5 opcode_i = OP_JALR;
        #5 opcode_i = OP_B_TYPE;
        #5 opcode_i = OP_LOAD;
        #5 opcode_i = OP_STORE;
        #5 opcode_i = OP_ARITHI;
        #5 opcode_i = OP_ARITH;
        #5 opcode_i = OP_FENCE;
        #5 opcode_i = OP_ENV;
        #5 opcode_i = $random;
      end
    end
  end


endmodule