data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter.v
data/verilator_xmls/c49b835f-5834-48ed-b16a-079e11fb0085.xml
module two_way_counter(input clk, rst, dir, zero, output reg [15:0] out);
    always @(posedge clk or posedge rst) 
        if (rst | zero) out <= 16'b0;
        else out <= (dir == 0) ? out + 1 : out - 1;
endmodule
module two_way_counter(input clk, rst, dir, zero, output reg [15:0] out);

    always @(posedge clk or posedge rst) 
        if (rst | zero) out <= 16'b0;
        else out <= (dir == 0) ? out + 1 : out - 1;
endmodule