data/full_repos/permissive/458737381/src/verilog-parser/tests/quest_for_in.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/quest_for_in.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #4 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/quest_for_in.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module quest_for_in();

integer i;
reg clk;

initial begin
  clk = 0;
  #4 $finish;
end

always #1 clk = !clk;

always @ (posedge clk)
begin
  for (i=0; i < 8; i = i + 1) begin : FOR_IN
    if (i == 5) begin
      disable FOR_IN;
    end
    $display ("Current i : %g",i);
  end
end
endmodule
module quest_for_in();


integer i;
reg clk;

initial begin
  clk = 0;
  #4 $finish;
end

always #1 clk = !clk;

always @ (posedge clk)
begin
  for (i=0; i < 8; i = i + 1) begin : FOR_IN
    if (i == 5) begin
      disable FOR_IN;
    end
    $display ("Current i : %g",i);
  end
end
endmodule