data/full_repos/permissive/434840709/week10/4.v
data/verilator_xmls/8cec3d17-b0bd-4d26-a0c6-0cd1ee487679.xml
module top_module(

            input a,

            input b,

            input c,

            input d,

            output out,

            output out_n   
); 
        wire o1 = a&b;
        wire o2 = c&d;

        assign out = o1|o2;
        assign out_n = ~(o1|o2);        
        assign out_n = ~(o1|o2);


endmodule
module top_module(

            input a,

            input b,

            input c,

            input d,

            output out,

            output out_n   
);
 
        wire o1 = a&b;
        wire o2 = c&d;

        assign out = o1|o2;
        assign out_n = ~(o1|o2);        
        assign out_n = ~(o1|o2);


endmodule