data/full_repos/permissive/493441306/Verilog Language/modules_hierarchy/04_moduleshift8.v
1: b'%Error: Cannot find file containing module: Language/modules_hierarchy,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             Language/modules_hierarchy,data/full_repos/permissive/493441306\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/modules_hierarchy/04_moduleshift8.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
    wire [7:0] q1, q2, q3;
    
    my_dff8 d1 ( clk, d, q1 );
    my_dff8 d2 ( clk, q1, q2 );
    my_dff8 d3 ( clk, q2, q3 );
    
    always@(*) begin
        case(sel)
            2'b00 : q = d;
            2'b01 : q = q1;
            2'b10 : q = q2;
            2'b11 : q = q3;
            default:q = 8'b0; 
        endcase
    end

endmodule
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    
    wire [7:0] q1, q2, q3;
    
    my_dff8 d1 ( clk, d, q1 );
    my_dff8 d2 ( clk, q1, q2 );
    my_dff8 d3 ( clk, q2, q3 );
    
    always@(*) begin
        case(sel)
            2'b00 : q = d;
            2'b01 : q = q1;
            2'b10 : q = q2;
            2'b11 : q = q3;
            default:q = 8'b0; 
        endcase
    end

endmodule