data/full_repos/permissive/515624136/rtl/MUX_4_1.v
data/verilator_xmls/093fd2e7-39d6-452f-8330-c1db99fcf895.xml
module MUX_4_1 #(parameter INPUT_DATA_WIDTH =32)(


input [INPUT_DATA_WIDTH-1:0] MUX_Input_0,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_1,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_2,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_3,

input [1:0] MUX_Sel_InBUS,


output[INPUT_DATA_WIDTH-1:0]  MUX_Output_OutBUS


);

reg [INPUT_DATA_WIDTH-1:0] Data;




always@(*)
begin
	case(MUX_Sel_InBUS)
		2'b00: Data=MUX_Input_0;
		2'b01: Data=MUX_Input_1;	
		2'b10: Data=MUX_Input_2;	
		2'b11: Data=MUX_Input_3;		
	endcase
end

assign MUX_Output_OutBUS=Data;

endmodule
module MUX_4_1 #(parameter INPUT_DATA_WIDTH =32)(


input [INPUT_DATA_WIDTH-1:0] MUX_Input_0,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_1,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_2,
input [INPUT_DATA_WIDTH-1:0] MUX_Input_3,

input [1:0] MUX_Sel_InBUS,


output[INPUT_DATA_WIDTH-1:0]  MUX_Output_OutBUS


);


reg [INPUT_DATA_WIDTH-1:0] Data;




always@(*)
begin
	case(MUX_Sel_InBUS)
		2'b00: Data=MUX_Input_0;
		2'b01: Data=MUX_Input_1;	
		2'b10: Data=MUX_Input_2;	
		2'b11: Data=MUX_Input_3;		
	endcase
end

assign MUX_Output_OutBUS=Data;

endmodule