data/full_repos/permissive/513199821/test.v
1: b'%Error: data/full_repos/permissive/513199821/test.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #32;    \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #32;\n  ^\n%Error: data/full_repos/permissive/513199821/test.v:500: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("/tmp/eonsoc.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:501: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:504: Unsupported or unknown PLI call: $timeformat\n  $timeformat (-6, 3, "us", 12);\n  ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:509: Unsupported: Ignoring delay on this delayed statement.\n  #128;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:514: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:516: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:522: Unsupported: Ignoring delay on this delayed statement.\n    # 64;\n    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module uartDump #(
     parameter CLKDIV = 8'd139
  ) (
    input  clk,
    input  resetn,
    input  ser_rx,
    input  [31:0] reg_div_di
);

reg [3:0] recv_state;
reg [7:0] recv_divcnt;
reg [7:0] recv_pattern;
reg	  done;


always @(posedge clk) begin
  if (!resetn) begin
    recv_state	 <= 0;
    recv_divcnt  <= 0;
    recv_pattern <= 0;
    done	 <= 0;
  end else begin
    recv_divcnt <= recv_divcnt + 1;
    case (recv_state)
      0: begin
	   if (!ser_rx)
	     recv_state <= 1;
	   recv_divcnt <= 0;
	 end
      1: begin
	   if (2*recv_divcnt > CLKDIV) begin
	     recv_state  <= 2;
	     recv_divcnt <= 0;
	   end
	 end
      10: begin
	   if (recv_divcnt > CLKDIV) begin

	     recv_state     <= 0;
	     $write ("%s", recv_pattern);
	   end
	 end
      default: begin
	   if (recv_divcnt > CLKDIV) begin
	     recv_pattern <= {ser_rx, recv_pattern[7:1]};
	     recv_state   <= recv_state + 1;
	     recv_divcnt  <= 0;
	   end
	 end
    endcase
  end
end
endmodule
module uartDump #(
     parameter CLKDIV = 8'd139
  ) (
    input  clk,
    input  resetn,
    input  ser_rx,
    input  [31:0] reg_div_di
);


reg [3:0] recv_state;
reg [7:0] recv_divcnt;
reg [7:0] recv_pattern;
reg	  done;


always @(posedge clk) begin
  if (!resetn) begin
    recv_state	 <= 0;
    recv_divcnt  <= 0;
    recv_pattern <= 0;
    done	 <= 0;
  end else begin
    recv_divcnt <= recv_divcnt + 1;
    case (recv_state)
      0: begin
	   if (!ser_rx)
	     recv_state <= 1;
	   recv_divcnt <= 0;
	 end
      1: begin
	   if (2*recv_divcnt > CLKDIV) begin
	     recv_state  <= 2;
	     recv_divcnt <= 0;
	   end
	 end
      10: begin
	   if (recv_divcnt > CLKDIV) begin

	     recv_state     <= 0;
	     $write ("%s", recv_pattern);
	   end
	 end
      default: begin
	   if (recv_divcnt > CLKDIV) begin
	     recv_pattern <= {ser_rx, recv_pattern[7:1]};
	     recv_state   <= recv_state + 1;
	     recv_divcnt  <= 0;
	   end
	 end
    endcase
  end
end
endmodule