data/full_repos/permissive/447976230/fpga/usrp3/top/x400/coregen_dsp/hbdec1_stub.v
data/verilator_xmls/63bedca9-d42d-4122-b050-6c5417f2b28a.xml
module hbdec1(
  sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, 
  coef_ld, dout_1, dout_2, din_1, din_2, coef_din
)
;
  input sclr;
  input ce;
  output rfd;
  output rdy;
  output data_valid;
  input coef_we;
  input nd;
  input clk;
  input coef_ld;
  output [46:0]dout_1;
  output [46:0]dout_2;
  input [23:0]din_1;
  input [23:0]din_2;
  input [17:0]coef_din;
endmodule
module hbdec1(
  sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, 
  coef_ld, dout_1, dout_2, din_1, din_2, coef_din
)
;

  input sclr;
  input ce;
  output rfd;
  output rdy;
  output data_valid;
  input coef_we;
  input nd;
  input clk;
  input coef_ld;
  output [46:0]dout_1;
  output [46:0]dout_2;
  input [23:0]din_1;
  input [23:0]din_2;
  input [17:0]coef_din;
endmodule