data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:140: Cannot find file containing module: \'cam\'\n   cam \n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam.sv\n             cam\n             cam.v\n             cam.sv\n             obj_dir/cam\n             obj_dir/cam.v\n             obj_dir/cam.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:160: Cannot find file containing module: \'cam\'\n   cam #(\n   ^~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:222: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:226: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n       cam_wr_addr_learn_next = reset_count;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:231: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:237: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:241: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_learn_next = reset_count;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:247: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
function integer log2;

      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction