data/full_repos/permissive/461141714/src/Pipelined CPU/ALU.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/ALU.v\n%Error: Exiting due to 3 error(s)\n'
module ALU(
    input [15:0] A,
    input [15:0] B,
    input [5:0] OP,
    output [15:0] C
    );
    
    reg [15:0] result;
    reg [15:0] newB;
    assign C = result;
    
    always @(*)
    begin
        case(OP)
        `FUNC_ADD:
            result = A + B;
        `FUNC_SUB:
            result = A - B;
        `FUNC_AND:
            result = A & B;
        `FUNC_ORR:
            result = A | B;
        `FUNC_NOT:
            result = ~A;
        `FUNC_TCP:
            result = ~A+1;
        `FUNC_SHL:
            result = {A[14:0], 1'b0};
        `FUNC_SHR:
            result = {A[15], A[15:1]};
        `FUNC_ADI:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_ORI:
            result = A | B;
        `FUNC_LHI:
            result = {B[7:0], 8'b0};
        `FUNC_LWD:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_SWD:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_BPC:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB + 1;
        end
        `FUNC_JPC:
        begin
            result = A + 1;
        end
        `FUNC_A:
            result = A;
        

        endcase
    end
endmodule
module ALU(
    input [15:0] A,
    input [15:0] B,
    input [5:0] OP,
    output [15:0] C
    );

    
    reg [15:0] result;
    reg [15:0] newB;
    assign C = result;
    
    always @(*)
    begin
        case(OP)
        `FUNC_ADD:
            result = A + B;
        `FUNC_SUB:
            result = A - B;
        `FUNC_AND:
            result = A & B;
        `FUNC_ORR:
            result = A | B;
        `FUNC_NOT:
            result = ~A;
        `FUNC_TCP:
            result = ~A+1;
        `FUNC_SHL:
            result = {A[14:0], 1'b0};
        `FUNC_SHR:
            result = {A[15], A[15:1]};
        `FUNC_ADI:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_ORI:
            result = A | B;
        `FUNC_LHI:
            result = {B[7:0], 8'b0};
        `FUNC_LWD:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_SWD:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB;
        end
        `FUNC_BPC:
        begin
            newB = {{8{B[7]}}, B[7:0]};
            result = A + newB + 1;
        end
        `FUNC_JPC:
        begin
            result = A + 1;
        end
        `FUNC_A:
            result = A;
        

        endcase
    end
endmodule