data/full_repos/permissive/458737381/src/verilog-parser/tests/forever-disable.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/forever-disable.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #1 i = i + 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/forever-disable.v:5: Can\'t find definition of variable: \'i\'\n    i = 0;\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/forever-disable.v:7: Can\'t find definition of variable: \'a\'\n        if (i==a)\n               ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module forever_disable();

initial begin
    i = 0;
    forever begin : continue_block
        if (i==a)
            disable continue_block;
        #1 i = i + 1;
    end
end

endmodule
module forever_disable();


initial begin
    i = 0;
    forever begin : continue_block
        if (i==a)
            disable continue_block;
        #1 i = i + 1;
    end
end

endmodule