data/full_repos/permissive/42434302/ivltests/pr3527694.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr3527694.v:26: Unsupported or unknown PLI call: $dumpflush\n $dumpflush;\n ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:84: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr3527694.v:140: Unsupported or unknown PLI call: $strobe\n $strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2);\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test3 (sys_clk, sys_rst);
input sys_clk;
input sys_rst;

parameter WIDTH1 = 0;
parameter WIDTH2 = 0;

localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2;

wire [31:0] wide = big_width;
wire [31:0] width1 = WIDTH1;
wire [31:0] width2 = WIDTH2;
initial begin
	$strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2);
end


endmodule
module test3 (sys_clk, sys_rst);

input sys_clk;
input sys_rst;

parameter WIDTH1 = 0;
parameter WIDTH2 = 0;

localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2;

wire [31:0] wide = big_width;
wire [31:0] width1 = WIDTH1;
wire [31:0] width2 = WIDTH2;
initial begin
	$strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2);
end


endmodule