data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:15: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:64: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:70: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:75: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:80: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:84: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:88: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:92: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:96: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:100: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:104: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:108: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:112: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:116: Unsupported: wait statements\n        wait (tb_syn_circle.dut.done === 1\'b1)\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:123: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:127: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:131: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:135: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:139: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:143: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:147: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:151: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:155: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:159: Unsupported: wait statements\n        wait (tb_syn_circle.dut.done === 1\'b1)\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:167: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:172: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:176: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:180: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:184: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:188: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:192: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:196: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:200: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:204: Unsupported: wait statements\n        wait (tb_syn_circle.dut.done === 1\'b1)\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_circle.sv:208: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: Exiting due to 3 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_circle();


    logic clk, rst_n, start, done, vga_plot, err;
    logic [2:0] colour, vga_colour;
    logic [7:0] centre_x, radius, vga_x;
    logic [6:0] centre_y, vga_y;

    circle dut(.*);

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done, exp_plot;
        begin
            $display("CASE %d", index);
            if (tb_syn_circle.dut.vga_x !== exp_x) begin
                $display("ERROR B: Expected vga_x is %d, actual vga_x is %d", exp_x, tb_syn_circle.dut.vga_x);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_y !== exp_y) begin
                $display("ERROR C: Expected vga_y is %d, actual vga_y is %d", exp_y, tb_syn_circle.dut.vga_y);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_colour !== exp_colour) begin
                $display("ERROR D: Expected vga_colour is %d, actual vga_colour is %d", exp_colour, tb_syn_circle.dut.vga_colour);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.done !== exp_done) begin
                $display("ERROR E: Expected done is %b, actual done is %b", exp_done, tb_syn_circle.dut.done);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_plot !== exp_plot) begin
                $display("ERROR F: Expected vga_plot is %b, actual vga_plot is %b", exp_plot, tb_syn_circle.dut.vga_plot);
                err = 1'b1;
            end
        end
    endtask


    `define BLACK    3'b000
    `define BLUE     3'b001
    `define GREEN    3'b010
    `define CYAN     3'b011
    `define RED      3'b100
    `define MAGENTA  3'b101
    `define YELLOW   3'b110
    `define WHITE    3'b111

    initial begin
        err = 1'b0;


        rst_n = 1'bx; start = 1'bx;
        #10;
        validator(1, 8'b0, 7'b0, 3'bx, 1'b0, 1'b0);


        rst_n = 1'b0; start = 1'b0;
        colour = `BLUE; centre_x = 8'd80; centre_y = 7'd60; radius = 8'd10;
        #10;
        validator(2, 8'd0, 7'd0, `BLUE, 1'b0, 1'b0);


        rst_n = 1'b1;
        #20;
        validator(3, 8'd0, 7'd0, `BLUE, 1'b0, 1'b0);


        start = 1'b1;
        #10;
        validator(4, 8'd90, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(5, 8'd80, 7'd70, `BLUE, 1'b0, 1'b1);


        #10;
        validator(6, 8'd70, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(7, 8'd80, 7'd70, `BLUE, 1'b0, 1'b1);


        #10;
        validator(8, 8'd70, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(9, 8'd80, 7'd50, `BLUE, 1'b0, 1'b1);
        

        #10;
        validator(10, 8'd90, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(11, 8'd80, 7'd50, `BLUE, 1'b0, 1'b1);


        #10;
        validator(12, 8'd90, 7'd61, `BLUE, 1'b0, 1'b1);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(13, 8'd87, 7'd53, `BLUE, 1'b1, 1'b0);


        
        colour = `MAGENTA; centre_x = 8'd159; centre_y = 7'd119; radius = 8'd5;
        start = 1'b0;
        #20;
        start = 1'b1;


        #10;
        validator(14, 8'd0, 7'd64, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(15, 8'd159, 7'd124, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(16, 8'd154, 7'd119, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(17, 8'd159, 7'd124, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(18, 8'd154, 7'd119, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(19, 8'd159, 7'd114, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(20, 8'd164, 7'd119, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(21, 8'd159, 7'd114, `MAGENTA, 1'b0, 1'b1);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(22, 8'd162, 7'd115, `MAGENTA, 1'b1, 1'b0);




        colour = `CYAN; centre_x = 8'd0; centre_y = 7'd0; radius = 8'd20;
        start = 0;
        #20;
        start = 1;
        validator(23, 8'd0, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(24, 8'd0, 7'd0, `CYAN, 1'b0, 1'b1);


        #10;
        validator(25, 8'd0, 7'd20, `CYAN, 1'b0, 1'b1);


        #10;
        validator(26, -20, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(27, 8'd0, 7'd20, `CYAN, 1'b0, 1'b1);


        #10;
        validator(28, -20, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(29, 8'd0, -20, `CYAN, 1'b0, 1'b0);


        #10;
        validator(30, 8'd20, 7'd0, `CYAN, 1'b0, 1'b1);


        #10;
        validator(31, 8'd0, -20, `CYAN, 1'b0, 1'b0);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(32, 8'd14, 7'd114, `CYAN, 1'b1, 1'b0);


        #20;
        validator(33, 8'd0, 7'd0, `CYAN, 1'b1, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_syn_circle();



    logic clk, rst_n, start, done, vga_plot, err;
    logic [2:0] colour, vga_colour;
    logic [7:0] centre_x, radius, vga_x;
    logic [6:0] centre_y, vga_y;

    circle dut(.*);

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done, exp_plot;
        begin
            $display("CASE %d", index);
            if (tb_syn_circle.dut.vga_x !== exp_x) begin
                $display("ERROR B: Expected vga_x is %d, actual vga_x is %d", exp_x, tb_syn_circle.dut.vga_x);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_y !== exp_y) begin
                $display("ERROR C: Expected vga_y is %d, actual vga_y is %d", exp_y, tb_syn_circle.dut.vga_y);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_colour !== exp_colour) begin
                $display("ERROR D: Expected vga_colour is %d, actual vga_colour is %d", exp_colour, tb_syn_circle.dut.vga_colour);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.done !== exp_done) begin
                $display("ERROR E: Expected done is %b, actual done is %b", exp_done, tb_syn_circle.dut.done);
                err = 1'b1;
            end
            if (tb_syn_circle.dut.vga_plot !== exp_plot) begin
                $display("ERROR F: Expected vga_plot is %b, actual vga_plot is %b", exp_plot, tb_syn_circle.dut.vga_plot);
                err = 1'b1;
            end
        end
    endtask


    `define BLACK    3'b000
    `define BLUE     3'b001
    `define GREEN    3'b010
    `define CYAN     3'b011
    `define RED      3'b100
    `define MAGENTA  3'b101
    `define YELLOW   3'b110
    `define WHITE    3'b111

    initial begin
        err = 1'b0;


        rst_n = 1'bx; start = 1'bx;
        #10;
        validator(1, 8'b0, 7'b0, 3'bx, 1'b0, 1'b0);


        rst_n = 1'b0; start = 1'b0;
        colour = `BLUE; centre_x = 8'd80; centre_y = 7'd60; radius = 8'd10;
        #10;
        validator(2, 8'd0, 7'd0, `BLUE, 1'b0, 1'b0);


        rst_n = 1'b1;
        #20;
        validator(3, 8'd0, 7'd0, `BLUE, 1'b0, 1'b0);


        start = 1'b1;
        #10;
        validator(4, 8'd90, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(5, 8'd80, 7'd70, `BLUE, 1'b0, 1'b1);


        #10;
        validator(6, 8'd70, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(7, 8'd80, 7'd70, `BLUE, 1'b0, 1'b1);


        #10;
        validator(8, 8'd70, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(9, 8'd80, 7'd50, `BLUE, 1'b0, 1'b1);
        

        #10;
        validator(10, 8'd90, 7'd60, `BLUE, 1'b0, 1'b1);


        #10;
        validator(11, 8'd80, 7'd50, `BLUE, 1'b0, 1'b1);


        #10;
        validator(12, 8'd90, 7'd61, `BLUE, 1'b0, 1'b1);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(13, 8'd87, 7'd53, `BLUE, 1'b1, 1'b0);


        
        colour = `MAGENTA; centre_x = 8'd159; centre_y = 7'd119; radius = 8'd5;
        start = 1'b0;
        #20;
        start = 1'b1;


        #10;
        validator(14, 8'd0, 7'd64, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(15, 8'd159, 7'd124, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(16, 8'd154, 7'd119, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(17, 8'd159, 7'd124, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(18, 8'd154, 7'd119, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(19, 8'd159, 7'd114, `MAGENTA, 1'b0, 1'b1);


        #10;
        validator(20, 8'd164, 7'd119, `MAGENTA, 1'b0, 1'b0);


        #10;
        validator(21, 8'd159, 7'd114, `MAGENTA, 1'b0, 1'b1);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(22, 8'd162, 7'd115, `MAGENTA, 1'b1, 1'b0);




        colour = `CYAN; centre_x = 8'd0; centre_y = 7'd0; radius = 8'd20;
        start = 0;
        #20;
        start = 1;
        validator(23, 8'd0, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(24, 8'd0, 7'd0, `CYAN, 1'b0, 1'b1);


        #10;
        validator(25, 8'd0, 7'd20, `CYAN, 1'b0, 1'b1);


        #10;
        validator(26, -20, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(27, 8'd0, 7'd20, `CYAN, 1'b0, 1'b1);


        #10;
        validator(28, -20, 7'd0, `CYAN, 1'b0, 1'b0);


        #10;
        validator(29, 8'd0, -20, `CYAN, 1'b0, 1'b0);


        #10;
        validator(30, 8'd20, 7'd0, `CYAN, 1'b0, 1'b1);


        #10;
        validator(31, 8'd0, -20, `CYAN, 1'b0, 1'b0);


        wait (tb_syn_circle.dut.done === 1'b1)
        validator(32, 8'd14, 7'd114, `CYAN, 1'b1, 1'b0);


        #20;
        validator(33, 8'd0, 7'd0, `CYAN, 1'b1, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule