data/full_repos/permissive/485721981/sources/synthesis/UART_Hello.v
1: b'%Warning-WIDTH: data/full_repos/permissive/485721981/sources/synthesis/UART_Hello.v:173: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                       : ... In instance UART_Hello\n        else if (rState == sIDLE) rCharCount <= {(C_MSG_LEN){1\'b0}};\n                                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module  UART_Hello # (
        parameter C_UART_DATA_WIDTH = 8,
        parameter C_MSG = "Hello",
        parameter C_MSG_LEN = 5
    ) (
        

        input rstb,
        input clk,
            

        input send,
        output reg busy,
        

        input txBusy,
        output reg txSend,
        output [C_UART_DATA_WIDTH - 1 : 0] txData,
        input txErr
    );
    
    





    localparam sIDLE    = 2'b00;
    localparam sWAIT    = 2'b01;
    localparam sCOUNT   = 2'b10;
	localparam sSEND    = 2'b11;
	

	localparam C_MSG_LEN_WIDTH = $clog2(C_MSG_LEN);
	
	





    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
    

    reg [C_MSG_LEN_WIDTH - 1 : 0] rCharCount = {(C_MSG_LEN_WIDTH){1'b0}};
    

    reg [8 * C_MSG_LEN - 1 : 0] rMsg = C_MSG;
    
    





    assign txData = rMsg[8 * (C_MSG_LEN - rCharCount) +: 8];
    

    





    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, txBusy, send) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (send == 1'b1) ? sWAIT : sIDLE; 
            end


            sWAIT: begin
                rNext <= (txBusy == 1'b1) ? sWAIT : sCOUNT;
            end



            sCOUNT: begin
                rNext <= (rCharCount < C_MSG_LEN) ? sSEND : sIDLE;
            end
            


            sSEND: begin
                rNext <= (txBusy) ? sWAIT : sSEND;
            end
        endcase    
    end
    




    always @(posedge clk) begin  
        

        if (rState == sCOUNT) rCharCount <= rCharCount + 1;


        else if (rState == sIDLE) rCharCount <= {(C_MSG_LEN){1'b0}};
    end
    
    




    





    always @(posedge clk) begin  
        

        busy <= (rState == sIDLE) ? 1'b0 : 1'b1;
        

        txSend <= (rState == sSEND) ? 1'b1 : 1'b0;
        
    end

endmodule
module  UART_Hello # (
        parameter C_UART_DATA_WIDTH = 8,
        parameter C_MSG = "Hello",
        parameter C_MSG_LEN = 5
    ) (
        

        input rstb,
        input clk,
            

        input send,
        output reg busy,
        

        input txBusy,
        output reg txSend,
        output [C_UART_DATA_WIDTH - 1 : 0] txData,
        input txErr
    );

    
    





    localparam sIDLE    = 2'b00;
    localparam sWAIT    = 2'b01;
    localparam sCOUNT   = 2'b10;
	localparam sSEND    = 2'b11;
	

	localparam C_MSG_LEN_WIDTH = $clog2(C_MSG_LEN);
	
	





    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
    

    reg [C_MSG_LEN_WIDTH - 1 : 0] rCharCount = {(C_MSG_LEN_WIDTH){1'b0}};
    

    reg [8 * C_MSG_LEN - 1 : 0] rMsg = C_MSG;
    
    





    assign txData = rMsg[8 * (C_MSG_LEN - rCharCount) +: 8];
    

    





    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, txBusy, send) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (send == 1'b1) ? sWAIT : sIDLE; 
            end


            sWAIT: begin
                rNext <= (txBusy == 1'b1) ? sWAIT : sCOUNT;
            end



            sCOUNT: begin
                rNext <= (rCharCount < C_MSG_LEN) ? sSEND : sIDLE;
            end
            


            sSEND: begin
                rNext <= (txBusy) ? sWAIT : sSEND;
            end
        endcase    
    end
    




    always @(posedge clk) begin  
        

        if (rState == sCOUNT) rCharCount <= rCharCount + 1;


        else if (rState == sIDLE) rCharCount <= {(C_MSG_LEN){1'b0}};
    end
    
    




    





    always @(posedge clk) begin  
        

        busy <= (rState == sIDLE) ? 1'b0 : 1'b1;
        

        txSend <= (rState == sSEND) ? 1'b1 : 1'b0;
        
    end

endmodule