data/full_repos/permissive/443867168/Verilog/CLA.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:33: Signal definition not found, creating implicitly: \'w0\'\n                                                                        : ... Suggested alternative: \'w1\'\n    and AND0(w0,p[0],Cin);\n             ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:36: Signal definition not found, creating implicitly: \'w11\'\n                                                                        : ... Suggested alternative: \'w1\'\n    and AND11(w11,p[1],p[0],Cin);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:37: Signal definition not found, creating implicitly: \'w12\'\n                                                                        : ... Suggested alternative: \'w1\'\n    and AND12(w12,p[1],g[0]);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:42: Signal definition not found, creating implicitly: \'w21\'\n                                                                        : ... Suggested alternative: \'w1\'\n    and AND21(w21,p[2],p[1],p[0],Cin);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:43: Signal definition not found, creating implicitly: \'w22\'\n                                                                        : ... Suggested alternative: \'w12\'\n    and AND22(w22,p[2],p[1],g[0]);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:44: Signal definition not found, creating implicitly: \'w23\'\n                                                                        : ... Suggested alternative: \'w2\'\n    and AND23(w23,p[2],g[1]);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:49: Signal definition not found, creating implicitly: \'w31\'\n                                                                        : ... Suggested alternative: \'w1\'\n    and AND31(w31,p[3],p[2],p[1],p[0],Cin);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:50: Signal definition not found, creating implicitly: \'w32\'\n                                                                        : ... Suggested alternative: \'w12\'\n    and AND32(w32,p[3],p[2],p[1],g[0]);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:51: Signal definition not found, creating implicitly: \'w33\'\n                                                                        : ... Suggested alternative: \'w23\'\n    and AND33(w33,p[3],p[2],g[1]);\n              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/443867168/Verilog/CLA.v:52: Signal definition not found, creating implicitly: \'w34\'\n                                                                        : ... Suggested alternative: \'w3\'\n    and AND34(w34,p[3],g[2]);\n              ^~~\n%Error: Exiting due to 10 warning(s)\n'
module CLA (a,b,Cin,sum,carry);


    input [3:0] a;
    input [3:0] b;
    input Cin;


    output [3:0] sum;
    output [3:0] carry;



    wire [3:0] p;

    wire [3:0] g;
    wire w1,w2,w3,w4;


    and GEN0(g[0],a[0],b[0]); 
    and GEN1(g[1],a[1],b[1]);
    and GEN2(g[2],a[2],b[2]); 
    and GEN3(g[3],a[3],b[3]);


    xor PROP0(p[0],a[0],b[0]);
    xor PROP1(p[1],a[1],b[1]);
    xor PROP2(p[2],a[2],b[2]);
    xor PROP3(p[3],a[3],b[3]);


    and AND0(w0,p[0],Cin);
    or OR0(carry[0],w0,g[0]);

    and AND11(w11,p[1],p[0],Cin);
    and AND12(w12,p[1],g[0]);
    or OR1(carry[1],w11,w12,g[1]);



    and AND21(w21,p[2],p[1],p[0],Cin);
    and AND22(w22,p[2],p[1],g[0]);
    and AND23(w23,p[2],g[1]);
    or OR2(carry[2],w21,w22,w23,g[2]);



    and AND31(w31,p[3],p[2],p[1],p[0],Cin);
    and AND32(w32,p[3],p[2],p[1],g[0]);
    and AND33(w33,p[3],p[2],g[1]);
    and AND34(w34,p[3],g[2]);
    or OR3(carry[3],w31,w32,w33,w34,g[3]);




    xor SUM0(sum[0],p[0],Cin);
    xor SUM1(sum[1],p[1],carry[0]);
    xor SUM2(sum[2],p[2],carry[1]);
    xor SUM3(sum[3],p[3],carry[2]);

endmodule
module CLA (a,b,Cin,sum,carry);



    input [3:0] a;
    input [3:0] b;
    input Cin;


    output [3:0] sum;
    output [3:0] carry;



    wire [3:0] p;

    wire [3:0] g;
    wire w1,w2,w3,w4;


    and GEN0(g[0],a[0],b[0]); 
    and GEN1(g[1],a[1],b[1]);
    and GEN2(g[2],a[2],b[2]); 
    and GEN3(g[3],a[3],b[3]);


    xor PROP0(p[0],a[0],b[0]);
    xor PROP1(p[1],a[1],b[1]);
    xor PROP2(p[2],a[2],b[2]);
    xor PROP3(p[3],a[3],b[3]);


    and AND0(w0,p[0],Cin);
    or OR0(carry[0],w0,g[0]);

    and AND11(w11,p[1],p[0],Cin);
    and AND12(w12,p[1],g[0]);
    or OR1(carry[1],w11,w12,g[1]);



    and AND21(w21,p[2],p[1],p[0],Cin);
    and AND22(w22,p[2],p[1],g[0]);
    and AND23(w23,p[2],g[1]);
    or OR2(carry[2],w21,w22,w23,g[2]);



    and AND31(w31,p[3],p[2],p[1],p[0],Cin);
    and AND32(w32,p[3],p[2],p[1],g[0]);
    and AND33(w33,p[3],p[2],g[1]);
    and AND34(w34,p[3],g[2]);
    or OR3(carry[3],w31,w32,w33,w34,g[3]);




    xor SUM0(sum[0],p[0],Cin);
    xor SUM1(sum[1],p[1],carry[0]);
    xor SUM2(sum[2],p[2],carry[1]);
    xor SUM3(sum[3],p[3],carry[2]);

endmodule