data/full_repos/permissive/429196919/FPGA/pwm/pwm.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:35: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/pwm,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:45: Define or directive not defined: \'`K1_25_PWM_STEP\'\n reg[$clog2(`K1_25_PWM_STEP*PRESCALE)-1:0] cycleCnt = 0;        \n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:45: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n reg[$clog2(`K1_25_PWM_STEP*PRESCALE)-1:0] cycleCnt = 0;        \n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:74: Define or directive not defined: \'`K1_25_PWM_STEP\'\n  else if(cycleCnt >= `K1_25_PWM_STEP*PRESCALE) begin        \n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:74: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n  else if(cycleCnt >= `K1_25_PWM_STEP*PRESCALE) begin        \n                                     ^\n%Error: data/full_repos/permissive/429196919/FPGA/pwm/pwm.v:78: syntax error, unexpected else\n  else if(stepCnt >= control) begin            \n  ^~~~\n%Error: Cannot continue\n'
module pwm	#(parameter PRESCALE = 1)
			(input wire[7:0] controlInput,
			 input load,
			 input masterClk,
			 output reg pwmOut);

	reg[7:0] control = 8'b0;
	reg[$clog2(`K1_25_PWM_STEP*PRESCALE)-1:0] cycleCnt = 0;
	reg[7:0] stepCnt = 8'b0;




	reg prevLoad;
	always @(posedge masterClk) begin
		prevLoad <= load;
	end
	`define PWM_LOAD_POSEDGE (load && !prevLoad)
	`define PWM_LOAD_NEGEDGE (!load && prevLoad)





	always @(posedge masterClk) begin
		if(`PWM_LOAD_POSEDGE) begin
			control <= controlInput;
		end
		else if(stepCnt == 8'hFF) begin
			cycleCnt <= 0;									
			stepCnt <= 0;
			if(control != 0)
				pwmOut <= 1'b1;
			else
				pwmOut <= 1'b0;
		end
		else if(cycleCnt >= `K1_25_PWM_STEP*PRESCALE) begin
			cycleCnt <= 0;
			stepCnt <= stepCnt + 1'b1;			
		end
		else if(stepCnt >= control) begin
			pwmOut <= 1'b0;
			cycleCnt <= cycleCnt + 1'b1;
		end
		else
			cycleCnt <= cycleCnt + 1'b1;
	end
endmodule
module pwm	#(parameter PRESCALE = 1)
			(input wire[7:0] controlInput,
			 input load,
			 input masterClk,
			 output reg pwmOut);


	reg[7:0] control = 8'b0;
	reg[$clog2(`K1_25_PWM_STEP*PRESCALE)-1:0] cycleCnt = 0;
	reg[7:0] stepCnt = 8'b0;




	reg prevLoad;
	always @(posedge masterClk) begin
		prevLoad <= load;
	end
	`define PWM_LOAD_POSEDGE (load && !prevLoad)
	`define PWM_LOAD_NEGEDGE (!load && prevLoad)





	always @(posedge masterClk) begin
		if(`PWM_LOAD_POSEDGE) begin
			control <= controlInput;
		end
		else if(stepCnt == 8'hFF) begin
			cycleCnt <= 0;									
			stepCnt <= 0;
			if(control != 0)
				pwmOut <= 1'b1;
			else
				pwmOut <= 1'b0;
		end
		else if(cycleCnt >= `K1_25_PWM_STEP*PRESCALE) begin
			cycleCnt <= 0;
			stepCnt <= stepCnt + 1'b1;			
		end
		else if(stepCnt >= control) begin
			pwmOut <= 1'b0;
			cycleCnt <= cycleCnt + 1'b1;
		end
		else
			cycleCnt <= cycleCnt + 1'b1;
	end
endmodule