data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/ram16.v
data/verilator_xmls/9a976857-c9b2-4dee-8e67-346dbb1289f9.xml
module ram16 (input clock, input write, 
	      input [3:0] wr_addr, input [15:0] wr_data,
	      input [3:0] rd_addr, output reg [15:0] rd_data);

   reg [15:0] 		ram_array [0:15];

   always @(posedge clock)
     rd_data <= #1 ram_array[rd_addr];

   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;

endmodule
module ram16 (input clock, input write, 
	      input [3:0] wr_addr, input [15:0] wr_data,
	      input [3:0] rd_addr, output reg [15:0] rd_data);


   reg [15:0] 		ram_array [0:15];

   always @(posedge clock)
     rd_data <= #1 ram_array[rd_addr];

   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;

endmodule