data/full_repos/permissive/527176783/Pipeline/noop_reg.v
data/verilator_xmls/4dea63d0-b93a-4d54-a4e3-5d4b81b90f93.xml
module noop_reg(
    input clk,
    input [31:0] noop_in,
    output reg [31:0] noop_out
);
    always @(posedge clk) begin
        noop_out <= noop_in;
    end

endmodule
module noop_reg(
    input clk,
    input [31:0] noop_in,
    output reg [31:0] noop_out
);

    always @(posedge clk) begin
        noop_out <= noop_in;
    end

endmodule