data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:15: Unsupported: Ignoring delay on this delayed statement.\n forever #(0.5) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:32: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:75: Unsupported: Ignoring delay on this delayed statement.\n  #0.1;\n  ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:76: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:77: Unsupported: Ignoring delay on this delayed statement.\n  #0.1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:110: Unsupported: Ignoring delay on this delayed statement.\n #0.3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:115: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:139: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.lxt");   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_YD_reg.sv:140: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);    \n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_YD_reg();

parameter DW=16;
parameter AW=4;

logic clk,rst,jpc,we0,we1;
logic [DW-1:0]din0,din1,dout0,dout1;
logic [AW-1:0]waddr0,waddr1,raddr0,raddr1;
logic we;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	jpc <= 0;
	din0 <= 0;
	din1 <= 0;
	waddr0 <= 0;
	waddr1 <= 0;
	raddr1 <= 0;
	raddr0 <= 0;
	we0 <= 0;
	we1 <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst


task write_d0;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we0=1;
		waddr0=w_addr;
		din0=w_data;
	end
endtask : write_d0

task write_d1;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we1=1;
		waddr1=w_addr;
		din1=w_data;
	end
endtask : write_d1

task read_d0;
	input [AW-1:0]r_addr;
	begin
		raddr0=r_addr;
	end
endtask : read_d0

task read_d1;
	input [AW-1:0]r_addr;
	begin
		raddr1=r_addr;
	end
endtask : read_d1

task ckpos();
	begin
		#0.1;
		@(posedge clk);
		#0.1;
		we0=0;
		we1=0;
	end
endtask : ckpos

initial begin
	sysrst(1);
	#1;
	write_d0(4'h1,16'h31);
	write_d1(4'h2,16'h32);
	read_d0(4'h2);
	read_d1(4'h1);
	ckpos();
	write_d0(4'h3,16'hA1);
	write_d1(4'h4,16'hA2);
	read_d0(4'h3);
	read_d1(4'h1);
	ckpos();
	read_d0(4'hF);
	read_d1(4'h4);
	ckpos();
	write_d0(4'hF,16'h1FFF);
	read_d0(4'h0);
	read_d1(4'h3);
	ckpos();
	jpc=1;
	write_d0(4'hF,16'h1FFF);
	write_d1(4'h1,16'h100F);
	read_d0(4'hF);
	read_d1(4'h4);
	ckpos();
	jpc=0;
	#0.3;
	read_d0(4'h1);
	read_d1(4'h2);


	#10
	$finish;
end


YD_reg test (
	.clk    (clk),
	.rst    (rst),
	.jpc    (jpc),
	.din0   (din0),
	.waddr0 (waddr0),
	.we0    (we0),
	.din1   (din1),
	.waddr1 (waddr1),
	.we1    (we1),
	.raddr0 (raddr0),
	.dout0  (dout0),
	.raddr1 (raddr1),
	.dout1  (dout1)
);



initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule
module tb_YD_reg();


parameter DW=16;
parameter AW=4;

logic clk,rst,jpc,we0,we1;
logic [DW-1:0]din0,din1,dout0,dout1;
logic [AW-1:0]waddr0,waddr1,raddr0,raddr1;
logic we;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	jpc <= 0;
	din0 <= 0;
	din1 <= 0;
	waddr0 <= 0;
	waddr1 <= 0;
	raddr1 <= 0;
	raddr0 <= 0;
	we0 <= 0;
	we1 <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst


task write_d0;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we0=1;
		waddr0=w_addr;
		din0=w_data;
	end
endtask : write_d0

task write_d1;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we1=1;
		waddr1=w_addr;
		din1=w_data;
	end
endtask : write_d1

task read_d0;
	input [AW-1:0]r_addr;
	begin
		raddr0=r_addr;
	end
endtask : read_d0

task read_d1;
	input [AW-1:0]r_addr;
	begin
		raddr1=r_addr;
	end
endtask : read_d1

task ckpos();
	begin
		#0.1;
		@(posedge clk);
		#0.1;
		we0=0;
		we1=0;
	end
endtask : ckpos

initial begin
	sysrst(1);
	#1;
	write_d0(4'h1,16'h31);
	write_d1(4'h2,16'h32);
	read_d0(4'h2);
	read_d1(4'h1);
	ckpos();
	write_d0(4'h3,16'hA1);
	write_d1(4'h4,16'hA2);
	read_d0(4'h3);
	read_d1(4'h1);
	ckpos();
	read_d0(4'hF);
	read_d1(4'h4);
	ckpos();
	write_d0(4'hF,16'h1FFF);
	read_d0(4'h0);
	read_d1(4'h3);
	ckpos();
	jpc=1;
	write_d0(4'hF,16'h1FFF);
	write_d1(4'h1,16'h100F);
	read_d0(4'hF);
	read_d1(4'h4);
	ckpos();
	jpc=0;
	#0.3;
	read_d0(4'h1);
	read_d1(4'h2);


	#10
	$finish;
end


YD_reg test (
	.clk    (clk),
	.rst    (rst),
	.jpc    (jpc),
	.din0   (din0),
	.waddr0 (waddr0),
	.we0    (we0),
	.din1   (din1),
	.waddr1 (waddr1),
	.we1    (we1),
	.raddr0 (raddr0),
	.dout0  (dout0),
	.raddr1 (raddr1),
	.dout1  (dout1)
);



initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule