data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:11: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 Sel = 1; #1 IN =0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 Sel = 1; #1 IN =0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #2 Sel = 1; #2 IN =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #2 Sel = 1; #2 IN =1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:18: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:22: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("Buffer32_32TestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:23: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,Buffer32_32TestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Buffer32_32/Buffer32_32TestBench.v:25: Unsupported or unknown PLI call: $monitor\n $monitor("T = %3d,Sel = %1b, Out = %5b",$time,Sel,OUT);   \n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Buffer32_32TestBench;

parameter sim_time = 750*2;

reg [31:0] IN;
reg Sel;
wire [31:0] OUT;

Buffer32_32 buffer(IN,Sel,OUT);

initial fork
		Sel = 0; IN =0;
		#1 Sel = 1; #1 IN =0;
		#2 Sel = 1; #2 IN =1;
join

	
initial #sim_time $finish;


initial begin
	$dumpfile("Buffer32_32TestBench.vcd");
	$dumpvars(0,Buffer32_32TestBench);
	$display(" Test Results" );
	$monitor("T = %3d,Sel = %1b, Out = %5b",$time,Sel,OUT);
end

endmodule
module Buffer32_32TestBench;


parameter sim_time = 750*2;

reg [31:0] IN;
reg Sel;
wire [31:0] OUT;

Buffer32_32 buffer(IN,Sel,OUT);

initial fork
		Sel = 0; IN =0;
		#1 Sel = 1; #1 IN =0;
		#2 Sel = 1; #2 IN =1;
join

	
initial #sim_time $finish;


initial begin
	$dumpfile("Buffer32_32TestBench.vcd");
	$dumpvars(0,Buffer32_32TestBench);
	$display(" Test Results" );
	$monitor("T = %3d,Sel = %1b, Out = %5b",$time,Sel,OUT);
end

endmodule