data/full_repos/permissive/514519566/pipeline/src/simulation/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514519566/pipeline/src/simulation/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514519566/pipeline/src/simulation/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/514519566/pipeline/src/simulation/tb.v:10: Cannot find file containing module: \'CPU\'\n CPU cpu1(reset, clk, leds, digitalTube);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/514519566/pipeline/src/simulation,data/full_repos/permissive/514519566/CPU\n             data/full_repos/permissive/514519566/pipeline/src/simulation,data/full_repos/permissive/514519566/CPU.v\n             data/full_repos/permissive/514519566/pipeline/src/simulation,data/full_repos/permissive/514519566/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_cpu();
	
	reg reset;
	reg clk;
	wire [7:0] leds;
	wire [11:0] digitalTube;
	
	CPU cpu1(reset, clk, leds, digitalTube);
	
	initial begin
		reset = 1;
		clk = 1;
		#100 reset = 0;
	end
	
	always #50 clk = ~clk;
		
endmodule
module test_cpu();

	
	reg reset;
	reg clk;
	wire [7:0] leds;
	wire [11:0] digitalTube;
	
	CPU cpu1(reset, clk, leds, digitalTube);
	
	initial begin
		reset = 1;
		clk = 1;
		#100 reset = 0;
	end
	
	always #50 clk = ~clk;
		
endmodule