data/full_repos/permissive/472196771/verilog/rtl/src/pipeline_ctrl.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/472196771/verilog/rtl/src/pipeline_ctrl.v:11: Little bit endian vector: MSB < LSB of bit range: 0:4\n  reg [0:WIDTH] valid = 0;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pipeline_ctrl(
  input   i_clk,
  input   i_enable,
  output  o_ack
);
  parameter WIDTH = 4;
  reg [0:WIDTH] valid = 0;

  assign o_ack = valid[WIDTH];

  integer i;
  initial begin
    valid = 0;
  end
  
  always @(posedge i_clk)
  begin
    valid[0] <= i_enable;

    for (i = 1; i <= WIDTH; i = i+1)
      valid[i] <= valid[i - 1];
  
  end

endmodule
module pipeline_ctrl(
  input   i_clk,
  input   i_enable,
  output  o_ack
);

  parameter WIDTH = 4;
  reg [0:WIDTH] valid = 0;

  assign o_ack = valid[WIDTH];

  integer i;
  initial begin
    valid = 0;
  end
  
  always @(posedge i_clk)
  begin
    valid[0] <= i_enable;

    for (i = 1; i <= WIDTH; i = i+1)
      valid[i] <= valid[i - 1];
  
  end

endmodule