data/full_repos/permissive/418819021/lab-02/checker_t.v
1: b'%Error: data/full_repos/permissive/418819021/lab-02/checker_t.v:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-02/checker_t.v:8: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n    output wire [`TEST_I_ADDR_WIDTH - 1:0] test,\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/checker_t.v:26: Define or directive not defined: \'`TEST_INSTR_WIDTH\'\n        .INSTR_WIDTH(`TEST_INSTR_WIDTH),\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/checker_t.v:27: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n        .DATA_WIDTH(`TEST_DATA_WIDTH),\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/checker_t.v:28: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n        .I_ADDR_WIDTH(`TEST_I_ADDR_WIDTH)\n                      ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module checker_t (
    output wire [`TEST_I_ADDR_WIDTH - 1:0] test,
    output reg                             result,
    input  wire                            clk,
    input  wire                            reset
);

`ifdef DEBUG
    wire [`STAGE_COUNT - 1:0]       debug_pipeline_stage;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_rr;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_rd;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_out;
    wire [`TEST_I_ADDR_WIDTH - 1:0] debug_program_counter;
    wire [`FLAG_COUNT - 1:0]        debug_flags_out;
`endif



    cpu #(
        .INSTR_WIDTH(`TEST_INSTR_WIDTH),
        .DATA_WIDTH(`TEST_DATA_WIDTH),
        .I_ADDR_WIDTH(`TEST_I_ADDR_WIDTH)
    ) uut (
        .clk(clk),
        .reset(reset)
`ifdef DEBUG
        ,
        .debug_pipeline_stage(debug_pipeline_stage),
        .debug_alu_rr(debug_alu_rr),
        .debug_alu_rd(debug_alu_rd),
        .debug_alu_out(debug_alu_out),
        .debug_program_counter(debug_program_counter),
        .debug_flags_out(debug_flags_out)
`endif
    );

    assign test = debug_program_counter;

    always @(*) begin






        case(debug_program_counter)
            0: begin

                if (debug_flags_out == 8'b0000_0000 && debug_alu_rr === 8'bz &&
                        debug_alu_rd === 8'bz && debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end
                
            1: begin

                if (debug_flags_out == 8'b0000_0001 && debug_alu_rd == 254 
                            && debug_alu_out == 2 && debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            2: begin

                if (debug_flags_out == 8'b0001_0100 && debug_alu_rr == 253 &&
                        debug_alu_rd == 2 && debug_alu_out == 255 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            3: begin

                if (debug_flags_out == 8'b0000_0000 && debug_alu_rr == 253 &&
                        debug_alu_rd == 255 && debug_alu_out == 2 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            4: begin

                if (debug_flags_out == 8'b0000_0010 && debug_alu_rr == 253 &&
                        debug_alu_rd == 2 && debug_alu_out == 0 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            5: begin

                if (debug_flags_out == 8'b0001_0100 && debug_alu_rr == 253 &&
                        debug_alu_rd == 0 && debug_alu_out == 253 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            default:
                result = 1'b1;
        endcase
    end
endmodule
module checker_t (
    output wire [`TEST_I_ADDR_WIDTH - 1:0] test,
    output reg                             result,
    input  wire                            clk,
    input  wire                            reset
);


`ifdef DEBUG
    wire [`STAGE_COUNT - 1:0]       debug_pipeline_stage;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_rr;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_rd;
    wire [`TEST_DATA_WIDTH - 1:0]   debug_alu_out;
    wire [`TEST_I_ADDR_WIDTH - 1:0] debug_program_counter;
    wire [`FLAG_COUNT - 1:0]        debug_flags_out;
`endif



    cpu #(
        .INSTR_WIDTH(`TEST_INSTR_WIDTH),
        .DATA_WIDTH(`TEST_DATA_WIDTH),
        .I_ADDR_WIDTH(`TEST_I_ADDR_WIDTH)
    ) uut (
        .clk(clk),
        .reset(reset)
`ifdef DEBUG
        ,
        .debug_pipeline_stage(debug_pipeline_stage),
        .debug_alu_rr(debug_alu_rr),
        .debug_alu_rd(debug_alu_rd),
        .debug_alu_out(debug_alu_out),
        .debug_program_counter(debug_program_counter),
        .debug_flags_out(debug_flags_out)
`endif
    );

    assign test = debug_program_counter;

    always @(*) begin






        case(debug_program_counter)
            0: begin

                if (debug_flags_out == 8'b0000_0000 && debug_alu_rr === 8'bz &&
                        debug_alu_rd === 8'bz && debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end
                
            1: begin

                if (debug_flags_out == 8'b0000_0001 && debug_alu_rd == 254 
                            && debug_alu_out == 2 && debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            2: begin

                if (debug_flags_out == 8'b0001_0100 && debug_alu_rr == 253 &&
                        debug_alu_rd == 2 && debug_alu_out == 255 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            3: begin

                if (debug_flags_out == 8'b0000_0000 && debug_alu_rr == 253 &&
                        debug_alu_rd == 255 && debug_alu_out == 2 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            4: begin

                if (debug_flags_out == 8'b0000_0010 && debug_alu_rr == 253 &&
                        debug_alu_rd == 2 && debug_alu_out == 0 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            5: begin

                if (debug_flags_out == 8'b0001_0100 && debug_alu_rr == 253 &&
                        debug_alu_rd == 0 && debug_alu_out == 253 &&
                        debug_pipeline_stage == 3)
                    result = 1'b1;
                else if (debug_pipeline_stage != 3)
                    result = 1'b1;
                else
                    result = 1'bx;
            end

            default:
                result = 1'b1;
        endcase
    end
endmodule