data/full_repos/permissive/503973366/SIM/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:48: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:55: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:60: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:66: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:72: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:77: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/counter_tb.v:83: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/counter_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: Exiting due to 7 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Counter_TB #(

    parameter COUNT_NUM = 16
    )
    (


    );
    
    reg     clk;
    reg     rst_n;
    reg     start_i;
    
    wire    done_o;
    

    Counter #(
        .COUNT_NUM ( COUNT_NUM )
    ) COUNTER_DUT (
        .clk     ( clk     ),
        .rst_n   ( rst_n   ),
        .start_i ( start_i ),
        .done_o  ( done_o  )
    );



    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end


    initial begin
        rst_n = 'b0;
        start_i = 'b0;
    end

    initial begin


        @(posedge clk);
        #(`DELTA)
        rst_n = 'b1;
        

        

        @(posedge clk);
        #(`DELTA)
        start_i = 1'b1;
        
        repeat (COUNT_NUM) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        
        repeat (3) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        

        @(posedge clk);
        #(`DELTA)
        start_i = 1'b1;
        
        repeat (COUNT_NUM) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        
        repeat (3) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
    end
    
endmodule
module Counter_TB #(

    parameter COUNT_NUM = 16
    )
    (


    );

    
    reg     clk;
    reg     rst_n;
    reg     start_i;
    
    wire    done_o;
    

    Counter #(
        .COUNT_NUM ( COUNT_NUM )
    ) COUNTER_DUT (
        .clk     ( clk     ),
        .rst_n   ( rst_n   ),
        .start_i ( start_i ),
        .done_o  ( done_o  )
    );



    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end


    initial begin
        rst_n = 'b0;
        start_i = 'b0;
    end

    initial begin


        @(posedge clk);
        #(`DELTA)
        rst_n = 'b1;
        

        

        @(posedge clk);
        #(`DELTA)
        start_i = 1'b1;
        
        repeat (COUNT_NUM) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        
        repeat (3) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        

        @(posedge clk);
        #(`DELTA)
        start_i = 1'b1;
        
        repeat (COUNT_NUM) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
        
        repeat (3) begin
            @(posedge clk);
            #(`DELTA)
            start_i = 1'b0;
        end
    end
    
endmodule