data/full_repos/permissive/485129576/mux4t1.v
data/verilator_xmls/4639b658-9628-43b2-a27c-54744b451301.xml
module MUX4t1 (
    input [7:0] A,
    input [7:0] B,
    input [7:0] C,
    input [7:0] D,
    input [1:0] sel,
    output reg [7:0] R
);
    always @(*) begin
        case(sel)
            2'b00 : R = A;
            2'b01 : R = B;
            2'b10 : R = C;
            2'b11 : R = D;
        endcase
    end

endmodule
module MUX4t1 (
    input [7:0] A,
    input [7:0] B,
    input [7:0] C,
    input [7:0] D,
    input [1:0] sel,
    output reg [7:0] R
);

    always @(*) begin
        case(sel)
            2'b00 : R = A;
            2'b01 : R = B;
            2'b10 : R = C;
            2'b11 : R = D;
        endcase
    end

endmodule