data/full_repos/permissive/437157208/src/TB_Datapath.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/437157208/src/TB_Datapath.v:23: Unsupported: Ignoring delay on this delayed statement.\n forever #2 clk_tb = !clk_tb;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/437157208/src/TB_Datapath.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 reset_tb = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/437157208/src/TB_Datapath.v:29: Unsupported: Ignoring delay on this delayed statement.\n #3 reset_tb = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/437157208/src/TB_Datapath.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 reset_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/437157208/src/TB_Datapath.v:9: Cannot find file containing module: \'Data_Path\'\nData_Path DUT\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Path\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Path.v\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/Data_Path.sv\n             Data_Path\n             Data_Path.v\n             Data_Path.sv\n             obj_dir/Data_Path\n             obj_dir/Data_Path.v\n             obj_dir/Data_Path.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_Datapath;

reg 	clk_tb = 0;
reg 	reset_tb;
reg  [7:0] GPIO_i_tb;
wire [7:0] GPIO_o_tb;
wire 	clk_signal_tb;

Data_Path DUT
(

	.clk(clk_tb),
 	.reset(reset_tb),
 	.GPIO_i(GPIO_i_tb),

	.clk_signal(clk_signal_tb),
	.GPIO_o(GPIO_o_tb)
);


initial 
begin
	forever #2 clk_tb = !clk_tb;
end


initial begin
	#1 reset_tb = 1'b1;
	#3 reset_tb = 1'b0;
	#3 reset_tb = 1'b1;
	GPIO_i_tb = 8'h3;
end

















endmodule
module TB_Datapath;


reg 	clk_tb = 0;
reg 	reset_tb;
reg  [7:0] GPIO_i_tb;
wire [7:0] GPIO_o_tb;
wire 	clk_signal_tb;

Data_Path DUT
(

	.clk(clk_tb),
 	.reset(reset_tb),
 	.GPIO_i(GPIO_i_tb),

	.clk_signal(clk_signal_tb),
	.GPIO_o(GPIO_o_tb)
);


initial 
begin
	forever #2 clk_tb = !clk_tb;
end


initial begin
	#1 reset_tb = 1'b1;
	#3 reset_tb = 1'b0;
	#3 reset_tb = 1'b1;
	GPIO_i_tb = 8'h3;
end

















endmodule