data/full_repos/permissive/490716708/Verilog/iCE40.v
1: b'%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:2: Cannot find include file: CPU6.v\n`include "CPU6.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.sv\n             CPU6.v\n             CPU6.v.v\n             CPU6.v.sv\n             obj_dir/CPU6.v\n             obj_dir/CPU6.v.v\n             obj_dir/CPU6.v.sv\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:3: Cannot find include file: LEDPanel.v\n`include "LEDPanel.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:4: Cannot find include file: PLL.v\n`include "PLL.v" \n         ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module Divide4(input wire clock_in, output wire clock_out);
    reg [1:0] counter;
    assign clock_out = counter[1];
    always @(posedge clock_in) begin
        counter <= counter + 1;
    end
endmodule
module Divide4(input wire clock_in, output wire clock_out);

    reg [1:0] counter;
    assign clock_out = counter[1];
    always @(posedge clock_in) begin
        counter <= counter + 1;
    end
endmodule