data/full_repos/permissive/52714256/INTERFACES/src/CAN/can.v
1: b"%Error: data/full_repos/permissive/52714256/INTERFACES/src/CAN/can.v:47: Cannot find file containing module: 'queue'\n    queue Q_TX (\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/INTERFACES/src/CAN,data/full_repos/permissive/52714256/queue\n             data/full_repos/permissive/52714256/INTERFACES/src/CAN,data/full_repos/permissive/52714256/queue.v\n             data/full_repos/permissive/52714256/INTERFACES/src/CAN,data/full_repos/permissive/52714256/queue.sv\n             queue\n             queue.v\n             queue.sv\n             obj_dir/queue\n             obj_dir/queue.v\n             obj_dir/queue.sv\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/CAN/can.v:57: Cannot find file containing module: 'queue'\n    queue Q_RX (\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module can
    (
    input wire GCLK,
    inout wire CANH,
    inout wire CANL,
    input wire RES,

    input wire [107:0] tx_q,
    input wire tx_q_push,
    output wire tx_q_ovf,

    output reg [107:0] rx_q,
    input wire rx_q_pull,
    output wire rx_q_ovf
    );
    
    assign CANL = ~CANH;
    
    reg [107:0] to_transmit_buf;
    reg [107:0] to_receive_buf;

    wire refresh_tx;
    wire refresh_rx;
    
    queue Q_TX (
        .GCLK(GCLK),
        .RES(RES),
        .get(refresh_tx),
        .put(tx_q_push),
        .full(tx_q_ovf),
        .DIN(tx_q),
        .DOUT(to_transmit_buf)
    );
    
    queue Q_RX (
        .GCLK(GCLK),
        .RES(RES),
        .get(rx_q_pull),
        .put(refresh_rx),
        .full(rx_q_ovf),
        .DIN(to_receive_buf),
        .DOUT(rx_q)
    );
    
    
    
    
endmodule
module can
    (
    input wire GCLK,
    inout wire CANH,
    inout wire CANL,
    input wire RES,

    input wire [107:0] tx_q,
    input wire tx_q_push,
    output wire tx_q_ovf,

    output reg [107:0] rx_q,
    input wire rx_q_pull,
    output wire rx_q_ovf
    );

    
    assign CANL = ~CANH;
    
    reg [107:0] to_transmit_buf;
    reg [107:0] to_receive_buf;

    wire refresh_tx;
    wire refresh_rx;
    
    queue Q_TX (
        .GCLK(GCLK),
        .RES(RES),
        .get(refresh_tx),
        .put(tx_q_push),
        .full(tx_q_ovf),
        .DIN(tx_q),
        .DOUT(to_transmit_buf)
    );
    
    queue Q_RX (
        .GCLK(GCLK),
        .RES(RES),
        .get(rx_q_pull),
        .put(refresh_rx),
        .full(rx_q_ovf),
        .DIN(to_receive_buf),
        .DOUT(rx_q)
    );
    
    
    
    
endmodule