data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:8: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:9: Cannot find include file: rtl/core/pc.v\n`include "rtl/core/pc.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:10: Cannot find include file: rtl/core/if_id.v\n`include "rtl/core/if_id.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:11: Cannot find include file: rtl/core/id.v\n`include "rtl/core/id.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:12: Cannot find include file: rtl/core/regs.v\n`include "rtl/core/regs.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:13: Cannot find include file: rtl/core/ex.v\n`include "rtl/core/ex.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:14: Cannot find include file: rtl/core/ctrl.v\n`include "rtl/core/ctrl.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:15: Cannot find include file: rtl/core/trans.v\n`include "rtl/core/trans.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:16: Cannot find include file: rtl/core/id_ex.v\n`include "rtl/core/id_ex.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:17: Cannot find include file: rtl/core/mem_wb.v\n`include "rtl/core/mem_wb.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:18: Cannot find include file: rtl/core/ex_memwb.v\n`include "rtl/core/ex_memwb.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:25: Define or directive not defined: \'`inst_bus\'\n    input wire [`inst_bus]          inst_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`inst_bus]          inst_i,\n                         ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:26: Define or directive not defined: \'`inst_addr_bus\'\n    output wire [`inst_addr_bus]    inst_addr_o,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                     mem_r_enable_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                     mem_enable_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`mem_addr_bus]     mem_w_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:31: Define or directive not defined: \'`mem_addr_bus\'\n    output wire [`mem_addr_bus]     mem_w_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:32: Define or directive not defined: \'`mem_addr_bus\'\n    output wire [`mem_addr_bus]     mem_r_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:33: Define or directive not defined: \'`mem_data_bus\'\n    input wire [`mem_data_bus]      mem_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:34: Define or directive not defined: \'`mem_data_bus\'\n    output wire [`mem_data_bus]     mem_data_o\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:37: Define or directive not defined: \'`hold_ctrl_bus\'\n    wire [`hold_ctrl_bus] hold_bus;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`hold_ctrl_bus] hold_bus;\n                        ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:38: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_pc = hold_bus[1:0];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_pc = hold_bus[1:0];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:39: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_if_id = hold_bus[3:2];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_if_id = hold_bus[3:2];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:40: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_id_ex = hold_bus[5:4];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_id_ex = hold_bus[5:4];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:41: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_ex_memwb = hold_bus[7:6];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_ex_memwb = hold_bus[7:6];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:44: Define or directive not defined: \'`inst_addr_bus\'\n    wire [`inst_addr_bus] jump_addr;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`inst_addr_bus] jump_addr;\n                        ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:45: Define or directive not defined: \'`inst_addr_bus\'\n    wire [`inst_addr_bus] pc_inst_addr;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`inst_addr_bus] pc_inst_addr;\n                        ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:61: Define or directive not defined: \'`inst_addr_bus\'\n    wire [`inst_addr_bus] if_id_inst_addr;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`inst_addr_bus] if_id_inst_addr;\n                        ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:62: Define or directive not defined: \'`inst_bus\'\n    wire [`inst_bus] if_id_inst;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`inst_bus] if_id_inst;\n                   ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:76: Define or directive not defined: \'`reg_addr_bus\'\n    wire [`reg_addr_bus] w_reg_addr;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`reg_addr_bus] w_reg_addr;\n                       ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:77: Define or directive not defined: \'`reg_data_bus\'\n    wire [`reg_data_bus] w_reg_data;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:77: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`reg_data_bus] w_reg_data;\n                       ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:78: Define or directive not defined: \'`reg_addr_bus\'\n    wire [`reg_addr_bus] r_reg_addr1;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`reg_addr_bus] r_reg_addr1;\n                       ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:79: Define or directive not defined: \'`reg_data_bus\'\n    wire [`reg_data_bus] r_reg_data1;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:79: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`reg_data_bus] r_reg_data1;\n                       ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:80: Define or directive not defined: \'`reg_addr_bus\'\n    wire [`reg_addr_bus] r_reg_addr2;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:80: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`reg_addr_bus] r_reg_addr2;\n                       ^\n%Error: data/full_repos/permissive/476296842/rtl/core/ayatsuki_core.v:81: Define or directive not defined: \'`reg_data_bus\'\n    wire [`reg_data_bus] r_reg_data2;\n          ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ayatsuki_core (
    input wire                      clk,
    input wire                      rst_n,
    
    input wire [`inst_bus]          inst_i,
    output wire [`inst_addr_bus]    inst_addr_o,

    output wire                     mem_w_enable_o,
    output wire                     mem_r_enable_o,
    output wire                     mem_enable_o,
    output wire [`mem_addr_bus]     mem_w_addr_o,
    output wire [`mem_addr_bus]     mem_r_addr_o,
    input wire [`mem_data_bus]      mem_data_i,
    output wire [`mem_data_bus]     mem_data_o
);

    wire [`hold_ctrl_bus] hold_bus;
    wire [`holdpip_bus] hold_pc = hold_bus[1:0];
    wire [`holdpip_bus] hold_if_id = hold_bus[3:2];
    wire [`holdpip_bus] hold_id_ex = hold_bus[5:4];
    wire [`holdpip_bus] hold_ex_memwb = hold_bus[7:6];

    wire jump_flag;
    wire [`inst_addr_bus] jump_addr;
    wire [`inst_addr_bus] pc_inst_addr;

    assign inst_addr_o = pc_inst_addr;

    pc u_pc(
    	.clk          (clk          ),
        .rst_n        (rst_n        ),
        .jump_flag_i  (jump_flag    ),
        .jump_addr_i  (jump_addr    ),
        .hold_flag_i  (hold_pc      ),
        .pc_o         (pc_inst_addr )

    );

    wire [`inst_addr_bus] if_id_inst_addr;
    wire [`inst_bus] if_id_inst;

    if_id u_if_id(
    	.clk         (clk               ),
        .rst_n       (rst_n             ),
        .hold_flag_i (hold_if_id        ),
        .inst_i      (inst_i            ),
        .inst_addr_i (pc_inst_addr      ),
        .inst_o      (if_id_inst        ),
        .inst_addr_o (if_id_inst_addr   )
    );
    

    wire w_reg_enable;
    wire [`reg_addr_bus] w_reg_addr;
    wire [`reg_data_bus] w_reg_data;
    wire [`reg_addr_bus] r_reg_addr1;
    wire [`reg_data_bus] r_reg_data1;
    wire [`reg_addr_bus] r_reg_addr2;
    wire [`reg_data_bus] r_reg_data2;

    regs u_regs(
    	.clk             (clk               ),
        .rst_n           (rst_n             ),
        .w_enable_i      (w_reg_enable      ),
        .w_addr_i        (w_reg_addr        ),
        .w_data_i        (w_reg_data        ),
        .r_addr_1_i      (r_reg_addr1       ),
        .r_data_1_o      (r_reg_data1       ),
        .r_addr_2_i      (r_reg_addr2       ),
        .r_data_2_o      (r_reg_data2       )

    );

    wire [`reg_data_bus] id_reg_data1;
    wire [`reg_data_bus] id_reg_data2;
    wire [`data_bus] id_imm_data;
    wire [`inst_addr_bus] id_pc_inst_addr;
    wire [`alu_inst_bus] id_alu_inst;
    wire [`inst_bus] id_inst;
    wire [`reg_addr_bus] id_w_reg_addr;
    wire [`data_type_bus] id_datatype;

    id u_id(
    	.inst_i         (if_id_inst         ),
        .inst_addr_i    (if_id_inst_addr    ),
        .r_reg_data_1_i (r_reg_data1        ),
        .r_reg_data_2_i (r_reg_data2        ),
        .r_reg_addr_1_o (r_reg_addr1        ),
        .r_reg_addr_2_o (r_reg_addr2        ),

        .r_reg_data_1_o (id_reg_data1       ),
        .r_reg_data_2_o (id_reg_data2       ),
        .imm_data_o     (id_imm_data        ),

        .r_pc_data_o    (id_pc_inst_addr    ),
        .alu_inst_o     (id_alu_inst        ),
        .r_inst_o       (id_inst            ),
        .w_reg_addr_o   (id_w_reg_addr      ),

        .data_type_o    (id_datatype        )
    );

    wire [`reg_addr_bus] id_ex_reg_addr1;
    wire [`reg_addr_bus] id_ex_reg_addr2;
    wire [`reg_data_bus] id_ex_r_reg_data1;
    wire [`reg_data_bus] id_ex_r_reg_data2;
    wire [`data_bus] id_ex_imm_data;
    wire [`inst_addr_bus] id_ex_pc_data;
    wire [`alu_inst_bus] id_ex_alu_inst;
    wire [`inst_bus] id_ex_inst;
    wire [`reg_addr_bus] id_ex_w_reg_addr;
    wire [`data_type_bus] id_ex_datatype;


    id_ex u_id_ex(
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .hold_flag_i    (hold_id_ex         ),
        .r_reg_addr_1_i (r_reg_addr1        ),
        .r_reg_addr_2_i (r_reg_addr2        ),

        .r_reg_data_1_i (id_reg_data1       ),
        .r_reg_data_2_i (id_reg_data2       ),
        .imm_data_i     (id_imm_data        ),

        .r_pc_data_i    (id_pc_inst_addr    ),
        .alu_inst_i     (id_alu_inst        ),
        .r_inst_i       (id_inst            ),
        .w_reg_addr_i   (id_w_reg_addr      ),

        .data_type_i    (id_datatype        ),

        .r_reg_addr_1_o (id_ex_reg_addr1    ),
        .r_reg_addr_2_o (id_ex_reg_addr2    ),

        .r_reg_data_1_o (id_ex_r_reg_data1  ),
        .r_reg_data_2_o (id_ex_r_reg_data2  ),
        .imm_data_o     (id_ex_imm_data     ),

        .r_pc_data_o    (id_ex_pc_data      ),
        .alu_inst_o     (id_ex_alu_inst     ),
        .r_inst_o       (id_ex_inst         ),
        .w_reg_addr_o   (id_ex_w_reg_addr   ),

        .data_type_o    (id_ex_datatype     )
    );
    

    wire [`reg_data_bus] trans_reg_data_1;
    wire [`reg_data_bus] trans_reg_data_2;

    trans u_trans(

    	.w_reg_req_i    (w_reg_enable       ),
        .w_reg_addr_i   (w_reg_addr         ),
        .w_reg_data_i   (w_reg_data         ),


        .r_reg_addr_1_i (id_ex_reg_addr1    ),
        .r_reg_addr_2_i (id_ex_reg_addr2    ),
        .r_reg_data_1_i (id_ex_r_reg_data1  ),
        .r_reg_data_2_i (id_ex_r_reg_data2  ),



        .r_reg_data_1_o (trans_reg_data_1   ),
        .r_reg_data_2_o (trans_reg_data_2   )

    );

    wire ex_jump_flag;
    wire [`inst_addr_bus] ex_jump_addr;
    wire ex_w_reg_enable;
    wire mem_w_reg_enable;
    wire [`reg_addr_bus] ex_w_reg_addr;
    wire [`data_bus] ex_w_reg_data;
    wire [`mem_addr_bus] ex_w_mem_addr;
    wire [`data_bus] ex_w_mem_data;
    wire ex_w_mem_enable;
    wire [`mem_addr_bus] ex_r_mem_addr;
    wire ex_r_mem_enable;
    wire [`data_type_bus] ex_datatype;

    ex u_ex(
    	.r_reg_data_1_i     (trans_reg_data_1   ),
        .r_reg_data_2_i     (trans_reg_data_2   ),
        .r_imm_data_i       (id_ex_imm_data     ),

        .r_pc_data_i        (id_ex_pc_data      ),
        .alu_inst_i         (id_ex_alu_inst     ),
        .r_inst_i           (id_ex_inst         ),
        .w_reg_addr_i       (id_ex_w_reg_addr   ),

        .data_type_i        (id_ex_datatype     ),

        .jump_enable_o      (ex_jump_flag       ),
        .jump_addr_o        (ex_jump_addr       ),

        .ex_w_reg_enable_o  (ex_w_reg_enable    ),
        .mem_w_reg_enable_o (mem_w_reg_enable   ),
        .w_reg_addr_o       (ex_w_reg_addr      ),
        .ex_w_reg_data_o    (ex_w_reg_data      ),
        .w_mem_addr_o       (ex_w_mem_addr      ),
        .w_mem_enable_o     (ex_w_mem_enable    ),
        .w_mem_data_o       (ex_w_mem_data      ),
        .r_mem_addr_o       (ex_r_mem_addr      ),
        .r_mem_enable_o     (ex_r_mem_enable    ),
        .data_type_o        (ex_datatype        )

    );

    ctrl u_ctrl(

        .ex_jump_flush_req_i       (ex_jump_flag            ),



        .ex_jump_flush_addr_i      (ex_jump_addr            ),
        .hold_ctrl_o               (hold_bus                ),
        .jump_flag_o               (jump_flag               ),
        .jump_addr_o               (jump_addr               )
    );

    wire ex_mw_exw_reg_enable;
    wire ex_mw_memw_reg_enable;
    wire [`reg_addr_bus] ex_mw_w_reg_addr;
    wire [`data_bus] ex_mw_w_reg_data;
    wire [`mem_addr_bus] ex_mw_w_mem_addr;
    wire ex_mw_w_mem_enable;
    wire [`data_bus] ex_mw_w_mem_data;
    wire [`mem_addr_bus] ex_mw_r_mem_addr;
    wire ex_mw_r_mem_enable;
    wire [`data_type_bus] ex_mw_datatype;

    ex_memwb u_ex_memwb(
    	.clk                (clk                ),
        .rst_n              (rst_n              ),
        .hold_flag_i        (hold_ex_memwb      ),

        .ex_w_reg_enable_i  (ex_w_reg_enable    ),
        .mem_w_reg_enable_i (mem_w_reg_enable   ),
        .w_reg_addr_i       (ex_w_reg_addr      ),
        .ex_w_reg_data_i    (ex_w_reg_data      ),
        .w_mem_addr_i       (ex_w_mem_addr      ),
        .w_mem_enable_i     (ex_w_mem_enable    ),
        .w_mem_data_i       (ex_w_mem_data      ),
        .r_mem_addr_i       (ex_r_mem_addr      ),
        .r_mem_enable_i     (ex_r_mem_enable    ),
        .data_type_i        (ex_datatype        ),

        .ex_w_reg_enable_o  (ex_mw_exw_reg_enable   ),
        .mem_w_reg_enable_o (ex_mw_memw_reg_enable  ),
        .w_reg_addr_o       (ex_mw_w_reg_addr       ),
        .ex_w_reg_data_o    (ex_mw_w_reg_data       ),
        .w_mem_addr_o       (ex_mw_w_mem_addr       ),
        .w_mem_enable_o     (ex_mw_w_mem_enable     ),
        .w_mem_data_o       (ex_mw_w_mem_data       ),
        .r_mem_addr_o       (ex_mw_r_mem_addr       ),
        .r_mem_enable_o     (ex_mw_r_mem_enable     ),
        .data_type_o        (ex_mw_datatype         )
    );

    
    mem_wb u_mem_wb(
    	.ex_w_reg_enable_i  (ex_mw_exw_reg_enable   ),
        .mem_w_reg_enable_i (ex_mw_memw_reg_enable  ),
        .w_reg_addr_i       (ex_mw_w_reg_addr       ),
        .ex_w_reg_data_i    (ex_mw_w_reg_data       ),
        .w_mem_addr_i       (ex_mw_w_mem_addr       ),
        .w_mem_enable_i     (ex_mw_w_mem_enable     ),
        .w_mem_data_i       (ex_mw_w_mem_data       ),
        .r_mem_addr_i       (ex_mw_r_mem_addr       ),
        .r_mem_enable_i     (ex_mw_r_mem_enable     ),
        .data_type_i        (ex_mw_datatype         ),

        .r_mem_data_i       (mem_data_i             ),
        .w_mem_addr_o       (mem_w_addr_o           ),
        .w_mem_data_o       (mem_data_o             ),
        .r_mem_addr_o       (mem_r_addr_o           ),
        .w_mem_enable_o     (mem_w_enable_o         ),
        .r_mem_enable_o     (mem_r_enable_o         ),
        .mem_enable_o       (mem_enable_o           ),
        .w_reg_addr_o       (w_reg_addr             ),
        .w_reg_data_o       (w_reg_data             ),
        .w_reg_enable_o     (w_reg_enable           )
    );
    
endmodule
module ayatsuki_core (
    input wire                      clk,
    input wire                      rst_n,
    
    input wire [`inst_bus]          inst_i,
    output wire [`inst_addr_bus]    inst_addr_o,

    output wire                     mem_w_enable_o,
    output wire                     mem_r_enable_o,
    output wire                     mem_enable_o,
    output wire [`mem_addr_bus]     mem_w_addr_o,
    output wire [`mem_addr_bus]     mem_r_addr_o,
    input wire [`mem_data_bus]      mem_data_i,
    output wire [`mem_data_bus]     mem_data_o
);


    wire [`hold_ctrl_bus] hold_bus;
    wire [`holdpip_bus] hold_pc = hold_bus[1:0];
    wire [`holdpip_bus] hold_if_id = hold_bus[3:2];
    wire [`holdpip_bus] hold_id_ex = hold_bus[5:4];
    wire [`holdpip_bus] hold_ex_memwb = hold_bus[7:6];

    wire jump_flag;
    wire [`inst_addr_bus] jump_addr;
    wire [`inst_addr_bus] pc_inst_addr;

    assign inst_addr_o = pc_inst_addr;

    pc u_pc(
    	.clk          (clk          ),
        .rst_n        (rst_n        ),
        .jump_flag_i  (jump_flag    ),
        .jump_addr_i  (jump_addr    ),
        .hold_flag_i  (hold_pc      ),
        .pc_o         (pc_inst_addr )

    );

    wire [`inst_addr_bus] if_id_inst_addr;
    wire [`inst_bus] if_id_inst;

    if_id u_if_id(
    	.clk         (clk               ),
        .rst_n       (rst_n             ),
        .hold_flag_i (hold_if_id        ),
        .inst_i      (inst_i            ),
        .inst_addr_i (pc_inst_addr      ),
        .inst_o      (if_id_inst        ),
        .inst_addr_o (if_id_inst_addr   )
    );
    

    wire w_reg_enable;
    wire [`reg_addr_bus] w_reg_addr;
    wire [`reg_data_bus] w_reg_data;
    wire [`reg_addr_bus] r_reg_addr1;
    wire [`reg_data_bus] r_reg_data1;
    wire [`reg_addr_bus] r_reg_addr2;
    wire [`reg_data_bus] r_reg_data2;

    regs u_regs(
    	.clk             (clk               ),
        .rst_n           (rst_n             ),
        .w_enable_i      (w_reg_enable      ),
        .w_addr_i        (w_reg_addr        ),
        .w_data_i        (w_reg_data        ),
        .r_addr_1_i      (r_reg_addr1       ),
        .r_data_1_o      (r_reg_data1       ),
        .r_addr_2_i      (r_reg_addr2       ),
        .r_data_2_o      (r_reg_data2       )

    );

    wire [`reg_data_bus] id_reg_data1;
    wire [`reg_data_bus] id_reg_data2;
    wire [`data_bus] id_imm_data;
    wire [`inst_addr_bus] id_pc_inst_addr;
    wire [`alu_inst_bus] id_alu_inst;
    wire [`inst_bus] id_inst;
    wire [`reg_addr_bus] id_w_reg_addr;
    wire [`data_type_bus] id_datatype;

    id u_id(
    	.inst_i         (if_id_inst         ),
        .inst_addr_i    (if_id_inst_addr    ),
        .r_reg_data_1_i (r_reg_data1        ),
        .r_reg_data_2_i (r_reg_data2        ),
        .r_reg_addr_1_o (r_reg_addr1        ),
        .r_reg_addr_2_o (r_reg_addr2        ),

        .r_reg_data_1_o (id_reg_data1       ),
        .r_reg_data_2_o (id_reg_data2       ),
        .imm_data_o     (id_imm_data        ),

        .r_pc_data_o    (id_pc_inst_addr    ),
        .alu_inst_o     (id_alu_inst        ),
        .r_inst_o       (id_inst            ),
        .w_reg_addr_o   (id_w_reg_addr      ),

        .data_type_o    (id_datatype        )
    );

    wire [`reg_addr_bus] id_ex_reg_addr1;
    wire [`reg_addr_bus] id_ex_reg_addr2;
    wire [`reg_data_bus] id_ex_r_reg_data1;
    wire [`reg_data_bus] id_ex_r_reg_data2;
    wire [`data_bus] id_ex_imm_data;
    wire [`inst_addr_bus] id_ex_pc_data;
    wire [`alu_inst_bus] id_ex_alu_inst;
    wire [`inst_bus] id_ex_inst;
    wire [`reg_addr_bus] id_ex_w_reg_addr;
    wire [`data_type_bus] id_ex_datatype;


    id_ex u_id_ex(
    	.clk            (clk                ),
        .rst_n          (rst_n              ),
        .hold_flag_i    (hold_id_ex         ),
        .r_reg_addr_1_i (r_reg_addr1        ),
        .r_reg_addr_2_i (r_reg_addr2        ),

        .r_reg_data_1_i (id_reg_data1       ),
        .r_reg_data_2_i (id_reg_data2       ),
        .imm_data_i     (id_imm_data        ),

        .r_pc_data_i    (id_pc_inst_addr    ),
        .alu_inst_i     (id_alu_inst        ),
        .r_inst_i       (id_inst            ),
        .w_reg_addr_i   (id_w_reg_addr      ),

        .data_type_i    (id_datatype        ),

        .r_reg_addr_1_o (id_ex_reg_addr1    ),
        .r_reg_addr_2_o (id_ex_reg_addr2    ),

        .r_reg_data_1_o (id_ex_r_reg_data1  ),
        .r_reg_data_2_o (id_ex_r_reg_data2  ),
        .imm_data_o     (id_ex_imm_data     ),

        .r_pc_data_o    (id_ex_pc_data      ),
        .alu_inst_o     (id_ex_alu_inst     ),
        .r_inst_o       (id_ex_inst         ),
        .w_reg_addr_o   (id_ex_w_reg_addr   ),

        .data_type_o    (id_ex_datatype     )
    );
    

    wire [`reg_data_bus] trans_reg_data_1;
    wire [`reg_data_bus] trans_reg_data_2;

    trans u_trans(

    	.w_reg_req_i    (w_reg_enable       ),
        .w_reg_addr_i   (w_reg_addr         ),
        .w_reg_data_i   (w_reg_data         ),


        .r_reg_addr_1_i (id_ex_reg_addr1    ),
        .r_reg_addr_2_i (id_ex_reg_addr2    ),
        .r_reg_data_1_i (id_ex_r_reg_data1  ),
        .r_reg_data_2_i (id_ex_r_reg_data2  ),



        .r_reg_data_1_o (trans_reg_data_1   ),
        .r_reg_data_2_o (trans_reg_data_2   )

    );

    wire ex_jump_flag;
    wire [`inst_addr_bus] ex_jump_addr;
    wire ex_w_reg_enable;
    wire mem_w_reg_enable;
    wire [`reg_addr_bus] ex_w_reg_addr;
    wire [`data_bus] ex_w_reg_data;
    wire [`mem_addr_bus] ex_w_mem_addr;
    wire [`data_bus] ex_w_mem_data;
    wire ex_w_mem_enable;
    wire [`mem_addr_bus] ex_r_mem_addr;
    wire ex_r_mem_enable;
    wire [`data_type_bus] ex_datatype;

    ex u_ex(
    	.r_reg_data_1_i     (trans_reg_data_1   ),
        .r_reg_data_2_i     (trans_reg_data_2   ),
        .r_imm_data_i       (id_ex_imm_data     ),

        .r_pc_data_i        (id_ex_pc_data      ),
        .alu_inst_i         (id_ex_alu_inst     ),
        .r_inst_i           (id_ex_inst         ),
        .w_reg_addr_i       (id_ex_w_reg_addr   ),

        .data_type_i        (id_ex_datatype     ),

        .jump_enable_o      (ex_jump_flag       ),
        .jump_addr_o        (ex_jump_addr       ),

        .ex_w_reg_enable_o  (ex_w_reg_enable    ),
        .mem_w_reg_enable_o (mem_w_reg_enable   ),
        .w_reg_addr_o       (ex_w_reg_addr      ),
        .ex_w_reg_data_o    (ex_w_reg_data      ),
        .w_mem_addr_o       (ex_w_mem_addr      ),
        .w_mem_enable_o     (ex_w_mem_enable    ),
        .w_mem_data_o       (ex_w_mem_data      ),
        .r_mem_addr_o       (ex_r_mem_addr      ),
        .r_mem_enable_o     (ex_r_mem_enable    ),
        .data_type_o        (ex_datatype        )

    );

    ctrl u_ctrl(

        .ex_jump_flush_req_i       (ex_jump_flag            ),



        .ex_jump_flush_addr_i      (ex_jump_addr            ),
        .hold_ctrl_o               (hold_bus                ),
        .jump_flag_o               (jump_flag               ),
        .jump_addr_o               (jump_addr               )
    );

    wire ex_mw_exw_reg_enable;
    wire ex_mw_memw_reg_enable;
    wire [`reg_addr_bus] ex_mw_w_reg_addr;
    wire [`data_bus] ex_mw_w_reg_data;
    wire [`mem_addr_bus] ex_mw_w_mem_addr;
    wire ex_mw_w_mem_enable;
    wire [`data_bus] ex_mw_w_mem_data;
    wire [`mem_addr_bus] ex_mw_r_mem_addr;
    wire ex_mw_r_mem_enable;
    wire [`data_type_bus] ex_mw_datatype;

    ex_memwb u_ex_memwb(
    	.clk                (clk                ),
        .rst_n              (rst_n              ),
        .hold_flag_i        (hold_ex_memwb      ),

        .ex_w_reg_enable_i  (ex_w_reg_enable    ),
        .mem_w_reg_enable_i (mem_w_reg_enable   ),
        .w_reg_addr_i       (ex_w_reg_addr      ),
        .ex_w_reg_data_i    (ex_w_reg_data      ),
        .w_mem_addr_i       (ex_w_mem_addr      ),
        .w_mem_enable_i     (ex_w_mem_enable    ),
        .w_mem_data_i       (ex_w_mem_data      ),
        .r_mem_addr_i       (ex_r_mem_addr      ),
        .r_mem_enable_i     (ex_r_mem_enable    ),
        .data_type_i        (ex_datatype        ),

        .ex_w_reg_enable_o  (ex_mw_exw_reg_enable   ),
        .mem_w_reg_enable_o (ex_mw_memw_reg_enable  ),
        .w_reg_addr_o       (ex_mw_w_reg_addr       ),
        .ex_w_reg_data_o    (ex_mw_w_reg_data       ),
        .w_mem_addr_o       (ex_mw_w_mem_addr       ),
        .w_mem_enable_o     (ex_mw_w_mem_enable     ),
        .w_mem_data_o       (ex_mw_w_mem_data       ),
        .r_mem_addr_o       (ex_mw_r_mem_addr       ),
        .r_mem_enable_o     (ex_mw_r_mem_enable     ),
        .data_type_o        (ex_mw_datatype         )
    );

    
    mem_wb u_mem_wb(
    	.ex_w_reg_enable_i  (ex_mw_exw_reg_enable   ),
        .mem_w_reg_enable_i (ex_mw_memw_reg_enable  ),
        .w_reg_addr_i       (ex_mw_w_reg_addr       ),
        .ex_w_reg_data_i    (ex_mw_w_reg_data       ),
        .w_mem_addr_i       (ex_mw_w_mem_addr       ),
        .w_mem_enable_i     (ex_mw_w_mem_enable     ),
        .w_mem_data_i       (ex_mw_w_mem_data       ),
        .r_mem_addr_i       (ex_mw_r_mem_addr       ),
        .r_mem_enable_i     (ex_mw_r_mem_enable     ),
        .data_type_i        (ex_mw_datatype         ),

        .r_mem_data_i       (mem_data_i             ),
        .w_mem_addr_o       (mem_w_addr_o           ),
        .w_mem_data_o       (mem_data_o             ),
        .r_mem_addr_o       (mem_r_addr_o           ),
        .w_mem_enable_o     (mem_w_enable_o         ),
        .r_mem_enable_o     (mem_r_enable_o         ),
        .mem_enable_o       (mem_enable_o           ),
        .w_reg_addr_o       (w_reg_addr             ),
        .w_reg_data_o       (w_reg_data             ),
        .w_reg_enable_o     (w_reg_enable           )
    );
    
endmodule