data/full_repos/permissive/441359809/src/yosys/tests/arch/common/add_sub.v
data/verilator_xmls/63786133-fe5e-47db-81f1-bb3794878aa2.xml
module top
(
    input [3:0] x,
    input [3:0] y,

    output [3:0] A,
    output [3:0] B
);

    assign A =  x + y;
    assign B =  x - y;
endmodule
module top
(
    input [3:0] x,
    input [3:0] y,

    output [3:0] A,
    output [3:0] B
);


    assign A =  x + y;
    assign B =  x - y;
endmodule