data/full_repos/permissive/500128826/HDLBits/Basics/Wire/top_module.v
data/verilator_xmls/6cee2f48-fb92-495e-98e6-9bea2a6ceb78.xml
module top_module (
    input  wire in,
    output wire out
);

  assign out = in;

endmodule
module top_module (
    input  wire in,
    output wire out
);


  assign out = in;

endmodule