data/full_repos/permissive/441359809/src/yosys/tests/sva/basic02.sv
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/basic02.sv:16: syntax error, unexpected |=>, expecting ')'\n a_wr: assert property ( @(posedge clock) write |=> ready );\n                                                ^~~\n%Error: Exiting due to 1 error(s)\n"
module top (input logic clock, ctrl);
	logic read = 0, write = 0, ready = 0;

	always @(posedge clock) begin
		read <= !ctrl;
		write <= ctrl;
		ready <= write;
	end
endmodule
module top (input logic clock, ctrl);

	logic read = 0, write = 0, ready = 0;

	always @(posedge clock) begin
		read <= !ctrl;
		write <= ctrl;
		ready <= write;
	end
endmodule