data/full_repos/permissive/486588912/verilog/mmio_seg7.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486588912/verilog/mmio_seg7.v:55: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 39 bits.\n                                                                           : ... In instance mmio_seg7\n                mmio_read_data <= {31\'b0, seg7_regs[_addr]};\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486588912/verilog/mmio_seg7.v:65: Cannot find file containing module: \'seg7\'\n    seg7 seg7_ins(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/seg7\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/seg7.v\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/seg7.sv\n             seg7\n             seg7.v\n             seg7.sv\n             obj_dir/seg7\n             obj_dir/seg7.v\n             obj_dir/seg7.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mmio_seg7(
    input sys_clk,
    input rst_n,
    
    input mmio_read,
    input mmio_write,
    input [31:0] mmio_addr,
    input [31:0] mmio_write_data,

    output mmio_work,
    output reg mmio_done,
    output reg [31:0] mmio_read_data,


    output [7:0] seg7_bits_pin, 
    output [7:0] seg7_led_pin,
    input bank_sys_clk
);



    wire [2:0] _addr = mmio_addr[4:2];
    assign mmio_work = mmio_addr[31:16] == 16'HFFFF && mmio_addr[15:5] == 11'b00000001_000 && (mmio_read || mmio_write);
    
    reg [7:0] seg7_regs [0:7];

    integer i;
    always @(posedge sys_clk) begin
        if (!rst_n) begin
            for (i=0;i<8;i=i+1) begin
                seg7_regs[i] <= 0;
            end
        end else begin
            for (i=0;i<8;i=i+1)
                seg7_regs[i] <= seg7_regs[i];
            if (mmio_work && mmio_write && !mmio_done)
                seg7_regs[_addr] <= mmio_write_data[7:0];
        end
    end
    



    always @(posedge sys_clk) begin
        if (!rst_n) begin
            mmio_done <= 0;
            mmio_read_data <= 0;
        end else begin
            if (mmio_done) begin
                mmio_done <= 0;
                mmio_read_data <= 0;
            end else if (mmio_work) begin
                mmio_done <= 1;
                mmio_read_data <= {31'b0, seg7_regs[_addr]};
            end else begin
                mmio_done <= mmio_done;
                mmio_read_data <= 0;
            end
        end
    end



    seg7 seg7_ins(
        .clk(sys_clk),
        .rst_n(rst_n),
        .numbers({seg7_regs[7],seg7_regs[6],seg7_regs[5],seg7_regs[4],seg7_regs[3],seg7_regs[2],seg7_regs[1],seg7_regs[0]}),
        .LED_BITS(seg7_bits_pin),
        .LED(seg7_led_pin)
    );

endmodule
module mmio_seg7(
    input sys_clk,
    input rst_n,
    
    input mmio_read,
    input mmio_write,
    input [31:0] mmio_addr,
    input [31:0] mmio_write_data,

    output mmio_work,
    output reg mmio_done,
    output reg [31:0] mmio_read_data,


    output [7:0] seg7_bits_pin, 
    output [7:0] seg7_led_pin,
    input bank_sys_clk
);




    wire [2:0] _addr = mmio_addr[4:2];
    assign mmio_work = mmio_addr[31:16] == 16'HFFFF && mmio_addr[15:5] == 11'b00000001_000 && (mmio_read || mmio_write);
    
    reg [7:0] seg7_regs [0:7];

    integer i;
    always @(posedge sys_clk) begin
        if (!rst_n) begin
            for (i=0;i<8;i=i+1) begin
                seg7_regs[i] <= 0;
            end
        end else begin
            for (i=0;i<8;i=i+1)
                seg7_regs[i] <= seg7_regs[i];
            if (mmio_work && mmio_write && !mmio_done)
                seg7_regs[_addr] <= mmio_write_data[7:0];
        end
    end
    



    always @(posedge sys_clk) begin
        if (!rst_n) begin
            mmio_done <= 0;
            mmio_read_data <= 0;
        end else begin
            if (mmio_done) begin
                mmio_done <= 0;
                mmio_read_data <= 0;
            end else if (mmio_work) begin
                mmio_done <= 1;
                mmio_read_data <= {31'b0, seg7_regs[_addr]};
            end else begin
                mmio_done <= mmio_done;
                mmio_read_data <= 0;
            end
        end
    end



    seg7 seg7_ins(
        .clk(sys_clk),
        .rst_n(rst_n),
        .numbers({seg7_regs[7],seg7_regs[6],seg7_regs[5],seg7_regs[4],seg7_regs[3],seg7_regs[2],seg7_regs[1],seg7_regs[0]}),
        .LED_BITS(seg7_bits_pin),
        .LED(seg7_led_pin)
    );

endmodule