data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v
1: b'%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:1: Cannot find include file: CNN_defines.vh\n`include "CNN_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464160784/atom_systolic,data/full_repos/permissive/464160784/CNN_defines.vh\n             data/full_repos/permissive/464160784/atom_systolic,data/full_repos/permissive/464160784/CNN_defines.vh.v\n             data/full_repos/permissive/464160784/atom_systolic,data/full_repos/permissive/464160784/CNN_defines.vh.sv\n             CNN_defines.vh\n             CNN_defines.vh.v\n             CNN_defines.vh.sv\n             obj_dir/CNN_defines.vh\n             obj_dir/CNN_defines.vh.v\n             obj_dir/CNN_defines.vh.sv\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:7: Define or directive not defined: \'`MAX_DW_Ratio\'\n    input [`MAX_DW_Ratio-1:0]Tin_factor, \n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:11: Define or directive not defined: \'`base_Tin\'\n    input [`base_Tin*`MAX_DAT_DW-1:0]dat,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:11: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    input [`base_Tin*`MAX_DAT_DW-1:0]dat,\n                    ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:11: Define or directive not defined: \'`MAX_DAT_DW\'\n    input [`base_Tin*`MAX_DAT_DW-1:0]dat,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:17: Define or directive not defined: \'`base_Tin\'\n    input [`base_Tin*`MAX_WT_DW-1:0]wt,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:17: Define or directive not defined: \'`MAX_WT_DW\'\n    input [`base_Tin*`MAX_WT_DW-1:0]wt,\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:18: Define or directive not defined: \'`log2Tout\'\n    input [`log2Tout-1:0]wt_sel,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:21: Define or directive not defined: \'`Tout\'\n    output [`Tout*(`MAX_DW2+`base_log2Tin)-1:0]dat_o\n            ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:21: Define or directive not defined: \'`MAX_DW2\'\n    output [`Tout*(`MAX_DW2+`base_log2Tin)-1:0]dat_o\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:21: Define or directive not defined: \'`base_log2Tin\'\n    output [`Tout*(`MAX_DW2+`base_log2Tin)-1:0]dat_o\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:25: Define or directive not defined: \'`base_Tin\'\nreg [`base_Tin*`MAX_DAT_DW-1:0]dat_reg;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:25: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`base_Tin*`MAX_DAT_DW-1:0]dat_reg;\n              ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:25: Define or directive not defined: \'`MAX_DAT_DW\'\nreg [`base_Tin*`MAX_DAT_DW-1:0]dat_reg;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:34: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n)\n^~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:41: Define or directive not defined: \'`MAX_DAT_DW\'\nwire [`MAX_DAT_DW-1:0] dat_to_mac[`base_Tin-1:0];\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:41: Define or directive not defined: \'`base_Tin\'\nwire [`MAX_DAT_DW-1:0] dat_to_mac[`base_Tin-1:0];\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:42: Define or directive not defined: \'`base_Tin\'\nreg [`base_Tin:0]dat_to_mac_vld;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:42: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`base_Tin:0]dat_to_mac_vld;\n              ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:43: Define or directive not defined: \'`Tout\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];\n      ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:43: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];\n           ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:43: Define or directive not defined: \'`base_log2Tin\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:43: Define or directive not defined: \'`MAX_DW2\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:43: Define or directive not defined: \'`base_Tin\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];\n                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:44: Define or directive not defined: \'`Tout\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;\n      ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:44: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;\n           ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:44: Define or directive not defined: \'`base_log2Tin\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:44: Define or directive not defined: \'`MAX_DW2\'\nwire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:49: Define or directive not defined: \'`base_Tin\'\n    for(i=0;i<`base_Tin;i=i+1)\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:53: Define or directive not defined: \'`MAX_DAT_DW\'\n            .DATA_WIDTH(`MAX_DAT_DW),\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:59: Define or directive not defined: \'`MAX_DAT_DW\'\n            .data_in(dat_reg[`MAX_DAT_DW*i+:`MAX_DAT_DW]),\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:59: Define or directive not defined: \'`MAX_DAT_DW\'\n            .data_in(dat_reg[`MAX_DAT_DW*i+:`MAX_DAT_DW]),\n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:70: Define or directive not defined: \'`base_Tin\'\n    for(i=0;i<`base_Tin;i=i+1)\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:86: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n)\n^~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:97: Define or directive not defined: \'`base_Tin\'\nwire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:97: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;\n               ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:97: Define or directive not defined: \'`Tout\'\nwire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;\n                ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:97: Define or directive not defined: \'`MAX_WT_DW\'\nwire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:98: Define or directive not defined: \'`Tout\'\nwire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];\n      ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:98: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];\n           ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:98: Define or directive not defined: \'`MAX_WT_DW\'\nwire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:98: Define or directive not defined: \'`base_Tin\'\nwire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:103: Define or directive not defined: \'`Tout\'\n    for(i=0;i<`Tout;i=i+1)\n              ^~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:105: Define or directive not defined: \'`base_Tin\'\n        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg1;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:105: Define or directive not defined: \'`MAX_WT_DW\'\n        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg1;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:106: Define or directive not defined: \'`base_Tin\'\n        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg2;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:106: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg2;\n                      ^\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:106: Define or directive not defined: \'`MAX_WT_DW\'\n        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg2;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:121: Define or directive not defined: \'`base_Tin\'\n        assign  tp_wt_reg3[`base_Tin*`MAX_WT_DW*i+:`base_Tin*`MAX_WT_DW]=wt_reg2;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/464160784/atom_systolic/Atom_Systolic_MAC_Control.v:121: Define or directive not defined: \'`MAX_WT_DW\'\n        assign  tp_wt_reg3[`base_Tin*`MAX_WT_DW*i+:`base_Tin*`MAX_WT_DW]=wt_reg2;\n                                     ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Atom_Systolic_MAC_Control
(
    input clk,
    input rst_n,
    input [`MAX_DW_Ratio-1:0]Tin_factor,
    

    input dat_vld,
    input [`base_Tin*`MAX_DAT_DW-1:0]dat,
    input Wout_loop_start,
    input Wout_loop_end,
    

    input wt_vld,
    input [`base_Tin*`MAX_WT_DW-1:0]wt,
    input [`log2Tout-1:0]wt_sel,
    

    output [`Tout*(`MAX_DW2+`base_log2Tin)-1:0]dat_o
);


reg [`base_Tin*`MAX_DAT_DW-1:0]dat_reg;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    dat_reg<='d0;
else
    if(dat_vld)
        dat_reg<=dat;

reg dat_vld_d;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    dat_vld_d<=1'b0;
else
    dat_vld_d<=dat_vld;

    
wire [`MAX_DAT_DW-1:0] dat_to_mac[`base_Tin-1:0];
reg [`base_Tin:0]dat_to_mac_vld;
wire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];
wire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;
    
generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        generate_shift_reg #
        (
            .DATA_WIDTH(`MAX_DAT_DW),
            .DEPTH(i+1)
        )dat_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(dat_reg[`MAX_DAT_DW*i+:`MAX_DAT_DW]),
            .data_out(dat_to_mac[i])
        );
    end
end
endgenerate


generate
begin
    genvar i;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        if(!rst_n)
            dat_to_mac_vld<='d0;
        else
            dat_to_mac_vld<={dat_to_mac_vld[i:0],dat_vld_d};
    end
end
endgenerate



wire wt_load_reg2;
wire wt_load_new=wt_vld&(wt_sel==0);
reg [1:0]wt_load_cnt;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    wt_load_cnt<=2'd0;
else
    case({wt_load_new,Wout_loop_start})
        2'b01:wt_load_cnt<=wt_load_cnt-2'd1;
        2'b10:wt_load_cnt<=wt_load_cnt+2'd1;
    endcase

assign wt_load_reg2=(wt_load_cnt==2'd1)&(wt_load_new|Wout_loop_start);

wire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;
wire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];

genvar i;
generate
begin
    for(i=0;i<`Tout;i=i+1)
    begin
        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg1;
        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg2;
        always @(posedge clk or negedge rst_n)
        if(~rst_n)
            wt_reg1<='d0;
        else
            if(wt_vld&(wt_sel==i))
                wt_reg1<=wt;

        always @(posedge clk or negedge rst_n)
        if(~rst_n)
            wt_reg2<='d0;
        else
            if(wt_load_reg2)
                wt_reg2<=wt_reg1;

        assign  tp_wt_reg3[`base_Tin*`MAX_WT_DW*i+:`base_Tin*`MAX_WT_DW]=wt_reg2;

    end
end
endgenerate

generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        for(j=0;j<`Tout;j=j+1)
        begin
            assign wt_reg3[i][j*`MAX_WT_DW+`MAX_WT_DW-1:j*`MAX_WT_DW]=tp_wt_reg3[j*(`base_Tin*`MAX_WT_DW)+i*`MAX_WT_DW+`MAX_WT_DW-1:j*(`base_Tin*`MAX_WT_DW)+i*`MAX_WT_DW];
        end
    end
end
endgenerate


wire [`Tout*`MAX_WT_DW-1:0]wt_to_mac[`base_Tin-1:0];
generate
begin
    genvar i;
    for(i=0;i<`base_Tin;i=i+1)
    begin
         generate_shift_reg #
        (
            .DATA_WIDTH(`Tout*`MAX_DAT_DW),
            .DEPTH(i+1)
        )wt_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(wt_reg3[i]),
            .data_out(wt_to_mac[i])
        );
    end
end
endgenerate

reg Wout_loop_start_d1;
reg Wout_loop_end_d1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
    Wout_loop_start_d1<='d0;
    Wout_loop_end_d1<='d0;
end
else
begin
    Wout_loop_start_d1<=Wout_loop_start;
    Wout_loop_end_d1<=Wout_loop_end;
end

reg [`base_Tin-1:0]Wout_loop_end_in_mac;
reg [`base_Tin-1:0]Wout_loop_start_in_mac;
generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        if(!rst_n) begin
            Wout_loop_end_in_mac<=0;
            Wout_loop_start_in_mac<=0;
        end
        else begin
            Wout_loop_end_in_mac<={Wout_loop_end_in_mac[i:0],Wout_loop_end_d1};
            Wout_loop_start_in_mac<={Wout_loop_start_in_mac[i:0],Wout_loop_start_d1};
        end
    end
end
endgenerate
 
Systolic_PE_Row Systolic_PE_Row0
(
    .clk(clk),
    .rst_n(rst_n),
    .wt(wt_to_mac[0]),
    .Tin_factor(Tin_factor),
    
    .wout_loop_start(Wout_loop_start_in_mac[0]),
    .wout_loop_end(Wout_loop_end_in_mac[0]),
    
    .input_vld(dat_to_mac_vld[0]),
    .left_dat_in(dat_to_mac[0]),
    .up_dat_in({(`Tout*(`base_log2Tin+`MAX_DW2)){1'b0}}),
    
    .down_dat_out(down_dat_out[0])
);

generate
begin
    genvar i;
    for(i=1;i<`base_Tin;i=i+1)
        begin
            Systolic_PE_Row Systolic_PE_Row
            (
                .clk(clk),
                .rst_n(rst_n),
                .wt(wt_to_mac[i]),
                .Tin_factor(Tin_factor),
                
                .wout_loop_start(Wout_loop_start_in_mac[i]),
                .wout_loop_end(Wout_loop_end_in_mac[i]),
                
                .input_vld(dat_to_mac_vld[i]),
                .left_dat_in(dat_to_mac[i]),
                .up_dat_in(down_dat_out[i-1]),
                
                .down_dat_out(down_dat_out[i])
            );
        end
    end
endgenerate

wire [(`MAX_DW2+`base_log2Tin)-1:0] dat_out_shift[`Tout-1:0];
generate
begin
    genvar i,j;
    for(i=0;i<`Tout;i=i+1)
    begin
        generate_shift_reg #
        (
            .DATA_WIDTH(`MAX_DW2+`base_log2Tin),
            .DEPTH(`Tout-i)
        )dat_out_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(down_dat_out[`base_Tin-1][i*(`base_log2Tin+`MAX_DW2)+:(`base_log2Tin+`MAX_DW2)]),
            .data_out(dat_out_shift[i])
        );
        assign dat_to_cacc[i*(`MAX_DW2+`base_log2Tin)+:(`MAX_DW2+`base_log2Tin)]=dat_out_shift[i];
    end
end
endgenerate

assign dat_o=dat_to_cacc;

endmodule
module Atom_Systolic_MAC_Control
(
    input clk,
    input rst_n,
    input [`MAX_DW_Ratio-1:0]Tin_factor,
    

    input dat_vld,
    input [`base_Tin*`MAX_DAT_DW-1:0]dat,
    input Wout_loop_start,
    input Wout_loop_end,
    

    input wt_vld,
    input [`base_Tin*`MAX_WT_DW-1:0]wt,
    input [`log2Tout-1:0]wt_sel,
    

    output [`Tout*(`MAX_DW2+`base_log2Tin)-1:0]dat_o
);



reg [`base_Tin*`MAX_DAT_DW-1:0]dat_reg;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    dat_reg<='d0;
else
    if(dat_vld)
        dat_reg<=dat;

reg dat_vld_d;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    dat_vld_d<=1'b0;
else
    dat_vld_d<=dat_vld;

    
wire [`MAX_DAT_DW-1:0] dat_to_mac[`base_Tin-1:0];
reg [`base_Tin:0]dat_to_mac_vld;
wire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]down_dat_out[`base_Tin-1:0];
wire [`Tout*(`base_log2Tin+`MAX_DW2)-1:0]dat_to_cacc;
    
generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        generate_shift_reg #
        (
            .DATA_WIDTH(`MAX_DAT_DW),
            .DEPTH(i+1)
        )dat_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(dat_reg[`MAX_DAT_DW*i+:`MAX_DAT_DW]),
            .data_out(dat_to_mac[i])
        );
    end
end
endgenerate


generate
begin
    genvar i;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        if(!rst_n)
            dat_to_mac_vld<='d0;
        else
            dat_to_mac_vld<={dat_to_mac_vld[i:0],dat_vld_d};
    end
end
endgenerate



wire wt_load_reg2;
wire wt_load_new=wt_vld&(wt_sel==0);
reg [1:0]wt_load_cnt;
always @(posedge clk or negedge rst_n)
if(~rst_n)
    wt_load_cnt<=2'd0;
else
    case({wt_load_new,Wout_loop_start})
        2'b01:wt_load_cnt<=wt_load_cnt-2'd1;
        2'b10:wt_load_cnt<=wt_load_cnt+2'd1;
    endcase

assign wt_load_reg2=(wt_load_cnt==2'd1)&(wt_load_new|Wout_loop_start);

wire [`base_Tin*`Tout*`MAX_WT_DW-1:0]tp_wt_reg3;
wire [`Tout*`MAX_WT_DW-1:0]wt_reg3[`base_Tin-1:0];

genvar i;
generate
begin
    for(i=0;i<`Tout;i=i+1)
    begin
        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg1;
        reg [`base_Tin*`MAX_WT_DW-1:0]wt_reg2;
        always @(posedge clk or negedge rst_n)
        if(~rst_n)
            wt_reg1<='d0;
        else
            if(wt_vld&(wt_sel==i))
                wt_reg1<=wt;

        always @(posedge clk or negedge rst_n)
        if(~rst_n)
            wt_reg2<='d0;
        else
            if(wt_load_reg2)
                wt_reg2<=wt_reg1;

        assign  tp_wt_reg3[`base_Tin*`MAX_WT_DW*i+:`base_Tin*`MAX_WT_DW]=wt_reg2;

    end
end
endgenerate

generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        for(j=0;j<`Tout;j=j+1)
        begin
            assign wt_reg3[i][j*`MAX_WT_DW+`MAX_WT_DW-1:j*`MAX_WT_DW]=tp_wt_reg3[j*(`base_Tin*`MAX_WT_DW)+i*`MAX_WT_DW+`MAX_WT_DW-1:j*(`base_Tin*`MAX_WT_DW)+i*`MAX_WT_DW];
        end
    end
end
endgenerate


wire [`Tout*`MAX_WT_DW-1:0]wt_to_mac[`base_Tin-1:0];
generate
begin
    genvar i;
    for(i=0;i<`base_Tin;i=i+1)
    begin
         generate_shift_reg #
        (
            .DATA_WIDTH(`Tout*`MAX_DAT_DW),
            .DEPTH(i+1)
        )wt_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(wt_reg3[i]),
            .data_out(wt_to_mac[i])
        );
    end
end
endgenerate

reg Wout_loop_start_d1;
reg Wout_loop_end_d1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
    Wout_loop_start_d1<='d0;
    Wout_loop_end_d1<='d0;
end
else
begin
    Wout_loop_start_d1<=Wout_loop_start;
    Wout_loop_end_d1<=Wout_loop_end;
end

reg [`base_Tin-1:0]Wout_loop_end_in_mac;
reg [`base_Tin-1:0]Wout_loop_start_in_mac;
generate
begin
    genvar i,j;
    for(i=0;i<`base_Tin;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        if(!rst_n) begin
            Wout_loop_end_in_mac<=0;
            Wout_loop_start_in_mac<=0;
        end
        else begin
            Wout_loop_end_in_mac<={Wout_loop_end_in_mac[i:0],Wout_loop_end_d1};
            Wout_loop_start_in_mac<={Wout_loop_start_in_mac[i:0],Wout_loop_start_d1};
        end
    end
end
endgenerate
 
Systolic_PE_Row Systolic_PE_Row0
(
    .clk(clk),
    .rst_n(rst_n),
    .wt(wt_to_mac[0]),
    .Tin_factor(Tin_factor),
    
    .wout_loop_start(Wout_loop_start_in_mac[0]),
    .wout_loop_end(Wout_loop_end_in_mac[0]),
    
    .input_vld(dat_to_mac_vld[0]),
    .left_dat_in(dat_to_mac[0]),
    .up_dat_in({(`Tout*(`base_log2Tin+`MAX_DW2)){1'b0}}),
    
    .down_dat_out(down_dat_out[0])
);

generate
begin
    genvar i;
    for(i=1;i<`base_Tin;i=i+1)
        begin
            Systolic_PE_Row Systolic_PE_Row
            (
                .clk(clk),
                .rst_n(rst_n),
                .wt(wt_to_mac[i]),
                .Tin_factor(Tin_factor),
                
                .wout_loop_start(Wout_loop_start_in_mac[i]),
                .wout_loop_end(Wout_loop_end_in_mac[i]),
                
                .input_vld(dat_to_mac_vld[i]),
                .left_dat_in(dat_to_mac[i]),
                .up_dat_in(down_dat_out[i-1]),
                
                .down_dat_out(down_dat_out[i])
            );
        end
    end
endgenerate

wire [(`MAX_DW2+`base_log2Tin)-1:0] dat_out_shift[`Tout-1:0];
generate
begin
    genvar i,j;
    for(i=0;i<`Tout;i=i+1)
    begin
        generate_shift_reg #
        (
            .DATA_WIDTH(`MAX_DW2+`base_log2Tin),
            .DEPTH(`Tout-i)
        )dat_out_shift_reg
        (
            .clk(clk),
            .rst_n(rst_n),
            .data_in(down_dat_out[`base_Tin-1][i*(`base_log2Tin+`MAX_DW2)+:(`base_log2Tin+`MAX_DW2)]),
            .data_out(dat_out_shift[i])
        );
        assign dat_to_cacc[i*(`MAX_DW2+`base_log2Tin)+:(`MAX_DW2+`base_log2Tin)]=dat_out_shift[i];
    end
end
endgenerate

assign dat_o=dat_to_cacc;

endmodule