data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:104: Signal definition not found, creating implicitly: \'start1\'\n                                                                                                                                             : ... Suggested alternative: \'start\'\n            state <= start1? RUNNING:IDLE;\n                     ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:71: Cannot find file containing module: \'fflopx\'\nfflopx #(256) iff1(clk,rst,a,a1);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:72: Cannot find file containing module: \'fflopx\'\nfflopx #(256) iff2(clk,rst,b,b1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:73: Cannot find file containing module: \'fflopx\'\nfflopx #(256) iff3(clk,rst,m,m1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:74: Cannot find file containing module: \'fflopx\'\nfflopx #(1) iff4(clk,rst,start,start1);\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:91: Operator NEGATE expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                         : ... In instance montprowrap\nassign           cntdone = moncnt == -1\'d1;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:121: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ZERO\' generates 256 bits.\n                                                                                                                                          : ... In instance montprowrap\n        moncnt <= ZERO;\n               ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:139: Cannot find file containing module: \'montpro\'\nmontpro #(WID,ZERO) imontpro\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montprowrap.v:160: Operator ASSIGNW expects 256 bits on the Assign RHS, but Assign RHS\'s COND generates 257 bits.\n                                                                                                                                          : ... In instance montprowrap\nassign         lstrs = (corers >= {1\'b0,m})? (corers - {1\'b0,m}) : corers; \n                     ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module montprowrap
    (
     clk,
     rst,
     
     a,
     b,
     m,
     r,
     
     start,
     vld
     );



`ifdef TEST
parameter WID = 4;
parameter CNTWID = 2;
parameter ZERO = 4'b0;
parameter IDLE = 1'b0;
parameter RUNNING = 1'b1;
`else
parameter WID = 256;
parameter CNTWID = 8;
parameter ZERO = 256'b0;
parameter IDLE = 1'b0;
parameter RUNNING = 1'b1;
`endif



input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;

output [WID-1:0] r;

input            start;
output           vld;







wire         shiften;


wire [WID-1:0]   a1;
wire [WID-1:0]   b1;
wire [WID-1:0]   m1;
wire             start;

fflopx #(256) iff1(clk,rst,a,a1);
fflopx #(256) iff2(clk,rst,b,b1);
fflopx #(256) iff3(clk,rst,m,m1);
fflopx #(1) iff4(clk,rst,start,start1);

reg              state;
reg [CNTWID-1:0] moncnt;
reg              doneflag;

wire             cntdone;
wire             isidle;
wire             cntflg;
wire             done;

assign           vld = doneflag;
assign           isidle = state == IDLE;
assign           done = isidle;
assign           cntflg = !isidle;


assign           cntdone = moncnt == -1'd1;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        doneflag <= 1'b0;
        end
    else
        begin
        if(isidle)
            begin
            state <= start1? RUNNING:IDLE;
            doneflag <= 1'b0;
            end
        else
            begin
            state <= ~(cntdone & shiften);
            doneflag <= cntdone & shiften;
            end
        end
    end



always@(posedge clk)
    begin
    if(rst)
        begin
        moncnt <= ZERO;
        end
    else if(cntflg && shiften) 
        begin
        moncnt <= moncnt + 1'b1;
        end
    else if (done && shiften)
        begin
        moncnt <= 0;
        end
    end





wire [WID:0] corers;

montpro #(WID,ZERO) imontpro
    (
     .clk(clk),
     .rst(rst),
     
     .a(a1),
     .b(b1),
     .m(m1),
     

     .ldnew(done),

     
     .r(corers),
     .shiften(shiften)
     );



wire [WID-1:0] lstrs;

assign         lstrs = (corers >= {1'b0,m})? (corers - {1'b0,m}) : corers; 



assign         r = lstrs;

endmodule
module montprowrap
    (
     clk,
     rst,
     
     a,
     b,
     m,
     r,
     
     start,
     vld
     );




`ifdef TEST
parameter WID = 4;
parameter CNTWID = 2;
parameter ZERO = 4'b0;
parameter IDLE = 1'b0;
parameter RUNNING = 1'b1;
`else
parameter WID = 256;
parameter CNTWID = 8;
parameter ZERO = 256'b0;
parameter IDLE = 1'b0;
parameter RUNNING = 1'b1;
`endif



input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;

output [WID-1:0] r;

input            start;
output           vld;







wire         shiften;


wire [WID-1:0]   a1;
wire [WID-1:0]   b1;
wire [WID-1:0]   m1;
wire             start;

fflopx #(256) iff1(clk,rst,a,a1);
fflopx #(256) iff2(clk,rst,b,b1);
fflopx #(256) iff3(clk,rst,m,m1);
fflopx #(1) iff4(clk,rst,start,start1);

reg              state;
reg [CNTWID-1:0] moncnt;
reg              doneflag;

wire             cntdone;
wire             isidle;
wire             cntflg;
wire             done;

assign           vld = doneflag;
assign           isidle = state == IDLE;
assign           done = isidle;
assign           cntflg = !isidle;


assign           cntdone = moncnt == -1'd1;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        doneflag <= 1'b0;
        end
    else
        begin
        if(isidle)
            begin
            state <= start1? RUNNING:IDLE;
            doneflag <= 1'b0;
            end
        else
            begin
            state <= ~(cntdone & shiften);
            doneflag <= cntdone & shiften;
            end
        end
    end



always@(posedge clk)
    begin
    if(rst)
        begin
        moncnt <= ZERO;
        end
    else if(cntflg && shiften) 
        begin
        moncnt <= moncnt + 1'b1;
        end
    else if (done && shiften)
        begin
        moncnt <= 0;
        end
    end





wire [WID:0] corers;

montpro #(WID,ZERO) imontpro
    (
     .clk(clk),
     .rst(rst),
     
     .a(a1),
     .b(b1),
     .m(m1),
     

     .ldnew(done),

     
     .r(corers),
     .shiften(shiften)
     );



wire [WID-1:0] lstrs;

assign         lstrs = (corers >= {1'b0,m})? (corers - {1'b0,m}) : corers; 



assign         r = lstrs;

endmodule