data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Add2Mul2u29Add2u8u8Mul2u32Add2u8u8_1.v
data/verilator_xmls/25bdb6c1-a783-429d-90f6-598f49e512ca.xml
module dut_Add2Mul2u29Add2u8u8Mul2u32Add2u8u8_1 (
	in6,
	in5,
	in4,
	in3,
	in2,
	in1,
	out1
	);
input [7:0] in6,
	in5;
input [31:0] in4;
input [7:0] in3,
	in2;
input [28:0] in1;
output [31:0] out1;
wire [31:0] asc001;
wire [8:0] asc002,
	asc003;

assign asc002 = 
	+(in6)
	+(in5);

assign asc003 = 
	+(in3)
	+(in2);

wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in4 * asc002);
assign asc001 = asc001_tmp_0
	+(in1 * asc003);

assign out1 = asc001;
endmodule
module dut_Add2Mul2u29Add2u8u8Mul2u32Add2u8u8_1 (
	in6,
	in5,
	in4,
	in3,
	in2,
	in1,
	out1
	);

input [7:0] in6,
	in5;
input [31:0] in4;
input [7:0] in3,
	in2;
input [28:0] in1;
output [31:0] out1;
wire [31:0] asc001;
wire [8:0] asc002,
	asc003;

assign asc002 = 
	+(in6)
	+(in5);

assign asc003 = 
	+(in3)
	+(in2);

wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = 
	+(in4 * asc002);
assign asc001 = asc001_tmp_0
	+(in1 * asc003);

assign out1 = asc001;
endmodule