data/full_repos/permissive/493514142/verilog/rtl/FPU/FPU_fpr_ctl.v
1: b'%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FPU_fpr_ctl.v:54: Cannot find file containing module: \'rvdffe\'\n      rvdffe #(32) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));\n      ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/rvdffe\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/rvdffe.v\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/rvdffe.sv\n             rvdffe\n             rvdffe.v\n             rvdffe.sv\n             obj_dir/rvdffe\n             obj_dir/rvdffe.v\n             obj_dir/rvdffe.sv\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/FPU_fpr_ctl.v:74: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                                     : ... In instance FPU_fpr_ctl\n             w0v[q]     = wen0  & (waddr0[4:0] == q );\n                                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module FPU_fpr_ctl
#(
  parameter FPLEN = 32
 )  (
 
    input rden0,
    input rden1,
    input rden2,
    
    input  [4:0]  raddr0,
    input  [4:0]  raddr1,
    input  [4:0]  raddr2,

    input         wen0,
    input  [4:0]  waddr0,
    input  [FPLEN-1:0] wd0,

    input         clk,
    input         rst_l,

    output  [FPLEN-1:0] rd0,
    output  [FPLEN-1:0] rd1,
    output  [FPLEN-1:0] rd2,

    input          scan_mode
);

   wire [FPLEN-1:0] fpr_out [31:0];
   reg  [FPLEN-1:0] fpr_in  [31:0];
   reg  [31:0] w0v;
   wire [31:0] fpr_wr_en;


   assign fpr_wr_en[31:0] = (rst_l == 1'b0) ? {32{1'b1}} : (w0v[31:0]);

genvar j;   
generate   
   for (j=0; j<32; j=j+1)
      rvdffe #(32) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));
endgenerate



      assign rd0 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden0 == 1'b1)) ? fpr_out[raddr0][FPLEN-1:0] : {FPLEN{1'b0}};
      assign rd1 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden1 == 1'b1)) ? fpr_out[raddr1][FPLEN-1:0] : {FPLEN{1'b0}};
      assign rd2 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden2 == 1'b1)) ? fpr_out[raddr2][FPLEN-1:0] : {FPLEN{1'b0}};  
   

integer q;
   always @(*) begin
       if(rst_l == 1'b0) begin
          w0v = 32'h00000000;
          for(q=0; q<32; q=q+1) begin
             fpr_in[q] = {FPLEN{1'b0}};
          end
       end
      else begin 
          for (q=0; q<32; q=q+1)  begin
             w0v[q]     = wen0  & (waddr0[4:0] == q );
             fpr_in[q]  =    ({FPLEN{w0v[q]}} & wd0[FPLEN-1:0]);
    	  end
      end
   end 

endmodule
module FPU_fpr_ctl
#(
  parameter FPLEN = 32
 )  (
 
    input rden0,
    input rden1,
    input rden2,
    
    input  [4:0]  raddr0,
    input  [4:0]  raddr1,
    input  [4:0]  raddr2,

    input         wen0,
    input  [4:0]  waddr0,
    input  [FPLEN-1:0] wd0,

    input         clk,
    input         rst_l,

    output  [FPLEN-1:0] rd0,
    output  [FPLEN-1:0] rd1,
    output  [FPLEN-1:0] rd2,

    input          scan_mode
);


   wire [FPLEN-1:0] fpr_out [31:0];
   reg  [FPLEN-1:0] fpr_in  [31:0];
   reg  [31:0] w0v;
   wire [31:0] fpr_wr_en;


   assign fpr_wr_en[31:0] = (rst_l == 1'b0) ? {32{1'b1}} : (w0v[31:0]);

genvar j;   
generate   
   for (j=0; j<32; j=j+1)
      rvdffe #(32) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));
endgenerate



      assign rd0 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden0 == 1'b1)) ? fpr_out[raddr0][FPLEN-1:0] : {FPLEN{1'b0}};
      assign rd1 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden1 == 1'b1)) ? fpr_out[raddr1][FPLEN-1:0] : {FPLEN{1'b0}};
      assign rd2 = (rst_l  == 1'b0) ? {FPLEN{1'b0}} : ((rden2 == 1'b1)) ? fpr_out[raddr2][FPLEN-1:0] : {FPLEN{1'b0}};  
   

integer q;
   always @(*) begin
       if(rst_l == 1'b0) begin
          w0v = 32'h00000000;
          for(q=0; q<32; q=q+1) begin
             fpr_in[q] = {FPLEN{1'b0}};
          end
       end
      else begin 
          for (q=0; q<32; q=q+1)  begin
             w0v[q]     = wen0  & (waddr0[4:0] == q );
             fpr_in[q]  =    ({FPLEN{w0v[q]}} & wd0[FPLEN-1:0]);
    	  end
      end
   end 

endmodule