data/full_repos/permissive/525452387/testbench/pcreg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1 pcreg_1_rst_ <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #1 pcreg_1_rst_ <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1 pcreg_1_rst_ <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #5 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #1 pcreg_1_jump_flag_i <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #3 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n    always #1 begin\n           ^\n%Error: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:101: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("pcreg.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/pcreg_tb.v:102: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, pcreg_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pcreg_test_bench;
    reg pcreg_1_clk;
    reg pcreg_1_rst_;
    reg pcreg_1_jump_flag_i;
    reg[31:0] pcreg_1_jump_addr_i;

    wire[31:0] pcreg_1_pc_o;

    pcreg pcreg_1 (
        .clk  (pcreg_1_clk),
        .rst_ (pcreg_1_rst_),
        .jump_flag_i(pcreg_1_jump_flag_i),
        .jump_addr_i(pcreg_1_jump_addr_i),

        .pc_o (pcreg_1_pc_o)
    );

    initial begin
        #0 begin
            pcreg_1_clk <= 1'b1;
            pcreg_1_rst_ <= 0;
        end


        #1 begin
            if (pcreg_1_pc_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end
        #1 pcreg_1_rst_ <= 1;


        #1 begin
            if (pcreg_1_pc_o == 32'h4) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 pcreg_1_rst_ <= 0;


        #1 begin
            if (pcreg_1_pc_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end
        #1 pcreg_1_rst_ <= 1;


        #5 begin
            if (pcreg_1_pc_o == 32'hC) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            pcreg_1_jump_flag_i <= 1;
            pcreg_1_jump_addr_i <= 32'hDEADBEEF;
        end


        #1 begin
            if (pcreg_1_pc_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 pcreg_1_jump_flag_i <= 0;


        #3 begin
            if (pcreg_1_pc_o == 32'hDEADBEF7) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        pcreg_1_clk <= ~pcreg_1_clk;
    end

    initial begin
        $dumpfile("pcreg.vcd");
        $dumpvars(0, pcreg_1);
    end

endmodule
module pcreg_test_bench;

    reg pcreg_1_clk;
    reg pcreg_1_rst_;
    reg pcreg_1_jump_flag_i;
    reg[31:0] pcreg_1_jump_addr_i;

    wire[31:0] pcreg_1_pc_o;

    pcreg pcreg_1 (
        .clk  (pcreg_1_clk),
        .rst_ (pcreg_1_rst_),
        .jump_flag_i(pcreg_1_jump_flag_i),
        .jump_addr_i(pcreg_1_jump_addr_i),

        .pc_o (pcreg_1_pc_o)
    );

    initial begin
        #0 begin
            pcreg_1_clk <= 1'b1;
            pcreg_1_rst_ <= 0;
        end


        #1 begin
            if (pcreg_1_pc_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end
        #1 pcreg_1_rst_ <= 1;


        #1 begin
            if (pcreg_1_pc_o == 32'h4) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 pcreg_1_rst_ <= 0;


        #1 begin
            if (pcreg_1_pc_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end
        #1 pcreg_1_rst_ <= 1;


        #5 begin
            if (pcreg_1_pc_o == 32'hC) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            pcreg_1_jump_flag_i <= 1;
            pcreg_1_jump_addr_i <= 32'hDEADBEEF;
        end


        #1 begin
            if (pcreg_1_pc_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 pcreg_1_jump_flag_i <= 0;


        #3 begin
            if (pcreg_1_pc_o == 32'hDEADBEF7) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        pcreg_1_clk <= ~pcreg_1_clk;
    end

    initial begin
        $dumpfile("pcreg.vcd");
        $dumpvars(0, pcreg_1);
    end

endmodule