data/full_repos/permissive/466874195/verilog/rtl/square_accumulate.v
data/verilator_xmls/e1106482-73dc-4453-933a-55fe22002b79.xml
module square_accumulate #
(
    parameter Z_WIDTH = 16
)
(
    input  wire                 clk,
    input  wire                 rst,

    input  wire [7:0]           a,
    input  wire [Z_WIDTH-1:0]   b,
    output reg  [Z_WIDTH-1:0]   z
);

initial begin
    z = 0;
end

wire signed [15:0] s;

assign s = {{8{a[7]}}, a};

always @(posedge clk)
    if (rst)
        z <= 0;
    else
        z <= $unsigned(s * s) + b;

endmodule
module square_accumulate #
(
    parameter Z_WIDTH = 16
)
(
    input  wire                 clk,
    input  wire                 rst,

    input  wire [7:0]           a,
    input  wire [Z_WIDTH-1:0]   b,
    output reg  [Z_WIDTH-1:0]   z
);


initial begin
    z = 0;
end

wire signed [15:0] s;

assign s = {{8{a[7]}}, a};

always @(posedge clk)
    if (rst)
        z <= 0;
    else
        z <= $unsigned(s * s) + b;

endmodule