data/full_repos/permissive/455874613/Projects/Module07/ControlUnit.v
1: b"%Error: data/full_repos/permissive/455874613/Projects/Module07/ControlUnit.v:49: Cannot find file containing module: 'PassCheckUnit'\n PassCheckUnit P(.pass(password),.key(syskey),.equal(write));\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455874613/Projects/Module07,data/full_repos/permissive/455874613/PassCheckUnit\n             data/full_repos/permissive/455874613/Projects/Module07,data/full_repos/permissive/455874613/PassCheckUnit.v\n             data/full_repos/permissive/455874613/Projects/Module07,data/full_repos/permissive/455874613/PassCheckUnit.sv\n             PassCheckUnit\n             PassCheckUnit.v\n             PassCheckUnit.sv\n             obj_dir/PassCheckUnit\n             obj_dir/PassCheckUnit.v\n             obj_dir/PassCheckUnit.sv\n%Error: Exiting due to 1 error(s)\n"
module ControlUnit(
	input         arst      ,
	input         clk       ,
	input         request   ,
	input         confirm   ,
	input  [ 1:0] password  ,
	input  [ 1:0] syskey    ,
	input  [34:0] configin  ,
	output reg [34:0] configout ,
	output reg write_en  ,
	output reg [ 2:0] dbg_state
    );
	wire write;
	PassCheckUnit P(.pass(password),.key(syskey),.equal(write));
	always @ (posedge clk or negedge arst)
	begin
		if (~arst)
		begin
			configout =0;
			write_en = 1'b0;
			dbg_state = `STATE_IDLE;
		end
		else
		begin
			case (dbg_state)
				`STATE_IDLE : begin
					write_en = 1'b0;
					if (request) dbg_state = `STATE_ACTIVE;
				end
				`STATE_ACTIVE : begin
					if (~request) dbg_state = `STATE_IDLE;
					else if (confirm)
					begin
						write_en = write;
						if (write_en)
							dbg_state = `STATE_REQUEST;
						else
							dbg_state = `STATE_TRAP;
					end
					else dbg_state = `STATE_OTHERS;
				end
				`STATE_REQUEST : begin
					if (~request) dbg_state = `STATE_IDLE;
					else if (confirm)
					begin

						configout = configin;
						dbg_state = `STATE_STORE;
					end
					else dbg_state = `STATE_OTHERS;
				end
				`STATE_STORE : begin
					if (~request) dbg_state = `STATE_IDLE;
					else
					begin
						configout = configin;
					end
				end
				`STATE_TRAP : begin

					if (~request) dbg_state = `STATE_IDLE;
				end
				`STATE_OTHERS : begin
					if (write_en) dbg_state = `STATE_REQUEST;
					else dbg_state = `STATE_ACTIVE;
				end	
			endcase
		end
	end

endmodule
module ControlUnit(
	input         arst      ,
	input         clk       ,
	input         request   ,
	input         confirm   ,
	input  [ 1:0] password  ,
	input  [ 1:0] syskey    ,
	input  [34:0] configin  ,
	output reg [34:0] configout ,
	output reg write_en  ,
	output reg [ 2:0] dbg_state
    );

	wire write;
	PassCheckUnit P(.pass(password),.key(syskey),.equal(write));
	always @ (posedge clk or negedge arst)
	begin
		if (~arst)
		begin
			configout =0;
			write_en = 1'b0;
			dbg_state = `STATE_IDLE;
		end
		else
		begin
			case (dbg_state)
				`STATE_IDLE : begin
					write_en = 1'b0;
					if (request) dbg_state = `STATE_ACTIVE;
				end
				`STATE_ACTIVE : begin
					if (~request) dbg_state = `STATE_IDLE;
					else if (confirm)
					begin
						write_en = write;
						if (write_en)
							dbg_state = `STATE_REQUEST;
						else
							dbg_state = `STATE_TRAP;
					end
					else dbg_state = `STATE_OTHERS;
				end
				`STATE_REQUEST : begin
					if (~request) dbg_state = `STATE_IDLE;
					else if (confirm)
					begin

						configout = configin;
						dbg_state = `STATE_STORE;
					end
					else dbg_state = `STATE_OTHERS;
				end
				`STATE_STORE : begin
					if (~request) dbg_state = `STATE_IDLE;
					else
					begin
						configout = configin;
					end
				end
				`STATE_TRAP : begin

					if (~request) dbg_state = `STATE_IDLE;
				end
				`STATE_OTHERS : begin
					if (write_en) dbg_state = `STATE_REQUEST;
					else dbg_state = `STATE_ACTIVE;
				end	
			endcase
		end
	end

endmodule