data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module clockgen_simple(input clk_in, output clk);
	assign clk = clk_in;
endmodule
module clockgen_simple(input clk_in, output clk);

	assign clk = clk_in;
endmodule