data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on basys3)/hours.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: basys3),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: basys3)/hours.v\n%Error: Exiting due to 9 error(s)\n'
module hours(
    input inc_hours,
    input reset,
    output [3:0] hours
    );
    
    reg [3:0] hrs_ctr = 12;
    
    always @(negedge inc_hours or posedge reset) begin
        if(reset)
            hrs_ctr <= 12;
        else
            if(hrs_ctr == 12)
                hrs_ctr <= 1;
            else
                hrs_ctr <= hrs_ctr + 1;
    end
    
    assign hours = hrs_ctr;
    
endmodule
module hours(
    input inc_hours,
    input reset,
    output [3:0] hours
    );

    
    reg [3:0] hrs_ctr = 12;
    
    always @(negedge inc_hours or posedge reset) begin
        if(reset)
            hrs_ctr <= 12;
        else
            if(hrs_ctr == 12)
                hrs_ctr <= 1;
            else
                hrs_ctr <= hrs_ctr + 1;
    end
    
    assign hours = hrs_ctr;
    
endmodule