data/full_repos/permissive/47537295/src/time_int.v
data/verilator_xmls/05a287cb-a97e-48d4-bfc7-8f68b2d88fae.xml
module time_int(
    input clk,
    input rst,
    input sync,
    input [31:0] sync_time,
    output reg [63:0] current_time,
    output reg time_up
    );

		parameter freq=100000000;
		parameter chg_time=30;
		localparam cycle=freq*chg_time;
		
		integer counter;
	
		always @(posedge clk) begin
		if (rst) begin
			counter <= 0;
			if (~sync)
				current_time <= 0;
			else current_time <= {32'b0,sync_time[31:0]};
			time_up <= 1;
		end else begin
			counter <= counter + 1;
			time_up <= 0;
			if (counter == cycle) begin
				counter <= 0;
				current_time <= current_time + 1;
				time_up <= 1;
			end
		end
	end

endmodule
module time_int(
    input clk,
    input rst,
    input sync,
    input [31:0] sync_time,
    output reg [63:0] current_time,
    output reg time_up
    );


		parameter freq=100000000;
		parameter chg_time=30;
		localparam cycle=freq*chg_time;
		
		integer counter;
	
		always @(posedge clk) begin
		if (rst) begin
			counter <= 0;
			if (~sync)
				current_time <= 0;
			else current_time <= {32'b0,sync_time[31:0]};
			time_up <= 1;
		end else begin
			counter <= counter + 1;
			time_up <= 0;
			if (counter == cycle) begin
				counter <= 0;
				current_time <= current_time + 1;
				time_up <= 1;
			end
		end
	end

endmodule