data/full_repos/permissive/418819021/lab-05/unitTestCpu.v
1: b'%Error: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:15: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n    wire [`TEST_I_ADDR_WIDTH-1:0] pc            ;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:16: Define or directive not defined: \'`STAGE_COUNT\'\n    wire [      `STAGE_COUNT-1:0] pipeline_stage;\n                ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:27: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:30: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("waves.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:31: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, unitTestCpu);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/418819021/lab-05/unitTestCpu.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #740;\n        ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module unitTestCpu ();


    reg clk  ;
    reg reset;


    wire                          result        ;
    wire [`TEST_I_ADDR_WIDTH-1:0] pc            ;
    wire [      `STAGE_COUNT-1:0] pipeline_stage;


    unitTest uut (
        .clk                  (clk           ),
        .reset                (reset         ),
        .result               (result        ),
        .debug_program_counter(pc            ),
        .debug_pipeline_stage (pipeline_stage)
    );

    always #10 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, unitTestCpu);

        clk = 0;
        reset = 1;


        #10;
        reset = 0;


        #740;
        $finish();
    end

endmodule
module unitTestCpu ();



    reg clk  ;
    reg reset;


    wire                          result        ;
    wire [`TEST_I_ADDR_WIDTH-1:0] pc            ;
    wire [      `STAGE_COUNT-1:0] pipeline_stage;


    unitTest uut (
        .clk                  (clk           ),
        .reset                (reset         ),
        .result               (result        ),
        .debug_program_counter(pc            ),
        .debug_pipeline_stage (pipeline_stage)
    );

    always #10 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, unitTestCpu);

        clk = 0;
        reset = 1;


        #10;
        reset = 0;


        #740;
        $finish();
    end

endmodule