data/full_repos/permissive/461141714/src/Pipelined CPU/pc_predictor.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/pc_predictor.v\n%Error: Exiting due to 3 error(s)\n'
module PC_PREDICTOR(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] PC,
        input [`WORD_SIZE-1:0] instruction,
        output reg [`WORD_SIZE-1:0] nextPC,
        

        input forcePC,
        input [`WORD_SIZE-1:0] forcePCdata
    );
    


    

    wire [3:0] opcode = instruction[15:12];
    wire [`WORD_SIZE-1:0] offset = {{8{instruction[7]}}, instruction[7:0]};
    
    reg reset_n_switch;
    initial reset_n_switch = 1;
    
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            reset_n_switch = 0;
        end
    end
    always @(posedge clk) begin
        if(reset_n != 0) reset_n_switch = 1;
        

    end
    
    always @(*) begin
    
        if(reset_n == 0) begin
            nextPC = `WORD_SIZE'b0;
            reset_n_switch = 0;
        end
        else begin
            if(opcode == `OPCODE_JMP || opcode == `OPCODE_JAL) begin
                nextPC = {PC[15:12], instruction[11:0]};
            end
            else if(opcode == `OPCODE_BNE || opcode == `OPCODE_BEQ || opcode == `OPCODE_BGZ || opcode == `OPCODE_BLZ) begin
                nextPC = PC + 1 + offset;
            end
            else begin
                nextPC = PC + 1;
            end
        end
        
    end
    

    
endmodule
module PC_PREDICTOR(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] PC,
        input [`WORD_SIZE-1:0] instruction,
        output reg [`WORD_SIZE-1:0] nextPC,
        

        input forcePC,
        input [`WORD_SIZE-1:0] forcePCdata
    );

    


    

    wire [3:0] opcode = instruction[15:12];
    wire [`WORD_SIZE-1:0] offset = {{8{instruction[7]}}, instruction[7:0]};
    
    reg reset_n_switch;
    initial reset_n_switch = 1;
    
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            reset_n_switch = 0;
        end
    end
    always @(posedge clk) begin
        if(reset_n != 0) reset_n_switch = 1;
        

    end
    
    always @(*) begin
    
        if(reset_n == 0) begin
            nextPC = `WORD_SIZE'b0;
            reset_n_switch = 0;
        end
        else begin
            if(opcode == `OPCODE_JMP || opcode == `OPCODE_JAL) begin
                nextPC = {PC[15:12], instruction[11:0]};
            end
            else if(opcode == `OPCODE_BNE || opcode == `OPCODE_BEQ || opcode == `OPCODE_BGZ || opcode == `OPCODE_BLZ) begin
                nextPC = PC + 1 + offset;
            end
            else begin
                nextPC = PC + 1;
            end
        end
        
    end
    

    
endmodule