data/full_repos/permissive/406635962/src/rtl/exu_oitf.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:7: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:15: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] dis_ptr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:16: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] ret_ptr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:18: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] ret_rdidx,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:25: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:26: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:27: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:39: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] vld_set;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:40: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] vld_clr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:41: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] vld_ena;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:42: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] vld_nxt;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:43: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] vld_r;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:44: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] rdwen_r;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:45: Define or directive not defined: \'`RFIDX_WIDTH\'\n    wire [`RFIDX_WIDTH-1:0] rdidx_r[`OITF_DEPTH-1:0];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:45: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`RFIDX_WIDTH-1:0] rdidx_r[`OITF_DEPTH-1:0];\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:53: Define or directive not defined: \'`ITAG_WIDTH\'\n    wire [`ITAG_WIDTH-1:0] alc_ptr_r;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:54: Define or directive not defined: \'`ITAG_WIDTH\'\n    wire [`ITAG_WIDTH-1:0] ret_ptr_r;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:57: Define or directive not defined: \'`OITF_DEPTH\'\n        if(`OITF_DEPTH > 1) begin: depth_gt1\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:57: syntax error, unexpected \'>\', expecting TYPE-IDENTIFIER\n        if(`OITF_DEPTH > 1) begin: depth_gt1\n                       ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:61: Define or directive not defined: \'`OITF_DEPTH\'\n            wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`OITF_DEPTH-1))) & alc_ptr_ena;\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:62: Define or directive not defined: \'`ITAG_WIDTH\'\n            wire [`ITAG_WIDTH-1:0] alc_ptr_nxt = alc_ptr_flg_ena ? `ITAG_WIDTH\'b0: (alc_ptr_r + 1\'b1);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:62: Define or directive not defined: \'`ITAG_WIDTH\'\n            wire [`ITAG_WIDTH-1:0] alc_ptr_nxt = alc_ptr_flg_ena ? `ITAG_WIDTH\'b0: (alc_ptr_r + 1\'b1);\n                                                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:66: Define or directive not defined: \'`OITF_DEPTH\'\n            wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`OITF_DEPTH-1))) & ret_ptr_ena;\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:67: Define or directive not defined: \'`ITAG_WIDTH\'\n            wire [`ITAG_WIDTH-1:0] ret_ptr_nxt = ret_ptr_flg_ena? `ITAG_WIDTH\'b0:(ret_ptr_r + 1\'b1);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:67: Define or directive not defined: \'`ITAG_WIDTH\'\n            wire [`ITAG_WIDTH-1:0] ret_ptr_nxt = ret_ptr_flg_ena? `ITAG_WIDTH\'b0:(ret_ptr_r + 1\'b1);\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:70: Define or directive not defined: \'`ITAG_WIDTH\'\n            gnrl_dfflr #(`ITAG_WIDTH) alc_ptr_dfflr(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:72: Define or directive not defined: \'`ITAG_WIDTH\'\n            gnrl_dfflr #(`ITAG_WIDTH) ret_ptr_dfflr(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:76: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:82: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:91: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] rd_match_rs1idx;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:92: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] rd_match_rs2idx;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:93: Define or directive not defined: \'`OITF_DEPTH\'\n    wire [`OITF_DEPTH-1:0] rd_match_rdidx;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:96: syntax error, unexpected generate\n    generate\n    ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:97: Define or directive not defined: \'`OITF_DEPTH\'\n        for(i=0; i<`OITF_DEPTH;i=i+1) begin:oitf_entries\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:104: Define or directive not defined: \'`RFIDX_WIDTH\'\n            gnrl_dfflr #(`RFIDX_WIDTH) rdidx_dffl(vld_set[i], disp_i_rdidx, rdidx_r[i],clk, rst_n);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:111: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_oitf.v:120: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module exu_oitf (
    output disp_ready,

    input disp_ena,
    input ret_ena,

    output [`ITAG_WIDTH-1:0] dis_ptr,
    output [`ITAG_WIDTH-1:0] ret_ptr,

    output [`RFIDX_WIDTH-1:0] ret_rdidx,
    output ret_rdwen,


    input disp_i_rs1en,
    input disp_i_rs2en,
    input disp_i_rdwen,
    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,

    

    output oitfrd_match_disprs1,
    output oitfrd_match_disprs2,
    output oitfrd_match_disprd,

    output oitf_empty,
    input clk,
    input rst_n
);
    wire [`OITF_DEPTH-1:0] vld_set;
    wire [`OITF_DEPTH-1:0] vld_clr;
    wire [`OITF_DEPTH-1:0] vld_ena;
    wire [`OITF_DEPTH-1:0] vld_nxt;
    wire [`OITF_DEPTH-1:0] vld_r;
    wire [`OITF_DEPTH-1:0] rdwen_r;
    wire [`RFIDX_WIDTH-1:0] rdidx_r[`OITF_DEPTH-1:0];


    wire alc_ptr_ena = disp_ena;
    wire ret_ptr_ena = ret_ena;

    wire oitf_full;

    wire [`ITAG_WIDTH-1:0] alc_ptr_r;
    wire [`ITAG_WIDTH-1:0] ret_ptr_r;

    generate
        if(`OITF_DEPTH > 1) begin: depth_gt1

            wire alc_ptr_flg_r;
            wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
            wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`OITF_DEPTH-1))) & alc_ptr_ena;
            wire [`ITAG_WIDTH-1:0] alc_ptr_nxt = alc_ptr_flg_ena ? `ITAG_WIDTH'b0: (alc_ptr_r + 1'b1);

            wire ret_ptr_flg_r;
            wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
            wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`OITF_DEPTH-1))) & ret_ptr_ena;
            wire [`ITAG_WIDTH-1:0] ret_ptr_nxt = ret_ptr_flg_ena? `ITAG_WIDTH'b0:(ret_ptr_r + 1'b1);

            gnrl_dfflr #(1) alc_ptr_flg_dfflr(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
            gnrl_dfflr #(`ITAG_WIDTH) alc_ptr_dfflr(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
            gnrl_dfflr #(1) ret_ptr_flg_dfflr(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
            gnrl_dfflr #(`ITAG_WIDTH) ret_ptr_dfflr(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
            
            assign oitf_empty = (alc_ptr_r == ret_ptr_r) & (ret_ptr_flg_r == alc_ptr_flg_r);
            assign oitf_full = (alc_ptr_r == ret_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
        end
        else begin: depth_eq1
            assign alc_ptr_r = 1'b0;
            assign ret_ptr_r = 1'b0;
            assign oitf_empty = ~vld_r[0];
            assign oitf_full = vld_r[0];
        end
    endgenerate
    assign dis_ptr = alc_ptr_r;
    assign ret_ptr = ret_ptr_r;
    

    assign disp_ready = ~oitf_full;


    wire [`OITF_DEPTH-1:0] rd_match_rs1idx;
    wire [`OITF_DEPTH-1:0] rd_match_rs2idx;
    wire [`OITF_DEPTH-1:0] rd_match_rdidx;

    genvar i;
    generate
        for(i=0; i<`OITF_DEPTH;i=i+1) begin:oitf_entries
            assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
            assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
            assign vld_ena[i] = vld_set[i] | vld_clr[i];
            assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);

            gnrl_dfflr #(1) vld_dfflr(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
            gnrl_dfflr #(`RFIDX_WIDTH) rdidx_dffl(vld_set[i], disp_i_rdidx, rdidx_r[i],clk, rst_n);
            gnrl_dfflr #(1) rdwen_dffl(vld_set[i], disp_i_rdwen, rdwen_r[i], clk, rst_n);


            assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdidx_r[i] == disp_i_rs1idx);
            assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdidx_r[i] == disp_i_rs2idx);
            assign rd_match_rdidx[i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdidx_r[i] == disp_i_rdidx);
        end
    endgenerate

    assign oitfrd_match_disprs1 = |rd_match_rs1idx;
    assign oitfrd_match_disprs2 = |rd_match_rs2idx;
    assign oitfrd_match_disprd = |rd_match_rdidx;
    
    assign ret_rdidx = rdidx_r[ret_ptr];
    assign ret_rdwen = rdwen_r[ret_ptr];
endmodule
module exu_oitf (
    output disp_ready,

    input disp_ena,
    input ret_ena,

    output [`ITAG_WIDTH-1:0] dis_ptr,
    output [`ITAG_WIDTH-1:0] ret_ptr,

    output [`RFIDX_WIDTH-1:0] ret_rdidx,
    output ret_rdwen,


    input disp_i_rs1en,
    input disp_i_rs2en,
    input disp_i_rdwen,
    input [`RFIDX_WIDTH-1:0] disp_i_rs1idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rs2idx,
    input [`RFIDX_WIDTH-1:0] disp_i_rdidx,

    

    output oitfrd_match_disprs1,
    output oitfrd_match_disprs2,
    output oitfrd_match_disprd,

    output oitf_empty,
    input clk,
    input rst_n
);

    wire [`OITF_DEPTH-1:0] vld_set;
    wire [`OITF_DEPTH-1:0] vld_clr;
    wire [`OITF_DEPTH-1:0] vld_ena;
    wire [`OITF_DEPTH-1:0] vld_nxt;
    wire [`OITF_DEPTH-1:0] vld_r;
    wire [`OITF_DEPTH-1:0] rdwen_r;
    wire [`RFIDX_WIDTH-1:0] rdidx_r[`OITF_DEPTH-1:0];


    wire alc_ptr_ena = disp_ena;
    wire ret_ptr_ena = ret_ena;

    wire oitf_full;

    wire [`ITAG_WIDTH-1:0] alc_ptr_r;
    wire [`ITAG_WIDTH-1:0] ret_ptr_r;

    generate
        if(`OITF_DEPTH > 1) begin: depth_gt1

            wire alc_ptr_flg_r;
            wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
            wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`OITF_DEPTH-1))) & alc_ptr_ena;
            wire [`ITAG_WIDTH-1:0] alc_ptr_nxt = alc_ptr_flg_ena ? `ITAG_WIDTH'b0: (alc_ptr_r + 1'b1);

            wire ret_ptr_flg_r;
            wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
            wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`OITF_DEPTH-1))) & ret_ptr_ena;
            wire [`ITAG_WIDTH-1:0] ret_ptr_nxt = ret_ptr_flg_ena? `ITAG_WIDTH'b0:(ret_ptr_r + 1'b1);

            gnrl_dfflr #(1) alc_ptr_flg_dfflr(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
            gnrl_dfflr #(`ITAG_WIDTH) alc_ptr_dfflr(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
            gnrl_dfflr #(1) ret_ptr_flg_dfflr(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
            gnrl_dfflr #(`ITAG_WIDTH) ret_ptr_dfflr(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
            
            assign oitf_empty = (alc_ptr_r == ret_ptr_r) & (ret_ptr_flg_r == alc_ptr_flg_r);
            assign oitf_full = (alc_ptr_r == ret_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
        end
        else begin: depth_eq1
            assign alc_ptr_r = 1'b0;
            assign ret_ptr_r = 1'b0;
            assign oitf_empty = ~vld_r[0];
            assign oitf_full = vld_r[0];
        end
    endgenerate
    assign dis_ptr = alc_ptr_r;
    assign ret_ptr = ret_ptr_r;
    

    assign disp_ready = ~oitf_full;


    wire [`OITF_DEPTH-1:0] rd_match_rs1idx;
    wire [`OITF_DEPTH-1:0] rd_match_rs2idx;
    wire [`OITF_DEPTH-1:0] rd_match_rdidx;

    genvar i;
    generate
        for(i=0; i<`OITF_DEPTH;i=i+1) begin:oitf_entries
            assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
            assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
            assign vld_ena[i] = vld_set[i] | vld_clr[i];
            assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);

            gnrl_dfflr #(1) vld_dfflr(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
            gnrl_dfflr #(`RFIDX_WIDTH) rdidx_dffl(vld_set[i], disp_i_rdidx, rdidx_r[i],clk, rst_n);
            gnrl_dfflr #(1) rdwen_dffl(vld_set[i], disp_i_rdwen, rdwen_r[i], clk, rst_n);


            assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdidx_r[i] == disp_i_rs1idx);
            assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdidx_r[i] == disp_i_rs2idx);
            assign rd_match_rdidx[i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdidx_r[i] == disp_i_rdidx);
        end
    endgenerate

    assign oitfrd_match_disprs1 = |rd_match_rs1idx;
    assign oitfrd_match_disprs2 = |rd_match_rs2idx;
    assign oitfrd_match_disprd = |rd_match_rdidx;
    
    assign ret_rdidx = rdidx_r[ret_ptr];
    assign ret_rdwen = rdwen_r[ret_ptr];
endmodule