data/full_repos/permissive/479997390/src/InstrMem.v
data/verilator_xmls/a2bcd93a-143c-43b4-be20-afa6e48ffddb.xml
module InstrMem_4k( InstrAddr, InstrOut );
    
    input [11:2] InstrAddr;
    output [31:0] InstrOut;
    
    (* ram_style="block" *) reg [31:0] imem[1023:0];
    
    assign InstrOut = imem[InstrAddr];
    
endmodule
module InstrMem_4k( InstrAddr, InstrOut );

    
    input [11:2] InstrAddr;
    output [31:0] InstrOut;
    
    (* ram_style="block" *) reg [31:0] imem[1023:0];
    
    assign InstrOut = imem[InstrAddr];
    
endmodule