data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv:63: Cannot find file containing module: 'simplex_xbar'\n  simplex_xbar #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/simplex_xbar\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/simplex_xbar.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect,data/full_repos/permissive/489147019/simplex_xbar.sv\n             simplex_xbar\n             simplex_xbar.v\n             simplex_xbar.sv\n             obj_dir/simplex_xbar\n             obj_dir/simplex_xbar.v\n             obj_dir/simplex_xbar.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv:85: Cannot find file containing module: 'simplex_xbar'\n  simplex_xbar #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module full_duplex_xbar #(
  parameter int unsigned NumIn         = 4,
  parameter int unsigned NumOut        = 4,
  parameter int unsigned ReqDataWidth  = 32,
  parameter int unsigned RespDataWidth = 32,
  parameter bit ExtPrio                = 1'b0,
  parameter bit SpillRegisterReq       = 1'b0,
  parameter bit SpillRegisterResp      = 1'b0,
  parameter bit AxiVldRdy              = 1'b0,
  parameter bit FallThroughRegister    = 1'b0,

  localparam int unsigned NumInLog     = NumIn == 1 ? 1 : $clog2(NumIn),
  localparam int unsigned NumOutLog    = NumOut == 1 ? 1 : $clog2(NumOut)
) (
  input  logic                                 clk_i,
  input  logic                                 rst_ni,

  input  logic [NumOut-1:0][NumInLog-1:0]      req_rr_i,
  input  logic [NumIn-1:0][NumOutLog-1:0]      resp_rr_i,

  input  logic [NumIn-1:0]                     req_valid_i,
  output logic [NumIn-1:0]                     req_ready_o,
  input  logic [NumIn-1:0][NumOutLog-1:0]      req_tgt_addr_i,
  input  logic [NumIn-1:0][ReqDataWidth-1:0]   req_wdata_i,
  output logic [NumIn-1:0]                     resp_valid_o,
  input  logic [NumIn-1:0]                     resp_ready_i,
  output logic [NumIn-1:0][RespDataWidth-1:0]  resp_rdata_o,

  output logic [NumOut-1:0]                    req_valid_o,
  input  logic [NumOut-1:0]                    req_ready_i,
  output logic [NumOut-1:0][NumInLog-1:0]      req_ini_addr_o,
  output logic [NumOut-1:0][ReqDataWidth-1:0]  req_wdata_o,
  input  logic [NumOut-1:0]                    resp_valid_i,
  output logic [NumOut-1:0]                    resp_ready_o,
  input  logic [NumOut-1:0][NumInLog-1:0]      resp_ini_addr_i,
  input  logic [NumOut-1:0][RespDataWidth-1:0] resp_rdata_i
);





  simplex_xbar #(
    .NumIn              (NumIn              ),
    .NumOut             (NumOut             ),
    .DataWidth          (ReqDataWidth       ),
    .ExtPrio            (ExtPrio            ),
    .AxiVldRdy          (AxiVldRdy          ),
    .SpillRegister      (SpillRegisterReq   ),
    .FallThroughRegister(FallThroughRegister)
  ) req_xbar (
    .clk_i     (clk_i         ),
    .rst_ni    (rst_ni        ),
    .rr_i      (req_rr_i      ),
    .valid_i   (req_valid_i   ),
    .ready_o   (req_ready_o   ),
    .tgt_addr_i(req_tgt_addr_i),
    .data_i    (req_wdata_i   ),
    .valid_o   (req_valid_o   ),
    .ini_addr_o(req_ini_addr_o),
    .ready_i   (req_ready_i   ),
    .data_o    (req_wdata_o   )
  );

  simplex_xbar #(
    .NumIn              (NumOut             ),
    .NumOut             (NumIn              ),
    .DataWidth          (RespDataWidth      ),
    .ExtPrio            (ExtPrio            ),
    .AxiVldRdy          (AxiVldRdy          ),
    .SpillRegister      (SpillRegisterResp  ),
    .FallThroughRegister(FallThroughRegister)
  ) resp_xbar (
    .clk_i     (clk_i          ),
    .rst_ni    (rst_ni         ),
    .rr_i      (resp_rr_i      ),
    .valid_i   (resp_valid_i   ),
    .ready_o   (resp_ready_o   ),
    .tgt_addr_i(resp_ini_addr_i),
    .data_i    (resp_rdata_i   ),
    .valid_o   (resp_valid_o   ),
    .ini_addr_o(),
    .ready_i   (resp_ready_i   ),
    .data_o    (resp_rdata_o   )
  );



  if (NumIn <= 0)
    $fatal(1, "[full_duplex_xbar] NumIn needs to be larger than 0.");

  if (NumOut <= 0)
    $fatal(1, "[full_duplex_xbar] NumOut needs to be larger than 0.");

endmodule
module full_duplex_xbar #(
  parameter int unsigned NumIn         = 4,
  parameter int unsigned NumOut        = 4,
  parameter int unsigned ReqDataWidth  = 32,
  parameter int unsigned RespDataWidth = 32,
  parameter bit ExtPrio                = 1'b0,
  parameter bit SpillRegisterReq       = 1'b0,
  parameter bit SpillRegisterResp      = 1'b0,
  parameter bit AxiVldRdy              = 1'b0,
  parameter bit FallThroughRegister    = 1'b0,

  localparam int unsigned NumInLog     = NumIn == 1 ? 1 : $clog2(NumIn),
  localparam int unsigned NumOutLog    = NumOut == 1 ? 1 : $clog2(NumOut)
) (
  input  logic                                 clk_i,
  input  logic                                 rst_ni,

  input  logic [NumOut-1:0][NumInLog-1:0]      req_rr_i,
  input  logic [NumIn-1:0][NumOutLog-1:0]      resp_rr_i,

  input  logic [NumIn-1:0]                     req_valid_i,
  output logic [NumIn-1:0]                     req_ready_o,
  input  logic [NumIn-1:0][NumOutLog-1:0]      req_tgt_addr_i,
  input  logic [NumIn-1:0][ReqDataWidth-1:0]   req_wdata_i,
  output logic [NumIn-1:0]                     resp_valid_o,
  input  logic [NumIn-1:0]                     resp_ready_i,
  output logic [NumIn-1:0][RespDataWidth-1:0]  resp_rdata_o,

  output logic [NumOut-1:0]                    req_valid_o,
  input  logic [NumOut-1:0]                    req_ready_i,
  output logic [NumOut-1:0][NumInLog-1:0]      req_ini_addr_o,
  output logic [NumOut-1:0][ReqDataWidth-1:0]  req_wdata_o,
  input  logic [NumOut-1:0]                    resp_valid_i,
  output logic [NumOut-1:0]                    resp_ready_o,
  input  logic [NumOut-1:0][NumInLog-1:0]      resp_ini_addr_i,
  input  logic [NumOut-1:0][RespDataWidth-1:0] resp_rdata_i
);






  simplex_xbar #(
    .NumIn              (NumIn              ),
    .NumOut             (NumOut             ),
    .DataWidth          (ReqDataWidth       ),
    .ExtPrio            (ExtPrio            ),
    .AxiVldRdy          (AxiVldRdy          ),
    .SpillRegister      (SpillRegisterReq   ),
    .FallThroughRegister(FallThroughRegister)
  ) req_xbar (
    .clk_i     (clk_i         ),
    .rst_ni    (rst_ni        ),
    .rr_i      (req_rr_i      ),
    .valid_i   (req_valid_i   ),
    .ready_o   (req_ready_o   ),
    .tgt_addr_i(req_tgt_addr_i),
    .data_i    (req_wdata_i   ),
    .valid_o   (req_valid_o   ),
    .ini_addr_o(req_ini_addr_o),
    .ready_i   (req_ready_i   ),
    .data_o    (req_wdata_o   )
  );

  simplex_xbar #(
    .NumIn              (NumOut             ),
    .NumOut             (NumIn              ),
    .DataWidth          (RespDataWidth      ),
    .ExtPrio            (ExtPrio            ),
    .AxiVldRdy          (AxiVldRdy          ),
    .SpillRegister      (SpillRegisterResp  ),
    .FallThroughRegister(FallThroughRegister)
  ) resp_xbar (
    .clk_i     (clk_i          ),
    .rst_ni    (rst_ni         ),
    .rr_i      (resp_rr_i      ),
    .valid_i   (resp_valid_i   ),
    .ready_o   (resp_ready_o   ),
    .tgt_addr_i(resp_ini_addr_i),
    .data_i    (resp_rdata_i   ),
    .valid_o   (resp_valid_o   ),
    .ini_addr_o(),
    .ready_i   (resp_ready_i   ),
    .data_o    (resp_rdata_o   )
  );



  if (NumIn <= 0)
    $fatal(1, "[full_duplex_xbar] NumIn needs to be larger than 0.");

  if (NumOut <= 0)
    $fatal(1, "[full_duplex_xbar] NumOut needs to be larger than 0.");

endmodule