data/full_repos/permissive/515100461/pipeline/processor.v
1: b'%Error: data/full_repos/permissive/515100461/pipeline/processor.v:1: Cannot find include file: fetch.v\n`include "fetch.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/pipeline,data/full_repos/permissive/515100461/fetch.v\n             data/full_repos/permissive/515100461/pipeline,data/full_repos/permissive/515100461/fetch.v.v\n             data/full_repos/permissive/515100461/pipeline,data/full_repos/permissive/515100461/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:2: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:3: Cannot find include file: decode.v\n`include "decode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:4: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:5: Cannot find include file: pcupdate.v\n`include "pcupdate.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:115: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:116: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,proc_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/pipeline/processor.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/515100461/pipeline/processor.v:176: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d,pc=%d,m_valM=%d,e_valE=%d,f_icode=%d,reg[3]=%d",clock,PC,m_valM,e_valE,f_icode,regmem3);\n  ^~~~~~~~\n%Error: Exiting due to 8 error(s), 16 warning(s)\n'
module proc_tb;

reg clk=0;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
reg [2:0]status;
wire inst_valid, mem_error;
reg[4:0] clock;


  wire [2:0]  f_stat;
  wire [3:0]  f_icode;
  wire [3:0]  f_ifun; 
  wire [3:0]  f_rA;
  wire [3:0]  f_rB;
  wire [63:0] f_valC;
  wire [63:0] f_valP;
  wire [3:0]  f_dstM;
  
  wire [2:0]  d_stat;
  wire [2:0]  D_stat;
  wire [3:0]  d_icode;
  wire [3:0]  d_ifun;
  wire [3:0]  d_rA;
  wire [3:0]  d_rB;
  wire [63:0] d_valC;
  wire [63:0] d_valP;
  wire [63:0] d_valA;
  wire [63:0] d_valB;
  wire [3:0]  d_srcA;
  wire [3:0]  d_srcB;
  wire [3:0]  d_dstM;
  wire d_bubble;


  wire [2:0]  e_stat;
  wire [2:0]  E_stat;
  wire [3:0]  e_icode,E_icode;
  wire [3:0]  e_ifun;
  wire        e_cnd;
  wire [3:0]  e_rA;
  wire [3:0]  e_rB;
  wire [63:0] e_valC;
  wire [63:0] e_valP;
  wire [63:0] e_valA;
  wire [63:0] e_valB;
  wire [63:0] e_valE;
  wire [3:0]  e_dstE;
  wire [3:0]  e_dstM;


  wire [2:0]  m_stat;
  wire [2:0]  M_stat;
  wire [3:0]  m_icode,m_ifun,M_icode;
  wire        m_cnd;
  wire [3:0]  m_rA;
  wire [3:0]  m_rB;
  wire [63:0] m_valC;
  wire [63:0] m_valP;
  wire [63:0] m_valA;
  wire [63:0] m_valB;
  wire [63:0] m_valE;
  wire [63:0] m_valM;
  wire [3:0]  m_dstE;
  wire [3:0]  m_dstM;
  
  wire [2:0]  w_stat ;
  wire [2:0]  W_stat;
  wire [3:0]  w_icode,w_ifun;
  wire        w_cnd;
  wire [3:0]  w_rA;
  wire [3:0]  w_rB;
  wire [63:0] w_valC;
  wire [63:0] w_valP;
  wire [63:0] w_valA;
  wire [63:0] w_valB;
  wire [63:0] w_valE;
  wire [63:0] w_valM;
  wire [3:0]  w_dstE;
  wire [3:0]  w_dstM;

wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6;
wire signed [63:0] regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire hlt;
wire [63:0] pc_pred;
fetch uut1(clk,PC,m_icode,m_ifun,m_cnd,m_valA,w_icode,w_valM,
           f_stat,f_icode,f_ifun,f_rA,f_rB,f_valC,f_valP,f_dstM,
           pc_pred,D_stat,d_icode,d_ifun,d_rA,d_rB,d_valC,d_valP,d_dstM,d_srcA,d_srcB,d_bubble,
           e_icode,e_dstM);

execute uut3(clk,d_srcA,d_srcB,E_icode,e_icode,e_ifun,e_rA,e_rB,e_valC,e_valP,e_valA,e_valB,e_cnd,e_valE,e_dstE,e_dstM,E_stat,
             M_icode,m_ifun,m_rA,m_rB,m_valC,m_valP,m_valA,m_valB,m_cnd,m_valE,m_dstE,m_dstM,M_stat);

decode uut2(clk,d_icode,d_ifun,d_rA,d_rB,d_dstM,D_stat,
            w_rA,w_rB,w_icode,w_dstE,w_dstM,w_valM,w_valE,d_valC,d_valP,m_cnd,m_valE,
            m_valM,m_dstM,m_dstE,m_icode,
            regmem0,regmem1,regmem2,regmem3,
            regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,
            regmem15,d_valA,d_valB,d_srcA,d_srcB,d_bubble,
            e_valE,E_icode,e_icode,e_ifun,e_rA,e_rB,e_valC,e_valP,e_valA,e_valB,e_dstE,e_dstM,E_stat,e_cnd);

memory uut4(clk,M_icode,m_icode,m_ifun,m_rA,m_rB,m_valC,m_valP,m_valA,m_valB,m_cnd,m_valE,m_valM,m_dstM,M_stat,m_stat,
            w_icode,w_ifun,w_rA,w_rB,w_valC,w_valP,w_valA,w_valB,w_cnd,w_valE,w_valM,w_dstM,W_stat);


initial 
begin
  $dumpfile("dump.vcd");
    $dumpvars(0,proc_tb);

    clock = 0;
    PC = 64'd39;
    clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;




end
 always@(*)
 begin
   if(hlt==1) 
   begin
   status = 2'b01;
    $display("status=%d Halt has occured!",status);
    $finish;
   end
   if(mem_error==1) 
   begin
   status = 2'b10;
   $display("status=%d memory error has occured!",status);
   $finish;
   end






   else  status = 2'b00;

  if(clk==1)clock = clock+1;
 end   
 
always@(negedge clk) PC = pc_pred;



initial 




  $monitor("clk=%d,pc=%d,m_valM=%d,e_valE=%d,f_icode=%d,reg[3]=%d",clock,PC,m_valM,e_valE,f_icode,regmem3);

endmodule
module proc_tb;


reg clk=0;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
reg [2:0]status;
wire inst_valid, mem_error;
reg[4:0] clock;


  wire [2:0]  f_stat;
  wire [3:0]  f_icode;
  wire [3:0]  f_ifun; 
  wire [3:0]  f_rA;
  wire [3:0]  f_rB;
  wire [63:0] f_valC;
  wire [63:0] f_valP;
  wire [3:0]  f_dstM;
  
  wire [2:0]  d_stat;
  wire [2:0]  D_stat;
  wire [3:0]  d_icode;
  wire [3:0]  d_ifun;
  wire [3:0]  d_rA;
  wire [3:0]  d_rB;
  wire [63:0] d_valC;
  wire [63:0] d_valP;
  wire [63:0] d_valA;
  wire [63:0] d_valB;
  wire [3:0]  d_srcA;
  wire [3:0]  d_srcB;
  wire [3:0]  d_dstM;
  wire d_bubble;


  wire [2:0]  e_stat;
  wire [2:0]  E_stat;
  wire [3:0]  e_icode,E_icode;
  wire [3:0]  e_ifun;
  wire        e_cnd;
  wire [3:0]  e_rA;
  wire [3:0]  e_rB;
  wire [63:0] e_valC;
  wire [63:0] e_valP;
  wire [63:0] e_valA;
  wire [63:0] e_valB;
  wire [63:0] e_valE;
  wire [3:0]  e_dstE;
  wire [3:0]  e_dstM;


  wire [2:0]  m_stat;
  wire [2:0]  M_stat;
  wire [3:0]  m_icode,m_ifun,M_icode;
  wire        m_cnd;
  wire [3:0]  m_rA;
  wire [3:0]  m_rB;
  wire [63:0] m_valC;
  wire [63:0] m_valP;
  wire [63:0] m_valA;
  wire [63:0] m_valB;
  wire [63:0] m_valE;
  wire [63:0] m_valM;
  wire [3:0]  m_dstE;
  wire [3:0]  m_dstM;
  
  wire [2:0]  w_stat ;
  wire [2:0]  W_stat;
  wire [3:0]  w_icode,w_ifun;
  wire        w_cnd;
  wire [3:0]  w_rA;
  wire [3:0]  w_rB;
  wire [63:0] w_valC;
  wire [63:0] w_valP;
  wire [63:0] w_valA;
  wire [63:0] w_valB;
  wire [63:0] w_valE;
  wire [63:0] w_valM;
  wire [3:0]  w_dstE;
  wire [3:0]  w_dstM;

wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6;
wire signed [63:0] regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire hlt;
wire [63:0] pc_pred;
fetch uut1(clk,PC,m_icode,m_ifun,m_cnd,m_valA,w_icode,w_valM,
           f_stat,f_icode,f_ifun,f_rA,f_rB,f_valC,f_valP,f_dstM,
           pc_pred,D_stat,d_icode,d_ifun,d_rA,d_rB,d_valC,d_valP,d_dstM,d_srcA,d_srcB,d_bubble,
           e_icode,e_dstM);

execute uut3(clk,d_srcA,d_srcB,E_icode,e_icode,e_ifun,e_rA,e_rB,e_valC,e_valP,e_valA,e_valB,e_cnd,e_valE,e_dstE,e_dstM,E_stat,
             M_icode,m_ifun,m_rA,m_rB,m_valC,m_valP,m_valA,m_valB,m_cnd,m_valE,m_dstE,m_dstM,M_stat);

decode uut2(clk,d_icode,d_ifun,d_rA,d_rB,d_dstM,D_stat,
            w_rA,w_rB,w_icode,w_dstE,w_dstM,w_valM,w_valE,d_valC,d_valP,m_cnd,m_valE,
            m_valM,m_dstM,m_dstE,m_icode,
            regmem0,regmem1,regmem2,regmem3,
            regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,
            regmem15,d_valA,d_valB,d_srcA,d_srcB,d_bubble,
            e_valE,E_icode,e_icode,e_ifun,e_rA,e_rB,e_valC,e_valP,e_valA,e_valB,e_dstE,e_dstM,E_stat,e_cnd);

memory uut4(clk,M_icode,m_icode,m_ifun,m_rA,m_rB,m_valC,m_valP,m_valA,m_valB,m_cnd,m_valE,m_valM,m_dstM,M_stat,m_stat,
            w_icode,w_ifun,w_rA,w_rB,w_valC,w_valP,w_valA,w_valB,w_cnd,w_valE,w_valM,w_dstM,W_stat);


initial 
begin
  $dumpfile("dump.vcd");
    $dumpvars(0,proc_tb);

    clock = 0;
    PC = 64'd39;
    clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk; 
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;
    #10 clk=~clk;




end
 always@(*)
 begin
   if(hlt==1) 
   begin
   status = 2'b01;
    $display("status=%d Halt has occured!",status);
    $finish;
   end
   if(mem_error==1) 
   begin
   status = 2'b10;
   $display("status=%d memory error has occured!",status);
   $finish;
   end






   else  status = 2'b00;

  if(clk==1)clock = clock+1;
 end   
 
always@(negedge clk) PC = pc_pred;



initial 




  $monitor("clk=%d,pc=%d,m_valM=%d,e_valE=%d,f_icode=%d,reg[3]=%d",clock,PC,m_valM,e_valE,f_icode,regmem3);

endmodule