data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/sync_wedge.sv
data/verilator_xmls/ae395201-ff20-4774-bd4d-f8951760d978.xml
module sync_wedge (
    input  logic clk_i,
    input  logic rst_ni,
    input  logic en_i,
    input  logic serial_i,
    output logic r_edge_o,
    output logic f_edge_o,
    output logic serial_o
);

   logic [2:0]  r_reg;

   assign serial_o =  r_reg[0];
   assign f_edge_o = (~r_reg[1]) & r_reg[0];
   assign r_edge_o =  r_reg[1] & (~r_reg[0]);

   always_ff @(posedge clk_i, negedge rst_ni) begin
        if (~rst_ni) begin
            r_reg <= 3'h0;
        end else begin
            if (en_i) begin
                r_reg <= {serial_i, r_reg[2:1]};
            end
        end
     end
endmodule
module sync_wedge (
    input  logic clk_i,
    input  logic rst_ni,
    input  logic en_i,
    input  logic serial_i,
    output logic r_edge_o,
    output logic f_edge_o,
    output logic serial_o
);


   logic [2:0]  r_reg;

   assign serial_o =  r_reg[0];
   assign f_edge_o = (~r_reg[1]) & r_reg[0];
   assign r_edge_o =  r_reg[1] & (~r_reg[0]);

   always_ff @(posedge clk_i, negedge rst_ni) begin
        if (~rst_ni) begin
            r_reg <= 3'h0;
        end else begin
            if (en_i) begin
                r_reg <= {serial_i, r_reg[2:1]};
            end
        end
     end
endmodule