data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module EXEMEM (clock, ewreg, em2reg, ewmem, ern, aluOut, eqb, 
               mwreg, mm2reg, mwmem, mrn, maluOut, mqb);
    input clock, ewreg, em2reg, ewmem;
    input [4:0] ern;
    input [31:0] aluOut, eqb;
    

    reg ewreg2, em2reg2, ewmem2;
    reg [4:0] ern2;
    reg [31:0] aluOut2, eqb2;
    
    output reg mwreg, mm2reg, mwmem;
    output reg [4:0] mrn;
    output reg [31:0] maluOut, mqb;
    
    always @ (posedge clock) begin
        ewreg2 <= ewreg;
        em2reg2 <= em2reg;
        ewmem2 <= ewmem;
        ern2 <= ern;
        aluOut2 <= aluOut;
        eqb2 <= eqb;
    end

    always @ (negedge clock) begin
        mwreg <= ewreg2;
        mm2reg <= em2reg;
        mwmem <= ewmem;
        mrn <= ern2;
        maluOut <= aluOut2;
        mqb <= eqb2;
    end
endmodule
module EXEMEM (clock, ewreg, em2reg, ewmem, ern, aluOut, eqb, 
               mwreg, mm2reg, mwmem, mrn, maluOut, mqb);

    input clock, ewreg, em2reg, ewmem;
    input [4:0] ern;
    input [31:0] aluOut, eqb;
    

    reg ewreg2, em2reg2, ewmem2;
    reg [4:0] ern2;
    reg [31:0] aluOut2, eqb2;
    
    output reg mwreg, mm2reg, mwmem;
    output reg [4:0] mrn;
    output reg [31:0] maluOut, mqb;
    
    always @ (posedge clock) begin
        ewreg2 <= ewreg;
        em2reg2 <= em2reg;
        ewmem2 <= ewmem;
        ern2 <= ern;
        aluOut2 <= aluOut;
        eqb2 <= eqb;
    end

    always @ (negedge clock) begin
        mwreg <= ewreg2;
        mm2reg <= em2reg;
        mwmem <= ewmem;
        mrn <= ern2;
        maluOut <= aluOut2;
        mqb <= eqb2;
    end
endmodule