data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:3: Cannot find include file: tcu_parameter.vh\n    `include "tcu_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.sv\n             tcu_parameter.vh\n             tcu_parameter.vh.v\n             tcu_parameter.vh.sv\n             obj_dir/tcu_parameter.vh\n             obj_dir/tcu_parameter.vh.v\n             obj_dir/tcu_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:4: Cannot find include file: noc_parameter.vh\n    ,`include "noc_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter  [0:0] RX_IF1_PRIO          = 1\'b0,         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:7: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter [31:0] RX_IF1_ADDR_START    = 32\'h0,        \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:8: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter [31:0] RX_IF1_ADDR_END      = 32\'hFFFFFFFF,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter  [0:0] RX_IF1_ONLY_HOMECHIP = 1\'b0,         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:10: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter  [0:0] RX_IF1_ONLY_MODE_2   = 1\'b0,         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:11: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter [31:0] RX_IF2_ADDR_START    = 32\'h0,        \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:12: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter [31:0] RX_IF2_ADDR_END      = 32\'hFFFFFFFF,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:13: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter  [0:0] RX_IF2_ONLY_MODE_2   = 1\'b0,         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter  [0:0] RX_IF2_ONLY_HOMECHIP = 1\'b0          \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:16: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          tcu_reset_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc1_tx_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc1_tx_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc1_tx_arq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_BSEL_SIZE-1:0] noc1_tx_bsel_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_src_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_src_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_trg_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_trg_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_MODE_SIZE-1:0] noc1_tx_mode_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_ADDR_SIZE-1:0] noc1_tx_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data0_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data1_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          noc1_tx_stall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           noc1_rx_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           noc1_rx_burst_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           noc1_rx_arq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_BSEL_SIZE-1:0] noc1_rx_bsel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_src_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_src_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_trg_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_trg_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:46: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_MODE_SIZE-1:0] noc1_rx_mode_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:47: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_ADDR_SIZE-1:0] noc1_rx_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data0_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:49: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data1_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:50: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                          noc1_rx_stall_i,    \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc2_tx_wrreq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc2_tx_burst_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:56: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc2_tx_arq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_BSEL_SIZE-1:0] noc2_tx_bsel_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:58: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_src_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:59: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_src_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:60: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_trg_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_noc_mux.v:61: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_trg_modid_i,\n    ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tcu_noc_mux #(
    `include "tcu_parameter.vh"
    ,`include "noc_parameter.vh"
    ,parameter [0:0] TX_IF1_PRIO          = 1'b0,
    parameter  [0:0] RX_IF1_PRIO          = 1'b0,
    parameter [31:0] RX_IF1_ADDR_START    = 32'h0,
    parameter [31:0] RX_IF1_ADDR_END      = 32'hFFFFFFFF,
    parameter  [0:0] RX_IF1_ONLY_HOMECHIP = 1'b0,
    parameter  [0:0] RX_IF1_ONLY_MODE_2   = 1'b0,
    parameter [31:0] RX_IF2_ADDR_START    = 32'h0,
    parameter [31:0] RX_IF2_ADDR_END      = 32'hFFFFFFFF,
    parameter  [0:0] RX_IF2_ONLY_MODE_2   = 1'b0,
    parameter  [0:0] RX_IF2_ONLY_HOMECHIP = 1'b0

)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,
    input  wire                          tcu_reset_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] home_chipid_i,



    input  wire                          noc1_tx_wrreq_i,
    input  wire                          noc1_tx_burst_i,
    input  wire                          noc1_tx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc1_tx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc1_tx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc1_tx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data1_i,
    output wire                          noc1_tx_stall_o,

    output reg                           noc1_rx_wrreq_o,
    output reg                           noc1_rx_burst_o,
    output reg                           noc1_rx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc1_rx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc1_rx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc1_rx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data1_o,
    input  wire                          noc1_rx_stall_i,



    input  wire                          noc2_tx_wrreq_i,
    input  wire                          noc2_tx_burst_i,
    input  wire                          noc2_tx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc2_tx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc2_tx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc2_tx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc2_tx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc2_tx_data1_i,
    output wire                          noc2_tx_stall_o,

    output reg                           noc2_rx_wrreq_o,
    output reg                           noc2_rx_burst_o,
    output reg                           noc2_rx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc2_rx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc2_rx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc2_rx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc2_rx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc2_rx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc2_rx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc2_rx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc2_rx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc2_rx_data1_o,
    input  wire                          noc2_rx_stall_i,



    output reg                           noc_out_tx_wrreq_o,
    output reg                           noc_out_tx_burst_o,
    output reg                           noc_out_tx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_out_tx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc_out_tx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc_out_tx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc_out_tx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc_out_tx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_out_tx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc_out_tx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_out_tx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_out_tx_data1_o,
    input  wire                          noc_out_tx_stall_i,

    input  wire                          noc_out_rx_wrreq_i,
    input  wire                          noc_out_rx_burst_i,
    input  wire                          noc_out_rx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_out_rx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_out_rx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_out_rx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_out_rx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_out_rx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_out_rx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_out_rx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_out_rx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_out_rx_data1_i,
    output reg                           noc_out_rx_stall_o,



    output wire [TCU_FLITCOUNT_SIZE-1:0] noc1_rx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc2_rx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc1_tx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc2_tx_flit_count_o
);

    localparam OUT_TX_IF0 = 2'h0;
    localparam OUT_TX_IF1 = 2'h1;
    localparam OUT_TX_IF2 = 2'h2;

    localparam OUT_RX_IF0 = 2'h0;
    localparam OUT_RX_IF1 = 2'h1;
    localparam OUT_RX_IF2 = 2'h2;


    reg  [1:0] r_tx_arbiter_result, rin_tx_arbiter_result;
    reg        tx_stall_if1, tx_stall_if2;
    reg        r_tx_burst_active, rin_tx_burst_active;

    reg  [1:0] r_rx_arbiter_result, rin_rx_arbiter_result;
    reg        r_rx_burst_active, rin_rx_burst_active;

    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc1_rx_flit_count, rin_noc1_rx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc2_rx_flit_count, rin_noc2_rx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc1_tx_flit_count, rin_noc1_tx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc2_tx_flit_count, rin_noc2_tx_flit_count;



    wire rx_mode_2 = (noc_out_rx_mode_i == MODE_WRITE_POSTED_2) ||
                        (noc_out_rx_mode_i == MODE_READ_REQ_2) ||
                        (noc_out_rx_mode_i == MODE_READ_RSP_2);


    wire rx_to_homechip = (noc_out_rx_trg_chipid_i == home_chipid_i);


    wire if1_rx_addr_valid = (noc_out_rx_addr_i >= RX_IF1_ADDR_START) && (noc_out_rx_addr_i <= RX_IF1_ADDR_END) && (!RX_IF1_ONLY_HOMECHIP || rx_to_homechip);
    wire if2_rx_addr_valid = (noc_out_rx_addr_i >= RX_IF2_ADDR_START) && (noc_out_rx_addr_i <= RX_IF2_ADDR_END) && (!RX_IF2_ONLY_HOMECHIP || rx_to_homechip);



    always @(posedge clk_i or negedge reset_n_i) begin
        if (!reset_n_i) begin
            r_tx_arbiter_result <= OUT_TX_IF0;
            r_tx_burst_active <= 1'b0;

            r_rx_arbiter_result <= OUT_RX_IF0;
            r_rx_burst_active <= 1'b0;

            r_noc1_rx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc2_rx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc1_tx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc2_tx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
        end
        else begin
            r_tx_arbiter_result <= rin_tx_arbiter_result;
            r_tx_burst_active <= rin_tx_burst_active;

            r_rx_arbiter_result <= rin_rx_arbiter_result;
            r_rx_burst_active <= rin_rx_burst_active;

            r_noc1_rx_flit_count <= rin_noc1_rx_flit_count;
            r_noc2_rx_flit_count <= rin_noc2_rx_flit_count;
            r_noc1_tx_flit_count <= rin_noc1_tx_flit_count;
            r_noc2_tx_flit_count <= rin_noc2_tx_flit_count;
        end
    end





    generate
    if (TX_IF1_PRIO) begin: TX_IF1

        always @* begin
            rin_tx_arbiter_result = r_tx_arbiter_result;
            tx_stall_if1 = 1'b0;
            tx_stall_if2 = 1'b0;


            if (!r_tx_burst_active) begin
                if (noc1_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF1;
                    tx_stall_if2 = 1'b1;
                end
                else if (noc2_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF2;
                end
                else begin
                    rin_tx_arbiter_result = OUT_TX_IF0;
                end
            end


            else if (r_tx_arbiter_result == OUT_TX_IF1) begin
                tx_stall_if2 = 1'b1;
            end
            else if (r_tx_arbiter_result == OUT_TX_IF2) begin
                tx_stall_if1 = 1'b1;
            end
        end

    end
    else begin: TX_IF2

        always @* begin
            rin_tx_arbiter_result = r_tx_arbiter_result;
            tx_stall_if1 = 1'b0;
            tx_stall_if2 = 1'b0;


            if (!r_tx_burst_active) begin
                if (noc2_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF2;
                    tx_stall_if1 = 1'b1;
                end
                else if (noc1_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF1;
                end
                else begin
                    rin_tx_arbiter_result = OUT_TX_IF0;
                end
            end


            else if (r_tx_arbiter_result == OUT_TX_IF1) begin
                tx_stall_if2 = 1'b1;
            end
            else if (r_tx_arbiter_result == OUT_TX_IF2) begin
                tx_stall_if1 = 1'b1;
            end
        end

    end
    endgenerate




    always @* begin
        rin_tx_burst_active = r_tx_burst_active;

        if (!noc_out_tx_stall_i && noc_out_tx_wrreq_o) begin
            if (noc_out_tx_burst_o) begin
                rin_tx_burst_active = 1'b1;
            end else begin
                rin_tx_burst_active = 1'b0;
            end
        end
    end



    always @* begin
        case(rin_tx_arbiter_result)
            OUT_TX_IF1: begin
                noc_out_tx_wrreq_o      = noc1_tx_wrreq_i;
                noc_out_tx_burst_o      = noc1_tx_burst_i;
                noc_out_tx_arq_o        = noc1_tx_arq_i;
                noc_out_tx_bsel_o       = noc1_tx_bsel_i;
                noc_out_tx_src_chipid_o = noc1_tx_src_chipid_i;
                noc_out_tx_src_modid_o  = noc1_tx_src_modid_i;
                noc_out_tx_trg_chipid_o = noc1_tx_trg_chipid_i;
                noc_out_tx_trg_modid_o  = noc1_tx_trg_modid_i;
                noc_out_tx_mode_o       = noc1_tx_mode_i;
                noc_out_tx_addr_o       = noc1_tx_addr_i;
                noc_out_tx_data0_o      = noc1_tx_data0_i;
                noc_out_tx_data1_o      = noc1_tx_data1_i;
            end

            OUT_TX_IF2: begin
                noc_out_tx_wrreq_o      = noc2_tx_wrreq_i;
                noc_out_tx_burst_o      = noc2_tx_burst_i;
                noc_out_tx_arq_o        = noc2_tx_arq_i;
                noc_out_tx_bsel_o       = noc2_tx_bsel_i;
                noc_out_tx_src_chipid_o = noc2_tx_src_chipid_i;
                noc_out_tx_src_modid_o  = noc2_tx_src_modid_i;
                noc_out_tx_trg_chipid_o = noc2_tx_trg_chipid_i;
                noc_out_tx_trg_modid_o  = noc2_tx_trg_modid_i;
                noc_out_tx_mode_o       = noc2_tx_mode_i;
                noc_out_tx_addr_o       = noc2_tx_addr_i;
                noc_out_tx_data0_o      = noc2_tx_data0_i;
                noc_out_tx_data1_o      = noc2_tx_data1_i;
            end

            default: begin
                noc_out_tx_wrreq_o      = 1'b0;
                noc_out_tx_burst_o      = 1'b0;
                noc_out_tx_arq_o        = 1'b0;
                noc_out_tx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc_out_tx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc_out_tx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc_out_tx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc_out_tx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc_out_tx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc_out_tx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc_out_tx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc_out_tx_data1_o      = {NOC_DATA_SIZE{1'b0}};
            end
        endcase
    end


    assign noc1_tx_stall_o = noc_out_tx_stall_i || tx_stall_if1;
    assign noc2_tx_stall_o = noc_out_tx_stall_i || tx_stall_if2;



    always @* begin
        rin_noc1_tx_flit_count = r_noc1_tx_flit_count;
        if (tcu_reset_i) begin
            rin_noc1_tx_flit_count = 0;
        end


        else if (noc1_tx_wrreq_i) begin
            rin_noc1_tx_flit_count = r_noc1_tx_flit_count + 1;
        end
    end

    always @* begin
        rin_noc2_tx_flit_count = r_noc2_tx_flit_count;
        if (tcu_reset_i) begin
            rin_noc2_tx_flit_count = 0;
        end


        else if (noc2_tx_wrreq_i) begin
            rin_noc2_tx_flit_count = r_noc2_tx_flit_count + 1;
        end
    end

    assign noc1_tx_flit_count_o = r_noc1_tx_flit_count;
    assign noc2_tx_flit_count_o = r_noc2_tx_flit_count;





    always @* begin
        rin_rx_arbiter_result = r_rx_arbiter_result;


        if (noc_out_rx_wrreq_i && !r_rx_burst_active) begin
            casez({rx_mode_2, if1_rx_addr_valid, if2_rx_addr_valid, RX_IF1_PRIO, RX_IF1_ONLY_MODE_2, RX_IF2_ONLY_MODE_2})

                6'b01??01: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b0?1?10: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b01?100: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b001100: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b0?1000: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b010000: rin_rx_arbiter_result = OUT_RX_IF1;


                6'b11?1??: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b1011??: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b1?10??: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b1100??: rin_rx_arbiter_result = OUT_RX_IF1;

                default: rin_rx_arbiter_result = OUT_RX_IF0;
            endcase
        end
    end



    always @* begin
        rin_rx_burst_active = r_rx_burst_active;

        if (noc_out_rx_wrreq_i && !noc1_rx_stall_i && !noc2_rx_stall_i) begin
            if (noc_out_rx_burst_i) begin
                rin_rx_burst_active = 1'b1;
            end else begin
                rin_rx_burst_active = 1'b0;
            end
        end
    end



    always @* begin
        case(rin_rx_arbiter_result)
            OUT_RX_IF1: begin
                noc1_rx_wrreq_o      = noc_out_rx_wrreq_i;
                noc1_rx_burst_o      = noc_out_rx_burst_i;
                noc1_rx_arq_o        = noc_out_rx_arq_i;
                noc1_rx_bsel_o       = noc_out_rx_bsel_i;
                noc1_rx_src_chipid_o = noc_out_rx_src_chipid_i;
                noc1_rx_src_modid_o  = noc_out_rx_src_modid_i;
                noc1_rx_trg_chipid_o = noc_out_rx_trg_chipid_i;
                noc1_rx_trg_modid_o  = noc_out_rx_trg_modid_i;
                noc1_rx_mode_o       = noc_out_rx_mode_i;
                noc1_rx_addr_o       = noc_out_rx_addr_i;
                noc1_rx_data0_o      = noc_out_rx_data0_i;
                noc1_rx_data1_o      = noc_out_rx_data1_i;

                noc2_rx_wrreq_o      = 1'b0;
                noc2_rx_burst_o      = 1'b0;
                noc2_rx_arq_o        = 1'b0;
                noc2_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc2_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc2_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc2_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc2_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc_out_rx_stall_o   = noc1_rx_stall_i;
            end

            OUT_RX_IF2: begin
                noc1_rx_wrreq_o      = 1'b0;
                noc1_rx_burst_o      = 1'b0;
                noc1_rx_arq_o        = 1'b0;
                noc1_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc1_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc1_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc1_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc1_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc2_rx_wrreq_o      = noc_out_rx_wrreq_i;
                noc2_rx_burst_o      = noc_out_rx_burst_i;
                noc2_rx_arq_o        = noc_out_rx_arq_i;
                noc2_rx_bsel_o       = noc_out_rx_bsel_i;
                noc2_rx_src_chipid_o = noc_out_rx_src_chipid_i;
                noc2_rx_src_modid_o  = noc_out_rx_src_modid_i;
                noc2_rx_trg_chipid_o = noc_out_rx_trg_chipid_i;
                noc2_rx_trg_modid_o  = noc_out_rx_trg_modid_i;
                noc2_rx_mode_o       = noc_out_rx_mode_i;
                noc2_rx_addr_o       = noc_out_rx_addr_i;
                noc2_rx_data0_o      = noc_out_rx_data0_i;
                noc2_rx_data1_o      = noc_out_rx_data1_i;

                noc_out_rx_stall_o   = noc2_rx_stall_i;
            end

            default: begin
                noc1_rx_wrreq_o      = 1'b0;
                noc1_rx_burst_o      = 1'b0;
                noc1_rx_arq_o        = 1'b0;
                noc1_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc1_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc1_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc1_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc1_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc2_rx_wrreq_o      = 1'b0;
                noc2_rx_burst_o      = 1'b0;
                noc2_rx_arq_o        = 1'b0;
                noc2_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc2_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc2_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc2_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc2_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc_out_rx_stall_o   = 1'b1;
            end
        endcase
    end


    always @* begin
        rin_noc1_rx_flit_count = r_noc1_rx_flit_count;
        if (tcu_reset_i) begin
            rin_noc1_rx_flit_count = 0;
        end
        else if (noc1_rx_wrreq_o && !noc1_rx_stall_i) begin
            rin_noc1_rx_flit_count = r_noc1_rx_flit_count + 1;
        end
    end

    always @* begin
        rin_noc2_rx_flit_count = r_noc2_rx_flit_count;
        if (tcu_reset_i) begin
            rin_noc2_rx_flit_count = 0;
        end
        else if (noc2_rx_wrreq_o && !noc2_rx_stall_i) begin
            rin_noc2_rx_flit_count = r_noc2_rx_flit_count + 1;
        end
    end

    assign noc1_rx_flit_count_o = r_noc1_rx_flit_count;
    assign noc2_rx_flit_count_o = r_noc2_rx_flit_count;


endmodule
module tcu_noc_mux #(
    `include "tcu_parameter.vh"
    ,`include "noc_parameter.vh"
    ,parameter [0:0] TX_IF1_PRIO          = 1'b0,
    parameter  [0:0] RX_IF1_PRIO          = 1'b0,
    parameter [31:0] RX_IF1_ADDR_START    = 32'h0,
    parameter [31:0] RX_IF1_ADDR_END      = 32'hFFFFFFFF,
    parameter  [0:0] RX_IF1_ONLY_HOMECHIP = 1'b0,
    parameter  [0:0] RX_IF1_ONLY_MODE_2   = 1'b0,
    parameter [31:0] RX_IF2_ADDR_START    = 32'h0,
    parameter [31:0] RX_IF2_ADDR_END      = 32'hFFFFFFFF,
    parameter  [0:0] RX_IF2_ONLY_MODE_2   = 1'b0,
    parameter  [0:0] RX_IF2_ONLY_HOMECHIP = 1'b0

)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,
    input  wire                          tcu_reset_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] home_chipid_i,



    input  wire                          noc1_tx_wrreq_i,
    input  wire                          noc1_tx_burst_i,
    input  wire                          noc1_tx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc1_tx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc1_tx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc1_tx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc1_tx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc1_tx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc1_tx_data1_i,
    output wire                          noc1_tx_stall_o,

    output reg                           noc1_rx_wrreq_o,
    output reg                           noc1_rx_burst_o,
    output reg                           noc1_rx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc1_rx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc1_rx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc1_rx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc1_rx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc1_rx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc1_rx_data1_o,
    input  wire                          noc1_rx_stall_i,



    input  wire                          noc2_tx_wrreq_i,
    input  wire                          noc2_tx_burst_i,
    input  wire                          noc2_tx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc2_tx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc2_tx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc2_tx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc2_tx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc2_tx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc2_tx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc2_tx_data1_i,
    output wire                          noc2_tx_stall_o,

    output reg                           noc2_rx_wrreq_o,
    output reg                           noc2_rx_burst_o,
    output reg                           noc2_rx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc2_rx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc2_rx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc2_rx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc2_rx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc2_rx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc2_rx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc2_rx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc2_rx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc2_rx_data1_o,
    input  wire                          noc2_rx_stall_i,



    output reg                           noc_out_tx_wrreq_o,
    output reg                           noc_out_tx_burst_o,
    output reg                           noc_out_tx_arq_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_out_tx_bsel_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc_out_tx_src_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc_out_tx_src_modid_o,
    output reg     [NOC_CHIPID_SIZE-1:0] noc_out_tx_trg_chipid_o,
    output reg      [NOC_MODID_SIZE-1:0] noc_out_tx_trg_modid_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_out_tx_mode_o,
    output reg       [NOC_ADDR_SIZE-1:0] noc_out_tx_addr_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_out_tx_data0_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_out_tx_data1_o,
    input  wire                          noc_out_tx_stall_i,

    input  wire                          noc_out_rx_wrreq_i,
    input  wire                          noc_out_rx_burst_i,
    input  wire                          noc_out_rx_arq_i,
    input  wire      [NOC_BSEL_SIZE-1:0] noc_out_rx_bsel_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_out_rx_src_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_out_rx_src_modid_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_out_rx_trg_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_out_rx_trg_modid_i,
    input  wire      [NOC_MODE_SIZE-1:0] noc_out_rx_mode_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_out_rx_addr_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_out_rx_data0_i,
    input  wire      [NOC_DATA_SIZE-1:0] noc_out_rx_data1_i,
    output reg                           noc_out_rx_stall_o,



    output wire [TCU_FLITCOUNT_SIZE-1:0] noc1_rx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc2_rx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc1_tx_flit_count_o,
    output wire [TCU_FLITCOUNT_SIZE-1:0] noc2_tx_flit_count_o
);


    localparam OUT_TX_IF0 = 2'h0;
    localparam OUT_TX_IF1 = 2'h1;
    localparam OUT_TX_IF2 = 2'h2;

    localparam OUT_RX_IF0 = 2'h0;
    localparam OUT_RX_IF1 = 2'h1;
    localparam OUT_RX_IF2 = 2'h2;


    reg  [1:0] r_tx_arbiter_result, rin_tx_arbiter_result;
    reg        tx_stall_if1, tx_stall_if2;
    reg        r_tx_burst_active, rin_tx_burst_active;

    reg  [1:0] r_rx_arbiter_result, rin_rx_arbiter_result;
    reg        r_rx_burst_active, rin_rx_burst_active;

    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc1_rx_flit_count, rin_noc1_rx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc2_rx_flit_count, rin_noc2_rx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc1_tx_flit_count, rin_noc1_tx_flit_count;
    reg [TCU_FLITCOUNT_SIZE-1:0] r_noc2_tx_flit_count, rin_noc2_tx_flit_count;



    wire rx_mode_2 = (noc_out_rx_mode_i == MODE_WRITE_POSTED_2) ||
                        (noc_out_rx_mode_i == MODE_READ_REQ_2) ||
                        (noc_out_rx_mode_i == MODE_READ_RSP_2);


    wire rx_to_homechip = (noc_out_rx_trg_chipid_i == home_chipid_i);


    wire if1_rx_addr_valid = (noc_out_rx_addr_i >= RX_IF1_ADDR_START) && (noc_out_rx_addr_i <= RX_IF1_ADDR_END) && (!RX_IF1_ONLY_HOMECHIP || rx_to_homechip);
    wire if2_rx_addr_valid = (noc_out_rx_addr_i >= RX_IF2_ADDR_START) && (noc_out_rx_addr_i <= RX_IF2_ADDR_END) && (!RX_IF2_ONLY_HOMECHIP || rx_to_homechip);



    always @(posedge clk_i or negedge reset_n_i) begin
        if (!reset_n_i) begin
            r_tx_arbiter_result <= OUT_TX_IF0;
            r_tx_burst_active <= 1'b0;

            r_rx_arbiter_result <= OUT_RX_IF0;
            r_rx_burst_active <= 1'b0;

            r_noc1_rx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc2_rx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc1_tx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
            r_noc2_tx_flit_count <= {TCU_FLITCOUNT_SIZE{1'b0}};
        end
        else begin
            r_tx_arbiter_result <= rin_tx_arbiter_result;
            r_tx_burst_active <= rin_tx_burst_active;

            r_rx_arbiter_result <= rin_rx_arbiter_result;
            r_rx_burst_active <= rin_rx_burst_active;

            r_noc1_rx_flit_count <= rin_noc1_rx_flit_count;
            r_noc2_rx_flit_count <= rin_noc2_rx_flit_count;
            r_noc1_tx_flit_count <= rin_noc1_tx_flit_count;
            r_noc2_tx_flit_count <= rin_noc2_tx_flit_count;
        end
    end





    generate
    if (TX_IF1_PRIO) begin: TX_IF1

        always @* begin
            rin_tx_arbiter_result = r_tx_arbiter_result;
            tx_stall_if1 = 1'b0;
            tx_stall_if2 = 1'b0;


            if (!r_tx_burst_active) begin
                if (noc1_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF1;
                    tx_stall_if2 = 1'b1;
                end
                else if (noc2_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF2;
                end
                else begin
                    rin_tx_arbiter_result = OUT_TX_IF0;
                end
            end


            else if (r_tx_arbiter_result == OUT_TX_IF1) begin
                tx_stall_if2 = 1'b1;
            end
            else if (r_tx_arbiter_result == OUT_TX_IF2) begin
                tx_stall_if1 = 1'b1;
            end
        end

    end
    else begin: TX_IF2

        always @* begin
            rin_tx_arbiter_result = r_tx_arbiter_result;
            tx_stall_if1 = 1'b0;
            tx_stall_if2 = 1'b0;


            if (!r_tx_burst_active) begin
                if (noc2_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF2;
                    tx_stall_if1 = 1'b1;
                end
                else if (noc1_tx_wrreq_i) begin
                    rin_tx_arbiter_result = OUT_TX_IF1;
                end
                else begin
                    rin_tx_arbiter_result = OUT_TX_IF0;
                end
            end


            else if (r_tx_arbiter_result == OUT_TX_IF1) begin
                tx_stall_if2 = 1'b1;
            end
            else if (r_tx_arbiter_result == OUT_TX_IF2) begin
                tx_stall_if1 = 1'b1;
            end
        end

    end
    endgenerate




    always @* begin
        rin_tx_burst_active = r_tx_burst_active;

        if (!noc_out_tx_stall_i && noc_out_tx_wrreq_o) begin
            if (noc_out_tx_burst_o) begin
                rin_tx_burst_active = 1'b1;
            end else begin
                rin_tx_burst_active = 1'b0;
            end
        end
    end



    always @* begin
        case(rin_tx_arbiter_result)
            OUT_TX_IF1: begin
                noc_out_tx_wrreq_o      = noc1_tx_wrreq_i;
                noc_out_tx_burst_o      = noc1_tx_burst_i;
                noc_out_tx_arq_o        = noc1_tx_arq_i;
                noc_out_tx_bsel_o       = noc1_tx_bsel_i;
                noc_out_tx_src_chipid_o = noc1_tx_src_chipid_i;
                noc_out_tx_src_modid_o  = noc1_tx_src_modid_i;
                noc_out_tx_trg_chipid_o = noc1_tx_trg_chipid_i;
                noc_out_tx_trg_modid_o  = noc1_tx_trg_modid_i;
                noc_out_tx_mode_o       = noc1_tx_mode_i;
                noc_out_tx_addr_o       = noc1_tx_addr_i;
                noc_out_tx_data0_o      = noc1_tx_data0_i;
                noc_out_tx_data1_o      = noc1_tx_data1_i;
            end

            OUT_TX_IF2: begin
                noc_out_tx_wrreq_o      = noc2_tx_wrreq_i;
                noc_out_tx_burst_o      = noc2_tx_burst_i;
                noc_out_tx_arq_o        = noc2_tx_arq_i;
                noc_out_tx_bsel_o       = noc2_tx_bsel_i;
                noc_out_tx_src_chipid_o = noc2_tx_src_chipid_i;
                noc_out_tx_src_modid_o  = noc2_tx_src_modid_i;
                noc_out_tx_trg_chipid_o = noc2_tx_trg_chipid_i;
                noc_out_tx_trg_modid_o  = noc2_tx_trg_modid_i;
                noc_out_tx_mode_o       = noc2_tx_mode_i;
                noc_out_tx_addr_o       = noc2_tx_addr_i;
                noc_out_tx_data0_o      = noc2_tx_data0_i;
                noc_out_tx_data1_o      = noc2_tx_data1_i;
            end

            default: begin
                noc_out_tx_wrreq_o      = 1'b0;
                noc_out_tx_burst_o      = 1'b0;
                noc_out_tx_arq_o        = 1'b0;
                noc_out_tx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc_out_tx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc_out_tx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc_out_tx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc_out_tx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc_out_tx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc_out_tx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc_out_tx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc_out_tx_data1_o      = {NOC_DATA_SIZE{1'b0}};
            end
        endcase
    end


    assign noc1_tx_stall_o = noc_out_tx_stall_i || tx_stall_if1;
    assign noc2_tx_stall_o = noc_out_tx_stall_i || tx_stall_if2;



    always @* begin
        rin_noc1_tx_flit_count = r_noc1_tx_flit_count;
        if (tcu_reset_i) begin
            rin_noc1_tx_flit_count = 0;
        end


        else if (noc1_tx_wrreq_i) begin
            rin_noc1_tx_flit_count = r_noc1_tx_flit_count + 1;
        end
    end

    always @* begin
        rin_noc2_tx_flit_count = r_noc2_tx_flit_count;
        if (tcu_reset_i) begin
            rin_noc2_tx_flit_count = 0;
        end


        else if (noc2_tx_wrreq_i) begin
            rin_noc2_tx_flit_count = r_noc2_tx_flit_count + 1;
        end
    end

    assign noc1_tx_flit_count_o = r_noc1_tx_flit_count;
    assign noc2_tx_flit_count_o = r_noc2_tx_flit_count;





    always @* begin
        rin_rx_arbiter_result = r_rx_arbiter_result;


        if (noc_out_rx_wrreq_i && !r_rx_burst_active) begin
            casez({rx_mode_2, if1_rx_addr_valid, if2_rx_addr_valid, RX_IF1_PRIO, RX_IF1_ONLY_MODE_2, RX_IF2_ONLY_MODE_2})

                6'b01??01: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b0?1?10: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b01?100: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b001100: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b0?1000: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b010000: rin_rx_arbiter_result = OUT_RX_IF1;


                6'b11?1??: rin_rx_arbiter_result = OUT_RX_IF1;
                6'b1011??: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b1?10??: rin_rx_arbiter_result = OUT_RX_IF2;
                6'b1100??: rin_rx_arbiter_result = OUT_RX_IF1;

                default: rin_rx_arbiter_result = OUT_RX_IF0;
            endcase
        end
    end



    always @* begin
        rin_rx_burst_active = r_rx_burst_active;

        if (noc_out_rx_wrreq_i && !noc1_rx_stall_i && !noc2_rx_stall_i) begin
            if (noc_out_rx_burst_i) begin
                rin_rx_burst_active = 1'b1;
            end else begin
                rin_rx_burst_active = 1'b0;
            end
        end
    end



    always @* begin
        case(rin_rx_arbiter_result)
            OUT_RX_IF1: begin
                noc1_rx_wrreq_o      = noc_out_rx_wrreq_i;
                noc1_rx_burst_o      = noc_out_rx_burst_i;
                noc1_rx_arq_o        = noc_out_rx_arq_i;
                noc1_rx_bsel_o       = noc_out_rx_bsel_i;
                noc1_rx_src_chipid_o = noc_out_rx_src_chipid_i;
                noc1_rx_src_modid_o  = noc_out_rx_src_modid_i;
                noc1_rx_trg_chipid_o = noc_out_rx_trg_chipid_i;
                noc1_rx_trg_modid_o  = noc_out_rx_trg_modid_i;
                noc1_rx_mode_o       = noc_out_rx_mode_i;
                noc1_rx_addr_o       = noc_out_rx_addr_i;
                noc1_rx_data0_o      = noc_out_rx_data0_i;
                noc1_rx_data1_o      = noc_out_rx_data1_i;

                noc2_rx_wrreq_o      = 1'b0;
                noc2_rx_burst_o      = 1'b0;
                noc2_rx_arq_o        = 1'b0;
                noc2_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc2_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc2_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc2_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc2_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc_out_rx_stall_o   = noc1_rx_stall_i;
            end

            OUT_RX_IF2: begin
                noc1_rx_wrreq_o      = 1'b0;
                noc1_rx_burst_o      = 1'b0;
                noc1_rx_arq_o        = 1'b0;
                noc1_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc1_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc1_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc1_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc1_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc2_rx_wrreq_o      = noc_out_rx_wrreq_i;
                noc2_rx_burst_o      = noc_out_rx_burst_i;
                noc2_rx_arq_o        = noc_out_rx_arq_i;
                noc2_rx_bsel_o       = noc_out_rx_bsel_i;
                noc2_rx_src_chipid_o = noc_out_rx_src_chipid_i;
                noc2_rx_src_modid_o  = noc_out_rx_src_modid_i;
                noc2_rx_trg_chipid_o = noc_out_rx_trg_chipid_i;
                noc2_rx_trg_modid_o  = noc_out_rx_trg_modid_i;
                noc2_rx_mode_o       = noc_out_rx_mode_i;
                noc2_rx_addr_o       = noc_out_rx_addr_i;
                noc2_rx_data0_o      = noc_out_rx_data0_i;
                noc2_rx_data1_o      = noc_out_rx_data1_i;

                noc_out_rx_stall_o   = noc2_rx_stall_i;
            end

            default: begin
                noc1_rx_wrreq_o      = 1'b0;
                noc1_rx_burst_o      = 1'b0;
                noc1_rx_arq_o        = 1'b0;
                noc1_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc1_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc1_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc1_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc1_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc1_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc1_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc2_rx_wrreq_o      = 1'b0;
                noc2_rx_burst_o      = 1'b0;
                noc2_rx_arq_o        = 1'b0;
                noc2_rx_bsel_o       = {NOC_BSEL_SIZE{1'b0}};
                noc2_rx_src_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_src_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_trg_chipid_o = {NOC_CHIPID_SIZE{1'b0}};
                noc2_rx_trg_modid_o  = {NOC_MODID_SIZE{1'b0}};
                noc2_rx_mode_o       = {NOC_MODE_SIZE{1'b0}};
                noc2_rx_addr_o       = {NOC_ADDR_SIZE{1'b0}};
                noc2_rx_data0_o      = {NOC_DATA_SIZE{1'b0}};
                noc2_rx_data1_o      = {NOC_DATA_SIZE{1'b0}};

                noc_out_rx_stall_o   = 1'b1;
            end
        endcase
    end


    always @* begin
        rin_noc1_rx_flit_count = r_noc1_rx_flit_count;
        if (tcu_reset_i) begin
            rin_noc1_rx_flit_count = 0;
        end
        else if (noc1_rx_wrreq_o && !noc1_rx_stall_i) begin
            rin_noc1_rx_flit_count = r_noc1_rx_flit_count + 1;
        end
    end

    always @* begin
        rin_noc2_rx_flit_count = r_noc2_rx_flit_count;
        if (tcu_reset_i) begin
            rin_noc2_rx_flit_count = 0;
        end
        else if (noc2_rx_wrreq_o && !noc2_rx_stall_i) begin
            rin_noc2_rx_flit_count = r_noc2_rx_flit_count + 1;
        end
    end

    assign noc1_rx_flit_count_o = r_noc1_rx_flit_count;
    assign noc2_rx_flit_count_o = r_noc2_rx_flit_count;


endmodule