data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:140: Cannot find file containing module: \'cam\'\n   cam \n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/cam.sv\n             cam\n             cam.v\n             cam.sv\n             obj_dir/cam\n             obj_dir/cam.v\n             obj_dir/cam.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:160: Cannot find file containing module: \'cam\'\n   cam #(\n   ^~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:222: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:226: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n       cam_wr_addr_learn_next = reset_count;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:231: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:237: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:241: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              cam_wr_addr_learn_next = reset_count;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/mac_cam_lut.v:247: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                                : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module mac_cam_lut
    #(parameter NUM_OUTPUT_QUEUES = 8,
      parameter LUT_DEPTH_BITS = 4,
      parameter LUT_DEPTH = 2**LUT_DEPTH_BITS,
      parameter DEFAULT_MISS_OUTPUT_PORTS = 8'h55)

   (
     input [47:0]                       dst_mac,
     input [47:0]                       src_mac,
     input [NUM_OUTPUT_QUEUES-1:0]      src_port,
     input                              lookup_req,
     output[NUM_OUTPUT_QUEUES-1:0]      dst_ports,
  

     output reg                         lookup_done,
     output reg				lut_miss,
     output reg				lut_hit,   


     input                              clk,
     input                              reset

     );


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam RESET            = 1;
   localparam IDLE             = 2;
   localparam LATCH_DST_LOOKUP = 4;



   wire [NUM_OUTPUT_QUEUES-1:0]          rd_oq;
   wire [47:0]				 rd_mac;

   wire                                  cam_busy;
   wire                                  cam_match;
   wire [LUT_DEPTH_BITS-1:0]             cam_match_addr;
   reg  [47:0]                           cam_cmp_din;
    
   reg  [47:0]                           cam_din, cam_din_next;
   reg                                   cam_we, cam_we_next;
   reg  [LUT_DEPTH_BITS-1:0]             cam_wr_addr, cam_wr_addr_next;

   wire                                  cam_busy_learn;
   wire                                  cam_match_learn;
   wire [LUT_DEPTH_BITS-1:0]             cam_match_addr_learn;
   reg  [47:0]                           cam_cmp_din_learn;

   reg  [47:0]                           cam_din_learn, cam_din_learn_next;
   reg                                   cam_we_learn, cam_we_learn_next;
   reg  [LUT_DEPTH_BITS-1:0]             cam_wr_addr_learn, cam_wr_addr_learn_next;


   reg  [NUM_OUTPUT_QUEUES-1:0]          src_port_latched;
   reg  [47:0]                           src_mac_latched;
   reg                                   latch_src;

   reg  [2:0]                            lookup_state, lookup_state_next;

   reg [LUT_DEPTH_BITS-1:0]              lut_rd_addr, lut_wr_addr, lut_wr_addr_next;
   reg                                   lut_wr_en, lut_wr_en_next;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut_wr_data, lut_wr_data_next;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut_rd_data;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut[LUT_DEPTH-1:0];

   reg                                   reset_count_inc;
   reg [LUT_DEPTH_BITS:0]                reset_count;

   reg                                   lut_miss_next;
   reg    				 lut_hit_next;
   reg					 lookup_done_next;

   reg [LUT_DEPTH_BITS-1:0]		 pointer_add_cam, pointer_add_cam_next;





   cam 
#(
   .C_TCAM_ADDR_WIDTH   (LUT_DEPTH_BITS),
   .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH_BITS),
   .C_TCAM_DATA_WIDTH   (48) 
)
mac_cam
     (  
      (* box_type = "user_black_box" *)

      .BUSY                             (cam_busy),
      .MATCH                            (cam_match),
      .MATCH_ADDR                       (cam_match_addr[LUT_DEPTH_BITS-1:0]),

      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din),
      .DIN                              (cam_din[47:0]),
      .WE                               (cam_we),
      .ADDR_WR                          (cam_wr_addr[LUT_DEPTH_BITS-1:0]));

   cam #(
   .C_TCAM_ADDR_WIDTH   (LUT_DEPTH_BITS), 
   .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH_BITS),
   .C_TCAM_DATA_WIDTH   (48) 
    )
mac_cam_learn
     (
      (* box_type = "user_black_box" *)
      .BUSY                             (cam_busy_learn),
      .MATCH                            (cam_match_learn),
      .MATCH_ADDR                       (cam_match_addr_learn[LUT_DEPTH_BITS-1:0]),
      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din_learn),
      .DIN                              (cam_din_learn[47:0]),
      .WE                               (cam_we_learn),
      .ADDR_WR                          (cam_wr_addr_learn[LUT_DEPTH_BITS-1:0]));







   assign rd_oq = lut_rd_data[NUM_OUTPUT_QUEUES+47:48];
   assign rd_mac = lut_rd_data[47:0];


   assign dst_ports = (lut_miss) ? (DEFAULT_MISS_OUTPUT_PORTS & ~src_port_latched)
                                           : (rd_oq & ~src_port_latched);


 
   always @(*) begin
      cam_wr_addr_next = pointer_add_cam;
      cam_din_next     = src_mac_latched;
      cam_we_next      = 0;
      cam_cmp_din      = 0;
    
      cam_wr_addr_learn_next = pointer_add_cam;
      cam_din_learn_next     = src_mac_latched;
      cam_we_learn_next      = 0;
      cam_cmp_din_learn      = 0;

      lut_rd_addr      = cam_match_addr;
      lut_wr_en_next   = 1'b0;
      lut_wr_data_next = {src_port_latched, src_mac_latched};      
      lut_wr_addr_next = cam_match_addr_learn;

      reset_count_inc  = 0;
      latch_src        = 0;
      lookup_done_next      = 0;
      lut_miss_next	       = 0;
      lut_hit_next	       = 0;
      pointer_add_cam_next = pointer_add_cam;

      lookup_state_next = lookup_state;

      case(lookup_state)

        RESET: begin
           if( !cam_we_learn && !cam_busy_learn && !cam_we && !cam_busy && reset_count < LUT_DEPTH-1) begin
              cam_wr_addr_next = reset_count;
              cam_we_next = 1;
              cam_din_next = 0;

	      cam_wr_addr_learn_next = reset_count;
              cam_we_learn_next = 1;
              cam_din_learn_next = 0;
	
              reset_count_inc = 1;
              lut_wr_addr_next = reset_count;
              lut_wr_data_next = 0;
              lut_wr_en_next = 1;
           end

           else if( !cam_we_learn && !cam_busy_learn && !cam_we && !cam_busy && reset_count == LUT_DEPTH-1) begin
              cam_wr_addr_next = reset_count;
              cam_we_next = 1;
              cam_din_next = ~48'h0;

              cam_wr_addr_learn_next = reset_count;
              cam_we_learn_next = 1;
              cam_din_learn_next = ~48'h0;

              reset_count_inc = 1;

              lut_wr_addr_next = reset_count;
              lut_wr_data_next = {DEFAULT_MISS_OUTPUT_PORTS, ~48'h0};
	      lut_wr_en_next = 1;
           end
           else if(!cam_we && !cam_busy) begin
              lookup_state_next = IDLE;
           end
        end

        IDLE: begin
           cam_cmp_din = dst_mac;
	   cam_cmp_din_learn = src_mac;
           if(lookup_req) begin
              lookup_state_next = LATCH_DST_LOOKUP;
              latch_src = 1;
           end
        end

        LATCH_DST_LOOKUP: begin

            lookup_done_next = 1;
            if(!cam_match)
		lut_miss_next = 1;
	    else
		lut_hit_next = 1;

	    if(cam_match_learn)
	    	lut_wr_en_next = 1;
	    else begin
		if(!cam_busy && !cam_busy_learn) begin
			lut_wr_addr_next = pointer_add_cam;
                	lut_wr_en_next = 1;
                	cam_we_next = 1;
			cam_we_learn_next = 1;
                	if(pointer_add_cam==LUT_DEPTH-2)
                        	pointer_add_cam_next = 0;
                	else
                        	pointer_add_cam_next = pointer_add_cam + 1;
            	end
	    end
            lookup_state_next = IDLE;
          
        end

        default: begin end
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         lut_rd_data       <= 0;
         reset_count       <= 0;
         src_port_latched  <= 0;
         src_mac_latched   <= 0;
         lookup_done       <= 0;
         lut_miss          <= 0;
         lut_hit	   <= 0;

         cam_wr_addr       <= 0;
         cam_din           <= 0;
         cam_we            <= 0;

         cam_wr_addr_learn       <= 0;
         cam_din_learn           <= 0;
         cam_we_learn            <= 0;

         lut_wr_en         <= 0;
         lut_wr_data       <= 0;
         lut_wr_addr       <= 0;

         pointer_add_cam   <= 0;

         lookup_state      <= RESET;
      end
      else begin
         reset_count       <= reset_count_inc ? reset_count + 1 : reset_count;
         src_port_latched  <= latch_src ? src_port : src_port_latched;
         src_mac_latched   <= latch_src ? src_mac : src_mac_latched;
         lookup_done       <= lookup_done_next;
         lut_miss          <= lut_miss_next;
         lut_hit	   <= lut_hit_next;

         pointer_add_cam   <= pointer_add_cam_next;

         lut_rd_data       <= lut[lut_rd_addr];
         if(lut_wr_en) begin
            lut[lut_wr_addr] <= lut_wr_data;
         end

         cam_wr_addr       <= cam_wr_addr_next;
         cam_din           <= cam_din_next;
         cam_we            <= cam_we_next;

         cam_wr_addr_learn       <= cam_wr_addr_learn_next;
         cam_din_learn           <= cam_din_learn_next;
         cam_we_learn            <= cam_we_learn_next;

         lut_wr_en         <= lut_wr_en_next;
         lut_wr_data       <= lut_wr_data_next;
         lut_wr_addr       <= lut_wr_addr_next;

         lookup_state      <= lookup_state_next;
      end
   end

endmodule
module mac_cam_lut
    #(parameter NUM_OUTPUT_QUEUES = 8,
      parameter LUT_DEPTH_BITS = 4,
      parameter LUT_DEPTH = 2**LUT_DEPTH_BITS,
      parameter DEFAULT_MISS_OUTPUT_PORTS = 8'h55)

   (
     input [47:0]                       dst_mac,
     input [47:0]                       src_mac,
     input [NUM_OUTPUT_QUEUES-1:0]      src_port,
     input                              lookup_req,
     output[NUM_OUTPUT_QUEUES-1:0]      dst_ports,
  

     output reg                         lookup_done,
     output reg				lut_miss,
     output reg				lut_hit,   


     input                              clk,
     input                              reset

     );



   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam RESET            = 1;
   localparam IDLE             = 2;
   localparam LATCH_DST_LOOKUP = 4;



   wire [NUM_OUTPUT_QUEUES-1:0]          rd_oq;
   wire [47:0]				 rd_mac;

   wire                                  cam_busy;
   wire                                  cam_match;
   wire [LUT_DEPTH_BITS-1:0]             cam_match_addr;
   reg  [47:0]                           cam_cmp_din;
    
   reg  [47:0]                           cam_din, cam_din_next;
   reg                                   cam_we, cam_we_next;
   reg  [LUT_DEPTH_BITS-1:0]             cam_wr_addr, cam_wr_addr_next;

   wire                                  cam_busy_learn;
   wire                                  cam_match_learn;
   wire [LUT_DEPTH_BITS-1:0]             cam_match_addr_learn;
   reg  [47:0]                           cam_cmp_din_learn;

   reg  [47:0]                           cam_din_learn, cam_din_learn_next;
   reg                                   cam_we_learn, cam_we_learn_next;
   reg  [LUT_DEPTH_BITS-1:0]             cam_wr_addr_learn, cam_wr_addr_learn_next;


   reg  [NUM_OUTPUT_QUEUES-1:0]          src_port_latched;
   reg  [47:0]                           src_mac_latched;
   reg                                   latch_src;

   reg  [2:0]                            lookup_state, lookup_state_next;

   reg [LUT_DEPTH_BITS-1:0]              lut_rd_addr, lut_wr_addr, lut_wr_addr_next;
   reg                                   lut_wr_en, lut_wr_en_next;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut_wr_data, lut_wr_data_next;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut_rd_data;
   reg [NUM_OUTPUT_QUEUES+47:0]          lut[LUT_DEPTH-1:0];

   reg                                   reset_count_inc;
   reg [LUT_DEPTH_BITS:0]                reset_count;

   reg                                   lut_miss_next;
   reg    				 lut_hit_next;
   reg					 lookup_done_next;

   reg [LUT_DEPTH_BITS-1:0]		 pointer_add_cam, pointer_add_cam_next;





   cam 
#(
   .C_TCAM_ADDR_WIDTH   (LUT_DEPTH_BITS),
   .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH_BITS),
   .C_TCAM_DATA_WIDTH   (48) 
)
mac_cam
     (  
      (* box_type = "user_black_box" *)

      .BUSY                             (cam_busy),
      .MATCH                            (cam_match),
      .MATCH_ADDR                       (cam_match_addr[LUT_DEPTH_BITS-1:0]),

      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din),
      .DIN                              (cam_din[47:0]),
      .WE                               (cam_we),
      .ADDR_WR                          (cam_wr_addr[LUT_DEPTH_BITS-1:0]));

   cam #(
   .C_TCAM_ADDR_WIDTH   (LUT_DEPTH_BITS), 
   .C_TCAM_MATCH_ADDR_WIDTH (LUT_DEPTH_BITS),
   .C_TCAM_DATA_WIDTH   (48) 
    )
mac_cam_learn
     (
      (* box_type = "user_black_box" *)
      .BUSY                             (cam_busy_learn),
      .MATCH                            (cam_match_learn),
      .MATCH_ADDR                       (cam_match_addr_learn[LUT_DEPTH_BITS-1:0]),
      .CLK                              (clk),
      .CMP_DIN                          (cam_cmp_din_learn),
      .DIN                              (cam_din_learn[47:0]),
      .WE                               (cam_we_learn),
      .ADDR_WR                          (cam_wr_addr_learn[LUT_DEPTH_BITS-1:0]));







   assign rd_oq = lut_rd_data[NUM_OUTPUT_QUEUES+47:48];
   assign rd_mac = lut_rd_data[47:0];


   assign dst_ports = (lut_miss) ? (DEFAULT_MISS_OUTPUT_PORTS & ~src_port_latched)
                                           : (rd_oq & ~src_port_latched);


 
   always @(*) begin
      cam_wr_addr_next = pointer_add_cam;
      cam_din_next     = src_mac_latched;
      cam_we_next      = 0;
      cam_cmp_din      = 0;
    
      cam_wr_addr_learn_next = pointer_add_cam;
      cam_din_learn_next     = src_mac_latched;
      cam_we_learn_next      = 0;
      cam_cmp_din_learn      = 0;

      lut_rd_addr      = cam_match_addr;
      lut_wr_en_next   = 1'b0;
      lut_wr_data_next = {src_port_latched, src_mac_latched};      
      lut_wr_addr_next = cam_match_addr_learn;

      reset_count_inc  = 0;
      latch_src        = 0;
      lookup_done_next      = 0;
      lut_miss_next	       = 0;
      lut_hit_next	       = 0;
      pointer_add_cam_next = pointer_add_cam;

      lookup_state_next = lookup_state;

      case(lookup_state)

        RESET: begin
           if( !cam_we_learn && !cam_busy_learn && !cam_we && !cam_busy && reset_count < LUT_DEPTH-1) begin
              cam_wr_addr_next = reset_count;
              cam_we_next = 1;
              cam_din_next = 0;

	      cam_wr_addr_learn_next = reset_count;
              cam_we_learn_next = 1;
              cam_din_learn_next = 0;
	
              reset_count_inc = 1;
              lut_wr_addr_next = reset_count;
              lut_wr_data_next = 0;
              lut_wr_en_next = 1;
           end

           else if( !cam_we_learn && !cam_busy_learn && !cam_we && !cam_busy && reset_count == LUT_DEPTH-1) begin
              cam_wr_addr_next = reset_count;
              cam_we_next = 1;
              cam_din_next = ~48'h0;

              cam_wr_addr_learn_next = reset_count;
              cam_we_learn_next = 1;
              cam_din_learn_next = ~48'h0;

              reset_count_inc = 1;

              lut_wr_addr_next = reset_count;
              lut_wr_data_next = {DEFAULT_MISS_OUTPUT_PORTS, ~48'h0};
	      lut_wr_en_next = 1;
           end
           else if(!cam_we && !cam_busy) begin
              lookup_state_next = IDLE;
           end
        end

        IDLE: begin
           cam_cmp_din = dst_mac;
	   cam_cmp_din_learn = src_mac;
           if(lookup_req) begin
              lookup_state_next = LATCH_DST_LOOKUP;
              latch_src = 1;
           end
        end

        LATCH_DST_LOOKUP: begin

            lookup_done_next = 1;
            if(!cam_match)
		lut_miss_next = 1;
	    else
		lut_hit_next = 1;

	    if(cam_match_learn)
	    	lut_wr_en_next = 1;
	    else begin
		if(!cam_busy && !cam_busy_learn) begin
			lut_wr_addr_next = pointer_add_cam;
                	lut_wr_en_next = 1;
                	cam_we_next = 1;
			cam_we_learn_next = 1;
                	if(pointer_add_cam==LUT_DEPTH-2)
                        	pointer_add_cam_next = 0;
                	else
                        	pointer_add_cam_next = pointer_add_cam + 1;
            	end
	    end
            lookup_state_next = IDLE;
          
        end

        default: begin end
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         lut_rd_data       <= 0;
         reset_count       <= 0;
         src_port_latched  <= 0;
         src_mac_latched   <= 0;
         lookup_done       <= 0;
         lut_miss          <= 0;
         lut_hit	   <= 0;

         cam_wr_addr       <= 0;
         cam_din           <= 0;
         cam_we            <= 0;

         cam_wr_addr_learn       <= 0;
         cam_din_learn           <= 0;
         cam_we_learn            <= 0;

         lut_wr_en         <= 0;
         lut_wr_data       <= 0;
         lut_wr_addr       <= 0;

         pointer_add_cam   <= 0;

         lookup_state      <= RESET;
      end
      else begin
         reset_count       <= reset_count_inc ? reset_count + 1 : reset_count;
         src_port_latched  <= latch_src ? src_port : src_port_latched;
         src_mac_latched   <= latch_src ? src_mac : src_mac_latched;
         lookup_done       <= lookup_done_next;
         lut_miss          <= lut_miss_next;
         lut_hit	   <= lut_hit_next;

         pointer_add_cam   <= pointer_add_cam_next;

         lut_rd_data       <= lut[lut_rd_addr];
         if(lut_wr_en) begin
            lut[lut_wr_addr] <= lut_wr_data;
         end

         cam_wr_addr       <= cam_wr_addr_next;
         cam_din           <= cam_din_next;
         cam_we            <= cam_we_next;

         cam_wr_addr_learn       <= cam_wr_addr_learn_next;
         cam_din_learn           <= cam_din_learn_next;
         cam_we_learn            <= cam_we_learn_next;

         lut_wr_en         <= lut_wr_en_next;
         lut_wr_data       <= lut_wr_data_next;
         lut_wr_addr       <= lut_wr_addr_next;

         lookup_state      <= lookup_state_next;
      end
   end

endmodule