data/full_repos/permissive/492140037/CPU/设计文件/executs32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/executs32.v:84: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LT generates 1 bits.\n                                                                                    : ... In instance executs32\n            ALU_FinalResult = Exe_code[0] == 1 ? Ainput < Binput : $signed(Ainput) < $signed(Binput);\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/executs32.v:84: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s LTS generates 1 bits.\n                                                                                    : ... In instance executs32\n            ALU_FinalResult = Exe_code[0] == 1 ? Ainput < Binput : $signed(Ainput) < $signed(Binput);\n                                               ^\n%Error: Exiting due to 2 warning(s)\n'
module executs32(Read_data_1,Read_data_2,Sign_extend,Function_opcode,Exe_opcode,ALUOp,
                 Shamt,ALUSrc,I_format,Zero,Jr,Sftmd,ALU_Result,Addr_Result,PC_plus_4
                 );
    input[31:0]  Read_data_1;
    input[31:0]  Read_data_2;
    input[31:0]  Sign_extend;
    input[5:0]   Function_opcode;
    input[5:0]   Exe_opcode;
    input[1:0]   ALUOp;
    input[4:0]   Shamt;
    input  		 Sftmd;
    input        ALUSrc;
    input        I_format;
    input        Jr;
    output       Zero;
    output[31:0] ALU_Result;
    output[31:0] Addr_Result;
    input[31:0]  PC_plus_4;

    wire[31:0] Ainput, Binput;
    wire[3:0] Exe_code;
    wire[2:0] ALU_ctl;
    wire[2:0] Sftm;
    reg[31:0] Shift_Result;
    reg[31:0] ALU_output_mux;
    wire[32:0] Branch_Addr;
    reg[31:0] ALU_FinalResult;

    assign Zero = (ALU_output_mux == 32'h0000_0000) ? 1'b1 : 1'b0;
    assign ALU_Result = ALU_FinalResult;
    assign Addr_Result = Branch_Addr[31:0];



    assign Branch_Addr = PC_plus_4 + Sign_extend;

    assign Ainput = Read_data_1;
    assign Binput = ALUSrc ? Sign_extend : Read_data_2;

    assign Exe_code = I_format ? {1'b0, Exe_opcode[2:0]}: Function_opcode[3:0];
    assign ALU_ctl[0] = (Exe_code[0] | Exe_code[3]) & ALUOp[1];
    assign ALU_ctl[1] = ((!Exe_code[2]) | (!ALUOp[1]));
    assign ALU_ctl[2] = (Exe_code[1] & ALUOp[1]) | ALUOp[0];

    assign Sftm = Function_opcode[2:0];

    always @(ALU_ctl or Ainput or Binput) begin
        case (ALU_ctl)
            3'b000: ALU_output_mux = Ainput & Binput;
            3'b001: ALU_output_mux = Ainput | Binput;
            3'b010: ALU_output_mux = $signed(Ainput) + $signed(Binput);
            3'b011: ALU_output_mux = Ainput + Binput;
            3'b100: ALU_output_mux = Ainput ^ Binput;
            3'b101: ALU_output_mux = ~(Ainput | Binput);
            3'b110: ALU_output_mux = $signed(Ainput) - $signed(Binput);
            3'b111: ALU_output_mux = Ainput - Binput;
            default: ALU_output_mux = 32'h0000_0000;
        endcase
    end

    always @(*) begin
        if (Sftmd) begin
            case(Sftm)
                3'b000: Shift_Result = Binput << Shamt;
                3'b010: Shift_Result = Binput >> Shamt;
                3'b100: Shift_Result = Binput << Ainput;
                3'b110: Shift_Result = Binput >> Ainput;
                3'b011: Shift_Result = $signed(Binput) >>> Shamt;
                3'b111: Shift_Result = $signed(Binput) >>> Ainput;
                default: Shift_Result = Binput;
            endcase
        end
        else begin
            Shift_Result = Binput;
        end
    end

    always @(*) begin

        if ((ALU_ctl == 3'b111 && Exe_code[3] == 1) || (ALU_ctl[2:1] == 2'b11 && I_format == 1'b1)) begin

            ALU_FinalResult = Exe_code[0] == 1 ? Ainput < Binput : $signed(Ainput) < $signed(Binput);
        end

        else if (ALU_ctl == 3'b101 && I_format == 1'b1) begin

            ALU_FinalResult = Sign_extend[31:0];
        end

        else if (Sftmd) begin
            ALU_FinalResult = Shift_Result;
        end
        else begin
            ALU_FinalResult = ALU_output_mux;
        end
    end

endmodule
module executs32(Read_data_1,Read_data_2,Sign_extend,Function_opcode,Exe_opcode,ALUOp,
                 Shamt,ALUSrc,I_format,Zero,Jr,Sftmd,ALU_Result,Addr_Result,PC_plus_4
                 );

    input[31:0]  Read_data_1;
    input[31:0]  Read_data_2;
    input[31:0]  Sign_extend;
    input[5:0]   Function_opcode;
    input[5:0]   Exe_opcode;
    input[1:0]   ALUOp;
    input[4:0]   Shamt;
    input  		 Sftmd;
    input        ALUSrc;
    input        I_format;
    input        Jr;
    output       Zero;
    output[31:0] ALU_Result;
    output[31:0] Addr_Result;
    input[31:0]  PC_plus_4;

    wire[31:0] Ainput, Binput;
    wire[3:0] Exe_code;
    wire[2:0] ALU_ctl;
    wire[2:0] Sftm;
    reg[31:0] Shift_Result;
    reg[31:0] ALU_output_mux;
    wire[32:0] Branch_Addr;
    reg[31:0] ALU_FinalResult;

    assign Zero = (ALU_output_mux == 32'h0000_0000) ? 1'b1 : 1'b0;
    assign ALU_Result = ALU_FinalResult;
    assign Addr_Result = Branch_Addr[31:0];



    assign Branch_Addr = PC_plus_4 + Sign_extend;

    assign Ainput = Read_data_1;
    assign Binput = ALUSrc ? Sign_extend : Read_data_2;

    assign Exe_code = I_format ? {1'b0, Exe_opcode[2:0]}: Function_opcode[3:0];
    assign ALU_ctl[0] = (Exe_code[0] | Exe_code[3]) & ALUOp[1];
    assign ALU_ctl[1] = ((!Exe_code[2]) | (!ALUOp[1]));
    assign ALU_ctl[2] = (Exe_code[1] & ALUOp[1]) | ALUOp[0];

    assign Sftm = Function_opcode[2:0];

    always @(ALU_ctl or Ainput or Binput) begin
        case (ALU_ctl)
            3'b000: ALU_output_mux = Ainput & Binput;
            3'b001: ALU_output_mux = Ainput | Binput;
            3'b010: ALU_output_mux = $signed(Ainput) + $signed(Binput);
            3'b011: ALU_output_mux = Ainput + Binput;
            3'b100: ALU_output_mux = Ainput ^ Binput;
            3'b101: ALU_output_mux = ~(Ainput | Binput);
            3'b110: ALU_output_mux = $signed(Ainput) - $signed(Binput);
            3'b111: ALU_output_mux = Ainput - Binput;
            default: ALU_output_mux = 32'h0000_0000;
        endcase
    end

    always @(*) begin
        if (Sftmd) begin
            case(Sftm)
                3'b000: Shift_Result = Binput << Shamt;
                3'b010: Shift_Result = Binput >> Shamt;
                3'b100: Shift_Result = Binput << Ainput;
                3'b110: Shift_Result = Binput >> Ainput;
                3'b011: Shift_Result = $signed(Binput) >>> Shamt;
                3'b111: Shift_Result = $signed(Binput) >>> Ainput;
                default: Shift_Result = Binput;
            endcase
        end
        else begin
            Shift_Result = Binput;
        end
    end

    always @(*) begin

        if ((ALU_ctl == 3'b111 && Exe_code[3] == 1) || (ALU_ctl[2:1] == 2'b11 && I_format == 1'b1)) begin

            ALU_FinalResult = Exe_code[0] == 1 ? Ainput < Binput : $signed(Ainput) < $signed(Binput);
        end

        else if (ALU_ctl == 3'b101 && I_format == 1'b1) begin

            ALU_FinalResult = Sign_extend[31:0];
        end

        else if (Sftmd) begin
            ALU_FinalResult = Shift_Result;
        end
        else begin
            ALU_FinalResult = ALU_output_mux;
        end
    end

endmodule