data/full_repos/permissive/530731752/src/tinycordic.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:79: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance tinycordic\n                    reg_x_next <= reg_x + reg_y[5:2];\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:80: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance tinycordic\n                    reg_y_next <= reg_y - reg_x[5:2];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:83: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance tinycordic\n                    reg_x_next <= reg_x - reg_y[5:2];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:84: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance tinycordic\n                    reg_y_next <= reg_y + reg_x[5:2];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:90: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                        : ... In instance tinycordic\n                    reg_x_next <= reg_x + reg_y[5:3];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:91: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                        : ... In instance tinycordic\n                    reg_y_next <= reg_y - reg_x[5:3];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:94: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                        : ... In instance tinycordic\n                    reg_x_next <= reg_x - reg_y[5:3];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:95: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                        : ... In instance tinycordic\n                    reg_y_next <= reg_y + reg_x[5:3];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:101: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance tinycordic\n                    reg_x_next <= reg_x + reg_y[5:4];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:102: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance tinycordic\n                    reg_y_next <= reg_y - reg_x[5:4];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:105: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance tinycordic\n                    reg_x_next <= reg_x - reg_y[5:4];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:106: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance tinycordic\n                    reg_y_next <= reg_y + reg_x[5:4];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:112: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tinycordic\n                    reg_x_next <= reg_x + reg_y[5];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:113: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tinycordic\n                    reg_y_next <= reg_y - reg_x[5];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:116: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tinycordic\n                    reg_x_next <= reg_x - reg_y[5];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:117: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tinycordic\n                    reg_y_next <= reg_y + reg_x[5];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:179: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_out\' generates 1 bits.\n                                                                         : ... In instance tinycordic\n    assign io_out[5:0] = data_out;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/530731752/src/tinycordic.v:181: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 6 bits.\n                                                                         : ... In instance tinycordic\n    assign data_out = (done) ? (clk) ? reg_x : reg_y : 0;\n                    ^\n%Error: Exiting due to 18 warning(s)\n'
module tinycordic (
    input wire [1023:0] read_x, read_y, read_z, real_ans_x, real_ans_y, inp_angle,
    input wire [7:0] io_in,
    output wire [7:0] io_out
    );






    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [5:0] z0 = io_in[7:2];


    reg [5:0]x0;
    reg [5:0]angle[5:0];
    always @(posedge clk) begin
        x0 <= 6'd19;
        angle[0] <= 6'd16;
        angle[1] <= 6'd9;
        angle[2] <= 6'd5;
        angle[3] <= 6'd2;
        angle[4] <= 6'd1;
        angle[5] <= 6'd1;
    end


    reg [5:0] reg_x, reg_y, reg_x_next, reg_y_next, reg_z, reg_z_next;
    reg en;
    always @(posedge clk) begin
        if (reset) begin
            reg_x <= x0;
            reg_y <= 0;
            reg_z <= z0;
        end else if (en) begin
            reg_x <= reg_x_next;
            reg_y <= reg_y_next;
            reg_z <= reg_z_next;
        end
    end


    wire d;
    assign d = reg_z[5];
    always @(*) begin
        case (i)
            3'd0: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y;
                    reg_y_next <= reg_y - reg_x;
                    reg_z_next <= reg_z + angle[0];
                end else begin
                    reg_x_next <= reg_x - reg_y;
                    reg_y_next <= reg_y + reg_x;
                    reg_z_next <= reg_z - angle[0];
                end
            end
            3'd1: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:1];
                    reg_y_next <= reg_y - reg_x[5:1];
                    reg_z_next <= reg_z + angle[1];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:1];
                    reg_y_next <= reg_y + reg_x[5:1];
                    reg_z_next <= reg_z - angle[1];
                end
            end
            3'd2: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:2];
                    reg_y_next <= reg_y - reg_x[5:2];
                    reg_z_next <= reg_z + angle[2];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:2];
                    reg_y_next <= reg_y + reg_x[5:2];
                    reg_z_next <= reg_z - angle[2];
                end
            end
            3'd3: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:3];
                    reg_y_next <= reg_y - reg_x[5:3];
                    reg_z_next <= reg_z + angle[3];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:3];
                    reg_y_next <= reg_y + reg_x[5:3];
                    reg_z_next <= reg_z - angle[3];
                end
            end
            3'd4: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:4];
                    reg_y_next <= reg_y - reg_x[5:4];
                    reg_z_next <= reg_z + angle[4];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:4];
                    reg_y_next <= reg_y + reg_x[5:4];
                    reg_z_next <= reg_z - angle[4];
                end
            end
            3'd5: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5];
                    reg_y_next <= reg_y - reg_x[5];
                    reg_z_next <= reg_z + angle[5];
                end else begin
                    reg_x_next <= reg_x - reg_y[5];
                    reg_y_next <= reg_y + reg_x[5];
                    reg_z_next <= reg_z - angle[5];
                end
            end
            default: begin
                reg_x_next <= 6'bx;
                reg_y_next <= 6'bx;
                reg_z_next <= 6'bx;
            end
        endcase    
    end



    reg [1:0] state;
    `define RESET 2'b0
    `define CALC 2'd1
    `define DONE 2'd2
    reg [2:0]i;
    reg done;
    always @(posedge clk) begin
        case (state)
            `RESET: begin
                done <= 0;
                i <= 0;
                
                if (!reset) begin
                    state <= `CALC;
                    en <= 1;
                end
                    
            end
            `CALC: begin
                if ( i < 5) begin
                    i <= i+1;
                    if (i == 4)
                        en <= 0;
                end
                    
                else begin
                    state <= `DONE;
                    
                end
            end
            `DONE: begin
                done <= 1;
                if (reset) 
                    state <= `RESET;
            end
            default: begin
                state <= 0;
            end

        endcase
    end


    assign io_out[7] = done;
    wire x_yb;
    assign x_yb = clk;
    assign io_out[6] = x_yb;
    wire data_out;
    assign io_out[5:0] = data_out;

    assign data_out = (done) ? (clk) ? reg_x : reg_y : 0;



    

    `ifdef COCOTB_SIM

    initial begin
    $dumpfile ("tinycordic.vcd");
    $dumpvars (0, tinycordic);
    #1;
    end
    `endif



endmodule
module tinycordic (
    input wire [1023:0] read_x, read_y, read_z, real_ans_x, real_ans_y, inp_angle,
    input wire [7:0] io_in,
    output wire [7:0] io_out
    );







    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [5:0] z0 = io_in[7:2];


    reg [5:0]x0;
    reg [5:0]angle[5:0];
    always @(posedge clk) begin
        x0 <= 6'd19;
        angle[0] <= 6'd16;
        angle[1] <= 6'd9;
        angle[2] <= 6'd5;
        angle[3] <= 6'd2;
        angle[4] <= 6'd1;
        angle[5] <= 6'd1;
    end


    reg [5:0] reg_x, reg_y, reg_x_next, reg_y_next, reg_z, reg_z_next;
    reg en;
    always @(posedge clk) begin
        if (reset) begin
            reg_x <= x0;
            reg_y <= 0;
            reg_z <= z0;
        end else if (en) begin
            reg_x <= reg_x_next;
            reg_y <= reg_y_next;
            reg_z <= reg_z_next;
        end
    end


    wire d;
    assign d = reg_z[5];
    always @(*) begin
        case (i)
            3'd0: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y;
                    reg_y_next <= reg_y - reg_x;
                    reg_z_next <= reg_z + angle[0];
                end else begin
                    reg_x_next <= reg_x - reg_y;
                    reg_y_next <= reg_y + reg_x;
                    reg_z_next <= reg_z - angle[0];
                end
            end
            3'd1: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:1];
                    reg_y_next <= reg_y - reg_x[5:1];
                    reg_z_next <= reg_z + angle[1];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:1];
                    reg_y_next <= reg_y + reg_x[5:1];
                    reg_z_next <= reg_z - angle[1];
                end
            end
            3'd2: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:2];
                    reg_y_next <= reg_y - reg_x[5:2];
                    reg_z_next <= reg_z + angle[2];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:2];
                    reg_y_next <= reg_y + reg_x[5:2];
                    reg_z_next <= reg_z - angle[2];
                end
            end
            3'd3: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:3];
                    reg_y_next <= reg_y - reg_x[5:3];
                    reg_z_next <= reg_z + angle[3];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:3];
                    reg_y_next <= reg_y + reg_x[5:3];
                    reg_z_next <= reg_z - angle[3];
                end
            end
            3'd4: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5:4];
                    reg_y_next <= reg_y - reg_x[5:4];
                    reg_z_next <= reg_z + angle[4];
                end else begin
                    reg_x_next <= reg_x - reg_y[5:4];
                    reg_y_next <= reg_y + reg_x[5:4];
                    reg_z_next <= reg_z - angle[4];
                end
            end
            3'd5: begin
                if (d) begin
                    reg_x_next <= reg_x + reg_y[5];
                    reg_y_next <= reg_y - reg_x[5];
                    reg_z_next <= reg_z + angle[5];
                end else begin
                    reg_x_next <= reg_x - reg_y[5];
                    reg_y_next <= reg_y + reg_x[5];
                    reg_z_next <= reg_z - angle[5];
                end
            end
            default: begin
                reg_x_next <= 6'bx;
                reg_y_next <= 6'bx;
                reg_z_next <= 6'bx;
            end
        endcase    
    end



    reg [1:0] state;
    `define RESET 2'b0
    `define CALC 2'd1
    `define DONE 2'd2
    reg [2:0]i;
    reg done;
    always @(posedge clk) begin
        case (state)
            `RESET: begin
                done <= 0;
                i <= 0;
                
                if (!reset) begin
                    state <= `CALC;
                    en <= 1;
                end
                    
            end
            `CALC: begin
                if ( i < 5) begin
                    i <= i+1;
                    if (i == 4)
                        en <= 0;
                end
                    
                else begin
                    state <= `DONE;
                    
                end
            end
            `DONE: begin
                done <= 1;
                if (reset) 
                    state <= `RESET;
            end
            default: begin
                state <= 0;
            end

        endcase
    end


    assign io_out[7] = done;
    wire x_yb;
    assign x_yb = clk;
    assign io_out[6] = x_yb;
    wire data_out;
    assign io_out[5:0] = data_out;

    assign data_out = (done) ? (clk) ? reg_x : reg_y : 0;



    

    `ifdef COCOTB_SIM

    initial begin
    $dumpfile ("tinycordic.vcd");
    $dumpvars (0, tinycordic);
    #1;
    end
    `endif



endmodule