data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v
1: b'%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:7: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:8: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter HOST_IP        = {8\'d192, 8\'d168, 8\'d42, 8\'d25},\n    ^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter HOST_PORT       = 16\'d1800,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:10: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FPGA_IP_BASE    = {8\'d192, 8\'d168, 8\'d42, 8\'d240},\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:11: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FPGA_PORT       = 16\'d1800,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:12: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FPGA_MAC_BASE   = 48\'h080028_030405,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:13: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter GATEWAY_IP_ADDR = {8\'d192, 8\'d168, 8\'d42, 8\'d1},\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter SUBNET_MASK     = {8\'d255, 8\'d255, 8\'d255, 8\'d0},\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:15: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter HOME_MODID      = {NOC_MODID_SIZE{1\'b0}},\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:16: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter SIMULATION      = 0\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:17: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  reset_eth_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  sgmii_rxn,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  sgmii_rxp,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  sgmii_txn,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  sgmii_txp,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  sgmii_clk_n,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  sgmii_clk_p,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  mdio_mdc,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                  mdio_mdio_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  mdio_mdio_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  mdio_mdio_t,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:44: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                           [15:0] eth_status_vector_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  eth_system_reset_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire            [NOC_CHIPID_SIZE-1:0] home_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire            [NOC_CHIPID_SIZE-1:0] host_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                  phy_reset_n,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:51: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                            [3:0] gpio_dip_sw_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:52: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:71: syntax error, unexpected assign\nassign eth_status_vector_o = eth_status_vector_s;\n^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_domain.v:80: syntax error, unexpected IDENTIFIER\nutil_reset_sync i_util_reset_sync_ref (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module ethernet_domain #(
    `include "noc_parameter.vh"
    ,parameter HOST_IP        = {8'd192, 8'd168, 8'd42, 8'd25},
    parameter HOST_PORT       = 16'd1800,
    parameter FPGA_IP_BASE    = {8'd192, 8'd168, 8'd42, 8'd240},
    parameter FPGA_PORT       = 16'd1800,
    parameter FPGA_MAC_BASE   = 48'h080028_030405,
    parameter GATEWAY_IP_ADDR = {8'd192, 8'd168, 8'd42, 8'd1},
    parameter SUBNET_MASK     = {8'd255, 8'd255, 8'd255, 8'd0},
    parameter HOME_MODID      = {NOC_MODID_SIZE{1'b0}},
    parameter SIMULATION      = 0
)
(
    input  wire                                  clk_eth_i,
    input  wire                                  reset_eth_n_i,
    

    input  wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,
    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,
    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,
    output wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,
    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,
    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,
    

    input  wire                                  sgmii_rxn,
    input  wire                                  sgmii_rxp,
    output wire                                  sgmii_txn,
    output wire                                  sgmii_txp,
    input  wire                                  sgmii_clk_n,
    input  wire                                  sgmii_clk_p,


    output wire                                  mdio_mdc,
    input  wire                                  mdio_mdio_i,
    output wire                                  mdio_mdio_o,
    output wire                                  mdio_mdio_t,

    output wire                           [15:0] eth_status_vector_o,
    output wire                                  eth_system_reset_o,
    output wire	           [NOC_CHIPID_SIZE-1:0] home_chipid_o,
    output wire	           [NOC_CHIPID_SIZE-1:0] host_chipid_o,

    output wire                                  phy_reset_n,

    input  wire                            [3:0] gpio_dip_sw_i
);



wire        gmii_clk;
wire        gmii_rst;
wire        gmii_clk_en;
wire  [7:0] gmii_txd;
wire        gmii_tx_en;
wire        gmii_tx_er;
wire  [7:0] gmii_rxd;
wire        gmii_rx_dv;
wire        gmii_rx_er;


wire [31:0] fpga_ip_addr;
wire [47:0] fpga_mac_addr;

wire [15:0] eth_status_vector_s;
assign eth_status_vector_o = eth_status_vector_s;

wire [31:0] eth_config_vector_s;
wire        eth_an_complete_s;
wire  [1:0] eth_pll_lock_s;

wire reset_eth_sync_n_s;


util_reset_sync i_util_reset_sync_ref (
    .clk_i(clk_eth_i),
    .reset_q_i(reset_eth_n_i),
    .scan_mode_i(1'b0),
    .sync_reset_q_o(reset_eth_sync_n_s)
);


ethernet_fpga_config #(
    .FPGA_IP_BASE           (FPGA_IP_BASE),
    .FPGA_MAC_BASE          (FPGA_MAC_BASE)
) i_ethernet_fpga_config (
    .switches_i             (gpio_dip_sw_i),
    .fpga_ip_addr_o         (fpga_ip_addr),
    .fpga_mac_addr_o        (fpga_mac_addr),
    .home_chipid_o          (home_chipid_o)
);



ethernet_pcs_pma_xcvu9p_wrap #(
    .SIMULATION          (SIMULATION)
) i_ethernet_pcs_pma_xcvu9p_wrap (
    .rst_eth_n_i         (reset_eth_sync_n_s),


    .sgmii_rxn           (sgmii_rxn),
	.sgmii_rxp           (sgmii_rxp),
	.sgmii_txn           (sgmii_txn),
	.sgmii_txp           (sgmii_txp),
    .sgmii_clk_n         (sgmii_clk_n),
	.sgmii_clk_p         (sgmii_clk_p),
	.phy_rst_n           (phy_reset_n),


    .gmii_clk            (gmii_clk),
    .gmii_rst            (gmii_rst),
    .gmii_clk_en         (gmii_clk_en),
    .gmii_txd            (gmii_txd),
    .gmii_tx_en          (gmii_tx_en),
    .gmii_tx_er          (gmii_tx_er),
    .gmii_rxd            (gmii_rxd),
    .gmii_rx_dv          (gmii_rx_dv),
    .gmii_rx_er          (gmii_rx_er),

    .eth_status_vector_o (eth_status_vector_s),
    .eth_config_vector_i (eth_config_vector_s),
    .eth_an_complete_o   (eth_an_complete_s),
    .eth_pll_lock_o      (eth_pll_lock_s)
);


ethernet_mdio_wrap #(
    .SIMULATION         (SIMULATION)
) i_ethernet_mdio_wrap (
    .clk_eth_i          (clk_eth_i),
    .rst_eth_n_i        (reset_eth_sync_n_s),
    .mdio_mdc           (mdio_mdc),
    .mdio_mdio_i        (mdio_mdio_i),
    .mdio_mdio_o        (mdio_mdio_o),
    .mdio_mdio_t        (mdio_mdio_t)
);


ethernet_wrap #(
    .HOST_IP                (HOST_IP),
    .HOST_PORT              (HOST_PORT),
    .FPGA_IP_BASE           (FPGA_IP_BASE),
    .FPGA_PORT              (FPGA_PORT),
    .GATEWAY_IP_ADDR        (GATEWAY_IP_ADDR),
    .SUBNET_MASK            (SUBNET_MASK),
    .HOME_MODID             (HOME_MODID)
) i_ethernet_wrap (
    .clk_eth_i              (clk_eth_i),
    .rst_eth_n_i            (reset_eth_sync_n_s),

    .noc_fifo_in_data_i     (noc_fifo_in_data_i),
    .noc_fifo_in_raddr_o    (noc_fifo_in_raddr_o),
    .noc_fifo_in_waddr_i    (noc_fifo_in_waddr_i),
    .noc_fifo_out_data_o    (noc_fifo_out_data_o),
    .noc_fifo_out_raddr_i   (noc_fifo_out_raddr_i),
    .noc_fifo_out_waddr_o   (noc_fifo_out_waddr_o),


    .gmii_clk               (gmii_clk),
    .gmii_rst               (gmii_rst),
    .gmii_clk_en            (gmii_clk_en),
    .gmii_txd               (gmii_txd),
    .gmii_tx_en             (gmii_tx_en),
    .gmii_tx_er             (gmii_tx_er),
    .gmii_rxd               (gmii_rxd),
    .gmii_rx_dv             (gmii_rx_dv),
    .gmii_rx_er             (gmii_rx_er),

    .eth_status_vector_i    (eth_status_vector_s),
    .eth_config_vector_o    (eth_config_vector_s),
    .eth_an_complete_i      (eth_an_complete_s),
    .eth_pll_lock_i         (eth_pll_lock_s),
    .eth_system_reset_o     (eth_system_reset_o),
    .fpga_ip_addr_i         (fpga_ip_addr),
    .fpga_mac_addr_i        (fpga_mac_addr),
    .home_chipid_i          (home_chipid_o),
    .host_chipid_o          (host_chipid_o)
);



endmodule
module ethernet_domain #(
    `include "noc_parameter.vh"
    ,parameter HOST_IP        = {8'd192, 8'd168, 8'd42, 8'd25},
    parameter HOST_PORT       = 16'd1800,
    parameter FPGA_IP_BASE    = {8'd192, 8'd168, 8'd42, 8'd240},
    parameter FPGA_PORT       = 16'd1800,
    parameter FPGA_MAC_BASE   = 48'h080028_030405,
    parameter GATEWAY_IP_ADDR = {8'd192, 8'd168, 8'd42, 8'd1},
    parameter SUBNET_MASK     = {8'd255, 8'd255, 8'd255, 8'd0},
    parameter HOME_MODID      = {NOC_MODID_SIZE{1'b0}},
    parameter SIMULATION      = 0
)
(
    input  wire                                  clk_eth_i,
    input  wire                                  reset_eth_n_i,
    

    input  wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,
    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,
    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,
    output wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,
    input  wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,
    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,
    

    input  wire                                  sgmii_rxn,
    input  wire                                  sgmii_rxp,
    output wire                                  sgmii_txn,
    output wire                                  sgmii_txp,
    input  wire                                  sgmii_clk_n,
    input  wire                                  sgmii_clk_p,


    output wire                                  mdio_mdc,
    input  wire                                  mdio_mdio_i,
    output wire                                  mdio_mdio_o,
    output wire                                  mdio_mdio_t,

    output wire                           [15:0] eth_status_vector_o,
    output wire                                  eth_system_reset_o,
    output wire	           [NOC_CHIPID_SIZE-1:0] home_chipid_o,
    output wire	           [NOC_CHIPID_SIZE-1:0] host_chipid_o,

    output wire                                  phy_reset_n,

    input  wire                            [3:0] gpio_dip_sw_i
);




wire        gmii_clk;
wire        gmii_rst;
wire        gmii_clk_en;
wire  [7:0] gmii_txd;
wire        gmii_tx_en;
wire        gmii_tx_er;
wire  [7:0] gmii_rxd;
wire        gmii_rx_dv;
wire        gmii_rx_er;


wire [31:0] fpga_ip_addr;
wire [47:0] fpga_mac_addr;

wire [15:0] eth_status_vector_s;
assign eth_status_vector_o = eth_status_vector_s;

wire [31:0] eth_config_vector_s;
wire        eth_an_complete_s;
wire  [1:0] eth_pll_lock_s;

wire reset_eth_sync_n_s;


util_reset_sync i_util_reset_sync_ref (
    .clk_i(clk_eth_i),
    .reset_q_i(reset_eth_n_i),
    .scan_mode_i(1'b0),
    .sync_reset_q_o(reset_eth_sync_n_s)
);


ethernet_fpga_config #(
    .FPGA_IP_BASE           (FPGA_IP_BASE),
    .FPGA_MAC_BASE          (FPGA_MAC_BASE)
) i_ethernet_fpga_config (
    .switches_i             (gpio_dip_sw_i),
    .fpga_ip_addr_o         (fpga_ip_addr),
    .fpga_mac_addr_o        (fpga_mac_addr),
    .home_chipid_o          (home_chipid_o)
);



ethernet_pcs_pma_xcvu9p_wrap #(
    .SIMULATION          (SIMULATION)
) i_ethernet_pcs_pma_xcvu9p_wrap (
    .rst_eth_n_i         (reset_eth_sync_n_s),


    .sgmii_rxn           (sgmii_rxn),
	.sgmii_rxp           (sgmii_rxp),
	.sgmii_txn           (sgmii_txn),
	.sgmii_txp           (sgmii_txp),
    .sgmii_clk_n         (sgmii_clk_n),
	.sgmii_clk_p         (sgmii_clk_p),
	.phy_rst_n           (phy_reset_n),


    .gmii_clk            (gmii_clk),
    .gmii_rst            (gmii_rst),
    .gmii_clk_en         (gmii_clk_en),
    .gmii_txd            (gmii_txd),
    .gmii_tx_en          (gmii_tx_en),
    .gmii_tx_er          (gmii_tx_er),
    .gmii_rxd            (gmii_rxd),
    .gmii_rx_dv          (gmii_rx_dv),
    .gmii_rx_er          (gmii_rx_er),

    .eth_status_vector_o (eth_status_vector_s),
    .eth_config_vector_i (eth_config_vector_s),
    .eth_an_complete_o   (eth_an_complete_s),
    .eth_pll_lock_o      (eth_pll_lock_s)
);


ethernet_mdio_wrap #(
    .SIMULATION         (SIMULATION)
) i_ethernet_mdio_wrap (
    .clk_eth_i          (clk_eth_i),
    .rst_eth_n_i        (reset_eth_sync_n_s),
    .mdio_mdc           (mdio_mdc),
    .mdio_mdio_i        (mdio_mdio_i),
    .mdio_mdio_o        (mdio_mdio_o),
    .mdio_mdio_t        (mdio_mdio_t)
);


ethernet_wrap #(
    .HOST_IP                (HOST_IP),
    .HOST_PORT              (HOST_PORT),
    .FPGA_IP_BASE           (FPGA_IP_BASE),
    .FPGA_PORT              (FPGA_PORT),
    .GATEWAY_IP_ADDR        (GATEWAY_IP_ADDR),
    .SUBNET_MASK            (SUBNET_MASK),
    .HOME_MODID             (HOME_MODID)
) i_ethernet_wrap (
    .clk_eth_i              (clk_eth_i),
    .rst_eth_n_i            (reset_eth_sync_n_s),

    .noc_fifo_in_data_i     (noc_fifo_in_data_i),
    .noc_fifo_in_raddr_o    (noc_fifo_in_raddr_o),
    .noc_fifo_in_waddr_i    (noc_fifo_in_waddr_i),
    .noc_fifo_out_data_o    (noc_fifo_out_data_o),
    .noc_fifo_out_raddr_i   (noc_fifo_out_raddr_i),
    .noc_fifo_out_waddr_o   (noc_fifo_out_waddr_o),


    .gmii_clk               (gmii_clk),
    .gmii_rst               (gmii_rst),
    .gmii_clk_en            (gmii_clk_en),
    .gmii_txd               (gmii_txd),
    .gmii_tx_en             (gmii_tx_en),
    .gmii_tx_er             (gmii_tx_er),
    .gmii_rxd               (gmii_rxd),
    .gmii_rx_dv             (gmii_rx_dv),
    .gmii_rx_er             (gmii_rx_er),

    .eth_status_vector_i    (eth_status_vector_s),
    .eth_config_vector_o    (eth_config_vector_s),
    .eth_an_complete_i      (eth_an_complete_s),
    .eth_pll_lock_i         (eth_pll_lock_s),
    .eth_system_reset_o     (eth_system_reset_o),
    .fpga_ip_addr_i         (fpga_ip_addr),
    .fpga_mac_addr_i        (fpga_mac_addr),
    .home_chipid_i          (home_chipid_o),
    .host_chipid_o          (host_chipid_o)
);



endmodule