data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array121x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array121x.v:40: Cannot find file containing module: 'array111x'\narray111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram1 (rst,wclk,wa,we,di,rclk1,ra1,do1);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/array111x\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/array111x.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/array111x.sv\n             array111x\n             array111x.v\n             array111x.sv\n             obj_dir/array111x\n             obj_dir/array111x.v\n             obj_dir/array111x.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/array121x.v:41: Cannot find file containing module: 'array111x'\narray111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram2 (rst,wclk,wa,we,di,rclk2,ra2,do2);\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module array121x (rst,wclk,wa,we,di,rclk1,ra1,do1,rclk2,ra2,do2);

parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter NUMCLK= 1;

input               rst;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk1;
input [ADDRBIT-1:0] ra1;
output [WIDTH-1:0]  do1;
input               rclk2;
input [ADDRBIT-1:0] ra2;
output [WIDTH-1:0]  do2;

array111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram1 (rst,wclk,wa,we,di,rclk1,ra1,do1);
array111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram2 (rst,wclk,wa,we,di,rclk2,ra2,do2);

endmodule
module array121x (rst,wclk,wa,we,di,rclk1,ra1,do1,rclk2,ra2,do2);


parameter ADDRBIT = 9;
parameter DEPTH = 512;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter NUMCLK= 1;

input               rst;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk1;
input [ADDRBIT-1:0] ra1;
output [WIDTH-1:0]  do1;
input               rclk2;
input [ADDRBIT-1:0] ra2;
output [WIDTH-1:0]  do2;

array111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram1 (rst,wclk,wa,we,di,rclk1,ra1,do1);
array111x #(ADDRBIT,DEPTH,WIDTH,TYPE,MAXDEPTH) ram2 (rst,wclk,wa,we,di,rclk2,ra2,do2);

endmodule