data/full_repos/permissive/463555432/Codes/amsg_sobel_v.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_sobel_v.v:16: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'n4\' generates 9 bits.\n                                                                            : ... In instance AMSG_sobel_v\n    assign ys1 = m1 + n4;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_sobel_v.v:22: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ys1\' generates 16 bits.\n                                                                            : ... In instance AMSG_sobel_v\n      y1 <= ys1;\n         ^~\n%Error: Exiting due to 2 warning(s)\n'
module AMSG_sobel_v(
input [7:0] p1, p3, p4, p6, p7, p9,
  output reg [7:0] y1
    );
    wire [15:0] ys1;
    wire [8:0] n1, n2, n3, n4;
    wire [15:0] m1;
    
    assign n1 = p1 + p7;
    assign n2 = p3 + p9;
    assign n3 = p6 - p4;
    assign m1 = 2 * n3;
    assign n4 = n2 - n1;
    assign ys1 = m1 + n4;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule
module AMSG_sobel_v(
input [7:0] p1, p3, p4, p6, p7, p9,
  output reg [7:0] y1
    );

    wire [15:0] ys1;
    wire [8:0] n1, n2, n3, n4;
    wire [15:0] m1;
    
    assign n1 = p1 + p7;
    assign n2 = p3 + p9;
    assign n3 = p6 - p4;
    assign m1 = 2 * n3;
    assign n4 = n2 - n1;
    assign ys1 = m1 + n4;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule