data/full_repos/permissive/422317798/~tmp5D_top.v
1: b"%Error: data/full_repos/permissive/422317798/~tmp5D_top.v:30: Cannot find file containing module: 'alu'\n    alu #(DATA_WIDTH) alu1 (clk, operand_a_i, operand_b_i, opcode_i, result1_i);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/422317798,data/full_repos/permissive/422317798/alu\n             data/full_repos/permissive/422317798,data/full_repos/permissive/422317798/alu.v\n             data/full_repos/permissive/422317798,data/full_repos/permissive/422317798/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: data/full_repos/permissive/422317798/~tmp5D_top.v:33: Cannot find file containing module: 'reg_mem'\n    reg_mem  #(DATA_WIDTH,ADDR_BITS) data_memory(result1_i, data_in_i, wen_i, clk, data_out_i);\n    ^~~~~~~\n%Error: data/full_repos/permissive/422317798/~tmp5D_top.v:36: Cannot find file containing module: 'CU'\n    CU  #(DATA_WIDTH,ADDR_BITS, INSTR_WIDTH) CU1(clk, rst, instruction, result2_i,\n    ^~\n%Error: Exiting due to 3 error(s)\n"
module simple_cpu( clk, rst, instruction );

    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;
    parameter INSTR_WIDTH =20;

    input [INSTR_WIDTH-1:0] instruction;
    input clk, rst;
 

    wire [ADDR_BITS-1:0] addr_i;
    wire [DATA_WIDTH-1:0] data_in_i, data_out_i, result2_i ;
    wire wen_i; 
    

    wire [DATA_WIDTH-1:0]operand_a_i, operand_b_i, result1_i;
    wire [3:0]opcode_i;
    
   

    wire [DATA_WIDTH-1:0]offset_i;
    wire sel1_i, sel3_i;
    wire [DATA_WIDTH-1:0] operand_1_i, operand_2_i,newreg0_i,newreg1_i, newreg2_i,newreg3_i;

   
    

    alu #(DATA_WIDTH) alu1 (clk, operand_a_i, operand_b_i, opcode_i, result1_i);
     

    reg_mem  #(DATA_WIDTH,ADDR_BITS) data_memory(result1_i, data_in_i, wen_i, clk, data_out_i);
    

    CU  #(DATA_WIDTH,ADDR_BITS, INSTR_WIDTH) CU1(clk, rst, instruction, result2_i,
        operand_1_i, operand_2_i, offset_i, opcode_i, sel1_i, sel3_i, wen_i,newreg0_i,newreg1_i, newreg2_i,newreg3_i);
    

    

    assign operand_a_i = operand_1_i;
    assign operand_b_i = (sel3_i == 0) ? operand_2_i: (sel3_i == 1) ? offset_i : 8'bx;
    

    assign data_in_i = operand_2_i;
    

    assign result2_i = (sel1_i == 0) ? data_out_i : (sel1_i == 1) ? result1_i : 8'bx;  

endmodule
module simple_cpu( clk, rst, instruction );


    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;
    parameter INSTR_WIDTH =20;

    input [INSTR_WIDTH-1:0] instruction;
    input clk, rst;
 

    wire [ADDR_BITS-1:0] addr_i;
    wire [DATA_WIDTH-1:0] data_in_i, data_out_i, result2_i ;
    wire wen_i; 
    

    wire [DATA_WIDTH-1:0]operand_a_i, operand_b_i, result1_i;
    wire [3:0]opcode_i;
    
   

    wire [DATA_WIDTH-1:0]offset_i;
    wire sel1_i, sel3_i;
    wire [DATA_WIDTH-1:0] operand_1_i, operand_2_i,newreg0_i,newreg1_i, newreg2_i,newreg3_i;

   
    

    alu #(DATA_WIDTH) alu1 (clk, operand_a_i, operand_b_i, opcode_i, result1_i);
     

    reg_mem  #(DATA_WIDTH,ADDR_BITS) data_memory(result1_i, data_in_i, wen_i, clk, data_out_i);
    

    CU  #(DATA_WIDTH,ADDR_BITS, INSTR_WIDTH) CU1(clk, rst, instruction, result2_i,
        operand_1_i, operand_2_i, offset_i, opcode_i, sel1_i, sel3_i, wen_i,newreg0_i,newreg1_i, newreg2_i,newreg3_i);
    

    

    assign operand_a_i = operand_1_i;
    assign operand_b_i = (sel3_i == 0) ? operand_2_i: (sel3_i == 1) ? offset_i : 8'bx;
    

    assign data_in_i = operand_2_i;
    

    assign result2_i = (sel1_i == 0) ? data_out_i : (sel1_i == 1) ? result1_i : 8'bx;  

endmodule