data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module close(
	input clk,
	input rst,
	
	input closex,
	
	input ready,
	
	input[7:0] out,
	
	output reg start4,
	output reg[7:0] in4,
	
	output reg rdy4
);

reg f_start;
reg n_start;

reg[3:0] f_tim;
reg[3:0] n_tim;

always@(posedge clk or posedge rst)
	if(rst) begin
		f_start <= 0;
		f_tim <= 0;
		end
	else begin
		f_start <= n_start;
		f_tim <= n_tim;
		end
always@(*)begin
	n_start = f_start;
	n_tim = f_tim;
	
	start4 = 0;
	in4 = 0;
	rdy4 = 0;
	
	if(closex)begin
		n_start = 1;
		
		in4 = 8'hFF;
		start4 = 1;
		n_tim = 1;
		
	end
	
	
	
	if(f_start)begin
		if(ready)begin
		
			if(f_tim != 0) n_tim = f_tim + 1;
			
			if(out == 8'hFF && f_tim == 0) begin
				n_start = 0;
				rdy4 = 1;
				end else
			begin
				in4 = 8'hFF;
				start4 = 1;
			end
			
		end
	end
	
	
end



endmodule
module close(
	input clk,
	input rst,
	
	input closex,
	
	input ready,
	
	input[7:0] out,
	
	output reg start4,
	output reg[7:0] in4,
	
	output reg rdy4
);


reg f_start;
reg n_start;

reg[3:0] f_tim;
reg[3:0] n_tim;

always@(posedge clk or posedge rst)
	if(rst) begin
		f_start <= 0;
		f_tim <= 0;
		end
	else begin
		f_start <= n_start;
		f_tim <= n_tim;
		end
always@(*)begin
	n_start = f_start;
	n_tim = f_tim;
	
	start4 = 0;
	in4 = 0;
	rdy4 = 0;
	
	if(closex)begin
		n_start = 1;
		
		in4 = 8'hFF;
		start4 = 1;
		n_tim = 1;
		
	end
	
	
	
	if(f_start)begin
		if(ready)begin
		
			if(f_tim != 0) n_tim = f_tim + 1;
			
			if(out == 8'hFF && f_tim == 0) begin
				n_start = 0;
				rdy4 = 1;
				end else
			begin
				in4 = 8'hFF;
				start4 = 1;
			end
			
		end
	end
	
	
end



endmodule