data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/More Circuits/Rule90/top_module.v
1: b'%Error: Cannot find file containing module: Logic/More\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.sv\n             Logic/More\n             Logic/More.v\n             Logic/More.sv\n             obj_dir/Logic/More\n             obj_dir/Logic/More.v\n             obj_dir/Logic/More.sv\n%Error: Cannot find file containing module: Circuits/Rule90,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Circuits/Rule90/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire clk,
    input wire load,
    input wire [511:0] data,
    output reg [511:0] q
);

  integer i;

  always @(posedge clk) begin
    if (load) q <= data;
    else begin
      for (i = 0; i < $bits(q); i = i + 1) begin
        if (i == 0) begin
          q[i] <= 1'b0 ^ q[i+1];
        end else if (i == $bits(q) - 1) begin
          q[i] <= q[i-1] ^ 1'b0;
        end else begin
          q[i] <= q[i-1] ^ q[i+1];
        end
      end
    end
  end

endmodule
module top_module (
    input wire clk,
    input wire load,
    input wire [511:0] data,
    output reg [511:0] q
);


  integer i;

  always @(posedge clk) begin
    if (load) q <= data;
    else begin
      for (i = 0; i < $bits(q); i = i + 1) begin
        if (i == 0) begin
          q[i] <= 1'b0 ^ q[i+1];
        end else if (i == $bits(q) - 1) begin
          q[i] <= q[i-1] ^ 1'b0;
        end else begin
          q[i] <= q[i-1] ^ q[i+1];
        end
      end
    end
  end

endmodule