data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:77: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:80: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:84: Define or directive not defined: \'`UART_ADDR_WIDTH\'\nwire [`UART_ADDR_WIDTH-1:0] wb_adr_i;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:112: Define or directive not defined: \'`UART_ADDR_WIDTH\'\nwire [`UART_ADDR_WIDTH-1:0] wb1_adr_i;\n      ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:160: Unsupported: Ignoring delay on this delayed statement.\n #50000 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1 wb_rst_ir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:197: Unsupported: Ignoring delay on this delayed statement.\n #10 wb_rst_ir = 0;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:201: Define or directive not defined: \'`UART_REG_LC\'\n wbm.wb_wr1(`UART_REG_LC, 4\'b1000, {8\'b10011011, 24\'b0});\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:203: Define or directive not defined: \'`UART_REG_DL1\'\n wbm.wb_wr1(`UART_REG_DL1,4\'b0001, 32\'d2);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:204: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:207: Define or directive not defined: \'`UART_REG_LC\'\n wbm.wb_wr1(`UART_REG_LC, 4\'b1000, {8\'b00011011, 24\'b0});  \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:210: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:214: Unsupported: wait statements\n wait (uart_snd.regs.tstate==0 && uart_snd.regs.transmitter.tf_count==0);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:236: Unsupported: Ignoring delay on this delayed statement.\n #11;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:239: Define or directive not defined: \'`UART_REG_LC\'\n wbm1.wb_wr1(`UART_REG_LC, 4\'b1000, {8\'b10011011, 24\'b0});\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:241: Define or directive not defined: \'`UART_REG_DL1\'\n wbm1.wb_wr1(`UART_REG_DL1, 4\'b1, 32\'d2);\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:242: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:245: Define or directive not defined: \'`UART_REG_LC\'\n wbm1.wb_wr1(`UART_REG_LC, 4\'b1000, {8\'b00011011, 24\'b0});\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:246: Define or directive not defined: \'`UART_REG_IE\'\n wbm1.wb_wr1(`UART_REG_IE, 4\'b0010, {16\'b0, 8\'b00001111, 8\'b0});\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:247: Unsupported: wait statements\n wait(uart_rcv.regs.receiver.rf_count == 2);\n ^~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:251: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:256: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:263: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:269: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:287: Define or directive not defined: \'`UART_ADDR_WIDTH\'\n  $display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH);\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:287: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH);\n                                    ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:287: Define or directive not defined: \'`UART_DATA_WIDTH\'\n  $display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH);\n                                      ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/rel_1/bench/verilog/uart_test.v:294: Unsupported: Ignoring delay on this delayed statement.\n #5 clkr = ~clk;\n ^\n%Error: Exiting due to 23 error(s), 5 warning(s)\n'
module uart_test ();

`include "uart_defines.v"

reg				clkr;
reg				wb_rst_ir;
wire	[`UART_ADDR_WIDTH-1:0]	wb_adr_i;
wire	[31:0]	wb_dat_i;
wire	[31:0]	wb_dat_o;
wire [3:0]		wb_sel_i;
wire				pad_stx_o;
reg				pad_srx_ir;

integer e;

uart_top	uart_snd(
	clk, 
	

						wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	wb_sel_i,
	int_o,



	pad_stx_o, pad_srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);




wire	[`UART_ADDR_WIDTH-1:0]	wb1_adr_i;
wire	[31:0]			wb1_dat_i;
wire	[31:0]			wb1_dat_o;
wire [3:0] 		wb1_sel_i;
wire				int1_o;
wire				stx1_o;
reg				srx1_ir;

uart_top	uart_rcv(
	clk, 
	

	wb_rst_i, wb1_adr_i, wb1_dat_i, wb1_dat_o, wb1_we_i, wb1_stb_i, wb1_cyc_i, wb1_ack_o, wb1_sel_i,	
	int1_o,



	stx1_o, srx1_i,


	rts1_o, cts1_i, dtr1_o, dsr1_i, ri1_i, dcd1_i

	);

assign clk = clkr;
assign wb_rst_i = wb_rst_ir;
assign pad_srx_i = pad_srx_ir;
assign cts_i = 1;
assign dsr_i = 1;
assign ri_i = 1;
assign dcd_i = 1;

assign srx1_i = srx1_ir;
assign cts1_i = 1;
assign dsr1_i = 1;
assign ri1_i = 1;
assign dcd1_i = 1;

reg [31:0] dat_o;

always @(pad_stx_o)
begin
	srx1_ir = pad_stx_o;	
end

initial
begin
	clkr = 0;
	#50000 $finish;
end

wb_mast wbm(
				.adr								 (wb_adr_i),
				.dout								 (wb_dat_i),
				.cyc								 (wb_cyc_i),
				.stb								 (wb_stb_i),
				.sel								 (wb_sel_i),
				.we								 (wb_we_i),

				.clk								 (clk),
				.rst								 (wb_rst_i),
				.din								 (wb_dat_o),
				.ack								 (wb_ack_o),
				.err								 (1'b0),
				.rty								 (1'b0));

wb_mast wbm1(
				 .adr								 (wb1_adr_i),
				 .dout							 (wb1_dat_i),
				 .cyc								 (wb1_cyc_i),
				 .stb								 (wb1_stb_i),
				 .sel								 (wb1_sel_i),
				 .we								 (wb1_we_i),

				 .clk								 (clk),
				 .rst								 (wb_rst_i),
				 .din								 (wb1_dat_o),
				 .ack								 (wb1_ack_o),
				 .err								 (1'b0),
				 .rty								 (1'b0));


initial
begin
	#1 wb_rst_ir = 1;
	#10 wb_rst_ir = 0;
		


	wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0});

	wbm.wb_wr1(`UART_REG_DL1,4'b0001, 32'd2);
	@(posedge clk);
	@(posedge clk);

	wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0});
	$display("%m : %t : sending : %h", $time, 8'b01101011);
	wbm.wb_wr1(0, 4'b1, 32'b01101011);
	@(posedge clk);
	@(posedge clk);
	$display("%m : %t : sending : %h", $time, 8'b01000101);
	wbm.wb_wr1(0, 4'b1, 32'b01000101);
	wait (uart_snd.regs.tstate==0 && uart_snd.regs.transmitter.tf_count==0);
end

always @(int1_o)
	if (int1_o)
		$display("INT_O high (%g)", $time);
	else
		$display("INT_O low (%g)", $time);
		
always @(int1_o)
begin
	if (int1_o) begin
		wbm1.wb_rd1(2,4'b0100, dat_o);
		$display("IIR : %h", dat_o);
		wbm1.wb_rd1(5,4'b0010, dat_o);
		$display("LSR : %h", dat_o);
	end
end


initial
begin
	#11;


	wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0});

	wbm1.wb_wr1(`UART_REG_DL1, 4'b1, 32'd2);
	@(posedge clk);
	@(posedge clk);

	wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0});
	wbm1.wb_wr1(`UART_REG_IE, 4'b0010, {16'b0, 8'b00001111, 8'b0});
	wait(uart_rcv.regs.receiver.rf_count == 2);
		e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	wbm1.wb_rd1(0, 4'b1, dat_o);
	$display("%m : %t : Data out: %h", $time, dat_o);
	@(posedge clk);
	wbm1.wb_rd1(0, 4'b1, dat_o);
	$display("%m : %t : Data out: %h", $time, dat_o);
	$display("%m : Finish");
	e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	$finish;
end






initial
	begin
		`ifdef DATA_BUS_WIDTH_8
$display("DATA BUS IS 8");
`else
$display("DATA BUS IS 32");
`endif
		$display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH);

	end


always
begin
	#5 clkr = ~clk;
end

endmodule
module uart_test ();


`include "uart_defines.v"

reg				clkr;
reg				wb_rst_ir;
wire	[`UART_ADDR_WIDTH-1:0]	wb_adr_i;
wire	[31:0]	wb_dat_i;
wire	[31:0]	wb_dat_o;
wire [3:0]		wb_sel_i;
wire				pad_stx_o;
reg				pad_srx_ir;

integer e;

uart_top	uart_snd(
	clk, 
	

						wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	wb_sel_i,
	int_o,



	pad_stx_o, pad_srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);




wire	[`UART_ADDR_WIDTH-1:0]	wb1_adr_i;
wire	[31:0]			wb1_dat_i;
wire	[31:0]			wb1_dat_o;
wire [3:0] 		wb1_sel_i;
wire				int1_o;
wire				stx1_o;
reg				srx1_ir;

uart_top	uart_rcv(
	clk, 
	

	wb_rst_i, wb1_adr_i, wb1_dat_i, wb1_dat_o, wb1_we_i, wb1_stb_i, wb1_cyc_i, wb1_ack_o, wb1_sel_i,	
	int1_o,



	stx1_o, srx1_i,


	rts1_o, cts1_i, dtr1_o, dsr1_i, ri1_i, dcd1_i

	);

assign clk = clkr;
assign wb_rst_i = wb_rst_ir;
assign pad_srx_i = pad_srx_ir;
assign cts_i = 1;
assign dsr_i = 1;
assign ri_i = 1;
assign dcd_i = 1;

assign srx1_i = srx1_ir;
assign cts1_i = 1;
assign dsr1_i = 1;
assign ri1_i = 1;
assign dcd1_i = 1;

reg [31:0] dat_o;

always @(pad_stx_o)
begin
	srx1_ir = pad_stx_o;	
end

initial
begin
	clkr = 0;
	#50000 $finish;
end

wb_mast wbm(
				.adr								 (wb_adr_i),
				.dout								 (wb_dat_i),
				.cyc								 (wb_cyc_i),
				.stb								 (wb_stb_i),
				.sel								 (wb_sel_i),
				.we								 (wb_we_i),

				.clk								 (clk),
				.rst								 (wb_rst_i),
				.din								 (wb_dat_o),
				.ack								 (wb_ack_o),
				.err								 (1'b0),
				.rty								 (1'b0));

wb_mast wbm1(
				 .adr								 (wb1_adr_i),
				 .dout							 (wb1_dat_i),
				 .cyc								 (wb1_cyc_i),
				 .stb								 (wb1_stb_i),
				 .sel								 (wb1_sel_i),
				 .we								 (wb1_we_i),

				 .clk								 (clk),
				 .rst								 (wb_rst_i),
				 .din								 (wb1_dat_o),
				 .ack								 (wb1_ack_o),
				 .err								 (1'b0),
				 .rty								 (1'b0));


initial
begin
	#1 wb_rst_ir = 1;
	#10 wb_rst_ir = 0;
		


	wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0});

	wbm.wb_wr1(`UART_REG_DL1,4'b0001, 32'd2);
	@(posedge clk);
	@(posedge clk);

	wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0});
	$display("%m : %t : sending : %h", $time, 8'b01101011);
	wbm.wb_wr1(0, 4'b1, 32'b01101011);
	@(posedge clk);
	@(posedge clk);
	$display("%m : %t : sending : %h", $time, 8'b01000101);
	wbm.wb_wr1(0, 4'b1, 32'b01000101);
	wait (uart_snd.regs.tstate==0 && uart_snd.regs.transmitter.tf_count==0);
end

always @(int1_o)
	if (int1_o)
		$display("INT_O high (%g)", $time);
	else
		$display("INT_O low (%g)", $time);
		
always @(int1_o)
begin
	if (int1_o) begin
		wbm1.wb_rd1(2,4'b0100, dat_o);
		$display("IIR : %h", dat_o);
		wbm1.wb_rd1(5,4'b0010, dat_o);
		$display("LSR : %h", dat_o);
	end
end


initial
begin
	#11;


	wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0});

	wbm1.wb_wr1(`UART_REG_DL1, 4'b1, 32'd2);
	@(posedge clk);
	@(posedge clk);

	wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0});
	wbm1.wb_wr1(`UART_REG_IE, 4'b0010, {16'b0, 8'b00001111, 8'b0});
	wait(uart_rcv.regs.receiver.rf_count == 2);
		e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	wbm1.wb_rd1(0, 4'b1, dat_o);
	$display("%m : %t : Data out: %h", $time, dat_o);
	@(posedge clk);
	wbm1.wb_rd1(0, 4'b1, dat_o);
	$display("%m : %t : Data out: %h", $time, dat_o);
	$display("%m : Finish");
	e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	e = 800;
	while (e > 0)
	begin
		@(posedge clk)
 		if (uart_rcv.regs.enable) e = e - 1;
	end
	$finish;
end






initial
	begin
		`ifdef DATA_BUS_WIDTH_8
$display("DATA BUS IS 8");
`else
$display("DATA BUS IS 32");
`endif
		$display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH);

	end


always
begin
	#5 clkr = ~clk;
end

endmodule