data/full_repos/permissive/459277146/complete.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:262: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:270: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd"); $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpvars\n  $dumpfile("dump.vcd"); $dumpvars;\n                         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:368: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD / 2) clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/459277146/complete.v:371: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%d:\\t%d /%d =%d (r =) (V=) (DBZ=)",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:378: Unsupported: Ignoring delay on this delayed statement.\n        #100    x = 4\'b0000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:381: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:383: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:386: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:388: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:391: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:393: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:396: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:398: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0001;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:401: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:403: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:406: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:410: Unsupported: Ignoring delay on this delayed statement.\n        #50     $finish;\n        ^\n%Error: data/full_repos/permissive/459277146/complete.v:413: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("div.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:414: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars; \n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier #(parameter DWIDTH = 8) (multicand, multiplier, product1, product2);

input [DWIDTH-1:0] multicand;
input [DWIDTH-1:0] multiplier;
output [DWIDTH-1:0] product1;
output [DWIDTH-1:0] product2;
wire [(DWIDTH + DWIDTH - 1):0] product;

assign product1 = product[DWIDTH-1:0];
assign product2 = product[(DWIDTH<<1)-1:DWIDTH];


wire [DWIDTH - 1:0] multicand_tmp [DWIDTH-1:0];
wire [DWIDTH - 1:0] product_tmp [DWIDTH-1:0];
wire [DWIDTH -1:0] carry_tmp;

genvar i, j;
generate 

 for(j = 0; j < DWIDTH; j = j + 1) begin: for_loop_j
 assign multicand_tmp[j] =  multicand & {DWIDTH{multiplier[j]}};
 end
 
 assign product_tmp[0] = multicand_tmp[0];
 assign carry_tmp[0] = 1'b0;
 assign product[0] = product_tmp[0][0];
 
 for(i = 1; i < DWIDTH; i = i + 1) begin: for_loop_i
 adder #(.DATA_WID(DWIDTH)) add1 (

     .sum(product_tmp[i]),
     .carry_out(carry_tmp[i]),

   .carry_in(1'b0),
     .in1(multicand_tmp[i]),
   .in2({carry_tmp[i-1],product_tmp[i-1][7-:7]}));
 assign product[i] = product_tmp[i][0];
 end
 assign product[(DWIDTH+DWIDTH-1):DWIDTH] = {carry_tmp[DWIDTH-1],product_tmp[DWIDTH-1][7-:7]};
endgenerate
endmodule
module multiplier #(parameter DWIDTH = 8) (multicand, multiplier, product1, product2);


input [DWIDTH-1:0] multicand;
input [DWIDTH-1:0] multiplier;
output [DWIDTH-1:0] product1;
output [DWIDTH-1:0] product2;
wire [(DWIDTH + DWIDTH - 1):0] product;

assign product1 = product[DWIDTH-1:0];
assign product2 = product[(DWIDTH<<1)-1:DWIDTH];


wire [DWIDTH - 1:0] multicand_tmp [DWIDTH-1:0];
wire [DWIDTH - 1:0] product_tmp [DWIDTH-1:0];
wire [DWIDTH -1:0] carry_tmp;

genvar i, j;
generate 

 for(j = 0; j < DWIDTH; j = j + 1) begin: for_loop_j
 assign multicand_tmp[j] =  multicand & {DWIDTH{multiplier[j]}};
 end
 
 assign product_tmp[0] = multicand_tmp[0];
 assign carry_tmp[0] = 1'b0;
 assign product[0] = product_tmp[0][0];
 
 for(i = 1; i < DWIDTH; i = i + 1) begin: for_loop_i
 adder #(.DATA_WID(DWIDTH)) add1 (

     .sum(product_tmp[i]),
     .carry_out(carry_tmp[i]),

   .carry_in(1'b0),
     .in1(multicand_tmp[i]),
   .in2({carry_tmp[i-1],product_tmp[i-1][7-:7]}));
 assign product[i] = product_tmp[i][0];
 end
 assign product[(DWIDTH+DWIDTH-1):DWIDTH] = {carry_tmp[DWIDTH-1],product_tmp[DWIDTH-1][7-:7]};
endgenerate
endmodule