data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v
1: b'%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:33: Cannot find include file: or1k_defines.v\n`include "or1k_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.sv\n             or1k_defines.v\n             or1k_defines.v.v\n             or1k_defines.v.sv\n             obj_dir/or1k_defines.v\n             obj_dir/or1k_defines.v.v\n             obj_dir/or1k_defines.v.sv\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:60: Define or directive not defined: \'`OR1K_INSN_WIDTH\'\n  input          [`OR1K_INSN_WIDTH-1:0] fetch_insn_i,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:107: Define or directive not defined: \'`OR1K_IMM_WIDTH\'\n  output reg      [`OR1K_IMM_WIDTH-1:0] dcod_imm16_o,\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:148: Define or directive not defined: \'`OR1K_COMP_OPC_WIDTH\'\n  output reg [`OR1K_COMP_OPC_WIDTH-1:0] dcod_opc_setflag_o,\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:173: Define or directive not defined: \'`OR1K_FPUOP_GENERIC_CMP_WIDTH\'\n  output reg [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] dcod_opc_fpxx_cmp_o,  \n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:173: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  output reg [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] dcod_opc_fpxx_cmp_o,  \n                                           ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:179: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_op_mtspr_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:180: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_op_mXspr_o,  \n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:184: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_except_illegal_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:185: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_except_syscall_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:186: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_except_trap_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:188: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_an_except_fd_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:191: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg                            dcod_op_rfe_o\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:202: Define or directive not defined: \'`OR1K_OPCODE_WIDTH\'\n  wire [`OR1K_OPCODE_WIDTH-1:0]  opc_insn = fetch_insn_i[`OR1K_OPCODE_SELECT];\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:202: Define or directive not defined: \'`OR1K_OPCODE_SELECT\'\n  wire [`OR1K_OPCODE_WIDTH-1:0]  opc_insn = fetch_insn_i[`OR1K_OPCODE_SELECT];\n                                                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:202: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [`OR1K_OPCODE_WIDTH-1:0]  opc_insn = fetch_insn_i[`OR1K_OPCODE_SELECT];\n                                                                            ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:211: Define or directive not defined: \'`OR1K_OPCODE_LWA\'\n  wire op_lsu_load = (opc_insn == `OR1K_OPCODE_LWA) |                                   \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:211: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire op_lsu_load = (opc_insn == `OR1K_OPCODE_LWA) |                                   \n                                                  ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:212: Define or directive not defined: \'`OR1K_OPCODE_LWZ\'\n                     (opc_insn == `OR1K_OPCODE_LWZ) | (opc_insn == `OR1K_OPCODE_LWS) |  \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:212: Define or directive not defined: \'`OR1K_OPCODE_LWS\'\n                     (opc_insn == `OR1K_OPCODE_LWZ) | (opc_insn == `OR1K_OPCODE_LWS) |  \n                                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:213: Define or directive not defined: \'`OR1K_OPCODE_LHZ\'\n                     (opc_insn == `OR1K_OPCODE_LHZ) | (opc_insn == `OR1K_OPCODE_LHS) |  \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:213: Define or directive not defined: \'`OR1K_OPCODE_LHS\'\n                     (opc_insn == `OR1K_OPCODE_LHZ) | (opc_insn == `OR1K_OPCODE_LHS) |  \n                                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:214: Define or directive not defined: \'`OR1K_OPCODE_LBZ\'\n                     (opc_insn == `OR1K_OPCODE_LBZ) | (opc_insn == `OR1K_OPCODE_LBS) |  \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:214: Define or directive not defined: \'`OR1K_OPCODE_LBS\'\n                     (opc_insn == `OR1K_OPCODE_LBZ) | (opc_insn == `OR1K_OPCODE_LBS) |  \n                                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:215: Define or directive not defined: \'`OR1K_OPCODE_LD\'\n                     ((opc_insn == `OR1K_OPCODE_LD) & (OPTION_OPERAND_WIDTH == 64));    \n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:218: Define or directive not defined: \'`OR1K_OPCODE_SWA\'\n  wire op_lsu_store = (opc_insn == `OR1K_OPCODE_SWA) | (opc_insn == `OR1K_OPCODE_SW)  |  \n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:218: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire op_lsu_store = (opc_insn == `OR1K_OPCODE_SWA) | (opc_insn == `OR1K_OPCODE_SW)  |  \n                                                   ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:218: Define or directive not defined: \'`OR1K_OPCODE_SW\'\n  wire op_lsu_store = (opc_insn == `OR1K_OPCODE_SWA) | (opc_insn == `OR1K_OPCODE_SW)  |  \n                                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:219: Define or directive not defined: \'`OR1K_OPCODE_SH\'\n                      (opc_insn == `OR1K_OPCODE_SH)  | (opc_insn == `OR1K_OPCODE_SB)  |  \n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:219: Define or directive not defined: \'`OR1K_OPCODE_SB\'\n                      (opc_insn == `OR1K_OPCODE_SH)  | (opc_insn == `OR1K_OPCODE_SB)  |  \n                                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:220: Define or directive not defined: \'`OR1K_OPCODE_SD\'\n                      ((opc_insn == `OR1K_OPCODE_SD) & (OPTION_OPERAND_WIDTH == 64));    \n                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:222: Define or directive not defined: \'`OR1K_OPCODE_LWA\'\n  wire op_lsu_atomic = (opc_insn == `OR1K_OPCODE_LWA) | (opc_insn == `OR1K_OPCODE_SWA);\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:222: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire op_lsu_atomic = (opc_insn == `OR1K_OPCODE_LWA) | (opc_insn == `OR1K_OPCODE_SWA);\n                                                    ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:222: Define or directive not defined: \'`OR1K_OPCODE_SWA\'\n  wire op_lsu_atomic = (opc_insn == `OR1K_OPCODE_LWA) | (opc_insn == `OR1K_OPCODE_SWA);\n                                                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:228: syntax error, unexpected always\n  always @(opc_insn)\n  ^~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:232: Define or directive not defined: \'`OR1K_OPCODE_SB\'\n      `OR1K_OPCODE_SB,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:233: Define or directive not defined: \'`OR1K_OPCODE_LBZ\'\n      `OR1K_OPCODE_LBZ,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:234: Define or directive not defined: \'`OR1K_OPCODE_LBS\'\n      `OR1K_OPCODE_LBS: lsu_length = 2\'b00;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:236: Define or directive not defined: \'`OR1K_OPCODE_SH\'\n      `OR1K_OPCODE_SH,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:237: Define or directive not defined: \'`OR1K_OPCODE_LHZ\'\n      `OR1K_OPCODE_LHZ,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:238: Define or directive not defined: \'`OR1K_OPCODE_LHS\'\n      `OR1K_OPCODE_LHS: lsu_length = 2\'b01;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:240: Define or directive not defined: \'`OR1K_OPCODE_SW\'\n      `OR1K_OPCODE_SW,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:241: Define or directive not defined: \'`OR1K_OPCODE_SWA\'\n      `OR1K_OPCODE_SWA,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:242: Define or directive not defined: \'`OR1K_OPCODE_LWZ\'\n      `OR1K_OPCODE_LWZ,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:243: Define or directive not defined: \'`OR1K_OPCODE_LWS\'\n      `OR1K_OPCODE_LWS,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:244: Define or directive not defined: \'`OR1K_OPCODE_LWA\'\n      `OR1K_OPCODE_LWA: lsu_length = 2\'b10;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:251: Define or directive not defined: \'`OR1K_OPCODE_SYSTRAPSYNC\'\n  wire op_msync = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &\n                               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:251: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire op_msync = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &\n                                                       ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:252: Define or directive not defined: \'`OR1K_SYSTRAPSYNC_OPC_SELECT\'\n                   (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==\n                                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v:253: Define or directive not defined: \'`OR1K_SYSTRAPSYNC_OPC_MSYNC\'\n                    `OR1K_SYSTRAPSYNC_OPC_MSYNC);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module or1k_marocchino_decode
#(
  parameter OPTION_OPERAND_WIDTH = 32,
  parameter OPTION_RF_ADDR_WIDTH =  5,

  parameter FEATURE_PSYNC        = "NONE",
  parameter FEATURE_CSYNC        = "NONE"
)
(

  input                                 cpu_clk,


  input                                 padv_dcod_i,
  input                                 padv_exec_i,
  input                                 pipeline_flush_i,



  input                                 fetch_valid_i,

  input                                 fetch_an_except_i,

  input                                 fetch_delay_slot_i,

  input          [`OR1K_INSN_WIDTH-1:0] fetch_insn_i,

  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa2_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb2_adr_i,

  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfd1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfd2_adr_i,


  output reg                            dcod_empty_o,
  output reg                            dcod_delay_slot_o,



  output reg                            dcod_rfa1_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfa1_adr_o,

  output reg                            dcod_rfb1_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfb1_adr_o,

  output reg                            dcod_rfa2_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfa2_adr_o,

  output reg                            dcod_rfb2_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfb2_adr_o,


  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfd1_adr_o,
  output reg                            dcod_rfd1_we_o,

  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfd2_adr_o,
  output reg                            dcod_rfd2_we_o,


  input      [OPTION_OPERAND_WIDTH-1:0] pc_fetch_i,
  output reg [OPTION_OPERAND_WIDTH-1:0] pc_decode_o,


  output reg [OPTION_OPERAND_WIDTH-1:0] dcod_immediate_o,
  output reg                            dcod_immediate_sel_o,


  output reg                            dcod_flag_we_o,


  output reg      [`OR1K_IMM_WIDTH-1:0] dcod_imm16_o,
  output reg                            dcod_op_lsu_load_o,
  output reg                            dcod_op_lsu_store_o,
  output reg                            dcod_op_lsu_atomic_o,
  output reg                      [1:0] dcod_lsu_length_o,
  output reg                            dcod_lsu_zext_o,
  output reg                            dcod_op_msync_o,
  output reg                            dcod_op_lsu_any_o,


  output reg                            dcod_op_push_exec_o,

  output reg                            dcod_op_push_wrbk_o,


  output reg                            dcod_op_1clk_o,

  output reg                            dcod_flag_carry_req_o,

  output reg                            dcod_op_add_o,
  output reg                            dcod_adder_do_sub_o,
  output reg                            dcod_adder_do_carry_o,

  output reg                            dcod_op_shift_o,
  output reg                      [3:0] dcod_opc_shift_o,

  output reg                            dcod_op_ffl1_o,
  output reg                            dcod_opc_ffl1_o,

  output reg                            dcod_op_movhi_o,
  output reg                            dcod_op_cmov_o,

  output reg                            dcod_op_extsz_o,
  output reg                      [3:0] dcod_opc_extsz_o,

  output reg                            dcod_op_logic_o,
  output reg                      [3:0] dcod_lut_logic_o,

  output reg                            dcod_op_jal_o,

  output reg                            dcod_op_setflag_o,
  output reg [`OR1K_COMP_OPC_WIDTH-1:0] dcod_opc_setflag_o,


  output reg                            dcod_op_mul_o,


  output reg                            dcod_op_div_o,
  output reg                            dcod_op_div_signed_o,
  output reg                            dcod_op_div_unsigned_o,


  output reg                            dcod_op_muldiv_o,


  output reg                            dcod_op_fpxx_arith_o,
  output reg                            dcod_op_fp64_arith_o,
  output reg                            dcod_op_fpxx_add_o,
  output reg                            dcod_op_fpxx_sub_o,
  output reg                            dcod_op_fpxx_mul_o,
  output reg                            dcod_op_fpxx_div_o,
  output reg                            dcod_op_fpxx_i2f_o,
  output reg                            dcod_op_fpxx_f2i_o,


  output reg                                   dcod_op_fpxx_cmp_o,
  output reg [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] dcod_opc_fpxx_cmp_o,


  output reg                            dcod_op_fpxx_any_o,


  output reg                            dcod_op_mtspr_o,
  output reg                            dcod_op_mXspr_o,



  output reg                            dcod_except_illegal_o,
  output reg                            dcod_except_syscall_o,
  output reg                            dcod_except_trap_o,

  output reg                            dcod_an_except_fd_o,


  output reg                            dcod_op_rfe_o
);

  wire [OPTION_OPERAND_WIDTH-1:0] imm_sext;
  wire                            imm_sext_sel;
  wire [OPTION_OPERAND_WIDTH-1:0] imm_zext;
  wire                            imm_zext_sel;
  wire [OPTION_OPERAND_WIDTH-1:0] imm_high;
  wire                            imm_high_sel;


  wire [`OR1K_OPCODE_WIDTH-1:0]  opc_insn = fetch_insn_i[`OR1K_OPCODE_SELECT];








  wire op_lsu_load = (opc_insn == `OR1K_OPCODE_LWA) |
                     (opc_insn == `OR1K_OPCODE_LWZ) | (opc_insn == `OR1K_OPCODE_LWS) |
                     (opc_insn == `OR1K_OPCODE_LHZ) | (opc_insn == `OR1K_OPCODE_LHS) |
                     (opc_insn == `OR1K_OPCODE_LBZ) | (opc_insn == `OR1K_OPCODE_LBS) |
                     ((opc_insn == `OR1K_OPCODE_LD) & (OPTION_OPERAND_WIDTH == 64));


  wire op_lsu_store = (opc_insn == `OR1K_OPCODE_SWA) | (opc_insn == `OR1K_OPCODE_SW)  |
                      (opc_insn == `OR1K_OPCODE_SH)  | (opc_insn == `OR1K_OPCODE_SB)  |
                      ((opc_insn == `OR1K_OPCODE_SD) & (OPTION_OPERAND_WIDTH == 64));

  wire op_lsu_atomic = (opc_insn == `OR1K_OPCODE_LWA) | (opc_insn == `OR1K_OPCODE_SWA);



  reg [1:0] lsu_length;

  always @(opc_insn)
    (* parallel_case *)
    case (opc_insn)

      `OR1K_OPCODE_SB,
      `OR1K_OPCODE_LBZ,
      `OR1K_OPCODE_LBS: lsu_length = 2'b00;

      `OR1K_OPCODE_SH,
      `OR1K_OPCODE_LHZ,
      `OR1K_OPCODE_LHS: lsu_length = 2'b01;

      `OR1K_OPCODE_SW,
      `OR1K_OPCODE_SWA,
      `OR1K_OPCODE_LWZ,
      `OR1K_OPCODE_LWS,
      `OR1K_OPCODE_LWA: lsu_length = 2'b10;

      default:          lsu_length = 2'b10;
  endcase

  wire lsu_zext = opc_insn[0];

  wire op_msync = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                   (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                    `OR1K_SYSTRAPSYNC_OPC_MSYNC);



  wire op_nop = (opc_insn == `OR1K_OPCODE_NOP);



  wire op_mtspr = (opc_insn == `OR1K_OPCODE_MTSPR);
  wire op_mfspr = (opc_insn == `OR1K_OPCODE_MFSPR);



  wire op_setflag = (opc_insn == `OR1K_OPCODE_SF) |
                    (opc_insn == `OR1K_OPCODE_SFIMM);



  wire op_jal = (opc_insn == `OR1K_OPCODE_JALR) | (opc_insn == `OR1K_OPCODE_JAL);



  wire [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu  = fetch_insn_i[`OR1K_ALU_OPC_SELECT];
  wire op_alu = (opc_insn == `OR1K_OPCODE_ALU);



  wire op_add = (op_alu &
                 ((opc_alu == `OR1K_ALU_OPC_ADDC) |
                  (opc_alu == `OR1K_ALU_OPC_ADD)  |
                  (opc_alu == `OR1K_ALU_OPC_SUB))) |
                (opc_insn == `OR1K_OPCODE_ADDIC)   |
                (opc_insn == `OR1K_OPCODE_ADDI)    |
                op_jal;


  wire adder_do_sub = (op_alu & (opc_alu == `OR1K_ALU_OPC_SUB)) |
                      op_setflag;

  wire adder_do_carry = (op_alu & (opc_alu == `OR1K_ALU_OPC_ADDC)) |
                        (opc_insn == `OR1K_OPCODE_ADDIC);



  wire op_mul_signed   = (op_alu & (opc_alu == `OR1K_ALU_OPC_MUL)) |
                         (opc_insn == `OR1K_OPCODE_MULI);
  wire op_mul_unsigned = op_alu & (opc_alu == `OR1K_ALU_OPC_MULU);
  wire op_mul          = op_mul_signed | op_mul_unsigned;



  wire op_div_signed   = op_alu & (opc_alu == `OR1K_ALU_OPC_DIV);
  wire op_div_unsigned = op_alu & (opc_alu == `OR1K_ALU_OPC_DIVU);
  wire op_div          = op_div_signed | op_div_unsigned;



  wire op_shift = (op_alu & (opc_alu  == `OR1K_ALU_OPC_SHRT)) |
                  (opc_insn == `OR1K_OPCODE_SHRTI);
  wire [`OR1K_ALU_OPC_SECONDARY_WIDTH-1:0] opc_shift;
  assign opc_shift = fetch_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT];



  wire op_ffl1  = op_alu & (opc_alu  == `OR1K_ALU_OPC_FFL1);
  wire opc_ffl1 = fetch_insn_i[8];



  wire op_movhi = (opc_insn == `OR1K_OPCODE_MOVHI);
  wire op_cmov  = (op_alu & (opc_alu == `OR1K_ALU_OPC_CMOV));




  wire is_extw  = (opc_alu == `OR1K_ALU_OPC_EXTW);
  wire op_extsz = op_alu & ((opc_alu == `OR1K_ALU_OPC_EXTBH) |
                            is_extw);
  wire [3:0] opc_extsz = {is_extw, fetch_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]};



  wire [3:0] lut_logic;
  assign lut_logic =
    ((op_alu & (opc_alu == `OR1K_ALU_OPC_OR )) | (opc_insn == `OR1K_OPCODE_ORI )) ? 4'b1110 :
   (((op_alu & (opc_alu == `OR1K_ALU_OPC_XOR)) | (opc_insn == `OR1K_OPCODE_XORI)) ? 4'b0110 :
   (((op_alu & (opc_alu == `OR1K_ALU_OPC_AND)) | (opc_insn == `OR1K_OPCODE_ANDI)) ? 4'b1000 :
                                                                                    4'b0000));


  wire op_fpxx = (opc_insn == `OR1K_OPCODE_FPU);



  wire op_fp64bit = fetch_insn_i[`OR1K_FPUOP_DOUBLE_BIT];



  wire op_fpxx_arith_t = (~fetch_insn_i[3]);

  wire op_fpxx_arith_l = op_fpxx_arith_t & (fetch_insn_i[2:0] < 3'd6);

  wire op_fpxx_arith = op_fpxx_arith_l & op_fpxx;








  wire op_fpxx_add = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd0) & op_fpxx;
  wire op_fpxx_sub = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd1) & op_fpxx;
  wire op_fpxx_mul = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd2) & op_fpxx;
  wire op_fpxx_div = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd3) & op_fpxx;
  wire op_fpxx_i2f = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd4) & op_fpxx;
  wire op_fpxx_f2i = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd5) & op_fpxx;



  wire op_fpxx_cmp_l = fetch_insn_i[3] & (fetch_insn_i[2:0] < 3'd7);

  wire op_fpxx_cmp = op_fpxx_cmp_l & op_fpxx;

















  wire [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] opc_fpxx_cmp;

  assign opc_fpxx_cmp = {fetch_insn_i[`OR1K_FPUOP_UNORDERED_CMP_BIT],
                         fetch_insn_i[`OR1K_FPUOP_GENERIC_CMP_SELECT]};


  wire [`OR1K_IMM_WIDTH-1:0] imm16;
  assign imm16 = (op_mtspr | op_lsu_store) ?
                  {fetch_insn_i[25:21],fetch_insn_i[10:0]} :
                  fetch_insn_i[`OR1K_IMM_SELECT];


  wire [`OR1K_IMM_WIDTH-1:0] opc_imm16 = fetch_insn_i[`OR1K_IMM_SELECT];



  assign imm_sext     = {{16{opc_imm16[15]}}, opc_imm16};
  assign imm_sext_sel = (opc_insn == `OR1K_OPCODE_ADDI)  |
                        (opc_insn == `OR1K_OPCODE_ADDIC) |
                        (opc_insn == `OR1K_OPCODE_XORI)  |
                        (opc_insn == `OR1K_OPCODE_MULI)  |
                        (opc_insn == `OR1K_OPCODE_SFIMM);



  assign imm_zext     = {16'd0, opc_imm16};
  assign imm_zext_sel = (opc_insn == `OR1K_OPCODE_ORI)  |
                        (opc_insn == `OR1K_OPCODE_ANDI) |
                        (opc_insn == `OR1K_OPCODE_SHRTI);


  assign imm_high     = {opc_imm16, 16'd0};
  assign imm_high_sel = op_movhi;


  wire [OPTION_OPERAND_WIDTH-1:0] immediate;
  assign immediate   = imm_sext_sel ? imm_sext :
                       imm_zext_sel ? imm_zext :
                                      imm_high;
  wire immediate_sel = imm_sext_sel | imm_zext_sel | imm_high_sel;



  wire op_rfe = (opc_insn == `OR1K_OPCODE_RFE);

  wire except_syscall = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                         (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                          `OR1K_SYSTRAPSYNC_OPC_SYSCALL);

  wire except_trap = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                      (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                       `OR1K_SYSTRAPSYNC_OPC_TRAP);




  reg attr_except_illegal;
  reg attr_op_1clk;
  reg attr_rfa1_req;
  reg attr_rfb1_req;
  reg attr_rfd1_we;
  reg attr_rfa2_req;
  reg attr_rfb2_req;

  always @(*) begin
    (* parallel_case *)
    case (opc_insn)
      `OR1K_OPCODE_J,
      `OR1K_OPCODE_JAL,
      `OR1K_OPCODE_JR,
      `OR1K_OPCODE_JALR,
      `OR1K_OPCODE_BNF,
      `OR1K_OPCODE_BF:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = op_jal;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = op_jal;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_MOVHI,
      `OR1K_OPCODE_RFE,
      `OR1K_OPCODE_NOP,
      `OR1K_OPCODE_CUST8:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = op_movhi;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = op_movhi;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_ADDI,
      `OR1K_OPCODE_ADDIC,
      `OR1K_OPCODE_ANDI,
      `OR1K_OPCODE_ORI,
      `OR1K_OPCODE_XORI,
      `OR1K_OPCODE_MULI,
      `OR1K_OPCODE_SF,
      `OR1K_OPCODE_SFIMM:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = (opc_insn != `OR1K_OPCODE_MULI);
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = (opc_insn == `OR1K_OPCODE_SF);
          attr_rfd1_we        = (opc_insn != `OR1K_OPCODE_SF) & (opc_insn != `OR1K_OPCODE_SFIMM);

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_MFSPR,
      `OR1K_OPCODE_LWZ,
      `OR1K_OPCODE_LWS,
      `OR1K_OPCODE_LBZ,
      `OR1K_OPCODE_LBS,
      `OR1K_OPCODE_LHZ,
      `OR1K_OPCODE_LHS,
      `OR1K_OPCODE_LWA:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = 1'b1;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_LD:
         begin
          attr_except_illegal = (OPTION_OPERAND_WIDTH != 64);
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = (OPTION_OPERAND_WIDTH == 64);

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
         end

      `OR1K_OPCODE_MTSPR,
      `OR1K_OPCODE_SW,
      `OR1K_OPCODE_SB,
      `OR1K_OPCODE_SH,
      `OR1K_OPCODE_SWA:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = 1'b1;
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_SD:
        begin
          attr_except_illegal = (OPTION_OPERAND_WIDTH != 64);
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfb1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_FPU:
        begin
          attr_except_illegal = ~(op_fpxx_arith_l | op_fpxx_cmp_l);
          attr_op_1clk        = 1'b0;
          if (op_fpxx_arith_l) begin
            attr_rfa1_req = 1'b1;
            attr_rfa2_req = op_fp64bit;
            if ((fetch_insn_i[2:0] == 3'd4) | (fetch_insn_i[2:0] == 3'd5)) begin
              attr_rfb1_req = 1'b0;
              attr_rfb2_req = 1'b0;
            end
            else begin
              attr_rfb1_req = 1'b1;
              attr_rfb2_req = op_fp64bit;
            end
            attr_rfd1_we = 1'b1;
          end
          else if (op_fpxx_cmp_l) begin

            attr_rfa1_req = 1'b1;
            attr_rfb1_req = 1'b1;
            attr_rfd1_we  = 1'b0;

            attr_rfa2_req = op_fp64bit;
            attr_rfb2_req = op_fp64bit;
          end
          else begin

            attr_rfa1_req = 1'b0;
            attr_rfb1_req = 1'b0;
            attr_rfd1_we  = 1'b0;

            attr_rfa2_req = 1'b0;
            attr_rfb2_req = 1'b0;
          end
        end

      `OR1K_OPCODE_SHRTI:
        begin
          (* parallel_case *)
          case (opc_shift)
            `OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
            `OR1K_ALU_OPC_SECONDARY_SHRT_SRL,
            `OR1K_ALU_OPC_SECONDARY_SHRT_SRA,
            `OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b1;
              end
            default:
              begin
                attr_except_illegal = 1'b1;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b0;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b0;
              end
          endcase

          attr_rfa2_req      = 1'b0;
          attr_rfb2_req      = 1'b0;
        end

      `OR1K_OPCODE_ALU:
        begin
          (* parallel_case *)
          case (opc_alu)
            `OR1K_ALU_OPC_EXTBH,
            `OR1K_ALU_OPC_EXTW,
            `OR1K_ALU_OPC_FFL1:
              begin
                attr_except_illegal = (OPTION_OPERAND_WIDTH == 64);
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_ADD,
            `OR1K_ALU_OPC_ADDC,
            `OR1K_ALU_OPC_SUB,
            `OR1K_ALU_OPC_OR,
            `OR1K_ALU_OPC_XOR,
            `OR1K_ALU_OPC_AND,
            `OR1K_ALU_OPC_CMOV:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b1;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_DIV,
            `OR1K_ALU_OPC_DIVU,
            `OR1K_ALU_OPC_MUL,
            `OR1K_ALU_OPC_MULU:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b1;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_SHRT:
              begin
                (* parallel_case *)
                case (opc_shift)
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SRL,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SRA,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
                    begin
                      attr_except_illegal = 1'b0;
                      attr_op_1clk        = 1'b1;
                      attr_rfa1_req       = 1'b1;
                      attr_rfb1_req       = 1'b1;
                      attr_rfd1_we        = 1'b1;
                    end
                  default:
                    begin
                      attr_except_illegal = 1'b1;
                      attr_op_1clk        = 1'b0;
                      attr_rfa1_req       = 1'b0;
                      attr_rfb1_req       = 1'b0;
                      attr_rfd1_we        = 1'b0;
                    end
                endcase
              end

            default:
              begin
                attr_except_illegal = 1'b1;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b0;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b0;
              end
          endcase

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_SYSTRAPSYNC: begin
        (* parallel_case *)
        case (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT])
          `OR1K_SYSTRAPSYNC_OPC_TRAP,
          `OR1K_SYSTRAPSYNC_OPC_SYSCALL:
            begin
              attr_except_illegal = 1'b0;
            end
          `OR1K_SYSTRAPSYNC_OPC_MSYNC:
            begin
              attr_except_illegal = 1'b0;
            end
          `OR1K_SYSTRAPSYNC_OPC_PSYNC:
            begin
              attr_except_illegal = 1'b1;
            end
          `OR1K_SYSTRAPSYNC_OPC_CSYNC:
            begin
              attr_except_illegal = 1'b1;
            end
          default:
            begin
              attr_except_illegal = 1'b1;
            end
        endcase
        attr_op_1clk      = 1'b0;
        attr_rfa1_req     = 1'b0;
        attr_rfb1_req     = 1'b0;
        attr_rfd1_we      = 1'b0;

        attr_rfa2_req     = 1'b0;
        attr_rfb2_req     = 1'b0;
      end

      default:
        begin
          attr_except_illegal = 1'b1;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end
    endcase
  end




  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  JAL_RFD1_ADR =  9;
  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  JAL_RFD2_ADR = 10;

  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  RST_RFD2_ADR =  1;









  wire op_jb_push_exec = (opc_insn == `OR1K_OPCODE_J)  | (opc_insn == `OR1K_OPCODE_JR) |
                         (opc_insn == `OR1K_OPCODE_BF) | (opc_insn == `OR1K_OPCODE_BNF);


  wire an_except_fd = fetch_an_except_i   |
                      attr_except_illegal | except_syscall | except_trap;


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin
      dcod_empty_o        <= 1'b1;
      dcod_op_1clk_o      <= 1'b0;
      dcod_op_muldiv_o    <= 1'b0;
      dcod_op_fpxx_any_o  <= 1'b0;
      dcod_op_lsu_any_o   <= 1'b0;
      dcod_op_mXspr_o     <= 1'b0;
      dcod_op_push_exec_o <= 1'b0;
      dcod_op_push_wrbk_o <= 1'b0;

      dcod_rfd1_we_o      <= 1'b0;
      dcod_rfd2_we_o      <= 1'b0;
      dcod_flag_we_o      <= 1'b0;
    end
    else if (padv_dcod_i) begin
      dcod_empty_o        <= (~fetch_valid_i);
      dcod_op_1clk_o      <= attr_op_1clk;
      dcod_op_muldiv_o    <= op_mul | op_div;
      dcod_op_fpxx_any_o  <= op_fpxx_arith | op_fpxx_cmp;
      dcod_op_lsu_any_o   <= op_lsu_load | op_lsu_store | op_msync;
      dcod_op_mXspr_o     <= op_mfspr | op_mtspr;
      dcod_op_push_exec_o <= an_except_fd | op_nop | op_rfe | op_jb_push_exec;
      dcod_op_push_wrbk_o <= an_except_fd | op_nop | op_rfe | op_msync;

      dcod_rfd1_we_o      <= attr_rfd1_we;
      dcod_rfd2_we_o      <= op_fpxx_arith & op_fp64bit;
      dcod_flag_we_o      <= op_setflag | op_fpxx_cmp | (opc_insn == `OR1K_OPCODE_SWA);
    end
    else if (padv_exec_i) begin
      dcod_empty_o        <= 1'b1;
      dcod_op_1clk_o      <= 1'b0;
      dcod_op_muldiv_o    <= 1'b0;
      dcod_op_fpxx_any_o  <= 1'b0;
      dcod_op_lsu_any_o   <= 1'b0;
      dcod_op_mXspr_o     <= 1'b0;
      dcod_op_push_exec_o <= 1'b0;
      dcod_op_push_wrbk_o <= 1'b0;

      dcod_rfd1_we_o      <= 1'b0;
      dcod_rfd2_we_o      <= 1'b0;
      dcod_flag_we_o      <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_delay_slot_o         <= fetch_delay_slot_i;

      dcod_rfd1_adr_o           <= op_jal ? JAL_RFD1_ADR : fetch_rfd1_adr_i;

      dcod_rfd2_adr_o           <= op_jal ? JAL_RFD2_ADR : fetch_rfd2_adr_i;

      dcod_immediate_o          <= immediate;
      dcod_immediate_sel_o      <= immediate_sel;

      dcod_imm16_o              <= imm16;
      dcod_op_lsu_load_o        <= op_lsu_load;
      dcod_op_lsu_store_o       <= op_lsu_store;
      dcod_op_lsu_atomic_o      <= op_lsu_atomic;
      dcod_lsu_length_o         <= lsu_length;
      dcod_lsu_zext_o           <= lsu_zext;
      dcod_op_msync_o           <= op_msync;

      dcod_flag_carry_req_o     <= op_cmov | adder_do_carry;

      dcod_op_add_o             <= op_add;
      dcod_adder_do_sub_o       <= adder_do_sub;
      dcod_adder_do_carry_o     <= adder_do_carry;

      dcod_op_shift_o           <= op_shift;
      dcod_opc_shift_o          <= {(opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SLL),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SRL),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SRA),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_ROR)};

      dcod_op_ffl1_o            <= op_ffl1;
      dcod_opc_ffl1_o           <= opc_ffl1;

      dcod_op_movhi_o           <= op_movhi;
      dcod_op_cmov_o            <= op_cmov;

      dcod_op_extsz_o           <= op_extsz;
      dcod_opc_extsz_o          <= opc_extsz;

      dcod_op_logic_o           <= |lut_logic;
      dcod_lut_logic_o          <= lut_logic;

      dcod_op_jal_o             <= op_jal;

      dcod_op_setflag_o         <= op_setflag;
      dcod_opc_setflag_o        <= fetch_insn_i[`OR1K_COMP_OPC_SELECT];

      dcod_op_mul_o             <= op_mul;

      dcod_op_div_o             <= op_div;
      dcod_op_div_signed_o      <= op_div_signed;
      dcod_op_div_unsigned_o    <= op_div_unsigned;

      dcod_op_fpxx_arith_o      <= op_fpxx_arith;
      dcod_op_fp64_arith_o      <= op_fp64bit;
      dcod_op_fpxx_add_o        <= op_fpxx_add;
      dcod_op_fpxx_sub_o        <= op_fpxx_sub;
      dcod_op_fpxx_mul_o        <= op_fpxx_mul;
      dcod_op_fpxx_div_o        <= op_fpxx_div;
      dcod_op_fpxx_i2f_o        <= op_fpxx_i2f;
      dcod_op_fpxx_f2i_o        <= op_fpxx_f2i;

      dcod_op_fpxx_cmp_o        <= op_fpxx_cmp;
      dcod_opc_fpxx_cmp_o       <= opc_fpxx_cmp;

      dcod_op_mtspr_o           <= op_mtspr;

      dcod_except_illegal_o     <= attr_except_illegal;
      dcod_except_syscall_o     <= except_syscall;
      dcod_except_trap_o        <= except_trap;

      dcod_an_except_fd_o       <= an_except_fd;

      dcod_op_rfe_o             <= op_rfe;

      pc_decode_o               <= pc_fetch_i;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_rfa1_req_o <= attr_rfa1_req;
      dcod_rfb1_req_o <= attr_rfb1_req;
      dcod_rfa2_req_o <= attr_rfa2_req;
      dcod_rfb2_req_o <= attr_rfb2_req;
    end
    else if (padv_exec_i) begin
      dcod_rfa1_req_o <= 1'b0;
      dcod_rfb1_req_o <= 1'b0;
      dcod_rfa2_req_o <= 1'b0;
      dcod_rfb2_req_o <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_rfa1_adr_o <= fetch_rfa1_adr_i;
      dcod_rfb1_adr_o <= fetch_rfb1_adr_i;
      dcod_rfa2_adr_o <= fetch_rfa2_adr_i;
      dcod_rfb2_adr_o <= fetch_rfb2_adr_i;
    end
  end

endmodule
module or1k_marocchino_decode
#(
  parameter OPTION_OPERAND_WIDTH = 32,
  parameter OPTION_RF_ADDR_WIDTH =  5,

  parameter FEATURE_PSYNC        = "NONE",
  parameter FEATURE_CSYNC        = "NONE"
)
(

  input                                 cpu_clk,


  input                                 padv_dcod_i,
  input                                 padv_exec_i,
  input                                 pipeline_flush_i,



  input                                 fetch_valid_i,

  input                                 fetch_an_except_i,

  input                                 fetch_delay_slot_i,

  input          [`OR1K_INSN_WIDTH-1:0] fetch_insn_i,

  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa2_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb2_adr_i,

  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfd1_adr_i,
  input      [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfd2_adr_i,


  output reg                            dcod_empty_o,
  output reg                            dcod_delay_slot_o,



  output reg                            dcod_rfa1_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfa1_adr_o,

  output reg                            dcod_rfb1_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfb1_adr_o,

  output reg                            dcod_rfa2_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfa2_adr_o,

  output reg                            dcod_rfb2_req_o,
  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfb2_adr_o,


  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfd1_adr_o,
  output reg                            dcod_rfd1_we_o,

  output reg [OPTION_RF_ADDR_WIDTH-1:0] dcod_rfd2_adr_o,
  output reg                            dcod_rfd2_we_o,


  input      [OPTION_OPERAND_WIDTH-1:0] pc_fetch_i,
  output reg [OPTION_OPERAND_WIDTH-1:0] pc_decode_o,


  output reg [OPTION_OPERAND_WIDTH-1:0] dcod_immediate_o,
  output reg                            dcod_immediate_sel_o,


  output reg                            dcod_flag_we_o,


  output reg      [`OR1K_IMM_WIDTH-1:0] dcod_imm16_o,
  output reg                            dcod_op_lsu_load_o,
  output reg                            dcod_op_lsu_store_o,
  output reg                            dcod_op_lsu_atomic_o,
  output reg                      [1:0] dcod_lsu_length_o,
  output reg                            dcod_lsu_zext_o,
  output reg                            dcod_op_msync_o,
  output reg                            dcod_op_lsu_any_o,


  output reg                            dcod_op_push_exec_o,

  output reg                            dcod_op_push_wrbk_o,


  output reg                            dcod_op_1clk_o,

  output reg                            dcod_flag_carry_req_o,

  output reg                            dcod_op_add_o,
  output reg                            dcod_adder_do_sub_o,
  output reg                            dcod_adder_do_carry_o,

  output reg                            dcod_op_shift_o,
  output reg                      [3:0] dcod_opc_shift_o,

  output reg                            dcod_op_ffl1_o,
  output reg                            dcod_opc_ffl1_o,

  output reg                            dcod_op_movhi_o,
  output reg                            dcod_op_cmov_o,

  output reg                            dcod_op_extsz_o,
  output reg                      [3:0] dcod_opc_extsz_o,

  output reg                            dcod_op_logic_o,
  output reg                      [3:0] dcod_lut_logic_o,

  output reg                            dcod_op_jal_o,

  output reg                            dcod_op_setflag_o,
  output reg [`OR1K_COMP_OPC_WIDTH-1:0] dcod_opc_setflag_o,


  output reg                            dcod_op_mul_o,


  output reg                            dcod_op_div_o,
  output reg                            dcod_op_div_signed_o,
  output reg                            dcod_op_div_unsigned_o,


  output reg                            dcod_op_muldiv_o,


  output reg                            dcod_op_fpxx_arith_o,
  output reg                            dcod_op_fp64_arith_o,
  output reg                            dcod_op_fpxx_add_o,
  output reg                            dcod_op_fpxx_sub_o,
  output reg                            dcod_op_fpxx_mul_o,
  output reg                            dcod_op_fpxx_div_o,
  output reg                            dcod_op_fpxx_i2f_o,
  output reg                            dcod_op_fpxx_f2i_o,


  output reg                                   dcod_op_fpxx_cmp_o,
  output reg [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] dcod_opc_fpxx_cmp_o,


  output reg                            dcod_op_fpxx_any_o,


  output reg                            dcod_op_mtspr_o,
  output reg                            dcod_op_mXspr_o,



  output reg                            dcod_except_illegal_o,
  output reg                            dcod_except_syscall_o,
  output reg                            dcod_except_trap_o,

  output reg                            dcod_an_except_fd_o,


  output reg                            dcod_op_rfe_o
);


  wire [OPTION_OPERAND_WIDTH-1:0] imm_sext;
  wire                            imm_sext_sel;
  wire [OPTION_OPERAND_WIDTH-1:0] imm_zext;
  wire                            imm_zext_sel;
  wire [OPTION_OPERAND_WIDTH-1:0] imm_high;
  wire                            imm_high_sel;


  wire [`OR1K_OPCODE_WIDTH-1:0]  opc_insn = fetch_insn_i[`OR1K_OPCODE_SELECT];








  wire op_lsu_load = (opc_insn == `OR1K_OPCODE_LWA) |
                     (opc_insn == `OR1K_OPCODE_LWZ) | (opc_insn == `OR1K_OPCODE_LWS) |
                     (opc_insn == `OR1K_OPCODE_LHZ) | (opc_insn == `OR1K_OPCODE_LHS) |
                     (opc_insn == `OR1K_OPCODE_LBZ) | (opc_insn == `OR1K_OPCODE_LBS) |
                     ((opc_insn == `OR1K_OPCODE_LD) & (OPTION_OPERAND_WIDTH == 64));


  wire op_lsu_store = (opc_insn == `OR1K_OPCODE_SWA) | (opc_insn == `OR1K_OPCODE_SW)  |
                      (opc_insn == `OR1K_OPCODE_SH)  | (opc_insn == `OR1K_OPCODE_SB)  |
                      ((opc_insn == `OR1K_OPCODE_SD) & (OPTION_OPERAND_WIDTH == 64));

  wire op_lsu_atomic = (opc_insn == `OR1K_OPCODE_LWA) | (opc_insn == `OR1K_OPCODE_SWA);



  reg [1:0] lsu_length;

  always @(opc_insn)
    (* parallel_case *)
    case (opc_insn)

      `OR1K_OPCODE_SB,
      `OR1K_OPCODE_LBZ,
      `OR1K_OPCODE_LBS: lsu_length = 2'b00;

      `OR1K_OPCODE_SH,
      `OR1K_OPCODE_LHZ,
      `OR1K_OPCODE_LHS: lsu_length = 2'b01;

      `OR1K_OPCODE_SW,
      `OR1K_OPCODE_SWA,
      `OR1K_OPCODE_LWZ,
      `OR1K_OPCODE_LWS,
      `OR1K_OPCODE_LWA: lsu_length = 2'b10;

      default:          lsu_length = 2'b10;
  endcase

  wire lsu_zext = opc_insn[0];

  wire op_msync = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                   (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                    `OR1K_SYSTRAPSYNC_OPC_MSYNC);



  wire op_nop = (opc_insn == `OR1K_OPCODE_NOP);



  wire op_mtspr = (opc_insn == `OR1K_OPCODE_MTSPR);
  wire op_mfspr = (opc_insn == `OR1K_OPCODE_MFSPR);



  wire op_setflag = (opc_insn == `OR1K_OPCODE_SF) |
                    (opc_insn == `OR1K_OPCODE_SFIMM);



  wire op_jal = (opc_insn == `OR1K_OPCODE_JALR) | (opc_insn == `OR1K_OPCODE_JAL);



  wire [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu  = fetch_insn_i[`OR1K_ALU_OPC_SELECT];
  wire op_alu = (opc_insn == `OR1K_OPCODE_ALU);



  wire op_add = (op_alu &
                 ((opc_alu == `OR1K_ALU_OPC_ADDC) |
                  (opc_alu == `OR1K_ALU_OPC_ADD)  |
                  (opc_alu == `OR1K_ALU_OPC_SUB))) |
                (opc_insn == `OR1K_OPCODE_ADDIC)   |
                (opc_insn == `OR1K_OPCODE_ADDI)    |
                op_jal;


  wire adder_do_sub = (op_alu & (opc_alu == `OR1K_ALU_OPC_SUB)) |
                      op_setflag;

  wire adder_do_carry = (op_alu & (opc_alu == `OR1K_ALU_OPC_ADDC)) |
                        (opc_insn == `OR1K_OPCODE_ADDIC);



  wire op_mul_signed   = (op_alu & (opc_alu == `OR1K_ALU_OPC_MUL)) |
                         (opc_insn == `OR1K_OPCODE_MULI);
  wire op_mul_unsigned = op_alu & (opc_alu == `OR1K_ALU_OPC_MULU);
  wire op_mul          = op_mul_signed | op_mul_unsigned;



  wire op_div_signed   = op_alu & (opc_alu == `OR1K_ALU_OPC_DIV);
  wire op_div_unsigned = op_alu & (opc_alu == `OR1K_ALU_OPC_DIVU);
  wire op_div          = op_div_signed | op_div_unsigned;



  wire op_shift = (op_alu & (opc_alu  == `OR1K_ALU_OPC_SHRT)) |
                  (opc_insn == `OR1K_OPCODE_SHRTI);
  wire [`OR1K_ALU_OPC_SECONDARY_WIDTH-1:0] opc_shift;
  assign opc_shift = fetch_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT];



  wire op_ffl1  = op_alu & (opc_alu  == `OR1K_ALU_OPC_FFL1);
  wire opc_ffl1 = fetch_insn_i[8];



  wire op_movhi = (opc_insn == `OR1K_OPCODE_MOVHI);
  wire op_cmov  = (op_alu & (opc_alu == `OR1K_ALU_OPC_CMOV));




  wire is_extw  = (opc_alu == `OR1K_ALU_OPC_EXTW);
  wire op_extsz = op_alu & ((opc_alu == `OR1K_ALU_OPC_EXTBH) |
                            is_extw);
  wire [3:0] opc_extsz = {is_extw, fetch_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]};



  wire [3:0] lut_logic;
  assign lut_logic =
    ((op_alu & (opc_alu == `OR1K_ALU_OPC_OR )) | (opc_insn == `OR1K_OPCODE_ORI )) ? 4'b1110 :
   (((op_alu & (opc_alu == `OR1K_ALU_OPC_XOR)) | (opc_insn == `OR1K_OPCODE_XORI)) ? 4'b0110 :
   (((op_alu & (opc_alu == `OR1K_ALU_OPC_AND)) | (opc_insn == `OR1K_OPCODE_ANDI)) ? 4'b1000 :
                                                                                    4'b0000));


  wire op_fpxx = (opc_insn == `OR1K_OPCODE_FPU);



  wire op_fp64bit = fetch_insn_i[`OR1K_FPUOP_DOUBLE_BIT];



  wire op_fpxx_arith_t = (~fetch_insn_i[3]);

  wire op_fpxx_arith_l = op_fpxx_arith_t & (fetch_insn_i[2:0] < 3'd6);

  wire op_fpxx_arith = op_fpxx_arith_l & op_fpxx;








  wire op_fpxx_add = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd0) & op_fpxx;
  wire op_fpxx_sub = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd1) & op_fpxx;
  wire op_fpxx_mul = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd2) & op_fpxx;
  wire op_fpxx_div = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd3) & op_fpxx;
  wire op_fpxx_i2f = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd4) & op_fpxx;
  wire op_fpxx_f2i = op_fpxx_arith_t & (fetch_insn_i[2:0] == 3'd5) & op_fpxx;



  wire op_fpxx_cmp_l = fetch_insn_i[3] & (fetch_insn_i[2:0] < 3'd7);

  wire op_fpxx_cmp = op_fpxx_cmp_l & op_fpxx;

















  wire [`OR1K_FPUOP_GENERIC_CMP_WIDTH:0] opc_fpxx_cmp;

  assign opc_fpxx_cmp = {fetch_insn_i[`OR1K_FPUOP_UNORDERED_CMP_BIT],
                         fetch_insn_i[`OR1K_FPUOP_GENERIC_CMP_SELECT]};


  wire [`OR1K_IMM_WIDTH-1:0] imm16;
  assign imm16 = (op_mtspr | op_lsu_store) ?
                  {fetch_insn_i[25:21],fetch_insn_i[10:0]} :
                  fetch_insn_i[`OR1K_IMM_SELECT];


  wire [`OR1K_IMM_WIDTH-1:0] opc_imm16 = fetch_insn_i[`OR1K_IMM_SELECT];



  assign imm_sext     = {{16{opc_imm16[15]}}, opc_imm16};
  assign imm_sext_sel = (opc_insn == `OR1K_OPCODE_ADDI)  |
                        (opc_insn == `OR1K_OPCODE_ADDIC) |
                        (opc_insn == `OR1K_OPCODE_XORI)  |
                        (opc_insn == `OR1K_OPCODE_MULI)  |
                        (opc_insn == `OR1K_OPCODE_SFIMM);



  assign imm_zext     = {16'd0, opc_imm16};
  assign imm_zext_sel = (opc_insn == `OR1K_OPCODE_ORI)  |
                        (opc_insn == `OR1K_OPCODE_ANDI) |
                        (opc_insn == `OR1K_OPCODE_SHRTI);


  assign imm_high     = {opc_imm16, 16'd0};
  assign imm_high_sel = op_movhi;


  wire [OPTION_OPERAND_WIDTH-1:0] immediate;
  assign immediate   = imm_sext_sel ? imm_sext :
                       imm_zext_sel ? imm_zext :
                                      imm_high;
  wire immediate_sel = imm_sext_sel | imm_zext_sel | imm_high_sel;



  wire op_rfe = (opc_insn == `OR1K_OPCODE_RFE);

  wire except_syscall = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                         (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                          `OR1K_SYSTRAPSYNC_OPC_SYSCALL);

  wire except_trap = (opc_insn == `OR1K_OPCODE_SYSTRAPSYNC) &
                      (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
                       `OR1K_SYSTRAPSYNC_OPC_TRAP);




  reg attr_except_illegal;
  reg attr_op_1clk;
  reg attr_rfa1_req;
  reg attr_rfb1_req;
  reg attr_rfd1_we;
  reg attr_rfa2_req;
  reg attr_rfb2_req;

  always @(*) begin
    (* parallel_case *)
    case (opc_insn)
      `OR1K_OPCODE_J,
      `OR1K_OPCODE_JAL,
      `OR1K_OPCODE_JR,
      `OR1K_OPCODE_JALR,
      `OR1K_OPCODE_BNF,
      `OR1K_OPCODE_BF:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = op_jal;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = op_jal;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_MOVHI,
      `OR1K_OPCODE_RFE,
      `OR1K_OPCODE_NOP,
      `OR1K_OPCODE_CUST8:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = op_movhi;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = op_movhi;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_ADDI,
      `OR1K_OPCODE_ADDIC,
      `OR1K_OPCODE_ANDI,
      `OR1K_OPCODE_ORI,
      `OR1K_OPCODE_XORI,
      `OR1K_OPCODE_MULI,
      `OR1K_OPCODE_SF,
      `OR1K_OPCODE_SFIMM:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = (opc_insn != `OR1K_OPCODE_MULI);
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = (opc_insn == `OR1K_OPCODE_SF);
          attr_rfd1_we        = (opc_insn != `OR1K_OPCODE_SF) & (opc_insn != `OR1K_OPCODE_SFIMM);

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_MFSPR,
      `OR1K_OPCODE_LWZ,
      `OR1K_OPCODE_LWS,
      `OR1K_OPCODE_LBZ,
      `OR1K_OPCODE_LBS,
      `OR1K_OPCODE_LHZ,
      `OR1K_OPCODE_LHS,
      `OR1K_OPCODE_LWA:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = 1'b1;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_LD:
         begin
          attr_except_illegal = (OPTION_OPERAND_WIDTH != 64);
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = (OPTION_OPERAND_WIDTH == 64);

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
         end

      `OR1K_OPCODE_MTSPR,
      `OR1K_OPCODE_SW,
      `OR1K_OPCODE_SB,
      `OR1K_OPCODE_SH,
      `OR1K_OPCODE_SWA:
        begin
          attr_except_illegal = 1'b0;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b1;
          attr_rfb1_req       = 1'b1;
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_SD:
        begin
          attr_except_illegal = (OPTION_OPERAND_WIDTH != 64);
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfb1_req       = (OPTION_OPERAND_WIDTH == 64);
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_FPU:
        begin
          attr_except_illegal = ~(op_fpxx_arith_l | op_fpxx_cmp_l);
          attr_op_1clk        = 1'b0;
          if (op_fpxx_arith_l) begin
            attr_rfa1_req = 1'b1;
            attr_rfa2_req = op_fp64bit;
            if ((fetch_insn_i[2:0] == 3'd4) | (fetch_insn_i[2:0] == 3'd5)) begin
              attr_rfb1_req = 1'b0;
              attr_rfb2_req = 1'b0;
            end
            else begin
              attr_rfb1_req = 1'b1;
              attr_rfb2_req = op_fp64bit;
            end
            attr_rfd1_we = 1'b1;
          end
          else if (op_fpxx_cmp_l) begin

            attr_rfa1_req = 1'b1;
            attr_rfb1_req = 1'b1;
            attr_rfd1_we  = 1'b0;

            attr_rfa2_req = op_fp64bit;
            attr_rfb2_req = op_fp64bit;
          end
          else begin

            attr_rfa1_req = 1'b0;
            attr_rfb1_req = 1'b0;
            attr_rfd1_we  = 1'b0;

            attr_rfa2_req = 1'b0;
            attr_rfb2_req = 1'b0;
          end
        end

      `OR1K_OPCODE_SHRTI:
        begin
          (* parallel_case *)
          case (opc_shift)
            `OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
            `OR1K_ALU_OPC_SECONDARY_SHRT_SRL,
            `OR1K_ALU_OPC_SECONDARY_SHRT_SRA,
            `OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b1;
              end
            default:
              begin
                attr_except_illegal = 1'b1;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b0;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b0;
              end
          endcase

          attr_rfa2_req      = 1'b0;
          attr_rfb2_req      = 1'b0;
        end

      `OR1K_OPCODE_ALU:
        begin
          (* parallel_case *)
          case (opc_alu)
            `OR1K_ALU_OPC_EXTBH,
            `OR1K_ALU_OPC_EXTW,
            `OR1K_ALU_OPC_FFL1:
              begin
                attr_except_illegal = (OPTION_OPERAND_WIDTH == 64);
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_ADD,
            `OR1K_ALU_OPC_ADDC,
            `OR1K_ALU_OPC_SUB,
            `OR1K_ALU_OPC_OR,
            `OR1K_ALU_OPC_XOR,
            `OR1K_ALU_OPC_AND,
            `OR1K_ALU_OPC_CMOV:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b1;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b1;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_DIV,
            `OR1K_ALU_OPC_DIVU,
            `OR1K_ALU_OPC_MUL,
            `OR1K_ALU_OPC_MULU:
              begin
                attr_except_illegal = 1'b0;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b1;
                attr_rfb1_req       = 1'b1;
                attr_rfd1_we        = 1'b1;
              end

            `OR1K_ALU_OPC_SHRT:
              begin
                (* parallel_case *)
                case (opc_shift)
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SRL,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_SRA,
                  `OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
                    begin
                      attr_except_illegal = 1'b0;
                      attr_op_1clk        = 1'b1;
                      attr_rfa1_req       = 1'b1;
                      attr_rfb1_req       = 1'b1;
                      attr_rfd1_we        = 1'b1;
                    end
                  default:
                    begin
                      attr_except_illegal = 1'b1;
                      attr_op_1clk        = 1'b0;
                      attr_rfa1_req       = 1'b0;
                      attr_rfb1_req       = 1'b0;
                      attr_rfd1_we        = 1'b0;
                    end
                endcase
              end

            default:
              begin
                attr_except_illegal = 1'b1;
                attr_op_1clk        = 1'b0;
                attr_rfa1_req       = 1'b0;
                attr_rfb1_req       = 1'b0;
                attr_rfd1_we        = 1'b0;
              end
          endcase

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end

      `OR1K_OPCODE_SYSTRAPSYNC: begin
        (* parallel_case *)
        case (fetch_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT])
          `OR1K_SYSTRAPSYNC_OPC_TRAP,
          `OR1K_SYSTRAPSYNC_OPC_SYSCALL:
            begin
              attr_except_illegal = 1'b0;
            end
          `OR1K_SYSTRAPSYNC_OPC_MSYNC:
            begin
              attr_except_illegal = 1'b0;
            end
          `OR1K_SYSTRAPSYNC_OPC_PSYNC:
            begin
              attr_except_illegal = 1'b1;
            end
          `OR1K_SYSTRAPSYNC_OPC_CSYNC:
            begin
              attr_except_illegal = 1'b1;
            end
          default:
            begin
              attr_except_illegal = 1'b1;
            end
        endcase
        attr_op_1clk      = 1'b0;
        attr_rfa1_req     = 1'b0;
        attr_rfb1_req     = 1'b0;
        attr_rfd1_we      = 1'b0;

        attr_rfa2_req     = 1'b0;
        attr_rfb2_req     = 1'b0;
      end

      default:
        begin
          attr_except_illegal = 1'b1;
          attr_op_1clk        = 1'b0;
          attr_rfa1_req       = 1'b0;
          attr_rfb1_req       = 1'b0;
          attr_rfd1_we        = 1'b0;

          attr_rfa2_req       = 1'b0;
          attr_rfb2_req       = 1'b0;
        end
    endcase
  end




  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  JAL_RFD1_ADR =  9;
  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  JAL_RFD2_ADR = 10;

  localparam [(OPTION_RF_ADDR_WIDTH-1):0]  RST_RFD2_ADR =  1;









  wire op_jb_push_exec = (opc_insn == `OR1K_OPCODE_J)  | (opc_insn == `OR1K_OPCODE_JR) |
                         (opc_insn == `OR1K_OPCODE_BF) | (opc_insn == `OR1K_OPCODE_BNF);


  wire an_except_fd = fetch_an_except_i   |
                      attr_except_illegal | except_syscall | except_trap;


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin
      dcod_empty_o        <= 1'b1;
      dcod_op_1clk_o      <= 1'b0;
      dcod_op_muldiv_o    <= 1'b0;
      dcod_op_fpxx_any_o  <= 1'b0;
      dcod_op_lsu_any_o   <= 1'b0;
      dcod_op_mXspr_o     <= 1'b0;
      dcod_op_push_exec_o <= 1'b0;
      dcod_op_push_wrbk_o <= 1'b0;

      dcod_rfd1_we_o      <= 1'b0;
      dcod_rfd2_we_o      <= 1'b0;
      dcod_flag_we_o      <= 1'b0;
    end
    else if (padv_dcod_i) begin
      dcod_empty_o        <= (~fetch_valid_i);
      dcod_op_1clk_o      <= attr_op_1clk;
      dcod_op_muldiv_o    <= op_mul | op_div;
      dcod_op_fpxx_any_o  <= op_fpxx_arith | op_fpxx_cmp;
      dcod_op_lsu_any_o   <= op_lsu_load | op_lsu_store | op_msync;
      dcod_op_mXspr_o     <= op_mfspr | op_mtspr;
      dcod_op_push_exec_o <= an_except_fd | op_nop | op_rfe | op_jb_push_exec;
      dcod_op_push_wrbk_o <= an_except_fd | op_nop | op_rfe | op_msync;

      dcod_rfd1_we_o      <= attr_rfd1_we;
      dcod_rfd2_we_o      <= op_fpxx_arith & op_fp64bit;
      dcod_flag_we_o      <= op_setflag | op_fpxx_cmp | (opc_insn == `OR1K_OPCODE_SWA);
    end
    else if (padv_exec_i) begin
      dcod_empty_o        <= 1'b1;
      dcod_op_1clk_o      <= 1'b0;
      dcod_op_muldiv_o    <= 1'b0;
      dcod_op_fpxx_any_o  <= 1'b0;
      dcod_op_lsu_any_o   <= 1'b0;
      dcod_op_mXspr_o     <= 1'b0;
      dcod_op_push_exec_o <= 1'b0;
      dcod_op_push_wrbk_o <= 1'b0;

      dcod_rfd1_we_o      <= 1'b0;
      dcod_rfd2_we_o      <= 1'b0;
      dcod_flag_we_o      <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_delay_slot_o         <= fetch_delay_slot_i;

      dcod_rfd1_adr_o           <= op_jal ? JAL_RFD1_ADR : fetch_rfd1_adr_i;

      dcod_rfd2_adr_o           <= op_jal ? JAL_RFD2_ADR : fetch_rfd2_adr_i;

      dcod_immediate_o          <= immediate;
      dcod_immediate_sel_o      <= immediate_sel;

      dcod_imm16_o              <= imm16;
      dcod_op_lsu_load_o        <= op_lsu_load;
      dcod_op_lsu_store_o       <= op_lsu_store;
      dcod_op_lsu_atomic_o      <= op_lsu_atomic;
      dcod_lsu_length_o         <= lsu_length;
      dcod_lsu_zext_o           <= lsu_zext;
      dcod_op_msync_o           <= op_msync;

      dcod_flag_carry_req_o     <= op_cmov | adder_do_carry;

      dcod_op_add_o             <= op_add;
      dcod_adder_do_sub_o       <= adder_do_sub;
      dcod_adder_do_carry_o     <= adder_do_carry;

      dcod_op_shift_o           <= op_shift;
      dcod_opc_shift_o          <= {(opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SLL),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SRL),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_SRA),
                                    (opc_shift == `OR1K_ALU_OPC_SECONDARY_SHRT_ROR)};

      dcod_op_ffl1_o            <= op_ffl1;
      dcod_opc_ffl1_o           <= opc_ffl1;

      dcod_op_movhi_o           <= op_movhi;
      dcod_op_cmov_o            <= op_cmov;

      dcod_op_extsz_o           <= op_extsz;
      dcod_opc_extsz_o          <= opc_extsz;

      dcod_op_logic_o           <= |lut_logic;
      dcod_lut_logic_o          <= lut_logic;

      dcod_op_jal_o             <= op_jal;

      dcod_op_setflag_o         <= op_setflag;
      dcod_opc_setflag_o        <= fetch_insn_i[`OR1K_COMP_OPC_SELECT];

      dcod_op_mul_o             <= op_mul;

      dcod_op_div_o             <= op_div;
      dcod_op_div_signed_o      <= op_div_signed;
      dcod_op_div_unsigned_o    <= op_div_unsigned;

      dcod_op_fpxx_arith_o      <= op_fpxx_arith;
      dcod_op_fp64_arith_o      <= op_fp64bit;
      dcod_op_fpxx_add_o        <= op_fpxx_add;
      dcod_op_fpxx_sub_o        <= op_fpxx_sub;
      dcod_op_fpxx_mul_o        <= op_fpxx_mul;
      dcod_op_fpxx_div_o        <= op_fpxx_div;
      dcod_op_fpxx_i2f_o        <= op_fpxx_i2f;
      dcod_op_fpxx_f2i_o        <= op_fpxx_f2i;

      dcod_op_fpxx_cmp_o        <= op_fpxx_cmp;
      dcod_opc_fpxx_cmp_o       <= opc_fpxx_cmp;

      dcod_op_mtspr_o           <= op_mtspr;

      dcod_except_illegal_o     <= attr_except_illegal;
      dcod_except_syscall_o     <= except_syscall;
      dcod_except_trap_o        <= except_trap;

      dcod_an_except_fd_o       <= an_except_fd;

      dcod_op_rfe_o             <= op_rfe;

      pc_decode_o               <= pc_fetch_i;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_rfa1_req_o <= attr_rfa1_req;
      dcod_rfb1_req_o <= attr_rfb1_req;
      dcod_rfa2_req_o <= attr_rfa2_req;
      dcod_rfb2_req_o <= attr_rfb2_req;
    end
    else if (padv_exec_i) begin
      dcod_rfa1_req_o <= 1'b0;
      dcod_rfb1_req_o <= 1'b0;
      dcod_rfa2_req_o <= 1'b0;
      dcod_rfb2_req_o <= 1'b0;
    end
  end


  always @(posedge cpu_clk) begin
    if (padv_dcod_i) begin
      dcod_rfa1_adr_o <= fetch_rfa1_adr_i;
      dcod_rfb1_adr_o <= fetch_rfb1_adr_i;
      dcod_rfa2_adr_o <= fetch_rfa2_adr_i;
      dcod_rfb2_adr_o <= fetch_rfb2_adr_i;
    end
  end

endmodule