data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/compare/compare.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/compare/compare.v:26: Cannot find file containing module: 'ADD'\n ADD \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/compare,data/full_repos/permissive/486954482/ADD\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/compare,data/full_repos/permissive/486954482/ADD.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/compare,data/full_repos/permissive/486954482/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: Exiting due to 1 error(s)\n"
module compare
#(
	parameter N=16384,
	parameter CC=1
)
(
	clk,
	rst,
	g_input,
	e_input,
	o
);
	localparam M = N/CC; 

	input clk;
	input rst;
	input[M-1:0] g_input;
	input[M-1:0] e_input;
	output o;

	reg ci;
	wire co;
	
	ADD 
	#(
		.N(M)
	) 
	UCOMP 
	(
		.A(g_input), 
		.B(~e_input), 
		.CI(ci),
		.S(),
		.CO(co)
	);

	assign o = co;
	
	generate
	if(CC>1)
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				ci <= 1'b1;
			end
			else
			begin
				ci <= co;	
			end
		end
	else
		always@(*)
		begin
			ci <= 1'b1;
		end
	endgenerate

endmodule
module compare
#(
	parameter N=16384,
	parameter CC=1
)
(
	clk,
	rst,
	g_input,
	e_input,
	o
);

	localparam M = N/CC; 

	input clk;
	input rst;
	input[M-1:0] g_input;
	input[M-1:0] e_input;
	output o;

	reg ci;
	wire co;
	
	ADD 
	#(
		.N(M)
	) 
	UCOMP 
	(
		.A(g_input), 
		.B(~e_input), 
		.CI(ci),
		.S(),
		.CO(co)
	);

	assign o = co;
	
	generate
	if(CC>1)
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				ci <= 1'b1;
			end
			else
			begin
				ci <= co;	
			end
		end
	else
		always@(*)
		begin
			ci <= 1'b1;
		end
	endgenerate

endmodule