data/full_repos/permissive/410821791/Read_16x8.v
data/verilator_xmls/7273e82f-7268-465b-9284-462713e4bb69.xml
module rout (
    output rout,
    input a, b, bin, qs, app
);
    assign rout = app ? (qs&(a^b^bin) | ~qs&a) : (qs&(a|b^bin) | ~qs&a);
endmodule
module rout (
    output rout,
    input a, b, bin, qs, app
);

    assign rout = app ? (qs&(a^b^bin) | ~qs&a) : (qs&(a|b^bin) | ~qs&a);
endmodule