data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:12: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'$_DFF_N_\'\nmodule \\$_DFF_N_ (input D, C, output Q);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'$_DFF_P_\'\nmodule \\$_DFF_P_ (input D, C, output Q);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_PP_\'\nmodule \\$_DFFE_PP_ (input D, C, E, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_NP_\'\nmodule \\$_DFFE_NP_ (input D, C, E, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFF_PP0_\'\nmodule \\$_SDFF_PP0_ (input D, C, R, output Q);\n       ^~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFF_NP0_\'\nmodule \\$_SDFF_NP0_ (input D, C, R, output Q);\n       ^~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFFE_PP0P_\'\nmodule \\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFFE_NP0P_\'\nmodule \\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFF_PP1_\'\nmodule \\$_SDFF_PP1_ (input D, C, R, output Q);\n       ^~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFF_NP1_\'\nmodule \\$_SDFF_NP1_ (input D, C, R, output Q);\n       ^~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFFE_PP1P_\'\nmodule \\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_SDFFE_NP1P_\'\nmodule \\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFF_PP1_\'\nmodule \\$_DFF_PP1_ (input D, C, R, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFF_NP1_\'\nmodule \\$_DFF_NP1_ (input D, C, R, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFF_PP0_\'\nmodule \\$_DFF_PP0_ (input D, C, R, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFF_NP0_\'\nmodule \\$_DFF_NP0_ (input D, C, R, output Q);\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_PP1P_\'\nmodule \\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_NP1P_\'\nmodule \\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_PP0P_\'\nmodule \\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                       : ... Top module \'$_DFFE_NP0P_\'\nmodule \\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                       : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:130: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WIDTH-1:0] A;\n       ^\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:121: Cannot find file containing module: \'DFFNCE\'\n DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/gowin,data/full_repos/permissive/460468583/DFFNCE\n             data/full_repos/permissive/460468583/data/yosys/gowin,data/full_repos/permissive/460468583/DFFNCE.v\n             data/full_repos/permissive/460468583/data/yosys/gowin,data/full_repos/permissive/460468583/DFFNCE.sv\n             DFFNCE\n             DFFNCE.v\n             DFFNCE.sv\n             obj_dir/DFFNCE\n             obj_dir/DFFNCE.v\n             obj_dir/DFFNCE.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:115: Cannot find file containing module: \'DFFCE\'\n DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:109: Cannot find file containing module: \'DFFNPE\'\n DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:103: Cannot find file containing module: \'DFFPE\'\n DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:97: Cannot find file containing module: \'DFFNC\'\n DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:91: Cannot find file containing module: \'DFFC\'\n DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:85: Cannot find file containing module: \'DFFNP\'\n DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:79: Cannot find file containing module: \'DFFP\'\n DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:73: Cannot find file containing module: \'DFFNSE\'\n DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:67: Cannot find file containing module: \'DFFSE\'\n DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:61: Cannot find file containing module: \'DFFNS\'\n DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:55: Cannot find file containing module: \'DFFS\'\n DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:49: Cannot find file containing module: \'DFFNRE\'\n DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:43: Cannot find file containing module: \'DFFRE\'\n DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:37: Cannot find file containing module: \'DFFNR\'\n DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:31: Cannot find file containing module: \'DFFR\'\n DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:25: Cannot find file containing module: \'DFFNE\'\n DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:19: Cannot find file containing module: \'DFFE\'\n DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:13: Cannot find file containing module: \'DFF\'\n DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n ^~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gowin/cells_map.v:7: Cannot find file containing module: \'DFFN\'\n DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n ^~~~\n%Error: Exiting due to 20 error(s), 2 warning(s)\n'
module \$lut (A, Y);
	parameter WIDTH = 0;
	parameter LUT = 0;

	(* force_downto *)
	input [WIDTH-1:0] A;
	output Y;

	generate
		if (WIDTH == 1) begin
			LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]));
		end else
		if (WIDTH == 2) begin
			LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]));
		end else
		if (WIDTH == 3) begin
			LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]), .I2(A[2]));
		end else
		if (WIDTH == 4) begin
			LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
		end else
		if (WIDTH == 5) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
			\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
			MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
		end else
		if (WIDTH == 6) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
			\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
			MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
		end else
		if (WIDTH == 7) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
			\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
			MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
		end else
		if (WIDTH == 8) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
			\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
			MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
		end else begin
			wire _TECHMAP_FAIL_ = 1;
		end
	endgenerate
endmodule
module \$lut (A, Y);

	parameter WIDTH = 0;
	parameter LUT = 0;

	(* force_downto *)
	input [WIDTH-1:0] A;
	output Y;

	generate
		if (WIDTH == 1) begin
			LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]));
		end else
		if (WIDTH == 2) begin
			LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]));
		end else
		if (WIDTH == 3) begin
			LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]), .I2(A[2]));
		end else
		if (WIDTH == 4) begin
			LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
				.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
		end else
		if (WIDTH == 5) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
			\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
			MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
		end else
		if (WIDTH == 6) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
			\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
			MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
		end else
		if (WIDTH == 7) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
			\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
			MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
		end else
		if (WIDTH == 8) begin
			wire f0, f1;
			\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
			\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
			MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
		end else begin
			wire _TECHMAP_FAIL_ = 1;
		end
	endgenerate
endmodule