data/full_repos/permissive/521867481/testbench/Uart8_tb.v
1: b'%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:3: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:4: Cannot find include file: src/Uart8.v\n`include "src/Uart8.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:8: Define or directive not defined: \'`CLOCK_RATE_100MHZ\'\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:8: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                                            ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:9: Define or directive not defined: \'`BAUD_RATE_115200\'\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:9: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                                           ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:10: Define or directive not defined: \'`OVERSAMPLING_16\'\n parameter OVERSAMPLING = `OVERSAMPLING_16;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter OVERSAMPLING = `OVERSAMPLING_16;\n                                          ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:11: Define or directive not defined: \'`DATA_BITS_8\'\n parameter DATA_BITS    = `DATA_BITS_8;\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter DATA_BITS    = `DATA_BITS_8;\n                                      ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:63: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:64: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX txStart <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX txStart <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX rx = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX txStart <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX txStart <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #0.5 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #50000 $finish;\n  ^\n%Error: Exiting due to 12 error(s), 46 warning(s)\n'
module tbUart8();

	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter OVERSAMPLING = `OVERSAMPLING_16;
	parameter DATA_BITS    = `DATA_BITS_8;





	localparam CLOCK_RX = CLOCK_RATE / BAUD_RATE;
	localparam CLOCK_TX = CLOCK_RATE / BAUD_RATE;

	reg clk = 0;
	wire [DATA_BITS - 1:0] in;
	wire [DATA_BITS - 1:0] out;


	reg rx = 1;
	reg rxEn = 1;
	wire rxDone;
	wire rxBusy;
	wire rxErr;


	wire tx;
	reg txEn = 1;
	reg txStart = 0;
	wire txDone;
	wire txBusy;

	assign in = out;

	Uart8 #(
        .CLOCK_RATE(CLOCK_RATE),
        .BAUD_RATE(BAUD_RATE),
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
	) test (
		.clk(clk),
        .rx(rx),
        .rxEn(rxEn),
        .out(out),
        .rxDone(rxDone),
        .rxBusy(rxBusy),
        .rxErr(rxErr),

        .tx(tx),
        .txEn(txEn),
        .txStart(txStart),
        .in(in),
        .txDone(txDone),
        .txBusy(txBusy)
	);

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin

			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 1;


			#CLOCK_TX txStart <= 1'b1;
			#CLOCK_TX txStart <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end

		begin

			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;

			#CLOCK_RX rx = 1;


			#CLOCK_TX txStart <= 1'b1;
			#CLOCK_TX txStart <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end
	end

	always begin
		#0.5 clk = ~clk;
	end

	initial begin
		#50000 $finish;
	end

endmodule
module tbUart8();


	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter OVERSAMPLING = `OVERSAMPLING_16;
	parameter DATA_BITS    = `DATA_BITS_8;





	localparam CLOCK_RX = CLOCK_RATE / BAUD_RATE;
	localparam CLOCK_TX = CLOCK_RATE / BAUD_RATE;

	reg clk = 0;
	wire [DATA_BITS - 1:0] in;
	wire [DATA_BITS - 1:0] out;


	reg rx = 1;
	reg rxEn = 1;
	wire rxDone;
	wire rxBusy;
	wire rxErr;


	wire tx;
	reg txEn = 1;
	reg txStart = 0;
	wire txDone;
	wire txBusy;

	assign in = out;

	Uart8 #(
        .CLOCK_RATE(CLOCK_RATE),
        .BAUD_RATE(BAUD_RATE),
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
	) test (
		.clk(clk),
        .rx(rx),
        .rxEn(rxEn),
        .out(out),
        .rxDone(rxDone),
        .rxBusy(rxBusy),
        .rxErr(rxErr),

        .tx(tx),
        .txEn(txEn),
        .txStart(txStart),
        .in(in),
        .txDone(txDone),
        .txBusy(txBusy)
	);

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin

			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 1;


			#CLOCK_TX txStart <= 1'b1;
			#CLOCK_TX txStart <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end

		begin

			#CLOCK_RX rx = 0;

			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 0;
			#CLOCK_RX rx = 1;

			#CLOCK_RX rx = 1;


			#CLOCK_TX txStart <= 1'b1;
			#CLOCK_TX txStart <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end
	end

	always begin
		#0.5 clk = ~clk;
	end

	initial begin
		#50000 $finish;
	end

endmodule