data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v
data/verilator_xmls/299f1d6a-0a1b-4cd6-b4b1-808a617b8a38.xml
module gated_clk_cell(
  clk_in,
  global_en,
  module_en,
  local_en,
  external_en,
  pad_yy_icg_scan_en,
  clk_out
);

input  clk_in;
input  global_en;
input  module_en;
input  local_en;
input  external_en;
input  pad_yy_icg_scan_en;
output clk_out;

wire   clk_en_bf_latch;
wire   SE;

assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;


assign SE	       = pad_yy_icg_scan_en;






assign clk_out = clk_in;

endmodule
module gated_clk_cell(
  clk_in,
  global_en,
  module_en,
  local_en,
  external_en,
  pad_yy_icg_scan_en,
  clk_out
);


input  clk_in;
input  global_en;
input  module_en;
input  local_en;
input  external_en;
input  pad_yy_icg_scan_en;
output clk_out;

wire   clk_en_bf_latch;
wire   SE;

assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;


assign SE	       = pad_yy_icg_scan_en;






assign clk_out = clk_in;

endmodule