data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:51: Cannot find file containing module: 'Dmx4to16'\n  Dmx4to16 readEnDmx(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Dmx4to16\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Dmx4to16.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Dmx4to16.sv\n             Dmx4to16\n             Dmx4to16.v\n             Dmx4to16.sv\n             obj_dir/Dmx4to16\n             obj_dir/Dmx4to16.v\n             obj_dir/Dmx4to16.sv\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:60: Cannot find file containing module: 'Dmx4to16'\n  Dmx4to16 writeEnDmx(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:71: Cannot find file containing module: 'SyzFETRegister3Out'\n  SyzFETRegister3Out regInstr(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:89: Cannot find file containing module: 'SyzFETRegister2Out'\n  SyzFETRegister2Out regStatus(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:105: Cannot find file containing module: 'SyzFETRegister3Out'\n  SyzFETRegister3Out regDataIn(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:125: Cannot find file containing module: 'SyzFETRegister2Out'\n  SyzFETRegister2Out regDataOut(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:141: Cannot find file containing module: 'SyzFETRegister3Out'\n  SyzFETRegister3Out regAddrLSB(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:151: Cannot find file containing module: 'SyzFETRegister3Out'\n  SyzFETRegister3Out regAddrMSB(\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:163: Cannot find file containing module: 'Or32B5Way'\n  Or32B5Way dOutOr(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:173: Cannot find file containing module: 'Mux16B8to1'\n  Mux16B8to1 sdIntDbgSel(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SDInterface.v:187: Cannot find file containing module: 'SDController'\n  SDController controller(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module SDInterface(
    

    input cpuClock,
    

    input periphSelect,
    input [3:0] regSelect,
    input readEn,
    input writeEn,
    input reset,
    input [31:0] dIn,
    input exec,
    

    input miso,
    input [4:0] debugRegSelect,
    output serialClockOut,
    output [31:0] dOut,
    output chipSel,
    output mosi,
    output [15:0] debugOut,
    output [15:0] debugControllerOut
  );



  wire [15:0] wReadEnSignals;
  Dmx4to16 readEnDmx(
    .sel(regSelect[3:0]),
    .en(periphSelect & readEn),
    .out(wReadEnSignals[15:0])
  );
  


  wire [15:0] wWriteEnSignals;
  Dmx4to16 writeEnDmx(
    .sel(regSelect[3:0]),
    .en(periphSelect & writeEn),
    .out(wWriteEnSignals[15:0])
  );
  


  wire [15:0] wR0Output;
  wire [15:0] wR0InstrOut;
  wire [15:0] wR0DebugOut;
  SyzFETRegister3Out regInstr(
   .dIn(dIn[15:0]),
   .clockSig(cpuClock),
   .read(wReadEnSignals[0]),
   .write(wWriteEnSignals[0]),
   .reset(reset),
   .dOut(wR0Output[15:0]),
   .dOut2(wR0InstrOut[15:0]),
   .debugOut(wR0DebugOut[15:0])
  );
  


  wire [2:0] wR1StatusIn;
  wire wSetR1;
  wire wEnR1Write;
  wire [15:0] wR1Output;
  wire [15:0] wR1DebugOut;
  SyzFETRegister2Out regStatus(
   .dIn({13'b0000000000000, wR1StatusIn[2:0]}),
   .clockSig(wSetR1),
   .read(wReadEnSignals[1]),
   .write(wEnR1Write),
   .reset(reset),
   .dOut(wR1Output[15:0]),
   .debugOut(wR1DebugOut[15:0])
  );
  



  wire [15:0] wR2Output;
  wire [15:0] wR2DataOut;
  wire [15:0] wR2DebugOut;
  SyzFETRegister3Out regDataIn(
   .dIn(dIn[15:0]),
   .clockSig(cpuClock),
   .read(wReadEnSignals[2]),
   .write(wWriteEnSignals[2]),
   .reset(reset),
   .dOut(wR2Output[15:0]),
   .dOut2(wR2DataOut[15:0]),
   .debugOut(wR2DebugOut[15:0])
  );
  




  wire [15:0] wR3DataOutIn;
  wire wSetR3;
  wire wEnR3Write;
  wire [15:0] wR3Output;
  wire [15:0] wR3DebugOut;
  SyzFETRegister2Out regDataOut(
   .dIn(wR3DataOutIn[15:0]),
   .clockSig(wSetR3),
   .read(wReadEnSignals[3]),
   .write(wEnR3Write),
   .reset(reset),
   .dOut(wR3Output[15:0]),
   .debugOut(wR3DebugOut[15:0])
  );
  



  wire [31:0] wR4Output;
  wire [31:0] wR4AddrOut;
  wire [15:0] wR4DebugOut;
  SyzFETRegister3Out regAddrLSB(
    .dIn(dIn[15:0]),
    .clockSig(cpuClock),
    .read(wReadEnSignals[4]),
    .write(wWriteEnSignals[4]),
    .reset(reset),
    .dOut(wR4Output[15:0]),
    .dOut2(wR4AddrOut[15:0]),
    .debugOut(wR4DebugOut[15:0])
  );
  SyzFETRegister3Out regAddrMSB(
    .dIn(dIn[31:16]),
    .clockSig(cpuClock),
    .read(wReadEnSignals[4]),
    .write(wWriteEnSignals[4]),
    .reset(reset),
    .dOut(wR4Output[31:16]),
    .dOut2(wR4AddrOut[31:16]),
    .debugOut()
  );
  

  Or32B5Way dOutOr(
    .aIn({16'h0000, wR0Output[15:0]}),
    .bIn({16'h0000, wR1Output[15:0]}),
    .cIn({16'h0000, wR2Output[15:0]}),
    .dIn({16'h0000, wR3Output[15:0]}),
    .eIn(wR4Output[31:0]),
    .dOut(dOut[31:0])
  );
  

  Mux16B8to1 sdIntDbgSel(
    .dIn0(wR0DebugOut[15:0]),
    .dIn1(wR1DebugOut[15:0]),
    .dIn2(wR2DebugOut[15:0]),
    .dIn3(wR3DebugOut[15:0]),
    .dIn4(wR4DebugOut[15:0]),
    .dIn5(16'h0000),
    .dIn6(16'h0000),
    .dIn7(16'h0000),
    .sel(debugRegSelect[2:0]),
    .dOut(debugOut[15:0])
  );
  

  SDController controller(
    .ctrlClk(cpuClock),
    .addr(wR4AddrOut[31:0]),
    .dIn(wR2DataOut[15:0]),
    .op(wR0InstrOut[15:0]),
    .exec(exec),
    .reset(reset),
    .miso(miso),
    .debugRegSelect(debugRegSelect[3:0]),
    .serialClockOut(serialClockOut),
    .status(wR1StatusIn[2:0]),
    .updateStatus(wEnR1Write),
    .clkR1(wSetR1),
    .dOut(wR3DataOutIn[15:0]),
    .updateDataOut(wEnR3Write),
    .clkR3(wSetR3),
    .chipSelect(chipSel),
    .mosi(mosi),
    .debugOut(debugControllerOut[15:0])
  );
  
endmodule
module SDInterface(
    

    input cpuClock,
    

    input periphSelect,
    input [3:0] regSelect,
    input readEn,
    input writeEn,
    input reset,
    input [31:0] dIn,
    input exec,
    

    input miso,
    input [4:0] debugRegSelect,
    output serialClockOut,
    output [31:0] dOut,
    output chipSel,
    output mosi,
    output [15:0] debugOut,
    output [15:0] debugControllerOut
  );




  wire [15:0] wReadEnSignals;
  Dmx4to16 readEnDmx(
    .sel(regSelect[3:0]),
    .en(periphSelect & readEn),
    .out(wReadEnSignals[15:0])
  );
  


  wire [15:0] wWriteEnSignals;
  Dmx4to16 writeEnDmx(
    .sel(regSelect[3:0]),
    .en(periphSelect & writeEn),
    .out(wWriteEnSignals[15:0])
  );
  


  wire [15:0] wR0Output;
  wire [15:0] wR0InstrOut;
  wire [15:0] wR0DebugOut;
  SyzFETRegister3Out regInstr(
   .dIn(dIn[15:0]),
   .clockSig(cpuClock),
   .read(wReadEnSignals[0]),
   .write(wWriteEnSignals[0]),
   .reset(reset),
   .dOut(wR0Output[15:0]),
   .dOut2(wR0InstrOut[15:0]),
   .debugOut(wR0DebugOut[15:0])
  );
  


  wire [2:0] wR1StatusIn;
  wire wSetR1;
  wire wEnR1Write;
  wire [15:0] wR1Output;
  wire [15:0] wR1DebugOut;
  SyzFETRegister2Out regStatus(
   .dIn({13'b0000000000000, wR1StatusIn[2:0]}),
   .clockSig(wSetR1),
   .read(wReadEnSignals[1]),
   .write(wEnR1Write),
   .reset(reset),
   .dOut(wR1Output[15:0]),
   .debugOut(wR1DebugOut[15:0])
  );
  



  wire [15:0] wR2Output;
  wire [15:0] wR2DataOut;
  wire [15:0] wR2DebugOut;
  SyzFETRegister3Out regDataIn(
   .dIn(dIn[15:0]),
   .clockSig(cpuClock),
   .read(wReadEnSignals[2]),
   .write(wWriteEnSignals[2]),
   .reset(reset),
   .dOut(wR2Output[15:0]),
   .dOut2(wR2DataOut[15:0]),
   .debugOut(wR2DebugOut[15:0])
  );
  




  wire [15:0] wR3DataOutIn;
  wire wSetR3;
  wire wEnR3Write;
  wire [15:0] wR3Output;
  wire [15:0] wR3DebugOut;
  SyzFETRegister2Out regDataOut(
   .dIn(wR3DataOutIn[15:0]),
   .clockSig(wSetR3),
   .read(wReadEnSignals[3]),
   .write(wEnR3Write),
   .reset(reset),
   .dOut(wR3Output[15:0]),
   .debugOut(wR3DebugOut[15:0])
  );
  



  wire [31:0] wR4Output;
  wire [31:0] wR4AddrOut;
  wire [15:0] wR4DebugOut;
  SyzFETRegister3Out regAddrLSB(
    .dIn(dIn[15:0]),
    .clockSig(cpuClock),
    .read(wReadEnSignals[4]),
    .write(wWriteEnSignals[4]),
    .reset(reset),
    .dOut(wR4Output[15:0]),
    .dOut2(wR4AddrOut[15:0]),
    .debugOut(wR4DebugOut[15:0])
  );
  SyzFETRegister3Out regAddrMSB(
    .dIn(dIn[31:16]),
    .clockSig(cpuClock),
    .read(wReadEnSignals[4]),
    .write(wWriteEnSignals[4]),
    .reset(reset),
    .dOut(wR4Output[31:16]),
    .dOut2(wR4AddrOut[31:16]),
    .debugOut()
  );
  

  Or32B5Way dOutOr(
    .aIn({16'h0000, wR0Output[15:0]}),
    .bIn({16'h0000, wR1Output[15:0]}),
    .cIn({16'h0000, wR2Output[15:0]}),
    .dIn({16'h0000, wR3Output[15:0]}),
    .eIn(wR4Output[31:0]),
    .dOut(dOut[31:0])
  );
  

  Mux16B8to1 sdIntDbgSel(
    .dIn0(wR0DebugOut[15:0]),
    .dIn1(wR1DebugOut[15:0]),
    .dIn2(wR2DebugOut[15:0]),
    .dIn3(wR3DebugOut[15:0]),
    .dIn4(wR4DebugOut[15:0]),
    .dIn5(16'h0000),
    .dIn6(16'h0000),
    .dIn7(16'h0000),
    .sel(debugRegSelect[2:0]),
    .dOut(debugOut[15:0])
  );
  

  SDController controller(
    .ctrlClk(cpuClock),
    .addr(wR4AddrOut[31:0]),
    .dIn(wR2DataOut[15:0]),
    .op(wR0InstrOut[15:0]),
    .exec(exec),
    .reset(reset),
    .miso(miso),
    .debugRegSelect(debugRegSelect[3:0]),
    .serialClockOut(serialClockOut),
    .status(wR1StatusIn[2:0]),
    .updateStatus(wEnR1Write),
    .clkR1(wSetR1),
    .dOut(wR3DataOutIn[15:0]),
    .updateDataOut(wEnR3Write),
    .clkR3(wSetR3),
    .chipSelect(chipSel),
    .mosi(mosi),
    .debugOut(debugControllerOut[15:0])
  );
  
endmodule