data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:31: Unsupported: Ignoring delay on this delayed statement.\n always #5 C = ~C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:35: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("salida.dmp");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:36: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:38: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | | O: %b, C: %b, num: %d", O, C, O);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #300;\n  ^\n%Error: data/full_repos/permissive/408955603/Sesion9/contadorBiestableJK.v:43: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module JKDown(output reg Q, output wire nQ, input wire J, input wire K, input wire C);
	initial Q = 0;
	not(nQ, Q);

	always @(negedge C)
		case ({J, K})
			2'b10: Q = 1;
			2'b01: Q = 0;
			2'b11: Q = ~Q;
		endcase
endmodule
module JKDown(output reg Q, output wire nQ, input wire J, input wire K, input wire C);

	initial Q = 0;
	not(nQ, Q);

	always @(negedge C)
		case ({J, K})
			2'b10: Q = 1;
			2'b01: Q = 0;
			2'b11: Q = ~Q;
		endcase
endmodule