data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_DL_16_1_mux.v
data/verilator_xmls/429554e9-cb71-404b-9fe5-36568767c11f.xml
module bm_DL_16_1_mux (W, S16, f);
	input [15:0] W;
	input [3:0] S16;
	output f;
	wire [3:0] M;

	mux4to1 Mux1 (W[3:0], S16[1:0], M[0]);
	mux4to1 Mux2 (W[7:4], S16[1:0], M[1]);
	mux4to1 Mux3 (W[11:8], S16[1:0], M[2]);
	mux4to1 Mux4 (W[15:12], S16[1:0], M[3]);
	mux4to1 Mux5 (M[3:0], S16[3:2], f);
		 
endmodule
module bm_DL_16_1_mux (W, S16, f);

	input [15:0] W;
	input [3:0] S16;
	output f;
	wire [3:0] M;

	mux4to1 Mux1 (W[3:0], S16[1:0], M[0]);
	mux4to1 Mux2 (W[7:4], S16[1:0], M[1]);
	mux4to1 Mux3 (W[11:8], S16[1:0], M[2]);
	mux4to1 Mux4 (W[15:12], S16[1:0], M[3]);
	mux4to1 Mux5 (M[3:0], S16[3:2], f);
		 
endmodule