data/full_repos/permissive/446997925/hw4/sign_extend_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/sign_extend_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/sign_extend_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw4/sign_extend_testbench.v:19: Unsupported or unknown PLI call: $monitor\n$monitor("time = %2d, a =%16b, out=%32b", $time, a, out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sign_extend_testbench();

reg [15:0] a;
wire [31:0] out;

sign_extend_16_32 s(a [15:0],out[31:0]);

initial begin
a = 32'b00000000_10101010;
#`DELAY;
a = 32'b10111111_11111111;
#`DELAY;
end

initial
begin
$monitor("time = %2d, a =%16b, out=%32b", $time, a, out);
end


endmodule
module sign_extend_testbench();


reg [15:0] a;
wire [31:0] out;

sign_extend_16_32 s(a [15:0],out[31:0]);

initial begin
a = 32'b00000000_10101010;
#`DELAY;
a = 32'b10111111_11111111;
#`DELAY;
end

initial
begin
$monitor("time = %2d, a =%16b, out=%32b", $time, a, out);
end


endmodule