data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n            #95;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n            # 30;\n            ^\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:36: Cannot find file containing module: \'ARINC429\'\n    ARINC429 uut(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/INTERFACES/src/ARINC429,data/full_repos/permissive/52714256/ARINC429\n             data/full_repos/permissive/52714256/INTERFACES/src/ARINC429,data/full_repos/permissive/52714256/ARINC429.v\n             data/full_repos/permissive/52714256/INTERFACES/src/ARINC429,data/full_repos/permissive/52714256/ARINC429.sv\n             ARINC429\n             ARINC429.v\n             ARINC429.sv\n             obj_dir/ARINC429\n             obj_dir/ARINC429.v\n             obj_dir/ARINC429.sv\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/ARINC429_testbench.v:64: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'habcde\' generates 22 bits.\n                                                                                                   : ... In instance ARINC429_testbench\n            dat1 = 22\'habcde;\n                 ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARINC429_testbench();

    wire X0;
    wire X1;
    reg st;
    wire [7:0] adr;
    wire [22:0] dat;
    wire ce_wr;
    reg clk;
    reg [1:0] nvel;
    reg [7:0] adr1;
    reg [22:0] dat1;
    
    ARINC429 uut(
        .nvel(nvel),
        .adr(adr1),
        .dat(dat1),
        .GCLK(clk),
        .TXD0(X0),
        .TXD1(X1),
        .RXD0(X0),
        .RXD1(X1),
        .st(st),
        .sr_adr(adr),
        .sr_dat(dat),
        .ce_wr(ce_wr)
    );
    
    always
        begin
            clk = 0;
            #10;
            clk = 1;
            #10;
        end
        
        
    initial
        begin
            nvel = 2'd2;
            adr1 = 8'haf;
            dat1 = 22'habcde;
            st = 0;
            #95;
            st = 1;
            # 30;
            st = 0;
        end
    
endmodule
module ARINC429_testbench();


    wire X0;
    wire X1;
    reg st;
    wire [7:0] adr;
    wire [22:0] dat;
    wire ce_wr;
    reg clk;
    reg [1:0] nvel;
    reg [7:0] adr1;
    reg [22:0] dat1;
    
    ARINC429 uut(
        .nvel(nvel),
        .adr(adr1),
        .dat(dat1),
        .GCLK(clk),
        .TXD0(X0),
        .TXD1(X1),
        .RXD0(X0),
        .RXD1(X1),
        .st(st),
        .sr_adr(adr),
        .sr_dat(dat),
        .ce_wr(ce_wr)
    );
    
    always
        begin
            clk = 0;
            #10;
            clk = 1;
            #10;
        end
        
        
    initial
        begin
            nvel = 2'd2;
            adr1 = 8'haf;
            dat1 = 22'habcde;
            st = 0;
            #95;
            st = 1;
            # 30;
            st = 0;
        end
    
endmodule