data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/sine_gen.v
data/verilator_xmls/5d97c1ac-b4c7-4129-89b2-4a313d9f02e1.xml
module sine_gen(
    input clk ,
    output reg [15:0] sineOutput
    );
parameter SIZE = 1024;    
reg [15:0] rom_memory [SIZE-1:0];
integer i;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
end
    

always@(posedge clk) begin
    sineOutput = rom_memory[i];
    i = i+ 1;
    if(i == SIZE)
        i = 0;
end
endmodule
module sine_gen(
    input clk ,
    output reg [15:0] sineOutput
    );

parameter SIZE = 1024;    
reg [15:0] rom_memory [SIZE-1:0];
integer i;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
end
    

always@(posedge clk) begin
    sineOutput = rom_memory[i];
    i = i+ 1;
    if(i == SIZE)
        i = 0;
end
endmodule