data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKROOT2.v
data/verilator_xmls/73e7a645-6b2a-4b39-adb8-72d8b7c279d0.xml
module ATCKROOT2
    (
     A,
     Y
     );
input A;
output Y;

reg    Y;
always @(A)
    begin
    Y = A;
    end

endmodule
module ATCKROOT2
    (
     A,
     Y
     );

input A;
output Y;

reg    Y;
always @(A)
    begin
    Y = A;
    end

endmodule