data/full_repos/permissive/519392866/level3_design/shift_reg.v
data/verilator_xmls/47ed75a1-9dbe-4a55-a0ae-b0f51c5fad12.xml
module multiplexer_4_1(X, A0, A1, A2, A3, S1, S0);
   parameter WIDTH=16;

   output [WIDTH-1:0] X;

   input [WIDTH-1:0]  A3;
   input [WIDTH-1:0]  A2;
   input [WIDTH-1:0]  A1;
   input [WIDTH-1:0]  A0;
   input 	      S0;
   input 	      S1;

   assign X = (S1 == 0 
	       ? (S0 == 0 
		  ? A0
		  : A1)
	       : (S0 == 0 
		  ? A2
		  : A3));
endmodule
module multiplexer_4_1(X, A0, A1, A2, A3, S1, S0);

   parameter WIDTH=16;

   output [WIDTH-1:0] X;

   input [WIDTH-1:0]  A3;
   input [WIDTH-1:0]  A2;
   input [WIDTH-1:0]  A1;
   input [WIDTH-1:0]  A0;
   input 	      S0;
   input 	      S1;

   assign X = (S1 == 0 
	       ? (S0 == 0 
		  ? A0
		  : A1)
	       : (S0 == 0 
		  ? A2
		  : A3));
endmodule