data/full_repos/permissive/497870922/rtl/spi module/spi_master_controller.v
1: b'%Error: Cannot find file containing module: module,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.sv\n             module,data/full_repos/permissive/497870922\n             module,data/full_repos/permissive/497870922.v\n             module,data/full_repos/permissive/497870922.sv\n             obj_dir/module,data/full_repos/permissive/497870922\n             obj_dir/module,data/full_repos/permissive/497870922.v\n             obj_dir/module,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/rtl/spi\n%Error: Cannot find file containing module: module/spi_master_controller.v\n%Error: Exiting due to 3 error(s)\n'
module spi_master_controller(
   Clk
  ,Rst_n
  ,MI
  ,MO
  ,SCLK
  ,CPol
  ,CPha
  ,Spr1
  ,Spr0
  ,CPre
  ,Spie
  ,Spse
  ,LoadMaster
  ,SpiBuf
  ,Busy
  ,WrBuf
  ,Int
  ,SpiSRRx
);
parameter SIZE = 8;

input             Clk;
input             Rst_n;


input             MI;
output            MO;
output            SCLK;

input  [SIZE-1:0] CPre;
input             CPol;
input             CPha;
input             Spr1,Spr0;


input             Spie;
input             Spse;
input             LoadMaster;
input  [SIZE-1:0] SpiBuf;
output            Busy;
output            WrBuf;
output            Int;
output [SIZE-1:0] SpiSRRx;


reg               SCLK;
reg               WrBuf;
reg               Int;
reg    [SIZE-1:0] SpiSRRx;


reg    [SIZE-1:0] txReg;
reg    [SIZE-1:0] clkCnt;
reg         [2:0] cycle_cnt;
wire              pulse;
wire              rstCount_n;
reg               cEn;
wire              startT;
reg               endT;


assign MO = txReg[7];


assign startT = Spse & LoadMaster;


assign Busy = cEn;


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n)      cEn <= 1'b0;
  else if(startT) cEn <= 1'b1;
  else if(endT)   cEn <= 1'b0;
  else            cEn <= cEn;


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) clkCnt <= 8'h0;
  else begin
    case ({Spr1,Spr0})
      2'b00: clkCnt <= 8'h01;
      2'b01: clkCnt <= 8'h03;
      2'b10: clkCnt <= 8'h07;
      2'b11: clkCnt <= CPre;
    endcase
  end


assign rstCount_n = Rst_n & cEn;


gray_counter #(SIZE) GC(
   .clk_i            (Clk)
  ,.rst_n_i          (rstCount_n)
  ,.en_i             (cEn)
  ,.period_i         (clkCnt)
  ,.clock_o          (pulse)
);


parameter IDLE   = 2'b00
         ,PHASE1 = 2'b01
         ,PHASE2 = 2'b10;

reg [1:0] state;
reg [1:0] next;

always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) state <= IDLE;
  else       state <= next;

always @(state or startT or pulse or cycle_cnt)
  case(state)
    IDLE   : if(startT) next = PHASE1;
             else      next = IDLE;

    PHASE1 : if(pulse) next = PHASE2;
             else      next = PHASE1;

    PHASE2 : if(pulse) begin
               if(cycle_cnt == 3'd7) next = IDLE;
               else                  next = PHASE1;
             end else                next = PHASE2;
    default : next = IDLE;
  endcase


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) begin
    SCLK      <= 1'b0;
    cycle_cnt <= 3'd0;
    txReg     <= 8'd0;
    SpiSRRx   <= 8'd0;
    endT      <= 1'b0;
    WrBuf     <= 1'b0;
    Int       <= 1'b0;
  end else begin
    case(state)
      IDLE   : begin
                 cycle_cnt <= 3'd0;
                 txReg     <= SpiBuf;
                 SpiSRRx   <= 8'd0;
                 endT      <= 1'b0;
                 WrBuf     <= 1'b0;
                 Int       <= 1'b0;
                 if(!startT) begin
                   SCLK      <= CPol;
                 end else begin
                   if(CPha) begin
                     SCLK     <= ~CPol;
                   end else begin
                     SCLK     <= CPol;
                   end
                 end
               end

      PHASE1 : begin
                 cycle_cnt <= cycle_cnt;
                 txReg     <= txReg;
                 endT      <= 1'b0;
                 WrBuf     <= 1'b0;
                 Int       <= 1'b0;
                 if(pulse) begin
                   SCLK     <= ~SCLK;
                   SpiSRRx  <= {SpiSRRx[6:0],MI};
                 end else begin
                   SCLK     <= SCLK;
                   SpiSRRx  <= SpiSRRx;
                 end
               end

      PHASE2 : begin
                 SpiSRRx <= SpiSRRx;
                 if(pulse) begin
                   txReg     <= {txReg[6:0],1'b0};
                   cycle_cnt <= cycle_cnt + 1'b1;
                   if(cycle_cnt == 3'd7) begin
                     SCLK    <= CPol;
                     endT    <= 1'b1;
                     WrBuf     <= 1'b1;
                     Int       <= 1'b1 & Spie;
                   end else begin
                     SCLK    <= ~SCLK;
                     endT    <= 1'b0;
                     WrBuf   <= 1'b0;
                     Int     <= 1'b0;
                   end
                 end else begin
                   cycle_cnt <= cycle_cnt;
                   SCLK      <= SCLK;
                   endT      <= 1'b0;
                   WrBuf     <= 1'b0;
                   Int       <= 1'b0;
                 end
                end

      default : begin
                  SCLK      <= 1'b0;
                  cycle_cnt <= 3'd0;
                  txReg     <= 8'd0;
                  SpiSRRx   <= 8'd0;
                  endT      <= 1'b0;
                  WrBuf     <= 1'b0;
                  Int       <= 1'b0;
                end
    endcase
  end

endmodule
module spi_master_controller(
   Clk
  ,Rst_n
  ,MI
  ,MO
  ,SCLK
  ,CPol
  ,CPha
  ,Spr1
  ,Spr0
  ,CPre
  ,Spie
  ,Spse
  ,LoadMaster
  ,SpiBuf
  ,Busy
  ,WrBuf
  ,Int
  ,SpiSRRx
);

parameter SIZE = 8;

input             Clk;
input             Rst_n;


input             MI;
output            MO;
output            SCLK;

input  [SIZE-1:0] CPre;
input             CPol;
input             CPha;
input             Spr1,Spr0;


input             Spie;
input             Spse;
input             LoadMaster;
input  [SIZE-1:0] SpiBuf;
output            Busy;
output            WrBuf;
output            Int;
output [SIZE-1:0] SpiSRRx;


reg               SCLK;
reg               WrBuf;
reg               Int;
reg    [SIZE-1:0] SpiSRRx;


reg    [SIZE-1:0] txReg;
reg    [SIZE-1:0] clkCnt;
reg         [2:0] cycle_cnt;
wire              pulse;
wire              rstCount_n;
reg               cEn;
wire              startT;
reg               endT;


assign MO = txReg[7];


assign startT = Spse & LoadMaster;


assign Busy = cEn;


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n)      cEn <= 1'b0;
  else if(startT) cEn <= 1'b1;
  else if(endT)   cEn <= 1'b0;
  else            cEn <= cEn;


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) clkCnt <= 8'h0;
  else begin
    case ({Spr1,Spr0})
      2'b00: clkCnt <= 8'h01;
      2'b01: clkCnt <= 8'h03;
      2'b10: clkCnt <= 8'h07;
      2'b11: clkCnt <= CPre;
    endcase
  end


assign rstCount_n = Rst_n & cEn;


gray_counter #(SIZE) GC(
   .clk_i            (Clk)
  ,.rst_n_i          (rstCount_n)
  ,.en_i             (cEn)
  ,.period_i         (clkCnt)
  ,.clock_o          (pulse)
);


parameter IDLE   = 2'b00
         ,PHASE1 = 2'b01
         ,PHASE2 = 2'b10;

reg [1:0] state;
reg [1:0] next;

always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) state <= IDLE;
  else       state <= next;

always @(state or startT or pulse or cycle_cnt)
  case(state)
    IDLE   : if(startT) next = PHASE1;
             else      next = IDLE;

    PHASE1 : if(pulse) next = PHASE2;
             else      next = PHASE1;

    PHASE2 : if(pulse) begin
               if(cycle_cnt == 3'd7) next = IDLE;
               else                  next = PHASE1;
             end else                next = PHASE2;
    default : next = IDLE;
  endcase


always @(posedge Clk or negedge Rst_n)
  if(!Rst_n) begin
    SCLK      <= 1'b0;
    cycle_cnt <= 3'd0;
    txReg     <= 8'd0;
    SpiSRRx   <= 8'd0;
    endT      <= 1'b0;
    WrBuf     <= 1'b0;
    Int       <= 1'b0;
  end else begin
    case(state)
      IDLE   : begin
                 cycle_cnt <= 3'd0;
                 txReg     <= SpiBuf;
                 SpiSRRx   <= 8'd0;
                 endT      <= 1'b0;
                 WrBuf     <= 1'b0;
                 Int       <= 1'b0;
                 if(!startT) begin
                   SCLK      <= CPol;
                 end else begin
                   if(CPha) begin
                     SCLK     <= ~CPol;
                   end else begin
                     SCLK     <= CPol;
                   end
                 end
               end

      PHASE1 : begin
                 cycle_cnt <= cycle_cnt;
                 txReg     <= txReg;
                 endT      <= 1'b0;
                 WrBuf     <= 1'b0;
                 Int       <= 1'b0;
                 if(pulse) begin
                   SCLK     <= ~SCLK;
                   SpiSRRx  <= {SpiSRRx[6:0],MI};
                 end else begin
                   SCLK     <= SCLK;
                   SpiSRRx  <= SpiSRRx;
                 end
               end

      PHASE2 : begin
                 SpiSRRx <= SpiSRRx;
                 if(pulse) begin
                   txReg     <= {txReg[6:0],1'b0};
                   cycle_cnt <= cycle_cnt + 1'b1;
                   if(cycle_cnt == 3'd7) begin
                     SCLK    <= CPol;
                     endT    <= 1'b1;
                     WrBuf     <= 1'b1;
                     Int       <= 1'b1 & Spie;
                   end else begin
                     SCLK    <= ~SCLK;
                     endT    <= 1'b0;
                     WrBuf   <= 1'b0;
                     Int     <= 1'b0;
                   end
                 end else begin
                   cycle_cnt <= cycle_cnt;
                   SCLK      <= SCLK;
                   endT      <= 1'b0;
                   WrBuf     <= 1'b0;
                   Int       <= 1'b0;
                 end
                end

      default : begin
                  SCLK      <= 1'b0;
                  cycle_cnt <= 3'd0;
                  txReg     <= 8'd0;
                  SpiSRRx   <= 8'd0;
                  endT      <= 1'b0;
                  WrBuf     <= 1'b0;
                  Int       <= 1'b0;
                end
    endcase
  end

endmodule