data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:61: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:72: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:74: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:83: syntax error, unexpected \'@\'\n    repeat(20) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:84: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:89: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:98: syntax error, unexpected \'@\'\n    repeat(20) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:99: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:104: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:113: syntax error, unexpected \'@\'\n    repeat(20) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:114: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:119: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:129: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:130: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:133: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:143: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:144: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:147: syntax error, unexpected \'@\'\n    repeat(8 * 10) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:154: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:157: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:165: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:167: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:176: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:178: Unsupported: wait statements\n    wait(ack == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:179: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:186: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:189: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/45473097/DriveTFT18.srcs/sim_1/new/sim_spi.v:191: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 26 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_spi(

    );
  reg         clk;
  reg         rsth;

  reg         mod_sel;
  reg         req;
  reg [3:0]   command;
  reg [17:0]  wdata;

  wire [31:0]  rdata;
  wire         ack;

  wire         oSCL;
  wire         oDCX;
  wire         oCSX;

  reg          r_SDA = 1'bz;
  wire         oSDA = r_SDA;

  reg [31:0]    read_data = 0;

  spi uut (
    .clk(clk),
    .rsth(rsth),
    .mod_sel(mod_sel),
    .req(req),
    .command(command),
    .wdata(wdata),
    .rdata(rdata),
    .ack(ack),
    .oSCL(oSCL),
    .oDCX(oDCX),
    .oCSX(oCSX),
    .oSDA(oSDA)
  );

  always #10 clk = ~clk;


  integer testnum = 0;
  initial begin
    clk       = 0;
    rsth      = 1;
    mod_sel   = 0;
    req       = 0;
    command   = 0;
    wdata     = 0;
    repeat (10) @(posedge clk);
    rsth = 0;
    repeat (10) @(posedge clk);


    testnum = 1;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command  <= 4'b0000;
    wdata <= 18'b11001010;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 2;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0000;
    wdata <= 8'ha5;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 3;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0001;
    wdata <= 8'b11101100;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 4;
    read_data = 'h12;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0100;
    wdata <= 8'b00110101;
    
    repeat(10) @(posedge clk);
    wait(ack == 1'b1);

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 5;
    read_data = 'h12345678;
    mod_sel <= 1'b1;
    command <= 4'b0111;
    wdata <= 8'b10100011;
    req <= 1'b1;
    
    repeat(10) @(posedge clk);
    wait(ack == 1'b1);

    req <= 1'b0;
    repeat(8 * 10) @(posedge clk);


    testnum = 6;
    mod_sel <= 1'b1;
    command <= 4'b1000;
    req <= 1'b1;
    repeat(100) @(posedge clk);
    req <= 1'b0;
    
    repeat(10) @(posedge clk);


    testnum = 7;
    mod_sel <= 1'b1;
    command <= 4'b1001;
    wdata   <= (6'b101010 << 12 ) | (6'b111000 << 6) | (6'b001101);
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    wait(ack == 1'b1);
    req <= 1'b0;
    

    testnum = 8;
    mod_sel <= 1'b1;
    command <= 4'b1001;
    wdata   <= (6'b110011 << 12 ) | (6'b010101 << 6) | (6'b000111);
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    wait(ack == 1'b1);
    repeat(10) @(posedge clk);
    

    testnum = 9;
    mod_sel <= 1'b1;
    command <= 4'b1010;
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    
    repeat(100) @(posedge clk);

    #100;
    $finish;
  end

  reg [5:0] read_pos = 6'b11_1111;
  reg req_1d;
  always @(negedge oSCL) begin
    req_1d <= req;
  end
  wire req_pe = ~req_1d & req;
  wire is_read_command = (command[3:2] == 2'b01);
  wire [1:0] readsize = command[1:0];
  always @(negedge oSCL or posedge req) begin
    if(rsth)                          read_pos = 6'b11_1111;
    else if(is_read_command & req_pe) read_pos = readsize * 8 + 8;
    else if(read_pos == 6'b11_1111)   read_pos = -1;
    else if(oCSX)                     read_pos = read_pos - 1;
  end

  always @(negedge oSCL) begin
    if(read_pos == 6'b11_1111) r_SDA = 1'bz;
    else                       r_SDA = read_data[read_pos];
  end


endmodule
module sim_spi(

    );

  reg         clk;
  reg         rsth;

  reg         mod_sel;
  reg         req;
  reg [3:0]   command;
  reg [17:0]  wdata;

  wire [31:0]  rdata;
  wire         ack;

  wire         oSCL;
  wire         oDCX;
  wire         oCSX;

  reg          r_SDA = 1'bz;
  wire         oSDA = r_SDA;

  reg [31:0]    read_data = 0;

  spi uut (
    .clk(clk),
    .rsth(rsth),
    .mod_sel(mod_sel),
    .req(req),
    .command(command),
    .wdata(wdata),
    .rdata(rdata),
    .ack(ack),
    .oSCL(oSCL),
    .oDCX(oDCX),
    .oCSX(oCSX),
    .oSDA(oSDA)
  );

  always #10 clk = ~clk;


  integer testnum = 0;
  initial begin
    clk       = 0;
    rsth      = 1;
    mod_sel   = 0;
    req       = 0;
    command   = 0;
    wdata     = 0;
    repeat (10) @(posedge clk);
    rsth = 0;
    repeat (10) @(posedge clk);


    testnum = 1;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command  <= 4'b0000;
    wdata <= 18'b11001010;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 2;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0000;
    wdata <= 8'ha5;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 3;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0001;
    wdata <= 8'b11101100;
    
    repeat(20) @(posedge clk);
    wait(ack == 1'b1);

    #100;

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 4;
    read_data = 'h12;
    mod_sel <= 1'b1;
    req <= 1'b1;
    command <= 4'b0100;
    wdata <= 8'b00110101;
    
    repeat(10) @(posedge clk);
    wait(ack == 1'b1);

    req <= 1'b0;
    repeat(10) @(posedge clk);


    testnum = 5;
    read_data = 'h12345678;
    mod_sel <= 1'b1;
    command <= 4'b0111;
    wdata <= 8'b10100011;
    req <= 1'b1;
    
    repeat(10) @(posedge clk);
    wait(ack == 1'b1);

    req <= 1'b0;
    repeat(8 * 10) @(posedge clk);


    testnum = 6;
    mod_sel <= 1'b1;
    command <= 4'b1000;
    req <= 1'b1;
    repeat(100) @(posedge clk);
    req <= 1'b0;
    
    repeat(10) @(posedge clk);


    testnum = 7;
    mod_sel <= 1'b1;
    command <= 4'b1001;
    wdata   <= (6'b101010 << 12 ) | (6'b111000 << 6) | (6'b001101);
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    wait(ack == 1'b1);
    req <= 1'b0;
    

    testnum = 8;
    mod_sel <= 1'b1;
    command <= 4'b1001;
    wdata   <= (6'b110011 << 12 ) | (6'b010101 << 6) | (6'b000111);
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    wait(ack == 1'b1);
    repeat(10) @(posedge clk);
    

    testnum = 9;
    mod_sel <= 1'b1;
    command <= 4'b1010;
    req <= 1'b1;
    repeat(10) @(posedge clk);
    req <= 1'b0;
    
    repeat(100) @(posedge clk);

    #100;
    $finish;
  end

  reg [5:0] read_pos = 6'b11_1111;
  reg req_1d;
  always @(negedge oSCL) begin
    req_1d <= req;
  end
  wire req_pe = ~req_1d & req;
  wire is_read_command = (command[3:2] == 2'b01);
  wire [1:0] readsize = command[1:0];
  always @(negedge oSCL or posedge req) begin
    if(rsth)                          read_pos = 6'b11_1111;
    else if(is_read_command & req_pe) read_pos = readsize * 8 + 8;
    else if(read_pos == 6'b11_1111)   read_pos = -1;
    else if(oCSX)                     read_pos = read_pos - 1;
  end

  always @(negedge oSCL) begin
    if(read_pos == 6'b11_1111) r_SDA = 1'bz;
    else                       r_SDA = read_data[read_pos];
  end


endmodule