data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:107: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:108: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:113: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module controlpath(Clock, Resetn, Counter, Frame_next, Plot_enable, Create_enable, Black_enable, Move_enable);
	
	input Clock, Resetn, Frame_next;
	input [3:0] Counter;
	
	output reg  Plot_enable, Create_enable, Black_enable, Move_enable;
	
	parameter S_DRAW = 2'd0, S_WAIT = 2'd1, S_DELETE = 2'd2, S_MOVE = 2'd3;
	
	reg [1:0]   now, next;
	
	
	always @(*)
		begin
			case (now)
				S_DRAW: next = Counter == 4'b1111 ? S_WAIT : now;
				S_WAIT: next = Frame_next ? S_DELETE : now;
				S_DELETE: next = Counter == 4'b1111 ? S_MOVE : now;
				S_MOVE: next = S_DRAW;
				default: next = S_DRAW;
			endcase
		end
	
	
	always @(*)
		begin
			Create_enable = 0;
			Black_enable = 0;
			Move_enable = 0;
			
			case (now)
				S_DRAW: 
					begin
						Create_enable = 1;
						Plot_enable = 1;
					end   
				S_DELETE: 
					begin
						Black_enable = 1;
						Plot_enable = 1;
					end
				S_MOVE: 
					begin
						Move_enable = 1;
						Plot_enable = 0;
					end
			endcase
		end
	
	
	always @ (posedge Clock)
		begin
			if (Resetn == 0) 
				now <= S_DRAW;
			else
				now <= next;
		end

endmodule
module controlpath(Clock, Resetn, Counter, Frame_next, Plot_enable, Create_enable, Black_enable, Move_enable);

	
	input Clock, Resetn, Frame_next;
	input [3:0] Counter;
	
	output reg  Plot_enable, Create_enable, Black_enable, Move_enable;
	
	parameter S_DRAW = 2'd0, S_WAIT = 2'd1, S_DELETE = 2'd2, S_MOVE = 2'd3;
	
	reg [1:0]   now, next;
	
	
	always @(*)
		begin
			case (now)
				S_DRAW: next = Counter == 4'b1111 ? S_WAIT : now;
				S_WAIT: next = Frame_next ? S_DELETE : now;
				S_DELETE: next = Counter == 4'b1111 ? S_MOVE : now;
				S_MOVE: next = S_DRAW;
				default: next = S_DRAW;
			endcase
		end
	
	
	always @(*)
		begin
			Create_enable = 0;
			Black_enable = 0;
			Move_enable = 0;
			
			case (now)
				S_DRAW: 
					begin
						Create_enable = 1;
						Plot_enable = 1;
					end   
				S_DELETE: 
					begin
						Black_enable = 1;
						Plot_enable = 1;
					end
				S_MOVE: 
					begin
						Move_enable = 1;
						Plot_enable = 0;
					end
			endcase
		end
	
	
	always @ (posedge Clock)
		begin
			if (Resetn == 0) 
				now <= S_DRAW;
			else
				now <= next;
		end

endmodule