data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #(CYCLE/2) clk = 0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #(CYCLE/2) clk = 1;\n   ^\n%Error: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:30: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE-Thold-Tsetup);\n ^\n%Error: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:51: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE-Thold-Tsetup);\n ^\n%Error: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:72: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:73: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:82: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE-Thold-Tsetup);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515201767/Hackathon_Screening_2022_Phase_1_Design_TB.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module synchronous_scanned_d_ff_tb;

   reg d0,d1,sel,rst,clk;
   wire q;

   parameter Thold  = 5,
	     Tsetup = 5,
	     CYCLE  = 100;
  
   synchronous_scanned_d_ff dut(d0,d1,sel,rst,clk,q);

   always
   begin
   #(CYCLE/2) clk = 0;
   #(CYCLE/2) clk = 1;
   end
    
	task sync_reset;
	begin
	rst=1;
	d0=1;
	d1=1;
	sel={$random}%2;
	@(posedge clk);
	#(Thold);
	if(q!==0)
	begin
	$display("Reset is not working");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("Reset is perfect");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask
	
    task load_d0;
	input data;
	begin
	rst=0;
	d0=data;
	d1=~data;
	sel=0;
	@(posedge clk);
	#(Thold);
	if(q!=data)
	begin
	$display("Execution failed");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("All_0 is well");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask
	
	task load_d1;
	input data;
	begin
	rst=0;
	d0=~data;
	d1=data;
	sel=1;
	@(posedge clk);
	#(Thold);
	if(q!=data)
	begin
	$display("Execution failed");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("All_1 is well");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask

   initial
      begin         
	 sync_reset;
	 load_d0(1'b1);
	 sync_reset;
	 load_d1(1'b1);
	 load_d0(1'b0);
	 load_d1(1'b0);
	 sync_reset;   
	 #100 $finish;
      end       
			
endmodule
module synchronous_scanned_d_ff_tb;


   reg d0,d1,sel,rst,clk;
   wire q;

   parameter Thold  = 5,
	     Tsetup = 5,
	     CYCLE  = 100;
  
   synchronous_scanned_d_ff dut(d0,d1,sel,rst,clk,q);

   always
   begin
   #(CYCLE/2) clk = 0;
   #(CYCLE/2) clk = 1;
   end
    
	task sync_reset;
	begin
	rst=1;
	d0=1;
	d1=1;
	sel={$random}%2;
	@(posedge clk);
	#(Thold);
	if(q!==0)
	begin
	$display("Reset is not working");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("Reset is perfect");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask
	
    task load_d0;
	input data;
	begin
	rst=0;
	d0=data;
	d1=~data;
	sel=0;
	@(posedge clk);
	#(Thold);
	if(q!=data)
	begin
	$display("Execution failed");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("All_0 is well");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask
	
	task load_d1;
	input data;
	begin
	rst=0;
	d0=~data;
	d1=data;
	sel=1;
	@(posedge clk);
	#(Thold);
	if(q!=data)
	begin
	$display("Execution failed");
	$display("Error at time %t" , $time);
	$stop;
	end
	$display("All_1 is well");
	{rst,d0,d1,sel}=4'bx;
	#(CYCLE-Thold-Tsetup);
	end
	endtask

   initial
      begin         
	 sync_reset;
	 load_d0(1'b1);
	 sync_reset;
	 load_d1(1'b1);
	 load_d0(1'b0);
	 load_d1(1'b0);
	 sync_reset;   
	 #100 $finish;
      end       
			
endmodule