data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:287: Cell has missing pin: \'reset\'\n loc_timer_int inst2(\n               ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:294: Cell has missing pin: \'reset\'\n adj_timer_int inst3(\n               ^~~~~\n%Error: Exiting due to 2 warning(s)\n'
module adj_timer_int(clk, reset, adj_timer_en, adj_max_clk, adj_timer_max);
	input clk, reset, adj_timer_en;
	input [9:0] adj_max_clk;
	output adj_timer_max;
	reg [9:0] adj_timer_q;


	initial begin
		adj_timer_q = 10'b0000000000;
	end

	always @(posedge clk or posedge reset)
	begin
		if (reset) 	
			adj_timer_q <= 10'b0;	
		else if (!adj_timer_en||(adj_timer_q == adj_max_clk))
			adj_timer_q <= 10'b0;
		else
			adj_timer_q <= adj_timer_q+1;
	end


	assign adj_timer_max = (adj_timer_q == adj_max_clk);
endmodule
module adj_timer_int(clk, reset, adj_timer_en, adj_max_clk, adj_timer_max);

	input clk, reset, adj_timer_en;
	input [9:0] adj_max_clk;
	output adj_timer_max;
	reg [9:0] adj_timer_q;


	initial begin
		adj_timer_q = 10'b0000000000;
	end

	always @(posedge clk or posedge reset)
	begin
		if (reset) 	
			adj_timer_q <= 10'b0;	
		else if (!adj_timer_en||(adj_timer_q == adj_max_clk))
			adj_timer_q <= 10'b0;
		else
			adj_timer_q <= adj_timer_q+1;
	end


	assign adj_timer_max = (adj_timer_q == adj_max_clk);
endmodule