data/full_repos/permissive/456793193/spi_tbf.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/456793193/spi_tbf.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456793193/spi_tbf.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456793193/spi_tbf.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/456793193/spi_tbf.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #14;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/456793193/spi_tbf.v:81: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: data/full_repos/permissive/456793193/spi_tbf.v:41: Cannot find file containing module: \'spi_topf\'\n spi_topf uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456793193,data/full_repos/permissive/456793193/spi_topf\n             data/full_repos/permissive/456793193,data/full_repos/permissive/456793193/spi_topf.v\n             data/full_repos/permissive/456793193,data/full_repos/permissive/456793193/spi_topf.sv\n             spi_topf\n             spi_topf.v\n             spi_topf.sv\n             obj_dir/spi_topf\n             obj_dir/spi_topf.v\n             obj_dir/spi_topf.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_tbf;


	reg clk;
	reg rst;
	reg [1:0] dtf;
	reg [1:0] slave;


	wire miso;
	wire mosi;
	wire sclk;
	wire ssb1;
	wire ssb2;


	spi_topf uut (
		.clk(clk), 
		.rst(rst), 
		.miso(miso), 
		.mosi(mosi), 
		.dtf(dtf), 
		.sclk(sclk), 
		.ssb1(ssb1), 
		.ssb2(ssb2), 
		.slave(slave)
	);

	
		initial begin

		clk = 0;
		rst = 1;

		dtf = 0;

		slave = 0;


		#10;
		rst = 0;
		dtf = 2'b10;


		slave = 2'b01;
        #6;
		  slave = 2'b10;
		  #10;
		  dtf = 2'b11;

		 #14;
		 dtf = 0;


	end
      
		always #1 clk = !clk;
      
endmodule
module spi_tbf;



	reg clk;
	reg rst;
	reg [1:0] dtf;
	reg [1:0] slave;


	wire miso;
	wire mosi;
	wire sclk;
	wire ssb1;
	wire ssb2;


	spi_topf uut (
		.clk(clk), 
		.rst(rst), 
		.miso(miso), 
		.mosi(mosi), 
		.dtf(dtf), 
		.sclk(sclk), 
		.ssb1(ssb1), 
		.ssb2(ssb2), 
		.slave(slave)
	);

	
		initial begin

		clk = 0;
		rst = 1;

		dtf = 0;

		slave = 0;


		#10;
		rst = 0;
		dtf = 2'b10;


		slave = 2'b01;
        #6;
		  slave = 2'b10;
		  #10;
		  dtf = 2'b11;

		 #14;
		 dtf = 0;


	end
      
		always #1 clk = !clk;
      
endmodule