data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    always #12.5 clock <= (clock === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:40: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("mprj_stimulus.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:41: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, mprj_stimulus_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:45: syntax error, unexpected \'@\'\n            repeat (1000) @(posedge clock);\n                          ^\n%Error: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:60: syntax error, unexpected \'@\'\n            repeat (700) @(posedge clock);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/501415069/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mprj_stimulus_tb;

    reg clock;
    reg RSTB;
    reg power1, power2;
    reg CSB;
    wire gpio;
    wire [37:0] mprj_io;
    wire [3:0] status;


    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

    always #12.5 clock <= (clock === 1'b0);

    initial begin
        clock = 0;
    end

    initial begin
        $dumpfile("mprj_stimulus.vcd");
        $dumpvars(0, mprj_stimulus_tb);


        repeat (100) begin
            repeat (1000) @(posedge clock);
        end
        $display("%c[1;31m",27);
        `ifdef GL
			$display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
		`endif
        $display("%c[0m",27);
        $finish;
    end

    initial begin
        $display("Monitor: mprj_stimulus test started");
        repeat (100) begin
            repeat (700) @(posedge clock);
        end
        $display("Monitor: mprj_stimulus test Passed");
        #10000;
        $finish;
    end


    initial begin
        CSB <= 1'b1;		
        RSTB <= 1'b0;
        #2000;
        RSTB <= 1'b1;
        #1000000;
        CSB <= 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire VSS = 1'b0;

    caravel uut (
        .vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
    );


    spiflash #(
        .FILENAME("mprj_stimulus.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule
module mprj_stimulus_tb;


    reg clock;
    reg RSTB;
    reg power1, power2;
    reg CSB;
    wire gpio;
    wire [37:0] mprj_io;
    wire [3:0] status;


    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

    always #12.5 clock <= (clock === 1'b0);

    initial begin
        clock = 0;
    end

    initial begin
        $dumpfile("mprj_stimulus.vcd");
        $dumpvars(0, mprj_stimulus_tb);


        repeat (100) begin
            repeat (1000) @(posedge clock);
        end
        $display("%c[1;31m",27);
        `ifdef GL
			$display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
		`endif
        $display("%c[0m",27);
        $finish;
    end

    initial begin
        $display("Monitor: mprj_stimulus test started");
        repeat (100) begin
            repeat (700) @(posedge clock);
        end
        $display("Monitor: mprj_stimulus test Passed");
        #10000;
        $finish;
    end


    initial begin
        CSB <= 1'b1;		
        RSTB <= 1'b0;
        #2000;
        RSTB <= 1'b1;
        #1000000;
        CSB <= 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire VSS = 1'b0;

    caravel uut (
        .vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
    );


    spiflash #(
        .FILENAME("mprj_stimulus.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule