data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #1 j = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #1 j = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 k = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1 k = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 j = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: data/full_repos/permissive/417288846/List_1/Task_1/JK_latch_tb.v:36: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " j=%d, k=%d, clk=%d out=%d", j, k, clk, out);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg j, k, clk;
    wire out;

    jk_latch jk1(.j(j), .k(k), .clk(clk), .q(out));
    initial begin
        clk = 0;
        j = 0;
        k = 0;

        #1 j = 1;
        #1 clk = 1;
        #1 clk = 0;

        #1 j = 0;
        #1 clk = 1;
        #1 clk = 0;

        #2 k = 1;
        #1 clk = 1;
        #1 clk = 0;
        #1 k = 0;

        #1 j = 1;
        k = 1;
        #1 clk = 1;
        #1 clk = 0;
        j = 0;
        k = 0;

        #1 clk = 1;
        #1 clk = 0;

        #2 $finish;
    end
    initial $monitor ($time, " j=%d, k=%d, clk=%d out=%d", j, k, clk, out);
endmodule
module testbench;

    reg j, k, clk;
    wire out;

    jk_latch jk1(.j(j), .k(k), .clk(clk), .q(out));
    initial begin
        clk = 0;
        j = 0;
        k = 0;

        #1 j = 1;
        #1 clk = 1;
        #1 clk = 0;

        #1 j = 0;
        #1 clk = 1;
        #1 clk = 0;

        #2 k = 1;
        #1 clk = 1;
        #1 clk = 0;
        #1 k = 0;

        #1 j = 1;
        k = 1;
        #1 clk = 1;
        #1 clk = 0;
        j = 0;
        k = 0;

        #1 clk = 1;
        #1 clk = 0;

        #2 $finish;
    end
    initial $monitor ($time, " j=%d, k=%d, clk=%d out=%d", j, k, clk, out);
endmodule