data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("pdm_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, pdm_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:40: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:42: syntax error, unexpected \'@\'\n        repeat(32) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:46: syntax error, unexpected \'@\'\n        repeat(32) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:49: syntax error, unexpected \'@\'\n        repeat(32) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:53: syntax error, unexpected \'@\'\n        repeat(300) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:56: syntax error, unexpected \'@\'\n        repeat(300) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:59: syntax error, unexpected \'@\'\n        repeat(300) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:62: syntax error, unexpected \'@\'\n        repeat(300) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_tb.v:65: syntax error, unexpected \'@\'\n        repeat(300) @(posedge clk);\n                    ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pdm_tb();

    reg clk, rst, en;
    reg [7:0] duty;
    wire pdm;

    pdm#(.DUTY_BITS(8)) DUT (
        .clk(clk),
        .rst(rst),
        .en(en),
        .duty(duty),
        .pdm(pdm)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("pdm_tb.vcd");
        $dumpvars(0, pdm_tb);

        en = 1'b0;
        duty = 8'd0;
        @(negedge rst);

        repeat(32) @(posedge clk);

        en = 1'b1;
        duty = 8'd255;
        repeat(32) @(posedge clk);

        en = 1'b0;
        repeat(32) @(posedge clk);

        en = 1'b1;
        duty = 8'd0;
        repeat(300) @(posedge clk);

        duty = 8'd128;
        repeat(300) @(posedge clk);

        duty = 8'd192;
        repeat(300) @(posedge clk);

        duty = 8'd255;
        repeat(300) @(posedge clk);

        duty = 8'd40;
        repeat(300) @(posedge clk);

        $display("%t: PDM testbench complete", $time);
        $finish;
  end

endmodule
module pdm_tb();


    reg clk, rst, en;
    reg [7:0] duty;
    wire pdm;

    pdm#(.DUTY_BITS(8)) DUT (
        .clk(clk),
        .rst(rst),
        .en(en),
        .duty(duty),
        .pdm(pdm)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("pdm_tb.vcd");
        $dumpvars(0, pdm_tb);

        en = 1'b0;
        duty = 8'd0;
        @(negedge rst);

        repeat(32) @(posedge clk);

        en = 1'b1;
        duty = 8'd255;
        repeat(32) @(posedge clk);

        en = 1'b0;
        repeat(32) @(posedge clk);

        en = 1'b1;
        duty = 8'd0;
        repeat(300) @(posedge clk);

        duty = 8'd128;
        repeat(300) @(posedge clk);

        duty = 8'd192;
        repeat(300) @(posedge clk);

        duty = 8'd255;
        repeat(300) @(posedge clk);

        duty = 8'd40;
        repeat(300) @(posedge clk);

        $display("%t: PDM testbench complete", $time);
        $finish;
  end

endmodule