data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:136: Cannot find file containing module: \'coeff_rom\'\n   coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3\'d1),.data(coeff));\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb,data/full_repos/permissive/447976230/coeff_rom\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb,data/full_repos/permissive/447976230/coeff_rom.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb,data/full_repos/permissive/447976230/coeff_rom.sv\n             coeff_rom\n             coeff_rom.v\n             coeff_rom.sv\n             obj_dir/coeff_rom\n             obj_dir/coeff_rom.v\n             obj_dir/coeff_rom.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:138: Cannot find file containing module: \'ram16_2sum\'\n   ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:143: Cannot find file containing module: \'ram16\'\n   ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd),   \n   ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:148: Cannot find file containing module: \'mult\'\n   mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));\n   ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:150: Cannot find file containing module: \'acc\'\n   acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),\n   ^~~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:159: Operator AND expects 16 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                               : ... In instance halfband_decim\n       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:159: Operator AND expects 16 bits on the RHS, but RHS\'s REDOR generates 1 bits.\n                                                                                               : ... In instance halfband_decim\n       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/halfband_decim.v:161: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                               : ... In instance halfband_decim\n   assign  debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};\n                     ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module halfband_decim
  (input clock, input reset, input enable, input strobe_in, output wire strobe_out,
   input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);

   reg [3:0] rd_addr1;
   reg [3:0] rd_addr2;
   reg [3:0] phase;
   reg [3:0] base_addr;

   wire      signed [15:0] mac_out,middle_data, sum, coeff;
   wire      signed [30:0] product;
   wire      signed [33:0] sum_even;
   wire      clear;
   reg 	     store_odd;
   
   always @(posedge clock)
     if(reset)
       store_odd <= #1 1'b0;
     else
       if(strobe_in)
	 store_odd <= #1 ~store_odd;

   wire      start = strobe_in & store_odd;
   always @(posedge clock)
     if(reset)
       base_addr <= #1 4'd0;
     else if(start)
       base_addr <= #1 base_addr + 4'd1;

   always @(posedge clock)
     if(reset)
       phase <= #1 4'd8;
     else if (start)
       phase <= #1 4'd0;
     else if(phase != 4'd8)
       phase <= #1 phase + 4'd1;

   reg 	     start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
   always @(posedge clock)
     begin
	start_d1 <= #1 start;
	start_d2 <= #1 start_d1;
	start_d3 <= #1 start_d2;
	start_d4 <= #1 start_d3;
	start_d5 <= #1 start_d4;
	start_d6 <= #1 start_d5;
	start_d7 <= #1 start_d6;
	start_d8 <= #1 start_d7;
	start_d9 <= #1 start_d8;
	start_dA <= #1 start_d9;
	start_dB <= #1 start_dA;
	start_dC <= #1 start_dB;
	start_dD <= #1 start_dC;
     end
   
   reg 	  mult_en, mult_en_pre;
   always @(posedge clock)
     begin
	mult_en_pre <= #1 phase!=8;
	mult_en <= #1 mult_en_pre;
     end
   
   assign clear = start_d4;
   wire   latch_result = start_d4;
   assign strobe_out = start_d5;
   wire   acc_en;
   
   always @*
     case(phase[2:0])
       3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
       3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end
       3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end
       3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end
       3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end
       3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end
       3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end
       3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end
       default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
     endcase
   
   coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff));
   
   ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
			  .wr_addr(base_addr),.wr_data(data_in),
			  .rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
			  .sum(sum));

   ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd),
		    .wr_addr(base_addr),.wr_data(data_in),

		    .rd_addr(base_addr+4'd6),.rd_data(middle_data));

   mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));

   acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
	   .clear(clear),.addend(product),.sum(sum_even));

   wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0};

   always @(posedge clock)
     if(reset)
       data_out <= #1 16'd0;
     else if(latch_result)
       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);

   assign  debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
   
endmodule
module halfband_decim
  (input clock, input reset, input enable, input strobe_in, output wire strobe_out,
   input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);


   reg [3:0] rd_addr1;
   reg [3:0] rd_addr2;
   reg [3:0] phase;
   reg [3:0] base_addr;

   wire      signed [15:0] mac_out,middle_data, sum, coeff;
   wire      signed [30:0] product;
   wire      signed [33:0] sum_even;
   wire      clear;
   reg 	     store_odd;
   
   always @(posedge clock)
     if(reset)
       store_odd <= #1 1'b0;
     else
       if(strobe_in)
	 store_odd <= #1 ~store_odd;

   wire      start = strobe_in & store_odd;
   always @(posedge clock)
     if(reset)
       base_addr <= #1 4'd0;
     else if(start)
       base_addr <= #1 base_addr + 4'd1;

   always @(posedge clock)
     if(reset)
       phase <= #1 4'd8;
     else if (start)
       phase <= #1 4'd0;
     else if(phase != 4'd8)
       phase <= #1 phase + 4'd1;

   reg 	     start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
   always @(posedge clock)
     begin
	start_d1 <= #1 start;
	start_d2 <= #1 start_d1;
	start_d3 <= #1 start_d2;
	start_d4 <= #1 start_d3;
	start_d5 <= #1 start_d4;
	start_d6 <= #1 start_d5;
	start_d7 <= #1 start_d6;
	start_d8 <= #1 start_d7;
	start_d9 <= #1 start_d8;
	start_dA <= #1 start_d9;
	start_dB <= #1 start_dA;
	start_dC <= #1 start_dB;
	start_dD <= #1 start_dC;
     end
   
   reg 	  mult_en, mult_en_pre;
   always @(posedge clock)
     begin
	mult_en_pre <= #1 phase!=8;
	mult_en <= #1 mult_en_pre;
     end
   
   assign clear = start_d4;
   wire   latch_result = start_d4;
   assign strobe_out = start_d5;
   wire   acc_en;
   
   always @*
     case(phase[2:0])
       3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
       3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end
       3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end
       3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end
       3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end
       3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end
       3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end
       3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end
       default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
     endcase
   
   coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff));
   
   ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
			  .wr_addr(base_addr),.wr_data(data_in),
			  .rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
			  .sum(sum));

   ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd),
		    .wr_addr(base_addr),.wr_data(data_in),

		    .rd_addr(base_addr+4'd6),.rd_data(middle_data));

   mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));

   acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
	   .clear(clear),.addend(product),.sum(sum_even));

   wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0};

   always @(posedge clock)
     if(reset)
       data_out <= #1 16'd0;
     else if(latch_result)
       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);

   assign  debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
   
endmodule