data/full_repos/permissive/430179659/LAB4/src/adder.sv
data/verilator_xmls/5c2fbe56-46a6-448c-8822-e19b14bbccce.xml
module adder(   input logic [63:0] A, B, 
                output logic [63:0] OUT );

    assign OUT = A + B;

endmodule
module adder(   input logic [63:0] A, B, 
                output logic [63:0] OUT );


    assign OUT = A + B;

endmodule