data/full_repos/permissive/513199821/commit.v
1: b'%Error: data/full_repos/permissive/513199821/commit.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: data/full_repos/permissive/513199821/commit.v:23: syntax error, unexpected new, expecting \'[\'\n    input  new,\n              ^\n%Error: data/full_repos/permissive/513199821/commit.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[2:0]     exc,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[WIDTH - 1:0] pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[WIDTH - 1:0] rval,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[$clog2 (SIZE) - 1:0] rbus\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:42: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/513199821/commit.v:49: syntax error, unexpected assign\nassign rob_rl = rmap[rl];\n^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:58: syntax error, unexpected assign\nassign rob_next = tail;\n^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:73: syntax error, unexpected always\nalways @ (posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:76: Define or directive not defined: \'`R_ZERO\'\n    rno  <= `R_ZERO;\n            ^~~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:77: Define or directive not defined: \'`EXC_NONE\'\n    exc  <= `EXC_NONE;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:84: Define or directive not defined: \'`R_ZERO\'\n    rno <= `R_ZERO;\n           ^~~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:85: Define or directive not defined: \'`EXC_NONE\'\n    exc <= `EXC_NONE;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/commit.v:95: Define or directive not defined: \'`R_ZERO\'\n      if (rno_i != `R_ZERO) begin\n                   ^~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module commit  #(
    parameter WIDTH = 32,
    parameter SIZE  = 8
  ) (
    input  clk,
    input  rst,


    input  [4:0] rl,
    input  [4:0] rr,
    output [1:0] rob_wait,
    output [$clog2 (SIZE) - 1:0] rob_rl,
    output [$clog2 (SIZE) - 1:0] rob_rr,
    output [$clog2 (SIZE) - 1:0] rob_next,


    input	 new,
    input	 full,
    input  [2:0] type,
    input  [4:0] rno_i,
    input  [WIDTH - 1:0] imm,
    input  [WIDTH - 1:0] pc_i,


    input	 ntf,
    input  [2:0] exc_n,
    input  [WIDTH - 1:0] val,
    input  [$clog2 (SIZE) - 1:0] at,


    output reg[4:0]	    rno,
    output reg[2:0]	    exc,
    output reg[WIDTH - 1:0] pc,
    output reg[WIDTH - 1:0] rval,
    output reg[$clog2 (SIZE) - 1:0] rbus
);

localparam BITS = $clog2 (SIZE);


reg		 rrob [0:31];
reg [BITS - 1:0] rmap [0:31];
assign rob_rl	= rmap[rl];
assign rob_rr	= rmap[rr];
assign rob_wait = {rrob[rl], rrob[rr]};


reg  [BITS - 1:0] head;
reg  [BITS - 1:0] tail;
wire empty = head == tail;

assign rob_next = tail;


reg		  rob_busy [0:SIZE - 1];
reg [2:0]	  rob_exc  [0:SIZE - 1];
reg [2:0]	  rob_typ  [0:SIZE - 1];
reg [4:0]	  rob_rno  [0:SIZE - 1];
reg [WIDTH - 1:0] rob_val  [0:SIZE - 1];
reg [WIDTH - 1:0] rob_pc   [0:SIZE - 1];


wire [4:0] current = rob_rno[head];

integer i;

always @ (posedge clk)
begin
  if (rst) begin
    rno  <= `R_ZERO;
    exc  <= `EXC_NONE;
    head <= 0;
    tail <= 0;
    for (i = 0; i < 32; i++)
	rrob[i] = 1'b0;
  end else begin

    rno <= `R_ZERO;
    exc <= `EXC_NONE;


    if (new & !full) begin
      rob_busy[tail] <= 1'b1;
      rob_typ [tail] <= type;
      rob_rno [tail] <= rno_i;
      rob_pc  [tail] <= pc_i;
      rob_val [tail] <= imm;
      tail	     <= tail + 1'b1;
      if (rno_i != `R_ZERO) begin
	rmap[rno_i] <= tail;
	rrob[rno_i] <= 1'b1;

      end
`ifdef COMMIT_TEST
      $display ("ROB++\t%x K%x rd=%x (%x, %x) PC=%x imm=%x", coreZ0.cycle, type, rno_i, head, tail, pc_i, imm);
`endif
    end


    if (ntf) begin
      rob_busy[at] <= 1'b0;
      rob_exc [at] <= exc_n;
      if (! (|exc_n))
	rob_val [at] <= val;
`ifdef COMMIT_TEST
      $display ("ROB==\t%x @%x exc=%x imm=%x (%x/%x)", coreZ0.cycle, at, exc_n, val, head, tail);
`endif
    end


    if (!empty & !rob_busy[head]) begin
      rno  <= current;
      exc  <= rob_exc[head];
      rval <= rob_val[head];
      pc   <= rob_pc [head];
      rbus <= head;
      head <= head + 1'b1;
      if (rmap[current] == head)
	rrob[current] <= 1'b0;
`ifdef COMMIT_TEST
      $display ("COMMIT\t%x pc=%x exc=%x rno=%x val=%x (%x, %x)", coreZ0.cycle, rob_pc[head], rob_exc[head], rob_rno[head], rob_val[head], head, tail);
`endif
    end

  end
end

endmodule
module commit  #(
    parameter WIDTH = 32,
    parameter SIZE  = 8
  ) (
    input  clk,
    input  rst,


    input  [4:0] rl,
    input  [4:0] rr,
    output [1:0] rob_wait,
    output [$clog2 (SIZE) - 1:0] rob_rl,
    output [$clog2 (SIZE) - 1:0] rob_rr,
    output [$clog2 (SIZE) - 1:0] rob_next,


    input	 new,
    input	 full,
    input  [2:0] type,
    input  [4:0] rno_i,
    input  [WIDTH - 1:0] imm,
    input  [WIDTH - 1:0] pc_i,


    input	 ntf,
    input  [2:0] exc_n,
    input  [WIDTH - 1:0] val,
    input  [$clog2 (SIZE) - 1:0] at,


    output reg[4:0]	    rno,
    output reg[2:0]	    exc,
    output reg[WIDTH - 1:0] pc,
    output reg[WIDTH - 1:0] rval,
    output reg[$clog2 (SIZE) - 1:0] rbus
);


localparam BITS = $clog2 (SIZE);


reg		 rrob [0:31];
reg [BITS - 1:0] rmap [0:31];
assign rob_rl	= rmap[rl];
assign rob_rr	= rmap[rr];
assign rob_wait = {rrob[rl], rrob[rr]};


reg  [BITS - 1:0] head;
reg  [BITS - 1:0] tail;
wire empty = head == tail;

assign rob_next = tail;


reg		  rob_busy [0:SIZE - 1];
reg [2:0]	  rob_exc  [0:SIZE - 1];
reg [2:0]	  rob_typ  [0:SIZE - 1];
reg [4:0]	  rob_rno  [0:SIZE - 1];
reg [WIDTH - 1:0] rob_val  [0:SIZE - 1];
reg [WIDTH - 1:0] rob_pc   [0:SIZE - 1];


wire [4:0] current = rob_rno[head];

integer i;

always @ (posedge clk)
begin
  if (rst) begin
    rno  <= `R_ZERO;
    exc  <= `EXC_NONE;
    head <= 0;
    tail <= 0;
    for (i = 0; i < 32; i++)
	rrob[i] = 1'b0;
  end else begin

    rno <= `R_ZERO;
    exc <= `EXC_NONE;


    if (new & !full) begin
      rob_busy[tail] <= 1'b1;
      rob_typ [tail] <= type;
      rob_rno [tail] <= rno_i;
      rob_pc  [tail] <= pc_i;
      rob_val [tail] <= imm;
      tail	     <= tail + 1'b1;
      if (rno_i != `R_ZERO) begin
	rmap[rno_i] <= tail;
	rrob[rno_i] <= 1'b1;

      end
`ifdef COMMIT_TEST
      $display ("ROB++\t%x K%x rd=%x (%x, %x) PC=%x imm=%x", coreZ0.cycle, type, rno_i, head, tail, pc_i, imm);
`endif
    end


    if (ntf) begin
      rob_busy[at] <= 1'b0;
      rob_exc [at] <= exc_n;
      if (! (|exc_n))
	rob_val [at] <= val;
`ifdef COMMIT_TEST
      $display ("ROB==\t%x @%x exc=%x imm=%x (%x/%x)", coreZ0.cycle, at, exc_n, val, head, tail);
`endif
    end


    if (!empty & !rob_busy[head]) begin
      rno  <= current;
      exc  <= rob_exc[head];
      rval <= rob_val[head];
      pc   <= rob_pc [head];
      rbus <= head;
      head <= head + 1'b1;
      if (rmap[current] == head)
	rrob[current] <= 1'b0;
`ifdef COMMIT_TEST
      $display ("COMMIT\t%x pc=%x exc=%x rno=%x val=%x (%x, %x)", coreZ0.cycle, rob_pc[head], rob_exc[head], rob_rno[head], rob_val[head], head, tail);
`endif
    end

  end
end

endmodule