data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/tc141_fflopd.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/tc141_fflopd.v:44: Cannot find file containing module: 'tc141_fflopx'\ntc141_fflopx #(DAT,VAL)   cr_temp[NPP-1:0](clk,rstn,nxt_temp,temp);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/tc141_fflopx.sv\n             tc141_fflopx\n             tc141_fflopx.v\n             tc141_fflopx.sv\n             obj_dir/tc141_fflopx\n             obj_dir/tc141_fflopx.v\n             obj_dir/tc141_fflopx.sv\n%Error: Internal Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/tc141_fflopd.v:44: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x55fb5189aeb0 <e182> {c44}  NPP [TEXT]\n                                                                                                                                           : ... In instance tc141_fflopd\ntc141_fflopx #(DAT,VAL)   cr_temp[NPP-1:0](clk,rstn,nxt_temp,temp);\n                                  ^~~\n"
module tc141_fflopd
    (
     clk    ,
     rstn   ,
     din    ,
     dout   
     );



parameter           DAT = 1;
parameter           NPP = 1;
parameter           VAL = 0;



input               clk ;
input               rstn;
input [DAT-1:0]     din;
output [DAT-1:0]    dout;






wire [DAT*NPP-1:0]  nxt_temp,temp;

tc141_fflopx #(DAT,VAL)   cr_temp[NPP-1:0](clk,rstn,nxt_temp,temp);

generate
if(NPP==0)
    begin : bypass
    assign          dout = din;
    end
else
    begin : delay
    assign          dout = temp[DAT-1:0];
    end
endgenerate

generate
if(NPP==1)
    begin : delay_1
    assign              nxt_temp = din;
    end
else
    begin : delay_n
    assign              nxt_temp = {din,temp[DAT*NPP-1:DAT]};
    end
endgenerate



endmodule
module tc141_fflopd
    (
     clk    ,
     rstn   ,
     din    ,
     dout   
     );




parameter           DAT = 1;
parameter           NPP = 1;
parameter           VAL = 0;



input               clk ;
input               rstn;
input [DAT-1:0]     din;
output [DAT-1:0]    dout;






wire [DAT*NPP-1:0]  nxt_temp,temp;

tc141_fflopx #(DAT,VAL)   cr_temp[NPP-1:0](clk,rstn,nxt_temp,temp);

generate
if(NPP==0)
    begin : bypass
    assign          dout = din;
    end
else
    begin : delay
    assign          dout = temp[DAT-1:0];
    end
endgenerate

generate
if(NPP==1)
    begin : delay_1
    assign              nxt_temp = din;
    end
else
    begin : delay_n
    assign              nxt_temp = {din,temp[DAT*NPP-1:DAT]};
    end
endgenerate



endmodule