data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:52: Unsupported: Ignoring delay on this delayed statement.\n fpga_reset = 1\'b1; #10000 fpga_reset = 1\'b0;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:56: Unsupported: Ignoring delay on this delayed statement.\n #9.259 internal_clock = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:57: Unsupported: Ignoring delay on this delayed statement.\n #9.259 internal_clock = 1\'b1; internal_audio_clock = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:58: Unsupported: Ignoring delay on this delayed statement.\n #9.259 internal_clock = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:59: Unsupported: Ignoring delay on this delayed statement.\n #9.259 internal_clock = 1\'b1; internal_audio_clock = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:63: Unsupported: Ignoring delay on this delayed statement.\n #12.5 internal_video_clock = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/502764644/mpeg_audio_video/CLOCKGEN/tb_CLOCKGEN.v:64: Unsupported: Ignoring delay on this delayed statement.\n #12.5 internal_video_clock = 1\'b1;\n ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module CLOCKGEN(
	MASTER_CLOCK_P,
	ALTERNATE_CLOCK_P,
	MEM_CLK_FBOUT_P,
	MEM_CLK_FBIN_P,
	EXTEND_DCM_RESET_P,
	internal_audio_clock,
	internal_video_clock,
	external_video_clock,
	internal_clock,
	external_clock,
	fpga_reset
);

input  		MASTER_CLOCK_P;
input  		ALTERNATE_CLOCK_P;
output 		MEM_CLK_FBOUT_P;
input  		MEM_CLK_FBIN_P;
input  		EXTEND_DCM_RESET_P;
output reg 	internal_audio_clock;
output reg 	internal_video_clock;
output		external_video_clock;
output reg 	internal_clock;
output 		external_clock;
output reg	fpga_reset;

assign MEM_CLK_FBOUT_P = MEM_CLK_FBIN_P;
assign external_video_clock = internal_video_clock;
assign external_clock = internal_clock;

initial begin
	internal_audio_clock = 1'b0;
	internal_video_clock = 1'b0;
	internal_clock = 1'b0;
	fpga_reset = 1'b1; #10000 fpga_reset = 1'b0;
end

always begin
	#9.259 internal_clock = 1'b0;
	#9.259 internal_clock = 1'b1; internal_audio_clock = 1'b0;
	#9.259 internal_clock = 1'b0;
	#9.259 internal_clock = 1'b1; internal_audio_clock = 1'b1;
end

always begin
	#12.5 internal_video_clock = 1'b0;
	#12.5 internal_video_clock = 1'b1;
end 

endmodule
module CLOCKGEN(
	MASTER_CLOCK_P,
	ALTERNATE_CLOCK_P,
	MEM_CLK_FBOUT_P,
	MEM_CLK_FBIN_P,
	EXTEND_DCM_RESET_P,
	internal_audio_clock,
	internal_video_clock,
	external_video_clock,
	internal_clock,
	external_clock,
	fpga_reset
);


input  		MASTER_CLOCK_P;
input  		ALTERNATE_CLOCK_P;
output 		MEM_CLK_FBOUT_P;
input  		MEM_CLK_FBIN_P;
input  		EXTEND_DCM_RESET_P;
output reg 	internal_audio_clock;
output reg 	internal_video_clock;
output		external_video_clock;
output reg 	internal_clock;
output 		external_clock;
output reg	fpga_reset;

assign MEM_CLK_FBOUT_P = MEM_CLK_FBIN_P;
assign external_video_clock = internal_video_clock;
assign external_clock = internal_clock;

initial begin
	internal_audio_clock = 1'b0;
	internal_video_clock = 1'b0;
	internal_clock = 1'b0;
	fpga_reset = 1'b1; #10000 fpga_reset = 1'b0;
end

always begin
	#9.259 internal_clock = 1'b0;
	#9.259 internal_clock = 1'b1; internal_audio_clock = 1'b0;
	#9.259 internal_clock = 1'b0;
	#9.259 internal_clock = 1'b1; internal_audio_clock = 1'b1;
end

always begin
	#12.5 internal_video_clock = 1'b0;
	#12.5 internal_video_clock = 1'b1;
end 

endmodule