data/full_repos/permissive/46981098/data_mem/datamem_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #2 Clk=!Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/data_mem/datamem_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  initial #300 $finish;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_dmem;
  reg [31:0] dataIn  = 32'h00000111;
  reg [31:0] address = 32'h00000003;
  reg [31:0] out;
  reg readmode;
  reg writemode;
  reg Clk=1'b0;

  dmem Datamemory(out,address,dataIn,readmode,writemode);

  always #2 Clk=!Clk;
  initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
  end

  initial begin
    writemode = 1'b1;
    readmode = 1'b0;
    #2
    writemode = 1'b0;
    #2
    readmode = 1'b1;
  end
  initial #300 $finish;

endmodule
module t_dmem;

  reg [31:0] dataIn  = 32'h00000111;
  reg [31:0] address = 32'h00000003;
  reg [31:0] out;
  reg readmode;
  reg writemode;
  reg Clk=1'b0;

  dmem Datamemory(out,address,dataIn,readmode,writemode);

  always #2 Clk=!Clk;
  initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
  end

  initial begin
    writemode = 1'b1;
    readmode = 1'b0;
    #2
    writemode = 1'b0;
    #2
    readmode = 1'b1;
  end
  initial #300 $finish;

endmodule