data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/48_two_gates_q4g.v
data/verilator_xmls/27120021-f4c8-461d-8313-c9b5bc63952a.xml
module top_module (
    input in1,
    input in2,
    input in3,
    output out);

    assign out = in3 ^ (in1 ~^ in2);
endmodule
module top_module (
    input in1,
    input in2,
    input in3,
    output out);


    assign out = in3 ^ (in1 ~^ in2);
endmodule