data/full_repos/permissive/43858668/final_verilog/src/clib/c_diag_op.v
1: b"%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_diag_op.v:39: Define or directive not defined: '`BINARY_OP_XOR'\n   parameter op = `BINARY_OP_XOR;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_diag_op.v:39: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   parameter op = `BINARY_OP_XOR;\n                                ^\n%Error: Exiting due to 2 error(s)\n"
module c_diag_op
  (data_in, data_out);
   

   parameter width = 1;
   

   parameter op = `BINARY_OP_XOR;
   

   input [0:width*width-1] data_in;
   

   output [0:width-1] 	   data_out;
   wire [0:width-1] 	   data_out;
   
   generate
      
      genvar 		   diag;
      
      for(diag = 0; diag < width; diag = diag + 1)
	begin:diags
	   
	   wire [0:width-1] diag_elems;
	   
	   genvar 	    row;
	   
	   for(row = 0; row < width; row = row + 1)
	     begin:rows
		assign diag_elems[row]
		  = data_in[row*width+(width+diag-row)%width];
	     end
	   
	   wire op_elem;
	   
	   c_binary_op
	     #(.num_ports(width),
	       .width(1),
	       .op(op))
	   op_elem_bop
	     (.data_in(diag_elems),
	      .data_out(op_elem));
	   
	   assign data_out[diag] = op_elem;
	   
	end
      
   endgenerate
   
endmodule
module c_diag_op
  (data_in, data_out);

   

   parameter width = 1;
   

   parameter op = `BINARY_OP_XOR;
   

   input [0:width*width-1] data_in;
   

   output [0:width-1] 	   data_out;
   wire [0:width-1] 	   data_out;
   
   generate
      
      genvar 		   diag;
      
      for(diag = 0; diag < width; diag = diag + 1)
	begin:diags
	   
	   wire [0:width-1] diag_elems;
	   
	   genvar 	    row;
	   
	   for(row = 0; row < width; row = row + 1)
	     begin:rows
		assign diag_elems[row]
		  = data_in[row*width+(width+diag-row)%width];
	     end
	   
	   wire op_elem;
	   
	   c_binary_op
	     #(.num_ports(width),
	       .width(1),
	       .op(op))
	   op_elem_bop
	     (.data_in(diag_elems),
	      .data_out(op_elem));
	   
	   assign data_out[diag] = op_elem;
	   
	end
      
   endgenerate
   
endmodule