data/full_repos/permissive/444327372/soc_lite_top.v
1: b"%Error: data/full_repos/permissive/444327372/soc_lite_top.v:142: syntax error, unexpected int\n    .int              (6'd0      ),   \n     ^~~\n%Error: Exiting due to 1 error(s)\n"
module soc_lite_top #(parameter SIMULATION=1'b0)
(
    input         resetn, 
    input         clk,


    output [15:0] led,
    output [1 :0] led_rg0,
    output [1 :0] led_rg1,
    output [7 :0] num_csn,
    output [6 :0] num_a_g,
    input  [7 :0] switch



);


wire [31:0] debug_wb_pc;
wire [3 :0] debug_wb_rf_wen;
wire [4 :0] debug_wb_rf_wnum;
wire [31:0] debug_wb_rf_wdata;


wire cpu_clk;
wire timer_clk;
reg cpu_resetn;
always @(posedge cpu_clk)
begin
    cpu_resetn <= resetn;
end
generate if(SIMULATION && `SIMU_USE_PLL==0)
begin: speedup_simulation
    assign cpu_clk   = clk;
    assign timer_clk = clk;
end
else
begin: pll
    clk_pll clk_pll
    (
        .clk_in1 (clk),
        .cpu_clk (cpu_clk),
        .timer_clk (timer_clk)
    );
end
endgenerate


wire        cpu_inst_en;
wire [3 :0] cpu_inst_wen;
wire [31:0] cpu_inst_addr;
wire [31:0] cpu_inst_wdata;
wire [31:0] cpu_inst_rdata;

wire        cpu_data_en;
wire [3 :0] cpu_data_wen;
wire [31:0] cpu_data_addr;
wire [31:0] cpu_data_wdata;
wire [31:0] cpu_data_rdata;


wire        data_sram_en;
wire [3 :0] data_sram_wen;
wire [31:0] data_sram_addr;
wire [31:0] data_sram_wdata;
wire [31:0] data_sram_rdata;

wire        conf_en;
wire [3 :0] conf_wen;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
wire [31:0] conf_rdata;


mycpu_top u_cpu(
    .clk              (cpu_clk   ),
    .resetn           (cpu_resetn),
    .int              (6'd0      ),

    .inst_sram_en     (cpu_inst_en   ),
    .inst_sram_wen    (cpu_inst_wen  ),
    .inst_sram_addr   (cpu_inst_addr ),
    .inst_sram_wdata  (cpu_inst_wdata),
    .inst_sram_rdata  (cpu_inst_rdata),
    
    .data_sram_en     (cpu_data_en   ),
    .data_sram_wen    (cpu_data_wen  ),
    .data_sram_addr   (cpu_data_addr ),
    .data_sram_wdata  (cpu_data_wdata),
    .data_sram_rdata  (cpu_data_rdata),


    .debug_wb_pc      (debug_wb_pc      ),
    .debug_wb_rf_wen  (debug_wb_rf_wen  ),
    .debug_wb_rf_wnum (debug_wb_rf_wnum ),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);


inst_ram inst_ram
(
    .clka  (cpu_clk            ),   
    .ena   (cpu_inst_en        ),
    .wea   (cpu_inst_wen       ),
    .addra (cpu_inst_addr[18:2]),
    .dina  (cpu_inst_wdata     ),
    .douta (cpu_inst_rdata     )
);

bridge_1x2 bridge_1x2(
    .clk             ( cpu_clk         ),
    .resetn          ( cpu_resetn      ),

    .cpu_data_en     ( cpu_data_en     ),
    .cpu_data_wen    ( cpu_data_wen    ),
    .cpu_data_addr   ( cpu_data_addr   ),
    .cpu_data_wdata  ( cpu_data_wdata  ),
    .cpu_data_rdata  ( cpu_data_rdata  ),

    .data_sram_en    ( data_sram_en    ),
    .data_sram_wen   ( data_sram_wen   ),
    .data_sram_addr  ( data_sram_addr  ),
    .data_sram_wdata ( data_sram_wdata ),
    .data_sram_rdata ( data_sram_rdata ),

    .conf_en         ( conf_en         ),
    .conf_wen        ( conf_wen        ),
    .conf_addr       ( conf_addr       ),
    .conf_wdata      ( conf_wdata      ),
    .conf_rdata      ( conf_rdata      )
 );


data_ram data_ram
(
    .clka  (cpu_clk             ),   
    .ena   (data_sram_en        ),
    .wea   (data_sram_wen       ),
    .addra (data_sram_addr[13:2]),
    .dina  (data_sram_wdata     ),
    .douta (data_sram_rdata     )
);


confreg #(.SIMULATION(SIMULATION)) confreg
(
    .clk         ( cpu_clk    ),
    .timer_clk   ( timer_clk  ),
    .resetn      ( cpu_resetn ),
    .conf_en     ( conf_en    ),
    .conf_wen    ( conf_wen   ),
    .conf_addr   ( conf_addr  ),
    .conf_wdata  ( conf_wdata ),
    .conf_rdata  ( conf_rdata ),
    .led         ( led        ),
    .led_rg0     ( led_rg0    ),
    .led_rg1     ( led_rg1    ),
    .num_csn     ( num_csn    ),
    .num_a_g     ( num_a_g    ),
    .switch      ( ~switch    )



);

endmodule
module soc_lite_top #(parameter SIMULATION=1'b0)
(
    input         resetn, 
    input         clk,


    output [15:0] led,
    output [1 :0] led_rg0,
    output [1 :0] led_rg1,
    output [7 :0] num_csn,
    output [6 :0] num_a_g,
    input  [7 :0] switch



);



wire [31:0] debug_wb_pc;
wire [3 :0] debug_wb_rf_wen;
wire [4 :0] debug_wb_rf_wnum;
wire [31:0] debug_wb_rf_wdata;


wire cpu_clk;
wire timer_clk;
reg cpu_resetn;
always @(posedge cpu_clk)
begin
    cpu_resetn <= resetn;
end
generate if(SIMULATION && `SIMU_USE_PLL==0)
begin: speedup_simulation
    assign cpu_clk   = clk;
    assign timer_clk = clk;
end
else
begin: pll
    clk_pll clk_pll
    (
        .clk_in1 (clk),
        .cpu_clk (cpu_clk),
        .timer_clk (timer_clk)
    );
end
endgenerate


wire        cpu_inst_en;
wire [3 :0] cpu_inst_wen;
wire [31:0] cpu_inst_addr;
wire [31:0] cpu_inst_wdata;
wire [31:0] cpu_inst_rdata;

wire        cpu_data_en;
wire [3 :0] cpu_data_wen;
wire [31:0] cpu_data_addr;
wire [31:0] cpu_data_wdata;
wire [31:0] cpu_data_rdata;


wire        data_sram_en;
wire [3 :0] data_sram_wen;
wire [31:0] data_sram_addr;
wire [31:0] data_sram_wdata;
wire [31:0] data_sram_rdata;

wire        conf_en;
wire [3 :0] conf_wen;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
wire [31:0] conf_rdata;


mycpu_top u_cpu(
    .clk              (cpu_clk   ),
    .resetn           (cpu_resetn),
    .int              (6'd0      ),

    .inst_sram_en     (cpu_inst_en   ),
    .inst_sram_wen    (cpu_inst_wen  ),
    .inst_sram_addr   (cpu_inst_addr ),
    .inst_sram_wdata  (cpu_inst_wdata),
    .inst_sram_rdata  (cpu_inst_rdata),
    
    .data_sram_en     (cpu_data_en   ),
    .data_sram_wen    (cpu_data_wen  ),
    .data_sram_addr   (cpu_data_addr ),
    .data_sram_wdata  (cpu_data_wdata),
    .data_sram_rdata  (cpu_data_rdata),


    .debug_wb_pc      (debug_wb_pc      ),
    .debug_wb_rf_wen  (debug_wb_rf_wen  ),
    .debug_wb_rf_wnum (debug_wb_rf_wnum ),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);


inst_ram inst_ram
(
    .clka  (cpu_clk            ),   
    .ena   (cpu_inst_en        ),
    .wea   (cpu_inst_wen       ),
    .addra (cpu_inst_addr[18:2]),
    .dina  (cpu_inst_wdata     ),
    .douta (cpu_inst_rdata     )
);

bridge_1x2 bridge_1x2(
    .clk             ( cpu_clk         ),
    .resetn          ( cpu_resetn      ),

    .cpu_data_en     ( cpu_data_en     ),
    .cpu_data_wen    ( cpu_data_wen    ),
    .cpu_data_addr   ( cpu_data_addr   ),
    .cpu_data_wdata  ( cpu_data_wdata  ),
    .cpu_data_rdata  ( cpu_data_rdata  ),

    .data_sram_en    ( data_sram_en    ),
    .data_sram_wen   ( data_sram_wen   ),
    .data_sram_addr  ( data_sram_addr  ),
    .data_sram_wdata ( data_sram_wdata ),
    .data_sram_rdata ( data_sram_rdata ),

    .conf_en         ( conf_en         ),
    .conf_wen        ( conf_wen        ),
    .conf_addr       ( conf_addr       ),
    .conf_wdata      ( conf_wdata      ),
    .conf_rdata      ( conf_rdata      )
 );


data_ram data_ram
(
    .clka  (cpu_clk             ),   
    .ena   (data_sram_en        ),
    .wea   (data_sram_wen       ),
    .addra (data_sram_addr[13:2]),
    .dina  (data_sram_wdata     ),
    .douta (data_sram_rdata     )
);


confreg #(.SIMULATION(SIMULATION)) confreg
(
    .clk         ( cpu_clk    ),
    .timer_clk   ( timer_clk  ),
    .resetn      ( cpu_resetn ),
    .conf_en     ( conf_en    ),
    .conf_wen    ( conf_wen   ),
    .conf_addr   ( conf_addr  ),
    .conf_wdata  ( conf_wdata ),
    .conf_rdata  ( conf_rdata ),
    .led         ( led        ),
    .led_rg0     ( led_rg0    ),
    .led_rg1     ( led_rg1    ),
    .num_csn     ( num_csn    ),
    .num_a_g     ( num_a_g    ),
    .switch      ( ~switch    )



);

endmodule