data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clock    = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #1.0 clock_50 = ~clock_50;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #2.0 clock_25 = ~clock_25;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end\n                                                     ^\n%Error: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:13: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/428028889/v20211112-thumbz80/tb.v:13: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end\n                                   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

reg clock;
reg clock_25;
reg clock_50;

always #0.5 clock    = ~clock;
always #1.0 clock_50 = ~clock_50;
always #2.0 clock_25 = ~clock_25;

initial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
initial begin $readmemh("tb.hex", memdata, 0); end

reg  [ 7:0] memdata[65536];
reg  [15:0] address_ctrl;
wire [15:0] address;
wire [ 7:0] i_data = memdata[ address_ctrl ];
wire [ 7:0] o_data;
wire        we;



always @(negedge clock) begin

    if (we) memdata[ address ] <= o_data;
    address_ctrl <= address;

end


tz80 MicroprocessorUnit80 
(
    .clock      (clock_50),
    .resetn     (1'b1),
    .locked     (1'b1),
    .address    (address),
    .i_data     (i_data),
    .o_data     (o_data),
    .we         (we)
);

endmodule
module tb;


reg clock;
reg clock_25;
reg clock_50;

always #0.5 clock    = ~clock;
always #1.0 clock_50 = ~clock_50;
always #2.0 clock_25 = ~clock_25;

initial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
initial begin $readmemh("tb.hex", memdata, 0); end

reg  [ 7:0] memdata[65536];
reg  [15:0] address_ctrl;
wire [15:0] address;
wire [ 7:0] i_data = memdata[ address_ctrl ];
wire [ 7:0] o_data;
wire        we;



always @(negedge clock) begin

    if (we) memdata[ address ] <= o_data;
    address_ctrl <= address;

end


tz80 MicroprocessorUnit80 
(
    .clock      (clock_50),
    .resetn     (1'b1),
    .locked     (1'b1),
    .address    (address),
    .i_data     (i_data),
    .o_data     (o_data),
    .we         (we)
);

endmodule