data/full_repos/permissive/527249789/src/regfile.v
1: b'%Error: data/full_repos/permissive/527249789/src/regfile.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/regfile.v:10: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]           waddr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`RegAddrBus]           waddr,\n                        ^\n%Error: data/full_repos/permissive/527249789/src/regfile.v:11: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]               wdata,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:15: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]           raddr1,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:16: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            rdata1,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:20: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]           raddr2,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:21: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            rdata2\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:25: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus]    regs[0:`RegNum-1];\n        ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus]    regs[0:`RegNum-1];\n               ^\n%Error: data/full_repos/permissive/527249789/src/regfile.v:25: Define or directive not defined: \'`RegNum\'\n    reg[`RegBus]    regs[0:`RegNum-1];\n                           ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:28: Define or directive not defined: \'`RstDisable\'\n        if (resetn == `RstDisable) begin\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:29: Define or directive not defined: \'`WriteEnable\'\n            if ((wen == `WriteEnable) && (waddr != `RegNumLog2\'d0)) begin\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:29: Define or directive not defined: \'`RegNumLog2\'\n            if ((wen == `WriteEnable) && (waddr != `RegNumLog2\'d0)) begin\n                                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:36: Define or directive not defined: \'`RstEnable\'\n        if (resetn == `RstEnable) begin\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:37: Define or directive not defined: \'`ZeroWord\'\n            rdata1 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:38: Define or directive not defined: \'`RegNumLog2\'\n        end else if (raddr1 == `RegNumLog2\'d0) begin\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:39: Define or directive not defined: \'`ZeroWord\'\n            rdata1 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:40: Define or directive not defined: \'`WriteEnable\'\n        end else if ((raddr1 == waddr) && (wen == `WriteEnable) && (ren1 == `ReadEnable)) begin\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:40: Define or directive not defined: \'`ReadEnable\'\n        end else if ((raddr1 == waddr) && (wen == `WriteEnable) && (ren1 == `ReadEnable)) begin\n                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:42: Define or directive not defined: \'`ReadEnable\'\n        end else if (ren1 == `ReadEnable) begin\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:45: Define or directive not defined: \'`ZeroWord\'\n            rdata1 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:50: Define or directive not defined: \'`RstEnable\'\n        if (resetn == `RstEnable) begin\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:51: Define or directive not defined: \'`ZeroWord\'\n            rdata2 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:52: Define or directive not defined: \'`RegNumLog2\'\n        end else if (raddr2 == `RegNumLog2\'d0) begin\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:53: Define or directive not defined: \'`ZeroWord\'\n            rdata2 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:54: Define or directive not defined: \'`WriteEnable\'\n        end else if ((raddr2 == waddr) && (wen == `WriteEnable) && (ren2 == `ReadEnable)) begin\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:54: Define or directive not defined: \'`ReadEnable\'\n        end else if ((raddr2 == waddr) && (wen == `WriteEnable) && (ren2 == `ReadEnable)) begin\n                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:56: Define or directive not defined: \'`ReadEnable\'\n        end else if (ren2 == `ReadEnable) begin\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/regfile.v:59: Define or directive not defined: \'`ZeroWord\'\n            rdata2 = `ZeroWord;\n                     ^~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module regfile(

    input                           clk,
    input                           resetn,


    input                           wen,
    input   [`RegAddrBus]           waddr,
    input   [`RegBus]               wdata,


    input                           ren1,
    input   [`RegAddrBus]           raddr1,
    output  reg[`RegBus]            rdata1,


    input                           ren2,
    input   [`RegAddrBus]           raddr2,
    output  reg[`RegBus]            rdata2

);

    reg[`RegBus]    regs[0:`RegNum-1];

    always @(posedge clk) begin
        if (resetn == `RstDisable) begin
            if ((wen == `WriteEnable) && (waddr != `RegNumLog2'd0)) begin
                regs[waddr] <= wdata;
            end
        end
    end

    always @(*) begin
        if (resetn == `RstEnable) begin
            rdata1 = `ZeroWord;
        end else if (raddr1 == `RegNumLog2'd0) begin
            rdata1 = `ZeroWord;
        end else if ((raddr1 == waddr) && (wen == `WriteEnable) && (ren1 == `ReadEnable)) begin
            rdata1 = wdata;
        end else if (ren1 == `ReadEnable) begin
            rdata1 = regs[raddr1];
        end else begin
            rdata1 = `ZeroWord;
        end
    end

    always @(*) begin
        if (resetn == `RstEnable) begin
            rdata2 = `ZeroWord;
        end else if (raddr2 == `RegNumLog2'd0) begin
            rdata2 = `ZeroWord;
        end else if ((raddr2 == waddr) && (wen == `WriteEnable) && (ren2 == `ReadEnable)) begin
            rdata2 = wdata;
        end else if (ren2 == `ReadEnable) begin
            rdata2 = regs[raddr2];
        end else begin
            rdata2 = `ZeroWord;
        end
    end

endmodule
module regfile(

    input                           clk,
    input                           resetn,


    input                           wen,
    input   [`RegAddrBus]           waddr,
    input   [`RegBus]               wdata,


    input                           ren1,
    input   [`RegAddrBus]           raddr1,
    output  reg[`RegBus]            rdata1,


    input                           ren2,
    input   [`RegAddrBus]           raddr2,
    output  reg[`RegBus]            rdata2

);


    reg[`RegBus]    regs[0:`RegNum-1];

    always @(posedge clk) begin
        if (resetn == `RstDisable) begin
            if ((wen == `WriteEnable) && (waddr != `RegNumLog2'd0)) begin
                regs[waddr] <= wdata;
            end
        end
    end

    always @(*) begin
        if (resetn == `RstEnable) begin
            rdata1 = `ZeroWord;
        end else if (raddr1 == `RegNumLog2'd0) begin
            rdata1 = `ZeroWord;
        end else if ((raddr1 == waddr) && (wen == `WriteEnable) && (ren1 == `ReadEnable)) begin
            rdata1 = wdata;
        end else if (ren1 == `ReadEnable) begin
            rdata1 = regs[raddr1];
        end else begin
            rdata1 = `ZeroWord;
        end
    end

    always @(*) begin
        if (resetn == `RstEnable) begin
            rdata2 = `ZeroWord;
        end else if (raddr2 == `RegNumLog2'd0) begin
            rdata2 = `ZeroWord;
        end else if ((raddr2 == waddr) && (wen == `WriteEnable) && (ren2 == `ReadEnable)) begin
            rdata2 = wdata;
        end else if (ren2 == `ReadEnable) begin
            rdata2 = regs[raddr2];
        end else begin
            rdata2 = `ZeroWord;
        end
    end

endmodule