data/full_repos/permissive/42434302/ivltests/pr584.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr584.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr584.v:12: Unsupported: Ignoring delay on this delayed statement.\n   #100\n   ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   reg clk;

always #50 clk = ~clk;

initial begin
   clk = 0;
   #100
     $display("%d", 1e3*2e-2);
     $display("%d", 1e2*0.2);
     $display("%d", 1e1*2);
     $display("%d", 1e0*20.0);
     $display("%d", 1e-1*200.0);



     $finish;
end
endmodule
module main;

   reg clk;

always #50 clk = ~clk;

initial begin
   clk = 0;
   #100
     $display("%d", 1e3*2e-2);
     $display("%d", 1e2*0.2);
     $display("%d", 1e1*2);
     $display("%d", 1e0*20.0);
     $display("%d", 1e-1*200.0);



     $finish;
end
endmodule