data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado/BRAM_SDP.v
data/verilator_xmls/59efab16-02d9-4b8a-95f8-3e352f469f64.xml
module BRAM_SDP
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
	input [(DATA_WIDTH-1):0] data,
	input [(ADDR_WIDTH-1):0] read_addr, write_addr,
	input we, clk,
	output reg [(DATA_WIDTH-1):0] q
);


(* ram_style = "auto" *)
	reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

	always @ (posedge clk)
	begin

		if (we)
			ram[write_addr] <= data;





		q <= ram[read_addr];
	end

endmodule
module BRAM_SDP
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
	input [(DATA_WIDTH-1):0] data,
	input [(ADDR_WIDTH-1):0] read_addr, write_addr,
	input we, clk,
	output reg [(DATA_WIDTH-1):0] q
);



(* ram_style = "auto" *)
	reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

	always @ (posedge clk)
	begin

		if (we)
			ram[write_addr] <= data;





		q <= ram[read_addr];
	end

endmodule