data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD tb_clk = !tb_clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:163: Unsupported: Ignoring delay on this delayed statement.\n      #(4 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:226: Unsupported: Ignoring delay on this delayed statement.\n      #(4 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:230: Unsupported: Ignoring delay on this delayed statement.\n      #(200 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:249: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:257: Unsupported: Ignoring delay on this delayed statement.\n          #(2 * CLK_HALF_PERIOD);\n          ^\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:135: Can\'t find definition of \'sha1_w_mem_ctrl_reg\' in dotted variable: \'dut.sha1_w_mem_ctrl_reg\'\n               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);\n                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:135: Can\'t find definition of \'w_ctr_reg\' in dotted variable: \'dut.w_ctr_reg\'\n               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:135: Can\'t find definition of \'init\' in dotted variable: \'dut.init\'\n               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);\n                                                           ^~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:135: Can\'t find definition of \'next\' in dotted variable: \'dut.next\'\n               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);\n                                                                     ^~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:137: Can\'t find definition of \'w_tmp\' in dotted variable: \'dut.w_tmp\'\n      $display("w_tmp   = %08x, w_new   = %08x", dut.w_tmp, dut.w_new);\n                                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:137: Can\'t find definition of \'w_new\' in dotted variable: \'dut.w_new\'\n      $display("w_tmp   = %08x, w_new   = %08x", dut.w_tmp, dut.w_new);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:140: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:140: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:140: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:140: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:143: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:143: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:143: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:143: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:146: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:146: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:146: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:146: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:149: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:149: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:149: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:149: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:194: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[00] = 0x%08x", dut.w_mem[00]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:195: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[01] = 0x%08x", dut.w_mem[01]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:196: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[02] = 0x%08x", dut.w_mem[02]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:197: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[03] = 0x%08x", dut.w_mem[03]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:198: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[04] = 0x%08x", dut.w_mem[04]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:199: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[05] = 0x%08x", dut.w_mem[05]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:200: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[06] = 0x%08x", dut.w_mem[06]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:201: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[07] = 0x%08x", dut.w_mem[07]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:202: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[08] = 0x%08x", dut.w_mem[08]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:203: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[09] = 0x%08x", dut.w_mem[09]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:204: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[10] = 0x%08x", dut.w_mem[10]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:205: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[11] = 0x%08x", dut.w_mem[11]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:206: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[12] = 0x%08x", dut.w_mem[12]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:207: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[13] = 0x%08x", dut.w_mem[13]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:208: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[14] = 0x%08x", dut.w_mem[14]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:209: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n      $display("W[15] = 0x%08x", dut.w_mem[15]);\n                                     ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_w_mem.v:255: Can\'t find definition of \'w_tmp\' in dotted variable: \'dut.w_tmp\'\n          $display("API: w%02x = 0x%02x", i, dut.w_tmp);\n                                                 ^~~~~\n%Error: Exiting due to 39 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sha1_w_mem();

  



  parameter DEBUG          = 1;
  parameter DISPLAY_CYCLES = 0;

  parameter CLK_HALF_PERIOD = 2;

  




  



  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_init;
  reg           tb_next;
  reg [511 : 0] tb_block;
  wire [31 : 0] tb_w;

  reg [63 : 0]  cycle_ctr;
  reg [31 : 0]  error_ctr;
  reg [31 : 0]  tc_ctr;
  
  



  sha1_w_mem dut(
                 .clk(tb_clk),
                 .reset_n(tb_reset_n),
                 
                 .block(tb_block),

                 .init(tb_init),
                 .next(tb_next),
                 
                 .w(tb_w)
                );
  






  always 
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end

  






  always @ (posedge tb_clk)
    begin : dut_monitor
      cycle_ctr = cycle_ctr + 1;

      if (DISPLAY_CYCLES)
        begin
          $display("cycle = %016x:", cycle_ctr);
        end

      if (DEBUG)
        begin
          dump_w_state();
        end
    end
      
  





  task dump_w_state();
    begin
      $display("W state:");

      
      $display("ctrl_reg = %01x, w_ctr_reg = %02x, init = %01x, next = %01x", 
               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);
      
      $display("w_tmp   = %08x, w_new   = %08x", dut.w_tmp, dut.w_new);
 
      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x", 
               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);

      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x", 
               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);

      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x", 
               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);

      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", 
               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);

      $display("");
    end
  endtask
  
  



  task reset_dut();
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask
  
  



  task init_sim();
    begin
      $display("*** Simulation init.");
      tb_clk     = 0;
      tb_reset_n = 1;
      cycle_ctr  = 0;
      tb_init    = 0;
      tb_next    = 0;
      tb_block   = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
    end
  endtask

  






  task dump_mem();
    begin
      $display("*** Dumping memory:");
      $display("W[00] = 0x%08x", dut.w_mem[00]);
      $display("W[01] = 0x%08x", dut.w_mem[01]);
      $display("W[02] = 0x%08x", dut.w_mem[02]);
      $display("W[03] = 0x%08x", dut.w_mem[03]);
      $display("W[04] = 0x%08x", dut.w_mem[04]);
      $display("W[05] = 0x%08x", dut.w_mem[05]);
      $display("W[06] = 0x%08x", dut.w_mem[06]);
      $display("W[07] = 0x%08x", dut.w_mem[07]);
      $display("W[08] = 0x%08x", dut.w_mem[08]);
      $display("W[09] = 0x%08x", dut.w_mem[09]);
      $display("W[10] = 0x%08x", dut.w_mem[10]);
      $display("W[11] = 0x%08x", dut.w_mem[11]);
      $display("W[12] = 0x%08x", dut.w_mem[12]);
      $display("W[13] = 0x%08x", dut.w_mem[13]);
      $display("W[14] = 0x%08x", dut.w_mem[14]);
      $display("W[15] = 0x%08x", dut.w_mem[15]);
      $display("");
    end
  endtask
  
  






  task test_w_schedule();
    begin
      $display("*** Test of W schedule processing. --");
      tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      tb_init = 1;
      #(4 * CLK_HALF_PERIOD);
      tb_init = 0;

      tb_next = 1;
      #(200 * CLK_HALF_PERIOD);
      
      dump_w_state();
    end
  endtask
  







  task test_read_w();
    reg [7 : 0] i;
    begin
      $display("*** Test of W read operations. --");
      i = 0;
      tb_init = 1;
      #(2 * CLK_HALF_PERIOD);
      tb_init = 0;
      
      while (i < 80)
        begin
          tb_next = i;
          $display("API: w%02x = 0x%02x", i, dut.w_tmp);
          i = i + 1;
          #(2 * CLK_HALF_PERIOD);
        end
    end
  endtask
  
    



  initial
    begin : w_mem_test
      $display("   -- Testbench for sha1 w memory started --");
      init_sim();

      dump_mem();
      reset_dut();
      dump_mem();
      
      test_w_schedule();

      test_read_w();

      $display("*** Simulation done.");
      $finish;
    end
  
endmodule
module tb_sha1_w_mem();


  



  parameter DEBUG          = 1;
  parameter DISPLAY_CYCLES = 0;

  parameter CLK_HALF_PERIOD = 2;

  




  



  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_init;
  reg           tb_next;
  reg [511 : 0] tb_block;
  wire [31 : 0] tb_w;

  reg [63 : 0]  cycle_ctr;
  reg [31 : 0]  error_ctr;
  reg [31 : 0]  tc_ctr;
  
  



  sha1_w_mem dut(
                 .clk(tb_clk),
                 .reset_n(tb_reset_n),
                 
                 .block(tb_block),

                 .init(tb_init),
                 .next(tb_next),
                 
                 .w(tb_w)
                );
  






  always 
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end

  






  always @ (posedge tb_clk)
    begin : dut_monitor
      cycle_ctr = cycle_ctr + 1;

      if (DISPLAY_CYCLES)
        begin
          $display("cycle = %016x:", cycle_ctr);
        end

      if (DEBUG)
        begin
          dump_w_state();
        end
    end
      
  





  task dump_w_state();
    begin
      $display("W state:");

      
      $display("ctrl_reg = %01x, w_ctr_reg = %02x, init = %01x, next = %01x", 
               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);
      
      $display("w_tmp   = %08x, w_new   = %08x", dut.w_tmp, dut.w_new);
 
      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x", 
               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);

      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x", 
               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);

      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x", 
               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);

      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", 
               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);

      $display("");
    end
  endtask
  
  



  task reset_dut();
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask
  
  



  task init_sim();
    begin
      $display("*** Simulation init.");
      tb_clk     = 0;
      tb_reset_n = 1;
      cycle_ctr  = 0;
      tb_init    = 0;
      tb_next    = 0;
      tb_block   = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
    end
  endtask

  






  task dump_mem();
    begin
      $display("*** Dumping memory:");
      $display("W[00] = 0x%08x", dut.w_mem[00]);
      $display("W[01] = 0x%08x", dut.w_mem[01]);
      $display("W[02] = 0x%08x", dut.w_mem[02]);
      $display("W[03] = 0x%08x", dut.w_mem[03]);
      $display("W[04] = 0x%08x", dut.w_mem[04]);
      $display("W[05] = 0x%08x", dut.w_mem[05]);
      $display("W[06] = 0x%08x", dut.w_mem[06]);
      $display("W[07] = 0x%08x", dut.w_mem[07]);
      $display("W[08] = 0x%08x", dut.w_mem[08]);
      $display("W[09] = 0x%08x", dut.w_mem[09]);
      $display("W[10] = 0x%08x", dut.w_mem[10]);
      $display("W[11] = 0x%08x", dut.w_mem[11]);
      $display("W[12] = 0x%08x", dut.w_mem[12]);
      $display("W[13] = 0x%08x", dut.w_mem[13]);
      $display("W[14] = 0x%08x", dut.w_mem[14]);
      $display("W[15] = 0x%08x", dut.w_mem[15]);
      $display("");
    end
  endtask
  
  






  task test_w_schedule();
    begin
      $display("*** Test of W schedule processing. --");
      tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      tb_init = 1;
      #(4 * CLK_HALF_PERIOD);
      tb_init = 0;

      tb_next = 1;
      #(200 * CLK_HALF_PERIOD);
      
      dump_w_state();
    end
  endtask
  







  task test_read_w();
    reg [7 : 0] i;
    begin
      $display("*** Test of W read operations. --");
      i = 0;
      tb_init = 1;
      #(2 * CLK_HALF_PERIOD);
      tb_init = 0;
      
      while (i < 80)
        begin
          tb_next = i;
          $display("API: w%02x = 0x%02x", i, dut.w_tmp);
          i = i + 1;
          #(2 * CLK_HALF_PERIOD);
        end
    end
  endtask
  
    



  initial
    begin : w_mem_test
      $display("   -- Testbench for sha1 w memory started --");
      init_sim();

      dump_mem();
      reset_dut();
      dump_mem();
      
      test_w_schedule();

      test_read_w();

      $display("*** Simulation done.");
      $finish;
    end
  
endmodule