data/full_repos/permissive/409594175/made/ShiftLeft4.v
data/verilator_xmls/cf797a84-5728-46a5-a0d2-f3506e748e69.xml
module ShiftLeft4(
    input  wire [31:0] data_in,
    output wire [31:0] shift_left_4_out
);

    assign shift_left_4_out = data_in << 2;

endmodule
module ShiftLeft4(
    input  wire [31:0] data_in,
    output wire [31:0] shift_left_4_out
);


    assign shift_left_4_out = data_in << 2;

endmodule