data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v
1: b'%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:83: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                              : ... In instance maxpooling\n    data[ptr] <= din;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:87: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                              : ... In instance maxpooling\n    data[ptr] <= din;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:101: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n     data_reg_0 <= data[ptr-7\'d24];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:98: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                              : ... In instance maxpooling\n    if(din>data[ptr-7\'d24])\n               ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:112: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n     data_reg_1 <= data[ptr-7\'d24];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:109: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n    if(din>data[ptr-7\'d24])\n               ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:123: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n     data_reg_0 <= data[ptr-7\'d9];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:120: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n    if(din>data[ptr-7\'d9])\n               ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:134: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n     data_reg_1 <= data[ptr-7\'d9];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/494353034/rtl/maxpooling_24X24.v:131: Bit extraction of array[23:0] requires 5 bit index, not 7 bits.\n                                                                               : ... In instance maxpooling\n    if(din>data[ptr-7\'d9])\n               ^\n%Error: Exiting due to 10 warning(s)\n'
module maxpooling
(
    input  clk,
    input  rstn,
    input  ivalid,
    input  state,
    input  [7:0] din,
    output ovalid,
    output [7:0] dout
);

	reg [7:0] data [0:23];
	reg [6:0] ptr;
	reg cnt;
	reg [7:0] data_reg_0;
	reg [7:0] data_reg_1;
	reg [7:0] dout_r;
	

	always@(posedge clk)begin
		if(!rstn)
			ptr <= 7'b0000000;
		else
			case(state)
				1'b0:begin
					if(ptr == 7'd48-1)
						ptr <= 7'd0;
					else 
						if(!ivalid)
							ptr <= ptr;
						else
							ptr <= ptr + 7'd1;
					end
				1'b1:begin
					if(ptr == 7'd16-1)
						ptr <= 7'd0;
					else 
						if(!ivalid)
							ptr <= ptr;
						else
							ptr <= ptr + 7'd1;
					end               
			endcase
	end
	




	always@(posedge clk or negedge rstn)begin
	if(!rstn)
		cnt <= 0;
	else
		case(state)
			1'b0:begin
					if(ptr < 7'd25 - 1)
						cnt <= 0;
					else
						if(ivalid)
							cnt <= cnt + 1'b1;
						else
							cnt <= cnt;
				end
			1'b1:begin
					if(ptr <= 7'd7)
						cnt <= 0;
					else
						if(ivalid)
							cnt <= cnt + 1'b1;
						else
							cnt <= cnt;
				end
		endcase
	end
	

	always@(posedge clk)
	begin
		case(state)
		1'b0:begin
			if(ptr <= 7'd24 && ivalid) 
				data[ptr] <= din;
			end
		1'b1:begin
			if(ptr <= 7'd8 && ivalid) 
				data[ptr] <= din;
			end          
		endcase   
	end

	always@(posedge clk)
	begin
		case({state,cnt})
		2'b00:begin
			if(ptr >= 7'd24)
			begin
				if(din>data[ptr-7'd24])
					data_reg_0 <= din;
				else
					data_reg_0 <= data[ptr-7'd24];
			end
			else
				data_reg_0 <= 0;
			end
		2'b01:begin
			if(ptr >= 7'd24)
			begin
				if(din>data[ptr-7'd24])
					data_reg_1 <= din;
				else
					data_reg_1 <= data[ptr-7'd24];
			end
			else
				data_reg_1 <= 0;
			end
		2'b10:begin
			if(ptr >= 7'd9)
			begin
				if(din>data[ptr-7'd9])
					data_reg_0 <= din;
				else
					data_reg_0 <= data[ptr-7'd9];
			end
			else
				data_reg_0 <= 0;
			end
		2'b11:begin
			if(ptr >= 7'd9)
			begin
				if(din>data[ptr-7'd9])
					data_reg_1 <= din;
				else
					data_reg_1 <= data[ptr-7'd9];
			end
			else
				data_reg_1 <= 0;
			end 
		default:begin
				data_reg_1 <= 0; 
				data_reg_0 <= 0;
				end         
		endcase
	end


	reg cnt_d;
	always@(posedge clk)begin
		if(!rstn)
			cnt_d <= 0;
		else
			cnt_d <= cnt;
	end
	


	assign ovalid = ~cnt && cnt_d;
	assign dout   = data_reg_1 > data_reg_0 ? data_reg_1 : data_reg_0;
	
endmodule
module maxpooling
(
    input  clk,
    input  rstn,
    input  ivalid,
    input  state,
    input  [7:0] din,
    output ovalid,
    output [7:0] dout
);


	reg [7:0] data [0:23];
	reg [6:0] ptr;
	reg cnt;
	reg [7:0] data_reg_0;
	reg [7:0] data_reg_1;
	reg [7:0] dout_r;
	

	always@(posedge clk)begin
		if(!rstn)
			ptr <= 7'b0000000;
		else
			case(state)
				1'b0:begin
					if(ptr == 7'd48-1)
						ptr <= 7'd0;
					else 
						if(!ivalid)
							ptr <= ptr;
						else
							ptr <= ptr + 7'd1;
					end
				1'b1:begin
					if(ptr == 7'd16-1)
						ptr <= 7'd0;
					else 
						if(!ivalid)
							ptr <= ptr;
						else
							ptr <= ptr + 7'd1;
					end               
			endcase
	end
	




	always@(posedge clk or negedge rstn)begin
	if(!rstn)
		cnt <= 0;
	else
		case(state)
			1'b0:begin
					if(ptr < 7'd25 - 1)
						cnt <= 0;
					else
						if(ivalid)
							cnt <= cnt + 1'b1;
						else
							cnt <= cnt;
				end
			1'b1:begin
					if(ptr <= 7'd7)
						cnt <= 0;
					else
						if(ivalid)
							cnt <= cnt + 1'b1;
						else
							cnt <= cnt;
				end
		endcase
	end
	

	always@(posedge clk)
	begin
		case(state)
		1'b0:begin
			if(ptr <= 7'd24 && ivalid) 
				data[ptr] <= din;
			end
		1'b1:begin
			if(ptr <= 7'd8 && ivalid) 
				data[ptr] <= din;
			end          
		endcase   
	end

	always@(posedge clk)
	begin
		case({state,cnt})
		2'b00:begin
			if(ptr >= 7'd24)
			begin
				if(din>data[ptr-7'd24])
					data_reg_0 <= din;
				else
					data_reg_0 <= data[ptr-7'd24];
			end
			else
				data_reg_0 <= 0;
			end
		2'b01:begin
			if(ptr >= 7'd24)
			begin
				if(din>data[ptr-7'd24])
					data_reg_1 <= din;
				else
					data_reg_1 <= data[ptr-7'd24];
			end
			else
				data_reg_1 <= 0;
			end
		2'b10:begin
			if(ptr >= 7'd9)
			begin
				if(din>data[ptr-7'd9])
					data_reg_0 <= din;
				else
					data_reg_0 <= data[ptr-7'd9];
			end
			else
				data_reg_0 <= 0;
			end
		2'b11:begin
			if(ptr >= 7'd9)
			begin
				if(din>data[ptr-7'd9])
					data_reg_1 <= din;
				else
					data_reg_1 <= data[ptr-7'd9];
			end
			else
				data_reg_1 <= 0;
			end 
		default:begin
				data_reg_1 <= 0; 
				data_reg_0 <= 0;
				end         
		endcase
	end


	reg cnt_d;
	always@(posedge clk)begin
		if(!rstn)
			cnt_d <= 0;
		else
			cnt_d <= cnt;
	end
	


	assign ovalid = ~cnt && cnt_d;
	assign dout   = data_reg_1 > data_reg_0 ? data_reg_1 : data_reg_0;
	
endmodule