data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/FINAL1/work/verilog/seven_seg_10.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                                          : ... In instance seven_seg_10\n    case (char)\n    ^~~~\n%Error: Exiting due to 12 warning(s)\n'
module seven_seg_10 (
    input [7:0] char,
    output reg [6:0] segs
  );
  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h08;
      end
      1'h1: begin
        segs = 7'h5e;
      end
      2'h2: begin
        segs = 7'h11;
      end
      2'h3: begin
        segs = 7'h12;
      end
      3'h4: begin
        segs = 7'h46;
      end
      3'h5: begin
        segs = 7'h22;
      end
      3'h6: begin
        segs = 7'h20;
      end
      3'h7: begin
        segs = 7'h1e;
      end
      4'h8: begin
        segs = 7'h00;
      end
      4'h9: begin
        segs = 7'h02;
      end
      4'hd: begin
        segs = 7'h05;
      end
      4'he: begin
        segs = 7'h2d;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule
module seven_seg_10 (
    input [7:0] char,
    output reg [6:0] segs
  );

  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h08;
      end
      1'h1: begin
        segs = 7'h5e;
      end
      2'h2: begin
        segs = 7'h11;
      end
      2'h3: begin
        segs = 7'h12;
      end
      3'h4: begin
        segs = 7'h46;
      end
      3'h5: begin
        segs = 7'h22;
      end
      3'h6: begin
        segs = 7'h20;
      end
      3'h7: begin
        segs = 7'h1e;
      end
      4'h8: begin
        segs = 7'h00;
      end
      4'h9: begin
        segs = 7'h02;
      end
      4'hd: begin
        segs = 7'h05;
      end
      4'he: begin
        segs = 7'h2d;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule