data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:20: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time CyclTime = 10ns;\n                             ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:21: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time ApplTime = 2ns;\n                             ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:22: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time TestTime = 8ns;\n                             ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:40: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:43: syntax error, unexpected \'@\'\n    repeat (5) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:45: Unsupported or unknown PLI call: $urandom_range\n      stall_cycles = $urandom_range(0, 5);\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:46: syntax error, unexpected \'@\'\n      repeat (stall_cycles) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:47: Unsupported or unknown PLI call: $urandom\n      test_data = payload_t\'($urandom());\n                             ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:51: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:53: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:54: Unsupported: Ignoring delay on this delayed statement.\n        #TestTime;\n        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:56: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:68: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:70: syntax error, unexpected \'@\'\n    repeat (5) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:72: Unsupported or unknown PLI call: $urandom\n      resp_ready <= #ApplTime $urandom();\n                              ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:73: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:79: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:81: syntax error, unexpected \'@\'\n    repeat (50) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:88: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:93: Unsupported or unknown PLI call: $urandom\n      mem_req_ready <= #ApplTime $urandom();\n                                 ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:94: Unsupported: Ignoring delay on this delayed statement.\n      #(CyclTime / 2);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:98: Unsupported: fork statements\n        fork\n        ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:101: syntax error, unexpected \'@\'\n              repeat (BufDepth) @(posedge clk);\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:102: Unsupported: Ignoring delay on this delayed statement.\n              #ApplTime;\n              ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:106: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:107: Unsupported: Ignoring delay on this delayed statement.\n            #(ApplTime / 2);\n            ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:112: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:118: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/stream_to_mem_tb.sv:119: Unsupported: wait statements\n    wait (sim_done);\n    ^~~~\n%Error: Exiting due to 23 error(s), 6 warning(s)\n'
module stream_to_mem_tb #(
  parameter int unsigned NumReq   = 32'd10000,
  parameter int unsigned BufDepth = 32'd1
);

  localparam time CyclTime = 10ns;
  localparam time ApplTime = 2ns;
  localparam time TestTime = 8ns;

  typedef logic [15:0] payload_t;



  logic     clk,       rst_n,      sim_done;
  payload_t req,       resp,       mem_req,       mem_resp;
  logic     req_valid, resp_valid, mem_req_valid, mem_resp_valid;
  logic     req_ready, resp_ready, mem_req_ready;


  payload_t data_fifo[$];


  initial begin : proc_stream_master
    automatic payload_t    test_data;
    automatic int unsigned stall_cycles;
    @(posedge rst_n);
    req       = '0;
    req_valid = '0;
    repeat (5) @(posedge clk);
    for (int unsigned i = 0; i < NumReq; i++) begin
      stall_cycles = $urandom_range(0, 5);
      repeat (stall_cycles) @(posedge clk);
      test_data = payload_t'($urandom());
      data_fifo.push_back(test_data);
      req       <= #ApplTime payload_t'(test_data);
      req_valid <= #ApplTime 1'b1;
      #TestTime;
      while (!req_ready) begin
        @(posedge clk);
        #TestTime;
      end
      @(posedge clk);
      req       <= #ApplTime '0;
      req_valid <= #ApplTime 1'b0;
    end
  end


  initial begin : proc_stream_slave
    automatic int unsigned stall_cycles;
    automatic payload_t    test_data;
    automatic int unsigned num_tested = 32'd0;
    sim_done = 0;
    @(posedge rst_n);
    resp_ready = '0;
    repeat (5) @(posedge clk);
    while (num_tested < NumReq) begin
      resp_ready <= #ApplTime $urandom();
      #TestTime;
      if (resp_valid && resp_ready) begin
        test_data = data_fifo.pop_front();
        assert(test_data === resp) else $error("test_data: %h, resp_data: %0h", test_data, resp);
        num_tested++;
      end
      @(posedge clk);
    end
    repeat (50) @(posedge clk);
    sim_done = 1'b1;
  end


  initial begin : proc_mem_reflect
    automatic payload_t reflect_fifo[$];
    @(posedge rst_n);
    mem_req_ready  = '0;
    mem_resp       = '0;
    mem_resp_valid = '0;
    forever begin
      mem_req_ready <= #ApplTime $urandom();
      #(CyclTime / 2);
      if (mem_req_valid && mem_req_ready) begin
        reflect_fifo.push_back(mem_req);

        fork
          begin
            if (BufDepth) begin
              repeat (BufDepth) @(posedge clk);
              #ApplTime;
            end
            mem_resp       = reflect_fifo.pop_front();
            mem_resp_valid = 1'b1;
            @(posedge clk);
            #(ApplTime / 2);
            mem_resp_valid = 1'b0;
          end
        join_none
      end
      @(posedge clk);
    end
  end


  initial begin : proc_sim_stop
    @(posedge rst_n);
    wait (sim_done);
    $stop();
  end


  clk_rst_gen #(
    .ClkPeriod    ( CyclTime ),
    .RstClkCycles ( 10       )
  ) i_clk_rst_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );


  stream_to_mem #(
    .mem_req_t  ( payload_t ),
    .mem_resp_t ( payload_t ),
    .BufDepth   ( BufDepth  )
  ) i_stream_to_mem_dut (
    .clk_i            ( clk            ),
    .rst_ni           ( rst_n          ),
    .req_i            ( req            ),
    .req_valid_i      ( req_valid      ),
    .req_ready_o      ( req_ready      ),
    .resp_o           ( resp           ),
    .resp_valid_o     ( resp_valid     ),
    .resp_ready_i     ( resp_ready     ),
    .mem_req_o        ( mem_req        ),
    .mem_req_valid_o  ( mem_req_valid  ),
    .mem_req_ready_i  ( mem_req_ready  ),
    .mem_resp_i       ( mem_resp       ),
    .mem_resp_valid_i ( mem_resp_valid )
  );

endmodule
module stream_to_mem_tb #(
  parameter int unsigned NumReq   = 32'd10000,
  parameter int unsigned BufDepth = 32'd1
);


  localparam time CyclTime = 10ns;
  localparam time ApplTime = 2ns;
  localparam time TestTime = 8ns;

  typedef logic [15:0] payload_t;



  logic     clk,       rst_n,      sim_done;
  payload_t req,       resp,       mem_req,       mem_resp;
  logic     req_valid, resp_valid, mem_req_valid, mem_resp_valid;
  logic     req_ready, resp_ready, mem_req_ready;


  payload_t data_fifo[$];


  initial begin : proc_stream_master
    automatic payload_t    test_data;
    automatic int unsigned stall_cycles;
    @(posedge rst_n);
    req       = '0;
    req_valid = '0;
    repeat (5) @(posedge clk);
    for (int unsigned i = 0; i < NumReq; i++) begin
      stall_cycles = $urandom_range(0, 5);
      repeat (stall_cycles) @(posedge clk);
      test_data = payload_t'($urandom());
      data_fifo.push_back(test_data);
      req       <= #ApplTime payload_t'(test_data);
      req_valid <= #ApplTime 1'b1;
      #TestTime;
      while (!req_ready) begin
        @(posedge clk);
        #TestTime;
      end
      @(posedge clk);
      req       <= #ApplTime '0;
      req_valid <= #ApplTime 1'b0;
    end
  end


  initial begin : proc_stream_slave
    automatic int unsigned stall_cycles;
    automatic payload_t    test_data;
    automatic int unsigned num_tested = 32'd0;
    sim_done = 0;
    @(posedge rst_n);
    resp_ready = '0;
    repeat (5) @(posedge clk);
    while (num_tested < NumReq) begin
      resp_ready <= #ApplTime $urandom();
      #TestTime;
      if (resp_valid && resp_ready) begin
        test_data = data_fifo.pop_front();
        assert(test_data === resp) else $error("test_data: %h, resp_data: %0h", test_data, resp);
        num_tested++;
      end
      @(posedge clk);
    end
    repeat (50) @(posedge clk);
    sim_done = 1'b1;
  end


  initial begin : proc_mem_reflect
    automatic payload_t reflect_fifo[$];
    @(posedge rst_n);
    mem_req_ready  = '0;
    mem_resp       = '0;
    mem_resp_valid = '0;
    forever begin
      mem_req_ready <= #ApplTime $urandom();
      #(CyclTime / 2);
      if (mem_req_valid && mem_req_ready) begin
        reflect_fifo.push_back(mem_req);

        fork
          begin
            if (BufDepth) begin
              repeat (BufDepth) @(posedge clk);
              #ApplTime;
            end
            mem_resp       = reflect_fifo.pop_front();
            mem_resp_valid = 1'b1;
            @(posedge clk);
            #(ApplTime / 2);
            mem_resp_valid = 1'b0;
          end
        join_none
      end
      @(posedge clk);
    end
  end


  initial begin : proc_sim_stop
    @(posedge rst_n);
    wait (sim_done);
    $stop();
  end


  clk_rst_gen #(
    .ClkPeriod    ( CyclTime ),
    .RstClkCycles ( 10       )
  ) i_clk_rst_gen (
    .clk_o  ( clk   ),
    .rst_no ( rst_n )
  );


  stream_to_mem #(
    .mem_req_t  ( payload_t ),
    .mem_resp_t ( payload_t ),
    .BufDepth   ( BufDepth  )
  ) i_stream_to_mem_dut (
    .clk_i            ( clk            ),
    .rst_ni           ( rst_n          ),
    .req_i            ( req            ),
    .req_valid_i      ( req_valid      ),
    .req_ready_o      ( req_ready      ),
    .resp_o           ( resp           ),
    .resp_valid_o     ( resp_valid     ),
    .resp_ready_i     ( resp_ready     ),
    .mem_req_o        ( mem_req        ),
    .mem_req_valid_o  ( mem_req_valid  ),
    .mem_req_ready_i  ( mem_req_ready  ),
    .mem_resp_i       ( mem_resp       ),
    .mem_resp_valid_i ( mem_resp_valid )
  );

endmodule