data/full_repos/permissive/529642835/rtl/Clock.v
data/verilator_xmls/a1de65fa-48fd-4eb7-b2ca-bf407254caa5.xml
module Clock
(
   input clk,
   input reset_n,
   
   output ce5,
   output ce1H,
   output ce2H, cm2H,
   
   output reg ce2Hd, ce2Hd2, ce2Hd3, ce2Hd4, ce2Hd5

);





reg [2:0] count;
always @(posedge clk or negedge reset_n)
begin
   if (~reset_n)
     count <= #1 3'b000;
   else 
      count <= #1 count + 3'b001;
end

assign ce5 = count[0];
assign ce1H = count == 1 || count == 5;
assign ce2H = count == 7;
assign cm2H = count[2];

always @(posedge clk) 
begin 
   ce2Hd <= #1 ce2H;
   ce2Hd2 <= #1 ce2Hd;
   ce2Hd3 <= #1 ce2Hd2;
   ce2Hd4 <= #1 ce2Hd3;
   ce2Hd5 <= #1 ce2Hd4;
end


endmodule
module Clock
(
   input clk,
   input reset_n,
   
   output ce5,
   output ce1H,
   output ce2H, cm2H,
   
   output reg ce2Hd, ce2Hd2, ce2Hd3, ce2Hd4, ce2Hd5

);






reg [2:0] count;
always @(posedge clk or negedge reset_n)
begin
   if (~reset_n)
     count <= #1 3'b000;
   else 
      count <= #1 count + 3'b001;
end

assign ce5 = count[0];
assign ce1H = count == 1 || count == 5;
assign ce2H = count == 7;
assign cm2H = count[2];

always @(posedge clk) 
begin 
   ce2Hd <= #1 ce2H;
   ce2Hd2 <= #1 ce2Hd;
   ce2Hd3 <= #1 ce2Hd2;
   ce2Hd4 <= #1 ce2Hd3;
   ce2Hd5 <= #1 ce2Hd4;
end


endmodule