data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:63: Define or directive not defined: '`IOB_RESET_STAT_WIDTH'\n   input [`IOB_RESET_STAT_WIDTH-1:0]clspine_iob_resetstat; \n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:72: Define or directive not defined: '`IOB_CPU_WIDTH'\n   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:92: Define or directive not defined: '`JBI_IOB_MONDO_BUS_WIDTH'\n   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data; \n          ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:101: Define or directive not defined: '`PCX_WIDTH'\n   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:123: Define or directive not defined: '`CPX_WIDTH'\n   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:124: Define or directive not defined: '`IOB_CPU_WIDTH'\n   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:125: Define or directive not defined: '`IOB_CPU_WIDTH'\n   output [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail; \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:136: Define or directive not defined: '`CLK_IOB_WIDTH'\n   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:139: Define or directive not defined: '`DRAM_IOB_WIDTH'\n   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:142: Define or directive not defined: '`DRAM_IOB_WIDTH'\n   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:145: Define or directive not defined: '`JBI_IOB_WIDTH'\n   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:148: Define or directive not defined: '`SPI_IOB_WIDTH'\n   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:151: Define or directive not defined: '`TAP_IOB_WIDTH'\n   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:155: Define or directive not defined: '`IOB_CLK_WIDTH'\n   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:158: Define or directive not defined: '`IOB_DRAM_WIDTH'\n   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;  \n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:161: Define or directive not defined: '`IOB_DRAM_WIDTH'\n   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;  \n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:164: Define or directive not defined: '`IOB_JBI_WIDTH'\n   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:167: Define or directive not defined: '`IOB_SPI_WIDTH'\n   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:170: Define or directive not defined: '`IOB_TAP_WIDTH'\n   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:182: Define or directive not defined: '`IOB_CPU_WIDTH'\n   reg [`IOB_CPU_WIDTH-1:0]      cpx_req;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:183: Define or directive not defined: '`CPX_WIDTH'\n   reg [`CPX_WIDTH-1:0]      cpx_data;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:185: Define or directive not defined: '`IOB_JBI_WIDTH'\n   reg [`IOB_JBI_WIDTH-1:0]      pio_data;      \n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:217: Define or directive not defined: '`PCX_WIDTH'\n   wire  [`PCX_WIDTH-1:0]           pcx_iob_data        = pcx_iob_data_px2;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:218: Define or directive not defined: '`IOB_CPU_WIDTH'\n   wire  [`IOB_CPU_WIDTH-1:0]       cpx_iob_grant       = cpx_iob_grant_cx2; \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:287: Unsupported or unknown PLI call: $init_iob_model\n $init_iob_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:289: syntax error, unexpected '@'\n repeat(1)@(posedge ctu_iob_wake_thr);\n          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:297: Unsupported or unknown PLI call: $iob_cdriver\n    $iob_cdriver( \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ciop_iob.v:328: Unsupported or unknown PLI call: $iob_jdriver\n $iob_jdriver(\n ^~~~~~~~~~~~\n%Error: Exiting due to 28 error(s)\n"
module ciop_iob(

   iob_pcx_stall_pq, iob_jbi_mondo_nack, iob_jbi_mondo_ack, 
   iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld, 
   iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data, 
   iob_ctu_coreavail, iob_cpx_req_cq, iob_cpx_data_ca, iob_clk_tr, 
   iob_clk_l2_tr, iob_clk_data, iob_clk_stall, iob_clk_vld, 
   iob_dram02_data, iob_dram02_stall, iob_dram02_vld, 
   iob_dram13_data, iob_dram13_stall, iob_dram13_vld, 
   iob_jbi_pio_data, iob_jbi_pio_stall, iob_jbi_pio_vld, 
   iob_jbi_spi_data, iob_jbi_spi_stall, iob_jbi_spi_vld, 
   iob_tap_data, iob_tap_stall, iob_tap_vld, iob_scanout, 
   iob_io_dbg_ck_p, iob_io_dbg_ck_n, 

   pcx_iob_data_rdy_px2, pcx_iob_data_px2, l2_dbgbus_23, 
   l2_dbgbus_01, jbus_grst_l, jbus_gdbginit_l, jbus_gclk, 
   jbus_arst_l, jbus_adbginit_l, jbi_iob_mondo_vld, 
   jbi_iob_mondo_data, io_trigin, io_temp_trig, global_shift_enable, 
   efc_iob_sernum2_dshift, efc_iob_sernum1_dshift, 
   efc_iob_sernum0_dshift, efc_iob_fusestat_dshift, 
   efc_iob_fuse_data, efc_iob_fuse_clk2, efc_iob_fuse_clk1, 
   efc_iob_coreavail_dshift, dbg_en_23, dbg_en_01, 
   ctu_tst_short_chain, ctu_tst_scanmode, ctu_tst_scan_disable, 
   ctu_tst_pre_grst_l, ctu_tst_macrotest, ctu_iob_wake_thr, 
   cpx_iob_grant_cx2, cmp_grst_l, cmp_gdbginit_l, cmp_gclk, 
   cmp_arst_l, cmp_adbginit_l, clspine_jbus_tx_sync, 
   clspine_jbus_rx_sync, clspine_iob_resetstat_wr, 
   clspine_iob_resetstat, clk_iob_cken, clk_iob_data, clk_iob_stall, 
   clk_iob_vld, dram02_iob_data, dram02_iob_stall, dram02_iob_vld, 
   dram13_iob_data, dram13_iob_stall, dram13_iob_vld, 
   jbi_iob_pio_data, jbi_iob_pio_stall, jbi_iob_pio_vld, 
   jbi_iob_spi_data, jbi_iob_spi_stall, jbi_iob_spi_vld, 
   tap_iob_data, tap_iob_stall, tap_iob_vld, iob_scanin,
   spc0_inst_done, pc_w0, spc1_inst_done, pc_w1, spc2_inst_done, 
   pc_w2, spc3_inst_done, pc_w3, spc4_inst_done, pc_w4, 
   spc5_inst_done, pc_w5, spc6_inst_done, pc_w6, spc7_inst_done, 
   pc_w7
   );

   input		clk_iob_cken;
   input [`IOB_RESET_STAT_WIDTH-1:0]clspine_iob_resetstat;
   input		clspine_iob_resetstat_wr;
   input		clspine_jbus_rx_sync;
   input		clspine_jbus_tx_sync;
   input		cmp_adbginit_l;
   input		cmp_arst_l;
   input		cmp_gclk;
   input		cmp_gdbginit_l;
   input		cmp_grst_l;
   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;
   input		ctu_iob_wake_thr;
   input		ctu_tst_macrotest;
   input		ctu_tst_pre_grst_l;
   input		ctu_tst_scan_disable;
   input		ctu_tst_scanmode;
   input		ctu_tst_short_chain;
   input		dbg_en_01;
   input		dbg_en_23;
   input		efc_iob_coreavail_dshift;
   input		efc_iob_fuse_clk1;
   input		efc_iob_fuse_clk2;
   input		efc_iob_fuse_data;
   input		efc_iob_fusestat_dshift;
   input		efc_iob_sernum0_dshift;
   input		efc_iob_sernum1_dshift;
   input		efc_iob_sernum2_dshift;
   input		global_shift_enable;
   input		io_temp_trig;
   input		io_trigin;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;
   input		jbi_iob_mondo_vld;
   input		jbus_adbginit_l;
   input		jbus_arst_l;
   input		jbus_gclk;
   input		jbus_gdbginit_l;
   input		jbus_grst_l;
   input [39:0]		l2_dbgbus_01;
   input [39:0]		l2_dbgbus_23;
   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;
   input		pcx_iob_data_rdy_px2;

   input                spc0_inst_done;
   input [48:0]         pc_w0;
   input                spc1_inst_done;
   input [48:0]         pc_w1;
   input                spc2_inst_done;
   input [48:0]         pc_w2;
   input                spc3_inst_done;
   input [48:0]         pc_w3;
   input                spc4_inst_done;
   input [48:0]         pc_w4;
   input                spc5_inst_done;
   input [48:0]         pc_w5;
   input                spc6_inst_done;
   input [48:0]         pc_w6;
   input                spc7_inst_done;
   input [48:0]         pc_w7;          

   output		iob_clk_l2_tr;
   output		iob_clk_tr;
   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;
   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;
   output [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail;
   output [39:0]	iob_io_dbg_data;
   output		iob_io_dbg_en;
   output [47:0]	iob_jbi_dbg_hi_data;
   output		iob_jbi_dbg_hi_vld;
   output [47:0]	iob_jbi_dbg_lo_data;
   output		iob_jbi_dbg_lo_vld;
   output		iob_jbi_mondo_ack;
   output		iob_jbi_mondo_nack;
   output		iob_pcx_stall_pq;

   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_stall;
   input		clk_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_stall;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_stall;
   input		dram13_iob_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_stall;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_stall;
   input		jbi_iob_spi_vld;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_stall;
   input		tap_iob_vld;

   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   output		iob_clk_stall;
   output		iob_clk_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   output		iob_dram02_stall;
   output		iob_dram02_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   output		iob_dram13_stall;
   output		iob_dram13_vld;
   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   output		iob_jbi_pio_stall;
   output		iob_jbi_pio_vld;
   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   output		iob_jbi_spi_stall;
   output		iob_jbi_spi_vld;
   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   output		iob_tap_stall;
   output		iob_tap_vld;

   input 	  iob_scanin;
   output         iob_scanout;
   
   output [2:0]	  iob_io_dbg_ck_p;
   output [2:0]   iob_io_dbg_ck_n;
   


   reg [`IOB_CPU_WIDTH-1:0] 	    cpx_req;
   reg [`CPX_WIDTH-1:0] 	    cpx_data;
   reg 				    pio_vld;
   reg [`IOB_JBI_WIDTH-1:0] 	    pio_data;		    

   reg [3:0] 			    jspi_data;
   reg 				    jspi_stall;
   reg 				    jspi_vld;

   reg [3:0] 			    dram02_data;
   reg 				    dram02_vld;
   reg [3:0] 			    dram13_data;
   reg 				    dram13_vld;
  
   wire 			    iob_pcx_stall_pq;
   wire 			    iob_jbi_pio_stall;
   wire 			    iob_jbi_dbg_hi_vld;
   wire 			    iob_jbi_dbg_lo_vld;
   wire 			    iob_jbi_mondo_ack;
   wire 			    iob_jbi_mondo_nack;
   wire 			    iob_clk_stall;
   wire 			    iob_clk_vld;
   wire 			    iob_clspine_stall;
   wire 			    iob_clspine_vld;
   wire 			    iob_dram02_stall;
   wire 			    iob_dram02_vld;
   wire 			    iob_dram13_stall;
   wire 			    iob_dram13_vld;
   
   wire 			    iob_jbi_spi_stall;
   wire 			    iob_jbi_spi_vld;
   wire 			    iob_tap_stall;
   wire 			    iob_tap_vld;
   

   wire  [`PCX_WIDTH-1:0]           pcx_iob_data        = pcx_iob_data_px2;
   wire  [`IOB_CPU_WIDTH-1:0]       cpx_iob_grant       = cpx_iob_grant_cx2;	
   wire                             spc0_inst_done_buf  = spc0_inst_done;
   wire [48:0]                      pc_w0_buf           = pc_w0;
   wire                             spc1_inst_done_buf  = spc1_inst_done;
   wire [48:0]                      pc_w1_buf           = pc_w1;
   wire                             spc2_inst_done_buf  = spc2_inst_done;
   wire [48:0]                      pc_w2_buf           = pc_w2;
   wire                             spc3_inst_done_buf  = spc3_inst_done;
   wire [48:0]                      pc_w3_buf           = pc_w3;
   wire                             spc4_inst_done_buf  = spc4_inst_done;
   wire [48:0]                      pc_w4_buf           = pc_w4;
   wire                             spc5_inst_done_buf  = spc5_inst_done;
   wire [48:0]                      pc_w5_buf           = pc_w5;
   wire                             spc6_inst_done_buf  = spc6_inst_done;
   wire [48:0]                      pc_w6_buf           = pc_w6;
   wire                             spc7_inst_done_buf  = spc7_inst_done;
   wire [48:0]                      pc_w7_buf           = pc_w7;          


   assign 			    iob_pcx_stall_pq    = 0;
   assign 			    iob_jbi_pio_stall   = 0;
   assign 			    iob_cpx_req_cq      = cpx_req;
   assign 			    iob_cpx_data_ca     = cpx_data;
   assign 			    iob_jbi_pio_vld     = pio_vld;
   assign 			    iob_jbi_pio_data    = pio_data;
   assign 			    iob_jbi_dbg_hi_vld  = 0;
   assign 			    iob_jbi_dbg_lo_vld  = 0;
   assign 			    iob_jbi_mondo_ack   = 0;
   assign 			    iob_jbi_mondo_nack  = 0;
   assign 			    iob_clk_stall       = 0;
   assign 			    iob_clk_vld         = 0;
   assign 			    iob_clspine_stall   = 0;
   assign 			    iob_clspine_vld     = 0;
   assign 			    iob_dram02_stall    = 0;
   assign 			    iob_dram02_vld      = dram02_vld;
   assign 			    iob_dram02_data     = dram02_data;
   assign 			    iob_dram13_stall    = 0;
   assign 			    iob_dram13_vld      = dram13_vld;
   assign 			    iob_dram13_data     = dram13_data;
   assign 			    iob_jbi_spi_stall   = 0;
   assign 			    iob_jbi_spi_vld     = 0;
   assign 			    iob_tap_stall       = 0;
   assign 			    iob_tap_vld         = 0;


   assign 			    iob_jbi_spi_stall   = 0;
   assign 			    iob_jbi_spi_vld     = jspi_vld;
   assign 			    iob_jbi_spi_data    = jspi_data;
   
 

   reg 	 ok_iob;
   initial
     begin
   	ok_iob    = 0;
	cpx_req   = 0;
	cpx_data  = 0;
	pio_vld   = 0;
	

	dram02_data = 0;
   	dram02_vld  = 0;

  	dram13_data = 0;
 	dram13_vld  = 0;

	jspi_vld    = 0;
	jspi_data   = 0;
	
	$init_iob_model();

	repeat(1)@(posedge ctu_iob_wake_thr);

   	ok_iob      = 1;
     end

   always @(negedge cmp_gclk)
     begin
	if(ok_iob)begin
	   $iob_cdriver(

		      pcx_iob_data,

		      cpx_req,
		      cpx_data,

		      cpx_iob_grant,

		      spc0_inst_done_buf,
		      pc_w0_buf,
		      spc1_inst_done_buf,
		      pc_w1_buf,
		      spc2_inst_done_buf,
		      pc_w2_buf,
		      spc3_inst_done_buf,
		      pc_w3_buf,
		      spc4_inst_done_buf,
		      pc_w4_buf,
		      spc5_inst_done_buf,
		      pc_w5_buf,
		      spc6_inst_done_buf,
		      pc_w6_buf,
		      spc7_inst_done_buf,
		      pc_w7_buf
		      );
	end
      end

  always @(posedge jbus_gclk)begin
     if(ok_iob)begin
	$iob_jdriver(
		     pio_vld, pio_data,


		     dram02_iob_stall, dram02_vld, dram02_data,
		     dram13_iob_stall, dram13_vld, dram13_data,

		     dram02_iob_vld,  dram02_iob_data,
		     dram13_iob_vld,  dram13_iob_data,

		     jbi_iob_pio_vld, jbi_iob_pio_data,


		     jbi_iob_spi_stall, jspi_vld, jspi_data,

		     jbi_iob_spi_vld, jbi_iob_spi_data
		     );
     end
    end
endmodule
module ciop_iob(

   iob_pcx_stall_pq, iob_jbi_mondo_nack, iob_jbi_mondo_ack, 
   iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld, 
   iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data, 
   iob_ctu_coreavail, iob_cpx_req_cq, iob_cpx_data_ca, iob_clk_tr, 
   iob_clk_l2_tr, iob_clk_data, iob_clk_stall, iob_clk_vld, 
   iob_dram02_data, iob_dram02_stall, iob_dram02_vld, 
   iob_dram13_data, iob_dram13_stall, iob_dram13_vld, 
   iob_jbi_pio_data, iob_jbi_pio_stall, iob_jbi_pio_vld, 
   iob_jbi_spi_data, iob_jbi_spi_stall, iob_jbi_spi_vld, 
   iob_tap_data, iob_tap_stall, iob_tap_vld, iob_scanout, 
   iob_io_dbg_ck_p, iob_io_dbg_ck_n, 

   pcx_iob_data_rdy_px2, pcx_iob_data_px2, l2_dbgbus_23, 
   l2_dbgbus_01, jbus_grst_l, jbus_gdbginit_l, jbus_gclk, 
   jbus_arst_l, jbus_adbginit_l, jbi_iob_mondo_vld, 
   jbi_iob_mondo_data, io_trigin, io_temp_trig, global_shift_enable, 
   efc_iob_sernum2_dshift, efc_iob_sernum1_dshift, 
   efc_iob_sernum0_dshift, efc_iob_fusestat_dshift, 
   efc_iob_fuse_data, efc_iob_fuse_clk2, efc_iob_fuse_clk1, 
   efc_iob_coreavail_dshift, dbg_en_23, dbg_en_01, 
   ctu_tst_short_chain, ctu_tst_scanmode, ctu_tst_scan_disable, 
   ctu_tst_pre_grst_l, ctu_tst_macrotest, ctu_iob_wake_thr, 
   cpx_iob_grant_cx2, cmp_grst_l, cmp_gdbginit_l, cmp_gclk, 
   cmp_arst_l, cmp_adbginit_l, clspine_jbus_tx_sync, 
   clspine_jbus_rx_sync, clspine_iob_resetstat_wr, 
   clspine_iob_resetstat, clk_iob_cken, clk_iob_data, clk_iob_stall, 
   clk_iob_vld, dram02_iob_data, dram02_iob_stall, dram02_iob_vld, 
   dram13_iob_data, dram13_iob_stall, dram13_iob_vld, 
   jbi_iob_pio_data, jbi_iob_pio_stall, jbi_iob_pio_vld, 
   jbi_iob_spi_data, jbi_iob_spi_stall, jbi_iob_spi_vld, 
   tap_iob_data, tap_iob_stall, tap_iob_vld, iob_scanin,
   spc0_inst_done, pc_w0, spc1_inst_done, pc_w1, spc2_inst_done, 
   pc_w2, spc3_inst_done, pc_w3, spc4_inst_done, pc_w4, 
   spc5_inst_done, pc_w5, spc6_inst_done, pc_w6, spc7_inst_done, 
   pc_w7
   );


   input		clk_iob_cken;
   input [`IOB_RESET_STAT_WIDTH-1:0]clspine_iob_resetstat;
   input		clspine_iob_resetstat_wr;
   input		clspine_jbus_rx_sync;
   input		clspine_jbus_tx_sync;
   input		cmp_adbginit_l;
   input		cmp_arst_l;
   input		cmp_gclk;
   input		cmp_gdbginit_l;
   input		cmp_grst_l;
   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;
   input		ctu_iob_wake_thr;
   input		ctu_tst_macrotest;
   input		ctu_tst_pre_grst_l;
   input		ctu_tst_scan_disable;
   input		ctu_tst_scanmode;
   input		ctu_tst_short_chain;
   input		dbg_en_01;
   input		dbg_en_23;
   input		efc_iob_coreavail_dshift;
   input		efc_iob_fuse_clk1;
   input		efc_iob_fuse_clk2;
   input		efc_iob_fuse_data;
   input		efc_iob_fusestat_dshift;
   input		efc_iob_sernum0_dshift;
   input		efc_iob_sernum1_dshift;
   input		efc_iob_sernum2_dshift;
   input		global_shift_enable;
   input		io_temp_trig;
   input		io_trigin;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;
   input		jbi_iob_mondo_vld;
   input		jbus_adbginit_l;
   input		jbus_arst_l;
   input		jbus_gclk;
   input		jbus_gdbginit_l;
   input		jbus_grst_l;
   input [39:0]		l2_dbgbus_01;
   input [39:0]		l2_dbgbus_23;
   input [`PCX_WIDTH-1:0]pcx_iob_data_px2;
   input		pcx_iob_data_rdy_px2;

   input                spc0_inst_done;
   input [48:0]         pc_w0;
   input                spc1_inst_done;
   input [48:0]         pc_w1;
   input                spc2_inst_done;
   input [48:0]         pc_w2;
   input                spc3_inst_done;
   input [48:0]         pc_w3;
   input                spc4_inst_done;
   input [48:0]         pc_w4;
   input                spc5_inst_done;
   input [48:0]         pc_w5;
   input                spc6_inst_done;
   input [48:0]         pc_w6;
   input                spc7_inst_done;
   input [48:0]         pc_w7;          

   output		iob_clk_l2_tr;
   output		iob_clk_tr;
   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;
   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;
   output [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail;
   output [39:0]	iob_io_dbg_data;
   output		iob_io_dbg_en;
   output [47:0]	iob_jbi_dbg_hi_data;
   output		iob_jbi_dbg_hi_vld;
   output [47:0]	iob_jbi_dbg_lo_data;
   output		iob_jbi_dbg_lo_vld;
   output		iob_jbi_mondo_ack;
   output		iob_jbi_mondo_nack;
   output		iob_pcx_stall_pq;

   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_stall;
   input		clk_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_stall;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_stall;
   input		dram13_iob_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_stall;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_stall;
   input		jbi_iob_spi_vld;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_stall;
   input		tap_iob_vld;

   output [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   output		iob_clk_stall;
   output		iob_clk_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   output		iob_dram02_stall;
   output		iob_dram02_vld;
   output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   output		iob_dram13_stall;
   output		iob_dram13_vld;
   output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   output		iob_jbi_pio_stall;
   output		iob_jbi_pio_vld;
   output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   output		iob_jbi_spi_stall;
   output		iob_jbi_spi_vld;
   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   output		iob_tap_stall;
   output		iob_tap_vld;

   input 	  iob_scanin;
   output         iob_scanout;
   
   output [2:0]	  iob_io_dbg_ck_p;
   output [2:0]   iob_io_dbg_ck_n;
   


   reg [`IOB_CPU_WIDTH-1:0] 	    cpx_req;
   reg [`CPX_WIDTH-1:0] 	    cpx_data;
   reg 				    pio_vld;
   reg [`IOB_JBI_WIDTH-1:0] 	    pio_data;		    

   reg [3:0] 			    jspi_data;
   reg 				    jspi_stall;
   reg 				    jspi_vld;

   reg [3:0] 			    dram02_data;
   reg 				    dram02_vld;
   reg [3:0] 			    dram13_data;
   reg 				    dram13_vld;
  
   wire 			    iob_pcx_stall_pq;
   wire 			    iob_jbi_pio_stall;
   wire 			    iob_jbi_dbg_hi_vld;
   wire 			    iob_jbi_dbg_lo_vld;
   wire 			    iob_jbi_mondo_ack;
   wire 			    iob_jbi_mondo_nack;
   wire 			    iob_clk_stall;
   wire 			    iob_clk_vld;
   wire 			    iob_clspine_stall;
   wire 			    iob_clspine_vld;
   wire 			    iob_dram02_stall;
   wire 			    iob_dram02_vld;
   wire 			    iob_dram13_stall;
   wire 			    iob_dram13_vld;
   
   wire 			    iob_jbi_spi_stall;
   wire 			    iob_jbi_spi_vld;
   wire 			    iob_tap_stall;
   wire 			    iob_tap_vld;
   

   wire  [`PCX_WIDTH-1:0]           pcx_iob_data        = pcx_iob_data_px2;
   wire  [`IOB_CPU_WIDTH-1:0]       cpx_iob_grant       = cpx_iob_grant_cx2;	
   wire                             spc0_inst_done_buf  = spc0_inst_done;
   wire [48:0]                      pc_w0_buf           = pc_w0;
   wire                             spc1_inst_done_buf  = spc1_inst_done;
   wire [48:0]                      pc_w1_buf           = pc_w1;
   wire                             spc2_inst_done_buf  = spc2_inst_done;
   wire [48:0]                      pc_w2_buf           = pc_w2;
   wire                             spc3_inst_done_buf  = spc3_inst_done;
   wire [48:0]                      pc_w3_buf           = pc_w3;
   wire                             spc4_inst_done_buf  = spc4_inst_done;
   wire [48:0]                      pc_w4_buf           = pc_w4;
   wire                             spc5_inst_done_buf  = spc5_inst_done;
   wire [48:0]                      pc_w5_buf           = pc_w5;
   wire                             spc6_inst_done_buf  = spc6_inst_done;
   wire [48:0]                      pc_w6_buf           = pc_w6;
   wire                             spc7_inst_done_buf  = spc7_inst_done;
   wire [48:0]                      pc_w7_buf           = pc_w7;          


   assign 			    iob_pcx_stall_pq    = 0;
   assign 			    iob_jbi_pio_stall   = 0;
   assign 			    iob_cpx_req_cq      = cpx_req;
   assign 			    iob_cpx_data_ca     = cpx_data;
   assign 			    iob_jbi_pio_vld     = pio_vld;
   assign 			    iob_jbi_pio_data    = pio_data;
   assign 			    iob_jbi_dbg_hi_vld  = 0;
   assign 			    iob_jbi_dbg_lo_vld  = 0;
   assign 			    iob_jbi_mondo_ack   = 0;
   assign 			    iob_jbi_mondo_nack  = 0;
   assign 			    iob_clk_stall       = 0;
   assign 			    iob_clk_vld         = 0;
   assign 			    iob_clspine_stall   = 0;
   assign 			    iob_clspine_vld     = 0;
   assign 			    iob_dram02_stall    = 0;
   assign 			    iob_dram02_vld      = dram02_vld;
   assign 			    iob_dram02_data     = dram02_data;
   assign 			    iob_dram13_stall    = 0;
   assign 			    iob_dram13_vld      = dram13_vld;
   assign 			    iob_dram13_data     = dram13_data;
   assign 			    iob_jbi_spi_stall   = 0;
   assign 			    iob_jbi_spi_vld     = 0;
   assign 			    iob_tap_stall       = 0;
   assign 			    iob_tap_vld         = 0;


   assign 			    iob_jbi_spi_stall   = 0;
   assign 			    iob_jbi_spi_vld     = jspi_vld;
   assign 			    iob_jbi_spi_data    = jspi_data;
   
 

   reg 	 ok_iob;
   initial
     begin
   	ok_iob    = 0;
	cpx_req   = 0;
	cpx_data  = 0;
	pio_vld   = 0;
	

	dram02_data = 0;
   	dram02_vld  = 0;

  	dram13_data = 0;
 	dram13_vld  = 0;

	jspi_vld    = 0;
	jspi_data   = 0;
	
	$init_iob_model();

	repeat(1)@(posedge ctu_iob_wake_thr);

   	ok_iob      = 1;
     end

   always @(negedge cmp_gclk)
     begin
	if(ok_iob)begin
	   $iob_cdriver(

		      pcx_iob_data,

		      cpx_req,
		      cpx_data,

		      cpx_iob_grant,

		      spc0_inst_done_buf,
		      pc_w0_buf,
		      spc1_inst_done_buf,
		      pc_w1_buf,
		      spc2_inst_done_buf,
		      pc_w2_buf,
		      spc3_inst_done_buf,
		      pc_w3_buf,
		      spc4_inst_done_buf,
		      pc_w4_buf,
		      spc5_inst_done_buf,
		      pc_w5_buf,
		      spc6_inst_done_buf,
		      pc_w6_buf,
		      spc7_inst_done_buf,
		      pc_w7_buf
		      );
	end
      end

  always @(posedge jbus_gclk)begin
     if(ok_iob)begin
	$iob_jdriver(
		     pio_vld, pio_data,


		     dram02_iob_stall, dram02_vld, dram02_data,
		     dram13_iob_stall, dram13_vld, dram13_data,

		     dram02_iob_vld,  dram02_iob_data,
		     dram13_iob_vld,  dram13_iob_data,

		     jbi_iob_pio_vld, jbi_iob_pio_data,


		     jbi_iob_spi_stall, jspi_vld, jspi_data,

		     jbi_iob_spi_vld, jbi_iob_spi_data
		     );
     end
    end
endmodule