data/full_repos/permissive/529469310/RSA/Modulo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/529469310/RSA/Modulo.v:54: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                    : ... In instance Modulo\n            Hreg2 <= (diff[8]? Hreg2 : diff[8-1:0]);                      \n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Modulo(clk, start, busy, C, Hreg, Lreg, M);

input clk, start;
input [`Bit-1:0] C;
input [`Bit:0] Hreg;
input [`Bit-1:0] Lreg;
output busy;
output [`Bit-1:0] M;

reg busy;
reg [`Bit:0] Hreg2;
reg [`Bit-1:0] Lreg2;
reg [1:0] state;
reg [`BitN:0] count;
wire [`Bit-1:0] M;
wire [`Bit:0] diff;

assign M = Hreg2[`Bit-1:0];  
assign diff = Hreg2 - C;

always @(posedge clk or negedge start) begin
if(!start) begin
    busy <= 0;
    count <= `BitN1'd`Bit1;
    state <= 2'd`Init;
end else begin
    if(count != 0) begin
        if(state == `Init) begin
            Hreg2 <= Hreg;
            Lreg2 <= Lreg;
            busy <= 1;
            state <= `Sub;
        end else if(state == `Sub) begin
            Hreg2 <= (diff[`Bit]? Hreg2 : diff[`Bit-1:0]);                      
          	count <= count - 1;
            state <= `Shift;
        end else if(state == `Shift) begin
            {Hreg2, Lreg2} <= {Hreg2[`Bit-1:0], Lreg2[`Bit-1:0], 1'b0};
            state <= `Sub;
        end else begin
            busy <= 0;
        end
    end else begin
    busy <= 0;
    end
end
end

endmodule
module Modulo(clk, start, busy, C, Hreg, Lreg, M);


input clk, start;
input [`Bit-1:0] C;
input [`Bit:0] Hreg;
input [`Bit-1:0] Lreg;
output busy;
output [`Bit-1:0] M;

reg busy;
reg [`Bit:0] Hreg2;
reg [`Bit-1:0] Lreg2;
reg [1:0] state;
reg [`BitN:0] count;
wire [`Bit-1:0] M;
wire [`Bit:0] diff;

assign M = Hreg2[`Bit-1:0];  
assign diff = Hreg2 - C;

always @(posedge clk or negedge start) begin
if(!start) begin
    busy <= 0;
    count <= `BitN1'd`Bit1;
    state <= 2'd`Init;
end else begin
    if(count != 0) begin
        if(state == `Init) begin
            Hreg2 <= Hreg;
            Lreg2 <= Lreg;
            busy <= 1;
            state <= `Sub;
        end else if(state == `Sub) begin
            Hreg2 <= (diff[`Bit]? Hreg2 : diff[`Bit-1:0]);                      
          	count <= count - 1;
            state <= `Shift;
        end else if(state == `Shift) begin
            {Hreg2, Lreg2} <= {Hreg2[`Bit-1:0], Lreg2[`Bit-1:0], 1'b0};
            state <= `Sub;
        end else begin
            busy <= 0;
        end
    end else begin
    busy <= 0;
    end
end
end

endmodule