data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/light_control_TB.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/light_control_TB.v\n%Error: Exiting due to 7 error(s)\n'
module light_control_TB;

reg T0;
reg T1;
reg T2;
reg T3;
reg T4;
reg T5;
reg T6;
reg T7;
reg T8;
reg T9;

reg S0;
reg S1;
reg S2;
reg S3;
reg S4;

reg CLOCK;

wire rL_Maj, rMR_Maj, yA_Maj, yLR_Maj, gA_Maj, gLR_Maj,
     rLR_min, yA_min, yLR_min, gA_min, gLR_min,



light_control LC0(
	.T0(T0),
	.T1(T1),
	.T2(T2),
	.T3(T3),
	.T4(T4),
	.T5(T5),
	.T6(T6),
	.T7(T7),
	.T8(T8),
	.T9(T9),
	
	.S0(S0),
	.S1(S1),
	.S2(S2),
	.S3(S3),
	.S4(S4),
	
	.CLOCK(CLK_int),
	
	.rL_Maj(rL_Maj),
	.rMR_Maj(rMR_Maj),
	.yA_Maj(yA_Maj),
	.yLR_Maj(yLR_Maj),
	.gA_Maj(gA_Maj),
	.gLR_Maj(gLR_Maj),
	.rLR_min(rLR_min),
	.yA_min(yA_min),
	.yLR_min(yLR_min),
	.gA_min(gA_min),
	.gLR_min(gLR_min)	
);	 


always
  #10 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("light_control_TB.vcd") ;
  $dumpvars(0, light_control_TB) ;
end


initial
begin
	T0;
	T1;
	T2;
	T3;
	T4;
	T5;
	T6;
	T7;
	T8;
	T9;

	S0;
	S1;
	S2;
	S3;
	S4;

reg CLOCK;


  #5000 $finish ; 
end

endmodule
module light_control_TB;


reg T0;
reg T1;
reg T2;
reg T3;
reg T4;
reg T5;
reg T6;
reg T7;
reg T8;
reg T9;

reg S0;
reg S1;
reg S2;
reg S3;
reg S4;

reg CLOCK;

wire rL_Maj, rMR_Maj, yA_Maj, yLR_Maj, gA_Maj, gLR_Maj,
     rLR_min, yA_min, yLR_min, gA_min, gLR_min,



light_control LC0(
	.T0(T0),
	.T1(T1),
	.T2(T2),
	.T3(T3),
	.T4(T4),
	.T5(T5),
	.T6(T6),
	.T7(T7),
	.T8(T8),
	.T9(T9),
	
	.S0(S0),
	.S1(S1),
	.S2(S2),
	.S3(S3),
	.S4(S4),
	
	.CLOCK(CLK_int),
	
	.rL_Maj(rL_Maj),
	.rMR_Maj(rMR_Maj),
	.yA_Maj(yA_Maj),
	.yLR_Maj(yLR_Maj),
	.gA_Maj(gA_Maj),
	.gLR_Maj(gLR_Maj),
	.rLR_min(rLR_min),
	.yA_min(yA_min),
	.yLR_min(yLR_min),
	.gA_min(gA_min),
	.gLR_min(gLR_min)	
);	 


always
  #10 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("light_control_TB.vcd") ;
  $dumpvars(0, light_control_TB) ;
end


initial
begin
	T0;
	T1;
	T2;
	T3;
	T4;
	T5;
	T6;
	T7;
	T8;
	T9;

	S0;
	S1;
	S2;
	S3;
	S4;

reg CLOCK;


  #5000 $finish ; 
end

endmodule