data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/MEM.v
data/verilator_xmls/d754c4ff-1b6a-4be3-b4b1-6d1ce15663cb.xml
module MEM(    
    input clk,
    input MWE,
    input [31:0] MRA,
    input [31:0] MWD,
    output [31:0] MRD
    );
    
    reg [31:0] Memory [550:0];
    
    initial begin

        Memory[0] <= 17;
        Memory[1] <= 31;
        Memory[2] <= -5;
        Memory[3] <= -2;
        Memory[4] <= 250;
        


















       












        
















        

        Memory[500] <= 32'b00100000000100000000000000000000;
        Memory[501] <= 32'b00100000000100010000000000000101;
        Memory[502] <= 32'b00100000000100100000000000000001;
        Memory[503] <= 32'b00000000000000000101100000100000;
        Memory[504] <= 32'b00010010000100010000000000000110;
        Memory[505] <= 32'b10001110000010000000000000000000;
        Memory[506] <= 32'b00000010001010000100000000000100;
        Memory[507] <= 32'b10101110000010000000000000011111;
        Memory[508] <= 32'b00000010010100001000000000100000;
        Memory[509] <= 32'b00000001011010000101100000100000;
        Memory[510] <= 32'b00001000000000001111111111111001;
        Memory[511] <= 32'b00000000000000000000000000100000;
        Memory[512] <= 32'b00000000000000000000000000100000;
    end
    
    assign MRD = Memory[MRA];
    
    always@(posedge clk) begin
        if (MWE) begin
            Memory[MRA] <= MWD;
        end
    end
endmodule
module MEM(    
    input clk,
    input MWE,
    input [31:0] MRA,
    input [31:0] MWD,
    output [31:0] MRD
    );

    
    reg [31:0] Memory [550:0];
    
    initial begin

        Memory[0] <= 17;
        Memory[1] <= 31;
        Memory[2] <= -5;
        Memory[3] <= -2;
        Memory[4] <= 250;
        


















       












        
















        

        Memory[500] <= 32'b00100000000100000000000000000000;
        Memory[501] <= 32'b00100000000100010000000000000101;
        Memory[502] <= 32'b00100000000100100000000000000001;
        Memory[503] <= 32'b00000000000000000101100000100000;
        Memory[504] <= 32'b00010010000100010000000000000110;
        Memory[505] <= 32'b10001110000010000000000000000000;
        Memory[506] <= 32'b00000010001010000100000000000100;
        Memory[507] <= 32'b10101110000010000000000000011111;
        Memory[508] <= 32'b00000010010100001000000000100000;
        Memory[509] <= 32'b00000001011010000101100000100000;
        Memory[510] <= 32'b00001000000000001111111111111001;
        Memory[511] <= 32'b00000000000000000000000000100000;
        Memory[512] <= 32'b00000000000000000000000000100000;
    end
    
    assign MRD = Memory[MRA];
    
    always@(posedge clk) begin
        if (MWE) begin
            Memory[MRA] <= MWD;
        end
    end
endmodule