data/full_repos/permissive/528252229/ex.v
1: b'%Error: data/full_repos/permissive/528252229/ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/ex.v:8: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]          aluop_i,   \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus]          aluop_i,   \n                     ^\n%Error: data/full_repos/permissive/528252229/ex.v:9: Define or directive not defined: \'`AluSelBus\'\n input wire[`AluSelBus]         alusel_i,   \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:10: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]            reg1_i,          \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]            reg2_i,          \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:12: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]        wd_i,    \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:13: Define or directive not defined: \'`WriteBus\'\n input wire[`WriteBus]           wreg_i,    \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    return_addr_i,   \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    inst_i,          \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:16: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]  pc_i,            \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:19: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]         wd_o,           \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:20: Define or directive not defined: \'`WriteBus\'\n output reg[`WriteBus]           wreg_o,         \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:21: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]       wdata_o,     \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:23: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]   aluop_o,        \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:24: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]       mem_addr_o,     \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:25: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]       reg2_o,         \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:27: Define or directive not defined: \'`InstAddrBus\'\n output wire[`InstAddrBus]  pc_o,           \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:33: Define or directive not defined: \'`NoStop\'\n    assign stallreq = `NoStop;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:37: Define or directive not defined: \'`RstDisable\'\n  if(rst == `RstDisable) begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:38: Define or directive not defined: \'`ZeroRegAddr\'\n   wd_o   <= `ZeroRegAddr;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:39: Define or directive not defined: \'`WriteDisable\'\n   wreg_o   <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:40: Define or directive not defined: \'`ZeroWord\'\n   wdata_o  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:41: Define or directive not defined: \'`ALU_OP_NOP\'\n   aluop_o  <= `ALU_OP_NOP;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:42: Define or directive not defined: \'`ZeroWord\'\n   mem_addr_o  <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:43: Define or directive not defined: \'`ZeroWord\'\n   reg2_o   <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:48: Define or directive not defined: \'`ZeroWord\'\n   wdata_o  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:50: Define or directive not defined: \'`ZeroWord\'\n   mem_addr_o  <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:54: Define or directive not defined: \'`ALU_OP_ORI\'\n    `ALU_OP_ORI : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:57: Define or directive not defined: \'`ALU_OP_ANDI\'\n    `ALU_OP_ANDI : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:60: Define or directive not defined: \'`ALU_OP_XORI\'\n    `ALU_OP_XORI : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:63: Define or directive not defined: \'`ALU_OP_LUI\'\n    `ALU_OP_LUI : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:66: Define or directive not defined: \'`ALU_OP_ADDI\'\n    `ALU_OP_ADDI : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:70: Define or directive not defined: \'`ALU_OP_ADDIU\'\n    `ALU_OP_ADDIU : begin\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:73: Define or directive not defined: \'`ALU_OP_SLTI\'\n    `ALU_OP_SLTI : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:97: Define or directive not defined: \'`ALU_OP_SLTIU\'\n    `ALU_OP_SLTIU : begin\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:105: Define or directive not defined: \'`ALU_OP_J\'\n    `ALU_OP_J : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:108: Define or directive not defined: \'`ALU_OP_JAL\'\n    `ALU_OP_JAL : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:111: Define or directive not defined: \'`ALU_OP_BEQ\'\n    `ALU_OP_BEQ : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:114: Define or directive not defined: \'`ALU_OP_B\'\n    `ALU_OP_B : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:117: Define or directive not defined: \'`ALU_OP_BGTZ\'\n    `ALU_OP_BGTZ : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:120: Define or directive not defined: \'`ALU_OP_BLEZ\'\n    `ALU_OP_BLEZ : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:123: Define or directive not defined: \'`ALU_OP_BNE\'\n    `ALU_OP_BNE : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:126: Define or directive not defined: \'`ALU_OP_BLTZ\'\n    `ALU_OP_BLTZ : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:129: Define or directive not defined: \'`ALU_OP_BLTZAL\'\n    `ALU_OP_BLTZAL : begin\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:132: Define or directive not defined: \'`ALU_OP_BGEZ\'\n    `ALU_OP_BGEZ : begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:135: Define or directive not defined: \'`ALU_OP_BGEZAL\'\n    `ALU_OP_BGEZAL : begin\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:138: Define or directive not defined: \'`ALU_OP_BAL\'\n    `ALU_OP_BAL : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:141: Define or directive not defined: \'`ALU_OP_LW\'\n    `ALU_OP_LW : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/ex.v:144: Define or directive not defined: \'`ALU_OP_SW\'\n    `ALU_OP_SW : begin\n    ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(

	input wire						rst,
	

	input wire[`AluOpBus]         	aluop_i,
	input wire[`AluSelBus]        	alusel_i,
	input wire[`RegBus]           	reg1_i,
	input wire[`RegBus]           	reg2_i,
	input wire[`RegAddrBus]       	wd_i,
	input wire[`WriteBus]           wreg_i,
	input wire[`RegBus] 			return_addr_i,
	input wire[`RegBus]				inst_i,
	input wire[`InstAddrBus]		pc_i,
	

	output reg[`RegAddrBus]         wd_o,
	output reg[`WriteBus]           wreg_o,
	output reg[`RegBus]			    wdata_o,

	output reg[`AluOpBus]			aluop_o,
	output reg[`RegBus]			    mem_addr_o,
	output reg[`RegBus]			    reg2_o,

	output wire[`InstAddrBus]		pc_o,
	output wire 				    stallreq
	
);
	
	assign pc_o = pc_i;
    assign stallreq = `NoStop;

	always @(*) begin

		if(rst == `RstDisable) begin
			wd_o 		<= `ZeroRegAddr;
			wreg_o 		<= `WriteDisable;
			wdata_o 	<= `ZeroWord;
			aluop_o 	<= `ALU_OP_NOP;
			mem_addr_o 	<= `ZeroWord;
			reg2_o 		<= `ZeroWord;
		end
		else begin
			wd_o 		<= wd_i;
			wreg_o 		<= wreg_i;
			wdata_o 	<= `ZeroWord;
			aluop_o 	<= aluop_i;
			mem_addr_o 	<= `ZeroWord;
			reg2_o 		<= reg2_i;

			case(aluop_i)
				`ALU_OP_ORI :	begin
					wdata_o <= reg1_i | reg2_i;
				end
				`ALU_OP_ANDI :	begin
					wdata_o <= reg1_i & reg2_i;
				end
				`ALU_OP_XORI :	begin
					wdata_o <= reg1_i ^ reg2_i;
				end
				`ALU_OP_LUI :	begin
					wdata_o <= reg2_i << 16;
				end
				`ALU_OP_ADDI :	begin

					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_ADDIU :	begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SLTI :	begin
					if(reg1_i[31] < reg2_i[31]) begin
						wdata_o <= 0;
					end
					else if(reg1_i[31] > reg2_i[31]) begin
						wdata_o <= 1;
					end
					else if(reg1_i[31] == 1'b0) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
					else if(reg1_i[31] == 1'b1) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
				end
				`ALU_OP_SLTIU :	begin
					if(reg1_i < reg2_i) begin
						wdata_o <= 1;
					end
					else begin
						wdata_o <= 0;
					end
				end
				`ALU_OP_J :	begin

				end
				`ALU_OP_JAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BEQ :	begin
					
				end
				`ALU_OP_B :	begin

				end
				`ALU_OP_BGTZ :	begin

				end
				`ALU_OP_BLEZ :	begin

				end
				`ALU_OP_BNE :	begin

				end
				`ALU_OP_BLTZ :	begin
					
				end
				`ALU_OP_BLTZAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BGEZ :	begin

				end
				`ALU_OP_BGEZAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_LW :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SW :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
				end
				`ALU_OP_LB :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SB :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
				end
				`ALU_OP_LH :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SH :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
			end
			`ALU_OP_AND : begin
				    wdata_o <= reg1_i & reg2_i;
				end
				`ALU_OP_NOR : begin
					wdata_o <= ~(reg1_i | reg2_i);
				end
				`ALU_OP_OR : begin
					wdata_o <= reg1_i | reg2_i;
				end
				`ALU_OP_XOR : begin
					wdata_o <= reg1_i ^ reg2_i;
				end
				`ALU_OP_SLL : begin
					wdata_o <= reg2_i << reg1_i[10:6];
				end
				`ALU_OP_SLLV : begin
					wdata_o <= reg2_i << reg1_i[4:0];
				end
				`ALU_OP_SRL : begin
					wdata_o <= reg2_i >> reg1_i[10:6];
				end
				`ALU_OP_SRLV : begin
					wdata_o <= reg2_i >> reg1_i[4:0];
				end
				`ALU_OP_SRA : begin
					wdata_o <= ({32{reg2_i[31]}} << (6'd32 - {1'b0, reg1_i[10:6]})) | reg2_i >> reg1_i[10:6];
				end
				`ALU_OP_SRAV : begin
					wdata_o <= ({32{reg2_i[31]}} << (6'd32 - {1'b0, reg1_i[4:0]})) | reg2_i >> reg1_i[4:0];
				end
				`ALU_OP_NOP : begin

				end
				`ALU_OP_SSNOP : begin

				end
				`ALU_OP_SYNC : begin

				end
				`ALU_OP_MOVN : begin
					if(reg2_i != 0) begin
						wdata_o <= reg1_i;
					end
				end
				`ALU_OP_MOVZ : begin
					if(reg2_i == 0) begin
						wdata_o <= reg1_i;
					end
				end
				`ALU_OP_ADD : begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_ADDU : begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SUB : begin
					wdata_o <= reg1_i - reg2_i;
				end
				`ALU_OP_SUBU : begin
					wdata_o <= reg1_i - reg2_i;
				end
				`ALU_OP_SLT : begin
					if(reg1_i[31] < reg2_i[31]) begin
						wdata_o <= 0;
					end
					else if(reg1_i[31] > reg2_i[31]) begin
						wdata_o <= 1;
					end
					else if(reg1_i[31] == 1'b0) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
					else if(reg1_i[31] == 1'b1) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
				end
				`ALU_OP_SLTU : begin
					if(reg1_i < reg2_i) begin
						wdata_o <= 1;
					end
					else begin
						wdata_o <= 0;
					end
				end
				`ALU_OP_JR : begin
				
				end
				`ALU_OP_JALR : begin
					wdata_o <= return_addr_i;
				end
				default : begin

				end
			endcase
		end
	end
endmodule
module ex(

	input wire						rst,
	

	input wire[`AluOpBus]         	aluop_i,
	input wire[`AluSelBus]        	alusel_i,
	input wire[`RegBus]           	reg1_i,
	input wire[`RegBus]           	reg2_i,
	input wire[`RegAddrBus]       	wd_i,
	input wire[`WriteBus]           wreg_i,
	input wire[`RegBus] 			return_addr_i,
	input wire[`RegBus]				inst_i,
	input wire[`InstAddrBus]		pc_i,
	

	output reg[`RegAddrBus]         wd_o,
	output reg[`WriteBus]           wreg_o,
	output reg[`RegBus]			    wdata_o,

	output reg[`AluOpBus]			aluop_o,
	output reg[`RegBus]			    mem_addr_o,
	output reg[`RegBus]			    reg2_o,

	output wire[`InstAddrBus]		pc_o,
	output wire 				    stallreq
	
);

	
	assign pc_o = pc_i;
    assign stallreq = `NoStop;

	always @(*) begin

		if(rst == `RstDisable) begin
			wd_o 		<= `ZeroRegAddr;
			wreg_o 		<= `WriteDisable;
			wdata_o 	<= `ZeroWord;
			aluop_o 	<= `ALU_OP_NOP;
			mem_addr_o 	<= `ZeroWord;
			reg2_o 		<= `ZeroWord;
		end
		else begin
			wd_o 		<= wd_i;
			wreg_o 		<= wreg_i;
			wdata_o 	<= `ZeroWord;
			aluop_o 	<= aluop_i;
			mem_addr_o 	<= `ZeroWord;
			reg2_o 		<= reg2_i;

			case(aluop_i)
				`ALU_OP_ORI :	begin
					wdata_o <= reg1_i | reg2_i;
				end
				`ALU_OP_ANDI :	begin
					wdata_o <= reg1_i & reg2_i;
				end
				`ALU_OP_XORI :	begin
					wdata_o <= reg1_i ^ reg2_i;
				end
				`ALU_OP_LUI :	begin
					wdata_o <= reg2_i << 16;
				end
				`ALU_OP_ADDI :	begin

					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_ADDIU :	begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SLTI :	begin
					if(reg1_i[31] < reg2_i[31]) begin
						wdata_o <= 0;
					end
					else if(reg1_i[31] > reg2_i[31]) begin
						wdata_o <= 1;
					end
					else if(reg1_i[31] == 1'b0) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
					else if(reg1_i[31] == 1'b1) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
				end
				`ALU_OP_SLTIU :	begin
					if(reg1_i < reg2_i) begin
						wdata_o <= 1;
					end
					else begin
						wdata_o <= 0;
					end
				end
				`ALU_OP_J :	begin

				end
				`ALU_OP_JAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BEQ :	begin
					
				end
				`ALU_OP_B :	begin

				end
				`ALU_OP_BGTZ :	begin

				end
				`ALU_OP_BLEZ :	begin

				end
				`ALU_OP_BNE :	begin

				end
				`ALU_OP_BLTZ :	begin
					
				end
				`ALU_OP_BLTZAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BGEZ :	begin

				end
				`ALU_OP_BGEZAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_BAL :	begin
					wdata_o <= return_addr_i;
				end
				`ALU_OP_LW :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SW :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
				end
				`ALU_OP_LB :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SB :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
				end
				`ALU_OP_LH :	begin
					mem_addr_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SH :	begin
					mem_addr_o <= reg1_i;
					wdata_o <= reg2_i;
			end
			`ALU_OP_AND : begin
				    wdata_o <= reg1_i & reg2_i;
				end
				`ALU_OP_NOR : begin
					wdata_o <= ~(reg1_i | reg2_i);
				end
				`ALU_OP_OR : begin
					wdata_o <= reg1_i | reg2_i;
				end
				`ALU_OP_XOR : begin
					wdata_o <= reg1_i ^ reg2_i;
				end
				`ALU_OP_SLL : begin
					wdata_o <= reg2_i << reg1_i[10:6];
				end
				`ALU_OP_SLLV : begin
					wdata_o <= reg2_i << reg1_i[4:0];
				end
				`ALU_OP_SRL : begin
					wdata_o <= reg2_i >> reg1_i[10:6];
				end
				`ALU_OP_SRLV : begin
					wdata_o <= reg2_i >> reg1_i[4:0];
				end
				`ALU_OP_SRA : begin
					wdata_o <= ({32{reg2_i[31]}} << (6'd32 - {1'b0, reg1_i[10:6]})) | reg2_i >> reg1_i[10:6];
				end
				`ALU_OP_SRAV : begin
					wdata_o <= ({32{reg2_i[31]}} << (6'd32 - {1'b0, reg1_i[4:0]})) | reg2_i >> reg1_i[4:0];
				end
				`ALU_OP_NOP : begin

				end
				`ALU_OP_SSNOP : begin

				end
				`ALU_OP_SYNC : begin

				end
				`ALU_OP_MOVN : begin
					if(reg2_i != 0) begin
						wdata_o <= reg1_i;
					end
				end
				`ALU_OP_MOVZ : begin
					if(reg2_i == 0) begin
						wdata_o <= reg1_i;
					end
				end
				`ALU_OP_ADD : begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_ADDU : begin
					wdata_o <= reg1_i + reg2_i;
				end
				`ALU_OP_SUB : begin
					wdata_o <= reg1_i - reg2_i;
				end
				`ALU_OP_SUBU : begin
					wdata_o <= reg1_i - reg2_i;
				end
				`ALU_OP_SLT : begin
					if(reg1_i[31] < reg2_i[31]) begin
						wdata_o <= 0;
					end
					else if(reg1_i[31] > reg2_i[31]) begin
						wdata_o <= 1;
					end
					else if(reg1_i[31] == 1'b0) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
					else if(reg1_i[31] == 1'b1) begin
						if(reg1_i < reg2_i) begin
							wdata_o <= 1;
						end
						else begin
							wdata_o <= 0;
						end
					end
				end
				`ALU_OP_SLTU : begin
					if(reg1_i < reg2_i) begin
						wdata_o <= 1;
					end
					else begin
						wdata_o <= 0;
					end
				end
				`ALU_OP_JR : begin
				
				end
				`ALU_OP_JALR : begin
					wdata_o <= return_addr_i;
				end
				default : begin

				end
			endcase
		end
	end
endmodule