data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:52: syntax error, unexpected \'@\'\n     repeat(5)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:54: syntax error, unexpected \'@\'\n     repeat(1)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:57: syntax error, unexpected \'@\'\n  repeat(8060)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:59: syntax error, unexpected \'@\'\n     repeat(1)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:62: syntax error, unexpected \'@\'\n  repeat(100)@(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/41989639/american_put_cyclone/src/compute_vex_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module compute_vex_tb;


	reg clk;
	reg nrst;
	reg start;
	reg [63:0] plus;
	reg [63:0] minus;
	reg [63:0] K_over_S;
	

	wire [63:0] v_ex;
	wire [12:0] wraddr;
	wire wren;
	

	compute_vex uut (
		.clk(clk),
		.nrst(nrst),
		.start(start),
		.log_lambda_up(plus),
		.log_lambda_down(minus),
		.K_over_S(K_over_S),
		.v_ex(v_ex),
		.wraddr(wraddr),
		.wren(wren)
	);
	
	initial begin

		clk    = 0;
		nrst   = 0;
		start  = 0;
		K_over_S <= 64'h4000000000000000;

        plus     <= 64'h3f50624dd2f1a9fc;
	    minus    <= 64'h3f1a36e2eb1c432d;
	    	

		#100;
		nrst <= 1'b1;
		

	    repeat(5)@(posedge clk);
		start <= 1'b1;
	    repeat(1)@(posedge clk);
		start <= 1'b0;
	    
		repeat(8060)@(posedge clk);
		start <= 1'b1;
	    repeat(1)@(posedge clk);
		start <= 1'b0;
	    
		repeat(100)@(posedge clk);
		
        $stop;
	end
	

	initial begin
	#20
	forever clk = #20 ~clk; 		
	end

      
endmodule
module compute_vex_tb;



	reg clk;
	reg nrst;
	reg start;
	reg [63:0] plus;
	reg [63:0] minus;
	reg [63:0] K_over_S;
	

	wire [63:0] v_ex;
	wire [12:0] wraddr;
	wire wren;
	

	compute_vex uut (
		.clk(clk),
		.nrst(nrst),
		.start(start),
		.log_lambda_up(plus),
		.log_lambda_down(minus),
		.K_over_S(K_over_S),
		.v_ex(v_ex),
		.wraddr(wraddr),
		.wren(wren)
	);
	
	initial begin

		clk    = 0;
		nrst   = 0;
		start  = 0;
		K_over_S <= 64'h4000000000000000;

        plus     <= 64'h3f50624dd2f1a9fc;
	    minus    <= 64'h3f1a36e2eb1c432d;
	    	

		#100;
		nrst <= 1'b1;
		

	    repeat(5)@(posedge clk);
		start <= 1'b1;
	    repeat(1)@(posedge clk);
		start <= 1'b0;
	    
		repeat(8060)@(posedge clk);
		start <= 1'b1;
	    repeat(1)@(posedge clk);
		start <= 1'b0;
	    
		repeat(100)@(posedge clk);
		
        $stop;
	end
	

	initial begin
	#20
	forever clk = #20 ~clk; 		
	end

      
endmodule