data/full_repos/permissive/523038000/lab7/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/523038000/lab7/alu_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/523038000/lab7/alu_tb.v:37: Cannot find file containing module: \'alu\'\n alu uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab7,data/full_repos/permissive/523038000/alu\n             data/full_repos/permissive/523038000/lab7,data/full_repos/permissive/523038000/alu.v\n             data/full_repos/permissive/523038000/lab7,data/full_repos/permissive/523038000/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb;


	reg [3:0] ctl;
	reg [31:0] a;
	reg [31:0] b;


	wire [31:0] out;
	wire zero;


	alu uut (
		.ctl(ctl), 
		.a(a), 
		.b(b), 
		.out(out), 
		.zero(zero)
	);

	initial begin

		ctl = 0;
		a = 0;
		b = 0;


		#100;
        



	end
      
endmodule
module alu_tb;



	reg [3:0] ctl;
	reg [31:0] a;
	reg [31:0] b;


	wire [31:0] out;
	wire zero;


	alu uut (
		.ctl(ctl), 
		.a(a), 
		.b(b), 
		.out(out), 
		.zero(zero)
	);

	initial begin

		ctl = 0;
		a = 0;
		b = 0;


		#100;
        



	end
      
endmodule