data/full_repos/permissive/441359809/src/yosys/backends/simplec/test00_uut.v
data/verilator_xmls/b7b6ca9c-4710-4090-895c-7527aecfe29b.xml
module unit_x(input [31:0] a, b, c, output [31:0] x);
  assign x = (a & b) | c;
endmodule
module unit_x(input [31:0] a, b, c, output [31:0] x);

  assign x = (a & b) | c;
endmodule