data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:16: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:19: Unsupported: Ignoring delay on this delayed statement.\n #(sim_time-1) Reset = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:31: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:34: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench5.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/EmbededSystem/ARM_CU_ALU_TestBench5.v:35: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench5);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench5;

parameter sim_time = 2000*2;

reg Reset , Clk , MEMSTORE,MEMLOAD;
wire [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE,MFC;
wire [7:0] MEMADD;


memory mem( MEMDAT, MFC,  MFA, READ_WRITE,  MEMADD,  WORD_BYTE, Reset);


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;
	#1 Reset = 0;
	#(sim_time-1) Reset = 1;
join

always@(*) begin
	$display("MEMADD = %d", MEMADD);
	MEMSTORE=!READ_WRITE;
	MEMLOAD=READ_WRITE;
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench5.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench5);


end

endmodule
module ARM_CU_ALU_TestBench5;


parameter sim_time = 2000*2;

reg Reset , Clk , MEMSTORE,MEMLOAD;
wire [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE,MFC;
wire [7:0] MEMADD;


memory mem( MEMDAT, MFC,  MFA, READ_WRITE,  MEMADD,  WORD_BYTE, Reset);


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;
	#1 Reset = 0;
	#(sim_time-1) Reset = 1;
join

always@(*) begin
	$display("MEMADD = %d", MEMADD);
	MEMSTORE=!READ_WRITE;
	MEMLOAD=READ_WRITE;
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench5.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench5);


end

endmodule