data/full_repos/permissive/449370139/verilog_code/devider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/devider.v:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance divider\n    integer first=1\'b0;\n                  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/devider.v:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance divider\n     count=1\'b0;\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module divider(I_CLK,rst,O_CLK);
    input I_CLK;
    input rst;
    output reg O_CLK;
    integer count;
    integer first=1'b0;
parameter NUM_DIV=20;

initial
begin
   if(first==0)
     begin
     O_CLK=1'b0;
     first=first+1;
     count=1'b0;
     end
end

always @ (posedge I_CLK)
begin
    count=count+1;
    if(rst)
        begin
        O_CLK=1'b0;
        count=0;
        end
    else if(count==NUM_DIV/2)
        begin
        O_CLK=~O_CLK;
        count=0;
        end
    else
        O_CLK=O_CLK;
end
endmodule
module divider(I_CLK,rst,O_CLK);

    input I_CLK;
    input rst;
    output reg O_CLK;
    integer count;
    integer first=1'b0;
parameter NUM_DIV=20;

initial
begin
   if(first==0)
     begin
     O_CLK=1'b0;
     first=first+1;
     count=1'b0;
     end
end

always @ (posedge I_CLK)
begin
    count=count+1;
    if(rst)
        begin
        O_CLK=1'b0;
        count=0;
        end
    else if(count==NUM_DIV/2)
        begin
        O_CLK=~O_CLK;
        count=0;
        end
    else
        O_CLK=O_CLK;
end
endmodule