data/full_repos/permissive/52703097/full_adder.test.v
1: b'%Error: data/full_repos/permissive/52703097/full_adder.test.v:1: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/full_adder.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/full_adder.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/full_adder.v.sv\n             full_adder.v\n             full_adder.v.v\n             full_adder.v.sv\n             obj_dir/full_adder.v\n             obj_dir/full_adder.v.v\n             obj_dir/full_adder.v.sv\n%Error: data/full_repos/permissive/52703097/full_adder.test.v:30: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/52703097/full_adder.test.v:31: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/full_adder.test.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #10 {a,b,cin} = i;  \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52703097/full_adder.test.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module test;


    reg a;
    reg b;
    reg cin;


    wire result;
    wire cout;

    integer i;


    full_adder uut(
        .i_a(a),
        .i_b(b),
        .i_cin(cin),
        .o_result(result),
        .o_cout(cout)
    );

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        a = 0;
        b = 0;
        cin = 0;
    end

    always @ (a, b, cin)
    begin
        for (i = 0; i < `TESTS; i = i+1)
            #10 {a,b,cin} = i;

        #10 $finish;
    end
endmodule
module test;



    reg a;
    reg b;
    reg cin;


    wire result;
    wire cout;

    integer i;


    full_adder uut(
        .i_a(a),
        .i_b(b),
        .i_cin(cin),
        .o_result(result),
        .o_cout(cout)
    );

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        a = 0;
        b = 0;
        cin = 0;
    end

    always @ (a, b, cin)
    begin
        for (i = 0; i < `TESTS; i = i+1)
            #10 {a,b,cin} = i;

        #10 $finish;
    end
endmodule