data/full_repos/permissive/470158975/rtl/rx_udp_ip.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:290: Signal definition not found, creating implicitly: \'ip_crc_valid\'\n                                                                           : ... Suggested alternative: \'ph_crc_valid\'\n            if (ip_crc_valid) begin \n                ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:209: Operator COND expects 2 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance rx_udp_ip\n   assign udp_payload_tkeep[7:6] = carry_last ? 1\'b0 : rx_tkeep[1:0];   \n                                              ^\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:225: Cannot find file containing module: \'axis_pipeline_register\'\n   axis_pipeline_register #(\n   ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470158975/rtl,data/full_repos/permissive/470158975/axis_pipeline_register\n             data/full_repos/permissive/470158975/rtl,data/full_repos/permissive/470158975/axis_pipeline_register.v\n             data/full_repos/permissive/470158975/rtl,data/full_repos/permissive/470158975/axis_pipeline_register.sv\n             axis_pipeline_register\n             axis_pipeline_register.v\n             axis_pipeline_register.sv\n             obj_dir/axis_pipeline_register\n             obj_dir/axis_pipeline_register.v\n             obj_dir/axis_pipeline_register.sv\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:302: Cannot find file containing module: \'ip_header_checksum\'\n   ip_header_checksum ip_header_checksum(\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:337: Cannot find file containing module: \'payload_crc_acc\'\n   payload_crc_acc payload_crc_acc(\n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:417: Cannot find file containing module: \'payload_crc_acc\'\n   payload_crc_acc ph_crc_acc(\n   ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:435: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                        : ... In instance rx_udp_ip\n   assign udp_crc_result = ~(udp_crc_result_tmp[15:0] + udp_crc_result_tmp[16]);\n                                                      ^\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:528: Cannot find file containing module: \'fwft_fifo\'\n   fwft_fifo #(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:541: Cannot find file containing module: \'fwft_fifo\'\n   fwft_fifo #(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/470158975/rtl/rx_udp_ip.v:556: Cannot find file containing module: \'axis_fifo\'\n   axis_fifo #(\n   ^~~~~~~~~\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module rx_udp_ip (

   input wire clk,
   input wire reset,

   input wire [47:0]  CFG_MAC,
   input wire [31:0]  CFG_IP,


   input wire [63:0]  rx_tdata,            
   input wire [7:0]   rx_tkeep,
   input wire         rx_tvalid,
   input wire         rx_tuser,
   input wire         rx_tlast,


   output wire [63:0]   tx_tdata,
   output wire [7:0]    tx_tkeep,
   output wire          tx_tvalid,
   output wire          tx_tlast,
   input wire           tx_tready,

   output wire [47:0]   src_mac,
   output wire [31:0]   src_ip,
   output wire [15:0]   src_udp,
   output wire [15:0]   dst_udp

);


/
      .s_axis_tdata(udp_payload_tdata),
      .s_axis_tkeep(udp_payload_tkeep),
      .s_axis_tvalid(udp_payload_tvalid),
      .s_axis_tready(),
      .s_axis_tlast(udp_payload_tlast),
      .s_axis_tuser(udp_payload_tuser),


      .m_axis_tdata(payload_tdata),
      .m_axis_tkeep(payload_tkeep),
      .m_axis_tvalid(payload_tvalid),
      .m_axis_tready(1'b1),
      .m_axis_tlast(payload_tlast),
      .m_axis_tuser(payload_tuser)
   );


   /
      .m_axis_tdata(tx_tdata),
      .m_axis_tkeep(tx_tkeep),
      .m_axis_tvalid(tx_tvalid),
      .m_axis_tready(tx_tready),
      .m_axis_tlast(tx_tlast),
      .m_axis_tid(),
      .m_axis_tdest(),
      .m_axis_tuser(),

      .status_overflow(),
      .status_bad_frame(),
      .status_good_frame()
   ); 

endmodule
module rx_udp_ip (

   input wire clk,
   input wire reset,

   input wire [47:0]  CFG_MAC,
   input wire [31:0]  CFG_IP,


   input wire [63:0]  rx_tdata,            
   input wire [7:0]   rx_tkeep,
   input wire         rx_tvalid,
   input wire         rx_tuser,
   input wire         rx_tlast,


   output wire [63:0]   tx_tdata,
   output wire [7:0]    tx_tkeep,
   output wire          tx_tvalid,
   output wire          tx_tlast,
   input wire           tx_tready,

   output wire [47:0]   src_mac,
   output wire [31:0]   src_ip,
   output wire [15:0]   src_udp,
   output wire [15:0]   dst_udp

);



/
      .s_axis_tdata(udp_payload_tdata),
      .s_axis_tkeep(udp_payload_tkeep),
      .s_axis_tvalid(udp_payload_tvalid),
      .s_axis_tready(),
      .s_axis_tlast(udp_payload_tlast),
      .s_axis_tuser(udp_payload_tuser),


      .m_axis_tdata(payload_tdata),
      .m_axis_tkeep(payload_tkeep),
      .m_axis_tvalid(payload_tvalid),
      .m_axis_tready(1'b1),
      .m_axis_tlast(payload_tlast),
      .m_axis_tuser(payload_tuser)
   );


   /
      .m_axis_tdata(tx_tdata),
      .m_axis_tkeep(tx_tkeep),
      .m_axis_tvalid(tx_tvalid),
      .m_axis_tready(tx_tready),
      .m_axis_tlast(tx_tlast),
      .m_axis_tid(),
      .m_axis_tdest(),
      .m_axis_tuser(),

      .status_overflow(),
      .status_bad_frame(),
      .status_good_frame()
   ); 

endmodule