data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v
1: b'%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:61: Unsupported: Static in this context\nstatic integer FILE;\n^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #(10/2) clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #(33/2) jclk = ~jclk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n#700000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:258: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:259: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb.x_soc);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:391: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:392: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:393: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:394: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:395: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:397: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:398: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:399: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:400: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:401: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:403: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:404: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:405: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:406: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:407: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:409: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:410: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:411: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:412: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:414: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:415: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:416: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:417: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:418: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:421: Unsupported: wait statements\n  wait (tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt==1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:422: Unsupported: Verilog 1995 force\n  force tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0] = virtual_counter[31:0];\n  ^~~~~\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:423: syntax error, unexpected \'@\'\n  @(posedge tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.pll_core_cpuclk);\n  ^\n%Error: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:424: Unsupported: Verilog 1995 release\n  release tb.x_soc.x_cpu_sub_system_ahb.x_e906_top.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0];\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/426286934/smart_run/logical/tb/tb.v:425: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 27 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function supply_off;

  input [8*`MAX_ARCH_STRLEN : 1] pad_name;
begin
  supply_off = $mvsim_supply_off(pad_name);
end
endfunction
function supply_off;


  input [8*`MAX_ARCH_STRLEN : 1] pad_name;
begin
  supply_off = $mvsim_supply_off(pad_name);
end
endfunction