data/full_repos/permissive/526285135/src/fpga/apf/common.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/526285135/src/fpga/apf/common.v:58: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'synch_2\'\nmodule synch_2 #(parameter WIDTH = 1) (\n       ^~~~~~~\n                                                                                : ... Top module \'synch_3\'\nmodule synch_3 #(parameter WIDTH = 1) (\n       ^~~~~~~\n                                                                                : ... Top module \'bram_block_dp\'\nmodule bram_block_dp #(\n       ^~~~~~~~~~~~~\n                                                                                : ... Top module \'bram_block_dp_nonstd\'\nmodule bram_block_dp_nonstd #(\n       ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module synch_3 #(parameter WIDTH = 1) (
   input  wire [WIDTH-1:0] i,
   output reg  [WIDTH-1:0] o,
   input  wire             clk,
   output wire             rise,
   output wire             fall
);

reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;

assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0;
assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0;
always @(posedge clk) 
   {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i};
   
endmodule
module synch_3 #(parameter WIDTH = 1) (
   input  wire [WIDTH-1:0] i,
   output reg  [WIDTH-1:0] o,
   input  wire             clk,
   output wire             rise,
   output wire             fall
);


reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;

assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0;
assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0;
always @(posedge clk) 
   {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i};
   
endmodule