data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential Logic/More Circuits/rule90.v
1: b'%Error: Cannot find file containing module: Logic/More\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/More\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/More.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/More.sv\n             Logic/More\n             Logic/More.v\n             Logic/More.sv\n             obj_dir/Logic/More\n             obj_dir/Logic/More.v\n             obj_dir/Logic/More.sv\n%Error: Cannot find file containing module: Circuits,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Circuits/rule90.v\n%Error: Exiting due to 4 error(s)\n'
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    reg [511:0] sreg;
    assign q = sreg;

    always @(posedge clk) begin
        if (load)
            sreg <= data;
        else begin



            sreg <= {sreg[510], sreg[511:2] ^ sreg[509:0], sreg[1]};
        end
    end

endmodule
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q );
 
    
    reg [511:0] sreg;
    assign q = sreg;

    always @(posedge clk) begin
        if (load)
            sreg <= data;
        else begin



            sreg <= {sreg[510], sreg[511:2] ^ sreg[509:0], sreg[1]};
        end
    end

endmodule