data/full_repos/permissive/452215364/rtl/opl2/operator/edge_detector.v
data/verilator_xmls/468a928f-654d-47f5-9ae7-f855c57ef04c.xml
module edge_detector #(
    parameter EDGE_LEVEL = 1,
    parameter CLK_DLY = 0,
    parameter INITIAL_INPUT_LEVEL = 0
) (
    input wire clk,
    input wire clk_en,
    input wire in, 
    output reg edge_detected
);
    reg in_r0 = INITIAL_INPUT_LEVEL;
    reg in_r1 = INITIAL_INPUT_LEVEL;
    
    always @(posedge clk)
    	if (!CLK_DLY)
            in_r0 <= in;
        else if (clk_en) begin
            in_r0 <= in;
            in_r1 <= in_r0;
        end
    
    always @ *
        if (EDGE_LEVEL)
            if (!CLK_DLY)
                edge_detected = in && !in_r0;
            else
                edge_detected = in_r0 && !in_r1;
        else
            if (!CLK_DLY)
                edge_detected = !in && in_r0;
            else 
                edge_detected = !in_r0 && in_r1;        
endmodule
module edge_detector #(
    parameter EDGE_LEVEL = 1,
    parameter CLK_DLY = 0,
    parameter INITIAL_INPUT_LEVEL = 0
) (
    input wire clk,
    input wire clk_en,
    input wire in, 
    output reg edge_detected
);

    reg in_r0 = INITIAL_INPUT_LEVEL;
    reg in_r1 = INITIAL_INPUT_LEVEL;
    
    always @(posedge clk)
    	if (!CLK_DLY)
            in_r0 <= in;
        else if (clk_en) begin
            in_r0 <= in;
            in_r1 <= in_r0;
        end
    
    always @ *
        if (EDGE_LEVEL)
            if (!CLK_DLY)
                edge_detected = in && !in_r0;
            else
                edge_detected = in_r0 && !in_r1;
        else
            if (!CLK_DLY)
                edge_detected = !in && in_r0;
            else 
                edge_detected = !in_r0 && in_r1;        
endmodule