data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/counter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #(PERIOD/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/counter_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD st = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/counter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #(20*PERIOD) st = 1;\n    ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/counter_tb.v:22: Cannot find file containing module: \'counter\'\ncounter  u_counter (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/counter\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/counter.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_counter;     


parameter PERIOD  = 10;



reg   clk                                  = 0 ;
reg   start                                = 0 ;
reg st = 0;
reg   [7:0]  m_time                        = 8'd10 ;
reg [7:0] fuck = 0;


wire  done                                 ;


always #(PERIOD/2) clk = ~clk;

counter  u_counter (
    .clk                     ( clk           ),
    .start                   ( start         ),
    .m_time                  ( m_time  [7:0] ),

    .done                    ( done          )
);

initial
begin
    #PERIOD st = 1;
    #(20*PERIOD) st = 1;
end

always @(posedge clk) begin
    if(st == 1) start = 1;
    else begin
        start = 0;
        st = 0;
    end
end

always @(*) begin
    if(done == 1) begin
        fuck = fuck + 1;
        start = 0;
    end
    else begin
        start = 1;
    end
end

endmodule
module tb_counter;
     


parameter PERIOD  = 10;



reg   clk                                  = 0 ;
reg   start                                = 0 ;
reg st = 0;
reg   [7:0]  m_time                        = 8'd10 ;
reg [7:0] fuck = 0;


wire  done                                 ;


always #(PERIOD/2) clk = ~clk;

counter  u_counter (
    .clk                     ( clk           ),
    .start                   ( start         ),
    .m_time                  ( m_time  [7:0] ),

    .done                    ( done          )
);

initial
begin
    #PERIOD st = 1;
    #(20*PERIOD) st = 1;
end

always @(posedge clk) begin
    if(st == 1) start = 1;
    else begin
        start = 0;
        st = 0;
    end
end

always @(*) begin
    if(done == 1) begin
        fuck = fuck + 1;
        start = 0;
    end
    else begin
        start = 1;
    end
end

endmodule