data/full_repos/permissive/503772164/top.v
1: b'%Error: data/full_repos/permissive/503772164/top.v:40: Cannot find file containing module: \'SB_PLL40_CORE\'\nSB_PLL40_CORE#(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503772164,data/full_repos/permissive/503772164/SB_PLL40_CORE\n             data/full_repos/permissive/503772164,data/full_repos/permissive/503772164/SB_PLL40_CORE.v\n             data/full_repos/permissive/503772164,data/full_repos/permissive/503772164/SB_PLL40_CORE.sv\n             SB_PLL40_CORE\n             SB_PLL40_CORE.v\n             SB_PLL40_CORE.sv\n             obj_dir/SB_PLL40_CORE\n             obj_dir/SB_PLL40_CORE.v\n             obj_dir/SB_PLL40_CORE.sv\n%Warning-WIDTH: data/full_repos/permissive/503772164/top.v:89: Operator SHIFTR expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'vcount\' generates 9 bits.\n                                                             : ... In instance top\n  pixel <= vbuf[ (hcount >> 3) + (vcount >> 3) * 80];\n                                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top(CLK,PIN_1,PIN_2,PIN_3,PIN_4,PIN_5,PIN_6,PIN_7,PIN_8,PIN_9,PIN_10,USBPU);

input CLK;

output PIN_1;
output PIN_2;

output PIN_3;
output PIN_4;
output PIN_5;
output PIN_6;
output PIN_7;
output PIN_8;
output PIN_9;
output PIN_10;

output USBPU;
assign USBPU = 0;

wire pclk;

reg [9:0] hcount;
reg [8:0] vcount;

reg hblank;
reg vblank;

reg hsync;
reg vsync;

reg [7:0] vbuf [4799:0];
reg [7:0] pixel;


initial begin
	$readmemh("pic.txt",vbuf);
end


SB_PLL40_CORE#(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),
		.DIVF(7'b0001000),
		.DIVQ(3'b010),
		.FILTER_RANGE(3'b001)
	)uut(
		.BYPASS(1'b0),
		.REFERENCECLK(CLK),
		.PLLOUTCORE(pclk),
		.RESETB(1'b1)
		);

always @(posedge pclk)begin
	

	hcount <= hcount + 1;
	if(hcount==10'd832)begin
		hcount <= 0;
		vcount <= vcount + 1;
		hblank <= 1'b1;
	end
	if(vcount==9'd509)begin
		vcount <= 0;
		vblank <= 1'b1;
	end
	if(hcount==10'd640)begin
		hblank <= 1'b0;
	end
	if(vcount==9'd480)begin
		vblank <= 1'b0;
	end
	

	if(hcount==10'd696)begin
		hsync <= 1'b0;
	end
	if(hcount==10'd752)begin
		hsync <= 1'b1;
	end
	if(vcount==9'd481)begin
		vsync <= 1'b0;
	end
	if(vcount==9'd484)begin
		vsync <= 1'b1;
	end
	

	if (hblank && vblank)begin
		pixel <= vbuf[ (hcount >> 3) + (vcount >> 3) * 80];
	end else begin
		pixel <= 8'b0;
	end
	
end

assign PIN_1 = hsync;
assign PIN_2 = vsync;

assign PIN_3  = pixel[0];
assign PIN_4  = pixel[1];
assign PIN_5  = pixel[2];
assign PIN_6  = pixel[3];
assign PIN_7  = pixel[4];
assign PIN_8  = pixel[5];
assign PIN_9  = pixel[6];
assign PIN_10 = pixel[7];

endmodule
module top(CLK,PIN_1,PIN_2,PIN_3,PIN_4,PIN_5,PIN_6,PIN_7,PIN_8,PIN_9,PIN_10,USBPU);


input CLK;

output PIN_1;
output PIN_2;

output PIN_3;
output PIN_4;
output PIN_5;
output PIN_6;
output PIN_7;
output PIN_8;
output PIN_9;
output PIN_10;

output USBPU;
assign USBPU = 0;

wire pclk;

reg [9:0] hcount;
reg [8:0] vcount;

reg hblank;
reg vblank;

reg hsync;
reg vsync;

reg [7:0] vbuf [4799:0];
reg [7:0] pixel;


initial begin
	$readmemh("pic.txt",vbuf);
end


SB_PLL40_CORE#(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),
		.DIVF(7'b0001000),
		.DIVQ(3'b010),
		.FILTER_RANGE(3'b001)
	)uut(
		.BYPASS(1'b0),
		.REFERENCECLK(CLK),
		.PLLOUTCORE(pclk),
		.RESETB(1'b1)
		);

always @(posedge pclk)begin
	

	hcount <= hcount + 1;
	if(hcount==10'd832)begin
		hcount <= 0;
		vcount <= vcount + 1;
		hblank <= 1'b1;
	end
	if(vcount==9'd509)begin
		vcount <= 0;
		vblank <= 1'b1;
	end
	if(hcount==10'd640)begin
		hblank <= 1'b0;
	end
	if(vcount==9'd480)begin
		vblank <= 1'b0;
	end
	

	if(hcount==10'd696)begin
		hsync <= 1'b0;
	end
	if(hcount==10'd752)begin
		hsync <= 1'b1;
	end
	if(vcount==9'd481)begin
		vsync <= 1'b0;
	end
	if(vcount==9'd484)begin
		vsync <= 1'b1;
	end
	

	if (hblank && vblank)begin
		pixel <= vbuf[ (hcount >> 3) + (vcount >> 3) * 80];
	end else begin
		pixel <= 8'b0;
	end
	
end

assign PIN_1 = hsync;
assign PIN_2 = vsync;

assign PIN_3  = pixel[0];
assign PIN_4  = pixel[1];
assign PIN_5  = pixel[2];
assign PIN_6  = pixel[3];
assign PIN_7  = pixel[4];
assign PIN_8  = pixel[5];
assign PIN_9  = pixel[6];
assign PIN_10 = pixel[7];

endmodule