data/full_repos/permissive/461569093/Mini ALU/bit8.v
1: b'%Error: Cannot find file containing module: ALU,data/full_repos/permissive/461569093\n        ... Looked in:\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.v\n             data/full_repos/permissive/461569093/Mini/ALU,data/full_repos/permissive/461569093.sv\n             ALU,data/full_repos/permissive/461569093\n             ALU,data/full_repos/permissive/461569093.v\n             ALU,data/full_repos/permissive/461569093.sv\n             obj_dir/ALU,data/full_repos/permissive/461569093\n             obj_dir/ALU,data/full_repos/permissive/461569093.v\n             obj_dir/ALU,data/full_repos/permissive/461569093.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461569093/Mini\n%Error: Cannot find file containing module: ALU/bit8.v\n%Error: Exiting due to 3 error(s)\n'
module bit8(
        input wire [5:0] x3, y3,
        output wire  c3
    );

    wire q, w, e, r;
    greater g1 (.p(x3[1:0]), .q(y3[1:0]), .r(q));
    greater g2 (.p(x3[3:2]), .q(y3[3:2]), .r(w));
    greater g3 (.p(x3[5:4]), .q(y3[5:4]), .r(e));

   
    wire s, d, f, g;
    equal e1 (.a(x3[1:0]), .b(y3[1:0]), .aeqb(s));
    equal e2 (.a(x3[3:2]), .b(y3[3:2]), .aeqb(d));
    equal e3 (.a(x3[5:4]), .b(y3[5:4]), .aeqb(f));

   
   assign r = 1'b0;
   assign g = 1'b1;
   
    assign c3 = (r|g&(e|f&(w|d&(q|s))));
    
    
   
   
endmodule
module bit8(
        input wire [5:0] x3, y3,
        output wire  c3
    );


    wire q, w, e, r;
    greater g1 (.p(x3[1:0]), .q(y3[1:0]), .r(q));
    greater g2 (.p(x3[3:2]), .q(y3[3:2]), .r(w));
    greater g3 (.p(x3[5:4]), .q(y3[5:4]), .r(e));

   
    wire s, d, f, g;
    equal e1 (.a(x3[1:0]), .b(y3[1:0]), .aeqb(s));
    equal e2 (.a(x3[3:2]), .b(y3[3:2]), .aeqb(d));
    equal e3 (.a(x3[5:4]), .b(y3[5:4]), .aeqb(f));

   
   assign r = 1'b0;
   assign g = 1'b1;
   
    assign c3 = (r|g&(e|f&(w|d&(q|s))));
    
    
   
   
endmodule