data/full_repos/permissive/420819839/Vectors/Vector4.v
data/verilator_xmls/3a2e7824-c393-4a98-97f5-170dc01f8b6e.xml
module top_module (
    input [7:0] in,
    output [31:0] out );


    assign out = {{24{in[7]}},in};
endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );



    assign out = {{24{in[7]}},in};
endmodule