data/full_repos/permissive/469775158/verilog/rtl/my_alu_xor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469775158/verilog/rtl/my_alu_xor.v:64: Operator AND expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                                : ... In instance my_alu_xor.alu_2\nALU_Result = A & B;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469775158/verilog/rtl/my_alu_xor.v:64: Operator AND expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                                : ... In instance my_alu_xor.alu_2\nALU_Result = A & B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/469775158/verilog/rtl/my_alu_xor.v:66: Operator OR expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                                : ... In instance my_alu_xor.alu_2\nALU_Result = A | B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/469775158/verilog/rtl/my_alu_xor.v:66: Operator OR expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                                : ... In instance my_alu_xor.alu_2\nALU_Result = A | B;\n               ^\n%Error: Exiting due to 4 warning(s)\n'
module my_alu_xor(
input clk,
input [7:0] A0,B0,A1,B1,
input [1:0] ALU_Sel1,ALU_Sel2,
output [7:0] ALU_Out1,ALU_Out2,
output CarryOut1,CarryOut2,
output [7:0] x,
output y
);

my_alu alu_1(
.A (A0),
.B (B0),
.ALU_Sel (ALU_Sel1),
.ALU_Out (ALU_Out1),
.CarryOut (CarryOut1)
);

my_alu alu_2(
.A (A1),
.B (B1),
.ALU_Sel (ALU_Sel2),
.ALU_Out (ALU_Out2),
.CarryOut (CarryOut2)
);


assign x[7:0] = ALU_Out1[7:0] ^ ALU_Out2[7:0];
assign y = CarryOut1 ^ CarryOut2;
always @(*)
begin
if (x!=0)
$display ("Faulty ALU");
else
$display ("ALU is right");
if (y!=0)
$display ("Faulty Carry");
else
$display ("Carry is right");
end


endmodule
module my_alu_xor(
input clk,
input [7:0] A0,B0,A1,B1,
input [1:0] ALU_Sel1,ALU_Sel2,
output [7:0] ALU_Out1,ALU_Out2,
output CarryOut1,CarryOut2,
output [7:0] x,
output y
);


my_alu alu_1(
.A (A0),
.B (B0),
.ALU_Sel (ALU_Sel1),
.ALU_Out (ALU_Out1),
.CarryOut (CarryOut1)
);

my_alu alu_2(
.A (A1),
.B (B1),
.ALU_Sel (ALU_Sel2),
.ALU_Out (ALU_Out2),
.CarryOut (CarryOut2)
);


assign x[7:0] = ALU_Out1[7:0] ^ ALU_Out2[7:0];
assign y = CarryOut1 ^ CarryOut2;
always @(*)
begin
if (x!=0)
$display ("Faulty ALU");
else
$display ("ALU is right");
if (y!=0)
$display ("Faulty Carry");
else
$display ("Carry is right");
end


endmodule