data/full_repos/permissive/52666593/vga/h_syncer.v
data/verilator_xmls/9dfda15e-78c2-4b57-b928-0cdc75bcad9e.xml
module h_syncer(clk,reset,h_sync,line_complete);
input clk,reset;
output wire h_sync;
output reg line_complete;

reg [9:0]h_sync_count;

always@(posedge clk,reset)
begin
	if(reset)
		h_sync_count <= 10'd0;
	else
	begin
		if(h_sync_count == 10'd800)
		begin
			h_sync_count <= 10'd0;
			line_complete <= 1'b1;
		end
		else
		begin
			h_sync_count <= h_sync_count + 1;
			line_complete <= 1'b0;
		end
	end

end


assign h_sync = (h_sync_count < 10'd97)? 1'b0:1'b1;

endmodule
module h_syncer(clk,reset,h_sync,line_complete);

input clk,reset;
output wire h_sync;
output reg line_complete;

reg [9:0]h_sync_count;

always@(posedge clk,reset)
begin
	if(reset)
		h_sync_count <= 10'd0;
	else
	begin
		if(h_sync_count == 10'd800)
		begin
			h_sync_count <= 10'd0;
			line_complete <= 1'b1;
		end
		else
		begin
			h_sync_count <= h_sync_count + 1;
			line_complete <= 1'b0;
		end
	end

end


assign h_sync = (h_sync_count < 10'd97)? 1'b0:1'b1;

endmodule