data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:744: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'Km\' generates 32 or 4 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n        matchListMatrix[k] <= Km;\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:748: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wdata\' generates 4 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n      matchListMatrix[addr] <= wdata;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:752: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                                                 : ... In instance stable_match.MatchListMatrix_\n  assign rdata = matchListMatrix[addr];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:345: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'matchListMatrix_rdata\' generates 4 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign m_assigned = matchListMatrix_rdata;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:348: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign mPrefMatrix_raddr = Km-pc_mIndex;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stable_match/stable_match.v:370: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'m\' generates 3 bits.\n                                                                                                                 : ... In instance stable_match.stable_match_core_\n  assign matchListMatrix_wdata = m;\n                               ^\n%Error: Exiting due to 6 warning(s)\n'
module MIsMatch
#(
  parameter Kw =8,
  parameter Km =8,
  parameter M  =8,
  parameter W  =8
)
(
  clk,
  rst,
  waddr1,
  wdata1,
  wen1,
  waddr2,
  wdata2,
  wen2,
  raddr,
  rdata
);

  function integer log2;
    input [31:0] value;
    reg [31:0] temp;
  begin
    temp = value - 1;
    for (log2=0; temp>0; log2=log2+1)
      temp = temp>>1;
  end
  endfunction

  localparam logM = log2(M);
  localparam logW = log2(W);
  localparam logKm = log2(Km);
  localparam logKw = log2(Kw);

  input clk,rst;

  input [logM-1:0] waddr1;
  input wdata1;
  input wen1;
  input [logM-1:0] waddr2;
  input wdata2;
  input wen2;
  input [logM-1:0] raddr;
  output rdata;


  reg [M-1:0] mIsMatch;

  integer k;
  always @(posedge clk or posedge rst) begin
    if (rst) begin
      for (k=0;k<M;k=k+1) begin :always_line
        mIsMatch[k] <= 1'b0;
      end
    end else if (wen1) begin
      mIsMatch[waddr1] <= wdata1;
    end else if (wen2) begin
      mIsMatch[waddr2] <= wdata2;
    end
  end

  assign rdata = mIsMatch[raddr];

endmodule
module MIsMatch
#(
  parameter Kw =8,
  parameter Km =8,
  parameter M  =8,
  parameter W  =8
)
(
  clk,
  rst,
  waddr1,
  wdata1,
  wen1,
  waddr2,
  wdata2,
  wen2,
  raddr,
  rdata
);


  function integer log2;
    input [31:0] value;
    reg [31:0] temp;
  begin
    temp = value - 1;
    for (log2=0; temp>0; log2=log2+1)
      temp = temp>>1;
  end
  endfunction

  localparam logM = log2(M);
  localparam logW = log2(W);
  localparam logKm = log2(Km);
  localparam logKw = log2(Kw);

  input clk,rst;

  input [logM-1:0] waddr1;
  input wdata1;
  input wen1;
  input [logM-1:0] waddr2;
  input wdata2;
  input wen2;
  input [logM-1:0] raddr;
  output rdata;


  reg [M-1:0] mIsMatch;

  integer k;
  always @(posedge clk or posedge rst) begin
    if (rst) begin
      for (k=0;k<M;k=k+1) begin :always_line
        mIsMatch[k] <= 1'b0;
      end
    end else if (wen1) begin
      mIsMatch[waddr1] <= wdata1;
    end else if (wen2) begin
      mIsMatch[waddr2] <= wdata2;
    end
  end

  assign rdata = mIsMatch[raddr];

endmodule