data/full_repos/permissive/51276512/mem.test.v
1: b'%Error: data/full_repos/permissive/51276512/mem.test.v:1: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51276512,data/full_repos/permissive/51276512/memory.v\n             data/full_repos/permissive/51276512,data/full_repos/permissive/51276512/memory.v.v\n             data/full_repos/permissive/51276512,data/full_repos/permissive/51276512/memory.v.sv\n             memory.v\n             memory.v.v\n             memory.v.sv\n             obj_dir/memory.v\n             obj_dir/memory.v.v\n             obj_dir/memory.v.sv\n%Error: data/full_repos/permissive/51276512/mem.test.v:2: Cannot find include file: sim.v\n`include "sim.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/51276512/mem.test.v:37: Define or directive not defined: \'`MEM_CMD_READ\'\n  .i_cmd(`MEM_CMD_READ),  \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module test();

wire reset;
wire clk;

reg [`ADDRESS_WIDTH-1:0] mem_address = 0;
wire [`DATA_WIDTH-1:0]   mem_data_out;

reg mem_valid;
wire mem_ready;
wire mem_res_valid;

always @(posedge clk) begin
  if (!reset && mem_ready) begin
    mem_valid <= 1;
  end

  if (!reset && mem_res_valid) begin
    mem_valid <= 0;
    mem_address += (`DATA_WIDTH / 8);
  end
end


memory #(`ADDRESS_WIDTH, `DATA_WIDTH) my_mem(
  .clk(clk),
  .reset(reset),

  .i_address(mem_address),
  .i_res_ready(1'b1),
  .i_cmd(`MEM_CMD_READ),
  .i_data(`DATA_WIDTH'bx),
  .i_valid(mem_valid),

  .o_data(mem_data_out),
  .o_res_valid(mem_res_valid),
  .o_ready(mem_ready)
);


sim my_sim(
  .clk(clk),
  .reset(reset)
);

endmodule
module test();


wire reset;
wire clk;

reg [`ADDRESS_WIDTH-1:0] mem_address = 0;
wire [`DATA_WIDTH-1:0]   mem_data_out;

reg mem_valid;
wire mem_ready;
wire mem_res_valid;

always @(posedge clk) begin
  if (!reset && mem_ready) begin
    mem_valid <= 1;
  end

  if (!reset && mem_res_valid) begin
    mem_valid <= 0;
    mem_address += (`DATA_WIDTH / 8);
  end
end


memory #(`ADDRESS_WIDTH, `DATA_WIDTH) my_mem(
  .clk(clk),
  .reset(reset),

  .i_address(mem_address),
  .i_res_ready(1'b1),
  .i_cmd(`MEM_CMD_READ),
  .i_data(`DATA_WIDTH'bx),
  .i_valid(mem_valid),

  .o_data(mem_data_out),
  .o_res_valid(mem_res_valid),
  .o_ready(mem_ready)
);


sim my_sim(
  .clk(clk),
  .reset(reset)
);

endmodule