data/full_repos/permissive/440170309/test_pmod/test_pmod_top.v
data/verilator_xmls/c040c5ab-f97b-42a2-bbde-d19f92fea4b6.xml
module test_pmod_top (

    input wire [15:0] switch,


    output wire [15:0] led,


    output wire [7:0] Ja,
    output wire [7:0] Jb,
    output wire [7:0] Jc,
    output wire [7:0] Jd
);

    assign led = switch;

    assign Ja = 8'h80;
    assign Jb = switch[15:8];
    assign Jc = 8'b0;
    assign Jd = switch[7 :0];
    
endmodule
module test_pmod_top (

    input wire [15:0] switch,


    output wire [15:0] led,


    output wire [7:0] Ja,
    output wire [7:0] Jb,
    output wire [7:0] Jc,
    output wire [7:0] Jd
);


    assign led = switch;

    assign Ja = 8'h80;
    assign Jb = switch[15:8];
    assign Jc = 8'b0;
    assign Jd = switch[7 :0];
    
endmodule