data/full_repos/permissive/510938582/rtl/top.v
1: b"%Error: data/full_repos/permissive/510938582/rtl/top.v:29: Cannot find file containing module: 'clk_div'\nclk_div quick(.clk(clk),.reset(rst),.symbol(32'd16384000),.div_clk(clk_quick));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/510938582/rtl,data/full_repos/permissive/510938582/clk_div\n             data/full_repos/permissive/510938582/rtl,data/full_repos/permissive/510938582/clk_div.v\n             data/full_repos/permissive/510938582/rtl,data/full_repos/permissive/510938582/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/510938582/rtl/top.v:30: Cannot find file containing module: 'clk_div'\nclk_div slow(.clk(clk),.reset(rst),.symbol(32'd49152000),.div_clk(clk_slow));\n^~~~~~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:31: Cannot find file containing module: 'clk_div'\nclk_div delay(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_delay));\n^~~~~~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:32: Cannot find file containing module: 'clk_div'\nclk_div mem(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_mem));\n^~~~~~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:33: Cannot find file containing module: 'clk_div'\nclk_div light(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_light));\n^~~~~~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:45: Cannot find file containing module: 'CPU_Controller'\nCPU_Controller controller(.SW1(SW1),.SW2(SW2),.CPU_state(cpustate));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:48: Cannot find file containing module: 'cpu'\ncpu mcpu(.data_in(rambus),.clk_quick(clk_quick),.clk_slow(clk_slow),.clk_delay(clk_delay),.zout(Z),\n^~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:57: Cannot find file containing module: 'ram'\nram mm(.clk(clk_mem),.data_in(data),.addr(addr),.A1(A1),.reset(rst),.read(read),.write(write),\n^~~\n%Error: data/full_repos/permissive/510938582/rtl/top.v:65: Cannot find file containing module: 'light_show'\nlight_show show(.light_clk(clk_light),.SW_choose(SW_choose),.check_in(check_out),.State(cpustate),.MAR(addr[7:0]),\n^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module top(clk,rst,A1,SW_choose,SW1,SW2,D,addr,rambus,data,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,acdbus,rdbus,cpustate_led,check_out,quick_low_led,read_led,write_led,arload_led,arinc_led,pcinc_led,pcload_led,drload_led,trload_led,irload_led,rload_led,acload_led,zload_led,pcbus_led,drhbus_led,drlbus_led,trbus_led,rbus_led,acbus_led,membus_led,busmem_led,clr_led);
input clk, rst;
input A1;
input SW_choose,SW1,SW2;
input [7:0] D;

output[15:0]addr;
output [7:0]rambus;
output [7:0] data;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
output [7:0] acdbus;
output [7:0] rdbus;
output [1:0] cpustate_led;
output [7:0] check_out;
output quick_low_led;
output read_led,write_led,arload_led,arinc_led,pcinc_led,pcload_led,drload_led,trload_led,irload_led,rload_led,acload_led,zload_led,pcbus_led,drhbus_led,drlbus_led,trbus_led,rbus_led,acbus_led,membus_led,busmem_led,clr_led;
wire Z;
wire read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem,clr;
wire clk_quick,clk_slow,clk_delay,clk_mem,clk_light;
wire [1:0] cpustate;



clk_div quick(.clk(clk),.reset(rst),.symbol(32'd16384000),.div_clk(clk_quick));
clk_div slow(.clk(clk),.reset(rst),.symbol(32'd49152000),.div_clk(clk_slow));
clk_div delay(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_delay));
clk_div mem(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_mem));
clk_div light(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_light));





CPU_Controller controller(.SW1(SW1),.SW2(SW2),.CPU_state(cpustate));


cpu mcpu(.data_in(rambus),.clk_quick(clk_quick),.clk_slow(clk_slow),.clk_delay(clk_delay),.zout(Z),
	.rst(rst),.SW_choose(SW_choose),.A1(A1),.cpustate(cpustate),.addr(addr),.data_out(data),.acdbus(acdbus),
	.rdbus(rdbus),.read(read),.write(write),.arload(arload),.arinc(arinc),.trload(trload),.trbus(trbus),
	.rload(rload),.rbus(rbus),.acbus(acbus), .pcload(pcload), .pcinc(pcinc),.pcbus(pcbus),.drdbus(drdbus),
	.membus(membus),.busmem(busmem), .drload(drload),.drlbus(drlbus),.drhbus(drhbus), .acload(acload),
	.bus(dbus),.irout(irout), .irload(irload),.zload(zload),.clr(clr));



ram mm(.clk(clk_mem),.data_in(data),.addr(addr),.A1(A1),.reset(rst),.read(read),.write(write),
		 .cpustate(cpustate),.D(D),.data_out(rambus),.check_out(check_out));






light_show show(.light_clk(clk_light),.SW_choose(SW_choose),.check_in(check_out),.State(cpustate),.MAR(addr[7:0]),
  .AC(acdbus),.R(rdbus),.Z(Z),.HEX0(HEX0),.HEX1(HEX1),.HEX2(HEX2),.HEX3(HEX3),.HEX4(HEX4),.HEX5(HEX5),.HEX6(HEX6),
  .HEX7(HEX7),.State_LED(cpustate_led),.quick_low_led(quick_low_led), .arload(arload), .arinc(arinc),
  .pcinc(pcinc),.pcload(pcload),.drload(drload),.trload(trload),.irload(irload),.rload(rload),.acload(acload),.zload(zload),.pcbus(pcbus),
  .drhbus(drhbus),.drlbus(drlbus),.trbus(trbus),.rbus(rbus),.acbus(acbus),.membus(membus),.busmem(busmen),.clr(clr),
  .read_led(read_led),.write_led(write_led),.arload_led(arload_led),.arinc_led(arinc_led),.pcinc_led(pcinc_led),.pcload_led(pcload_led), 
  .drload_led(drload_led),.trload_led(trload_led),.irload_led(irload_led),.rload_led(rload_led),.acload_led(acload_led),.zload_led(zload_led),
  .pcbus_led(pcbus_led),.drhbus_led(drhbus_led),.drlbus_led(drlbus_led),.trbus_led(trbus_led),.rbus_led(rbus_led),.acbus_led(acbus_led),
  .membus_led(membus_led),.busmem_led(busmem_led),.clr_led(clr_led),.read(read),.write(write));

endmodule
module top(clk,rst,A1,SW_choose,SW1,SW2,D,addr,rambus,data,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,acdbus,rdbus,cpustate_led,check_out,quick_low_led,read_led,write_led,arload_led,arinc_led,pcinc_led,pcload_led,drload_led,trload_led,irload_led,rload_led,acload_led,zload_led,pcbus_led,drhbus_led,drlbus_led,trbus_led,rbus_led,acbus_led,membus_led,busmem_led,clr_led);

input clk, rst;
input A1;
input SW_choose,SW1,SW2;
input [7:0] D;

output[15:0]addr;
output [7:0]rambus;
output [7:0] data;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
output [7:0] acdbus;
output [7:0] rdbus;
output [1:0] cpustate_led;
output [7:0] check_out;
output quick_low_led;
output read_led,write_led,arload_led,arinc_led,pcinc_led,pcload_led,drload_led,trload_led,irload_led,rload_led,acload_led,zload_led,pcbus_led,drhbus_led,drlbus_led,trbus_led,rbus_led,acbus_led,membus_led,busmem_led,clr_led;
wire Z;
wire read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem,clr;
wire clk_quick,clk_slow,clk_delay,clk_mem,clk_light;
wire [1:0] cpustate;



clk_div quick(.clk(clk),.reset(rst),.symbol(32'd16384000),.div_clk(clk_quick));
clk_div slow(.clk(clk),.reset(rst),.symbol(32'd49152000),.div_clk(clk_slow));
clk_div delay(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_delay));
clk_div mem(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_mem));
clk_div light(.clk(clk),.reset(rst),.symbol(32'd2048000),.div_clk(clk_light));





CPU_Controller controller(.SW1(SW1),.SW2(SW2),.CPU_state(cpustate));


cpu mcpu(.data_in(rambus),.clk_quick(clk_quick),.clk_slow(clk_slow),.clk_delay(clk_delay),.zout(Z),
	.rst(rst),.SW_choose(SW_choose),.A1(A1),.cpustate(cpustate),.addr(addr),.data_out(data),.acdbus(acdbus),
	.rdbus(rdbus),.read(read),.write(write),.arload(arload),.arinc(arinc),.trload(trload),.trbus(trbus),
	.rload(rload),.rbus(rbus),.acbus(acbus), .pcload(pcload), .pcinc(pcinc),.pcbus(pcbus),.drdbus(drdbus),
	.membus(membus),.busmem(busmem), .drload(drload),.drlbus(drlbus),.drhbus(drhbus), .acload(acload),
	.bus(dbus),.irout(irout), .irload(irload),.zload(zload),.clr(clr));



ram mm(.clk(clk_mem),.data_in(data),.addr(addr),.A1(A1),.reset(rst),.read(read),.write(write),
		 .cpustate(cpustate),.D(D),.data_out(rambus),.check_out(check_out));






light_show show(.light_clk(clk_light),.SW_choose(SW_choose),.check_in(check_out),.State(cpustate),.MAR(addr[7:0]),
  .AC(acdbus),.R(rdbus),.Z(Z),.HEX0(HEX0),.HEX1(HEX1),.HEX2(HEX2),.HEX3(HEX3),.HEX4(HEX4),.HEX5(HEX5),.HEX6(HEX6),
  .HEX7(HEX7),.State_LED(cpustate_led),.quick_low_led(quick_low_led), .arload(arload), .arinc(arinc),
  .pcinc(pcinc),.pcload(pcload),.drload(drload),.trload(trload),.irload(irload),.rload(rload),.acload(acload),.zload(zload),.pcbus(pcbus),
  .drhbus(drhbus),.drlbus(drlbus),.trbus(trbus),.rbus(rbus),.acbus(acbus),.membus(membus),.busmem(busmen),.clr(clr),
  .read_led(read_led),.write_led(write_led),.arload_led(arload_led),.arinc_led(arinc_led),.pcinc_led(pcinc_led),.pcload_led(pcload_led), 
  .drload_led(drload_led),.trload_led(trload_led),.irload_led(irload_led),.rload_led(rload_led),.acload_led(acload_led),.zload_led(zload_led),
  .pcbus_led(pcbus_led),.drhbus_led(drhbus_led),.drlbus_led(drlbus_led),.trbus_led(trbus_led),.rbus_led(rbus_led),.acbus_led(acbus_led),
  .membus_led(membus_led),.busmem_led(busmem_led),.clr_led(clr_led),.read(read),.write(write));

endmodule