data/full_repos/permissive/516084497/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.behavioral.v
1: b'%Error: data/full_repos/permissive/516084497/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.behavioral.v:25: Can\'t resolve module reference: \'gf180mcu_fd_sc_mcu7t5v0__xor3_4_func\'\n gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/516084497/cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.behavioral.v:25: Multiple top level modules\n                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                  : ... Top module \'gf180mcu_fd_sc_mcu7t5v0__xor3_4\'\nmodule gf180mcu_fd_sc_mcu7t5v0__xor3_4( A2, A1, A3, Z );\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                  : ... Top module \'gf180mcu_fd_sc_mcu7t5v0__xor3_4_func\'\n gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module gf180mcu_fd_sc_mcu7t5v0__xor3_4( A2, A1, A3, Z );
input A1, A2, A3;
output Z;

   `ifdef FUNCTIONAL

	gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_behav_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));

   `else

	gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));








   specify



	if(A2===1'b0 && A3===1'b1)

	 (A1 => Z) = (1.0,1.0);

	if(A2===1'b1 && A3===1'b0)

	 (A1 => Z) = (1.0,1.0);

	ifnone

	 (posedge A1 => (Z:A1)) = (1.0,1.0);

	ifnone

	 (negedge A1 => (Z:A1)) = (1.0,1.0);

	if(A2===1'b0 && A3===1'b0)

	 (A1 => Z) = (1.0,1.0);

	if(A2===1'b1 && A3===1'b1)

	 (A1 => Z) = (1.0,1.0);

	if(A1===1'b0 && A3===1'b1)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b1 && A3===1'b0)

	 (A2 => Z) = (1.0,1.0);

	ifnone

	 (posedge A2 => (Z:A2)) = (1.0,1.0);

	ifnone

	 (negedge A2 => (Z:A2)) = (1.0,1.0);

	if(A1===1'b0 && A3===1'b0)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b1 && A3===1'b1)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b0 && A2===1'b1)

	 (A3 => Z) = (1.0,1.0);

	if(A1===1'b1 && A2===1'b0)

	 (A3 => Z) = (1.0,1.0);

	ifnone

	 (posedge A3 => (Z:A3)) = (1.0,1.0);

	ifnone

	 (negedge A3 => (Z:A3)) = (1.0,1.0);

	if(A1===1'b0 && A2===1'b0)

	 (A3 => Z) = (1.0,1.0);

	if(A1===1'b1 && A2===1'b1)

	 (A3 => Z) = (1.0,1.0);



   endspecify

   `endif

endmodule
module gf180mcu_fd_sc_mcu7t5v0__xor3_4( A2, A1, A3, Z );

input A1, A2, A3;
output Z;

   `ifdef FUNCTIONAL

	gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_behav_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));

   `else

	gf180mcu_fd_sc_mcu7t5v0__xor3_4_func gf180mcu_fd_sc_mcu7t5v0__xor3_4_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));








   specify



	if(A2===1'b0 && A3===1'b1)

	 (A1 => Z) = (1.0,1.0);

	if(A2===1'b1 && A3===1'b0)

	 (A1 => Z) = (1.0,1.0);

	ifnone

	 (posedge A1 => (Z:A1)) = (1.0,1.0);

	ifnone

	 (negedge A1 => (Z:A1)) = (1.0,1.0);

	if(A2===1'b0 && A3===1'b0)

	 (A1 => Z) = (1.0,1.0);

	if(A2===1'b1 && A3===1'b1)

	 (A1 => Z) = (1.0,1.0);

	if(A1===1'b0 && A3===1'b1)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b1 && A3===1'b0)

	 (A2 => Z) = (1.0,1.0);

	ifnone

	 (posedge A2 => (Z:A2)) = (1.0,1.0);

	ifnone

	 (negedge A2 => (Z:A2)) = (1.0,1.0);

	if(A1===1'b0 && A3===1'b0)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b1 && A3===1'b1)

	 (A2 => Z) = (1.0,1.0);

	if(A1===1'b0 && A2===1'b1)

	 (A3 => Z) = (1.0,1.0);

	if(A1===1'b1 && A2===1'b0)

	 (A3 => Z) = (1.0,1.0);

	ifnone

	 (posedge A3 => (Z:A3)) = (1.0,1.0);

	ifnone

	 (negedge A3 => (Z:A3)) = (1.0,1.0);

	if(A1===1'b0 && A2===1'b0)

	 (A3 => Z) = (1.0,1.0);

	if(A1===1'b1 && A2===1'b1)

	 (A3 => Z) = (1.0,1.0);



   endspecify

   `endif

endmodule