data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\nforever #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n#400\n^\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n#400\n^\n%Error: data/full_repos/permissive/514835397/tb/uart_transmitter_TB.v:10: Cannot find file containing module: \'uart_transmitter\'\nuart_transmitter dut\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/uart_transmitter\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/uart_transmitter.v\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/uart_transmitter.sv\n             uart_transmitter\n             uart_transmitter.v\n             uart_transmitter.sv\n             obj_dir/uart_transmitter\n             obj_dir/uart_transmitter.v\n             obj_dir/uart_transmitter.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_transmitter_TB();

wire suart_tx_o;
wire sdata_buffer_full_o;
reg [7:0] sdata_i;
reg [5:0] sdata_buffer_full_thres_i;
reg sdata_write_i, sclock_i, sreset_n_i;
reg [1:0] sbaudrate_select_i;

uart_transmitter dut
(
	.data_i(sdata_i),
	.data_write_i(sdata_write_i),
	.data_buffer_full_o(sdata_buffer_full_o),
	.data_buffer_full_thres_i(sdata_buffer_full_thres_i),
	.baudrate_select_i(sbaudrate_select_i),
	.clock_i(sclock_i),
	.reset_n_i(sreset_n_i),
	.uart_tx_o(suart_tx_o)
);

initial begin
	sclock_i = 0;
forever #2
	sclock_i = ~sclock_i;
end

initial begin
	sreset_n_i = 0;
	sdata_buffer_full_thres_i = 32;
	sdata_i = 8'b10101110;
	sbaudrate_select_i = 0;
	sdata_write_i = 0;
#4
	sreset_n_i = 1;
	sdata_write_i = 1;
#400
	sdata_write_i = 0;
#400
	$stop;
end

endmodule
module uart_transmitter_TB();


wire suart_tx_o;
wire sdata_buffer_full_o;
reg [7:0] sdata_i;
reg [5:0] sdata_buffer_full_thres_i;
reg sdata_write_i, sclock_i, sreset_n_i;
reg [1:0] sbaudrate_select_i;

uart_transmitter dut
(
	.data_i(sdata_i),
	.data_write_i(sdata_write_i),
	.data_buffer_full_o(sdata_buffer_full_o),
	.data_buffer_full_thres_i(sdata_buffer_full_thres_i),
	.baudrate_select_i(sbaudrate_select_i),
	.clock_i(sclock_i),
	.reset_n_i(sreset_n_i),
	.uart_tx_o(suart_tx_o)
);

initial begin
	sclock_i = 0;
forever #2
	sclock_i = ~sclock_i;
end

initial begin
	sreset_n_i = 0;
	sdata_buffer_full_thres_i = 32;
	sdata_i = 8'b10101110;
	sbaudrate_select_i = 0;
	sdata_write_i = 0;
#4
	sreset_n_i = 1;
	sdata_write_i = 1;
#400
	sdata_write_i = 0;
#400
	$stop;
end

endmodule