data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/pipestage.v
data/verilator_xmls/21fd1181-783b-49b0-96eb-08924e1b05be.xml
module pipestage
  #(parameter TAGWIDTH = 1)
   (input clk,
    input reset,
    input stb_in,
    input stb_out,
    output reg valid,
    input [TAGWIDTH-1:0] tag_in,
    output reg [TAGWIDTH-1:0] tag_out);

   always @(posedge clk)
     if(reset)
       begin
	  valid <= 0;
	  tag_out <= 0;
       end
     else if(stb_in)
       begin
	  valid <= 1;
	  tag_out <= tag_in;
       end
     else if(stb_out)
       begin
	  valid <= 0;
	  tag_out <= 0;
       end
   
endmodule
module pipestage
  #(parameter TAGWIDTH = 1)
   (input clk,
    input reset,
    input stb_in,
    input stb_out,
    output reg valid,
    input [TAGWIDTH-1:0] tag_in,
    output reg [TAGWIDTH-1:0] tag_out);


   always @(posedge clk)
     if(reset)
       begin
	  valid <= 0;
	  tag_out <= 0;
       end
     else if(stb_in)
       begin
	  valid <= 1;
	  tag_out <= tag_in;
       end
     else if(stb_out)
       begin
	  valid <= 0;
	  tag_out <= 0;
       end
   
endmodule