data/full_repos/permissive/423539813/source_files/BasicStructure.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/423539813/source_files/BasicStructure.v:147: Cell has missing pin: \'instruction_type\'\n Control_Unit controller(.opcode(instruction[6:0]) , .func3(instruction[14:12]) , .func7(instruction[31:25]), .ZeroOut(ZeroOut), .CarryOut(CarryOut),\n              ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:136: Cannot find file containing module: \'adder\'\n adder pcplus4ins(.a(pc),.b(32\'h4),.y(PCPlus4));\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder.v\n             data/full_repos/permissive/423539813/source_files,data/full_repos/permissive/423539813/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:138: Cannot find file containing module: \'adder\'\n adder pctargetins(.a(pc),.b(immext),.y(PCTarget));\n ^~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:142: Cannot find file containing module: \'instruction_memory\'\n instruction_memory instructionmemory(.pc(pc),.instruction(instruction));\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:152: Cannot find file containing module: \'extend\'\n     extend ext(.instruction(instruction[31:7]), .immsrc(immsrc), .immext(immext));\n     ^~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:154: Cannot find file containing module: \'register_file\'\n     register_file registerfile(.Port_A(Port_A), .Port_B(Port_B),.hardwire(hardwire), .RESULT(RESULT), .Addr_A(instruction[19:15]), .Addr_B(instruction[24:20]), .Addr_Wr(instruction[11:7]), .wr(RegWrite), .clk(clk),.rst(rst));\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:156: Cannot find file containing module: \'alu\'\n     alu alu( .A(Port_A),.B(B),.ALU_Sel(ALUControl),.ALU_Out(ALU_Out),.CarryOut(CarryOut), .ZeroOut(ZeroOut));\n     ^~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:158: Cannot find file containing module: \'address_gen\'\n     address_gen AddressGenerator(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423539813/source_files/BasicStructure.v:162: Cannot find file containing module: \'Data_Memory\'\n     Data_Memory datamemory(.Data_Out(Data_Out),.Data_In(Port_B),.D_Addr(ALU_Out), .wr(MemWrite), .rst(rst),.clk(clk));\n     ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module Control_Unit(input [6:0] opcode , input [2:0] func3 , input [6:0] func7,input ZeroOut,input CarryOut,
					output reg PCSrc, MemWrite, ALUSrc, RegWrite,
					output reg [3:0] ALUControl,
					output reg  ResultSrc,
					output [1:0] ImmSrc,
					output reg [2:0] instruction_type);			

	
	always @ (*)
	begin
	case (opcode)
	7'b0010011: instruction_type = 3'd0;
	7'b1100111: instruction_type = 3'd0;
	7'b0000011: instruction_type = 3'd0;
	7'b0100011: instruction_type = 3'd1;
	7'b1100011: instruction_type = 3'd2;
	7'b1101111: instruction_type = 3'd3;
	7'b0110011: instruction_type = 3'd4;
	7'b0110111: instruction_type = 3'd5;
	7'b0010111: instruction_type = 3'd5;
	default: instruction_type = 3'd0; 
	endcase
	end
	assign ImmSrc = instruction_type[1:0];
	always @(*)
	begin
	if (instruction_type == 0 || instruction_type == 3'd4 || instruction_type == 3'd5 || instruction_type == 3'd3)
        RegWrite=1;
     else
        RegWrite =0;
            
    if (instruction_type==1)
        MemWrite=1;
    else
        MemWrite=0;
        
    if(opcode == 7'b0000011)
        ResultSrc = 1;


    else
        ResultSrc =0;
        
    if ( instruction_type== 3'd2 || instruction_type == 3'd4)
        ALUSrc = 0;
    else
        ALUSrc =1;
    end
	
	always @(*)
    begin
        casex({opcode,func3,func7})
        17'b01100110000000000: ALUControl = 4'b0000;
        17'b01100110000100000: ALUControl = 4'b0001;
        17'b01100110000000001: ALUControl = 4'b0010;
        17'b01100111000000001: ALUControl = 4'b0011;
        17'b0010011000xxxxxxx: ALUControl = 4'b0000;
        17'b1100011000xxxxxxx: ALUControl = 4'b0001;
        17'b1100011001xxxxxxx: ALUControl = 4'b0001;
        17'b1100011100xxxxxxx: ALUControl = 4'b0001;
            
        endcase
    end
        
    always @(*)
        begin
            casex({opcode,func3})
                10'b1101111xxx, 10'b1100111xxx: PCSrc = 1;
                10'b1100011000: PCSrc = ZeroOut;
                10'b1100011001: PCSrc = ~ZeroOut;
                10'b1100011101, 10'b1100011111 : PCSrc = (~CarryOut) || ZeroOut;
                10'b1100011100, 10'b1100011111: PCSrc =CarryOut;
                default: PCSrc=0;
            endcase
        end
	
endmodule
module Control_Unit(input [6:0] opcode , input [2:0] func3 , input [6:0] func7,input ZeroOut,input CarryOut,
					output reg PCSrc, MemWrite, ALUSrc, RegWrite,
					output reg [3:0] ALUControl,
					output reg  ResultSrc,
					output [1:0] ImmSrc,
					output reg [2:0] instruction_type);
			

	
	always @ (*)
	begin
	case (opcode)
	7'b0010011: instruction_type = 3'd0;
	7'b1100111: instruction_type = 3'd0;
	7'b0000011: instruction_type = 3'd0;
	7'b0100011: instruction_type = 3'd1;
	7'b1100011: instruction_type = 3'd2;
	7'b1101111: instruction_type = 3'd3;
	7'b0110011: instruction_type = 3'd4;
	7'b0110111: instruction_type = 3'd5;
	7'b0010111: instruction_type = 3'd5;
	default: instruction_type = 3'd0; 
	endcase
	end
	assign ImmSrc = instruction_type[1:0];
	always @(*)
	begin
	if (instruction_type == 0 || instruction_type == 3'd4 || instruction_type == 3'd5 || instruction_type == 3'd3)
        RegWrite=1;
     else
        RegWrite =0;
            
    if (instruction_type==1)
        MemWrite=1;
    else
        MemWrite=0;
        
    if(opcode == 7'b0000011)
        ResultSrc = 1;


    else
        ResultSrc =0;
        
    if ( instruction_type== 3'd2 || instruction_type == 3'd4)
        ALUSrc = 0;
    else
        ALUSrc =1;
    end
	
	always @(*)
    begin
        casex({opcode,func3,func7})
        17'b01100110000000000: ALUControl = 4'b0000;
        17'b01100110000100000: ALUControl = 4'b0001;
        17'b01100110000000001: ALUControl = 4'b0010;
        17'b01100111000000001: ALUControl = 4'b0011;
        17'b0010011000xxxxxxx: ALUControl = 4'b0000;
        17'b1100011000xxxxxxx: ALUControl = 4'b0001;
        17'b1100011001xxxxxxx: ALUControl = 4'b0001;
        17'b1100011100xxxxxxx: ALUControl = 4'b0001;
            
        endcase
    end
        
    always @(*)
        begin
            casex({opcode,func3})
                10'b1101111xxx, 10'b1100111xxx: PCSrc = 1;
                10'b1100011000: PCSrc = ZeroOut;
                10'b1100011001: PCSrc = ~ZeroOut;
                10'b1100011101, 10'b1100011111 : PCSrc = (~CarryOut) || ZeroOut;
                10'b1100011100, 10'b1100011111: PCSrc =CarryOut;
                default: PCSrc=0;
            endcase
        end
	
endmodule