data/full_repos/permissive/451048101/src/fpga/zynq7020/rule_lookup_1to2.v
1: b"%Error: data/full_repos/permissive/451048101/src/fpga/zynq7020/rule_lookup_1to2.v:147: Cannot find file containing module: 'fifo_64b_512'\n  fifo_64b_512 fifo_meta (\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/fifo_64b_512\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/fifo_64b_512.v\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/fifo_64b_512.sv\n             fifo_64b_512\n             fifo_64b_512.v\n             fifo_64b_512.sv\n             obj_dir/fifo_64b_512\n             obj_dir/fifo_64b_512.v\n             obj_dir/fifo_64b_512.sv\n%Error: Exiting due to 1 error(s)\n"
module rule_lookup_1to2(
	input						rst_n,
	input						clk,
	input			[511:0]		metadata_in,
	input			[3:0]		metadata_in_valid,
	input			[3:0]		rden_metadata,
	output	wire	[3:0]		empty_metadata,
	output	wire	[511:0]		data_metadata
	
);

wire	[63:0]	metadata_in_w[3:0];
assign	{metadata_in_w[3],metadata_in_w[2],metadata_in_w[1],
			metadata_in_w[0]} = {metadata_in[447:384],
			metadata_in[319:256],metadata_in[191:128],metadata_in[63:0]};


(* mark_debug = "true"*)reg		[3:0]	wren_meta;
(* mark_debug = "true"*)reg		[63:0]	din_meta;
(* mark_debug = "true"*)wire	[63:0]	dout_meta[3:0];

assign	data_metadata = {64'b0,dout_meta[3],64'b0,dout_meta[2],
							64'b0,dout_meta[1],64'b0,dout_meta[0]};

reg		[3:0]	bitmap_match[3:0];
integer i,j;





(* mark_debug = "true"*)reg		[63:0]	temp_meta[3:0];
(* mark_debug = "true"*)reg		[3:0]	metaIn_ready[1:0];
(* mark_debug = "true"*)wire	[3:0]	tag_metaIn_ready;


(* mark_debug = "true"*)reg		[7:0]	cnt_pkt_recv, cnt_pkt_send;

assign	tag_metaIn_ready = metaIn_ready[1]^metaIn_ready[0];

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		din_meta			<= 64'b0;
		for(i=0; i<4; i=i+1) begin
			wren_meta[i]	<= 1'b0;
			temp_meta[i]	<= 64'b0;
			bitmap_match[i]	<= 4'b0;
		end
		metaIn_ready[0]		<= 4'b0;
		metaIn_ready[1]		<= 4'b0;

		cnt_pkt_recv		<= 8'b0;
		cnt_pkt_send		<= 8'b0;
	end
	else begin



		for(i=0; i<4; i=i+1) begin
			if(metadata_in_valid[i] == 1'b1) begin
				temp_meta[i]		<= metadata_in_w[i];
				metaIn_ready[0][i]	<= ~metaIn_ready[0][i];









				if(metadata_in_w[i][55] == 1'b1) begin
					cnt_pkt_recv		<= 8'd1 + cnt_pkt_recv;
					if(metadata_in_w[i][49:48] == 2'b0)
						bitmap_match[i]	<= 4'b1111;
					else if(metadata_in_w[i][49:48] == 2'd3)
						bitmap_match[i]	<= 4'b0;
					else
						bitmap_match[i]	<= 4'b1 << metadata_in_w[i][41:40];
				end
				else begin

					bitmap_match[i]		<= 4'b0;
				end
			end
		end
		


		wren_meta					<= 4'b0;
		if(tag_metaIn_ready != 4'h0) begin
			(* parallel_case, full_case *)
			casez(tag_metaIn_ready)
				4'b1???: begin
					din_meta			<= temp_meta[3];
					wren_meta			<= bitmap_match[3];
					metaIn_ready[1][3]	<= ~metaIn_ready[1][3];
				end
				4'b01??: begin
					din_meta			<= temp_meta[2];
					wren_meta			<= bitmap_match[2];
					metaIn_ready[1][2]	<= ~metaIn_ready[1][2];
				end
				4'b001?: begin
					din_meta			<= temp_meta[1];
					wren_meta			<= bitmap_match[1];
					metaIn_ready[1][1]	<= ~metaIn_ready[1][1];
				end
				4'b0001: begin
					din_meta			<= temp_meta[0];
					wren_meta			<= bitmap_match[0];
					metaIn_ready[1][0]	<= ~metaIn_ready[1][0];
				end
			endcase
		end
	end
end



genvar i_port;
generate
	for (i_port = 0; i_port < 4; i_port = i_port+1) begin: fifo_inst
		fifo_64b_512 fifo_meta (
			.clk(clk),
			.srst(!rst_n),
			.din(din_meta),
			.wr_en(wren_meta[i_port]),
			.rd_en(rden_metadata[i_port]),
			.dout(dout_meta[i_port]),
			.full(),
			.empty(empty_metadata[i_port]),
			.data_count()
		);
	end
endgenerate



endmodule
module rule_lookup_1to2(
	input						rst_n,
	input						clk,
	input			[511:0]		metadata_in,
	input			[3:0]		metadata_in_valid,
	input			[3:0]		rden_metadata,
	output	wire	[3:0]		empty_metadata,
	output	wire	[511:0]		data_metadata
	
);


wire	[63:0]	metadata_in_w[3:0];
assign	{metadata_in_w[3],metadata_in_w[2],metadata_in_w[1],
			metadata_in_w[0]} = {metadata_in[447:384],
			metadata_in[319:256],metadata_in[191:128],metadata_in[63:0]};


(* mark_debug = "true"*)reg		[3:0]	wren_meta;
(* mark_debug = "true"*)reg		[63:0]	din_meta;
(* mark_debug = "true"*)wire	[63:0]	dout_meta[3:0];

assign	data_metadata = {64'b0,dout_meta[3],64'b0,dout_meta[2],
							64'b0,dout_meta[1],64'b0,dout_meta[0]};

reg		[3:0]	bitmap_match[3:0];
integer i,j;





(* mark_debug = "true"*)reg		[63:0]	temp_meta[3:0];
(* mark_debug = "true"*)reg		[3:0]	metaIn_ready[1:0];
(* mark_debug = "true"*)wire	[3:0]	tag_metaIn_ready;


(* mark_debug = "true"*)reg		[7:0]	cnt_pkt_recv, cnt_pkt_send;

assign	tag_metaIn_ready = metaIn_ready[1]^metaIn_ready[0];

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		din_meta			<= 64'b0;
		for(i=0; i<4; i=i+1) begin
			wren_meta[i]	<= 1'b0;
			temp_meta[i]	<= 64'b0;
			bitmap_match[i]	<= 4'b0;
		end
		metaIn_ready[0]		<= 4'b0;
		metaIn_ready[1]		<= 4'b0;

		cnt_pkt_recv		<= 8'b0;
		cnt_pkt_send		<= 8'b0;
	end
	else begin



		for(i=0; i<4; i=i+1) begin
			if(metadata_in_valid[i] == 1'b1) begin
				temp_meta[i]		<= metadata_in_w[i];
				metaIn_ready[0][i]	<= ~metaIn_ready[0][i];









				if(metadata_in_w[i][55] == 1'b1) begin
					cnt_pkt_recv		<= 8'd1 + cnt_pkt_recv;
					if(metadata_in_w[i][49:48] == 2'b0)
						bitmap_match[i]	<= 4'b1111;
					else if(metadata_in_w[i][49:48] == 2'd3)
						bitmap_match[i]	<= 4'b0;
					else
						bitmap_match[i]	<= 4'b1 << metadata_in_w[i][41:40];
				end
				else begin

					bitmap_match[i]		<= 4'b0;
				end
			end
		end
		


		wren_meta					<= 4'b0;
		if(tag_metaIn_ready != 4'h0) begin
			(* parallel_case, full_case *)
			casez(tag_metaIn_ready)
				4'b1???: begin
					din_meta			<= temp_meta[3];
					wren_meta			<= bitmap_match[3];
					metaIn_ready[1][3]	<= ~metaIn_ready[1][3];
				end
				4'b01??: begin
					din_meta			<= temp_meta[2];
					wren_meta			<= bitmap_match[2];
					metaIn_ready[1][2]	<= ~metaIn_ready[1][2];
				end
				4'b001?: begin
					din_meta			<= temp_meta[1];
					wren_meta			<= bitmap_match[1];
					metaIn_ready[1][1]	<= ~metaIn_ready[1][1];
				end
				4'b0001: begin
					din_meta			<= temp_meta[0];
					wren_meta			<= bitmap_match[0];
					metaIn_ready[1][0]	<= ~metaIn_ready[1][0];
				end
			endcase
		end
	end
end



genvar i_port;
generate
	for (i_port = 0; i_port < 4; i_port = i_port+1) begin: fifo_inst
		fifo_64b_512 fifo_meta (
			.clk(clk),
			.srst(!rst_n),
			.din(din_meta),
			.wr_en(wren_meta[i_port]),
			.rd_en(rden_metadata[i_port]),
			.dout(dout_meta[i_port]),
			.full(),
			.empty(empty_metadata[i_port]),
			.data_count()
		);
	end
endgenerate



endmodule