data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga/tc_clk_xilinx.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga/tc_clk_xilinx.sv:23: Multiple top level modules\n                                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                             : ... Top module \'tc_clk_and2\'\nmodule tc_clk_and2 (\n       ^~~~~~~~~~~\n                                                                                                                             : ... Top module \'tc_clk_buffer\'\nmodule tc_clk_buffer (\n       ^~~~~~~~~~~~~\n                                                                                                                             : ... Top module \'tc_clk_gating\'\nmodule tc_clk_gating (\n       ^~~~~~~~~~~~~\n                                                                                                                             : ... Top module \'tc_clk_inverter\'\nmodule tc_clk_inverter (\n       ^~~~~~~~~~~~~~~\n                                                                                                                             : ... Top module \'tc_clk_mux2\'\nmodule tc_clk_mux2 (\n       ^~~~~~~~~~~\n                                                                                                                             : ... Top module \'tc_clk_xor2\'\nmodule tc_clk_xor2 (\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga/tc_clk_xilinx.sv:60: Cannot find file containing module: \'BUFGMUX\'\n  BUFGMUX i_BUFGMUX (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/BUFGMUX\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/BUFGMUX.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/BUFGMUX.sv\n             BUFGMUX\n             BUFGMUX.v\n             BUFGMUX.sv\n             obj_dir/BUFGMUX\n             obj_dir/BUFGMUX.v\n             obj_dir/BUFGMUX.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module tc_clk_inverter (
  input  logic clk_i,
  output logic clk_o
);

  assign clk_o = ~clk_i;

endmodule
module tc_clk_inverter (
  input  logic clk_i,
  output logic clk_o
);


  assign clk_o = ~clk_i;

endmodule