data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_DL_2_1_mux.v
data/verilator_xmls/e733eb48-67d5-4118-9f7d-fca3a0697d9b.xml
module bm_DL_2_1_mux  (w0, w1, s, f);
	input w0, w1, s;
	output f;
	
	assign f = s ? w1 : w0;
		
endmodule
module bm_DL_2_1_mux  (w0, w1, s, f);

	input w0, w1, s;
	output f;
	
	assign f = s ? w1 : w0;
		
endmodule