data/full_repos/permissive/485129576/regfile.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/485129576/regfile.v:19: Signal definition not found, creating implicitly: \'t0\'\n                                                                    : ... Suggested alternative: \'C0\'\n    assign C0 = write && t0;\n                         ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/485129576/regfile.v:20: Signal definition not found, creating implicitly: \'t1\'\n                                                                    : ... Suggested alternative: \'C1\'\n    assign C1 = write && t1;\n                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/485129576/regfile.v:21: Signal definition not found, creating implicitly: \'t2\'\n                                                                    : ... Suggested alternative: \'C2\'\n    assign C2 = write && t2;\n                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/485129576/regfile.v:22: Signal definition not found, creating implicitly: \'t3\'\n                                                                    : ... Suggested alternative: \'C3\'\n    assign C3 = write && t3;\n                         ^~\n%Error: data/full_repos/permissive/485129576/regfile.v:17: Cannot find file containing module: \'DEMUX4t1\'\n    DEMUX4t1 demux(.sel(selDin), .A(t0), .B(t1), .C(t2), .D(t3));\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/DEMUX4t1\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/DEMUX4t1.v\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/DEMUX4t1.sv\n             DEMUX4t1\n             DEMUX4t1.v\n             DEMUX4t1.sv\n             obj_dir/DEMUX4t1\n             obj_dir/DEMUX4t1.v\n             obj_dir/DEMUX4t1.sv\n%Error: data/full_repos/permissive/485129576/regfile.v:26: Cannot find file containing module: \'REG8\'\n    REG8 X0(.D(data), .Q(Q0), .clkR(C0));\n    ^~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:27: Cannot find file containing module: \'REG8\'\n    REG8 X1(.D(data), .Q(Q1), .clkR(C1));\n    ^~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:28: Cannot find file containing module: \'REG8\'\n    REG8 X2(.D(data), .Q(Q2), .clkR(C2));\n    ^~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:29: Cannot find file containing module: \'REG8\'\n    REG8 X3(.D(data), .Q(Q3), .clkR(C3));\n    ^~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:31: Cannot find file containing module: \'REG2\'\n    REG2 X4(.D(flagsIn), .Q(Q4), .clkR(C4));\n    ^~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:33: Cannot find file containing module: \'MUX4t1\'\n    MUX4t1 muxA(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selAout), .R(muxAout));\n    ^~~~~~\n%Error: data/full_repos/permissive/485129576/regfile.v:34: Cannot find file containing module: \'MUX4t1\'\n    MUX4t1 muxB(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selBout), .R(muxBout));\n    ^~~~~~\n%Error: Exiting due to 8 error(s), 4 warning(s)\n'
module REGFILE (
    input [1:0] selDin,
    input [1:0] selAout,
    input [1:0] selBout,
    input [1:0] flagsIn,
    input write,
    input [7:0] data,
    output wire [7:0] regoutA,
    output wire [7:0] regoutB,
    output wire [1:0] flagsOut
);
    wire C0, C1, C2, C3, C4;
    wire [7:0] Q0, Q1, Q2, Q3;
    wire [1:0] Q4;
    wire [7:0] muxAout, muxBout;

    DEMUX4t1 demux(.sel(selDin), .A(t0), .B(t1), .C(t2), .D(t3));

    assign C0 = write && t0;
    assign C1 = write && t1;
    assign C2 = write && t2;
    assign C3 = write && t3;

    assign C4 = write;

    REG8 X0(.D(data), .Q(Q0), .clkR(C0));
    REG8 X1(.D(data), .Q(Q1), .clkR(C1));
    REG8 X2(.D(data), .Q(Q2), .clkR(C2));
    REG8 X3(.D(data), .Q(Q3), .clkR(C3));

    REG2 X4(.D(flagsIn), .Q(Q4), .clkR(C4));

    MUX4t1 muxA(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selAout), .R(muxAout));
    MUX4t1 muxB(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selBout), .R(muxBout));

    assign regoutA = muxAout;
    assign regoutB = muxBout;

    assign flagsOut = Q4;

endmodule
module REGFILE (
    input [1:0] selDin,
    input [1:0] selAout,
    input [1:0] selBout,
    input [1:0] flagsIn,
    input write,
    input [7:0] data,
    output wire [7:0] regoutA,
    output wire [7:0] regoutB,
    output wire [1:0] flagsOut
);

    wire C0, C1, C2, C3, C4;
    wire [7:0] Q0, Q1, Q2, Q3;
    wire [1:0] Q4;
    wire [7:0] muxAout, muxBout;

    DEMUX4t1 demux(.sel(selDin), .A(t0), .B(t1), .C(t2), .D(t3));

    assign C0 = write && t0;
    assign C1 = write && t1;
    assign C2 = write && t2;
    assign C3 = write && t3;

    assign C4 = write;

    REG8 X0(.D(data), .Q(Q0), .clkR(C0));
    REG8 X1(.D(data), .Q(Q1), .clkR(C1));
    REG8 X2(.D(data), .Q(Q2), .clkR(C2));
    REG8 X3(.D(data), .Q(Q3), .clkR(C3));

    REG2 X4(.D(flagsIn), .Q(Q4), .clkR(C4));

    MUX4t1 muxA(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selAout), .R(muxAout));
    MUX4t1 muxB(.A(Q0), .B(Q1), .C(Q2), .D(Q3), .sel(selBout), .R(muxBout));

    assign regoutA = muxAout;
    assign regoutB = muxBout;

    assign flagsOut = Q4;

endmodule