data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/mux4x1_test.v
1: b"%Error: data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/mux4x1_test.v:1: syntax error, unexpected ',', expecting '['\nmodule mux4x1_test(t1, t2,, p);\n                          ^\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/03_mux4x1/mux4x1_test.v:9: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mux4x1_test(t1, t2,, p);
output [3:0]t1;
output [1:0]t2;
input p;

reg [3:0] t1;
reg [1:0] t2;

initial begin
   t1 <= 4'b0101;
   t2 <= 2'b00;

   #100;
   t2 <= 2'b01;

    #100;
   t2 <= 2'b10;

    #100;
   t2 <= 2'b11;

    #100;
    $finish;
end

endmodule
module mux4x1_test(t1, t2,, p);

output [3:0]t1;
output [1:0]t2;
input p;

reg [3:0] t1;
reg [1:0] t2;

initial begin
   t1 <= 4'b0101;
   t2 <= 2'b00;

   #100;
   t2 <= 2'b01;

    #100;
   t2 <= 2'b10;

    #100;
   t2 <= 2'b11;

    #100;
    $finish;
end

endmodule