data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlnosegintxwrp.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlnosegintxwrp.v:130: Cannot find file containing module: 'fflopx'\nfflopx #(3) alrmrestpli\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/at6rtlnosegintxwrp.v:226: Cannot find file containing module: 'at6rtlnosegintx'\nat6rtlnosegintx  #(STYW,STAW,STCHEW,SEGB,SEGNUM,UPW) at6rtlnosegintxi    \n^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module at6rtlnosegintxwrp
    (
     iclk,
     rst,
     ipactive,

     ialrmrest,
  

     iupen,
     iupa,
     iupws,
     iuprs,
     iupdi,
     ouprdy,
     oupdo,
     oupint,

     idtvl,
     isegid,
    
     istyreq,
     ista,
     ista_msk,
     ista_chgen,
     iinttypeen,


     ochwe,
     ochwa,     
     ochwrd,    
     ochre,
     ochra,
     ichrdd
     );
     



parameter   STYW        = 5;
parameter   STAW        = 5;
parameter   STCHEW      = 5;

parameter   SEGB        = 4;

parameter   SEGNUM      = 12;

parameter   UPW         = 12;

parameter   UPA         = SEGB + 2;

parameter   CHAW        = SEGB;
parameter   CHDW        = 2*STYW + STAW;



input               iclk;
input               rst;
input               ipactive;

input               ialrmrest;



input               iupen;
input [UPA-1:0]     iupa;
input               iupws;
input               iuprs;
input [UPW-1:0]     iupdi;
output              ouprdy;
output [UPW-1:0]    oupdo;
output              oupint;

input               idtvl;
input [SEGB-1:0]    isegid;
input [STYW-1:0]    istyreq;
input [STAW-1:0]    ista;



input [STAW-1:0]    ista_msk;
input [STCHEW-1:0]  ista_chgen;

input [STYW-1:0]    iinttypeen;









output              ochwe;
output [CHAW-1:0]   ochwa;
output [CHDW-1:0]   ochwrd;
output              ochre;
output [CHAW-1:0]   ochra;
input [CHDW-1:0]    ichrdd;







parameter   IDLE        = 3'd0;
parameter   PREREAD     = 3'd1;
parameter   WAIT1       = 3'd2;
parameter   WAIT2       = 3'd3;
parameter   CLEARSTA    = 3'd4;
parameter   SETSTK      = 3'd5;


wire [2:0]         alrmrestpl;

fflopx #(3) alrmrestpli
    (iclk,rst,{alrmrestpl[1:0],ialrmrest},alrmrestpl);

wire                alrmrestpos  = alrmrestpl[1] & (!alrmrestpl[2]);

reg [SEGB-1:0]      alrmrestcnt = 0;
reg                 dtvli;
reg [SEGB-1:0]      segidi;
reg [STYW-1:0]      styreqi;
reg [STAW-1:0]      stai;
reg [STAW-1:0]      stalat;
reg [STAW-1:0]      sta_mski;
reg [STCHEW-1:0]    sta_chgeni;
reg [STYW-1:0]      inttypeen;

reg [2:0]           alrmreststate = 3'd0;

wire               alrmregvl    = |{alrmrestcnt,alrmrestpos};



always @(posedge iclk)
    begin

        case(alrmreststate)
            IDLE:
                begin
                alrmreststate   <= alrmrestpos ? PREREAD : IDLE;
                alrmrestcnt     <= {SEGB{1'b0}};
                dtvli       <= idtvl;
                segidi      <= isegid;
                styreqi     <= istyreq;
                stai        <= ista;
                sta_mski    <= ista_msk;
                sta_chgeni  <= ista_chgen;
                inttypeen   <= iinttypeen;              
                end
            PREREAD:
                begin
                dtvli       <= 1'b1;
                segidi      <= alrmrestcnt;
                styreqi     <= {STYW{1'b0}};
                stai        <= {STAW{1'b0}};
                sta_mski    <= {STAW{1'b0}};
                sta_chgeni  <= {STCHEW{1'b1}};
                inttypeen   <= {STYW{1'b1}};                
                
                alrmreststate   <= WAIT1;
                end
            WAIT1:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT2;
                end
            WAIT2:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= CLEARSTA;
                end
            CLEARSTA:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt;
                styreqi         <= {STYW{1'b0}};
                stai            <= {STAW{1'b0}};
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                stalat          <= ichrdd[STYW+STAW-1:STYW];
                alrmreststate   <= SETSTK;
                end
            SETSTK:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt;
                styreqi         <= {STYW{1'b0}};
                stai            <= stalat;
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                alrmreststate   <= &alrmrestcnt ? IDLE: PREREAD;
                
                alrmrestcnt     <= alrmrestcnt + 1'b1;
                end
            default:
                begin
                alrmreststate   <= IDLE;
                dtvli           <= 1'b0;
                end
        endcase
        
    end


at6rtlnosegintx  #(STYW,STAW,STCHEW,SEGB,SEGNUM,UPW) at6rtlnosegintxi    
    (
     .iclk      (iclk),
     .rst       (rst),
     .ipactive  (ipactive),

     .iupen     (iupen),
     .iupa      (iupa),
     .iupws     (iupws),
     .iuprs     (iuprs),
     .iupdi     (iupdi),
     .ouprdy    (ouprdy),
     .oupdo     (oupdo),
     .oupint    (oupint),

     .idtvl     (dtvli),
     .isegid    (segidi),
    
     .istyreq   (styreqi),
     .ista      (stai),
     .ista_msk  (sta_mski),
     .ista_chgen(sta_chgeni),
     .iinttypeen(inttypeen),


     .ochwe (ochwe),
     .ochwa (ochwa),     
     .ochwrd(ochwrd),    
     .ochre (ochre),
     .ochra (ochra),
     .ichrdd(ichrdd)
     );
        
endmodule
module at6rtlnosegintxwrp
    (
     iclk,
     rst,
     ipactive,

     ialrmrest,
  

     iupen,
     iupa,
     iupws,
     iuprs,
     iupdi,
     ouprdy,
     oupdo,
     oupint,

     idtvl,
     isegid,
    
     istyreq,
     ista,
     ista_msk,
     ista_chgen,
     iinttypeen,


     ochwe,
     ochwa,     
     ochwrd,    
     ochre,
     ochra,
     ichrdd
     );

     



parameter   STYW        = 5;
parameter   STAW        = 5;
parameter   STCHEW      = 5;

parameter   SEGB        = 4;

parameter   SEGNUM      = 12;

parameter   UPW         = 12;

parameter   UPA         = SEGB + 2;

parameter   CHAW        = SEGB;
parameter   CHDW        = 2*STYW + STAW;



input               iclk;
input               rst;
input               ipactive;

input               ialrmrest;



input               iupen;
input [UPA-1:0]     iupa;
input               iupws;
input               iuprs;
input [UPW-1:0]     iupdi;
output              ouprdy;
output [UPW-1:0]    oupdo;
output              oupint;

input               idtvl;
input [SEGB-1:0]    isegid;
input [STYW-1:0]    istyreq;
input [STAW-1:0]    ista;



input [STAW-1:0]    ista_msk;
input [STCHEW-1:0]  ista_chgen;

input [STYW-1:0]    iinttypeen;









output              ochwe;
output [CHAW-1:0]   ochwa;
output [CHDW-1:0]   ochwrd;
output              ochre;
output [CHAW-1:0]   ochra;
input [CHDW-1:0]    ichrdd;







parameter   IDLE        = 3'd0;
parameter   PREREAD     = 3'd1;
parameter   WAIT1       = 3'd2;
parameter   WAIT2       = 3'd3;
parameter   CLEARSTA    = 3'd4;
parameter   SETSTK      = 3'd5;


wire [2:0]         alrmrestpl;

fflopx #(3) alrmrestpli
    (iclk,rst,{alrmrestpl[1:0],ialrmrest},alrmrestpl);

wire                alrmrestpos  = alrmrestpl[1] & (!alrmrestpl[2]);

reg [SEGB-1:0]      alrmrestcnt = 0;
reg                 dtvli;
reg [SEGB-1:0]      segidi;
reg [STYW-1:0]      styreqi;
reg [STAW-1:0]      stai;
reg [STAW-1:0]      stalat;
reg [STAW-1:0]      sta_mski;
reg [STCHEW-1:0]    sta_chgeni;
reg [STYW-1:0]      inttypeen;

reg [2:0]           alrmreststate = 3'd0;

wire               alrmregvl    = |{alrmrestcnt,alrmrestpos};



always @(posedge iclk)
    begin

        case(alrmreststate)
            IDLE:
                begin
                alrmreststate   <= alrmrestpos ? PREREAD : IDLE;
                alrmrestcnt     <= {SEGB{1'b0}};
                dtvli       <= idtvl;
                segidi      <= isegid;
                styreqi     <= istyreq;
                stai        <= ista;
                sta_mski    <= ista_msk;
                sta_chgeni  <= ista_chgen;
                inttypeen   <= iinttypeen;              
                end
            PREREAD:
                begin
                dtvli       <= 1'b1;
                segidi      <= alrmrestcnt;
                styreqi     <= {STYW{1'b0}};
                stai        <= {STAW{1'b0}};
                sta_mski    <= {STAW{1'b0}};
                sta_chgeni  <= {STCHEW{1'b1}};
                inttypeen   <= {STYW{1'b1}};                
                
                alrmreststate   <= WAIT1;
                end
            WAIT1:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= WAIT2;
                end
            WAIT2:
                begin
                dtvli           <= 1'b0;
                alrmreststate   <= CLEARSTA;
                end
            CLEARSTA:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt;
                styreqi         <= {STYW{1'b0}};
                stai            <= {STAW{1'b0}};
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                stalat          <= ichrdd[STYW+STAW-1:STYW];
                alrmreststate   <= SETSTK;
                end
            SETSTK:
                begin
                dtvli           <= 1'b1;
                segidi          <= alrmrestcnt;
                styreqi         <= {STYW{1'b0}};
                stai            <= stalat;
                sta_mski        <= {STAW{1'b1}};
                sta_chgeni      <= {STCHEW{1'b1}};
                inttypeen       <= {STYW{1'b1}};                
                
                alrmreststate   <= &alrmrestcnt ? IDLE: PREREAD;
                
                alrmrestcnt     <= alrmrestcnt + 1'b1;
                end
            default:
                begin
                alrmreststate   <= IDLE;
                dtvli           <= 1'b0;
                end
        endcase
        
    end


at6rtlnosegintx  #(STYW,STAW,STCHEW,SEGB,SEGNUM,UPW) at6rtlnosegintxi    
    (
     .iclk      (iclk),
     .rst       (rst),
     .ipactive  (ipactive),

     .iupen     (iupen),
     .iupa      (iupa),
     .iupws     (iupws),
     .iuprs     (iuprs),
     .iupdi     (iupdi),
     .ouprdy    (ouprdy),
     .oupdo     (oupdo),
     .oupint    (oupint),

     .idtvl     (dtvli),
     .isegid    (segidi),
    
     .istyreq   (styreqi),
     .ista      (stai),
     .ista_msk  (sta_mski),
     .ista_chgen(sta_chgeni),
     .iinttypeen(inttypeen),


     .ochwe (ochwe),
     .ochwa (ochwa),     
     .ochwrd(ochwrd),    
     .ochre (ochre),
     .ochra (ochra),
     .ichrdd(ichrdd)
     );
        
endmodule