data/full_repos/permissive/524522105/m8330_simple/src/m8330_simple_test.v
1: b'%Error: data/full_repos/permissive/524522105/m8330_simple/src/m8330_simple_test.v:11: syntax error, unexpected return, expecting IDENTIFIER or do or final\n  wire       return;\n             ^~~~~~\n%Error: data/full_repos/permissive/524522105/m8330_simple/src/m8330_simple_test.v:36: syntax error, unexpected return\n                           .return(return),\n                            ^~~~~~\n%Error: data/full_repos/permissive/524522105/m8330_simple/src/m8330_simple_test.v:56: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n  assign led[0] = ~return;\n                   ^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module m8330_simple_test ( input        clock,
                           output [7:0] diag,
                           output [5:0] led );

  reg        power_on = 1'b0;
  wire       start;
  wire       return;
  wire       source;
  wire       strobe;
  wire       inhibit;
  wire       write;
  wire [3:0] timing_pulse;
  wire [3:0] timing_state;
  wire       test_clock;
  wire       osc;
  wire       mode;
  reg  [3:0] counter = 4'b0000;



  Gowin_rPLL std_clock ( .clkin(clock),
                         .clkout(test_clock) );

  m8330_simple timing_gen( .clock(test_clock),
                           .power_on(start),
                           .cycle_ctrl(1'b0),
                           .io_ctrl(1'b0),
                           .return(return),
                           .source(source),
                           .strobe(strobe),
                           .inhibit(inhibit),
                           .write(write),
                           .tp(timing_pulse),
                           .ts(timing_state) );

  generate
    genvar i;

    for(i=0; i<4; i=i+1)
    begin: timing
      assign diag[i*2] = timing_state[i];
      assign diag[i*2+1] = timing_pulse[i];
    end
  endgenerate  
  
  assign start = power_on;

  assign led[0] = ~return;
  assign led[1] = ~source;
  assign led[2] = ~strobe;
  assign led[3] = ~inhibit;
  assign led[4] = ~write;
  assign led[5] = ~power_on;

  always @ (posedge test_clock) begin
    counter <= counter + 1;
    if (counter[3]) begin
        power_on <= 1'b1;
    end
  end
endmodule
module m8330_simple_test ( input        clock,
                           output [7:0] diag,
                           output [5:0] led );


  reg        power_on = 1'b0;
  wire       start;
  wire       return;
  wire       source;
  wire       strobe;
  wire       inhibit;
  wire       write;
  wire [3:0] timing_pulse;
  wire [3:0] timing_state;
  wire       test_clock;
  wire       osc;
  wire       mode;
  reg  [3:0] counter = 4'b0000;



  Gowin_rPLL std_clock ( .clkin(clock),
                         .clkout(test_clock) );

  m8330_simple timing_gen( .clock(test_clock),
                           .power_on(start),
                           .cycle_ctrl(1'b0),
                           .io_ctrl(1'b0),
                           .return(return),
                           .source(source),
                           .strobe(strobe),
                           .inhibit(inhibit),
                           .write(write),
                           .tp(timing_pulse),
                           .ts(timing_state) );

  generate
    genvar i;

    for(i=0; i<4; i=i+1)
    begin: timing
      assign diag[i*2] = timing_state[i];
      assign diag[i*2+1] = timing_pulse[i];
    end
  endgenerate  
  
  assign start = power_on;

  assign led[0] = ~return;
  assign led[1] = ~source;
  assign led[2] = ~strobe;
  assign led[3] = ~inhibit;
  assign led[4] = ~write;
  assign led[5] = ~power_on;

  always @ (posedge test_clock) begin
    counter <= counter + 1;
    if (counter[3]) begin
        power_on <= 1'b1;
    end
  end
endmodule