data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/mod100_counter_TB.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/mod100_counter_TB.v\n%Error: Exiting due to 5 error(s)\n'
module mod100_counter_TB;

reg CLOCK, RESET;
wire sig100;


mod100_counter ctr100(.CLOCK(CLOCK), .RESET(RESET), .sig100(sig100));

always #5 CLOCK = ~CLOCK;


initial begin
	CLOCK = 0;
	RESET = 0;
	
	#100 RESET = 1;
	#50  RESET = 0;
	
	#5000 $finish;
end


initial begin
	$dumpfile("mod100_counter_TB.vcd");
	$dumpvars(0, mod100_counter_TB);
end

endmodule
module mod100_counter_TB;


reg CLOCK, RESET;
wire sig100;


mod100_counter ctr100(.CLOCK(CLOCK), .RESET(RESET), .sig100(sig100));

always #5 CLOCK = ~CLOCK;


initial begin
	CLOCK = 0;
	RESET = 0;
	
	#100 RESET = 1;
	#50  RESET = 0;
	
	#5000 $finish;
end


initial begin
	$dumpfile("mod100_counter_TB.vcd");
	$dumpvars(0, mod100_counter_TB);
end

endmodule