data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v
1: b'%Error: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:31: Cannot find file containing module: \'ALU_32bit\'\nALU_32bit alu_32(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/ALU_32bit\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/ALU_32bit.v\n             data/full_repos/permissive/428158935/sources_1/new,data/full_repos/permissive/428158935/ALU_32bit.sv\n             ALU_32bit\n             ALU_32bit.v\n             ALU_32bit.sv\n             obj_dir/ALU_32bit\n             obj_dir/ALU_32bit.v\n             obj_dir/ALU_32bit.sv\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:42: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'Out\' generates 32 bits.\n                                                                                         : ... In instance ALU_Display\n assign led_cout = Out;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:55: Cannot find file containing module: \'lcd_module\'\nlcd_module lcd_module(\n^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:118: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_value\' generates 32 bits.\n                                                                                          : ... In instance ALU_Display\n   F <= input_value;\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:131: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_value\' generates 32 bits.\n                                                                                          : ... In instance ALU_Display\n   Dir <= input_value;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:144: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_value\' generates 32 bits.\n                                                                                          : ... In instance ALU_Display\n   Bite <= input_value;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:169: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'CI\' generates 1 bits.\n                                                                                          : ... In instance ALU_Display\n   display_value <= CI;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:175: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'F\' generates 3 bits.\n                                                                                          : ... In instance ALU_Display\n   display_value <= F;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:181: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Dir\' generates 2 bits.\n                                                                                          : ... In instance ALU_Display\n   display_value <= Dir;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:187: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Bite\' generates 5 bits.\n                                                                                          : ... In instance ALU_Display\n   display_value <= Bite;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/428158935/sources_1/new/ALU_32bit_Display.v:199: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'CO\' generates 1 bits.\n                                                                                          : ... In instance ALU_Display\n   display_value <= CO;\n                 ^~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module ALU_Display (

input clk,
input resetn, 
input [2:0] input_sel, 
input sw_cin,
output led_cout,
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);

 reg [31:0] In1;
 reg [31:0] In2;
 wire          CI;
 reg [2:0]  F;
 reg [1:0] Dir;
 reg [4:0] Bite;

 wire [31:0]   Out;
 wire          CO;
ALU_32bit alu_32(
    .a        (In1),
    .b        (In2),
    .CI         (CI),
    .F          (F),
    .dir        (Dir),
    .bite       (Bite),
    .S          (Out),
    .CO         (CO)
 );
 assign CI = sw_cin;
 assign led_cout = Out;





 reg display_valid;
 reg [39:0] display_name;
 reg [31:0] display_value;
 wire [5:0] display_number;
 wire input_valid;
 wire [31:0] input_value;

lcd_module lcd_module(
 .clk (clk ),
 .resetn (resetn ),


 .display_valid (display_valid ),
 .display_name (display_name ),
 .display_value (display_value ),
 .display_number (display_number),
 .input_valid (input_valid ),
 .input_value (input_value ),


 .lcd_rst (lcd_rst ),
 .lcd_cs (lcd_cs ),
 .lcd_rs (lcd_rs ),
 .lcd_wr (lcd_wr ),
 .lcd_rd (lcd_rd ),
 .lcd_data_io (lcd_data_io ),
 .lcd_bl_ctr (lcd_bl_ctr ),
 .ct_int (ct_int ),
 .ct_sda (ct_sda ),
 .ct_scl (ct_scl ),
 .ct_rstn (ct_rstn )
);





 always @(posedge clk)
 begin
 if (!resetn)
 begin
   In1 <= 32'd0;
 end
 else if (input_valid && input_sel==3'b000 )
 begin
   In1 <= input_value;
 end
 end


always @(posedge clk)
 begin
 if (!resetn)
 begin
   In2 <= 32'd0;
 end
 else if (input_valid && input_sel==3'b001 )
 begin
   In2 <= input_value;
 end
 end

always @(posedge clk)
 begin
 if (!resetn)
 begin
   F <= 3'd0;
 end
 else if (input_valid && input_sel==3'b010 )
 begin
   F <= input_value;
 end
 end


 always @(posedge clk)
 begin
 if (!resetn)
 begin
   Dir <= 2'd0;
 end
 else if (input_valid && input_sel==3'b011 )
 begin
   Dir <= input_value;
 end
 end


 always @(posedge clk)
 begin
 if (!resetn)
 begin
   Bite <= 5'd0;
 end
 else if (input_valid && input_sel==3'b100 )
 begin
   Bite <= input_value;
 end
 end



 always @(posedge clk)
 begin
 case(display_number)
 6'd1 :
 begin
   display_valid <= 1'b1;
   display_name <= "OP1";
   display_value <= In1;
 end
 6'd2 :
 begin
   display_valid <= 1'b1;
   display_name <= "OP2";
   display_value <= In2;
 end
 6'd3 :
 begin
   display_valid <= 1'b1;
   display_name <= "CI";
   display_value <= CI;
 end
 6'd4 :
 begin
   display_valid <= 1'b1;
   display_name <= "F";
   display_value <= F;
 end
6'd5 :
 begin
   display_valid <= 1'b1;
   display_name <= "DIR";
   display_value <= Dir;
 end
 6'd6 :
 begin
   display_valid <= 1'b1;
   display_name <= "BITE";
   display_value <= Bite;
 end
 6'd7 :
 begin
   display_valid <= 1'b1;
   display_name <= "OUT";
   display_value <= Out;
 end
 6'd8 :
 begin
   display_valid <= 1'b1;
   display_name <= "CO";
   display_value <= CO;
 end
 default :
 begin
   display_valid <= 1'b0;
   display_name <= 40'd0;
   display_value <= 32'd0;
end
endcase
end


endmodule
module ALU_Display (

input clk,
input resetn, 
input [2:0] input_sel, 
input sw_cin,
output led_cout,
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);


 reg [31:0] In1;
 reg [31:0] In2;
 wire          CI;
 reg [2:0]  F;
 reg [1:0] Dir;
 reg [4:0] Bite;

 wire [31:0]   Out;
 wire          CO;
ALU_32bit alu_32(
    .a        (In1),
    .b        (In2),
    .CI         (CI),
    .F          (F),
    .dir        (Dir),
    .bite       (Bite),
    .S          (Out),
    .CO         (CO)
 );
 assign CI = sw_cin;
 assign led_cout = Out;





 reg display_valid;
 reg [39:0] display_name;
 reg [31:0] display_value;
 wire [5:0] display_number;
 wire input_valid;
 wire [31:0] input_value;

lcd_module lcd_module(
 .clk (clk ),
 .resetn (resetn ),


 .display_valid (display_valid ),
 .display_name (display_name ),
 .display_value (display_value ),
 .display_number (display_number),
 .input_valid (input_valid ),
 .input_value (input_value ),


 .lcd_rst (lcd_rst ),
 .lcd_cs (lcd_cs ),
 .lcd_rs (lcd_rs ),
 .lcd_wr (lcd_wr ),
 .lcd_rd (lcd_rd ),
 .lcd_data_io (lcd_data_io ),
 .lcd_bl_ctr (lcd_bl_ctr ),
 .ct_int (ct_int ),
 .ct_sda (ct_sda ),
 .ct_scl (ct_scl ),
 .ct_rstn (ct_rstn )
);





 always @(posedge clk)
 begin
 if (!resetn)
 begin
   In1 <= 32'd0;
 end
 else if (input_valid && input_sel==3'b000 )
 begin
   In1 <= input_value;
 end
 end


always @(posedge clk)
 begin
 if (!resetn)
 begin
   In2 <= 32'd0;
 end
 else if (input_valid && input_sel==3'b001 )
 begin
   In2 <= input_value;
 end
 end

always @(posedge clk)
 begin
 if (!resetn)
 begin
   F <= 3'd0;
 end
 else if (input_valid && input_sel==3'b010 )
 begin
   F <= input_value;
 end
 end


 always @(posedge clk)
 begin
 if (!resetn)
 begin
   Dir <= 2'd0;
 end
 else if (input_valid && input_sel==3'b011 )
 begin
   Dir <= input_value;
 end
 end


 always @(posedge clk)
 begin
 if (!resetn)
 begin
   Bite <= 5'd0;
 end
 else if (input_valid && input_sel==3'b100 )
 begin
   Bite <= input_value;
 end
 end



 always @(posedge clk)
 begin
 case(display_number)
 6'd1 :
 begin
   display_valid <= 1'b1;
   display_name <= "OP1";
   display_value <= In1;
 end
 6'd2 :
 begin
   display_valid <= 1'b1;
   display_name <= "OP2";
   display_value <= In2;
 end
 6'd3 :
 begin
   display_valid <= 1'b1;
   display_name <= "CI";
   display_value <= CI;
 end
 6'd4 :
 begin
   display_valid <= 1'b1;
   display_name <= "F";
   display_value <= F;
 end
6'd5 :
 begin
   display_valid <= 1'b1;
   display_name <= "DIR";
   display_value <= Dir;
 end
 6'd6 :
 begin
   display_valid <= 1'b1;
   display_name <= "BITE";
   display_value <= Bite;
 end
 6'd7 :
 begin
   display_valid <= 1'b1;
   display_name <= "OUT";
   display_value <= Out;
 end
 6'd8 :
 begin
   display_valid <= 1'b1;
   display_name <= "CO";
   display_value <= CO;
 end
 default :
 begin
   display_valid <= 1'b0;
   display_name <= 40'd0;
   display_value <= 32'd0;
end
endcase
end


endmodule