data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #0   Sb=1\'b1; Rb=1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b1; Rb=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b0; Rb=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b1; Rb=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b0; Rb=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b1; Rb=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10  Sb=1\'b1; Rb=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:22: Unsupported: Ignoring delay on this delayed statement.\n    initial #70 $finish;\n            ^\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:26: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("sbrblatch.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_SbRb_Latch_gatelevel.v:27: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars;\n            ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Lab3_SbRb_Latch_gatelevel();

    wire Q, NQ;
    reg  Sb, Rb;

    Lab3_SbRb_Latch_gatelevel M0(Q, NQ, Sb, Rb);

    initial
    begin

        #0   Sb=1'b1; Rb=1'b0;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b0; Rb=1'b1;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b0; Rb=1'b0;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b1; Rb=1'b0;

    end

    initial #70 $finish;

    initial
        begin
            $dumpfile("sbrblatch.vcd");
            $dumpvars;
        end

endmodule
module t_Lab3_SbRb_Latch_gatelevel();


    wire Q, NQ;
    reg  Sb, Rb;

    Lab3_SbRb_Latch_gatelevel M0(Q, NQ, Sb, Rb);

    initial
    begin

        #0   Sb=1'b1; Rb=1'b0;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b0; Rb=1'b1;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b0; Rb=1'b0;
        #10  Sb=1'b1; Rb=1'b1;
        #10  Sb=1'b1; Rb=1'b0;

    end

    initial #70 $finish;

    initial
        begin
            $dumpfile("sbrblatch.vcd");
            $dumpvars;
        end

endmodule