data/full_repos/permissive/518325211/pll/DSM_lib/OpenLane/src/Adder.v
data/verilator_xmls/9702929d-98bf-469e-b1a2-4312a6c8e456.xml
module adder(in_1,in_2,out);

	input [4:0] in_1,in_2;
	output [5:0] out;

	assign out = in_1 + in_2;

endmodule
module adder(in_1,in_2,out);


	input [4:0] in_1,in_2;
	output [5:0] out;

	assign out = in_1 + in_2;

endmodule