data/full_repos/permissive/440263190/wrapper.v
1: b"%Error: data/full_repos/permissive/440263190/wrapper.v:78: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  wire [`MPRJ_IO_PADS-1:0] io_in,   \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:79: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_out,  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:80: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_oeb,  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:101: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:102: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:161: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:162: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/440263190/wrapper.v:172: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign buf_io_oeb[`MPRJ_IO_PADS-1:13+1] = 0;\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module wrapped_silife(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire  [3:0]   wbs_sel_i,
    input wire  [31:0]  wbs_dat_i,
    input wire  [31:0]  wbs_adr_i,
    output wire         wbs_ack_o,
    output wire [31:0]  wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    output wire         rambus_wb_clk_o,
    output wire         rambus_wb_rst_o,
    output wire         rambus_wb_stb_o,
    output wire         rambus_wb_cyc_o,
    output wire         rambus_wb_we_o,
    output wire [3:0]   rambus_wb_sel_o,
    output wire [31:0]  rambus_wb_dat_o,
    output wire [9:0]   rambus_wb_adr_o,
    input  wire         rambus_wb_ack_i,
    input  wire [31:0]  rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);


    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif



    wire silife_busy;
    assign buf_io_oeb[`MPRJ_IO_PADS-1:`PIN_SYNC_BUSY+1] = 0;
    assign buf_io_oeb[`PIN_SYNC_BUSY] = silife_busy;
    assign buf_io_oeb[`PIN_SYNC_BUSY-1:0] = 0;
    assign buf_io_out[`PIN_SYNC_BUSY] = 0;




    silife #(.WIDTH(32), .HEIGHT(32)) silife1 (
        .reset(la1_data_in[0]),
        .clk(wb_clk_i),

        .spi_cs(buf_io_out[`PIN_MAX7219_CS]),
        .spi_sck(buf_io_out[`PIN_MAX7219_SCK]),
        .spi_mosi(buf_io_out[`PIN_MAX7219_MOSI]),


        .i_sync_clk$syn(io_in[`PIN_SYNC_CLK]),
        .i_sync_active$syn(io_in[`PIN_SYNC_ACTIVE]),
        .i_sync_in_n$syn(io_in[`PIN_SYNC_N_IN]),
        .i_sync_in_e$syn(io_in[`PIN_SYNC_E_IN]),
        .i_sync_in_s$syn(io_in[`PIN_SYNC_S_IN]),
        .i_sync_in_w$syn(io_in[`PIN_SYNC_W_IN]),
        .o_busy(silife_busy),
        .o_sync_out_n$syn(buf_io_out[`PIN_SYNC_N_OUT]),
        .o_sync_out_e$syn(buf_io_out[`PIN_SYNC_E_OUT]),
        .o_sync_out_s$syn(buf_io_out[`PIN_SYNC_S_OUT]),
        .o_sync_out_w$syn(buf_io_out[`PIN_SYNC_W_OUT]),


        .i_load_cs$load(io_in[`PIN_LOADER_CS]),
        .i_load_clk$load(io_in[`PIN_LOADER_CLK]),
        .i_load_data$load(io_in[`PIN_LOADER_DIN]),
        .o_load_data$load(buf_io_out[`PIN_LOADER_DOUT]),


        .i_wb_cyc(wbs_stb_i),
        .i_wb_stb(wbs_stb_i),
        .i_wb_we(wbs_we_i),
        .i_wb_addr(wbs_adr_i),
        .i_wb_data(wbs_dat_i),
        .o_wb_ack(buf_wbs_ack_o),
        .o_wb_data(buf_wbs_dat_o)
    );

endmodule
module wrapped_silife(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire  [3:0]   wbs_sel_i,
    input wire  [31:0]  wbs_dat_i,
    input wire  [31:0]  wbs_adr_i,
    output wire         wbs_ack_o,
    output wire [31:0]  wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    output wire         rambus_wb_clk_o,
    output wire         rambus_wb_rst_o,
    output wire         rambus_wb_stb_o,
    output wire         rambus_wb_cyc_o,
    output wire         rambus_wb_we_o,
    output wire [3:0]   rambus_wb_sel_o,
    output wire [31:0]  rambus_wb_dat_o,
    output wire [9:0]   rambus_wb_adr_o,
    input  wire         rambus_wb_ack_i,
    input  wire [31:0]  rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);



    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif



    wire silife_busy;
    assign buf_io_oeb[`MPRJ_IO_PADS-1:`PIN_SYNC_BUSY+1] = 0;
    assign buf_io_oeb[`PIN_SYNC_BUSY] = silife_busy;
    assign buf_io_oeb[`PIN_SYNC_BUSY-1:0] = 0;
    assign buf_io_out[`PIN_SYNC_BUSY] = 0;




    silife #(.WIDTH(32), .HEIGHT(32)) silife1 (
        .reset(la1_data_in[0]),
        .clk(wb_clk_i),

        .spi_cs(buf_io_out[`PIN_MAX7219_CS]),
        .spi_sck(buf_io_out[`PIN_MAX7219_SCK]),
        .spi_mosi(buf_io_out[`PIN_MAX7219_MOSI]),


        .i_sync_clk$syn(io_in[`PIN_SYNC_CLK]),
        .i_sync_active$syn(io_in[`PIN_SYNC_ACTIVE]),
        .i_sync_in_n$syn(io_in[`PIN_SYNC_N_IN]),
        .i_sync_in_e$syn(io_in[`PIN_SYNC_E_IN]),
        .i_sync_in_s$syn(io_in[`PIN_SYNC_S_IN]),
        .i_sync_in_w$syn(io_in[`PIN_SYNC_W_IN]),
        .o_busy(silife_busy),
        .o_sync_out_n$syn(buf_io_out[`PIN_SYNC_N_OUT]),
        .o_sync_out_e$syn(buf_io_out[`PIN_SYNC_E_OUT]),
        .o_sync_out_s$syn(buf_io_out[`PIN_SYNC_S_OUT]),
        .o_sync_out_w$syn(buf_io_out[`PIN_SYNC_W_OUT]),


        .i_load_cs$load(io_in[`PIN_LOADER_CS]),
        .i_load_clk$load(io_in[`PIN_LOADER_CLK]),
        .i_load_data$load(io_in[`PIN_LOADER_DIN]),
        .o_load_data$load(buf_io_out[`PIN_LOADER_DOUT]),


        .i_wb_cyc(wbs_stb_i),
        .i_wb_stb(wbs_stb_i),
        .i_wb_we(wbs_we_i),
        .i_wb_addr(wbs_adr_i),
        .i_wb_data(wbs_dat_i),
        .o_wb_ack(buf_wbs_ack_o),
        .o_wb_data(buf_wbs_dat_o)
    );

endmodule