data/full_repos/permissive/500596939/rtl/ls30rot_decoder.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/ls30rot_decoder.sv:58: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'data_changed\' generates 8 bits.\n                                                                              : ... In instance ls30rot_decoder\n    if(data_changed && !wait_data) begin\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ls30rot_decoder (
  input wire clk,
  input wire wait_data,
  input wire [3:0] curr_data,
  input wire [3:0] last_data,
  output logic [3:0] pos
);
	logic [3:0] r_curr_data;
	logic [3:0] r_last_data;
	logic signed [1:0] delta_value;
	logic [7:0] data_changed;
	
	logic [3:0] r_pos = 4'd11;
	assign data_changed = {r_last_data,r_curr_data} ^ {last_data,curr_data};
	

	always_comb begin
		case ({last_data,curr_data})
		8'b1001_0001: delta_value = 1;
		8'b0011_0010: delta_value = 1;
		8'b0110_0100: delta_value = 1;
		8'b1100_1000: delta_value = 1;
		8'b1001_1000: delta_value = -1;
		8'b1100_0100: delta_value = -1;
		8'b0110_0010: delta_value = -1;
		8'b0011_0001: delta_value = -1;
		default:      delta_value = 0;
		endcase
	end
  
  always_ff @(posedge clk) begin
	r_curr_data <= curr_data;
	r_last_data <= last_data;
    if(data_changed && !wait_data) begin
		if (r_pos == 4'd11) begin
		if(delta_value > 0) r_pos = 4'd0;
		else if(delta_value < 0) r_pos = r_pos - 4'd1;
		end
		else if (r_pos == 4'd0) begin
		if(delta_value < 0) r_pos = 4'd11;
		else if(delta_value > 0) r_pos = r_pos + 4'd1;
		end
		else begin
		if(delta_value < 0) r_pos = r_pos - 4'd1;
		else if(delta_value > 0) r_pos = r_pos + 4'd1;
		end
	end
  end
  
  assign pos = r_pos;
endmodule
module ls30rot_decoder (
  input wire clk,
  input wire wait_data,
  input wire [3:0] curr_data,
  input wire [3:0] last_data,
  output logic [3:0] pos
);

	logic [3:0] r_curr_data;
	logic [3:0] r_last_data;
	logic signed [1:0] delta_value;
	logic [7:0] data_changed;
	
	logic [3:0] r_pos = 4'd11;
	assign data_changed = {r_last_data,r_curr_data} ^ {last_data,curr_data};
	

	always_comb begin
		case ({last_data,curr_data})
		8'b1001_0001: delta_value = 1;
		8'b0011_0010: delta_value = 1;
		8'b0110_0100: delta_value = 1;
		8'b1100_1000: delta_value = 1;
		8'b1001_1000: delta_value = -1;
		8'b1100_0100: delta_value = -1;
		8'b0110_0010: delta_value = -1;
		8'b0011_0001: delta_value = -1;
		default:      delta_value = 0;
		endcase
	end
  
  always_ff @(posedge clk) begin
	r_curr_data <= curr_data;
	r_last_data <= last_data;
    if(data_changed && !wait_data) begin
		if (r_pos == 4'd11) begin
		if(delta_value > 0) r_pos = 4'd0;
		else if(delta_value < 0) r_pos = r_pos - 4'd1;
		end
		else if (r_pos == 4'd0) begin
		if(delta_value < 0) r_pos = 4'd11;
		else if(delta_value > 0) r_pos = r_pos + 4'd1;
		end
		else begin
		if(delta_value < 0) r_pos = r_pos - 4'd1;
		else if(delta_value > 0) r_pos = r_pos + 4'd1;
		end
	end
  end
  
  assign pos = r_pos;
endmodule