data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_sift_feat.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_sift_feat.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_sift_feat.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk_sys=~clk_sys;\n  ^\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_sift_feat.v:41: Cannot find file containing module: \'sift_feat\'\n sift_feat uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/sift_feat\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/sift_feat.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/sift_feat.sv\n             sift_feat\n             sift_feat.v\n             sift_feat.sv\n             obj_dir/sift_feat\n             obj_dir/sift_feat.v\n             obj_dir/sift_feat.sv\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_sift_feat.v:80: Bit extraction of array[262144:0] requires 19 bit index, not 18 bits.\n                                                                                                      : ... In instance tf_sift_feat\n            din <= data_img[addr];\n                           ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_sift_feat;


	reg clk_sys;
	reg rst_sys;
	reg [7:0] din;


	wire [7:0] max;
	wire [7:0] min;
	wire dout_kp;
	wire [7:0] mag;
	wire [5:0] dir;
	wire out_en;
    wire complete1;
    wire complete2;
	reg     [7:0]   data_img[262144:0];

	wire [17:0] addr;



	sift_feat uut (
		.clk(clk_sys), 
        .clk_90(clk_sys), 
		.rst(rst_sys), 
		.din(din),
		.addr(addr),

		.max(max), 
		.min(min), 
		.dout_kp(dout_kp), 
		
		.mag(mag), 
		.dir(dir), 
		.out_en(out_en),
        .complete1(complete1),
        .complete2(complete2)
	);

	initial begin

		clk_sys = 0;
		rst_sys = 0;
		din = 0;
		$readmemh("ram_image.txt", data_img);


		#100;
		rst_sys=1;


	end

	always
		#10 clk_sys=~clk_sys;
    
    always@(posedge clk_sys or negedge rst_sys)
        if(rst_sys == 1'b0)
            din <= 8'd0;
        else 
            din <= data_img[addr];
      
endmodule
module tf_sift_feat;



	reg clk_sys;
	reg rst_sys;
	reg [7:0] din;


	wire [7:0] max;
	wire [7:0] min;
	wire dout_kp;
	wire [7:0] mag;
	wire [5:0] dir;
	wire out_en;
    wire complete1;
    wire complete2;
	reg     [7:0]   data_img[262144:0];

	wire [17:0] addr;



	sift_feat uut (
		.clk(clk_sys), 
        .clk_90(clk_sys), 
		.rst(rst_sys), 
		.din(din),
		.addr(addr),

		.max(max), 
		.min(min), 
		.dout_kp(dout_kp), 
		
		.mag(mag), 
		.dir(dir), 
		.out_en(out_en),
        .complete1(complete1),
        .complete2(complete2)
	);

	initial begin

		clk_sys = 0;
		rst_sys = 0;
		din = 0;
		$readmemh("ram_image.txt", data_img);


		#100;
		rst_sys=1;


	end

	always
		#10 clk_sys=~clk_sys;
    
    always@(posedge clk_sys or negedge rst_sys)
        if(rst_sys == 1'b0)
            din <= 8'd0;
        else 
            din <= data_img[addr];
      
endmodule