data/full_repos/permissive/508331744/verilog/rtl/RCA.v
1: b"%Error: data/full_repos/permissive/508331744/verilog/rtl/RCA.v:16: Cannot find file containing module: 'FA'\n          FA full_adder(x[c],y[c],carries[c],carries[c+1],sum[c]);\n          ^~\n        ... Looked in:\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/FA\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/FA.v\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/FA.sv\n             FA\n             FA.v\n             FA.sv\n             obj_dir/FA\n             obj_dir/FA.v\n             obj_dir/FA.sv\n%Error: Exiting due to 1 error(s)\n"
module RCA #(parameter SIZE = 4)(
 
    input [SIZE-1:0] x,y,
    input ci,
    output cout,
    output [SIZE-1:0] sum
);
(* dont_touch="true" *)  wire [SIZE:0] carries;
assign carries[0] = ci;
assign cout = carries[SIZE];

genvar c;
generate 
    for( c=0; c<SIZE; c=c+1)
        begin: loop
          FA full_adder(x[c],y[c],carries[c],carries[c+1],sum[c]);
        end 
endgenerate
endmodule
module RCA #(parameter SIZE = 4)(
 
    input [SIZE-1:0] x,y,
    input ci,
    output cout,
    output [SIZE-1:0] sum
);

(* dont_touch="true" *)  wire [SIZE:0] carries;
assign carries[0] = ci;
assign cout = carries[SIZE];

genvar c;
generate 
    for( c=0; c<SIZE; c=c+1)
        begin: loop
          FA full_adder(x[c],y[c],carries[c],carries[c+1],sum[c]);
        end 
endgenerate
endmodule