data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:36: Operator EQ expects 2 bits on the RHS, but RHS\'s VARREF \'STATE_WAIT\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\nassign    ack_o = (state == STATE_WAIT) && (count == 4\'d9);\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:37: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                : ... In instance Data_Memory\nassign    addr = addr_i>>5;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:42: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\n        state <= STATE_IDLE;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:49: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_WAIT\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\n                    state <= STATE_WAIT;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:55: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\n                    state <= STATE_IDLE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:46: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'STATE_IDLE\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\n        case(state) \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:46: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'STATE_WAIT\' generates 1 bits.\n                                                                                : ... In instance Data_Memory\n        case(state) \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:70: Bit extraction of array[511:0] requires 9 bit index, not 27 bits.\n                                                                                : ... In instance Data_Memory\n            memory[addr] <= data_i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/419273451/lab2/codes/Data_Memory.v:74: Bit extraction of array[511:0] requires 9 bit index, not 27 bits.\n                                                                                : ... In instance Data_Memory\n            data = memory[addr];\n                         ^\n%Error: Exiting due to 9 warning(s)\n'
module Data_Memory
(
    clk_i,
    rst_i,
    addr_i,
    data_i,
    enable_i,
    write_i,
    ack_o,
    data_o
);


input               clk_i;
input               rst_i;
input    [31:0]     addr_i;
input    [255:0]    data_i;
input               enable_i;
input               write_i;
output              ack_o;
output   [255:0]    data_o;



reg      [255:0]    memory[0:511];
reg      [3:0]      count;

reg      [255:0]    data;
wire     [26:0]     addr;

parameter STATE_IDLE            = 1'h0,
          STATE_WAIT            = 1'h1;            

reg        [1:0]        state;

assign    ack_o = (state == STATE_WAIT) && (count == 4'd9);
assign    addr = addr_i>>5;
assign    data_o = data;

always@(posedge clk_i or posedge rst_i) begin
    if(rst_i) begin
        state <= STATE_IDLE;
        count <= 4'd0;
    end
    else begin
        case(state) 
            STATE_IDLE: begin
                if(enable_i) begin
                    state <= STATE_WAIT;
                    count <= count + 1;
                end
            end
            STATE_WAIT: begin
                if(count == 4'd9) begin    
                    state <= STATE_IDLE;
                    count <= 0;
                end
                else begin
                    count <= count + 1;
                end
            end
        endcase    
    end
end


always@(posedge clk_i) begin
    if (ack_o) begin
        if (write_i) begin
            memory[addr] <= data_i;
            data <= data_i;
        end
        else begin
            data = memory[addr];
        end
    end
end

endmodule
module Data_Memory
(
    clk_i,
    rst_i,
    addr_i,
    data_i,
    enable_i,
    write_i,
    ack_o,
    data_o
);



input               clk_i;
input               rst_i;
input    [31:0]     addr_i;
input    [255:0]    data_i;
input               enable_i;
input               write_i;
output              ack_o;
output   [255:0]    data_o;



reg      [255:0]    memory[0:511];
reg      [3:0]      count;

reg      [255:0]    data;
wire     [26:0]     addr;

parameter STATE_IDLE            = 1'h0,
          STATE_WAIT            = 1'h1;            

reg        [1:0]        state;

assign    ack_o = (state == STATE_WAIT) && (count == 4'd9);
assign    addr = addr_i>>5;
assign    data_o = data;

always@(posedge clk_i or posedge rst_i) begin
    if(rst_i) begin
        state <= STATE_IDLE;
        count <= 4'd0;
    end
    else begin
        case(state) 
            STATE_IDLE: begin
                if(enable_i) begin
                    state <= STATE_WAIT;
                    count <= count + 1;
                end
            end
            STATE_WAIT: begin
                if(count == 4'd9) begin    
                    state <= STATE_IDLE;
                    count <= 0;
                end
                else begin
                    count <= count + 1;
                end
            end
        endcase    
    end
end


always@(posedge clk_i) begin
    if (ack_o) begin
        if (write_i) begin
            memory[addr] <= data_i;
            data <= data_i;
        end
        else begin
            data = memory[addr];
        end
    end
end

endmodule