data/full_repos/permissive/486216880/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486216880/main.v:23: Unsupported: Ignoring delay on this delayed statement.\n  always begin #5 clk = ~clk; end\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486216880/main.v:33: Cannot find file containing module: \'core\'\n  core #(.RAM_DEPTH(RAM_DEPTH)) \n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core.v\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/486216880/main.v:45: Cannot find file containing module: \'ROM\'\n  ROM inst_rom(\n  ^~~\n%Error: data/full_repos/permissive/486216880/main.v:51: Cannot find file containing module: \'RAM\'\n  RAM #(.RAM_DEPTH(RAM_DEPTH))\n  ^~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function integer clogb2;
input integer depth;
	for (clogb2=0; depth>0; clogb2=clogb2+1)
		depth = depth >> 1;
endfunction
function integer clogb2;

input integer depth;
	for (clogb2=0; depth>0; clogb2=clogb2+1)
		depth = depth >> 1;
endfunction