data/full_repos/permissive/412284801/adders/halfsubtractor/d_halfsub.v
data/verilator_xmls/8962736d-8920-4923-930f-601d4ae696de.xml
module d_halfsub(a,b,d,bo);
    input a,b;
    output d,bo;
    assign d = a^b,bo=(~a)&b;
endmodule
module d_halfsub(a,b,d,bo);

    input a,b;
    output d,bo;
    assign d = a^b,bo=(~a)&b;
endmodule