data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v:28: Little bit endian vector: MSB < LSB of bit range: -1:0\n    (input [bits_in-1:0] in,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v:29: Little bit endian vector: MSB < LSB of bit range: -1:0\n     output [bits_out-1:0] out);\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [bits_out-1:0]     rounded;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v:33: Cannot find file containing module: \'round\'\n   round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out))\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/round\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/round.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/round.sv\n             round\n             round.v\n             round.sv\n             obj_dir/round\n             obj_dir/round.v\n             obj_dir/round.sv\n%Error: Internal Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_and_round.v:40: ../V3Width.cpp:3809: Under node REPLICATE has no expected width?? Missing Visitor func?\n                                                                                                   : ... In instance clip_and_round\n      (in[bits_in-1] ? {1\'b1,{(bits_out-1){1\'b0}}} : {1\'b0,{(bits_out-1){1\'b1}}}) :\n                       ^\n'
module clip_and_round
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter clip_bits=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out);

   wire [bits_out-1:0] 	   rounded;
   
   round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out))
     round (.in(in[bits_in-clip_bits-1:0]),.out(rounded));
   
   wire 		   overflow = |in[bits_in-1:bits_in-clip_bits-1] 
			   & ~(&in[bits_in-1:bits_in-clip_bits-1]);
   
   assign 		   out = overflow ? 
			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
			   rounded;
   
endmodule
module clip_and_round
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter clip_bits=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out);


   wire [bits_out-1:0] 	   rounded;
   
   round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out))
     round (.in(in[bits_in-clip_bits-1:0]),.out(rounded));
   
   wire 		   overflow = |in[bits_in-1:bits_in-clip_bits-1] 
			   & ~(&in[bits_in-1:bits_in-clip_bits-1]);
   
   assign 		   out = overflow ? 
			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
			   rounded;
   
endmodule