data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v
1: b'%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    csr_mepc_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus]    csr_mepc_i,\n                   ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    csr_mtvec_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus]    new_pc,\n ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:21: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    new_pc,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:28: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:31: Define or directive not defined: \'`ZeroWord\'\n   new_pc = `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:32: Define or directive not defined: \'`ZeroWord\'\n  end else if(excepttype_i != `ZeroWord) begin\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:41: Define or directive not defined: \'`Stop\'\n  end else if(stallreq_from_mem == `Stop) begin\n                                   ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:44: Define or directive not defined: \'`Stop\'\n  end else if(stallreq_from_ex == `Stop) begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:47: Define or directive not defined: \'`Stop\'\n  end else if(stallreq_from_id == `Stop) begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:50: Define or directive not defined: \'`Stop\'\n  end else if(stallreq_from_if == `Stop) begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/ctrl.v:56: Define or directive not defined: \'`ZeroWord\'\n   new_pc = `ZeroWord;\n            ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module ctrl(

	input wire										rst,
	
	input wire							stallreq_from_if,
	input wire							stallreq_from_mem,

	input wire                   stallreq_from_id,


	input wire                   stallreq_from_ex,
	
	input wire[31:0]					excepttype_i,
	input wire[`RegBus]				csr_mepc_i,
	input wire[`RegBus]				csr_mtvec_i,
	
	output reg[5:0]              stall,
	
	output reg[`RegBus]				new_pc,
	output reg							flush
	
);


	always @ (*) begin
		if(rst == `RstEnable) begin
			stall = 6'b000000;
			flush = 1'b0;
			new_pc = `ZeroWord;
		end else if(excepttype_i != `ZeroWord) begin
			flush = 1'b1;
			stall = 6'b000000;
			
			if(excepttype_i == 32'h0000000a) begin
				new_pc = csr_mepc_i;
			end else begin
				new_pc = csr_mtvec_i;
			end
		end else if(stallreq_from_mem == `Stop) begin
			stall = 6'b011111;
			flush = 1'b0;
		end else if(stallreq_from_ex == `Stop) begin
			stall = 6'b001111;
			flush = 1'b0;
		end else if(stallreq_from_id == `Stop) begin
			stall = 6'b000111;		
			flush = 1'b0;
		end else if(stallreq_from_if == `Stop) begin
			stall = 6'b000011;
			flush = 1'b0;
		end else begin
			stall = 6'b000000;
			flush = 1'b0;
			new_pc = `ZeroWord;
		end
	end
			

endmodule
module ctrl(

	input wire										rst,
	
	input wire							stallreq_from_if,
	input wire							stallreq_from_mem,

	input wire                   stallreq_from_id,


	input wire                   stallreq_from_ex,
	
	input wire[31:0]					excepttype_i,
	input wire[`RegBus]				csr_mepc_i,
	input wire[`RegBus]				csr_mtvec_i,
	
	output reg[5:0]              stall,
	
	output reg[`RegBus]				new_pc,
	output reg							flush
	
);



	always @ (*) begin
		if(rst == `RstEnable) begin
			stall = 6'b000000;
			flush = 1'b0;
			new_pc = `ZeroWord;
		end else if(excepttype_i != `ZeroWord) begin
			flush = 1'b1;
			stall = 6'b000000;
			
			if(excepttype_i == 32'h0000000a) begin
				new_pc = csr_mepc_i;
			end else begin
				new_pc = csr_mtvec_i;
			end
		end else if(stallreq_from_mem == `Stop) begin
			stall = 6'b011111;
			flush = 1'b0;
		end else if(stallreq_from_ex == `Stop) begin
			stall = 6'b001111;
			flush = 1'b0;
		end else if(stallreq_from_id == `Stop) begin
			stall = 6'b000111;		
			flush = 1'b0;
		end else if(stallreq_from_if == `Stop) begin
			stall = 6'b000011;
			flush = 1'b0;
		end else begin
			stall = 6'b000000;
			flush = 1'b0;
			new_pc = `ZeroWord;
		end
	end
			

endmodule