data/full_repos/permissive/443770883/lab3/testBench4to1.v
1: b'%Error: data/full_repos/permissive/443770883/lab3/testBench4to1.v:8: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dump3.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab3/testBench4to1.v:9: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0, TB);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/testBench4to1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/testBench4to1.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/testBench4to1.v:23: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB;
reg [0:3]ii;
reg s0;
reg s1;
wire yy;
initial
begin
$dumpfile("dump3.vcd");
$dumpvars(0, TB);
end
mux4 newMUX(.i(ii), .j0(s0),.j1(s1),.o(yy));
initial
begin
ii = 4'b0001;
s0=1'b0;
s1=1'b0;
#5
ii = 4'b1000;
#5
ii = 4'b0001;
s0=1'b1;
s1=1'b1;
#5
ii = 4'b0000;
s0=1'b1;
s1=1'b0;
end
endmodule
module TB;

reg [0:3]ii;
reg s0;
reg s1;
wire yy;
initial
begin
$dumpfile("dump3.vcd");
$dumpvars(0, TB);
end
mux4 newMUX(.i(ii), .j0(s0),.j1(s1),.o(yy));
initial
begin
ii = 4'b0001;
s0=1'b0;
s1=1'b0;
#5
ii = 4'b1000;
#5
ii = 4'b0001;
s0=1'b1;
s1=1'b1;
#5
ii = 4'b0000;
s0=1'b1;
s1=1'b0;
end
endmodule