data/full_repos/permissive/486367830/hdl/unsigned_mult.v
data/verilator_xmls/24b27094-417d-462e-a844-574ed9df4960.xml
module unsigned_mult #(
parameter DWIDTH = 8
)(

input  [  DWIDTH -1:0] op1    ,
input  [  DWIDTH -1:0] op2    ,
output [2*DWIDTH -1:0] result

); 

assign result = op1 * op2;

endmodule
module unsigned_mult #(
parameter DWIDTH = 8
)(

input  [  DWIDTH -1:0] op1    ,
input  [  DWIDTH -1:0] op2    ,
output [2*DWIDTH -1:0] result

);
 

assign result = op1 * op2;

endmodule