data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #20 opcode = 6\'b000100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #20 opcode = 6\'b000101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20 opcode = 6\'b000111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #20 opcode = 6\'b000110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #20 opcode = 6\'b000001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #120 $finish;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/ControlUnit_TEST.v:37: Cannot find file containing module: \'ControlUnit\'\n ControlUnit uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ControlUnit\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ControlUnit.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ControlUnit_TEST;

	 reg [5:0] opcode; 
	 wire RegDst;
    wire ALUSrc;
    wire MemtoReg;
    wire RegWrite;
    wire MemRead;
    wire MemWrite;
    wire Branch;
    wire [1:0] ALUOp;

	ControlUnit uut (
	 .opcode(opcode),
	 .RegDst(RegDst),
    .ALUSrc(ALUSrc),
    .MemtoReg(MemtoReg),
    .RegWrite(RegWrite),
    .MemRead(MemRead),
    .MemWrite(MemWrite),
    .Branch(Branch),
    .ALUOp(ALUOp)
	);

	initial begin

		opcode = 0;

		#20 opcode = 6'b000100;
		#20 opcode = 6'b000101;
		#20 opcode = 6'b000111;
		#20 opcode = 6'b000110;
		#20 opcode = 6'b000001;
      
		#120 $finish;


	end
      
endmodule
module ControlUnit_TEST;


	 reg [5:0] opcode; 
	 wire RegDst;
    wire ALUSrc;
    wire MemtoReg;
    wire RegWrite;
    wire MemRead;
    wire MemWrite;
    wire Branch;
    wire [1:0] ALUOp;

	ControlUnit uut (
	 .opcode(opcode),
	 .RegDst(RegDst),
    .ALUSrc(ALUSrc),
    .MemtoReg(MemtoReg),
    .RegWrite(RegWrite),
    .MemRead(MemRead),
    .MemWrite(MemWrite),
    .Branch(Branch),
    .ALUOp(ALUOp)
	);

	initial begin

		opcode = 0;

		#20 opcode = 6'b000100;
		#20 opcode = 6'b000101;
		#20 opcode = 6'b000111;
		#20 opcode = 6'b000110;
		#20 opcode = 6'b000001;
      
		#120 $finish;


	end
      
endmodule