data/full_repos/permissive/481044442/BDCDrv/uart_rx.v
data/verilator_xmls/ebbf1a86-b988-48b6-917c-0e9d3a234d3b.xml
module uart_rx(clk,reset,serial_in,parallel_out,done,busy,err);
input clk;
input reset;
input serial_in;

output reg [7:0] parallel_out;
output reg done;
output reg busy;
output reg err;


parameter STATE_IDLE=2'b00;
parameter STATE_DATA_BITS=2'b01;
parameter STATE_STOP_BIT=2'b10;
reg [1:0] my_fsm;


wire negedge_rxd;



reg [1:0] shift_serial_in;

assign negedge_rxd=shift_serial_in[1]&(~shift_serial_in[0]);


reg [7:0] received_data;

reg [3:0] clock_count;


reg [2:0] bitIndex;

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				parallel_out<=8'd0;
				received_data<=8'd0;
				bitIndex<=3'd0;
				shift_serial_in<=2'd0;
				clock_count<=4'd0;
				done<=1'b0;
				busy<=1'b0;
				err<=1'b0;
				my_fsm<=STATE_IDLE;
	          end
	else begin

			shift_serial_in<={shift_serial_in[0],serial_in};
			case(my_fsm)
				STATE_IDLE: begin
									done<=1'b0;  
									err<=1'b0;
									if(clock_count==4'd8) begin
																clock_count<=4'd0;
																my_fsm<=STATE_DATA_BITS;
																busy<=1'b1;
																received_data<=8'd0;
																bitIndex<=3'd0;
															end
									else if(negedge_rxd || clock_count!=4'd0) begin

																				if(&shift_serial_in) begin
																										err<=1'b1;
																										clock_count<=4'd0;
																										my_fsm<=STATE_IDLE;
																									 end
																				else
																					clock_count<=clock_count+1'b1;
																			  end	
							end
				STATE_DATA_BITS: begin 									
									if(clock_count==4'd15) begin
																clock_count<=4'd0;
																received_data[bitIndex]<=shift_serial_in[0];
																if(bitIndex==3'd7) begin
																				bitIndex<=3'd0;
																				my_fsm<=STATE_STOP_BIT;
																	  			end
																else
																		bitIndex<=bitIndex+1'b1;
									                 		end
									else
										clock_count<=clock_count+1'b1;
								 end
				STATE_STOP_BIT: begin 
									if(clock_count==4'd15) begin
																clock_count<=4'd0;
																my_fsm<=STATE_IDLE;
																busy<=1'b0;


																if(!(|shift_serial_in)) begin
																							err<=1'b1;
																						 end
																else begin
																		done<=1'b1;
																		parallel_out<=received_data;
																	 end
														   end
									else begin
											clock_count<=clock_count+1'b1;
										 end
								end
				default:  my_fsm<=STATE_IDLE;
			endcase
	     end
end
endmodule
module uart_rx(clk,reset,serial_in,parallel_out,done,busy,err);

input clk;
input reset;
input serial_in;

output reg [7:0] parallel_out;
output reg done;
output reg busy;
output reg err;


parameter STATE_IDLE=2'b00;
parameter STATE_DATA_BITS=2'b01;
parameter STATE_STOP_BIT=2'b10;
reg [1:0] my_fsm;


wire negedge_rxd;



reg [1:0] shift_serial_in;

assign negedge_rxd=shift_serial_in[1]&(~shift_serial_in[0]);


reg [7:0] received_data;

reg [3:0] clock_count;


reg [2:0] bitIndex;

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				parallel_out<=8'd0;
				received_data<=8'd0;
				bitIndex<=3'd0;
				shift_serial_in<=2'd0;
				clock_count<=4'd0;
				done<=1'b0;
				busy<=1'b0;
				err<=1'b0;
				my_fsm<=STATE_IDLE;
	          end
	else begin

			shift_serial_in<={shift_serial_in[0],serial_in};
			case(my_fsm)
				STATE_IDLE: begin
									done<=1'b0;  
									err<=1'b0;
									if(clock_count==4'd8) begin
																clock_count<=4'd0;
																my_fsm<=STATE_DATA_BITS;
																busy<=1'b1;
																received_data<=8'd0;
																bitIndex<=3'd0;
															end
									else if(negedge_rxd || clock_count!=4'd0) begin

																				if(&shift_serial_in) begin
																										err<=1'b1;
																										clock_count<=4'd0;
																										my_fsm<=STATE_IDLE;
																									 end
																				else
																					clock_count<=clock_count+1'b1;
																			  end	
							end
				STATE_DATA_BITS: begin 									
									if(clock_count==4'd15) begin
																clock_count<=4'd0;
																received_data[bitIndex]<=shift_serial_in[0];
																if(bitIndex==3'd7) begin
																				bitIndex<=3'd0;
																				my_fsm<=STATE_STOP_BIT;
																	  			end
																else
																		bitIndex<=bitIndex+1'b1;
									                 		end
									else
										clock_count<=clock_count+1'b1;
								 end
				STATE_STOP_BIT: begin 
									if(clock_count==4'd15) begin
																clock_count<=4'd0;
																my_fsm<=STATE_IDLE;
																busy<=1'b0;


																if(!(|shift_serial_in)) begin
																							err<=1'b1;
																						 end
																else begin
																		done<=1'b1;
																		parallel_out<=received_data;
																	 end
														   end
									else begin
											clock_count<=clock_count+1'b1;
										 end
								end
				default:  my_fsm<=STATE_IDLE;
			endcase
	     end
end
endmodule