data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:8: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:10: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:12: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Main_Control.v:19: Unsupported or unknown PLI call: $monitor\n$monitor("op=%4b,RegDst=%1b,ALUSrc=%1b,MemtoReg=%1b,RegWrite=%1b,MemRead=%1b,MemWrite=%1b,Branch=%1b,Branch_not=%1b,ALUop0=%1b,ALUop1=%1b,ALUop2=%1b",\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_Main_Control();
reg [3:0]op;
wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
Main_Control ahmet(op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);
initial begin
op = 4'b0000;
#`DELAY;
op = 4'b0001;
#`DELAY;
op = 4'b0101;
#`DELAY;
op = 4'b1000;
#`DELAY;
op = 4'b1001;
#`DELAY;
end
initial begin
$monitor("op=%4b,RegDst=%1b,ALUSrc=%1b,MemtoReg=%1b,RegWrite=%1b,MemRead=%1b,MemWrite=%1b,Branch=%1b,Branch_not=%1b,ALUop0=%1b,ALUop1=%1b,ALUop2=%1b",
					op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);


end

endmodule
module test_bench_Main_Control();

reg [3:0]op;
wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
Main_Control ahmet(op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);
initial begin
op = 4'b0000;
#`DELAY;
op = 4'b0001;
#`DELAY;
op = 4'b0101;
#`DELAY;
op = 4'b1000;
#`DELAY;
op = 4'b1001;
#`DELAY;
end
initial begin
$monitor("op=%4b,RegDst=%1b,ALUSrc=%1b,MemtoReg=%1b,RegWrite=%1b,MemRead=%1b,MemWrite=%1b,Branch=%1b,Branch_not=%1b,ALUop0=%1b,ALUop1=%1b,ALUop2=%1b",
					op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);


end

endmodule