data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v
1: b'%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v:19: Cannot find file containing module: \'gen_counter\'\ngen_counter COUNT0 (.wait_val(NUM_SAMPS), .clk(CLK), .en(EN), .f(internal_done));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/gen_counter\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/gen_counter.v\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/gen_counter.sv\n             gen_counter\n             gen_counter.v\n             gen_counter.sv\n             obj_dir/gen_counter\n             obj_dir/gen_counter.v\n             obj_dir/gen_counter.sv\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v:20: Cannot find file containing module: \'gen_counter\'\ngen_counter COUNT1 (.wait_val(NUM_SAMPS+1), .clk(CLK), .en(EN), .f(internal_done_monitor));\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v:22: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                                    : ... In instance ADC_AVERAGE\nreg  [ ADC_WIDTH : 0] VALID_SUM = {ADC_WIDTH{1\'b0}};\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v:24: Operator ASSIGNW expects 23 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                                    : ... In instance ADC_AVERAGE\nassign ADDER_IN = {{12{DATA_IN[ADC_WIDTH-1]}}, DATA_IN} ;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_AVERAGE.v:37: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s SEL generates 14 bits.\n                                                                                                    : ... In instance ADC_AVERAGE\n        VALID_SUM = SUM[13+10:10];\n                  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module ADC_AVERAGE
#(
    parameter ADC_WIDTH = 12,
    parameter NUM_SAMPS = 1024
)
(
    input CLK,
    input EN,
    input  [ADC_WIDTH - 1 : 0] DATA_IN,
    output DONE,
    output [ADC_WIDTH - 1 : 0] DATA_OUT
);

reg [ 24-1 : 0] SUM = 24'h000000;

wire internal_done;
wire internal_done_monitor;
wire [24-2 : 0] ADDER_IN;
gen_counter COUNT0 (.wait_val(NUM_SAMPS), .clk(CLK), .en(EN), .f(internal_done));
gen_counter COUNT1 (.wait_val(NUM_SAMPS+1), .clk(CLK), .en(EN), .f(internal_done_monitor));

reg  [ ADC_WIDTH : 0] VALID_SUM = {ADC_WIDTH{1'b0}};

assign ADDER_IN = {{12{DATA_IN[ADC_WIDTH-1]}}, DATA_IN} ;

always @(posedge CLK)
if (EN == 1'b0) begin
    SUM   = 24'h000000;
end 
else
begin
    if (!internal_done) begin
        SUM   = $signed(SUM) + $signed(ADDER_IN);
    end
    else
    begin
        VALID_SUM = SUM[13+10:10];
    end
end

assign DONE = internal_done_monitor;
assign DATA_OUT = VALID_SUM[ADC_WIDTH - 1:0];
endmodule
module ADC_AVERAGE
#(
    parameter ADC_WIDTH = 12,
    parameter NUM_SAMPS = 1024
)
(
    input CLK,
    input EN,
    input  [ADC_WIDTH - 1 : 0] DATA_IN,
    output DONE,
    output [ADC_WIDTH - 1 : 0] DATA_OUT
);


reg [ 24-1 : 0] SUM = 24'h000000;

wire internal_done;
wire internal_done_monitor;
wire [24-2 : 0] ADDER_IN;
gen_counter COUNT0 (.wait_val(NUM_SAMPS), .clk(CLK), .en(EN), .f(internal_done));
gen_counter COUNT1 (.wait_val(NUM_SAMPS+1), .clk(CLK), .en(EN), .f(internal_done_monitor));

reg  [ ADC_WIDTH : 0] VALID_SUM = {ADC_WIDTH{1'b0}};

assign ADDER_IN = {{12{DATA_IN[ADC_WIDTH-1]}}, DATA_IN} ;

always @(posedge CLK)
if (EN == 1'b0) begin
    SUM   = 24'h000000;
end 
else
begin
    if (!internal_done) begin
        SUM   = $signed(SUM) + $signed(ADDER_IN);
    end
    else
    begin
        VALID_SUM = SUM[13+10:10];
    end
end

assign DONE = internal_done_monitor;
assign DATA_OUT = VALID_SUM[ADC_WIDTH - 1:0];
endmodule