data/full_repos/permissive/470803657/modules/register.v
data/verilator_xmls/2cf00005-6501-44ea-af58-a6b142efde07.xml
module register (input  wire       clock,
                 input  wire       reset,
                 input  wire       load,
                 input  wire [7:0] in_reg,
                 output reg  [7:0] out_reg);

always @ (posedge clock or negedge reset) begin
  if(!reset)
    out_reg <= 0;
  else if(load)
    out_reg <= in_reg;
  else
    out_reg <= out_reg; 
end

endmodule
module register (input  wire       clock,
                 input  wire       reset,
                 input  wire       load,
                 input  wire [7:0] in_reg,
                 output reg  [7:0] out_reg);


always @ (posedge clock or negedge reset) begin
  if(!reset)
    out_reg <= 0;
  else if(load)
    out_reg <= in_reg;
  else
    out_reg <= out_reg; 
end

endmodule