data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_1/seq_det_101_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_1,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_1/seq_det_101_TB.v\n%Error: Exiting due to 5 error(s)\n'
module seq_det_101_TB;
	reg  clock;
	reg  reset;
	reg  serial_in;
	wire detect_101;

	sequence_detector_101 DUT(.clock(clock), .reset(reset), 
							  .serial_in(serial_in), 
							  .detect_101(detect_101));

	always #2 clock = ~clock;

	initial begin
		$dumpfile("seq_det_101_TB.vcd");
		$dumpvars(0, seq_det_101_TB);
	end

	reg [15:0] data = 16'b0100_1010_0101_1011;

	integer i;
	
	initial begin
		clock = 0;
		reset = 0;
		serial_in = 0;
		#9 reset = 1;
		
		for(i = 0; i < 16; i = i + 1) begin
			serial_in = data[i];
			#4;
		end
		
		#4 $finish;
	end

endmodule
module seq_det_101_TB;

	reg  clock;
	reg  reset;
	reg  serial_in;
	wire detect_101;

	sequence_detector_101 DUT(.clock(clock), .reset(reset), 
							  .serial_in(serial_in), 
							  .detect_101(detect_101));

	always #2 clock = ~clock;

	initial begin
		$dumpfile("seq_det_101_TB.vcd");
		$dumpvars(0, seq_det_101_TB);
	end

	reg [15:0] data = 16'b0100_1010_0101_1011;

	integer i;
	
	initial begin
		clock = 0;
		reset = 0;
		serial_in = 0;
		#9 reset = 1;
		
		for(i = 0; i < 16; i = i + 1) begin
			serial_in = data[i];
			#4;
		end
		
		#4 $finish;
	end

endmodule