data/full_repos/permissive/529984920/src/mul_2_bits.v
1: b'%Error: data/full_repos/permissive/529984920/src/mul_2_bits.v:4: Cannot find include file: ./src/pos_add.v\n`include "./src/pos_add.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/529984920/src,data/full_repos/permissive/529984920/./src/pos_add.v\n             data/full_repos/permissive/529984920/src,data/full_repos/permissive/529984920/./src/pos_add.v.v\n             data/full_repos/permissive/529984920/src,data/full_repos/permissive/529984920/./src/pos_add.v.sv\n             ./src/pos_add.v\n             ./src/pos_add.v.v\n             ./src/pos_add.v.sv\n             obj_dir/./src/pos_add.v\n             obj_dir/./src/pos_add.v.v\n             obj_dir/./src/pos_add.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mul_2_bits (a, b, c);


    input wire [1:0] a, b;
    output wire [3:0] c;
   

    wire [2:0] b_zero;
    wire [2:0] zero_b;
    assign b_zero = {b, 1'b0};
    assign zero_b = {1'b0, b};


    wire [2:0] b_zero_a_1;
    wire [2:0] zero_b_a_0;
    assign b_zero_a_1 = a[1] ? b_zero : 3'b0;
    assign zero_b_a_0 = a[0] ? zero_b : 3'b0;


    pos_add #(3) ADD (b_zero_a_1, zero_b_a_0, c);

endmodule
module mul_2_bits (a, b, c);



    input wire [1:0] a, b;
    output wire [3:0] c;
   

    wire [2:0] b_zero;
    wire [2:0] zero_b;
    assign b_zero = {b, 1'b0};
    assign zero_b = {1'b0, b};


    wire [2:0] b_zero_a_1;
    wire [2:0] zero_b_a_0;
    assign b_zero_a_1 = a[1] ? b_zero : 3'b0;
    assign zero_b_a_0 = a[0] ? zero_b : 3'b0;


    pos_add #(3) ADD (b_zero_a_1, zero_b_a_0, c);

endmodule