data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:1: Cannot find include file: arbiter.v\n`include "arbiter.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/arbiter.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/arbiter.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/arbiter.v.sv\n             arbiter.v\n             arbiter.v.v\n             arbiter.v.sv\n             obj_dir/arbiter.v\n             obj_dir/arbiter.v.v\n             obj_dir/arbiter.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("arbiter.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars();\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst = 0;\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:28: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:30: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:32: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:35: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:38: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:41: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:43: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:45: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/arbiter_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module top ();

reg             clk;    
reg             rst;    
reg             req3;   
reg             req2;   
reg             req1;   
reg             req0;   
wire            gnt3;   
wire            gnt2;   
wire            gnt1;   
wire            gnt0;  


always #1 clk = ~clk;

initial begin
  $dumpfile ("arbiter.vcd");
  $dumpvars();
  clk = 0;
  rst = 1;
  req0 = 0;
  req1 = 0;
  req2 = 0;
  req3 = 0;
  #10 rst = 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  req1 <= 1;
  repeat (1) @ (posedge clk);
  req2 <= 1;
  req1 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 1;
  req2 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  #10 $finish;
end 


arbiter U (
 clk,    
 rst,    
 req3,   
 req2,   
 req1,   
 req0,   
 gnt3,   
 gnt2,   
 gnt1,   
 gnt0   
);

endmodule
module top ();


reg             clk;    
reg             rst;    
reg             req3;   
reg             req2;   
reg             req1;   
reg             req0;   
wire            gnt3;   
wire            gnt2;   
wire            gnt1;   
wire            gnt0;  


always #1 clk = ~clk;

initial begin
  $dumpfile ("arbiter.vcd");
  $dumpvars();
  clk = 0;
  rst = 1;
  req0 = 0;
  req1 = 0;
  req2 = 0;
  req3 = 0;
  #10 rst = 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  req1 <= 1;
  repeat (1) @ (posedge clk);
  req2 <= 1;
  req1 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 1;
  req2 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  #10 $finish;
end 


arbiter U (
 clk,    
 rst,    
 req3,   
 req2,   
 req1,   
 req0,   
 gnt3,   
 gnt2,   
 gnt1,   
 gnt0   
);

endmodule