data/full_repos/permissive/471089853/src/arith_to_s3.v
1: b"%Error: data/full_repos/permissive/471089853/src/arith_to_s3.v:98: Cannot find file containing module: 'LZOCShifter_6_to_6_counting_8_F400_uid18'\n  LZOCShifter_6_to_6_counting_8_F400_uid18 lzoc (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifter_6_to_6_counting_8_F400_uid18\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifter_6_to_6_counting_8_F400_uid18.v\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/LZOCShifter_6_to_6_counting_8_F400_uid18.sv\n             LZOCShifter_6_to_6_counting_8_F400_uid18\n             LZOCShifter_6_to_6_counting_8_F400_uid18.v\n             LZOCShifter_6_to_6_counting_8_F400_uid18.sv\n             obj_dir/LZOCShifter_6_to_6_counting_8_F400_uid18\n             obj_dir/LZOCShifter_6_to_6_counting_8_F400_uid18.v\n             obj_dir/LZOCShifter_6_to_6_counting_8_F400_uid18.sv\n%Error: Exiting due to 1 error(s)\n"
module Arith_to_S3(clk, arith_i, S3_o);
  reg _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire [2:0] _10_;
  reg _11_;
  wire [5:0] _12_;
  wire _13_;
  wire [3:0] _14_;
  wire [3:0] _15_;
  wire [3:0] _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg [3:0] _21_;
  reg [4:0] _22_;
  reg [3:0] _23_;
  output [11:0] S3_o;
  input [7:0] arith_i;
  wire [3:0] biased_exponent;
  input clk;
  wire [3:0] comp2_range_count;
  wire [3:0] exponent;
  wire [3:0] exponent_d1;
  wire [3:0] extended_neg_count;
  wire [3:0] extended_neg_count_d1;
  wire [4:0] fraction;
  wire [4:0] fraction_d1;
  wire implicit;
  wire implicit_d1;
  wire implicit_d2;
  wire is_nar;
  wire is_nar_d1;
  wire is_nar_d2;
  wire [2:0] lzcount;
  wire neg_count;
  wire not_s;
  wire regime_check;
  wire [5:0] remainder;
  wire sign;
  wire sign_d1;
  wire sign_d2;
  wire [5:0] usefulbits;
  wire zero_nar;
  always @(posedge clk)
    _00_ <= sign;
  always @(posedge clk)
    _11_ <= sign_d1;
  always @(posedge clk)
    _17_ <= is_nar;
  always @(posedge clk)
    _18_ <= is_nar_d1;
  always @(posedge clk)
    _19_ <= implicit;
  always @(posedge clk)
    _20_ <= implicit_d1;
  always @(posedge clk)
    _21_ <= extended_neg_count;
  always @(posedge clk)
    _22_ <= fraction;
  always @(posedge clk)
    _23_ <= exponent;
  assign _01_ = ~ sign;
  assign _02_ = ~ regime_check;
  assign _03_ = remainder == 6'h00;
  assign _04_ = _03_ ? _02_ : 1'h0;
  assign _05_ = zero_nar & sign;
  assign _06_ = zero_nar & not_s;
  assign _07_ = ~ _06_;
  assign _08_ = sign ^ regime_check;
  assign _09_ = ~ _08_;
  assign _13_ = neg_count == 1'h1;
  function [3:0] \43 ;
    input [3:0] a;
    input [3:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \43  = b[3:0];
      default:
        \43  = a;
    endcase
  endfunction
  assign _14_ = \43 (4'h0, 4'hf, _13_);
  assign _15_ = extended_neg_count_d1 ^ { 1'h0, lzcount };
  assign _16_ = exponent_d1 + 4'h6;
  LZOCShifter_6_to_6_counting_8_F400_uid18 lzoc (
    .Count(_10_),
    .I(remainder),
    .O(_12_),
    .OZb(regime_check),
    .clk(clk)
  );
  assign sign = arith_i[7];
  assign sign_d1 = _00_;
  assign sign_d2 = _11_;
  assign regime_check = arith_i[6];
  assign remainder = arith_i[5:0];
  assign not_s = _01_;
  assign zero_nar = _04_;
  assign is_nar = _05_;
  assign is_nar_d1 = _17_;
  assign is_nar_d2 = _18_;
  assign implicit = _07_;
  assign implicit_d1 = _19_;
  assign implicit_d2 = _20_;
  assign neg_count = _09_;
  assign lzcount = _10_;
  assign usefulbits = _12_;
  assign extended_neg_count = _14_;
  assign extended_neg_count_d1 = _21_;
  assign comp2_range_count = _15_;
  assign fraction = usefulbits[4:0];
  assign fraction_d1 = _22_;
  assign exponent = comp2_range_count;
  assign exponent_d1 = _23_;
  assign biased_exponent = _16_;
  assign S3_o = { is_nar_d2, sign_d2, implicit_d2, fraction_d1, biased_exponent };
endmodule
module Arith_to_S3(clk, arith_i, S3_o);

  reg _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire [2:0] _10_;
  reg _11_;
  wire [5:0] _12_;
  wire _13_;
  wire [3:0] _14_;
  wire [3:0] _15_;
  wire [3:0] _16_;
  reg _17_;
  reg _18_;
  reg _19_;
  reg _20_;
  reg [3:0] _21_;
  reg [4:0] _22_;
  reg [3:0] _23_;
  output [11:0] S3_o;
  input [7:0] arith_i;
  wire [3:0] biased_exponent;
  input clk;
  wire [3:0] comp2_range_count;
  wire [3:0] exponent;
  wire [3:0] exponent_d1;
  wire [3:0] extended_neg_count;
  wire [3:0] extended_neg_count_d1;
  wire [4:0] fraction;
  wire [4:0] fraction_d1;
  wire implicit;
  wire implicit_d1;
  wire implicit_d2;
  wire is_nar;
  wire is_nar_d1;
  wire is_nar_d2;
  wire [2:0] lzcount;
  wire neg_count;
  wire not_s;
  wire regime_check;
  wire [5:0] remainder;
  wire sign;
  wire sign_d1;
  wire sign_d2;
  wire [5:0] usefulbits;
  wire zero_nar;
  always @(posedge clk)
    _00_ <= sign;
  always @(posedge clk)
    _11_ <= sign_d1;
  always @(posedge clk)
    _17_ <= is_nar;
  always @(posedge clk)
    _18_ <= is_nar_d1;
  always @(posedge clk)
    _19_ <= implicit;
  always @(posedge clk)
    _20_ <= implicit_d1;
  always @(posedge clk)
    _21_ <= extended_neg_count;
  always @(posedge clk)
    _22_ <= fraction;
  always @(posedge clk)
    _23_ <= exponent;
  assign _01_ = ~ sign;
  assign _02_ = ~ regime_check;
  assign _03_ = remainder == 6'h00;
  assign _04_ = _03_ ? _02_ : 1'h0;
  assign _05_ = zero_nar & sign;
  assign _06_ = zero_nar & not_s;
  assign _07_ = ~ _06_;
  assign _08_ = sign ^ regime_check;
  assign _09_ = ~ _08_;
  assign _13_ = neg_count == 1'h1;
  function [3:0] \43 ;
    input [3:0] a;
    input [3:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \43  = b[3:0];
      default:
        \43  = a;
    endcase
  endfunction
  assign _14_ = \43 (4'h0, 4'hf, _13_);
  assign _15_ = extended_neg_count_d1 ^ { 1'h0, lzcount };
  assign _16_ = exponent_d1 + 4'h6;
  LZOCShifter_6_to_6_counting_8_F400_uid18 lzoc (
    .Count(_10_),
    .I(remainder),
    .O(_12_),
    .OZb(regime_check),
    .clk(clk)
  );
  assign sign = arith_i[7];
  assign sign_d1 = _00_;
  assign sign_d2 = _11_;
  assign regime_check = arith_i[6];
  assign remainder = arith_i[5:0];
  assign not_s = _01_;
  assign zero_nar = _04_;
  assign is_nar = _05_;
  assign is_nar_d1 = _17_;
  assign is_nar_d2 = _18_;
  assign implicit = _07_;
  assign implicit_d1 = _19_;
  assign implicit_d2 = _20_;
  assign neg_count = _09_;
  assign lzcount = _10_;
  assign usefulbits = _12_;
  assign extended_neg_count = _14_;
  assign extended_neg_count_d1 = _21_;
  assign comp2_range_count = _15_;
  assign fraction = usefulbits[4:0];
  assign fraction_d1 = _22_;
  assign exponent = comp2_range_count;
  assign exponent_d1 = _23_;
  assign biased_exponent = _16_;
  assign S3_o = { is_nar_d2, sign_d2, implicit_d2, fraction_d1, biased_exponent };
endmodule