data/full_repos/permissive/425166201/01_test_div/tb.v
1: b'%Error: data/full_repos/permissive/425166201/01_test_div/tb.v:51: Cannot find include file: divmod.v\n`include "divmod.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425166201/01_test_div,data/full_repos/permissive/425166201/divmod.v\n             data/full_repos/permissive/425166201/01_test_div,data/full_repos/permissive/425166201/divmod.v.v\n             data/full_repos/permissive/425166201/01_test_div,data/full_repos/permissive/425166201/divmod.v.sv\n             divmod.v\n             divmod.v.v\n             divmod.v.sv\n             obj_dir/divmod.v\n             obj_dir/divmod.v.v\n             obj_dir/divmod.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/425166201/01_test_div/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clock    = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425166201/01_test_div/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #1.0 clock_50 = ~clock_50;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/425166201/01_test_div/tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #2.0 clock_25 = ~clock_25;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/425166201/01_test_div/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clock = 0; clock_25 = 0; clock_50 = 0; #2000 $finish; end\n                                                     ^\n%Error: data/full_repos/permissive/425166201/01_test_div/tb.v:15: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/425166201/01_test_div/tb.v:15: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end\n                                   ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module tb;

reg clock;
reg clock_25;
reg clock_50;


always #0.5 clock    = ~clock;
always #1.0 clock_50 = ~clock_50;
always #2.0 clock_25 = ~clock_25;


initial begin clock = 0; clock_25 = 0; clock_50 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end


localparam depth = 4;
localparam width = 8;

wire [(width-1):0] ro[depth];
wire [(width-1):0] qo[depth];

wire [(width-1):0] q    = 4'hF;
wire [(width-1):0] b    = 4'h2;
wire [(width-1):0] zero = 1'b0;

divmod #(.WIDTH( width )) UnitDivMod
(
    .b  (b),
    .q  (q),     .r  (zero),
    .qo (qo[0]), .ro (ro[0])
);

genvar i;
generate

for (i = 0; i < depth-1; i=i+1) begin : DivModX
divmod #(.WIDTH(width)) UnitDivMod
(
    .b  (b),
    .q  (qo[i  ]), .r  (ro[i  ]),
    .qo (qo[i+1]), .ro (ro[i+1])
);
end

endgenerate

endmodule
module tb;


reg clock;
reg clock_25;
reg clock_50;


always #0.5 clock    = ~clock;
always #1.0 clock_50 = ~clock_50;
always #2.0 clock_25 = ~clock_25;


initial begin clock = 0; clock_25 = 0; clock_50 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end


localparam depth = 4;
localparam width = 8;

wire [(width-1):0] ro[depth];
wire [(width-1):0] qo[depth];

wire [(width-1):0] q    = 4'hF;
wire [(width-1):0] b    = 4'h2;
wire [(width-1):0] zero = 1'b0;

divmod #(.WIDTH( width )) UnitDivMod
(
    .b  (b),
    .q  (q),     .r  (zero),
    .qo (qo[0]), .ro (ro[0])
);

genvar i;
generate

for (i = 0; i < depth-1; i=i+1) begin : DivModX
divmod #(.WIDTH(width)) UnitDivMod
(
    .b  (b),
    .q  (qo[i  ]), .r  (ro[i  ]),
    .qo (qo[i+1]), .ro (ro[i+1])
);
end

endgenerate

endmodule