data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:225: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:243: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:253: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:259: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:263: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:265: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:266: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:269: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:274: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:277: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:278: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:279: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:280: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:282: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:283: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:286: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:288: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:291: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:293: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:294: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:297: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:299: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:300: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:302: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:303: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:306: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:307: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:308: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:312: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:313: Unsupported: Ignoring delay on this delayed statement.\n #10 adc_clk = ~adc_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/new_FSM_tb.v:13: Cannot find file containing module: \'new_FSM\'\nnew_FSM FSM(.TRIG_IN(TRIG_IN), .adc_clk(adc_clk), .start(start), .FSM_JP_WRT(FSM_JP_WRT), .FSM_JM_WRT(FSM_JM_WRT), .FSM_U_WRT(FSM_U_WRT), .FSM_DAC_SEL(FSM_DAC_SEL), .FSM_STATE(FSM_STATE));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/new_FSM\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/new_FSM.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/new_FSM.sv\n             new_FSM\n             new_FSM.v\n             new_FSM.sv\n             obj_dir/new_FSM\n             obj_dir/new_FSM.v\n             obj_dir/new_FSM.sv\n%Error: Exiting due to 1 error(s), 295 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module new_FSM_tb;

reg TRIG_IN = 1'b0;
reg adc_clk = 1'b0;
reg start = 1'b0;
wire FSM_JP_WRT;
wire FSM_JM_WRT;
wire FSM_U_WRT;
wire [1:0] FSM_DAC_SEL;
wire [5:0] FSM_STATE;


new_FSM FSM(.TRIG_IN(TRIG_IN), .adc_clk(adc_clk), .start(start), .FSM_JP_WRT(FSM_JP_WRT), .FSM_JM_WRT(FSM_JM_WRT), .FSM_U_WRT(FSM_U_WRT), .FSM_DAC_SEL(FSM_DAC_SEL), .FSM_STATE(FSM_STATE));

initial
begin
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	start = 1'b1;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	TRIG_IN = 1'b1;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	TRIG_IN = 1'b0;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 $finish;
end
endmodule
module new_FSM_tb;


reg TRIG_IN = 1'b0;
reg adc_clk = 1'b0;
reg start = 1'b0;
wire FSM_JP_WRT;
wire FSM_JM_WRT;
wire FSM_U_WRT;
wire [1:0] FSM_DAC_SEL;
wire [5:0] FSM_STATE;


new_FSM FSM(.TRIG_IN(TRIG_IN), .adc_clk(adc_clk), .start(start), .FSM_JP_WRT(FSM_JP_WRT), .FSM_JM_WRT(FSM_JM_WRT), .FSM_U_WRT(FSM_U_WRT), .FSM_DAC_SEL(FSM_DAC_SEL), .FSM_STATE(FSM_STATE));

initial
begin
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	start = 1'b1;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	TRIG_IN = 1'b1;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	TRIG_IN = 1'b0;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 adc_clk = ~adc_clk;
	#10 $finish;
end
endmodule