data/full_repos/permissive/493019833/test/testcase/firrtl/Memo/reference/Memo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Memo/reference/Memo.v:92: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                  : ... In instance Memo.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Memo(
    input clock,
    input reset,
    input io_wen,
    input [7:0] io_wrAddr,
    input [7:0] io_wrData,
    input io_ren,
    input [7:0] io_rdAddr,
    output [7:0] io_rdData
);
    wire mem__T_19_clk;
    wire mem__T_19_en;
    wire mem__T_19_mask;
    wire [7:0] mem__T_19_addr;
    wire [7:0] mem__T_19_data;
    wire [7:0] mem__T_21_data;
    wire mem__T_21_clk;
    wire mem__T_21_en;
    wire [7:0] mem__T_21_addr;
    RAMMEM #(.depth(256), .addrbits(8), .width(8), .isSyncRead(0)) mem (
        .read_data(mem__T_21_data),
        .read_clk(mem__T_21_clk),
        .read_en(mem__T_21_en),
        .read_addr(mem__T_21_addr),
        .write_clk(mem__T_19_clk),
        .write_en(mem__T_19_en),
        .write_mask(mem__T_19_mask),
        .write_addr(mem__T_19_addr),
        .write_data(mem__T_19_data)
    );
    assign mem__T_19_addr = io_wrAddr;
    assign mem__T_19_en = io_wen;
    assign mem__T_19_clk = clock;
    assign mem__T_19_mask = 1'h1;
    assign mem__T_21_addr = io_rdAddr;
    assign mem__T_21_en = io_ren;
    assign mem__T_21_clk = clock;
    wire [7:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(8)) u_pad_1 (
        .y(_WTEMP_0),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(8)) u_mux_2 (
        .y(io_rdData),
        .sel(io_ren),
        .a(mem__T_21_data),
        .b(_WTEMP_0)
    );
    assign mem__T_19_data = io_wrData;
endmodule
module Memo(
    input clock,
    input reset,
    input io_wen,
    input [7:0] io_wrAddr,
    input [7:0] io_wrData,
    input io_ren,
    input [7:0] io_rdAddr,
    output [7:0] io_rdData
);

    wire mem__T_19_clk;
    wire mem__T_19_en;
    wire mem__T_19_mask;
    wire [7:0] mem__T_19_addr;
    wire [7:0] mem__T_19_data;
    wire [7:0] mem__T_21_data;
    wire mem__T_21_clk;
    wire mem__T_21_en;
    wire [7:0] mem__T_21_addr;
    RAMMEM #(.depth(256), .addrbits(8), .width(8), .isSyncRead(0)) mem (
        .read_data(mem__T_21_data),
        .read_clk(mem__T_21_clk),
        .read_en(mem__T_21_en),
        .read_addr(mem__T_21_addr),
        .write_clk(mem__T_19_clk),
        .write_en(mem__T_19_en),
        .write_mask(mem__T_19_mask),
        .write_addr(mem__T_19_addr),
        .write_data(mem__T_19_data)
    );
    assign mem__T_19_addr = io_wrAddr;
    assign mem__T_19_en = io_wen;
    assign mem__T_19_clk = clock;
    assign mem__T_19_mask = 1'h1;
    assign mem__T_21_addr = io_rdAddr;
    assign mem__T_21_en = io_ren;
    assign mem__T_21_clk = clock;
    wire [7:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(1), .n(8)) u_pad_1 (
        .y(_WTEMP_0),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(8)) u_mux_2 (
        .y(io_rdData),
        .sel(io_ren),
        .a(mem__T_21_data),
        .b(_WTEMP_0)
    );
    assign mem__T_19_data = io_wrData;
endmodule