data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/83816707-9daa-4bf5-bc10-0e1f6445f6a9.xml
module dut_vlwrapper(
      clk,
       rst,
       din_1_busy,
       din_1_vld,
       din_1_data,
       din_2_busy,
       din_2_vld,
       din_2_data,
       dout_busy,
       dout_vld,
       dout_data

    );

	input clk;
	input rst;
	output din_1_busy;
	reg din_1_busy;
	wire m_din_1_busy;
	input din_1_vld;
	input [7:0] din_1_data;
	output din_2_busy;
	reg din_2_busy;
	wire m_din_2_busy;
	input din_2_vld;
	input [7:0] din_2_data;
	input dout_busy;
	output dout_vld;
	reg dout_vld;
	wire m_dout_vld;
	output [8:0] dout_data;
	reg[8:0] dout_data;
	wire [8:0] m_dout_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .din_1_busy(m_din_1_busy),
         .din_1_vld(din_1_vld),
         .din_1_data(din_1_data),
         .din_2_busy(m_din_2_busy),
         .din_2_vld(din_2_vld),
         .din_2_data(din_2_data),
         .dout_busy(dout_busy),
         .dout_vld(m_dout_vld),
         .dout_data(m_dout_data)

    );




    always @(m_din_1_busy)
     begin
      din_1_busy <= m_din_1_busy;
     end
    always @(m_din_2_busy)
     begin
      din_2_busy <= m_din_2_busy;
     end
    always @(m_dout_vld)
     begin
      dout_vld <= m_dout_vld;
     end
    always @(m_dout_data)
     begin
      dout_data <= m_dout_data;
     end


endmodule
module dut_vlwrapper(
      clk,
       rst,
       din_1_busy,
       din_1_vld,
       din_1_data,
       din_2_busy,
       din_2_vld,
       din_2_data,
       dout_busy,
       dout_vld,
       dout_data

    );


	input clk;
	input rst;
	output din_1_busy;
	reg din_1_busy;
	wire m_din_1_busy;
	input din_1_vld;
	input [7:0] din_1_data;
	output din_2_busy;
	reg din_2_busy;
	wire m_din_2_busy;
	input din_2_vld;
	input [7:0] din_2_data;
	input dout_busy;
	output dout_vld;
	reg dout_vld;
	wire m_dout_vld;
	output [8:0] dout_data;
	reg[8:0] dout_data;
	wire [8:0] m_dout_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .din_1_busy(m_din_1_busy),
         .din_1_vld(din_1_vld),
         .din_1_data(din_1_data),
         .din_2_busy(m_din_2_busy),
         .din_2_vld(din_2_vld),
         .din_2_data(din_2_data),
         .dout_busy(dout_busy),
         .dout_vld(m_dout_vld),
         .dout_data(m_dout_data)

    );




    always @(m_din_1_busy)
     begin
      din_1_busy <= m_din_1_busy;
     end
    always @(m_din_2_busy)
     begin
      din_2_busy <= m_din_2_busy;
     end
    always @(m_dout_vld)
     begin
      dout_vld <= m_dout_vld;
     end
    always @(m_dout_data)
     begin
      dout_data <= m_dout_data;
     end


endmodule