data/full_repos/permissive/411831376/LCD.v
1: b'%Error: data/full_repos/permissive/411831376/LCD.v:44: Cannot find file containing module: \'InSSaP\'\n InSSaP InSSaP(.source(InSSaPQ), .probe(1\'d0));\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/InSSaP\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/InSSaP.v\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/InSSaP.sv\n             InSSaP\n             InSSaP.v\n             InSSaP.sv\n             obj_dir/InSSaP\n             obj_dir/InSSaP.v\n             obj_dir/InSSaP.sv\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:93: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'TSLQ\' generates 2 bits.\n                                                             : ... In instance LCD\n wire L_DY = L_DQ & (!TSLQ | &TSLQ);\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:177: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'CTRAMQ\' generates 6 bits.\n                                                              : ... In instance LCD\n     else if(DEC_CTRAMY & !CTRAMQ) CTRAMQ <= 6\'d39;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:184: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'CTRAMQ\' generates 6 bits.\n                                                              : ... In instance LCD\n       else if (DEC_CTRAMY &  TADDRAMQ & !CTRAMQ  ) TADDRAMQ <= 1\'d0;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:183: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'CTRAMQ\' generates 6 bits.\n                                                              : ... In instance LCD\n      else if  (DEC_CTRAMY & !TADDRAMQ & !CTRAMQ  ) TADDRAMQ <= 1\'d1;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:204: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'CTBaseDispQ\' generates 6 bits.\n                                                              : ... In instance LCD\n    else if(DEC_CTBaseDispY & !CTBaseDispQ) CTBaseDispQ <= 6\'d39;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:212: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h5\' generates 7 bits.\n                                                              : ... In instance LCD\n  if(WR_REGBKQ) REGBKQ <= REGDRQ<7\'d5 ? 7\'d5 : (REGDRQ>7\'d95 ? 7\'d95 : REGDRQ[6:0]);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:212: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h5f\' generates 7 bits.\n                                                              : ... In instance LCD\n  if(WR_REGBKQ) REGBKQ <= REGDRQ<7\'d5 ? 7\'d5 : (REGDRQ>7\'d95 ? 7\'d95 : REGDRQ[6:0]);\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:217: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'REGSyncIQ\' generates 2 bits.\n                                                              : ... In instance LCD\n REG TBF(.Q(TBFQ), .L(1\'d1), .D( REGSyncIQ || L_IQ ||\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/411831376/LCD.v:217: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'REGSyncDQ\' generates 2 bits.\n                                                              : ... In instance LCD\n REG TBF(.Q(TBFQ), .L(1\'d1), .D( REGSyncIQ || L_IQ ||\n                                                   ^~\n%Error: data/full_repos/permissive/411831376/LCD.v:232: Cannot find file containing module: \'DDROM\'\n DDROM DDROM(.q(DDROMQ), .address(REGDRQ), .clock(CQ));\n ^~~~~\n%Error: data/full_repos/permissive/411831376/LCD.v:237: Cannot find file containing module: \'CGRAM\'\n CGRAM CGRAM(.q(CGRAMQ), .wraddress(CTCGRAMQ), .data(REGDRQ), .wren(TSelRAMQ & WR_CGRAMY), .rdaddress(REGDRQ[2:0]),\n ^~~~~\n%Error: data/full_repos/permissive/411831376/LCD.v:260: Cannot find file containing module: \'DDRAM\'\n DDRAM DDRAMUp( .q_a(DDRAMUpQa), .address_a(ACQ[5:0] ), .data_a(DataY), .wren_a(WR_DDRAMUpY), .clock_a(CQ),\n ^~~~~\n%Error: data/full_repos/permissive/411831376/LCD.v:262: Cannot find file containing module: \'DDRAM\'\n DDRAM DDRAMDw( .q_a(DDRAMDwQa), .address_a(ACQ[5:0] ), .data_a(DataY), .wren_a(WR_DDRAMDwY), .clock_a(CQ),\n ^~~~~\n%Error: data/full_repos/permissive/411831376/LCD.v:343: Cannot find file containing module: \'Futaba\'\n Futaba Futaba( .TCLKQ(FutabaCLKQ),\n ^~~~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module REG #(parameter N = 1) (output reg [N-1:0]Q = 0, input L, input [N-1:0]D, input C, aR);
	always @(posedge C or posedge aR)
									if(aR) Q <= 0;
										else
		if(L) Q <= D;
endmodule
module REG #(parameter N = 1) (output reg [N-1:0]Q = 0, input L, input [N-1:0]D, input C, aR);

	always @(posedge C or posedge aR)
									if(aR) Q <= 0;
										else
		if(L) Q <= D;
endmodule