data/full_repos/permissive/472097485/Chu03/Int2Flt_05/Int2Flt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/Int2Flt_05/Int2Flt.v:19: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                  : ... In instance Int2Flt\n  7\'b0000000 : r[11:0] = { 4\'b0000, 7\'b0000000 };\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Int2Flt( input [7:0] a, output reg [12:0] r );

always @*
begin
	r[12] = a[7];
	casez( a[6:0] )
		7'b1?????? : r[11:0] = { 4'b0111, a[6:0], 1'b0 };
		7'b01????? : r[11:0] = { 4'b0110, a[5:0], 2'b00 };
		7'b001???? : r[11:0] = { 4'b0101, a[4:0], 3'b000 };
		7'b0001??? : r[11:0] = { 4'b0100, a[3:0], 4'b0000 };
		7'b00001?? : r[11:0] = { 4'b0011, a[2:0], 5'b00000 };
		7'b000001? : r[11:0] = { 4'b0010, a[1:0], 6'b000000 };
		7'b0000001 : r[11:0] = { 4'b0001, a[0:0], 7'b0000000 };
		7'b0000000 : r[11:0] = { 4'b0000, 7'b0000000 };
	endcase
end

endmodule
module Int2Flt( input [7:0] a, output reg [12:0] r );


always @*
begin
	r[12] = a[7];
	casez( a[6:0] )
		7'b1?????? : r[11:0] = { 4'b0111, a[6:0], 1'b0 };
		7'b01????? : r[11:0] = { 4'b0110, a[5:0], 2'b00 };
		7'b001???? : r[11:0] = { 4'b0101, a[4:0], 3'b000 };
		7'b0001??? : r[11:0] = { 4'b0100, a[3:0], 4'b0000 };
		7'b00001?? : r[11:0] = { 4'b0011, a[2:0], 5'b00000 };
		7'b000001? : r[11:0] = { 4'b0010, a[1:0], 6'b000000 };
		7'b0000001 : r[11:0] = { 4'b0001, a[0:0], 7'b0000000 };
		7'b0000000 : r[11:0] = { 4'b0000, 7'b0000000 };
	endcase
end

endmodule