data/full_repos/permissive/516180498/al_ip/bram_frame.v
1: b"%Error: data/full_repos/permissive/516180498/al_ip/bram_frame.v:33: Cannot find file containing module: 'EG_LOGIC_BRAM'\n EG_LOGIC_BRAM #( .DATA_WIDTH_A(DATA_WIDTH_A),\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516180498/al_ip,data/full_repos/permissive/516180498/EG_LOGIC_BRAM\n             data/full_repos/permissive/516180498/al_ip,data/full_repos/permissive/516180498/EG_LOGIC_BRAM.v\n             data/full_repos/permissive/516180498/al_ip,data/full_repos/permissive/516180498/EG_LOGIC_BRAM.sv\n             EG_LOGIC_BRAM\n             EG_LOGIC_BRAM.v\n             EG_LOGIC_BRAM.sv\n             obj_dir/EG_LOGIC_BRAM\n             obj_dir/EG_LOGIC_BRAM.v\n             obj_dir/EG_LOGIC_BRAM.sv\n%Error: Exiting due to 1 error(s)\n"
module bram_frame ( doa, dia, addra, cea, clka, wea );

	output [129:0] doa;

	input  [129:0] dia;
	input  [6:0] addra;
	input  wea;
	input  cea;
	input  clka;



	parameter DATA_WIDTH_A = 130; 
	parameter ADDR_WIDTH_A = 7;
	parameter DATA_DEPTH_A = 66;
	parameter DATA_WIDTH_B = 130;
	parameter ADDR_WIDTH_B = 7;
	parameter DATA_DEPTH_B = 66;

	EG_LOGIC_BRAM #( .DATA_WIDTH_A(DATA_WIDTH_A),
				.ADDR_WIDTH_A(ADDR_WIDTH_A),
				.DATA_DEPTH_A(DATA_DEPTH_A),
				.DATA_WIDTH_B(DATA_WIDTH_B),
				.ADDR_WIDTH_B(ADDR_WIDTH_B),
				.DATA_DEPTH_B(DATA_DEPTH_B),
				.MODE("SP"),
				.REGMODE_A("NOREG"),
				.WRITEMODE_A("NORMAL"),
				.RESETMODE("SYNC"),
				.IMPLEMENT("9K"),
				.DEBUGGABLE("NO"),
				.PACKABLE("NO"),
				.INIT_FILE("NONE"),
				.FILL_ALL("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"))
			inst(
				.dia(dia),
				.dib({130{1'b0}}),
				.addra(addra),
				.addrb({7{1'b0}}),
				.cea(cea),
				.ceb(1'b0),
				.ocea(1'b0),
				.oceb(1'b0),
				.clka(clka),
				.clkb(1'b0),
				.wea(wea),
				.web(1'b0),
				.bea(1'b0),
				.beb(1'b0),
				.rsta(1'b0),
				.rstb(1'b0),
				.doa(doa),
				.dob());


endmodule
module bram_frame ( doa, dia, addra, cea, clka, wea );


	output [129:0] doa;

	input  [129:0] dia;
	input  [6:0] addra;
	input  wea;
	input  cea;
	input  clka;



	parameter DATA_WIDTH_A = 130; 
	parameter ADDR_WIDTH_A = 7;
	parameter DATA_DEPTH_A = 66;
	parameter DATA_WIDTH_B = 130;
	parameter ADDR_WIDTH_B = 7;
	parameter DATA_DEPTH_B = 66;

	EG_LOGIC_BRAM #( .DATA_WIDTH_A(DATA_WIDTH_A),
				.ADDR_WIDTH_A(ADDR_WIDTH_A),
				.DATA_DEPTH_A(DATA_DEPTH_A),
				.DATA_WIDTH_B(DATA_WIDTH_B),
				.ADDR_WIDTH_B(ADDR_WIDTH_B),
				.DATA_DEPTH_B(DATA_DEPTH_B),
				.MODE("SP"),
				.REGMODE_A("NOREG"),
				.WRITEMODE_A("NORMAL"),
				.RESETMODE("SYNC"),
				.IMPLEMENT("9K"),
				.DEBUGGABLE("NO"),
				.PACKABLE("NO"),
				.INIT_FILE("NONE"),
				.FILL_ALL("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"))
			inst(
				.dia(dia),
				.dib({130{1'b0}}),
				.addra(addra),
				.addrb({7{1'b0}}),
				.cea(cea),
				.ceb(1'b0),
				.ocea(1'b0),
				.oceb(1'b0),
				.clka(clka),
				.clkb(1'b0),
				.wea(wea),
				.web(1'b0),
				.bea(1'b0),
				.beb(1'b0),
				.rsta(1'b0),
				.rstb(1'b0),
				.doa(doa),
				.dob());


endmodule