data/full_repos/permissive/494305189/log/log.v
data/verilator_xmls/60be768c-8513-4552-a461-e86533567edd.xml
module log(input clk, rst, input[6:0] a, output reg[6:0] result);
	reg[6:0] buffer, count;
	reg finish;
	always @(posedge clk) begin
		if (rst) begin
			finish <= 0;
			result <= 0;
			buffer <= 0;
			count <= 0;
		end
		else if (finish == 0) begin
			if (a <= 1) begin
				result <= 0;
				finish <= 1;
			end
			if (count == 0) begin
				buffer <= a;
				count <= count + 1;
			end
			else if (buffer >= 2) begin
				buffer <= buffer / 2;
				count <= count + 1;
			end
			else begin
				result <= count - 1;
				finish <= 1;
			end
		end
	end
endmodule
module log(input clk, rst, input[6:0] a, output reg[6:0] result);

	reg[6:0] buffer, count;
	reg finish;
	always @(posedge clk) begin
		if (rst) begin
			finish <= 0;
			result <= 0;
			buffer <= 0;
			count <= 0;
		end
		else if (finish == 0) begin
			if (a <= 1) begin
				result <= 0;
				finish <= 1;
			end
			if (count == 0) begin
				buffer <= a;
				count <= count + 1;
			end
			else if (buffer >= 2) begin
				buffer <= buffer / 2;
				count <= count + 1;
			end
			else begin
				result <= count - 1;
				finish <= 1;
			end
		end
	end
endmodule