data/full_repos/permissive/460328193/ipa_proj_pipe/execute.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/execute.v:1: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: Exiting due to 1 error(s)\n'
module execute(icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);


input [3:0] icode;
input [3:0] ifun;
input [63:0] valC;
input [63:0] valA;
input [63:0] valB;
input clock;
output reg [63:0] valE;
output reg Cnd=1'b0;
input [2:0]cc;

reg [63:0] aluA, aluB;
wire [63:0] alu_out;
reg [1:0] alufun;
wire overflow;

output reg [2:0]new_cc=3'b0;
reg ZF,SF,OF;
output reg set_cc=1'b0;

alu ALU(alufun,aluA,aluB,alu_out,overflow);
always @(*)    
begin
	ZF<=cc[0];
	SF<=cc[1];
	OF<=cc[2];
    if(icode==4'h2)
	begin
        alufun<=2'b00;
		aluA<=valA;
        aluB<=64'b0;
	end
	else if(icode==4'h3)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=64'b0;
	end
	else if(icode==4'h4)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=valB;
	end	
	else if(icode==4'h5)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=valB;
	end
	else if(icode==4'h6)
	begin
        alufun<=ifun[1:0];
		aluA<=valA;
        aluB<=valB;
		set_cc<=1'b1;
	end
	else if(icode==4'h8)
	begin
        alufun<=2'b00;
		aluA<=-64'h8;
        aluB<=valB;
	end
	else if(icode==4'h9)
	begin
        alufun<=2'b00;
		aluA<=64'h8;
        aluB<=valB;
	end
	else if(icode==4'hA)
	begin
        alufun<=2'b00;
		aluA<=-64'h8;
        aluB<=valB;
	end
	else if(icode==4'hB)
	begin
        alufun<=2'b00;
		aluA<=64'h8;
        aluB<=valB;
	end
	valE<=alu_out;
	if(icode==4'h2 || icode==4'h7)
	begin
		if(ifun==4'h0)
			Cnd=1'b1;
		else if(ifun==4'h1)
			Cnd=((SF^OF)|ZF);
		else if(ifun==4'h2)
			Cnd=SF^OF;
		else if(ifun==4'h3)
			Cnd<=ZF;
		else if(ifun==4'h4)
			Cnd=~ZF;
		else if(ifun==4'h5)
			Cnd=(~SF^OF);
		else if(ifun==4'h6)
			Cnd=((~SF^OF)&~ZF);
	end
	if(set_cc==1'b1)
    begin
		if(valE==0)
			new_cc[0]<=1'b1;
		else
			new_cc[0]<=1'b0;
		new_cc[1]<=valE[63];
		new_cc[2]<=overflow;
    end
end

endmodule
module execute(icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);



input [3:0] icode;
input [3:0] ifun;
input [63:0] valC;
input [63:0] valA;
input [63:0] valB;
input clock;
output reg [63:0] valE;
output reg Cnd=1'b0;
input [2:0]cc;

reg [63:0] aluA, aluB;
wire [63:0] alu_out;
reg [1:0] alufun;
wire overflow;

output reg [2:0]new_cc=3'b0;
reg ZF,SF,OF;
output reg set_cc=1'b0;

alu ALU(alufun,aluA,aluB,alu_out,overflow);
always @(*)    
begin
	ZF<=cc[0];
	SF<=cc[1];
	OF<=cc[2];
    if(icode==4'h2)
	begin
        alufun<=2'b00;
		aluA<=valA;
        aluB<=64'b0;
	end
	else if(icode==4'h3)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=64'b0;
	end
	else if(icode==4'h4)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=valB;
	end	
	else if(icode==4'h5)
	begin
        alufun<=2'b00;
		aluA<=valC;
        aluB<=valB;
	end
	else if(icode==4'h6)
	begin
        alufun<=ifun[1:0];
		aluA<=valA;
        aluB<=valB;
		set_cc<=1'b1;
	end
	else if(icode==4'h8)
	begin
        alufun<=2'b00;
		aluA<=-64'h8;
        aluB<=valB;
	end
	else if(icode==4'h9)
	begin
        alufun<=2'b00;
		aluA<=64'h8;
        aluB<=valB;
	end
	else if(icode==4'hA)
	begin
        alufun<=2'b00;
		aluA<=-64'h8;
        aluB<=valB;
	end
	else if(icode==4'hB)
	begin
        alufun<=2'b00;
		aluA<=64'h8;
        aluB<=valB;
	end
	valE<=alu_out;
	if(icode==4'h2 || icode==4'h7)
	begin
		if(ifun==4'h0)
			Cnd=1'b1;
		else if(ifun==4'h1)
			Cnd=((SF^OF)|ZF);
		else if(ifun==4'h2)
			Cnd=SF^OF;
		else if(ifun==4'h3)
			Cnd<=ZF;
		else if(ifun==4'h4)
			Cnd=~ZF;
		else if(ifun==4'h5)
			Cnd=(~SF^OF);
		else if(ifun==4'h6)
			Cnd=((~SF^OF)&~ZF);
	end
	if(set_cc==1'b1)
    begin
		if(valE==0)
			new_cc[0]<=1'b1;
		else
			new_cc[0]<=1'b0;
		new_cc[1]<=valE[63];
		new_cc[2]<=overflow;
    end
end

endmodule