data/full_repos/permissive/496508301/Lesson4/counter/counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #20     res<=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #6000   $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:38: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("conv_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson4/counter/counter.v:39: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module con_tb;
reg         clk, res;
wire[7:0]   y;
con con(
    .clk(clk),
    .res(res),
    .y(y)
);
initial begin
            clk <= 0; res <= 0;
    #20     res<=1;
    #6000   $stop;
end
always #5 clk=~clk;

initial begin
    $dumpfile("conv_tb.vcd");
    $dumpvars;
end
endmodule
module con_tb;

reg         clk, res;
wire[7:0]   y;
con con(
    .clk(clk),
    .res(res),
    .y(y)
);
initial begin
            clk <= 0; res <= 0;
    #20     res<=1;
    #6000   $stop;
end
always #5 clk=~clk;

initial begin
    $dumpfile("conv_tb.vcd");
    $dumpvars;
end
endmodule