data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pulp_clock_and2.sv
data/verilator_xmls/2fa8d0fb-c879-4ee0-964c-e459469d54f1.xml
module pulp_clock_and2
(
    input  logic clk0_i,
    input  logic clk1_i,
    output logic clk_o
);

   assign clk_o = clk0_i & clk1_i;

endmodule
module pulp_clock_and2
(
    input  logic clk0_i,
    input  logic clk1_i,
    output logic clk_o
);


   assign clk_o = clk0_i & clk1_i;

endmodule