data/full_repos/permissive/529457593/Sprint10/frequencyDivider.v
data/verilator_xmls/59da9451-8cfa-48f2-b653-524ae03953a5.xml
module frequencyDivider (input clock50M, input [25:0] divider, output reg clock1);

	reg[25:0] count = 26'd0;

	always @ (posedge clock50M) begin
		count <= count + 26'd1;
		clock1 = (count > (divider/2)) ? 1'b0 : 1'b1;

		if(count > (divider-1))
			count <= 26'd0;
	end

endmodule
module frequencyDivider (input clock50M, input [25:0] divider, output reg clock1);


	reg[25:0] count = 26'd0;

	always @ (posedge clock50M) begin
		count <= count + 26'd1;
		clock1 = (count > (divider/2)) ? 1'b0 : 1'b1;

		if(count > (divider-1))
			count <= 26'd0;
	end

endmodule