data/full_repos/permissive/434840709/作业/组合电路1/cg.v
data/verilator_xmls/7935931b-e954-45fa-ae4f-ae78aea9db77.xml
module top_module (

        input a,

        input b,

        output q );

assign q = a&b;


endmodule
module top_module (

        input a,

        input b,

        output q );


assign q = a&b;


endmodule