data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:83: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][7:0]   <= data0_i[7:0];\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:85: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][15:8]  <= data0_i[15:8];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:87: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][23:16] <= data0_i[23:16];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:89: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][31:24] <= data0_i[31:24];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:91: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][39:32] <= data0_i[39:32];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:93: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][47:40] <= data0_i[47:40];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:95: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][55:48] <= data0_i[55:48];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:97: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr0_i][63:56] <= data0_i[63:56];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:99: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                       : ... In instance tcm_mem_ram\n            ram[addr1_i][7:0]   <= data1_i[7:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:101: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][15:8]  <= data1_i[15:8];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:103: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][23:16] <= data1_i[23:16];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:105: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][31:24] <= data1_i[31:24];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:107: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][39:32] <= data1_i[39:32];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:109: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][47:40] <= data1_i[47:40];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:111: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][55:48] <= data1_i[55:48];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:113: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n            ram[addr1_i][63:56] <= data1_i[63:56];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:128: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n        ram_read0_q <= ram[addr0_i];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/524616929/tb/tb_core_icarus/tcm_mem_ram.v:129: Bit extraction of array[63:0] requires 6 bit index, not 14 bits.\n                                                                                        : ... In instance tcm_mem_ram\n        ram_read1_q <= ram[addr1_i];\n                          ^\n%Error: Exiting due to 18 warning(s)\n'
module tcm_mem_ram
(

     input           clk
    ,input           rst_n
    
    ,input  [ 13:0]  addr0_i
    ,input  [ 63:0]  data0_i
    ,input  [  7:0]  wr0_i

    ,input  [ 13:0]  addr1_i
    ,input  [ 63:0]  data1_i
    ,input  [  7:0]  wr1_i


    ,output [ 63:0]  data0_o
    ,output [ 63:0]  data1_o
);








reg [63:0]   ram [63:0];


reg [63:0] ram_read0_q;
reg [63:0] ram_read1_q;





always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin


        ram[0][31:0]    <= 32'h01700313;
        ram[0][63:32]   <= 32'h01400393;
        ram[1][31:0]    <= 32'h00200413;
        ram[1][63:32]   <= 32'hfff00493;
        ram[2][31:0]    <= 32'hfe700513;
        ram[2][63:32]   <= 32'h01000593;
        ram[3][31:0]    <= 32'h00000613;
        ram[3][63:32]   <= 32'hff500693;
        ram[4][31:0]    <= 32'hffc00713;
        ram[4][63:32]   <= 32'h00700793;
        ram[5][31:0]    <= 32'h00601023;
        ram[5][63:32]   <= 32'h00701123;
        ram[6][31:0]    <= 32'h00801223;
        ram[6][63:32]   <= 32'h00901323;
        ram[7][31:0]    <= 32'h00a01423;
        ram[7][63:32]   <= 32'h00b01523;
        ram[8][31:0]    <= 32'h00c01623;
        ram[8][63:32]   <= 32'h00d01723;
        ram[9][31:0]    <= 32'h00e01823;
        ram[9][63:32]   <= 32'h00f01923;
        ram[10][31:0]   <= 32'h01200113;
        ram[10][63:32]  <= 32'h00000193;
        ram[11][31:0]   <= 32'h00015463;
        ram[11][63:32]  <= 32'h090000e7;
        ram[12][31:0]   <= 32'h0021a233;
        ram[12][63:32]  <= 32'h02020063;
        ram[13][31:0]   <= 32'h00019283;
        ram[13][63:32]  <= 32'h00219303;
        ram[14][31:0]   <= 32'h0062c663;
        ram[14][63:32]  <= 32'h00619023;
        ram[15][31:0]   <= 32'h00519123;
        ram[15][63:32]  <= 32'h00218193;
        ram[16][31:0]   <= 32'hfe1ff0ef;
        ram[16][63:32]  <= 32'h00000193;
        ram[17][31:0]   <= 32'hffe10113;
        ram[17][63:32]  <= 32'hfcdff0ef;
        ram[18][31:0]   <= 32'h090000e7;
    end

    else begin
        if (wr0_i[0])
            ram[addr0_i][7:0]   <= data0_i[7:0];
        if (wr0_i[1])
            ram[addr0_i][15:8]  <= data0_i[15:8];
        if (wr0_i[2])
            ram[addr0_i][23:16] <= data0_i[23:16];
        if (wr0_i[3])
            ram[addr0_i][31:24] <= data0_i[31:24];
        if (wr0_i[4])
            ram[addr0_i][39:32] <= data0_i[39:32];
        if (wr0_i[5])
            ram[addr0_i][47:40] <= data0_i[47:40];
        if (wr0_i[6])
            ram[addr0_i][55:48] <= data0_i[55:48];
        if (wr0_i[7])
            ram[addr0_i][63:56] <= data0_i[63:56];
        if (wr1_i[0])
            ram[addr1_i][7:0]   <= data1_i[7:0];
        if (wr1_i[1])
            ram[addr1_i][15:8]  <= data1_i[15:8];
        if (wr1_i[2])
            ram[addr1_i][23:16] <= data1_i[23:16];
        if (wr1_i[3])
            ram[addr1_i][31:24] <= data1_i[31:24];
        if (wr1_i[4])
            ram[addr1_i][39:32] <= data1_i[39:32];
        if (wr1_i[5])
            ram[addr1_i][47:40] <= data1_i[47:40];
        if (wr1_i[6])
            ram[addr1_i][55:48] <= data1_i[55:48];
        if (wr1_i[7])
            ram[addr1_i][63:56] <= data1_i[63:56];
    end
end




always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        ram_read0_q <=  0;
        ram_read1_q <=  0;
    end

    else begin
        ram_read0_q <= ram[addr0_i];
        ram_read1_q <= ram[addr1_i];
    end
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;



endmodule
module tcm_mem_ram
(

     input           clk
    ,input           rst_n
    
    ,input  [ 13:0]  addr0_i
    ,input  [ 63:0]  data0_i
    ,input  [  7:0]  wr0_i

    ,input  [ 13:0]  addr1_i
    ,input  [ 63:0]  data1_i
    ,input  [  7:0]  wr1_i


    ,output [ 63:0]  data0_o
    ,output [ 63:0]  data1_o
);









reg [63:0]   ram [63:0];


reg [63:0] ram_read0_q;
reg [63:0] ram_read1_q;





always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin


        ram[0][31:0]    <= 32'h01700313;
        ram[0][63:32]   <= 32'h01400393;
        ram[1][31:0]    <= 32'h00200413;
        ram[1][63:32]   <= 32'hfff00493;
        ram[2][31:0]    <= 32'hfe700513;
        ram[2][63:32]   <= 32'h01000593;
        ram[3][31:0]    <= 32'h00000613;
        ram[3][63:32]   <= 32'hff500693;
        ram[4][31:0]    <= 32'hffc00713;
        ram[4][63:32]   <= 32'h00700793;
        ram[5][31:0]    <= 32'h00601023;
        ram[5][63:32]   <= 32'h00701123;
        ram[6][31:0]    <= 32'h00801223;
        ram[6][63:32]   <= 32'h00901323;
        ram[7][31:0]    <= 32'h00a01423;
        ram[7][63:32]   <= 32'h00b01523;
        ram[8][31:0]    <= 32'h00c01623;
        ram[8][63:32]   <= 32'h00d01723;
        ram[9][31:0]    <= 32'h00e01823;
        ram[9][63:32]   <= 32'h00f01923;
        ram[10][31:0]   <= 32'h01200113;
        ram[10][63:32]  <= 32'h00000193;
        ram[11][31:0]   <= 32'h00015463;
        ram[11][63:32]  <= 32'h090000e7;
        ram[12][31:0]   <= 32'h0021a233;
        ram[12][63:32]  <= 32'h02020063;
        ram[13][31:0]   <= 32'h00019283;
        ram[13][63:32]  <= 32'h00219303;
        ram[14][31:0]   <= 32'h0062c663;
        ram[14][63:32]  <= 32'h00619023;
        ram[15][31:0]   <= 32'h00519123;
        ram[15][63:32]  <= 32'h00218193;
        ram[16][31:0]   <= 32'hfe1ff0ef;
        ram[16][63:32]  <= 32'h00000193;
        ram[17][31:0]   <= 32'hffe10113;
        ram[17][63:32]  <= 32'hfcdff0ef;
        ram[18][31:0]   <= 32'h090000e7;
    end

    else begin
        if (wr0_i[0])
            ram[addr0_i][7:0]   <= data0_i[7:0];
        if (wr0_i[1])
            ram[addr0_i][15:8]  <= data0_i[15:8];
        if (wr0_i[2])
            ram[addr0_i][23:16] <= data0_i[23:16];
        if (wr0_i[3])
            ram[addr0_i][31:24] <= data0_i[31:24];
        if (wr0_i[4])
            ram[addr0_i][39:32] <= data0_i[39:32];
        if (wr0_i[5])
            ram[addr0_i][47:40] <= data0_i[47:40];
        if (wr0_i[6])
            ram[addr0_i][55:48] <= data0_i[55:48];
        if (wr0_i[7])
            ram[addr0_i][63:56] <= data0_i[63:56];
        if (wr1_i[0])
            ram[addr1_i][7:0]   <= data1_i[7:0];
        if (wr1_i[1])
            ram[addr1_i][15:8]  <= data1_i[15:8];
        if (wr1_i[2])
            ram[addr1_i][23:16] <= data1_i[23:16];
        if (wr1_i[3])
            ram[addr1_i][31:24] <= data1_i[31:24];
        if (wr1_i[4])
            ram[addr1_i][39:32] <= data1_i[39:32];
        if (wr1_i[5])
            ram[addr1_i][47:40] <= data1_i[47:40];
        if (wr1_i[6])
            ram[addr1_i][55:48] <= data1_i[55:48];
        if (wr1_i[7])
            ram[addr1_i][63:56] <= data1_i[63:56];
    end
end




always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        ram_read0_q <=  0;
        ram_read1_q <=  0;
    end

    else begin
        ram_read0_q <= ram[addr0_i];
        ram_read1_q <= ram[addr1_i];
    end
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;



endmodule