data/full_repos/permissive/493441306/Verilog Language/procedures/01_alwaysblock2.v
1: b'%Error: Cannot find file containing module: Language/procedures,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.sv\n             Language/procedures,data/full_repos/permissive/493441306\n             Language/procedures,data/full_repos/permissive/493441306.v\n             Language/procedures,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.v\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/procedures/01_alwaysblock2.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign = a ^ b;
    
    always@(*) 
        out_always_comb = out_assign;
    
    always@( posedge clk )
        out_always_ff <= out_assign;

endmodule
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );

    
    assign out_assign = a ^ b;
    
    always@(*) 
        out_always_comb = out_assign;
    
    always@( posedge clk )
        out_always_ff <= out_assign;

endmodule