data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_rcv_dc.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_rcv_dc.v:31: syntax error, unexpected ',', expecting '['\n  pad, ref, vddo\n          ^\n%Error: Exiting due to 1 error(s)\n"
module bw_io_dtl_rcv_dc (

  so, 

  pad, ref, vddo
  );

  output	so;
  input		pad;
  input		ref;
  input		vddo;


  assign so = pad ;


  endmodule
module bw_io_dtl_rcv_dc (

  so, 

  pad, ref, vddo
  );


  output	so;
  input		pad;
  input		ref;
  input		vddo;


  assign so = pad ;


  endmodule