data/full_repos/permissive/420117502/Environment_Test/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420117502/Environment_Test/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk<=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420117502/Environment_Test/tb.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("./dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/420117502/Environment_Test/tb.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Environment_Test/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        # 2 a<=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Environment_Test/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        # 2 b<=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Environment_Test/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        # 2 a<=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Environment_Test/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        # 2\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (
);
    reg clk;
    reg a;
    reg b;
    wire sum;
    wire carry;
    HalfAdder ha(
        .a(a),
        .b(b),
        .sum(sum),
        .carry(carry)
    );
    always #1 clk<=~clk;
    initial begin
        $dumpfile("./dumpfile.vcd");
        $dumpvars;
        clk<=1'b1;
        a<=1'b1;
        b<=1'b1;
        # 2 a<=1'b0;
        # 2 b<=1'b0;
        # 2 a<=1'b1;
        # 2
        $finish;
    end

endmodule
module tb (
);

    reg clk;
    reg a;
    reg b;
    wire sum;
    wire carry;
    HalfAdder ha(
        .a(a),
        .b(b),
        .sum(sum),
        .carry(carry)
    );
    always #1 clk<=~clk;
    initial begin
        $dumpfile("./dumpfile.vcd");
        $dumpvars;
        clk<=1'b1;
        a<=1'b1;
        b<=1'b1;
        # 2 a<=1'b0;
        # 2 b<=1'b0;
        # 2 a<=1'b1;
        # 2
        $finish;
    end

endmodule