data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/int_test.v
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/int_test.v:5: Cannot find file containing module: 'RAMB4_S16'\nRAMB4_S16 ram_256_x_16(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/RAMB4_S16\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/RAMB4_S16.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/RAMB4_S16.sv\n             RAMB4_S16\n             RAMB4_S16.v\n             RAMB4_S16.sv\n             obj_dir/RAMB4_S16\n             obj_dir/RAMB4_S16.v\n             obj_dir/RAMB4_S16.sv\n%Error: Exiting due to 1 error(s)\n"
module int_test(address, instruction, clk);
input [7:0] address;
output [15:0] instruction;
input clk;
RAMB4_S16 ram_256_x_16(
	.DI  (16'b0),
	.EN (1'b1),
	.WE (1'b0),
	.RST (1'b0),
	.CLK (clk),
	.ADDR(address),
	.DO (instruction)
);

defparam ram_256_x_16.INIT_00 = 256'h0000000000000000000000000000810332FF950560010007E202803002AA0A00;
defparam ram_256_x_16.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0B = 256'h000000000000000000000000000000000000000000000000000080F0EA044A01;
defparam ram_256_x_16.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0F = 256'h81B0000000000000000000000000000000000000000000000000000000000000;

















endmodule
module int_test(address, instruction, clk);

input [7:0] address;
output [15:0] instruction;
input clk;
RAMB4_S16 ram_256_x_16(
	.DI  (16'b0),
	.EN (1'b1),
	.WE (1'b0),
	.RST (1'b0),
	.CLK (clk),
	.ADDR(address),
	.DO (instruction)
);

defparam ram_256_x_16.INIT_00 = 256'h0000000000000000000000000000810332FF950560010007E202803002AA0A00;
defparam ram_256_x_16.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0B = 256'h000000000000000000000000000000000000000000000000000080F0EA044A01;
defparam ram_256_x_16.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam ram_256_x_16.INIT_0F = 256'h81B0000000000000000000000000000000000000000000000000000000000000;

















endmodule