data/full_repos/permissive/493851698/verilog/gl/my_alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/gl/my_alu.v:20: Operator AND expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                           : ... In instance my_alu\n                                ALU_Result = A & B;\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/gl/my_alu.v:20: Operator AND expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                           : ... In instance my_alu\n                                ALU_Result = A & B;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/gl/my_alu.v:22: Operator OR expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                           : ... In instance my_alu\n                        ALU_Result = A | B;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/gl/my_alu.v:22: Operator OR expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                           : ... In instance my_alu\n                        ALU_Result = A | B;\n                                       ^\n%Error: Exiting due to 4 warning(s)\n'
module my_alu(
        input [7:0] A,B,
        input [1:0] ALU_Sel,
        output [7:0] ALU_Out,
                output CarryOut
        );
        reg [8:0] ALU_Result;

        assign ALU_Out = ALU_Result[7:0];
        assign CarryOut = ALU_Result[8];

        always @(*)
        begin
                case(ALU_Sel)
                        2'b00:
                                ALU_Result = A + B ;
                        2'b01:
                                ALU_Result = A - B ;
                        2'b10:
                                ALU_Result = A & B;
                        2'b11:
                        ALU_Result = A | B;

                default: ALU_Result = A + B ;
        endcase
end

endmodule
module my_alu(
        input [7:0] A,B,
        input [1:0] ALU_Sel,
        output [7:0] ALU_Out,
                output CarryOut
        );

        reg [8:0] ALU_Result;

        assign ALU_Out = ALU_Result[7:0];
        assign CarryOut = ALU_Result[8];

        always @(*)
        begin
                case(ALU_Sel)
                        2'b00:
                                ALU_Result = A + B ;
                        2'b01:
                                ALU_Result = A - B ;
                        2'b10:
                                ALU_Result = A & B;
                        2'b11:
                        ALU_Result = A | B;

                default: ALU_Result = A + B ;
        endcase
end

endmodule