data/full_repos/permissive/413230008/Seven-Segment Display Driver/Code/Sources/first_sseg_driver_test.v
1: b'%Error: Cannot find file containing module: Display\n        ... Looked in:\n             data/full_repos/permissive/413230008/Seven-Segment/Display\n             data/full_repos/permissive/413230008/Seven-Segment/Display.v\n             data/full_repos/permissive/413230008/Seven-Segment/Display.sv\n             Display\n             Display.v\n             Display.sv\n             obj_dir/Display\n             obj_dir/Display.v\n             obj_dir/Display.sv\n%Error: Cannot find file containing module: Driver/Code/Sources,data/full_repos/permissive/413230008\n%Error: Cannot find file containing module: data/full_repos/permissive/413230008/Seven-Segment\n%Error: Cannot find file containing module: Driver/Code/Sources/first_sseg_driver_test.v\n%Error: Exiting due to 4 error(s)\n'
module first_sseg_driver_test(

        input dp_ctrl,
        input clk,



        output DP,
        output [6:0] sseg,
        output [7:0] AN


        );
        wire done;
        wire [2:0] counter_result;
        wire [3:0] temp;

        assign temp = {0, counter_result[2:0]};
        

        timer_input (
            .clk(clk),
            .reset_n(1'b0),
            .enable(1'b1),
            .FINAL_VALUE(1000),
            .done(done)
        );
        
        udl_counter (
            .clk(clk),
            .reset_n(1'b0),
            .enable(done),
            .up(1'b1),
            .load(1'b0),
            .D(3'b000),
            .Q(counter_result)
        );

        first_sseg_driver (
            .active_digit(temp),
            .num(counter_result),
            .dp_ctrl(1'b0),
            .sseg(sseg), 
            .AN(AN),
            .DP(DP)
        );
        
        



endmodule
module first_sseg_driver_test(

        input dp_ctrl,
        input clk,



        output DP,
        output [6:0] sseg,
        output [7:0] AN


        );

        wire done;
        wire [2:0] counter_result;
        wire [3:0] temp;

        assign temp = {0, counter_result[2:0]};
        

        timer_input (
            .clk(clk),
            .reset_n(1'b0),
            .enable(1'b1),
            .FINAL_VALUE(1000),
            .done(done)
        );
        
        udl_counter (
            .clk(clk),
            .reset_n(1'b0),
            .enable(done),
            .up(1'b1),
            .load(1'b0),
            .D(3'b000),
            .Q(counter_result)
        );

        first_sseg_driver (
            .active_digit(temp),
            .num(counter_result),
            .dp_ctrl(1'b0),
            .sseg(sseg), 
            .AN(AN),
            .DP(DP)
        );
        
        



endmodule