data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #2.5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v:40: Unsupported: fork statements\n  fork begin\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #0 clk = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #100 nrst = 1\'b1;\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_bmc_encoder.v:48: syntax error, unexpected \'@\'\n   @(posedge din_rdy)\n   ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_bmc_encoder;

	reg		clk;
	reg		nrst;
	reg		dut_data;
	
	wire	din_rdy;
	wire	dout;
	
	bmc_encoder#(
		.system_khz(200000)
	)DUT(
		.nrst	(nrst),
		.clock	(clk),
		.enable	(1'b1),
		.data	(dut_data),
		.rdy	(din_rdy),
		.dmc_q	(dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			dut_data = 1'b0;
			
			#100 nrst = 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
		end join
	end
	
endmodule
module tb_bmc_encoder;


	reg		clk;
	reg		nrst;
	reg		dut_data;
	
	wire	din_rdy;
	wire	dout;
	
	bmc_encoder#(
		.system_khz(200000)
	)DUT(
		.nrst	(nrst),
		.clock	(clk),
		.enable	(1'b1),
		.data	(dut_data),
		.rdy	(din_rdy),
		.dmc_q	(dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			dut_data = 1'b0;
			
			#100 nrst = 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
			@(posedge din_rdy)
			dut_data <= 1'b1;
			
			@(posedge din_rdy)
			dut_data <= 1'b0;
			
		end join
	end
	
endmodule