data/full_repos/permissive/409580086/design.v
data/verilator_xmls/e79e232f-5739-46b8-b826-cce31d35f28a.xml
module uart(input_stream,clock,output_stream);
  input input_stream,clock;
  output reg [7:0]output_stream;
  integer count;
  integer clocks_per_bit=0;
  





  localparam idle=0, start=1, receive=2, stop=3;
  reg [1:0] machine;
  
  always@(posedge clock) begin
    case(machine)
      idle: begin
        if(input_stream==0) machine<=start;
        else machine<=idle;
      end
      start: begin
        if(clocks_per_bit<(2605/2)) begin
          clocks_per_bit=clocks_per_bit+1;
          machine<=start;
        end
        else begin
          clocks_per_bit=0;
          machine<=receive;
        end
      end
      receive: begin
        if(count<8) begin
          if(clocks_per_bit<2605) begin
          	clocks_per_bit=clocks_per_bit+1;
            machine<=receive;
          end
          else begin
            output_stream[count]<=input_stream;
          	count=count+1;
            clocks_per_bit=0;
            machine<=receive;
          end
        end
        else begin
          count=0;
          clocks_per_bit=0;
          if(input_stream==1'b1) begin
          machine<=stop;
          end
          else begin
          	machine<=idle;
          end
        end
      end
      stop: begin
        if(clocks_per_bit<2605) begin
		  clocks_per_bit=clocks_per_bit+1;
          machine<=stop;
        end
        else begin
          machine<=idle;
        end
      end
      default: begin
        output_stream=8'b00000000;
        machine<=idle;
        count=0;
        clocks_per_bit=0;
      end
    endcase
  end
endmodule
module uart(input_stream,clock,output_stream);

  input input_stream,clock;
  output reg [7:0]output_stream;
  integer count;
  integer clocks_per_bit=0;
  





  localparam idle=0, start=1, receive=2, stop=3;
  reg [1:0] machine;
  
  always@(posedge clock) begin
    case(machine)
      idle: begin
        if(input_stream==0) machine<=start;
        else machine<=idle;
      end
      start: begin
        if(clocks_per_bit<(2605/2)) begin
          clocks_per_bit=clocks_per_bit+1;
          machine<=start;
        end
        else begin
          clocks_per_bit=0;
          machine<=receive;
        end
      end
      receive: begin
        if(count<8) begin
          if(clocks_per_bit<2605) begin
          	clocks_per_bit=clocks_per_bit+1;
            machine<=receive;
          end
          else begin
            output_stream[count]<=input_stream;
          	count=count+1;
            clocks_per_bit=0;
            machine<=receive;
          end
        end
        else begin
          count=0;
          clocks_per_bit=0;
          if(input_stream==1'b1) begin
          machine<=stop;
          end
          else begin
          	machine<=idle;
          end
        end
      end
      stop: begin
        if(clocks_per_bit<2605) begin
		  clocks_per_bit=clocks_per_bit+1;
          machine<=stop;
        end
        else begin
          machine<=idle;
        end
      end
      default: begin
        output_stream=8'b00000000;
        machine<=idle;
        count=0;
        clocks_per_bit=0;
      end
    endcase
  end
endmodule