data/full_repos/permissive/512649487/verilog/rtl/prediction.v
1: b"%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:86: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:87: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:201: syntax error, unexpected new, expecting IDENTIFIER or '=' or do or final\nreg [2:0] new;\n             ^\n%Error: data/full_repos/permissive/512649487/verilog/rtl/prediction.v:383: syntax error, unexpected new\nnew=temp;\n   ^\n%Error: Exiting due to 6 error(s)\n"
module prediction #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,








    output [31:0] wbs_dat_o,







    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out




);
    wire clk;



    
    
    wire [1:0] mat_sel;
    wire [1:0] adr;

    wire [20:0] w2;
    wire [2:0] decision;
    
    
    
    
    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;

    
    












    
    assign clk=wb_clk_i;



    assign mat_sel= io_in[26:25];
    assign adr=io_in[23:22];
    

    assign w2=io_in[20:0];



   

    assign io_out[31:29]=decision;
    assign wbs_dat_o = decision;
   
















    mul_matr #(
        .BITS(BITS)
    ) mul_matr(
        .clk(clk),



        .mat_sel(mat_sel),
        .adr(adr),

        .w2(w2),
        .decision(decision)



        




    );

endmodule
module prediction #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,








    output [31:0] wbs_dat_o,







    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out




);

    wire clk;



    
    
    wire [1:0] mat_sel;
    wire [1:0] adr;

    wire [20:0] w2;
    wire [2:0] decision;
    
    
    
    
    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;

    
    












    
    assign clk=wb_clk_i;



    assign mat_sel= io_in[26:25];
    assign adr=io_in[23:22];
    

    assign w2=io_in[20:0];



   

    assign io_out[31:29]=decision;
    assign wbs_dat_o = decision;
   
















    mul_matr #(
        .BITS(BITS)
    ) mul_matr(
        .clk(clk),



        .mat_sel(mat_sel),
        .adr(adr),

        .w2(w2),
        .decision(decision)



        




    );

endmodule