data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:49: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:50: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:67: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:75: Define or directive not defined: \'`SIG_CC_TUSER_W\'\n     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:87: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]                  TXC_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:88: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]                  TXC_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:89: Define or directive not defined: \'`SIG_LOWADDR_W\'\n     input [`SIG_LOWADDR_W-1:0]              TXC_META_ADDR,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:90: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]                 TXC_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:91: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]                  TXC_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:92: Define or directive not defined: \'`SIG_BYTECNT_W\'\n     input [`SIG_BYTECNT_W-1:0]              TXC_META_BYTE_COUNT,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:93: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]                  TXC_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:94: Define or directive not defined: \'`SIG_REQID_W\'\n     input [`SIG_REQID_W-1:0]                TXC_META_REQUESTER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:95: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]                   TXC_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:96: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]                 TXC_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:119: Define or directive not defined: \'`SIG_NONPAY_W\'\n    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:120: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:121: Define or directive not defined: \'`SIG_LEN_W\'\n    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:154: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:155: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:156: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:165: Define or directive not defined: \'`SIG_CPLID_W\'\n         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),\n                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:167: Define or directive not defined: \'`SIG_FBE_W\'\n         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:168: Define or directive not defined: \'`SIG_LBE_W\'\n         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:169: Define or directive not defined: \'`SIG_LOWADDR_W\'\n         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),\n                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:170: Define or directive not defined: \'`SIG_LEN_W\'\n         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:171: Define or directive not defined: \'`SIG_TYPE_W\'\n         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:172: Define or directive not defined: \'`SIG_BYTECNT_W\'\n         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),\n                                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:173: Define or directive not defined: \'`SIG_TAG_W\'\n         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:174: Define or directive not defined: \'`SIG_REQID_W\'\n         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),\n                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:175: Define or directive not defined: \'`SIG_TC_W\'\n         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:176: Define or directive not defined: \'`SIG_ATTR_W\'\n         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:206: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:207: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:208: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:236: Define or directive not defined: \'`SIG_CC_TUSER_W\'\n         .S_AXIS_CC_TUSER               (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:256: Define or directive not defined: \'`UPKT_TXC_MAXHDR_W\'\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W\n                                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:257: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      )\n      ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:266: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:270: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:271: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:272: Define or directive not defined: \'`SIG_LOWADDR_W\'\n     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:273: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:274: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:275: Define or directive not defined: \'`SIG_BYTECNT_W\'\n     input [`SIG_BYTECNT_W-1:0]    TXC_META_BYTE_COUNT,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:276: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]        TXC_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:277: Define or directive not defined: \'`SIG_REQID_W\'\n     input [`SIG_REQID_W-1:0]      TXC_META_REQUESTER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:278: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]         TXC_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:279: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]       TXC_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:286: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/txc_engine_ultrascale.v:287: Define or directive not defined: \'`SIG_NONPAY_W\'\n     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,\n             ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module txc_translation_layer
    #(
      parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 0
    
      )
    (

     input                                   CLK,


     input                                   RST_IN,


     output                                  TXC_PKT_READY,
     input [C_PCI_DATA_WIDTH-1:0]            TXC_PKT,
     input                                   TXC_PKT_VALID,
     input                                   TXC_PKT_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
     input                                   TXC_PKT_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,


     input                                   S_AXIS_CC_TREADY,
     output                                  S_AXIS_CC_TVALID,
     output                                  S_AXIS_CC_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_CC_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_CC_TKEEP,
     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER
     );

    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
    localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;

    wire                                     wTxcPktReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxcPkt;
    wire                                     wTxcPktValid;
    wire                                     wTxcPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktStartOffset;
    wire                                     wTxcPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktEndOffset;

    wire                                     wSAxisCcTReady;
    wire                                     wSAxisCcTValid;
    wire                                     wSAxisCcTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisCcTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisCcTKeep;
    wire [`SIG_CC_TUSER_W-1:0]               wSAxisCcTUser;


    assign wTxcPktReady = wSAxisCcTReady;
    assign wSAxisCcTValid = wTxcPktValid;
    assign wSAxisCcTLast = wTxcPktEndFlag;
    assign wSAxisCcTData = wTxcPkt;
    assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0;
    
    pipeline
        #(

          .C_DEPTH                         (C_INPUT_STAGES),
          .C_WIDTH                         (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (

         .WR_DATA_READY                  (TXC_PKT_READY),
         .RD_DATA                        ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
         .RD_DATA_VALID                  (wTxcPktValid),

         .WR_DATA                        ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
                                           TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
         .WR_DATA_VALID                  (TXC_PKT_VALID),
         .RD_DATA_READY                  (wTxcPktReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    offset_to_mask
        #(

          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    otom_inst
        (

         .MASK                          (wSAxisCcTKeep),

         .OFFSET_ENABLE                 (wTxcPktEndFlag),
         .OFFSET                        (wTxcPktEndOffset)
);
    
    pipeline
        #(

          .C_DEPTH                         (C_OUTPUT_STAGES),
          .C_WIDTH                         (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wSAxisCcTReady),
         .RD_DATA                        ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
         .RD_DATA_VALID                  (S_AXIS_CC_TVALID),

         .WR_DATA                        ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
         .WR_DATA_VALID                  (wSAxisCcTValid),
         .RD_DATA_READY                  (S_AXIS_CC_TREADY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

endmodule
module txc_translation_layer
    #(
      parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 0
    
      )
    (

     input                                   CLK,


     input                                   RST_IN,


     output                                  TXC_PKT_READY,
     input [C_PCI_DATA_WIDTH-1:0]            TXC_PKT,
     input                                   TXC_PKT_VALID,
     input                                   TXC_PKT_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
     input                                   TXC_PKT_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,


     input                                   S_AXIS_CC_TREADY,
     output                                  S_AXIS_CC_TVALID,
     output                                  S_AXIS_CC_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_CC_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_CC_TKEEP,
     output [`SIG_CC_TUSER_W-1:0]            S_AXIS_CC_TUSER
     );


    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
    localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;

    wire                                     wTxcPktReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxcPkt;
    wire                                     wTxcPktValid;
    wire                                     wTxcPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktStartOffset;
    wire                                     wTxcPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxcPktEndOffset;

    wire                                     wSAxisCcTReady;
    wire                                     wSAxisCcTValid;
    wire                                     wSAxisCcTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisCcTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisCcTKeep;
    wire [`SIG_CC_TUSER_W-1:0]               wSAxisCcTUser;


    assign wTxcPktReady = wSAxisCcTReady;
    assign wSAxisCcTValid = wTxcPktValid;
    assign wSAxisCcTLast = wTxcPktEndFlag;
    assign wSAxisCcTData = wTxcPkt;
    assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0;
    
    pipeline
        #(

          .C_DEPTH                         (C_INPUT_STAGES),
          .C_WIDTH                         (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (

         .WR_DATA_READY                  (TXC_PKT_READY),
         .RD_DATA                        ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
         .RD_DATA_VALID                  (wTxcPktValid),

         .WR_DATA                        ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
                                           TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
         .WR_DATA_VALID                  (TXC_PKT_VALID),
         .RD_DATA_READY                  (wTxcPktReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));


    offset_to_mask
        #(

          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    otom_inst
        (

         .MASK                          (wSAxisCcTKeep),

         .OFFSET_ENABLE                 (wTxcPktEndFlag),
         .OFFSET                        (wTxcPktEndOffset)
);
    
    pipeline
        #(

          .C_DEPTH                         (C_OUTPUT_STAGES),
          .C_WIDTH                         (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wSAxisCcTReady),
         .RD_DATA                        ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
         .RD_DATA_VALID                  (S_AXIS_CC_TVALID),

         .WR_DATA                        ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
         .WR_DATA_VALID                  (wSAxisCcTValid),
         .RD_DATA_READY                  (S_AXIS_CC_TREADY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

endmodule