data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:15: Cannot find include file: common_cells/registers.svh\n`include "common_cells/registers.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/common_cells/registers.svh.sv\n             common_cells/registers.svh\n             common_cells/registers.svh.v\n             common_cells/registers.svh.sv\n             obj_dir/common_cells/registers.svh\n             obj_dir/common_cells/registers.svh.v\n             obj_dir/common_cells/registers.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:215: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:216: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:100: syntax error, unexpected ::\n            if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin\n                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:115: syntax error, unexpected end, expecting endcase\n      end\n      ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:122: syntax error, unexpected ::, expecting \':\'\n          if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin\n                                       ^~\n                                                                                                : ... Perhaps \'axi_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:128: syntax error, unexpected \'=\', expecting IDENTIFIER\n            state_d = AtopExecute;\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:137: syntax error, unexpected \'=\', expecting IDENTIFIER\n    mst_req_o.b_ready  = slv_req_i.b_ready  & ~wr_fifo_empty;\n                       ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:140: syntax error, unexpected \'=\', expecting IDENTIFIER\n    slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty;\n                       ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:141: syntax error, unexpected \'=\', expecting IDENTIFIER\n    mst_req_o.r_ready  = slv_req_i.r_ready  & ~rd_fifo_empty;\n                       ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:184: Define or directive not defined: \'`FFARN\'\n  `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:184: syntax error, unexpected \'(\'\n  `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)\n         ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:247: Define or directive not defined: \'`AXI_TYPEDEF_AW_CHAN_T\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:247: syntax error, unexpected \'(\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:248: Define or directive not defined: \'`AXI_TYPEDEF_W_CHAN_T\'\n  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:249: Define or directive not defined: \'`AXI_TYPEDEF_B_CHAN_T\'\n  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:250: Define or directive not defined: \'`AXI_TYPEDEF_AR_CHAN_T\'\n  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:251: Define or directive not defined: \'`AXI_TYPEDEF_R_CHAN_T\'\n  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:252: Define or directive not defined: \'`AXI_TYPEDEF_REQ_T\'\n  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:253: Define or directive not defined: \'`AXI_TYPEDEF_RESP_T\'\n  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:256: Define or directive not defined: \'`AXI_ASSIGN_TO_REQ\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:256: syntax error, unexpected \'(\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n                     ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:257: Define or directive not defined: \'`AXI_ASSIGN_FROM_RESP\'\n  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:258: Define or directive not defined: \'`AXI_ASSIGN_FROM_REQ\'\n  `AXI_ASSIGN_FROM_REQ(mst, mst_req)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_serializer.sv:259: Define or directive not defined: \'`AXI_ASSIGN_TO_RESP\'\n  `AXI_ASSIGN_TO_RESP(mst_resp, mst)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module axi_serializer #(

  parameter int unsigned MaxReadTxns  = 32'd0,

  parameter int unsigned MaxWriteTxns = 32'd0,

  parameter int unsigned AxiIdWidth   = 32'd0,

  parameter type         req_t        = logic,

  parameter type         resp_t       = logic
) (

  input  logic  clk_i,

  input  logic  rst_ni,

  input  req_t  slv_req_i,

  output resp_t slv_resp_o,

  output req_t  mst_req_o,

  input  resp_t mst_resp_i
);

  typedef logic [AxiIdWidth-1:0] id_t;
  typedef enum logic [1:0] {
    AtopIdle    = 2'b00,
    AtopDrain   = 2'b01,
    AtopExecute = 2'b10
  } state_e;

  logic   rd_fifo_full, rd_fifo_empty, rd_fifo_push, rd_fifo_pop,
          wr_fifo_full, wr_fifo_empty, wr_fifo_push, wr_fifo_pop;
  id_t    b_id,
          r_id,         ar_id;
  state_e state_q,      state_d;

  always_comb begin

    state_d      = state_q;
    rd_fifo_push = 1'b0;
    wr_fifo_push = 1'b0;


    mst_req_o  = slv_req_i;
    slv_resp_o = mst_resp_i;


    mst_req_o.aw.id = '0;
    mst_req_o.ar.id = '0;


    ar_id           = slv_req_i.ar.id;
    slv_resp_o.b.id = b_id;
    slv_resp_o.r.id = r_id;


    mst_req_o.ar_valid  = 1'b0;
    slv_resp_o.ar_ready = 1'b0;
    mst_req_o.aw_valid  = 1'b0;
    slv_resp_o.aw_ready = 1'b0;

    unique case (state_q)
      AtopIdle, AtopExecute: begin


        if (state_q == AtopExecute) begin
          if ((wr_fifo_empty && rd_fifo_empty) || (wr_fifo_pop && rd_fifo_pop) ||
              (wr_fifo_empty && rd_fifo_pop)   || (wr_fifo_pop && rd_fifo_empty)) begin
            state_d = AtopIdle;
          end
        end



        if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin

          mst_req_o.ar_valid  = slv_req_i.ar_valid  & ~rd_fifo_full;
          slv_resp_o.ar_ready = mst_resp_i.ar_ready & ~rd_fifo_full;
          rd_fifo_push        = mst_req_o.ar_valid  & mst_resp_i.ar_ready;
          if (slv_req_i.aw_valid) begin
            if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin


              mst_req_o.aw_valid  = ~wr_fifo_full;
              slv_resp_o.aw_ready = mst_resp_i.aw_ready & ~wr_fifo_full;
              wr_fifo_push        = mst_req_o.aw_valid  & mst_resp_i.aw_ready;
            end else begin


              if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_resp_i.ar_ready)) begin
                state_d = AtopDrain;
              end
            end
          end
        end
      end
      AtopDrain: begin

        if (wr_fifo_empty && rd_fifo_empty) begin
          mst_req_o.aw_valid  = 1'b1;
          slv_resp_o.aw_ready = mst_resp_i.aw_ready;
          wr_fifo_push        = mst_resp_i.aw_ready;
          if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin

            ar_id        = slv_req_i.aw.id;
            rd_fifo_push = mst_resp_i.aw_ready;
          end
          if (mst_resp_i.aw_ready) begin
            state_d = AtopExecute;
          end
        end
      end
      default :;
    endcase


    slv_resp_o.b_valid = mst_resp_i.b_valid & ~wr_fifo_empty;
    mst_req_o.b_ready  = slv_req_i.b_ready  & ~wr_fifo_empty;


    slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty;
    mst_req_o.r_ready  = slv_req_i.r_ready  & ~rd_fifo_empty;
  end

  fifo_v3 #(
    .FALL_THROUGH ( 1'b0        ),
    .DEPTH        ( MaxReadTxns ),
    .dtype        ( id_t        )
  ) i_rd_id_fifo (
    .clk_i,
    .rst_ni,
    .flush_i    ( 1'b0          ),
    .testmode_i ( 1'b0          ),
    .data_i     ( ar_id         ),
    .push_i     ( rd_fifo_push  ),
    .full_o     ( rd_fifo_full  ),
    .data_o     ( r_id          ),
    .empty_o    ( rd_fifo_empty ),
    .pop_i      ( rd_fifo_pop   ),
    .usage_o    ()
  );

  assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last;

  fifo_v3 #(
    .FALL_THROUGH ( 1'b0         ),
    .DEPTH        ( MaxWriteTxns ),
    .dtype        ( id_t         )
  ) i_wr_id_fifo (
    .clk_i,
    .rst_ni,
    .flush_i    ( 1'b0            ),
    .testmode_i ( 1'b0            ),
    .data_i     ( slv_req_i.aw.id ),
    .push_i     ( wr_fifo_push    ),
    .full_o     ( wr_fifo_full    ),
    .data_o     ( b_id            ),
    .empty_o    ( wr_fifo_empty   ),
    .pop_i      ( wr_fifo_pop     ),
    .usage_o    ()
  );

  assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready;

  `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)


`ifndef VERILATOR
  initial begin: p_assertions
    assert (AxiIdWidth    >= 1) else $fatal(1, "AXI ID width must be at least 1!");
    assert (MaxReadTxns   >= 1)
      else $fatal(1, "Maximum number of read transactions must be >= 1!");
    assert (MaxWriteTxns  >= 1)
      else $fatal(1, "Maximum number of write transactions must be >= 1!");
  end
  default disable iff (~rst_ni);
  aw_lost : assert property( @(posedge clk_i)
      (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready))
    else $error("AW beat lost.");
  w_lost  : assert property( @(posedge clk_i)
      (slv_req_i.w_valid & slv_resp_o.w_ready |-> mst_req_o.w_valid & mst_resp_i.w_ready))
    else $error("W beat lost.");
  b_lost  : assert property( @(posedge clk_i)
      (mst_resp_i.b_valid & mst_req_o.b_ready |-> slv_resp_o.b_valid & slv_req_i.b_ready))
    else $error("B beat lost.");
  ar_lost : assert property( @(posedge clk_i)
      (slv_req_i.ar_valid & slv_resp_o.ar_ready |-> mst_req_o.ar_valid & mst_resp_i.ar_ready))
    else $error("AR beat lost.");
  r_lost :  assert property( @(posedge clk_i)
      (mst_resp_i.r_valid & mst_req_o.r_ready |-> slv_resp_o.r_valid & slv_req_i.r_ready))
    else $error("R beat lost.");
`endif

endmodule
module axi_serializer #(

  parameter int unsigned MaxReadTxns  = 32'd0,

  parameter int unsigned MaxWriteTxns = 32'd0,

  parameter int unsigned AxiIdWidth   = 32'd0,

  parameter type         req_t        = logic,

  parameter type         resp_t       = logic
) (

  input  logic  clk_i,

  input  logic  rst_ni,

  input  req_t  slv_req_i,

  output resp_t slv_resp_o,

  output req_t  mst_req_o,

  input  resp_t mst_resp_i
);


  typedef logic [AxiIdWidth-1:0] id_t;
  typedef enum logic [1:0] {
    AtopIdle    = 2'b00,
    AtopDrain   = 2'b01,
    AtopExecute = 2'b10
  } state_e;

  logic   rd_fifo_full, rd_fifo_empty, rd_fifo_push, rd_fifo_pop,
          wr_fifo_full, wr_fifo_empty, wr_fifo_push, wr_fifo_pop;
  id_t    b_id,
          r_id,         ar_id;
  state_e state_q,      state_d;

  always_comb begin

    state_d      = state_q;
    rd_fifo_push = 1'b0;
    wr_fifo_push = 1'b0;


    mst_req_o  = slv_req_i;
    slv_resp_o = mst_resp_i;


    mst_req_o.aw.id = '0;
    mst_req_o.ar.id = '0;


    ar_id           = slv_req_i.ar.id;
    slv_resp_o.b.id = b_id;
    slv_resp_o.r.id = r_id;


    mst_req_o.ar_valid  = 1'b0;
    slv_resp_o.ar_ready = 1'b0;
    mst_req_o.aw_valid  = 1'b0;
    slv_resp_o.aw_ready = 1'b0;

    unique case (state_q)
      AtopIdle, AtopExecute: begin


        if (state_q == AtopExecute) begin
          if ((wr_fifo_empty && rd_fifo_empty) || (wr_fifo_pop && rd_fifo_pop) ||
              (wr_fifo_empty && rd_fifo_pop)   || (wr_fifo_pop && rd_fifo_empty)) begin
            state_d = AtopIdle;
          end
        end



        if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin

          mst_req_o.ar_valid  = slv_req_i.ar_valid  & ~rd_fifo_full;
          slv_resp_o.ar_ready = mst_resp_i.ar_ready & ~rd_fifo_full;
          rd_fifo_push        = mst_req_o.ar_valid  & mst_resp_i.ar_ready;
          if (slv_req_i.aw_valid) begin
            if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin


              mst_req_o.aw_valid  = ~wr_fifo_full;
              slv_resp_o.aw_ready = mst_resp_i.aw_ready & ~wr_fifo_full;
              wr_fifo_push        = mst_req_o.aw_valid  & mst_resp_i.aw_ready;
            end else begin


              if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_resp_i.ar_ready)) begin
                state_d = AtopDrain;
              end
            end
          end
        end
      end
      AtopDrain: begin

        if (wr_fifo_empty && rd_fifo_empty) begin
          mst_req_o.aw_valid  = 1'b1;
          slv_resp_o.aw_ready = mst_resp_i.aw_ready;
          wr_fifo_push        = mst_resp_i.aw_ready;
          if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin

            ar_id        = slv_req_i.aw.id;
            rd_fifo_push = mst_resp_i.aw_ready;
          end
          if (mst_resp_i.aw_ready) begin
            state_d = AtopExecute;
          end
        end
      end
      default :;
    endcase


    slv_resp_o.b_valid = mst_resp_i.b_valid & ~wr_fifo_empty;
    mst_req_o.b_ready  = slv_req_i.b_ready  & ~wr_fifo_empty;


    slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty;
    mst_req_o.r_ready  = slv_req_i.r_ready  & ~rd_fifo_empty;
  end

  fifo_v3 #(
    .FALL_THROUGH ( 1'b0        ),
    .DEPTH        ( MaxReadTxns ),
    .dtype        ( id_t        )
  ) i_rd_id_fifo (
    .clk_i,
    .rst_ni,
    .flush_i    ( 1'b0          ),
    .testmode_i ( 1'b0          ),
    .data_i     ( ar_id         ),
    .push_i     ( rd_fifo_push  ),
    .full_o     ( rd_fifo_full  ),
    .data_o     ( r_id          ),
    .empty_o    ( rd_fifo_empty ),
    .pop_i      ( rd_fifo_pop   ),
    .usage_o    ()
  );

  assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last;

  fifo_v3 #(
    .FALL_THROUGH ( 1'b0         ),
    .DEPTH        ( MaxWriteTxns ),
    .dtype        ( id_t         )
  ) i_wr_id_fifo (
    .clk_i,
    .rst_ni,
    .flush_i    ( 1'b0            ),
    .testmode_i ( 1'b0            ),
    .data_i     ( slv_req_i.aw.id ),
    .push_i     ( wr_fifo_push    ),
    .full_o     ( wr_fifo_full    ),
    .data_o     ( b_id            ),
    .empty_o    ( wr_fifo_empty   ),
    .pop_i      ( wr_fifo_pop     ),
    .usage_o    ()
  );

  assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready;

  `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)


`ifndef VERILATOR
  initial begin: p_assertions
    assert (AxiIdWidth    >= 1) else $fatal(1, "AXI ID width must be at least 1!");
    assert (MaxReadTxns   >= 1)
      else $fatal(1, "Maximum number of read transactions must be >= 1!");
    assert (MaxWriteTxns  >= 1)
      else $fatal(1, "Maximum number of write transactions must be >= 1!");
  end
  default disable iff (~rst_ni);
  aw_lost : assert property( @(posedge clk_i)
      (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready))
    else $error("AW beat lost.");
  w_lost  : assert property( @(posedge clk_i)
      (slv_req_i.w_valid & slv_resp_o.w_ready |-> mst_req_o.w_valid & mst_resp_i.w_ready))
    else $error("W beat lost.");
  b_lost  : assert property( @(posedge clk_i)
      (mst_resp_i.b_valid & mst_req_o.b_ready |-> slv_resp_o.b_valid & slv_req_i.b_ready))
    else $error("B beat lost.");
  ar_lost : assert property( @(posedge clk_i)
      (slv_req_i.ar_valid & slv_resp_o.ar_ready |-> mst_req_o.ar_valid & mst_resp_i.ar_ready))
    else $error("AR beat lost.");
  r_lost :  assert property( @(posedge clk_i)
      (mst_resp_i.r_valid & mst_req_o.r_ready |-> slv_resp_o.r_valid & slv_req_i.r_ready))
    else $error("R beat lost.");
`endif

endmodule