data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montinvp1.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montinvp1.v:84: Cannot find file containing module: 'aladder'\naladder ifull_sub_uv(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder.sv\n             aladder\n             aladder.v\n             aladder.sv\n             obj_dir/aladder\n             obj_dir/aladder.v\n             obj_dir/aladder.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montinvp1.v:105: Cannot find file containing module: 'aladder'\naladder ifull_sub_vu(\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montinvp1.v:126: Cannot find file containing module: 'aladder'\naladder iadd(\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module montinvp1
    (
     clk,
     rst,
     din,
     mod,
     en,
     ainv,
     exp,
     vld
     );




parameter WIDTH = 256;
parameter CWID  = 10;

parameter INIT0 = 0;
parameter INIT1 = 1;




input clk;
input rst;
input [WIDTH-1:0] din;
input [WIDTH-1:0] mod;
input             en;

output [WIDTH-1:0] ainv;
output [CWID-1:0]  exp;
output             vld;





reg [CWID-1:0]     exp;
reg                vld;




reg [WIDTH-1:0]    u, v, r, s, p;

always @(posedge clk)
    begin
    if (rst)
        begin
        p   <= INIT0;
        end
    else if (en)
        begin
        p   <= mod;
        end
    end

wire [WIDTH-1:0] u_v;
wire             u_lrg_eq_v;


aladder ifull_sub_uv(
    .cin(1'b1),
    .clock(clk),
    .dataa(u),
    .datab(v),
    .cout(u_lrg_eq_v),
    .result(u_v)
                     );

wire [WIDTH-1:0] v_u;
wire             v_lrg_eq_u;


aladder ifull_sub_vu(
    .cin(1'b1),
    .clock(clk),
    .dataa(v),
    .datab(u),
    .cout(v_lrg_eq_u),
    .result(v_u)
                     );

wire [WIDTH-1:0] sr;



aladder iadd(
    .cin(1'b0),
    .clock(clk),
    .dataa(s),
    .datab(r),
    .cout(),
    .result(sr)
             );



reg stop;

always @(posedge clk)
    begin
    if (rst)
        begin
        stop    <= 1'b1;
        vld     <= 1'b0;
        end
    else if (en)
        begin
        stop    <= 1'b0;
        vld     <= 1'b0;
        end
    else if ((v == 0) && (!stop))
        begin
        stop    <= 1'b1;
        vld     <= 1'b1;
        end
    else
        begin
        stop    <= stop;
        vld     <= 1'b0;
        end
    end



reg msb;

always @(posedge clk)
    begin
    if (rst)
        begin
        u   <= INIT0;
        v   <= INIT0;
        r   <= INIT0;
        s   <= INIT0;
        exp <= INIT0;
        msb <= INIT0;
        end
    else if (en)
        begin
        u   <= mod;
        v   <= din;
        r   <= INIT0;
        s   <= INIT1;
        exp <= INIT0;
        msb <= INIT0;
        end
    else if (v > 0)
        begin
        if (u[2:0] == 3'b000)
            begin
            u   <= {3'b0, u[WIDTH-1:3]};
            s   <= {s[WIDTH-4:0], 3'b0};
            exp <= exp + 3;
            end
        else if (u[2:0] == 3'b100)
            begin
            u   <= {2'b0, u[WIDTH-1:2]};
            s   <= {s[WIDTH-3:0], 2'b0};
            exp <= exp + 2;
            end
        else if (u[1:0] == 2'b10)
            begin
            u   <= {1'b0, u[WIDTH-1:1]};
            s   <= {s[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        else if (v[2:0] == 3'b000)
            begin
            v   <= {3'b0, v[WIDTH-1:3]};
            r   <= {r[WIDTH-4:0], 3'b0};
            exp <= exp + 3;
            end
        else if (v[2:0] == 3'b100)
            begin
            v   <= {2'b0, v[WIDTH-1:2]};
            r   <= {r[WIDTH-3:0], 2'b0};
            exp <= exp + 2;
            end
        else if (v[1:0] == 2'b10)
            begin
            v   <= {1'b0, v[WIDTH-1:1]};
            r   <= {r[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        else if (v_lrg_eq_u)
            begin
            v   <= {1'b0, v_u[WIDTH-1:1]};
            r   <= {r[WIDTH-2:0], 1'b0};
            s   <= sr;
            exp <= exp + 1;
            msb <= r[WIDTH-1];
            end
        else
            begin
            u   <= {1'b0, u_v[WIDTH-1:1]};
            r   <= sr;
            s   <= {s[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        end
    else if ((v == 0) && (!stop))
        begin
        if ((r >= p) || msb)
            begin
            r   <= {p[WIDTH-2:0], 1'b0} - r;
            end
        else
            begin
            r   <= p - r;
            end
        end
    end

assign ainv = r;

endmodule
module montinvp1
    (
     clk,
     rst,
     din,
     mod,
     en,
     ainv,
     exp,
     vld
     );





parameter WIDTH = 256;
parameter CWID  = 10;

parameter INIT0 = 0;
parameter INIT1 = 1;




input clk;
input rst;
input [WIDTH-1:0] din;
input [WIDTH-1:0] mod;
input             en;

output [WIDTH-1:0] ainv;
output [CWID-1:0]  exp;
output             vld;





reg [CWID-1:0]     exp;
reg                vld;




reg [WIDTH-1:0]    u, v, r, s, p;

always @(posedge clk)
    begin
    if (rst)
        begin
        p   <= INIT0;
        end
    else if (en)
        begin
        p   <= mod;
        end
    end

wire [WIDTH-1:0] u_v;
wire             u_lrg_eq_v;


aladder ifull_sub_uv(
    .cin(1'b1),
    .clock(clk),
    .dataa(u),
    .datab(v),
    .cout(u_lrg_eq_v),
    .result(u_v)
                     );

wire [WIDTH-1:0] v_u;
wire             v_lrg_eq_u;


aladder ifull_sub_vu(
    .cin(1'b1),
    .clock(clk),
    .dataa(v),
    .datab(u),
    .cout(v_lrg_eq_u),
    .result(v_u)
                     );

wire [WIDTH-1:0] sr;



aladder iadd(
    .cin(1'b0),
    .clock(clk),
    .dataa(s),
    .datab(r),
    .cout(),
    .result(sr)
             );



reg stop;

always @(posedge clk)
    begin
    if (rst)
        begin
        stop    <= 1'b1;
        vld     <= 1'b0;
        end
    else if (en)
        begin
        stop    <= 1'b0;
        vld     <= 1'b0;
        end
    else if ((v == 0) && (!stop))
        begin
        stop    <= 1'b1;
        vld     <= 1'b1;
        end
    else
        begin
        stop    <= stop;
        vld     <= 1'b0;
        end
    end



reg msb;

always @(posedge clk)
    begin
    if (rst)
        begin
        u   <= INIT0;
        v   <= INIT0;
        r   <= INIT0;
        s   <= INIT0;
        exp <= INIT0;
        msb <= INIT0;
        end
    else if (en)
        begin
        u   <= mod;
        v   <= din;
        r   <= INIT0;
        s   <= INIT1;
        exp <= INIT0;
        msb <= INIT0;
        end
    else if (v > 0)
        begin
        if (u[2:0] == 3'b000)
            begin
            u   <= {3'b0, u[WIDTH-1:3]};
            s   <= {s[WIDTH-4:0], 3'b0};
            exp <= exp + 3;
            end
        else if (u[2:0] == 3'b100)
            begin
            u   <= {2'b0, u[WIDTH-1:2]};
            s   <= {s[WIDTH-3:0], 2'b0};
            exp <= exp + 2;
            end
        else if (u[1:0] == 2'b10)
            begin
            u   <= {1'b0, u[WIDTH-1:1]};
            s   <= {s[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        else if (v[2:0] == 3'b000)
            begin
            v   <= {3'b0, v[WIDTH-1:3]};
            r   <= {r[WIDTH-4:0], 3'b0};
            exp <= exp + 3;
            end
        else if (v[2:0] == 3'b100)
            begin
            v   <= {2'b0, v[WIDTH-1:2]};
            r   <= {r[WIDTH-3:0], 2'b0};
            exp <= exp + 2;
            end
        else if (v[1:0] == 2'b10)
            begin
            v   <= {1'b0, v[WIDTH-1:1]};
            r   <= {r[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        else if (v_lrg_eq_u)
            begin
            v   <= {1'b0, v_u[WIDTH-1:1]};
            r   <= {r[WIDTH-2:0], 1'b0};
            s   <= sr;
            exp <= exp + 1;
            msb <= r[WIDTH-1];
            end
        else
            begin
            u   <= {1'b0, u_v[WIDTH-1:1]};
            r   <= sr;
            s   <= {s[WIDTH-2:0], 1'b0};
            exp <= exp + 1;
            end
        end
    else if ((v == 0) && (!stop))
        begin
        if ((r >= p) || msb)
            begin
            r   <= {p[WIDTH-2:0], 1'b0} - r;
            end
        else
            begin
            r   <= p - r;
            end
        end
    end

assign ainv = r;

endmodule