data/full_repos/permissive/434840709/week10/5.v
data/verilator_xmls/4f10843e-97a1-412c-a0ff-d95fec4b7354.xml
module top_module( 

        input in, 

        output out 

);

        assign out = in;

endmodule
module top_module( 

        input in, 

        output out 

);


        assign out = in;

endmodule