data/full_repos/permissive/435914753/Display_kbd/vga_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:21: Value too large for 2 bit number: 4\nassign clkdiv5 = (cnt==2\'d4);\n                       ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:284: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                        : ... Top module \'oneFifthMegaHertz\'\nmodule oneFifthMegaHertz (reset, clk, enable, clkdiv5);\n       ^~~~~~~~~~~~~~~~~\n                                                                                        : ... Top module \'top\'\nmodule top (reset, clk, r, g, b, hsync, vsync, ps2clk, ps2data, left, right);\n       ^~~\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:307: Cannot find file containing module: \'kbd_protocol\'\nkbd_protocol kbd (reset, clk, ps2clk, ps2data, scan, scanPrev, scanPrev2);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435914753/Display_kbd,data/full_repos/permissive/435914753/kbd_protocol\n             data/full_repos/permissive/435914753/Display_kbd,data/full_repos/permissive/435914753/kbd_protocol.v\n             data/full_repos/permissive/435914753/Display_kbd,data/full_repos/permissive/435914753/kbd_protocol.sv\n             kbd_protocol\n             kbd_protocol.v\n             kbd_protocol.sv\n             obj_dir/kbd_protocol\n             obj_dir/kbd_protocol.v\n             obj_dir/kbd_protocol.sv\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:308: Cannot find file containing module: \'scan_2_bin\'\nscan_2_bin s2b0 (scan, bin);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:309: Cannot find file containing module: \'bin2bcd\'\nbin2bcd b2b0(bin, bcd);\n^~~~~~~\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:310: Cannot find file containing module: \'bcd_2_7seg\'\nbcd_2_7seg b27s0(bcd, left);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:311: Cannot find file containing module: \'bcd_2_7seg\'\nbcd_2_7seg b27s1(4\'b1111, right);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:313: Cannot find file containing module: \'numORcolour\'\nnumORcolour noc0 (clk, bin, reds, greens, blues);\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/435914753/Display_kbd/vga_controller.v:21: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                    : ... In instance oneFifthMegaHertz\nassign clkdiv5 = (cnt==2\'d4);\n                     ^~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module vga_controller (clk, pixelClk, r, g, b, hsync, vsync, reds, greens, blues);

parameter hbp = 48;
parameter hfp = 16;
parameter hsp = 96;
parameter visPix = 640;

parameter startVisH = hbp+hfp+hsp;
parameter endHSync = startVisH + visPix;

parameter boxSizeH = visPix/3;
parameter box_y1 = startVisH + boxSizeH;
parameter box_y2 = box_y1 + boxSizeH;
parameter box_y3 = box_y2 + boxSizeH;



parameter vbp = 35;
parameter vfp = 12;
parameter vsp = 2;
parameter visRow = 400;

parameter startVisV = vbp+vfp+vsp;
parameter endVSync = startVisV + visRow;

parameter boxSizeV = visRow/3;
parameter box_1x = startVisV + boxSizeV;
parameter box_2x = box_1x + boxSizeV;
parameter box_3x = box_2x + boxSizeV;


input clk, pixelClk;

input [26:0] reds;
input [26:0] greens;
input [26:0] blues;


output [2:0] r, g, b;
reg [2:0] r, g, b;
output hsync, vsync;
reg hsync, vsync;

reg [9:0] countR;
reg [8:0] countV;



wire visibleR;
wire visibleV;
wire visibleArea;
wire first_row;
wire second_row;
wire third_row;
wire first_column;
wire second_column;
wire third_column;

wire selectedBoxRow;
wire selectedBoxCol;
wire selected;






 always@(posedge clk)
 begin
 
 
 if (pixelClk == 1'b1)
 begin 
	if (countR == 10'd799)
	begin
		countR <= 10'd0;
		if(countV == 9'd448) countV <= 9'd0;
		else countV <= countV+9'b1;
	end
	else countR <= countR+10'b1;	
	
	
	if (countR >= 16 && countR < 48)	hsync <= 1'b0;
   else hsync <= 1'b1;
 
	if (countV >= 12 && countV < 35)	vsync <= 1'b1;
	else vsync <= 1'b0;
	
	
 end
 
 
 
 end
 
 
 assign visibleR = (countR >= startVisH && countR < endHSync);
 assign visibleV = (countV >= startVisV && countV < endVSync);
 assign visibleArea = visibleV && visibleR;
 
 assign first_row = (countV >= startVisV && countV < box_1x );
 assign second_row = (countV >= box_1x && countV < box_2x );
 assign third_row = (countV >= box_2x && countV < box_3x );
 
 assign first_column = ( countR >= startVisH && countR < box_y1 );
 assign second_column = ( countR >= box_y1 && countR < box_y2 );
 assign third_column = ( countR >= box_y2 && countR < box_y3 );
 


								  
 
 
 always@(posedge clk)
 if (pixelClk == 1'b1)
 begin
	 if( visibleArea == 1'b1)
	 begin
		if ( first_row && first_column ) begin



			
			r <= reds[2:0] ; 
			g <= greens[2:0] ; 
			b <= blues[2:0] ; 
		end
		else if ( first_row && second_column) begin



			
			r <= reds[5:3] ; 
			g <= greens[5:3] ; 
			b <= blues[5:3] ; 
		end
		else if ( first_row && third_column ) begin



			
			r <= reds[8:6] ; 
			g <= greens[8:6] ; 
			b <= blues[8:6] ; 
		end
		else if ( second_row && first_column ) begin




			
			r <= reds[11:9]  ; 
			g <= greens[11:9] ; 
			b <= blues[11:9] ; 

		end
		else if ( second_row && second_column ) begin



			
			r <= reds[14:12]; 
			g <= greens[14:12] ; 
			b <= blues[14:12] ; 
		end
		else if ( second_row && third_column) begin



			
			r <= reds[17:15]; 
			g <= greens[17:15] ; 
			b <= blues[17:15]; 
		end
		else if ( third_row && first_column ) begin



			
			r <= reds[20:18]; 
			g <= greens[20:18] ; 
			b <= blues[20:18] ; 
		end
		else if ( third_row && second_column ) begin



			
			r <= reds[23:21]; 
			g <= greens[23:21]; 
			b <= blues[23:21]; 
		end
		else if ( third_row && third_column ) begin



			
			r <= reds[26:24] ; 
			g <= greens[26:24] ; 
			b <= blues[26:24] ; 
		end

		else
		begin
		r <= 3'b000;
		g <= 3'b000;
		b <= 3'b000;
		end
	 end
	 else 
	 begin 
		r <= 3'b000;
		g <= 3'b000;
		b <= 3'b000;
	 end
 end
 
  
endmodule
module vga_controller (clk, pixelClk, r, g, b, hsync, vsync, reds, greens, blues);


parameter hbp = 48;
parameter hfp = 16;
parameter hsp = 96;
parameter visPix = 640;

parameter startVisH = hbp+hfp+hsp;
parameter endHSync = startVisH + visPix;

parameter boxSizeH = visPix/3;
parameter box_y1 = startVisH + boxSizeH;
parameter box_y2 = box_y1 + boxSizeH;
parameter box_y3 = box_y2 + boxSizeH;



parameter vbp = 35;
parameter vfp = 12;
parameter vsp = 2;
parameter visRow = 400;

parameter startVisV = vbp+vfp+vsp;
parameter endVSync = startVisV + visRow;

parameter boxSizeV = visRow/3;
parameter box_1x = startVisV + boxSizeV;
parameter box_2x = box_1x + boxSizeV;
parameter box_3x = box_2x + boxSizeV;


input clk, pixelClk;

input [26:0] reds;
input [26:0] greens;
input [26:0] blues;


output [2:0] r, g, b;
reg [2:0] r, g, b;
output hsync, vsync;
reg hsync, vsync;

reg [9:0] countR;
reg [8:0] countV;



wire visibleR;
wire visibleV;
wire visibleArea;
wire first_row;
wire second_row;
wire third_row;
wire first_column;
wire second_column;
wire third_column;

wire selectedBoxRow;
wire selectedBoxCol;
wire selected;






 always@(posedge clk)
 begin
 
 
 if (pixelClk == 1'b1)
 begin 
	if (countR == 10'd799)
	begin
		countR <= 10'd0;
		if(countV == 9'd448) countV <= 9'd0;
		else countV <= countV+9'b1;
	end
	else countR <= countR+10'b1;	
	
	
	if (countR >= 16 && countR < 48)	hsync <= 1'b0;
   else hsync <= 1'b1;
 
	if (countV >= 12 && countV < 35)	vsync <= 1'b1;
	else vsync <= 1'b0;
	
	
 end
 
 
 
 end
 
 
 assign visibleR = (countR >= startVisH && countR < endHSync);
 assign visibleV = (countV >= startVisV && countV < endVSync);
 assign visibleArea = visibleV && visibleR;
 
 assign first_row = (countV >= startVisV && countV < box_1x );
 assign second_row = (countV >= box_1x && countV < box_2x );
 assign third_row = (countV >= box_2x && countV < box_3x );
 
 assign first_column = ( countR >= startVisH && countR < box_y1 );
 assign second_column = ( countR >= box_y1 && countR < box_y2 );
 assign third_column = ( countR >= box_y2 && countR < box_y3 );
 


								  
 
 
 always@(posedge clk)
 if (pixelClk == 1'b1)
 begin
	 if( visibleArea == 1'b1)
	 begin
		if ( first_row && first_column ) begin



			
			r <= reds[2:0] ; 
			g <= greens[2:0] ; 
			b <= blues[2:0] ; 
		end
		else if ( first_row && second_column) begin



			
			r <= reds[5:3] ; 
			g <= greens[5:3] ; 
			b <= blues[5:3] ; 
		end
		else if ( first_row && third_column ) begin



			
			r <= reds[8:6] ; 
			g <= greens[8:6] ; 
			b <= blues[8:6] ; 
		end
		else if ( second_row && first_column ) begin




			
			r <= reds[11:9]  ; 
			g <= greens[11:9] ; 
			b <= blues[11:9] ; 

		end
		else if ( second_row && second_column ) begin



			
			r <= reds[14:12]; 
			g <= greens[14:12] ; 
			b <= blues[14:12] ; 
		end
		else if ( second_row && third_column) begin



			
			r <= reds[17:15]; 
			g <= greens[17:15] ; 
			b <= blues[17:15]; 
		end
		else if ( third_row && first_column ) begin



			
			r <= reds[20:18]; 
			g <= greens[20:18] ; 
			b <= blues[20:18] ; 
		end
		else if ( third_row && second_column ) begin



			
			r <= reds[23:21]; 
			g <= greens[23:21]; 
			b <= blues[23:21]; 
		end
		else if ( third_row && third_column ) begin



			
			r <= reds[26:24] ; 
			g <= greens[26:24] ; 
			b <= blues[26:24] ; 
		end

		else
		begin
		r <= 3'b000;
		g <= 3'b000;
		b <= 3'b000;
		end
	 end
	 else 
	 begin 
		r <= 3'b000;
		g <= 3'b000;
		b <= 3'b000;
	 end
 end
 
  
endmodule