data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:38: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:69: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n   parameter connectivity = `CONNECTIVITY_LINE;\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter connectivity = `CONNECTIVITY_LINE;\n                                              ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:72: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:75: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:140: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n      `ROUTING_TYPE_PHASED_DOR:\n      ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:140: syntax error, unexpected \':\', expecting endcase\n      `ROUTING_TYPE_PHASED_DOR:\n                              ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:155: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n     (((connectivity == `CONNECTIVITY_LINE) || \n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:156: Define or directive not defined: \'`CONNECTIVITY_RING\'\n       (connectivity == `CONNECTIVITY_RING)) &&\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:167: Define or directive not defined: \'`CONNECTIVITY_FULL\'\n     ((connectivity == `CONNECTIVITY_FULL) &&\n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:181: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n     (((((dim_order == `DIM_ORDER_ASCENDING) || \n                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:182: Define or directive not defined: \'`DIM_ORDER_BY_CLASS\'\n         ((dim_order == `DIM_ORDER_BY_CLASS) && \n                        ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:188: Define or directive not defined: \'`DIM_ORDER_DESCENDING\'\n       (((dim_order == `DIM_ORDER_DESCENDING) || \n                       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:189: Define or directive not defined: \'`DIM_ORDER_BY_CLASS\'\n         (dim_order == `DIM_ORDER_BY_CLASS) && \n                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:203: syntax error, unexpected else\n         else\n         ^~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:207: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:221: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:226: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:245: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:256: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n    `ROUTING_TYPE_PHASED_DOR:\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:256: syntax error, unexpected \':\', expecting endcase\n    `ROUTING_TYPE_PHASED_DOR:\n                            ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:267: syntax error, unexpected else\n         else\n         ^~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:271: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_route_filter.v:308: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module rtr_route_filter
  (clk, route_valid, route_in_op, route_in_orc, route_out_op, route_out_orc, 
   errors);
   
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   parameter num_vcs_per_class = 1;
   

   parameter num_ports = 5;
   

   parameter num_neighbors_per_dim = 2;
   

   parameter num_nodes_per_router = 4;
   



   parameter restrict_turns = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter port_id = 0;
   

   parameter vc_id = 0;
   
   



   

   localparam message_class
     = (vc_id / (num_resource_classes*num_vcs_per_class)) % num_message_classes;
   

   localparam resource_class
     = (vc_id / num_vcs_per_class) % num_resource_classes;
   
   



   
   input clk;
   

   input route_valid;
   

   input [0:num_ports-1] route_in_op;
   

   input [0:num_resource_classes-1] route_in_orc;
   

   output [0:num_ports-1] 	    route_out_op;
   wire [0:num_ports-1] 	    route_out_op;
   

   output [0:num_resource_classes-1] route_out_orc;
   wire [0:num_resource_classes-1]   route_out_orc;
   

   output [0:1] 		     errors;
   wire [0:1] 			     errors;   
   
   



   
   wire [0:num_ports-1] 	     error_op;
   
   genvar 			     op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   case(routing_type)
	     
	     `ROUTING_TYPE_PHASED_DOR:
	       begin
		  

		  if(op < (num_ports - num_nodes_per_router))
		    begin
		       
		       if(
			  





			  
			  (((connectivity == `CONNECTIVITY_LINE) || 
			    (connectivity == `CONNECTIVITY_RING)) &&
			   
			   (op == port_id) &&
			   
			   (resource_class == (num_resource_classes - 1))) || 
			  




			  
			  ((connectivity == `CONNECTIVITY_FULL) &&
			   
			   ((op / num_neighbors_per_dim) == 
			    (port_id / num_neighbors_per_dim)) &&
			   
			   (resource_class == (num_resource_classes - 1))) ||
			  






			  
			  (((((dim_order == `DIM_ORDER_ASCENDING) || 
			      ((dim_order == `DIM_ORDER_BY_CLASS) && 
			       ((message_class % 2) == 0))) && 
			     
			     ((op / num_neighbors_per_dim) < 
			      (port_id / num_neighbors_per_dim))) || 
			    
			    (((dim_order == `DIM_ORDER_DESCENDING) || 
			      (dim_order == `DIM_ORDER_BY_CLASS) && 
			      ((message_class % 2) == 1)) && 
			     
			     ((op / num_neighbors_per_dim) > 
			      (port_id / num_neighbors_per_dim)))) && 
			   
			   (resource_class == (num_resource_classes - 1)) && 
			   
			   (port_id < (num_ports - num_nodes_per_router))))
			 
			 begin
			    assign route_out_op[op] = 1'b0;
			    assign error_op[op] = route_in_op[op];
			 end
		       else
			 begin
			    assign route_out_op[op] = route_in_op[op];
			    assign error_op[op] = 1'b0;
			 end
		       
		    end
		  

		  else
		    begin
		       


		       if(op == port_id)
			 begin
			    assign route_out_op[op] = 1'b0;
			    assign error_op[op] = route_in_op[op];
			 end
		       else
			 begin
			    assign route_out_op[op] = route_in_op[op];
			    assign error_op[op] = 1'b0;
			 end
		    end
		  
	       end
	     
	   endcase
	   
	end
      
   endgenerate
   
   wire [0:num_resource_classes-1] error_orc;
   
   generate
      
      if(num_resource_classes == 1)
	begin
	   assign route_out_orc = 1'b1;
	   assign error_orc = ~route_out_orc;
	end
      else if(num_resource_classes > 1)
	begin
	   
	   genvar orc;
	   
	   for(orc = 0; orc < num_resource_classes; orc = orc + 1)
	     begin:orcs
		
		case(routing_type)
		  
		  `ROUTING_TYPE_PHASED_DOR:
		    begin
		       


		       if((orc == resource_class) || 
			  (orc == (resource_class + 1)))
			 begin
			    assign route_out_orc[orc] = route_in_orc[orc];
			    assign error_orc[orc] = 1'b0;
			 end
		       else
			 begin
			    assign route_out_orc[orc] = 1'b0;
			    assign error_orc[orc] = route_in_orc[orc];
			 end
		       
		    end
		  
		endcase
		
	     end
	   
	end
      
   endgenerate
   
   wire error_invalid_port;
   assign error_invalid_port = route_valid & ((|error_op) | (~|route_in_op));
   
   wire error_invalid_class;
   assign error_invalid_class = route_valid & ((|error_orc) | (~|route_in_orc));
   

   always @(posedge clk)
     begin
	
	if(error_invalid_port)
	  $display({"ERROR: Received flit's destination port violates ",
		    "constraints in module %m."});
	
	if(error_invalid_class)
	  $display({"ERROR: Received flit's destination class violates ",
		    "constraints in module %m."});
	
     end
   

   
   assign errors[0] = error_invalid_port;
   assign errors[1] = error_invalid_class;
   
endmodule
module rtr_route_filter
  (clk, route_valid, route_in_op, route_in_orc, route_out_op, route_out_orc, 
   errors);

   
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   parameter num_vcs_per_class = 1;
   

   parameter num_ports = 5;
   

   parameter num_neighbors_per_dim = 2;
   

   parameter num_nodes_per_router = 4;
   



   parameter restrict_turns = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter port_id = 0;
   

   parameter vc_id = 0;
   
   



   

   localparam message_class
     = (vc_id / (num_resource_classes*num_vcs_per_class)) % num_message_classes;
   

   localparam resource_class
     = (vc_id / num_vcs_per_class) % num_resource_classes;
   
   



   
   input clk;
   

   input route_valid;
   

   input [0:num_ports-1] route_in_op;
   

   input [0:num_resource_classes-1] route_in_orc;
   

   output [0:num_ports-1] 	    route_out_op;
   wire [0:num_ports-1] 	    route_out_op;
   

   output [0:num_resource_classes-1] route_out_orc;
   wire [0:num_resource_classes-1]   route_out_orc;
   

   output [0:1] 		     errors;
   wire [0:1] 			     errors;   
   
   



   
   wire [0:num_ports-1] 	     error_op;
   
   genvar 			     op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   case(routing_type)
	     
	     `ROUTING_TYPE_PHASED_DOR:
	       begin
		  

		  if(op < (num_ports - num_nodes_per_router))
		    begin
		       
		       if(
			  





			  
			  (((connectivity == `CONNECTIVITY_LINE) || 
			    (connectivity == `CONNECTIVITY_RING)) &&
			   
			   (op == port_id) &&
			   
			   (resource_class == (num_resource_classes - 1))) || 
			  




			  
			  ((connectivity == `CONNECTIVITY_FULL) &&
			   
			   ((op / num_neighbors_per_dim) == 
			    (port_id / num_neighbors_per_dim)) &&
			   
			   (resource_class == (num_resource_classes - 1))) ||
			  






			  
			  (((((dim_order == `DIM_ORDER_ASCENDING) || 
			      ((dim_order == `DIM_ORDER_BY_CLASS) && 
			       ((message_class % 2) == 0))) && 
			     
			     ((op / num_neighbors_per_dim) < 
			      (port_id / num_neighbors_per_dim))) || 
			    
			    (((dim_order == `DIM_ORDER_DESCENDING) || 
			      (dim_order == `DIM_ORDER_BY_CLASS) && 
			      ((message_class % 2) == 1)) && 
			     
			     ((op / num_neighbors_per_dim) > 
			      (port_id / num_neighbors_per_dim)))) && 
			   
			   (resource_class == (num_resource_classes - 1)) && 
			   
			   (port_id < (num_ports - num_nodes_per_router))))
			 
			 begin
			    assign route_out_op[op] = 1'b0;
			    assign error_op[op] = route_in_op[op];
			 end
		       else
			 begin
			    assign route_out_op[op] = route_in_op[op];
			    assign error_op[op] = 1'b0;
			 end
		       
		    end
		  

		  else
		    begin
		       


		       if(op == port_id)
			 begin
			    assign route_out_op[op] = 1'b0;
			    assign error_op[op] = route_in_op[op];
			 end
		       else
			 begin
			    assign route_out_op[op] = route_in_op[op];
			    assign error_op[op] = 1'b0;
			 end
		    end
		  
	       end
	     
	   endcase
	   
	end
      
   endgenerate
   
   wire [0:num_resource_classes-1] error_orc;
   
   generate
      
      if(num_resource_classes == 1)
	begin
	   assign route_out_orc = 1'b1;
	   assign error_orc = ~route_out_orc;
	end
      else if(num_resource_classes > 1)
	begin
	   
	   genvar orc;
	   
	   for(orc = 0; orc < num_resource_classes; orc = orc + 1)
	     begin:orcs
		
		case(routing_type)
		  
		  `ROUTING_TYPE_PHASED_DOR:
		    begin
		       


		       if((orc == resource_class) || 
			  (orc == (resource_class + 1)))
			 begin
			    assign route_out_orc[orc] = route_in_orc[orc];
			    assign error_orc[orc] = 1'b0;
			 end
		       else
			 begin
			    assign route_out_orc[orc] = 1'b0;
			    assign error_orc[orc] = route_in_orc[orc];
			 end
		       
		    end
		  
		endcase
		
	     end
	   
	end
      
   endgenerate
   
   wire error_invalid_port;
   assign error_invalid_port = route_valid & ((|error_op) | (~|route_in_op));
   
   wire error_invalid_class;
   assign error_invalid_class = route_valid & ((|error_orc) | (~|route_in_orc));
   

   always @(posedge clk)
     begin
	
	if(error_invalid_port)
	  $display({"ERROR: Received flit's destination port violates ",
		    "constraints in module %m."});
	
	if(error_invalid_class)
	  $display({"ERROR: Received flit's destination class violates ",
		    "constraints in module %m."});
	
     end
   

   
   assign errors[0] = error_invalid_port;
   assign errors[1] = error_invalid_class;
   
endmodule