data/full_repos/permissive/458737381/src/verilog-parser/tests/mux.v
data/verilator_xmls/0bd4b56e-d58a-4485-89ec-4ab096af5889.xml
module mux (a,b,c,d,sel,y); 
input a, b, c, d; 
input [1:0] sel; 
output y; 

reg y;

always @ (a or b or c or d or sel) 
case (sel) 
  0 : y = a; 
  1 : y = b; 
  2 : y = c; 
  3 : y = d; 
  default : $display("Error in SEL"); 
endcase 
    
endmodule
module mux (a,b,c,d,sel,y);
 
input a, b, c, d; 
input [1:0] sel; 
output y; 

reg y;

always @ (a or b or c or d or sel) 
case (sel) 
  0 : y = a; 
  1 : y = b; 
  2 : y = c; 
  3 : y = d; 
  default : $display("Error in SEL"); 
endcase 
    
endmodule