data/full_repos/permissive/421223411/verilog/rtl/accelerator/CoreTop.v
data/verilator_xmls/0e0a0b45-d48b-4011-aaf8-3dc66ac7878c.xml
module Datapath(
  input         clock,
  input         reset,
  output [15:0] io_instr_imm,
  output        io_instr_bra_mask_z,
  output        io_instr_bra_mask_c,
  output        io_instr_bra_mask_n,
  output        io_instr_bra_mask_v,
  output        io_instr_has_jump,
  output        io_instr_has_stop,
  output        io_instr_has_branch,
  output        io_instr_has_mem,
  output        io_instr_has_wb,
  output        io_instr_has_imm,
  input         io_issue_if,
  output        io_if_done,
  input         io_issue_mem,
  input         io_mem_we,
  output        io_mem_done,
  input  [2:0]  io_state,
  output [15:0] io_ibus_addr,
  input  [31:0] io_ibus_data_rd,
  output        io_ibus_stb,
  input         io_ibus_ack,
  output [15:0] io_dbus_addr,
  output        io_dbus_we,
  input  [15:0] io_dbus_data_rd,
  output [15:0] io_dbus_data_wr,
  output        io_dbus_stb,
  input         io_dbus_ack,
  input  [15:0] io_restart_pc,
  input         io_restart
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
`endif
  wire [15:0] decoder_io_instr;
  wire [15:0] decoder_io_imm;
  wire [2:0] decoder_io_decoded_rs1;
  wire [2:0] decoder_io_decoded_rs2;
  wire [2:0] decoder_io_decoded_rd;
  wire [15:0] decoder_io_decoded_imm;
  wire [1:0] decoder_io_decoded_cc_mode;
  wire [3:0] decoder_io_decoded_alu_op;
  wire  decoder_io_decoded_bra_mask_z;
  wire  decoder_io_decoded_bra_mask_c;
  wire  decoder_io_decoded_bra_mask_n;
  wire  decoder_io_decoded_bra_mask_v;
  wire  decoder_io_decoded_has_jump;
  wire  decoder_io_decoded_has_stop;
  wire  decoder_io_decoded_has_branch;
  wire  decoder_io_decoded_has_mem;
  wire  decoder_io_decoded_has_wb;
  wire  decoder_io_decoded_has_imm;
  wire [15:0] alu_io_in1;
  wire [15:0] alu_io_in2;
  wire [3:0] alu_io_op;
  wire [15:0] alu_io_out;
  wire  alu_io_cc_z;
  wire  alu_io_cc_c;
  wire  alu_io_cc_n;
  wire  alu_io_cc_v;
  wire  regfile_clock;
  wire [2:0] regfile_io_rs1;
  wire [2:0] regfile_io_rs2;
  wire [15:0] regfile_io_rs1_dat;
  wire [15:0] regfile_io_rs2_dat;
  wire [2:0] regfile_io_rd;
  wire [15:0] regfile_io_rd_dat;
  wire  regfile_io_rd_en;
  wire  regfile_io_cc_in_z;
  wire  regfile_io_cc_in_c;
  wire  regfile_io_cc_in_n;
  wire  regfile_io_cc_in_v;
  wire  regfile_io_cc_en;
  wire  regfile_io_cc_out_z;
  wire  regfile_io_cc_out_c;
  wire  regfile_io_cc_out_n;
  wire  regfile_io_cc_out_v;
  reg [15:0] pc_reg;
  reg [31:0] ifetch_reg;
  reg [2:0] instr_reg_rd;
  reg [15:0] instr_reg_imm;
  reg [1:0] instr_reg_cc_mode;
  reg [3:0] instr_reg_alu_op;
  reg  instr_reg_bra_mask_z;
  reg  instr_reg_bra_mask_c;
  reg  instr_reg_bra_mask_n;
  reg  instr_reg_bra_mask_v;
  reg  instr_reg_has_jump;
  reg  instr_reg_has_stop;
  reg  instr_reg_has_branch;
  reg  instr_reg_has_mem;
  reg  instr_reg_has_wb;
  reg  instr_reg_has_imm;
  reg [15:0] rs1_reg;
  reg [15:0] rs2_reg;
  reg  cc_reg_z;
  reg  cc_reg_c;
  reg  cc_reg_n;
  reg  cc_reg_v;
  reg [15:0] result_reg;
  reg  result_cc_reg_z;
  reg  result_cc_reg_c;
  reg  result_cc_reg_n;
  reg  result_cc_reg_v;
  reg  REG;
  wire  _T_1 = io_state == 3'h3;
  wire [2:0] _pc_reg_T = io_instr_has_imm ? 3'h4 : 3'h2;
  wire [15:0] _GEN_40 = {{13'd0}, _pc_reg_T};
  wire [15:0] _pc_reg_T_2 = pc_reg + _GEN_40;
  wire [3:0] _take_branch_T = {io_instr_bra_mask_z,io_instr_bra_mask_c,io_instr_bra_mask_n,io_instr_bra_mask_v};
  wire [3:0] _take_branch_T_1 = {cc_reg_z,cc_reg_c,cc_reg_n,cc_reg_v};
  wire [3:0] _take_branch_T_2 = _take_branch_T & _take_branch_T_1;
  wire  take_branch = |_take_branch_T_2;
  wire  _T_4 = io_state == 3'h2;
  InstrDecoder decoder (
    .io_instr(decoder_io_instr),
    .io_imm(decoder_io_imm),
    .io_decoded_rs1(decoder_io_decoded_rs1),
    .io_decoded_rs2(decoder_io_decoded_rs2),
    .io_decoded_rd(decoder_io_decoded_rd),
    .io_decoded_imm(decoder_io_decoded_imm),
    .io_decoded_cc_mode(decoder_io_decoded_cc_mode),
    .io_decoded_alu_op(decoder_io_decoded_alu_op),
    .io_decoded_bra_mask_z(decoder_io_decoded_bra_mask_z),
    .io_decoded_bra_mask_c(decoder_io_decoded_bra_mask_c),
    .io_decoded_bra_mask_n(decoder_io_decoded_bra_mask_n),
    .io_decoded_bra_mask_v(decoder_io_decoded_bra_mask_v),
    .io_decoded_has_jump(decoder_io_decoded_has_jump),
    .io_decoded_has_stop(decoder_io_decoded_has_stop),
    .io_decoded_has_branch(decoder_io_decoded_has_branch),
    .io_decoded_has_mem(decoder_io_decoded_has_mem),
    .io_decoded_has_wb(decoder_io_decoded_has_wb),
    .io_decoded_has_imm(decoder_io_decoded_has_imm)
  );
  ALU alu (
    .io_in1(alu_io_in1),
    .io_in2(alu_io_in2),
    .io_op(alu_io_op),
    .io_out(alu_io_out),
    .io_cc_z(alu_io_cc_z),
    .io_cc_c(alu_io_cc_c),
    .io_cc_n(alu_io_cc_n),
    .io_cc_v(alu_io_cc_v)
  );
  RegFile regfile (
    .clock(regfile_clock),
    .io_rs1(regfile_io_rs1),
    .io_rs2(regfile_io_rs2),
    .io_rs1_dat(regfile_io_rs1_dat),
    .io_rs2_dat(regfile_io_rs2_dat),
    .io_rd(regfile_io_rd),
    .io_rd_dat(regfile_io_rd_dat),
    .io_rd_en(regfile_io_rd_en),
    .io_cc_in_z(regfile_io_cc_in_z),
    .io_cc_in_c(regfile_io_cc_in_c),
    .io_cc_in_n(regfile_io_cc_in_n),
    .io_cc_in_v(regfile_io_cc_in_v),
    .io_cc_en(regfile_io_cc_en),
    .io_cc_out_z(regfile_io_cc_out_z),
    .io_cc_out_c(regfile_io_cc_out_c),
    .io_cc_out_n(regfile_io_cc_out_n),
    .io_cc_out_v(regfile_io_cc_out_v)
  );
  assign io_instr_imm = instr_reg_imm;
  assign io_instr_bra_mask_z = instr_reg_bra_mask_z;
  assign io_instr_bra_mask_c = instr_reg_bra_mask_c;
  assign io_instr_bra_mask_n = instr_reg_bra_mask_n;
  assign io_instr_bra_mask_v = instr_reg_bra_mask_v;
  assign io_instr_has_jump = instr_reg_has_jump;
  assign io_instr_has_stop = instr_reg_has_stop;
  assign io_instr_has_branch = instr_reg_has_branch;
  assign io_instr_has_mem = instr_reg_has_mem;
  assign io_instr_has_wb = instr_reg_has_wb;
  assign io_instr_has_imm = instr_reg_has_imm;
  assign io_if_done = io_ibus_ack;
  assign io_mem_done = io_dbus_ack;
  assign io_ibus_addr = pc_reg;
  assign io_ibus_stb = io_issue_if;
  assign io_dbus_addr = result_reg;
  assign io_dbus_we = io_mem_we;
  assign io_dbus_data_wr = rs2_reg;
  assign io_dbus_stb = io_issue_mem;
  assign decoder_io_instr = ifetch_reg[31:16];
  assign decoder_io_imm = ifetch_reg[15:0];
  assign alu_io_in1 = rs1_reg;
  assign alu_io_in2 = instr_reg_has_imm ? instr_reg_imm : rs2_reg;
  assign alu_io_op = instr_reg_alu_op;
  assign regfile_clock = clock;
  assign regfile_io_rs1 = decoder_io_decoded_rs1;
  assign regfile_io_rs2 = decoder_io_decoded_rs2;
  assign regfile_io_rd = instr_reg_rd;
  assign regfile_io_rd_dat = result_reg;
  assign regfile_io_rd_en = io_state == 3'h6;
  assign regfile_io_cc_in_z = instr_reg_cc_mode == 2'h0 ? result_cc_reg_z : result_reg == 16'h0;
  assign regfile_io_cc_in_c = instr_reg_cc_mode == 2'h0 & result_cc_reg_c;
  assign regfile_io_cc_in_n = instr_reg_cc_mode == 2'h0 ? result_cc_reg_n : result_reg[15];
  assign regfile_io_cc_in_v = instr_reg_cc_mode == 2'h0 & result_cc_reg_v;
  assign regfile_io_cc_en = io_state == 3'h6 & instr_reg_cc_mode != 2'h2;
  always @(posedge clock) begin
    if (reset) begin
      pc_reg <= 16'h0;
    end else if (io_restart) begin
      if (~REG) begin
        pc_reg <= io_restart_pc;
      end
    end else if (io_state == 3'h3) begin
      if (io_instr_has_jump | io_instr_has_branch & take_branch) begin
        pc_reg <= io_instr_imm;
      end else begin
        pc_reg <= _pc_reg_T_2;
      end
    end
    if (reset) begin
      ifetch_reg <= 32'h0;
    end else if (io_ibus_ack) begin
      ifetch_reg <= io_ibus_data_rd;
    end
    if (reset) begin
      instr_reg_rd <= 3'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_rd <= decoder_io_decoded_rd;
    end
    if (reset) begin
      instr_reg_imm <= 16'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_imm <= decoder_io_decoded_imm;
    end
    if (reset) begin
      instr_reg_cc_mode <= 2'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_cc_mode <= decoder_io_decoded_cc_mode;
    end
    if (reset) begin
      instr_reg_alu_op <= 4'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_alu_op <= decoder_io_decoded_alu_op;
    end
    if (reset) begin
      instr_reg_bra_mask_z <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_z <= decoder_io_decoded_bra_mask_z;
    end
    if (reset) begin
      instr_reg_bra_mask_c <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_c <= decoder_io_decoded_bra_mask_c;
    end
    if (reset) begin
      instr_reg_bra_mask_n <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_n <= decoder_io_decoded_bra_mask_n;
    end
    if (reset) begin
      instr_reg_bra_mask_v <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_v <= decoder_io_decoded_bra_mask_v;
    end
    if (reset) begin
      instr_reg_has_jump <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_jump <= decoder_io_decoded_has_jump;
    end
    if (reset) begin
      instr_reg_has_stop <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_stop <= decoder_io_decoded_has_stop;
    end
    if (reset) begin
      instr_reg_has_branch <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_branch <= decoder_io_decoded_has_branch;
    end
    if (reset) begin
      instr_reg_has_mem <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_mem <= decoder_io_decoded_has_mem;
    end
    if (reset) begin
      instr_reg_has_wb <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_wb <= decoder_io_decoded_has_wb;
    end
    if (reset) begin
      instr_reg_has_imm <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_imm <= decoder_io_decoded_has_imm;
    end
    if (reset) begin
      rs1_reg <= 16'h0;
    end else if (_T_4) begin
      rs1_reg <= regfile_io_rs1_dat;
    end
    if (reset) begin
      rs2_reg <= 16'h0;
    end else if (_T_4) begin
      rs2_reg <= regfile_io_rs2_dat;
    end
    if (reset) begin
      cc_reg_z <= 1'h0;
    end else if (_T_4) begin
      cc_reg_z <= regfile_io_cc_out_z;
    end
    if (reset) begin
      cc_reg_c <= 1'h0;
    end else if (_T_4) begin
      cc_reg_c <= regfile_io_cc_out_c;
    end
    if (reset) begin
      cc_reg_n <= 1'h0;
    end else if (_T_4) begin
      cc_reg_n <= regfile_io_cc_out_n;
    end
    if (reset) begin
      cc_reg_v <= 1'h0;
    end else if (_T_4) begin
      cc_reg_v <= regfile_io_cc_out_v;
    end
    if (reset) begin
      result_reg <= 16'h0;
    end else if (io_state == 3'h5 & ~io_mem_we & io_dbus_ack) begin
      result_reg <= io_dbus_data_rd;
    end else if (_T_1) begin
      result_reg <= alu_io_out;
    end
    if (reset) begin
      result_cc_reg_z <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_z <= alu_io_cc_z;
    end
    if (reset) begin
      result_cc_reg_c <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_c <= alu_io_cc_c;
    end
    if (reset) begin
      result_cc_reg_n <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_n <= alu_io_cc_n;
    end
    if (reset) begin
      result_cc_reg_v <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_v <= alu_io_cc_v;
    end
    REG <= io_restart;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pc_reg = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  ifetch_reg = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  instr_reg_rd = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  instr_reg_imm = _RAND_3[15:0];
  _RAND_4 = {1{`RANDOM}};
  instr_reg_cc_mode = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  instr_reg_alu_op = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  instr_reg_bra_mask_z = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  instr_reg_bra_mask_c = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  instr_reg_bra_mask_n = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  instr_reg_bra_mask_v = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  instr_reg_has_jump = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  instr_reg_has_stop = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  instr_reg_has_branch = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  instr_reg_has_mem = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  instr_reg_has_wb = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  instr_reg_has_imm = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  rs1_reg = _RAND_16[15:0];
  _RAND_17 = {1{`RANDOM}};
  rs2_reg = _RAND_17[15:0];
  _RAND_18 = {1{`RANDOM}};
  cc_reg_z = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  cc_reg_c = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  cc_reg_n = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  cc_reg_v = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  result_reg = _RAND_22[15:0];
  _RAND_23 = {1{`RANDOM}};
  result_cc_reg_z = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  result_cc_reg_c = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  result_cc_reg_n = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  result_cc_reg_v = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  REG = _RAND_27[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Datapath(
  input         clock,
  input         reset,
  output [15:0] io_instr_imm,
  output        io_instr_bra_mask_z,
  output        io_instr_bra_mask_c,
  output        io_instr_bra_mask_n,
  output        io_instr_bra_mask_v,
  output        io_instr_has_jump,
  output        io_instr_has_stop,
  output        io_instr_has_branch,
  output        io_instr_has_mem,
  output        io_instr_has_wb,
  output        io_instr_has_imm,
  input         io_issue_if,
  output        io_if_done,
  input         io_issue_mem,
  input         io_mem_we,
  output        io_mem_done,
  input  [2:0]  io_state,
  output [15:0] io_ibus_addr,
  input  [31:0] io_ibus_data_rd,
  output        io_ibus_stb,
  input         io_ibus_ack,
  output [15:0] io_dbus_addr,
  output        io_dbus_we,
  input  [15:0] io_dbus_data_rd,
  output [15:0] io_dbus_data_wr,
  output        io_dbus_stb,
  input         io_dbus_ack,
  input  [15:0] io_restart_pc,
  input         io_restart
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
`endif
  wire [15:0] decoder_io_instr;
  wire [15:0] decoder_io_imm;
  wire [2:0] decoder_io_decoded_rs1;
  wire [2:0] decoder_io_decoded_rs2;
  wire [2:0] decoder_io_decoded_rd;
  wire [15:0] decoder_io_decoded_imm;
  wire [1:0] decoder_io_decoded_cc_mode;
  wire [3:0] decoder_io_decoded_alu_op;
  wire  decoder_io_decoded_bra_mask_z;
  wire  decoder_io_decoded_bra_mask_c;
  wire  decoder_io_decoded_bra_mask_n;
  wire  decoder_io_decoded_bra_mask_v;
  wire  decoder_io_decoded_has_jump;
  wire  decoder_io_decoded_has_stop;
  wire  decoder_io_decoded_has_branch;
  wire  decoder_io_decoded_has_mem;
  wire  decoder_io_decoded_has_wb;
  wire  decoder_io_decoded_has_imm;
  wire [15:0] alu_io_in1;
  wire [15:0] alu_io_in2;
  wire [3:0] alu_io_op;
  wire [15:0] alu_io_out;
  wire  alu_io_cc_z;
  wire  alu_io_cc_c;
  wire  alu_io_cc_n;
  wire  alu_io_cc_v;
  wire  regfile_clock;
  wire [2:0] regfile_io_rs1;
  wire [2:0] regfile_io_rs2;
  wire [15:0] regfile_io_rs1_dat;
  wire [15:0] regfile_io_rs2_dat;
  wire [2:0] regfile_io_rd;
  wire [15:0] regfile_io_rd_dat;
  wire  regfile_io_rd_en;
  wire  regfile_io_cc_in_z;
  wire  regfile_io_cc_in_c;
  wire  regfile_io_cc_in_n;
  wire  regfile_io_cc_in_v;
  wire  regfile_io_cc_en;
  wire  regfile_io_cc_out_z;
  wire  regfile_io_cc_out_c;
  wire  regfile_io_cc_out_n;
  wire  regfile_io_cc_out_v;
  reg [15:0] pc_reg;
  reg [31:0] ifetch_reg;
  reg [2:0] instr_reg_rd;
  reg [15:0] instr_reg_imm;
  reg [1:0] instr_reg_cc_mode;
  reg [3:0] instr_reg_alu_op;
  reg  instr_reg_bra_mask_z;
  reg  instr_reg_bra_mask_c;
  reg  instr_reg_bra_mask_n;
  reg  instr_reg_bra_mask_v;
  reg  instr_reg_has_jump;
  reg  instr_reg_has_stop;
  reg  instr_reg_has_branch;
  reg  instr_reg_has_mem;
  reg  instr_reg_has_wb;
  reg  instr_reg_has_imm;
  reg [15:0] rs1_reg;
  reg [15:0] rs2_reg;
  reg  cc_reg_z;
  reg  cc_reg_c;
  reg  cc_reg_n;
  reg  cc_reg_v;
  reg [15:0] result_reg;
  reg  result_cc_reg_z;
  reg  result_cc_reg_c;
  reg  result_cc_reg_n;
  reg  result_cc_reg_v;
  reg  REG;
  wire  _T_1 = io_state == 3'h3;
  wire [2:0] _pc_reg_T = io_instr_has_imm ? 3'h4 : 3'h2;
  wire [15:0] _GEN_40 = {{13'd0}, _pc_reg_T};
  wire [15:0] _pc_reg_T_2 = pc_reg + _GEN_40;
  wire [3:0] _take_branch_T = {io_instr_bra_mask_z,io_instr_bra_mask_c,io_instr_bra_mask_n,io_instr_bra_mask_v};
  wire [3:0] _take_branch_T_1 = {cc_reg_z,cc_reg_c,cc_reg_n,cc_reg_v};
  wire [3:0] _take_branch_T_2 = _take_branch_T & _take_branch_T_1;
  wire  take_branch = |_take_branch_T_2;
  wire  _T_4 = io_state == 3'h2;
  InstrDecoder decoder (
    .io_instr(decoder_io_instr),
    .io_imm(decoder_io_imm),
    .io_decoded_rs1(decoder_io_decoded_rs1),
    .io_decoded_rs2(decoder_io_decoded_rs2),
    .io_decoded_rd(decoder_io_decoded_rd),
    .io_decoded_imm(decoder_io_decoded_imm),
    .io_decoded_cc_mode(decoder_io_decoded_cc_mode),
    .io_decoded_alu_op(decoder_io_decoded_alu_op),
    .io_decoded_bra_mask_z(decoder_io_decoded_bra_mask_z),
    .io_decoded_bra_mask_c(decoder_io_decoded_bra_mask_c),
    .io_decoded_bra_mask_n(decoder_io_decoded_bra_mask_n),
    .io_decoded_bra_mask_v(decoder_io_decoded_bra_mask_v),
    .io_decoded_has_jump(decoder_io_decoded_has_jump),
    .io_decoded_has_stop(decoder_io_decoded_has_stop),
    .io_decoded_has_branch(decoder_io_decoded_has_branch),
    .io_decoded_has_mem(decoder_io_decoded_has_mem),
    .io_decoded_has_wb(decoder_io_decoded_has_wb),
    .io_decoded_has_imm(decoder_io_decoded_has_imm)
  );
  ALU alu (
    .io_in1(alu_io_in1),
    .io_in2(alu_io_in2),
    .io_op(alu_io_op),
    .io_out(alu_io_out),
    .io_cc_z(alu_io_cc_z),
    .io_cc_c(alu_io_cc_c),
    .io_cc_n(alu_io_cc_n),
    .io_cc_v(alu_io_cc_v)
  );
  RegFile regfile (
    .clock(regfile_clock),
    .io_rs1(regfile_io_rs1),
    .io_rs2(regfile_io_rs2),
    .io_rs1_dat(regfile_io_rs1_dat),
    .io_rs2_dat(regfile_io_rs2_dat),
    .io_rd(regfile_io_rd),
    .io_rd_dat(regfile_io_rd_dat),
    .io_rd_en(regfile_io_rd_en),
    .io_cc_in_z(regfile_io_cc_in_z),
    .io_cc_in_c(regfile_io_cc_in_c),
    .io_cc_in_n(regfile_io_cc_in_n),
    .io_cc_in_v(regfile_io_cc_in_v),
    .io_cc_en(regfile_io_cc_en),
    .io_cc_out_z(regfile_io_cc_out_z),
    .io_cc_out_c(regfile_io_cc_out_c),
    .io_cc_out_n(regfile_io_cc_out_n),
    .io_cc_out_v(regfile_io_cc_out_v)
  );
  assign io_instr_imm = instr_reg_imm;
  assign io_instr_bra_mask_z = instr_reg_bra_mask_z;
  assign io_instr_bra_mask_c = instr_reg_bra_mask_c;
  assign io_instr_bra_mask_n = instr_reg_bra_mask_n;
  assign io_instr_bra_mask_v = instr_reg_bra_mask_v;
  assign io_instr_has_jump = instr_reg_has_jump;
  assign io_instr_has_stop = instr_reg_has_stop;
  assign io_instr_has_branch = instr_reg_has_branch;
  assign io_instr_has_mem = instr_reg_has_mem;
  assign io_instr_has_wb = instr_reg_has_wb;
  assign io_instr_has_imm = instr_reg_has_imm;
  assign io_if_done = io_ibus_ack;
  assign io_mem_done = io_dbus_ack;
  assign io_ibus_addr = pc_reg;
  assign io_ibus_stb = io_issue_if;
  assign io_dbus_addr = result_reg;
  assign io_dbus_we = io_mem_we;
  assign io_dbus_data_wr = rs2_reg;
  assign io_dbus_stb = io_issue_mem;
  assign decoder_io_instr = ifetch_reg[31:16];
  assign decoder_io_imm = ifetch_reg[15:0];
  assign alu_io_in1 = rs1_reg;
  assign alu_io_in2 = instr_reg_has_imm ? instr_reg_imm : rs2_reg;
  assign alu_io_op = instr_reg_alu_op;
  assign regfile_clock = clock;
  assign regfile_io_rs1 = decoder_io_decoded_rs1;
  assign regfile_io_rs2 = decoder_io_decoded_rs2;
  assign regfile_io_rd = instr_reg_rd;
  assign regfile_io_rd_dat = result_reg;
  assign regfile_io_rd_en = io_state == 3'h6;
  assign regfile_io_cc_in_z = instr_reg_cc_mode == 2'h0 ? result_cc_reg_z : result_reg == 16'h0;
  assign regfile_io_cc_in_c = instr_reg_cc_mode == 2'h0 & result_cc_reg_c;
  assign regfile_io_cc_in_n = instr_reg_cc_mode == 2'h0 ? result_cc_reg_n : result_reg[15];
  assign regfile_io_cc_in_v = instr_reg_cc_mode == 2'h0 & result_cc_reg_v;
  assign regfile_io_cc_en = io_state == 3'h6 & instr_reg_cc_mode != 2'h2;
  always @(posedge clock) begin
    if (reset) begin
      pc_reg <= 16'h0;
    end else if (io_restart) begin
      if (~REG) begin
        pc_reg <= io_restart_pc;
      end
    end else if (io_state == 3'h3) begin
      if (io_instr_has_jump | io_instr_has_branch & take_branch) begin
        pc_reg <= io_instr_imm;
      end else begin
        pc_reg <= _pc_reg_T_2;
      end
    end
    if (reset) begin
      ifetch_reg <= 32'h0;
    end else if (io_ibus_ack) begin
      ifetch_reg <= io_ibus_data_rd;
    end
    if (reset) begin
      instr_reg_rd <= 3'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_rd <= decoder_io_decoded_rd;
    end
    if (reset) begin
      instr_reg_imm <= 16'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_imm <= decoder_io_decoded_imm;
    end
    if (reset) begin
      instr_reg_cc_mode <= 2'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_cc_mode <= decoder_io_decoded_cc_mode;
    end
    if (reset) begin
      instr_reg_alu_op <= 4'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_alu_op <= decoder_io_decoded_alu_op;
    end
    if (reset) begin
      instr_reg_bra_mask_z <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_z <= decoder_io_decoded_bra_mask_z;
    end
    if (reset) begin
      instr_reg_bra_mask_c <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_c <= decoder_io_decoded_bra_mask_c;
    end
    if (reset) begin
      instr_reg_bra_mask_n <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_n <= decoder_io_decoded_bra_mask_n;
    end
    if (reset) begin
      instr_reg_bra_mask_v <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_bra_mask_v <= decoder_io_decoded_bra_mask_v;
    end
    if (reset) begin
      instr_reg_has_jump <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_jump <= decoder_io_decoded_has_jump;
    end
    if (reset) begin
      instr_reg_has_stop <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_stop <= decoder_io_decoded_has_stop;
    end
    if (reset) begin
      instr_reg_has_branch <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_branch <= decoder_io_decoded_has_branch;
    end
    if (reset) begin
      instr_reg_has_mem <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_mem <= decoder_io_decoded_has_mem;
    end
    if (reset) begin
      instr_reg_has_wb <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_wb <= decoder_io_decoded_has_wb;
    end
    if (reset) begin
      instr_reg_has_imm <= 1'h0;
    end else if (io_state == 3'h2) begin
      instr_reg_has_imm <= decoder_io_decoded_has_imm;
    end
    if (reset) begin
      rs1_reg <= 16'h0;
    end else if (_T_4) begin
      rs1_reg <= regfile_io_rs1_dat;
    end
    if (reset) begin
      rs2_reg <= 16'h0;
    end else if (_T_4) begin
      rs2_reg <= regfile_io_rs2_dat;
    end
    if (reset) begin
      cc_reg_z <= 1'h0;
    end else if (_T_4) begin
      cc_reg_z <= regfile_io_cc_out_z;
    end
    if (reset) begin
      cc_reg_c <= 1'h0;
    end else if (_T_4) begin
      cc_reg_c <= regfile_io_cc_out_c;
    end
    if (reset) begin
      cc_reg_n <= 1'h0;
    end else if (_T_4) begin
      cc_reg_n <= regfile_io_cc_out_n;
    end
    if (reset) begin
      cc_reg_v <= 1'h0;
    end else if (_T_4) begin
      cc_reg_v <= regfile_io_cc_out_v;
    end
    if (reset) begin
      result_reg <= 16'h0;
    end else if (io_state == 3'h5 & ~io_mem_we & io_dbus_ack) begin
      result_reg <= io_dbus_data_rd;
    end else if (_T_1) begin
      result_reg <= alu_io_out;
    end
    if (reset) begin
      result_cc_reg_z <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_z <= alu_io_cc_z;
    end
    if (reset) begin
      result_cc_reg_c <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_c <= alu_io_cc_c;
    end
    if (reset) begin
      result_cc_reg_n <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_n <= alu_io_cc_n;
    end
    if (reset) begin
      result_cc_reg_v <= 1'h0;
    end else if (_T_1) begin
      result_cc_reg_v <= alu_io_cc_v;
    end
    REG <= io_restart;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pc_reg = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  ifetch_reg = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  instr_reg_rd = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  instr_reg_imm = _RAND_3[15:0];
  _RAND_4 = {1{`RANDOM}};
  instr_reg_cc_mode = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  instr_reg_alu_op = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  instr_reg_bra_mask_z = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  instr_reg_bra_mask_c = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  instr_reg_bra_mask_n = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  instr_reg_bra_mask_v = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  instr_reg_has_jump = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  instr_reg_has_stop = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  instr_reg_has_branch = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  instr_reg_has_mem = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  instr_reg_has_wb = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  instr_reg_has_imm = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  rs1_reg = _RAND_16[15:0];
  _RAND_17 = {1{`RANDOM}};
  rs2_reg = _RAND_17[15:0];
  _RAND_18 = {1{`RANDOM}};
  cc_reg_z = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  cc_reg_c = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  cc_reg_n = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  cc_reg_v = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  result_reg = _RAND_22[15:0];
  _RAND_23 = {1{`RANDOM}};
  result_cc_reg_z = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  result_cc_reg_c = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  result_cc_reg_n = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  result_cc_reg_v = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  REG = _RAND_27[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule