data/full_repos/permissive/475231219/module/addsub.v
1: b"%Error: data/full_repos/permissive/475231219/module/addsub.v:12: Cannot find file containing module: 'add16'\n    add16 d1(a[15:0],b1[15:0],sub,sum[15:0],cout);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/475231219/module,data/full_repos/permissive/475231219/add16\n             data/full_repos/permissive/475231219/module,data/full_repos/permissive/475231219/add16.v\n             data/full_repos/permissive/475231219/module,data/full_repos/permissive/475231219/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/475231219/module/addsub.v:13: Cannot find file containing module: 'add16'\n    add16 d2(a[31:16],b1[31:16],cout,sum[31:16],);\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [31:0] b1;
    assign b1 = b^{32{sub}};
    wire cout;
    add16 d1(a[15:0],b1[15:0],sub,sum[15:0],cout);
    add16 d2(a[31:16],b1[31:16],cout,sum[31:16],);
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

    wire [31:0] b1;
    assign b1 = b^{32{sub}};
    wire cout;
    add16 d1(a[15:0],b1[15:0],sub,sum[15:0],cout);
    add16 d2(a[31:16],b1[31:16],cout,sum[31:16],);
endmodule