data/full_repos/permissive/441359809/src/yosys/techlibs/intel/common/ff_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/common/ff_map.v:7: Cannot find file containing module: \'dffeas\'\n     dffeas #(.is_wysiwyg("TRUE"), .power_up("low")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1\'b1), .ena(E), .asdata(1\'b0), .aload(1\'b0), .sclr(1\'b0), .sload(1\'b0));\n     ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/common,data/full_repos/permissive/441359809/dffeas\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/common,data/full_repos/permissive/441359809/dffeas.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/common,data/full_repos/permissive/441359809/dffeas.sv\n             dffeas\n             dffeas.v\n             dffeas.sv\n             obj_dir/dffeas\n             obj_dir/dffeas.v\n             obj_dir/dffeas.sv\n%Error: Exiting due to 1 error(s)\n'
module  \$_DFFE_PN0P_ (input D, C, R, E, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin
     dffeas #(.is_wysiwyg("TRUE"), .power_up("high")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
   end else begin
     dffeas #(.is_wysiwyg("TRUE"), .power_up("low")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
   end
   endgenerate
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module  \$_DFFE_PN0P_ (input D, C, R, E, output Q);

   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin
     dffeas #(.is_wysiwyg("TRUE"), .power_up("high")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
   end else begin
     dffeas #(.is_wysiwyg("TRUE"), .power_up("low")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
   end
   endgenerate
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule