data/full_repos/permissive/458208177/test/mux_2_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458208177/test/mux_2_1_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458208177/test/mux_2_1_tb.v:17: Cannot find file containing module: \'mux_2_1\'\nmux_2_1 M1(out, A, B, select);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/mux_2_1\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/mux_2_1.v\n             data/full_repos/permissive/458208177/test,data/full_repos/permissive/458208177/mux_2_1.sv\n             mux_2_1\n             mux_2_1.v\n             mux_2_1.sv\n             obj_dir/mux_2_1\n             obj_dir/mux_2_1.v\n             obj_dir/mux_2_1.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_mux_2_1;

wire        out;

reg         check;
reg         A, B, select;

reg[2:0] i;


integer num_correct;
integer num_wrong;


mux_2_1 M1(out, A, B, select);


initial begin
  $display("Running testbench, this may take a minute or two...");


  num_correct = 0; num_wrong = 0;

  for (i = 0; i < 6; i = i+1) begin

    {A, B, select} = i;
    #2;
    if (!select) begin
      check = A;
    end else begin
      check = B;
    end

    if (out == check) begin
      num_correct = num_correct + 1;
    end else begin
      num_wrong = num_wrong + 1;
      $display($time, " ASSERTION ERROR: input (A, B, select) = %b, output_from_chip = %b, output_from_checker = %b", i, out, check);
    end

  end


  $display("num_correct = %d, num_wrong = %d", num_correct, num_wrong);


  $finish;
end

endmodule
module t_mux_2_1;


wire        out;

reg         check;
reg         A, B, select;

reg[2:0] i;


integer num_correct;
integer num_wrong;


mux_2_1 M1(out, A, B, select);


initial begin
  $display("Running testbench, this may take a minute or two...");


  num_correct = 0; num_wrong = 0;

  for (i = 0; i < 6; i = i+1) begin

    {A, B, select} = i;
    #2;
    if (!select) begin
      check = A;
    end else begin
      check = B;
    end

    if (out == check) begin
      num_correct = num_correct + 1;
    end else begin
      num_wrong = num_wrong + 1;
      $display($time, " ASSERTION ERROR: input (A, B, select) = %b, output_from_chip = %b, output_from_checker = %b", i, out, check);
    end

  end


  $display("num_correct = %d, num_wrong = %d", num_correct, num_wrong);


  $finish;
end

endmodule