data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/pc_adder.v
data/verilator_xmls/3f0d25a4-60ce-44a4-a3e2-4ae7eac8c9af.xml
module pc_adder(
    input [31:0] pc,
    output reg [31:0] next_pc
    );
    
    initial next_pc = 100;
    
    always @(*) begin
        next_pc <= pc + 32'd4;
    end
endmodule
module pc_adder(
    input [31:0] pc,
    output reg [31:0] next_pc
    );

    
    initial next_pc = 100;
    
    always @(*) begin
        next_pc <= pc + 32'd4;
    end
endmodule