data/full_repos/permissive/441359809/src/yosys/tests/simple/arraycells.v
data/verilator_xmls/6aecb8fc-94c6-4b17-b8e6-4cc5b5faeabb.xml
module aoi12(a, b, c, y);
	input a, b, c;
	output y;
	assign y = ~((a & b) | c);
endmodule
module aoi12(a, b, c, y);

	input a, b, c;
	output y;
	assign y = ~((a & b) | c);
endmodule