data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATDFF2_SET.v
data/verilator_xmls/5a5228af-cfc6-483d-a2c6-c386a9fe6ca0.xml
module ATDFF2_SET
    (
     D,
     CK,
     SET_,
     Q
     );
input   D,CK,SET_;
output  Q;


reg     Q;
always @(posedge CK or negedge SET_)
    begin
    if (!SET_) Q <= 1'b1;
    else Q <= D;
    end
endmodule
module ATDFF2_SET
    (
     D,
     CK,
     SET_,
     Q
     );

input   D,CK,SET_;
output  Q;


reg     Q;
always @(posedge CK or negedge SET_)
    begin
    if (!SET_) Q <= 1'b1;
    else Q <= D;
    end
endmodule