data/full_repos/permissive/509691520/top_FSMplusD_testbench.v
1: b'%Error: data/full_repos/permissive/509691520/top_FSMplusD_testbench.v:19: Unsupported or unknown PLI call: $monitor\n      $monitor($time, " R1=%d, R2=%d, R3=%d, PS=%d, NS=%d", R1, R2, R3, PS, NS);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/509691520/top_FSMplusD_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("top_FSMplusD.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/509691520/top_FSMplusD_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, top_FSMplusD_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509691520/top_FSMplusD_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #0 clock=0; reset=1; a=1; b=2; c=3; d=4; e=5;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509691520/top_FSMplusD_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #50 clock = ~clock; reset=0;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_FSMplusD_tb ();

  reg clock, reset;
  reg [3:0] a, b, c, d, e;
  wire [3:0] R1, R2, R3, PS, NS;

  top_FSMplusD DUT (
    .clock(clock), .reset(reset),
    .a(a), .b(b), .c(c), .d(d), .e(e),
    .R1(R1), .R2(R2), .R3(R3), .PS(PS), .NS(NS)
  );

  initial
    begin
      $monitor($time, " R1=%d, R2=%d, R3=%d, PS=%d, NS=%d", R1, R2, R3, PS, NS);
    end

  initial
    begin
      $dumpfile("top_FSMplusD.vcd");
      $dumpvars(1, top_FSMplusD_tb);

      #0 clock=0; reset=1; a=1; b=2; c=3; d=4; e=5;

      repeat(100) begin
        #50 clock = ~clock; reset=0;
      end

    end

endmodule
module top_FSMplusD_tb ();


  reg clock, reset;
  reg [3:0] a, b, c, d, e;
  wire [3:0] R1, R2, R3, PS, NS;

  top_FSMplusD DUT (
    .clock(clock), .reset(reset),
    .a(a), .b(b), .c(c), .d(d), .e(e),
    .R1(R1), .R2(R2), .R3(R3), .PS(PS), .NS(NS)
  );

  initial
    begin
      $monitor($time, " R1=%d, R2=%d, R3=%d, PS=%d, NS=%d", R1, R2, R3, PS, NS);
    end

  initial
    begin
      $dumpfile("top_FSMplusD.vcd");
      $dumpvars(1, top_FSMplusD_tb);

      #0 clock=0; reset=1; a=1; b=2; c=3; d=4; e=5;

      repeat(100) begin
        #50 clock = ~clock; reset=0;
      end

    end

endmodule