data/full_repos/permissive/448063237/TropicalAluTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/448063237/TropicalAluTest.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/448063237/TropicalAluTest.v:7: Cannot find file containing module: \'TropicalALU\'\n TropicalALU uut(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448063237,data/full_repos/permissive/448063237/TropicalALU\n             data/full_repos/permissive/448063237,data/full_repos/permissive/448063237/TropicalALU.v\n             data/full_repos/permissive/448063237,data/full_repos/permissive/448063237/TropicalALU.sv\n             TropicalALU\n             TropicalALU.v\n             TropicalALU.sv\n             obj_dir/TropicalALU\n             obj_dir/TropicalALU.v\n             obj_dir/TropicalALU.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TropicalALUTest();
	reg clk;
	wire [31:0] Instr_code,ALU_result;
	
	TropicalALU uut(
		.clk(clk),
		.Instr_code(Instr_code),
		.ALU_result(ALU_result)
		);
	
	initial 
		begin
			clk = 0;
		end
	
	always
		begin
		#10 clk = ~clk;		
		end

endmodule
module TropicalALUTest();

	reg clk;
	wire [31:0] Instr_code,ALU_result;
	
	TropicalALU uut(
		.clk(clk),
		.Instr_code(Instr_code),
		.ALU_result(ALU_result)
		);
	
	initial 
		begin
			clk = 0;
		end
	
	always
		begin
		#10 clk = ~clk;		
		end

endmodule