data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:9: Define or directive not defined: \'`outfile\'\n  file = $fopen(`outfile);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  file = $fopen(`outfile);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 1;     \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable = 1;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #100 enable = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock;  \n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module testbench();

reg clock = 1, reset = 0, enable = 0;
wire [3:0] counter_out;
integer file;


initial begin        
  file = $fopen(`outfile);
  $fdisplay (file, "time\t clk reset enable counter");	
  #5 reset = 1;
  #10 reset = 0;
  #10 enable = 1;
  #100 enable = 0;
  #5 $finish;
end

always @(negedge clock)
  $fdisplay (file, "%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out);	


initial begin
  #1;
  forever
    #5 clock = ~clock;
end


first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule
module testbench();


reg clock = 1, reset = 0, enable = 0;
wire [3:0] counter_out;
integer file;


initial begin        
  file = $fopen(`outfile);
  $fdisplay (file, "time\t clk reset enable counter");	
  #5 reset = 1;
  #10 reset = 0;
  #10 enable = 1;
  #100 enable = 0;
  #5 $finish;
end

always @(negedge clock)
  $fdisplay (file, "%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out);	


initial begin
  #1;
  forever
    #5 clock = ~clock;
end


first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule