data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v
1: b'%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:20: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425928416/verilog/dv/jacaranda_test,data/full_repos/permissive/425928416/uprj_netlists.v\n             data/full_repos/permissive/425928416/verilog/dv/jacaranda_test,data/full_repos/permissive/425928416/uprj_netlists.v.v\n             data/full_repos/permissive/425928416/verilog/dv/jacaranda_test,data/full_repos/permissive/425928416/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:21: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:22: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("jacaranda_test.fst");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, jacaranda_test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:50: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425928416/verilog/dv/jacaranda_test/jacaranda_test_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module jacaranda_test_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("jacaranda_test.fst");
		$dumpvars(0, jacaranda_test_tb);


		repeat (70) begin
			repeat (1000) @(posedge clock);
			    $display("+1000 cycles");
		end
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("jacaranda_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module jacaranda_test_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("jacaranda_test.fst");
		$dumpvars(0, jacaranda_test_tb);


		repeat (70) begin
			repeat (1000) @(posedge clock);
			    $display("+1000 cycles");
		end
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("jacaranda_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule