data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:115: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'rvdffsc\'\nmodule rvdffsc (\n       ^~~~~~~\n                                                                                     : ... Top module \'rvdffs_fpga\'\nmodule rvdffs_fpga (\n       ^~~~~~~~~~~\n                                                                                     : ... Top module \'rvdffsc_fpga\'\nmodule rvdffsc_fpga (\n       ^~~~~~~~~~~~\n                                                                                     : ... Top module \'rvdffe\'\nmodule rvdffe (\n       ^~~~~~\n                                                                                     : ... Top module \'rvdffpcie\'\nmodule rvdffpcie (\n       ^~~~~~~~~\n                                                                                     : ... Top module \'rvdfflie\'\nmodule rvdfflie (\n       ^~~~~~~~\n                                                                                     : ... Top module \'rvdffppe\'\nmodule rvdffppe (\n       ^~~~~~~~\n                                                                                     : ... Top module \'rvdffie\'\nmodule rvdffie (\n       ^~~~~~~\n                                                                                     : ... Top module \'rvdffiee\'\nmodule rvdffiee (\n       ^~~~~~~~\n                                                                                     : ... Top module \'rvsyncss\'\nmodule rvsyncss (\n       ^~~~~~~~\n                                                                                     : ... Top module \'rvsyncss_fpga\'\nmodule rvsyncss_fpga (\n       ^~~~~~~~~~~~~\n                                                                                     : ... Top module \'rvlsadder\'\nmodule rvlsadder (\n       ^~~~~~~~~\n                                                                                     : ... Top module \'rvbradder\'\nmodule rvbradder (\n       ^~~~~~~~~\n                                                                                     : ... Top module \'rvtwoscomp\'\nmodule rvtwoscomp (\n       ^~~~~~~~~~\n                                                                                     : ... Top module \'rvfindfirst1\'\nmodule rvfindfirst1 (\n       ^~~~~~~~~~~~\n                                                                                     : ... Top module \'rvfindfirst1hot\'\nmodule rvfindfirst1hot (\n       ^~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'rvmaskandmatch\'\nmodule rvmaskandmatch (\n       ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'rvrangecheck\'\nmodule rvrangecheck (\n       ^~~~~~~~~~~~\n                                                                                     : ... Top module \'rveven_paritygen\'\nmodule rveven_paritygen (\n       ^~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'rveven_paritycheck\'\nmodule rveven_paritycheck (\n       ^~~~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'rvecc_encode\'\nmodule rvecc_encode (\n       ^~~~~~~~~~~~\n                                                                                     : ... Top module \'rvecc_decode\'\nmodule rvecc_decode (\n       ^~~~~~~~~~~~\n                                                                                     : ... Top module \'rvecc_encode_64\'\nmodule rvecc_encode_64 (\n       ^~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'rvecc_decode_64\'\nmodule rvecc_decode_64 (\n       ^~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'clockhdr\'\nmodule clockhdr (\n       ^~~~~~~~\n                                                                                     : ... Top module \'rvoclkhdr\'\nmodule rvoclkhdr (\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:46: Input port connection \'din\' expects 1 bits on the pin connection, but pin connection\'s COND generates 31 bits.\n                                                                                 : ... In instance rvdffpcie.genblock.dff\n    .din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])),\n     ^~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:49: Output port connection \'dout\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'dout\' generates 31 bits.\n                                                                                 : ... In instance rvdffpcie.genblock.dff\n    .dout(dout)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:46: Input port connection \'din\' expects 1 bits on the pin connection, but pin connection\'s COND generates 16 bits.\n                                                                                 : ... In instance rvdfflie.genblock.dff\n    .din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])),\n     ^~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:49: Output port connection \'dout\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'dout\' generates 16 bits.\n                                                                                 : ... In instance rvdfflie.genblock.dff\n    .dout(dout)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:46: Input port connection \'din\' expects 1 bits on the pin connection, but pin connection\'s COND generates 251 bits.\n                                                                                 : ... In instance rvsyncss_fpga.sync_ff1.genblk2.dffs\n    .din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])),\n     ^~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:49: Output port connection \'dout\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'dout\' generates 251 bits.\n                                                                                 : ... In instance rvsyncss_fpga.sync_ff1.genblk2.dffs\n    .dout(dout)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:497: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                  : ... In instance rvfindfirst1\n     dout[SHIFT - 1:0] = dout[SHIFT - 1:0] + (done ? 1\'b0 : 1\'b1);\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/493514142/verilog/rtl/FPU/beh_lib.v:497: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                  : ... In instance rvfindfirst1\n     dout[SHIFT - 1:0] = dout[SHIFT - 1:0] + (done ? 1\'b0 : 1\'b1);\n                                                   ^\n%Error: Exiting due to 9 warning(s)\n'
module clockhdr (
	SE,
	EN,
	CK,
	Q
);
	input wire SE;
	input wire EN;
	input wire CK;
	output Q;
	reg en_ff;
	wire enable;
	assign enable = EN | SE;
	always @(CK or enable)
		if (!CK)
			en_ff = enable;
	assign Q = CK & en_ff;
endmodule
module clockhdr (
	SE,
	EN,
	CK,
	Q
);

	input wire SE;
	input wire EN;
	input wire CK;
	output Q;
	reg en_ff;
	wire enable;
	assign enable = EN | SE;
	always @(CK or enable)
		if (!CK)
			en_ff = enable;
	assign Q = CK & en_ff;
endmodule