data/full_repos/permissive/460468583/data/yosys/machxo2/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/machxo2/cells_sim.v:154: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'FACADE_SLICE\'\nmodule FACADE_SLICE #(\n       ^~~~~~~~~~~~\n                                                                                          : ... Top module \'FACADE_IO\'\nmodule FACADE_IO #(\n       ^~~~~~~~~\n                                                                                          : ... Top module \'OSCH\'\nmodule OSCH #(\n       ^~~~\n                                                                                          : ... Top module \'DCCA\'\nmodule DCCA (\n       ^~~~\n                                                                                          : ... Top module \'DCMA\'\nmodule DCMA (\n       ^~~~\n                                                                                          : ... Top module \'$__FACADE_OUTPAD\'\nmodule  \\$__FACADE_OUTPAD (input I, output O); endmodule\n        ^~~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'$__FACADE_INPAD\'\nmodule  \\$__FACADE_INPAD (input I, output O); endmodule\n        ^~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'$__FACADE_TOUTPAD\'\nmodule  \\$__FACADE_TOUTPAD (input I, T, output O); endmodule\n        ^~~~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'$__FACADE_TINOUTPAD\'\nmodule  \\$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule\n        ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/machxo2/cells_sim.v:30: Operator GENCASE expects 24 bits on the Case expression, but Case expression\'s VARREF \'CEMUX\' generates 8 bits.\n                                                                                      : ... In instance FACADE_SLICE.REG_1\n  case (CEMUX)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/machxo2/cells_sim.v:40: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'CLKMUX\' generates 8 bits.\n                                                                                      : ... In instance FACADE_SLICE.REG_1\n wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;\n                       ^~\n%Error: Exiting due to 3 warning(s)\n'
module OSCH #(
	parameter NOM_FREQ = "2.08"
) (
	input STDBY,
	output OSC,
	output SEDSTDBY
);
endmodule
module OSCH #(
	parameter NOM_FREQ = "2.08"
) (
	input STDBY,
	output OSC,
	output SEDSTDBY
);

endmodule