data/full_repos/permissive/494657797/verilog/rtl/sar_logic.v
data/verilator_xmls/abfc2317-331c-4ee4-8dad-a71d7200b02c.xml
module dff ( input wire d,
              input wire rst,
              input wire clk,
              output reg q,
              output wire qn);
	
      initial begin
        q <= 0;
      end

      always @ (posedge clk or posedge rst)
            if (rst)
                  q <= 0;
            else
                  q <= d;
      
      assign qn = ~q;

endmodule
module dff ( input wire d,
              input wire rst,
              input wire clk,
              output reg q,
              output wire qn);

	
      initial begin
        q <= 0;
      end

      always @ (posedge clk or posedge rst)
            if (rst)
                  q <= 0;
            else
                  q <= d;
      
      assign qn = ~q;

endmodule