data/full_repos/permissive/494664634/AxisFifo/src/hdl/AxiStreamFifo.v
1: b"%Error: data/full_repos/permissive/494664634/AxisFifo/src/hdl/AxiStreamFifo.v:54: Cannot find file containing module: 'xpm_fifo_sync'\n  xpm_fifo_sync\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494664634/AxisFifo/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync\n             data/full_repos/permissive/494664634/AxisFifo/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync.v\n             data/full_repos/permissive/494664634/AxisFifo/src/hdl,data/full_repos/permissive/494664634/xpm_fifo_sync.sv\n             xpm_fifo_sync\n             xpm_fifo_sync.v\n             xpm_fifo_sync.sv\n             obj_dir/xpm_fifo_sync\n             obj_dir/xpm_fifo_sync.v\n             obj_dir/xpm_fifo_sync.sv\n%Error: Exiting due to 1 error(s)\n"
module AxiStreamFifo(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXIS:S_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  input  [31:0] s_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
  input         s_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
  output        s_axis_tready
);
  wire  fifo_almost_empty;
  wire  fifo_almost_full;
  wire  fifo_data_valid;
  wire  fifo_dbiterr;
  wire [31:0] fifo_din;
  wire [31:0] fifo_dout;
  wire  fifo_empty;
  wire  fifo_full;
  wire  fifo_injectdbiterr;
  wire  fifo_injectsbiterr;
  wire  fifo_overflow;
  wire  fifo_prog_empty;
  wire  fifo_prog_full;
  wire [9:0] fifo_rd_data_count;
  wire  fifo_rd_en;
  wire  fifo_rd_rst_busy;
  wire  fifo_rst;
  wire  fifo_sbiterr;
  wire  fifo_sleep;
  wire  fifo_underflow;
  wire  fifo_wr_ack;
  wire  fifo_wr_clk;
  wire [9:0] fifo_wr_data_count;
  wire  fifo_wr_en;
  wire  fifo_wr_rst_busy;
  xpm_fifo_sync
    #(.RD_DATA_COUNT_WIDTH(10), .READ_DATA_WIDTH(32), .WRITE_DATA_WIDTH(32), .FIFO_WRITE_DEPTH(512), .PROG_EMPTY_THRESH(5), .READ_MODE("fwft"), .WR_DATA_COUNT_WIDTH(10), .PROG_FULL_THRESH(507), .FULL_RESET_VALUE(1), .FIFO_READ_LATENCY(1))
    fifo (
    .almost_empty(fifo_almost_empty),
    .almost_full(fifo_almost_full),
    .data_valid(fifo_data_valid),
    .dbiterr(fifo_dbiterr),
    .din(fifo_din),
    .dout(fifo_dout),
    .empty(fifo_empty),
    .full(fifo_full),
    .injectdbiterr(fifo_injectdbiterr),
    .injectsbiterr(fifo_injectsbiterr),
    .overflow(fifo_overflow),
    .prog_empty(fifo_prog_empty),
    .prog_full(fifo_prog_full),
    .rd_data_count(fifo_rd_data_count),
    .rd_en(fifo_rd_en),
    .rd_rst_busy(fifo_rd_rst_busy),
    .rst(fifo_rst),
    .sbiterr(fifo_sbiterr),
    .sleep(fifo_sleep),
    .underflow(fifo_underflow),
    .wr_ack(fifo_wr_ack),
    .wr_clk(fifo_wr_clk),
    .wr_data_count(fifo_wr_data_count),
    .wr_en(fifo_wr_en),
    .wr_rst_busy(fifo_wr_rst_busy)
  );
  assign m_axis_tdata = fifo_dout;
  assign m_axis_tvalid = ~fifo_empty;
  assign s_axis_tready = ~fifo_full;
  assign fifo_din = s_axis_tdata;
  assign fifo_injectdbiterr = 1'h0;
  assign fifo_injectsbiterr = 1'h0;
  assign fifo_rd_en = m_axis_tready;
  assign fifo_rst = reset;
  assign fifo_sleep = 1'h0;
  assign fifo_wr_clk = clock;
  assign fifo_wr_en = s_axis_tvalid;
endmodule
module AxiStreamFifo(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXIS:S_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock" *)
  input  [31:0] s_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
  input         s_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
  output        s_axis_tready
);

  wire  fifo_almost_empty;
  wire  fifo_almost_full;
  wire  fifo_data_valid;
  wire  fifo_dbiterr;
  wire [31:0] fifo_din;
  wire [31:0] fifo_dout;
  wire  fifo_empty;
  wire  fifo_full;
  wire  fifo_injectdbiterr;
  wire  fifo_injectsbiterr;
  wire  fifo_overflow;
  wire  fifo_prog_empty;
  wire  fifo_prog_full;
  wire [9:0] fifo_rd_data_count;
  wire  fifo_rd_en;
  wire  fifo_rd_rst_busy;
  wire  fifo_rst;
  wire  fifo_sbiterr;
  wire  fifo_sleep;
  wire  fifo_underflow;
  wire  fifo_wr_ack;
  wire  fifo_wr_clk;
  wire [9:0] fifo_wr_data_count;
  wire  fifo_wr_en;
  wire  fifo_wr_rst_busy;
  xpm_fifo_sync
    #(.RD_DATA_COUNT_WIDTH(10), .READ_DATA_WIDTH(32), .WRITE_DATA_WIDTH(32), .FIFO_WRITE_DEPTH(512), .PROG_EMPTY_THRESH(5), .READ_MODE("fwft"), .WR_DATA_COUNT_WIDTH(10), .PROG_FULL_THRESH(507), .FULL_RESET_VALUE(1), .FIFO_READ_LATENCY(1))
    fifo (
    .almost_empty(fifo_almost_empty),
    .almost_full(fifo_almost_full),
    .data_valid(fifo_data_valid),
    .dbiterr(fifo_dbiterr),
    .din(fifo_din),
    .dout(fifo_dout),
    .empty(fifo_empty),
    .full(fifo_full),
    .injectdbiterr(fifo_injectdbiterr),
    .injectsbiterr(fifo_injectsbiterr),
    .overflow(fifo_overflow),
    .prog_empty(fifo_prog_empty),
    .prog_full(fifo_prog_full),
    .rd_data_count(fifo_rd_data_count),
    .rd_en(fifo_rd_en),
    .rd_rst_busy(fifo_rd_rst_busy),
    .rst(fifo_rst),
    .sbiterr(fifo_sbiterr),
    .sleep(fifo_sleep),
    .underflow(fifo_underflow),
    .wr_ack(fifo_wr_ack),
    .wr_clk(fifo_wr_clk),
    .wr_data_count(fifo_wr_data_count),
    .wr_en(fifo_wr_en),
    .wr_rst_busy(fifo_wr_rst_busy)
  );
  assign m_axis_tdata = fifo_dout;
  assign m_axis_tvalid = ~fifo_empty;
  assign s_axis_tready = ~fifo_full;
  assign fifo_din = s_axis_tdata;
  assign fifo_injectdbiterr = 1'h0;
  assign fifo_injectsbiterr = 1'h0;
  assign fifo_rd_en = m_axis_tready;
  assign fifo_rst = reset;
  assign fifo_sleep = 1'h0;
  assign fifo_wr_clk = clock;
  assign fifo_wr_en = s_axis_tvalid;
endmodule