data/full_repos/permissive/425063349/Hash_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #80 Reset = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #800 Reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #100 Reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #800 Reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #100 Reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Hash_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #50 Clock = ~Clock;\n  ^\n%Error: data/full_repos/permissive/425063349/Hash_tb.v:7: Cannot find file containing module: \'Hash\'\n Hash h1(hashValue, Z, word, Reset, Clock);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Hash\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Hash.v\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Hash.sv\n             Hash\n             Hash.v\n             Hash.sv\n             obj_dir/Hash\n             obj_dir/Hash.v\n             obj_dir/Hash.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Hash_tb;
	wire [63:0] hashValue;
	reg Clock = 1;
	reg Reset = 1;
	wire Z;
	reg [2:0] word = 3'b100;
	Hash h1(hashValue, Z, word, Reset, Clock);
	
	initial begin
		#80 Reset = 1'b0;
		#800 Reset = 1'b1;
		word = 3'b010;
		
		#100 Reset = 1'b0;
		#800 Reset = 1'b1;
		word = 3'b001;
		
		#100 Reset = 1'b0;

	end

	always
		#50 Clock = ~Clock;
endmodule
module Hash_tb;

	wire [63:0] hashValue;
	reg Clock = 1;
	reg Reset = 1;
	wire Z;
	reg [2:0] word = 3'b100;
	Hash h1(hashValue, Z, word, Reset, Clock);
	
	initial begin
		#80 Reset = 1'b0;
		#800 Reset = 1'b1;
		word = 3'b010;
		
		#100 Reset = 1'b0;
		#800 Reset = 1'b1;
		word = 3'b001;
		
		#100 Reset = 1'b0;

	end

	always
		#50 Clock = ~Clock;
endmodule