data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_explicit_mem/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/cdc4afdb-7a4c-48c5-b3d3-73b9a2d7a7cf.xml
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data,
       dout_busy,
       dout_vld,
       dout_data,
       mem_WE0,
       mem_DIN0,
       mem_DOUT0,
       mem_A0,
       mem_REQ0

    ) (* integer foreign = "SystemC";
    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data;
	input dout_busy;
	output dout_vld;
	output [10:0] dout_data;
	output mem_WE0;
	output [7:0] mem_DIN0;
	input [7:0] mem_DOUT0;
	output [5:0] mem_A0;
	output mem_REQ0;


endmodule
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data,
       dout_busy,
       dout_vld,
       dout_data,
       mem_WE0,
       mem_DIN0,
       mem_DOUT0,
       mem_A0,
       mem_REQ0

    ) (* integer foreign = "SystemC";

    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data;
	input dout_busy;
	output dout_vld;
	output [10:0] dout_data;
	output mem_WE0;
	output [7:0] mem_DIN0;
	input [7:0] mem_DOUT0;
	output [5:0] mem_A0;
	output mem_REQ0;


endmodule