data/full_repos/permissive/456317201/backends/i2c_initiator_byte_ctrl.v
1: b"%Error: data/full_repos/permissive/456317201/backends/i2c_initiator_byte_ctrl.v:139: Cannot find file containing module: 'i2c_initiator_bit_ctrl'\n i2c_initiator_bit_ctrl bit_controller (\n ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456317201/backends,data/full_repos/permissive/456317201/i2c_initiator_bit_ctrl\n             data/full_repos/permissive/456317201/backends,data/full_repos/permissive/456317201/i2c_initiator_bit_ctrl.v\n             data/full_repos/permissive/456317201/backends,data/full_repos/permissive/456317201/i2c_initiator_bit_ctrl.sv\n             i2c_initiator_bit_ctrl\n             i2c_initiator_bit_ctrl.v\n             i2c_initiator_bit_ctrl.sv\n             obj_dir/i2c_initiator_bit_ctrl\n             obj_dir/i2c_initiator_bit_ctrl.v\n             obj_dir/i2c_initiator_bit_ctrl.sv\n%Error: Exiting due to 1 error(s)\n"
module i2c_initiator_byte_ctrl (
	input clock,
	input reset,
	input ena,
	input[15:0] clk_cnt,

	input start, 
	input stop, 
	input read, 
	input write, 
	input ack_in, 
	input[7:0] din,
	

	output reg cmd_ack, 
	output reg ack_out, 
	output[7:0] dout, 
	output i2c_busy, 
	output i2c_al, 

	input scl_i, 
	output scl_o, 
	output scl_oen, 
	input sda_i, 
	output sda_o, 
	output sda_oen);






	parameter [4:0] ST_IDLE  = 5'b0_0000;
	parameter [4:0] ST_START = 5'b0_0001;
	parameter [4:0] ST_READ  = 5'b0_0010;
	parameter [4:0] ST_WRITE = 5'b0_0100;
	parameter [4:0] ST_ACK   = 5'b0_1000;
	parameter [4:0] ST_STOP  = 5'b1_0000;
	
	localparam [3:0] I2C_CMD_NOP   = 4'b0000;
	localparam [3:0] I2C_CMD_START = 4'b0001;
	localparam [3:0] I2C_CMD_STOP  = 4'b0010;
	localparam [3:0] I2C_CMD_WRITE = 4'b0100;
	localparam [3:0] I2C_CMD_READ  = 4'b1000;


	reg  [3:0] core_cmd;
	reg        core_txd;
	wire       core_ack, core_rxd;


	reg [7:0] sr;
	reg       shift, ld;


	wire       go;
	reg  [2:0] dcnt;
	wire       cnt_done;






	i2c_initiator_bit_ctrl bit_controller (
		.clock     ( clock      ),
		.reset     ( reset      ),
		.ena     ( ena      ),
		.clk_cnt ( clk_cnt  ),
		.cmd     ( core_cmd ),
		.cmd_ack ( core_ack ),
		.busy    ( i2c_busy ),
		.al      ( i2c_al   ),
		.din     ( core_txd ),
		.dout    ( core_rxd ),
		.scl_i   ( scl_i    ),
		.scl_o   ( scl_o    ),
		.scl_oen ( scl_oen  ),
		.sda_i   ( sda_i    ),
		.sda_o   ( sda_o    ),
		.sda_oen ( sda_oen  )
	);


	assign go = ( read | write | stop) & ~cmd_ack;


	assign dout = sr;


	always @(posedge clock or posedge reset)
	  if (reset)
	    sr <= 8'h0;
	  else if (ld)
	    sr <= din;
	  else if (shift)
	    sr <= {sr[6:0], core_rxd};


	always @(posedge clock or posedge reset) begin
		if (reset) begin
			dcnt <= 3'h0;
			$display("RESET");
		end else begin
			if (ld) begin
				dcnt <= 3'h7;
			end else if (shift) begin
				dcnt <= dcnt - 3'h1;
			end
		end
	end

	assign cnt_done = ~(|dcnt);




	reg [4:0] c_state;

	always @(posedge clock or posedge reset)
		if (reset) begin
	       core_cmd <= I2C_CMD_NOP;
	       core_txd <= 1'b0;
	       shift    <= 1'b0;
	       ld       <= 1'b0;
	       cmd_ack  <= 1'b0;
	       c_state  <= ST_IDLE;
	       ack_out  <= 1'b0;
		end else begin
			if ( i2c_al) begin
				core_cmd <= I2C_CMD_NOP;
				core_txd <= 1'b0;
				shift    <= 1'b0;
				ld       <= 1'b0;
				cmd_ack  <= 1'b0;
				c_state  <= ST_IDLE;
				ack_out  <= 1'b0;
			end else begin

				core_txd <= sr[7];
				shift    <= 1'b0;
				ld       <= 1'b0;
				cmd_ack  <= 1'b0;

				case (c_state)
					ST_IDLE:
						if (go)
						begin
							if (start) begin
								c_state  <= ST_START;
								core_cmd <= I2C_CMD_START;
							end else if (read) begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end else if (write) begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
							end else
							begin
								c_state  <= ST_STOP;
								core_cmd <= I2C_CMD_STOP;
							end

							ld <= 1'b1;
						end

					ST_START:
						if (core_ack) begin
							if (read) begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end else begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
							end

							ld <= 1'b1;
						end

					ST_WRITE:
						if (core_ack)
							if (cnt_done) begin
								c_state  <= ST_ACK;
								core_cmd <= I2C_CMD_READ;
							end else begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
								shift    <= 1'b1;
							end

					ST_READ:
						if (core_ack)
						begin
							if (cnt_done)
							begin
								c_state  <= ST_ACK;
								core_cmd <= I2C_CMD_WRITE;
							end
							else
							begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end

							shift    <= 1'b1;
							core_txd <= ack_in;
						end

					ST_ACK:
						if (core_ack)
						begin
							if (stop)
							begin
								c_state  <= ST_STOP;
								core_cmd <= I2C_CMD_STOP;
							end
							else
							begin
								c_state  <= ST_IDLE;
								core_cmd <= I2C_CMD_NOP;


								cmd_ack  <= 1'b1;
							end


							ack_out <= core_rxd;

							core_txd <= 1'b1;
						end
						else
							core_txd <= ack_in;

					ST_STOP:
						if (core_ack)
						begin
							c_state  <= ST_IDLE;
							core_cmd <= I2C_CMD_NOP;


							cmd_ack  <= 1'b1;
						end
					endcase
			end
	  end
endmodule
module i2c_initiator_byte_ctrl (
	input clock,
	input reset,
	input ena,
	input[15:0] clk_cnt,

	input start, 
	input stop, 
	input read, 
	input write, 
	input ack_in, 
	input[7:0] din,
	

	output reg cmd_ack, 
	output reg ack_out, 
	output[7:0] dout, 
	output i2c_busy, 
	output i2c_al, 

	input scl_i, 
	output scl_o, 
	output scl_oen, 
	input sda_i, 
	output sda_o, 
	output sda_oen);







	parameter [4:0] ST_IDLE  = 5'b0_0000;
	parameter [4:0] ST_START = 5'b0_0001;
	parameter [4:0] ST_READ  = 5'b0_0010;
	parameter [4:0] ST_WRITE = 5'b0_0100;
	parameter [4:0] ST_ACK   = 5'b0_1000;
	parameter [4:0] ST_STOP  = 5'b1_0000;
	
	localparam [3:0] I2C_CMD_NOP   = 4'b0000;
	localparam [3:0] I2C_CMD_START = 4'b0001;
	localparam [3:0] I2C_CMD_STOP  = 4'b0010;
	localparam [3:0] I2C_CMD_WRITE = 4'b0100;
	localparam [3:0] I2C_CMD_READ  = 4'b1000;


	reg  [3:0] core_cmd;
	reg        core_txd;
	wire       core_ack, core_rxd;


	reg [7:0] sr;
	reg       shift, ld;


	wire       go;
	reg  [2:0] dcnt;
	wire       cnt_done;






	i2c_initiator_bit_ctrl bit_controller (
		.clock     ( clock      ),
		.reset     ( reset      ),
		.ena     ( ena      ),
		.clk_cnt ( clk_cnt  ),
		.cmd     ( core_cmd ),
		.cmd_ack ( core_ack ),
		.busy    ( i2c_busy ),
		.al      ( i2c_al   ),
		.din     ( core_txd ),
		.dout    ( core_rxd ),
		.scl_i   ( scl_i    ),
		.scl_o   ( scl_o    ),
		.scl_oen ( scl_oen  ),
		.sda_i   ( sda_i    ),
		.sda_o   ( sda_o    ),
		.sda_oen ( sda_oen  )
	);


	assign go = ( read | write | stop) & ~cmd_ack;


	assign dout = sr;


	always @(posedge clock or posedge reset)
	  if (reset)
	    sr <= 8'h0;
	  else if (ld)
	    sr <= din;
	  else if (shift)
	    sr <= {sr[6:0], core_rxd};


	always @(posedge clock or posedge reset) begin
		if (reset) begin
			dcnt <= 3'h0;
			$display("RESET");
		end else begin
			if (ld) begin
				dcnt <= 3'h7;
			end else if (shift) begin
				dcnt <= dcnt - 3'h1;
			end
		end
	end

	assign cnt_done = ~(|dcnt);




	reg [4:0] c_state;

	always @(posedge clock or posedge reset)
		if (reset) begin
	       core_cmd <= I2C_CMD_NOP;
	       core_txd <= 1'b0;
	       shift    <= 1'b0;
	       ld       <= 1'b0;
	       cmd_ack  <= 1'b0;
	       c_state  <= ST_IDLE;
	       ack_out  <= 1'b0;
		end else begin
			if ( i2c_al) begin
				core_cmd <= I2C_CMD_NOP;
				core_txd <= 1'b0;
				shift    <= 1'b0;
				ld       <= 1'b0;
				cmd_ack  <= 1'b0;
				c_state  <= ST_IDLE;
				ack_out  <= 1'b0;
			end else begin

				core_txd <= sr[7];
				shift    <= 1'b0;
				ld       <= 1'b0;
				cmd_ack  <= 1'b0;

				case (c_state)
					ST_IDLE:
						if (go)
						begin
							if (start) begin
								c_state  <= ST_START;
								core_cmd <= I2C_CMD_START;
							end else if (read) begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end else if (write) begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
							end else
							begin
								c_state  <= ST_STOP;
								core_cmd <= I2C_CMD_STOP;
							end

							ld <= 1'b1;
						end

					ST_START:
						if (core_ack) begin
							if (read) begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end else begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
							end

							ld <= 1'b1;
						end

					ST_WRITE:
						if (core_ack)
							if (cnt_done) begin
								c_state  <= ST_ACK;
								core_cmd <= I2C_CMD_READ;
							end else begin
								c_state  <= ST_WRITE;
								core_cmd <= I2C_CMD_WRITE;
								shift    <= 1'b1;
							end

					ST_READ:
						if (core_ack)
						begin
							if (cnt_done)
							begin
								c_state  <= ST_ACK;
								core_cmd <= I2C_CMD_WRITE;
							end
							else
							begin
								c_state  <= ST_READ;
								core_cmd <= I2C_CMD_READ;
							end

							shift    <= 1'b1;
							core_txd <= ack_in;
						end

					ST_ACK:
						if (core_ack)
						begin
							if (stop)
							begin
								c_state  <= ST_STOP;
								core_cmd <= I2C_CMD_STOP;
							end
							else
							begin
								c_state  <= ST_IDLE;
								core_cmd <= I2C_CMD_NOP;


								cmd_ack  <= 1'b1;
							end


							ack_out <= core_rxd;

							core_txd <= 1'b1;
						end
						else
							core_txd <= ack_in;

					ST_STOP:
						if (core_ack)
						begin
							c_state  <= ST_IDLE;
							core_cmd <= I2C_CMD_NOP;


							cmd_ack  <= 1'b1;
						end
					endcase
			end
	  end
endmodule