data/full_repos/permissive/490649362/single-cycle/src/Adder4.v
data/verilator_xmls/5e7af649-0c30-4d30-a7c7-1cee9368be04.xml
module Adder4(in, out);

    input  [31:0] in;
    output [31:0] out;

    assign out = in + 4;

endmodule
module Adder4(in, out);


    input  [31:0] in;
    output [31:0] out;

    assign out = in + 4;

endmodule