data/full_repos/permissive/52900389/FF-D.v
data/verilator_xmls/2257e7b2-6bfa-470f-b49f-f818df7f5feb.xml
module FFD(dato,clk,q);
input dato, clk; 
output reg q;

always @ ( posedge clk)
begin
  q <= dato;
end
endmodule
module FFD(dato,clk,q);

input dato, clk; 
output reg q;

always @ ( posedge clk)
begin
  q <= dato;
end
endmodule