data/full_repos/permissive/42434302/ivltests/pr2138979d.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:133: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_uu = sel ?         a  :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:133: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_uu = sel ?         a  :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:134: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_us = sel ?         a  : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:134: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_us = sel ?         a  : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:135: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_su = sel ? $signed(a) :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:135: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_su = sel ? $signed(a) :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:136: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_ss = sel ? $signed(a) : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:136: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_ss = sel ? $signed(a) : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:138: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_uu =         a  ==         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:139: Operator EQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_us =         a  == $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:140: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_su = $signed(a) ==         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:141: Operator EQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_ss = $signed(a) == $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:143: Operator NEQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_uu =         a  !=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:144: Operator NEQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_us =         a  != $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:145: Operator NEQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_su = $signed(a) !=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:146: Operator NEQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_ss = $signed(a) != $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:148: Operator NOT expects 16 bits on the LHS, but LHS\'s UNSIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sgn_u = ~$unsigned(c) ;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:149: Operator NOT expects 16 bits on the LHS, but LHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sgn_s = ~$signed(c) ;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:151: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_uu =         a  +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:151: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_uu =         a  +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:152: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_us =         a  + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:152: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_us =         a  + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:153: Operator ADD expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_su = $signed(a) +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:153: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_su = $signed(a) +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:154: Operator ADD expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_ss = $signed(a) + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:154: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_ss = $signed(a) + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:156: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_uu =         a  -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:156: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_uu =         a  -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:157: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_us =         a  - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:157: Operator SUB expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_us =         a  - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:158: Operator SUB expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_su = $signed(a) -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:158: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_su = $signed(a) -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:159: Operator SUB expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_ss = $signed(a) - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:159: Operator SUB expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_ss = $signed(a) - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:166: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_uu =         a  <         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:167: Operator LT expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_us =         a  < $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:168: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_su = $signed(a) <         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:169: Operator LTS expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_ss = $signed(a) < $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:171: Operator LTE expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_uu =         a  <=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:172: Operator LTE expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_us =         a  <= $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:173: Operator LTE expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_su = $signed(a) <=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:174: Operator LTES expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_ss = $signed(a) <= $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:30: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        sel = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        a   = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        b   = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:33: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        c   = $random;\n            ^\n%Error: Exiting due to 47 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module signed_logic_operators_bug();

reg         sel;
reg   [7:0] a, b;
reg   [5:0] c;
wire [15:0] y_mux_uu, y_mux_us, y_mux_su, y_mux_ss;
wire        y_eql_uu, y_eql_us, y_eql_su, y_eql_ss;
wire        y_neq_uu, y_neq_us, y_neq_su, y_neq_ss;
wire [15:0] y_sgn_u,  y_sgn_s;
wire [15:0] y_add_uu, y_add_us, y_add_su, y_add_ss;
wire [15:0] y_sub_uu, y_sub_us, y_sub_su, y_sub_ss;
wire [15:0] y_mul_uu, y_mul_us, y_mul_su, y_mul_ss;
wire        y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss;
wire        y_leq_uu, y_leq_us, y_leq_su, y_leq_ss;
wire [15:0] z_mux_uu, z_mux_us, z_mux_su, z_mux_ss;
wire        z_eql_uu, z_eql_us, z_eql_su, z_eql_ss;
wire        z_neq_uu, z_neq_us, z_neq_su, z_neq_ss;
wire [15:0] z_sgn_u,  z_sgn_s;
wire [15:0] z_add_uu, z_add_us, z_add_su, z_add_ss;
wire [15:0] z_sub_uu, z_sub_us, z_sub_su, z_sub_ss;
wire [15:0] z_mul_uu, z_mul_us, z_mul_su, z_mul_ss;
wire        z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss;
wire        z_leq_uu, z_leq_us, z_leq_su, z_leq_ss;

integer i;

initial begin
    for (i = 0; i < 100; i = i + 1) begin

        sel = $random;
        a   = $random;
        b   = $random;
        c   = $random;


        #1;


        $display("sel = %b", sel);
        $display("a   = %b", a);
        $display("b   = %b", b);
        $display("c   = %b", c);
        $display("y_mux_uu = %b   y_mux_us = %b   y_mux_su = %b   y_mux_ss = %b", y_mux_uu, y_mux_us, y_mux_su, y_mux_ss);
        $display("z_mux_uu = %b   z_mux_us = %b   z_mux_su = %b   z_mux_ss = %b", z_mux_uu, z_mux_us, z_mux_su, z_mux_ss);
        $display("y_eql_uu = %b   y_eql_us = %b   y_eql_su = %b   y_eql_ss = %b", y_eql_uu, y_eql_us, y_eql_su, y_eql_ss);
        $display("z_eql_uu = %b   z_eql_us = %b   z_eql_su = %b   z_eql_ss = %b", z_eql_uu, z_eql_us, z_eql_su, z_eql_ss);
        $display("y_neq_uu = %b   y_neq_us = %b   y_neq_su = %b   y_neq_ss = %b", y_neq_uu, y_neq_us, y_neq_su, y_neq_ss);
        $display("z_neq_uu = %b   z_neq_us = %b   z_neq_su = %b   z_neq_ss = %b", z_neq_uu, z_neq_us, z_neq_su, z_neq_ss);
        $display("y_sgn_u  = %b   y_sgn_s  = %b"                                , y_sgn_u,  y_sgn_s);
        $display("z_sgn_u  = %b   z_sgn_s  = %b"                                , z_sgn_u,  z_sgn_s);
        $display("y_add_uu = %b   y_add_us = %b   y_add_su = %b   y_add_ss = %b", y_add_uu, y_add_us, y_add_su, y_add_ss);
        $display("z_add_uu = %b   z_add_us = %b   z_add_su = %b   z_add_ss = %b", z_add_uu, z_add_us, z_add_su, z_add_ss);
        $display("y_sub_uu = %b   y_sub_us = %b   y_sub_su = %b   y_sub_ss = %b", y_sub_uu, y_sub_us, y_sub_su, y_sub_ss);
        $display("z_sub_uu = %b   z_sub_us = %b   z_sub_su = %b   z_sub_ss = %b", z_sub_uu, z_sub_us, z_sub_su, z_sub_ss);
        $display("y_mul_uu = %b   y_mul_us = %b   y_mul_su = %b   y_mul_ss = %b", y_mul_uu, y_mul_us, y_mul_su, y_mul_ss);
        $display("z_mul_uu = %b   z_mul_us = %b   z_mul_su = %b   z_mul_ss = %b", z_mul_uu, z_mul_us, z_mul_su, z_mul_ss);
        $display("y_ltn_uu = %b   y_ltn_us = %b   y_ltn_su = %b   y_ltn_ss = %b", y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss);
        $display("z_ltn_uu = %b   z_ltn_us = %b   z_ltn_su = %b   z_ltn_ss = %b", z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss);
        $display("y_leq_uu = %b   y_leq_us = %b   y_leq_su = %b   y_leq_ss = %b", y_leq_uu, y_leq_us, y_leq_su, y_leq_ss);
        $display("z_leq_uu = %b   z_leq_us = %b   z_leq_su = %b   z_leq_ss = %b", z_leq_uu, z_leq_us, z_leq_su, z_leq_ss);
    end


    $finish;
end


manually_extended_operators INST1(
    sel,
    a, b,
    c,
    y_mux_uu, y_mux_us, y_mux_su, y_mux_ss,
    y_eql_uu, y_eql_us, y_eql_su, y_eql_ss,
    y_neq_uu, y_neq_us, y_neq_su, y_neq_ss,
    y_sgn_u,  y_sgn_s,
    y_add_uu, y_add_us, y_add_su, y_add_ss,
    y_sub_uu, y_sub_us, y_sub_su, y_sub_ss,
    y_mul_uu, y_mul_us, y_mul_su, y_mul_ss,
    y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss,
    y_leq_uu, y_leq_us, y_leq_su, y_leq_ss
    );


signed_operators INST2(
    sel,
    a, b,
    c,
    z_mux_uu, z_mux_us, z_mux_su, z_mux_ss,
    z_eql_uu, z_eql_us, z_eql_su, z_eql_ss,
    z_neq_uu, z_neq_us, z_neq_su, z_neq_ss,
    z_sgn_u,  z_sgn_s,
    z_add_uu, z_add_us, z_add_su, z_add_ss,
    z_sub_uu, z_sub_us, z_sub_su, z_sub_ss,
    z_mul_uu, z_mul_us, z_mul_su, z_mul_ss,
    z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss,
    z_leq_uu, z_leq_us, z_leq_su, z_leq_ss
    );

endmodule
module signed_logic_operators_bug();


reg         sel;
reg   [7:0] a, b;
reg   [5:0] c;
wire [15:0] y_mux_uu, y_mux_us, y_mux_su, y_mux_ss;
wire        y_eql_uu, y_eql_us, y_eql_su, y_eql_ss;
wire        y_neq_uu, y_neq_us, y_neq_su, y_neq_ss;
wire [15:0] y_sgn_u,  y_sgn_s;
wire [15:0] y_add_uu, y_add_us, y_add_su, y_add_ss;
wire [15:0] y_sub_uu, y_sub_us, y_sub_su, y_sub_ss;
wire [15:0] y_mul_uu, y_mul_us, y_mul_su, y_mul_ss;
wire        y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss;
wire        y_leq_uu, y_leq_us, y_leq_su, y_leq_ss;
wire [15:0] z_mux_uu, z_mux_us, z_mux_su, z_mux_ss;
wire        z_eql_uu, z_eql_us, z_eql_su, z_eql_ss;
wire        z_neq_uu, z_neq_us, z_neq_su, z_neq_ss;
wire [15:0] z_sgn_u,  z_sgn_s;
wire [15:0] z_add_uu, z_add_us, z_add_su, z_add_ss;
wire [15:0] z_sub_uu, z_sub_us, z_sub_su, z_sub_ss;
wire [15:0] z_mul_uu, z_mul_us, z_mul_su, z_mul_ss;
wire        z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss;
wire        z_leq_uu, z_leq_us, z_leq_su, z_leq_ss;

integer i;

initial begin
    for (i = 0; i < 100; i = i + 1) begin

        sel = $random;
        a   = $random;
        b   = $random;
        c   = $random;


        #1;


        $display("sel = %b", sel);
        $display("a   = %b", a);
        $display("b   = %b", b);
        $display("c   = %b", c);
        $display("y_mux_uu = %b   y_mux_us = %b   y_mux_su = %b   y_mux_ss = %b", y_mux_uu, y_mux_us, y_mux_su, y_mux_ss);
        $display("z_mux_uu = %b   z_mux_us = %b   z_mux_su = %b   z_mux_ss = %b", z_mux_uu, z_mux_us, z_mux_su, z_mux_ss);
        $display("y_eql_uu = %b   y_eql_us = %b   y_eql_su = %b   y_eql_ss = %b", y_eql_uu, y_eql_us, y_eql_su, y_eql_ss);
        $display("z_eql_uu = %b   z_eql_us = %b   z_eql_su = %b   z_eql_ss = %b", z_eql_uu, z_eql_us, z_eql_su, z_eql_ss);
        $display("y_neq_uu = %b   y_neq_us = %b   y_neq_su = %b   y_neq_ss = %b", y_neq_uu, y_neq_us, y_neq_su, y_neq_ss);
        $display("z_neq_uu = %b   z_neq_us = %b   z_neq_su = %b   z_neq_ss = %b", z_neq_uu, z_neq_us, z_neq_su, z_neq_ss);
        $display("y_sgn_u  = %b   y_sgn_s  = %b"                                , y_sgn_u,  y_sgn_s);
        $display("z_sgn_u  = %b   z_sgn_s  = %b"                                , z_sgn_u,  z_sgn_s);
        $display("y_add_uu = %b   y_add_us = %b   y_add_su = %b   y_add_ss = %b", y_add_uu, y_add_us, y_add_su, y_add_ss);
        $display("z_add_uu = %b   z_add_us = %b   z_add_su = %b   z_add_ss = %b", z_add_uu, z_add_us, z_add_su, z_add_ss);
        $display("y_sub_uu = %b   y_sub_us = %b   y_sub_su = %b   y_sub_ss = %b", y_sub_uu, y_sub_us, y_sub_su, y_sub_ss);
        $display("z_sub_uu = %b   z_sub_us = %b   z_sub_su = %b   z_sub_ss = %b", z_sub_uu, z_sub_us, z_sub_su, z_sub_ss);
        $display("y_mul_uu = %b   y_mul_us = %b   y_mul_su = %b   y_mul_ss = %b", y_mul_uu, y_mul_us, y_mul_su, y_mul_ss);
        $display("z_mul_uu = %b   z_mul_us = %b   z_mul_su = %b   z_mul_ss = %b", z_mul_uu, z_mul_us, z_mul_su, z_mul_ss);
        $display("y_ltn_uu = %b   y_ltn_us = %b   y_ltn_su = %b   y_ltn_ss = %b", y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss);
        $display("z_ltn_uu = %b   z_ltn_us = %b   z_ltn_su = %b   z_ltn_ss = %b", z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss);
        $display("y_leq_uu = %b   y_leq_us = %b   y_leq_su = %b   y_leq_ss = %b", y_leq_uu, y_leq_us, y_leq_su, y_leq_ss);
        $display("z_leq_uu = %b   z_leq_us = %b   z_leq_su = %b   z_leq_ss = %b", z_leq_uu, z_leq_us, z_leq_su, z_leq_ss);
    end


    $finish;
end


manually_extended_operators INST1(
    sel,
    a, b,
    c,
    y_mux_uu, y_mux_us, y_mux_su, y_mux_ss,
    y_eql_uu, y_eql_us, y_eql_su, y_eql_ss,
    y_neq_uu, y_neq_us, y_neq_su, y_neq_ss,
    y_sgn_u,  y_sgn_s,
    y_add_uu, y_add_us, y_add_su, y_add_ss,
    y_sub_uu, y_sub_us, y_sub_su, y_sub_ss,
    y_mul_uu, y_mul_us, y_mul_su, y_mul_ss,
    y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss,
    y_leq_uu, y_leq_us, y_leq_su, y_leq_ss
    );


signed_operators INST2(
    sel,
    a, b,
    c,
    z_mux_uu, z_mux_us, z_mux_su, z_mux_ss,
    z_eql_uu, z_eql_us, z_eql_su, z_eql_ss,
    z_neq_uu, z_neq_us, z_neq_su, z_neq_ss,
    z_sgn_u,  z_sgn_s,
    z_add_uu, z_add_us, z_add_su, z_add_ss,
    z_sub_uu, z_sub_us, z_sub_su, z_sub_ss,
    z_mul_uu, z_mul_us, z_mul_su, z_mul_ss,
    z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss,
    z_leq_uu, z_leq_us, z_leq_su, z_leq_ss
    );

endmodule