data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_Mul_32Ux9U_32U_1.v
data/verilator_xmls/b9200cf9-2b92-4a0b-a2c4-1fc10b3223f9.xml
module dut_Mul_32Ux9U_32U_1 (
	in2,
	in1,
	out1
	);
input [31:0] in2;
input [8:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule
module dut_Mul_32Ux9U_32U_1 (
	in2,
	in1,
	out1
	);

input [31:0] in2;
input [8:0] in1;
output [31:0] out1;
wire [31:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule