data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:40: Signal definition not found, creating implicitly: \'is_predict_miss1\'\n                                                                                              : ... Suggested alternative: \'is_predict_miss\'\n assign is_predict_miss1 = (_is_predict_miss1 && is_two_instr_branch1);\n        ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:41: Signal definition not found, creating implicitly: \'is_predict_miss2\'\n                                                                                              : ... Suggested alternative: \'is_predict_miss\'\n assign is_predict_miss2 = (_is_predict_miss2 && is_one_instr_branch1);\n        ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'branch_dst2\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'branch_dst1\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'12\'h1\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance branch_predictor\n   for(i = 4\'b0000; i <= 4\'b1111; i = i + 4\'b0001) begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:52: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                           : ... In instance branch_predictor\n   for(i = 4\'b0000; i <= 4\'b1111; i = i + 4\'b0001) begin\n                                        ^\n%Error: Exiting due to 8 warning(s)\n'
function [11:0] predict(
		input [15:0] instr,
		input [15:0] instr_address,
		input is_branch
	);
		begin
			
			reg [7:0] d = instr[7:0];
			reg [11:0] exd = (d[7] ? {4'b1111,d} : {4'b0000,d});
			reg [11:0] branch_src = instr_address[11:0];
			reg [11:0] predict_address;
		
			if(is_branch) begin
				if(predict_satis(branch_src)) begin
					predict_address = branch_src + 12'h001 + exd;
				end
				else begin
					predict_address = branch_src + 12'h001;
				end
			end 
			else begin
				predict_address = branch_src + 12'h001;
			end
			predict = predict_address;
		end
	endfunction
function [11:0] predict(
		input [15:0] instr,
		input [15:0] instr_address,
		input is_branch
	);

		begin
			
			reg [7:0] d = instr[7:0];
			reg [11:0] exd = (d[7] ? {4'b1111,d} : {4'b0000,d});
			reg [11:0] branch_src = instr_address[11:0];
			reg [11:0] predict_address;
		
			if(is_branch) begin
				if(predict_satis(branch_src)) begin
					predict_address = branch_src + 12'h001 + exd;
				end
				else begin
					predict_address = branch_src + 12'h001;
				end
			end 
			else begin
				predict_address = branch_src + 12'h001;
			end
			predict = predict_address;
		end
	endfunction