data/full_repos/permissive/448780010/code/mycpu_core.v
1: b'%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:1: Cannot find include file: mycpu.h\n`include "mycpu.h" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.v\n             data/full_repos/permissive/448780010/code,data/full_repos/permissive/448780010/mycpu.h.sv\n             mycpu.h\n             mycpu.h.v\n             mycpu.h.sv\n             obj_dir/mycpu.h\n             obj_dir/mycpu.h.v\n             obj_dir/mycpu.h.sv\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:46: Define or directive not defined: \'`FS_TO_DS_BUS_WD\'\nwire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:47: Define or directive not defined: \'`DS_TO_ES_BUS_WD\'\nwire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:48: Define or directive not defined: \'`ES_TO_MS_BUS_WD\'\nwire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:49: Define or directive not defined: \'`MS_TO_WS_BUS_WD\'\nwire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:50: Define or directive not defined: \'`WS_TO_RF_BUS_WD\'\nwire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:51: Define or directive not defined: \'`BR_BUS_WD\'\nwire [`BR_BUS_WD       -1:0] br_bus;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:52: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_es_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:53: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_ms_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:54: Define or directive not defined: \'`RAW_BUS_WD\'\nwire [`RAW_BUS_WD      -1:0] raw_ws_bus;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:57: Define or directive not defined: \'`ES_REFLUSH_FS_WD\'\nwire [`ES_REFLUSH_FS_WD -1:0]es_reflush_fs_bus;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:61: Define or directive not defined: \'`PFS_TO_FS_BUS_WD\'\nwire [`PFS_TO_FS_BUS_WD - 1:0] pfs_to_fs_bus;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448780010/code/mycpu_core.v:128: Define or directive not defined: \'`ES_TO_FS_BUS_WD\'\nwire [`ES_TO_FS_BUS_WD - 1 :0] es_to_fs_bus;\n      ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module vaddr_transfer(
    input  [31:0] va,
    input  [ 2:0] inst_op,
    output [31:0] pa,
    output [ 5:0] tlb_ex_bus,

    output [18:0] s_vppn,
    output        s_va_bit12,
    output [ 9:0] s_asid,
    input         s_found,
    input  [ 3:0] s_index,
    input  [19:0] s_ppn,
    input  [ 5:0] s_ps,
    input  [ 1:0] s_plv,
    input  [ 1:0] s_mat,
    input         s_d,
    input         s_v,

    input  [31:0] csr_asid,
    input  [31:0] csr_crmd,

    output dmw_hit,
    input  [31:0] csr_dmw0,
    input  [31:0] csr_dmw1
    
);
    parameter ps4k = 12;
    wire direct;
    wire mapping;

    wire dmw_hit0;
    wire dmw_hit1;
    wire [31:0] dmw_pa0;
    wire [31:0] dmw_pa1;
    wire [31:0] tlb_pa;
    wire [31:0] tlb_pa4k;
    wire [31:0] tlb_pa4m;
    assign direct = csr_crmd[3] & ~csr_crmd[4];

    assign dmw_hit0 = csr_dmw0[csr_crmd[1:0]] && (csr_dmw0[31:29]==va[31:29]);
    assign dmw_hit1 = csr_dmw1[csr_crmd[1:0]] && (csr_dmw1[31:29]==va[31:29]);
    assign dmw_pa0  = {csr_dmw0[27:25],va[28:0]};
    assign dmw_pa1  = {csr_dmw1[27:25],va[28:0]};

     assign s_vppn =  va[31:13];
     assign s_va_bit12 = va[12];
     assign s_asid =  csr_asid[9:0];
     assign tlb_ex_bus = {direct?1'b0:~dmw_hit & inst_op[1]&~s_d,
                          direct?1'b0:~dmw_hit &csr_crmd[1:0]>s_plv,
                          direct?1'b0:~dmw_hit &inst_op[1]&~s_v,
                          direct?1'b0:~dmw_hit &inst_op[2]&~s_v,
                          direct?1'b0:~dmw_hit &inst_op[0]&~s_v,
                          direct?1'b0:~dmw_hit &~s_found
                          };
     assign tlb_pa4k = {s_ppn[19:0],va[11:0]};
     assign tlb_pa4m = {s_ppn[19:10],va[21:0]};
     assign tlb_pa = (s_ps==ps4k)? tlb_pa4k:tlb_pa4m;
     assign dmw_hit = dmw_hit0 | dmw_hit1;
     assign pa = direct ? va:(dmw_hit0 ? dmw_pa0 : (dmw_hit1 ? dmw_pa1 : tlb_pa));
endmodule
module vaddr_transfer(
    input  [31:0] va,
    input  [ 2:0] inst_op,
    output [31:0] pa,
    output [ 5:0] tlb_ex_bus,

    output [18:0] s_vppn,
    output        s_va_bit12,
    output [ 9:0] s_asid,
    input         s_found,
    input  [ 3:0] s_index,
    input  [19:0] s_ppn,
    input  [ 5:0] s_ps,
    input  [ 1:0] s_plv,
    input  [ 1:0] s_mat,
    input         s_d,
    input         s_v,

    input  [31:0] csr_asid,
    input  [31:0] csr_crmd,

    output dmw_hit,
    input  [31:0] csr_dmw0,
    input  [31:0] csr_dmw1
    
);

    parameter ps4k = 12;
    wire direct;
    wire mapping;

    wire dmw_hit0;
    wire dmw_hit1;
    wire [31:0] dmw_pa0;
    wire [31:0] dmw_pa1;
    wire [31:0] tlb_pa;
    wire [31:0] tlb_pa4k;
    wire [31:0] tlb_pa4m;
    assign direct = csr_crmd[3] & ~csr_crmd[4];

    assign dmw_hit0 = csr_dmw0[csr_crmd[1:0]] && (csr_dmw0[31:29]==va[31:29]);
    assign dmw_hit1 = csr_dmw1[csr_crmd[1:0]] && (csr_dmw1[31:29]==va[31:29]);
    assign dmw_pa0  = {csr_dmw0[27:25],va[28:0]};
    assign dmw_pa1  = {csr_dmw1[27:25],va[28:0]};

     assign s_vppn =  va[31:13];
     assign s_va_bit12 = va[12];
     assign s_asid =  csr_asid[9:0];
     assign tlb_ex_bus = {direct?1'b0:~dmw_hit & inst_op[1]&~s_d,
                          direct?1'b0:~dmw_hit &csr_crmd[1:0]>s_plv,
                          direct?1'b0:~dmw_hit &inst_op[1]&~s_v,
                          direct?1'b0:~dmw_hit &inst_op[2]&~s_v,
                          direct?1'b0:~dmw_hit &inst_op[0]&~s_v,
                          direct?1'b0:~dmw_hit &~s_found
                          };
     assign tlb_pa4k = {s_ppn[19:0],va[11:0]};
     assign tlb_pa4m = {s_ppn[19:10],va[21:0]};
     assign tlb_pa = (s_ps==ps4k)? tlb_pa4k:tlb_pa4m;
     assign dmw_hit = dmw_hit0 | dmw_hit1;
     assign pa = direct ? va:(dmw_hit0 ? dmw_pa0 : (dmw_hit1 ? dmw_pa1 : tlb_pa));
endmodule