data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:27: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:169: Unsupported: Ignoring delay on this delayed statement.\n    #(300)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:183: Unsupported: Ignoring delay on this delayed statement.\n      #(ref_clk_width) slow_ext_clk_reg = ~slow_ext_clk_reg ; \n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:201: syntax error, unexpected \'@\'\n      @(jdiv) @(negedge slow_ext_clk_reg) #1\n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:209: syntax error, unexpected \'@\'\n      @(slow_ext_clk_reg)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:213: Unsupported: Ignoring delay on this delayed statement.\n        #(fast_ext_clk_width) fast_ext_clk_reg = ~fast_ext_clk_reg ;\n        ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:223: syntax error, unexpected \'@\'\n    @(posedge ref_clk) ref_clk_last_edge = $time ;\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:226: syntax error, unexpected \'@\'\n      @(ref_clk)\n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:241: syntax error, unexpected \'@\'\n      @(jdiv) @(negedge ref_clk) #1\n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:250: syntax error, unexpected \'@\'\n      @(ref_clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:255: Unsupported: Ignoring delay on this delayed statement.\n        #(fast_int_clk_width) fast_int_clk_reg = ~fast_int_clk_reg ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:248: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:293: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly0) osc_reg0 = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:297: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly0) osc_reg0 = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:301: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly1) osc_reg1 = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:305: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly1) osc_reg1 = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:309: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly2) osc_reg2 = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:313: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly2) osc_reg2 = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:317: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly3) osc_reg3 = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:321: Unsupported: Ignoring delay on this delayed statement.\n     #(osc_dly3) osc_reg3 = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:325: Unsupported: Ignoring delay on this delayed statement.\n     #(10) osc_out = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:329: Unsupported: Ignoring delay on this delayed statement.\n     #(10) osc_out = 1\'b0;\n     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:346: syntax error, unexpected \'@\'\n      @(pll_arst_l)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:344: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:351: syntax error, unexpected else\n      else if ( pll_arst_l === 1 ) begin\n      ^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:356: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:379: syntax error, unexpected \'@\'\n      @(posedge pll_arst_l) ;  \n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:384: syntax error, unexpected \'@\'\n      @(posedge vco_pump_up or negedge pll_arst_l) ; \n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:388: syntax error, unexpected \'@\'\n       repeat (freq_step_ctr+1) @(posedge osc_out) ;\n                                ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:414: syntax error, unexpected \'@\'\n      @(negedge pll_bypass); \n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:420: syntax error, unexpected \'@\'\n      @(posedge pll_arst_l);        \n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:424: syntax error, unexpected \'@\'\n      @(posedge freq_locked)\n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:429: syntax error, unexpected \'@\'\n      @(posedge feedback) beg_time = $time ;\n      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:438: syntax error, unexpected \'@\'\n        @(ref_clk)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:446: Unsupported: Ignoring delay on this delayed statement.\n        #(10000) ; \n        ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:451: syntax error, unexpected \'@\'\n      @(negedge pll_arst_l) ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:457: Unsupported: Ignoring delay on this delayed statement.\n      #(10000) ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:463: Unsupported: Ignoring delay on this delayed statement.\n      #(10000) ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:469: Unsupported: Ignoring delay on this delayed statement.\n      #(10000) ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:475: Unsupported: Ignoring delay on this delayed statement.\n      #(10000) ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:540: Unsupported: Ignoring delay on this delayed statement.\n      #1  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:561: Unsupported: Ignoring delay on this delayed statement.\n    #10 if ( vreg_seldb_l !== 1\'b0 )\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:568: syntax error, unexpected \'@\'\n    forever begin @ ( vreg_seldb_l )    \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:578: Unsupported: Ignoring delay on this delayed statement.\n    #10 if ( pll_clamp_fltr !== 1\'b0 )\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:585: syntax error, unexpected \'@\'\n    forever begin @ ( pll_clamp_fltr )    \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:604: Unsupported: Ignoring delay on this delayed statement.\n    #10 if ( pll_div1 !== 6\'b000000 )\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:611: syntax error, unexpected \'@\'\n    forever begin @ ( pll_div1 )    \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:621: Unsupported: Ignoring delay on this delayed statement.\n    #10 if ( pll_div2 !== 6\'b000000 )\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:628: syntax error, unexpected \'@\'\n    forever begin @ ( pll_div2 )    \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:638: Unsupported: Ignoring delay on this delayed statement.\n    #10 if ( pll_div3 !== 6\'b000000 )\n    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_pll.v:644: syntax error, unexpected \'@\'\n    forever begin @ ( pll_div3 )    \n                  ^\n%Error: Exiting due to 24 error(s), 27 warning(s)\n'
module bw_pll (



  pll_sys_clk ,
  pll_bypass ,
  pll_arst_l ,
  l2clk ,
  pll_clamp_fltr ,
  pll_div1 ,

  pll_div2 ,


  pll_div3 ,

  vdd_pll ,
  pll_char_in ,
  testmode ,
  vreg_seldb_l ,


  pll_raw_clk_out ,
  pll_vco_out ,
  pll_clk_out ,
  pll_clk_out_l ,
  pll_char_out
);

  input [1:0] pll_sys_clk;
  input       pll_bypass;
  input       pll_arst_l;
  input       l2clk;
  input       pll_clamp_fltr;
  input [5:0] pll_div1;
  input [5:0] pll_div2;
  input [5:0] pll_div3;
  input       vdd_pll;
  input       pll_char_in;
  input       testmode;
  input       vreg_seldb_l;
 
  output       pll_raw_clk_out;
  output       pll_vco_out;
  output       pll_clk_out;
  output       pll_clk_out_l;
  output [1:0] pll_char_out;



  wire  [4:0] jdiv ;
  reg   [7:0] jmhz ;

  integer     ref_clk_last_edge ;
  integer     ref_clk_this_edge ;
  integer     ref_clk_width ;
  reg         ref_clk_vld ;

  reg         slow_ext_clk_reg ;

  reg         fast_ext_clk_reg ;
  integer     fast_ext_clk_jdiv;
  integer     fast_ext_clk_width;

  reg         fast_int_clk_reg ;
  integer     fast_int_clk_jdiv ;
  integer     fast_int_clk_width ;
  integer     fast_int_clk_residue ;

  reg         osc_reg0;
  reg         osc_reg1;
  reg         osc_reg2;
  reg         osc_reg3;
  reg         osc_out;
   
  integer     osc_dly0;
  integer     osc_dly1;
  integer     osc_dly2;
  integer     osc_dly3;

  reg         osc_dly0_set;
  reg         osc_dly1_set;
  reg         osc_dly2_set;
  reg         osc_dly3_set;

  reg         vco_reg;
  reg         vco_off;
  wire        vco_out;

  integer     freq_step_ctr;
  wire        freq_locked ;
  reg         phase_locked;
  reg         edge_locked;
  integer     phase_match_ctr;
  integer     sync_errors;

  wire        ref_clk  = pll_sys_clk[0] ;
  wire        feedback = l2clk ; 

  integer     beg_time, end_time ;

  wire        pll_clk_free ;

  wire        pll_lock = freq_locked && phase_locked &&
                         (phase_match_ctr>`PHASE_LOCK_THRESHOLD) &&
                         (sync_errors==0) ;

  reg         pll_raw_clk_reg ;
   

  assign pll_char_out[0] =  pll_char_in;
  assign pll_char_out[1] = ~pll_char_in;


  assign pll_clk_out   =  pll_bypass ? pll_sys_clk[0] : vco_out ;
  assign pll_clk_out_l = ~pll_clk_out;

  assign pll_clk_free  =  pll_bypass ? fast_ext_clk_reg : osc_out ;
   
  assign pll_vco_out     = vco_out;
  assign pll_raw_clk_out = pll_raw_clk_reg ;

  initial pll_raw_clk_reg = 1'b0 ; 

  always @(pll_sys_clk[0]) begin
    #(`RAW_CLK_OUTPUT_DLY)
    pll_raw_clk_reg = pll_sys_clk[0];
  end


   



  initial begin
    if (! $value$plusargs("jmhz=%d", jmhz)) jmhz = `DEFAULT_JMHZ ;
    ref_clk_width = 1000000/(2*jmhz) ;
    slow_ext_clk_reg = 1'b0 ;
    forever begin
      #(ref_clk_width) slow_ext_clk_reg = ~slow_ext_clk_reg ; 
    end
  end












  initial begin
    fast_ext_clk_jdiv = `DEFAULT_JDIV ;
    forever begin
      @(jdiv) @(negedge slow_ext_clk_reg) #1
      fast_ext_clk_jdiv = jdiv ;
    end    
  end

  initial begin
    fast_ext_clk_reg = 1'b0 ;
    forever begin
      @(slow_ext_clk_reg)
      fast_ext_clk_reg = 1'b1 ;
      fast_ext_clk_width = ref_clk_width/(2*fast_ext_clk_jdiv) ;
      repeat ((2*fast_ext_clk_jdiv)-1)
        #(fast_ext_clk_width) fast_ext_clk_reg = ~fast_ext_clk_reg ;
    end
  end





  initial begin
    ref_clk_vld = 1'b0 ;
    @(posedge ref_clk) ref_clk_last_edge = $time ;
    @(negedge ref_clk) ref_clk_this_edge = $time ;
    forever begin
      @(ref_clk)
      ref_clk_last_edge = ref_clk_this_edge ;
      ref_clk_this_edge = $time ;
      if ((ref_clk_this_edge-ref_clk_last_edge) == ref_clk_width)
        ref_clk_vld = 1'b1 ; 
      else
        ref_clk_vld = 1'b0 ;
    end
  end



  initial begin
    fast_int_clk_jdiv = `DEFAULT_JDIV ;
    forever begin
      @(jdiv) @(negedge ref_clk) #1
      fast_int_clk_jdiv = jdiv ;
    end    
  end

  initial begin
    fast_int_clk_reg = 1'b0 ;
    #1
    forever begin
      @(ref_clk)
      fast_int_clk_reg = 1'b1 ;
      fast_int_clk_width  = ref_clk_width/(2*fast_int_clk_jdiv) ;
      fast_int_clk_residue= ref_clk_width%(2*fast_int_clk_jdiv) ;
      repeat ((2*fast_int_clk_jdiv)-1)
        #(fast_int_clk_width) fast_int_clk_reg = ~fast_int_clk_reg ;
    end
  end







  initial begin
    osc_reg0 = 0;
    osc_reg1 = 0;
    osc_reg2 = 0;
    osc_reg3 = 0;
    osc_out  = 0;
    osc_dly0 = 0;
    osc_dly1 = 0;
    osc_dly2 = 0;
    osc_dly3 = 0;
    osc_dly0_set = 0;
    osc_dly1_set = 0;
    osc_dly2_set = 0;
    osc_dly3_set = 0;
  end

  always @(negedge pll_arst_l) begin
    osc_dly0 = 0;
    osc_dly1 = 0;
    osc_dly2 = 0;
    osc_dly3 = 0;
    osc_dly0_set = 0;
    osc_dly1_set = 0;
    osc_dly2_set = 0;
    osc_dly3_set = 0;
  end

  always @(posedge fast_int_clk_reg) begin
     #(osc_dly0) osc_reg0 = 1'b1;
  end

  always @(negedge fast_int_clk_reg) begin
     #(osc_dly0) osc_reg0 = 1'b0;
  end
 
  always @(posedge osc_reg0) begin
     #(osc_dly1) osc_reg1 = 1'b1;
  end

  always @(negedge osc_reg0) begin
     #(osc_dly1) osc_reg1 = 1'b0;
  end
 
  always @(posedge osc_reg1) begin
     #(osc_dly2) osc_reg2 = 1'b1;
  end

  always @(negedge osc_reg1) begin
     #(osc_dly2) osc_reg2 = 1'b0;
  end
 
  always @(posedge osc_reg2) begin
     #(osc_dly3) osc_reg3 = 1'b1;
  end

  always @(negedge osc_reg2) begin
     #(osc_dly3) osc_reg3 = 1'b0;
  end
 
  always @(posedge osc_reg3) begin
     #(`OSC_DLY) osc_out = 1'b1;
  end

  always @(negedge osc_reg3) begin
     #(`OSC_DLY) osc_out = 1'b0;
  end








  reg vco_pump_up ;
   
  initial begin
    freq_step_ctr = `FREQ_STEP_COUNT;
    vco_pump_up   = 1'b1 ;
    #1
    forever begin
      @(pll_arst_l)
      if ( pll_arst_l===0 ) begin
        freq_step_ctr <= `FREQ_STEP_COUNT;
        vco_pump_up   = 1'b0 ;
      end
      else if ( pll_arst_l === 1 ) begin
        #(`PLL_START_UP_DLY); 
        if( pll_arst_l === 1 )
          vco_pump_up = 1'b1 ;
      end
    end
  end
   
  always @(posedge ref_clk) begin
    if ( (freq_step_ctr>0) && (vco_pump_up==1'b1) )
      freq_step_ctr <= freq_step_ctr-1;
  end

  assign freq_locked = (freq_step_ctr===0) ;





  initial begin
    vco_reg = 1'b0;
    vco_off = 1'b0;
  end

  always begin
    if (pll_arst_l === 1'b0) begin
      vco_reg = 1'b0;
      vco_off = 1'b1;
      @(posedge pll_arst_l) ;  
      vco_off  = 0;
    end
   
    else if (vco_pump_up === 1'b0) begin
      @(posedge vco_pump_up or negedge pll_arst_l) ; 
    end

    else begin
       repeat (freq_step_ctr+1) @(posedge osc_out) ;
       vco_reg = ~vco_reg ;
    end
  end



  assign vco_out = vco_reg & ~vco_off;










  initial begin
    phase_locked = 0;
    edge_locked  = 0;
  end

  always begin

    if (pll_bypass===1'b1) begin
      @(negedge pll_bypass); 
    end

    else if (pll_arst_l===1'b0) begin
      phase_locked = 0;  
      edge_locked  = 0;
      @(posedge pll_arst_l);        
    end

    else if (freq_locked===1'b0) begin
      @(posedge freq_locked)
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if (phase_locked===1'b0) begin
      @(posedge feedback) beg_time = $time ;
      @(posedge ref_clk)  end_time = $time ;

      if ((end_time-beg_time)<(4*fast_int_clk_width+fast_int_clk_residue)) begin
        phase_locked= 1'b1 ;
      end
           
      else begin

        @(ref_clk)
        @(negedge vco_reg)
        #1
        vco_off <= 1'b1;
        @(vco_reg)
        @(vco_reg)
        #1
        vco_off <= 1'b0;
        #(`FEEDBACK_DLY_MAX) ; 
      end
    end
     
    else if (edge_locked===1'b1) begin
      @(negedge pll_arst_l) ;
    end

    else if ( osc_dly0_set === 1'b0 ) begin    
      osc_dly0 = (end_time-beg_time)/4;
      osc_dly0_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly1_set === 1'b0 ) begin    
      osc_dly1 = (end_time-beg_time)/4;
      osc_dly1_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly2_set === 1'b0 ) begin    
      osc_dly2 = (end_time-beg_time)/4;
      osc_dly2_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly3_set === 1'b0 ) begin    
      osc_dly3 = (end_time-beg_time) - (osc_dly0+osc_dly1+osc_dly2) ;
      osc_dly3_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else begin
      edge_locked = 1;
    end

  end
   

   





































   




  initial begin
    phase_match_ctr = 0;
    sync_errors     = 0;
  end

  always @(negedge pll_arst_l) begin
    phase_match_ctr = 0;          
    sync_errors     = 0;
  end

  always @(posedge ref_clk or posedge feedback) begin

      #1
                       
      if ( ref_clk==feedback ) begin
        phase_match_ctr <= phase_match_ctr+1;
      end

      else begin

        if (pll_lock==1) sync_errors <= sync_errors+1;
        phase_match_ctr <= 0;          
      end

  end







  initial begin
    #10 if ( vreg_seldb_l !== 1'b0 )
	`ifdef MODELSIM
      $display("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
	`else  
      $error("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
	`endif  

    forever begin @ ( vreg_seldb_l )    
	`ifdef MODELSIM
      $display("bw_pll", "%m vreg_seldb_l changing during sim\n" );
	`else  
      $error("bw_pll", "%m vreg_seldb_l changing during sim\n" );
	`endif  
    end
  end

  initial begin
    #10 if ( pll_clamp_fltr !== 1'b0 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
	`endif
	
    forever begin @ ( pll_clamp_fltr )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
	`endif
    end
  end










  initial begin
    #10 if ( pll_div1 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div1 not low at t=1\n" );
	`else
      $error("bw_pll", "%m pll_div1 not low at t=1\n" );
	`endif  	

    forever begin @ ( pll_div1 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div1 changing during sim\n" );
	`else
      $error("bw_pll", "%m pll_div1 changing during sim\n" );
	`endif
    end
  end

  initial begin
    #10 if ( pll_div2 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div2 not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_div2 not low at t=1\n" );
 	`endif
	
    forever begin @ ( pll_div2 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div2 changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_div2 changing during sim\n" );
	`endif  
    end
  end

  initial begin
    #10 if ( pll_div3 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div3 not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_div3 not low at t=1\n" );
	`endif
    forever begin @ ( pll_div3 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div3 changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_div3 changing during sim\n" );
	`endif
    end
  end
             


endmodule
module bw_pll (



  pll_sys_clk ,
  pll_bypass ,
  pll_arst_l ,
  l2clk ,
  pll_clamp_fltr ,
  pll_div1 ,

  pll_div2 ,


  pll_div3 ,

  vdd_pll ,
  pll_char_in ,
  testmode ,
  vreg_seldb_l ,


  pll_raw_clk_out ,
  pll_vco_out ,
  pll_clk_out ,
  pll_clk_out_l ,
  pll_char_out
);


  input [1:0] pll_sys_clk;
  input       pll_bypass;
  input       pll_arst_l;
  input       l2clk;
  input       pll_clamp_fltr;
  input [5:0] pll_div1;
  input [5:0] pll_div2;
  input [5:0] pll_div3;
  input       vdd_pll;
  input       pll_char_in;
  input       testmode;
  input       vreg_seldb_l;
 
  output       pll_raw_clk_out;
  output       pll_vco_out;
  output       pll_clk_out;
  output       pll_clk_out_l;
  output [1:0] pll_char_out;



  wire  [4:0] jdiv ;
  reg   [7:0] jmhz ;

  integer     ref_clk_last_edge ;
  integer     ref_clk_this_edge ;
  integer     ref_clk_width ;
  reg         ref_clk_vld ;

  reg         slow_ext_clk_reg ;

  reg         fast_ext_clk_reg ;
  integer     fast_ext_clk_jdiv;
  integer     fast_ext_clk_width;

  reg         fast_int_clk_reg ;
  integer     fast_int_clk_jdiv ;
  integer     fast_int_clk_width ;
  integer     fast_int_clk_residue ;

  reg         osc_reg0;
  reg         osc_reg1;
  reg         osc_reg2;
  reg         osc_reg3;
  reg         osc_out;
   
  integer     osc_dly0;
  integer     osc_dly1;
  integer     osc_dly2;
  integer     osc_dly3;

  reg         osc_dly0_set;
  reg         osc_dly1_set;
  reg         osc_dly2_set;
  reg         osc_dly3_set;

  reg         vco_reg;
  reg         vco_off;
  wire        vco_out;

  integer     freq_step_ctr;
  wire        freq_locked ;
  reg         phase_locked;
  reg         edge_locked;
  integer     phase_match_ctr;
  integer     sync_errors;

  wire        ref_clk  = pll_sys_clk[0] ;
  wire        feedback = l2clk ; 

  integer     beg_time, end_time ;

  wire        pll_clk_free ;

  wire        pll_lock = freq_locked && phase_locked &&
                         (phase_match_ctr>`PHASE_LOCK_THRESHOLD) &&
                         (sync_errors==0) ;

  reg         pll_raw_clk_reg ;
   

  assign pll_char_out[0] =  pll_char_in;
  assign pll_char_out[1] = ~pll_char_in;


  assign pll_clk_out   =  pll_bypass ? pll_sys_clk[0] : vco_out ;
  assign pll_clk_out_l = ~pll_clk_out;

  assign pll_clk_free  =  pll_bypass ? fast_ext_clk_reg : osc_out ;
   
  assign pll_vco_out     = vco_out;
  assign pll_raw_clk_out = pll_raw_clk_reg ;

  initial pll_raw_clk_reg = 1'b0 ; 

  always @(pll_sys_clk[0]) begin
    #(`RAW_CLK_OUTPUT_DLY)
    pll_raw_clk_reg = pll_sys_clk[0];
  end


   



  initial begin
    if (! $value$plusargs("jmhz=%d", jmhz)) jmhz = `DEFAULT_JMHZ ;
    ref_clk_width = 1000000/(2*jmhz) ;
    slow_ext_clk_reg = 1'b0 ;
    forever begin
      #(ref_clk_width) slow_ext_clk_reg = ~slow_ext_clk_reg ; 
    end
  end












  initial begin
    fast_ext_clk_jdiv = `DEFAULT_JDIV ;
    forever begin
      @(jdiv) @(negedge slow_ext_clk_reg) #1
      fast_ext_clk_jdiv = jdiv ;
    end    
  end

  initial begin
    fast_ext_clk_reg = 1'b0 ;
    forever begin
      @(slow_ext_clk_reg)
      fast_ext_clk_reg = 1'b1 ;
      fast_ext_clk_width = ref_clk_width/(2*fast_ext_clk_jdiv) ;
      repeat ((2*fast_ext_clk_jdiv)-1)
        #(fast_ext_clk_width) fast_ext_clk_reg = ~fast_ext_clk_reg ;
    end
  end





  initial begin
    ref_clk_vld = 1'b0 ;
    @(posedge ref_clk) ref_clk_last_edge = $time ;
    @(negedge ref_clk) ref_clk_this_edge = $time ;
    forever begin
      @(ref_clk)
      ref_clk_last_edge = ref_clk_this_edge ;
      ref_clk_this_edge = $time ;
      if ((ref_clk_this_edge-ref_clk_last_edge) == ref_clk_width)
        ref_clk_vld = 1'b1 ; 
      else
        ref_clk_vld = 1'b0 ;
    end
  end



  initial begin
    fast_int_clk_jdiv = `DEFAULT_JDIV ;
    forever begin
      @(jdiv) @(negedge ref_clk) #1
      fast_int_clk_jdiv = jdiv ;
    end    
  end

  initial begin
    fast_int_clk_reg = 1'b0 ;
    #1
    forever begin
      @(ref_clk)
      fast_int_clk_reg = 1'b1 ;
      fast_int_clk_width  = ref_clk_width/(2*fast_int_clk_jdiv) ;
      fast_int_clk_residue= ref_clk_width%(2*fast_int_clk_jdiv) ;
      repeat ((2*fast_int_clk_jdiv)-1)
        #(fast_int_clk_width) fast_int_clk_reg = ~fast_int_clk_reg ;
    end
  end







  initial begin
    osc_reg0 = 0;
    osc_reg1 = 0;
    osc_reg2 = 0;
    osc_reg3 = 0;
    osc_out  = 0;
    osc_dly0 = 0;
    osc_dly1 = 0;
    osc_dly2 = 0;
    osc_dly3 = 0;
    osc_dly0_set = 0;
    osc_dly1_set = 0;
    osc_dly2_set = 0;
    osc_dly3_set = 0;
  end

  always @(negedge pll_arst_l) begin
    osc_dly0 = 0;
    osc_dly1 = 0;
    osc_dly2 = 0;
    osc_dly3 = 0;
    osc_dly0_set = 0;
    osc_dly1_set = 0;
    osc_dly2_set = 0;
    osc_dly3_set = 0;
  end

  always @(posedge fast_int_clk_reg) begin
     #(osc_dly0) osc_reg0 = 1'b1;
  end

  always @(negedge fast_int_clk_reg) begin
     #(osc_dly0) osc_reg0 = 1'b0;
  end
 
  always @(posedge osc_reg0) begin
     #(osc_dly1) osc_reg1 = 1'b1;
  end

  always @(negedge osc_reg0) begin
     #(osc_dly1) osc_reg1 = 1'b0;
  end
 
  always @(posedge osc_reg1) begin
     #(osc_dly2) osc_reg2 = 1'b1;
  end

  always @(negedge osc_reg1) begin
     #(osc_dly2) osc_reg2 = 1'b0;
  end
 
  always @(posedge osc_reg2) begin
     #(osc_dly3) osc_reg3 = 1'b1;
  end

  always @(negedge osc_reg2) begin
     #(osc_dly3) osc_reg3 = 1'b0;
  end
 
  always @(posedge osc_reg3) begin
     #(`OSC_DLY) osc_out = 1'b1;
  end

  always @(negedge osc_reg3) begin
     #(`OSC_DLY) osc_out = 1'b0;
  end








  reg vco_pump_up ;
   
  initial begin
    freq_step_ctr = `FREQ_STEP_COUNT;
    vco_pump_up   = 1'b1 ;
    #1
    forever begin
      @(pll_arst_l)
      if ( pll_arst_l===0 ) begin
        freq_step_ctr <= `FREQ_STEP_COUNT;
        vco_pump_up   = 1'b0 ;
      end
      else if ( pll_arst_l === 1 ) begin
        #(`PLL_START_UP_DLY); 
        if( pll_arst_l === 1 )
          vco_pump_up = 1'b1 ;
      end
    end
  end
   
  always @(posedge ref_clk) begin
    if ( (freq_step_ctr>0) && (vco_pump_up==1'b1) )
      freq_step_ctr <= freq_step_ctr-1;
  end

  assign freq_locked = (freq_step_ctr===0) ;





  initial begin
    vco_reg = 1'b0;
    vco_off = 1'b0;
  end

  always begin
    if (pll_arst_l === 1'b0) begin
      vco_reg = 1'b0;
      vco_off = 1'b1;
      @(posedge pll_arst_l) ;  
      vco_off  = 0;
    end
   
    else if (vco_pump_up === 1'b0) begin
      @(posedge vco_pump_up or negedge pll_arst_l) ; 
    end

    else begin
       repeat (freq_step_ctr+1) @(posedge osc_out) ;
       vco_reg = ~vco_reg ;
    end
  end



  assign vco_out = vco_reg & ~vco_off;










  initial begin
    phase_locked = 0;
    edge_locked  = 0;
  end

  always begin

    if (pll_bypass===1'b1) begin
      @(negedge pll_bypass); 
    end

    else if (pll_arst_l===1'b0) begin
      phase_locked = 0;  
      edge_locked  = 0;
      @(posedge pll_arst_l);        
    end

    else if (freq_locked===1'b0) begin
      @(posedge freq_locked)
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if (phase_locked===1'b0) begin
      @(posedge feedback) beg_time = $time ;
      @(posedge ref_clk)  end_time = $time ;

      if ((end_time-beg_time)<(4*fast_int_clk_width+fast_int_clk_residue)) begin
        phase_locked= 1'b1 ;
      end
           
      else begin

        @(ref_clk)
        @(negedge vco_reg)
        #1
        vco_off <= 1'b1;
        @(vco_reg)
        @(vco_reg)
        #1
        vco_off <= 1'b0;
        #(`FEEDBACK_DLY_MAX) ; 
      end
    end
     
    else if (edge_locked===1'b1) begin
      @(negedge pll_arst_l) ;
    end

    else if ( osc_dly0_set === 1'b0 ) begin    
      osc_dly0 = (end_time-beg_time)/4;
      osc_dly0_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly1_set === 1'b0 ) begin    
      osc_dly1 = (end_time-beg_time)/4;
      osc_dly1_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly2_set === 1'b0 ) begin    
      osc_dly2 = (end_time-beg_time)/4;
      osc_dly2_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else if ( osc_dly3_set === 1'b0 ) begin    
      osc_dly3 = (end_time-beg_time) - (osc_dly0+osc_dly1+osc_dly2) ;
      osc_dly3_set = 1'b1 ; 
      #(`FEEDBACK_DLY_MAX) ;
    end

    else begin
      edge_locked = 1;
    end

  end
   

   





































   




  initial begin
    phase_match_ctr = 0;
    sync_errors     = 0;
  end

  always @(negedge pll_arst_l) begin
    phase_match_ctr = 0;          
    sync_errors     = 0;
  end

  always @(posedge ref_clk or posedge feedback) begin

      #1
                       
      if ( ref_clk==feedback ) begin
        phase_match_ctr <= phase_match_ctr+1;
      end

      else begin

        if (pll_lock==1) sync_errors <= sync_errors+1;
        phase_match_ctr <= 0;          
      end

  end







  initial begin
    #10 if ( vreg_seldb_l !== 1'b0 )
	`ifdef MODELSIM
      $display("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
	`else  
      $error("bw_pll", "%m vreg_seldb_l not low at t=1\n" );
	`endif  

    forever begin @ ( vreg_seldb_l )    
	`ifdef MODELSIM
      $display("bw_pll", "%m vreg_seldb_l changing during sim\n" );
	`else  
      $error("bw_pll", "%m vreg_seldb_l changing during sim\n" );
	`endif  
    end
  end

  initial begin
    #10 if ( pll_clamp_fltr !== 1'b0 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_clamp_fltr not low at t=1\n" );
	`endif
	
    forever begin @ ( pll_clamp_fltr )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_clamp_fltr changing during sim\n" );
	`endif
    end
  end










  initial begin
    #10 if ( pll_div1 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div1 not low at t=1\n" );
	`else
      $error("bw_pll", "%m pll_div1 not low at t=1\n" );
	`endif  	

    forever begin @ ( pll_div1 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div1 changing during sim\n" );
	`else
      $error("bw_pll", "%m pll_div1 changing during sim\n" );
	`endif
    end
  end

  initial begin
    #10 if ( pll_div2 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div2 not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_div2 not low at t=1\n" );
 	`endif
	
    forever begin @ ( pll_div2 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div2 changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_div2 changing during sim\n" );
	`endif  
    end
  end

  initial begin
    #10 if ( pll_div3 !== 6'b000000 )
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div3 not low at t=1\n" );
	`else  
      $error("bw_pll", "%m pll_div3 not low at t=1\n" );
	`endif
    forever begin @ ( pll_div3 )    
	`ifdef MODELSIM
      $display("bw_pll", "%m pll_div3 changing during sim\n" );
	`else  
      $error("bw_pll", "%m pll_div3 changing during sim\n" );
	`endif
    end
  end
             


endmodule