data/full_repos/permissive/463395574/memory.v
1: b'%Error: data/full_repos/permissive/463395574/memory.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/memory.v:6: Define or directive not defined: \'`ADDR_SIZE\'\n    input  [`ADDR_SIZE-1:0]   addr,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:7: Define or directive not defined: \'`INSTR_SIZE\'\n    output [`INSTR_SIZE-1:0]  data\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:9: Define or directive not defined: \'`INSTR_SIZE\'\n    reg [`INSTR_SIZE-1:0] RAM[`IMEM_SIZE-1:0];\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:9: Define or directive not defined: \'`IMEM_SIZE\'\n    reg [`INSTR_SIZE-1:0] RAM[`IMEM_SIZE-1:0];\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:17: Define or directive not defined: \'`ADDR_SIZE\'\n    input  [`ADDR_SIZE-1:0] addr,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:19: Define or directive not defined: \'`WORD_LEN\'\n    input  [`WORD_LEN-1:0]  writeData,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:20: Define or directive not defined: \'`WORD_LEN\'\n    output reg [`WORD_LEN-1:0]  readData\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:22: Define or directive not defined: \'`WORD_LEN\'\n    reg [`WORD_LEN-1:0] RAM[`DMEM_SIZE-1:0];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:22: Define or directive not defined: \'`DMEM_SIZE\'\n    reg [`WORD_LEN-1:0] RAM[`DMEM_SIZE-1:0];\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:25: Define or directive not defined: \'`DMEM_SIZE_WIDTH\'\n    wire [`DMEM_SIZE_WIDTH-1:0] realAccessAddr = addr[`ADDR_SIZE-1:2];\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:25: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`DMEM_SIZE_WIDTH-1:0] realAccessAddr = addr[`ADDR_SIZE-1:2];\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:26: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] readWord = RAM[realAccessAddr];\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:33: Define or directive not defined: \'`FUNCT3_BYTE\'\n            `FUNCT3_BYTE:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:33: syntax error, unexpected \':\', expecting endcase\n            `FUNCT3_BYTE:\n                        ^\n%Error: data/full_repos/permissive/463395574/memory.v:35: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b00: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:36: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b01: readData <= {{{`WORD_LEN-8}{readWord[15]}}, readWord[15:8]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:37: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b10: readData <= {{{`WORD_LEN-8}{readWord[23]}}, readWord[23:16]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:38: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b11: readData <= {{{`WORD_LEN-8}{readWord[31]}}, readWord[31:24]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:39: Define or directive not defined: \'`WORD_LEN\'\n                    default: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:41: Define or directive not defined: \'`FUNCT3_HALF\'\n            `FUNCT3_HALF:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:43: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b00: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:44: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b10: readData <= {{{`WORD_LEN-16}{readWord[31]}}, readWord[31:16]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:45: Define or directive not defined: \'`WORD_LEN\'\n                    default: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:47: Define or directive not defined: \'`FUNCT3_WORD\'\n            `FUNCT3_WORD:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:49: Define or directive not defined: \'`FUNCT3_BYTE_UNSIGNED\'\n            `FUNCT3_BYTE_UNSIGNED:\n            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:51: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b00: readData <= {{{`WORD_LEN-8}{1\'b0}}, readWord[7:0]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:52: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b01: readData <= {{{`WORD_LEN-8}{1\'b0}}, readWord[15:8]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:53: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b10: readData <= {{{`WORD_LEN-8}{1\'b0}}, readWord[23:16]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:54: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b11: readData <= {{{`WORD_LEN-8}{1\'b0}}, readWord[31:24]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:55: Define or directive not defined: \'`WORD_LEN\'\n                    default: readData <= {{{`WORD_LEN-8}{1\'b0}}, readWord[7:0]};\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:57: Define or directive not defined: \'`FUNCT3_HALF_UNSIGNED\'\n            `FUNCT3_HALF_UNSIGNED:\n            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:59: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b00: readData <= {{{`WORD_LEN-16}{1\'b0}}, readWord[15:0]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:60: Define or directive not defined: \'`WORD_LEN\'\n                    2\'b10: readData <= {{{`WORD_LEN-16}{1\'b0}}, readWord[31:16]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:61: Define or directive not defined: \'`WORD_LEN\'\n                    default: readData <= {{{`WORD_LEN-16}{1\'b0}}, readWord[15:0]};\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:72: Define or directive not defined: \'`FUNCT3_BYTE\'\n            `FUNCT3_BYTE:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:80: Define or directive not defined: \'`FUNCT3_HALF\'\n            `FUNCT3_HALF:\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/memory.v:86: Define or directive not defined: \'`FUNCT3_WORD\'\n            `FUNCT3_WORD:\n            ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module DMem(
    input                   clk, readEnable, writeEnable,
    input  [`ADDR_SIZE-1:0] addr,
    input  [2:0]            unitSize,
    input  [`WORD_LEN-1:0]  writeData,
    output reg [`WORD_LEN-1:0]  readData
);
    reg [`WORD_LEN-1:0] RAM[`DMEM_SIZE-1:0];


    wire [`DMEM_SIZE_WIDTH-1:0] realAccessAddr = addr[`ADDR_SIZE-1:2];
    wire [`WORD_LEN-1:0] readWord = RAM[realAccessAddr];
    wire [1:0] wordOffset = addr[1:0];


    always @(*)
    if (readEnable) begin
        case (unitSize)
            `FUNCT3_BYTE:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};
                    2'b01: readData <= {{{`WORD_LEN-8}{readWord[15]}}, readWord[15:8]};
                    2'b10: readData <= {{{`WORD_LEN-8}{readWord[23]}}, readWord[23:16]};
                    2'b11: readData <= {{{`WORD_LEN-8}{readWord[31]}}, readWord[31:24]};
                    default: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};
                endcase
            `FUNCT3_HALF:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};
                    2'b10: readData <= {{{`WORD_LEN-16}{readWord[31]}}, readWord[31:16]};
                    default: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};
                endcase
            `FUNCT3_WORD:
                readData <= readWord;
            `FUNCT3_BYTE_UNSIGNED:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[7:0]};
                    2'b01: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[15:8]};
                    2'b10: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[23:16]};
                    2'b11: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[31:24]};
                    default: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[7:0]};
                endcase
            `FUNCT3_HALF_UNSIGNED:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[15:0]};
                    2'b10: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[31:16]};
                    default: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[15:0]};
                endcase
            default:
                readData <= readWord;
        endcase
    end


    always @(posedge clk)
    if (writeEnable) begin
        case (unitSize)
            `FUNCT3_BYTE:
                case (wordOffset)
                    2'b00: RAM[realAccessAddr][7:0] <= writeData[7:0];
                    2'b01: RAM[realAccessAddr][15:8] <= writeData[7:0];
                    2'b10: RAM[realAccessAddr][23:16] <= writeData[7:0];
                    2'b11: RAM[realAccessAddr][31:24] <= writeData[7:0];
                    default: RAM[realAccessAddr][7:0] <= writeData[7:0];
                endcase
            `FUNCT3_HALF:
                case (wordOffset)
                    2'b00: RAM[realAccessAddr][15:0] <= writeData[15:0];
                    2'b10: RAM[realAccessAddr][31:16] <= writeData[15:0];
                    default: RAM[realAccessAddr][15:0] <= writeData[15:0];
                endcase
            `FUNCT3_WORD:
                RAM[realAccessAddr] <= writeData;
            default:
                RAM[realAccessAddr] <= writeData;
        endcase
  	end
endmodule
module DMem(
    input                   clk, readEnable, writeEnable,
    input  [`ADDR_SIZE-1:0] addr,
    input  [2:0]            unitSize,
    input  [`WORD_LEN-1:0]  writeData,
    output reg [`WORD_LEN-1:0]  readData
);

    reg [`WORD_LEN-1:0] RAM[`DMEM_SIZE-1:0];


    wire [`DMEM_SIZE_WIDTH-1:0] realAccessAddr = addr[`ADDR_SIZE-1:2];
    wire [`WORD_LEN-1:0] readWord = RAM[realAccessAddr];
    wire [1:0] wordOffset = addr[1:0];


    always @(*)
    if (readEnable) begin
        case (unitSize)
            `FUNCT3_BYTE:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};
                    2'b01: readData <= {{{`WORD_LEN-8}{readWord[15]}}, readWord[15:8]};
                    2'b10: readData <= {{{`WORD_LEN-8}{readWord[23]}}, readWord[23:16]};
                    2'b11: readData <= {{{`WORD_LEN-8}{readWord[31]}}, readWord[31:24]};
                    default: readData <= {{{`WORD_LEN-8}{readWord[7]}}, readWord[7:0]};
                endcase
            `FUNCT3_HALF:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};
                    2'b10: readData <= {{{`WORD_LEN-16}{readWord[31]}}, readWord[31:16]};
                    default: readData <= {{{`WORD_LEN-16}{readWord[15]}}, readWord[15:0]};
                endcase
            `FUNCT3_WORD:
                readData <= readWord;
            `FUNCT3_BYTE_UNSIGNED:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[7:0]};
                    2'b01: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[15:8]};
                    2'b10: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[23:16]};
                    2'b11: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[31:24]};
                    default: readData <= {{{`WORD_LEN-8}{1'b0}}, readWord[7:0]};
                endcase
            `FUNCT3_HALF_UNSIGNED:
                case (wordOffset)
                    2'b00: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[15:0]};
                    2'b10: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[31:16]};
                    default: readData <= {{{`WORD_LEN-16}{1'b0}}, readWord[15:0]};
                endcase
            default:
                readData <= readWord;
        endcase
    end


    always @(posedge clk)
    if (writeEnable) begin
        case (unitSize)
            `FUNCT3_BYTE:
                case (wordOffset)
                    2'b00: RAM[realAccessAddr][7:0] <= writeData[7:0];
                    2'b01: RAM[realAccessAddr][15:8] <= writeData[7:0];
                    2'b10: RAM[realAccessAddr][23:16] <= writeData[7:0];
                    2'b11: RAM[realAccessAddr][31:24] <= writeData[7:0];
                    default: RAM[realAccessAddr][7:0] <= writeData[7:0];
                endcase
            `FUNCT3_HALF:
                case (wordOffset)
                    2'b00: RAM[realAccessAddr][15:0] <= writeData[15:0];
                    2'b10: RAM[realAccessAddr][31:16] <= writeData[15:0];
                    default: RAM[realAccessAddr][15:0] <= writeData[15:0];
                endcase
            `FUNCT3_WORD:
                RAM[realAccessAddr] <= writeData;
            default:
                RAM[realAccessAddr] <= writeData;
        endcase
  	end
endmodule