data/full_repos/permissive/420101818/RegMem_tb.v
1: b'%Error: data/full_repos/permissive/420101818/RegMem_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/420101818/RegMem_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, tb_reg_mem);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420101818/RegMem_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n            repeat (2) #1 clk = ~clk;\n                       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420101818/RegMem_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/420101818/RegMem_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n            repeat (2) #1 clk = ~clk;\n                       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_reg_mem;

    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;

    reg [ADDR_BITS-1:0] addr;
    reg [DATA_WIDTH-1:0] data_in;
    wire [DATA_WIDTH-1:0] data_out;
    reg wen, clk;


    reg_mem #(DATA_WIDTH,ADDR_BITS) RM (addr, data_in, wen, clk, data_out);

    initial begin
        /
        
        clk = 0;
        wen = 1;
       

        for(int i=10;i<18;i=i+1) 
        begin
            data_in = i; 
            addr = (i+2);
            $display("Write %d to address %d",data_in,addr);
            repeat (2) #1 clk = ~clk;
        end
        wen =0;
        #1;

        for(int i=10;i<18;i=i+1) 
        begin
            data_in = i; 
            addr = (i+2);
            $display("Read %d from address %d",data_in,addr);
            repeat (2) #1 clk = ~clk;
        end


        
    end
endmodule
module tb_reg_mem;


    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;

    reg [ADDR_BITS-1:0] addr;
    reg [DATA_WIDTH-1:0] data_in;
    wire [DATA_WIDTH-1:0] data_out;
    reg wen, clk;


    reg_mem #(DATA_WIDTH,ADDR_BITS) RM (addr, data_in, wen, clk, data_out);

    initial begin
        /
        
        clk = 0;
        wen = 1;
       

        for(int i=10;i<18;i=i+1) 
        begin
            data_in = i; 
            addr = (i+2);
            $display("Write %d to address %d",data_in,addr);
            repeat (2) #1 clk = ~clk;
        end
        wen =0;
        #1;

        for(int i=10;i<18;i=i+1) 
        begin
            data_in = i; 
            addr = (i+2);
            $display("Read %d from address %d",data_in,addr);
            repeat (2) #1 clk = ~clk;
        end


        
    end
endmodule