data/full_repos/permissive/468612001/Week06/fsm/fsm.v
data/verilator_xmls/36d2cce6-5df5-4480-ac8d-0070fed7f903.xml
module fsm(clk, rst, bypss, out);
	input clk, rst;
	input bypss;
	output reg [1:0] out;
	parameter ST0 = 2'b00, ST1 = 2'b01, ST2 = 2'b10, ST3 = 2'b11;
	
	reg [1:0] state, next;
	
	always @(posedge clk or negedge rst) begin

		if(!rst) state <= ST0;
		else		state <= next;
	end
	
	always @(state or bypss) begin

		case(state)
			ST0:  next = ST1;
			ST1:	if(bypss == 1)	next = ST3;
					else	next = ST2;
			ST2:	next = ST3;
			ST3:	next = ST0;
		endcase
	end
	
	always @(posedge clk or negedge rst) begin

			if(!rst) out <= 2'b00;
			else begin
				case(next)
					ST0: out <= 2'b00;
					ST1: out <= 2'b01;
					ST2: out <= 2'b10;
					ST3: out <= 2'b11;
				endcase
			end
	end
endmodule
module fsm(clk, rst, bypss, out);

	input clk, rst;
	input bypss;
	output reg [1:0] out;
	parameter ST0 = 2'b00, ST1 = 2'b01, ST2 = 2'b10, ST3 = 2'b11;
	
	reg [1:0] state, next;
	
	always @(posedge clk or negedge rst) begin

		if(!rst) state <= ST0;
		else		state <= next;
	end
	
	always @(state or bypss) begin

		case(state)
			ST0:  next = ST1;
			ST1:	if(bypss == 1)	next = ST3;
					else	next = ST2;
			ST2:	next = ST3;
			ST3:	next = ST0;
		endcase
	end
	
	always @(posedge clk or negedge rst) begin

			if(!rst) out <= 2'b00;
			else begin
				case(next)
					ST0: out <= 2'b00;
					ST1: out <= 2'b01;
					ST2: out <= 2'b10;
					ST3: out <= 2'b11;
				endcase
			end
	end
endmodule