data/full_repos/permissive/416882019/test/wb_openram_wrapper_tb.v
1: b'%Error: data/full_repos/permissive/416882019/test/wb_openram_wrapper_tb.v:4: Cannot find include file: sky130_sram_1kbyte_1rw1r_32x256_8.v\n`include "sky130_sram_1kbyte_1rw1r_32x256_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416882019/test,data/full_repos/permissive/416882019/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             data/full_repos/permissive/416882019/test,data/full_repos/permissive/416882019/sky130_sram_1kbyte_1rw1r_32x256_8.v.v\n             data/full_repos/permissive/416882019/test,data/full_repos/permissive/416882019/sky130_sram_1kbyte_1rw1r_32x256_8.v.sv\n             sky130_sram_1kbyte_1rw1r_32x256_8.v\n             sky130_sram_1kbyte_1rw1r_32x256_8.v.v\n             sky130_sram_1kbyte_1rw1r_32x256_8.v.sv\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.v.v\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.v.sv\n%Error: data/full_repos/permissive/416882019/test/wb_openram_wrapper_tb.v:38: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("wb_openram_wrapper.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/416882019/test/wb_openram_wrapper_tb.v:39: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0, wb_openram_wrapper_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/416882019/test/wb_openram_wrapper_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module wb_openram_wrapper_tb (


    input           		writable_port_req,


    input           		wb_a_clk_i,
    input           		wb_a_rst_i,
    input           		wbs_a_stb_i,
    input           		wbs_a_cyc_i,
    input           		wbs_a_we_i,
    input   [3:0]   		wbs_a_sel_i,
    input   [31:0]  		wbs_a_dat_i,
    input   [10:0]          wbs_a_adr_i,
    output          		wbs_a_ack_o,
    output  [31:0]  		wbs_a_dat_o,


    input           		wb_b_clk_i,
    input           		wb_b_rst_i,
    input           		wbs_b_stb_i,
    input           		wbs_b_cyc_i,
    input           		wbs_b_we_i,
    input   [3:0]   		wbs_b_sel_i,
    input   [31:0]  		wbs_b_dat_i,
    input   [9:0] 	        wbs_b_adr_i,
    output          		wbs_b_ack_o,
    output  [31:0]  		wbs_b_dat_o
);

    initial begin
        $dumpfile ("wb_openram_wrapper.vcd");
        $dumpvars (0, wb_openram_wrapper_tb);
        #1;
    end


    wire openram_clk0;
    wire openram_csb0;
    wire openram_web0;
    wire [3:0] openram_wmask0;
    wire [7:0] openram_addr0;
    wire [31:0] openram_din0;
    wire [31:0] openram_dout0;
    wire openram_clk1;
    wire openram_csb1;
    wire [7:0] openram_addr1;
    wire [31:0] openram_dout1;

    sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
    (
        .clk0 (openram_clk0),
        .csb0 (openram_csb0),
        .web0 (openram_web0),
        .wmask0 (openram_wmask0),
        .addr0 (openram_addr0),
        .din0 (openram_din0),
        .dout0 (openram_dout0),

        .clk1 (openram_clk1),
        .csb1 (openram_csb1),
        .addr1 (openram_addr1),
        .dout1 (openram_dout1)
    );

    wb_openram_wrapper wb_openram_wrapper
    (
        .writable_port_req  (writable_port_req),


        .wb_a_clk_i     (wb_a_clk_i),
        .wb_a_rst_i     (wb_a_rst_i),
        .wbs_a_stb_i    (wbs_a_stb_i),
        .wbs_a_cyc_i    (wbs_a_cyc_i),
        .wbs_a_we_i     (wbs_a_we_i),
        .wbs_a_sel_i    (wbs_a_sel_i),
        .wbs_a_dat_i    (wbs_a_dat_i),
        .wbs_a_adr_i    (wbs_a_adr_i),
        .wbs_a_ack_o    (wbs_a_ack_o),
        .wbs_a_dat_o    (wbs_a_dat_o),


        .wb_b_clk_i     (wb_b_clk_i),
        .wb_b_rst_i     (wb_b_rst_i),
        .wbs_b_stb_i    (wbs_b_stb_i),
        .wbs_b_cyc_i    (wbs_b_cyc_i),
        .wbs_b_we_i     (wbs_b_we_i),
        .wbs_b_sel_i    (wbs_b_sel_i),
        .wbs_b_dat_i    (wbs_b_dat_i),
        .wbs_b_adr_i    (wbs_b_adr_i),
        .wbs_b_ack_o    (wbs_b_ack_o),
        .wbs_b_dat_o    (wbs_b_dat_o),



        .ram_clk0       (openram_clk0),
        .ram_csb0       (openram_csb0),
        .ram_web0       (openram_web0),
        .ram_wmask0     (openram_wmask0),
        .ram_addr0      (openram_addr0),
        .ram_din0       (openram_din0),
        .ram_dout0      (openram_dout0),


        .ram_clk1       (openram_clk1),
        .ram_csb1       (openram_csb1),
        .ram_addr1      (openram_addr1),
        .ram_dout1      (openram_dout1)   
    );

endmodule
module wb_openram_wrapper_tb (


    input           		writable_port_req,


    input           		wb_a_clk_i,
    input           		wb_a_rst_i,
    input           		wbs_a_stb_i,
    input           		wbs_a_cyc_i,
    input           		wbs_a_we_i,
    input   [3:0]   		wbs_a_sel_i,
    input   [31:0]  		wbs_a_dat_i,
    input   [10:0]          wbs_a_adr_i,
    output          		wbs_a_ack_o,
    output  [31:0]  		wbs_a_dat_o,


    input           		wb_b_clk_i,
    input           		wb_b_rst_i,
    input           		wbs_b_stb_i,
    input           		wbs_b_cyc_i,
    input           		wbs_b_we_i,
    input   [3:0]   		wbs_b_sel_i,
    input   [31:0]  		wbs_b_dat_i,
    input   [9:0] 	        wbs_b_adr_i,
    output          		wbs_b_ack_o,
    output  [31:0]  		wbs_b_dat_o
);


    initial begin
        $dumpfile ("wb_openram_wrapper.vcd");
        $dumpvars (0, wb_openram_wrapper_tb);
        #1;
    end


    wire openram_clk0;
    wire openram_csb0;
    wire openram_web0;
    wire [3:0] openram_wmask0;
    wire [7:0] openram_addr0;
    wire [31:0] openram_din0;
    wire [31:0] openram_dout0;
    wire openram_clk1;
    wire openram_csb1;
    wire [7:0] openram_addr1;
    wire [31:0] openram_dout1;

    sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
    (
        .clk0 (openram_clk0),
        .csb0 (openram_csb0),
        .web0 (openram_web0),
        .wmask0 (openram_wmask0),
        .addr0 (openram_addr0),
        .din0 (openram_din0),
        .dout0 (openram_dout0),

        .clk1 (openram_clk1),
        .csb1 (openram_csb1),
        .addr1 (openram_addr1),
        .dout1 (openram_dout1)
    );

    wb_openram_wrapper wb_openram_wrapper
    (
        .writable_port_req  (writable_port_req),


        .wb_a_clk_i     (wb_a_clk_i),
        .wb_a_rst_i     (wb_a_rst_i),
        .wbs_a_stb_i    (wbs_a_stb_i),
        .wbs_a_cyc_i    (wbs_a_cyc_i),
        .wbs_a_we_i     (wbs_a_we_i),
        .wbs_a_sel_i    (wbs_a_sel_i),
        .wbs_a_dat_i    (wbs_a_dat_i),
        .wbs_a_adr_i    (wbs_a_adr_i),
        .wbs_a_ack_o    (wbs_a_ack_o),
        .wbs_a_dat_o    (wbs_a_dat_o),


        .wb_b_clk_i     (wb_b_clk_i),
        .wb_b_rst_i     (wb_b_rst_i),
        .wbs_b_stb_i    (wbs_b_stb_i),
        .wbs_b_cyc_i    (wbs_b_cyc_i),
        .wbs_b_we_i     (wbs_b_we_i),
        .wbs_b_sel_i    (wbs_b_sel_i),
        .wbs_b_dat_i    (wbs_b_dat_i),
        .wbs_b_adr_i    (wbs_b_adr_i),
        .wbs_b_ack_o    (wbs_b_ack_o),
        .wbs_b_dat_o    (wbs_b_dat_o),



        .ram_clk0       (openram_clk0),
        .ram_csb0       (openram_csb0),
        .ram_web0       (openram_web0),
        .ram_wmask0     (openram_wmask0),
        .ram_addr0      (openram_addr0),
        .ram_din0       (openram_din0),
        .ram_dout0      (openram_dout0),


        .ram_clk1       (openram_clk1),
        .ram_csb1       (openram_csb1),
        .ram_addr1      (openram_addr1),
        .ram_dout1      (openram_dout1)   
    );

endmodule