data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:1: Cannot find include file: VX_cache_define.vh\n`include "VX_cache_define.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/cache,data/full_repos/permissive/473423187/VX_cache_define.vh\n             data/full_repos/permissive/473423187/hw/rtl/cache,data/full_repos/permissive/473423187/VX_cache_define.vh.v\n             data/full_repos/permissive/473423187/hw/rtl/cache,data/full_repos/permissive/473423187/VX_cache_define.vh.sv\n             VX_cache_define.vh\n             VX_cache_define.vh.v\n             VX_cache_define.vh.sv\n             obj_dir/VX_cache_define.vh\n             obj_dir/VX_cache_define.vh.v\n             obj_dir/VX_cache_define.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:19: Define or directive not defined: \'`UP\'\n    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)\n                                  ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:19: Define or directive not defined: \'`WORD_SELECT_BITS\'\n    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)\n                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)\n                                                       ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                          reset,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                          stall,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                          read,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                          fill, \n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                          write,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`LINE_ADDR_WIDTH-1:0]    addr,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:36: Define or directive not defined: \'`LINE_ADDR_WIDTH\'\n    input wire[`LINE_ADDR_WIDTH-1:0]    addr,\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [NUM_PORTS-1:0]          pmask,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:40: Define or directive not defined: \'`WORDS_PER_LINE\'\n    input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:40: Define or directive not defined: \'`WORD_WIDTH\'\n    input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data,\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:41: Define or directive not defined: \'`WORD_WIDTH\'\n    input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data,\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data\n    ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:42: Define or directive not defined: \'`WORD_WIDTH\'\n    output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:43: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:44: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (CACHE_ID)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:45: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (BANK_ID)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:46: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (WORD_SIZE)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:47: Define or directive not defined: \'`UNUSED_VAR\'\n    `UNUSED_VAR (reset)\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:48: Define or directive not defined: \'`UNUSED_VAR\'\n    `UNUSED_VAR (addr)\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:49: Define or directive not defined: \'`UNUSED_VAR\'\n    `UNUSED_VAR (read)\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:53: Define or directive not defined: \'`WORDS_PER_LINE\'\n    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:53: Define or directive not defined: \'`WORD_WIDTH\'\n    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata;\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:54: Define or directive not defined: \'`WORDS_PER_LINE\'\n    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:54: Define or directive not defined: \'`WORD_WIDTH\'\n    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata;\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:57: Define or directive not defined: \'`LINE_SELECT_BITS\'\n    wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:57: Define or directive not defined: \'`LINE_SELECT_BITS\'\n    wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];\n                                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:59: syntax error, unexpected if\n    if (WRITE_ENABLE) begin\n    ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:60: Define or directive not defined: \'`WORDS_PER_LINE\'\n        if (`WORDS_PER_LINE > 1) begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:61: Define or directive not defined: \'`WORDS_PER_LINE\'\n            reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r;\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:61: Define or directive not defined: \'`WORD_WIDTH\'\n            reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r;\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:62: Define or directive not defined: \'`WORDS_PER_LINE\'\n            reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r;\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:63: syntax error, unexpected if\n            if (NUM_PORTS > 1) begin\n            ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:67: syntax error, unexpected IDENTIFIER\n                    for (integer i = 0; i < NUM_PORTS; ++i) begin\n                                        ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:75: Define or directive not defined: \'`UNUSED_VAR\'\n                `UNUSED_VAR (pmask)\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:77: Define or directive not defined: \'`WORDS_PER_LINE\'\n                    wdata_r = {`WORDS_PER_LINE{write_data}};\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:85: Define or directive not defined: \'`UNUSED_VAR\'\n            `UNUSED_VAR (wsel)\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:86: Define or directive not defined: \'`UNUSED_VAR\'\n            `UNUSED_VAR (pmask)\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:91: Define or directive not defined: \'`UNUSED_VAR\'\n        `UNUSED_VAR (write)\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:92: Define or directive not defined: \'`UNUSED_VAR\'\n        `UNUSED_VAR (byteen)\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:93: Define or directive not defined: \'`UNUSED_VAR\'\n        `UNUSED_VAR (pmask)\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:94: Define or directive not defined: \'`UNUSED_VAR\'\n        `UNUSED_VAR (write_data)\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/cache/VX_data_access.sv:100: Define or directive not defined: \'`CACHE_LINE_WIDTH\'\n        .DATAW      (`CACHE_LINE_WIDTH),\n                     ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module VX_data_access #(
    parameter CACHE_ID          = 0,
    parameter BANK_ID           = 0,

    parameter CACHE_SIZE        = 1, 

    parameter CACHE_LINE_SIZE   = 1, 

    parameter NUM_BANKS         = 1, 

    parameter NUM_PORTS         = 1,

    parameter WORD_SIZE         = 1,

    parameter WRITE_ENABLE      = 1,

    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)
) (
    input wire                          clk,
    input wire                          reset,

`ifdef DBG_CACHE_REQ_INFO
`IGNORE_UNUSED_BEGIN
    input wire[31:0]                    debug_pc,
    input wire[`NW_BITS-1:0]            debug_wid,
`IGNORE_UNUSED_END
`endif

    input wire                          stall,

    input wire                          read,
    input wire                          fill, 
    input wire                          write,
    input wire[`LINE_ADDR_WIDTH-1:0]    addr,
    input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel,
    input wire [NUM_PORTS-1:0]          pmask,
    input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen,
    input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,
    input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data,
    output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data
);
    `UNUSED_PARAM (CACHE_ID)
    `UNUSED_PARAM (BANK_ID)
    `UNUSED_PARAM (WORD_SIZE)
    `UNUSED_VAR (reset)
    `UNUSED_VAR (addr)
    `UNUSED_VAR (read)

    localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;

    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata;
    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata;
    wire [BYTEENW-1:0] wren;

    wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];

    if (WRITE_ENABLE) begin
        if (`WORDS_PER_LINE > 1) begin
            reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r;
            reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r;
            if (NUM_PORTS > 1) begin
                always @(*) begin
                    wdata_r = 'x;
                    wren_r  = 0;
                    for (integer i = 0; i < NUM_PORTS; ++i) begin
                        if (pmask[i]) begin
                            wdata_r[wsel[i]] = write_data[i];
                            wren_r[wsel[i]] = byteen[i];
                        end
                    end
                end
            end else begin
                `UNUSED_VAR (pmask)
                always @(*) begin                
                    wdata_r = {`WORDS_PER_LINE{write_data}};
                    wren_r  = 0;
                    wren_r[wsel] = byteen;
                end
            end
            assign wdata = write ? wdata_r : fill_data;
            assign wren  = write ? wren_r : {BYTEENW{fill}};
        end else begin
            `UNUSED_VAR (wsel)
            `UNUSED_VAR (pmask)
            assign wdata = write ? write_data : fill_data;
            assign wren  = write ? byteen : {BYTEENW{fill}};
        end
    end else begin
        `UNUSED_VAR (write)
        `UNUSED_VAR (byteen)
        `UNUSED_VAR (pmask)
        `UNUSED_VAR (write_data)
        assign wdata = fill_data;
        assign wren  = fill;
    end

    VX_sp_ram #(
        .DATAW      (`CACHE_LINE_WIDTH),
        .SIZE       (`LINES_PER_BANK),
        .BYTEENW    (BYTEENW),
        .NO_RWCHECK (1)
    ) data_store (
        .clk   (clk),
        .addr  (line_addr),
        .wren  (wren),
        .wdata (wdata),
        .rdata (rdata)
    );

    if (`WORDS_PER_LINE > 1) begin
        for (genvar i = 0; i < NUM_PORTS; ++i) begin
            assign read_data[i] = rdata[wsel[i]];
        end
    end else begin
        assign read_data = rdata;
    end

    `UNUSED_VAR (stall)

`ifdef DBG_TRACE_CACHE_DATA
    always @(posedge clk) begin 
        if (fill && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);
        end
        if (read && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data);
        end 
        if (write && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byteen, line_addr, write_data);
        end      
    end    
`endif

endmodule
module VX_data_access #(
    parameter CACHE_ID          = 0,
    parameter BANK_ID           = 0,

    parameter CACHE_SIZE        = 1, 

    parameter CACHE_LINE_SIZE   = 1, 

    parameter NUM_BANKS         = 1, 

    parameter NUM_PORTS         = 1,

    parameter WORD_SIZE         = 1,

    parameter WRITE_ENABLE      = 1,

    parameter WORD_SELECT_BITS  = `UP(`WORD_SELECT_BITS)
) (
    input wire                          clk,
    input wire                          reset,

`ifdef DBG_CACHE_REQ_INFO
`IGNORE_UNUSED_BEGIN
    input wire[31:0]                    debug_pc,
    input wire[`NW_BITS-1:0]            debug_wid,
`IGNORE_UNUSED_END
`endif

    input wire                          stall,

    input wire                          read,
    input wire                          fill, 
    input wire                          write,
    input wire[`LINE_ADDR_WIDTH-1:0]    addr,
    input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel,
    input wire [NUM_PORTS-1:0]          pmask,
    input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen,
    input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,
    input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data,
    output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data
);

    `UNUSED_PARAM (CACHE_ID)
    `UNUSED_PARAM (BANK_ID)
    `UNUSED_PARAM (WORD_SIZE)
    `UNUSED_VAR (reset)
    `UNUSED_VAR (addr)
    `UNUSED_VAR (read)

    localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;

    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata;
    wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata;
    wire [BYTEENW-1:0] wren;

    wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];

    if (WRITE_ENABLE) begin
        if (`WORDS_PER_LINE > 1) begin
            reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r;
            reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r;
            if (NUM_PORTS > 1) begin
                always @(*) begin
                    wdata_r = 'x;
                    wren_r  = 0;
                    for (integer i = 0; i < NUM_PORTS; ++i) begin
                        if (pmask[i]) begin
                            wdata_r[wsel[i]] = write_data[i];
                            wren_r[wsel[i]] = byteen[i];
                        end
                    end
                end
            end else begin
                `UNUSED_VAR (pmask)
                always @(*) begin                
                    wdata_r = {`WORDS_PER_LINE{write_data}};
                    wren_r  = 0;
                    wren_r[wsel] = byteen;
                end
            end
            assign wdata = write ? wdata_r : fill_data;
            assign wren  = write ? wren_r : {BYTEENW{fill}};
        end else begin
            `UNUSED_VAR (wsel)
            `UNUSED_VAR (pmask)
            assign wdata = write ? write_data : fill_data;
            assign wren  = write ? byteen : {BYTEENW{fill}};
        end
    end else begin
        `UNUSED_VAR (write)
        `UNUSED_VAR (byteen)
        `UNUSED_VAR (pmask)
        `UNUSED_VAR (write_data)
        assign wdata = fill_data;
        assign wren  = fill;
    end

    VX_sp_ram #(
        .DATAW      (`CACHE_LINE_WIDTH),
        .SIZE       (`LINES_PER_BANK),
        .BYTEENW    (BYTEENW),
        .NO_RWCHECK (1)
    ) data_store (
        .clk   (clk),
        .addr  (line_addr),
        .wren  (wren),
        .wdata (wdata),
        .rdata (rdata)
    );

    if (`WORDS_PER_LINE > 1) begin
        for (genvar i = 0; i < NUM_PORTS; ++i) begin
            assign read_data[i] = rdata[wsel[i]];
        end
    end else begin
        assign read_data = rdata;
    end

    `UNUSED_VAR (stall)

`ifdef DBG_TRACE_CACHE_DATA
    always @(posedge clk) begin 
        if (fill && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);
        end
        if (read && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data);
        end 
        if (write && ~stall) begin
            dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byteen, line_addr, write_data);
        end      
    end    
`endif

endmodule