data/full_repos/permissive/444465810/func/axi/RF.v
data/verilator_xmls/3bbea9e6-9c9b-47fa-b0fe-b881d69c06d4.xml
module RF(
    input clk,
    input rst,
    input RFWr,
    input [4:0]A1,
    input [4:0]A2,
    input [4:0]A3,
    input [31:0]WD,
    output [31:0]RD1,
    output [31:0]RD2
);
integer i;
reg [31:0]RF[31:0];

assign RD1 = RF[A1];
assign RD2 = RF[A2];


always @(posedge clk) begin
    if(rst)
        for(i = 0;i < 32;i = i + 1)
            RF[i] = 32'h0;
    else if(RFWr)
        RF[A3] <= WD;
end
endmodule
module RF(
    input clk,
    input rst,
    input RFWr,
    input [4:0]A1,
    input [4:0]A2,
    input [4:0]A3,
    input [31:0]WD,
    output [31:0]RD1,
    output [31:0]RD2
);

integer i;
reg [31:0]RF[31:0];

assign RD1 = RF[A1];
assign RD2 = RF[A2];


always @(posedge clk) begin
    if(rst)
        for(i = 0;i < 32;i = i + 1)
            RF[i] = 32'h0;
    else if(RFWr)
        RF[A3] <= WD;
end
endmodule