data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v
1: b'%Error: data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v:34: Cannot find file containing module: \'Gowin_rPLL\'\n Gowin_rPLL chip_pll(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src,data/full_repos/permissive/489392257/Gowin_rPLL\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src,data/full_repos/permissive/489392257/Gowin_rPLL.v\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src,data/full_repos/permissive/489392257/Gowin_rPLL.sv\n             Gowin_rPLL\n             Gowin_rPLL.v\n             Gowin_rPLL.sv\n             obj_dir/Gowin_rPLL\n             obj_dir/Gowin_rPLL.v\n             obj_dir/Gowin_rPLL.sv\n%Error: data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v:41: Cannot find file containing module: \'vga\'\n vga vga_inst(\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v:63: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                    : ... In instance top\n   cnt_r <= 24\'d0;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v:67: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                    : ... In instance top\n   cnt_r <= 24\'d0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/489392257/1.9.8/tang-nano-9k/src/top.v:74: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'24\'h3d0900\' generates 24 bits.\n                                                                                    : ... In instance top\n  end else if (cnt_r == 24\'d400_0000) begin\n                     ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module top
(
	input           ARST_N,
	input           PSW,
	input           XTAL_IN,

	output          LCD_CLK,
	output          LCD_HSYNC,
	output          LCD_VSYNC,
	output          LCD_DEN,
	output  [4:0]   LCD_R,
	output  [5:0]   LCD_G,
	output  [4:0]   LCD_B,
	output  [5:0]   LED
);

	wire    CLK_SYS;
	wire    CLK_PIX;
	wire    oscout_o;





	Gowin_rPLL chip_pll(
		.clkout(CLK_SYS),
		.clkoutd(CLK_PIX),
		.clkin(XTAL_IN)
	);


	vga vga_inst(
		.CLK      (CLK_SYS),
		.ARST_N    (ARST_N),

		.PixelClk (CLK_PIX),
		.LCD_DE   (LCD_DEN),
		.LCD_HSYNC(LCD_HSYNC),
		.LCD_VSYNC(LCD_VSYNC),

		.LCD_B    (LCD_B),
		.LCD_G    (LCD_G),
		.LCD_R    (LCD_R)
	);
	assign LCD_CLK = CLK_PIX;


	reg     [31:0]  cnt_r;
	reg     [5:0]   led_r;
	assign LED = led_r;

	always @ (posedge XTAL_IN or negedge ARST_N) begin
		if (!ARST_N) begin
			cnt_r <= 24'd0;
		end else if (cnt_r < 24'd400_0000) begin
			cnt_r <= cnt_r + 1;
		end else begin
			cnt_r <= 24'd0;
		end
	end

	always @ (posedge XTAL_IN or negedge ARST_N) begin
		if (!ARST_N) begin
			led_r <= 6'b111110;
		end else if (cnt_r == 24'd400_0000) begin
			led_r[5:0] <= {led_r[4:0],led_r[5]};
		end else begin
			led_r <= led_r;
		end
	end
endmodule
module top
(
	input           ARST_N,
	input           PSW,
	input           XTAL_IN,

	output          LCD_CLK,
	output          LCD_HSYNC,
	output          LCD_VSYNC,
	output          LCD_DEN,
	output  [4:0]   LCD_R,
	output  [5:0]   LCD_G,
	output  [4:0]   LCD_B,
	output  [5:0]   LED
);


	wire    CLK_SYS;
	wire    CLK_PIX;
	wire    oscout_o;





	Gowin_rPLL chip_pll(
		.clkout(CLK_SYS),
		.clkoutd(CLK_PIX),
		.clkin(XTAL_IN)
	);


	vga vga_inst(
		.CLK      (CLK_SYS),
		.ARST_N    (ARST_N),

		.PixelClk (CLK_PIX),
		.LCD_DE   (LCD_DEN),
		.LCD_HSYNC(LCD_HSYNC),
		.LCD_VSYNC(LCD_VSYNC),

		.LCD_B    (LCD_B),
		.LCD_G    (LCD_G),
		.LCD_R    (LCD_R)
	);
	assign LCD_CLK = CLK_PIX;


	reg     [31:0]  cnt_r;
	reg     [5:0]   led_r;
	assign LED = led_r;

	always @ (posedge XTAL_IN or negedge ARST_N) begin
		if (!ARST_N) begin
			cnt_r <= 24'd0;
		end else if (cnt_r < 24'd400_0000) begin
			cnt_r <= cnt_r + 1;
		end else begin
			cnt_r <= 24'd0;
		end
	end

	always @ (posedge XTAL_IN or negedge ARST_N) begin
		if (!ARST_N) begin
			led_r <= 6'b111110;
		end else if (cnt_r == 24'd400_0000) begin
			led_r[5:0] <= {led_r[4:0],led_r[5]};
		end else begin
			led_r <= led_r;
		end
	end
endmodule