data/full_repos/permissive/480141277/clk_div.v
data/verilator_xmls/c24f680e-5b0b-4091-b7e5-f8d0f8cd0ac2.xml
module clk_div(
	input clk,
	input rst,
	output reg clk25
	);
	
	always @(posedge clk) begin
		if(rst)
			clk25 <= 0;
		else
			clk25 <= ~clk25;
	end
	
endmodule
module clk_div(
	input clk,
	input rst,
	output reg clk25
	);

	
	always @(posedge clk) begin
		if(rst)
			clk25 <= 0;
		else
			clk25 <= ~clk25;
	end
	
endmodule