data/full_repos/permissive/421450529/PC_jal.v
data/verilator_xmls/4dcb4e63-ddc2-4f5b-a175-8f286cdef3e5.xml
module PC_jal(
   input[31:0] Instr,
	input[31:0] PC4_D,
	output[31:0] pc_jal
    );
   assign pc_jal={PC4_D[31:28],Instr[25:0],2'b00};
endmodule
module PC_jal(
   input[31:0] Instr,
	input[31:0] PC4_D,
	output[31:0] pc_jal
    );

   assign pc_jal={PC4_D[31:28],Instr[25:0],2'b00};
endmodule