data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 0; B = 0; C0 = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 0; B = 1; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 0; B = 1; C0 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 0; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 0; C0 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 1; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = 1; B = 1; C0 = 1;\n        ^\n%Error: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:25: Unsupported or unknown PLI call: $monitor\n        $monitor ("time = ", $time, ", A = %b B = %b C0 = %b S = %b C = %b G = %b P = %b",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #10 {G_h, P_h, G_l, P_l} = i;\n            ^\n%Error: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:47: Unsupported or unknown PLI call: $monitor\n            $monitor ("time = ", $time, ", G_h = %b P_h = %b G_l = %b P_l = %b t_G_hl = %b t_P_hl = %b",\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000000; B[7:0] = 8\'b00000001; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000001; B[7:0] = 8\'b00000000; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000001; B[7:0] = 8\'b00000001; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000000; B[7:0] = 8\'b00000010; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000010; B[7:0] = 8\'b00000010; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00010000; B[7:0] = 8\'b00000000; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b00000100; B[7:0] = 8\'b00011111; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #20 A[7:0] = 8\'b11111111; B[7:0] = 8\'b11111111; C0 = 0;\n        ^\n%Error: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:96: Unsupported or unknown PLI call: $monitor\n        $monitor ("time = ", $time, ", x = %b y = %b S = %b C = %b P = %b G = %b",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n            #10 A = i; B = 65555; C0 = 1\'b0;\n            ^\n%Error: data/full_repos/permissive/458208177/test/32_bit_add_cla_tree_tb.v:118: Unsupported or unknown PLI call: $monitor\n            $monitor ("time = ", $time, ", A = %b B = %b S = %b C = %b",\n            ^~~~~~~~\n%Error: Exiting due to 4 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_full_adder_gp;
    wire t_S, t_C, t_G, t_P;

    reg A, B, C0;





    full_adder_gp M1(t_S, t_C, t_G, t_P, A, B, C0);

    initial begin
            A = 0; B = 0; C0 = 0;
        #10 A = 0; B = 0; C0 = 1;
        #10 A = 0; B = 1; C0 = 0;
        #10 A = 0; B = 1; C0 = 1;
        #10 A = 1; B = 0; C0 = 0;
        #10 A = 1; B = 0; C0 = 1;
        #10 A = 1; B = 1; C0 = 0;
        #10 A = 1; B = 1; C0 = 1;
   end

    initial begin
        $monitor ("time = ", $time, ", A = %b B = %b C0 = %b S = %b C = %b G = %b P = %b",
            A, B, C0, t_S, t_C, t_G, t_P);
    end
endmodule
module t_full_adder_gp;

    wire t_S, t_C, t_G, t_P;

    reg A, B, C0;





    full_adder_gp M1(t_S, t_C, t_G, t_P, A, B, C0);

    initial begin
            A = 0; B = 0; C0 = 0;
        #10 A = 0; B = 0; C0 = 1;
        #10 A = 0; B = 1; C0 = 0;
        #10 A = 0; B = 1; C0 = 1;
        #10 A = 1; B = 0; C0 = 0;
        #10 A = 1; B = 0; C0 = 1;
        #10 A = 1; B = 1; C0 = 0;
        #10 A = 1; B = 1; C0 = 1;
   end

    initial begin
        $monitor ("time = ", $time, ", A = %b B = %b C0 = %b S = %b C = %b G = %b P = %b",
            A, B, C0, t_S, t_C, t_G, t_P);
    end
endmodule