data/full_repos/permissive/489994352/Image-Part/conv2d3x3.v
data/verilator_xmls/7adf0c8b-6fd7-492d-a20f-541e4cdeb65f.xml
module conv2d3x3#(parameter datwidth=16,input_channel=3,output_filter=1,inputsize=224, outputsize=222,pad=0, stride=2, start_channel=0, output_size=111, inpfile="inpf.txt",weightfile="conv1wf1.txt",outputfile="opf.txt")
                (clk,rst, currentRdChBuffer,imgdata1, imgdata2, imgdata3, imgdata4, imgdata5, imgdata6, imgdata7, imgdata8, imgdata9, output_im,bias, i_data_valid,o_convolved_data_valid);
input clk, rst, i_data_valid;
input [2*datwidth-1:0] bias;
output [datwidth-1:0] output_im;
reg [datwidth-1:0] kernel [9*input_channel-1:0];
input [datwidth-1:0] imgdata1, imgdata2, imgdata3, imgdata4, imgdata5, imgdata6, imgdata7, imgdata8, imgdata9;
input [1:0] currentRdChBuffer;
output o_convolved_data_valid;
initial
begin

    $readmemh(weightfile,kernel);

end







reg multDataValid;
reg [2*datwidth-1:0] multData[8:0];
wire [2*datwidth-1:0] multDataw[8:0];

wire [2*datwidth-1:0] kaddr;
assign kaddr = currentRdChBuffer*9;

mul_signed mul1 (kernel[kaddr+0],imgdata1,multDataw[0]);
mul_signed mul2 (kernel[kaddr+1],imgdata2,multDataw[1]);
mul_signed mul3 (kernel[kaddr+2],imgdata3,multDataw[2]);

mul_signed mul4 (kernel[kaddr+3],imgdata4,multDataw[3]);
mul_signed mul5 (kernel[kaddr+4],imgdata5,multDataw[4]);
mul_signed mul6 (kernel[kaddr+5],imgdata6,multDataw[5]);

mul_signed mul7 (kernel[kaddr+6],imgdata7,multDataw[6]);
mul_signed mul8 (kernel[kaddr+7],imgdata8,multDataw[7]);
mul_signed mul9 (kernel[kaddr+8],imgdata9,multDataw[8]);

always @(posedge clk)
begin


    multData[0] <= multDataw[0];
    multData[1] <= multDataw[1];
    multData[2] <= multDataw[2];

    multData[3] <= multDataw[3];
    multData[4] <= multDataw[4];
    multData[5] <= multDataw[5];

    multData[6] <= multDataw[6];
    multData[7] <= multDataw[7];
    multData[8] <= multDataw[8];

    multDataValid <= i_data_valid;
end


reg [2*datwidth-1:0] sum1,sum2,sum3;
reg [2*datwidth-1:0] totalsum;
reg [2*datwidth-1:0] channelsum;
reg [datwidth-1:0] sumData;
reg sumDataValid;
always @(*)
begin

    sum1 = multData[0] + multData[1] + multData[2];
    sum2 = multData[3] + multData[4] + multData[5];
    sum3 = multData[6] + multData[7] + multData[8];
    totalsum = sum1 + sum2 + sum3;
end

always @(posedge clk)
begin
    if (rst)
        channelsum <= 0;
    else begin
        if (multDataValid && currentRdChBuffer==2'b01)
            channelsum <= bias+totalsum;
        else if(multDataValid)
            channelsum <= channelsum + totalsum;
    end
end

always @(posedge clk)
begin
    sumData <= {channelsum[23:16],channelsum[15:8]};
    sumDataValid <= multDataValid;
end

reg validch;
always @(posedge clk)
begin
    validch <= (currentRdChBuffer==2'b10);
end
reg validchd;
always @(posedge clk)
begin
    validchd <= validch;
end
reg validchd2;
always @(posedge clk)
begin
    validchd2 <= validchd;
end

reg [datwidth-1:0] o_convolved_data;
reg o_convolved_data_valid;
always @(posedge clk)
begin

    o_convolved_data <= sumData;

    if (validchd2)
        o_convolved_data_valid <= sumDataValid;
    else
        o_convolved_data_valid <= 1'b0;
end
assign output_im = o_convolved_data_valid? o_convolved_data : 16'd0;

endmodule
module conv2d3x3#(parameter datwidth=16,input_channel=3,output_filter=1,inputsize=224, outputsize=222,pad=0, stride=2, start_channel=0, output_size=111, inpfile="inpf.txt",weightfile="conv1wf1.txt",outputfile="opf.txt")
                (clk,rst, currentRdChBuffer,imgdata1, imgdata2, imgdata3, imgdata4, imgdata5, imgdata6, imgdata7, imgdata8, imgdata9, output_im,bias, i_data_valid,o_convolved_data_valid);

input clk, rst, i_data_valid;
input [2*datwidth-1:0] bias;
output [datwidth-1:0] output_im;
reg [datwidth-1:0] kernel [9*input_channel-1:0];
input [datwidth-1:0] imgdata1, imgdata2, imgdata3, imgdata4, imgdata5, imgdata6, imgdata7, imgdata8, imgdata9;
input [1:0] currentRdChBuffer;
output o_convolved_data_valid;
initial
begin

    $readmemh(weightfile,kernel);

end







reg multDataValid;
reg [2*datwidth-1:0] multData[8:0];
wire [2*datwidth-1:0] multDataw[8:0];

wire [2*datwidth-1:0] kaddr;
assign kaddr = currentRdChBuffer*9;

mul_signed mul1 (kernel[kaddr+0],imgdata1,multDataw[0]);
mul_signed mul2 (kernel[kaddr+1],imgdata2,multDataw[1]);
mul_signed mul3 (kernel[kaddr+2],imgdata3,multDataw[2]);

mul_signed mul4 (kernel[kaddr+3],imgdata4,multDataw[3]);
mul_signed mul5 (kernel[kaddr+4],imgdata5,multDataw[4]);
mul_signed mul6 (kernel[kaddr+5],imgdata6,multDataw[5]);

mul_signed mul7 (kernel[kaddr+6],imgdata7,multDataw[6]);
mul_signed mul8 (kernel[kaddr+7],imgdata8,multDataw[7]);
mul_signed mul9 (kernel[kaddr+8],imgdata9,multDataw[8]);

always @(posedge clk)
begin


    multData[0] <= multDataw[0];
    multData[1] <= multDataw[1];
    multData[2] <= multDataw[2];

    multData[3] <= multDataw[3];
    multData[4] <= multDataw[4];
    multData[5] <= multDataw[5];

    multData[6] <= multDataw[6];
    multData[7] <= multDataw[7];
    multData[8] <= multDataw[8];

    multDataValid <= i_data_valid;
end


reg [2*datwidth-1:0] sum1,sum2,sum3;
reg [2*datwidth-1:0] totalsum;
reg [2*datwidth-1:0] channelsum;
reg [datwidth-1:0] sumData;
reg sumDataValid;
always @(*)
begin

    sum1 = multData[0] + multData[1] + multData[2];
    sum2 = multData[3] + multData[4] + multData[5];
    sum3 = multData[6] + multData[7] + multData[8];
    totalsum = sum1 + sum2 + sum3;
end

always @(posedge clk)
begin
    if (rst)
        channelsum <= 0;
    else begin
        if (multDataValid && currentRdChBuffer==2'b01)
            channelsum <= bias+totalsum;
        else if(multDataValid)
            channelsum <= channelsum + totalsum;
    end
end

always @(posedge clk)
begin
    sumData <= {channelsum[23:16],channelsum[15:8]};
    sumDataValid <= multDataValid;
end

reg validch;
always @(posedge clk)
begin
    validch <= (currentRdChBuffer==2'b10);
end
reg validchd;
always @(posedge clk)
begin
    validchd <= validch;
end
reg validchd2;
always @(posedge clk)
begin
    validchd2 <= validchd;
end

reg [datwidth-1:0] o_convolved_data;
reg o_convolved_data_valid;
always @(posedge clk)
begin

    o_convolved_data <= sumData;

    if (validchd2)
        o_convolved_data_valid <= sumDataValid;
    else
        o_convolved_data_valid <= 1'b0;
end
assign output_im = o_convolved_data_valid? o_convolved_data : 16'd0;

endmodule