data/full_repos/permissive/514835397/tb/tx_baud_gen_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/tx_baud_gen_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\nforever #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/tx_baud_gen_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/tx_baud_gen_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/514835397/tb/tx_baud_gen_TB.v:7: Cannot find file containing module: \'tx_baud_gen\'\ntx_baud_gen dut\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/tx_baud_gen\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/tx_baud_gen.v\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/tx_baud_gen.sv\n             tx_baud_gen\n             tx_baud_gen.v\n             tx_baud_gen.sv\n             obj_dir/tx_baud_gen\n             obj_dir/tx_baud_gen.v\n             obj_dir/tx_baud_gen.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tx_baud_gen_TB();

reg sclock, sreset_n;
reg [1:0] sbaudrate_select;
wire stx_baud;

tx_baud_gen dut
(
	.clock(sclock),
	.reset_n(sreset_n),
	.baudrate_select(sbaudrate_select),
	.tx_baud(stx_baud)
);

initial begin
	sclock = 0;
forever #2
	sclock = ~sclock;
end

initial begin
	sreset_n = 0;
	sbaudrate_select = 1;
#3
	sreset_n = 1;
#100
	$stop;
end

endmodule
module tx_baud_gen_TB();


reg sclock, sreset_n;
reg [1:0] sbaudrate_select;
wire stx_baud;

tx_baud_gen dut
(
	.clock(sclock),
	.reset_n(sreset_n),
	.baudrate_select(sbaudrate_select),
	.tx_baud(stx_baud)
);

initial begin
	sclock = 0;
forever #2
	sclock = ~sclock;
end

initial begin
	sreset_n = 0;
	sbaudrate_select = 1;
#3
	sreset_n = 1;
#100
	$stop;
end

endmodule