data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/RCAdder16B.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/RCAdder16B.v:31: Cannot find file containing module: 'FullAdder'\n  FullAdder fa0 (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/FullAdder\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/FullAdder.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/FullAdder.sv\n             FullAdder\n             FullAdder.v\n             FullAdder.sv\n             obj_dir/FullAdder\n             obj_dir/FullAdder.v\n             obj_dir/FullAdder.sv\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/RCAdder16B.v:42: Cannot find file containing module: 'FullAdder'\n    FullAdder FullAdder_inst(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/RCAdder16B.v:52: Cannot find file containing module: 'FullAdder'\n  FullAdder faF (\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module RCAdder16B(
    input [15:0] aIn,
    input [15:0] bIn,
    input cIn,
    output [15:0] dOut,
    output cOut
  );
  
  wire [15:0] carry;
  FullAdder fa0 (
    .aIn(aIn[0]),
    .bIn(bIn[0]),
    .cIn(cIn),
    .sum(dOut[0]),
    .cOut(carry[0])
  );
  
  genvar i;
  generate
  for(i = 1; i < 15; i = i + 1) begin : fa_gen
    FullAdder FullAdder_inst(
      .aIn(aIn[i]),
      .bIn(bIn[i]),
      .cIn(carry[i - 1]),
      .sum(dOut[i]),
      .cOut(carry[i])
    );
  end
  endgenerate
  
  FullAdder faF (
    .aIn(aIn[15]),
    .bIn(bIn[15]),
    .cIn(carry[14]),
    .sum(dOut[15]),
    .cOut(cOut)
  );
  
endmodule
module RCAdder16B(
    input [15:0] aIn,
    input [15:0] bIn,
    input cIn,
    output [15:0] dOut,
    output cOut
  );

  
  wire [15:0] carry;
  FullAdder fa0 (
    .aIn(aIn[0]),
    .bIn(bIn[0]),
    .cIn(cIn),
    .sum(dOut[0]),
    .cOut(carry[0])
  );
  
  genvar i;
  generate
  for(i = 1; i < 15; i = i + 1) begin : fa_gen
    FullAdder FullAdder_inst(
      .aIn(aIn[i]),
      .bIn(bIn[i]),
      .cIn(carry[i - 1]),
      .sum(dOut[i]),
      .cOut(carry[i])
    );
  end
  endgenerate
  
  FullAdder faF (
    .aIn(aIn[15]),
    .bIn(bIn[15]),
    .cIn(carry[14]),
    .sum(dOut[15]),
    .cOut(cOut)
  );
  
endmodule