data/full_repos/permissive/423852699/tb/soc_IO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("result.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(5);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #6\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423852699/tb/soc_IO_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #50000\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module soc_tb();
    reg clk;
    reg reset;
    reg[7:0] opr1;
    reg[7:0] opr2;

    wire[15:0] result;

    integer load_branch_conflict_cnt;

    SoC soc(
        .base_clk(clk),
        .reset(reset),
        .opr1(opr1),
        .opr2(opr2),
        .result(result)
    );

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        $dumpfile("result.vcd");
        $dumpvars(5);

        reset = 0;
        opr1 = 3;
        opr2 = 15;

        load_branch_conflict_cnt = 0;

        #6
        reset = 1;

        #10
        if (soc.core0.load_branch_conflict) begin
            load_branch_conflict_cnt = load_branch_conflict_cnt + 1;
        end

        #50000
        $finish;
    end
    
endmodule
module soc_tb();

    reg clk;
    reg reset;
    reg[7:0] opr1;
    reg[7:0] opr2;

    wire[15:0] result;

    integer load_branch_conflict_cnt;

    SoC soc(
        .base_clk(clk),
        .reset(reset),
        .opr1(opr1),
        .opr2(opr2),
        .result(result)
    );

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        $dumpfile("result.vcd");
        $dumpvars(5);

        reset = 0;
        opr1 = 3;
        opr2 = 15;

        load_branch_conflict_cnt = 0;

        #6
        reset = 1;

        #10
        if (soc.core0.load_branch_conflict) begin
            load_branch_conflict_cnt = load_branch_conflict_cnt + 1;
        end

        #50000
        $finish;
    end
    
endmodule