data/full_repos/permissive/494148647/src/util/counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/494148647/src/util/counter.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance counter\n            count_q <= #1 1\'b0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter #(
    parameter COUNT_BITS = 8,
    parameter HIDDEN_BITS = 0
    ) (
    input clk,
    input rst,
    output [COUNT_BITS-1:0] count
    );

    reg [COUNT_BITS+HIDDEN_BITS-1:0] count_d, count_q;

    assign count = count_q[COUNT_BITS+HIDDEN_BITS-1:HIDDEN_BITS];

    always @(count_q)
        count_d = count_q + 1'b1;

    always @(posedge clk)
        if (rst)
            count_q <= #1 1'b0;
        else
            count_q <= #1 count_d;

endmodule
module counter #(
    parameter COUNT_BITS = 8,
    parameter HIDDEN_BITS = 0
    ) (
    input clk,
    input rst,
    output [COUNT_BITS-1:0] count
    );


    reg [COUNT_BITS+HIDDEN_BITS-1:0] count_d, count_q;

    assign count = count_q[COUNT_BITS+HIDDEN_BITS-1:HIDDEN_BITS];

    always @(count_q)
        count_d = count_q + 1'b1;

    always @(posedge clk)
        if (rst)
            count_q <= #1 1'b0;
        else
            count_q <= #1 count_d;

endmodule