data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation/Pred_Calc_Addr_Gen.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation/Pred_Calc_Addr_Gen.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Pred_Calc_Addr_Gen(
	Bank_Sel_Flag_I,
	Block_Counter_I,
	Row_Counter_I,
	Column_Counter_I,
	
	Write_Address_O,
	Retrieve_Address_O,
	Y_nCbCr_O
);

input 				Bank_Sel_Flag_I;
input 	[3:0]		Block_Counter_I;
input 	[3:0]		Row_Counter_I;
input		[1:0]		Column_Counter_I;
	
output reg [9:0]	Write_Address_O;
output 	[8:0]		Retrieve_Address_O;
output 				Y_nCbCr_O;

wire 		[1:0]		cc;
wire 		[3:0]		CbCr_row;

assign CbCr_row = Row_Counter_I;

assign cc = 
	(Block_Counter_I[3:2] == 2'h0) ? 2'h0 : 
	(Block_Counter_I[0]) ? 2'h2 : 2'h1;

assign Retrieve_Address_O = Y_nCbCr_O ? 
	{2'b00, Row_Counter_I[2:0], Block_Counter_I[0], Column_Counter_I} +
		{Row_Counter_I[3],6'h00} + {Block_Counter_I[1],6'h00} : 
	Column_Counter_I + (144 * cc) + 
		4 * CbCr_row;


always @(
	cc, Bank_Sel_Flag_I, Block_Counter_I, 
	Row_Counter_I, Column_Counter_I, CbCr_row
) begin
	Write_Address_O = 10'h000;
	case (cc)
		2'h0 : Write_Address_O = {
			Bank_Sel_Flag_I, 2'h0,
			Block_Counter_I[1:0], 
			Row_Counter_I[2:0],
			Column_Counter_I };  
		2'h1 : Write_Address_O = {
			Bank_Sel_Flag_I, 4'h4, 
			CbCr_row[2:0],	Column_Counter_I};
		2'h2 : Write_Address_O = {
			Bank_Sel_Flag_I, 4'h5, 
			CbCr_row[2:0],	Column_Counter_I};
	endcase				
end

assign Y_nCbCr_O = (cc == 2'h0);

endmodule
module Pred_Calc_Addr_Gen(
	Bank_Sel_Flag_I,
	Block_Counter_I,
	Row_Counter_I,
	Column_Counter_I,
	
	Write_Address_O,
	Retrieve_Address_O,
	Y_nCbCr_O
);


input 				Bank_Sel_Flag_I;
input 	[3:0]		Block_Counter_I;
input 	[3:0]		Row_Counter_I;
input		[1:0]		Column_Counter_I;
	
output reg [9:0]	Write_Address_O;
output 	[8:0]		Retrieve_Address_O;
output 				Y_nCbCr_O;

wire 		[1:0]		cc;
wire 		[3:0]		CbCr_row;

assign CbCr_row = Row_Counter_I;

assign cc = 
	(Block_Counter_I[3:2] == 2'h0) ? 2'h0 : 
	(Block_Counter_I[0]) ? 2'h2 : 2'h1;

assign Retrieve_Address_O = Y_nCbCr_O ? 
	{2'b00, Row_Counter_I[2:0], Block_Counter_I[0], Column_Counter_I} +
		{Row_Counter_I[3],6'h00} + {Block_Counter_I[1],6'h00} : 
	Column_Counter_I + (144 * cc) + 
		4 * CbCr_row;


always @(
	cc, Bank_Sel_Flag_I, Block_Counter_I, 
	Row_Counter_I, Column_Counter_I, CbCr_row
) begin
	Write_Address_O = 10'h000;
	case (cc)
		2'h0 : Write_Address_O = {
			Bank_Sel_Flag_I, 2'h0,
			Block_Counter_I[1:0], 
			Row_Counter_I[2:0],
			Column_Counter_I };  
		2'h1 : Write_Address_O = {
			Bank_Sel_Flag_I, 4'h4, 
			CbCr_row[2:0],	Column_Counter_I};
		2'h2 : Write_Address_O = {
			Bank_Sel_Flag_I, 4'h5, 
			CbCr_row[2:0],	Column_Counter_I};
	endcase				
end

assign Y_nCbCr_O = (cc == 2'h0);

endmodule