data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #100 pin_btn_c = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #100 pin_btn_c = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5  pin_clk = ! pin_clk ;\n    ^\n%Error: data/full_repos/permissive/431487364/sim/buceros_soc_top_tb.v:13: Cannot find file containing module: \'buceros_soc_top\'\n  buceros_soc_top \n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/buceros_soc_top\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/buceros_soc_top.v\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/buceros_soc_top.sv\n             buceros_soc_top\n             buceros_soc_top.v\n             buceros_soc_top.sv\n             obj_dir/buceros_soc_top\n             obj_dir/buceros_soc_top.v\n             obj_dir/buceros_soc_top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buceros_soc_top_tb;




  reg  pin_clk = 0;
  reg  pin_btn_c = 0;
  reg [15:0] pin_sw;
  wire [15:0] pin_led;
  wire [ 7:0] pin_seg;
  wire [ 3:0] pin_seg_sel;

  buceros_soc_top 
  buceros_soc_top_dut (
    .pin_clk (pin_clk ),
    .pin_btn_c (pin_btn_c ),
    .pin_sw (pin_sw ),
    .pin_led (pin_led ),
    .pin_seg (pin_seg ),
    .pin_seg_sel  ( pin_seg_sel)
  );

  initial begin
    begin
      pin_sw = 0;
      pin_btn_c = 0;
      #100 pin_btn_c = 1;
      #100 pin_btn_c = 0;
      #10000;
    $finish;
    end
  end

  always
    #5  pin_clk = ! pin_clk ;

endmodule
module buceros_soc_top_tb;





  reg  pin_clk = 0;
  reg  pin_btn_c = 0;
  reg [15:0] pin_sw;
  wire [15:0] pin_led;
  wire [ 7:0] pin_seg;
  wire [ 3:0] pin_seg_sel;

  buceros_soc_top 
  buceros_soc_top_dut (
    .pin_clk (pin_clk ),
    .pin_btn_c (pin_btn_c ),
    .pin_sw (pin_sw ),
    .pin_led (pin_led ),
    .pin_seg (pin_seg ),
    .pin_seg_sel  ( pin_seg_sel)
  );

  initial begin
    begin
      pin_sw = 0;
      pin_btn_c = 0;
      #100 pin_btn_c = 1;
      #100 pin_btn_c = 0;
      #10000;
    $finish;
    end
  end

  always
    #5  pin_clk = ! pin_clk ;

endmodule