data/full_repos/permissive/500947188/rtl/clocks/A6001_1.v
data/verilator_xmls/5a16eeab-a964-43c9-9969-36b72e6bd393.xml
module A6001_1 (
    Reset_n,
    clk,

    Cen,
    F15_BE_Qn,
    C3A_Q,
    F15_AE_Qn,
    C3A_Qn,
    A15_QA,
    A15_QB,
    A15_QC,
    PLOAD_RSHIFTn,
    VDG,
    RL_Sel,
    VLK,
    AB_Sel,
    V_C,
    G15_CE
);
    input wire Reset_n;
    input wire clk;
    input wire Cen;
    input wire F15_BE_Qn;
    input wire C3A_Q;
    input wire F15_AE_Qn;
    input wire C3A_Qn;
    input wire A15_QA;
    input wire A15_QB;
    input wire A15_QC;
    output wire PLOAD_RSHIFTn;
    output wire VDG;
    output wire RL_Sel;
    output wire VLK;
    output wire AB_Sel;
    output wire V_C;
    output wire G15_CE;

    reg rVDG, rRL_Sel, rVLK, rAB_Sel, rV_C;
    wire rVDGn, rRL_Seln, rVLKn, rAB_Seln, rV_Cn;
    wire rVDGneg, rRL_Selneg, rVLKneg, rAB_Selneg, rV_Cneg;
    wire VDGterm, RL_Selterm, VLKterm, AB_SELterm, V_Cterm;
    wire A15_QCn, A15_QBn;
    wire F15_AE_Q;
	
    assign  A15_QCn = ~A15_QC;
    assign  A15_QBn = ~A15_QB;
    assign  F15_AE_Q = ~F15_AE_Qn;

    assign  PLOAD_RSHIFTn = ~((                                       A15_QCn & rV_Cn) |
                              (F15_BE_Qn &      F15_AE_Qn &           C3A_Q          ) |
                              (F15_BE_Qn &      F15_AE_Qn &           A15_QCn        ) |
                              (F15_BE_Qn &      F15_AE_Qn & C3A_Q   & rV_Cn          ));


    assign  VDGterm = A15_QBn & rV_Cn;
    
    reg last_cen;
    always @(posedge clk) begin
        if (!Reset_n) begin
            rVDG     <= 1'b0;
            rRL_Sel  <= 1'b0;
            rVLK     <= 1'b0;
            rAB_Sel  <= 1'b0;
            rV_C     <= 1'b0;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;
            if(Cen && !last_cen)  begin
                rVDG    <= VDGterm;
                rRL_Sel <= RL_Selterm;
                rVLK    <= VLKterm;
                rAB_Sel <= AB_SELterm;
                rV_C    <= V_Cterm;
            end
        end
    end

    assign  rVDGn = ~rVDG;
    assign  rVDGneg = ~rVDGn;
    assign  VDG = ~rVDG;


    assign  RL_Selterm = A15_QA & A15_QBn & rV_Cn;

    assign  rRL_Seln = ~rRL_Sel;
    assign  rRL_Selneg = ~rRL_Seln;
    assign  RL_Sel = ~rRL_Sel;


    assign  VLKterm = C3A_Qn & A15_QA & A15_QBn & rV_Cneg;

    assign  rVLKn = ~rVLK;
    assign  rVLKneg = ~rVLKn;
    assign  VLK = ~rVLK;

    assign  AB_SELterm = F15_AE_Q;
    
    assign  rAB_Seln = ~rAB_Sel;
    assign  rAB_Selneg = ~rAB_Seln;
    assign  AB_Sel = ~rAB_Sel;


    assign  V_Cterm = F15_BE_Qn & F15_AE_Qn;

    assign  rV_Cn = ~rV_C;
    assign  rV_Cneg = ~rV_Cn;
    assign  V_C = ~rV_C;


    assign  G15_CE = ~(rV_Cneg | A15_QB);

endmodule
module A6001_1 (
    Reset_n,
    clk,

    Cen,
    F15_BE_Qn,
    C3A_Q,
    F15_AE_Qn,
    C3A_Qn,
    A15_QA,
    A15_QB,
    A15_QC,
    PLOAD_RSHIFTn,
    VDG,
    RL_Sel,
    VLK,
    AB_Sel,
    V_C,
    G15_CE
);

    input wire Reset_n;
    input wire clk;
    input wire Cen;
    input wire F15_BE_Qn;
    input wire C3A_Q;
    input wire F15_AE_Qn;
    input wire C3A_Qn;
    input wire A15_QA;
    input wire A15_QB;
    input wire A15_QC;
    output wire PLOAD_RSHIFTn;
    output wire VDG;
    output wire RL_Sel;
    output wire VLK;
    output wire AB_Sel;
    output wire V_C;
    output wire G15_CE;

    reg rVDG, rRL_Sel, rVLK, rAB_Sel, rV_C;
    wire rVDGn, rRL_Seln, rVLKn, rAB_Seln, rV_Cn;
    wire rVDGneg, rRL_Selneg, rVLKneg, rAB_Selneg, rV_Cneg;
    wire VDGterm, RL_Selterm, VLKterm, AB_SELterm, V_Cterm;
    wire A15_QCn, A15_QBn;
    wire F15_AE_Q;
	
    assign  A15_QCn = ~A15_QC;
    assign  A15_QBn = ~A15_QB;
    assign  F15_AE_Q = ~F15_AE_Qn;

    assign  PLOAD_RSHIFTn = ~((                                       A15_QCn & rV_Cn) |
                              (F15_BE_Qn &      F15_AE_Qn &           C3A_Q          ) |
                              (F15_BE_Qn &      F15_AE_Qn &           A15_QCn        ) |
                              (F15_BE_Qn &      F15_AE_Qn & C3A_Q   & rV_Cn          ));


    assign  VDGterm = A15_QBn & rV_Cn;
    
    reg last_cen;
    always @(posedge clk) begin
        if (!Reset_n) begin
            rVDG     <= 1'b0;
            rRL_Sel  <= 1'b0;
            rVLK     <= 1'b0;
            rAB_Sel  <= 1'b0;
            rV_C     <= 1'b0;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;
            if(Cen && !last_cen)  begin
                rVDG    <= VDGterm;
                rRL_Sel <= RL_Selterm;
                rVLK    <= VLKterm;
                rAB_Sel <= AB_SELterm;
                rV_C    <= V_Cterm;
            end
        end
    end

    assign  rVDGn = ~rVDG;
    assign  rVDGneg = ~rVDGn;
    assign  VDG = ~rVDG;


    assign  RL_Selterm = A15_QA & A15_QBn & rV_Cn;

    assign  rRL_Seln = ~rRL_Sel;
    assign  rRL_Selneg = ~rRL_Seln;
    assign  RL_Sel = ~rRL_Sel;


    assign  VLKterm = C3A_Qn & A15_QA & A15_QBn & rV_Cneg;

    assign  rVLKn = ~rVLK;
    assign  rVLKneg = ~rVLKn;
    assign  VLK = ~rVLK;

    assign  AB_SELterm = F15_AE_Q;
    
    assign  rAB_Seln = ~rAB_Sel;
    assign  rAB_Selneg = ~rAB_Seln;
    assign  AB_Sel = ~rAB_Sel;


    assign  V_Cterm = F15_BE_Qn & F15_AE_Qn;

    assign  rV_Cn = ~rV_C;
    assign  rV_Cneg = ~rV_Cn;
    assign  V_C = ~rV_C;


    assign  G15_CE = ~(rV_Cneg | A15_QB);

endmodule