data/full_repos/permissive/525452387/testbench/regs_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #3 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/regs_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n    always #1 begin\n           ^\n%Error: data/full_repos/permissive/525452387/testbench/regs_tb.v:105: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("regs.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/regs_tb.v:106: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, regs_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regs_test_bench;
    reg regs_1_clk;
    reg regs_1_rst_;
    reg regs_1_we_i;

    reg[4:0]  regs_1_waddr_i;
    reg[31:0] regs_1_wdata_i;
    reg[4:0] regs_1_raddr1_i;
    reg[4:0] regs_1_raddr2_i;

    wire[31:0] regs_1_rdata1_o;
    wire[31:0] regs_1_rdata2_o;

    regs regs_1 (
        .clk  (regs_1_clk),
        .rst_ (regs_1_rst_),
        .we_i(regs_1_we_i),
        .waddr_i(regs_1_waddr_i),
        .wdata_i(regs_1_wdata_i),
        .raddr1_i(regs_1_raddr1_i),
        .raddr2_i(regs_1_raddr2_i),
        .rdata1_o(regs_1_rdata1_o),
        .rdata2_o(regs_1_rdata2_o)
    );

    initial begin
        #0 begin
            regs_1_clk <= 1'b1;
            regs_1_rst_ <= 0;
        end


        #1 begin
            regs_1_rst_ <= 1;
        end


        #1 begin
            regs_1_waddr_i <= 5'h1;
            regs_1_wdata_i <= 32'h42;
            regs_1_we_i <= 1'b1;
            regs_1_raddr1_i <= 5'h1;
        end


        #1 begin
            if (regs_1_rdata1_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            regs_1_we_i <= 1'b0;
        end


        #1 begin
            regs_1_raddr1_i <= 5'h1;
            regs_1_raddr2_i <= 5'h0;
        end


        #1 begin
            if (regs_1_rdata1_o == 32'h42 && regs_1_rdata2_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            regs_1_waddr_i <= 5'h1f;
            regs_1_wdata_i <= 32'hDEADBEEF;
            regs_1_we_i <= 1'b1;
        end


        #1 begin
            regs_1_raddr1_i <= 5'h1f;
            regs_1_we_i <= 1'b0;
        end


        #3 begin
            regs_1_raddr1_i <= 5'h1f;
            if (regs_1_rdata1_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        regs_1_clk <= ~regs_1_clk;
    end

    initial begin
        $dumpfile("regs.vcd");
        $dumpvars(0, regs_1);
    end

endmodule
module regs_test_bench;

    reg regs_1_clk;
    reg regs_1_rst_;
    reg regs_1_we_i;

    reg[4:0]  regs_1_waddr_i;
    reg[31:0] regs_1_wdata_i;
    reg[4:0] regs_1_raddr1_i;
    reg[4:0] regs_1_raddr2_i;

    wire[31:0] regs_1_rdata1_o;
    wire[31:0] regs_1_rdata2_o;

    regs regs_1 (
        .clk  (regs_1_clk),
        .rst_ (regs_1_rst_),
        .we_i(regs_1_we_i),
        .waddr_i(regs_1_waddr_i),
        .wdata_i(regs_1_wdata_i),
        .raddr1_i(regs_1_raddr1_i),
        .raddr2_i(regs_1_raddr2_i),
        .rdata1_o(regs_1_rdata1_o),
        .rdata2_o(regs_1_rdata2_o)
    );

    initial begin
        #0 begin
            regs_1_clk <= 1'b1;
            regs_1_rst_ <= 0;
        end


        #1 begin
            regs_1_rst_ <= 1;
        end


        #1 begin
            regs_1_waddr_i <= 5'h1;
            regs_1_wdata_i <= 32'h42;
            regs_1_we_i <= 1'b1;
            regs_1_raddr1_i <= 5'h1;
        end


        #1 begin
            if (regs_1_rdata1_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            regs_1_we_i <= 1'b0;
        end


        #1 begin
            regs_1_raddr1_i <= 5'h1;
            regs_1_raddr2_i <= 5'h0;
        end


        #1 begin
            if (regs_1_rdata1_o == 32'h42 && regs_1_rdata2_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end


        #1 begin
            regs_1_waddr_i <= 5'h1f;
            regs_1_wdata_i <= 32'hDEADBEEF;
            regs_1_we_i <= 1'b1;
        end


        #1 begin
            regs_1_raddr1_i <= 5'h1f;
            regs_1_we_i <= 1'b0;
        end


        #3 begin
            regs_1_raddr1_i <= 5'h1f;
            if (regs_1_rdata1_o == 32'hDEADBEEF) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        regs_1_clk <= ~regs_1_clk;
    end

    initial begin
        $dumpfile("regs.vcd");
        $dumpvars(0, regs_1);
    end

endmodule