data/full_repos/permissive/484316383/rtl/common/cache_controller.v
1: b'%Error: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:138: Cannot find file containing module: \'bram\'\n bram cache_mem\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/bram\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/bram.v\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/bram.sv\n             bram\n             bram.v\n             bram.sv\n             obj_dir/bram\n             obj_dir/bram.v\n             obj_dir/bram.sv\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:181: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache0[3:1] <= fit[0] ? 3\'b111 : cache0[3:1] - (cache0[3:1] > csblk); \n                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:182: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache1[3:1] <= fit[1] ? 3\'b111 : cache1[3:1] - (cache1[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:183: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache2[3:1] <= fit[2] ? 3\'b111 : cache2[3:1] - (cache2[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:184: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache3[3:1] <= fit[3] ? 3\'b111 : cache3[3:1] - (cache3[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:185: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache4[3:1] <= fit[4] ? 3\'b111 : cache4[3:1] - (cache4[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:186: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache5[3:1] <= fit[5] ? 3\'b111 : cache5[3:1] - (cache5[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:187: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache6[3:1] <= fit[6] ? 3\'b111 : cache6[3:1] - (cache6[3:1] > csblk); \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/cache_controller.v:188: Operator SUB expects 3 bits on the RHS, but RHS\'s GT generates 1 bits.\n                                                                                      : ... In instance cache_controller\n      cache7[3:1] <= fit[7] ? 3\'b111 : cache7[3:1] - (cache7[3:1] > csblk); \n                                                   ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module cache_controller(
	 input [20:0] addr,
     output [31:0] dout,
	 input [31:0]din,
	 input clk,	
	 input mreq,
	 input [3:0]wmask,
	 output ce,
	 input [15:0]ddr_din,
	 output reg[15:0]ddr_dout,
	 input ddr_clk,
	 input cache_write_data,
	 input cache_read_data,
	 output reg ddr_rd = 0,
	 output reg ddr_wr = 0,
	 output reg [12:0] waddr,
	 input flush
    );
	
	wire [7:0]fit;
	wire [7:0]free;
	wire wr = |wmask;
	reg [16:0]cache0 = 17'h00000;
	reg [16:0]cache1 = 17'h00012;
	reg [16:0]cache2 = 17'h00024;
	reg [16:0]cache3 = 17'h00036;
	reg [16:0]cache4 = 17'h0ffc8;
	reg [16:0]cache5 = 17'h0ffda;
	reg [16:0]cache6 = 17'h0ffec;
	reg [16:0]cache7 = 17'h0fffe;
	
	reg dirty;	
	reg [2:0]STATE = 0;
	reg [6:0]lowaddr = 0;
	reg s_lowaddr5 = 0;
	wire [31:0]cache_QA;

	assign fit[0] = cache0[16:4] == addr[20:8];
	assign fit[1] = cache1[16:4] == addr[20:8];
	assign fit[2] = cache2[16:4] == addr[20:8];
	assign fit[3] = cache3[16:4] == addr[20:8];
	assign fit[4] = cache4[16:4] == addr[20:8];
	assign fit[5] = cache5[16:4] == addr[20:8];
	assign fit[6] = cache6[16:4] == addr[20:8];
	assign fit[7] = cache7[16:4] == addr[20:8];
	
	assign free[0] = cache0[3:1] == 3'b000;
    assign free[1] = cache1[3:1] == 3'b000;
    assign free[2] = cache2[3:1] == 3'b000;
    assign free[3] = cache3[3:1] == 3'b000;
    assign free[4] = cache4[3:1] == 3'b000;
    assign free[5] = cache5[3:1] == 3'b000;
    assign free[6] = cache6[3:1] == 3'b000;
    assign free[7] = cache7[3:1] == 3'b000;

	wire hit = |fit;
	wire st0 = STATE == 0;
	assign ce = st0 && (~mreq || hit);

	wire [2:0]blk =  {fit[4] | fit[5] | fit[6] | fit[7], fit[2] | fit[3] | fit[6] | fit[7], fit[1] | fit[3] | fit[5] | fit[7]};
	wire [2:0]fblk = {free[4] | free[5] | free[6] | free[7], free[2] | free[3] | free[6] | free[7], free[1] | free[3] | free[5] | free[7]};
	wire [2:0]csblk = ({3{fit[0]}} & cache0[3:1]) | ({3{fit[1]}} & cache1[3:1]) |
							({3{fit[2]}} & cache2[3:1]) | ({3{fit[3]}} & cache3[3:1]) |
							({3{fit[4]}} & cache4[3:1]) | ({3{fit[5]}} & cache5[3:1]) |
							({3{fit[6]}} & cache6[3:1]) | ({3{fit[7]}} & cache7[3:1]);
	
	always @(posedge ddr_clk) begin
		if(cache_write_data || cache_read_data) lowaddr <= lowaddr + 1;
		ddr_dout <= lowaddr[0] ? cache_QA[15:0] : cache_QA[31:16];
	end
	

	
	bram cache_mem
	(

    .clock_a(ddr_clk), 				
    .wren_a({4{cache_write_data}} & {lowaddr[0], lowaddr[0], ~lowaddr[0], ~lowaddr[0]}),
    .address_a({blk, lowaddr[6:1]}), 		
    .data_a({ddr_din, ddr_din}),
    .q_a(cache_QA), 				
     

    .clock_b(clk), 				
    .wren_b({4{mreq & hit & st0 & wr}} & wmask),
    .address_b({blk, addr[7:2]}), 	
    .data_b(din),
    .q_b(dout), 				

    .byteena_a(cache_write_data | cache_read_data), 			
    .byteena_b(mreq & hit & st0)

	);
	
	always @(cache0, cache1, cache2, cache3, cache4, cache5, cache6, cache7) begin
		dirty = 1'bx;
		case(1)
			free[0]: begin dirty = cache0[0]; end		
			free[1]: begin dirty = cache1[0]; end
			free[2]: begin dirty = cache2[0]; end
			free[3]: begin dirty = cache3[0]; end
			free[4]: begin dirty = cache4[0]; end
			free[5]: begin dirty = cache5[0]; end
			free[6]: begin dirty = cache6[0]; end
			free[7]: begin dirty = cache7[0]; end
		endcase
	end
	

	always @(posedge clk) begin
		s_lowaddr5 <= lowaddr[6];
		
		case(STATE)
			3'b000: begin
				if(mreq) begin
					if(hit) begin
						cache0[3:1] <= fit[0] ? 3'b111 : cache0[3:1] - (cache0[3:1] > csblk); 
						cache1[3:1] <= fit[1] ? 3'b111 : cache1[3:1] - (cache1[3:1] > csblk); 
						cache2[3:1] <= fit[2] ? 3'b111 : cache2[3:1] - (cache2[3:1] > csblk); 
						cache3[3:1] <= fit[3] ? 3'b111 : cache3[3:1] - (cache3[3:1] > csblk); 
						cache4[3:1] <= fit[4] ? 3'b111 : cache4[3:1] - (cache4[3:1] > csblk); 
						cache5[3:1] <= fit[5] ? 3'b111 : cache5[3:1] - (cache5[3:1] > csblk); 
						cache6[3:1] <= fit[6] ? 3'b111 : cache6[3:1] - (cache6[3:1] > csblk); 
						cache7[3:1] <= fit[7] ? 3'b111 : cache7[3:1] - (cache7[3:1] > csblk); 
					end else begin
						case(fblk)
							0:	begin waddr <= cache0[16:4]; cache0[16:4] <= addr[20:8]; end
							1:	begin waddr <= cache1[16:4]; cache1[16:4] <= addr[20:8]; end
							2:	begin waddr <= cache2[16:4]; cache2[16:4] <= addr[20:8]; end
							3:	begin waddr <= cache3[16:4]; cache3[16:4] <= addr[20:8]; end
							4:	begin waddr <= cache4[16:4]; cache4[16:4] <= addr[20:8]; end
							5:	begin waddr <= cache5[16:4]; cache5[16:4] <= addr[20:8]; end
							6:	begin waddr <= cache6[16:4]; cache6[16:4] <= addr[20:8]; end
							7:	begin waddr <= cache7[16:4]; cache7[16:4] <= addr[20:8]; end
						endcase
						ddr_rd <= ~dirty;
						ddr_wr <= dirty;
						STATE <= dirty ? 3'b011 : 3'b100;
					end
					if(hit) case(1)
						fit[0]: cache0[0] <= (cache0[0] | wr);
						fit[1]: cache1[0] <= (cache1[0] | wr);
						fit[2]: cache2[0] <= (cache2[0] | wr);
						fit[3]: cache3[0] <= (cache3[0] | wr);
						fit[4]: cache4[0] <= (cache4[0] | wr);
						fit[5]: cache5[0] <= (cache5[0] | wr);
						fit[6]: cache6[0] <= (cache6[0] | wr);
						fit[7]: cache7[0] <= (cache7[0] | wr);
					endcase else case(1)
						free[0]: cache0[0] <= 0;
						free[1]: cache1[0] <= 0;
						free[2]: cache2[0] <= 0;
						free[3]: cache3[0] <= 0;
						free[4]: cache4[0] <= 0;
						free[5]: cache5[0] <= 0;
						free[6]: cache6[0] <= 0;
						free[7]: cache7[0] <= 0;
					endcase				
				end
			end
			3'b011: begin
				ddr_rd <= 1'b1;
				if(s_lowaddr5) begin
					ddr_wr <= 1'b0;
					STATE <= 3'b111;
				end
			end
			3'b111: begin
				if(~s_lowaddr5) STATE <= 3'b100;
			end
			3'b100: begin	
				if(s_lowaddr5) STATE <= 3'b101;
			end
			3'b101: begin
				ddr_rd <= 1'b0;
				if(~s_lowaddr5) STATE <= 3'b000;
			end
		endcase
	end
	
endmodule
module cache_controller(
	 input [20:0] addr,
     output [31:0] dout,
	 input [31:0]din,
	 input clk,	
	 input mreq,
	 input [3:0]wmask,
	 output ce,
	 input [15:0]ddr_din,
	 output reg[15:0]ddr_dout,
	 input ddr_clk,
	 input cache_write_data,
	 input cache_read_data,
	 output reg ddr_rd = 0,
	 output reg ddr_wr = 0,
	 output reg [12:0] waddr,
	 input flush
    );

	
	wire [7:0]fit;
	wire [7:0]free;
	wire wr = |wmask;
	reg [16:0]cache0 = 17'h00000;
	reg [16:0]cache1 = 17'h00012;
	reg [16:0]cache2 = 17'h00024;
	reg [16:0]cache3 = 17'h00036;
	reg [16:0]cache4 = 17'h0ffc8;
	reg [16:0]cache5 = 17'h0ffda;
	reg [16:0]cache6 = 17'h0ffec;
	reg [16:0]cache7 = 17'h0fffe;
	
	reg dirty;	
	reg [2:0]STATE = 0;
	reg [6:0]lowaddr = 0;
	reg s_lowaddr5 = 0;
	wire [31:0]cache_QA;

	assign fit[0] = cache0[16:4] == addr[20:8];
	assign fit[1] = cache1[16:4] == addr[20:8];
	assign fit[2] = cache2[16:4] == addr[20:8];
	assign fit[3] = cache3[16:4] == addr[20:8];
	assign fit[4] = cache4[16:4] == addr[20:8];
	assign fit[5] = cache5[16:4] == addr[20:8];
	assign fit[6] = cache6[16:4] == addr[20:8];
	assign fit[7] = cache7[16:4] == addr[20:8];
	
	assign free[0] = cache0[3:1] == 3'b000;
    assign free[1] = cache1[3:1] == 3'b000;
    assign free[2] = cache2[3:1] == 3'b000;
    assign free[3] = cache3[3:1] == 3'b000;
    assign free[4] = cache4[3:1] == 3'b000;
    assign free[5] = cache5[3:1] == 3'b000;
    assign free[6] = cache6[3:1] == 3'b000;
    assign free[7] = cache7[3:1] == 3'b000;

	wire hit = |fit;
	wire st0 = STATE == 0;
	assign ce = st0 && (~mreq || hit);

	wire [2:0]blk =  {fit[4] | fit[5] | fit[6] | fit[7], fit[2] | fit[3] | fit[6] | fit[7], fit[1] | fit[3] | fit[5] | fit[7]};
	wire [2:0]fblk = {free[4] | free[5] | free[6] | free[7], free[2] | free[3] | free[6] | free[7], free[1] | free[3] | free[5] | free[7]};
	wire [2:0]csblk = ({3{fit[0]}} & cache0[3:1]) | ({3{fit[1]}} & cache1[3:1]) |
							({3{fit[2]}} & cache2[3:1]) | ({3{fit[3]}} & cache3[3:1]) |
							({3{fit[4]}} & cache4[3:1]) | ({3{fit[5]}} & cache5[3:1]) |
							({3{fit[6]}} & cache6[3:1]) | ({3{fit[7]}} & cache7[3:1]);
	
	always @(posedge ddr_clk) begin
		if(cache_write_data || cache_read_data) lowaddr <= lowaddr + 1;
		ddr_dout <= lowaddr[0] ? cache_QA[15:0] : cache_QA[31:16];
	end
	

	
	bram cache_mem
	(

    .clock_a(ddr_clk), 				
    .wren_a({4{cache_write_data}} & {lowaddr[0], lowaddr[0], ~lowaddr[0], ~lowaddr[0]}),
    .address_a({blk, lowaddr[6:1]}), 		
    .data_a({ddr_din, ddr_din}),
    .q_a(cache_QA), 				
     

    .clock_b(clk), 				
    .wren_b({4{mreq & hit & st0 & wr}} & wmask),
    .address_b({blk, addr[7:2]}), 	
    .data_b(din),
    .q_b(dout), 				

    .byteena_a(cache_write_data | cache_read_data), 			
    .byteena_b(mreq & hit & st0)

	);
	
	always @(cache0, cache1, cache2, cache3, cache4, cache5, cache6, cache7) begin
		dirty = 1'bx;
		case(1)
			free[0]: begin dirty = cache0[0]; end		
			free[1]: begin dirty = cache1[0]; end
			free[2]: begin dirty = cache2[0]; end
			free[3]: begin dirty = cache3[0]; end
			free[4]: begin dirty = cache4[0]; end
			free[5]: begin dirty = cache5[0]; end
			free[6]: begin dirty = cache6[0]; end
			free[7]: begin dirty = cache7[0]; end
		endcase
	end
	

	always @(posedge clk) begin
		s_lowaddr5 <= lowaddr[6];
		
		case(STATE)
			3'b000: begin
				if(mreq) begin
					if(hit) begin
						cache0[3:1] <= fit[0] ? 3'b111 : cache0[3:1] - (cache0[3:1] > csblk); 
						cache1[3:1] <= fit[1] ? 3'b111 : cache1[3:1] - (cache1[3:1] > csblk); 
						cache2[3:1] <= fit[2] ? 3'b111 : cache2[3:1] - (cache2[3:1] > csblk); 
						cache3[3:1] <= fit[3] ? 3'b111 : cache3[3:1] - (cache3[3:1] > csblk); 
						cache4[3:1] <= fit[4] ? 3'b111 : cache4[3:1] - (cache4[3:1] > csblk); 
						cache5[3:1] <= fit[5] ? 3'b111 : cache5[3:1] - (cache5[3:1] > csblk); 
						cache6[3:1] <= fit[6] ? 3'b111 : cache6[3:1] - (cache6[3:1] > csblk); 
						cache7[3:1] <= fit[7] ? 3'b111 : cache7[3:1] - (cache7[3:1] > csblk); 
					end else begin
						case(fblk)
							0:	begin waddr <= cache0[16:4]; cache0[16:4] <= addr[20:8]; end
							1:	begin waddr <= cache1[16:4]; cache1[16:4] <= addr[20:8]; end
							2:	begin waddr <= cache2[16:4]; cache2[16:4] <= addr[20:8]; end
							3:	begin waddr <= cache3[16:4]; cache3[16:4] <= addr[20:8]; end
							4:	begin waddr <= cache4[16:4]; cache4[16:4] <= addr[20:8]; end
							5:	begin waddr <= cache5[16:4]; cache5[16:4] <= addr[20:8]; end
							6:	begin waddr <= cache6[16:4]; cache6[16:4] <= addr[20:8]; end
							7:	begin waddr <= cache7[16:4]; cache7[16:4] <= addr[20:8]; end
						endcase
						ddr_rd <= ~dirty;
						ddr_wr <= dirty;
						STATE <= dirty ? 3'b011 : 3'b100;
					end
					if(hit) case(1)
						fit[0]: cache0[0] <= (cache0[0] | wr);
						fit[1]: cache1[0] <= (cache1[0] | wr);
						fit[2]: cache2[0] <= (cache2[0] | wr);
						fit[3]: cache3[0] <= (cache3[0] | wr);
						fit[4]: cache4[0] <= (cache4[0] | wr);
						fit[5]: cache5[0] <= (cache5[0] | wr);
						fit[6]: cache6[0] <= (cache6[0] | wr);
						fit[7]: cache7[0] <= (cache7[0] | wr);
					endcase else case(1)
						free[0]: cache0[0] <= 0;
						free[1]: cache1[0] <= 0;
						free[2]: cache2[0] <= 0;
						free[3]: cache3[0] <= 0;
						free[4]: cache4[0] <= 0;
						free[5]: cache5[0] <= 0;
						free[6]: cache6[0] <= 0;
						free[7]: cache7[0] <= 0;
					endcase				
				end
			end
			3'b011: begin
				ddr_rd <= 1'b1;
				if(s_lowaddr5) begin
					ddr_wr <= 1'b0;
					STATE <= 3'b111;
				end
			end
			3'b111: begin
				if(~s_lowaddr5) STATE <= 3'b100;
			end
			3'b100: begin	
				if(s_lowaddr5) STATE <= 3'b101;
			end
			3'b101: begin
				ddr_rd <= 1'b0;
				if(~s_lowaddr5) STATE <= 3'b000;
			end
		endcase
	end
	
endmodule