data/full_repos/permissive/437204475/pipeline_bp/hazard.v
1: b'%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:4: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:16: Define or directive not defined: \'`FALSE\'\n            pc_flush <= `FALSE;\n                        ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            pc_flush <= `FALSE;\n                              ^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:17: Define or directive not defined: \'`FALSE\'\n            pc_stall <= `FALSE;\n                        ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            pc_stall <= `FALSE;\n                              ^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:18: Define or directive not defined: \'`FALSE\'\n            id_stall <= `FALSE;\n                        ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            id_stall <= `FALSE;\n                              ^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:19: Define or directive not defined: \'`FALSE\'\n            id_ex_bubble <= `FALSE;\n                            ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            id_ex_bubble <= `FALSE;\n                                  ^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:32: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_pc, exmem_pc,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_targ_else_offset, exmem_targ_else_offset,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_pc_addr_src_reg,     \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_rs_val,       \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_imm,          \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire exmem_pc_addr_src_reg,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] exmem_rs_val,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:45: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] exmem_imm,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] flush_addr\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:48: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:51: syntax error, unexpected always\n    always @(*) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:64: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:68: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire exmem_branch_take,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:70: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_jump,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:73: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire predict_j_taken,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:74: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] predict_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:77: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_pc, exmem_pc,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:78: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_targ_else_offset, exmem_targ_else_offset,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:79: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire idex_pc_addr_src_reg,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:80: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_rs_val,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:81: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] idex_imm,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:82: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire exmem_pc_addr_src_reg,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:83: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] exmem_rs_val,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:84: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] exmem_imm,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:87: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg j_ctrl_hazard,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:89: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg branch_ctrl_hazard,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:91: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire[W-1:0] flush_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:92: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg upd,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:93: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg add_else_minus,           \n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:94: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[W-1:0] upd_src_pc         \n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/hazard.v:95: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: Exiting due to 43 error(s)\n'
module ctrl_hazard_detect #(
    parameter W = `WORD_WIDTH
) (

    input wire exmem_can_branch,
    input wire exmem_branch_take,

    input wire idex_jump,


    input wire predict_j_taken,
    input wire[W-1:0] predict_addr,


    input wire[W-1:0] idex_pc, exmem_pc,
    input wire idex_targ_else_offset, exmem_targ_else_offset,
    input wire idex_pc_addr_src_reg,
    input wire[W-1:0] idex_rs_val,
    input wire[W-1:0] idex_imm,
    input wire exmem_pc_addr_src_reg,
    input wire[W-1:0] exmem_rs_val,
    input wire[W-1:0] exmem_imm,


    output reg j_ctrl_hazard,

    output reg branch_ctrl_hazard,

    output wire[W-1:0] flush_addr,
    output reg upd,
    output reg add_else_minus,
    output reg[W-1:0] upd_src_pc
);

    actual_addr_gen addr_gen_inst(
        .idex_jump(idex_jump), .exmem_can_branch(exmem_can_branch),

        .idex_pc(idex_pc), .exmem_pc(exmem_pc),
        .idex_targ_else_offset(idex_targ_else_offset), .exmem_targ_else_offset(exmem_targ_else_offset),
        .idex_pc_addr_src_reg(idex_pc_addr_src_reg),
        .idex_rs_val(idex_rs_val), .idex_imm(idex_imm),
        .exmem_pc_addr_src_reg(exmem_pc_addr_src_reg),
        .exmem_rs_val(exmem_rs_val), .exmem_imm(exmem_imm),

        .flush_addr(flush_addr)
    );

    always @(*) begin
        j_ctrl_hazard = (idex_jump != predict_j_taken);
        branch_ctrl_hazard = (exmem_can_branch && 
            (exmem_branch_take != predict_j_taken || flush_addr != predict_addr)
        );
        upd = (exmem_can_branch || idex_jump);
        add_else_minus = (exmem_can_branch ? exmem_branch_take : 1);
        upd_src_pc = (exmem_can_branch ? exmem_pc : idex_pc);
    end
endmodule
module ctrl_hazard_detect #(
    parameter W = `WORD_WIDTH
) (

    input wire exmem_can_branch,
    input wire exmem_branch_take,

    input wire idex_jump,


    input wire predict_j_taken,
    input wire[W-1:0] predict_addr,


    input wire[W-1:0] idex_pc, exmem_pc,
    input wire idex_targ_else_offset, exmem_targ_else_offset,
    input wire idex_pc_addr_src_reg,
    input wire[W-1:0] idex_rs_val,
    input wire[W-1:0] idex_imm,
    input wire exmem_pc_addr_src_reg,
    input wire[W-1:0] exmem_rs_val,
    input wire[W-1:0] exmem_imm,


    output reg j_ctrl_hazard,

    output reg branch_ctrl_hazard,

    output wire[W-1:0] flush_addr,
    output reg upd,
    output reg add_else_minus,
    output reg[W-1:0] upd_src_pc
);


    actual_addr_gen addr_gen_inst(
        .idex_jump(idex_jump), .exmem_can_branch(exmem_can_branch),

        .idex_pc(idex_pc), .exmem_pc(exmem_pc),
        .idex_targ_else_offset(idex_targ_else_offset), .exmem_targ_else_offset(exmem_targ_else_offset),
        .idex_pc_addr_src_reg(idex_pc_addr_src_reg),
        .idex_rs_val(idex_rs_val), .idex_imm(idex_imm),
        .exmem_pc_addr_src_reg(exmem_pc_addr_src_reg),
        .exmem_rs_val(exmem_rs_val), .exmem_imm(exmem_imm),

        .flush_addr(flush_addr)
    );

    always @(*) begin
        j_ctrl_hazard = (idex_jump != predict_j_taken);
        branch_ctrl_hazard = (exmem_can_branch && 
            (exmem_branch_take != predict_j_taken || flush_addr != predict_addr)
        );
        upd = (exmem_can_branch || idex_jump);
        add_else_minus = (exmem_can_branch ? exmem_branch_take : 1);
        upd_src_pc = (exmem_can_branch ? exmem_pc : idex_pc);
    end
endmodule