data/full_repos/permissive/460183508/rtl/loadable_upcounter.v
data/verilator_xmls/464fb0ee-8a24-4d5d-ac02-7148d2eba758.xml
module loadable_upcounter
#(parameter WIDTH=8,
            INCREMENT=1
)
(
    input wire reset,
    input wire clk,
    input wire load,
    input wire [WIDTH-1:0] value,
    output reg [WIDTH-1:0] count
);
    always @(posedge reset, posedge clk) begin
        if (reset) begin

            count <= {WIDTH{1'b0}};
        end
        else begin
            if (load) begin

                count <= value;
            end
            else begin

                count <= count + INCREMENT;
            end
        end
    end
endmodule
module loadable_upcounter
#(parameter WIDTH=8,
            INCREMENT=1
)
(
    input wire reset,
    input wire clk,
    input wire load,
    input wire [WIDTH-1:0] value,
    output reg [WIDTH-1:0] count
);

    always @(posedge reset, posedge clk) begin
        if (reset) begin

            count <= {WIDTH{1'b0}};
        end
        else begin
            if (load) begin

                count <= value;
            end
            else begin

                count <= count + INCREMENT;
            end
        end
    end
endmodule