data/full_repos/permissive/50700015/spl2_write_through/cci_std_afu.sv
1: b"%Error: data/full_repos/permissive/50700015/spl2_write_through/cci_std_afu.sv:91: Cannot find file containing module: 'spl_cci_top'\n    spl_cci_top spl_cci_top(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50700015/spl2_write_through,data/full_repos/permissive/50700015/spl_cci_top\n             data/full_repos/permissive/50700015/spl2_write_through,data/full_repos/permissive/50700015/spl_cci_top.v\n             data/full_repos/permissive/50700015/spl2_write_through,data/full_repos/permissive/50700015/spl_cci_top.sv\n             spl_cci_top\n             spl_cci_top.v\n             spl_cci_top.sv\n             obj_dir/spl_cci_top\n             obj_dir/spl_cci_top.v\n             obj_dir/spl_cci_top.sv\n%Error: data/full_repos/permissive/50700015/spl2_write_through/cci_std_afu.sv:152: Cannot find file containing module: 'cci_ext_afu'\n    cci_ext_afu cci_ext_afu(\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cci_std_afu(

  inputlogic             vl_clk_LPdomain_32ui,
  inputlogic             vl_clk_LPdomain_16ui,
  inputlogic             ffs_vl_LP32ui_lp2sy_SystemReset_n,
  inputlogic             ffs_vl_LP32ui_lp2sy_SoftReset_n,



  inputlogic      [17:0] ffs_vl18_LP32ui_lp2sy_C0RxHdr,
  inputlogic     [511:0] ffs_vl512_LP32ui_lp2sy_C0RxData,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxWrValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxRdValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxCgValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxUgValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxIrValid,

  inputlogic      [17:0] ffs_vl18_LP32ui_lp2sy_C1RxHdr,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1RxWrValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1RxIrValid,


  outputlogic      [60:0] ffs_vl61_LP32ui_sy2lp_C0TxHdr,
  outputlogic             ffs_vl_LP32ui_sy2lp_C0TxRdValid,

  outputlogic      [60:0] ffs_vl61_LP32ui_sy2lp_C1TxHdr,
  outputlogic     [511:0] ffs_vl512_LP32ui_sy2lp_C1TxData,
  outputlogic             ffs_vl_LP32ui_sy2lp_C1TxWrValid,
  outputlogic             ffs_vl_LP32ui_sy2lp_C1TxIrValid,

  inputlogic             ffs_vl_LP32ui_lp2sy_C0TxAlmFull,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1TxAlmFull,

  inputlogic             ffs_vl_LP32ui_lp2sy_InitDnForSys
);




    wire                    spl_tx_rd_almostfull;
    wire                    afu_tx_rd_valid;
    wire                    spl_ctx_base;
    wire [98:0]             afu_tx_rd_hdr;
    wire                    spl_tx_wr_almostfull;
    wire                    afu_tx_wr_valid;
    wire                    afu_tx_intr_valid;
    wire [98:0]             afu_tx_wr_hdr;
    wire [511:0]            afu_tx_data;    
    wire                    spl_rx_rd_valid;
    wire                    spl_rx_wr_valid0;
    wire                    spl_rx_cfg_valid;
    wire                    spl_rx_intr_valid0;
    wire                    spl_rx_umsg_valid;
    wire [17:0]             spl_rx_hdr0;
    wire [511:0]            spl_rx_data;
    wire                    spl_rx_wr_valid1;
    wire                    spl_rx_intr_valid1;
    wire [17:0]             spl_rx_hdr1;
    wire                    spl_enable;
    wire                    spl_reset;
    
    
    spl_cci_top spl_cci_top(
        .clk                        (vl_clk_LPdomain_32ui),
        .reset_n                    (ffs_vl_LP32ui_lp2sy_SystemReset_n),
        .linkup                     (ffs_vl_LP32ui_lp2sy_InitDnForSys),
        .spl_enable                 (spl_enable),
        .spl_reset                  (spl_reset),
    

        .spl_tx_rd_almostfull       (spl_tx_rd_almostfull),
        .afu_tx_rd_valid            (afu_tx_rd_valid),
        .afu_tx_rd_hdr              (afu_tx_rd_hdr),
    

        .spl_tx_wr_almostfull       (spl_tx_wr_almostfull),
        .afu_tx_wr_valid            (afu_tx_wr_valid),
        .afu_tx_intr_valid          (afu_tx_intr_valid),
        .afu_tx_wr_hdr              (afu_tx_wr_hdr),    
        .afu_tx_data                (afu_tx_data),
    

        .spl_rx_rd_valid            (spl_rx_rd_valid),
        .spl_rx_wr_valid0           (spl_rx_wr_valid0),
        .spl_rx_cfg_valid           (spl_rx_cfg_valid),
        .spl_rx_intr_valid0         (spl_rx_intr_valid0),
        .spl_rx_umsg_valid          (spl_rx_umsg_valid),
        .spl_rx_hdr0                (spl_rx_hdr0),
        .spl_rx_data                (spl_rx_data),
    

        .spl_rx_wr_valid1           (spl_rx_wr_valid1),
        .spl_rx_intr_valid1         (spl_rx_intr_valid1),
        .spl_rx_hdr1                (spl_rx_hdr1),
    

        .cci_tx_rd_almostfull       (ffs_vl_LP32ui_lp2sy_C0TxAlmFull),
        .spl_tx_rd_valid            (ffs_vl_LP32ui_sy2lp_C0TxRdValid),
        .spl_tx_rd_hdr              (ffs_vl61_LP32ui_sy2lp_C0TxHdr),
    

        .cci_tx_wr_almostfull       (ffs_vl_LP32ui_lp2sy_C1TxAlmFull),
        .spl_tx_wr_valid            (ffs_vl_LP32ui_sy2lp_C1TxWrValid),
        .spl_tx_intr_valid          (ffs_vl_LP32ui_sy2lp_C1TxIrValid),
        .spl_tx_wr_hdr              (ffs_vl61_LP32ui_sy2lp_C1TxHdr),    
        .spl_tx_data                (ffs_vl512_LP32ui_sy2lp_C1TxData),
    

        .cci_rx_rd_valid            (ffs_vl_LP32ui_lp2sy_C0RxRdValid),
        .cci_rx_wr_valid0           (ffs_vl_LP32ui_lp2sy_C0RxWrValid),
        .cci_rx_cfg_valid           (ffs_vl_LP32ui_lp2sy_C0RxCgValid),
        .cci_rx_intr_valid0         (ffs_vl_LP32ui_lp2sy_C0RxIrValid),
        .cci_rx_umsg_valid          (ffs_vl_LP32ui_lp2sy_C0RxUgValid),
        .cci_rx_hdr0                (ffs_vl18_LP32ui_lp2sy_C0RxHdr),
        .cci_rx_data                (ffs_vl512_LP32ui_lp2sy_C0RxData),
    

        .cci_rx_wr_valid1           (ffs_vl_LP32ui_lp2sy_C1RxWrValid),
        .cci_rx_intr_valid1         (ffs_vl_LP32ui_lp2sy_C1RxIrValid),
        .cci_rx_hdr1                (ffs_vl18_LP32ui_lp2sy_C1RxHdr)
    );


    cci_ext_afu cci_ext_afu(
      .vl_clk_LPdomain_32ui             (vl_clk_LPdomain_32ui),
      .vl_clk_LPdomain_16ui             (vl_clk_LPdomain_16ui),
      .ffs_vl_LP32ui_lp2sy_SystemReset_n(ffs_vl_LP32ui_lp2sy_SystemReset_n),
      .ffs_vl_LP32ui_lp2sy_SoftReset_n  (~spl_reset),

      .ffs_vl24_LP32ui_lp2sy_C0RxHdr    (spl_rx_hdr0),
      .ffs_vl512_LP32ui_lp2sy_C0RxData  (spl_rx_data),
      .ffs_vl_LP32ui_lp2sy_C0RxWrValid  (spl_rx_wr_valid0),
      .ffs_vl_LP32ui_lp2sy_C0RxRdValid  (spl_rx_rd_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxCgValid  (spl_rx_cfg_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxUgValid  (spl_rx_umsg_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxIrValid  (spl_rx_intr_valid0),

      .ffs_vl24_LP32ui_lp2sy_C1RxHdr    (spl_rx_hdr1),
      .ffs_vl_LP32ui_lp2sy_C1RxWrValid  (spl_rx_wr_valid1),
      .ffs_vl_LP32ui_lp2sy_C1RxIrValid  (spl_rx_intr_valid1),

      .ffs_vl99_LP32ui_sy2lp_C0TxHdr    (afu_tx_rd_hdr),
      .ffs_vl_LP32ui_sy2lp_C0TxRdValid  (afu_tx_rd_valid),

      .ffs_vl99_LP32ui_sy2lp_C1TxHdr    (afu_tx_wr_hdr),
      .ffs_vl512_LP32ui_sy2lp_C1TxData  (afu_tx_data),
      .ffs_vl_LP32ui_sy2lp_C1TxWrValid  (afu_tx_wr_valid),
      .ffs_vl_LP32ui_sy2lp_C1TxIrValid  (afu_tx_intr_valid),

      .ffs_vl_LP32ui_lp2sy_C0TxAlmFull  (spl_tx_rd_almostfull),
      .ffs_vl_LP32ui_lp2sy_C1TxAlmFull  (spl_tx_wr_almostfull),

      .ffs_vl_LP32ui_lp2sy_InitDnForSys (spl_enable)
    );

endmodule
module cci_std_afu(

  inputlogic             vl_clk_LPdomain_32ui,
  inputlogic             vl_clk_LPdomain_16ui,
  inputlogic             ffs_vl_LP32ui_lp2sy_SystemReset_n,
  inputlogic             ffs_vl_LP32ui_lp2sy_SoftReset_n,



  inputlogic      [17:0] ffs_vl18_LP32ui_lp2sy_C0RxHdr,
  inputlogic     [511:0] ffs_vl512_LP32ui_lp2sy_C0RxData,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxWrValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxRdValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxCgValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxUgValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C0RxIrValid,

  inputlogic      [17:0] ffs_vl18_LP32ui_lp2sy_C1RxHdr,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1RxWrValid,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1RxIrValid,


  outputlogic      [60:0] ffs_vl61_LP32ui_sy2lp_C0TxHdr,
  outputlogic             ffs_vl_LP32ui_sy2lp_C0TxRdValid,

  outputlogic      [60:0] ffs_vl61_LP32ui_sy2lp_C1TxHdr,
  outputlogic     [511:0] ffs_vl512_LP32ui_sy2lp_C1TxData,
  outputlogic             ffs_vl_LP32ui_sy2lp_C1TxWrValid,
  outputlogic             ffs_vl_LP32ui_sy2lp_C1TxIrValid,

  inputlogic             ffs_vl_LP32ui_lp2sy_C0TxAlmFull,
  inputlogic             ffs_vl_LP32ui_lp2sy_C1TxAlmFull,

  inputlogic             ffs_vl_LP32ui_lp2sy_InitDnForSys
);





    wire                    spl_tx_rd_almostfull;
    wire                    afu_tx_rd_valid;
    wire                    spl_ctx_base;
    wire [98:0]             afu_tx_rd_hdr;
    wire                    spl_tx_wr_almostfull;
    wire                    afu_tx_wr_valid;
    wire                    afu_tx_intr_valid;
    wire [98:0]             afu_tx_wr_hdr;
    wire [511:0]            afu_tx_data;    
    wire                    spl_rx_rd_valid;
    wire                    spl_rx_wr_valid0;
    wire                    spl_rx_cfg_valid;
    wire                    spl_rx_intr_valid0;
    wire                    spl_rx_umsg_valid;
    wire [17:0]             spl_rx_hdr0;
    wire [511:0]            spl_rx_data;
    wire                    spl_rx_wr_valid1;
    wire                    spl_rx_intr_valid1;
    wire [17:0]             spl_rx_hdr1;
    wire                    spl_enable;
    wire                    spl_reset;
    
    
    spl_cci_top spl_cci_top(
        .clk                        (vl_clk_LPdomain_32ui),
        .reset_n                    (ffs_vl_LP32ui_lp2sy_SystemReset_n),
        .linkup                     (ffs_vl_LP32ui_lp2sy_InitDnForSys),
        .spl_enable                 (spl_enable),
        .spl_reset                  (spl_reset),
    

        .spl_tx_rd_almostfull       (spl_tx_rd_almostfull),
        .afu_tx_rd_valid            (afu_tx_rd_valid),
        .afu_tx_rd_hdr              (afu_tx_rd_hdr),
    

        .spl_tx_wr_almostfull       (spl_tx_wr_almostfull),
        .afu_tx_wr_valid            (afu_tx_wr_valid),
        .afu_tx_intr_valid          (afu_tx_intr_valid),
        .afu_tx_wr_hdr              (afu_tx_wr_hdr),    
        .afu_tx_data                (afu_tx_data),
    

        .spl_rx_rd_valid            (spl_rx_rd_valid),
        .spl_rx_wr_valid0           (spl_rx_wr_valid0),
        .spl_rx_cfg_valid           (spl_rx_cfg_valid),
        .spl_rx_intr_valid0         (spl_rx_intr_valid0),
        .spl_rx_umsg_valid          (spl_rx_umsg_valid),
        .spl_rx_hdr0                (spl_rx_hdr0),
        .spl_rx_data                (spl_rx_data),
    

        .spl_rx_wr_valid1           (spl_rx_wr_valid1),
        .spl_rx_intr_valid1         (spl_rx_intr_valid1),
        .spl_rx_hdr1                (spl_rx_hdr1),
    

        .cci_tx_rd_almostfull       (ffs_vl_LP32ui_lp2sy_C0TxAlmFull),
        .spl_tx_rd_valid            (ffs_vl_LP32ui_sy2lp_C0TxRdValid),
        .spl_tx_rd_hdr              (ffs_vl61_LP32ui_sy2lp_C0TxHdr),
    

        .cci_tx_wr_almostfull       (ffs_vl_LP32ui_lp2sy_C1TxAlmFull),
        .spl_tx_wr_valid            (ffs_vl_LP32ui_sy2lp_C1TxWrValid),
        .spl_tx_intr_valid          (ffs_vl_LP32ui_sy2lp_C1TxIrValid),
        .spl_tx_wr_hdr              (ffs_vl61_LP32ui_sy2lp_C1TxHdr),    
        .spl_tx_data                (ffs_vl512_LP32ui_sy2lp_C1TxData),
    

        .cci_rx_rd_valid            (ffs_vl_LP32ui_lp2sy_C0RxRdValid),
        .cci_rx_wr_valid0           (ffs_vl_LP32ui_lp2sy_C0RxWrValid),
        .cci_rx_cfg_valid           (ffs_vl_LP32ui_lp2sy_C0RxCgValid),
        .cci_rx_intr_valid0         (ffs_vl_LP32ui_lp2sy_C0RxIrValid),
        .cci_rx_umsg_valid          (ffs_vl_LP32ui_lp2sy_C0RxUgValid),
        .cci_rx_hdr0                (ffs_vl18_LP32ui_lp2sy_C0RxHdr),
        .cci_rx_data                (ffs_vl512_LP32ui_lp2sy_C0RxData),
    

        .cci_rx_wr_valid1           (ffs_vl_LP32ui_lp2sy_C1RxWrValid),
        .cci_rx_intr_valid1         (ffs_vl_LP32ui_lp2sy_C1RxIrValid),
        .cci_rx_hdr1                (ffs_vl18_LP32ui_lp2sy_C1RxHdr)
    );


    cci_ext_afu cci_ext_afu(
      .vl_clk_LPdomain_32ui             (vl_clk_LPdomain_32ui),
      .vl_clk_LPdomain_16ui             (vl_clk_LPdomain_16ui),
      .ffs_vl_LP32ui_lp2sy_SystemReset_n(ffs_vl_LP32ui_lp2sy_SystemReset_n),
      .ffs_vl_LP32ui_lp2sy_SoftReset_n  (~spl_reset),

      .ffs_vl24_LP32ui_lp2sy_C0RxHdr    (spl_rx_hdr0),
      .ffs_vl512_LP32ui_lp2sy_C0RxData  (spl_rx_data),
      .ffs_vl_LP32ui_lp2sy_C0RxWrValid  (spl_rx_wr_valid0),
      .ffs_vl_LP32ui_lp2sy_C0RxRdValid  (spl_rx_rd_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxCgValid  (spl_rx_cfg_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxUgValid  (spl_rx_umsg_valid),
      .ffs_vl_LP32ui_lp2sy_C0RxIrValid  (spl_rx_intr_valid0),

      .ffs_vl24_LP32ui_lp2sy_C1RxHdr    (spl_rx_hdr1),
      .ffs_vl_LP32ui_lp2sy_C1RxWrValid  (spl_rx_wr_valid1),
      .ffs_vl_LP32ui_lp2sy_C1RxIrValid  (spl_rx_intr_valid1),

      .ffs_vl99_LP32ui_sy2lp_C0TxHdr    (afu_tx_rd_hdr),
      .ffs_vl_LP32ui_sy2lp_C0TxRdValid  (afu_tx_rd_valid),

      .ffs_vl99_LP32ui_sy2lp_C1TxHdr    (afu_tx_wr_hdr),
      .ffs_vl512_LP32ui_sy2lp_C1TxData  (afu_tx_data),
      .ffs_vl_LP32ui_sy2lp_C1TxWrValid  (afu_tx_wr_valid),
      .ffs_vl_LP32ui_sy2lp_C1TxIrValid  (afu_tx_intr_valid),

      .ffs_vl_LP32ui_lp2sy_C0TxAlmFull  (spl_tx_rd_almostfull),
      .ffs_vl_LP32ui_lp2sy_C1TxAlmFull  (spl_tx_wr_almostfull),

      .ffs_vl_LP32ui_lp2sy_InitDnForSys (spl_enable)
    );

endmodule