data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:2: Cannot find include file: NAND_G.v\n `include "NAND_G.v" \n          ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate,data/full_repos/permissive/414867793/NAND_G.v\n             data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate,data/full_repos/permissive/414867793/NAND_G.v.v\n             data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate,data/full_repos/permissive/414867793/NAND_G.v.sv\n             NAND_G.v\n             NAND_G.v.v\n             NAND_G.v.sv\n             obj_dir/NAND_G.v\n             obj_dir/NAND_G.v.v\n             obj_dir/NAND_G.v.sv\n%Error: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("NAND_G_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1,NAND_G_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/Nand_Gate/NAND_G_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module NAND_G_tb();
reg A,B;
wire C;
NAND_G uut(A,B,C);

initial begin
  $dumpfile("NAND_G_tb.vcd");
  $dumpvars(1,NAND_G_tb);
   
   A=0;
   B=0;
   #20
   A=0;
   B=1;
   #20;
   A=1;
   B=0;
   #20
   A=1;
   B=1;
   #20
   $display("Done Testing");
end

endmodule
module NAND_G_tb();

reg A,B;
wire C;
NAND_G uut(A,B,C);

initial begin
  $dumpfile("NAND_G_tb.vcd");
  $dumpvars(1,NAND_G_tb);
   
   A=0;
   B=0;
   #20
   A=0;
   B=1;
   #20;
   A=1;
   B=0;
   #20
   A=1;
   B=1;
   #20
   $display("Done Testing");
end

endmodule