data/full_repos/permissive/52633518/core_top.v
1: b"%Error: data/full_repos/permissive/52633518/core_top.v:20: Cannot find file containing module: 'register_file'\nregister_file register_file0(clk, rst, reg_we, reg_addr_a, reg_addr_b, reg_addr_c, reg_addr_d, reg_data_c, reg_data_a, reg_data_b, reg_data_d);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52633518,data/full_repos/permissive/52633518/register_file\n             data/full_repos/permissive/52633518,data/full_repos/permissive/52633518/register_file.v\n             data/full_repos/permissive/52633518,data/full_repos/permissive/52633518/register_file.sv\n             register_file\n             register_file.v\n             register_file.sv\n             obj_dir/register_file\n             obj_dir/register_file.v\n             obj_dir/register_file.sv\n%Error: data/full_repos/permissive/52633518/core_top.v:22: Cannot find file containing module: 'alu16'\nalu16 alu16_0( clk,rst,alu_operator, alu_op_a, reg_data_b, alu_out, alu_status);\n^~~~~\n%Error: data/full_repos/permissive/52633518/core_top.v:24: Cannot find file containing module: 'control_fsm'\ncontrol_fsm control_fsm0( clk, rst, run_n, ram_q, reg_data_a, reg_data_b, alu_status, alu_out,\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/52633518/core_top.v:28: Cannot find file containing module: 'main_memory'\nmain_memory main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);          \n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module core_top(

  input clk, rst, run_n,
  input [3:0] reg_addr_d, 
  output [15:0] reg_out

);


wire reg_we, sram_we_n, ram_wren;
wire [2:0] alu_operator;
wire [3:0] reg_addr_a, reg_addr_b, reg_addr_c;
wire [15:0] ram_addr, ram_data, reg_data_a, reg_data_b, reg_data_c, reg_data_d, alu_op_a,alu_out,alu_status, ram_q,pc;

assign reg_out = reg_data_d;
assign ram_wren = ~sram_we_n;



register_file register_file0(clk, rst, reg_we, reg_addr_a, reg_addr_b, reg_addr_c, reg_addr_d, reg_data_c, reg_data_a, reg_data_b, reg_data_d);

alu16 alu16_0( clk,rst,alu_operator, alu_op_a, reg_data_b, alu_out, alu_status);

control_fsm control_fsm0( clk, rst, run_n, ram_q, reg_data_a, reg_data_b, alu_status, alu_out,
								  sram_we_n, reg_we, alu_operator, reg_addr_a, reg_addr_b,
								  reg_addr_c, alu_op_a, reg_data_c, ram_addr, ram_data);

main_memory main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);								  









  
endmodule
module core_top(

  input clk, rst, run_n,
  input [3:0] reg_addr_d, 
  output [15:0] reg_out

);



wire reg_we, sram_we_n, ram_wren;
wire [2:0] alu_operator;
wire [3:0] reg_addr_a, reg_addr_b, reg_addr_c;
wire [15:0] ram_addr, ram_data, reg_data_a, reg_data_b, reg_data_c, reg_data_d, alu_op_a,alu_out,alu_status, ram_q,pc;

assign reg_out = reg_data_d;
assign ram_wren = ~sram_we_n;



register_file register_file0(clk, rst, reg_we, reg_addr_a, reg_addr_b, reg_addr_c, reg_addr_d, reg_data_c, reg_data_a, reg_data_b, reg_data_d);

alu16 alu16_0( clk,rst,alu_operator, alu_op_a, reg_data_b, alu_out, alu_status);

control_fsm control_fsm0( clk, rst, run_n, ram_q, reg_data_a, reg_data_b, alu_status, alu_out,
								  sram_we_n, reg_we, alu_operator, reg_addr_a, reg_addr_b,
								  reg_addr_c, alu_op_a, reg_data_c, ram_addr, ram_data);

main_memory main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);								  









  
endmodule