data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/new/rom.v
data/verilator_xmls/e843e4e2-6efd-4083-a047-2191b73333db.xml
module ROM(
    output reg [7:0] dout,
    input [4:0] addr,
    input clk
);

    reg [7:0] mem [31:0];
    initial $readmemb("rom.data", mem);

    always @(posedge clk)
    begin
        dout <= mem[addr];
    end
endmodule
module ROM(
    output reg [7:0] dout,
    input [4:0] addr,
    input clk
);


    reg [7:0] mem [31:0];
    initial $readmemb("rom.data", mem);

    always @(posedge clk)
    begin
        dout <= mem[addr];
    end
endmodule