data/full_repos/permissive/527249789/src/mycpu_top.v
1: b'%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:55: Define or directive not defined: \'`InstAddrBus\'\n    output  [`InstAddrBus]              debug_wb_pc,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output  [`InstAddrBus]              debug_wb_pc,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:57: Define or directive not defined: \'`RegAddrBus\'\n    output  [`RegAddrBus]               debug_wb_rf_wnum,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:58: Define or directive not defined: \'`RegBus\'\n    output  [`RegBus]                   debug_wb_rf_wdata\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:98: syntax error, unexpected int, expecting IDENTIFIER or do or final\nwire[5:0] int;\n          ^~~\n%Error: data/full_repos/permissive/527249789/src/mycpu_top.v:100: syntax error, unexpected assign\nassign int = {timer_int, ext_int[4:0]};\n^~~~~~\n%Error: Exiting due to 7 error(s)\n'
module mycpu_top(
    input   [5:0]                       ext_int,

    input                               aclk,
    input                               aresetn,


    output  [3:0]                       arid,
    output  [31:0]                      araddr,
    output  [7:0]                       arlen,
    output  [2:0]                       arsize,
    output  [1:0]                       arburst,
    output  [1:0]                       arlock,
    output  [3:0]                       arcache,
    output  [2:0]                       arprot,
    output                              arvalid,
    input                               arready,


    input   [3:0]                       rid,
    input   [31:0]                      rdata,
    input   [1:0]                       rresp,
    input                               rlast,
    input                               rvalid,
    output                              rready,


    output  [3:0]                       awid,
    output  [31:0]                      awaddr,
    output  [7:0]                       awlen,
    output  [2:0]                       awsize,
    output  [1:0]                       awburst,
    output  [1:0]                       awlock,
    output  [3:0]                       awcache,
    output  [2:0]                       awprot,
    output                              awvalid,
    input                               awready,


    output  [3:0]                       wid,
    output  [31:0]                      wdata,
    output  [3:0]                       wstrb,
    output                              wlast,
    output                              wvalid,
    input                               wready,


    input   [3:0]                       bid,
    input   [1:0]                       bresp,
    input                               bvalid,
    output                              bready,

    output  [`InstAddrBus]              debug_wb_pc,
    output  [3:0]                       debug_wb_rf_wen,
    output  [`RegAddrBus]               debug_wb_rf_wnum,
    output  [`RegBus]                   debug_wb_rf_wdata
);
wire        cpu_cache_ireq;
wire        cpu_cache_iwr;
wire [1 :0] cpu_cache_isize;
wire [31:0] cpu_cache_iaddr;
wire [31:0] cpu_cache_iwdata;
wire [31:0] cpu_cache_irdata;
wire        cpu_cache_iaddrok;
wire        cpu_cache_idataok;

wire        axi_cache_arready;
wire        axi_cache_rvalid;
wire        axi_cache_rlast;
wire [31:0] axi_cache_rdata;
wire        axi_cache_arvalid;
wire [1: 0] axi_cache_rtype;
wire [31:0] axi_cache_raddr;
wire        axi_cache_rready;
wire        axi_cache_bvalid;











wire data_req;
wire data_wr;
wire[1:0] data_size;
wire[31:0] data_addr;
wire[31:0] data_wdata;
wire[31:0] data_rdata;
wire data_addr_ok;
wire data_data_ok;

wire[5:0] int;
wire timer_int;
assign int = {timer_int, ext_int[4:0]};

cpu_axi_interface u_cpu_axi_interface(
    .clk(aclk),
    .resetn(aresetn),
    
    .cache_arready(axi_cache_arready),
    .cache_rvalid(axi_cache_rvalid),
    .cache_rlast(axi_cache_rlast),
    .cache_rdata(axi_cache_rdata),
    .cache_rreq(axi_cache_arvalid),
    .cache_rtype(axi_cache_rtype),
    .cache_raddr(axi_cache_raddr),
    .cache_rready(axi_cache_rready),
    .cache_bvalid(axi_cache_bvalid),
    









    .data_req(data_req),
    .data_wr(data_wr),
    .data_size(data_size),
    .data_addr(data_addr),
    .data_wdata(data_wdata),
    .data_rdata(data_rdata),
    .data_addr_ok(data_addr_ok),
    .data_data_ok(data_data_ok),

    .arid(arid),
    .araddr(araddr),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),
    .arlock(arlock),
    .arcache(arcache),
    .arprot(arprot),
    .arvalid(arvalid),
    .arready(arready),

    .rid(rid),
    .rdata(rdata),
    .rresp(rresp),
    .rlast(rlast),
    .rvalid(rvalid),
    .rready(rready),

    .awid(awid),
    .awaddr(awaddr),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),
    .awlock(awlock),
    .awcache(awcache),
    .awprot(awprot),
    .awvalid(awvalid),
    .awready(awready),

    .wid(wid),
    .wdata(wdata),
    .wstrb(wstrb),
    .wlast(wlast),
    .wvalid(wvalid),
    .wready(wready),

    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready)
);

mycpu u_mycpu(
    .clk(aclk),
    .resetn(aresetn),
    .ext_int(int),
    .timer_int_o(timer_int),

    .inst_req(cpu_cache_ireq),
    .inst_wr(cpu_cache_iwr),
    .inst_size(cpu_cache_isize),
    .inst_addr(cpu_cache_iaddr),
    .inst_wdata(cpu_cache_iwdata),
    .inst_rdata(cpu_cache_irdata),
    .inst_addr_ok(cpu_cache_iaddrok),
    .inst_data_ok(cpu_cache_idataok),

    .data_req(data_req),
    .data_wr(data_wr),
    .data_size(data_size),
    .data_addr(data_addr),
    .data_wdata(data_wdata),
    .data_rdata(data_rdata),
    .data_addr_ok(data_addr_ok),
    .data_data_ok(data_data_ok),

    .debug_wb_pc(debug_wb_pc),
    .debug_wb_rf_wen(debug_wb_rf_wen),
    .debug_wb_rf_wnum(debug_wb_rf_wnum),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);

Cache_top u_cache(
    .clk(aclk),
    .resetn(aresetn),
    
    .inst_cpu_req(cpu_cache_ireq),
    .inst_cpu_wr(cpu_cache_iwr),
    .inst_cpu_size(cpu_cache_isize),
    .inst_cpu_addr(cpu_cache_iaddr),
    .inst_cpu_wdata(cpu_cache_iwdata),
    .inst_cpu_rdata(cpu_cache_irdata),
    .inst_cpu_arready(cpu_cache_iaddrok),
    .inst_cpu_rready(cpu_cache_idataok),
    








    
    .axi_arready(axi_cache_arready),
    .axi_rvalid(axi_cache_rvalid),
    .axi_rlast(axi_cache_rlast),
    .axi_rdata(axi_cache_rdata),
    
    .axi_rreq(axi_cache_arvalid),
    .axi_rtype(axi_cache_rtype),
    .axi_raddr(axi_cache_raddr),
    .axi_rready(axi_cache_rready),
    







    .bvalid(axi_cache_bvalid)
);

endmodule
module mycpu_top(
    input   [5:0]                       ext_int,

    input                               aclk,
    input                               aresetn,


    output  [3:0]                       arid,
    output  [31:0]                      araddr,
    output  [7:0]                       arlen,
    output  [2:0]                       arsize,
    output  [1:0]                       arburst,
    output  [1:0]                       arlock,
    output  [3:0]                       arcache,
    output  [2:0]                       arprot,
    output                              arvalid,
    input                               arready,


    input   [3:0]                       rid,
    input   [31:0]                      rdata,
    input   [1:0]                       rresp,
    input                               rlast,
    input                               rvalid,
    output                              rready,


    output  [3:0]                       awid,
    output  [31:0]                      awaddr,
    output  [7:0]                       awlen,
    output  [2:0]                       awsize,
    output  [1:0]                       awburst,
    output  [1:0]                       awlock,
    output  [3:0]                       awcache,
    output  [2:0]                       awprot,
    output                              awvalid,
    input                               awready,


    output  [3:0]                       wid,
    output  [31:0]                      wdata,
    output  [3:0]                       wstrb,
    output                              wlast,
    output                              wvalid,
    input                               wready,


    input   [3:0]                       bid,
    input   [1:0]                       bresp,
    input                               bvalid,
    output                              bready,

    output  [`InstAddrBus]              debug_wb_pc,
    output  [3:0]                       debug_wb_rf_wen,
    output  [`RegAddrBus]               debug_wb_rf_wnum,
    output  [`RegBus]                   debug_wb_rf_wdata
);

wire        cpu_cache_ireq;
wire        cpu_cache_iwr;
wire [1 :0] cpu_cache_isize;
wire [31:0] cpu_cache_iaddr;
wire [31:0] cpu_cache_iwdata;
wire [31:0] cpu_cache_irdata;
wire        cpu_cache_iaddrok;
wire        cpu_cache_idataok;

wire        axi_cache_arready;
wire        axi_cache_rvalid;
wire        axi_cache_rlast;
wire [31:0] axi_cache_rdata;
wire        axi_cache_arvalid;
wire [1: 0] axi_cache_rtype;
wire [31:0] axi_cache_raddr;
wire        axi_cache_rready;
wire        axi_cache_bvalid;











wire data_req;
wire data_wr;
wire[1:0] data_size;
wire[31:0] data_addr;
wire[31:0] data_wdata;
wire[31:0] data_rdata;
wire data_addr_ok;
wire data_data_ok;

wire[5:0] int;
wire timer_int;
assign int = {timer_int, ext_int[4:0]};

cpu_axi_interface u_cpu_axi_interface(
    .clk(aclk),
    .resetn(aresetn),
    
    .cache_arready(axi_cache_arready),
    .cache_rvalid(axi_cache_rvalid),
    .cache_rlast(axi_cache_rlast),
    .cache_rdata(axi_cache_rdata),
    .cache_rreq(axi_cache_arvalid),
    .cache_rtype(axi_cache_rtype),
    .cache_raddr(axi_cache_raddr),
    .cache_rready(axi_cache_rready),
    .cache_bvalid(axi_cache_bvalid),
    









    .data_req(data_req),
    .data_wr(data_wr),
    .data_size(data_size),
    .data_addr(data_addr),
    .data_wdata(data_wdata),
    .data_rdata(data_rdata),
    .data_addr_ok(data_addr_ok),
    .data_data_ok(data_data_ok),

    .arid(arid),
    .araddr(araddr),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),
    .arlock(arlock),
    .arcache(arcache),
    .arprot(arprot),
    .arvalid(arvalid),
    .arready(arready),

    .rid(rid),
    .rdata(rdata),
    .rresp(rresp),
    .rlast(rlast),
    .rvalid(rvalid),
    .rready(rready),

    .awid(awid),
    .awaddr(awaddr),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),
    .awlock(awlock),
    .awcache(awcache),
    .awprot(awprot),
    .awvalid(awvalid),
    .awready(awready),

    .wid(wid),
    .wdata(wdata),
    .wstrb(wstrb),
    .wlast(wlast),
    .wvalid(wvalid),
    .wready(wready),

    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready)
);

mycpu u_mycpu(
    .clk(aclk),
    .resetn(aresetn),
    .ext_int(int),
    .timer_int_o(timer_int),

    .inst_req(cpu_cache_ireq),
    .inst_wr(cpu_cache_iwr),
    .inst_size(cpu_cache_isize),
    .inst_addr(cpu_cache_iaddr),
    .inst_wdata(cpu_cache_iwdata),
    .inst_rdata(cpu_cache_irdata),
    .inst_addr_ok(cpu_cache_iaddrok),
    .inst_data_ok(cpu_cache_idataok),

    .data_req(data_req),
    .data_wr(data_wr),
    .data_size(data_size),
    .data_addr(data_addr),
    .data_wdata(data_wdata),
    .data_rdata(data_rdata),
    .data_addr_ok(data_addr_ok),
    .data_data_ok(data_data_ok),

    .debug_wb_pc(debug_wb_pc),
    .debug_wb_rf_wen(debug_wb_rf_wen),
    .debug_wb_rf_wnum(debug_wb_rf_wnum),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)
);

Cache_top u_cache(
    .clk(aclk),
    .resetn(aresetn),
    
    .inst_cpu_req(cpu_cache_ireq),
    .inst_cpu_wr(cpu_cache_iwr),
    .inst_cpu_size(cpu_cache_isize),
    .inst_cpu_addr(cpu_cache_iaddr),
    .inst_cpu_wdata(cpu_cache_iwdata),
    .inst_cpu_rdata(cpu_cache_irdata),
    .inst_cpu_arready(cpu_cache_iaddrok),
    .inst_cpu_rready(cpu_cache_idataok),
    








    
    .axi_arready(axi_cache_arready),
    .axi_rvalid(axi_cache_rvalid),
    .axi_rlast(axi_cache_rlast),
    .axi_rdata(axi_cache_rdata),
    
    .axi_rreq(axi_cache_arvalid),
    .axi_rtype(axi_cache_rtype),
    .axi_raddr(axi_cache_raddr),
    .axi_rready(axi_cache_rready),
    







    .bvalid(axi_cache_bvalid)
);

endmodule