data/full_repos/permissive/443520440/code/seg7_driver.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/443520440/code/seg7_driver.v:65: Cell has missing pin: \'rst\'\n    Divider display_div(.I_CLK(clk), .O_CLK(display_clk));\n            ^~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module display7(
	input 				clk		,
	input [3:0] 		led1	,
	input [3:0] 		led2	,
	input [3:0] 		led3	,
	input [3:0] 		led4	,
	input [3:0] 		led5	,
	input [3:0] 		led6	,
	input [3:0] 		led7	,
	input [3:0] 		led8	,
	output reg [7:0] 	ena		,
	output [7:0] 		ctl
);
    wire display_clk;
    Divider display_div(.I_CLK(clk), .O_CLK(display_clk));
	reg [3:0] led;
	trans7 trans7_0(led, ctl);
	reg [2:0] cnt;
	initial begin
	  cnt <= 0;
	  ena <= 0;
	end
	always @(posedge display_clk) begin
		cnt <= cnt + 1;
	end
	always @(posedge display_clk)
		case(cnt)
			default: led <= led1;
			3'b000:	led <= led1;
			3'b001:	led <= led2;
			3'b010:	led <= led3;
			3'b011:	led <= led4;
			3'b100:	led <= led5;
			3'b101:	led <= led6;
			3'b110:	led <= led7;
			3'b111:	led <= led8;
		endcase
	always @(posedge display_clk)
		case(cnt)
			default: ena <= 8'b11111110;
			3'b000:	ena <= 8'b11111110;
			3'b001:	ena <= 8'b11111101;
			3'b010:	ena <= 8'b11111011;
			3'b011:	ena <= 8'b11110111;
			3'b100:	ena <= 8'b11101111;
			3'b101:	ena <= 8'b11011111;
			3'b110:	ena <= 8'b10111111;
			3'b111:	ena <= 8'b01111111;
		endcase
endmodule
module display7(
	input 				clk		,
	input [3:0] 		led1	,
	input [3:0] 		led2	,
	input [3:0] 		led3	,
	input [3:0] 		led4	,
	input [3:0] 		led5	,
	input [3:0] 		led6	,
	input [3:0] 		led7	,
	input [3:0] 		led8	,
	output reg [7:0] 	ena		,
	output [7:0] 		ctl
);

    wire display_clk;
    Divider display_div(.I_CLK(clk), .O_CLK(display_clk));
	reg [3:0] led;
	trans7 trans7_0(led, ctl);
	reg [2:0] cnt;
	initial begin
	  cnt <= 0;
	  ena <= 0;
	end
	always @(posedge display_clk) begin
		cnt <= cnt + 1;
	end
	always @(posedge display_clk)
		case(cnt)
			default: led <= led1;
			3'b000:	led <= led1;
			3'b001:	led <= led2;
			3'b010:	led <= led3;
			3'b011:	led <= led4;
			3'b100:	led <= led5;
			3'b101:	led <= led6;
			3'b110:	led <= led7;
			3'b111:	led <= led8;
		endcase
	always @(posedge display_clk)
		case(cnt)
			default: ena <= 8'b11111110;
			3'b000:	ena <= 8'b11111110;
			3'b001:	ena <= 8'b11111101;
			3'b010:	ena <= 8'b11111011;
			3'b011:	ena <= 8'b11110111;
			3'b100:	ena <= 8'b11101111;
			3'b101:	ena <= 8'b11011111;
			3'b110:	ena <= 8'b10111111;
			3'b111:	ena <= 8'b01111111;
		endcase
endmodule