data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:10: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    sysio_axi_awaddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`MemAddrBus]    sysio_axi_awaddr , \n                           ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sysio_axi_awready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:14: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemBus]        sysio_axi_wdata  , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:14: Define or directive not defined: \'`MemBus\'\n    input wire [`MemBus]        sysio_axi_wdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                  sysio_axi_wvalid , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sysio_axi_wready , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:19: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [`MemAddrBus]    sysio_axi_araddr , \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:19: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus]    sysio_axi_araddr , \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                  sysio_axi_arready, \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`MemBus]        sysio_axi_rdata  , \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:23: Define or directive not defined: \'`MemBus\'\n    output reg [`MemBus]        sysio_axi_rdata  , \n                ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:25: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire                  sysio_axi_rready  \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:36: Define or directive not defined: \'`MemBus\'\nwire [`MemBus]din = sysio_axi_wdata; \n      ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`MemBus]din = sysio_axi_wdata; \n             ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:39: syntax error, unexpected always\nalways @(*) begin\n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:47: Define or directive not defined: \'`MemBus\'\nwire [`MemBus]dout; \n      ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`MemBus]dout; \n             ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:69: syntax error, unexpected genvar\ngenvar i;\n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:78: syntax error, unexpected generate\ngenerate\n^~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:84: syntax error, unexpected always\nalways @(posedge clk ) begin\n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/sysio.v:90: Define or directive not defined: \'`MemBus\'\nwire [`MemBus]data_o[0:15];\n      ^~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module sysio (
	input clk,
	input rst_n,

    inout wire [31:0] fpioa,



    input wire [`MemAddrBus]    sysio_axi_awaddr ,
    input wire                  sysio_axi_awvalid,
    output reg                  sysio_axi_awready,

    input wire [`MemBus]        sysio_axi_wdata  ,
    input wire [3:0]            sysio_axi_wstrb  ,
    input wire                  sysio_axi_wvalid ,
    output reg                  sysio_axi_wready ,

    input wire [`MemAddrBus]    sysio_axi_araddr ,
    input wire                  sysio_axi_arvalid,
    output reg                  sysio_axi_arready,

    output reg [`MemBus]        sysio_axi_rdata  ,
    output reg                  sysio_axi_rvalid ,
    input wire                  sysio_axi_rready
	
);

wire [31:0] gpio_oe ;
wire [31:0] gpio_out;
wire [31:0] gpio_in ;


wire axi_whsk = sysio_axi_awvalid & sysio_axi_wvalid;
wire [7:0] waddr = {sysio_axi_awaddr[7:2], 2'b00};
wire [`MemBus]din = sysio_axi_wdata;
wire [3:0]sel = sysio_axi_wstrb;
wire we = axi_whsk;
always @(*) begin
    sysio_axi_awready = axi_whsk;
    sysio_axi_wready  = axi_whsk;
end

wire axi_rhsk = sysio_axi_arvalid & (~sysio_axi_rvalid | (sysio_axi_rvalid & sysio_axi_rready));
wire [7:0] raddr = {sysio_axi_araddr[7:2], 2'b00};
wire rd = axi_rhsk;
wire [`MemBus]dout;
always @(posedge clk or negedge rst_n)
if (~rst_n)
    sysio_axi_rvalid <=1'b0;
else begin
    if (axi_rhsk)
        sysio_axi_rvalid <=1'b1;
    else if (sysio_axi_rvalid & sysio_axi_rready)
        sysio_axi_rvalid <=1'b0;
    else
        sysio_axi_rvalid <= sysio_axi_rvalid;
end
always @(*) begin
    sysio_axi_arready = axi_rhsk;
    sysio_axi_rdata = dout;
end





wire [15:0]we_en;
genvar i;
generate
for (i = 0; i<16; i=i+1) begin
    assign we_en[i] = (sysio_axi_awaddr[11:8] == i)? axi_whsk : 1'b0;
end
endgenerate


wire [15:0]rd_en;
generate
for (i = 0; i<16; i=i+1) begin
    assign rd_en[i] = (sysio_axi_araddr[11:8] == i)? axi_rhsk : 1'b0;
end
endgenerate
reg [15:0]rd_en_r;
always @(posedge clk ) begin
    if(axi_rhsk)
        rd_en_r <= rd_en;
    else
        rd_en_r <= rd_en_r;
end
wire [`MemBus]data_o[0:15];
assign dout = {32{rd_en_r[0]}} & data_o[0]
            | {32{rd_en_r[1]}} & data_o[1]
            | {32{rd_en_r[2]}} & data_o[2]
            | {32{rd_en_r[3]}} & data_o[3]
            | {32{rd_en_r[4]}} & data_o[4]
            | {32{rd_en_r[5]}} & data_o[5]
            | {32{rd_en_r[6]}} & data_o[6]
            | {32{rd_en_r[7]}} & data_o[7]
            | {32{rd_en_r[8]}} & data_o[8]
            | {32{rd_en_r[9]}} & data_o[9]
            | {32{rd_en_r[10]}} & data_o[10]
            | {32{rd_en_r[11]}} & data_o[11]
            | {32{rd_en_r[12]}} & data_o[12]
            | {32{rd_en_r[13]}} & data_o[13]
            | {32{rd_en_r[14]}} & data_o[14]
            | {32{rd_en_r[15]}} & data_o[15];


uart inst_uart0
(
    .clk     (clk),
    .rst_n   (rst_n),

    .waddr_i (waddr[7:0]),
    .data_i  (din),
    .sel_i   (sel),
    .we_i    (we_en[0]),
    .raddr_i (raddr),
    .rd_i    (rd_en[0]),
    .data_o  (data_o[0]),

    .tx_pin  (uart0_tx),
    .rx_pin  (uart0_rx)
);

uart inst_uart1
(
    .clk     (clk),
    .rst_n   (rst_n),

    .waddr_i (waddr),
    .data_i  (din),
    .sel_i   (sel),
    .we_i    (we_en[1]),
    .raddr_i (raddr),
    .rd_i    (rd_en[1]),
    .data_o  (data_o[1]),

    .tx_pin  (uart1_tx),
    .rx_pin  (uart1_rx)
);

spi inst_spi0
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[2]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[2]),
    .data_o   (data_o[2]),

    .spi_mosi (spi0_mosi),
    .spi_miso (spi0_miso),
    .spi_cs   (spi0_cs  ),
    .spi_clk  (spi0_clk )
);

spi inst_spi1
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[3]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[3]),
    .data_o   (data_o[3]),

    .spi_mosi (spi1_mosi),
    .spi_miso (spi1_miso),
    .spi_cs   (spi1_cs  ),
    .spi_clk  (spi1_clk )
);

gpio inst_gpio
(
    .clk           (clk),
    .rst_n         (rst_n),

    .waddr_i       (waddr),
    .data_i        (din),
    .sel_i         (sel),
    .we_i          (we_en[4]),
    .raddr_i       (raddr),
    .rd_i          (rd_en[4]),
    .data_o        (data_o[4]),

    .gpio_oe       (gpio_oe ),
    .gpio_out      (gpio_out),
    .gpio_in       (gpio_in )
);

fpioa inst_fpioa
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[15]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[15]),
    .data_o   (data_o[15]),

    .SPI0_SCK  (spi0_clk),
    .SPI0_MOSI (spi0_mosi),
    .SPI0_MISO (spi0_miso),
    .SPI0_CS   (spi0_cs),
    .SPI1_SCK  (spi1_clk),
    .SPI1_MOSI (spi1_mosi),
    .SPI1_MISO (spi1_miso),
    .SPI1_CS   (spi1_cs),
    .UART0_TX  (uart0_tx),
    .UART0_RX  (uart0_rx),
    .UART1_TX  (uart1_tx),
    .UART1_RX  (uart1_rx),

    .gpio_oe  (gpio_oe ),
    .gpio_out (gpio_out),
    .gpio_in  (gpio_in ),

    .fpioa    (fpioa)
);

endmodule
module sysio (
	input clk,
	input rst_n,

    inout wire [31:0] fpioa,



    input wire [`MemAddrBus]    sysio_axi_awaddr ,
    input wire                  sysio_axi_awvalid,
    output reg                  sysio_axi_awready,

    input wire [`MemBus]        sysio_axi_wdata  ,
    input wire [3:0]            sysio_axi_wstrb  ,
    input wire                  sysio_axi_wvalid ,
    output reg                  sysio_axi_wready ,

    input wire [`MemAddrBus]    sysio_axi_araddr ,
    input wire                  sysio_axi_arvalid,
    output reg                  sysio_axi_arready,

    output reg [`MemBus]        sysio_axi_rdata  ,
    output reg                  sysio_axi_rvalid ,
    input wire                  sysio_axi_rready
	
);


wire [31:0] gpio_oe ;
wire [31:0] gpio_out;
wire [31:0] gpio_in ;


wire axi_whsk = sysio_axi_awvalid & sysio_axi_wvalid;
wire [7:0] waddr = {sysio_axi_awaddr[7:2], 2'b00};
wire [`MemBus]din = sysio_axi_wdata;
wire [3:0]sel = sysio_axi_wstrb;
wire we = axi_whsk;
always @(*) begin
    sysio_axi_awready = axi_whsk;
    sysio_axi_wready  = axi_whsk;
end

wire axi_rhsk = sysio_axi_arvalid & (~sysio_axi_rvalid | (sysio_axi_rvalid & sysio_axi_rready));
wire [7:0] raddr = {sysio_axi_araddr[7:2], 2'b00};
wire rd = axi_rhsk;
wire [`MemBus]dout;
always @(posedge clk or negedge rst_n)
if (~rst_n)
    sysio_axi_rvalid <=1'b0;
else begin
    if (axi_rhsk)
        sysio_axi_rvalid <=1'b1;
    else if (sysio_axi_rvalid & sysio_axi_rready)
        sysio_axi_rvalid <=1'b0;
    else
        sysio_axi_rvalid <= sysio_axi_rvalid;
end
always @(*) begin
    sysio_axi_arready = axi_rhsk;
    sysio_axi_rdata = dout;
end





wire [15:0]we_en;
genvar i;
generate
for (i = 0; i<16; i=i+1) begin
    assign we_en[i] = (sysio_axi_awaddr[11:8] == i)? axi_whsk : 1'b0;
end
endgenerate


wire [15:0]rd_en;
generate
for (i = 0; i<16; i=i+1) begin
    assign rd_en[i] = (sysio_axi_araddr[11:8] == i)? axi_rhsk : 1'b0;
end
endgenerate
reg [15:0]rd_en_r;
always @(posedge clk ) begin
    if(axi_rhsk)
        rd_en_r <= rd_en;
    else
        rd_en_r <= rd_en_r;
end
wire [`MemBus]data_o[0:15];
assign dout = {32{rd_en_r[0]}} & data_o[0]
            | {32{rd_en_r[1]}} & data_o[1]
            | {32{rd_en_r[2]}} & data_o[2]
            | {32{rd_en_r[3]}} & data_o[3]
            | {32{rd_en_r[4]}} & data_o[4]
            | {32{rd_en_r[5]}} & data_o[5]
            | {32{rd_en_r[6]}} & data_o[6]
            | {32{rd_en_r[7]}} & data_o[7]
            | {32{rd_en_r[8]}} & data_o[8]
            | {32{rd_en_r[9]}} & data_o[9]
            | {32{rd_en_r[10]}} & data_o[10]
            | {32{rd_en_r[11]}} & data_o[11]
            | {32{rd_en_r[12]}} & data_o[12]
            | {32{rd_en_r[13]}} & data_o[13]
            | {32{rd_en_r[14]}} & data_o[14]
            | {32{rd_en_r[15]}} & data_o[15];


uart inst_uart0
(
    .clk     (clk),
    .rst_n   (rst_n),

    .waddr_i (waddr[7:0]),
    .data_i  (din),
    .sel_i   (sel),
    .we_i    (we_en[0]),
    .raddr_i (raddr),
    .rd_i    (rd_en[0]),
    .data_o  (data_o[0]),

    .tx_pin  (uart0_tx),
    .rx_pin  (uart0_rx)
);

uart inst_uart1
(
    .clk     (clk),
    .rst_n   (rst_n),

    .waddr_i (waddr),
    .data_i  (din),
    .sel_i   (sel),
    .we_i    (we_en[1]),
    .raddr_i (raddr),
    .rd_i    (rd_en[1]),
    .data_o  (data_o[1]),

    .tx_pin  (uart1_tx),
    .rx_pin  (uart1_rx)
);

spi inst_spi0
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[2]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[2]),
    .data_o   (data_o[2]),

    .spi_mosi (spi0_mosi),
    .spi_miso (spi0_miso),
    .spi_cs   (spi0_cs  ),
    .spi_clk  (spi0_clk )
);

spi inst_spi1
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[3]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[3]),
    .data_o   (data_o[3]),

    .spi_mosi (spi1_mosi),
    .spi_miso (spi1_miso),
    .spi_cs   (spi1_cs  ),
    .spi_clk  (spi1_clk )
);

gpio inst_gpio
(
    .clk           (clk),
    .rst_n         (rst_n),

    .waddr_i       (waddr),
    .data_i        (din),
    .sel_i         (sel),
    .we_i          (we_en[4]),
    .raddr_i       (raddr),
    .rd_i          (rd_en[4]),
    .data_o        (data_o[4]),

    .gpio_oe       (gpio_oe ),
    .gpio_out      (gpio_out),
    .gpio_in       (gpio_in )
);

fpioa inst_fpioa
(
    .clk      (clk),
    .rst_n    (rst_n),

    .waddr_i  (waddr),
    .data_i   (din),
    .sel_i    (sel),
    .we_i     (we_en[15]),
    .raddr_i  (raddr),
    .rd_i     (rd_en[15]),
    .data_o   (data_o[15]),

    .SPI0_SCK  (spi0_clk),
    .SPI0_MOSI (spi0_mosi),
    .SPI0_MISO (spi0_miso),
    .SPI0_CS   (spi0_cs),
    .SPI1_SCK  (spi1_clk),
    .SPI1_MOSI (spi1_mosi),
    .SPI1_MISO (spi1_miso),
    .SPI1_CS   (spi1_cs),
    .UART0_TX  (uart0_tx),
    .UART0_RX  (uart0_rx),
    .UART1_TX  (uart1_tx),
    .UART1_RX  (uart1_rx),

    .gpio_oe  (gpio_oe ),
    .gpio_out (gpio_out),
    .gpio_in  (gpio_in ),

    .fpioa    (fpioa)
);

endmodule