data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:53: Unsupported: Ignoring delay on this delayed statement.\n#1000;  \n^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:86: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'A\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A & B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:86: Operator AND expects 5 bits on the RHS, but RHS\'s VARREF \'B\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A & B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:88: Operator OR expects 5 bits on the LHS, but LHS\'s VARREF \'A\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A | B;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/493851698/verilog/rtl/alu_xor_4.v:88: Operator OR expects 5 bits on the RHS, but RHS\'s VARREF \'B\' generates 4 bits.\n                                                                               : ... In instance alu_xor_4.alu_4_2\nALU_Result = A | B;\n               ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_4(
  input [3:0] A,B,
input [1:0] ALU_Sel,
  output [3:0] ALU_Out,
output CarryOut
);
  reg [4:0] ALU_Result;

  assign ALU_Out = ALU_Result[3:0];
  assign CarryOut = ALU_Result[4];

always @(*)
begin
case(ALU_Sel)
2'b00:
ALU_Result = A + B ;
2'b01:
ALU_Result = A - B ;
2'b10:
ALU_Result = A & B;
2'b11:
ALU_Result = A | B;

default: ALU_Result = A + B ;
endcase
end

endmodule
module alu_4(
  input [3:0] A,B,
input [1:0] ALU_Sel,
  output [3:0] ALU_Out,
output CarryOut
);

  reg [4:0] ALU_Result;

  assign ALU_Out = ALU_Result[3:0];
  assign CarryOut = ALU_Result[4];

always @(*)
begin
case(ALU_Sel)
2'b00:
ALU_Result = A + B ;
2'b01:
ALU_Result = A - B ;
2'b10:
ALU_Result = A & B;
2'b11:
ALU_Result = A | B;

default: ALU_Result = A + B ;
endcase
end

endmodule