data/full_repos/permissive/515100461/sequential/memory.v
1: b"%Error: data/full_repos/permissive/515100461/sequential/memory.v:7: Input/output/inout does not appear in port list: 'data_mem'\noutput reg[0:512] data_mem = 0; \n                  ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module memory(clk,icode,valE,valP,valA,valM);
input clk;
input [3:0] icode;
input [63:0] valE,valP,valA;

output reg[63:0] valM;
output reg[0:512] data_mem = 0;

always@(*)
begin
   case(icode)
  
  4'b0100 :
  begin
     data_mem[valE] = valA;
  end

  4'b0101 :
  begin
      valM = data_mem[valE];
  end

   4'b1000 :
   begin
      data_mem[valE] = valP;
   end

   4'b1001 :
   begin
       valM = data_mem[valA];
   end

   4'b1010:
   begin
      data_mem[valE] = valA;
   end

   4'b1011:
   begin
      valM = data_mem[valA];
   end
  endcase
end
endmodule
module memory(clk,icode,valE,valP,valA,valM);

input clk;
input [3:0] icode;
input [63:0] valE,valP,valA;

output reg[63:0] valM;
output reg[0:512] data_mem = 0;

always@(*)
begin
   case(icode)
  
  4'b0100 :
  begin
     data_mem[valE] = valA;
  end

  4'b0101 :
  begin
      valM = data_mem[valE];
  end

   4'b1000 :
   begin
      data_mem[valE] = valP;
   end

   4'b1001 :
   begin
       valM = data_mem[valA];
   end

   4'b1010:
   begin
      data_mem[valE] = valA;
   end

   4'b1011:
   begin
      valM = data_mem[valA];
   end
  endcase
end
endmodule