data/full_repos/permissive/479997390/src/WB.v
data/verilator_xmls/2ac60994-8623-4f3d-b0a9-7aeffa24ad72.xml
module WB (
  DataOut, ALUOut, MemToReg, WriteRegAddrIn, RegWriteIn,
  RegWriteOut, WriteRegAddrOut, WriteRegData
);

  input [31:0] DataOut, ALUOut;
  input MemToReg, RegWriteIn;
  input [4:0] WriteRegAddrIn;
  output RegWriteOut;
  output [4:0] WriteRegAddrOut;
  output [31:0] WriteRegData;

  assign WriteRegData = MemToReg ? DataOut : ALUOut;
  assign WriteRegAddrOut = WriteRegAddrIn;
  assign RegWriteOut = RegWriteIn;
endmodule
module WB (
  DataOut, ALUOut, MemToReg, WriteRegAddrIn, RegWriteIn,
  RegWriteOut, WriteRegAddrOut, WriteRegData
);


  input [31:0] DataOut, ALUOut;
  input MemToReg, RegWriteIn;
  input [4:0] WriteRegAddrIn;
  output RegWriteOut;
  output [4:0] WriteRegAddrOut;
  output [31:0] WriteRegData;

  assign WriteRegData = MemToReg ? DataOut : ALUOut;
  assign WriteRegAddrOut = WriteRegAddrIn;
  assign RegWriteOut = RegWriteIn;
endmodule