data/full_repos/permissive/423547971/FPGA Projects/Traffic_Controller_Basys3/state_machine.v
1: b'%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3/state_machine.v\n%Error: Exiting due to 3 error(s)\n'
module state_machine(
    input reset,
    input clk_1Hz,
    output reg [2:0] main_st,
    output reg [2:0] cross_st
    );
    

    parameter main_green_cross_red  = 2'b00;
    parameter main_yellow_cross_red = 2'b01;
    parameter main_red_cross_green  = 2'b10;
    parameter main_red_cross_yellow = 2'b11;
    

    reg [1:0] state_reg;
    

    reg [4:0] light_counter = 0;




    

    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            state_reg <= main_green_cross_red;
        else
            case(state_reg)
                main_green_cross_red  : if(light_counter == 15)     state_reg <= main_yellow_cross_red;
                main_yellow_cross_red : if(light_counter == 18)     state_reg <= main_red_cross_green;
                main_red_cross_green  : if(light_counter == 28)     state_reg <= main_red_cross_yellow;
                main_red_cross_yellow : if(light_counter == 31)     state_reg <= main_green_cross_red;
                default : state_reg <= main_green_cross_red; 
            endcase
    end
    

    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            light_counter <= 0;
        else
            if(light_counter == 31) 
                light_counter <= 0;
            else
                light_counter <= light_counter + 1;
    end
    
    always @(posedge clk_1Hz) begin
        case(state_reg) 
            main_green_cross_red  : begin
                                        main_st  = 3'b001;
                                        cross_st = 3'b100;
                                    end
            main_yellow_cross_red : begin
                                        main_st  = 3'b010;
                                        cross_st = 3'b100;
                                    end
            main_red_cross_green  : begin
                                        main_st  = 3'b100;
                                        cross_st = 3'b001;
                                    end
            main_red_cross_yellow : begin
                                        main_st  = 3'b100;
                                        cross_st = 3'b010;
                                    end
        endcase
    end
    
endmodule
module state_machine(
    input reset,
    input clk_1Hz,
    output reg [2:0] main_st,
    output reg [2:0] cross_st
    );

    

    parameter main_green_cross_red  = 2'b00;
    parameter main_yellow_cross_red = 2'b01;
    parameter main_red_cross_green  = 2'b10;
    parameter main_red_cross_yellow = 2'b11;
    

    reg [1:0] state_reg;
    

    reg [4:0] light_counter = 0;




    

    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            state_reg <= main_green_cross_red;
        else
            case(state_reg)
                main_green_cross_red  : if(light_counter == 15)     state_reg <= main_yellow_cross_red;
                main_yellow_cross_red : if(light_counter == 18)     state_reg <= main_red_cross_green;
                main_red_cross_green  : if(light_counter == 28)     state_reg <= main_red_cross_yellow;
                main_red_cross_yellow : if(light_counter == 31)     state_reg <= main_green_cross_red;
                default : state_reg <= main_green_cross_red; 
            endcase
    end
    

    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            light_counter <= 0;
        else
            if(light_counter == 31) 
                light_counter <= 0;
            else
                light_counter <= light_counter + 1;
    end
    
    always @(posedge clk_1Hz) begin
        case(state_reg) 
            main_green_cross_red  : begin
                                        main_st  = 3'b001;
                                        cross_st = 3'b100;
                                    end
            main_yellow_cross_red : begin
                                        main_st  = 3'b010;
                                        cross_st = 3'b100;
                                    end
            main_red_cross_green  : begin
                                        main_st  = 3'b100;
                                        cross_st = 3'b001;
                                    end
            main_red_cross_yellow : begin
                                        main_st  = 3'b100;
                                        cross_st = 3'b010;
                                    end
        endcase
    end
    
endmodule