data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_serialdp/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_serialdp,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_serialdp/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module fsm_output (
    input wire [2:0] state,
    input wire [9:0] data,
    output reg [7:0] out_byte,
    output reg done
);

  parameter STATE_STOP = 3'b011;

  always @(*) begin
    case (state)
      STATE_STOP: done = ^data[8:0] == data[9];
      default: done = 1'b0;
    endcase

    out_byte = data[7:0];
  end
endmodule
module fsm_output (
    input wire [2:0] state,
    input wire [9:0] data,
    output reg [7:0] out_byte,
    output reg done
);


  parameter STATE_STOP = 3'b011;

  always @(*) begin
    case (state)
      STATE_STOP: done = ^data[8:0] == data[9];
      default: done = 1'b0;
    endcase

    out_byte = data[7:0];
  end
endmodule