data/full_repos/permissive/510956372/src/reg_4bit.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/510956372/src/reg_4bit.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                         : ... In instance reg_4bit\n      q = d;\n      ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module reg_4bit ( input ld,
                  input clk,
                 input [3:0] d,
                 output [3:0] q);
  always @(posedge clk) begin
    if (ld) begin
      q = d;
    end else begin end
  end
endmodule
module reg_4bit ( input ld,
                  input clk,
                 input [3:0] d,
                 output [3:0] q);

  always @(posedge clk) begin
    if (ld) begin
      q = d;
    end else begin end
  end
endmodule