data/full_repos/permissive/515613199/even.v
1: b'%Error: data/full_repos/permissive/515613199/even.v:1: Cannot find include file: reg_size.v\n`include "reg_size.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.sv\n             reg_size.v\n             reg_size.v.v\n             reg_size.v.sv\n             obj_dir/reg_size.v\n             obj_dir/reg_size.v.v\n             obj_dir/reg_size.v.sv\n%Error: data/full_repos/permissive/515613199/even.v:5: Define or directive not defined: \'`SIZE\'\n input [`SIZE-1:0] N,  \n        ^~~~~\n%Error: data/full_repos/permissive/515613199/even.v:11: Define or directive not defined: \'`SIZE\'\n wire[`SIZE-2:0] divN_2;\n      ^~~~~\n%Error: data/full_repos/permissive/515613199/even.v:12: Define or directive not defined: \'`SIZE\'\n reg [`SIZE-2:0] counter;\n      ^~~~~\n%Error: data/full_repos/permissive/515613199/even.v:16: Define or directive not defined: \'`SIZE\'\n assign divN_2 = N[`SIZE-1:1];\n                   ^~~~~\n%Error: Exiting due to 5 error(s)\n'
module even_divider(
    input clk,
	input [`SIZE-1:0] N,
	input reset,
	input enable,
    output out
    );

	wire[`SIZE-2:0] divN_2;
	reg [`SIZE-2:0] counter;
	reg out_count;

	assign out 	  = (enable) ? out_count : 1'hz;
	assign divN_2 = N[`SIZE-1:1];


	always @(posedge reset or posedge clk)
	begin
		if(reset)
		begin
			counter   <= 1;
			out_count <= 1'b0;
		end
		else if(enable)
		begin
			if(counter == 1)
			begin
				counter <= divN_2;
				out_count <= ~out_count;
			end
			else
			begin
				counter <= counter-1;
			end
		end
	end

endmodule
module even_divider(
    input clk,
	input [`SIZE-1:0] N,
	input reset,
	input enable,
    output out
    );


	wire[`SIZE-2:0] divN_2;
	reg [`SIZE-2:0] counter;
	reg out_count;

	assign out 	  = (enable) ? out_count : 1'hz;
	assign divN_2 = N[`SIZE-1:1];


	always @(posedge reset or posedge clk)
	begin
		if(reset)
		begin
			counter   <= 1;
			out_count <= 1'b0;
		end
		else if(enable)
		begin
			if(counter == 1)
			begin
				counter <= divN_2;
				out_count <= ~out_count;
			end
			else
			begin
				counter <= counter-1;
			end
		end
	end

endmodule