data/full_repos/permissive/515135468/verilog/rtl/spm.v
data/verilator_xmls/1aeea747-0eaa-47dd-b534-510811c95339.xml
module TCMP (
    input wire  clk, 
    input wire  rst,
    input wire  a, 
    output reg  s
);
  
    reg z;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            s <= 1'b0;
            z <= 1'b0;
        end
        else begin
            z <= a | z;
            s <= a ^ z;
        end
    end

endmodule
module TCMP (
    input wire  clk, 
    input wire  rst,
    input wire  a, 
    output reg  s
);

  
    reg z;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            s <= 1'b0;
            z <= 1'b0;
        end
        else begin
            z <= a | z;
            s <= a ^ z;
        end
    end

endmodule