data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/01_Basic_Gates/15_3-bit_population_count.v
data/verilator_xmls/a7af28e5-393d-47c8-8063-3204820fb2a0.xml
module top_module( 
    input [2:0] in,
    output [1:0] out
);
    
    assign out[1] = in[0] & in[1] | in[0] & in[2] | in[1] & in[2];
    assign out[0] = in[0] ^ in[1] ^ in[2];

endmodule
module top_module( 
    input [2:0] in,
    output [1:0] out
);

    
    assign out[1] = in[0] & in[1] | in[0] & in[2] | in[1] & in[2];
    assign out[0] = in[0] ^ in[1] ^ in[2];

endmodule