data/full_repos/permissive/467899092/design.sv
data/verilator_xmls/35fe8e43-a564-4cfc-a616-ba407286fbad.xml
module my_xor(output myout, input ina, input inb);
  wire x, y, not_ina, not_inb;
  and(x, ina, not_inb);
  and(y, not_ina, inb);
  or(myout, x, y);
  not(not_ina, ina);
  not(not_inb, inb);
endmodule
module my_xor(output myout, input ina, input inb);

  wire x, y, not_ina, not_inb;
  and(x, ina, not_inb);
  and(y, not_ina, inb);
  or(myout, x, y);
  not(not_ina, ina);
  not(not_inb, inb);
endmodule