data/full_repos/permissive/470590146/core/if_stage.v
data/verilator_xmls/4d246497-4c4a-43e7-8330-721c9c7a6316.xml
module if_stage (
	 input clk
	,input rst_n


    ,input             ds_ready
    ,output reg        fs_valid

	,input      [31:0] pre_pc
	,input 		       pc_src

	,output reg [31:0] fs_pc
    ,output     [31:0] fs_inst

    ,output        inst_ram_ren
	,output [31:0] inst_ram_raddr
    ,input  [31:0] inst_ram_rdata
);

wire [31:0] pc;
wire [31:0] n_pc;


assign n_pc = fs_pc + 32'd4;
assign pc   = pc_src == 1'b1 ? pre_pc : n_pc;


wire fs_ready;
wire fs_valid_pre;

wire fs_ok_go;

assign fs_valid_pre = rst_n;
assign fs_ready     = !fs_valid_pre || ds_ready;
always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        fs_valid <= 0;
    end
    else if (fs_ready) begin
        fs_valid <= fs_valid_pre;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        fs_pc <= 0;
    end
    else if (fs_valid_pre && fs_ready) begin

        fs_pc <= pc;
    end
end

assign inst_ram_ren   = fs_valid_pre && fs_ready;
assign inst_ram_raddr = pc;
assign fs_inst        = inst_ram_rdata;

endmodule
module if_stage (
	 input clk
	,input rst_n


    ,input             ds_ready
    ,output reg        fs_valid

	,input      [31:0] pre_pc
	,input 		       pc_src

	,output reg [31:0] fs_pc
    ,output     [31:0] fs_inst

    ,output        inst_ram_ren
	,output [31:0] inst_ram_raddr
    ,input  [31:0] inst_ram_rdata
);


wire [31:0] pc;
wire [31:0] n_pc;


assign n_pc = fs_pc + 32'd4;
assign pc   = pc_src == 1'b1 ? pre_pc : n_pc;


wire fs_ready;
wire fs_valid_pre;

wire fs_ok_go;

assign fs_valid_pre = rst_n;
assign fs_ready     = !fs_valid_pre || ds_ready;
always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        fs_valid <= 0;
    end
    else if (fs_ready) begin
        fs_valid <= fs_valid_pre;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin

        fs_pc <= 0;
    end
    else if (fs_valid_pre && fs_ready) begin

        fs_pc <= pc;
    end
end

assign inst_ram_ren   = fs_valid_pre && fs_ready;
assign inst_ram_raddr = pc;
assign fs_inst        = inst_ram_rdata;

endmodule