data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ControlUnit(op,func,rs,rt,mrn,mm2reg,mwreg,ern,em2reg,ewreg,
                   aluc,wreg,m2reg,wmem,aluimm,fwda,fwdb,wpcir,regrt);
    input [5:0] op,func;
    input [4:0] rs,rt;
    input [4:0] mrn;
    input mm2reg,mwreg;
    input [4:0] ern;
    input em2reg,ewreg;
    output reg [3:0] aluc;
    output reg wreg, m2reg, wmem, aluimm, regrt;
    
    output reg [1:0] fwda, fwdb;
    output reg wpcir;
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end
    always @ (op,func) begin
        if(op == 0) begin
            case(func)
                32: aluc <= 2;
                34: aluc <= 6;
                36: aluc <= 0;
                37: aluc <= 1;
                39: aluc <= 12;
             endcase
             wreg <= 1;
             m2reg <= 0;
             wmem <= 0;
             aluimm <= 0;
             regrt <= 1;
        end
        if(op == 6'b100011) begin
            aluc <= 2;
            wreg <= 1;
            m2reg <= 1;
            wmem <= 0;
            aluimm <= 1;
            regrt <= 0;
        end
        if(op == 6'b101011) begin
            aluc <= 2;
            wreg <= 0;
            m2reg <= 0;
            wmem <= 1;
            aluimm <= 1;
            regrt <= 1;
        end
        if (op == 6'b000100)
        begin
            aluc <= 6;
            wreg <= 0;
            m2reg <= 0;
            wmem <= 0;
            aluimm <= 0;
            regrt <= 1;
        end

    end
    


    always @ (rs or rt) begin

        if (ewreg && (ern != 0) && !em2reg) begin
            assign fwda = 2'b01;
        end 
        else if (mwreg && (mrn != 0) && !mm2reg) begin
            assign fwda = 2'b10;
        end
        else if (mwreg && (mrn != 0) && mm2reg) begin
            assign fwda = 2'b11;
        end
        else begin
            assign fwda = 2'b00;
        end
        

        if (ewreg && (ern != 0) && !em2reg) begin
            assign fwdb = 2'b01;
        end 
        else if (mwreg && (mrn != 0) && !mm2reg) begin
            assign fwdb = 2'b10;
        end 
        else if (mwreg && (mrn != 0) && mm2reg) begin
            assign fwdb = 2'b11;
        end
        else begin
            assign fwdb = 2'b00;
        end
    end
endmodule
module ControlUnit(op,func,rs,rt,mrn,mm2reg,mwreg,ern,em2reg,ewreg,
                   aluc,wreg,m2reg,wmem,aluimm,fwda,fwdb,wpcir,regrt);

    input [5:0] op,func;
    input [4:0] rs,rt;
    input [4:0] mrn;
    input mm2reg,mwreg;
    input [4:0] ern;
    input em2reg,ewreg;
    output reg [3:0] aluc;
    output reg wreg, m2reg, wmem, aluimm, regrt;
    
    output reg [1:0] fwda, fwdb;
    output reg wpcir;
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end
    always @ (op,func) begin
        if(op == 0) begin
            case(func)
                32: aluc <= 2;
                34: aluc <= 6;
                36: aluc <= 0;
                37: aluc <= 1;
                39: aluc <= 12;
             endcase
             wreg <= 1;
             m2reg <= 0;
             wmem <= 0;
             aluimm <= 0;
             regrt <= 1;
        end
        if(op == 6'b100011) begin
            aluc <= 2;
            wreg <= 1;
            m2reg <= 1;
            wmem <= 0;
            aluimm <= 1;
            regrt <= 0;
        end
        if(op == 6'b101011) begin
            aluc <= 2;
            wreg <= 0;
            m2reg <= 0;
            wmem <= 1;
            aluimm <= 1;
            regrt <= 1;
        end
        if (op == 6'b000100)
        begin
            aluc <= 6;
            wreg <= 0;
            m2reg <= 0;
            wmem <= 0;
            aluimm <= 0;
            regrt <= 1;
        end

    end
    


    always @ (rs or rt) begin

        if (ewreg && (ern != 0) && !em2reg) begin
            assign fwda = 2'b01;
        end 
        else if (mwreg && (mrn != 0) && !mm2reg) begin
            assign fwda = 2'b10;
        end
        else if (mwreg && (mrn != 0) && mm2reg) begin
            assign fwda = 2'b11;
        end
        else begin
            assign fwda = 2'b00;
        end
        

        if (ewreg && (ern != 0) && !em2reg) begin
            assign fwdb = 2'b01;
        end 
        else if (mwreg && (mrn != 0) && !mm2reg) begin
            assign fwdb = 2'b10;
        end 
        else if (mwreg && (mrn != 0) && mm2reg) begin
            assign fwdb = 2'b11;
        end
        else begin
            assign fwdb = 2'b00;
        end
    end
endmodule