data/full_repos/permissive/486598419/6.1/extend_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/extend_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/486598419/6.1/extend_tb.v:27: Cannot find file containing module: \'extend\'\n   extend uut (.a(a),.sext(sext),.b(b));\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/extend\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/extend.v\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/extend.sv\n             extend\n             extend.v\n             extend.sv\n             obj_dir/extend\n             obj_dir/extend.v\n             obj_dir/extend.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module extend_tb;
   reg [15:0] a;
   reg sext;
   wire [31:0] b;
   extend uut (.a(a),.sext(sext),.b(b));
   initial
   begin
      a=0;
      sext=0;
      #100;
      sext=1;
      a=16'h0000;
      #100;
      sext=0;
      a=16'h8000;
      #100;
      sext=1;
      a=16'h8000;
      #100;
      sext=0;
      a=16'hffff;
      #100;
      sext=1;
      a=16'hffff;
      #100;
   end
endmodule
module extend_tb;

   reg [15:0] a;
   reg sext;
   wire [31:0] b;
   extend uut (.a(a),.sext(sext),.b(b));
   initial
   begin
      a=0;
      sext=0;
      #100;
      sext=1;
      a=16'h0000;
      #100;
      sext=0;
      a=16'h8000;
      #100;
      sext=1;
      a=16'h8000;
      #100;
      sext=0;
      a=16'hffff;
      #100;
      sext=1;
      a=16'hffff;
      #100;
   end
endmodule