data/full_repos/permissive/515613617/lift_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515613617/lift_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk =~ clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515613617/lift_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515613617/lift_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#600\n^\n%Warning-STMTDLY: data/full_repos/permissive/515613617/lift_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#400\n^\n%Warning-STMTDLY: data/full_repos/permissive/515613617/lift_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#600\n^\n%Error: data/full_repos/permissive/515613617/lift_tb.v:9: Cannot find file containing module: \'lift\'\nlift dut(clk,reset,req_floor,stop,door,Up,Down,y);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/515613617,data/full_repos/permissive/515613617/lift\n             data/full_repos/permissive/515613617,data/full_repos/permissive/515613617/lift.v\n             data/full_repos/permissive/515613617,data/full_repos/permissive/515613617/lift.sv\n             lift\n             lift.v\n             lift.sv\n             obj_dir/lift\n             obj_dir/lift.v\n             obj_dir/lift.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lift_Tb();
reg clk,reset;
reg [5:0] req_floor;
wire [1:0] stop,door,Up,Down; 
wire [5:0] y;

lift dut(clk,reset,req_floor,stop,door,Up,Down,y);

initial begin
clk=0;
forever #5 clk =~ clk;
end
initial begin 
reset = 1;
#10;
reset=0;
req_floor=6'd2;
#600
req_floor=6'd3;
#400
req_floor=6'd25;
#600
req_floor=6'd10;
end
endmodule
module lift_Tb();

reg clk,reset;
reg [5:0] req_floor;
wire [1:0] stop,door,Up,Down; 
wire [5:0] y;

lift dut(clk,reset,req_floor,stop,door,Up,Down,y);

initial begin
clk=0;
forever #5 clk =~ clk;
end
initial begin 
reset = 1;
#10;
reset=0;
req_floor=6'd2;
#600
req_floor=6'd3;
#400
req_floor=6'd25;
#600
req_floor=6'd10;
end
endmodule