data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:53: Unsupported: Ignoring delay on this delayed statement.\n#50 clk =1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:54: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:113: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:123: Unsupported: Ignoring delay on this delayed statement.\n#1000 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:133: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:144: Unsupported: wait statements\nwait(vld);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:146: Unsupported: Ignoring delay on this delayed statement.\n#50000;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:152: Unsupported or unknown PLI call: $monitor\n$monitor ("mmul_cnt_state = %d", iecc_core.iauc_wrap.iauc_mmul.iauc_mmul_comp.cnt);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:164: Unsupported or unknown PLI call: $shm_open\n$shm_open ("my_waves");\n^~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:165: Unsupported or unknown PLI call: $shm_probe\n$shm_probe (tb_ex_sim,"ACM");\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:166: Unsupported or unknown PLI call: $recordfile\n$recordfile("testsample.trn");\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/tb_ex_sim.sv:167: Unsupported or unknown PLI call: $recordvars\n$recordvars();\n^~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ex_sim;



parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;



reg               clk;
reg               rst;


reg [3*WIDTH-1:0] din;
reg [2:0]         mode; 
reg               start;
wire [WIDTH-1:0]  dout;
wire [1:0]        status;

reg [WIDTH-1:0]   test_num;

ecc_core
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .test_num(test_num)
     );

wire              vld;
assign            vld = status[1] == 1'b1;


always begin
clk = 0;
#50 clk =1;
#50;
end

initial begin




rst = 1'b1;
din[WIDTH-1:0] = 256'he6db6867583030db3594c1a424b15f7c726624ec26b3353b10a903a6d0ab1c4c;
din[2*WIDTH-1: WIDTH] = 256'ha546e36bf0527c9d3b16154b82465edd62144c0ac1fc5a18506a2244ba449ac4;
din[3*WIDTH-1: 2*WIDTH] = 0;
mode = 3'b110;
start = 1'b0;
test_num = 0;



#100 rst = 1'b0;
din[WIDTH-1:0] = 256'he6db6867583030db3594c1a424b15f7c726624ec26b3353b10a903a6d0ab1c4c;
din[2*WIDTH-1: WIDTH] = 256'ha546e36bf0527c9d3b16154b82465edd62144c0ac1fc5a18506a2244ba449ac4;
din[3*WIDTH-1: 2*WIDTH] = 0;
mode = 3'b110;
start = 1'b1;
test_num = 0;



#1000 rst = 1'b0;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b0;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;



#100 rst = 1'b0;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b0;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;




wait(vld);

#50000;
$finish;
end

initial begin

$monitor ("mmul_cnt_state = %d", iecc_core.iauc_wrap.iauc_mmul.iauc_mmul_comp.cnt);
end
          
always @(posedge clk)
    begin
    if (status == 2'b10)
        $display (" Output: %h", dout);
    end



initial begin
$shm_open ("my_waves");
$shm_probe (tb_ex_sim,"ACM");
$recordfile("testsample.trn");
$recordvars();
end


endmodule
module tb_ex_sim;




parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;



reg               clk;
reg               rst;


reg [3*WIDTH-1:0] din;
reg [2:0]         mode; 
reg               start;
wire [WIDTH-1:0]  dout;
wire [1:0]        status;

reg [WIDTH-1:0]   test_num;

ecc_core
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .test_num(test_num)
     );

wire              vld;
assign            vld = status[1] == 1'b1;


always begin
clk = 0;
#50 clk =1;
#50;
end

initial begin




rst = 1'b1;
din[WIDTH-1:0] = 256'he6db6867583030db3594c1a424b15f7c726624ec26b3353b10a903a6d0ab1c4c;
din[2*WIDTH-1: WIDTH] = 256'ha546e36bf0527c9d3b16154b82465edd62144c0ac1fc5a18506a2244ba449ac4;
din[3*WIDTH-1: 2*WIDTH] = 0;
mode = 3'b110;
start = 1'b0;
test_num = 0;



#100 rst = 1'b0;
din[WIDTH-1:0] = 256'he6db6867583030db3594c1a424b15f7c726624ec26b3353b10a903a6d0ab1c4c;
din[2*WIDTH-1: WIDTH] = 256'ha546e36bf0527c9d3b16154b82465edd62144c0ac1fc5a18506a2244ba449ac4;
din[3*WIDTH-1: 2*WIDTH] = 0;
mode = 3'b110;
start = 1'b1;
test_num = 0;



#1000 rst = 1'b0;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b0;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;



#100 rst = 1'b0;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b0;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;




wait(vld);

#50000;
$finish;
end

initial begin

$monitor ("mmul_cnt_state = %d", iecc_core.iauc_wrap.iauc_mmul.iauc_mmul_comp.cnt);
end
          
always @(posedge clk)
    begin
    if (status == 2'b10)
        $display (" Output: %h", dout);
    end



initial begin
$shm_open ("my_waves");
$shm_probe (tb_ex_sim,"ACM");
$recordfile("testsample.trn");
$recordvars();
end


endmodule