data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:73: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,1) iffxkclkx1(clk,rst,din,din3);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclkx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclkx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclkx.sv\n             ffxkclkx\n             ffxkclkx.v\n             ffxkclkx.sv\n             obj_dir/ffxkclkx\n             obj_dir/ffxkclkx.v\n             obj_dir/ffxkclkx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:74: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,3) iffxkclkx2(clk,rst,mode,mode3);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:75: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,1) iffxkclkx3(clk,rst,start,start3);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:76: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,1) iffxkclkx4(clk,rst,dout1,dout3);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:77: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,2) iffxkclkx5(clk,rst,status3,status);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:78: Cannot find file containing module: 'ffxkclkx'\nffxkclkx #(3,1) iffxkclkx6(clk,rst,test_num,test_num3);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:87: Cannot find file containing module: 'rtldbgsipo1'\nrtldbgsipo1 \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:98: Cannot find file containing module: 'rtldbgsipo1'\nrtldbgsipo1 \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:109: Cannot find file containing module: 'rtldbgsipo1'\nrtldbgsipo1 \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_top.v:123: Cannot find file containing module: 'ecc_core'\necc_core iecc_core\n^~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module ecc_top
    (
     clk,
     rst,

     din,
     mode,
     start,
     dout,
     status,

     test_num
     );




`define             RTL_SIMULATION
`define             RWSAMECLK

parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;
parameter           CURWID  = 255;
parameter           OPWID   = 4;




input               clk;
input               rst;


input               din;
input [2:0]         mode;
input               start;
output              dout;
output [1:0]        status;

input               test_num;








wire               din3;
wire [2:0]         mode3;
wire               start3;
wire              dout3;
wire              dout1;
wire [1:0]        status3;

wire               test_num3;

ffxkclkx #(3,1) iffxkclkx1(clk,rst,din,din3);
ffxkclkx #(3,3) iffxkclkx2(clk,rst,mode,mode3);
ffxkclkx #(3,1) iffxkclkx3(clk,rst,start,start3);
ffxkclkx #(3,1) iffxkclkx4(clk,rst,dout1,dout3);
ffxkclkx #(3,2) iffxkclkx5(clk,rst,status3,status);
ffxkclkx #(3,1) iffxkclkx6(clk,rst,test_num,test_num3);

assign             dout = dout3;


wire [3*WIDTH-1:0] dinp;
wire [WIDTH-1:0] doutp;
wire [WIDTH-1:0] test_nump;

rtldbgsipo1
    #(3*WIDTH,1)
    irtldbgsipo1
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(din3),
         .odat(dinp)
         );

rtldbgsipo1
    #(WIDTH,1)
    irtldbgsipo2
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(test_num3),
         .odat(test_nump)
         );

rtldbgsipo1
    #(1,WIDTH)
    irtldbgsipo3
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(doutp),
         .odat(dout1)
         );




ecc_core iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(dinp),
     .mode(mode3),
     .start(start),
     .dout(doutp),
     .status(status3),

     .test_num(test_nump)
     );

endmodule
module ecc_top
    (
     clk,
     rst,

     din,
     mode,
     start,
     dout,
     status,

     test_num
     );





`define             RTL_SIMULATION
`define             RWSAMECLK

parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;
parameter           CURWID  = 255;
parameter           OPWID   = 4;




input               clk;
input               rst;


input               din;
input [2:0]         mode;
input               start;
output              dout;
output [1:0]        status;

input               test_num;








wire               din3;
wire [2:0]         mode3;
wire               start3;
wire              dout3;
wire              dout1;
wire [1:0]        status3;

wire               test_num3;

ffxkclkx #(3,1) iffxkclkx1(clk,rst,din,din3);
ffxkclkx #(3,3) iffxkclkx2(clk,rst,mode,mode3);
ffxkclkx #(3,1) iffxkclkx3(clk,rst,start,start3);
ffxkclkx #(3,1) iffxkclkx4(clk,rst,dout1,dout3);
ffxkclkx #(3,2) iffxkclkx5(clk,rst,status3,status);
ffxkclkx #(3,1) iffxkclkx6(clk,rst,test_num,test_num3);

assign             dout = dout3;


wire [3*WIDTH-1:0] dinp;
wire [WIDTH-1:0] doutp;
wire [WIDTH-1:0] test_nump;

rtldbgsipo1
    #(3*WIDTH,1)
    irtldbgsipo1
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(din3),
         .odat(dinp)
         );

rtldbgsipo1
    #(WIDTH,1)
    irtldbgsipo2
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(test_num3),
         .odat(test_nump)
         );

rtldbgsipo1
    #(1,WIDTH)
    irtldbgsipo3
        (
         .clk(clk),
         .rst(rst),
         .iena(1'b1),
         .idat(doutp),
         .odat(dout1)
         );




ecc_core iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(dinp),
     .mode(mode3),
     .start(start),
     .dout(doutp),
     .status(status3),

     .test_num(test_nump)
     );

endmodule