data/full_repos/permissive/514437299/digital/rtl/rng.v
1: b"%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:125: Cannot find file containing module: 'INVLONG_OSC23'\n  INVLONG_OSC23 U_RNG_OSC(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23.sv\n             INVLONG_OSC23\n             INVLONG_OSC23.v\n             INVLONG_OSC23.sv\n             obj_dir/INVLONG_OSC23\n             obj_dir/INVLONG_OSC23.v\n             obj_dir/INVLONG_OSC23.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:131: Cannot find file containing module: 'INVD2'\n  INVD2 U_RNG_OSC_DRV(\n  ^~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:135: Cannot find file containing module: 'clkdiv'\n  clkdiv U_CLKDIV_RNG(\n  ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module casr37(input  wire        clk,
              input  wire        rst_n,
              input  wire        i_en,
              input  wire        i_ptb,
              input  wire        i_ptb_valid,
              input  wire        i_si,
              input  wire        i_sr_valid,
              input  wire [36:0] i_state,
              input  wire        i_load_state,
              output wire        o_so,
              output reg  [36:0] o_state);

  wire [36:0] nxt_state;

  integer idx;

  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      o_state <= 37'b0;
    else
      if (i_en)
        for (idx = 0; idx < 37; idx = idx+1)
          o_state[idx] <= nxt_state[idx];
      else begin
        if (i_load_state)
          o_state <= i_state;
        else if (i_sr_valid)
          o_state <= {o_state[35:0], i_si};
      end

  genvar  i;

  generate

    for (i = 1; i <= 37; i = i+1) begin : casr_blk
      wire left  = (i > 1)  ? o_state[37-i+1] : i_ptb & i_ptb_valid;
      wire right = (i < 37) ? o_state[37-i-1] : i_ptb & i_ptb_valid;
      assign nxt_state[37-i] = (i == 9) ? left ^ right ^ o_state[37-9] : left ^ right;
    end
  endgenerate

  assign o_so = o_state[36];

endmodule
module casr37(input  wire        clk,
              input  wire        rst_n,
              input  wire        i_en,
              input  wire        i_ptb,
              input  wire        i_ptb_valid,
              input  wire        i_si,
              input  wire        i_sr_valid,
              input  wire [36:0] i_state,
              input  wire        i_load_state,
              output wire        o_so,
              output reg  [36:0] o_state);


  wire [36:0] nxt_state;

  integer idx;

  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      o_state <= 37'b0;
    else
      if (i_en)
        for (idx = 0; idx < 37; idx = idx+1)
          o_state[idx] <= nxt_state[idx];
      else begin
        if (i_load_state)
          o_state <= i_state;
        else if (i_sr_valid)
          o_state <= {o_state[35:0], i_si};
      end

  genvar  i;

  generate

    for (i = 1; i <= 37; i = i+1) begin : casr_blk
      wire left  = (i > 1)  ? o_state[37-i+1] : i_ptb & i_ptb_valid;
      wire right = (i < 37) ? o_state[37-i-1] : i_ptb & i_ptb_valid;
      assign nxt_state[37-i] = (i == 9) ? left ^ right ^ o_state[37-9] : left ^ right;
    end
  endgenerate

  assign o_so = o_state[36];

endmodule