data/full_repos/permissive/468066752/rtl/ALU.sv
1: b'%Error: data/full_repos/permissive/468066752/rtl/ALU.sv:11: Cannot find file containing module: \'mul_signed\'\n  mul_signed mul_s(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/mul_signed\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/mul_signed.v\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/mul_signed.sv\n             mul_signed\n             mul_signed.v\n             mul_signed.sv\n             obj_dir/mul_signed\n             obj_dir/mul_signed.v\n             obj_dir/mul_signed.sv\n%Error: data/full_repos/permissive/468066752/rtl/ALU.sv:19: Cannot find file containing module: \'mul_unsigned\'\n  mul_unsigned mul_u(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/468066752/rtl/ALU.sv:30: Cannot find file containing module: \'div_signed\'\n  div_signed div_s(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/468066752/rtl/ALU.sv:39: Cannot find file containing module: \'div_unsigned\'\n  div_unsigned div_u(\n  ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/ALU.sv:53: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                  : ... In instance ALU\n      5\'d02:    ALUResult = $signed(A) < $signed(B);  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/ALU.sv:54: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                  : ... In instance ALU\n      5\'d03:    ALUResult = A  <  B;  \n                          ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module ALU (
  input  logic ACLK,
  input  logic RESET,
  input  logic [31:0] A,
  input  logic [31:0] B,
  input  logic [ 4:0] aluop,
  output logic [31:0] ALUResult
);

  logic [63:00] multiplication_signed, multiplication_unsigned, multiplication_signed_unsigned;
  mul_signed mul_s(
    .aclr(RESET),
    .clock(ACLK),
    .dataa(A),
    .datab(B),
    .result(multiplication_signed)
  );

  mul_unsigned mul_u(
    .aclr(RESET),
    .clock(ACLK),
    .dataa(A),
    .datab(B),
    .result(multiplication_unsigned)
  );
  assign multiplication_signed_unsigned = multiplication_signed;


  logic [31:00] division_signed, division_unsigned, remainder_signed, remainder_unsigned;
  div_signed div_s(
    .aclr(RESET),
    .clock(ACLK),
    .denom(B),
    .numer(A),
    .quotient(division_signed),
    .remain(remainder_signed)
  );

  div_unsigned div_u(
    .aclr(RESET),
    .clock(ACLK),
    .denom(B),
    .numer(A),
    .quotient(division_unsigned),
    .remain(remainder_unsigned)
  );


  always_comb begin
    case (aluop)
      5'd00:    ALUResult = A  +  B;
      5'd01:    ALUResult = A  -  B;
      5'd02:    ALUResult = $signed(A) < $signed(B);
      5'd03:    ALUResult = A  <  B;
      5'd04:    ALUResult = A  &  B;
      5'd05:    ALUResult = A  |  B;
      5'd06:    ALUResult = A  ^  B;
      5'd07:    ALUResult = A  << B[04:00];
      5'd08:    ALUResult = A  >> B[04:00];
      5'd09:    ALUResult = $signed(A) >>> B[04:00];
      5'd10:    ALUResult = multiplication_signed[31:00];
      5'd11:    ALUResult = multiplication_signed[63:32];
      5'd12:    ALUResult = multiplication_unsigned[63:32];
      5'd13:    ALUResult = multiplication_signed_unsigned[63:32];
      5'd14:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = 32'hffffffff;
                  end
                  else if (A == 32'h8000000 && B == 32'hffffffff) begin
                    ALUResult = 32'h8000000;
                  end
                  else begin
                    ALUResult = division_signed[31:00];
                  end
                end
      5'd15:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = 32'hffffffff;
                  end
                  else begin
                    ALUResult = division_unsigned[31:00];
                  end
                end
      5'd16:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = A;
                  end
                  else if (A == 32'h8000000 && B == 32'hffffffff) begin
                    ALUResult = 32'h0;
                  end
                  else begin
                    ALUResult = remainder_signed[31:00];
                  end
                end
      5'd17:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = A;
                  end
                  else begin
                    ALUResult = remainder_unsigned[31:00];
                  end
                end
      5'd18:    ALUResult = B;
      default: ALUResult = 32'd0;
    endcase
  end

endmodule
module ALU (
  input  logic ACLK,
  input  logic RESET,
  input  logic [31:0] A,
  input  logic [31:0] B,
  input  logic [ 4:0] aluop,
  output logic [31:0] ALUResult
);


  logic [63:00] multiplication_signed, multiplication_unsigned, multiplication_signed_unsigned;
  mul_signed mul_s(
    .aclr(RESET),
    .clock(ACLK),
    .dataa(A),
    .datab(B),
    .result(multiplication_signed)
  );

  mul_unsigned mul_u(
    .aclr(RESET),
    .clock(ACLK),
    .dataa(A),
    .datab(B),
    .result(multiplication_unsigned)
  );
  assign multiplication_signed_unsigned = multiplication_signed;


  logic [31:00] division_signed, division_unsigned, remainder_signed, remainder_unsigned;
  div_signed div_s(
    .aclr(RESET),
    .clock(ACLK),
    .denom(B),
    .numer(A),
    .quotient(division_signed),
    .remain(remainder_signed)
  );

  div_unsigned div_u(
    .aclr(RESET),
    .clock(ACLK),
    .denom(B),
    .numer(A),
    .quotient(division_unsigned),
    .remain(remainder_unsigned)
  );


  always_comb begin
    case (aluop)
      5'd00:    ALUResult = A  +  B;
      5'd01:    ALUResult = A  -  B;
      5'd02:    ALUResult = $signed(A) < $signed(B);
      5'd03:    ALUResult = A  <  B;
      5'd04:    ALUResult = A  &  B;
      5'd05:    ALUResult = A  |  B;
      5'd06:    ALUResult = A  ^  B;
      5'd07:    ALUResult = A  << B[04:00];
      5'd08:    ALUResult = A  >> B[04:00];
      5'd09:    ALUResult = $signed(A) >>> B[04:00];
      5'd10:    ALUResult = multiplication_signed[31:00];
      5'd11:    ALUResult = multiplication_signed[63:32];
      5'd12:    ALUResult = multiplication_unsigned[63:32];
      5'd13:    ALUResult = multiplication_signed_unsigned[63:32];
      5'd14:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = 32'hffffffff;
                  end
                  else if (A == 32'h8000000 && B == 32'hffffffff) begin
                    ALUResult = 32'h8000000;
                  end
                  else begin
                    ALUResult = division_signed[31:00];
                  end
                end
      5'd15:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = 32'hffffffff;
                  end
                  else begin
                    ALUResult = division_unsigned[31:00];
                  end
                end
      5'd16:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = A;
                  end
                  else if (A == 32'h8000000 && B == 32'hffffffff) begin
                    ALUResult = 32'h0;
                  end
                  else begin
                    ALUResult = remainder_signed[31:00];
                  end
                end
      5'd17:    begin
                  if (A != 32'd0 && B == 32'd0) begin
                    ALUResult = A;
                  end
                  else begin
                    ALUResult = remainder_unsigned[31:00];
                  end
                end
      5'd18:    ALUResult = B;
      default: ALUResult = 32'd0;
    endcase
  end

endmodule