data/full_repos/permissive/445695969/src_rtl/protected/cms1/skinny_sbox8_cms1_non_pipelined_de.v
data/verilator_xmls/43c77a4a-bde1-46b4-8f3a-84393603a668.xml
module cms1_sbox8_cfn_fr (

   f,

   a, b, z, r, clk
   ) ;
   output [1:0]        f;
   input [1:0]         a, b, z;
   input [3:0]	       r;
   input 	       clk;
   wire [1:0] 	       x;
   wire [1:0] 	       y;
   (*equivalent_register_removal = "no" *)reg [3:0] 	       rg;
   assign x = {a[1],~a[0]};
   assign y = {b[1],~b[0]};
   always @ (posedge clk) begin      
      rg[0] <= (x[0] & y[0]) ^ r[0] ^ r[1];
      rg[1] <= (x[0] & y[1]) ^ r[1] ^ r[2];
      rg[2] <= (x[1] & y[0]) ^ r[2] ^ r[3];
      rg[3] <= (x[1] & y[1]) ^ r[3] ^ r[0];
   end
   assign f[0] = ^rg[1:0] ^ z[0];
   assign f[1] = ^rg[3:2] ^ z[1]; 

endmodule
module cms1_sbox8_cfn_fr (

   f,

   a, b, z, r, clk
   ) ;

   output [1:0]        f;
   input [1:0]         a, b, z;
   input [3:0]	       r;
   input 	       clk;
   wire [1:0] 	       x;
   wire [1:0] 	       y;
   (*equivalent_register_removal = "no" *)reg [3:0] 	       rg;
   assign x = {a[1],~a[0]};
   assign y = {b[1],~b[0]};
   always @ (posedge clk) begin      
      rg[0] <= (x[0] & y[0]) ^ r[0] ^ r[1];
      rg[1] <= (x[0] & y[1]) ^ r[1] ^ r[2];
      rg[2] <= (x[1] & y[0]) ^ r[2] ^ r[3];
      rg[3] <= (x[1] & y[1]) ^ r[3] ^ r[0];
   end
   assign f[0] = ^rg[1:0] ^ z[0];
   assign f[1] = ^rg[3:2] ^ z[1]; 

endmodule