data/full_repos/permissive/42835347/EMU_Basic_Project/DM_TLV5619_DAC_Interface_Module.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/42835347/EMU_Basic_Project/DM_TLV5619_DAC_Interface_Module.v:54: Signal definition not found, creating implicitly: \'DACMemWE\'\n                                                                                                             : ... Suggested alternative: \'DACWE\'\nassign DACMemWE = IFFTOutputWE;    \n       ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DM_TLV5619_DAC_Interface_Module(
DACDataInput,
DACCS,
CLK,
SampleDelayZero,
DACLDAC,
DACPD,
DACWE,
IFFTOutput,
DMLocationWritingTo,
IFFTOutputWE,
IFFTOutputIndex
);
	 
	 
input          CLK, SampleDelayZero, IFFTOutputWE;
input [9:0]    DMLocationWritingTo;
input [11:0]   IFFTOutput;
input [8:0]    IFFTOutputIndex;

output         DACCS, DACLDAC, DACPD, DACWE;
output [11:0]  DACDataInput;

reg [11:0]     DACDataInput;   
reg [14:0]     DACDelayCount;

wire           SampleDelayZero, DACCS, IFFTOutputWE;
wire [11:0]    IFFTOutput;
wire [8:0]     IFFTOutputIndex;


   (* RAM_STYLE="{auto | block |  block_power1 | block_power2}" *)
reg [11:0]      StoredDACValues [0:1023];


assign DACCS     = 0;

assign DACLDAC   = 0;

assign DACPD     = 1;

assign DACWE     = (~| DACDelayCount[12:4]) && ( DACDelayCount[3]);



assign DACMemWE = IFFTOutputWE;



always @(posedge CLK)
begin
  if (DACMemWE)
  begin
    StoredDACValues [ {!DMLocationWritingTo[9], IFFTOutputIndex} ] <= IFFTOutput[11:0];
  end
  
  DACDataInput[11:0] <= StoredDACValues[DMLocationWritingTo + 4];
end


always @(posedge CLK)
begin
  if ( SampleDelayZero )
  begin
    DACDelayCount <= 0;
  end
  
  else
  begin
    DACDelayCount <= DACDelayCount + 1; 
  end
  
end  



endmodule
module DM_TLV5619_DAC_Interface_Module(
DACDataInput,
DACCS,
CLK,
SampleDelayZero,
DACLDAC,
DACPD,
DACWE,
IFFTOutput,
DMLocationWritingTo,
IFFTOutputWE,
IFFTOutputIndex
);

	 
	 
input          CLK, SampleDelayZero, IFFTOutputWE;
input [9:0]    DMLocationWritingTo;
input [11:0]   IFFTOutput;
input [8:0]    IFFTOutputIndex;

output         DACCS, DACLDAC, DACPD, DACWE;
output [11:0]  DACDataInput;

reg [11:0]     DACDataInput;   
reg [14:0]     DACDelayCount;

wire           SampleDelayZero, DACCS, IFFTOutputWE;
wire [11:0]    IFFTOutput;
wire [8:0]     IFFTOutputIndex;


   (* RAM_STYLE="{auto | block |  block_power1 | block_power2}" *)
reg [11:0]      StoredDACValues [0:1023];


assign DACCS     = 0;

assign DACLDAC   = 0;

assign DACPD     = 1;

assign DACWE     = (~| DACDelayCount[12:4]) && ( DACDelayCount[3]);



assign DACMemWE = IFFTOutputWE;



always @(posedge CLK)
begin
  if (DACMemWE)
  begin
    StoredDACValues [ {!DMLocationWritingTo[9], IFFTOutputIndex} ] <= IFFTOutput[11:0];
  end
  
  DACDataInput[11:0] <= StoredDACValues[DMLocationWritingTo + 4];
end


always @(posedge CLK)
begin
  if ( SampleDelayZero )
  begin
    DACDelayCount <= 0;
  end
  
  else
  begin
    DACDelayCount <= DACDelayCount + 1; 
  end
  
end  



endmodule