data/full_repos/permissive/496903659/037 conditional.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/037\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/037\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/037.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/037.sv\n             data/full_repos/permissive/496903659/037\n             data/full_repos/permissive/496903659/037.v\n             data/full_repos/permissive/496903659/037.sv\n             obj_dir/data/full_repos/permissive/496903659/037\n             obj_dir/data/full_repos/permissive/496903659/037.v\n             obj_dir/data/full_repos/permissive/496903659/037.sv\n%Error: Cannot find file containing module: conditional.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);

    wire [7:0] min_0, min_1;

	assign min_0 = a < b ? a : b;
    assign min_1 = c < d ? c : d;
    assign min = min_0 < min_1 ? min_0 : min_1;
    
endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);


    wire [7:0] min_0, min_1;

	assign min_0 = a < b ? a : b;
    assign min_1 = c < d ? c : d;
    assign min = min_0 < min_1 ? min_0 : min_1;
    
endmodule