data/full_repos/permissive/460468583/data/yosys/intel_alm/common/misc_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/intel_alm/common/misc_sim.v:5: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'MISTRAL_IB\'\nmodule MISTRAL_IB((* iopad_external_pin *)  input PAD, output O);\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'MISTRAL_OB\'\nmodule MISTRAL_OB((* iopad_external_pin *)  output PAD, input I);\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'MISTRAL_IO\'\nmodule MISTRAL_IO((* iopad_external_pin *)  inout PAD, input I, input OE, output O);\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'MISTRAL_CLKBUF\'\nmodule MISTRAL_CLKBUF (\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MISTRAL_OB((* iopad_external_pin *)  output PAD, input I);
	assign PAD = I;
endmodule
module MISTRAL_OB((* iopad_external_pin *)  output PAD, input I);

	assign PAD = I;
endmodule