data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/f920458c-5eda-4f37-a0e3-be0c9bc5ba51.xml
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";
    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data;
	input dout_busy;
	output dout_vld;
	output [10:0] dout_data;


endmodule
module dut_type_wrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data,
       dout_busy,
       dout_vld,
       dout_data

    ) (* integer foreign = "SystemC";

    *);

	input clk;
	input rst;
	output din_busy;
	input din_vld;
	input [7:0] din_data;
	input dout_busy;
	output dout_vld;
	output [10:0] dout_data;


endmodule