data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iramspx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iramspx.v:39: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iramspx.v:57: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;\n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iramspx.v:62: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg [WIDTH-1:0] do;\n                ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iramspx.v:79: syntax error, unexpected <=\n    if (test) do <= {WIDTH{1'b0}};\n                 ^~\n%Error: Cannot continue\n"
module iramspx
    (
     clk,
     a,
     we,
     re,
     di,
     do,
     
     test,
     mask
     );

parameter ADDRBIT = 11;
parameter DEPTH = 1536;
parameter WIDTH = 32;
parameter TYPE  = "AUTO";
parameter MAXDEPTH = 0;
parameter DISPLAY_ERR_RAM_RD    = "ON";

input               clk;
input [ADDRBIT-1:0] a;
input               we;
input [WIDTH-1:0]   di;
input               re;
output [WIDTH-1:0]  do;
input               mask;
input               test;

reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] do;

integer i;
initial
    begin 
    for(i=0;i<DEPTH;i=i+1)
        ram[i] = {WIDTH{1'b0}};
    end

always @ (posedge clk)
    begin
    if (we & (!test))
        begin
        ram[a] <= di;

        end

    if (test) do <= {WIDTH{1'b0}};
    else if (re | mask)
        begin
        if (!we)    do <= ram[a];
        else
            begin
            do <= {WIDTH{1'bx}};

            `ifdef DISPLAY_ERR_RAM_RD_OFF
            `else
            if (DISPLAY_ERR_RAM_RD == "ON")
                $display("ERR_RAM: RD and WR at the same time at %h %t %m",a,$time);
            `endif
          
            end
        end
    else    do  <= {WIDTH{1'bx}};
    end


wire    sameaddr;
assign sameaddr = we & re;

endmodule
module iramspx
    (
     clk,
     a,
     we,
     re,
     di,
     do,
     
     test,
     mask
     );


parameter ADDRBIT = 11;
parameter DEPTH = 1536;
parameter WIDTH = 32;
parameter TYPE  = "AUTO";
parameter MAXDEPTH = 0;
parameter DISPLAY_ERR_RAM_RD    = "ON";

input               clk;
input [ADDRBIT-1:0] a;
input               we;
input [WIDTH-1:0]   di;
input               re;
output [WIDTH-1:0]  do;
input               mask;
input               test;

reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] do;

integer i;
initial
    begin 
    for(i=0;i<DEPTH;i=i+1)
        ram[i] = {WIDTH{1'b0}};
    end

always @ (posedge clk)
    begin
    if (we & (!test))
        begin
        ram[a] <= di;

        end

    if (test) do <= {WIDTH{1'b0}};
    else if (re | mask)
        begin
        if (!we)    do <= ram[a];
        else
            begin
            do <= {WIDTH{1'bx}};

            `ifdef DISPLAY_ERR_RAM_RD_OFF
            `else
            if (DISPLAY_ERR_RAM_RD == "ON")
                $display("ERR_RAM: RD and WR at the same time at %h %t %m",a,$time);
            `endif
          
            end
        end
    else    do  <= {WIDTH{1'bx}};
    end


wire    sameaddr;
assign sameaddr = we & re;

endmodule