data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/MReg.v
data/verilator_xmls/aba79f5b-0efb-499d-a1cb-134a9ee3ae90.xml
module MReg(
    input clk,
    input RFWEE,
    input MtoRFSelE,
    input DMWEE,
    input [31:0] ALUOut,
    input [31:0] DMdinE,
    input [4:0] RFAE,
    output reg RFWEM,
    output reg MtoRFSelM,
    output reg DMWEM,
    output reg [31:0] ALUOutM,
    output reg [31:0] DMdinM,
    output reg [4:0] RFAM
    );
    
    always @(posedge clk) begin
        RFWEM <= RFWEE;
        MtoRFSelM <= MtoRFSelE;
        DMWEM <= DMWEE;
        ALUOutM <= ALUOut;
        DMdinM <= DMdinE;
        RFAM <= RFAE;
    end
endmodule
module MReg(
    input clk,
    input RFWEE,
    input MtoRFSelE,
    input DMWEE,
    input [31:0] ALUOut,
    input [31:0] DMdinE,
    input [4:0] RFAE,
    output reg RFWEM,
    output reg MtoRFSelM,
    output reg DMWEM,
    output reg [31:0] ALUOutM,
    output reg [31:0] DMdinM,
    output reg [4:0] RFAM
    );

    
    always @(posedge clk) begin
        RFWEM <= RFWEE;
        MtoRFSelM <= MtoRFSelE;
        DMWEM <= DMWEE;
        ALUOutM <= ALUOut;
        DMdinM <= DMdinE;
        RFAM <= RFAE;
    end
endmodule