data/full_repos/permissive/431487364/src/core/regfile.v
1: b'%Error: data/full_repos/permissive/431487364/src/core/regfile.v:9: Cannot find include file: ../headers/buceros_header.v\n`include "../headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v.sv\n             ../headers/buceros_header.v\n             ../headers/buceros_header.v.v\n             ../headers/buceros_header.v.sv\n             obj_dir/../headers/buceros_header.v\n             obj_dir/../headers/buceros_header.v.v\n             obj_dir/../headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:14: Define or directive not defined: \'`RegAddrBus\'\n    input  wire [`RegAddrBus] r_addr1_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire [`RegAddrBus] r_addr1_i,\n                            ^\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:15: Define or directive not defined: \'`RegAddrBus\'\n    input  wire [`RegAddrBus] r_addr2_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`RegAddrBus] w_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:17: Define or directive not defined: \'`RegAddrBus\'\n    input  wire [`RegAddrBus] w_addr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:18: Define or directive not defined: \'`RegDataBus\'\n    input  wire [`RegDataBus] w_data_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:20: Define or directive not defined: \'`RegDataBus\'\n    output wire [`RegDataBus] r_data1_o,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:21: Define or directive not defined: \'`RegDataBus\'\n    output wire [`RegDataBus] r_data2_o\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:24: Define or directive not defined: \'`RegDataBus\'\n    wire [`RegDataBus] regfile   [0:`REG_NUM-1];\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`RegDataBus] regfile   [0:`REG_NUM-1];\n                     ^\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:24: Define or directive not defined: \'`REG_NUM\'\n    wire [`RegDataBus] regfile   [0:`REG_NUM-1];\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:25: Define or directive not defined: \'`RegDataBus\'\n    reg  [`RegDataBus] regfile_r [1:`REG_NUM-1];\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg  [`RegDataBus] regfile_r [1:`REG_NUM-1];\n                     ^\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:25: Define or directive not defined: \'`REG_NUM\'\n    reg  [`RegDataBus] regfile_r [1:`REG_NUM-1];\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:29: syntax error, unexpected assign\n    assign r1_x0 = r_addr1_i == `REG_ADDR_W\'b0;\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:29: Define or directive not defined: \'`REG_ADDR_W\'\n    assign r1_x0 = r_addr1_i == `REG_ADDR_W\'b0;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:30: Define or directive not defined: \'`REG_ADDR_W\'\n    assign r2_x0 = r_addr2_i == `REG_ADDR_W\'b0;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:32: Define or directive not defined: \'`REG_DATA_W\'\n    assign r_data1_o = {`REG_DATA_W{~r1_x0}} & ((w_en_i && (r_addr1_i == w_addr_i)) ? w_data_i : regfile[r_addr1_i]);\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:33: Define or directive not defined: \'`REG_DATA_W\'\n    assign r_data2_o = {`REG_DATA_W{~r2_x0}} & ((w_en_i && (r_addr2_i == w_addr_i)) ? w_data_i : regfile[r_addr2_i]);\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/regfile.v:37: Define or directive not defined: \'`REG_NUM\'\n        for(reg_idx=1;reg_idx<`REG_NUM;reg_idx=reg_idx+1) begin: loop_regfile\n                              ^~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module regfile (
    input  wire               clk,
    input  wire               rst_n,
    input  wire [`RegAddrBus] r_addr1_i,
    input  wire [`RegAddrBus] r_addr2_i,
    input  wire               w_en_i,
    input  wire [`RegAddrBus] w_addr_i,
    input  wire [`RegDataBus] w_data_i,

    output wire [`RegDataBus] r_data1_o,
    output wire [`RegDataBus] r_data2_o
);

    wire [`RegDataBus] regfile   [0:`REG_NUM-1];
    reg  [`RegDataBus] regfile_r [1:`REG_NUM-1];
    wire               r1_x0;
    wire               r2_x0;

    assign r1_x0 = r_addr1_i == `REG_ADDR_W'b0;
    assign r2_x0 = r_addr2_i == `REG_ADDR_W'b0;

    assign r_data1_o = {`REG_DATA_W{~r1_x0}} & ((w_en_i && (r_addr1_i == w_addr_i)) ? w_data_i : regfile[r_addr1_i]);
    assign r_data2_o = {`REG_DATA_W{~r2_x0}} & ((w_en_i && (r_addr2_i == w_addr_i)) ? w_data_i : regfile[r_addr2_i]);

    genvar reg_idx;
    generate
        for(reg_idx=1;reg_idx<`REG_NUM;reg_idx=reg_idx+1) begin: loop_regfile
            always @(posedge clk or negedge rst_n) begin
                if(~rst_n) begin
                    regfile_r[reg_idx] <= 0;
                end else begin
                    if(w_en_i && w_addr_i == reg_idx) begin
                        regfile_r[reg_idx] <= w_data_i;
                    end else begin
                        regfile_r[reg_idx] <= regfile_r[reg_idx];
                    end
                end
            end
            assign regfile[reg_idx] = regfile_r[reg_idx];
        end
    endgenerate

    assign regfile[0] = 32'b0;

endmodule
module regfile (
    input  wire               clk,
    input  wire               rst_n,
    input  wire [`RegAddrBus] r_addr1_i,
    input  wire [`RegAddrBus] r_addr2_i,
    input  wire               w_en_i,
    input  wire [`RegAddrBus] w_addr_i,
    input  wire [`RegDataBus] w_data_i,

    output wire [`RegDataBus] r_data1_o,
    output wire [`RegDataBus] r_data2_o
);


    wire [`RegDataBus] regfile   [0:`REG_NUM-1];
    reg  [`RegDataBus] regfile_r [1:`REG_NUM-1];
    wire               r1_x0;
    wire               r2_x0;

    assign r1_x0 = r_addr1_i == `REG_ADDR_W'b0;
    assign r2_x0 = r_addr2_i == `REG_ADDR_W'b0;

    assign r_data1_o = {`REG_DATA_W{~r1_x0}} & ((w_en_i && (r_addr1_i == w_addr_i)) ? w_data_i : regfile[r_addr1_i]);
    assign r_data2_o = {`REG_DATA_W{~r2_x0}} & ((w_en_i && (r_addr2_i == w_addr_i)) ? w_data_i : regfile[r_addr2_i]);

    genvar reg_idx;
    generate
        for(reg_idx=1;reg_idx<`REG_NUM;reg_idx=reg_idx+1) begin: loop_regfile
            always @(posedge clk or negedge rst_n) begin
                if(~rst_n) begin
                    regfile_r[reg_idx] <= 0;
                end else begin
                    if(w_en_i && w_addr_i == reg_idx) begin
                        regfile_r[reg_idx] <= w_data_i;
                    end else begin
                        regfile_r[reg_idx] <= regfile_r[reg_idx];
                    end
                end
            end
            assign regfile[reg_idx] = regfile_r[reg_idx];
        end
    endgenerate

    assign regfile[0] = 32'b0;

endmodule