data/full_repos/permissive/430026064/adder_32bit.v
data/verilator_xmls/1d3f44bc-32b7-445b-ba0b-28863e2fb83e.xml
module adder_32bit (
  input [31:0] in1,
  input [31:0] in2,
  output reg [31:0] out
);
  
  initial begin
    out = 0;
  end

  always@(in1, in2) begin
    out = in1 + in2;

  end
endmodule
module adder_32bit (
  input [31:0] in1,
  input [31:0] in2,
  output reg [31:0] out
);

  
  initial begin
    out = 0;
  end

  always@(in1, in2) begin
    out = in1 + in2;

  end
endmodule