data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/seven_seg_display_controller.v
1: b"%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/seven_seg_display_controller.v:20: Cannot find file containing module: 'clock_divider'\n    clock_divider clkd1(clk, 32'd100000, d_clk);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/clock_divider\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/clock_divider.v\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s)\n"
module ssd_controller(
    input clk,
    input[15:0] value,
    
    output reg[6:0] cathode,
    output[3:0] anode
    );
    
    reg[1:0] segment = 0;
    reg[3:0] digit;
    
    assign anode = ~(4'b0001 << segment);

    wire d_clk;
    clock_divider clkd1(clk, 32'd100000, d_clk);
    
    always@(posedge d_clk) begin

        segment = segment + 1;

        case (segment)
           2'h0: digit = value[3:0];
           2'h1: digit = value[7:4]; 
           2'h2: digit = value[11:8]; 
           2'h3: digit = value[15:12];
        endcase
        
        
        case (digit)
            4'h0: cathode = 7'b1000000;
            4'h1: cathode = 7'b1111001;
            4'h2: cathode = 7'b0100100;
            4'h3: cathode = 7'b0110000;
            4'h4: cathode = 7'b0011001;
            4'h5: cathode = 7'b0010010;
            4'h6: cathode = 7'b0000010;
            4'h7: cathode = 7'b1111000;
            4'h8: cathode = 7'b0000000;
            4'h9: cathode = 7'b0010000;
            4'ha: cathode = 7'b0001000;
            4'hb: cathode = 7'b0000011;
            4'hc: cathode = 7'b1000110;
            4'hd: cathode = 7'b0100001;
            4'he: cathode = 7'b0000110;
            default: cathode = 7'b0001110;
        endcase
    end
    
endmodule
module ssd_controller(
    input clk,
    input[15:0] value,
    
    output reg[6:0] cathode,
    output[3:0] anode
    );

    
    reg[1:0] segment = 0;
    reg[3:0] digit;
    
    assign anode = ~(4'b0001 << segment);

    wire d_clk;
    clock_divider clkd1(clk, 32'd100000, d_clk);
    
    always@(posedge d_clk) begin

        segment = segment + 1;

        case (segment)
           2'h0: digit = value[3:0];
           2'h1: digit = value[7:4]; 
           2'h2: digit = value[11:8]; 
           2'h3: digit = value[15:12];
        endcase
        
        
        case (digit)
            4'h0: cathode = 7'b1000000;
            4'h1: cathode = 7'b1111001;
            4'h2: cathode = 7'b0100100;
            4'h3: cathode = 7'b0110000;
            4'h4: cathode = 7'b0011001;
            4'h5: cathode = 7'b0010010;
            4'h6: cathode = 7'b0000010;
            4'h7: cathode = 7'b1111000;
            4'h8: cathode = 7'b0000000;
            4'h9: cathode = 7'b0010000;
            4'ha: cathode = 7'b0001000;
            4'hb: cathode = 7'b0000011;
            4'hc: cathode = 7'b1000110;
            4'hd: cathode = 7'b0100001;
            4'he: cathode = 7'b0000110;
            default: cathode = 7'b0001110;
        endcase
    end
    
endmodule