data/full_repos/permissive/460328193/ipa_proj_pipe/decode.v
data/verilator_xmls/73d6fa4a-35e5-4c8b-bf85-7a4c9a67edda.xml
module decode(icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);

input [3:0] icode;
input Cnd;
input [3:0] rA;
input [3:0] rB;
input clock;

output reg [3:0] srcA,srcB,destM,destE;
always @(*)    
begin
    if(icode==4'h0)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h1)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h2)
	begin
		srcA<=rA;
        srcB<=4'hF;
	end
	else if(icode==4'h3)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h4)
	begin
		srcA<=rA;
        srcB<=rB;
	end	
	else if(icode==4'h5)
	begin
		srcA<=4'hF;
        srcB<=rB;
	end
	else if(icode==4'h6)
	begin
		srcA<=rA;
        srcB<=rB;
	end
	else if(icode==4'h7)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h8)
	begin
		srcA<=4'hF;
        srcB<=4;
	end
	else if(icode==4'h9)
	begin
		srcA<=4;
        srcB<=4;
	end
	else if(icode==4'hA)
	begin
		srcA<=rA;
        srcB<=4;
	end
	else if(icode==4'hB)
	begin
		srcA<=4;
        srcB<=4;
	end
end

always @(*)  
begin
    if(icode==4'h0)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h1)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if((icode==4'h2) && (Cnd==1'b1))
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h3)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h4)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end	
	else if(icode==4'h5)
	begin
		destM<=rA;
        destE<=4'hF;
	end
	else if(icode==4'h6)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h7)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h8)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'h9)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hA)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hB)
	begin
		destM<=rA;
        destE<=4;
	end
end
endmodule
module decode(icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);


input [3:0] icode;
input Cnd;
input [3:0] rA;
input [3:0] rB;
input clock;

output reg [3:0] srcA,srcB,destM,destE;
always @(*)    
begin
    if(icode==4'h0)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h1)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h2)
	begin
		srcA<=rA;
        srcB<=4'hF;
	end
	else if(icode==4'h3)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h4)
	begin
		srcA<=rA;
        srcB<=rB;
	end	
	else if(icode==4'h5)
	begin
		srcA<=4'hF;
        srcB<=rB;
	end
	else if(icode==4'h6)
	begin
		srcA<=rA;
        srcB<=rB;
	end
	else if(icode==4'h7)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h8)
	begin
		srcA<=4'hF;
        srcB<=4;
	end
	else if(icode==4'h9)
	begin
		srcA<=4;
        srcB<=4;
	end
	else if(icode==4'hA)
	begin
		srcA<=rA;
        srcB<=4;
	end
	else if(icode==4'hB)
	begin
		srcA<=4;
        srcB<=4;
	end
end

always @(*)  
begin
    if(icode==4'h0)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h1)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if((icode==4'h2) && (Cnd==1'b1))
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h3)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h4)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end	
	else if(icode==4'h5)
	begin
		destM<=rA;
        destE<=4'hF;
	end
	else if(icode==4'h6)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h7)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h8)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'h9)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hA)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hB)
	begin
		destM<=rA;
        destE<=4;
	end
end
endmodule