data/full_repos/permissive/441359809/src/yosys/tests/simple/implicit_ports.v
data/verilator_xmls/18a3ce0e-ca3b-4355-ab08-e39c1c3b4404.xml
module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
	wire cin = 1;
	alu alu (
		.a(a),
		.b,
		.cin(),
		.cout(cout),
		.result(alu_result)
	);
endmodule
module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);

	wire cin = 1;
	alu alu (
		.a(a),
		.b,
		.cin(),
		.cout(cout),
		.result(alu_result)
	);
endmodule