data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v
1: b"%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:50: Define or directive not defined: '`DATA_WIDTH'\noutput [`DATA_WIDTH-1:0] data_out;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:57: Define or directive not defined: '`XY_WIDTH'\ninput [`XY_WIDTH-1:0] my_loc_x_in;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:58: Define or directive not defined: '`XY_WIDTH'\ninput [`XY_WIDTH-1:0] my_loc_y_in;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:59: Define or directive not defined: '`CHIP_ID_WIDTH'\ninput [`CHIP_ID_WIDTH-1:0] my_chip_id_in;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:61: Define or directive not defined: '`DATA_WIDTH'\ninput [`DATA_WIDTH-1:0] data_in;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:74: Define or directive not defined: '`DATA_WIDTH'\nwire [`DATA_WIDTH-1:0] data_out_internal;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:75: Define or directive not defined: '`DATA_WIDTH'\nwire [`DATA_WIDTH-1:0] data_out_internal_pre;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:92: Define or directive not defined: '`DATA_WIDTH'\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:92: Define or directive not defined: '`CHIP_ID_WIDTH'\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:92: Define or directive not defined: '`XY_WIDTH'\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:92: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n%Error: data/full_repos/permissive/522312766/verilog/rtl/dynamic_node/dynamic/dynamic_input_top_16_para.tmp.v:92: Define or directive not defined: '`PAYLOAD_LEN'\n%Error: Exiting due to 12 error(s)\n"
module dynamic_input_top_16_para(route_req_0_out, route_req_1_out, default_ready_0_out, default_ready_1_out, tail_out, yummy_out, data_out, valid_out, clk, reset, my_loc_x_in, my_loc_y_in, my_chip_id_in, valid_in, data_in,thanks_0, thanks_1);



output route_req_0_out;
output route_req_1_out;
output default_ready_0_out;
output default_ready_1_out;

output tail_out;
output yummy_out;
output [`DATA_WIDTH-1:0] data_out;
output valid_out;


input clk;
input reset;

input [`XY_WIDTH-1:0] my_loc_x_in;
input [`XY_WIDTH-1:0] my_loc_y_in;
input [`CHIP_ID_WIDTH-1:0] my_chip_id_in;
input valid_in;
input [`DATA_WIDTH-1:0] data_in;
input thanks_0;
input thanks_1;


   





wire thanks_all_temp;
wire valid_out_internal;
wire [`DATA_WIDTH-1:0] data_out_internal;
wire [`DATA_WIDTH-1:0] data_out_internal_pre;



assign valid_out = valid_out_internal;
assign data_out = data_out_internal;


network_input_blk_multi_out #(.LOG2_NUMBER_FIFO_ELEMENTS(4)) NIB(.clk(clk), .reset(reset), .data_in(data_in), .valid_in(valid_in), .yummy_out(yummy_out), .thanks_in(thanks_all_temp), .data_val(data_out_internal_pre), .data_val1(), .data_avail(valid_out_internal));



assign data_out_internal = data_out_internal_pre;



dynamic_input_control_para control(.thanks_all_temp_out(thanks_all_temp), .route_req_0_out(route_req_0_out), .route_req_1_out(route_req_1_out), .default_ready_0(default_ready_0_out), .default_ready_1(default_ready_1_out), .tail_out(tail_out), .clk(clk), .reset(reset), .my_loc_x_in(my_loc_x_in), .my_loc_y_in(my_loc_y_in), 
    .my_chip_id_in(my_chip_id_in), .abs_x(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH-`XY_WIDTH]), .abs_y(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-`XY_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH]), .abs_chip_id(data_out_internal[`DATA_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH]),.final_bits(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-2:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-4]), .valid_in(valid_out_internal), .thanks_0(thanks_0), .thanks_1(thanks_1), .length(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-5:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-4-`PAYLOAD_LEN]));

endmodule
module dynamic_input_top_16_para(route_req_0_out, route_req_1_out, default_ready_0_out, default_ready_1_out, tail_out, yummy_out, data_out, valid_out, clk, reset, my_loc_x_in, my_loc_y_in, my_chip_id_in, valid_in, data_in,thanks_0, thanks_1);




output route_req_0_out;
output route_req_1_out;
output default_ready_0_out;
output default_ready_1_out;

output tail_out;
output yummy_out;
output [`DATA_WIDTH-1:0] data_out;
output valid_out;


input clk;
input reset;

input [`XY_WIDTH-1:0] my_loc_x_in;
input [`XY_WIDTH-1:0] my_loc_y_in;
input [`CHIP_ID_WIDTH-1:0] my_chip_id_in;
input valid_in;
input [`DATA_WIDTH-1:0] data_in;
input thanks_0;
input thanks_1;


   





wire thanks_all_temp;
wire valid_out_internal;
wire [`DATA_WIDTH-1:0] data_out_internal;
wire [`DATA_WIDTH-1:0] data_out_internal_pre;



assign valid_out = valid_out_internal;
assign data_out = data_out_internal;


network_input_blk_multi_out #(.LOG2_NUMBER_FIFO_ELEMENTS(4)) NIB(.clk(clk), .reset(reset), .data_in(data_in), .valid_in(valid_in), .yummy_out(yummy_out), .thanks_in(thanks_all_temp), .data_val(data_out_internal_pre), .data_val1(), .data_avail(valid_out_internal));



assign data_out_internal = data_out_internal_pre;



dynamic_input_control_para control(.thanks_all_temp_out(thanks_all_temp), .route_req_0_out(route_req_0_out), .route_req_1_out(route_req_1_out), .default_ready_0(default_ready_0_out), .default_ready_1(default_ready_1_out), .tail_out(tail_out), .clk(clk), .reset(reset), .my_loc_x_in(my_loc_x_in), .my_loc_y_in(my_loc_y_in), 
    .my_chip_id_in(my_chip_id_in), .abs_x(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH-`XY_WIDTH]), .abs_y(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-`XY_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH]), .abs_chip_id(data_out_internal[`DATA_WIDTH-1:`DATA_WIDTH-`CHIP_ID_WIDTH]),.final_bits(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-2:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-4]), .valid_in(valid_out_internal), .thanks_0(thanks_0), .thanks_1(thanks_1), .length(data_out_internal[`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-5:`DATA_WIDTH-`CHIP_ID_WIDTH-2*`XY_WIDTH-4-`PAYLOAD_LEN]));

endmodule