data/full_repos/permissive/502764644/msm5205.sv
1: b"%Error-ASSIGNIN: data/full_repos/permissive/502764644/msm5205.sv:15: Assigning to input/const variable: 'data_in'\nalways_ff @(posedge clk) if (~adpcm_select) data_in[0] <= 0;\n                                            ^~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module msm5205
(
    input  logic       clk,
    input  logic       reset,
    input  logic [1:0] sample_select,
    input  logic       adpcm_select,
    input  logic [3:0] data_in,
    output logic [9:0] audio_out,
    output logic       out_vck,
    output logic       out_clk
);

always_ff @(posedge clk) if (~adpcm_select) data_in[0] <= 0;


logic [1:0] clk_cnt;
always_ff @(posedge clk) begin
    if (reset) clk_cnt <= 0;
    else clk_cnt <= clk_cnt + 1;
end


logic reset_trig;
always_ff @(posedge clk) begin
    reset_trig <= 0;
    if (reset) begin
        if (clk_cnt > 2) reset_trig <= 1;
    end
end


logic sample_freq;
always_comb begin
    case (sample_select)
        2'b00   : sample_freq = clk / 96;
        2'b01   : sample_freq = clk / 64;
        2'b10   : sample_freq = clk / 48;
        default : sample_freq = 0;
    endcase
end


logic [11:0] adpcm_synth;





always_ff @(posedge clk) if (reset_trig) audio_out <= 0;

endmodule
module msm5205
(
    input  logic       clk,
    input  logic       reset,
    input  logic [1:0] sample_select,
    input  logic       adpcm_select,
    input  logic [3:0] data_in,
    output logic [9:0] audio_out,
    output logic       out_vck,
    output logic       out_clk
);


always_ff @(posedge clk) if (~adpcm_select) data_in[0] <= 0;


logic [1:0] clk_cnt;
always_ff @(posedge clk) begin
    if (reset) clk_cnt <= 0;
    else clk_cnt <= clk_cnt + 1;
end


logic reset_trig;
always_ff @(posedge clk) begin
    reset_trig <= 0;
    if (reset) begin
        if (clk_cnt > 2) reset_trig <= 1;
    end
end


logic sample_freq;
always_comb begin
    case (sample_select)
        2'b00   : sample_freq = clk / 96;
        2'b01   : sample_freq = clk / 64;
        2'b10   : sample_freq = clk / 48;
        default : sample_freq = 0;
    endcase
end


logic [11:0] adpcm_synth;





always_ff @(posedge clk) if (reset_trig) audio_out <= 0;

endmodule