data/full_repos/permissive/498662723/Circuits/Sequential Logic/Shift Registers/m2014 q4k (shift register).v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/m2014\n%Error: Cannot find file containing module: q4k\n%Error: Cannot find file containing module: (shift\n%Error: Cannot find file containing module: register).v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input resetn,
    input in,
    output out);
    
    wire [2:0]q;
    
    always @ (posedge clk)
        begin
            if (resetn == 0)
                q[2] <= 1'b0;
            else
                begin
                    q[2] <= in;
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                q[1] <= 1'b0;
            else
                begin
                    q[1] <= q[2];
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                q[0] <= 1'b0;
            else
                begin
                    q[0] <= q[1];
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                out <= 1'b0;
            else
                begin
                    out <= q[0];
                end
        end

endmodule
module top_module (
    input clk,
    input resetn,
    input in,
    output out);

    
    wire [2:0]q;
    
    always @ (posedge clk)
        begin
            if (resetn == 0)
                q[2] <= 1'b0;
            else
                begin
                    q[2] <= in;
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                q[1] <= 1'b0;
            else
                begin
                    q[1] <= q[2];
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                q[0] <= 1'b0;
            else
                begin
                    q[0] <= q[1];
                end
        end
    
        always @ (posedge clk)
        begin
            if (resetn == 0)
                out <= 1'b0;
            else
                begin
                    out <= q[0];
                end
        end

endmodule