data/full_repos/permissive/479923049/alu_tb.v
1: b'%Error: data/full_repos/permissive/479923049/alu_tb.v:10: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n    task checker;   \n         ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    task checker;   \n                ^\n%Error: data/full_repos/permissive/479923049/alu_tb.v:12: syntax error, unexpected begin\n        begin \n        ^~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:25: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b100); \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:28: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b001);\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:31: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b110); \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:34: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b100);\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:37: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b000);\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:40: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b010);\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:43: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(3\'b100);\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/alu_tb.v:45: syntax error, unexpected $display\n        if( ~err ) $display("PASSED");\n                   ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();
    reg     [15:0] Ain, Bin;
    reg     [1:0] ALUop;
    wire    [15:0] out;
    wire    [2:0] status;
    reg     err;

    ALU DUT(Ain,Bin,ALUop,out,status);

    task checker;
        input [2:0] expected_status;
        begin 
            if( status !== expected_status ) begin
            $display("ERROR ** status is %b, expected %b", status, expected_status );
            err = 1'b1;
            end
        end
    endtask



    initial begin 
        err = 0;
        Ain = 16'd12; Bin = 16'd20; ALUop = 2'b01; #10;
        checker(3'b100); 
        
        Ain = 16'd0; Bin = 16'd0; ALUop = 2'b01; #10;
        checker(3'b001);
        
        Ain = 16'b0111_1111_1111_1111; Bin = 16'b0111_1111_1111_1111; ALUop = 2'b00; #10;
        checker(3'b110);

        Ain = -16'd10000; Bin = -16'd10000; ALUop = 2'b00; #10;
        checker(3'b100);

        Ain = -16'd3245; Bin = 16'd4000; ALUop = 2'b00; #10;
        checker(3'b000);

        Ain = -16'd32045; Bin = 16'd20324; ALUop = 2'b01; #10;
        checker(3'b010);

        Ain = 16'd0; Bin = 16'd2; ALUop = 2'b11; #10;
        checker(3'b100);
        
        if( ~err ) $display("PASSED");
        else $display("FAILED");

        
    end
endmodule
module ALU_tb();

    reg     [15:0] Ain, Bin;
    reg     [1:0] ALUop;
    wire    [15:0] out;
    wire    [2:0] status;
    reg     err;

    ALU DUT(Ain,Bin,ALUop,out,status);

    task checker;
        input [2:0] expected_status;
        begin 
            if( status !== expected_status ) begin
            $display("ERROR ** status is %b, expected %b", status, expected_status );
            err = 1'b1;
            end
        end
    endtask



    initial begin 
        err = 0;
        Ain = 16'd12; Bin = 16'd20; ALUop = 2'b01; #10;
        checker(3'b100); 
        
        Ain = 16'd0; Bin = 16'd0; ALUop = 2'b01; #10;
        checker(3'b001);
        
        Ain = 16'b0111_1111_1111_1111; Bin = 16'b0111_1111_1111_1111; ALUop = 2'b00; #10;
        checker(3'b110);

        Ain = -16'd10000; Bin = -16'd10000; ALUop = 2'b00; #10;
        checker(3'b100);

        Ain = -16'd3245; Bin = 16'd4000; ALUop = 2'b00; #10;
        checker(3'b000);

        Ain = -16'd32045; Bin = 16'd20324; ALUop = 2'b01; #10;
        checker(3'b010);

        Ain = 16'd0; Bin = 16'd2; ALUop = 2'b11; #10;
        checker(3'b100);
        
        if( ~err ) $display("PASSED");
        else $display("FAILED");

        
    end
endmodule