data/full_repos/permissive/441359809/src/yosys/tests/simple/signedexpr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/signedexpr.v:9: Operator ADD expects 4 bits on the LHS, but LHS\'s VARREF \'a\' generates 2 bits.\n                                                                                          : ... In instance signed_test01\nassign xu = (a + b) + 3\'d0;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/signedexpr.v:10: Operator ADD expects 4 bits on the LHS, but LHS\'s VARREF \'a\' generates 2 bits.\n                                                                                           : ... In instance signed_test01\nassign xs = (a + b) + 3\'sd0;\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module signed_test01(a, b, xu, xs, yu, ys, zu, zs);

input signed [1:0] a;
input signed [2:0] b;
output [3:0] xu, xs;
output [3:0] yu, ys;
output zu, zs;

assign xu = (a + b) + 3'd0;
assign xs = (a + b) + 3'sd0;

assign yu = {a + b} + 3'd0;
assign ys = {a + b} + 3'sd0;

assign zu = a + b != 3'd0;
assign zs = a + b != 3'sd0;

endmodule
module signed_test01(a, b, xu, xs, yu, ys, zu, zs);


input signed [1:0] a;
input signed [2:0] b;
output [3:0] xu, xs;
output [3:0] yu, ys;
output zu, zs;

assign xu = (a + b) + 3'd0;
assign xs = (a + b) + 3'sd0;

assign yu = {a + b} + 3'd0;
assign ys = {a + b} + 3'sd0;

assign zu = a + b != 3'd0;
assign zs = a + b != 3'sd0;

endmodule