data/full_repos/permissive/519893543/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/519893543/verilog/rtl/user_project_wrapper.v:90: Cannot find file containing module: 'bqmain'\nbqmain bqmain0 (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519893543/verilog/rtl,data/full_repos/permissive/519893543/bqmain\n             data/full_repos/permissive/519893543/verilog/rtl,data/full_repos/permissive/519893543/bqmain.v\n             data/full_repos/permissive/519893543/verilog/rtl,data/full_repos/permissive/519893543/bqmain.sv\n             bqmain\n             bqmain.v\n             bqmain.sv\n             obj_dir/bqmain\n             obj_dir/bqmain.v\n             obj_dir/bqmain.sv\n%Error: Exiting due to 1 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);






bqmain bqmain0 (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),



    .wb_cyc_i(wbs_cyc_i),
    .wb_stb_i(wbs_stb_i),
    .wb_we_i(wbs_we_i),
    .wb_adr_i(wbs_adr_i),
    .wb_dat_i(wbs_dat_i),
    .wb_ack_o(wbs_ack_o),
    .wb_dat_o(wbs_dat_o),

    .nreset(la_data_in[16]),


    .bq_clk_i(user_clock2),
    .x(io_in[19:8]),

    .y(la_data_out[11:0])

);



endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);







bqmain bqmain0 (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),



    .wb_cyc_i(wbs_cyc_i),
    .wb_stb_i(wbs_stb_i),
    .wb_we_i(wbs_we_i),
    .wb_adr_i(wbs_adr_i),
    .wb_dat_i(wbs_dat_i),
    .wb_ack_o(wbs_ack_o),
    .wb_dat_o(wbs_dat_o),

    .nreset(la_data_in[16]),


    .bq_clk_i(user_clock2),
    .x(io_in[19:8]),

    .y(la_data_out[11:0])

);



endmodule