data/full_repos/permissive/480681467/Source/TB/inverter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/inverter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/inverter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/Source/TB/inverter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/480681467/Source/TB/inverter_tb.v:12: Cannot find file containing module: \'inverter\'\n inverter uut(p,q,clk,reset,finish,e,d);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/inverter\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/inverter.v\n             data/full_repos/permissive/480681467/Source/TB,data/full_repos/permissive/480681467/inverter.sv\n             inverter\n             inverter.v\n             inverter.sv\n             obj_dir/inverter\n             obj_dir/inverter.v\n             obj_dir/inverter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_inverter;
    reg [`WIDTH-1:0] p;
	reg [`WIDTH-1:0] q;
	reg clk;
	reg reset;
	wire finish;
	wire [`WIDTH-1:0] e;
	wire [`WIDTH*2-1:0] d;
	
	inverter uut(p,q,clk,reset,finish,e,d);
	
	initial begin
	   p = 32'd23;
	   q = 32'd5;
	   clk = 0;
	   reset = 0;
	   #10 reset = 1;
	   #10 reset = 0;
	end
	
	always #5 clk = ~clk;
endmodule
module tb_inverter;

    reg [`WIDTH-1:0] p;
	reg [`WIDTH-1:0] q;
	reg clk;
	reg reset;
	wire finish;
	wire [`WIDTH-1:0] e;
	wire [`WIDTH*2-1:0] d;
	
	inverter uut(p,q,clk,reset,finish,e,d);
	
	initial begin
	   p = 32'd23;
	   q = 32'd5;
	   clk = 0;
	   reset = 0;
	   #10 reset = 1;
	   #10 reset = 0;
	end
	
	always #5 clk = ~clk;
endmodule