data/full_repos/permissive/455657973/and_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n       forever #10 Clock = ~ Clock; \n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n                        #10 Read <= 1; MDRin <= 1;   \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n                        #15 Read <= 0; MDRin <= 0;    \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n                        #10 MDRout <= 1; R2in <= 1;   \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n                        #15 MDRout <= 0; R2in <= 0;      \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10 Read <= 1; MDRin <= 1;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #15 Read <= 0; MDRin <= 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n                       #10 MDRout <= 1; R4in <= 1;   \n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n                       #15 MDRout <= 0; R4in <= 0;   \n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n                       #10 Read <= 1; MDRin <= 1;   \n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n                       #15 Read <= 0; MDRin <= 0; \n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n                       #10 MDRout <= 1; R5in <= 1;   \n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/and_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n                       #15 MDRout <= 0; R5in <= 0;   \n                       ^\n%Error: data/full_repos/permissive/455657973/and_tb.v:20: Cannot find file containing module: \'datapath\'\ndatapath DUT(PCout, ZHighout, Zlowout, HIout, LOout, InPortout, Cout, MDRout, R2out, R4out, MARin, PCin, MDRin, IRin, Yin, IncPC,Read,\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/datapath\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/datapath.v\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_tb;       
	reg	PCout, ZHighout, Zlowout, HIout, LOout, InPortout, Cout, MDRout, R2out, R4out;
	reg	MARin, PCin, MDRin, IRin, Yin;
	reg 	IncPC, Read;
	reg	[4:0] AND; 
	reg	R5in, R2in, R4in;
	reg	HIin, LOin, ZHighIn, Cin, ZLowIn;
	reg	Clock, Clear;
	reg	[31:0] Mdatain;
    reg branch_flag;

    parameter Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011,  
                             Reg_load2b = 4'b0100, Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111,  
                             T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100; 
    reg   [3:0] Present_state = Default; 
 

datapath DUT(PCout, ZHighout, Zlowout, HIout, LOout, InPortout, Cout, MDRout, R2out, R4out, MARin, PCin, MDRin, IRin, Yin, IncPC,Read,
            AND, R5in, R2in, R4in, Clock, Mdatain, Clear, HIin, LOin, ZHighIn, ZLowIn, Cin, branch_flag);


initial  
    begin 
       Clock = 0; 
       forever #10 Clock = ~ Clock; 
end 
 
always @(posedge Clock)
   begin 
      case (Present_state) 
        Default   :  Present_state = Reg_load1a; 
        Reg_load1a  :  Present_state = Reg_load1b; 
        Reg_load1b  :  Present_state = Reg_load2a; 
        Reg_load2a  :  Present_state = Reg_load2b; 
        Reg_load2b  :  Present_state = Reg_load3a; 
        Reg_load3a  :  Present_state = Reg_load3b; 
        Reg_load3b  :  Present_state = T0; 
        T0    :  Present_state = T1; 
        T1    :  Present_state = T2; 
        T2    :  Present_state = T3; 
        T3    :  Present_state = T4; 
        T4    :  Present_state = T5; 
       endcase 
   end   
                                                          
always @(Present_state)
begin 
    case (Present_state)
        Default: begin 
              		PCout <= 0;   Zlowout <= 0; ZHighout <= 0;  MDRout<= 0;
						R2out <= 0;   R4out <= 0;   MARin <= 0;   ZLowIn <= 0;  
						PCin <=0;   MDRin <= 0;   IRin  <= 0;   Yin <= 0;  
						IncPC <= 0;   Read <= 0;   AND <= 0;    branch_flag <=0;
						HIout<=0;  LOout<=0; InPortout<=0; Cout<=0;
						R5in <= 0; R2in <= 0; R4in <= 0; Mdatain <= 32'h00000000;
        end 
        Reg_load1a: begin   
                        Mdatain <= 32'h00000022; 
                        Read = 0; MDRin = 0;
                        #10 Read <= 1; MDRin <= 1;   
                        #15 Read <= 0; MDRin <= 0;    
        end 
        Reg_load1b: begin  
                        #10 MDRout <= 1; R2in <= 1;   
                        #15 MDRout <= 0; R2in <= 0;
        end 
        Reg_load2a: begin   
                       Mdatain <= 32'h00000024; 
								#10 Read <= 1; MDRin <= 1;   
								#15 Read <= 0; MDRin <= 0;       
        end 
        Reg_load2b: begin  
                       #10 MDRout <= 1; R4in <= 1;   
                       #15 MDRout <= 0; R4in <= 0;
        end 
        Reg_load3a: begin   
                       Mdatain <= 32'h00000026; 
                       #10 Read <= 1; MDRin <= 1;   
                       #15 Read <= 0; MDRin <= 0; 
        end 
        Reg_load3b: begin  
                       #10 MDRout <= 1; R5in <= 1;   
                       #15 MDRout <= 0; R5in <= 0;
        end 
 
        T0: begin
              PCout <= 1; MARin <= 1; IncPC <= 1; ZLowIn <= 1;   
        end 
        T1: begin 
              Zlowout <= 1; PCin <= 1; Read <= 1; MDRin <= 1;   
              Mdatain <= 32'h4A920000;
        end 
        T2: begin 
              MDRout <= 1; IRin <= 1;    
        end 
        T3: begin 
              R2out <= 1; Yin <= 1;    
        end 
        T4: begin 
              R4out <= 1; AND <= 5'b01001; ZLowIn <= 1;    
        end 
        T5: begin 
              Zlowout <= 1; R5in <= 1;    
        end 
    endcase 
end 
endmodule
module and_tb;
       
	reg	PCout, ZHighout, Zlowout, HIout, LOout, InPortout, Cout, MDRout, R2out, R4out;
	reg	MARin, PCin, MDRin, IRin, Yin;
	reg 	IncPC, Read;
	reg	[4:0] AND; 
	reg	R5in, R2in, R4in;
	reg	HIin, LOin, ZHighIn, Cin, ZLowIn;
	reg	Clock, Clear;
	reg	[31:0] Mdatain;
    reg branch_flag;

    parameter Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011,  
                             Reg_load2b = 4'b0100, Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111,  
                             T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100; 
    reg   [3:0] Present_state = Default; 
 

datapath DUT(PCout, ZHighout, Zlowout, HIout, LOout, InPortout, Cout, MDRout, R2out, R4out, MARin, PCin, MDRin, IRin, Yin, IncPC,Read,
            AND, R5in, R2in, R4in, Clock, Mdatain, Clear, HIin, LOin, ZHighIn, ZLowIn, Cin, branch_flag);


initial  
    begin 
       Clock = 0; 
       forever #10 Clock = ~ Clock; 
end 
 
always @(posedge Clock)
   begin 
      case (Present_state) 
        Default   :  Present_state = Reg_load1a; 
        Reg_load1a  :  Present_state = Reg_load1b; 
        Reg_load1b  :  Present_state = Reg_load2a; 
        Reg_load2a  :  Present_state = Reg_load2b; 
        Reg_load2b  :  Present_state = Reg_load3a; 
        Reg_load3a  :  Present_state = Reg_load3b; 
        Reg_load3b  :  Present_state = T0; 
        T0    :  Present_state = T1; 
        T1    :  Present_state = T2; 
        T2    :  Present_state = T3; 
        T3    :  Present_state = T4; 
        T4    :  Present_state = T5; 
       endcase 
   end   
                                                          
always @(Present_state)
begin 
    case (Present_state)
        Default: begin 
              		PCout <= 0;   Zlowout <= 0; ZHighout <= 0;  MDRout<= 0;
						R2out <= 0;   R4out <= 0;   MARin <= 0;   ZLowIn <= 0;  
						PCin <=0;   MDRin <= 0;   IRin  <= 0;   Yin <= 0;  
						IncPC <= 0;   Read <= 0;   AND <= 0;    branch_flag <=0;
						HIout<=0;  LOout<=0; InPortout<=0; Cout<=0;
						R5in <= 0; R2in <= 0; R4in <= 0; Mdatain <= 32'h00000000;
        end 
        Reg_load1a: begin   
                        Mdatain <= 32'h00000022; 
                        Read = 0; MDRin = 0;
                        #10 Read <= 1; MDRin <= 1;   
                        #15 Read <= 0; MDRin <= 0;    
        end 
        Reg_load1b: begin  
                        #10 MDRout <= 1; R2in <= 1;   
                        #15 MDRout <= 0; R2in <= 0;
        end 
        Reg_load2a: begin   
                       Mdatain <= 32'h00000024; 
								#10 Read <= 1; MDRin <= 1;   
								#15 Read <= 0; MDRin <= 0;       
        end 
        Reg_load2b: begin  
                       #10 MDRout <= 1; R4in <= 1;   
                       #15 MDRout <= 0; R4in <= 0;
        end 
        Reg_load3a: begin   
                       Mdatain <= 32'h00000026; 
                       #10 Read <= 1; MDRin <= 1;   
                       #15 Read <= 0; MDRin <= 0; 
        end 
        Reg_load3b: begin  
                       #10 MDRout <= 1; R5in <= 1;   
                       #15 MDRout <= 0; R5in <= 0;
        end 
 
        T0: begin
              PCout <= 1; MARin <= 1; IncPC <= 1; ZLowIn <= 1;   
        end 
        T1: begin 
              Zlowout <= 1; PCin <= 1; Read <= 1; MDRin <= 1;   
              Mdatain <= 32'h4A920000;
        end 
        T2: begin 
              MDRout <= 1; IRin <= 1;    
        end 
        T3: begin 
              R2out <= 1; Yin <= 1;    
        end 
        T4: begin 
              R4out <= 1; AND <= 5'b01001; ZLowIn <= 1;    
        end 
        T5: begin 
              Zlowout <= 1; R5in <= 1;    
        end 
    endcase 
end 
endmodule