data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n repeat (100) #5 clk <= ~clk;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:17: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mem_simple_4x1_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, uut);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

reg clk, rst;
wire [7:0] out;
wire [4:0] counter;

uut uut (clk, rst, out, counter);

initial begin
	#5 clk <= 0;
	repeat (100) #5 clk <= ~clk;
	#5 $finish;
end

initial begin
	rst <= 1;
	repeat (2) @(posedge clk);
	rst <= 0;
end

always @(posedge clk)
	$display("%d %d %d", rst, out, counter);

initial begin
	$dumpfile("mem_simple_4x1_tb.vcd");
	$dumpvars(0, uut);
end

endmodule
module tb;


reg clk, rst;
wire [7:0] out;
wire [4:0] counter;

uut uut (clk, rst, out, counter);

initial begin
	#5 clk <= 0;
	repeat (100) #5 clk <= ~clk;
	#5 $finish;
end

initial begin
	rst <= 1;
	repeat (2) @(posedge clk);
	rst <= 0;
end

always @(posedge clk)
	$display("%d %d %d", rst, out, counter);

initial begin
	$dumpfile("mem_simple_4x1_tb.vcd");
	$dumpvars(0, uut);
end

endmodule