data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/PC_TB.v:13: Cannot find file containing module: \'PCnt\'\n    PCnt DUT(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/PCnt\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/PCnt.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/PCnt.sv\n             PCnt\n             PCnt.v\n             PCnt.sv\n             obj_dir/PCnt\n             obj_dir/PCnt.v\n             obj_dir/PCnt.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PC_TB(

    );
    reg clk=0;
    reg rst=0;
    reg we=1;                                 
    reg [31:0] next_pc;
    wire [31:0] pc;

    
    PCnt DUT(
    .clk(clk), .rstn(rst), .we(we), .data_in(next_pc), .data_out(pc)
    );    
    
    initial begin: CLK_GEN
        #5;
        rst <=1;
        forever begin
            clk <=0;
            #5;
            clk <=1;
            #5;
        end
    end
    
    initial begin
        #10;
        next_pc <= 32'h0100004;
        #5;
        rst <=1;
        #5;
        if(pc != 32'h0100004) $fatal("Expected output not received");
        #5;
        next_pc <= 32'h0100008;
        #10;
        if(pc != 32'h0100008) $fatal("Expected output not received");
        next_pc <= 32'h010000c;
        #10;
        if(pc != 32'h010000c) $fatal("Expected output not received");
        next_pc <= 32'h0100010;
        #10;
        if(pc != 32'h0100010) $fatal("Expected output not received");
        rst <=0;
        #10;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        next_pc <= 32'h01000008;
        #5;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        #5;
        rst <=1;
        next_pc <= 32'h0100000c;
        #10;
        if(pc != 32'h0100000c) $fatal("Expected output not received");
        next_pc <= 32'h01000010;
        #10;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        we <=0;
        next_pc <= 32'h01000014;
        #5;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        #10;
        next_pc <= 32'h01000018;
        #5;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        #5;
        we <=1;
        next_pc <= 32'h0100001c;
        #10;
        if(pc != 32'h0100001c) $fatal("Expected output not received");
        next_pc <= 32'h01000020;
        #10;
        if(pc != 32'h01000020) $fatal("Expected output not received");
        #5;
        rst<=0;
        next_pc <= 32'h01000021;
        #10;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        #5;
        
        $display("All test cases passed");
        $finish;
    end
    
endmodule
module PC_TB(

    );

    reg clk=0;
    reg rst=0;
    reg we=1;                                 
    reg [31:0] next_pc;
    wire [31:0] pc;

    
    PCnt DUT(
    .clk(clk), .rstn(rst), .we(we), .data_in(next_pc), .data_out(pc)
    );    
    
    initial begin: CLK_GEN
        #5;
        rst <=1;
        forever begin
            clk <=0;
            #5;
            clk <=1;
            #5;
        end
    end
    
    initial begin
        #10;
        next_pc <= 32'h0100004;
        #5;
        rst <=1;
        #5;
        if(pc != 32'h0100004) $fatal("Expected output not received");
        #5;
        next_pc <= 32'h0100008;
        #10;
        if(pc != 32'h0100008) $fatal("Expected output not received");
        next_pc <= 32'h010000c;
        #10;
        if(pc != 32'h010000c) $fatal("Expected output not received");
        next_pc <= 32'h0100010;
        #10;
        if(pc != 32'h0100010) $fatal("Expected output not received");
        rst <=0;
        #10;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        next_pc <= 32'h01000008;
        #5;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        #5;
        rst <=1;
        next_pc <= 32'h0100000c;
        #10;
        if(pc != 32'h0100000c) $fatal("Expected output not received");
        next_pc <= 32'h01000010;
        #10;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        we <=0;
        next_pc <= 32'h01000014;
        #5;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        #10;
        next_pc <= 32'h01000018;
        #5;
        if(pc != 32'h01000010) $fatal("Expected output not received");
        #5;
        we <=1;
        next_pc <= 32'h0100001c;
        #10;
        if(pc != 32'h0100001c) $fatal("Expected output not received");
        next_pc <= 32'h01000020;
        #10;
        if(pc != 32'h01000020) $fatal("Expected output not received");
        #5;
        rst<=0;
        next_pc <= 32'h01000021;
        #10;
        if(pc != 32'h01000000) $fatal("Expected output not received");
        #5;
        
        $display("All test cases passed");
        $finish;
    end
    
endmodule