data/full_repos/permissive/433619616/7to1_Mux_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b001;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b011;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel <= 3\'b111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433619616/7to1_Mux_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/433619616/7to1_Mux_tb.v:8: Cannot find file containing module: \'mux_7to1\'\n mux_7to1 mux0 ( .in (in),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433619616,data/full_repos/permissive/433619616/mux_7to1\n             data/full_repos/permissive/433619616,data/full_repos/permissive/433619616/mux_7to1.v\n             data/full_repos/permissive/433619616,data/full_repos/permissive/433619616/mux_7to1.sv\n             mux_7to1\n             mux_7to1.v\n             mux_7to1.sv\n             obj_dir/mux_7to1\n             obj_dir/mux_7to1.v\n             obj_dir/mux_7to1.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_7to1_tb;

	reg [6:0] in;
	wire out;
	reg [2:0] sel;

	mux_7to1 mux0 ( .in (in),
					.out (out),
					.sel (sel));

	initial begin
		 in[0] <= 1'b0;
		 in[1] <= 1'b1;
		 in[2] <= 1'b0;
		 in[3] <= 1'b1;
		 in[4] <= 1'b0;
		 in[5] <= 1'b1;
		 in[6] <= 1'b0;

		 sel <= 3'b000; 
		#10 sel <= 3'b001;
		#10 sel <= 3'b010;
		#10 sel <= 3'b011;
		#10 sel <= 3'b100;
		#10 sel <= 3'b101;
		#10 sel <= 3'b110;
		#10 sel <= 3'b111;
		#10;
	end
endmodule
module mux_7to1_tb;


	reg [6:0] in;
	wire out;
	reg [2:0] sel;

	mux_7to1 mux0 ( .in (in),
					.out (out),
					.sel (sel));

	initial begin
		 in[0] <= 1'b0;
		 in[1] <= 1'b1;
		 in[2] <= 1'b0;
		 in[3] <= 1'b1;
		 in[4] <= 1'b0;
		 in[5] <= 1'b1;
		 in[6] <= 1'b0;

		 sel <= 3'b000; 
		#10 sel <= 3'b001;
		#10 sel <= 3'b010;
		#10 sel <= 3'b011;
		#10 sel <= 3'b100;
		#10 sel <= 3'b101;
		#10 sel <= 3'b110;
		#10 sel <= 3'b111;
		#10;
	end
endmodule