data/full_repos/permissive/460468583/data/verilog/display-main.v
1: b"%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:2: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\ninput [`BITMAP_NB_SEGMENTS-1:0] msg;\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:3: Define or directive not defined: '`RNDSIZE'\ninput [`RNDSIZE-1:0] rnd;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:5: Define or directive not defined: '`WIDTH'\noutput [`WIDTH*`HEIGHT-1:0] pix;\n        ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:5: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\noutput [`WIDTH*`HEIGHT-1:0] pix;\n              ^\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:5: Define or directive not defined: '`HEIGHT'\noutput [`WIDTH*`HEIGHT-1:0] pix;\n               ^~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:6: Define or directive not defined: '`RNDSIZE'\nwire [`RNDSIZE*(`RNDSIZE-1)/2-1:0] rndx;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:6: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\nwire [`RNDSIZE*(`RNDSIZE-1)/2-1:0] rndx;\n              ^\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:6: Define or directive not defined: '`RNDSIZE'\nwire [`RNDSIZE*(`RNDSIZE-1)/2-1:0] rndx;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/verilog/display-main.v:7: Define or directive not defined: '`BITMAP_NB_SEGMENTS'\nwire [`BITMAP_NB_SEGMENTS-1:0] selseg;\n      ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module main ( msg , rnd , z , pix );
input [`BITMAP_NB_SEGMENTS-1:0] msg;
input [`RNDSIZE-1:0] rnd;
input z;
output [`WIDTH*`HEIGHT-1:0] pix;
wire [`RNDSIZE*(`RNDSIZE-1)/2-1:0] rndx;
wire [`BITMAP_NB_SEGMENTS-1:0] selseg;

xorexpand xe(.r (rnd), .p (rndx));
rndswitch rs(.s (msg), .r (rndx), .z (z), .o (selseg));
segment2pixel sp(.s (selseg), .p (pix));
endmodule
module main ( msg , rnd , z , pix );

input [`BITMAP_NB_SEGMENTS-1:0] msg;
input [`RNDSIZE-1:0] rnd;
input z;
output [`WIDTH*`HEIGHT-1:0] pix;
wire [`RNDSIZE*(`RNDSIZE-1)/2-1:0] rndx;
wire [`BITMAP_NB_SEGMENTS-1:0] selseg;

xorexpand xe(.r (rnd), .p (rndx));
rndswitch rs(.s (msg), .r (rndx), .z (z), .o (selseg));
segment2pixel sp(.s (selseg), .p (pix));
endmodule