data/full_repos/permissive/468612001/Week04/fulladder_4bit/fulladder_4bit.v
data/verilator_xmls/69bdae6e-bdf6-4671-ae76-afda1c98ee9c.xml
module fulladder_4bit(a, b, cin, sum, cout);
	input [3:0] a, b;
	input cin;
	output [3:0] sum;
	output cout;
	

	wire [2:0] c;
	


	

	
	fulladder_1bit F1(a[0], b[0], cin, sum[0], c[0]);
	fulladder_1bit F2(a[1], b[1], c[0], sum[1], c[1]);
	fulladder_1bit F3(a[2], b[2], c[1], sum[2], c[2]);
	fulladder_1bit F4(a[3], b[3], c[2], sum[3], cout);

endmodule
module fulladder_4bit(a, b, cin, sum, cout);

	input [3:0] a, b;
	input cin;
	output [3:0] sum;
	output cout;
	

	wire [2:0] c;
	


	

	
	fulladder_1bit F1(a[0], b[0], cin, sum[0], c[0]);
	fulladder_1bit F2(a[1], b[1], c[0], sum[1], c[1]);
	fulladder_1bit F3(a[2], b[2], c[1], sum[2], c[2]);
	fulladder_1bit F4(a[3], b[3], c[2], sum[3], cout);

endmodule