data/full_repos/permissive/52900389/DPWM_TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:75: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DPWM_TestBench.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: data/full_repos/permissive/52900389/DPWM_TestBench.v:42: Cannot find file containing module: \'DPWM\'\n DPWM uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DPWM\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DPWM.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DPWM.sv\n             DPWM\n             DPWM.v\n             DPWM.sv\n             obj_dir/DPWM\n             obj_dir/DPWM.v\n             obj_dir/DPWM.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DPWM_TestBench;


	reg CLK_FPGA_BOARD;
	reg boton_aumentar;
	reg boton_disminuir;
	reg seleccion_funcion;
	reg seleccion_salida;
	reg reinicio;


	wire BUCK_Gate;
	wire Full_Bridge;
	wire [3:0] anodos_7seg;
	wire [7:0] catodos_7seg;


	DPWM uut (
		.CLK_FPGA_BOARD(CLK_FPGA_BOARD), 
		.boton_aumentar(boton_aumentar), 
		.boton_disminuir(boton_disminuir), 
		.seleccion_funcion(seleccion_funcion), 
		.seleccion_salida(seleccion_salida), 
		.reinicio(reinicio), 
		.BUCK_Gate(BUCK_Gate), 
		.Full_Bridge(Full_Bridge), 
		.anodos_7seg(anodos_7seg), 
		.catodos_7seg(catodos_7seg)
	);

	initial 
	begin

		CLK_FPGA_BOARD = 0;
		boton_aumentar = 0;
		boton_disminuir = 0;
		seleccion_funcion = 0;
		seleccion_salida = 0;
		reinicio = 0;
	end



		
			
			

		initial 
		begin
		CLK_FPGA_BOARD = 0;
		forever #5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;
		end
        

		
		initial
		begin
		
		reinicio = 1;
		boton_aumentar = 0;
		boton_disminuir = 0;
		seleccion_funcion = 0;
		seleccion_salida = 0;
		#10
		
		reinicio = 0;
		#10
		
		reinicio = 0;
		boton_aumentar = 1;
		#50
		boton_aumentar = 0;
		#20
		boton_aumentar = 1;
		#20
		boton_aumentar = 0;
		boton_disminuir = 0;


		
		end
      
endmodule
module DPWM_TestBench;



	reg CLK_FPGA_BOARD;
	reg boton_aumentar;
	reg boton_disminuir;
	reg seleccion_funcion;
	reg seleccion_salida;
	reg reinicio;


	wire BUCK_Gate;
	wire Full_Bridge;
	wire [3:0] anodos_7seg;
	wire [7:0] catodos_7seg;


	DPWM uut (
		.CLK_FPGA_BOARD(CLK_FPGA_BOARD), 
		.boton_aumentar(boton_aumentar), 
		.boton_disminuir(boton_disminuir), 
		.seleccion_funcion(seleccion_funcion), 
		.seleccion_salida(seleccion_salida), 
		.reinicio(reinicio), 
		.BUCK_Gate(BUCK_Gate), 
		.Full_Bridge(Full_Bridge), 
		.anodos_7seg(anodos_7seg), 
		.catodos_7seg(catodos_7seg)
	);

	initial 
	begin

		CLK_FPGA_BOARD = 0;
		boton_aumentar = 0;
		boton_disminuir = 0;
		seleccion_funcion = 0;
		seleccion_salida = 0;
		reinicio = 0;
	end



		
			
			

		initial 
		begin
		CLK_FPGA_BOARD = 0;
		forever #5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;
		end
        

		
		initial
		begin
		
		reinicio = 1;
		boton_aumentar = 0;
		boton_disminuir = 0;
		seleccion_funcion = 0;
		seleccion_salida = 0;
		#10
		
		reinicio = 0;
		#10
		
		reinicio = 0;
		boton_aumentar = 1;
		#50
		boton_aumentar = 0;
		#20
		boton_aumentar = 1;
		#20
		boton_aumentar = 0;
		boton_disminuir = 0;


		
		end
      
endmodule