data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_synch_jlcl.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_synch_jlcl.v:26: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_clsp_synch_jlcl.v:27: Cannot find include file: ctu.h\n`include "ctu.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ctu_clsp_synch_jlcl(

update_clkctrl_reg_cl, stop_id_vld_cl, sctag3_ctu_tr_cl, 
sctag2_ctu_tr_cl, sctag1_ctu_tr_cl, sctag0_ctu_tr_cl, 
rstctrl_idle_cl, rstctrl_enclk_cl, rstctrl_disclk_cl, 
rd_clkctrl_reg_cl, jbi_ctu_tr_cl, iob_ctu_tr_cl, iob_ctu_l2_tr_cl, 
dram_a_grst_cl, dram13_ctu_tr_cl, dram02_ctu_tr_cl, de_grst_cl, 
de_dbginit_cl, dbgtrig_dly_cnt_val_cl, ctu_sparc7_cmp_cken_cg, 
ctu_sparc6_cmp_cken_cg, ctu_sparc5_cmp_cken_cg, 
ctu_sparc4_cmp_cken_cg, ctu_sparc3_cmp_cken_cg, 
ctu_sparc2_cmp_cken_cg, ctu_sparc1_cmp_cken_cg, 
ctu_sparc0_cmp_cken_cg, ctu_sctag3_cmp_cken_cg, 
ctu_sctag2_cmp_cken_cg, ctu_sctag1_cmp_cken_cg, 
ctu_sctag0_cmp_cken_cg, ctu_scdata3_cmp_cken_cg, 
ctu_scdata2_cmp_cken_cg, ctu_scdata1_cmp_cken_cg, 
ctu_scdata0_cmp_cken_cg, ctu_misc_cken_pre_jl, ctu_jbusr_cken_pre_jl, 
ctu_jbusl_cken_pre_jl, ctu_jbi_cmp_cken_cg, ctu_jbi_cken_pre_jl, 
ctu_iob_cmp_cken_cg, ctu_iob_cken_pre_jl, ctu_io_j_err_jl, 
ctu_fpu_cmp_cken_cg, ctu_efc_cken_pre_jl, ctu_dram13_cmp_cken_cg, 
ctu_dram13_cken_pre_jl, ctu_dram02_cmp_cken_cg, 
ctu_dram02_cken_pre_jl, ctu_dbg_cken_pre_jl, ctu_ccx_cmp_cken_cg, 
creg_cken_vld_cl, clsp_ctrl_srarm_pre_jl, clkctrl_dn_jl, a_grst_cl, 
a_dbginit_cl, start_clk_cl, update_shadow_cl, 

stop_id_vld_jl, sctag3_ctu_tr, sctag2_ctu_tr, sctag1_ctu_tr, 
sctag0_ctu_tr, rstctrl_idle_jl, rstctrl_enclk_jl, rstctrl_disclk_jl, 
jbus_tx_sync, jbi_ctu_tr_jl, iob_ctu_tr_jl, iob_ctu_l2_tr_jl, 
dram_a_grst_jl, dram13_ctu_tr_jl, dram02_ctu_tr_jl, de_grst_jl, 
de_dbginit_jl, dbgtrig_dly_cnt_val, ctu_sparc7_cken_cl, 
ctu_sparc6_cken_cl, ctu_sparc5_cken_cl, ctu_sparc4_cken_cl, 
ctu_sparc3_cken_cl, ctu_sparc2_cken_cl, ctu_sparc1_cken_cl, 
ctu_sparc0_cken_cl, ctu_sctag3_cken_cl, ctu_sctag2_cken_cl, 
ctu_sctag1_cken_cl, ctu_sctag0_cken_cl, ctu_scdata3_cken_cl, 
ctu_scdata2_cken_cl, ctu_scdata1_cken_cl, ctu_scdata0_cken_cl, 
ctu_jbi_cken_cl, ctu_iob_cken_cl, ctu_io_j_err_cl, ctu_fpu_cken_cl, 
ctu_efc_cken_cl, ctu_dram13_cken_cl, ctu_dram02_cken_cl, 
ctu_ccx_cken_cl, creg_cken_vld_jl, cmp_clk, clsp_ctrl_srarm_cl, 
clkctrl_dn_cl, a_grst_jl, a_dbginit_jl, jbus_rx_sync, io_pwron_rst_l, 
update_shadow_jl, ctu_jbus_rx_sync_cl, ctu_jbusr_cken_cl, 
ctu_jbusl_cken_cl, ctu_misc_cken_cl, ctu_dbg_cken_cl, 
update_clkctrl_reg_jl, rd_clkctrl_reg_jl, start_clk_early_jl, 
jtag_clsp_force_cken_cmp, testmode_l
);



input			a_dbginit_jl;
input			a_grst_jl;
input			clkctrl_dn_cl;
input			clsp_ctrl_srarm_cl;
input			cmp_clk;
input			creg_cken_vld_jl;
input			ctu_ccx_cken_cl;
input			ctu_dram02_cken_cl;
input			ctu_dram13_cken_cl;
input			ctu_efc_cken_cl;
input			ctu_fpu_cken_cl;
input			ctu_io_j_err_cl;
input			ctu_iob_cken_cl;
input			ctu_jbi_cken_cl;
input			ctu_scdata0_cken_cl;
input			ctu_scdata1_cken_cl;
input			ctu_scdata2_cken_cl;
input			ctu_scdata3_cken_cl;
input			ctu_sctag0_cken_cl;
input			ctu_sctag1_cken_cl;
input			ctu_sctag2_cken_cl;
input			ctu_sctag3_cken_cl;
input			ctu_sparc0_cken_cl;
input			ctu_sparc1_cken_cl;
input			ctu_sparc2_cken_cl;
input			ctu_sparc3_cken_cl;
input			ctu_sparc4_cken_cl;
input			ctu_sparc5_cken_cl;
input			ctu_sparc6_cken_cl;
input			ctu_sparc7_cken_cl;
input [4:0]		dbgtrig_dly_cnt_val;
input			de_dbginit_jl;
input			de_grst_jl;
input			dram02_ctu_tr_jl;
input			dram13_ctu_tr_jl;
input			dram_a_grst_jl;
input			iob_ctu_l2_tr_jl;
input			iob_ctu_tr_jl;
input			jbi_ctu_tr_jl;
input			jbus_tx_sync;
input			rstctrl_disclk_jl;
input			rstctrl_enclk_jl;
input			rstctrl_idle_jl;
input			sctag0_ctu_tr;
input			sctag1_ctu_tr;
input			sctag2_ctu_tr;
input			sctag3_ctu_tr;
input			stop_id_vld_jl;

input			jbus_rx_sync;
input                   io_pwron_rst_l;
input			update_shadow_jl;
input                   ctu_jbus_rx_sync_cl;
input                   ctu_jbusr_cken_cl;
input                   ctu_jbusl_cken_cl;
input                   ctu_misc_cken_cl;
input                   ctu_dbg_cken_cl;
input                   update_clkctrl_reg_jl;
input                   rd_clkctrl_reg_jl;
input                   start_clk_early_jl;
input                   jtag_clsp_force_cken_cmp;
input                   testmode_l;



output			a_dbginit_cl;
output			a_grst_cl;
output			clkctrl_dn_jl;
output			clsp_ctrl_srarm_pre_jl;
output			creg_cken_vld_cl;
output			ctu_ccx_cmp_cken_cg;
output			ctu_dbg_cken_pre_jl;
output			ctu_dram02_cken_pre_jl;
output			ctu_dram02_cmp_cken_cg;
output			ctu_dram13_cken_pre_jl;
output			ctu_dram13_cmp_cken_cg;
output			ctu_efc_cken_pre_jl;
output			ctu_fpu_cmp_cken_cg;
output			ctu_io_j_err_jl;
output			ctu_iob_cken_pre_jl;
output			ctu_iob_cmp_cken_cg;
output			ctu_jbi_cken_pre_jl;
output			ctu_jbi_cmp_cken_cg;
output			ctu_jbusl_cken_pre_jl;
output			ctu_jbusr_cken_pre_jl;
output			ctu_misc_cken_pre_jl;
output			ctu_scdata0_cmp_cken_cg;
output			ctu_scdata1_cmp_cken_cg;
output			ctu_scdata2_cmp_cken_cg;
output			ctu_scdata3_cmp_cken_cg;
output			ctu_sctag0_cmp_cken_cg;
output			ctu_sctag1_cmp_cken_cg;
output			ctu_sctag2_cmp_cken_cg;
output			ctu_sctag3_cmp_cken_cg;
output			ctu_sparc0_cmp_cken_cg;
output			ctu_sparc1_cmp_cken_cg;
output			ctu_sparc2_cmp_cken_cg;
output			ctu_sparc3_cmp_cken_cg;
output			ctu_sparc4_cmp_cken_cg;
output			ctu_sparc5_cmp_cken_cg;
output			ctu_sparc6_cmp_cken_cg;
output			ctu_sparc7_cmp_cken_cg;
output [4:0]		dbgtrig_dly_cnt_val_cl;
output			de_dbginit_cl;
output			de_grst_cl;
output			dram02_ctu_tr_cl;
output			dram13_ctu_tr_cl;
output			dram_a_grst_cl;
output			iob_ctu_l2_tr_cl;
output			iob_ctu_tr_cl;
output			jbi_ctu_tr_cl;
output			rd_clkctrl_reg_cl;
output			rstctrl_disclk_cl;
output			rstctrl_enclk_cl;
output			rstctrl_idle_cl;
output			sctag0_ctu_tr_cl;
output			sctag1_ctu_tr_cl;
output			sctag2_ctu_tr_cl;
output			sctag3_ctu_tr_cl;
output			stop_id_vld_cl;
output			update_clkctrl_reg_cl;

output			start_clk_cl;
output			update_shadow_cl;


wire			sctag0_ctu_tr_ff;
wire			sctag1_ctu_tr_ff;
wire			sctag2_ctu_tr_ff;
wire			sctag3_ctu_tr_ff;




wire ctu_jbusl_cken_jl_nxt;
wire ctu_jbusr_cken_jl_nxt;
wire ctu_jbusl_cken_pre_jl;
wire ctu_jbusr_cken_pre_jl;
wire update_clkctrl_reg_jl_nxt;
wire rd_clkctrl_reg_jl_nxt;
wire ctu_misc_cken_jl_nxt;
wire ctu_dbg_cken_jl_nxt;
wire start_clk_sync_nxt;



wire start_clk_tmp_nxt;
wire start_clk_tmp;
wire start_clk_dly_nxt;
wire start_clk_dly1;
wire start_clk_dly2;
wire start_clk_dly3;
wire start_clk_dly4;
wire start_clk_dly5;
wire start_clk_dly6;
wire start_clk_dly7;
wire update_shadow_cl_nxt;
wire force_cken ;


    assign force_cken = jtag_clsp_force_cken_cmp | ~testmode_l;


    assign  start_clk_tmp_nxt = ctu_jbus_rx_sync_cl? 1'b1: start_clk_tmp;

    dffrl_async_ns  u_start_clk_tmp(
                   .din (start_clk_tmp_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_tmp));

    assign  start_clk_dly_nxt = ctu_jbus_rx_sync_cl & start_clk_tmp ? 1'b1: start_clk_dly1;

    dffrl_async_ns  u_start_clk_dly1(
                   .din (start_clk_dly_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly1));

    dffrl_async_ns  u_start_clk_dly2(
                   .din (start_clk_dly1),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly2));

    dffrl_async_ns  u_start_clk_dly3(
                   .din (start_clk_dly2),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly3));

    dffrl_async_ns  u_start_clk_dly4(
                   .din (start_clk_dly3),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly4));

    dffrl_async_ns  u_start_clk_dly5(
                   .din (start_clk_dly4),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly5));

    dffrl_async_ns  u_start_clk_dly6(
                   .din (start_clk_dly5),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly6));

    dffrl_async_ns  u_start_clk_dly7(
                   .din (start_clk_dly6),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly7));








    assign start_clk_sync_nxt = (jbus_rx_sync ?  start_clk_early_jl : start_clk_cl) & start_clk_dly7;

    dffrl_async_ns  u_start_clk_cl(
                   .din (start_clk_sync_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_cl));


    assign update_shadow_cl_nxt = (jbus_rx_sync ? update_shadow_jl : update_shadow_cl) & start_clk_cl;

    dffrl_async_ns  u_update_shadow_cl(
                   .din (update_shadow_cl_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (update_shadow_cl));




   ctu_synch_cl_cg u_ctu_sparc0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc0_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc0_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc1_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc1_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc2_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc2_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc3_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc3_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc4_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc4_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc4_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc5_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc5_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc5_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc6_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc6_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc6_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc7_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc7_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc7_cken_cl));


   ctu_synch_cl_cg u_ctu_scdata0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata0_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata0_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata1_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata1_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata2_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata2_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata3_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata3_cken_cl));
    



   ctu_synch_cl_cg u_ctu_sctag0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag0_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag0_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag1_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag1_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag2_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag2_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag3_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag3_cken_cl));


   ctu_synch_cl_cg u_ctu_ccx_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_ccx_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_ccx_cken_cl));


   ctu_synch_cl_cg u_ctu_fpu_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_fpu_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_fpu_cken_cl));



   ctu_synch_cl_cg u_ctu_iob_cmp_cken_cl(
					    .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_iob_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_iob_cken_cl));


   ctu_synch_cl_cg u_ctu_jbi_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_jbi_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_jbi_cken_cl));


   ctu_synch_cl_cg u_ctu_dram02_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_dram02_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_dram02_cken_cl));


   ctu_synch_cl_cg u_ctu_dram13_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_dram13_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_dram13_cken_cl));




     dffrle_ns  u_grst_en(
			  .rst_l	(start_clk_cl),


			  .q		(de_grst_cl),

			  .din		(de_grst_jl),
			  .en		(jbus_rx_sync),
			  .clk		(cmp_clk));


     dffrle_ns u_grst_dis(
			  .rst_l	(start_clk_cl),


			  .q		(a_grst_cl),

			  .din		(a_grst_jl),
			  .en		(jbus_rx_sync),
			  .clk		(cmp_clk));


    dffrle_ns u_dram_grst_dis(
			      .rst_l	(start_clk_cl),


			      .q	(dram_a_grst_cl),

			      .din	(dram_a_grst_jl),
			      .en	(jbus_rx_sync),
			      .clk	(cmp_clk));






     dffrle_ns u_de_dbginit(
			       .rst_l	(start_clk_cl),


			    .q		(de_dbginit_cl),

			    .din	(de_dbginit_jl),
			    .en		(jbus_rx_sync),
			    .clk	(cmp_clk));



     dffrle_ns u_a_dbginit(
			       .rst_l	(start_clk_cl),


			   .q		(a_dbginit_cl),

			   .din		(a_dbginit_jl),
			   .en		(jbus_rx_sync),
			   .clk		(cmp_clk));





     dffrl_ns u_sctag0_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag0_ctu_tr_ff),

				  .din	(sctag0_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag1_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag1_ctu_tr_ff),

				  .din	(sctag1_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag2_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag2_ctu_tr_ff),

				  .din	(sctag2_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag3_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag3_ctu_tr_ff),

				  .din	(sctag3_ctu_tr),
				  .clk	(cmp_clk));


     dffrl_ns u_sctag0_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag0_ctu_tr_cl),

				  .din	(sctag0_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag1_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag1_ctu_tr_cl),

				  .din	(sctag1_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag2_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag2_ctu_tr_cl),

				  .din	(sctag2_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag3_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag3_ctu_tr_cl),

				  .din	(sctag3_ctu_tr_ff),
				  .clk	(cmp_clk));
      


     dffrle_ns u_creg_cken_vld_cl( .rst_l	(start_clk_cl),

				  .q	(creg_cken_vld_cl),

				  .din	(creg_cken_vld_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));


     dffrle_ns u_rstctrl_idle_cl( .rst_l	(start_clk_cl),

				 .q	(rstctrl_idle_cl),

				 .din	(rstctrl_idle_jl),
				 .en	(jbus_rx_sync),
				 .clk	(cmp_clk));


     dffrle_ns u_rstctrl_disclk_cl( .rst_l	(start_clk_cl),

				   .q	(rstctrl_disclk_cl),

				   .din	(rstctrl_disclk_jl),
				   .en	(jbus_rx_sync),
				   .clk	(cmp_clk));



     dffrle_ns u_rstctrl_enclk_cl( .rst_l	(start_clk_cl),

				  .q	(rstctrl_enclk_cl),

				  .din	(rstctrl_enclk_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));



     dffrle_ns u_iob_ctu_tr_cl( .rst_l	(start_clk_cl),

			       .q	(iob_ctu_tr_cl),

			       .din	(iob_ctu_tr_jl),
			       .en	(jbus_rx_sync),
			       .clk	(cmp_clk));


     dffrle_ns u_dram02_ctu_tr_cl( .rst_l	(start_clk_cl),

				  .q	(dram02_ctu_tr_cl),

				  .din	(dram02_ctu_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));
     dffrle_ns u_dram13_ctu_tr_cl( .rst_l	(start_clk_cl),

				  .q	(dram13_ctu_tr_cl),

				  .din	(dram13_ctu_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));


     dffrle_ns u_jbi_ctu_tr_cl( .rst_l	(start_clk_cl),

			       .q	(jbi_ctu_tr_cl),

			       .din	(jbi_ctu_tr_jl),
			       .en	(jbus_rx_sync),
			       .clk	(cmp_clk));



     dffrle_ns u_iob_ctu_l2_tr_cl( .rst_l	(start_clk_cl),

				  .q	(iob_ctu_l2_tr_cl),

				  .din	(iob_ctu_l2_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));




     dffrle_ns u_stop_id_vld_cl( .rst_l	(start_clk_cl),

				.q	(stop_id_vld_cl),

				.din	(stop_id_vld_jl),
				.en	(jbus_rx_sync),
				.clk	(cmp_clk));












     dffrle_ns #(5) u_dbgtrig_dly_cnt_val ( .rst_l	(start_clk_cl),

					   .q(dbgtrig_dly_cnt_val_cl[4:0]),

					   .din(dbgtrig_dly_cnt_val[4:0]),
					   .en(jbus_rx_sync),
					   .clk(cmp_clk));


   
     assign update_clkctrl_reg_jl_nxt = (jbus_rx_sync ? update_clkctrl_reg_jl : update_clkctrl_reg_cl)
				        & start_clk_cl;

     dffrl_async_ns u_update_clkctrl_reg_cl( .din (update_clkctrl_reg_jl_nxt),

					    .q(update_clkctrl_reg_cl),

					    .clk(cmp_clk),
					    .rst_l(io_pwron_rst_l));


     assign rd_clkctrl_reg_jl_nxt = (jbus_rx_sync ? rd_clkctrl_reg_jl : rd_clkctrl_reg_cl)
				        & start_clk_cl;

     dffrl_async_ns u_rd_clkctrl_reg_jl( .din (rd_clkctrl_reg_jl_nxt),

					.q(rd_clkctrl_reg_cl),

					.clk(cmp_clk),
					.rst_l(io_pwron_rst_l));





     dffrle_ns u_clkctrl_dn_jl ( .rst_l        (start_clk_cl),

				.q	(clkctrl_dn_jl),

				.din	(clkctrl_dn_cl),
				.en	(jbus_tx_sync),
				.clk	(cmp_clk));


     dffrle_ns u_ctu_io_j_err_jl ( .rst_l        (start_clk_cl),

				  .q	(ctu_io_j_err_jl),

				  .din	(ctu_io_j_err_cl),
				  .en	(jbus_tx_sync),
				  .clk	(cmp_clk));



     dffrle_ns u_ctu_dram02_cken_jl( .rst_l	(start_clk_cl),

				    .q	(ctu_dram02_cken_pre_jl),

				    .din(ctu_dram02_cken_cl),
				    .en	(jbus_tx_sync),
				    .clk(cmp_clk));
     dffrle_ns u_ctu_dram13_cken_jl( .rst_l	(start_clk_cl),

				    .q	(ctu_dram13_cken_pre_jl),

				    .din(ctu_dram13_cken_cl),
				    .en	(jbus_tx_sync),
				    .clk(cmp_clk));



     dffrle_ns u_ctu_iob_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_iob_cken_pre_jl),

				 .din	(ctu_iob_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));


     dffrle_ns u_ctu_efc_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_efc_cken_pre_jl),

				 .din	(ctu_efc_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));



     assign ctu_jbusl_cken_jl_nxt =  start_clk_cl ? 
                                     (jbus_rx_sync? ctu_jbusl_cken_cl: ctu_jbusl_cken_pre_jl):
                                      1'b1;
 
     dffsl_async_ns u_ctu_jbusl_cken_jl(
				   .din	(ctu_jbusl_cken_jl_nxt),


					.q(ctu_jbusl_cken_pre_jl),

					.clk(cmp_clk),
					.set_l(io_pwron_rst_l));


     assign ctu_jbusr_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_jbusr_cken_cl:  ctu_jbusr_cken_pre_jl):
                                      1'b1;

     dffsl_async_ns u_ctu_jbusr_cken_jl( 
				   .din	(ctu_jbusr_cken_jl_nxt),


					.q(ctu_jbusr_cken_pre_jl),

					.clk(cmp_clk),
					.set_l(io_pwron_rst_l));



     dffrle_ns u_ctu_jbi_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_jbi_cken_pre_jl),

				 .din	(ctu_jbi_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));



     assign ctu_dbg_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_dbg_cken_cl:  ctu_dbg_cken_pre_jl):
                                      1'b1;
     dffsl_async_ns u_ctu_dbg_cken_jl( .din	(ctu_dbg_cken_jl_nxt),


				      .q(ctu_dbg_cken_pre_jl),

				      .clk(cmp_clk),
				      .set_l(io_pwron_rst_l));




     assign ctu_misc_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_misc_cken_cl:  ctu_misc_cken_pre_jl):
                                      1'b1;
     dffsl_async_ns u_ctu_misc_cken_jl( .din	(ctu_misc_cken_jl_nxt),


				       .q(ctu_misc_cken_pre_jl),

				       .clk(cmp_clk),
				       .set_l(io_pwron_rst_l));




     dffrle_ns u_clsp_ctrl_srarm_pre_jl( .rst_l	(start_clk_cl),

					.q(clsp_ctrl_srarm_pre_jl),

					.din(clsp_ctrl_srarm_cl),
					.en(jbus_tx_sync),
					.clk(cmp_clk));

endmodule
module ctu_clsp_synch_jlcl(

update_clkctrl_reg_cl, stop_id_vld_cl, sctag3_ctu_tr_cl, 
sctag2_ctu_tr_cl, sctag1_ctu_tr_cl, sctag0_ctu_tr_cl, 
rstctrl_idle_cl, rstctrl_enclk_cl, rstctrl_disclk_cl, 
rd_clkctrl_reg_cl, jbi_ctu_tr_cl, iob_ctu_tr_cl, iob_ctu_l2_tr_cl, 
dram_a_grst_cl, dram13_ctu_tr_cl, dram02_ctu_tr_cl, de_grst_cl, 
de_dbginit_cl, dbgtrig_dly_cnt_val_cl, ctu_sparc7_cmp_cken_cg, 
ctu_sparc6_cmp_cken_cg, ctu_sparc5_cmp_cken_cg, 
ctu_sparc4_cmp_cken_cg, ctu_sparc3_cmp_cken_cg, 
ctu_sparc2_cmp_cken_cg, ctu_sparc1_cmp_cken_cg, 
ctu_sparc0_cmp_cken_cg, ctu_sctag3_cmp_cken_cg, 
ctu_sctag2_cmp_cken_cg, ctu_sctag1_cmp_cken_cg, 
ctu_sctag0_cmp_cken_cg, ctu_scdata3_cmp_cken_cg, 
ctu_scdata2_cmp_cken_cg, ctu_scdata1_cmp_cken_cg, 
ctu_scdata0_cmp_cken_cg, ctu_misc_cken_pre_jl, ctu_jbusr_cken_pre_jl, 
ctu_jbusl_cken_pre_jl, ctu_jbi_cmp_cken_cg, ctu_jbi_cken_pre_jl, 
ctu_iob_cmp_cken_cg, ctu_iob_cken_pre_jl, ctu_io_j_err_jl, 
ctu_fpu_cmp_cken_cg, ctu_efc_cken_pre_jl, ctu_dram13_cmp_cken_cg, 
ctu_dram13_cken_pre_jl, ctu_dram02_cmp_cken_cg, 
ctu_dram02_cken_pre_jl, ctu_dbg_cken_pre_jl, ctu_ccx_cmp_cken_cg, 
creg_cken_vld_cl, clsp_ctrl_srarm_pre_jl, clkctrl_dn_jl, a_grst_cl, 
a_dbginit_cl, start_clk_cl, update_shadow_cl, 

stop_id_vld_jl, sctag3_ctu_tr, sctag2_ctu_tr, sctag1_ctu_tr, 
sctag0_ctu_tr, rstctrl_idle_jl, rstctrl_enclk_jl, rstctrl_disclk_jl, 
jbus_tx_sync, jbi_ctu_tr_jl, iob_ctu_tr_jl, iob_ctu_l2_tr_jl, 
dram_a_grst_jl, dram13_ctu_tr_jl, dram02_ctu_tr_jl, de_grst_jl, 
de_dbginit_jl, dbgtrig_dly_cnt_val, ctu_sparc7_cken_cl, 
ctu_sparc6_cken_cl, ctu_sparc5_cken_cl, ctu_sparc4_cken_cl, 
ctu_sparc3_cken_cl, ctu_sparc2_cken_cl, ctu_sparc1_cken_cl, 
ctu_sparc0_cken_cl, ctu_sctag3_cken_cl, ctu_sctag2_cken_cl, 
ctu_sctag1_cken_cl, ctu_sctag0_cken_cl, ctu_scdata3_cken_cl, 
ctu_scdata2_cken_cl, ctu_scdata1_cken_cl, ctu_scdata0_cken_cl, 
ctu_jbi_cken_cl, ctu_iob_cken_cl, ctu_io_j_err_cl, ctu_fpu_cken_cl, 
ctu_efc_cken_cl, ctu_dram13_cken_cl, ctu_dram02_cken_cl, 
ctu_ccx_cken_cl, creg_cken_vld_jl, cmp_clk, clsp_ctrl_srarm_cl, 
clkctrl_dn_cl, a_grst_jl, a_dbginit_jl, jbus_rx_sync, io_pwron_rst_l, 
update_shadow_jl, ctu_jbus_rx_sync_cl, ctu_jbusr_cken_cl, 
ctu_jbusl_cken_cl, ctu_misc_cken_cl, ctu_dbg_cken_cl, 
update_clkctrl_reg_jl, rd_clkctrl_reg_jl, start_clk_early_jl, 
jtag_clsp_force_cken_cmp, testmode_l
);




input			a_dbginit_jl;
input			a_grst_jl;
input			clkctrl_dn_cl;
input			clsp_ctrl_srarm_cl;
input			cmp_clk;
input			creg_cken_vld_jl;
input			ctu_ccx_cken_cl;
input			ctu_dram02_cken_cl;
input			ctu_dram13_cken_cl;
input			ctu_efc_cken_cl;
input			ctu_fpu_cken_cl;
input			ctu_io_j_err_cl;
input			ctu_iob_cken_cl;
input			ctu_jbi_cken_cl;
input			ctu_scdata0_cken_cl;
input			ctu_scdata1_cken_cl;
input			ctu_scdata2_cken_cl;
input			ctu_scdata3_cken_cl;
input			ctu_sctag0_cken_cl;
input			ctu_sctag1_cken_cl;
input			ctu_sctag2_cken_cl;
input			ctu_sctag3_cken_cl;
input			ctu_sparc0_cken_cl;
input			ctu_sparc1_cken_cl;
input			ctu_sparc2_cken_cl;
input			ctu_sparc3_cken_cl;
input			ctu_sparc4_cken_cl;
input			ctu_sparc5_cken_cl;
input			ctu_sparc6_cken_cl;
input			ctu_sparc7_cken_cl;
input [4:0]		dbgtrig_dly_cnt_val;
input			de_dbginit_jl;
input			de_grst_jl;
input			dram02_ctu_tr_jl;
input			dram13_ctu_tr_jl;
input			dram_a_grst_jl;
input			iob_ctu_l2_tr_jl;
input			iob_ctu_tr_jl;
input			jbi_ctu_tr_jl;
input			jbus_tx_sync;
input			rstctrl_disclk_jl;
input			rstctrl_enclk_jl;
input			rstctrl_idle_jl;
input			sctag0_ctu_tr;
input			sctag1_ctu_tr;
input			sctag2_ctu_tr;
input			sctag3_ctu_tr;
input			stop_id_vld_jl;

input			jbus_rx_sync;
input                   io_pwron_rst_l;
input			update_shadow_jl;
input                   ctu_jbus_rx_sync_cl;
input                   ctu_jbusr_cken_cl;
input                   ctu_jbusl_cken_cl;
input                   ctu_misc_cken_cl;
input                   ctu_dbg_cken_cl;
input                   update_clkctrl_reg_jl;
input                   rd_clkctrl_reg_jl;
input                   start_clk_early_jl;
input                   jtag_clsp_force_cken_cmp;
input                   testmode_l;



output			a_dbginit_cl;
output			a_grst_cl;
output			clkctrl_dn_jl;
output			clsp_ctrl_srarm_pre_jl;
output			creg_cken_vld_cl;
output			ctu_ccx_cmp_cken_cg;
output			ctu_dbg_cken_pre_jl;
output			ctu_dram02_cken_pre_jl;
output			ctu_dram02_cmp_cken_cg;
output			ctu_dram13_cken_pre_jl;
output			ctu_dram13_cmp_cken_cg;
output			ctu_efc_cken_pre_jl;
output			ctu_fpu_cmp_cken_cg;
output			ctu_io_j_err_jl;
output			ctu_iob_cken_pre_jl;
output			ctu_iob_cmp_cken_cg;
output			ctu_jbi_cken_pre_jl;
output			ctu_jbi_cmp_cken_cg;
output			ctu_jbusl_cken_pre_jl;
output			ctu_jbusr_cken_pre_jl;
output			ctu_misc_cken_pre_jl;
output			ctu_scdata0_cmp_cken_cg;
output			ctu_scdata1_cmp_cken_cg;
output			ctu_scdata2_cmp_cken_cg;
output			ctu_scdata3_cmp_cken_cg;
output			ctu_sctag0_cmp_cken_cg;
output			ctu_sctag1_cmp_cken_cg;
output			ctu_sctag2_cmp_cken_cg;
output			ctu_sctag3_cmp_cken_cg;
output			ctu_sparc0_cmp_cken_cg;
output			ctu_sparc1_cmp_cken_cg;
output			ctu_sparc2_cmp_cken_cg;
output			ctu_sparc3_cmp_cken_cg;
output			ctu_sparc4_cmp_cken_cg;
output			ctu_sparc5_cmp_cken_cg;
output			ctu_sparc6_cmp_cken_cg;
output			ctu_sparc7_cmp_cken_cg;
output [4:0]		dbgtrig_dly_cnt_val_cl;
output			de_dbginit_cl;
output			de_grst_cl;
output			dram02_ctu_tr_cl;
output			dram13_ctu_tr_cl;
output			dram_a_grst_cl;
output			iob_ctu_l2_tr_cl;
output			iob_ctu_tr_cl;
output			jbi_ctu_tr_cl;
output			rd_clkctrl_reg_cl;
output			rstctrl_disclk_cl;
output			rstctrl_enclk_cl;
output			rstctrl_idle_cl;
output			sctag0_ctu_tr_cl;
output			sctag1_ctu_tr_cl;
output			sctag2_ctu_tr_cl;
output			sctag3_ctu_tr_cl;
output			stop_id_vld_cl;
output			update_clkctrl_reg_cl;

output			start_clk_cl;
output			update_shadow_cl;


wire			sctag0_ctu_tr_ff;
wire			sctag1_ctu_tr_ff;
wire			sctag2_ctu_tr_ff;
wire			sctag3_ctu_tr_ff;




wire ctu_jbusl_cken_jl_nxt;
wire ctu_jbusr_cken_jl_nxt;
wire ctu_jbusl_cken_pre_jl;
wire ctu_jbusr_cken_pre_jl;
wire update_clkctrl_reg_jl_nxt;
wire rd_clkctrl_reg_jl_nxt;
wire ctu_misc_cken_jl_nxt;
wire ctu_dbg_cken_jl_nxt;
wire start_clk_sync_nxt;



wire start_clk_tmp_nxt;
wire start_clk_tmp;
wire start_clk_dly_nxt;
wire start_clk_dly1;
wire start_clk_dly2;
wire start_clk_dly3;
wire start_clk_dly4;
wire start_clk_dly5;
wire start_clk_dly6;
wire start_clk_dly7;
wire update_shadow_cl_nxt;
wire force_cken ;


    assign force_cken = jtag_clsp_force_cken_cmp | ~testmode_l;


    assign  start_clk_tmp_nxt = ctu_jbus_rx_sync_cl? 1'b1: start_clk_tmp;

    dffrl_async_ns  u_start_clk_tmp(
                   .din (start_clk_tmp_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_tmp));

    assign  start_clk_dly_nxt = ctu_jbus_rx_sync_cl & start_clk_tmp ? 1'b1: start_clk_dly1;

    dffrl_async_ns  u_start_clk_dly1(
                   .din (start_clk_dly_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly1));

    dffrl_async_ns  u_start_clk_dly2(
                   .din (start_clk_dly1),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly2));

    dffrl_async_ns  u_start_clk_dly3(
                   .din (start_clk_dly2),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly3));

    dffrl_async_ns  u_start_clk_dly4(
                   .din (start_clk_dly3),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly4));

    dffrl_async_ns  u_start_clk_dly5(
                   .din (start_clk_dly4),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly5));

    dffrl_async_ns  u_start_clk_dly6(
                   .din (start_clk_dly5),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly6));

    dffrl_async_ns  u_start_clk_dly7(
                   .din (start_clk_dly6),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_dly7));








    assign start_clk_sync_nxt = (jbus_rx_sync ?  start_clk_early_jl : start_clk_cl) & start_clk_dly7;

    dffrl_async_ns  u_start_clk_cl(
                   .din (start_clk_sync_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (start_clk_cl));


    assign update_shadow_cl_nxt = (jbus_rx_sync ? update_shadow_jl : update_shadow_cl) & start_clk_cl;

    dffrl_async_ns  u_update_shadow_cl(
                   .din (update_shadow_cl_nxt),
                   .clk (cmp_clk),
                   .rst_l(io_pwron_rst_l),
                   .q (update_shadow_cl));




   ctu_synch_cl_cg u_ctu_sparc0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc0_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc0_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc1_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc1_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc2_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc2_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc3_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc3_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc4_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc4_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc4_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc5_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc5_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc5_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc6_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc6_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc6_cken_cl));
   ctu_synch_cl_cg u_ctu_sparc7_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sparc7_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sparc7_cken_cl));


   ctu_synch_cl_cg u_ctu_scdata0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata0_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata0_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata1_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata1_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata2_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata2_cken_cl));
   ctu_synch_cl_cg u_ctu_scdata3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					     .syncdata(ctu_scdata3_cmp_cken_cg),

					     .cmp_clk(cmp_clk),
					     .arst_l(io_pwron_rst_l),
					     .force_cken(force_cken),
					     .presyncdata(ctu_scdata3_cken_cl));
    



   ctu_synch_cl_cg u_ctu_sctag0_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag0_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag0_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag1_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag1_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag1_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag2_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag2_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag2_cken_cl));
   ctu_synch_cl_cg u_ctu_sctag3_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_sctag3_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_sctag3_cken_cl));


   ctu_synch_cl_cg u_ctu_ccx_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_ccx_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_ccx_cken_cl));


   ctu_synch_cl_cg u_ctu_fpu_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_fpu_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_fpu_cken_cl));



   ctu_synch_cl_cg u_ctu_iob_cmp_cken_cl(
					    .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_iob_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_iob_cken_cl));


   ctu_synch_cl_cg u_ctu_jbi_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					 .syncdata(ctu_jbi_cmp_cken_cg),

					 .cmp_clk(cmp_clk),
					 .arst_l(io_pwron_rst_l),
					 .force_cken(force_cken),
					 .presyncdata(ctu_jbi_cken_cl));


   ctu_synch_cl_cg u_ctu_dram02_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_dram02_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_dram02_cken_cl));


   ctu_synch_cl_cg u_ctu_dram13_cmp_cken_cl(
					       .start_clk_cl(start_clk_cl),


					    .syncdata(ctu_dram13_cmp_cken_cg),

					    .cmp_clk(cmp_clk),
					    .arst_l(io_pwron_rst_l),
					    .force_cken(force_cken),
					    .presyncdata(ctu_dram13_cken_cl));




     dffrle_ns  u_grst_en(
			  .rst_l	(start_clk_cl),


			  .q		(de_grst_cl),

			  .din		(de_grst_jl),
			  .en		(jbus_rx_sync),
			  .clk		(cmp_clk));


     dffrle_ns u_grst_dis(
			  .rst_l	(start_clk_cl),


			  .q		(a_grst_cl),

			  .din		(a_grst_jl),
			  .en		(jbus_rx_sync),
			  .clk		(cmp_clk));


    dffrle_ns u_dram_grst_dis(
			      .rst_l	(start_clk_cl),


			      .q	(dram_a_grst_cl),

			      .din	(dram_a_grst_jl),
			      .en	(jbus_rx_sync),
			      .clk	(cmp_clk));






     dffrle_ns u_de_dbginit(
			       .rst_l	(start_clk_cl),


			    .q		(de_dbginit_cl),

			    .din	(de_dbginit_jl),
			    .en		(jbus_rx_sync),
			    .clk	(cmp_clk));



     dffrle_ns u_a_dbginit(
			       .rst_l	(start_clk_cl),


			   .q		(a_dbginit_cl),

			   .din		(a_dbginit_jl),
			   .en		(jbus_rx_sync),
			   .clk		(cmp_clk));





     dffrl_ns u_sctag0_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag0_ctu_tr_ff),

				  .din	(sctag0_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag1_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag1_ctu_tr_ff),

				  .din	(sctag1_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag2_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag2_ctu_tr_ff),

				  .din	(sctag2_ctu_tr),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag3_ctu_tr_ff ( .rst_l	(start_clk_cl),

				  .q	(sctag3_ctu_tr_ff),

				  .din	(sctag3_ctu_tr),
				  .clk	(cmp_clk));


     dffrl_ns u_sctag0_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag0_ctu_tr_cl),

				  .din	(sctag0_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag1_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag1_ctu_tr_cl),

				  .din	(sctag1_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag2_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag2_ctu_tr_cl),

				  .din	(sctag2_ctu_tr_ff),
				  .clk	(cmp_clk));
     dffrl_ns u_sctag3_ctu_tr_cl ( .rst_l	(start_clk_cl),

				  .q	(sctag3_ctu_tr_cl),

				  .din	(sctag3_ctu_tr_ff),
				  .clk	(cmp_clk));
      


     dffrle_ns u_creg_cken_vld_cl( .rst_l	(start_clk_cl),

				  .q	(creg_cken_vld_cl),

				  .din	(creg_cken_vld_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));


     dffrle_ns u_rstctrl_idle_cl( .rst_l	(start_clk_cl),

				 .q	(rstctrl_idle_cl),

				 .din	(rstctrl_idle_jl),
				 .en	(jbus_rx_sync),
				 .clk	(cmp_clk));


     dffrle_ns u_rstctrl_disclk_cl( .rst_l	(start_clk_cl),

				   .q	(rstctrl_disclk_cl),

				   .din	(rstctrl_disclk_jl),
				   .en	(jbus_rx_sync),
				   .clk	(cmp_clk));



     dffrle_ns u_rstctrl_enclk_cl( .rst_l	(start_clk_cl),

				  .q	(rstctrl_enclk_cl),

				  .din	(rstctrl_enclk_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));



     dffrle_ns u_iob_ctu_tr_cl( .rst_l	(start_clk_cl),

			       .q	(iob_ctu_tr_cl),

			       .din	(iob_ctu_tr_jl),
			       .en	(jbus_rx_sync),
			       .clk	(cmp_clk));


     dffrle_ns u_dram02_ctu_tr_cl( .rst_l	(start_clk_cl),

				  .q	(dram02_ctu_tr_cl),

				  .din	(dram02_ctu_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));
     dffrle_ns u_dram13_ctu_tr_cl( .rst_l	(start_clk_cl),

				  .q	(dram13_ctu_tr_cl),

				  .din	(dram13_ctu_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));


     dffrle_ns u_jbi_ctu_tr_cl( .rst_l	(start_clk_cl),

			       .q	(jbi_ctu_tr_cl),

			       .din	(jbi_ctu_tr_jl),
			       .en	(jbus_rx_sync),
			       .clk	(cmp_clk));



     dffrle_ns u_iob_ctu_l2_tr_cl( .rst_l	(start_clk_cl),

				  .q	(iob_ctu_l2_tr_cl),

				  .din	(iob_ctu_l2_tr_jl),
				  .en	(jbus_rx_sync),
				  .clk	(cmp_clk));




     dffrle_ns u_stop_id_vld_cl( .rst_l	(start_clk_cl),

				.q	(stop_id_vld_cl),

				.din	(stop_id_vld_jl),
				.en	(jbus_rx_sync),
				.clk	(cmp_clk));












     dffrle_ns #(5) u_dbgtrig_dly_cnt_val ( .rst_l	(start_clk_cl),

					   .q(dbgtrig_dly_cnt_val_cl[4:0]),

					   .din(dbgtrig_dly_cnt_val[4:0]),
					   .en(jbus_rx_sync),
					   .clk(cmp_clk));


   
     assign update_clkctrl_reg_jl_nxt = (jbus_rx_sync ? update_clkctrl_reg_jl : update_clkctrl_reg_cl)
				        & start_clk_cl;

     dffrl_async_ns u_update_clkctrl_reg_cl( .din (update_clkctrl_reg_jl_nxt),

					    .q(update_clkctrl_reg_cl),

					    .clk(cmp_clk),
					    .rst_l(io_pwron_rst_l));


     assign rd_clkctrl_reg_jl_nxt = (jbus_rx_sync ? rd_clkctrl_reg_jl : rd_clkctrl_reg_cl)
				        & start_clk_cl;

     dffrl_async_ns u_rd_clkctrl_reg_jl( .din (rd_clkctrl_reg_jl_nxt),

					.q(rd_clkctrl_reg_cl),

					.clk(cmp_clk),
					.rst_l(io_pwron_rst_l));





     dffrle_ns u_clkctrl_dn_jl ( .rst_l        (start_clk_cl),

				.q	(clkctrl_dn_jl),

				.din	(clkctrl_dn_cl),
				.en	(jbus_tx_sync),
				.clk	(cmp_clk));


     dffrle_ns u_ctu_io_j_err_jl ( .rst_l        (start_clk_cl),

				  .q	(ctu_io_j_err_jl),

				  .din	(ctu_io_j_err_cl),
				  .en	(jbus_tx_sync),
				  .clk	(cmp_clk));



     dffrle_ns u_ctu_dram02_cken_jl( .rst_l	(start_clk_cl),

				    .q	(ctu_dram02_cken_pre_jl),

				    .din(ctu_dram02_cken_cl),
				    .en	(jbus_tx_sync),
				    .clk(cmp_clk));
     dffrle_ns u_ctu_dram13_cken_jl( .rst_l	(start_clk_cl),

				    .q	(ctu_dram13_cken_pre_jl),

				    .din(ctu_dram13_cken_cl),
				    .en	(jbus_tx_sync),
				    .clk(cmp_clk));



     dffrle_ns u_ctu_iob_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_iob_cken_pre_jl),

				 .din	(ctu_iob_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));


     dffrle_ns u_ctu_efc_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_efc_cken_pre_jl),

				 .din	(ctu_efc_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));



     assign ctu_jbusl_cken_jl_nxt =  start_clk_cl ? 
                                     (jbus_rx_sync? ctu_jbusl_cken_cl: ctu_jbusl_cken_pre_jl):
                                      1'b1;
 
     dffsl_async_ns u_ctu_jbusl_cken_jl(
				   .din	(ctu_jbusl_cken_jl_nxt),


					.q(ctu_jbusl_cken_pre_jl),

					.clk(cmp_clk),
					.set_l(io_pwron_rst_l));


     assign ctu_jbusr_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_jbusr_cken_cl:  ctu_jbusr_cken_pre_jl):
                                      1'b1;

     dffsl_async_ns u_ctu_jbusr_cken_jl( 
				   .din	(ctu_jbusr_cken_jl_nxt),


					.q(ctu_jbusr_cken_pre_jl),

					.clk(cmp_clk),
					.set_l(io_pwron_rst_l));



     dffrle_ns u_ctu_jbi_cken_jl( .rst_l	(start_clk_cl),

				 .q	(ctu_jbi_cken_pre_jl),

				 .din	(ctu_jbi_cken_cl),
				 .en	(jbus_tx_sync),
				 .clk	(cmp_clk));



     assign ctu_dbg_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_dbg_cken_cl:  ctu_dbg_cken_pre_jl):
                                      1'b1;
     dffsl_async_ns u_ctu_dbg_cken_jl( .din	(ctu_dbg_cken_jl_nxt),


				      .q(ctu_dbg_cken_pre_jl),

				      .clk(cmp_clk),
				      .set_l(io_pwron_rst_l));




     assign ctu_misc_cken_jl_nxt =   start_clk_cl ? 
                                      (jbus_rx_sync  ? ctu_misc_cken_cl:  ctu_misc_cken_pre_jl):
                                      1'b1;
     dffsl_async_ns u_ctu_misc_cken_jl( .din	(ctu_misc_cken_jl_nxt),


				       .q(ctu_misc_cken_pre_jl),

				       .clk(cmp_clk),
				       .set_l(io_pwron_rst_l));




     dffrle_ns u_clsp_ctrl_srarm_pre_jl( .rst_l	(start_clk_cl),

					.q(clsp_ctrl_srarm_pre_jl),

					.din(clsp_ctrl_srarm_cl),
					.en(jbus_tx_sync),
					.clk(cmp_clk));

endmodule