data/full_repos/permissive/426611218/MIPS32_Processor.v
1: b'%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:1: Cannot find include file: PC.v\n`include "PC.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/426611218,data/full_repos/permissive/426611218/PC.v\n             data/full_repos/permissive/426611218,data/full_repos/permissive/426611218/PC.v.v\n             data/full_repos/permissive/426611218,data/full_repos/permissive/426611218/PC.v.sv\n             PC.v\n             PC.v.v\n             PC.v.sv\n             obj_dir/PC.v\n             obj_dir/PC.v.v\n             obj_dir/PC.v.sv\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:2: Cannot find include file: ControlUnit.v\n`include "ControlUnit.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:3: Cannot find include file: DataMemory.v\n`include "DataMemory.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:4: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:5: Cannot find include file: ALU_cntrl.v\n`include "ALU_cntrl.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:6: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/426611218/MIPS32_Processor.v:7: Cannot find include file: Ins_mem.v\n`include "Ins_mem.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module MIPS32_Processor (
    input clk, rst,
    output [31:0] result, pc_cnt_out
);

    wire RegDst, MemtoReg, Jump, Branch, MemRead, MemWrite, ALUSrc, RegWrite, Branchn, zero_flag, carry_flag, AndG1, AndG2, XORG1;
    wire [1:0] ALUOp;
    wire [3:0] ALUControl;
    wire [4:0] reg_r_addr_1, reg_r_addr_2, reg_w_dest, reg_w_dest_mux;
    wire [5:0] Opcode, Function;
    wire [15:0] immediate;
    wire [31:0] instr, reg_w_data, reg_r_data_1, reg_r_data_2, A, B, ALU_out, Dmem_out, Branch_addr;

    
    PC pc(clk, rst, Jump, pc_cnt_in, pc_cnt_out);        
    Ins_mem Imem(pc_cnt_out, instr);




    assign Opcode = instr[31:26];
    assign reg_r_addr_1 = instr[25:21];
    assign reg_r_addr_2 = instr[20:16];
    assign reg_w_dest_mux_in = instr[15:11];
    assign immediate = instr[15:0]; 
    assign Function = instr[5:0];



    ControlUnit cu(ALUOp, RegDst, MemtoReg, Jump, Branch, MemRead, MemWrite, ALUSrc, RegWrite, Branchn, Opcode, clk, rst);


    
    assign reg_w_dest = (RegDst)? reg_r_addr_2 : reg_w_dest_mux_in;
    Register regis(clk, rst, reg_w_en, reg_w_dest, reg_w_data, reg_r_addr_1, reg_r_addr_2, reg_r_data_1, reg_r_data_2);
    


    ALU_cntrl aluCtrl(ALUOp, Function, ALUControl);



    assign A = reg_r_data_1;
    assign B = (ALUSrc)? immediate : reg_r_data_2;
    ALU alu(A, B, ALUControl, zero_flag, carry_flag, ALU_out);



    DataMemory Dmem(ALU_out, immediate, MemWrite, MemRead, clk, Dmem_out);
    assign reg_w_data = (MemtoReg)? Dmem_out : ALU_out;



    assign AndG1 = zero_flag & Branch;
    assign AndG2 = ~zero_flag & Branchn;
    assign XORG1 = AndG1 | AndG2;
    assign Branch_addr = pc_cnt_out + immediate;

    assign pc_cnt_in = (XORG1)? Branch_addr : pc_cnt_out;
    assign pc_cnt_in = (Jump)? instr[25:0] : Branch_addr;

    
endmodule
module MIPS32_Processor (
    input clk, rst,
    output [31:0] result, pc_cnt_out
);


    wire RegDst, MemtoReg, Jump, Branch, MemRead, MemWrite, ALUSrc, RegWrite, Branchn, zero_flag, carry_flag, AndG1, AndG2, XORG1;
    wire [1:0] ALUOp;
    wire [3:0] ALUControl;
    wire [4:0] reg_r_addr_1, reg_r_addr_2, reg_w_dest, reg_w_dest_mux;
    wire [5:0] Opcode, Function;
    wire [15:0] immediate;
    wire [31:0] instr, reg_w_data, reg_r_data_1, reg_r_data_2, A, B, ALU_out, Dmem_out, Branch_addr;

    
    PC pc(clk, rst, Jump, pc_cnt_in, pc_cnt_out);        
    Ins_mem Imem(pc_cnt_out, instr);




    assign Opcode = instr[31:26];
    assign reg_r_addr_1 = instr[25:21];
    assign reg_r_addr_2 = instr[20:16];
    assign reg_w_dest_mux_in = instr[15:11];
    assign immediate = instr[15:0]; 
    assign Function = instr[5:0];



    ControlUnit cu(ALUOp, RegDst, MemtoReg, Jump, Branch, MemRead, MemWrite, ALUSrc, RegWrite, Branchn, Opcode, clk, rst);


    
    assign reg_w_dest = (RegDst)? reg_r_addr_2 : reg_w_dest_mux_in;
    Register regis(clk, rst, reg_w_en, reg_w_dest, reg_w_data, reg_r_addr_1, reg_r_addr_2, reg_r_data_1, reg_r_data_2);
    


    ALU_cntrl aluCtrl(ALUOp, Function, ALUControl);



    assign A = reg_r_data_1;
    assign B = (ALUSrc)? immediate : reg_r_data_2;
    ALU alu(A, B, ALUControl, zero_flag, carry_flag, ALU_out);



    DataMemory Dmem(ALU_out, immediate, MemWrite, MemRead, clk, Dmem_out);
    assign reg_w_data = (MemtoReg)? Dmem_out : ALU_out;



    assign AndG1 = zero_flag & Branch;
    assign AndG2 = ~zero_flag & Branchn;
    assign XORG1 = AndG1 | AndG2;
    assign Branch_addr = pc_cnt_out + immediate;

    assign pc_cnt_in = (XORG1)? Branch_addr : pc_cnt_out;
    assign pc_cnt_in = (Jump)? instr[25:0] : Branch_addr;

    
endmodule