data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:113: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xc2_3_ (\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_128x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_128x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_128x.sv\n             bw_clk_cclk_inv_128x\n             bw_clk_cclk_inv_128x.v\n             bw_clk_cclk_inv_128x.sv\n             obj_dir/bw_clk_cclk_inv_128x\n             obj_dir/bw_clk_cclk_inv_128x.v\n             obj_dir/bw_clk_cclk_inv_128x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:116: Cannot find file containing module: 'bw_clk_cclk_inv_96x'\nbw_clk_cclk_inv_96x xc3_1_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:119: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc4_0_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:122: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc4_1_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:125: Cannot find file containing module: 'bw_clk_cclk_inv_48x'\nbw_clk_cclk_inv_48x xc5_0_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:128: Cannot find file containing module: 'bw_clk_cclk_inv_48x'\nbw_clk_cclk_inv_48x xc5_1_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:131: Cannot find file containing module: 'bw_clk_cclk_hdr_64x'\nbw_clk_cclk_hdr_64x xclhdr (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:145: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xc2_0_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:148: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xc2_1_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:151: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xc2_2_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:154: Cannot find file containing module: 'bw_clk_cclk_inv_96x'\nbw_clk_cclk_inv_96x xc3_0_ (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:66: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:69: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:72: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc11_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:75: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:78: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:81: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:84: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc11_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:87: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:33: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x5 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:36: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x6 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:39: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x7 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:42: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x8 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:45: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x xc14 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_fdbk.v:48: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x x1 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n"
module bw_clk_gl_fdbk(clk_fdbk_in ,clk_fdbk_out );
output		clk_fdbk_out ;
input		clk_fdbk_in ;
 
wire		clk12 ;
wire		gclk ;
 
 
bw_clk_gl_fdbk_hz i0 (
     .c12             (clk12 ),
     .c16             (clk_fdbk_in ) );
bw_clk_gl_fdbk_vrt i1 (
     .c12             (clk12 ),
     .gclk            (gclk ) );
bw_clk_gl_fdbk_clstr i2 (
     .rclk            (clk_fdbk_out ),
     .gclk            (gclk ) );
endmodule
module bw_clk_gl_fdbk(clk_fdbk_in ,clk_fdbk_out );

output		clk_fdbk_out ;
input		clk_fdbk_in ;
 
wire		clk12 ;
wire		gclk ;
 
 
bw_clk_gl_fdbk_hz i0 (
     .c12             (clk12 ),
     .c16             (clk_fdbk_in ) );
bw_clk_gl_fdbk_vrt i1 (
     .c12             (clk12 ),
     .gclk            (gclk ) );
bw_clk_gl_fdbk_clstr i2 (
     .rclk            (clk_fdbk_out ),
     .gclk            (gclk ) );
endmodule