data/full_repos/permissive/463395574/cpu.v
1: b'%Error: data/full_repos/permissive/463395574/cpu.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/cpu.v:299: Define or directive not defined: \'`INSTR_SIZE\'\n    wire [`INSTR_SIZE-1:0] instr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:300: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] pc, newPC, newSeqAddr, newJumpAddr;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:301: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] immOut, readData1, readData2, regWriteData;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:302: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] readAddr1 = instr[19:15];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:303: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] readAddr2 = instr[24:20];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:304: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] writeAddr = instr[11:7];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:306: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] aluInputA, aluInputB, aluOut;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:307: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] memReadData;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:317: Define or directive not defined: \'`WORD_LEN\'\n    addrAdder adder1(pc, {{{`WORD_LEN-3}{1\'b0}}, 3\'b100}, newSeqAddr);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                                                 ^\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`JUMP_TYPE_JALR\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                      ^\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:344: Define or directive not defined: \'`JUMP_TYPE_NONE\'\n        .isJumpOp(jumpType != `JUMP_TYPE_NONE),\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:344: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .isJumpOp(jumpType != `JUMP_TYPE_NONE),\n                                             ^\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                                                 ^\n%Error: Exiting due to 25 error(s)\n'
module CPU (
    input clk, rst
);

    wire [`INSTR_SIZE-1:0] instr;
    wire [`ADDR_SIZE-1:0] pc, newPC, newSeqAddr, newJumpAddr;
    wire [`WORD_LEN-1:0] immOut, readData1, readData2, regWriteData;
    wire [`REG_IDX_WIDTH-1:0] readAddr1 = instr[19:15];
    wire [`REG_IDX_WIDTH-1:0] readAddr2 = instr[24:20];
    wire [`REG_IDX_WIDTH-1:0] writeAddr = instr[11:7];
    wire ALUSrcA, ALUSrcB, isBranchOp, memRead, memWrite, regWrite;
    wire [`WORD_LEN-1:0] aluInputA, aluInputB, aluOut;
    wire [`WORD_LEN-1:0] memReadData;
    wire [4:0] immCtrl;
    wire [3:0] ALUCtrl;
    wire [2:0] funct3;
    wire [1:0] memtoReg;
    wire [1:0] jumpType;
    wire branchCtrl;


    PC programCounter(clk, rst, 1'b1, newPC, pc);
    addrAdder adder1(pc, {{{`WORD_LEN-3}{1'b0}}, 3'b100}, newSeqAddr);
    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, immOut};
    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, readData1} : pc;
    addrAdder adder2(addrAdderSrc1, addrAdderSrc2 ,newJumpAddr);
    PCSrcMux pcSrcMux(newSeqAddr, newJumpAddr, branchCtrl, newPC);


    IMem imem(pc, instr);


    ControlUnit cu(
        .instr(instr),
        .immCtrl(immCtrl),
        .ALUCtrl(ALUCtrl),
        .ALUSrcA(ALUSrcA),
        .ALUSrcB(ALUSrcB),
        .branch(isBranchOp),
        .funct3(funct3),
        .jumpType(jumpType),
        .memRead(memRead),
        .memWrite(memWrite),
        .memtoReg(memtoReg),
        .regWrite(regWrite)
    );
    PCSrcController pcSrcController(
        .isBranchOp(isBranchOp),
        .branchType(funct3),
        .isJumpOp(jumpType != `JUMP_TYPE_NONE),
        .rs1(readData1),
        .rs2(readData2),
        .branchCtrl(branchCtrl)
    );


    ImmGen immGen(instr, immCtrl, immOut);


    RegFile regfile(
        .clk(clk),
        .readAddr1(readAddr1),
        .readAddr2(readAddr2),
        .readData1(readData1),
        .readData2(readData2),
        .writeEnable(regWrite),
        .writeAddr(writeAddr),
        .writeData(regWriteData)
    );


    ALUSrcAMux aluSrcAMux(readData1, pc, ALUSrcA, aluInputA);
    ALUSrcBMux aluSrcBMux(readData2, immOut, ALUSrcB, aluInputB);
    ALU alu(aluInputA, aluInputB, ALUCtrl, aluOut);


    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, aluOut};
    DMem dmem(
        .clk(clk),
        .readEnable(memRead),
        .writeEnable(memWrite),
        .addr(memAccessAddr),
        .unitSize(funct3),
        .writeData(readData2),
        .readData(memReadData)
    );
    MemtoRegMux memtoRegMux(
        .ALUResult(aluOut),
        .memData(memReadData),
        .newSeqAddr(newSeqAddr),
        .MemtoReg(memtoReg),
        .out(regWriteData)
    );
endmodule
module CPU (
    input clk, rst
);


    wire [`INSTR_SIZE-1:0] instr;
    wire [`ADDR_SIZE-1:0] pc, newPC, newSeqAddr, newJumpAddr;
    wire [`WORD_LEN-1:0] immOut, readData1, readData2, regWriteData;
    wire [`REG_IDX_WIDTH-1:0] readAddr1 = instr[19:15];
    wire [`REG_IDX_WIDTH-1:0] readAddr2 = instr[24:20];
    wire [`REG_IDX_WIDTH-1:0] writeAddr = instr[11:7];
    wire ALUSrcA, ALUSrcB, isBranchOp, memRead, memWrite, regWrite;
    wire [`WORD_LEN-1:0] aluInputA, aluInputB, aluOut;
    wire [`WORD_LEN-1:0] memReadData;
    wire [4:0] immCtrl;
    wire [3:0] ALUCtrl;
    wire [2:0] funct3;
    wire [1:0] memtoReg;
    wire [1:0] jumpType;
    wire branchCtrl;


    PC programCounter(clk, rst, 1'b1, newPC, pc);
    addrAdder adder1(pc, {{{`WORD_LEN-3}{1'b0}}, 3'b100}, newSeqAddr);
    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, immOut};
    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, readData1} : pc;
    addrAdder adder2(addrAdderSrc1, addrAdderSrc2 ,newJumpAddr);
    PCSrcMux pcSrcMux(newSeqAddr, newJumpAddr, branchCtrl, newPC);


    IMem imem(pc, instr);


    ControlUnit cu(
        .instr(instr),
        .immCtrl(immCtrl),
        .ALUCtrl(ALUCtrl),
        .ALUSrcA(ALUSrcA),
        .ALUSrcB(ALUSrcB),
        .branch(isBranchOp),
        .funct3(funct3),
        .jumpType(jumpType),
        .memRead(memRead),
        .memWrite(memWrite),
        .memtoReg(memtoReg),
        .regWrite(regWrite)
    );
    PCSrcController pcSrcController(
        .isBranchOp(isBranchOp),
        .branchType(funct3),
        .isJumpOp(jumpType != `JUMP_TYPE_NONE),
        .rs1(readData1),
        .rs2(readData2),
        .branchCtrl(branchCtrl)
    );


    ImmGen immGen(instr, immCtrl, immOut);


    RegFile regfile(
        .clk(clk),
        .readAddr1(readAddr1),
        .readAddr2(readAddr2),
        .readData1(readData1),
        .readData2(readData2),
        .writeEnable(regWrite),
        .writeAddr(writeAddr),
        .writeData(regWriteData)
    );


    ALUSrcAMux aluSrcAMux(readData1, pc, ALUSrcA, aluInputA);
    ALUSrcBMux aluSrcBMux(readData2, immOut, ALUSrcB, aluInputB);
    ALU alu(aluInputA, aluInputB, ALUCtrl, aluOut);


    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1'b0}}, aluOut};
    DMem dmem(
        .clk(clk),
        .readEnable(memRead),
        .writeEnable(memWrite),
        .addr(memAccessAddr),
        .unitSize(funct3),
        .writeData(readData2),
        .readData(memReadData)
    );
    MemtoRegMux memtoRegMux(
        .ALUResult(aluOut),
        .memData(memReadData),
        .newSeqAddr(newSeqAddr),
        .MemtoReg(memtoReg),
        .out(regWriteData)
    );
endmodule