data/full_repos/permissive/473722449/reg_4bit.v
data/verilator_xmls/ca11cd74-ba0f-44ea-93f4-cf05086e6296.xml
module reg_4bit(
    input [3:0] d,
    input clk,
    output reg [3:0] q
    );
    always@(posedge clk)
    begin
        q=d;
    end
endmodule
module reg_4bit(
    input [3:0] d,
    input clk,
    output reg [3:0] q
    );

    always@(posedge clk)
    begin
        q=d;
    end
endmodule