data/full_repos/permissive/486954482/netlists/relu64.v
data/verilator_xmls/b569272f-38ef-430d-bdb2-c9b32803b2ed.xml
module relu(
    input [63:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );
    assign o = (e_input[63] == 0)? e_input : 0;
endmodule
module relu(
    input [63:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );

    assign o = (e_input[63] == 0)? e_input : 0;
endmodule