data/full_repos/permissive/423539813/testbenches/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:43: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:45: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:49: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:51: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:52: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:54: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:55: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:57: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:61: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:63: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:69: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:72: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:75: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:76: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:78: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:79: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:84: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:85: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:88: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=1; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:89: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=0; rst=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/test.v:92: Unsupported: Ignoring delay on this delayed statement.\n#5 $stop;\n^\n%Error: data/full_repos/permissive/423539813/testbenches/test.v:29: Cannot find file containing module: \'main\'\nmain mainfile(.rst(rst), .clk(clk), .alu_z(alu_z), .Anode_Activate(Anode_Activate), .LED_out(LED_out));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/main\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/main.v\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 35 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
reg rst, clk;
wire alu_z;
wire[7:0] Anode_Activate;
wire [6:0] LED_out;

main mainfile(.rst(rst), .clk(clk), .alu_z(alu_z), .Anode_Activate(Anode_Activate), .LED_out(LED_out));







initial begin
clk=0; rst=1;
#5 clk=1; rst=1;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;


#5 clk=1; rst=0;
#5 clk=0; rst=0;


#5 $stop;
end
endmodule
module test;

reg rst, clk;
wire alu_z;
wire[7:0] Anode_Activate;
wire [6:0] LED_out;

main mainfile(.rst(rst), .clk(clk), .alu_z(alu_z), .Anode_Activate(Anode_Activate), .LED_out(LED_out));







initial begin
clk=0; rst=1;
#5 clk=1; rst=1;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;

#5 clk=1; rst=0;
#5 clk=0; rst=0;


#5 clk=1; rst=0;
#5 clk=0; rst=0;


#5 $stop;
end
endmodule