data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign.v:8: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'carry_in\' generates 1 bits.\n                                                                                                      : ... In instance adder\nassign {carry_out, sum_out} = ina + inb + carry_in;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module adder (sum_out, carry_out, carry_in, ina, inb);
output carry_out;
output [3:0] sum_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule
module adder (sum_out, carry_out, carry_in, ina, inb);

output carry_out;
output [3:0] sum_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule