data/full_repos/permissive/516830490/RTL/Top_design.v
1: b"%Error: data/full_repos/permissive/516830490/RTL/Top_design.v:43: Cannot find file containing module: 'seven_seg_display'\nseven_seg_display SS( .i_hex_en(seg_out) , .o_out(Sseg_out) ); \n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/seven_seg_display\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/seven_seg_display.v\n             data/full_repos/permissive/516830490/RTL,data/full_repos/permissive/516830490/seven_seg_display.sv\n             seven_seg_display\n             seven_seg_display.v\n             seven_seg_display.sv\n             obj_dir/seven_seg_display\n             obj_dir/seven_seg_display.v\n             obj_dir/seven_seg_display.sv\n%Error: data/full_repos/permissive/516830490/RTL/Top_design.v:47: Cannot find file containing module: 'clk_div'\n  clk_div DIV_CLK(.i_clk(i_clk) , .clk_o(clk_out));\n  ^~~~~~~\n%Error: data/full_repos/permissive/516830490/RTL/Top_design.v:54: Cannot find file containing module: 'Multiplexer_circuit'\n Multiplexer_circuit MUX(\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Top_design(
input i_clk , 
input i_rst, 
input incr , 
input decr ,
output [`SEG_WID-1:0] o_seg_en ,
output  an_seg ,   
output [`SEG_WIDTH-1:0] Sseg_out);

assign an_seg  = 1'b1;   
wire [3:0] seg_out ;
reg p_state ;
reg [`N_WIDTH-1:0] digit0 , digit1 ;

reg [`COUNT_WID_REFRESH-1:0] refresh_cnt = 0 ; 
 
seven_seg_display SS( .i_hex_en(seg_out) , .o_out(Sseg_out) ); 
 
    wire clk_out ;
    
  clk_div DIV_CLK(.i_clk(i_clk) , .clk_o(clk_out));
 
 always @(posedge i_clk)
          begin
              refresh_cnt <= refresh_cnt + 1'b1 ; 
                end
                
 Multiplexer_circuit MUX(
.i_clk(refresh_cnt[16]) ,  
.o_seg1(digit0) ,
.o_seg2(digit1) ,
.o_en(o_seg_en)  , 
.o_seg(seg_out)
 );  
    
always @(posedge clk_out)
   begin
            case (p_state)
   0:           begin
                 digit0 <= 4'b0000;
                digit1 <= 4'b0000;
                p_state <= 1'b1 ;
                end
                
   1:       begin
                if (i_rst==1'b1)
                            begin
                                  p_state <= 1'b0 ;
                                      end    
              else if ( incr == 1'b1 && decr == 1'b0)
                                begin
                                   if (digit0 < 4'b1001)
                                                begin
                                                         digit0 <= digit0 + 1'b1 ;
                                                              end 
                                                                   else if (digit1 <4'b1001)
                                                                          begin
                                                                 digit1 <= digit1 + 1'b1 ; 
                                                         digit0 <= 4'b0000;
                                                   end
                                           end
              else if ( incr ==1'b0 && decr == 1'b1)
                                   begin
                                       if (digit0 >4'b0000) 
                                               begin
                                                       digit0 <= digit0 - 1'b1 ;
                                                     end
                                                  else if (digit1 >4'b0000)
                                                begin
                                             digit1 <= digit1 - 1'b1 ;
                                         digit0 <= 4'b1001;
                                     end 
                                end
             else if (incr == 1'b1 && decr == 1'b1)
                       begin 
                          
                          p_state <= 0;
                          end
                      end    
             default : begin
                           p_state <= 0;
                           end              
                    endcase
        end                                                                                                
endmodule
module Top_design(
input i_clk , 
input i_rst, 
input incr , 
input decr ,
output [`SEG_WID-1:0] o_seg_en ,
output  an_seg ,   
output [`SEG_WIDTH-1:0] Sseg_out);


assign an_seg  = 1'b1;   
wire [3:0] seg_out ;
reg p_state ;
reg [`N_WIDTH-1:0] digit0 , digit1 ;

reg [`COUNT_WID_REFRESH-1:0] refresh_cnt = 0 ; 
 
seven_seg_display SS( .i_hex_en(seg_out) , .o_out(Sseg_out) ); 
 
    wire clk_out ;
    
  clk_div DIV_CLK(.i_clk(i_clk) , .clk_o(clk_out));
 
 always @(posedge i_clk)
          begin
              refresh_cnt <= refresh_cnt + 1'b1 ; 
                end
                
 Multiplexer_circuit MUX(
.i_clk(refresh_cnt[16]) ,  
.o_seg1(digit0) ,
.o_seg2(digit1) ,
.o_en(o_seg_en)  , 
.o_seg(seg_out)
 );  
    
always @(posedge clk_out)
   begin
            case (p_state)
   0:           begin
                 digit0 <= 4'b0000;
                digit1 <= 4'b0000;
                p_state <= 1'b1 ;
                end
                
   1:       begin
                if (i_rst==1'b1)
                            begin
                                  p_state <= 1'b0 ;
                                      end    
              else if ( incr == 1'b1 && decr == 1'b0)
                                begin
                                   if (digit0 < 4'b1001)
                                                begin
                                                         digit0 <= digit0 + 1'b1 ;
                                                              end 
                                                                   else if (digit1 <4'b1001)
                                                                          begin
                                                                 digit1 <= digit1 + 1'b1 ; 
                                                         digit0 <= 4'b0000;
                                                   end
                                           end
              else if ( incr ==1'b0 && decr == 1'b1)
                                   begin
                                       if (digit0 >4'b0000) 
                                               begin
                                                       digit0 <= digit0 - 1'b1 ;
                                                     end
                                                  else if (digit1 >4'b0000)
                                                begin
                                             digit1 <= digit1 - 1'b1 ;
                                         digit0 <= 4'b1001;
                                     end 
                                end
             else if (incr == 1'b1 && decr == 1'b1)
                       begin 
                          
                          p_state <= 0;
                          end
                      end    
             default : begin
                           p_state <= 0;
                           end              
                    endcase
        end                                                                                                
endmodule