data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:44: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:49: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:50: Unsupported: Ignoring delay on this delayed statement.\n            #2 \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineBuffer_tb.sv:59: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish();\n        ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LineBuffer_tb;
bit clk;
bit arstn;
bit [13:0]data_in;
bit wrreq;
wire [13:0]data_out;
bit rdreq;
wire [8:0]usedw;
wire empty;
wire full;

always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        wrreq = 1'b0;
        rdreq = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        #20
        for(int i=0;i<512;i=i+1)
        begin
            @(posedge clk);
            #2 
                data_in = i;
                wrreq = 1'b1;
                if(i==256)
                begin
                    rdreq = 1'b1;
                end
        end
        
        #200 $finish();
    end


LineBuffer #
(
    .DATA_WIDTH(14),
    .BUFFER_DEPTH(256),
    .FIFO_WIDTH(8)
)Dut
(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .wrreq(wrreq),
    .data_out(data_out),
    .rdreq(rdreq),
    .usedw(usedw),
    .empty(empty),
    .full(full)
);
endmodule
module LineBuffer_tb;

bit clk;
bit arstn;
bit [13:0]data_in;
bit wrreq;
wire [13:0]data_out;
bit rdreq;
wire [8:0]usedw;
wire empty;
wire full;

always #5 clk = ~clk;
initial
    begin
        arstn = 1'b1;
        wrreq = 1'b0;
        rdreq = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        #20
        for(int i=0;i<512;i=i+1)
        begin
            @(posedge clk);
            #2 
                data_in = i;
                wrreq = 1'b1;
                if(i==256)
                begin
                    rdreq = 1'b1;
                end
        end
        
        #200 $finish();
    end


LineBuffer #
(
    .DATA_WIDTH(14),
    .BUFFER_DEPTH(256),
    .FIFO_WIDTH(8)
)Dut
(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .wrreq(wrreq),
    .data_out(data_out),
    .rdreq(rdreq),
    .usedw(usedw),
    .empty(empty),
    .full(full)
);
endmodule