data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v:382: Unsupported or unknown PLI call: $RollPLI\n        prand_inst0 = $RollPLI(min, max, "auto");\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v:437: Unsupported or unknown PLI call: $RollPLI\n        prand_inst1 = $RollPLI(min, max, "auto");\n                      ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NV_NVDLA_CDP_DP_mul (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,fp16_en
  ,int16_en
  ,int8_en
  ,intp2mul_pd_0
  ,intp2mul_pd_1
  ,intp2mul_pd_2
  ,intp2mul_pd_3
  ,intp2mul_pd_4
  ,intp2mul_pd_5
  ,intp2mul_pd_6
  ,intp2mul_pd_7
  ,intp2mul_pvld
  ,mul2ocvt_prdy
  ,nvdla_op_gated_clk_fp16
  ,nvdla_op_gated_clk_int
  ,reg2dp_input_data_type
  ,reg2dp_mul_bypass
  ,sync2mul_pd
  ,sync2mul_pvld
  ,intp2mul_prdy
  ,mul2ocvt_pd
  ,mul2ocvt_pvld
  ,sync2mul_prdy
  );
input          nvdla_core_clk;
input          nvdla_core_rstn;
input          fp16_en;
input          int16_en;
input          int8_en;
input   [16:0] intp2mul_pd_0;
input   [16:0] intp2mul_pd_1;
input   [16:0] intp2mul_pd_2;
input   [16:0] intp2mul_pd_3;
input   [16:0] intp2mul_pd_4;
input   [16:0] intp2mul_pd_5;
input   [16:0] intp2mul_pd_6;
input   [16:0] intp2mul_pd_7;
input          intp2mul_pvld;
input          mul2ocvt_prdy;
input          nvdla_op_gated_clk_fp16;
input          nvdla_op_gated_clk_int;
input    [1:0] reg2dp_input_data_type;
input          reg2dp_mul_bypass;
input   [71:0] sync2mul_pd;
input          sync2mul_pvld;
output         intp2mul_prdy;
output [199:0] mul2ocvt_pd;
output         mul2ocvt_pvld;
output         sync2mul_prdy;
reg    [199:0] mul2ocvt_pd;
reg            mul2ocvt_prdy_f;
reg            mul2ocvt_pvld;
reg            mul_bypass_en;
reg    [199:0] p1_pipe_data;
reg    [199:0] p1_pipe_rand_data;
reg            p1_pipe_rand_ready;
reg            p1_pipe_rand_valid;
reg            p1_pipe_ready;
reg            p1_pipe_ready_bc;
reg            p1_pipe_valid;
reg            p1_skid_catch;
reg    [199:0] p1_skid_data;
reg    [199:0] p1_skid_pipe_data;
reg            p1_skid_pipe_ready;
reg            p1_skid_pipe_valid;
reg            p1_skid_ready;
reg            p1_skid_ready_flop;
reg            p1_skid_valid;
wire    [16:0] icvt_out_0;
wire    [16:0] icvt_out_1;
wire    [16:0] icvt_out_2;
wire    [16:0] icvt_out_3;
wire   [199:0] intp_out_ext;
wire   [199:0] intp_out_fp16;
wire    [49:0] intp_out_fp16_0;
wire    [49:0] intp_out_fp16_1;
wire    [49:0] intp_out_fp16_2;
wire    [49:0] intp_out_fp16_3;
wire   [199:0] intp_out_int16;
wire   [199:0] intp_out_int8;
wire     [3:0] is_nan_in;
wire   [199:0] mul2ocvt_pd_f;
wire           mul2ocvt_pvld_f;
wire           mul_in_rdy;
wire           mul_in_vld;
wire     [3:0] mul_rdy;
wire    [49:0] mul_unit_pd_0;
wire    [49:0] mul_unit_pd_1;
wire    [49:0] mul_unit_pd_2;
wire    [49:0] mul_unit_pd_3;
wire     [3:0] mul_unit_rdy;
wire     [3:0] mul_unit_vld;
wire     [3:0] mul_vld;


















always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_bypass_en <= 1'b0;
  end else begin
  mul_bypass_en <= reg2dp_mul_bypass   == 1'h1;
  end
end




assign intp2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & sync2mul_pvld;
assign sync2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & intp2mul_pvld;

assign mul_in_vld = mul_bypass_en ? 1'b0 : (sync2mul_pvld & intp2mul_pvld);
assign mul_in_rdy = &mul_rdy;

assign mul_vld[0] = mul_in_vld & (&mul_rdy[3:1]);
assign mul_vld[1] = mul_in_vld & (&{mul_rdy[3:1],mul_rdy[0]});
assign mul_vld[2] = mul_in_vld & (&{mul_rdy[3],mul_rdy[1:0]});
assign mul_vld[3] = mul_in_vld & (&mul_rdy[2:0]);
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit0 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[17:0])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_0[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_4[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[0])
  ,.mul_vld                 (mul_vld[0])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[0])
  ,.mul_unit_pd             (mul_unit_pd_0[49:0])
  ,.mul_unit_vld            (mul_unit_vld[0])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit1 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[35:18])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_1[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_5[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[1])
  ,.mul_vld                 (mul_vld[1])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[1])
  ,.mul_unit_pd             (mul_unit_pd_1[49:0])
  ,.mul_unit_vld            (mul_unit_vld[1])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit2 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[53:36])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_2[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_6[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[2])
  ,.mul_vld                 (mul_vld[2])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[2])
  ,.mul_unit_pd             (mul_unit_pd_2[49:0])
  ,.mul_unit_vld            (mul_unit_vld[2])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit3 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[71:54])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_3[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_7[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[3])
  ,.mul_vld                 (mul_vld[3])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[3])
  ,.mul_unit_pd             (mul_unit_pd_3[49:0])
  ,.mul_unit_vld            (mul_unit_vld[3])
  );

assign mul_unit_rdy[0] = mul2ocvt_prdy_f & (&mul_unit_vld[3:1]);
assign mul_unit_rdy[1] = mul2ocvt_prdy_f & (&{mul_unit_vld[3:2],mul_unit_vld[0]});
assign mul_unit_rdy[2] = mul2ocvt_prdy_f & (&{mul_unit_vld[3],mul_unit_vld[1:0]});
assign mul_unit_rdy[3] = mul2ocvt_prdy_f & (&mul_unit_vld[2:0]);



assign icvt_out_0 = sync2mul_pd[16:0];
assign icvt_out_1 = sync2mul_pd[34:18];
assign icvt_out_2 = sync2mul_pd[52:36];
assign icvt_out_3 = sync2mul_pd[70:54];
assign is_nan_in[0] = fp16_en ? (&icvt_out_0[15:10]) & (|icvt_out_0[9:0]) : 1'b0;
assign is_nan_in[1] = fp16_en ? (&icvt_out_1[15:10]) & (|icvt_out_1[9:0]) : 1'b0;
assign is_nan_in[2] = fp16_en ? (&icvt_out_2[15:10]) & (|icvt_out_2[9:0]) : 1'b0;
assign is_nan_in[3] = fp16_en ? (&icvt_out_3[15:10]) & (|icvt_out_3[9:0]) : 1'b0;

assign intp_out_int8  = {{{8{intp2mul_pd_7[16]}}, intp2mul_pd_7[16:0]},{{8{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]},
                         {{8{intp2mul_pd_6[16]}}, intp2mul_pd_6[16:0]},{{8{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]},
                         {{8{intp2mul_pd_5[16]}}, intp2mul_pd_5[16:0]},{{8{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]},
                         {{8{intp2mul_pd_4[16]}}, intp2mul_pd_4[16:0]},{{8{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}};
assign intp_out_int16 = {{{33{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]},{{33{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]},
                         {{33{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]},{{33{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}};

assign intp_out_fp16_0 = is_nan_in[0] ? {{33{icvt_out_0[16]}}, icvt_out_0[16:0]} : {{33{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]};
assign intp_out_fp16_1 = is_nan_in[1] ? {{33{icvt_out_1[16]}}, icvt_out_1[16:0]} : {{33{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]};
assign intp_out_fp16_2 = is_nan_in[2] ? {{33{icvt_out_2[16]}}, icvt_out_2[16:0]} : {{33{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]};
assign intp_out_fp16_3 = is_nan_in[3] ? {{33{icvt_out_3[16]}}, icvt_out_3[16:0]} : {{33{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]};
assign intp_out_fp16 = {intp_out_fp16_3,intp_out_fp16_2,intp_out_fp16_1,intp_out_fp16_0};

assign intp_out_ext  = int8_en ? intp_out_int8 : (int16_en ? intp_out_int16 : intp_out_fp16);

assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : {mul_unit_pd_3,mul_unit_pd_2,mul_unit_pd_1,mul_unit_pd_0};
assign mul2ocvt_pvld_f = mul_bypass_en ? (sync2mul_pvld & intp2mul_pvld) : (&mul_unit_vld);




`ifndef SYNTHESIS
reg p1_pipe_rand_active;
`endif
always @(
  `ifndef SYNTHESIS
  p1_pipe_rand_active
  or 
     `endif
     mul2ocvt_pvld_f
  or p1_pipe_rand_ready
  or mul2ocvt_pd_f
  ) begin
  `ifdef SYNTHESIS
  p1_pipe_rand_valid = mul2ocvt_pvld_f;
  mul2ocvt_prdy_f = p1_pipe_rand_ready;
  p1_pipe_rand_data = mul2ocvt_pd_f;
  `else

  p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mul2ocvt_pvld_f;
  mul2ocvt_prdy_f = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready;
  p1_pipe_rand_data = (p1_pipe_rand_active)?  'bx : mul2ocvt_pd_f;

  `endif
end
`ifndef SYNTHESIS


integer p1_pipe_stall_cycles;
integer p1_pipe_stall_probability;
integer p1_pipe_stall_cycles_min;
integer p1_pipe_stall_cycles_max;
initial begin
  p1_pipe_stall_cycles = 0;
  p1_pipe_stall_probability = 0;
  p1_pipe_stall_cycles_min = 1;
  p1_pipe_stall_cycles_max = 10;
`ifndef SYNTH_LEVEL1_COMPILE
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_rand_probability=%d",  p1_pipe_stall_probability ) ) ;
  else if ( $value$plusargs(    "default_pipe_rand_probability=%d",  p1_pipe_stall_probability ) ) ;
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; 
  else if ( $value$plusargs(    "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; 
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_min=%d",  p1_pipe_stall_cycles_min  ) ) ;
  else if ( $value$plusargs(    "default_pipe_stall_cycles_min=%d",  p1_pipe_stall_cycles_min  ) ) ;
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_max=%d",  p1_pipe_stall_cycles_max  ) ) ;
  else if ( $value$plusargs(    "default_pipe_stall_cycles_max=%d",  p1_pipe_stall_cycles_max  ) ) ;
`endif
end

`ifndef SYNTH_LEVEL1_COMPILE
`ifdef SIMTOP_RANDOMIZE_STALLS
always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability;
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_min"  ) ) p1_pipe_stall_cycles_min  = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min;
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_max"  ) ) p1_pipe_stall_cycles_max  = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max;
end
`endif
`endif

reg p1_pipe_rand_enable;
reg p1_pipe_rand_poised;
always @(
  p1_pipe_stall_cycles
  or p1_pipe_stall_probability
  or mul2ocvt_pvld_f
  ) begin
  p1_pipe_rand_active = p1_pipe_stall_cycles != 0;
  p1_pipe_rand_enable = p1_pipe_stall_probability != 0;
  p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mul2ocvt_pvld_f === 1'b1;
end

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_pipe_stall_cycles <= 1'b0;
  end else begin
  if (p1_pipe_rand_poised) begin
    if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin
      p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max);
    end
  end else if (p1_pipe_rand_active) begin
    p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1;
  end else begin
    p1_pipe_stall_cycles <= 0;
  end
  end
end

`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG

reg [47:0] prand_local_seed0;
reg prand_initialized0;
reg prand_no_rollpli0;
`endif
`endif
`endif

function [31:0] prand_inst0;

    input [31:0] min;
    input [31:0] max;
    reg [32:0] diff;
    
    begin
`ifdef SYNTH_LEVEL1_COMPILE
        prand_inst0 = min;
`else
`ifdef SYNTHESIS
        prand_inst0 = min;
`else
`ifdef PRAND_VERILOG
        if (prand_initialized0 !== 1'b1) begin
            prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI");
            if (!prand_no_rollpli0)
                prand_local_seed0 = {$prand_get_seed(0), 16'b0};
            prand_initialized0 = 1'b1;
        end
        if (prand_no_rollpli0) begin
            prand_inst0 = min;
        end else begin
            diff = max - min + 1;
            prand_inst0 = min + prand_local_seed0[47:16] % diff;

            prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11;
        end
`else
`ifdef PRAND_OFF
        prand_inst0 = min;
`else
        prand_inst0 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
    end

endfunction


`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG

reg [47:0] prand_local_seed1;
reg prand_initialized1;
reg prand_no_rollpli1;
`endif
`endif
`endif

function [31:0] prand_inst1;

    input [31:0] min;
    input [31:0] max;
    reg [32:0] diff;
    
    begin
`ifdef SYNTH_LEVEL1_COMPILE
        prand_inst1 = min;
`else
`ifdef SYNTHESIS
        prand_inst1 = min;
`else
`ifdef PRAND_VERILOG
        if (prand_initialized1 !== 1'b1) begin
            prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI");
            if (!prand_no_rollpli1)
                prand_local_seed1 = {$prand_get_seed(1), 16'b0};
            prand_initialized1 = 1'b1;
        end
        if (prand_no_rollpli1) begin
            prand_inst1 = min;
        end else begin
            diff = max - min + 1;
            prand_inst1 = min + prand_local_seed1[47:16] % diff;

            prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11;
        end
`else
`ifdef PRAND_OFF
        prand_inst1 = min;
`else
        prand_inst1 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
    end

endfunction

`endif


always @(
  p1_pipe_rand_valid
  or p1_skid_ready_flop
  or p1_skid_pipe_ready
  or p1_skid_valid
  ) begin
  p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready;  
  p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch;
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_skid_valid <= 1'b0;
    p1_skid_ready_flop <= 1'b1;
    p1_pipe_rand_ready <= 1'b1;
  end else begin
  p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch;
  p1_skid_ready_flop <= p1_skid_ready;
  p1_pipe_rand_ready <= p1_skid_ready;
  end
end
always @(posedge nvdla_core_clk) begin

  p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data;

end
always @(
  p1_skid_ready_flop
  or p1_pipe_rand_valid
  or p1_skid_valid
  or p1_pipe_rand_data
  or p1_skid_data
  ) begin
  p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; 

  p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data;

end

always @(
  p1_pipe_ready
  or p1_pipe_valid
  ) begin
  p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid;
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_pipe_valid <= 1'b0;
  end else begin
  p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1;
  end
end
always @(posedge nvdla_core_clk) begin

  p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data;

end
always @(
  p1_pipe_ready_bc
  ) begin
  p1_skid_pipe_ready = p1_pipe_ready_bc;
end

always @(
  p1_pipe_valid
  or mul2ocvt_prdy
  or p1_pipe_data
  ) begin
  mul2ocvt_pvld = p1_pipe_valid;
  p1_pipe_ready = mul2ocvt_prdy;
  mul2ocvt_pd = p1_pipe_data;
end

`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS
wire p1_assert_clk = nvdla_core_clk;
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul2ocvt_pvld^mul2ocvt_prdy^mul2ocvt_pvld_f^mul2ocvt_prdy_f));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif

  nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready")      zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul2ocvt_pvld_f && !mul2ocvt_prdy_f), (mul2ocvt_pvld_f), (mul2ocvt_prdy_f));

`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`endif


endmodule
module NV_NVDLA_CDP_DP_mul (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,fp16_en
  ,int16_en
  ,int8_en
  ,intp2mul_pd_0
  ,intp2mul_pd_1
  ,intp2mul_pd_2
  ,intp2mul_pd_3
  ,intp2mul_pd_4
  ,intp2mul_pd_5
  ,intp2mul_pd_6
  ,intp2mul_pd_7
  ,intp2mul_pvld
  ,mul2ocvt_prdy
  ,nvdla_op_gated_clk_fp16
  ,nvdla_op_gated_clk_int
  ,reg2dp_input_data_type
  ,reg2dp_mul_bypass
  ,sync2mul_pd
  ,sync2mul_pvld
  ,intp2mul_prdy
  ,mul2ocvt_pd
  ,mul2ocvt_pvld
  ,sync2mul_prdy
  );

input          nvdla_core_clk;
input          nvdla_core_rstn;
input          fp16_en;
input          int16_en;
input          int8_en;
input   [16:0] intp2mul_pd_0;
input   [16:0] intp2mul_pd_1;
input   [16:0] intp2mul_pd_2;
input   [16:0] intp2mul_pd_3;
input   [16:0] intp2mul_pd_4;
input   [16:0] intp2mul_pd_5;
input   [16:0] intp2mul_pd_6;
input   [16:0] intp2mul_pd_7;
input          intp2mul_pvld;
input          mul2ocvt_prdy;
input          nvdla_op_gated_clk_fp16;
input          nvdla_op_gated_clk_int;
input    [1:0] reg2dp_input_data_type;
input          reg2dp_mul_bypass;
input   [71:0] sync2mul_pd;
input          sync2mul_pvld;
output         intp2mul_prdy;
output [199:0] mul2ocvt_pd;
output         mul2ocvt_pvld;
output         sync2mul_prdy;
reg    [199:0] mul2ocvt_pd;
reg            mul2ocvt_prdy_f;
reg            mul2ocvt_pvld;
reg            mul_bypass_en;
reg    [199:0] p1_pipe_data;
reg    [199:0] p1_pipe_rand_data;
reg            p1_pipe_rand_ready;
reg            p1_pipe_rand_valid;
reg            p1_pipe_ready;
reg            p1_pipe_ready_bc;
reg            p1_pipe_valid;
reg            p1_skid_catch;
reg    [199:0] p1_skid_data;
reg    [199:0] p1_skid_pipe_data;
reg            p1_skid_pipe_ready;
reg            p1_skid_pipe_valid;
reg            p1_skid_ready;
reg            p1_skid_ready_flop;
reg            p1_skid_valid;
wire    [16:0] icvt_out_0;
wire    [16:0] icvt_out_1;
wire    [16:0] icvt_out_2;
wire    [16:0] icvt_out_3;
wire   [199:0] intp_out_ext;
wire   [199:0] intp_out_fp16;
wire    [49:0] intp_out_fp16_0;
wire    [49:0] intp_out_fp16_1;
wire    [49:0] intp_out_fp16_2;
wire    [49:0] intp_out_fp16_3;
wire   [199:0] intp_out_int16;
wire   [199:0] intp_out_int8;
wire     [3:0] is_nan_in;
wire   [199:0] mul2ocvt_pd_f;
wire           mul2ocvt_pvld_f;
wire           mul_in_rdy;
wire           mul_in_vld;
wire     [3:0] mul_rdy;
wire    [49:0] mul_unit_pd_0;
wire    [49:0] mul_unit_pd_1;
wire    [49:0] mul_unit_pd_2;
wire    [49:0] mul_unit_pd_3;
wire     [3:0] mul_unit_rdy;
wire     [3:0] mul_unit_vld;
wire     [3:0] mul_vld;


















always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_bypass_en <= 1'b0;
  end else begin
  mul_bypass_en <= reg2dp_mul_bypass   == 1'h1;
  end
end




assign intp2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & sync2mul_pvld;
assign sync2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & intp2mul_pvld;

assign mul_in_vld = mul_bypass_en ? 1'b0 : (sync2mul_pvld & intp2mul_pvld);
assign mul_in_rdy = &mul_rdy;

assign mul_vld[0] = mul_in_vld & (&mul_rdy[3:1]);
assign mul_vld[1] = mul_in_vld & (&{mul_rdy[3:1],mul_rdy[0]});
assign mul_vld[2] = mul_in_vld & (&{mul_rdy[3],mul_rdy[1:0]});
assign mul_vld[3] = mul_in_vld & (&mul_rdy[2:0]);
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit0 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[17:0])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_0[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_4[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[0])
  ,.mul_vld                 (mul_vld[0])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[0])
  ,.mul_unit_pd             (mul_unit_pd_0[49:0])
  ,.mul_unit_vld            (mul_unit_vld[0])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit1 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[35:18])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_1[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_5[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[1])
  ,.mul_vld                 (mul_vld[1])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[1])
  ,.mul_unit_pd             (mul_unit_pd_1[49:0])
  ,.mul_unit_vld            (mul_unit_vld[1])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit2 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[53:36])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_2[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_6[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[2])
  ,.mul_vld                 (mul_vld[2])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[2])
  ,.mul_unit_pd             (mul_unit_pd_2[49:0])
  ,.mul_unit_vld            (mul_unit_vld[2])
  );

NV_NVDLA_CDP_DP_MUL_unit u_mul_unit3 (
   .nvdla_core_clk          (nvdla_core_clk)
  ,.nvdla_op_gated_clk_int  (nvdla_op_gated_clk_int)
  ,.nvdla_core_rstn         (nvdla_core_rstn)
  ,.datin_pd                (sync2mul_pd[71:54])
  ,.fp16_en                 (fp16_en)
  ,.intp2mul_pd_0           (intp2mul_pd_3[16:0])
  ,.intp2mul_pd_1           (intp2mul_pd_7[16:0])
  ,.mul_unit_rdy            (mul_unit_rdy[3])
  ,.mul_vld                 (mul_vld[3])
  ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16)
  ,.reg2dp_input_data_type  (reg2dp_input_data_type[1:0])
  ,.mul_rdy                 (mul_rdy[3])
  ,.mul_unit_pd             (mul_unit_pd_3[49:0])
  ,.mul_unit_vld            (mul_unit_vld[3])
  );

assign mul_unit_rdy[0] = mul2ocvt_prdy_f & (&mul_unit_vld[3:1]);
assign mul_unit_rdy[1] = mul2ocvt_prdy_f & (&{mul_unit_vld[3:2],mul_unit_vld[0]});
assign mul_unit_rdy[2] = mul2ocvt_prdy_f & (&{mul_unit_vld[3],mul_unit_vld[1:0]});
assign mul_unit_rdy[3] = mul2ocvt_prdy_f & (&mul_unit_vld[2:0]);



assign icvt_out_0 = sync2mul_pd[16:0];
assign icvt_out_1 = sync2mul_pd[34:18];
assign icvt_out_2 = sync2mul_pd[52:36];
assign icvt_out_3 = sync2mul_pd[70:54];
assign is_nan_in[0] = fp16_en ? (&icvt_out_0[15:10]) & (|icvt_out_0[9:0]) : 1'b0;
assign is_nan_in[1] = fp16_en ? (&icvt_out_1[15:10]) & (|icvt_out_1[9:0]) : 1'b0;
assign is_nan_in[2] = fp16_en ? (&icvt_out_2[15:10]) & (|icvt_out_2[9:0]) : 1'b0;
assign is_nan_in[3] = fp16_en ? (&icvt_out_3[15:10]) & (|icvt_out_3[9:0]) : 1'b0;

assign intp_out_int8  = {{{8{intp2mul_pd_7[16]}}, intp2mul_pd_7[16:0]},{{8{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]},
                         {{8{intp2mul_pd_6[16]}}, intp2mul_pd_6[16:0]},{{8{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]},
                         {{8{intp2mul_pd_5[16]}}, intp2mul_pd_5[16:0]},{{8{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]},
                         {{8{intp2mul_pd_4[16]}}, intp2mul_pd_4[16:0]},{{8{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}};
assign intp_out_int16 = {{{33{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]},{{33{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]},
                         {{33{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]},{{33{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}};

assign intp_out_fp16_0 = is_nan_in[0] ? {{33{icvt_out_0[16]}}, icvt_out_0[16:0]} : {{33{intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]};
assign intp_out_fp16_1 = is_nan_in[1] ? {{33{icvt_out_1[16]}}, icvt_out_1[16:0]} : {{33{intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]};
assign intp_out_fp16_2 = is_nan_in[2] ? {{33{icvt_out_2[16]}}, icvt_out_2[16:0]} : {{33{intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]};
assign intp_out_fp16_3 = is_nan_in[3] ? {{33{icvt_out_3[16]}}, icvt_out_3[16:0]} : {{33{intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]};
assign intp_out_fp16 = {intp_out_fp16_3,intp_out_fp16_2,intp_out_fp16_1,intp_out_fp16_0};

assign intp_out_ext  = int8_en ? intp_out_int8 : (int16_en ? intp_out_int16 : intp_out_fp16);

assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : {mul_unit_pd_3,mul_unit_pd_2,mul_unit_pd_1,mul_unit_pd_0};
assign mul2ocvt_pvld_f = mul_bypass_en ? (sync2mul_pvld & intp2mul_pvld) : (&mul_unit_vld);




`ifndef SYNTHESIS
reg p1_pipe_rand_active;
`endif
always @(
  `ifndef SYNTHESIS
  p1_pipe_rand_active
  or 
     `endif
     mul2ocvt_pvld_f
  or p1_pipe_rand_ready
  or mul2ocvt_pd_f
  ) begin
  `ifdef SYNTHESIS
  p1_pipe_rand_valid = mul2ocvt_pvld_f;
  mul2ocvt_prdy_f = p1_pipe_rand_ready;
  p1_pipe_rand_data = mul2ocvt_pd_f;
  `else

  p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mul2ocvt_pvld_f;
  mul2ocvt_prdy_f = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready;
  p1_pipe_rand_data = (p1_pipe_rand_active)?  'bx : mul2ocvt_pd_f;

  `endif
end
`ifndef SYNTHESIS


integer p1_pipe_stall_cycles;
integer p1_pipe_stall_probability;
integer p1_pipe_stall_cycles_min;
integer p1_pipe_stall_cycles_max;
initial begin
  p1_pipe_stall_cycles = 0;
  p1_pipe_stall_probability = 0;
  p1_pipe_stall_cycles_min = 1;
  p1_pipe_stall_cycles_max = 10;
`ifndef SYNTH_LEVEL1_COMPILE
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_rand_probability=%d",  p1_pipe_stall_probability ) ) ;
  else if ( $value$plusargs(    "default_pipe_rand_probability=%d",  p1_pipe_stall_probability ) ) ;
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; 
  else if ( $value$plusargs(    "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; 
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_min=%d",  p1_pipe_stall_cycles_min  ) ) ;
  else if ( $value$plusargs(    "default_pipe_stall_cycles_min=%d",  p1_pipe_stall_cycles_min  ) ) ;
  if      ( $value$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_max=%d",  p1_pipe_stall_cycles_max  ) ) ;
  else if ( $value$plusargs(    "default_pipe_stall_cycles_max=%d",  p1_pipe_stall_cycles_max  ) ) ;
`endif
end

`ifndef SYNTH_LEVEL1_COMPILE
`ifdef SIMTOP_RANDOMIZE_STALLS
always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability;
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_min"  ) ) p1_pipe_stall_cycles_min  = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min;
  if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_mul_pipe_stall_cycles_max"  ) ) p1_pipe_stall_cycles_max  = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max;
end
`endif
`endif

reg p1_pipe_rand_enable;
reg p1_pipe_rand_poised;
always @(
  p1_pipe_stall_cycles
  or p1_pipe_stall_probability
  or mul2ocvt_pvld_f
  ) begin
  p1_pipe_rand_active = p1_pipe_stall_cycles != 0;
  p1_pipe_rand_enable = p1_pipe_stall_probability != 0;
  p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mul2ocvt_pvld_f === 1'b1;
end

always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_pipe_stall_cycles <= 1'b0;
  end else begin
  if (p1_pipe_rand_poised) begin
    if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin
      p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max);
    end
  end else if (p1_pipe_rand_active) begin
    p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1;
  end else begin
    p1_pipe_stall_cycles <= 0;
  end
  end
end

`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG

reg [47:0] prand_local_seed0;
reg prand_initialized0;
reg prand_no_rollpli0;
`endif
`endif
`endif

function [31:0] prand_inst0;

    input [31:0] min;
    input [31:0] max;
    reg [32:0] diff;
    
    begin
`ifdef SYNTH_LEVEL1_COMPILE
        prand_inst0 = min;
`else
`ifdef SYNTHESIS
        prand_inst0 = min;
`else
`ifdef PRAND_VERILOG
        if (prand_initialized0 !== 1'b1) begin
            prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI");
            if (!prand_no_rollpli0)
                prand_local_seed0 = {$prand_get_seed(0), 16'b0};
            prand_initialized0 = 1'b1;
        end
        if (prand_no_rollpli0) begin
            prand_inst0 = min;
        end else begin
            diff = max - min + 1;
            prand_inst0 = min + prand_local_seed0[47:16] % diff;

            prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11;
        end
`else
`ifdef PRAND_OFF
        prand_inst0 = min;
`else
        prand_inst0 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
    end

endfunction


`ifdef SYNTH_LEVEL1_COMPILE
`else
`ifdef SYNTHESIS
`else
`ifdef PRAND_VERILOG

reg [47:0] prand_local_seed1;
reg prand_initialized1;
reg prand_no_rollpli1;
`endif
`endif
`endif

function [31:0] prand_inst1;

    input [31:0] min;
    input [31:0] max;
    reg [32:0] diff;
    
    begin
`ifdef SYNTH_LEVEL1_COMPILE
        prand_inst1 = min;
`else
`ifdef SYNTHESIS
        prand_inst1 = min;
`else
`ifdef PRAND_VERILOG
        if (prand_initialized1 !== 1'b1) begin
            prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI");
            if (!prand_no_rollpli1)
                prand_local_seed1 = {$prand_get_seed(1), 16'b0};
            prand_initialized1 = 1'b1;
        end
        if (prand_no_rollpli1) begin
            prand_inst1 = min;
        end else begin
            diff = max - min + 1;
            prand_inst1 = min + prand_local_seed1[47:16] % diff;

            prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11;
        end
`else
`ifdef PRAND_OFF
        prand_inst1 = min;
`else
        prand_inst1 = $RollPLI(min, max, "auto");
`endif
`endif
`endif
`endif
    end

endfunction

`endif


always @(
  p1_pipe_rand_valid
  or p1_skid_ready_flop
  or p1_skid_pipe_ready
  or p1_skid_valid
  ) begin
  p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready;  
  p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch;
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_skid_valid <= 1'b0;
    p1_skid_ready_flop <= 1'b1;
    p1_pipe_rand_ready <= 1'b1;
  end else begin
  p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch;
  p1_skid_ready_flop <= p1_skid_ready;
  p1_pipe_rand_ready <= p1_skid_ready;
  end
end
always @(posedge nvdla_core_clk) begin

  p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data;

end
always @(
  p1_skid_ready_flop
  or p1_pipe_rand_valid
  or p1_skid_valid
  or p1_pipe_rand_data
  or p1_skid_data
  ) begin
  p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; 

  p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data;

end

always @(
  p1_pipe_ready
  or p1_pipe_valid
  ) begin
  p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid;
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    p1_pipe_valid <= 1'b0;
  end else begin
  p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1;
  end
end
always @(posedge nvdla_core_clk) begin

  p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data;

end
always @(
  p1_pipe_ready_bc
  ) begin
  p1_skid_pipe_ready = p1_pipe_ready_bc;
end

always @(
  p1_pipe_valid
  or mul2ocvt_prdy
  or p1_pipe_data
  ) begin
  mul2ocvt_pvld = p1_pipe_valid;
  p1_pipe_ready = mul2ocvt_prdy;
  mul2ocvt_pd = p1_pipe_data;
end

`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS
wire p1_assert_clk = nvdla_core_clk;
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_no_x #(0,1,0,"No X's allowed on control signals")      zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul2ocvt_pvld^mul2ocvt_prdy^mul2ocvt_pvld_f^mul2ocvt_prdy_f));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif

  nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready")      zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul2ocvt_pvld_f && !mul2ocvt_prdy_f), (mul2ocvt_pvld_f), (mul2ocvt_prdy_f));

`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`endif


endmodule