data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:41: Cannot find file containing module: 'bw_u1_nand3_1x'\nbw_u1_nand3_1x I1 (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_nand3_1x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_nand3_1x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_nand3_1x.sv\n             bw_u1_nand3_1x\n             bw_u1_nand3_1x.v\n             bw_u1_nand3_1x.sv\n             obj_dir/bw_u1_nand3_1x\n             obj_dir/bw_u1_nand3_1x.v\n             obj_dir/bw_u1_nand3_1x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:46: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x I2 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:50: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x I3 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:54: Cannot find file containing module: 'bw_u1_nor2_2x'\nbw_u1_nor2_2x I4 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:58: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x I9 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:62: Cannot find file containing module: 'bw_u1_nor2_1x'\nbw_u1_nor2_1x I12 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:66: Cannot find file containing module: 'bw_u1_nor3_1x'\nbw_u1_nor3_1x I13 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:71: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x I47 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:74: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x I52 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:77: Cannot find file containing module: 'bw_u1_nand2_1x'\nbw_u1_nand2_1x I53 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:81: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x I54 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_logic.v:84: Cannot find file containing module: 'bw_io_ddr_vref_logic_high'\nbw_io_ddr_vref_logic_high x0 (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module bw_io_ddr_vref_logic(a ,vrefcode ,c ,b ,vdd18 );
output [7:0]	vrefcode ;
input		a ;
input		c ;
input		b ;
input		vdd18 ;
 
wire		net202 ;
wire		net185 ;
wire		net190 ;
wire		net193 ;
wire		net0106 ;
wire		net196 ;
wire		net0107 ;
wire		net198 ;
wire		net0109 ;
wire		net0120 ;
wire		net181 ;
 
 
bw_u1_nand3_1x I1 (
     .z               (net202 ),
     .a               (a ),
     .b               (b ),
     .c               (c ) );
bw_u1_nand2_1x I2 (
     .z               (net196 ),
     .a               (a ),
     .b               (b ) );
bw_u1_nand2_1x I3 (
     .z               (net193 ),
     .a               (net0107 ),
     .b               (a ) );
bw_u1_nor2_2x I4 (
     .z               (net190 ),
     .a               (c ),
     .b               (b ) );
bw_u1_nand2_1x I9 (
     .z               (net198 ),
     .a               (b ),
     .b               (c ) );
bw_u1_nor2_1x I12 (
     .z               (net185 ),
     .a               (b ),
     .b               (a ) );
bw_u1_nor3_1x I13 (
     .z               (net181 ),
     .a               (c ),
     .b               (b ),
     .c               (a ) );
bw_u1_inv_1x I47 (
     .z               (net0106 ),
     .a               (a ) );
bw_u1_inv_1x I52 (
     .z               (net0109 ),
     .a               (net0120 ) );
bw_u1_nand2_1x I53 (
     .z               (net0120 ),
     .a               (net0106 ),
     .b               (net198 ) );
bw_u1_inv_1x I54 (
     .z               (net0107 ),
     .a               (net190 ) );
bw_io_ddr_vref_logic_high x0 (
     .in              ({net202 ,net196 ,net193 ,net0106 ,net0109 ,net185
             ,net181 } ),
     .vrefcode        ({vrefcode } ),
     .vdd18           (vdd18 ) );
endmodule
module bw_io_ddr_vref_logic(a ,vrefcode ,c ,b ,vdd18 );

output [7:0]	vrefcode ;
input		a ;
input		c ;
input		b ;
input		vdd18 ;
 
wire		net202 ;
wire		net185 ;
wire		net190 ;
wire		net193 ;
wire		net0106 ;
wire		net196 ;
wire		net0107 ;
wire		net198 ;
wire		net0109 ;
wire		net0120 ;
wire		net181 ;
 
 
bw_u1_nand3_1x I1 (
     .z               (net202 ),
     .a               (a ),
     .b               (b ),
     .c               (c ) );
bw_u1_nand2_1x I2 (
     .z               (net196 ),
     .a               (a ),
     .b               (b ) );
bw_u1_nand2_1x I3 (
     .z               (net193 ),
     .a               (net0107 ),
     .b               (a ) );
bw_u1_nor2_2x I4 (
     .z               (net190 ),
     .a               (c ),
     .b               (b ) );
bw_u1_nand2_1x I9 (
     .z               (net198 ),
     .a               (b ),
     .b               (c ) );
bw_u1_nor2_1x I12 (
     .z               (net185 ),
     .a               (b ),
     .b               (a ) );
bw_u1_nor3_1x I13 (
     .z               (net181 ),
     .a               (c ),
     .b               (b ),
     .c               (a ) );
bw_u1_inv_1x I47 (
     .z               (net0106 ),
     .a               (a ) );
bw_u1_inv_1x I52 (
     .z               (net0109 ),
     .a               (net0120 ) );
bw_u1_nand2_1x I53 (
     .z               (net0120 ),
     .a               (net0106 ),
     .b               (net198 ) );
bw_u1_inv_1x I54 (
     .z               (net0107 ),
     .a               (net190 ) );
bw_io_ddr_vref_logic_high x0 (
     .in              ({net202 ,net196 ,net193 ,net0106 ,net0109 ,net185
             ,net181 } ),
     .vrefcode        ({vrefcode } ),
     .vdd18           (vdd18 ) );
endmodule