data/full_repos/permissive/453980391/src/and_beh.v
data/verilator_xmls/fb00c446-a31e-4a30-9602-8b833e0a5598.xml
module and_b(out, x, y);
    input x, y;
    output out;
    assign out = x & y;
endmodule
module and_b(out, x, y);

    input x, y;
    output out;
    assign out = x & y;
endmodule