data/full_repos/permissive/462608388/RTL/FPU for OR1200 CPU/mul.v
1: b'%Error: Cannot find file containing module: for\n        ... Looked in:\n             data/full_repos/permissive/462608388/RTL/FPU/for\n             data/full_repos/permissive/462608388/RTL/FPU/for.v\n             data/full_repos/permissive/462608388/RTL/FPU/for.sv\n             for\n             for.v\n             for.sv\n             obj_dir/for\n             obj_dir/for.v\n             obj_dir/for.sv\n%Error: Cannot find file containing module: OR1200\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/462608388\n%Error: Cannot find file containing module: data/full_repos/permissive/462608388/RTL/FPU\n%Error: Cannot find file containing module: CPU/mul.v\n%Error: Exiting due to 5 error(s)\n'
module DW02_mult_inst( inst_A, inst_B, PRODUCT_inst,clk );
parameter A_width = 24;
parameter B_width = 24;
input [A_width-1 : 0] inst_A;
input [B_width-1 : 0] inst_B;

output reg [A_width+B_width-1 : 0] PRODUCT_inst;

input clk;
wire [A_width+B_width-1 : 0] out0;
reg [A_width+B_width-1 : 0] out1;
reg [A_width+B_width-1 : 0] out2;










DW02_mult #(A_width, B_width)
U1 ( .A(inst_A), .B(inst_B), .TC(1'b0), .PRODUCT(out0) );

always @ (posedge clk)
begin
	out1 = out0;
end
always @ (posedge clk)
begin
	out2 = out1;
end

always @ (posedge clk)
begin
	PRODUCT_inst = out2;
end

endmodule
module DW02_mult_inst( inst_A, inst_B, PRODUCT_inst,clk );

parameter A_width = 24;
parameter B_width = 24;
input [A_width-1 : 0] inst_A;
input [B_width-1 : 0] inst_B;

output reg [A_width+B_width-1 : 0] PRODUCT_inst;

input clk;
wire [A_width+B_width-1 : 0] out0;
reg [A_width+B_width-1 : 0] out1;
reg [A_width+B_width-1 : 0] out2;










DW02_mult #(A_width, B_width)
U1 ( .A(inst_A), .B(inst_B), .TC(1'b0), .PRODUCT(out0) );

always @ (posedge clk)
begin
	out1 = out0;
end
always @ (posedge clk)
begin
	out2 = out1;
end

always @ (posedge clk)
begin
	PRODUCT_inst = out2;
end

endmodule