data/full_repos/permissive/409594175/made/SignExtend8.v
data/verilator_xmls/d1e00614-60bd-400d-a93f-166d7901be56.xml
module SignExtend8(
    input   wire   [31:0]   memory_data,
    output  wire   [31:0]   sign_out_32 
);

    assign sign_out_32 = {{24{1'b0}}, memory_data[7:0]}; 

endmodule
module SignExtend8(
    input   wire   [31:0]   memory_data,
    output  wire   [31:0]   sign_out_32 
);


    assign sign_out_32 = {{24{1'b0}}, memory_data[7:0]}; 

endmodule