data/full_repos/permissive/517031174/Template/top.v
1: b'%Error: data/full_repos/permissive/517031174/Template/top.v:57: Cannot find file containing module: \'pll\'\npll u_pll(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/517031174/Template,data/full_repos/permissive/517031174/pll\n             data/full_repos/permissive/517031174/Template,data/full_repos/permissive/517031174/pll.v\n             data/full_repos/permissive/517031174/Template,data/full_repos/permissive/517031174/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/517031174/Template/top.v:62: Cannot find file containing module: \'pll_dac\'\npll_dac u_pll_dac(\n^~~~~~~\n%Error: data/full_repos/permissive/517031174/Template/top.v:72: Cannot find file containing module: \'spi\'\nspi u_spi(\n^~~\n%Error: data/full_repos/permissive/517031174/Template/top.v:104: Cannot find file containing module: \'fifo_16b_8192w\'\nfifo_16b_8192w u_fifo_16b_8192w(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517031174/Template/top.v:124: Cannot find file containing module: \'adc_module_9226\'\nadc_module_9226 u0_adc_module_9226(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517031174/Template/top.v:154: Cannot find file containing module: \'adc_module_9226\'\nadc_module_9226 u1_adc_module_9226(\n^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:192: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance top\n        cmd_data_length <= 4\'d0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:226: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= 4\'d1;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:230: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= 4\'d2;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:234: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= 4\'d1;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:238: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= 4\'d0;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:250: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= cmd_data_length - 4\'d1;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:248: Operator GT expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                    if(cmd_data_length > 4\'d1) begin\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:258: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'rxd_data\' generates 16 bits.\n                                                                       : ... In instance top\n                    adc_sample_freq <= (adc_sample_freq<<16) | rxd_data;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:262: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= cmd_data_length - 4\'d1;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:260: Operator GT expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                    if(cmd_data_length > 4\'d1) begin\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:273: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                        cmd_data_length <= cmd_data_length - 4\'d1;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:271: Operator GT expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                       : ... In instance top\n                    if(cmd_data_length > 4\'d1) begin\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/517031174/Template/top.v:339: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance top\n                    cmd_state <= 4\'b0000;\n                              ^~\n%Error: Exiting due to 6 error(s), 13 warning(s)\n'
module top (
    input clk,
	input rst_n,

    input ad9226_otr_0,
    input [11:0] ad9226_data_in_0,
    output ad9226_clk_0,

    input ad9226_otr_1,
    input [11:0] ad9226_data_in_1,
    output ad9226_clk_1,

    output dac_clk,
    output dac_pd,
    output [11:0] dac_data,

    input           CS_N,
    input           SCK,
    input           MOSI,
    output          MISO
);



parameter DATA_SCAN=16'h0000;

parameter CMD_HEAD=16'hAABB;
parameter CMD_ADC=16'hCADC;
parameter CMD_ADC_SELECT=16'hCA01;
parameter CMD_ADC_FREQ=16'hCA02;
parameter CMD_ADC_POINTS=16'hCA03;
parameter CMD_DAC=16'hCDAC;
parameter CMD_DAC_SELECT=16'hCD01;
parameter CMD_DAC_FREQ=16'hCD02;
parameter CMD_DAC_PHASE=16'hCD03;
parameter CMD_TAIL=16'hBBAA;

parameter ADC_9226_0=16'hADC0;
parameter ADC_9226_1=16'hADC1;

parameter READ_HEAD=16'hCCDD;
parameter WRITE_WAIT=16'hABAD;
parameter TXD_START=16'hABCD;
parameter TXD_WAIT=16'hB2B3;
parameter TXD_END=16'hDCBA;





parameter READ_TAIL=16'hDDCC;


wire clk_256M;
wire clk_165M;
wire clk_64M;
pll u_pll(
    .inclk0 (clk ),
    .c0     (clk_256M),
    .c1     (clk_64M)
);
pll_dac u_pll_dac(
    .inclk0 (clk ),
    .c0     (clk_165M     )
);


wire rxd_flag_p;
wire txd_flag_p;
wire [15:0]  rxd_data;
reg [15:0]  txd_data;
spi u_spi(
    .clk        (clk        ),
    .rst_n      (rst_n      ),
    .CS_N       (CS_N       ),
    .SCK        (SCK        ),
    .MOSI       (MOSI       ),
    .MISO       (MISO       ),
    .rxd_flag_p (rxd_flag_p ),
    .rxd_data   (rxd_data   ),
    .txd_data   (txd_data   )
);


wire fifo_rd_en;
wire fifo_wr_busy;
wire fifo_rdreq;
wire fifo_rdempty;
wire fifo_wrclk;
wire fifo_wrreq;
wire fifo_wrfull;
wire [12:0] fifo_rd_num;
wire [12:0] fifo_wr_num;
wire [15:0] fifo_di;
wire [15:0] fifo_do;
reg fifo_aclr;

assign fifo_rdreq = (adc_select==ADC_9226_0)?ad9226_fifo_rdreq_0:((adc_select==ADC_9226_1)?ad9226_fifo_rdreq_1:0);
assign fifo_wrclk = (adc_select==ADC_9226_0)?ad9226_fifo_wrclk_0:((adc_select==ADC_9226_1)?ad9226_fifo_wrclk_1:0);
assign fifo_wrreq = (adc_select==ADC_9226_0)?ad9226_fifo_wrreq_0:((adc_select==ADC_9226_1)?ad9226_fifo_wrreq_1:0);
assign fifo_di = (adc_select==ADC_9226_0)?ad9226_fifo_di_0:((adc_select==ADC_9226_1)?ad9226_fifo_di_1:0);
assign fifo_rd_en=(adc_select==ADC_9226_0)?ad9226_fifo_rd_en_0:((adc_select==ADC_9226_1)?ad9226_fifo_rd_en_1:0);

fifo_16b_8192w u_fifo_16b_8192w(
    .aclr    (fifo_aclr    ),
    .data    (fifo_di    ),
    .rdclk   (rdclk   ),
    .rdreq   (fifo_rdreq   ),
    .wrclk   (fifo_wrclk   ),
    .wrreq   (fifo_wrreq   ),
    .q       (fifo_do       ),
    .rdempty (fifo_rdempty ),
    .rdusedw (fifo_rd_num ),
    .wrfull  (fifo_wrfull  ),
    .wrusedw (fifo_wr_num )
);

wire ad9226_fifo_rd_en_0;
wire ad9226_fifo_rdreq_0;
wire ad9226_fifo_wrclk_0;
wire ad9226_fifo_wrreq_0;
wire [15:0] ad9226_fifo_di_0;

adc_module_9226 u0_adc_module_9226(
    .rst_n                  ((adc_select==ADC_9226_0)?1'b1:1'b0),
    .clk_256M               (clk_256M               ),
    .rxd_flag_p             (rxd_flag_p             ),

    .ad9226_otr             (ad9226_otr_0             ),
    .ad9226_data_in         (ad9226_data_in_0         ),
    .ad9226_clk             (ad9226_clk_0             ),

    .ad9226_sample_freq     ((adc_select==ADC_9226_0)?adc_sample_freq:0),
    .ad9226_sample_num      ((adc_select==ADC_9226_0)?adc_sample_num:0),
    .ad9226_fifo_rd_control ((adc_select==ADC_9226_0)?adc_fifo_rd_control:0),
    .ad9226_fifo_wr_control ((adc_select==ADC_9226_0)?adc_fifo_wr_control:0),
    .ad9226_fifo_rd_num     ((adc_select==ADC_9226_0)?fifo_rd_num:0),
    .ad9226_fifo_wrfull     ((adc_select==ADC_9226_0)?fifo_wrfull:0),
    .ad9226_fifo_wr_num     ((adc_select==ADC_9226_0)?fifo_wr_num:0),

    .ad9226_fifo_rd_en      (ad9226_fifo_rd_en_0      ),
    .ad9226_fifo_rdreq      (ad9226_fifo_rdreq_0      ),
    .ad9226_fifo_wrclk      (ad9226_fifo_wrclk_0      ),
    .ad9226_fifo_wrreq      (ad9226_fifo_wrreq_0      ),
    .ad9226_fifo_di         (ad9226_fifo_di_0         )
);

wire ad9226_fifo_rd_en_1;
wire ad9226_fifo_rdreq_1;
wire ad9226_fifo_wrclk_1;
wire ad9226_fifo_wrreq_1;
wire [15:0] ad9226_fifo_di_1;

adc_module_9226 u1_adc_module_9226(
    .rst_n                  ((adc_select==ADC_9226_1)?1'b1:1'b0),
    .clk_256M               (clk_256M               ),
    .rxd_flag_p             (rxd_flag_p             ),

    .ad9226_otr             (ad9226_otr_1             ),
    .ad9226_data_in         (ad9226_data_in_1         ),
    .ad9226_clk             (ad9226_clk_1             ),

    .ad9226_sample_freq     ((adc_select==ADC_9226_1)?adc_sample_freq:0),
    .ad9226_sample_num      ((adc_select==ADC_9226_1)?adc_sample_num:0),
    .ad9226_fifo_rd_control ((adc_select==ADC_9226_1)?adc_fifo_rd_control:0),
    .ad9226_fifo_wr_control ((adc_select==ADC_9226_1)?adc_fifo_wr_control:0),
    .ad9226_fifo_rd_num     ((adc_select==ADC_9226_1)?fifo_rd_num:0),
    .ad9226_fifo_wrfull     ((adc_select==ADC_9226_1)?fifo_wrfull:0),
    .ad9226_fifo_wr_num     ((adc_select==ADC_9226_1)?fifo_wr_num:0),

    .ad9226_fifo_rd_en      (ad9226_fifo_rd_en_1      ),
    .ad9226_fifo_rdreq      (ad9226_fifo_rdreq_1      ),
    .ad9226_fifo_wrclk      (ad9226_fifo_wrclk_1      ),
    .ad9226_fifo_wrreq      (ad9226_fifo_wrreq_1      ),
    .ad9226_fifo_di         (ad9226_fifo_di_1         )
);

reg [15:0] adc_select;
reg adc_fifo_rd_control;
reg adc_fifo_wr_control;
reg [31:0] adc_sample_freq;
reg [15:0] adc_sample_num;
reg [15:0] txd_sample_num;
reg [15:0] cmd_data_length;
reg [15:0] cmd_state;



always @(posedge rxd_flag_p or negedge rst_n) begin
    if(!rst_n) begin
        cmd_state <= DATA_SCAN;
        cmd_data_length <= 4'd0;
        adc_select <= 16'h0000;
        adc_sample_num=16'd512;
        txd_sample_num=16'd512;
        fifo_aclr <=1'b0;
        txd_data<= 16'h0;
        adc_fifo_wr_control<=1'd1;
        adc_fifo_rd_control<=1'd0;

    end else begin
        case(cmd_state)
            DATA_SCAN:
                begin
                    fifo_aclr <=1'b0;
                    txd_data<= 16'h0;
                    if(rxd_data == CMD_HEAD)
                        cmd_state <= CMD_HEAD;
                    else if(rxd_data == READ_HEAD)
                        cmd_state <= READ_HEAD;
                    else
                        cmd_state <= cmd_state;
                 end
            CMD_HEAD:
                begin
                    if(rxd_data == CMD_ADC)
                        cmd_state <= CMD_ADC;  
                    else if(rxd_data == CMD_DAC)
                        cmd_state <= CMD_DAC;  
                    else
                        cmd_state <= cmd_state;  
                end
            CMD_ADC:
                begin
                    if(rxd_data == CMD_ADC_SELECT) begin
                        cmd_data_length <= 4'd1;
                        cmd_state <= CMD_ADC_SELECT;
                    end
                    else if(rxd_data == CMD_ADC_FREQ) begin
                        cmd_data_length <= 4'd2;
                        cmd_state <= CMD_ADC_FREQ;
                    end
                    else if(rxd_data == CMD_ADC_POINTS) begin
                        cmd_data_length <= 4'd1;
                        cmd_state <= CMD_ADC_POINTS;
                    end  
                    else if(rxd_data == CMD_TAIL) begin
                        cmd_data_length <= 4'd0;
                        cmd_state <= READ_HEAD;
                    end 
                    else begin
                        cmd_state <= cmd_state; 
                    end  
                end
            CMD_ADC_SELECT:
                begin
                    adc_select <= rxd_data;
                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_ADC_FREQ:
                begin
                    adc_sample_freq <= (adc_sample_freq<<16) | rxd_data;

                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_ADC_POINTS:
                begin
                    adc_sample_num <= rxd_data;
                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_TAIL:
                begin
                    cmd_state <= DATA_SCAN;
                end
            READ_HEAD:
                begin

                    fifo_aclr <= 1'b1;

                    adc_fifo_wr_control<=1'd1;
                    adc_fifo_rd_control<=1'd0;
                    txd_data <= 16'h0;
                    cmd_state <= WRITE_WAIT;
                end
            WRITE_WAIT:
                begin

                    fifo_aclr <= 1'b0;
                    if(fifo_rd_en)begin

                        adc_fifo_rd_control<=1'd1;
                        adc_fifo_wr_control<=1'd0;
                        txd_data <= TXD_START;
                        txd_sample_num <= adc_sample_num;
                        cmd_state <= TXD_WAIT;
                    end
                    else begin
                        cmd_state <= cmd_state;    
                    end
                end
            TXD_WAIT:
                begin
                    if(txd_sample_num!=16'd0) begin

                        txd_sample_num <= txd_sample_num-1'b1;
                        txd_data <= fifo_do;
                        cmd_state <= cmd_state;
                    end 
                    else begin

                        fifo_aclr <= 1'b1;
                        adc_fifo_rd_control <= 1'd0;
                        adc_fifo_wr_control <= 1'd1;
                        adc_select<=16'h0;
                        cmd_state <= READ_TAIL; 
                        txd_data<= TXD_END;
                    end
                end
             READ_TAIL:
                begin
                    txd_data<= 16'h0;
                    if(rxd_data==16'hDCAB) begin
                        cmd_state <= DATA_SCAN; 
                    end
                    else begin
                        cmd_state <= cmd_state;
                    end
                end
            default: 
                begin
                    cmd_state <= 4'b0000;
                end
        endcase
    end
end















endmodule
module top (
    input clk,
	input rst_n,

    input ad9226_otr_0,
    input [11:0] ad9226_data_in_0,
    output ad9226_clk_0,

    input ad9226_otr_1,
    input [11:0] ad9226_data_in_1,
    output ad9226_clk_1,

    output dac_clk,
    output dac_pd,
    output [11:0] dac_data,

    input           CS_N,
    input           SCK,
    input           MOSI,
    output          MISO
);




parameter DATA_SCAN=16'h0000;

parameter CMD_HEAD=16'hAABB;
parameter CMD_ADC=16'hCADC;
parameter CMD_ADC_SELECT=16'hCA01;
parameter CMD_ADC_FREQ=16'hCA02;
parameter CMD_ADC_POINTS=16'hCA03;
parameter CMD_DAC=16'hCDAC;
parameter CMD_DAC_SELECT=16'hCD01;
parameter CMD_DAC_FREQ=16'hCD02;
parameter CMD_DAC_PHASE=16'hCD03;
parameter CMD_TAIL=16'hBBAA;

parameter ADC_9226_0=16'hADC0;
parameter ADC_9226_1=16'hADC1;

parameter READ_HEAD=16'hCCDD;
parameter WRITE_WAIT=16'hABAD;
parameter TXD_START=16'hABCD;
parameter TXD_WAIT=16'hB2B3;
parameter TXD_END=16'hDCBA;





parameter READ_TAIL=16'hDDCC;


wire clk_256M;
wire clk_165M;
wire clk_64M;
pll u_pll(
    .inclk0 (clk ),
    .c0     (clk_256M),
    .c1     (clk_64M)
);
pll_dac u_pll_dac(
    .inclk0 (clk ),
    .c0     (clk_165M     )
);


wire rxd_flag_p;
wire txd_flag_p;
wire [15:0]  rxd_data;
reg [15:0]  txd_data;
spi u_spi(
    .clk        (clk        ),
    .rst_n      (rst_n      ),
    .CS_N       (CS_N       ),
    .SCK        (SCK        ),
    .MOSI       (MOSI       ),
    .MISO       (MISO       ),
    .rxd_flag_p (rxd_flag_p ),
    .rxd_data   (rxd_data   ),
    .txd_data   (txd_data   )
);


wire fifo_rd_en;
wire fifo_wr_busy;
wire fifo_rdreq;
wire fifo_rdempty;
wire fifo_wrclk;
wire fifo_wrreq;
wire fifo_wrfull;
wire [12:0] fifo_rd_num;
wire [12:0] fifo_wr_num;
wire [15:0] fifo_di;
wire [15:0] fifo_do;
reg fifo_aclr;

assign fifo_rdreq = (adc_select==ADC_9226_0)?ad9226_fifo_rdreq_0:((adc_select==ADC_9226_1)?ad9226_fifo_rdreq_1:0);
assign fifo_wrclk = (adc_select==ADC_9226_0)?ad9226_fifo_wrclk_0:((adc_select==ADC_9226_1)?ad9226_fifo_wrclk_1:0);
assign fifo_wrreq = (adc_select==ADC_9226_0)?ad9226_fifo_wrreq_0:((adc_select==ADC_9226_1)?ad9226_fifo_wrreq_1:0);
assign fifo_di = (adc_select==ADC_9226_0)?ad9226_fifo_di_0:((adc_select==ADC_9226_1)?ad9226_fifo_di_1:0);
assign fifo_rd_en=(adc_select==ADC_9226_0)?ad9226_fifo_rd_en_0:((adc_select==ADC_9226_1)?ad9226_fifo_rd_en_1:0);

fifo_16b_8192w u_fifo_16b_8192w(
    .aclr    (fifo_aclr    ),
    .data    (fifo_di    ),
    .rdclk   (rdclk   ),
    .rdreq   (fifo_rdreq   ),
    .wrclk   (fifo_wrclk   ),
    .wrreq   (fifo_wrreq   ),
    .q       (fifo_do       ),
    .rdempty (fifo_rdempty ),
    .rdusedw (fifo_rd_num ),
    .wrfull  (fifo_wrfull  ),
    .wrusedw (fifo_wr_num )
);

wire ad9226_fifo_rd_en_0;
wire ad9226_fifo_rdreq_0;
wire ad9226_fifo_wrclk_0;
wire ad9226_fifo_wrreq_0;
wire [15:0] ad9226_fifo_di_0;

adc_module_9226 u0_adc_module_9226(
    .rst_n                  ((adc_select==ADC_9226_0)?1'b1:1'b0),
    .clk_256M               (clk_256M               ),
    .rxd_flag_p             (rxd_flag_p             ),

    .ad9226_otr             (ad9226_otr_0             ),
    .ad9226_data_in         (ad9226_data_in_0         ),
    .ad9226_clk             (ad9226_clk_0             ),

    .ad9226_sample_freq     ((adc_select==ADC_9226_0)?adc_sample_freq:0),
    .ad9226_sample_num      ((adc_select==ADC_9226_0)?adc_sample_num:0),
    .ad9226_fifo_rd_control ((adc_select==ADC_9226_0)?adc_fifo_rd_control:0),
    .ad9226_fifo_wr_control ((adc_select==ADC_9226_0)?adc_fifo_wr_control:0),
    .ad9226_fifo_rd_num     ((adc_select==ADC_9226_0)?fifo_rd_num:0),
    .ad9226_fifo_wrfull     ((adc_select==ADC_9226_0)?fifo_wrfull:0),
    .ad9226_fifo_wr_num     ((adc_select==ADC_9226_0)?fifo_wr_num:0),

    .ad9226_fifo_rd_en      (ad9226_fifo_rd_en_0      ),
    .ad9226_fifo_rdreq      (ad9226_fifo_rdreq_0      ),
    .ad9226_fifo_wrclk      (ad9226_fifo_wrclk_0      ),
    .ad9226_fifo_wrreq      (ad9226_fifo_wrreq_0      ),
    .ad9226_fifo_di         (ad9226_fifo_di_0         )
);

wire ad9226_fifo_rd_en_1;
wire ad9226_fifo_rdreq_1;
wire ad9226_fifo_wrclk_1;
wire ad9226_fifo_wrreq_1;
wire [15:0] ad9226_fifo_di_1;

adc_module_9226 u1_adc_module_9226(
    .rst_n                  ((adc_select==ADC_9226_1)?1'b1:1'b0),
    .clk_256M               (clk_256M               ),
    .rxd_flag_p             (rxd_flag_p             ),

    .ad9226_otr             (ad9226_otr_1             ),
    .ad9226_data_in         (ad9226_data_in_1         ),
    .ad9226_clk             (ad9226_clk_1             ),

    .ad9226_sample_freq     ((adc_select==ADC_9226_1)?adc_sample_freq:0),
    .ad9226_sample_num      ((adc_select==ADC_9226_1)?adc_sample_num:0),
    .ad9226_fifo_rd_control ((adc_select==ADC_9226_1)?adc_fifo_rd_control:0),
    .ad9226_fifo_wr_control ((adc_select==ADC_9226_1)?adc_fifo_wr_control:0),
    .ad9226_fifo_rd_num     ((adc_select==ADC_9226_1)?fifo_rd_num:0),
    .ad9226_fifo_wrfull     ((adc_select==ADC_9226_1)?fifo_wrfull:0),
    .ad9226_fifo_wr_num     ((adc_select==ADC_9226_1)?fifo_wr_num:0),

    .ad9226_fifo_rd_en      (ad9226_fifo_rd_en_1      ),
    .ad9226_fifo_rdreq      (ad9226_fifo_rdreq_1      ),
    .ad9226_fifo_wrclk      (ad9226_fifo_wrclk_1      ),
    .ad9226_fifo_wrreq      (ad9226_fifo_wrreq_1      ),
    .ad9226_fifo_di         (ad9226_fifo_di_1         )
);

reg [15:0] adc_select;
reg adc_fifo_rd_control;
reg adc_fifo_wr_control;
reg [31:0] adc_sample_freq;
reg [15:0] adc_sample_num;
reg [15:0] txd_sample_num;
reg [15:0] cmd_data_length;
reg [15:0] cmd_state;



always @(posedge rxd_flag_p or negedge rst_n) begin
    if(!rst_n) begin
        cmd_state <= DATA_SCAN;
        cmd_data_length <= 4'd0;
        adc_select <= 16'h0000;
        adc_sample_num=16'd512;
        txd_sample_num=16'd512;
        fifo_aclr <=1'b0;
        txd_data<= 16'h0;
        adc_fifo_wr_control<=1'd1;
        adc_fifo_rd_control<=1'd0;

    end else begin
        case(cmd_state)
            DATA_SCAN:
                begin
                    fifo_aclr <=1'b0;
                    txd_data<= 16'h0;
                    if(rxd_data == CMD_HEAD)
                        cmd_state <= CMD_HEAD;
                    else if(rxd_data == READ_HEAD)
                        cmd_state <= READ_HEAD;
                    else
                        cmd_state <= cmd_state;
                 end
            CMD_HEAD:
                begin
                    if(rxd_data == CMD_ADC)
                        cmd_state <= CMD_ADC;  
                    else if(rxd_data == CMD_DAC)
                        cmd_state <= CMD_DAC;  
                    else
                        cmd_state <= cmd_state;  
                end
            CMD_ADC:
                begin
                    if(rxd_data == CMD_ADC_SELECT) begin
                        cmd_data_length <= 4'd1;
                        cmd_state <= CMD_ADC_SELECT;
                    end
                    else if(rxd_data == CMD_ADC_FREQ) begin
                        cmd_data_length <= 4'd2;
                        cmd_state <= CMD_ADC_FREQ;
                    end
                    else if(rxd_data == CMD_ADC_POINTS) begin
                        cmd_data_length <= 4'd1;
                        cmd_state <= CMD_ADC_POINTS;
                    end  
                    else if(rxd_data == CMD_TAIL) begin
                        cmd_data_length <= 4'd0;
                        cmd_state <= READ_HEAD;
                    end 
                    else begin
                        cmd_state <= cmd_state; 
                    end  
                end
            CMD_ADC_SELECT:
                begin
                    adc_select <= rxd_data;
                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_ADC_FREQ:
                begin
                    adc_sample_freq <= (adc_sample_freq<<16) | rxd_data;

                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_ADC_POINTS:
                begin
                    adc_sample_num <= rxd_data;
                    if(cmd_data_length > 4'd1) begin
                        cmd_state <= cmd_state;
                        cmd_data_length <= cmd_data_length - 4'd1;
                    end
                    else begin
                        cmd_state <= CMD_ADC;
                    end
                end
            CMD_TAIL:
                begin
                    cmd_state <= DATA_SCAN;
                end
            READ_HEAD:
                begin

                    fifo_aclr <= 1'b1;

                    adc_fifo_wr_control<=1'd1;
                    adc_fifo_rd_control<=1'd0;
                    txd_data <= 16'h0;
                    cmd_state <= WRITE_WAIT;
                end
            WRITE_WAIT:
                begin

                    fifo_aclr <= 1'b0;
                    if(fifo_rd_en)begin

                        adc_fifo_rd_control<=1'd1;
                        adc_fifo_wr_control<=1'd0;
                        txd_data <= TXD_START;
                        txd_sample_num <= adc_sample_num;
                        cmd_state <= TXD_WAIT;
                    end
                    else begin
                        cmd_state <= cmd_state;    
                    end
                end
            TXD_WAIT:
                begin
                    if(txd_sample_num!=16'd0) begin

                        txd_sample_num <= txd_sample_num-1'b1;
                        txd_data <= fifo_do;
                        cmd_state <= cmd_state;
                    end 
                    else begin

                        fifo_aclr <= 1'b1;
                        adc_fifo_rd_control <= 1'd0;
                        adc_fifo_wr_control <= 1'd1;
                        adc_select<=16'h0;
                        cmd_state <= READ_TAIL; 
                        txd_data<= TXD_END;
                    end
                end
             READ_TAIL:
                begin
                    txd_data<= 16'h0;
                    if(rxd_data==16'hDCAB) begin
                        cmd_state <= DATA_SCAN; 
                    end
                    else begin
                        cmd_state <= cmd_state;
                    end
                end
            default: 
                begin
                    cmd_state <= 4'b0000;
                end
        endcase
    end
end















endmodule