data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/F_ADD.v
data/verilator_xmls/a93b4c64-4f05-4455-9dca-63c4b832afa4.xml
module F_ADD(A,B,C,S,O);
input A,B,C;
output S,O;

assign S=A^B^C;
assign O=(A&B)|C&(A^B);

endmodule
module F_ADD(A,B,C,S,O);

input A,B,C;
output S,O;

assign S=A^B^C;
assign O=(A&B)|C&(A^B);

endmodule