data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v
1: b'%Error: data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v:91: Cannot find include file: hdmi_setup.v\n    `include "hdmi_setup.v" \n             ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414664427/it6613,data/full_repos/permissive/414664427/hdmi_setup.v\n             data/full_repos/permissive/414664427/it6613,data/full_repos/permissive/414664427/hdmi_setup.v.v\n             data/full_repos/permissive/414664427/it6613,data/full_repos/permissive/414664427/hdmi_setup.v.sv\n             hdmi_setup.v\n             hdmi_setup.v.v\n             hdmi_setup.v.sv\n             obj_dir/hdmi_setup.v\n             obj_dir/hdmi_setup.v.v\n             obj_dir/hdmi_setup.v.sv\n%Error: data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v:39: syntax error, unexpected \')\', expecting \'[\'\n       );\n       ^\n%Error: data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v:50: syntax error, unexpected assign\nassign hdmi_r = {r3, r2, r1, r0, 8\'h0};\n^~~~~~\n%Error: data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v:72: syntax error, unexpected always\nalways @(posedge clk100) begin\n^~~~~~\n%Error: data/full_repos/permissive/414664427/it6613/i2c_lut_skel.v:89: syntax error, unexpected always\nalways @* begin\n^~~~~~\n%Error: Exiting due to 5 error(s)\n'
module top(
           input  wire clk100,
           output wire [11:0] hdmi_r,
           output wire [11:0] hdmi_g,
           output wire [11:0] hdmi_b,

           output wire hdmi_pclk,

           output wire hdmi_hsync,
           output wire hdmi_vsync,

           output wire hdmi_de,
           output wire hdmi_scl,
           inout wire hdmi_sda,
       );


wire hsync;
wire vsync;
wire blank;

wire r3, r2, r1, r0;
wire g3, g2, g1, g0;
wire b3, b2, b1, b0;

assign hdmi_r = {r3, r2, r1, r0, 8'h0};
assign hdmi_g = {g3, g2, g1, g0, 8'h0};

assign hdmi_b = {b3, b2, b1, b0, 8'h0};

assign hdmi_hsync = hsync;
assign hdmi_vsync = vsync;
assign hdmi_de = ~blank;
assign hdmi_pclk = clk;

assign hdmi_scl = scl;
assign hdmi_sda = sda_output ? sda : 1'bz;
(* keep *)
wire hdmi_sda_in = hdmi_sda;



reg [9: 0] cycle_cnt;

wire tick = cycle_cnt == (1000/2 -1);

reg [$clog2(2048) -1:0] i2c_row;
always @(posedge clk100) begin
  if (!resetn) begin
    cycle_cnt <= 0;
    i2c_row <= 0;
  end else begin
    cycle_cnt <= tick ? 0 : cycle_cnt + 1; 
    if (tick) begin
      if (!&i2c_row) i2c_row <= i2c_row + 1;
    end
end
end


reg scl;
reg sda;
reg sda_output;

always @* begin
  case (i2c_row)
    `include "hdmi_setup.v"
    default:
      {scl, sda, sda_output} = {1'b1, 1'b1, 1'b1};
  endcase
end

endmodule
module top(
           input  wire clk100,
           output wire [11:0] hdmi_r,
           output wire [11:0] hdmi_g,
           output wire [11:0] hdmi_b,

           output wire hdmi_pclk,

           output wire hdmi_hsync,
           output wire hdmi_vsync,

           output wire hdmi_de,
           output wire hdmi_scl,
           inout wire hdmi_sda,
       );



wire hsync;
wire vsync;
wire blank;

wire r3, r2, r1, r0;
wire g3, g2, g1, g0;
wire b3, b2, b1, b0;

assign hdmi_r = {r3, r2, r1, r0, 8'h0};
assign hdmi_g = {g3, g2, g1, g0, 8'h0};

assign hdmi_b = {b3, b2, b1, b0, 8'h0};

assign hdmi_hsync = hsync;
assign hdmi_vsync = vsync;
assign hdmi_de = ~blank;
assign hdmi_pclk = clk;

assign hdmi_scl = scl;
assign hdmi_sda = sda_output ? sda : 1'bz;
(* keep *)
wire hdmi_sda_in = hdmi_sda;



reg [9: 0] cycle_cnt;

wire tick = cycle_cnt == (1000/2 -1);

reg [$clog2(2048) -1:0] i2c_row;
always @(posedge clk100) begin
  if (!resetn) begin
    cycle_cnt <= 0;
    i2c_row <= 0;
  end else begin
    cycle_cnt <= tick ? 0 : cycle_cnt + 1; 
    if (tick) begin
      if (!&i2c_row) i2c_row <= i2c_row + 1;
    end
end
end


reg scl;
reg sda;
reg sda_output;

always @* begin
  case (i2c_row)
    `include "hdmi_setup.v"
    default:
      {scl, sda, sda_output} = {1'b1, 1'b1, 1'b1};
  endcase
end

endmodule