data/full_repos/permissive/497819211/02/Add16_tb.v
1: b'%Error: data/full_repos/permissive/497819211/02/Add16_tb.v:1: Cannot find include file: Add16.v\n`include "Add16.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/02,data/full_repos/permissive/497819211/Add16.v\n             data/full_repos/permissive/497819211/02,data/full_repos/permissive/497819211/Add16.v.v\n             data/full_repos/permissive/497819211/02,data/full_repos/permissive/497819211/Add16.v.sv\n             Add16.v\n             Add16.v.v\n             Add16.v.sv\n             obj_dir/Add16.v\n             obj_dir/Add16.v.v\n             obj_dir/Add16.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/497819211/02/Add16_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n     #1 $fwrite(file, "|%16b|%16b|%16b|\\n", a,b,out);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/497819211/02/Add16_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Add16_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/02/Add16_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Add16_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Add16_tb();

	integer file;

	reg[15:0] a = 16'b0000000000000000;
	reg[15:0] b = 16'b0000000000000000;
	wire[15:0] out;
	
	Add16 ADD16(
	    .a(a),
		.b(b),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%16b|%16b|%16b|\n", a,b,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Add16_tb.vcd");
  		$dumpvars(0, Add16_tb);
		file = $fopen("Add16.out","w");
    	$fwrite(file, "|a|b|out|\n");
		
		a=16'b0000000000000000;b=16'b0000000000000000;
		display();

        a=16'b0000000000000000;b=16'b1111111111111111;
		display();
  		
		a=16'b1111111111111111;b=16'b1111111111111111;
		display();

        a=16'b1010101010101010;b=16'b0101010101010101;
		display();
		
		a=16'b0011110011000011;b=16'b0000111111110000;
		display();

        a=16'b0001001000110100;b=16'b1001100001110110;
		display();
		$finish();	
	end

endmodule
module Add16_tb();


	integer file;

	reg[15:0] a = 16'b0000000000000000;
	reg[15:0] b = 16'b0000000000000000;
	wire[15:0] out;
	
	Add16 ADD16(
	    .a(a),
		.b(b),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%16b|%16b|%16b|\n", a,b,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Add16_tb.vcd");
  		$dumpvars(0, Add16_tb);
		file = $fopen("Add16.out","w");
    	$fwrite(file, "|a|b|out|\n");
		
		a=16'b0000000000000000;b=16'b0000000000000000;
		display();

        a=16'b0000000000000000;b=16'b1111111111111111;
		display();
  		
		a=16'b1111111111111111;b=16'b1111111111111111;
		display();

        a=16'b1010101010101010;b=16'b0101010101010101;
		display();
		
		a=16'b0011110011000011;b=16'b0000111111110000;
		display();

        a=16'b0001001000110100;b=16'b1001100001110110;
		display();
		$finish();	
	end

endmodule