data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:18: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\nmodule tlb import ariane_pkg::*; #(\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:20: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter int unsigned ASID_WIDTH  = 1\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:21: syntax error, unexpected ')', expecting ';'\n  )(\n  ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:23: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                    rst_ni,    \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:24: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                    flush_i,   \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:26: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  tlb_update_t             update_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:29: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [ASID_WIDTH-1:0]   lu_asid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:30: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [riscv::VLEN-1:0]  lu_vaddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:30: syntax error, unexpected ::, expecting ':'\n    input  logic [riscv::VLEN-1:0]  lu_vaddr_i,\n                       ^~\n                                                                                                       : ... Perhaps 'riscv' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:33: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [riscv::VLEN-1:0]  vaddr_to_be_flushed_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:33: syntax error, unexpected ::, expecting ':'\n    input  logic [riscv::VLEN-1:0]  vaddr_to_be_flushed_i,\n                       ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:35: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                    lu_is_1G_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:36: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                    lu_hit_o\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:42: syntax error, unexpected ::, expecting ':'\n      logic [riscv::VPN2:0]  vpn2;\n                  ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:48: syntax error, unexpected '}'\n    } [TLB_ENTRIES-1:0] tags_q, tags_n;\n    ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:52: syntax error, unexpected ::, expecting ':'\n    logic [riscv::VPN2:0] vpn2;\n                ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:58: syntax error, unexpected always_comb\n    always_comb begin : translation\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:70: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:103: syntax error, unexpected assign\n    assign asid_to_be_flushed_is0 =  ~(|asid_to_be_flushed_i);\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:113: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:155: syntax error, unexpected always_comb\n    always_comb begin : plru_replacement\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:180: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin\n                                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:183: syntax error, unexpected if\n            if (lu_hit[i] & lu_access_i) begin\n            ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:185: syntax error, unexpected IDENTIFIER\n                for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin\n                                           ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:209: syntax error, unexpected IDENTIFIER\n        for (int unsigned i = 0; i < TLB_ENTRIES; i += 1) begin\n                                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:212: syntax error, unexpected IDENTIFIER\n            en = 1'b1;\n            ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tlb.sv:213: syntax error, unexpected IDENTIFIER\n            for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin\n                                       ^~~\n%Error: Exiting due to 27 error(s)\n"
function int countSetBits(logic[TLB_ENTRIES-1:0] vector);
      automatic int count = 0;
      foreach (vector[idx]) begin
        count += vector[idx];
      end
      return count;
    endfunction
function int countSetBits(logic[TLB_ENTRIES-1:0] vector);

      automatic int count = 0;
      foreach (vector[idx]) begin
        count += vector[idx];
      end
      return count;
    endfunction