data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/sign_extend.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/sign_extend.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [bits_in-1:0] in;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/sign_extend.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [bits_out-1:0] out;\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module sign_extend (in,out);
	parameter bits_in=0;
	parameter bits_out=0;
	
	input [bits_in-1:0] in;
	output [bits_out-1:0] out;
	
	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
	
endmodule
module sign_extend (in,out);

	parameter bits_in=0;
	parameter bits_out=0;
	
	input [bits_in-1:0] in;
	output [bits_out-1:0] out;
	
	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
	
endmodule