data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp/cells_map.v:29: Multiple top level modules\n                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                           : ... Top module \'$__inpad\'\nmodule \\$__inpad (input I, output O);\n       ^~~~~~~~~\n                                                                                                           : ... Top module \'$__outpad\'\nmodule \\$__outpad (input I, output O);\n       ^~~~~~~~~~\n                                                                                                           : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp/cells_map.v:40: Little bit endian vector: MSB < LSB of bit range: -1:0\n   input [WIDTH-1:0] A;\n         ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp/cells_map.v:30: Cannot find file containing module: \'cyclone10lp_io_obuf\'\n   cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1\'b1));\n   ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp,data/full_repos/permissive/441359809/cyclone10lp_io_obuf\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp,data/full_repos/permissive/441359809/cyclone10lp_io_obuf.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp,data/full_repos/permissive/441359809/cyclone10lp_io_obuf.sv\n             cyclone10lp_io_obuf\n             cyclone10lp_io_obuf.v\n             cyclone10lp_io_obuf.sv\n             obj_dir/cyclone10lp_io_obuf\n             obj_dir/cyclone10lp_io_obuf.v\n             obj_dir/cyclone10lp_io_obuf.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cyclone10lp/cells_map.v:25: Cannot find file containing module: \'cyclone10lp_io_ibuf\'\n   cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1\'b0));\n   ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   (* force_downto *)
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	 assign Y = ~A[0];
      end else
        if (WIDTH == 2) begin
           cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                .dataa(A[0]),
                                                                                .datab(A[1]),
                                                                                .datac(1'b1),
                                                                                .datad(1'b1));
        end else
          if(WIDTH == 3) begin
	     cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                  .dataa(A[0]),
                                                                                  .datab(A[1]),
                                                                                  .datac(A[2]),
                                                                                  .datad(1'b1));
          end else
            if(WIDTH == 4) begin
	       cyclone10lp_lcell_comb #(.lut_mask(LUT),
                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                    .dataa(A[0]),
                                                                                    .datab(A[1]),
                                                                                    .datac(A[2]),
                                                                                    .datad(A[3]));
            end else
	             wire _TECHMAP_FAIL_ = 1;
   endgenerate

endmodule
module \$lut (A, Y);

   parameter WIDTH  = 0;
   parameter LUT    = 0;
   (* force_downto *)
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	 assign Y = ~A[0];
      end else
        if (WIDTH == 2) begin
           cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                .dataa(A[0]),
                                                                                .datab(A[1]),
                                                                                .datac(1'b1),
                                                                                .datad(1'b1));
        end else
          if(WIDTH == 3) begin
	     cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                  .dataa(A[0]),
                                                                                  .datab(A[1]),
                                                                                  .datac(A[2]),
                                                                                  .datad(1'b1));
          end else
            if(WIDTH == 4) begin
	       cyclone10lp_lcell_comb #(.lut_mask(LUT),
                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                    .dataa(A[0]),
                                                                                    .datab(A[1]),
                                                                                    .datac(A[2]),
                                                                                    .datad(A[3]));
            end else
	             wire _TECHMAP_FAIL_ = 1;
   endgenerate

endmodule