data/full_repos/permissive/474275312/Day 2/Post Implementation/primitives.v
1: b'%Error: Cannot find file containing module: 2/Post\n        ... Looked in:\n             data/full_repos/permissive/474275312/Day/2/Post\n             data/full_repos/permissive/474275312/Day/2/Post.v\n             data/full_repos/permissive/474275312/Day/2/Post.sv\n             2/Post\n             2/Post.v\n             2/Post.sv\n             obj_dir/2/Post\n             obj_dir/2/Post.v\n             obj_dir/2/Post.sv\n%Error: Cannot find file containing module: Implementation,data/full_repos/permissive/474275312\n%Error: Cannot find file containing module: data/full_repos/permissive/474275312/Day\n%Error: Cannot find file containing module: Implementation/primitives.v\n%Error: Exiting due to 4 error(s)\n'
module dual_port_ram #(
    parameter ADDR_WIDTH = 1,
    parameter DATA_WIDTH = 1
) (
    input clock,

    input [ADDR_WIDTH-1:0] addr1,
    input [ADDR_WIDTH-1:0] addr2,
    input [DATA_WIDTH-1:0] data1,
    input [DATA_WIDTH-1:0] data2,
    input we1,
    input we2,
    output reg [DATA_WIDTH-1:0] out1,
    output reg [DATA_WIDTH-1:0] out2
);

    localparam MEM_DEPTH = 2 ** ADDR_WIDTH;

    reg [DATA_WIDTH-1:0] Mem[MEM_DEPTH-1:0];

    specify
        (clock*>out1)="";
        (clock*>out2)="";
        $setup(addr1, posedge clock, "");
        $setup(addr2, posedge clock, "");
        $setup(data1, posedge clock, "");
        $setup(data2, posedge clock, "");
        $setup(we1, posedge clock, "");
        $setup(we2, posedge clock, "");
        $hold(posedge clock, addr1, "");
        $hold(posedge clock, addr2, "");
        $hold(posedge clock, data1, "");
        $hold(posedge clock, data2, "");
        $hold(posedge clock, we1, "");
        $hold(posedge clock, we2, "");
    endspecify
   
    always@(posedge clock) begin
        if(we1) begin
            Mem[addr1] = data1;
        end
        out1 = Mem[addr1];
    end

    always@(posedge clock) begin
        if(we2) begin
            Mem[addr2] = data2;
        end
        out2 = Mem[addr2];
    end
   
endmodule
module dual_port_ram #(
    parameter ADDR_WIDTH = 1,
    parameter DATA_WIDTH = 1
) (
    input clock,

    input [ADDR_WIDTH-1:0] addr1,
    input [ADDR_WIDTH-1:0] addr2,
    input [DATA_WIDTH-1:0] data1,
    input [DATA_WIDTH-1:0] data2,
    input we1,
    input we2,
    output reg [DATA_WIDTH-1:0] out1,
    output reg [DATA_WIDTH-1:0] out2
);


    localparam MEM_DEPTH = 2 ** ADDR_WIDTH;

    reg [DATA_WIDTH-1:0] Mem[MEM_DEPTH-1:0];

    specify
        (clock*>out1)="";
        (clock*>out2)="";
        $setup(addr1, posedge clock, "");
        $setup(addr2, posedge clock, "");
        $setup(data1, posedge clock, "");
        $setup(data2, posedge clock, "");
        $setup(we1, posedge clock, "");
        $setup(we2, posedge clock, "");
        $hold(posedge clock, addr1, "");
        $hold(posedge clock, addr2, "");
        $hold(posedge clock, data1, "");
        $hold(posedge clock, data2, "");
        $hold(posedge clock, we1, "");
        $hold(posedge clock, we2, "");
    endspecify
   
    always@(posedge clock) begin
        if(we1) begin
            Mem[addr1] = data1;
        end
        out1 = Mem[addr1];
    end

    always@(posedge clock) begin
        if(we2) begin
            Mem[addr2] = data2;
        end
        out2 = Mem[addr2];
    end
   
endmodule