data/full_repos/permissive/484799296/verilog/ram/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:16: Unknown escape sequence: \\d\n        $display("enable\\twrite_enable\\taddr\\t\\tdata\\data_bus");\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:17: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t\\t%b\\t%b\\t%b", enable, write_enable, addr, data, data_bus);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 enable=1; write_enable=0; addr=0; data=1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; write_enable=0; addr=2; data=2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; write_enable=1; addr=2; data=2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/ram/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; write_enable=0; addr=2; data=0;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module top();

    reg enable;
    reg write_enable;
    reg [11:0] addr;
    reg [3:0] data;
    wire [3:0] data_bus;

    ram RAM(enable, write_enable, addr, data_bus);

    assign data_bus = ~(enable & ~write_enable)?data:4'bzzzz;

    initial begin
        enable=0; write_enable=0; addr=0; data=1;

        $display("enable\twrite_enable\taddr\t\tdata\data_bus");
        $monitor("%b\t%b\t\t%b\t%b\t%b", enable, write_enable, addr, data, data_bus);

        #1 enable=1; write_enable=0; addr=0; data=1;
        #2 enable=1; write_enable=0; addr=2; data=2;
        #2 enable=1; write_enable=1; addr=2; data=2;
        #2 enable=1; write_enable=0; addr=2; data=0;

        $finish;
    end


endmodule
module top();


    reg enable;
    reg write_enable;
    reg [11:0] addr;
    reg [3:0] data;
    wire [3:0] data_bus;

    ram RAM(enable, write_enable, addr, data_bus);

    assign data_bus = ~(enable & ~write_enable)?data:4'bzzzz;

    initial begin
        enable=0; write_enable=0; addr=0; data=1;

        $display("enable\twrite_enable\taddr\t\tdata\data_bus");
        $monitor("%b\t%b\t\t%b\t%b\t%b", enable, write_enable, addr, data, data_bus);

        #1 enable=1; write_enable=0; addr=0; data=1;
        #2 enable=1; write_enable=0; addr=2; data=2;
        #2 enable=1; write_enable=1; addr=2; data=2;
        #2 enable=1; write_enable=0; addr=2; data=0;

        $finish;
    end


endmodule