data/full_repos/permissive/42434302/ivltests/final.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/final.v:4: Unsupported: Ignoring delay on this delayed statement.\ninitial #5 x = 2;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/final.v:5: Unsupported: Ignoring delay on this delayed statement.\nalways @(x) #5 x = 3;\n            ^\n%Warning-MULTITOP: data/full_repos/permissive/42434302/ivltests/final.v:14: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                          : ... Top module \'t\'\nmodule t;\n       ^\n                                                                          : ... Top module \'t2\'\nmodule t2;\n       ^~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t;
reg [7:0] x = 1;

initial #5 x = 2;
always @(x) #5 x = 3;

final begin
   if (x == 3) $display("x =%d, PASSED", x);
   $finish();
   $display("FAILED! Executed past $finish in final block!");
end
endmodule
module t;

reg [7:0] x = 1;

initial #5 x = 2;
always @(x) #5 x = 3;

final begin
   if (x == 3) $display("x =%d, PASSED", x);
   $finish();
   $display("FAILED! Executed past $finish in final block!");
end
endmodule