data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/test/aes_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/test/aes_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/test/aes_testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #3\n    ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/test/aes_testbench.v:69: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/test/aes_testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module aes_testbench_seq();

  localparam CC = 1;

  reg clk;
  reg rst;

  wire [127:0] g_init;
  wire [127:0] e_init;
  wire [127:0] o;

  aes_11cc utt_aes_seq
  (
    .clk(clk),
    .rst(rst),
    .g_init(g_init),
    .e_init(e_init),
    .o(o)
  );


  assign g_init = 128'h00000000000000000000000000000000;
  assign e_init = 128'h00000000000000000000000000000000;

  integer i;
  initial begin
    clk =1;
    rst =1;
    #3
    rst =0;
    for(i=0;i<11;i=i+1) begin
      @(posedge clk);
    end
    $stop;
  end

  always #5 clk = ~clk;

endmodule
module aes_testbench_seq();


  localparam CC = 1;

  reg clk;
  reg rst;

  wire [127:0] g_init;
  wire [127:0] e_init;
  wire [127:0] o;

  aes_11cc utt_aes_seq
  (
    .clk(clk),
    .rst(rst),
    .g_init(g_init),
    .e_init(e_init),
    .o(o)
  );


  assign g_init = 128'h00000000000000000000000000000000;
  assign e_init = 128'h00000000000000000000000000000000;

  integer i;
  initial begin
    clk =1;
    rst =1;
    #3
    rst =0;
    for(i=0;i<11;i=i+1) begin
      @(posedge clk);
    end
    $stop;
  end

  always #5 clk = ~clk;

endmodule