data/full_repos/permissive/514992586/1_Verilog_language/Modules/24_Module_shift8.v
1: b"%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/24_Module_shift8.v:11: Cannot find file containing module: 'my_dff8'\n    my_dff8 instance1(.clk(clk), .d(d), .q(w1));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff8\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff8.v\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff8.sv\n             my_dff8\n             my_dff8.v\n             my_dff8.sv\n             obj_dir/my_dff8\n             obj_dir/my_dff8.v\n             obj_dir/my_dff8.sv\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/24_Module_shift8.v:12: Cannot find file containing module: 'my_dff8'\n    my_dff8 instance2(.clk(clk), .d(w1), .q(w2));\n    ^~~~~~~\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/24_Module_shift8.v:13: Cannot find file containing module: 'my_dff8'\n    my_dff8 instance3(.clk(clk), .d(w2), .q(w3));\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    wire [7:0] w1;
    wire [7:0] w2;
    wire [7:0] w3;
    my_dff8 instance1(.clk(clk), .d(d), .q(w1));
    my_dff8 instance2(.clk(clk), .d(w1), .q(w2));
    my_dff8 instance3(.clk(clk), .d(w2), .q(w3));
    
    always @(*)
        begin
            case (sel)
                0: q = d;
                1: q = w1;
                2: q = w2;
                3: q = w3;
            endcase
        end
endmodule
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);


    wire [7:0] w1;
    wire [7:0] w2;
    wire [7:0] w3;
    my_dff8 instance1(.clk(clk), .d(d), .q(w1));
    my_dff8 instance2(.clk(clk), .d(w1), .q(w2));
    my_dff8 instance3(.clk(clk), .d(w2), .q(w3));
    
    always @(*)
        begin
            case (sel)
                0: q = d;
                1: q = w1;
                2: q = w2;
                3: q = w3;
            endcase
        end
endmodule