data/full_repos/permissive/488093047/Verilog Codes/TB_RippleCarrySign.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_RippleCarrySign.v\n%Error: Exiting due to 3 error(s)\n'
module TB_RippleCarrySign();
parameter N=32;
reg [N-1:0]A,B;
reg Cin;
wire Cout;

wire [N-1:0]Sum;

RippleCarrySign #(.N(N)) DUT1(.A(A),.B(B),.Sum(Sum),.Cin(Cin),.Cout(Cout));
initial begin

A=32'd153;B=32'd415;Cin=1'b0;
#10 A=32'd133;B=32'd542;Cin=1'b0;

#10 A=-32'd153;B=32'd415;Cin=1'b0;
#10 A=32'd133;B=-32'd542;Cin=1'b0;

end
endmodule
module TB_RippleCarrySign();

parameter N=32;
reg [N-1:0]A,B;
reg Cin;
wire Cout;

wire [N-1:0]Sum;

RippleCarrySign #(.N(N)) DUT1(.A(A),.B(B),.Sum(Sum),.Cin(Cin),.Cout(Cout));
initial begin

A=32'd153;B=32'd415;Cin=1'b0;
#10 A=32'd133;B=32'd542;Cin=1'b0;

#10 A=-32'd153;B=32'd415;Cin=1'b0;
#10 A=32'd133;B=-32'd542;Cin=1'b0;

end
endmodule