data/full_repos/permissive/50724111/vga/bench/verilog/vga_demo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/50724111/vga/bench/verilog/vga_demo_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/50724111/vga/bench/verilog/vga_demo_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/vga/bench/verilog/vga_demo_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #1 VGA_CLK = !VGA_CLK;\n        ^\n%Error: data/full_repos/permissive/50724111/vga/bench/verilog/vga_demo_tb.v:16: Cannot find file containing module: \'vga_demo\'\n    vga_demo vga_ins(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50724111/vga/bench/verilog,data/full_repos/permissive/50724111/vga_demo\n             data/full_repos/permissive/50724111/vga/bench/verilog,data/full_repos/permissive/50724111/vga_demo.v\n             data/full_repos/permissive/50724111/vga/bench/verilog,data/full_repos/permissive/50724111/vga_demo.sv\n             vga_demo\n             vga_demo.v\n             vga_demo.sv\n             obj_dir/vga_demo\n             obj_dir/vga_demo.v\n             obj_dir/vga_demo.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_demo_tb();


    reg VGA_CLK;
    reg RESET;
    wire [7:0] VGA_RED;
    wire [7:0] VGA_GREEN;
    wire [7:0] VGA_BLUE;
    wire VGA_HS;
    wire VGA_VS;
    wire BLANK_N;

    vga_demo vga_ins(
        .CLOCK_PIXEL(VGA_CLK),
        .RESET(RESET),
        .VGA_RED(VGA_RED),
        .VGA_GREEN(VGA_GREEN),
        .VGA_BLUE(VGA_BLUE),
        .VGA_HS(VGA_HS),
        .VGA_VS(VGA_VS),
        .BLANK_N(BLANK_N)
    );

    initial begin
        RESET = 0;
        VGA_CLK = 0;
        
        #2
        RESET = 1;
        
        #2
        RESET = 0;

    
    end
    

    always begin
        #1 VGA_CLK = !VGA_CLK;
    end
 
endmodule
module vga_demo_tb();



    reg VGA_CLK;
    reg RESET;
    wire [7:0] VGA_RED;
    wire [7:0] VGA_GREEN;
    wire [7:0] VGA_BLUE;
    wire VGA_HS;
    wire VGA_VS;
    wire BLANK_N;

    vga_demo vga_ins(
        .CLOCK_PIXEL(VGA_CLK),
        .RESET(RESET),
        .VGA_RED(VGA_RED),
        .VGA_GREEN(VGA_GREEN),
        .VGA_BLUE(VGA_BLUE),
        .VGA_HS(VGA_HS),
        .VGA_VS(VGA_VS),
        .BLANK_N(BLANK_N)
    );

    initial begin
        RESET = 0;
        VGA_CLK = 0;
        
        #2
        RESET = 1;
        
        #2
        RESET = 0;

    
    end
    

    always begin
        #1 VGA_CLK = !VGA_CLK;
    end
 
endmodule