data/full_repos/permissive/429196919/FPGA/genericIOSateliteEnv_TB.v
1: b"%Error: data/full_repos/permissive/429196919/FPGA/genericIOSateliteEnv_TB.v:227: syntax error, unexpected type, expecting IDENTIFIER or '=' or do or final\n  reg[7:0] type;\n           ^~~~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSateliteEnv_TB.v:238: syntax error, unexpected '=', expecting '('\n    type = type_p;\n         ^\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSateliteEnv_TB.v:266: syntax error, unexpected ==, expecting '('\n     if(type == 0)\n             ^~\n%Error: data/full_repos/permissive/429196919/FPGA/genericIOSateliteEnv_TB.v:273: syntax error, unexpected ==, expecting '('\n     if(type == 0)\n             ^~\n%Error: Exiting due to 4 error(s)\n"
module PROBE(input wire[7:0] type_p, input wire pin, input wire triggerEdge_p, input wire[63:0] timeout_p, input wire arm, input wire masterClk, output reg[7:0] state = `PROBE_READY, output reg[7:0] errCause = `ERR_CAUSE_NONE, output reg[63:0] pulseTime = 0, output reg[63:0] timeToTrigger = 0, output reg[63:0] cycleTime = 0);	
		reg triggerEdge, prevArm, prevPin;
		reg[7:0] type;
		reg[63:0] timeout;
		time t0;

		always @ (posedge masterClk) begin 
			prevArm <= arm;
			prevPin <= pin;
			if(arm && !prevArm) begin
				t0 = $time;
				state = `PROBE_ARMED;
				errCause = `ERR_CAUSE_NONE;
				type = type_p;
				triggerEdge = triggerEdge_p;
				timeout = timeout_p;
				pulseTime = 0;
				cycleTime = 0;
			end
			else if(timeout && $time-t0 > timeout && state != `PROBE_READY) begin
				if(state == `PROBE_ARMED)
					errCause = `ERR_CAUSE_TRIGGER1_TIMEOUT;
				else if(state == `PROBE_TRIGGERED1)
					errCause = `ERR_CAUSE_TRIGGER2_TIMEOUT;
				else if(state == `PROBE_TRIGGERED2)
					errCause = `ERR_CAUSE_READY_TIMEOUT;
				state = `PROBE_ERR;
			end
			else if(state == `PROBE_ARMED) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && pin && !prevPin) begin
					state = `PROBE_TRIGGERED1;
					timeToTrigger = $time - t0;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && !pin && prevPin) begin
					state = `PROBE_TRIGGERED1;
					timeToTrigger = $time - t0;
				end
			end
			else if(state == `PROBE_TRIGGERED1) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && !pin && prevPin) begin
					pulseTime = $time - t0 - timeToTrigger;
					if(type == `PROBE_TYPE_PWM)
						state = `PROBE_TRIGGERED2;
					else
						state = `PROBE_READY;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && pin && !prevPin) begin
					pulseTime = $time - t0 - timeToTrigger;
					if(type == `PROBE_TYPE_PWM)
						state = `PROBE_TRIGGERED2;
					else
						state = `PROBE_READY;
				end
			end
			else if (state == `PROBE_TRIGGERED2) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && pin && !prevPin) begin
					cycleTime = $time - t0 - timeToTrigger;
					state = `PROBE_READY;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && !pin && prevPin) begin
					cycleTime = $time - t0 - timeToTrigger;
					state = `PROBE_READY;
				end
			end
		end
	endmodule
module PROBE(input wire[7:0] type_p, input wire pin, input wire triggerEdge_p, input wire[63:0] timeout_p, input wire arm, input wire masterClk, output reg[7:0] state = `PROBE_READY, output reg[7:0] errCause = `ERR_CAUSE_NONE, output reg[63:0] pulseTime = 0, output reg[63:0] timeToTrigger = 0, output reg[63:0] cycleTime = 0);
	
		reg triggerEdge, prevArm, prevPin;
		reg[7:0] type;
		reg[63:0] timeout;
		time t0;

		always @ (posedge masterClk) begin 
			prevArm <= arm;
			prevPin <= pin;
			if(arm && !prevArm) begin
				t0 = $time;
				state = `PROBE_ARMED;
				errCause = `ERR_CAUSE_NONE;
				type = type_p;
				triggerEdge = triggerEdge_p;
				timeout = timeout_p;
				pulseTime = 0;
				cycleTime = 0;
			end
			else if(timeout && $time-t0 > timeout && state != `PROBE_READY) begin
				if(state == `PROBE_ARMED)
					errCause = `ERR_CAUSE_TRIGGER1_TIMEOUT;
				else if(state == `PROBE_TRIGGERED1)
					errCause = `ERR_CAUSE_TRIGGER2_TIMEOUT;
				else if(state == `PROBE_TRIGGERED2)
					errCause = `ERR_CAUSE_READY_TIMEOUT;
				state = `PROBE_ERR;
			end
			else if(state == `PROBE_ARMED) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && pin && !prevPin) begin
					state = `PROBE_TRIGGERED1;
					timeToTrigger = $time - t0;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && !pin && prevPin) begin
					state = `PROBE_TRIGGERED1;
					timeToTrigger = $time - t0;
				end
			end
			else if(state == `PROBE_TRIGGERED1) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && !pin && prevPin) begin
					pulseTime = $time - t0 - timeToTrigger;
					if(type == `PROBE_TYPE_PWM)
						state = `PROBE_TRIGGERED2;
					else
						state = `PROBE_READY;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && pin && !prevPin) begin
					pulseTime = $time - t0 - timeToTrigger;
					if(type == `PROBE_TYPE_PWM)
						state = `PROBE_TRIGGERED2;
					else
						state = `PROBE_READY;
				end
			end
			else if (state == `PROBE_TRIGGERED2) begin
				if(triggerEdge == `TRIGGER_EDGE_POS && pin && !prevPin) begin
					cycleTime = $time - t0 - timeToTrigger;
					state = `PROBE_READY;
				end
				else if(triggerEdge == `TRIGGER_EDGE_NEG && !pin && prevPin) begin
					cycleTime = $time - t0 - timeToTrigger;
					state = `PROBE_READY;
				end
			end
		end
	endmodule