data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/bdw_work/modules/dut/FLAT/v_rtl/dut_DECODE_128U_6_4.v
data/verilator_xmls/521724d2-0759-42fd-8aca-ad9e05218d5d.xml
module dut_DECODE_128U_6_4 (
	in1,
	out1
	);
input [6:0] in1;
output [127:0] out1;
wire [127:0] asc001;

assign asc001 = 128'B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
    << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_128U_6_4 (
	in1,
	out1
	);

input [6:0] in1;
output [127:0] out1;
wire [127:0] asc001;

assign asc001 = 128'B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
    << in1;

assign out1 = asc001;
endmodule