data/full_repos/permissive/439731184/counter_state_machine.v
1: b'%Error: data/full_repos/permissive/439731184/counter_state_machine.v:42: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%b\\t%h", $time, in, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1 flip;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #2 flip;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #2 flip;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #3 flip;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 flip;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 flip;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter_state_machine.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module csm_tb();

parameter N_BITS = 4;

reg in = 0;
wire[N_BITS-1:0] out;

csm #(N_BITS) C (out, in);

task flip; 
    in = !in;
endtask

initial begin
    $display("time\tin\tout");
    $monitor("%h\t%b\t%h", $time, in, out);
    #1 flip;
    #2 flip;
    #2 flip;
    #3 flip;
    #1 flip;
    #1 flip;
    #1 $finish;
end

endmodule
module csm_tb();


parameter N_BITS = 4;

reg in = 0;
wire[N_BITS-1:0] out;

csm #(N_BITS) C (out, in);

task flip; 
    in = !in;
endtask

initial begin
    $display("time\tin\tout");
    $monitor("%h\t%b\t%h", $time, in, out);
    #1 flip;
    #2 flip;
    #2 flip;
    #3 flip;
    #1 flip;
    #1 flip;
    #1 $finish;
end

endmodule