data/full_repos/permissive/528912093/Proiect/InputReg.v
1: b"%Error: data/full_repos/permissive/528912093/Proiect/InputReg.v:9: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire ;\n      ^\n%Error: data/full_repos/permissive/528912093/Proiect/InputReg.v:17: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module InputReg( DataIn[0],DataIn[1],DataIn[2],DataIn[3],EnableIn,B0,B3,B2,
 B1);
 input DataIn[0],DataIn[1],DataIn[2],DataIn[3],EnableIn;
 output B0,B3,B2,B1;
 wire ;
 bufif1 #(1) bufif1_1(B0,DataIn[0],EnableIn);
 bufif1 #(1) bufif1_2(B1,DataIn[1],EnableIn);
 bufif1 #(1) bufif1_3(B2,DataIn[2],EnableIn);
 bufif1 #(1) bufif1_4(B3,DataIn[3],EnableIn);
endmodule
module InputReg( DataIn[0],DataIn[1],DataIn[2],DataIn[3],EnableIn,B0,B3,B2,
 B1);

 input DataIn[0],DataIn[1],DataIn[2],DataIn[3],EnableIn;
 output B0,B3,B2,B1;
 wire ;
 bufif1 #(1) bufif1_1(B0,DataIn[0],EnableIn);
 bufif1 #(1) bufif1_2(B1,DataIn[1],EnableIn);
 bufif1 #(1) bufif1_3(B2,DataIn[2],EnableIn);
 bufif1 #(1) bufif1_4(B3,DataIn[3],EnableIn);
endmodule