data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl/wfg_core_top.sv
1: b"%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl/wfg_core_top.sv:39: Cannot find file containing module: 'wfg_core_wishbone_reg'\n    wfg_core_wishbone_reg wfg_core_wishbone_reg (\n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl,data/full_repos/permissive/500717851/wfg_core_wishbone_reg\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl,data/full_repos/permissive/500717851/wfg_core_wishbone_reg.v\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl,data/full_repos/permissive/500717851/wfg_core_wishbone_reg.sv\n             wfg_core_wishbone_reg\n             wfg_core_wishbone_reg.v\n             wfg_core_wishbone_reg.sv\n             obj_dir/wfg_core_wishbone_reg\n             obj_dir/wfg_core_wishbone_reg.v\n             obj_dir/wfg_core_wishbone_reg.sv\n%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_core/rtl/wfg_core_top.sv:63: Cannot find file containing module: 'wfg_core'\n    wfg_core wfg_core (\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module wfg_core_top #(
    parameter int BUSW = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    output wire       wfg_core_sync_o,
    output wire       wfg_core_subcycle_o,
    output wire       wfg_core_start_o,
    output wire [7:0] wfg_core_subcycle_cnt_o,
    output wire       active_o
);






    logic [23: 8] cfg_subcycle_q;
    logic [ 7: 0] cfg_sync_q;
    logic         ctrl_en_q;



    wfg_core_wishbone_reg wfg_core_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_subcycle_q_o(cfg_subcycle_q),
        .cfg_sync_q_o    (cfg_sync_q),
        .ctrl_en_q_o     (ctrl_en_q)


    );

    wfg_core wfg_core (
        .clk  (wb_clk_i),
        .rst_n(!wb_rst_i),


        .en_i(ctrl_en_q),


        .wfg_sync_count_i    (cfg_sync_q),
        .wfg_subcycle_count_i(cfg_subcycle_q),


        .wfg_core_sync_o        (wfg_core_sync_o),
        .wfg_core_subcycle_o    (wfg_core_subcycle_o),
        .wfg_core_start_o       (wfg_core_start_o),
        .wfg_core_subcycle_cnt_o(wfg_core_subcycle_cnt_o),
        .active_o               (active_o)
    );

endmodule
module wfg_core_top #(
    parameter int BUSW = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    output wire       wfg_core_sync_o,
    output wire       wfg_core_subcycle_o,
    output wire       wfg_core_start_o,
    output wire [7:0] wfg_core_subcycle_cnt_o,
    output wire       active_o
);







    logic [23: 8] cfg_subcycle_q;
    logic [ 7: 0] cfg_sync_q;
    logic         ctrl_en_q;



    wfg_core_wishbone_reg wfg_core_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_subcycle_q_o(cfg_subcycle_q),
        .cfg_sync_q_o    (cfg_sync_q),
        .ctrl_en_q_o     (ctrl_en_q)


    );

    wfg_core wfg_core (
        .clk  (wb_clk_i),
        .rst_n(!wb_rst_i),


        .en_i(ctrl_en_q),


        .wfg_sync_count_i    (cfg_sync_q),
        .wfg_subcycle_count_i(cfg_subcycle_q),


        .wfg_core_sync_o        (wfg_core_sync_o),
        .wfg_core_subcycle_o    (wfg_core_subcycle_o),
        .wfg_core_start_o       (wfg_core_start_o),
        .wfg_core_subcycle_cnt_o(wfg_core_subcycle_cnt_o),
        .active_o               (active_o)
    );

endmodule