data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/cla.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/cla.v:49: Cannot find file containing module: 'full_adder'\n    full_adder fai\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_adder\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_adder.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module cla
    (
     a,
     b,
     sum,
     c
     );




parameter WID = 6;




input [WID-1:0] a,b;

output [WID-1:0] sum;
output       c;







wire [WID:0] w_c;
wire [WID-1:0] w_g,w_p,w_s;

genvar i;

generate
for(i = 0; i<WID; i = i+1)
    begin : FAgen
    full_adder fai
            (
             .a(a[i]),
             .b(b[i]),
             .c_i(w_c[i]),
             .sum(w_s[i]),
             .c_o()
             );
    end
endgenerate

genvar j;
generate
    for (j=0;j<WID;j=j+1)
        begin : clgen
        assign w_g[j] = a[j] & b[j];
        assign w_p[j] = a[j] | b[j];
        assign w_c[j+1] = w_g[j] | (w_p[j] & w_c[j]);
        end
endgenerate

assign         w_c[0] = 1'b0;

assign         sum = w_s;
assign         c = w_c[WID];

endmodule
module cla
    (
     a,
     b,
     sum,
     c
     );





parameter WID = 6;




input [WID-1:0] a,b;

output [WID-1:0] sum;
output       c;







wire [WID:0] w_c;
wire [WID-1:0] w_g,w_p,w_s;

genvar i;

generate
for(i = 0; i<WID; i = i+1)
    begin : FAgen
    full_adder fai
            (
             .a(a[i]),
             .b(b[i]),
             .c_i(w_c[i]),
             .sum(w_s[i]),
             .c_o()
             );
    end
endgenerate

genvar j;
generate
    for (j=0;j<WID;j=j+1)
        begin : clgen
        assign w_g[j] = a[j] & b[j];
        assign w_p[j] = a[j] | b[j];
        assign w_c[j+1] = w_g[j] | (w_p[j] & w_c[j]);
        end
endgenerate

assign         w_c[0] = 1'b0;

assign         sum = w_s;
assign         c = w_c[WID];

endmodule