data/full_repos/permissive/52696447/testbench_mojo_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52696447/testbench_mojo_top.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/52696447/testbench_mojo_top.v:49: Cannot find file containing module: \'mojo_top\'\n mojo_top uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/mojo_top\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/mojo_top.v\n             data/full_repos/permissive/52696447,data/full_repos/permissive/52696447/mojo_top.sv\n             mojo_top\n             mojo_top.v\n             mojo_top.sv\n             obj_dir/mojo_top\n             obj_dir/mojo_top.v\n             obj_dir/mojo_top.sv\n%Error: data/full_repos/permissive/52696447/testbench_mojo_top.v:74: Cannot find file containing module: \'M24FC512\'\nM24FC512 eeprom (\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_mojo_top;


	reg clk;
	reg rst_n;
	reg cclk;
	reg spi_ss;
	reg spi_mosi;
	reg spi_sck;
	reg avr_tx;
	reg avr_rx_busy;


	wire [7:0] led;
	wire spi_miso;
	wire [3:0] spi_channel;
	wire avr_rx;
	wire i2c_scl;
	wire i2c_clk_in;


	wire i2c_sda;


	mojo_top uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.cclk(cclk), 
		.led(led), 
		.spi_miso(spi_miso), 
		.spi_ss(spi_ss), 
		.spi_mosi(spi_mosi), 
		.spi_sck(spi_sck), 
		.spi_channel(spi_channel), 
		.avr_tx(avr_tx), 
		.avr_rx(avr_rx), 
		.avr_rx_busy(avr_rx_busy), 
		.i2c_scl(i2c_scl), 
		.i2c_sda(i2c_sda), 
		.i2c_clk_in(i2c_clk_in)
	);


	wire A0 = 0;
wire A1 = 0;
wire A2 = 0;
wire WP = 0;
wire reset = ~rst_n;

M24FC512 eeprom (
	.A0(A0),
	.A1(A1),
	.A2(A2),
	.WP(WP),
	.SDA(i2c_sda),
	.SCL(i2c_scl),
	.RESET(reset)
	);

	initial begin

		clk = 0;
		forever begin 
			clk = #1 ~clk;
		end
	end

	initial begin

		rst_n = 0;
		cclk = 0;
		spi_ss = 0;
		spi_mosi = 0;
		spi_sck = 0;
		avr_tx = 0;
		avr_rx_busy = 0;


		#100;
        

		cclk = 1;
		rst_n = 1;

	end
      
endmodule
module testbench_mojo_top;



	reg clk;
	reg rst_n;
	reg cclk;
	reg spi_ss;
	reg spi_mosi;
	reg spi_sck;
	reg avr_tx;
	reg avr_rx_busy;


	wire [7:0] led;
	wire spi_miso;
	wire [3:0] spi_channel;
	wire avr_rx;
	wire i2c_scl;
	wire i2c_clk_in;


	wire i2c_sda;


	mojo_top uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.cclk(cclk), 
		.led(led), 
		.spi_miso(spi_miso), 
		.spi_ss(spi_ss), 
		.spi_mosi(spi_mosi), 
		.spi_sck(spi_sck), 
		.spi_channel(spi_channel), 
		.avr_tx(avr_tx), 
		.avr_rx(avr_rx), 
		.avr_rx_busy(avr_rx_busy), 
		.i2c_scl(i2c_scl), 
		.i2c_sda(i2c_sda), 
		.i2c_clk_in(i2c_clk_in)
	);


	wire A0 = 0;
wire A1 = 0;
wire A2 = 0;
wire WP = 0;
wire reset = ~rst_n;

M24FC512 eeprom (
	.A0(A0),
	.A1(A1),
	.A2(A2),
	.WP(WP),
	.SDA(i2c_sda),
	.SCL(i2c_scl),
	.RESET(reset)
	);

	initial begin

		clk = 0;
		forever begin 
			clk = #1 ~clk;
		end
	end

	initial begin

		rst_n = 0;
		cclk = 0;
		spi_ss = 0;
		spi_mosi = 0;
		spi_sck = 0;
		avr_tx = 0;
		avr_rx_busy = 0;


		#100;
        

		cclk = 1;
		rst_n = 1;

	end
      
endmodule