data/full_repos/permissive/40581558/fpga_sim/model_rec/cmd_gen_submodule.v
1: b"%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/cmd_gen_submodule.v:75: Cannot find file containing module: 'transmit_test_model'\n   transmit_test_model    transmit_test_rev   (\n   ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model.v\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model.sv\n             transmit_test_model\n             transmit_test_model.v\n             transmit_test_model.sv\n             obj_dir/transmit_test_model\n             obj_dir/transmit_test_model.v\n             obj_dir/transmit_test_model.sv\n%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/cmd_gen_submodule.v:102: Cannot find file containing module: 'Transmit'\n     Transmit   Transmit_rev  (\n     ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module   cmd_gen_submodule (



        input                  clk     ,

        input                  reset_n ,
 
                 


        
       output   [7:0]           Line_Num,

       output   [1:0]           Focus_Num,

       output                   Pr_Gate  ,

       output                   RX_Gate  ,

       output                  Sample_Gate,

       output                  Envelop   ,
 
       output                   End_Gate 


);


   





       wire    [7:0]            Line_Num_buf    ;

       wire    [1:0]            Focus_Num_buf   ;

       wire                     Pr_Gate_buf     ;

       wire                     RX_Gate_buf     ;

       wire                     Sample_Gate_buf ;
 
       wire                     End_Gate_buf    ; 

     
       wire                     Envelop_buf     ;









      
     












   transmit_test_model    transmit_test_rev   (
 

        
            .clk_100M      (clk),
         
            .reset_n       (reset_n) ,

            .Line_Num      (Line_Num_buf),

            .Focus_Num     (Focus_Num_buf),
       
            .Pr_Gate       (Pr_Gate_buf)  ,
     
            .RX_Gate       (RX_Gate_buf) ,
      
            .End_Gate      (End_Gate_buf),
      
            .Envelop       (Envelop_buf)  
   
    );




   

     Transmit   Transmit_rev  (
 


          .Transmit_CLK   (clk),
	  .Line_Num       (Line_Num_buf),
	  .Focus_Num      (Focus_Num_buf),
	  .Pr_Gate        (Pr_Gate_buf),
	  .RX_Gate        (RX_Gate_buf),


	  .Sample_Gate    (Sample_Gate_buf),
	  .P              (),
	  .N              (),
	
	  .HV_SW_CLR      (),
	  .HV_SW_LE       (),
	  .HV_SW_CLK      (),
	  .HV_SW_DOUT     (),
	
	 .AX              (),
	 .AY              (),
	 .MT_CS           (),
	 .MT_Strobe       (),
	 .MT_Data         ()



    );



   assign       Line_Num    =    Line_Num_buf  ;


    assign       Focus_Num   =   Focus_Num_buf  ;


    assign       Pr_Gate     =   Pr_Gate_buf    ;

    
    assign       RX_Gate     =   RX_Gate_buf   ;


    assign      End_Gate    =   End_Gate_buf   ;  


    assign      Sample_Gate =   Sample_Gate_buf;


    assign      Envelop     =   Envelop_buf   ; 


endmodule
module   cmd_gen_submodule (



        input                  clk     ,

        input                  reset_n ,
 
                 


        
       output   [7:0]           Line_Num,

       output   [1:0]           Focus_Num,

       output                   Pr_Gate  ,

       output                   RX_Gate  ,

       output                  Sample_Gate,

       output                  Envelop   ,
 
       output                   End_Gate 


);



   





       wire    [7:0]            Line_Num_buf    ;

       wire    [1:0]            Focus_Num_buf   ;

       wire                     Pr_Gate_buf     ;

       wire                     RX_Gate_buf     ;

       wire                     Sample_Gate_buf ;
 
       wire                     End_Gate_buf    ; 

     
       wire                     Envelop_buf     ;









      
     












   transmit_test_model    transmit_test_rev   (
 

        
            .clk_100M      (clk),
         
            .reset_n       (reset_n) ,

            .Line_Num      (Line_Num_buf),

            .Focus_Num     (Focus_Num_buf),
       
            .Pr_Gate       (Pr_Gate_buf)  ,
     
            .RX_Gate       (RX_Gate_buf) ,
      
            .End_Gate      (End_Gate_buf),
      
            .Envelop       (Envelop_buf)  
   
    );




   

     Transmit   Transmit_rev  (
 


          .Transmit_CLK   (clk),
	  .Line_Num       (Line_Num_buf),
	  .Focus_Num      (Focus_Num_buf),
	  .Pr_Gate        (Pr_Gate_buf),
	  .RX_Gate        (RX_Gate_buf),


	  .Sample_Gate    (Sample_Gate_buf),
	  .P              (),
	  .N              (),
	
	  .HV_SW_CLR      (),
	  .HV_SW_LE       (),
	  .HV_SW_CLK      (),
	  .HV_SW_DOUT     (),
	
	 .AX              (),
	 .AY              (),
	 .MT_CS           (),
	 .MT_Strobe       (),
	 .MT_Data         ()



    );



   assign       Line_Num    =    Line_Num_buf  ;


    assign       Focus_Num   =   Focus_Num_buf  ;


    assign       Pr_Gate     =   Pr_Gate_buf    ;

    
    assign       RX_Gate     =   RX_Gate_buf   ;


    assign      End_Gate    =   End_Gate_buf   ;  


    assign      Sample_Gate =   Sample_Gate_buf;


    assign      Envelop     =   Envelop_buf   ; 


endmodule