data/full_repos/permissive/516415799/fa.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/516415799/fa.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5;a=1\'b1; b=1\'b0; cin=1\'b0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516415799/fa.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5;a=1\'b0; b=1\'b1; cin=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/516415799/fa.v:20: Unsupported: Ignoring delay on this delayed statement.\n#5;a=1\'b1; b=1\'b1; cin=1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/516415799/fa.v:21: Unsupported: Ignoring delay on this delayed statement.\n#5 a=1\'b0; b=1\'b0; cin=1\'b1;\n^\n%Warning-IMPLICIT: data/full_repos/permissive/516415799/fa.v:4: Signal definition not found, creating implicitly: \'w0\'\nxor x1(w0,a,b);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/516415799/fa.v:5: Signal definition not found, creating implicitly: \'w1\'\n                                                              : ... Suggested alternative: \'w0\'\nand a1(w1,a,b);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/516415799/fa.v:6: Signal definition not found, creating implicitly: \'w2\'\n                                                              : ... Suggested alternative: \'w0\'\nxor x2(w2,w0,cin);\n       ^~\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
xor x1(w0,a,b);
and a1(w1,a,b);
xor x2(w2,w0,cin);
and a2(w2,w0,cin);
or o1(cout,w1,w2);
endmodule
module fa(sum,cout,a,b,cin);

input a,b,cin;
output sum,cout;
xor x1(w0,a,b);
and a1(w1,a,b);
xor x2(w2,w0,cin);
and a2(w2,w0,cin);
or o1(cout,w1,w2);
endmodule