data/full_repos/permissive/427221126/src/BasicArith.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/BasicArith.v:89: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'MAC\'\nmodule MAC\n       ^~~\n                                                                           : ... Top module \'ComplexMult\'\nmodule ComplexMult \n       ^~~~~~~~~~~\n                                                                           : ... Top module \'FMA\'\nmodule FMA\n       ^~~\n                                                                           : ... Top module \'Acc\'\nmodule Acc\n       ^~~\n                                                                           : ... Top module \'FMApFRound\'\nmodule FMApFRound\n       ^~~~~~~~~~\n                                                                           : ... Top module \'Max4\'\nmodule Max4\n       ^~~~\n                                                                           : ... Top module \'Add3\'\nmodule Add3(clk, reset, en, a, d, c, y);\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 24 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the LHS, but LHS\'s VARREF \'ain\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'din\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 96 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the LHS, but LHS\'s VARREF \'ain\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the RHS, but RHS\'s VARREF \'din\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:555: Output port connection \'Y\' expects 97 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 50 bits.\n                                                                         : ... In instance Add3\n  .Y(y)\n   ^\n%Error: data/full_repos/permissive/427221126/src/BasicArith.v:408: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.sv\n             FRound\n             FRound.v\n             FRound.sv\n             obj_dir/FRound\n             obj_dir/FRound.v\n             obj_dir/FRound.sv\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:291: Operator ASSIGNDLY expects 47 bits on the Assign RHS, but Assign RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= din_reg;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:293: Operator ADD expects 47 bits on the RHS, but RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= sum + din_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:225: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 29 bits.\n                                                                         : ... In instance FMA\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:76: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= mult;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:78: Operator ADD expects 42 bits on the RHS, but RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= sum + mult;\n                   ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module Max4
  #(
    parameter INWIDTH = 16
  )
  (
    input                       CLK,
    input                       RESET,
    input                       EN,
    input  signed [INWIDTH-1:0] DIN0,
    input  signed [INWIDTH-1:0] DIN1,
    input  signed [INWIDTH-1:0] DIN2,
    input  signed [INWIDTH-1:0] DIN3,
    output signed [INWIDTH-1:0] MAX
  );
  reg signed [INWIDTH-1:0] din [0:3];
  reg signed [INWIDTH-1:0] max01, max23, max;

  wire signed [INWIDTH-1:0] max01_w = (din[0] > din[1]) ? din[0] : din[1];
  wire signed [INWIDTH-1:0] max23_w = (din[2] > din[3]) ? din[2] : din[3];
  wire signed [INWIDTH-1:0] max4_w = (max01 > max23) ? max01 : max23;

  always @(posedge CLK)
    if (RESET) begin
      din[0] <= 0;
      din[1] <= 0;
      din[2] <= 0;
      din[3] <= 0;
    end else if (EN) begin
      din[0] <= DIN0;
      din[1] <= DIN1;
      din[2] <= DIN2;
      din[3] <= DIN3;
    end

  always @(posedge CLK) begin
    if (RESET) begin
      max01 <= 0;
      max23 <= 0;
    end else if (EN) begin
      max01 <= max01_w;
      max23 <= max23_w;
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      max <= 0;
    end else if (EN) begin
      max <= max4_w;
    end
  end

  assign MAX = max;
endmodule
module Max4
  #(
    parameter INWIDTH = 16
  )
  (
    input                       CLK,
    input                       RESET,
    input                       EN,
    input  signed [INWIDTH-1:0] DIN0,
    input  signed [INWIDTH-1:0] DIN1,
    input  signed [INWIDTH-1:0] DIN2,
    input  signed [INWIDTH-1:0] DIN3,
    output signed [INWIDTH-1:0] MAX
  );

  reg signed [INWIDTH-1:0] din [0:3];
  reg signed [INWIDTH-1:0] max01, max23, max;

  wire signed [INWIDTH-1:0] max01_w = (din[0] > din[1]) ? din[0] : din[1];
  wire signed [INWIDTH-1:0] max23_w = (din[2] > din[3]) ? din[2] : din[3];
  wire signed [INWIDTH-1:0] max4_w = (max01 > max23) ? max01 : max23;

  always @(posedge CLK)
    if (RESET) begin
      din[0] <= 0;
      din[1] <= 0;
      din[2] <= 0;
      din[3] <= 0;
    end else if (EN) begin
      din[0] <= DIN0;
      din[1] <= DIN1;
      din[2] <= DIN2;
      din[3] <= DIN3;
    end

  always @(posedge CLK) begin
    if (RESET) begin
      max01 <= 0;
      max23 <= 0;
    end else if (EN) begin
      max01 <= max01_w;
      max23 <= max23_w;
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      max <= 0;
    end else if (EN) begin
      max <= max4_w;
    end
  end

  assign MAX = max;
endmodule