data/full_repos/permissive/521867481/src/Uart8Receiver.v
1: b'%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:4: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:5: Cannot find include file: src/Uart8Receiver.v\n`include "src/Uart8Receiver.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:8: Define or directive not defined: \'`OVERSAMPLING_16\'\n        parameter OVERSAMPLING  = `OVERSAMPLING_16,  \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        parameter OVERSAMPLING  = `OVERSAMPLING_16,  \n                                                  ^\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:9: Define or directive not defined: \'`DATA_BITS_8\'\n        parameter DATA_BITS     = `DATA_BITS_8       \n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:10: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )(\n    ^\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire                   en,    \n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire                   in,    \n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output reg [DATA_BITS - 1:0] out,   \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n        output reg                   done,  \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n        output reg                   busy,  \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n        output reg                   err    \n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:20: Define or directive not defined: \'`STATE_RESET\'\n    reg [2:0] state        = `STATE_RESET;\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [2:0] state        = `STATE_RESET;\n                                         ^\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:30: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:41: Define or directive not defined: \'`STATE_RESET\'\n            state <= `STATE_RESET;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:45: Define or directive not defined: \'`STATE_RESET\'\n            `STATE_RESET: begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:54: Define or directive not defined: \'`STATE_IDLE\'\n                    state <= `STATE_IDLE;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:58: Define or directive not defined: \'`STATE_IDLE\'\n            `STATE_IDLE: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:67: Define or directive not defined: \'`STATE_DATA_BITS\'\n                    state <= `STATE_DATA_BITS;\n                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:72: Define or directive not defined: \'`STATE_RESET\'\n                        state <= `STATE_RESET;\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:79: Define or directive not defined: \'`STATE_DATA_BITS\'\n            `STATE_DATA_BITS: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:86: Define or directive not defined: \'`STATE_STOP_BIT\'\n                        state <= `STATE_STOP_BIT;\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:99: Define or directive not defined: \'`STATE_STOP_BIT\'\n            `STATE_STOP_BIT: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:101: Define or directive not defined: \'`STATE_IDLE\'\n                    state <= `STATE_IDLE;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:111: Define or directive not defined: \'`STATE_RESET\'\n                        state <= `STATE_RESET;\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8Receiver.v:117: Define or directive not defined: \'`STATE_IDLE\'\n                state <= `STATE_IDLE;\n                         ^~~~~~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module Uart8Receiver #(
        parameter OVERSAMPLING  = `OVERSAMPLING_16,
        parameter DATA_BITS     = `DATA_BITS_8
    )(
        input wire                   clk,
        input wire                   en,
        input wire                   in,
        output reg [DATA_BITS - 1:0] out,
        output reg                   done,
        output reg                   busy,
        output reg                   err
    );
    
    reg [2:0] state        = `STATE_RESET;
    reg [1:0] shiftReg     = 0;
    reg [7:0] receivedData = 0;

    localparam CLK_CNT_WIDTH   = $clog2(OVERSAMPLING);
    localparam DATA_BITS_WIDTH = $clog2(DATA_BITS);

    reg [CLK_CNT_WIDTH - 1:0]   clockCount = 0;
    reg [DATA_BITS_WIDTH - 1:0] bitIdx     = 0;

    initial begin
        out  <= 0;
        err  <= 0;
        done <= 0;
        busy <= 0;
    end

    always @ (posedge clk) begin
        shiftReg = { shiftReg[0], in };

        if (!en) begin
            state <= `STATE_RESET;
        end

        case (state)
            `STATE_RESET: begin
                out  <= 0;
                done <= 0;
                busy <= 0;
                err  <= 0;
                bitIdx       <= 0;
                clockCount   <= 0;
                receivedData <= 0;
                if (en) begin
                    state <= `STATE_IDLE;
                end
            end

            `STATE_IDLE: begin
                done <= 1'b0;
                if (&clockCount) begin
                    out  <= 8'b0;
                    busy <= 1'b1;
                    err  <= 1'b0;
                    bitIdx       <= 3'b0;
                    clockCount   <= 4'b0;
                    receivedData <= 8'b0;
                    state <= `STATE_DATA_BITS;
                end else if (!(&shiftReg) || |clockCount) begin

                    if (shiftReg == 2'b11) begin
                        err <= 1'b1;
                        state <= `STATE_RESET;
                    end
                    clockCount <= clockCount + 1;
                end
            end


            `STATE_DATA_BITS: begin
                if (&clockCount) begin
                    clockCount <= 4'b0;

                    receivedData[bitIdx] <= shiftReg[0];
                    if (&bitIdx) begin
                        bitIdx <= 3'b0;
                        state <= `STATE_STOP_BIT;
                    end else begin
                        bitIdx <= bitIdx + 3'b1;
                    end
                end else begin
                    clockCount <= clockCount + 4'b1;
                end
            end


            `STATE_STOP_BIT: begin
                if (&clockCount || (clockCount >= 4'h8 && !(|shiftReg))) begin
                    state <= `STATE_IDLE;
                    done <= 1'b1;
                    busy <= 1'b0;
                    out <= receivedData;
                    clockCount <= 4'b0;
                end else begin
                    clockCount <= clockCount + 1;

                    if (!(|shiftReg)) begin
                        err <= 1'b1;
                        state <= `STATE_RESET;
                    end
                end
            end

            default:
                state <= `STATE_IDLE;
        endcase
    end

endmodule
module Uart8Receiver #(
        parameter OVERSAMPLING  = `OVERSAMPLING_16,
        parameter DATA_BITS     = `DATA_BITS_8
    )(
        input wire                   clk,
        input wire                   en,
        input wire                   in,
        output reg [DATA_BITS - 1:0] out,
        output reg                   done,
        output reg                   busy,
        output reg                   err
    );

    
    reg [2:0] state        = `STATE_RESET;
    reg [1:0] shiftReg     = 0;
    reg [7:0] receivedData = 0;

    localparam CLK_CNT_WIDTH   = $clog2(OVERSAMPLING);
    localparam DATA_BITS_WIDTH = $clog2(DATA_BITS);

    reg [CLK_CNT_WIDTH - 1:0]   clockCount = 0;
    reg [DATA_BITS_WIDTH - 1:0] bitIdx     = 0;

    initial begin
        out  <= 0;
        err  <= 0;
        done <= 0;
        busy <= 0;
    end

    always @ (posedge clk) begin
        shiftReg = { shiftReg[0], in };

        if (!en) begin
            state <= `STATE_RESET;
        end

        case (state)
            `STATE_RESET: begin
                out  <= 0;
                done <= 0;
                busy <= 0;
                err  <= 0;
                bitIdx       <= 0;
                clockCount   <= 0;
                receivedData <= 0;
                if (en) begin
                    state <= `STATE_IDLE;
                end
            end

            `STATE_IDLE: begin
                done <= 1'b0;
                if (&clockCount) begin
                    out  <= 8'b0;
                    busy <= 1'b1;
                    err  <= 1'b0;
                    bitIdx       <= 3'b0;
                    clockCount   <= 4'b0;
                    receivedData <= 8'b0;
                    state <= `STATE_DATA_BITS;
                end else if (!(&shiftReg) || |clockCount) begin

                    if (shiftReg == 2'b11) begin
                        err <= 1'b1;
                        state <= `STATE_RESET;
                    end
                    clockCount <= clockCount + 1;
                end
            end


            `STATE_DATA_BITS: begin
                if (&clockCount) begin
                    clockCount <= 4'b0;

                    receivedData[bitIdx] <= shiftReg[0];
                    if (&bitIdx) begin
                        bitIdx <= 3'b0;
                        state <= `STATE_STOP_BIT;
                    end else begin
                        bitIdx <= bitIdx + 3'b1;
                    end
                end else begin
                    clockCount <= clockCount + 4'b1;
                end
            end


            `STATE_STOP_BIT: begin
                if (&clockCount || (clockCount >= 4'h8 && !(|shiftReg))) begin
                    state <= `STATE_IDLE;
                    done <= 1'b1;
                    busy <= 1'b0;
                    out <= receivedData;
                    clockCount <= 4'b0;
                end else begin
                    clockCount <= clockCount + 1;

                    if (!(|shiftReg)) begin
                        err <= 1'b1;
                        state <= `STATE_RESET;
                    end
                end
            end

            default:
                state <= `STATE_IDLE;
        endcase
    end

endmodule