data/full_repos/permissive/426029503/distance.v
1: b'%Error: data/full_repos/permissive/426029503/distance.v:4: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n  output reg[2:0]dist);\n                 ^~~~\n%Error: data/full_repos/permissive/426029503/distance.v:4: syntax error, unexpected \')\', expecting IDENTIFIER or do or final\n  output reg[2:0]dist);\n                     ^\n%Error: data/full_repos/permissive/426029503/distance.v:8: syntax error, unexpected always\n  always @(*) begin\n  ^~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:30: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 0;\n         ^~~~\n%Error: data/full_repos/permissive/426029503/distance.v:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 1;\n         ^~~~\n%Error: data/full_repos/permissive/426029503/distance.v:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 2;\n         ^~~~\n%Error: data/full_repos/permissive/426029503/distance.v:36: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:37: Value too large for 6 bit number: 100\n     6\'d000100:\n     ^~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/426029503/distance.v:38: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:40: Value too large for 6 bit number: 1000\n     6\'d001000:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:41: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 1;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:42: Value too large for 6 bit number: 1001\n     6\'d001001:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:43: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 1;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:44: Value too large for 6 bit number: 1010\n     6\'d001010:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:45: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 2;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:46: Value too large for 6 bit number: 1011\n     6\'d001011:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:47: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:48: Value too large for 6 bit number: 1100\n     6\'d001100:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:49: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:51: Value too large for 6 bit number: 10000\n     6\'d010000:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:52: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 2;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:53: Value too large for 6 bit number: 10001\n     6\'d010001:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:54: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 2;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:55: Value too large for 6 bit number: 10010\n     6\'d010010:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:57: Value too large for 6 bit number: 10011\n     6\'d010011:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:59: Value too large for 6 bit number: 10100\n     6\'d010100:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:62: Value too large for 6 bit number: 11000\n     6\'d011000:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:63: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:64: Value too large for 6 bit number: 11001\n     6\'d011001:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:66: Value too large for 6 bit number: 11010\n     6\'d011010:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:68: Value too large for 6 bit number: 11011\n     6\'d011011:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:69: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:70: Value too large for 6 bit number: 11100\n     6\'d011100:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:71: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 5;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:73: Value too large for 6 bit number: 100000\n     6\'d100000:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:74: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:75: Value too large for 6 bit number: 100001\n     6\'d100001:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:76: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:77: Value too large for 6 bit number: 100010\n     6\'d100010:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 4;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:79: Value too large for 6 bit number: 100011\n     6\'d100011:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 5;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/426029503/distance.v:81: Value too large for 6 bit number: 100100\n     6\'d100100:\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/426029503/distance.v:82: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n         dist = 6;\n         ^~~~\n%Error: Exiting due to 28 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module distance(
    input [3:0]diffX,
	 input [3:0]diffY,
	 output reg[2:0]dist);
	 
	 reg [3:0]xAbs, yAbs;
	 
	 always @(*) begin
	      case({diffX[3], diffY[3]}) 
			    2'b00: begin
				    xAbs = diffX;
					 yAbs = diffY;

				 end 2'b10: begin
				    xAbs = -diffX;
					 yAbs = diffY;
				 end 2'b01: begin
				    xAbs = diffX;
					 yAbs = -diffY;
				 end 2'b11: begin
				    xAbs = -diffX;
					 yAbs = -diffY;
				 end
			endcase
    end
	 always @(*) begin
	     case({yAbs, xAbs}) 

		       6'd000000:
				     dist = 0;
				 6'd000001:
				     dist = 1;
				 6'd000010:
				     dist = 2;
				 6'd000011:
				     dist = 3;
				 6'd000100:
				     dist = 4;

				 6'd001000:
				     dist = 1;
				 6'd001001:
				     dist = 1;
				 6'd001010:
				     dist = 2;
				 6'd001011:
				     dist = 3;
				 6'd001100:
				     dist = 4;

				 6'd010000:
				     dist = 2;
				 6'd010001:
				     dist = 2;
				 6'd010010:
				     dist = 3;
				 6'd010011:
				     dist = 4;
				 6'd010100:
				     dist = 4;

				 6'd011000:
				     dist = 3;
				 6'd011001:
				     dist = 3;
				 6'd011010:
				     dist = 4;
				 6'd011011:
				     dist = 4;
				 6'd011100:
				     dist = 5;

				 6'd100000:
				     dist = 4;
				 6'd100001:
				     dist = 4;
				 6'd100010:
				     dist = 4;
				 6'd100011:
				     dist = 5;
				 6'd100100:
				     dist = 6;
			endcase
	end
endmodule
module distance(
    input [3:0]diffX,
	 input [3:0]diffY,
	 output reg[2:0]dist);

	 
	 reg [3:0]xAbs, yAbs;
	 
	 always @(*) begin
	      case({diffX[3], diffY[3]}) 
			    2'b00: begin
				    xAbs = diffX;
					 yAbs = diffY;

				 end 2'b10: begin
				    xAbs = -diffX;
					 yAbs = diffY;
				 end 2'b01: begin
				    xAbs = diffX;
					 yAbs = -diffY;
				 end 2'b11: begin
				    xAbs = -diffX;
					 yAbs = -diffY;
				 end
			endcase
    end
	 always @(*) begin
	     case({yAbs, xAbs}) 

		       6'd000000:
				     dist = 0;
				 6'd000001:
				     dist = 1;
				 6'd000010:
				     dist = 2;
				 6'd000011:
				     dist = 3;
				 6'd000100:
				     dist = 4;

				 6'd001000:
				     dist = 1;
				 6'd001001:
				     dist = 1;
				 6'd001010:
				     dist = 2;
				 6'd001011:
				     dist = 3;
				 6'd001100:
				     dist = 4;

				 6'd010000:
				     dist = 2;
				 6'd010001:
				     dist = 2;
				 6'd010010:
				     dist = 3;
				 6'd010011:
				     dist = 4;
				 6'd010100:
				     dist = 4;

				 6'd011000:
				     dist = 3;
				 6'd011001:
				     dist = 3;
				 6'd011010:
				     dist = 4;
				 6'd011011:
				     dist = 4;
				 6'd011100:
				     dist = 5;

				 6'd100000:
				     dist = 4;
				 6'd100001:
				     dist = 4;
				 6'd100010:
				     dist = 4;
				 6'd100011:
				     dist = 5;
				 6'd100100:
				     dist = 6;
			endcase
	end
endmodule