data/full_repos/permissive/411838135/rv/test.sv
1: b'%Error: data/full_repos/permissive/411838135/rv/test.sv:37: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/test.sv:59: Unsupported or unknown PLI call: $fopenr\n   file = $fopenr("x.bin");\n          ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/test.sv:77: Unsupported or unknown PLI call: $fopenr\n   file = $fopenr("x.bin");\n          ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/test.sv:91: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/test.sv:93: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/test.sv:94: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/test.sv:97: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk=1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/test.sv:98: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk=0;\n   ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

	integer count;
	reg clk, reset;
	integer file, res;
	integer i;
	reg	  quit;
	parameter NCPU = 1;

	reg [31:0]gpio;
	reg [31:0]block_addr_0 = 0;
	reg [31:0]block_count_0 = 0;
	reg [31:0]block_addr_1 = 0;
	reg [31:0]block_count_1 = 0;

	initial begin 
		gpio= 0;
		$dumpvars;
		count=0;
		reset = 1;
		clk = 1;
`ifdef NOTDEF
		file = $fopenr("x.bin");
		res = $fread(chip.c[0].cpu.ic.icache, file);
		$fclose(file);
		for (res = 0;res < 65536;res=res+1) begin :rr
			reg [127:0]t;

			t = chip.c[0].cpu.ic.icache[res];
			t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56],t[71:64],t[79:72],t[87:80], t[95:88],t[103:96],t[111:104],t[119:112], t[127:120]};
			chip.c[0].cpu.ic.icache[res] = t;
		end
`endif

		block_addr_0 = 0;
		block_count_0 = 0;
		block_addr_1 = 0;
		block_count_1 = 0;
		if ($test$plusargs ("b")) begin
			file = $fopenr("x.bin");
			quit = 0;
			for (i = 0;!quit;i=i+1) begin :rcx
				reg [63:0]t;

				res = $fread(t, file);
				if (res > 0) begin
					t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56]};
                                	chip.io_switch.sd.disk[i] = t;
				end else begin
					quit = 1;
				end
			end
			$fclose(file);
			gpio = 1;
			block_addr_0 = 0;
			block_count_0 = ((i>>5)+1);
		end else begin
			file = $fopenr("x.bin");
			res = $fread(chip.mem.mem, file);
			$fclose(file);
			for (res = 0;res < 65536;res=res+1) begin :rc
				reg [511:0]t;
	
				t = chip.mem.mem[res];
				t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56],t[71:64],t[79:72],t[87:80], t[95:88],t[103:96],t[111:104],t[119:112], t[127:120],
			     	t[135:128],t[143:136],t[151:144],t[159:152],t[167:160],t[175:168],t[183:176], t[191:184],t[199:192],t[207:200],t[215:208], t[223:216],t[231:224],t[239:232],t[247:240], t[255:248],
			     	t[263:256],t[271:264],t[279:272],t[287:280],t[295:288],t[303:296],t[311:304], t[319:312],t[327:320],t[335:328],t[343:336], t[351:344],t[359:352],t[367:360],t[375:368], t[383:376],
			     	t[391:384],t[399:392],t[407:400],t[415:408],t[423:416],t[431:424],t[439:432], t[447:440],t[455:448],t[463:456],t[471:464], t[479:472],t[487:480],t[495:488],t[503:496], t[511:504]};
				chip.mem.mem[res] = t;
			end
		end
		#5 clk=0;
		reset = 1;
		#10 clk=1;
		#5 clk=0;
		reset = 0;
		forever begin
			#5 clk=1;
			#5 clk=0;

		end
	end

	integer limit;
	initial begin
		if (!$value$plusargs("l=%d", limit)) 
			limit = 10000;
	end
	
	always @(posedge clk)
	if (!reset) begin
		count = count+1;




		if (count > limit)
			$finish;
	end

	wire [31:0]gpio_pads = gpio;
	wire	reset_out;

	chip #(.NCPU(NCPU))chip(.clk_in(clk), .ireset(reset),
		.reset_out(reset_out),
		.reset_out_ack(reset_out),
`ifdef SIMD
		.simd_enable(1'b1),
`endif
		.uart_rx(1'b0),
		.uart_cts(1'b0),
		.cpu_id(5'd0),
		.block_count_0(block_count_0),
		.block_addr_0(block_addr_0),
		.block_count_1(block_count_1),
		.block_addr_1(block_addr_1),
		.gpio_pads(gpio_pads));

endmodule
module test;


	integer count;
	reg clk, reset;
	integer file, res;
	integer i;
	reg	  quit;
	parameter NCPU = 1;

	reg [31:0]gpio;
	reg [31:0]block_addr_0 = 0;
	reg [31:0]block_count_0 = 0;
	reg [31:0]block_addr_1 = 0;
	reg [31:0]block_count_1 = 0;

	initial begin 
		gpio= 0;
		$dumpvars;
		count=0;
		reset = 1;
		clk = 1;
`ifdef NOTDEF
		file = $fopenr("x.bin");
		res = $fread(chip.c[0].cpu.ic.icache, file);
		$fclose(file);
		for (res = 0;res < 65536;res=res+1) begin :rr
			reg [127:0]t;

			t = chip.c[0].cpu.ic.icache[res];
			t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56],t[71:64],t[79:72],t[87:80], t[95:88],t[103:96],t[111:104],t[119:112], t[127:120]};
			chip.c[0].cpu.ic.icache[res] = t;
		end
`endif

		block_addr_0 = 0;
		block_count_0 = 0;
		block_addr_1 = 0;
		block_count_1 = 0;
		if ($test$plusargs ("b")) begin
			file = $fopenr("x.bin");
			quit = 0;
			for (i = 0;!quit;i=i+1) begin :rcx
				reg [63:0]t;

				res = $fread(t, file);
				if (res > 0) begin
					t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56]};
                                	chip.io_switch.sd.disk[i] = t;
				end else begin
					quit = 1;
				end
			end
			$fclose(file);
			gpio = 1;
			block_addr_0 = 0;
			block_count_0 = ((i>>5)+1);
		end else begin
			file = $fopenr("x.bin");
			res = $fread(chip.mem.mem, file);
			$fclose(file);
			for (res = 0;res < 65536;res=res+1) begin :rc
				reg [511:0]t;
	
				t = chip.mem.mem[res];
				t = {t[7:0],t[15:8],t[23:16],t[31:24],t[39:32],t[47:40],t[55:48], t[63:56],t[71:64],t[79:72],t[87:80], t[95:88],t[103:96],t[111:104],t[119:112], t[127:120],
			     	t[135:128],t[143:136],t[151:144],t[159:152],t[167:160],t[175:168],t[183:176], t[191:184],t[199:192],t[207:200],t[215:208], t[223:216],t[231:224],t[239:232],t[247:240], t[255:248],
			     	t[263:256],t[271:264],t[279:272],t[287:280],t[295:288],t[303:296],t[311:304], t[319:312],t[327:320],t[335:328],t[343:336], t[351:344],t[359:352],t[367:360],t[375:368], t[383:376],
			     	t[391:384],t[399:392],t[407:400],t[415:408],t[423:416],t[431:424],t[439:432], t[447:440],t[455:448],t[463:456],t[471:464], t[479:472],t[487:480],t[495:488],t[503:496], t[511:504]};
				chip.mem.mem[res] = t;
			end
		end
		#5 clk=0;
		reset = 1;
		#10 clk=1;
		#5 clk=0;
		reset = 0;
		forever begin
			#5 clk=1;
			#5 clk=0;

		end
	end

	integer limit;
	initial begin
		if (!$value$plusargs("l=%d", limit)) 
			limit = 10000;
	end
	
	always @(posedge clk)
	if (!reset) begin
		count = count+1;




		if (count > limit)
			$finish;
	end

	wire [31:0]gpio_pads = gpio;
	wire	reset_out;

	chip #(.NCPU(NCPU))chip(.clk_in(clk), .ireset(reset),
		.reset_out(reset_out),
		.reset_out_ack(reset_out),
`ifdef SIMD
		.simd_enable(1'b1),
`endif
		.uart_rx(1'b0),
		.uart_cts(1'b0),
		.cpu_id(5'd0),
		.block_count_0(block_count_0),
		.block_addr_0(block_addr_0),
		.block_count_1(block_count_1),
		.block_addr_1(block_addr_1),
		.gpio_pads(gpio_pads));

endmodule