data/full_repos/permissive/488739248/rtl/ym3526/jtopl_pg_inc.v
data/verilator_xmls/51b13b5f-2b41-45b1-a1c9-48cca4e8bf13.xml
module jtopl_pg_inc (
    input  wire       [ 2:0] block,
    input  wire       [ 9:0] fnum,
    input  wire signed [ 3:0] pm_offset,
    output reg   [16:0] phinc_pure
);

reg [16:0] freq;

always @(*) begin 
    freq       = { 7'd0, fnum } + { {13{pm_offset[3]}}, pm_offset };

    freq       = freq << block;
    phinc_pure = freq >> 1;
end

endmodule
module jtopl_pg_inc (
    input  wire       [ 2:0] block,
    input  wire       [ 9:0] fnum,
    input  wire signed [ 3:0] pm_offset,
    output reg   [16:0] phinc_pure
);


reg [16:0] freq;

always @(*) begin 
    freq       = { 7'd0, fnum } + { {13{pm_offset[3]}}, pm_offset };

    freq       = freq << block;
    phinc_pure = freq >> 1;
end

endmodule