data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/Equals.v
data/verilator_xmls/f6d1371e-29a5-4718-9172-85ee5a86a14c.xml
module Equals(
    input [31:0] First,
    input [31:0] Second,
    output reg EqualD
    );
    
    always@(*) begin
        if (First == Second) begin
            EqualD <= 1'b1;
        end
        else begin
            EqualD <= 1'b0;
        end
    end
endmodule
module Equals(
    input [31:0] First,
    input [31:0] Second,
    output reg EqualD
    );

    
    always@(*) begin
        if (First == Second) begin
            EqualD <= 1'b1;
        end
        else begin
            EqualD <= 1'b0;
        end
    end
endmodule