data/full_repos/permissive/431474762/WB.v
1: b'%Error: data/full_repos/permissive/431474762/WB.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.v\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/431474762/WB.v:6: Define or directive not defined: \'`StallBus\'\n    input wire [`StallBus-1:0] stall,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:8: Define or directive not defined: \'`MEM_TO_WB_WD\'\n    input wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:10: Define or directive not defined: \'`WB_TO_RF_WD\'\n    output wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:17: Define or directive not defined: \'`MEM_TO_WB_WD\'\n    reg [`MEM_TO_WB_WD-1:0] mem_to_wb_bus_r;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:20: Define or directive not defined: \'`MEM_TO_WB_WD\'\n            mem_to_wb_bus_r <= `MEM_TO_WB_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:25: Define or directive not defined: \'`Stop\'\n        else if (stall[4]==`Stop && stall[5]==`NoStop) begin\n                           ^~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:25: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        else if (stall[4]==`Stop && stall[5]==`NoStop) begin\n                                 ^~\n%Error: data/full_repos/permissive/431474762/WB.v:25: Define or directive not defined: \'`NoStop\'\n        else if (stall[4]==`Stop && stall[5]==`NoStop) begin\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:26: Define or directive not defined: \'`MEM_TO_WB_WD\'\n            mem_to_wb_bus_r <= `MEM_TO_WB_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/WB.v:28: Define or directive not defined: \'`NoStop\'\n        else if (stall[4]==`NoStop) begin\n                           ^~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module WB(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,

    input wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,

    output wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus,
    output wire [31:0] debug_wb_pc,
    output wire [3:0] debug_wb_rf_wen,
    output wire [4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata 
);

    reg [`MEM_TO_WB_WD-1:0] mem_to_wb_bus_r;
    always @ (posedge clk) begin
        if (rst) begin
            mem_to_wb_bus_r <= `MEM_TO_WB_WD'b0;
        end



        else if (stall[4]==`Stop && stall[5]==`NoStop) begin
            mem_to_wb_bus_r <= `MEM_TO_WB_WD'b0;
        end
        else if (stall[4]==`NoStop) begin
            mem_to_wb_bus_r <= mem_to_wb_bus;
        end
    end

    wire [31:0] wb_pc;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire hl_we;
    wire [1:0]hl_waddr;
    wire [63:0] hl_wdata;
    assign {
        hl_wdata,
        hl_waddr,
        hl_we,
        wb_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    } = mem_to_wb_bus_r;



    assign wb_to_rf_bus = {
        hl_wdata,
        hl_waddr,
        hl_we,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    
    assign debug_wb_pc = wb_pc;
    assign debug_wb_rf_wen = {4{rf_we}};
    assign debug_wb_rf_wnum = rf_waddr;
    assign debug_wb_rf_wdata = rf_wdata;
    
    
endmodule
module WB(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,

    input wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,

    output wire [`WB_TO_RF_WD-1:0] wb_to_rf_bus,
    output wire [31:0] debug_wb_pc,
    output wire [3:0] debug_wb_rf_wen,
    output wire [4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata 
);


    reg [`MEM_TO_WB_WD-1:0] mem_to_wb_bus_r;
    always @ (posedge clk) begin
        if (rst) begin
            mem_to_wb_bus_r <= `MEM_TO_WB_WD'b0;
        end



        else if (stall[4]==`Stop && stall[5]==`NoStop) begin
            mem_to_wb_bus_r <= `MEM_TO_WB_WD'b0;
        end
        else if (stall[4]==`NoStop) begin
            mem_to_wb_bus_r <= mem_to_wb_bus;
        end
    end

    wire [31:0] wb_pc;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire hl_we;
    wire [1:0]hl_waddr;
    wire [63:0] hl_wdata;
    assign {
        hl_wdata,
        hl_waddr,
        hl_we,
        wb_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    } = mem_to_wb_bus_r;



    assign wb_to_rf_bus = {
        hl_wdata,
        hl_waddr,
        hl_we,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    
    assign debug_wb_pc = wb_pc;
    assign debug_wb_rf_wen = {4{rf_we}};
    assign debug_wb_rf_wnum = rf_waddr;
    assign debug_wb_rf_wdata = rf_wdata;
    
    
endmodule