data/full_repos/permissive/500345502/verilog/rtl/snn-accelerator/properties/src/out_neuron.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500345502/verilog/rtl/snn-accelerator/properties/src/out_neuron.v:43: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                               : ... In instance out_neuron.num_ones0\n            ones = ones + A[i];  \n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module num_ones (
    input [127:0] A,
    output reg [7:0] ones
    );

    integer i;

    always@(A)
    begin
        ones = 0;
        for(i=0;i<128;i=i+1)
            ones = ones + A[i];
    end

endmodule
module num_ones (
    input [127:0] A,
    output reg [7:0] ones
    );


    integer i;

    always@(A)
    begin
        ones = 0;
        for(i=0;i<128;i=i+1)
            ones = ones + A[i];
    end

endmodule