data/full_repos/permissive/472097485/Chu03/Barrel_01c/RorL.v
data/verilator_xmls/5946d3c6-b7f8-4ea4-b6ea-568bcc7435cc.xml
module RorL( input [7:0] a, input rr, output reg [7:0] r );

	always @*
	begin
		if ( rr )
			begin
			r = { a[0], a[7:1] };
			end
		else
			begin
			r = { a[6:0], a[7] };
			end
	end

endmodule
module RorL( input [7:0] a, input rr, output reg [7:0] r );


	always @*
	begin
		if ( rr )
			begin
			r = { a[0], a[7:1] };
			end
		else
			begin
			r = { a[6:0], a[7] };
			end
	end

endmodule