data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v
1: b"%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:13: Define or directive not defined: '`CORES'\n   input [`CORES*`PC_WIDTH-1:0] raddr,\n          ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:13: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n   input [`CORES*`PC_WIDTH-1:0] raddr,\n                ^\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:13: Define or directive not defined: '`PC_WIDTH'\n   input [`CORES*`PC_WIDTH-1:0] raddr,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:14: Define or directive not defined: '`CORES'\n   output [`CORES*`INSTR_WIDTH-1:0] rdata,\n           ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:14: Define or directive not defined: '`INSTR_WIDTH'\n   output [`CORES*`INSTR_WIDTH-1:0] rdata,\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:15: Define or directive not defined: '`CORES'\n   input [`CORES-1:0] we,\n          ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:16: Define or directive not defined: '`CORES'\n   input [`CORES*`PC_WIDTH-1:0] waddr,\n          ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:16: Define or directive not defined: '`PC_WIDTH'\n   input [`CORES*`PC_WIDTH-1:0] waddr,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:17: Define or directive not defined: '`CORES'\n   input [`CORES*`INSTR_WIDTH-1:0] wdata\n          ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:17: Define or directive not defined: '`INSTR_WIDTH'\n   input [`CORES*`INSTR_WIDTH-1:0] wdata\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:20: Define or directive not defined: '`LOG_CORES'\nlocalparam CORES_RNDUP = 1 << `LOG_CORES;\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:20: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\nlocalparam CORES_RNDUP = 1 << `LOG_CORES;\n                                        ^\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:23: Define or directive not defined: '`CORES'\nfor(core=0; core<`CORES; core=core+1) begin:g_core\n                 ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:30: Define or directive not defined: '`INSTR_DEPTH'\n   localparam DEPTH = `INSTR_DEPTH * DEPTH_MULT;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:30: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n   localparam DEPTH = `INSTR_DEPTH * DEPTH_MULT;\n                                   ^\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:32: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:32: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:32: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                                      ^~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:32: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:34: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:34: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:34: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                                      ^~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:34: Define or directive not defined: '`PC_WIDTH'\n   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];\n                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:35: Define or directive not defined: '`INSTR_WIDTH'\n   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:35: Define or directive not defined: '`INSTR_WIDTH'\n   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:35: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];\n                                                            ^~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:35: Define or directive not defined: '`INSTR_WIDTH'\n   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];\n                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:37: Define or directive not defined: '`INSTR_WIDTH'\n   reg [`INSTR_WIDTH-1:0] mem[DEPTH-1:0];\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:39: Define or directive not defined: '`INSTR_WIDTH'\n   wire [`INSTR_WIDTH-1:0] crdata = mem[craddr];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:40: syntax error, unexpected assign\n   assign rdata[core*`INSTR_WIDTH +: `INSTR_WIDTH] = crdata;\n   ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:40: Define or directive not defined: '`INSTR_WIDTH'\n   assign rdata[core*`INSTR_WIDTH +: `INSTR_WIDTH] = crdata;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:40: Define or directive not defined: '`INSTR_WIDTH'\n   assign rdata[core*`INSTR_WIDTH +: `INSTR_WIDTH] = crdata;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:43: syntax error, unexpected always\n   always @ (posedge clk) begin\n   ^~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/instr_mem.v:46: Define or directive not defined: '`INSTR_WIDTH'\n            mem[i] <= {(`INSTR_WIDTH){1'b0}};\n                        ^~~~~~~~~~~~\n%Error: Exiting due to 34 error(s)\n"
module instr_mem (
   input clk,
   input rst_n,
   input [`CORES*`PC_WIDTH-1:0] raddr,
   output [`CORES*`INSTR_WIDTH-1:0] rdata,
   input [`CORES-1:0] we,
   input [`CORES*`PC_WIDTH-1:0] waddr,
   input [`CORES*`INSTR_WIDTH-1:0] wdata
);

localparam CORES_RNDUP = 1 << `LOG_CORES;

generate genvar core;
for(core=0; core<`CORES; core=core+1) begin:g_core

   localparam DEPTH_MULT = (core + CORES_RNDUP) & ~(core + CORES_RNDUP-1);



   
   localparam DEPTH = `INSTR_DEPTH * DEPTH_MULT;

   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];
   wire cwe = we[core];
   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];
   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];

   reg [`INSTR_WIDTH-1:0] mem[DEPTH-1:0];

   wire [`INSTR_WIDTH-1:0] crdata = mem[craddr];
   assign rdata[core*`INSTR_WIDTH +: `INSTR_WIDTH] = crdata;

   integer i;
   always @ (posedge clk) begin
      if (!rst_n) begin
         for (i=0; i<DEPTH; i=i+1) begin
            mem[i] <= {(`INSTR_WIDTH){1'b0}};
         end
      end else begin
         if (cwe) mem[cwaddr] <= cwdata;
      end
   end

end
endgenerate

endmodule
module instr_mem (
   input clk,
   input rst_n,
   input [`CORES*`PC_WIDTH-1:0] raddr,
   output [`CORES*`INSTR_WIDTH-1:0] rdata,
   input [`CORES-1:0] we,
   input [`CORES*`PC_WIDTH-1:0] waddr,
   input [`CORES*`INSTR_WIDTH-1:0] wdata
);


localparam CORES_RNDUP = 1 << `LOG_CORES;

generate genvar core;
for(core=0; core<`CORES; core=core+1) begin:g_core

   localparam DEPTH_MULT = (core + CORES_RNDUP) & ~(core + CORES_RNDUP-1);



   
   localparam DEPTH = `INSTR_DEPTH * DEPTH_MULT;

   wire [`PC_WIDTH-1:0] craddr = raddr[core*`PC_WIDTH +: `PC_WIDTH];
   wire cwe = we[core];
   wire [`PC_WIDTH-1:0] cwaddr = waddr[core*`PC_WIDTH +: `PC_WIDTH];
   wire [`INSTR_WIDTH-1:0] cwdata = wdata[core*`INSTR_WIDTH +: `INSTR_WIDTH];

   reg [`INSTR_WIDTH-1:0] mem[DEPTH-1:0];

   wire [`INSTR_WIDTH-1:0] crdata = mem[craddr];
   assign rdata[core*`INSTR_WIDTH +: `INSTR_WIDTH] = crdata;

   integer i;
   always @ (posedge clk) begin
      if (!rst_n) begin
         for (i=0; i<DEPTH; i=i+1) begin
            mem[i] <= {(`INSTR_WIDTH){1'b0}};
         end
      end else begin
         if (cwe) mem[cwaddr] <= cwdata;
      end
   end

end
endgenerate

endmodule