data/full_repos/permissive/487110065/PC.v
data/verilator_xmls/2343861b-9fd8-4c39-bd3a-e3e2b3f645d3.xml
module PC (
    clock,
    jump,
    reseta,
    endereco,
    saida,
    halt
);

input halt;
input clock;
input jump;
input reseta;
input [31:0] endereco;

output reg [31:0] saida;
initial begin
    saida <= 32'b0;
end

always @(posedge clock) begin
    if (reseta) begin
        saida <= 32'b0;
    end else if (jump == 1) begin
        saida <= endereco;
    end else if (halt == 1) begin
        saida <= saida;
    end else begin
        saida <= saida + 1;
    end
end

endmodule
module PC (
    clock,
    jump,
    reseta,
    endereco,
    saida,
    halt
);


input halt;
input clock;
input jump;
input reseta;
input [31:0] endereco;

output reg [31:0] saida;
initial begin
    saida <= 32'b0;
end

always @(posedge clock) begin
    if (reseta) begin
        saida <= 32'b0;
    end else if (jump == 1) begin
        saida <= endereco;
    end else if (halt == 1) begin
        saida <= saida;
    end else begin
        saida <= saida + 1;
    end
end

endmodule