data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_mdio_wrap.v
1: b"%Error: data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog/ethernet_mdio_wrap.v:145: Cannot find file containing module: 'mdio_master'\nmdio_master mdio_master_inst (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/mdio_master\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/mdio_master.v\n             data/full_repos/permissive/463204869/units/ethernet/source/rtl/verilog,data/full_repos/permissive/463204869/mdio_master.sv\n             mdio_master\n             mdio_master.v\n             mdio_master.sv\n             obj_dir/mdio_master\n             obj_dir/mdio_master.v\n             obj_dir/mdio_master.sv\n%Error: Exiting due to 1 error(s)\n"
module ethernet_mdio_wrap #(
    parameter SIMULATION = 0
)
(
    input  wire               clk_eth_i,
    input  wire               rst_eth_n_i,

    output wire               mdio_mdc,
    input  wire               mdio_mdio_i,
    output wire               mdio_mdio_o,
    output wire               mdio_mdio_t
);


reg [19:0] delay_reg = SIMULATION ? 20'h1a00 : 20'hfffff;

reg [4:0] mdio_cmd_phy_addr = 5'h03;
reg [4:0] mdio_cmd_reg_addr = 5'h00;
reg [15:0] mdio_cmd_data = 16'd0;
reg [1:0] mdio_cmd_opcode = 2'b01;
reg mdio_cmd_valid = 1'b0;
wire mdio_cmd_ready;

reg [3:0] state_reg = 0;


always @(posedge clk_eth_i) begin
    if (rst_eth_n_i == 1'b0) begin
        state_reg <= 0;
        delay_reg <= SIMULATION ? 20'h1a00 : 20'hfffff;
        mdio_cmd_reg_addr <= 5'h00;
        mdio_cmd_data <= 16'd0;
        mdio_cmd_valid <= 1'b0;
    end else begin
        mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready;
        if (delay_reg > 0) begin
            delay_reg <= delay_reg - 1;
        end else if (!mdio_cmd_ready) begin

            state_reg <= state_reg;
        end else begin
            mdio_cmd_valid <= 1'b0;
            case (state_reg)


                4'd0: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd1;
                end
                4'd1: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0031;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd2;
                end
                4'd2: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd3;
                end
                4'd3: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0070;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd4;
                end


                4'd4: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd5;
                end
                4'd5: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h00D3;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd6;
                end
                4'd6: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd7;
                end
                4'd7: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h4000;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd8;
                end


                4'd8: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd9;
                end
                4'd9: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h016F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd10;
                end
                4'd10: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd11;
                end
                4'd11: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0015;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd12;
                end
                4'd12: begin

                    state_reg <= 4'd12;
                end
            endcase
        end
    end
end


mdio_master mdio_master_inst (
    .clk            (clk_eth_i),
    .rst            (~rst_eth_n_i),

    .cmd_phy_addr   (mdio_cmd_phy_addr),
    .cmd_reg_addr   (mdio_cmd_reg_addr),
    .cmd_data       (mdio_cmd_data),
    .cmd_opcode     (mdio_cmd_opcode),
    .cmd_valid      (mdio_cmd_valid),
    .cmd_ready      (mdio_cmd_ready),

    .data_out       (),
    .data_out_valid (),
    .data_out_ready (1'b1),

    .mdc_o          (mdio_mdc),
    .mdio_i         (mdio_mdio_i),
    .mdio_o         (mdio_mdio_o),
    .mdio_t         (mdio_mdio_t),

    .busy           (),

    .prescale       (8'd3)
);



endmodule
module ethernet_mdio_wrap #(
    parameter SIMULATION = 0
)
(
    input  wire               clk_eth_i,
    input  wire               rst_eth_n_i,

    output wire               mdio_mdc,
    input  wire               mdio_mdio_i,
    output wire               mdio_mdio_o,
    output wire               mdio_mdio_t
);



reg [19:0] delay_reg = SIMULATION ? 20'h1a00 : 20'hfffff;

reg [4:0] mdio_cmd_phy_addr = 5'h03;
reg [4:0] mdio_cmd_reg_addr = 5'h00;
reg [15:0] mdio_cmd_data = 16'd0;
reg [1:0] mdio_cmd_opcode = 2'b01;
reg mdio_cmd_valid = 1'b0;
wire mdio_cmd_ready;

reg [3:0] state_reg = 0;


always @(posedge clk_eth_i) begin
    if (rst_eth_n_i == 1'b0) begin
        state_reg <= 0;
        delay_reg <= SIMULATION ? 20'h1a00 : 20'hfffff;
        mdio_cmd_reg_addr <= 5'h00;
        mdio_cmd_data <= 16'd0;
        mdio_cmd_valid <= 1'b0;
    end else begin
        mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready;
        if (delay_reg > 0) begin
            delay_reg <= delay_reg - 1;
        end else if (!mdio_cmd_ready) begin

            state_reg <= state_reg;
        end else begin
            mdio_cmd_valid <= 1'b0;
            case (state_reg)


                4'd0: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd1;
                end
                4'd1: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0031;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd2;
                end
                4'd2: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd3;
                end
                4'd3: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0070;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd4;
                end


                4'd4: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd5;
                end
                4'd5: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h00D3;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd6;
                end
                4'd6: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd7;
                end
                4'd7: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h4000;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd8;
                end


                4'd8: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h001F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd9;
                end
                4'd9: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h016F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd10;
                end
                4'd10: begin

                    mdio_cmd_reg_addr <= 5'h0D;
                    mdio_cmd_data <= 16'h401F;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd11;
                end
                4'd11: begin

                    mdio_cmd_reg_addr <= 5'h0E;
                    mdio_cmd_data <= 16'h0015;
                    mdio_cmd_valid <= 1'b1;
                    state_reg <= 4'd12;
                end
                4'd12: begin

                    state_reg <= 4'd12;
                end
            endcase
        end
    end
end


mdio_master mdio_master_inst (
    .clk            (clk_eth_i),
    .rst            (~rst_eth_n_i),

    .cmd_phy_addr   (mdio_cmd_phy_addr),
    .cmd_reg_addr   (mdio_cmd_reg_addr),
    .cmd_data       (mdio_cmd_data),
    .cmd_opcode     (mdio_cmd_opcode),
    .cmd_valid      (mdio_cmd_valid),
    .cmd_ready      (mdio_cmd_ready),

    .data_out       (),
    .data_out_valid (),
    .data_out_ready (1'b1),

    .mdc_o          (mdio_mdc),
    .mdio_i         (mdio_mdio_i),
    .mdio_o         (mdio_mdio_o),
    .mdio_t         (mdio_mdio_t),

    .busy           (),

    .prescale       (8'd3)
);



endmodule