data/full_repos/permissive/433621701/generic_CB_array/generic_CB_array.v
data/verilator_xmls/fd06e278-bb93-4e8c-8afc-57a7fd90af91.xml
module FACB_four_input(input a_old, a_new, b_old, b_new, enable, carry_in, output carry_out, sum);
    wire FA_in0, FA_in1, FA_out, tri_in0, tri_in1;
    two_in_and_gate and0(.a(a_old), .b(b_new), .z(tri_in0));
    two_in_and_gate and1(.a(a_new), .b(b_old), .z(tri_in1));
    tri_state tri_0(.a(tri_in0), .enable(enable), .out(FA_in0));
    tri_state tri_1(.a(tri_in1), .enable(enable), .out(FA_in1));
    Full_Adder FA(.a(FA_in0), .b(FA_in1), .carry_in(carry_in), .sum(FA_out), .carry_out(carry_out));
    mux mux0(.a(tri_in1), .b(FA_out), .select(enable), .out(sum));
endmodule
module FACB_four_input(input a_old, a_new, b_old, b_new, enable, carry_in, output carry_out, sum);

    wire FA_in0, FA_in1, FA_out, tri_in0, tri_in1;
    two_in_and_gate and0(.a(a_old), .b(b_new), .z(tri_in0));
    two_in_and_gate and1(.a(a_new), .b(b_old), .z(tri_in1));
    tri_state tri_0(.a(tri_in0), .enable(enable), .out(FA_in0));
    tri_state tri_1(.a(tri_in1), .enable(enable), .out(FA_in1));
    Full_Adder FA(.a(FA_in0), .b(FA_in1), .carry_in(carry_in), .sum(FA_out), .carry_out(carry_out));
    mux mux0(.a(tri_in1), .b(FA_out), .select(enable), .out(sum));
endmodule