data/full_repos/permissive/429737743/sources_1/new/PCReg.v
1: b'%Error: data/full_repos/permissive/429737743/sources_1/new/PCReg.v:1: Cannot find include file: cpu_constant.v\n`include "cpu_constant.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.sv\n             cpu_constant.v\n             cpu_constant.v.v\n             cpu_constant.v.sv\n             obj_dir/cpu_constant.v\n             obj_dir/cpu_constant.v.v\n             obj_dir/cpu_constant.v.sv\n%Error: data/full_repos/permissive/429737743/sources_1/new/PCReg.v:8: Define or directive not defined: \'`auipcType\'\n    if ((op == `auipcType) || (op == `luiType)) begin\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/PCReg.v:8: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if ((op == `auipcType) || (op == `luiType)) begin\n                         ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/PCReg.v:8: Define or directive not defined: \'`luiType\'\n    if ((op == `auipcType) || (op == `luiType)) begin\n                                     ^~~~~~~~\n%Error: Cannot continue\n'
module PCReg (op, pc, imm, out);
    input [6 : 0] op;
    input [31 : 0] pc, imm;
    output [31 : 0] out;
    reg [31 : 0] out;
always @(*) begin
    if ((op == `auipcType) || (op == `luiType)) begin
        out = pc + (imm << 12);
    end
    else begin
        out = pc + 4;
    end
end
    
endmodule
module PCReg (op, pc, imm, out);

    input [6 : 0] op;
    input [31 : 0] pc, imm;
    output [31 : 0] out;
    reg [31 : 0] out;
always @(*) begin
    if ((op == `auipcType) || (op == `luiType)) begin
        out = pc + (imm << 12);
    end
    else begin
        out = pc + 4;
    end
end
    
endmodule