data/full_repos/permissive/530404104/src/user_module_341364381657858642.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530404104/src/user_module_341364381657858642.v:67: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                                            : ... In instance user_module_341364381657858642.mcpu6bit_top\nassign dataout   = clk ?  {1\'b00,adreg} : accumulator[5:0]; \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module user_module_341364381657858642(
  input [7:0] io_in,
  output [7:0] io_out
);

mcpu6bit mcpu6bit_top (
  .clk(io_in[0]),
  .rst(io_in[1]),
  .datain(io_in[7:2]),

  .we(io_out[1]),
  .dataout(io_out[7:2])
);

endmodule
module user_module_341364381657858642(
  input [7:0] io_in,
  output [7:0] io_out
);


mcpu6bit mcpu6bit_top (
  .clk(io_in[0]),
  .rst(io_in[1]),
  .datain(io_in[7:2]),

  .we(io_out[1]),
  .dataout(io_out[7:2])
);

endmodule