data/full_repos/permissive/441359809/src/yosys/examples/gowin/demo.v
data/verilator_xmls/543d56bf-9fa3-4da8-8052-8c3be0e28bbe.xml
module demo (
	input clk,
	output [15:0] leds,
	output unused
);
	localparam PRESCALE = 20;
	reg [PRESCALE+3:0] counter = 0;
	always @(posedge clk) counter <= counter + 1;
	assign leds = 1 << counter[PRESCALE +: 4];
endmodule
module demo (
	input clk,
	output [15:0] leds,
	output unused
);

	localparam PRESCALE = 20;
	reg [PRESCALE+3:0] counter = 0;
	always @(posedge clk) counter <= counter + 1;
	assign leds = 1 << counter[PRESCALE +: 4];
endmodule