data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v:183: Signal definition not found, creating implicitly: \'grant_valid\'\nwire wbm0_sel = grant[0] & grant_valid;\n                           ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl/wb_arbiter_8.v:302: Cannot find file containing module: \'arbiter\'\narbiter #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl,data/full_repos/permissive/414822257/arbiter\n             data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl,data/full_repos/permissive/414822257/arbiter.v\n             data/full_repos/permissive/414822257/ip/third_party/verilog-wishbone/rtl,data/full_repos/permissive/414822257/arbiter.sv\n             arbiter\n             arbiter.v\n             arbiter.sv\n             obj_dir/arbiter\n             obj_dir/arbiter.v\n             obj_dir/arbiter.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wb_arbiter_8 #
(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32,
    parameter SELECT_WIDTH = (DATA_WIDTH/8),
    parameter ARB_TYPE = "PRIORITY",
    parameter LSB_PRIORITY = "HIGH"
)
(
    input  wire                    clk,
    input  wire                    rst,


    input  wire [ADDR_WIDTH-1:0]   wbm0_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm0_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm0_dat_o,
    input  wire                    wbm0_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm0_sel_i,
    input  wire                    wbm0_stb_i,
    output wire                    wbm0_ack_o,
    output wire                    wbm0_err_o,
    output wire                    wbm0_rty_o,
    input  wire                    wbm0_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm1_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm1_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm1_dat_o,
    input  wire                    wbm1_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm1_sel_i,
    input  wire                    wbm1_stb_i,
    output wire                    wbm1_ack_o,
    output wire                    wbm1_err_o,
    output wire                    wbm1_rty_o,
    input  wire                    wbm1_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm2_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm2_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm2_dat_o,
    input  wire                    wbm2_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm2_sel_i,
    input  wire                    wbm2_stb_i,
    output wire                    wbm2_ack_o,
    output wire                    wbm2_err_o,
    output wire                    wbm2_rty_o,
    input  wire                    wbm2_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm3_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm3_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm3_dat_o,
    input  wire                    wbm3_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm3_sel_i,
    input  wire                    wbm3_stb_i,
    output wire                    wbm3_ack_o,
    output wire                    wbm3_err_o,
    output wire                    wbm3_rty_o,
    input  wire                    wbm3_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm4_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm4_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm4_dat_o,
    input  wire                    wbm4_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm4_sel_i,
    input  wire                    wbm4_stb_i,
    output wire                    wbm4_ack_o,
    output wire                    wbm4_err_o,
    output wire                    wbm4_rty_o,
    input  wire                    wbm4_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm5_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm5_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm5_dat_o,
    input  wire                    wbm5_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm5_sel_i,
    input  wire                    wbm5_stb_i,
    output wire                    wbm5_ack_o,
    output wire                    wbm5_err_o,
    output wire                    wbm5_rty_o,
    input  wire                    wbm5_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm6_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm6_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm6_dat_o,
    input  wire                    wbm6_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm6_sel_i,
    input  wire                    wbm6_stb_i,
    output wire                    wbm6_ack_o,
    output wire                    wbm6_err_o,
    output wire                    wbm6_rty_o,
    input  wire                    wbm6_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm7_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm7_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm7_dat_o,
    input  wire                    wbm7_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm7_sel_i,
    input  wire                    wbm7_stb_i,
    output wire                    wbm7_ack_o,
    output wire                    wbm7_err_o,
    output wire                    wbm7_rty_o,
    input  wire                    wbm7_cyc_i,


    output wire [ADDR_WIDTH-1:0]   wbs_adr_o,
    input  wire [DATA_WIDTH-1:0]   wbs_dat_i,
    output wire [DATA_WIDTH-1:0]   wbs_dat_o,
    output wire                    wbs_we_o,
    output wire [SELECT_WIDTH-1:0] wbs_sel_o,
    output wire                    wbs_stb_o,
    input  wire                    wbs_ack_i,
    input  wire                    wbs_err_i,
    input  wire                    wbs_rty_i,
    output wire                    wbs_cyc_o
);

wire [7:0] request;
wire [7:0] grant;

assign request[0] = wbm0_cyc_i;
assign request[1] = wbm1_cyc_i;
assign request[2] = wbm2_cyc_i;
assign request[3] = wbm3_cyc_i;
assign request[4] = wbm4_cyc_i;
assign request[5] = wbm5_cyc_i;
assign request[6] = wbm6_cyc_i;
assign request[7] = wbm7_cyc_i;

wire wbm0_sel = grant[0] & grant_valid;
wire wbm1_sel = grant[1] & grant_valid;
wire wbm2_sel = grant[2] & grant_valid;
wire wbm3_sel = grant[3] & grant_valid;
wire wbm4_sel = grant[4] & grant_valid;
wire wbm5_sel = grant[5] & grant_valid;
wire wbm6_sel = grant[6] & grant_valid;
wire wbm7_sel = grant[7] & grant_valid;


assign wbm0_dat_o = wbs_dat_i;
assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
assign wbm0_err_o = wbs_err_i & wbm0_sel;
assign wbm0_rty_o = wbs_rty_i & wbm0_sel;


assign wbm1_dat_o = wbs_dat_i;
assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
assign wbm1_err_o = wbs_err_i & wbm1_sel;
assign wbm1_rty_o = wbs_rty_i & wbm1_sel;


assign wbm2_dat_o = wbs_dat_i;
assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
assign wbm2_err_o = wbs_err_i & wbm2_sel;
assign wbm2_rty_o = wbs_rty_i & wbm2_sel;


assign wbm3_dat_o = wbs_dat_i;
assign wbm3_ack_o = wbs_ack_i & wbm3_sel;
assign wbm3_err_o = wbs_err_i & wbm3_sel;
assign wbm3_rty_o = wbs_rty_i & wbm3_sel;


assign wbm4_dat_o = wbs_dat_i;
assign wbm4_ack_o = wbs_ack_i & wbm4_sel;
assign wbm4_err_o = wbs_err_i & wbm4_sel;
assign wbm4_rty_o = wbs_rty_i & wbm4_sel;


assign wbm5_dat_o = wbs_dat_i;
assign wbm5_ack_o = wbs_ack_i & wbm5_sel;
assign wbm5_err_o = wbs_err_i & wbm5_sel;
assign wbm5_rty_o = wbs_rty_i & wbm5_sel;


assign wbm6_dat_o = wbs_dat_i;
assign wbm6_ack_o = wbs_ack_i & wbm6_sel;
assign wbm6_err_o = wbs_err_i & wbm6_sel;
assign wbm6_rty_o = wbs_rty_i & wbm6_sel;


assign wbm7_dat_o = wbs_dat_i;
assign wbm7_ack_o = wbs_ack_i & wbm7_sel;
assign wbm7_err_o = wbs_err_i & wbm7_sel;
assign wbm7_rty_o = wbs_rty_i & wbm7_sel;


assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
                   wbm1_sel ? wbm1_adr_i :
                   wbm2_sel ? wbm2_adr_i :
                   wbm3_sel ? wbm3_adr_i :
                   wbm4_sel ? wbm4_adr_i :
                   wbm5_sel ? wbm5_adr_i :
                   wbm6_sel ? wbm6_adr_i :
                   wbm7_sel ? wbm7_adr_i :
                   {ADDR_WIDTH{1'b0}};

assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
                   wbm1_sel ? wbm1_dat_i :
                   wbm2_sel ? wbm2_dat_i :
                   wbm3_sel ? wbm3_dat_i :
                   wbm4_sel ? wbm4_dat_i :
                   wbm5_sel ? wbm5_dat_i :
                   wbm6_sel ? wbm6_dat_i :
                   wbm7_sel ? wbm7_dat_i :
                   {DATA_WIDTH{1'b0}};

assign wbs_we_o = wbm0_sel ? wbm0_we_i :
                  wbm1_sel ? wbm1_we_i :
                  wbm2_sel ? wbm2_we_i :
                  wbm3_sel ? wbm3_we_i :
                  wbm4_sel ? wbm4_we_i :
                  wbm5_sel ? wbm5_we_i :
                  wbm6_sel ? wbm6_we_i :
                  wbm7_sel ? wbm7_we_i :
                  1'b0;

assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
                   wbm1_sel ? wbm1_sel_i :
                   wbm2_sel ? wbm2_sel_i :
                   wbm3_sel ? wbm3_sel_i :
                   wbm4_sel ? wbm4_sel_i :
                   wbm5_sel ? wbm5_sel_i :
                   wbm6_sel ? wbm6_sel_i :
                   wbm7_sel ? wbm7_sel_i :
                   {SELECT_WIDTH{1'b0}};

assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
                   wbm1_sel ? wbm1_stb_i :
                   wbm2_sel ? wbm2_stb_i :
                   wbm3_sel ? wbm3_stb_i :
                   wbm4_sel ? wbm4_stb_i :
                   wbm5_sel ? wbm5_stb_i :
                   wbm6_sel ? wbm6_stb_i :
                   wbm7_sel ? wbm7_stb_i :
                   1'b0;

assign wbs_cyc_o = wbm0_sel ? 1'b1 :
                   wbm1_sel ? 1'b1 :
                   wbm2_sel ? 1'b1 :
                   wbm3_sel ? 1'b1 :
                   wbm4_sel ? 1'b1 :
                   wbm5_sel ? 1'b1 :
                   wbm6_sel ? 1'b1 :
                   wbm7_sel ? 1'b1 :
                   1'b0;


arbiter #(
    .PORTS(8),
    .TYPE(ARB_TYPE),
    .BLOCK("REQUEST"),
    .LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
    .clk(clk),
    .rst(rst),
    .request(request),
    .acknowledge(),
    .grant(grant),
    .grant_valid(grant_valid),
    .grant_encoded()
);

endmodule
module wb_arbiter_8 #
(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32,
    parameter SELECT_WIDTH = (DATA_WIDTH/8),
    parameter ARB_TYPE = "PRIORITY",
    parameter LSB_PRIORITY = "HIGH"
)
(
    input  wire                    clk,
    input  wire                    rst,


    input  wire [ADDR_WIDTH-1:0]   wbm0_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm0_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm0_dat_o,
    input  wire                    wbm0_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm0_sel_i,
    input  wire                    wbm0_stb_i,
    output wire                    wbm0_ack_o,
    output wire                    wbm0_err_o,
    output wire                    wbm0_rty_o,
    input  wire                    wbm0_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm1_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm1_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm1_dat_o,
    input  wire                    wbm1_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm1_sel_i,
    input  wire                    wbm1_stb_i,
    output wire                    wbm1_ack_o,
    output wire                    wbm1_err_o,
    output wire                    wbm1_rty_o,
    input  wire                    wbm1_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm2_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm2_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm2_dat_o,
    input  wire                    wbm2_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm2_sel_i,
    input  wire                    wbm2_stb_i,
    output wire                    wbm2_ack_o,
    output wire                    wbm2_err_o,
    output wire                    wbm2_rty_o,
    input  wire                    wbm2_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm3_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm3_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm3_dat_o,
    input  wire                    wbm3_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm3_sel_i,
    input  wire                    wbm3_stb_i,
    output wire                    wbm3_ack_o,
    output wire                    wbm3_err_o,
    output wire                    wbm3_rty_o,
    input  wire                    wbm3_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm4_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm4_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm4_dat_o,
    input  wire                    wbm4_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm4_sel_i,
    input  wire                    wbm4_stb_i,
    output wire                    wbm4_ack_o,
    output wire                    wbm4_err_o,
    output wire                    wbm4_rty_o,
    input  wire                    wbm4_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm5_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm5_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm5_dat_o,
    input  wire                    wbm5_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm5_sel_i,
    input  wire                    wbm5_stb_i,
    output wire                    wbm5_ack_o,
    output wire                    wbm5_err_o,
    output wire                    wbm5_rty_o,
    input  wire                    wbm5_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm6_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm6_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm6_dat_o,
    input  wire                    wbm6_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm6_sel_i,
    input  wire                    wbm6_stb_i,
    output wire                    wbm6_ack_o,
    output wire                    wbm6_err_o,
    output wire                    wbm6_rty_o,
    input  wire                    wbm6_cyc_i,


    input  wire [ADDR_WIDTH-1:0]   wbm7_adr_i,
    input  wire [DATA_WIDTH-1:0]   wbm7_dat_i,
    output wire [DATA_WIDTH-1:0]   wbm7_dat_o,
    input  wire                    wbm7_we_i,
    input  wire [SELECT_WIDTH-1:0] wbm7_sel_i,
    input  wire                    wbm7_stb_i,
    output wire                    wbm7_ack_o,
    output wire                    wbm7_err_o,
    output wire                    wbm7_rty_o,
    input  wire                    wbm7_cyc_i,


    output wire [ADDR_WIDTH-1:0]   wbs_adr_o,
    input  wire [DATA_WIDTH-1:0]   wbs_dat_i,
    output wire [DATA_WIDTH-1:0]   wbs_dat_o,
    output wire                    wbs_we_o,
    output wire [SELECT_WIDTH-1:0] wbs_sel_o,
    output wire                    wbs_stb_o,
    input  wire                    wbs_ack_i,
    input  wire                    wbs_err_i,
    input  wire                    wbs_rty_i,
    output wire                    wbs_cyc_o
);


wire [7:0] request;
wire [7:0] grant;

assign request[0] = wbm0_cyc_i;
assign request[1] = wbm1_cyc_i;
assign request[2] = wbm2_cyc_i;
assign request[3] = wbm3_cyc_i;
assign request[4] = wbm4_cyc_i;
assign request[5] = wbm5_cyc_i;
assign request[6] = wbm6_cyc_i;
assign request[7] = wbm7_cyc_i;

wire wbm0_sel = grant[0] & grant_valid;
wire wbm1_sel = grant[1] & grant_valid;
wire wbm2_sel = grant[2] & grant_valid;
wire wbm3_sel = grant[3] & grant_valid;
wire wbm4_sel = grant[4] & grant_valid;
wire wbm5_sel = grant[5] & grant_valid;
wire wbm6_sel = grant[6] & grant_valid;
wire wbm7_sel = grant[7] & grant_valid;


assign wbm0_dat_o = wbs_dat_i;
assign wbm0_ack_o = wbs_ack_i & wbm0_sel;
assign wbm0_err_o = wbs_err_i & wbm0_sel;
assign wbm0_rty_o = wbs_rty_i & wbm0_sel;


assign wbm1_dat_o = wbs_dat_i;
assign wbm1_ack_o = wbs_ack_i & wbm1_sel;
assign wbm1_err_o = wbs_err_i & wbm1_sel;
assign wbm1_rty_o = wbs_rty_i & wbm1_sel;


assign wbm2_dat_o = wbs_dat_i;
assign wbm2_ack_o = wbs_ack_i & wbm2_sel;
assign wbm2_err_o = wbs_err_i & wbm2_sel;
assign wbm2_rty_o = wbs_rty_i & wbm2_sel;


assign wbm3_dat_o = wbs_dat_i;
assign wbm3_ack_o = wbs_ack_i & wbm3_sel;
assign wbm3_err_o = wbs_err_i & wbm3_sel;
assign wbm3_rty_o = wbs_rty_i & wbm3_sel;


assign wbm4_dat_o = wbs_dat_i;
assign wbm4_ack_o = wbs_ack_i & wbm4_sel;
assign wbm4_err_o = wbs_err_i & wbm4_sel;
assign wbm4_rty_o = wbs_rty_i & wbm4_sel;


assign wbm5_dat_o = wbs_dat_i;
assign wbm5_ack_o = wbs_ack_i & wbm5_sel;
assign wbm5_err_o = wbs_err_i & wbm5_sel;
assign wbm5_rty_o = wbs_rty_i & wbm5_sel;


assign wbm6_dat_o = wbs_dat_i;
assign wbm6_ack_o = wbs_ack_i & wbm6_sel;
assign wbm6_err_o = wbs_err_i & wbm6_sel;
assign wbm6_rty_o = wbs_rty_i & wbm6_sel;


assign wbm7_dat_o = wbs_dat_i;
assign wbm7_ack_o = wbs_ack_i & wbm7_sel;
assign wbm7_err_o = wbs_err_i & wbm7_sel;
assign wbm7_rty_o = wbs_rty_i & wbm7_sel;


assign wbs_adr_o = wbm0_sel ? wbm0_adr_i :
                   wbm1_sel ? wbm1_adr_i :
                   wbm2_sel ? wbm2_adr_i :
                   wbm3_sel ? wbm3_adr_i :
                   wbm4_sel ? wbm4_adr_i :
                   wbm5_sel ? wbm5_adr_i :
                   wbm6_sel ? wbm6_adr_i :
                   wbm7_sel ? wbm7_adr_i :
                   {ADDR_WIDTH{1'b0}};

assign wbs_dat_o = wbm0_sel ? wbm0_dat_i :
                   wbm1_sel ? wbm1_dat_i :
                   wbm2_sel ? wbm2_dat_i :
                   wbm3_sel ? wbm3_dat_i :
                   wbm4_sel ? wbm4_dat_i :
                   wbm5_sel ? wbm5_dat_i :
                   wbm6_sel ? wbm6_dat_i :
                   wbm7_sel ? wbm7_dat_i :
                   {DATA_WIDTH{1'b0}};

assign wbs_we_o = wbm0_sel ? wbm0_we_i :
                  wbm1_sel ? wbm1_we_i :
                  wbm2_sel ? wbm2_we_i :
                  wbm3_sel ? wbm3_we_i :
                  wbm4_sel ? wbm4_we_i :
                  wbm5_sel ? wbm5_we_i :
                  wbm6_sel ? wbm6_we_i :
                  wbm7_sel ? wbm7_we_i :
                  1'b0;

assign wbs_sel_o = wbm0_sel ? wbm0_sel_i :
                   wbm1_sel ? wbm1_sel_i :
                   wbm2_sel ? wbm2_sel_i :
                   wbm3_sel ? wbm3_sel_i :
                   wbm4_sel ? wbm4_sel_i :
                   wbm5_sel ? wbm5_sel_i :
                   wbm6_sel ? wbm6_sel_i :
                   wbm7_sel ? wbm7_sel_i :
                   {SELECT_WIDTH{1'b0}};

assign wbs_stb_o = wbm0_sel ? wbm0_stb_i :
                   wbm1_sel ? wbm1_stb_i :
                   wbm2_sel ? wbm2_stb_i :
                   wbm3_sel ? wbm3_stb_i :
                   wbm4_sel ? wbm4_stb_i :
                   wbm5_sel ? wbm5_stb_i :
                   wbm6_sel ? wbm6_stb_i :
                   wbm7_sel ? wbm7_stb_i :
                   1'b0;

assign wbs_cyc_o = wbm0_sel ? 1'b1 :
                   wbm1_sel ? 1'b1 :
                   wbm2_sel ? 1'b1 :
                   wbm3_sel ? 1'b1 :
                   wbm4_sel ? 1'b1 :
                   wbm5_sel ? 1'b1 :
                   wbm6_sel ? 1'b1 :
                   wbm7_sel ? 1'b1 :
                   1'b0;


arbiter #(
    .PORTS(8),
    .TYPE(ARB_TYPE),
    .BLOCK("REQUEST"),
    .LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
    .clk(clk),
    .rst(rst),
    .request(request),
    .acknowledge(),
    .grant(grant),
    .grant_valid(grant_valid),
    .grant_encoded()
);

endmodule