data/full_repos/permissive/405912356/rv32i_alu.v
data/verilator_xmls/eaab452b-8a7d-4375-b560-f9801d2f6361.xml
module Alu(
    input wire [3:0] sel,
    input wire [31:0] in_a,
    input wire [31:0] in_b,
    output reg [31:0] out
    );

    wire [31:0] a_signed;
    wire [31:0] b_signed;
    assign a_signed = $signed(in_a);
    assign b_signed = $signed(in_b);

    always @ (*) begin
        case (sel)
            4'b0000: out = in_a + in_b;
            4'b0010: out = a_signed < b_signed ? 1 : 0;
            4'b0011: out = in_a < in_b ? 1 : 0;
            4'b0100: out = in_a ^ in_b;
            4'b0110: out = in_a | in_b;
            4'b0111: out = in_a & in_b;
            4'b0001: out = in_a << in_b;
            4'b0101: out = in_a >> in_b;
            4'b1101: out = a_signed >> in_b;
            4'b1000: out = in_a - in_b;
            default: out = 32'h00000000;
        endcase
    end
endmodule
module Alu(
    input wire [3:0] sel,
    input wire [31:0] in_a,
    input wire [31:0] in_b,
    output reg [31:0] out
    );


    wire [31:0] a_signed;
    wire [31:0] b_signed;
    assign a_signed = $signed(in_a);
    assign b_signed = $signed(in_b);

    always @ (*) begin
        case (sel)
            4'b0000: out = in_a + in_b;
            4'b0010: out = a_signed < b_signed ? 1 : 0;
            4'b0011: out = in_a < in_b ? 1 : 0;
            4'b0100: out = in_a ^ in_b;
            4'b0110: out = in_a | in_b;
            4'b0111: out = in_a & in_b;
            4'b0001: out = in_a << in_b;
            4'b0101: out = in_a >> in_b;
            4'b1101: out = a_signed >> in_b;
            4'b1000: out = in_a - in_b;
            default: out = 32'h00000000;
        endcase
    end
endmodule