data/full_repos/permissive/460183508/rtl/upcounter.v
data/verilator_xmls/c254a2d1-7242-4bfd-a3f8-4175fe7cd758.xml
module upcounter
#(parameter WIDTH=8,
            INCREMENT=1,
            MAX_COUNT=-1,
            RESET_VALUE=0
)
(
    input wire reset,
    input wire enable,
    input wire clk,
    output reg[WIDTH-1:0] count
);
    always @(posedge clk, posedge reset) begin
        if (reset) begin

            count <= RESET_VALUE;
        end
        else begin
            if (enable) begin
                if (count < MAX_COUNT) begin

                    count <= count + INCREMENT;
                end
                else begin

                    count <= {WIDTH{1'b0}};
                end
            end
        end
    end
endmodule
module upcounter
#(parameter WIDTH=8,
            INCREMENT=1,
            MAX_COUNT=-1,
            RESET_VALUE=0
)
(
    input wire reset,
    input wire enable,
    input wire clk,
    output reg[WIDTH-1:0] count
);

    always @(posedge clk, posedge reset) begin
        if (reset) begin

            count <= RESET_VALUE;
        end
        else begin
            if (enable) begin
                if (count < MAX_COUNT) begin

                    count <= count + INCREMENT;
                end
                else begin

                    count <= {WIDTH{1'b0}};
                end
            end
        end
    end
endmodule