data/full_repos/permissive/428125225/fifo_rd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428125225/fifo_rd.v:26: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                 : ... In instance fifo_rd\n        data_fifo <= 8\'d0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428125225/fifo_rd.v:41: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                 : ... In instance fifo_rd\n                    data_fifo <= 8\'d0;\n                              ^~\n%Error: Exiting due to 2 warning(s)\n'
module fifo_rd(

    input                    clk    ,
    input                    rst_n  ,


    input           [8:0]    data   ,
    input                    full ,
    input                    empty,
    output   reg             rdreq,
    output                  fifodate
);


reg   [8:0]                  data_fifo;
reg   [1:0]                  flow_cnt ;
wire [8:0] fifodata ;




assign fifodata  = data_fifo;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        rdreq <= 1'b0;
        data_fifo <= 8'd0;
    end
    else begin
        case(flow_cnt)
            2'd0: begin
                if(full) begin
                    rdreq <= 1'b1;
                    flow_cnt <= flow_cnt + 1'b1;
                end
                else
                    flow_cnt <= flow_cnt;
            end 
            2'd1: begin
                if(empty) begin
                    rdreq <= 1'b0;
                    data_fifo <= 8'd0;
                    flow_cnt  <= 2'd0;
                end
                else begin
                    rdreq <= 1'b1;
                    data_fifo <= data;
                end 
            end 
            default: flow_cnt <= 2'd0;
        endcase
    end
end

endmodule
module fifo_rd(

    input                    clk    ,
    input                    rst_n  ,


    input           [8:0]    data   ,
    input                    full ,
    input                    empty,
    output   reg             rdreq,
    output                  fifodate
);



reg   [8:0]                  data_fifo;
reg   [1:0]                  flow_cnt ;
wire [8:0] fifodata ;




assign fifodata  = data_fifo;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        rdreq <= 1'b0;
        data_fifo <= 8'd0;
    end
    else begin
        case(flow_cnt)
            2'd0: begin
                if(full) begin
                    rdreq <= 1'b1;
                    flow_cnt <= flow_cnt + 1'b1;
                end
                else
                    flow_cnt <= flow_cnt;
            end 
            2'd1: begin
                if(empty) begin
                    rdreq <= 1'b0;
                    data_fifo <= 8'd0;
                    flow_cnt  <= 2'd0;
                end
                else begin
                    rdreq <= 1'b1;
                    data_fifo <= data;
                end 
            end 
            default: flow_cnt <= 2'd0;
        endcase
    end
end

endmodule