data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/clk_divider.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/clk_divider.v:24: Define or directive not defined: '`DLA_CLOCK_DIVIDE'\n        clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/clk_divider.v:32: Define or directive not defined: '`DLA_CLOCK_DIVIDE'\n                clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;\n                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/clk_divider.v:35: Define or directive not defined: '`DLA_CLOCK_DIVIDE'\n            clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;\n                        ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module clk_divider(
    clk,
    reset,
    slow_clk
);

input clk;
input reset;
output reg slow_clk;

reg [7:0] clkCount;
reg firstTime;
reg clkPrev;


always @(posedge clk or negedge reset) begin
    if(!reset) begin
        slow_clk <= 0;
        clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        firstTime <= 1'b1;
    end else begin
    if (clkCount == 0) begin

        if (firstTime == 1'b1 )  begin
                slow_clk <= 1'b1;
                firstTime <= 1'b0;
                clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        end else begin
            slow_clk <= ~slow_clk;
            clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        end
    end else begin
        clkCount <= clkCount - 2'b10;
    end

    end
end

endmodule
module clk_divider(
    clk,
    reset,
    slow_clk
);


input clk;
input reset;
output reg slow_clk;

reg [7:0] clkCount;
reg firstTime;
reg clkPrev;


always @(posedge clk or negedge reset) begin
    if(!reset) begin
        slow_clk <= 0;
        clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        firstTime <= 1'b1;
    end else begin
    if (clkCount == 0) begin

        if (firstTime == 1'b1 )  begin
                slow_clk <= 1'b1;
                firstTime <= 1'b0;
                clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        end else begin
            slow_clk <= ~slow_clk;
            clkCount <= `DLA_CLOCK_DIVIDE - 2'b10;
        end
    end else begin
        clkCount <= clkCount - 2'b10;
    end

    end
end

endmodule