data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/adder.v
data/verilator_xmls/ea1cd6a9-4d89-4d2b-9cd9-74e16a24b68b.xml
module adder (
  input [31:0] a, b,
  output wire [31:0] y
);



assign y = a + b;

endmodule
module adder (
  input [31:0] a, b,
  output wire [31:0] y
);




assign y = a + b;

endmodule