data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:1: Cannot find include file: fetch.v\n`include"fetch.v" \n        ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:24: Unsupported or unknown PLI call: $monitor\n $monitor ($time,"ns:  clock=%b, PC=%h, icode=%h, ifun=%h, valP=%h\\n",clock,PC,icode,ifun,valP); \n ^~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fetch.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,PC, icode,ifun,rA,rB,valC, valP,clock,instr_valid,imem_error);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/fetch_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module testbench;

	reg[63:0]PC;
	reg clock;
	wire [1:0]status;
wire [3:0] icode;
wire [3:0] ifun;
wire [3:0] rA;
wire [3:0] rB; 
wire [63:0] valC;
wire [63:0] valP;
wire [79:0] test;
wire instr_valid;
wire imem_error;
wire [1:0]f_stat;


	integer i,k,j;
	fetch DUT(PC, icode,ifun,rA,rB,valC, valP,clock,instr_valid,imem_error,f_stat);
	initial begin
	
	$monitor ($time,"ns:  clock=%b, PC=%h, icode=%h, ifun=%h, valP=%h\n",clock,PC,icode,ifun,valP); 
	$dumpfile("fetch.vcd");
    	$dumpvars(0,PC, icode,ifun,rA,rB,valC, valP,clock,instr_valid,imem_error);
	clock=0;
    PC=4;
	#10;
	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	PC=valP;
	clock=0;
	#10;
	end
end
endmodule
module testbench;


	reg[63:0]PC;
	reg clock;
	wire [1:0]status;
wire [3:0] icode;
wire [3:0] ifun;
wire [3:0] rA;
wire [3:0] rB; 
wire [63:0] valC;
wire [63:0] valP;
wire [79:0] test;
wire instr_valid;
wire imem_error;
wire [1:0]f_stat;


	integer i,k,j;
	fetch DUT(PC, icode,ifun,rA,rB,valC, valP,clock,instr_valid,imem_error,f_stat);
	initial begin
	
	$monitor ($time,"ns:  clock=%b, PC=%h, icode=%h, ifun=%h, valP=%h\n",clock,PC,icode,ifun,valP); 
	$dumpfile("fetch.vcd");
    	$dumpvars(0,PC, icode,ifun,rA,rB,valC, valP,clock,instr_valid,imem_error);
	clock=0;
    PC=4;
	#10;
	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	PC=valP;
	clock=0;
	#10;
	end
end
endmodule