data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/MSBComponents/Reg_Comp/rtl/verilog/wb_reg_dev.v
data/verilator_xmls/a08eca61-ddb5-4f71-ad9b-80dad3eaacfe.xml
module wb_reg_dev
   #(
      parameter CLK_MHZ = 25,
      parameter reg_08_int_val = 32'h1234abcd
   )
   (





      wb_reset,
      wb_clk,






      wb_adr,
      wb_master_data,
      wb_cyc,
      wb_stb,
      wb_sel,
      wb_we,
      wb_slave_data,
      wb_ack,
      wb_err,
      wb_rty,








      wb_intr,





      out_pins
   );
   input wb_reset;
   input wb_clk;
   input [31:0] wb_adr;
   input [31:0] wb_master_data;
   input wb_cyc;
   input wb_stb;
   input [3:0] wb_sel;
   input wb_we;
   output [31:0] wb_slave_data;
   output wb_ack;
   output wb_err;
   output wb_rty;
   output wb_intr;
   output [7:0] out_pins;













   reg [31:0] reg_00;
   reg [31:0] reg_04;

   reg write_ack;





   wire reg_00_sel;
   wire reg_04_sel;
   wire reg_08_sel;
   wire read_ack;
   wire [31:0] read_data;





   assign reg_00_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b00) ) ? 1'b1 : 1'b0;
   assign reg_04_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b01) ) ? 1'b1 : 1'b0;
   assign reg_08_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b10) ) ? 1'b1 : 1'b0;




   assign read_ack = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_we == 1'b0)) ? 1'b1:1'b0;



   assign read_data = (reg_00_sel == 1'b1)? reg_00 :
   (reg_04_sel == 1'b1)? reg_04 :
   (reg_08_sel == 1'b1)? reg_08_int_val :
   32'hdeadbeef;



   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         write_ack <= 0;
      end
      else begin
         if( (wb_stb == 1'b1) && (wb_cyc == 1'b1) &&
            (wb_we == 1'b1) && (write_ack == 1'b0) ) begin
            write_ack <= 1'b1;
         end
         else begin
            write_ack <= 1'b0;
         end
      end



   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         reg_00 <= 32'b0;
      end
      else begin
         if ( (reg_00_sel == 1'b1) && (wb_we == 1'b1) &&
            (write_ack == 1'b0) ) begin
            if( wb_sel[0] == 1'b1 ) begin
               reg_00[7:0] <= wb_master_data[7:0];
            end
            if( wb_sel[1] == 1'b1 ) begin
               reg_00[15:8] <= wb_master_data[15:8];
            end
            if( wb_sel[2] == 1'b1 ) begin
               reg_00[23:16] <= wb_master_data[23:16];
            end
            if( wb_sel[3] == 1'b1 ) begin
               reg_00[31:24] <= wb_master_data[31:24];
            end
         end
      end



   function integer i_clk_mhz;
      input integer clk_mhz;
      begin
         i_clk_mhz = clk_mhz;
      end
   endfunction
   parameter CLK_MHZ_INT_VALUE = i_clk_mhz(CLK_MHZ);
   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         reg_04 <= CLK_MHZ_INT_VALUE;
      end
      else begin
         if ( (reg_04_sel == 1'b1) && (wb_we == 1'b1) &&
            (write_ack == 1'b0) ) begin
            if( wb_sel[0] == 1'b1 ) begin
               reg_04[7:0] <= wb_master_data[7:0];
            end
            if( wb_sel[1] == 1'b1 ) begin
               reg_04[15:8] <= wb_master_data[15:8];
            end
            if( wb_sel[2] == 1'b1 ) begin
               reg_04[23:16] <= wb_master_data[23:16];
            end
            if( wb_sel[3] == 1'b1 ) begin
               reg_04[31:24] <= wb_master_data[31:24];
            end
         end
      end






   assign wb_ack = read_ack | write_ack;

   assign wb_slave_data = read_data;

   assign wb_rty = 1'b0;
   assign wb_err = 1'b0;

   assign wb_intr = 1'b0;
   assign out_pins = reg_00[7:0];
	
	endmodule
module wb_reg_dev
   #(
      parameter CLK_MHZ = 25,
      parameter reg_08_int_val = 32'h1234abcd
   )
   (





      wb_reset,
      wb_clk,






      wb_adr,
      wb_master_data,
      wb_cyc,
      wb_stb,
      wb_sel,
      wb_we,
      wb_slave_data,
      wb_ack,
      wb_err,
      wb_rty,








      wb_intr,





      out_pins
   );

   input wb_reset;
   input wb_clk;
   input [31:0] wb_adr;
   input [31:0] wb_master_data;
   input wb_cyc;
   input wb_stb;
   input [3:0] wb_sel;
   input wb_we;
   output [31:0] wb_slave_data;
   output wb_ack;
   output wb_err;
   output wb_rty;
   output wb_intr;
   output [7:0] out_pins;













   reg [31:0] reg_00;
   reg [31:0] reg_04;

   reg write_ack;





   wire reg_00_sel;
   wire reg_04_sel;
   wire reg_08_sel;
   wire read_ack;
   wire [31:0] read_data;





   assign reg_00_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b00) ) ? 1'b1 : 1'b0;
   assign reg_04_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b01) ) ? 1'b1 : 1'b0;
   assign reg_08_sel = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_adr[3:2] == 2'b10) ) ? 1'b1 : 1'b0;




   assign read_ack = ((wb_stb == 1'b1) && (wb_cyc == 1'b1)
   && (wb_we == 1'b0)) ? 1'b1:1'b0;



   assign read_data = (reg_00_sel == 1'b1)? reg_00 :
   (reg_04_sel == 1'b1)? reg_04 :
   (reg_08_sel == 1'b1)? reg_08_int_val :
   32'hdeadbeef;



   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         write_ack <= 0;
      end
      else begin
         if( (wb_stb == 1'b1) && (wb_cyc == 1'b1) &&
            (wb_we == 1'b1) && (write_ack == 1'b0) ) begin
            write_ack <= 1'b1;
         end
         else begin
            write_ack <= 1'b0;
         end
      end



   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         reg_00 <= 32'b0;
      end
      else begin
         if ( (reg_00_sel == 1'b1) && (wb_we == 1'b1) &&
            (write_ack == 1'b0) ) begin
            if( wb_sel[0] == 1'b1 ) begin
               reg_00[7:0] <= wb_master_data[7:0];
            end
            if( wb_sel[1] == 1'b1 ) begin
               reg_00[15:8] <= wb_master_data[15:8];
            end
            if( wb_sel[2] == 1'b1 ) begin
               reg_00[23:16] <= wb_master_data[23:16];
            end
            if( wb_sel[3] == 1'b1 ) begin
               reg_00[31:24] <= wb_master_data[31:24];
            end
         end
      end



   function integer i_clk_mhz;
      input integer clk_mhz;
      begin
         i_clk_mhz = clk_mhz;
      end
   endfunction
   parameter CLK_MHZ_INT_VALUE = i_clk_mhz(CLK_MHZ);
   always @( posedge wb_clk or posedge wb_reset )
      if ( wb_reset ) begin
         reg_04 <= CLK_MHZ_INT_VALUE;
      end
      else begin
         if ( (reg_04_sel == 1'b1) && (wb_we == 1'b1) &&
            (write_ack == 1'b0) ) begin
            if( wb_sel[0] == 1'b1 ) begin
               reg_04[7:0] <= wb_master_data[7:0];
            end
            if( wb_sel[1] == 1'b1 ) begin
               reg_04[15:8] <= wb_master_data[15:8];
            end
            if( wb_sel[2] == 1'b1 ) begin
               reg_04[23:16] <= wb_master_data[23:16];
            end
            if( wb_sel[3] == 1'b1 ) begin
               reg_04[31:24] <= wb_master_data[31:24];
            end
         end
      end






   assign wb_ack = read_ack | write_ack;

   assign wb_slave_data = read_data;

   assign wb_rty = 1'b0;
   assign wb_err = 1'b0;

   assign wb_intr = 1'b0;
   assign out_pins = reg_00[7:0];
	
	endmodule