data/full_repos/permissive/450760589/src/receiver.v
1: b'%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:36: Operator EQ expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'in\' generates 1 bits.\n                                                                      : ... In instance receiver\n      if(in == (value + 1) % 2)\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:50: Operator ADD expects 48 bits on the RHS, but RHS\'s VARREF \'in\' generates 1 bits.\n                                                                      : ... In instance receiver\n      desMAC = (desMAC << 1) + in;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:55: Operator ADD expects 48 bits on the RHS, but RHS\'s VARREF \'in\' generates 1 bits.\n                                                                      : ... In instance receiver\n      srcMAC = (srcMAC << 1) + in;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:60: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'in\' generates 1 bits.\n                                                                      : ... In instance receiver\n      ET = (ET << 1) + in;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:67: Operator ADD expects 1532 bits on the RHS, but RHS\'s VARREF \'in\' generates 1 bits.\n                                                                      : ... In instance receiver\n      Payload = (Payload << 1) + in;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:69: Operator ASSIGN expects 1500 bits on the Assign RHS, but Assign RHS\'s VARREF \'Payload\' generates 1532 bits.\n                                                                      : ... In instance receiver\n        out = Payload;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:68: Operator EQ expects 32 or 15 bits on the LHS, but LHS\'s VARREF \'value\' generates 14 bits.\n                                                                      : ... In instance receiver\n      if(value == 175 + ET)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:73: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ET\' generates 15 bits.\n                                                                      : ... In instance receiver\n        for(i = ET + 31; i > 32; i = i - 1)\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:82: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 15 bits.\n                                                                      : ... In instance receiver\n          size = ET >> 3;  \n               ^\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:70: Operator EQ expects 32 or 15 bits on the LHS, but LHS\'s VARREF \'value\' generates 14 bits.\n                                                                      : ... In instance receiver\n      if(value == 175 + ET + 32)  \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/450760589/src/receiver.v:65: Operator LTE expects 32 or 15 bits on the LHS, but LHS\'s VARREF \'value\' generates 14 bits.\n                                                                      : ... In instance receiver\n    else if(value > 175 && value <= 175 + ET + 32)  \n                                 ^~\n%Warning-UNSIGNED: data/full_repos/permissive/450760589/src/receiver.v:34: Comparison is constant due to unsigned arithmetic\n                                                                         : ... In instance receiver\n    if(value >= 0 && value <= 55)\n             ^~\n%Error: Exiting due to 12 warning(s)\n'
module receiver(clock, in, out, size, desMAC, srcMAC, done);
  input in, clock;
  output reg [11:0] size;
  output reg [47:0] desMAC, srcMAC;
  output reg [1499:0] out;
  output reg done;
  reg [13:0] value;
  reg [7:0] sfdVal = 8'b11010101;
  reg [14:0] ET;
  reg [1499+32:0] Payload;
  reg [32:0] CRC32 = 33'b100000100110000010001110110110111;
  integer i, j;

  initial
  begin
    value = 0;
    out = 0;
    size = 0;
    done = 0;
  end

  always@(posedge clock)
  begin
    if(value == 0)
    begin
      desMAC = 0;
      srcMAC = 0;
      ET = 0;
      Payload = 0;
      size = 0;
      out = 0;
      done = 0;
    end
    if(value >= 0 && value <= 55)
    begin
      if(in == (value + 1) % 2)
        value = value + 1;
      else
        value = 0;
    end
    else if( value > 55 && value <= 63)
    begin
      if(in == sfdVal[value - 56])
        value = value + 1;
      else
        value = 0;
    end
    else if(value > 63 && value <= 111)
    begin
      desMAC = (desMAC << 1) + in;
      value = value + 1;
    end
    else if(value > 111 && value <= 159)
    begin
      srcMAC = (srcMAC << 1) + in;
      value = value + 1;
    end
    else if(value > 159 && value <= 175)
    begin
      ET = (ET << 1) + in;
      if(value == 175)
        ET = ET << 3;
      value = value + 1;
    end
    else if(value > 175 && value <= 175 + ET + 32)
    begin
      Payload = (Payload << 1) + in;
      if(value == 175 + ET)
        out = Payload;
      if(value == 175 + ET + 32)
      begin

        for(i = ET + 31; i > 32; i = i - 1)
          if(Payload[i] == 1)
          begin
            for(j = 0; j < 33; j = j + 1)
              Payload[i - j] = Payload[i - j] ^ CRC32[32 - j];
          end
        if(Payload == 0)
        begin
          done = 1;
          size = ET >> 3;
          value = 0;
        end
        else
        begin
          done = 0;
          value = 0;
        end
      end
      value = value + 1;
    end
  end
endmodule
module receiver(clock, in, out, size, desMAC, srcMAC, done);

  input in, clock;
  output reg [11:0] size;
  output reg [47:0] desMAC, srcMAC;
  output reg [1499:0] out;
  output reg done;
  reg [13:0] value;
  reg [7:0] sfdVal = 8'b11010101;
  reg [14:0] ET;
  reg [1499+32:0] Payload;
  reg [32:0] CRC32 = 33'b100000100110000010001110110110111;
  integer i, j;

  initial
  begin
    value = 0;
    out = 0;
    size = 0;
    done = 0;
  end

  always@(posedge clock)
  begin
    if(value == 0)
    begin
      desMAC = 0;
      srcMAC = 0;
      ET = 0;
      Payload = 0;
      size = 0;
      out = 0;
      done = 0;
    end
    if(value >= 0 && value <= 55)
    begin
      if(in == (value + 1) % 2)
        value = value + 1;
      else
        value = 0;
    end
    else if( value > 55 && value <= 63)
    begin
      if(in == sfdVal[value - 56])
        value = value + 1;
      else
        value = 0;
    end
    else if(value > 63 && value <= 111)
    begin
      desMAC = (desMAC << 1) + in;
      value = value + 1;
    end
    else if(value > 111 && value <= 159)
    begin
      srcMAC = (srcMAC << 1) + in;
      value = value + 1;
    end
    else if(value > 159 && value <= 175)
    begin
      ET = (ET << 1) + in;
      if(value == 175)
        ET = ET << 3;
      value = value + 1;
    end
    else if(value > 175 && value <= 175 + ET + 32)
    begin
      Payload = (Payload << 1) + in;
      if(value == 175 + ET)
        out = Payload;
      if(value == 175 + ET + 32)
      begin

        for(i = ET + 31; i > 32; i = i - 1)
          if(Payload[i] == 1)
          begin
            for(j = 0; j < 33; j = j + 1)
              Payload[i - j] = Payload[i - j] ^ CRC32[32 - j];
          end
        if(Payload == 0)
        begin
          done = 1;
          size = ET >> 3;
          value = 0;
        end
        else
        begin
          done = 0;
          value = 0;
        end
      end
      value = value + 1;
    end
  end
endmodule