data/full_repos/permissive/42434302/ivltests/pr1664684.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr1664684.v:8: Unsupported or unknown PLI call: $monitor\n   initial $monitor($time,,rdo,,rm,cpen,,up14,,rdi);\n           ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr1664684.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   initial $monitor($time,,rdo,,rm,cpen,,up14,,rdi);\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1664684.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1664684.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bench;

   reg [31:0] up14;
   wire [31:0] rdo;
   reg	       rm, cpen;
   tri0 [31:0] rdi;

   bug u1 (rdo, rm, cpen, up14, rdi);

   initial begin
      rm = 1'bX;
      cpen = 1'b0;
      up14 = 'hX;
      #40;
      up14 = 32'd0;
      rm = 1'b0;
      #40;
      $finish;
   end
 endmodule
module bench;


   reg [31:0] up14;
   wire [31:0] rdo;
   reg	       rm, cpen;
   tri0 [31:0] rdi;

   bug u1 (rdo, rm, cpen, up14, rdi);

   initial begin
      rm = 1'bX;
      cpen = 1'b0;
      up14 = 'hX;
      #40;
      up14 = 32'd0;
      rm = 1'b0;
      #40;
      $finish;
   end
 endmodule