data/full_repos/permissive/481044442/BDCDrv/clk_prescale.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481044442/BDCDrv/clk_prescale.v:17: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                             : ... In instance clk_prescale\n     clk_main<=8\'b0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clk_prescale(clk,reset,clk_main);
input clk;
input reset;
output reg clk_main;







reg [7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					counter<=0;
					clk_main<=8'b0;
				end
	else if(counter==8'd9)	begin
								counter<=8'd0;
								clk_main=~clk_main;
							end
		else
			counter<=counter+1'b1;
end
endmodule
module clk_prescale(clk,reset,clk_main);

input clk;
input reset;
output reg clk_main;







reg [7:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset)	begin
					counter<=0;
					clk_main<=8'b0;
				end
	else if(counter==8'd9)	begin
								counter<=8'd0;
								clk_main=~clk_main;
							end
		else
			counter<=counter+1'b1;
end
endmodule