data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:141: Cannot find file containing module: 'MEM4X1'\n    MEM4X1 _TECHMAP_REPLACE_ (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1.v\n             data/full_repos/permissive/441359809/src/yosys/tests/techmap,data/full_repos/permissive/441359809/MEM4X1.sv\n             MEM4X1\n             MEM4X1.v\n             MEM4X1.sv\n             obj_dir/MEM4X1\n             obj_dir/MEM4X1.v\n             obj_dir/MEM4X1.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:66: Unsupported: MSB < LSB of bit extract: -1<0\n                                                                                            : ... In instance __024mem\n   if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=\n                              ^\n%Error: Internal Error: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_map.v:67: ../V3Width.cpp:3809: Under node SEL has no expected width?? Missing Visitor func?\n                                                                                                            : ... In instance __024mem\n     _TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])\n                            ^\n"
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
	parameter MEMID = "";
	parameter SIZE = 256;
	parameter OFFSET = 0;
	parameter ABITS = 8;
	parameter WIDTH = 8;
	parameter signed INIT = 1'bx;

	parameter RD_PORTS = 1;
	parameter RD_CLK_ENABLE = 1'b1;
	parameter RD_CLK_POLARITY = 1'b1;
	parameter RD_TRANSPARENT = 1'b1;

	parameter WR_PORTS = 1;
	parameter WR_CLK_ENABLE = 1'b1;
	parameter WR_CLK_POLARITY = 1'b1;

	input [RD_PORTS-1:0] RD_CLK;
	input [RD_PORTS-1:0] RD_EN;
	input [RD_PORTS*ABITS-1:0] RD_ADDR;
	output reg [RD_PORTS*WIDTH-1:0] RD_DATA;

	input [WR_PORTS-1:0] WR_CLK;
	input [WR_PORTS*WIDTH-1:0] WR_EN;
	input [WR_PORTS*ABITS-1:0] WR_ADDR;
	input [WR_PORTS*WIDTH-1:0] WR_DATA;

	wire [1023:0] _TECHMAP_DO_ = "proc; clean";

	parameter _TECHMAP_CONNMAP_RD_CLK_ = 0;
	parameter _TECHMAP_CONNMAP_WR_CLK_ = 0;

	parameter _TECHMAP_CONSTVAL_RD_EN_ = 0;

	parameter _TECHMAP_BITS_CONNMAP_ = 0;
	parameter _TECHMAP_CONNMAP_WR_EN_ = 0;

	reg _TECHMAP_FAIL_;
	integer k;
	initial begin
		_TECHMAP_FAIL_ <= 0;


		if (INIT !== 1'bx)
			_TECHMAP_FAIL_ <= 1;


		if (RD_PORTS > 1 || WR_PORTS > 1)
			_TECHMAP_FAIL_ <= 1;


		if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1)
			_TECHMAP_FAIL_ <= 1;


		if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
			_TECHMAP_FAIL_ <= 1;


		if (!WR_CLK_ENABLE || !WR_CLK_POLARITY)
			_TECHMAP_FAIL_ <= 1;


		for (k = 1; k < WR_PORTS*WIDTH; k = k+1)
			if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=
					_TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])
				_TECHMAP_FAIL_ <= 1;


		if (_TECHMAP_CONNMAP_RD_CLK_ != _TECHMAP_CONNMAP_WR_CLK_)
			_TECHMAP_FAIL_ <= 1;


		if (OFFSET != 0 || ABITS < 4 || SIZE < 16)
			_TECHMAP_FAIL_ <= 1;
	end

	genvar i;
	generate
	  for (i = 0; i < WIDTH; i=i+1) begin:slice
		\$__mem_4x1_generator #(
			.ABITS(ABITS),
			.SIZE(SIZE)
		) bit_slice (
			.CLK(RD_CLK),
			.RD_ADDR(RD_ADDR),
			.RD_DATA(RD_DATA[i]),
			.WR_ADDR(WR_ADDR),
			.WR_DATA(WR_DATA[i]),
			.WR_EN(WR_EN[0])
		);
	  end
	endgenerate
endmodule
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);

	parameter MEMID = "";
	parameter SIZE = 256;
	parameter OFFSET = 0;
	parameter ABITS = 8;
	parameter WIDTH = 8;
	parameter signed INIT = 1'bx;

	parameter RD_PORTS = 1;
	parameter RD_CLK_ENABLE = 1'b1;
	parameter RD_CLK_POLARITY = 1'b1;
	parameter RD_TRANSPARENT = 1'b1;

	parameter WR_PORTS = 1;
	parameter WR_CLK_ENABLE = 1'b1;
	parameter WR_CLK_POLARITY = 1'b1;

	input [RD_PORTS-1:0] RD_CLK;
	input [RD_PORTS-1:0] RD_EN;
	input [RD_PORTS*ABITS-1:0] RD_ADDR;
	output reg [RD_PORTS*WIDTH-1:0] RD_DATA;

	input [WR_PORTS-1:0] WR_CLK;
	input [WR_PORTS*WIDTH-1:0] WR_EN;
	input [WR_PORTS*ABITS-1:0] WR_ADDR;
	input [WR_PORTS*WIDTH-1:0] WR_DATA;

	wire [1023:0] _TECHMAP_DO_ = "proc; clean";

	parameter _TECHMAP_CONNMAP_RD_CLK_ = 0;
	parameter _TECHMAP_CONNMAP_WR_CLK_ = 0;

	parameter _TECHMAP_CONSTVAL_RD_EN_ = 0;

	parameter _TECHMAP_BITS_CONNMAP_ = 0;
	parameter _TECHMAP_CONNMAP_WR_EN_ = 0;

	reg _TECHMAP_FAIL_;
	integer k;
	initial begin
		_TECHMAP_FAIL_ <= 0;


		if (INIT !== 1'bx)
			_TECHMAP_FAIL_ <= 1;


		if (RD_PORTS > 1 || WR_PORTS > 1)
			_TECHMAP_FAIL_ <= 1;


		if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1)
			_TECHMAP_FAIL_ <= 1;


		if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
			_TECHMAP_FAIL_ <= 1;


		if (!WR_CLK_ENABLE || !WR_CLK_POLARITY)
			_TECHMAP_FAIL_ <= 1;


		for (k = 1; k < WR_PORTS*WIDTH; k = k+1)
			if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=
					_TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])
				_TECHMAP_FAIL_ <= 1;


		if (_TECHMAP_CONNMAP_RD_CLK_ != _TECHMAP_CONNMAP_WR_CLK_)
			_TECHMAP_FAIL_ <= 1;


		if (OFFSET != 0 || ABITS < 4 || SIZE < 16)
			_TECHMAP_FAIL_ <= 1;
	end

	genvar i;
	generate
	  for (i = 0; i < WIDTH; i=i+1) begin:slice
		\$__mem_4x1_generator #(
			.ABITS(ABITS),
			.SIZE(SIZE)
		) bit_slice (
			.CLK(RD_CLK),
			.RD_ADDR(RD_ADDR),
			.RD_DATA(RD_DATA[i]),
			.WR_ADDR(WR_ADDR),
			.WR_DATA(WR_DATA[i]),
			.WR_EN(WR_EN[0])
		);
	  end
	endgenerate
endmodule