data/full_repos/permissive/504677412/src/clk_div.v
data/verilator_xmls/b551b097-9822-42df-9e8a-c9bcf2c813af.xml
module clk_div (
  clk, 
  rst,
  en,
  clk_out
);


  parameter DIV_FACTOR            = 10;
  

  input  wire                       clk;
  input  wire                       rst;
  input  wire                       en;
  output wire                       clk_out;
    

  localparam CNT_WIDTH            = $clog2(DIV_FACTOR);
  

  reg  [CNT_WIDTH-1:0]              cnt_div;
  wire                              cnt_done;
  reg                               en_d1;
  reg                               en_sync;
  reg                               clk_reg;


  always@(posedge clk) begin
    en_d1   <= en;
    en_sync <= en_d1;
  end

  always @(posedge clk or posedge rst) begin
    if(rst) begin
      cnt_div <= {CNT_WIDTH{1'b0}};
    end else if(en_sync) begin
      if(cnt_done) begin
        cnt_div <= {CNT_WIDTH{1'b0}};
      end else begin
        cnt_div <= cnt_div + 1;
      end
    end
  end
  
  assign cnt_done = (cnt_div == DIV_FACTOR-1) ? 1'b1 : 1'b0;
  
  always @(posedge clk or posedge rst) begin
    if(rst) begin
      clk_reg <= 1'b0;
    end else if(en_sync & cnt_done) begin
      clk_reg <= ~clk_reg;
    end
  end
  











  
  assign clk_out = clk_reg;
  
endmodule
module clk_div (
  clk, 
  rst,
  en,
  clk_out
);



  parameter DIV_FACTOR            = 10;
  

  input  wire                       clk;
  input  wire                       rst;
  input  wire                       en;
  output wire                       clk_out;
    

  localparam CNT_WIDTH            = $clog2(DIV_FACTOR);
  

  reg  [CNT_WIDTH-1:0]              cnt_div;
  wire                              cnt_done;
  reg                               en_d1;
  reg                               en_sync;
  reg                               clk_reg;


  always@(posedge clk) begin
    en_d1   <= en;
    en_sync <= en_d1;
  end

  always @(posedge clk or posedge rst) begin
    if(rst) begin
      cnt_div <= {CNT_WIDTH{1'b0}};
    end else if(en_sync) begin
      if(cnt_done) begin
        cnt_div <= {CNT_WIDTH{1'b0}};
      end else begin
        cnt_div <= cnt_div + 1;
      end
    end
  end
  
  assign cnt_done = (cnt_div == DIV_FACTOR-1) ? 1'b1 : 1'b0;
  
  always @(posedge clk or posedge rst) begin
    if(rst) begin
      clk_reg <= 1'b0;
    end else if(en_sync & cnt_done) begin
      clk_reg <= ~clk_reg;
    end
  end
  











  
  assign clk_out = clk_reg;
  
endmodule