data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v
1: b"%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:11: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(21) (clk,reset,clk_count);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:12: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(17) (clk,reset,clk_sel);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:15: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select #(2) (clk_sel,reset,seg7_sel);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:23: syntax error, unexpected '(', expecting IDENTIFIER\ncount_0_9 (clk,reset,enable,carry0,count0_out);\n           ^~~\n%Error: Exiting due to 4 error(s)\n"
module freq_div(clk_in, reset, clk_out);
parameter exp = 20;   
input clk_in, reset;
output clk_out;
reg[exp-1:0] divider;
integer i;
assign clk_out= divider[exp-1];
always@ (posedge clk_in or posedge reset)
begin
if(reset)
for(i=0; i < exp; i=i+1)
divider[i] = 1'b0;
else
divider = divider+ 1'b1;
end
endmodule
module freq_div(clk_in, reset, clk_out);

parameter exp = 20;   
input clk_in, reset;
output clk_out;
reg[exp-1:0] divider;
integer i;
assign clk_out= divider[exp-1];
always@ (posedge clk_in or posedge reset)
begin
if(reset)
for(i=0; i < exp; i=i+1)
divider[i] = 1'b0;
else
divider = divider+ 1'b1;
end
endmodule