data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:34: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ALU\'\nmodule ALU(a, b, s, r, zero, overflow, negative);\n       ^~~\n                                                                           : ... Top module \'MUL\'\nmodule MUL(a, b, r, sign);\n       ^~~\n                                                                           : ... Top module \'DIV\'\nmodule DIV(a, b, q, r, sign, dbz);\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:113: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n    assign q_abs = ((!(d00 < b_abs)) << 5\'d00) + ((!(d01 < b_abs)) << 5\'d01) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:113: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n    assign q_abs = ((!(d00 < b_abs)) << 5\'d00) + ((!(d01 < b_abs)) << 5\'d01) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:114: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d02 < b_abs)) << 5\'d02) + ((!(d03 < b_abs)) << 5\'d03) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:114: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d02 < b_abs)) << 5\'d02) + ((!(d03 < b_abs)) << 5\'d03) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:115: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d04 < b_abs)) << 5\'d04) + ((!(d05 < b_abs)) << 5\'d05) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:115: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d04 < b_abs)) << 5\'d04) + ((!(d05 < b_abs)) << 5\'d05) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:116: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d06 < b_abs)) << 5\'d06) + ((!(d07 < b_abs)) << 5\'d07) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:116: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d06 < b_abs)) << 5\'d06) + ((!(d07 < b_abs)) << 5\'d07) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:117: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d08 < b_abs)) << 5\'d08) + ((!(d09 < b_abs)) << 5\'d09) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:117: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d08 < b_abs)) << 5\'d08) + ((!(d09 < b_abs)) << 5\'d09) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:118: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d10 < b_abs)) << 5\'d10) + ((!(d11 < b_abs)) << 5\'d11) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:118: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d10 < b_abs)) << 5\'d10) + ((!(d11 < b_abs)) << 5\'d11) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:119: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d12 < b_abs)) << 5\'d12) + ((!(d13 < b_abs)) << 5\'d13) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:119: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d12 < b_abs)) << 5\'d12) + ((!(d13 < b_abs)) << 5\'d13) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:120: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d14 < b_abs)) << 5\'d14) + ((!(d15 < b_abs)) << 5\'d15) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:120: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d14 < b_abs)) << 5\'d14) + ((!(d15 < b_abs)) << 5\'d15) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:121: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d16 < b_abs)) << 5\'d16) + ((!(d17 < b_abs)) << 5\'d17) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:121: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d16 < b_abs)) << 5\'d16) + ((!(d17 < b_abs)) << 5\'d17) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:122: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d18 < b_abs)) << 5\'d18) + ((!(d19 < b_abs)) << 5\'d19) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:122: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d18 < b_abs)) << 5\'d18) + ((!(d19 < b_abs)) << 5\'d19) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:123: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d20 < b_abs)) << 5\'d20) + ((!(d21 < b_abs)) << 5\'d21) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:123: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d20 < b_abs)) << 5\'d20) + ((!(d21 < b_abs)) << 5\'d21) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:124: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d22 < b_abs)) << 5\'d22) + ((!(d23 < b_abs)) << 5\'d23) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:124: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d22 < b_abs)) << 5\'d22) + ((!(d23 < b_abs)) << 5\'d23) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:125: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d24 < b_abs)) << 5\'d24) + ((!(d25 < b_abs)) << 5\'d25) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:125: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d24 < b_abs)) << 5\'d24) + ((!(d25 < b_abs)) << 5\'d25) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:126: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d26 < b_abs)) << 5\'d26) + ((!(d27 < b_abs)) << 5\'d27) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:126: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d26 < b_abs)) << 5\'d26) + ((!(d27 < b_abs)) << 5\'d27) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:127: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d28 < b_abs)) << 5\'d28) + ((!(d29 < b_abs)) << 5\'d29) +\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:127: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d28 < b_abs)) << 5\'d28) + ((!(d29 < b_abs)) << 5\'d29) +\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:128: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d30 < b_abs)) << 5\'d30) + ((!(d31 < b_abs)) << 5\'d31);\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:128: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s LOGNOT generates 1 bits.\n                                                                         : ... In instance DIV\n                   ((!(d30 < b_abs)) << 5\'d30) + ((!(d31 < b_abs)) << 5\'d31);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:25: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LTS generates 1 bits.\n                                                                        : ... In instance ALU\n              (s == 4\'b1011 ? $signed(a) < $signed(b) :\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/MIPS/CPU54/ALU.v:26: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LT generates 1 bits.\n                                                                        : ... In instance ALU\n              (s == 4\'b1010 ? a < b :\n                            ^\n%Error: Exiting due to 35 warning(s)\n'
module MUL(a, b, r, sign);
    input [31:0] a;
    input [31:0] b;
    input sign;
    output [63:0] r;
    wire [31:0] a_abs;
    wire [31:0] b_abs;
    wire [63:0] r_abs;
    assign a_abs = sign & a[31] ? -a : a;
    assign b_abs = sign & b[31] ? -b : b;
    assign r_abs =
        ((b_abs[00] ? {32'b0, a_abs}        : 64'b0) + (b_abs[01] ? {31'b0, a_abs, 01'b0} : 64'b0) +
         (b_abs[02] ? {30'b0, a_abs, 02'b0} : 64'b0) + (b_abs[03] ? {29'b0, a_abs, 03'b0} : 64'b0) +
         (b_abs[04] ? {28'b0, a_abs, 04'b0} : 64'b0) + (b_abs[05] ? {27'b0, a_abs, 05'b0} : 64'b0) +
         (b_abs[06] ? {26'b0, a_abs, 06'b0} : 64'b0) + (b_abs[07] ? {25'b0, a_abs, 07'b0} : 64'b0) +
         (b_abs[08] ? {24'b0, a_abs, 08'b0} : 64'b0) + (b_abs[09] ? {23'b0, a_abs, 09'b0} : 64'b0) +
         (b_abs[10] ? {22'b0, a_abs, 10'b0} : 64'b0) + (b_abs[11] ? {21'b0, a_abs, 11'b0} : 64'b0) +
         (b_abs[12] ? {20'b0, a_abs, 12'b0} : 64'b0) + (b_abs[13] ? {19'b0, a_abs, 13'b0} : 64'b0) +
         (b_abs[14] ? {18'b0, a_abs, 14'b0} : 64'b0) + (b_abs[15] ? {17'b0, a_abs, 15'b0} : 64'b0) +
         (b_abs[16] ? {16'b0, a_abs, 16'b0} : 64'b0) + (b_abs[17] ? {15'b0, a_abs, 17'b0} : 64'b0) +
         (b_abs[18] ? {14'b0, a_abs, 18'b0} : 64'b0) + (b_abs[19] ? {13'b0, a_abs, 19'b0} : 64'b0) +
         (b_abs[20] ? {12'b0, a_abs, 20'b0} : 64'b0) + (b_abs[21] ? {11'b0, a_abs, 21'b0} : 64'b0) +
         (b_abs[22] ? {10'b0, a_abs, 22'b0} : 64'b0) + (b_abs[23] ? {09'b0, a_abs, 23'b0} : 64'b0) +
         (b_abs[24] ? {08'b0, a_abs, 24'b0} : 64'b0) + (b_abs[25] ? {07'b0, a_abs, 25'b0} : 64'b0) +
         (b_abs[26] ? {06'b0, a_abs, 26'b0} : 64'b0) + (b_abs[27] ? {05'b0, a_abs, 27'b0} : 64'b0) +
         (b_abs[28] ? {04'b0, a_abs, 28'b0} : 64'b0) + (b_abs[29] ? {03'b0, a_abs, 29'b0} : 64'b0) +
         (b_abs[30] ? {02'b0, a_abs, 30'b0} : 64'b0) + (b_abs[31] ? {01'b0, a_abs, 31'b0} : 64'b0));
    assign r = sign & (a[31] ^ b[31]) ? -r_abs : r_abs;
endmodule
module MUL(a, b, r, sign);

    input [31:0] a;
    input [31:0] b;
    input sign;
    output [63:0] r;
    wire [31:0] a_abs;
    wire [31:0] b_abs;
    wire [63:0] r_abs;
    assign a_abs = sign & a[31] ? -a : a;
    assign b_abs = sign & b[31] ? -b : b;
    assign r_abs =
        ((b_abs[00] ? {32'b0, a_abs}        : 64'b0) + (b_abs[01] ? {31'b0, a_abs, 01'b0} : 64'b0) +
         (b_abs[02] ? {30'b0, a_abs, 02'b0} : 64'b0) + (b_abs[03] ? {29'b0, a_abs, 03'b0} : 64'b0) +
         (b_abs[04] ? {28'b0, a_abs, 04'b0} : 64'b0) + (b_abs[05] ? {27'b0, a_abs, 05'b0} : 64'b0) +
         (b_abs[06] ? {26'b0, a_abs, 06'b0} : 64'b0) + (b_abs[07] ? {25'b0, a_abs, 07'b0} : 64'b0) +
         (b_abs[08] ? {24'b0, a_abs, 08'b0} : 64'b0) + (b_abs[09] ? {23'b0, a_abs, 09'b0} : 64'b0) +
         (b_abs[10] ? {22'b0, a_abs, 10'b0} : 64'b0) + (b_abs[11] ? {21'b0, a_abs, 11'b0} : 64'b0) +
         (b_abs[12] ? {20'b0, a_abs, 12'b0} : 64'b0) + (b_abs[13] ? {19'b0, a_abs, 13'b0} : 64'b0) +
         (b_abs[14] ? {18'b0, a_abs, 14'b0} : 64'b0) + (b_abs[15] ? {17'b0, a_abs, 15'b0} : 64'b0) +
         (b_abs[16] ? {16'b0, a_abs, 16'b0} : 64'b0) + (b_abs[17] ? {15'b0, a_abs, 17'b0} : 64'b0) +
         (b_abs[18] ? {14'b0, a_abs, 18'b0} : 64'b0) + (b_abs[19] ? {13'b0, a_abs, 19'b0} : 64'b0) +
         (b_abs[20] ? {12'b0, a_abs, 20'b0} : 64'b0) + (b_abs[21] ? {11'b0, a_abs, 21'b0} : 64'b0) +
         (b_abs[22] ? {10'b0, a_abs, 22'b0} : 64'b0) + (b_abs[23] ? {09'b0, a_abs, 23'b0} : 64'b0) +
         (b_abs[24] ? {08'b0, a_abs, 24'b0} : 64'b0) + (b_abs[25] ? {07'b0, a_abs, 25'b0} : 64'b0) +
         (b_abs[26] ? {06'b0, a_abs, 26'b0} : 64'b0) + (b_abs[27] ? {05'b0, a_abs, 27'b0} : 64'b0) +
         (b_abs[28] ? {04'b0, a_abs, 28'b0} : 64'b0) + (b_abs[29] ? {03'b0, a_abs, 29'b0} : 64'b0) +
         (b_abs[30] ? {02'b0, a_abs, 30'b0} : 64'b0) + (b_abs[31] ? {01'b0, a_abs, 31'b0} : 64'b0));
    assign r = sign & (a[31] ^ b[31]) ? -r_abs : r_abs;
endmodule