data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G.v
data/verilator_xmls/5862f122-b3af-4764-91ed-9c1e42ed3018.xml
module AND_G(A,B,C);

input A,B;
output C;

assign C= A&B;
endmodule
module AND_G(A,B,C);


input A,B;
output C;

assign C= A&B;
endmodule