data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/Control_Unit.v
data/verilator_xmls/fa16a414-1a7a-4e6c-9608-9dcfb445dbc0.xml
module Control_Unit(
input [3:0]op,
input ctrl,
input [1:0]re_config,
output jmp,eop,ctrl_sel,mem_wr,wr_bk_sel,
output [1:0]reg_wr,
output [3:0]alu_sel,
output [1:0]dir_val
    );

wire w1,w2,w3,w4,k,shiftv;


assign w1=(op[3]&~op[2]&op[1]&op[0]);
assign w2=(op[3]&op[2]&~op[1]&op[0]);
assign w3=(op[3]&op[2]&op[1]&~op[0]);
assign w4=(op[3]&op[2]&op[1]&op[0]);
assign k=w1|w2|w3|w4;

assign shiftv=re_config[1]&re_config[0]&op[3]&op[2]&~op[1]&~op[0];
assign reg_wr[1]=(re_config[1]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);
assign reg_wr[0]=(re_config[0]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);

assign mem_wr=w1;


assign wr_bk_sel=(op[3]&~op[2]&op[1]&~op[0]);


assign ctrl_sel=ctrl&~w3;


assign jmp=(op[3]&op[2]&~op[1]&op[0]);


assign eop=(op[3]&op[2]&op[1]&op[0]);


assign dir_val[1]=op[3]&~op[2]&~op[1]&op[0]&ctrl;
assign dir_val[0]=op[3]&op[2]&~op[1]&~op[0];


assign alu_sel=(op&{4{~w3}})|({~op[3],op[2],op[1],~op[0]}&{4{w3}});

endmodule
module Control_Unit(
input [3:0]op,
input ctrl,
input [1:0]re_config,
output jmp,eop,ctrl_sel,mem_wr,wr_bk_sel,
output [1:0]reg_wr,
output [3:0]alu_sel,
output [1:0]dir_val
    );


wire w1,w2,w3,w4,k,shiftv;


assign w1=(op[3]&~op[2]&op[1]&op[0]);
assign w2=(op[3]&op[2]&~op[1]&op[0]);
assign w3=(op[3]&op[2]&op[1]&~op[0]);
assign w4=(op[3]&op[2]&op[1]&op[0]);
assign k=w1|w2|w3|w4;

assign shiftv=re_config[1]&re_config[0]&op[3]&op[2]&~op[1]&~op[0];
assign reg_wr[1]=(re_config[1]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);
assign reg_wr[0]=(re_config[0]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);

assign mem_wr=w1;


assign wr_bk_sel=(op[3]&~op[2]&op[1]&~op[0]);


assign ctrl_sel=ctrl&~w3;


assign jmp=(op[3]&op[2]&~op[1]&op[0]);


assign eop=(op[3]&op[2]&op[1]&op[0]);


assign dir_val[1]=op[3]&~op[2]&~op[1]&op[0]&ctrl;
assign dir_val[0]=op[3]&op[2]&~op[1]&~op[0];


assign alu_sel=(op&{4{~w3}})|({~op[3],op[2],op[1],~op[0]}&{4{w3}});

endmodule