data/full_repos/permissive/424292861/guia9/Exemplo_0902.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #12 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #3 signal = 1\'b0; \n  ^\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:40: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n always @(posedge clock & on) begin\n                        ^\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:60: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Exemplo_0802.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:61: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1,clock0,p1,p,t1);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #060 p = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #120 p = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #180 p = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #240 p = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #300 p = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #360 p = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/424292861/guia9/Exemplo_0902.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #376  $finish;\n  ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module exemplo_0902;
	wire clock0;
	clock CLOCK1(clock0);
	reg p;
	wire p1,t1;
	pulse PULSE1(p1,clock0);
	trigger TRIGGER1(t1,p,clock0);
	initial begin
		p = 1'b0;
	end
	
	initial begin
		$dumpfile("Exemplo_0802.vcd");
		$dumpvars(1,clock0,p1,p,t1);
		
		#060	p = 1'b1;
		#120	p = 1'b0;
		#180	p = 1'b1;
		#240	p = 1'b0;
		#300	p = 1'b1;
		#360	p = 1'b0;
		#376 	$finish;
	end
endmodule
module exemplo_0902;

	wire clock0;
	clock CLOCK1(clock0);
	reg p;
	wire p1,t1;
	pulse PULSE1(p1,clock0);
	trigger TRIGGER1(t1,p,clock0);
	initial begin
		p = 1'b0;
	end
	
	initial begin
		$dumpfile("Exemplo_0802.vcd");
		$dumpvars(1,clock0,p1,p,t1);
		
		#060	p = 1'b1;
		#120	p = 1'b0;
		#180	p = 1'b1;
		#240	p = 1'b0;
		#300	p = 1'b1;
		#360	p = 1'b0;
		#376 	$finish;
	end
endmodule