data/full_repos/permissive/423547971/FPGA Projects/Star Wars Imperial March Song/fH_698Hz.v
1: b'%Error: Cannot find file containing module: Projects/Star\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Star\n             data/full_repos/permissive/423547971/FPGA/Projects/Star.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Star.sv\n             Projects/Star\n             Projects/Star.v\n             Projects/Star.sv\n             obj_dir/Projects/Star\n             obj_dir/Projects/Star.v\n             obj_dir/Projects/Star.sv\n%Error: Cannot find file containing module: Wars\n%Error: Cannot find file containing module: Imperial\n%Error: Cannot find file containing module: March\n%Error: Cannot find file containing module: Song,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Song/fH_698Hz.v\n%Error: Exiting due to 7 error(s)\n'
module fH_698Hz(
    input clk_100MHz,
    output o_698Hz    
    );
    

    reg r_698Hz;
    reg [16:0] r_counter = 0;
    
    always @(posedge clk_100MHz)
        if(r_counter == 17'd71_633) begin
            r_counter <= 0;
            r_698Hz <= ~r_698Hz;
            end
        else
            r_counter <= r_counter + 1;

    assign o_698Hz = r_698Hz;
    
endmodule
module fH_698Hz(
    input clk_100MHz,
    output o_698Hz    
    );

    

    reg r_698Hz;
    reg [16:0] r_counter = 0;
    
    always @(posedge clk_100MHz)
        if(r_counter == 17'd71_633) begin
            r_counter <= 0;
            r_698Hz <= ~r_698Hz;
            end
        else
            r_counter <= r_counter + 1;

    assign o_698Hz = r_698Hz;
    
endmodule