data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Latches and Flip-Flops/Create circuit from truth table.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Create\n%Error: Cannot find file containing module: circuit\n%Error: Cannot find file containing module: from\n%Error: Cannot find file containing module: truth\n%Error: Cannot find file containing module: table.v\n%Error: Exiting due to 9 error(s)\n'
module top_module (
    input clk,
    input j,
    input k,
    output Q); 

    always @(posedge clk) begin
        if (j == 0) begin
            if (k == 1) begin
                Q <= 1'b0;
            end
        end

        if (j == 1) begin
            if (k == 0) begin
                Q <= 1;
            end else begin
                Q <= !Q;
            end
        end
    end
endmodule
module top_module (
    input clk,
    input j,
    input k,
    output Q);
 

    always @(posedge clk) begin
        if (j == 0) begin
            if (k == 1) begin
                Q <= 1'b0;
            end
        end

        if (j == 1) begin
            if (k == 0) begin
                Q <= 1;
            end else begin
                Q <= !Q;
            end
        end
    end
endmodule