data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:60: Signal definition not found, creating implicitly: \'BtnC\'\n                                                                                                        : ... Suggested alternative: \'btnC\'\n    assign set0[0] = BtnC | bout[3];\n                     ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:65: Signal definition not found, creating implicitly: \'BtnU\'\n                                                                                                        : ... Suggested alternative: \'BtnC\'\n    assign set9[0] = BtnU | cout[3];\n                     ^~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:70: Cannot find file containing module: \'Button\'\n    Button bc(BtnC,btnC,clk);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/Button\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/Button.v\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new,data/full_repos/permissive/423958267/Button.sv\n             Button\n             Button.v\n             Button.sv\n             obj_dir/Button\n             obj_dir/Button.v\n             obj_dir/Button.sv\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:71: Cannot find file containing module: \'Button\'\n    Button bu(BtnU,btnU,clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:73: Cannot find file containing module: \'Switch\'\n    Switch s0(SW[0],sw[0],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:74: Cannot find file containing module: \'Switch\'\n    Switch s1(SW[1],sw[1],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:75: Cannot find file containing module: \'Switch\'\n    Switch s2(SW[2],sw[2],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:76: Cannot find file containing module: \'Switch\'\n    Switch s3(SW[3],sw[3],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:77: Cannot find file containing module: \'Switch\'\n    Switch s4(SW[4],sw[4],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:78: Cannot find file containing module: \'Switch\'\n    Switch s5(SW[5],sw[5],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:79: Cannot find file containing module: \'Switch\'\n    Switch s6(SW[6],sw[6],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:80: Cannot find file containing module: \'Switch\'\n    Switch s7(SW[7],sw[7],clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:92: Cannot find file containing module: \'OneDigitBCDCounter\'\n    OneDigitBCDCounter D0(digit0[3],digit0[2],digit0[1],digit0[0],cout[0],bout[0],up[0],down[0],set9[0],set0[0],clk);\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:93: Cannot find file containing module: \'OneDigitBCDCounter\'\n    OneDigitBCDCounter D1(digit1[3],digit1[2],digit1[1],digit1[0],cout[1],bout[1],up[1],down[1],set9[1],set0[1],clk);\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:94: Cannot find file containing module: \'OneDigitBCDCounter\'\n    OneDigitBCDCounter D2(digit2[3],digit2[2],digit2[1],digit2[0],cout[2],bout[2],up[2],down[2],set9[2],set0[2],clk);\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:95: Cannot find file containing module: \'OneDigitBCDCounter\'\n    OneDigitBCDCounter D3(digit3[3],digit3[2],digit3[1],digit3[0],cout[3],bout[3],up[3],down[3],set9[3],set0[3],clk);\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:102: Cannot find file containing module: \'Counter\'\n    Counter #(20) c(counter,nreset,clk);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:106: Cannot find file containing module: \'Mux4to1\'\n    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:107: Cannot find file containing module: \'Decoder4\'\n    Decoder4 dec(sel,q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/imports/new/main.v:108: Cannot find file containing module: \'HexTo7Seg\'\n    HexTo7Seg h(seg,d);\n    ^~~~~~~~~\n%Error: Exiting due to 18 error(s), 2 warning(s)\n'
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input btnC,
    input btnU,
    input [7:0] sw,
    input clk
);
    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [3:0] coutP,boutP,cout,bout,up,down,set0,set9;
    wire [7:0] SW;

    reg nreset;
    wire max, min;
    
    assign max = digit0 == 4'b1001 && digit1 == 4'b1001 && digit2 == 4'b1001 && digit3 == 4'b1001;
    assign min = digit0 == 4'b0000 && digit1 == 4'b0000 && digit2 == 4'b0000 && digit3 == 4'b0000;

    assign up[0] = SW[0] & ~max;
    assign down[0] = SW[1] & ~min;

    assign up[1] = (SW[2] | cout[0]) & ~max;
    assign down[1] = (SW[3] | bout[0]) & ~min;

    assign up[2] = (SW[4] | cout[1]) & ~max;
    assign down[2] = (SW[5] | bout[1]) & ~min;

    assign up[3] = (SW[6] | cout[2]) & ~max;
    assign down[3] = (SW[7] | bout[2]) & ~min;

    assign set0[0] = BtnC | bout[3];
    assign set0[1] = BtnC | bout[3];
    assign set0[2] = BtnC | bout[3];
    assign set0[3] = BtnC | bout[3];

    assign set9[0] = BtnU | cout[3];
    assign set9[1] = BtnU | cout[3];
    assign set9[2] = BtnU | cout[3];
    assign set9[3] = BtnU | cout[3];

    Button bc(BtnC,btnC,clk);
    Button bu(BtnU,btnU,clk);
    
    Switch s0(SW[0],sw[0],clk);
    Switch s1(SW[1],sw[1],clk);
    Switch s2(SW[2],sw[2],clk);
    Switch s3(SW[3],sw[3],clk);
    Switch s4(SW[4],sw[4],clk);
    Switch s5(SW[5],sw[5],clk);
    Switch s6(SW[6],sw[6],clk);
    Switch s7(SW[7],sw[7],clk);











    OneDigitBCDCounter D0(digit0[3],digit0[2],digit0[1],digit0[0],cout[0],bout[0],up[0],down[0],set9[0],set0[0],clk);
    OneDigitBCDCounter D1(digit1[3],digit1[2],digit1[1],digit1[0],cout[1],bout[1],up[1],down[1],set9[1],set0[1],clk);
    OneDigitBCDCounter D2(digit2[3],digit2[2],digit2[1],digit2[0],cout[2],bout[2],up[2],down[2],set9[2],set0[2],clk);
    OneDigitBCDCounter D3(digit3[3],digit3[2],digit3[1],digit3[0],cout[3],bout[3],up[3],down[3],set9[3],set0[3],clk);

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);



    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input btnC,
    input btnU,
    input [7:0] sw,
    input clk
);

    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [3:0] coutP,boutP,cout,bout,up,down,set0,set9;
    wire [7:0] SW;

    reg nreset;
    wire max, min;
    
    assign max = digit0 == 4'b1001 && digit1 == 4'b1001 && digit2 == 4'b1001 && digit3 == 4'b1001;
    assign min = digit0 == 4'b0000 && digit1 == 4'b0000 && digit2 == 4'b0000 && digit3 == 4'b0000;

    assign up[0] = SW[0] & ~max;
    assign down[0] = SW[1] & ~min;

    assign up[1] = (SW[2] | cout[0]) & ~max;
    assign down[1] = (SW[3] | bout[0]) & ~min;

    assign up[2] = (SW[4] | cout[1]) & ~max;
    assign down[2] = (SW[5] | bout[1]) & ~min;

    assign up[3] = (SW[6] | cout[2]) & ~max;
    assign down[3] = (SW[7] | bout[2]) & ~min;

    assign set0[0] = BtnC | bout[3];
    assign set0[1] = BtnC | bout[3];
    assign set0[2] = BtnC | bout[3];
    assign set0[3] = BtnC | bout[3];

    assign set9[0] = BtnU | cout[3];
    assign set9[1] = BtnU | cout[3];
    assign set9[2] = BtnU | cout[3];
    assign set9[3] = BtnU | cout[3];

    Button bc(BtnC,btnC,clk);
    Button bu(BtnU,btnU,clk);
    
    Switch s0(SW[0],sw[0],clk);
    Switch s1(SW[1],sw[1],clk);
    Switch s2(SW[2],sw[2],clk);
    Switch s3(SW[3],sw[3],clk);
    Switch s4(SW[4],sw[4],clk);
    Switch s5(SW[5],sw[5],clk);
    Switch s6(SW[6],sw[6],clk);
    Switch s7(SW[7],sw[7],clk);











    OneDigitBCDCounter D0(digit0[3],digit0[2],digit0[1],digit0[0],cout[0],bout[0],up[0],down[0],set9[0],set0[0],clk);
    OneDigitBCDCounter D1(digit1[3],digit1[2],digit1[1],digit1[0],cout[1],bout[1],up[1],down[1],set9[1],set0[1],clk);
    OneDigitBCDCounter D2(digit2[3],digit2[2],digit2[1],digit2[0],cout[2],bout[2],up[2],down[2],set9[2],set0[2],clk);
    OneDigitBCDCounter D3(digit3[3],digit3[2],digit3[1],digit3[0],cout[3],bout[3],up[3],down[3],set9[3],set0[3],clk);

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);



    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule