data/full_repos/permissive/450205124/Assignment1/Q4-8-3-bit-Priority-Encoder/A1Q4_priority_encoder_8_3.v
data/verilator_xmls/e89ce72a-bbfa-4b32-a73c-a72ccd42790d.xml
module priority_encoder_8_3(out, inp, enable);
output [2:0] out;
input [7:0] inp;
input enable;

assign out[0] = enable && ~inp[0] && (inp[1] || (~inp[2] && (inp[3] || (~inp[4] && (inp[5] || (~inp[6] && (inp[7]))))))); 
assign out[1] = enable && (~inp[0] && ~inp[1] && (inp[2] || inp[3] || (~inp[4] && ~inp[5] && (inp[6] || inp[7]))));
assign out[2] = enable && ~inp[0] && ~inp[1] && ~inp[2] && ~inp[3];

endmodule
module priority_encoder_8_3(out, inp, enable);

output [2:0] out;
input [7:0] inp;
input enable;

assign out[0] = enable && ~inp[0] && (inp[1] || (~inp[2] && (inp[3] || (~inp[4] && (inp[5] || (~inp[6] && (inp[7]))))))); 
assign out[1] = enable && (~inp[0] && ~inp[1] && (inp[2] || inp[3] || (~inp[4] && ~inp[5] && (inp[6] || inp[7]))));
assign out[2] = enable && ~inp[0] && ~inp[1] && ~inp[2] && ~inp[3];

endmodule