data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v
1: b'%Error: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:14: Unsupported or unknown PLI call: $dumpvars\n                $dumpvars(0, tb_DEC_INPUT_KEY);\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:15: Unsupported or unknown PLI call: $dumpfile\n                $dumpfile("my.vcd");\n                ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:19: Unsupported: Ignoring delay on this delayed statement.\n                        #5 clk = ~clk;\n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #4\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #12\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/CONTROLLER/tb_DEC_INPUT_KEY.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_DEC_INPUT_KEY;

	reg input_key;
	reg valid_cmd;
	reg reset;
	reg clk;
	wire active;
	wire mode;

	DEC_INPUT_KEY DUT (input_key, valid_cmd, reset, clk, active, mode);

	initial begin

                $dumpvars(0, tb_DEC_INPUT_KEY);
                $dumpfile("my.vcd");

                clk = 0;
                forever
                        #5 clk = ~clk;

        end

	
	initial begin

		reset = 1;
		valid_cmd = 0;
		input_key = 0;
		#4
		display;

		reset = 0;
		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		#300
		$finish;

	end


	task display;
		$display("reset = %0h, clk = %0h, valid = %0h, in = %0h, active = %0h, mode = %0h", reset, clk, valid_cmd, input_key, active, mode);
	endtask

endmodule
module tb_DEC_INPUT_KEY;


	reg input_key;
	reg valid_cmd;
	reg reset;
	reg clk;
	wire active;
	wire mode;

	DEC_INPUT_KEY DUT (input_key, valid_cmd, reset, clk, active, mode);

	initial begin

                $dumpvars(0, tb_DEC_INPUT_KEY);
                $dumpfile("my.vcd");

                clk = 0;
                forever
                        #5 clk = ~clk;

        end

	
	initial begin

		reset = 1;
		valid_cmd = 0;
		input_key = 0;
		#4
		display;

		reset = 0;
		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		valid_cmd = 1;
		input_key = 1;
		#12
		display;

		valid_cmd = 1;
		input_key = 0;
		#12
		display;

		#300
		$finish;

	end


	task display;
		$display("reset = %0h, clk = %0h, valid = %0h, in = %0h, active = %0h, mode = %0h", reset, clk, valid_cmd, input_key, active, mode);
	endtask

endmodule