data/full_repos/permissive/500128826/HDLBits/Circuits/Building Larger Circuits/review2015_fsmseq/top_module.v
1: b'%Error: Cannot find file containing module: Larger\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.sv\n             Larger\n             Larger.v\n             Larger.sv\n             obj_dir/Larger\n             obj_dir/Larger.v\n             obj_dir/Larger.sv\n%Error: Cannot find file containing module: Circuits/review2015_fsmseq,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Building\n%Error: Cannot find file containing module: Circuits/review2015_fsmseq/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire data,
    output reg  start_shifting
);

  parameter STATE_X0 = 3'b000;
  parameter STATE_X1 = 3'b001;
  parameter STATE_X2 = 3'b010;
  parameter STATE_X3 = 3'b011;
  parameter STATE_F0 = 3'b100;
  parameter STATE_ILLEGAL = 3'b111;

  reg [2:0] state = STATE_X0, next_state = STATE_X0;


  always @(*) begin
    casez ({
      data, state
    })
      {1'b0, STATE_X0} : next_state = STATE_X0;
      {1'b1, STATE_X0} : next_state = STATE_X1;
      {1'b0, STATE_X1} : next_state = STATE_X0;
      {1'b1, STATE_X1} : next_state = STATE_X2;
      {1'b0, STATE_X2} : next_state = STATE_X3;
      {1'b1, STATE_X2} : next_state = STATE_X2;
      {1'b0, STATE_X3} : next_state = STATE_X0;
      {1'b1, STATE_X3} : next_state = STATE_F0;
      {1'bz, STATE_F0} : next_state = STATE_F0;
      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_X0;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case (state)
      STATE_X0, STATE_X1, STATE_X2, STATE_X3: start_shifting = 1'b0;
      STATE_F0: start_shifting = 1'b1;
      default: start_shifting = 1'bx;
    endcase
  end

endmodule
module top_module (
    input  wire clk,
    input  wire reset,
    input  wire data,
    output reg  start_shifting
);


  parameter STATE_X0 = 3'b000;
  parameter STATE_X1 = 3'b001;
  parameter STATE_X2 = 3'b010;
  parameter STATE_X3 = 3'b011;
  parameter STATE_F0 = 3'b100;
  parameter STATE_ILLEGAL = 3'b111;

  reg [2:0] state = STATE_X0, next_state = STATE_X0;


  always @(*) begin
    casez ({
      data, state
    })
      {1'b0, STATE_X0} : next_state = STATE_X0;
      {1'b1, STATE_X0} : next_state = STATE_X1;
      {1'b0, STATE_X1} : next_state = STATE_X0;
      {1'b1, STATE_X1} : next_state = STATE_X2;
      {1'b0, STATE_X2} : next_state = STATE_X3;
      {1'b1, STATE_X2} : next_state = STATE_X2;
      {1'b0, STATE_X3} : next_state = STATE_X0;
      {1'b1, STATE_X3} : next_state = STATE_F0;
      {1'bz, STATE_F0} : next_state = STATE_F0;
      default: next_state = STATE_ILLEGAL;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= STATE_X0;
    else if (clk) state <= next_state;
  end


  always @(*) begin
    case (state)
      STATE_X0, STATE_X1, STATE_X2, STATE_X3: start_shifting = 1'b0;
      STATE_F0: start_shifting = 1'b1;
      default: start_shifting = 1'bx;
    endcase
  end

endmodule