data/full_repos/permissive/427220253/Quartus_project/mem_test_sm.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/427220253/Quartus_project/mem_test_sm.sv:200: Operator ADD expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                                       : ... In instance mem_test_sm\n      bit_flip_count_r <= bit_flip_count_r + {{31{1\'b0}},1\'b1};\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/427220253/Quartus_project/mem_test_sm.sv:274: Cannot find file containing module: \'mem_loader\'\n mem_loader mem_loader_inst (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427220253/Quartus_project,data/full_repos/permissive/427220253/mem_loader\n             data/full_repos/permissive/427220253/Quartus_project,data/full_repos/permissive/427220253/mem_loader.v\n             data/full_repos/permissive/427220253/Quartus_project,data/full_repos/permissive/427220253/mem_loader.sv\n             mem_loader\n             mem_loader.v\n             mem_loader.sv\n             obj_dir/mem_loader\n             obj_dir/mem_loader.v\n             obj_dir/mem_loader.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mem_test_sm
	#(
	  parameter ADDR_WIDTH = 'd64,
	  parameter WORD_WIDTH = 'd64,
	  parameter ROW_WIDTH  = 'd12,
	  parameter ROW_POS    = 'd10,
	  parameter COL_WIDTH  = 'd10,
	  parameter COL_POS	  = 'd1,
	  parameter MEM_TEST_SM_START   			= 4'd0,
	  parameter MEM_TEST_SM_LOAD_COUNT		= 4'd8,
	  parameter MEM_TEST_SM_LOAD_ADDRESS	= 4'd9,
	  parameter MEM_TEST_SM_LOAD_PATTERN	= 4'd10,
	  parameter MEM_TEST_SM_INITIALIZE_MEM	= 4'd1,
	  parameter MEM_TEST_SM_ADDRESS_RESET_0= 4'd6,
	  parameter MEM_TEST_SM_HAMMER_MEM		= 4'd2,
	  parameter MEM_TEST_SM_ADDRESS_RESET_1= 4'd7,
	  parameter MEM_TEST_SM_READ_MEM			= 4'd3,
	  parameter MEM_TEST_SM_TALLY_MEM		= 4'd4,
	  parameter MEM_TEST_SM_STOR_FLIPS		= 4'd11,
	  parameter MEM_TEST_SIG_FINISH			= 4'd12,
	  parameter MEM_TEST_SM_FINISH			= 4'd5
	)
	(
	

	input							clk,
	input							reset,
	input							wait_request,
	input							read_data_valid,
	input [WORD_WIDTH-1:0]  pattern_rb,
	

	output [ADDR_WIDTH-1:0] gen_address,
	output [WORD_WIDTH-1:0] gen_word,
	output						write,
	output						read,
	output [3:0]				state
	);
	

	logic [WORD_WIDTH-1:0]  pattern;
	logic [ADDR_WIDTH-1:0]  address;
	logic [31:0]            count;
	

	logic [63:0]				qdata;
	logic [4:0]					raddr;
	logic							wren;
	logic [63:0]				write_data;
	

	logic  [ADDR_WIDTH-1:0] gen_address_r;
	
	logic [31:0] count_r;
	logic [3:0]  state_r;
	logic 		 direction_r;
	logic [COL_WIDTH-1:0] word_r;
	logic [1:0]  word_q_r;
	

	logic  [63:0] 		bit_flip_count_r;
	logic					confirm;
	

	always_ff@(posedge clk) begin
		if(reset) begin
			gen_address_r 	  <= 'b0;
			count_r		  <= 'b0;
			state_r		  <= 'b0;
			word_r		  <= 'b0;
			word_q_r		  <= 'b0;
			bit_flip_count_r <= 'b0;
			raddr <= 'b0;
			wren  <= 'b0;
		end
		else begin

			case(state_r)
				MEM_TEST_SM_START: begin
					state_r <= MEM_TEST_SM_LOAD_COUNT;
				end
				MEM_TEST_SM_LOAD_COUNT: begin
					state_r <= MEM_TEST_SM_LOAD_ADDRESS;
				end
				MEM_TEST_SM_LOAD_ADDRESS: begin
					state_r <= MEM_TEST_SM_LOAD_PATTERN;
				end
				MEM_TEST_SM_LOAD_PATTERN: begin
					state_r <= MEM_TEST_SM_INITIALIZE_MEM;
				end
				MEM_TEST_SM_INITIALIZE_MEM: begin
					if((word_r == {COL_WIDTH{1'b1}}) & confirm) begin
						state_r <= MEM_TEST_SM_ADDRESS_RESET_0;
					end
					else begin
						state_r <= MEM_TEST_SM_INITIALIZE_MEM;
					end
				end
				MEM_TEST_SM_ADDRESS_RESET_0:begin
					state_r <= MEM_TEST_SM_HAMMER_MEM;
				end
				MEM_TEST_SM_HAMMER_MEM: begin
					if((count_r == count) & confirm) begin
						state_r <= MEM_TEST_SM_ADDRESS_RESET_1;
					end
					else begin
						state_r <= MEM_TEST_SM_HAMMER_MEM;
					end
				end
				MEM_TEST_SM_ADDRESS_RESET_1:begin
					state_r <= MEM_TEST_SM_READ_MEM;
				end
				MEM_TEST_SM_READ_MEM: begin
						if(confirm) begin
							state_r <= MEM_TEST_SM_TALLY_MEM;
						end
						else begin
							state_r <= MEM_TEST_SM_READ_MEM;
						end
				end
				MEM_TEST_SM_TALLY_MEM: begin
					if(word_q_r == 2'b11 & word_r == {COL_WIDTH{1'b1}}) begin
						state_r <= MEM_TEST_SIG_FINISH;
					end
					else if(word_q_r == 2'b11) begin
						state_r <= MEM_TEST_SM_READ_MEM;
					end
					else begin
						state_r <= MEM_TEST_SM_TALLY_MEM;
					end
				end
				MEM_TEST_SIG_FINISH: begin
					state_r <= MEM_TEST_SM_FINISH;
				end
				MEM_TEST_SM_FINISH: begin
					state_r <= MEM_TEST_SM_FINISH;
				end			
				default: begin
					state_r <= MEM_TEST_SM_FINISH;
				end
			endcase
			


			if(state_r == MEM_TEST_SM_INITIALIZE_MEM || state_r == MEM_TEST_SM_READ_MEM) begin
				gen_address_r[COL_WIDTH + COL_POS - 1 : COL_POS] <= word_r;
			end
			else if(state_r == MEM_TEST_SM_HAMMER_MEM) begin
				gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] <= direction_r ? (gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] - 1'b1) :
																									  (gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] + 1'b1);
			end
			else if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				gen_address_r <= gen_address_r;
			end
			else begin
				gen_address_r <= address;
			end

			if(state_r == MEM_TEST_SM_INITIALIZE_MEM | state_r == MEM_TEST_SM_READ_MEM | state_r == MEM_TEST_SM_TALLY_MEM) begin
				if(confirm & state_r != MEM_TEST_SM_TALLY_MEM) begin
					word_r <= word_r + {{(COL_WIDTH-1){1'b0}},1'b1};
				end
				else begin	
					word_r <= word_r;
				end
			end
			else begin
				word_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				word_q_r <= word_q_r + 2'b01;
			end
			else begin
				word_q_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_HAMMER_MEM) begin
				if(confirm) begin
					count_r <= count_r + 32'd1;
				end
				else begin
					count_r <= count_r;
				end
			end
			else begin
				count_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				for(int i = 0; i < (WORD_WIDTH/4); i++) begin
					if(pattern[i + (word_q_r * (WORD_WIDTH/4))] ^ pattern_rb[i + (word_q_r * (WORD_WIDTH/4))]) begin
						bit_flip_count_r <= bit_flip_count_r + {{31{1'b0}},1'b1};
					end
				end
			end
			else begin
				bit_flip_count_r <= bit_flip_count_r;
			end
			

			if(state_r == MEM_TEST_SM_START) begin
				raddr <= 5'b00000;
				address <= address;
				pattern <= pattern;
				count <= count;
			end
			else if(state_r == MEM_TEST_SM_LOAD_ADDRESS) begin
				raddr <= 5'b00001;
				address <= qdata[ADDR_WIDTH-1:0];
				count <= count;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SM_LOAD_COUNT) begin
				raddr <= 5'b00010;
				count <= qdata[31:0];
				address <= address;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SM_LOAD_PATTERN) begin
				pattern <= qdata[WORD_WIDTH-1:0];
				raddr <= raddr;
				count <= count;
				address <= address;
			end
			else if(state_r == MEM_TEST_SM_STOR_FLIPS)begin
				raddr <= 5'b00011;
				count <= count;
				address <= address;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SIG_FINISH) begin
				raddr <= 5'b00100;
				count <= count;
				address <= address;
				pattern <= pattern;
			end
			else begin
				raddr <= raddr;
				count <= count;
				address <= address;
				pattern <= pattern;
			end

			if(state_r == MEM_TEST_SM_STOR_FLIPS || state_r == MEM_TEST_SIG_FINISH) begin
				wren <= 1'b1;
			end
			else begin
				wren <= 1'b0;
			end
		end
	end
	

	assign direction_r = count_r[0];
	assign confirm = !(wait_request || (!read_data_valid & state_r == MEM_TEST_SM_READ_MEM));
	

	assign write = (state_r == MEM_TEST_SM_INITIALIZE_MEM);
	assign read  = (state_r == MEM_TEST_SM_READ_MEM || state_r == MEM_TEST_SM_HAMMER_MEM);
	assign gen_word = pattern;
	assign gen_address = gen_address_r;
	assign state = state_r;
	assign write_data = (state_r == MEM_TEST_SIG_FINISH) ? 'b1 : bit_flip_count_r;
	

	mem_loader	mem_loader_inst (
	.clock 		(clk),
	.data 		(write_data),
	.address 	(raddr),
	.wren 		(wren),
	.q 			(qdata)
	);
	
endmodule
module mem_test_sm
	#(
	  parameter ADDR_WIDTH = 'd64,
	  parameter WORD_WIDTH = 'd64,
	  parameter ROW_WIDTH  = 'd12,
	  parameter ROW_POS    = 'd10,
	  parameter COL_WIDTH  = 'd10,
	  parameter COL_POS	  = 'd1,
	  parameter MEM_TEST_SM_START   			= 4'd0,
	  parameter MEM_TEST_SM_LOAD_COUNT		= 4'd8,
	  parameter MEM_TEST_SM_LOAD_ADDRESS	= 4'd9,
	  parameter MEM_TEST_SM_LOAD_PATTERN	= 4'd10,
	  parameter MEM_TEST_SM_INITIALIZE_MEM	= 4'd1,
	  parameter MEM_TEST_SM_ADDRESS_RESET_0= 4'd6,
	  parameter MEM_TEST_SM_HAMMER_MEM		= 4'd2,
	  parameter MEM_TEST_SM_ADDRESS_RESET_1= 4'd7,
	  parameter MEM_TEST_SM_READ_MEM			= 4'd3,
	  parameter MEM_TEST_SM_TALLY_MEM		= 4'd4,
	  parameter MEM_TEST_SM_STOR_FLIPS		= 4'd11,
	  parameter MEM_TEST_SIG_FINISH			= 4'd12,
	  parameter MEM_TEST_SM_FINISH			= 4'd5
	)
	(
	

	input							clk,
	input							reset,
	input							wait_request,
	input							read_data_valid,
	input [WORD_WIDTH-1:0]  pattern_rb,
	

	output [ADDR_WIDTH-1:0] gen_address,
	output [WORD_WIDTH-1:0] gen_word,
	output						write,
	output						read,
	output [3:0]				state
	);

	

	logic [WORD_WIDTH-1:0]  pattern;
	logic [ADDR_WIDTH-1:0]  address;
	logic [31:0]            count;
	

	logic [63:0]				qdata;
	logic [4:0]					raddr;
	logic							wren;
	logic [63:0]				write_data;
	

	logic  [ADDR_WIDTH-1:0] gen_address_r;
	
	logic [31:0] count_r;
	logic [3:0]  state_r;
	logic 		 direction_r;
	logic [COL_WIDTH-1:0] word_r;
	logic [1:0]  word_q_r;
	

	logic  [63:0] 		bit_flip_count_r;
	logic					confirm;
	

	always_ff@(posedge clk) begin
		if(reset) begin
			gen_address_r 	  <= 'b0;
			count_r		  <= 'b0;
			state_r		  <= 'b0;
			word_r		  <= 'b0;
			word_q_r		  <= 'b0;
			bit_flip_count_r <= 'b0;
			raddr <= 'b0;
			wren  <= 'b0;
		end
		else begin

			case(state_r)
				MEM_TEST_SM_START: begin
					state_r <= MEM_TEST_SM_LOAD_COUNT;
				end
				MEM_TEST_SM_LOAD_COUNT: begin
					state_r <= MEM_TEST_SM_LOAD_ADDRESS;
				end
				MEM_TEST_SM_LOAD_ADDRESS: begin
					state_r <= MEM_TEST_SM_LOAD_PATTERN;
				end
				MEM_TEST_SM_LOAD_PATTERN: begin
					state_r <= MEM_TEST_SM_INITIALIZE_MEM;
				end
				MEM_TEST_SM_INITIALIZE_MEM: begin
					if((word_r == {COL_WIDTH{1'b1}}) & confirm) begin
						state_r <= MEM_TEST_SM_ADDRESS_RESET_0;
					end
					else begin
						state_r <= MEM_TEST_SM_INITIALIZE_MEM;
					end
				end
				MEM_TEST_SM_ADDRESS_RESET_0:begin
					state_r <= MEM_TEST_SM_HAMMER_MEM;
				end
				MEM_TEST_SM_HAMMER_MEM: begin
					if((count_r == count) & confirm) begin
						state_r <= MEM_TEST_SM_ADDRESS_RESET_1;
					end
					else begin
						state_r <= MEM_TEST_SM_HAMMER_MEM;
					end
				end
				MEM_TEST_SM_ADDRESS_RESET_1:begin
					state_r <= MEM_TEST_SM_READ_MEM;
				end
				MEM_TEST_SM_READ_MEM: begin
						if(confirm) begin
							state_r <= MEM_TEST_SM_TALLY_MEM;
						end
						else begin
							state_r <= MEM_TEST_SM_READ_MEM;
						end
				end
				MEM_TEST_SM_TALLY_MEM: begin
					if(word_q_r == 2'b11 & word_r == {COL_WIDTH{1'b1}}) begin
						state_r <= MEM_TEST_SIG_FINISH;
					end
					else if(word_q_r == 2'b11) begin
						state_r <= MEM_TEST_SM_READ_MEM;
					end
					else begin
						state_r <= MEM_TEST_SM_TALLY_MEM;
					end
				end
				MEM_TEST_SIG_FINISH: begin
					state_r <= MEM_TEST_SM_FINISH;
				end
				MEM_TEST_SM_FINISH: begin
					state_r <= MEM_TEST_SM_FINISH;
				end			
				default: begin
					state_r <= MEM_TEST_SM_FINISH;
				end
			endcase
			


			if(state_r == MEM_TEST_SM_INITIALIZE_MEM || state_r == MEM_TEST_SM_READ_MEM) begin
				gen_address_r[COL_WIDTH + COL_POS - 1 : COL_POS] <= word_r;
			end
			else if(state_r == MEM_TEST_SM_HAMMER_MEM) begin
				gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] <= direction_r ? (gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] - 1'b1) :
																									  (gen_address_r[ROW_WIDTH + ROW_POS - 1: ROW_POS] + 1'b1);
			end
			else if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				gen_address_r <= gen_address_r;
			end
			else begin
				gen_address_r <= address;
			end

			if(state_r == MEM_TEST_SM_INITIALIZE_MEM | state_r == MEM_TEST_SM_READ_MEM | state_r == MEM_TEST_SM_TALLY_MEM) begin
				if(confirm & state_r != MEM_TEST_SM_TALLY_MEM) begin
					word_r <= word_r + {{(COL_WIDTH-1){1'b0}},1'b1};
				end
				else begin	
					word_r <= word_r;
				end
			end
			else begin
				word_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				word_q_r <= word_q_r + 2'b01;
			end
			else begin
				word_q_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_HAMMER_MEM) begin
				if(confirm) begin
					count_r <= count_r + 32'd1;
				end
				else begin
					count_r <= count_r;
				end
			end
			else begin
				count_r <= 'b0;
			end
			

			if(state_r == MEM_TEST_SM_TALLY_MEM) begin
				for(int i = 0; i < (WORD_WIDTH/4); i++) begin
					if(pattern[i + (word_q_r * (WORD_WIDTH/4))] ^ pattern_rb[i + (word_q_r * (WORD_WIDTH/4))]) begin
						bit_flip_count_r <= bit_flip_count_r + {{31{1'b0}},1'b1};
					end
				end
			end
			else begin
				bit_flip_count_r <= bit_flip_count_r;
			end
			

			if(state_r == MEM_TEST_SM_START) begin
				raddr <= 5'b00000;
				address <= address;
				pattern <= pattern;
				count <= count;
			end
			else if(state_r == MEM_TEST_SM_LOAD_ADDRESS) begin
				raddr <= 5'b00001;
				address <= qdata[ADDR_WIDTH-1:0];
				count <= count;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SM_LOAD_COUNT) begin
				raddr <= 5'b00010;
				count <= qdata[31:0];
				address <= address;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SM_LOAD_PATTERN) begin
				pattern <= qdata[WORD_WIDTH-1:0];
				raddr <= raddr;
				count <= count;
				address <= address;
			end
			else if(state_r == MEM_TEST_SM_STOR_FLIPS)begin
				raddr <= 5'b00011;
				count <= count;
				address <= address;
				pattern <= pattern;
			end
			else if(state_r == MEM_TEST_SIG_FINISH) begin
				raddr <= 5'b00100;
				count <= count;
				address <= address;
				pattern <= pattern;
			end
			else begin
				raddr <= raddr;
				count <= count;
				address <= address;
				pattern <= pattern;
			end

			if(state_r == MEM_TEST_SM_STOR_FLIPS || state_r == MEM_TEST_SIG_FINISH) begin
				wren <= 1'b1;
			end
			else begin
				wren <= 1'b0;
			end
		end
	end
	

	assign direction_r = count_r[0];
	assign confirm = !(wait_request || (!read_data_valid & state_r == MEM_TEST_SM_READ_MEM));
	

	assign write = (state_r == MEM_TEST_SM_INITIALIZE_MEM);
	assign read  = (state_r == MEM_TEST_SM_READ_MEM || state_r == MEM_TEST_SM_HAMMER_MEM);
	assign gen_word = pattern;
	assign gen_address = gen_address_r;
	assign state = state_r;
	assign write_data = (state_r == MEM_TEST_SIG_FINISH) ? 'b1 : bit_flip_count_r;
	

	mem_loader	mem_loader_inst (
	.clock 		(clk),
	.data 		(write_data),
	.address 	(raddr),
	.wren 		(wren),
	.q 			(qdata)
	);
	
endmodule