data/full_repos/permissive/439514885/testbench/cy62148E.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/cy62148E.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = !clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cy62148E(

    data,


    ce_b,
    we_b,
    oe_b,
    addr
);

inout [7:0] data;

input ce_b;
input we_b;
input oe_b;
input [18:0] addr;

reg[7:0] mem[0:514288];
reg[7:0] tmp_data;



reg clk;
initial
   begin
      clk <= 1'b0;
   end

always
   begin
      #5 clk = !clk;
   end







always @(posedge clk)
   begin
      if (!ce_b & !we_b)
         begin
            mem[addr] <= data;
         end
   end

always @(posedge clk)
   begin
       if (!ce_b & !oe_b)
          begin
             tmp_data <= mem[addr];
          end
   end

assign data = !ce_b & !oe_b & we_b ? tmp_data : 8'hz;

endmodule
module cy62148E(

    data,


    ce_b,
    we_b,
    oe_b,
    addr
);


inout [7:0] data;

input ce_b;
input we_b;
input oe_b;
input [18:0] addr;

reg[7:0] mem[0:514288];
reg[7:0] tmp_data;



reg clk;
initial
   begin
      clk <= 1'b0;
   end

always
   begin
      #5 clk = !clk;
   end







always @(posedge clk)
   begin
      if (!ce_b & !we_b)
         begin
            mem[addr] <= data;
         end
   end

always @(posedge clk)
   begin
       if (!ce_b & !oe_b)
          begin
             tmp_data <= mem[addr];
          end
   end

assign data = !ce_b & !oe_b & we_b ? tmp_data : 8'hz;

endmodule