data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:722: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:722: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d0_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc0_wr_data = (acc_valid_content[selected_centroid])? d0_to_acc + mem_acc_0_out : d0_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:723: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:723: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d1_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc1_wr_data = (acc_valid_content[selected_centroid])? d1_to_acc + mem_acc_1_out : d1_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:724: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:724: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'d2_to_acc\' generates 8 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_acc_block_k5n3\n  assign mem_acc2_wr_data = (acc_valid_content[selected_centroid])? d2_to_acc + mem_acc_2_out : d2_to_acc;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:490: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k0_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:490: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k0_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k0_st2 <= sqr_k0_d0_st1 + sqr_k0_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:491: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k1_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:491: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k1_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k1_st2 <= sqr_k1_d0_st1 + sqr_k1_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:492: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k2_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k2_st2 <= sqr_k2_d0_st1 + sqr_k2_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:492: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k2_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k2_st2 <= sqr_k2_d0_st1 + sqr_k2_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:493: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k3_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k3_st2 <= sqr_k3_d0_st1 + sqr_k3_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:493: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k3_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k3_st2 <= sqr_k3_d0_st1 + sqr_k3_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:494: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'sqr_k4_d0_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k4_st2 <= sqr_k4_d0_st1 + sqr_k4_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:494: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'sqr_k4_d1_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add0_k4_st2 <= sqr_k4_d0_st1 + sqr_k4_d1_st1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:495: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k0_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add1_k0_st2 <= sqr_k0_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:496: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k1_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add1_k1_st2 <= sqr_k1_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:497: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k2_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add1_k2_st2 <= sqr_k2_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:498: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k3_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add1_k3_st2 <= sqr_k3_d2_st1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/527214800/verilog/kmeans_k5n3_top.v:499: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'sqr_k4_d2_st1\' generates 16 bits.\n                                                                                  : ... In instance kmeans_k5n3_top.kmeans_pipeline_k5_d3\n    add1_k4_st2 <= sqr_k4_d2_st1;\n                ^~\n%Error: Exiting due to 21 warning(s)\n'
module kmeans_k5n3_top #
(
  parameter input_data_width = 8,
  parameter input_data_qty = 256,
  parameter input_data_qty_bit_width = 8,
  parameter acc_width = 16,
  parameter mem_d0_init_file = "./db/d0.txt",
  parameter mem_d1_init_file = "./db/d1.txt",
  parameter mem_d2_init_file = "./db/d2.txt",
  parameter k0_d0_initial = 0,
  parameter k0_d1_initial = 0,
  parameter k0_d2_initial = 0,
  parameter k1_d0_initial = 1,
  parameter k1_d1_initial = 1,
  parameter k1_d2_initial = 1,
  parameter k2_d0_initial = 2,
  parameter k2_d1_initial = 2,
  parameter k2_d2_initial = 2,
  parameter k3_d0_initial = 3,
  parameter k3_d1_initial = 3,
  parameter k3_d2_initial = 3,
  parameter k4_d0_initial = 4,
  parameter k4_d1_initial = 4,
  parameter k4_d2_initial = 4
)
(
  input clk,
  input rst,
  input start
);



  reg [input_data_width-1:0] k0d0;
  reg [input_data_width-1:0] k0d1;
  reg [input_data_width-1:0] k0d2;
  reg [input_data_width-1:0] k1d0;
  reg [input_data_width-1:0] k1d1;
  reg [input_data_width-1:0] k1d2;
  reg [input_data_width-1:0] k2d0;
  reg [input_data_width-1:0] k2d1;
  reg [input_data_width-1:0] k2d2;
  reg [input_data_width-1:0] k3d0;
  reg [input_data_width-1:0] k3d1;
  reg [input_data_width-1:0] k3d2;
  reg [input_data_width-1:0] k4d0;
  reg [input_data_width-1:0] k4d1;
  reg [input_data_width-1:0] k4d2;


  reg [input_data_width-1:0] new_centroid_k0 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k1 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k2 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k3 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k4 [0:3-1];


  wire [input_data_width-1:0] new_k0d0;
  wire [input_data_width-1:0] new_k0d1;
  wire [input_data_width-1:0] new_k0d2;
  wire [input_data_width-1:0] new_k1d0;
  wire [input_data_width-1:0] new_k1d1;
  wire [input_data_width-1:0] new_k1d2;
  wire [input_data_width-1:0] new_k2d0;
  wire [input_data_width-1:0] new_k2d1;
  wire [input_data_width-1:0] new_k2d2;
  wire [input_data_width-1:0] new_k3d0;
  wire [input_data_width-1:0] new_k3d1;
  wire [input_data_width-1:0] new_k3d2;
  wire [input_data_width-1:0] new_k4d0;
  wire [input_data_width-1:0] new_k4d1;
  wire [input_data_width-1:0] new_k4d2;


  assign new_k0d0 = new_centroid_k0[0];
  assign new_k0d1 = new_centroid_k0[1];
  assign new_k0d2 = new_centroid_k0[2];
  assign new_k1d0 = new_centroid_k1[0];
  assign new_k1d1 = new_centroid_k1[1];
  assign new_k1d2 = new_centroid_k1[2];
  assign new_k2d0 = new_centroid_k2[0];
  assign new_k2d1 = new_centroid_k2[1];
  assign new_k2d2 = new_centroid_k2[2];
  assign new_k3d0 = new_centroid_k3[0];
  assign new_k3d1 = new_centroid_k3[1];
  assign new_k3d2 = new_centroid_k3[2];
  assign new_k4d0 = new_centroid_k4[0];
  assign new_k4d1 = new_centroid_k4[1];
  assign new_k4d2 = new_centroid_k4[2];



  wire [input_data_qty_bit_width-1:0] input_ram_rd_address;
  wire [input_data_width-1:0] d0;
  wire [input_data_width-1:0] d1;
  wire [input_data_width-1:0] d2;

  kmeans_input_data_block_3dim
  #(
    .input_data_width(input_data_width),
    .memory_depth_bits(input_data_qty_bit_width),
    .mem_d0_init_file(mem_d0_init_file),
    .mem_d1_init_file(mem_d1_init_file),
    .mem_d2_init_file(mem_d2_init_file)
  )
  kmeans_input_data_block_3dim
  (
    .clk(clk),
    .rd_address(input_ram_rd_address),
    .output_data0(d0),
    .output_data1(d1),
    .output_data2(d2)
  );



  wire [input_data_width-1:0] d0_to_acc;
  wire [input_data_width-1:0] d1_to_acc;
  wire [input_data_width-1:0] d2_to_acc;
  wire [3-1:0] selected_centroid;

  kmeans_pipeline_k5_d3
  kmeans_pipeline_k5_d3
  (
    .clk(clk),
    .centroid0_d0(k0d0),
    .centroid0_d1(k0d1),
    .centroid0_d2(k0d2),
    .centroid1_d0(k1d0),
    .centroid1_d1(k1d1),
    .centroid1_d2(k1d2),
    .centroid2_d0(k2d0),
    .centroid2_d1(k2d1),
    .centroid2_d2(k2d2),
    .centroid3_d0(k3d0),
    .centroid3_d1(k3d1),
    .centroid3_d2(k3d2),
    .centroid4_d0(k4d0),
    .centroid4_d1(k4d1),
    .centroid4_d2(k4d2),
    .input_data0(d0),
    .input_data1(d1),
    .input_data2(d2),
    .output_data0(d0_to_acc),
    .output_data1(d1_to_acc),
    .output_data2(d2_to_acc),
    .selected_centroid(selected_centroid)
  );



  wire [acc_width-1:0] acc0_output;
  wire [acc_width-1:0] acc1_output;
  wire [acc_width-1:0] acc2_output;
  wire [3-1:0] centroid_acc_output;
  wire [input_data_qty_bit_width-1:0] acc_counter_output;

  kmeans_acc_block_k5n3
  #(
    .input_data_width(input_data_width),
    .input_data_qty_bit_width(input_data_qty_bit_width),
    .acc_width(acc_width)
  )
  kmeans_acc_block_k5n3
  (
    .clk(clk),
    .rst(0),
    .acc_enable(0),
    .d0_to_acc(d0_to_acc),
    .d1_to_acc(d1_to_acc),
    .d2_to_acc(d2_to_acc),
    .selected_centroid(selected_centroid),
    .rd_acc_en(0),
    .rd_acc_centroid(0),
    .centroid_output(centroid_acc_output),
    .acc0_output(acc0_output),
    .acc1_output(acc1_output),
    .acc2_output(acc2_output),
    .acc_counter_output(acc_counter_output)
  );

  integer i_initial;

  initial begin
    k0d0 = 0;
    k0d1 = 0;
    k0d2 = 0;
    k1d0 = 0;
    k1d1 = 0;
    k1d2 = 0;
    k2d0 = 0;
    k2d1 = 0;
    k2d2 = 0;
    k3d0 = 0;
    k3d1 = 0;
    k3d2 = 0;
    k4d0 = 0;
    k4d1 = 0;
    k4d2 = 0;
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k0[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k1[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k2[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k3[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k4[i_initial] = 0;
    end
  end


endmodule
module kmeans_k5n3_top #
(
  parameter input_data_width = 8,
  parameter input_data_qty = 256,
  parameter input_data_qty_bit_width = 8,
  parameter acc_width = 16,
  parameter mem_d0_init_file = "./db/d0.txt",
  parameter mem_d1_init_file = "./db/d1.txt",
  parameter mem_d2_init_file = "./db/d2.txt",
  parameter k0_d0_initial = 0,
  parameter k0_d1_initial = 0,
  parameter k0_d2_initial = 0,
  parameter k1_d0_initial = 1,
  parameter k1_d1_initial = 1,
  parameter k1_d2_initial = 1,
  parameter k2_d0_initial = 2,
  parameter k2_d1_initial = 2,
  parameter k2_d2_initial = 2,
  parameter k3_d0_initial = 3,
  parameter k3_d1_initial = 3,
  parameter k3_d2_initial = 3,
  parameter k4_d0_initial = 4,
  parameter k4_d1_initial = 4,
  parameter k4_d2_initial = 4
)
(
  input clk,
  input rst,
  input start
);




  reg [input_data_width-1:0] k0d0;
  reg [input_data_width-1:0] k0d1;
  reg [input_data_width-1:0] k0d2;
  reg [input_data_width-1:0] k1d0;
  reg [input_data_width-1:0] k1d1;
  reg [input_data_width-1:0] k1d2;
  reg [input_data_width-1:0] k2d0;
  reg [input_data_width-1:0] k2d1;
  reg [input_data_width-1:0] k2d2;
  reg [input_data_width-1:0] k3d0;
  reg [input_data_width-1:0] k3d1;
  reg [input_data_width-1:0] k3d2;
  reg [input_data_width-1:0] k4d0;
  reg [input_data_width-1:0] k4d1;
  reg [input_data_width-1:0] k4d2;


  reg [input_data_width-1:0] new_centroid_k0 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k1 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k2 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k3 [0:3-1];
  reg [input_data_width-1:0] new_centroid_k4 [0:3-1];


  wire [input_data_width-1:0] new_k0d0;
  wire [input_data_width-1:0] new_k0d1;
  wire [input_data_width-1:0] new_k0d2;
  wire [input_data_width-1:0] new_k1d0;
  wire [input_data_width-1:0] new_k1d1;
  wire [input_data_width-1:0] new_k1d2;
  wire [input_data_width-1:0] new_k2d0;
  wire [input_data_width-1:0] new_k2d1;
  wire [input_data_width-1:0] new_k2d2;
  wire [input_data_width-1:0] new_k3d0;
  wire [input_data_width-1:0] new_k3d1;
  wire [input_data_width-1:0] new_k3d2;
  wire [input_data_width-1:0] new_k4d0;
  wire [input_data_width-1:0] new_k4d1;
  wire [input_data_width-1:0] new_k4d2;


  assign new_k0d0 = new_centroid_k0[0];
  assign new_k0d1 = new_centroid_k0[1];
  assign new_k0d2 = new_centroid_k0[2];
  assign new_k1d0 = new_centroid_k1[0];
  assign new_k1d1 = new_centroid_k1[1];
  assign new_k1d2 = new_centroid_k1[2];
  assign new_k2d0 = new_centroid_k2[0];
  assign new_k2d1 = new_centroid_k2[1];
  assign new_k2d2 = new_centroid_k2[2];
  assign new_k3d0 = new_centroid_k3[0];
  assign new_k3d1 = new_centroid_k3[1];
  assign new_k3d2 = new_centroid_k3[2];
  assign new_k4d0 = new_centroid_k4[0];
  assign new_k4d1 = new_centroid_k4[1];
  assign new_k4d2 = new_centroid_k4[2];



  wire [input_data_qty_bit_width-1:0] input_ram_rd_address;
  wire [input_data_width-1:0] d0;
  wire [input_data_width-1:0] d1;
  wire [input_data_width-1:0] d2;

  kmeans_input_data_block_3dim
  #(
    .input_data_width(input_data_width),
    .memory_depth_bits(input_data_qty_bit_width),
    .mem_d0_init_file(mem_d0_init_file),
    .mem_d1_init_file(mem_d1_init_file),
    .mem_d2_init_file(mem_d2_init_file)
  )
  kmeans_input_data_block_3dim
  (
    .clk(clk),
    .rd_address(input_ram_rd_address),
    .output_data0(d0),
    .output_data1(d1),
    .output_data2(d2)
  );



  wire [input_data_width-1:0] d0_to_acc;
  wire [input_data_width-1:0] d1_to_acc;
  wire [input_data_width-1:0] d2_to_acc;
  wire [3-1:0] selected_centroid;

  kmeans_pipeline_k5_d3
  kmeans_pipeline_k5_d3
  (
    .clk(clk),
    .centroid0_d0(k0d0),
    .centroid0_d1(k0d1),
    .centroid0_d2(k0d2),
    .centroid1_d0(k1d0),
    .centroid1_d1(k1d1),
    .centroid1_d2(k1d2),
    .centroid2_d0(k2d0),
    .centroid2_d1(k2d1),
    .centroid2_d2(k2d2),
    .centroid3_d0(k3d0),
    .centroid3_d1(k3d1),
    .centroid3_d2(k3d2),
    .centroid4_d0(k4d0),
    .centroid4_d1(k4d1),
    .centroid4_d2(k4d2),
    .input_data0(d0),
    .input_data1(d1),
    .input_data2(d2),
    .output_data0(d0_to_acc),
    .output_data1(d1_to_acc),
    .output_data2(d2_to_acc),
    .selected_centroid(selected_centroid)
  );



  wire [acc_width-1:0] acc0_output;
  wire [acc_width-1:0] acc1_output;
  wire [acc_width-1:0] acc2_output;
  wire [3-1:0] centroid_acc_output;
  wire [input_data_qty_bit_width-1:0] acc_counter_output;

  kmeans_acc_block_k5n3
  #(
    .input_data_width(input_data_width),
    .input_data_qty_bit_width(input_data_qty_bit_width),
    .acc_width(acc_width)
  )
  kmeans_acc_block_k5n3
  (
    .clk(clk),
    .rst(0),
    .acc_enable(0),
    .d0_to_acc(d0_to_acc),
    .d1_to_acc(d1_to_acc),
    .d2_to_acc(d2_to_acc),
    .selected_centroid(selected_centroid),
    .rd_acc_en(0),
    .rd_acc_centroid(0),
    .centroid_output(centroid_acc_output),
    .acc0_output(acc0_output),
    .acc1_output(acc1_output),
    .acc2_output(acc2_output),
    .acc_counter_output(acc_counter_output)
  );

  integer i_initial;

  initial begin
    k0d0 = 0;
    k0d1 = 0;
    k0d2 = 0;
    k1d0 = 0;
    k1d1 = 0;
    k1d2 = 0;
    k2d0 = 0;
    k2d1 = 0;
    k2d2 = 0;
    k3d0 = 0;
    k3d1 = 0;
    k3d2 = 0;
    k4d0 = 0;
    k4d1 = 0;
    k4d2 = 0;
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k0[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k1[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k2[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k3[i_initial] = 0;
    end
    for(i_initial=0; i_initial<3; i_initial=i_initial+1) begin
      new_centroid_k4[i_initial] = 0;
    end
  end


endmodule