data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:32: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:56: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:57: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:74: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:75: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:76: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:77: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:78: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:79: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:80: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:81: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:100: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:110: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:111: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:112: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:113: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:114: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:115: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:116: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:117: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:128: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:138: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:139: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:140: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:141: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:142: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:143: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:144: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array02.v:145: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));\n                                         ^~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module pcx_dp_array02(

   pcx_scache2_data_px_l, pcx_scache0_data_px_l, scan_out, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk, 
   arbpc2_pcxdp_shift_px, arbpc2_pcxdp_qsel1_pa, 
   arbpc2_pcxdp_qsel0_pa, arbpc2_pcxdp_q0_hold_pa, 
   arbpc2_pcxdp_grant_pa, arbpc0_pcxdp_shift_px, 
   arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa, 
   arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa, scan_in
   );



   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;




   input [7:0]		arbpc0_pcxdp_grant_pa;
   input [7:0]		arbpc0_pcxdp_q0_hold_pa;
   input [7:0]		arbpc0_pcxdp_qsel0_pa;
   input [7:0]		arbpc0_pcxdp_qsel1_pa;
   input [7:0]		arbpc0_pcxdp_shift_px;
   input [7:0]		arbpc2_pcxdp_grant_pa;
   input [7:0]		arbpc2_pcxdp_q0_hold_pa;
   input [7:0]		arbpc2_pcxdp_qsel0_pa;
   input [7:0]		arbpc2_pcxdp_qsel1_pa;
   input [7:0]		arbpc2_pcxdp_shift_px;
   input		rclk;
   input		shiftenable;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;






   input  scan_in;
   output scan_out;
   

                 
   pcx_dp0 pcx_dp0(

		   .scan_out		(),
		   .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
		   .arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
		   .arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
		   .arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
		   .arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp2 pcx_dp2(

		   .scan_out		(),
		   .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
		   .arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
		   .arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
		   .arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
		   .arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));

endmodule
module pcx_dp_array02(

   pcx_scache2_data_px_l, pcx_scache0_data_px_l, scan_out, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk, 
   arbpc2_pcxdp_shift_px, arbpc2_pcxdp_qsel1_pa, 
   arbpc2_pcxdp_qsel0_pa, arbpc2_pcxdp_q0_hold_pa, 
   arbpc2_pcxdp_grant_pa, arbpc0_pcxdp_shift_px, 
   arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa, 
   arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa, scan_in
   );




   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;




   input [7:0]		arbpc0_pcxdp_grant_pa;
   input [7:0]		arbpc0_pcxdp_q0_hold_pa;
   input [7:0]		arbpc0_pcxdp_qsel0_pa;
   input [7:0]		arbpc0_pcxdp_qsel1_pa;
   input [7:0]		arbpc0_pcxdp_shift_px;
   input [7:0]		arbpc2_pcxdp_grant_pa;
   input [7:0]		arbpc2_pcxdp_q0_hold_pa;
   input [7:0]		arbpc2_pcxdp_qsel0_pa;
   input [7:0]		arbpc2_pcxdp_qsel1_pa;
   input [7:0]		arbpc2_pcxdp_shift_px;
   input		rclk;
   input		shiftenable;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;






   input  scan_in;
   output scan_out;
   

                 
   pcx_dp0 pcx_dp0(

		   .scan_out		(),
		   .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
		   .arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
		   .arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
		   .arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
		   .arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp2 pcx_dp2(

		   .scan_out		(),
		   .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
		   .arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
		   .arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
		   .arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
		   .arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));

endmodule