data/full_repos/permissive/492932150/hardware/src/system_core.v
1: b'%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:2: Cannot find include file: system.vh\n`include "system.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492932150/hardware/src,data/full_repos/permissive/492932150/system.vh\n             data/full_repos/permissive/492932150/hardware/src,data/full_repos/permissive/492932150/system.vh.v\n             data/full_repos/permissive/492932150/hardware/src,data/full_repos/permissive/492932150/system.vh.sv\n             system.vh\n             system.vh.v\n             system.vh.sv\n             obj_dir/system.vh\n             obj_dir/system.vh.v\n             obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:3: Cannot find include file: iob_lib.vh\n`include "iob_lib.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:4: Cannot find include file: iob_intercon.vh\n`include "iob_intercon.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:67: Cannot find include file: iob_gen_if.vh\n`include "iob_gen_if.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:11: Define or directive not defined: \'`ADDR_W\'\n    parameter ADDR_W=`ADDR_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:11: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter ADDR_W=`ADDR_W,\n                            ^\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:12: Define or directive not defined: \'`DATA_W\'\n    parameter DATA_W=`DATA_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:12: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter DATA_W=`DATA_W,\n                            ^\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_ADDR_W=`DDR_ADDR_W,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:14: Define or directive not defined: \'`DDR_ADDR_W\'\n    parameter AXI_ADDR_W=`DDR_ADDR_W,\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:14: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter AXI_ADDR_W=`DDR_ADDR_W,\n                                    ^\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:15: Define or directive not defined: \'`DDR_DATA_W\'\n    parameter AXI_DATA_W=`DDR_DATA_W\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:16: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )\n    ^\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:28: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awid, AXI_ID_W),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:29: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awaddr, AXI_ADDR_W),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:30: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awlen, 8),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:31: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awsize, 3),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:32: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awburst, 2),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:33: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awlock, 2),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:34: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awcache, 4),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:35: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awprot, 3),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:36: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awqos, 4),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:37: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_awvalid, 1),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:38: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_awready, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:39: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_wdata, AXI_DATA_W),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:40: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_wstrb, (AXI_DATA_W/8)),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:41: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_wlast, 1),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:42: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_wvalid, 1),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:43: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_wready, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:44: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_bid, AXI_ID_W),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:45: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_bresp, 2),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:46: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_bvalid, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:47: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_bready, 1),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:48: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arid, AXI_ID_W),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:49: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_araddr, AXI_ADDR_W),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:50: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arlen, 8),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:51: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arsize, 3),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:52: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arburst, 2),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:53: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arlock, 2),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:54: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arcache, 4),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:55: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arprot, 3),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:56: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arqos, 4),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:57: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_arvalid, 1),  \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:58: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_arready, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:59: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_rid, AXI_ID_W),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:60: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_rdata, AXI_DATA_W),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:61: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_rresp, 2),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:62: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_rlast, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:63: Define or directive not defined: \'`IOB_INPUT\'\n `IOB_INPUT(m_axi_rvalid, 1),  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/492932150/hardware/src/system_core.v:64: Define or directive not defined: \'`IOB_OUTPUT\'\n `IOB_OUTPUT(m_axi_rready, 1),  \n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module system
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`DDR_ADDR_W,
    parameter AXI_DATA_W=`DDR_DATA_W
    )
  (




   output trap,
          




 `IOB_OUTPUT(m_axi_awid, AXI_ID_W),
 `IOB_OUTPUT(m_axi_awaddr, AXI_ADDR_W),
 `IOB_OUTPUT(m_axi_awlen, 8),
 `IOB_OUTPUT(m_axi_awsize, 3),
 `IOB_OUTPUT(m_axi_awburst, 2),
 `IOB_OUTPUT(m_axi_awlock, 2),
 `IOB_OUTPUT(m_axi_awcache, 4),
 `IOB_OUTPUT(m_axi_awprot, 3),
 `IOB_OUTPUT(m_axi_awqos, 4),
 `IOB_OUTPUT(m_axi_awvalid, 1),
 `IOB_INPUT(m_axi_awready, 1),
 `IOB_OUTPUT(m_axi_wdata, AXI_DATA_W),
 `IOB_OUTPUT(m_axi_wstrb, (AXI_DATA_W/8)),
 `IOB_OUTPUT(m_axi_wlast, 1),
 `IOB_OUTPUT(m_axi_wvalid, 1),
 `IOB_INPUT(m_axi_wready, 1),
 `IOB_INPUT(m_axi_bid, AXI_ID_W),
 `IOB_INPUT(m_axi_bresp, 2),
 `IOB_INPUT(m_axi_bvalid, 1),
 `IOB_OUTPUT(m_axi_bready, 1),
 `IOB_OUTPUT(m_axi_arid, AXI_ID_W),
 `IOB_OUTPUT(m_axi_araddr, AXI_ADDR_W),
 `IOB_OUTPUT(m_axi_arlen, 8),
 `IOB_OUTPUT(m_axi_arsize, 3),
 `IOB_OUTPUT(m_axi_arburst, 2),
 `IOB_OUTPUT(m_axi_arlock, 2),
 `IOB_OUTPUT(m_axi_arcache, 4),
 `IOB_OUTPUT(m_axi_arprot, 3),
 `IOB_OUTPUT(m_axi_arqos, 4),
 `IOB_OUTPUT(m_axi_arvalid, 1),
 `IOB_INPUT(m_axi_arready, 1),
 `IOB_INPUT(m_axi_rid, AXI_ID_W),
 `IOB_INPUT(m_axi_rdata, AXI_DATA_W),
 `IOB_INPUT(m_axi_rresp, 2),
 `IOB_INPUT(m_axi_rlast, 1),
 `IOB_INPUT(m_axi_rvalid, 1),
 `IOB_OUTPUT(m_axi_rready, 1),

          
`include "iob_gen_if.vh"
   );
   




   wire   boot;
   wire   cpu_reset;
   





   wire [`REQ_W-1:0] cpu_i_req;
   wire [`RESP_W-1:0] cpu_i_resp;


   wire [`REQ_W-1:0]  cpu_d_req;
   wire [`RESP_W-1:0] cpu_d_resp;
   

   iob_picorv32 cpu
       (
        .clk (clk),
        .rst (cpu_reset),
        .boot (boot),
        .trap (trap),
        

        .ibus_req (cpu_i_req),
        .ibus_resp (cpu_i_resp),
        

        .dbus_req (cpu_d_req),
        .dbus_resp (cpu_d_resp)
        );







   wire [`REQ_W-1:0]  int_mem_i_req;
   wire [`RESP_W-1:0] int_mem_i_resp;

`ifdef RUN_EXTMEM
   wire [`REQ_W-1:0]  ext_mem_i_req;
   wire [`RESP_W-1:0] ext_mem_i_resp;
`endif


   iob_split
     #(
`ifdef RUN_EXTMEM
       .N_SLAVES(2),
`else
       .N_SLAVES(1),
`endif
       .P_SLAVES(`E_BIT)
       )
   ibus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (cpu_i_req),
      .m_resp (cpu_i_resp),
      

`ifdef RUN_EXTMEM
      .s_req ( {ext_mem_i_req, int_mem_i_req} ),
      .s_resp ( {ext_mem_i_resp, int_mem_i_resp} )
`else
      .s_req (int_mem_i_req),
      .s_resp ( int_mem_i_resp)
`endif
      );




`ifdef USE_DDR

   wire [`REQ_W-1:0]         ext_mem_d_req;
   wire [`RESP_W-1:0]        ext_mem_d_resp;

   wire [`REQ_W-1:0]         int_d_req;
   wire [`RESP_W-1:0]        int_d_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`E_BIT)
       )
   dbus_split
     (
      .clk    ( clk   ),
      .rst    ( cpu_reset ),


      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),


      .s_req  ( {ext_mem_d_req, int_d_req}   ),
      .s_resp ( {ext_mem_d_resp, int_d_resp} )
      );
`endif






   wire [`REQ_W-1:0]         int_mem_d_req;
   wire [`RESP_W-1:0]        int_mem_d_resp;

   wire [`REQ_W-1:0]         pbus_req;
   wire [`RESP_W-1:0]        pbus_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`P_BIT)
       )
   int_dbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

`ifdef USE_DDR

      .m_req  ( int_d_req  ),
      .m_resp ( int_d_resp ),
`else

      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),
`endif


      .s_req  ( {pbus_req, int_mem_d_req}   ),
      .s_resp ( {pbus_resp, int_mem_d_resp} )
      );







   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;
   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;

   iob_split
     #(
       .N_SLAVES(`N_SLAVES),
       .P_SLAVES(`P_BIT-1)
       )
   pbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (pbus_req),
      .m_resp (pbus_resp),
      

      .s_req (slaves_req),
      .s_resp (slaves_resp)
      );






   int_mem int_mem0
     (
      .clk (clk),
      .rst (rst),
      .boot (boot),
      .cpu_reset (cpu_reset),


      .i_req (int_mem_i_req),
      .i_resp (int_mem_i_resp),


      .d_req (int_mem_d_req),
      .d_resp (int_mem_d_resp)
      );

`ifdef USE_DDR



   ext_mem
     #(
       .AXI_ID_W(AXI_ID_W),
       .AXI_ADDR_W(AXI_ADDR_W),
       .AXI_DATA_W(AXI_DATA_W)
       )
   ext_mem0
   (
 `ifdef RUN_EXTMEM

      .i_req ( {ext_mem_i_req[`valid(0)], ext_mem_i_req[`address(0, `FIRM_ADDR_W)-2], ext_mem_i_req[`write(0)]} ),
      .i_resp (ext_mem_i_resp),
 `endif

      .d_req ( {ext_mem_d_req[`valid(0)], ext_mem_d_req[`address(0, `DCACHE_ADDR_W+1)-2], ext_mem_d_req[`write(0)]} ),
      .d_resp (ext_mem_d_resp),


`include "m_axi_portmap.vh"
      .clk (clk),
      .rst (cpu_reset)
      );
`endif



endmodule
module system
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`DDR_ADDR_W,
    parameter AXI_DATA_W=`DDR_DATA_W
    )
  (




   output trap,
          




 `IOB_OUTPUT(m_axi_awid, AXI_ID_W),
 `IOB_OUTPUT(m_axi_awaddr, AXI_ADDR_W),
 `IOB_OUTPUT(m_axi_awlen, 8),
 `IOB_OUTPUT(m_axi_awsize, 3),
 `IOB_OUTPUT(m_axi_awburst, 2),
 `IOB_OUTPUT(m_axi_awlock, 2),
 `IOB_OUTPUT(m_axi_awcache, 4),
 `IOB_OUTPUT(m_axi_awprot, 3),
 `IOB_OUTPUT(m_axi_awqos, 4),
 `IOB_OUTPUT(m_axi_awvalid, 1),
 `IOB_INPUT(m_axi_awready, 1),
 `IOB_OUTPUT(m_axi_wdata, AXI_DATA_W),
 `IOB_OUTPUT(m_axi_wstrb, (AXI_DATA_W/8)),
 `IOB_OUTPUT(m_axi_wlast, 1),
 `IOB_OUTPUT(m_axi_wvalid, 1),
 `IOB_INPUT(m_axi_wready, 1),
 `IOB_INPUT(m_axi_bid, AXI_ID_W),
 `IOB_INPUT(m_axi_bresp, 2),
 `IOB_INPUT(m_axi_bvalid, 1),
 `IOB_OUTPUT(m_axi_bready, 1),
 `IOB_OUTPUT(m_axi_arid, AXI_ID_W),
 `IOB_OUTPUT(m_axi_araddr, AXI_ADDR_W),
 `IOB_OUTPUT(m_axi_arlen, 8),
 `IOB_OUTPUT(m_axi_arsize, 3),
 `IOB_OUTPUT(m_axi_arburst, 2),
 `IOB_OUTPUT(m_axi_arlock, 2),
 `IOB_OUTPUT(m_axi_arcache, 4),
 `IOB_OUTPUT(m_axi_arprot, 3),
 `IOB_OUTPUT(m_axi_arqos, 4),
 `IOB_OUTPUT(m_axi_arvalid, 1),
 `IOB_INPUT(m_axi_arready, 1),
 `IOB_INPUT(m_axi_rid, AXI_ID_W),
 `IOB_INPUT(m_axi_rdata, AXI_DATA_W),
 `IOB_INPUT(m_axi_rresp, 2),
 `IOB_INPUT(m_axi_rlast, 1),
 `IOB_INPUT(m_axi_rvalid, 1),
 `IOB_OUTPUT(m_axi_rready, 1),

          
`include "iob_gen_if.vh"
   );

   




   wire   boot;
   wire   cpu_reset;
   





   wire [`REQ_W-1:0] cpu_i_req;
   wire [`RESP_W-1:0] cpu_i_resp;


   wire [`REQ_W-1:0]  cpu_d_req;
   wire [`RESP_W-1:0] cpu_d_resp;
   

   iob_picorv32 cpu
       (
        .clk (clk),
        .rst (cpu_reset),
        .boot (boot),
        .trap (trap),
        

        .ibus_req (cpu_i_req),
        .ibus_resp (cpu_i_resp),
        

        .dbus_req (cpu_d_req),
        .dbus_resp (cpu_d_resp)
        );







   wire [`REQ_W-1:0]  int_mem_i_req;
   wire [`RESP_W-1:0] int_mem_i_resp;

`ifdef RUN_EXTMEM
   wire [`REQ_W-1:0]  ext_mem_i_req;
   wire [`RESP_W-1:0] ext_mem_i_resp;
`endif


   iob_split
     #(
`ifdef RUN_EXTMEM
       .N_SLAVES(2),
`else
       .N_SLAVES(1),
`endif
       .P_SLAVES(`E_BIT)
       )
   ibus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (cpu_i_req),
      .m_resp (cpu_i_resp),
      

`ifdef RUN_EXTMEM
      .s_req ( {ext_mem_i_req, int_mem_i_req} ),
      .s_resp ( {ext_mem_i_resp, int_mem_i_resp} )
`else
      .s_req (int_mem_i_req),
      .s_resp ( int_mem_i_resp)
`endif
      );




`ifdef USE_DDR

   wire [`REQ_W-1:0]         ext_mem_d_req;
   wire [`RESP_W-1:0]        ext_mem_d_resp;

   wire [`REQ_W-1:0]         int_d_req;
   wire [`RESP_W-1:0]        int_d_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`E_BIT)
       )
   dbus_split
     (
      .clk    ( clk   ),
      .rst    ( cpu_reset ),


      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),


      .s_req  ( {ext_mem_d_req, int_d_req}   ),
      .s_resp ( {ext_mem_d_resp, int_d_resp} )
      );
`endif






   wire [`REQ_W-1:0]         int_mem_d_req;
   wire [`RESP_W-1:0]        int_mem_d_resp;

   wire [`REQ_W-1:0]         pbus_req;
   wire [`RESP_W-1:0]        pbus_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`P_BIT)
       )
   int_dbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

`ifdef USE_DDR

      .m_req  ( int_d_req  ),
      .m_resp ( int_d_resp ),
`else

      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),
`endif


      .s_req  ( {pbus_req, int_mem_d_req}   ),
      .s_resp ( {pbus_resp, int_mem_d_resp} )
      );







   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;
   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;

   iob_split
     #(
       .N_SLAVES(`N_SLAVES),
       .P_SLAVES(`P_BIT-1)
       )
   pbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (pbus_req),
      .m_resp (pbus_resp),
      

      .s_req (slaves_req),
      .s_resp (slaves_resp)
      );






   int_mem int_mem0
     (
      .clk (clk),
      .rst (rst),
      .boot (boot),
      .cpu_reset (cpu_reset),


      .i_req (int_mem_i_req),
      .i_resp (int_mem_i_resp),


      .d_req (int_mem_d_req),
      .d_resp (int_mem_d_resp)
      );

`ifdef USE_DDR



   ext_mem
     #(
       .AXI_ID_W(AXI_ID_W),
       .AXI_ADDR_W(AXI_ADDR_W),
       .AXI_DATA_W(AXI_DATA_W)
       )
   ext_mem0
   (
 `ifdef RUN_EXTMEM

      .i_req ( {ext_mem_i_req[`valid(0)], ext_mem_i_req[`address(0, `FIRM_ADDR_W)-2], ext_mem_i_req[`write(0)]} ),
      .i_resp (ext_mem_i_resp),
 `endif

      .d_req ( {ext_mem_d_req[`valid(0)], ext_mem_d_req[`address(0, `DCACHE_ADDR_W+1)-2], ext_mem_d_req[`write(0)]} ),
      .d_resp (ext_mem_d_resp),


`include "m_axi_portmap.vh"
      .clk (clk),
      .rst (cpu_reset)
      );
`endif



endmodule