data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:45: Define or directive not defined: \'`CROSSBAR_TYPE_MUX\'\n   parameter crossbar_type = `CROSSBAR_TYPE_MUX;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter crossbar_type = `CROSSBAR_TYPE_MUX;\n                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:77: Define or directive not defined: \'`CROSSBAR_TYPE_TRISTATE\'\n      `CROSSBAR_TYPE_TRISTATE:\n      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:77: syntax error, unexpected \':\', expecting endcase\n      `CROSSBAR_TYPE_TRISTATE:\n                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:93: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:95: Define or directive not defined: \'`CROSSBAR_TYPE_MUX\'\n      `CROSSBAR_TYPE_MUX:\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:110: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:112: Define or directive not defined: \'`CROSSBAR_TYPE_DIST_MUX\'\n      `CROSSBAR_TYPE_DIST_MUX:\n      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_crossbar.v:140: syntax error, unexpected end\n        end\n        ^~~\n%Error: Cannot continue\n'
module c_crossbar
  (ctrl_ip_op, data_in_ip, data_out_op);
   
`include "c_constants.v"
   

   parameter num_in_ports = 5;
   parameter num_out_ports = 5;
   

   parameter width = 32;
   

   parameter crossbar_type = `CROSSBAR_TYPE_MUX;
   

   input [0:num_in_ports*num_out_ports-1] ctrl_ip_op;
   

   input [0:num_in_ports*width-1] data_in_ip;
   

   output [0:num_out_ports*width-1] data_out_op;
   wire [0:num_out_ports*width-1] data_out_op;
   
   wire [0:num_out_ports*num_in_ports-1] ctrl_op_ip;
   c_interleave
     #(.width(num_in_ports*num_out_ports),
       .num_blocks(num_in_ports))
   ctrl_intl
     (.data_in(ctrl_ip_op),
      .data_out(ctrl_op_ip));
   
   generate
      
      genvar 				 op;
      for(op = 0; op < num_out_ports; op = op + 1)
	begin:ops
	   
	   wire [0:width-1] data_out;
	   
	   genvar 	    ip;
	   
	   case(crossbar_type)
	     
	     `CROSSBAR_TYPE_TRISTATE:
	       begin
		  
		  for(ip = 0; ip < num_in_ports; ip = ip + 1)
		    begin:tristate_ips
		       
		       wire [0:width-1] in;
		       assign in = data_in_ip[ip*width:(ip+1)*width-1];
		       
		       wire 		ctrl;
		       assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
		       
		       assign data_out = ctrl ? in : {width{1'bz}};
		       
		    end
		  
	       end
	     
	     `CROSSBAR_TYPE_MUX:
	       begin
		  
		  wire [0:num_in_ports-1] ctrl_ip;
		  assign ctrl_ip
		    = ctrl_op_ip[op*num_in_ports:(op+1)*num_in_ports-1];
		  
		  c_select_1ofn
		    #(.width(width),
		      .num_ports(num_in_ports))
		  out_mux
		    (.select(ctrl_ip),
		     .data_in(data_in_ip),
		     .data_out(data_out));
		  
	       end
	     
	     `CROSSBAR_TYPE_DIST_MUX:
	       begin
		  
		  wire [0:num_in_ports*width-1] data;
		  assign data[0:width-1] = data_in_ip[0:width-1];
		  
		  for(ip = 1; ip < num_in_ports; ip = ip + 1)
		    begin:dist_mux_ips
		       
		       wire [0:width-1] in;
		       assign in = data_in_ip[ip*width:(ip+1)*width-1];
		       
		       wire [0:width-1] thru;
		       assign thru = data[(ip-1)*width:ip*width-1];
		       
		       wire 		ctrl;
		       assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
		       
		       wire [0:width-1] out;
		       assign out = ctrl ? in : thru;
		       
		       assign data[ip*width:(ip+1)*width-1] = out;
		       
		    end
		  
		  assign data_out
		    = data[(num_in_ports-1)*width:num_in_ports*width-1];
		  
	       end
	     
	   endcase
	   
	   assign data_out_op[op*width:(op+1)*width-1] = data_out;
	   
	end
      
   endgenerate
   
endmodule
module c_crossbar
  (ctrl_ip_op, data_in_ip, data_out_op);

   
`include "c_constants.v"
   

   parameter num_in_ports = 5;
   parameter num_out_ports = 5;
   

   parameter width = 32;
   

   parameter crossbar_type = `CROSSBAR_TYPE_MUX;
   

   input [0:num_in_ports*num_out_ports-1] ctrl_ip_op;
   

   input [0:num_in_ports*width-1] data_in_ip;
   

   output [0:num_out_ports*width-1] data_out_op;
   wire [0:num_out_ports*width-1] data_out_op;
   
   wire [0:num_out_ports*num_in_ports-1] ctrl_op_ip;
   c_interleave
     #(.width(num_in_ports*num_out_ports),
       .num_blocks(num_in_ports))
   ctrl_intl
     (.data_in(ctrl_ip_op),
      .data_out(ctrl_op_ip));
   
   generate
      
      genvar 				 op;
      for(op = 0; op < num_out_ports; op = op + 1)
	begin:ops
	   
	   wire [0:width-1] data_out;
	   
	   genvar 	    ip;
	   
	   case(crossbar_type)
	     
	     `CROSSBAR_TYPE_TRISTATE:
	       begin
		  
		  for(ip = 0; ip < num_in_ports; ip = ip + 1)
		    begin:tristate_ips
		       
		       wire [0:width-1] in;
		       assign in = data_in_ip[ip*width:(ip+1)*width-1];
		       
		       wire 		ctrl;
		       assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
		       
		       assign data_out = ctrl ? in : {width{1'bz}};
		       
		    end
		  
	       end
	     
	     `CROSSBAR_TYPE_MUX:
	       begin
		  
		  wire [0:num_in_ports-1] ctrl_ip;
		  assign ctrl_ip
		    = ctrl_op_ip[op*num_in_ports:(op+1)*num_in_ports-1];
		  
		  c_select_1ofn
		    #(.width(width),
		      .num_ports(num_in_ports))
		  out_mux
		    (.select(ctrl_ip),
		     .data_in(data_in_ip),
		     .data_out(data_out));
		  
	       end
	     
	     `CROSSBAR_TYPE_DIST_MUX:
	       begin
		  
		  wire [0:num_in_ports*width-1] data;
		  assign data[0:width-1] = data_in_ip[0:width-1];
		  
		  for(ip = 1; ip < num_in_ports; ip = ip + 1)
		    begin:dist_mux_ips
		       
		       wire [0:width-1] in;
		       assign in = data_in_ip[ip*width:(ip+1)*width-1];
		       
		       wire [0:width-1] thru;
		       assign thru = data[(ip-1)*width:ip*width-1];
		       
		       wire 		ctrl;
		       assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
		       
		       wire [0:width-1] out;
		       assign out = ctrl ? in : thru;
		       
		       assign data[ip*width:(ip+1)*width-1] = out;
		       
		    end
		  
		  assign data_out
		    = data[(num_in_ports-1)*width:num_in_ports*width-1];
		  
	       end
	     
	   endcase
	   
	   assign data_out_op[op*width:(op+1)*width-1] = data_out;
	   
	end
      
   endgenerate
   
endmodule