data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:2: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/cache,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/cache,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/cache,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:3: Cannot find include file: rtl/core/pc.v\n`include "rtl/core/pc.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:4: Cannot find include file: rtl/core/if_id.v\n`include "rtl/core/if_id.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:5: Cannot find include file: rtl/core/id.v\n`include "rtl/core/id.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:12: Define or directive not defined: \'`inst_bus\'\n    input wire [`inst_bus]          inst_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`inst_bus]          inst_i,\n                         ^\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:13: Define or directive not defined: \'`inst_addr_bus\'\n    output wire [`inst_addr_bus]    inst_addr_o,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`inst_addr_bus] jump_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:16: Define or directive not defined: \'`inst_addr_bus\'\n    input wire [`inst_addr_bus] jump_addr_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:17: Define or directive not defined: \'`hold_ctrl_bus\'\n    input wire [`hold_ctrl_bus] hold_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:18: Define or directive not defined: \'`inst_bus\'\n    output wire [`inst_bus] inst_o\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:21: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_pc_i = hold_i[1:0];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_pc_i = hold_i[1:0];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:22: Define or directive not defined: \'`holdpip_bus\'\n    wire [`holdpip_bus] hold_if_id_i = hold_i[3:2];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`holdpip_bus] hold_if_id_i = hold_i[3:2];\n                      ^\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:24: Define or directive not defined: \'`inst_addr_bus\'\n    wire [`inst_addr_bus] ifid_pc_o;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/cache/pc_ifid.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`inst_addr_bus] ifid_pc_o;\n                        ^\n%Error: Exiting due to 17 error(s)\n'
module pc_ifid (
    input wire                      clk,
    input wire                      rst_n,

    input wire [`inst_bus]          inst_i,
    output wire [`inst_addr_bus]    inst_addr_o,

    input wire jump_flag_i,
    input wire [`inst_addr_bus] jump_addr_i,
    input wire [`hold_ctrl_bus] hold_i,
    output wire [`inst_bus] inst_o
);

    wire [`holdpip_bus] hold_pc_i = hold_i[1:0];
    wire [`holdpip_bus] hold_if_id_i = hold_i[3:2];

    wire [`inst_addr_bus] ifid_pc_o;

    pc u_pc(
    	.clk          (clk          ),
        .rst_n        (rst_n        ),
        .jump_flag_i  (jump_flag_i  ),
        .jump_addr_i  (jump_addr_i  ),
        .hold_flag_i  (hold_pc_i    ),
        .jtag_reset_i (jtag_reset_i ),
        .pc_o         (inst_addr_o  )
    );
    
    if_id u_if_id(
    	.clk         (clk         ),
        .rst_n       (rst_n       ),
        .hold_flag_i (hold_if_id_i),
        .inst_i      (inst_i      ),
        .inst_addr_i (inst_addr_o ),
        .inst_o      (inst_o      ),
        .inst_addr_o (ifid_pc_o   )
    );

    id u_id(
    	.inst_i         (inst_o         ),
        .inst_addr_i    (ifid_pc_o      )
    );
    
    
    
endmodule
module pc_ifid (
    input wire                      clk,
    input wire                      rst_n,

    input wire [`inst_bus]          inst_i,
    output wire [`inst_addr_bus]    inst_addr_o,

    input wire jump_flag_i,
    input wire [`inst_addr_bus] jump_addr_i,
    input wire [`hold_ctrl_bus] hold_i,
    output wire [`inst_bus] inst_o
);


    wire [`holdpip_bus] hold_pc_i = hold_i[1:0];
    wire [`holdpip_bus] hold_if_id_i = hold_i[3:2];

    wire [`inst_addr_bus] ifid_pc_o;

    pc u_pc(
    	.clk          (clk          ),
        .rst_n        (rst_n        ),
        .jump_flag_i  (jump_flag_i  ),
        .jump_addr_i  (jump_addr_i  ),
        .hold_flag_i  (hold_pc_i    ),
        .jtag_reset_i (jtag_reset_i ),
        .pc_o         (inst_addr_o  )
    );
    
    if_id u_if_id(
    	.clk         (clk         ),
        .rst_n       (rst_n       ),
        .hold_flag_i (hold_if_id_i),
        .inst_i      (inst_i      ),
        .inst_addr_i (inst_addr_o ),
        .inst_o      (inst_o      ),
        .inst_addr_o (ifid_pc_o   )
    );

    id u_id(
    	.inst_i         (inst_o         ),
        .inst_addr_i    (ifid_pc_o      )
    );
    
    
    
endmodule