data/full_repos/permissive/446312960/Verilog_Simulation/05_decoder/decoder_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/05_decoder/decoder_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/05_decoder/decoder_test.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/05_decoder/decoder_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/05_decoder/decoder_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decoder_test(t1, t2);
output [1:0]   t1;
input  [3:0]   t2;


reg       t1;

initial begin
   t1 <= 2'b00;
   
   #100;
   t1 <= 2'b01;

   #100;
   t1 <= 2'b10;

   #100;
   t1 <= 2'b11;

   #100;
   $finish;
end

endmodule
module decoder_test(t1, t2);

output [1:0]   t1;
input  [3:0]   t2;


reg       t1;

initial begin
   t1 <= 2'b00;
   
   #100;
   t1 <= 2'b01;

   #100;
   t1 <= 2'b10;

   #100;
   t1 <= 2'b11;

   #100;
   $finish;
end

endmodule