data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rf/100m/adc_gearbox_2x1.v
data/verilator_xmls/78b27b2e-94fe-4f92-9b21-68f141101141.xml
module adc_gearbox_2x1 (
  input  wire        clk1x,
  input  wire        reset_n_1x,

  input  wire [31:0] adc_q_in_1x,
  input  wire [31:0] adc_i_in_1x,
  input  wire        valid_in_1x,

  input  wire        enable_1x,

  input  wire        clk2x,

  input  wire        swap_iq_2x,
  output wire [31:0] adc_out_2x,
  output wire        valid_out_2x
);



  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [31:0] data_out_2x = 32'b0, adc_q_data_in_2x = 32'b0, adc_i_data_in_2x = 32'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end









  reg        toggle_2x_fall   = 1'b0;
  reg [31:0] adc_q_in_2x_fall = 32'b0;
  reg [31:0] adc_i_in_2x_fall = 32'b0;
  reg        valid_in_2x_fall = 1'b0;
  reg        enable_2x_fall   = 1'b0;

  always @(negedge clk2x) begin
    toggle_2x_fall   <= toggle_1x;
    adc_q_in_2x_fall <= adc_q_in_1x;
    adc_i_in_2x_fall <= adc_i_in_1x;
    valid_in_2x_fall <= valid_in_1x;
    enable_2x_fall   <= enable_1x;
  end










  always @(posedge clk2x) begin
    toggle_2x     <= toggle_2x_fall;
    toggle_2x_dly <= toggle_2x;
    adc_q_data_in_2x <= adc_q_in_2x_fall;
    adc_i_data_in_2x <= adc_i_in_2x_fall;

    if (valid_2x) begin
      if (swap_iq_2x) begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x[31:16] <= adc_i_data_in_2x[15:0];
          data_out_2x[15: 0] <= adc_q_data_in_2x[15:0];
        end else begin
          data_out_2x[31:16] <= adc_i_data_in_2x[31:16];
          data_out_2x[15: 0] <= adc_q_data_in_2x[31:16];
        end
      end else begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x[31:16] <= adc_q_data_in_2x[15:0];
          data_out_2x[15: 0] <= adc_i_data_in_2x[15:0];
        end else begin
          data_out_2x[31:16] <= adc_q_data_in_2x[31:16];
          data_out_2x[15: 0] <= adc_i_data_in_2x[31:16];
        end
      end
    end else begin
      data_out_2x <= 32'b0;
    end


    valid_2x     <= valid_in_2x_fall && enable_2x_fall;
    valid_dly_2x <= valid_2x;
  end

  assign adc_out_2x   = data_out_2x;
  assign valid_out_2x = valid_dly_2x;

endmodule
module adc_gearbox_2x1 (
  input  wire        clk1x,
  input  wire        reset_n_1x,

  input  wire [31:0] adc_q_in_1x,
  input  wire [31:0] adc_i_in_1x,
  input  wire        valid_in_1x,

  input  wire        enable_1x,

  input  wire        clk2x,

  input  wire        swap_iq_2x,
  output wire [31:0] adc_out_2x,
  output wire        valid_out_2x
);




  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [31:0] data_out_2x = 32'b0, adc_q_data_in_2x = 32'b0, adc_i_data_in_2x = 32'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end









  reg        toggle_2x_fall   = 1'b0;
  reg [31:0] adc_q_in_2x_fall = 32'b0;
  reg [31:0] adc_i_in_2x_fall = 32'b0;
  reg        valid_in_2x_fall = 1'b0;
  reg        enable_2x_fall   = 1'b0;

  always @(negedge clk2x) begin
    toggle_2x_fall   <= toggle_1x;
    adc_q_in_2x_fall <= adc_q_in_1x;
    adc_i_in_2x_fall <= adc_i_in_1x;
    valid_in_2x_fall <= valid_in_1x;
    enable_2x_fall   <= enable_1x;
  end










  always @(posedge clk2x) begin
    toggle_2x     <= toggle_2x_fall;
    toggle_2x_dly <= toggle_2x;
    adc_q_data_in_2x <= adc_q_in_2x_fall;
    adc_i_data_in_2x <= adc_i_in_2x_fall;

    if (valid_2x) begin
      if (swap_iq_2x) begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x[31:16] <= adc_i_data_in_2x[15:0];
          data_out_2x[15: 0] <= adc_q_data_in_2x[15:0];
        end else begin
          data_out_2x[31:16] <= adc_i_data_in_2x[31:16];
          data_out_2x[15: 0] <= adc_q_data_in_2x[31:16];
        end
      end else begin
        if (toggle_2x != toggle_2x_dly) begin
          data_out_2x[31:16] <= adc_q_data_in_2x[15:0];
          data_out_2x[15: 0] <= adc_i_data_in_2x[15:0];
        end else begin
          data_out_2x[31:16] <= adc_q_data_in_2x[31:16];
          data_out_2x[15: 0] <= adc_i_data_in_2x[31:16];
        end
      end
    end else begin
      data_out_2x <= 32'b0;
    end


    valid_2x     <= valid_in_2x_fall && enable_2x_fall;
    valid_dly_2x <= valid_2x;
  end

  assign adc_out_2x   = data_out_2x;
  assign valid_out_2x = valid_dly_2x;

endmodule