data/full_repos/permissive/489642764/src/wb_gpio/tb.v
1: b'%Error: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:48: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:49: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:51: syntax error, unexpected \'@\'\n   @ ( posedge clk50 );\n   ^\n%Error: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:58: syntax error, unexpected \'@\'\n  @ (negedge arst_n);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #(1.24 * 2000);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #(18.9 * 2000);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_gpio/tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
	wire    arst_n;
	wire    clk50;
	wire    clk125;
	wire    clk50_srst_n;
	wire    clk125_srst_n;
	wire    gpio_out;


	clk_gen clk_gen_inst(
		.arst_n       (arst_n),
		.clk50        (clk50),
		.clk125       (clk125),
		.clk50_srst_n (clk50_srst_n),
		.clk125_srst_n(clk125_srst_n)
	);


	wb_gpio dut(

		.wb_clk_i (clk50),
		.wb_rst_i (! clk50_srst_n),
		.wb_cyc_i (),
		.wb_adr_i (),
		.wb_dat_i (),
		.wb_sel_i (),
		.wb_we_i  (),
		.wb_stb_i (),
		.wb_dat_o (),
		.wb_ack_o (),
		.wb_err_o (),
		.wb_inta_o(),


		.gpio_i   (),
		.gpio_o   (),
		.gpio_oe_o()
	);


	integer k;
	initial begin
		$dumpfile("dump.vcd");
		$dumpvars(1, dut);
		for ( k = 0 ; k < 10000 ; k = k + 1 ) begin
			@ ( posedge clk50 );
		end
		$finish;
	end


	initial begin
		@ (negedge arst_n);
		@ (posedge arst_n);
	end
endmodule
module tb;

	wire    arst_n;
	wire    clk50;
	wire    clk125;
	wire    clk50_srst_n;
	wire    clk125_srst_n;
	wire    gpio_out;


	clk_gen clk_gen_inst(
		.arst_n       (arst_n),
		.clk50        (clk50),
		.clk125       (clk125),
		.clk50_srst_n (clk50_srst_n),
		.clk125_srst_n(clk125_srst_n)
	);


	wb_gpio dut(

		.wb_clk_i (clk50),
		.wb_rst_i (! clk50_srst_n),
		.wb_cyc_i (),
		.wb_adr_i (),
		.wb_dat_i (),
		.wb_sel_i (),
		.wb_we_i  (),
		.wb_stb_i (),
		.wb_dat_o (),
		.wb_ack_o (),
		.wb_err_o (),
		.wb_inta_o(),


		.gpio_i   (),
		.gpio_o   (),
		.gpio_oe_o()
	);


	integer k;
	initial begin
		$dumpfile("dump.vcd");
		$dumpvars(1, dut);
		for ( k = 0 ; k < 10000 ; k = k + 1 ) begin
			@ ( posedge clk50 );
		end
		$finish;
	end


	initial begin
		@ (negedge arst_n);
		@ (posedge arst_n);
	end
endmodule