data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Up.v
data/verilator_xmls/459ae218-bb26-4ae7-a4df-789f645db6b0.xml
module count1(input wire clk,reset,count,inc,output wire cout,q);
wire w1,w2,w3;
assign w1=q;
xor2 x1(w1,inc,w3);
and2 a1(count,w3,cout);
xor2 x2(count,w1,w2);
dfr d1(clk,reset,w2,q);
endmodule
module count1(input wire clk,reset,count,inc,output wire cout,q);

wire w1,w2,w3;
assign w1=q;
xor2 x1(w1,inc,w3);
and2 a1(count,w3,cout);
xor2 x2(count,w1,w2);
dfr d1(clk,reset,w2,q);
endmodule