data/full_repos/permissive/443520440/testbench/seg7_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/443520440/testbench/seg7_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/443520440/testbench/seg7_tb.v:16: Cannot find file containing module: \'display7\'\n    display7 display7_0(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/display7\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/display7.v\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/display7.sv\n             display7\n             display7.v\n             display7.sv\n             obj_dir/display7\n             obj_dir/display7.v\n             obj_dir/display7.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display7_tb();
    reg clk;
    reg [3:0] led1;
    reg [3:0] led2;
    reg [3:0] led3;
    reg [3:0] led4;
    reg [3:0] led5;
    reg [3:0] led6;
    reg [3:0] led7;
    reg [3:0] led8;

    wire [7:0] ena;
    wire [7:0] ctl;
    display7 display7_0(
        clk,
        led1,
        led2,
        led3,
        led4,
        led5,
        led6,
        led7,
        led8,
        ena,
        ctl
    );
    initial begin 
        clk = 0;
        led1 = 2;
        led2 = 3;
        led3 = 4;
        led4 = 5;
        led5 = 6;
        led6 = 7;
        led7 = 8;
        led8 = 9;
    end
    always #1 clk = ~clk;
endmodule
module display7_tb();

    reg clk;
    reg [3:0] led1;
    reg [3:0] led2;
    reg [3:0] led3;
    reg [3:0] led4;
    reg [3:0] led5;
    reg [3:0] led6;
    reg [3:0] led7;
    reg [3:0] led8;

    wire [7:0] ena;
    wire [7:0] ctl;
    display7 display7_0(
        clk,
        led1,
        led2,
        led3,
        led4,
        led5,
        led6,
        led7,
        led8,
        ena,
        ctl
    );
    initial begin 
        clk = 0;
        led1 = 2;
        led2 = 3;
        led3 = 4;
        led4 = 5;
        led5 = 6;
        led6 = 7;
        led7 = 8;
        led8 = 9;
    end
    always #1 clk = ~clk;
endmodule