data/full_repos/permissive/452183855/lab2/D_ff_AR.v
data/verilator_xmls/84915e70-cac0-488b-aa86-0cea48180643.xml
module D_ff_AR(Q, D, clock, reset);
    
    output Q;
    input  D, clock, reset;
    reg    Q;


    always @(posedge clock, negedge reset)
        if(!reset)Q <= 1'b0;
        else Q <= D;

endmodule
module D_ff_AR(Q, D, clock, reset);

    
    output Q;
    input  D, clock, reset;
    reg    Q;


    always @(posedge clock, negedge reset)
        if(!reset)Q <= 1'b0;
        else Q <= D;

endmodule