data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit signed multiplier using wallace tree/multi_16bit.v
1: b'%Error: Cannot find file containing module: signed\n        ... Looked in:\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.v\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.sv\n             signed\n             signed.v\n             signed.sv\n             obj_dir/signed\n             obj_dir/signed.v\n             obj_dir/signed.sv\n%Error: Cannot find file containing module: multiplier\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: wallace\n%Error: Cannot find file containing module: tree,data/full_repos/permissive/405799749\n%Error: Cannot find file containing module: data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit\n%Error: Cannot find file containing module: tree/multi_16bit.v\n%Error: Exiting due to 7 error(s)\n'
module multi_16bit(prod,a,b,clk,rst,load);
	output [31:0] prod;
	input [15:0] a,b;
	input clk,rst,load;
	wire [15:0] ahxl,alxl,ahxh,alxh,ahxhm;
	wire [23:0] ahxlex,alxhex,s1,c1;
	multi_8bit_signed_unsigned m8bsu1(.prod(ahxl),.a(a[15:8]),.b(b[7:0]),.clk(clk),.rst(rst),.load(load));

	multi_8bit_unsigned m8bu1(.prod(alxl),.a(a[7:0]),.b(b[7:0]),.clk(clk),.rst(rst),.load(load));
	multi_8bit m8b1(.prod(ahxhm),.a(a[15:8]),.b(b[15:8]),.clk(clk),.rst(rst),.load(load));
	dff_16bit d16b2(.q(ahxh),.d(ahxhm),.clk(clk),.rst(rst));
	multi_8bit_signed_unsigned m8bsu2(.prod(alxh),.a(b[15:8]),.b(a[7:0]),.clk(clk),.rst(rst),.load(load));

	assign ahxlex = { {8{ahxl[15]}} , ahxl };
	assign alxhex = { {8{alxh[15]}} , alxh };
	csa_24bit c24b1(.s(s1),.c(c1),.x(ahxlex),.y({ahxh,alxl[15:8]}),.z(alxhex));
	cla_ripple_24bit cr24b1(.sum(prod[31:8]),.c24(x),.a(s1),.b({c1[22:0],1'b0}),.c0(1'b0));
	assign prod[7:0]=alxl[7:0];
endmodule
module multi_16bit(prod,a,b,clk,rst,load);

	output [31:0] prod;
	input [15:0] a,b;
	input clk,rst,load;
	wire [15:0] ahxl,alxl,ahxh,alxh,ahxhm;
	wire [23:0] ahxlex,alxhex,s1,c1;
	multi_8bit_signed_unsigned m8bsu1(.prod(ahxl),.a(a[15:8]),.b(b[7:0]),.clk(clk),.rst(rst),.load(load));

	multi_8bit_unsigned m8bu1(.prod(alxl),.a(a[7:0]),.b(b[7:0]),.clk(clk),.rst(rst),.load(load));
	multi_8bit m8b1(.prod(ahxhm),.a(a[15:8]),.b(b[15:8]),.clk(clk),.rst(rst),.load(load));
	dff_16bit d16b2(.q(ahxh),.d(ahxhm),.clk(clk),.rst(rst));
	multi_8bit_signed_unsigned m8bsu2(.prod(alxh),.a(b[15:8]),.b(a[7:0]),.clk(clk),.rst(rst),.load(load));

	assign ahxlex = { {8{ahxl[15]}} , ahxl };
	assign alxhex = { {8{alxh[15]}} , alxh };
	csa_24bit c24b1(.s(s1),.c(c1),.x(ahxlex),.y({ahxh,alxl[15:8]}),.z(alxhex));
	cla_ripple_24bit cr24b1(.sum(prod[31:8]),.c24(x),.a(s1),.b({c1[22:0],1'b0}),.c0(1'b0));
	assign prod[7:0]=alxl[7:0];
endmodule