data/full_repos/permissive/435877241/prj_30.v
data/verilator_xmls/c887540f-3f8a-417e-b7bd-186d0acc2db1.xml
module prj_30(
	input [3:0] data,
	output [1:0] out0,
	output [1:0] out1
	);
	assign out0=data[3:2];
	assign out1=data[1:0];
endmodule
module prj_30(
	input [3:0] data,
	output [1:0] out0,
	output [1:0] out1
	);

	assign out0=data[3:2];
	assign out1=data[1:0];
endmodule