data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v:1: Cannot find include file: decode.v\n`include"decode.v" \n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/decode.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/decode.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/decode.v.sv\n             decode.v\n             decode.v.v\n             decode.v.sv\n             obj_dir/decode.v\n             obj_dir/decode.v.v\n             obj_dir/decode.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("decode.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/decode_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module testbench;
reg [3:0] icode;
reg Cnd;
reg [3:0] rA;
reg [3:0] rB;
reg clock;
wire [3:0] srcA,srcB,destM,destE;


	integer i,k,j;
	decode DUT(icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);
	initial begin

	$dumpfile("decode.vcd");
    	$dumpvars(0,icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);
	clock=0;
	icode=4'hB;
	rA=4'h2;
	rB=4'h7;
	Cnd=0;


	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	clock=0;
	#10;
	end
end
endmodule
module testbench;

reg [3:0] icode;
reg Cnd;
reg [3:0] rA;
reg [3:0] rB;
reg clock;
wire [3:0] srcA,srcB,destM,destE;


	integer i,k,j;
	decode DUT(icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);
	initial begin

	$dumpfile("decode.vcd");
    	$dumpvars(0,icode,Cnd,rA,rB,clock,srcA,srcB,destM,destE);
	clock=0;
	icode=4'hB;
	rA=4'h2;
	rB=4'h7;
	Cnd=0;


	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	clock=0;
	#10;
	end
end
endmodule