data/full_repos/permissive/427221126/src/ConvLayer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ConvLayer.v:459: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ConvLayer\'\nmodule ConvLayer\n       ^~~~~~~~~\n                                                                           : ... Top module \'ConvCore_nC\'\nmodule ConvCore_nC\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:129: Operator ASSIGNDLY expects 41 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n      psum[0] <= mul[0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:140: Operator ADD expects 41 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n          psum[ii] <= mul[ii] + psum[ii-1];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:423: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g] ;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:425: Operator ADD expects 48 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g]  + psum[g-1];\n                                          ^\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:243: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.sv\n             ShiftRegSIPOnB\n             ShiftRegSIPOnB.v\n             ShiftRegSIPOnB.sv\n             obj_dir/ShiftRegSIPOnB\n             obj_dir/ShiftRegSIPOnB.v\n             obj_dir/ShiftRegSIPOnB.sv\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:255: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:290: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:623: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:639: Cannot find file containing module: \'FIFOsync\'\n  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:651: Cannot find file containing module: \'FIFOpi\'\n  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (\n  ^~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module Vecdot9 
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10
  ) 
  (
    input                       clk       ,
    input                       reset     , 
    input                       en        ,
    input  signed [INWIDTH-1:0] hin       ,
    input                       hin_valid ,
    input  signed [INWIDTH-1:0] xin       ,
    input                       xin_valid ,
    output signed [INWIDTH-1:0] dout      ,
    output                      dout_valid
  );
  localparam VECTOR_LEN = 9;
  localparam CNTWIDTH = $clog2(VECTOR_LEN);
  reg            [CNTWIDTH-1:0] hcounter;
  wire                          shreg_bksh_h;
  wire [INWIDTH*VECTOR_LEN-1:0] pout_h;
  reg            [CNTWIDTH-1:0] xcounter;
  wire                          shreg_bksh_x;
  wire [INWIDTH*VECTOR_LEN-1:0] pout_x;
  reg                    [14:1] xc_wrap_d;

  wire hcounter_wrap;
  wire xcounter_wrap;

  wire signed [INWIDTH*2+8:0] core_out;

  wire round_satu, round_ovfl, round_udfl;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      hcounter <= 0;
    end
    else if (en) begin
      if (hin_valid)
        if (!hcounter_wrap) 
          hcounter <= hcounter + 1;
        else
          hcounter <= 0;
    end
  end

  assign hcounter_wrap = (hcounter == 4'd8);
  assign xcounter_wrap = (xcounter == 4'd8);

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      xcounter <= 0;
    end
    else if (en) begin
      if (xin_valid)
        if (!xcounter_wrap) 
          xcounter <= xcounter + 1;
        else
          xcounter <= 0;
    end
  end
  
  assign shreg_bksh_h = hcounter_wrap && hin_valid;
  assign shreg_bksh_x = xcounter_wrap && xin_valid;

  always @(posedge clk) begin
    if (reset == 1'b1) 
      xc_wrap_d <= 14'h0000;
    else if (en)
      xc_wrap_d <= {xc_wrap_d[14-1:1], shreg_bksh_x};
  end

  assign dout_valid = xc_wrap_d[14];

  ShiftRegSIPOnB #(
    .INWIDTH(INWIDTH),
    .DEPTH(VECTOR_LEN),
    .NUM_BANKS(2)
  ) U_ifm_shreg (
    .clk(clk), .reset(reset), .en(en),
    .din(xin), .din_valid(xin_valid),
    .bksh(shreg_bksh_x),
    .pout(pout_x),
    .casout()
  );
  
  ShiftRegSIPOnB #(
    .INWIDTH(INWIDTH),
    .DEPTH(VECTOR_LEN),
    .NUM_BANKS(2)
  ) U_ker_shreg (
    .clk(clk), .reset(reset), .en(en),
    .din(hin), .din_valid(hin_valid),
    .bksh(shreg_bksh_h),
    .pout(pout_h),
    .casout()
  );

  ConvCore3x3 #(.INWIDTH(INWIDTH)) U_core (
    .clk(clk), .reset(reset), .en(en),
    .h0(pout_h[INWIDTH*(0+1)-1:INWIDTH*0]), 
    .h1(pout_h[INWIDTH*(1+1)-1:INWIDTH*1]), 
    .h2(pout_h[INWIDTH*(2+1)-1:INWIDTH*2]), 
    .h3(pout_h[INWIDTH*(3+1)-1:INWIDTH*3]), 
    .h4(pout_h[INWIDTH*(4+1)-1:INWIDTH*4]), 
    .h5(pout_h[INWIDTH*(5+1)-1:INWIDTH*5]), 
    .h6(pout_h[INWIDTH*(6+1)-1:INWIDTH*6]), 
    .h7(pout_h[INWIDTH*(7+1)-1:INWIDTH*7]), 
    .h8(pout_h[INWIDTH*(8+1)-1:INWIDTH*8]), 
    .x0(pout_x[INWIDTH*(0+1)-1:INWIDTH*0]),
    .x1(pout_x[INWIDTH*(1+1)-1:INWIDTH*1]),
    .x2(pout_x[INWIDTH*(2+1)-1:INWIDTH*2]),
    .x3(pout_x[INWIDTH*(3+1)-1:INWIDTH*3]),
    .x4(pout_x[INWIDTH*(4+1)-1:INWIDTH*4]),
    .x5(pout_x[INWIDTH*(5+1)-1:INWIDTH*5]),
    .x6(pout_x[INWIDTH*(6+1)-1:INWIDTH*6]),
    .x7(pout_x[INWIDTH*(7+1)-1:INWIDTH*7]),
    .x8(pout_x[INWIDTH*(8+1)-1:INWIDTH*8]),
    .y(core_out)
  );

  FRound #(
    .INWIDTH(INWIDTH*2+9),
    .IN_FRAC(IN_FRAC*2),
    .OUTWIDTH(INWIDTH),
    .OUT_FRAC(IN_FRAC)
  ) U_round (
    .CLK(clk), .EN(en), .RESET(reset),
    .DIN(core_out),
    .DOUT(dout),
    .SATUR(round_satu),
    .OVFL(round_ovfl),
    .UDFL(round_udfl)
  );
endmodule
module Vecdot9 
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10
  ) 
  (
    input                       clk       ,
    input                       reset     , 
    input                       en        ,
    input  signed [INWIDTH-1:0] hin       ,
    input                       hin_valid ,
    input  signed [INWIDTH-1:0] xin       ,
    input                       xin_valid ,
    output signed [INWIDTH-1:0] dout      ,
    output                      dout_valid
  );

  localparam VECTOR_LEN = 9;
  localparam CNTWIDTH = $clog2(VECTOR_LEN);
  reg            [CNTWIDTH-1:0] hcounter;
  wire                          shreg_bksh_h;
  wire [INWIDTH*VECTOR_LEN-1:0] pout_h;
  reg            [CNTWIDTH-1:0] xcounter;
  wire                          shreg_bksh_x;
  wire [INWIDTH*VECTOR_LEN-1:0] pout_x;
  reg                    [14:1] xc_wrap_d;

  wire hcounter_wrap;
  wire xcounter_wrap;

  wire signed [INWIDTH*2+8:0] core_out;

  wire round_satu, round_ovfl, round_udfl;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      hcounter <= 0;
    end
    else if (en) begin
      if (hin_valid)
        if (!hcounter_wrap) 
          hcounter <= hcounter + 1;
        else
          hcounter <= 0;
    end
  end

  assign hcounter_wrap = (hcounter == 4'd8);
  assign xcounter_wrap = (xcounter == 4'd8);

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      xcounter <= 0;
    end
    else if (en) begin
      if (xin_valid)
        if (!xcounter_wrap) 
          xcounter <= xcounter + 1;
        else
          xcounter <= 0;
    end
  end
  
  assign shreg_bksh_h = hcounter_wrap && hin_valid;
  assign shreg_bksh_x = xcounter_wrap && xin_valid;

  always @(posedge clk) begin
    if (reset == 1'b1) 
      xc_wrap_d <= 14'h0000;
    else if (en)
      xc_wrap_d <= {xc_wrap_d[14-1:1], shreg_bksh_x};
  end

  assign dout_valid = xc_wrap_d[14];

  ShiftRegSIPOnB #(
    .INWIDTH(INWIDTH),
    .DEPTH(VECTOR_LEN),
    .NUM_BANKS(2)
  ) U_ifm_shreg (
    .clk(clk), .reset(reset), .en(en),
    .din(xin), .din_valid(xin_valid),
    .bksh(shreg_bksh_x),
    .pout(pout_x),
    .casout()
  );
  
  ShiftRegSIPOnB #(
    .INWIDTH(INWIDTH),
    .DEPTH(VECTOR_LEN),
    .NUM_BANKS(2)
  ) U_ker_shreg (
    .clk(clk), .reset(reset), .en(en),
    .din(hin), .din_valid(hin_valid),
    .bksh(shreg_bksh_h),
    .pout(pout_h),
    .casout()
  );

  ConvCore3x3 #(.INWIDTH(INWIDTH)) U_core (
    .clk(clk), .reset(reset), .en(en),
    .h0(pout_h[INWIDTH*(0+1)-1:INWIDTH*0]), 
    .h1(pout_h[INWIDTH*(1+1)-1:INWIDTH*1]), 
    .h2(pout_h[INWIDTH*(2+1)-1:INWIDTH*2]), 
    .h3(pout_h[INWIDTH*(3+1)-1:INWIDTH*3]), 
    .h4(pout_h[INWIDTH*(4+1)-1:INWIDTH*4]), 
    .h5(pout_h[INWIDTH*(5+1)-1:INWIDTH*5]), 
    .h6(pout_h[INWIDTH*(6+1)-1:INWIDTH*6]), 
    .h7(pout_h[INWIDTH*(7+1)-1:INWIDTH*7]), 
    .h8(pout_h[INWIDTH*(8+1)-1:INWIDTH*8]), 
    .x0(pout_x[INWIDTH*(0+1)-1:INWIDTH*0]),
    .x1(pout_x[INWIDTH*(1+1)-1:INWIDTH*1]),
    .x2(pout_x[INWIDTH*(2+1)-1:INWIDTH*2]),
    .x3(pout_x[INWIDTH*(3+1)-1:INWIDTH*3]),
    .x4(pout_x[INWIDTH*(4+1)-1:INWIDTH*4]),
    .x5(pout_x[INWIDTH*(5+1)-1:INWIDTH*5]),
    .x6(pout_x[INWIDTH*(6+1)-1:INWIDTH*6]),
    .x7(pout_x[INWIDTH*(7+1)-1:INWIDTH*7]),
    .x8(pout_x[INWIDTH*(8+1)-1:INWIDTH*8]),
    .y(core_out)
  );

  FRound #(
    .INWIDTH(INWIDTH*2+9),
    .IN_FRAC(IN_FRAC*2),
    .OUTWIDTH(INWIDTH),
    .OUT_FRAC(IN_FRAC)
  ) U_round (
    .CLK(clk), .EN(en), .RESET(reset),
    .DIN(core_out),
    .DOUT(dout),
    .SATUR(round_satu),
    .OVFL(round_ovfl),
    .UDFL(round_udfl)
  );
endmodule