data/full_repos/permissive/493019833/test/testcase/firrtl/OverflowTypeCircuit/sbt/OverflowTypeCircuit.v
data/verilator_xmls/7669169f-057d-4c60-9374-c431d2cdec88.xml
module OverflowTypeCircuit(
  input        clock,
  input        reset,
  input  [3:0] io_a,
  input  [3:0] io_b,
  output [4:0] io_addWrap,
  output [4:0] io_addGrow,
  output [4:0] io_subWrap,
  output [4:0] io_subGrow
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [3:0] regAddWrap;
  reg [4:0] regAddGrow;
  reg [3:0] regSubWrap;
  reg [4:0] regSubGrow;
  assign io_addWrap = {{1{regAddWrap[3]}},regAddWrap};
  assign io_addGrow = regAddGrow;
  assign io_subWrap = {{1{regSubWrap[3]}},regSubWrap};
  assign io_subGrow = regSubGrow;
  always @(posedge clock) begin
    regAddWrap <= $signed(io_a) + $signed(io_b);
    regAddGrow <= $signed(io_a) + $signed(io_b);
    regSubWrap <= $signed(io_a) - $signed(io_b);
    regSubGrow <= $signed(io_a) - $signed(io_b);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regAddWrap = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  regAddGrow = _RAND_1[4:0];
  _RAND_2 = {1{`RANDOM}};
  regSubWrap = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  regSubGrow = _RAND_3[4:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module OverflowTypeCircuit(
  input        clock,
  input        reset,
  input  [3:0] io_a,
  input  [3:0] io_b,
  output [4:0] io_addWrap,
  output [4:0] io_addGrow,
  output [4:0] io_subWrap,
  output [4:0] io_subGrow
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [3:0] regAddWrap;
  reg [4:0] regAddGrow;
  reg [3:0] regSubWrap;
  reg [4:0] regSubGrow;
  assign io_addWrap = {{1{regAddWrap[3]}},regAddWrap};
  assign io_addGrow = regAddGrow;
  assign io_subWrap = {{1{regSubWrap[3]}},regSubWrap};
  assign io_subGrow = regSubGrow;
  always @(posedge clock) begin
    regAddWrap <= $signed(io_a) + $signed(io_b);
    regAddGrow <= $signed(io_a) + $signed(io_b);
    regSubWrap <= $signed(io_a) - $signed(io_b);
    regSubGrow <= $signed(io_a) - $signed(io_b);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regAddWrap = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  regAddGrow = _RAND_1[4:0];
  _RAND_2 = {1{`RANDOM}};
  regSubWrap = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  regSubGrow = _RAND_3[4:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule