data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module multi_xor #(parameter length= 7)(
    input [length:1] ros_i,
    output rosx
    );
    
wire [length-1:1] Xor_out;
sky130_fd_sc_hd__xor2_4 xor_initial (
	.A(ros_i[1]),
	.B(ros_i[2]),
	.X(Xor_out[1])
);
genvar i;
generate 
   for (i=1; i<=length-2; i=i+1)begin
	sky130_fd_sc_hd__xor2_4 xors (
		.A(Xor_out[i]),
		.B(ros_i[i+2]),
		.X(Xor_out[i+1])
	);
   end
endgenerate

assign rosx = Xor_out[length-1];
endmodule
module multi_xor #(parameter length= 7)(
    input [length:1] ros_i,
    output rosx
    );

    
wire [length-1:1] Xor_out;
sky130_fd_sc_hd__xor2_4 xor_initial (
	.A(ros_i[1]),
	.B(ros_i[2]),
	.X(Xor_out[1])
);
genvar i;
generate 
   for (i=1; i<=length-2; i=i+1)begin
	sky130_fd_sc_hd__xor2_4 xors (
		.A(Xor_out[i]),
		.B(ros_i[i+2]),
		.X(Xor_out[i+1])
	);
   end
endgenerate

assign rosx = Xor_out[length-1];
endmodule