data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:261: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                       : ... In instance AddSub.u_pad_20\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:254: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                       : ... In instance AddSub.s_pad_19\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:239: Operator MODDIVS expects 6 bits on the LHS, but LHS\'s SIGNED generates 4 bits.\n                                                                                                       : ... In instance AddSub.s_rem_16\n    assign y = $signed(num) % $signed(den);\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:239: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 6 bits.\n                                                                                                       : ... In instance AddSub.s_rem_16\n    assign y = $signed(num) % $signed(den);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:230: Operator MODDIV expects 6 bits on the LHS, but LHS\'s VARREF \'num\' generates 4 bits.\n                                                                                                       : ... In instance AddSub.u_rem_15\n    assign y = num % den;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:230: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 6 bits.\n                                                                                                       : ... In instance AddSub.u_rem_15\n    assign y = num % den;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:221: Operator DIVS expects 6 bits on the LHS, but LHS\'s SIGNED generates 4 bits.\n                                                                                                       : ... In instance AddSub.s_div_14\n    assign y = $signed(num) / $signed(den);\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:221: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s DIVS generates 6 bits.\n                                                                                                       : ... In instance AddSub.s_div_14\n    assign y = $signed(num) / $signed(den);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:213: Operator DIV expects 6 bits on the LHS, but LHS\'s VARREF \'num\' generates 4 bits.\n                                                                                                       : ... In instance AddSub.u_div_13\n    assign y = num / den;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/AddSub/reference/AddSub.v:213: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 6 bits.\n                                                                                                       : ... In instance AddSub.u_div_13\n    assign y = num / den;\n             ^\n%Error: Exiting due to 10 warning(s)\n'
module ASUINT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $unsigned(in);
endmodule
module ASUINT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $unsigned(in);
endmodule