data/full_repos/permissive/430337995/TinyML/src/acc.v
1: b'%Error: data/full_repos/permissive/430337995/TinyML/src/acc.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/TinyML/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/TinyML/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/TinyML/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/TinyML/src/acc.v:14: Define or directive not defined: \'`WORD_SIZE\'\n    output reg [`WORD_SIZE-1:0] uni_addr,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/TinyML/src/acc.v:15: Define or directive not defined: \'`WORD_SIZE\'\n    input   [`WORD_SIZE-1:0]    uni_data_in,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/TinyML/src/acc.v:19: syntax error, unexpected \')\', expecting IDENTIFIER or do or final\n);\n^\n%Error: Exiting due to 4 error(s)\n'
module TinyML (
    input                       clk,
    input                       reset,


    input                       start,
    input    [4:0]              m,
    input    [4:0]              n,
    output reg                  done,
    
    output reg                  uni_wen,
    output reg [`WORD_SIZE-1:0] uni_addr,
    input   [`WORD_SIZE-1:0]    uni_data_in,

    output reg                  

);
























endmodule
module TinyML (
    input                       clk,
    input                       reset,


    input                       start,
    input    [4:0]              m,
    input    [4:0]              n,
    output reg                  done,
    
    output reg                  uni_wen,
    output reg [`WORD_SIZE-1:0] uni_addr,
    input   [`WORD_SIZE-1:0]    uni_data_in,

    output reg                  

);

























endmodule