data/full_repos/permissive/484765019/BIST/DFF.v
data/verilator_xmls/16b372b9-343a-49f9-9227-0fdfc6550b01.xml
module DFF(D,clk,n_rst,Q);
input D;
input clk;
input n_rst;
output reg Q;
always @(posedge clk or negedge n_rst) 
begin
 if(n_rst==1'b0)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule
module DFF(D,clk,n_rst,Q);

input D;
input clk;
input n_rst;
output reg Q;
always @(posedge clk or negedge n_rst) 
begin
 if(n_rst==1'b0)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule