data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:13: Unsupported: Ignoring delay on this delayed statement.\n#1 clk=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:14: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:33: Unsupported: Ignoring delay on this delayed statement.\n#3 t_rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:34: Unsupported: Ignoring delay on this delayed statement.\n#2 t_rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:36: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:38: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:39: Unsupported: wait statements\nwait(done);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:40: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:48: Unsupported or unknown PLI call: $monitor\n$monitor ("main status = %d",itestwrap.iauc_mmul.main);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:49: Unsupported or unknown PLI call: $monitor\n$monitor ("comp cnt = %d at time = %t",itestwrap.iauc_mmul.iauc_mmul_comp.cnt,$time);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:86: Unsupported or unknown PLI call: $shm_open\n$shm_open ("my_waves");\n^~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:87: Unsupported or unknown PLI call: $shm_probe\n$shm_probe (tb_testwrap,"ACM");\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:88: Unsupported or unknown PLI call: $recordfile\n$recordfile("testsample.trn");\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/FixingMontScar/tb_testwrap.v:89: Unsupported or unknown PLI call: $recordvars\n$recordvars();\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testwrap;
`define TESTWRAPMONT
localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;
reg clk;
reg t_rst;

always begin
clk = 0;
#1 clk=1;
#1;
end

wire done;
reg  en;

testwrap itestwrap
    (
     .clk(clk),
     .rst(t_rst),
     .en(en),
     .done(done)
     );



initial begin
t_rst = 1'b0;
en = 1'b0;
#3 t_rst = 1'b1;
#2 t_rst = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
wait(done);
#100;
$finish;
end
initial begin
$display ("==========OUTPUT==========");
end

initial begin
$monitor ("main status = %d",itestwrap.iauc_mmul.main);
$monitor ("comp cnt = %d at time = %t",itestwrap.iauc_mmul.iauc_mmul_comp.cnt,$time);
end

always@(posedge clk)
    begin
    if(itestwrap.iauc_mmul.mmul_we)
        begin
        $display ("==========write enable ==========");  
        $display ("at main state = %d",itestwrap.iauc_mmul.main);
        if(itestwrap.iauc_mmul.main == INIT)
            $display ("at init state = %d",  itestwrap.iauc_mmul.iauc_mmul_init.init_state);
        if(itestwrap.iauc_mmul.iauc_mmul_comp.comp_en)
            $display ("k after init = %h",itestwrap.ialram113x.ialram112x.mem[11]);
        else if(itestwrap.iauc_mmul.main == COMP)
            begin
            $display ("==========cnt %d ==========",itestwrap.iauc_mmul.iauc_mmul_comp.cnt);
            $display ("at comp state = %d",  itestwrap.iauc_mmul.iauc_mmul_comp.comp_state);
            end
        else if(itestwrap.iauc_mmul.main == FINAL)
            $display ("at final state = %d",itestwrap.iauc_mmul.iauc_mmul_final.final_state);
        $display ("write data is = %d",itestwrap.iauc_mmul.mmul_wd);
        $display ("write address is = %d",  itestwrap.iauc_mmul.mmul_wa);
        end
    
    end


always@(posedge clk) begin
if(done)
    begin
    $display ("done");
    $display ("final_result = %h",itestwrap.ialram113x.ialram112x.mem[15]);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_testwrap,"ACM");
$recordfile("testsample.trn");
$recordvars();
end

endmodule
module tb_testwrap;

`define TESTWRAPMONT
localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;
reg clk;
reg t_rst;

always begin
clk = 0;
#1 clk=1;
#1;
end

wire done;
reg  en;

testwrap itestwrap
    (
     .clk(clk),
     .rst(t_rst),
     .en(en),
     .done(done)
     );



initial begin
t_rst = 1'b0;
en = 1'b0;
#3 t_rst = 1'b1;
#2 t_rst = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
wait(done);
#100;
$finish;
end
initial begin
$display ("==========OUTPUT==========");
end

initial begin
$monitor ("main status = %d",itestwrap.iauc_mmul.main);
$monitor ("comp cnt = %d at time = %t",itestwrap.iauc_mmul.iauc_mmul_comp.cnt,$time);
end

always@(posedge clk)
    begin
    if(itestwrap.iauc_mmul.mmul_we)
        begin
        $display ("==========write enable ==========");  
        $display ("at main state = %d",itestwrap.iauc_mmul.main);
        if(itestwrap.iauc_mmul.main == INIT)
            $display ("at init state = %d",  itestwrap.iauc_mmul.iauc_mmul_init.init_state);
        if(itestwrap.iauc_mmul.iauc_mmul_comp.comp_en)
            $display ("k after init = %h",itestwrap.ialram113x.ialram112x.mem[11]);
        else if(itestwrap.iauc_mmul.main == COMP)
            begin
            $display ("==========cnt %d ==========",itestwrap.iauc_mmul.iauc_mmul_comp.cnt);
            $display ("at comp state = %d",  itestwrap.iauc_mmul.iauc_mmul_comp.comp_state);
            end
        else if(itestwrap.iauc_mmul.main == FINAL)
            $display ("at final state = %d",itestwrap.iauc_mmul.iauc_mmul_final.final_state);
        $display ("write data is = %d",itestwrap.iauc_mmul.mmul_wd);
        $display ("write address is = %d",  itestwrap.iauc_mmul.mmul_wa);
        end
    
    end


always@(posedge clk) begin
if(done)
    begin
    $display ("done");
    $display ("final_result = %h",itestwrap.ialram113x.ialram112x.mem[15]);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_testwrap,"ACM");
$recordfile("testsample.trn");
$recordvars();
end

endmodule