data/full_repos/permissive/426889244/tb/clock.v
data/verilator_xmls/3c345fe0-3185-4283-88c7-46013c97c8f0.xml
module clock (
    input wire clk_in1,
    input wire resetn,

    output wire clk_out1
);
    reg[15:0] cnt;

    always @(posedge clk_in1 or negedge resetn) begin
        if (~resetn) begin
            cnt <= 0;
        end
        else begin
            cnt <= cnt + 1;
        end
    end

    assign clk_out1 = cnt[15];
endmodule
module clock (
    input wire clk_in1,
    input wire resetn,

    output wire clk_out1
);

    reg[15:0] cnt;

    always @(posedge clk_in1 or negedge resetn) begin
        if (~resetn) begin
            cnt <= 0;
        end
        else begin
            cnt <= cnt + 1;
        end
    end

    assign clk_out1 = cnt[15];
endmodule