data/full_repos/permissive/472385934/control_unit.v
data/verilator_xmls/8b0e7ebe-7d2e-4a8d-beaa-ba31b453d6b4.xml
module control_unit(
input [5:0] funct,
input [5:0] op,
input rst_n,
output reg regwrite,
output reg memtoreg,
output reg memwrite,
output reg [1:0] branch,
output reg [3:0] alucontrol,
output reg alusrc,
output reg regdst,
output reg jump,
output reg mult_sel);

wire [3:0] aluop;

main_decoder main_decoder(.op(op),.rst_n(rst_n),.aluop(aluop),.regwrite(regwrite),
            .memtoreg(memtoreg),.memwrite(memwrite),
            .branch(branch),.alusrc(alusrc),.regdst(regdst),.jump(jump));

alu_decoder alu_decoder(.funct(funct),.rst_n(rst_n),.aluop(aluop),
                        .mult_sel(mult_sel),.func(alucontrol));
                        
endmodule
module control_unit(
input [5:0] funct,
input [5:0] op,
input rst_n,
output reg regwrite,
output reg memtoreg,
output reg memwrite,
output reg [1:0] branch,
output reg [3:0] alucontrol,
output reg alusrc,
output reg regdst,
output reg jump,
output reg mult_sel);


wire [3:0] aluop;

main_decoder main_decoder(.op(op),.rst_n(rst_n),.aluop(aluop),.regwrite(regwrite),
            .memtoreg(memtoreg),.memwrite(memwrite),
            .branch(branch),.alusrc(alusrc),.regdst(regdst),.jump(jump));

alu_decoder alu_decoder(.funct(funct),.rst_n(rst_n),.aluop(aluop),
                        .mult_sel(mult_sel),.func(alucontrol));
                        
endmodule