data/full_repos/permissive/497819211/04/Computer.v
1: b'%Error: data/full_repos/permissive/497819211/04/Computer.v:2: Cannot find include file: Mux16.v\n`include "Mux16.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v.v\n             data/full_repos/permissive/497819211/04,data/full_repos/permissive/497819211/Mux16.v.sv\n             Mux16.v\n             Mux16.v.v\n             Mux16.v.sv\n             obj_dir/Mux16.v\n             obj_dir/Mux16.v.v\n             obj_dir/Mux16.v.sv\n%Error: data/full_repos/permissive/497819211/04/Computer.v:3: Cannot find include file: DMux.v\n`include "DMux.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:4: Cannot find include file: Btn.v\n`include "Btn.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:5: Cannot find include file: Led.v\n`include "Led.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:7: Cannot find include file: Not.v\n`include "Not.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:8: Cannot find include file: And.v\n`include "And.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:9: Cannot find include file: Or.v\n`include "Or.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:10: Cannot find include file: RAM.v\n`include "RAM.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:11: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:12: Cannot find include file: ALUusr.v\n`include "ALUusr.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:13: Cannot find include file: PC.v\n`include "PC.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:14: Cannot find include file: Not16.v\n`include "Not16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:15: Cannot find include file: And16.v\n`include "And16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:16: Cannot find include file: Add16.v\n`include "Add16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:17: Cannot find include file: Or8Way.v\n`include "Or8Way.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:19: Cannot find include file: Memory.v\n`include "Memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:20: Cannot find include file: CPU.v\n`include "CPU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:21: Cannot find include file: ROM.v\n`include "ROM.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/497819211/04/Computer.v:22: Cannot find include file: Clk.v\n`include "Clk.v" \n         ^~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module Computer( 
    input clk_in,
    input btn,
	output led,
    input reset
);
	



    wire clk_out;
    Clk CLK(
		.in(clk_in),
		.out(clk_out)
	);

    wire [15:0] addressM;
    wire [15:0] outM;
    wire [15:0] instruction;
    wire [15:0] pc;
    wire [15:0] Mout;

    wire writeM;

	ROM ROM(
		.instruction(instruction),
		.pc(pc)
	);
	CPU CPU(
		.clk(clk_out),
		.inM(Mout),
		.instruction(instruction),
		.reset(~reset),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);

	Memory MEMORY(
		.clk(clk_out),
		.address(addressM),
		.in(outM),
		.out(Mout),
		.load(writeM),
        .btn(btn),
        .led(led)
	);

endmodule
module Computer( 
    input clk_in,
    input btn,
	output led,
    input reset
);

	



    wire clk_out;
    Clk CLK(
		.in(clk_in),
		.out(clk_out)
	);

    wire [15:0] addressM;
    wire [15:0] outM;
    wire [15:0] instruction;
    wire [15:0] pc;
    wire [15:0] Mout;

    wire writeM;

	ROM ROM(
		.instruction(instruction),
		.pc(pc)
	);
	CPU CPU(
		.clk(clk_out),
		.inM(Mout),
		.instruction(instruction),
		.reset(~reset),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);

	Memory MEMORY(
		.clk(clk_out),
		.address(addressM),
		.in(outM),
		.out(Mout),
		.load(writeM),
        .btn(btn),
        .led(led)
	);

endmodule