data/full_repos/permissive/527249789/src/cp0_reg.v
1: b'%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:8: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]           waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`RegAddrBus]           waddr_i,\n                        ^\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:9: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]           raddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:10: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]               data_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:11: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            data_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:13: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]               exception_type_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:15: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]               current_inst_addr_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:16: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]               mem_data_addr_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:19: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            badvaddr_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:20: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            count_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:21: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            compare_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:22: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            status_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:23: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            cause_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:24: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            epc_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:25: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]            ebase_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:35: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:36: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:38: Define or directive not defined: \'`ZeroWord\'\n        badvaddr_o <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:39: Define or directive not defined: \'`ZeroWord\'\n        count_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:40: Define or directive not defined: \'`ZeroWord\'\n        compare_o <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:41: Define or directive not defined: \'`CP0_REG_STATUS_RESET_VALUE\'\n        status_o <= `CP0_REG_STATUS_RESET_VALUE;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:42: Define or directive not defined: \'`ZeroWord\'\n        cause_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:43: Define or directive not defined: \'`ZeroWord\'\n        epc_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:44: Define or directive not defined: \'`ExceptionInitialPC\'\n        ebase_o <= `ExceptionInitialPC;\n                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:45: Define or directive not defined: \'`InterruptNotAssert\'\n        timer_int_o <= `InterruptNotAssert;\n                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:53: Define or directive not defined: \'`ZeroWord\'\n        if ((compare_o != `ZeroWord) && (count_o == compare_o)) timer_int_o <= `InterruptAssert;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:53: Define or directive not defined: \'`InterruptAssert\'\n        if ((compare_o != `ZeroWord) && (count_o == compare_o)) timer_int_o <= `InterruptAssert;\n                                                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:59: Define or directive not defined: \'`WriteEnable\'\n        if (wen_i == `WriteEnable) begin\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:61: Define or directive not defined: \'`CP0_REG_COUNT\'\n                `CP0_REG_COUNT: begin\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:65: Define or directive not defined: \'`CP0_REG_COMPARE\'\n                `CP0_REG_COMPARE: begin\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:67: Define or directive not defined: \'`InterruptNotAssert\'\n                    timer_int_o <= `InterruptNotAssert;\n                                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:69: Define or directive not defined: \'`CP0_REG_STATUS\'\n                `CP0_REG_STATUS: begin\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:73: Define or directive not defined: \'`CP0_REG_CAUSE\'\n                `CP0_REG_CAUSE: begin\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:76: Define or directive not defined: \'`CP0_REG_EPC\'\n                `CP0_REG_EPC: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:79: Define or directive not defined: \'`CP0_REG_EBASE\'\n                `CP0_REG_EBASE: begin\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:92: Define or directive not defined: \'`EXECEPTION_INT\'\n            `EXECEPTION_INT: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:95: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:106: Define or directive not defined: \'`EXECEPTION_ADEL\'\n            `EXECEPTION_ADEL: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:109: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:122: Define or directive not defined: \'`EXECEPTION_ADES\'\n            `EXECEPTION_ADES: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:125: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:137: Define or directive not defined: \'`EXECEPTION_SYS\'\n            `EXECEPTION_SYS: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:140: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:151: Define or directive not defined: \'`EXECEPTION_BREAK\'\n            `EXECEPTION_BREAK: begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:154: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:165: Define or directive not defined: \'`EXECEPTION_INSTVALID\'\n            `EXECEPTION_INSTVALID: begin\n            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:168: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:179: Define or directive not defined: \'`EXECEPTION_OV\'\n            `EXECEPTION_OV: begin\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/cp0_reg.v:182: Define or directive not defined: \'`InDelaySlot\'\n                    if (is_in_delayslot_i == `InDelaySlot) begin\n                                             ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cp0_reg(
    input                           clk,
    input                           resetn,

    input                           wen_i,
    input   [`RegAddrBus]           waddr_i,
    input   [`RegAddrBus]           raddr_i,
    input   [`RegBus]               data_i,
    output  reg[`RegBus]            data_o,

    input   [`RegBus]               exception_type_i,
    input   [5:0]                   int_i,
    input   [`RegBus]               current_inst_addr_i,
    input   [`RegBus]               mem_data_addr_i,
    input                           is_in_delayslot_i,

    output  reg[`RegBus]            badvaddr_o,
    output  reg[`RegBus]            count_o,
    output  reg[`RegBus]            compare_o,
    output  reg[`RegBus]            status_o,
    output  reg[`RegBus]            cause_o,
    output  reg[`RegBus]            epc_o,
    output  reg[`RegBus]            ebase_o,



    output  reg                     timer_int_o
);


reg clk_double;

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        clk_double <= 1'b0;
        badvaddr_o <= `ZeroWord;
        count_o <= `ZeroWord;
        compare_o <= `ZeroWord;
        status_o <= `CP0_REG_STATUS_RESET_VALUE;
        cause_o <= `ZeroWord;
        epc_o <= `ZeroWord;
        ebase_o <= `ExceptionInitialPC;
        timer_int_o <= `InterruptNotAssert;
    end else begin

        clk_double <= ~clk_double;
        if (clk_double) count_o <= count_o + 1;
        cause_o[15:10] <= int_i;
        cause_o[30] <= timer_int_o;

        if ((compare_o != `ZeroWord) && (count_o == compare_o)) timer_int_o <= `InterruptAssert;





        if (wen_i == `WriteEnable) begin
            case (waddr_i)
                `CP0_REG_COUNT: begin
                    clk_double <= 1'b0;
                    count_o <= data_i;
                end
                `CP0_REG_COMPARE: begin
                    compare_o <= data_i;
                    timer_int_o <= `InterruptNotAssert;
                end
                `CP0_REG_STATUS: begin
                    status_o[15:8] <= data_i[15:8];
                    status_o[1:0] <= data_i[1:0];
                end
                `CP0_REG_CAUSE: begin
                    cause_o[9:8] <= data_i[9:8];
                end
                `CP0_REG_EPC: begin
                    epc_o <= data_i;
                end
                `CP0_REG_EBASE: begin
                    ebase_o <= data_i;
                end
                default: begin
                end
            endcase
        end





        case (exception_type_i)
            `EXECEPTION_INT: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd0;
            end
            `EXECEPTION_ADEL: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd4;
                if (current_inst_addr_i[1:0] != 2'b00) badvaddr_o <= current_inst_addr_i;
                else badvaddr_o <= mem_data_addr_i;
            end
            `EXECEPTION_ADES: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd5;
                badvaddr_o <= mem_data_addr_i;
            end
            `EXECEPTION_SYS: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd8;
            end
            `EXECEPTION_BREAK: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd9;
            end
            `EXECEPTION_INSTVALID: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd10;
            end
            `EXECEPTION_OV: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd12;
            end
            `EXECEPTION_ERET: begin

                status_o[1] <= 1'b0;
            end
            default: begin
            end
        endcase

    end
end





always @(*) begin
    if (resetn == `RstEnable) begin
        data_o = `ZeroWord;
    end else begin
        case (raddr_i)
            `CP0_REG_BADVADDR: begin
                data_o = badvaddr_o;
            end
            `CP0_REG_COUNT: begin
                data_o = count_o;
            end
            `CP0_REG_COMPARE: begin
                data_o = compare_o;
            end
            `CP0_REG_STATUS: begin
                data_o = status_o;
            end
            `CP0_REG_CAUSE: begin
                data_o = cause_o;
            end
            `CP0_REG_EPC: begin
                data_o = epc_o;
            end
            `CP0_REG_EBASE: begin
                data_o = ebase_o;
            end
            default: begin
                data_o = `ZeroWord;
            end
        endcase
    end
end





endmodule
module cp0_reg(
    input                           clk,
    input                           resetn,

    input                           wen_i,
    input   [`RegAddrBus]           waddr_i,
    input   [`RegAddrBus]           raddr_i,
    input   [`RegBus]               data_i,
    output  reg[`RegBus]            data_o,

    input   [`RegBus]               exception_type_i,
    input   [5:0]                   int_i,
    input   [`RegBus]               current_inst_addr_i,
    input   [`RegBus]               mem_data_addr_i,
    input                           is_in_delayslot_i,

    output  reg[`RegBus]            badvaddr_o,
    output  reg[`RegBus]            count_o,
    output  reg[`RegBus]            compare_o,
    output  reg[`RegBus]            status_o,
    output  reg[`RegBus]            cause_o,
    output  reg[`RegBus]            epc_o,
    output  reg[`RegBus]            ebase_o,



    output  reg                     timer_int_o
);



reg clk_double;

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        clk_double <= 1'b0;
        badvaddr_o <= `ZeroWord;
        count_o <= `ZeroWord;
        compare_o <= `ZeroWord;
        status_o <= `CP0_REG_STATUS_RESET_VALUE;
        cause_o <= `ZeroWord;
        epc_o <= `ZeroWord;
        ebase_o <= `ExceptionInitialPC;
        timer_int_o <= `InterruptNotAssert;
    end else begin

        clk_double <= ~clk_double;
        if (clk_double) count_o <= count_o + 1;
        cause_o[15:10] <= int_i;
        cause_o[30] <= timer_int_o;

        if ((compare_o != `ZeroWord) && (count_o == compare_o)) timer_int_o <= `InterruptAssert;





        if (wen_i == `WriteEnable) begin
            case (waddr_i)
                `CP0_REG_COUNT: begin
                    clk_double <= 1'b0;
                    count_o <= data_i;
                end
                `CP0_REG_COMPARE: begin
                    compare_o <= data_i;
                    timer_int_o <= `InterruptNotAssert;
                end
                `CP0_REG_STATUS: begin
                    status_o[15:8] <= data_i[15:8];
                    status_o[1:0] <= data_i[1:0];
                end
                `CP0_REG_CAUSE: begin
                    cause_o[9:8] <= data_i[9:8];
                end
                `CP0_REG_EPC: begin
                    epc_o <= data_i;
                end
                `CP0_REG_EBASE: begin
                    ebase_o <= data_i;
                end
                default: begin
                end
            endcase
        end





        case (exception_type_i)
            `EXECEPTION_INT: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd0;
            end
            `EXECEPTION_ADEL: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd4;
                if (current_inst_addr_i[1:0] != 2'b00) badvaddr_o <= current_inst_addr_i;
                else badvaddr_o <= mem_data_addr_i;
            end
            `EXECEPTION_ADES: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd5;
                badvaddr_o <= mem_data_addr_i;
            end
            `EXECEPTION_SYS: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd8;
            end
            `EXECEPTION_BREAK: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd9;
            end
            `EXECEPTION_INSTVALID: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd10;
            end
            `EXECEPTION_OV: begin

                if (status_o[1] == 1'b0) begin
                    if (is_in_delayslot_i == `InDelaySlot) begin
                        epc_o <= current_inst_addr_i - 4;
                        cause_o[31] <= 1'b1;
                    end else begin
                        epc_o <= current_inst_addr_i;
                        cause_o[31] <= 1'b0;
                    end
                end
                status_o[1] <= 1'b1;
                cause_o[6:2] <= 5'd12;
            end
            `EXECEPTION_ERET: begin

                status_o[1] <= 1'b0;
            end
            default: begin
            end
        endcase

    end
end





always @(*) begin
    if (resetn == `RstEnable) begin
        data_o = `ZeroWord;
    end else begin
        case (raddr_i)
            `CP0_REG_BADVADDR: begin
                data_o = badvaddr_o;
            end
            `CP0_REG_COUNT: begin
                data_o = count_o;
            end
            `CP0_REG_COMPARE: begin
                data_o = compare_o;
            end
            `CP0_REG_STATUS: begin
                data_o = status_o;
            end
            `CP0_REG_CAUSE: begin
                data_o = cause_o;
            end
            `CP0_REG_EPC: begin
                data_o = epc_o;
            end
            `CP0_REG_EBASE: begin
                data_o = ebase_o;
            end
            default: begin
                data_o = `ZeroWord;
            end
        endcase
    end
end





endmodule