data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:6: Cannot find file containing module: \'g_fullsub\'\n    g_fullsub g(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412284801/adders/fullsubtractor,data/full_repos/permissive/412284801/g_fullsub\n             data/full_repos/permissive/412284801/adders/fullsubtractor,data/full_repos/permissive/412284801/g_fullsub.v\n             data/full_repos/permissive/412284801/adders/fullsubtractor,data/full_repos/permissive/412284801/g_fullsub.sv\n             g_fullsub\n             g_fullsub.v\n             g_fullsub.sv\n             obj_dir/g_fullsub\n             obj_dir/g_fullsub.v\n             obj_dir/g_fullsub.sv\n%Error: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:13: Cannot find file containing module: \'d_fullsub\'\n    d_fullsub d(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/412284801/adders/fullsubtractor/fullsub_tb.v:20: Cannot find file containing module: \'b_fullsub\'\n    b_fullsub B(\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fullsub_tb;
    reg a,b,bin;
    wire ds,bs,gs;
    wire dc,bc,gc;

    g_fullsub g(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(gc),
        .d(gs)
    );
    d_fullsub d(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(dc),
        .d(ds)
    );
    b_fullsub B(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(bc),
        .d(bs)
    );

    initial
    begin
        bin =0;
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
        bin =1;
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
    end
endmodule
module fullsub_tb;

    reg a,b,bin;
    wire ds,bs,gs;
    wire dc,bc,gc;

    g_fullsub g(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(gc),
        .d(gs)
    );
    d_fullsub d(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(dc),
        .d(ds)
    );
    b_fullsub B(
        .a(a),
        .b(b),
        .bin(bin),
        .bout(bc),
        .d(bs)
    );

    initial
    begin
        bin =0;
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
        bin =1;
        a = 1;
        b = 0;
        #100;
        a = 1;
        b = 1;
        #100;
        a = 0;
        b = 0;
        #100;
        a = 0;
        b = 1;
        #100;
    end
endmodule