data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v
1: b"%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v:161: Cannot find file containing module: 'ZBT_bank_connections'\nZBT_bank_connections bank0_inst(\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/ZBT,data/full_repos/permissive/502764644/ZBT_bank_connections\n             data/full_repos/permissive/502764644/mpeg_audio_video/ZBT,data/full_repos/permissive/502764644/ZBT_bank_connections.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ZBT,data/full_repos/permissive/502764644/ZBT_bank_connections.sv\n             ZBT_bank_connections\n             ZBT_bank_connections.v\n             ZBT_bank_connections.sv\n             obj_dir/ZBT_bank_connections\n             obj_dir/ZBT_bank_connections.v\n             obj_dir/ZBT_bank_connections.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v:185: Cannot find file containing module: 'ZBT_bank_connections'\nZBT_bank_connections bank1_inst(\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v:209: Cannot find file containing module: 'ZBT_bank_connections'\nZBT_bank_connections bank2_inst(\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v:233: Cannot find file containing module: 'ZBT_bank_connections'\nZBT_bank_connections bank3_inst(\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ZBT/ZBT_connections.v:257: Cannot find file containing module: 'ZBT_bank_connections'\nZBT_bank_connections bank4_inst(\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ZBT_connections(
	MEMORY_BANK0_CLK_P,
	MEMORY_BANK0_CLKEN_N,
	MEMORY_BANK0_WEN_N,
	MEMORY_BANK0_WENA_N,
	MEMORY_BANK0_WENB_N,
	MEMORY_BANK0_WENC_N,
	MEMORY_BANK0_WEND_N,
	MEMORY_BANK0_ADV_LD_N,
	MEMORY_BANK0_OEN_N,
	MEMORY_BANK0_CEN_N,
	MEMORY_BANK0_ADDR_P,
	MEMORY_BANK0_DATA_A_P,
	MEMORY_BANK0_DATA_B_P,
	MEMORY_BANK0_DATA_C_P,
	MEMORY_BANK0_DATA_D_P,

	MEMORY_BANK1_CLK_P,
	MEMORY_BANK1_CLKEN_N,
	MEMORY_BANK1_WEN_N,
	MEMORY_BANK1_WENA_N,
	MEMORY_BANK1_WENB_N,
	MEMORY_BANK1_WENC_N,
	MEMORY_BANK1_WEND_N,
	MEMORY_BANK1_ADV_LD_N,
	MEMORY_BANK1_OEN_N,
	MEMORY_BANK1_CEN_N,
	MEMORY_BANK1_ADDR_P,
	MEMORY_BANK1_DATA_A_P,
	MEMORY_BANK1_DATA_B_P,
	MEMORY_BANK1_DATA_C_P,
	MEMORY_BANK1_DATA_D_P,

	MEMORY_BANK2_CLK_P,
	MEMORY_BANK2_CLKEN_N,
	MEMORY_BANK2_WEN_N,
	MEMORY_BANK2_WENA_N,
	MEMORY_BANK2_WENB_N,
	MEMORY_BANK2_WENC_N,
	MEMORY_BANK2_WEND_N,
	MEMORY_BANK2_ADV_LD_N,
	MEMORY_BANK2_OEN_N,
	MEMORY_BANK2_CEN_N,
	MEMORY_BANK2_ADDR_P,
	MEMORY_BANK2_DATA_A_P,
	MEMORY_BANK2_DATA_B_P,
	MEMORY_BANK2_DATA_C_P,
	MEMORY_BANK2_DATA_D_P,

	MEMORY_BANK3_CLK_P,
	MEMORY_BANK3_CLKEN_N,
	MEMORY_BANK3_WEN_N,
	MEMORY_BANK3_WENA_N,
	MEMORY_BANK3_WENB_N,
	MEMORY_BANK3_WENC_N,
	MEMORY_BANK3_WEND_N,
	MEMORY_BANK3_ADV_LD_N,
	MEMORY_BANK3_OEN_N,
	MEMORY_BANK3_CEN_N,
	MEMORY_BANK3_ADDR_P,
	MEMORY_BANK3_DATA_A_P,
	MEMORY_BANK3_DATA_B_P,
	MEMORY_BANK3_DATA_C_P,
	MEMORY_BANK3_DATA_D_P,

	MEMORY_BANK4_CLK_P,
	MEMORY_BANK4_CLKEN_N,
	MEMORY_BANK4_WEN_N,
	MEMORY_BANK4_WENA_N,
	MEMORY_BANK4_WENB_N,
	MEMORY_BANK4_WENC_N,
	MEMORY_BANK4_WEND_N,
	MEMORY_BANK4_ADV_LD_N,
	MEMORY_BANK4_OEN_N,
	MEMORY_BANK4_CEN_N,
	MEMORY_BANK4_ADDR_P,
	MEMORY_BANK4_DATA_A_P,
	MEMORY_BANK4_DATA_B_P,
	MEMORY_BANK4_DATA_C_P,
	MEMORY_BANK4_DATA_D_P,

	internal_clock_bank0,
	external_clock_bank0,
	read_data_bank0,
	write_data_bank0,
	address_bank0,
	data_direction_bank0,

	internal_clock_bank1,
	external_clock_bank1,
	read_data_bank1,
	write_data_bank1,
	address_bank1,
	data_direction_bank1,

	internal_clock_bank2,
	external_clock_bank2,
	read_data_bank2,
	write_data_bank2,
	address_bank2,
	data_direction_bank2,

	internal_clock_bank3,
	external_clock_bank3,
	read_data_bank3,
	write_data_bank3,
	address_bank3,
	data_direction_bank3,

	internal_clock_bank4,
	external_clock_bank4,
	read_data_bank4,
	write_data_bank4,
	address_bank4,
	data_direction_bank4
);


output 			MEMORY_BANK0_CLK_P,		MEMORY_BANK1_CLK_P,		MEMORY_BANK2_CLK_P,		MEMORY_BANK3_CLK_P,		MEMORY_BANK4_CLK_P;
output 			MEMORY_BANK0_CLKEN_N,	MEMORY_BANK1_CLKEN_N,	MEMORY_BANK2_CLKEN_N,	MEMORY_BANK3_CLKEN_N,	MEMORY_BANK4_CLKEN_N;
output 			MEMORY_BANK0_WEN_N,		MEMORY_BANK1_WEN_N,		MEMORY_BANK2_WEN_N,		MEMORY_BANK3_WEN_N,		MEMORY_BANK4_WEN_N;
output 			MEMORY_BANK0_WENA_N,		MEMORY_BANK1_WENA_N,		MEMORY_BANK2_WENA_N,		MEMORY_BANK3_WENA_N,		MEMORY_BANK4_WENA_N;
output 			MEMORY_BANK0_WENB_N,		MEMORY_BANK1_WENB_N,		MEMORY_BANK2_WENB_N,		MEMORY_BANK3_WENB_N,		MEMORY_BANK4_WENB_N;
output 			MEMORY_BANK0_WENC_N,		MEMORY_BANK1_WENC_N,		MEMORY_BANK2_WENC_N,		MEMORY_BANK3_WENC_N,		MEMORY_BANK4_WENC_N;
output 			MEMORY_BANK0_WEND_N,		MEMORY_BANK1_WEND_N,		MEMORY_BANK2_WEND_N,		MEMORY_BANK3_WEND_N,		MEMORY_BANK4_WEND_N;
output 			MEMORY_BANK0_ADV_LD_N,	MEMORY_BANK1_ADV_LD_N,	MEMORY_BANK2_ADV_LD_N,	MEMORY_BANK3_ADV_LD_N,	MEMORY_BANK4_ADV_LD_N;
output 			MEMORY_BANK0_OEN_N,		MEMORY_BANK1_OEN_N,		MEMORY_BANK2_OEN_N,		MEMORY_BANK3_OEN_N,		MEMORY_BANK4_OEN_N;
output 			MEMORY_BANK0_CEN_N,		MEMORY_BANK1_CEN_N,		MEMORY_BANK2_CEN_N,		MEMORY_BANK3_CEN_N,		MEMORY_BANK4_CEN_N;
output [18:0]	MEMORY_BANK0_ADDR_P,		MEMORY_BANK1_ADDR_P,		MEMORY_BANK2_ADDR_P,		MEMORY_BANK3_ADDR_P,		MEMORY_BANK4_ADDR_P;
inout  [7:0] 	MEMORY_BANK0_DATA_A_P,	MEMORY_BANK1_DATA_A_P,	MEMORY_BANK2_DATA_A_P,	MEMORY_BANK3_DATA_A_P,	MEMORY_BANK4_DATA_A_P;
inout  [7:0] 	MEMORY_BANK0_DATA_B_P,	MEMORY_BANK1_DATA_B_P,	MEMORY_BANK2_DATA_B_P,	MEMORY_BANK3_DATA_B_P,	MEMORY_BANK4_DATA_B_P;
inout  [7:0] 	MEMORY_BANK0_DATA_C_P,	MEMORY_BANK1_DATA_C_P,	MEMORY_BANK2_DATA_C_P,	MEMORY_BANK3_DATA_C_P,	MEMORY_BANK4_DATA_C_P;
inout  [7:0] 	MEMORY_BANK0_DATA_D_P,	MEMORY_BANK1_DATA_D_P,	MEMORY_BANK2_DATA_D_P,	MEMORY_BANK3_DATA_D_P,	MEMORY_BANK4_DATA_D_P;



input 			internal_clock_bank0,	internal_clock_bank1,	internal_clock_bank2,	internal_clock_bank3,	internal_clock_bank4;
input 			external_clock_bank0,	external_clock_bank1,	external_clock_bank2,	external_clock_bank3,	external_clock_bank4;
input				data_direction_bank0,	data_direction_bank1,	data_direction_bank2,	data_direction_bank3,	data_direction_bank4;
output [31:0]	read_data_bank0,			read_data_bank1,			read_data_bank2,			read_data_bank3,			read_data_bank4;
input  [31:0]	write_data_bank0,			write_data_bank1,			write_data_bank2,			write_data_bank3,			write_data_bank4;
input  [18:0]	address_bank0,				address_bank1,				address_bank2,				address_bank3,				address_bank4;

ZBT_bank_connections bank0_inst(
	internal_clock_bank0,
	external_clock_bank0,
	read_data_bank0,
	write_data_bank0,
	address_bank0,
	data_direction_bank0,
   MEMORY_BANK0_CLK_P,
   MEMORY_BANK0_CLKEN_N,
   MEMORY_BANK0_WEN_N,
   MEMORY_BANK0_WENA_N,
   MEMORY_BANK0_WENB_N,
   MEMORY_BANK0_WENC_N,
   MEMORY_BANK0_WEND_N,
   MEMORY_BANK0_ADV_LD_N,
   MEMORY_BANK0_OEN_N,
   MEMORY_BANK0_CEN_N,
   MEMORY_BANK0_ADDR_P,
   MEMORY_BANK0_DATA_A_P,
   MEMORY_BANK0_DATA_B_P,
   MEMORY_BANK0_DATA_C_P,
   MEMORY_BANK0_DATA_D_P
);

ZBT_bank_connections bank1_inst(
	internal_clock_bank1,
	external_clock_bank1,
	read_data_bank1,
	write_data_bank1,
	address_bank1,
	data_direction_bank1,
   MEMORY_BANK1_CLK_P,
   MEMORY_BANK1_CLKEN_N,
   MEMORY_BANK1_WEN_N,
   MEMORY_BANK1_WENA_N,
   MEMORY_BANK1_WENB_N,
   MEMORY_BANK1_WENC_N,
   MEMORY_BANK1_WEND_N,
   MEMORY_BANK1_ADV_LD_N,
   MEMORY_BANK1_OEN_N,
   MEMORY_BANK1_CEN_N,
   MEMORY_BANK1_ADDR_P,
   MEMORY_BANK1_DATA_A_P,
   MEMORY_BANK1_DATA_B_P,
   MEMORY_BANK1_DATA_C_P,
   MEMORY_BANK1_DATA_D_P
);

ZBT_bank_connections bank2_inst(
	internal_clock_bank2,
	external_clock_bank2,
	read_data_bank2,
	write_data_bank2,
	address_bank2,
	data_direction_bank2,
   MEMORY_BANK2_CLK_P,
   MEMORY_BANK2_CLKEN_N,
   MEMORY_BANK2_WEN_N,
   MEMORY_BANK2_WENA_N,
   MEMORY_BANK2_WENB_N,
   MEMORY_BANK2_WENC_N,
   MEMORY_BANK2_WEND_N,
   MEMORY_BANK2_ADV_LD_N,
   MEMORY_BANK2_OEN_N,
   MEMORY_BANK2_CEN_N,
   MEMORY_BANK2_ADDR_P,
   MEMORY_BANK2_DATA_A_P,
   MEMORY_BANK2_DATA_B_P,
   MEMORY_BANK2_DATA_C_P,
   MEMORY_BANK2_DATA_D_P
);

ZBT_bank_connections bank3_inst(
	internal_clock_bank3,
	external_clock_bank3,
	read_data_bank3,
	write_data_bank3,
	address_bank3,
	data_direction_bank3,
   MEMORY_BANK3_CLK_P,
   MEMORY_BANK3_CLKEN_N,
   MEMORY_BANK3_WEN_N,
   MEMORY_BANK3_WENA_N,
   MEMORY_BANK3_WENB_N,
   MEMORY_BANK3_WENC_N,
   MEMORY_BANK3_WEND_N,
   MEMORY_BANK3_ADV_LD_N,
   MEMORY_BANK3_OEN_N,
   MEMORY_BANK3_CEN_N,
   MEMORY_BANK3_ADDR_P,
   MEMORY_BANK3_DATA_A_P,
   MEMORY_BANK3_DATA_B_P,
   MEMORY_BANK3_DATA_C_P,
   MEMORY_BANK3_DATA_D_P
);

ZBT_bank_connections bank4_inst(
	internal_clock_bank4,
	external_clock_bank4,
	read_data_bank4,
	write_data_bank4,
	address_bank4,
	data_direction_bank4,
   MEMORY_BANK4_CLK_P,
   MEMORY_BANK4_CLKEN_N,
   MEMORY_BANK4_WEN_N,
   MEMORY_BANK4_WENA_N,
   MEMORY_BANK4_WENB_N,
   MEMORY_BANK4_WENC_N,
   MEMORY_BANK4_WEND_N,
   MEMORY_BANK4_ADV_LD_N,
   MEMORY_BANK4_OEN_N,
   MEMORY_BANK4_CEN_N,
   MEMORY_BANK4_ADDR_P,
   MEMORY_BANK4_DATA_A_P,
   MEMORY_BANK4_DATA_B_P,
   MEMORY_BANK4_DATA_C_P,
   MEMORY_BANK4_DATA_D_P
);

endmodule
module ZBT_connections(
	MEMORY_BANK0_CLK_P,
	MEMORY_BANK0_CLKEN_N,
	MEMORY_BANK0_WEN_N,
	MEMORY_BANK0_WENA_N,
	MEMORY_BANK0_WENB_N,
	MEMORY_BANK0_WENC_N,
	MEMORY_BANK0_WEND_N,
	MEMORY_BANK0_ADV_LD_N,
	MEMORY_BANK0_OEN_N,
	MEMORY_BANK0_CEN_N,
	MEMORY_BANK0_ADDR_P,
	MEMORY_BANK0_DATA_A_P,
	MEMORY_BANK0_DATA_B_P,
	MEMORY_BANK0_DATA_C_P,
	MEMORY_BANK0_DATA_D_P,

	MEMORY_BANK1_CLK_P,
	MEMORY_BANK1_CLKEN_N,
	MEMORY_BANK1_WEN_N,
	MEMORY_BANK1_WENA_N,
	MEMORY_BANK1_WENB_N,
	MEMORY_BANK1_WENC_N,
	MEMORY_BANK1_WEND_N,
	MEMORY_BANK1_ADV_LD_N,
	MEMORY_BANK1_OEN_N,
	MEMORY_BANK1_CEN_N,
	MEMORY_BANK1_ADDR_P,
	MEMORY_BANK1_DATA_A_P,
	MEMORY_BANK1_DATA_B_P,
	MEMORY_BANK1_DATA_C_P,
	MEMORY_BANK1_DATA_D_P,

	MEMORY_BANK2_CLK_P,
	MEMORY_BANK2_CLKEN_N,
	MEMORY_BANK2_WEN_N,
	MEMORY_BANK2_WENA_N,
	MEMORY_BANK2_WENB_N,
	MEMORY_BANK2_WENC_N,
	MEMORY_BANK2_WEND_N,
	MEMORY_BANK2_ADV_LD_N,
	MEMORY_BANK2_OEN_N,
	MEMORY_BANK2_CEN_N,
	MEMORY_BANK2_ADDR_P,
	MEMORY_BANK2_DATA_A_P,
	MEMORY_BANK2_DATA_B_P,
	MEMORY_BANK2_DATA_C_P,
	MEMORY_BANK2_DATA_D_P,

	MEMORY_BANK3_CLK_P,
	MEMORY_BANK3_CLKEN_N,
	MEMORY_BANK3_WEN_N,
	MEMORY_BANK3_WENA_N,
	MEMORY_BANK3_WENB_N,
	MEMORY_BANK3_WENC_N,
	MEMORY_BANK3_WEND_N,
	MEMORY_BANK3_ADV_LD_N,
	MEMORY_BANK3_OEN_N,
	MEMORY_BANK3_CEN_N,
	MEMORY_BANK3_ADDR_P,
	MEMORY_BANK3_DATA_A_P,
	MEMORY_BANK3_DATA_B_P,
	MEMORY_BANK3_DATA_C_P,
	MEMORY_BANK3_DATA_D_P,

	MEMORY_BANK4_CLK_P,
	MEMORY_BANK4_CLKEN_N,
	MEMORY_BANK4_WEN_N,
	MEMORY_BANK4_WENA_N,
	MEMORY_BANK4_WENB_N,
	MEMORY_BANK4_WENC_N,
	MEMORY_BANK4_WEND_N,
	MEMORY_BANK4_ADV_LD_N,
	MEMORY_BANK4_OEN_N,
	MEMORY_BANK4_CEN_N,
	MEMORY_BANK4_ADDR_P,
	MEMORY_BANK4_DATA_A_P,
	MEMORY_BANK4_DATA_B_P,
	MEMORY_BANK4_DATA_C_P,
	MEMORY_BANK4_DATA_D_P,

	internal_clock_bank0,
	external_clock_bank0,
	read_data_bank0,
	write_data_bank0,
	address_bank0,
	data_direction_bank0,

	internal_clock_bank1,
	external_clock_bank1,
	read_data_bank1,
	write_data_bank1,
	address_bank1,
	data_direction_bank1,

	internal_clock_bank2,
	external_clock_bank2,
	read_data_bank2,
	write_data_bank2,
	address_bank2,
	data_direction_bank2,

	internal_clock_bank3,
	external_clock_bank3,
	read_data_bank3,
	write_data_bank3,
	address_bank3,
	data_direction_bank3,

	internal_clock_bank4,
	external_clock_bank4,
	read_data_bank4,
	write_data_bank4,
	address_bank4,
	data_direction_bank4
);



output 			MEMORY_BANK0_CLK_P,		MEMORY_BANK1_CLK_P,		MEMORY_BANK2_CLK_P,		MEMORY_BANK3_CLK_P,		MEMORY_BANK4_CLK_P;
output 			MEMORY_BANK0_CLKEN_N,	MEMORY_BANK1_CLKEN_N,	MEMORY_BANK2_CLKEN_N,	MEMORY_BANK3_CLKEN_N,	MEMORY_BANK4_CLKEN_N;
output 			MEMORY_BANK0_WEN_N,		MEMORY_BANK1_WEN_N,		MEMORY_BANK2_WEN_N,		MEMORY_BANK3_WEN_N,		MEMORY_BANK4_WEN_N;
output 			MEMORY_BANK0_WENA_N,		MEMORY_BANK1_WENA_N,		MEMORY_BANK2_WENA_N,		MEMORY_BANK3_WENA_N,		MEMORY_BANK4_WENA_N;
output 			MEMORY_BANK0_WENB_N,		MEMORY_BANK1_WENB_N,		MEMORY_BANK2_WENB_N,		MEMORY_BANK3_WENB_N,		MEMORY_BANK4_WENB_N;
output 			MEMORY_BANK0_WENC_N,		MEMORY_BANK1_WENC_N,		MEMORY_BANK2_WENC_N,		MEMORY_BANK3_WENC_N,		MEMORY_BANK4_WENC_N;
output 			MEMORY_BANK0_WEND_N,		MEMORY_BANK1_WEND_N,		MEMORY_BANK2_WEND_N,		MEMORY_BANK3_WEND_N,		MEMORY_BANK4_WEND_N;
output 			MEMORY_BANK0_ADV_LD_N,	MEMORY_BANK1_ADV_LD_N,	MEMORY_BANK2_ADV_LD_N,	MEMORY_BANK3_ADV_LD_N,	MEMORY_BANK4_ADV_LD_N;
output 			MEMORY_BANK0_OEN_N,		MEMORY_BANK1_OEN_N,		MEMORY_BANK2_OEN_N,		MEMORY_BANK3_OEN_N,		MEMORY_BANK4_OEN_N;
output 			MEMORY_BANK0_CEN_N,		MEMORY_BANK1_CEN_N,		MEMORY_BANK2_CEN_N,		MEMORY_BANK3_CEN_N,		MEMORY_BANK4_CEN_N;
output [18:0]	MEMORY_BANK0_ADDR_P,		MEMORY_BANK1_ADDR_P,		MEMORY_BANK2_ADDR_P,		MEMORY_BANK3_ADDR_P,		MEMORY_BANK4_ADDR_P;
inout  [7:0] 	MEMORY_BANK0_DATA_A_P,	MEMORY_BANK1_DATA_A_P,	MEMORY_BANK2_DATA_A_P,	MEMORY_BANK3_DATA_A_P,	MEMORY_BANK4_DATA_A_P;
inout  [7:0] 	MEMORY_BANK0_DATA_B_P,	MEMORY_BANK1_DATA_B_P,	MEMORY_BANK2_DATA_B_P,	MEMORY_BANK3_DATA_B_P,	MEMORY_BANK4_DATA_B_P;
inout  [7:0] 	MEMORY_BANK0_DATA_C_P,	MEMORY_BANK1_DATA_C_P,	MEMORY_BANK2_DATA_C_P,	MEMORY_BANK3_DATA_C_P,	MEMORY_BANK4_DATA_C_P;
inout  [7:0] 	MEMORY_BANK0_DATA_D_P,	MEMORY_BANK1_DATA_D_P,	MEMORY_BANK2_DATA_D_P,	MEMORY_BANK3_DATA_D_P,	MEMORY_BANK4_DATA_D_P;



input 			internal_clock_bank0,	internal_clock_bank1,	internal_clock_bank2,	internal_clock_bank3,	internal_clock_bank4;
input 			external_clock_bank0,	external_clock_bank1,	external_clock_bank2,	external_clock_bank3,	external_clock_bank4;
input				data_direction_bank0,	data_direction_bank1,	data_direction_bank2,	data_direction_bank3,	data_direction_bank4;
output [31:0]	read_data_bank0,			read_data_bank1,			read_data_bank2,			read_data_bank3,			read_data_bank4;
input  [31:0]	write_data_bank0,			write_data_bank1,			write_data_bank2,			write_data_bank3,			write_data_bank4;
input  [18:0]	address_bank0,				address_bank1,				address_bank2,				address_bank3,				address_bank4;

ZBT_bank_connections bank0_inst(
	internal_clock_bank0,
	external_clock_bank0,
	read_data_bank0,
	write_data_bank0,
	address_bank0,
	data_direction_bank0,
   MEMORY_BANK0_CLK_P,
   MEMORY_BANK0_CLKEN_N,
   MEMORY_BANK0_WEN_N,
   MEMORY_BANK0_WENA_N,
   MEMORY_BANK0_WENB_N,
   MEMORY_BANK0_WENC_N,
   MEMORY_BANK0_WEND_N,
   MEMORY_BANK0_ADV_LD_N,
   MEMORY_BANK0_OEN_N,
   MEMORY_BANK0_CEN_N,
   MEMORY_BANK0_ADDR_P,
   MEMORY_BANK0_DATA_A_P,
   MEMORY_BANK0_DATA_B_P,
   MEMORY_BANK0_DATA_C_P,
   MEMORY_BANK0_DATA_D_P
);

ZBT_bank_connections bank1_inst(
	internal_clock_bank1,
	external_clock_bank1,
	read_data_bank1,
	write_data_bank1,
	address_bank1,
	data_direction_bank1,
   MEMORY_BANK1_CLK_P,
   MEMORY_BANK1_CLKEN_N,
   MEMORY_BANK1_WEN_N,
   MEMORY_BANK1_WENA_N,
   MEMORY_BANK1_WENB_N,
   MEMORY_BANK1_WENC_N,
   MEMORY_BANK1_WEND_N,
   MEMORY_BANK1_ADV_LD_N,
   MEMORY_BANK1_OEN_N,
   MEMORY_BANK1_CEN_N,
   MEMORY_BANK1_ADDR_P,
   MEMORY_BANK1_DATA_A_P,
   MEMORY_BANK1_DATA_B_P,
   MEMORY_BANK1_DATA_C_P,
   MEMORY_BANK1_DATA_D_P
);

ZBT_bank_connections bank2_inst(
	internal_clock_bank2,
	external_clock_bank2,
	read_data_bank2,
	write_data_bank2,
	address_bank2,
	data_direction_bank2,
   MEMORY_BANK2_CLK_P,
   MEMORY_BANK2_CLKEN_N,
   MEMORY_BANK2_WEN_N,
   MEMORY_BANK2_WENA_N,
   MEMORY_BANK2_WENB_N,
   MEMORY_BANK2_WENC_N,
   MEMORY_BANK2_WEND_N,
   MEMORY_BANK2_ADV_LD_N,
   MEMORY_BANK2_OEN_N,
   MEMORY_BANK2_CEN_N,
   MEMORY_BANK2_ADDR_P,
   MEMORY_BANK2_DATA_A_P,
   MEMORY_BANK2_DATA_B_P,
   MEMORY_BANK2_DATA_C_P,
   MEMORY_BANK2_DATA_D_P
);

ZBT_bank_connections bank3_inst(
	internal_clock_bank3,
	external_clock_bank3,
	read_data_bank3,
	write_data_bank3,
	address_bank3,
	data_direction_bank3,
   MEMORY_BANK3_CLK_P,
   MEMORY_BANK3_CLKEN_N,
   MEMORY_BANK3_WEN_N,
   MEMORY_BANK3_WENA_N,
   MEMORY_BANK3_WENB_N,
   MEMORY_BANK3_WENC_N,
   MEMORY_BANK3_WEND_N,
   MEMORY_BANK3_ADV_LD_N,
   MEMORY_BANK3_OEN_N,
   MEMORY_BANK3_CEN_N,
   MEMORY_BANK3_ADDR_P,
   MEMORY_BANK3_DATA_A_P,
   MEMORY_BANK3_DATA_B_P,
   MEMORY_BANK3_DATA_C_P,
   MEMORY_BANK3_DATA_D_P
);

ZBT_bank_connections bank4_inst(
	internal_clock_bank4,
	external_clock_bank4,
	read_data_bank4,
	write_data_bank4,
	address_bank4,
	data_direction_bank4,
   MEMORY_BANK4_CLK_P,
   MEMORY_BANK4_CLKEN_N,
   MEMORY_BANK4_WEN_N,
   MEMORY_BANK4_WENA_N,
   MEMORY_BANK4_WENB_N,
   MEMORY_BANK4_WENC_N,
   MEMORY_BANK4_WEND_N,
   MEMORY_BANK4_ADV_LD_N,
   MEMORY_BANK4_OEN_N,
   MEMORY_BANK4_CEN_N,
   MEMORY_BANK4_ADDR_P,
   MEMORY_BANK4_DATA_A_P,
   MEMORY_BANK4_DATA_B_P,
   MEMORY_BANK4_DATA_C_P,
   MEMORY_BANK4_DATA_D_P
);

endmodule