data/full_repos/permissive/412297935/hdl/busMonitor.v
1: b'%Error: data/full_repos/permissive/412297935/hdl/busMonitor.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module BusMonitor
	(
    input 	wire		clk,
	input 	wire		a8_clk,
	input	wire		a8_rst_n,
	output 	wire		a8_addr_strobe,
	output 	wire		a8_write_strobe,
	output 	wire		a8_read_strobe,
	output 	wire		a8_clk_falling
	);

	




	localparam 	TICK_BITS				= 7;
	localparam 	TICK_ADDRESS_VALID		= 16;
	localparam 	TICK_WRITE_VALID		= 42;
	localparam 	TICK_READ_VALID			= 48;
	




	(* async_reg = "true" *) reg [2:0] clkDetect;  
	always @(posedge clk) 
		if (a8_rst_n == 1'b0)
			clkDetect <= 3'b0;
		else
			clkDetect <= {clkDetect[1:0], a8_clk};




	wire a8_clk_rising		= (clkDetect[2:1]==2'b01);   
	assign a8_clk_falling	= (clkDetect[2:1]==2'b10);  




	reg  [1:0] 	validClocks;
	always @(posedge clk)
		if (a8_rst_n == 1'b0)
			validClocks <= 2'b00;
		else
			begin
				if (a8_clk_rising == 1'b1)
					validClocks[0] <= 1'b1;
				if (a8_clk_falling == 1'b1)
					validClocks[1] <= 1'b1;
			end
	assign clkValid = validClocks[0] | validClocks[1];




	wire a8_clk_rising_valid		= a8_clk_rising & clkValid;   
	wire a8_clk_falling_valid		= a8_clk_falling & clkValid;  
	



	reg	[TICK_BITS-1:0]			ticks;
		
	always @ (posedge clk)
		if (a8_rst_n == 1'b0)
			begin
				ticks	<= {TICK_BITS{1'b0}};
			end
		else
			begin
				if (a8_clk_falling_valid == 1'b1)
					begin
						ticks 	<= {TICK_BITS{1'b0}};
					end
				else
					ticks	<= ticks + 7'b1;
			end
	



	assign a8_addr_strobe 	= (ticks == TICK_ADDRESS_VALID);
	assign a8_write_strobe	= (ticks == TICK_WRITE_VALID);
	assign a8_read_strobe	= (ticks == TICK_READ_VALID);

endmodule
module BusMonitor
	(
    input 	wire		clk,
	input 	wire		a8_clk,
	input	wire		a8_rst_n,
	output 	wire		a8_addr_strobe,
	output 	wire		a8_write_strobe,
	output 	wire		a8_read_strobe,
	output 	wire		a8_clk_falling
	);


	




	localparam 	TICK_BITS				= 7;
	localparam 	TICK_ADDRESS_VALID		= 16;
	localparam 	TICK_WRITE_VALID		= 42;
	localparam 	TICK_READ_VALID			= 48;
	




	(* async_reg = "true" *) reg [2:0] clkDetect;  
	always @(posedge clk) 
		if (a8_rst_n == 1'b0)
			clkDetect <= 3'b0;
		else
			clkDetect <= {clkDetect[1:0], a8_clk};




	wire a8_clk_rising		= (clkDetect[2:1]==2'b01);   
	assign a8_clk_falling	= (clkDetect[2:1]==2'b10);  




	reg  [1:0] 	validClocks;
	always @(posedge clk)
		if (a8_rst_n == 1'b0)
			validClocks <= 2'b00;
		else
			begin
				if (a8_clk_rising == 1'b1)
					validClocks[0] <= 1'b1;
				if (a8_clk_falling == 1'b1)
					validClocks[1] <= 1'b1;
			end
	assign clkValid = validClocks[0] | validClocks[1];




	wire a8_clk_rising_valid		= a8_clk_rising & clkValid;   
	wire a8_clk_falling_valid		= a8_clk_falling & clkValid;  
	



	reg	[TICK_BITS-1:0]			ticks;
		
	always @ (posedge clk)
		if (a8_rst_n == 1'b0)
			begin
				ticks	<= {TICK_BITS{1'b0}};
			end
		else
			begin
				if (a8_clk_falling_valid == 1'b1)
					begin
						ticks 	<= {TICK_BITS{1'b0}};
					end
				else
					ticks	<= ticks + 7'b1;
			end
	



	assign a8_addr_strobe 	= (ticks == TICK_ADDRESS_VALID);
	assign a8_write_strobe	= (ticks == TICK_WRITE_VALID);
	assign a8_read_strobe	= (ticks == TICK_READ_VALID);

endmodule