data/full_repos/permissive/492140037/CPU/仿真文件/Ifetc32_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/Ifetc32_sim.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #500 clock = ~clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6/Ifetc32_sim.v:18: Cannot find file containing module: \'Ifetc32\'\nIfetc32 ifetc(Instruction,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/Ifetc32\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/Ifetc32.v\n             data/full_repos/permissive/492140037/CPU/\xe4\xbb\xbf\xe7\x9c\x9f\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/Ifetc32.sv\n             Ifetc32\n             Ifetc32.v\n             Ifetc32.sv\n             obj_dir/Ifetc32\n             obj_dir/Ifetc32.v\n             obj_dir/Ifetc32.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ifetc32_sim();

reg[31:0] Addr_result;
reg[31:0] Read_data_1;
reg Branch;
reg nBranch;            
reg Jmp;                
reg Jal;                
reg Jr;
reg Zero;
reg clock,reset;  
reg[31:0] Instruction;		
wire[31:0] branch_base_addr;  
wire[31:0] link_addr; 

Ifetc32 ifetc(Instruction,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr);

initial begin
    clock = 1'b0;
    reset = 1'b0;
    Branch = 1'b0;
    nBranch = 1'b0;
    Jmp = 1'b0;
    Jal = 1'b0;
    Jr = 1'b0;
    Zero = 1'b0;
    Addr_result = 32'b0;
    Read_data_1 = 32'b0;
    Instruction = 872939524;

    #500 clock = ~clock;
    Instruction = 873005060;

end


endmodule
module Ifetc32_sim();


reg[31:0] Addr_result;
reg[31:0] Read_data_1;
reg Branch;
reg nBranch;            
reg Jmp;                
reg Jal;                
reg Jr;
reg Zero;
reg clock,reset;  
reg[31:0] Instruction;		
wire[31:0] branch_base_addr;  
wire[31:0] link_addr; 

Ifetc32 ifetc(Instruction,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr);

initial begin
    clock = 1'b0;
    reset = 1'b0;
    Branch = 1'b0;
    nBranch = 1'b0;
    Jmp = 1'b0;
    Jal = 1'b0;
    Jr = 1'b0;
    Zero = 1'b0;
    Addr_result = 32'b0;
    Read_data_1 = 32'b0;
    Instruction = 872939524;

    #500 clock = ~clock;
    Instruction = 873005060;

end


endmodule