data/full_repos/permissive/52714256/SINGEN/src/SPI/spi.v
1: b"%Error: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi.v:59: Cannot find file containing module: 'SPI_MASTER'\n    SPI_MASTER #(.m(m)) spi_master\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER.v\n             data/full_repos/permissive/52714256/SINGEN/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER.sv\n             SPI_MASTER\n             SPI_MASTER.v\n             SPI_MASTER.sv\n             obj_dir/SPI_MASTER\n             obj_dir/SPI_MASTER.v\n             obj_dir/SPI_MASTER.sv\n%Error: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi.v:74: Cannot find file containing module: 'SPI_SLAVE'\n    SPI_SLAVE #(.m(m)) spi_slave \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/52714256/SINGEN/src/SPI/spi.v:86: Cannot find file containing module: 'CLK_DIV'\n    CLK_DIV clk_div\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module SPI#
    (
    parameter integer m = 15,
    parameter integer Tbit = 100
    )
    (

    output reg [127:0] str0 = "                ",
    output reg [127:0] str1 = "                ",
    output reg [127:0] str2 = "                ",
    output reg [127:0] str3 = "                ",
    input wire GCLK,
    input wire RST,
    input wire [7:0] SW,

    input wire st,

    input wire MASTER_MISO,
    output wire MASTER_MOSI,
    output wire MASTER_SS,
    output wire MASTER_SCLK,

    input wire SLAVE_MOSI,
    output wire SLAVE_MISO,
    input wire SLAVE_SS,
    input wire SLAVE_SCLK
    );
    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 15'b010110000110110;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 15'b110101100110110;
    
    wire clk_Tbit;
    
    SPI_MASTER #(.m(m)) spi_master
        (
        .clk(GCLK),
        .ce(clk_Tbit),
        .st(st),
        .SCLK(MASTER_SCLK),
        .MISO(MASTER_MISO),
        .MOSI(MASTER_MOSI),
        .LOAD(MASTER_SS),
        .TX_MD(MASTER_TX),
        .RX_SD(MASTER_RX),
        .RST(RST),
        .LEFT(1'b1)
        );

    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .GCLK(GCLK),
        .RST(RST),
        .SCLK(SLAVE_SCLK),
        .MISO(SLAVE_MISO),
        .MOSI(SLAVE_MOSI),
        .SS(SLAVE_SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );
   
    CLK_DIV clk_div
        (
        .GCLK(GCLK),
        .out(clk_Tbit),
        .T(Tbit)
        );
        

    wire [127:0] str_m_tx;
    wire [127:0] str_s_tx;
    wire [127:0] str_m_rx;
    wire [127:0] str_s_rx;

    always @(posedge clk_Tbit) begin
        if (SW[6] == 1'b1) begin
            str0 <= "SPI Interface   ";
            str1 <= SW[7] ? " M-R TX/SLAVE RX" : " SLAVE TX/M-R RX";
            str2 <= SW[7] ? str_m_tx : str_s_tx;
            str3 <= SW[7] ? str_s_rx : str_m_rx;
        end
    end
    
endmodule
module SPI#
    (
    parameter integer m = 15,
    parameter integer Tbit = 100
    )
    (

    output reg [127:0] str0 = "                ",
    output reg [127:0] str1 = "                ",
    output reg [127:0] str2 = "                ",
    output reg [127:0] str3 = "                ",
    input wire GCLK,
    input wire RST,
    input wire [7:0] SW,

    input wire st,

    input wire MASTER_MISO,
    output wire MASTER_MOSI,
    output wire MASTER_SS,
    output wire MASTER_SCLK,

    input wire SLAVE_MOSI,
    output wire SLAVE_MISO,
    input wire SLAVE_SS,
    input wire SLAVE_SCLK
    );

    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 15'b010110000110110;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 15'b110101100110110;
    
    wire clk_Tbit;
    
    SPI_MASTER #(.m(m)) spi_master
        (
        .clk(GCLK),
        .ce(clk_Tbit),
        .st(st),
        .SCLK(MASTER_SCLK),
        .MISO(MASTER_MISO),
        .MOSI(MASTER_MOSI),
        .LOAD(MASTER_SS),
        .TX_MD(MASTER_TX),
        .RX_SD(MASTER_RX),
        .RST(RST),
        .LEFT(1'b1)
        );

    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .GCLK(GCLK),
        .RST(RST),
        .SCLK(SLAVE_SCLK),
        .MISO(SLAVE_MISO),
        .MOSI(SLAVE_MOSI),
        .SS(SLAVE_SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );
   
    CLK_DIV clk_div
        (
        .GCLK(GCLK),
        .out(clk_Tbit),
        .T(Tbit)
        );
        

    wire [127:0] str_m_tx;
    wire [127:0] str_s_tx;
    wire [127:0] str_m_rx;
    wire [127:0] str_s_rx;

    always @(posedge clk_Tbit) begin
        if (SW[6] == 1'b1) begin
            str0 <= "SPI Interface   ";
            str1 <= SW[7] ? " M-R TX/SLAVE RX" : " SLAVE TX/M-R RX";
            str2 <= SW[7] ? str_m_tx : str_s_tx;
            str3 <= SW[7] ? str_s_rx : str_m_rx;
        end
    end
    
endmodule