data/full_repos/permissive/469273213/multiplier/rtl/claAdder4.v
data/verilator_xmls/45b959cf-a579-4762-aa28-e7be94ce4a9c.xml
module claAdder4 (
    input wire  [3:0]   in_a,
    input wire  [3:0]   in_b,
    input wire  c_in,
    output wire [3:0]   s,
    output wire c_out
);

    wire [3:0] p, g, c;

    assign c[0] = c_in;
    assign p[3:0] = in_a[3:0] ^ in_b[3:0];
    assign g[3:0] = in_a[3:0] & in_b[3:0];

    assign c[1] = g[0] | (p[0] & c_in);
    assign c[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & c_in);
    assign c[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c_in);

    assign c_out = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & c_in);
    assign s[3:0] = p[3:0] ^ c[3:0];
    
endmodule
module claAdder4 (
    input wire  [3:0]   in_a,
    input wire  [3:0]   in_b,
    input wire  c_in,
    output wire [3:0]   s,
    output wire c_out
);


    wire [3:0] p, g, c;

    assign c[0] = c_in;
    assign p[3:0] = in_a[3:0] ^ in_b[3:0];
    assign g[3:0] = in_a[3:0] & in_b[3:0];

    assign c[1] = g[0] | (p[0] & c_in);
    assign c[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & c_in);
    assign c[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c_in);

    assign c_out = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & c_in);
    assign s[3:0] = p[3:0] ^ c[3:0];
    
endmodule