data/full_repos/permissive/42434302/ivltests/pr534.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:23: Unsupported: Ignoring delay on this delayed statement.\n  always #(15.0/2) PCI_Clk <= ~PCI_Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:34: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 4500) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:39: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 6000) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(15.0);\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:42: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 7500) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #(15.0 *2);\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:45: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 10500) fail = 1;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:48: Unsupported or unknown PLI call: $timeformat\n    $timeformat(-9,2,"ns",20);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:53: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 15000) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:56: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 16500) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #(15.0);\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:59: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 18000) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #(15.0 *2);\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr534.v:62: Unsupported or unknown PLI call: $simtime\n    if($simtime !== 21000) fail = 1;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr534.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #(15.0 * delta);\n      ^\n%Error: Exiting due to 9 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg PCI_Clk;
  reg fail;

  initial PCI_Clk <= 0;
  always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;

  initial begin
    fail = 0;
    $display("\n\t\t==> CHECK THIS DISPLAY ==>\n");
    $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
    $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
    if($time !== 0) fail = 1;
    if (fail == 1)
      $display("$time=%0d (0)", $time);
    delay_pci(3);
    if($simtime !== 4500) fail = 1;
    if($time !== 45) fail = 1;
    if (fail == 1)
      $display("$time=%0d (45)", $time);
    #15;
    if($simtime !== 6000) fail = 1;
    if($time !== 60) fail = 1;
    #(`PCI_CLK_PERIOD);
    if($simtime !== 7500) fail = 1;
    if($time !== 75) fail = 1;
    #(`PCI_CLK_PERIOD *2);
    if($simtime !== 10500) fail = 1;
    if($time !== 105) fail = 1;

    $timeformat(-9,2,"ns",20);
    $display("after setting timeformat:");
    $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
    $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
    delay_pci(3);
    if($simtime !== 15000) fail = 1;
    if($time !== 150) fail = 1;
    #15;
    if($simtime !== 16500) fail = 1;
    if($time !== 165) fail = 1;
    #(`PCI_CLK_PERIOD);
    if($simtime !== 18000) fail = 1;
    if($time !== 180) fail = 1;
    #(`PCI_CLK_PERIOD *2);
    if($simtime !== 21000) fail = 1;
    if($time !== 210) fail = 1;

    $display("\t\t**********************************************");
    if(fail) $display("\t\t****** time representation test BAD    *******");
    else     $display("\t\t****** time representation test OK     *******");
    $display("\t\t**********************************************\n");
    $finish;
  end

  task delay_pci;
    input delta;
    integer delta;
    integer ii;
    begin
      #(`PCI_CLK_PERIOD * delta);
    end
  endtask

endmodule
module top;

  reg PCI_Clk;
  reg fail;

  initial PCI_Clk <= 0;
  always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;

  initial begin
    fail = 0;
    $display("\n\t\t==> CHECK THIS DISPLAY ==>\n");
    $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
    $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
    if($time !== 0) fail = 1;
    if (fail == 1)
      $display("$time=%0d (0)", $time);
    delay_pci(3);
    if($simtime !== 4500) fail = 1;
    if($time !== 45) fail = 1;
    if (fail == 1)
      $display("$time=%0d (45)", $time);
    #15;
    if($simtime !== 6000) fail = 1;
    if($time !== 60) fail = 1;
    #(`PCI_CLK_PERIOD);
    if($simtime !== 7500) fail = 1;
    if($time !== 75) fail = 1;
    #(`PCI_CLK_PERIOD *2);
    if($simtime !== 10500) fail = 1;
    if($time !== 105) fail = 1;

    $timeformat(-9,2,"ns",20);
    $display("after setting timeformat:");
    $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
    $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
    delay_pci(3);
    if($simtime !== 15000) fail = 1;
    if($time !== 150) fail = 1;
    #15;
    if($simtime !== 16500) fail = 1;
    if($time !== 165) fail = 1;
    #(`PCI_CLK_PERIOD);
    if($simtime !== 18000) fail = 1;
    if($time !== 180) fail = 1;
    #(`PCI_CLK_PERIOD *2);
    if($simtime !== 21000) fail = 1;
    if($time !== 210) fail = 1;

    $display("\t\t**********************************************");
    if(fail) $display("\t\t****** time representation test BAD    *******");
    else     $display("\t\t****** time representation test OK     *******");
    $display("\t\t**********************************************\n");
    $finish;
  end

  task delay_pci;
    input delta;
    integer delta;
    integer ii;
    begin
      #(`PCI_CLK_PERIOD * delta);
    end
  endtask

endmodule