data/full_repos/permissive/441359809/src/yosys/tests/various/port_sign_extend.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/port_sign_extend.v:60: syntax error, unexpected ref, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule ref(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);\n       ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/port_sign_extend.v:63: syntax error, unexpected assign\n assign o1 = 4'b0001;\n ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/port_sign_extend.v:70: syntax error, unexpected assign\n assign yay1 = 3'b111;\n ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/port_sign_extend.v:74: syntax error, unexpected assign\n assign yay2 = 3'b110;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
	output wire [3:0] o1, o2, o3, o4, o5;


	PassThrough pt1(1'b1, o1);


	wire tmp2;
	assign tmp2 = 1'sb1;
	PassThrough pt2(tmp2, o2);


	PassThrough pt3(1'sb1, o3);


	wire signed tmp4;
	assign tmp4 = 1'sb1;
	PassThrough pt4(tmp4, o4);


	wire signed [1:0] tmp5a = 2'b11;
	wire signed [1:0] tmp5b = 2'b01;
	PassThrough pt5(tmp5a ^ tmp5b, o5);

	output wire [2:0] yay1, nay1;
	GeneratorSigned1   os1(yay1);
	GeneratorUnsigned1 ou1(nay1);

	output wire [2:0] yay2, nay2;
	GeneratorSigned2   os2(yay2);
	GeneratorUnsigned2 ou2(nay2);
endmodule
module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);

	output wire [3:0] o1, o2, o3, o4, o5;


	PassThrough pt1(1'b1, o1);


	wire tmp2;
	assign tmp2 = 1'sb1;
	PassThrough pt2(tmp2, o2);


	PassThrough pt3(1'sb1, o3);


	wire signed tmp4;
	assign tmp4 = 1'sb1;
	PassThrough pt4(tmp4, o4);


	wire signed [1:0] tmp5a = 2'b11;
	wire signed [1:0] tmp5b = 2'b01;
	PassThrough pt5(tmp5a ^ tmp5b, o5);

	output wire [2:0] yay1, nay1;
	GeneratorSigned1   os1(yay1);
	GeneratorUnsigned1 ou1(nay1);

	output wire [2:0] yay2, nay2;
	GeneratorSigned2   os2(yay2);
	GeneratorUnsigned2 ou2(nay2);
endmodule