data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/tb_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/tb_testbench.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/tb_testbench.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire n1,n2,n3,n4;

mux_test tester(n1,n2,n3,n4);


my_mux dut     (n1,n2,n3,n4);

always @( n1, n2, n3, n4 )
begin
    #1;
    $display("%b %b %b %b",n1,n2,n3,n4);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire n1,n2,n3,n4;

mux_test tester(n1,n2,n3,n4);


my_mux dut     (n1,n2,n3,n4);

always @( n1, n2, n3, n4 )
begin
    #1;
    $display("%b %b %b %b",n1,n2,n3,n4);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule