data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:18: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh.sv\n             axi/assign.svh\n             axi/assign.svh.v\n             axi/assign.svh.sv\n             obj_dir/axi/assign.svh\n             obj_dir/axi/assign.svh.v\n             obj_dir/axi/assign.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:41: Unsupported: classes\n  class ax_transfer;\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:43: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    rand axi_pkg::len_t   len   = \'0;\n         ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:52: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time CyclTime = 10ns;\n                             ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:53: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time ApplTime =  2ns;\n                              ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:54: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time TestTime =  8ns;\n                              ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:56: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_rand_master #(\n                  ^~\n                                                                                                  : ... Perhaps \'axi_test\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:70: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_rand_slave #(\n                  ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:100: Define or directive not defined: \'`AXI_ASSIGN\'\n  `AXI_ASSIGN(slave_dv, master_dv)\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:100: syntax error, unexpected \'(\'\n  `AXI_ASSIGN(slave_dv, master_dv)\n              ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:114: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic axi_rand_master_t axi_rand_master = new(master_dv);\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:116: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:117: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::WTHRU_NOALLOCATE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:118: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::WBACK_RWALLOCATE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:120: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:123: syntax error, unexpected \'@\'\n    repeat (10000) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:128: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic axi_rand_slave_t  axi_rand_slave  = new(slave_dv);\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:130: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:140: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:143: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:144: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:184: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:185: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:202: Unsupported: wait statements\n      wait (ax_queue.size());\n      ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:212: syntax error, unexpected ::, expecting \';\'\n        test_addr = axi_pkg::beat_addr(ax_beat.addr, ax_beat.size, ax_beat.len, ax_beat.burst, i);\n                           ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:229: syntax error, unexpected ::, expecting \')\'\n      int unsigned burst_length, axi_pkg::burst_t mode);\n                                        ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:240: syntax error, unexpected \'(\', expecting \'#\' or final\n    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});\n            ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:246: syntax error, unexpected ::\n    if (mode == axi_pkg::BURST_WRAP) begin\n                       ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:254: syntax error, unexpected ::\n      if (mode != axi_pkg::BURST_FIXED) begin\n                         ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:272: syntax error, unexpected ::, expecting \',\' or \':\'\n      axi_pkg::BURST_FIXED: $display("TYPE: BURST_FIXED");\n             ^~\n%Error: Cannot continue\n'
module tb_axi_addr_test #(

  int unsigned NumTests = 32'd10000,

  bit          PrintDbg = 1'b0
);

  localparam int unsigned AxiIdWidth   = 32'd1;
  localparam int unsigned AxiAddrWidth = 32'd16;
  localparam int unsigned AxiDataWidth = 32'd1024;
  localparam int unsigned AxiUserWidth = 32'd1;


  localparam int unsigned PrintTnx = 1000;
  localparam int unsigned NoReads  = 0;
  localparam int unsigned NoWrites = NumTests;


  typedef logic [AxiAddrWidth:0] addr_t;


  class ax_transfer;
    rand addr_t           addr  = '0;
    rand axi_pkg::len_t   len   = '0;
    rand axi_pkg::size_t  size  = '0;
    rand axi_pkg::burst_t burst = '0;
  endclass


  localparam int unsigned NoPendingDut = 16;


  localparam time CyclTime = 10ns;
  localparam time ApplTime =  2ns;
  localparam time TestTime =  8ns;

  typedef axi_test::axi_rand_master #(

    .AW ( AxiAddrWidth ),
    .DW ( AxiDataWidth ),
    .IW ( AxiIdWidth   ),
    .UW ( AxiUserWidth ),

    .TA ( ApplTime ),
    .TT ( TestTime ),

    .AXI_BURST_FIXED ( 1'b1 ),
    .AXI_BURST_INCR  ( 1'b1 ),
    .AXI_BURST_WRAP  ( 1'b1 )
  ) axi_rand_master_t;
  typedef axi_test::axi_rand_slave #(

    .AW ( AxiAddrWidth ),
    .DW ( AxiDataWidth ),
    .IW ( AxiIdWidth   ),
    .UW ( AxiUserWidth ),

    .TA ( ApplTime ),
    .TT ( TestTime )
  ) axi_rand_slave_t;



  logic clk;
  logic rst_n;
  logic end_of_sim;

  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth ),
    .AXI_DATA_WIDTH ( AxiDataWidth ),
    .AXI_ID_WIDTH   ( AxiIdWidth   ),
    .AXI_USER_WIDTH ( AxiUserWidth )
  ) master_dv (clk);
  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth ),
    .AXI_DATA_WIDTH ( AxiDataWidth ),
    .AXI_ID_WIDTH   ( AxiIdWidth   ),
    .AXI_USER_WIDTH ( AxiUserWidth )
  ) slave_dv (clk);

  `AXI_ASSIGN(slave_dv, master_dv)




  clk_rst_gen #(
    .ClkPeriod   ( CyclTime ),
    .RstClkCycles( 5        )
  ) i_clk_gen (
    .clk_o (clk),
    .rst_no(rst_n)
  );

  initial begin : proc_axi_master
    automatic axi_rand_master_t axi_rand_master = new(master_dv);
    end_of_sim <= 1'b0;
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE);
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE);
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE);
    axi_rand_master.reset();
    @(posedge rst_n);
    axi_rand_master.run(0, NumTests);
    end_of_sim <= 1'b1;
    repeat (10000) @(posedge clk);
    $stop();
  end

  initial begin : proc_axi_slave
    automatic axi_rand_slave_t  axi_rand_slave  = new(slave_dv);
    axi_rand_slave.reset();
    @(posedge rst_n);
    axi_rand_slave.run();
  end

  initial begin : proc_sim_progress
    automatic int unsigned aw         = 0;
    automatic int unsigned ar         = 0;
    automatic bit          aw_printed = 1'b0;
    automatic bit          ar_printed = 1'b0;

    @(posedge rst_n);

    forever begin
      @(posedge clk);
      #TestTime;
      if (master_dv.aw_valid && master_dv.aw_ready) begin
        aw++;
      end
      if (master_dv.ar_valid && master_dv.ar_ready) begin
        ar++;
      end

      if ((aw % PrintTnx == 0) && ! aw_printed) begin
        $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites);
        aw_printed = 1'b1;
      end
      if ((ar % PrintTnx == 0) && !ar_printed) begin
        $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads);
        ar_printed = 1'b1;
      end

      if (aw % PrintTnx == 1) begin
        aw_printed = 1'b0;
      end
      if (ar % PrintTnx == 1) begin
        ar_printed = 1'b0;
      end

      if (end_of_sim) begin
        $info("All transactions completed.");
        break;
      end
    end
  end


  ax_transfer ax_queue[$];
  addr_t      gold_addr[$];

  initial begin : generate_tests
    automatic logic       rand_success;
    automatic ax_transfer ax_beat;

    forever begin
      @(posedge clk);
      #TestTime;
      if (master_dv.aw_valid && master_dv.aw_ready) begin
        ax_beat = new;
        ax_beat.addr  = master_dv.aw_addr;
        ax_beat.len   = master_dv.aw_len;
        ax_beat.size  = master_dv.aw_size;
        ax_beat.burst = master_dv.aw_burst;

        ax_queue.push_back(ax_beat);
      end
    end
  end

  initial begin : proc_test
    automatic ax_transfer ax_beat;
    automatic addr_t      test_addr, exp_addr;
    for (int unsigned i = 0; i < NumTests; i++) begin
      wait (ax_queue.size());

      ax_beat = ax_queue.pop_front();
      if (PrintDbg) begin
        print_ax(ax_beat);
      end

      data_transfer(ax_beat.addr, (2**ax_beat.size), (ax_beat.len+1), ax_beat.burst);

      for (int unsigned i = 0; i <= ax_beat.len; i++) begin
        test_addr = axi_pkg::beat_addr(ax_beat.addr, ax_beat.size, ax_beat.len, ax_beat.burst, i);
        exp_addr  = gold_addr.pop_front();
        if (PrintDbg) begin
          print_addr(test_addr, i);
        end
        assert (test_addr == exp_addr) else
          begin
            print_ax(ax_beat);
            print_addr(test_addr, i);
            $error("Expected ADDR: %0h was ADDR: %0h", exp_addr, test_addr);
          end
      end
    end
  end


  function automatic void data_transfer(addr_t start_addr, int unsigned num_bytes,
      int unsigned burst_length, axi_pkg::burst_t mode);

    localparam int unsigned large_addr = $bits(addr_t);
    typedef logic [large_addr:0] laddr_t;

    laddr_t      addr;
    laddr_t      aligned_addr;
    bit          aligned;
    int unsigned dtsize;
    laddr_t      lower_wrap_boundary;
    laddr_t      upper_wrap_boundary;
    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});
    addr         = laddr_t'(start_addr);
    aligned_addr = laddr_t'((addr / num_bytes) * num_bytes);
    aligned      = (aligned_addr == addr);
    dtsize       = num_bytes * burst_length;

    if (mode == axi_pkg::BURST_WRAP) begin
      lower_wrap_boundary = laddr_t'((addr / dtsize) * dtsize);
      upper_wrap_boundary = lower_wrap_boundary + dtsize;
    end

    for (int unsigned n = 1; n <= burst_length; n++) begin
      gold_addr.push_back(addr_t'(addr));

      if (mode != axi_pkg::BURST_FIXED) begin
        if (aligned) begin
          addr += num_bytes;
        end else begin
          addr    = aligned_addr + num_bytes;
          aligned = 1'b1;
        end
        if (mode == axi_pkg::BURST_WRAP && (addr >= upper_wrap_boundary)) begin
          addr = lower_wrap_boundary;
        end
      end
    end
  endfunction : data_transfer

  function automatic void print_ax (ax_transfer ax);
    $display("####################################################################",);
    $display("AX transfer with:");
    case (ax.burst)
      axi_pkg::BURST_FIXED: $display("TYPE: BURST_FIXED");
      axi_pkg::BURST_INCR:  $display("TYPE: BURST_INCR");
      axi_pkg::BURST_WRAP:  $display("TYPE: BURST_WRAP");
      default : $error("TYPE: NOT_DEFINED");
    endcase
    $display("ADDR: %0h", ax.addr);
    $display("SIZE: %0h", ax.size);
    $display("LEN:  %0h", ax.len);
  endfunction : print_ax

  function automatic void print_addr(addr_t addr, int unsigned i_addr);
    $display("i_beat: %0h ADDR: %0h", i_addr, addr);
  endfunction : print_addr

endmodule
module tb_axi_addr_test #(

  int unsigned NumTests = 32'd10000,

  bit          PrintDbg = 1'b0
);


  localparam int unsigned AxiIdWidth   = 32'd1;
  localparam int unsigned AxiAddrWidth = 32'd16;
  localparam int unsigned AxiDataWidth = 32'd1024;
  localparam int unsigned AxiUserWidth = 32'd1;


  localparam int unsigned PrintTnx = 1000;
  localparam int unsigned NoReads  = 0;
  localparam int unsigned NoWrites = NumTests;


  typedef logic [AxiAddrWidth:0] addr_t;


  class ax_transfer;
    rand addr_t           addr  = '0;
    rand axi_pkg::len_t   len   = '0;
    rand axi_pkg::size_t  size  = '0;
    rand axi_pkg::burst_t burst = '0;
  endclass


  localparam int unsigned NoPendingDut = 16;


  localparam time CyclTime = 10ns;
  localparam time ApplTime =  2ns;
  localparam time TestTime =  8ns;

  typedef axi_test::axi_rand_master #(

    .AW ( AxiAddrWidth ),
    .DW ( AxiDataWidth ),
    .IW ( AxiIdWidth   ),
    .UW ( AxiUserWidth ),

    .TA ( ApplTime ),
    .TT ( TestTime ),

    .AXI_BURST_FIXED ( 1'b1 ),
    .AXI_BURST_INCR  ( 1'b1 ),
    .AXI_BURST_WRAP  ( 1'b1 )
  ) axi_rand_master_t;
  typedef axi_test::axi_rand_slave #(

    .AW ( AxiAddrWidth ),
    .DW ( AxiDataWidth ),
    .IW ( AxiIdWidth   ),
    .UW ( AxiUserWidth ),

    .TA ( ApplTime ),
    .TT ( TestTime )
  ) axi_rand_slave_t;



  logic clk;
  logic rst_n;
  logic end_of_sim;

  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth ),
    .AXI_DATA_WIDTH ( AxiDataWidth ),
    .AXI_ID_WIDTH   ( AxiIdWidth   ),
    .AXI_USER_WIDTH ( AxiUserWidth )
  ) master_dv (clk);
  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth ),
    .AXI_DATA_WIDTH ( AxiDataWidth ),
    .AXI_ID_WIDTH   ( AxiIdWidth   ),
    .AXI_USER_WIDTH ( AxiUserWidth )
  ) slave_dv (clk);

  `AXI_ASSIGN(slave_dv, master_dv)




  clk_rst_gen #(
    .ClkPeriod   ( CyclTime ),
    .RstClkCycles( 5        )
  ) i_clk_gen (
    .clk_o (clk),
    .rst_no(rst_n)
  );

  initial begin : proc_axi_master
    automatic axi_rand_master_t axi_rand_master = new(master_dv);
    end_of_sim <= 1'b0;
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE);
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE);
    axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE);
    axi_rand_master.reset();
    @(posedge rst_n);
    axi_rand_master.run(0, NumTests);
    end_of_sim <= 1'b1;
    repeat (10000) @(posedge clk);
    $stop();
  end

  initial begin : proc_axi_slave
    automatic axi_rand_slave_t  axi_rand_slave  = new(slave_dv);
    axi_rand_slave.reset();
    @(posedge rst_n);
    axi_rand_slave.run();
  end

  initial begin : proc_sim_progress
    automatic int unsigned aw         = 0;
    automatic int unsigned ar         = 0;
    automatic bit          aw_printed = 1'b0;
    automatic bit          ar_printed = 1'b0;

    @(posedge rst_n);

    forever begin
      @(posedge clk);
      #TestTime;
      if (master_dv.aw_valid && master_dv.aw_ready) begin
        aw++;
      end
      if (master_dv.ar_valid && master_dv.ar_ready) begin
        ar++;
      end

      if ((aw % PrintTnx == 0) && ! aw_printed) begin
        $display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites);
        aw_printed = 1'b1;
      end
      if ((ar % PrintTnx == 0) && !ar_printed) begin
        $display("%t> Transmit AR %d of %d.", $time(), ar, NoReads);
        ar_printed = 1'b1;
      end

      if (aw % PrintTnx == 1) begin
        aw_printed = 1'b0;
      end
      if (ar % PrintTnx == 1) begin
        ar_printed = 1'b0;
      end

      if (end_of_sim) begin
        $info("All transactions completed.");
        break;
      end
    end
  end


  ax_transfer ax_queue[$];
  addr_t      gold_addr[$];

  initial begin : generate_tests
    automatic logic       rand_success;
    automatic ax_transfer ax_beat;

    forever begin
      @(posedge clk);
      #TestTime;
      if (master_dv.aw_valid && master_dv.aw_ready) begin
        ax_beat = new;
        ax_beat.addr  = master_dv.aw_addr;
        ax_beat.len   = master_dv.aw_len;
        ax_beat.size  = master_dv.aw_size;
        ax_beat.burst = master_dv.aw_burst;

        ax_queue.push_back(ax_beat);
      end
    end
  end

  initial begin : proc_test
    automatic ax_transfer ax_beat;
    automatic addr_t      test_addr, exp_addr;
    for (int unsigned i = 0; i < NumTests; i++) begin
      wait (ax_queue.size());

      ax_beat = ax_queue.pop_front();
      if (PrintDbg) begin
        print_ax(ax_beat);
      end

      data_transfer(ax_beat.addr, (2**ax_beat.size), (ax_beat.len+1), ax_beat.burst);

      for (int unsigned i = 0; i <= ax_beat.len; i++) begin
        test_addr = axi_pkg::beat_addr(ax_beat.addr, ax_beat.size, ax_beat.len, ax_beat.burst, i);
        exp_addr  = gold_addr.pop_front();
        if (PrintDbg) begin
          print_addr(test_addr, i);
        end
        assert (test_addr == exp_addr) else
          begin
            print_ax(ax_beat);
            print_addr(test_addr, i);
            $error("Expected ADDR: %0h was ADDR: %0h", exp_addr, test_addr);
          end
      end
    end
  end


  function automatic void data_transfer(addr_t start_addr, int unsigned num_bytes,
      int unsigned burst_length, axi_pkg::burst_t mode);

    localparam int unsigned large_addr = $bits(addr_t);
    typedef logic [large_addr:0] laddr_t;

    laddr_t      addr;
    laddr_t      aligned_addr;
    bit          aligned;
    int unsigned dtsize;
    laddr_t      lower_wrap_boundary;
    laddr_t      upper_wrap_boundary;
    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});
    addr         = laddr_t'(start_addr);
    aligned_addr = laddr_t'((addr / num_bytes) * num_bytes);
    aligned      = (aligned_addr == addr);
    dtsize       = num_bytes * burst_length;

    if (mode == axi_pkg::BURST_WRAP) begin
      lower_wrap_boundary = laddr_t'((addr / dtsize) * dtsize);
      upper_wrap_boundary = lower_wrap_boundary + dtsize;
    end

    for (int unsigned n = 1; n <= burst_length; n++) begin
      gold_addr.push_back(addr_t'(addr));

      if (mode != axi_pkg::BURST_FIXED) begin
        if (aligned) begin
          addr += num_bytes;
        end else begin
          addr    = aligned_addr + num_bytes;
          aligned = 1'b1;
        end
        if (mode == axi_pkg::BURST_WRAP && (addr >= upper_wrap_boundary)) begin
          addr = lower_wrap_boundary;
        end
      end
    end
  endfunction : data_transfer

  function automatic void print_ax (ax_transfer ax);
    $display("####################################################################",);
    $display("AX transfer with:");
    case (ax.burst)
      axi_pkg::BURST_FIXED: $display("TYPE: BURST_FIXED");
      axi_pkg::BURST_INCR:  $display("TYPE: BURST_INCR");
      axi_pkg::BURST_WRAP:  $display("TYPE: BURST_WRAP");
      default : $error("TYPE: NOT_DEFINED");
    endcase
    $display("ADDR: %0h", ax.addr);
    $display("SIZE: %0h", ax.size);
    $display("LEN:  %0h", ax.len);
  endfunction : print_ax

  function automatic void print_addr(addr_t addr, int unsigned i_addr);
    $display("i_beat: %0h ADDR: %0h", i_addr, addr);
  endfunction : print_addr

endmodule