data/full_repos/permissive/48250786/test_subbytesall.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #20 subIn = 128\'h89d810e8855ace682d1843d8cb128fe4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #20 subIn = 128\'h4915598f55e5d7a0daca94fa1f0a63f7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #20 subIn = 128\'hfa636a2825b339c940668a3157244d17;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #20 subIn = 128\'h247240236966b3fa6ed2753288425b6c;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytesall.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #20 subIn = 128\'hc81677bc9b7ac93b25027992b0261996;\n  ^\n%Error: data/full_repos/permissive/48250786/test_subbytesall.v:36: Cannot find file containing module: \'subBytesAll\'\n subBytesAll uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytesAll\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytesAll.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytesAll.sv\n             subBytesAll\n             subBytesAll.v\n             subBytesAll.sv\n             obj_dir/subBytesAll\n             obj_dir/subBytesAll.v\n             obj_dir/subBytesAll.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_subbytesall;


	reg [127:0] subIn;
	reg clk;
	reg inverse;


	wire [127:0] subOut;


	subBytesAll uut (
		.subOut(subOut), 
		.subIn(subIn), 
		.clk(clk), 
		.inverse(inverse)
	);
	
	always begin
		clk = 0;
		#10;
		clk = 1;
		#10;
	end

	initial begin

		subIn = 128'h00102030405060708090a0b0c0d0e0f0;
		inverse = 0;


		#10
		
		#20 subIn = 128'h89d810e8855ace682d1843d8cb128fe4;
		#20 subIn = 128'h4915598f55e5d7a0daca94fa1f0a63f7;
		#20 subIn = 128'hfa636a2825b339c940668a3157244d17;
		#20 subIn = 128'h247240236966b3fa6ed2753288425b6c;
		#20 subIn = 128'hc81677bc9b7ac93b25027992b0261996;

		


	end
      
endmodule
module test_subbytesall;



	reg [127:0] subIn;
	reg clk;
	reg inverse;


	wire [127:0] subOut;


	subBytesAll uut (
		.subOut(subOut), 
		.subIn(subIn), 
		.clk(clk), 
		.inverse(inverse)
	);
	
	always begin
		clk = 0;
		#10;
		clk = 1;
		#10;
	end

	initial begin

		subIn = 128'h00102030405060708090a0b0c0d0e0f0;
		inverse = 0;


		#10
		
		#20 subIn = 128'h89d810e8855ace682d1843d8cb128fe4;
		#20 subIn = 128'h4915598f55e5d7a0daca94fa1f0a63f7;
		#20 subIn = 128'hfa636a2825b339c940668a3157244d17;
		#20 subIn = 128'h247240236966b3fa6ed2753288425b6c;
		#20 subIn = 128'hc81677bc9b7ac93b25027992b0261996;

		


	end
      
endmodule