data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x23.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x23.v:84: Cannot find file containing module: 'fpga_ram'\nfpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/fpga/rtl,data/full_repos/permissive/418752214/fpga_ram.sv\n             fpga_ram\n             fpga_ram.v\n             fpga_ram.sv\n             obj_dir/fpga_ram\n             obj_dir/fpga_ram.v\n             obj_dir/fpga_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module ct_f_spsram_256x23(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);


input   [7 :0]  A;           
input           CEN;         
input           CLK;         
input   [22:0]  D;           
input           GWEN;        
input   [22:0]  WEN;         
output  [22:0]  Q;           


reg     [7 :0]  addr_holding; 


wire    [7 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [22:0]  D;           
wire            GWEN;        
wire    [22:0]  Q;           
wire    [22:0]  WEN;         
wire    [7 :0]  addr;        
wire    [22:0]  ram0_din;    
wire    [22:0]  ram0_dout;   
wire            ram0_wen;    


parameter ADDR_WIDTH = 8;
parameter WRAP_SIZE  = 23;




assign ram0_wen = !CEN && !WEN[0] && !GWEN;




assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];



assign Q[WRAP_SIZE-1:0]             = ram0_dout[WRAP_SIZE-1:0];


fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));


endmodule
module ct_f_spsram_256x23(
  A,
  CEN,
  CLK,
  D,
  GWEN,
  Q,
  WEN
);



input   [7 :0]  A;           
input           CEN;         
input           CLK;         
input   [22:0]  D;           
input           GWEN;        
input   [22:0]  WEN;         
output  [22:0]  Q;           


reg     [7 :0]  addr_holding; 


wire    [7 :0]  A;           
wire            CEN;         
wire            CLK;         
wire    [22:0]  D;           
wire            GWEN;        
wire    [22:0]  Q;           
wire    [22:0]  WEN;         
wire    [7 :0]  addr;        
wire    [22:0]  ram0_din;    
wire    [22:0]  ram0_dout;   
wire            ram0_wen;    


parameter ADDR_WIDTH = 8;
parameter WRAP_SIZE  = 23;




assign ram0_wen = !CEN && !WEN[0] && !GWEN;




assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];


always@(posedge CLK)
begin
  if(!CEN) begin
    addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
  end
end

assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
                                  : A[ADDR_WIDTH-1:0];



assign Q[WRAP_SIZE-1:0]             = ram0_dout[WRAP_SIZE-1:0];


fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
  .PortAClk (CLK),
  .PortAAddr(addr),
  .PortADataIn (ram0_din),
  .PortAWriteEnable(ram0_wen),
  .PortADataOut(ram0_dout));


endmodule