data/full_repos/permissive/515818836/mem.v
1: b'%Error: data/full_repos/permissive/515818836/mem.v:43: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515818836,data/full_repos/permissive/515818836/defines.v\n             data/full_repos/permissive/515818836,data/full_repos/permissive/515818836/defines.v.v\n             data/full_repos/permissive/515818836,data/full_repos/permissive/515818836/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/515818836/mem.v:50: Define or directive not defined: \'`RegAddrBus\'\n           input wire [ `RegAddrBus ] wd_i,\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n           input wire [ `RegAddrBus ] wd_i,\n                                    ^\n%Error: data/full_repos/permissive/515818836/mem.v:52: syntax error, unexpected input, expecting IDENTIFIER or do or final\n           input wire [ `RegBus ] wdata_i,\n           ^~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:52: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] wdata_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:53: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] hi_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:54: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] lo_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n           input wire [ `AluOpBus ] aluop_i,\n           ^~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:57: Define or directive not defined: \'`AluOpBus\'\n           input wire [ `AluOpBus ] aluop_i,\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:58: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] mem_addr_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:59: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] reg2_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:62: Define or directive not defined: \'`RegBus\'\n           input wire [ `RegBus ] mem_data_i,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:67: syntax error, unexpected input, expecting IDENTIFIER or do or final\n           input wire wb_LLbit_we_i,\n           ^~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:68: syntax error, unexpected input, expecting IDENTIFIER or do or final\n           input wire wb_LLbit_value_i,\n           ^~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:71: syntax error, unexpected output, expecting IDENTIFIER or do or final\n           output reg [ `RegAddrBus ] wd_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:71: Define or directive not defined: \'`RegAddrBus\'\n           output reg [ `RegAddrBus ] wd_o,\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:73: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n           output reg [ `RegBus ] wdata_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:73: Define or directive not defined: \'`RegBus\'\n           output reg [ `RegBus ] wdata_o,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:74: Define or directive not defined: \'`RegBus\'\n           output reg [ `RegBus ] hi_o,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:75: Define or directive not defined: \'`RegBus\'\n           output reg [ `RegBus ] lo_o,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:78: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n           output reg LLbit_we_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:79: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n           output reg LLbit_value_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:82: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n           output reg [ `RegBus ] mem_addr_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:82: Define or directive not defined: \'`RegBus\'\n           output reg [ `RegBus ] mem_addr_o,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:84: syntax error, unexpected output, expecting IDENTIFIER or do or final\n           output reg [ 3: 0 ] mem_sel_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:85: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n           output reg [ `RegBus ] mem_data_o,\n           ^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:85: Define or directive not defined: \'`RegBus\'\n           output reg [ `RegBus ] mem_data_o,\n                        ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:92: Define or directive not defined: \'`RegBus\'\nwire [ `RegBus ] zero32;\n       ^~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:92: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [ `RegBus ] zero32;\n               ^\n%Error: data/full_repos/permissive/515818836/mem.v:96: syntax error, unexpected assign\nassign mem_we_o = mem_we ;\n^~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:97: Define or directive not defined: \'`ZeroWord\'\nassign zero32 = `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:103: Define or directive not defined: \'`RstEnable\'\n        if ( rst == `RstEnable )\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:122: Define or directive not defined: \'`RstEnable\'\n        if ( rst == `RstEnable )\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:124: Define or directive not defined: \'`NOPRegAddr\'\n                wd_o <= `NOPRegAddr;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:125: Define or directive not defined: \'`WriteDisable\'\n                wreg_o <= `WriteDisable;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:126: Define or directive not defined: \'`ZeroWord\'\n                wdata_o <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:127: Define or directive not defined: \'`ZeroWord\'\n                hi_o <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:128: Define or directive not defined: \'`ZeroWord\'\n                lo_o <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:129: Define or directive not defined: \'`WriteDisable\'\n                whilo_o <= `WriteDisable;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:130: Define or directive not defined: \'`ZeroWord\'\n                mem_addr_o <= `ZeroWord;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:131: Define or directive not defined: \'`WriteDisable\'\n                mem_we <= `WriteDisable;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:133: Define or directive not defined: \'`ZeroWord\'\n                mem_data_o <= `ZeroWord;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:134: Define or directive not defined: \'`ChipDisable\'\n                mem_ce_o <= `ChipDisable;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:146: Define or directive not defined: \'`WriteDisable\'\n                mem_we <= `WriteDisable;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:147: Define or directive not defined: \'`ZeroWord\'\n                mem_addr_o <= `ZeroWord;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:149: Define or directive not defined: \'`ChipDisable\'\n                mem_ce_o <= `ChipDisable;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:156: Define or directive not defined: \'`EXE_LB_OP\'\n                    `EXE_LB_OP:\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:159: Define or directive not defined: \'`WriteDisable\'\n                            mem_we <= `WriteDisable;\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:160: Define or directive not defined: \'`ChipEnable\'\n                            mem_ce_o <= `ChipEnable;\n                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515818836/mem.v:194: Define or directive not defined: \'`ZeroWord\'\n                                        wdata_o <= `ZeroWord;\n                                                   ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(

           input wire rst,


           input wire [ `RegAddrBus ] wd_i,
           input wire wreg_i,
           input wire [ `RegBus ] wdata_i,
           input wire [ `RegBus ] hi_i,
           input wire [ `RegBus ] lo_i,
           input wire whilo_i,

           input wire [ `AluOpBus ] aluop_i,
           input wire [ `RegBus ] mem_addr_i,
           input wire [ `RegBus ] reg2_i,


           input wire [ `RegBus ] mem_data_i,


           input wire LLbit_i,

           input wire wb_LLbit_we_i,
           input wire wb_LLbit_value_i,


           output reg [ `RegAddrBus ] wd_o,
           output reg wreg_o,
           output reg [ `RegBus ] wdata_o,
           output reg [ `RegBus ] hi_o,
           output reg [ `RegBus ] lo_o,
           output reg whilo_o,

           output reg LLbit_we_o,
           output reg LLbit_value_o,


           output reg [ `RegBus ] mem_addr_o,
           output wire mem_we_o,
           output reg [ 3: 0 ] mem_sel_o,
           output reg [ `RegBus ] mem_data_o,
           output reg mem_ce_o

       );


reg LLbit;
wire [ `RegBus ] zero32;
reg mem_we;


assign mem_we_o = mem_we ;
assign zero32 = `ZeroWord;



always @ ( * )
    begin
        if ( rst == `RstEnable )
            begin
                LLbit <= 1'b0;
            end
        else
            begin
                if ( wb_LLbit_we_i == 1'b1 )
                    begin
                        LLbit <= wb_LLbit_value_i;
                    end
                else
                    begin
                        LLbit <= LLbit_i;
                    end
            end
    end

always @ ( * )
    begin
        if ( rst == `RstEnable )
            begin
                wd_o <= `NOPRegAddr;
                wreg_o <= `WriteDisable;
                wdata_o <= `ZeroWord;
                hi_o <= `ZeroWord;
                lo_o <= `ZeroWord;
                whilo_o <= `WriteDisable;
                mem_addr_o <= `ZeroWord;
                mem_we <= `WriteDisable;
                mem_sel_o <= 4'b0000;
                mem_data_o <= `ZeroWord;
                mem_ce_o <= `ChipDisable;
                LLbit_we_o <= 1'b0;
                LLbit_value_o <= 1'b0;
            end
        else
            begin
                wd_o <= wd_i;
                wreg_o <= wreg_i;
                wdata_o <= wdata_i;
                hi_o <= hi_i;
                lo_o <= lo_i;
                whilo_o <= whilo_i;
                mem_we <= `WriteDisable;
                mem_addr_o <= `ZeroWord;
                mem_sel_o <= 4'b1111;
                mem_ce_o <= `ChipDisable;
                LLbit_we_o <= 1'b0;
                LLbit_value_o <= 1'b0;

                case ( aluop_i )


                    `EXE_LB_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;






                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 31 ] } }, mem_data_i[ 31: 24 ] };
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 23 ] } }, mem_data_i[ 23: 16 ] };
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 15 ] } }, mem_data_i[ 15: 8 ] };
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 7 ] } }, mem_data_i[ 7: 0 ] };
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LBU_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 31: 24 ] };
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 23: 16 ] };
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 15: 8 ] };
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 7: 0 ] };
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LH_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 16{ mem_data_i[ 31 ] } }, mem_data_i[ 31: 16 ] };
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 16{ mem_data_i[ 15 ] } }, mem_data_i[ 15: 0 ] };
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LHU_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 16{ 1'b0 } }, mem_data_i[ 31: 16 ] };
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 16{ 1'b0 } }, mem_data_i[ 15: 0 ] };
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LW_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            wdata_o <= mem_data_i;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_LWL_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteDisable;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;





                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= mem_data_i[ 31: 0 ];
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { mem_data_i[ 23: 0 ], reg2_i[ 7: 0 ] };
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { mem_data_i[ 15: 0 ], reg2_i[ 15: 0 ] };
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { mem_data_i[ 7: 0 ], reg2_i[ 23: 0 ] };
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LWR_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteDisable;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 8 ], mem_data_i[ 31: 24 ] };
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 16 ], mem_data_i[ 31: 16 ] };
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 24 ], mem_data_i[ 31: 8 ] };
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= mem_data_i;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LL_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            wdata_o <= mem_data_i;
                            LLbit_we_o <= 1'b1;
                            LLbit_value_o <= 1'b1;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_SB_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= { reg2_i[ 7: 0 ], reg2_i[ 7: 0 ], reg2_i[ 7: 0 ], reg2_i[ 7: 0 ] };
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SH_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= { reg2_i[ 15: 0 ], reg2_i[ 15: 0 ] };
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SW_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= reg2_i;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_SWL_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteEnable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1111;
                                        mem_data_o <= reg2_i;
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b0111;
                                        mem_data_o <= { zero32[ 7: 0 ], reg2_i[ 31: 8 ] };
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0011;
                                        mem_data_o <= { zero32[ 15: 0 ], reg2_i[ 31: 16 ] };
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b0001;
                                        mem_data_o <= { zero32[ 23: 0 ], reg2_i[ 31: 24 ] };
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SWR_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteEnable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1000;
                                        mem_data_o <= { reg2_i[ 7: 0 ], zero32[ 23: 0 ] };
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b1100;
                                        mem_data_o <= { reg2_i[ 15: 0 ], zero32[ 15: 0 ] };
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b1110;
                                        mem_data_o <= { reg2_i[ 23: 0 ], zero32[ 7: 0 ] };
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b1111;
                                        mem_data_o <= reg2_i[ 31: 0 ];
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SC_OP:
                        begin
                            if ( LLbit == 1'b1 )
                                begin
                                    LLbit_we_o <= 1'b1;
                                    LLbit_value_o <= 1'b0;
                                    mem_addr_o <= mem_addr_i;
                                    mem_we <= `WriteEnable;
                                    mem_data_o <= reg2_i;
                                    wdata_o <= 32'b1;
                                    mem_sel_o <= 4'b1111;
                                    mem_ce_o <= `ChipEnable;
                                end
                            else
                                begin
                                    wdata_o <= 32'b0;
                                end
                        end

                    default:
                        begin

                        end

                endcase
            end
    end


endmodule
module mem(

           input wire rst,


           input wire [ `RegAddrBus ] wd_i,
           input wire wreg_i,
           input wire [ `RegBus ] wdata_i,
           input wire [ `RegBus ] hi_i,
           input wire [ `RegBus ] lo_i,
           input wire whilo_i,

           input wire [ `AluOpBus ] aluop_i,
           input wire [ `RegBus ] mem_addr_i,
           input wire [ `RegBus ] reg2_i,


           input wire [ `RegBus ] mem_data_i,


           input wire LLbit_i,

           input wire wb_LLbit_we_i,
           input wire wb_LLbit_value_i,


           output reg [ `RegAddrBus ] wd_o,
           output reg wreg_o,
           output reg [ `RegBus ] wdata_o,
           output reg [ `RegBus ] hi_o,
           output reg [ `RegBus ] lo_o,
           output reg whilo_o,

           output reg LLbit_we_o,
           output reg LLbit_value_o,


           output reg [ `RegBus ] mem_addr_o,
           output wire mem_we_o,
           output reg [ 3: 0 ] mem_sel_o,
           output reg [ `RegBus ] mem_data_o,
           output reg mem_ce_o

       );



reg LLbit;
wire [ `RegBus ] zero32;
reg mem_we;


assign mem_we_o = mem_we ;
assign zero32 = `ZeroWord;



always @ ( * )
    begin
        if ( rst == `RstEnable )
            begin
                LLbit <= 1'b0;
            end
        else
            begin
                if ( wb_LLbit_we_i == 1'b1 )
                    begin
                        LLbit <= wb_LLbit_value_i;
                    end
                else
                    begin
                        LLbit <= LLbit_i;
                    end
            end
    end

always @ ( * )
    begin
        if ( rst == `RstEnable )
            begin
                wd_o <= `NOPRegAddr;
                wreg_o <= `WriteDisable;
                wdata_o <= `ZeroWord;
                hi_o <= `ZeroWord;
                lo_o <= `ZeroWord;
                whilo_o <= `WriteDisable;
                mem_addr_o <= `ZeroWord;
                mem_we <= `WriteDisable;
                mem_sel_o <= 4'b0000;
                mem_data_o <= `ZeroWord;
                mem_ce_o <= `ChipDisable;
                LLbit_we_o <= 1'b0;
                LLbit_value_o <= 1'b0;
            end
        else
            begin
                wd_o <= wd_i;
                wreg_o <= wreg_i;
                wdata_o <= wdata_i;
                hi_o <= hi_i;
                lo_o <= lo_i;
                whilo_o <= whilo_i;
                mem_we <= `WriteDisable;
                mem_addr_o <= `ZeroWord;
                mem_sel_o <= 4'b1111;
                mem_ce_o <= `ChipDisable;
                LLbit_we_o <= 1'b0;
                LLbit_value_o <= 1'b0;

                case ( aluop_i )


                    `EXE_LB_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;






                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 31 ] } }, mem_data_i[ 31: 24 ] };
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 23 ] } }, mem_data_i[ 23: 16 ] };
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 15 ] } }, mem_data_i[ 15: 8 ] };
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { { 24{ mem_data_i[ 7 ] } }, mem_data_i[ 7: 0 ] };
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LBU_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 31: 24 ] };
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 23: 16 ] };
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 15: 8 ] };
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { { 24{ 1'b0 } }, mem_data_i[ 7: 0 ] };
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LH_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 16{ mem_data_i[ 31 ] } }, mem_data_i[ 31: 16 ] };
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 16{ mem_data_i[ 15 ] } }, mem_data_i[ 15: 0 ] };
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LHU_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { { 16{ 1'b0 } }, mem_data_i[ 31: 16 ] };
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { { 16{ 1'b0 } }, mem_data_i[ 15: 0 ] };
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LW_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            wdata_o <= mem_data_i;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_LWL_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteDisable;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;





                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= mem_data_i[ 31: 0 ];
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { mem_data_i[ 23: 0 ], reg2_i[ 7: 0 ] };
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { mem_data_i[ 15: 0 ], reg2_i[ 15: 0 ] };
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= { mem_data_i[ 7: 0 ], reg2_i[ 23: 0 ] };
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LWR_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteDisable;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 8 ], mem_data_i[ 31: 24 ] };
                                    end

                                2'b01:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 16 ], mem_data_i[ 31: 16 ] };
                                    end

                                2'b10:
                                    begin
                                        wdata_o <= { reg2_i[ 31: 24 ], mem_data_i[ 31: 8 ] };
                                    end

                                2'b11:
                                    begin
                                        wdata_o <= mem_data_i;
                                    end

                                default:
                                    begin
                                        wdata_o <= `ZeroWord;
                                    end

                            endcase
                        end

                    `EXE_LL_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteDisable;
                            wdata_o <= mem_data_i;
                            LLbit_we_o <= 1'b1;
                            LLbit_value_o <= 1'b1;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_SB_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= { reg2_i[ 7: 0 ], reg2_i[ 7: 0 ], reg2_i[ 7: 0 ], reg2_i[ 7: 0 ] };
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1000;
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b0100;
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0010;
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b0001;
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SH_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= { reg2_i[ 15: 0 ], reg2_i[ 15: 0 ] };
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1100;
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0011;
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SW_OP:
                        begin
                            mem_addr_o <= mem_addr_i;
                            mem_we <= `WriteEnable;
                            mem_data_o <= reg2_i;
                            mem_sel_o <= 4'b1111;
                            mem_ce_o <= `ChipEnable;
                        end



                    `EXE_SWL_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteEnable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1111;
                                        mem_data_o <= reg2_i;
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b0111;
                                        mem_data_o <= { zero32[ 7: 0 ], reg2_i[ 31: 8 ] };
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b0011;
                                        mem_data_o <= { zero32[ 15: 0 ], reg2_i[ 31: 16 ] };
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b0001;
                                        mem_data_o <= { zero32[ 23: 0 ], reg2_i[ 31: 24 ] };
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SWR_OP:
                        begin
                            mem_addr_o <= { mem_addr_i[ 31: 2 ], 2'b00 };
                            mem_we <= `WriteEnable;
                            mem_ce_o <= `ChipEnable;

                            case ( mem_addr_i[ 1: 0 ] )
                                2'b00:
                                    begin
                                        mem_sel_o <= 4'b1000;
                                        mem_data_o <= { reg2_i[ 7: 0 ], zero32[ 23: 0 ] };
                                    end

                                2'b01:
                                    begin
                                        mem_sel_o <= 4'b1100;
                                        mem_data_o <= { reg2_i[ 15: 0 ], zero32[ 15: 0 ] };
                                    end

                                2'b10:
                                    begin
                                        mem_sel_o <= 4'b1110;
                                        mem_data_o <= { reg2_i[ 23: 0 ], zero32[ 7: 0 ] };
                                    end

                                2'b11:
                                    begin
                                        mem_sel_o <= 4'b1111;
                                        mem_data_o <= reg2_i[ 31: 0 ];
                                    end

                                default:
                                    begin
                                        mem_sel_o <= 4'b0000;
                                    end

                            endcase
                        end

                    `EXE_SC_OP:
                        begin
                            if ( LLbit == 1'b1 )
                                begin
                                    LLbit_we_o <= 1'b1;
                                    LLbit_value_o <= 1'b0;
                                    mem_addr_o <= mem_addr_i;
                                    mem_we <= `WriteEnable;
                                    mem_data_o <= reg2_i;
                                    wdata_o <= 32'b1;
                                    mem_sel_o <= 4'b1111;
                                    mem_ce_o <= `ChipEnable;
                                end
                            else
                                begin
                                    wdata_o <= 32'b0;
                                end
                        end

                    default:
                        begin

                        end

                endcase
            end
    end


endmodule