data/full_repos/permissive/461620575/Galaga on FPGA/ALU/alu.v
1: b'%Error: Cannot find file containing module: on\n        ... Looked in:\n             data/full_repos/permissive/461620575/Galaga/on\n             data/full_repos/permissive/461620575/Galaga/on.v\n             data/full_repos/permissive/461620575/Galaga/on.sv\n             on\n             on.v\n             on.sv\n             obj_dir/on\n             obj_dir/on.v\n             obj_dir/on.sv\n%Error: Cannot find file containing module: FPGA/ALU,data/full_repos/permissive/461620575\n%Error: Cannot find file containing module: data/full_repos/permissive/461620575/Galaga\n%Error: Cannot find file containing module: FPGA/ALU/alu.v\n%Error: Exiting due to 4 error(s)\n'
module alu(A, B, C, Opcode, Flags);

	input  [15:0] A, B;
	input  [7:0]  Opcode;
	
	output reg [15:0] C;
	output reg [4:0]  Flags;
	
	reg C_in;
	

	parameter carry_f    = 3'd4;
	parameter low_f      = 3'd3;
	parameter overflow_f = 3'd2;
	parameter zero_f     = 3'd1;
	parameter negative_f = 3'd0;




	parameter ADD  = 8'b00000101;
	parameter ADDI = 8'b0101xxxx;
	parameter ADDU = 8'b00000110;
	parameter ADDUI= 8'b0110xxxx;
	parameter ADDC = 8'b00000111;
	parameter ADDCI= 8'b0111xxxx;
	
	parameter SUB  = 8'b00001001;
	parameter SUBI = 8'b1001xxxx;
	parameter SUBC = 8'b00001010;
	parameter SUBCI= 8'b1010xxxx; 
	parameter CMP  = 8'b00001011;
	parameter CMPI = 8'b1011xxxx;
	parameter AND  = 8'b00000001;
	parameter ANDI = 8'b0001xxxx;
	parameter OR   = 8'b00000010;
	parameter ORI  = 8'b0010xxxx;
	parameter XOR  = 8'b00000011;
	parameter XORI = 8'b0011xxxx;
	parameter MOV  = 8'b00001101;
	parameter MOVI = 8'b1101xxxx;
	parameter LSH  = 8'b10000100;
	parameter LSHI = 8'b1000000x;
	parameter ASHU = 8'b10000110;
	parameter ASHUI= 8'b1000001x;
	parameter LUI  = 8'b1111xxxx;
	

	parameter LOAD = 8'b01000000;
	parameter STOR = 8'b01000100;
	parameter Bcond= 8'b1100xxxx;
	parameter Jcond= 8'b01001100;
	parameter JAL  = 8'b01001000;
	
	
	always@(*)
	begin		
		C_in = Flags[carry_f];
		C = 16'b0;
		Flags = 5'b0;
		
		casex (Opcode)
		ADD:
			begin
			{Flags[carry_f], C} = A + B; 
			


			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDI:
			begin

			{Flags[carry_f], C} = A + {{8{B[7]}} , B[7:0]};
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDU:
			begin
			C = A + B;
			end
			
		ADDUI:
			begin
			C = A + {8'b0, B[7:0]};
			end
			
		ADDC:
			begin
			{Flags[carry_f], C} = A + B + C_in;
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDCI:
			begin
			{Flags[carry_f], C} = A + {{8{B[7]}} , B[7:0]} + C_in;
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		SUB:
			begin
			{Flags[carry_f], C} = A - B;
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			


			if((A[15] & ~B[15] & ~C[15]) | (~A[15] & B[15] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;			
			end
			
		SUBI:
			begin
			{Flags[carry_f], C} = A - {{8{B[7]}} , B[7:0]};
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			
			if((A[15] & ~B[7] & ~C[15]) | (~A[15] & B[7] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
			
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;			
			end
			
		SUBC:
			begin
			{Flags[carry_f], C} = A - (B + C_in);
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			


			if((A[15] & ~B[15] & ~C[15]) | (~A[15] & B[15] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;	
			end
			
		SUBCI:
			begin
			{Flags[carry_f], C} = A - ({{8{B[7]}} , B[7:0]} + C_in);
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			
			if((A[15] & ~B[7] & ~C[15]) | (~A[15] & B[7] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
			
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;
			end
		
		CMP:
			begin
			
			if(A == B)
				Flags[zero_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;
				
			if(A < B)
				Flags[low_f] = 1'b1;
			
			end
			
		CMPI:
			begin 
			if(A == {{8{B[7]}} , B[7:0]})
				Flags[zero_f] = 1'b1;
				
			if($signed(A) < $signed({{8{B[7]}} , B[7:0]}))
				Flags[negative_f] = 1'b1;
				
			if(A < {8'b0 , B[7:0]})
				Flags[low_f] = 1'b1;
			end

		AND:
			begin
			C = A & B;
			
			if(C == 16'b0)
				Flags[zero_f] = 1'b1;
			end
			
		ANDI:
			begin
			C = A & {8'b0 , B[7:0]}; 
			
			if(C == 16'b0)
				Flags[zero_f] = 1'b1;
			end
			
		OR:
			begin
			C = A | B; 
			end
			
		ORI:
			begin
			C = A | {8'b0 , B[7:0]}; 
			end
			
		XOR:
			begin
			C = A ^ B;
			end
			
		XORI:
			begin
			C = A ^ {8'b0 , B[7:0]}; 
			end
			
		MOV:
			begin
			C = A; 
			end
			
		MOVI:
			begin
			C = {8'b0 , B[7:0]}; 
			end
			
		LSH:
			begin
			if(B[15] == 1'b0) 
				C = A << B;
			else
				C = A >> (-B);
			end			
			
		LSHI:
			begin
			if(Opcode[0] == 1'b0)
				C = A << {1'b0, B[3:0]};
			else
				begin
				C = A >> {1'b0, B[3:0]};
				end
			end
			
		ASHU:
			begin
			if(B[15] == 1'b0)
				C = $signed(A) <<< B; 
			else
				C = $signed(A) >>> (-B);
			end
			
		ASHUI:
			begin
			if(Opcode[0] == 1'b0)
				C = $signed(A) <<< {1'b0, B[3:0]};
			else
				C = $signed(A) >>> {1'b0, B[3:0]}; 
			end
			
		LUI:
			begin
			C = {B [7:0], 8'b0}; 
			end
			
		LOAD:
			begin
			C = B;
			end








































































































































































































































			







		
		default:
			begin
				C = A;
				Flags = Flags;
			end		
		endcase
		
	end
	
endmodule
module alu(A, B, C, Opcode, Flags);


	input  [15:0] A, B;
	input  [7:0]  Opcode;
	
	output reg [15:0] C;
	output reg [4:0]  Flags;
	
	reg C_in;
	

	parameter carry_f    = 3'd4;
	parameter low_f      = 3'd3;
	parameter overflow_f = 3'd2;
	parameter zero_f     = 3'd1;
	parameter negative_f = 3'd0;




	parameter ADD  = 8'b00000101;
	parameter ADDI = 8'b0101xxxx;
	parameter ADDU = 8'b00000110;
	parameter ADDUI= 8'b0110xxxx;
	parameter ADDC = 8'b00000111;
	parameter ADDCI= 8'b0111xxxx;
	
	parameter SUB  = 8'b00001001;
	parameter SUBI = 8'b1001xxxx;
	parameter SUBC = 8'b00001010;
	parameter SUBCI= 8'b1010xxxx; 
	parameter CMP  = 8'b00001011;
	parameter CMPI = 8'b1011xxxx;
	parameter AND  = 8'b00000001;
	parameter ANDI = 8'b0001xxxx;
	parameter OR   = 8'b00000010;
	parameter ORI  = 8'b0010xxxx;
	parameter XOR  = 8'b00000011;
	parameter XORI = 8'b0011xxxx;
	parameter MOV  = 8'b00001101;
	parameter MOVI = 8'b1101xxxx;
	parameter LSH  = 8'b10000100;
	parameter LSHI = 8'b1000000x;
	parameter ASHU = 8'b10000110;
	parameter ASHUI= 8'b1000001x;
	parameter LUI  = 8'b1111xxxx;
	

	parameter LOAD = 8'b01000000;
	parameter STOR = 8'b01000100;
	parameter Bcond= 8'b1100xxxx;
	parameter Jcond= 8'b01001100;
	parameter JAL  = 8'b01001000;
	
	
	always@(*)
	begin		
		C_in = Flags[carry_f];
		C = 16'b0;
		Flags = 5'b0;
		
		casex (Opcode)
		ADD:
			begin
			{Flags[carry_f], C} = A + B; 
			


			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDI:
			begin

			{Flags[carry_f], C} = A + {{8{B[7]}} , B[7:0]};
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDU:
			begin
			C = A + B;
			end
			
		ADDUI:
			begin
			C = A + {8'b0, B[7:0]};
			end
			
		ADDC:
			begin
			{Flags[carry_f], C} = A + B + C_in;
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		ADDCI:
			begin
			{Flags[carry_f], C} = A + {{8{B[7]}} , B[7:0]} + C_in;
			
			if((~A[15] & ~B[15] & C[15]) | (A[15] & B[15] & ~C[15])) 
				Flags[overflow_f] = 1'b1;
			end
			
		SUB:
			begin
			{Flags[carry_f], C} = A - B;
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			


			if((A[15] & ~B[15] & ~C[15]) | (~A[15] & B[15] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;			
			end
			
		SUBI:
			begin
			{Flags[carry_f], C} = A - {{8{B[7]}} , B[7:0]};
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			
			if((A[15] & ~B[7] & ~C[15]) | (~A[15] & B[7] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
			
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;			
			end
			
		SUBC:
			begin
			{Flags[carry_f], C} = A - (B + C_in);
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			


			if((A[15] & ~B[15] & ~C[15]) | (~A[15] & B[15] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;	
			end
			
		SUBCI:
			begin
			{Flags[carry_f], C} = A - ({{8{B[7]}} , B[7:0]} + C_in);
			
			if(A == B) 
				Flags[zero_f] = 1'b1; 
			
			if((A[15] & ~B[7] & ~C[15]) | (~A[15] & B[7] & C[15])) 
				Flags[overflow_f] = 1'b1;
			
			if(A < B)
				Flags[low_f] = 1'b1;
			
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;
			end
		
		CMP:
			begin
			
			if(A == B)
				Flags[zero_f] = 1'b1;
				
			if($signed(A) < $signed(B))
				Flags[negative_f] = 1'b1;
				
			if(A < B)
				Flags[low_f] = 1'b1;
			
			end
			
		CMPI:
			begin 
			if(A == {{8{B[7]}} , B[7:0]})
				Flags[zero_f] = 1'b1;
				
			if($signed(A) < $signed({{8{B[7]}} , B[7:0]}))
				Flags[negative_f] = 1'b1;
				
			if(A < {8'b0 , B[7:0]})
				Flags[low_f] = 1'b1;
			end

		AND:
			begin
			C = A & B;
			
			if(C == 16'b0)
				Flags[zero_f] = 1'b1;
			end
			
		ANDI:
			begin
			C = A & {8'b0 , B[7:0]}; 
			
			if(C == 16'b0)
				Flags[zero_f] = 1'b1;
			end
			
		OR:
			begin
			C = A | B; 
			end
			
		ORI:
			begin
			C = A | {8'b0 , B[7:0]}; 
			end
			
		XOR:
			begin
			C = A ^ B;
			end
			
		XORI:
			begin
			C = A ^ {8'b0 , B[7:0]}; 
			end
			
		MOV:
			begin
			C = A; 
			end
			
		MOVI:
			begin
			C = {8'b0 , B[7:0]}; 
			end
			
		LSH:
			begin
			if(B[15] == 1'b0) 
				C = A << B;
			else
				C = A >> (-B);
			end			
			
		LSHI:
			begin
			if(Opcode[0] == 1'b0)
				C = A << {1'b0, B[3:0]};
			else
				begin
				C = A >> {1'b0, B[3:0]};
				end
			end
			
		ASHU:
			begin
			if(B[15] == 1'b0)
				C = $signed(A) <<< B; 
			else
				C = $signed(A) >>> (-B);
			end
			
		ASHUI:
			begin
			if(Opcode[0] == 1'b0)
				C = $signed(A) <<< {1'b0, B[3:0]};
			else
				C = $signed(A) >>> {1'b0, B[3:0]}; 
			end
			
		LUI:
			begin
			C = {B [7:0], 8'b0}; 
			end
			
		LOAD:
			begin
			C = B;
			end








































































































































































































































			







		
		default:
			begin
				C = A;
				Flags = Flags;
			end		
		endcase
		
	end
	
endmodule