data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v
1: b"%Error: data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v:28: Cannot find file containing module: 'Reg1'\nReg1 A(.load(ld_a),.data(dataa),.clk(clk),.X(ax));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/471941633/adder_multiplier,data/full_repos/permissive/471941633/Reg1\n             data/full_repos/permissive/471941633/adder_multiplier,data/full_repos/permissive/471941633/Reg1.v\n             data/full_repos/permissive/471941633/adder_multiplier,data/full_repos/permissive/471941633/Reg1.sv\n             Reg1\n             Reg1.v\n             Reg1.sv\n             obj_dir/Reg1\n             obj_dir/Reg1.v\n             obj_dir/Reg1.sv\n%Error: data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v:29: Cannot find file containing module: 'Reg2'\nReg2 P(.load_P(ld_p),.clear_p(cr_p),.data_P(out),.clk(clk),.Y(py));\n^~~~\n%Error: data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v:30: Cannot find file containing module: 'Reg3'\nReg3 B(.loadb(ld_b),.clk(clk),.dcb(dc_b),.datb(datab),.datout(bd));\n^~~~\n%Error: data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v:31: Cannot find file containing module: 'comp'\ncomp CMP(.clk(clk),.in(bd),.zer(zero));\n^~~~\n%Error: data/full_repos/permissive/471941633/adder_multiplier/add_mlt.v:32: Cannot find file containing module: 'multiply'\nmultiply ADD(.clk(clk),.eqzero(zero),.a(ax),.p(py),.Z(out));\n^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module add_mlt(input clk,
               input[15:0]dataa,datab,
input ld_a,ld_b,ld_p,cr_p,dc_b,
output [15:0]ax,py,bd,
output zero,[15:0]out
    );

Reg1 A(.load(ld_a),.data(dataa),.clk(clk),.X(ax));
Reg2 P(.load_P(ld_p),.clear_p(cr_p),.data_P(out),.clk(clk),.Y(py));
Reg3 B(.loadb(ld_b),.clk(clk),.dcb(dc_b),.datb(datab),.datout(bd));
comp CMP(.clk(clk),.in(bd),.zer(zero));
multiply ADD(.clk(clk),.eqzero(zero),.a(ax),.p(py),.Z(out));

endmodule
module add_mlt(input clk,
               input[15:0]dataa,datab,
input ld_a,ld_b,ld_p,cr_p,dc_b,
output [15:0]ax,py,bd,
output zero,[15:0]out
    );


Reg1 A(.load(ld_a),.data(dataa),.clk(clk),.X(ax));
Reg2 P(.load_P(ld_p),.clear_p(cr_p),.data_P(out),.clk(clk),.Y(py));
Reg3 B(.loadb(ld_b),.clk(clk),.dcb(dc_b),.datb(datab),.datout(bd));
comp CMP(.clk(clk),.in(bd),.zer(zero));
multiply ADD(.clk(clk),.eqzero(zero),.a(ax),.p(py),.Z(out));

endmodule