data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/TestAndSet.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/TestAndSet.sv:46: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module TestAndSet 
#(
    parameter ADDR_MEM_WIDTH  = 12,
    parameter ID_WIDTH        = 20,
    parameter DATA_WIDTH      = 32,
    parameter BE_WIDTH        = DATA_WIDTH/8
)
(
    input  logic                                 clk,
    input  logic                                 rst_n,        


    input  logic                                 data_req_i,
    input  logic [ADDR_MEM_WIDTH-1:0]            data_add_i,
    input  logic                                 data_wen_i,
    input  logic [DATA_WIDTH-1:0]                data_wdata_i,
    input  logic [BE_WIDTH-1:0]                  data_be_i,
    input  logic [ID_WIDTH-1:0]                  data_ID_i,
`ifdef GNT_BASED_FC
    output logic                                 data_gnt_o,
`else
    output logic                                 data_stall_o,
`endif



    output logic                                 data_req_o,
    output logic                                 data_ts_set_o,
    output logic [ADDR_MEM_WIDTH-2:0]            data_add_o,
    output logic                                 data_wen_o,
    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
`ifdef GNT_BASED_FC        
    input  logic                                 data_gnt_i
`else
    input  logic                                 data_stall_i
`endif
);

    enum logic { LOAD_STORE, SET_STORE }       CS, NS;
    logic                                      Enable;


    logic                                      TestAndSet;


    logic [ADDR_MEM_WIDTH-2:0]                 data_add_S;
    logic [BE_WIDTH-1:0]                       data_be_S;


    logic [ID_WIDTH-1:0]                       data_ID_S;



    assign TestAndSet = (data_add_i[ADDR_MEM_WIDTH-1]) && (data_wen_i == 1'b1);
    assign data_ts_set_o = (CS == SET_STORE);

    always_ff @(posedge clk, negedge  rst_n)
    begin : TestAndSet_UpdataState
      if(rst_n == 1'b0)
        begin
          CS <= LOAD_STORE;
          data_add_S   <= '0;
          data_be_S    <= '0;
          data_ID_S    <= '0;
        end
      else
        begin
          CS <= NS;


          if(Enable == 1'b1)
            begin
              data_add_S   <= data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_S    <= data_be_i;
              data_ID_S    <= data_ID_i;
            end

        end
    end


    always_comb
    begin : TestAndSet_ComputeState

      case(CS)

          LOAD_STORE: 
          begin : LOAD_STORE_STATE
              data_req_o   = data_req_i;
         `ifdef GNT_BASED_FC
              data_gnt_o = data_gnt_i;
         `else
              data_stall_o = data_stall_i;
         `endif
              data_add_o   = data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_o    = data_be_i;
              data_wdata_o = data_wdata_i;
              data_wen_o   = data_wen_i;
              data_ID_o    = data_ID_i;

              if((TestAndSet == 1'b1) && (data_req_i == 1'b1))
              begin
              `ifdef GNT_BASED_FC
                  if(data_gnt_i  == 1'b1)
              `else
                  if(data_stall_i == 1'b0)
              `endif
                  begin
                    NS = SET_STORE;
                    Enable = 1'b1;
                  end
                  else
                  begin
                    NS = LOAD_STORE;
                    Enable = 1'b0;
                  end
              end
              else
              begin
                  NS = LOAD_STORE;
                  Enable = 1'b0;
              end

          end

          SET_STORE:
          begin : SET_STORE_STATE
              data_req_o   = 1'b1;

        `ifdef GNT_BASED_FC

              data_gnt_o = 1'b0;
        `else

              data_stall_o = 1'b1;
        `endif

              data_add_o   = data_add_S;
              data_be_o    = data_be_S;
              data_wdata_o = '1;
              data_wen_o   = 1'b0;
              data_ID_o    = data_ID_S;
              Enable       = 1'b0;

        `ifdef GNT_BASED_FC
              if(data_gnt_i  == 1'b1)
        `else
              if(data_stall_i == 1'b0)
        `endif
              begin
                    NS = LOAD_STORE;
              end
              else
              begin
                    NS = SET_STORE;
              end
          end



          default:
          begin
              data_req_o = 1'b0;

           `ifdef GNT_BASED_FC
              data_gnt_o = data_gnt_i;
           `else
              data_stall_o = data_stall_i;
           `endif

              data_add_o   = data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_o    = data_be_i;
              data_wdata_o = data_wdata_i;
              data_wen_o   = data_wen_i;
              data_ID_o    = data_ID_i;

              Enable     = 1'b0;
              NS         = LOAD_STORE;
          end

      endcase
    end

endmodule
module TestAndSet 
#(
    parameter ADDR_MEM_WIDTH  = 12,
    parameter ID_WIDTH        = 20,
    parameter DATA_WIDTH      = 32,
    parameter BE_WIDTH        = DATA_WIDTH/8
)
(
    input  logic                                 clk,
    input  logic                                 rst_n,        


    input  logic                                 data_req_i,
    input  logic [ADDR_MEM_WIDTH-1:0]            data_add_i,
    input  logic                                 data_wen_i,
    input  logic [DATA_WIDTH-1:0]                data_wdata_i,
    input  logic [BE_WIDTH-1:0]                  data_be_i,
    input  logic [ID_WIDTH-1:0]                  data_ID_i,
`ifdef GNT_BASED_FC
    output logic                                 data_gnt_o,
`else
    output logic                                 data_stall_o,
`endif



    output logic                                 data_req_o,
    output logic                                 data_ts_set_o,
    output logic [ADDR_MEM_WIDTH-2:0]            data_add_o,
    output logic                                 data_wen_o,
    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
`ifdef GNT_BASED_FC        
    input  logic                                 data_gnt_i
`else
    input  logic                                 data_stall_i
`endif
);


    enum logic { LOAD_STORE, SET_STORE }       CS, NS;
    logic                                      Enable;


    logic                                      TestAndSet;


    logic [ADDR_MEM_WIDTH-2:0]                 data_add_S;
    logic [BE_WIDTH-1:0]                       data_be_S;


    logic [ID_WIDTH-1:0]                       data_ID_S;



    assign TestAndSet = (data_add_i[ADDR_MEM_WIDTH-1]) && (data_wen_i == 1'b1);
    assign data_ts_set_o = (CS == SET_STORE);

    always_ff @(posedge clk, negedge  rst_n)
    begin : TestAndSet_UpdataState
      if(rst_n == 1'b0)
        begin
          CS <= LOAD_STORE;
          data_add_S   <= '0;
          data_be_S    <= '0;
          data_ID_S    <= '0;
        end
      else
        begin
          CS <= NS;


          if(Enable == 1'b1)
            begin
              data_add_S   <= data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_S    <= data_be_i;
              data_ID_S    <= data_ID_i;
            end

        end
    end


    always_comb
    begin : TestAndSet_ComputeState

      case(CS)

          LOAD_STORE: 
          begin : LOAD_STORE_STATE
              data_req_o   = data_req_i;
         `ifdef GNT_BASED_FC
              data_gnt_o = data_gnt_i;
         `else
              data_stall_o = data_stall_i;
         `endif
              data_add_o   = data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_o    = data_be_i;
              data_wdata_o = data_wdata_i;
              data_wen_o   = data_wen_i;
              data_ID_o    = data_ID_i;

              if((TestAndSet == 1'b1) && (data_req_i == 1'b1))
              begin
              `ifdef GNT_BASED_FC
                  if(data_gnt_i  == 1'b1)
              `else
                  if(data_stall_i == 1'b0)
              `endif
                  begin
                    NS = SET_STORE;
                    Enable = 1'b1;
                  end
                  else
                  begin
                    NS = LOAD_STORE;
                    Enable = 1'b0;
                  end
              end
              else
              begin
                  NS = LOAD_STORE;
                  Enable = 1'b0;
              end

          end

          SET_STORE:
          begin : SET_STORE_STATE
              data_req_o   = 1'b1;

        `ifdef GNT_BASED_FC

              data_gnt_o = 1'b0;
        `else

              data_stall_o = 1'b1;
        `endif

              data_add_o   = data_add_S;
              data_be_o    = data_be_S;
              data_wdata_o = '1;
              data_wen_o   = 1'b0;
              data_ID_o    = data_ID_S;
              Enable       = 1'b0;

        `ifdef GNT_BASED_FC
              if(data_gnt_i  == 1'b1)
        `else
              if(data_stall_i == 1'b0)
        `endif
              begin
                    NS = LOAD_STORE;
              end
              else
              begin
                    NS = SET_STORE;
              end
          end



          default:
          begin
              data_req_o = 1'b0;

           `ifdef GNT_BASED_FC
              data_gnt_o = data_gnt_i;
           `else
              data_stall_o = data_stall_i;
           `endif

              data_add_o   = data_add_i[ADDR_MEM_WIDTH-2:0];
              data_be_o    = data_be_i;
              data_wdata_o = data_wdata_i;
              data_wen_o   = data_wen_i;
              data_ID_o    = data_ID_i;

              Enable     = 1'b0;
              NS         = LOAD_STORE;
          end

      endcase
    end

endmodule