data/full_repos/permissive/468929885/verilog/rtl/c_elem_xil.v
1: b"%Error: data/full_repos/permissive/468929885/verilog/rtl/c_elem_xil.v:24: Cannot find file containing module: 'rs_lat'\nrs_lat lat\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/rs_lat\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/rs_lat.v\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/rs_lat.sv\n             rs_lat\n             rs_lat.v\n             rs_lat.sv\n             obj_dir/rs_lat\n             obj_dir/rs_lat.v\n             obj_dir/rs_lat.sv\n%Error: Exiting due to 1 error(s)\n"
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]			in,

	output							out

);

wire r;

assign r = !(|in);

wire s;

assign s = &in;

rs_lat lat
(

	.rst(rst),
	
	.r(r),
	.s(s),
	.out(out)
);

endmodule
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]			in,

	output							out

);


wire r;

assign r = !(|in);

wire s;

assign s = &in;

rs_lat lat
(

	.rst(rst),
	
	.r(r),
	.s(s),
	.out(out)
);

endmodule