data/full_repos/permissive/437141606/MIPS_fpga.v
1: b"%Error: data/full_repos/permissive/437141606/MIPS_fpga.v:33: Cannot find file containing module: 'mips'\n mips mips(clksec, reset,writedata, dataadr, \n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.v\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s)\n"
module mips_fpga(input			clk, reset, 
				 output			memwrite,
				 output[ 3:0]	top_an, 
				 output[ 7:0]	top_sseg,
				 input[ 7:0]	switches,
				 output			sinkBit );

	wire[31:0] 	pc, instr, dataadr, writedata, dispDat;
	wire 		clksec;
	reg[ 7:0] 	reg_hex1, reg_hex0;


	clk_gen top_clk(.clk50MHz(clk), .reset(reset), .clksec(clksec));
      

	mips mips(clksec, reset,writedata, dataadr, 
			     memwrite, switches[4:0], dispDat, pc, instr);	


	disp_hex_mux disp_unit (.clk(clk), .reset(1'b0), 
		.hex3(reg_hex1[7:4]), .hex2(reg_hex1[3:0]), 
		.hex1(reg_hex0[7:4]), .hex0(reg_hex0[3:0]),  
		.dp_in(4'b1111), .an(top_an), .sseg(top_sseg));










	always @ (posedge clk) begin
		reg_hex1 = pc[7:0];
		case ({switches[7],switches[6], switches[5]})
			3'b000:	begin
					reg_hex0 = dispDat[ 7:0];
					end
			3'b001:	begin
					reg_hex0 = instr[ 7:0];
					end
			3'b010:	begin
					reg_hex0 = dataadr[ 7:0];
					end
			3'b011:	begin
					reg_hex0 = writedata[ 7:0];
					end
			3'b100:	begin
					reg_hex0 = instr[ 7:0];
					end
			3'b101:	begin
					reg_hex0 = instr[ 15:8];
					end
			3'b110:	begin
					reg_hex0 = instr[ 23:16];
					end
			3'b111:	begin
					reg_hex0 = instr[ 31:24];
					end
			endcase
	end		


	assign sinkBit = (pc > 0) ^ (instr > 0) ^ (dataadr > 0) ^ (writedata > 0) ^ 
					 (dispDat > 0);
endmodule
module mips_fpga(input			clk, reset, 
				 output			memwrite,
				 output[ 3:0]	top_an, 
				 output[ 7:0]	top_sseg,
				 input[ 7:0]	switches,
				 output			sinkBit );


	wire[31:0] 	pc, instr, dataadr, writedata, dispDat;
	wire 		clksec;
	reg[ 7:0] 	reg_hex1, reg_hex0;


	clk_gen top_clk(.clk50MHz(clk), .reset(reset), .clksec(clksec));
      

	mips mips(clksec, reset,writedata, dataadr, 
			     memwrite, switches[4:0], dispDat, pc, instr);	


	disp_hex_mux disp_unit (.clk(clk), .reset(1'b0), 
		.hex3(reg_hex1[7:4]), .hex2(reg_hex1[3:0]), 
		.hex1(reg_hex0[7:4]), .hex0(reg_hex0[3:0]),  
		.dp_in(4'b1111), .an(top_an), .sseg(top_sseg));










	always @ (posedge clk) begin
		reg_hex1 = pc[7:0];
		case ({switches[7],switches[6], switches[5]})
			3'b000:	begin
					reg_hex0 = dispDat[ 7:0];
					end
			3'b001:	begin
					reg_hex0 = instr[ 7:0];
					end
			3'b010:	begin
					reg_hex0 = dataadr[ 7:0];
					end
			3'b011:	begin
					reg_hex0 = writedata[ 7:0];
					end
			3'b100:	begin
					reg_hex0 = instr[ 7:0];
					end
			3'b101:	begin
					reg_hex0 = instr[ 15:8];
					end
			3'b110:	begin
					reg_hex0 = instr[ 23:16];
					end
			3'b111:	begin
					reg_hex0 = instr[ 31:24];
					end
			endcase
	end		


	assign sinkBit = (pc > 0) ^ (instr > 0) ^ (dataadr > 0) ^ (writedata > 0) ^ 
					 (dispDat > 0);
endmodule