data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:157: syntax error, unexpected \'(\', expecting IDENTIFIER\npixel_clock(clk, clk25);\n            ^~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module enhanced_sync_output_tb; 


reg clk = 0;
wire vsync, hsync, data_enable;
wire [12:0] vcount, hcount;
always begin
    #20;
    clk = !clk;
    
end
enhanced_sync_signals dut(clk, vsync, hsync, data_enable, vcount, hcount);
endmodule
module enhanced_sync_output_tb;
 


reg clk = 0;
wire vsync, hsync, data_enable;
wire [12:0] vcount, hcount;
always begin
    #20;
    clk = !clk;
    
end
enhanced_sync_signals dut(clk, vsync, hsync, data_enable, vcount, hcount);
endmodule