data/full_repos/permissive/426016479/ISCAS/true_true_true_3/best_insertion/counter16_buffered.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/426016479/ISCAS/true_true_true_3/best_insertion/counter16_buffered.v:9: Multiple top level modules\n                                                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                    : ... Top module \'inverter\'\nmodule inverter( i , o );\n       ^~~~~~~~\n                                                                                                                    : ... Top module \'top\'\nmodule top( in_0_ , in_1_ , in_2_ , in_3_ , in_4_ , in_5_ , in_6_ , in_7_ , in_8_ , in_9_ , in_10_ , in_11_ , in_12_ , in_13_ , in_14_ , in_15_ , out_0_ , out_1_ , out_2_ , out_3_ , out_4_ );\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module buffer( i , o );
  input i ;
  output o ;
endmodule
module buffer( i , o );

  input i ;
  output o ;
endmodule