data/full_repos/permissive/446939020/risc-v/testbench.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:11: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:15: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:17: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:19: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:21: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446939020/risc-v/testbench.sv:23: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Error: data/full_repos/permissive/446939020/risc-v/testbench.sv:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/testbench.sv:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_Top_Module;
  
  reg clk,reset;



  
  Top_Module t1(clk,reset);
  
  initial clk=0;
  always #5 clk=~clk;
  
  initial begin
    reset=1;
    #10
    reset=0;
    #20
    reset=0;
    #20
   	reset=0;
    #20
    reset=0;
    #200
    $finish;
  end
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
  end

endmodule
module tb_Top_Module;

  
  reg clk,reset;



  
  Top_Module t1(clk,reset);
  
  initial clk=0;
  always #5 clk=~clk;
  
  initial begin
    reset=1;
    #10
    reset=0;
    #20
    reset=0;
    #20
   	reset=0;
    #20
    reset=0;
    #200
    $finish;
  end
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
  end

endmodule