data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1 if(product == expected)\n        ^\n%Error: data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v:21: Cannot find file containing module: \'multiplication\'\n    multiplication mul(.in_a(in_a), .in_b(in_b), .prod(product));\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469273213/multiplier/rtl,data/full_repos/permissive/469273213/multiplication\n             data/full_repos/permissive/469273213/multiplier/rtl,data/full_repos/permissive/469273213/multiplication.v\n             data/full_repos/permissive/469273213/multiplier/rtl,data/full_repos/permissive/469273213/multiplication.sv\n             multiplication\n             multiplication.v\n             multiplication.sv\n             obj_dir/multiplication\n             obj_dir/multiplication.v\n             obj_dir/multiplication.sv\n%Warning-WIDTH: data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v:26: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                          : ... In instance multiplication_tb\n            in_a = i;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/469273213/multiplier/rtl/multiplication_tb.v:28: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                          : ... In instance multiplication_tb\n                in_b = j;\n                     ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplication_tb;
    reg     [15:0] in_a, in_b;
    wire    [31:0] product;

    integer i, j, passed, failed;


    reg [31:0] expected;

    multiplication mul(.in_a(in_a), .in_b(in_b), .prod(product));

    initial begin
        passed = 0; failed = 0;
        for(i=0; i<=65_535; i=i+1) begin
            in_a = i;
            for (j=0; j<=65_535; j=j+1) begin
                in_b = j;
                expected = in_a*in_b;
            #10;
            end
        end
        $display("All tests were passed succesfully: %d", passed);
        $finish;
    end
    always @(expected) begin
        #1 if(product == expected)
            passed = passed + 1;
        else begin
            $display("Last test was failed.");
            failed = failed + 1;
            $finish;
        end
    end

endmodule
module multiplication_tb;

    reg     [15:0] in_a, in_b;
    wire    [31:0] product;

    integer i, j, passed, failed;


    reg [31:0] expected;

    multiplication mul(.in_a(in_a), .in_b(in_b), .prod(product));

    initial begin
        passed = 0; failed = 0;
        for(i=0; i<=65_535; i=i+1) begin
            in_a = i;
            for (j=0; j<=65_535; j=j+1) begin
                in_b = j;
                expected = in_a*in_b;
            #10;
            end
        end
        $display("All tests were passed succesfully: %d", passed);
        $finish;
    end
    always @(expected) begin
        #1 if(product == expected)
            passed = passed + 1;
        else begin
            $display("Last test was failed.");
            failed = failed + 1;
            $finish;
        end
    end

endmodule