data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:14: Cannot find include file: common_cells/registers.svh\n`include "common_cells/registers.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh.sv\n             common_cells/registers.svh\n             common_cells/registers.svh.v\n             common_cells/registers.svh.sv\n             obj_dir/common_cells/registers.svh\n             obj_dir/common_cells/registers.svh.v\n             obj_dir/common_cells/registers.svh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:17: syntax error, unexpected ::, expecting \')\' or \',\'\n  parameter fpnew_pkg::fmt_logic_t   FpFmtConfig  = \'1,\n                     ^~\n                                                                                                : ... Perhaps \'fpnew_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:20: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::AFTER,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:22: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter type                     AuxType     = logic,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:24: syntax error, unexpected localparam, expecting IDENTIFIER\n  localparam int unsigned WIDTH       = fpnew_pkg::max_fp_width(FpFmtConfig),\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:24: syntax error, unexpected ::, expecting \';\'\n  localparam int unsigned WIDTH       = fpnew_pkg::max_fp_width(FpFmtConfig),\n                                                 ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:25: syntax error, unexpected ::, expecting \';\'\n  localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS\n                                                 ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:28: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                        rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:30: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [1:0][WIDTH-1:0]       operands_i,  \n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:31: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [NUM_FORMATS-1:0][1:0] is_boxed_i,  \n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:32: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  fpnew_pkg::roundmode_e       rnd_mode_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:36: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  AuxType                      aux_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:38: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                        in_valid_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                        in_ready_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:40: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                        flush_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [WIDTH-1:0]            result_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output fpnew_pkg::status_t          status_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output TagType                      tag_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:46: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output AuxType                      aux_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                        out_valid_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:49: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                        out_ready_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:51: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                        busy_o\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:58: syntax error, unexpected ::\n  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE)\n                                                    ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:63: syntax error, unexpected ::\n  localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE)\n                                                    ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:74: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::roundmode_e rnd_mode_q;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:81: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                       inp_pipe_rnd_mode_q;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:91: syntax error, unexpected assign\n  assign inp_pipe_operands_q[0] = operands_i;\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:107: syntax error, unexpected assign\n    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];\n    ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:109: Define or directive not defined: \'`FFLARNC\'\n    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1\'b0, clk_i, rst_ni)\n    ^~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:113: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, \'0)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:114: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:115: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:116: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_dst_fmt_q[i+1],  inp_pipe_dst_fmt_q[i],  reg_ena, fpnew_pkg::fp_format_e\'(0))\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:117: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType\'(\'0))\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:118: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType\'(\'0))\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:135: syntax error, unexpected always_comb\n  always_comb begin : translate_fmt\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:168: syntax error, unexpected assign\n  assign inp_pipe_ready[NUM_INP_REGS] = in_ready;\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:240: Define or directive not defined: \'`FF\'\n  `FF(state_q, state_d, IDLE)\n  ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:248: Define or directive not defined: \'`FFL\'\n  `FFL(result_is_fp8_q, input_is_fp8,                 op_starting, \'0)\n  ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:248: syntax error, unexpected \'(\'\n  `FFL(result_is_fp8_q, input_is_fp8,                 op_starting, \'0)\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:249: Define or directive not defined: \'`FFL\'\n  `FFL(result_tag_q,    inp_pipe_tag_q[NUM_INP_REGS], op_starting, \'0)\n  ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:250: Define or directive not defined: \'`FFL\'\n  `FFL(result_aux_q,    inp_pipe_aux_q[NUM_INP_REGS], op_starting, \'0)\n  ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:257: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t unit_status, held_status_q;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:280: Define or directive not defined: \'`FFLNR\'\n  `FFLNR(held_result_q, adjusted_result, hold_result, clk_i)\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:281: Define or directive not defined: \'`FFLNR\'\n  `FFLNR(held_status_q, unit_status,     hold_result, clk_i)\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:287: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t status_d;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:297: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t [0:NUM_OUT_REGS]            out_pipe_status_q;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:305: syntax error, unexpected assign\n  assign out_pipe_result_q[0] = result_d;\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:319: syntax error, unexpected assign\n    assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];\n    ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_divsqrt_multi.sv:321: Define or directive not defined: \'`FFLARNC\'\n    `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1\'b0, clk_i, rst_ni)\n    ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module fpnew_divsqrt_multi #(
  parameter fpnew_pkg::fmt_logic_t   FpFmtConfig  = '1,

  parameter int unsigned             NumPipeRegs = 0,
  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::AFTER,
  parameter type                     TagType     = logic,
  parameter type                     AuxType     = logic,

  localparam int unsigned WIDTH       = fpnew_pkg::max_fp_width(FpFmtConfig),
  localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS
) (
  input  logic                        clk_i,
  input  logic                        rst_ni,

  input  logic [1:0][WIDTH-1:0]       operands_i,
  input  logic [NUM_FORMATS-1:0][1:0] is_boxed_i,
  input  fpnew_pkg::roundmode_e       rnd_mode_i,
  input  fpnew_pkg::operation_e       op_i,
  input  fpnew_pkg::fp_format_e       dst_fmt_i,
  input  TagType                      tag_i,
  input  AuxType                      aux_i,

  input  logic                        in_valid_i,
  output logic                        in_ready_o,
  input  logic                        flush_i,

  output logic [WIDTH-1:0]            result_o,
  output fpnew_pkg::status_t          status_o,
  output logic                        extension_bit_o,
  output TagType                      tag_o,
  output AuxType                      aux_o,

  output logic                        out_valid_o,
  input  logic                        out_ready_i,

  output logic                        busy_o
);





  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? (NumPipeRegs / 2)
                               : 0);
  localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? ((NumPipeRegs + 1) / 2)
                               : 0);





  logic [1:0][WIDTH-1:0] operands_q;
  fpnew_pkg::roundmode_e rnd_mode_q;
  fpnew_pkg::operation_e op_q;
  fpnew_pkg::fp_format_e dst_fmt_q;
  logic                  in_valid_q;


  logic                  [0:NUM_INP_REGS][1:0][WIDTH-1:0]       inp_pipe_operands_q;
  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                       inp_pipe_rnd_mode_q;
  fpnew_pkg::operation_e [0:NUM_INP_REGS]                       inp_pipe_op_q;
  fpnew_pkg::fp_format_e [0:NUM_INP_REGS]                       inp_pipe_dst_fmt_q;
  TagType                [0:NUM_INP_REGS]                       inp_pipe_tag_q;
  AuxType                [0:NUM_INP_REGS]                       inp_pipe_aux_q;
  logic                  [0:NUM_INP_REGS]                       inp_pipe_valid_q;

  logic [0:NUM_INP_REGS] inp_pipe_ready;


  assign inp_pipe_operands_q[0] = operands_i;
  assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
  assign inp_pipe_op_q[0]       = op_i;
  assign inp_pipe_dst_fmt_q[0]  = dst_fmt_i;
  assign inp_pipe_tag_q[0]      = tag_i;
  assign inp_pipe_aux_q[0]      = aux_i;
  assign inp_pipe_valid_q[0]    = in_valid_i;

  assign in_ready_o = inp_pipe_ready[0];

  for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline

    logic reg_ena;



    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];

    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];

    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)
    `FFL(inp_pipe_dst_fmt_q[i+1],  inp_pipe_dst_fmt_q[i],  reg_ena, fpnew_pkg::fp_format_e'(0))
    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType'('0))
    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType'('0))
  end

  assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
  assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS];
  assign op_q       = inp_pipe_op_q[NUM_INP_REGS];
  assign dst_fmt_q  = inp_pipe_dst_fmt_q[NUM_INP_REGS];
  assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS];




  logic [1:0]       divsqrt_fmt;
  logic [1:0][63:0] divsqrt_operands;
  logic             input_is_fp8;


  always_comb begin : translate_fmt
    unique case (dst_fmt_q)
      fpnew_pkg::FP32:    divsqrt_fmt = 2'b00;
      fpnew_pkg::FP64:    divsqrt_fmt = 2'b01;
      fpnew_pkg::FP16:    divsqrt_fmt = 2'b10;
      fpnew_pkg::FP16ALT: divsqrt_fmt = 2'b11;
      default:            divsqrt_fmt = 2'b10;
    endcase


    input_is_fp8 = FpFmtConfig[fpnew_pkg::FP8] & (dst_fmt_q == fpnew_pkg::FP8);


    divsqrt_operands[0] = input_is_fp8 ? operands_q[0] << 8 : operands_q[0];
    divsqrt_operands[1] = input_is_fp8 ? operands_q[1] << 8 : operands_q[1];
  end




  logic in_ready;
  logic div_valid, sqrt_valid;
  logic unit_ready, unit_done;
  logic op_starting;
  logic out_valid, out_ready;
  logic hold_result;
  logic data_is_held;
  logic unit_busy;

  typedef enum logic [1:0] {IDLE, BUSY, HOLD} fsm_state_e;
  fsm_state_e state_q, state_d;


  assign inp_pipe_ready[NUM_INP_REGS] = in_ready;


  assign div_valid   = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i;
  assign sqrt_valid  = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i;
  assign op_starting = div_valid | sqrt_valid;


  always_comb begin : flag_fsm

    in_ready     = 1'b0;
    out_valid    = 1'b0;
    hold_result  = 1'b0;
    data_is_held = 1'b0;
    unit_busy    = 1'b0;
    state_d      = state_q;

    unique case (state_q)

      IDLE: begin
        in_ready = 1'b1;
        if (in_valid_q && unit_ready) begin
          state_d = BUSY;
        end
      end

      BUSY: begin
        unit_busy = 1'b1;

        if (unit_done) begin
          out_valid = 1'b1;

          if (out_ready) begin
            state_d = IDLE;
            if (in_valid_q && unit_ready) begin
              in_ready = 1'b1;
              state_d  = BUSY;
            end

          end else begin
            hold_result = 1'b1;
            state_d     = HOLD;
          end
        end
      end

      HOLD: begin
        unit_busy    = 1'b1;
        data_is_held = 1'b1;
        out_valid    = 1'b1;

        if (out_ready) begin
          state_d = IDLE;
          if (in_valid_q && unit_ready) begin
            in_ready = 1'b1;
            state_d  = BUSY;
          end
        end
      end

      default: state_d = IDLE;
    endcase


    if (flush_i) begin
      unit_busy = 1'b0;
      out_valid = 1'b0;
      state_d   = IDLE;
    end
  end


  `FF(state_q, state_d, IDLE)


  logic result_is_fp8_q;
  TagType result_tag_q;
  AuxType result_aux_q;


  `FFL(result_is_fp8_q, input_is_fp8,                 op_starting, '0)
  `FFL(result_tag_q,    inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0)
  `FFL(result_aux_q,    inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0)




  logic [63:0]        unit_result;
  logic [WIDTH-1:0]   adjusted_result, held_result_q;
  fpnew_pkg::status_t unit_status, held_status_q;

  div_sqrt_top_mvp i_divsqrt_lei (
   .Clk_CI           ( clk_i               ),
   .Rst_RBI          ( rst_ni              ),
   .Div_start_SI     ( div_valid           ),
   .Sqrt_start_SI    ( sqrt_valid          ),
   .Operand_a_DI     ( divsqrt_operands[0] ),
   .Operand_b_DI     ( divsqrt_operands[1] ),
   .RM_SI            ( rnd_mode_q          ),
   .Precision_ctl_SI ( '0                  ),
   .Format_sel_SI    ( divsqrt_fmt         ),
   .Kill_SI          ( flush_i             ),
   .Result_DO        ( unit_result         ),
   .Fflags_SO        ( unit_status         ),
   .Ready_SO         ( unit_ready          ),
   .Done_SO          ( unit_done           )
  );


  assign adjusted_result = result_is_fp8_q ? unit_result >> 8 : unit_result;


  `FFLNR(held_result_q, adjusted_result, hold_result, clk_i)
  `FFLNR(held_status_q, unit_status,     hold_result, clk_i)




  logic [WIDTH-1:0]   result_d;
  fpnew_pkg::status_t status_d;

  assign result_d = data_is_held ? held_result_q : adjusted_result;
  assign status_d = data_is_held ? held_status_q : unit_status;





  logic               [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q;
  fpnew_pkg::status_t [0:NUM_OUT_REGS]            out_pipe_status_q;
  TagType             [0:NUM_OUT_REGS]            out_pipe_tag_q;
  AuxType             [0:NUM_OUT_REGS]            out_pipe_aux_q;
  logic               [0:NUM_OUT_REGS]            out_pipe_valid_q;

  logic [0:NUM_OUT_REGS] out_pipe_ready;


  assign out_pipe_result_q[0] = result_d;
  assign out_pipe_status_q[0] = status_d;
  assign out_pipe_tag_q[0]    = result_tag_q;
  assign out_pipe_aux_q[0]    = result_aux_q;
  assign out_pipe_valid_q[0]  = out_valid;

  assign out_ready = out_pipe_ready[0];

  for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline

    logic reg_ena;



    assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];

    `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];

    `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
    `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
    `FFL(out_pipe_tag_q[i+1],    out_pipe_tag_q[i],    reg_ena, TagType'('0))
    `FFL(out_pipe_aux_q[i+1],    out_pipe_aux_q[i],    reg_ena, AuxType'('0))
  end

  assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;

  assign result_o        = out_pipe_result_q[NUM_OUT_REGS];
  assign status_o        = out_pipe_status_q[NUM_OUT_REGS];
  assign extension_bit_o = 1'b1;
  assign tag_o           = out_pipe_tag_q[NUM_OUT_REGS];
  assign aux_o           = out_pipe_aux_q[NUM_OUT_REGS];
  assign out_valid_o     = out_pipe_valid_q[NUM_OUT_REGS];
  assign busy_o          = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});
endmodule
module fpnew_divsqrt_multi #(
  parameter fpnew_pkg::fmt_logic_t   FpFmtConfig  = '1,

  parameter int unsigned             NumPipeRegs = 0,
  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::AFTER,
  parameter type                     TagType     = logic,
  parameter type                     AuxType     = logic,

  localparam int unsigned WIDTH       = fpnew_pkg::max_fp_width(FpFmtConfig),
  localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS
) (
  input  logic                        clk_i,
  input  logic                        rst_ni,

  input  logic [1:0][WIDTH-1:0]       operands_i,
  input  logic [NUM_FORMATS-1:0][1:0] is_boxed_i,
  input  fpnew_pkg::roundmode_e       rnd_mode_i,
  input  fpnew_pkg::operation_e       op_i,
  input  fpnew_pkg::fp_format_e       dst_fmt_i,
  input  TagType                      tag_i,
  input  AuxType                      aux_i,

  input  logic                        in_valid_i,
  output logic                        in_ready_o,
  input  logic                        flush_i,

  output logic [WIDTH-1:0]            result_o,
  output fpnew_pkg::status_t          status_o,
  output logic                        extension_bit_o,
  output TagType                      tag_o,
  output AuxType                      aux_o,

  output logic                        out_valid_o,
  input  logic                        out_ready_i,

  output logic                        busy_o
);






  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? (NumPipeRegs / 2)
                               : 0);
  localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? ((NumPipeRegs + 1) / 2)
                               : 0);





  logic [1:0][WIDTH-1:0] operands_q;
  fpnew_pkg::roundmode_e rnd_mode_q;
  fpnew_pkg::operation_e op_q;
  fpnew_pkg::fp_format_e dst_fmt_q;
  logic                  in_valid_q;


  logic                  [0:NUM_INP_REGS][1:0][WIDTH-1:0]       inp_pipe_operands_q;
  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                       inp_pipe_rnd_mode_q;
  fpnew_pkg::operation_e [0:NUM_INP_REGS]                       inp_pipe_op_q;
  fpnew_pkg::fp_format_e [0:NUM_INP_REGS]                       inp_pipe_dst_fmt_q;
  TagType                [0:NUM_INP_REGS]                       inp_pipe_tag_q;
  AuxType                [0:NUM_INP_REGS]                       inp_pipe_aux_q;
  logic                  [0:NUM_INP_REGS]                       inp_pipe_valid_q;

  logic [0:NUM_INP_REGS] inp_pipe_ready;


  assign inp_pipe_operands_q[0] = operands_i;
  assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
  assign inp_pipe_op_q[0]       = op_i;
  assign inp_pipe_dst_fmt_q[0]  = dst_fmt_i;
  assign inp_pipe_tag_q[0]      = tag_i;
  assign inp_pipe_aux_q[0]      = aux_i;
  assign inp_pipe_valid_q[0]    = in_valid_i;

  assign in_ready_o = inp_pipe_ready[0];

  for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline

    logic reg_ena;



    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];

    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];

    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)
    `FFL(inp_pipe_dst_fmt_q[i+1],  inp_pipe_dst_fmt_q[i],  reg_ena, fpnew_pkg::fp_format_e'(0))
    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType'('0))
    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType'('0))
  end

  assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
  assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS];
  assign op_q       = inp_pipe_op_q[NUM_INP_REGS];
  assign dst_fmt_q  = inp_pipe_dst_fmt_q[NUM_INP_REGS];
  assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS];




  logic [1:0]       divsqrt_fmt;
  logic [1:0][63:0] divsqrt_operands;
  logic             input_is_fp8;


  always_comb begin : translate_fmt
    unique case (dst_fmt_q)
      fpnew_pkg::FP32:    divsqrt_fmt = 2'b00;
      fpnew_pkg::FP64:    divsqrt_fmt = 2'b01;
      fpnew_pkg::FP16:    divsqrt_fmt = 2'b10;
      fpnew_pkg::FP16ALT: divsqrt_fmt = 2'b11;
      default:            divsqrt_fmt = 2'b10;
    endcase


    input_is_fp8 = FpFmtConfig[fpnew_pkg::FP8] & (dst_fmt_q == fpnew_pkg::FP8);


    divsqrt_operands[0] = input_is_fp8 ? operands_q[0] << 8 : operands_q[0];
    divsqrt_operands[1] = input_is_fp8 ? operands_q[1] << 8 : operands_q[1];
  end




  logic in_ready;
  logic div_valid, sqrt_valid;
  logic unit_ready, unit_done;
  logic op_starting;
  logic out_valid, out_ready;
  logic hold_result;
  logic data_is_held;
  logic unit_busy;

  typedef enum logic [1:0] {IDLE, BUSY, HOLD} fsm_state_e;
  fsm_state_e state_q, state_d;


  assign inp_pipe_ready[NUM_INP_REGS] = in_ready;


  assign div_valid   = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i;
  assign sqrt_valid  = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i;
  assign op_starting = div_valid | sqrt_valid;


  always_comb begin : flag_fsm

    in_ready     = 1'b0;
    out_valid    = 1'b0;
    hold_result  = 1'b0;
    data_is_held = 1'b0;
    unit_busy    = 1'b0;
    state_d      = state_q;

    unique case (state_q)

      IDLE: begin
        in_ready = 1'b1;
        if (in_valid_q && unit_ready) begin
          state_d = BUSY;
        end
      end

      BUSY: begin
        unit_busy = 1'b1;

        if (unit_done) begin
          out_valid = 1'b1;

          if (out_ready) begin
            state_d = IDLE;
            if (in_valid_q && unit_ready) begin
              in_ready = 1'b1;
              state_d  = BUSY;
            end

          end else begin
            hold_result = 1'b1;
            state_d     = HOLD;
          end
        end
      end

      HOLD: begin
        unit_busy    = 1'b1;
        data_is_held = 1'b1;
        out_valid    = 1'b1;

        if (out_ready) begin
          state_d = IDLE;
          if (in_valid_q && unit_ready) begin
            in_ready = 1'b1;
            state_d  = BUSY;
          end
        end
      end

      default: state_d = IDLE;
    endcase


    if (flush_i) begin
      unit_busy = 1'b0;
      out_valid = 1'b0;
      state_d   = IDLE;
    end
  end


  `FF(state_q, state_d, IDLE)


  logic result_is_fp8_q;
  TagType result_tag_q;
  AuxType result_aux_q;


  `FFL(result_is_fp8_q, input_is_fp8,                 op_starting, '0)
  `FFL(result_tag_q,    inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0)
  `FFL(result_aux_q,    inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0)




  logic [63:0]        unit_result;
  logic [WIDTH-1:0]   adjusted_result, held_result_q;
  fpnew_pkg::status_t unit_status, held_status_q;

  div_sqrt_top_mvp i_divsqrt_lei (
   .Clk_CI           ( clk_i               ),
   .Rst_RBI          ( rst_ni              ),
   .Div_start_SI     ( div_valid           ),
   .Sqrt_start_SI    ( sqrt_valid          ),
   .Operand_a_DI     ( divsqrt_operands[0] ),
   .Operand_b_DI     ( divsqrt_operands[1] ),
   .RM_SI            ( rnd_mode_q          ),
   .Precision_ctl_SI ( '0                  ),
   .Format_sel_SI    ( divsqrt_fmt         ),
   .Kill_SI          ( flush_i             ),
   .Result_DO        ( unit_result         ),
   .Fflags_SO        ( unit_status         ),
   .Ready_SO         ( unit_ready          ),
   .Done_SO          ( unit_done           )
  );


  assign adjusted_result = result_is_fp8_q ? unit_result >> 8 : unit_result;


  `FFLNR(held_result_q, adjusted_result, hold_result, clk_i)
  `FFLNR(held_status_q, unit_status,     hold_result, clk_i)




  logic [WIDTH-1:0]   result_d;
  fpnew_pkg::status_t status_d;

  assign result_d = data_is_held ? held_result_q : adjusted_result;
  assign status_d = data_is_held ? held_status_q : unit_status;





  logic               [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q;
  fpnew_pkg::status_t [0:NUM_OUT_REGS]            out_pipe_status_q;
  TagType             [0:NUM_OUT_REGS]            out_pipe_tag_q;
  AuxType             [0:NUM_OUT_REGS]            out_pipe_aux_q;
  logic               [0:NUM_OUT_REGS]            out_pipe_valid_q;

  logic [0:NUM_OUT_REGS] out_pipe_ready;


  assign out_pipe_result_q[0] = result_d;
  assign out_pipe_status_q[0] = status_d;
  assign out_pipe_tag_q[0]    = result_tag_q;
  assign out_pipe_aux_q[0]    = result_aux_q;
  assign out_pipe_valid_q[0]  = out_valid;

  assign out_ready = out_pipe_ready[0];

  for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline

    logic reg_ena;



    assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];

    `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];

    `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
    `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
    `FFL(out_pipe_tag_q[i+1],    out_pipe_tag_q[i],    reg_ena, TagType'('0))
    `FFL(out_pipe_aux_q[i+1],    out_pipe_aux_q[i],    reg_ena, AuxType'('0))
  end

  assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;

  assign result_o        = out_pipe_result_q[NUM_OUT_REGS];
  assign status_o        = out_pipe_status_q[NUM_OUT_REGS];
  assign extension_bit_o = 1'b1;
  assign tag_o           = out_pipe_tag_q[NUM_OUT_REGS];
  assign aux_o           = out_pipe_aux_q[NUM_OUT_REGS];
  assign out_valid_o     = out_pipe_valid_q[NUM_OUT_REGS];
  assign busy_o          = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});
endmodule