data/full_repos/permissive/529698244/ai_accel.v
1: b'%Error: data/full_repos/permissive/529698244/ai_accel.v:320: syntax error, unexpected var, expecting IDENTIFIER\n  variance var(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}),\n           ^~~\n%Error: Exiting due to 1 error(s)\n'
module ai_accel
(
        rst_n		,
        clk,
        addr		,
		  wr_en,
		  accel_select,
		  data_in,
		  ctr,
        data_out
    );
	 
	 input rst_n;
	 input clk;
	 input [31:0] addr;
	 input wr_en;
	 input accel_select;
	 input [31:0] data_in;
	 output [31:0] data_out;
	 output [15:0] ctr;
	 
	 reg [31:0] data_out;
 
	 reg go_bit;
	 wire go_bit_in;
	 reg done_bit;
	 wire done_bit_in;

	 reg [15:0] counter;
	 


	 wire [31:0] data_G;
	 reg [31:0] result;

	 




	 reg [31:0] img_row_1, 
					img_row_2, 
					img_row_3, 
					img_row_4;
					

	 reg [31:0] msk_row_1, 
					msk_row_2, 
					msk_row_3;
					

	 wire [31:0] m_out_1_1, m_out_1_2, m_out_1_3, m_out_1_4,
					 m_out_2_1, m_out_2_2, m_out_2_3, m_out_2_4,
					 m_out_3_1, m_out_3_2, m_out_3_3, m_out_3_4;
					 

	 wire [31:0] a_out_1,
					 a_out_2,
					 a_out_3,
					 a_out_4;
					 

	 wire [31:0] mean_out;
					 

	 wire[31:0] z_mean_out;
	 

	 wire[31:0] var_out;
	 

	 assign ctr = counter;
	 

	 always @(addr[6:2], img_row_1, img_row_2, img_row_3, img_row_4,
				 msk_row_1, msk_row_2, msk_row_3,
				 data_G, counter, done_bit, go_bit, counter) begin
		case(addr[6:2])
		5'b01000: data_out = {done_bit, 30'b0, go_bit};
		5'b01001: data_out = {16'b0, counter}; 


		5'b01010: data_out = img_row_1;
		5'b01011: data_out = img_row_2;
		5'b01100: data_out = img_row_3;
		5'b01101: data_out = img_row_4;
		5'b01110: data_out = msk_row_1;
		5'b01111: data_out = msk_row_2;
		5'b10000: data_out = msk_row_3;
		5'b10001: data_out = data_G;
		default: data_out = 32'b1;
		endcase
	 end
	 
	 assign go_bit_in = (wr_en & accel_select & (addr[6:2] == 5'b01000));
	
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) go_bit <= 1'b0;
		else go_bit <=  go_bit_in ? 1'b1 : 1'b0;
		
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) begin
			counter <= 16'b0;
			
			img_row_1 <= 32'b0;
			img_row_2 <= 32'b0;
			img_row_3 <= 32'b0;
			img_row_4 <= 32'b0;
			
			msk_row_1 <= 32'b0;
			msk_row_2 <= 32'b0;
			msk_row_3 <= 32'b0;
			


		end
		else begin
			if (wr_en & accel_select) begin	
				img_row_1 <= (addr[6:2] == 5'b01010) ? data_in : img_row_1;
				img_row_2 <= (addr[6:2] == 5'b01011) ? data_in : img_row_2;
				img_row_3 <= (addr[6:2] == 5'b01100) ? data_in : img_row_3;
				img_row_4 <= (addr[6:2] == 5'b01101) ? data_in : img_row_4;
				
				msk_row_1 <= (addr[6:2] == 5'b01110) ? data_in : msk_row_1;
				msk_row_2 <= (addr[6:2] == 5'b01111) ? data_in : msk_row_2;
				msk_row_3 <= (addr[6:2] == 5'b10000) ? data_in : msk_row_3;
				


			end
			else begin
				img_row_1 <= img_row_1;
				img_row_2 <= img_row_2;
				img_row_3 <= img_row_3;
				img_row_4 <= img_row_4;
				
				msk_row_1 <= msk_row_1; 
				msk_row_2 <= msk_row_2;
				msk_row_3 <= msk_row_3;
								


			end
			counter <= go_bit_in? 16'h00 : done_bit_in ? counter : counter +16'h01;
		end
		


	 

	 

	 multiplier mul_1_1(.a(msk_row_1), .b({img_row_1[31:8], 8'b0}), .c(m_out_1_1));
	 multiplier mul_1_2(.a(msk_row_1), .b({img_row_1[23:0], 8'b0}), .c(m_out_1_2));
	 multiplier mul_1_3(.a(msk_row_1), .b({img_row_2[31:8], 8'b0}), .c(m_out_1_3));
	 multiplier mul_1_4(.a(msk_row_1), .b({img_row_2[23:0], 8'b0}), .c(m_out_1_4));
	 
	 multiplier mul_2_1(.a(msk_row_2), .b({img_row_2[31:8], 8'b0}), .c(m_out_2_1));
	 multiplier mul_2_2(.a(msk_row_2), .b({img_row_2[23:0], 8'b0}), .c(m_out_2_2));
	 multiplier mul_2_3(.a(msk_row_2), .b({img_row_3[31:8], 8'b0}), .c(m_out_2_3));
	 multiplier mul_2_4(.a(msk_row_2), .b({img_row_3[23:0], 8'b0}), .c(m_out_2_4));
	 
	 multiplier mul_3_1(.a(msk_row_3), .b({img_row_3[31:8], 8'b0}), .c(m_out_3_1));
	 multiplier mul_3_2(.a(msk_row_3), .b({img_row_3[23:0], 8'b0}), .c(m_out_3_2));
	 multiplier mul_3_3(.a(msk_row_3), .b({img_row_4[31:8], 8'b0}), .c(m_out_3_3));
	 multiplier mul_3_4(.a(msk_row_3), .b({img_row_4[23:0], 8'b0}), .c(m_out_3_4));
	 
	 

	 adder add_1(.a(m_out_1_1), .b(m_out_2_1), .c(m_out_3_1), .d(a_out_1));
	 adder add_2(.a(m_out_1_2), .b(m_out_2_2), .c(m_out_3_2), .d(a_out_2));
	 adder add_3(.a(m_out_1_3), .b(m_out_2_3), .c(m_out_3_3), .d(a_out_3));
	 adder add_4(.a(m_out_1_4), .b(m_out_2_4), .c(m_out_3_4), .d(a_out_4));
	 

	 mean mn(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}), .b(mean_out));
	 

	 zero_mean z_mean(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}),
							.b(z_mean_out), .e(mean_out));
							

	 variance var(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}),
					  .b(mean_out), .c(var_out));
	 


	assign data_G = z_mean_out;
							 
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) result <=32'h0;

	 	 

	 
	 assign done_bit_in = !(z_mean_out != 32'd0) ;
	 
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) done_bit <= 1'b0;
		else done_bit <= go_bit_in ? 1'b0 : done_bit_in;
	 
endmodule
module ai_accel
(
        rst_n		,
        clk,
        addr		,
		  wr_en,
		  accel_select,
		  data_in,
		  ctr,
        data_out
    );

	 
	 input rst_n;
	 input clk;
	 input [31:0] addr;
	 input wr_en;
	 input accel_select;
	 input [31:0] data_in;
	 output [31:0] data_out;
	 output [15:0] ctr;
	 
	 reg [31:0] data_out;
 
	 reg go_bit;
	 wire go_bit_in;
	 reg done_bit;
	 wire done_bit_in;

	 reg [15:0] counter;
	 


	 wire [31:0] data_G;
	 reg [31:0] result;

	 




	 reg [31:0] img_row_1, 
					img_row_2, 
					img_row_3, 
					img_row_4;
					

	 reg [31:0] msk_row_1, 
					msk_row_2, 
					msk_row_3;
					

	 wire [31:0] m_out_1_1, m_out_1_2, m_out_1_3, m_out_1_4,
					 m_out_2_1, m_out_2_2, m_out_2_3, m_out_2_4,
					 m_out_3_1, m_out_3_2, m_out_3_3, m_out_3_4;
					 

	 wire [31:0] a_out_1,
					 a_out_2,
					 a_out_3,
					 a_out_4;
					 

	 wire [31:0] mean_out;
					 

	 wire[31:0] z_mean_out;
	 

	 wire[31:0] var_out;
	 

	 assign ctr = counter;
	 

	 always @(addr[6:2], img_row_1, img_row_2, img_row_3, img_row_4,
				 msk_row_1, msk_row_2, msk_row_3,
				 data_G, counter, done_bit, go_bit, counter) begin
		case(addr[6:2])
		5'b01000: data_out = {done_bit, 30'b0, go_bit};
		5'b01001: data_out = {16'b0, counter}; 


		5'b01010: data_out = img_row_1;
		5'b01011: data_out = img_row_2;
		5'b01100: data_out = img_row_3;
		5'b01101: data_out = img_row_4;
		5'b01110: data_out = msk_row_1;
		5'b01111: data_out = msk_row_2;
		5'b10000: data_out = msk_row_3;
		5'b10001: data_out = data_G;
		default: data_out = 32'b1;
		endcase
	 end
	 
	 assign go_bit_in = (wr_en & accel_select & (addr[6:2] == 5'b01000));
	
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) go_bit <= 1'b0;
		else go_bit <=  go_bit_in ? 1'b1 : 1'b0;
		
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) begin
			counter <= 16'b0;
			
			img_row_1 <= 32'b0;
			img_row_2 <= 32'b0;
			img_row_3 <= 32'b0;
			img_row_4 <= 32'b0;
			
			msk_row_1 <= 32'b0;
			msk_row_2 <= 32'b0;
			msk_row_3 <= 32'b0;
			


		end
		else begin
			if (wr_en & accel_select) begin	
				img_row_1 <= (addr[6:2] == 5'b01010) ? data_in : img_row_1;
				img_row_2 <= (addr[6:2] == 5'b01011) ? data_in : img_row_2;
				img_row_3 <= (addr[6:2] == 5'b01100) ? data_in : img_row_3;
				img_row_4 <= (addr[6:2] == 5'b01101) ? data_in : img_row_4;
				
				msk_row_1 <= (addr[6:2] == 5'b01110) ? data_in : msk_row_1;
				msk_row_2 <= (addr[6:2] == 5'b01111) ? data_in : msk_row_2;
				msk_row_3 <= (addr[6:2] == 5'b10000) ? data_in : msk_row_3;
				


			end
			else begin
				img_row_1 <= img_row_1;
				img_row_2 <= img_row_2;
				img_row_3 <= img_row_3;
				img_row_4 <= img_row_4;
				
				msk_row_1 <= msk_row_1; 
				msk_row_2 <= msk_row_2;
				msk_row_3 <= msk_row_3;
								


			end
			counter <= go_bit_in? 16'h00 : done_bit_in ? counter : counter +16'h01;
		end
		


	 

	 

	 multiplier mul_1_1(.a(msk_row_1), .b({img_row_1[31:8], 8'b0}), .c(m_out_1_1));
	 multiplier mul_1_2(.a(msk_row_1), .b({img_row_1[23:0], 8'b0}), .c(m_out_1_2));
	 multiplier mul_1_3(.a(msk_row_1), .b({img_row_2[31:8], 8'b0}), .c(m_out_1_3));
	 multiplier mul_1_4(.a(msk_row_1), .b({img_row_2[23:0], 8'b0}), .c(m_out_1_4));
	 
	 multiplier mul_2_1(.a(msk_row_2), .b({img_row_2[31:8], 8'b0}), .c(m_out_2_1));
	 multiplier mul_2_2(.a(msk_row_2), .b({img_row_2[23:0], 8'b0}), .c(m_out_2_2));
	 multiplier mul_2_3(.a(msk_row_2), .b({img_row_3[31:8], 8'b0}), .c(m_out_2_3));
	 multiplier mul_2_4(.a(msk_row_2), .b({img_row_3[23:0], 8'b0}), .c(m_out_2_4));
	 
	 multiplier mul_3_1(.a(msk_row_3), .b({img_row_3[31:8], 8'b0}), .c(m_out_3_1));
	 multiplier mul_3_2(.a(msk_row_3), .b({img_row_3[23:0], 8'b0}), .c(m_out_3_2));
	 multiplier mul_3_3(.a(msk_row_3), .b({img_row_4[31:8], 8'b0}), .c(m_out_3_3));
	 multiplier mul_3_4(.a(msk_row_3), .b({img_row_4[23:0], 8'b0}), .c(m_out_3_4));
	 
	 

	 adder add_1(.a(m_out_1_1), .b(m_out_2_1), .c(m_out_3_1), .d(a_out_1));
	 adder add_2(.a(m_out_1_2), .b(m_out_2_2), .c(m_out_3_2), .d(a_out_2));
	 adder add_3(.a(m_out_1_3), .b(m_out_2_3), .c(m_out_3_3), .d(a_out_3));
	 adder add_4(.a(m_out_1_4), .b(m_out_2_4), .c(m_out_3_4), .d(a_out_4));
	 

	 mean mn(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}), .b(mean_out));
	 

	 zero_mean z_mean(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}),
							.b(z_mean_out), .e(mean_out));
							

	 variance var(.a({a_out_1[7:0], a_out_2[7:0], a_out_3[7:0], a_out_4[7:0]}),
					  .b(mean_out), .c(var_out));
	 


	assign data_G = z_mean_out;
							 
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) result <=32'h0;

	 	 

	 
	 assign done_bit_in = !(z_mean_out != 32'd0) ;
	 
	 always @(posedge clk or negedge rst_n)
		if(~rst_n) done_bit <= 1'b0;
		else done_bit <= go_bit_in ? 1'b0 : done_bit_in;
	 
endmodule