data/full_repos/permissive/476411617/Controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:298: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:298: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:299: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_up_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:299: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:302: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset-LENGTH/2;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:302: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset-LENGTH/2;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:303: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_up_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:303: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:306: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset - LENGTH/2;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:306: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_ptr  <= rd_ptr + offset - LENGTH/2;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:307: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'rd_up_ptr\' generates 10 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset - LENGTH/2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/Controller.v:307: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                     : ... In instance Controller\n     rd_up_ptr <= rd_up_ptr + offset - LENGTH/2;\n               ^~\n%Error: Exiting due to 12 warning(s)\n'
module  Controller  #(parameter LENGTH = 32)
	(
		input clk, 
		input reset,
		input start,

		input[31:0] instruction,
		

        output reg[3:0] alu_op,


        output reg wea,
		output reg web,
		output reg[9:0] addra, 
		output reg[9:0] addrb,


		output reg east, 
		output reg west, 
		output reg south, 
		output reg north,
		output reg[1:0] east_mode,
		output reg[1:0] west_mode,
		output reg[1:0] south_mode,
		output reg[1:0] north_mode,


		output reg[7:0] count,



		output reg[2:0] state
    );

parameter  Q = 3'b000, OP = 3'b001, SHIFT = 3'b010, WB = 3'b011, DFF_BRAM = 3'b100, DFF_ALU = 3'b101;


wire[9:0] rs1_base, rs2_base, rd_base, rd_up_base;
wire[5:0] opcode;

reg[31:0] offset;
reg[9:0] rs1_ptr, rs2_ptr, rd_ptr, rd_up_ptr, q_ptr, shift_ptr;
reg[10:0] ram_ptr;
reg[6:0] iter;
reg start_flag;

reg finish_flag;

integer i;

assign rd_base    = (opcode == 9 || opcode == 10) ? instruction[25:21]*LENGTH+LENGTH-1 : instruction[25:21]*LENGTH;
assign rs1_base   = (opcode == 9 || opcode == 10) ? instruction[20:16]*LENGTH+LENGTH-1 : instruction[20:16]*LENGTH;
assign rs2_base   = (opcode == 9 || opcode == 10) ? instruction[15:11]*LENGTH+LENGTH-1 : instruction[15:11]*LENGTH;
assign rd_up_base = instruction[25:21]*LENGTH+LENGTH;

assign opcode = instruction[31:26];



always @ (posedge clk)
begin
	
	if (reset == 0) begin


		wea			<=	0;
		web			<=	0;
		addra		<=	0;
		addrb		<=	0;




		east		<=	0;
		west		<=	0;
		south		<=	0;
		north		<=	0;
		east_mode	<=	0;
		west_mode	<= 	0;
		south_mode	<=	0;
		north_mode	<=	0;

		rs1_ptr 	<= rs1_base;
		rs2_ptr 	<= rs2_base;
		rd_ptr 		<= rd_base;
		rd_up_ptr 	<= rd_base;
		q_ptr		<= rs2_base;
		shift_ptr	<= rd_base;
		ram_ptr		<=	'h400;

		count		<=	0;
		iter		<=	0;
		offset		<= 	0;

		start_flag	<= 	0;
		finish_flag	<=	0;

		case(opcode)
			0:	begin

				alu_op		<=	0;

				state		<=	OP;
				end
			1:	begin

				alu_op		<=	1;

				state		<=	OP;
				end
			2:	begin

				alu_op		<=	2;

				state		<=	Q;		
				end
			5,6,7,8: 	begin

				alu_op		<=	'hf;

				state		<=	OP;
				end
			9:	begin

				alu_op		<=	9;

				state		<=	OP;
				end
			10:	begin

				alu_op		<=	10;

				state		<=	OP;
				end
		endcase	
		
	end

	else if(start) begin

		wea			<=	0;
		web			<=	0;
		addra		<=	0;
		addrb		<=	0;




		east		<=	0;
		west		<=	0;
		south		<=	0;
		north		<=	0;
		east_mode	<=	0;
		west_mode	<=	0;
		south_mode	<=	0;
		north_mode	<=	0;


		rs1_ptr 	<= rs1_base;
		rs2_ptr 	<= rs2_base;
		rd_ptr 		<= rd_base;
		rd_up_ptr 	<= rd_base;
		q_ptr		<= rs2_base;
		shift_ptr	<= rd_base;
		ram_ptr		<=	0;

		count		<=	0;
		iter		<=	0;
		offset		<= 	0;

		start_flag	<= 	1;
		finish_flag	<=	0;

		case(opcode)
			0:	begin

				alu_op		<=	0;

				state		<=	OP;
				end
			1:	begin

				alu_op		<=	1;

				state		<=	OP;
				end
			2:	begin

				alu_op		<=	2;

				state		<=	Q;
				end
			5,6,7,8: 	begin

				alu_op		<=	'hf;

				state		<=	OP;
				end			
			9:	begin

				alu_op		<=	9;

				state		<=	OP;
				end
			10:	begin

				alu_op		<=	10;

				state		<=	OP;
				end
		endcase	
	end
	
	else if(start_flag&&!finish_flag) begin
		count <= count + 1;
		case(opcode)
		0,1:	begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr + 1;
					rs2_ptr 	<= rs2_ptr + 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr + 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end
		2:	begin
				
				if(iter<=LENGTH) begin
				case(state)
				Q: begin

					rs1_ptr 	<= rs1_base;
					rs2_ptr 	<= rs2_base;
					q_ptr 		<= q_ptr + 1;

					addrb 		<= q_ptr;
					wea 		<= 0;

					iter 		<= iter + 1;
					offset		<= offset + 1;

					state 		<= OP;
					if(iter<LENGTH/2) begin				
					rd_ptr		<= rd_ptr + offset;
					rd_up_ptr	<= rd_up_ptr + offset;
					end
					else if(iter==LENGTH/2) begin
					rd_ptr		<= rd_ptr + offset-LENGTH/2;
					rd_up_ptr	<= rd_up_ptr + offset;
					end
					else if(iter>LENGTH/2) begin
					rd_ptr		<= rd_ptr + offset - LENGTH/2;
					rd_up_ptr	<= rd_up_ptr + offset - LENGTH/2;
					end
				end
				OP: begin
					

					rd_up_ptr	<= rd_up_ptr + 1;
					rd_ptr 		<= rd_ptr + 1;
					rs1_ptr		<= rs1_ptr + 1;
					


					if(iter==1 && count<(2*LENGTH)+1) begin
						addra <= 0;
						addrb <= rs1_ptr;
					end

					else if(count==(2*LENGTH)+1) begin
						addra 	<= rd_ptr - 1;
						addrb 	<= 0;
					end

					else begin
						addra  	<= rd_up_ptr;
						addrb 	<= rs1_ptr;
					end
					wea 	<= 0;

					state 		<= WB;			
				end

				WB: begin
				
					if(count<(2*LENGTH)+2) begin
						addra 		<= rd_ptr-1;
						wea 		<= 1;

						state 		<= OP;
					end 

					else if(iter<LENGTH+1) begin
						rd_ptr		<= rd_base;
						rd_up_ptr	<= rd_base;

						addra		<= rd_ptr-1;
						addrb		<= 0;
						wea			<= 1;

						count 		<= 0;

						state 		<= SHIFT;
						
					end

					else begin
						wea 		<= 0;

						state 		<= Q;
					end
					
				
				end
				SHIFT: begin

					
					rd_ptr		<= rd_base;
					rd_up_ptr	<= rd_base;
					
					addra		<= 0;
					addrb 		<= 0;
					wea			<= 0;
					
					count 		<= 0;
					
					state 		<= Q;
				end
				endcase
				end
				else finish_flag <= 1;
				
			end
		5: 	begin
				east	<= 1;
				east_mode	<=	1; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	0;

				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					east_mode	<=	0; 
					north_mode	<=	2;
				end
				if(count==LENGTH+1) begin
					finish_flag <=  1;
					east_mode	<=	0; 
					north_mode	<=	0;
					wea 		<= 0;
					web			<= 0;
				end
			end
	
		7: 	begin
				south	<= 1;
				east_mode	<=	0; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	0;
				
				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					finish_flag <=  1;
				end
			end
		8: 	begin
				north	<= 1;
				east_mode	<=	0; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	1;

				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					north_mode	<=	2;
				end
				if(count==LENGTH+1) begin
					north_mode	<=	0;
					finish_flag <=  1;
				end
			end
		9:
			begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr - 1;
					rs2_ptr 	<= rs2_ptr - 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr - 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end		
		10:
			begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr - 1;
					rs2_ptr 	<= rs2_ptr - 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr - 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end
		endcase
		end
end
endmodule
module  Controller  #(parameter LENGTH = 32)
	(
		input clk, 
		input reset,
		input start,

		input[31:0] instruction,
		

        output reg[3:0] alu_op,


        output reg wea,
		output reg web,
		output reg[9:0] addra, 
		output reg[9:0] addrb,


		output reg east, 
		output reg west, 
		output reg south, 
		output reg north,
		output reg[1:0] east_mode,
		output reg[1:0] west_mode,
		output reg[1:0] south_mode,
		output reg[1:0] north_mode,


		output reg[7:0] count,



		output reg[2:0] state
    );


parameter  Q = 3'b000, OP = 3'b001, SHIFT = 3'b010, WB = 3'b011, DFF_BRAM = 3'b100, DFF_ALU = 3'b101;


wire[9:0] rs1_base, rs2_base, rd_base, rd_up_base;
wire[5:0] opcode;

reg[31:0] offset;
reg[9:0] rs1_ptr, rs2_ptr, rd_ptr, rd_up_ptr, q_ptr, shift_ptr;
reg[10:0] ram_ptr;
reg[6:0] iter;
reg start_flag;

reg finish_flag;

integer i;

assign rd_base    = (opcode == 9 || opcode == 10) ? instruction[25:21]*LENGTH+LENGTH-1 : instruction[25:21]*LENGTH;
assign rs1_base   = (opcode == 9 || opcode == 10) ? instruction[20:16]*LENGTH+LENGTH-1 : instruction[20:16]*LENGTH;
assign rs2_base   = (opcode == 9 || opcode == 10) ? instruction[15:11]*LENGTH+LENGTH-1 : instruction[15:11]*LENGTH;
assign rd_up_base = instruction[25:21]*LENGTH+LENGTH;

assign opcode = instruction[31:26];



always @ (posedge clk)
begin
	
	if (reset == 0) begin


		wea			<=	0;
		web			<=	0;
		addra		<=	0;
		addrb		<=	0;




		east		<=	0;
		west		<=	0;
		south		<=	0;
		north		<=	0;
		east_mode	<=	0;
		west_mode	<= 	0;
		south_mode	<=	0;
		north_mode	<=	0;

		rs1_ptr 	<= rs1_base;
		rs2_ptr 	<= rs2_base;
		rd_ptr 		<= rd_base;
		rd_up_ptr 	<= rd_base;
		q_ptr		<= rs2_base;
		shift_ptr	<= rd_base;
		ram_ptr		<=	'h400;

		count		<=	0;
		iter		<=	0;
		offset		<= 	0;

		start_flag	<= 	0;
		finish_flag	<=	0;

		case(opcode)
			0:	begin

				alu_op		<=	0;

				state		<=	OP;
				end
			1:	begin

				alu_op		<=	1;

				state		<=	OP;
				end
			2:	begin

				alu_op		<=	2;

				state		<=	Q;		
				end
			5,6,7,8: 	begin

				alu_op		<=	'hf;

				state		<=	OP;
				end
			9:	begin

				alu_op		<=	9;

				state		<=	OP;
				end
			10:	begin

				alu_op		<=	10;

				state		<=	OP;
				end
		endcase	
		
	end

	else if(start) begin

		wea			<=	0;
		web			<=	0;
		addra		<=	0;
		addrb		<=	0;




		east		<=	0;
		west		<=	0;
		south		<=	0;
		north		<=	0;
		east_mode	<=	0;
		west_mode	<=	0;
		south_mode	<=	0;
		north_mode	<=	0;


		rs1_ptr 	<= rs1_base;
		rs2_ptr 	<= rs2_base;
		rd_ptr 		<= rd_base;
		rd_up_ptr 	<= rd_base;
		q_ptr		<= rs2_base;
		shift_ptr	<= rd_base;
		ram_ptr		<=	0;

		count		<=	0;
		iter		<=	0;
		offset		<= 	0;

		start_flag	<= 	1;
		finish_flag	<=	0;

		case(opcode)
			0:	begin

				alu_op		<=	0;

				state		<=	OP;
				end
			1:	begin

				alu_op		<=	1;

				state		<=	OP;
				end
			2:	begin

				alu_op		<=	2;

				state		<=	Q;
				end
			5,6,7,8: 	begin

				alu_op		<=	'hf;

				state		<=	OP;
				end			
			9:	begin

				alu_op		<=	9;

				state		<=	OP;
				end
			10:	begin

				alu_op		<=	10;

				state		<=	OP;
				end
		endcase	
	end
	
	else if(start_flag&&!finish_flag) begin
		count <= count + 1;
		case(opcode)
		0,1:	begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr + 1;
					rs2_ptr 	<= rs2_ptr + 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr + 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end
		2:	begin
				
				if(iter<=LENGTH) begin
				case(state)
				Q: begin

					rs1_ptr 	<= rs1_base;
					rs2_ptr 	<= rs2_base;
					q_ptr 		<= q_ptr + 1;

					addrb 		<= q_ptr;
					wea 		<= 0;

					iter 		<= iter + 1;
					offset		<= offset + 1;

					state 		<= OP;
					if(iter<LENGTH/2) begin				
					rd_ptr		<= rd_ptr + offset;
					rd_up_ptr	<= rd_up_ptr + offset;
					end
					else if(iter==LENGTH/2) begin
					rd_ptr		<= rd_ptr + offset-LENGTH/2;
					rd_up_ptr	<= rd_up_ptr + offset;
					end
					else if(iter>LENGTH/2) begin
					rd_ptr		<= rd_ptr + offset - LENGTH/2;
					rd_up_ptr	<= rd_up_ptr + offset - LENGTH/2;
					end
				end
				OP: begin
					

					rd_up_ptr	<= rd_up_ptr + 1;
					rd_ptr 		<= rd_ptr + 1;
					rs1_ptr		<= rs1_ptr + 1;
					


					if(iter==1 && count<(2*LENGTH)+1) begin
						addra <= 0;
						addrb <= rs1_ptr;
					end

					else if(count==(2*LENGTH)+1) begin
						addra 	<= rd_ptr - 1;
						addrb 	<= 0;
					end

					else begin
						addra  	<= rd_up_ptr;
						addrb 	<= rs1_ptr;
					end
					wea 	<= 0;

					state 		<= WB;			
				end

				WB: begin
				
					if(count<(2*LENGTH)+2) begin
						addra 		<= rd_ptr-1;
						wea 		<= 1;

						state 		<= OP;
					end 

					else if(iter<LENGTH+1) begin
						rd_ptr		<= rd_base;
						rd_up_ptr	<= rd_base;

						addra		<= rd_ptr-1;
						addrb		<= 0;
						wea			<= 1;

						count 		<= 0;

						state 		<= SHIFT;
						
					end

					else begin
						wea 		<= 0;

						state 		<= Q;
					end
					
				
				end
				SHIFT: begin

					
					rd_ptr		<= rd_base;
					rd_up_ptr	<= rd_base;
					
					addra		<= 0;
					addrb 		<= 0;
					wea			<= 0;
					
					count 		<= 0;
					
					state 		<= Q;
				end
				endcase
				end
				else finish_flag <= 1;
				
			end
		5: 	begin
				east	<= 1;
				east_mode	<=	1; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	0;

				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					east_mode	<=	0; 
					north_mode	<=	2;
				end
				if(count==LENGTH+1) begin
					finish_flag <=  1;
					east_mode	<=	0; 
					north_mode	<=	0;
					wea 		<= 0;
					web			<= 0;
				end
			end
	
		7: 	begin
				south	<= 1;
				east_mode	<=	0; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	0;
				
				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					finish_flag <=  1;
				end
			end
		8: 	begin
				north	<= 1;
				east_mode	<=	0; 
				west_mode	<=	0;
				south_mode	<=	0;
				north_mode	<=	1;

				case(state)
				OP: begin
					rs1_ptr		<= rs1_ptr + 2;

					addra 		<= rs1_ptr;
					addrb 		<= rs1_ptr+1;
					wea 		<= 0;
					web			<= 0;

					state 		<= WB;
				end

				WB: begin
					rd_ptr		<= rd_ptr + 2;

					addra		<= rd_ptr;
					addrb		<= rd_ptr+1;
					if(count<=LENGTH) begin
						wea 		<= 1;
						web			<= 1;
					end

					state 		<= OP;
				end
				endcase
				if(count==LENGTH) begin
					north_mode	<=	2;
				end
				if(count==LENGTH+1) begin
					north_mode	<=	0;
					finish_flag <=  1;
				end
			end
		9:
			begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr - 1;
					rs2_ptr 	<= rs2_ptr - 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr - 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end		
		10:
			begin
				case(state)
				OP: begin

					rs1_ptr		<= rs1_ptr - 1;
					rs2_ptr 	<= rs2_ptr - 1;

					addra 		<= rs1_ptr;
					addrb 		<= rs2_ptr;
					wea 		<= 0;

					state 		<= WB;
				end

				WB: begin

					rd_ptr 		<= rd_ptr - 1;

					addra 		<= rd_ptr;
					wea 		<= 1;

					state 		<= OP;
				end
				endcase

				if(count==2*LENGTH) begin
					start_flag	<= 0;
					finish_flag <= 1;
				end
			end
		endcase
		end
end
endmodule