data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:123: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/typedef.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/typedef.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/typedef.svh.sv\n             axi/typedef.svh\n             axi/typedef.svh.v\n             axi/typedef.svh.sv\n             obj_dir/axi/typedef.svh\n             obj_dir/axi/typedef.svh.v\n             obj_dir/axi/typedef.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:124: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:150: Define or directive not defined: \'`AXI_TYPEDEF_AW_CHAN_T\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:150: syntax error, unexpected \'(\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:151: Define or directive not defined: \'`AXI_TYPEDEF_W_CHAN_T\'\n  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:152: Define or directive not defined: \'`AXI_TYPEDEF_B_CHAN_T\'\n  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:153: Define or directive not defined: \'`AXI_TYPEDEF_AR_CHAN_T\'\n  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:154: Define or directive not defined: \'`AXI_TYPEDEF_R_CHAN_T\'\n  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:155: Define or directive not defined: \'`AXI_TYPEDEF_REQ_T\'\n  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:156: Define or directive not defined: \'`AXI_TYPEDEF_RESP_T\'\n  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:161: Define or directive not defined: \'`AXI_ASSIGN_TO_REQ\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:161: syntax error, unexpected \'(\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n                     ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:162: Define or directive not defined: \'`AXI_ASSIGN_FROM_RESP\'\n  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:164: Define or directive not defined: \'`AXI_ASSIGN_FROM_REQ\'\n  `AXI_ASSIGN_FROM_REQ(mst, mst_req)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_delayer.sv:165: Define or directive not defined: \'`AXI_ASSIGN_TO_RESP\'\n  `AXI_ASSIGN_TO_RESP(mst_resp, mst)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module axi_delayer #(

  parameter type aw_chan_t = logic,
  parameter type  w_chan_t = logic,
  parameter type  b_chan_t = logic,
  parameter type ar_chan_t = logic,
  parameter type  r_chan_t = logic,

  parameter type     req_t = logic,
  parameter type    resp_t = logic,

  parameter bit          StallRandomInput  = 0,
  parameter bit          StallRandomOutput = 0,
  parameter int unsigned FixedDelayInput   = 1,
  parameter int unsigned FixedDelayOutput  = 1
) (
  input  logic  clk_i,
  input  logic  rst_ni,

  input  req_t  slv_req_i,
  output resp_t slv_resp_o,

  output req_t  mst_req_o,
  input  resp_t mst_resp_i
);

  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( aw_chan_t        )
  ) i_stream_delay_aw (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.aw        ),
    .ready_o   ( slv_resp_o.aw_ready ),
    .valid_i   ( slv_req_i.aw_valid  ),
    .payload_o ( mst_req_o.aw        ),
    .ready_i   ( mst_resp_i.aw_ready ),
    .valid_o   ( mst_req_o.aw_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( ar_chan_t        )
  ) i_stream_delay_ar (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.ar        ),
    .ready_o   ( slv_resp_o.ar_ready ),
    .valid_i   ( slv_req_i.ar_valid  ),
    .payload_o ( mst_req_o.ar        ),
    .ready_i   ( mst_resp_i.ar_ready ),
    .valid_o   ( mst_req_o.ar_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( w_chan_t         )
  ) i_stream_delay_w (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.w        ),
    .ready_o   ( slv_resp_o.w_ready ),
    .valid_i   ( slv_req_i.w_valid  ),
    .payload_o ( mst_req_o.w        ),
    .ready_i   ( mst_resp_i.w_ready ),
    .valid_o   ( mst_req_o.w_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomOutput ),
    .FixedDelay  ( FixedDelayOutput  ),
    .payload_t   ( b_chan_t          )
  ) i_stream_delay_b (
    .clk_i,
    .rst_ni,
    .payload_i ( mst_resp_i.b       ),
    .ready_o   ( mst_req_o.b_ready  ),
    .valid_i   ( mst_resp_i.b_valid ),
    .payload_o ( slv_resp_o.b       ),
    .ready_i   ( slv_req_i.b_ready  ),
    .valid_o   ( slv_resp_o.b_valid )
  );


   stream_delay #(
    .StallRandom ( StallRandomOutput ),
    .FixedDelay  ( FixedDelayOutput  ),
    .payload_t   ( r_chan_t          )
  ) i_stream_delay_r (
    .clk_i,
    .rst_ni,
    .payload_i ( mst_resp_i.r       ),
    .ready_o   ( mst_req_o.r_ready  ),
    .valid_i   ( mst_resp_i.r_valid ),
    .payload_o ( slv_resp_o.r       ),
    .ready_i   ( slv_req_i.r_ready  ),
    .valid_o   ( slv_resp_o.r_valid )
  );
endmodule
module axi_delayer #(

  parameter type aw_chan_t = logic,
  parameter type  w_chan_t = logic,
  parameter type  b_chan_t = logic,
  parameter type ar_chan_t = logic,
  parameter type  r_chan_t = logic,

  parameter type     req_t = logic,
  parameter type    resp_t = logic,

  parameter bit          StallRandomInput  = 0,
  parameter bit          StallRandomOutput = 0,
  parameter int unsigned FixedDelayInput   = 1,
  parameter int unsigned FixedDelayOutput  = 1
) (
  input  logic  clk_i,
  input  logic  rst_ni,

  input  req_t  slv_req_i,
  output resp_t slv_resp_o,

  output req_t  mst_req_o,
  input  resp_t mst_resp_i
);


  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( aw_chan_t        )
  ) i_stream_delay_aw (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.aw        ),
    .ready_o   ( slv_resp_o.aw_ready ),
    .valid_i   ( slv_req_i.aw_valid  ),
    .payload_o ( mst_req_o.aw        ),
    .ready_i   ( mst_resp_i.aw_ready ),
    .valid_o   ( mst_req_o.aw_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( ar_chan_t        )
  ) i_stream_delay_ar (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.ar        ),
    .ready_o   ( slv_resp_o.ar_ready ),
    .valid_i   ( slv_req_i.ar_valid  ),
    .payload_o ( mst_req_o.ar        ),
    .ready_i   ( mst_resp_i.ar_ready ),
    .valid_o   ( mst_req_o.ar_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomInput ),
    .FixedDelay  ( FixedDelayInput  ),
    .payload_t   ( w_chan_t         )
  ) i_stream_delay_w (
    .clk_i,
    .rst_ni,
    .payload_i ( slv_req_i.w        ),
    .ready_o   ( slv_resp_o.w_ready ),
    .valid_i   ( slv_req_i.w_valid  ),
    .payload_o ( mst_req_o.w        ),
    .ready_i   ( mst_resp_i.w_ready ),
    .valid_o   ( mst_req_o.w_valid  )
  );


  stream_delay #(
    .StallRandom ( StallRandomOutput ),
    .FixedDelay  ( FixedDelayOutput  ),
    .payload_t   ( b_chan_t          )
  ) i_stream_delay_b (
    .clk_i,
    .rst_ni,
    .payload_i ( mst_resp_i.b       ),
    .ready_o   ( mst_req_o.b_ready  ),
    .valid_i   ( mst_resp_i.b_valid ),
    .payload_o ( slv_resp_o.b       ),
    .ready_i   ( slv_req_i.b_ready  ),
    .valid_o   ( slv_resp_o.b_valid )
  );


   stream_delay #(
    .StallRandom ( StallRandomOutput ),
    .FixedDelay  ( FixedDelayOutput  ),
    .payload_t   ( r_chan_t          )
  ) i_stream_delay_r (
    .clk_i,
    .rst_ni,
    .payload_i ( mst_resp_i.r       ),
    .ready_o   ( mst_req_o.r_ready  ),
    .valid_i   ( mst_resp_i.r_valid ),
    .payload_o ( slv_resp_o.r       ),
    .ready_i   ( slv_req_i.r_ready  ),
    .valid_o   ( slv_resp_o.r_valid )
  );
endmodule