data/full_repos/permissive/426864978/lab2/task2/fillscreen.sv
data/verilator_xmls/3a973978-031f-448c-9ccd-624ab6e7b3da.xml
module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour,
                  input logic start, output logic done,
                  output logic [7:0] vga_x, output logic [6:0] vga_y,
                  output logic [2:0] vga_colour, output logic vga_plot);


     `define WAIT 2'b00
     `define FILL 2'b01
     `define DONE 2'b10


     

     reg [7:0] current_x;
     reg [6:0] current_y;
     reg [1:0] state, out;


     assign { done, vga_plot } = out;
     assign vga_x = current_x;
     assign vga_y = current_y;
     assign vga_colour = current_x[2:0];

     always @(posedge clk or negedge rst_n) begin
          if (!rst_n) begin
               state <= `WAIT;
               current_x <= 8'b0;
               current_y <= 7'b0;
               out <= 2'b0;
          end 
          else begin
               case ({ state, start })
                    {`WAIT, 1'b1}: state <= `FILL;
                    {`FILL, 1'b1}:
                         if (current_y !== 7'd119)
                              current_y++;
                         else begin
                              if (current_x == 8'd159 && current_y == 7'd119)
                                   state <= `DONE;
                              else begin
                                   current_x++;
                                   current_y <= 7'b0;
                              end  
                         end
                    {`DONE, 1'b1}: begin
                         current_x <= 8'b0;
                         current_y <= 7'b0;
                    end
                    default: begin
                         state <= `WAIT;
                         current_x <= 8'b0;
                         current_y <= 7'b0;
                    end
               endcase

               case ({ state, start })
                    {`WAIT, 1'b1}: out <= 2'b01;
                    {`FILL, 1'b1}: out <= 2'b01;
                    {`DONE, 1'b1}: out <= 2'b10;
                    default: out <= 2'b0;
               endcase
          end
     end

endmodule
module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour,
                  input logic start, output logic done,
                  output logic [7:0] vga_x, output logic [6:0] vga_y,
                  output logic [2:0] vga_colour, output logic vga_plot);



     `define WAIT 2'b00
     `define FILL 2'b01
     `define DONE 2'b10


     

     reg [7:0] current_x;
     reg [6:0] current_y;
     reg [1:0] state, out;


     assign { done, vga_plot } = out;
     assign vga_x = current_x;
     assign vga_y = current_y;
     assign vga_colour = current_x[2:0];

     always @(posedge clk or negedge rst_n) begin
          if (!rst_n) begin
               state <= `WAIT;
               current_x <= 8'b0;
               current_y <= 7'b0;
               out <= 2'b0;
          end 
          else begin
               case ({ state, start })
                    {`WAIT, 1'b1}: state <= `FILL;
                    {`FILL, 1'b1}:
                         if (current_y !== 7'd119)
                              current_y++;
                         else begin
                              if (current_x == 8'd159 && current_y == 7'd119)
                                   state <= `DONE;
                              else begin
                                   current_x++;
                                   current_y <= 7'b0;
                              end  
                         end
                    {`DONE, 1'b1}: begin
                         current_x <= 8'b0;
                         current_y <= 7'b0;
                    end
                    default: begin
                         state <= `WAIT;
                         current_x <= 8'b0;
                         current_y <= 7'b0;
                    end
               endcase

               case ({ state, start })
                    {`WAIT, 1'b1}: out <= 2'b01;
                    {`FILL, 1'b1}: out <= 2'b01;
                    {`DONE, 1'b1}: out <= 2'b10;
                    default: out <= 2'b0;
               endcase
          end
     end

endmodule