data/full_repos/permissive/471089853/src/leftshifter12_by_max_31_f400_uid38.v
data/verilator_xmls/6a5f5fd9-7131-4d27-a570-2170d1398aeb.xml
module LeftShifter12_by_max_31_F400_uid38(clk, X, S, padBit, R);
  reg [4:0] _0_;
  reg [12:0] _1_;
  reg _2_;
  wire [12:0] _3_;
  wire [14:0] _4_;
  wire [18:0] _5_;
  wire [26:0] _6_;
  wire [42:0] _7_;
  output [42:0] R;
  input [4:0] S;
  input [11:0] X;
  input clk;
  wire [11:0] level0;
  wire [12:0] level1;
  wire [12:0] level1_d1;
  wire [14:0] level2;
  wire [18:0] level3;
  wire [26:0] level4;
  wire [42:0] level5;
  input padBit;
  wire padbit_d1;
  wire [4:0] ps;
  wire [4:0] ps_d1;
  always @(posedge clk)
    _2_ <= padBit;
  assign _3_ = ps[0] ? { level0, 1'h0 } : { padBit, level0 };
  assign _4_ = ps_d1[1] ? { level1_d1, 2'h0 } : { padbit_d1, padbit_d1, level1_d1 };
  assign _5_ = ps_d1[2] ? { level2, 4'h0 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, level2 };
  assign _6_ = ps_d1[3] ? { level3, 8'h00 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, level3 };
  assign _7_ = ps_d1[4] ? { level4, 16'h0000 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, level4 };
  always @(posedge clk)
    _0_ <= ps;
  always @(posedge clk)
    _1_ <= level1;
  assign ps = S;
  assign ps_d1 = _0_;
  assign level0 = X;
  assign level1 = _3_;
  assign level1_d1 = _1_;
  assign level2 = _4_;
  assign level3 = _5_;
  assign level4 = _6_;
  assign level5 = _7_;
  assign padbit_d1 = _2_;
  assign R = level5;
endmodule
module LeftShifter12_by_max_31_F400_uid38(clk, X, S, padBit, R);

  reg [4:0] _0_;
  reg [12:0] _1_;
  reg _2_;
  wire [12:0] _3_;
  wire [14:0] _4_;
  wire [18:0] _5_;
  wire [26:0] _6_;
  wire [42:0] _7_;
  output [42:0] R;
  input [4:0] S;
  input [11:0] X;
  input clk;
  wire [11:0] level0;
  wire [12:0] level1;
  wire [12:0] level1_d1;
  wire [14:0] level2;
  wire [18:0] level3;
  wire [26:0] level4;
  wire [42:0] level5;
  input padBit;
  wire padbit_d1;
  wire [4:0] ps;
  wire [4:0] ps_d1;
  always @(posedge clk)
    _2_ <= padBit;
  assign _3_ = ps[0] ? { level0, 1'h0 } : { padBit, level0 };
  assign _4_ = ps_d1[1] ? { level1_d1, 2'h0 } : { padbit_d1, padbit_d1, level1_d1 };
  assign _5_ = ps_d1[2] ? { level2, 4'h0 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, level2 };
  assign _6_ = ps_d1[3] ? { level3, 8'h00 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, level3 };
  assign _7_ = ps_d1[4] ? { level4, 16'h0000 } : { padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, padbit_d1, level4 };
  always @(posedge clk)
    _0_ <= ps;
  always @(posedge clk)
    _1_ <= level1;
  assign ps = S;
  assign ps_d1 = _0_;
  assign level0 = X;
  assign level1 = _3_;
  assign level1_d1 = _1_;
  assign level2 = _4_;
  assign level3 = _5_;
  assign level4 = _6_;
  assign level5 = _7_;
  assign padbit_d1 = _2_;
  assign R = level5;
endmodule