data/full_repos/permissive/51997848/sigma_delta_dac.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51997848/sigma_delta_dac.v:19: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s REPLICATE generates 2 bits.\n                                                                        : ... In instance sigma_delta_dac\nalways @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);\n                                                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51997848/sigma_delta_dac.v:20: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'DACin\' generates 8 bits.\n                                                                        : ... In instance sigma_delta_dac\nalways @(*) DeltaAdder = DACin + DeltaB;\n                               ^\n%Error: Exiting due to 2 warning(s)\n'
module sigma_delta_dac #(parameter MSBI=7)
(
   output reg      DACout,
   input  [MSBI:0] DACin,
   input           CLK,
   input           RESET
);

reg [MSBI+2:0] DeltaAdder;
reg [MSBI+2:0] SigmaAdder;
reg [MSBI+2:0] SigmaLatch;
reg [MSBI+2:0] DeltaB;

always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;

always @(posedge CLK or posedge RESET) begin
   if(RESET) begin
      SigmaLatch <= 1'b1 << (MSBI+1);
      DACout <= 1'b0;
   end else begin
      SigmaLatch <= SigmaAdder;
      DACout <= SigmaLatch[MSBI+2];
   end
end

endmodule
module sigma_delta_dac #(parameter MSBI=7)
(
   output reg      DACout,
   input  [MSBI:0] DACin,
   input           CLK,
   input           RESET
);


reg [MSBI+2:0] DeltaAdder;
reg [MSBI+2:0] SigmaAdder;
reg [MSBI+2:0] SigmaLatch;
reg [MSBI+2:0] DeltaB;

always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;

always @(posedge CLK or posedge RESET) begin
   if(RESET) begin
      SigmaLatch <= 1'b1 << (MSBI+1);
      DACout <= 1'b0;
   end else begin
      SigmaLatch <= SigmaAdder;
      DACout <= SigmaLatch[MSBI+2];
   end
end

endmodule