data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n always #1 clock=~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n always #6 LineEnd=~LineEnd;\n        ^\n%Error: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:23: Unsupported: fork statements\n initial fork\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 reset=1;  #12 reset=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 reset=1;  #12 reset=0; \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Pong/Phase2/vsyncModule2015fall_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #300 $stop;\n   ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vsyncModule2015fall_tb;

	reg LineEnd;
	reg [9:0] SynchPulse, FrontPorch, ActiveVideo, BackPorch;
	reg reset, clock;

	wire vsync;
	wire [9:0] yposition;

	vsyncModule uut (LineEnd, SynchPulse, FrontPorch, ActiveVideo, BackPorch, vsync, yposition, reset, clock);
	
	initial begin
		SynchPulse = 2;  BackPorch = 3;  ActiveVideo = 5;
		FrontPorch = 2;   reset = 0; clock = 0;    LineEnd=0; end
	always #1 clock=~clock;
	always #6 LineEnd=~LineEnd;
	initial fork
	#0 reset=1; 	#12 reset=0; 

   #300 $stop;
	join
endmodule
module vsyncModule2015fall_tb;


	reg LineEnd;
	reg [9:0] SynchPulse, FrontPorch, ActiveVideo, BackPorch;
	reg reset, clock;

	wire vsync;
	wire [9:0] yposition;

	vsyncModule uut (LineEnd, SynchPulse, FrontPorch, ActiveVideo, BackPorch, vsync, yposition, reset, clock);
	
	initial begin
		SynchPulse = 2;  BackPorch = 3;  ActiveVideo = 5;
		FrontPorch = 2;   reset = 0; clock = 0;    LineEnd=0; end
	always #1 clock=~clock;
	always #6 LineEnd=~LineEnd;
	initial fork
	#0 reset=1; 	#12 reset=0; 

   #300 $stop;
	join
endmodule