data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/cluster_clock_inverter.sv
data/verilator_xmls/5e9c73bc-467b-41e6-9b18-cad1bd65fba8.xml
module cluster_clock_inverter
  (
   input  logic clk_i,
   output logic clk_o
   );
   
   assign clk_o = ~clk_i;
   
endmodule
module cluster_clock_inverter
  (
   input  logic clk_i,
   output logic clk_o
   );

   
   assign clk_o = ~clk_i;
   
endmodule