data/full_repos/permissive/490299936/verilog/adxl345_top.v
1: b"%Error: data/full_repos/permissive/490299936/verilog/adxl345_top.v:43: Cannot find file containing module: 'adxl345_controller'\nadxl345_controller axdxl345_controller_i(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490299936/verilog,data/full_repos/permissive/490299936/adxl345_controller\n             data/full_repos/permissive/490299936/verilog,data/full_repos/permissive/490299936/adxl345_controller.v\n             data/full_repos/permissive/490299936/verilog,data/full_repos/permissive/490299936/adxl345_controller.sv\n             adxl345_controller\n             adxl345_controller.v\n             adxl345_controller.sv\n             obj_dir/adxl345_controller\n             obj_dir/adxl345_controller.v\n             obj_dir/adxl345_controller.sv\n%Error: data/full_repos/permissive/490299936/verilog/adxl345_top.v:60: Cannot find file containing module: 'iic_controller'\niic_controller iic_controller_i(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module adxl345_top(
	input clk,
	input rst_n,
	output adxl345_iic_scl,
	inout adxl345_iic_sda,
	output[12:0] x_axis,
	output[12:0] y_axis,
	output[12:0] z_axis
    );


wire iicwr_req;
wire iicrd_req;

wire [7:0] iic_addr;

wire [7:0] iic_wrdb;

wire [7:0] iic_rddb;

wire iic_ack;

adxl345_controller axdxl345_controller_i(

	.clk(clk),
	.rst_n(rst_n),
	.iic_rddb(iic_rddb),
	.iic_ack(iic_ack),

	.iicwr_req(iicwr_req),
	.iicrd_req(iicrd_req),
	.iic_addr(iic_addr),
	.iic_wrdb(iic_wrdb),

	.x_axis(x_axis),
	.y_axis(y_axis),
	.z_axis(z_axis)
);

iic_controller iic_controller_i(

	.clk(clk),
	.rst_n(rst_n),

	.iicwr_req(iicwr_req),
	.iicrd_req(iicrd_req),

	.iic_addr(iic_addr),
	.iic_wrdb(iic_wrdb),
	.iic_rddb(iic_rddb),
	.iic_ack(iic_ack),

	.scl(adxl345_iic_scl),
	.sda(adxl345_iic_sda)
);

endmodule
module adxl345_top(
	input clk,
	input rst_n,
	output adxl345_iic_scl,
	inout adxl345_iic_sda,
	output[12:0] x_axis,
	output[12:0] y_axis,
	output[12:0] z_axis
    );



wire iicwr_req;
wire iicrd_req;

wire [7:0] iic_addr;

wire [7:0] iic_wrdb;

wire [7:0] iic_rddb;

wire iic_ack;

adxl345_controller axdxl345_controller_i(

	.clk(clk),
	.rst_n(rst_n),
	.iic_rddb(iic_rddb),
	.iic_ack(iic_ack),

	.iicwr_req(iicwr_req),
	.iicrd_req(iicrd_req),
	.iic_addr(iic_addr),
	.iic_wrdb(iic_wrdb),

	.x_axis(x_axis),
	.y_axis(y_axis),
	.z_axis(z_axis)
);

iic_controller iic_controller_i(

	.clk(clk),
	.rst_n(rst_n),

	.iicwr_req(iicwr_req),
	.iicrd_req(iicrd_req),

	.iic_addr(iic_addr),
	.iic_wrdb(iic_wrdb),
	.iic_rddb(iic_rddb),
	.iic_ack(iic_ack),

	.scl(adxl345_iic_scl),
	.sda(adxl345_iic_sda)
);

endmodule