data/full_repos/permissive/514939538/Controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:40: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                    : ... In instance Controller\n            current_floor=4\'d0;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:41: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                    : ... In instance Controller\n            wait_floor=4\'d1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:42: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                    : ... In instance Controller\n            door = 1\'d1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:43: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n            Up=1\'d0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:44: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n            Down=1\'d0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:53: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    door=1\'d0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:54: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                    : ... In instance Controller\n                    wait_floor=4\'d0;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:55: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Up=1\'d0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:56: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Down=1\'d1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:61: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    door=1\'d0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:62: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                    : ... In instance Controller\n                    wait_floor=4\'d0;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:63: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Up=1\'d1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:64: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Down=1\'d0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:69: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    door=1\'d1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:70: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                    : ... In instance Controller\n                    wait_floor=4\'d1;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:71: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Up=1\'d0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:72: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance Controller\n                    Down=1\'d0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/514939538/Controller.v:48: Operator LT expects 5 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                    : ... In instance Controller\n            if(requested_floor < 4\'d15)\n                               ^\n%Error: Exiting due to 18 warning(s)\n'
module Controller(clk,reset,requested_floor,wait_floor,door,Up,Down,y);

input clk,reset;
input [4:0] requested_floor;

output reg[1:0] door;
output reg[1:0] Up;
output reg[1:0] Down;
output reg[1:0] wait_floor;
output [4:0] y;

reg [4:0] current_floor ;

always @ (posedge clk)
    begin
        if(reset)
        begin
            current_floor=4'd0;
            wait_floor=4'd1;
            door = 1'd1;
            Up=1'd0;
            Down=1'd0;
        end
        else
        begin
            if(requested_floor < 4'd15)
            begin
                if(requested_floor < current_floor)
                begin
                    current_floor=current_floor-1;
                    door=1'd0;
                    wait_floor=4'd0;
                    Up=1'd0;
                    Down=1'd1;
                end
                else if (requested_floor > current_floor)
                begin
                    current_floor = current_floor+1;
                    door=1'd0;
                    wait_floor=4'd0;
                    Up=1'd1;
                    Down=1'd0;
                end
                else if(requested_floor == current_floor)
                begin
                    current_floor = requested_floor;
                    door=1'd1;
                    wait_floor=4'd1;
                    Up=1'd0;
                    Down=1'd0;
                end
            end
        end
    end
    
assign y = current_floor;

endmodule
module Controller(clk,reset,requested_floor,wait_floor,door,Up,Down,y);


input clk,reset;
input [4:0] requested_floor;

output reg[1:0] door;
output reg[1:0] Up;
output reg[1:0] Down;
output reg[1:0] wait_floor;
output [4:0] y;

reg [4:0] current_floor ;

always @ (posedge clk)
    begin
        if(reset)
        begin
            current_floor=4'd0;
            wait_floor=4'd1;
            door = 1'd1;
            Up=1'd0;
            Down=1'd0;
        end
        else
        begin
            if(requested_floor < 4'd15)
            begin
                if(requested_floor < current_floor)
                begin
                    current_floor=current_floor-1;
                    door=1'd0;
                    wait_floor=4'd0;
                    Up=1'd0;
                    Down=1'd1;
                end
                else if (requested_floor > current_floor)
                begin
                    current_floor = current_floor+1;
                    door=1'd0;
                    wait_floor=4'd0;
                    Up=1'd1;
                    Down=1'd0;
                end
                else if(requested_floor == current_floor)
                begin
                    current_floor = requested_floor;
                    door=1'd1;
                    wait_floor=4'd1;
                    Up=1'd0;
                    Down=1'd0;
                end
            end
        end
    end
    
assign y = current_floor;

endmodule