data/full_repos/permissive/479997390/src/Control.v
1: b'%Error: data/full_repos/permissive/479997390/src/Control.v:1: Cannot find include file: CtrlDef.v\n`include "CtrlDef.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.sv\n             CtrlDef.v\n             CtrlDef.v.v\n             CtrlDef.v.sv\n             obj_dir/CtrlDef.v\n             obj_dir/CtrlDef.v.v\n             obj_dir/CtrlDef.v.sv\n%Error: data/full_repos/permissive/479997390/src/Control.v:2: Cannot find include file: InstrDef.v\n`include "InstrDef.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:14: Define or directive not defined: \'`INSTR_RTYPE_OP\'\n  assign PCDist = (OpCode == `INSTR_RTYPE_OP && Funct == `INSTR_JR_FUNCT);\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:14: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n  assign PCDist = (OpCode == `INSTR_RTYPE_OP && Funct == `INSTR_JR_FUNCT);\n                                             ^~\n%Error: data/full_repos/permissive/479997390/src/Control.v:14: Define or directive not defined: \'`INSTR_JR_FUNCT\'\n  assign PCDist = (OpCode == `INSTR_RTYPE_OP && Funct == `INSTR_JR_FUNCT);\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:15: Define or directive not defined: \'`INSTR_BEQ_OP\'\n  assign BranchEql = (OpCode == `INSTR_BEQ_OP ? 1 : 0);\n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:15: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n  assign BranchEql = (OpCode == `INSTR_BEQ_OP ? 1 : 0);\n                                              ^\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: Define or directive not defined: \'`INSTR_LUI_OP\'\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                                          ^\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: Define or directive not defined: \'`EXT_HIGHPOS\'\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: Define or directive not defined: \'`INSTR_ORI_OP\'\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                                                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: Define or directive not defined: \'`EXT_ZERO\'\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:16: Define or directive not defined: \'`EXT_SIGNED\'\n  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));\n                                                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`INSTR_J_OP\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                          ^~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`INSTR_JAL_OP\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`NPC_JUMP\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`INSTR_BEQ_OP\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`INSTR_BNE_OP\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`NPC_BRANCH\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`NPC_JR\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                                                                                                                 ^~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:17: Define or directive not defined: \'`NPC_PLUS4\'\n  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));\n                                                                                                                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:21: Define or directive not defined: \'`INSTR_RTYPE_OP\'\n      `INSTR_RTYPE_OP: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:21: syntax error, unexpected \':\', expecting endcase\n      `INSTR_RTYPE_OP: begin\n                     ^\n%Error: data/full_repos/permissive/479997390/src/Control.v:28: Define or directive not defined: \'`INSTR_JR_FUNCT\'\n        if (Funct == `INSTR_JR_FUNCT) begin\n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (Funct == `INSTR_JR_FUNCT) begin\n                                    ^\n%Error: data/full_repos/permissive/479997390/src/Control.v:29: Define or directive not defined: \'`ALUOp_NULL\'\n          ALUOp = `ALUOp_NULL;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:31: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:32: Define or directive not defined: \'`ALUOp_RTYPE\'\n          ALUOp = `ALUOp_RTYPE;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:36: Define or directive not defined: \'`INSTR_LW_OP\'\n      `INSTR_LW_OP: begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:37: Define or directive not defined: \'`ALUOp_ADD\'\n        ALUOp = `ALUOp_ADD;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:46: Define or directive not defined: \'`INSTR_SW_OP\'\n      `INSTR_SW_OP: begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:47: Define or directive not defined: \'`ALUOp_ADD\'\n        ALUOp = `ALUOp_ADD;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:56: Define or directive not defined: \'`INSTR_ADDI_OP\'\n      `INSTR_ADDI_OP: begin\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:57: Define or directive not defined: \'`ALUOp_ADD\'\n        ALUOp = `ALUOp_ADD;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:66: Define or directive not defined: \'`INSTR_ORI_OP\'\n      `INSTR_ORI_OP: begin\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:67: Define or directive not defined: \'`ALUOp_OR\'\n        ALUOp = `ALUOp_OR;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:76: Define or directive not defined: \'`INSTR_LUI_OP\'\n      `INSTR_LUI_OP: begin  \n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:77: Define or directive not defined: \'`ALUOp_LUI\'\n        ALUOp = `ALUOp_LUI;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:86: Define or directive not defined: \'`INSTR_SLTI_OP\'\n      `INSTR_SLTI_OP: begin\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:87: Define or directive not defined: \'`ALUOp_SLT\'\n        ALUOp = `ALUOp_SLT;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:96: Define or directive not defined: \'`INSTR_BEQ_OP\'\n      `INSTR_BEQ_OP: begin\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:97: Define or directive not defined: \'`ALUOp_BEQ\'\n        ALUOp = `ALUOp_BEQ;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:106: Define or directive not defined: \'`INSTR_BNE_OP\'\n      `INSTR_BNE_OP: begin\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:107: Define or directive not defined: \'`ALUOp_BNE\'\n        ALUOp = `ALUOp_BNE;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:116: Define or directive not defined: \'`INSTR_J_OP\'\n      `INSTR_J_OP: begin\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:117: Define or directive not defined: \'`ALUOp_NULL\'\n        ALUOp = `ALUOp_NULL;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:126: Define or directive not defined: \'`INSTR_JAL_OP\'\n      `INSTR_JAL_OP: begin\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:127: Define or directive not defined: \'`ALUOp_JAL\'\n        ALUOp = `ALUOp_JAL;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Control.v:137: Define or directive not defined: \'`ALUOp_NULL\'\n        ALUOp = `ALUOp_NULL;\n                ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Control (
  OpCode, Funct, PCDist, NPCCtrl, BranchEql, MemRead, MemToReg, MemWrite, RegDist, RegWrite, ALUSrc, RegDistDist, ExtOp, ALUOp
);

  input [5:0] OpCode, Funct;
  output PCDist, BranchEql;
  output reg MemRead, MemToReg, MemWrite, RegDist, RegWrite, ALUSrc, RegDistDist;
  output [1:0] ExtOp, NPCCtrl;
  output reg [4:0] ALUOp;

  assign PCDist = (OpCode == `INSTR_RTYPE_OP && Funct == `INSTR_JR_FUNCT);
  assign BranchEql = (OpCode == `INSTR_BEQ_OP ? 1 : 0);
  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));
  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));

  always @(OpCode or Funct) begin
    case (OpCode)
      `INSTR_RTYPE_OP: begin
        RegDist = 1'b1;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
        if (Funct == `INSTR_JR_FUNCT) begin
          ALUOp = `ALUOp_NULL;
          RegWrite = 1'b0;
        end else begin
          ALUOp = `ALUOp_RTYPE;
          RegWrite = 1'b1;
        end
      end
      `INSTR_LW_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b1;
        MemWrite = 1'b0;
        MemToReg = 1'b1;
        RegDistDist = 1'b0;
      end
      `INSTR_SW_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b1;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_ADDI_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_ORI_OP: begin
        ALUOp = `ALUOp_OR;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_LUI_OP: begin
        ALUOp = `ALUOp_LUI;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_SLTI_OP: begin
        ALUOp = `ALUOp_SLT;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_BEQ_OP: begin
        ALUOp = `ALUOp_BEQ;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_BNE_OP: begin
        ALUOp = `ALUOp_BNE;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_J_OP: begin
        ALUOp = `ALUOp_NULL;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_JAL_OP: begin
        ALUOp = `ALUOp_JAL;
        RegDist = 1'b1;
        RegWrite = 1'b1;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b1;
      end
      default: begin
        ALUOp = `ALUOp_NULL;
      end
    endcase
  end
endmodule
module Control (
  OpCode, Funct, PCDist, NPCCtrl, BranchEql, MemRead, MemToReg, MemWrite, RegDist, RegWrite, ALUSrc, RegDistDist, ExtOp, ALUOp
);


  input [5:0] OpCode, Funct;
  output PCDist, BranchEql;
  output reg MemRead, MemToReg, MemWrite, RegDist, RegWrite, ALUSrc, RegDistDist;
  output [1:0] ExtOp, NPCCtrl;
  output reg [4:0] ALUOp;

  assign PCDist = (OpCode == `INSTR_RTYPE_OP && Funct == `INSTR_JR_FUNCT);
  assign BranchEql = (OpCode == `INSTR_BEQ_OP ? 1 : 0);
  assign ExtOp = (OpCode == `INSTR_LUI_OP ? `EXT_HIGHPOS : (OpCode == `INSTR_ORI_OP ? `EXT_ZERO : `EXT_SIGNED));
  assign NPCCtrl = (OpCode == `INSTR_J_OP || OpCode == `INSTR_JAL_OP ? `NPC_JUMP : (OpCode == `INSTR_BEQ_OP || OpCode == `INSTR_BNE_OP ? `NPC_BRANCH : (PCDist ? `NPC_JR : `NPC_PLUS4)));

  always @(OpCode or Funct) begin
    case (OpCode)
      `INSTR_RTYPE_OP: begin
        RegDist = 1'b1;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
        if (Funct == `INSTR_JR_FUNCT) begin
          ALUOp = `ALUOp_NULL;
          RegWrite = 1'b0;
        end else begin
          ALUOp = `ALUOp_RTYPE;
          RegWrite = 1'b1;
        end
      end
      `INSTR_LW_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b1;
        MemWrite = 1'b0;
        MemToReg = 1'b1;
        RegDistDist = 1'b0;
      end
      `INSTR_SW_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b1;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_ADDI_OP: begin
        ALUOp = `ALUOp_ADD;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_ORI_OP: begin
        ALUOp = `ALUOp_OR;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_LUI_OP: begin
        ALUOp = `ALUOp_LUI;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_SLTI_OP: begin
        ALUOp = `ALUOp_SLT;
        RegDist = 1'b0;
        RegWrite = 1'b1;
        ALUSrc = 1'b1;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_BEQ_OP: begin
        ALUOp = `ALUOp_BEQ;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_BNE_OP: begin
        ALUOp = `ALUOp_BNE;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_J_OP: begin
        ALUOp = `ALUOp_NULL;
        RegDist = 1'b0;
        RegWrite = 1'b0;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b0;
      end
      `INSTR_JAL_OP: begin
        ALUOp = `ALUOp_JAL;
        RegDist = 1'b1;
        RegWrite = 1'b1;
        ALUSrc = 1'b0;
        MemRead = 1'b0;
        MemWrite = 1'b0;
        MemToReg = 1'b0;
        RegDistDist = 1'b1;
      end
      default: begin
        ALUOp = `ALUOp_NULL;
      end
    endcase
  end
endmodule