data/full_repos/permissive/468493488/vga_basic.v
1: b'%Error: data/full_repos/permissive/468493488/vga_basic.v:33: Cannot find file containing module: \'clocksyn\'\nclocksyn clock_synth ( .CLKIN_IN (Clk12), \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468493488,data/full_repos/permissive/468493488/clocksyn\n             data/full_repos/permissive/468493488,data/full_repos/permissive/468493488/clocksyn.v\n             data/full_repos/permissive/468493488,data/full_repos/permissive/468493488/clocksyn.sv\n             clocksyn\n             clocksyn.v\n             clocksyn.sv\n             obj_dir/clocksyn\n             obj_dir/clocksyn.v\n             obj_dir/clocksyn.sv\n%Error: data/full_repos/permissive/468493488/vga_basic.v:47: Cannot find file containing module: \'vga_sync\'\nvga_sync vs(.CLK (CLK), .HS (HSync), .VS (VSync), .x (x), .y (y), .blank(blank));\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:127: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                    : ... In instance vga_basic\nassign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);\n                                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:127: Operator AND expects 8 bits on the LHS, but LHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:127: Operator AND expects 8 bits on the RHS, but RHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:127: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 8 bits.\n                                                                    : ... In instance vga_basic\nassign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:128: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                    : ... In instance vga_basic\nassign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:128: Operator AND expects 8 bits on the LHS, but LHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:128: Operator AND expects 8 bits on the RHS, but RHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:128: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 8 bits.\n                                                                    : ... In instance vga_basic\nassign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:129: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                    : ... In instance vga_basic\nassign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:129: Operator AND expects 8 bits on the LHS, but LHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:129: Operator AND expects 8 bits on the RHS, but RHS\'s LT generates 1 bits.\n                                                                    : ... In instance vga_basic\nassign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/468493488/vga_basic.v:129: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 8 bits.\n                                                                    : ... In instance vga_basic\nassign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);\n                ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n'
module vga_basic(
    input Clk12,
    output HSync,
    output VSync,
    output [2:0] Red,
    output [2:0] Green,
    output [1:0] Blue,
	 input [7:0] IO_P1,
	 output [7:0] LED
    );
assign LED = IO_P1;
wire CLK;
clocksyn clock_synth ( .CLKIN_IN (Clk12), 
                   .CLKFX_OUT (CLK));
localparam MEM_SIZE = 128;
reg [7:0] memory [0:MEM_SIZE-1];
initial begin
  $readmemh("ghost32.txt", memory);
end
reg [7:0] memory2 [0:MEM_SIZE-1];
initial begin
  $readmemh("ball32.txt", memory2);
end
wire [9:0] x;
wire [9:0] y;
wire blank;
vga_sync vs(.CLK (CLK), .HS (HSync), .VS (VSync), .x (x), .y (y), .blank(blank));
reg VSync2;
always @(posedge CLK)
begin
  VSync2 <= VSync;
end
wire Upd;
assign Upd = VSync & ~VSync2;

localparam SP_COUNT =3;
reg [9:0] xp [0:SP_COUNT-1],yp [0:SP_COUNT-1];
reg xd [0:SP_COUNT-1],yd [0:SP_COUNT-1];
initial begin
  xp[0]=50;
  yp[0]=60;
  xp[1]=100;
  yp[1]=80;
  xp[2]=200;
  yp[2]=120;
  xd[0]=1;
  yd[0]=0;
  xd[1]=0;
  yd[1]=1;
  xd[2]=0;
  yd[2]=1;
end
integer i;

always @(posedge CLK)
begin
  if (Upd)
  begin
	 for(i=0; i<SP_COUNT; i=i+1)
	 begin
    if (xd[i])
	 begin
      xp[i] <= xp[i]+1;
      if (xp[i]>=(640-1-32))
		begin
		  xd[i]<=0;
		end  
    end
	 else
	 begin
      xp[i] <= xp[i]-1;
      if (xp[i]<=1)
		begin
		  xd[i]<=1;
		end  
    end
    if (yd[i])
	 begin
      yp[i] <= yp[i]+1;
      if (yp[i]>=(480-1-32))
		begin
		  yd[i]<=0;
		end  
    end
	 else
	 begin
      yp[i] <= yp[i]-1;
      if (yp[i]<=1)
		begin
		  yd[i]<=1;
		end  
    end
    end
  end
end
wire [9:0] xs[0:SP_COUNT-1],ys[0:SP_COUNT-1];
wire shape [0:SP_COUNT-1];

genvar j;
generate
  for(j=0; j<SP_COUNT; j=j+1) 
  begin:genblk
    assign xs[j] = x-xp[j];
    assign ys[j] = y-yp[j];
  end
endgenerate
assign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);
assign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);
assign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);

reg [2:0] Red2,Green2;
reg [1:0] Blue2;

always @(posedge CLK)
begin
  Red2 <= (shape[2]^(~blank &(x >= 0) & (x < 200) & (y > 0) & (y < 300)))?7:0;
  Green2 <= (shape[1]^((x > 200) & (x < 400) & (y > 150) & (y < 350)))?7:0;
  Blue2 <= (shape[0]^((x > 300) & (x < 640) & (y > 180) & (y < 480)))?3:0;
end
assign Red = Red2;
assign Green = Green2;
assign Blue = Blue2;

endmodule
module vga_basic(
    input Clk12,
    output HSync,
    output VSync,
    output [2:0] Red,
    output [2:0] Green,
    output [1:0] Blue,
	 input [7:0] IO_P1,
	 output [7:0] LED
    );

assign LED = IO_P1;
wire CLK;
clocksyn clock_synth ( .CLKIN_IN (Clk12), 
                   .CLKFX_OUT (CLK));
localparam MEM_SIZE = 128;
reg [7:0] memory [0:MEM_SIZE-1];
initial begin
  $readmemh("ghost32.txt", memory);
end
reg [7:0] memory2 [0:MEM_SIZE-1];
initial begin
  $readmemh("ball32.txt", memory2);
end
wire [9:0] x;
wire [9:0] y;
wire blank;
vga_sync vs(.CLK (CLK), .HS (HSync), .VS (VSync), .x (x), .y (y), .blank(blank));
reg VSync2;
always @(posedge CLK)
begin
  VSync2 <= VSync;
end
wire Upd;
assign Upd = VSync & ~VSync2;

localparam SP_COUNT =3;
reg [9:0] xp [0:SP_COUNT-1],yp [0:SP_COUNT-1];
reg xd [0:SP_COUNT-1],yd [0:SP_COUNT-1];
initial begin
  xp[0]=50;
  yp[0]=60;
  xp[1]=100;
  yp[1]=80;
  xp[2]=200;
  yp[2]=120;
  xd[0]=1;
  yd[0]=0;
  xd[1]=0;
  yd[1]=1;
  xd[2]=0;
  yd[2]=1;
end
integer i;

always @(posedge CLK)
begin
  if (Upd)
  begin
	 for(i=0; i<SP_COUNT; i=i+1)
	 begin
    if (xd[i])
	 begin
      xp[i] <= xp[i]+1;
      if (xp[i]>=(640-1-32))
		begin
		  xd[i]<=0;
		end  
    end
	 else
	 begin
      xp[i] <= xp[i]-1;
      if (xp[i]<=1)
		begin
		  xd[i]<=1;
		end  
    end
    if (yd[i])
	 begin
      yp[i] <= yp[i]+1;
      if (yp[i]>=(480-1-32))
		begin
		  yd[i]<=0;
		end  
    end
	 else
	 begin
      yp[i] <= yp[i]-1;
      if (yp[i]<=1)
		begin
		  yd[i]<=1;
		end  
    end
    end
  end
end
wire [9:0] xs[0:SP_COUNT-1],ys[0:SP_COUNT-1];
wire shape [0:SP_COUNT-1];

genvar j;
generate
  for(j=0; j<SP_COUNT; j=j+1) 
  begin:genblk
    assign xs[j] = x-xp[j];
    assign ys[j] = y-yp[j];
  end
endgenerate
assign shape[0] = (xs[0] < 32) & (ys[0] < 32) & (memory [xs[0][4:3]+ys[0]*4]>>~xs[0][2:0]);
assign shape[1] = (xs[1] < 32) & (ys[1] < 32) & (memory2[xs[1][4:3]+ys[1]*4]>>~xs[1][2:0]);
assign shape[2] = (xs[2] < 32) & (ys[2] < 32) & (memory2[xs[2][4:3]+ys[2]*4]>>~xs[2][2:0]);

reg [2:0] Red2,Green2;
reg [1:0] Blue2;

always @(posedge CLK)
begin
  Red2 <= (shape[2]^(~blank &(x >= 0) & (x < 200) & (y > 0) & (y < 300)))?7:0;
  Green2 <= (shape[1]^((x > 200) & (x < 400) & (y > 150) & (y < 350)))?7:0;
  Blue2 <= (shape[0]^((x > 300) & (x < 640) & (y > 180) & (y < 480)))?3:0;
end
assign Red = Red2;
assign Green = Green2;
assign Blue = Blue2;

endmodule