data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:19: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t%b\\t%b\\t%d\\t%d\\t",clk , enable, reset, load, pre_load, value);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #5 enable=1; pre_load=15; load=0; reset=0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; pre_load=15; load=0; reset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #30 enable=1; pre_load=15; load=1; reset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #2  enable=1; pre_load=15; load=0; reset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 enable=1; pre_load=15; load=0; reset=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/program_counter/top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg clk;
    reg enable;
    reg [11:0] pre_load;
    reg load;
    reg reset;
    wire [11:0] value;


    program_counter PC(clk, enable, reset, load, pre_load, value);

    initial begin
        clk=0; enable=0; pre_load=0; load=0; reset=0;

        $display("clk\tenable\treset\tload\t_preload\tvalue");
        $monitor("%b\t%b\t%b\t%b\t%d\t%d\t",clk , enable, reset, load, pre_load, value);

        #5 enable=1; pre_load=15; load=0; reset=0;
        #2 enable=1; pre_load=15; load=0; reset=0;

        #30 enable=1; pre_load=15; load=1; reset=0;
        #2  enable=1; pre_load=15; load=0; reset=0;

        #10 enable=1; pre_load=15; load=0; reset=1;

        #20 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


endmodule
module testbench();


    reg clk;
    reg enable;
    reg [11:0] pre_load;
    reg load;
    reg reset;
    wire [11:0] value;


    program_counter PC(clk, enable, reset, load, pre_load, value);

    initial begin
        clk=0; enable=0; pre_load=0; load=0; reset=0;

        $display("clk\tenable\treset\tload\t_preload\tvalue");
        $monitor("%b\t%b\t%b\t%b\t%d\t%d\t",clk , enable, reset, load, pre_load, value);

        #5 enable=1; pre_load=15; load=0; reset=0;
        #2 enable=1; pre_load=15; load=0; reset=0;

        #30 enable=1; pre_load=15; load=1; reset=0;
        #2  enable=1; pre_load=15; load=0; reset=0;

        #10 enable=1; pre_load=15; load=0; reset=1;

        #20 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


endmodule