data/full_repos/permissive/512077043/rgb_fifo/async-fifo.v
1: b"%Error: data/full_repos/permissive/512077043/rgb_fifo/async-fifo.v:105: Cannot find file containing module: 'w_ptr_full'\n    w_ptr_full #(.ADDR_SIZE(ADDR_SIZE)) w_ptr_full (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/512077043/rgb_fifo,data/full_repos/permissive/512077043/w_ptr_full\n             data/full_repos/permissive/512077043/rgb_fifo,data/full_repos/permissive/512077043/w_ptr_full.v\n             data/full_repos/permissive/512077043/rgb_fifo,data/full_repos/permissive/512077043/w_ptr_full.sv\n             w_ptr_full\n             w_ptr_full.v\n             w_ptr_full.sv\n             obj_dir/w_ptr_full\n             obj_dir/w_ptr_full.v\n             obj_dir/w_ptr_full.sv\n%Error: data/full_repos/permissive/512077043/rgb_fifo/async-fifo.v:116: Cannot find file containing module: 'r_ptr_empty'\n    r_ptr_empty #(.ADDR_SIZE(ADDR_SIZE)) r_ptr_empty (\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module async_fifo #(


    parameter   DATA_SIZE = 8,
    parameter   ADDR_SIZE = 4
) (


    input       [DATA_SIZE-1:0] w_data,
    input                       w_en,
    input                       w_clk,
    input                       w_rst,
    input                       r_en,
    input                       r_clk,
    input                       r_rst,
    

    output                      w_full,
    output  reg [DATA_SIZE-1:0] r_data,
    output                      r_empty
);


    localparam  FIFO_DEPTH  = (1 << ADDR_SIZE);
    

    wire    [ADDR_SIZE-1:0] w_addr;
    wire    [ADDR_SIZE:0]   w_gray;
    wire    [ADDR_SIZE-1:0] r_addr;
    wire    [ADDR_SIZE:0]   r_gray;
    

    reg     [ADDR_SIZE:0]   w_syn_r_gray;
    reg     [ADDR_SIZE:0]   w_syn_r_gray_pipe;
    reg     [ADDR_SIZE:0]   r_syn_w_gray;
    reg     [ADDR_SIZE:0]   r_syn_w_gray_pipe;
    

    reg     [DATA_SIZE-1:0] mem [0:FIFO_DEPTH-1];
    


    


    always @ (posedge w_clk) begin
        if (w_en & ~w_full) begin
            mem[w_addr] <= w_data;
        end
    end
    


    always @ (posedge r_clk) begin
        if (r_en & ~r_empty) begin
            r_data <= mem[r_addr];
        end
    end
    


    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_syn_r_gray_pipe <= 0;
            w_syn_r_gray <= 0;
        end else begin
            w_syn_r_gray_pipe <= r_gray;
            w_syn_r_gray <= w_syn_r_gray_pipe;
        end
    end
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_syn_w_gray_pipe <= 0;
            r_syn_w_gray <= 0;
        end else begin
            r_syn_w_gray_pipe <= w_gray;
            r_syn_w_gray <= r_syn_w_gray_pipe;
        end
    end
    


    

    w_ptr_full #(.ADDR_SIZE(ADDR_SIZE)) w_ptr_full (
        .w_syn_r_gray(w_syn_r_gray),
        .w_inc(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .w_addr(w_addr),
        .w_gray(w_gray),
        .w_full(w_full)
    );
    

    r_ptr_empty #(.ADDR_SIZE(ADDR_SIZE)) r_ptr_empty (
        .r_syn_w_gray(r_syn_w_gray),
        .r_inc(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .r_addr(r_addr),
        .r_gray(r_gray),
        .r_empty(r_empty)
    );
    
endmodule
module async_fifo #(


    parameter   DATA_SIZE = 8,
    parameter   ADDR_SIZE = 4
) (


    input       [DATA_SIZE-1:0] w_data,
    input                       w_en,
    input                       w_clk,
    input                       w_rst,
    input                       r_en,
    input                       r_clk,
    input                       r_rst,
    

    output                      w_full,
    output  reg [DATA_SIZE-1:0] r_data,
    output                      r_empty
);



    localparam  FIFO_DEPTH  = (1 << ADDR_SIZE);
    

    wire    [ADDR_SIZE-1:0] w_addr;
    wire    [ADDR_SIZE:0]   w_gray;
    wire    [ADDR_SIZE-1:0] r_addr;
    wire    [ADDR_SIZE:0]   r_gray;
    

    reg     [ADDR_SIZE:0]   w_syn_r_gray;
    reg     [ADDR_SIZE:0]   w_syn_r_gray_pipe;
    reg     [ADDR_SIZE:0]   r_syn_w_gray;
    reg     [ADDR_SIZE:0]   r_syn_w_gray_pipe;
    

    reg     [DATA_SIZE-1:0] mem [0:FIFO_DEPTH-1];
    


    


    always @ (posedge w_clk) begin
        if (w_en & ~w_full) begin
            mem[w_addr] <= w_data;
        end
    end
    


    always @ (posedge r_clk) begin
        if (r_en & ~r_empty) begin
            r_data <= mem[r_addr];
        end
    end
    


    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_syn_r_gray_pipe <= 0;
            w_syn_r_gray <= 0;
        end else begin
            w_syn_r_gray_pipe <= r_gray;
            w_syn_r_gray <= w_syn_r_gray_pipe;
        end
    end
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_syn_w_gray_pipe <= 0;
            r_syn_w_gray <= 0;
        end else begin
            r_syn_w_gray_pipe <= w_gray;
            r_syn_w_gray <= r_syn_w_gray_pipe;
        end
    end
    


    

    w_ptr_full #(.ADDR_SIZE(ADDR_SIZE)) w_ptr_full (
        .w_syn_r_gray(w_syn_r_gray),
        .w_inc(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .w_addr(w_addr),
        .w_gray(w_gray),
        .w_full(w_full)
    );
    

    r_ptr_empty #(.ADDR_SIZE(ADDR_SIZE)) r_ptr_empty (
        .r_syn_w_gray(r_syn_w_gray),
        .r_inc(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .r_addr(r_addr),
        .r_gray(r_gray),
        .r_empty(r_empty)
    );
    
endmodule