data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/Notgate.v
data/verilator_xmls/c21c2b29-de32-4925-8be6-3976c999e589.xml
module top_module( 
    input in, 
    output out );

    assign out = ~in;
endmodule
module top_module( 
    input in, 
    output out );


    assign out = ~in;
endmodule