data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v
1: b"%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:7: Cannot find file containing module: 'FD1'\n  FD1 DFF_0(CK,G5,G10);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/FD1\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/FD1.v\n             data/full_repos/permissive/494490807/bench/ISCAS/Verilog,data/full_repos/permissive/494490807/FD1.sv\n             FD1\n             FD1.v\n             FD1.sv\n             obj_dir/FD1\n             obj_dir/FD1.v\n             obj_dir/FD1.sv\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:8: Cannot find file containing module: 'FD1'\n  FD1 DFF_1(CK,G6,G11);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:9: Cannot find file containing module: 'FD1'\n  FD1 DFF_2(CK,G7,G13);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:10: Cannot find file containing module: 'IV'\n  IV  NOT_0(G14,G0);\n  ^~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:11: Cannot find file containing module: 'IV'\n  IV  NOT_1(G17,G11);\n  ^~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:12: Cannot find file containing module: 'AN2'\n  AN2 AND2_0(G8,G14,G6);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:13: Cannot find file containing module: 'OR2'\n  OR2 OR2_0(G15,G12,G8);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:14: Cannot find file containing module: 'OR2'\n  OR2 OR2_1(G16,G3,G8);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:15: Cannot find file containing module: 'ND2'\n  ND2 NAND2_0(G9,G16,G15);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:16: Cannot find file containing module: 'NR2'\n  NR2 NOR2_0(G10,G14,G11);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:17: Cannot find file containing module: 'NR2'\n  NR2 NOR2_1(G11,G5,G9);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:18: Cannot find file containing module: 'NR2'\n  NR2 NOR2_2(G12,G1,G7);\n  ^~~\n%Error: data/full_repos/permissive/494490807/bench/ISCAS/Verilog/s27.v:19: Cannot find file containing module: 'NR2'\n  NR2 NOR2_3(G13,G2,G12);\n  ^~~\n%Error: Exiting due to 13 error(s)\n"
module s27(VDD,CK,G0,G1,G17,G2,G3);
input VDD,CK,G0,G1,G2,G3;
output G17;

  wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

  FD1 DFF_0(CK,G5,G10);
  FD1 DFF_1(CK,G6,G11);
  FD1 DFF_2(CK,G7,G13);
  IV  NOT_0(G14,G0);
  IV  NOT_1(G17,G11);
  AN2 AND2_0(G8,G14,G6);
  OR2 OR2_0(G15,G12,G8);
  OR2 OR2_1(G16,G3,G8);
  ND2 NAND2_0(G9,G16,G15);
  NR2 NOR2_0(G10,G14,G11);
  NR2 NOR2_1(G11,G5,G9);
  NR2 NOR2_2(G12,G1,G7);
  NR2 NOR2_3(G13,G2,G12);

endmodule
module s27(VDD,CK,G0,G1,G17,G2,G3);

input VDD,CK,G0,G1,G2,G3;
output G17;

  wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

  FD1 DFF_0(CK,G5,G10);
  FD1 DFF_1(CK,G6,G11);
  FD1 DFF_2(CK,G7,G13);
  IV  NOT_0(G14,G0);
  IV  NOT_1(G17,G11);
  AN2 AND2_0(G8,G14,G6);
  OR2 OR2_0(G15,G12,G8);
  OR2 OR2_1(G16,G3,G8);
  ND2 NAND2_0(G9,G16,G15);
  NR2 NOR2_0(G10,G14,G11);
  NR2 NOR2_1(G11,G5,G9);
  NR2 NOR2_2(G12,G1,G7);
  NR2 NOR2_3(G13,G2,G12);

endmodule