data/full_repos/permissive/42434302/ivltests/pr377.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr377.v:1: syntax error, unexpected \'.\', expecting \'[\'\nmodule dummy (.B(A[2:1]));\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr377.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #1 A <= idx;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr377.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #1 $finish;\n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module dummy (.B(A[2:1]));
  input [2:1] A;
always @(A)
   $display (A);
endmodule
module dummy (.B(A[2:1]));

  input [2:1] A;
always @(A)
   $display (A);
endmodule