data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational Logic/Multiplexers/mux9to1v.v
1: b'%Error: Cannot find file containing module: Logic/Multiplexers,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/506562943.sv\n             Logic/Multiplexers,data/full_repos/permissive/506562943\n             Logic/Multiplexers,data/full_repos/permissive/506562943.v\n             Logic/Multiplexers,data/full_repos/permissive/506562943.sv\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/506562943\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/506562943.v\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Combinational\n%Error: Cannot find file containing module: Logic/Multiplexers/mux9to1v.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );

    always @(*) begin
        case (sel)
            4'd0: out = a;
            4'd1: out = b;
            4'd2: out = c;
            4'd3: out = d;
            4'd4: out = e;
            4'd5: out = f;
            4'd6: out = g;
            4'd7: out = h;
            4'd8: out = i;
            default: out = 16'hffff;
        endcase
    end
    
endmodule
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );


    always @(*) begin
        case (sel)
            4'd0: out = a;
            4'd1: out = b;
            4'd2: out = c;
            4'd3: out = d;
            4'd4: out = e;
            4'd5: out = f;
            4'd6: out = g;
            4'd7: out = h;
            4'd8: out = i;
            default: out = 16'hffff;
        endcase
    end
    
endmodule