data/full_repos/permissive/446939020/risc-v/adr_gen.v
data/verilator_xmls/93d87a77-1ed4-43ad-a5ef-a775cbc3f8f3.xml
module addr_gen(output [31:0]PCnext,PCplus4,input PCSrc,input [31:0]immext,pc);
  
  reg [31:0]PCTarget;
  
  assign PCplus4= pc+32'h4;
  assign PCTarget=immext+pc;
  
  assign PCnext = PCSrc ? PCTarget : PCplus4;
  
  
endmodule
module addr_gen(output [31:0]PCnext,PCplus4,input PCSrc,input [31:0]immext,pc);

  
  reg [31:0]PCTarget;
  
  assign PCplus4= pc+32'h4;
  assign PCTarget=immext+pc;
  
  assign PCnext = PCSrc ? PCTarget : PCplus4;
  
  
endmodule