data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:11: Unsupported: Ignoring delay on this delayed statement.\n        clock = 0; forever #10 clock = ~clock; \n                           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:15: Unsupported: fork statements\n    fork\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #0    D = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #15   D = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #35   D = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #65   D = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #88   D = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #125  D = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #130  D = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:26: Unsupported: Ignoring delay on this delayed statement.\n    initial #150 $finish;\n            ^\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:30: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("posedgedff.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/452183855/lab3/t_Lab3_Pos_Edge_D_FF_gatelevel.v:31: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars;\n            ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Lab3_Pos_Edge_D_FF_gatelevel();
    
    wire Q, NQ;
    reg  D, clock;

    Lab3_Pos_Edge_D_FF_gatelevel M0(Q, NQ, D, clock);

    initial 
    begin
        clock = 0; forever #10 clock = ~clock; 
    end

    initial 
    fork

        #0    D = 0;
        #15   D = 1;
        #35   D = 0;
        #65   D = 1;
        #88   D = 0;
        #125  D = 1;
        #130  D = 0;

    join
    initial #150 $finish;

    initial
        begin
            $dumpfile("posedgedff.vcd");
            $dumpvars;
        end
endmodule
module t_Lab3_Pos_Edge_D_FF_gatelevel();

    
    wire Q, NQ;
    reg  D, clock;

    Lab3_Pos_Edge_D_FF_gatelevel M0(Q, NQ, D, clock);

    initial 
    begin
        clock = 0; forever #10 clock = ~clock; 
    end

    initial 
    fork

        #0    D = 0;
        #15   D = 1;
        #35   D = 0;
        #65   D = 1;
        #88   D = 0;
        #125  D = 1;
        #130  D = 0;

    join
    initial #150 $finish;

    initial
        begin
            $dumpfile("posedgedff.vcd");
            $dumpvars;
        end
endmodule