data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v
1: b'%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v.v\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:19: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] csr_mie,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus] csr_mie,\n                   ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:20: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] csr_mstatus\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:31: Define or directive not defined: \'`DoubleRegBus\'\n reg[`DoubleRegBus]    mtime;   \n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`DoubleRegBus]    mtime;   \n                  ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:32: Define or directive not defined: \'`DoubleRegBus\'\n reg[`DoubleRegBus]    mtimecmp;  \n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`DoubleRegBus]    mtimecmp;  \n                  ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:33: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]      msip;\n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]      msip;\n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:36: syntax error, unexpected always\n    always @(posedge wb_clk_i) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:39: Define or directive not defined: \'`ZeroWord\'\n    wb_dat_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:41: Define or directive not defined: \'`ZeroWord\'\n    msip <= `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:42: Define or directive not defined: \'`ZeroWord\'\n    mtimecmp[63:32] <= `ZeroWord;      \n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:50: Define or directive not defined: \'`CLINT_BASE\'\n     if(wb_adr_i == `CLINT_BASE + 32\'h4000) begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:52: Define or directive not defined: \'`CLINT_BASE\'\n     end else if(wb_adr_i == `CLINT_BASE) begin\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:56: Define or directive not defined: \'`CLINT_BASE\'\n     if(wb_adr_i == `CLINT_BASE + 32\'h4000) begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:58: Define or directive not defined: \'`CLINT_BASE\'\n     end else if(wb_adr_i == `CLINT_BASE + 32\'hbff8) begin\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/clint.v:60: Define or directive not defined: \'`CLINT_BASE\'\n     end else if(wb_adr_i == `CLINT_BASE) begin\n                             ^~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module clint(
	input  wire 	wb_clk_i,
	input  wire   	wb_rst_i,
	input  wire   	[31:0] wb_adr_i,
	output reg 		[31:0] wb_dat_o,
	input  wire   	[31:0] wb_dat_i,
	input  wire   	[3:0] wb_sel_i,
	input  wire   	wb_we_i,
	input  wire   	wb_stb_i,
	input  wire   	wb_cyc_i,
	output reg 		wb_ack_o,

	output reg Interrupt,
	output reg [30:0] Exception_code,
	

	input wire[`RegBus]	csr_mie,
	input wire[`RegBus]	csr_mstatus
);

    parameter aw = 32;
    parameter dw = 32;


    wire wb_acc = wb_cyc_i & wb_stb_i;
    wire wb_wr  = wb_acc & wb_we_i;
    wire wb_rd  = wb_acc & !wb_we_i;

	reg[`DoubleRegBus]				mtime;
	reg[`DoubleRegBus]				mtimecmp;
	reg[`RegBus]						msip;
	reg software_interrupt_already;
	
    always @(posedge wb_clk_i) begin
        if( wb_rst_i == 1'b1 ) begin
            wb_ack_o <= 1'b0;
				wb_dat_o <= `ZeroWord;
				mtime <= 64'h0000000000000000;
				msip <= `ZeroWord;
				mtimecmp[63:32] <= `ZeroWord;
        end else if(wb_acc == 1'b0) begin
				mtime <= mtime + 1'h1;
            wb_ack_o <= 1'b0;

        end else if(wb_acc == 1'b1) begin
				mtime <= mtime + 1'h1;
				if(wb_wr == 1'b1) begin
					if(wb_adr_i == `CLINT_BASE + 32'h4000) begin
						mtimecmp[31:0] <= wb_dat_i;
					end else if(wb_adr_i == `CLINT_BASE) begin
						msip <= wb_dat_i;
					end
				end else if(wb_rd == 1'b1) begin
					if(wb_adr_i == `CLINT_BASE + 32'h4000) begin
						wb_dat_o <= mtimecmp[31:0];
					end else if(wb_adr_i == `CLINT_BASE + 32'hbff8) begin
						wb_dat_o <= mtime[31:0];
					end else if(wb_adr_i == `CLINT_BASE) begin
						wb_dat_o <= msip;
					end
				end
				 wb_ack_o <= 1'b1;
        end
		  if(software_interrupt_already == 1'b1) begin
				msip <= 1'b0;
			end
      end
	
	always @ (*) begin
		if(wb_rst_i == 1'b1) begin
			Interrupt = 1'b0;
			Exception_code = {3'b0, 28'h0000000};
			software_interrupt_already = 1'b0;
		end else begin
			if((mtime >= mtimecmp) &&
					(csr_mstatus[3] == 1'b1) &&
								(csr_mie[7] == 1'b1))begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h0000007};
			end else if((msip == 32'h00000001) &&
								(csr_mstatus[3] == 1'b1) &&
									(csr_mie[3] == 1'b1)) begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h0000000};
				software_interrupt_already <= 1'b1;
			end else begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
		end
		if(msip == 32'h00000000) begin
			software_interrupt_already = 1'b0;
		end
	end
	
	
endmodule
module clint(
	input  wire 	wb_clk_i,
	input  wire   	wb_rst_i,
	input  wire   	[31:0] wb_adr_i,
	output reg 		[31:0] wb_dat_o,
	input  wire   	[31:0] wb_dat_i,
	input  wire   	[3:0] wb_sel_i,
	input  wire   	wb_we_i,
	input  wire   	wb_stb_i,
	input  wire   	wb_cyc_i,
	output reg 		wb_ack_o,

	output reg Interrupt,
	output reg [30:0] Exception_code,
	

	input wire[`RegBus]	csr_mie,
	input wire[`RegBus]	csr_mstatus
);


    parameter aw = 32;
    parameter dw = 32;


    wire wb_acc = wb_cyc_i & wb_stb_i;
    wire wb_wr  = wb_acc & wb_we_i;
    wire wb_rd  = wb_acc & !wb_we_i;

	reg[`DoubleRegBus]				mtime;
	reg[`DoubleRegBus]				mtimecmp;
	reg[`RegBus]						msip;
	reg software_interrupt_already;
	
    always @(posedge wb_clk_i) begin
        if( wb_rst_i == 1'b1 ) begin
            wb_ack_o <= 1'b0;
				wb_dat_o <= `ZeroWord;
				mtime <= 64'h0000000000000000;
				msip <= `ZeroWord;
				mtimecmp[63:32] <= `ZeroWord;
        end else if(wb_acc == 1'b0) begin
				mtime <= mtime + 1'h1;
            wb_ack_o <= 1'b0;

        end else if(wb_acc == 1'b1) begin
				mtime <= mtime + 1'h1;
				if(wb_wr == 1'b1) begin
					if(wb_adr_i == `CLINT_BASE + 32'h4000) begin
						mtimecmp[31:0] <= wb_dat_i;
					end else if(wb_adr_i == `CLINT_BASE) begin
						msip <= wb_dat_i;
					end
				end else if(wb_rd == 1'b1) begin
					if(wb_adr_i == `CLINT_BASE + 32'h4000) begin
						wb_dat_o <= mtimecmp[31:0];
					end else if(wb_adr_i == `CLINT_BASE + 32'hbff8) begin
						wb_dat_o <= mtime[31:0];
					end else if(wb_adr_i == `CLINT_BASE) begin
						wb_dat_o <= msip;
					end
				end
				 wb_ack_o <= 1'b1;
        end
		  if(software_interrupt_already == 1'b1) begin
				msip <= 1'b0;
			end
      end
	
	always @ (*) begin
		if(wb_rst_i == 1'b1) begin
			Interrupt = 1'b0;
			Exception_code = {3'b0, 28'h0000000};
			software_interrupt_already = 1'b0;
		end else begin
			if((mtime >= mtimecmp) &&
					(csr_mstatus[3] == 1'b1) &&
								(csr_mie[7] == 1'b1))begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h0000007};
			end else if((msip == 32'h00000001) &&
								(csr_mstatus[3] == 1'b1) &&
									(csr_mie[3] == 1'b1)) begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h0000000};
				software_interrupt_already <= 1'b1;
			end else begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
		end
		if(msip == 32'h00000000) begin
			software_interrupt_already = 1'b0;
		end
	end
	
	
endmodule