data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/06_encoder/encoder_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module encoder_test(t1, t2);
output [7:0]   t1;
input  [2:0]   t2;


reg            t1;

initial begin
   t1 <= 8'b0000_0001;

   #100;
   t1 <= 8'b0000_0010;

   #100;
   t1 <= 8'b0000_0100;

   #100;
   t1 <= 8'b0000_1000;

   #100;
   t1 <= 8'b0001_0000;

   #100;
   t1 <= 8'b0010_0000;

   #100;
   t1 <= 8'b0100_0000;

   #100;
   t1 <= 8'b1000_0000;

   #100;
   $finish;
end

endmodule
module encoder_test(t1, t2);

output [7:0]   t1;
input  [2:0]   t2;


reg            t1;

initial begin
   t1 <= 8'b0000_0001;

   #100;
   t1 <= 8'b0000_0010;

   #100;
   t1 <= 8'b0000_0100;

   #100;
   t1 <= 8'b0000_1000;

   #100;
   t1 <= 8'b0001_0000;

   #100;
   t1 <= 8'b0010_0000;

   #100;
   t1 <= 8'b0100_0000;

   #100;
   t1 <= 8'b1000_0000;

   #100;
   $finish;
end

endmodule