data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:294: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'counter\'\nmodule counter(\n       ^~~~~~~\n                                                                                           : ... Top module \'buf1clear\'\nmodule buf1clear(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:468: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_addr\' generates 15 bits.\n                                                                                        : ... In instance counter.sA\n      toSave = s_addr;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:476: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      1: i_addr = 16\'d2;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:477: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      2: i_addr = 16\'d3;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:478: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      3: i_addr = 16\'d4;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:479: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      4: i_addr = 16\'d5;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:480: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      5: i_addr = 16\'d6;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:481: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      6: i_addr = 16\'d7;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:482: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      7: i_addr = 16\'d8;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:486: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n     if(exp) i_addr = 16\'d8;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:499: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n    JMP: if(dataAddr == 0) i_addr = num;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:518: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n        if(dataAddr == 0) i_addr = num;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:546: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh2\' generates 32 or 2 bits.\n                                                                                        : ... In instance counter.sA\n         n_int = 2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:531: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'toCont\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = toCont;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:536: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = num;\n                 ^\n%Error: Exiting due to 15 warning(s)\n'
module saveAddr(
	input clk,
	input rst,
	
	input prst,
	
	input s,
	
	input[7:0] offset,
	
	input gt,
	input lt,
	input eq,
	
	input irq1,
	input irq2,
	input irq3,
	
	input exp,
	input cmpStart,
	
	output reg rem,
	
	input hlt,
	
	input[3:0] mOper,
	input[14:0] dataAddr,
	
	input[15:0] num,
	
	input[7:0] s_stackAddr,
	input[7:0] s_irq,

	
	output reg[7:0] i_irq,
	output reg[7:0] i_stackAddr,
	
	output reg pop,
	output reg push,
	
	output reg[15:0] toSave,
	input[15:0] toCont,
	
	output reg eirq,
	
	input aeq,
	input[14:0] s_addr,
	output reg[14:0] i_addr,
	
	output reg inter,
	
	input read,
	input save
);

localparam NOP = 4'd0;
localparam JEQ = 4'd1;
localparam JGT = 4'd2;
localparam JLT = 4'd3;
localparam JIS = 4'd4;
localparam JMP = 4'd5;
localparam NEX = 4'd6;
localparam CALL = 4'd7;
localparam RET = 4'd8;


wire isaeq = (aeq & eq);

reg stack1 = 0;
reg stack2 = 0;

reg f_int = 1;
reg n_int = 1;

always@(posedge clk or posedge rst)begin
	if(rst) f_int <= 1;
	else f_int <= n_int;
end

always@(posedge clk)
	stack2 <= stack1;
	
always@(*) begin
	
	pop = 0;
	push = 0;
	toSave = 0;
	stack1 = 0;
	
	n_int = f_int;
	i_stackAddr = s_stackAddr;
	
	i_addr = s_addr;
	i_irq = s_irq;
	
	eirq = 0;
	rem = 0;
	
	inter = 0;
	
	if(s_irq != 0) 
		if(~stack2) inter = 1;
		
	if(s) begin
		
			
		
		
		if((irq1 | irq2 | irq3 | exp) && (~inter) && f_int) begin

				
					push = 1;
					
					if(save) stack1 = 1;
					if(mOper != NEX) begin
						toSave = s_addr;
					end else
						toSave = s_addr + 1;
									
					i_stackAddr = s_stackAddr + 8'b1;
					i_irq = s_stackAddr + 8'd1;
					
					case({irq3,irq2,irq1})
						1: i_addr = 16'd2;
						2: i_addr = 16'd3;
						3: i_addr = 16'd4;
						4: i_addr = 16'd5;
						5: i_addr = 16'd6;
						6: i_addr = 16'd7;
						7: i_addr = 16'd8;
						default:;
					endcase
					
					if(exp) i_addr = 16'd8;
				

			end else
			case(mOper)
				default: i_addr = s_addr;
				JEQ: 	if(isaeq | eq) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;
				JLT:  if(isaeq | lt) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;
				JGT:  if(isaeq | gt) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;	
				
				JMP: if(dataAddr == 0) i_addr = num;
						else i_addr = dataAddr;
				
				NEX: begin
						if(hlt) begin
							i_addr = s_addr;
						end
						
						if(~(hlt)) i_addr = s_addr + 15'b1;
						end
						
				CALL: begin
									
								push = 1;
								toSave = s_addr + 15'd1;
								
							
								i_stackAddr = s_stackAddr + 8'b1;
								
								if(dataAddr == 0) i_addr = num;
								else i_addr = dataAddr;
						
						end
				RET:  begin
							case(dataAddr)
								default: begin
									if(s_stackAddr == s_irq && (inter)) begin
										i_irq = 0;
										eirq = 1;
									end
		
									if(dataAddr == 0) begin
										i_addr = toCont;
										i_stackAddr = s_stackAddr - 8'b1;
										pop = 1;
									end
									else begin
										i_addr = num;
										i_stackAddr = 0;
										pop = 0;
									end
								end
								1: begin
									n_int = 1;
									i_addr = s_addr + 15'b1;
								end
								2: begin
									n_int = 2;
									i_addr = s_addr + 15'b1;
								end
								
							endcase
							
						end
				
			endcase
		
		rem = 1;
				
	end
end

endmodule
module saveAddr(
	input clk,
	input rst,
	
	input prst,
	
	input s,
	
	input[7:0] offset,
	
	input gt,
	input lt,
	input eq,
	
	input irq1,
	input irq2,
	input irq3,
	
	input exp,
	input cmpStart,
	
	output reg rem,
	
	input hlt,
	
	input[3:0] mOper,
	input[14:0] dataAddr,
	
	input[15:0] num,
	
	input[7:0] s_stackAddr,
	input[7:0] s_irq,

	
	output reg[7:0] i_irq,
	output reg[7:0] i_stackAddr,
	
	output reg pop,
	output reg push,
	
	output reg[15:0] toSave,
	input[15:0] toCont,
	
	output reg eirq,
	
	input aeq,
	input[14:0] s_addr,
	output reg[14:0] i_addr,
	
	output reg inter,
	
	input read,
	input save
);


localparam NOP = 4'd0;
localparam JEQ = 4'd1;
localparam JGT = 4'd2;
localparam JLT = 4'd3;
localparam JIS = 4'd4;
localparam JMP = 4'd5;
localparam NEX = 4'd6;
localparam CALL = 4'd7;
localparam RET = 4'd8;


wire isaeq = (aeq & eq);

reg stack1 = 0;
reg stack2 = 0;

reg f_int = 1;
reg n_int = 1;

always@(posedge clk or posedge rst)begin
	if(rst) f_int <= 1;
	else f_int <= n_int;
end

always@(posedge clk)
	stack2 <= stack1;
	
always@(*) begin
	
	pop = 0;
	push = 0;
	toSave = 0;
	stack1 = 0;
	
	n_int = f_int;
	i_stackAddr = s_stackAddr;
	
	i_addr = s_addr;
	i_irq = s_irq;
	
	eirq = 0;
	rem = 0;
	
	inter = 0;
	
	if(s_irq != 0) 
		if(~stack2) inter = 1;
		
	if(s) begin
		
			
		
		
		if((irq1 | irq2 | irq3 | exp) && (~inter) && f_int) begin

				
					push = 1;
					
					if(save) stack1 = 1;
					if(mOper != NEX) begin
						toSave = s_addr;
					end else
						toSave = s_addr + 1;
									
					i_stackAddr = s_stackAddr + 8'b1;
					i_irq = s_stackAddr + 8'd1;
					
					case({irq3,irq2,irq1})
						1: i_addr = 16'd2;
						2: i_addr = 16'd3;
						3: i_addr = 16'd4;
						4: i_addr = 16'd5;
						5: i_addr = 16'd6;
						6: i_addr = 16'd7;
						7: i_addr = 16'd8;
						default:;
					endcase
					
					if(exp) i_addr = 16'd8;
				

			end else
			case(mOper)
				default: i_addr = s_addr;
				JEQ: 	if(isaeq | eq) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;
				JLT:  if(isaeq | lt) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;
				JGT:  if(isaeq | gt) i_addr = dataAddr;
						else i_addr = s_addr + 15'b1;	
				
				JMP: if(dataAddr == 0) i_addr = num;
						else i_addr = dataAddr;
				
				NEX: begin
						if(hlt) begin
							i_addr = s_addr;
						end
						
						if(~(hlt)) i_addr = s_addr + 15'b1;
						end
						
				CALL: begin
									
								push = 1;
								toSave = s_addr + 15'd1;
								
							
								i_stackAddr = s_stackAddr + 8'b1;
								
								if(dataAddr == 0) i_addr = num;
								else i_addr = dataAddr;
						
						end
				RET:  begin
							case(dataAddr)
								default: begin
									if(s_stackAddr == s_irq && (inter)) begin
										i_irq = 0;
										eirq = 1;
									end
		
									if(dataAddr == 0) begin
										i_addr = toCont;
										i_stackAddr = s_stackAddr - 8'b1;
										pop = 1;
									end
									else begin
										i_addr = num;
										i_stackAddr = 0;
										pop = 0;
									end
								end
								1: begin
									n_int = 1;
									i_addr = s_addr + 15'b1;
								end
								2: begin
									n_int = 2;
									i_addr = s_addr + 15'b1;
								end
								
							endcase
							
						end
				
			endcase
		
		rem = 1;
				
	end
end

endmodule