data/full_repos/permissive/468612001/Week06/blk/non_blk1.v
data/verilator_xmls/b9357076-1b1d-49c5-a6ea-d347d098670c.xml
module non_blk1(clk, d, q3);
	input clk;
	input d;
	output q3;
	reg q0, q1, q2, q3;
	
	always @(posedge clk) begin
		q0 <= d;
		q1 <= q0;
		q2 <= q1;
		q3 <= q2;
	end
endmodule
module non_blk1(clk, d, q3);

	input clk;
	input d;
	output q3;
	reg q0, q1, q2, q3;
	
	always @(posedge clk) begin
		q0 <= d;
		q1 <= q0;
		q2 <= q1;
		q3 <= q2;
	end
endmodule