data/full_repos/permissive/493019833/test/testcase/firrtl/ShouldBeBadUIntSubtractWithGrow/reference/ShouldBeBadUIntSubtractWithGrow.v
data/verilator_xmls/458c244b-1131-43cc-a1e8-d69a711083e1.xml
module ShouldBeBadUIntSubtractWithGrow(
    input clock,
    input reset,
    input [3:0] io_a,
    input [3:0] io_b,
    output [3:0] io_o
);
    wire [4:0] _T_5;
    SUB_UNSIGNED #(.width(4)) u_sub_1 (
        .y(_T_5),
        .a(io_a),
        .b(io_b)
    );
    wire [4:0] _T_6;
    ASUINT #(.width(5)) asuint_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [3:0] _T_7;
    TAIL #(.width(5), .n(1)) tail_3 (
        .y(_T_7),
        .in(_T_6)
    );
    wire [3:0] _r__q;
    wire [3:0] _r__d;
    DFF_POSCLK #(.width(4)) r (
        .q(_r__q),
        .d(_r__d),
        .clk(clock)
    );
    assign io_o = _r__q;
    assign _r__d = _T_7;
endmodule
module ShouldBeBadUIntSubtractWithGrow(
    input clock,
    input reset,
    input [3:0] io_a,
    input [3:0] io_b,
    output [3:0] io_o
);

    wire [4:0] _T_5;
    SUB_UNSIGNED #(.width(4)) u_sub_1 (
        .y(_T_5),
        .a(io_a),
        .b(io_b)
    );
    wire [4:0] _T_6;
    ASUINT #(.width(5)) asuint_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [3:0] _T_7;
    TAIL #(.width(5), .n(1)) tail_3 (
        .y(_T_7),
        .in(_T_6)
    );
    wire [3:0] _r__q;
    wire [3:0] _r__d;
    DFF_POSCLK #(.width(4)) r (
        .q(_r__q),
        .d(_r__d),
        .clk(clock)
    );
    assign io_o = _r__q;
    assign _r__d = _T_7;
endmodule