data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/convclk_grayffrd.v
data/verilator_xmls/615475e2-a187-4a80-a8d7-63a50799213d.xml
module convclk_grayffrd
    (
     rdclk,
     rdrst,

     fiford,
     fifoflush,
     fifonemp,
     rdfifolen,
     rdpnt_gray,
     
     rdaddr,
     read,


     wrpnt_gray
     );



parameter   ADDRB = 4;
parameter   FSHW = 2;



input               rdclk;
input               rdrst;

input               fiford;
input               fifoflush;
output              fifonemp;
output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    rdpnt_gray;

output [ADDRB-1:0]  rdaddr;
output              read;

input [ADDRB:0]     wrpnt_gray;







reg [ADDRB:0]       wrpnt_gray1= {(ADDRB+1){1'b0}};
reg [ADDRB:0]       wrpnt_gray2= {(ADDRB+1){1'b0}};

always @ ( posedge rdclk)






        begin
        wrpnt_gray1  <= wrpnt_gray;
        wrpnt_gray2  <= wrpnt_gray1;      
        end

reg [ADDRB:0] wrpnt_bin = {(ADDRB+1){1'b0}};
reg [ADDRB:0] wrpnt_bin_n= {(ADDRB+1){1'b0}};
integer       i;
always @ (wrpnt_gray2)  for (i=0;i<(ADDRB+1);i=i+1) wrpnt_bin_n[i] = ^(wrpnt_gray2[ADDRB:0]>>i);

generate
    begin
    if (FSHW == 2)
        begin: inst_2clkpp
        always @ (wrpnt_bin_n)  wrpnt_bin = wrpnt_bin_n;
        end
    else
        begin: inst_3clkpp
        always @ (posedge rdclk)    wrpnt_bin <= wrpnt_bin_n;
        end
    end
endgenerate


reg     [ADDRB:0]   rdpnt_bin= {(ADDRB+1){1'b0}};

wire                fifonemp;
assign              fifonemp    = ~ (wrpnt_bin[ADDRB:0] == rdpnt_bin[ADDRB:0]);

wire                read;
assign              read        = fiford & fifonemp;

wire [ADDRB-1:0]    rdaddr;
assign              rdaddr      = rdpnt_bin[ADDRB-1:0];

wire [ADDRB:0]      rdfifolen;
assign              rdfifolen   = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];


always @ ( posedge rdclk)
    if(rdrst)
        begin
        rdpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) rdpnt_bin <= {(ADDRB+1){1'b0}};
        else if (read) rdpnt_bin <= rdpnt_bin + 1'b1;      
        end

reg [ADDRB:0]       rdpnt_gray= {(ADDRB+1){1'b0}};

always @ ( posedge rdclk)
    if(rdrst)
        begin
        rdpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        rdpnt_gray  <= rdpnt_bin ^ {1'b0,rdpnt_bin[ADDRB:1]};
        end

endmodule
module convclk_grayffrd
    (
     rdclk,
     rdrst,

     fiford,
     fifoflush,
     fifonemp,
     rdfifolen,
     rdpnt_gray,
     
     rdaddr,
     read,


     wrpnt_gray
     );




parameter   ADDRB = 4;
parameter   FSHW = 2;



input               rdclk;
input               rdrst;

input               fiford;
input               fifoflush;
output              fifonemp;
output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    rdpnt_gray;

output [ADDRB-1:0]  rdaddr;
output              read;

input [ADDRB:0]     wrpnt_gray;







reg [ADDRB:0]       wrpnt_gray1= {(ADDRB+1){1'b0}};
reg [ADDRB:0]       wrpnt_gray2= {(ADDRB+1){1'b0}};

always @ ( posedge rdclk)






        begin
        wrpnt_gray1  <= wrpnt_gray;
        wrpnt_gray2  <= wrpnt_gray1;      
        end

reg [ADDRB:0] wrpnt_bin = {(ADDRB+1){1'b0}};
reg [ADDRB:0] wrpnt_bin_n= {(ADDRB+1){1'b0}};
integer       i;
always @ (wrpnt_gray2)  for (i=0;i<(ADDRB+1);i=i+1) wrpnt_bin_n[i] = ^(wrpnt_gray2[ADDRB:0]>>i);

generate
    begin
    if (FSHW == 2)
        begin: inst_2clkpp
        always @ (wrpnt_bin_n)  wrpnt_bin = wrpnt_bin_n;
        end
    else
        begin: inst_3clkpp
        always @ (posedge rdclk)    wrpnt_bin <= wrpnt_bin_n;
        end
    end
endgenerate


reg     [ADDRB:0]   rdpnt_bin= {(ADDRB+1){1'b0}};

wire                fifonemp;
assign              fifonemp    = ~ (wrpnt_bin[ADDRB:0] == rdpnt_bin[ADDRB:0]);

wire                read;
assign              read        = fiford & fifonemp;

wire [ADDRB-1:0]    rdaddr;
assign              rdaddr      = rdpnt_bin[ADDRB-1:0];

wire [ADDRB:0]      rdfifolen;
assign              rdfifolen   = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];


always @ ( posedge rdclk)
    if(rdrst)
        begin
        rdpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) rdpnt_bin <= {(ADDRB+1){1'b0}};
        else if (read) rdpnt_bin <= rdpnt_bin + 1'b1;      
        end

reg [ADDRB:0]       rdpnt_gray= {(ADDRB+1){1'b0}};

always @ ( posedge rdclk)
    if(rdrst)
        begin
        rdpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        rdpnt_gray  <= rdpnt_bin ^ {1'b0,rdpnt_bin[ADDRB:1]};
        end

endmodule