data/full_repos/permissive/519420376/RTL/Pix_clk_gen.v
data/verilator_xmls/c2f76b5f-db34-48cb-a2c7-dedb02f25130.xml
module Pix_clk_gen(
    input i_clk,
    input i_rst_n , 
    output out_clk
    );
    reg [1:0] clk_cnt = 0 ;
    
    always @(posedge i_clk or negedge i_rst_n)
            begin
              if (i_rst_n==1'b0)
                    begin
                      clk_cnt <= 0;
                         end
                      else
                   begin      
                 clk_cnt <= clk_cnt + 1'b1 ;
               end
           end
       assign out_clk = (clk_cnt == 2'b00)?1'b1: 1'b0;
             
endmodule
module Pix_clk_gen(
    input i_clk,
    input i_rst_n , 
    output out_clk
    );

    reg [1:0] clk_cnt = 0 ;
    
    always @(posedge i_clk or negedge i_rst_n)
            begin
              if (i_rst_n==1'b0)
                    begin
                      clk_cnt <= 0;
                         end
                      else
                   begin      
                 clk_cnt <= clk_cnt + 1'b1 ;
               end
           end
       assign out_clk = (clk_cnt == 2'b00)?1'b1: 1'b0;
             
endmodule