data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv
1: b'%Error: data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv:22: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb,data/full_repos/permissive/506636840/timescale.v\n             data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb,data/full_repos/permissive/506636840/timescale.v.v\n             data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb,data/full_repos/permissive/506636840/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv:24: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n       ^~~~~~~\n%Error: data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv:65: syntax error, unexpected \'#\'\n  uvm_config_db #(virtual apb_if)::set(null, "uvm_test_top", "APB_vif", APB);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv:78: Unsupported: Ignoring delay on this delayed statement.\n    #10ns PCLK = ~PCLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506636840/block_level_tbs/spi_tb/tb/top_tb.sv:82: Unsupported: Ignoring delay on this delayed statement.\n    #10ns PCLK = ~PCLK;\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module top_tb;

`include "timescale.v"

import uvm_pkg::*;
import spi_test_lib_pkg::*;



logic PCLK;
logic PRESETn;




apb_if APB(PCLK, PRESETn);
spi_if SPI();
intr_if INTR();


spi_top DUT(

    .PCLK(PCLK),
    .PRESETN(PRESETn),
    .PSEL(APB.PSEL[0]),
    .PADDR(APB.PADDR[4:0]),
    .PWDATA(APB.PWDATA),
    .PRDATA(APB.PRDATA),
    .PENABLE(APB.PENABLE),
    .PREADY(APB.PREADY),
    .PSLVERR(),
    .PWRITE(APB.PWRITE),

    .IRQ(INTR.IRQ),

    .ss_pad_o(SPI.cs),
    .sclk_pad_o(SPI.clk),
    .mosi_pad_o(SPI.mosi),
    .miso_pad_i(SPI.miso)
);




initial begin
  uvm_config_db #(virtual apb_if)::set(null, "uvm_test_top", "APB_vif", APB);
  uvm_config_db #(virtual spi_if)::set(null, "uvm_test_top", "SPI_vif", SPI);
  uvm_config_db #(virtual intr_if)::set(null, "uvm_test_top", "INTR_vif", INTR);
  run_test();
end




initial begin
  PCLK = 0;
  PRESETn = 0;
  repeat(8) begin
    #10ns PCLK = ~PCLK;
  end
  PRESETn = 1;
  forever begin
    #10ns PCLK = ~PCLK;
  end
end

endmodule
module top_tb;


`include "timescale.v"

import uvm_pkg::*;
import spi_test_lib_pkg::*;



logic PCLK;
logic PRESETn;




apb_if APB(PCLK, PRESETn);
spi_if SPI();
intr_if INTR();


spi_top DUT(

    .PCLK(PCLK),
    .PRESETN(PRESETn),
    .PSEL(APB.PSEL[0]),
    .PADDR(APB.PADDR[4:0]),
    .PWDATA(APB.PWDATA),
    .PRDATA(APB.PRDATA),
    .PENABLE(APB.PENABLE),
    .PREADY(APB.PREADY),
    .PSLVERR(),
    .PWRITE(APB.PWRITE),

    .IRQ(INTR.IRQ),

    .ss_pad_o(SPI.cs),
    .sclk_pad_o(SPI.clk),
    .mosi_pad_o(SPI.mosi),
    .miso_pad_i(SPI.miso)
);




initial begin
  uvm_config_db #(virtual apb_if)::set(null, "uvm_test_top", "APB_vif", APB);
  uvm_config_db #(virtual spi_if)::set(null, "uvm_test_top", "SPI_vif", SPI);
  uvm_config_db #(virtual intr_if)::set(null, "uvm_test_top", "INTR_vif", INTR);
  run_test();
end




initial begin
  PCLK = 0;
  PRESETn = 0;
  repeat(8) begin
    #10ns PCLK = ~PCLK;
  end
  PRESETn = 1;
  forever begin
    #10ns PCLK = ~PCLK;
  end
end

endmodule