data/full_repos/permissive/445488268/trivium-verilog/trivium_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445488268/trivium-verilog/trivium_top_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445488268/trivium-verilog/trivium_top_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk_i = ~clk_i;\n    ^\n%Error: data/full_repos/permissive/445488268/trivium-verilog/trivium_top_tb.v:56: Cannot find file containing module: \'trivium_top\'\ntrivium_top uut(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/trivium_top\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/trivium_top.v\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/trivium_top.sv\n             trivium_top\n             trivium_top.v\n             trivium_top.sv\n             obj_dir/trivium_top\n             obj_dir/trivium_top.v\n             obj_dir/trivium_top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trivium_top_tb;






reg             clk_i;
reg             n_rst_i;
reg     [31:0]  dat_i;
reg     [31:0]  ld_dat_i;
reg     [2:0]   ld_reg_a_i;
reg     [2:0]   ld_reg_b_i;   
reg             init_i;
reg             proc_i;


wire    [31:0]  dat_o;
wire            busy_o;     


reg start_tests_s;
reg     [95:0]  key_r;
reg     [95:0]  iv_r;
integer instr_v;
integer dat_cntr_v;
integer cur_test_v;




trivium_top uut(
    .clk_i(clk_i),
    .n_rst_i(n_rst_i),
    .dat_i(dat_i),
    .ld_dat_i(ld_dat_i),
    .ld_reg_a_i(ld_reg_a_i),
    .ld_reg_b_i(ld_reg_b_i),   
    .init_i(init_i),    
    .proc_i(proc_i),    
    .dat_o(dat_o),
    .busy_o(busy_o)     
);




initial begin

    clk_i = 0;
    n_rst_i = 0;
    dat_i = 0;
    ld_dat_i = 0;
    ld_reg_a_i = 0;
    ld_reg_b_i = 0;   
    init_i = 0;
    proc_i = 0;
    

    start_tests_s = 0;
    instr_v = 0;
    dat_cntr_v = 0;
    cur_test_v = 0;
    

    #100;
    n_rst_i = 1'b1;
    start_tests_s = 1'b1;
end




always begin
    #10 clk_i = ~clk_i;
end




always @(posedge clk_i or negedge n_rst_i) begin
    if (!n_rst_i) begin

        dat_i <= 0;
        ld_dat_i <= 0;
        ld_reg_a_i <= 0;
        ld_reg_b_i <= 0;   
        init_i <= 0;
        proc_i <= 0;   
        instr_v <= 0;
        dat_cntr_v <= 0;
        key_r <= 0;
        iv_r <= 0;
    end
    else if (start_tests_s) begin
        case (instr_v)
            0: begin
                if (busy_o) begin
                    $display("ERROR: Test (Core ready) failed!");
                    $finish;
                end


                key_r[79:0] <= 80'b0;
                iv_r[79:0] <= 80'b0;

                instr_v <= instr_v + 1;
            end
         
            1: begin

                ld_reg_a_i <= 0;
                
                if (dat_cntr_v < 3) begin
                    ld_reg_a_i[dat_cntr_v] <= 1'b1;
                    ld_dat_i <= key_r[(dat_cntr_v*32)+:32];
                    dat_cntr_v <= dat_cntr_v + 1;
                end
                else begin
                   dat_cntr_v = 0;
                   instr_v <= instr_v + 1;
                end
             end
         
            2: begin

                ld_reg_b_i <= 0;
             
                if (dat_cntr_v < 3) begin
                    ld_reg_b_i[dat_cntr_v] <= 1'b1;
                    ld_dat_i <= iv_r[(dat_cntr_v*32)+:32];
                    dat_cntr_v <= dat_cntr_v + 1;
                end
                else begin
                    dat_cntr_v <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            3: begin
                init_i <= 1'b1;
                if (busy_o)
                    instr_v <= instr_v + 1;
            end
         
            4: begin
                init_i <= 0;
                if (!busy_o) begin
                    proc_i <= 1'b1;
                    dat_i <= 32'b0;
                    instr_v <= instr_v + 1;
                end
            end
            
            5: begin
                if (busy_o) begin
                    proc_i <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            6: begin
                if (!busy_o) begin

                   if (dat_o != 32'h26bfe0fb) begin
                        $display("ERROR: Incorrect output!");
                        $display("%04x != %04x, input = %04x", dat_o, 32'h8f85cc52, 32'h74657374);
                        $finish;
                   end
               
                    dat_cntr_v <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            7: begin
                cur_test_v <= 0;
                instr_v <= instr_v + 1;
            end
         
            default: begin
                $display("Tests successfully completed!");
                $finish;
            end
        endcase
    end
end
      
endmodule
module trivium_top_tb;







reg             clk_i;
reg             n_rst_i;
reg     [31:0]  dat_i;
reg     [31:0]  ld_dat_i;
reg     [2:0]   ld_reg_a_i;
reg     [2:0]   ld_reg_b_i;   
reg             init_i;
reg             proc_i;


wire    [31:0]  dat_o;
wire            busy_o;     


reg start_tests_s;
reg     [95:0]  key_r;
reg     [95:0]  iv_r;
integer instr_v;
integer dat_cntr_v;
integer cur_test_v;




trivium_top uut(
    .clk_i(clk_i),
    .n_rst_i(n_rst_i),
    .dat_i(dat_i),
    .ld_dat_i(ld_dat_i),
    .ld_reg_a_i(ld_reg_a_i),
    .ld_reg_b_i(ld_reg_b_i),   
    .init_i(init_i),    
    .proc_i(proc_i),    
    .dat_o(dat_o),
    .busy_o(busy_o)     
);




initial begin

    clk_i = 0;
    n_rst_i = 0;
    dat_i = 0;
    ld_dat_i = 0;
    ld_reg_a_i = 0;
    ld_reg_b_i = 0;   
    init_i = 0;
    proc_i = 0;
    

    start_tests_s = 0;
    instr_v = 0;
    dat_cntr_v = 0;
    cur_test_v = 0;
    

    #100;
    n_rst_i = 1'b1;
    start_tests_s = 1'b1;
end




always begin
    #10 clk_i = ~clk_i;
end




always @(posedge clk_i or negedge n_rst_i) begin
    if (!n_rst_i) begin

        dat_i <= 0;
        ld_dat_i <= 0;
        ld_reg_a_i <= 0;
        ld_reg_b_i <= 0;   
        init_i <= 0;
        proc_i <= 0;   
        instr_v <= 0;
        dat_cntr_v <= 0;
        key_r <= 0;
        iv_r <= 0;
    end
    else if (start_tests_s) begin
        case (instr_v)
            0: begin
                if (busy_o) begin
                    $display("ERROR: Test (Core ready) failed!");
                    $finish;
                end


                key_r[79:0] <= 80'b0;
                iv_r[79:0] <= 80'b0;

                instr_v <= instr_v + 1;
            end
         
            1: begin

                ld_reg_a_i <= 0;
                
                if (dat_cntr_v < 3) begin
                    ld_reg_a_i[dat_cntr_v] <= 1'b1;
                    ld_dat_i <= key_r[(dat_cntr_v*32)+:32];
                    dat_cntr_v <= dat_cntr_v + 1;
                end
                else begin
                   dat_cntr_v = 0;
                   instr_v <= instr_v + 1;
                end
             end
         
            2: begin

                ld_reg_b_i <= 0;
             
                if (dat_cntr_v < 3) begin
                    ld_reg_b_i[dat_cntr_v] <= 1'b1;
                    ld_dat_i <= iv_r[(dat_cntr_v*32)+:32];
                    dat_cntr_v <= dat_cntr_v + 1;
                end
                else begin
                    dat_cntr_v <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            3: begin
                init_i <= 1'b1;
                if (busy_o)
                    instr_v <= instr_v + 1;
            end
         
            4: begin
                init_i <= 0;
                if (!busy_o) begin
                    proc_i <= 1'b1;
                    dat_i <= 32'b0;
                    instr_v <= instr_v + 1;
                end
            end
            
            5: begin
                if (busy_o) begin
                    proc_i <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            6: begin
                if (!busy_o) begin

                   if (dat_o != 32'h26bfe0fb) begin
                        $display("ERROR: Incorrect output!");
                        $display("%04x != %04x, input = %04x", dat_o, 32'h8f85cc52, 32'h74657374);
                        $finish;
                   end
               
                    dat_cntr_v <= 0;
                    instr_v <= instr_v + 1;
                end
            end
         
            7: begin
                cur_test_v <= 0;
                instr_v <= instr_v + 1;
            end
         
            default: begin
                $display("Tests successfully completed!");
                $finish;
            end
        endcase
    end
end
      
endmodule