data/full_repos/permissive/43856783/Booth_64/comp_32.v
data/verilator_xmls/ae9e3bf7-2c92-47a4-a108-7f6fd9d86f48.xml
module comp_32(
    input [31:0] A,
    output [31:0] C
    );
	 
	 assign C = (~A)+1'b1;
	 
endmodule
module comp_32(
    input [31:0] A,
    output [31:0] C
    );

	 
	 assign C = (~A)+1'b1;
	 
endmodule