data/full_repos/permissive/418749135/shift_left.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418749135/shift_left.v:16: Unsupported or unknown PLI call: $monitor\n        $monitor(" in = ", in ," en = ", en,  " clk = ",clk, " Q = %b", Q);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:21: Unsupported: Ignoring delay on this delayed statement.\n           #4 in = 1;     en = 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:22: Unsupported: Ignoring delay on this delayed statement.\n           #4 in = 0;     en = 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:23: Unsupported: Ignoring delay on this delayed statement.\n           #4 in = 1;     en = 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:24: Unsupported: Ignoring delay on this delayed statement.\n           #4 in = 0;     en = 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:25: Unsupported: Ignoring delay on this delayed statement.\n     #4 in = 1;     en = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #4 in = 0;     en = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:27: Unsupported: Ignoring delay on this delayed statement.\n     #4 in = 0;     en = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #4 in = 1;     en = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/shift_left.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #5 $finish;\n     ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulas;

    reg en, in , clk; 
    wire [7:0] Q;

    shift_left_register   srr1(in, en, Q, clk);

    initial 
        clk = 0;
    
    always
        #2 clk = ~clk;
    
    initial 
        $monitor(" in = ", in ," en = ", en,  " clk = ",clk, " Q = %b", Q);
    
    initial 
        begin
		      in = 0;     en = 0;
           #4 in = 1;     en = 1;
           #4 in = 0;     en = 1;
           #4 in = 1;     en = 1;
           #4 in = 0;     en = 1;
		   #4 in = 1;     en = 1;
		   #4 in = 0;     en = 1;
		   #4 in = 0;     en = 1;
		   #4 in = 1;     en = 1;
		   
		   #5 $finish;
   end

endmodule
module stimulas;


    reg en, in , clk; 
    wire [7:0] Q;

    shift_left_register   srr1(in, en, Q, clk);

    initial 
        clk = 0;
    
    always
        #2 clk = ~clk;
    
    initial 
        $monitor(" in = ", in ," en = ", en,  " clk = ",clk, " Q = %b", Q);
    
    initial 
        begin
		      in = 0;     en = 0;
           #4 in = 1;     en = 1;
           #4 in = 0;     en = 1;
           #4 in = 1;     en = 1;
           #4 in = 0;     en = 1;
		   #4 in = 1;     en = 1;
		   #4 in = 0;     en = 1;
		   #4 in = 0;     en = 1;
		   #4 in = 1;     en = 1;
		   
		   #5 $finish;
   end

endmodule