data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:8: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.sv\n             ./const/parameters.v\n             ./const/parameters.v.v\n             ./const/parameters.v.sv\n             obj_dir/./const/parameters.v\n             obj_dir/./const/parameters.v.v\n             obj_dir/./const/parameters.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:218: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:265: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:302: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:330: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:364: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:512: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:912: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module normalizeAndExpUpdate(prenormalized, lza_shamt, cExpIsSmall, shamt, exp_correction, normalized, res_exp, normalized_exp);

  `include "./const/parameters.v"

  input [2*(SIG_WIDTH+1)+CSIG_WIDTH+8:0] prenormalized;
  input [5:0] lza_shamt, shamt;
  input cExpIsSmall;
  input [EXP_WIDTH-1:0] res_exp;
  output [EXP_WIDTH-1:0] normalized_exp;


  output exp_correction;
  output [(CSIG_WIDTH+1)+2:0] normalized;

  wire [2*(SIG_WIDTH+1)+CSIG_WIDTH+8:0] normalized1,normalized2,normalized3;



  wire shamt_portion = (shamt >2*(SIG_WIDTH+1)+4);
  wire [5:0] lza_corrected1 = (shamt_portion)? lza_shamt+(2*(SIG_WIDTH+1)+4) : shamt;
  wire [EXP_WIDTH-1:0] exp_update1 = (shamt_portion)? res_exp-lza_shamt+3+cExpIsSmall-(shamt<=21) : res_exp+1;


  assign normalized1 = prenormalized << lza_corrected1;


  reg [1:0] corr_shamt;
  reg [EXP_WIDTH-1:0] exp_update2;
  always @ * begin
     casex(normalized1[2*(SIG_WIDTH+1)+CSIG_WIDTH+8:2*(SIG_WIDTH+1)+CSIG_WIDTH+8-2])
       3'b001: begin corr_shamt=2;  exp_update2 = exp_update1 - 2; end
       3'b01x: begin corr_shamt=1; exp_update2 = exp_update1 - 1; end
       3'b000: begin corr_shamt=3; exp_update2 = exp_update1 - 3; end
       default: begin corr_shamt=0; exp_update2 = exp_update1; end
     endcase
  end

  assign normalized2 = normalized1<< corr_shamt;

  assign normalized = normalized2[2*(SIG_WIDTH+1)+CSIG_WIDTH+8:2*(SIG_WIDTH+1)+5];
  assign exp_correction = (~normalized1[2*(SIG_WIDTH+1)+CSIG_WIDTH+8]);

  assign normalized_exp = exp_update2;

endmodule
module normalizeAndExpUpdate(prenormalized, lza_shamt, cExpIsSmall, shamt, exp_correction, normalized, res_exp, normalized_exp);


  `include "./const/parameters.v"

  input [2*(SIG_WIDTH+1)+CSIG_WIDTH+8:0] prenormalized;
  input [5:0] lza_shamt, shamt;
  input cExpIsSmall;
  input [EXP_WIDTH-1:0] res_exp;
  output [EXP_WIDTH-1:0] normalized_exp;


  output exp_correction;
  output [(CSIG_WIDTH+1)+2:0] normalized;

  wire [2*(SIG_WIDTH+1)+CSIG_WIDTH+8:0] normalized1,normalized2,normalized3;



  wire shamt_portion = (shamt >2*(SIG_WIDTH+1)+4);
  wire [5:0] lza_corrected1 = (shamt_portion)? lza_shamt+(2*(SIG_WIDTH+1)+4) : shamt;
  wire [EXP_WIDTH-1:0] exp_update1 = (shamt_portion)? res_exp-lza_shamt+3+cExpIsSmall-(shamt<=21) : res_exp+1;


  assign normalized1 = prenormalized << lza_corrected1;


  reg [1:0] corr_shamt;
  reg [EXP_WIDTH-1:0] exp_update2;
  always @ * begin
     casex(normalized1[2*(SIG_WIDTH+1)+CSIG_WIDTH+8:2*(SIG_WIDTH+1)+CSIG_WIDTH+8-2])
       3'b001: begin corr_shamt=2;  exp_update2 = exp_update1 - 2; end
       3'b01x: begin corr_shamt=1; exp_update2 = exp_update1 - 1; end
       3'b000: begin corr_shamt=3; exp_update2 = exp_update1 - 3; end
       default: begin corr_shamt=0; exp_update2 = exp_update1; end
     endcase
  end

  assign normalized2 = normalized1<< corr_shamt;

  assign normalized = normalized2[2*(SIG_WIDTH+1)+CSIG_WIDTH+8:2*(SIG_WIDTH+1)+5];
  assign exp_correction = (~normalized1[2*(SIG_WIDTH+1)+CSIG_WIDTH+8]);

  assign normalized_exp = exp_update2;

endmodule