data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:142: Multiple top level modules\n                                                                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                        : ... Top module \'data_arrays_0_ext\'\nmodule data_arrays_0_ext(\n       ^~~~~~~~~~~~~~~~~\n                                                                                                                                                        : ... Top module \'tag_array_ext\'\nmodule tag_array_ext(\n       ^~~~~~~~~~~~~\n                                                                                                                                                        : ... Top module \'tag_array_0_ext\'\nmodule tag_array_0_ext(\n       ^~~~~~~~~~~~~~~\n                                                                                                                                                        : ... Top module \'data_arrays_0_0_ext\'\nmodule data_arrays_0_0_ext(\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:322: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram0l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517705285/verilog/rtl/marmot,data/full_repos/permissive/517705285/sky130_sram_2kbyte_1rw1r_32x512_8\n             data/full_repos/permissive/517705285/verilog/rtl/marmot,data/full_repos/permissive/517705285/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/517705285/verilog/rtl/marmot,data/full_repos/permissive/517705285/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             sky130_sram_2kbyte_1rw1r_32x512_8\n             sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:342: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram0h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:362: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram1l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:382: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram1h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:402: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram2l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:422: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram2h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:442: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram3l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:462: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram3h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:234: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(0)) raml (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:254: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(0)) ramh (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:166: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(0)) raml (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:186: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 #(.VERBOSE(0)) ramh (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:58: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram0l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:78: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram0h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:98: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram1l (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/517705285/verilog/rtl/marmot/shc.marmotcaravel.MarmotCaravelChip.MarmotCaravelConfig.top.mems.sky130.v:118: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(0)) ram1h (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s), 1 warning(s)\n'
module data_arrays_0_ext(
  input  [9:0]  RW0_addr,
  input         RW0_clk,
  input  [63:0] RW0_wdata,
  output [63:0] RW0_rdata,
  input         RW0_en,
  input         RW0_wmode,
  input  [7:0]  RW0_wmask
);

  wire [1:0]  ram_clk;
  wire [1:0]  ram_csb0;
  wire [1:0]  ram_web0;
  wire [7:0]  ram_wmask0[1:0];
  wire [8:0]  ram_addr0[1:0];
  wire [63:0] ram_din0[1:0];
  wire [63:0] ram_dout0[1:0];
  wire [1:0]  ram_csb1;
  wire [8:0]  ram_addr1[1:0];
  reg  [1:0]  ram_dout0_sel;


  always @(posedge RW0_clk) begin
    ram_dout0_sel <= ~ram_csb0;
  end

  assign RW0_rdata = ram_dout0_sel[0] ? ram_dout0[0] :
                                        ram_dout0[1];


  genvar i;
  for (i = 0; i < 2; i = i + 1) begin : g_ram
    assign ram_clk[i]    = RW0_clk;
    assign ram_csb0[i]   = ~(RW0_en & (RW0_addr[9] == i));
    assign ram_web0[i]   = ~RW0_wmode;
    assign ram_wmask0[i] = RW0_wmask;
    assign ram_addr0[i]  = RW0_addr[8:0];
    assign ram_din0[i]   = RW0_wdata;
    assign ram_csb1[i]   = 1'b1;
    assign ram_addr1[i]  = 9'h1ff;
  end

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram0l (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[0]),
      .csb0   (ram_csb0[0]),
      .web0   (ram_web0[0]),
      .wmask0 (ram_wmask0[0][3:0]),
      .addr0  (ram_addr0[0]),
      .din0   (ram_din0[0][31:0]),
      .dout0  (ram_dout0[0][31:0]),
      .clk1   (ram_clk[0]),
      .csb1   (ram_csb1[0]),
      .addr1  (ram_addr1[0]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram0h (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[0]),
      .csb0   (ram_csb0[0]),
      .web0   (ram_web0[0]),
      .wmask0 (ram_wmask0[0][7:4]),
      .addr0  (ram_addr0[0]),
      .din0   (ram_din0[0][63:32]),
      .dout0  (ram_dout0[0][63:32]),
      .clk1   (ram_clk[0]),
      .csb1   (ram_csb1[0]),
      .addr1  (ram_addr1[0]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram1l (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[1]),
      .csb0   (ram_csb0[1]),
      .web0   (ram_web0[1]),
      .wmask0 (ram_wmask0[1][3:0]),
      .addr0  (ram_addr0[1]),
      .din0   (ram_din0[1][31:0]),
      .dout0  (ram_dout0[1][31:0]),
      .clk1   (ram_clk[1]),
      .csb1   (ram_csb1[1]),
      .addr1  (ram_addr1[1]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram1h (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[1]),
      .csb0   (ram_csb0[1]),
      .web0   (ram_web0[1]),
      .wmask0 (ram_wmask0[1][7:4]),
      .addr0  (ram_addr0[1]),
      .din0   (ram_din0[1][63:32]),
      .dout0  (ram_dout0[1][63:32]),
      .clk1   (ram_clk[1]),
      .csb1   (ram_csb1[1]),
      .addr1  (ram_addr1[1]),

      .dout1  ()

    );  
endmodule
module data_arrays_0_ext(
  input  [9:0]  RW0_addr,
  input         RW0_clk,
  input  [63:0] RW0_wdata,
  output [63:0] RW0_rdata,
  input         RW0_en,
  input         RW0_wmode,
  input  [7:0]  RW0_wmask
);


  wire [1:0]  ram_clk;
  wire [1:0]  ram_csb0;
  wire [1:0]  ram_web0;
  wire [7:0]  ram_wmask0[1:0];
  wire [8:0]  ram_addr0[1:0];
  wire [63:0] ram_din0[1:0];
  wire [63:0] ram_dout0[1:0];
  wire [1:0]  ram_csb1;
  wire [8:0]  ram_addr1[1:0];
  reg  [1:0]  ram_dout0_sel;


  always @(posedge RW0_clk) begin
    ram_dout0_sel <= ~ram_csb0;
  end

  assign RW0_rdata = ram_dout0_sel[0] ? ram_dout0[0] :
                                        ram_dout0[1];


  genvar i;
  for (i = 0; i < 2; i = i + 1) begin : g_ram
    assign ram_clk[i]    = RW0_clk;
    assign ram_csb0[i]   = ~(RW0_en & (RW0_addr[9] == i));
    assign ram_web0[i]   = ~RW0_wmode;
    assign ram_wmask0[i] = RW0_wmask;
    assign ram_addr0[i]  = RW0_addr[8:0];
    assign ram_din0[i]   = RW0_wdata;
    assign ram_csb1[i]   = 1'b1;
    assign ram_addr1[i]  = 9'h1ff;
  end

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram0l (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[0]),
      .csb0   (ram_csb0[0]),
      .web0   (ram_web0[0]),
      .wmask0 (ram_wmask0[0][3:0]),
      .addr0  (ram_addr0[0]),
      .din0   (ram_din0[0][31:0]),
      .dout0  (ram_dout0[0][31:0]),
      .clk1   (ram_clk[0]),
      .csb1   (ram_csb1[0]),
      .addr1  (ram_addr1[0]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram0h (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[0]),
      .csb0   (ram_csb0[0]),
      .web0   (ram_web0[0]),
      .wmask0 (ram_wmask0[0][7:4]),
      .addr0  (ram_addr0[0]),
      .din0   (ram_din0[0][63:32]),
      .dout0  (ram_dout0[0][63:32]),
      .clk1   (ram_clk[0]),
      .csb1   (ram_csb1[0]),
      .addr1  (ram_addr1[0]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram1l (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[1]),
      .csb0   (ram_csb0[1]),
      .web0   (ram_web0[1]),
      .wmask0 (ram_wmask0[1][3:0]),
      .addr0  (ram_addr0[1]),
      .din0   (ram_din0[1][31:0]),
      .dout0  (ram_dout0[1][31:0]),
      .clk1   (ram_clk[1]),
      .csb1   (ram_csb1[1]),
      .addr1  (ram_addr1[1]),

      .dout1  ()

    );  

    sky130_sram_2kbyte_1rw1r_32x512_8 #(.VERBOSE(`VERBOSE)) ram1h (
  `ifdef USE_POWER_PINS
      .vccd1  (vccd1),
      .vssd1  (vssd1),
  `endif
      .clk0   (ram_clk[1]),
      .csb0   (ram_csb0[1]),
      .web0   (ram_web0[1]),
      .wmask0 (ram_wmask0[1][7:4]),
      .addr0  (ram_addr0[1]),
      .din0   (ram_din0[1][63:32]),
      .dout0  (ram_dout0[1][63:32]),
      .clk1   (ram_clk[1]),
      .csb1   (ram_csb1[1]),
      .addr1  (ram_addr1[1]),

      .dout1  ()

    );  
endmodule