data/full_repos/permissive/487568919/basic_verilog/vm80a.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/vm80a.v:826: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'cl\' generates 1 bits.\n                                                                              : ... In instance vm80a.core\n          | ((id_rxc | id_ora | id_ana | id_xra) ? 8\'h00 : (x + r + cl))\n                                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function cmp
(
   input [7:0] i,
   input [7:0] c,
   input [7:0] m
);
   cmp = &(~(i ^ c) | m);
endfunction
function cmp
(
   input [7:0] i,
   input [7:0] c,
   input [7:0] m
);

   cmp = &(~(i ^ c) | m);
endfunction