data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_dtl_clkgen.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_dtl_clkgen.v:41: Cannot find file containing module: 'bw_io_impctl_dtl_sclk'\nbw_io_impctl_dtl_sclk I227 (\n^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_dtl_sclk\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_dtl_sclk.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_dtl_sclk.sv\n             bw_io_impctl_dtl_sclk\n             bw_io_impctl_dtl_sclk.v\n             bw_io_impctl_dtl_sclk.sv\n             obj_dir/bw_io_impctl_dtl_sclk\n             obj_dir/bw_io_impctl_dtl_sclk.v\n             obj_dir/bw_io_impctl_dtl_sclk.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_dtl_clkgen.v:49: Cannot find file containing module: 'bw_io_impctl_dtl_upclk'\nbw_io_impctl_dtl_upclk I208 (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bw_io_impctl_dtl_clkgen(se ,updclk ,clk ,so_l ,si_l ,
     synced_upd_imped ,avgcntr_rst ,bypass ,global_reset_n ,hard_reset_n
      ,sclk ,reset_l );
output		updclk ;
output		so_l ;
output		avgcntr_rst ;
output		bypass ;
output		global_reset_n ;
output		sclk ;
input		se ;
input		clk ;
input		si_l ;
input		synced_upd_imped ;
input		hard_reset_n ;
input		reset_l ;
 
wire		int_sclk ;
wire		net42 ;
 
 
bw_io_impctl_dtl_sclk I227 (
     .l2clk           (clk ),
     .int_sclk        (int_sclk ),
     .sclk            (sclk ),
     .ssclk_n         (net42 ),
     .se              (se ),
     .si_l            (si_l ),
     .global_reset_n  (global_reset_n ) );
bw_io_impctl_dtl_upclk I208 (
     .avgcntr_rst     (avgcntr_rst ),
     .int_sclk        (int_sclk ),
     .l2clk           (clk ),
     .synced_upd_imped (synced_upd_imped ),
     .updclk          (updclk ),
     .reset_l         (reset_l ),
     .bypass          (bypass ),
     .so_l            (so_l ),
     .hard_reset_n    (hard_reset_n ),
     .si_l            (net42 ),
     .se              (se ),
     .global_reset_n  (global_reset_n ) );
endmodule
module bw_io_impctl_dtl_clkgen(se ,updclk ,clk ,so_l ,si_l ,
     synced_upd_imped ,avgcntr_rst ,bypass ,global_reset_n ,hard_reset_n
      ,sclk ,reset_l );

output		updclk ;
output		so_l ;
output		avgcntr_rst ;
output		bypass ;
output		global_reset_n ;
output		sclk ;
input		se ;
input		clk ;
input		si_l ;
input		synced_upd_imped ;
input		hard_reset_n ;
input		reset_l ;
 
wire		int_sclk ;
wire		net42 ;
 
 
bw_io_impctl_dtl_sclk I227 (
     .l2clk           (clk ),
     .int_sclk        (int_sclk ),
     .sclk            (sclk ),
     .ssclk_n         (net42 ),
     .se              (se ),
     .si_l            (si_l ),
     .global_reset_n  (global_reset_n ) );
bw_io_impctl_dtl_upclk I208 (
     .avgcntr_rst     (avgcntr_rst ),
     .int_sclk        (int_sclk ),
     .l2clk           (clk ),
     .synced_upd_imped (synced_upd_imped ),
     .updclk          (updclk ),
     .reset_l         (reset_l ),
     .bypass          (bypass ),
     .so_l            (so_l ),
     .hard_reset_n    (hard_reset_n ),
     .si_l            (net42 ),
     .se              (se ),
     .global_reset_n  (global_reset_n ) );
endmodule