data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC_top.sv
1: b"%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC_top.sv:16: Cannot find file containing module: 'soc_top'\nsoc_top soc_inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Quartus/DE0Nano_USTCRVSoC,data/full_repos/permissive/435890256/soc_top\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Quartus/DE0Nano_USTCRVSoC,data/full_repos/permissive/435890256/soc_top.v\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Quartus/DE0Nano_USTCRVSoC,data/full_repos/permissive/435890256/soc_top.sv\n             soc_top\n             soc_top.v\n             soc_top.sv\n             obj_dir/soc_top\n             obj_dir/soc_top.v\n             obj_dir/soc_top.sv\n%Error: Exiting due to 1 error(s)\n"
module DE0Nano_USTCRVSoC_top(

    input  CLOCK_50,

    output [ 7:0]  LED,

    input  [ 1:0]  GPIO_0_IN,
    inout  [33:0]  GPIO_0,
    input  [ 1:0]  GPIO_1_IN,
    inout  [33:0]  GPIO_1
);

logic vga_red, vga_green, vga_blue;
assign GPIO_0[31:16] = {{5{vga_blue}},{6{vga_green}},{5{vga_red}}};

soc_top soc_inst(
    .clk              ( CLOCK_50      ),
    .isp_uart_rx      ( GPIO_1_IN[0]  ),
    .isp_uart_tx      ( GPIO_1[0]     ),
    .vga_hsync        ( GPIO_0[33]    ),
    .vga_vsync        ( GPIO_0[32]    ),
    .vga_red          ( vga_red       ),
    .vga_green        ( vga_green     ),
    .vga_blue         ( vga_blue      )
);


assign LED[7:6] = ~{GPIO_1_IN[0],GPIO_1[0]};


assign GPIO_0[12] = 1'b0;


reg [21:0] cnt = 22'h0;
reg [ 5:0] flow = 6'h0;
always @ (posedge CLOCK_50) begin
    cnt <= cnt + 22'h1;
    if(cnt==22'h0)
        flow <= {flow[4:0], ~flow[5]};
end
    
assign LED[5:0] = flow;

endmodule
module DE0Nano_USTCRVSoC_top(

    input  CLOCK_50,

    output [ 7:0]  LED,

    input  [ 1:0]  GPIO_0_IN,
    inout  [33:0]  GPIO_0,
    input  [ 1:0]  GPIO_1_IN,
    inout  [33:0]  GPIO_1
);


logic vga_red, vga_green, vga_blue;
assign GPIO_0[31:16] = {{5{vga_blue}},{6{vga_green}},{5{vga_red}}};

soc_top soc_inst(
    .clk              ( CLOCK_50      ),
    .isp_uart_rx      ( GPIO_1_IN[0]  ),
    .isp_uart_tx      ( GPIO_1[0]     ),
    .vga_hsync        ( GPIO_0[33]    ),
    .vga_vsync        ( GPIO_0[32]    ),
    .vga_red          ( vga_red       ),
    .vga_green        ( vga_green     ),
    .vga_blue         ( vga_blue      )
);


assign LED[7:6] = ~{GPIO_1_IN[0],GPIO_1[0]};


assign GPIO_0[12] = 1'b0;


reg [21:0] cnt = 22'h0;
reg [ 5:0] flow = 6'h0;
always @ (posedge CLOCK_50) begin
    cnt <= cnt + 22'h1;
    if(cnt==22'h0)
        flow <= {flow[4:0], ~flow[5]};
end
    
assign LED[5:0] = flow;

endmodule