data/full_repos/permissive/522149450/02.psram/src/psram_top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:70: Signal definition not found, creating implicitly: \'calib\'\n        if (calib) begin\n            ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:31: Cannot find file containing module: \'Gowin_rPLL\'\nGowin_rPLL pll( .clkout(memory_clk), .lock(pll_lock), .clkoutd(clk_d), .clkin(sys_clk));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522149450/02.psram/src,data/full_repos/permissive/522149450/Gowin_rPLL\n             data/full_repos/permissive/522149450/02.psram/src,data/full_repos/permissive/522149450/Gowin_rPLL.v\n             data/full_repos/permissive/522149450/02.psram/src,data/full_repos/permissive/522149450/Gowin_rPLL.sv\n             Gowin_rPLL\n             Gowin_rPLL.v\n             Gowin_rPLL.sv\n             obj_dir/Gowin_rPLL\n             obj_dir/Gowin_rPLL.v\n             obj_dir/Gowin_rPLL.sv\n%Error: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:43: Cannot find file containing module: \'PSRAM_Memory_Interface_HS_Top\'\nPSRAM_Memory_Interface_HS_Top psram(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:61: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                : ... In instance psram_top\n        cycle <= 8\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:75: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                : ... In instance psram_top\n                    cycle <= 8\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/522149450/02.psram/src/psram_top.v:93: Operator NEQ expects 8 bits on the LHS, but LHS\'s VARREF \'cycle\' generates 6 bits.\n                                                                                : ... In instance psram_top\n                if (cycle != 8\'b11_1111)\n                          ^~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module psram_top (
    input sys_clk,
    input sys_resetn,
    input button,

    output reg [5:0] led,

    output [CS_WIDTH-1:0] O_psram_ck,
    output [CS_WIDTH-1:0] O_psram_ck_n,
    inout [CS_WIDTH-1:0] IO_psram_rwds,
    inout [DQ_WIDTH-1:0] IO_psram_dq,
    output [CS_WIDTH-1:0] O_psram_reset_n,
    output [CS_WIDTH-1:0] O_psram_cs_n 
);

localparam  DQ_WIDTH = 16;
localparam  CS_WIDTH = 2;

wire clk;


Gowin_rPLL pll( .clkout(memory_clk), .lock(pll_lock), .clkoutd(clk_d), .clkin(sys_clk));

reg [63:0] wr_data;
wire [63:0] rd_data;
wire rd_data_valid;
reg [20:0] addr;
reg cmd;
reg cmd_en;
reg [7:0] data_mask;



PSRAM_Memory_Interface_HS_Top psram(
    .clk(sys_clk), .memory_clk(memory_clk), .pll_lock(pll_lock), .rst_n(sys_resetn),
    .O_psram_ck(O_psram_ck), .O_psram_ck_n(O_psram_ck_n), .IO_psram_rwds(IO_psram_rwds),
    .IO_psram_dq(IO_psram_dq), .O_psram_reset_n(O_psram_reset_n), .O_psram_cs_n(O_psram_cs_n),
    .addr(addr), .wr_data(wr_data), .rd_data(rd_data), .rd_data_valid(rd_data_valid),
    .cmd(cmd), .cmd_en(cmd_en), .data_mask(data_mask),
    .clk_out(clk), .init_calib(calib)
);

reg state;
reg [5:0] cycle;
reg [7:0] read_back;
reg [7:0] read_count;
reg [5:0] read_cycles;

always @(posedge clk) begin
    if (!sys_resetn) begin
        state <= 1'b0;
        cycle <= 8'b0;
        cmd_en <= 0;
        read_cycles <= 0;
        read_back <= 0;
    end else begin



        led <= button ? ~read_back[5:0] : ~read_cycles;
        if (calib) begin
            if (state == 1'b0) begin

                cycle <= cycle + 6'b1;
                if (cycle == 13) begin
                    cycle <= 8'b0;
                    state <= 1'b1;
                end

                if (cycle == 0) begin
                    addr <= 0;
                    wr_data <= {56'b0, 8'b10010011};

                    data_mask <= ~8'h01;
                    cmd <= 1'b1;
                    cmd_en <= 1'b1;
                end else begin

                    cmd_en <= 1'b0;
                    data_mask <= 8'hff;
                end
            end else begin

                if (cycle != 8'b11_1111)
                    cycle <= cycle + 6'b1;
                if (cycle == 0) begin
                    addr <= 0;
                    cmd <= 1'b0;
                    cmd_en <= 1'b1;
                    data_mask <= 8'h00;
                    read_count <= 0;
                end else begin
                    cmd_en <= 1'b0;
                    if (rd_data_valid) begin
                        read_count <= read_count + 8'b1;
                        if (read_count == 0)
                            read_back <= rd_data[7:0];
                        if (read_count == 3)
                            read_cycles <= cycle;
                    end
                end
            end
        end
    end
end


endmodule
module psram_top (
    input sys_clk,
    input sys_resetn,
    input button,

    output reg [5:0] led,

    output [CS_WIDTH-1:0] O_psram_ck,
    output [CS_WIDTH-1:0] O_psram_ck_n,
    inout [CS_WIDTH-1:0] IO_psram_rwds,
    inout [DQ_WIDTH-1:0] IO_psram_dq,
    output [CS_WIDTH-1:0] O_psram_reset_n,
    output [CS_WIDTH-1:0] O_psram_cs_n 
);


localparam  DQ_WIDTH = 16;
localparam  CS_WIDTH = 2;

wire clk;


Gowin_rPLL pll( .clkout(memory_clk), .lock(pll_lock), .clkoutd(clk_d), .clkin(sys_clk));

reg [63:0] wr_data;
wire [63:0] rd_data;
wire rd_data_valid;
reg [20:0] addr;
reg cmd;
reg cmd_en;
reg [7:0] data_mask;



PSRAM_Memory_Interface_HS_Top psram(
    .clk(sys_clk), .memory_clk(memory_clk), .pll_lock(pll_lock), .rst_n(sys_resetn),
    .O_psram_ck(O_psram_ck), .O_psram_ck_n(O_psram_ck_n), .IO_psram_rwds(IO_psram_rwds),
    .IO_psram_dq(IO_psram_dq), .O_psram_reset_n(O_psram_reset_n), .O_psram_cs_n(O_psram_cs_n),
    .addr(addr), .wr_data(wr_data), .rd_data(rd_data), .rd_data_valid(rd_data_valid),
    .cmd(cmd), .cmd_en(cmd_en), .data_mask(data_mask),
    .clk_out(clk), .init_calib(calib)
);

reg state;
reg [5:0] cycle;
reg [7:0] read_back;
reg [7:0] read_count;
reg [5:0] read_cycles;

always @(posedge clk) begin
    if (!sys_resetn) begin
        state <= 1'b0;
        cycle <= 8'b0;
        cmd_en <= 0;
        read_cycles <= 0;
        read_back <= 0;
    end else begin



        led <= button ? ~read_back[5:0] : ~read_cycles;
        if (calib) begin
            if (state == 1'b0) begin

                cycle <= cycle + 6'b1;
                if (cycle == 13) begin
                    cycle <= 8'b0;
                    state <= 1'b1;
                end

                if (cycle == 0) begin
                    addr <= 0;
                    wr_data <= {56'b0, 8'b10010011};

                    data_mask <= ~8'h01;
                    cmd <= 1'b1;
                    cmd_en <= 1'b1;
                end else begin

                    cmd_en <= 1'b0;
                    data_mask <= 8'hff;
                end
            end else begin

                if (cycle != 8'b11_1111)
                    cycle <= cycle + 6'b1;
                if (cycle == 0) begin
                    addr <= 0;
                    cmd <= 1'b0;
                    cmd_en <= 1'b1;
                    data_mask <= 8'h00;
                    read_count <= 0;
                end else begin
                    cmd_en <= 1'b0;
                    if (rd_data_valid) begin
                        read_count <= read_count + 8'b1;
                        if (read_count == 0)
                            read_back <= rd_data[7:0];
                        if (read_count == 3)
                            read_cycles <= cycle;
                    end
                end
            end
        end
    end
end


endmodule