data/full_repos/permissive/479308240/sourcemux.v
data/verilator_xmls/ffb47c77-8efa-411e-85de-148ad90ca2ee.xml
module sourcemux(input wire [7:0] A,
                 input wire [7:0] B,
                 input wire [7:0] INna,
                 input wire [7:0] outbuf,
                 input wire [2:0] sel,
                 input wire clk,
                 output reg [7:0] outna,
                 input wire srcoe
                 );


always@(posedge clk)
begin 
    if(srcoe) 
        begin
        case(sel)
                3'h1: 
                outna=A;
                3'h2: 
                outna=B;
                3'h3: 
                outna=INna;
                3'h4: 
                outna=outbuf;
                3'h5: 
                outna=8'hzz;
                3'h6: 
                outna=8'hzz;
                3'h7: 
                outna=8'hzz;
                3'h0: 
                outna=8'hzz;
           endcase
        end
end



endmodule
module sourcemux(input wire [7:0] A,
                 input wire [7:0] B,
                 input wire [7:0] INna,
                 input wire [7:0] outbuf,
                 input wire [2:0] sel,
                 input wire clk,
                 output reg [7:0] outna,
                 input wire srcoe
                 );



always@(posedge clk)
begin 
    if(srcoe) 
        begin
        case(sel)
                3'h1: 
                outna=A;
                3'h2: 
                outna=B;
                3'h3: 
                outna=INna;
                3'h4: 
                outna=outbuf;
                3'h5: 
                outna=8'hzz;
                3'h6: 
                outna=8'hzz;
                3'h7: 
                outna=8'hzz;
                3'h0: 
                outna=8'hzz;
           endcase
        end
end



endmodule