data/full_repos/permissive/418819021/lab-06/unitTest.v
1: b'%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:15: Cannot find include file: unit_tests.vh\n    `include "unit_tests.vh" // include test function in unitTest scope \n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:11: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n    output wire     [`TEST_I_ADDR_WIDTH-1:0] debug_program_counter,\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:12: Define or directive not defined: \'`STAGE_COUNT\'\n    output wire     [      `STAGE_COUNT-1:0] debug_pipeline_stage\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:17: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] pa;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:18: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] pb;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:20: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rr ;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:21: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rd ;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:22: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] debug_alu_out;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:24: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rr_addr    ;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:25: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rd_addr    ;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:26: Define or directive not defined: \'`FLAG_COUNT\'\n    wire [         `FLAG_COUNT:0] debug_flags_out  ;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:26: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [         `FLAG_COUNT:0] debug_flags_out  ;\n                              ^\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:27: Define or directive not defined: \'`TEST_INSTR_WIDTH\'\n    wire [ `TEST_INSTR_WIDTH-1:0] debug_bus_address;\n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:28: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [  `TEST_DATA_WIDTH-1:0] debug_bus_data   ;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:30: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_X;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:31: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Y;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:32: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Z;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:35: Define or directive not defined: \'`OPCODE_COUNT\'\n    wire [   `OPCODE_COUNT-1:0] debug_opcode_type    ;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:36: Define or directive not defined: \'`GROUP_COUNT\'\n    wire [    `GROUP_COUNT-1:0] debug_opcode_group   ;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:38: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n    wire [`TEST_DATA_WIDTH-1:0] debug_writeback_value;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:39: Define or directive not defined: \'`SIGNAL_COUNT\'\n    wire [   `SIGNAL_COUNT-1:0] debug_signals        ;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:42: Define or directive not defined: \'`TEST_INSTR_WIDTH\'\n        .INSTR_WIDTH     (`TEST_INSTR_WIDTH ),\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:43: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n        .DATA_WIDTH      (`TEST_DATA_WIDTH  ),\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:44: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:94: Define or directive not defined: \'`TEST_I_ADDR_WIDTH\'\n    reg [`TEST_I_ADDR_WIDTH-1:0] last_pc;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:132: Define or directive not defined: \'`STAGE_WB\'\n                    if (debug_pipeline_stage == `STAGE_WB) begin\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:132: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    if (debug_pipeline_stage == `STAGE_WB) begin\n                                                         ^\n%Error: data/full_repos/permissive/418819021/lab-06/unitTest.v:146: syntax error, unexpected INTEGER NUMBER\n            2 :  \n            ^\n%Error: Cannot continue\n'
module unitTest (
    input  wire                              clk                  ,
    input  wire                              reset                ,
    output      reg                          result               ,
    output wire     [`TEST_I_ADDR_WIDTH-1:0] debug_program_counter,
    output wire     [      `STAGE_COUNT-1:0] debug_pipeline_stage
);

    `include "unit_tests.vh"

    wire [`TEST_DATA_WIDTH-1:0] pa;
    wire [`TEST_DATA_WIDTH-1:0] pb;

    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rr ;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rd ;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_out;

    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rr_addr    ;
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rd_addr    ;
    wire [         `FLAG_COUNT:0] debug_flags_out  ;
    wire [ `TEST_INSTR_WIDTH-1:0] debug_bus_address;
    wire [  `TEST_DATA_WIDTH-1:0] debug_bus_data   ;

    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_X;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Y;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Z;

    wire [                11:0] debug_opcode_imd     ;
    wire [   `OPCODE_COUNT-1:0] debug_opcode_type    ;
    wire [    `GROUP_COUNT-1:0] debug_opcode_group   ;
    wire [                 2:0] debug_opcode_bit     ;
    wire [`TEST_DATA_WIDTH-1:0] debug_writeback_value;
    wire [   `SIGNAL_COUNT-1:0] debug_signals        ;

    cpu #(
        .INSTR_WIDTH     (`TEST_INSTR_WIDTH ),
        .DATA_WIDTH      (`TEST_DATA_WIDTH  ),
        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),
        .RST_ACTIVE_LEVEL(1                 )
    ) uut (
        .clk  (clk  ),
        .reset(reset),
        .pa   (pa   ),
        .pb   (pb   )
        `ifdef DEBUG
        ,
        .debug_pipeline_stage (debug_pipeline_stage ),
        .debug_alu_rr         (debug_alu_rr         ), 
        .debug_alu_rd         (debug_alu_rd         ), 
        .debug_alu_out        (debug_alu_out        ),
        .debug_program_counter(debug_program_counter),
        .debug_flags_out      (debug_flags_out      ),
        .debug_bus_address    (debug_bus_address    ),
        .debug_bus_data       (debug_bus_data       ),
        .debug_register_X     (debug_register_X     ),
        .debug_register_Y     (debug_register_Y     ),
        .debug_register_Z     (debug_register_Z     ),
        .debug_opcode_imd     (debug_opcode_imd     ),
        .debug_writeback_value(debug_writeback_value),
        .debug_signals        (debug_signals        )
        `endif
    );

    `ifndef DEBUG
    assign debug_program_counter = uut.program_counter;
    assign debug_pipeline_stage  = uut.pipeline_stage;

    assign debug_alu_rr  = uut.alu_rr ;
    assign debug_alu_rd  = uut.alu_rd ;
    assign debug_alu_out = uut.alu_out;

    assign debug_rr_addr     = uut.rr_addr      ;
    assign debug_rd_addr     = uut.rd_addr      ;
    assign debug_flags_out   = uut.alu_flags_out;
    assign debug_bus_address = uut.bus_addr     ;
    assign debug_bus_data    = uut.bus_data     ;

    assign debug_register_Y = {uut.reg_file.memory[29], uut.reg_file.memory[28]};

    assign debug_opcode_imd      = uut.control.opcode_imd     ;
    assign debug_opcode_type     = uut.control.opcode_type    ;
    assign debug_opcode_group    = uut.control.opcode_group   ;
    assign debug_opcode_bit      = uut.control.opcode_bit     ;
    assign debug_writeback_value = uut.control.writeback_value;
    assign debug_signals         = uut.control.signals        ;
    `endif

    reg [`TEST_I_ADDR_WIDTH-1:0] last_pc;

    integer reg_19, reg_20, reg_28, reg_17, reg_16;

    integer address;
    integer io_addr;
    integer rr_addr;
    integer rd_addr;
    integer value  ;
    integer next_pc;
    integer bit_val;

    initial begin
        $display("Init regs..");
        reg_19 = 32'dx;
        reg_20 = 32'dx;
        reg_28 = 32'dx;
        reg_17 = 32'dx;
        reg_16 = 32'dx;

        address = 32'dx;
        io_addr = 32'dx;
        rr_addr = 32'dx;
        rd_addr = 32'dx;
        bit_val = 32'dx;
        value   = 32'dx;
        result  = 0;
    end

    always @(posedge clk) begin
        case(debug_program_counter)
            0 :
                begin

                    rd_addr <= 16;
                    value   <= 1;
                    result  <= TEST_LDI(rd_addr, value);

                    if (debug_pipeline_stage == `STAGE_WB) begin
                        reg_16 <= value;
                    end
                end

            1 :
                begin

                    io_addr <= 1;
                    rr_addr <= 16;
                    result  <= TEST_OUT(io_addr, rr_addr, reg_28);

                end

            2 :
                begin

                    bit_val <= 1;
                    io_addr <= 1;

                    result <= TEST_SBI(io_addr, bit_val);





                end

            3 :
                begin
                    bit_val <= 0;
                    io_addr <= 1;

                    result <= TEST_CBI(io_addr, bit_val);

                end

            4 :
                begin
                    rd_addr <= 17;
                    io_addr <= 1;
                    result  <= TEST_IN(io_addr, rd_addr);
                end

            default :
                result <= 1'bz;
        endcase
        last_pc <= debug_program_counter;
    end

endmodule
module unitTest (
    input  wire                              clk                  ,
    input  wire                              reset                ,
    output      reg                          result               ,
    output wire     [`TEST_I_ADDR_WIDTH-1:0] debug_program_counter,
    output wire     [      `STAGE_COUNT-1:0] debug_pipeline_stage
);


    `include "unit_tests.vh"

    wire [`TEST_DATA_WIDTH-1:0] pa;
    wire [`TEST_DATA_WIDTH-1:0] pb;

    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rr ;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_rd ;
    wire [`TEST_DATA_WIDTH-1:0] debug_alu_out;

    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rr_addr    ;
    wire [`TEST_R_ADDR_WIDTH-1:0] debug_rd_addr    ;
    wire [         `FLAG_COUNT:0] debug_flags_out  ;
    wire [ `TEST_INSTR_WIDTH-1:0] debug_bus_address;
    wire [  `TEST_DATA_WIDTH-1:0] debug_bus_data   ;

    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_X;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Y;
    wire [2*`TEST_DATA_WIDTH-1:0] debug_register_Z;

    wire [                11:0] debug_opcode_imd     ;
    wire [   `OPCODE_COUNT-1:0] debug_opcode_type    ;
    wire [    `GROUP_COUNT-1:0] debug_opcode_group   ;
    wire [                 2:0] debug_opcode_bit     ;
    wire [`TEST_DATA_WIDTH-1:0] debug_writeback_value;
    wire [   `SIGNAL_COUNT-1:0] debug_signals        ;

    cpu #(
        .INSTR_WIDTH     (`TEST_INSTR_WIDTH ),
        .DATA_WIDTH      (`TEST_DATA_WIDTH  ),
        .I_ADDR_WIDTH    (`TEST_I_ADDR_WIDTH),
        .RST_ACTIVE_LEVEL(1                 )
    ) uut (
        .clk  (clk  ),
        .reset(reset),
        .pa   (pa   ),
        .pb   (pb   )
        `ifdef DEBUG
        ,
        .debug_pipeline_stage (debug_pipeline_stage ),
        .debug_alu_rr         (debug_alu_rr         ), 
        .debug_alu_rd         (debug_alu_rd         ), 
        .debug_alu_out        (debug_alu_out        ),
        .debug_program_counter(debug_program_counter),
        .debug_flags_out      (debug_flags_out      ),
        .debug_bus_address    (debug_bus_address    ),
        .debug_bus_data       (debug_bus_data       ),
        .debug_register_X     (debug_register_X     ),
        .debug_register_Y     (debug_register_Y     ),
        .debug_register_Z     (debug_register_Z     ),
        .debug_opcode_imd     (debug_opcode_imd     ),
        .debug_writeback_value(debug_writeback_value),
        .debug_signals        (debug_signals        )
        `endif
    );

    `ifndef DEBUG
    assign debug_program_counter = uut.program_counter;
    assign debug_pipeline_stage  = uut.pipeline_stage;

    assign debug_alu_rr  = uut.alu_rr ;
    assign debug_alu_rd  = uut.alu_rd ;
    assign debug_alu_out = uut.alu_out;

    assign debug_rr_addr     = uut.rr_addr      ;
    assign debug_rd_addr     = uut.rd_addr      ;
    assign debug_flags_out   = uut.alu_flags_out;
    assign debug_bus_address = uut.bus_addr     ;
    assign debug_bus_data    = uut.bus_data     ;

    assign debug_register_Y = {uut.reg_file.memory[29], uut.reg_file.memory[28]};

    assign debug_opcode_imd      = uut.control.opcode_imd     ;
    assign debug_opcode_type     = uut.control.opcode_type    ;
    assign debug_opcode_group    = uut.control.opcode_group   ;
    assign debug_opcode_bit      = uut.control.opcode_bit     ;
    assign debug_writeback_value = uut.control.writeback_value;
    assign debug_signals         = uut.control.signals        ;
    `endif

    reg [`TEST_I_ADDR_WIDTH-1:0] last_pc;

    integer reg_19, reg_20, reg_28, reg_17, reg_16;

    integer address;
    integer io_addr;
    integer rr_addr;
    integer rd_addr;
    integer value  ;
    integer next_pc;
    integer bit_val;

    initial begin
        $display("Init regs..");
        reg_19 = 32'dx;
        reg_20 = 32'dx;
        reg_28 = 32'dx;
        reg_17 = 32'dx;
        reg_16 = 32'dx;

        address = 32'dx;
        io_addr = 32'dx;
        rr_addr = 32'dx;
        rd_addr = 32'dx;
        bit_val = 32'dx;
        value   = 32'dx;
        result  = 0;
    end

    always @(posedge clk) begin
        case(debug_program_counter)
            0 :
                begin

                    rd_addr <= 16;
                    value   <= 1;
                    result  <= TEST_LDI(rd_addr, value);

                    if (debug_pipeline_stage == `STAGE_WB) begin
                        reg_16 <= value;
                    end
                end

            1 :
                begin

                    io_addr <= 1;
                    rr_addr <= 16;
                    result  <= TEST_OUT(io_addr, rr_addr, reg_28);

                end

            2 :
                begin

                    bit_val <= 1;
                    io_addr <= 1;

                    result <= TEST_SBI(io_addr, bit_val);





                end

            3 :
                begin
                    bit_val <= 0;
                    io_addr <= 1;

                    result <= TEST_CBI(io_addr, bit_val);

                end

            4 :
                begin
                    rd_addr <= 17;
                    io_addr <= 1;
                    result  <= TEST_IN(io_addr, rd_addr);
                end

            default :
                result <= 1'bz;
        endcase
        last_pc <= debug_program_counter;
    end

endmodule