data/full_repos/permissive/426864978/lab0/src/adder.sv
data/verilator_xmls/f29da8c8-d337-4eb6-b175-8699f31f5ff4.xml
module adder(input [7:0] SW, output [3:0] LEDR);
    assign LEDR = SW[7:4] + SW[3:0];
endmodule
module adder(input [7:0] SW, output [3:0] LEDR);

    assign LEDR = SW[7:4] + SW[3:0];
endmodule