data/full_repos/permissive/485295380/counter/counter_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:28: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESET\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n            state <= RESET;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:37: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'UP\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n        next_state <= UP;    \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:43: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DOWN\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n                   next_state <= DOWN;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:42: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 4 bits.\n                                                                             : ... In instance Counter_fsm\n               if (count == max) begin\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:50: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'UP\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n                    next_state <= UP;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'UP\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n                next_state <= UP;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:40: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                             : ... In instance Counter_fsm\n        case (state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:60: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                             : ... In instance Counter_fsm\n        next_state <= IDLE;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/485295380/counter/counter_fsm.v:35: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'state\' generates 2 bits.\n                                                                             : ... In instance Counter_fsm\n        if (state == RESET)begin\n                  ^~\n%Error: Exiting due to 9 warning(s)\n'
module Counter_fsm (
    input rst,
    input clk,
    input en,
    output reg [3:0] count
    );
    parameter [2:0]
        RESET = 0,
        IDLE = 1,
        UP = 2,
        DOWN = 3;
    integer max = 15;
    reg [1:0] state, next_state;
    reg clk_div;
    reg [27:0] clk_counter;
    parameter div = 28'd100000000 ;

    always @(posedge clk) begin
        clk_counter <= clk_counter + 28'd1;
        if (clk_counter >= (div - 1)) begin
            clk_counter <= 28'd0;
            clk_div <= (clk_counter < div/2) ? 1'b1 : 1'b0;
        end  
    end

    always @(posedge clk) begin
        if (rst) 
            state <= RESET;
        else 
            state <= next_state;   
    end


    always @(negedge clk_div) begin
        if (state == RESET)begin
        count <= 0;
        next_state <= UP;    
    end
    else if (en) begin
        case (state)
            UP:
               if (count == max) begin
                   next_state <= DOWN;
                   count <= count - 1'b1;
               end else begin
                   count <= count + 1'b1;
               end
            DOWN:
                if (count == 0) begin
                    next_state <= UP;
                    count <= count + 1'b1;
                end else begin
                    count <= count - 1'b1;
                end
            IDLE:
                next_state <= UP;
        endcase
        
    end else begin
        next_state <= IDLE;
    end 
    end
endmodule
module Counter_fsm (
    input rst,
    input clk,
    input en,
    output reg [3:0] count
    );

    parameter [2:0]
        RESET = 0,
        IDLE = 1,
        UP = 2,
        DOWN = 3;
    integer max = 15;
    reg [1:0] state, next_state;
    reg clk_div;
    reg [27:0] clk_counter;
    parameter div = 28'd100000000 ;

    always @(posedge clk) begin
        clk_counter <= clk_counter + 28'd1;
        if (clk_counter >= (div - 1)) begin
            clk_counter <= 28'd0;
            clk_div <= (clk_counter < div/2) ? 1'b1 : 1'b0;
        end  
    end

    always @(posedge clk) begin
        if (rst) 
            state <= RESET;
        else 
            state <= next_state;   
    end


    always @(negedge clk_div) begin
        if (state == RESET)begin
        count <= 0;
        next_state <= UP;    
    end
    else if (en) begin
        case (state)
            UP:
               if (count == max) begin
                   next_state <= DOWN;
                   count <= count - 1'b1;
               end else begin
                   count <= count + 1'b1;
               end
            DOWN:
                if (count == 0) begin
                    next_state <= UP;
                    count <= count + 1'b1;
                end else begin
                    count <= count - 1'b1;
                end
            IDLE:
                next_state <= UP;
        endcase
        
    end else begin
        next_state <= IDLE;
    end 
    end
endmodule