data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:32: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:68: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:69: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:70: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:71: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:72: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:107: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:108: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:109: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:110: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:111: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:112: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:113: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:114: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:133: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:134: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:149: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:150: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:151: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:152: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:153: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:154: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:155: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:156: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:167: Define or directive not defined: \'`PCX_WIDTH\'\n       .pcx_fpio_data_px_l(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:168: Define or directive not defined: \'`PCX_WIDTH\'\n       .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:169: Define or directive not defined: \'`PCX_WIDTH\'\n       .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:189: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:190: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:191: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:192: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:193: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:194: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:195: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array.v:196: Define or directive not defined: \'`PCX_WIDTH\'\n       .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                          ^~~~~~~~~~\n%Error: Exiting due to 36 error(s)\n'
module pcx_dp_array(

   pcx_scache3_data_px_l, pcx_scache2_data_px_l, 
   pcx_scache1_data_px_l, pcx_scache0_data_px_l, pcx_fpio_data_px_l, 
   pcx_dp_array134_so_0, pcx_dp_array02_so_1, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, si_1, si_0, se_buf1_top, 
   se_buf1_bottom, rclk, arbpc4_pcxdp_shift_px, 
   arbpc4_pcxdp_qsel1_pa, arbpc4_pcxdp_qsel0_pa, 
   arbpc4_pcxdp_q0_hold_pa, arbpc4_pcxdp_grant_pa, 
   arbpc3_pcxdp_shift_px, arbpc3_pcxdp_qsel1_pa, 
   arbpc3_pcxdp_qsel0_pa, arbpc3_pcxdp_q0_hold_pa, 
   arbpc3_pcxdp_grant_pa, arbpc2_pcxdp_shift_px, 
   arbpc2_pcxdp_qsel1_pa, arbpc2_pcxdp_qsel0_pa, 
   arbpc2_pcxdp_q0_hold_pa, arbpc2_pcxdp_grant_pa, 
   arbpc1_pcxdp_shift_px, arbpc1_pcxdp_qsel1_pa, 
   arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_q0_hold_pa, 
   arbpc1_pcxdp_grant_pa, arbpc0_pcxdp_shift_px, 
   arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa, 
   arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa
   );



   output		pcx_dp_array02_so_1;
   output		pcx_dp_array134_so_0;
   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l;




   input [7:0]		arbpc0_pcxdp_grant_pa;
   input [7:0]		arbpc0_pcxdp_q0_hold_pa;
   input [7:0]		arbpc0_pcxdp_qsel0_pa;
   input [7:0]		arbpc0_pcxdp_qsel1_pa;
   input [7:0]		arbpc0_pcxdp_shift_px;
   input [7:0]		arbpc1_pcxdp_grant_pa;
   input [7:0]		arbpc1_pcxdp_q0_hold_pa;
   input [7:0]		arbpc1_pcxdp_qsel0_pa;
   input [7:0]		arbpc1_pcxdp_qsel1_pa;
   input [7:0]		arbpc1_pcxdp_shift_px;
   input [7:0]		arbpc2_pcxdp_grant_pa;
   input [7:0]		arbpc2_pcxdp_q0_hold_pa;
   input [7:0]		arbpc2_pcxdp_qsel0_pa;
   input [7:0]		arbpc2_pcxdp_qsel1_pa;
   input [7:0]		arbpc2_pcxdp_shift_px;
   input [7:0]		arbpc3_pcxdp_grant_pa;
   input [7:0]		arbpc3_pcxdp_q0_hold_pa;
   input [7:0]		arbpc3_pcxdp_qsel0_pa;
   input [7:0]		arbpc3_pcxdp_qsel1_pa;
   input [7:0]		arbpc3_pcxdp_shift_px;
   input [7:0]		arbpc4_pcxdp_grant_pa;
   input [7:0]		arbpc4_pcxdp_q0_hold_pa;
   input [7:0]		arbpc4_pcxdp_qsel0_pa;
   input [7:0]		arbpc4_pcxdp_qsel1_pa;
   input [7:0]		arbpc4_pcxdp_shift_px;
   input		rclk;
   input		se_buf1_bottom;
   input		se_buf1_top;
   input		si_0;
   input		si_1;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;








   

                 
   pcx_dp_array02 pcx_dp_array02(

				 .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
				 .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
				 .scan_out(pcx_dp_array02_so_1),

				 .arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
				 .arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
				 .arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
				 .arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
				 .arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
				 .arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
				 .arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
				 .arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
				 .arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
				 .arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
				 .rclk	(rclk),
				 .shiftenable(se_buf1_top),
				 .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .scan_in(si_1));


   pcx_dp_array134 pcx_dp_array134(

				   .pcx_fpio_data_px_l(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),
				   .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),
				   .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),
				   .scan_out(pcx_dp_array134_so_0),

				   .arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
				   .arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7:0]),
				   .arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
				   .arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7:0]),
				   .arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
				   .arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
				   .arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa[7:0]),
				   .arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
				   .arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa[7:0]),
				   .arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
				   .arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
				   .arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[7:0]),
				   .arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
				   .arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[7:0]),
				   .arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
				   .rclk(rclk),
				   .shiftenable(se_buf1_bottom),
				   .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .scan_in(si_0));
endmodule
module pcx_dp_array(

   pcx_scache3_data_px_l, pcx_scache2_data_px_l, 
   pcx_scache1_data_px_l, pcx_scache0_data_px_l, pcx_fpio_data_px_l, 
   pcx_dp_array134_so_0, pcx_dp_array02_so_1, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, si_1, si_0, se_buf1_top, 
   se_buf1_bottom, rclk, arbpc4_pcxdp_shift_px, 
   arbpc4_pcxdp_qsel1_pa, arbpc4_pcxdp_qsel0_pa, 
   arbpc4_pcxdp_q0_hold_pa, arbpc4_pcxdp_grant_pa, 
   arbpc3_pcxdp_shift_px, arbpc3_pcxdp_qsel1_pa, 
   arbpc3_pcxdp_qsel0_pa, arbpc3_pcxdp_q0_hold_pa, 
   arbpc3_pcxdp_grant_pa, arbpc2_pcxdp_shift_px, 
   arbpc2_pcxdp_qsel1_pa, arbpc2_pcxdp_qsel0_pa, 
   arbpc2_pcxdp_q0_hold_pa, arbpc2_pcxdp_grant_pa, 
   arbpc1_pcxdp_shift_px, arbpc1_pcxdp_qsel1_pa, 
   arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_q0_hold_pa, 
   arbpc1_pcxdp_grant_pa, arbpc0_pcxdp_shift_px, 
   arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa, 
   arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa
   );




   output		pcx_dp_array02_so_1;
   output		pcx_dp_array134_so_0;
   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l;




   input [7:0]		arbpc0_pcxdp_grant_pa;
   input [7:0]		arbpc0_pcxdp_q0_hold_pa;
   input [7:0]		arbpc0_pcxdp_qsel0_pa;
   input [7:0]		arbpc0_pcxdp_qsel1_pa;
   input [7:0]		arbpc0_pcxdp_shift_px;
   input [7:0]		arbpc1_pcxdp_grant_pa;
   input [7:0]		arbpc1_pcxdp_q0_hold_pa;
   input [7:0]		arbpc1_pcxdp_qsel0_pa;
   input [7:0]		arbpc1_pcxdp_qsel1_pa;
   input [7:0]		arbpc1_pcxdp_shift_px;
   input [7:0]		arbpc2_pcxdp_grant_pa;
   input [7:0]		arbpc2_pcxdp_q0_hold_pa;
   input [7:0]		arbpc2_pcxdp_qsel0_pa;
   input [7:0]		arbpc2_pcxdp_qsel1_pa;
   input [7:0]		arbpc2_pcxdp_shift_px;
   input [7:0]		arbpc3_pcxdp_grant_pa;
   input [7:0]		arbpc3_pcxdp_q0_hold_pa;
   input [7:0]		arbpc3_pcxdp_qsel0_pa;
   input [7:0]		arbpc3_pcxdp_qsel1_pa;
   input [7:0]		arbpc3_pcxdp_shift_px;
   input [7:0]		arbpc4_pcxdp_grant_pa;
   input [7:0]		arbpc4_pcxdp_q0_hold_pa;
   input [7:0]		arbpc4_pcxdp_qsel0_pa;
   input [7:0]		arbpc4_pcxdp_qsel1_pa;
   input [7:0]		arbpc4_pcxdp_shift_px;
   input		rclk;
   input		se_buf1_bottom;
   input		se_buf1_top;
   input		si_0;
   input		si_1;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;








   

                 
   pcx_dp_array02 pcx_dp_array02(

				 .pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
				 .pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
				 .scan_out(pcx_dp_array02_so_1),

				 .arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
				 .arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
				 .arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
				 .arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
				 .arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
				 .arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
				 .arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
				 .arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
				 .arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
				 .arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
				 .rclk	(rclk),
				 .shiftenable(se_buf1_top),
				 .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),
				 .scan_in(si_1));


   pcx_dp_array134 pcx_dp_array134(

				   .pcx_fpio_data_px_l(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),
				   .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),
				   .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),
				   .scan_out(pcx_dp_array134_so_0),

				   .arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
				   .arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7:0]),
				   .arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
				   .arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7:0]),
				   .arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
				   .arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
				   .arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa[7:0]),
				   .arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
				   .arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa[7:0]),
				   .arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
				   .arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
				   .arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[7:0]),
				   .arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
				   .arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[7:0]),
				   .arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
				   .rclk(rclk),
				   .shiftenable(se_buf1_bottom),
				   .spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),
				   .scan_in(si_0));
endmodule