data/full_repos/permissive/437204475/pipeline_bp/if.v
1: b'%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/pipeline_bp,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:6: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter W = `WORD_WIDTH,\n                             ^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:8: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BP_MAX = 2\'b11,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BP_MIN = 2\'b00,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:10: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BTB_W = 8\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:11: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire stall,            \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire flush,            \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] flush_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire upd,                      \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire add_else_minus,           \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] upd_src_pc,        \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg predict_j_taken,          \n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[W-1:0] predict_addr,      \n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:26: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire[W-1:0] read_inst,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] inst\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:28: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:31: Define or directive not defined: \'`ZERO_WORD\'\n            inst <= `ZERO_WORD;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:32: Define or directive not defined: \'`ZERO_WORD\'\n            pc <= `ZERO_WORD;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:33: Define or directive not defined: \'`FALSE\'\n            predict_j_taken <= `FALSE;\n                               ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:42: syntax error, unexpected generate\n    generate\n    ^~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:44: syntax error, unexpected always\n        always @(*) begin\n        ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:46: Define or directive not defined: \'`ZERO_WORD\'\n                btb[i] <= `ZERO_WORD;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline_bp/if.v:77: Define or directive not defined: \'`ZERO_WORD\'\n            pc <= `ZERO_WORD;\n                  ^~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module pc_with_bp_btb #(
    parameter W = `WORD_WIDTH,
    parameter BP_BITS = 2,
    parameter BP_MAX = 2'b11,
    parameter BP_MIN = 2'b00,
    parameter BTB_W = 8
) (
    input wire clk, rst,
    input wire stall,
    input wire flush,
    input wire[W-1:0] flush_addr,

    input wire upd,
    input wire add_else_minus,
    input wire[W-1:0] upd_src_pc,

    output reg[W-1:0] pc,

    output reg predict_j_taken,
    output reg[W-1:0] predict_addr,

    input wire[W-1:0] read_inst,
    output reg[W-1:0] inst
);
    always @(*) begin
        if (rst) begin
            inst <= `ZERO_WORD;
            pc <= `ZERO_WORD;
            predict_j_taken <= `FALSE;
        end
    end


    reg[BP_BITS-1:0] bp[(1<<BTB_W)-1:0];

    reg[W-1:0] btb[(1<<BTB_W)-1:0];

    generate
        integer i;
        always @(*) begin
            if (rst) for (i = 0; i < (1<<BTB_W); i = i + 1) begin: bp_btb_rst
                btb[i] <= `ZERO_WORD;
                bp[i] <= (BP_BITS >> 1);
            end
        end
    endgenerate


    always @(posedge clk) begin
        if (upd) begin
            if (add_else_minus) begin
                if (bp[upd_src_pc[BTB_W+1:2]] != BP_MAX) begin
                    bp[upd_src_pc[BTB_W+1:2]] <= bp[upd_src_pc[BTB_W+1:2]] + 1;
                end
            end
            else begin
                if (bp[upd_src_pc[BTB_W+1:2]] != BP_MIN) begin
                    bp[upd_src_pc[BTB_W+1:2]] <= bp[upd_src_pc[BTB_W+1:2]] - 1;
                end
            end
        end
    end


    always @(posedge clk) begin
        predict_j_taken <= ( | (bp[pc[BTB_W+1:2]] >> (BTB_W>>1)) );
        predict_addr <= btb[pc[BTB_W+1:2]];
    end


    always @(posedge clk) begin
        if (rst) begin
            pc <= `ZERO_WORD;
        end
        else if (stall) begin
            pc <= pc;
        end
        else if (flush) begin
            pc <= flush_addr;
            btb[upd_src_pc[BTB_W+1:2]] <= flush_addr;
        end
        else if (predict_j_taken) begin
            pc <= predict_addr;
        end
        else begin
            pc <= pc + 4;
        end
    end

    always @(negedge clk) begin
        inst <= read_inst;
    end

endmodule
module pc_with_bp_btb #(
    parameter W = `WORD_WIDTH,
    parameter BP_BITS = 2,
    parameter BP_MAX = 2'b11,
    parameter BP_MIN = 2'b00,
    parameter BTB_W = 8
) (
    input wire clk, rst,
    input wire stall,
    input wire flush,
    input wire[W-1:0] flush_addr,

    input wire upd,
    input wire add_else_minus,
    input wire[W-1:0] upd_src_pc,

    output reg[W-1:0] pc,

    output reg predict_j_taken,
    output reg[W-1:0] predict_addr,

    input wire[W-1:0] read_inst,
    output reg[W-1:0] inst
);

    always @(*) begin
        if (rst) begin
            inst <= `ZERO_WORD;
            pc <= `ZERO_WORD;
            predict_j_taken <= `FALSE;
        end
    end


    reg[BP_BITS-1:0] bp[(1<<BTB_W)-1:0];

    reg[W-1:0] btb[(1<<BTB_W)-1:0];

    generate
        integer i;
        always @(*) begin
            if (rst) for (i = 0; i < (1<<BTB_W); i = i + 1) begin: bp_btb_rst
                btb[i] <= `ZERO_WORD;
                bp[i] <= (BP_BITS >> 1);
            end
        end
    endgenerate


    always @(posedge clk) begin
        if (upd) begin
            if (add_else_minus) begin
                if (bp[upd_src_pc[BTB_W+1:2]] != BP_MAX) begin
                    bp[upd_src_pc[BTB_W+1:2]] <= bp[upd_src_pc[BTB_W+1:2]] + 1;
                end
            end
            else begin
                if (bp[upd_src_pc[BTB_W+1:2]] != BP_MIN) begin
                    bp[upd_src_pc[BTB_W+1:2]] <= bp[upd_src_pc[BTB_W+1:2]] - 1;
                end
            end
        end
    end


    always @(posedge clk) begin
        predict_j_taken <= ( | (bp[pc[BTB_W+1:2]] >> (BTB_W>>1)) );
        predict_addr <= btb[pc[BTB_W+1:2]];
    end


    always @(posedge clk) begin
        if (rst) begin
            pc <= `ZERO_WORD;
        end
        else if (stall) begin
            pc <= pc;
        end
        else if (flush) begin
            pc <= flush_addr;
            btb[upd_src_pc[BTB_W+1:2]] <= flush_addr;
        end
        else if (predict_j_taken) begin
            pc <= predict_addr;
        end
        else begin
            pc <= pc + 4;
        end
    end

    always @(negedge clk) begin
        inst <= read_inst;
    end

endmodule