data/full_repos/permissive/425106492/rtl/clock_generator.v
1: b"%Error: data/full_repos/permissive/425106492/rtl/clock_generator.v:25: Cannot find file containing module: 'clk_wiz_0'\n    clk_wiz_0\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/clk_wiz_0\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/clk_wiz_0.v\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: Exiting due to 1 error(s)\n"
module clock_unit
(
    input  wire i_clock,
    input  wire i_reset,
    output wire o_sys_clock,
    output wire o_adc_clock,
    output wire o_dac_clock,
    output wire o_valid
);
    
    wire        locked;
    
    assign  o_valid =   ~locked;


    clk_wiz_0
    u_clk_wiz_0
    (
        .clk_out1           ( o_sys_clock   ),
        .clk_out2           ( o_adc_clock   ),
        .clk_out3           ( o_dac_clock   ),
        .reset              ( i_reset       ),
        .locked             ( locked        ),
        .clk_in1            ( i_clock       )
    );
    
endmodule
module clock_unit
(
    input  wire i_clock,
    input  wire i_reset,
    output wire o_sys_clock,
    output wire o_adc_clock,
    output wire o_dac_clock,
    output wire o_valid
);

    
    wire        locked;
    
    assign  o_valid =   ~locked;


    clk_wiz_0
    u_clk_wiz_0
    (
        .clk_out1           ( o_sys_clock   ),
        .clk_out2           ( o_adc_clock   ),
        .clk_out3           ( o_dac_clock   ),
        .reset              ( i_reset       ),
        .locked             ( locked        ),
        .clk_in1            ( i_clock       )
    );
    
endmodule