data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_tx_c.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_tx_c.v:1: Cannot find include file: byte_striping_c.v\n`include "byte_striping_c.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_striping_c.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_striping_c.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/byte_striping_c.v.sv\n             byte_striping_c.v\n             byte_striping_c.v.v\n             byte_striping_c.v.sv\n             obj_dir/byte_striping_c.v\n             obj_dir/byte_striping_c.v.v\n             obj_dir/byte_striping_c.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_tx_c.v:2: Cannot find include file: word32_8bits_c.v\n`include "word32_8bits_c.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_tx_c.v:3: Cannot find include file: parallel_serial_c.v\n`include "parallel_serial_c.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module phy_tx_c (
	input clk_32f,
	input clk_2f_c,
	input clk_4f_c,
	input reset,
	input valid_in,
	input [31:0] Data_in,
	output reg Data_out_1bit_0_c,
	output reg Data_out_1bit_1_c
);
	wire clk_32f;
	wire clk_2f_c;
	wire clk_4f_c;
	wire reset;
	wire valid_0_c;
	wire [31:0] lane_0_c;
	wire valid_1_c;
	wire [31:0] lane_1_c;
	wire valid_out_0_c;
	wire [7:0] Data_out_0_c;
	wire valid_out_1_c;
	wire [7:0] Data_out_1_c;
	wire Out_0_c;
	wire Out_1_c;

	always @(*) begin
		Data_out_1bit_0_c <= Out_0_c;
		Data_out_1bit_1_c <= Out_1_c;
	end

    byte_striping_c byte_striping_1(


				    .valid_0_c		(valid_0_c),
				    .lane_0_c		(lane_0_c[31:0]),
				    .valid_1_c		(valid_1_c),
				    .lane_1_c		(lane_1_c[31:0]),

				    .clk_2f_c		(clk_2f_c),
				    .reset		(reset),
				    .valid_in		(valid_in),
				    .Data_in		(Data_in[31:0]));
	
    word32_8bits_c word32_8bits_1(


				  .valid_out_c		(valid_out_0_c),
				  .Data_out_c		(Data_out_0_c[7:0]),

				  .clk_4f_c		(clk_4f_c),
				  .reset		(reset),
				  .valid_in		(valid_0_c),
				  .Data_in		(lane_0_c[31:0])); 

    word32_8bits_c word32_8bits_2(


				  .valid_out_c		(valid_out_1_c),
				  .Data_out_c		(Data_out_1_c[7:0]),

				  .clk_4f_c		(clk_4f_c),
				  .reset		(reset),
				  .valid_in		(valid_1_c),
				  .Data_in		(lane_1_c[31:0]));

    parallel_serial_c parallel_serial_c1 ( 


					  .Data_out_c		(Out_0_c),

					  .clk_32f		(clk_32f),
					  .reset		(reset),
					  .valid_in		(valid_out_0_c),
					  .Data_in		(Data_out_0_c[7:0]));

    parallel_serial_c parallel_serial_c2 (


					  .Data_out_c		(Out_1_c),

					  .clk_32f		(clk_32f),
					  .reset		(reset),
					  .valid_in		(valid_out_1_c),
					  .Data_in		(Data_out_1_c[7:0]));

	
endmodule
module phy_tx_c (
	input clk_32f,
	input clk_2f_c,
	input clk_4f_c,
	input reset,
	input valid_in,
	input [31:0] Data_in,
	output reg Data_out_1bit_0_c,
	output reg Data_out_1bit_1_c
);

	wire clk_32f;
	wire clk_2f_c;
	wire clk_4f_c;
	wire reset;
	wire valid_0_c;
	wire [31:0] lane_0_c;
	wire valid_1_c;
	wire [31:0] lane_1_c;
	wire valid_out_0_c;
	wire [7:0] Data_out_0_c;
	wire valid_out_1_c;
	wire [7:0] Data_out_1_c;
	wire Out_0_c;
	wire Out_1_c;

	always @(*) begin
		Data_out_1bit_0_c <= Out_0_c;
		Data_out_1bit_1_c <= Out_1_c;
	end

    byte_striping_c byte_striping_1(


				    .valid_0_c		(valid_0_c),
				    .lane_0_c		(lane_0_c[31:0]),
				    .valid_1_c		(valid_1_c),
				    .lane_1_c		(lane_1_c[31:0]),

				    .clk_2f_c		(clk_2f_c),
				    .reset		(reset),
				    .valid_in		(valid_in),
				    .Data_in		(Data_in[31:0]));
	
    word32_8bits_c word32_8bits_1(


				  .valid_out_c		(valid_out_0_c),
				  .Data_out_c		(Data_out_0_c[7:0]),

				  .clk_4f_c		(clk_4f_c),
				  .reset		(reset),
				  .valid_in		(valid_0_c),
				  .Data_in		(lane_0_c[31:0])); 

    word32_8bits_c word32_8bits_2(


				  .valid_out_c		(valid_out_1_c),
				  .Data_out_c		(Data_out_1_c[7:0]),

				  .clk_4f_c		(clk_4f_c),
				  .reset		(reset),
				  .valid_in		(valid_1_c),
				  .Data_in		(lane_1_c[31:0]));

    parallel_serial_c parallel_serial_c1 ( 


					  .Data_out_c		(Out_0_c),

					  .clk_32f		(clk_32f),
					  .reset		(reset),
					  .valid_in		(valid_out_0_c),
					  .Data_in		(Data_out_0_c[7:0]));

    parallel_serial_c parallel_serial_c2 (


					  .Data_out_c		(Out_1_c),

					  .clk_32f		(clk_32f),
					  .reset		(reset),
					  .valid_in		(valid_out_1_c),
					  .Data_in		(Data_out_1_c[7:0]));

	
endmodule