data/full_repos/permissive/52682338/Cartridge/aes_prog.v
1: b"%Error: data/full_repos/permissive/52682338/Cartridge/aes_prog.v:55: Cannot find file containing module: 'rom_p1'\n rom_p1 P1(M68K_ADDR[18:1], M68K_DATA, M68K_ADDR[19], nROMOE);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_p1\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_p1.v\n             data/full_repos/permissive/52682338/Cartridge,data/full_repos/permissive/52682338/rom_p1.sv\n             rom_p1\n             rom_p1.v\n             rom_p1.sv\n             obj_dir/rom_p1\n             obj_dir/rom_p1.v\n             obj_dir/rom_p1.sv\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_prog.v:60: Cannot find file containing module: 'rom_v1'\n rom_v1 V1(V1_ADDR[18:0], RAD, nROE);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/Cartridge/aes_prog.v:61: Cannot find file containing module: 'rom_v2'\n rom_v2 V2(V2_ADDR[18:0], PAD, nPOE);\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module aes_prog(
	input nPORTADRS,
	input PMPX, nSDPOE,
	input [11:8] PA,
	inout [7:0] PAD,
	input nRESET,
	input CLK_68KCLKB,
	input nPORTWEL, nPORTWEU,
	input nPORTOEL, nPORTOEU,
	input nROMOEL, nROMOEU,
	input nAS, M68K_RW,
	inout [15:0] M68K_DATA,
	input [19:1] M68K_ADDR,
	input nROMOE,
	output nROMWAIT, nPWAIT1, nPWAIT0, PDTACK,
	inout [7:0] RAD,
	input [9:8] RA_L,
	input [23:20] RA_U,
	input RMPX, nSDROE,
	input CLK_4MB
);


	reg [23:0] V1_ADDR;
	reg [23:0] V2_ADDR;
	

	
	assign nROMWAIT = 1'b1;
	assign nPWAIT0 = 1'b1;
	assign nPWAIT1 = 1'b1;
	assign PDTACK = 1'b1;
	


	
	rom_p1 P1(M68K_ADDR[18:1], M68K_DATA, M68K_ADDR[19], nROMOE);
	


	
	rom_v1 V1(V1_ADDR[18:0], RAD, nROE);
	rom_v2 V2(V2_ADDR[18:0], PAD, nPOE);
	
	

	always @(posedge RMPX)
		V1_ADDR[9:0] <= {RA_L[9:8], RAD};

	always @(negedge RMPX)
		V1_ADDR[23:10] <= {RA_U[23:20], RA_L[9:8], RAD};

	always @(posedge PMPX)
		V2_ADDR[11:0] <= {PA[11:8], PAD};
		
	always @(negedge PMPX)
		V2_ADDR[23:12] <= {PA[11:8], PAD};
	
endmodule
module aes_prog(
	input nPORTADRS,
	input PMPX, nSDPOE,
	input [11:8] PA,
	inout [7:0] PAD,
	input nRESET,
	input CLK_68KCLKB,
	input nPORTWEL, nPORTWEU,
	input nPORTOEL, nPORTOEU,
	input nROMOEL, nROMOEU,
	input nAS, M68K_RW,
	inout [15:0] M68K_DATA,
	input [19:1] M68K_ADDR,
	input nROMOE,
	output nROMWAIT, nPWAIT1, nPWAIT0, PDTACK,
	inout [7:0] RAD,
	input [9:8] RA_L,
	input [23:20] RA_U,
	input RMPX, nSDROE,
	input CLK_4MB
);



	reg [23:0] V1_ADDR;
	reg [23:0] V2_ADDR;
	

	
	assign nROMWAIT = 1'b1;
	assign nPWAIT0 = 1'b1;
	assign nPWAIT1 = 1'b1;
	assign PDTACK = 1'b1;
	


	
	rom_p1 P1(M68K_ADDR[18:1], M68K_DATA, M68K_ADDR[19], nROMOE);
	


	
	rom_v1 V1(V1_ADDR[18:0], RAD, nROE);
	rom_v2 V2(V2_ADDR[18:0], PAD, nPOE);
	
	

	always @(posedge RMPX)
		V1_ADDR[9:0] <= {RA_L[9:8], RAD};

	always @(negedge RMPX)
		V1_ADDR[23:10] <= {RA_U[23:20], RA_L[9:8], RAD};

	always @(posedge PMPX)
		V2_ADDR[11:0] <= {PA[11:8], PAD};
		
	always @(negedge PMPX)
		V2_ADDR[23:12] <= {PA[11:8], PAD};
	
endmodule