data/full_repos/permissive/443770883/lab3/d.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/443770883/lab3/d.v:39: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'nand2\'\nmodule nand2(input wire i0, i1, output wire o5);\n       ^~~~~\n                                                                   : ... Top module \'fulladdR\'\nmodule fulladdR(input wire [3:0] a, b, input wire cin, output wire [3:0] sum, output wire cout);\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module fulladdR(input wire [3:0] a, b, input wire cin, output wire [3:0] sum, output wire cout);


   wire [2:0] c;

	fulladd f1(a[0], b[0], cin, sum[0], c[0]);
	fulladd f2(a[1], b[1], c[0], sum[1], c[1]);
	fulladd f3(a[2], b[2], c[1], sum[2], c[2]);
	fulladd f4(a[3], b[3], c[2], sum[3], cout);


endmodule
module fulladdR(input wire [3:0] a, b, input wire cin, output wire [3:0] sum, output wire cout);



   wire [2:0] c;

	fulladd f1(a[0], b[0], cin, sum[0], c[0]);
	fulladd f2(a[1], b[1], c[0], sum[1], c[1]);
	fulladd f3(a[2], b[2], c[1], sum[2], c[2]);
	fulladd f4(a[3], b[3], c[2], sum[3], cout);


endmodule