data/full_repos/permissive/493019833/test/testcase/firrtl/SqDist/reference/SqDist.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SqDist/reference/SqDist.v:605: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                       : ... In instance SqDist.s_shr_98\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module SHR_SIGNED(y, in);
    parameter width = 4;
    parameter n = 2;
    output [(n < width ? (width-n-1) : 0):0] y;
    input [width-1:0] in;
    assign y = n < width ? in[width-1:n] : in[width-1:width-1];
endmodule
module SHR_SIGNED(y, in);

    parameter width = 4;
    parameter n = 2;
    output [(n < width ? (width-n-1) : 0):0] y;
    input [width-1:0] in;
    assign y = n < width ? in[width-1:n] : in[width-1:width-1];
endmodule