data/full_repos/permissive/484316383/rtl/common/timer8253.v
1: b'%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/timer8253.v:213: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                               : ... In instance timer_8253.counter2\n     end else if (gate) count <= count - 2\'d2; else mode[6] <= 1;\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module timer_8253(
	input CS,
	input WR,
	input [1:0]addr,
	input [7:0]din,
	output wire [7:0]dout,
	input CLK_25,
	input clk,
	input gate2,
	output out0,
	output out2,

	output reg dbg_wr,
	output reg [1:0] dbg_addr,
	output reg [7:0] dbg_din
	);
	 
	reg [8:0]rclk = 0;
	reg [1:0]cclk = 0;

	always @(posedge CLK_25) begin
		if(rclk[7:0] < 8'd208) rclk <= rclk + 8'd21;
		else rclk <= rclk + 8'd57;
	end
	
	always @ (posedge clk) begin
		cclk <= {cclk[0], rclk[8]};
	end

	always @(posedge clk)
		if (CS) begin
			dbg_wr <= WR;
			dbg_addr <= addr;
			if (WR) dbg_din <= din;
		end

	wire a0 = addr == 0;
	wire a2 = addr == 2;
	wire a3 = addr == 3;
	wire cmd0 = a3 && din[7:6] == 0;
	wire cmd2 = a3 && din[7:6] == 2;
	wire [7:0]dout0;
	wire [7:0]dout2;
	wire [7:0]mode0;
	wire [7:0]mode2;

	counter counter0 (
		.CS(CS && (a0 || cmd0)),
		.WR(WR),
		.clk(clk),
		.gate(1'b1),
		.cmd(cmd0),
		.din(din),
		.dout(dout0),
		.out(out0),
		.CE(cclk)
	);

	counter counter2 (
		.CS(CS && (a2 || cmd2)),
		.WR(WR),
		.clk(clk),
		.gate(gate2),
		.cmd(cmd2),
		.din(din),
		.dout(dout2),
		.out(out2),
		.CE(cclk)
	);

	assign dout = 	a0 ? dout0 : dout2;
	
endmodule
module timer_8253(
	input CS,
	input WR,
	input [1:0]addr,
	input [7:0]din,
	output wire [7:0]dout,
	input CLK_25,
	input clk,
	input gate2,
	output out0,
	output out2,

	output reg dbg_wr,
	output reg [1:0] dbg_addr,
	output reg [7:0] dbg_din
	);

	 
	reg [8:0]rclk = 0;
	reg [1:0]cclk = 0;

	always @(posedge CLK_25) begin
		if(rclk[7:0] < 8'd208) rclk <= rclk + 8'd21;
		else rclk <= rclk + 8'd57;
	end
	
	always @ (posedge clk) begin
		cclk <= {cclk[0], rclk[8]};
	end

	always @(posedge clk)
		if (CS) begin
			dbg_wr <= WR;
			dbg_addr <= addr;
			if (WR) dbg_din <= din;
		end

	wire a0 = addr == 0;
	wire a2 = addr == 2;
	wire a3 = addr == 3;
	wire cmd0 = a3 && din[7:6] == 0;
	wire cmd2 = a3 && din[7:6] == 2;
	wire [7:0]dout0;
	wire [7:0]dout2;
	wire [7:0]mode0;
	wire [7:0]mode2;

	counter counter0 (
		.CS(CS && (a0 || cmd0)),
		.WR(WR),
		.clk(clk),
		.gate(1'b1),
		.cmd(cmd0),
		.din(din),
		.dout(dout0),
		.out(out0),
		.CE(cclk)
	);

	counter counter2 (
		.CS(CS && (a2 || cmd2)),
		.WR(WR),
		.clk(clk),
		.gate(gate2),
		.cmd(cmd2),
		.din(din),
		.dout(dout2),
		.out(out2),
		.CE(cclk)
	);

	assign dout = 	a0 ? dout0 : dout2;
	
endmodule