data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n always  #1 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("updown.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #250;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/518306084/iiitb_bidicntr_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #128;\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_bidcntr_tb;
	reg clk,ctrl,reset;
	wire [3:0] count;
	iiitb_bidicntr counter(.clk(clk),.reset(reset),.ctrl(ctrl),.count(count));
	always  #1 clk=~clk;
	

	initial
		begin
		$dumpfile("updown.vcd");
		$dumpvars(0);

		clk = 0;
		reset=1;
		#4;
		reset=0;
		ctrl=0;
		#250;
		ctrl=1;
		#128;
		reset=1;
		$finish;
		end
endmodule
module iiitb_bidcntr_tb;

	reg clk,ctrl,reset;
	wire [3:0] count;
	iiitb_bidicntr counter(.clk(clk),.reset(reset),.ctrl(ctrl),.count(count));
	always  #1 clk=~clk;
	

	initial
		begin
		$dumpfile("updown.vcd");
		$dumpvars(0);

		clk = 0;
		reset=1;
		#4;
		reset=0;
		ctrl=0;
		#250;
		ctrl=1;
		#128;
		reset=1;
		$finish;
		end
endmodule