data/full_repos/permissive/508059792/signextend.v
data/verilator_xmls/f3f3f44e-e680-47b5-aaa8-634c1c917bdc.xml
module signextend (out,  in ) ;
    
    output [31 : 0]  out;
    input [15 : 0]  in ;
    
    assign out ={{16 {in [ 15 ]}},in};
endmodule
module signextend (out,  in ) ;

    
    output [31 : 0]  out;
    input [15 : 0]  in ;
    
    assign out ={{16 {in [ 15 ]}},in};
endmodule