data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v
1: b'%Error: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:7: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("iiitb_sqd_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:8: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0);\n^~~~~~~~~\n%Error: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:10: Unsupported or unknown PLI call: $monitor\n$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);\n^~~~~~~~\n%Error: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:10: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n#10 din=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 din=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10 din=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#10 din=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#10 din=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10 din=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10 din=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10 din=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 din=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=~clk;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521269333/iiitb_sqd_1010_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#80 $finish ;\n^\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_sqd_1010_tb;
reg din,clk,reset;
wire y;
iiitb_sqd_1010 m1(din, reset, clk, y);
initial
begin
$dumpfile("iiitb_sqd_tb.vcd");
$dumpvars(0);
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#5 din=1;



end
always
#5 clk=~clk;
initial
#80 $finish ;
endmodule
module iiitb_sqd_1010_tb;

reg din,clk,reset;
wire y;
iiitb_sqd_1010 m1(din, reset, clk, y);
initial
begin
$dumpfile("iiitb_sqd_tb.vcd");
$dumpvars(0);
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#5 din=1;



end
always
#5 clk=~clk;
initial
#80 $finish ;
endmodule