data/full_repos/permissive/503973366/SIM/fifov2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:61: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:65: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:72: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:78: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:85: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:90: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:97: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:101: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:107: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:115: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifov2_tb.v:122: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 11 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO_v2_TB #(

    parameter DATA_WIDTH = 8,
    parameter FIFO_DEPTH = 6
    )
    (


    );
    reg     clk;
    reg     rst_n;
    reg     wren_i;
    reg     rden_i;
    
    wire    full_o;
    wire    empty_o;
    
    reg     [DATA_WIDTH-1:0] wdata_i;
    wire    [DATA_WIDTH-1:0] rdata_o;
    
    

    FIFO_v2 #(
        .DATA_WIDTH ( DATA_WIDTH ),
        .FIFO_DEPTH ( FIFO_DEPTH )
    )u_FIFO_v2(
        .clk        ( clk        ),
        .rst_n      ( rst_n      ),
        .wren_i     ( wren_i     ),
        .rden_i     ( rden_i     ),
        .full_o     ( full_o     ),
        .empty_o    ( empty_o    ),
        .wdata_i    ( wdata_i    ),
        .rdata_o    ( rdata_o    )
    );



    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;


    initial begin

        rst_n = 1'b1;
        wren_i = 1'b0;
        rden_i = 1'b0;
        wdata_i = {(DATA_WIDTH){1'b0}};
    

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        
        

        for (i=0; i < FIFO_DEPTH+2; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            wdata_i = i;
        end

        @(posedge clk);
        #(`DELTA)
        wren_i = 1'b0;    
        
        

        for (i=0; i < FIFO_DEPTH+2; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            rden_i = 1'b1;
        end

        @(posedge clk);
        #(`DELTA)
        rden_i = 1'b0;
            

        

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        

        for (i=0; i < FIFO_DEPTH; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            wdata_i = i;
        end
        

        for (i=0; i < FIFO_DEPTH; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            rden_i = 1'b1;
            wdata_i = i+10;
        end
        
        @(posedge clk);
        @(`DELTA)
        wren_i = 1'b0;
        rden_i = 1'b0;
        wdata_i = 'd0;
    end
    
    endmodule
module FIFO_v2_TB #(

    parameter DATA_WIDTH = 8,
    parameter FIFO_DEPTH = 6
    )
    (


    );

    reg     clk;
    reg     rst_n;
    reg     wren_i;
    reg     rden_i;
    
    wire    full_o;
    wire    empty_o;
    
    reg     [DATA_WIDTH-1:0] wdata_i;
    wire    [DATA_WIDTH-1:0] rdata_o;
    
    

    FIFO_v2 #(
        .DATA_WIDTH ( DATA_WIDTH ),
        .FIFO_DEPTH ( FIFO_DEPTH )
    )u_FIFO_v2(
        .clk        ( clk        ),
        .rst_n      ( rst_n      ),
        .wren_i     ( wren_i     ),
        .rden_i     ( rden_i     ),
        .full_o     ( full_o     ),
        .empty_o    ( empty_o    ),
        .wdata_i    ( wdata_i    ),
        .rdata_o    ( rdata_o    )
    );



    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;


    initial begin

        rst_n = 1'b1;
        wren_i = 1'b0;
        rden_i = 1'b0;
        wdata_i = {(DATA_WIDTH){1'b0}};
    

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        
        

        for (i=0; i < FIFO_DEPTH+2; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            wdata_i = i;
        end

        @(posedge clk);
        #(`DELTA)
        wren_i = 1'b0;    
        
        

        for (i=0; i < FIFO_DEPTH+2; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            rden_i = 1'b1;
        end

        @(posedge clk);
        #(`DELTA)
        rden_i = 1'b0;
            

        

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        

        for (i=0; i < FIFO_DEPTH; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            wdata_i = i;
        end
        

        for (i=0; i < FIFO_DEPTH; i=i+1) begin
            @(posedge clk);
            #(`DELTA)
            wren_i = 1'b1;
            rden_i = 1'b1;
            wdata_i = i+10;
        end
        
        @(posedge clk);
        @(`DELTA)
        wren_i = 1'b0;
        rden_i = 1'b0;
        wdata_i = 'd0;
    end
    
    endmodule