data/full_repos/permissive/485189979/ledBlink/clock_divider.v
data/verilator_xmls/4f3ff6b5-2cbe-4bdf-b420-70bc56efacfe.xml
module clock_divider(
  input wire clk,
  output reg divided_clk = 0
  );


localparam div_value = 99999999;
integer counter_value = 0;

always@ (posedge clk)
begin
  if (counter_value == div_value)
    counter_value <= 0;
  else
    counter_value <= counter_value + 1; 
end


always@ (posedge clk)
begin  
  if (counter_value == div_value)
    divided_clk <= ~divided_clk;
end

endmodule
module clock_divider(
  input wire clk,
  output reg divided_clk = 0
  );



localparam div_value = 99999999;
integer counter_value = 0;

always@ (posedge clk)
begin
  if (counter_value == div_value)
    counter_value <= 0;
  else
    counter_value <= counter_value + 1; 
end


always@ (posedge clk)
begin  
  if (counter_value == div_value)
    divided_clk <= ~divided_clk;
end

endmodule