data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v:139: Cannot find file containing module: 'NV_NVDLA_SDP_MRDMA_gate'\n NV_NVDLA_SDP_MRDMA_gate u_gate (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_MRDMA_gate\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_MRDMA_gate.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp,data/full_repos/permissive/509468557/NV_NVDLA_SDP_MRDMA_gate.sv\n             NV_NVDLA_SDP_MRDMA_gate\n             NV_NVDLA_SDP_MRDMA_gate.v\n             NV_NVDLA_SDP_MRDMA_gate.sv\n             obj_dir/NV_NVDLA_SDP_MRDMA_gate\n             obj_dir/NV_NVDLA_SDP_MRDMA_gate.v\n             obj_dir/NV_NVDLA_SDP_MRDMA_gate.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v:152: Cannot find file containing module: 'NV_NVDLA_SDP_MRDMA_ig'\n NV_NVDLA_SDP_MRDMA_ig u_ig (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v:182: Cannot find file containing module: 'NV_NVDLA_SDP_MRDMA_cq'\n NV_NVDLA_SDP_MRDMA_cq u_cq (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v:196: Cannot find file containing module: 'NV_NVDLA_SDP_MRDMA_eg'\n NV_NVDLA_SDP_MRDMA_eg u_eg (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module NV_NVDLA_SDP_mrdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,mrdma_disable
  ,mrdma_slcg_op_en
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_channel
  ,reg2dp_height
  ,reg2dp_in_precision
  ,reg2dp_op_en
  ,reg2dp_perf_dma_en
  ,reg2dp_perf_nan_inf_count_en
  ,reg2dp_proc_precision
  ,reg2dp_src_base_addr_high
  ,reg2dp_src_base_addr_low
  ,reg2dp_src_line_stride
  ,reg2dp_src_ram_type
  ,reg2dp_src_surface_stride
  ,reg2dp_width
  ,sdp2cvif_rd_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp_mrdma2cmux_ready
  ,tmc2slcg_disable_clock_gating
  ,cvif2sdp_rd_rsp_ready
  ,dp2reg_done
  ,dp2reg_mrdma_stall
  ,dp2reg_status_inf_input_num
  ,dp2reg_status_nan_input_num
  ,mcif2sdp_rd_rsp_ready
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp_mrdma2cmux_pd
  ,sdp_mrdma2cmux_valid
  );



 input  nvdla_core_clk;
 input  nvdla_core_rstn;

 input          cvif2sdp_rd_rsp_valid;
 output         cvif2sdp_rd_rsp_ready;
 input  [513:0] cvif2sdp_rd_rsp_pd;

 input          mcif2sdp_rd_rsp_valid;
 output         mcif2sdp_rd_rsp_ready;
 input  [513:0] mcif2sdp_rd_rsp_pd;

 input [31:0] pwrbus_ram_pd;

 output  sdp2cvif_rd_cdt_lat_fifo_pop;

 output        sdp2cvif_rd_req_valid;
 input         sdp2cvif_rd_req_ready;
 output [78:0] sdp2cvif_rd_req_pd;

 output  sdp2mcif_rd_cdt_lat_fifo_pop;

 output        sdp2mcif_rd_req_valid;
 input         sdp2mcif_rd_req_ready;
 output [78:0] sdp2mcif_rd_req_pd;

 output         sdp_mrdma2cmux_valid;
 input          sdp_mrdma2cmux_ready;
 output [513:0] sdp_mrdma2cmux_pd;

 input   [4:0] reg2dp_batch_number;
 input  [12:0] reg2dp_channel;
 input  [12:0] reg2dp_height;
 input   [1:0] reg2dp_in_precision;
 input         reg2dp_op_en;
 input         reg2dp_perf_dma_en;
 input         reg2dp_perf_nan_inf_count_en;
 input   [1:0] reg2dp_proc_precision;
 input  [31:0] reg2dp_src_base_addr_high;
 input  [26:0] reg2dp_src_base_addr_low;
 input  [26:0] reg2dp_src_line_stride;
 input         reg2dp_src_ram_type;
 input  [26:0] reg2dp_src_surface_stride;
 input  [12:0] reg2dp_width;
 output        dp2reg_done;
 output [31:0] dp2reg_mrdma_stall;
 output [31:0] dp2reg_status_inf_input_num;
 output [31:0] dp2reg_status_nan_input_num;
 input         dla_clk_ovr_on_sync;
 input         global_clk_ovr_on_sync;
 input         tmc2slcg_disable_clock_gating;
 input         mrdma_disable;
 input         mrdma_slcg_op_en;
 reg           layer_process;
 wire   [13:0] cq2eg_pd;
 wire          cq2eg_prdy;
 wire          cq2eg_pvld;
 wire          eg_done;
 wire   [13:0] ig2cq_pd;
 wire          ig2cq_prdy;
 wire          ig2cq_pvld;
 wire          nvdla_gated_clk;
 wire          op_load;




assign op_load = reg2dp_op_en & ~layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    layer_process <= 1'b0;
  end else begin
    if (op_load) begin
        layer_process <= 1'b1;
    end else if (eg_done) begin
        layer_process <= 1'b0;
    end
  end
end
assign dp2reg_done = eg_done;

 NV_NVDLA_SDP_MRDMA_gate u_gate (
    .nvdla_core_clk                (nvdla_core_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
   ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
   ,.mrdma_disable                 (mrdma_disable)
   ,.mrdma_slcg_op_en              (mrdma_slcg_op_en)
   ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
   ,.nvdla_gated_clk               (nvdla_gated_clk)
   );



 NV_NVDLA_SDP_MRDMA_ig u_ig (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.sdp2mcif_rd_req_valid         (sdp2mcif_rd_req_valid)
   ,.sdp2mcif_rd_req_ready         (sdp2mcif_rd_req_ready)
   ,.sdp2mcif_rd_req_pd            (sdp2mcif_rd_req_pd[78:0])
   ,.sdp2cvif_rd_req_valid         (sdp2cvif_rd_req_valid)
   ,.sdp2cvif_rd_req_ready         (sdp2cvif_rd_req_ready)
   ,.sdp2cvif_rd_req_pd            (sdp2cvif_rd_req_pd[78:0])
   ,.ig2cq_pvld                    (ig2cq_pvld)
   ,.ig2cq_prdy                    (ig2cq_prdy)
   ,.ig2cq_pd                      (ig2cq_pd[13:0])
   ,.op_load                       (op_load)
   ,.reg2dp_batch_number           (reg2dp_batch_number[4:0])
   ,.reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
   ,.reg2dp_perf_dma_en            (reg2dp_perf_dma_en)
   ,.reg2dp_proc_precision         (reg2dp_proc_precision[1:0])
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_mrdma_stall            (dp2reg_mrdma_stall[31:0])
   );



 NV_NVDLA_SDP_MRDMA_cq u_cq (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.ig2cq_prdy                    (ig2cq_prdy)
   ,.ig2cq_pvld                    (ig2cq_pvld)
   ,.ig2cq_pd                      (ig2cq_pd[13:0])
   ,.cq2eg_prdy                    (cq2eg_prdy)
   ,.cq2eg_pvld                    (cq2eg_pvld)
   ,.cq2eg_pd                      (cq2eg_pd[13:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );



 NV_NVDLA_SDP_MRDMA_eg u_eg (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cq2eg_pvld                    (cq2eg_pvld)
   ,.cq2eg_prdy                    (cq2eg_prdy)
   ,.cq2eg_pd                      (cq2eg_pd[13:0])
   ,.cvif2sdp_rd_rsp_valid         (cvif2sdp_rd_rsp_valid)
   ,.cvif2sdp_rd_rsp_ready         (cvif2sdp_rd_rsp_ready)
   ,.cvif2sdp_rd_rsp_pd            (cvif2sdp_rd_rsp_pd[513:0])
   ,.mcif2sdp_rd_rsp_valid         (mcif2sdp_rd_rsp_valid)
   ,.mcif2sdp_rd_rsp_ready         (mcif2sdp_rd_rsp_ready)
   ,.mcif2sdp_rd_rsp_pd            (mcif2sdp_rd_rsp_pd[513:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   ,.sdp2cvif_rd_cdt_lat_fifo_pop  (sdp2cvif_rd_cdt_lat_fifo_pop)
   ,.sdp2mcif_rd_cdt_lat_fifo_pop  (sdp2mcif_rd_cdt_lat_fifo_pop)
   ,.sdp_mrdma2cmux_valid          (sdp_mrdma2cmux_valid)
   ,.sdp_mrdma2cmux_ready          (sdp_mrdma2cmux_ready)
   ,.sdp_mrdma2cmux_pd             (sdp_mrdma2cmux_pd[513:0])
   ,.op_load                       (op_load)
   ,.eg_done                       (eg_done)
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
   ,.reg2dp_perf_nan_inf_count_en  (reg2dp_perf_nan_inf_count_en)
   ,.reg2dp_proc_precision         (reg2dp_proc_precision[1:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_status_inf_input_num   (dp2reg_status_inf_input_num[31:0])
   ,.dp2reg_status_nan_input_num   (dp2reg_status_nan_input_num[31:0])
   );
 
endmodule
module NV_NVDLA_SDP_mrdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,mrdma_disable
  ,mrdma_slcg_op_en
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_channel
  ,reg2dp_height
  ,reg2dp_in_precision
  ,reg2dp_op_en
  ,reg2dp_perf_dma_en
  ,reg2dp_perf_nan_inf_count_en
  ,reg2dp_proc_precision
  ,reg2dp_src_base_addr_high
  ,reg2dp_src_base_addr_low
  ,reg2dp_src_line_stride
  ,reg2dp_src_ram_type
  ,reg2dp_src_surface_stride
  ,reg2dp_width
  ,sdp2cvif_rd_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp_mrdma2cmux_ready
  ,tmc2slcg_disable_clock_gating
  ,cvif2sdp_rd_rsp_ready
  ,dp2reg_done
  ,dp2reg_mrdma_stall
  ,dp2reg_status_inf_input_num
  ,dp2reg_status_nan_input_num
  ,mcif2sdp_rd_rsp_ready
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp_mrdma2cmux_pd
  ,sdp_mrdma2cmux_valid
  );




 input  nvdla_core_clk;
 input  nvdla_core_rstn;

 input          cvif2sdp_rd_rsp_valid;
 output         cvif2sdp_rd_rsp_ready;
 input  [513:0] cvif2sdp_rd_rsp_pd;

 input          mcif2sdp_rd_rsp_valid;
 output         mcif2sdp_rd_rsp_ready;
 input  [513:0] mcif2sdp_rd_rsp_pd;

 input [31:0] pwrbus_ram_pd;

 output  sdp2cvif_rd_cdt_lat_fifo_pop;

 output        sdp2cvif_rd_req_valid;
 input         sdp2cvif_rd_req_ready;
 output [78:0] sdp2cvif_rd_req_pd;

 output  sdp2mcif_rd_cdt_lat_fifo_pop;

 output        sdp2mcif_rd_req_valid;
 input         sdp2mcif_rd_req_ready;
 output [78:0] sdp2mcif_rd_req_pd;

 output         sdp_mrdma2cmux_valid;
 input          sdp_mrdma2cmux_ready;
 output [513:0] sdp_mrdma2cmux_pd;

 input   [4:0] reg2dp_batch_number;
 input  [12:0] reg2dp_channel;
 input  [12:0] reg2dp_height;
 input   [1:0] reg2dp_in_precision;
 input         reg2dp_op_en;
 input         reg2dp_perf_dma_en;
 input         reg2dp_perf_nan_inf_count_en;
 input   [1:0] reg2dp_proc_precision;
 input  [31:0] reg2dp_src_base_addr_high;
 input  [26:0] reg2dp_src_base_addr_low;
 input  [26:0] reg2dp_src_line_stride;
 input         reg2dp_src_ram_type;
 input  [26:0] reg2dp_src_surface_stride;
 input  [12:0] reg2dp_width;
 output        dp2reg_done;
 output [31:0] dp2reg_mrdma_stall;
 output [31:0] dp2reg_status_inf_input_num;
 output [31:0] dp2reg_status_nan_input_num;
 input         dla_clk_ovr_on_sync;
 input         global_clk_ovr_on_sync;
 input         tmc2slcg_disable_clock_gating;
 input         mrdma_disable;
 input         mrdma_slcg_op_en;
 reg           layer_process;
 wire   [13:0] cq2eg_pd;
 wire          cq2eg_prdy;
 wire          cq2eg_pvld;
 wire          eg_done;
 wire   [13:0] ig2cq_pd;
 wire          ig2cq_prdy;
 wire          ig2cq_pvld;
 wire          nvdla_gated_clk;
 wire          op_load;




assign op_load = reg2dp_op_en & ~layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    layer_process <= 1'b0;
  end else begin
    if (op_load) begin
        layer_process <= 1'b1;
    end else if (eg_done) begin
        layer_process <= 1'b0;
    end
  end
end
assign dp2reg_done = eg_done;

 NV_NVDLA_SDP_MRDMA_gate u_gate (
    .nvdla_core_clk                (nvdla_core_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
   ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
   ,.mrdma_disable                 (mrdma_disable)
   ,.mrdma_slcg_op_en              (mrdma_slcg_op_en)
   ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
   ,.nvdla_gated_clk               (nvdla_gated_clk)
   );



 NV_NVDLA_SDP_MRDMA_ig u_ig (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.sdp2mcif_rd_req_valid         (sdp2mcif_rd_req_valid)
   ,.sdp2mcif_rd_req_ready         (sdp2mcif_rd_req_ready)
   ,.sdp2mcif_rd_req_pd            (sdp2mcif_rd_req_pd[78:0])
   ,.sdp2cvif_rd_req_valid         (sdp2cvif_rd_req_valid)
   ,.sdp2cvif_rd_req_ready         (sdp2cvif_rd_req_ready)
   ,.sdp2cvif_rd_req_pd            (sdp2cvif_rd_req_pd[78:0])
   ,.ig2cq_pvld                    (ig2cq_pvld)
   ,.ig2cq_prdy                    (ig2cq_prdy)
   ,.ig2cq_pd                      (ig2cq_pd[13:0])
   ,.op_load                       (op_load)
   ,.reg2dp_batch_number           (reg2dp_batch_number[4:0])
   ,.reg2dp_channel                (reg2dp_channel[12:0])
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
   ,.reg2dp_perf_dma_en            (reg2dp_perf_dma_en)
   ,.reg2dp_proc_precision         (reg2dp_proc_precision[1:0])
   ,.reg2dp_src_base_addr_high     (reg2dp_src_base_addr_high[31:0])
   ,.reg2dp_src_base_addr_low      (reg2dp_src_base_addr_low[26:0])
   ,.reg2dp_src_line_stride        (reg2dp_src_line_stride[26:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_src_surface_stride     (reg2dp_src_surface_stride[26:0])
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_mrdma_stall            (dp2reg_mrdma_stall[31:0])
   );



 NV_NVDLA_SDP_MRDMA_cq u_cq (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.ig2cq_prdy                    (ig2cq_prdy)
   ,.ig2cq_pvld                    (ig2cq_pvld)
   ,.ig2cq_pd                      (ig2cq_pd[13:0])
   ,.cq2eg_prdy                    (cq2eg_prdy)
   ,.cq2eg_pvld                    (cq2eg_pvld)
   ,.cq2eg_pd                      (cq2eg_pd[13:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   );



 NV_NVDLA_SDP_MRDMA_eg u_eg (
    .nvdla_core_clk                (nvdla_gated_clk)
   ,.nvdla_core_rstn               (nvdla_core_rstn)
   ,.cq2eg_pvld                    (cq2eg_pvld)
   ,.cq2eg_prdy                    (cq2eg_prdy)
   ,.cq2eg_pd                      (cq2eg_pd[13:0])
   ,.cvif2sdp_rd_rsp_valid         (cvif2sdp_rd_rsp_valid)
   ,.cvif2sdp_rd_rsp_ready         (cvif2sdp_rd_rsp_ready)
   ,.cvif2sdp_rd_rsp_pd            (cvif2sdp_rd_rsp_pd[513:0])
   ,.mcif2sdp_rd_rsp_valid         (mcif2sdp_rd_rsp_valid)
   ,.mcif2sdp_rd_rsp_ready         (mcif2sdp_rd_rsp_ready)
   ,.mcif2sdp_rd_rsp_pd            (mcif2sdp_rd_rsp_pd[513:0])
   ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
   ,.sdp2cvif_rd_cdt_lat_fifo_pop  (sdp2cvif_rd_cdt_lat_fifo_pop)
   ,.sdp2mcif_rd_cdt_lat_fifo_pop  (sdp2mcif_rd_cdt_lat_fifo_pop)
   ,.sdp_mrdma2cmux_valid          (sdp_mrdma2cmux_valid)
   ,.sdp_mrdma2cmux_ready          (sdp_mrdma2cmux_ready)
   ,.sdp_mrdma2cmux_pd             (sdp_mrdma2cmux_pd[513:0])
   ,.op_load                       (op_load)
   ,.eg_done                       (eg_done)
   ,.reg2dp_height                 (reg2dp_height[12:0])
   ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
   ,.reg2dp_perf_nan_inf_count_en  (reg2dp_perf_nan_inf_count_en)
   ,.reg2dp_proc_precision         (reg2dp_proc_precision[1:0])
   ,.reg2dp_src_ram_type           (reg2dp_src_ram_type)
   ,.reg2dp_width                  (reg2dp_width[12:0])
   ,.dp2reg_status_inf_input_num   (dp2reg_status_inf_input_num[31:0])
   ,.dp2reg_status_nan_input_num   (dp2reg_status_nan_input_num[31:0])
   );
 
endmodule