data/full_repos/permissive/472097485/Chu03/Bcd_00/DispHexMux.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/Bcd_00/DispHexMux.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                 : ... In instance DispHexMux\n     hex_in = 3\'b000;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/Bcd_00/DispHexMux.v:39: Operator CASE expects 3 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n                                                                                 : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/Bcd_00/DispHexMux.v:39: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                 : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu03/Bcd_00/DispHexMux.v:39: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                 : ... In instance DispHexMux\n      case (q_reg[N-1:N-2])\n      ^~~~\n%Error: Exiting due to 4 warning(s)\n'
module DispHexMux
   (
    input wire clk, reset,
    input wire [3:0] hex2, hex1, hex0,
    input wire [2:0] dp_in,
	 input wire [2:0] en_in,
    output reg [2:0] an,
    output reg [7:0] sseg
   );



   localparam N = 18;

   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;
   reg [3:0] hex_in;
   reg dp;
	reg en;



   always @(posedge clk, posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         3'b00:
            begin
               an =  3'b110;
               hex_in = hex0;
               dp = dp_in[0];
					en = en_in[0];
            end
         2'b01:
            begin
               an =  3'b101;
               hex_in = hex1;
               dp = dp_in[1];
					en = en_in[1];
            end
         2'b10:
            begin
               an =  3'b011;
               hex_in = hex2;
               dp = dp_in[2];
					en = en_in[2];
            end
         default:
				begin
					hex_in = 3'b000;
					dp = 1'b0;
					en = 1'b0;
					an = 3'b111;
				end
       endcase


   always @*
   begin
		if( en )
			case(hex_in)
				4'h0: sseg[6:0] = 7'b0000001;
				4'h1: sseg[6:0] = 7'b1001111;
				4'h2: sseg[6:0] = 7'b0010010;
				4'h3: sseg[6:0] = 7'b0000110;
				4'h4: sseg[6:0] = 7'b1001100;
				4'h5: sseg[6:0] = 7'b0100100;
				4'h6: sseg[6:0] = 7'b0100000;
				4'h7: sseg[6:0] = 7'b0001111;
				4'h8: sseg[6:0] = 7'b0000000;
				4'h9: sseg[6:0] = 7'b0000100;
				4'ha: sseg[6:0] = 7'b0001000;
				4'hb: sseg[6:0] = 7'b1100000;
				4'hc: sseg[6:0] = 7'b0110001;
				4'hd: sseg[6:0] = 7'b1000010;
				4'he: sseg[6:0] = 7'b0110000;
				default: sseg[6:0] = 7'b0111000;
		  endcase
		else
			sseg[6:0] = 7'b1111111;
      sseg[7] = ~dp;
   end

endmodule
module DispHexMux
   (
    input wire clk, reset,
    input wire [3:0] hex2, hex1, hex0,
    input wire [2:0] dp_in,
	 input wire [2:0] en_in,
    output reg [2:0] an,
    output reg [7:0] sseg
   );




   localparam N = 18;

   reg [N-1:0] q_reg;
   wire [N-1:0] q_next;
   reg [3:0] hex_in;
   reg dp;
	reg en;



   always @(posedge clk, posedge reset)
      if (reset)
         q_reg <= 0;
      else
         q_reg <= q_next;


   assign q_next = q_reg + 1;



   always @*
      case (q_reg[N-1:N-2])
         3'b00:
            begin
               an =  3'b110;
               hex_in = hex0;
               dp = dp_in[0];
					en = en_in[0];
            end
         2'b01:
            begin
               an =  3'b101;
               hex_in = hex1;
               dp = dp_in[1];
					en = en_in[1];
            end
         2'b10:
            begin
               an =  3'b011;
               hex_in = hex2;
               dp = dp_in[2];
					en = en_in[2];
            end
         default:
				begin
					hex_in = 3'b000;
					dp = 1'b0;
					en = 1'b0;
					an = 3'b111;
				end
       endcase


   always @*
   begin
		if( en )
			case(hex_in)
				4'h0: sseg[6:0] = 7'b0000001;
				4'h1: sseg[6:0] = 7'b1001111;
				4'h2: sseg[6:0] = 7'b0010010;
				4'h3: sseg[6:0] = 7'b0000110;
				4'h4: sseg[6:0] = 7'b1001100;
				4'h5: sseg[6:0] = 7'b0100100;
				4'h6: sseg[6:0] = 7'b0100000;
				4'h7: sseg[6:0] = 7'b0001111;
				4'h8: sseg[6:0] = 7'b0000000;
				4'h9: sseg[6:0] = 7'b0000100;
				4'ha: sseg[6:0] = 7'b0001000;
				4'hb: sseg[6:0] = 7'b1100000;
				4'hc: sseg[6:0] = 7'b0110001;
				4'hd: sseg[6:0] = 7'b1000010;
				4'he: sseg[6:0] = 7'b0110000;
				default: sseg[6:0] = 7'b0111000;
		  endcase
		else
			sseg[6:0] = 7'b1111111;
      sseg[7] = ~dp;
   end

endmodule