data/full_repos/permissive/452721391/03/slowclktest.v
data/verilator_xmls/d3b1a15f-8584-45cc-a2ea-b7c3cdc61fc1.xml
module slowclktest (
input wire clk50,
output reg clkout
    );
localparam div_value = 499999999;


integer counter_value = 0;

always@ (posedge clk50)
begin
    if (counter_value == div_value)
        counter_value <= 0;
    else
        counter_value <= counter_value+1;
end


always@ (posedge clk50)
begin
    if(counter_value == div_value)
        clkout <= ~clkout;
    
end
endmodule
module slowclktest (
input wire clk50,
output reg clkout
    );

localparam div_value = 499999999;


integer counter_value = 0;

always@ (posedge clk50)
begin
    if (counter_value == div_value)
        counter_value <= 0;
    else
        counter_value <= counter_value+1;
end


always@ (posedge clk50)
begin
    if(counter_value == div_value)
        clkout <= ~clkout;
    
end
endmodule