data/full_repos/permissive/42414927/memory/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42414927/memory/testbench.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42414927/memory/testbench.v:31: Cannot find file containing module: \'fetch\'\n fetch  test_fetch(.clk(clk), \n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/fetch\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/fetch.v\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/fetch.sv\n             fetch\n             fetch.v\n             fetch.sv\n             obj_dir/fetch\n             obj_dir/fetch.v\n             obj_dir/fetch.sv\n%Error: data/full_repos/permissive/42414927/memory/testbench.v:39: Cannot find file containing module: \'mips_memory2\'\n mips_memory2    test_memory(.clk(clk), \n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ();
	
	parameter START_ADDR = 32'h80020000;


	reg   [31:0]	test_counter;	


	reg 		clk;


	reg		stall;
	reg		reset;


	wire   [31:0]	addr;	
	reg		rw;
	wire   [1:0]	access_size;
	wire		enable;


	reg   [31:0]	din;


	wire		busy;


	wire  [31:0]	dout;


	fetch		test_fetch(.clk(clk), 
				   .stall(stall), 
				   .reset(reset), 
				   .pc(addr), 
				   .rw(), 
				   .access_size(access_size), 
				   .enable(enable));

	mips_memory2    test_memory(.clk(clk), 
			            .addr(addr), 
			            .din(din), 
			            .dout(dout), 
			            .access_size(access_size), 
			            .rw(rw), 
			            .busy(busy), 
			            .enable(enable));



	reg    [7:0]  mem[0:256];

	initial
	begin
		clk = 1'b1;

		test_counter = 0;

		stall = 0;
		reset = 0;

		rw = 1;
		
		din =  32'b0000_0000;

		$readmemh("SumArray.x", mem);
	end

	

	always @(posedge clk)
	begin
		if (test_counter <= 2)
		begin
			test_counter <= test_counter + 1;
			reset <= 1;
			din <= 'x;
			$display("1");
		end
		else if (test_counter > 2 && test_counter <= 15)
		begin
			test_counter <= test_counter + 1;
			reset <= 0;			
			din[31:24] = mem[addr - START_ADDR];
			din[23:16] = mem[addr + 1 - START_ADDR];
			din[15:8] = mem[addr + 2 - START_ADDR];
			din[7:0] = mem[addr + 3 - START_ADDR];
			$display("2");
		end
		else
		begin
			test_counter <= 0;
			reset <= 1;
			din <= 'x;
			rw <= !rw;
			$display("3");
		end
	end

	always
		#5 clk = !clk;

endmodule
module testbench ();

	
	parameter START_ADDR = 32'h80020000;


	reg   [31:0]	test_counter;	


	reg 		clk;


	reg		stall;
	reg		reset;


	wire   [31:0]	addr;	
	reg		rw;
	wire   [1:0]	access_size;
	wire		enable;


	reg   [31:0]	din;


	wire		busy;


	wire  [31:0]	dout;


	fetch		test_fetch(.clk(clk), 
				   .stall(stall), 
				   .reset(reset), 
				   .pc(addr), 
				   .rw(), 
				   .access_size(access_size), 
				   .enable(enable));

	mips_memory2    test_memory(.clk(clk), 
			            .addr(addr), 
			            .din(din), 
			            .dout(dout), 
			            .access_size(access_size), 
			            .rw(rw), 
			            .busy(busy), 
			            .enable(enable));



	reg    [7:0]  mem[0:256];

	initial
	begin
		clk = 1'b1;

		test_counter = 0;

		stall = 0;
		reset = 0;

		rw = 1;
		
		din =  32'b0000_0000;

		$readmemh("SumArray.x", mem);
	end

	

	always @(posedge clk)
	begin
		if (test_counter <= 2)
		begin
			test_counter <= test_counter + 1;
			reset <= 1;
			din <= 'x;
			$display("1");
		end
		else if (test_counter > 2 && test_counter <= 15)
		begin
			test_counter <= test_counter + 1;
			reset <= 0;			
			din[31:24] = mem[addr - START_ADDR];
			din[23:16] = mem[addr + 1 - START_ADDR];
			din[15:8] = mem[addr + 2 - START_ADDR];
			din[7:0] = mem[addr + 3 - START_ADDR];
			$display("2");
		end
		else
		begin
			test_counter <= 0;
			reset <= 1;
			din <= 'x;
			rw <= !rw;
			$display("3");
		end
	end

	always
		#5 clk = !clk;

endmodule