data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module shift_right #(parameter WIDTH=32, LOGWIDTH=$clog2(WIDTH) ) (
	input  wire [WIDTH-1:0]     a, 
	output wire [WIDTH-1:0]     r, 
	input  wire [LOGWIDTH-1:0]  shamt, 
	input                       ar
);

    wire [WIDTH-1:0] row[LOGWIDTH:0];
    
    wire fill = ar ? a[WIDTH-1] : 1'b0;
    
    assign row[0] = a;
    assign r = row[LOGWIDTH];

    generate
        genvar i; 
        for(i=0; i<LOGWIDTH; i=i+1) 
            assign row[i+1] = shamt[i] ? { { (2**i) {fill} }, row[i][WIDTH-1:(2**i)] } : row[i];
    endgenerate

endmodule
module shift_right #(parameter WIDTH=32, LOGWIDTH=$clog2(WIDTH) ) (
	input  wire [WIDTH-1:0]     a, 
	output wire [WIDTH-1:0]     r, 
	input  wire [LOGWIDTH-1:0]  shamt, 
	input                       ar
);


    wire [WIDTH-1:0] row[LOGWIDTH:0];
    
    wire fill = ar ? a[WIDTH-1] : 1'b0;
    
    assign row[0] = a;
    assign r = row[LOGWIDTH];

    generate
        genvar i; 
        for(i=0; i<LOGWIDTH; i=i+1) 
            assign row[i+1] = shamt[i] ? { { (2**i) {fill} }, row[i][WIDTH-1:(2**i)] } : row[i];
    endgenerate

endmodule