data/full_repos/permissive/523038000/lab14/stim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #50000 ps2d = 1\'b0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[2];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[3];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[4];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[5];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[6];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[7];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #60000 ps2d = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2c = 1\'b0;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/523038000/lab14/stim.v:125: Too many digits for 1 bit number: 1\'b10\n        #1000 ps2d = 1\'b10;\n                     ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:149: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:162: Unsupported: Ignoring delay on this delayed statement.\n        #60000 ps2d = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:163: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2c = 1\'b0;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:166: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:169: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:170: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:172: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[2];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:173: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:174: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[3];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:176: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:178: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[4];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:179: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:180: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:181: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[5];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:182: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:184: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[6];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:185: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:187: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = key_code2snd[7];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:188: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:190: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:191: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:192: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:193: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:194: Unsupported: Ignoring delay on this delayed statement.\n        #1000 ps2d = 1\'b1;          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:195: Unsupported: Ignoring delay on this delayed statement.\n        #39000 ps2c = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:196: Unsupported: Ignoring delay on this delayed statement.\n        #40000 ps2c = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab14/stim.v:199: Unsupported: Ignoring delay on this delayed statement.\n        #100000 $stop;      \n        ^\n%Error: Exiting due to 1 error(s), 103 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stim;































    
    reg clk,reset,ps2d,ps2c;
    
    wire [7:0] key_code;
    wire interrupt;
    
    reg [7:0] key_code2snd;
    
    ps2_rx ps2_rx_inst1 
								( 
			.clk(clk), 
			.reset(reset), 
			.ps2d(ps2d),
			.ps2c(ps2c), 
			.key_code(key_code), 
			.interrupt(interrupt) 
								);
							
	always
	#10 clk = ~clk;
	
	
	initial
	   begin
	       

	       
	       
	       key_code2snd = 8'b10101010;
	       
	       

	       
	       
	       ps2d = 1'b1;
	       ps2c = 1'b1;
	       clk = 1'b0;
	       reset = 1'b0;
	       #1 reset = 1'b1;
	       #1 reset = 1'b0;
	       
	       
	       

	           
	       #50000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[0];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[1];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[2];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[3];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[4];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[5];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[6];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[7];
	       #39000 ps2c = 1'b0;
	   
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       
	       
	       

	       
	       

	       
	       #60000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b10;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	   
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;  
	       #40000 ps2c = 1'b1;
	       
	       
	       
	       

	       
	       #60000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[0];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[1];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[2];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[3];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[4];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[5];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[6];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[7];
	       #39000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       
	       
	       #100000 $stop;      
	   end
	      
endmodule
module stim;
































    
    reg clk,reset,ps2d,ps2c;
    
    wire [7:0] key_code;
    wire interrupt;
    
    reg [7:0] key_code2snd;
    
    ps2_rx ps2_rx_inst1 
								( 
			.clk(clk), 
			.reset(reset), 
			.ps2d(ps2d),
			.ps2c(ps2c), 
			.key_code(key_code), 
			.interrupt(interrupt) 
								);
							
	always
	#10 clk = ~clk;
	
	
	initial
	   begin
	       

	       
	       
	       key_code2snd = 8'b10101010;
	       
	       

	       
	       
	       ps2d = 1'b1;
	       ps2c = 1'b1;
	       clk = 1'b0;
	       reset = 1'b0;
	       #1 reset = 1'b1;
	       #1 reset = 1'b0;
	       
	       
	       

	           
	       #50000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[0];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[1];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[2];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[3];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[4];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[5];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[6];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[7];
	       #39000 ps2c = 1'b0;
	   
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       
	       
	       

	       
	       

	       
	       #60000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b10;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b0;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	   
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;  
	       #40000 ps2c = 1'b1;
	       
	       
	       
	       

	       
	       #60000 ps2d = 1'b0;
	       #1000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[0];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[1];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[2];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[3];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[4];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[5];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[6];
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = key_code2snd[7];
	       #39000 ps2c = 1'b0;
	       
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       #1000 ps2d = 1'b1;
	       #39000 ps2c = 1'b0;
	       #40000 ps2c = 1'b1;
	       
	       
	       #100000 $stop;      
	   end
	      
endmodule