data/full_repos/permissive/434187796/testbench/BEEP_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n                #100 rst = 1\'b1;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n                #1_000 beep_enabled = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n                #1_000 beep = 1\'b1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n                #1_000 beep = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n                #1_000 beep_enabled = 1\'b0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n                #1_000 $stop;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        always #10 clk = ~clk;\n               ^\n%Error: data/full_repos/permissive/434187796/testbench/BEEP_tb.v:10: Cannot find file containing module: \'BEEP_CONTROLLER\'\n        BEEP_CONTROLLER beep_controller_ (\n        ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/BEEP_CONTROLLER\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/BEEP_CONTROLLER.v\n             data/full_repos/permissive/434187796/testbench,data/full_repos/permissive/434187796/BEEP_CONTROLLER.sv\n             BEEP_CONTROLLER\n             BEEP_CONTROLLER.v\n             BEEP_CONTROLLER.sv\n             obj_dir/BEEP_CONTROLLER\n             obj_dir/BEEP_CONTROLLER.v\n             obj_dir/BEEP_CONTROLLER.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BEEP_CONTROLLER_tb;
        reg clk;
        reg rst;
        reg beep;
        reg beep_enabled;
        wire beep_port;

        BEEP_CONTROLLER beep_controller_ (
                .clk(clk),
                .rst(rst),
                .beep(beep),
                .beep_enabled(beep_enabled),
                .beep_port(beep_port)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b0;
                beep = 1'b0;
                beep_enabled = 1'b0;

                #100 rst = 1'b1;

                #1_000 beep_enabled = 1'b1;
                #1_000 beep = 1'b1;
                #1_000 beep = 1'b0;
                #1_000 beep_enabled = 1'b0;
                #1_000 $stop;
        end

        always #10 clk = ~clk;
endmodule
module BEEP_CONTROLLER_tb;

        reg clk;
        reg rst;
        reg beep;
        reg beep_enabled;
        wire beep_port;

        BEEP_CONTROLLER beep_controller_ (
                .clk(clk),
                .rst(rst),
                .beep(beep),
                .beep_enabled(beep_enabled),
                .beep_port(beep_port)
        );

        initial begin
                clk = 1'b0;
                rst = 1'b0;
                beep = 1'b0;
                beep_enabled = 1'b0;

                #100 rst = 1'b1;

                #1_000 beep_enabled = 1'b1;
                #1_000 beep = 1'b1;
                #1_000 beep = 1'b0;
                #1_000 beep_enabled = 1'b0;
                #1_000 $stop;
        end

        always #10 clk = ~clk;
endmodule