data/full_repos/permissive/494353034/rtl/src_top/FIFO_fmap.v
data/verilator_xmls/705d3c1b-6de0-4347-be53-b15ebf9c3b66.xml
module FIFO_fmap
( 	
    input  clk,
	input  rstn,
	input  [7:0] din,
	input  wr_en,
	input  rd_en,
	input  rd_rst,
	output empty,
	output full,
	output [7:0] dout
);
	reg [7:0] rd_ptr, wr_ptr;
	reg [7:0] mem [0:149];
	reg [7:0] dout_r;
	integer i;
	
	assign empty = (wr_ptr == rd_ptr);
	assign full  = ((wr_ptr - rd_ptr) == 8'd150);
	

	reg wr_en_delay;
	always@(posedge clk)begin
		if(!rstn)
			wr_en_delay <= 0;
		else
			wr_en_delay <= wr_en;
	end

	always @(posedge clk or negedge rstn)begin
		if(!rstn)
			dout_r <= 0;
		else if(rd_en && !empty)
			dout_r <= mem[rd_ptr];
	end

	always @(posedge clk) 
	begin
	if(rstn && wr_en_delay && !full)
		mem[wr_ptr] <= din;
	end
	

	always @(posedge clk or negedge rstn) 
	begin
		if(!rstn) 
			wr_ptr <= 0;
		else if(!full && wr_en_delay)
			wr_ptr <= wr_ptr + 1;
	end
	

	always @(posedge clk or negedge rstn) 
	begin
		if(!rstn)
			rd_ptr <= 0;
		else
			if(rd_rst)	
				rd_ptr <= 0;
			else if(!empty && rd_en)
				rd_ptr <= rd_ptr + 1;
		end
	
	assign dout = dout_r;

endmodule
module FIFO_fmap
( 	
    input  clk,
	input  rstn,
	input  [7:0] din,
	input  wr_en,
	input  rd_en,
	input  rd_rst,
	output empty,
	output full,
	output [7:0] dout
);

	reg [7:0] rd_ptr, wr_ptr;
	reg [7:0] mem [0:149];
	reg [7:0] dout_r;
	integer i;
	
	assign empty = (wr_ptr == rd_ptr);
	assign full  = ((wr_ptr - rd_ptr) == 8'd150);
	

	reg wr_en_delay;
	always@(posedge clk)begin
		if(!rstn)
			wr_en_delay <= 0;
		else
			wr_en_delay <= wr_en;
	end

	always @(posedge clk or negedge rstn)begin
		if(!rstn)
			dout_r <= 0;
		else if(rd_en && !empty)
			dout_r <= mem[rd_ptr];
	end

	always @(posedge clk) 
	begin
	if(rstn && wr_en_delay && !full)
		mem[wr_ptr] <= din;
	end
	

	always @(posedge clk or negedge rstn) 
	begin
		if(!rstn) 
			wr_ptr <= 0;
		else if(!full && wr_en_delay)
			wr_ptr <= wr_ptr + 1;
	end
	

	always @(posedge clk or negedge rstn) 
	begin
		if(!rstn)
			rd_ptr <= 0;
		else
			if(rd_rst)	
				rd_ptr <= 0;
			else if(!empty && rd_en)
				rd_ptr <= rd_ptr + 1;
		end
	
	assign dout = dout_r;

endmodule