data/full_repos/permissive/468612001/Week03/mux8b_2to1/mux8b_2to1_case.v
data/verilator_xmls/1d0be1a3-8b00-4e38-8f63-fa2ff1c11614.xml
module mux8b_2to1_case(a, b, sel, out);
	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	reg [7:0] out;
	
	always @(a, b, sel) begin
		case(sel)
			1'b0 : out = a;
			1'b1 : out = b;
		endcase
	end
endmodule
module mux8b_2to1_case(a, b, sel, out);

	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	reg [7:0] out;
	
	always @(a, b, sel) begin
		case(sel)
			1'b0 : out = a;
			1'b1 : out = b;
		endcase
	end
endmodule