data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #0.5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #0.5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB2.v:11: Cannot find file containing module: \'Processor\'\n    Processor DUT(.clk(t_clk), .rstn(t_rstn));\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/Processor\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/Processor.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/Processor.sv\n             Processor\n             Processor.v\n             Processor.sv\n             obj_dir/Processor\n             obj_dir/Processor.v\n             obj_dir/Processor.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Processor_TB2(

    );
    reg t_clk = 1;
    reg t_rstn = 0;
    reg [31:0] t_pc;
    
    Processor DUT(.clk(t_clk), .rstn(t_rstn));
    
    initial begin : CLK_GEN
        forever begin
            t_clk <=1;
            #0.5;
            t_clk <=0;
            #0.5;
        end
    end
    
    initial begin : TEST_PROCESS
           
        #100
        

        
        #2;
        t_rstn <= 1;







        

  


        













        


        






                       





        






         











































        





        





        

 




        





         





        





        





        





        





        





       





        





        


        





        
        




















        






         



        



        







        



        



        



        



        


        
        


































        



        


        



        







        



        



        



                



        



        



        



        



        



        



        



        



        



        



        



        



        





        







        
        
        $display("\nAll test Passed\n");

    end
endmodule
module Processor_TB2(

    );

    reg t_clk = 1;
    reg t_rstn = 0;
    reg [31:0] t_pc;
    
    Processor DUT(.clk(t_clk), .rstn(t_rstn));
    
    initial begin : CLK_GEN
        forever begin
            t_clk <=1;
            #0.5;
            t_clk <=0;
            #0.5;
        end
    end
    
    initial begin : TEST_PROCESS
           
        #100
        

        
        #2;
        t_rstn <= 1;







        

  


        













        


        






                       





        






         











































        





        





        

 




        





         





        





        





        





        





        





       





        





        


        





        
        




















        






         



        



        







        



        



        



        



        


        
        


































        



        


        



        







        



        



        



                



        



        



        



        



        



        



        



        



        



        



        



        



        





        







        
        
        $display("\nAll test Passed\n");

    end
endmodule