data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_4bit.v
1: b"%Error: data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_4bit.v:33: Cannot find file containing module: 'full_adder'\n    full_adder FA2\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder.v\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_4bit.v:42: Cannot find file containing module: 'full_adder'\n    full_adder FA0\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_4bit.v:51: Cannot find file containing module: 'full_adder'\n    full_adder FA1\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_4bit.v:60: Cannot find file containing module: 'full_adder'\n    full_adder FA3\n    ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module rca_4bit(
    input [3:0] x, 
    input [3:0] y,
    input c_in,
    output [3:0] s,
    output c_out
    );
    
    wire [3:1] c;
    
    full_adder FA2
    (
    .x(x[2]),
    .y(y[2]),
    .c_in(c[2]),
    .s(s[2]),
    .c_out(c[3])
    );
    
    full_adder FA0
    (
    .x(x[0]),
    .y(y[0]),
    .c_in(c_in),
    .s(s[0]),
    .c_out(c[1])
    );
    
    full_adder FA1
    (
    .x(x[1]),
    .y(y[1]),
    .c_in(c[1]),
    .s(s[1]),
    .c_out(c[2])
    );
    
    full_adder FA3
    (
    .x(x[3]),
    .y(y[3]),
    .c_in(c[3]),
    .s(s[3]),
    .c_out(c_out)
    );
    
    
endmodule
module rca_4bit(
    input [3:0] x, 
    input [3:0] y,
    input c_in,
    output [3:0] s,
    output c_out
    );

    
    wire [3:1] c;
    
    full_adder FA2
    (
    .x(x[2]),
    .y(y[2]),
    .c_in(c[2]),
    .s(s[2]),
    .c_out(c[3])
    );
    
    full_adder FA0
    (
    .x(x[0]),
    .y(y[0]),
    .c_in(c_in),
    .s(s[0]),
    .c_out(c[1])
    );
    
    full_adder FA1
    (
    .x(x[1]),
    .y(y[1]),
    .c_in(c[1]),
    .s(s[1]),
    .c_out(c[2])
    );
    
    full_adder FA3
    (
    .x(x[3]),
    .y(y[3]),
    .c_in(c[3]),
    .s(s[3]),
    .c_out(c_out)
    );
    
    
endmodule