data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:36: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #0 clock = 0; reset = 0; push = 0; pop = 0; in = 8\'d0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #25 in = 8\'h15; push = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 push = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 in = 8\'h16; push = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 push = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 in = 8\'h17; push = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 push = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #210 pop = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 pop = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #50 pop = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10 pop = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #50 pop = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 pop = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish;\n        ^\n%Error: data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new/test1.v:34: Cannot find file containing module: \'Stack\'\n    Stack s(size,top,push,pop,in,reset,clock);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new,data/full_repos/permissive/423958267/Stack\n             data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new,data/full_repos/permissive/423958267/Stack.v\n             data/full_repos/permissive/423958267/lab04_1/lab04_1.srcs/sim_1/new,data/full_repos/permissive/423958267/Stack.sv\n             Stack\n             Stack.v\n             Stack.sv\n             obj_dir/Stack\n             obj_dir/Stack.v\n             obj_dir/Stack.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test1(

    );
    wire [7:0] size;
    wire [7:0] top;
    reg push;
    reg pop;
    reg [7:0] in;
    reg reset;
    reg clock;
    
    Stack s(size,top,push,pop,in,reset,clock);
    
    always #10 clock = ~clock;
    
    initial
    begin
        #0 clock = 0; reset = 0; push = 0; pop = 0; in = 8'd0;
        #25 in = 8'h15; push = 1;
        #10 push = 0;
        #10 in = 8'h16; push = 1;
        #10 push = 0;
        #10 in = 8'h17; push = 1;
        #10 push = 0;
        #210 pop = 1;
        #10 pop = 0;
        #50 pop = 1;
        #10 pop = 0;
        #50 pop = 1;
        #10 pop = 0;
        #200 $finish;
    end
endmodule
module test1(

    );

    wire [7:0] size;
    wire [7:0] top;
    reg push;
    reg pop;
    reg [7:0] in;
    reg reset;
    reg clock;
    
    Stack s(size,top,push,pop,in,reset,clock);
    
    always #10 clock = ~clock;
    
    initial
    begin
        #0 clock = 0; reset = 0; push = 0; pop = 0; in = 8'd0;
        #25 in = 8'h15; push = 1;
        #10 push = 0;
        #10 in = 8'h16; push = 1;
        #10 push = 0;
        #10 in = 8'h17; push = 1;
        #10 push = 0;
        #210 pop = 1;
        #10 pop = 0;
        #50 pop = 1;
        #10 pop = 0;
        #50 pop = 1;
        #10 pop = 0;
        #200 $finish;
    end
endmodule