data/full_repos/permissive/504478691/temperature/history/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/504478691/temperature/history/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504478691/temperature/history/tb.v:5: Cannot find file containing module: \'temperature\'\ntemperature inst(.clk(clk), .sda(sda), .scl(scl));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/temperature/history,data/full_repos/permissive/504478691/temperature\n             data/full_repos/permissive/504478691/temperature/history,data/full_repos/permissive/504478691/temperature.v\n             data/full_repos/permissive/504478691/temperature/history,data/full_repos/permissive/504478691/temperature.sv\n             temperature\n             temperature.v\n             temperature.sv\n             obj_dir/temperature\n             obj_dir/temperature.v\n             obj_dir/temperature.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
reg clk = 1;
wire sda, scl;
temperature inst(.clk(clk), .sda(sda), .scl(scl));
integer i;
initial
begin
    for (i = 0; i <= 500_000; i = i + 1)
    begin
        clk = !clk;
        #1;
    end
end
endmodule
module tb();

reg clk = 1;
wire sda, scl;
temperature inst(.clk(clk), .sda(sda), .scl(scl));
integer i;
initial
begin
    for (i = 0; i <= 500_000; i = i + 1)
    begin
        clk = !clk;
        #1;
    end
end
endmodule