data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:19: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic [N_MASTER-1:0][ID_WIDTH-1:0]   inp_id_i,\n                             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:19: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic [N_MASTER-1:0][ID_WIDTH-1:0]   inp_id_i,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:20: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic [N_MASTER-1:0][AUX_WIDTH-1:0]  inp_aux_i,\n                             ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:20: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic [N_MASTER-1:0][AUX_WIDTH-1:0]  inp_aux_i,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:21: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic [N_MASTER-1:0]                 inp_valid_i,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:22: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output logic [N_MASTER-1:0]                 inp_ready_o,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:24: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output logic [ID_WIDTH-1:0]                 oup_id_o,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:25: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output logic [AUX_WIDTH-1:0]                oup_aux_o,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n    logic [AUX_WIDTH-1:0] aux;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:32: Little bit endian vector: MSB < LSB of bit range: -1:0\n    logic [ID_WIDTH-1:0]  id;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:35: Little bit endian vector: MSB < LSB of bit range: -1:0\n  axi_meta_t [N_MASTER-1:0] inp_meta;\n             ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src/axi_node_arbiter.sv:43: Cannot find file containing module: \'stream_arbiter\'\n  stream_arbiter #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src,data/full_repos/permissive/509468557/stream_arbiter\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src,data/full_repos/permissive/509468557/stream_arbiter.v\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi_node/src,data/full_repos/permissive/509468557/stream_arbiter.sv\n             stream_arbiter\n             stream_arbiter.v\n             stream_arbiter.sv\n             obj_dir/stream_arbiter\n             obj_dir/stream_arbiter.v\n             obj_dir/stream_arbiter.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module axi_node_arbiter #(
  parameter int unsigned AUX_WIDTH = 0,
  parameter int unsigned ID_WIDTH = 0,
  parameter int unsigned N_MASTER = 0
) (
  input  logic                                clk_i,
  input  logic                                rst_ni,

  input  logic [N_MASTER-1:0][ID_WIDTH-1:0]   inp_id_i,
  input  logic [N_MASTER-1:0][AUX_WIDTH-1:0]  inp_aux_i,
  input  logic [N_MASTER-1:0]                 inp_valid_i,
  output logic [N_MASTER-1:0]                 inp_ready_o,

  output logic [ID_WIDTH-1:0]                 oup_id_o,
  output logic [AUX_WIDTH-1:0]                oup_aux_o,
  output logic                                oup_valid_o,
  input  logic                                oup_ready_i
);

  typedef struct packed {
    logic [AUX_WIDTH-1:0] aux;
    logic [ID_WIDTH-1:0]  id;
  } axi_meta_t;

  axi_meta_t [N_MASTER-1:0] inp_meta;
  axi_meta_t oup_meta;

  for (genvar i = 0; i < N_MASTER; i++) begin: gen_inp_meta
    assign inp_meta[i].aux = inp_aux_i[i];
    assign inp_meta[i].id = inp_id_i[i];
  end

  stream_arbiter #(
    .DATA_T (axi_meta_t),
    .N_INP  (N_MASTER)
  ) i_arb_inp (
    .clk_i        (clk_i),
    .rst_ni       (rst_ni),
    .inp_data_i   (inp_meta),
    .inp_valid_i  (inp_valid_i),
    .inp_ready_o  (inp_ready_o),
    .oup_data_o   (oup_meta),
    .oup_valid_o  (oup_valid_o),
    .oup_ready_i  (oup_ready_i)
  );

  assign oup_id_o = oup_meta.id;
  assign oup_aux_o = oup_meta.aux;


`ifndef VERILATOR
  initial begin: p_assertions
    assert (AUX_WIDTH >= 1) else $fatal("Minimum width of auxiliary data is 1!");
    assert (ID_WIDTH >= 1) else $fatal("Minimum width of ID is 1!");
    assert (N_MASTER >= 1) else $fatal("Minimum number of masters is 1!");
  end
`endif


endmodule
module axi_node_arbiter #(
  parameter int unsigned AUX_WIDTH = 0,
  parameter int unsigned ID_WIDTH = 0,
  parameter int unsigned N_MASTER = 0
) (
  input  logic                                clk_i,
  input  logic                                rst_ni,

  input  logic [N_MASTER-1:0][ID_WIDTH-1:0]   inp_id_i,
  input  logic [N_MASTER-1:0][AUX_WIDTH-1:0]  inp_aux_i,
  input  logic [N_MASTER-1:0]                 inp_valid_i,
  output logic [N_MASTER-1:0]                 inp_ready_o,

  output logic [ID_WIDTH-1:0]                 oup_id_o,
  output logic [AUX_WIDTH-1:0]                oup_aux_o,
  output logic                                oup_valid_o,
  input  logic                                oup_ready_i
);


  typedef struct packed {
    logic [AUX_WIDTH-1:0] aux;
    logic [ID_WIDTH-1:0]  id;
  } axi_meta_t;

  axi_meta_t [N_MASTER-1:0] inp_meta;
  axi_meta_t oup_meta;

  for (genvar i = 0; i < N_MASTER; i++) begin: gen_inp_meta
    assign inp_meta[i].aux = inp_aux_i[i];
    assign inp_meta[i].id = inp_id_i[i];
  end

  stream_arbiter #(
    .DATA_T (axi_meta_t),
    .N_INP  (N_MASTER)
  ) i_arb_inp (
    .clk_i        (clk_i),
    .rst_ni       (rst_ni),
    .inp_data_i   (inp_meta),
    .inp_valid_i  (inp_valid_i),
    .inp_ready_o  (inp_ready_o),
    .oup_data_o   (oup_meta),
    .oup_valid_o  (oup_valid_o),
    .oup_ready_i  (oup_ready_i)
  );

  assign oup_id_o = oup_meta.id;
  assign oup_aux_o = oup_meta.aux;


`ifndef VERILATOR
  initial begin: p_assertions
    assert (AUX_WIDTH >= 1) else $fatal("Minimum width of auxiliary data is 1!");
    assert (ID_WIDTH >= 1) else $fatal("Minimum width of ID is 1!");
    assert (N_MASTER >= 1) else $fatal("Minimum number of masters is 1!");
  end
`endif


endmodule