data/full_repos/permissive/485129576/alu8.v
data/verilator_xmls/7e04ceb6-62cd-4798-8472-e546f7191a3d.xml
module ALU8 (
    input [3:0] op,
    input [7:0] A,
    input [7:0] B,
    output reg [7:0] R,
    output wire [1:0] flags
);
    always@(*) begin
        case(op)

            4'b1000 : R = A + B;
            4'b1001 : R = A + (~B + 8'b00000001);
            4'b1010 : R = A * B;


            4'b1011 : R = A & B;
            4'b1100 : R = A | B;
            4'b1101 : R = A << B;
            4'b1111 : R = A >> B;



            4'b0001 : R = A + B;
            4'b0010 : R = A + (~B + 8'b00000001);


            4'b0011 : R = A & B;
            4'b0100 : R = A | B;
            4'b0101 : R = A ^ B;

            default : R = 8'bZZZZZZZZ;
        endcase
    end


    assign flags[1] = R[7];
    assign flags[0] = (R == 8'b0);

endmodule
module ALU8 (
    input [3:0] op,
    input [7:0] A,
    input [7:0] B,
    output reg [7:0] R,
    output wire [1:0] flags
);

    always@(*) begin
        case(op)

            4'b1000 : R = A + B;
            4'b1001 : R = A + (~B + 8'b00000001);
            4'b1010 : R = A * B;


            4'b1011 : R = A & B;
            4'b1100 : R = A | B;
            4'b1101 : R = A << B;
            4'b1111 : R = A >> B;



            4'b0001 : R = A + B;
            4'b0010 : R = A + (~B + 8'b00000001);


            4'b0011 : R = A & B;
            4'b0100 : R = A | B;
            4'b0101 : R = A ^ B;

            default : R = 8'bZZZZZZZZ;
        endcase
    end


    assign flags[1] = R[7];
    assign flags[0] = (R == 8'b0);

endmodule