data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count_clock_1/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count_clock_1/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    input wire ena,
    output wire pm,
    output wire [7:0] hh,
    output wire [7:0] mm,
    output wire [7:0] ss
);

  wire [23:0] bcd24h;

  bcdcount24h standard_time_format (
      .clk(clk),
      .reset(reset),
      .enable(ena),
      .Q(bcd24h)
  );

  bcd24h2complex12h really_complex_time_format (
      .bcd24h(bcd24h),
      .pm(pm),
      .bcd12h({hh, mm, ss})
  );

endmodule
module top_module (
    input wire clk,
    input wire reset,
    input wire ena,
    output wire pm,
    output wire [7:0] hh,
    output wire [7:0] mm,
    output wire [7:0] ss
);


  wire [23:0] bcd24h;

  bcdcount24h standard_time_format (
      .clk(clk),
      .reset(reset),
      .enable(ena),
      .Q(bcd24h)
  );

  bcd24h2complex12h really_complex_time_format (
      .bcd24h(bcd24h),
      .pm(pm),
      .bcd12h({hh, mm, ss})
  );

endmodule