data/full_repos/permissive/520695407/src/metaball.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/520695407/src/metaball.sv:44: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 31 bits.\n                                                                       : ... In instance metaball\n  assign dividend = rad_sq[45:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520695407/src/metaball.sv:46: Cannot find file containing module: \'qmult\'\n  qmult #(15,32) sq1(\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/qmult\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/qmult.v\n             data/full_repos/permissive/520695407/src,data/full_repos/permissive/520695407/qmult.sv\n             qmult\n             qmult.v\n             qmult.sv\n             obj_dir/qmult\n             obj_dir/qmult.v\n             obj_dir/qmult.sv\n%Error: data/full_repos/permissive/520695407/src/metaball.sv:52: Cannot find file containing module: \'qmult\'\n  qmult #(15,32) sq2(\n  ^~~~~\n%Error: data/full_repos/permissive/520695407/src/metaball.sv:59: Cannot find file containing module: \'qdiv\'\n  qdiv #(15,32) func(\n  ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module metaball #(
    parameter WIDTH  = 32'h000f_8000,
    parameter HEIGHT = 32'h000f_c000,
    parameter RAD    = 32'h0001_4000,
    parameter I_X    = 32'h0007_c000,
    parameter I_Y    = 32'h0000_0000,

    parameter IV_X   = 32'h0000_0000,
    parameter IV_Y   = 32'h0000_0333

  )(
    input               clk,
    input               rst,
    input               mov_en,
    input               px_stb,

    input int           p_x,
    input int           p_y,
    output logic        vld,

    output logic [31:0] out
  );


  logic [31:0] x = I_X,
	       y = I_Y;

  logic [31:0] v_x = IV_X,
	       v_y = IV_Y;




  wire [31:0] dx, dy, dx_sq, dy_sq;
  assign dx = p_x - x;
  assign dy = p_y - y;

  wire [63:0] rad_sq;
  wire [31:0] dividend, divisor;
  assign rad_sq = RAD * RAD;
  assign dividend = rad_sq[45:15];

  qmult #(15,32) sq1(
    .i_multiplicand(dx),
    .i_multiplier(dx),
    .o_result(dx_sq),
    .ovr()
  );
  qmult #(15,32) sq2(
    .i_multiplicand(dy),
    .i_multiplier(dy),
    .o_result(dy_sq),
    .ovr()
  );
  assign divisor = dx_sq + dy_sq;
  qdiv #(15,32) func(
    .i_dividend(dividend),
    .i_divisor(divisor),
    .i_start(px_stb),
    .i_clk(clk),
    .o_quotient_out(out),
    .o_complete(vld),
    .o_overflow()
  );
  
  always_ff @ (posedge clk) begin
    if (rst) begin
      x <= I_X;
      y <= I_Y;
    end else begin
      if (mov_en) begin
	x <= x + v_x;
	y <= y + v_y;

	if (x >= (WIDTH - RAD) || x <= RAD) v_x = ~v_x + 1;
	if (y >= (HEIGHT - RAD) || y <= RAD) v_y = ~v_y + 1;
      end
    end
  end
endmodule
module metaball #(
    parameter WIDTH  = 32'h000f_8000,
    parameter HEIGHT = 32'h000f_c000,
    parameter RAD    = 32'h0001_4000,
    parameter I_X    = 32'h0007_c000,
    parameter I_Y    = 32'h0000_0000,

    parameter IV_X   = 32'h0000_0000,
    parameter IV_Y   = 32'h0000_0333

  )(
    input               clk,
    input               rst,
    input               mov_en,
    input               px_stb,

    input int           p_x,
    input int           p_y,
    output logic        vld,

    output logic [31:0] out
  );



  logic [31:0] x = I_X,
	       y = I_Y;

  logic [31:0] v_x = IV_X,
	       v_y = IV_Y;




  wire [31:0] dx, dy, dx_sq, dy_sq;
  assign dx = p_x - x;
  assign dy = p_y - y;

  wire [63:0] rad_sq;
  wire [31:0] dividend, divisor;
  assign rad_sq = RAD * RAD;
  assign dividend = rad_sq[45:15];

  qmult #(15,32) sq1(
    .i_multiplicand(dx),
    .i_multiplier(dx),
    .o_result(dx_sq),
    .ovr()
  );
  qmult #(15,32) sq2(
    .i_multiplicand(dy),
    .i_multiplier(dy),
    .o_result(dy_sq),
    .ovr()
  );
  assign divisor = dx_sq + dy_sq;
  qdiv #(15,32) func(
    .i_dividend(dividend),
    .i_divisor(divisor),
    .i_start(px_stb),
    .i_clk(clk),
    .o_quotient_out(out),
    .o_complete(vld),
    .o_overflow()
  );
  
  always_ff @ (posedge clk) begin
    if (rst) begin
      x <= I_X;
      y <= I_Y;
    end else begin
      if (mov_en) begin
	x <= x + v_x;
	y <= y + v_y;

	if (x >= (WIDTH - RAD) || x <= RAD) v_x = ~v_x + 1;
	if (y >= (HEIGHT - RAD) || y <= RAD) v_y = ~v_y + 1;
      end
    end
  end
endmodule