data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/clk/rtl/pa_clk_top.v
data/verilator_xmls/36d3a38f-fa34-432a-b25a-62b8d12fd9ab.xml
module pa_clk_top(
  clk_en,
  clk_en_f,
  forever_cpuclk,
  pll_core_cpuclk
);


input        clk_en;         
input        pll_core_cpuclk; 
output       clk_en_f;       
output       forever_cpuclk; 


reg          clk_en_f;       


wire         clk_en;         
wire         forever_cpuclk; 
wire         pll_core_cpuclk; 



assign forever_cpuclk = pll_core_cpuclk;


always@(posedge forever_cpuclk)
begin
  clk_en_f <= clk_en;
end



endmodule
module pa_clk_top(
  clk_en,
  clk_en_f,
  forever_cpuclk,
  pll_core_cpuclk
);



input        clk_en;         
input        pll_core_cpuclk; 
output       clk_en_f;       
output       forever_cpuclk; 


reg          clk_en_f;       


wire         clk_en;         
wire         forever_cpuclk; 
wire         pll_core_cpuclk; 



assign forever_cpuclk = pll_core_cpuclk;


always@(posedge forever_cpuclk)
begin
  clk_en_f <= clk_en;
end



endmodule