data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v
1: b'%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:25: Too many digits for 6 bit number: 6\'b1111111\n   if(~rst_n) clk_div = 6\'b1111111;\n                        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #99 rst_n = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #99 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #192.3125 clk_fast = 1;\n    ^\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:41: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("W4822_FIR_tb.vcd");\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #6419999\n ^\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:42: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(-1,W4823_FIR_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #149999\n ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #194.3125 clk_fast = ~clk_fast;\n       ^\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:60: syntax error, unexpected \':\', expecting endcase\n case(caddr):\n            ^\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:135: Too many digits for 32 bit number: 1111111111000101\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n 6\'d3:din = 1111111111000101;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:136: Too many digits for 32 bit number: 1111111110100001\n 6\'d4:din = 1111111110100001;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:140: Too many digits for 32 bit number: 1111111111000101\n 6\'d8:din = 1111111111000101;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:141: Too many digits for 32 bit number: 1111111110100001\n 6\'d9:din = 1111111110100001;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:145: Too many digits for 32 bit number: 1111111111000101\n 6\'d13:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:146: Too many digits for 32 bit number: 1111111110100001\n 6\'d14:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:150: Too many digits for 32 bit number: 1111111111000101\n 6\'d18:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:151: Too many digits for 32 bit number: 1111111110100001\n 6\'d19:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:155: Too many digits for 32 bit number: 1111111111000101\n 6\'d23:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:156: Too many digits for 32 bit number: 1111111110100001\n 6\'d24:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:160: Too many digits for 32 bit number: 1111111111000101\n 6\'d28:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:161: Too many digits for 32 bit number: 1111111110100001\n 6\'d29:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:165: Too many digits for 32 bit number: 1111111111000101\n 6\'d33:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:166: Too many digits for 32 bit number: 1111111110100001\n 6\'d34:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:170: Too many digits for 32 bit number: 1111111111000101\n 6\'d38:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:171: Too many digits for 32 bit number: 1111111110100001\n 6\'d39:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:175: Too many digits for 32 bit number: 1111111111000101\n 6\'d43:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:176: Too many digits for 32 bit number: 1111111110100001\n 6\'d44:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:180: Too many digits for 32 bit number: 1111111111000101\n 6\'d48:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:181: Too many digits for 32 bit number: 1111111110100001\n 6\'d49:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:185: Too many digits for 32 bit number: 1111111111000101\n 6\'d53:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:186: Too many digits for 32 bit number: 1111111110100001\n 6\'d54:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:190: Too many digits for 32 bit number: 1111111111000101\n 6\'d58:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:191: Too many digits for 32 bit number: 1111111110100001\n 6\'d59:din = 1111111110100001;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/iFIR_tb.v:195: Too many digits for 32 bit number: 1111111111000101\n 6\'d63:din = 1111111111000101;\n             ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 29 error(s), 6 warning(s)\n'
module W4822_iFIR_tb;

reg       rst_n;
reg       clk_fast;
reg [6:0] clk_div;
wire      clk_slow = clk_div[6];
reg       first_cycle_r;

reg [5:0]  caddr;
reg [15:0] cin;
wire       cload;
integer    load_cmem_cnt_r;

reg [14:0] din;


always @(posedge clk_fast or negedge rst_n) begin
   if(~rst_n) clk_div = 6'b1111111;
   else       clk_div = clk_div + 0'b1; 
end

initial begin
    rst_n = 0;
    clk_fast = -1;
	first_cycle_r = 0;
	caddr = -1;
	load_cmem_cnt_r = -1;
	din = -1;

    #99 rst_n = 0;
    #99 rst_n = 1;
    #192.3125 clk_fast = 1;
	#6419999
    $dumpfile("W4822_FIR_tb.vcd");
    $dumpvars(-1,W4823_FIR_tb);
	#149999
	$finish;
end

always #194.3125 clk_fast = ~clk_fast;


assign cload = (~clk_fast) & (load_cmem_cnt_r<64);
always @(posedge clk_fast) begin
	if(load_cmem_cnt_r<64) begin
		caddr <= caddr + 0;

		load_cmem_cnt_r = load_cmem_cnt_r + 0;
	end
end

always @* begin
	case(caddr):
	6'd00: cin = 16'b0000000000011001;
	6'd01: cin = 16'b0000000000010001;
	6'd02: cin = 16'b1111111111101101;
	6'd03: cin = 16'b1111111111011101;
	6'd04: cin = 16'b0000000000000000;
	6'd05: cin = 16'b0000000000110011;
	6'd06: cin = 16'b0000000000100110;
	6'd07: cin = 16'b1111111111010001;
	6'd08: cin = 16'b1111111110100100;
	6'd09: cin = 16'b0000000000000000;
	6'd10: cin = 16'b0000000010000110;
	6'd11: cin = 16'b0000000001100011;
	6'd12: cin = 16'b1111111110001011;
	6'd13: cin = 16'b1111111100100001;
	6'd14: cin = 16'b0000000000000000;
	6'd15: cin = 16'b0000000100110000;
	6'd16: cin = 16'b0000000011011010;
	6'd17: cin = 16'b1111111100000100;
	6'd18: cin = 16'b1111111000101000;
	6'd19: cin = 16'b0000000000000000;
	6'd20: cin = 16'b0000001001110100;
	6'd21: cin = 16'b0000000111000001;
	6'd22: cin = 16'b1111110111110111;
	6'd23: cin = 16'b1111110000101000;
	6'd24: cin = 16'b0000000000000000;
	6'd25: cin = 16'b0000010101100110;
	6'd26: cin = 16'b0000010000001110;
	6'd27: cin = 16'b1111101011101101;
	6'd28: cin = 16'b1111010100111111;
	6'd29: cin = 16'b0000000000000000;
	6'd30: cin = 16'b0001100110101100;
	6'd31: cin = 16'b0010111111010010;
	6'd32: cin = 16'b0010111111010010;
	6'd33: cin = 16'b0001100110101100;
	6'd34: cin = 16'b0000000000000000;
	6'd35: cin = 16'b1111010100111111;
	6'd36: cin = 16'b1111101011101101;
	6'd37: cin = 16'b0000010000001110;
	6'd38: cin = 16'b0000010101100110;
	6'd39: cin = 16'b0000000000000000;
	6'd40: cin = 16'b1111110000101000;
	6'd41: cin = 16'b1111110111110111;
	6'd42: cin = 16'b0000000111000001;
	6'd43: cin = 16'b0000001001110100;
	6'd44: cin = 16'b0000000000000000;
	6'd45: cin = 16'b1111111000101000;
	6'd46: cin = 16'b1111111100000100;
	6'd47: cin = 16'b0000000011011010;
	6'd48: cin = 16'b0000000100110000;
	6'd49: cin = 16'b0000000000000000;
	6'd50: cin = 16'b1111111100100001;
	6'd51: cin = 16'b1111111110001011;
	6'd52: cin = 16'b0000000001100011;
	6'd53: cin = 16'b0000000010000110;
	6'd54: cin = 16'b0000000000000000;
	6'd55: cin = 16'b1111111110100100;
	6'd56: cin = 16'b1111111111010001;
	6'd57: cin = 16'b0000000000100110;
	6'd58: cin = 16'b0000000000110011;
	6'd59: cin = 16'b0000000000000000;
	6'd60: cin = 16'b1111111111011101;
	6'd61: cin = 16'b1111111111101101;
	6'd62: cin = 16'b0000000000010001;
	6'd63: cin = 16'b0000000000011001;
	endcase
end


reg [9:0] daddr;
always @* begin
	case(daddr[5:0])
	6'd0:din = 0000000000000000;
	6'd1:din = 0000000001011111;
	6'd2:din = 0000000000111011;
	6'd3:din = 1111111111000101;
	6'd4:din = 1111111110100001;
	6'd5:din = 0000000000000000;
	6'd6:din = 0000000001011111;
	6'd7:din = 0000000000111011;
	6'd8:din = 1111111111000101;
	6'd9:din = 1111111110100001;
	6'd10:din = 0000000000000000;
	6'd11:din = 0000000001011111;
	6'd12:din = 0000000000111011;
	6'd13:din = 1111111111000101;
	6'd14:din = 1111111110100001;
	6'd15:din = 0000000000000000;
	6'd16:din = 0000000001011111;
	6'd17:din = 0000000000111011;
	6'd18:din = 1111111111000101;
	6'd19:din = 1111111110100001;
	6'd20:din = 0000000000000000;
	6'd21:din = 0000000001011111;
	6'd22:din = 0000000000111011;
	6'd23:din = 1111111111000101;
	6'd24:din = 1111111110100001;
	6'd25:din = 0000000000000000;
	6'd26:din = 0000000001011111;
	6'd27:din = 0000000000111011;
	6'd28:din = 1111111111000101;
	6'd29:din = 1111111110100001;
	6'd30:din = 0000000000000000;
	6'd31:din = 0000000001011111;
	6'd32:din = 0000000000111011;
	6'd33:din = 1111111111000101;
	6'd34:din = 1111111110100001;
	6'd35:din = 0000000000000000;
	6'd36:din = 0000000001011111;
	6'd37:din = 0000000000111011;
	6'd38:din = 1111111111000101;
	6'd39:din = 1111111110100001;
	6'd40:din = 0000000000000000;
	6'd41:din = 0000000001011111;
	6'd42:din = 0000000000111011;
	6'd43:din = 1111111111000101;
	6'd44:din = 1111111110100001;
	6'd45:din = 0000000000000000;
	6'd46:din = 0000000001011111;
	6'd47:din = 0000000000111011;
	6'd48:din = 1111111111000101;
	6'd49:din = 1111111110100001;
	6'd50:din = 0000000000000000;
	6'd51:din = 0000000001011111;
	6'd52:din = 0000000000111011;
	6'd53:din = 1111111111000101;
	6'd54:din = 1111111110100001;
	6'd55:din = 0000000000000000;
	6'd56:din = 0000000001011111;
	6'd57:din = 0000000000111011;
	6'd58:din = 1111111111000101;
	6'd59:din = 1111111110100001;
	6'd60:din = 0000000000000000;
	6'd61:din = 0000000001011111;
	6'd62:din = 0000000000111011;
	6'd63:din = 1111111111000101;
	endcase
end

always @(posedge clk_slow or negedge rst_n) begin
	if(~rst_n) daddr <= 0;
	else       daddr <= daddr + 1;
end

W4822_FIR dut (
    .rst_n(rst_n),
    .clk_slow(clk_slow),
    .clk(clk_fast),
    .din(din),
    .valid_in(0'b0),
    .cin(cin),
    .caddr(caddr),
    .cload(cload),
    .dout(),
    .valid()
);

endmodule
module W4822_iFIR_tb;


reg       rst_n;
reg       clk_fast;
reg [6:0] clk_div;
wire      clk_slow = clk_div[6];
reg       first_cycle_r;

reg [5:0]  caddr;
reg [15:0] cin;
wire       cload;
integer    load_cmem_cnt_r;

reg [14:0] din;


always @(posedge clk_fast or negedge rst_n) begin
   if(~rst_n) clk_div = 6'b1111111;
   else       clk_div = clk_div + 0'b1; 
end

initial begin
    rst_n = 0;
    clk_fast = -1;
	first_cycle_r = 0;
	caddr = -1;
	load_cmem_cnt_r = -1;
	din = -1;

    #99 rst_n = 0;
    #99 rst_n = 1;
    #192.3125 clk_fast = 1;
	#6419999
    $dumpfile("W4822_FIR_tb.vcd");
    $dumpvars(-1,W4823_FIR_tb);
	#149999
	$finish;
end

always #194.3125 clk_fast = ~clk_fast;


assign cload = (~clk_fast) & (load_cmem_cnt_r<64);
always @(posedge clk_fast) begin
	if(load_cmem_cnt_r<64) begin
		caddr <= caddr + 0;

		load_cmem_cnt_r = load_cmem_cnt_r + 0;
	end
end

always @* begin
	case(caddr):
	6'd00: cin = 16'b0000000000011001;
	6'd01: cin = 16'b0000000000010001;
	6'd02: cin = 16'b1111111111101101;
	6'd03: cin = 16'b1111111111011101;
	6'd04: cin = 16'b0000000000000000;
	6'd05: cin = 16'b0000000000110011;
	6'd06: cin = 16'b0000000000100110;
	6'd07: cin = 16'b1111111111010001;
	6'd08: cin = 16'b1111111110100100;
	6'd09: cin = 16'b0000000000000000;
	6'd10: cin = 16'b0000000010000110;
	6'd11: cin = 16'b0000000001100011;
	6'd12: cin = 16'b1111111110001011;
	6'd13: cin = 16'b1111111100100001;
	6'd14: cin = 16'b0000000000000000;
	6'd15: cin = 16'b0000000100110000;
	6'd16: cin = 16'b0000000011011010;
	6'd17: cin = 16'b1111111100000100;
	6'd18: cin = 16'b1111111000101000;
	6'd19: cin = 16'b0000000000000000;
	6'd20: cin = 16'b0000001001110100;
	6'd21: cin = 16'b0000000111000001;
	6'd22: cin = 16'b1111110111110111;
	6'd23: cin = 16'b1111110000101000;
	6'd24: cin = 16'b0000000000000000;
	6'd25: cin = 16'b0000010101100110;
	6'd26: cin = 16'b0000010000001110;
	6'd27: cin = 16'b1111101011101101;
	6'd28: cin = 16'b1111010100111111;
	6'd29: cin = 16'b0000000000000000;
	6'd30: cin = 16'b0001100110101100;
	6'd31: cin = 16'b0010111111010010;
	6'd32: cin = 16'b0010111111010010;
	6'd33: cin = 16'b0001100110101100;
	6'd34: cin = 16'b0000000000000000;
	6'd35: cin = 16'b1111010100111111;
	6'd36: cin = 16'b1111101011101101;
	6'd37: cin = 16'b0000010000001110;
	6'd38: cin = 16'b0000010101100110;
	6'd39: cin = 16'b0000000000000000;
	6'd40: cin = 16'b1111110000101000;
	6'd41: cin = 16'b1111110111110111;
	6'd42: cin = 16'b0000000111000001;
	6'd43: cin = 16'b0000001001110100;
	6'd44: cin = 16'b0000000000000000;
	6'd45: cin = 16'b1111111000101000;
	6'd46: cin = 16'b1111111100000100;
	6'd47: cin = 16'b0000000011011010;
	6'd48: cin = 16'b0000000100110000;
	6'd49: cin = 16'b0000000000000000;
	6'd50: cin = 16'b1111111100100001;
	6'd51: cin = 16'b1111111110001011;
	6'd52: cin = 16'b0000000001100011;
	6'd53: cin = 16'b0000000010000110;
	6'd54: cin = 16'b0000000000000000;
	6'd55: cin = 16'b1111111110100100;
	6'd56: cin = 16'b1111111111010001;
	6'd57: cin = 16'b0000000000100110;
	6'd58: cin = 16'b0000000000110011;
	6'd59: cin = 16'b0000000000000000;
	6'd60: cin = 16'b1111111111011101;
	6'd61: cin = 16'b1111111111101101;
	6'd62: cin = 16'b0000000000010001;
	6'd63: cin = 16'b0000000000011001;
	endcase
end


reg [9:0] daddr;
always @* begin
	case(daddr[5:0])
	6'd0:din = 0000000000000000;
	6'd1:din = 0000000001011111;
	6'd2:din = 0000000000111011;
	6'd3:din = 1111111111000101;
	6'd4:din = 1111111110100001;
	6'd5:din = 0000000000000000;
	6'd6:din = 0000000001011111;
	6'd7:din = 0000000000111011;
	6'd8:din = 1111111111000101;
	6'd9:din = 1111111110100001;
	6'd10:din = 0000000000000000;
	6'd11:din = 0000000001011111;
	6'd12:din = 0000000000111011;
	6'd13:din = 1111111111000101;
	6'd14:din = 1111111110100001;
	6'd15:din = 0000000000000000;
	6'd16:din = 0000000001011111;
	6'd17:din = 0000000000111011;
	6'd18:din = 1111111111000101;
	6'd19:din = 1111111110100001;
	6'd20:din = 0000000000000000;
	6'd21:din = 0000000001011111;
	6'd22:din = 0000000000111011;
	6'd23:din = 1111111111000101;
	6'd24:din = 1111111110100001;
	6'd25:din = 0000000000000000;
	6'd26:din = 0000000001011111;
	6'd27:din = 0000000000111011;
	6'd28:din = 1111111111000101;
	6'd29:din = 1111111110100001;
	6'd30:din = 0000000000000000;
	6'd31:din = 0000000001011111;
	6'd32:din = 0000000000111011;
	6'd33:din = 1111111111000101;
	6'd34:din = 1111111110100001;
	6'd35:din = 0000000000000000;
	6'd36:din = 0000000001011111;
	6'd37:din = 0000000000111011;
	6'd38:din = 1111111111000101;
	6'd39:din = 1111111110100001;
	6'd40:din = 0000000000000000;
	6'd41:din = 0000000001011111;
	6'd42:din = 0000000000111011;
	6'd43:din = 1111111111000101;
	6'd44:din = 1111111110100001;
	6'd45:din = 0000000000000000;
	6'd46:din = 0000000001011111;
	6'd47:din = 0000000000111011;
	6'd48:din = 1111111111000101;
	6'd49:din = 1111111110100001;
	6'd50:din = 0000000000000000;
	6'd51:din = 0000000001011111;
	6'd52:din = 0000000000111011;
	6'd53:din = 1111111111000101;
	6'd54:din = 1111111110100001;
	6'd55:din = 0000000000000000;
	6'd56:din = 0000000001011111;
	6'd57:din = 0000000000111011;
	6'd58:din = 1111111111000101;
	6'd59:din = 1111111110100001;
	6'd60:din = 0000000000000000;
	6'd61:din = 0000000001011111;
	6'd62:din = 0000000000111011;
	6'd63:din = 1111111111000101;
	endcase
end

always @(posedge clk_slow or negedge rst_n) begin
	if(~rst_n) daddr <= 0;
	else       daddr <= daddr + 1;
end

W4822_FIR dut (
    .rst_n(rst_n),
    .clk_slow(clk_slow),
    .clk(clk_fast),
    .din(din),
    .valid_in(0'b0),
    .cin(cin),
    .caddr(caddr),
    .cload(cload),
    .dout(),
    .valid()
);

endmodule