data/full_repos/permissive/511828706/sonic.v
data/verilator_xmls/ec664830-cedf-4d9e-b8bb-f92e8a758b1b.xml
module sonic # (parameter WIDTH = 30)
(
	input clk,
	input echo,
	input [WIDTH-1:0] counter,
	output reg trig,
	output reg [WIDTH-1:0] data
);


	reg [WIDTH-1:0] pulse_start;
	reg echohigh;
	always @(posedge clk) begin
		if (counter == 1) begin
			trig <= 1;
		end else if (counter == 50) begin

			trig <= 0;
		end 
		if (echohigh == 0 && echo == 1) begin
			pulse_start <= counter;
			echohigh <= 1;
		end else if (echohigh == 1 && echo == 0) begin

			echohigh <= 0;
			data <= (counter-pulse_start);
		end
	end
endmodule
module sonic # (parameter WIDTH = 30)
(
	input clk,
	input echo,
	input [WIDTH-1:0] counter,
	output reg trig,
	output reg [WIDTH-1:0] data
);



	reg [WIDTH-1:0] pulse_start;
	reg echohigh;
	always @(posedge clk) begin
		if (counter == 1) begin
			trig <= 1;
		end else if (counter == 50) begin

			trig <= 0;
		end 
		if (echohigh == 0 && echo == 1) begin
			pulse_start <= counter;
			echohigh <= 1;
		end else if (echohigh == 1 && echo == 0) begin

			echohigh <= 0;
			data <= (counter-pulse_start);
		end
	end
endmodule