data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/tb_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/tb_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/tb_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 


wire    a, b, cin, f1, f0;
wire    cout, res; 

alu1bit_test tester (.t1(a), .t2(b), .t3(cin), .t4(f1), .t5(f0), .p1(cout), .p2(res));


alu1bit         dut (.A(a), .B(b), .CIN(cin), .F1(f1), .F0(f0), .COUT(cout), .RES(res));  



always @(a or b or cin or f1 or f0 or cout or res )

begin
    #1;
    $display("%b %b %b %b%b %b %b", a, b, cin, f1, f0, res, cout);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars;
end

endmodule
module tb_testbench;
 


wire    a, b, cin, f1, f0;
wire    cout, res; 

alu1bit_test tester (.t1(a), .t2(b), .t3(cin), .t4(f1), .t5(f0), .p1(cout), .p2(res));


alu1bit         dut (.A(a), .B(b), .CIN(cin), .F1(f1), .F0(f0), .COUT(cout), .RES(res));  



always @(a or b or cin or f1 or f0 or cout or res )

begin
    #1;
    $display("%b %b %b %b%b %b %b", a, b, cin, f1, f0, res, cout);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars;
end

endmodule