data/full_repos/permissive/517906272/syn_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/517906272/syn_fifo.v:24: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'wp\' generates 3 bits.\n                                                                  : ... In instance syn_fifo\n        if(wp==depth-1 && rp==\'d0)\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517906272/syn_fifo.v:38: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'rp\' generates 3 bits.\n                                                                  : ... In instance syn_fifo\n        if(rp==depth-1)\n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module syn_fifo(clk,rst,we,re,data,read_data);

parameter pointer_size='d3,depth='d8,width='d4;

reg [pointer_size-1:0] wp,rp; 
input clk,rst,we,re;
reg[width-1:0] fifo[depth-1:0];
input[width-1:0] data;
integer i;
output reg [width-1:0] read_data;

always @(posedge clk)
begin
    
    if(rst) 
    begin
        for(i=0;i<=depth-1;i=i+1)
        fifo[i]='d0;
        wp='d0;
        rp='d0;
    end
    else if(we)
    begin
        if(wp==depth-1 && rp=='d0)
        begin
            fifo[wp]=data;
            wp=0; 
            $display("fifo is full");
        end
        else
        begin
            fifo[wp]=data;
            wp=wp+1;
        end
    end
    else if(re)
    begin
        if(rp==depth-1)
        begin
            $display("fifo is empty");
            read_data=fifo[rp];
            fifo[rp]='d0;
            rp=0;
        end
        else
        begin
            read_data=fifo[rp];
            fifo[rp]='d0; 
            rp=rp+1;
        end
    end
    else
    begin
        wp=wp;
        rp=rp;
        $display("No Operation");
    end
end

endmodule
module syn_fifo(clk,rst,we,re,data,read_data);


parameter pointer_size='d3,depth='d8,width='d4;

reg [pointer_size-1:0] wp,rp; 
input clk,rst,we,re;
reg[width-1:0] fifo[depth-1:0];
input[width-1:0] data;
integer i;
output reg [width-1:0] read_data;

always @(posedge clk)
begin
    
    if(rst) 
    begin
        for(i=0;i<=depth-1;i=i+1)
        fifo[i]='d0;
        wp='d0;
        rp='d0;
    end
    else if(we)
    begin
        if(wp==depth-1 && rp=='d0)
        begin
            fifo[wp]=data;
            wp=0; 
            $display("fifo is full");
        end
        else
        begin
            fifo[wp]=data;
            wp=wp+1;
        end
    end
    else if(re)
    begin
        if(rp==depth-1)
        begin
            $display("fifo is empty");
            read_data=fifo[rp];
            fifo[rp]='d0;
            rp=0;
        end
        else
        begin
            read_data=fifo[rp];
            fifo[rp]='d0; 
            rp=rp+1;
        end
    end
    else
    begin
        wp=wp;
        rp=rp;
        $display("No Operation");
    end
end

endmodule