data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v
data/verilator_xmls/f5f1872e-e0a8-45fb-af2b-25f74a31a1f1.xml
module tri_buf (a,b,enable);
 input a;
 output b;
 input enable;
 wire b;
 
assign b = (enable) ? a : 1'bz;
  	  	 
endmodule
module tri_buf (a,b,enable);

 input a;
 output b;
 input enable;
 wire b;
 
assign b = (enable) ? a : 1'bz;
  	  	 
endmodule