data/full_repos/permissive/449071180/clk_divider_game.v
data/verilator_xmls/cbc028e3-6b1f-4d69-be1d-324f775fe210.xml
module clk_divider_game(clk_50Mhz, rst, clk1hz);

input clk_50Mhz,rst;

output reg clk1hz;

reg [21:0] count;

always@(posedge clk_50Mhz,  posedge rst) begin

if(rst == 1)begin
count <= 22'b0;
clk1hz <= 0;
end
else if(count == 2499999) begin
count <= 22'b0;
clk1hz <= ~clk1hz;
end

else begin
count <= count + 22'b1;
clk1hz <= clk1hz;
end


end

endmodule
module clk_divider_game(clk_50Mhz, rst, clk1hz);


input clk_50Mhz,rst;

output reg clk1hz;

reg [21:0] count;

always@(posedge clk_50Mhz,  posedge rst) begin

if(rst == 1)begin
count <= 22'b0;
clk1hz <= 0;
end
else if(count == 2499999) begin
count <= 22'b0;
clk1hz <= ~clk1hz;
end

else begin
count <= count + 22'b1;
clk1hz <= clk1hz;
end


end

endmodule