data/full_repos/permissive/493019833/test/testcase/firrtl/DynamicMemorySearchTests1/sbt/DynamicMemorySearchTests1.v
data/verilator_xmls/218cf90e-a765-4c10-a7a2-4eb535c872c4.xml
module DynamicMemorySearch(
  input        clock,
  input        reset,
  input        io_isWr,
  input  [2:0] io_wrAddr,
  input  [3:0] io_data,
  input        io_en,
  output [2:0] io_target,
  output       io_done
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
`endif
  reg [3:0] list [0:7];
  wire  list_memVal_en;
  wire [2:0] list_memVal_addr;
  wire [3:0] list_memVal_data;
  wire [3:0] list__T_19_data;
  wire [2:0] list__T_19_addr;
  wire  list__T_19_mask;
  wire  list__T_19_en;
  wire [3:0] list__T_22_data;
  wire [2:0] list__T_22_addr;
  wire  list__T_22_mask;
  wire  list__T_22_en;
  wire [3:0] list__T_25_data;
  wire [2:0] list__T_25_addr;
  wire  list__T_25_mask;
  wire  list__T_25_en;
  wire [3:0] list__T_28_data;
  wire [2:0] list__T_28_addr;
  wire  list__T_28_mask;
  wire  list__T_28_en;
  wire [3:0] list__T_31_data;
  wire [2:0] list__T_31_addr;
  wire  list__T_31_mask;
  wire  list__T_31_en;
  wire [3:0] list__T_34_data;
  wire [2:0] list__T_34_addr;
  wire  list__T_34_mask;
  wire  list__T_34_en;
  wire [3:0] list__T_37_data;
  wire [2:0] list__T_37_addr;
  wire  list__T_37_mask;
  wire  list__T_37_en;
  wire [3:0] list__T_40_data;
  wire [2:0] list__T_40_addr;
  wire  list__T_40_mask;
  wire  list__T_40_en;
  wire [3:0] list__T_42_data;
  wire [2:0] list__T_42_addr;
  wire  list__T_42_mask;
  wire  list__T_42_en;
  reg [2:0] index;
  wire  _T_13 = ~io_en;
  wire  over = ~io_en & (list_memVal_data == io_data | index == 3'h7);
  wire  _T_44 = ~io_isWr;
  wire  _T_53 = _T_44 & _T_13;
  wire [2:0] _T_57 = index + 3'h1;
  assign list_memVal_en = 1'h1;
  assign list_memVal_addr = index;
  assign list_memVal_data = list[list_memVal_addr];
  assign list__T_19_data = 4'h0;
  assign list__T_19_addr = 3'h0;
  assign list__T_19_mask = 1'h1;
  assign list__T_19_en = reset;
  assign list__T_22_data = 4'h0;
  assign list__T_22_addr = 3'h1;
  assign list__T_22_mask = 1'h1;
  assign list__T_22_en = reset;
  assign list__T_25_data = 4'h0;
  assign list__T_25_addr = 3'h2;
  assign list__T_25_mask = 1'h1;
  assign list__T_25_en = reset;
  assign list__T_28_data = 4'h0;
  assign list__T_28_addr = 3'h3;
  assign list__T_28_mask = 1'h1;
  assign list__T_28_en = reset;
  assign list__T_31_data = 4'h0;
  assign list__T_31_addr = 3'h4;
  assign list__T_31_mask = 1'h1;
  assign list__T_31_en = reset;
  assign list__T_34_data = 4'h0;
  assign list__T_34_addr = 3'h5;
  assign list__T_34_mask = 1'h1;
  assign list__T_34_en = reset;
  assign list__T_37_data = 4'h0;
  assign list__T_37_addr = 3'h6;
  assign list__T_37_mask = 1'h1;
  assign list__T_37_en = reset;
  assign list__T_40_data = 4'h0;
  assign list__T_40_addr = 3'h7;
  assign list__T_40_mask = 1'h1;
  assign list__T_40_en = reset;
  assign list__T_42_data = io_data;
  assign list__T_42_addr = io_wrAddr;
  assign list__T_42_mask = 1'h1;
  assign list__T_42_en = io_isWr;
  assign io_target = index;
  assign io_done = ~io_en & (list_memVal_data == io_data | index == 3'h7);
  always @(posedge clock) begin
    if (list__T_19_en & list__T_19_mask) begin
      list[list__T_19_addr] <= list__T_19_data;
    end
    if (list__T_22_en & list__T_22_mask) begin
      list[list__T_22_addr] <= list__T_22_data;
    end
    if (list__T_25_en & list__T_25_mask) begin
      list[list__T_25_addr] <= list__T_25_data;
    end
    if (list__T_28_en & list__T_28_mask) begin
      list[list__T_28_addr] <= list__T_28_data;
    end
    if (list__T_31_en & list__T_31_mask) begin
      list[list__T_31_addr] <= list__T_31_data;
    end
    if (list__T_34_en & list__T_34_mask) begin
      list[list__T_34_addr] <= list__T_34_data;
    end
    if (list__T_37_en & list__T_37_mask) begin
      list[list__T_37_addr] <= list__T_37_data;
    end
    if (list__T_40_en & list__T_40_mask) begin
      list[list__T_40_addr] <= list__T_40_data;
    end
    if (list__T_42_en & list__T_42_mask) begin
      list[list__T_42_addr] <= list__T_42_data;
    end
    if (reset) begin
      index <= 3'h0;
    end else if (_T_53 & ~over) begin
      index <= _T_57;
    end else if (_T_44 & io_en) begin
      index <= 3'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    list[initvar] = _RAND_0[3:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  index = _RAND_1[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module DynamicMemorySearch(
  input        clock,
  input        reset,
  input        io_isWr,
  input  [2:0] io_wrAddr,
  input  [3:0] io_data,
  input        io_en,
  output [2:0] io_target,
  output       io_done
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
`endif
  reg [3:0] list [0:7];
  wire  list_memVal_en;
  wire [2:0] list_memVal_addr;
  wire [3:0] list_memVal_data;
  wire [3:0] list__T_19_data;
  wire [2:0] list__T_19_addr;
  wire  list__T_19_mask;
  wire  list__T_19_en;
  wire [3:0] list__T_22_data;
  wire [2:0] list__T_22_addr;
  wire  list__T_22_mask;
  wire  list__T_22_en;
  wire [3:0] list__T_25_data;
  wire [2:0] list__T_25_addr;
  wire  list__T_25_mask;
  wire  list__T_25_en;
  wire [3:0] list__T_28_data;
  wire [2:0] list__T_28_addr;
  wire  list__T_28_mask;
  wire  list__T_28_en;
  wire [3:0] list__T_31_data;
  wire [2:0] list__T_31_addr;
  wire  list__T_31_mask;
  wire  list__T_31_en;
  wire [3:0] list__T_34_data;
  wire [2:0] list__T_34_addr;
  wire  list__T_34_mask;
  wire  list__T_34_en;
  wire [3:0] list__T_37_data;
  wire [2:0] list__T_37_addr;
  wire  list__T_37_mask;
  wire  list__T_37_en;
  wire [3:0] list__T_40_data;
  wire [2:0] list__T_40_addr;
  wire  list__T_40_mask;
  wire  list__T_40_en;
  wire [3:0] list__T_42_data;
  wire [2:0] list__T_42_addr;
  wire  list__T_42_mask;
  wire  list__T_42_en;
  reg [2:0] index;
  wire  _T_13 = ~io_en;
  wire  over = ~io_en & (list_memVal_data == io_data | index == 3'h7);
  wire  _T_44 = ~io_isWr;
  wire  _T_53 = _T_44 & _T_13;
  wire [2:0] _T_57 = index + 3'h1;
  assign list_memVal_en = 1'h1;
  assign list_memVal_addr = index;
  assign list_memVal_data = list[list_memVal_addr];
  assign list__T_19_data = 4'h0;
  assign list__T_19_addr = 3'h0;
  assign list__T_19_mask = 1'h1;
  assign list__T_19_en = reset;
  assign list__T_22_data = 4'h0;
  assign list__T_22_addr = 3'h1;
  assign list__T_22_mask = 1'h1;
  assign list__T_22_en = reset;
  assign list__T_25_data = 4'h0;
  assign list__T_25_addr = 3'h2;
  assign list__T_25_mask = 1'h1;
  assign list__T_25_en = reset;
  assign list__T_28_data = 4'h0;
  assign list__T_28_addr = 3'h3;
  assign list__T_28_mask = 1'h1;
  assign list__T_28_en = reset;
  assign list__T_31_data = 4'h0;
  assign list__T_31_addr = 3'h4;
  assign list__T_31_mask = 1'h1;
  assign list__T_31_en = reset;
  assign list__T_34_data = 4'h0;
  assign list__T_34_addr = 3'h5;
  assign list__T_34_mask = 1'h1;
  assign list__T_34_en = reset;
  assign list__T_37_data = 4'h0;
  assign list__T_37_addr = 3'h6;
  assign list__T_37_mask = 1'h1;
  assign list__T_37_en = reset;
  assign list__T_40_data = 4'h0;
  assign list__T_40_addr = 3'h7;
  assign list__T_40_mask = 1'h1;
  assign list__T_40_en = reset;
  assign list__T_42_data = io_data;
  assign list__T_42_addr = io_wrAddr;
  assign list__T_42_mask = 1'h1;
  assign list__T_42_en = io_isWr;
  assign io_target = index;
  assign io_done = ~io_en & (list_memVal_data == io_data | index == 3'h7);
  always @(posedge clock) begin
    if (list__T_19_en & list__T_19_mask) begin
      list[list__T_19_addr] <= list__T_19_data;
    end
    if (list__T_22_en & list__T_22_mask) begin
      list[list__T_22_addr] <= list__T_22_data;
    end
    if (list__T_25_en & list__T_25_mask) begin
      list[list__T_25_addr] <= list__T_25_data;
    end
    if (list__T_28_en & list__T_28_mask) begin
      list[list__T_28_addr] <= list__T_28_data;
    end
    if (list__T_31_en & list__T_31_mask) begin
      list[list__T_31_addr] <= list__T_31_data;
    end
    if (list__T_34_en & list__T_34_mask) begin
      list[list__T_34_addr] <= list__T_34_data;
    end
    if (list__T_37_en & list__T_37_mask) begin
      list[list__T_37_addr] <= list__T_37_data;
    end
    if (list__T_40_en & list__T_40_mask) begin
      list[list__T_40_addr] <= list__T_40_data;
    end
    if (list__T_42_en & list__T_42_mask) begin
      list[list__T_42_addr] <= list__T_42_data;
    end
    if (reset) begin
      index <= 3'h0;
    end else if (_T_53 & ~over) begin
      index <= _T_57;
    end else if (_T_44 & io_en) begin
      index <= 3'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    list[initvar] = _RAND_0[3:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  index = _RAND_1[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule