data/full_repos/permissive/485026242/Lock-system/counter.v
data/verilator_xmls/70a457bd-efbc-4a0a-89ba-cb81b0f3d8a2.xml
module counter(clk,check,rstn,cnt,Access,Alarm);
    parameter N=4;
    input clk,rstn;
  input [11:0] check;
    output reg Access,Alarm;
    output reg  [1:0] cnt;
    initial begin 
    cnt=0;Access=0;Alarm=0;
    end 
    always @(posedge clk or posedge rstn)
        begin    
          if(check==12'h0) begin
            Access<=1;
            Alarm<=0;
            cnt<=0;
          end
          else if(check!=12'h0 & cnt==0)
            begin
            cnt<=cnt+1;
            Access<=0;
            Alarm<=0;
            end
          else if(check!=12'h0)
            begin
            if(cnt==1)
                begin
                Alarm<=0;
                Access<=0;
                cnt<=cnt+1;
                end
            if(cnt==2)
                begin
                Alarm<=1;
                Access<=0;
                cnt<=cnt+1;
                end
            if(cnt==3)
                begin
                Alarm<=1;
                Access<=0;
                cnt<=3;
                end
            end
          if(rstn==1)
            begin
            Alarm<=0;
            cnt<=0;
            Access<=0;
            end
        end
endmodule
module counter(clk,check,rstn,cnt,Access,Alarm);

    parameter N=4;
    input clk,rstn;
  input [11:0] check;
    output reg Access,Alarm;
    output reg  [1:0] cnt;
    initial begin 
    cnt=0;Access=0;Alarm=0;
    end 
    always @(posedge clk or posedge rstn)
        begin    
          if(check==12'h0) begin
            Access<=1;
            Alarm<=0;
            cnt<=0;
          end
          else if(check!=12'h0 & cnt==0)
            begin
            cnt<=cnt+1;
            Access<=0;
            Alarm<=0;
            end
          else if(check!=12'h0)
            begin
            if(cnt==1)
                begin
                Alarm<=0;
                Access<=0;
                cnt<=cnt+1;
                end
            if(cnt==2)
                begin
                Alarm<=1;
                Access<=0;
                cnt<=cnt+1;
                end
            if(cnt==3)
                begin
                Alarm<=1;
                Access<=0;
                cnt<=3;
                end
            end
          if(rstn==1)
            begin
            Alarm<=0;
            cnt<=0;
            Access<=0;
            end
        end
endmodule