data/full_repos/permissive/524553217/src/branch.v
data/verilator_xmls/e2c37b25-08d6-4c6a-9b05-f2d5bcc84a34.xml
module branch(
    input [9:0] branch_inst,
    input [31:0] rs1_v,
    input [31:0] rs2_v,
    output reg branch_e
    );
    
    always @(*) begin
        case(branch_inst[6:0])
            7'b1100011: begin
                case(branch_inst[9:7])
                    3'b000:
                        branch_e = (rs1_v == rs2_v) ? 1 : 0;
                    3'b001:
                        branch_e = (rs1_v == rs2_v) ? 0 : 1;
                    3'b100:
                        branch_e = ($signed(rs1_v) < $signed(rs2_v)) ? 1 : 0;
                    3'b101:
                        branch_e = ($signed(rs1_v) < $signed(rs2_v)) ? 0 : 1;
                    3'b110:
                        branch_e = (rs1_v < rs2_v) ? 1 : 0;
                    3'b111:
                        branch_e = (rs1_v < rs2_v) ? 0 : 1;
                    default:
                        branch_e = 0;
                endcase
            end
            default:
                branch_e = 0;
        endcase
    end
endmodule
module branch(
    input [9:0] branch_inst,
    input [31:0] rs1_v,
    input [31:0] rs2_v,
    output reg branch_e
    );

    
    always @(*) begin
        case(branch_inst[6:0])
            7'b1100011: begin
                case(branch_inst[9:7])
                    3'b000:
                        branch_e = (rs1_v == rs2_v) ? 1 : 0;
                    3'b001:
                        branch_e = (rs1_v == rs2_v) ? 0 : 1;
                    3'b100:
                        branch_e = ($signed(rs1_v) < $signed(rs2_v)) ? 1 : 0;
                    3'b101:
                        branch_e = ($signed(rs1_v) < $signed(rs2_v)) ? 0 : 1;
                    3'b110:
                        branch_e = (rs1_v < rs2_v) ? 1 : 0;
                    3'b111:
                        branch_e = (rs1_v < rs2_v) ? 0 : 1;
                    default:
                        branch_e = 0;
                endcase
            end
            default:
                branch_e = 0;
        endcase
    end
endmodule