data/full_repos/permissive/520487363/EX1 - Clock and Periodic Signal Generation/PashaBarahimi/FPGA Design/UART/ABRCKT_Datapath.v
1: b'%Error: Invalid Option: -\n'
module ABRCKT_Datapath (input cnt_en, cnt_rst, ld_en, clk, rst, output [7:0] count, N);
    wire [7:0] cntOut;
    assign count = cntOut;
    NBitCounter #(.N(8)) counter(clk, rst, cnt_en, cnt_rst, cntOut);
    NBitRegister #(.N(8)) register(cntOut, ld_en, clk, rst, N);
endmodule
module ABRCKT_Datapath (input cnt_en, cnt_rst, ld_en, clk, rst, output [7:0] count, N);

    wire [7:0] cntOut;
    assign count = cntOut;
    NBitCounter #(.N(8)) counter(clk, rst, cnt_en, cnt_rst, cntOut);
    NBitRegister #(.N(8)) register(cntOut, ld_en, clk, rst, N);
endmodule