data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v
1: b'%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:12: Cannot find include file: Bitlet_Defs.vh\n`include "Bitlet_Defs.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.v\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Defs.vh.sv\n             Bitlet_Defs.vh\n             Bitlet_Defs.vh.v\n             Bitlet_Defs.vh.sv\n             obj_dir/Bitlet_Defs.vh\n             obj_dir/Bitlet_Defs.vh.v\n             obj_dir/Bitlet_Defs.vh.sv\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:25: Define or directive not defined: \'`Wid_exp\'\n    input   [N_total*`Wid_exp-1:0]  Wexp_vec,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:26: Define or directive not defined: \'`Wid_abs\'\n    input   [N_total*`Wid_abs-1:0]  Wabs_vec,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:28: Define or directive not defined: \'`Wid_bin\'\n    input   [N_input*`Wid_bin-1:0]  Abin_vec,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:30: Define or directive not defined: \'`Wid_exs\'\n    output  [`Wid_exs-1:0]          Emax,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:32: Define or directive not defined: \'`Wid_fix\'\n    output  [N_total*`Wid_fix-1:0]  Afix_buff,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:33: Define or directive not defined: \'`Wid_abs\'\n    output  [N_total*`Wid_abs-1:0]  Wabs_buff\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:37: Define or directive not defined: \'`N_check\'\nlocalparam  N_align = `N_check;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nlocalparam  N_align = `N_check;\n                              ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:52: Define or directive not defined: \'`Wid_exs\'\nwire    [N_input*`Wid_exs-1:0]  Esum_dasm;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:53: Define or directive not defined: \'`Wid_fix\'\nwire    [N_input*`Wid_fix-1:0]  Afix_dasm;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:55: Define or directive not defined: \'`Wid_exp\'\nwire    [N_input*`Wid_exp-1:0]  Wexp_sel;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:59: Define or directive not defined: \'`Wid_exp\'\nassign  Wexp_sel    = Wexp_vec[(input_cnt*N_input*`Wid_exp)+:(N_input*`Wid_exp)];\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign  Wexp_sel    = Wexp_vec[(input_cnt*N_input*`Wid_exp)+:(N_input*`Wid_exp)];\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:59: Define or directive not defined: \'`Wid_exp\'\nassign  Wexp_sel    = Wexp_vec[(input_cnt*N_input*`Wid_exp)+:(N_input*`Wid_exp)];\n                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:77: Define or directive not defined: \'`Wid_exs\'\nwire    [N_total*`Wid_exs-1:0]  Esum_buff;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:94: Define or directive not defined: \'`Wid_exs\'\nBitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_exs)) UBUFFERESUM\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:94: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nBitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_exs)) UBUFFERESUM\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:112: Define or directive not defined: \'`Wid_fix\'\nBitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_fix)) UBUFFERAFIX\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:112: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nBitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_fix)) UBUFFERAFIX\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:124: Define or directive not defined: \'`Wid_exs\'\nwire    [N_input*`Wid_exs-1:0]  Esum_check;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:134: Define or directive not defined: \'`Wid_exs\'\nassign  Esum_check  = Esum_buff[(ckmax_cnt*N_input*`Wid_exs)+:(N_input*`Wid_exs)];\n                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:134: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign  Esum_check  = Esum_buff[(ckmax_cnt*N_input*`Wid_exs)+:(N_input*`Wid_exs)];\n                                                           ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:134: Define or directive not defined: \'`Wid_exs\'\nassign  Esum_check  = Esum_buff[(ckmax_cnt*N_input*`Wid_exs)+:(N_input*`Wid_exs)];\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:148: Define or directive not defined: \'`Wid_abs\'\nwire    [N_align*`Wid_abs-1:0]  Wabs_sel;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:149: Define or directive not defined: \'`Wid_exs\'\nwire    [N_align*`Wid_exs-1:0]  Esum_align;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:150: Define or directive not defined: \'`Wid_abs\'\nwire    [N_align*`Wid_abs-1:0]  Walign_vec;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:154: Define or directive not defined: \'`Wid_abs\'\nassign  Wabs_sel    = Wabs_vec[(align_cnt*N_align*`Wid_abs)+:(N_align*`Wid_abs)];\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:154: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign  Wabs_sel    = Wabs_vec[(align_cnt*N_align*`Wid_abs)+:(N_align*`Wid_abs)];\n                                                          ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:154: Define or directive not defined: \'`Wid_abs\'\nassign  Wabs_sel    = Wabs_vec[(align_cnt*N_align*`Wid_abs)+:(N_align*`Wid_abs)];\n                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:155: Define or directive not defined: \'`Wid_exs\'\nassign  Esum_align  = Esum_buff[(align_cnt*N_align*`Wid_exs)+:(N_align*`Wid_exs)];\n                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:155: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign  Esum_align  = Esum_buff[(align_cnt*N_align*`Wid_exs)+:(N_align*`Wid_exs)];\n                                                           ^\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:155: Define or directive not defined: \'`Wid_exs\'\nassign  Esum_align  = Esum_buff[(align_cnt*N_align*`Wid_exs)+:(N_align*`Wid_exs)];\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:204: Define or directive not defined: \'`Wid_abs\'\nBitlet_Prim_BufferArray #(.N(P_align), .W(N_align*`Wid_abs)) UBUFFERWABS\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Preprocessor.v:204: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nBitlet_Prim_BufferArray #(.N(P_align), .W(N_align*`Wid_abs)) UBUFFERWABS\n                                                          ^\n%Error: Exiting due to 35 error(s)\n'
module Bitlet_Preprocessor
#(
    parameter   N_total = 64,
    parameter   N_input = 16
)
(
    input                           clk,
    input                           rst_n,
    input                           isfix,
    input                           flush,
    input   [N_total*1-1:0]         Wsig_vec,
    input   [N_total*`Wid_exp-1:0]  Wexp_vec,
    input   [N_total*`Wid_abs-1:0]  Wabs_vec,
    input                           Abin_vld,
    input   [N_input*`Wid_bin-1:0]  Abin_vec,
    output                          Emax_vld,
    output  [`Wid_exs-1:0]          Emax,
    output                          finish,
    output  [N_total*`Wid_fix-1:0]  Afix_buff,
    output  [N_total*`Wid_abs-1:0]  Wabs_buff
);

localparam  P_input = N_total/N_input;
localparam  N_align = `N_check;
localparam  P_align = N_total/N_align;


reg     [$clog2(P_input)-1:0]   input_cnt;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        input_cnt   <= 'b0;
    else if (Abin_vld)
        input_cnt   <= input_cnt+1;
end


wire    [N_input*`Wid_exs-1:0]  Esum_dasm;
wire    [N_input*`Wid_fix-1:0]  Afix_dasm;
wire    [N_input*1-1:0]         Wsig_sel;
wire    [N_input*`Wid_exp-1:0]  Wexp_sel;
reg                             dasm_vld;

assign  Wsig_sel    = Wsig_vec[(input_cnt*N_input*1)+:(N_input*1)];
assign  Wexp_sel    = Wexp_vec[(input_cnt*N_input*`Wid_exp)+:(N_input*`Wid_exp)];

always @(*)
begin
    dasm_vld    = Abin_vld;
end

Bitlet_ReassemblerArray #(.N_input(N_input)) UDEASSEMBLERARRAY
(
    .isfix(isfix),
    .Wsig_vec(Wsig_sel),
    .Wexp_vec(Wexp_sel),
    .Abin_vec(Abin_vec),
    .Esum_vec(Esum_dasm),
    .Afix_vec(Afix_dasm)
);


wire    [N_total*`Wid_exs-1:0]  Esum_buff;
reg                             Esum_enw;
reg                             Esum_vld;

always @(*)
begin
    Esum_enw    = (!isfix)&dasm_vld;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Esum_vld    <= 'b0;
    else if (Emax_vld!=dasm_vld)
        Esum_vld    <= dasm_vld;
end

Bitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_exs)) UBUFFERESUM
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Esum_enw),
    .sel(input_cnt),
    .DI(Esum_dasm),
    .DO(Esum_buff)
);


reg                             Afix_enw;

always @(*)
begin
    Afix_enw    = dasm_vld;
end

Bitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_fix)) UBUFFERAFIX
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Afix_enw),
    .sel(input_cnt),
    .DI(Afix_dasm),
    .DO(Afix_buff)
);


reg     [$clog2(P_input)-1:0]   ckmax_cnt;
wire    [N_input*`Wid_exs-1:0]  Esum_check;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        ckmax_cnt   <= 'b0;
    else if (ckmax_cnt!=input_cnt)
        ckmax_cnt   <= input_cnt;
end

assign  Esum_check  = Esum_buff[(ckmax_cnt*N_input*`Wid_exs)+:(N_input*`Wid_exs)];

Bitlet_FindMax #(.N_input(N_input), .P_input(P_input)) UFINDMAX
(
    .clk(clk),
    .rst_n(rst_n),
    .flush(flush),
    .Esum_vld(Esum_vld),
    .Esum_vec(Esum_check),
    .Emax_vld(Emax_vld),
    .Emax(Emax)
);


wire    [N_align*`Wid_abs-1:0]  Wabs_sel;
wire    [N_align*`Wid_exs-1:0]  Esum_align;
wire    [N_align*`Wid_abs-1:0]  Walign_vec;
reg     [$clog2(P_align)-1:0]   align_cnt;
reg                             align_vld;

assign  Wabs_sel    = Wabs_vec[(align_cnt*N_align*`Wid_abs)+:(N_align*`Wid_abs)];
assign  Esum_align  = Esum_buff[(align_cnt*N_align*`Wid_exs)+:(N_align*`Wid_exs)];

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        align_cnt   <= 'b0;
    else if (flush)
        align_cnt   <= 'b0;
    else if (align_vld)
        align_cnt   <= align_cnt + 1;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        align_vld   <= 1'b0;
    else if (flush)
        align_vld   <= 1'b0;
    else if (Emax_vld)
        align_vld   <= 1'b1;
    else if (align_cnt==P_align-1)
        align_vld   <= 1'b0;
end

Bitlet_AlignerArray #(.N_align(N_align)) UALIGNERARRAY
(
    .Wabs_vec(Wabs_sel),
    .Esum_vec(Esum_align),
    .Emax(Emax),
    .Walign_vec(Walign_vec)
);


reg                             Wabs_enw;
reg                             Wabs_vld;

always @(*)
begin
    Wabs_enw    = align_vld;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Wabs_vld    <= 1'b0;
    else if (Wabs_vld!=align_vld)
        Wabs_vld    <= align_vld;
end

Bitlet_Prim_BufferArray #(.N(P_align), .W(N_align*`Wid_abs)) UBUFFERWABS
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Wabs_enw),
    .sel(align_cnt),
    .DI(Walign_vec),
    .DO(Wabs_buff)
);


assign  finish  = Wabs_vld;

endmodule
module Bitlet_Preprocessor
#(
    parameter   N_total = 64,
    parameter   N_input = 16
)
(
    input                           clk,
    input                           rst_n,
    input                           isfix,
    input                           flush,
    input   [N_total*1-1:0]         Wsig_vec,
    input   [N_total*`Wid_exp-1:0]  Wexp_vec,
    input   [N_total*`Wid_abs-1:0]  Wabs_vec,
    input                           Abin_vld,
    input   [N_input*`Wid_bin-1:0]  Abin_vec,
    output                          Emax_vld,
    output  [`Wid_exs-1:0]          Emax,
    output                          finish,
    output  [N_total*`Wid_fix-1:0]  Afix_buff,
    output  [N_total*`Wid_abs-1:0]  Wabs_buff
);


localparam  P_input = N_total/N_input;
localparam  N_align = `N_check;
localparam  P_align = N_total/N_align;


reg     [$clog2(P_input)-1:0]   input_cnt;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        input_cnt   <= 'b0;
    else if (Abin_vld)
        input_cnt   <= input_cnt+1;
end


wire    [N_input*`Wid_exs-1:0]  Esum_dasm;
wire    [N_input*`Wid_fix-1:0]  Afix_dasm;
wire    [N_input*1-1:0]         Wsig_sel;
wire    [N_input*`Wid_exp-1:0]  Wexp_sel;
reg                             dasm_vld;

assign  Wsig_sel    = Wsig_vec[(input_cnt*N_input*1)+:(N_input*1)];
assign  Wexp_sel    = Wexp_vec[(input_cnt*N_input*`Wid_exp)+:(N_input*`Wid_exp)];

always @(*)
begin
    dasm_vld    = Abin_vld;
end

Bitlet_ReassemblerArray #(.N_input(N_input)) UDEASSEMBLERARRAY
(
    .isfix(isfix),
    .Wsig_vec(Wsig_sel),
    .Wexp_vec(Wexp_sel),
    .Abin_vec(Abin_vec),
    .Esum_vec(Esum_dasm),
    .Afix_vec(Afix_dasm)
);


wire    [N_total*`Wid_exs-1:0]  Esum_buff;
reg                             Esum_enw;
reg                             Esum_vld;

always @(*)
begin
    Esum_enw    = (!isfix)&dasm_vld;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Esum_vld    <= 'b0;
    else if (Emax_vld!=dasm_vld)
        Esum_vld    <= dasm_vld;
end

Bitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_exs)) UBUFFERESUM
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Esum_enw),
    .sel(input_cnt),
    .DI(Esum_dasm),
    .DO(Esum_buff)
);


reg                             Afix_enw;

always @(*)
begin
    Afix_enw    = dasm_vld;
end

Bitlet_Prim_BufferArray #(.N(P_input), .W(N_input*`Wid_fix)) UBUFFERAFIX
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Afix_enw),
    .sel(input_cnt),
    .DI(Afix_dasm),
    .DO(Afix_buff)
);


reg     [$clog2(P_input)-1:0]   ckmax_cnt;
wire    [N_input*`Wid_exs-1:0]  Esum_check;

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        ckmax_cnt   <= 'b0;
    else if (ckmax_cnt!=input_cnt)
        ckmax_cnt   <= input_cnt;
end

assign  Esum_check  = Esum_buff[(ckmax_cnt*N_input*`Wid_exs)+:(N_input*`Wid_exs)];

Bitlet_FindMax #(.N_input(N_input), .P_input(P_input)) UFINDMAX
(
    .clk(clk),
    .rst_n(rst_n),
    .flush(flush),
    .Esum_vld(Esum_vld),
    .Esum_vec(Esum_check),
    .Emax_vld(Emax_vld),
    .Emax(Emax)
);


wire    [N_align*`Wid_abs-1:0]  Wabs_sel;
wire    [N_align*`Wid_exs-1:0]  Esum_align;
wire    [N_align*`Wid_abs-1:0]  Walign_vec;
reg     [$clog2(P_align)-1:0]   align_cnt;
reg                             align_vld;

assign  Wabs_sel    = Wabs_vec[(align_cnt*N_align*`Wid_abs)+:(N_align*`Wid_abs)];
assign  Esum_align  = Esum_buff[(align_cnt*N_align*`Wid_exs)+:(N_align*`Wid_exs)];

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        align_cnt   <= 'b0;
    else if (flush)
        align_cnt   <= 'b0;
    else if (align_vld)
        align_cnt   <= align_cnt + 1;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        align_vld   <= 1'b0;
    else if (flush)
        align_vld   <= 1'b0;
    else if (Emax_vld)
        align_vld   <= 1'b1;
    else if (align_cnt==P_align-1)
        align_vld   <= 1'b0;
end

Bitlet_AlignerArray #(.N_align(N_align)) UALIGNERARRAY
(
    .Wabs_vec(Wabs_sel),
    .Esum_vec(Esum_align),
    .Emax(Emax),
    .Walign_vec(Walign_vec)
);


reg                             Wabs_enw;
reg                             Wabs_vld;

always @(*)
begin
    Wabs_enw    = align_vld;
end

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        Wabs_vld    <= 1'b0;
    else if (Wabs_vld!=align_vld)
        Wabs_vld    <= align_vld;
end

Bitlet_Prim_BufferArray #(.N(P_align), .W(N_align*`Wid_abs)) UBUFFERWABS
(
    .clk(clk),
    .rst_n(rst_n),
    .enw(Wabs_enw),
    .sel(align_cnt),
    .DI(Walign_vec),
    .DO(Wabs_buff)
);


assign  finish  = Wabs_vld;

endmodule