data/full_repos/permissive/507203156/03-源代码/sift_tb/tf_sift_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_sift_top.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_sift_top.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk_sys=~clk_sys;\n  ^\n%Error: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_sift_top.v:17: Cannot find file containing module: \'sift_top\'\n sift_top uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top.v\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top.sv\n             sift_top\n             sift_top.v\n             sift_top.sv\n             obj_dir/sift_top\n             obj_dir/sift_top.v\n             obj_dir/sift_top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_sift_top;


	reg clk_sys;
	reg rst_sys;


	wire complete3;
	wire [7:0] desc_out;
	wire complete1;


	sift_top uut (
		.clk_sys(clk_sys), 
		.rst_sys(rst_sys), 
		.complete3(complete3), 
		.desc_out(desc_out), 
		.complete1(complete1)
	);

	initial begin

		clk_sys = 0;
		rst_sys = 0;


		#100;
		rst_sys=1;
        


	end
	
	always
	begin
		#5 clk_sys=~clk_sys;
	end
      
endmodule
module tf_sift_top;



	reg clk_sys;
	reg rst_sys;


	wire complete3;
	wire [7:0] desc_out;
	wire complete1;


	sift_top uut (
		.clk_sys(clk_sys), 
		.rst_sys(rst_sys), 
		.complete3(complete3), 
		.desc_out(desc_out), 
		.complete1(complete1)
	);

	initial begin

		clk_sys = 0;
		rst_sys = 0;


		#100;
		rst_sys=1;
        


	end
	
	always
	begin
		#5 clk_sys=~clk_sys;
	end
      
endmodule