data/full_repos/permissive/458935738/common/ir_modules.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458935738/common/ir_modules.v:152: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                            : ... In instance IRcontrol.ch7\n            ttd <= timerttd[15:0];\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:27: Cannot find file containing module: \'pwm\'\n    pwm irevenLED (clk, ir_evenLED_en, 16\'d16000, ir_evenLED);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.v\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:28: Cannot find file containing module: \'pwm\'\n    pwm iroddLED (clk, ir_oddLED_en, 16\'d16000, ir_oddLED);\n    ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module IRcontrol (
    input wire clk,
    input wire [7:0] channel_sel,
    
    inout wire ir_snsrch0, ir_snsrch1, ir_snsrch2, ir_snsrch3,
            ir_snsrch4, ir_snsrch5, ir_snsrch6, ir_snsrch7,
    output wire[16:0] ttd0, ttd1, ttd2, ttd3, ttd4, ttd5, ttd6, ttd7,
    output wire ir_evenLED, ir_oddLED
    );
    

    wire ir_evenLED_en, ir_oddLED_en;
    




    
    
    pwm irevenLED (clk, ir_evenLED_en, 16'd16000, ir_evenLED);
    pwm iroddLED (clk, ir_oddLED_en, 16'd16000, ir_oddLED);
    
    IRread ch0 (clk, channel_sel[0], ir_snsrch0, ttd0);
    IRread ch1 (clk, channel_sel[1], ir_snsrch1, ttd1);
    IRread ch2 (clk, channel_sel[2], ir_snsrch2, ttd2);
    IRread ch3 (clk, channel_sel[3], ir_snsrch3, ttd3);
    IRread ch4 (clk, channel_sel[4], ir_snsrch4, ttd4);
    IRread ch5 (clk, channel_sel[5], ir_snsrch5, ttd5);
    IRread ch6 (clk, channel_sel[6], ir_snsrch6, ttd6);
    IRread ch7 (clk, channel_sel[7], ir_snsrch7, ttd7);
    


    assign ir_evenLED_en = channel_sel[0] | channel_sel[2] | channel_sel[4] | channel_sel[6];
    assign ir_oddLED_en = channel_sel[1] | channel_sel[3] | channel_sel[5] | channel_sel[7];
    
endmodule
module IRcontrol (
    input wire clk,
    input wire [7:0] channel_sel,
    
    inout wire ir_snsrch0, ir_snsrch1, ir_snsrch2, ir_snsrch3,
            ir_snsrch4, ir_snsrch5, ir_snsrch6, ir_snsrch7,
    output wire[16:0] ttd0, ttd1, ttd2, ttd3, ttd4, ttd5, ttd6, ttd7,
    output wire ir_evenLED, ir_oddLED
    );

    

    wire ir_evenLED_en, ir_oddLED_en;
    




    
    
    pwm irevenLED (clk, ir_evenLED_en, 16'd16000, ir_evenLED);
    pwm iroddLED (clk, ir_oddLED_en, 16'd16000, ir_oddLED);
    
    IRread ch0 (clk, channel_sel[0], ir_snsrch0, ttd0);
    IRread ch1 (clk, channel_sel[1], ir_snsrch1, ttd1);
    IRread ch2 (clk, channel_sel[2], ir_snsrch2, ttd2);
    IRread ch3 (clk, channel_sel[3], ir_snsrch3, ttd3);
    IRread ch4 (clk, channel_sel[4], ir_snsrch4, ttd4);
    IRread ch5 (clk, channel_sel[5], ir_snsrch5, ttd5);
    IRread ch6 (clk, channel_sel[6], ir_snsrch6, ttd6);
    IRread ch7 (clk, channel_sel[7], ir_snsrch7, ttd7);
    


    assign ir_evenLED_en = channel_sel[0] | channel_sel[2] | channel_sel[4] | channel_sel[6];
    assign ir_oddLED_en = channel_sel[1] | channel_sel[3] | channel_sel[5] | channel_sel[7];
    
endmodule