data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v
1: b'%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:1: Cannot find include file: Opcode.vh\n`include "Opcode.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/Opcode.vh\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/Opcode.vh.v\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/Opcode.vh.sv\n             Opcode.vh\n             Opcode.vh.v\n             Opcode.vh.sv\n             obj_dir/Opcode.vh\n             obj_dir/Opcode.vh.v\n             obj_dir/Opcode.vh.sv\n%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:18: Define or directive not defined: \'`FNC_SH\'\n      `FNC_SH: begin\n      ^~~~~~~\n%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:18: syntax error, unexpected \':\', expecting endcase\n      `FNC_SH: begin\n             ^\n%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:51: Define or directive not defined: \'`FNC_SW\'\n      `FNC_SW: wea_out = 4\'b1111;\n      ^~~~~~~\n%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:51: syntax error, unexpected \':\', expecting endcase\n      `FNC_SW: wea_out = 4\'b1111;\n             ^\n%Error: data/full_repos/permissive/448204225/src/riscv_core/MemDataGen.v:52: Define or directive not defined: \'`FNC_SH\'\n      `FNC_SH: wea_out = 4\'b0011 << mask_index;\n      ^~~~~~~\n%Error: Cannot continue\n'
module MEM_DATA_GEN #(
  parameter DATA_WIDTH = 32
) (
  input [DATA_WIDTH - 1:0] data_in,
  input [2:0] inst_func_in,
  input [1:0] byte_addr_in,
  output [DATA_WIDTH - 1:0] data_out,
  output reg [DATA_WIDTH / 8 - 1:0] wea_out
);

  wire [5:0] bit_index;
  reg [2:0] mask_index;

  always @(*) begin
    case (inst_func_in)
      `FNC_SH: begin
        case (byte_addr_in)
          2'd0: mask_index = 0;
          2'd1: mask_index = 0;
          2'd2: mask_index = 2;
          2'd3: mask_index = 2;
          default: mask_index = 0;
        endcase
      end
      default: begin
        mask_index = byte_addr_in;
      end
    endcase
  end

  assign bit_index = mask_index << 3;















  always @(*) begin
    case (inst_func_in)
      `FNC_SW: wea_out = 4'b1111;
      `FNC_SH: wea_out = 4'b0011 << mask_index;
      default: wea_out = 4'b0001 << mask_index;
    endcase
  end

  assign data_out = data_in << bit_index;
                   
endmodule
module MEM_DATA_GEN #(
  parameter DATA_WIDTH = 32
) (
  input [DATA_WIDTH - 1:0] data_in,
  input [2:0] inst_func_in,
  input [1:0] byte_addr_in,
  output [DATA_WIDTH - 1:0] data_out,
  output reg [DATA_WIDTH / 8 - 1:0] wea_out
);


  wire [5:0] bit_index;
  reg [2:0] mask_index;

  always @(*) begin
    case (inst_func_in)
      `FNC_SH: begin
        case (byte_addr_in)
          2'd0: mask_index = 0;
          2'd1: mask_index = 0;
          2'd2: mask_index = 2;
          2'd3: mask_index = 2;
          default: mask_index = 0;
        endcase
      end
      default: begin
        mask_index = byte_addr_in;
      end
    endcase
  end

  assign bit_index = mask_index << 3;















  always @(*) begin
    case (inst_func_in)
      `FNC_SW: wea_out = 4'b1111;
      `FNC_SH: wea_out = 4'b0011 << mask_index;
      default: wea_out = 4'b0001 << mask_index;
    endcase
  end

  assign data_out = data_in << bit_index;
                   
endmodule