data/full_repos/permissive/528047272/rtl/instr_mem.v
1: b'%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:2: syntax error, unexpected parameter, expecting \'[\'\n  parameter DEPTH = 64,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:3: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter WIDTH = 32,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:4: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter WIDTH_ADR = 32,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter DEPTH_SIZE = $clog2(DEPTH)\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:7: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/528047272/rtl/instr_mem.v:14: syntax error, unexpected initial\n  initial $readmemh ("prog.txt", ram);\n  ^~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module instr_mem (
  parameter DEPTH = 64,
  parameter WIDTH = 32,
  parameter WIDTH_ADR = 32,
  
  parameter DEPTH_SIZE = $clog2(DEPTH)
) (
  input   [WIDTH_ADR-1 : 0] A,
  output  [WIDTH-1     : 0] Instruction
);


  reg [WIDTH-1 : 0] ram [0 : DEPTH-1];
  initial $readmemh ("prog.txt", ram);

  assign Instruction = ram [A[DEPTH_SIZE-1 : 0]];


endmodule
module instr_mem (
  parameter DEPTH = 64,
  parameter WIDTH = 32,
  parameter WIDTH_ADR = 32,
  
  parameter DEPTH_SIZE = $clog2(DEPTH)
) (
  input   [WIDTH_ADR-1 : 0] A,
  output  [WIDTH-1     : 0] Instruction
);



  reg [WIDTH-1 : 0] ram [0 : DEPTH-1];
  initial $readmemh ("prog.txt", ram);

  assign Instruction = ram [A[DEPTH_SIZE-1 : 0]];


endmodule