data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/tx_riffa_axi.v
1: b'%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/tx_riffa_axi.v:70: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'last_tkeep_value\' generates 5 bits.\n                                                                                                                                                        : ... In instance tx_riffa_axi\n  if (!last_tkeep_value) begin\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/tx_riffa_axi.v:264: Operator FUNCREF \'last_tkeep_conv\' expects 5 bits on the Function Argument, but Function Argument\'s SEL generates 4 bits.\n                                                                                                                                                         : ... In instance tx_riffa_axi\n  mt_last_tkeep = last_tkeep_conv(CHNL_RX_DATA[35:32]);\n                  ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/sume/tx_riffa_axi.v:266: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 2 bits.\n                                                                                                                                                         : ... In instance tx_riffa_axi\n  mt_num_words  = (CHNL_RX_LEN[1:0]) ? CHNL_RX_LEN[31:2] + 1\'b1 : CHNL_RX_LEN[31:2];  \n                                     ^\n%Error: Exiting due to 3 warning(s)\n'
module tx_riffa_axi #(
    parameter C_PCI_DATA_WIDTH  = 128,
    parameter C_PREAM_VALUE 	= 16'hCAFE 	
)(

    input wire                          CLK,
    input wire                          RST,

    input                          CHNL_RX,
    input [(C_PCI_DATA_WIDTH-1):0]   CHNL_RX_DATA,           
    input                           CHNL_RX_DATA_VALID,     
    input                           CHNL_RX_LAST,           
	input  [31:0]                   CHNL_RX_LEN,
    input  [30:0]                   CHNL_RX_OFF,                
	output                          CHNL_RX_DATA_REN,
    output                          CHNL_RX_ACK,


    output reg [(C_PCI_DATA_WIDTH-1):0]   tdata,
    output reg [((C_PCI_DATA_WIDTH/8)-1):0] tkeep,
    output reg [127:0]         			tuser,
    output reg                          tvalid,
    output reg                          tlast,
    input wire                          tready      

);





function [15:0] last_tkeep_conv; 
  input  [4:0] last_tkeep_value;
  begin : func_last_tstrb
  	integer i;
    last_tkeep_conv = 0;	 
	 if (!last_tkeep_value) begin
	 	last_tkeep_conv = {2{8'hFF}};
	 end	
	 else begin
		for (i=0; i < last_tkeep_value; i = i+1)
				last_tkeep_conv[i] = 1'b1;
	 end			
  end			
endfunction





localparam max_dws_trans_lp    = (C_PCI_DATA_WIDTH/32);


localparam fsm_width_lp    	    = 3;
localparam DELAY            	= 3'd0,
           WAIT_RIFFA_ACTIVE    = 3'd1,
           GENERATE_RIFFA_ACK   = 3'd2,
  	       METADATA_DETECTED    = 3'd3,			
           AXI_TRANSACTION      = 3'd4,
           TRANSACTION_ERROR    = 3'd5;





reg [fsm_width_lp-1:0] 	 fsm_state, fsm_state_next;

reg                    	     riffa_rack;
reg                    	     riffa_rren;
wire                         riffa_word_valid;

reg [29:0]                   mt_num_words;
reg [63:0]                   mt_tstamp;
reg [15:0]                   mt_len_B;
reg [7:0]                    mt_src_port;
reg [7:0]                    mt_des_port;
reg [15:0]                   mt_last_tkeep;
reg [15:0]		             mt_pream;
wire 			             pream_detected;

reg [29:0]      	         words2send;
reg [29:0]                   words_sent;

wire 			             words_sent_max;
reg 			             word_cntr_enbl;

reg [127:0]		 	         tuser_next;
reg [C_PCI_DATA_WIDTH/8-1:0] last_tkeep; 




assign CHNL_RX_ACK      = riffa_rack;
assign CHNL_RX_DATA_REN = riffa_rren;


always @ (*) begin : riffa_axi_comb_l
	fsm_state_next       = fsm_state;
	

	word_cntr_enbl       = 1'b0;


	riffa_rren           = 1'b0;
	riffa_rack           = 1'b0;


	tuser_next	         = tuser;
	tvalid		         = 1'b0;	
    tlast		         = 1'b0;	

	case (fsm_state)

        DELAY : begin
		    fsm_state_next  = WAIT_RIFFA_ACTIVE; 
	    end

        WAIT_RIFFA_ACTIVE : begin



		    if (CHNL_RX) begin			
			    fsm_state_next  = GENERATE_RIFFA_ACK;
		    end
	    end	 

	    GENERATE_RIFFA_ACK: begin
		    if (CHNL_RX) begin
			    riffa_rack      = 1'b1;
			    fsm_state_next  = METADATA_DETECTED;
			    


			    if (CHNL_RX_DATA_VALID) begin
                        riffa_rren      = 1'b1;
                        tuser_next      = {mt_tstamp, 32'h0, mt_des_port, mt_src_port, mt_len_B};
                                        
                        fsm_state_next  = (pream_detected) ? AXI_TRANSACTION : TRANSACTION_ERROR;
                end
		    end
	    end	
	
	    METADATA_DETECTED : begin
	    	if (CHNL_RX && CHNL_RX_DATA_VALID) begin





			    riffa_rren      = 1'b1;
	    		tuser_next	    = {mt_tstamp, 32'h0, mt_des_port, mt_src_port, mt_len_B};
						
	    		fsm_state_next  = (pream_detected) ? AXI_TRANSACTION : TRANSACTION_ERROR;
		    end		
	    end  

	    AXI_TRANSACTION : begin			


		    if (CHNL_RX && CHNL_RX_DATA_VALID && tready) begin


		        tvalid 	         = 1'b1; 			   	
        	    riffa_rren       = 1'b1;
			    word_cntr_enbl   = 1'b1;
				
			    if (words_sent_max) begin
				    tlast           = 1'b1;
				    fsm_state_next  = DELAY;
			    end			
		    end	
	     end
	
	     TRANSACTION_ERROR : begin




    		fsm_state_next  = TRANSACTION_ERROR;
	     end	
 		
	     default : begin
		    fsm_state_next  = DELAY;	
	     end	
	endcase
end


always @ (posedge CLK) begin : riffa_axi_seq_l
	if (RST) begin
		fsm_state       <= DELAY;
		tuser	        <= 'b0;			
	end
	else begin
	 	fsm_state       <= fsm_state_next;
		tuser	        <= tuser_next;		
	end
end


always @ (*) begin : axis_data_keep_l
	tdata  = 'b0;
	tkeep  = {2{8'hFF}};
	
	if (fsm_state == AXI_TRANSACTION) begin
		tdata  = CHNL_RX_DATA;
		tkeep  = (tlast) ? last_tkeep : {2{8'hFF}};	
	end
end


assign pream_detected = (mt_pream == C_PREAM_VALUE);
always @ (*) begin : metadata_comb_l
	mt_tstamp 		= 'b0;
	mt_len_B	 	= 'b0;
	mt_des_port		= 'b0;
	mt_src_port		= 'b0;
	mt_last_tkeep	= 'b0;
	mt_pream		= 'b0;
			
	mt_num_words    = 'b0;
		
	if ((fsm_state == GENERATE_RIFFA_ACK) || (fsm_state == METADATA_DETECTED)) begin
		mt_tstamp 	  = CHNL_RX_DATA[127:64];
	 	mt_pream	  = CHNL_RX_DATA[63:48];
		mt_len_B	  = CHNL_RX_DATA[47:32];
		mt_des_port	  = CHNL_RX_DATA[23:16];
		mt_src_port	  = CHNL_RX_DATA[7:0];  
 		

		mt_last_tkeep = last_tkeep_conv(CHNL_RX_DATA[35:32]);

		mt_num_words  = (CHNL_RX_LEN[1:0]) ? CHNL_RX_LEN[31:2] + 1'b1 : CHNL_RX_LEN[31:2];
	end
end


assign words_sent_max = ((words2send - 1'b1) == words_sent);
always @ (posedge CLK) begin : wcount_seq_l
	if (RST) begin
		words2send  <= 'b0;
		words_sent	<= 'b0;
		last_tkeep	<= 'b0;
	end
	else begin
	    words_sent	<= 'b0;   

	    if (fsm_state == AXI_TRANSACTION) begin
		  words_sent <= (word_cntr_enbl) ? (words_sent + 1'b1) : words_sent;
		end
		     

		if((fsm_state == GENERATE_RIFFA_ACK) || (fsm_state == METADATA_DETECTED)) begin
			last_tkeep  <= mt_last_tkeep;
			words2send  <= mt_num_words - 1'b1;
		end
	end		
end

endmodule
module tx_riffa_axi #(
    parameter C_PCI_DATA_WIDTH  = 128,
    parameter C_PREAM_VALUE 	= 16'hCAFE 	
)(

    input wire                          CLK,
    input wire                          RST,

    input                          CHNL_RX,
    input [(C_PCI_DATA_WIDTH-1):0]   CHNL_RX_DATA,           
    input                           CHNL_RX_DATA_VALID,     
    input                           CHNL_RX_LAST,           
	input  [31:0]                   CHNL_RX_LEN,
    input  [30:0]                   CHNL_RX_OFF,                
	output                          CHNL_RX_DATA_REN,
    output                          CHNL_RX_ACK,


    output reg [(C_PCI_DATA_WIDTH-1):0]   tdata,
    output reg [((C_PCI_DATA_WIDTH/8)-1):0] tkeep,
    output reg [127:0]         			tuser,
    output reg                          tvalid,
    output reg                          tlast,
    input wire                          tready      

);






function [15:0] last_tkeep_conv; 
  input  [4:0] last_tkeep_value;
  begin : func_last_tstrb
  	integer i;
    last_tkeep_conv = 0;	 
	 if (!last_tkeep_value) begin
	 	last_tkeep_conv = {2{8'hFF}};
	 end	
	 else begin
		for (i=0; i < last_tkeep_value; i = i+1)
				last_tkeep_conv[i] = 1'b1;
	 end			
  end			
endfunction





localparam max_dws_trans_lp    = (C_PCI_DATA_WIDTH/32);


localparam fsm_width_lp    	    = 3;
localparam DELAY            	= 3'd0,
           WAIT_RIFFA_ACTIVE    = 3'd1,
           GENERATE_RIFFA_ACK   = 3'd2,
  	       METADATA_DETECTED    = 3'd3,			
           AXI_TRANSACTION      = 3'd4,
           TRANSACTION_ERROR    = 3'd5;





reg [fsm_width_lp-1:0] 	 fsm_state, fsm_state_next;

reg                    	     riffa_rack;
reg                    	     riffa_rren;
wire                         riffa_word_valid;

reg [29:0]                   mt_num_words;
reg [63:0]                   mt_tstamp;
reg [15:0]                   mt_len_B;
reg [7:0]                    mt_src_port;
reg [7:0]                    mt_des_port;
reg [15:0]                   mt_last_tkeep;
reg [15:0]		             mt_pream;
wire 			             pream_detected;

reg [29:0]      	         words2send;
reg [29:0]                   words_sent;

wire 			             words_sent_max;
reg 			             word_cntr_enbl;

reg [127:0]		 	         tuser_next;
reg [C_PCI_DATA_WIDTH/8-1:0] last_tkeep; 




assign CHNL_RX_ACK      = riffa_rack;
assign CHNL_RX_DATA_REN = riffa_rren;


always @ (*) begin : riffa_axi_comb_l
	fsm_state_next       = fsm_state;
	

	word_cntr_enbl       = 1'b0;


	riffa_rren           = 1'b0;
	riffa_rack           = 1'b0;


	tuser_next	         = tuser;
	tvalid		         = 1'b0;	
    tlast		         = 1'b0;	

	case (fsm_state)

        DELAY : begin
		    fsm_state_next  = WAIT_RIFFA_ACTIVE; 
	    end

        WAIT_RIFFA_ACTIVE : begin



		    if (CHNL_RX) begin			
			    fsm_state_next  = GENERATE_RIFFA_ACK;
		    end
	    end	 

	    GENERATE_RIFFA_ACK: begin
		    if (CHNL_RX) begin
			    riffa_rack      = 1'b1;
			    fsm_state_next  = METADATA_DETECTED;
			    


			    if (CHNL_RX_DATA_VALID) begin
                        riffa_rren      = 1'b1;
                        tuser_next      = {mt_tstamp, 32'h0, mt_des_port, mt_src_port, mt_len_B};
                                        
                        fsm_state_next  = (pream_detected) ? AXI_TRANSACTION : TRANSACTION_ERROR;
                end
		    end
	    end	
	
	    METADATA_DETECTED : begin
	    	if (CHNL_RX && CHNL_RX_DATA_VALID) begin





			    riffa_rren      = 1'b1;
	    		tuser_next	    = {mt_tstamp, 32'h0, mt_des_port, mt_src_port, mt_len_B};
						
	    		fsm_state_next  = (pream_detected) ? AXI_TRANSACTION : TRANSACTION_ERROR;
		    end		
	    end  

	    AXI_TRANSACTION : begin			


		    if (CHNL_RX && CHNL_RX_DATA_VALID && tready) begin


		        tvalid 	         = 1'b1; 			   	
        	    riffa_rren       = 1'b1;
			    word_cntr_enbl   = 1'b1;
				
			    if (words_sent_max) begin
				    tlast           = 1'b1;
				    fsm_state_next  = DELAY;
			    end			
		    end	
	     end
	
	     TRANSACTION_ERROR : begin




    		fsm_state_next  = TRANSACTION_ERROR;
	     end	
 		
	     default : begin
		    fsm_state_next  = DELAY;	
	     end	
	endcase
end


always @ (posedge CLK) begin : riffa_axi_seq_l
	if (RST) begin
		fsm_state       <= DELAY;
		tuser	        <= 'b0;			
	end
	else begin
	 	fsm_state       <= fsm_state_next;
		tuser	        <= tuser_next;		
	end
end


always @ (*) begin : axis_data_keep_l
	tdata  = 'b0;
	tkeep  = {2{8'hFF}};
	
	if (fsm_state == AXI_TRANSACTION) begin
		tdata  = CHNL_RX_DATA;
		tkeep  = (tlast) ? last_tkeep : {2{8'hFF}};	
	end
end


assign pream_detected = (mt_pream == C_PREAM_VALUE);
always @ (*) begin : metadata_comb_l
	mt_tstamp 		= 'b0;
	mt_len_B	 	= 'b0;
	mt_des_port		= 'b0;
	mt_src_port		= 'b0;
	mt_last_tkeep	= 'b0;
	mt_pream		= 'b0;
			
	mt_num_words    = 'b0;
		
	if ((fsm_state == GENERATE_RIFFA_ACK) || (fsm_state == METADATA_DETECTED)) begin
		mt_tstamp 	  = CHNL_RX_DATA[127:64];
	 	mt_pream	  = CHNL_RX_DATA[63:48];
		mt_len_B	  = CHNL_RX_DATA[47:32];
		mt_des_port	  = CHNL_RX_DATA[23:16];
		mt_src_port	  = CHNL_RX_DATA[7:0];  
 		

		mt_last_tkeep = last_tkeep_conv(CHNL_RX_DATA[35:32]);

		mt_num_words  = (CHNL_RX_LEN[1:0]) ? CHNL_RX_LEN[31:2] + 1'b1 : CHNL_RX_LEN[31:2];
	end
end


assign words_sent_max = ((words2send - 1'b1) == words_sent);
always @ (posedge CLK) begin : wcount_seq_l
	if (RST) begin
		words2send  <= 'b0;
		words_sent	<= 'b0;
		last_tkeep	<= 'b0;
	end
	else begin
	    words_sent	<= 'b0;   

	    if (fsm_state == AXI_TRANSACTION) begin
		  words_sent <= (word_cntr_enbl) ? (words_sent + 1'b1) : words_sent;
		end
		     

		if((fsm_state == GENERATE_RIFFA_ACK) || (fsm_state == METADATA_DETECTED)) begin
			last_tkeep  <= mt_last_tkeep;
			words2send  <= mt_num_words - 1'b1;
		end
	end		
end

endmodule