data/full_repos/permissive/515851157/verilog/rtl/simple.v
1: b"%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:76: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/515851157/verilog/rtl/simple.v:77: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module simple #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,








    output [31:0] wbs_dat_o,







    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out




);
    wire clk;

    wire rd_en;
    wire wr_en;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;

    
    
    wire [7:0] rout_data; 
    wire [7:0] wdata;
    wire [5:0] addr;









    
    assign clk=wb_clk_i;



    
    assign rd_en=io_in[0];
    assign wr_en=io_in[3];
    
    assign wdata=io_in[15:8];
    assign addr=io_in[30:25];


   

    assign io_out[23:16]=rout_data;
    assign wbs_dat_o = rout_data;
   
















    mem_block #(
        .BITS(BITS)
    ) mem_block(
        .clk(clk),



        .addr(addr),
        .wdata(wdata),
        .rout_data(rout_data),
        .rd_en(rd_en),
        .wr_en(wr_en)
        




    );

endmodule
module simple #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,








    output [31:0] wbs_dat_o,







    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out




);

    wire clk;

    wire rd_en;
    wire wr_en;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;

    
    
    wire [7:0] rout_data; 
    wire [7:0] wdata;
    wire [5:0] addr;









    
    assign clk=wb_clk_i;



    
    assign rd_en=io_in[0];
    assign wr_en=io_in[3];
    
    assign wdata=io_in[15:8];
    assign addr=io_in[30:25];


   

    assign io_out[23:16]=rout_data;
    assign wbs_dat_o = rout_data;
   
















    mem_block #(
        .BITS(BITS)
    ) mem_block(
        .clk(clk),



        .addr(addr),
        .wdata(wdata),
        .rout_data(rout_data),
        .rd_en(rd_en),
        .wr_en(wr_en)
        




    );

endmodule