data/full_repos/permissive/427041400/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/427041400/verilog/rtl/user_proj_example.v:48: Cannot find file containing module: 'rvmyth'\n    rvmyth core (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427041400/verilog/rtl,data/full_repos/permissive/427041400/rvmyth\n             data/full_repos/permissive/427041400/verilog/rtl,data/full_repos/permissive/427041400/rvmyth.v\n             data/full_repos/permissive/427041400/verilog/rtl,data/full_repos/permissive/427041400/rvmyth.sv\n             rvmyth\n             rvmyth.v\n             rvmyth.sv\n             obj_dir/rvmyth\n             obj_dir/rvmyth.v\n             obj_dir/rvmyth.sv\n%Error: Exiting due to 1 error(s)\n"
module user_proj_example (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    output [9:0] OUT,
    input CLK,
    input reset
);

    rvmyth core (
      .OUT(OUT),
      .CLK(CLK),
      .reset(reset)
    );

endmodule
module user_proj_example (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    output [9:0] OUT,
    input CLK,
    input reset
);


    rvmyth core (
      .OUT(OUT),
      .CLK(CLK),
      .reset(reset)
    );

endmodule