data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/DatapathTestbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/DatapathTestbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/DatapathTestbench.v:10: Cannot find file containing module: \'CoreDatapath\'\n    CoreDatapath coreDatapath(clk);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/CoreDatapath\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/CoreDatapath.v\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/CoreDatapath.sv\n             CoreDatapath\n             CoreDatapath.v\n             CoreDatapath.sv\n             obj_dir/CoreDatapath\n             obj_dir/CoreDatapath.v\n             obj_dir/CoreDatapath.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DatapathTestbench ();

    reg clk;

    CoreDatapath coreDatapath(clk);

    initial clk = 0;
    always #5 clk = ~clk;

endmodule
module DatapathTestbench ();


    reg clk;

    CoreDatapath coreDatapath(clk);

    initial clk = 0;
    always #5 clk = ~clk;

endmodule