data/full_repos/permissive/46224382/src/Counter/counter.v
1: b'%Error: data/full_repos/permissive/46224382/src/Counter/counter.v:27: Unsupported: Verilog 1995 deassign\n            deassign out;\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter (out, clk, rst);

    parameter WIDTH = 8;
    

    output [WIDTH - 1 : 0] out;
    input clk;
    input rst;


    reg [WIDTH - 1 : 0] out;
    wire clk;
    wire rst;


    always @(posedge clk)
    begin

        out <= out + 1;
    end
    
    always @(rst)
    begin
        if (rst)
            assign out = 0;
        else
            deassign out;
    end

endmodule
module counter (out, clk, rst);


    parameter WIDTH = 8;
    

    output [WIDTH - 1 : 0] out;
    input clk;
    input rst;


    reg [WIDTH - 1 : 0] out;
    wire clk;
    wire rst;


    always @(posedge clk)
    begin

        out <= out + 1;
    end
    
    always @(rst)
    begin
        if (rst)
            assign out = 0;
        else
            deassign out;
    end

endmodule