data/full_repos/permissive/434840709/week10/2.v
data/verilator_xmls/259808d7-f65e-4202-8805-fe3615b628b0.xml
module top_module( 
              input a, 
              input b, 
              output out 
);

    and(out,a,b);


endmodule
module top_module( 
              input a, 
              input b, 
              output out 
);


    and(out,a,b);


endmodule