data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/always02.v
data/verilator_xmls/eee6f8a9-c03e-4012-8d84-981aa23b3350.xml
module uut_always02(clock, reset, c3, c2, c1, c0);

input clock, reset;
output c3, c2, c1, c0;
reg [3:0] count;

assign {c3, c2, c1, c0} = count;

always @(posedge clock) begin
	count <= count + 1;
	if (reset)
		count <= 0;
end

endmodule
module uut_always02(clock, reset, c3, c2, c1, c0);


input clock, reset;
output c3, c2, c1, c0;
reg [3:0] count;

assign {c3, c2, c1, c0} = count;

always @(posedge clock) begin
	count <= count + 1;
	if (reset)
		count <= 0;
end

endmodule