data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_1/sequence_detector_101.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_1,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_1/sequence_detector_101.v\n%Error: Exiting due to 5 error(s)\n'
module sequence_detector_101(
	input  clock,
	input  reset,
	input  serial_in,
	output detect_101
);

	wire a2b, b2c, c;

	d_ff DFFa(.clock(clock), .reset(reset), 
			  .data_in(serial_in), .q(a2b));
	d_ff DFFb(.clock(clock), .reset(reset), 
			  .data_in(a2b), .q(b2c));
	d_ff DFFc(.clock(clock), .reset(reset), 
			  .data_in(b2c), .q(c));

	assign detect_101 = a2b & ~b2c & c;

endmodule
module sequence_detector_101(
	input  clock,
	input  reset,
	input  serial_in,
	output detect_101
);


	wire a2b, b2c, c;

	d_ff DFFa(.clock(clock), .reset(reset), 
			  .data_in(serial_in), .q(a2b));
	d_ff DFFb(.clock(clock), .reset(reset), 
			  .data_in(a2b), .q(b2c));
	d_ff DFFc(.clock(clock), .reset(reset), 
			  .data_in(b2c), .q(c));

	assign detect_101 = a2b & ~b2c & c;

endmodule