data/full_repos/permissive/406635962/src/general/gnrl_pipe_stage.v
1: b"%Error: data/full_repos/permissive/406635962/src/general/gnrl_pipe_stage.v:33: Cannot find file containing module: 'gnrl_dfflr'\n    gnrl_dfflr #(1) vld_dfflr(vld_ena, vld_nxt, vld_r, clk, rst_n);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/general,data/full_repos/permissive/406635962/gnrl_dfflr\n             data/full_repos/permissive/406635962/src/general,data/full_repos/permissive/406635962/gnrl_dfflr.v\n             data/full_repos/permissive/406635962/src/general,data/full_repos/permissive/406635962/gnrl_dfflr.sv\n             gnrl_dfflr\n             gnrl_dfflr.v\n             gnrl_dfflr.sv\n             obj_dir/gnrl_dfflr\n             obj_dir/gnrl_dfflr.v\n             obj_dir/gnrl_dfflr.sv\n%Error: data/full_repos/permissive/406635962/src/general/gnrl_pipe_stage.v:34: Cannot find file containing module: 'gnrl_dfflr'\n    gnrl_dfflr #(DW) dat_dfflr(vld_set, i_dat, o_dat, clk, rst_n);\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module gnrl_pipe_stage #(

    parameter DP = 1,
    parameter DW = 32
)(
    input           i_vld, 
    output          i_rdy, 
    input  [DW-1:0] i_dat,
    output          o_vld, 
    input           o_rdy, 
    output [DW-1:0] o_dat,

    input           clk,
    input           rst_n
);
    wire vld_set;
    wire vld_clr;
    wire vld_ena;
    wire vld_r;
    wire vld_nxt;

    assign vld_set = i_vld & i_rdy;
    assign vld_clr = o_vld & o_rdy;

    assign vld_ena = vld_set | vld_clr;
    assign vld_nxt = vld_set | (~ vld_clr);

    gnrl_dfflr #(1) vld_dfflr(vld_ena, vld_nxt, vld_r, clk, rst_n);
    gnrl_dfflr #(DW) dat_dfflr(vld_set, i_dat, o_dat, clk, rst_n);

    assign o_vld = vld_r;
    assign i_rdy = (~vld_r) | vld_clr;
endmodule
module gnrl_pipe_stage #(

    parameter DP = 1,
    parameter DW = 32
)(
    input           i_vld, 
    output          i_rdy, 
    input  [DW-1:0] i_dat,
    output          o_vld, 
    input           o_rdy, 
    output [DW-1:0] o_dat,

    input           clk,
    input           rst_n
);

    wire vld_set;
    wire vld_clr;
    wire vld_ena;
    wire vld_r;
    wire vld_nxt;

    assign vld_set = i_vld & i_rdy;
    assign vld_clr = o_vld & o_rdy;

    assign vld_ena = vld_set | vld_clr;
    assign vld_nxt = vld_set | (~ vld_clr);

    gnrl_dfflr #(1) vld_dfflr(vld_ena, vld_nxt, vld_r, clk, rst_n);
    gnrl_dfflr #(DW) dat_dfflr(vld_set, i_dat, o_dat, clk, rst_n);

    assign o_vld = vld_r;
    assign i_rdy = (~vld_r) | vld_clr;
endmodule