data/full_repos/permissive/468437506/ep2/ep2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:15: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                 : ... In instance ep2\n   D3 = Key_in /100;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:16: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                 : ... In instance ep2\n   D2 = (Key_in%100)/10;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:17: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                 : ... In instance ep2\n D1 = Key_in%10;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:41: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'D1\' generates 4 bits.\n                                                                 : ... In instance ep2\n  0:begin smg_en<=4\'b1000;Q<=D1; h<=0; end\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:42: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'D2\' generates 4 bits.\n                                                                 : ... In instance ep2\n  1:begin smg_en<=4\'b0100;Q<=D2; h<=0; end\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/468437506/ep2/ep2.v:43: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'D3\' generates 4 bits.\n                                                                 : ... In instance ep2\n    2:begin smg_en<=4\'b0010;Q<=D3; h<=0; end\n                             ^~\n%Error: Exiting due to 6 warning(s)\n'
module ep2(Key_in,clk_50M,smg_en,Q,h,clk_1k);
input clk_50M;
input [7:0] Key_in;
output reg[3:0] smg_en=0;
output reg[2:0] Q=0;
output reg h=0;
output reg clk_1k=0;
reg [31:0] counter=0;
reg [1:0] cnt=0;
reg [3:0] D3 = 0,D2 = 0,D1 = 0;
parameter Nmax=32'd25_000;

always@(Key_in)
begin
   D3 = Key_in /100;
   D2 = (Key_in%100)/10;
	D1 = Key_in%10;
end
always@(posedge clk_50M)
begin
	if(counter==Nmax-1) 
	begin
	   counter<=0;
		clk_1k<=~clk_1k;
	end
	else 
	   counter<= counter + 1;
end

always@(posedge clk_1k)
begin
	if(cnt==3) 
	   cnt<=0;
	else 
	   cnt <= cnt + 1;
end

always@(posedge clk_1k)
begin 
		case(cnt)
		0:begin smg_en<=4'b1000;Q<=D1; h<=0; end
		1:begin smg_en<=4'b0100;Q<=D2; h<=0; end
	   2:begin smg_en<=4'b0010;Q<=D3; h<=0; end
		default:begin smg_en<=4'b0000; h<=0; end
		endcase
end 
endmodule
module ep2(Key_in,clk_50M,smg_en,Q,h,clk_1k);

input clk_50M;
input [7:0] Key_in;
output reg[3:0] smg_en=0;
output reg[2:0] Q=0;
output reg h=0;
output reg clk_1k=0;
reg [31:0] counter=0;
reg [1:0] cnt=0;
reg [3:0] D3 = 0,D2 = 0,D1 = 0;
parameter Nmax=32'd25_000;

always@(Key_in)
begin
   D3 = Key_in /100;
   D2 = (Key_in%100)/10;
	D1 = Key_in%10;
end
always@(posedge clk_50M)
begin
	if(counter==Nmax-1) 
	begin
	   counter<=0;
		clk_1k<=~clk_1k;
	end
	else 
	   counter<= counter + 1;
end

always@(posedge clk_1k)
begin
	if(cnt==3) 
	   cnt<=0;
	else 
	   cnt <= cnt + 1;
end

always@(posedge clk_1k)
begin 
		case(cnt)
		0:begin smg_en<=4'b1000;Q<=D1; h<=0; end
		1:begin smg_en<=4'b0100;Q<=D2; h<=0; end
	   2:begin smg_en<=4'b0010;Q<=D3; h<=0; end
		default:begin smg_en<=4'b0000; h<=0; end
		endcase
end 
endmodule