data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #105;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:74: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;      \n       ^\n%Error: data/full_repos/permissive/494117590/hdl_src/tb/tb_complex_mult.v:22: Cannot find file containing module: \'cplx_mult\'\ncplx_mult uut1  (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/cplx_mult\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/cplx_mult.v\n             data/full_repos/permissive/494117590/hdl_src/tb,data/full_repos/permissive/494117590/cplx_mult.sv\n             cplx_mult\n             cplx_mult.v\n             cplx_mult.sv\n             obj_dir/cplx_mult\n             obj_dir/cplx_mult.v\n             obj_dir/cplx_mult.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_SS_CM_18x18;


reg signed [17:0] AR;
reg signed [17:0] AI;
reg signed [17:0] BR;
reg signed [17:0] BI;

reg u1_valid_in;

reg clk;
reg rst_n;


wire [47:0] OR;
wire [47:0] OI;
wire u1_valid_out;


cplx_mult uut1  (
  .clk(clk) ,
  .rst_n(rst_n),
  .i_u1_valid_in(u1_valid_in),
  .o_u1_valid_out(u1_valid_out),
  .i_s18_AR(AR),  
  .i_s18_AI(AI), 
  .i_s18_BR(BR), 
  .i_s18_BI(BI),
  .o_s48_R(OR),
  .o_s48_I(OI)
);

initial begin

    AR = -9830  ;
    AI = 51118  ;
    BR = -51511 ;
    BI = 3696   ;
    u1_valid_in = 0;
    clk = 0;
    rst_n = 0;


    #105;
    #10 rst_n = 1;
    #50
    u1_valid_in = 1;
    #20
    u1_valid_in = 0;




    #300
    AR = -4981;
    AI = 19661;
    BR = -3277;
    BI = 4443 ;
    u1_valid_in = 1;
    #20
    AR = -9830  ;
    AI = 51118  ;
    BR = -51511 ;
    BI = 3696   ;
    #20
    u1_valid_in = 0;
    #20
    
    #100;

end
always #5 clk=~clk;      
endmodule
module Test_SS_CM_18x18;



reg signed [17:0] AR;
reg signed [17:0] AI;
reg signed [17:0] BR;
reg signed [17:0] BI;

reg u1_valid_in;

reg clk;
reg rst_n;


wire [47:0] OR;
wire [47:0] OI;
wire u1_valid_out;


cplx_mult uut1  (
  .clk(clk) ,
  .rst_n(rst_n),
  .i_u1_valid_in(u1_valid_in),
  .o_u1_valid_out(u1_valid_out),
  .i_s18_AR(AR),  
  .i_s18_AI(AI), 
  .i_s18_BR(BR), 
  .i_s18_BI(BI),
  .o_s48_R(OR),
  .o_s48_I(OI)
);

initial begin

    AR = -9830  ;
    AI = 51118  ;
    BR = -51511 ;
    BI = 3696   ;
    u1_valid_in = 0;
    clk = 0;
    rst_n = 0;


    #105;
    #10 rst_n = 1;
    #50
    u1_valid_in = 1;
    #20
    u1_valid_in = 0;




    #300
    AR = -4981;
    AI = 19661;
    BR = -3277;
    BI = 4443 ;
    u1_valid_in = 1;
    #20
    AR = -9830  ;
    AI = 51118  ;
    BR = -51511 ;
    BI = 3696   ;
    #20
    u1_valid_in = 0;
    #20
    
    #100;

end
always #5 clk=~clk;      
endmodule