data/full_repos/permissive/503973366/SIM/fifo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:57: Unsupported or unknown PLI call: $monitor\n        $monitor("RESET_N = %b, Write_EN = %b, Read_EN = %b, FULL = %b, EMPTY = %b, Write_DATA = %b, Read_DATA = %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:73: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:76: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:84: syntax error, unexpected \'@\'\n            @(posedge CLK);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:91: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:99: syntax error, unexpected \'@\'\n            @(posedge CLK);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/fifo_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/fifo_tb.v:105: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: Exiting due to 7 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO_TB #(

    parameter DATA_WIDTH = 32,
    parameter FIFO_DEPTH = 8
    )
    (


    );
    

    reg     CLK;    
    reg     RST_N;    
    reg     WE;   
    reg     RE;  
    
    wire    FULL;   
    wire    EMPTY;  
    
    reg    [DATA_WIDTH-1:0] WD;
    wire   [DATA_WIDTH-1:0] RD; 


    FIFO #(
        .DATA_WIDTH(DATA_WIDTH),
        .FIFO_DEPTH(FIFO_DEPTH)
    ) DUT (

        .clk    (CLK),    
        .rst_n  (RST_N),    
        .wren_i (WE),   
        .rden_i (RE),  
        
        .full_o (FULL),   
        .empty_o(EMPTY),  
        
        .wdata_i(WD),
        .rdata_o(RD) 
    );



    initial begin
        CLK = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) CLK = ~CLK;
        end
    end



    initial begin 
        $monitor("RESET_N = %b, Write_EN = %b, Read_EN = %b, FULL = %b, EMPTY = %b, Write_DATA = %b, Read_DATA = %b",
                    RST_N, WE, RE, FULL, EMPTY, WD, RD);
    end
    
    integer i;
    

    initial begin

        RST_N = 1'b1;
        WE = 1'b0;
        RE = 1'b0;
        WD = {(DATA_WIDTH){1'b0}};


        RST_N = 1'b0;
        @(posedge CLK);
        RST_N = 1'b1;
        
        @(posedge CLK);
        #(`DELTA)

        for (i=0; i<FIFO_DEPTH; i=i+1) begin
            $display("Write %d", i);
            #(`DELTA)
            WE = 1'b1;
            WD = i;
            @(posedge CLK);
        end
        

        WE = 1'b0;
        WD = {(DATA_WIDTH){1'b0}};
        
        @(posedge CLK);
        #(`DELTA)
        

        for (i=0; i<FIFO_DEPTH; i=i+1) begin
            $display("Read %d", i);
            #(`DELTA)
            RE = 1'b1;
            @(posedge CLK);
        end
        
        #(`DELTA)
        RE = 1'b0;
        $display("finished testbench");
        @(posedge CLK);
    end

endmodule
module FIFO_TB #(

    parameter DATA_WIDTH = 32,
    parameter FIFO_DEPTH = 8
    )
    (


    );

    

    reg     CLK;    
    reg     RST_N;    
    reg     WE;   
    reg     RE;  
    
    wire    FULL;   
    wire    EMPTY;  
    
    reg    [DATA_WIDTH-1:0] WD;
    wire   [DATA_WIDTH-1:0] RD; 


    FIFO #(
        .DATA_WIDTH(DATA_WIDTH),
        .FIFO_DEPTH(FIFO_DEPTH)
    ) DUT (

        .clk    (CLK),    
        .rst_n  (RST_N),    
        .wren_i (WE),   
        .rden_i (RE),  
        
        .full_o (FULL),   
        .empty_o(EMPTY),  
        
        .wdata_i(WD),
        .rdata_o(RD) 
    );



    initial begin
        CLK = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) CLK = ~CLK;
        end
    end



    initial begin 
        $monitor("RESET_N = %b, Write_EN = %b, Read_EN = %b, FULL = %b, EMPTY = %b, Write_DATA = %b, Read_DATA = %b",
                    RST_N, WE, RE, FULL, EMPTY, WD, RD);
    end
    
    integer i;
    

    initial begin

        RST_N = 1'b1;
        WE = 1'b0;
        RE = 1'b0;
        WD = {(DATA_WIDTH){1'b0}};


        RST_N = 1'b0;
        @(posedge CLK);
        RST_N = 1'b1;
        
        @(posedge CLK);
        #(`DELTA)

        for (i=0; i<FIFO_DEPTH; i=i+1) begin
            $display("Write %d", i);
            #(`DELTA)
            WE = 1'b1;
            WD = i;
            @(posedge CLK);
        end
        

        WE = 1'b0;
        WD = {(DATA_WIDTH){1'b0}};
        
        @(posedge CLK);
        #(`DELTA)
        

        for (i=0; i<FIFO_DEPTH; i=i+1) begin
            $display("Read %d", i);
            #(`DELTA)
            RE = 1'b1;
            @(posedge CLK);
        end
        
        #(`DELTA)
        RE = 1'b0;
        $display("finished testbench");
        @(posedge CLK);
    end

endmodule