data/full_repos/permissive/524522105/library/m8330_simple.v
1: b"%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:9: syntax error, unexpected return, expecting IDENTIFIER or do or final\n                      output reg       return = 1'b0,\n                                       ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:11: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n                      output reg       strobe = 1'b0,\n                      ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:12: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n                      output reg       inhibit = 1'b0,\n                      ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:13: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n                      output reg       write = 1'b0,\n                      ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:14: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n                      output reg [3:0] tp = 4'b0,\n                      ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:15: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n                      output reg [3:0] ts = 4'b0);\n                      ^~~~~~\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:15: syntax error, unexpected ')', expecting ',' or ';'\n                      output reg [3:0] ts = 4'b0);\n                                                ^\n%Error: data/full_repos/permissive/524522105/library/m8330_simple.v:22: syntax error, unexpected generate\n  generate\n  ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module m8330_simple ( input            clock,
                      input            power_on,
                      input            cycle_ctrl,
                      input            io_ctrl,
                      output reg       return = 1'b0,
                      output reg       source = 1'b0,
                      output reg       strobe = 1'b0,
                      output reg       inhibit = 1'b0,
                      output reg       write = 1'b0,
                      output reg [3:0] tp = 4'b0,
                      output reg [3:0] ts = 4'b0);

  wire [9:0] serial_in;
  wire [9:0] mode;
  wire [3:0] parallel_in [9:0];


  generate
    genvar i;

    for(i=0; i<10; i=i+1) 
    begin: chain
      sr74194 shift_reg( .clock(clock),
                         .mode(mode[i]),
                         .serial_in(serial_in[i]),
                         .parallel_in(parallel_in[i]) );

    end
  endgenerate


  assign mode[0] = ~power_on;
  assign parallel_in[0] = 4'b0011;
  assign serial_in[0] = chain[9].shift_reg.parallel_out[1];


  assign mode[1] = 1'b0;
  assign parallel_in[1] = 4'b0000;
  assign serial_in[1] = chain[0].shift_reg.parallel_out[3];


  assign mode[2] = 1'b0;
  assign parallel_in[2] = 4'b0000;
  assign serial_in[2] = chain[1].shift_reg.parallel_out[3];


  assign mode[3] = 1'b0;
  assign parallel_in[3] = 4'b0000;
  assign serial_in[3] = chain[2].shift_reg.parallel_out[1];


  assign mode[4] = 1'b0;
  assign parallel_in[4] = 4'b0000;
  assign serial_in[4] = chain[3].shift_reg.parallel_out[3];


  assign mode[5] = 1'b0;
  assign parallel_in[5] = 4'b0000;
  assign serial_in[5] = chain[4].shift_reg.parallel_out[3];


  assign mode[6] = 1'b0;
  assign parallel_in[6] = 4'b0000;
  assign serial_in[6] = chain[5].shift_reg.parallel_out[3];


  assign mode[7] = 1'b0;
  assign parallel_in[7] = 4'b0000;
  assign serial_in[7] = chain[6].shift_reg.parallel_out[3];


  assign mode[8] = 1'b0;
  assign parallel_in[8] = 4'b0000;
  assign serial_in[8] = chain[5].shift_reg.parallel_out[3];


  assign mode[9] = 1'b0;
  assign parallel_in[9] = 4'b0000;
  assign serial_in[9] = chain[8].shift_reg.parallel_out[3];

  always @ (posedge clock) begin


    if (chain[0].shift_reg.parallel_out[3]) begin
      return <= 1'b1;
      source <= 1'b1;
    end


    tp[0] <= chain[1].shift_reg.parallel_out[2];
    if (chain[1].shift_reg.parallel_out[2]) begin
      strobe <= 1'b1;
    end
    if (chain[1].shift_reg.parallel_out[3]) begin
      ts[0] <= 1'b1;
      ts[1] <= 1'b0;
    end


    if (chain[2].shift_reg.parallel_out[1]) begin
      strobe <= 1'b0;
    end
    if (chain[2].shift_reg.parallel_out[2]) begin
      source <= 1'b0;
    end
    if (chain[2].shift_reg.parallel_out[3]) begin
      return <= 1'b0;
    end

    

    tp[1] <= chain[4].shift_reg.parallel_out[1];
    if (chain[4].shift_reg.parallel_out[2]) begin
      ts[1] <= 1'b1;
      ts[2] <= 1'b0;
    end


    if (chain[5].shift_reg.parallel_out[0]) begin
      write <= 1'b1;
    end
    if (chain[5].shift_reg.parallel_out[2]) begin
      return <= 1'b1;
      source <= 1'b1;
      inhibit <= 1'b1;
    end


    tp[2] <= chain[6].shift_reg.parallel_out[0];


    if (chain[7].shift_reg.parallel_out[1]) begin
      source <= 1'b0;
      inhibit <= 1'b0;
    end
    if (chain[7].shift_reg.parallel_out[3]) begin
      return <= 1'b0;
      write <= 1'b0;
    end


    if (chain[8].shift_reg.parallel_out[1]) begin
      ts[2] <= 1'b1;
      ts[3] <= 1'b0;
    end


    tp[3] <= chain[9].shift_reg.parallel_out[2];
    if (chain[9].shift_reg.parallel_out[3]) begin
      ts[3] <= 1'b1;
      ts[0] <= 1'b0;
    end
  end

endmodule
module m8330_simple ( input            clock,
                      input            power_on,
                      input            cycle_ctrl,
                      input            io_ctrl,
                      output reg       return = 1'b0,
                      output reg       source = 1'b0,
                      output reg       strobe = 1'b0,
                      output reg       inhibit = 1'b0,
                      output reg       write = 1'b0,
                      output reg [3:0] tp = 4'b0,
                      output reg [3:0] ts = 4'b0);


  wire [9:0] serial_in;
  wire [9:0] mode;
  wire [3:0] parallel_in [9:0];


  generate
    genvar i;

    for(i=0; i<10; i=i+1) 
    begin: chain
      sr74194 shift_reg( .clock(clock),
                         .mode(mode[i]),
                         .serial_in(serial_in[i]),
                         .parallel_in(parallel_in[i]) );

    end
  endgenerate


  assign mode[0] = ~power_on;
  assign parallel_in[0] = 4'b0011;
  assign serial_in[0] = chain[9].shift_reg.parallel_out[1];


  assign mode[1] = 1'b0;
  assign parallel_in[1] = 4'b0000;
  assign serial_in[1] = chain[0].shift_reg.parallel_out[3];


  assign mode[2] = 1'b0;
  assign parallel_in[2] = 4'b0000;
  assign serial_in[2] = chain[1].shift_reg.parallel_out[3];


  assign mode[3] = 1'b0;
  assign parallel_in[3] = 4'b0000;
  assign serial_in[3] = chain[2].shift_reg.parallel_out[1];


  assign mode[4] = 1'b0;
  assign parallel_in[4] = 4'b0000;
  assign serial_in[4] = chain[3].shift_reg.parallel_out[3];


  assign mode[5] = 1'b0;
  assign parallel_in[5] = 4'b0000;
  assign serial_in[5] = chain[4].shift_reg.parallel_out[3];


  assign mode[6] = 1'b0;
  assign parallel_in[6] = 4'b0000;
  assign serial_in[6] = chain[5].shift_reg.parallel_out[3];


  assign mode[7] = 1'b0;
  assign parallel_in[7] = 4'b0000;
  assign serial_in[7] = chain[6].shift_reg.parallel_out[3];


  assign mode[8] = 1'b0;
  assign parallel_in[8] = 4'b0000;
  assign serial_in[8] = chain[5].shift_reg.parallel_out[3];


  assign mode[9] = 1'b0;
  assign parallel_in[9] = 4'b0000;
  assign serial_in[9] = chain[8].shift_reg.parallel_out[3];

  always @ (posedge clock) begin


    if (chain[0].shift_reg.parallel_out[3]) begin
      return <= 1'b1;
      source <= 1'b1;
    end


    tp[0] <= chain[1].shift_reg.parallel_out[2];
    if (chain[1].shift_reg.parallel_out[2]) begin
      strobe <= 1'b1;
    end
    if (chain[1].shift_reg.parallel_out[3]) begin
      ts[0] <= 1'b1;
      ts[1] <= 1'b0;
    end


    if (chain[2].shift_reg.parallel_out[1]) begin
      strobe <= 1'b0;
    end
    if (chain[2].shift_reg.parallel_out[2]) begin
      source <= 1'b0;
    end
    if (chain[2].shift_reg.parallel_out[3]) begin
      return <= 1'b0;
    end

    

    tp[1] <= chain[4].shift_reg.parallel_out[1];
    if (chain[4].shift_reg.parallel_out[2]) begin
      ts[1] <= 1'b1;
      ts[2] <= 1'b0;
    end


    if (chain[5].shift_reg.parallel_out[0]) begin
      write <= 1'b1;
    end
    if (chain[5].shift_reg.parallel_out[2]) begin
      return <= 1'b1;
      source <= 1'b1;
      inhibit <= 1'b1;
    end


    tp[2] <= chain[6].shift_reg.parallel_out[0];


    if (chain[7].shift_reg.parallel_out[1]) begin
      source <= 1'b0;
      inhibit <= 1'b0;
    end
    if (chain[7].shift_reg.parallel_out[3]) begin
      return <= 1'b0;
      write <= 1'b0;
    end


    if (chain[8].shift_reg.parallel_out[1]) begin
      ts[2] <= 1'b1;
      ts[3] <= 1'b0;
    end


    tp[3] <= chain[9].shift_reg.parallel_out[2];
    if (chain[9].shift_reg.parallel_out[3]) begin
      ts[3] <= 1'b1;
      ts[0] <= 1'b0;
    end
  end

endmodule