data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/testbench_lfsr.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/testbench_lfsr.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #(T/2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/testbench_lfsr.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #(T/2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/testbench_lfsr.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #200 rst_n = 1\'b0;\n   ^\n%Error: data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/testbench_lfsr.v:9: Cannot find file containing module: \'lfsr\'\n    lfsr UUT(.clk(clk),.rst_n(rst_n),.Q_out(Q_out),.max_tick_reg(max_tick_reg));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new,data/full_repos/permissive/461569093/lfsr\n             data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new,data/full_repos/permissive/461569093/lfsr.v\n             data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new,data/full_repos/permissive/461569093/lfsr.sv\n             lfsr\n             lfsr.v\n             lfsr.sv\n             obj_dir/lfsr\n             obj_dir/lfsr.v\n             obj_dir/lfsr.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_lfsr(

    );
    reg clk,rst_n;
    wire max_tick_reg;
    wire [15:0] Q_out;
    
    lfsr UUT(.clk(clk),.rst_n(rst_n),.Q_out(Q_out),.max_tick_reg(max_tick_reg));
    localparam T = 20;

	always
		begin
			clk = 1'b1;
			#(T/2);
			clk = 1'b0;
			#(T/2);
		end
	
    

	initial 
		begin
			 rst_n = 1'b1; 	


			#200 rst_n = 1'b0;

		end 

endmodule
module testbench_lfsr(

    );

    reg clk,rst_n;
    wire max_tick_reg;
    wire [15:0] Q_out;
    
    lfsr UUT(.clk(clk),.rst_n(rst_n),.Q_out(Q_out),.max_tick_reg(max_tick_reg));
    localparam T = 20;

	always
		begin
			clk = 1'b1;
			#(T/2);
			clk = 1'b0;
			#(T/2);
		end
	
    

	initial 
		begin
			 rst_n = 1'b1; 	


			#200 rst_n = 1'b0;

		end 

endmodule