data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v
1: b'%Error: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:2: Cannot find include file: q.v\n`include "q.v" \n         ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/528677531/LAB-5/Q4,data/full_repos/permissive/528677531/q.v\n             data/full_repos/permissive/528677531/LAB-5/Q4,data/full_repos/permissive/528677531/q.v.v\n             data/full_repos/permissive/528677531/LAB-5/Q4,data/full_repos/permissive/528677531/q.v.sv\n             q.v\n             q.v.v\n             q.v.sv\n             obj_dir/q.v\n             obj_dir/q.v.v\n             obj_dir/q.v.sv\n%Error: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("q_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,q_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\na=4\'b1010; b=4\'b1001; #20;\n                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\na=4\'b1010; b=4\'b1010; #20;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-5/Q4/q_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\na=4\'b1001; b=4\'b1010; #20;\n                      ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module q_tb();
reg [3:0]a,b;
wire aeqb,agtb,altb;
comp4 comp4(a,b,aeqb,agtb,altb);
initial
begin
$dumpfile("q_tb.vcd");
$dumpvars(0,q_tb);
a=4'b1010; b=4'b1001; #20;
a=4'b1010; b=4'b1010; #20;
a=4'b1001; b=4'b1010; #20;
$display("Test Complete");
end
endmodule
module q_tb();

reg [3:0]a,b;
wire aeqb,agtb,altb;
comp4 comp4(a,b,aeqb,agtb,altb);
initial
begin
$dumpfile("q_tb.vcd");
$dumpvars(0,q_tb);
a=4'b1010; b=4'b1001; #20;
a=4'b1010; b=4'b1010; #20;
a=4'b1001; b=4'b1010; #20;
$display("Test Complete");
end
endmodule