data/full_repos/permissive/446997925/hw4/register.v
data/verilator_xmls/53a2ae84-6751-46b0-a540-e229e828428a.xml
module register_32(in, rst, out, clock);
input rst, clock;
output reg [31:0] out;
input [31:0] in;

always @ (posedge clock)
	if (rst)
		out <= 32'b0;
	else
		out <= in;

endmodule
module register_32(in, rst, out, clock);

input rst, clock;
output reg [31:0] out;
input [31:0] in;

always @ (posedge clock)
	if (rst)
		out <= 32'b0;
	else
		out <= in;

endmodule