data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_register_file_ff.v
1: b'%Warning-WIDTH: data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_register_file_ff.v:52: Operator FUNCREF \'sv2v_cast_5\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n                                                                                                 : ... In instance ibex_register_file_ff\n    we_a_dec[i] = (waddr_a_i == sv2v_cast_5(i) ? we_a_i : 1\'b0);\n                                ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_register_file_ff.v:61: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                 : ... In instance ibex_register_file_ff\n     rf_reg_q[i* DataWidth +: DataWidth] <= 1\'sb0;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_register_file_ff.v:79: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                 : ... In instance ibex_register_file_ff\n   assign rf_reg[0 +:DataWidth] = 1\'sb0;\n                                ^\n%Error: Exiting due to 3 warning(s)\n'
function automatic [4:0] sv2v_cast_5;
		input reg [4:0] inp;
		sv2v_cast_5 = inp;
	endfunction
function automatic [4:0] sv2v_cast_5;

		input reg [4:0] inp;
		sv2v_cast_5 = inp;
	endfunction