data/full_repos/permissive/419538859/lab8/lab8.v
data/verilator_xmls/72eaa1fa-e1a0-4b8a-9606-e8f8e9cdaa6a.xml
module 	vaild (clk,rst,press,press_valid);
input press,clk,rst;
output press_valid;
reg[6:0] gg;
assign press_valid=(press&~(gg[5]));
always@(posedge clk or posedge rst)
begin
if(rst)
	gg<=7'b0;
else
	gg<={gg[5:0],press};
end
endmodule
module 	vaild (clk,rst,press,press_valid);

input press,clk,rst;
output press_valid;
reg[6:0] gg;
assign press_valid=(press&~(gg[5]));
always@(posedge clk or posedge rst)
begin
if(rst)
	gg<=7'b0;
else
	gg<={gg[5:0],press};
end
endmodule