data/full_repos/permissive/465552624/verilogfiles/sensoham_2to1mux.v
data/verilator_xmls/34ff62ef-ed94-4b2e-a4c3-ba9e15db4e6d.xml
module sensoham_2to1mux (input i0 , input i1 , input sel , output reg y);
always @ (*)
begin
	if(sel)
		y <= i1;
	else 
		y <= i0;
end
endmodule
module sensoham_2to1mux (input i0 , input i1 , input sel , output reg y);

always @ (*)
begin
	if(sel)
		y <= i1;
	else 
		y <= i0;
end
endmodule