data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montexp.v
data/verilator_xmls/1611d6f7-32cb-4869-8b36-dfed1b268759.xml
module montexp
    (
     clk,
     rst,
     
     a,
     b,
     expk,
     exp2k,
     r,
     
     start,
     vld,


     mpa1,
     mpb1,
     mpr1,
     
     mpstart1,
     mpvld1,


     mpa2,
     mpb2,
     mpr2,
     
     mpstart2,
     mpvld2
     );



parameter WID = 256;
parameter CNTWID = 8;
parameter CNTVL = 255;
parameter ZERO = 0;

localparam SWID   = 2;
localparam IDLE   = 2'd0;
localparam INIT  = 2'd1;

localparam LOOP   = 2'd2;

localparam FINAL = 2'd3;



input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;

input [WID-1:0] expk;
input [WID-1:0] exp2k;

output [WID-1:0] r;

input            start;
output           vld;


output [WID-1:0] mpa1;
output [WID-1:0] mpb1;
input [WID-1:0]  mpr1;

output          mpstart1;
input           mpvld1;


output [WID-1:0] mpa2;
output [WID-1:0] mpb2;
input [WID-1:0]  mpr2;

output          mpstart2;
input           mpvld2;







reg [CNTWID-1:0] cnt;

reg [SWID-1:0]  state;

wire            isidle;

assign          isidle = state == IDLE;

wire            isinit;

assign          isinit = state == INIT;

wire            isinitvld;

assign          isinitvld = isinit & mpvld2;

wire            isloop;

assign          isloop = state == LOOP;

wire            isloopvld1;

assign          isloopvld1 = isloop & mpvld1;

wire            isloopvld2;

assign          isloopvld2 = isloop & mpvld2;

wire            isloopvld;

assign          isloopvld = isloopvld1 & isloopvld2;

wire            loopmax;

assign          loopmax = cnt == 8'd255;

wire            isloopdone;

assign          isloopdone = isloop & loopmax &isloopvld;

wire            isnotloopdone;

assign          isnotloopdone = isloop & !loopmax &isloopvld;

wire            isfinal;

assign          isfinal = state == FINAL;

wire            isfinalvld;

assign          isfinalvld = isfinal & mpvld1;

reg             mpstart1;
reg             mpstart2;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        mpstart1 <= 1'b0;
        mpstart2 <= 1'b0;
        end
    else
        begin
        if(isidle & start)
            begin
            state <= INIT;
            mpstart2 <= 1'b1;
            end
        else if(isinitvld)
            begin
            state <= LOOP;
            mpstart1 <= 1'b1;
            mpstart2 <= 1'b1;
            end
        else if(isnotloopdone)
            begin
            state <= LOOP;
            mpstart1 <= 1'b1;
            mpstart2 <= 1'b1;
            end
        else if(isloopdone)
            begin
            state <= FINAL;
            mpstart1 <= 1'b1;
            end
        else if(isfinalvld)
            begin
            state <= IDLE;
            end
        else
            begin
            state <= state;
            mpstart1 <= 1'b0;
            mpstart2 <= 1'b0;
            end
        end
    end



always@(posedge clk)
    begin
    if(rst)
        begin
        cnt <= ZERO;
        end
    else
        begin
        if(isloopvld)
            begin
            cnt <= cnt + 1;
            end
        else if(isinit)
            begin
            cnt <= ZERO;
            end
        else
            begin
            cnt <= cnt;
            end
        end
    end


reg [WID-1:0] evalue;

always@(posedge clk)
    begin
    if(rst)
        begin
        evalue <= ZERO;
        end
    else
        begin
        if(isinit)
            begin
            evalue <= expk;
            end
        else if(isloopvld1)
            begin
            evalue <= b[cnt]? mpr1 : evalue;
            end
        else
            begin
            evalue <= evalue;
            end
        end
    end


reg [WID-1:0] tyvalue;

always@(posedge clk)
    begin
    if(rst)
        begin
        tyvalue <= ZERO;
        end
    else
        begin
        if(isinitvld)
            begin
            tyvalue <= mpr2;
            end
        else if(isloopvld2)
            begin
            tyvalue <= mpr2;
            end
        else
            begin
            tyvalue <= tyvalue;
            end
        end
    end


assign mpa1 = evalue;
assign mpb1 = isfinal? 256'd1 : tyvalue;


assign mpa2 = isinit? a : tyvalue;
assign mpb2 = isinit? exp2k : tyvalue;


reg    vld;
reg [WID-1:0] r;

always@(posedge clk)
    begin
    if(rst)
        begin
        vld <= 1'b0;
        r <= ZERO;
        end
    else
        begin
        if(isfinalvld)
            begin
            r <= mpr1;
            vld <= 1'b1;
            end
        else
            begin
            r <= ZERO;
            vld <= 1'b0;
            end
        end
    end

endmodule
module montexp
    (
     clk,
     rst,
     
     a,
     b,
     expk,
     exp2k,
     r,
     
     start,
     vld,


     mpa1,
     mpb1,
     mpr1,
     
     mpstart1,
     mpvld1,


     mpa2,
     mpb2,
     mpr2,
     
     mpstart2,
     mpvld2
     );




parameter WID = 256;
parameter CNTWID = 8;
parameter CNTVL = 255;
parameter ZERO = 0;

localparam SWID   = 2;
localparam IDLE   = 2'd0;
localparam INIT  = 2'd1;

localparam LOOP   = 2'd2;

localparam FINAL = 2'd3;



input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;

input [WID-1:0] expk;
input [WID-1:0] exp2k;

output [WID-1:0] r;

input            start;
output           vld;


output [WID-1:0] mpa1;
output [WID-1:0] mpb1;
input [WID-1:0]  mpr1;

output          mpstart1;
input           mpvld1;


output [WID-1:0] mpa2;
output [WID-1:0] mpb2;
input [WID-1:0]  mpr2;

output          mpstart2;
input           mpvld2;







reg [CNTWID-1:0] cnt;

reg [SWID-1:0]  state;

wire            isidle;

assign          isidle = state == IDLE;

wire            isinit;

assign          isinit = state == INIT;

wire            isinitvld;

assign          isinitvld = isinit & mpvld2;

wire            isloop;

assign          isloop = state == LOOP;

wire            isloopvld1;

assign          isloopvld1 = isloop & mpvld1;

wire            isloopvld2;

assign          isloopvld2 = isloop & mpvld2;

wire            isloopvld;

assign          isloopvld = isloopvld1 & isloopvld2;

wire            loopmax;

assign          loopmax = cnt == 8'd255;

wire            isloopdone;

assign          isloopdone = isloop & loopmax &isloopvld;

wire            isnotloopdone;

assign          isnotloopdone = isloop & !loopmax &isloopvld;

wire            isfinal;

assign          isfinal = state == FINAL;

wire            isfinalvld;

assign          isfinalvld = isfinal & mpvld1;

reg             mpstart1;
reg             mpstart2;

always@(posedge clk)
    begin
    if(rst)
        begin
        state <= IDLE;
        mpstart1 <= 1'b0;
        mpstart2 <= 1'b0;
        end
    else
        begin
        if(isidle & start)
            begin
            state <= INIT;
            mpstart2 <= 1'b1;
            end
        else if(isinitvld)
            begin
            state <= LOOP;
            mpstart1 <= 1'b1;
            mpstart2 <= 1'b1;
            end
        else if(isnotloopdone)
            begin
            state <= LOOP;
            mpstart1 <= 1'b1;
            mpstart2 <= 1'b1;
            end
        else if(isloopdone)
            begin
            state <= FINAL;
            mpstart1 <= 1'b1;
            end
        else if(isfinalvld)
            begin
            state <= IDLE;
            end
        else
            begin
            state <= state;
            mpstart1 <= 1'b0;
            mpstart2 <= 1'b0;
            end
        end
    end



always@(posedge clk)
    begin
    if(rst)
        begin
        cnt <= ZERO;
        end
    else
        begin
        if(isloopvld)
            begin
            cnt <= cnt + 1;
            end
        else if(isinit)
            begin
            cnt <= ZERO;
            end
        else
            begin
            cnt <= cnt;
            end
        end
    end


reg [WID-1:0] evalue;

always@(posedge clk)
    begin
    if(rst)
        begin
        evalue <= ZERO;
        end
    else
        begin
        if(isinit)
            begin
            evalue <= expk;
            end
        else if(isloopvld1)
            begin
            evalue <= b[cnt]? mpr1 : evalue;
            end
        else
            begin
            evalue <= evalue;
            end
        end
    end


reg [WID-1:0] tyvalue;

always@(posedge clk)
    begin
    if(rst)
        begin
        tyvalue <= ZERO;
        end
    else
        begin
        if(isinitvld)
            begin
            tyvalue <= mpr2;
            end
        else if(isloopvld2)
            begin
            tyvalue <= mpr2;
            end
        else
            begin
            tyvalue <= tyvalue;
            end
        end
    end


assign mpa1 = evalue;
assign mpb1 = isfinal? 256'd1 : tyvalue;


assign mpa2 = isinit? a : tyvalue;
assign mpb2 = isinit? exp2k : tyvalue;


reg    vld;
reg [WID-1:0] r;

always@(posedge clk)
    begin
    if(rst)
        begin
        vld <= 1'b0;
        r <= ZERO;
        end
    else
        begin
        if(isfinalvld)
            begin
            r <= mpr1;
            vld <= 1'b1;
            end
        else
            begin
            r <= ZERO;
            vld <= 1'b0;
            end
        end
    end

endmodule