data/full_repos/permissive/425816165/rtl/kbdhandler.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/kbdhandler.v:193: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s SEL generates 5 bits.\n                                                                         : ... In instance kbdhandler.scan2ascii\n assign ascii = ctrl ? base[4:0] : base[6:0];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425816165/rtl/kbdhandler.v:15: Cannot find file containing module: \'edgedet\'\n edgedet data_edge(clk, reset, newdata, scanpulse);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet.v\n             data/full_repos/permissive/425816165/rtl,data/full_repos/permissive/425816165/edgedet.sv\n             edgedet\n             edgedet.v\n             edgedet.sv\n             obj_dir/edgedet\n             obj_dir/edgedet.v\n             obj_dir/edgedet.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module kbdhandler(
	input wire clk,
	input wire reset,

	input wire newdata,
	input wire [7:0] scancode,

	output reg sendchar,
	output wire [6:0] ascii
);

	wire scanpulse;
	edgedet data_edge(clk, reset, newdata, scanpulse);

	reg ext = 0;
	reg down = 1;
	reg shift = 0;
	reg ctrl = 0;
	reg alt = 0;

	always @(posedge clk or posedge reset) begin
		if(reset) begin
			sendchar <= 0;

			ext = 0;
			down = 1;
			shift = 0;
			ctrl = 0;
			alt = 0;
		end else begin
			if(scanpulse) begin
				if(scancode == 'hF0) begin
					down <= 0;
				end else if(scancode == 'hE0) begin
					ext <= 1;
				end else begin
					down <= 1;
					ext <= 0;
					if(scancode == 'h12 || scancode == 'h59)
						shift <= down;
					else if(scancode == 'h14 || scancode == 'h58)
						ctrl <= down;
					else if(scancode == 'h11)
						alt <= down;

					if(~invalid)
						sendchar <= down;
				end
			end
			if(sendchar)
				sendchar <= 0;
		end
	end

	wire invalid;
	scan2ascii scan2ascii(.scan(scancode),
		.shift(shift), .ctrl(ctrl), .ascii(ascii), .invalid(invalid));
endmodule
module kbdhandler(
	input wire clk,
	input wire reset,

	input wire newdata,
	input wire [7:0] scancode,

	output reg sendchar,
	output wire [6:0] ascii
);


	wire scanpulse;
	edgedet data_edge(clk, reset, newdata, scanpulse);

	reg ext = 0;
	reg down = 1;
	reg shift = 0;
	reg ctrl = 0;
	reg alt = 0;

	always @(posedge clk or posedge reset) begin
		if(reset) begin
			sendchar <= 0;

			ext = 0;
			down = 1;
			shift = 0;
			ctrl = 0;
			alt = 0;
		end else begin
			if(scanpulse) begin
				if(scancode == 'hF0) begin
					down <= 0;
				end else if(scancode == 'hE0) begin
					ext <= 1;
				end else begin
					down <= 1;
					ext <= 0;
					if(scancode == 'h12 || scancode == 'h59)
						shift <= down;
					else if(scancode == 'h14 || scancode == 'h58)
						ctrl <= down;
					else if(scancode == 'h11)
						alt <= down;

					if(~invalid)
						sendchar <= down;
				end
			end
			if(sendchar)
				sendchar <= 0;
		end
	end

	wire invalid;
	scan2ascii scan2ascii(.scan(scancode),
		.shift(shift), .ctrl(ctrl), .ascii(ascii), .invalid(invalid));
endmodule