data/full_repos/permissive/519420376/RTL/Vga_controller.v
1: b"%Error: data/full_repos/permissive/519420376/RTL/Vga_controller.v:54: Cannot find file containing module: 'Pix_clk_gen'\n Pix_clk_gen CLK(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Pix_clk_gen\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Pix_clk_gen.v\n             data/full_repos/permissive/519420376/RTL,data/full_repos/permissive/519420376/Pix_clk_gen.sv\n             Pix_clk_gen\n             Pix_clk_gen.v\n             Pix_clk_gen.sv\n             obj_dir/Pix_clk_gen\n             obj_dir/Pix_clk_gen.v\n             obj_dir/Pix_clk_gen.sv\n%Error: Exiting due to 1 error(s)\n"
module Vga_controller
(input i_clk , 
 input i_rst_n , 
 output H_sync , 
 output V_sync , 
 output Vid_on , 
 output [`WIDTH-1:0] pix_x ,
 output [`WIDTH-1:0] pix_y);
 


   


  parameter H_Area = 800 ;
  parameter H_Disp = 640 ;

  parameter H_retrace = 96 ;
  parameter H_Front_porch = 16 ;
  parameter H_Back_porch = 48 ;
 

  parameter V_Area = 525;
  parameter V_Disp = 480 ;

  parameter V_retrace = 2 ;
  parameter V_Front_porch = 10 ;
  parameter V_Back_porch = 33 ;
 
 wire pix_clk_25MHZ ;
 
	Pix_clk_gen CLK(
    .i_clk(i_clk),
    .i_rst_n(i_rst_n) , 
    .out_clk(pix_clk_25MHZ)
    );
 reg [`WIDTH-1:0] H_next_cnt , V_next_cnt;
 reg [`WIDTH-1:0] H_cnt ;
 reg [`WIDTH-1:0] V_cnt ;

 assign H_sync = (H_cnt >=0 & H_cnt < H_retrace)?1'b1: 1'b0;

 assign V_sync = (V_cnt < V_retrace)?1'b1:1'b0;

 assign Vid_on = (H_cnt >(H_Back_porch + H_retrace-1) & H_cnt <=(H_Area-H_Front_porch)) & ((V_cnt >V_Back_porch+ V_retrace-1) & (V_cnt <=V_Area-V_Front_porch))?1'b1 : 1'b0;
 assign pix_x = H_cnt ;
 assign pix_y = V_cnt ;
 

 wire H_total =  (H_cnt == H_Area-1)? 1'b1 :1'b0;

 wire V_total =  (V_cnt == V_Area-1)?1'b1 : 1'b0;
 
 
 always @(posedge i_clk or negedge i_rst_n)
         begin
          if (i_rst_n ==1'b0)
               begin
                  H_cnt <= 0;
                  V_cnt <= 0;
                   end
                 else
                     begin 
                  H_cnt <= H_next_cnt ;
                  V_cnt <= V_next_cnt ; 
           end
    end
                      

 always @(*)
           begin
                  if (pix_clk_25MHZ)
                         begin
                          if (H_total)
                       begin
                             H_next_cnt <= 0;
                                end
                          else
                              begin
                           H_next_cnt <= H_cnt + 1'b1 ;
                     end
                 end
              else
           begin
        H_next_cnt <=H_cnt ;         
       end 
 end 

        

 always @(*)
            if (pix_clk_25MHZ & H_total)
                 begin
                     if (V_total )
                             begin
                                V_next_cnt <= 0;
                                end
                                   else
                                        begin
                                       V_next_cnt <= V_cnt + 1'b1 ;
                                 end  
                             end
                         else
                    begin
                 V_next_cnt <= V_cnt ;
             end    
    
endmodule
module Vga_controller
(input i_clk , 
 input i_rst_n , 
 output H_sync , 
 output V_sync , 
 output Vid_on , 
 output [`WIDTH-1:0] pix_x ,
 output [`WIDTH-1:0] pix_y);

 


   


  parameter H_Area = 800 ;
  parameter H_Disp = 640 ;

  parameter H_retrace = 96 ;
  parameter H_Front_porch = 16 ;
  parameter H_Back_porch = 48 ;
 

  parameter V_Area = 525;
  parameter V_Disp = 480 ;

  parameter V_retrace = 2 ;
  parameter V_Front_porch = 10 ;
  parameter V_Back_porch = 33 ;
 
 wire pix_clk_25MHZ ;
 
	Pix_clk_gen CLK(
    .i_clk(i_clk),
    .i_rst_n(i_rst_n) , 
    .out_clk(pix_clk_25MHZ)
    );
 reg [`WIDTH-1:0] H_next_cnt , V_next_cnt;
 reg [`WIDTH-1:0] H_cnt ;
 reg [`WIDTH-1:0] V_cnt ;

 assign H_sync = (H_cnt >=0 & H_cnt < H_retrace)?1'b1: 1'b0;

 assign V_sync = (V_cnt < V_retrace)?1'b1:1'b0;

 assign Vid_on = (H_cnt >(H_Back_porch + H_retrace-1) & H_cnt <=(H_Area-H_Front_porch)) & ((V_cnt >V_Back_porch+ V_retrace-1) & (V_cnt <=V_Area-V_Front_porch))?1'b1 : 1'b0;
 assign pix_x = H_cnt ;
 assign pix_y = V_cnt ;
 

 wire H_total =  (H_cnt == H_Area-1)? 1'b1 :1'b0;

 wire V_total =  (V_cnt == V_Area-1)?1'b1 : 1'b0;
 
 
 always @(posedge i_clk or negedge i_rst_n)
         begin
          if (i_rst_n ==1'b0)
               begin
                  H_cnt <= 0;
                  V_cnt <= 0;
                   end
                 else
                     begin 
                  H_cnt <= H_next_cnt ;
                  V_cnt <= V_next_cnt ; 
           end
    end
                      

 always @(*)
           begin
                  if (pix_clk_25MHZ)
                         begin
                          if (H_total)
                       begin
                             H_next_cnt <= 0;
                                end
                          else
                              begin
                           H_next_cnt <= H_cnt + 1'b1 ;
                     end
                 end
              else
           begin
        H_next_cnt <=H_cnt ;         
       end 
 end 

        

 always @(*)
            if (pix_clk_25MHZ & H_total)
                 begin
                     if (V_total )
                             begin
                                V_next_cnt <= 0;
                                end
                                   else
                                        begin
                                       V_next_cnt <= V_cnt + 1'b1 ;
                                 end  
                             end
                         else
                    begin
                 V_next_cnt <= V_cnt ;
             end    
    
endmodule