data/full_repos/permissive/46981098/cpu_eda.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46981098/cpu_eda.v:277: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'mux5_2to1\'\nmodule mux5_2to1(out, in0, in1, sel);\n       ^~~~~~~~~\n                                                                    : ... Top module \'cpu\'\nmodule cpu (\n       ^~~\n%Error: data/full_repos/permissive/46981098/cpu_eda.v:298: Duplicate declaration of signal: \'pc\'\n    reg[31:0] pc;\n              ^~\n        data/full_repos/permissive/46981098/cpu_eda.v:280: ... Location of original declaration\n     output reg [31:0] pc,\n                       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/46981098/cpu_eda.v:354: Signal definition not found, creating implicitly: \'mux05_result\'\n                                                                    : ... Suggested alternative: \'mux04_result\'\n   mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);\n                     ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module alu_control(ALUOp,funct,ALUCon);
	input [1:0] ALUOp;
	input [5:0] funct;
	output [3:0] ALUCon;

	reg [3:0] ALUCon;

	always @(*) begin
		case(ALUOp)
			2'b00: ALUCon <= 4'b0010;
			2'b01: ALUCon <= 4'b0110;
            2'b10 :
              begin
                case (funct)
                  6'b100000: ALUCon <= 4'b0010;
                  6'b100010: ALUCon <= 4'b0110;
                  6'b100101: ALUCon <= 4'b0001;
                  6'b100100: ALUCon <= 4'b0000;
                  6'b101010: ALUCon <= 4'b0111;
                  default: 	 ALUCon <= 4'b0000;
                endcase
              end
			default: ALUCon <= 4'b0000;
		endcase
	end

endmodule
module alu_control(ALUOp,funct,ALUCon);

	input [1:0] ALUOp;
	input [5:0] funct;
	output [3:0] ALUCon;

	reg [3:0] ALUCon;

	always @(*) begin
		case(ALUOp)
			2'b00: ALUCon <= 4'b0010;
			2'b01: ALUCon <= 4'b0110;
            2'b10 :
              begin
                case (funct)
                  6'b100000: ALUCon <= 4'b0010;
                  6'b100010: ALUCon <= 4'b0110;
                  6'b100101: ALUCon <= 4'b0001;
                  6'b100100: ALUCon <= 4'b0000;
                  6'b101010: ALUCon <= 4'b0111;
                  default: 	 ALUCon <= 4'b0000;
                endcase
              end
			default: ALUCon <= 4'b0000;
		endcase
	end

endmodule