data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleComplexAdder/reference/SimpleComplexAdder.v
data/verilator_xmls/534200d5-57af-4b87-8be8-729846d8a4c1.xml
module ADD_SIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule
module ADD_SIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule