data/full_repos/permissive/409594175/made/SignExtend16.v
data/verilator_xmls/315647ea-1540-4933-af0c-b444e45064a7.xml
module SignExtend16(
    input  wire [15:0] data_in,
    output wire [31:0] data_out_32 
);

    assign data_out_32 = (data_in[15]) ? {{16{1'b1}}, data_in} : {{16{1'b0}}, data_in};

endmodule
module SignExtend16(
    input  wire [15:0] data_in,
    output wire [31:0] data_out_32 
);


    assign data_out_32 = (data_in[15]) ? {{16{1'b1}}, data_in} : {{16{1'b0}}, data_in};

endmodule