data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20;    \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #32\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #388\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #60;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #500;\n ^\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1self/control_tb.v:14: Cannot find file containing module: \'control\'\ncontrol control_instance(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab7/lab7_1self,data/full_repos/permissive/419538859/control\n             data/full_repos/permissive/419538859/lab7/lab7_1self,data/full_repos/permissive/419538859/control.v\n             data/full_repos/permissive/419538859/lab7/lab7_1self,data/full_repos/permissive/419538859/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;

reg		clk, reset, enable, nightcomes;
wire	[3:0]cnt_d0;
wire	[2:0]NS_lights, EW_lights;


wire		[2:0]next_NS_lights, next_EW_lights;
wire		[1:0]traffic_state, next_state;
wire		timer_clr, EW_side, next_timer_clr, next_EW_side;
wire		[3:0]timer;

control control_instance(
		.clk(clk),
		.reset(reset),
		.enable(enable),

		.nightcomes(nightcomes),
		.cnt_d0(cnt_d0),
		.EW_lights(EW_lights),
		.NS_lights(NS_lights));
parameter	exp = 1; 
parameter clkper = 5;
initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b0;
 enable=1'b0;
 nightcomes=1'b0;
 #20;
 reset = 1'b1;
 #32
 enable=1'b1;
 #388
 nightcomes=1'b1;
 #60;
 nightcomes=1'b0;
 #500;
end
endmodule
module 	testbench;


reg		clk, reset, enable, nightcomes;
wire	[3:0]cnt_d0;
wire	[2:0]NS_lights, EW_lights;


wire		[2:0]next_NS_lights, next_EW_lights;
wire		[1:0]traffic_state, next_state;
wire		timer_clr, EW_side, next_timer_clr, next_EW_side;
wire		[3:0]timer;

control control_instance(
		.clk(clk),
		.reset(reset),
		.enable(enable),

		.nightcomes(nightcomes),
		.cnt_d0(cnt_d0),
		.EW_lights(EW_lights),
		.NS_lights(NS_lights));
parameter	exp = 1; 
parameter clkper = 5;
initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b0;
 enable=1'b0;
 nightcomes=1'b0;
 #20;
 reset = 1'b1;
 #32
 enable=1'b1;
 #388
 nightcomes=1'b1;
 #60;
 nightcomes=1'b0;
 #500;
end
endmodule