data/full_repos/permissive/491135068/leftShift2Module.v
data/verilator_xmls/02980b08-6214-4fa6-9c22-a91ae6239d1d.xml
module leftShift2Module(
    input [31:0] in,
    output reg [31:0] out
    );
    
    always@(in) begin
        out = in << 2;
    end
endmodule
module leftShift2Module(
    input [31:0] in,
    output reg [31:0] out
    );

    
    always@(in) begin
        out = in << 2;
    end
endmodule