data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/control_and_timing_16_a.v
1: b"%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/control_and_timing_16_a.v:223: Duplicate declaration of signal: 'ws_out'\n                                                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg         ws_out          = 1'b0;  \n                ^~~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/control_and_timing_16_a.v:111: ... Location of original declaration\n    output          ws_out,\n                    ^~~~~~\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/control_and_timing_16_a.v:226: Duplicate declaration of signal: 'ws_in'\n    wire        ws_in;                   \n                ^~~~~\n        data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/control_and_timing_16_a.v:110: ... Location of original declaration\n    input           ws_in,           \n                    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module control_and_timing_16_a #(
    parameter       NewArch = 0
)
(

    output          ia_out,
    input           ws_in,
    output          ws_out,
    output          ws_active,
    output reg      SYNC,
    output reg      ROW0,
    output reg      ROW1,
    output reg      ROW3,
    output reg      ROW5,
    output reg      ROW7,


    input           COL3,
    input           COL6,
















































































        .b18        (b18),
        .b35        (b35),
        .b54        (b54),
        .CARRY_FF   (CARRY_FF),
        .stqzero    (stqzero),
        .is_eq_ptr  (IS == ptr[1])
    );





    always@(posedge PHI2) begin : proc_dly_mksum
        makesum_r <= makesum;
    end
    assign sum2sr   = chgstat | (~JSB & stepaddr);
    assign sr2sr    = ~JSB & ~sum2sr;
    assign makesum  = stepaddr | PTI | PTD;
    assign chgstat  = keyset_s0 | SST | RST | IST;
    assign sr2x     = chgstat | stepaddr;
    assign p2x      = PTI;
    assign pn2x     = PTD;
    assign one2y    = makesum & ~makesum_r;
    assign srn2y    = keyset_s0 | SST;
    assign sr2y     = RST | IST;
    assign sr2ci    = IST;
    assign co2ci    = makesum & makesum_r;
    assign sum2p    = PTI;
    assign sumn2p   = PTD;



endmodule
module control_and_timing_16_a #(
    parameter       NewArch = 0
)
(

    output          ia_out,
    input           ws_in,
    output          ws_out,
    output          ws_active,
    output reg      SYNC,
    output reg      ROW0,
    output reg      ROW1,
    output reg      ROW3,
    output reg      ROW5,
    output reg      ROW7,


    input           COL3,
    input           COL6,
















































































        .b18        (b18),
        .b35        (b35),
        .b54        (b54),
        .CARRY_FF   (CARRY_FF),
        .stqzero    (stqzero),
        .is_eq_ptr  (IS == ptr[1])
    );






    always@(posedge PHI2) begin : proc_dly_mksum
        makesum_r <= makesum;
    end
    assign sum2sr   = chgstat | (~JSB & stepaddr);
    assign sr2sr    = ~JSB & ~sum2sr;
    assign makesum  = stepaddr | PTI | PTD;
    assign chgstat  = keyset_s0 | SST | RST | IST;
    assign sr2x     = chgstat | stepaddr;
    assign p2x      = PTI;
    assign pn2x     = PTD;
    assign one2y    = makesum & ~makesum_r;
    assign srn2y    = keyset_s0 | SST;
    assign sr2y     = RST | IST;
    assign sr2ci    = IST;
    assign co2ci    = makesum & makesum_r;
    assign sum2p    = PTI;
    assign sumn2p   = PTD;



endmodule