data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module sender(
	input clk,
	input rst,
	
	input[5:0] f_cmd,
	input[31:0] f_arg,
	input[6:0] f_crc,
	input f_c,
	input f_answ40,
	
	input[4:0] p_tim,
	input[2:0] p_ttim,
	
	input ready,
	input[7:0] into,
	
	output reg rdyread_in,
	
	output reg start1 = 0,
	output reg[7:0] in1 = 0,
	output reg rdy1 = 0

);

reg[4:0] f_tim = 0;
reg[4:0] tim = 0;

reg[2:0] f_ttim = 0;
reg[2:0] ttim = 0;

reg waitforread;
reg f_waitforread;

always@(posedge clk or posedge rst)begin
	if(rst) f_waitforread <= 0;
	else f_waitforread <= waitforread;
end

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_tim <= 0;
		f_ttim <= 0;
	
	end else
	begin
		f_tim <= tim;
		f_ttim <= ttim;
		
	end
end

always@(*) begin	
	tim = f_tim;
	in1 = 0;
	start1 = 0;
	ttim = f_ttim;
	rdy1 = 0;
	
	rdyread_in = 0;
	if(f_cmd == 6'd17) waitforread = 1;
	else waitforread = 0;
	
	if(f_ttim != 0)begin
		ttim = f_ttim - 1;
		
	end
	
	
	if(p_tim != 31) tim = p_tim;
	if(p_ttim != 7) ttim = p_ttim;
		
		case(f_tim)
			1: begin
					if(f_ttim == 0) ttim = 7;
					if(f_ttim == 1) tim = 2;
				end
			2: begin
				if(f_c) in1 = 8'hFF;
				else in1 = {2'b01,f_cmd};
				
				start1 = 1;
				tim = 3;
			end
			3: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 4;
				end
			4:begin
				in1 = f_arg[31:24];
				start1 = 1;
				tim = 5;
			end
			5: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim =6;
				end
			6:begin
				in1 = f_arg[23:16];
				start1 = 1;
				tim = 7;
			end
			7: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 8;
				end
			8:begin
				in1 = f_arg[15:8];
				start1 = 1;
				tim =9;
			end 
			9: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 10;
				end
			10:begin
				in1 = f_arg[7:0];
				start1 = 1;
				tim = 11;
			end
			11: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 12;
				end
			12:begin
				if(f_c) in1 = 8'hFF;
				else in1 = {f_crc,1'b1};
				start1 = 1;
				tim = 13;
			end
			13: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 14;
				end
			14:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 15;
			end
			15: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 16;
				end
			16:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 17;
				
			end
			17: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
						
					if(f_ttim == 1) begin
					
						if(f_answ40)
							if(into == 8'hFE) tim = 26;
							else tim = 18;
						
						else begin
							tim = 0;
							rdy1 = 1;
							end
							
						ttim = 0;
						
					end
					end
			18:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 19;
				
			end
			19: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin
						if(into == 8'hFE) tim = 26;
						else tim = 20;
						end
				end
			20:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 21;
				
			end
			21: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin
						if(into == 8'hFE) tim = 26;
						else tim = 22;
						end
				end
			22:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 23;
				
			end
			23: begin
					if(ready) begin
						
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin 
						if(into == 8'hFE) tim = 26;
						else tim = 24;
						end
				end
			24:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 25;
				
			end

			25: begin
					if(ready) begin
					
						if(into == 8'hFE) tim = 26;
						else if(waitforread) tim = 27;
						else tim = 26;
						
						rdyread_in = 1;
						end
				end
			26: begin
						rdy1 =1;
						tim = 0;
					end
			27: begin
					in1 = 8'd255;
					start1 = 1;
					tim = 28;
			end
			28: begin
					if(ready)
						if(into == 8'hFE) tim = 26;
						else tim = 27;
			end
		endcase
end

endmodule
module sender(
	input clk,
	input rst,
	
	input[5:0] f_cmd,
	input[31:0] f_arg,
	input[6:0] f_crc,
	input f_c,
	input f_answ40,
	
	input[4:0] p_tim,
	input[2:0] p_ttim,
	
	input ready,
	input[7:0] into,
	
	output reg rdyread_in,
	
	output reg start1 = 0,
	output reg[7:0] in1 = 0,
	output reg rdy1 = 0

);


reg[4:0] f_tim = 0;
reg[4:0] tim = 0;

reg[2:0] f_ttim = 0;
reg[2:0] ttim = 0;

reg waitforread;
reg f_waitforread;

always@(posedge clk or posedge rst)begin
	if(rst) f_waitforread <= 0;
	else f_waitforread <= waitforread;
end

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_tim <= 0;
		f_ttim <= 0;
	
	end else
	begin
		f_tim <= tim;
		f_ttim <= ttim;
		
	end
end

always@(*) begin	
	tim = f_tim;
	in1 = 0;
	start1 = 0;
	ttim = f_ttim;
	rdy1 = 0;
	
	rdyread_in = 0;
	if(f_cmd == 6'd17) waitforread = 1;
	else waitforread = 0;
	
	if(f_ttim != 0)begin
		ttim = f_ttim - 1;
		
	end
	
	
	if(p_tim != 31) tim = p_tim;
	if(p_ttim != 7) ttim = p_ttim;
		
		case(f_tim)
			1: begin
					if(f_ttim == 0) ttim = 7;
					if(f_ttim == 1) tim = 2;
				end
			2: begin
				if(f_c) in1 = 8'hFF;
				else in1 = {2'b01,f_cmd};
				
				start1 = 1;
				tim = 3;
			end
			3: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 4;
				end
			4:begin
				in1 = f_arg[31:24];
				start1 = 1;
				tim = 5;
			end
			5: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim =6;
				end
			6:begin
				in1 = f_arg[23:16];
				start1 = 1;
				tim = 7;
			end
			7: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 8;
				end
			8:begin
				in1 = f_arg[15:8];
				start1 = 1;
				tim =9;
			end 
			9: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 10;
				end
			10:begin
				in1 = f_arg[7:0];
				start1 = 1;
				tim = 11;
			end
			11: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 12;
				end
			12:begin
				if(f_c) in1 = 8'hFF;
				else in1 = {f_crc,1'b1};
				start1 = 1;
				tim = 13;
			end
			13: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 14;
				end
			14:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 15;
			end
			15: begin
					if(ready) ttim = 7;
					if(f_ttim == 1) tim = 16;
				end
			16:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 17;
				
			end
			17: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
						
					if(f_ttim == 1) begin
					
						if(f_answ40)
							if(into == 8'hFE) tim = 26;
							else tim = 18;
						
						else begin
							tim = 0;
							rdy1 = 1;
							end
							
						ttim = 0;
						
					end
					end
			18:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 19;
				
			end
			19: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin
						if(into == 8'hFE) tim = 26;
						else tim = 20;
						end
				end
			20:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 21;
				
			end
			21: begin
					if(ready) begin
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin
						if(into == 8'hFE) tim = 26;
						else tim = 22;
						end
				end
			22:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 23;
				
			end
			23: begin
					if(ready) begin
						
						ttim = 7;
						rdyread_in = 1;
						end
					if(f_ttim == 1) begin 
						if(into == 8'hFE) tim = 26;
						else tim = 24;
						end
				end
			24:begin
				in1 = 8'd255;
				start1 = 1;
				tim = 25;
				
			end

			25: begin
					if(ready) begin
					
						if(into == 8'hFE) tim = 26;
						else if(waitforread) tim = 27;
						else tim = 26;
						
						rdyread_in = 1;
						end
				end
			26: begin
						rdy1 =1;
						tim = 0;
					end
			27: begin
					in1 = 8'd255;
					start1 = 1;
					tim = 28;
			end
			28: begin
					if(ready)
						if(into == 8'hFE) tim = 26;
						else tim = 27;
			end
		endcase
end

endmodule