data/full_repos/permissive/443770883/lab2/MUX4to1.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/443770883/lab2/MUX4to1.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\nmodule mux4 (input wire [0:3] i, input wire j1, j0, output wire o);\n                        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux2 (input wire i0, i1, j, output wire o);
  assign o = (j==0)?i0:i1;
endmodule
module mux2 (input wire i0, i1, j, output wire o);

  assign o = (j==0)?i0:i1;
endmodule