data/full_repos/permissive/475644481/simulation/new/top.v
1: b'%Error: data/full_repos/permissive/475644481/simulation/new/top.v:33: Unsupported or unknown PLI call: $monitor\n$monitor("%b,%b,%b,%b,%b,%b,%b\\n",SA,SB,SC,SD,SE,SF,SG);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:40: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:45: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:50: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:55: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:60: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:65: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:70: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:75: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475644481/simulation/new/top.v:80: Unsupported: Ignoring delay on this delayed statement.\n#5  E[0] = 1;\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

reg [0:3]E;
wire SA,SB,SC,SD,SE,SF,SG;

Seven_Segment_Decoder m1(E,SA,SB,SC,SD,SE,SF,SG);

initial
begin

$monitor("%b,%b,%b,%b,%b,%b,%b\n",SA,SB,SC,SD,SE,SF,SG);

    E[0] = 0;
    E[1] = 0;
    E[2] = 0;
    E[3] = 0;       

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 0;
    E[3] = 1;     

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 1;
    E[3] = 0;       

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 1;
    E[3] = 1;  

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 0;
    E[3] = 0;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 0;
    E[3] = 1;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 1;
    E[3] = 0;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 1;
    E[3] = 1;   

#5  E[0] = 1;
    E[1] = 0;
    E[2] = 0;
    E[3] = 0;   

#5  E[0] = 1;
    E[1] = 0;
    E[2] = 0;
    E[3] = 1;        
    
    
end
endmodule
module top();


reg [0:3]E;
wire SA,SB,SC,SD,SE,SF,SG;

Seven_Segment_Decoder m1(E,SA,SB,SC,SD,SE,SF,SG);

initial
begin

$monitor("%b,%b,%b,%b,%b,%b,%b\n",SA,SB,SC,SD,SE,SF,SG);

    E[0] = 0;
    E[1] = 0;
    E[2] = 0;
    E[3] = 0;       

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 0;
    E[3] = 1;     

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 1;
    E[3] = 0;       

#5  E[0] = 0;
    E[1] = 0;
    E[2] = 1;
    E[3] = 1;  

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 0;
    E[3] = 0;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 0;
    E[3] = 1;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 1;
    E[3] = 0;   

#5  E[0] = 0;
    E[1] = 1;
    E[2] = 1;
    E[3] = 1;   

#5  E[0] = 1;
    E[1] = 0;
    E[2] = 0;
    E[3] = 0;   

#5  E[0] = 1;
    E[1] = 0;
    E[2] = 0;
    E[3] = 1;        
    
    
end
endmodule