data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/new/mean.v
1: b'%Warning-WIDTH: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/new/mean.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                                                          : ... In instance mean\n    x_value = rom_memory[i];                         \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/new/mean.v:49: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 bits.\n                                                                                                          : ... In instance mean\n    mean=sum/count;                                      \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module mean(
    input clk,
    output reg [15:0] mean
    );

parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i, sum,x_value, count;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    mean=0;
    sum=0;
    x_value=0;
    count=1;
end

always@(posedge clk) begin
    x_value = rom_memory[i];
    sum = sum + x_value;

    if(i == SIZE)
        
    i = i+ 1;
    count=count+1;
    mean=sum/count;
end

endmodule
module mean(
    input clk,
    output reg [15:0] mean
    );


parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i, sum,x_value, count;

initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    mean=0;
    sum=0;
    x_value=0;
    count=1;
end

always@(posedge clk) begin
    x_value = rom_memory[i];
    sum = sum + x_value;

    if(i == SIZE)
        
    i = i+ 1;
    count=count+1;
    mean=sum/count;
end

endmodule