data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/FullAdder_O.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/FullAdder_O.v:10: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                                                       : ... In instance FullAdder_O\n assign {Cout, Out} = A + B + Cin;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module FullAdder_O  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	A, B,
	input 	wire 				Cin,
	output 	wire [W-1:0] 	Out,
	output 	wire 				Cout
);

	assign {Cout, Out} = A + B + Cin;
endmodule
module FullAdder_O  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	A, B,
	input 	wire 				Cin,
	output 	wire [W-1:0] 	Out,
	output 	wire 				Cout
);


	assign {Cout, Out} = A + B + Cin;
endmodule