data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/fine_delay.v
1: b"%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/fine_delay.v:28: Cannot find file containing module: 'IDELAYCTRL'\n   IDELAYCTRL IDELAYCTRL_inst (\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new,data/full_repos/permissive/416231581/IDELAYCTRL\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new,data/full_repos/permissive/416231581/IDELAYCTRL.v\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new,data/full_repos/permissive/416231581/IDELAYCTRL.sv\n             IDELAYCTRL\n             IDELAYCTRL.v\n             IDELAYCTRL.sv\n             obj_dir/IDELAYCTRL\n             obj_dir/IDELAYCTRL.v\n             obj_dir/IDELAYCTRL.sv\n%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/fine_delay.v:34: Cannot find file containing module: 'IDELAYE2'\n IDELAYE2 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/fine_delay.v:63: Cannot find file containing module: 'IDELAYE2'\n IDELAYE2 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/fine_delay.v:92: Cannot find file containing module: 'IDELAYE2'\n IDELAYE2 #(\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module fine_delay(
    input clk_400,
    input reset,
    input [4:0] fineDelay1,
    input [4:0] fineDelay2,
    input [4:0] fineDelay3,
    input signal_in,
    output [4:0] fineDelay_data1,
    output [4:0] fineDelay_data2,
    output [4:0] fineDelay_data3,
    output signal_delayed
    );

  
 wire signal_predelayed, signal_predelayed2;
 
 wire idelayctrl_rdy;
   IDELAYCTRL IDELAYCTRL_inst (
      .RDY(idelayctrl_rdy),
      .REFCLK(clk_400),
      .RST(reset)
   );   

 IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("DATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VAR_LOAD_PIPE"),
    .IDELAY_VALUE(0),
    .PIPE_SEL("TRUE"),
    .REFCLK_FREQUENCY(400.0),
    .SIGNAL_PATTERN("DATA")
 )
 IDELAYE2_inst (
    .CNTVALUEOUT(fineDelay_data1),
    .DATAOUT(signal_predelayed),
    .C(clk_400),
    .CE(),
    .CINVCTRL(),
    .CNTVALUEIN(fineDelay1),
    .DATAIN(signal_in),
    .IDATAIN(),
    .INC(),
    .LD(1),
    .LDPIPEEN(1),
    .REGRST(!idelayctrl_rdy)
 );
 
 
 
 

 IDELAYE2 #(
     .CINVCTRL_SEL("FALSE"),
     .DELAY_SRC("DATAIN"),
     .HIGH_PERFORMANCE_MODE("TRUE"),
     .IDELAY_TYPE("VAR_LOAD_PIPE"),
     .IDELAY_VALUE(0),
     .PIPE_SEL("TRUE"),
     .REFCLK_FREQUENCY(400.0),
     .SIGNAL_PATTERN("DATA")
  )
 IDELAYE2_inst2 (
     .CNTVALUEOUT(fineDelay_data2),
     .DATAOUT(signal_predelayed2),
     .C(clk_400),
     .CE(),
     .CINVCTRL(),
     .CNTVALUEIN(fineDelay2),
     .DATAIN(signal_predelayed),
     .IDATAIN(),
     .INC(),
     .LD(1),
     .LDPIPEEN(1),
     .REGRST(!idelayctrl_rdy)
  );
  
  
  
  
  
 IDELAYE2 #(
      .CINVCTRL_SEL("FALSE"),
      .DELAY_SRC("DATAIN"),
      .HIGH_PERFORMANCE_MODE("TRUE"),
      .IDELAY_TYPE("VAR_LOAD_PIPE"),
      .IDELAY_VALUE(0),
      .PIPE_SEL("TRUE"),
      .REFCLK_FREQUENCY(400.0),
      .SIGNAL_PATTERN("DATA")
   )
 IDELAYE2_inst3 (
      .CNTVALUEOUT(fineDelay_data3),
      .DATAOUT(signal_delayed),
      .C(clk_400),
      .CE(),
      .CINVCTRL(),
      .CNTVALUEIN(fineDelay3),
      .DATAIN(signal_predelayed2),
      .IDATAIN(),
      .INC(),
      .LD(1),
      .LDPIPEEN(1),
      .REGRST(!idelayctrl_rdy)
   );      
    
endmodule
module fine_delay(
    input clk_400,
    input reset,
    input [4:0] fineDelay1,
    input [4:0] fineDelay2,
    input [4:0] fineDelay3,
    input signal_in,
    output [4:0] fineDelay_data1,
    output [4:0] fineDelay_data2,
    output [4:0] fineDelay_data3,
    output signal_delayed
    );


  
 wire signal_predelayed, signal_predelayed2;
 
 wire idelayctrl_rdy;
   IDELAYCTRL IDELAYCTRL_inst (
      .RDY(idelayctrl_rdy),
      .REFCLK(clk_400),
      .RST(reset)
   );   

 IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("DATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VAR_LOAD_PIPE"),
    .IDELAY_VALUE(0),
    .PIPE_SEL("TRUE"),
    .REFCLK_FREQUENCY(400.0),
    .SIGNAL_PATTERN("DATA")
 )
 IDELAYE2_inst (
    .CNTVALUEOUT(fineDelay_data1),
    .DATAOUT(signal_predelayed),
    .C(clk_400),
    .CE(),
    .CINVCTRL(),
    .CNTVALUEIN(fineDelay1),
    .DATAIN(signal_in),
    .IDATAIN(),
    .INC(),
    .LD(1),
    .LDPIPEEN(1),
    .REGRST(!idelayctrl_rdy)
 );
 
 
 
 

 IDELAYE2 #(
     .CINVCTRL_SEL("FALSE"),
     .DELAY_SRC("DATAIN"),
     .HIGH_PERFORMANCE_MODE("TRUE"),
     .IDELAY_TYPE("VAR_LOAD_PIPE"),
     .IDELAY_VALUE(0),
     .PIPE_SEL("TRUE"),
     .REFCLK_FREQUENCY(400.0),
     .SIGNAL_PATTERN("DATA")
  )
 IDELAYE2_inst2 (
     .CNTVALUEOUT(fineDelay_data2),
     .DATAOUT(signal_predelayed2),
     .C(clk_400),
     .CE(),
     .CINVCTRL(),
     .CNTVALUEIN(fineDelay2),
     .DATAIN(signal_predelayed),
     .IDATAIN(),
     .INC(),
     .LD(1),
     .LDPIPEEN(1),
     .REGRST(!idelayctrl_rdy)
  );
  
  
  
  
  
 IDELAYE2 #(
      .CINVCTRL_SEL("FALSE"),
      .DELAY_SRC("DATAIN"),
      .HIGH_PERFORMANCE_MODE("TRUE"),
      .IDELAY_TYPE("VAR_LOAD_PIPE"),
      .IDELAY_VALUE(0),
      .PIPE_SEL("TRUE"),
      .REFCLK_FREQUENCY(400.0),
      .SIGNAL_PATTERN("DATA")
   )
 IDELAYE2_inst3 (
      .CNTVALUEOUT(fineDelay_data3),
      .DATAOUT(signal_delayed),
      .C(clk_400),
      .CE(),
      .CINVCTRL(),
      .CNTVALUEIN(fineDelay3),
      .DATAIN(signal_predelayed2),
      .IDATAIN(),
      .INC(),
      .LD(1),
      .LDPIPEEN(1),
      .REGRST(!idelayctrl_rdy)
   );      
    
endmodule