data/full_repos/permissive/515186003/univ_shift_reg.v
data/verilator_xmls/f3975291-df1a-4817-9745-d6873736f923.xml
module UniversalShiftReg(
    input clk,
    input clr,
    input s0,
    input s1,
    input q0,
    input q1,
    input q2,
    input q3,
    input sinr,
    input sinl,
    output d0,
    output d1,
    output d2,
    output d3
    );
    wire out0,out1,out2,out3;
    
    mux a1(s0,s1,d0,sinr,d1,q0,out0);
    mux a2(s0,s1,d1,d0,d2,q1,out1);
    mux a3(s0,s1,d2,d1,d3,q2,out2);
    mux a4(s0,s1,d3,d2,sinl,q3,out3);
    DFF f1(out0,clk,clr,d0);
    DFF f2(out1,clk,clr,d1);
    DFF f3(out2,clk,clr,d2);
    DFF f4(out3,clk,clr,d3);
    
endmodule
module UniversalShiftReg(
    input clk,
    input clr,
    input s0,
    input s1,
    input q0,
    input q1,
    input q2,
    input q3,
    input sinr,
    input sinl,
    output d0,
    output d1,
    output d2,
    output d3
    );

    wire out0,out1,out2,out3;
    
    mux a1(s0,s1,d0,sinr,d1,q0,out0);
    mux a2(s0,s1,d1,d0,d2,q1,out1);
    mux a3(s0,s1,d2,d1,d3,q2,out2);
    mux a4(s0,s1,d3,d2,sinl,q3,out3);
    DFF f1(out0,clk,clr,d0);
    DFF f2(out1,clk,clr,d1);
    DFF f3(out2,clk,clr,d2);
    DFF f4(out3,clk,clr,d3);
    
endmodule