data/full_repos/permissive/441359809/src/yosys/tests/sva/basic02.sv
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/basic02.sv:16: syntax error, unexpected |=>, expecting ')'\n a_wr: assert property ( @(posedge clock) write |=> ready );\n                                                ^~~\n%Error: Exiting due to 1 error(s)\n"
module top_properties (input logic clock, read, write, ready);
	a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL
	a_wr: assert property ( @(posedge clock) write |-> ready );
`else
	a_wr: assert property ( @(posedge clock) write |=> ready );
`endif
endmodule
module top_properties (input logic clock, read, write, ready);

	a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL
	a_wr: assert property ( @(posedge clock) write |-> ready );
`else
	a_wr: assert property ( @(posedge clock) write |=> ready );
`endif
endmodule