data/full_repos/permissive/479923049/shifter.v
data/verilator_xmls/dec7a17b-c95c-481e-af0d-7b34bd631f55.xml
module shifter(in,shift,sout);
    input   [15:0] in;
    input   [1:0] shift;
    output  [15:0] sout;

    reg [15:0] sout;
    reg tempbm;

    always @(*) begin
        tempbm = in[15];

        case(shift)
            2'b00: sout = in; 
            2'b01: sout = in << 1;
            2'b10: sout = in >> 1;
            2'b11: sout = in >> 1;
            default: sout = {16{1'bx}};
        endcase
        
        if (shift == 2'b11)
            sout[15] = tempbm;
    end
endmodule
module shifter(in,shift,sout);

    input   [15:0] in;
    input   [1:0] shift;
    output  [15:0] sout;

    reg [15:0] sout;
    reg tempbm;

    always @(*) begin
        tempbm = in[15];

        case(shift)
            2'b00: sout = in; 
            2'b01: sout = in << 1;
            2'b10: sout = in >> 1;
            2'b11: sout = in >> 1;
            default: sout = {16{1'bx}};
        endcase
        
        if (shift == 2'b11)
            sout[15] = tempbm;
    end
endmodule