data/full_repos/permissive/465239880/RTL/slow_clk.v
data/verilator_xmls/7519c466-8413-45e1-8eab-21230fb785c9.xml
module slow_clk(
    input i_clk,
    output out_slow_clk
    );
parameter DATA_WIDTH = 25 ;


parameter count_5HZ = 10_000_000;
reg [DATA_WIDTH-1:0] reg_CNT_5HZ ;

reg Toggle_5HZ ;

always @ (posedge i_clk)
  begin 
   reg_CNT_5HZ = reg_CNT_5HZ + 1'b1 ;
               if (reg_CNT_5HZ == count_5HZ-1)
         begin
               Toggle_5HZ = ~Toggle_5HZ ;
               reg_CNT_5HZ = 0 ;
          end
           
end			  

assign out_slow_clk = Toggle_5HZ ;									  
endmodule
module slow_clk(
    input i_clk,
    output out_slow_clk
    );

parameter DATA_WIDTH = 25 ;


parameter count_5HZ = 10_000_000;
reg [DATA_WIDTH-1:0] reg_CNT_5HZ ;

reg Toggle_5HZ ;

always @ (posedge i_clk)
  begin 
   reg_CNT_5HZ = reg_CNT_5HZ + 1'b1 ;
               if (reg_CNT_5HZ == count_5HZ-1)
         begin
               Toggle_5HZ = ~Toggle_5HZ ;
               reg_CNT_5HZ = 0 ;
          end
           
end			  

assign out_slow_clk = Toggle_5HZ ;									  
endmodule