data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:18: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'test_def\'\nmodule test_def(a, y);\n       ^~~~~~~~\n                                                                                          : ... Top module \'test_ifdef\'\nmodule test_ifdef(a, y);\n       ^~~~~~~~~~\n                                                                                          : ... Top module \'test_comment_in_macro\'\nmodule test_comment_in_macro ( din_a, dout_a );\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:37: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:44: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[1];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:51: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:60: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:70: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:79: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:92: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:99: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance test_ifdef\n   y = (y << 1) | a[1];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:108: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:112: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:119: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:127: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:140: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:147: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[1];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:154: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:163: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:173: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:182: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:195: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:202: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[1];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:211: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:215: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:222: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/macros.v:230: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance test_ifdef\n   y = (y << 1) | a[2];\n                ^\n%Error: Exiting due to 25 warning(s)\n'
module test_ifdef(a, y);

input [2:0] a;
output reg [31:0] y;

always @* begin
	y = 0;

	`undef X
	`ifdef X
		y = y + 42;
	`else
		`undef  A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef  A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
	`endif

	`define X
	`ifdef X
		`undef  A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef  A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
	`else
		y = y + 42;
	`endif
end

endmodule
module test_ifdef(a, y);


input [2:0] a;
output reg [31:0] y;

always @* begin
	y = 0;

	`undef X
	`ifdef X
		y = y + 42;
	`else
		`undef  A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef  A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
	`endif

	`define X
	`ifdef X
		`undef  A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifdef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef  A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`undef  A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`undef  B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`define B
		`ifndef A
			y = (y << 1) | a[0];
		`elsif B
			y = (y << 1) | a[1];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifdef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif

		`undef A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
		`define A
		`ifndef A
			y = (y << 1) | a[0];
		`else
			y = (y << 1) | a[2];
		`endif
	`else
		y = y + 42;
	`endif
end

endmodule