data/full_repos/permissive/429462627/mips_pipeline.v
1: b'%Error: data/full_repos/permissive/429462627/mips_pipeline.v:138: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " :A = %b,\\n\\t B = %b,\\n\\t ALU_ctrlerartion = %b,\\n\\t Result = %b,\\n\\t Carry Out = %b,\\n\\t Zero = %b.", A, B, ALU_ctrl, result, carry_out, zero);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #0  A = 32\'ha5a5a5a5; B = 32\'h5a5a5a5a; ALU_ctrl = 4\'b0000;      \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0001;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0010;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0110;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10  A = 32\'hA5A5A5A5; B = 32\'hA5A5A5A5; ALU_ctrl = 4\'b0110;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b0111;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b1100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #20  $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1090: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1096: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1098: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipelined_proc (
    input clk, reset, 
    output [31:0] read_data1);


    wire [31:0] pc_in;
    wire [31:0] pc_out;
    program_counter #(.N(32)) u0 (.clk(clk), .reset(reset), .PCWrite(PCWrite), .pc_in(pc_in), .pc_out(pc_out));


    wire [31:0] instruction;
    instruction_memory u1 (.reset(reset), .read_addr(pc_out), .instruction(instruction));


    wire [31:0] pc_inc4;
    wire carry_out;
    wire zero; 
    ALU_32_bit u2 (.ALU_ctrl(4'b0010), .A(pc_out), .B(32'b0100), .result(pc_inc4), .carry_out(carry_out), .zero(zero));


    wire [31:0] branch_jump_addr;
    wire PCsrc;
    mux_N_bit #(.N(32)) u3 (.in0(pc_inc4), .in1(branch_jump_addr), .select(PCSrc), .mux_out(pc_out));


    wire [31:0] IF_ID_pc_out;
    wire [31:0] IF_ID_instruction_out;
    IF_ID_reg u4 (.clk(clk), .reset(reset), .IF_ID_write(IF_ID_write), .IF_flush(IF_flush), .pc_inc4_in(pc_inc4), .instruction_in(instruction), .pc_inc4_out(IF_ID_pc_out), .instruction_out(IF_ID_instruction_out));


    wire RegWrite;
    wire [4:0] read_addr1;
    wire [4:0] MEM_WB_register_rd;
    wire [31:0] reg_write_data;

    wire [31:0] read_data2;
    register_file u5 (.clk(clk), .reset(reset), .RegWrite(RegWrite), .read_addr1(read_addr1), .read_addr2(IF_ID_instruction_out[20:16]), .write_addr(MEM_WB_register_rd), .write_data(reg_write_data), .read_data1(read_data1), .read_data2(read_data2));


    wire [31:0] imm_sign_extended;
    sign_extender u6 (.in(IF_ID_instruction_out[15:0]), .out(imm_sign_extended));


    wire [27:0] jump_target;
    left_shifter_jump u7 (.in(IF_ID_instruction_out[25:0]), .out(jump_target));
    wire [31:0] jump_addr;
    assign jump_addr = {IF_ID_pc_out[31:28], jump_target}; 


    wire RegDst; 
    wire Jump; 
    wire Branch; 
    wire MemRead; 
    wire MemtoReg; 
    wire MemWrite; 
    wire ALUSrc; 

    wire [1:0] ALU_op;
    main_control u8 (.op_code(IF_ID_instruction_out[31:26]),.RegDst(RegDst), .Jump(Jump), .Branch(Branch), .MemRead(MemRead), .MemtoReg(MemtoReg), .MemWrite(MemWrite), .ALUSrc(ALUSrc), .RegWrite(RegWrite), .ALU_op(ALU_op));


    wire ID_EX_RegDst, ID_EX_Jump, ID_EX_Branch, ID_EX_MemRead, ID_EX_MemtoReg, ID_EX_MemWrite, ID_EX_ALUSrc, ID_EX_RegWrite;
    wire [1:0] ID_EX_ALUOp;
    wire [31:0] ID_EX_jump_addr;
    wire [31:0] ID_EX_pc_inc4, ID_EX_reg_read_data1, ID_EX_reg_read_data2;
    wire [31:0] ID_EX_imm_sign_extended;
    wire [4:0] ID_EX_register_rs, ID_EX_register_rt, ID_EX_register_rd;
    wire [5:0] ID_EX_funct, ID_EX_opcode;
    ID_EX_reg u9 (.clk(clk), .reset(reset), .ID_flush_lw_stall(ID_flush_lw_stall), .ID_flush_branch(ID_flush_branch), .RegWrite_in(RegWrite), .MemtoReg_in(MemtoReg), .Branch_in(Branch), .MemRead_in(MemRead), .MemWrite_in(MemWrite), .Jump_in(Jump), 
    .RegDst_in(RegDst), .ALUSrc_in(ALUSrc), .ALUOp_in(ALU_op), .jump_addr_in(jump_addr), .pc_inc4_in(IF_ID_pc_out), .IF_ID_register_rs_in(IF_ID_instruction_out[25:21]), .IF_ID_register_rt_in(IF_ID_instruction_out[20:16]), 
    .IF_ID_register_rd_in(IF_ID_instruction_out[15:11]), .IF_ID_funct_in(IF_ID_instruction_out[5:0]), .IF_ID_opcode_in(IF_ID_instruction_out[31:26]), .RegWrite_out(ID_EX_RegWrite), .MemtoReg_out(ID_EX_MemtoReg), 
    .Branch_out(ID_EX_Branch), .MemRead_out(ID_EX_MemRead), .MemWrite_out(ID_EX_MemWrite), .Jump_out(ID_EX_Jump), .reg_read_data1_in(read_data1), .reg_read_data2_in(read_data2), .imm_sign_extended_in(imm_sign_extended),
    .RegDst_out(ID_EX_RegDst), .ALUSrc_out(ID_EX_ALUSrc), .ALUOp_out(ID_EX_ALUOp), .jump_addr_out(ID_EX_jump_addr), .pc_inc4_out(ID_EX_pc_inc4),.reg_read_data1_out(ID_EX_reg_read_data1), .reg_read_data2_out(ID_EX_reg_read_data2), 
    .imm_sign_extended_out(ID_EX_imm_sign_extended), .IF_ID_register_rs_out(ID_EX_register_rs), .IF_ID_register_rt_out(ID_EX_register_rt), .IF_ID_register_rd_out(ID_EX_register_rd), .IF_ID_funct_out(ID_EX_funct), 
    .IF_ID_opcode_out(ID_EX_opcode));
 

    wire [4:0] EX_register_rd;
    mux_N_bit #(.N(5)) u10 (.in0(ID_EX_register_rt), .in1(ID_EX_register_rd), .select(ID_EX_RegDst), .mux_out(EX_register_rd));


    wire [3:0] ALU_ctrl;
    ALU_control u11 (.ALU_op(ID_EX_ALUOp), .funct(ID_EX_funct), .op_code(ID_EX_opcode), .ALU_ctrl(ALU_ctrl));


    wire [31:0] muxA_out, muxB_out;
    wire [1:0] ForwardA, ForwardB;
    wire [31:0] EX_MEM_ALU_result;
    mux_N_bit_3to1 #(.N(32)) u12 (.in0(ID_EX_reg_read_data1), .in1(reg_write_data), .in2(EX_MEM_ALU_result), .select(ForwardA), .mux_out(muxA_out)); 
    mux_N_bit_3to1 #(.N(32)) u13 (.in0(ID_EX_reg_read_data2), .in1(reg_write_data), .in2(EX_MEM_ALU_result), .select(ForwardB), .mux_out(muxB_out)); 

    wire [31:0] after_ALUSrc;
    mux_N_bit #(.N(32)) u14 (.in0(muxB_out), .in1(ID_EX_imm_sign_extended), .select(ID_EX_ALUSrc), .mux_out(after_ALUSrc));


    wire [31:0] ALU_result;
    wire ALU_zero, ALU_carry_out;
    ALU_32_bit u15 (.ALU_ctrl(ALU_ctrl), .A(muxA_out), .B(after_ALUSrc), .result(ALU_result), .carry_out(ALU_carry_out), .zero(ALU_zero));


    wire [31:0] after_shift;
    left_shifter_branch u16 (.in(ID_EX_imm_sign_extended), .out(after_shift));
    wire [31:0] branch_addr;
    ALU_32_bit u17 (.ALU_ctrl(4'b0010), .A(ID_EX_pc_inc4), .B(after_shift), .result(branch_addr), .carry_out(carry_out), .zero(zero));


    wire [4:0] EX_MEM_register_rd;
    wire EX_MEM_RegWrite, EX_MEM_MemtoReg, EX_MEM_Branch, EX_MEM_MemRead, EX_MEM_MemWrite, EX_MEM_Jump;
    wire [31:0] EX_MEM_jump_addr, EX_MEM_branch_addr;
    wire EX_MEM_ALU_zero;
    wire [31:0] EX_MEM_reg_read_data2;
    EX_MEM_reg u18 (.clk(clk), .reset(reset), .EX_flush(EX_flush), .RegWrite_in(ID_EX_RegWrite), .MemtoReg_in(ID_EX_MemtoReg), .Branch_in(ID_EX_Branch), 
    .MemRead_in(ID_EX_MemRead), .MemWrite_in(ID_EX_MemWrite), .Jump_in(ID_EX_Jump), .jump_addr_in(ID_EX_jump_addr), .branch_addr_in(branch_addr),
    .ALU_zero_in(ALU_zero), .ALU_result_in(ALU_result), .reg_read_data2_in(muxB_out), .ID_EX_register_rd_in(EX_register_rd), .RegWrite_out(EX_MEM_RegWrite), 
    .MemtoReg_out(EX_MEM_MemtoReg), .Branch_out(EX_MEM_Branch), .MemRead_out(EX_MEM_MemRead), .MemWrite_out(EX_MEM_MemWrite), .Jump_out(EX_MEM_Jump),  
    .jump_addr_out(EX_MEM_jump_addr), .branch_addr_out(EX_MEM_branch_addr), .ALU_zero_out(EX_MEM_ALU_zero), .ALU_result_out(EX_MEM_ALU_result), 
    .reg_read_data2_out(EX_MEM_reg_read_data2), .EX_MEM_register_rd_out(EX_MEM_register_rd));


    wire [31:0] dm_read_data;
    data_memory u19 ( .clk(clk), .reset(reset), .MemRead(EX_MEM_MemRead), .MemWrite(EX_MEM_MemWrite),.addr(EX_MEM_ALU_result[7:0]), .write_data(EX_MEM_reg_read_data2), .read_data(dm_read_data));
    and (Branch_taken, EX_MEM_Branch, EX_MEM_ALU_zero);



    determine_jump_or_branch u20 (.Jump(EX_MEM_Jump), .Branch_taken(Branch_taken), .branch_addr(EX_MEM_branch_addr), .jump_addr(EX_MEM_jump_addr), .PCSrc(PCSrc), .addr_out(branch_jump_addr));


    wire MEM_WB_RegWrite, MEM_WB_MemtoReg;
    wire [31:0] MEM_WB_dm_read_data, MEM_WB_dm_read_addr;
    MEM_WB_reg u21 (.clk(clk), .reset(reset), .RegWrite_in(EX_MEM_RegWrite), .MemtoReg_in(EX_MEM_MemtoReg), .dm_read_data_in(dm_read_data), .dm_read_addr_in(EX_MEM_ALU_result), 
    .EX_MEM_register_rd_in(EX_MEM_register_rd), .RegWrite_out(MEM_WB_RegWrite), .MemtoReg_out(MEM_WB_MemtoReg),  .dm_read_data_out(MEM_WB_dm_read_data), 
    .dm_read_addr_out(MEM_WB_dm_read_addr), .MEM_WB_register_rd_out(MEM_WB_register_rd));
    mux_N_bit #(32) u22 (.in0(MEM_WB_dm_read_addr), .in1(MEM_WB_dm_read_data), .select(MEM_WB_MemtoReg), .mux_out(reg_write_data));


    forwarding_unit u23 (.EX_MEM_RegWrite(EX_MEM_RegWrite), .MEM_WB_RegWrite(MEM_WB_RegWrite), .IF_ID_register_rs(IF_ID_instruction_out[25:21]),.IF_ID_register_rt(IF_ID_instruction_out[20:16]),
    .ID_EX_register_rs(ID_EX_register_rs), .ID_EX_register_rt(ID_EX_register_rt), .EX_MEM_register_rd(EX_MEM_register_rd), .MEM_WB_register_rd(MEM_WB_register_rd), 
    .ForwardA(ForwardA), .ForwardB(ForwardB));


    lw_stall_unit u24 (.ID_EX_MemRead(ID_EX_MemRead), .ID_EX_register_rt(ID_EX_register_rt), .IF_ID_register_rs(IF_ID_instruction_out[25:21]), .IF_ID_register_rt(IF_ID_instruction_out[20:16]),
    .PCWrite(PCWrite), .IF_ID_write(IF_ID_write), .ID_flush_lw_stall(ID_flush_lw_stall));
    branch_and_jump_hazard_unit u25 (.MEM_PCSrc(PCSrc), .IF_flush(IF_flush), .ID_flush_branch(ID_flush_branch), .EX_flush(EX_flush));

endmodule
module pipelined_proc (
    input clk, reset, 
    output [31:0] read_data1);



    wire [31:0] pc_in;
    wire [31:0] pc_out;
    program_counter #(.N(32)) u0 (.clk(clk), .reset(reset), .PCWrite(PCWrite), .pc_in(pc_in), .pc_out(pc_out));


    wire [31:0] instruction;
    instruction_memory u1 (.reset(reset), .read_addr(pc_out), .instruction(instruction));


    wire [31:0] pc_inc4;
    wire carry_out;
    wire zero; 
    ALU_32_bit u2 (.ALU_ctrl(4'b0010), .A(pc_out), .B(32'b0100), .result(pc_inc4), .carry_out(carry_out), .zero(zero));


    wire [31:0] branch_jump_addr;
    wire PCsrc;
    mux_N_bit #(.N(32)) u3 (.in0(pc_inc4), .in1(branch_jump_addr), .select(PCSrc), .mux_out(pc_out));


    wire [31:0] IF_ID_pc_out;
    wire [31:0] IF_ID_instruction_out;
    IF_ID_reg u4 (.clk(clk), .reset(reset), .IF_ID_write(IF_ID_write), .IF_flush(IF_flush), .pc_inc4_in(pc_inc4), .instruction_in(instruction), .pc_inc4_out(IF_ID_pc_out), .instruction_out(IF_ID_instruction_out));


    wire RegWrite;
    wire [4:0] read_addr1;
    wire [4:0] MEM_WB_register_rd;
    wire [31:0] reg_write_data;

    wire [31:0] read_data2;
    register_file u5 (.clk(clk), .reset(reset), .RegWrite(RegWrite), .read_addr1(read_addr1), .read_addr2(IF_ID_instruction_out[20:16]), .write_addr(MEM_WB_register_rd), .write_data(reg_write_data), .read_data1(read_data1), .read_data2(read_data2));


    wire [31:0] imm_sign_extended;
    sign_extender u6 (.in(IF_ID_instruction_out[15:0]), .out(imm_sign_extended));


    wire [27:0] jump_target;
    left_shifter_jump u7 (.in(IF_ID_instruction_out[25:0]), .out(jump_target));
    wire [31:0] jump_addr;
    assign jump_addr = {IF_ID_pc_out[31:28], jump_target}; 


    wire RegDst; 
    wire Jump; 
    wire Branch; 
    wire MemRead; 
    wire MemtoReg; 
    wire MemWrite; 
    wire ALUSrc; 

    wire [1:0] ALU_op;
    main_control u8 (.op_code(IF_ID_instruction_out[31:26]),.RegDst(RegDst), .Jump(Jump), .Branch(Branch), .MemRead(MemRead), .MemtoReg(MemtoReg), .MemWrite(MemWrite), .ALUSrc(ALUSrc), .RegWrite(RegWrite), .ALU_op(ALU_op));


    wire ID_EX_RegDst, ID_EX_Jump, ID_EX_Branch, ID_EX_MemRead, ID_EX_MemtoReg, ID_EX_MemWrite, ID_EX_ALUSrc, ID_EX_RegWrite;
    wire [1:0] ID_EX_ALUOp;
    wire [31:0] ID_EX_jump_addr;
    wire [31:0] ID_EX_pc_inc4, ID_EX_reg_read_data1, ID_EX_reg_read_data2;
    wire [31:0] ID_EX_imm_sign_extended;
    wire [4:0] ID_EX_register_rs, ID_EX_register_rt, ID_EX_register_rd;
    wire [5:0] ID_EX_funct, ID_EX_opcode;
    ID_EX_reg u9 (.clk(clk), .reset(reset), .ID_flush_lw_stall(ID_flush_lw_stall), .ID_flush_branch(ID_flush_branch), .RegWrite_in(RegWrite), .MemtoReg_in(MemtoReg), .Branch_in(Branch), .MemRead_in(MemRead), .MemWrite_in(MemWrite), .Jump_in(Jump), 
    .RegDst_in(RegDst), .ALUSrc_in(ALUSrc), .ALUOp_in(ALU_op), .jump_addr_in(jump_addr), .pc_inc4_in(IF_ID_pc_out), .IF_ID_register_rs_in(IF_ID_instruction_out[25:21]), .IF_ID_register_rt_in(IF_ID_instruction_out[20:16]), 
    .IF_ID_register_rd_in(IF_ID_instruction_out[15:11]), .IF_ID_funct_in(IF_ID_instruction_out[5:0]), .IF_ID_opcode_in(IF_ID_instruction_out[31:26]), .RegWrite_out(ID_EX_RegWrite), .MemtoReg_out(ID_EX_MemtoReg), 
    .Branch_out(ID_EX_Branch), .MemRead_out(ID_EX_MemRead), .MemWrite_out(ID_EX_MemWrite), .Jump_out(ID_EX_Jump), .reg_read_data1_in(read_data1), .reg_read_data2_in(read_data2), .imm_sign_extended_in(imm_sign_extended),
    .RegDst_out(ID_EX_RegDst), .ALUSrc_out(ID_EX_ALUSrc), .ALUOp_out(ID_EX_ALUOp), .jump_addr_out(ID_EX_jump_addr), .pc_inc4_out(ID_EX_pc_inc4),.reg_read_data1_out(ID_EX_reg_read_data1), .reg_read_data2_out(ID_EX_reg_read_data2), 
    .imm_sign_extended_out(ID_EX_imm_sign_extended), .IF_ID_register_rs_out(ID_EX_register_rs), .IF_ID_register_rt_out(ID_EX_register_rt), .IF_ID_register_rd_out(ID_EX_register_rd), .IF_ID_funct_out(ID_EX_funct), 
    .IF_ID_opcode_out(ID_EX_opcode));
 

    wire [4:0] EX_register_rd;
    mux_N_bit #(.N(5)) u10 (.in0(ID_EX_register_rt), .in1(ID_EX_register_rd), .select(ID_EX_RegDst), .mux_out(EX_register_rd));


    wire [3:0] ALU_ctrl;
    ALU_control u11 (.ALU_op(ID_EX_ALUOp), .funct(ID_EX_funct), .op_code(ID_EX_opcode), .ALU_ctrl(ALU_ctrl));


    wire [31:0] muxA_out, muxB_out;
    wire [1:0] ForwardA, ForwardB;
    wire [31:0] EX_MEM_ALU_result;
    mux_N_bit_3to1 #(.N(32)) u12 (.in0(ID_EX_reg_read_data1), .in1(reg_write_data), .in2(EX_MEM_ALU_result), .select(ForwardA), .mux_out(muxA_out)); 
    mux_N_bit_3to1 #(.N(32)) u13 (.in0(ID_EX_reg_read_data2), .in1(reg_write_data), .in2(EX_MEM_ALU_result), .select(ForwardB), .mux_out(muxB_out)); 

    wire [31:0] after_ALUSrc;
    mux_N_bit #(.N(32)) u14 (.in0(muxB_out), .in1(ID_EX_imm_sign_extended), .select(ID_EX_ALUSrc), .mux_out(after_ALUSrc));


    wire [31:0] ALU_result;
    wire ALU_zero, ALU_carry_out;
    ALU_32_bit u15 (.ALU_ctrl(ALU_ctrl), .A(muxA_out), .B(after_ALUSrc), .result(ALU_result), .carry_out(ALU_carry_out), .zero(ALU_zero));


    wire [31:0] after_shift;
    left_shifter_branch u16 (.in(ID_EX_imm_sign_extended), .out(after_shift));
    wire [31:0] branch_addr;
    ALU_32_bit u17 (.ALU_ctrl(4'b0010), .A(ID_EX_pc_inc4), .B(after_shift), .result(branch_addr), .carry_out(carry_out), .zero(zero));


    wire [4:0] EX_MEM_register_rd;
    wire EX_MEM_RegWrite, EX_MEM_MemtoReg, EX_MEM_Branch, EX_MEM_MemRead, EX_MEM_MemWrite, EX_MEM_Jump;
    wire [31:0] EX_MEM_jump_addr, EX_MEM_branch_addr;
    wire EX_MEM_ALU_zero;
    wire [31:0] EX_MEM_reg_read_data2;
    EX_MEM_reg u18 (.clk(clk), .reset(reset), .EX_flush(EX_flush), .RegWrite_in(ID_EX_RegWrite), .MemtoReg_in(ID_EX_MemtoReg), .Branch_in(ID_EX_Branch), 
    .MemRead_in(ID_EX_MemRead), .MemWrite_in(ID_EX_MemWrite), .Jump_in(ID_EX_Jump), .jump_addr_in(ID_EX_jump_addr), .branch_addr_in(branch_addr),
    .ALU_zero_in(ALU_zero), .ALU_result_in(ALU_result), .reg_read_data2_in(muxB_out), .ID_EX_register_rd_in(EX_register_rd), .RegWrite_out(EX_MEM_RegWrite), 
    .MemtoReg_out(EX_MEM_MemtoReg), .Branch_out(EX_MEM_Branch), .MemRead_out(EX_MEM_MemRead), .MemWrite_out(EX_MEM_MemWrite), .Jump_out(EX_MEM_Jump),  
    .jump_addr_out(EX_MEM_jump_addr), .branch_addr_out(EX_MEM_branch_addr), .ALU_zero_out(EX_MEM_ALU_zero), .ALU_result_out(EX_MEM_ALU_result), 
    .reg_read_data2_out(EX_MEM_reg_read_data2), .EX_MEM_register_rd_out(EX_MEM_register_rd));


    wire [31:0] dm_read_data;
    data_memory u19 ( .clk(clk), .reset(reset), .MemRead(EX_MEM_MemRead), .MemWrite(EX_MEM_MemWrite),.addr(EX_MEM_ALU_result[7:0]), .write_data(EX_MEM_reg_read_data2), .read_data(dm_read_data));
    and (Branch_taken, EX_MEM_Branch, EX_MEM_ALU_zero);



    determine_jump_or_branch u20 (.Jump(EX_MEM_Jump), .Branch_taken(Branch_taken), .branch_addr(EX_MEM_branch_addr), .jump_addr(EX_MEM_jump_addr), .PCSrc(PCSrc), .addr_out(branch_jump_addr));


    wire MEM_WB_RegWrite, MEM_WB_MemtoReg;
    wire [31:0] MEM_WB_dm_read_data, MEM_WB_dm_read_addr;
    MEM_WB_reg u21 (.clk(clk), .reset(reset), .RegWrite_in(EX_MEM_RegWrite), .MemtoReg_in(EX_MEM_MemtoReg), .dm_read_data_in(dm_read_data), .dm_read_addr_in(EX_MEM_ALU_result), 
    .EX_MEM_register_rd_in(EX_MEM_register_rd), .RegWrite_out(MEM_WB_RegWrite), .MemtoReg_out(MEM_WB_MemtoReg),  .dm_read_data_out(MEM_WB_dm_read_data), 
    .dm_read_addr_out(MEM_WB_dm_read_addr), .MEM_WB_register_rd_out(MEM_WB_register_rd));
    mux_N_bit #(32) u22 (.in0(MEM_WB_dm_read_addr), .in1(MEM_WB_dm_read_data), .select(MEM_WB_MemtoReg), .mux_out(reg_write_data));


    forwarding_unit u23 (.EX_MEM_RegWrite(EX_MEM_RegWrite), .MEM_WB_RegWrite(MEM_WB_RegWrite), .IF_ID_register_rs(IF_ID_instruction_out[25:21]),.IF_ID_register_rt(IF_ID_instruction_out[20:16]),
    .ID_EX_register_rs(ID_EX_register_rs), .ID_EX_register_rt(ID_EX_register_rt), .EX_MEM_register_rd(EX_MEM_register_rd), .MEM_WB_register_rd(MEM_WB_register_rd), 
    .ForwardA(ForwardA), .ForwardB(ForwardB));


    lw_stall_unit u24 (.ID_EX_MemRead(ID_EX_MemRead), .ID_EX_register_rt(ID_EX_register_rt), .IF_ID_register_rs(IF_ID_instruction_out[25:21]), .IF_ID_register_rt(IF_ID_instruction_out[20:16]),
    .PCWrite(PCWrite), .IF_ID_write(IF_ID_write), .ID_flush_lw_stall(ID_flush_lw_stall));
    branch_and_jump_hazard_unit u25 (.MEM_PCSrc(PCSrc), .IF_flush(IF_flush), .ID_flush_branch(ID_flush_branch), .EX_flush(EX_flush));

endmodule