data/full_repos/permissive/517777997/verilog/rtl/user_id_programming.v
1: b"%Error: data/full_repos/permissive/517777997/verilog/rtl/user_id_programming.v:38: Can't resolve module reference: 'gf180mcu_fd_sc_mcu7t5v0__tieh'\n    gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one [31:0] (\n                                  ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module user_id_programming #(
    parameter USER_PROJECT_ID = 32'h0
) (
`ifdef USE_POWER_PINS
    inout VDD,
    inout VSS,
`endif
    output [31:0] mask_rev
);
    wire [31:0] mask_rev;
    wire [31:0] user_proj_id_high;
    wire [31:0] user_proj_id_low;




    gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one [31:0] (
`ifdef USE_POWER_PINS
            .VDD(VDD),
            .VSS(VSS),
`endif
            .Z(user_proj_id_high)
    );

    gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero [31:0] (
`ifdef USE_POWER_PINS
            .VDD(VDD),
            .VSS(VSS),
`endif
            .ZN(user_proj_id_low)
    );

    genvar i;
    generate
	for (i = 0; i < 32; i = i+1) begin
	    assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
			user_proj_id_high[i] : user_proj_id_low[i];
	end
    endgenerate

endmodule
module user_id_programming #(
    parameter USER_PROJECT_ID = 32'h0
) (
`ifdef USE_POWER_PINS
    inout VDD,
    inout VSS,
`endif
    output [31:0] mask_rev
);

    wire [31:0] mask_rev;
    wire [31:0] user_proj_id_high;
    wire [31:0] user_proj_id_low;




    gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one [31:0] (
`ifdef USE_POWER_PINS
            .VDD(VDD),
            .VSS(VSS),
`endif
            .Z(user_proj_id_high)
    );

    gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero [31:0] (
`ifdef USE_POWER_PINS
            .VDD(VDD),
            .VSS(VSS),
`endif
            .ZN(user_proj_id_low)
    );

    genvar i;
    generate
	for (i = 0; i < 32; i = i+1) begin
	    assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
			user_proj_id_high[i] : user_proj_id_low[i];
	end
    endgenerate

endmodule