data/full_repos/permissive/40580763/internal_ram.v
1: b"%Error: data/full_repos/permissive/40580763/internal_ram.v:11: Duplicate declaration of signal: 'dout'\n                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [data_width-1:0] dout;  \n                      ^~~~\n        data/full_repos/permissive/40580763/internal_ram.v:6: ... Location of original declaration\n      output [data_width-1:0] dout\n                              ^~~~\n%Error: Exiting due to 1 error(s)\n"
module internal_ram ( 	input clk, 
						input [addr_width-1:0] addr, 
						input write_en, 
						input [data_width-1:0] din, 
						output [data_width-1:0] dout
);

	parameter addr_width = 9;
	parameter data_width = 32;
	reg [data_width-1:0] dout;
	reg [data_width-1:0] mem [(1<<addr_width)-1:0];
	always @(posedge clk)
	begin
	    if (write_en)
	      mem[(addr)] <= din;
		dout = mem[addr];
	end
endmodule
module internal_ram ( 	input clk, 
						input [addr_width-1:0] addr, 
						input write_en, 
						input [data_width-1:0] din, 
						output [data_width-1:0] dout
);


	parameter addr_width = 9;
	parameter data_width = 32;
	reg [data_width-1:0] dout;
	reg [data_width-1:0] mem [(1<<addr_width)-1:0];
	always @(posedge clk)
	begin
	    if (write_en)
	      mem[(addr)] <= din;
		dout = mem[addr];
	end
endmodule