data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Error: data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("lab4_1.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/419538859/lab4/lab4_1/sim/lab4_1_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	lab4_1_tb;

reg 	clk,reset;
reg		[1:0]sel;
wire	[7:0]row, column_green, column_red;
wire 	clk_shift, clk_scan;
wire	[7:0]idx, idx_cnt;
wire	[7:0]column_out;

lab4_1 lab4_1(
						.clk(clk),
						.reset(reset),
						.row(row),
						.sel(sel),
						.column_green(column_green),
						.column_red(column_red)			);


parameter	clkper = 5;
parameter	exp = 1;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 sel	= 2'b01;
 #1000;	
 $finish;		
end

initial begin
	$dumpfile("lab4_1.vcd");
	$dumpvars;
end

endmodule
module 	lab4_1_tb;


reg 	clk,reset;
reg		[1:0]sel;
wire	[7:0]row, column_green, column_red;
wire 	clk_shift, clk_scan;
wire	[7:0]idx, idx_cnt;
wire	[7:0]column_out;

lab4_1 lab4_1(
						.clk(clk),
						.reset(reset),
						.row(row),
						.sel(sel),
						.column_green(column_green),
						.column_red(column_red)			);


parameter	clkper = 5;
parameter	exp = 1;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 sel	= 2'b01;
 #1000;	
 $finish;		
end

initial begin
	$dumpfile("lab4_1.vcd");
	$dumpvars;
end

endmodule