data/full_repos/permissive/458737381/src/verilog-parser/tests/simple_task.v
data/verilator_xmls/85279cc9-31a5-4457-8e67-7020dce6c57a.xml
module simple_task();

task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
  temp_out = (9/5) *( temp_in + 32);
end
endtask

endmodule
module simple_task();


task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
  temp_out = (9/5) *( temp_in + 32);
end
endtask

endmodule