data/full_repos/permissive/411831376/Futaba.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/411831376/Futaba.v:63: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'Futaba\'\nmodule Futaba( output reg TCLKQ,\n       ^~~~~~\n                                                                   : ... Top module \'DTT\'\nmodule DTT #(parameter N = 1) (output reg [N-1:0]Q, input [N-1:0]D, input C, aR);\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/411831376/Futaba.v:71: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'E\' generates 1 bits.\n                                                                : ... In instance Futaba.DC\n assign Y = E << X;\n              ^~\n%Error: data/full_repos/permissive/411831376/Futaba.v:30: Cannot find file containing module: \'CD\'\n CD CD( .a(CDa),\n ^~\n        ... Looked in:\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD.v\n             data/full_repos/permissive/411831376,data/full_repos/permissive/411831376/CD.sv\n             CD\n             CD.v\n             CD.sv\n             obj_dir/CD\n             obj_dir/CD.v\n             obj_dir/CD.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Futaba(	output reg TCLKQ,
				output SIQ,
				output reg TLATQ = 0,
				output reg TBKQ = 0,
				output DemandY,
					input [80:0]Data,
					input [6:0]BK,
							input C);

	wire [1:0]CDa;

	wire L_Y;
	wire SH_Y;
	wire INC_Y;
	wire INV_TCLKY;
	wire INV_TLATY;
	wire R_TBKY;
	wire S_TBKY;
	wire INV_TWordY;


	wire [31:0]DCY;



	reg [6:0]CTQ;
	reg [95:0]REGQ;
	assign SIQ = REGQ[95];

	CD CD(	.a(CDa),

			.L_Y(L_Y),
			.SH_Y(SH_Y),
			.INC_Y(INC_Y),
			.INV_TCLKY(INV_TCLKY),
			.INV_TLATY(INV_TLATY),
			.R_TBKY(R_TBKY),
			.S_TBKY(S_TBKY),
			.INV_TWordY(INV_TWordY),
			.DemandY(DemandY),

				.CTEq95(CTQ == 7'd95),
				.CTEq32(CTQ == BK),
					.C(C), .aR(1'd0));

	
	DC #(5) DC(.Y(DCY), .X(Data[80:76]), .E(1'd1));
	
	initial TCLKQ <= 1'd1;
	always @(posedge C)
	begin
		if(INV_TCLKY) TCLKQ <= !TCLKQ;
		if(INV_TLATY) TLATQ <= !TLATQ;
		if(R_TBKY) TBKQ  <= 0; else if(S_TBKY) TBKQ  <= 1'd1;
		if(INC_Y & (CTQ == 7'd95)) CTQ <= 0;
			else if(INC_Y) CTQ <= CTQ + 1'd1;
		if(L_Y) REGQ <={DCY[00], DCY[01], DCY[02], DCY[03], DCY[04], DCY[05], DCY[06], DCY[07], DCY[08], DCY[09],
						DCY[10], DCY[11], DCY[12], DCY[13], DCY[14], DCY[15], DCY[16], DCY[17], DCY[18], DCY[19], Data[75:0]};
			else if(SH_Y) REGQ <= {REGQ[94:0], 1'dx};
	end
endmodule
module Futaba(	output reg TCLKQ,
				output SIQ,
				output reg TLATQ = 0,
				output reg TBKQ = 0,
				output DemandY,
					input [80:0]Data,
					input [6:0]BK,
							input C);


	wire [1:0]CDa;

	wire L_Y;
	wire SH_Y;
	wire INC_Y;
	wire INV_TCLKY;
	wire INV_TLATY;
	wire R_TBKY;
	wire S_TBKY;
	wire INV_TWordY;


	wire [31:0]DCY;



	reg [6:0]CTQ;
	reg [95:0]REGQ;
	assign SIQ = REGQ[95];

	CD CD(	.a(CDa),

			.L_Y(L_Y),
			.SH_Y(SH_Y),
			.INC_Y(INC_Y),
			.INV_TCLKY(INV_TCLKY),
			.INV_TLATY(INV_TLATY),
			.R_TBKY(R_TBKY),
			.S_TBKY(S_TBKY),
			.INV_TWordY(INV_TWordY),
			.DemandY(DemandY),

				.CTEq95(CTQ == 7'd95),
				.CTEq32(CTQ == BK),
					.C(C), .aR(1'd0));

	
	DC #(5) DC(.Y(DCY), .X(Data[80:76]), .E(1'd1));
	
	initial TCLKQ <= 1'd1;
	always @(posedge C)
	begin
		if(INV_TCLKY) TCLKQ <= !TCLKQ;
		if(INV_TLATY) TLATQ <= !TLATQ;
		if(R_TBKY) TBKQ  <= 0; else if(S_TBKY) TBKQ  <= 1'd1;
		if(INC_Y & (CTQ == 7'd95)) CTQ <= 0;
			else if(INC_Y) CTQ <= CTQ + 1'd1;
		if(L_Y) REGQ <={DCY[00], DCY[01], DCY[02], DCY[03], DCY[04], DCY[05], DCY[06], DCY[07], DCY[08], DCY[09],
						DCY[10], DCY[11], DCY[12], DCY[13], DCY[14], DCY[15], DCY[16], DCY[17], DCY[18], DCY[19], Data[75:0]};
			else if(SH_Y) REGQ <= {REGQ[94:0], 1'dx};
	end
endmodule