data/full_repos/permissive/477770962/mux41.v
data/verilator_xmls/931d182f-fd7c-498e-ac6c-aec13d77b9f5.xml
module mux41(a, b, c, d, s, y);
	input [3:0] a, b, c, d;
	input [1:0] s;
	output reg [3:0] y;  	

always@(*) begin
	assign y = s[1] ? (s[0] ? d : c) : (s[0] ? b : a);

end
	
endmodule
module mux41(a, b, c, d, s, y);

	input [3:0] a, b, c, d;
	input [1:0] s;
	output reg [3:0] y;  	

always@(*) begin
	assign y = s[1] ? (s[0] ? d : c) : (s[0] ? b : a);

end
	
endmodule