data/full_repos/permissive/452016975/src/data_memory.v
1: b'%Error: data/full_repos/permissive/452016975/src/data_memory.v:22: Unsupported or unknown PLI call: $writememb\n  $writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", _memory);\n  ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_memory(read_data,address,write_data,mem_write,mem_read);

output reg [31:0] read_data;
input [31:0] address; 
input [31:0] write_data;
input mem_read,mem_write;


reg [31:0] _memory [255:0]; 

initial begin
	$readmemb("C:/Users/okant/Desktop/16-bit-MiniMIPS-CPU/simulation/modelsim/mem_memory.txt", _memory);
end

always @(*) begin
	if (mem_read) begin
		read_data <= _memory[address];
	end
	
	if (mem_write) begin
		_memory[address] <= write_data[31:0];
		$writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", _memory);
	end
end

endmodule
module data_memory(read_data,address,write_data,mem_write,mem_read);


output reg [31:0] read_data;
input [31:0] address; 
input [31:0] write_data;
input mem_read,mem_write;


reg [31:0] _memory [255:0]; 

initial begin
	$readmemb("C:/Users/okant/Desktop/16-bit-MiniMIPS-CPU/simulation/modelsim/mem_memory.txt", _memory);
end

always @(*) begin
	if (mem_read) begin
		read_data <= _memory[address];
	end
	
	if (mem_write) begin
		_memory[address] <= write_data[31:0];
		$writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", _memory);
	end
end

endmodule