data/full_repos/permissive/487478597/riscv_mem.v
1: b'%Error: data/full_repos/permissive/487478597/riscv_mem.v:66: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(status == 2\'b01) begin\n                    ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:71: syntax error, unexpected \'{\'\n                    {cache_reg[index][{addr[3:2], 2\'h3}], cache_reg[index][{addr[3:2], 2\'h2}], \n                    ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:74: syntax error, unexpected \'[\', expecting IDENTIFIER\n                else cache_reg[index][addr[3:0]] = Wdata;\n                              ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:79: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    Rdata = {cache_reg[index][{addr[3:2], 2\'h3}], \n                          ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};\n                           ^\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:95: syntax error, unexpected <=, expecting IDENTIFIER\n           mem_Wdata <= {cache_reg[index][{cnt, 2\'h3}], \n                     ^~\n%Error: data/full_repos/permissive/487478597/riscv_mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n            mem_Wdata <= 0;\n                      ^~\n%Warning-STMTDLY: data/full_repos/permissive/487478597/riscv_mem.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #1 request_num = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module cache #(parameter cache_sz = 64, block_sz = 128, addr_sz = 10, data_sz = 32) (
    input isWrite,
    input [addr_sz-1:0] addr,
    input [data_sz-1:0] Wdata,
    input [data_sz-1:0] mem_Rdata,
    input Done,
    output reg [data_sz-1:0] Rdata,
    output reg hit,
    output reg mem_Write,
    output reg [addr_sz-1:0] mem_addr,
    output reg [data_sz-1:0] mem_Wdata
);
    reg [1:0] status, next;
    reg [7:0] cache_reg [0:3] [15:0];
    reg [5:0] mark [0:3];
    reg [3:0] tag;
    reg [1:0] index;
    reg [3:0] word;
    reg [1:0] cnt;


    integer i, j;
    initial begin 
        {next, cnt, mem_Write} = 0;
        hit = 1;
        for (i=0;i<4;i=i+1) begin 
            for (j=0;j<16;j=j+1) begin cache_reg[i][j] = 0; end
            mark[i] = 0; 
        end
    end
    

    always @(*) begin hit = (mark[index][5] & (tag == mark[index][3:0])); end
    always @(isWrite, addr, Wdata) begin 
        next = 2'b01; 
        tag = addr[9:6];
        index = addr[5:4];
        word = addr[5:2];
    end


    always @(posedge Done) begin
        case (status)
            2'b10: begin
                mark[index][4] = 0;
                next = (cnt == 2'b11)? 2'b11:2'b10;
                cnt = (cnt == 2'b11)? 0 : cnt + 1;
            end
            2'b11: begin
                mark[index][3:0] = tag;
                mark[index][5] = 1;
                {cache_reg[index][{cnt, 2'h3}], 
                    cache_reg[index][{cnt, 2'h2}], 
                    cache_reg[index][{cnt, 2'h1}], 
                    cache_reg[index][{cnt, 2'h0}]
                } = mem_Rdata; 
                next = (cnt == 2'b11)? 2'b01:2'b11; 
                cnt = (cnt == 2'b11)? 0 : cnt + 1;
            end
        endcase
    end


    always @(status == 2'b01) begin
        if (hit) begin
            next = 2'b0;
            if (isWrite) begin
                if (addr[1:0] == 0) begin 
                    {cache_reg[index][{addr[3:2], 2'h3}], cache_reg[index][{addr[3:2], 2'h2}], 
                        cache_reg[index][{addr[3:2], 2'h1}], cache_reg[index][{addr[3:2], 2'h0}]} = Wdata;
                end
                else cache_reg[index][addr[3:0]] = Wdata;
                mark[index][4] = 1;
            end
            else begin 
                if (addr[1:0] == 0) begin 
                    Rdata = {cache_reg[index][{addr[3:2], 2'h3}], 
                            cache_reg[index][{addr[3:2], 2'h2}], 
                            cache_reg[index][{addr[3:2], 2'h1}], 
                            cache_reg[index][{addr[3:2], 2'h0}]}; 
                end
                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};
            end
        end
        else begin next = (mark[index][5:4] == 2'b11)? 2'b10:2'b11; end
    end



    always @(*) begin 
        status = next; 
        if (next == 2'b10) begin
           mem_Wdata <= {cache_reg[index][{cnt, 2'h3}], 
                            cache_reg[index][{cnt, 2'h2}], 
                            cache_reg[index][{cnt, 2'h1}], 
                            cache_reg[index][{cnt, 2'h0}]}; 
           mem_Write <= 1;
           mem_addr <= {mark[index][3:0], index, cnt, 2'b00};
        end
        else begin
            mem_Wdata <= 0;
            mem_Write <= 0;
            mem_addr <= {tag, index, cnt, 2'b00};
        end
    end
endmodule
module cache #(parameter cache_sz = 64, block_sz = 128, addr_sz = 10, data_sz = 32) (
    input isWrite,
    input [addr_sz-1:0] addr,
    input [data_sz-1:0] Wdata,
    input [data_sz-1:0] mem_Rdata,
    input Done,
    output reg [data_sz-1:0] Rdata,
    output reg hit,
    output reg mem_Write,
    output reg [addr_sz-1:0] mem_addr,
    output reg [data_sz-1:0] mem_Wdata
);

    reg [1:0] status, next;
    reg [7:0] cache_reg [0:3] [15:0];
    reg [5:0] mark [0:3];
    reg [3:0] tag;
    reg [1:0] index;
    reg [3:0] word;
    reg [1:0] cnt;


    integer i, j;
    initial begin 
        {next, cnt, mem_Write} = 0;
        hit = 1;
        for (i=0;i<4;i=i+1) begin 
            for (j=0;j<16;j=j+1) begin cache_reg[i][j] = 0; end
            mark[i] = 0; 
        end
    end
    

    always @(*) begin hit = (mark[index][5] & (tag == mark[index][3:0])); end
    always @(isWrite, addr, Wdata) begin 
        next = 2'b01; 
        tag = addr[9:6];
        index = addr[5:4];
        word = addr[5:2];
    end


    always @(posedge Done) begin
        case (status)
            2'b10: begin
                mark[index][4] = 0;
                next = (cnt == 2'b11)? 2'b11:2'b10;
                cnt = (cnt == 2'b11)? 0 : cnt + 1;
            end
            2'b11: begin
                mark[index][3:0] = tag;
                mark[index][5] = 1;
                {cache_reg[index][{cnt, 2'h3}], 
                    cache_reg[index][{cnt, 2'h2}], 
                    cache_reg[index][{cnt, 2'h1}], 
                    cache_reg[index][{cnt, 2'h0}]
                } = mem_Rdata; 
                next = (cnt == 2'b11)? 2'b01:2'b11; 
                cnt = (cnt == 2'b11)? 0 : cnt + 1;
            end
        endcase
    end


    always @(status == 2'b01) begin
        if (hit) begin
            next = 2'b0;
            if (isWrite) begin
                if (addr[1:0] == 0) begin 
                    {cache_reg[index][{addr[3:2], 2'h3}], cache_reg[index][{addr[3:2], 2'h2}], 
                        cache_reg[index][{addr[3:2], 2'h1}], cache_reg[index][{addr[3:2], 2'h0}]} = Wdata;
                end
                else cache_reg[index][addr[3:0]] = Wdata;
                mark[index][4] = 1;
            end
            else begin 
                if (addr[1:0] == 0) begin 
                    Rdata = {cache_reg[index][{addr[3:2], 2'h3}], 
                            cache_reg[index][{addr[3:2], 2'h2}], 
                            cache_reg[index][{addr[3:2], 2'h1}], 
                            cache_reg[index][{addr[3:2], 2'h0}]}; 
                end
                else Rdata = {{25{cache_reg[index][addr[3:0]][7]}}, cache_reg[index][addr[3:0]][6:0]};
            end
        end
        else begin next = (mark[index][5:4] == 2'b11)? 2'b10:2'b11; end
    end



    always @(*) begin 
        status = next; 
        if (next == 2'b10) begin
           mem_Wdata <= {cache_reg[index][{cnt, 2'h3}], 
                            cache_reg[index][{cnt, 2'h2}], 
                            cache_reg[index][{cnt, 2'h1}], 
                            cache_reg[index][{cnt, 2'h0}]}; 
           mem_Write <= 1;
           mem_addr <= {mark[index][3:0], index, cnt, 2'b00};
        end
        else begin
            mem_Wdata <= 0;
            mem_Write <= 0;
            mem_addr <= {tag, index, cnt, 2'b00};
        end
    end
endmodule