data/full_repos/permissive/438129974/gameserver/VGA.v
1: b"%Error: data/full_repos/permissive/438129974/gameserver/VGA.v:479: Cannot find file containing module: 'blk_mem_gen_1'\n    blk_mem_gen_1 blk_mem_gen_1_inst(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/438129974/gameserver,data/full_repos/permissive/438129974/blk_mem_gen_1\n             data/full_repos/permissive/438129974/gameserver,data/full_repos/permissive/438129974/blk_mem_gen_1.v\n             data/full_repos/permissive/438129974/gameserver,data/full_repos/permissive/438129974/blk_mem_gen_1.sv\n             blk_mem_gen_1\n             blk_mem_gen_1.v\n             blk_mem_gen_1.sv\n             obj_dir/blk_mem_gen_1\n             obj_dir/blk_mem_gen_1.v\n             obj_dir/blk_mem_gen_1.sv\n%Error: Exiting due to 1 error(s)\n"
module clock_divisor(clk1, clk, rst_n);
	input clk;
	input rst_n;
	output clk1;

	reg [1:0] num;
	wire [1:0] next_num;

	always @(posedge clk) begin
		if(rst_n)
			num <= 2'd0;
		else
			num <= next_num;
	end

	assign next_num = num + 1'b1;
	assign clk1 = num[1];

endmodule
module clock_divisor(clk1, clk, rst_n);

	input clk;
	input rst_n;
	output clk1;

	reg [1:0] num;
	wire [1:0] next_num;

	always @(posedge clk) begin
		if(rst_n)
			num <= 2'd0;
		else
			num <= next_num;
	end

	assign next_num = num + 1'b1;
	assign clk1 = num[1];

endmodule