data/full_repos/permissive/41334298/tests/elementary/t3.v
data/verilator_xmls/f4a12059-10e5-49a9-81bd-b26f7512cbb2.xml
module top (a, b, c, y);
input a, b, c;
output y;


xor (y, a, b, c);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;


xor (y, a, b, c);

endmodule