data/full_repos/permissive/458737381/src/verilog-parser/tests/inc-2.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/inc-2.v:2: Cannot find include file: inc-1.h\n`include "inc-1.h" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/inc-1.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/inc-1.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/inc-1.h.sv\n             inc-1.h\n             inc-1.h.v\n             inc-1.h.sv\n             obj_dir/inc-1.h\n             obj_dir/inc-1.h.v\n             obj_dir/inc-1.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/inc-2.v:6: Define or directive not defined: \'`BUS_WIDTH\'\n    input [`BUS_WIDTH] bus\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/inc-2.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`BUS_WIDTH] bus\n                     ^\n%Error: Exiting due to 3 error(s)\n'
module a_module(
    input [`BUS_WIDTH] bus
);

endmodule
module a_module(
    input [`BUS_WIDTH] bus
);


endmodule