data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/DELTA.v
data/verilator_xmls/bc43b9c4-0dd8-4541-bdb3-88e15beb0bdc.xml
module DELTA#(parameter  WLI = 1, WLF = 15, WL = WLI + WLF)
    (
    input RST, CLK, codeWord,
    output reg [WL-1:0] delta
    );
    reg signed [WL-1:0] deltaP1, deltaUnclipped; 
    wire [WL-1:0] deltaDiv, deltaMult;
    assign deltaDiv = delta >>> 1;
    assign deltaMult = delta <<< 1;
    
    always @(*) begin
        if (codeWord == 'b0)
            deltaUnclipped = deltaDiv;
        else if (codeWord == 'b1) 
            deltaUnclipped = deltaMult;
    end
    always @(*) begin 
        if(deltaUnclipped < `DELTA_MIN)
            deltaP1 = `DELTA_MIN;
        else 
            deltaP1 = deltaUnclipped;
    end

    always@(posedge CLK, posedge RST)begin 
        if(RST==1) delta <= `DELTA_MIN;
        else delta <= deltaP1;
    end

endmodule
module DELTA#(parameter  WLI = 1, WLF = 15, WL = WLI + WLF)
    (
    input RST, CLK, codeWord,
    output reg [WL-1:0] delta
    );

    reg signed [WL-1:0] deltaP1, deltaUnclipped; 
    wire [WL-1:0] deltaDiv, deltaMult;
    assign deltaDiv = delta >>> 1;
    assign deltaMult = delta <<< 1;
    
    always @(*) begin
        if (codeWord == 'b0)
            deltaUnclipped = deltaDiv;
        else if (codeWord == 'b1) 
            deltaUnclipped = deltaMult;
    end
    always @(*) begin 
        if(deltaUnclipped < `DELTA_MIN)
            deltaP1 = `DELTA_MIN;
        else 
            deltaP1 = deltaUnclipped;
    end

    always@(posedge CLK, posedge RST)begin 
        if(RST==1) delta <= `DELTA_MIN;
        else delta <= deltaP1;
    end

endmodule