data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v:50: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 4 bits.\n                                                                                 : ... In instance part2\n   3\'b011: ALUtemp = (Data|Data_b) ? 8\'b00000001 : 8\'b0;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module fulladder(a,b,cin,s,cout);

	input a,b,cin;
	output s,cout;
	
	assign s = cin^a^b;
	assign cout = (a&b)|(cin&a)|(cin&b);
	
endmodule
module fulladder(a,b,cin,s,cout);


	input a,b,cin;
	output s,cout;
	
	assign s = cin^a^b;
	assign cout = (a&b)|(cin&a)|(cin&b);
	
endmodule