data/full_repos/permissive/458113953/lab12_2019A8PS0621H/Main_Module_ALU.v
1: b"%Error: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/Main_Module_ALU.v:32: Cannot find file containing module: 'ALU'\n    ALU a1(A,B,S,Yh,Yl);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/458113953/lab12_2019A8PS0621H,data/full_repos/permissive/458113953/ALU\n             data/full_repos/permissive/458113953/lab12_2019A8PS0621H,data/full_repos/permissive/458113953/ALU.v\n             data/full_repos/permissive/458113953/lab12_2019A8PS0621H,data/full_repos/permissive/458113953/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: data/full_repos/permissive/458113953/lab12_2019A8PS0621H/Main_Module_ALU.v:33: Cannot find file containing module: 'vio_1'\n    vio_1 a2(Clk,Yh,Yl,A,B,S);\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module Main_Module_ALU(
    input Clk,
    output [7:0] LSB
    );
    wire [7:0] A;
    wire[7:0] B;
        wire [2:0] S;
        wire[7:0] Yh;
        wire [7:0]Yl;
    ALU a1(A,B,S,Yh,Yl);
    vio_1 a2(Clk,Yh,Yl,A,B,S);
    assign LSB=Yl;
endmodule
module Main_Module_ALU(
    input Clk,
    output [7:0] LSB
    );

    wire [7:0] A;
    wire[7:0] B;
        wire [2:0] S;
        wire[7:0] Yh;
        wire [7:0]Yl;
    ALU a1(A,B,S,Yh,Yl);
    vio_1 a2(Clk,Yh,Yl,A,B,S);
    assign LSB=Yl;
endmodule