data/full_repos/permissive/497530416/pipe/ADD_SUB/add_sub_64bit.v
1: b"%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_sub_64bit.v:32: Cannot find file containing module: 'add_1bit'\n    add_1bit A11(a[j], b_xor_m[j], carry[j], sum[j], carry[j+1]);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497530416/pipe/ADD_SUB,data/full_repos/permissive/497530416/add_1bit\n             data/full_repos/permissive/497530416/pipe/ADD_SUB,data/full_repos/permissive/497530416/add_1bit.v\n             data/full_repos/permissive/497530416/pipe/ADD_SUB,data/full_repos/permissive/497530416/add_1bit.sv\n             add_1bit\n             add_1bit.v\n             add_1bit.sv\n             obj_dir/add_1bit\n             obj_dir/add_1bit.v\n             obj_dir/add_1bit.sv\n%Error: Exiting due to 1 error(s)\n"
module add_sub_64bit(a,b,sum,m, OF);

input signed [63:0] a;
input signed [63:0] b;
input m;
output signed [63:0] sum;
output OF;



wire [64:0] carry;


assign carry[0] = m;

wire [63:0] b_xor_m;


genvar i;



generate for(i = 0; i < 64; i = i + 1)
begin
    xor X11(b_xor_m[i], b[i], m);
end
endgenerate

genvar j;
generate for(j = 0; j < 64; j = j + 1)
begin
    add_1bit A11(a[j], b_xor_m[j], carry[j], sum[j], carry[j+1]);
end
endgenerate



 
xor X2(OF, carry[64], carry[63]);

endmodule
module add_sub_64bit(a,b,sum,m, OF);


input signed [63:0] a;
input signed [63:0] b;
input m;
output signed [63:0] sum;
output OF;



wire [64:0] carry;


assign carry[0] = m;

wire [63:0] b_xor_m;


genvar i;



generate for(i = 0; i < 64; i = i + 1)
begin
    xor X11(b_xor_m[i], b[i], m);
end
endgenerate

genvar j;
generate for(j = 0; j < 64; j = j + 1)
begin
    add_1bit A11(a[j], b_xor_m[j], carry[j], sum[j], carry[j+1]);
end
endgenerate



 
xor X2(OF, carry[64], carry[63]);

endmodule