data/full_repos/permissive/488093047/Verilog Codes/TB_CPU.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_CPU.v\n%Error: Exiting due to 3 error(s)\n'
module TB_CPU();
reg [31:0]INS,ManIn;
reg [2:0]RSM;
reg WR,reset,clk,LO;
wire OV;
wire [31:0] reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8;

CPU DUT1 (.INS(INS),.ManIn(ManIn),.LO(LO),.WR(WR),.clk(clk),.reset(reset),.OV(OV),.RSM(RSM),
.reg1(reg1),.reg2(reg2),.reg3(reg3),.reg4(reg4),.reg5(reg5),.reg6(reg6),.reg7(reg7),.reg8(reg8));
initial begin

clk = 1'b1;
reset = 1'b1;
WR=1'b0;RSM=3'b000;INS=32'b000;LO=1'b0;
ManIn=32'd0;
#50;

reset = 1'b0;

#50 WR=1'b1;RSM=3'b000;LO=1'b0;ManIn=32'd345;
#50 WR=1'b1;RSM=3'b001;LO=1'b0;ManIn=32'd456;
#50 WR=1'b1;RSM=3'b001;LO=1'b1;ManIn=32'd456;
INS=32'b000000_00000_00001_00010_00000_000000;
#50 INS=32'b000100_00000_00001_00011_00000_000000;
#50 INS=32'b000001_00000_00001_00100_00000_000000;
#50 INS=32'b000010_00000_00001_00101_00000_000000;
#50 INS=32'b000011_00000_00001_00110_00000_000000;








end

always #10 clk = ~clk;
endmodule
module TB_CPU();

reg [31:0]INS,ManIn;
reg [2:0]RSM;
reg WR,reset,clk,LO;
wire OV;
wire [31:0] reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8;

CPU DUT1 (.INS(INS),.ManIn(ManIn),.LO(LO),.WR(WR),.clk(clk),.reset(reset),.OV(OV),.RSM(RSM),
.reg1(reg1),.reg2(reg2),.reg3(reg3),.reg4(reg4),.reg5(reg5),.reg6(reg6),.reg7(reg7),.reg8(reg8));
initial begin

clk = 1'b1;
reset = 1'b1;
WR=1'b0;RSM=3'b000;INS=32'b000;LO=1'b0;
ManIn=32'd0;
#50;

reset = 1'b0;

#50 WR=1'b1;RSM=3'b000;LO=1'b0;ManIn=32'd345;
#50 WR=1'b1;RSM=3'b001;LO=1'b0;ManIn=32'd456;
#50 WR=1'b1;RSM=3'b001;LO=1'b1;ManIn=32'd456;
INS=32'b000000_00000_00001_00010_00000_000000;
#50 INS=32'b000100_00000_00001_00011_00000_000000;
#50 INS=32'b000001_00000_00001_00100_00000_000000;
#50 INS=32'b000010_00000_00001_00101_00000_000000;
#50 INS=32'b000011_00000_00001_00110_00000_000000;








end

always #10 clk = ~clk;
endmodule