data/full_repos/permissive/520452389/source_codes/Execution.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/520452389/source_codes/Execution.v:22: Signal definition not found, creating implicitly: \'zero\'\n                                                                                   : ... Suggested alternative: \'zero_s3\'\n        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);\n                                                                                                              ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:18: Cannot find file containing module: \'ksa_add\'\nksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.v\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.sv\n             ksa_add\n             ksa_add.v\n             ksa_add.sv\n             obj_dir/ksa_add\n             obj_dir/ksa_add.v\n             obj_dir/ksa_add.sv\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:20: Cannot find file containing module: \'ALU\'\nALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);\n^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module dff3 (input clk,input [31:0]ALU_result,input [31:0]read_data2_s2,input Branch_s2, input MemWrite_s2,input MemtoReg_s2,
        input MemRead_s2,output reg [31:0]ALU_result_s3,output reg [31:0]read_data2_s3,output reg  MemWrite_s3,
        output reg MemtoReg_s3,output reg MemRead_s3,input RegWrite_s2,output reg RegWrite_s3,output reg Branch_s3,
        input [4:0] write_reg,output reg [4:0] write_reg_s3,input [31:0] pc_out1_ss,output reg [31:0] pc_out1_s3,input zero,output reg zero_s3);

always @(posedge clk) begin 
     ALU_result_s3<=ALU_result;
     zero_s3<=zero;
     read_data2_s3<=read_data2_s2;
     pc_out1_s3<=pc_out1_ss;
     MemWrite_s3<=MemWrite_s2;
     MemtoReg_s3<=MemtoReg_s2;
     MemRead_s3<=MemRead_s2;
     RegWrite_s3<=RegWrite_s2;
     Branch_s3<=Branch_s2;
     write_reg_s3<=write_reg;

end
endmodule
module dff3 (input clk,input [31:0]ALU_result,input [31:0]read_data2_s2,input Branch_s2, input MemWrite_s2,input MemtoReg_s2,
        input MemRead_s2,output reg [31:0]ALU_result_s3,output reg [31:0]read_data2_s3,output reg  MemWrite_s3,
        output reg MemtoReg_s3,output reg MemRead_s3,input RegWrite_s2,output reg RegWrite_s3,output reg Branch_s3,
        input [4:0] write_reg,output reg [4:0] write_reg_s3,input [31:0] pc_out1_ss,output reg [31:0] pc_out1_s3,input zero,output reg zero_s3);


always @(posedge clk) begin 
     ALU_result_s3<=ALU_result;
     zero_s3<=zero;
     read_data2_s3<=read_data2_s2;
     pc_out1_s3<=pc_out1_ss;
     MemWrite_s3<=MemWrite_s2;
     MemtoReg_s3<=MemtoReg_s2;
     MemRead_s3<=MemRead_s2;
     RegWrite_s3<=RegWrite_s2;
     Branch_s3<=Branch_s2;
     write_reg_s3<=write_reg;

end
endmodule