data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v
1: b'%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v:1: Cannot find include file: div_freq_100hz.v\n`include "div_freq_100hz.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/div_freq_100hz.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/div_freq_100hz.v.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/div_freq_100hz.v.sv\n             div_freq_100hz.v\n             div_freq_100hz.v.v\n             div_freq_100hz.v.sv\n             obj_dir/div_freq_100hz.v\n             obj_dir/div_freq_100hz.v.v\n             obj_dir/div_freq_100hz.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    always #5 CLK_IN = ~CLK_IN;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("div_freq_100hz_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, div_freq_100hz_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/div_freq_100hz_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10000 $finish();\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module div_freq_100hz_tb();

    reg CLK_IN;
    wire CLK_OUT;

    div_freq_100hz dut(CLK_IN, CLK_OUT);

    initial begin

        CLK_IN = 0;

    end

    always #5 CLK_IN = ~CLK_IN;


    initial begin
        $dumpfile("div_freq_100hz_tb.vcd");
        $dumpvars(0, div_freq_100hz_tb);
        #10000 $finish();
    end



endmodule
module div_freq_100hz_tb();


    reg CLK_IN;
    wire CLK_OUT;

    div_freq_100hz dut(CLK_IN, CLK_OUT);

    initial begin

        CLK_IN = 0;

    end

    always #5 CLK_IN = ~CLK_IN;


    initial begin
        $dumpfile("div_freq_100hz_tb.vcd");
        $dumpvars(0, div_freq_100hz_tb);
        #10000 $finish();
    end



endmodule