data/full_repos/permissive/43339463/memory.v
1: b'%Error: data/full_repos/permissive/43339463/memory.v:34: Unsupported or unknown PLI call: $monitor\n  $monitor("%t: rw = %b, addr = %x, wline = %x, rline = %x", $time, rw, addr, wline, rline);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43339463/memory.v:64: Unsupported: Ignoring delay on this delayed statement.\n always #10 begin\n        ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_test;
	reg clk;
	reg [1:0] rw;
	reg [15:0] addr;
	wire line;
	reg [31:0] wline;
	wire [47:0] rline;
	
	memory memory(clk, wline, rline, addr, rw);

	initial begin
		$monitor("%t: rw = %b, addr = %x, wline = %x, rline = %x", $time, rw, addr, wline, rline);
		
		clk <= 0;
		#10
		rw <= 2'b11;
		addr <= 0;
		wline <= 48'h123456789ABC;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b10;
		addr <= 1;
		wline <= 48'hDEF012345678;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b11;
		addr <= 3;
		wline <= 48'h9ABCDEF12345;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b00;
		addr <= 2;
		#10 $finish;
	end
	
	always #10 begin
		clk <= ~clk;
	end
endmodule
module memory_test;

	reg clk;
	reg [1:0] rw;
	reg [15:0] addr;
	wire line;
	reg [31:0] wline;
	wire [47:0] rline;
	
	memory memory(clk, wline, rline, addr, rw);

	initial begin
		$monitor("%t: rw = %b, addr = %x, wline = %x, rline = %x", $time, rw, addr, wline, rline);
		
		clk <= 0;
		#10
		rw <= 2'b11;
		addr <= 0;
		wline <= 48'h123456789ABC;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b10;
		addr <= 1;
		wline <= 48'hDEF012345678;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b11;
		addr <= 3;
		wline <= 48'h9ABCDEF12345;
		#10
		rw <= 2'b00;
		addr <= 0;
		#10
		rw <= 2'b00;
		addr <= 2;
		#10 $finish;
	end
	
	always #10 begin
		clk <= ~clk;
	end
endmodule