data/full_repos/permissive/423270459/verilog/rtl/nco.v
data/verilator_xmls/2fe4aac3-f7a1-4d1a-a629-08455e8230dc.xml
module nco_ctrl (

    input              clk,
    input              reset_n,
    input              t_angle_req,
    output             t_angle_ack,
    output             i_nco_req,
    input              i_nco_ack,
    output             en0,
    output             en1,
    output             en2,
    output             en3,
    output             en4,
    output             en5,
    output             en6,
    output             en7,
    output             en8
);

wire             req0, ack0, ack0_0, req0_0;
wire             req1, ack1, ack1_0, req1_0;
wire             req2, ack2, ack2_0, req2_0;
wire             req3, ack3, ack3_0, req3_0;
wire             req4, ack4, ack4_0, req4_0;
wire             req5, ack5, ack5_0, req5_0;
wire             req6, ack6, ack6_0, req6_0;
wire             req7, ack7, ack7_0, req7_0;
wire             req8, ack8, ack8_0, req8_0;
wire             req9, ack9, ack9_0, req9_0;

assign req0 = t_angle_req;
assign t_angle_ack = ack0;


wire ack0m;
reg req0m;
assign en0 = req0 & ack0;
assign ack0 = ~req0m | ack0m;
always @(posedge clk or negedge reset_n) if (~reset_n) req0m <= 1'b0; else req0m <= ~ack0 | req0;





assign req0_0 = req0m;

assign ack0m = ack0_0;




wire ack1m;
reg req1m;
assign en1 = req1 & ack1;
assign ack1 = ~req1m | ack1m;
always @(posedge clk or negedge reset_n) if (~reset_n) req1m <= 1'b0; else req1m <= ~ack1 | req1;





assign req1_0 = req1m;

assign ack1m = ack1_0;




wire ack2m;
reg req2m;
assign en2 = req2 & ack2;
assign ack2 = ~req2m | ack2m;
always @(posedge clk or negedge reset_n) if (~reset_n) req2m <= 1'b0; else req2m <= ~ack2 | req2;





assign req2_0 = req2m;

assign ack2m = ack2_0;




wire ack3m;
reg req3m;
assign en3 = req3 & ack3;
assign ack3 = ~req3m | ack3m;
always @(posedge clk or negedge reset_n) if (~reset_n) req3m <= 1'b0; else req3m <= ~ack3 | req3;





assign req3_0 = req3m;

assign ack3m = ack3_0;




wire ack4m;
reg req4m;
assign en4 = req4 & ack4;
assign ack4 = ~req4m | ack4m;
always @(posedge clk or negedge reset_n) if (~reset_n) req4m <= 1'b0; else req4m <= ~ack4 | req4;





assign req4_0 = req4m;

assign ack4m = ack4_0;




wire ack5m;
reg req5m;
assign en5 = req5 & ack5;
assign ack5 = ~req5m | ack5m;
always @(posedge clk or negedge reset_n) if (~reset_n) req5m <= 1'b0; else req5m <= ~ack5 | req5;





assign req5_0 = req5m;

assign ack5m = ack5_0;




wire ack6m;
reg req6m;
assign en6 = req6 & ack6;
assign ack6 = ~req6m | ack6m;
always @(posedge clk or negedge reset_n) if (~reset_n) req6m <= 1'b0; else req6m <= ~ack6 | req6;





assign req6_0 = req6m;

assign ack6m = ack6_0;




wire ack7m;
reg req7m;
assign en7 = req7 & ack7;
assign ack7 = ~req7m | ack7m;
always @(posedge clk or negedge reset_n) if (~reset_n) req7m <= 1'b0; else req7m <= ~ack7 | req7;





assign req7_0 = req7m;

assign ack7m = ack7_0;




wire ack8m;
reg req8m;
assign en8 = req8 & ack8;
assign ack8 = ~req8m | ack8m;
always @(posedge clk or negedge reset_n) if (~reset_n) req8m <= 1'b0; else req8m <= ~ack8 | req8;





assign req8_0 = req8m;

assign ack8m = ack8_0;




wire ack9m, req9m;
assign req9m = req9;
assign ack9 = ack9m;





assign req9_0 = req9m;

assign ack9m = ack9_0;



assign req1 = req0_0;
assign ack0_0 = ack1;

assign req2 = req1_0;
assign ack1_0 = ack2;

assign req3 = req2_0;
assign ack2_0 = ack3;

assign req4 = req3_0;
assign ack3_0 = ack4;

assign req5 = req4_0;
assign ack4_0 = ack5;

assign req6 = req5_0;
assign ack5_0 = ack6;

assign req7 = req6_0;
assign ack6_0 = ack7;

assign req8 = req7_0;
assign ack7_0 = ack8;

assign req9 = req8_0;
assign ack8_0 = ack9;

assign i_nco_req = req9_0;
assign ack9_0 = i_nco_ack;
endmodule
module nco_ctrl (

    input              clk,
    input              reset_n,
    input              t_angle_req,
    output             t_angle_ack,
    output             i_nco_req,
    input              i_nco_ack,
    output             en0,
    output             en1,
    output             en2,
    output             en3,
    output             en4,
    output             en5,
    output             en6,
    output             en7,
    output             en8
);


wire             req0, ack0, ack0_0, req0_0;
wire             req1, ack1, ack1_0, req1_0;
wire             req2, ack2, ack2_0, req2_0;
wire             req3, ack3, ack3_0, req3_0;
wire             req4, ack4, ack4_0, req4_0;
wire             req5, ack5, ack5_0, req5_0;
wire             req6, ack6, ack6_0, req6_0;
wire             req7, ack7, ack7_0, req7_0;
wire             req8, ack8, ack8_0, req8_0;
wire             req9, ack9, ack9_0, req9_0;

assign req0 = t_angle_req;
assign t_angle_ack = ack0;


wire ack0m;
reg req0m;
assign en0 = req0 & ack0;
assign ack0 = ~req0m | ack0m;
always @(posedge clk or negedge reset_n) if (~reset_n) req0m <= 1'b0; else req0m <= ~ack0 | req0;





assign req0_0 = req0m;

assign ack0m = ack0_0;




wire ack1m;
reg req1m;
assign en1 = req1 & ack1;
assign ack1 = ~req1m | ack1m;
always @(posedge clk or negedge reset_n) if (~reset_n) req1m <= 1'b0; else req1m <= ~ack1 | req1;





assign req1_0 = req1m;

assign ack1m = ack1_0;




wire ack2m;
reg req2m;
assign en2 = req2 & ack2;
assign ack2 = ~req2m | ack2m;
always @(posedge clk or negedge reset_n) if (~reset_n) req2m <= 1'b0; else req2m <= ~ack2 | req2;





assign req2_0 = req2m;

assign ack2m = ack2_0;




wire ack3m;
reg req3m;
assign en3 = req3 & ack3;
assign ack3 = ~req3m | ack3m;
always @(posedge clk or negedge reset_n) if (~reset_n) req3m <= 1'b0; else req3m <= ~ack3 | req3;





assign req3_0 = req3m;

assign ack3m = ack3_0;




wire ack4m;
reg req4m;
assign en4 = req4 & ack4;
assign ack4 = ~req4m | ack4m;
always @(posedge clk or negedge reset_n) if (~reset_n) req4m <= 1'b0; else req4m <= ~ack4 | req4;





assign req4_0 = req4m;

assign ack4m = ack4_0;




wire ack5m;
reg req5m;
assign en5 = req5 & ack5;
assign ack5 = ~req5m | ack5m;
always @(posedge clk or negedge reset_n) if (~reset_n) req5m <= 1'b0; else req5m <= ~ack5 | req5;





assign req5_0 = req5m;

assign ack5m = ack5_0;




wire ack6m;
reg req6m;
assign en6 = req6 & ack6;
assign ack6 = ~req6m | ack6m;
always @(posedge clk or negedge reset_n) if (~reset_n) req6m <= 1'b0; else req6m <= ~ack6 | req6;





assign req6_0 = req6m;

assign ack6m = ack6_0;




wire ack7m;
reg req7m;
assign en7 = req7 & ack7;
assign ack7 = ~req7m | ack7m;
always @(posedge clk or negedge reset_n) if (~reset_n) req7m <= 1'b0; else req7m <= ~ack7 | req7;





assign req7_0 = req7m;

assign ack7m = ack7_0;




wire ack8m;
reg req8m;
assign en8 = req8 & ack8;
assign ack8 = ~req8m | ack8m;
always @(posedge clk or negedge reset_n) if (~reset_n) req8m <= 1'b0; else req8m <= ~ack8 | req8;





assign req8_0 = req8m;

assign ack8m = ack8_0;




wire ack9m, req9m;
assign req9m = req9;
assign ack9 = ack9m;





assign req9_0 = req9m;

assign ack9m = ack9_0;



assign req1 = req0_0;
assign ack0_0 = ack1;

assign req2 = req1_0;
assign ack1_0 = ack2;

assign req3 = req2_0;
assign ack2_0 = ack3;

assign req4 = req3_0;
assign ack3_0 = ack4;

assign req5 = req4_0;
assign ack4_0 = ack5;

assign req6 = req5_0;
assign ack5_0 = ack6;

assign req7 = req6_0;
assign ack6_0 = ack7;

assign req8 = req7_0;
assign ack7_0 = ack8;

assign req9 = req8_0;
assign ack8_0 = ack9;

assign i_nco_req = req9_0;
assign ack9_0 = i_nco_ack;
endmodule