data/full_repos/permissive/518304282/iiitb_rtc.v
data/verilator_xmls/9fd4bca6-5cb2-42cd-ab00-83fca15efb93.xml
module iiitb_rtc (
input clkin,rst,
output [3:0]hrm,hrl,minm,minl,secm,secl);
wire [3:0]hrms,hrls,minms,minls,secms,secls;
wire hrclr;
assign hrclr = ((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5) && (hrl==4'd3) && (hrm==4'd2));

  counter #(9) c1(.clk(clkin),.rst(rst),.clr(1'b0),.en(1'b1),.count(secl));
  counter #(5) c2(.clk(clkin),.rst(rst),.clr(1'b0),.en(secl==4'd9),.count(secm));
  counter #(9) c3(.clk(clkin),.rst(rst),.clr(1'b0),.en((secl==4'd9) && (secm==4'd5)),.count(minl));
  counter #(5) c4(.clk(clkin),.rst(rst),.clr(1'b0),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9)),.count(minm));
  counter #(9) c5(.clk(clkin),.rst(rst),.clr(hrclr),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5)),.count(hrl));
  counter #(2) c6(.clk(clkin),.rst(rst),.clr(hrclr),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5) && (hrl==4'd9)),.count(hrm));
endmodule
module iiitb_rtc (
input clkin,rst,
output [3:0]hrm,hrl,minm,minl,secm,secl);

wire [3:0]hrms,hrls,minms,minls,secms,secls;
wire hrclr;
assign hrclr = ((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5) && (hrl==4'd3) && (hrm==4'd2));

  counter #(9) c1(.clk(clkin),.rst(rst),.clr(1'b0),.en(1'b1),.count(secl));
  counter #(5) c2(.clk(clkin),.rst(rst),.clr(1'b0),.en(secl==4'd9),.count(secm));
  counter #(9) c3(.clk(clkin),.rst(rst),.clr(1'b0),.en((secl==4'd9) && (secm==4'd5)),.count(minl));
  counter #(5) c4(.clk(clkin),.rst(rst),.clr(1'b0),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9)),.count(minm));
  counter #(9) c5(.clk(clkin),.rst(rst),.clr(hrclr),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5)),.count(hrl));
  counter #(2) c6(.clk(clkin),.rst(rst),.clr(hrclr),.en((secl==4'd9) && (secm==4'd5) && (minl==4'd9) && (minm==4'd5) && (hrl==4'd9)),.count(hrm));
endmodule