data/full_repos/permissive/428125225/jiance.v
1: b"%Error: data/full_repos/permissive/428125225/jiance.v:8: Duplicate declaration of signal: 'sum'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg   [8:0] sum;\n            ^~~\n        data/full_repos/permissive/428125225/jiance.v:5: ... Location of original declaration\n output   sum\n          ^~~\n%Error: Exiting due to 1 error(s)\n"
module jiance(
 input     clk,
 input  [8:0] sum_out, 
 input    rst,
 output   sum
 );

reg   [8:0] sum;
always@(posedge clk or posedge rst)
begin
	if(rst == 1'b1)
		sum <= 0;
 else   sum  <= sum_out + 'd5;
end
endmodule
module jiance(
 input     clk,
 input  [8:0] sum_out, 
 input    rst,
 output   sum
 );


reg   [8:0] sum;
always@(posedge clk or posedge rst)
begin
	if(rst == 1'b1)
		sum <= 0;
 else   sum  <= sum_out + 'd5;
end
endmodule