data/full_repos/permissive/447976230/fpga/usrp2/control_lib/gray_send.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/gray_send.v:29: Cannot find file containing module: 'bin2gray'\n   bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/bin2gray\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/bin2gray.v\n             data/full_repos/permissive/447976230/fpga/usrp2/control_lib,data/full_repos/permissive/447976230/bin2gray.sv\n             bin2gray\n             bin2gray.v\n             bin2gray.sv\n             obj_dir/bin2gray\n             obj_dir/bin2gray.v\n             obj_dir/bin2gray.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/gray_send.v:40: Cannot find file containing module: 'gray2bin'\n   gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );\n   ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module gray_send
  #(parameter WIDTH = 8)
    (input clk_in, input [WIDTH-1:0] addr_in,
     input clk_out, output reg [WIDTH-1:0] addr_out);

   reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
   wire [WIDTH-1:0] gray, bin;

   bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );

   always @(posedge clk_in)
     gray_clkin <= gray;

   always @(posedge clk_out)
     gray_clkout <= gray_clkin;

   always @(posedge clk_out)
     gray_clkout_d1 <= gray_clkout;
   
   gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );


   always @(posedge clk_out)
     addr_out <= bin;
   
endmodule
module gray_send
  #(parameter WIDTH = 8)
    (input clk_in, input [WIDTH-1:0] addr_in,
     input clk_out, output reg [WIDTH-1:0] addr_out);


   reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
   wire [WIDTH-1:0] gray, bin;

   bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );

   always @(posedge clk_in)
     gray_clkin <= gray;

   always @(posedge clk_out)
     gray_clkout <= gray_clkin;

   always @(posedge clk_out)
     gray_clkout_d1 <= gray_clkout;
   
   gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );


   always @(posedge clk_out)
     addr_out <= bin;
   
endmodule