data/full_repos/permissive/480580678/hardware/src/sram.v
1: b'%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:2: Cannot find include file: system.vh\n`include "system.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480580678/hardware/src,data/full_repos/permissive/480580678/system.vh\n             data/full_repos/permissive/480580678/hardware/src,data/full_repos/permissive/480580678/system.vh.v\n             data/full_repos/permissive/480580678/hardware/src,data/full_repos/permissive/480580678/system.vh.sv\n             system.vh\n             system.vh.v\n             system.vh.sv\n             obj_dir/system.vh\n             obj_dir/system.vh.v\n             obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:13: Define or directive not defined: \'`SRAM_ADDR_W\'\n    input [`SRAM_ADDR_W-3:0] i_addr,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:14: Define or directive not defined: \'`DATA_W\'\n    input [`DATA_W-1:0]      i_wdata,  \n           ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:15: Define or directive not defined: \'`DATA_W\'\n    input [`DATA_W/8-1:0]    i_wstrb,  \n           ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:15: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    input [`DATA_W/8-1:0]    i_wstrb,  \n                  ^\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:16: Define or directive not defined: \'`DATA_W\'\n    output [`DATA_W-1:0]     i_rdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:20: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                    d_valid,\n    ^~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:21: Define or directive not defined: \'`SRAM_ADDR_W\'\n    input [`SRAM_ADDR_W-3:0] d_addr,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:22: Define or directive not defined: \'`DATA_W\'\n    input [`DATA_W-1:0]      d_wdata,\n           ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:23: Define or directive not defined: \'`DATA_W\'\n    input [`DATA_W/8-1:0]    d_wstrb,\n           ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:24: Define or directive not defined: \'`DATA_W\'\n    output [`DATA_W-1:0]     d_rdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:31: Define or directive not defined: \'`SRAM_ADDR_W\'\n       .ADDR_W(`SRAM_ADDR_W-2),\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/src/sram.v:32: Define or directive not defined: \'`DATA_W\'\n       .DATA_W(`DATA_W)\n               ^~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module sram #(
              parameter FILE = "none"
	      )
   (
    input                    clk,
    input                    rst,


    input                    i_valid,
    input [`SRAM_ADDR_W-3:0] i_addr,
    input [`DATA_W-1:0]      i_wdata,
    input [`DATA_W/8-1:0]    i_wstrb,
    output [`DATA_W-1:0]     i_rdata,
    output reg               i_ready,


    input                    d_valid,
    input [`SRAM_ADDR_W-3:0] d_addr,
    input [`DATA_W-1:0]      d_wdata,
    input [`DATA_W/8-1:0]    d_wstrb,
    output [`DATA_W-1:0]     d_rdata,
    output reg               d_ready
    );

   iob_dp_ram_be
     #(
       .FILE(FILE),
       .ADDR_W(`SRAM_ADDR_W-2),
       .DATA_W(`DATA_W)
       )
   main_mem_byte
     (
      .clk   (clk),


      .enA   (d_valid),
      .addrA (d_addr),
      .weA   (d_wstrb),
      .dinA  (d_wdata),
      .doutA (d_rdata),


      .enB   (i_valid),
      .addrB (i_addr),
      .weB   (i_wstrb),
      .dinB  (i_wdata),
      .doutB (i_rdata)
      );


   always @(posedge clk, posedge rst)
     if(rst) begin
	    d_ready <= 1'b0;
	    i_ready <= 1'b0;
     end else begin 
	    d_ready <= d_valid;
	    i_ready <= i_valid;
     end
endmodule
module sram #(
              parameter FILE = "none"
	      )
   (
    input                    clk,
    input                    rst,


    input                    i_valid,
    input [`SRAM_ADDR_W-3:0] i_addr,
    input [`DATA_W-1:0]      i_wdata,
    input [`DATA_W/8-1:0]    i_wstrb,
    output [`DATA_W-1:0]     i_rdata,
    output reg               i_ready,


    input                    d_valid,
    input [`SRAM_ADDR_W-3:0] d_addr,
    input [`DATA_W-1:0]      d_wdata,
    input [`DATA_W/8-1:0]    d_wstrb,
    output [`DATA_W-1:0]     d_rdata,
    output reg               d_ready
    );


   iob_dp_ram_be
     #(
       .FILE(FILE),
       .ADDR_W(`SRAM_ADDR_W-2),
       .DATA_W(`DATA_W)
       )
   main_mem_byte
     (
      .clk   (clk),


      .enA   (d_valid),
      .addrA (d_addr),
      .weA   (d_wstrb),
      .dinA  (d_wdata),
      .doutA (d_rdata),


      .enB   (i_valid),
      .addrB (i_addr),
      .weB   (i_wstrb),
      .dinB  (i_wdata),
      .doutB (i_rdata)
      );


   always @(posedge clk, posedge rst)
     if(rst) begin
	    d_ready <= 1'b0;
	    i_ready <= 1'b0;
     end else begin 
	    d_ready <= d_valid;
	    i_ready <= i_valid;
     end
endmodule