data/full_repos/permissive/450962776/processor/src/Mips.v
1: b"%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:26: Cannot find file containing module: 'Adder_5_bit'\n Adder_5_bit m13(pc_current,5'b00001,adding_pc);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/Adder_5_bit\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/Adder_5_bit.v\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/Adder_5_bit.sv\n             Adder_5_bit\n             Adder_5_bit.v\n             Adder_5_bit.sv\n             obj_dir/Adder_5_bit\n             obj_dir/Adder_5_bit.v\n             obj_dir/Adder_5_bit.sv\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:27: Cannot find file containing module: 'Instruction_Memory'\nInstruction_Memory m0(pc_current,instruction);\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:29: Cannot find file containing module: 'Main_Control'\nMain_Control m1(instruction[15:12],RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:31: Cannot find file containing module: 'Alu_Control'\nAlu_Control m6(ALUop2,ALUop1,ALUop0,instruction[2:0],C2,C1,C0);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:32: Cannot find file containing module: 'm21_3_bit'\nm21_3_bit m2(rt_rd,instruction[8:6],instruction[5:3],RegDst);\n^~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:33: Cannot find file containing module: 'Registers'\nRegisters m3(read_data_1, read_data_2, write_data, instruction[11:9], instruction[8:6],rt_rd,RegWrite,clk);\n^~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:34: Cannot find file containing module: 'Sign_Extend'\nSign_Extend m4(instruction [5:0] ,_32_bit);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:36: Cannot find file containing module: 'm21_32_bit'\nm21_32_bit m5(Alu_choose, read_data_2, _32_bit,ALUSrc);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:38: Cannot find file containing module: 'alu_32_bit'\nalu_32_bit m7(read_data_1,Alu_choose,C0,C1,C2,C1,Alu_result,Co);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:39: Cannot find file containing module: 'or_for_beq'\nor_for_beq m14(Alu_result,or_for_beq);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:42: Cannot find file containing module: 'Data_Memory'\nData_Memory m8(clk,Alu_result, read_data_2, MemWrite,MemRead,read_data);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:43: Cannot find file containing module: 'm21_32_bit'\nm21_32_bit m9(write_data,Alu_result,read_data,MemtoReg);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:47: Cannot find file containing module: 'Adder_5_bit'\nAdder_5_bit m11(_32_bit[4:0],adding_pc,adding_branch);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Mips.v:48: Cannot find file containing module: 'm21_5_bit'\nm21_5_bit m12(branch_result, adding_pc, adding_branch,branch_);\n^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module Mips(input clk);
wire [15:0]instruction;
wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
wire [2:0]rt_rd;
wire [31:0]read_data_1, read_data_2;
wire [31:0]write_data;
wire [31:0] _32_bit;
wire [31:0] Alu_choose;
wire [31:0] Alu_result;
wire C2,C1,C0;
wire Co;
wire [31:0] read_data;
wire branch_1,branch_2,branch_;
wire [4:0]branch_result,adding_branch;
reg [4:0]pc_current;
wire [4:0] adding_pc;
wire or_for_beq,xor_for_beq;
initial begin
  pc_current <= 5'b00000;
 end
 always @(posedge clk)
 begin 
   pc_current <= branch_result;
 end

 Adder_5_bit m13(pc_current,5'b00001,adding_pc);
Instruction_Memory m0(pc_current,instruction);

Main_Control m1(instruction[15:12],RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);

Alu_Control m6(ALUop2,ALUop1,ALUop0,instruction[2:0],C2,C1,C0);
m21_3_bit m2(rt_rd,instruction[8:6],instruction[5:3],RegDst);
Registers m3(read_data_1, read_data_2, write_data, instruction[11:9], instruction[8:6],rt_rd,RegWrite,clk);
Sign_Extend m4(instruction [5:0] ,_32_bit);

m21_32_bit m5(Alu_choose, read_data_2, _32_bit,ALUSrc);

alu_32_bit m7(read_data_1,Alu_choose,C0,C1,C2,C1,Alu_result,Co);
or_for_beq m14(Alu_result,or_for_beq);
xor m15(xor_for_beq,or_for_beq,1'b1);

Data_Memory m8(clk,Alu_result, read_data_2, MemWrite,MemRead,read_data);
m21_32_bit m9(write_data,Alu_result,read_data,MemtoReg);
and m10(branch_1,xor_for_beq,Branch);
and m16(branch_2,or_for_beq,Branch_not);
or m17(branch_,branch_1,branch_2);
Adder_5_bit m11(_32_bit[4:0],adding_pc,adding_branch);
m21_5_bit m12(branch_result, adding_pc, adding_branch,branch_);
endmodule
module Mips(input clk);

wire [15:0]instruction;
wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
wire [2:0]rt_rd;
wire [31:0]read_data_1, read_data_2;
wire [31:0]write_data;
wire [31:0] _32_bit;
wire [31:0] Alu_choose;
wire [31:0] Alu_result;
wire C2,C1,C0;
wire Co;
wire [31:0] read_data;
wire branch_1,branch_2,branch_;
wire [4:0]branch_result,adding_branch;
reg [4:0]pc_current;
wire [4:0] adding_pc;
wire or_for_beq,xor_for_beq;
initial begin
  pc_current <= 5'b00000;
 end
 always @(posedge clk)
 begin 
   pc_current <= branch_result;
 end

 Adder_5_bit m13(pc_current,5'b00001,adding_pc);
Instruction_Memory m0(pc_current,instruction);

Main_Control m1(instruction[15:12],RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);

Alu_Control m6(ALUop2,ALUop1,ALUop0,instruction[2:0],C2,C1,C0);
m21_3_bit m2(rt_rd,instruction[8:6],instruction[5:3],RegDst);
Registers m3(read_data_1, read_data_2, write_data, instruction[11:9], instruction[8:6],rt_rd,RegWrite,clk);
Sign_Extend m4(instruction [5:0] ,_32_bit);

m21_32_bit m5(Alu_choose, read_data_2, _32_bit,ALUSrc);

alu_32_bit m7(read_data_1,Alu_choose,C0,C1,C2,C1,Alu_result,Co);
or_for_beq m14(Alu_result,or_for_beq);
xor m15(xor_for_beq,or_for_beq,1'b1);

Data_Memory m8(clk,Alu_result, read_data_2, MemWrite,MemRead,read_data);
m21_32_bit m9(write_data,Alu_result,read_data,MemtoReg);
and m10(branch_1,xor_for_beq,Branch);
and m16(branch_2,or_for_beq,Branch_not);
or m17(branch_,branch_1,branch_2);
Adder_5_bit m11(_32_bit[4:0],adding_pc,adding_branch);
m21_5_bit m12(branch_result, adding_pc, adding_branch,branch_);
endmodule