data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/55_Mt2015_q4.v
data/verilator_xmls/9b2deb4a-4120-43aa-844a-09b639a18ab6.xml
module A(input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule
module A(input x, input y, output z);

    assign z = (x ^ y) & x;
endmodule