data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:38: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:39: Cannot find include file: whr_constants.v\n`include "whr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:51: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:54: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:62: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? 1 :\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:62: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? 1 :\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:66: Define or directive not defined: \'`ELIG_MASK_NONE\'\n   parameter elig_mask = `ELIG_MASK_NONE;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter elig_mask = `ELIG_MASK_NONE;\n                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:70: Define or directive not defined: \'`ELIG_MASK_USED\'\n     = flow_ctrl_bypass && (elig_mask == `ELIG_MASK_USED);\n                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:70: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = flow_ctrl_bypass && (elig_mask == `ELIG_MASK_USED);\n                                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:92: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:92: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:94: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:96: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:108: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NO_HOLD\'\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:113: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:191: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n       .mgmt_type(`FB_MGMT_TYPE_STATIC),\n                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:246: Define or directive not defined: \'`ELIG_MASK_NONE\'\n `ELIG_MASK_NONE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:246: syntax error, unexpected \':\', expecting endcase\n `ELIG_MASK_NONE:\n                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:249: Define or directive not defined: \'`ELIG_MASK_FULL\'\n `ELIG_MASK_FULL:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:252: Define or directive not defined: \'`ELIG_MASK_USED\'\n `ELIG_MASK_USED:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:289: syntax error, unexpected generate\n   generate\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:291: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NONE\'\n      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/whr_op_ctrl_mac.v:309: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 30 error(s)\n'
module whr_op_ctrl_mac
  (clk, reset, flow_ctrl_in, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_data_in, channel_out, elig, full, error);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "whr_constants.v"
   

   parameter buffer_size = 8;
   

   parameter num_routers_per_dim = 4;
   

   parameter num_ports = 5;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? 1 :
       -1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam fast_almost_empty
     = flow_ctrl_bypass && (elig_mask == `ELIG_MASK_USED);
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);


   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   input 		       flit_valid_in;
   

   input 		       flit_head_in;
   

   input 		       flit_tail_in;
   

   input [0:flit_data_width-1] flit_data_in;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   

   output 		       elig;
   wire 		       elig;
   

   output 		       full;
   wire 		       full;
   

   output 		       error;
   wire 		       error;
   
   



   
   wire 		       fcs_fc_active;
   
   wire 		       flow_ctrl_active;
   assign flow_ctrl_active = fcs_fc_active;
   
   wire 		       fc_event_valid;
   wire 		       fc_event_sel_ovc;
   rtr_flow_ctrl_input
     #(.num_vcs(1),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fci
     (.clk(clk),
      .reset(reset),
      .active(flow_ctrl_active),
      .flow_ctrl_in(flow_ctrl_in),
      .fc_event_valid_out(fc_event_valid),
      .fc_event_sel_out_ovc(fc_event_sel_ovc));
   
   



   
   wire 		       fcs_active;
   assign fcs_active = flit_valid_in | fc_event_valid;
   
   wire 		       fcs_empty;
   wire 		       fcs_almost_full;
   wire 		       fcs_full;
   wire 		       fcs_full_prev;
   wire [0:1] 		       fcs_errors;
   rtr_fc_state
     #(.num_vcs(1),
       .buffer_size(buffer_size),
       .flow_ctrl_type(flow_ctrl_type),
       .flow_ctrl_bypass(flow_ctrl_bypass),
       .mgmt_type(`FB_MGMT_TYPE_STATIC),
       .fast_almost_empty(fast_almost_empty),
       .disable_static_reservations(0),
       .reset_type(reset_type))
   fcs
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .flit_valid(flit_valid_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .flit_sel_ovc(1'b1),
      .fc_event_valid(fc_event_valid),
      .fc_event_sel_ovc(1'b1),
      .fc_active(fcs_fc_active),
      .empty_ovc(fcs_empty),
      .almost_full_ovc(fcs_almost_full),
      .full_ovc(fcs_full),
      .full_prev_ovc(fcs_full_prev),
      .errors_ovc(fcs_errors));
   
   assign full = fcs_full;
   
   



   






   
   wire 		       allocated;
   
   wire 		       allocated_s, allocated_q;
   assign allocated_s = allocated;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   allocatedq
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .d(allocated_s),
      .q(allocated_q));
   
   assign allocated = flit_valid_in ? ~flit_tail_in : allocated_q;
   
   generate
      
      case(elig_mask)
	
	`ELIG_MASK_NONE:
	  assign elig = ~allocated;
	
	`ELIG_MASK_FULL:
	  assign elig = ~allocated & ~fcs_full;
	
	`ELIG_MASK_USED:
	  assign elig = ~allocated & fcs_empty;
	
      endcase
      
   endgenerate
   
   



   
   wire 					 flit_out_active;
   assign flit_out_active = flit_valid_in;
   
   rtr_channel_output
     #(.num_vcs(1),
       .packet_format(packet_format),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   cho
     (.clk(clk),
      .reset(reset),
      .active(flit_out_active),
      .flit_valid_in(flit_valid_in),
      .flit_head_in(flit_head_in),
      .flit_tail_in(flit_tail_in),
      .flit_data_in(flit_data_in),
      .flit_sel_in_ovc(1'b1),
      .channel_out(channel_out));
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:1] errors_s, errors_q;
	   assign errors_s = fcs_errors;
	   c_err_rpt
	     #(.num_errors(2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule
module whr_op_ctrl_mac
  (clk, reset, flow_ctrl_in, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_data_in, channel_out, elig, full, error);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "whr_constants.v"
   

   parameter buffer_size = 8;
   

   parameter num_routers_per_dim = 4;
   

   parameter num_ports = 5;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? 1 :
       -1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam fast_almost_empty
     = flow_ctrl_bypass && (elig_mask == `ELIG_MASK_USED);
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);


   parameter enable_link_pm = 1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + 1) : 
       -1;
   

   parameter flit_data_width = 64;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   input 		       flit_valid_in;
   

   input 		       flit_head_in;
   

   input 		       flit_tail_in;
   

   input [0:flit_data_width-1] flit_data_in;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   

   output 		       elig;
   wire 		       elig;
   

   output 		       full;
   wire 		       full;
   

   output 		       error;
   wire 		       error;
   
   



   
   wire 		       fcs_fc_active;
   
   wire 		       flow_ctrl_active;
   assign flow_ctrl_active = fcs_fc_active;
   
   wire 		       fc_event_valid;
   wire 		       fc_event_sel_ovc;
   rtr_flow_ctrl_input
     #(.num_vcs(1),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fci
     (.clk(clk),
      .reset(reset),
      .active(flow_ctrl_active),
      .flow_ctrl_in(flow_ctrl_in),
      .fc_event_valid_out(fc_event_valid),
      .fc_event_sel_out_ovc(fc_event_sel_ovc));
   
   



   
   wire 		       fcs_active;
   assign fcs_active = flit_valid_in | fc_event_valid;
   
   wire 		       fcs_empty;
   wire 		       fcs_almost_full;
   wire 		       fcs_full;
   wire 		       fcs_full_prev;
   wire [0:1] 		       fcs_errors;
   rtr_fc_state
     #(.num_vcs(1),
       .buffer_size(buffer_size),
       .flow_ctrl_type(flow_ctrl_type),
       .flow_ctrl_bypass(flow_ctrl_bypass),
       .mgmt_type(`FB_MGMT_TYPE_STATIC),
       .fast_almost_empty(fast_almost_empty),
       .disable_static_reservations(0),
       .reset_type(reset_type))
   fcs
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .flit_valid(flit_valid_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .flit_sel_ovc(1'b1),
      .fc_event_valid(fc_event_valid),
      .fc_event_sel_ovc(1'b1),
      .fc_active(fcs_fc_active),
      .empty_ovc(fcs_empty),
      .almost_full_ovc(fcs_almost_full),
      .full_ovc(fcs_full),
      .full_prev_ovc(fcs_full_prev),
      .errors_ovc(fcs_errors));
   
   assign full = fcs_full;
   
   



   






   
   wire 		       allocated;
   
   wire 		       allocated_s, allocated_q;
   assign allocated_s = allocated;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   allocatedq
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .d(allocated_s),
      .q(allocated_q));
   
   assign allocated = flit_valid_in ? ~flit_tail_in : allocated_q;
   
   generate
      
      case(elig_mask)
	
	`ELIG_MASK_NONE:
	  assign elig = ~allocated;
	
	`ELIG_MASK_FULL:
	  assign elig = ~allocated & ~fcs_full;
	
	`ELIG_MASK_USED:
	  assign elig = ~allocated & fcs_empty;
	
      endcase
      
   endgenerate
   
   



   
   wire 					 flit_out_active;
   assign flit_out_active = flit_valid_in;
   
   rtr_channel_output
     #(.num_vcs(1),
       .packet_format(packet_format),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   cho
     (.clk(clk),
      .reset(reset),
      .active(flit_out_active),
      .flit_valid_in(flit_valid_in),
      .flit_head_in(flit_head_in),
      .flit_tail_in(flit_tail_in),
      .flit_data_in(flit_data_in),
      .flit_sel_in_ovc(1'b1),
      .channel_out(channel_out));
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:1] errors_s, errors_q;
	   assign errors_s = fcs_errors;
	   c_err_rpt
	     #(.num_errors(2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule