data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Adder.v
data/verilator_xmls/b7608e35-34a6-4eee-be90-2d5850c15b8b.xml
module Adder(input[31:0] op1,
		input[31:0] op2,
		output[31:0] result);
	
	assign result = op1 + op2;

endmodule
module Adder(input[31:0] op1,
		input[31:0] op2,
		output[31:0] result);

	
	assign result = op1 + op2;

endmodule