data/full_repos/permissive/505376079/testbench/tb_nblock.sv
1: b'%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:38: syntax error, unexpected clocking\n  clocking drv_ck @(posedge aclk);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:42: syntax error, unexpected endclocking\n  endclocking\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:54: Unsupported: wait statements\n    wait(intf.drv_ck.m_tvalid == 1\'b1)\n    ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:62: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:72: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:78: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:84: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:91: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:112: Unsupported: Ignoring delay on this delayed statement.\n    #1.5625 aclk = !aclk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:117: Unsupported: Ignoring delay on this delayed statement.\n  #15.6 aresetn <= 0;\n  ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:118: syntax error, unexpected \'@\'\n  repeat(5) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:120: syntax error, unexpected \'@\'\n  repeat(10) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:124: syntax error, unexpected \'@\'\n  repeat(5) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:127: syntax error, unexpected \'@\'\n  repeat(2) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:189: syntax error, unexpected \'@\'\n  repeat(20) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:193: syntax error, unexpected \'@\'\n  repeat(50) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:198: syntax error, unexpected \'@\'\n  repeat(20) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:199: Unsupported: wait statements\n  wait ( intf.s_tready == 1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:208: Unsupported: fork statements\n  fork\n  ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:210: Unsupported: wait statements\n                wait(intf.drv_ck.m_tvalid == 1\'b1)\n                ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:250: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module tb_network;

bit aclk;
logic aresetn;

mlp_if intf(.*);
sim_mlp sim_mlp(intf);
int n,j,k,m;
  integer weight_in4,weight_in3,weight_in2,weight_in1,activation_in;
  integer fid_in4,fid_in3,fid_in2,fid_in1,fid_in,num_out;

initial begin 
    fid_in4 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc4weightbias.txt","r");
    fid_in3 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc3weightbias.txt","r");
    fid_in2 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc2weightbias.txt","r");
    fid_in1 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc1weightbias.txt","r");
    fid_in = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/activation.txt","r");
    num_out = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/txt_out.txt","w");
  forever begin
    #1.5625 aclk = !aclk;
  end
end

initial begin 
  #15.6 aresetn <= 0;
  repeat(5) @(posedge aclk);
  sim_mlp.set_idle;
  repeat(10) @(posedge aclk);
  aresetn <= 1;

  sim_mlp.set_idle;
  repeat(5) @(posedge aclk);
  sim_mlp.set_reg(2);
  sim_mlp.set_idle;
  repeat(2) @(posedge aclk);


  for (j = 0; j<1; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<4; n=n+1) 
      begin
        $fscanf(fid_in1,"%d",weight_in1);
          m =weight_in1;
        sim_mlp.sent_weight(256+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end

  for (j = 0; j<3; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in2,"%d",weight_in2);
          m =weight_in2;
        sim_mlp.sent_weight((256<<1)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end


  for (j = 0; j<3; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in3,"%d",weight_in3);
          m =weight_in3;
        sim_mlp.sent_weight((256<<2)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end

  for (j = 0; j<1; j=j+1) 
  begin
    for (k = 0; k<3; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in4,"%d",weight_in4);
          m =weight_in4;
        sim_mlp.sent_weight((256<<3)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end



  repeat(20) @(posedge aclk);
  sim_mlp.set_reg(1);
  sim_mlp.set_idle;
  intf.m_tready = 1'b1;
  repeat(50) @(posedge aclk);


for (j = 0; j<199223; j=j+1)
      begin 
  repeat(20) @(posedge aclk);
  wait ( intf.s_tready == 1'b1);
  for ( n = 1; n<4; n=n+1) 
  begin
  $fscanf(fid_in,"%d",activation_in);
            m =activation_in;
   sim_mlp.sent_pack(m, 0);
  end
  sim_mlp.sent_pack(256, 1);
  sim_mlp.set_idle;
  fork
            shortint resut_nn;
                wait(intf.drv_ck.m_tvalid == 1'b1)
                    begin
                        resut_nn = intf.m_tdata;
                        $fwrite(num_out,"%d \n", resut_nn);
                    end
           sim_mlp.print_result;
        join
  end
  end



mlp_stcf  mlp_stcf(
    .aclk(aclk),
    .aresetn(aresetn),


    .w_tdata(intf.w_tdata),




    .s_tvalid(intf.s_tvalid),
    .s_tready(intf.s_tready),
    .s_tdata(intf.s_tdata),
    .s_tlast(intf.s_tlast),


    .set_in(intf.set_in),
    .set_en(intf.set_en),
    .set_out(intf.set_out),



    .m_tvalid(intf.m_tvalid),
    .m_tready(intf.m_tready),
    .m_tdata(intf.m_tdata)


    );
endmodule
module tb_network;


bit aclk;
logic aresetn;

mlp_if intf(.*);
sim_mlp sim_mlp(intf);
int n,j,k,m;
  integer weight_in4,weight_in3,weight_in2,weight_in1,activation_in;
  integer fid_in4,fid_in3,fid_in2,fid_in1,fid_in,num_out;

initial begin 
    fid_in4 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc4weightbias.txt","r");
    fid_in3 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc3weightbias.txt","r");
    fid_in2 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc2weightbias.txt","r");
    fid_in1 = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/fc1weightbias.txt","r");
    fid_in = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/activation.txt","r");
    num_out = $fopen("D:/xilinx/Vivado/design_flow/muon_trigger2/txt_out.txt","w");
  forever begin
    #1.5625 aclk = !aclk;
  end
end

initial begin 
  #15.6 aresetn <= 0;
  repeat(5) @(posedge aclk);
  sim_mlp.set_idle;
  repeat(10) @(posedge aclk);
  aresetn <= 1;

  sim_mlp.set_idle;
  repeat(5) @(posedge aclk);
  sim_mlp.set_reg(2);
  sim_mlp.set_idle;
  repeat(2) @(posedge aclk);


  for (j = 0; j<1; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<4; n=n+1) 
      begin
        $fscanf(fid_in1,"%d",weight_in1);
          m =weight_in1;
        sim_mlp.sent_weight(256+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end

  for (j = 0; j<3; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in2,"%d",weight_in2);
          m =weight_in2;
        sim_mlp.sent_weight((256<<1)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end


  for (j = 0; j<3; j=j+1) 
  begin
    for (k = 0; k<20; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in3,"%d",weight_in3);
          m =weight_in3;
        sim_mlp.sent_weight((256<<2)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end

  for (j = 0; j<1; j=j+1) 
  begin
    for (k = 0; k<3; k=k+1) 
    begin
      for (n = 0; n<7; n=n+1) 
      begin
        $fscanf(fid_in4,"%d",weight_in4);
          m =weight_in4;
        sim_mlp.sent_weight((256<<3)+j*32+k,m);
      end
      sim_mlp.set_idle;
    end  
  end



  repeat(20) @(posedge aclk);
  sim_mlp.set_reg(1);
  sim_mlp.set_idle;
  intf.m_tready = 1'b1;
  repeat(50) @(posedge aclk);


for (j = 0; j<199223; j=j+1)
      begin 
  repeat(20) @(posedge aclk);
  wait ( intf.s_tready == 1'b1);
  for ( n = 1; n<4; n=n+1) 
  begin
  $fscanf(fid_in,"%d",activation_in);
            m =activation_in;
   sim_mlp.sent_pack(m, 0);
  end
  sim_mlp.sent_pack(256, 1);
  sim_mlp.set_idle;
  fork
            shortint resut_nn;
                wait(intf.drv_ck.m_tvalid == 1'b1)
                    begin
                        resut_nn = intf.m_tdata;
                        $fwrite(num_out,"%d \n", resut_nn);
                    end
           sim_mlp.print_result;
        join
  end
  end



mlp_stcf  mlp_stcf(
    .aclk(aclk),
    .aresetn(aresetn),


    .w_tdata(intf.w_tdata),




    .s_tvalid(intf.s_tvalid),
    .s_tready(intf.s_tready),
    .s_tdata(intf.s_tdata),
    .s_tlast(intf.s_tlast),


    .set_in(intf.set_in),
    .set_en(intf.set_en),
    .set_out(intf.set_out),



    .m_tvalid(intf.m_tvalid),
    .m_tready(intf.m_tready),
    .m_tdata(intf.m_tdata)


    );
endmodule