data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0/axis_ram_writer.v
1: b'%Error: data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0/axis_ram_writer.v:114: Cannot find file containing module: \'FIFO36E1\'\n      FIFO36E1 #(\n      ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0,data/full_repos/permissive/428611613/FIFO36E1\n             data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0,data/full_repos/permissive/428611613/FIFO36E1.v\n             data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0,data/full_repos/permissive/428611613/FIFO36E1.sv\n             FIFO36E1\n             FIFO36E1.v\n             FIFO36E1.sv\n             obj_dir/FIFO36E1\n             obj_dir/FIFO36E1.v\n             obj_dir/FIFO36E1.sv\n%Warning-WIDTH: data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0/axis_ram_writer.v:149: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                     : ... In instance axis_ram_writer\n   int_res_reg <= 8\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0/axis_ram_writer.v:199: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 19 bits.\n                                                                                                     : ... In instance axis_ram_writer\n  assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1\'b0}}};\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/428611613/cores/axis_ram_writer_v2_0/axis_ram_writer.v:201: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADDR_SIZE\' generates 32 bits.\n                                                                                                     : ... In instance axis_ram_writer\n  assign m_axi_awsize = ADDR_SIZE;\n                      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module axis_ram_writer #
(
  parameter integer ADDR_WIDTH = 16,
  parameter integer AXI_ID_WIDTH = 3,
  parameter integer AXI_ADDR_WIDTH = 32,
  parameter integer AXI_DATA_WIDTH = 64,
  parameter integer AXIS_TDATA_WIDTH = 64
)
(

  input  wire                        aclk,
  input  wire                        aresetn,

  input  wire [AXI_ADDR_WIDTH-1:0]   cfg_data,
  output wire [ADDR_WIDTH-1:0]       sts_data,


  output wire [AXI_ID_WIDTH-1:0]     m_axi_awid,
  output wire [AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
  output wire [3:0]                  m_axi_awlen,
  output wire [2:0]                  m_axi_awsize,
  output wire [1:0]                  m_axi_awburst,
  output wire [3:0]                  m_axi_awcache,
  output wire                        m_axi_awvalid,
  input  wire                        m_axi_awready,
  output wire [AXI_ID_WIDTH-1:0]     m_axi_wid,
  output wire [AXI_DATA_WIDTH-1:0]   m_axi_wdata,
  output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
  output wire                        m_axi_wlast,
  output wire                        m_axi_wvalid,
  input  wire                        m_axi_wready,
  input  wire                        m_axi_bvalid,
  output wire                        m_axi_bready,


  output wire                        s_axis_tready,
  input  wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
  input  wire                        s_axis_tvalid
);

  function integer clogb2 (input integer value);
    for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
  endfunction

  localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);

  reg int_awvalid_reg, int_awvalid_next;
  reg int_wvalid_reg, int_wvalid_next;
  reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
  reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
  reg [3:0] int_res_reg, int_res_next;
  

  wire int_fifo_rst_wire;
  wire int_full_wire_0, int_empty_wire_0, int_rden_wire_0, int_full_wire_1, int_empty_wire_1 , int_rden_wire_1;
  wire int_wlast_wire, int_tready_wire;
  wire [71:0] int_wdata_wire_0, int_wdata_wire_1;

  assign int_tready_wire = ~int_full_wire_0;
  assign int_wlast_wire = &int_addr_reg[3:0];
  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
    assign int_rden_wire_0 = m_axi_wready & int_wvalid_reg & int_addr_reg[0:0];
    assign int_rden_wire_1 = m_axi_wready & int_wvalid_reg & ~int_addr_reg[0:0];
  end
  else
  begin
    assign int_rden_wire_0 = m_axi_wready & int_wvalid_reg;
  end
  endgenerate
  assign int_fifo_rst_wire = int_res_reg >= 4'b1110;

  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_0 (
        .FULL(int_full_wire_0),
        .ALMOSTEMPTY(int_empty_wire_0),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({8'b0, s_axis_tdata[63:0]}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_0),
        .DO(int_wdata_wire_0)
      );
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_1 (
        .FULL(int_full_wire_1),
        .ALMOSTEMPTY(int_empty_wire_1),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({{(136-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata[AXIS_TDATA_WIDTH-1:64]}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_1),
        .DO(int_wdata_wire_1)
      );
  end
  else
  begin
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_0 (
        .FULL(int_full_wire_0),
        .ALMOSTEMPTY(int_empty_wire_0),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_0),
        .DO(int_wdata_wire_0)
      );
  end
  endgenerate
  
  always @(posedge aclk)
  begin
    if(~aresetn)
    begin
      int_awvalid_reg <= 1'b0;
      int_wvalid_reg <= 1'b0;
      int_addr_reg <= {(ADDR_WIDTH){1'b0}};
      int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
	  int_res_reg <= int_res_next;
    end
    else
    begin
      int_awvalid_reg <= int_awvalid_next;
      int_wvalid_reg <= int_wvalid_next;
      int_addr_reg <= int_addr_next;
      int_wid_reg <= int_wid_next;
	  int_res_reg <= 8'b0;
    end
  end
  
  always @*
  begin
    int_awvalid_next = int_awvalid_reg;
    int_wvalid_next = int_wvalid_reg;
    int_addr_next = int_addr_reg;
    int_wid_next = int_wid_reg;
    int_res_next = int_res_reg;
    
    if(int_res_reg < 4'b1110)
    begin
        int_res_next = int_res_reg + 1'b1;
    end
    
    if((~int_empty_wire_0 & ~int_empty_wire_1) & ~int_awvalid_reg & ~int_wvalid_reg)
    begin
      int_awvalid_next = 1'b1;
      int_wvalid_next = 1'b1;
    end

    if(m_axi_awready & int_awvalid_reg)
    begin
      int_awvalid_next = 1'b0;
    end

    if(int_rden_wire_0 | int_rden_wire_1)
    begin
      int_addr_next = int_addr_reg + 1'b1;
    end

    if(m_axi_wready & int_wlast_wire)
    begin
      int_wid_next = int_wid_reg + 1'b1;
      if(int_empty_wire_0 | int_empty_wire_1)
      begin
        int_wvalid_next = 1'b0;
      end
      else
      begin
        int_awvalid_next = 1'b1;
      end
    end
  end
  
  assign sts_data = int_addr_reg;

  assign m_axi_awid = int_wid_reg;
  assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
  assign m_axi_awlen = 4'd15;
  assign m_axi_awsize = ADDR_SIZE;
  assign m_axi_awburst = 2'b01;
  assign m_axi_awcache = 4'b1111;
  assign m_axi_awvalid = int_awvalid_reg;
  assign m_axi_wid = int_wid_reg;
  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
    assign m_axi_wdata = int_addr_reg[0:0] ? int_wdata_wire_1[AXI_DATA_WIDTH-1:0] : int_wdata_wire_0[AXI_DATA_WIDTH-1:0];
  end
  else
  begin
    assign m_axi_wdata = int_wdata_wire_0[AXI_DATA_WIDTH-1:0];
  end
  endgenerate
  assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
  assign m_axi_wlast = int_wlast_wire;
  assign m_axi_wvalid = int_wvalid_reg;
  assign m_axi_bready = 1'b1;

  assign s_axis_tready = int_tready_wire;

endmodule
module axis_ram_writer #
(
  parameter integer ADDR_WIDTH = 16,
  parameter integer AXI_ID_WIDTH = 3,
  parameter integer AXI_ADDR_WIDTH = 32,
  parameter integer AXI_DATA_WIDTH = 64,
  parameter integer AXIS_TDATA_WIDTH = 64
)
(

  input  wire                        aclk,
  input  wire                        aresetn,

  input  wire [AXI_ADDR_WIDTH-1:0]   cfg_data,
  output wire [ADDR_WIDTH-1:0]       sts_data,


  output wire [AXI_ID_WIDTH-1:0]     m_axi_awid,
  output wire [AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
  output wire [3:0]                  m_axi_awlen,
  output wire [2:0]                  m_axi_awsize,
  output wire [1:0]                  m_axi_awburst,
  output wire [3:0]                  m_axi_awcache,
  output wire                        m_axi_awvalid,
  input  wire                        m_axi_awready,
  output wire [AXI_ID_WIDTH-1:0]     m_axi_wid,
  output wire [AXI_DATA_WIDTH-1:0]   m_axi_wdata,
  output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
  output wire                        m_axi_wlast,
  output wire                        m_axi_wvalid,
  input  wire                        m_axi_wready,
  input  wire                        m_axi_bvalid,
  output wire                        m_axi_bready,


  output wire                        s_axis_tready,
  input  wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
  input  wire                        s_axis_tvalid
);


  function integer clogb2 (input integer value);
    for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
  endfunction

  localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);

  reg int_awvalid_reg, int_awvalid_next;
  reg int_wvalid_reg, int_wvalid_next;
  reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
  reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
  reg [3:0] int_res_reg, int_res_next;
  

  wire int_fifo_rst_wire;
  wire int_full_wire_0, int_empty_wire_0, int_rden_wire_0, int_full_wire_1, int_empty_wire_1 , int_rden_wire_1;
  wire int_wlast_wire, int_tready_wire;
  wire [71:0] int_wdata_wire_0, int_wdata_wire_1;

  assign int_tready_wire = ~int_full_wire_0;
  assign int_wlast_wire = &int_addr_reg[3:0];
  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
    assign int_rden_wire_0 = m_axi_wready & int_wvalid_reg & int_addr_reg[0:0];
    assign int_rden_wire_1 = m_axi_wready & int_wvalid_reg & ~int_addr_reg[0:0];
  end
  else
  begin
    assign int_rden_wire_0 = m_axi_wready & int_wvalid_reg;
  end
  endgenerate
  assign int_fifo_rst_wire = int_res_reg >= 4'b1110;

  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_0 (
        .FULL(int_full_wire_0),
        .ALMOSTEMPTY(int_empty_wire_0),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({8'b0, s_axis_tdata[63:0]}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_0),
        .DO(int_wdata_wire_0)
      );
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_1 (
        .FULL(int_full_wire_1),
        .ALMOSTEMPTY(int_empty_wire_1),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({{(136-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata[AXIS_TDATA_WIDTH-1:64]}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_1),
        .DO(int_wdata_wire_1)
      );
  end
  else
  begin
      FIFO36E1 #(
        .FIRST_WORD_FALL_THROUGH("TRUE"),
        .ALMOST_EMPTY_OFFSET(13'hf),
        .DATA_WIDTH(72),
        .FIFO_MODE("FIFO36_72")
      ) fifo_0 (
        .FULL(int_full_wire_0),
        .ALMOSTEMPTY(int_empty_wire_0),
        .RST(int_fifo_rst_wire),
        .WRCLK(aclk),
        .WREN(int_tready_wire & s_axis_tvalid),
        .DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
        .RDCLK(aclk),
        .RDEN(int_rden_wire_0),
        .DO(int_wdata_wire_0)
      );
  end
  endgenerate
  
  always @(posedge aclk)
  begin
    if(~aresetn)
    begin
      int_awvalid_reg <= 1'b0;
      int_wvalid_reg <= 1'b0;
      int_addr_reg <= {(ADDR_WIDTH){1'b0}};
      int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
	  int_res_reg <= int_res_next;
    end
    else
    begin
      int_awvalid_reg <= int_awvalid_next;
      int_wvalid_reg <= int_wvalid_next;
      int_addr_reg <= int_addr_next;
      int_wid_reg <= int_wid_next;
	  int_res_reg <= 8'b0;
    end
  end
  
  always @*
  begin
    int_awvalid_next = int_awvalid_reg;
    int_wvalid_next = int_wvalid_reg;
    int_addr_next = int_addr_reg;
    int_wid_next = int_wid_reg;
    int_res_next = int_res_reg;
    
    if(int_res_reg < 4'b1110)
    begin
        int_res_next = int_res_reg + 1'b1;
    end
    
    if((~int_empty_wire_0 & ~int_empty_wire_1) & ~int_awvalid_reg & ~int_wvalid_reg)
    begin
      int_awvalid_next = 1'b1;
      int_wvalid_next = 1'b1;
    end

    if(m_axi_awready & int_awvalid_reg)
    begin
      int_awvalid_next = 1'b0;
    end

    if(int_rden_wire_0 | int_rden_wire_1)
    begin
      int_addr_next = int_addr_reg + 1'b1;
    end

    if(m_axi_wready & int_wlast_wire)
    begin
      int_wid_next = int_wid_reg + 1'b1;
      if(int_empty_wire_0 | int_empty_wire_1)
      begin
        int_wvalid_next = 1'b0;
      end
      else
      begin
        int_awvalid_next = 1'b1;
      end
    end
  end
  
  assign sts_data = int_addr_reg;

  assign m_axi_awid = int_wid_reg;
  assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
  assign m_axi_awlen = 4'd15;
  assign m_axi_awsize = ADDR_SIZE;
  assign m_axi_awburst = 2'b01;
  assign m_axi_awcache = 4'b1111;
  assign m_axi_awvalid = int_awvalid_reg;
  assign m_axi_wid = int_wid_reg;
  generate
  if (AXIS_TDATA_WIDTH > 64)
  begin
    assign m_axi_wdata = int_addr_reg[0:0] ? int_wdata_wire_1[AXI_DATA_WIDTH-1:0] : int_wdata_wire_0[AXI_DATA_WIDTH-1:0];
  end
  else
  begin
    assign m_axi_wdata = int_wdata_wire_0[AXI_DATA_WIDTH-1:0];
  end
  endgenerate
  assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
  assign m_axi_wlast = int_wlast_wire;
  assign m_axi_wvalid = int_wvalid_reg;
  assign m_axi_bready = 1'b1;

  assign s_axis_tready = int_tready_wire;

endmodule