data/full_repos/permissive/406831108/MEALY seqence detector.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/406831108/MEALY\n        ... Looked in:\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY.v\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY.sv\n             data/full_repos/permissive/406831108/MEALY\n             data/full_repos/permissive/406831108/MEALY.v\n             data/full_repos/permissive/406831108/MEALY.sv\n             obj_dir/data/full_repos/permissive/406831108/MEALY\n             obj_dir/data/full_repos/permissive/406831108/MEALY.v\n             obj_dir/data/full_repos/permissive/406831108/MEALY.sv\n%Error: Cannot find file containing module: seqence\n%Error: Cannot find file containing module: detector.v\n%Error: Exiting due to 3 error(s)\n'
module test_sequence;
reg clock;
reg reset;
reg in_bit;
wire out_bit;
sequence_0111 uut (
.clock(clock),
.reset(reset),
.in_bit(in_bit),
.out_bit(out_bit)
);
initial begin
  $dumpfile("dump.vcd");
  $dumpvars(1);
clock = 0;
reset = 0;
in_bit = 0;
#10;
reset = 1;
in_bit = 0;
#10;
reset = 0;
in_bit = 0;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 1;
in_bit = 1;
#10;
reset = 0;
in_bit = 0;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
  $finish;
end
always begin #5 clock=~clock; end
endmodule
module test_sequence;

reg clock;
reg reset;
reg in_bit;
wire out_bit;
sequence_0111 uut (
.clock(clock),
.reset(reset),
.in_bit(in_bit),
.out_bit(out_bit)
);
initial begin
  $dumpfile("dump.vcd");
  $dumpvars(1);
clock = 0;
reset = 0;
in_bit = 0;
#10;
reset = 1;
in_bit = 0;
#10;
reset = 0;
in_bit = 0;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 1;
in_bit = 1;
#10;
reset = 0;
in_bit = 0;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
reset = 0;
in_bit = 1;
#10;
  $finish;
end
always begin #5 clock=~clock; end
endmodule