data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:43: Cannot find file containing module: 'i66vedic'\ni66vedic i66vedic1i\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i66vedic\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i66vedic.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i66vedic.sv\n             i66vedic\n             i66vedic.v\n             i66vedic.sv\n             obj_dir/i66vedic\n             obj_dir/i66vedic.v\n             obj_dir/i66vedic.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:52: Cannot find file containing module: 'i66vedic'\ni66vedic i66vedic2i\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:61: Cannot find file containing module: 'i66vedic'\ni66vedic i66vedic3i\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:70: Cannot find file containing module: 'i66vedic'\ni66vedic i66vedic4i\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:80: Cannot find file containing module: 'cla'\ncla #(12) i1212cla1i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:91: Cannot find file containing module: 'cla'\ncla #(12) i1212cla2i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i1212vedic.v:105: Cannot find file containing module: 'cla'\ncla #(12) i1212cla3i\n^~~\n%Error: Exiting due to 7 error(s)\n"
module i1212vedic
    (
     a,
     b,
     rslt
     );




parameter WIDTH = 12;
parameter RSWID = 24;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w66rslt1;

i66vedic i66vedic1i
    (
     .a(a[5:0]),
     .b(b[5:0]),
     .rslt(w66rslt1)
     );

wire [WIDTH-1:0]   w66rslt2;

i66vedic i66vedic2i
    (
     .a(a[5:0]),
     .b(b[11:6]),
     .rslt(w66rslt2)
     );

wire [WIDTH-1:0]   w66rslt3;

i66vedic i66vedic3i
    (
     .a(a[11:6]),
     .b(b[5:0]),
     .rslt(w66rslt3)
     );

wire [WIDTH-1:0]   w66rslt4;

i66vedic i66vedic4i
    (
     .a(a[11:6]),
     .b(b[11:6]),
     .rslt(w66rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(12) i1212cla1i
    (
     .a(w66rslt2),
     .b(w66rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(12) i1212cla2i
    (
     .a({6'b0,w66rslt1[11:6]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(12) i1212cla3i
    (
     .a(w66rslt4),
     .b({5'b0,cla3cin,cla2rslt[11:6]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[5:0],w66rslt1[5:0]};

endmodule
module i1212vedic
    (
     a,
     b,
     rslt
     );





parameter WIDTH = 12;
parameter RSWID = 24;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w66rslt1;

i66vedic i66vedic1i
    (
     .a(a[5:0]),
     .b(b[5:0]),
     .rslt(w66rslt1)
     );

wire [WIDTH-1:0]   w66rslt2;

i66vedic i66vedic2i
    (
     .a(a[5:0]),
     .b(b[11:6]),
     .rslt(w66rslt2)
     );

wire [WIDTH-1:0]   w66rslt3;

i66vedic i66vedic3i
    (
     .a(a[11:6]),
     .b(b[5:0]),
     .rslt(w66rslt3)
     );

wire [WIDTH-1:0]   w66rslt4;

i66vedic i66vedic4i
    (
     .a(a[11:6]),
     .b(b[11:6]),
     .rslt(w66rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(12) i1212cla1i
    (
     .a(w66rslt2),
     .b(w66rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(12) i1212cla2i
    (
     .a({6'b0,w66rslt1[11:6]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(12) i1212cla3i
    (
     .a(w66rslt4),
     .b({5'b0,cla3cin,cla2rslt[11:6]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[5:0],w66rslt1[5:0]};

endmodule