data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module.v:16: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance top_module\n  reg [9:0] q = 1\'b0;\n                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/CS450/timer/top_module.v:18: Operator EQ expects 10 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance top_module\n  assign tc = (q == 1\'b0);\n                 ^~\n%Error: Exiting due to 2 warning(s)\n'
module top_module(
	input wire clk,
	input wire load,
	input wire [9:0] data,
	output wire tc
);
  reg [9:0] q = 1'b0;

  assign tc = (q == 1'b0);

  always @(posedge clk) begin
    if (load) begin
      q <= data;
    end

    if (~load & ~tc) begin
      q <= q - 1'b1;
    end
  end
endmodule
module top_module(
	input wire clk,
	input wire load,
	input wire [9:0] data,
	output wire tc
);

  reg [9:0] q = 1'b0;

  assign tc = (q == 1'b0);

  always @(posedge clk) begin
    if (load) begin
      q <= data;
    end

    if (~load & ~tc) begin
      q <= q - 1'b1;
    end
  end
endmodule