data/full_repos/permissive/470816788/verilog/rtl/wrapped_hack_soc/hack_soc/DFFRF_2R1W.v
data/verilator_xmls/56005b70-3c5d-4e29-bbb5-cf41cd24d0fb.xml
module DFFRF_2R1W (
`ifdef USE_POWER_PINS
    inout vccd1,  
    inout vssd1,  
`endif
    input CLK,
    
    output [31:0] DA,
    output [31:0] DB,
    input [31:0] DW,
    input [4:0] RA,
    input [4:0] RB,
    input [4:0] RW,    
    input WE
); 



reg [31:0] RAM[ 31 : 0];

assign DA = RAM[RA];
assign DB = RAM[RB];



always @(posedge CLK) begin
    if (WE) begin
        RAM[RW] <= DW;
    end
end



endmodule
module DFFRF_2R1W (
`ifdef USE_POWER_PINS
    inout vccd1,  
    inout vssd1,  
`endif
    input CLK,
    
    output [31:0] DA,
    output [31:0] DB,
    input [31:0] DW,
    input [4:0] RA,
    input [4:0] RB,
    input [4:0] RW,    
    input WE
);
 



reg [31:0] RAM[ 31 : 0];

assign DA = RAM[RA];
assign DB = RAM[RB];



always @(posedge CLK) begin
    if (WE) begin
        RAM[RW] <= DW;
    end
end



endmodule