data/full_repos/permissive/507312280/rtl/core/rstc.v
data/verilator_xmls/b7987d2f-fd90-46d0-9e15-de32b860d155.xml
module rstc (
    input wire clk,
    input wire hard_rst_n,
    input wire soft_rst_en,
    input wire jtag_rst_en,
    output reg rst_n
);
reg [3:0] sys_rst_cnt = 4'h0;
reg hard_rst_r,hard_rst_en;


always @(posedge clk) begin
    hard_rst_r <= ~hard_rst_n;
    hard_rst_en <= hard_rst_r;
    if (jtag_rst_en | soft_rst_en | hard_rst_en) begin
        sys_rst_cnt <= 4'h0;
        rst_n <= 1'b0;
    end
    else begin
        if(sys_rst_cnt == 4'hF) begin
            sys_rst_cnt <= sys_rst_cnt;
            rst_n <= 1'b1;
        end
        else begin
            sys_rst_cnt <= sys_rst_cnt + 1;
            rst_n <= 1'b0;
        end
    end
end

endmodule
module rstc (
    input wire clk,
    input wire hard_rst_n,
    input wire soft_rst_en,
    input wire jtag_rst_en,
    output reg rst_n
);

reg [3:0] sys_rst_cnt = 4'h0;
reg hard_rst_r,hard_rst_en;


always @(posedge clk) begin
    hard_rst_r <= ~hard_rst_n;
    hard_rst_en <= hard_rst_r;
    if (jtag_rst_en | soft_rst_en | hard_rst_en) begin
        sys_rst_cnt <= 4'h0;
        rst_n <= 1'b0;
    end
    else begin
        if(sys_rst_cnt == 4'hF) begin
            sys_rst_cnt <= sys_rst_cnt;
            rst_n <= 1'b1;
        end
        else begin
            sys_rst_cnt <= sys_rst_cnt + 1;
            rst_n <= 1'b0;
        end
    end
end

endmodule