data/full_repos/permissive/475937410/Ass4/test_CPU.v
1: b'%Error: data/full_repos/permissive/475937410/Ass4/test_CPU.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/475937410/Ass4/test_CPU.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, CPU_test);     \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #period \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #period   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #period\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #period     total_clocks = total_clocks + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #period     total_clocks = total_clocks + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #period     total_clocks = total_clocks + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #period     total_clocks = total_clocks + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #period $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass4/test_CPU.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #5clock=~clock;\n       ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_test;


    reg clock;
    reg start;
    integer f_addr;
    integer total_clocks;
    integer f_mem_addr;

    integer i;

    CPU a(.clock(clock),.start(1'b0));

    initial begin
    clock=0;
    start=0;
    total_clocks = 2;

    $dumpfile("wave.vcd");
    $dumpvars(0, CPU_test);
    
    #period
    #period   

    while(a.InstrD != 32'b1 && total_clocks < 100000)
    begin
        #period 
        total_clocks = total_clocks + 1;
    end

    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;

    $display("Result memory space succesfully generated in <actual_memory.txt>");
    $display("Total clock count: %d", total_clocks);


    



    f_mem_addr = $fopen("actual_memory.txt","w");
    for(i = 0; i < 512; i = i + 1)begin
        $fwrite(f_mem_addr,"%b\n",a.b.DATA_RAM[i]);
    end






    #period $finish;

end

parameter period=10;
always #5clock=~clock;

endmodule
module CPU_test;



    reg clock;
    reg start;
    integer f_addr;
    integer total_clocks;
    integer f_mem_addr;

    integer i;

    CPU a(.clock(clock),.start(1'b0));

    initial begin
    clock=0;
    start=0;
    total_clocks = 2;

    $dumpfile("wave.vcd");
    $dumpvars(0, CPU_test);
    
    #period
    #period   

    while(a.InstrD != 32'b1 && total_clocks < 100000)
    begin
        #period 
        total_clocks = total_clocks + 1;
    end

    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;
    #period     total_clocks = total_clocks + 1;

    $display("Result memory space succesfully generated in <actual_memory.txt>");
    $display("Total clock count: %d", total_clocks);


    



    f_mem_addr = $fopen("actual_memory.txt","w");
    for(i = 0; i < 512; i = i + 1)begin
        $fwrite(f_mem_addr,"%b\n",a.b.DATA_RAM[i]);
    end






    #period $finish;

end

parameter period=10;
always #5clock=~clock;

endmodule