data/full_repos/permissive/477502690/vrased/hw-mod/VERSA_metadata.v
1: b'%Warning-WIDTH: data/full_repos/permissive/477502690/vrased/hw-mod/VERSA_metadata.v:81: Operator AND expects 512 bits on the LHS, but LHS\'s VARREF \'reg_dec\' generates 4 bits.\n                                                                                      : ... In instance VERSA_metadata\nwire [DEC_SZ-1:0] reg_wr    = reg_dec & {512{reg_write}};\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/477502690/vrased/hw-mod/VERSA_metadata.v:81: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 512 bits.\n                                                                                      : ... In instance VERSA_metadata\nwire [DEC_SZ-1:0] reg_wr    = reg_dec & {512{reg_write}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/477502690/vrased/hw-mod/VERSA_metadata.v:82: Operator AND expects 512 bits on the LHS, but LHS\'s VARREF \'reg_dec\' generates 4 bits.\n                                                                                      : ... In instance VERSA_metadata\nwire [DEC_SZ-1:0] reg_rd    = reg_dec & {512{reg_read}};\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/477502690/vrased/hw-mod/VERSA_metadata.v:82: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 512 bits.\n                                                                                      : ... In instance VERSA_metadata\nwire [DEC_SZ-1:0] reg_rd    = reg_dec & {512{reg_read}};\n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module  VERSA_metadata (


    per_dout,
    ER_min,
    ER_max,


    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    puc_rst
);


output      [15:0] per_dout;
output      [15:0] ER_min;
output      [15:0] ER_max;


input              mclk;
input       [13:0] per_addr;
input       [15:0] per_din;
input              per_en;
input        [1:0] per_we;
input              puc_rst;












parameter       [14:0] BASE_ADDR   = 15'h0140;

                                                         

parameter              DEC_WD      =  2;
                                                         

parameter [DEC_WD-1:0] ERMIN      =  'h0,               
                       ERMAX      =  'h1;            
                                                         
                                                         

parameter              DEC_SZ      =  (1 << DEC_WD);        
parameter [DEC_SZ-1:0] BASE_REG   =  {{DEC_SZ-1{1'b0}}, 1'b1};
                                                         

parameter [DEC_SZ-1:0] ERMIN_D  = (BASE_REG << ERMIN), 
                       ERMAX_D  = (BASE_REG << ERMAX);
                       





wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};


wire [DEC_SZ-1:0] reg_dec      = (ERMIN_D  &  {DEC_SZ{(reg_addr==ERMIN)}}) |
                                 (ERMAX_D  &  {DEC_SZ{(reg_addr==ERMAX)}});
                                 


wire              reg_write =  |per_we & reg_sel;
wire              reg_read  = ~|per_we & reg_sel;


wire [DEC_SZ-1:0] reg_wr    = reg_dec & {512{reg_write}};
wire [DEC_SZ-1:0] reg_rd    = reg_dec & {512{reg_read}};








reg  [15:0] ermin;

wire       ermin_wr  = reg_wr[ERMIN];
wire [15:0] ermin_nxt = per_din;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        ermin <=  16'hE07A;
  else if (ermin_wr)  ermin <=  ermin_nxt;
  


reg  [15:0] ermax;

wire       ermax_wr  = reg_wr[ERMAX];
wire [15:0] ermax_nxt = per_din;

always @ (posedge mclk or posedge puc_rst)
if (puc_rst)        ermax <=  16'hF000;
else if (ermax_wr) ermax <=  ermax_nxt;







wire [15:0] ermin_rd     = ermin             & {16{reg_rd[ERMIN]}};
wire [15:0] ermax_rd     = ermax             & {16{reg_rd[ERMAX]}};

wire [15:0] per_dout  =  ermin_rd  |
                         ermax_rd;
                         
wire [15:0] ER_min = ermin;
wire [15:0] ER_max = ermax;

endmodule
module  VERSA_metadata (


    per_dout,
    ER_min,
    ER_max,


    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    puc_rst
);



output      [15:0] per_dout;
output      [15:0] ER_min;
output      [15:0] ER_max;


input              mclk;
input       [13:0] per_addr;
input       [15:0] per_din;
input              per_en;
input        [1:0] per_we;
input              puc_rst;












parameter       [14:0] BASE_ADDR   = 15'h0140;

                                                         

parameter              DEC_WD      =  2;
                                                         

parameter [DEC_WD-1:0] ERMIN      =  'h0,               
                       ERMAX      =  'h1;            
                                                         
                                                         

parameter              DEC_SZ      =  (1 << DEC_WD);        
parameter [DEC_SZ-1:0] BASE_REG   =  {{DEC_SZ-1{1'b0}}, 1'b1};
                                                         

parameter [DEC_SZ-1:0] ERMIN_D  = (BASE_REG << ERMIN), 
                       ERMAX_D  = (BASE_REG << ERMAX);
                       





wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};


wire [DEC_SZ-1:0] reg_dec      = (ERMIN_D  &  {DEC_SZ{(reg_addr==ERMIN)}}) |
                                 (ERMAX_D  &  {DEC_SZ{(reg_addr==ERMAX)}});
                                 


wire              reg_write =  |per_we & reg_sel;
wire              reg_read  = ~|per_we & reg_sel;


wire [DEC_SZ-1:0] reg_wr    = reg_dec & {512{reg_write}};
wire [DEC_SZ-1:0] reg_rd    = reg_dec & {512{reg_read}};








reg  [15:0] ermin;

wire       ermin_wr  = reg_wr[ERMIN];
wire [15:0] ermin_nxt = per_din;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        ermin <=  16'hE07A;
  else if (ermin_wr)  ermin <=  ermin_nxt;
  


reg  [15:0] ermax;

wire       ermax_wr  = reg_wr[ERMAX];
wire [15:0] ermax_nxt = per_din;

always @ (posedge mclk or posedge puc_rst)
if (puc_rst)        ermax <=  16'hF000;
else if (ermax_wr) ermax <=  ermax_nxt;







wire [15:0] ermin_rd     = ermin             & {16{reg_rd[ERMIN]}};
wire [15:0] ermax_rd     = ermax             & {16{reg_rd[ERMAX]}};

wire [15:0] per_dout  =  ermin_rd  |
                         ermax_rd;
                         
wire [15:0] ER_min = ermin;
wire [15:0] ER_max = ermax;

endmodule