data/full_repos/permissive/528677531/LAB-4/Q2/qb.v
1: b"%Error: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:3: Input/output/inout does not appear in port list: 'Y'\ninput [3:0]x,y,Y;\n               ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:7: Assigning to input/const variable: 'Y'\nassign Y[0]=y[0]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:8: Assigning to input/const variable: 'Y'\nassign Y[1]=y[1]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:9: Assigning to input/const variable: 'Y'\nassign Y[2]=y[2]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:10: Assigning to input/const variable: 'Y'\nassign Y[3]=y[3]^carryin;\n       ^\n%Error: Exiting due to 5 error(s)\n"
module adder4 (carryin,x,y,s,carryout);
input carryin;
input [3:0]x,y,Y;
output [3:0]s;
output carryout;
wire [3:0]c;
assign Y[0]=y[0]^carryin;
assign Y[1]=y[1]^carryin;
assign Y[2]=y[2]^carryin;
assign Y[3]=y[3]^carryin;
fulladd stage0 (carryin, x[0], Y[0], s[0], c[1]);
fulladd stage1 (c[1], x[1], Y[1], s[1], c[2]);
fulladd stage2 (c[2], x[2], Y[2], s[2], c[3]);
fulladd stage3 (c[3], x[3], Y[3], s[3], carryout);
endmodule
module adder4 (carryin,x,y,s,carryout);

input carryin;
input [3:0]x,y,Y;
output [3:0]s;
output carryout;
wire [3:0]c;
assign Y[0]=y[0]^carryin;
assign Y[1]=y[1]^carryin;
assign Y[2]=y[2]^carryin;
assign Y[3]=y[3]^carryin;
fulladd stage0 (carryin, x[0], Y[0], s[0], c[1]);
fulladd stage1 (c[1], x[1], Y[1], s[1], c[2]);
fulladd stage2 (c[2], x[2], Y[2], s[2], c[3]);
fulladd stage3 (c[3], x[3], Y[3], s[3], carryout);
endmodule