data/full_repos/permissive/43264243/utx.v
1: b'%Error: data/full_repos/permissive/43264243/utx.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/utx.v:45: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/43264243/utx.v:52: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module comb_utx_sm(load, shiftregin, baudce, cur_utx_state, bitcounter, nextbit, bitcounterce, busy, done_int, serialout, next_utx_state);
	input load;
	input shiftregin;
	input baudce;
	input [1:0] cur_utx_state;
	input [3:0] bitcounter;
	output reg nextbit;
	output reg bitcounterce;
	output reg busy;
	output reg done_int;
	output reg serialout;
	output reg [1:0] next_utx_state;
	
	always @(*) begin
	

		busy <= 1;
		done_int <= 0;
		nextbit <= 0;
		serialout <= 1;
		bitcounterce <= baudce;
		
		case(cur_utx_state)
			`IDLE:
				if(load) begin
					next_utx_state <= `SENDSTART;
					serialout <= 0;
				end else begin
					busy <= 0;
					bitcounterce <= 0;
					next_utx_state <= `IDLE;
				end
		
			`SENDSTART:			
				if(baudce) begin

					next_utx_state <= `SENDBITS;
					serialout <= shiftregin;
				end else begin

					serialout <= 0;
					next_utx_state <= `SENDSTART;
				end
		
			`SENDBITS:

			
				begin
					if(bitcounter == 9) begin

						next_utx_state <= `SENDSTOP;
						serialout <= 1;
					end else begin

						serialout <= shiftregin;
						next_utx_state <= `SENDBITS;
						nextbit <= baudce;		
					end
				end
		
			`SENDSTOP:
				if(baudce) begin

					next_utx_state <= `IDLE;
					done_int <= 1;
					nextbit <= baudce;
				end else begin

					next_utx_state <= `SENDSTOP;
				end
	
		
			default:
				begin
					bitcounterce <= 1'bx;
					serialout <= 1'bx;
					busy <= 1'bx;
					next_utx_state <= 2'bxx;
				end
		endcase
	end
	
endmodule
module comb_utx_sm(load, shiftregin, baudce, cur_utx_state, bitcounter, nextbit, bitcounterce, busy, done_int, serialout, next_utx_state);

	input load;
	input shiftregin;
	input baudce;
	input [1:0] cur_utx_state;
	input [3:0] bitcounter;
	output reg nextbit;
	output reg bitcounterce;
	output reg busy;
	output reg done_int;
	output reg serialout;
	output reg [1:0] next_utx_state;
	
	always @(*) begin
	

		busy <= 1;
		done_int <= 0;
		nextbit <= 0;
		serialout <= 1;
		bitcounterce <= baudce;
		
		case(cur_utx_state)
			`IDLE:
				if(load) begin
					next_utx_state <= `SENDSTART;
					serialout <= 0;
				end else begin
					busy <= 0;
					bitcounterce <= 0;
					next_utx_state <= `IDLE;
				end
		
			`SENDSTART:			
				if(baudce) begin

					next_utx_state <= `SENDBITS;
					serialout <= shiftregin;
				end else begin

					serialout <= 0;
					next_utx_state <= `SENDSTART;
				end
		
			`SENDBITS:

			
				begin
					if(bitcounter == 9) begin

						next_utx_state <= `SENDSTOP;
						serialout <= 1;
					end else begin

						serialout <= shiftregin;
						next_utx_state <= `SENDBITS;
						nextbit <= baudce;		
					end
				end
		
			`SENDSTOP:
				if(baudce) begin

					next_utx_state <= `IDLE;
					done_int <= 1;
					nextbit <= baudce;
				end else begin

					next_utx_state <= `SENDSTOP;
				end
	
		
			default:
				begin
					bitcounterce <= 1'bx;
					serialout <= 1'bx;
					busy <= 1'bx;
					next_utx_state <= 2'bxx;
				end
		endcase
	end
	
endmodule