data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential Logic/Counters/count15.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943.sv\n             Logic/Counters,data/full_repos/permissive/506562943\n             Logic/Counters,data/full_repos/permissive/506562943.v\n             Logic/Counters,data/full_repos/permissive/506562943.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/count15.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input clk,
    input reset,
    output [3:0] q);

    reg [3:0] acc;
    initial acc = 0;
    assign q = acc;
    
    always @(posedge clk) begin
        if (reset)
            acc = 4'd0;
        else
            acc += 1'd1;
    end
    
endmodule
module top_module (
    input clk,
    input reset,
    output [3:0] q);


    reg [3:0] acc;
    initial acc = 0;
    assign q = acc;
    
    always @(posedge clk) begin
        if (reset)
            acc = 4'd0;
        else
            acc += 1'd1;
    end
    
endmodule