data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:8: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.sv\n             ./const/parameters.v\n             ./const/parameters.v.v\n             ./const/parameters.v.sv\n             obj_dir/./const/parameters.v\n             obj_dir/./const/parameters.v.v\n             obj_dir/./const/parameters.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:218: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:265: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:302: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:330: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:364: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:512: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:912: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module eac_cla_group(a, b, GG, GP, s, s_plus_one);



  parameter CLA_GRP_WIDTH=12;


  input [CLA_GRP_WIDTH-1:0] a, b;
  output [CLA_GRP_WIDTH-1:0] s, s_plus_one;
  output GG, GP;

  reg [CLA_GRP_WIDTH-1:0] G, P, sum, sum1;
  reg [CLA_GRP_WIDTH:0]  carry_in, carry_in1;

  wire cin;
  assign s = sum;
  assign s_plus_one = sum1;
  assign GG = carry_in[CLA_GRP_WIDTH];
  assign GP = &P;

  integer i;

  always @ (*) begin

     for(i=0;i<CLA_GRP_WIDTH;i=i+1) begin
        G[i] = a[i] & b[i];
        P[i] = a[i] ^ b[i];

     end


     carry_in[0] = 0;
     for(i=1;i<=CLA_GRP_WIDTH;i=i+1) begin
             carry_in[i]=G[i-1] | (carry_in[i-1] & P[i-1]) ;
     end

     carry_in1[0] = 1;
     for(i=1;i<=CLA_GRP_WIDTH;i=i+1) begin
             carry_in1[i]=G[i-1] | (carry_in1[i-1] & P[i-1]) ;
     end


  end


  always @ (*) begin
    for(i=0;i<CLA_GRP_WIDTH;i=i+1) begin
      sum[i] = carry_in[i] ^ P[i];
      sum1[i] = carry_in1[i] ^ P[i];
    end
  end


endmodule
module eac_cla_group(a, b, GG, GP, s, s_plus_one);




  parameter CLA_GRP_WIDTH=12;


  input [CLA_GRP_WIDTH-1:0] a, b;
  output [CLA_GRP_WIDTH-1:0] s, s_plus_one;
  output GG, GP;

  reg [CLA_GRP_WIDTH-1:0] G, P, sum, sum1;
  reg [CLA_GRP_WIDTH:0]  carry_in, carry_in1;

  wire cin;
  assign s = sum;
  assign s_plus_one = sum1;
  assign GG = carry_in[CLA_GRP_WIDTH];
  assign GP = &P;

  integer i;

  always @ (*) begin

     for(i=0;i<CLA_GRP_WIDTH;i=i+1) begin
        G[i] = a[i] & b[i];
        P[i] = a[i] ^ b[i];

     end


     carry_in[0] = 0;
     for(i=1;i<=CLA_GRP_WIDTH;i=i+1) begin
             carry_in[i]=G[i-1] | (carry_in[i-1] & P[i-1]) ;
     end

     carry_in1[0] = 1;
     for(i=1;i<=CLA_GRP_WIDTH;i=i+1) begin
             carry_in1[i]=G[i-1] | (carry_in1[i-1] & P[i-1]) ;
     end


  end


  always @ (*) begin
    for(i=0;i<CLA_GRP_WIDTH;i=i+1) begin
      sum[i] = carry_in[i] ^ P[i];
      sum1[i] = carry_in1[i] ^ P[i];
    end
  end


endmodule