data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/DM.v
data/verilator_xmls/12ba1877-0b70-404f-b0c1-b93e8ceede80.xml
module DM(
    input clk,
    input DMWE,
    input [31:0] DMA,
    input [31:0] DMWD,
    output [31:0] DMRD
    );
        
    reg [31:0] Memory [400:0];
    
    initial begin
        Memory[0] <= 17;
        Memory[1] <= 31;
        Memory[2] <= -5;
        Memory[3] <= -2;
        Memory[4] <= 250;
    end
    
    assign DMRD = (!DMWE) ? Memory[DMA] : 32'bX;
    
    always @(posedge clk) begin
        if (DMWE) begin
            Memory[DMA] <= DMWD;
        end
    end
endmodule
module DM(
    input clk,
    input DMWE,
    input [31:0] DMA,
    input [31:0] DMWD,
    output [31:0] DMRD
    );

        
    reg [31:0] Memory [400:0];
    
    initial begin
        Memory[0] <= 17;
        Memory[1] <= 31;
        Memory[2] <= -5;
        Memory[3] <= -2;
        Memory[4] <= 250;
    end
    
    assign DMRD = (!DMWE) ? Memory[DMA] : 32'bX;
    
    always @(posedge clk) begin
        if (DMWE) begin
            Memory[DMA] <= DMWD;
        end
    end
endmodule