data/full_repos/permissive/44647742/OneHot.v
data/verilator_xmls/21bf6897-60fc-4e36-bd25-8a2d48c44dd1.xml
module OneHot(
    input rst_n,
    input clk,
    input inp,
    output reg output_oneHot
    );
	 
	 reg[1:0] hold_state;
	 
	 always@(posedge clk or negedge rst_n)
	 begin
		if (~rst_n)
		begin
			hold_state<=2'b0;
			output_oneHot<=0;
		end
		else
		case(hold_state)
		2'b0:
		begin
			output_oneHot<=1'b0;
			if(inp==1'b0)
				hold_state<=2'b1;
		end
		2'b1:
		begin
			output_oneHot<=1'b0;
			if(inp==1'b1)
			begin
				hold_state<=2'b0;
				output_oneHot<=1'b1;
			end
		end
		endcase
	end
			


endmodule
module OneHot(
    input rst_n,
    input clk,
    input inp,
    output reg output_oneHot
    );

	 
	 reg[1:0] hold_state;
	 
	 always@(posedge clk or negedge rst_n)
	 begin
		if (~rst_n)
		begin
			hold_state<=2'b0;
			output_oneHot<=0;
		end
		else
		case(hold_state)
		2'b0:
		begin
			output_oneHot<=1'b0;
			if(inp==1'b0)
				hold_state<=2'b1;
		end
		2'b1:
		begin
			output_oneHot<=1'b0;
			if(inp==1'b1)
			begin
				hold_state<=2'b0;
				output_oneHot<=1'b1;
			end
		end
		endcase
	end
			


endmodule