data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/ProgamCounter.v
data/verilator_xmls/b98aa494-736d-4e6d-9251-57ec34c20e2d.xml
module ProgamCounter(
    input clk,
    input en,
    input w_en,
    input complete,
    input inc,
    input [27:0] data_in,
    output reg [7:0] instruction_address
    );
    reg start=1'b1;
    
    always @(posedge en)
        start<=1'b1;
    
    
     initial
        begin
            instruction_address=8'b0;
        end
    
    always @(posedge clk)
        begin
            if (complete==1)
                begin
                instruction_address <= instruction_address;
                end
            else if (start) 
                begin
                    if(w_en==1)
                        begin
                            instruction_address <= data_in[7:0];
                        end
                     else if (inc==1)
                         begin
                            instruction_address <= instruction_address+1;
                         end
                     else
                         begin
                            instruction_address<=instruction_address;
                         end
                 end   
        end
    
    
    
    
    
    
endmodule
module ProgamCounter(
    input clk,
    input en,
    input w_en,
    input complete,
    input inc,
    input [27:0] data_in,
    output reg [7:0] instruction_address
    );

    reg start=1'b1;
    
    always @(posedge en)
        start<=1'b1;
    
    
     initial
        begin
            instruction_address=8'b0;
        end
    
    always @(posedge clk)
        begin
            if (complete==1)
                begin
                instruction_address <= instruction_address;
                end
            else if (start) 
                begin
                    if(w_en==1)
                        begin
                            instruction_address <= data_in[7:0];
                        end
                     else if (inc==1)
                         begin
                            instruction_address <= instruction_address+1;
                         end
                     else
                         begin
                            instruction_address<=instruction_address;
                         end
                 end   
        end
    
    
    
    
    
    
endmodule