data/full_repos/permissive/434840709/week10/3.v
data/verilator_xmls/47f36fd3-3a96-449b-9933-3732f72a03a4.xml
module top_module( 
              input a, 
              input b, 
              output out 
);

    nor(out,a,b);


endmodule
module top_module( 
              input a, 
              input b, 
              output out 
);


    nor(out,a,b);


endmodule