data/full_repos/permissive/411457613/Pyverilog/verilogcode/function.v
data/verilator_xmls/61364be8-0ef0-41c6-97bb-8c4a8b690969.xml
function [3:0] inc;
    input [3:0] in;
    begin
      if(&inc) begin
        inc = 0;
      end else begin
        inc = in + 1;
      end
    end
  endfunction
function [3:0] inc;

    input [3:0] in;
    begin
      if(&inc) begin
        inc = 0;
      end else begin
        inc = in + 1;
      end
    end
  endfunction