data/full_repos/permissive/505451992/E_TOP.v
1: b"%Error: data/full_repos/permissive/505451992/E_TOP.v:52: Cannot find file containing module: 'encoder'\n    encoder ecd(.reset(reset),\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/encoder.sv\n             encoder\n             encoder.v\n             encoder.sv\n             obj_dir/encoder\n             obj_dir/encoder.v\n             obj_dir/encoder.sv\n%Error: data/full_repos/permissive/505451992/E_TOP.v:56: Cannot find file containing module: 'encoder'\n     encoder ece(.reset(reset),\n     ^~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:59: Cannot find file containing module: 'Clock'\n     Clock cok(.reset(reset),\n     ^~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:62: Cannot find file containing module: 'Converters'\n     Converters cvt(.PPR(PPR),\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:65: Cannot find file containing module: 'Converters'\n     Converters cvy(.PPR(PPR),\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:68: Cannot find file containing module: 'PWM_Generator'\n     PWM_Generator pga(\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:78: Cannot find file containing module: 'PWM_Generator'\n     PWM_Generator pgc(\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:91: Cannot find file containing module: 'Rate_switch'\n   Rate_switch rsh(.reset(reset),\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505451992/E_TOP.v:95: Cannot find file containing module: 'PPR_switch'\n   PPR_switch psh(.reset(reset),\n   ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module E_TOP(
input reset,
input clk,
input [3:0]PR,
input[2:0] R,
input A,
input B,
input C,
input D,

output PWM_AB,
output PWM_CD
    );

reg CLK;
wire [23:0] Rate;
wire [9:0] PPR;
wire signed [9:0] P_AB;
wire signed [9:0] P_CD;
wire [9:0] Position_AB;
wire [9:0] Position_CD;








    encoder ecd(.reset(reset),
     .CLK(clk),.A(A),.B(B),.PPR(PPR),.P(P_AB));
     

     encoder ece(.reset(reset),
     .CLK(clk),.A(C),.B(D),.PPR(PPR),.P(P_CD));
     
     Clock cok(.reset(reset),
      .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
     
     Converters cvt(.PPR(PPR),
     .P(P_AB),.Position(Position_AB));
     
     Converters cvy(.PPR(PPR),
     .P(P_CD),.Position(Position_CD));
    
     PWM_Generator pga(
     .reset(reset),
     .CLK(CLK_PWM),


     .Position(Position_AB),

     .pwm(PWM_AB)
         );

     PWM_Generator pgc(
     .reset(reset),
     .CLK(CLK_PWM),


     .Position(Position_CD),

     .pwm(PWM_CD)
         );    
    
    

    
   Rate_switch rsh(.reset(reset),
        .clk(clk),.R(R),.Rate_1(Rate));
          

   PPR_switch psh(.reset(reset),
         .clk(clk),
         .PR(PR),
      .PPR_1(PPR)
    );
 
      
    
endmodule
module E_TOP(
input reset,
input clk,
input [3:0]PR,
input[2:0] R,
input A,
input B,
input C,
input D,

output PWM_AB,
output PWM_CD
    );


reg CLK;
wire [23:0] Rate;
wire [9:0] PPR;
wire signed [9:0] P_AB;
wire signed [9:0] P_CD;
wire [9:0] Position_AB;
wire [9:0] Position_CD;








    encoder ecd(.reset(reset),
     .CLK(clk),.A(A),.B(B),.PPR(PPR),.P(P_AB));
     

     encoder ece(.reset(reset),
     .CLK(clk),.A(C),.B(D),.PPR(PPR),.P(P_CD));
     
     Clock cok(.reset(reset),
      .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
     
     Converters cvt(.PPR(PPR),
     .P(P_AB),.Position(Position_AB));
     
     Converters cvy(.PPR(PPR),
     .P(P_CD),.Position(Position_CD));
    
     PWM_Generator pga(
     .reset(reset),
     .CLK(CLK_PWM),


     .Position(Position_AB),

     .pwm(PWM_AB)
         );

     PWM_Generator pgc(
     .reset(reset),
     .CLK(CLK_PWM),


     .Position(Position_CD),

     .pwm(PWM_CD)
         );    
    
    

    
   Rate_switch rsh(.reset(reset),
        .clk(clk),.R(R),.Rate_1(Rate));
          

   PPR_switch psh(.reset(reset),
         .clk(clk),
         .PR(PR),
      .PPR_1(PPR)
    );
 
      
    
endmodule