data/full_repos/permissive/435108851/openlane/user_project_wrapper/src/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/435108851/openlane/user_project_wrapper/src/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435108851/openlane/user_project_wrapper/src/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435108851/openlane/user_project_wrapper/src/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435108851/openlane/user_project_wrapper/src/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





/

wire o_csb0;
wire o_web0;
wire [3:0] o_wmask0;
wire [8:0] o_waddr0;
wire [31:0]o_din0;
wire [31:0]i_dout0;

wire o_csb0_1;
wire o_web0_1;
wire [3:0] o_wmask0_1;
wire [8:0] o_waddr0_1;
wire [31:0]o_din0_1;
wire [31:0]i_dout0_1;

sky130_sram_2kbyte_1rw1r_32x512_8 sram (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wb_clk_i),
    .csb0   (o_csb0),
    .web0   (o_web0),
    .wmask0 (o_wmask0),
    .addr0  (o_waddr0),
    .din0   (o_din0),
    .dout0  (i_dout0),
    .clk1   (1'b0),
    .csb1   (1'b0),
    .addr1  (9'h0)
);

sky130_sram_2kbyte_1rw1r_32x512_8 sram1 (
    `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wb_clk_i),
    .csb0   (o_csb0_1),
    .web0   (o_web0_1),
    .wmask0 (o_wmask0_1),
    .addr0  (o_waddr0_1),
    .din0   (o_din0_1),
    .dout0  (i_dout0_1),
    .clk1   (1'b0),
    .csb1   (1'b0),
    .addr1  (9'h0)
);

user_proj mprj (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .clk_i(wb_clk_i),
    .rst_i(wb_rst_i),

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),


    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_dat_o(wbs_dat_o),


    .io_in(io_in),
    .io_out(io_out),
    .io_oeb(io_oeb),


    .irq(user_irq),


    .o_wmask0(o_wmask0),
    .o_waddr0(o_waddr0),
    .o_din0(o_din0),
    .i_dout0(i_dout0),
    .o_web0(o_web0),
    .o_csb0(o_csb0),


    .o_wmask0_1(o_wmask0_1),
    .o_waddr0_1(o_waddr0_1),
    .o_din0_1(o_din0_1),
    .i_dout0_1(i_dout0_1),
    .o_web0_1(o_web0_1),
    .o_csb0_1(o_csb0_1)
);

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);






/

wire o_csb0;
wire o_web0;
wire [3:0] o_wmask0;
wire [8:0] o_waddr0;
wire [31:0]o_din0;
wire [31:0]i_dout0;

wire o_csb0_1;
wire o_web0_1;
wire [3:0] o_wmask0_1;
wire [8:0] o_waddr0_1;
wire [31:0]o_din0_1;
wire [31:0]i_dout0_1;

sky130_sram_2kbyte_1rw1r_32x512_8 sram (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wb_clk_i),
    .csb0   (o_csb0),
    .web0   (o_web0),
    .wmask0 (o_wmask0),
    .addr0  (o_waddr0),
    .din0   (o_din0),
    .dout0  (i_dout0),
    .clk1   (1'b0),
    .csb1   (1'b0),
    .addr1  (9'h0)
);

sky130_sram_2kbyte_1rw1r_32x512_8 sram1 (
    `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wb_clk_i),
    .csb0   (o_csb0_1),
    .web0   (o_web0_1),
    .wmask0 (o_wmask0_1),
    .addr0  (o_waddr0_1),
    .din0   (o_din0_1),
    .dout0  (i_dout0_1),
    .clk1   (1'b0),
    .csb1   (1'b0),
    .addr1  (9'h0)
);

user_proj mprj (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif

    .clk_i(wb_clk_i),
    .rst_i(wb_rst_i),

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),


    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_dat_o(wbs_dat_o),


    .io_in(io_in),
    .io_out(io_out),
    .io_oeb(io_oeb),


    .irq(user_irq),


    .o_wmask0(o_wmask0),
    .o_waddr0(o_waddr0),
    .o_din0(o_din0),
    .i_dout0(i_dout0),
    .o_web0(o_web0),
    .o_csb0(o_csb0),


    .o_wmask0_1(o_wmask0_1),
    .o_waddr0_1(o_waddr0_1),
    .o_din0_1(o_din0_1),
    .i_dout0_1(i_dout0_1),
    .o_web0_1(o_web0_1),
    .o_csb0_1(o_csb0_1)
);

endmodule