data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:11: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Pcin = 32\'bz ; #1 Rd = 1 ; #1 Mem = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 Rd = 1 ; #2 Mem = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:19: Unsupported: Ignoring delay on this delayed statement.\n #3 Pcin = 32\'bz ; #3 Rd = 1 ; #3 Mem = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:21: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 Rd = 1 ; #4 Mem = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 Pcin = 32\'bz ; #5 Rd = 1 ; #5 Mem = 32\'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:25: Unsupported: Ignoring delay on this delayed statement.\n #6 Pcin = 32\'bz ; #6 Rd = 1 ; #6 Mem = 32\'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;\n                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:31: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:34: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("RegisterFileTestBench_nogenerate.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:35: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,RegisterFileTestBench_nogenerate);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/RegisterFile/RegisterFileTestBench_nogenerate.v:37: Unsupported or unknown PLI call: $monitor\n $monitor("time = %3d ,Pcin = %3d , Rd = %3d , Mem = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, Rd, Mem, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 44 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFileTestBench_nogenerate;

parameter sim_time = 750*2;

reg [31:0] Rd,Mem,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
RegisterFile_nogenerate RF(Rd,Mem,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork

	Clk = 0 ; RESET = 0 ; Pcin = 32'bz ; Rd = 32'bz ; Mem = 32'bz ; LOADPC = 0 ; LOAD = 0 ; IR_CU = 0 ; RSLCT = 0 ;

	#1 Pcin = 32'bz ; #1 Rd = 1 ; #1 Mem = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;

	#2 Pcin = 32'bz ; #2 Rd = 1 ; #2 Mem = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;

	#3 Pcin = 32'bz ; #3 Rd = 1 ; #3 Mem = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;

	#4 Pcin = 32'bz ; #4 Rd = 1 ; #4 Mem = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;

	#5 Pcin = 32'bz ; #5 Rd = 1 ; #5 Mem = 32'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;

	#6 Pcin = 32'bz ; #6 Rd = 1 ; #6 Mem = 32'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("RegisterFileTestBench_nogenerate.vcd");
	$dumpvars(0,RegisterFileTestBench_nogenerate);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , Rd = %3d , Mem = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, Rd, Mem, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end

endmodule
module RegisterFileTestBench_nogenerate;


parameter sim_time = 750*2;

reg [31:0] Rd,Mem,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
RegisterFile_nogenerate RF(Rd,Mem,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork

	Clk = 0 ; RESET = 0 ; Pcin = 32'bz ; Rd = 32'bz ; Mem = 32'bz ; LOADPC = 0 ; LOAD = 0 ; IR_CU = 0 ; RSLCT = 0 ;

	#1 Pcin = 32'bz ; #1 Rd = 1 ; #1 Mem = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;

	#2 Pcin = 32'bz ; #2 Rd = 1 ; #2 Mem = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;

	#3 Pcin = 32'bz ; #3 Rd = 1 ; #3 Mem = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;

	#4 Pcin = 32'bz ; #4 Rd = 1 ; #4 Mem = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;

	#5 Pcin = 32'bz ; #5 Rd = 1 ; #5 Mem = 32'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;

	#6 Pcin = 32'bz ; #6 Rd = 1 ; #6 Mem = 32'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("RegisterFileTestBench_nogenerate.vcd");
	$dumpvars(0,RegisterFileTestBench_nogenerate);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , Rd = %3d , Mem = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, Rd, Mem, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end

endmodule