data/full_repos/permissive/433621701/generic_RB_array/generic_RB_array.v
data/verilator_xmls/f286a25c-41cd-4fb2-9dca-4e8b4365cf08.xml
module tri_state(input a, enable, output reg out);
    always @(a or enable)
    begin
    if (enable == 0)
        out = 1'bz;        
    else
        out = a;
    end
endmodule
module tri_state(input a, enable, output reg out);

    always @(a or enable)
    begin
    if (enable == 0)
        out = 1'bz;        
    else
        out = a;
    end
endmodule