data/full_repos/permissive/430026064/PC_increment.v
data/verilator_xmls/9c9bd60d-d2ae-4f18-8637-593d581702d9.xml
module PC_increment(in1, out);
  	input [31:0] in1;
    output reg [31:0] out;
  
  	initial begin
      out = 0;
    end
	
  	always@(in1) begin
		out = in1 + 4;

	end
endmodule
module PC_increment(in1, out);

  	input [31:0] in1;
    output reg [31:0] out;
  
  	initial begin
      out = 0;
    end
	
  	always@(in1) begin
		out = in1 + 4;

	end
endmodule