data/full_repos/permissive/522095295/control.v
1: b'%Error: data/full_repos/permissive/522095295/control.v:1: Cannot find include file: itype.v\n`include "itype.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v.v\n             data/full_repos/permissive/522095295,data/full_repos/permissive/522095295/itype.v.sv\n             itype.v\n             itype.v.v\n             itype.v.sv\n             obj_dir/itype.v\n             obj_dir/itype.v.v\n             obj_dir/itype.v.sv\n%Error: data/full_repos/permissive/522095295/control.v:60: Define or directive not defined: \'`RTYPE\'\n            if (itype_i == `RTYPE) begin\n                           ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:60: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if (itype_i == `RTYPE) begin\n                                 ^\n%Error: data/full_repos/permissive/522095295/control.v:65: Define or directive not defined: \'`ITYPE\'\n            else if (itype_i == `ITYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            else if (itype_i == `ITYPE) begin\n                                      ^\n%Error: data/full_repos/permissive/522095295/control.v:70: Define or directive not defined: \'`STYPE\'\n            else if (itype_i == `STYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:70: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            else if (itype_i == `STYPE) begin\n                                      ^\n%Error: data/full_repos/permissive/522095295/control.v:75: syntax error, unexpected else\n            else if (itype_i == `BTYPE) begin\n            ^~~~\n%Error: data/full_repos/permissive/522095295/control.v:75: Define or directive not defined: \'`BTYPE\'\n            else if (itype_i == `BTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:80: Define or directive not defined: \'`UTYPE\'\n            else if (itype_i == `UTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:85: Define or directive not defined: \'`LTYPE\'\n            else if (itype_i == `LTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:90: Define or directive not defined: \'`JTYPE\'\n            else if (itype_i == `JTYPE) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:95: Define or directive not defined: \'`JRTYPE\'\n            else if (itype_i == `JRTYPE) begin\n                                ^~~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:114: Define or directive not defined: \'`RTYPE\'\n            if (itype_i == `RTYPE || itype_i == `ITYPE\n                           ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:114: Define or directive not defined: \'`ITYPE\'\n            if (itype_i == `RTYPE || itype_i == `ITYPE\n                                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:115: Define or directive not defined: \'`UTYPE\'\n               || itype_i == `UTYPE || itype_i == `LTYPE\n                             ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:115: Define or directive not defined: \'`LTYPE\'\n               || itype_i == `UTYPE || itype_i == `LTYPE\n                                                  ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:116: Define or directive not defined: \'`JTYPE\'\n               || itype_i == `JTYPE ||  itype_i == `JRTYPE) begin\n                             ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:116: Define or directive not defined: \'`JRTYPE\'\n               || itype_i == `JTYPE ||  itype_i == `JRTYPE) begin\n                                                   ^~~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:119: Define or directive not defined: \'`STYPE\'\n            if (itype_i == `STYPE) begin\n                           ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:127: Define or directive not defined: \'`RTYPE\'\n            if (itype_i == `RTYPE || itype_i == `ITYPE\n                           ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:127: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n            if (itype_i == `RTYPE || itype_i == `ITYPE\n                                  ^~\n%Error: data/full_repos/permissive/522095295/control.v:127: Define or directive not defined: \'`ITYPE\'\n            if (itype_i == `RTYPE || itype_i == `ITYPE\n                                                ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:128: Define or directive not defined: \'`UTYPE\'\n               || itype_i == `UTYPE || itype_i == `LTYPE\n                             ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:128: Define or directive not defined: \'`LTYPE\'\n               || itype_i == `UTYPE || itype_i == `LTYPE\n                                                  ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:129: Define or directive not defined: \'`UPCTYPE\'\n               || itype_i == `UPCTYPE || itype_i == `JTYPE\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:129: Define or directive not defined: \'`JTYPE\'\n               || itype_i == `UPCTYPE || itype_i == `JTYPE\n                                                    ^~~~~~\n%Error: data/full_repos/permissive/522095295/control.v:130: Define or directive not defined: \'`JRTYPE\'\n               || itype_i == `JRTYPE) begin\n                             ^~~~~~~\n%Error: Cannot continue\n'
module control
(
   input wire clk, 
   input wire reset,
   output wire [2:0] stage_o,

   output reg we_o,
   output reg [31:0] addr_o,
   input wire [31:0] data_i,

   output reg pc_readin_o,
   input wire [31:0] pc_i,

   output wire [31:0] ir_o,

   output reg readin_a_o,
   output reg readin_b_o,
   output reg readin_pass_o,
   input wire [4:0] itype_i,

   output reg mem_we_o,

   output reg wd_q_o,
   output reg wd_q_readin_o
);

   reg [31:0] ir; 
   assign ir_o = ir;


   reg ir_readin_o;


   counter stage (
           .clk (clk),
           .reset (reset),
           .out (stage_o));
   
   always @ (posedge ir_readin_o) begin
      ir = data_i;
   end

   always @ (posedge clk) begin
      if (!reset) begin
         if(stage_o == 1) begin
            wd_q_readin_o <= 0;
            wd_q_o <= 0;


            pc_readin_o <= 0;
            addr_o <= pc_i;
            ir_readin_o <= 1;
         end
         else if(stage_o == 2) begin

            ir_readin_o <= 0;

            if (itype_i == `RTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `ITYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `STYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 1;
            end
            else if (itype_i == `BTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 1;
            end
            else if (itype_i == `UTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else if (itype_i == `LTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `JTYPE) begin
               readin_a_o <= 0;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else if (itype_i == `JRTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else begin
               readin_a_o <= 0;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
         end
         else if(stage_o == 3) begin

            readin_a_o <= 0;
            readin_b_o <= 0;
            readin_pass_o <= 0;
         end
         else if(stage_o == 4) begin

            if (itype_i == `RTYPE || itype_i == `ITYPE
               || itype_i == `UTYPE || itype_i == `LTYPE
               || itype_i == `JTYPE ||  itype_i == `JRTYPE) begin
               wd_q_readin_o <= 1;
            end
            if (itype_i == `STYPE) begin
               mem_we_o <= 1;
            end
         end
         else if(stage_o == 5) begin
            mem_we_o <= 0;
            wd_q_readin_o <= 0;

            if (itype_i == `RTYPE || itype_i == `ITYPE
               || itype_i == `UTYPE || itype_i == `LTYPE
               || itype_i == `UPCTYPE || itype_i == `JTYPE
               || itype_i == `JRTYPE) begin
               wd_q_o <= 1;
            end
   
            pc_readin_o <= 1;
         end
      end
   end

   always @ (reset) begin
      we_o <= 0;
      addr_o <= 0;
      pc_readin_o = 1;
      ir_readin_o = 0;
      ir = 0;
      addr_o = 0;
      readin_a_o = 0;
      readin_b_o = 0;
      readin_pass_o = 0;
      wd_q_o = 0;
      wd_q_readin_o = 0;
      mem_we_o = 0;
   end

   initial begin
      pc_readin_o = 1;
      ir_readin_o = 0;
      ir = 0;
      addr_o = 0;
      readin_a_o = 0;
      readin_b_o = 0;
      readin_pass_o = 0;
      wd_q_o = 0;
      wd_q_readin_o = 0;
      mem_we_o = 0;
   end
endmodule
module control
(
   input wire clk, 
   input wire reset,
   output wire [2:0] stage_o,

   output reg we_o,
   output reg [31:0] addr_o,
   input wire [31:0] data_i,

   output reg pc_readin_o,
   input wire [31:0] pc_i,

   output wire [31:0] ir_o,

   output reg readin_a_o,
   output reg readin_b_o,
   output reg readin_pass_o,
   input wire [4:0] itype_i,

   output reg mem_we_o,

   output reg wd_q_o,
   output reg wd_q_readin_o
);


   reg [31:0] ir; 
   assign ir_o = ir;


   reg ir_readin_o;


   counter stage (
           .clk (clk),
           .reset (reset),
           .out (stage_o));
   
   always @ (posedge ir_readin_o) begin
      ir = data_i;
   end

   always @ (posedge clk) begin
      if (!reset) begin
         if(stage_o == 1) begin
            wd_q_readin_o <= 0;
            wd_q_o <= 0;


            pc_readin_o <= 0;
            addr_o <= pc_i;
            ir_readin_o <= 1;
         end
         else if(stage_o == 2) begin

            ir_readin_o <= 0;

            if (itype_i == `RTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `ITYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `STYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 1;
            end
            else if (itype_i == `BTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 1;
            end
            else if (itype_i == `UTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else if (itype_i == `LTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 1;
               readin_pass_o <= 0;
            end
            else if (itype_i == `JTYPE) begin
               readin_a_o <= 0;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else if (itype_i == `JRTYPE) begin
               readin_a_o <= 1;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
            else begin
               readin_a_o <= 0;
               readin_b_o <= 0;
               readin_pass_o <= 0;
            end
         end
         else if(stage_o == 3) begin

            readin_a_o <= 0;
            readin_b_o <= 0;
            readin_pass_o <= 0;
         end
         else if(stage_o == 4) begin

            if (itype_i == `RTYPE || itype_i == `ITYPE
               || itype_i == `UTYPE || itype_i == `LTYPE
               || itype_i == `JTYPE ||  itype_i == `JRTYPE) begin
               wd_q_readin_o <= 1;
            end
            if (itype_i == `STYPE) begin
               mem_we_o <= 1;
            end
         end
         else if(stage_o == 5) begin
            mem_we_o <= 0;
            wd_q_readin_o <= 0;

            if (itype_i == `RTYPE || itype_i == `ITYPE
               || itype_i == `UTYPE || itype_i == `LTYPE
               || itype_i == `UPCTYPE || itype_i == `JTYPE
               || itype_i == `JRTYPE) begin
               wd_q_o <= 1;
            end
   
            pc_readin_o <= 1;
         end
      end
   end

   always @ (reset) begin
      we_o <= 0;
      addr_o <= 0;
      pc_readin_o = 1;
      ir_readin_o = 0;
      ir = 0;
      addr_o = 0;
      readin_a_o = 0;
      readin_b_o = 0;
      readin_pass_o = 0;
      wd_q_o = 0;
      wd_q_readin_o = 0;
      mem_we_o = 0;
   end

   initial begin
      pc_readin_o = 1;
      ir_readin_o = 0;
      ir = 0;
      addr_o = 0;
      readin_a_o = 0;
      readin_b_o = 0;
      readin_pass_o = 0;
      wd_q_o = 0;
      wd_q_readin_o = 0;
      mem_we_o = 0;
   end
endmodule