data/full_repos/permissive/50700015/spl2_write_through/spl_csr.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/50700015/spl2_write_through/spl_csr.v:94: Unsupported: Ignoring delay on this delayed statement.\n                            assert (io_rx_csr_data[31:6] == 26\'b0) else #100ns $fatal("spl_dsr_baseh = %x is out of 256GB range", io_rx_csr_data);\n                                                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spl_csr(
    input  wire                             clk,
    input  wire                             reset_n,
    

    output reg                              csr_enable,
    output reg                              csr_reset,
            

    output reg                              csr_cfg_valid,
    output reg  [13:0]                      csr_cfg_addr,
    output reg  [31:0]                      csr_cfg_data,
    output wire                             csr_afu_cfg_valid,
 

    output reg                              csr_dsr_base_valid,
    output reg  [31:0]                      csr_dsr_base,
    

    output reg                              csr_ctx_base_valid,
    output reg  [31:0]                      csr_ctx_base,
        

    input  wire                             io_rx_csr_valid,
    input  wire [13:0]                      io_rx_csr_addr,
    input  wire [31:0]                      io_rx_csr_data
);


    localparam [5:0]
        SPL_CSR_DSR_BASEL          = 6'b00_0000,
        SPL_CSR_DSR_BASEH          = 6'b00_0001,
        SPL_CSR_CTX_BASELL         = 6'b00_0010,
        SPL_CSR_CTX_BASELH         = 6'b00_0011,
        SPL_CSR_CTRL               = 6'b00_0100,
        SPL_CSR_SCRATCH            = 6'b11_1111;
                
    localparam [5:0]
        SPL_DSR_ID                  = 6'h0;      
    
    reg  [5:0]                     spl_dsr_base_hi;
    
    



    always @(posedge clk) begin
        if ((~reset_n) | csr_reset) begin
            csr_reset <= 1'b0;
            csr_enable <= 1'b0;
            csr_dsr_base_valid <= 1'b0;
            csr_ctx_base_valid <= 1'b0;
            csr_cfg_valid <= 1'b0;
        end 
        
        else begin
            csr_reset <= 1'b0;               
            csr_cfg_valid <= 1'b0;                              
                                               
            if (io_rx_csr_valid) begin
                if (io_rx_csr_addr[13:6] == 8'h10) begin
                    case (io_rx_csr_addr[5:0]) 
                        SPL_CSR_DSR_BASEH : begin                
                            spl_dsr_base_hi <= io_rx_csr_data[5:0];  
                            

                            assert (io_rx_csr_data[31:6] == 26'b0) else #100ns $fatal("spl_dsr_baseh = %x is out of 256GB range", io_rx_csr_data);

                        end

                        SPL_CSR_DSR_BASEL : begin                
                            csr_dsr_base_valid <= 1'b1;
                            csr_dsr_base <= {spl_dsr_base_hi, io_rx_csr_data[31:6]};
                            

                            assert (io_rx_csr_data[5:0] == 6'b0) else $fatal("spl_dsr_basel = %x is not CL aligned", io_rx_csr_data);

                        end

                        SPL_CSR_CTX_BASELH : begin                
                            csr_ctx_base[31:26] <= io_rx_csr_data[5:0];
                            

                            assert (io_rx_csr_data[31:6] == 26'b0) else $fatal("csr_ctx_baseh = %x is out of 256GB range", io_rx_csr_data);

                        end

                        SPL_CSR_CTX_BASELL : begin                
                            csr_ctx_base[25:0] <= io_rx_csr_data[31:6];                            
                            csr_ctx_base_valid <= 1'b1;
                            

                            assert (io_rx_csr_data[5:0] == 6'b0) else $fatal("csr_ctx_base = %x is not CL aligned", io_rx_csr_data);

                        end
                        
                        SPL_CSR_CTRL : begin                
                            csr_reset <= io_rx_csr_data[0];
                            csr_enable <= io_rx_csr_data[1];
                        end          
                    endcase
                end
                
                else begin
                    csr_cfg_valid <= 1'b1;
                    csr_cfg_addr <= io_rx_csr_addr;
                    csr_cfg_data <= io_rx_csr_data;
                end
            end
        end
    end

    assign csr_afu_cfg_valid = io_rx_csr_valid & (io_rx_csr_addr[13:6] != 8'h10);

endmodule
module spl_csr(
    input  wire                             clk,
    input  wire                             reset_n,
    

    output reg                              csr_enable,
    output reg                              csr_reset,
            

    output reg                              csr_cfg_valid,
    output reg  [13:0]                      csr_cfg_addr,
    output reg  [31:0]                      csr_cfg_data,
    output wire                             csr_afu_cfg_valid,
 

    output reg                              csr_dsr_base_valid,
    output reg  [31:0]                      csr_dsr_base,
    

    output reg                              csr_ctx_base_valid,
    output reg  [31:0]                      csr_ctx_base,
        

    input  wire                             io_rx_csr_valid,
    input  wire [13:0]                      io_rx_csr_addr,
    input  wire [31:0]                      io_rx_csr_data
);



    localparam [5:0]
        SPL_CSR_DSR_BASEL          = 6'b00_0000,
        SPL_CSR_DSR_BASEH          = 6'b00_0001,
        SPL_CSR_CTX_BASELL         = 6'b00_0010,
        SPL_CSR_CTX_BASELH         = 6'b00_0011,
        SPL_CSR_CTRL               = 6'b00_0100,
        SPL_CSR_SCRATCH            = 6'b11_1111;
                
    localparam [5:0]
        SPL_DSR_ID                  = 6'h0;      
    
    reg  [5:0]                     spl_dsr_base_hi;
    
    



    always @(posedge clk) begin
        if ((~reset_n) | csr_reset) begin
            csr_reset <= 1'b0;
            csr_enable <= 1'b0;
            csr_dsr_base_valid <= 1'b0;
            csr_ctx_base_valid <= 1'b0;
            csr_cfg_valid <= 1'b0;
        end 
        
        else begin
            csr_reset <= 1'b0;               
            csr_cfg_valid <= 1'b0;                              
                                               
            if (io_rx_csr_valid) begin
                if (io_rx_csr_addr[13:6] == 8'h10) begin
                    case (io_rx_csr_addr[5:0]) 
                        SPL_CSR_DSR_BASEH : begin                
                            spl_dsr_base_hi <= io_rx_csr_data[5:0];  
                            

                            assert (io_rx_csr_data[31:6] == 26'b0) else #100ns $fatal("spl_dsr_baseh = %x is out of 256GB range", io_rx_csr_data);

                        end

                        SPL_CSR_DSR_BASEL : begin                
                            csr_dsr_base_valid <= 1'b1;
                            csr_dsr_base <= {spl_dsr_base_hi, io_rx_csr_data[31:6]};
                            

                            assert (io_rx_csr_data[5:0] == 6'b0) else $fatal("spl_dsr_basel = %x is not CL aligned", io_rx_csr_data);

                        end

                        SPL_CSR_CTX_BASELH : begin                
                            csr_ctx_base[31:26] <= io_rx_csr_data[5:0];
                            

                            assert (io_rx_csr_data[31:6] == 26'b0) else $fatal("csr_ctx_baseh = %x is out of 256GB range", io_rx_csr_data);

                        end

                        SPL_CSR_CTX_BASELL : begin                
                            csr_ctx_base[25:0] <= io_rx_csr_data[31:6];                            
                            csr_ctx_base_valid <= 1'b1;
                            

                            assert (io_rx_csr_data[5:0] == 6'b0) else $fatal("csr_ctx_base = %x is not CL aligned", io_rx_csr_data);

                        end
                        
                        SPL_CSR_CTRL : begin                
                            csr_reset <= io_rx_csr_data[0];
                            csr_enable <= io_rx_csr_data[1];
                        end          
                    endcase
                end
                
                else begin
                    csr_cfg_valid <= 1'b1;
                    csr_cfg_addr <= io_rx_csr_addr;
                    csr_cfg_data <= io_rx_csr_data;
                end
            end
        end
    end

    assign csr_afu_cfg_valid = io_rx_csr_valid & (io_rx_csr_addr[13:6] != 8'h10);

endmodule