data/full_repos/permissive/504677412/src/functions.v
1: b'%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'g\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:27: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n      y  = 16\'d16  + (((r<<6)+(r<<1)+(g<<7)+g+(b<<4)+(b<<3)+b)>>8);\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:28: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      cb = 16\'d128 + ((-((r<<5)+(r<<2)+(r<<1))-((g<<6)+(g<<3)+(g<<1))+(b<<7)-(b<<4))>>8);\n                                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'r\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'g\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/504677412/src/functions.v:29: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'b\' generates 8 bits.\n      cr = 16\'d128 + (((r<<7)-(r<<4)-((g<<6)+(g<<5)-(g<<1))-((b<<4)+(b<<1)))>>8);\n                                                                      ^~\n%Error: Exiting due to 22 warning(s)\n'
function [23:0] ycbcr422torgb888;
    input [7:0] y, cb, cr;
    reg   [7:0] r, g, b, cb_minus_128, cr_minus_128;
    begin


      cb_minus_128 = cb - 128;
      cr_minus_128 = cr - 128;
      

      r = y+cr_minus_128+(cr_minus_128>>2)+(cr_minus_128>>3)+(cr_minus_128>>5);
      g = y-((cb_minus_128>>2)+(cb_minus_128>>4)+(cb_minus_128>>5))-((cr_minus_128>>1)+(cr_minus_128>>3)+(cr_minus_128>>4)+(cr_minus_128>>5));
      b = y+cb_minus_128+(cb_minus_128>>1)+(cb_minus_128>>2)+(cb_minus_128>>6);
      
      ycbcr422torgb888 = {r,g,b};
    end
  endfunction
function [23:0] ycbcr422torgb888;

    input [7:0] y, cb, cr;
    reg   [7:0] r, g, b, cb_minus_128, cr_minus_128;
    begin


      cb_minus_128 = cb - 128;
      cr_minus_128 = cr - 128;
      

      r = y+cr_minus_128+(cr_minus_128>>2)+(cr_minus_128>>3)+(cr_minus_128>>5);
      g = y-((cb_minus_128>>2)+(cb_minus_128>>4)+(cb_minus_128>>5))-((cr_minus_128>>1)+(cr_minus_128>>3)+(cr_minus_128>>4)+(cr_minus_128>>5));
      b = y+cb_minus_128+(cb_minus_128>>1)+(cb_minus_128>>2)+(cb_minus_128>>6);
      
      ycbcr422torgb888 = {r,g,b};
    end
  endfunction