data/full_repos/permissive/521867481/src/Uart8.v
1: b'%Error: data/full_repos/permissive/521867481/src/Uart8.v:4: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/src,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:5: Cannot find include file: src/BaudRateGenerator.v\n`include "src/BaudRateGenerator.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:6: Cannot find include file: src/Uart8Receiver.v\n`include "src/Uart8Receiver.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:7: Cannot find include file: src/Uart8Transmitter.v\n`include "src/Uart8Transmitter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:10: Define or directive not defined: \'`CLOCK_RATE_100MHZ\'\n        parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ,  \n                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:10: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ,  \n                                                   ^\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:11: Define or directive not defined: \'`BAUD_RATE_115200\'\n        parameter BAUD_RATE    = `BAUD_RATE_115200,   \n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:11: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        parameter BAUD_RATE    = `BAUD_RATE_115200,   \n                                                  ^\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:12: Define or directive not defined: \'`OVERSAMPLING_16\'\n        parameter OVERSAMPLING = `OVERSAMPLING_16,    \n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:12: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        parameter OVERSAMPLING = `OVERSAMPLING_16,    \n                                                 ^\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:13: Define or directive not defined: \'`DATA_BITS_8\'\n        parameter DATA_BITS    = `DATA_BITS_8         \n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:14: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )(\n    ^\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire rx,\n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire rxEn,\n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire [DATA_BITS - 1:0] out,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire rxDone,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire rxBusy,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire rxErr,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire tx,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire txEn,\n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire txStart,\n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire [DATA_BITS - 1:0] in,\n        ^~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire txDone,\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire txBusy\n        ^~~~~~\n%Error: data/full_repos/permissive/521867481/src/Uart8.v:37: syntax error, unexpected IDENTIFIER\n    BaudRateGenerator #(\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module Uart8 #(
        parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ,
        parameter BAUD_RATE    = `BAUD_RATE_115200,
        parameter OVERSAMPLING = `OVERSAMPLING_16,
        parameter DATA_BITS    = `DATA_BITS_8
    )(
        input wire clk,


        input wire rx,
        input wire rxEn,
        output wire [DATA_BITS - 1:0] out,
        output wire rxDone,
        output wire rxBusy,
        output wire rxErr,


        output wire tx,
        input wire txEn,
        input wire txStart,
        input wire [DATA_BITS - 1:0] in,
        output wire txDone,
        output wire txBusy
    );

    wire rxClk;
    wire txClk;

    BaudRateGenerator #(
        .CLOCK_RATE(CLOCK_RATE),
        .BAUD_RATE(BAUD_RATE),
        .OVERSAMPLING(OVERSAMPLING)
    ) generatorInst (
        .clk(clk),
        .rxClk(rxClk),
        .txClk(txClk)
    );

    Uart8Receiver #(
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
    ) rxInst (
        .clk(rxClk),
        .en(rxEn),
        .in(rx),
        .out(out),
        .done(rxDone),
        .busy(rxBusy),
        .err(rxErr)
    );

    Uart8Transmitter #(
        .DATA_BITS(DATA_BITS)
    ) txInst (
        .clk(txClk),
        .en(txEn),
        .start(txStart),
        .in(in),
        .out(tx),
        .done(txDone),
        .busy(txBusy)
    );

endmodule
module Uart8 #(
        parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ,
        parameter BAUD_RATE    = `BAUD_RATE_115200,
        parameter OVERSAMPLING = `OVERSAMPLING_16,
        parameter DATA_BITS    = `DATA_BITS_8
    )(
        input wire clk,


        input wire rx,
        input wire rxEn,
        output wire [DATA_BITS - 1:0] out,
        output wire rxDone,
        output wire rxBusy,
        output wire rxErr,


        output wire tx,
        input wire txEn,
        input wire txStart,
        input wire [DATA_BITS - 1:0] in,
        output wire txDone,
        output wire txBusy
    );


    wire rxClk;
    wire txClk;

    BaudRateGenerator #(
        .CLOCK_RATE(CLOCK_RATE),
        .BAUD_RATE(BAUD_RATE),
        .OVERSAMPLING(OVERSAMPLING)
    ) generatorInst (
        .clk(clk),
        .rxClk(rxClk),
        .txClk(txClk)
    );

    Uart8Receiver #(
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
    ) rxInst (
        .clk(rxClk),
        .en(rxEn),
        .in(rx),
        .out(out),
        .done(rxDone),
        .busy(rxBusy),
        .err(rxErr)
    );

    Uart8Transmitter #(
        .DATA_BITS(DATA_BITS)
    ) txInst (
        .clk(txClk),
        .en(txEn),
        .start(txStart),
        .in(in),
        .out(tx),
        .done(txDone),
        .busy(txBusy)
    );

endmodule