data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:31: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:56: Define or directive not defined: \'`PCX_WIDTH\'\n              output [`PCX_WIDTH-1:0]  pcx_scache1_data_px_l;   \n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:70: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc0_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:71: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc1_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:72: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc2_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:73: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc3_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:74: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc4_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:75: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc5_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:76: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc6_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:77: Define or directive not defined: \'`PCX_WIDTH\'\n              input [`PCX_WIDTH-1:0]   spc7_pcx_data_pa;        \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:143: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:179: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:195: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:223: Define or directive not defined: \'`PCX_WIDTH\'\n        .data_out_px_l ({unused[5:0],pcx_scache1_data_px_l[`PCX_WIDTH-1:0]}),  \n                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:232: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:272: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:288: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:304: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp1.v:341: Define or directive not defined: \'`PCX_WIDTH\'\n        .src_pcx_data_pa ({6\'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}),  \n                                                      ^~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module pcx_dp1(

   scan_out, pcx_scache1_data_px_l, 

   shiftenable, scan_in, rclk, arbpc1_pcxdp_shift_px, 
   arbpc1_pcxdp_qsel1_pa, arbpc1_pcxdp_qsel0_pa, 
   arbpc1_pcxdp_q0_hold_pa, arbpc1_pcxdp_grant_pa, spc0_pcx_data_pa, 
   spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa, 
   spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa, 
   spc7_pcx_data_pa
   );	




	      output [7:0]    scan_out;

   
              output [`PCX_WIDTH-1:0]  pcx_scache1_data_px_l;



	      input [7:0]     arbpc1_pcxdp_grant_pa;
	      input [7:0]     arbpc1_pcxdp_q0_hold_pa;
	      input [7:0]     arbpc1_pcxdp_qsel0_pa;
	      input [7:0]     arbpc1_pcxdp_qsel1_pa;
	      input [7:0]     arbpc1_pcxdp_shift_px;
	      input	      rclk;
	      input [7:0]     scan_in;
	      input	      shiftenable;


              input [`PCX_WIDTH-1:0]   spc0_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc1_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc2_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc3_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc4_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc5_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc6_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc7_pcx_data_pa;




	      wire [129:0]    pcx_col0_data_px_l;
	      wire [129:0]    pcx_col1_data_px_l;
	      wire [129:0]    pcx_col2_data_px_l;
	      wire [129:0]    pcx_col4_data_px_l;
	      wire [129:0]    pcx_col5_data_px_l;
	      wire [129:0]    pcx_col6_data_px_l;
	      wire [129:0]    pcx_col7_data_px_l;
	      wire [7:1]      shiftenable_buf;

   
              wire [5:0]      unused;







   pcx_dp_maca_r mac0(

		      .data_out_px_l	(pcx_col0_data_px_l[129:0]),
		      .scan_out		(scan_out[0]),
		      .shiftenable_buf	(),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[0]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[0]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[0]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[0]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[0]),
		      .src_pcx_data_pa	({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .rclk		(rclk),
		      .scan_in		(scan_in[0]),
		      .shiftenable	(shiftenable_buf[1]));

   pcx_dp_macb_r mac1(

		      .data_out_px_l	(pcx_col1_data_px_l[129:0]),
		      .scan_out		(scan_out[1]),
		      .shiftenable_buf	(shiftenable_buf[1]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[1]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[1]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[1]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[1]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[1]),
		      .src_pcx_data_pa	({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col0_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[1]),
		      .shiftenable	(shiftenable_buf[2]));
   pcx_dp_macb_r mac2(

		      .data_out_px_l	(pcx_col2_data_px_l[129:0]),
		      .scan_out		(scan_out[2]),
		      .shiftenable_buf	(shiftenable_buf[2]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[2]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[2]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[2]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[2]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[2]),
		      .src_pcx_data_pa	({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col1_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[2]),
		      .shiftenable	(shiftenable_buf[3]));

   pcx_dp_macc_r mac3(

		      .data_out_px_l	({unused[5:0],pcx_scache1_data_px_l[`PCX_WIDTH-1:0]}),
		      .scan_out		(scan_out[3]),
		      .shiftenable_buf	(shiftenable_buf[3]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[3]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[3]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[3]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[3]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[3]),
		      .src_pcx_data_pa	({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_crit_px_l	(pcx_col4_data_px_l[129:0]),
		      .data_ncrit_px_l	(pcx_col2_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[3]),
		      .shiftenable	(shiftenable_buf[4]));



   pcx_dp_macb_l mac4(

		      .data_out_px_l	(pcx_col4_data_px_l[129:0]),
		      .scan_out		(scan_out[4]),
		      .shiftenable_buf	(shiftenable_buf[4]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[4]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[4]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[4]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[4]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[4]),
		      .src_pcx_data_pa	({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col5_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[4]),
		      .shiftenable	(shiftenable_buf[5]));
   pcx_dp_macb_l mac5(

		      .data_out_px_l	(pcx_col5_data_px_l[129:0]),
		      .scan_out		(scan_out[5]),
		      .shiftenable_buf	(shiftenable_buf[5]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[5]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[5]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[5]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[5]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[5]),
		      .src_pcx_data_pa	({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col6_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[5]),
		      .shiftenable	(shiftenable_buf[6]));
   pcx_dp_macb_l mac6(

		      .data_out_px_l	(pcx_col6_data_px_l[129:0]),
		      .scan_out		(scan_out[6]),
		      .shiftenable_buf	(shiftenable_buf[6]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[6]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[6]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[6]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[6]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[6]),
		      .src_pcx_data_pa	({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col7_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[6]),
		      .shiftenable	(shiftenable_buf[7]));


   pcx_dp_maca_l mac7(

		      .data_out_px_l	(pcx_col7_data_px_l[129:0]),
		      .scan_out		(scan_out[7]),
		      .shiftenable_buf	(shiftenable_buf[7]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7]),
		      .src_pcx_data_pa	({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .rclk		(rclk),
		      .scan_in		(scan_in[7]),
		      .shiftenable	(shiftenable));








endmodule
module pcx_dp1(

   scan_out, pcx_scache1_data_px_l, 

   shiftenable, scan_in, rclk, arbpc1_pcxdp_shift_px, 
   arbpc1_pcxdp_qsel1_pa, arbpc1_pcxdp_qsel0_pa, 
   arbpc1_pcxdp_q0_hold_pa, arbpc1_pcxdp_grant_pa, spc0_pcx_data_pa, 
   spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa, 
   spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa, 
   spc7_pcx_data_pa
   );
	




	      output [7:0]    scan_out;

   
              output [`PCX_WIDTH-1:0]  pcx_scache1_data_px_l;



	      input [7:0]     arbpc1_pcxdp_grant_pa;
	      input [7:0]     arbpc1_pcxdp_q0_hold_pa;
	      input [7:0]     arbpc1_pcxdp_qsel0_pa;
	      input [7:0]     arbpc1_pcxdp_qsel1_pa;
	      input [7:0]     arbpc1_pcxdp_shift_px;
	      input	      rclk;
	      input [7:0]     scan_in;
	      input	      shiftenable;


              input [`PCX_WIDTH-1:0]   spc0_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc1_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc2_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc3_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc4_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc5_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc6_pcx_data_pa;
              input [`PCX_WIDTH-1:0]   spc7_pcx_data_pa;




	      wire [129:0]    pcx_col0_data_px_l;
	      wire [129:0]    pcx_col1_data_px_l;
	      wire [129:0]    pcx_col2_data_px_l;
	      wire [129:0]    pcx_col4_data_px_l;
	      wire [129:0]    pcx_col5_data_px_l;
	      wire [129:0]    pcx_col6_data_px_l;
	      wire [129:0]    pcx_col7_data_px_l;
	      wire [7:1]      shiftenable_buf;

   
              wire [5:0]      unused;







   pcx_dp_maca_r mac0(

		      .data_out_px_l	(pcx_col0_data_px_l[129:0]),
		      .scan_out		(scan_out[0]),
		      .shiftenable_buf	(),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[0]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[0]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[0]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[0]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[0]),
		      .src_pcx_data_pa	({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .rclk		(rclk),
		      .scan_in		(scan_in[0]),
		      .shiftenable	(shiftenable_buf[1]));

   pcx_dp_macb_r mac1(

		      .data_out_px_l	(pcx_col1_data_px_l[129:0]),
		      .scan_out		(scan_out[1]),
		      .shiftenable_buf	(shiftenable_buf[1]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[1]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[1]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[1]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[1]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[1]),
		      .src_pcx_data_pa	({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col0_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[1]),
		      .shiftenable	(shiftenable_buf[2]));
   pcx_dp_macb_r mac2(

		      .data_out_px_l	(pcx_col2_data_px_l[129:0]),
		      .scan_out		(scan_out[2]),
		      .shiftenable_buf	(shiftenable_buf[2]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[2]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[2]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[2]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[2]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[2]),
		      .src_pcx_data_pa	({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col1_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[2]),
		      .shiftenable	(shiftenable_buf[3]));

   pcx_dp_macc_r mac3(

		      .data_out_px_l	({unused[5:0],pcx_scache1_data_px_l[`PCX_WIDTH-1:0]}),
		      .scan_out		(scan_out[3]),
		      .shiftenable_buf	(shiftenable_buf[3]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[3]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[3]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[3]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[3]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[3]),
		      .src_pcx_data_pa	({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_crit_px_l	(pcx_col4_data_px_l[129:0]),
		      .data_ncrit_px_l	(pcx_col2_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[3]),
		      .shiftenable	(shiftenable_buf[4]));



   pcx_dp_macb_l mac4(

		      .data_out_px_l	(pcx_col4_data_px_l[129:0]),
		      .scan_out		(scan_out[4]),
		      .shiftenable_buf	(shiftenable_buf[4]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[4]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[4]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[4]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[4]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[4]),
		      .src_pcx_data_pa	({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col5_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[4]),
		      .shiftenable	(shiftenable_buf[5]));
   pcx_dp_macb_l mac5(

		      .data_out_px_l	(pcx_col5_data_px_l[129:0]),
		      .scan_out		(scan_out[5]),
		      .shiftenable_buf	(shiftenable_buf[5]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[5]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[5]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[5]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[5]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[5]),
		      .src_pcx_data_pa	({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col6_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[5]),
		      .shiftenable	(shiftenable_buf[6]));
   pcx_dp_macb_l mac6(

		      .data_out_px_l	(pcx_col6_data_px_l[129:0]),
		      .scan_out		(scan_out[6]),
		      .shiftenable_buf	(shiftenable_buf[6]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[6]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[6]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[6]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[6]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[6]),
		      .src_pcx_data_pa	({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .data_prev_px_l	(pcx_col7_data_px_l[129:0]),
		      .rclk		(rclk),
		      .scan_in		(scan_in[6]),
		      .shiftenable	(shiftenable_buf[7]));


   pcx_dp_maca_l mac7(

		      .data_out_px_l	(pcx_col7_data_px_l[129:0]),
		      .scan_out		(scan_out[7]),
		      .shiftenable_buf	(shiftenable_buf[7]),

		      .arb_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7]),
		      .arb_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7]),
		      .arb_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7]),
		      .arb_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7]),
		      .arb_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7]),
		      .src_pcx_data_pa	({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}),
		      .rclk		(rclk),
		      .scan_in		(scan_in[7]),
		      .shiftenable	(shiftenable));








endmodule