data/full_repos/permissive/525152535/ROM16.v
data/verilator_xmls/2dd2bd67-2bd3-4998-9255-71d3805e909d.xml
module ROM16
#(
    parameter [15:0] INIT_0 = 16'h0
)
(
    input  [3:0] AD,
    output       DO
);

    reg [15:0] _r_mem;
    
    initial begin
    
        _r_mem = INIT_0;
    end
    
    assign DO = _r_mem[AD];

endmodule
module ROM16
#(
    parameter [15:0] INIT_0 = 16'h0
)
(
    input  [3:0] AD,
    output       DO
);


    reg [15:0] _r_mem;
    
    initial begin
    
        _r_mem = INIT_0;
    end
    
    assign DO = _r_mem[AD];

endmodule