data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/matrix_mult/test/matrixMultSeqTest.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/matrix_mult/test/matrixMultSeqTest.v:34: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/matrix_mult/test/matrixMultSeqTest.v:39: Unsupported or unknown PLI call: $monitor\n    $monitor($time,"o = %x",o); \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/matrix_mult/test/matrixMultSeqTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module matrixMultSeqTest();

	parameter N=3;
	parameter M=32;
	reg clk, rst;
	
	reg[M*N*N-1:0] x;
	reg[M*N*N-1:0] y;
	wire[M*N*N-1:0] o;


	matrixMultSeq 
	#(
	.N(N),
	.M(M)
	)
	UTT
	(
		.clk(clk),
		.x(x),
		.y(y),
		.o(o)
	);

  integer i;
	initial
	begin
		clk=0;
	  x = {N*N*M/32{$random}};
	  y = {N*N*M/32{$random}};
		for(i=0;i<N*N*N;i=i+1)
			@(negedge clk);
		$stop;
	end

  initial 
    $monitor($time,"o = %x",o); 

	always #5 clk = !clk;
endmodule
module matrixMultSeqTest();


	parameter N=3;
	parameter M=32;
	reg clk, rst;
	
	reg[M*N*N-1:0] x;
	reg[M*N*N-1:0] y;
	wire[M*N*N-1:0] o;


	matrixMultSeq 
	#(
	.N(N),
	.M(M)
	)
	UTT
	(
		.clk(clk),
		.x(x),
		.y(y),
		.o(o)
	);

  integer i;
	initial
	begin
		clk=0;
	  x = {N*N*M/32{$random}};
	  y = {N*N*M/32{$random}};
		for(i=0;i<N*N*N;i=i+1)
			@(negedge clk);
		$stop;
	end

  initial 
    $monitor($time,"o = %x",o); 

	always #5 clk = !clk;
endmodule