data/full_repos/permissive/491294671/timer_input_control/div_100/div_100_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/491294671/timer_input_control/div_100/div_100_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clock <= ~clock;  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491294671/timer_input_control/div_100/div_100_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("div_5.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491294671/timer_input_control/div_100/div_100_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, clock_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491294671/timer_input_control/div_100/div_100_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #6000 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_tb;
  
  reg clock;
  wire clock_div;
  
  div_100 dut(.clock(clock), .clock_div(clock_div));

 	
  always #5 clock <= ~clock;
  

  
  initial begin
    
    $dumpfile("div_5.vcd");
    $dumpvars(0, clock_tb);
    
    clock = 0;
    #6000 $finish;
     
  end
  
endmodule
module clock_tb;

  
  reg clock;
  wire clock_div;
  
  div_100 dut(.clock(clock), .clock_div(clock_div));

 	
  always #5 clock <= ~clock;
  

  
  initial begin
    
    $dumpfile("div_5.vcd");
    $dumpvars(0, clock_tb);
    
    clock = 0;
    #6000 $finish;
     
  end
  
endmodule