data/full_repos/permissive/458134463/Modules/half_adder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/half_adder_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#0  value1 = 1\'b0; value2 = 1\'b0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/half_adder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 1\'b0; value2 = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/half_adder_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 1\'b1; value2 = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/half_adder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20 value1 = 1\'b1; value2 = 1\'b1;\n^\n%Error: data/full_repos/permissive/458134463/Modules/half_adder_tb.v:22: Unsupported or unknown PLI call: $monitor\n$monitor("Time: %2d, value1: %1b, value2: %1b, sum: %1b, carry_out: %1b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module half_adder_tb();

reg value1;
reg value2;

wire sum;
wire carry_out;


half_adder ha(value1, value2, sum, carry_out);


initial begin
#0  value1 = 1'b0; value2 = 1'b0;
#20 value1 = 1'b0; value2 = 1'b1;
#20 value1 = 1'b1; value2 = 1'b0;
#20 value1 = 1'b1; value2 = 1'b1;
end


initial begin
$monitor("Time: %2d, value1: %1b, value2: %1b, sum: %1b, carry_out: %1b", 
			$time, 	
			value1, 
			value2, 
			sum, 
			carry_out);
end

endmodule
module half_adder_tb();


reg value1;
reg value2;

wire sum;
wire carry_out;


half_adder ha(value1, value2, sum, carry_out);


initial begin
#0  value1 = 1'b0; value2 = 1'b0;
#20 value1 = 1'b0; value2 = 1'b1;
#20 value1 = 1'b1; value2 = 1'b0;
#20 value1 = 1'b1; value2 = 1'b1;
end


initial begin
$monitor("Time: %2d, value1: %1b, value2: %1b, sum: %1b, carry_out: %1b", 
			$time, 	
			value1, 
			value2, 
			sum, 
			carry_out);
end

endmodule