data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_encode_8.v
data/verilator_xmls/a62e331b-c521-4ea6-b626-6e4b0d2cbf43.xml
module ct_rtu_encode_8(
  x_num,
  x_num_expand
);


input   [7:0]  x_num_expand; 
output  [2:0]  x_num;       




wire    [2:0]  x_num;       
wire    [7:0]  x_num_expand; 





assign x_num[2:0] =
           {3{x_num_expand[0]}} & 3'd0
         | {3{x_num_expand[1]}} & 3'd1
         | {3{x_num_expand[2]}} & 3'd2
         | {3{x_num_expand[3]}} & 3'd3
         | {3{x_num_expand[4]}} & 3'd4
         | {3{x_num_expand[5]}} & 3'd5
         | {3{x_num_expand[6]}} & 3'd6
         | {3{x_num_expand[7]}} & 3'd7;


endmodule
module ct_rtu_encode_8(
  x_num,
  x_num_expand
);



input   [7:0]  x_num_expand; 
output  [2:0]  x_num;       




wire    [2:0]  x_num;       
wire    [7:0]  x_num_expand; 





assign x_num[2:0] =
           {3{x_num_expand[0]}} & 3'd0
         | {3{x_num_expand[1]}} & 3'd1
         | {3{x_num_expand[2]}} & 3'd2
         | {3{x_num_expand[3]}} & 3'd3
         | {3{x_num_expand[4]}} & 3'd4
         | {3{x_num_expand[5]}} & 3'd5
         | {3{x_num_expand[6]}} & 3'd6
         | {3{x_num_expand[7]}} & 3'd7;


endmodule