data/full_repos/permissive/426611218/ALU_cntrl.v
data/verilator_xmls/7a84c1b3-c64e-4020-ab98-bbeb02f20aac.xml
module alucontrol (
    input [1:0] ALUOp,
    input [5:0] Function,
    output reg [3:0] ALUControl
    );

wire [7:0] ALUControlIn;

assign ALUControlIn = {ALUOp,Function};

    always @(ALUControlIn)
    begin
        casex (ALUControlIn)
            8'b10100000: ALUControl=4'b0000;
            8'b10100010: ALUControl=4'b0001;
            8'b10100100: ALUControl=4'b0010;
            8'b10100101: ALUControl=4'b0011;
            8'b10101010: ALUControl=4'b0100;
            8'b10101011: ALUControl=4'b0101;
            8'b10101111: ALUControl=4'b1000;
            8'b01xxxxxx: ALUControl=4'b0001;
            8'b00xxxxxx: ALUControl=4'b0000;
            default: ALUControl=4'b0010;
        endcase
    end
endmodule
module alucontrol (
    input [1:0] ALUOp,
    input [5:0] Function,
    output reg [3:0] ALUControl
    );


wire [7:0] ALUControlIn;

assign ALUControlIn = {ALUOp,Function};

    always @(ALUControlIn)
    begin
        casex (ALUControlIn)
            8'b10100000: ALUControl=4'b0000;
            8'b10100010: ALUControl=4'b0001;
            8'b10100100: ALUControl=4'b0010;
            8'b10100101: ALUControl=4'b0011;
            8'b10101010: ALUControl=4'b0100;
            8'b10101011: ALUControl=4'b0101;
            8'b10101111: ALUControl=4'b1000;
            8'b01xxxxxx: ALUControl=4'b0001;
            8'b00xxxxxx: ALUControl=4'b0000;
            default: ALUControl=4'b0010;
        endcase
    end
endmodule