data/full_repos/permissive/467292628/mem.v
1: b'%Error: data/full_repos/permissive/467292628/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v.v\n             data/full_repos/permissive/467292628,data/full_repos/permissive/467292628/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/467292628/mem.v:9: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:9: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:14: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:18: Define or directive not defined: \'`MEMORY_SIZE\'\n reg[7:0] data[`MEMORY_SIZE-1:0];  \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:22: syntax error, unexpected assign\n assign mask[0] = 1;\n ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:65: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:65: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:70: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:71: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:73: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg hlt,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:74: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg hlt_error\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:107: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:107: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:112: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:113: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:115: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [8:0] data_in,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:117: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/467292628/mem.v:162: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:162: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  input [`MEMORY_ACCESS_SIZE:0] mem_size,\n                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:167: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_done,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:168: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg mem_error,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:170: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [63:0] mtime,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:171: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tip,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:178: syntax error, unexpected assign\n assign tip = (mtimecmp != 0) && (mtime >= mtimecmp);\n ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:243: Unsupported: SystemVerilog 2012 reserved word not implemented: \'interconnect\'\nmodule interconnect #(\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: Define or directive not defined: \'`MEMORY_SIZE\'\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:245: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter RX_1_END_ADDR   = RX_1_START_ADDR + `MEMORY_SIZE,\n                                                            ^\n%Error: data/full_repos/permissive/467292628/mem.v:247: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_2_END_ADDR   = 32\'h0201_03ff,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:248: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_3_START_ADDR = 32\'h1001_3000,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:249: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_3_END_ADDR   = 32\'h1001_3fff,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:250: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_4_START_ADDR = 32\'h0200_0000,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:251: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter RX_4_END_ADDR   = 32\'h0200_ffff\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:252: syntax error, unexpected \')\', expecting \';\'\n )\n ^\n%Error: data/full_repos/permissive/467292628/mem.v:259: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  input [`MEMORY_ACCESS_SIZE:0] tx_mem_size,    \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:264: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tx_mem_ready,     \n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:268: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx1_mem_addr,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:269: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:269: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  output reg [`MEMORY_ACCESS_SIZE:0] rx1_mem_size,\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:271: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg rx1_mem_w_mode,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:272: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx1_mem_w_data,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:273: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [31:0] rx1_mem_r_data,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:279: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:279: Define or directive not defined: \'`MEMORY_ACCESS_SIZE\'\n  output reg [`MEMORY_ACCESS_SIZE:0] rx2_mem_size,\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:281: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg rx2_mem_w_mode,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:282: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [31:0] rx2_mem_w_data,\n  ^~~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:283: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input [31:0] rx2_mem_r_data,\n  ^~~~~\n%Error: data/full_repos/permissive/467292628/mem.v:289: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output reg [`MEMORY_ACCESS_SIZE:0] rx3_mem_size,\n  ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module memory
	(
		input reset,
		input clock,
		
		input [31:0] mem_addr,
		input [`MEMORY_ACCESS_SIZE:0] mem_size,
		input mem_enable,
		input mem_w_mode,
		input [31:0] mem_w_data,
		output reg [31:0] mem_r_data,
		output reg mem_done,
		output reg mem_error
	);
	
	reg[7:0] data[`MEMORY_SIZE-1:0];
	integer i;
	wire[3:0] mask;
	
	assign mask[0] = 1;
	assign mask[1] = mem_size == 2 || mem_size == 4;
	assign mask[2] = mem_size == 4;
	assign mask[3] = mem_size == 4;
	
	always @(posedge clock) begin
		if (reset) begin
			mem_done <= 0;
			mem_error <= 0;
		end else begin
			if (mem_enable) begin
				if (mem_w_mode) begin
					if (mask[0])
						data[mem_addr    ] <= mem_w_data[7:0];
					if (mask[1])
						data[mem_addr + 1] <= mem_w_data[15:8];
					if (mask[2])
						data[mem_addr + 2] <= mem_w_data[23:16];
					if (mask[3])
						data[mem_addr + 3] <= mem_w_data[31:24];
				end else begin
					mem_r_data <= {
						mask[3] ? data[mem_addr+3] : 8'b0, 
						mask[2] ? data[mem_addr+2] : 8'b0, 
						mask[1] ? data[mem_addr+1] : 8'b0, 
						mask[0] ? data[mem_addr] : 8'b0
					};
				end
				mem_done <= 1;
			end else begin
				mem_done <= 0;
			end
		end
	end
endmodule
module memory
	(
		input reset,
		input clock,
		
		input [31:0] mem_addr,
		input [`MEMORY_ACCESS_SIZE:0] mem_size,
		input mem_enable,
		input mem_w_mode,
		input [31:0] mem_w_data,
		output reg [31:0] mem_r_data,
		output reg mem_done,
		output reg mem_error
	);

	
	reg[7:0] data[`MEMORY_SIZE-1:0];
	integer i;
	wire[3:0] mask;
	
	assign mask[0] = 1;
	assign mask[1] = mem_size == 2 || mem_size == 4;
	assign mask[2] = mem_size == 4;
	assign mask[3] = mem_size == 4;
	
	always @(posedge clock) begin
		if (reset) begin
			mem_done <= 0;
			mem_error <= 0;
		end else begin
			if (mem_enable) begin
				if (mem_w_mode) begin
					if (mask[0])
						data[mem_addr    ] <= mem_w_data[7:0];
					if (mask[1])
						data[mem_addr + 1] <= mem_w_data[15:8];
					if (mask[2])
						data[mem_addr + 2] <= mem_w_data[23:16];
					if (mask[3])
						data[mem_addr + 3] <= mem_w_data[31:24];
				end else begin
					mem_r_data <= {
						mask[3] ? data[mem_addr+3] : 8'b0, 
						mask[2] ? data[mem_addr+2] : 8'b0, 
						mask[1] ? data[mem_addr+1] : 8'b0, 
						mask[0] ? data[mem_addr] : 8'b0
					};
				end
				mem_done <= 1;
			end else begin
				mem_done <= 0;
			end
		end
	end
endmodule