data/full_repos/permissive/529457593/Sprint10/Parallel_Out.v
data/verilator_xmls/4ac8304d-a905-4680-9a53-c94c6b8fa26a.xml
module Parallel_OUT (input we, clk, input[7:0] RegData, Address, output wren, output reg[7:0] DataOut);

	wire fioA, fioB;
	
	assign fioA = (Address == 8'hff) ? 1 : 0;
	assign fioB = we & fioA;
	assign wren = we & ~(fioA);
	
	always @ (posedge clk) begin
		if(fioB == 1)
			DataOut = RegData;
	end

endmodule
module Parallel_OUT (input we, clk, input[7:0] RegData, Address, output wren, output reg[7:0] DataOut);


	wire fioA, fioB;
	
	assign fioA = (Address == 8'hff) ? 1 : 0;
	assign fioB = we & fioA;
	assign wren = we & ~(fioA);
	
	always @ (posedge clk) begin
		if(fioB == 1)
			DataOut = RegData;
	end

endmodule