data/full_repos/permissive/487568919/basic_verilog/uart_rx.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/uart_rx.sv:35: Operator VAR \'BAUD_DIVISOR_2\' expects 16 bits on the Initial value, but Initial value\'s DIVS generates 32 or 28 bits.\n                                                                                : ... In instance uart_rx\n  bit [15:0] BAUD_DIVISOR_2 = CLK_HZ / BAUD / 2\n             ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/487568919/basic_verilog/uart_rx.sv:50: Cannot find file containing module: \'delay\'\ndelay #(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay.sv\n             delay\n             delay.v\n             delay.sv\n             obj_dir/delay\n             obj_dir/delay.v\n             obj_dir/delay.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/uart_rx.sv:63: Cannot find file containing module: \'edge_detect\'\nedge_detect rxd_fall_detector (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module uart_rx #( parameter
  CLK_HZ = 200_000_000,
  BAUD = 9600,
  bit [15:0] BAUD_DIVISOR_2 = CLK_HZ / BAUD / 2
)(
  input clk,
  input nrst,

  output logic [7:0] rx_data = '0,
  output logic rx_busy = 1'b0,
  output logic rx_done,
  output logic rx_err,
  input rxd
);



logic rxd_s;
delay #(
  .LENGTH( 2 ),
  .WIDTH( 1 )
) rxd_synch (
  .clk( clk ),
  .nrst( nrst ),
  .ena( 1'b1 ),
  .in( rxd ),
  .out( rxd_s )
);


logic start_bit_strobe;
edge_detect rxd_fall_detector (
  .clk( clk ),
  .nrst( nrst ),
  .in( rxd_s ),
  .falling( start_bit_strobe )
);


logic [15:0] rx_sample_cntr = (BAUD_DIVISOR_2 - 1'b1);

logic rx_do_sample;
assign rx_do_sample = (rx_sample_cntr[15:0] == '0);



logic rx_data_9th_bit = 1'b0;
always_ff @ (posedge clk) begin
  if( ~nrst ) begin
    rx_busy <= 1'b0;
    rx_sample_cntr <= (BAUD_DIVISOR_2 - 1'b1);
    {rx_data[7:0],rx_data_9th_bit} <= '0;
  end else begin
    if( ~rx_busy ) begin
      if( start_bit_strobe ) begin


        rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 3 - 1'b1);
        rx_busy <= 1'b1;
        {rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;

      end
    end else begin

      if( rx_sample_cntr[15:0] == '0 ) begin

        rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1'b1);
      end else begin

        rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1'b1;
      end

      if( rx_do_sample ) begin
        if( rx_data_9th_bit == 1'b1 ) begin

          rx_busy <= 1'b0;
        end else begin
          {rx_data[7:0],rx_data_9th_bit} <= {rxd_s, rx_data[7:0]};
        end
      end

    end
  end
end

always_comb begin

  rx_done <= rx_data_9th_bit && rx_do_sample && rxd_s;
  rx_err <= rx_data_9th_bit && rx_do_sample && ~rxd_s;
end

endmodule
module uart_rx #( parameter
  CLK_HZ = 200_000_000,
  BAUD = 9600,
  bit [15:0] BAUD_DIVISOR_2 = CLK_HZ / BAUD / 2
)(
  input clk,
  input nrst,

  output logic [7:0] rx_data = '0,
  output logic rx_busy = 1'b0,
  output logic rx_done,
  output logic rx_err,
  input rxd
);




logic rxd_s;
delay #(
  .LENGTH( 2 ),
  .WIDTH( 1 )
) rxd_synch (
  .clk( clk ),
  .nrst( nrst ),
  .ena( 1'b1 ),
  .in( rxd ),
  .out( rxd_s )
);


logic start_bit_strobe;
edge_detect rxd_fall_detector (
  .clk( clk ),
  .nrst( nrst ),
  .in( rxd_s ),
  .falling( start_bit_strobe )
);


logic [15:0] rx_sample_cntr = (BAUD_DIVISOR_2 - 1'b1);

logic rx_do_sample;
assign rx_do_sample = (rx_sample_cntr[15:0] == '0);



logic rx_data_9th_bit = 1'b0;
always_ff @ (posedge clk) begin
  if( ~nrst ) begin
    rx_busy <= 1'b0;
    rx_sample_cntr <= (BAUD_DIVISOR_2 - 1'b1);
    {rx_data[7:0],rx_data_9th_bit} <= '0;
  end else begin
    if( ~rx_busy ) begin
      if( start_bit_strobe ) begin


        rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 3 - 1'b1);
        rx_busy <= 1'b1;
        {rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;

      end
    end else begin

      if( rx_sample_cntr[15:0] == '0 ) begin

        rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1'b1);
      end else begin

        rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1'b1;
      end

      if( rx_do_sample ) begin
        if( rx_data_9th_bit == 1'b1 ) begin

          rx_busy <= 1'b0;
        end else begin
          {rx_data[7:0],rx_data_9th_bit} <= {rxd_s, rx_data[7:0]};
        end
      end

    end
  end
end

always_comb begin

  rx_done <= rx_data_9th_bit && rx_do_sample && rxd_s;
  rx_err <= rx_data_9th_bit && rx_do_sample && ~rxd_s;
end

endmodule