data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:15: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:24: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:27: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_TestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:28: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_TestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit/ARM_CU_TestBench.v:30: Unsupported or unknown PLI call: $monitor\n $monitor("IR_CU=%d  RFLOAD=%d  PCLOAD=%d  SRLOAD=%d  SRENABLED=%d  ALUSTORE=%d  MFA=%d  WORD_BYTE=%d READ_WRITE=%d IRLOAD=%d MBRLOAD=%d MBRSTORE=%d MARLOAD=%d opcode=%d CU=%d  MFC=%d Reset=%d Clk=%d",IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD, opcode, CU,  MFC, Reset,Clk);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_TestBench;

parameter sim_time = 750*2;
wire [17:0] signals;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;


ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ;
	#1 MFC = 1;#1 Reset=0 ;
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_TestBench.vcd");
	$dumpvars(0,ARM_CU_TestBench);
	$display(" Test Results" );
	$monitor("IR_CU=%d  RFLOAD=%d  PCLOAD=%d  SRLOAD=%d  SRENABLED=%d  ALUSTORE=%d  MFA=%d  WORD_BYTE=%d READ_WRITE=%d IRLOAD=%d MBRLOAD=%d MBRSTORE=%d MARLOAD=%d opcode=%d CU=%d  MFC=%d Reset=%d Clk=%d",IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD, opcode, CU,  MFC, Reset,Clk);
end

endmodule
module ARM_CU_TestBench;


parameter sim_time = 750*2;
wire [17:0] signals;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;


ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ;
	#1 MFC = 1;#1 Reset=0 ;
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_TestBench.vcd");
	$dumpvars(0,ARM_CU_TestBench);
	$display(" Test Results" );
	$monitor("IR_CU=%d  RFLOAD=%d  PCLOAD=%d  SRLOAD=%d  SRENABLED=%d  ALUSTORE=%d  MFA=%d  WORD_BYTE=%d READ_WRITE=%d IRLOAD=%d MBRLOAD=%d MBRSTORE=%d MARLOAD=%d opcode=%d CU=%d  MFC=%d Reset=%d Clk=%d",IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD, opcode, CU,  MFC, Reset,Clk);
end

endmodule