data/full_repos/permissive/52703097/multiplier.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52703097/multiplier.v:20: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'bits\' generates 5 bits.\n                                                                   : ... In instance multiplier\n    assign ready = !bits;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52703097/multiplier.v:29: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh20\' generates 32 or 6 bits.\n                                                                   : ... In instance multiplier\n            bits = 32;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/52703097/multiplier.v:34: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bits\' generates 5 bits.\n                                                                   : ... In instance multiplier\n        else if (bits) begin\n             ^~\n%Error: Exiting due to 3 warning(s)\n'
module multiplier(
    input start,
    input clk,
    input [`WIDTH - 1:0] multiplier,
    input [`WIDTH - 1:0] multiplicand,
    output reg [`WIDTH + `WIDTH - 1:0] product,
    output ready);

    reg[`WIDTH - 1:0] multiplier_copy;
    reg[`WIDTH + `WIDTH - 1:0] multiplicand_copy;
    reg[4:0] bits;

    assign ready = !bits;

    initial begin
       bits = 0;
    end


    always @(posedge clk) begin
        if (ready & start) begin
            bits = `WIDTH;
            product = 0;
            multiplicand_copy = {`WIDTH'd0, multiplicand};
            multiplier_copy = multiplier;
        end
        else if (bits) begin
            if (multiplier_copy[0] == 1'b1)
                product = product + multiplicand_copy;

            multiplier_copy = multiplier_copy >> 1;
            multiplicand_copy = multiplicand_copy << 1;

            bits = bits - 1;
        end
    end
endmodule
module multiplier(
    input start,
    input clk,
    input [`WIDTH - 1:0] multiplier,
    input [`WIDTH - 1:0] multiplicand,
    output reg [`WIDTH + `WIDTH - 1:0] product,
    output ready);


    reg[`WIDTH - 1:0] multiplier_copy;
    reg[`WIDTH + `WIDTH - 1:0] multiplicand_copy;
    reg[4:0] bits;

    assign ready = !bits;

    initial begin
       bits = 0;
    end


    always @(posedge clk) begin
        if (ready & start) begin
            bits = `WIDTH;
            product = 0;
            multiplicand_copy = {`WIDTH'd0, multiplicand};
            multiplier_copy = multiplier;
        end
        else if (bits) begin
            if (multiplier_copy[0] == 1'b1)
                product = product + multiplicand_copy;

            multiplier_copy = multiplier_copy >> 1;
            multiplicand_copy = multiplicand_copy << 1;

            bits = bits - 1;
        end
    end
endmodule