data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v
1: b"%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:11: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(21) (clk,reset,clk_count);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:12: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(17) (clk,reset,clk_sel);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:15: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select #(2) (clk_sel,reset,seg7_sel);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:23: syntax error, unexpected '(', expecting IDENTIFIER\ncount_0_9 (clk,reset,enable,carry0,count0_out);\n           ^~~\n%Error: Exiting due to 4 error(s)\n"
module count_00_99(clk, reset, enable, count1_out, count0_out, carry_out);
input	clk, reset, enable;
output[3:0] count1_out, count0_out;
output	carry_out = carry1 & carry0;
wire	carry0,carry1;
count_0_9 (clk,reset,enable,carry0,count0_out);
count_0_9 (clk,reset,carry0,carry1,count1_out);
endmodule
module count_00_99(clk, reset, enable, count1_out, count0_out, carry_out);

input	clk, reset, enable;
output[3:0] count1_out, count0_out;
output	carry_out = carry1 & carry0;
wire	carry0,carry1;
count_0_9 (clk,reset,enable,carry0,count0_out);
count_0_9 (clk,reset,carry0,carry1,count1_out);
endmodule