data/full_repos/permissive/425166201/03_testzx/de0.v
1: b"%Error: data/full_repos/permissive/425166201/03_testzx/de0.v:82: Cannot find file containing module: 'de0pll'\nde0pll unit_pll\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425166201/03_testzx,data/full_repos/permissive/425166201/de0pll\n             data/full_repos/permissive/425166201/03_testzx,data/full_repos/permissive/425166201/de0pll.v\n             data/full_repos/permissive/425166201/03_testzx,data/full_repos/permissive/425166201/de0pll.sv\n             de0pll\n             de0pll.v\n             de0pll.sv\n             obj_dir/de0pll\n             obj_dir/de0pll.v\n             obj_dir/de0pll.sv\n%Error: data/full_repos/permissive/425166201/03_testzx/de0.v:93: Cannot find file containing module: 'vram'\nvram UnitVram\n^~~~\n%Error: data/full_repos/permissive/425166201/03_testzx/de0.v:101: Cannot find file containing module: 'adapter'\nadapter VAdapterZX\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module de0(


    input              RESET_N,


    input              CLOCK_50,
    input              CLOCK2_50,
    input              CLOCK3_50,
    inout              CLOCK4_50,


    output             DRAM_CKE,
    output             DRAM_CLK,
    output      [1:0]  DRAM_BA,
    output      [12:0] DRAM_ADDR,
    inout       [15:0] DRAM_DQ,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,
    output             DRAM_WE_N,
    output             DRAM_CS_N,
    output             DRAM_LDQM,
    output             DRAM_UDQM,


    inout       [35:0] GPIO_0,
    inout       [35:0] GPIO_1,


    output      [6:0]  HEX0,
    output      [6:0]  HEX1,
    output      [6:0]  HEX2,
    output      [6:0]  HEX3,
    output      [6:0]  HEX4,
    output      [6:0]  HEX5,


    input       [3:0]  KEY,


    output      [9:0]  LEDR,


    inout              PS2_CLK,
    inout              PS2_DAT,
    inout              PS2_CLK2,
    inout              PS2_DAT2,


    output             SD_CLK,
    inout              SD_CMD,
    inout       [3:0]  SD_DATA,


    input       [9:0]  SW,


    output      [3:0]  VGA_R,
    output      [3:0]  VGA_G,
    output      [3:0]  VGA_B,
    output             VGA_HS,
    output             VGA_VS
);


assign DRAM_DQ = 16'hzzzz;
assign GPIO_0  = 36'hzzzzzzzz;
assign GPIO_1  = 36'hzzzzzzzz;


assign HEX0 = 7'b1111111;
assign HEX1 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;


wire locked;
wire clock_25;

de0pll unit_pll
(
    .clkin     (CLOCK_50),
    .m25       (clock_25),
    .locked    (locked)
);


wire [ 7:0] data_in;
wire [15:0] address;

vram UnitVram
(
    .clock     (CLOCK_50),
    .address_a (address[13:0]),
    .q_a       (data_in),
);


adapter VAdapterZX
(
    .clock_25   (clock_25),
    .vga_hs     (VGA_HS),
    .vga_vs     (VGA_VS),
    .vga_r      (VGA_R),
    .vga_g      (VGA_G),
    .vga_b      (VGA_B),
    .bgcolor    (3'b111),
    .address    (address),
    .data_in    (data_in)
);

endmodule
module de0(


    input              RESET_N,


    input              CLOCK_50,
    input              CLOCK2_50,
    input              CLOCK3_50,
    inout              CLOCK4_50,


    output             DRAM_CKE,
    output             DRAM_CLK,
    output      [1:0]  DRAM_BA,
    output      [12:0] DRAM_ADDR,
    inout       [15:0] DRAM_DQ,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,
    output             DRAM_WE_N,
    output             DRAM_CS_N,
    output             DRAM_LDQM,
    output             DRAM_UDQM,


    inout       [35:0] GPIO_0,
    inout       [35:0] GPIO_1,


    output      [6:0]  HEX0,
    output      [6:0]  HEX1,
    output      [6:0]  HEX2,
    output      [6:0]  HEX3,
    output      [6:0]  HEX4,
    output      [6:0]  HEX5,


    input       [3:0]  KEY,


    output      [9:0]  LEDR,


    inout              PS2_CLK,
    inout              PS2_DAT,
    inout              PS2_CLK2,
    inout              PS2_DAT2,


    output             SD_CLK,
    inout              SD_CMD,
    inout       [3:0]  SD_DATA,


    input       [9:0]  SW,


    output      [3:0]  VGA_R,
    output      [3:0]  VGA_G,
    output      [3:0]  VGA_B,
    output             VGA_HS,
    output             VGA_VS
);



assign DRAM_DQ = 16'hzzzz;
assign GPIO_0  = 36'hzzzzzzzz;
assign GPIO_1  = 36'hzzzzzzzz;


assign HEX0 = 7'b1111111;
assign HEX1 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;


wire locked;
wire clock_25;

de0pll unit_pll
(
    .clkin     (CLOCK_50),
    .m25       (clock_25),
    .locked    (locked)
);


wire [ 7:0] data_in;
wire [15:0] address;

vram UnitVram
(
    .clock     (CLOCK_50),
    .address_a (address[13:0]),
    .q_a       (data_in),
);


adapter VAdapterZX
(
    .clock_25   (clock_25),
    .vga_hs     (VGA_HS),
    .vga_vs     (VGA_VS),
    .vga_r      (VGA_R),
    .vga_g      (VGA_G),
    .vga_b      (VGA_B),
    .bgcolor    (3'b111),
    .address    (address),
    .data_in    (data_in)
);

endmodule