data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb/knn_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb/knn_top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk_en=~clk_en;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb/knn_top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #40 reset_n=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb/knn_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #30 knn_en=1;\n    ^\n%Error: data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb/knn_top_tb.v:40: Cannot find file containing module: \'knn_top\'\nknn_top inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb,data/full_repos/permissive/514467334/knn_top\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb,data/full_repos/permissive/514467334/knn_top.v\n             data/full_repos/permissive/514467334/project/ConvKing/source/Accelerator/KNN/tb,data/full_repos/permissive/514467334/knn_top.sv\n             knn_top\n             knn_top.v\n             knn_top.sv\n             obj_dir/knn_top\n             obj_dir/knn_top.v\n             obj_dir/knn_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module knn_top_tb();

reg clk_en;
reg reset_n;
reg knn_en;

reg [9:0] postion_lu_x;
reg [9:0] postion_lu_y;
reg [9:0] postion_rd_x;
reg [9:0] postion_rd_y;

wire [3:0] knn_result;
wire knn_outflag;

initial begin
    clk_en=0;
    forever #10 clk_en=~clk_en;
end


initial begin
    reset_n=0;
    #40 reset_n=1;

end

initial begin
    postion_lu_x=0;
    postion_lu_y=0;
    postion_rd_x=4;
    postion_rd_y=4;
end

initial begin
    knn_en=0;
    #30 knn_en=1;
end

knn_top inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .knn_en     (knn_en),

    .postion_lu_x   (postion_lu_x),
    .postion_lu_y   (postion_lu_y),
    .postion_rd_x   (postion_rd_x),
    .postion_rd_y   (postion_rd_y),
    
    .knn_result     (knn_result),
    .knn_outflag    (knn_outflag)
);




endmodule
module knn_top_tb();


reg clk_en;
reg reset_n;
reg knn_en;

reg [9:0] postion_lu_x;
reg [9:0] postion_lu_y;
reg [9:0] postion_rd_x;
reg [9:0] postion_rd_y;

wire [3:0] knn_result;
wire knn_outflag;

initial begin
    clk_en=0;
    forever #10 clk_en=~clk_en;
end


initial begin
    reset_n=0;
    #40 reset_n=1;

end

initial begin
    postion_lu_x=0;
    postion_lu_y=0;
    postion_rd_x=4;
    postion_rd_y=4;
end

initial begin
    knn_en=0;
    #30 knn_en=1;
end

knn_top inst(
    .clk_en     (clk_en),
    .reset_n    (reset_n),
    .knn_en     (knn_en),

    .postion_lu_x   (postion_lu_x),
    .postion_lu_y   (postion_lu_y),
    .postion_rd_x   (postion_rd_x),
    .postion_rd_y   (postion_rd_y),
    
    .knn_result     (knn_result),
    .knn_outflag    (knn_outflag)
);




endmodule