data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v:35: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n wire [LOGW-1:0] dist;\n                 ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v:35: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire [LOGW-1:0] dist;\n                     ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v:67: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n  .S(dist)\n     ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v:176: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n assign local_min_dist[K] = dist;\n                            ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns/k_nns_seq.v:176: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n assign local_min_dist[K] = dist;\n                                ^\n%Error: Exiting due to 5 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
function integer log2;
		input [31:0] value;
		reg [31:0] temp;
	begin
		temp = value;
		for (log2=0; temp>0; log2=log2+1)
			temp = temp>>1;
	end
	endfunction
function integer log2;

		input [31:0] value;
		reg [31:0] temp;
	begin
		temp = value;
		for (log2=0; temp>0; log2=log2+1)
			temp = temp>>1;
	end
	endfunction