data/full_repos/permissive/455874613/Projects/Module01/TemperatureCalculatorUtils.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/455874613/Projects/Module01/TemperatureCalculatorUtils.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/455874613/Projects/Module01/TemperatureCalculatorUtils.v:28: Cannot find file containing module: \'TemperatureCalculator\'\n TemperatureCalculator uut (tc_base, tc_ref, adc_data, tempc);\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455874613/Projects/Module01,data/full_repos/permissive/455874613/TemperatureCalculator\n             data/full_repos/permissive/455874613/Projects/Module01,data/full_repos/permissive/455874613/TemperatureCalculator.v\n             data/full_repos/permissive/455874613/Projects/Module01,data/full_repos/permissive/455874613/TemperatureCalculator.sv\n             TemperatureCalculator\n             TemperatureCalculator.v\n             TemperatureCalculator.sv\n             obj_dir/TemperatureCalculator\n             obj_dir/TemperatureCalculator.v\n             obj_dir/TemperatureCalculator.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TemperatureCalculatorUtils();
	reg  [31:0] tc_base  ;
	reg  [ 7:0] tc_ref   ;
	reg  [15:0] adc_data ;
	wire [31:0] tempc;

	TemperatureCalculator uut (tc_base, tc_ref, adc_data, tempc);

	initial begin
		tc_base = 1;
		tc_ref = 4;
		adc_data = 4;
		#100;
		tc_base = 32'b10101010101010101010101010101010;
	   adc_data = 16'b1010101010101010;
	   tc_ref = 8'b11000110 ;
	end
endmodule
module TemperatureCalculatorUtils();

	reg  [31:0] tc_base  ;
	reg  [ 7:0] tc_ref   ;
	reg  [15:0] adc_data ;
	wire [31:0] tempc;

	TemperatureCalculator uut (tc_base, tc_ref, adc_data, tempc);

	initial begin
		tc_base = 1;
		tc_ref = 4;
		adc_data = 4;
		#100;
		tc_base = 32'b10101010101010101010101010101010;
	   adc_data = 16'b1010101010101010;
	   tc_ref = 8'b11000110 ;
	end
endmodule