data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                    : ... In instance top_module\n            4'b0000: out = a;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                    : ... In instance top_module\n            4'b0001: out = b;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0010: out = c;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0011: out = d;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0100: out = e;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0101: out = f;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:14: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0110: out = g;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:15: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b0111: out = h;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:16: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'b1000: out = i;\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            default: out = {16{1'b1}};\n                     ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n        out = '1;        \n        ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:29: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h0: out = a;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h1: out = b;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h2: out = c;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:32: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h3: out = d;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:33: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h4: out = e;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h5: out = f;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h6: out = g;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:36: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h7: out = h;\n                  ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/63_Mux9to1v.v:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n            4'h8: out = i;\n                  ^~~\n%Error: Exiting due to 20 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );

    always @(*) begin
        case (sel)
            4'b0000: out = a;
            4'b0001: out = b;
            4'b0010: out = c;
            4'b0011: out = d;
            4'b0100: out = e;
            4'b0101: out = f;
            4'b0110: out = g;
            4'b0111: out = h;
            4'b1000: out = i;
            default: out = {16{1'b1}};
        endcase
    end



    always @(*) begin
        out = '1;



        case (sel)
            4'h0: out = a;
            4'h1: out = b;
            4'h2: out = c;
            4'h3: out = d;
            4'h4: out = e;
            4'h5: out = f;
            4'h6: out = g;
            4'h7: out = h;
            4'h8: out = i;
        endcase
    end
endmodule
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );


    always @(*) begin
        case (sel)
            4'b0000: out = a;
            4'b0001: out = b;
            4'b0010: out = c;
            4'b0011: out = d;
            4'b0100: out = e;
            4'b0101: out = f;
            4'b0110: out = g;
            4'b0111: out = h;
            4'b1000: out = i;
            default: out = {16{1'b1}};
        endcase
    end



    always @(*) begin
        out = '1;



        case (sel)
            4'h0: out = a;
            4'h1: out = b;
            4'h2: out = c;
            4'h3: out = d;
            4'h4: out = e;
            4'h5: out = f;
            4'h6: out = g;
            4'h7: out = h;
            4'h8: out = i;
        endcase
    end
endmodule