data/full_repos/permissive/520452389/source_codes/mem_ld_sv.v
data/verilator_xmls/51d08d3b-81b9-4396-857b-4868e5380a9d.xml
module dff4 (input clk,input MemtoReg_s3,output reg MemtoReg_s4,input [31:0]read_data3,output reg [31:0]read_data3_s4,
             input [31:0]ALU_result_s3,output reg [31:0]ALU_result_s4,input RegWrite_s3,output reg RegWrite_s4,input [4:0] write_reg_s3,output reg [4:0] write_reg_s4);

always @(posedge clk) begin 
     MemtoReg_s4<=MemtoReg_s3;
     read_data3_s4<=read_data3;
     ALU_result_s4<=ALU_result_s3;
     RegWrite_s4<=RegWrite_s3;
     write_reg_s4<=write_reg_s3;

end
endmodule
module dff4 (input clk,input MemtoReg_s3,output reg MemtoReg_s4,input [31:0]read_data3,output reg [31:0]read_data3_s4,
             input [31:0]ALU_result_s3,output reg [31:0]ALU_result_s4,input RegWrite_s3,output reg RegWrite_s4,input [4:0] write_reg_s3,output reg [4:0] write_reg_s4);


always @(posedge clk) begin 
     MemtoReg_s4<=MemtoReg_s3;
     read_data3_s4<=read_data3;
     ALU_result_s4<=ALU_result_s3;
     RegWrite_s4<=RegWrite_s3;
     write_reg_s4<=write_reg_s3;

end
endmodule