data/full_repos/permissive/52900389/TB_synchro.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_synchro.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_synchro.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_synchro.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/52900389/TB_synchro.v:35: Cannot find file containing module: \'Synchro\'\n Synchro uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Synchro\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Synchro.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Synchro.sv\n             Synchro\n             Synchro.v\n             Synchro.sv\n             obj_dir/Synchro\n             obj_dir/Synchro.v\n             obj_dir/Synchro.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_synchro;


	reg dato;
	reg clk;


	wire ds;


	Synchro uut (
		.dato(dato), 
		.clk(clk), 
		.ds(ds)
	);

	initial begin

		dato = 0;
		clk = 0;


		#30;
      dato = 1;
		#50;
      dato = 0;


	end
 
always #10 clk = ~clk;
endmodule
module TB_synchro;



	reg dato;
	reg clk;


	wire ds;


	Synchro uut (
		.dato(dato), 
		.clk(clk), 
		.ds(ds)
	);

	initial begin

		dato = 0;
		clk = 0;


		#30;
      dato = 1;
		#50;
      dato = 0;


	end
 
always #10 clk = ~clk;
endmodule