data/full_repos/permissive/462122681/shl_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n       forever #10 clk = ~ clk; \n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   Default   :   #40 Present_state = Reg_load1a; \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load1a  :  #40 Present_state = Reg_load1b; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load1b  :  #40 Present_state = Reg_load2a; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load2a  :  #40 Present_state = Reg_load2b; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load2b  :  #40 Present_state = Reg_load3a; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load3a  :  #40 Present_state = Reg_load3b; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n   Reg_load3b  :  #40 Present_state = T0; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   T0    :  #40 Present_state = T1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   T1    :  #40 Present_state = T2; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   T2    :  #40 Present_state = T3; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   T3    :  #40 Present_state = T4; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   T4    :  #40 Present_state = T5; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout <= 1; R2in <= 1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout <= 0; R2in <= 0;      \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0;      \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout <= 1; R4in <= 1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout <= 0; R4in <= 0;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout <= 1; R5in <= 1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout <= 0; R5in <= 0;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #10 Zlowout <= 0; PCin <= 0; Read <= 0; MDRin <= 0;      \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout <= 0; IRin <= 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #10 R2out <= 1; Yin <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #15 R2out <= 0; Yin <= 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #25 R4out <= 0; Zin <= 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/462122681/shl_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #30 Zlowout <= 0; R5in <= 0;\n    ^\n%Error: data/full_repos/permissive/462122681/shl_tb.v:24: Cannot find file containing module: \'CPU_datapath\'\nCPU_datapath DUT(.Mdatain(Mdatain), .PCout(PCout), .Zhighout(Zhighout), .Zlowout(Zlowout), .MDRout(MDRout), .R2out(R2out), .R4out(R4out), .MARin(MARin), .PCin(PCin), .MDRin(MDRin), \n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/CPU_datapath\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/CPU_datapath.v\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/CPU_datapath.sv\n             CPU_datapath\n             CPU_datapath.v\n             CPU_datapath.sv\n             obj_dir/CPU_datapath\n             obj_dir/CPU_datapath.v\n             obj_dir/CPU_datapath.sv\n%Error: Exiting due to 1 error(s), 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shl_tb;       
    reg  PCout, Zlowout, Zhighout, MDRout, R2out, R4out;
    reg  MARin, PCin, MDRin, IRin, Yin, Cin, Zin;    
    reg  IncPC, Read, R5in, R2in, R4in;
	 reg  [4:0] SHL;
	 reg  R1in, R3in, R6in, R7in, R8in, R9in, R10in, R11in; 
	 reg  R12in, R13in, R14in, R15in;
    reg  clk, rst;
	 reg  LOin, HIin; 
    reg  [31:0] Mdatain;
	 
	 wire [31:0] bus_cont;
	 wire [63:0] alu_out;

	 
	
	 
parameter   Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011, Reg_load2b = 4'b0100, 
Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111, T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100;
				
reg   [3:0] Present_state = Default; 
 
CPU_datapath DUT(.Mdatain(Mdatain), .PCout(PCout), .Zhighout(Zhighout), .Zlowout(Zlowout), .MDRout(MDRout), .R2out(R2out), .R4out(R4out), .MARin(MARin), .PCin(PCin), .MDRin(MDRin), 
.IRin(IRin), .Yin(Yin), .IncPC(IncPC), .Read(Read),.AND(SHL), .R5in(R5in), .R2in(R2in), .R4in(R4in), .clk(clk), .rst(rst), .R1in(R1in), .R3in(R3in), 
.R6in(R6in), .R7in(R7in), .R8in(R8in), .R9in(R9in), .R10in(R10in), .R11in(R11in), .R12in(R12in), .R13in(R13in), .R14in(R14in), .R15in(R15in), .HIin(HIin), .LOin(LOin), 
.Zin(Zin), .Cin(Cin), .bus_cont(bus_cont), .alu_out(alu_out));
 
 initial rst = 0;

initial  
    begin 
       clk = 0; 
       forever #10 clk = ~ clk; 
end 
 
always @(posedge clk)
   begin 
      case (Present_state) 
			Default   :   #40 Present_state = Reg_load1a; 
			Reg_load1a  :  #40 Present_state = Reg_load1b; 
			Reg_load1b  :  #40 Present_state = Reg_load2a; 
			Reg_load2a  :  #40 Present_state = Reg_load2b; 
			Reg_load2b  :  #40 Present_state = Reg_load3a; 
			Reg_load3a  :  #40 Present_state = Reg_load3b; 
			Reg_load3b  :  #40 Present_state = T0; 
			T0    :  #40 Present_state = T1; 
			T1    :  #40 Present_state = T2; 
			T2    :  #40 Present_state = T3; 
			T3    :  #40 Present_state = T4; 
			T4    :  #40 Present_state = T5; 
			  
       endcase 
   end   
                                                          
always @(Present_state)
   begin 
      case (Present_state)
			Default: begin 
				PCout <= 0; Zlowout <= 0; MDRout <= 0;
				R2out <= 0; R4out <= 0; MARin <= 0;   
				Zin <= 0; PCin <=0; MDRin <= 0;   
				IRin  <= 0; Yin <= 0; IncPC <= 0;   
				Read <= 0; SHL <= 0; R5in <= 0; 
				R2in <= 0; R4in <= 0; R1in <= 0;
				R3in <= 0; R6in <= 0; R7in <= 0;
				R8in <= 0; R9in <= 0; R10in <= 0;
				R11in <= 0; R12in <= 0; R13in <= 0;
				R14in <= 0; R15in <= 0; Cin <= 0;
				Zhighout <= 0;LOin <= 0; HIin <= 0;
				Mdatain <= 32'h00000000; 
			end
			
			Reg_load1a: begin   
				Mdatain <= 32'h00000022; 
				Read <= 0; MDRin <= 0;
				#10 Read <= 1; MDRin <= 1;
				#15 Read <= 0; MDRin <= 0;    
			end 
			
			Reg_load1b: begin  
				#10 MDRout <= 1; R2in <= 1;   
				#15 MDRout <= 0; R2in <= 0;
			end
			
			Reg_load2a: begin   
				Mdatain <= 32'h00000002; 
				#10 Read <= 1; MDRin <= 1;    
				#15 Read <= 0; MDRin <= 0;      
			end
			
			Reg_load2b: begin  
				#10 MDRout <= 1; R4in <= 1;   
				#15 MDRout <= 0; R4in <= 0;
			end
			
			Reg_load3a: begin   
				Mdatain <= 32'h00000026; 
				#10 Read <= 1; MDRin <= 1;   
				#15 Read <= 0; MDRin <= 0; 
			end
			
			Reg_load3b: begin  
				#10 MDRout <= 1; R5in <= 1;   
				#15 MDRout <= 0; R5in <= 0;
			end 
 
			T0: begin
				PCout <= 1; MARin <= 1; IncPC <= 1; Zin <= 1;
				PCout <= 0; MARin <= 0; IncPC <= 0; Zin <= 0;	
			end
			
			T1: begin 
				Zlowout <= 1; PCin <= 1; Read <= 1; MDRin <= 1;

				#10 Zlowout <= 0; PCin <= 0; Read <= 0; MDRin <= 0;
			end
			
			T2: begin 
				 MDRout <= 1; IRin <= 1;
				#10 MDRout <= 0; IRin <= 0;	
			end 
 
			T3: begin 
				#10 R2out <= 1; Yin <= 1;
				#15 R2out <= 0; Yin <= 0;	
			end
			
			T4: begin 
				R4out <= 1;SHL <= 5'b00110; Zin <= 1;
				#25 R4out <= 0; Zin <= 0;	
			end
			
			T5: begin 
				 Zlowout <= 1; R5in <= 1;
				#30 Zlowout <= 0; R5in <= 0;
			end 
		endcase 
    end 
endmodule
module shl_tb;
       
    reg  PCout, Zlowout, Zhighout, MDRout, R2out, R4out;
    reg  MARin, PCin, MDRin, IRin, Yin, Cin, Zin;    
    reg  IncPC, Read, R5in, R2in, R4in;
	 reg  [4:0] SHL;
	 reg  R1in, R3in, R6in, R7in, R8in, R9in, R10in, R11in; 
	 reg  R12in, R13in, R14in, R15in;
    reg  clk, rst;
	 reg  LOin, HIin; 
    reg  [31:0] Mdatain;
	 
	 wire [31:0] bus_cont;
	 wire [63:0] alu_out;

	 
	
	 
parameter   Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011, Reg_load2b = 4'b0100, 
Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111, T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100;
				
reg   [3:0] Present_state = Default; 
 
CPU_datapath DUT(.Mdatain(Mdatain), .PCout(PCout), .Zhighout(Zhighout), .Zlowout(Zlowout), .MDRout(MDRout), .R2out(R2out), .R4out(R4out), .MARin(MARin), .PCin(PCin), .MDRin(MDRin), 
.IRin(IRin), .Yin(Yin), .IncPC(IncPC), .Read(Read),.AND(SHL), .R5in(R5in), .R2in(R2in), .R4in(R4in), .clk(clk), .rst(rst), .R1in(R1in), .R3in(R3in), 
.R6in(R6in), .R7in(R7in), .R8in(R8in), .R9in(R9in), .R10in(R10in), .R11in(R11in), .R12in(R12in), .R13in(R13in), .R14in(R14in), .R15in(R15in), .HIin(HIin), .LOin(LOin), 
.Zin(Zin), .Cin(Cin), .bus_cont(bus_cont), .alu_out(alu_out));
 
 initial rst = 0;

initial  
    begin 
       clk = 0; 
       forever #10 clk = ~ clk; 
end 
 
always @(posedge clk)
   begin 
      case (Present_state) 
			Default   :   #40 Present_state = Reg_load1a; 
			Reg_load1a  :  #40 Present_state = Reg_load1b; 
			Reg_load1b  :  #40 Present_state = Reg_load2a; 
			Reg_load2a  :  #40 Present_state = Reg_load2b; 
			Reg_load2b  :  #40 Present_state = Reg_load3a; 
			Reg_load3a  :  #40 Present_state = Reg_load3b; 
			Reg_load3b  :  #40 Present_state = T0; 
			T0    :  #40 Present_state = T1; 
			T1    :  #40 Present_state = T2; 
			T2    :  #40 Present_state = T3; 
			T3    :  #40 Present_state = T4; 
			T4    :  #40 Present_state = T5; 
			  
       endcase 
   end   
                                                          
always @(Present_state)
   begin 
      case (Present_state)
			Default: begin 
				PCout <= 0; Zlowout <= 0; MDRout <= 0;
				R2out <= 0; R4out <= 0; MARin <= 0;   
				Zin <= 0; PCin <=0; MDRin <= 0;   
				IRin  <= 0; Yin <= 0; IncPC <= 0;   
				Read <= 0; SHL <= 0; R5in <= 0; 
				R2in <= 0; R4in <= 0; R1in <= 0;
				R3in <= 0; R6in <= 0; R7in <= 0;
				R8in <= 0; R9in <= 0; R10in <= 0;
				R11in <= 0; R12in <= 0; R13in <= 0;
				R14in <= 0; R15in <= 0; Cin <= 0;
				Zhighout <= 0;LOin <= 0; HIin <= 0;
				Mdatain <= 32'h00000000; 
			end
			
			Reg_load1a: begin   
				Mdatain <= 32'h00000022; 
				Read <= 0; MDRin <= 0;
				#10 Read <= 1; MDRin <= 1;
				#15 Read <= 0; MDRin <= 0;    
			end 
			
			Reg_load1b: begin  
				#10 MDRout <= 1; R2in <= 1;   
				#15 MDRout <= 0; R2in <= 0;
			end
			
			Reg_load2a: begin   
				Mdatain <= 32'h00000002; 
				#10 Read <= 1; MDRin <= 1;    
				#15 Read <= 0; MDRin <= 0;      
			end
			
			Reg_load2b: begin  
				#10 MDRout <= 1; R4in <= 1;   
				#15 MDRout <= 0; R4in <= 0;
			end
			
			Reg_load3a: begin   
				Mdatain <= 32'h00000026; 
				#10 Read <= 1; MDRin <= 1;   
				#15 Read <= 0; MDRin <= 0; 
			end
			
			Reg_load3b: begin  
				#10 MDRout <= 1; R5in <= 1;   
				#15 MDRout <= 0; R5in <= 0;
			end 
 
			T0: begin
				PCout <= 1; MARin <= 1; IncPC <= 1; Zin <= 1;
				PCout <= 0; MARin <= 0; IncPC <= 0; Zin <= 0;	
			end
			
			T1: begin 
				Zlowout <= 1; PCin <= 1; Read <= 1; MDRin <= 1;

				#10 Zlowout <= 0; PCin <= 0; Read <= 0; MDRin <= 0;
			end
			
			T2: begin 
				 MDRout <= 1; IRin <= 1;
				#10 MDRout <= 0; IRin <= 0;	
			end 
 
			T3: begin 
				#10 R2out <= 1; Yin <= 1;
				#15 R2out <= 0; Yin <= 0;	
			end
			
			T4: begin 
				R4out <= 1;SHL <= 5'b00110; Zin <= 1;
				#25 R4out <= 0; Zin <= 0;	
			end
			
			T5: begin 
				 Zlowout <= 1; R5in <= 1;
				#30 Zlowout <= 0; R5in <= 0;
			end 
		endcase 
    end 
endmodule