data/full_repos/permissive/498662723/Verilog Language/Modules Hierarchy/module add.v
1: b'%Error: Cannot find file containing module: Language/Modules\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Modules\n             data/full_repos/permissive/498662723/Verilog/Language/Modules.v\n             data/full_repos/permissive/498662723/Verilog/Language/Modules.sv\n             Language/Modules\n             Language/Modules.v\n             Language/Modules.sv\n             obj_dir/Language/Modules\n             obj_dir/Language/Modules.v\n             obj_dir/Language/Modules.sv\n%Error: Cannot find file containing module: Hierarchy,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Hierarchy/module\n%Error: Cannot find file containing module: add.v\n%Error: Exiting due to 5 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout, cout2;
    add16 sum1 (a[15:0], b[15:0], 1'b0, sum[15:0], cout);
    add16 sum2 (a[31:16], b[31:16], cout, sum[31:16], cout2);

endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire cout, cout2;
    add16 sum1 (a[15:0], b[15:0], 1'b0, sum[15:0], cout);
    add16 sum2 (a[31:16], b[31:16], cout, sum[31:16], cout2);

endmodule