data/full_repos/permissive/522145661/Test_Arbiter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #15 CLK = !CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:51: Unsupported: Ignoring delay on this delayed statement.\n #400 RST = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50  RST = 0;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #100 HREQ_1 <= 1; HREQ_2 <= 0; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2\'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #200 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2\'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 1;HLOCK_2 <= 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Arbiter.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2\'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;\n  ^\n%Error: data/full_repos/permissive/522145661/Test_Arbiter.v:30: Cannot find file containing module: \'Arbiter\'\n Arbiter uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Arbiter\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Arbiter.v\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Arbiter.sv\n             Arbiter\n             Arbiter.v\n             Arbiter.sv\n             obj_dir/Arbiter\n             obj_dir/Arbiter.v\n             obj_dir/Arbiter.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Arbiter;


	reg CLK;
	reg RST;
	reg HREQ_1;
	reg HLOCK_1;
	reg HREQ_2;
	reg HLOCK_2;
	reg [1:0] HSPLIT;
	reg [1:0] HRESP;


	wire HGRANT_1;
	wire HGRANT_2;
	wire [1:0] HMAS;
	wire MLOCK;
	wire [1:0] SEL;
	wire AB;


	Arbiter uut (
		.CLK(CLK), 
		.RST(RST), 
		.HREQ_1(HREQ_1), 
		.HLOCK_1(HLOCK_1), 
		.HREQ_2(HREQ_2), 
		.HLOCK_2(HLOCK_2), 
		.HSPLIT(HSPLIT), 
		.HRESP(HRESP), 
		.HGRANT_1(HGRANT_1), 
		.HGRANT_2(HGRANT_2), 
		.HMAS(HMAS), 
		.MLOCK(MLOCK), 
		.SEL(SEL), 
		.AB(AB),
		.HREADY(HREADY)
	);
	
	always #15 CLK = !CLK;
	 
	initial begin
	#400 RST = 1;
	#50  RST = 0;  
	end

	initial begin

		CLK = 0;
		RST = 0;
   

		
      #100 HREQ_1 <= 1; HREQ_2 <= 0; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;
		
		#100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; 
		
		#100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;
		
		#200 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; 
		
		#100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 1;HLOCK_2 <= 0;
		
		#100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;

	end
      
endmodule
module Test_Arbiter;



	reg CLK;
	reg RST;
	reg HREQ_1;
	reg HLOCK_1;
	reg HREQ_2;
	reg HLOCK_2;
	reg [1:0] HSPLIT;
	reg [1:0] HRESP;


	wire HGRANT_1;
	wire HGRANT_2;
	wire [1:0] HMAS;
	wire MLOCK;
	wire [1:0] SEL;
	wire AB;


	Arbiter uut (
		.CLK(CLK), 
		.RST(RST), 
		.HREQ_1(HREQ_1), 
		.HLOCK_1(HLOCK_1), 
		.HREQ_2(HREQ_2), 
		.HLOCK_2(HLOCK_2), 
		.HSPLIT(HSPLIT), 
		.HRESP(HRESP), 
		.HGRANT_1(HGRANT_1), 
		.HGRANT_2(HGRANT_2), 
		.HMAS(HMAS), 
		.MLOCK(MLOCK), 
		.SEL(SEL), 
		.AB(AB),
		.HREADY(HREADY)
	);
	
	always #15 CLK = !CLK;
	 
	initial begin
	#400 RST = 1;
	#50  RST = 0;  
	end

	initial begin

		CLK = 0;
		RST = 0;
   

		
      #100 HREQ_1 <= 1; HREQ_2 <= 0; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;
		
		#100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; 
		
		#100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;
		
		#200 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0; 
		
		#100 HREQ_1 <= 1; HREQ_2 <= 1; HRESP <= 0; HSPLIT <= 0;HLOCK_1 <= 1;HLOCK_2 <= 0;
		
		#100 HREQ_1 <= 0; HREQ_2 <= 0; HRESP <= 2'b01; HSPLIT <= 0;HLOCK_1 <= 0;HLOCK_2 <= 0;

	end
      
endmodule