data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_serialdp/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_serialdp,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_serialdp/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module fsm_state_transition (
    input wire clk,
    input wire in,
    input wire reset,
    input wire [2:0] next_state,
    output reg [4:0] bits,
    output reg [2:0] state,
    output reg [9:0] data
);

  parameter STATE_START = 3'b001;
  parameter STATE_DATA = 3'b010;
  parameter STATE_STOP = 3'b011;

  always @(posedge clk) begin
    if (reset) state <= STATE_START;
    else if (clk) begin
      state <= next_state;

      case (state)
        STATE_START, STATE_STOP: bits <= 4'd0;
        STATE_DATA: bits <= (bits < 4'd9) ? bits + 1'b1 : bits;
      endcase

      data <= data >> 1;
      data[9] <= in;
    end
  end
endmodule
module fsm_state_transition (
    input wire clk,
    input wire in,
    input wire reset,
    input wire [2:0] next_state,
    output reg [4:0] bits,
    output reg [2:0] state,
    output reg [9:0] data
);


  parameter STATE_START = 3'b001;
  parameter STATE_DATA = 3'b010;
  parameter STATE_STOP = 3'b011;

  always @(posedge clk) begin
    if (reset) state <= STATE_START;
    else if (clk) begin
      state <= next_state;

      case (state)
        STATE_START, STATE_STOP: bits <= 4'd0;
        STATE_DATA: bits <= (bits < 4'd9) ? bits + 1'b1 : bits;
      endcase

      data <= data >> 1;
      data[9] <= in;
    end
  end
endmodule