data/full_repos/permissive/528472518/verilog/rtl/yonga_can_pulse_gen.v
data/verilator_xmls/edee8da1-7500-4724-9f6c-bdee8b3ab55b.xml
module yonga_can_pulse_gen(
    input wire i_pulse_gen_clk,
    input wire i_pulse_gen_rst,

    input wire i_pulse_gen_config_en,

    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_prescaler_val,
    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg1_time_quanta_val,
    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg2_time_quanta_val,

    output wire o_pulse_gen_synced,

    output wire o_pulse_gen_drive_pulse,
    output wire o_pulse_gen_sample_pulse
 );


    parameter STATE_RESET = 0, STATE_SYNC_SEG = 1, STATE_PROP_SEG = 2, STATE_PHASE_SEG1 = 3, STATE_PHASE_SEG2 = 4;



    reg [3:0] state_reg;


    reg [`NUM_OF_QUANTUM_BITS-1:0] nom_time_qtm_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] qtm_counter_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg1_counter_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg2_counter_reg;


    reg sync_reg;
    reg drive_pulse_reg;
    reg sample_pulse_reg;

    always@(posedge i_pulse_gen_clk) begin
        if(i_pulse_gen_rst == 1'b1) begin
            nom_time_qtm_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            sync_reg <= 1'b0;
            drive_pulse_reg <= 1'b0;
            sample_pulse_reg <= 1'b0;
            state_reg <= STATE_RESET;
        end
        else begin
            case(state_reg)
                STATE_RESET: begin
                    if(i_pulse_gen_config_en) begin
                        nom_time_qtm_reg <= i_pulse_gen_prescaler_val;
                        state_reg <= STATE_SYNC_SEG;
                    end
                end
                STATE_SYNC_SEG: begin
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        drive_pulse_reg <= 1'b1;
                        state_reg <= STATE_PHASE_SEG1;
                    end
                end


                STATE_PHASE_SEG1: begin
                    drive_pulse_reg <= 1'b0;
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        phase_seg1_counter_reg <= phase_seg1_counter_reg + 1'b1;
                        if(phase_seg1_counter_reg == i_pulse_gen_phase_seg1_time_quanta_val) begin
                            phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                            sample_pulse_reg <= 1'b1;
                            state_reg <= STATE_PHASE_SEG2;
                        end
                    end
                end
                STATE_PHASE_SEG2: begin
                    sample_pulse_reg <= 1'b0;
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        phase_seg2_counter_reg <= phase_seg2_counter_reg + 1'b1;
                        if(phase_seg2_counter_reg == i_pulse_gen_phase_seg2_time_quanta_val) begin
                            phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                            sync_reg <= 1'b1;
                            state_reg <= STATE_SYNC_SEG;
                        end
                    end
                end
            endcase
        end
    end

    assign o_pulse_gen_synced = sync_reg;
    assign o_pulse_gen_drive_pulse = drive_pulse_reg;
    assign o_pulse_gen_sample_pulse = sample_pulse_reg;

endmodule
module yonga_can_pulse_gen(
    input wire i_pulse_gen_clk,
    input wire i_pulse_gen_rst,

    input wire i_pulse_gen_config_en,

    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_prescaler_val,
    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg1_time_quanta_val,
    input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg2_time_quanta_val,

    output wire o_pulse_gen_synced,

    output wire o_pulse_gen_drive_pulse,
    output wire o_pulse_gen_sample_pulse
 );



    parameter STATE_RESET = 0, STATE_SYNC_SEG = 1, STATE_PROP_SEG = 2, STATE_PHASE_SEG1 = 3, STATE_PHASE_SEG2 = 4;



    reg [3:0] state_reg;


    reg [`NUM_OF_QUANTUM_BITS-1:0] nom_time_qtm_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] qtm_counter_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg1_counter_reg;
    reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg2_counter_reg;


    reg sync_reg;
    reg drive_pulse_reg;
    reg sample_pulse_reg;

    always@(posedge i_pulse_gen_clk) begin
        if(i_pulse_gen_rst == 1'b1) begin
            nom_time_qtm_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
            sync_reg <= 1'b0;
            drive_pulse_reg <= 1'b0;
            sample_pulse_reg <= 1'b0;
            state_reg <= STATE_RESET;
        end
        else begin
            case(state_reg)
                STATE_RESET: begin
                    if(i_pulse_gen_config_en) begin
                        nom_time_qtm_reg <= i_pulse_gen_prescaler_val;
                        state_reg <= STATE_SYNC_SEG;
                    end
                end
                STATE_SYNC_SEG: begin
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        drive_pulse_reg <= 1'b1;
                        state_reg <= STATE_PHASE_SEG1;
                    end
                end


                STATE_PHASE_SEG1: begin
                    drive_pulse_reg <= 1'b0;
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        phase_seg1_counter_reg <= phase_seg1_counter_reg + 1'b1;
                        if(phase_seg1_counter_reg == i_pulse_gen_phase_seg1_time_quanta_val) begin
                            phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                            sample_pulse_reg <= 1'b1;
                            state_reg <= STATE_PHASE_SEG2;
                        end
                    end
                end
                STATE_PHASE_SEG2: begin
                    sample_pulse_reg <= 1'b0;
                    qtm_counter_reg <= qtm_counter_reg + 1'b1;
                    if(qtm_counter_reg == nom_time_qtm_reg) begin
                        qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                        phase_seg2_counter_reg <= phase_seg2_counter_reg + 1'b1;
                        if(phase_seg2_counter_reg == i_pulse_gen_phase_seg2_time_quanta_val) begin
                            phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
                            sync_reg <= 1'b1;
                            state_reg <= STATE_SYNC_SEG;
                        end
                    end
                end
            endcase
        end
    end

    assign o_pulse_gen_synced = sync_reg;
    assign o_pulse_gen_drive_pulse = drive_pulse_reg;
    assign o_pulse_gen_sample_pulse = sample_pulse_reg;

endmodule