data/full_repos/permissive/431682734/LabL/LabL2.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:3: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    reg [1:0] a, b, expect;\n                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:3: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n    reg [1:0] a, b, expect;\n                          ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            expect[0] = (a[0] & ~c) | (b[0] & c);  \n            ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:18: syntax error, unexpected \'[\'\n            expect[0] = (a[0] & ~c) | (b[0] & c);  \n                  ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:19: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            expect[1] = (a[1] & ~c) | (b[1] & c);  \n            ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabL/LabL2.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #1;  \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:23: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            if (expect === z)\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL2.v:23: syntax error, unexpected ===, expecting TYPE-IDENTIFIER\n            if (expect === z)\n                       ^~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labL;
    reg c;
    reg [1:0] a, b, expect;
    wire [1:0] z;
    integer i, j, k;


    yMux2 mine[1:0](z, a, b, c);


    initial begin
        repeat (10)
        begin
            i = $random % 4;
            j = $random % 4;
            k = $random % 2;
            a = i; b = j; c = k;
            expect[0] = (a[0] & ~c) | (b[0] & c);
            expect[1] = (a[1] & ~c) | (b[1] & c);
            #1;


            if (expect === z)
                $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
            else
                $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
        end
    $finish;
    end
endmodule
module labL;

    reg c;
    reg [1:0] a, b, expect;
    wire [1:0] z;
    integer i, j, k;


    yMux2 mine[1:0](z, a, b, c);


    initial begin
        repeat (10)
        begin
            i = $random % 4;
            j = $random % 4;
            k = $random % 2;
            a = i; b = j; c = k;
            expect[0] = (a[0] & ~c) | (b[0] & c);
            expect[1] = (a[1] & ~c) | (b[1] & c);
            #1;


            if (expect === z)
                $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
            else
                $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
        end
    $finish;
    end
endmodule