data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:74: Define or directive not defined: \'`x_or_0\'\n            ld2st_wr_pvld_in <= `x_or_0;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:74: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ld2st_wr_pvld_in <= `x_or_0;\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:110: Define or directive not defined: \'`x_or_0\'\n            ld2st_wr_count <= {5{`x_or_0}};\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:110: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            ld2st_wr_count <= {5{`x_or_0}};\n                                        ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:163: Define or directive not defined: \'`x_or_0\'\n            ld2st_rd_adr <= {5{`x_or_0}};\n                               ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:163: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            ld2st_rd_adr <= {5{`x_or_0}};\n                                      ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:200: Define or directive not defined: \'`x_or_0\'\n            ld2st_rd_count_p <= {5{`x_or_0}};\n                                   ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:200: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            ld2st_rd_count_p <= {5{`x_or_0}};\n                                          ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:221: Define or directive not defined: \'`x_or_0\'\n        ld2st_rd_pd <= {161{`x_or_0}};\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:221: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        ld2st_rd_pd <= {161{`x_or_0}};\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:567: Define or directive not defined: \'`x_or_0\'\n    default: dout = {161{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_BDMA_cq.v:567: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {161{`x_or_0}};\n                                ^\n%Error: Exiting due to 13 error(s)\n'
module vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 (
   Wa0, we0, Di0,
   Ra0, Do0
   );
input [4:0] Wa0;
input we0;
input [160:0] Di0;
input [4:0] Ra0;
output [160:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 161'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [160:0] mem[19:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [160:0] Q0 = mem[0];
wire [160:0] Q1 = mem[1];
wire [160:0] Q2 = mem[2];
wire [160:0] Q3 = mem[3];
wire [160:0] Q4 = mem[4];
wire [160:0] Q5 = mem[5];
wire [160:0] Q6 = mem[6];
wire [160:0] Q7 = mem[7];
wire [160:0] Q8 = mem[8];
wire [160:0] Q9 = mem[9];
wire [160:0] Q10 = mem[10];
wire [160:0] Q11 = mem[11];
wire [160:0] Q12 = mem[12];
wire [160:0] Q13 = mem[13];
wire [160:0] Q14 = mem[14];
wire [160:0] Q15 = mem[15];
wire [160:0] Q16 = mem[16];
wire [160:0] Q17 = mem[17];
wire [160:0] Q18 = mem[18];
wire [160:0] Q19 = mem[19];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule
module vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 (
   Wa0, we0, Di0,
   Ra0, Do0
   );

input [4:0] Wa0;
input we0;
input [160:0] Di0;
input [4:0] Ra0;
output [160:0] Do0;

`ifdef SPYGLASS_FLOPRAM
assign Do0 = 161'd0;
wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0);
`endif

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg [160:0] mem[19:0];

`ifdef EMU_EXPAND_FLOPRAM_MEM
wire [160:0] Q0 = mem[0];
wire [160:0] Q1 = mem[1];
wire [160:0] Q2 = mem[2];
wire [160:0] Q3 = mem[3];
wire [160:0] Q4 = mem[4];
wire [160:0] Q5 = mem[5];
wire [160:0] Q6 = mem[6];
wire [160:0] Q7 = mem[7];
wire [160:0] Q8 = mem[8];
wire [160:0] Q9 = mem[9];
wire [160:0] Q10 = mem[10];
wire [160:0] Q11 = mem[11];
wire [160:0] Q12 = mem[12];
wire [160:0] Q13 = mem[13];
wire [160:0] Q14 = mem[14];
wire [160:0] Q15 = mem[15];
wire [160:0] Q16 = mem[16];
wire [160:0] Q17 = mem[17];
wire [160:0] Q18 = mem[18];
wire [160:0] Q19 = mem[19];
`endif

always @(*) begin
  if ( we0 == 1'b1 ) begin
    #0.1;
    mem[Wa0] = Di0;
  end
end
assign Do0 = mem[Ra0];
`endif
`endif




endmodule