data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:11: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:54: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:59: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:63: Unsupported: Ignoring delay on this delayed statement.\n        rst_n = 1\'b1; #1; en = 1\'b1;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:64: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:70: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:75: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:22: Can\'t find definition of \'state\' in dotted variable: \'tb_rtl_init.dut.state\'\n            if (tb_rtl_init.dut.state !== exp_state) begin\n                                ^~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:23: Can\'t find definition of \'state\' in dotted variable: \'tb_rtl_init.dut.state\'\n                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_init.dut.state);\n                                                                                                         ^~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:26: Can\'t find definition of \'rdy\' in dotted variable: \'tb_rtl_init.dut.rdy\'\n            if (tb_rtl_init.dut.rdy !== exp_rdy) begin\n                                ^~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:27: Can\'t find definition of \'rdy\' in dotted variable: \'tb_rtl_init.dut.rdy\'\n                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_init.dut.rdy);\n                                                                                                   ^~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:30: Can\'t find definition of \'addr\' in dotted variable: \'tb_rtl_init.dut.addr\'\n            if (tb_rtl_init.dut.addr !== exp_addr) begin\n                                ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:31: Can\'t find definition of \'addr\' in dotted variable: \'tb_rtl_init.dut.addr\'\n                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_init.dut.addr);\n                                                                                                      ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:34: Can\'t find definition of \'wrdata\' in dotted variable: \'tb_rtl_init.dut.wrdata\'\n            if (tb_rtl_init.dut.wrdata !== exp_wrdata) begin\n                                ^~~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:35: Can\'t find definition of \'wrdata\' in dotted variable: \'tb_rtl_init.dut.wrdata\'\n                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_init.dut.wrdata);\n                                                                                                            ^~~~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:38: Can\'t find definition of \'wren\' in dotted variable: \'tb_rtl_init.dut.wren\'\n            if (tb_rtl_init.dut.wren !== exp_wren) begin\n                                ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task1/tb_rtl_init.sv:39: Can\'t find definition of \'wren\' in dotted variable: \'tb_rtl_init.dut.wren\'\n                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_init.dut.wren);\n                                                                                                      ^~~~\n%Error: Exiting due to 10 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_init();

    logic clk, rst_n, en, rdy, wren, err;
    logic [7:0] addr, wrdata;
    integer i;

    init dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input [1:0] exp_state;
        input exp_rdy;
        input [7:0] exp_addr, exp_wrdata;
        input exp_wren;
        begin
            $display("CASE %d", index);
            if (tb_rtl_init.dut.state !== exp_state) begin
                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_init.dut.state);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_init.dut.rdy);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.addr !== exp_addr) begin
                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_init.dut.addr);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.wrdata !== exp_wrdata) begin
                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_init.dut.wrdata);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.wren !== exp_wren) begin
                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_init.dut.wren);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE 1'b0
    `define WRITE 1'b1

    initial begin
        err = 1'b0;


        rst_n = 1'bx; en = 1'bx;
        #10;
        validator(1, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        rst_n = 1'b0;
        #10;
        validator(2, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);
        

        rst_n = 1'b1; #1; en = 1'b1;
        #10;
        validator(3, `WRITE, 1'b0, 8'b0, 8'b0, 1'b1);


        en = 1'b0;
        for (int i = 1; i < 256; i++) begin
            #10;
            validator(i, `WRITE, 1'b0, i, i, 1'b1);
        end


        #20;
        validator(5, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_rtl_init();


    logic clk, rst_n, en, rdy, wren, err;
    logic [7:0] addr, wrdata;
    integer i;

    init dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input [1:0] exp_state;
        input exp_rdy;
        input [7:0] exp_addr, exp_wrdata;
        input exp_wren;
        begin
            $display("CASE %d", index);
            if (tb_rtl_init.dut.state !== exp_state) begin
                $display("ERROR A: Expected state is %d, actual state is %d", exp_state, tb_rtl_init.dut.state);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_rtl_init.dut.rdy);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.addr !== exp_addr) begin
                $display("ERROR C: Expected addr is %d, actual addr is %d", exp_addr, tb_rtl_init.dut.addr);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.wrdata !== exp_wrdata) begin
                $display("ERROR D: Expected wrdata is %d, actual wrdata is %d", exp_wrdata, tb_rtl_init.dut.wrdata);
                err = 1'b1;
            end
            if (tb_rtl_init.dut.wren !== exp_wren) begin
                $display("ERROR E: Expected wren is %d, actual wren is %d", exp_wren, tb_rtl_init.dut.wren);
                err = 1'b1;
            end
        end
    endtask


    `define IDLE 1'b0
    `define WRITE 1'b1

    initial begin
        err = 1'b0;


        rst_n = 1'bx; en = 1'bx;
        #10;
        validator(1, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);


        rst_n = 1'b0;
        #10;
        validator(2, `IDLE, 1'b0, 8'b0, 8'b0, 1'b0);
        

        rst_n = 1'b1; #1; en = 1'b1;
        #10;
        validator(3, `WRITE, 1'b0, 8'b0, 8'b0, 1'b1);


        en = 1'b0;
        for (int i = 1; i < 256; i++) begin
            #10;
            validator(i, `WRITE, 1'b0, i, i, 1'b1);
        end


        #20;
        validator(5, `IDLE, 1'b1, 8'b0, 8'b0, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule