data/full_repos/permissive/434840709/week10/9.v
data/verilator_xmls/cddf2044-3451-43ec-8caa-c4d28b2ead22.xml
module top_module (

                input in1,

                input in2,

                output out
                
);
                assign out = in1 * ~in2;

endmodule
module top_module (

                input in1,

                input in2,

                output out
                
);

                assign out = in1 * ~in2;

endmodule