data/full_repos/permissive/502544928/ra_packetizer.v
1: b"%Error: data/full_repos/permissive/502544928/ra_packetizer.v:126: Cannot find file containing module: 'ra_packetizer_core'\nra_packetizer_core #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, \n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_packetizer_core\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_packetizer_core.v\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_packetizer_core.sv\n             ra_packetizer_core\n             ra_packetizer_core.v\n             ra_packetizer_core.sv\n             obj_dir/ra_packetizer_core\n             obj_dir/ra_packetizer_core.v\n             obj_dir/ra_packetizer_core.sv\n%Error: data/full_repos/permissive/502544928/ra_packetizer.v:151: Cannot find file containing module: 'ra_packetizer_cache'\nra_packetizer_cache #(CORE, DATA_WIDTH, ADDRESS_BITS, VC_BITS, \n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502544928/ra_packetizer.v:176: Cannot find file containing module: 'ra_packetizer_network'\nra_packetizer_network #(CORE, DATA_WIDTH, ADDRESS_BITS, IN_PORTS, OUT_PORTS, VC_BITS, \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ra_packetizer #(parameter CORE = 0, DATA_WIDTH = 32, ADDRESS_BITS = 32, 
				       REAL_ADDR_BITS = 16, MEM_ADDR_BITS = 20, 
					   IN_PORTS = 1, OUT_PORTS = 1, VC_BITS = 1, VC_DEPTH_BITS = 4,
                       ID_BITS = 4, EXTRA  = 2, TYPE_BITS = 2) ( 
					
				     clock, reset, 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full  
				     
);
localparam VC_PER_PORTS  = (1 << VC_BITS); 
localparam FLOW_BITS     = (2*ID_BITS) + EXTRA;  
localparam FLIT_WIDTH    = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;

input clock, reset; 

input core2net_iRead,    core2net_iWrite;
input [ADDRESS_BITS-1:0] core2net_iAddr; 
input [DATA_WIDTH-1:0]   core2net_iData;  
					 				     
input core2net_dRead,    core2net_dWrite;
input [ADDRESS_BITS-1:0] core2net_dAddr; 
input [DATA_WIDTH-1:0]   core2net_dData; 

input cache2net_iValid , cache2net_iReady;
input [ADDRESS_BITS-1:0] cache2net_iAddr;
input [DATA_WIDTH-1:0]   cache2net_iData;

input cache2net_dValid,  cache2net_dReady;
input [ADDRESS_BITS-1:0] cache2net_dAddr;
input [DATA_WIDTH-1:0]   cache2net_dData;

output net2cache_iRead, net2cache_iWrite;
output [ADDRESS_BITS-1:0]net2cache_iAddr; 
output [DATA_WIDTH-1:0]   net2cache_iData;
				     
output net2cache_dRead, net2cache_dWrite; 
output [ADDRESS_BITS-1:0] net2cache_dAddr;
output [DATA_WIDTH-1:0]   net2cache_dData;

output [ADDRESS_BITS-1:0] net2core_iAddr; 
output [DATA_WIDTH-1:0]   net2core_iData;
output net2core_iValid,   net2core_iReady;
				     
output [ADDRESS_BITS-1:0] net2core_dAddr; 
output [DATA_WIDTH-1:0]   net2core_dData; 
output net2core_dValid,   net2core_dReady;
	
output [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit;
output [IN_PORTS-1: 0] v_from_core;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_empty;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_full; 
  
input  [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit;
input  [OUT_PORTS-1: 0] v_to_core;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_empty;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_full;

wire [ID_BITS - 1: 0] core_ID = CORE; 

wire [FLIT_WIDTH -1:0] p_flit_to_send;
wire pv_send_flit; 				 
wire [FLIT_WIDTH -1:0] p_flit_received; 
wire pv_rec_flit; 
wire p_ready;

wire [FLIT_WIDTH -1:0] c_flit_to_send;
wire cv_send_flit; 				 
wire [FLIT_WIDTH -1:0] c_flit_received; 
wire cv_rec_flit; 
wire c_ready;

ra_packetizer_core #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, 
					VC_BITS, ID_BITS, EXTRA, TYPE_BITS) ra_core( 
					
				     clock, reset, 
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     p_flit_to_send, pv_send_flit, 
  					 p_flit_received, pv_rec_flit, 
					 p_ready
				     
);

ra_packetizer_cache #(CORE, DATA_WIDTH, ADDRESS_BITS, VC_BITS, 
                    ID_BITS, EXTRA, TYPE_BITS) ra_cache ( 
					
				     clock, reset, 
					 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     c_flit_to_send, cv_send_flit, 
  					 c_flit_received, cv_rec_flit, 
					 c_ready
				     
);

ra_packetizer_network #(CORE, DATA_WIDTH, ADDRESS_BITS, IN_PORTS, OUT_PORTS, VC_BITS, 
					VC_DEPTH_BITS, ID_BITS, EXTRA, TYPE_BITS) ra_network ( 
					
				     clock, reset, 


				     c_flit_to_send,  cv_send_flit, 
  					 c_flit_received, cv_rec_flit, 
					 c_ready,
					 

				     p_flit_to_send, pv_send_flit, 
  					 p_flit_received, pv_rec_flit, 
					 p_ready, 
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full  
				     
);


  
endmodule
module ra_packetizer #(parameter CORE = 0, DATA_WIDTH = 32, ADDRESS_BITS = 32, 
				       REAL_ADDR_BITS = 16, MEM_ADDR_BITS = 20, 
					   IN_PORTS = 1, OUT_PORTS = 1, VC_BITS = 1, VC_DEPTH_BITS = 4,
                       ID_BITS = 4, EXTRA  = 2, TYPE_BITS = 2) ( 
					
				     clock, reset, 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full  
				     
);

localparam VC_PER_PORTS  = (1 << VC_BITS); 
localparam FLOW_BITS     = (2*ID_BITS) + EXTRA;  
localparam FLIT_WIDTH    = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;

input clock, reset; 

input core2net_iRead,    core2net_iWrite;
input [ADDRESS_BITS-1:0] core2net_iAddr; 
input [DATA_WIDTH-1:0]   core2net_iData;  
					 				     
input core2net_dRead,    core2net_dWrite;
input [ADDRESS_BITS-1:0] core2net_dAddr; 
input [DATA_WIDTH-1:0]   core2net_dData; 

input cache2net_iValid , cache2net_iReady;
input [ADDRESS_BITS-1:0] cache2net_iAddr;
input [DATA_WIDTH-1:0]   cache2net_iData;

input cache2net_dValid,  cache2net_dReady;
input [ADDRESS_BITS-1:0] cache2net_dAddr;
input [DATA_WIDTH-1:0]   cache2net_dData;

output net2cache_iRead, net2cache_iWrite;
output [ADDRESS_BITS-1:0]net2cache_iAddr; 
output [DATA_WIDTH-1:0]   net2cache_iData;
				     
output net2cache_dRead, net2cache_dWrite; 
output [ADDRESS_BITS-1:0] net2cache_dAddr;
output [DATA_WIDTH-1:0]   net2cache_dData;

output [ADDRESS_BITS-1:0] net2core_iAddr; 
output [DATA_WIDTH-1:0]   net2core_iData;
output net2core_iValid,   net2core_iReady;
				     
output [ADDRESS_BITS-1:0] net2core_dAddr; 
output [DATA_WIDTH-1:0]   net2core_dData; 
output net2core_dValid,   net2core_dReady;
	
output [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit;
output [IN_PORTS-1: 0] v_from_core;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_empty;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_full; 
  
input  [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit;
input  [OUT_PORTS-1: 0] v_to_core;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_empty;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_full;

wire [ID_BITS - 1: 0] core_ID = CORE; 

wire [FLIT_WIDTH -1:0] p_flit_to_send;
wire pv_send_flit; 				 
wire [FLIT_WIDTH -1:0] p_flit_received; 
wire pv_rec_flit; 
wire p_ready;

wire [FLIT_WIDTH -1:0] c_flit_to_send;
wire cv_send_flit; 				 
wire [FLIT_WIDTH -1:0] c_flit_received; 
wire cv_rec_flit; 
wire c_ready;

ra_packetizer_core #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, 
					VC_BITS, ID_BITS, EXTRA, TYPE_BITS) ra_core( 
					
				     clock, reset, 
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     p_flit_to_send, pv_send_flit, 
  					 p_flit_received, pv_rec_flit, 
					 p_ready
				     
);

ra_packetizer_cache #(CORE, DATA_WIDTH, ADDRESS_BITS, VC_BITS, 
                    ID_BITS, EXTRA, TYPE_BITS) ra_cache ( 
					
				     clock, reset, 
					 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     c_flit_to_send, cv_send_flit, 
  					 c_flit_received, cv_rec_flit, 
					 c_ready
				     
);

ra_packetizer_network #(CORE, DATA_WIDTH, ADDRESS_BITS, IN_PORTS, OUT_PORTS, VC_BITS, 
					VC_DEPTH_BITS, ID_BITS, EXTRA, TYPE_BITS) ra_network ( 
					
				     clock, reset, 


				     c_flit_to_send,  cv_send_flit, 
  					 c_flit_received, cv_rec_flit, 
					 c_ready,
					 

				     p_flit_to_send, pv_send_flit, 
  					 p_flit_received, pv_rec_flit, 
					 p_ready, 
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full  
				     
);


  
endmodule