data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v
1: b'%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:72: Cannot find include file: DFFRAM/DFFRAM.v\n`include "DFFRAM/DFFRAM.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492704601/verilog/dv/user_pwm,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v\n             data/full_repos/permissive/492704601/verilog/dv/user_pwm,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v.v\n             data/full_repos/permissive/492704601/verilog/dv/user_pwm,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v.sv\n             DFFRAM/DFFRAM.v\n             DFFRAM/DFFRAM.v.v\n             DFFRAM/DFFRAM.v.sv\n             obj_dir/DFFRAM/DFFRAM.v\n             obj_dir/DFFRAM/DFFRAM.v.v\n             obj_dir/DFFRAM/DFFRAM.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:137: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:140: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:144: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:144: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:144: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                        ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:147: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h03F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:147: Define or directive not defined: \'`PINMUX_GPIO_MULTI_FUNC\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h03F);\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:147: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h03F);\n                                                                             ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:149: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:154: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:154: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:154: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:157: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:157: Define or directive not defined: \'`PINMUX_GBL_CFG1\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:157: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:160: syntax error, unexpected \'@\'\n         repeat (200) @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:161: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:161: Define or directive not defined: \'`WBHOST_BANK_SEL\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:161: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:165: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,\'h0000_0000);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:165: Define or directive not defined: \'`PINMUX_CFG_PWM0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,\'h0000_0000);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:165: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,\'h0000_0000);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:166: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,\'h0000_0001);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:166: Define or directive not defined: \'`PINMUX_CFG_PWM1\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,\'h0000_0001);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:166: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,\'h0000_0001);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:167: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,\'h0001_0001);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:167: Define or directive not defined: \'`PINMUX_CFG_PWM2\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,\'h0001_0001);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:167: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,\'h0001_0001);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:168: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,\'h0001_0002);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:168: Define or directive not defined: \'`PINMUX_CFG_PWM3\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,\'h0001_0002);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:168: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,\'h0001_0002);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:169: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,\'h0002_0002);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:169: Define or directive not defined: \'`PINMUX_CFG_PWM4\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,\'h0002_0002);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:169: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,\'h0002_0002);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:170: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,\'h0002_0003);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:170: Define or directive not defined: \'`PINMUX_CFG_PWM5\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,\'h0002_0003);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:170: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,\'h0002_0003);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:173: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clock);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:217: Unsupported: Verilog 1995 force\n   force clock_mon = pwm0;\n   ^~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:219: Unsupported: Verilog 1995 release\n   release clock_mon;\n   ^~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:221: Unsupported: Verilog 1995 force\n   force clock_mon = pwm1;\n   ^~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:223: Unsupported: Verilog 1995 release\n   release clock_mon;\n   ^~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:225: Unsupported: Verilog 1995 force\n   force clock_mon = pwm2;\n   ^~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:227: Unsupported: Verilog 1995 release\n   release clock_mon;\n   ^~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:229: Unsupported: Verilog 1995 force\n   force clock_mon = pwm3;\n   ^~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:231: Unsupported: Verilog 1995 release\n   release clock_mon;\n   ^~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:233: Unsupported: Verilog 1995 force\n   force clock_mon = pwm4;\n   ^~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:235: Unsupported: Verilog 1995 release\n   release clock_mon;\n   ^~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_pwm/user_pwm_tb.v:237: Unsupported: Verilog 1995 force\n   force clock_mon = pwm5;\n   ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module user_pwm_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
	reg [31:0] OneMsPeriod;
        integer    test_step;
        wire       clock_mon;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		OneMsPeriod = 1000;
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, `TB_GLBL);
	   	$dumpvars(0, `TB_GLBL.u_top.u_wb_host);
	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
	   	$dumpvars(0, `TB_GLBL.u_top.u_intercon);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F);

	        repeat (2) @(posedge clock);
		#1;



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);

		test_fail = 0;
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);

	        $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
	        test_step = 1;
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003);
	        pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);

		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: PWM Mode (GL) Passed");
		   `else
		       $display("Monitor: PWM Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: PWM Mode (GL) Failed");
		    `else
		        $display("Monitor: PWM Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

wire pwm0 = io_out[4];
wire pwm1 = io_out[8];
wire pwm2 = io_out[9];
wire pwm3 = io_out[12];
wire pwm4 = io_out[13];
wire pwm5 = io_out[14];


task pwm_monitor;
input [31:0] pwm0_period;
input [31:0] pwm1_period;
input [31:0] pwm2_period;
input [31:0] pwm3_period;
input [31:0] pwm4_period;
input [31:0] pwm5_period;
begin
   force clock_mon = pwm0;
   check_clock_period("PWM0 Clock",pwm0_period);
   release clock_mon;

   force clock_mon = pwm1;
   check_clock_period("PWM1 Clock",pwm1_period);
   release clock_mon;

   force clock_mon = pwm2;
   check_clock_period("PWM2 Clock",pwm2_period);
   release clock_mon;

   force clock_mon = pwm3;
   check_clock_period("PWM3 Clock",pwm3_period);
   release clock_mon;

   force clock_mon = pwm4;
   check_clock_period("PWM4 Clock",pwm4_period);
   release clock_mon;

   force clock_mon = pwm5;
   check_clock_period("PWM5 Clock",pwm5_period);
   release clock_mon;
end
endtask





task check_clock_period;
input [127:0] clk_name;
input [31:0] clk_period;
time prev_t, next_t, periodd;
begin
    $timeformat(-12,3,"ns",10);
   repeat(1) @(posedge clock_mon);
   repeat(1) @(posedge clock_mon);
   prev_t  = $realtime;
   repeat(2) @(posedge clock_mon);
   next_t  = $realtime;
   periodd = (next_t-prev_t)/2;
   periodd = (periodd)/1e3;
   if(clk_period != periodd) begin
       $display("STATUS: FAIL => %s Exp Period: %d ms Rxd: %d ms",clk_name,clk_period,periodd);
       test_fail = 1;
   end else begin
       $display("STATUS: PASS => %s  Period: %d ms ",clk_name,clk_period);
   end
end
endtask

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    






task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     `TB_GLBL.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif



endmodule
module user_pwm_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
	reg [31:0] OneMsPeriod;
        integer    test_step;
        wire       clock_mon;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		OneMsPeriod = 1000;
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(1, `TB_GLBL);
	   	$dumpvars(0, `TB_GLBL.u_top.u_wb_host);
	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
	   	$dumpvars(0, `TB_GLBL.u_top.u_intercon);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F);

	        repeat (2) @(posedge clock);
		#1;



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);

		test_fail = 0;
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);

	        $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
	        test_step = 1;
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002);
                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003);
	        pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);

		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: PWM Mode (GL) Passed");
		   `else
		       $display("Monitor: PWM Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: PWM Mode (GL) Failed");
		    `else
		        $display("Monitor: PWM Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

wire pwm0 = io_out[4];
wire pwm1 = io_out[8];
wire pwm2 = io_out[9];
wire pwm3 = io_out[12];
wire pwm4 = io_out[13];
wire pwm5 = io_out[14];


task pwm_monitor;
input [31:0] pwm0_period;
input [31:0] pwm1_period;
input [31:0] pwm2_period;
input [31:0] pwm3_period;
input [31:0] pwm4_period;
input [31:0] pwm5_period;
begin
   force clock_mon = pwm0;
   check_clock_period("PWM0 Clock",pwm0_period);
   release clock_mon;

   force clock_mon = pwm1;
   check_clock_period("PWM1 Clock",pwm1_period);
   release clock_mon;

   force clock_mon = pwm2;
   check_clock_period("PWM2 Clock",pwm2_period);
   release clock_mon;

   force clock_mon = pwm3;
   check_clock_period("PWM3 Clock",pwm3_period);
   release clock_mon;

   force clock_mon = pwm4;
   check_clock_period("PWM4 Clock",pwm4_period);
   release clock_mon;

   force clock_mon = pwm5;
   check_clock_period("PWM5 Clock",pwm5_period);
   release clock_mon;
end
endtask





task check_clock_period;
input [127:0] clk_name;
input [31:0] clk_period;
time prev_t, next_t, periodd;
begin
    $timeformat(-12,3,"ns",10);
   repeat(1) @(posedge clock_mon);
   repeat(1) @(posedge clock_mon);
   prev_t  = $realtime;
   repeat(2) @(posedge clock_mon);
   next_t  = $realtime;
   periodd = (next_t-prev_t)/2;
   periodd = (periodd)/1e3;
   if(clk_period != periodd) begin
       $display("STATUS: FAIL => %s Exp Period: %d ms Rxd: %d ms",clk_name,clk_period,periodd);
       test_fail = 1;
   end else begin
       $display("STATUS: PASS => %s  Period: %d ms ",clk_name,clk_period);
   end
end
endtask

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    






task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     `TB_GLBL.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif



endmodule