data/full_repos/permissive/431550602/sources_1/uart_baudrate_generator.v
data/verilator_xmls/ffd3793d-fa4d-46b2-b626-a2a8e4756434.xml
module uart_baudrate_generator #(parameter divisior = 54)
    (  
    input clk, reset,
    output reg uart_tick = 1'b0
    );
    
    reg [5:0] counter = 6'b0;
    
    always@ (posedge clk) begin
        if (reset) begin
            counter <= 6'b0;
            uart_tick <= 1'b0; 
        end            
        else if (counter == divisior - 1) begin
            counter <= 6'b0;
            uart_tick <= 1'b1;
        end
        else begin
            counter <= counter + 6'b1;
            uart_tick <= 1'b0;                
        end                                                   
    end
    
endmodule
module uart_baudrate_generator #(parameter divisior = 54)
    (  
    input clk, reset,
    output reg uart_tick = 1'b0
    );

    
    reg [5:0] counter = 6'b0;
    
    always@ (posedge clk) begin
        if (reset) begin
            counter <= 6'b0;
            uart_tick <= 1'b0; 
        end            
        else if (counter == divisior - 1) begin
            counter <= 6'b0;
            uart_tick <= 1'b1;
        end
        else begin
            counter <= counter + 6'b1;
            uart_tick <= 1'b0;                
        end                                                   
    end
    
endmodule