data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_sim.v:16: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'EFX_LUT4\'\nmodule EFX_LUT4(\n       ^~~~~~~~\n                                                                                                : ... Top module \'EFX_ADD\'\nmodule EFX_ADD(\n       ^~~~~~~\n                                                                                                : ... Top module \'EFX_FF\'\nmodule EFX_FF(\n       ^~~~~~\n                                                                                                : ... Top module \'EFX_GBUFCE\'\nmodule EFX_GBUFCE(\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'EFX_RAM_5K\'\nmodule EFX_RAM_5K(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module EFX_ADD(
   output O,
   output CO,
   input I0,
   input I1,
   input CI
);
   parameter I0_POLARITY   = 1;
   parameter I1_POLARITY   = 1;

   wire i0;
   wire i1;

   assign i0 = I0_POLARITY ? I0 : ~I0;
   assign i1 = I1_POLARITY ? I1 : ~I1;

   assign {CO, O} = i0 + i1 + CI;
endmodule
module EFX_ADD(
   output O,
   output CO,
   input I0,
   input I1,
   input CI
);

   parameter I0_POLARITY   = 1;
   parameter I1_POLARITY   = 1;

   wire i0;
   wire i1;

   assign i0 = I0_POLARITY ? I0 : ~I0;
   assign i1 = I1_POLARITY ? I1 : ~I1;

   assign {CO, O} = i0 + i1 + CI;
endmodule