data/full_repos/permissive/47956074/rtl/bytewrite_ram_1b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47956074/rtl/bytewrite_ram_1b.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_1b.v:46: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                             : ... In instance bytewrite_ram_1b\n    dout <= RAM[addr];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_1b.v:55: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                             : ... In instance bytewrite_ram_1b\n        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];\n           ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bytewrite_ram_1b (clk, we, addr, din, dout);

parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;

parameter filename = "code.hex";


input	clk;
input	[NB_COL-1:0]	we;
input	[ADDR_WIDTH-1:0]	addr;
input	[NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

   integer                     _i;

initial begin
`ifndef IVERILOG
   $readmemh(filename,RAM);
`endif
   #10;

   for(_i=0;_i<6;_i=_i+1) begin
      $display("idx : %d data : %x",_i,RAM[_i]);
   end
   $display("======================");
end


always @(posedge clk)
begin
    dout <= RAM[addr];
end

generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
    if (we[i])
        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
    end
end
endgenerate

endmodule
module bytewrite_ram_1b (clk, we, addr, din, dout);


parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;

parameter filename = "code.hex";


input	clk;
input	[NB_COL-1:0]	we;
input	[ADDR_WIDTH-1:0]	addr;
input	[NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

   integer                     _i;

initial begin
`ifndef IVERILOG
   $readmemh(filename,RAM);
`endif
   #10;

   for(_i=0;_i<6;_i=_i+1) begin
      $display("idx : %d data : %x",_i,RAM[_i]);
   end
   $display("======================");
end


always @(posedge clk)
begin
    dout <= RAM[addr];
end

generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
    if (we[i])
        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
    end
end
endgenerate

endmodule