data/full_repos/permissive/435890256/my_riscv/riscv_alu.sv
data/verilator_xmls/552a06e7-2b46-46c8-a3d9-97e3bd24105d.xml
module riscv_alu(
  input logic [6:0] i_opcode,
  input logic [6:0] i_funct7,
  input logic [2:0] i_funct3,
  input logic [31:0] i_num1,
  input logic [31:0] i_num2,
  input logic [31:0] i_imm_num,
  input logic [31:0] i_pc,
  output logic o_if_branch,
  output logic [31:0] o_num,
  output logic [31:0] o_pc
);












parameter OP_JALR   = 7'b1100111;
parameter OP_BRANCH = 7'b1100011;
parameter OP_BEQ    = 3'b000;
parameter OP_BNE    = 3'b001;
parameter OP_BLT    = 3'b100;
parameter OP_BGE    = 3'b101;
parameter OP_BLTU   = 3'b110;
parameter OP_BGEU   = 3'b111;

logic [ 4:0] shamt, shamt_rs;
logic [31:0] num1_plus_imm;
logic [31:0] pc_plus_imm;
logic signed [31:0] i_num1s, i_num2s, i_imm_nums;

assign shamt         = i_imm_num[4:0];
assign shamt_rs      = i_num2[4:0];
assign num1_plus_imm = i_num1 + i_imm_num;
assign pc_plus_imm   = i_pc + i_imm_num;
assign i_num1s       = i_num1;
assign i_num2s       = i_num2;
assign i_imm_nums    = i_imm_num;


always_comb begin : PC_handle
  case(i_opcode)




    OP_JALR: begin
      o_if_branch <= 1'b1;
      o_pc        <= num1_plus_imm;
    end   
    OP_BRANCH: begin
      case(i_funct3)
        OP_BEQ:  o_if_branch <= (i_num1  == i_num2 );
        OP_BNE:  o_if_branch <= (i_num1  != i_num2 );
        OP_BLT:  o_if_branch <= (i_num1s <  i_num2s);
        OP_BGE:  o_if_branch <= (i_num1s >= i_num2s);
        OP_BLTU: o_if_branch <= (i_num1  <  i_num2 );
        OP_BGEU: o_if_branch <= (i_num1  >= i_num2 );
        default: o_if_branch <= 1'b0;
      endcase
      o_pc        <= pc_plus_imm;
    end
    default: begin
      o_if_branch <= 1'b0;
      o_pc        <= 32'b0;
    end
  endcase
end


always_comb begin : ONUM_handle
  casex({i_funct7,i_funct3,i_opcode})
    17'bxxxxxxx_xxx_0110111: o_num <= i_imm_num;
    17'bxxxxxxx_xxx_0010111: o_num <= pc_plus_imm;
    17'bxxxxxxx_xxx_110x111: o_num <= i_pc + 4;
    17'bxxxxxxx_000_0010011: o_num <= num1_plus_imm;
    17'bxxxxxxx_010_0010011: o_num <= (i_num1s < i_imm_nums) ? 1 : 0;

    17'bxxxxxxx_011_0010011: o_num <= (i_num1 < i_imm_num) ? 1 : 0;
    17'bxxxxxxx_100_0010011: o_num <= i_num1 ^ i_imm_num;
    17'bxxxxxxx_110_0010011: o_num <= i_num1 | i_imm_num;
    17'bxxxxxxx_111_0010011: o_num <= i_num1 & i_imm_num;
    17'b0000000_001_0010011: o_num <= i_num1 << shamt;
    17'b0000000_101_0010011: o_num <= i_num1 >> shamt;
    17'b0100000_101_0010011: o_num <= i_num1s >>> shamt;
    17'b0000000_000_0110011: o_num <= i_num1 + i_num2;
    17'b0100000_000_0110011: o_num <= i_num1 - i_num2;
    17'b0000000_001_0110011: o_num <= i_num1 << shamt_rs;
    17'b0000000_010_0110011: o_num <= (i_num1s < i_num2s) ? 1 : 0;
    17'b0000000_011_0110011: o_num <= (i_num1 < i_num2) ? 1 : 0;
    17'b0000000_100_0110011: o_num <= i_num1 ^ i_num2;
    17'b0000000_101_0110011: o_num <= i_num1 >> shamt_rs;
    17'b0100000_101_0110011: o_num <= i_num1s >>> shamt_rs;
    17'b0000000_110_0110011: o_num <= i_num1 | i_num2;
    17'b0000000_111_0110011: o_num <= i_num1 & i_num2;

    default:                 o_num <= 0;
  endcase
end

endmodule
module riscv_alu(
  input logic [6:0] i_opcode,
  input logic [6:0] i_funct7,
  input logic [2:0] i_funct3,
  input logic [31:0] i_num1,
  input logic [31:0] i_num2,
  input logic [31:0] i_imm_num,
  input logic [31:0] i_pc,
  output logic o_if_branch,
  output logic [31:0] o_num,
  output logic [31:0] o_pc
);













parameter OP_JALR   = 7'b1100111;
parameter OP_BRANCH = 7'b1100011;
parameter OP_BEQ    = 3'b000;
parameter OP_BNE    = 3'b001;
parameter OP_BLT    = 3'b100;
parameter OP_BGE    = 3'b101;
parameter OP_BLTU   = 3'b110;
parameter OP_BGEU   = 3'b111;

logic [ 4:0] shamt, shamt_rs;
logic [31:0] num1_plus_imm;
logic [31:0] pc_plus_imm;
logic signed [31:0] i_num1s, i_num2s, i_imm_nums;

assign shamt         = i_imm_num[4:0];
assign shamt_rs      = i_num2[4:0];
assign num1_plus_imm = i_num1 + i_imm_num;
assign pc_plus_imm   = i_pc + i_imm_num;
assign i_num1s       = i_num1;
assign i_num2s       = i_num2;
assign i_imm_nums    = i_imm_num;


always_comb begin : PC_handle
  case(i_opcode)




    OP_JALR: begin
      o_if_branch <= 1'b1;
      o_pc        <= num1_plus_imm;
    end   
    OP_BRANCH: begin
      case(i_funct3)
        OP_BEQ:  o_if_branch <= (i_num1  == i_num2 );
        OP_BNE:  o_if_branch <= (i_num1  != i_num2 );
        OP_BLT:  o_if_branch <= (i_num1s <  i_num2s);
        OP_BGE:  o_if_branch <= (i_num1s >= i_num2s);
        OP_BLTU: o_if_branch <= (i_num1  <  i_num2 );
        OP_BGEU: o_if_branch <= (i_num1  >= i_num2 );
        default: o_if_branch <= 1'b0;
      endcase
      o_pc        <= pc_plus_imm;
    end
    default: begin
      o_if_branch <= 1'b0;
      o_pc        <= 32'b0;
    end
  endcase
end


always_comb begin : ONUM_handle
  casex({i_funct7,i_funct3,i_opcode})
    17'bxxxxxxx_xxx_0110111: o_num <= i_imm_num;
    17'bxxxxxxx_xxx_0010111: o_num <= pc_plus_imm;
    17'bxxxxxxx_xxx_110x111: o_num <= i_pc + 4;
    17'bxxxxxxx_000_0010011: o_num <= num1_plus_imm;
    17'bxxxxxxx_010_0010011: o_num <= (i_num1s < i_imm_nums) ? 1 : 0;

    17'bxxxxxxx_011_0010011: o_num <= (i_num1 < i_imm_num) ? 1 : 0;
    17'bxxxxxxx_100_0010011: o_num <= i_num1 ^ i_imm_num;
    17'bxxxxxxx_110_0010011: o_num <= i_num1 | i_imm_num;
    17'bxxxxxxx_111_0010011: o_num <= i_num1 & i_imm_num;
    17'b0000000_001_0010011: o_num <= i_num1 << shamt;
    17'b0000000_101_0010011: o_num <= i_num1 >> shamt;
    17'b0100000_101_0010011: o_num <= i_num1s >>> shamt;
    17'b0000000_000_0110011: o_num <= i_num1 + i_num2;
    17'b0100000_000_0110011: o_num <= i_num1 - i_num2;
    17'b0000000_001_0110011: o_num <= i_num1 << shamt_rs;
    17'b0000000_010_0110011: o_num <= (i_num1s < i_num2s) ? 1 : 0;
    17'b0000000_011_0110011: o_num <= (i_num1 < i_num2) ? 1 : 0;
    17'b0000000_100_0110011: o_num <= i_num1 ^ i_num2;
    17'b0000000_101_0110011: o_num <= i_num1 >> shamt_rs;
    17'b0100000_101_0110011: o_num <= i_num1s >>> shamt_rs;
    17'b0000000_110_0110011: o_num <= i_num1 | i_num2;
    17'b0000000_111_0110011: o_num <= i_num1 & i_num2;

    default:                 o_num <= 0;
  endcase
end

endmodule