data/full_repos/permissive/523038000/lab14/ps2_rx.v
1: b"%Error: data/full_repos/permissive/523038000/lab14/ps2_rx.v:59: Cannot find file containing module: 'ps2'\n   ps2 ps2_inst1 \n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/ps2\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/ps2.v\n             data/full_repos/permissive/523038000/lab14,data/full_repos/permissive/523038000/ps2.sv\n             ps2\n             ps2.v\n             ps2.sv\n             obj_dir/ps2\n             obj_dir/ps2.v\n             obj_dir/ps2.sv\n%Error: Exiting due to 1 error(s)\n"
module ps2_rx 
(
   input  wire  clk, reset, 
   input  wire  ps2d,  ps2c, 
   output  wire  interrupt, 
   output wire  [7:0]  key_code 
);


wire [7:0] dout1;
wire rx_done_tick;
reg [7:0] dout;
reg inter;

wire [7:0] dout_nxt;
wire inter_nxt; 





   ps2 ps2_inst1 
								( 
			.clk(clk), 
			.reset(reset), 
			.ps2d(ps2d),
			.ps2c(ps2c),
			.rx_en(1'b1), 
			.rx_done_tick(rx_done_tick), 
			.dout(dout1) 
								);
								
								
								
always @ (posedge clk or posedge reset)
   begin
       if (reset)
       begin
           inter <= 1'b0;
           dout <= 8'b0;
       end
       
       else
       
       begin
           inter <= inter_nxt;
           dout <= dout_nxt;
       end
          
   end   

   
   
   assign dout_nxt = (rx_done_tick==1'b1) ? dout1 : dout;
   assign inter_nxt = rx_done_tick;
   
   
   assign key_code = dout;
   assign interrupt = inter;  

endmodule
module ps2_rx 
(
   input  wire  clk, reset, 
   input  wire  ps2d,  ps2c, 
   output  wire  interrupt, 
   output wire  [7:0]  key_code 
);



wire [7:0] dout1;
wire rx_done_tick;
reg [7:0] dout;
reg inter;

wire [7:0] dout_nxt;
wire inter_nxt; 





   ps2 ps2_inst1 
								( 
			.clk(clk), 
			.reset(reset), 
			.ps2d(ps2d),
			.ps2c(ps2c),
			.rx_en(1'b1), 
			.rx_done_tick(rx_done_tick), 
			.dout(dout1) 
								);
								
								
								
always @ (posedge clk or posedge reset)
   begin
       if (reset)
       begin
           inter <= 1'b0;
           dout <= 8'b0;
       end
       
       else
       
       begin
           inter <= inter_nxt;
           dout <= dout_nxt;
       end
          
   end   

   
   
   assign dout_nxt = (rx_done_tick==1'b1) ? dout1 : dout;
   assign inter_nxt = rx_done_tick;
   
   
   assign key_code = dout;
   assign interrupt = inter;  

endmodule