data/full_repos/permissive/485085993/verilog/rtl/muxes.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:114: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'mux_2level_tapbuf_size6\'\nmodule mux_2level_tapbuf_size6(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'mux_2level_tapbuf_size4\'\nmodule mux_2level_tapbuf_size4(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'mux_2level_tapbuf_size3\'\nmodule mux_2level_tapbuf_size3(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'mux_2level_tapbuf_size2\'\nmodule mux_2level_tapbuf_size2(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'mux_2level_size14\'\nmodule mux_2level_size14(in,\n       ^~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'mux_1level_tapbuf_size2\'\nmodule mux_1level_tapbuf_size2(in,\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                               : ... Top module \'lut4_mux\'\nmodule lut4_mux(in,\n       ^~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:575: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:577: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] sram;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:579: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] sram_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:628: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_0_ (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1.sv\n             INVTX1\n             INVTX1.v\n             INVTX1.sv\n             obj_dir/INVTX1\n             obj_dir/INVTX1.v\n             obj_dir/INVTX1.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:632: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_1_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:636: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_2_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:640: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_3_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:644: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_4_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:648: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_5_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:652: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_6_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:656: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_7_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:660: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_8_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:664: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_9_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:668: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_10_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:672: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_11_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:676: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_12_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:680: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_13_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:684: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_14_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:688: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_15_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:692: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_16_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:696: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_0_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:702: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_1_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:708: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_2_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:714: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_3_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:720: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_4_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:726: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_5_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:732: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_6_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:738: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l1_in_7_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:744: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l2_in_0_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:750: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l2_in_1_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:756: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l2_in_2_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:762: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l2_in_3_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:768: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l3_in_0_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:774: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l3_in_1_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:780: Cannot find file containing module: \'lut4_mux_basis_input2_mem1\'\n lut4_mux_basis_input2_mem1 mux_l4_in_0_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:510: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:512: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] sram;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:514: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] sram_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:536: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_0_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:540: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_1_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:544: Cannot find file containing module: \'const1\'\n const1 const1_0_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:547: Cannot find file containing module: \'tap_buf4\'\n tap_buf4 tap_buf4_0_ (\n ^~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:551: Cannot find file containing module: \'mux_1level_tapbuf_basis_input3_mem3\'\n mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:357: Little bit endian vector: MSB < LSB of bit range: 0:13\ninput [0:13] in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:359: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] sram;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:361: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] sram_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:399: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_0_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:403: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_1_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:407: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_2_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:411: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_3_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:415: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_4_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:419: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_5_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:423: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_6_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:427: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_7_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:431: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_8_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:435: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_9_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:439: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_10_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:443: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_11_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/muxes.v:447: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_12_ (\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mux_2level_tapbuf_size6(in,
                               sram,
                               sram_inv,
                               out);

input [0:5] in;

input [0:5] sram;

input [0:5] sram_inv;

output [0:0] out;









wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out;






	INVTX1 INVTX1_0_ (
		.in(in[0]),
		.out(INVTX1_0_out));

	INVTX1 INVTX1_1_ (
		.in(in[1]),
		.out(INVTX1_1_out));

	INVTX1 INVTX1_2_ (
		.in(in[2]),
		.out(INVTX1_2_out));

	INVTX1 INVTX1_3_ (
		.in(in[3]),
		.out(INVTX1_3_out));

	INVTX1 INVTX1_4_ (
		.in(in[4]),
		.out(INVTX1_4_out));

	INVTX1 INVTX1_5_ (
		.in(in[5]),
		.out(INVTX1_5_out));

	const1 const1_0_ (
		.const1(const1_0_const1));

	tap_buf4 tap_buf4_0_ (
		.in(mux_2level_tapbuf_basis_input3_mem3_2_out),
		.out(out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l1_in_0_ (
		.in({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out}),
		.mem(sram[0:2]),
		.mem_inv(sram_inv[0:2]),
		.out(mux_2level_tapbuf_basis_input3_mem3_0_out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l1_in_1_ (
		.in({INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}),
		.mem(sram[0:2]),
		.mem_inv(sram_inv[0:2]),
		.out(mux_2level_tapbuf_basis_input3_mem3_1_out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
		.in({mux_2level_tapbuf_basis_input3_mem3_0_out, mux_2level_tapbuf_basis_input3_mem3_1_out, const1_0_const1}),
		.mem(sram[3:5]),
		.mem_inv(sram_inv[3:5]),
		.out(mux_2level_tapbuf_basis_input3_mem3_2_out));

endmodule
module mux_2level_tapbuf_size6(in,
                               sram,
                               sram_inv,
                               out);


input [0:5] in;

input [0:5] sram;

input [0:5] sram_inv;

output [0:0] out;









wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out;
wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out;






	INVTX1 INVTX1_0_ (
		.in(in[0]),
		.out(INVTX1_0_out));

	INVTX1 INVTX1_1_ (
		.in(in[1]),
		.out(INVTX1_1_out));

	INVTX1 INVTX1_2_ (
		.in(in[2]),
		.out(INVTX1_2_out));

	INVTX1 INVTX1_3_ (
		.in(in[3]),
		.out(INVTX1_3_out));

	INVTX1 INVTX1_4_ (
		.in(in[4]),
		.out(INVTX1_4_out));

	INVTX1 INVTX1_5_ (
		.in(in[5]),
		.out(INVTX1_5_out));

	const1 const1_0_ (
		.const1(const1_0_const1));

	tap_buf4 tap_buf4_0_ (
		.in(mux_2level_tapbuf_basis_input3_mem3_2_out),
		.out(out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l1_in_0_ (
		.in({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out}),
		.mem(sram[0:2]),
		.mem_inv(sram_inv[0:2]),
		.out(mux_2level_tapbuf_basis_input3_mem3_0_out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l1_in_1_ (
		.in({INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}),
		.mem(sram[0:2]),
		.mem_inv(sram_inv[0:2]),
		.out(mux_2level_tapbuf_basis_input3_mem3_1_out));

	mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
		.in({mux_2level_tapbuf_basis_input3_mem3_0_out, mux_2level_tapbuf_basis_input3_mem3_1_out, const1_0_const1}),
		.mem(sram[3:5]),
		.mem_inv(sram_inv[3:5]),
		.out(mux_2level_tapbuf_basis_input3_mem3_2_out));

endmodule