data/full_repos/permissive/458134463/Modules/register.v
data/verilator_xmls/121b4ecd-c8b0-496a-b0fe-3063f0bf46fa.xml
module register(read_reg1, read_reg2, write_reg, write_data, RegWrite, read_data1, read_data2, clock);

input [2:0] read_reg1;
input [2:0] read_reg2;
input [2:0] write_reg;
input [31:0]write_data;
input RegWrite, clock;

output [31:0] read_data1;
output [31:0] read_data2;


reg [31:0] registers [7:0];

assign read_data1 = registers[read_reg1];
assign read_data2 = registers[read_reg2];

always @(posedge clock) begin
	if(RegWrite && write_reg != 3'b000)
		registers[write_reg] = write_data;
end

endmodule
module register(read_reg1, read_reg2, write_reg, write_data, RegWrite, read_data1, read_data2, clock);


input [2:0] read_reg1;
input [2:0] read_reg2;
input [2:0] write_reg;
input [31:0]write_data;
input RegWrite, clock;

output [31:0] read_data1;
output [31:0] read_data2;


reg [31:0] registers [7:0];

assign read_data1 = registers[read_reg1];
assign read_data2 = registers[read_reg2];

always @(posedge clock) begin
	if(RegWrite && write_reg != 3'b000)
		registers[write_reg] = write_data;
end

endmodule