data/full_repos/permissive/426889244/tb/jitter_proc.v
data/verilator_xmls/23d244df-5964-4e52-b29e-7b11ace70990.xml
module jitter_proc (
    input wire clk,
    input wire reset,
    input wire sig_in,

    output wire valid_sig
);
    reg[3:0] buffer;

    assign valid_sig = & buffer;

    always @(posedge clk or negedge reset) begin
        if (~reset) begin
            buffer <= 0;
        end
        else begin
            buffer <= {buffer[2:0], sig_in};
        end
    end
endmodule
module jitter_proc (
    input wire clk,
    input wire reset,
    input wire sig_in,

    output wire valid_sig
);

    reg[3:0] buffer;

    assign valid_sig = & buffer;

    always @(posedge clk or negedge reset) begin
        if (~reset) begin
            buffer <= 0;
        end
        else begin
            buffer <= {buffer[2:0], sig_in};
        end
    end
endmodule