data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/More Circuits/Rule110/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/More\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/More.sv\n             Logic/More\n             Logic/More.v\n             Logic/More.sv\n             obj_dir/Logic/More\n             obj_dir/Logic/More.v\n             obj_dir/Logic/More.sv\n%Error: Cannot find file containing module: Circuits/Rule110,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Circuits/Rule110/top_module_tb.v\n%Error: Exiting due to 4 error(s)\n'
module top_module_tb ();
  reg clk = 1'b1;
  reg load = 1'b0;
  reg [511:0] data = 512'b1;
  wire [511:0] q;

  localparam ITERATIONS = 1024;

  always begin
    #1 clk = clk + 1;
  end

  initial begin
    #2 load = 1'b1;
    #1 load = 1'b0;
  end


  top_module uut (
      .clk(clk),
      .load(load),
      .data(data),
      .q(q)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg clk = 1'b1;
  reg load = 1'b0;
  reg [511:0] data = 512'b1;
  wire [511:0] q;

  localparam ITERATIONS = 1024;

  always begin
    #1 clk = clk + 1;
  end

  initial begin
    #2 load = 1'b1;
    #1 load = 1'b0;
  end


  top_module uut (
      .clk(clk),
      .load(load),
      .data(data),
      .q(q)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule