data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/imemrwpx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/imemrwpx.v:31: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/imemrwpx.v:53: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/imemrwpx.v:65: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg [WIDTH-1:0]     do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/imemrwpx.v:98: syntax error, unexpected <=\n        do      <= {WIDTH{1'b0}};\n                ^~\n%Error: Cannot continue\n"
module imemrwpx
    (
     wrst_,
     wrclk,
     wa,
     we,
     di,

     rrst_,
     rdclk,
     ra,
     re,
     do,
     
     test,
     mask
     );

parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               wrst_;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst_;
input               rdclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
reg                 ire;
reg [WIDTH-1:0]     do;



always @ (posedge wrclk or negedge wrst_)
    if (~wrst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end


always @ (posedge rdclk or negedge rrst_)
    if (~rrst_)
        begin
        ira <= {ADDRBIT{1'b0}};
        ire <= 1'b0;
        end
    else
        begin
        ira <= ra;
        ire <= re;
        end

always @ (posedge rdclk or negedge rrst_)
    if (~rrst_)
        do      <= {WIDTH{1'b0}};
    else
        do      <= ido;


iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ire,ido,test,mask);

endmodule
module imemrwpx
    (
     wrst_,
     wrclk,
     wa,
     we,
     di,

     rrst_,
     rdclk,
     ra,
     re,
     do,
     
     test,
     mask
     );


parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               wrst_;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst_;
input               rdclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
reg                 ire;
reg [WIDTH-1:0]     do;



always @ (posedge wrclk or negedge wrst_)
    if (~wrst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end


always @ (posedge rdclk or negedge rrst_)
    if (~rrst_)
        begin
        ira <= {ADDRBIT{1'b0}};
        ire <= 1'b0;
        end
    else
        begin
        ira <= ra;
        ire <= re;
        end

always @ (posedge rdclk or negedge rrst_)
    if (~rrst_)
        do      <= {WIDTH{1'b0}};
    else
        do      <= ido;


iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ire,ido,test,mask);

endmodule