data/full_repos/permissive/490649362/pipeline/src/MUX_2x1.v
data/verilator_xmls/8a1e21da-b969-4fd1-aff5-8b9a05ef0c3c.xml
module MUX_2x1 (A, B, sel, F);

    parameter size = 32;

    input [size-1:0] A,B;
    output [size-1:0] F;
    input sel;

    reg [size-1:0] F;

    always @(*) begin
        case (sel)
            1'b0:
                F = A;
            1'b1:
                F = B;
            default:
                F = A;
        endcase
    end

endmodule
module MUX_2x1 (A, B, sel, F);


    parameter size = 32;

    input [size-1:0] A,B;
    output [size-1:0] F;
    input sel;

    reg [size-1:0] F;

    always @(*) begin
        case (sel)
            1'b0:
                F = A;
            1'b1:
                F = B;
            default:
                F = A;
        endcase
    end

endmodule