data/full_repos/permissive/501358050/src/core/memory_access.v
1: b'%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:38: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                : ... In instance memory_access\nassign wb_pc_data = (in_mem_write_data == 12\'h0) ? csr_trap_vec_data : (\n                                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:39: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'12\'h1\' generates 12 bits.\n                                                                                : ... In instance memory_access\n    (in_mem_write_data == 12\'h1) ? csr_trap_vec_data : (\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:40: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'12\'h302\' generates 12 bits.\n                                                                                : ... In instance memory_access\n        (in_mem_write_data == 12\'h302) ? csr_exception_pc_data : 12\'h0\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:40: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                : ... In instance memory_access\n        (in_mem_write_data == 12\'h302) ? csr_exception_pc_data : 12\'h0\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:75: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                : ... In instance memory_access\n                    out_wb_data <= $signed(mem_data[7:0]);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:78: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                : ... In instance memory_access\n                    out_wb_data <= $signed(mem_data[15:0]);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:84: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                : ... In instance memory_access\n                    out_wb_data <= $unsigned(mem_data[7:0]);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/501358050/src/core/memory_access.v:87: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n                                                                                : ... In instance memory_access\n                    out_wb_data <= $unsigned(mem_data[15:0]);\n                                ^~\n%Error: Exiting due to 8 warning(s)\n'
module memory_access (
    input clk,
    input stop,
    input [4:0] in_reg_d,

    input [4:0] in_mem_command,
    input [31:0] in_alu_out, 
    input [31:0] in_mem_write_data, 
    input [31:0] in_now_pc,
    input [31:0] mem_data,
    input [31:0] csr_data,
    input [31:0] csr_trap_vec_data,
    input [31:0] csr_exception_pc_data,

    output [11:0] csr_addr,
    output [31:0] mem_addr,
    output reg is_mem_write,
    output wb_pc,
    output reg wb_csr,
    output reg [11:0] out_csr_addr,
    output [31:0] wb_pc_data,
    output reg [31:0] out_mem_addr,
    output reg [31:0] out_mem_data,
    output reg [31:0] out_wb_data,
    output reg [4:0] out_reg_d,
    output reg [31:0] out_now_pc,
    output reg [31:0] out_csr_data
);

assign mem_addr = in_alu_out;
assign csr_addr = in_mem_write_data[11:0];

assign wb_pc = (in_mem_command == 5'b00010);
assign wb_pc_data = (in_mem_write_data == 12'h0) ? csr_trap_vec_data : (
    (in_mem_write_data == 12'h1) ? csr_trap_vec_data : (
        (in_mem_write_data == 12'h302) ? csr_exception_pc_data : 12'h0
    )
);

always @(posedge clk) begin
    if (in_mem_command[0]) begin

        if (in_mem_command[1:0] == 2'b11) begin
            case (in_mem_command[4:2])
                3'b000: begin
                    out_mem_data[31:8] <= mem_data[31:8];
                    out_mem_data[7:0] <= in_mem_write_data[7:0];
                    is_mem_write <= 1'b1;
                end
                3'b001: begin
                    out_mem_data[31:16] <= mem_data[31:16];
                    out_mem_data[15:0] <= in_mem_write_data[15:0];
                    is_mem_write <= 1'b1;
                end
                3'b010: begin
                    out_mem_data <= in_mem_write_data;
                    is_mem_write <= 1'b1;
                end
                default: begin
                    out_mem_data <= mem_data;
                    is_mem_write <= 1'b0;
                end
            endcase
            out_wb_data <= in_alu_out;
        end


        else if (in_mem_command[1:0] == 2'b01) begin
            case (in_mem_command[4:2])
                3'b000: begin
                    out_wb_data <= $signed(mem_data[7:0]);
                end
                3'b001: begin
                    out_wb_data <= $signed(mem_data[15:0]);
                end
                3'b010: begin
                    out_wb_data <= mem_data;
                end
                3'b100: begin
                    out_wb_data <= $unsigned(mem_data[7:0]);
                end
                3'b101: begin
                    out_wb_data <= $unsigned(mem_data[15:0]);
                end
                default: begin
                    out_wb_data <= mem_data;
                end
            endcase
            out_mem_data <= mem_data;
            is_mem_write <= 1'b0;
        end
        out_csr_data <= 32'b0;
        wb_csr <= 1'b0;
        out_mem_addr <= mem_addr;
    end


    else if (in_mem_command[1:0] == 2'b10) begin
        case(in_mem_command[4:2])
            3'b000: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b001: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b010: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data | in_alu_out;
            end
            3'b011: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data & ~in_alu_out;
            end
            3'b101: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b110: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data | in_alu_out;
            end
            3'b111: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data & ~in_alu_out;
            end
            default: begin
                out_wb_data <= 32'b0;
                out_csr_data <= csr_data;
            end
        endcase
        out_mem_data <= mem_data;
        is_mem_write <= 1'b0;
        wb_csr <= 1'b1;
        out_mem_addr <= mem_addr;
    end

    else begin
        out_mem_data <= mem_data;
        out_wb_data <= in_alu_out;
        is_mem_write <= 1'b0;
        out_csr_data <= 32'b0;
        wb_csr <= 1'b0;
        out_mem_addr <= mem_addr;
    end

    out_csr_addr <= csr_addr;
    out_reg_d <= in_reg_d;
    out_now_pc <= in_now_pc;
end

endmodule
module memory_access (
    input clk,
    input stop,
    input [4:0] in_reg_d,

    input [4:0] in_mem_command,
    input [31:0] in_alu_out, 
    input [31:0] in_mem_write_data, 
    input [31:0] in_now_pc,
    input [31:0] mem_data,
    input [31:0] csr_data,
    input [31:0] csr_trap_vec_data,
    input [31:0] csr_exception_pc_data,

    output [11:0] csr_addr,
    output [31:0] mem_addr,
    output reg is_mem_write,
    output wb_pc,
    output reg wb_csr,
    output reg [11:0] out_csr_addr,
    output [31:0] wb_pc_data,
    output reg [31:0] out_mem_addr,
    output reg [31:0] out_mem_data,
    output reg [31:0] out_wb_data,
    output reg [4:0] out_reg_d,
    output reg [31:0] out_now_pc,
    output reg [31:0] out_csr_data
);


assign mem_addr = in_alu_out;
assign csr_addr = in_mem_write_data[11:0];

assign wb_pc = (in_mem_command == 5'b00010);
assign wb_pc_data = (in_mem_write_data == 12'h0) ? csr_trap_vec_data : (
    (in_mem_write_data == 12'h1) ? csr_trap_vec_data : (
        (in_mem_write_data == 12'h302) ? csr_exception_pc_data : 12'h0
    )
);

always @(posedge clk) begin
    if (in_mem_command[0]) begin

        if (in_mem_command[1:0] == 2'b11) begin
            case (in_mem_command[4:2])
                3'b000: begin
                    out_mem_data[31:8] <= mem_data[31:8];
                    out_mem_data[7:0] <= in_mem_write_data[7:0];
                    is_mem_write <= 1'b1;
                end
                3'b001: begin
                    out_mem_data[31:16] <= mem_data[31:16];
                    out_mem_data[15:0] <= in_mem_write_data[15:0];
                    is_mem_write <= 1'b1;
                end
                3'b010: begin
                    out_mem_data <= in_mem_write_data;
                    is_mem_write <= 1'b1;
                end
                default: begin
                    out_mem_data <= mem_data;
                    is_mem_write <= 1'b0;
                end
            endcase
            out_wb_data <= in_alu_out;
        end


        else if (in_mem_command[1:0] == 2'b01) begin
            case (in_mem_command[4:2])
                3'b000: begin
                    out_wb_data <= $signed(mem_data[7:0]);
                end
                3'b001: begin
                    out_wb_data <= $signed(mem_data[15:0]);
                end
                3'b010: begin
                    out_wb_data <= mem_data;
                end
                3'b100: begin
                    out_wb_data <= $unsigned(mem_data[7:0]);
                end
                3'b101: begin
                    out_wb_data <= $unsigned(mem_data[15:0]);
                end
                default: begin
                    out_wb_data <= mem_data;
                end
            endcase
            out_mem_data <= mem_data;
            is_mem_write <= 1'b0;
        end
        out_csr_data <= 32'b0;
        wb_csr <= 1'b0;
        out_mem_addr <= mem_addr;
    end


    else if (in_mem_command[1:0] == 2'b10) begin
        case(in_mem_command[4:2])
            3'b000: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b001: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b010: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data | in_alu_out;
            end
            3'b011: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data & ~in_alu_out;
            end
            3'b101: begin
                out_wb_data <= csr_data;
                out_csr_data <= in_alu_out;
            end
            3'b110: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data | in_alu_out;
            end
            3'b111: begin
                out_wb_data <= csr_data;
                out_csr_data <= csr_data & ~in_alu_out;
            end
            default: begin
                out_wb_data <= 32'b0;
                out_csr_data <= csr_data;
            end
        endcase
        out_mem_data <= mem_data;
        is_mem_write <= 1'b0;
        wb_csr <= 1'b1;
        out_mem_addr <= mem_addr;
    end

    else begin
        out_mem_data <= mem_data;
        out_wb_data <= in_alu_out;
        is_mem_write <= 1'b0;
        out_csr_data <= 32'b0;
        wb_csr <= 1'b0;
        out_mem_addr <= mem_addr;
    end

    out_csr_addr <= csr_addr;
    out_reg_d <= in_reg_d;
    out_now_pc <= in_now_pc;
end

endmodule