data/full_repos/permissive/436822793/src/dpll.v
1: b"%Error: data/full_repos/permissive/436822793/src/dpll.v:22: Cannot find file containing module: 'oscillator'\n oscillator osc\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436822793/src,data/full_repos/permissive/436822793/oscillator\n             data/full_repos/permissive/436822793/src,data/full_repos/permissive/436822793/oscillator.v\n             data/full_repos/permissive/436822793/src,data/full_repos/permissive/436822793/oscillator.sv\n             oscillator\n             oscillator.v\n             oscillator.sv\n             obj_dir/oscillator\n             obj_dir/oscillator.v\n             obj_dir/oscillator.sv\n%Error: data/full_repos/permissive/436822793/src/dpll.v:29: Cannot find file containing module: 'clock_ctl'\n clock_ctl ctl\n ^~~~~~~~~\n%Error: data/full_repos/permissive/436822793/src/dpll.v:43: Cannot find file containing module: 'delay_module'\n delay_module delay_line\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/436822793/src/dpll.v:50: Cannot find file containing module: 'CLKAND2X8'\n CLKAND2X8 p_adjust(.A(1'b1), .B(tmp_out), .Y(clk_out));\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module DPLL
(
	input         resetn,

	input         ref_clk,
	input [15:0]  ref_counter,

	input [ 8:0]  init,
	input [15:0]  counter,

	input         clk_in,
	output        clk_out,

	output [2:0]  status
);

	wire [511:0] en;
	wire         clk;

	oscillator osc
	(
		.resetn(resetn),
		.en(en),
		.out(clk)
	);

	clock_ctl ctl
	(
		.resetn(resetn),
		.ref_clk(ref_clk),
		.ref_counter(ref_counter),
		.init(init),
		.counter(counter),
		.clk(clk),
		.status(status),
		.en(en)
	);

	wire  tmp_out;

	delay_module delay_line
    (
        .in(clk_in),
        .en(en),
        .out(tmp_out)
    );

	CLKAND2X8 p_adjust(.A(1'b1), .B(tmp_out), .Y(clk_out));

endmodule
module DPLL
(
	input         resetn,

	input         ref_clk,
	input [15:0]  ref_counter,

	input [ 8:0]  init,
	input [15:0]  counter,

	input         clk_in,
	output        clk_out,

	output [2:0]  status
);


	wire [511:0] en;
	wire         clk;

	oscillator osc
	(
		.resetn(resetn),
		.en(en),
		.out(clk)
	);

	clock_ctl ctl
	(
		.resetn(resetn),
		.ref_clk(ref_clk),
		.ref_counter(ref_counter),
		.init(init),
		.counter(counter),
		.clk(clk),
		.status(status),
		.en(en)
	);

	wire  tmp_out;

	delay_module delay_line
    (
        .in(clk_in),
        .en(en),
        .out(tmp_out)
    );

	CLKAND2X8 p_adjust(.A(1'b1), .B(tmp_out), .Y(clk_out));

endmodule