data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/axi_sd_fifo_filler.v
1: b"%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/axi_sd_fifo_filler.v:79: Cannot find file containing module: 'axi_sd_fifo'\naxi_sd_fifo #(.addr_bits(fifo_addr_bits)) rx_fifo (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/axi_sd_fifo\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/axi_sd_fifo.v\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/axi_sd_fifo.sv\n             axi_sd_fifo\n             axi_sd_fifo.v\n             axi_sd_fifo.sv\n             obj_dir/axi_sd_fifo\n             obj_dir/axi_sd_fifo.v\n             obj_dir/axi_sd_fifo.sv\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/axi_sd_fifo_filler.v:91: Cannot find file containing module: 'axi_sd_fifo'\naxi_sd_fifo #(.addr_bits(fifo_addr_bits)) tx_fifo (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module axi_sd_fifo_filler #(parameter fifo_addr_bits = 6) (
    input clock,
    input clock_posedge,
    input reset,


    output reg [31:2] bus_adr_o,
    output [31:0] bus_dat_o,
    input [31:0] bus_dat_i,
    output bus_we_o,
    output bus_stb_o,
    input bus_last_i,
    input bus_ack_i,


    input en_rx_i,
    input en_tx_i,
    input [31:2] adr_i,


    input [31:0] dat_i,
    output [31:0] dat_o,
    input wr_i,
    input rd_i,
    output [fifo_addr_bits-1:0] tx_free,
    output [fifo_addr_bits-1:0] rx_data,
    output rx_full_o,
    output tx_empty_o,
    output tx_ready_o,
    output rx_empty_o
);

localparam fifo_threshold = 1 << (fifo_addr_bits - 1);

reg bus_wait;
wire [fifo_addr_bits-1:0] tx_data;
wire tx_stb;
wire rx_stb;

assign tx_ready_o = tx_data >= fifo_threshold;
assign tx_stb = en_tx_i && tx_free >= fifo_threshold;
assign rx_stb = en_rx_i ? (rx_data >= fifo_threshold) : !rx_empty_o;
assign bus_we_o = !rx_empty_o;
assign bus_stb_o = bus_wait | tx_stb | rx_stb;


axi_sd_fifo #(.addr_bits(fifo_addr_bits)) rx_fifo (
    .clk(clock),
    .rst(reset),
    .din(dat_i),
    .we(wr_i & clock_posedge),
    .dout(bus_dat_o),
    .re(bus_we_o & bus_stb_o & bus_ack_i),
    .data_len(rx_data),
    .full(rx_full_o),
    .empty(rx_empty_o));


axi_sd_fifo #(.addr_bits(fifo_addr_bits)) tx_fifo (
    .clk(clock),
    .rst(reset | !en_tx_i),
    .din(bus_dat_i),
    .we(!bus_we_o & bus_stb_o & bus_ack_i),
    .dout(dat_o),
    .re(rd_i & clock_posedge),
    .free_len(tx_free),
    .data_len(tx_data),
    .empty(tx_empty_o));

always @(posedge clock)
    if (reset) begin
        bus_adr_o <= 0;
        bus_wait <= 0;
    end else if (bus_stb_o & bus_ack_i) begin
        bus_adr_o <= bus_adr_o + 1;
        bus_wait <= !bus_last_i;
    end else if (bus_stb_o) begin
        bus_wait <= 1;
    end else if (!en_rx_i & !en_tx_i & rx_empty_o)
        bus_adr_o <= adr_i;

endmodule
module axi_sd_fifo_filler #(parameter fifo_addr_bits = 6) (
    input clock,
    input clock_posedge,
    input reset,


    output reg [31:2] bus_adr_o,
    output [31:0] bus_dat_o,
    input [31:0] bus_dat_i,
    output bus_we_o,
    output bus_stb_o,
    input bus_last_i,
    input bus_ack_i,


    input en_rx_i,
    input en_tx_i,
    input [31:2] adr_i,


    input [31:0] dat_i,
    output [31:0] dat_o,
    input wr_i,
    input rd_i,
    output [fifo_addr_bits-1:0] tx_free,
    output [fifo_addr_bits-1:0] rx_data,
    output rx_full_o,
    output tx_empty_o,
    output tx_ready_o,
    output rx_empty_o
);


localparam fifo_threshold = 1 << (fifo_addr_bits - 1);

reg bus_wait;
wire [fifo_addr_bits-1:0] tx_data;
wire tx_stb;
wire rx_stb;

assign tx_ready_o = tx_data >= fifo_threshold;
assign tx_stb = en_tx_i && tx_free >= fifo_threshold;
assign rx_stb = en_rx_i ? (rx_data >= fifo_threshold) : !rx_empty_o;
assign bus_we_o = !rx_empty_o;
assign bus_stb_o = bus_wait | tx_stb | rx_stb;


axi_sd_fifo #(.addr_bits(fifo_addr_bits)) rx_fifo (
    .clk(clock),
    .rst(reset),
    .din(dat_i),
    .we(wr_i & clock_posedge),
    .dout(bus_dat_o),
    .re(bus_we_o & bus_stb_o & bus_ack_i),
    .data_len(rx_data),
    .full(rx_full_o),
    .empty(rx_empty_o));


axi_sd_fifo #(.addr_bits(fifo_addr_bits)) tx_fifo (
    .clk(clock),
    .rst(reset | !en_tx_i),
    .din(bus_dat_i),
    .we(!bus_we_o & bus_stb_o & bus_ack_i),
    .dout(dat_o),
    .re(rd_i & clock_posedge),
    .free_len(tx_free),
    .data_len(tx_data),
    .empty(tx_empty_o));

always @(posedge clock)
    if (reset) begin
        bus_adr_o <= 0;
        bus_wait <= 0;
    end else if (bus_stb_o & bus_ack_i) begin
        bus_adr_o <= bus_adr_o + 1;
        bus_wait <= !bus_last_i;
    end else if (bus_stb_o) begin
        bus_wait <= 1;
    end else if (!en_rx_i & !en_tx_i & rx_empty_o)
        bus_adr_o <= adr_i;

endmodule