data/full_repos/permissive/471089853/src/systolicarray.v
1: b"%Error: data/full_repos/permissive/471089853/src/systolicarray.v:103: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\cols_a2s3:1.a2s3_j  (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/Arith_to_S3\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/Arith_to_S3.v\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/Arith_to_S3.sv\n             Arith_to_S3\n             Arith_to_S3.v\n             Arith_to_S3.sv\n             obj_dir/Arith_to_S3\n             obj_dir/Arith_to_S3.v\n             obj_dir/Arith_to_S3.sv\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:108: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\cols_a2s3:2.a2s3_j  (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:113: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\cols_a2s3:3.a2s3_j  (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:118: Cannot find file containing module: 'l2a'\n  l2a \\cols_l2a:1.l2a_i  (\n  ^~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:124: Cannot find file containing module: 'l2a'\n  l2a \\cols_l2a:2.l2a_i  (\n  ^~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:130: Cannot find file containing module: 'l2a'\n  l2a \\cols_l2a:3.l2a_i  (\n  ^~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:136: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\rows_a2s3:1.a2s3_i  (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:141: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\rows_a2s3:2.a2s3_i  (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:146: Cannot find file containing module: 'Arith_to_S3'\n  Arith_to_S3 \\rows_a2s3:3.a2s3_i  (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/471089853/src/systolicarray.v:151: Cannot find file containing module: 'SystolicArrayKernel'\n  SystolicArrayKernel sak (\n  ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module SystolicArray(clk, rst, rowsA, colsB, SOB, EOB, colsC, EOB_Q_o);
  reg [7:0] _00_;
  reg _01_;
  reg [7:0] _02_;
  reg [7:0] _03_;
  reg [7:0] _04_;
  wire [11:0] _05_;
  wire [11:0] _06_;
  wire [11:0] _07_;
  wire [11:0] _08_;
  wire [11:0] _09_;
  wire [11:0] _10_;
  reg [7:0] _11_;
  wire [98:0] _12_;
  wire _13_;
  wire [7:0] _14_;
  wire [7:0] _15_;
  wire [7:0] _16_;
  reg [7:0] _17_;
  reg [7:0] _18_;
  reg [7:0] _19_;
  reg [7:0] _20_;
  reg _21_;
  reg _22_;
  reg _23_;
  input EOB;
  output EOB_Q_o;
  input SOB;
  wire [7:0] arith_in_col_0;
  wire [7:0] arith_in_col_0_q0;
  wire [7:0] arith_in_col_1;
  wire [7:0] arith_in_col_1_d1;
  wire [7:0] arith_in_col_1_q1;
  wire [7:0] arith_in_col_2;
  wire [7:0] arith_in_col_2_d1;
  wire [7:0] arith_in_col_2_d2;
  wire [7:0] arith_in_col_2_q2;
  wire [7:0] arith_in_row_0;
  wire [7:0] arith_in_row_0_q0;
  wire [7:0] arith_in_row_1;
  wire [7:0] arith_in_row_1_d1;
  wire [7:0] arith_in_row_1_q1;
  wire [7:0] arith_in_row_2;
  wire [7:0] arith_in_row_2_d1;
  wire [7:0] arith_in_row_2_d2;
  wire [7:0] arith_in_row_2_q2;
  wire [7:0] arith_out_col_out_0;
  wire [7:0] arith_out_col_out_0_d1;
  wire [7:0] arith_out_col_out_0_d2;
  wire [7:0] arith_out_col_out_0_q2;
  wire [7:0] arith_out_col_out_1;
  wire [7:0] arith_out_col_out_1_d1;
  wire [7:0] arith_out_col_out_1_q1;
  wire [7:0] arith_out_col_out_2;
  wire [7:0] arith_out_col_out_2_q0;
  input clk;
  input [23:0] colsB;
  output [23:0] colsC;
  wire [23:0] cols_j_arith;
  wire [35:0] cols_j_s3;
  wire [98:0] colsc_laicpt2;
  wire eob_q2;
  wire eob_select;
  wire eob_select_d1;
  wire eob_select_d2;
  wire [23:0] laicpt2_to_arith;
  input [23:0] rowsA;
  wire [23:0] rows_i_arith;
  wire [35:0] rows_i_s3;
  input rst;
  wire sob_q2;
  wire sob_select;
  wire sob_select_d1;
  wire sob_select_d2;
  always @(posedge clk)
    _00_ <= arith_in_row_1;
  always @(posedge clk)
    _11_ <= arith_in_row_2;
  always @(posedge clk)
    _17_ <= arith_in_row_2_d1;
  always @(posedge clk)
    _18_ <= arith_in_col_1;
  always @(posedge clk)
    _19_ <= arith_in_col_2;
  always @(posedge clk)
    _20_ <= arith_in_col_2_d1;
  always @(posedge clk)
    _21_ <= sob_select;
  always @(posedge clk)
    _22_ <= sob_select_d1;
  always @(posedge clk)
    _23_ <= eob_select;
  always @(posedge clk)
    _01_ <= eob_select_d1;
  always @(posedge clk)
    _02_ <= arith_out_col_out_0;
  always @(posedge clk)
    _03_ <= arith_out_col_out_0_d1;
  always @(posedge clk)
    _04_ <= arith_out_col_out_1;
  Arith_to_S3 \cols_a2s3:1.a2s3_j  (
    .S3_o(_08_),
    .arith_i(cols_j_arith[7:0]),
    .clk(clk)
  );
  Arith_to_S3 \cols_a2s3:2.a2s3_j  (
    .S3_o(_09_),
    .arith_i(cols_j_arith[15:8]),
    .clk(clk)
  );
  Arith_to_S3 \cols_a2s3:3.a2s3_j  (
    .S3_o(_10_),
    .arith_i(cols_j_arith[23:16]),
    .clk(clk)
  );
  l2a \cols_l2a:1.l2a_i  (
    .A(colsc_laicpt2[31:0]),
    .arith_o(_14_),
    .clk(clk),
    .isNaN(colsc_laicpt2[32])
  );
  l2a \cols_l2a:2.l2a_i  (
    .A(colsc_laicpt2[64:33]),
    .arith_o(_15_),
    .clk(clk),
    .isNaN(colsc_laicpt2[65])
  );
  l2a \cols_l2a:3.l2a_i  (
    .A(colsc_laicpt2[97:66]),
    .arith_o(_16_),
    .clk(clk),
    .isNaN(colsc_laicpt2[98])
  );
  Arith_to_S3 \rows_a2s3:1.a2s3_i  (
    .S3_o(_05_),
    .arith_i(rows_i_arith[7:0]),
    .clk(clk)
  );
  Arith_to_S3 \rows_a2s3:2.a2s3_i  (
    .S3_o(_06_),
    .arith_i(rows_i_arith[15:8]),
    .clk(clk)
  );
  Arith_to_S3 \rows_a2s3:3.a2s3_i  (
    .S3_o(_07_),
    .arith_i(rows_i_arith[23:16]),
    .clk(clk)
  );
  SystolicArrayKernel sak (
    .EOB(eob_q2),
    .EOB_Q_o(_13_),
    .SOB(sob_q2),
    .clk(clk),
    .colsB(cols_j_s3),
    .colsC(_12_),
    .rowsA(rows_i_s3),
    .rst(rst)
  );
  assign arith_in_row_0 = rowsA[7:0];
  assign arith_in_row_0_q0 = arith_in_row_0;
  assign arith_in_row_1 = rowsA[15:8];
  assign arith_in_row_1_d1 = _00_;
  assign arith_in_row_1_q1 = arith_in_row_1_d1;
  assign arith_in_row_2 = rowsA[23:16];
  assign arith_in_row_2_d1 = _11_;
  assign arith_in_row_2_d2 = _17_;
  assign arith_in_row_2_q2 = arith_in_row_2_d2;
  assign arith_in_col_0 = colsB[7:0];
  assign arith_in_col_0_q0 = arith_in_col_0;
  assign arith_in_col_1 = colsB[15:8];
  assign arith_in_col_1_d1 = _18_;
  assign arith_in_col_1_q1 = arith_in_col_1_d1;
  assign arith_in_col_2 = colsB[23:16];
  assign arith_in_col_2_d1 = _19_;
  assign arith_in_col_2_d2 = _20_;
  assign arith_in_col_2_q2 = arith_in_col_2_d2;
  assign colsc_laicpt2 = _12_;
  assign sob_select = SOB;
  assign sob_select_d1 = _21_;
  assign sob_select_d2 = _22_;
  assign sob_q2 = sob_select_d2;
  assign eob_select = EOB;
  assign eob_select_d1 = _23_;
  assign eob_select_d2 = _01_;
  assign eob_q2 = eob_select_d2;
  assign laicpt2_to_arith = { _16_, _15_, _14_ };
  assign arith_out_col_out_0 = laicpt2_to_arith[7:0];
  assign arith_out_col_out_0_d1 = _02_;
  assign arith_out_col_out_0_d2 = _03_;
  assign arith_out_col_out_0_q2 = arith_out_col_out_0_d2;
  assign arith_out_col_out_1 = laicpt2_to_arith[15:8];
  assign arith_out_col_out_1_d1 = _04_;
  assign arith_out_col_out_1_q1 = arith_out_col_out_1_d1;
  assign arith_out_col_out_2 = laicpt2_to_arith[23:16];
  assign arith_out_col_out_2_q0 = arith_out_col_out_2;
  assign rows_i_arith = { arith_in_row_2_q2, arith_in_row_1_q1, arith_in_row_0_q0 };
  assign rows_i_s3 = { _07_, _06_, _05_ };
  assign cols_j_arith = { arith_in_col_2_q2, arith_in_col_1_q1, arith_in_col_0_q0 };
  assign cols_j_s3 = { _10_, _09_, _08_ };
  assign colsC = { arith_out_col_out_2_q0, arith_out_col_out_1_q1, arith_out_col_out_0_q2 };
  assign EOB_Q_o = _13_;
endmodule
module SystolicArray(clk, rst, rowsA, colsB, SOB, EOB, colsC, EOB_Q_o);

  reg [7:0] _00_;
  reg _01_;
  reg [7:0] _02_;
  reg [7:0] _03_;
  reg [7:0] _04_;
  wire [11:0] _05_;
  wire [11:0] _06_;
  wire [11:0] _07_;
  wire [11:0] _08_;
  wire [11:0] _09_;
  wire [11:0] _10_;
  reg [7:0] _11_;
  wire [98:0] _12_;
  wire _13_;
  wire [7:0] _14_;
  wire [7:0] _15_;
  wire [7:0] _16_;
  reg [7:0] _17_;
  reg [7:0] _18_;
  reg [7:0] _19_;
  reg [7:0] _20_;
  reg _21_;
  reg _22_;
  reg _23_;
  input EOB;
  output EOB_Q_o;
  input SOB;
  wire [7:0] arith_in_col_0;
  wire [7:0] arith_in_col_0_q0;
  wire [7:0] arith_in_col_1;
  wire [7:0] arith_in_col_1_d1;
  wire [7:0] arith_in_col_1_q1;
  wire [7:0] arith_in_col_2;
  wire [7:0] arith_in_col_2_d1;
  wire [7:0] arith_in_col_2_d2;
  wire [7:0] arith_in_col_2_q2;
  wire [7:0] arith_in_row_0;
  wire [7:0] arith_in_row_0_q0;
  wire [7:0] arith_in_row_1;
  wire [7:0] arith_in_row_1_d1;
  wire [7:0] arith_in_row_1_q1;
  wire [7:0] arith_in_row_2;
  wire [7:0] arith_in_row_2_d1;
  wire [7:0] arith_in_row_2_d2;
  wire [7:0] arith_in_row_2_q2;
  wire [7:0] arith_out_col_out_0;
  wire [7:0] arith_out_col_out_0_d1;
  wire [7:0] arith_out_col_out_0_d2;
  wire [7:0] arith_out_col_out_0_q2;
  wire [7:0] arith_out_col_out_1;
  wire [7:0] arith_out_col_out_1_d1;
  wire [7:0] arith_out_col_out_1_q1;
  wire [7:0] arith_out_col_out_2;
  wire [7:0] arith_out_col_out_2_q0;
  input clk;
  input [23:0] colsB;
  output [23:0] colsC;
  wire [23:0] cols_j_arith;
  wire [35:0] cols_j_s3;
  wire [98:0] colsc_laicpt2;
  wire eob_q2;
  wire eob_select;
  wire eob_select_d1;
  wire eob_select_d2;
  wire [23:0] laicpt2_to_arith;
  input [23:0] rowsA;
  wire [23:0] rows_i_arith;
  wire [35:0] rows_i_s3;
  input rst;
  wire sob_q2;
  wire sob_select;
  wire sob_select_d1;
  wire sob_select_d2;
  always @(posedge clk)
    _00_ <= arith_in_row_1;
  always @(posedge clk)
    _11_ <= arith_in_row_2;
  always @(posedge clk)
    _17_ <= arith_in_row_2_d1;
  always @(posedge clk)
    _18_ <= arith_in_col_1;
  always @(posedge clk)
    _19_ <= arith_in_col_2;
  always @(posedge clk)
    _20_ <= arith_in_col_2_d1;
  always @(posedge clk)
    _21_ <= sob_select;
  always @(posedge clk)
    _22_ <= sob_select_d1;
  always @(posedge clk)
    _23_ <= eob_select;
  always @(posedge clk)
    _01_ <= eob_select_d1;
  always @(posedge clk)
    _02_ <= arith_out_col_out_0;
  always @(posedge clk)
    _03_ <= arith_out_col_out_0_d1;
  always @(posedge clk)
    _04_ <= arith_out_col_out_1;
  Arith_to_S3 \cols_a2s3:1.a2s3_j  (
    .S3_o(_08_),
    .arith_i(cols_j_arith[7:0]),
    .clk(clk)
  );
  Arith_to_S3 \cols_a2s3:2.a2s3_j  (
    .S3_o(_09_),
    .arith_i(cols_j_arith[15:8]),
    .clk(clk)
  );
  Arith_to_S3 \cols_a2s3:3.a2s3_j  (
    .S3_o(_10_),
    .arith_i(cols_j_arith[23:16]),
    .clk(clk)
  );
  l2a \cols_l2a:1.l2a_i  (
    .A(colsc_laicpt2[31:0]),
    .arith_o(_14_),
    .clk(clk),
    .isNaN(colsc_laicpt2[32])
  );
  l2a \cols_l2a:2.l2a_i  (
    .A(colsc_laicpt2[64:33]),
    .arith_o(_15_),
    .clk(clk),
    .isNaN(colsc_laicpt2[65])
  );
  l2a \cols_l2a:3.l2a_i  (
    .A(colsc_laicpt2[97:66]),
    .arith_o(_16_),
    .clk(clk),
    .isNaN(colsc_laicpt2[98])
  );
  Arith_to_S3 \rows_a2s3:1.a2s3_i  (
    .S3_o(_05_),
    .arith_i(rows_i_arith[7:0]),
    .clk(clk)
  );
  Arith_to_S3 \rows_a2s3:2.a2s3_i  (
    .S3_o(_06_),
    .arith_i(rows_i_arith[15:8]),
    .clk(clk)
  );
  Arith_to_S3 \rows_a2s3:3.a2s3_i  (
    .S3_o(_07_),
    .arith_i(rows_i_arith[23:16]),
    .clk(clk)
  );
  SystolicArrayKernel sak (
    .EOB(eob_q2),
    .EOB_Q_o(_13_),
    .SOB(sob_q2),
    .clk(clk),
    .colsB(cols_j_s3),
    .colsC(_12_),
    .rowsA(rows_i_s3),
    .rst(rst)
  );
  assign arith_in_row_0 = rowsA[7:0];
  assign arith_in_row_0_q0 = arith_in_row_0;
  assign arith_in_row_1 = rowsA[15:8];
  assign arith_in_row_1_d1 = _00_;
  assign arith_in_row_1_q1 = arith_in_row_1_d1;
  assign arith_in_row_2 = rowsA[23:16];
  assign arith_in_row_2_d1 = _11_;
  assign arith_in_row_2_d2 = _17_;
  assign arith_in_row_2_q2 = arith_in_row_2_d2;
  assign arith_in_col_0 = colsB[7:0];
  assign arith_in_col_0_q0 = arith_in_col_0;
  assign arith_in_col_1 = colsB[15:8];
  assign arith_in_col_1_d1 = _18_;
  assign arith_in_col_1_q1 = arith_in_col_1_d1;
  assign arith_in_col_2 = colsB[23:16];
  assign arith_in_col_2_d1 = _19_;
  assign arith_in_col_2_d2 = _20_;
  assign arith_in_col_2_q2 = arith_in_col_2_d2;
  assign colsc_laicpt2 = _12_;
  assign sob_select = SOB;
  assign sob_select_d1 = _21_;
  assign sob_select_d2 = _22_;
  assign sob_q2 = sob_select_d2;
  assign eob_select = EOB;
  assign eob_select_d1 = _23_;
  assign eob_select_d2 = _01_;
  assign eob_q2 = eob_select_d2;
  assign laicpt2_to_arith = { _16_, _15_, _14_ };
  assign arith_out_col_out_0 = laicpt2_to_arith[7:0];
  assign arith_out_col_out_0_d1 = _02_;
  assign arith_out_col_out_0_d2 = _03_;
  assign arith_out_col_out_0_q2 = arith_out_col_out_0_d2;
  assign arith_out_col_out_1 = laicpt2_to_arith[15:8];
  assign arith_out_col_out_1_d1 = _04_;
  assign arith_out_col_out_1_q1 = arith_out_col_out_1_d1;
  assign arith_out_col_out_2 = laicpt2_to_arith[23:16];
  assign arith_out_col_out_2_q0 = arith_out_col_out_2;
  assign rows_i_arith = { arith_in_row_2_q2, arith_in_row_1_q1, arith_in_row_0_q0 };
  assign rows_i_s3 = { _07_, _06_, _05_ };
  assign cols_j_arith = { arith_in_col_2_q2, arith_in_col_1_q1, arith_in_col_0_q0 };
  assign cols_j_s3 = { _10_, _09_, _08_ };
  assign colsC = { arith_out_col_out_2_q0, arith_out_col_out_1_q1, arith_out_col_out_0_q2 };
  assign EOB_Q_o = _13_;
endmodule