data/full_repos/permissive/435885222/sources/ex.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435885222/sources/ex.v:46: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg1_lt_reg2\' generates 1 bits.\n                                                                    : ... In instance ex\n                8\'b00101010,8\'b00101011:arithmeticres<=reg1_lt_reg2; \n                                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ex(
    input rst,
    input [7:0] aluop_in,
    input [2:0] alusel_in,
    input [31:0] reg1_in,
    input [31:0] reg2_in,
    input [4:0] wd_in,
    input wreg_in,
    input [31:0] link_address_in,
    input [31:0] inst_in,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output reg[31:0] wdata_out,
    output wire[7:0] aluop_out,
    output wire[31:0] mem_addr_out,
    output wire[31:0] reg2_out
    );
    reg[31:0] logicout;
    reg[31:0] shiftres;
    reg[31:0] arithmeticres;
    wire ov_sum;
    wire reg1_lt_reg2;
    wire[31:0] reg2_in_mux;
    wire[31:0] result_sum;
    assign reg2_in_mux=((aluop_in==8'b00100010)||(aluop_in==8'b00100011)||(aluop_in==8'b00101010))?(~reg2_in)+1:reg2_in;
    assign result_sum=reg1_in+reg2_in_mux;
    assign ov_sum=((!reg1_in[31]&&!reg2_in_mux[31])&&result_sum[31])||((reg1_in[31]&&reg2_in_mux[31])&&(!result_sum[31]));

    assign reg1_lt_reg2=((aluop_in==8'b00101010))?((reg1_in[31]&&!reg2_in[31])||(!reg1_in[31]&&!reg2_in[31]&&result_sum[31])||(reg1_in[31]&&reg2_in[31]&&result_sum[31])):(reg1_in<reg2_in);

    assign aluop_out=aluop_in;
    assign mem_addr_out=reg1_in+{{16{inst_in[15]}},inst_in[15:0]};
    assign reg2_out=reg2_in;
    always @(*)begin
        if(rst==1'b1) arithmeticres<=32'h00000000;
        else begin
            case(aluop_in)
                8'b00101010,8'b00101011:arithmeticres<=reg1_lt_reg2;
                8'b00100000,8'b00100001:arithmeticres<=result_sum;
                8'b00100010,8'b00100011:arithmeticres<=result_sum;
                default:arithmeticres<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        if(rst==1'b1) logicout<=32'h00000000;
        else begin
            case(aluop_in)
                8'b00100101:logicout<=reg1_in|reg2_in;
                8'b00100100:logicout<=reg1_in&reg2_in;
                8'b00100111:logicout<=~(reg1_in|reg2_in);
                8'b00100110:logicout<=reg1_in^reg2_in;
                default:logicout<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        if(rst==1'b1) shiftres<=32'h00000000;
        else begin
            case(aluop_in)
                8'b01111100:shiftres<=reg2_in<<reg1_in[4:0];
                8'b00000010:shiftres<=reg2_in>>reg1_in[4:0];
                8'b00000011:shiftres<=({32{reg2_in[31]}}<<(6'd32-{1'b0,reg1_in[4:0]}))|reg2_in>>reg1_in[4:0];
                default:shiftres<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        wd_out<=wd_in;
        if(((aluop_in==8'b00100000)||(aluop_in==8'b00100010))&&(ov_sum==1'b1)) wreg_out<=1'b0;
        else wreg_out<=wreg_in;
        case(alusel_in) 
            3'b001:wdata_out<=logicout;
            3'b010:wdata_out<=shiftres;
            3'b011:wdata_out<=arithmeticres;
            3'b000:wdata_out<=link_address_in;
            default:wdata_out<=32'h00000000;
        endcase
    end
endmodule
module ex(
    input rst,
    input [7:0] aluop_in,
    input [2:0] alusel_in,
    input [31:0] reg1_in,
    input [31:0] reg2_in,
    input [4:0] wd_in,
    input wreg_in,
    input [31:0] link_address_in,
    input [31:0] inst_in,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output reg[31:0] wdata_out,
    output wire[7:0] aluop_out,
    output wire[31:0] mem_addr_out,
    output wire[31:0] reg2_out
    );

    reg[31:0] logicout;
    reg[31:0] shiftres;
    reg[31:0] arithmeticres;
    wire ov_sum;
    wire reg1_lt_reg2;
    wire[31:0] reg2_in_mux;
    wire[31:0] result_sum;
    assign reg2_in_mux=((aluop_in==8'b00100010)||(aluop_in==8'b00100011)||(aluop_in==8'b00101010))?(~reg2_in)+1:reg2_in;
    assign result_sum=reg1_in+reg2_in_mux;
    assign ov_sum=((!reg1_in[31]&&!reg2_in_mux[31])&&result_sum[31])||((reg1_in[31]&&reg2_in_mux[31])&&(!result_sum[31]));

    assign reg1_lt_reg2=((aluop_in==8'b00101010))?((reg1_in[31]&&!reg2_in[31])||(!reg1_in[31]&&!reg2_in[31]&&result_sum[31])||(reg1_in[31]&&reg2_in[31]&&result_sum[31])):(reg1_in<reg2_in);

    assign aluop_out=aluop_in;
    assign mem_addr_out=reg1_in+{{16{inst_in[15]}},inst_in[15:0]};
    assign reg2_out=reg2_in;
    always @(*)begin
        if(rst==1'b1) arithmeticres<=32'h00000000;
        else begin
            case(aluop_in)
                8'b00101010,8'b00101011:arithmeticres<=reg1_lt_reg2;
                8'b00100000,8'b00100001:arithmeticres<=result_sum;
                8'b00100010,8'b00100011:arithmeticres<=result_sum;
                default:arithmeticres<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        if(rst==1'b1) logicout<=32'h00000000;
        else begin
            case(aluop_in)
                8'b00100101:logicout<=reg1_in|reg2_in;
                8'b00100100:logicout<=reg1_in&reg2_in;
                8'b00100111:logicout<=~(reg1_in|reg2_in);
                8'b00100110:logicout<=reg1_in^reg2_in;
                default:logicout<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        if(rst==1'b1) shiftres<=32'h00000000;
        else begin
            case(aluop_in)
                8'b01111100:shiftres<=reg2_in<<reg1_in[4:0];
                8'b00000010:shiftres<=reg2_in>>reg1_in[4:0];
                8'b00000011:shiftres<=({32{reg2_in[31]}}<<(6'd32-{1'b0,reg1_in[4:0]}))|reg2_in>>reg1_in[4:0];
                default:shiftres<=32'h00000000;
            endcase
        end
    end
    always @(*)begin
        wd_out<=wd_in;
        if(((aluop_in==8'b00100000)||(aluop_in==8'b00100010))&&(ov_sum==1'b1)) wreg_out<=1'b0;
        else wreg_out<=wreg_in;
        case(alusel_in) 
            3'b001:wdata_out<=logicout;
            3'b010:wdata_out<=shiftres;
            3'b011:wdata_out<=arithmeticres;
            3'b000:wdata_out<=link_address_in;
            default:wdata_out<=32'h00000000;
        endcase
    end
endmodule