data/full_repos/permissive/52714256/ZOLED/src/toplevel.v
1: b"%Error: data/full_repos/permissive/52714256/ZOLED/src/toplevel.v:101: Cannot find file containing module: 'ZedboardOLED'\nZedboardOLED OLED\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/ZOLED/src,data/full_repos/permissive/52714256/ZedboardOLED\n             data/full_repos/permissive/52714256/ZOLED/src,data/full_repos/permissive/52714256/ZedboardOLED.v\n             data/full_repos/permissive/52714256/ZOLED/src,data/full_repos/permissive/52714256/ZedboardOLED.sv\n             ZedboardOLED\n             ZedboardOLED.v\n             ZedboardOLED.sv\n             obj_dir/ZedboardOLED\n             obj_dir/ZedboardOLED.v\n             obj_dir/ZedboardOLED.sv\n%Error: Exiting due to 1 error(s)\n"
module toplevel
   (DC,
    RES,
    SCLK,
    SDIN,
    VBAT,
    VDD,
    JA1,
    JA2,
    JA3,
    JA4,
    JA7,
    JA8,
    JA9,
    JA10,
    SW0,
    SW1,
    SW2,
    SW3,
    SW4,
    SW5,
    SW6,
    SW7,
    LD0,
    LD1,
    LD2,
    LD3,
    LD4,
    LD5,
    LD6,
    LD7,
    GCLK
    );
    
    output wire JA1;
    output wire JA2;
    output wire JA3;
    output wire JA4;
    output wire JA7;
    output wire JA8;
    output wire JA9;
    output wire JA10;

    output wire DC;
    output wire RES;
    output wire SCLK;
    output wire SDIN;
    output wire VBAT;
    output wire VDD;
    input wire SW0;
    input wire SW1;
    input wire SW2;
    input wire SW3;
    input wire SW4;
    input wire SW5;
    input wire SW6;
    input wire SW7;
    output wire LD0;
    output wire LD1;
    output wire LD2;
    output wire LD3;
    output wire LD4;
    output wire LD5;
    output wire LD6;
    output wire LD7;
    input wire GCLK;

reg [127:0] str;

always @(posedge GCLK) begin
    if (SW1 == 1'b1) begin
        str <= "Hello, world!";
    end
    else begin
        str <= "************";
    end

end    

ZedboardOLED OLED
       (
        .s1(str),
        .s2(str),
        .s3(str),
        .s4(str),
        .DC(DC),
        .RES(RES),
        .SCLK(SCLK),
        .SDIN(SDIN),
        .VBAT(VBAT),
        .VDD(VDD),
        .CLK(GCLK)
        );
        
endmodule
module toplevel
   (DC,
    RES,
    SCLK,
    SDIN,
    VBAT,
    VDD,
    JA1,
    JA2,
    JA3,
    JA4,
    JA7,
    JA8,
    JA9,
    JA10,
    SW0,
    SW1,
    SW2,
    SW3,
    SW4,
    SW5,
    SW6,
    SW7,
    LD0,
    LD1,
    LD2,
    LD3,
    LD4,
    LD5,
    LD6,
    LD7,
    GCLK
    );

    
    output wire JA1;
    output wire JA2;
    output wire JA3;
    output wire JA4;
    output wire JA7;
    output wire JA8;
    output wire JA9;
    output wire JA10;

    output wire DC;
    output wire RES;
    output wire SCLK;
    output wire SDIN;
    output wire VBAT;
    output wire VDD;
    input wire SW0;
    input wire SW1;
    input wire SW2;
    input wire SW3;
    input wire SW4;
    input wire SW5;
    input wire SW6;
    input wire SW7;
    output wire LD0;
    output wire LD1;
    output wire LD2;
    output wire LD3;
    output wire LD4;
    output wire LD5;
    output wire LD6;
    output wire LD7;
    input wire GCLK;

reg [127:0] str;

always @(posedge GCLK) begin
    if (SW1 == 1'b1) begin
        str <= "Hello, world!";
    end
    else begin
        str <= "************";
    end

end    

ZedboardOLED OLED
       (
        .s1(str),
        .s2(str),
        .s3(str),
        .s4(str),
        .DC(DC),
        .RES(RES),
        .SCLK(SCLK),
        .SDIN(SDIN),
        .VBAT(VBAT),
        .VDD(VDD),
        .CLK(GCLK)
        );
        
endmodule