data/full_repos/permissive/497530416/pipe/m_reg.v
data/verilator_xmls/48a483bb-4a97-483f-b49b-f8c664c6690d.xml
module m_reg_pipe (clk, e_cnd, e_icode, e_valA, e_valE, e_dstE, e_dstM, 
                M_cnd, M_icode, M_valE, M_valA, M_dstE, M_dstM);

input clk, e_cnd;

input [3:0] e_icode, e_dstE, e_dstM;
input [63:0] e_valA, e_valE;

output reg M_cnd;

output reg [3:0] M_icode, M_dstE, M_dstM; 
output reg [63:0] M_valE, M_valA;

always @(posedge clk)
    begin

        M_cnd <= e_cnd;
        M_icode <= e_icode;



        M_valA <= e_valA;



        M_valE <= e_valE;
        M_dstE <= e_dstE;
        M_dstM <= e_dstM;
    end
endmodule
module m_reg_pipe (clk, e_cnd, e_icode, e_valA, e_valE, e_dstE, e_dstM, 
                M_cnd, M_icode, M_valE, M_valA, M_dstE, M_dstM);


input clk, e_cnd;

input [3:0] e_icode, e_dstE, e_dstM;
input [63:0] e_valA, e_valE;

output reg M_cnd;

output reg [3:0] M_icode, M_dstE, M_dstM; 
output reg [63:0] M_valE, M_valA;

always @(posedge clk)
    begin

        M_cnd <= e_cnd;
        M_icode <= e_icode;



        M_valA <= e_valA;



        M_valE <= e_valE;
        M_dstE <= e_dstE;
        M_dstM <= e_dstM;
    end
endmodule