data/full_repos/permissive/515599642/Simple CPU module using Verilog/Q_Register.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/Q_Register.v\n%Error: Exiting due to 6 error(s)\n'
module Q_Reg(S, clk, Q_EN, Q);

input[3:0] S;
input clk;
input Q_EN;
output reg[3:0] Q;

always@(posedge clk)begin
	if (Q_EN==1)
		Q=S;
	else
		Q=Q;
	end
endmodule
module Q_Reg(S, clk, Q_EN, Q);


input[3:0] S;
input clk;
input Q_EN;
output reg[3:0] Q;

always@(posedge clk)begin
	if (Q_EN==1)
		Q=S;
	else
		Q=Q;
	end
endmodule