data/full_repos/permissive/520428138/verilog/rtl/scan_controller/scan_controller.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/scan_controller/scan_controller.v:36: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] oeb  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/scan_controller/scan_controller.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign oeb = {`MPRJ_IO_PADS{1'b0}};\n                  ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module clk_divider #(
    parameter integer DIV_WIDTH = 8
)(
    input  wire clk,
    input  wire ce,
    input  wire reset,
    input  wire set,
    input  wire [DIV_WIDTH-1:0] divider,
    output wire active,
    output reg  slow_clk
);

    reg [DIV_WIDTH-1:0] counter;
    reg [DIV_WIDTH-1:0] compare;
    wire                match;

    reg [2:0] set_sync;
    reg       set_now;


    always @(posedge clk)
    begin
        set_sync <= { set_sync[1:0], set };
        set_now  <= ~set_sync[2] & set_sync[1];
    end

    assign active = set_sync[2];


    always @(posedge clk)
        if (set_now)
            compare <= divider;


    assign match = (counter == compare);


    always @(posedge clk or posedge reset)
        if (reset)
            counter <= 0;
        else if (ce)
            counter <= match ? 0 : (counter + 1);


    always @(posedge clk or posedge reset)
        if (reset)
            slow_clk <= 1'b0;
        else if (ce)
            slow_clk <= slow_clk ^ match;

endmodule
module clk_divider #(
    parameter integer DIV_WIDTH = 8
)(
    input  wire clk,
    input  wire ce,
    input  wire reset,
    input  wire set,
    input  wire [DIV_WIDTH-1:0] divider,
    output wire active,
    output reg  slow_clk
);


    reg [DIV_WIDTH-1:0] counter;
    reg [DIV_WIDTH-1:0] compare;
    wire                match;

    reg [2:0] set_sync;
    reg       set_now;


    always @(posedge clk)
    begin
        set_sync <= { set_sync[1:0], set };
        set_now  <= ~set_sync[2] & set_sync[1];
    end

    assign active = set_sync[2];


    always @(posedge clk)
        if (set_now)
            compare <= divider;


    assign match = (counter == compare);


    always @(posedge clk or posedge reset)
        if (reset)
            counter <= 0;
        else if (ce)
            counter <= match ? 0 : (counter + 1);


    always @(posedge clk or posedge reset)
        if (reset)
            slow_clk <= 1'b0;
        else if (ce)
            slow_clk <= slow_clk ^ match;

endmodule