data/full_repos/permissive/496903659/166 sim#circuit3.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/166\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/166\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/166.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/166.sv\n             data/full_repos/permissive/496903659/166\n             data/full_repos/permissive/496903659/166.v\n             data/full_repos/permissive/496903659/166.sv\n             obj_dir/data/full_repos/permissive/496903659/166\n             obj_dir/data/full_repos/permissive/496903659/166.v\n             obj_dir/data/full_repos/permissive/496903659/166.sv\n%Error: Cannot find file containing module: sim#circuit3.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = (a | b) & (c | d);

endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );


    assign q = (a | b) & (c | d);

endmodule