data/full_repos/permissive/418753087/smart_run/logical/smpu/smpu_top.v
1: b"%Error: data/full_repos/permissive/418753087/smart_run/logical/smpu/smpu_top.v:151: Cannot find file containing module: 'smpu_comp_hit'\nsmpu_comp_hit  x_smpu_comp_hit_0 (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418753087/smart_run/logical/smpu,data/full_repos/permissive/418753087/smpu_comp_hit\n             data/full_repos/permissive/418753087/smart_run/logical/smpu,data/full_repos/permissive/418753087/smpu_comp_hit.v\n             data/full_repos/permissive/418753087/smart_run/logical/smpu,data/full_repos/permissive/418753087/smpu_comp_hit.sv\n             smpu_comp_hit\n             smpu_comp_hit.v\n             smpu_comp_hit.sv\n             obj_dir/smpu_comp_hit\n             obj_dir/smpu_comp_hit.v\n             obj_dir/smpu_comp_hit.sv\n%Error: data/full_repos/permissive/418753087/smart_run/logical/smpu/smpu_top.v:167: Cannot find file containing module: 'smpu_comp_hit'\nsmpu_comp_hit  x_smpu_comp_hit_1 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/smpu/smpu_top.v:182: Cannot find file containing module: 'smpu_comp_hit'\nsmpu_comp_hit  x_smpu_comp_hit_2 (\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module smpu_top(
  biu_pad_haddr,
  biu_pad_hprot,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  smpu_deny
);


input   [31:0]  biu_pad_haddr;   
input   [3 :0]  biu_pad_hprot;   
input   [3 :2]  paddr;           
input           pclk;            
input           penable;         
input           presetn;         
input           psel;            
input   [31:0]  pwdata;          
input           pwrite;          
output  [31:0]  prdata;          
output          smpu_deny;       


reg     [31:0]  prdata;          
reg     [31:0]  smpu_entry0;     
reg     [31:0]  smpu_entry1;     
reg     [31:0]  smpu_entry2;     


wire    [31:0]  biu_pad_haddr;   
wire    [3 :0]  biu_pad_hprot;   
wire            hsec_0;          
wire            hsec_1;          
wire            hsec_2;          
wire            pad_biu_hsec_pre; 
wire    [3 :2]  paddr;           
wire            pclk;            
wire            penable;         
wire            presetn;         
wire            psel;            
wire    [31:0]  pwdata;          
wire            pwrite;          
wire            smpu_deny;       
wire            smpu_hit0;       
wire            smpu_hit1;       
wire            smpu_hit2;       









always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
    smpu_entry0 <= 32'b0;
    smpu_entry1 <= 32'b0;
    smpu_entry2 <= 32'b0;
  end
  else
  begin
    if(psel && pwrite && penable)
    begin
      case(paddr[3:2])
        2'b00:
        begin
          smpu_entry0[31:0] <= pwdata[31:0];
        end
        2'b01:
        begin
          smpu_entry1[31:0] <= pwdata[31:0];
        end
        2'b10:
        begin
          smpu_entry2[31:0] <= pwdata[31:0];
        end
      endcase
    end
  end
end
    



always @(posedge pclk)
begin
  if(psel && !pwrite && !penable)
  begin
    case(paddr[3:2])
      2'b00:
      begin
        prdata[31:0] <= smpu_entry0[31:0];
      end
      2'b01:
      begin
        prdata[31:0] <= smpu_entry1[31:0];
      end
      2'b10:
      begin
        prdata[31:0] <= smpu_entry2[31:0];
      end
      default:
      begin
        prdata[31:0] <= 32'bx;
      end
    endcase
  end
end













assign smpu_deny = smpu_hit0 || smpu_hit1 || smpu_hit2;


smpu_comp_hit  x_smpu_comp_hit_0 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry0  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit0    ),
  .smpu_hsec     (hsec_0       )
);








smpu_comp_hit  x_smpu_comp_hit_1 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry1  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit1    ),
  .smpu_hsec     (hsec_1       )
);







smpu_comp_hit  x_smpu_comp_hit_2 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry2  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit2    ),
  .smpu_hsec     (hsec_2       )
);








assign pad_biu_hsec_pre = hsec_0 || hsec_1 || hsec_2;







endmodule
module smpu_top(
  biu_pad_haddr,
  biu_pad_hprot,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  smpu_deny
);



input   [31:0]  biu_pad_haddr;   
input   [3 :0]  biu_pad_hprot;   
input   [3 :2]  paddr;           
input           pclk;            
input           penable;         
input           presetn;         
input           psel;            
input   [31:0]  pwdata;          
input           pwrite;          
output  [31:0]  prdata;          
output          smpu_deny;       


reg     [31:0]  prdata;          
reg     [31:0]  smpu_entry0;     
reg     [31:0]  smpu_entry1;     
reg     [31:0]  smpu_entry2;     


wire    [31:0]  biu_pad_haddr;   
wire    [3 :0]  biu_pad_hprot;   
wire            hsec_0;          
wire            hsec_1;          
wire            hsec_2;          
wire            pad_biu_hsec_pre; 
wire    [3 :2]  paddr;           
wire            pclk;            
wire            penable;         
wire            presetn;         
wire            psel;            
wire    [31:0]  pwdata;          
wire            pwrite;          
wire            smpu_deny;       
wire            smpu_hit0;       
wire            smpu_hit1;       
wire            smpu_hit2;       









always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
    smpu_entry0 <= 32'b0;
    smpu_entry1 <= 32'b0;
    smpu_entry2 <= 32'b0;
  end
  else
  begin
    if(psel && pwrite && penable)
    begin
      case(paddr[3:2])
        2'b00:
        begin
          smpu_entry0[31:0] <= pwdata[31:0];
        end
        2'b01:
        begin
          smpu_entry1[31:0] <= pwdata[31:0];
        end
        2'b10:
        begin
          smpu_entry2[31:0] <= pwdata[31:0];
        end
      endcase
    end
  end
end
    



always @(posedge pclk)
begin
  if(psel && !pwrite && !penable)
  begin
    case(paddr[3:2])
      2'b00:
      begin
        prdata[31:0] <= smpu_entry0[31:0];
      end
      2'b01:
      begin
        prdata[31:0] <= smpu_entry1[31:0];
      end
      2'b10:
      begin
        prdata[31:0] <= smpu_entry2[31:0];
      end
      default:
      begin
        prdata[31:0] <= 32'bx;
      end
    endcase
  end
end













assign smpu_deny = smpu_hit0 || smpu_hit1 || smpu_hit2;


smpu_comp_hit  x_smpu_comp_hit_0 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry0  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit0    ),
  .smpu_hsec     (hsec_0       )
);








smpu_comp_hit  x_smpu_comp_hit_1 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry1  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit1    ),
  .smpu_hsec     (hsec_1       )
);







smpu_comp_hit  x_smpu_comp_hit_2 (
  .biu_pad_haddr (biu_pad_haddr),
  .biu_pad_hprot (biu_pad_hprot),
  .smpu_entry    (smpu_entry2  ),
  .smpu_entry0   (smpu_entry0  ),
  .smpu_hit      (smpu_hit2    ),
  .smpu_hsec     (hsec_2       )
);








assign pad_biu_hsec_pre = hsec_0 || hsec_1 || hsec_2;







endmodule