data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/testbench/sourcexxxxx/tbcoretest.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/testbench/sourcexxxxx/tbcoretest.v:68: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'fifowr_en\' generates 1 bits.\n                                                                                                                                              : ... In instance tbcoretest\nalways @ (posedge clk)  fifodi <= fifodi + fifowr_en; \n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module tbcoretest
    (clk,
     rst,


     fifowr,
     fifodi,


     fiford,
     fifodo,
     fifodovld
     );



parameter   WID = 8;
parameter   WRBW = 50;
parameter   RDBW = 50;



input               clk,
                    rst;


output              fifowr;
output [WID-1:0]    fifodi;



output              fiford;
input [WID-1:0]     fifodo;
input               fifodovld;








reg [7:0]           bwcnt;
always @ (posedge clk or posedge rst)
    begin
    if (rst)    bwcnt <= 8'd0;
    else        bwcnt <= (bwcnt >= 8'd99) ? 8'd0 : bwcnt + 1'b1;
    end

reg                 fifowr = 1'b0;
wire                fifowr_en = (bwcnt < WRBW); 
always @ (posedge clk)  fifowr <= fifowr_en;

reg [WID-1:0]       fifodi = 8'd0;
always @ (posedge clk)  fifodi <= fifodi + fifowr_en;

reg                 fiford = 1'b0;
wire                fiford_en = (bwcnt < RDBW); 
always @ (posedge clk)  fiford <= fiford_en;

reg [WID-1:0]       fifodo_lat = 8'd0;
always @ (posedge clk)  if (fifodovld)  fifodo_lat <= fifodo;

wire                error;
assign              error = fifodovld & (fifodo != fifodo_lat + 1'b1);


`ifdef  RTL_LOG_FILE
always @ (posedge clk)
    begin
    if (error) $fdisplay (rtllogfile,"ERROR @time %t",$time);
    end
`endif
endmodule
module tbcoretest
    (clk,
     rst,


     fifowr,
     fifodi,


     fiford,
     fifodo,
     fifodovld
     );




parameter   WID = 8;
parameter   WRBW = 50;
parameter   RDBW = 50;



input               clk,
                    rst;


output              fifowr;
output [WID-1:0]    fifodi;



output              fiford;
input [WID-1:0]     fifodo;
input               fifodovld;








reg [7:0]           bwcnt;
always @ (posedge clk or posedge rst)
    begin
    if (rst)    bwcnt <= 8'd0;
    else        bwcnt <= (bwcnt >= 8'd99) ? 8'd0 : bwcnt + 1'b1;
    end

reg                 fifowr = 1'b0;
wire                fifowr_en = (bwcnt < WRBW); 
always @ (posedge clk)  fifowr <= fifowr_en;

reg [WID-1:0]       fifodi = 8'd0;
always @ (posedge clk)  fifodi <= fifodi + fifowr_en;

reg                 fiford = 1'b0;
wire                fiford_en = (bwcnt < RDBW); 
always @ (posedge clk)  fiford <= fiford_en;

reg [WID-1:0]       fifodo_lat = 8'd0;
always @ (posedge clk)  if (fifodovld)  fifodo_lat <= fifodo;

wire                error;
assign              error = fifodovld & (fifodo != fifodo_lat + 1'b1);


`ifdef  RTL_LOG_FILE
always @ (posedge clk)
    begin
    if (error) $fdisplay (rtllogfile,"ERROR @time %t",$time);
    end
`endif
endmodule