data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:47: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'in3\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in2);\n ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:47: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in2\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:49: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in1\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:54: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'in6\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in5);\n ^\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:54: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in5\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in5);\n ^\n%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2Add3u8u8u8Add3u8u8u8_1.v:56: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'in4\' generates 8 bits.\n                                                                                                                                                                     : ... In instance dut_Mul2Add3u8u8u8Add3u8u8u8_1\n +(in4);\n ^\n%Error: Exiting due to 6 warning(s)\n'
module dut_Mul2Add3u8u8u8Add3u8u8u8_1 (
	in6,
	in5,
	in4,
	in3,
	in2,
	in1,
	out1
	);
input [7:0] in6,
	in5,
	in4,
	in3,
	in2,
	in1;
output [19:0] out1;
wire [19:0] asc001;
wire [9:0] asc002,
	asc003;

wire [9:0] asc002_tmp_0;
assign asc002_tmp_0 = 
	+(in3)
	+(in2);
assign asc002 = asc002_tmp_0
	+(in1);

wire [9:0] asc003_tmp_1;
assign asc003_tmp_1 = 
	+(in6)
	+(in5);
assign asc003 = asc003_tmp_1
	+(in4);

assign asc001 = 
	+(asc002 * asc003);

assign out1 = asc001;
endmodule
module dut_Mul2Add3u8u8u8Add3u8u8u8_1 (
	in6,
	in5,
	in4,
	in3,
	in2,
	in1,
	out1
	);

input [7:0] in6,
	in5,
	in4,
	in3,
	in2,
	in1;
output [19:0] out1;
wire [19:0] asc001;
wire [9:0] asc002,
	asc003;

wire [9:0] asc002_tmp_0;
assign asc002_tmp_0 = 
	+(in3)
	+(in2);
assign asc002 = asc002_tmp_0
	+(in1);

wire [9:0] asc003_tmp_1;
assign asc003_tmp_1 = 
	+(in6)
	+(in5);
assign asc003 = asc003_tmp_1
	+(in4);

assign asc001 = 
	+(asc002 * asc003);

assign out1 = asc001;
endmodule