data/full_repos/permissive/515477729/source/alu.v
data/verilator_xmls/69d5df65-5fb9-4c02-98e9-ddf361552209.xml
module alu  (output reg [15:0] out, input [15:0] in1, input [15:0] in2, input addsub);

    always @(*) begin
        if (addsub == 0) 
            out = in1 - in2;
        else 
            out = in1 + in2;
    end
endmodule
module alu  (output reg [15:0] out, input [15:0] in1, input [15:0] in2, input addsub);


    always @(*) begin
        if (addsub == 0) 
            out = in1 - in2;
        else 
            out = in1 + in2;
    end
endmodule