data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_lut_1(glb_rstn_i, config_i, logic_i, logic_o);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire _7_;
  wire _8_;
  input [1:0] config_i;
  input glb_rstn_i;
  input logic_i;
  output logic_o;
  wire lut_out;
  wire sublut0_out;
  wire sublut1_out;
  assign _0_ = ~ sublut0_out;
  assign _1_ = ~ sublut1_out;
  assign _2_ = _0_ & _1_;
  assign _3_ = sublut0_out & sublut1_out;
  assign _4_ = ~ logic_i;
  assign _5_ = logic_i ? sublut1_out : 1'h0;
  assign _6_ = _4_ ? sublut0_out : _5_;
  assign _7_ = _3_ ? 1'h1 : _6_;
  assign _8_ = _2_ ? 1'h0 : _7_;
  assign lut_out = _8_;
  assign sublut0_out = config_i[0];
  assign sublut1_out = config_i[1];
  assign logic_o = lut_out;
endmodule
module fpga_lut_1(glb_rstn_i, config_i, logic_i, logic_o);

  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire _7_;
  wire _8_;
  input [1:0] config_i;
  input glb_rstn_i;
  input logic_i;
  output logic_o;
  wire lut_out;
  wire sublut0_out;
  wire sublut1_out;
  assign _0_ = ~ sublut0_out;
  assign _1_ = ~ sublut1_out;
  assign _2_ = _0_ & _1_;
  assign _3_ = sublut0_out & sublut1_out;
  assign _4_ = ~ logic_i;
  assign _5_ = logic_i ? sublut1_out : 1'h0;
  assign _6_ = _4_ ? sublut0_out : _5_;
  assign _7_ = _3_ ? 1'h1 : _6_;
  assign _8_ = _2_ ? 1'h0 : _7_;
  assign lut_out = _8_;
  assign sublut0_out = config_i[0];
  assign sublut1_out = config_i[1];
  assign logic_o = lut_out;
endmodule