data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v
data/verilator_xmls/2cb91ad2-cdcb-4b03-b687-ce1e1ce57d09.xml
module pfpu_marocchino_div
(

  input             cpu_clk,

  input             pipeline_flush_i,
  input             s1o_div_ready_i,
  output            div_busy_o,
  output            div_taking_op_o,
  output reg        div_rdy_o,
  input             rnd_taking_div_i,

  input             s1o_signc_i,
  input      [12:0] s2t_exp13c_i,
  input      [10:0] s2t_shrx_i,
  input      [52:0] s1o_fract53a_i,
  input      [52:0] s1o_fract53b_i,
  input             s1o_opc_0_i,
  input             s1o_dbz_i,
  input             s1o_op_fp64_arith_i,

  output reg        div_sign_o,
  output reg [10:0] div_shr_o,
  output reg        div_shl_o,
  output reg [12:0] div_exp13sh0_o,
  output reg [56:0] div_fract57_o,
  output reg        div_dbz_o
);





  wire  s2o_div_ready, s2o_proc;

  wire out_busy = div_rdy_o & ~rnd_taking_div_i;
  wire s2_busy  = s2o_proc | (s2o_div_ready & out_busy);

  wire s2_adv  = s1o_div_ready_i & ~s2_busy;
  wire out_adv = s2o_div_ready   & ~out_busy;

  assign div_busy_o      = s1o_div_ready_i & s2_busy;
  assign div_taking_op_o = s2_adv;



  reg        s2o_signc;
  reg [12:0] s2o_exp13c;
  reg [10:0] s2o_shrx;

  wire       s2o_dbz;

  reg        s2o_op_fp64_arith;

  always @(posedge cpu_clk) begin
    if (s2_adv) begin
      s2o_signc         <= s1o_signc_i;
      s2o_exp13c        <= s2t_exp13c_i;
      s2o_shrx          <= s1o_opc_0_i ? 11'd0 : s2t_shrx_i;
      s2o_op_fp64_arith <= s1o_op_fp64_arith_i;
    end
  end

  wire [57:0] s3t_rem58;
  wire [57:0] s3t_qtnt58;



  r4div_fract58 u_r4div_fract
  (

    .cpu_clk              (cpu_clk),

    .pipeline_flush_i     (pipeline_flush_i),
    .div_start_i          (s2_adv),
    .div_proc_o           (s2o_proc),
    .div_valid_o          (s2o_div_ready),
    .wb_taking_div_i      (out_adv),

    .s1o_opc_0_i          (s1o_opc_0_i),
    .s1o_dbz_i            (s1o_dbz_i),

    .num_i                ({2'b0,s1o_fract53a_i,3'd0}),
    .den_i                ({s1o_fract53b_i,5'd0}),

    .s1o_op_fp64_arith_i  (s1o_op_fp64_arith_i),

    .dbz_o                (s2o_dbz),
    .rem_o                (s3t_rem58),
    .qtnt_o               (s3t_qtnt58)
  );











  wire        s3t_sticky = (s2o_op_fp64_arith & s3t_qtnt58[1]) | (s3t_qtnt58[0]) | (|s3t_rem58);
  wire [56:0] s3t_qtnt57 = {(s2o_op_fp64_arith ? (s3t_qtnt58[57:2]) : (s3t_qtnt58[56:1])), s3t_sticky};





  wire s3t_nlz = s2o_op_fp64_arith ? (~s3t_qtnt58[56]) : (~s3t_qtnt58[26]);

  wire s3t_shlx  =

        (~s3t_nlz)            ? 1'b0 :

        (s2o_exp13c >  13'd1) ? 1'b1 : 1'b0;


  always @(posedge cpu_clk) begin
    if (out_adv) begin
      div_sign_o     <= s2o_signc;
      div_shr_o      <= s2o_shrx;
      div_shl_o      <= s3t_shlx;
      div_exp13sh0_o <= s2o_exp13c;
      div_fract57_o  <= s3t_qtnt57;
    end
  end

  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      div_dbz_o <= 1'b0;
    else if (out_adv)
      div_dbz_o <= s2o_dbz;
  end



  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      div_rdy_o <= 1'b0;
    else if (out_adv)
      div_rdy_o <= 1'b1;
    else if (rnd_taking_div_i)
      div_rdy_o <= 1'b0;
  end

endmodule
module pfpu_marocchino_div
(

  input             cpu_clk,

  input             pipeline_flush_i,
  input             s1o_div_ready_i,
  output            div_busy_o,
  output            div_taking_op_o,
  output reg        div_rdy_o,
  input             rnd_taking_div_i,

  input             s1o_signc_i,
  input      [12:0] s2t_exp13c_i,
  input      [10:0] s2t_shrx_i,
  input      [52:0] s1o_fract53a_i,
  input      [52:0] s1o_fract53b_i,
  input             s1o_opc_0_i,
  input             s1o_dbz_i,
  input             s1o_op_fp64_arith_i,

  output reg        div_sign_o,
  output reg [10:0] div_shr_o,
  output reg        div_shl_o,
  output reg [12:0] div_exp13sh0_o,
  output reg [56:0] div_fract57_o,
  output reg        div_dbz_o
);






  wire  s2o_div_ready, s2o_proc;

  wire out_busy = div_rdy_o & ~rnd_taking_div_i;
  wire s2_busy  = s2o_proc | (s2o_div_ready & out_busy);

  wire s2_adv  = s1o_div_ready_i & ~s2_busy;
  wire out_adv = s2o_div_ready   & ~out_busy;

  assign div_busy_o      = s1o_div_ready_i & s2_busy;
  assign div_taking_op_o = s2_adv;



  reg        s2o_signc;
  reg [12:0] s2o_exp13c;
  reg [10:0] s2o_shrx;

  wire       s2o_dbz;

  reg        s2o_op_fp64_arith;

  always @(posedge cpu_clk) begin
    if (s2_adv) begin
      s2o_signc         <= s1o_signc_i;
      s2o_exp13c        <= s2t_exp13c_i;
      s2o_shrx          <= s1o_opc_0_i ? 11'd0 : s2t_shrx_i;
      s2o_op_fp64_arith <= s1o_op_fp64_arith_i;
    end
  end

  wire [57:0] s3t_rem58;
  wire [57:0] s3t_qtnt58;



  r4div_fract58 u_r4div_fract
  (

    .cpu_clk              (cpu_clk),

    .pipeline_flush_i     (pipeline_flush_i),
    .div_start_i          (s2_adv),
    .div_proc_o           (s2o_proc),
    .div_valid_o          (s2o_div_ready),
    .wb_taking_div_i      (out_adv),

    .s1o_opc_0_i          (s1o_opc_0_i),
    .s1o_dbz_i            (s1o_dbz_i),

    .num_i                ({2'b0,s1o_fract53a_i,3'd0}),
    .den_i                ({s1o_fract53b_i,5'd0}),

    .s1o_op_fp64_arith_i  (s1o_op_fp64_arith_i),

    .dbz_o                (s2o_dbz),
    .rem_o                (s3t_rem58),
    .qtnt_o               (s3t_qtnt58)
  );











  wire        s3t_sticky = (s2o_op_fp64_arith & s3t_qtnt58[1]) | (s3t_qtnt58[0]) | (|s3t_rem58);
  wire [56:0] s3t_qtnt57 = {(s2o_op_fp64_arith ? (s3t_qtnt58[57:2]) : (s3t_qtnt58[56:1])), s3t_sticky};





  wire s3t_nlz = s2o_op_fp64_arith ? (~s3t_qtnt58[56]) : (~s3t_qtnt58[26]);

  wire s3t_shlx  =

        (~s3t_nlz)            ? 1'b0 :

        (s2o_exp13c >  13'd1) ? 1'b1 : 1'b0;


  always @(posedge cpu_clk) begin
    if (out_adv) begin
      div_sign_o     <= s2o_signc;
      div_shr_o      <= s2o_shrx;
      div_shl_o      <= s3t_shlx;
      div_exp13sh0_o <= s2o_exp13c;
      div_fract57_o  <= s3t_qtnt57;
    end
  end

  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      div_dbz_o <= 1'b0;
    else if (out_adv)
      div_dbz_o <= s2o_dbz;
  end



  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      div_rdy_o <= 1'b0;
    else if (out_adv)
      div_rdy_o <= 1'b1;
    else if (rnd_taking_div_i)
      div_rdy_o <= 1'b0;
  end

endmodule