data/full_repos/permissive/470590146/core/regfile.v
data/verilator_xmls/456bb300-07f3-40c5-b649-4fbf547a93e4.xml
module regfile (
	input clk,


	input  [4 :0] rd_addr_1,
	output [31:0] data_o_1,

	input  [4 :0] rd_addr_2,
	output [31:0] data_o_2,

	input  [4 :0] wr_addr,
	input  wr_en,
	input  [31:0] wr_data  
);

reg [31:0] files [0:31];

always @(posedge clk) begin
	if (wr_en == 1'b1)
		files[wr_addr] <= wr_data;
end

assign data_o_1 = rd_addr_1 == 5'd0 ? 32'd0 : files[rd_addr_1];
assign data_o_2 = rd_addr_2 == 5'd0 ? 32'd0 : files[rd_addr_2];


endmodule
module regfile (
	input clk,


	input  [4 :0] rd_addr_1,
	output [31:0] data_o_1,

	input  [4 :0] rd_addr_2,
	output [31:0] data_o_2,

	input  [4 :0] wr_addr,
	input  wr_en,
	input  [31:0] wr_data  
);


reg [31:0] files [0:31];

always @(posedge clk) begin
	if (wr_en == 1'b1)
		files[wr_addr] <= wr_data;
end

assign data_o_1 = rd_addr_1 == 5'd0 ? 32'd0 : files[rd_addr_1];
assign data_o_2 = rd_addr_2 == 5'd0 ? 32'd0 : files[rd_addr_2];


endmodule