data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341457494561784402.v:11: Pin not found: '__pinNumber3'\n    );\n    ^\n%Error: Exiting due to 1 error(s)\n"
module GCD_341457494561784402(
  input        clock,
  input  [3:0] io_value1,
  input  [3:0] io_value2,
  input        io_loadingValues,
  output [3:0] io_outputGCD,
  output       io_outputValid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg [3:0] x;
  reg [3:0] y;
  wire [3:0] _x_T_1 = x - y;
  wire [3:0] _y_T_1 = y - x;
  assign io_outputGCD = x;
  assign io_outputValid = y == 4'h0;
  always @(posedge clock) begin
    if (io_loadingValues) begin
      x <= io_value1;
    end else if (x > y) begin
      x <= _x_T_1;
    end
    if (io_loadingValues) begin
      y <= io_value2;
    end else if (!(x > y)) begin
      y <= _y_T_1;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module GCD_341457494561784402(
  input        clock,
  input  [3:0] io_value1,
  input  [3:0] io_value2,
  input        io_loadingValues,
  output [3:0] io_outputGCD,
  output       io_outputValid
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  reg [3:0] x;
  reg [3:0] y;
  wire [3:0] _x_T_1 = x - y;
  wire [3:0] _y_T_1 = y - x;
  assign io_outputGCD = x;
  assign io_outputValid = y == 4'h0;
  always @(posedge clock) begin
    if (io_loadingValues) begin
      x <= io_value1;
    end else if (x > y) begin
      x <= _x_T_1;
    end
    if (io_loadingValues) begin
      y <= io_value2;
    end else if (!(x > y)) begin
      y <= _y_T_1;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule