data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:36: Cannot find file containing module: \'SerialServo\'\nSerialServo U0 (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialServo\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialServo.v\n             data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new,data/full_repos/permissive/48004801/SerialServo.sv\n             SerialServo\n             SerialServo.v\n             SerialServo.sv\n             obj_dir/SerialServo\n             obj_dir/SerialServo.v\n             obj_dir/SerialServo.sv\n%Error: data/full_repos/permissive/48004801/ServoCommander.srcs/sim_1/new/SerialServo_tb.v:47: Cannot find file containing module: \'SerialServo\'\nSerialServo U1 (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SerialServo_tb;

parameter CHANNEL_WIDTH = 5;
parameter POSITION_WIDTH = 11;

reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [1:0] pwm;

reg [7:0] data_in [3:0];

SerialServo U0 (
    .clk100MHz(clk),
    .clk1MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .channel(5'h02),
    .pwm(pwm[0])
);

SerialServo U1 (
    .clk100MHz(clk),
    .clk1MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .channel(5'h04),
    .pwm(pwm[1])
);

integer i = 0;
integer state = 0;
initial
begin
    ext_clk = 0;
    rst = 1;
    ext_flush = 0;
    serial = 0;
    data_in[0] = 8'b00010_111;
    data_in[1] = 8'b1111_1111;

    data_in[2] = 8'b00100_100;
    data_in[3] = 8'b0000_0000;
    #5
    ext_flush = 1;
    rst = 0;
    #5
    ext_flush = 0;
    
    state = 1;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[2][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end
    
    state = 2;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[3][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 3;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[0][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 4;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 5;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = 1; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end
    #5
    ext_flush = 1;
    #5
    ext_flush = 0;
    #50
    #10 $stop;   
    #5 $finish;
end

endmodule
module SerialServo_tb;


parameter CHANNEL_WIDTH = 5;
parameter POSITION_WIDTH = 11;

reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [1:0] pwm;

reg [7:0] data_in [3:0];

SerialServo U0 (
    .clk100MHz(clk),
    .clk1MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .channel(5'h02),
    .pwm(pwm[0])
);

SerialServo U1 (
    .clk100MHz(clk),
    .clk1MHz(clk),
    .rst(rst),
    .ext_clk(ext_clk),
    .ext_flush(ext_flush),
    .serial(serial),
    .channel(5'h04),
    .pwm(pwm[1])
);

integer i = 0;
integer state = 0;
initial
begin
    ext_clk = 0;
    rst = 1;
    ext_flush = 0;
    serial = 0;
    data_in[0] = 8'b00010_111;
    data_in[1] = 8'b1111_1111;

    data_in[2] = 8'b00100_100;
    data_in[3] = 8'b0000_0000;
    #5
    ext_flush = 1;
    rst = 0;
    #5
    ext_flush = 0;
    
    state = 1;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[2][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end
    
    state = 2;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[3][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 3;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[0][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 4;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = data_in[1][7-i]; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end

    state = 5;
    for(i = 0; i < 8; i=i+1) begin
        #1
        clk = 0;
        ext_clk = 0;
        #1
        clk = 1;
        #1
        clk = 0;
        serial = 1; 
        #5
        ext_clk = 1;
        #1
        clk = 1;
    end
    #5
    ext_flush = 1;
    #5
    ext_flush = 0;
    #50
    #10 $stop;   
    #5 $finish;
end

endmodule