data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Counters/4-digit decimal counter.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/463549945\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945.sv\n             Logic/Counters,data/full_repos/permissive/463549945\n             Logic/Counters,data/full_repos/permissive/463549945.v\n             Logic/Counters,data/full_repos/permissive/463549945.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/4-digit\n%Error: Cannot find file containing module: decimal\n%Error: Cannot find file containing module: counter.v\n%Error: Exiting due to 5 error(s)\n'
module decade_cnt (
    input clk,
    input reset,
    input enable,
    output [3:0] q);

    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0;
        end else if (enable) begin
            if (q == 4'd9) begin
                q <= 4'b0;
            end else begin
                q <= q + 1;
            end
        end
    end
endmodule
module decade_cnt (
    input clk,
    input reset,
    input enable,
    output [3:0] q);


    always @(posedge clk) begin
        if (reset) begin
            q <= 4'b0;
        end else if (enable) begin
            if (q == 4'd9) begin
                q <= 4'b0;
            end else begin
                q <= q + 1;
            end
        end
    end
endmodule