data/full_repos/permissive/421048855/Verilog Language/Procedures/Always nolathes.v
1: b'%Error: Cannot find file containing module: Language/Procedures,data/full_repos/permissive/421048855\n        ... Looked in:\n             data/full_repos/permissive/421048855/Verilog/Language/Procedures,data/full_repos/permissive/421048855\n             data/full_repos/permissive/421048855/Verilog/Language/Procedures,data/full_repos/permissive/421048855.v\n             data/full_repos/permissive/421048855/Verilog/Language/Procedures,data/full_repos/permissive/421048855.sv\n             Language/Procedures,data/full_repos/permissive/421048855\n             Language/Procedures,data/full_repos/permissive/421048855.v\n             Language/Procedures,data/full_repos/permissive/421048855.sv\n             obj_dir/Language/Procedures,data/full_repos/permissive/421048855\n             obj_dir/Language/Procedures,data/full_repos/permissive/421048855.v\n             obj_dir/Language/Procedures,data/full_repos/permissive/421048855.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Verilog\n%Error: Cannot find file containing module: Language/Procedures/Always\n%Error: Cannot find file containing module: nolathes.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always @(*) begin
        case(scancode)
            16'he06b: {left, down, right, up} = 4'b1000;
            16'he072: {left, down, right, up} = 4'b0100;
            16'he074: {left, down, right, up} = 4'b0010;
            16'he075: {left, down, right, up} = 4'b0001;
            default: {left, down, right, up} = 4'b0000;   
        endcase
    end
endmodule
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  );
 
    always @(*) begin
        case(scancode)
            16'he06b: {left, down, right, up} = 4'b1000;
            16'he072: {left, down, right, up} = 4'b0100;
            16'he074: {left, down, right, up} = 4'b0010;
            16'he075: {left, down, right, up} = 4'b0001;
            default: {left, down, right, up} = 4'b0000;   
        endcase
    end
endmodule