data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/tx_chain.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/tx_chain.v:38: Cannot find file containing module: 'cic_interp'\n   cic_interp cic_interp_i\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cic_interp\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cic_interp.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/cic_interp.sv\n             cic_interp\n             cic_interp.v\n             cic_interp.sv\n             obj_dir/cic_interp\n             obj_dir/cic_interp.v\n             obj_dir/cic_interp.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/tx_chain.v:43: Cannot find file containing module: 'cic_interp'\n   cic_interp cic_interp_q\n   ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module tx_chain
  (input clock,
   input reset,
   input enable,
   input wire [7:0] interp_rate,
   input sample_strobe,
   input interpolator_strobe,
   input wire [31:0] freq,
   input wire [15:0] i_in,
   input wire [15:0] q_in,
   output wire [15:0] i_out,
   output wire [15:0] q_out
   );

   wire [15:0] bb_i, bb_q;

   cic_interp cic_interp_i
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
       .signal_in(i_in),.signal_out(bb_i) );

   cic_interp cic_interp_q
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
       .signal_in(q_in),.signal_out(bb_q) );
   
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
   assign      i_out = bb_i;
   assign      q_out = bb_q;
`else
   wire [31:0] phase;

   phase_acc phase_acc_tx
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq),.phase(phase) );
   
   cordic tx_cordic_0
     ( .clock(clock),.reset(reset),.enable(sample_strobe), 
       .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
       .xo(i_out),.yo(q_out),.zo() );
`endif

endmodule
module tx_chain
  (input clock,
   input reset,
   input enable,
   input wire [7:0] interp_rate,
   input sample_strobe,
   input interpolator_strobe,
   input wire [31:0] freq,
   input wire [15:0] i_in,
   input wire [15:0] q_in,
   output wire [15:0] i_out,
   output wire [15:0] q_out
   );


   wire [15:0] bb_i, bb_q;

   cic_interp cic_interp_i
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
       .signal_in(i_in),.signal_out(bb_i) );

   cic_interp cic_interp_q
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
       .signal_in(q_in),.signal_out(bb_q) );
   
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
   assign      i_out = bb_i;
   assign      q_out = bb_q;
`else
   wire [31:0] phase;

   phase_acc phase_acc_tx
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq),.phase(phase) );
   
   cordic tx_cordic_0
     ( .clock(clock),.reset(reset),.enable(sample_strobe), 
       .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
       .xo(i_out),.yo(q_out),.zo() );
`endif

endmodule