data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, fn_sw_4_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L2/fn_sw_4/fn_sw_4_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    always #10 absel<=absel+1;\n           ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fn_sw_4_tb; 
    reg[3:0] absel; 
    wire y;
    fn_sw_4 fn_sw_4(
        .a(absel[0]), 
        .b(absel[1]), 
        .sel(absel[3:2]), 
        .y(y)
        );

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, fn_sw_4_tb);
    end

    initial begin
            absel<=0;
        #200 $finish;
    end

    always #10 absel<=absel+1;

endmodule
module fn_sw_4_tb;
 
    reg[3:0] absel; 
    wire y;
    fn_sw_4 fn_sw_4(
        .a(absel[0]), 
        .b(absel[1]), 
        .sel(absel[3:2]), 
        .y(y)
        );

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, fn_sw_4_tb);
    end

    initial begin
            absel<=0;
        #200 $finish;
    end

    always #10 absel<=absel+1;

endmodule