data/full_repos/permissive/433111929/float_alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/433111929/float_alu_tb.v:42: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n  a1<=repeat(2) @(posedge clk) a;\n      ^~~~~~\n%Error: data/full_repos/permissive/433111929/float_alu_tb.v:43: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n  b1<=repeat(2) @(posedge clk)b;\n      ^~~~~~\n%Error: data/full_repos/permissive/433111929/float_alu_tb.v:44: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n  op1<=repeat(2) @(posedge clk)op;\n       ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #50; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/433111929/float_alu_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Error: Exiting due to 3 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module falu_tb;


	reg [31:0] a,b,a1,b1;
	reg clk,f;
	reg [2:0] op,op1;

	wire [31:0] out;


	float_alu uut (
		.a(a),.b(b),.clk(clk),.op(op), 
		.out(out)
	);
	always #5 clk=~clk;
	
	always@(posedge clk) begin
		a1<=repeat(2) @(posedge clk) a;
		b1<=repeat(2) @(posedge clk)b;
		op1<=repeat(2) @(posedge clk)op;
	end
	
	always@(posedge clk)
		$display("op=%b,a=%b %b %b,b=%b %b %b,c=%b %b %b",op1,a1[31],a1[30:23],a1[22:0],b1[31],b1[30:23],b1[22:0],out[31],out[30:23],out[22:0]);
	
	initial begin

		clk=0;f=0;
		
		b=32'b0_10000000_00000000000000000000000;
		
		op=0;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;	
		
		op=1;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=2;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=3;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=4;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=5;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=6;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=7;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		$finish;
	end
      
endmodule
module falu_tb;



	reg [31:0] a,b,a1,b1;
	reg clk,f;
	reg [2:0] op,op1;

	wire [31:0] out;


	float_alu uut (
		.a(a),.b(b),.clk(clk),.op(op), 
		.out(out)
	);
	always #5 clk=~clk;
	
	always@(posedge clk) begin
		a1<=repeat(2) @(posedge clk) a;
		b1<=repeat(2) @(posedge clk)b;
		op1<=repeat(2) @(posedge clk)op;
	end
	
	always@(posedge clk)
		$display("op=%b,a=%b %b %b,b=%b %b %b,c=%b %b %b",op1,a1[31],a1[30:23],a1[22:0],b1[31],b1[30:23],b1[22:0],out[31],out[30:23],out[22:0]);
	
	initial begin

		clk=0;f=0;
		
		b=32'b0_10000000_00000000000000000000000;
		
		op=0;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;	
		
		op=1;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=2;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=3;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=4;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=5;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=6;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		op=7;
		a=32'b0_10000001_11010000000000000000000;
		#10;
		a=32'b0_01111011_11010000000000000000000;
		#10;
		a=32'b0_01111111_11010000000000000000000;
		#50;
		
		$finish;
	end
      
endmodule