data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:61: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'rbm_0_data\'\nmodule rbm_0_data(CLK, rbm_0_data_CE0, rbm_0_data_A0, rbm_0_data_D0, rbm_0_data_WE0, rbm_0_data_WEM0, rbm_0_data_CE2, rbm_0_data_A2, rbm_0_data_Q2, rbm_0_data_CE1, rbm_0_data_A1, rbm_0_data_Q1);\n       ^~~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_edges\'\nmodule rbm_0_edges(CLK, rbm_0_edges_CE0, rbm_0_edges_A0, rbm_0_edges_D0, rbm_0_edges_WE0, rbm_0_edges_WEM0, rbm_0_edges_CE2, rbm_0_edges_A2, rbm_0_edges_Q2, rbm_0_edges_CE1, rbm_0_edges_A1, rbm_0_edges_Q1);\n       ^~~~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_hidden_unit\'\nmodule rbm_0_hidden_unit(CLK, rbm_0_hidden_unit_CE1, rbm_0_hidden_unit_A1, rbm_0_hidden_unit_D1, rbm_0_hidden_unit_WE1, rbm_0_hidden_unit_WEM1, rbm_0_hidden_unit_CE3, rbm_0_hidden_unit_A3, rbm_0_hidden_unit_Q3, rbm_0_hidden_unit_CE0, rbm_0_hidden_unit_A0, rbm_0_hidden_unit_D0, rbm_0_hidden_unit_WE0, rbm_0_hidden_unit_WEM0, rbm_0_hidden_unit_CE2, rbm_0_hidden_unit_A2, rbm_0_hidden_unit_Q2);\n       ^~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_mt\'\nmodule rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1);\n       ^~~~~~~~\n                                                                                            : ... Top module \'rbm_0_neg\'\nmodule rbm_0_neg(CLK, rbm_0_neg_CE0, rbm_0_neg_A0, rbm_0_neg_D0, rbm_0_neg_WE0, rbm_0_neg_WEM0, rbm_0_neg_CE1, rbm_0_neg_A1, rbm_0_neg_Q1);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_pos\'\nmodule rbm_0_pos(CLK, rbm_0_pos_CE0, rbm_0_pos_A0, rbm_0_pos_D0, rbm_0_pos_WE0, rbm_0_pos_WEM0, rbm_0_pos_CE1, rbm_0_pos_A1, rbm_0_pos_Q1);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_predict_result\'\nmodule rbm_0_predict_result(CLK, rbm_0_predict_result_CE1, rbm_0_predict_result_A1, rbm_0_predict_result_Q1, rbm_0_predict_result_CE0, rbm_0_predict_result_A0, rbm_0_predict_result_D0, rbm_0_predict_result_WE0, rbm_0_predict_result_WEM0);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'rbm_0_visibleEnergies\'\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:1083: Cannot find file containing module: \'SRAM2S_128X16\'\n  SRAM2S_128X16 mem_0(.CLK(CLK),\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437995305/verilog,data/full_repos/permissive/437995305/SRAM2S_128X16\n             data/full_repos/permissive/437995305/verilog,data/full_repos/permissive/437995305/SRAM2S_128X16.v\n             data/full_repos/permissive/437995305/verilog,data/full_repos/permissive/437995305/SRAM2S_128X16.sv\n             SRAM2S_128X16\n             SRAM2S_128X16.v\n             SRAM2S_128X16.sv\n             obj_dir/SRAM2S_128X16\n             obj_dir/SRAM2S_128X16.v\n             obj_dir/SRAM2S_128X16.sv\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:1097: Cannot find file containing module: \'SRAM2S_128X16\'\n  SRAM2S_128X16 mem_1(.CLK(CLK),\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:842: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_0(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:856: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_1(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:870: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_2(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:884: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_3(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:898: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_4(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:912: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_5(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:926: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_6(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:523: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_0(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:537: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_1(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:551: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_2(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:565: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_3(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:579: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_4(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:593: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_5(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:607: Cannot find file containing module: \'SRAM2S_8192X16\'\n  SRAM2S_8192X16 mem_6(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:288: Cannot find file containing module: \'SRAM2S_1024X32\'\n  SRAM2S_1024X32 mem_0(.CLK(CLK),\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:213: Cannot find file containing module: \'SRAM2S_128X16\'\n  SRAM2S_128X16 mem_0(.CLK(CLK),\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:227: Cannot find file containing module: \'SRAM2S_128X16\'\n  SRAM2S_128X16 mem_1(.CLK(CLK),\n  ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/437995305/verilog/mem_rbm_0_cmos32soi_rtl.v:971: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bxxxxxxxx\' generates 8 bits.\n                                                                                          : ... In instance rbm_0_predict_result\n      rbm_0_predict_result_Q1 <= 8\'hxx;\n                              ^~\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1);
  input CLK;

  input rbm_0_mt_CE0;
  input [9:0] rbm_0_mt_A0;
  input [31:0] rbm_0_mt_D0;
  input rbm_0_mt_WE0;
  input [31:0] rbm_0_mt_WEM0;

  input rbm_0_mt_CE1;
  input [9:0] rbm_0_mt_A1;
  output [31:0] rbm_0_mt_Q1;


  wire mem_0_CE0;
  wire [9:0] mem_0_A0;
  wire [31:0] mem_0_D0;
  wire mem_0_WE0;
  wire [31:0] mem_0_WEM0;
  wire [31:0] mem_0_Q0;
  wire mem_0_CE1;
  wire [9:0] mem_0_A1;
  wire [31:0] mem_0_D1;
  wire mem_0_WE1;
  wire [31:0] mem_0_WEM1;
  wire [31:0] mem_0_Q1;




  assign mem_0_CE0 = rbm_0_mt_CE0 ? 1'b1 : (1'b0);
  assign mem_0_A0 = rbm_0_mt_CE0 ? rbm_0_mt_A0[9:0] : ({10{1'b0}});
  assign mem_0_D0 = rbm_0_mt_CE0 ? rbm_0_mt_D0[31:0] : ({32{1'b0}});
  assign mem_0_WE0 = rbm_0_mt_CE0 ? rbm_0_mt_WE0 : (1'b0);
  assign mem_0_WEM0 = rbm_0_mt_CE0 ? rbm_0_mt_WEM0[31:0] : ({32{1'b0}});
  assign mem_0_CE1 = rbm_0_mt_CE1 ? 1'b1 : (1'b0);
  assign mem_0_A1 = rbm_0_mt_CE1 ? rbm_0_mt_A1[9:0] : ({10{1'b0}});
  assign mem_0_D1 = {32{1'b0}};
  assign mem_0_WE1 = 1'b0;
  assign mem_0_WEM1 = {32{1'b0}};


  assign rbm_0_mt_Q1 = mem_0_Q1;


  SRAM2S_1024X32 mem_0(.CLK(CLK),
      .CE0(mem_0_CE0),
      .A0(mem_0_A0),
      .D0(mem_0_D0),
      .WE0(mem_0_WE0),
      .WEM0(mem_0_WEM0),
      .Q0(mem_0_Q0),
      .CE1(mem_0_CE1),
      .A1(mem_0_A1),
      .D1(mem_0_D1),
      .WE1(mem_0_WE1),
      .WEM1(mem_0_WEM1),
      .Q1(mem_0_Q1));

endmodule
module rbm_0_mt(CLK, rbm_0_mt_CE0, rbm_0_mt_A0, rbm_0_mt_D0, rbm_0_mt_WE0, rbm_0_mt_WEM0, rbm_0_mt_CE1, rbm_0_mt_A1, rbm_0_mt_Q1);

  input CLK;

  input rbm_0_mt_CE0;
  input [9:0] rbm_0_mt_A0;
  input [31:0] rbm_0_mt_D0;
  input rbm_0_mt_WE0;
  input [31:0] rbm_0_mt_WEM0;

  input rbm_0_mt_CE1;
  input [9:0] rbm_0_mt_A1;
  output [31:0] rbm_0_mt_Q1;


  wire mem_0_CE0;
  wire [9:0] mem_0_A0;
  wire [31:0] mem_0_D0;
  wire mem_0_WE0;
  wire [31:0] mem_0_WEM0;
  wire [31:0] mem_0_Q0;
  wire mem_0_CE1;
  wire [9:0] mem_0_A1;
  wire [31:0] mem_0_D1;
  wire mem_0_WE1;
  wire [31:0] mem_0_WEM1;
  wire [31:0] mem_0_Q1;




  assign mem_0_CE0 = rbm_0_mt_CE0 ? 1'b1 : (1'b0);
  assign mem_0_A0 = rbm_0_mt_CE0 ? rbm_0_mt_A0[9:0] : ({10{1'b0}});
  assign mem_0_D0 = rbm_0_mt_CE0 ? rbm_0_mt_D0[31:0] : ({32{1'b0}});
  assign mem_0_WE0 = rbm_0_mt_CE0 ? rbm_0_mt_WE0 : (1'b0);
  assign mem_0_WEM0 = rbm_0_mt_CE0 ? rbm_0_mt_WEM0[31:0] : ({32{1'b0}});
  assign mem_0_CE1 = rbm_0_mt_CE1 ? 1'b1 : (1'b0);
  assign mem_0_A1 = rbm_0_mt_CE1 ? rbm_0_mt_A1[9:0] : ({10{1'b0}});
  assign mem_0_D1 = {32{1'b0}};
  assign mem_0_WE1 = 1'b0;
  assign mem_0_WEM1 = {32{1'b0}};


  assign rbm_0_mt_Q1 = mem_0_Q1;


  SRAM2S_1024X32 mem_0(.CLK(CLK),
      .CE0(mem_0_CE0),
      .A0(mem_0_A0),
      .D0(mem_0_D0),
      .WE0(mem_0_WE0),
      .WEM0(mem_0_WEM0),
      .Q0(mem_0_Q0),
      .CE1(mem_0_CE1),
      .A1(mem_0_A1),
      .D1(mem_0_D1),
      .WE1(mem_0_WE1),
      .WEM1(mem_0_WEM1),
      .Q1(mem_0_Q1));

endmodule