data/full_repos/permissive/48602886/src/device/sci/uart.v
1: b"%Error: data/full_repos/permissive/48602886/src/device/sci/uart.v:43: Cannot find file containing module: 'uart_sync_fifo'\n uart_sync_fifo #(8, 16, 4) TX_FIFO(\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48602886/src/device/sci,data/full_repos/permissive/48602886/uart_sync_fifo\n             data/full_repos/permissive/48602886/src/device/sci,data/full_repos/permissive/48602886/uart_sync_fifo.v\n             data/full_repos/permissive/48602886/src/device/sci,data/full_repos/permissive/48602886/uart_sync_fifo.sv\n             uart_sync_fifo\n             uart_sync_fifo.v\n             uart_sync_fifo.sv\n             obj_dir/uart_sync_fifo\n             obj_dir/uart_sync_fifo.v\n             obj_dir/uart_sync_fifo.sv\n%Error: data/full_repos/permissive/48602886/src/device/sci/uart.v:61: Cannot find file containing module: 'uart_sync_fifo'\n uart_sync_fifo #(8, 16, 4) RX_FIFO(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48602886/src/device/sci/uart.v:82: Cannot find file containing module: 'uart_transmitter'\n uart_transmitter #(20'd108) UART_TRANSMITTER(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48602886/src/device/sci/uart.v:99: Cannot find file containing module: 'uart_receiver'\n uart_receiver #(20'd108) UART_RECEIVER(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module uart(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iTX_EN,
		input wire iTX_REQ,
		output wire oTX_BUSY,
		input wire [7:0] iTX_DATA,
		output wire [3:0] oTX_BUFF_CNT,
		output wire oTX_TRANSMIT,

		input wire iRX_EN,
		input wire iRX_REQ,
		output wire oRX_EMPTY,
		output wire [7:0] oRX_DATA,
		output wire [3:0] oRX_BUFF_CNT,
		output wire oRX_RECEIVE,

		output wire oIRQ_VALID,

		output wire oUART_TXD,
		input wire iUART_RXD
	);
	
	

	wire transmitter_tx_enable;
	wire transmitter_tx_busy;
	wire [7:0] transmitter_tx_data;
	
	wire receiver_rx_enable;
	wire receiver_rx_busy;
	wire [7:0] receiver_rx_data;


	uart_sync_fifo #(8, 16, 4) TX_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(oTX_BUFF_CNT),

		.iWR_EN(iTX_EN && iTX_REQ),
		.iWR_DATA(iTX_DATA),
		.oWR_FULL(oTX_BUSY),

		.iRD_EN(!transmitter_tx_enable && !transmitter_tx_busy),
		.oRD_DATA(transmitter_tx_data),
		.oRD_EMPTY(transmitter_tx_enable)
	);

	

	uart_sync_fifo #(8, 16, 4) RX_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(oRX_BUFF_CNT),

		.iWR_EN(receiver_rx_enable && !receiver_rx_busy),
		.iWR_DATA(receiver_rx_data),
		.oWR_FULL(receiver_rx_busy),

		.iRD_EN(iRX_EN && iRX_REQ),
		.oRD_DATA(oRX_DATA),
		.oRD_EMPTY(oRX_EMPTY)
	);
	
	


	uart_transmitter #(20'd108) UART_TRANSMITTER(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.iTX_REQ(!transmitter_tx_enable && !transmitter_tx_busy),
		.oTX_BUSY(transmitter_tx_busy),
		.iTX_DATA(transmitter_tx_data),

		.oUART_TXD(oUART_TXD)
	);
	


	uart_receiver #(20'd108) UART_RECEIVER(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.oRX_VALID(receiver_rx_enable),
		.oRX_DATA(receiver_rx_data),

		.iUART_RXD(iUART_RXD)
	);
	

	assign oTX_TRANSMIT = !transmitter_tx_enable && !transmitter_tx_busy;
	assign oRX_RECEIVE = receiver_rx_enable;
	
	assign oIRQ_VALID = 1'h0;

	
endmodule
module uart(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iTX_EN,
		input wire iTX_REQ,
		output wire oTX_BUSY,
		input wire [7:0] iTX_DATA,
		output wire [3:0] oTX_BUFF_CNT,
		output wire oTX_TRANSMIT,

		input wire iRX_EN,
		input wire iRX_REQ,
		output wire oRX_EMPTY,
		output wire [7:0] oRX_DATA,
		output wire [3:0] oRX_BUFF_CNT,
		output wire oRX_RECEIVE,

		output wire oIRQ_VALID,

		output wire oUART_TXD,
		input wire iUART_RXD
	);

	
	

	wire transmitter_tx_enable;
	wire transmitter_tx_busy;
	wire [7:0] transmitter_tx_data;
	
	wire receiver_rx_enable;
	wire receiver_rx_busy;
	wire [7:0] receiver_rx_data;


	uart_sync_fifo #(8, 16, 4) TX_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(oTX_BUFF_CNT),

		.iWR_EN(iTX_EN && iTX_REQ),
		.iWR_DATA(iTX_DATA),
		.oWR_FULL(oTX_BUSY),

		.iRD_EN(!transmitter_tx_enable && !transmitter_tx_busy),
		.oRD_DATA(transmitter_tx_data),
		.oRD_EMPTY(transmitter_tx_enable)
	);

	

	uart_sync_fifo #(8, 16, 4) RX_FIFO(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iREMOVE(iRESET_SYNC),
		.oCOUNT(oRX_BUFF_CNT),

		.iWR_EN(receiver_rx_enable && !receiver_rx_busy),
		.iWR_DATA(receiver_rx_data),
		.oWR_FULL(receiver_rx_busy),

		.iRD_EN(iRX_EN && iRX_REQ),
		.oRD_DATA(oRX_DATA),
		.oRD_EMPTY(oRX_EMPTY)
	);
	
	


	uart_transmitter #(20'd108) UART_TRANSMITTER(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.iTX_REQ(!transmitter_tx_enable && !transmitter_tx_busy),
		.oTX_BUSY(transmitter_tx_busy),
		.iTX_DATA(transmitter_tx_data),

		.oUART_TXD(oUART_TXD)
	);
	


	uart_receiver #(20'd108) UART_RECEIVER(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),

		.oRX_VALID(receiver_rx_enable),
		.oRX_DATA(receiver_rx_data),

		.iUART_RXD(iUART_RXD)
	);
	

	assign oTX_TRANSMIT = !transmitter_tx_enable && !transmitter_tx_busy;
	assign oRX_RECEIVE = receiver_rx_enable;
	
	assign oIRQ_VALID = 1'h0;

	
endmodule