data/full_repos/permissive/484316383/rtl/bram.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/484316383/rtl/bram.sv:19: Little bit endian vector: MSB < LSB of bit range: -17:0\n    input   wire    [width_a-25:0]  data_b,     \n                    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/484316383/rtl/bram.sv:20: Little bit endian vector: MSB < LSB of bit range: -17:0\n    output  reg     [width_a-25:0]  q_b,        \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/bram.sv:54: Bit extraction of array[1023:0] requires 10 bit index, not 8 bits.\n                                                                   : ... In instance bram\n    q_a      <= mem[address_a];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/bram.sv:57: Bit extraction of array[1023:0] requires 10 bit index, not 8 bits.\n                                                                   : ... In instance bram\n        mem[address_a] <= data_a;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/bram.sv:63: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                   : ... In instance bram\n    q_b      <= mem[address_b];\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/bram.sv:66: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_b\' generates 18 bits.\n                                                                   : ... In instance bram\n        mem[address_b] <= data_b;\n                       ^~\n%Error: Exiting due to 6 warning(s)\n'
module bram #(
    parameter width_a = 8,
    parameter widthad_a = 10,
    parameter init_file= ""
) (

    input   wire                    clock_a,
    input   wire                    wren_a,
    input   wire    [widthad_a-3:0] address_a,
    input   wire    [width_a-1:0]   data_a,
    output  reg     [width_a-1:0]   q_a,
     

    input   wire                    clock_b,
    input   wire                    wren_b,
    input   wire    [widthad_a-1:0] address_b,
    input   wire    [width_a-25:0]  data_b,
    output  reg     [width_a-25:0]  q_b,

    input wire byteena_a,
    input wire byteena_b



);

    initial begin
        $display("Loading rom.");
        $display(init_file);
        if (init_file>0)
        	$readmemh(init_file, mem);
    end

 

reg [width_a-1:0] mem [(2**widthad_a)-1:0];

always @(posedge clock_a) begin
    q_a      <= mem[address_a];
    if(wren_a) begin
        q_a      <= data_a;
        mem[address_a] <= data_a;
    end
end
 

always @(posedge clock_b) begin
    q_b      <= mem[address_b];
    if(wren_b) begin
        q_b      <= data_b;
        mem[address_b] <= data_b;
    end
end
 
endmodule
module bram #(
    parameter width_a = 8,
    parameter widthad_a = 10,
    parameter init_file= ""
) (

    input   wire                    clock_a,
    input   wire                    wren_a,
    input   wire    [widthad_a-3:0] address_a,
    input   wire    [width_a-1:0]   data_a,
    output  reg     [width_a-1:0]   q_a,
     

    input   wire                    clock_b,
    input   wire                    wren_b,
    input   wire    [widthad_a-1:0] address_b,
    input   wire    [width_a-25:0]  data_b,
    output  reg     [width_a-25:0]  q_b,

    input wire byteena_a,
    input wire byteena_b



);


    initial begin
        $display("Loading rom.");
        $display(init_file);
        if (init_file>0)
        	$readmemh(init_file, mem);
    end

 

reg [width_a-1:0] mem [(2**widthad_a)-1:0];

always @(posedge clock_a) begin
    q_a      <= mem[address_a];
    if(wren_a) begin
        q_a      <= data_a;
        mem[address_a] <= data_a;
    end
end
 

always @(posedge clock_b) begin
    q_b      <= mem[address_b];
    if(wren_b) begin
        q_b      <= data_b;
        mem[address_b] <= data_b;
    end
end
 
endmodule