data/full_repos/permissive/519458744/BLI201V32I/rtl/core/bli201v32i_core_exu_bru.v
data/verilator_xmls/88d61ad6-0979-4fc2-8d4e-50776433c46d.xml
module bru (
  input  [31:0] bru_i_a, 
  input  [31:0] bru_i_b,
  input         bru_i_br_un,
  output        bru_o_br_eq, 
  output        bru_o_br_lt
);

  wire signed [31:0] a_signed, b_signed;
  
  assign a_signed = bru_i_a;
  assign b_signed = bru_i_b;
  
  assign bru_o_br_eq = (bru_i_a === bru_i_b);
  assign bru_o_br_lt = bru_i_br_un ? (bru_i_a < bru_i_b) : (a_signed < b_signed);
  
endmodule
module bru (
  input  [31:0] bru_i_a, 
  input  [31:0] bru_i_b,
  input         bru_i_br_un,
  output        bru_o_br_eq, 
  output        bru_o_br_lt
);


  wire signed [31:0] a_signed, b_signed;
  
  assign a_signed = bru_i_a;
  assign b_signed = bru_i_b;
  
  assign bru_o_br_eq = (bru_i_a === bru_i_b);
  assign bru_o_br_lt = bru_i_br_un ? (bru_i_a < bru_i_b) : (a_signed < b_signed);
  
endmodule