data/full_repos/permissive/506186384/project-files/lab6/Predict_PC.v
data/verilator_xmls/20581be5-c29c-4bbc-b475-43efb41a2549.xml
module Predict_PC(
    input Clk,
    input reset,
    input [31:0] Instr,
    input [31:0] IF_CurPC,
    input [1:0] TwoBitPredictor,
    output [31:0] Predict_Next_PC,
    output IF_Predict
    );
    
    reg [31:0] pre_next_pc;
    reg if_predict;
    
    always @(IF_CurPC or Instr or TwoBitPredictor) begin
        
        
        case(Instr[31:26])
            6'b000010: begin
                pre_next_pc = {IF_CurPC[31:28],Instr[25:0],2'b00};
                if_predict = 0;
            end
            6'b000011: begin
                pre_next_pc = {IF_CurPC[31:28],Instr[25:0],2'b00};
                if_predict = 0;
            end
            6'b000100: begin
                if(TwoBitPredictor > 1) begin
                    pre_next_pc = IF_CurPC + 4 + {{14{Instr[15]}},Instr[15:0],2'b00};
                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                end
                if_predict = 1;
            end
            6'b000101: begin
                if(TwoBitPredictor > 1) begin
                    pre_next_pc = IF_CurPC + 4 + {{14{Instr[15]}},Instr[15:0],2'b00};
                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                end
                if_predict = 1;
            end
            6'b000000: begin
                if(Instr[5:0] == 6'b001000) begin
                    pre_next_pc = IF_CurPC + 4;
                    if_predict = 0;

                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                    if_predict = 0;
                end
            end
            default: begin
                pre_next_pc = IF_CurPC + 4;
                if_predict = 0;
            end
        endcase
    end
    
    assign Predict_Next_PC = pre_next_pc;
    assign IF_Predict = if_predict;
    always @(posedge reset) begin
        
    end
    
endmodule
module Predict_PC(
    input Clk,
    input reset,
    input [31:0] Instr,
    input [31:0] IF_CurPC,
    input [1:0] TwoBitPredictor,
    output [31:0] Predict_Next_PC,
    output IF_Predict
    );

    
    reg [31:0] pre_next_pc;
    reg if_predict;
    
    always @(IF_CurPC or Instr or TwoBitPredictor) begin
        
        
        case(Instr[31:26])
            6'b000010: begin
                pre_next_pc = {IF_CurPC[31:28],Instr[25:0],2'b00};
                if_predict = 0;
            end
            6'b000011: begin
                pre_next_pc = {IF_CurPC[31:28],Instr[25:0],2'b00};
                if_predict = 0;
            end
            6'b000100: begin
                if(TwoBitPredictor > 1) begin
                    pre_next_pc = IF_CurPC + 4 + {{14{Instr[15]}},Instr[15:0],2'b00};
                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                end
                if_predict = 1;
            end
            6'b000101: begin
                if(TwoBitPredictor > 1) begin
                    pre_next_pc = IF_CurPC + 4 + {{14{Instr[15]}},Instr[15:0],2'b00};
                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                end
                if_predict = 1;
            end
            6'b000000: begin
                if(Instr[5:0] == 6'b001000) begin
                    pre_next_pc = IF_CurPC + 4;
                    if_predict = 0;

                end
                else begin
                    pre_next_pc = IF_CurPC + 4;
                    if_predict = 0;
                end
            end
            default: begin
                pre_next_pc = IF_CurPC + 4;
                if_predict = 0;
            end
        endcase
    end
    
    assign Predict_Next_PC = pre_next_pc;
    assign IF_Predict = if_predict;
    always @(posedge reset) begin
        
    end
    
endmodule