data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Shift Registers/Mt2015_lfsr/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers/Mt2015_lfsr,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/Mt2015_lfsr/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire [2:0] SW,
    input wire [1:0] KEY,
    output wire [2:0] LEDR
);

  reg [2:0] q = 3'b0;
  assign LEDR = q;

  always @(posedge KEY[0]) begin
    if (KEY[1]) q <= SW;
    else begin
      q[2] <= q[2] ^ q[1];
      q[1] <= q[0];
      q[0] <= q[2];
    end
  end

endmodule
module top_module (
    input wire [2:0] SW,
    input wire [1:0] KEY,
    output wire [2:0] LEDR
);


  reg [2:0] q = 3'b0;
  assign LEDR = q;

  always @(posedge KEY[0]) begin
    if (KEY[1]) q <= SW;
    else begin
      q[2] <= q[2] ^ q[1];
      q[1] <= q[0];
      q[0] <= q[2];
    end
  end

endmodule