data/full_repos/permissive/523038000/lab14/clkdiv.v
data/verilator_xmls/ac3427ff-d476-4b13-b62d-b9c7f70b16b9.xml
module clkdiv(

input wire mclk,
input wire clr,
output wire clk25
    );

reg [24:0] q;

always @ (posedge mclk or posedge clr)
	begin
		if (clr == 1)
			q <= 0;
		else
			q <= q + 1;
	end

assign clk25 = q[0];

endmodule
module clkdiv(

input wire mclk,
input wire clr,
output wire clk25
    );


reg [24:0] q;

always @ (posedge mclk or posedge clr)
	begin
		if (clr == 1)
			q <= 0;
		else
			q <= q + 1;
	end

assign clk25 = q[0];

endmodule