data/full_repos/permissive/459277146/complete.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:262: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:270: Unsupported: Ignoring delay on this delayed statement.\n  #(10)  \n  ^\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd"); $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:275: Unsupported or unknown PLI call: $dumpvars\n  $dumpfile("dump.vcd"); $dumpvars;\n                         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:368: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD / 2) clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/459277146/complete.v:371: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%d:\\t%d /%d =%d (r =) (V=) (DBZ=)",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:378: Unsupported: Ignoring delay on this delayed statement.\n        #100    x = 4\'b0000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:381: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:383: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:386: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:388: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:391: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:393: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:396: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:398: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0001;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:401: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:403: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:406: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/complete.v:410: Unsupported: Ignoring delay on this delayed statement.\n        #50     $finish;\n        ^\n%Error: data/full_repos/permissive/459277146/complete.v:413: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("div.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/complete.v:414: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars; \n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divider_tb();

    parameter CLK_PERIOD = 10;
    parameter DWIDTH = 8;

    logic clk;
    logic start;



    logic [DWIDTH-1:0] x;
    logic [DWIDTH-1:0] y;
    logic [(DWIDTH<<1)-1:0] dout;


    divider #(.DWIDTH(DWIDTH)) divider_inst (.*);

    always #(CLK_PERIOD / 2) clk = ~clk;

    initial begin
        $monitor("\t%d:\t%d /%d =%d (r =) (V=) (DBZ=)",
            $time, x, y, dout);
    end

    initial begin
        clk = 1;

        #100    x = 4'b0000;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0010;
                y = 4'b0000;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0111;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1111;
                y = 4'b0101;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0001;
                y = 4'b0001;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1000;
                y = 4'b1001;
                start = 1;
        #10     start = 0;



        #50     $finish;
    end
   initial begin
  $dumpfile("div.vcd"); 
  $dumpvars; 
 end
endmodule
module divider_tb();


    parameter CLK_PERIOD = 10;
    parameter DWIDTH = 8;

    logic clk;
    logic start;



    logic [DWIDTH-1:0] x;
    logic [DWIDTH-1:0] y;
    logic [(DWIDTH<<1)-1:0] dout;


    divider #(.DWIDTH(DWIDTH)) divider_inst (.*);

    always #(CLK_PERIOD / 2) clk = ~clk;

    initial begin
        $monitor("\t%d:\t%d /%d =%d (r =) (V=) (DBZ=)",
            $time, x, y, dout);
    end

    initial begin
        clk = 1;

        #100    x = 4'b0000;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0010;
                y = 4'b0000;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0111;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1111;
                y = 4'b0101;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0001;
                y = 4'b0001;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1000;
                y = 4'b1001;
                start = 1;
        #10     start = 0;



        #50     $finish;
    end
   initial begin
  $dumpfile("div.vcd"); 
  $dumpvars; 
 end
endmodule