data/full_repos/permissive/528252229/mem.v
1: b'%Error: data/full_repos/permissive/528252229/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/mem.v:8: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]        wd_i,        \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus]        wd_i,        \n                       ^\n%Error: data/full_repos/permissive/528252229/mem.v:9: Define or directive not defined: \'`WriteBus\'\n input wire[`WriteBus]           wreg_i,     \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:10: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    wdata_i,     \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:12: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]   aluop_i,  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    mem_addr_i,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    reg2_i,   \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:15: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]  pc_i,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:18: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           mem_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:21: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]      wd_o,           \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:22: Define or directive not defined: \'`WriteBus\'\n output reg[`WriteBus]           wreg_o,        \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:23: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    wdata_o,       \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    mem_addr_o,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus]    mem_data_o,  \n ^~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:28: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    mem_data_o,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:32: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire[`InstAddrBus]  pc_o,        \n ^~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:32: Define or directive not defined: \'`InstAddrBus\'\n output wire[`InstAddrBus]  pc_o,        \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:33: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]   aluop_o,     \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:39: Define or directive not defined: \'`ALU_OP_LW\'\n assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:39: Define or directive not defined: \'`ALU_OP_LB\'\n assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;\n                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:39: Define or directive not defined: \'`ALU_OP_LH\'\n assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;\n                                                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:39: Define or directive not defined: \'`Stop\'\n assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;\n                                                                                                     ^~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:39: Define or directive not defined: \'`NoStop\'\n assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;\n                                                                                                             ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:42: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:43: Define or directive not defined: \'`ZeroRegAddr\'\n            wd_o <= `ZeroRegAddr;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:44: Define or directive not defined: \'`WriteDisable\'\n            wreg_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:45: Define or directive not defined: \'`ZeroWord\'\n            wdata_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:46: Define or directive not defined: \'`ALU_OP_NOP\'\n            aluop_o <= `ALU_OP_NOP;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:47: Define or directive not defined: \'`ZeroWord\'\n   mem_addr_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:48: Define or directive not defined: \'`WriteDisable\'\n   mem_we_o <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:49: Define or directive not defined: \'`ZeroWord\'\n   mem_data_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:50: Define or directive not defined: \'`WriteDisable\'\n   mem_ce_o <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:56: Define or directive not defined: \'`ZeroWord\'\n   mem_addr_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:58: Define or directive not defined: \'`ZeroWord\'\n   mem_data_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:59: Define or directive not defined: \'`ReadDisable\'\n   mem_ce_o <= `ReadDisable;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:61: Define or directive not defined: \'`ALU_OP_LW\'\n    `ALU_OP_LW : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:65: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:67: Define or directive not defined: \'`ALU_OP_LB\'\n    `ALU_OP_LB : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:69: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:88: Define or directive not defined: \'`ZeroWord\'\n       wdata_o <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:92: Define or directive not defined: \'`ALU_OP_LH\'\n    `ALU_OP_LH : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:94: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:105: Define or directive not defined: \'`ZeroWord\'\n       wdata_o <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:109: Define or directive not defined: \'`ALU_OP_SW\'\n    `ALU_OP_SW : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:113: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:115: Define or directive not defined: \'`ALU_OP_SB\'\n    `ALU_OP_SB : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:117: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:134: Define or directive not defined: \'`ALU_OP_SH\'\n    `ALU_OP_SH : begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem.v:136: Define or directive not defined: \'`ReadEnable\'\n     mem_ce_o <= `ReadEnable;\n                 ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(

	input wire						rst,
	

	input wire[`RegAddrBus]       	wd_i,
	input wire[`WriteBus]           wreg_i,
	input wire[`RegBus]				wdata_i,
	
	input wire[`AluOpBus]			aluop_i,
	input wire[`RegBus]				mem_addr_i,
	input wire[`RegBus]				reg2_i,
	input wire[`InstAddrBus]		pc_i,
	

	input wire[`RegBus]          	mem_data_i,
	

	output reg[`RegAddrBus]     	wd_o,
	output reg[`WriteBus]           wreg_o,
	output reg[`RegBus]				wdata_o,


	output reg[`RegBus]				mem_addr_o,
	output reg[3:0]					mem_we_o,
	output reg[`RegBus]				mem_data_o,
	output reg						mem_ce_o,
	
	
	output wire[`InstAddrBus]		pc_o,
	output reg[`AluOpBus]			aluop_o,
	output wire 					stallreq

);
    
	assign pc_o = pc_i;
	assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;

    always @(*) begin
        if(rst == `RstDisable) begin
            wd_o <= `ZeroRegAddr;
            wreg_o <= `WriteDisable;
            wdata_o <= `ZeroWord;
            aluop_o <= `ALU_OP_NOP;
			mem_addr_o <= `ZeroWord;
			mem_we_o <= `WriteDisable;
			mem_data_o <= `ZeroWord;
			mem_ce_o <= `WriteDisable;
        end else begin
            wd_o <= wd_i;
            wreg_o <= wreg_i;
            wdata_o <= wdata_i;
            aluop_o <= aluop_i;
			mem_addr_o <= `ZeroWord;
			mem_we_o <= 4'b1111;
			mem_data_o <= `ZeroWord;
			mem_ce_o <= `ReadDisable;
			case(aluop_i)
				`ALU_OP_LW : begin
					mem_addr_o <= mem_addr_i;
					mem_we_o <= 4'b0000;
					wdata_o <= mem_data_i;
					mem_ce_o <= `ReadEnable;
				end
				`ALU_OP_LB : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					case(mem_addr_i[1:0]) 
						2'b00 : begin
							wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
							mem_we_o <= 4'b1000;
						end
						2'b01 : begin
							wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
							mem_we_o <= 4'b0100;
						end
						2'b10 : begin
							wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
							mem_we_o <= 4'b0010;
						end
						2'b11 : begin
							wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
							mem_we_o <= 4'b0001;
						end
						default : begin
							wdata_o <= `ZeroWord;
						end
					endcase
				end
				`ALU_OP_LH : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					case(mem_addr_i[1:0]) 
						2'b00 : begin
							wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:16]};
							mem_we_o <= 4'b1100;
						end
						2'b10 : begin
							wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:0]};
							mem_we_o <= 4'b0011;
						end
						default : begin
							wdata_o <= `ZeroWord;
						end
					endcase
				end
				`ALU_OP_SW : begin
					mem_addr_o <= mem_addr_i;

					mem_data_o <= reg2_i;
					mem_ce_o <= `ReadEnable;
				end
				`ALU_OP_SB : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					mem_data_o <= {reg2_i[7:0], reg2_i[7:0], reg2_i[7:0], reg2_i[7:0]};
					case(mem_addr_i[1:0])
						2'b00 : begin
							mem_we_o <= 4'b1000;
						end
						2'b01 : begin
							mem_we_o <= 4'b0100;
						end
						2'b10 : begin
							mem_we_o <= 4'b0010;
						end
						2'b11 : begin
							mem_we_o <= 4'b0001;
						end
					endcase
				end
				`ALU_OP_SH : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					mem_data_o <= {reg2_i[15:0], reg2_i[15:0]};
					case(mem_addr_i[1:0])
						2'b00 : begin
							mem_we_o <= 4'b1100;
						end
						2'b10 : begin
							mem_we_o <= 4'b0011;
						end
					endcase
				end
				default : begin

				end
			endcase
        end
        
    end
    
endmodule
module mem(

	input wire						rst,
	

	input wire[`RegAddrBus]       	wd_i,
	input wire[`WriteBus]           wreg_i,
	input wire[`RegBus]				wdata_i,
	
	input wire[`AluOpBus]			aluop_i,
	input wire[`RegBus]				mem_addr_i,
	input wire[`RegBus]				reg2_i,
	input wire[`InstAddrBus]		pc_i,
	

	input wire[`RegBus]          	mem_data_i,
	

	output reg[`RegAddrBus]     	wd_o,
	output reg[`WriteBus]           wreg_o,
	output reg[`RegBus]				wdata_o,


	output reg[`RegBus]				mem_addr_o,
	output reg[3:0]					mem_we_o,
	output reg[`RegBus]				mem_data_o,
	output reg						mem_ce_o,
	
	
	output wire[`InstAddrBus]		pc_o,
	output reg[`AluOpBus]			aluop_o,
	output wire 					stallreq

);

    
	assign pc_o = pc_i;
	assign stallreq = ((aluop_i == `ALU_OP_LW) || (aluop_i == `ALU_OP_LB) || (aluop_i == `ALU_OP_LH)) ? `Stop : `NoStop;

    always @(*) begin
        if(rst == `RstDisable) begin
            wd_o <= `ZeroRegAddr;
            wreg_o <= `WriteDisable;
            wdata_o <= `ZeroWord;
            aluop_o <= `ALU_OP_NOP;
			mem_addr_o <= `ZeroWord;
			mem_we_o <= `WriteDisable;
			mem_data_o <= `ZeroWord;
			mem_ce_o <= `WriteDisable;
        end else begin
            wd_o <= wd_i;
            wreg_o <= wreg_i;
            wdata_o <= wdata_i;
            aluop_o <= aluop_i;
			mem_addr_o <= `ZeroWord;
			mem_we_o <= 4'b1111;
			mem_data_o <= `ZeroWord;
			mem_ce_o <= `ReadDisable;
			case(aluop_i)
				`ALU_OP_LW : begin
					mem_addr_o <= mem_addr_i;
					mem_we_o <= 4'b0000;
					wdata_o <= mem_data_i;
					mem_ce_o <= `ReadEnable;
				end
				`ALU_OP_LB : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					case(mem_addr_i[1:0]) 
						2'b00 : begin
							wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
							mem_we_o <= 4'b1000;
						end
						2'b01 : begin
							wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
							mem_we_o <= 4'b0100;
						end
						2'b10 : begin
							wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
							mem_we_o <= 4'b0010;
						end
						2'b11 : begin
							wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
							mem_we_o <= 4'b0001;
						end
						default : begin
							wdata_o <= `ZeroWord;
						end
					endcase
				end
				`ALU_OP_LH : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					case(mem_addr_i[1:0]) 
						2'b00 : begin
							wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:16]};
							mem_we_o <= 4'b1100;
						end
						2'b10 : begin
							wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:0]};
							mem_we_o <= 4'b0011;
						end
						default : begin
							wdata_o <= `ZeroWord;
						end
					endcase
				end
				`ALU_OP_SW : begin
					mem_addr_o <= mem_addr_i;

					mem_data_o <= reg2_i;
					mem_ce_o <= `ReadEnable;
				end
				`ALU_OP_SB : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					mem_data_o <= {reg2_i[7:0], reg2_i[7:0], reg2_i[7:0], reg2_i[7:0]};
					case(mem_addr_i[1:0])
						2'b00 : begin
							mem_we_o <= 4'b1000;
						end
						2'b01 : begin
							mem_we_o <= 4'b0100;
						end
						2'b10 : begin
							mem_we_o <= 4'b0010;
						end
						2'b11 : begin
							mem_we_o <= 4'b0001;
						end
					endcase
				end
				`ALU_OP_SH : begin
					mem_addr_o <= mem_addr_i;
					mem_ce_o <= `ReadEnable;
					mem_data_o <= {reg2_i[15:0], reg2_i[15:0]};
					case(mem_addr_i[1:0])
						2'b00 : begin
							mem_we_o <= 4'b1100;
						end
						2'b10 : begin
							mem_we_o <= 4'b0011;
						end
					endcase
				end
				default : begin

				end
			endcase
        end
        
    end
    
endmodule