data/full_repos/permissive/46981098/data_mem/datamem.v
data/verilator_xmls/226c369a-6bb6-47f0-8387-bc2d7537e3cc.xml
module datamem (
  input clk,
  output [31:0] dataOut,
  input [31:0] address, dataIn,
  input writemode, readmode

);

  reg [31:0] Mem [2499:250];

  always @(*) begin
    if(writemode)
      Mem[address >> 2] = dataIn;
  end
     assign dataOut = readmode ? Mem[address >> 2] : 0;
endmodule
module datamem (
  input clk,
  output [31:0] dataOut,
  input [31:0] address, dataIn,
  input writemode, readmode

);


  reg [31:0] Mem [2499:250];

  always @(*) begin
    if(writemode)
      Mem[address >> 2] = dataIn;
  end
     assign dataOut = readmode ? Mem[address >> 2] : 0;
endmodule