data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v
data/verilator_xmls/03a04a92-3ab2-4543-8841-a3d4c3ff27f3.xml
module mux_21 (a,b,sel,y);
  	  	input a, b;
  	  	output y;
  	  	input sel;
  	  	wire y;
  	  	 
  	  	assign y = (sel) ? b : a;
  	  	 
endmodule
module mux_21 (a,b,sel,y);

  	  	input a, b;
  	  	output y;
  	  	input sel;
  	  	wire y;
  	  	 
  	  	assign y = (sel) ? b : a;
  	  	 
endmodule