data/full_repos/permissive/463204869/units/mem/source/rtl/verilog/xpm_sdp_distram.v
1: b"%Error: data/full_repos/permissive/463204869/units/mem/source/rtl/verilog/xpm_sdp_distram.v:35: Cannot find file containing module: 'xpm_memory_sdpram'\n        xpm_memory_sdpram #(\n        ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_sdpram\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_sdpram.v\n             data/full_repos/permissive/463204869/units/mem/source/rtl/verilog,data/full_repos/permissive/463204869/xpm_memory_sdpram.sv\n             xpm_memory_sdpram\n             xpm_memory_sdpram.v\n             xpm_memory_sdpram.sv\n             obj_dir/xpm_memory_sdpram\n             obj_dir/xpm_memory_sdpram.v\n             obj_dir/xpm_memory_sdpram.sv\n%Error: Exiting due to 1 error(s)\n"
module xpm_sdp_distram #(
    parameter MEM_DATAWIDTH = 128,
    parameter MEM_ADDRWIDTH = 14
)
(
    input   wire                              clk,
    input   wire                              reset,

    input   wire                              ena,
    input   wire          [MEM_DATAWIDTH-1:0] wea,
    input   wire          [MEM_ADDRWIDTH-1:0] addra,
    input   wire          [MEM_DATAWIDTH-1:0] dina,

    input   wire                              enb,
    input   wire          [MEM_ADDRWIDTH-1:0] addrb,
    output  wire          [MEM_DATAWIDTH-1:0] doutb
);

    genvar i_gen;
    generate


    for (i_gen=0; i_gen<MEM_DATAWIDTH; i_gen=i_gen+1) begin: xpm_bit

        wire doutb_bit;
        wire dina_bit = dina[i_gen];
        wire wea_bit = wea[i_gen];

        assign doutb[i_gen] = doutb_bit;




        xpm_memory_sdpram #(
            .ADDR_WIDTH_A(MEM_ADDRWIDTH),
            .ADDR_WIDTH_B(MEM_ADDRWIDTH),
            .AUTO_SLEEP_TIME(0),
            .BYTE_WRITE_WIDTH_A(1),
            .CASCADE_HEIGHT(0),
            .CLOCKING_MODE("common_clock"),
            .ECC_MODE("no_ecc"),
            .MEMORY_INIT_FILE("none"),
            .MEMORY_INIT_PARAM("0"),
            .MEMORY_OPTIMIZATION("true"),
            .MEMORY_PRIMITIVE("distributed"),
            .MEMORY_SIZE(1<<MEM_ADDRWIDTH),
            .MESSAGE_CONTROL(0),
            .READ_DATA_WIDTH_B(1),
            .READ_LATENCY_B(1),
            .READ_RESET_VALUE_B("0"),
            .RST_MODE_A("SYNC"),
            .RST_MODE_B("SYNC"),
            .SIM_ASSERT_CHK(0),
            .USE_EMBEDDED_CONSTRAINT(0),
            .USE_MEM_INIT(0),
            .WAKEUP_TIME("disable_sleep"),
            .WRITE_DATA_WIDTH_A(1),
            .WRITE_MODE_B("read_first")
        )
        xpm_memory_sdpram_inst (
            .dbiterrb(),

            .doutb(doutb_bit),
            .sbiterrb(),

            .addra(addra),
            .addrb(addrb),
            .clka(clk),

            .clkb(clk),

            .dina(dina_bit),
            .ena(ena),

            .enb(enb),

            .injectdbiterra(1'b0),

            .injectsbiterra(1'b0),

            .regceb(1'b1),
            .rstb(reset),

            .sleep(1'b0),
            .wea(wea_bit)





        );

    end
    endgenerate


endmodule
module xpm_sdp_distram #(
    parameter MEM_DATAWIDTH = 128,
    parameter MEM_ADDRWIDTH = 14
)
(
    input   wire                              clk,
    input   wire                              reset,

    input   wire                              ena,
    input   wire          [MEM_DATAWIDTH-1:0] wea,
    input   wire          [MEM_ADDRWIDTH-1:0] addra,
    input   wire          [MEM_DATAWIDTH-1:0] dina,

    input   wire                              enb,
    input   wire          [MEM_ADDRWIDTH-1:0] addrb,
    output  wire          [MEM_DATAWIDTH-1:0] doutb
);


    genvar i_gen;
    generate


    for (i_gen=0; i_gen<MEM_DATAWIDTH; i_gen=i_gen+1) begin: xpm_bit

        wire doutb_bit;
        wire dina_bit = dina[i_gen];
        wire wea_bit = wea[i_gen];

        assign doutb[i_gen] = doutb_bit;




        xpm_memory_sdpram #(
            .ADDR_WIDTH_A(MEM_ADDRWIDTH),
            .ADDR_WIDTH_B(MEM_ADDRWIDTH),
            .AUTO_SLEEP_TIME(0),
            .BYTE_WRITE_WIDTH_A(1),
            .CASCADE_HEIGHT(0),
            .CLOCKING_MODE("common_clock"),
            .ECC_MODE("no_ecc"),
            .MEMORY_INIT_FILE("none"),
            .MEMORY_INIT_PARAM("0"),
            .MEMORY_OPTIMIZATION("true"),
            .MEMORY_PRIMITIVE("distributed"),
            .MEMORY_SIZE(1<<MEM_ADDRWIDTH),
            .MESSAGE_CONTROL(0),
            .READ_DATA_WIDTH_B(1),
            .READ_LATENCY_B(1),
            .READ_RESET_VALUE_B("0"),
            .RST_MODE_A("SYNC"),
            .RST_MODE_B("SYNC"),
            .SIM_ASSERT_CHK(0),
            .USE_EMBEDDED_CONSTRAINT(0),
            .USE_MEM_INIT(0),
            .WAKEUP_TIME("disable_sleep"),
            .WRITE_DATA_WIDTH_A(1),
            .WRITE_MODE_B("read_first")
        )
        xpm_memory_sdpram_inst (
            .dbiterrb(),

            .doutb(doutb_bit),
            .sbiterrb(),

            .addra(addra),
            .addrb(addrb),
            .clka(clk),

            .clkb(clk),

            .dina(dina_bit),
            .ena(ena),

            .enb(enb),

            .injectdbiterra(1'b0),

            .injectsbiterra(1'b0),

            .regceb(1'b1),
            .rstb(reset),

            .sleep(1'b0),
            .wea(wea_bit)





        );

    end
    endgenerate


endmodule