data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/DFF.v
data/verilator_xmls/1ea89d67-fc0d-4061-ad2f-0fa98fb499ad.xml
module DFF #(parameter WI = 5, WF = 11)
    (
    input CLK,EN,RST,
    input [(WI+WF)-1:0] D, 
    output reg [(WI+WF)-1:0] Q
    );
    

    always @(posedge CLK) begin
        if(EN) begin
            if (D != 0) begin
                Q <= D;
            end else begin
                Q <= 0;
            end
        end
    end
    always @(RST) begin
        if (RST) begin
            Q <= 0;
        end
    end
endmodule
module DFF #(parameter WI = 5, WF = 11)
    (
    input CLK,EN,RST,
    input [(WI+WF)-1:0] D, 
    output reg [(WI+WF)-1:0] Q
    );

    

    always @(posedge CLK) begin
        if(EN) begin
            if (D != 0) begin
                Q <= D;
            end else begin
                Q <= 0;
            end
        end
    end
    always @(RST) begin
        if (RST) begin
            Q <= 0;
        end
    end
endmodule