data/full_repos/permissive/505761772/code/InOutStuff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/InOutStuff.v:30: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'SPI\'\nmodule SPI( input       CLK,\n       ^~~\n                                                                            : ... Top module \'DAC\'\nmodule DAC( input               SCK,\n       ^~~\n                                                                            : ... Top module \'GAIN\'\nmodule GAIN(input       SCK,\n       ^~~~\n                                                                            : ... Top module \'ADC\'\nmodule ADC( input       SCK,\n       ^~~\n                                                                            : ... Top module \'SERIAL_TX\'\nmodule SERIAL_TX (input [7:0]  DATA,\n       ^~~~~~~~~\n                                                                            : ... Top module \'SERIAL_RX\'\nmodule SERIAL_RX (input         CLK,\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'gain\' generates 4 bits.\n                                                                         : ... In instance GAIN\nreg [7:0] data = gain;\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/InOutStuff.v:58: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'AorB\' generates 1 bits.\n                                                                         : ... In instance DAC\n      dataReg <= {8\'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};\n                        ^\n%Error: Exiting due to 3 warning(s)\n'
module DAC( input               SCK,
            output reg          MOSI,
            output reg          CS,
            output              CLR,
            input               EN,
            input signed [11:0] A,
            input signed [11:0] B,
            output reg          AorB);

reg [19:0]  dataReg;
reg [5:0]   stateReg;
reg [4:0]   cnt;

initial begin
  CS = 1;
  AorB = 0;
  stateReg = 6'h19;
end

always @(negedge SCK) begin
  if(stateReg == 6'h19)
    if(!EN && !AorB)
      CS <= 1;
    else begin
      CS <= 0;
      AorB <= !AorB;
      stateReg <= 6'h00;

      dataReg <= {8'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};
  end else begin
    stateReg <= stateReg + 1;
    if(stateReg == 6'h18)
      CS <= 1;
    else if(stateReg < 6'h14) begin
      MOSI <= dataReg[19];
      dataReg <= dataReg << 1;
    end else if(stateReg < 6'h18)
      MOSI <= 0;
  end
end

assign CLR = 1;

endmodule
module DAC( input               SCK,
            output reg          MOSI,
            output reg          CS,
            output              CLR,
            input               EN,
            input signed [11:0] A,
            input signed [11:0] B,
            output reg          AorB);


reg [19:0]  dataReg;
reg [5:0]   stateReg;
reg [4:0]   cnt;

initial begin
  CS = 1;
  AorB = 0;
  stateReg = 6'h19;
end

always @(negedge SCK) begin
  if(stateReg == 6'h19)
    if(!EN && !AorB)
      CS <= 1;
    else begin
      CS <= 0;
      AorB <= !AorB;
      stateReg <= 6'h00;

      dataReg <= {8'h30 + AorB, (AorB ? {!A[11],A[10:0]} : {!B[11],B[10:0]} )};
  end else begin
    stateReg <= stateReg + 1;
    if(stateReg == 6'h18)
      CS <= 1;
    else if(stateReg < 6'h14) begin
      MOSI <= dataReg[19];
      dataReg <= dataReg << 1;
    end else if(stateReg < 6'h18)
      MOSI <= 0;
  end
end

assign CLR = 1;

endmodule