data/full_repos/permissive/503973366/RTL/AXI/myip_v1_0_S00_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/AXI/myip_v1_0_S00_AXI.v:371: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n       axi_araddr  <= 32\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503973366/RTL/AXI/myip_v1_0_S00_AXI.v:499: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'mem0_addr_cnt\' generates 7 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n   if(mem0_addr_cnt == MEM0_DEPTH-1)\n                    ^~\n%Error: Exiting due to 2 warning(s)\n'
module myip_v1_0_S00_AXI #
	(

		parameter integer MEM0_DEPTH = 98,
		parameter integer MEM0_ADDR_WIDTH = 7,
		parameter integer MEM0_DATA_WIDTH = 128,




		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 5
	)
	(

		input wire [MEM0_DATA_WIDTH-1:0] mem0_q1,
		output wire	[MEM0_ADDR_WIDTH-1:0] mem0_addr1,
		output wire	mem0_ce1,
		output wire	mem0_we1,
		output wire	[MEM0_DATA_WIDTH-1:0] mem0_d1,




		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;
	reg		axi_rvalid_d;
	reg 	axi_rvalid_selected;
	





	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;



	assign S_AXI_RVALID = axi_rvalid_selected;






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      aw_en <= 1'b1;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin




	          axi_awready <= 1'b1;
	          aw_en <= 1'b0;
	        end
	        else if (S_AXI_BREADY && axi_bvalid)
	            begin
	              aw_en <= 1'b1;
	              axi_awready <= 1'b0;
	            end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;





	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          3'h0:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h1:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h2:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h3:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end 





























	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;





	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    


	reg slv_reg_rden_d;
	always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
	    if(!S_AXI_ARESETN) begin
			axi_rvalid_d	<= 'd0;
			slv_reg_rden_d	<= 'd0;
	    end else begin
			axi_rvalid_d	<= axi_rvalid;
			slv_reg_rden_d	<= slv_reg_rden;
	    end 
	end






	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        3'h0   : reg_data_out <= slv_reg0;
	        3'h1   : reg_data_out <= slv_reg1;
	        3'h2   : reg_data_out <= slv_reg2;
	        3'h3   : reg_data_out <= slv_reg3;
	        3'h4   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH*3)+:C_S_AXI_DATA_WIDTH];
	        3'h5   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH*2)+:C_S_AXI_DATA_WIDTH];
	        3'h6   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH)  +:C_S_AXI_DATA_WIDTH];
	        3'h7   : reg_data_out <= mem0_q1[ 0                    +:C_S_AXI_DATA_WIDTH];
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    


	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_0_addr = 'h0;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_1_addr = 'h4;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_2_addr = 'h8;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_3_addr = 'hc;

	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_4_addr = 'h10;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_5_addr = 'h14;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_6_addr = 'h18;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_7_addr = 'h1c;


	wire mem0_data_write_hit = slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_3_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]);
	reg mem0_data_write_hit_delay;
	always@(posedge S_AXI_ACLK) begin
		mem0_data_write_hit_delay <= mem0_data_write_hit;
	end

	wire mem0_data_read_hit = slv_reg_rden;
	wire mem0_data_read_hit_cnt = 	slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_7_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]);									
	
	reg [MEM0_ADDR_WIDTH-1:0] mem0_addr_cnt;
	always@(posedge S_AXI_ACLK) begin
		if ( S_AXI_ARESETN == 1'b0 ) begin
			mem0_addr_cnt <= 0;
		end else if(mem0_data_write_hit_delay || mem0_data_read_hit_cnt) begin
			if(mem0_addr_cnt == MEM0_DEPTH-1)
				mem0_addr_cnt <= 0;
			else
				mem0_addr_cnt <= mem0_addr_cnt + 1;
		end
	end
	
	always@(*) begin
		if(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_4_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB])
			axi_rvalid_selected = axi_rvalid_d;
		else
			axi_rvalid_selected = axi_rvalid;
	end


	assign mem0_addr1 	= mem0_addr_cnt[MEM0_ADDR_WIDTH-1:0]; 
	assign mem0_ce1		= mem0_data_write_hit_delay || mem0_data_read_hit;
	assign mem0_we1		= mem0_data_write_hit_delay;
	assign mem0_d1		= {slv_reg0, slv_reg1, slv_reg2, slv_reg3};


	endmodule
module myip_v1_0_S00_AXI #
	(

		parameter integer MEM0_DEPTH = 98,
		parameter integer MEM0_ADDR_WIDTH = 7,
		parameter integer MEM0_DATA_WIDTH = 128,




		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 5
	)
	(

		input wire [MEM0_DATA_WIDTH-1:0] mem0_q1,
		output wire	[MEM0_ADDR_WIDTH-1:0] mem0_addr1,
		output wire	mem0_ce1,
		output wire	mem0_we1,
		output wire	[MEM0_DATA_WIDTH-1:0] mem0_d1,




		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);



	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;
	reg		axi_rvalid_d;
	reg 	axi_rvalid_selected;
	





	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;



	assign S_AXI_RVALID = axi_rvalid_selected;






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      aw_en <= 1'b1;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin




	          axi_awready <= 1'b1;
	          aw_en <= 1'b0;
	        end
	        else if (S_AXI_BREADY && axi_bvalid)
	            begin
	              aw_en <= 1'b1;
	              axi_awready <= 1'b0;
	            end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;





	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          3'h0:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h1:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h2:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h3:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end 





























	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;





	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    


	reg slv_reg_rden_d;
	always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
	    if(!S_AXI_ARESETN) begin
			axi_rvalid_d	<= 'd0;
			slv_reg_rden_d	<= 'd0;
	    end else begin
			axi_rvalid_d	<= axi_rvalid;
			slv_reg_rden_d	<= slv_reg_rden;
	    end 
	end






	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        3'h0   : reg_data_out <= slv_reg0;
	        3'h1   : reg_data_out <= slv_reg1;
	        3'h2   : reg_data_out <= slv_reg2;
	        3'h3   : reg_data_out <= slv_reg3;
	        3'h4   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH*3)+:C_S_AXI_DATA_WIDTH];
	        3'h5   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH*2)+:C_S_AXI_DATA_WIDTH];
	        3'h6   : reg_data_out <= mem0_q1[(C_S_AXI_DATA_WIDTH)  +:C_S_AXI_DATA_WIDTH];
	        3'h7   : reg_data_out <= mem0_q1[ 0                    +:C_S_AXI_DATA_WIDTH];
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    


	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_0_addr = 'h0;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_1_addr = 'h4;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_2_addr = 'h8;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_3_addr = 'hc;

	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_4_addr = 'h10;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_5_addr = 'h14;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_6_addr = 'h18;
	wire [C_S_AXI_ADDR_WIDTH-1:0]   slv_reg_7_addr = 'h1c;


	wire mem0_data_write_hit = slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_3_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]);
	reg mem0_data_write_hit_delay;
	always@(posedge S_AXI_ACLK) begin
		mem0_data_write_hit_delay <= mem0_data_write_hit;
	end

	wire mem0_data_read_hit = slv_reg_rden;
	wire mem0_data_read_hit_cnt = 	slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_7_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]);									
	
	reg [MEM0_ADDR_WIDTH-1:0] mem0_addr_cnt;
	always@(posedge S_AXI_ACLK) begin
		if ( S_AXI_ARESETN == 1'b0 ) begin
			mem0_addr_cnt <= 0;
		end else if(mem0_data_write_hit_delay || mem0_data_read_hit_cnt) begin
			if(mem0_addr_cnt == MEM0_DEPTH-1)
				mem0_addr_cnt <= 0;
			else
				mem0_addr_cnt <= mem0_addr_cnt + 1;
		end
	end
	
	always@(*) begin
		if(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == slv_reg_4_addr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB])
			axi_rvalid_selected = axi_rvalid_d;
		else
			axi_rvalid_selected = axi_rvalid;
	end


	assign mem0_addr1 	= mem0_addr_cnt[MEM0_ADDR_WIDTH-1:0]; 
	assign mem0_ce1		= mem0_data_write_hit_delay || mem0_data_read_hit;
	assign mem0_we1		= mem0_data_write_hit_delay;
	assign mem0_d1		= {slv_reg0, slv_reg1, slv_reg2, slv_reg3};


	endmodule