data/full_repos/permissive/498662723/Circuits/Combinational Logic/Multiplexers/mux2to1v.v
1: b'%Error: Cannot find file containing module: Logic/Multiplexers,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Circuits/Combinational/Logic/Multiplexers,data/full_repos/permissive/498662723.sv\n             Logic/Multiplexers,data/full_repos/permissive/498662723\n             Logic/Multiplexers,data/full_repos/permissive/498662723.v\n             Logic/Multiplexers,data/full_repos/permissive/498662723.sv\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/498662723\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/498662723.v\n             obj_dir/Logic/Multiplexers,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Combinational\n%Error: Cannot find file containing module: Logic/Multiplexers/mux2to1v.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    
    assign out = (sel == 1'b1) ? b : a;

endmodule
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

    
    assign out = (sel == 1'b1) ? b : a;

endmodule